From e68d0ffcffeb66e1f81b12fafed8c5ac74a0050b Mon Sep 17 00:00:00 2001 From: Waldemar Brodkorb Date: Thu, 1 Dec 2011 16:41:29 +0100 Subject: refresh linux kernels --- target/linux/patches/2.6.36/ar7.patch | 90 - target/linux/patches/2.6.36/ar71xx.patch | 18666 ---- target/linux/patches/2.6.36/aufs2.patch | 33532 ------- target/linux/patches/2.6.36/brcm.patch | 169 - .../linux/patches/2.6.36/bsd-compatibility.patch | 2512 - target/linux/patches/2.6.36/cc-abstract.patch | 14 - target/linux/patches/2.6.36/cris.patch | 5736 -- target/linux/patches/2.6.36/cygwin-compat.patch | 14 - target/linux/patches/2.6.36/drm-kconfig.patch | 34 - target/linux/patches/2.6.36/exmap.patch | 11 - target/linux/patches/2.6.36/foxg20.patch | 522 - target/linux/patches/2.6.36/freebsd-compat.patch | 11 - target/linux/patches/2.6.36/gemalto.patch | 11 - target/linux/patches/2.6.36/lemote.patch | 4267 - target/linux/patches/2.6.36/mtd-root.patch | 62 - target/linux/patches/2.6.36/ocf-20100325.patch | 87545 ---------------- target/linux/patches/2.6.36/rb532.patch | 18 - target/linux/patches/2.6.36/startup.patch | 20 - target/linux/patches/2.6.36/uuid.patch | 261 - target/linux/patches/2.6.36/yaffs2.patch | 16912 ---- target/linux/patches/2.6.36/zboot-brcm-reloc.patch | 297 - target/linux/patches/2.6.37/ar7.patch | 90 - target/linux/patches/2.6.37/ar71xx.patch | 18667 ---- target/linux/patches/2.6.37/atheros.patch | 6332 -- target/linux/patches/2.6.37/aufs2.patch | 28523 ------ target/linux/patches/2.6.37/brcm.patch | 396 - .../linux/patches/2.6.37/bsd-compatibility.patch | 2512 - target/linux/patches/2.6.37/cc-abstract.patch | 14 - target/linux/patches/2.6.37/cris.patch | 5745 -- target/linux/patches/2.6.37/cygwin-compat.patch | 14 - target/linux/patches/2.6.37/drm-kconfig.patch | 36 - target/linux/patches/2.6.37/exmap.patch | 11 - target/linux/patches/2.6.37/foxg20.patch | 520 - target/linux/patches/2.6.37/freebsd-compat.patch | 11 - target/linux/patches/2.6.37/gemalto.patch | 11 - target/linux/patches/2.6.37/lemote.patch | 4271 - target/linux/patches/2.6.37/mtd-rootfs.patch | 25 - target/linux/patches/2.6.37/ocf-20100325.patch | 87545 ---------------- target/linux/patches/2.6.37/rb532.patch | 18 - target/linux/patches/2.6.37/startup.patch | 20 - target/linux/patches/2.6.37/usb-defaults-off.patch | 32 - target/linux/patches/2.6.37/uuid.patch | 261 - .../patches/2.6.37/vga-cons-default-off.patch | 12 - target/linux/patches/2.6.37/yaffs2.patch | 16912 ---- target/linux/patches/2.6.37/zlib-inflate.patch | 12 - target/linux/patches/2.6.39/arm-statcmd.patch | 12 - .../linux/patches/2.6.39/bsd-compatibility.patch | 2512 - target/linux/patches/2.6.39/cris-etrax.patch | 12 - .../linux/patches/2.6.39/cris-thread-macro.patch | 12 - target/linux/patches/2.6.39/cris.patch | 5739 -- target/linux/patches/2.6.39/defaults.patch | 26 - target/linux/patches/2.6.39/fon2100.patch | 6279 -- target/linux/patches/2.6.39/gemalto.patch | 11 - target/linux/patches/2.6.39/mips-malta.patch | 135 - target/linux/patches/2.6.39/mmc-host.patch | 36 - target/linux/patches/2.6.39/non-static.patch | 33 - target/linux/patches/2.6.39/ocf-20100325.patch | 90176 ----------------- target/linux/patches/2.6.39/rb4xx.patch | 25253 ----- target/linux/patches/2.6.39/sparc-include.patch | 11 - target/linux/patches/2.6.39/startup.patch | 20 - target/linux/patches/2.6.39/usb-defaults-off.patch | 32 - target/linux/patches/2.6.39/uuid.patch | 255 - .../patches/2.6.39/vga-cons-default-off.patch | 12 - target/linux/patches/2.6.39/wlan-cf.patch | 11 - target/linux/patches/2.6.39/x86-build.patch | 11 - target/linux/patches/2.6.39/zlib-inflate.patch | 12 - target/linux/patches/3.0.4/bsd-compatibility.patch | 2512 - target/linux/patches/3.0.4/cris-etrax.patch | 12 - target/linux/patches/3.0.4/defaults.patch | 22 - target/linux/patches/3.0.4/fon2100.patch | 6279 -- target/linux/patches/3.0.4/gemalto.patch | 11 - target/linux/patches/3.0.4/mips-malta.patch | 135 - target/linux/patches/3.0.4/mmc-host.patch | 36 - target/linux/patches/3.0.4/non-static.patch | 33 - target/linux/patches/3.0.4/ocf-20110720.patch | 99170 ------------------- target/linux/patches/3.0.4/sparc-include.patch | 11 - target/linux/patches/3.0.4/startup.patch | 20 - target/linux/patches/3.0.4/usb-defaults-off.patch | 32 - target/linux/patches/3.0.4/uuid.patch | 255 - .../linux/patches/3.0.4/vga-cons-default-off.patch | 12 - target/linux/patches/3.0.4/wlan-cf.patch | 11 - target/linux/patches/3.0.4/x86-build.patch | 11 - target/linux/patches/3.0.4/zlib-inflate.patch | 12 - target/linux/patches/3.0.8/bsd-compatibility.patch | 2512 - target/linux/patches/3.0.8/cris-etrax.patch | 12 - target/linux/patches/3.0.8/defaults.patch | 22 - target/linux/patches/3.0.8/fon2100.patch | 6279 -- target/linux/patches/3.0.8/gemalto.patch | 11 - target/linux/patches/3.0.8/mips-malta.patch | 135 - target/linux/patches/3.0.8/mmc-host.patch | 36 - target/linux/patches/3.0.8/non-static.patch | 33 - target/linux/patches/3.0.8/ocf-20110720.patch | 99170 ------------------- target/linux/patches/3.0.8/sparc-include.patch | 11 - target/linux/patches/3.0.8/startup.patch | 20 - target/linux/patches/3.0.8/usb-defaults-off.patch | 32 - target/linux/patches/3.0.8/uuid.patch | 255 - .../linux/patches/3.0.8/vga-cons-default-off.patch | 12 - target/linux/patches/3.0.8/wlan-cf.patch | 11 - target/linux/patches/3.0.8/x86-build.patch | 11 - target/linux/patches/3.0.8/zlib-inflate.patch | 12 - target/linux/patches/3.0.9/bsd-compatibility.patch | 2512 + target/linux/patches/3.0.9/cris-etrax.patch | 12 + target/linux/patches/3.0.9/defaults.patch | 22 + target/linux/patches/3.0.9/fon2100.patch | 6279 ++ target/linux/patches/3.0.9/gemalto.patch | 11 + target/linux/patches/3.0.9/mips-malta.patch | 135 + target/linux/patches/3.0.9/mmc-host.patch | 36 + target/linux/patches/3.0.9/non-static.patch | 33 + target/linux/patches/3.0.9/ocf-20110720.patch | 99170 +++++++++++++++++++ target/linux/patches/3.0.9/sparc-include.patch | 11 + target/linux/patches/3.0.9/startup.patch | 20 + target/linux/patches/3.0.9/usb-defaults-off.patch | 32 + target/linux/patches/3.0.9/uuid.patch | 255 + .../linux/patches/3.0.9/vga-cons-default-off.patch | 12 + target/linux/patches/3.0.9/wlan-cf.patch | 11 + target/linux/patches/3.0.9/x86-build.patch | 11 + target/linux/patches/3.0.9/zlib-inflate.patch | 12 + target/linux/patches/3.1.4/bsd-compatibility.patch | 2512 + target/linux/patches/3.1.4/cris-etrax.patch | 12 + target/linux/patches/3.1.4/defaults.patch | 22 + target/linux/patches/3.1.4/fon2100.patch | 6279 ++ target/linux/patches/3.1.4/gemalto.patch | 11 + target/linux/patches/3.1.4/mmc-host.patch | 36 + target/linux/patches/3.1.4/non-static.patch | 33 + target/linux/patches/3.1.4/ocf-20110720.patch | 96377 ++++++++++++++++++ target/linux/patches/3.1.4/sparc-include.patch | 11 + target/linux/patches/3.1.4/startup.patch | 20 + target/linux/patches/3.1.4/usb-defaults-off.patch | 32 + target/linux/patches/3.1.4/uuid.patch | 255 + .../linux/patches/3.1.4/vga-cons-default-off.patch | 12 + target/linux/patches/3.1.4/wlan-cf.patch | 11 + target/linux/patches/3.1.4/x86-build.patch | 11 + target/linux/patches/3.1.4/zlib-inflate.patch | 12 + 133 files changed, 214220 insertions(+), 690442 deletions(-) delete mode 100644 target/linux/patches/2.6.36/ar7.patch delete mode 100644 target/linux/patches/2.6.36/ar71xx.patch delete mode 100644 target/linux/patches/2.6.36/aufs2.patch delete mode 100644 target/linux/patches/2.6.36/brcm.patch delete mode 100644 target/linux/patches/2.6.36/bsd-compatibility.patch delete mode 100644 target/linux/patches/2.6.36/cc-abstract.patch delete mode 100644 target/linux/patches/2.6.36/cris.patch delete mode 100644 target/linux/patches/2.6.36/cygwin-compat.patch delete mode 100644 target/linux/patches/2.6.36/drm-kconfig.patch delete mode 100644 target/linux/patches/2.6.36/exmap.patch delete mode 100644 target/linux/patches/2.6.36/foxg20.patch delete mode 100644 target/linux/patches/2.6.36/freebsd-compat.patch delete mode 100644 target/linux/patches/2.6.36/gemalto.patch delete mode 100644 target/linux/patches/2.6.36/lemote.patch delete mode 100644 target/linux/patches/2.6.36/mtd-root.patch delete mode 100644 target/linux/patches/2.6.36/ocf-20100325.patch delete mode 100644 target/linux/patches/2.6.36/rb532.patch delete mode 100644 target/linux/patches/2.6.36/startup.patch delete mode 100644 target/linux/patches/2.6.36/uuid.patch delete mode 100644 target/linux/patches/2.6.36/yaffs2.patch delete mode 100644 target/linux/patches/2.6.36/zboot-brcm-reloc.patch delete mode 100644 target/linux/patches/2.6.37/ar7.patch delete mode 100644 target/linux/patches/2.6.37/ar71xx.patch delete mode 100644 target/linux/patches/2.6.37/atheros.patch delete mode 100644 target/linux/patches/2.6.37/aufs2.patch delete mode 100644 target/linux/patches/2.6.37/brcm.patch delete mode 100644 target/linux/patches/2.6.37/bsd-compatibility.patch delete mode 100644 target/linux/patches/2.6.37/cc-abstract.patch delete mode 100644 target/linux/patches/2.6.37/cris.patch delete mode 100644 target/linux/patches/2.6.37/cygwin-compat.patch delete mode 100644 target/linux/patches/2.6.37/drm-kconfig.patch delete mode 100644 target/linux/patches/2.6.37/exmap.patch delete mode 100644 target/linux/patches/2.6.37/foxg20.patch delete mode 100644 target/linux/patches/2.6.37/freebsd-compat.patch delete mode 100644 target/linux/patches/2.6.37/gemalto.patch delete mode 100644 target/linux/patches/2.6.37/lemote.patch delete mode 100644 target/linux/patches/2.6.37/mtd-rootfs.patch delete mode 100644 target/linux/patches/2.6.37/ocf-20100325.patch delete mode 100644 target/linux/patches/2.6.37/rb532.patch delete mode 100644 target/linux/patches/2.6.37/startup.patch delete mode 100644 target/linux/patches/2.6.37/usb-defaults-off.patch delete mode 100644 target/linux/patches/2.6.37/uuid.patch delete mode 100644 target/linux/patches/2.6.37/vga-cons-default-off.patch delete mode 100644 target/linux/patches/2.6.37/yaffs2.patch delete mode 100644 target/linux/patches/2.6.37/zlib-inflate.patch delete mode 100644 target/linux/patches/2.6.39/arm-statcmd.patch delete mode 100644 target/linux/patches/2.6.39/bsd-compatibility.patch delete mode 100644 target/linux/patches/2.6.39/cris-etrax.patch delete mode 100644 target/linux/patches/2.6.39/cris-thread-macro.patch delete mode 100644 target/linux/patches/2.6.39/cris.patch delete mode 100644 target/linux/patches/2.6.39/defaults.patch delete mode 100644 target/linux/patches/2.6.39/fon2100.patch delete mode 100644 target/linux/patches/2.6.39/gemalto.patch delete mode 100644 target/linux/patches/2.6.39/mips-malta.patch delete mode 100644 target/linux/patches/2.6.39/mmc-host.patch delete mode 100644 target/linux/patches/2.6.39/non-static.patch delete mode 100644 target/linux/patches/2.6.39/ocf-20100325.patch delete mode 100644 target/linux/patches/2.6.39/rb4xx.patch delete mode 100644 target/linux/patches/2.6.39/sparc-include.patch delete mode 100644 target/linux/patches/2.6.39/startup.patch delete mode 100644 target/linux/patches/2.6.39/usb-defaults-off.patch delete mode 100644 target/linux/patches/2.6.39/uuid.patch delete mode 100644 target/linux/patches/2.6.39/vga-cons-default-off.patch delete mode 100644 target/linux/patches/2.6.39/wlan-cf.patch delete mode 100644 target/linux/patches/2.6.39/x86-build.patch delete mode 100644 target/linux/patches/2.6.39/zlib-inflate.patch delete mode 100644 target/linux/patches/3.0.4/bsd-compatibility.patch delete mode 100644 target/linux/patches/3.0.4/cris-etrax.patch delete mode 100644 target/linux/patches/3.0.4/defaults.patch delete mode 100644 target/linux/patches/3.0.4/fon2100.patch delete mode 100644 target/linux/patches/3.0.4/gemalto.patch delete mode 100644 target/linux/patches/3.0.4/mips-malta.patch delete mode 100644 target/linux/patches/3.0.4/mmc-host.patch delete mode 100644 target/linux/patches/3.0.4/non-static.patch delete mode 100644 target/linux/patches/3.0.4/ocf-20110720.patch delete mode 100644 target/linux/patches/3.0.4/sparc-include.patch delete mode 100644 target/linux/patches/3.0.4/startup.patch delete mode 100644 target/linux/patches/3.0.4/usb-defaults-off.patch delete mode 100644 target/linux/patches/3.0.4/uuid.patch delete mode 100644 target/linux/patches/3.0.4/vga-cons-default-off.patch delete mode 100644 target/linux/patches/3.0.4/wlan-cf.patch delete mode 100644 target/linux/patches/3.0.4/x86-build.patch delete mode 100644 target/linux/patches/3.0.4/zlib-inflate.patch delete mode 100644 target/linux/patches/3.0.8/bsd-compatibility.patch delete mode 100644 target/linux/patches/3.0.8/cris-etrax.patch delete mode 100644 target/linux/patches/3.0.8/defaults.patch delete mode 100644 target/linux/patches/3.0.8/fon2100.patch delete mode 100644 target/linux/patches/3.0.8/gemalto.patch delete mode 100644 target/linux/patches/3.0.8/mips-malta.patch delete mode 100644 target/linux/patches/3.0.8/mmc-host.patch delete mode 100644 target/linux/patches/3.0.8/non-static.patch delete mode 100644 target/linux/patches/3.0.8/ocf-20110720.patch delete mode 100644 target/linux/patches/3.0.8/sparc-include.patch delete mode 100644 target/linux/patches/3.0.8/startup.patch delete mode 100644 target/linux/patches/3.0.8/usb-defaults-off.patch delete mode 100644 target/linux/patches/3.0.8/uuid.patch delete mode 100644 target/linux/patches/3.0.8/vga-cons-default-off.patch delete mode 100644 target/linux/patches/3.0.8/wlan-cf.patch delete mode 100644 target/linux/patches/3.0.8/x86-build.patch delete mode 100644 target/linux/patches/3.0.8/zlib-inflate.patch create mode 100644 target/linux/patches/3.0.9/bsd-compatibility.patch create mode 100644 target/linux/patches/3.0.9/cris-etrax.patch create mode 100644 target/linux/patches/3.0.9/defaults.patch create mode 100644 target/linux/patches/3.0.9/fon2100.patch create mode 100644 target/linux/patches/3.0.9/gemalto.patch create mode 100644 target/linux/patches/3.0.9/mips-malta.patch create mode 100644 target/linux/patches/3.0.9/mmc-host.patch create mode 100644 target/linux/patches/3.0.9/non-static.patch create mode 100644 target/linux/patches/3.0.9/ocf-20110720.patch create mode 100644 target/linux/patches/3.0.9/sparc-include.patch create mode 100644 target/linux/patches/3.0.9/startup.patch create mode 100644 target/linux/patches/3.0.9/usb-defaults-off.patch create mode 100644 target/linux/patches/3.0.9/uuid.patch create mode 100644 target/linux/patches/3.0.9/vga-cons-default-off.patch create mode 100644 target/linux/patches/3.0.9/wlan-cf.patch create mode 100644 target/linux/patches/3.0.9/x86-build.patch create mode 100644 target/linux/patches/3.0.9/zlib-inflate.patch create mode 100644 target/linux/patches/3.1.4/bsd-compatibility.patch create mode 100644 target/linux/patches/3.1.4/cris-etrax.patch create mode 100644 target/linux/patches/3.1.4/defaults.patch create mode 100644 target/linux/patches/3.1.4/fon2100.patch create mode 100644 target/linux/patches/3.1.4/gemalto.patch create mode 100644 target/linux/patches/3.1.4/mmc-host.patch create mode 100644 target/linux/patches/3.1.4/non-static.patch create mode 100644 target/linux/patches/3.1.4/ocf-20110720.patch create mode 100644 target/linux/patches/3.1.4/sparc-include.patch create mode 100644 target/linux/patches/3.1.4/startup.patch create mode 100644 target/linux/patches/3.1.4/usb-defaults-off.patch create mode 100644 target/linux/patches/3.1.4/uuid.patch create mode 100644 target/linux/patches/3.1.4/vga-cons-default-off.patch create mode 100644 target/linux/patches/3.1.4/wlan-cf.patch create mode 100644 target/linux/patches/3.1.4/x86-build.patch create mode 100644 target/linux/patches/3.1.4/zlib-inflate.patch (limited to 'target/linux') diff --git a/target/linux/patches/2.6.36/ar7.patch b/target/linux/patches/2.6.36/ar7.patch deleted file mode 100644 index 5f3b69ce1..000000000 --- a/target/linux/patches/2.6.36/ar7.patch +++ /dev/null @@ -1,90 +0,0 @@ -diff -Nur linux-2.6.36.orig/arch/mips/Kconfig linux-2.6.36/arch/mips/Kconfig ---- linux-2.6.36.orig/arch/mips/Kconfig 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/arch/mips/Kconfig 2010-12-16 21:02:19.000000000 +0100 -@@ -46,7 +46,6 @@ - select CEVT_R4K - select CSRC_R4K - select IRQ_CPU -- select NO_EXCEPT_FILL - select SWAP_IO_SPACE - select SYS_HAS_CPU_MIPS32_R1 - select SYS_HAS_EARLY_PRINTK -diff -Nur linux-2.6.36.orig/arch/mips/ar7/prom.c linux-2.6.36/arch/mips/ar7/prom.c ---- linux-2.6.36.orig/arch/mips/ar7/prom.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/arch/mips/ar7/prom.c 2010-12-16 21:02:19.000000000 +0100 -@@ -206,6 +206,14 @@ - if (strstr(arcs_cmdline, "console=")) - return; - -+#ifdef CONFIG_KGDB -+ if (!strstr(prom_getcmdline(), "nokgdb")) { -+ strcat(prom_getcmdline(), " console=kgdb"); -+ kgdb_enabled = 1; -+ return; -+ } -+#endif -+ - s = prom_getenv("modetty0"); - if (s) { - baud = simple_strtoul(s, &p, 10); -diff -Nur linux-2.6.36.orig/drivers/mtd/ar7part.c linux-2.6.36/drivers/mtd/ar7part.c ---- linux-2.6.36.orig/drivers/mtd/ar7part.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/drivers/mtd/ar7part.c 2010-12-16 21:02:19.000000000 +0100 -@@ -28,7 +28,7 @@ - #include - #include - --#define AR7_PARTS 4 -+#define AR7_PARTS 5 - #define ROOT_OFFSET 0xe0000 - - #define LOADER_MAGIC1 le32_to_cpu(0xfeedfa42) -@@ -122,14 +122,19 @@ - - ar7_parts[2].name = "linux"; - ar7_parts[2].offset = pre_size; -- ar7_parts[2].size = master->size - pre_size - post_size; -+ ar7_parts[2].size = master->size - pre_size - post_size - 2*master->erasesize; - ar7_parts[2].mask_flags = 0; - - ar7_parts[3].name = "rootfs"; - ar7_parts[3].offset = root_offset; -- ar7_parts[3].size = master->size - root_offset - post_size; -+ ar7_parts[3].size = master->size - root_offset - post_size - 2*master->erasesize; - ar7_parts[3].mask_flags = 0; - -+ ar7_parts[4].name = "cfgfs"; -+ ar7_parts[4].offset = master->size - 2*master->erasesize; -+ ar7_parts[4].size = 2*master->erasesize; -+ ar7_parts[4].mask_flags = 0; -+ - *pparts = ar7_parts; - return AR7_PARTS; - } -diff -Nur linux-2.6.36.orig/drivers/mtd/maps/physmap.c linux-2.6.36/drivers/mtd/maps/physmap.c ---- linux-2.6.36.orig/drivers/mtd/maps/physmap.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/drivers/mtd/maps/physmap.c 2010-12-16 21:02:19.000000000 +0100 -@@ -79,7 +79,7 @@ - "map_rom", - NULL }; - #ifdef CONFIG_MTD_PARTITIONS --static const char *part_probe_types[] = { "cmdlinepart", "RedBoot", NULL }; -+static const char *part_probe_types[] = { "cmdlinepart", "RedBoot", "ar7part", NULL }; - #endif - - static int physmap_flash_probe(struct platform_device *dev) -diff -Nur linux-2.6.36.orig/drivers/serial/8250.c linux-2.6.36/drivers/serial/8250.c ---- linux-2.6.36.orig/drivers/serial/8250.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/drivers/serial/8250.c 2010-12-16 21:02:19.000000000 +0100 -@@ -2761,7 +2761,11 @@ - { - struct uart_8250_port *up = (struct uart_8250_port *)port; - -+#ifdef CONFIG_AR7 -+ wait_for_xmitr(up, BOTH_EMPTY); -+#else - wait_for_xmitr(up, UART_LSR_THRE); -+#endif - serial_out(up, UART_TX, ch); - } - diff --git a/target/linux/patches/2.6.36/ar71xx.patch b/target/linux/patches/2.6.36/ar71xx.patch deleted file mode 100644 index 487b8f215..000000000 --- a/target/linux/patches/2.6.36/ar71xx.patch +++ /dev/null @@ -1,18666 +0,0 @@ -diff -Nur linux-2.6.36.orig/arch/mips/Kconfig linux-2.6.36/arch/mips/Kconfig ---- linux-2.6.36.orig/arch/mips/Kconfig 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/arch/mips/Kconfig 2010-12-17 18:34:51.000000000 +0100 -@@ -60,6 +60,23 @@ - Support for the Texas Instruments AR7 System-on-a-Chip - family: TNETD7100, 7200 and 7300. - -+config ATHEROS_AR71XX -+ bool "Atheros AR71xx based boards" -+ select CEVT_R4K -+ select CSRC_R4K -+ select DMA_NONCOHERENT -+ select HW_HAS_PCI -+ select IRQ_CPU -+ select ARCH_REQUIRE_GPIOLIB -+ select SYS_HAS_CPU_MIPS32_R1 -+ select SYS_HAS_CPU_MIPS32_R2 -+ select SYS_SUPPORTS_32BIT_KERNEL -+ select SYS_SUPPORTS_BIG_ENDIAN -+ select SYS_HAS_EARLY_PRINTK -+ select MIPS_MACHINE -+ help -+ Support for Atheros AR71xx based boards. -+ - config BCM47XX - bool "Broadcom BCM47XX based boards" - select CEVT_R4K -@@ -709,6 +726,7 @@ - endchoice - - source "arch/mips/alchemy/Kconfig" -+source "arch/mips/ar71xx/Kconfig" - source "arch/mips/bcm63xx/Kconfig" - source "arch/mips/jazz/Kconfig" - source "arch/mips/jz4740/Kconfig" -@@ -872,9 +890,15 @@ - config MIPS_DISABLE_OBSOLETE_IDE - bool - -+config MYLOADER -+ bool -+ - config SYNC_R4K - bool - -+config MIPS_MACHINE -+ def_bool n -+ - config NO_IOPORT - def_bool n - -diff -Nur linux-2.6.36.orig/arch/mips/Makefile linux-2.6.36/arch/mips/Makefile ---- linux-2.6.36.orig/arch/mips/Makefile 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/arch/mips/Makefile 2010-12-17 18:34:51.000000000 +0100 -@@ -160,6 +160,13 @@ - cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -Wa,-march=octeon - endif - -+# -+# Atheros AR71xx -+# -+core-$(CONFIG_ATHEROS_AR71XX) += arch/mips/ar71xx/ -+cflags-$(CONFIG_ATHEROS_AR71XX) += -I$(srctree)/arch/mips/include/asm/mach-ar71xx -+load-$(CONFIG_ATHEROS_AR71XX) += 0xffffffff80060000 -+ - cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,) - cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += $(call cc-option,-mfix-r4400,) - cflags-$(CONFIG_CPU_DADDI_WORKAROUNDS) += $(call cc-option,-mno-daddi,) -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/Kconfig linux-2.6.36/arch/mips/ar71xx/Kconfig ---- linux-2.6.36.orig/arch/mips/ar71xx/Kconfig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/Kconfig 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,264 @@ -+if ATHEROS_AR71XX -+ -+menu "Atheros AR71xx machine selection" -+ -+config AR71XX_MACH_AP81 -+ bool "Atheros AP81 board support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AR913X_WMAC -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ default n -+ -+config AR71XX_MACH_AP83 -+ bool "Atheros AP83 board support" -+ select AR71XX_DEV_AR913X_WMAC -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ default n -+ -+config AR71XX_MACH_DIR_600_A1 -+ bool "D-Link DIR-600 rev. A1 support" -+ select AR71XX_DEV_AP91_ETH -+ select AR71XX_DEV_AP91_PCI if PCI -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_NVRAM -+ default n -+ -+config AR71XX_MACH_DIR_615_C1 -+ bool "D-Link DIR-615 rev. C1 support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AR913X_WMAC -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_NVRAM -+ default n -+ -+config AR71XX_MACH_DIR_825_B1 -+ bool "D-Link DIR-825 rev. B1 board support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AP94_PCI if PCI -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ default n -+ -+config AR71XX_MACH_PB42 -+ bool "Atheros PB42 board support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_PB42_PCI if PCI -+ default n -+ -+config AR71XX_MACH_PB44 -+ bool "Atheros PB44 board support" -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_PB42_PCI if PCI -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ default n -+ -+config AR71XX_MACH_PB92 -+ bool "Atheros PB92 board support" -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_PB9X_PCI if PCI -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ default n -+ -+config AR71XX_MACH_AW_NR580 -+ bool "AzureWave AW-NR580 board support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_PB42_PCI if PCI -+ select AR71XX_DEV_LEDS_GPIO -+ default n -+ -+config AR71XX_MACH_WZR_HP_G300NH -+ bool "Buffalo WZR-HP-G300NH board support" -+ select AR71XX_DEV_AR913X_WMAC -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ default y -+ -+config AR71XX_MACH_WP543 -+ bool "Compex WP543/WPJ543 board support" -+ select MYLOADER -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_PB42_PCI if PCI -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ default n -+ -+config AR71XX_MACH_WRT160NL -+ bool "Linksys WRT160NL board support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AR913X_WMAC -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ select AR71XX_NVRAM -+ default n -+ -+config AR71XX_MACH_WRT400N -+ bool "Linksys WRT400N board support" -+ select AR71XX_DEV_AP94_PCI if PCI -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ default n -+ -+config AR71XX_MACH_RB4XX -+ bool "MikroTik RouterBOARD 4xx series support" -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ default n -+ -+config AR71XX_MACH_RB750 -+ bool "MikroTik RouterBOARD 750 support" -+ select AR71XX_DEV_AP91_ETH -+ default n -+ -+config AR71XX_MACH_WNDR3700 -+ bool "NETGEAR WNDR3700 board support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AP94_PCI if PCI -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ default n -+ -+config AR71XX_MACH_WNR2000 -+ bool "NETGEAR WNR2000 board support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AR913X_WMAC -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ default n -+ -+config AR71XX_MACH_MZK_W04NU -+ bool "Planex MZK-W04NU board support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AR913X_WMAC -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ default n -+ -+config AR71XX_MACH_MZK_W300NH -+ bool "Planex MZK-W300NH board support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AR913X_WMAC -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ default n -+ -+config AR71XX_MACH_NBG460N -+ bool "Zyxel NBG460N/550N/550NH board support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AR913X_WMAC -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ default n -+ -+config AR71XX_MACH_TL_WR741ND -+ bool "TP-LINK TL-WR741ND support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AP91_ETH -+ select AR71XX_DEV_AP91_PCI if PCI -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ default n -+ -+config AR71XX_MACH_TL_WR841N_V1 -+ bool "TP-LINK TL-WR841N v1 support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_PB42_PCI if PCI -+ select AR71XX_DEV_DSA -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ default n -+ -+config AR71XX_MACH_TL_WR941ND -+ bool "TP-LINK TL-WR941ND support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AR913X_WMAC -+ select AR71XX_DEV_DSA -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ default n -+ -+config AR71XX_MACH_TL_WR1043ND -+ bool "TP-LINK TL-WR1043ND support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AR913X_WMAC -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ default n -+ -+config AR71XX_MACH_TEW_632BRP -+ bool "TRENDnet TEW-632BRP support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AR913X_WMAC -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_NVRAM -+ default n -+ -+config AR71XX_MACH_UBNT -+ bool "Ubiquiti AR71xx based boards support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AP91_PCI if PCI -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_PB42_PCI if PCI -+ select AR71XX_DEV_USB -+ default n -+ -+endmenu -+ -+config AR71XX_DEV_M25P80 -+ def_bool n -+ -+config AR71XX_DEV_AP91_PCI -+ def_bool n -+ -+config AR71XX_DEV_AP91_ETH -+ def_bool n -+ -+config AR71XX_DEV_AP94_PCI -+ def_bool n -+ -+config AR71XX_DEV_AR913X_WMAC -+ def_bool n -+ -+config AR71XX_DEV_DSA -+ def_bool n -+ -+config AR71XX_DEV_GPIO_BUTTONS -+ def_bool n -+ -+config AR71XX_DEV_LEDS_GPIO -+ def_bool n -+ -+config AR71XX_DEV_PB42_PCI -+ def_bool n -+ -+config AR71XX_DEV_PB9X_PCI -+ def_bool n -+ -+config AR71XX_DEV_USB -+ def_bool n -+ -+config AR71XX_NVRAM -+ def_bool n -+ -+endif -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/Makefile linux-2.6.36/arch/mips/ar71xx/Makefile ---- linux-2.6.36.orig/arch/mips/ar71xx/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/Makefile 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,54 @@ -+# -+# Makefile for the Atheros AR71xx SoC specific parts of the kernel -+# -+# Copyright (C) 2008-2009 Gabor Juhos -+# Copyright (C) 2008 Imre Kaloz -+# -+# This program is free software; you can redistribute it and/or modify it -+# under the terms of the GNU General Public License version 2 as published -+# by the Free Software Foundation. -+ -+obj-y := prom.o irq.o setup.o devices.o gpio.o ar71xx.o -+ -+obj-$(CONFIG_EARLY_PRINTK) += early_printk.o -+obj-$(CONFIG_PCI) += pci.o -+ -+obj-$(CONFIG_AR71XX_DEV_AP91_ETH) += dev-ap91-eth.o -+obj-$(CONFIG_AR71XX_DEV_AP91_PCI) += dev-ap91-pci.o -+obj-$(CONFIG_AR71XX_DEV_AP94_PCI) += dev-ap94-pci.o -+obj-$(CONFIG_AR71XX_DEV_AR913X_WMAC) += dev-ar913x-wmac.o -+obj-$(CONFIG_AR71XX_DEV_DSA) += dev-dsa.o -+obj-$(CONFIG_AR71XX_DEV_GPIO_BUTTONS) += dev-gpio-buttons.o -+obj-$(CONFIG_AR71XX_DEV_LEDS_GPIO) += dev-leds-gpio.o -+obj-$(CONFIG_AR71XX_DEV_M25P80) += dev-m25p80.o -+obj-$(CONFIG_AR71XX_DEV_PB42_PCI) += dev-pb42-pci.o -+obj-$(CONFIG_AR71XX_DEV_PB9X_PCI) += dev-pb9x-pci.o -+obj-$(CONFIG_AR71XX_DEV_USB) += dev-usb.o -+ -+obj-$(CONFIG_AR71XX_NVRAM) += nvram.o -+ -+obj-$(CONFIG_AR71XX_MACH_AP81) += mach-ap81.o -+obj-$(CONFIG_AR71XX_MACH_AP83) += mach-ap83.o -+obj-$(CONFIG_AR71XX_MACH_AW_NR580) += mach-aw-nr580.o -+obj-$(CONFIG_AR71XX_MACH_DIR_600_A1) += mach-dir-600-a1.o -+obj-$(CONFIG_AR71XX_MACH_DIR_615_C1) += mach-dir-615-c1.o -+obj-$(CONFIG_AR71XX_MACH_DIR_825_B1) += mach-dir-825-b1.o -+obj-$(CONFIG_AR71XX_MACH_MZK_W04NU) += mach-mzk-w04nu.o -+obj-$(CONFIG_AR71XX_MACH_MZK_W300NH) += mach-mzk-w300nh.o -+obj-$(CONFIG_AR71XX_MACH_NBG460N) += mach-nbg460n.o -+obj-$(CONFIG_AR71XX_MACH_PB42) += mach-pb42.o -+obj-$(CONFIG_AR71XX_MACH_PB44) += mach-pb44.o -+obj-$(CONFIG_AR71XX_MACH_PB92) += mach-pb92.o -+obj-$(CONFIG_AR71XX_MACH_RB4XX) += mach-rb4xx.o -+obj-$(CONFIG_AR71XX_MACH_RB750) += mach-rb750.o -+obj-$(CONFIG_AR71XX_MACH_TEW_632BRP) += mach-tew-632brp.o -+obj-$(CONFIG_AR71XX_MACH_TL_WR741ND) += mach-tl-wr741nd.o -+obj-$(CONFIG_AR71XX_MACH_TL_WR841N_V1) += mach-tl-wr841n.o -+obj-$(CONFIG_AR71XX_MACH_TL_WR941ND) += mach-tl-wr941nd.o -+obj-$(CONFIG_AR71XX_MACH_TL_WR1043ND) += mach-tl-wr1043nd.o -+obj-$(CONFIG_AR71XX_MACH_UBNT) += mach-ubnt.o -+obj-$(CONFIG_AR71XX_MACH_WNDR3700) += mach-wndr3700.o -+obj-$(CONFIG_AR71XX_MACH_WNR2000) += mach-wnr2000.o -+obj-$(CONFIG_AR71XX_MACH_WP543) += mach-wp543.o -+obj-$(CONFIG_AR71XX_MACH_WRT160NL) += mach-wrt160nl.o -+obj-$(CONFIG_AR71XX_MACH_WRT400N) += mach-wrt400n.o -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/ar71xx.c linux-2.6.36/arch/mips/ar71xx/ar71xx.c ---- linux-2.6.36.orig/arch/mips/ar71xx/ar71xx.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/ar71xx.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,177 @@ -+/* -+ * AR71xx SoC routines -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include -+ -+static DEFINE_MUTEX(ar71xx_flash_mutex); -+ -+void __iomem *ar71xx_ddr_base; -+EXPORT_SYMBOL_GPL(ar71xx_ddr_base); -+ -+void __iomem *ar71xx_pll_base; -+EXPORT_SYMBOL_GPL(ar71xx_pll_base); -+ -+void __iomem *ar71xx_reset_base; -+EXPORT_SYMBOL_GPL(ar71xx_reset_base); -+ -+void __iomem *ar71xx_gpio_base; -+EXPORT_SYMBOL_GPL(ar71xx_gpio_base); -+ -+void __iomem *ar71xx_usb_ctrl_base; -+EXPORT_SYMBOL_GPL(ar71xx_usb_ctrl_base); -+ -+void ar71xx_device_stop(u32 mask) -+{ -+ unsigned long flags; -+ u32 mask_inv; -+ u32 t; -+ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7130: -+ case AR71XX_SOC_AR7141: -+ case AR71XX_SOC_AR7161: -+ local_irq_save(flags); -+ t = ar71xx_reset_rr(AR71XX_RESET_REG_RESET_MODULE); -+ ar71xx_reset_wr(AR71XX_RESET_REG_RESET_MODULE, t | mask); -+ local_irq_restore(flags); -+ break; -+ -+ case AR71XX_SOC_AR7240: -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ mask_inv = mask & RESET_MODULE_USB_OHCI_DLL_7240; -+ local_irq_save(flags); -+ t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE); -+ t |= mask; -+ t &= ~mask_inv; -+ ar71xx_reset_wr(AR724X_RESET_REG_RESET_MODULE, t); -+ local_irq_restore(flags); -+ break; -+ -+ case AR71XX_SOC_AR9130: -+ case AR71XX_SOC_AR9132: -+ local_irq_save(flags); -+ t = ar71xx_reset_rr(AR91XX_RESET_REG_RESET_MODULE); -+ ar71xx_reset_wr(AR91XX_RESET_REG_RESET_MODULE, t | mask); -+ local_irq_restore(flags); -+ break; -+ -+ default: -+ BUG(); -+ } -+} -+EXPORT_SYMBOL_GPL(ar71xx_device_stop); -+ -+void ar71xx_device_start(u32 mask) -+{ -+ unsigned long flags; -+ u32 mask_inv; -+ u32 t; -+ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7130: -+ case AR71XX_SOC_AR7141: -+ case AR71XX_SOC_AR7161: -+ local_irq_save(flags); -+ t = ar71xx_reset_rr(AR71XX_RESET_REG_RESET_MODULE); -+ ar71xx_reset_wr(AR71XX_RESET_REG_RESET_MODULE, t & ~mask); -+ local_irq_restore(flags); -+ break; -+ -+ case AR71XX_SOC_AR7240: -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ mask_inv = mask & RESET_MODULE_USB_OHCI_DLL_7240; -+ local_irq_save(flags); -+ t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE); -+ t &= ~mask; -+ t |= mask_inv; -+ ar71xx_reset_wr(AR724X_RESET_REG_RESET_MODULE, t); -+ local_irq_restore(flags); -+ break; -+ -+ case AR71XX_SOC_AR9130: -+ case AR71XX_SOC_AR9132: -+ local_irq_save(flags); -+ t = ar71xx_reset_rr(AR91XX_RESET_REG_RESET_MODULE); -+ ar71xx_reset_wr(AR91XX_RESET_REG_RESET_MODULE, t & ~mask); -+ local_irq_restore(flags); -+ break; -+ -+ default: -+ BUG(); -+ } -+} -+EXPORT_SYMBOL_GPL(ar71xx_device_start); -+ -+int ar71xx_device_stopped(u32 mask) -+{ -+ unsigned long flags; -+ u32 t; -+ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7130: -+ case AR71XX_SOC_AR7141: -+ case AR71XX_SOC_AR7161: -+ local_irq_save(flags); -+ t = ar71xx_reset_rr(AR71XX_RESET_REG_RESET_MODULE); -+ local_irq_restore(flags); -+ break; -+ -+ case AR71XX_SOC_AR7240: -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ local_irq_save(flags); -+ t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE); -+ local_irq_restore(flags); -+ break; -+ -+ case AR71XX_SOC_AR9130: -+ case AR71XX_SOC_AR9132: -+ local_irq_save(flags); -+ t = ar71xx_reset_rr(AR91XX_RESET_REG_RESET_MODULE); -+ local_irq_restore(flags); -+ break; -+ -+ default: -+ BUG(); -+ } -+ -+ return ((t & mask) == mask); -+} -+EXPORT_SYMBOL_GPL(ar71xx_device_stopped); -+ -+void ar71xx_ddr_flush(u32 reg) -+{ -+ ar71xx_ddr_wr(reg, 1); -+ while ((ar71xx_ddr_rr(reg) & 0x1)); -+ -+ ar71xx_ddr_wr(reg, 1); -+ while ((ar71xx_ddr_rr(reg) & 0x1)); -+} -+EXPORT_SYMBOL_GPL(ar71xx_ddr_flush); -+ -+void ar71xx_flash_acquire(void) -+{ -+ mutex_lock(&ar71xx_flash_mutex); -+} -+EXPORT_SYMBOL_GPL(ar71xx_flash_acquire); -+ -+void ar71xx_flash_release(void) -+{ -+ mutex_unlock(&ar71xx_flash_mutex); -+} -+EXPORT_SYMBOL_GPL(ar71xx_flash_release); -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/dev-ap91-eth.c linux-2.6.36/arch/mips/ar71xx/dev-ap91-eth.c ---- linux-2.6.36.orig/arch/mips/ar71xx/dev-ap91-eth.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/dev-ap91-eth.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,70 @@ -+/* -+ * Atheros AP91 reference board ethernet initialization -+ * -+ * Copyright (C) 2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include "devices.h" -+#include "dev-dsa.h" -+#include "dev-ap91-eth.h" -+ -+static struct dsa_chip_data ap91_dsa_chip = { -+ .port_names[0] = "cpu", -+ .port_names[1] = "lan1", -+ .port_names[2] = "lan2", -+ .port_names[3] = "lan3", -+ .port_names[4] = "lan4", -+}; -+ -+static struct dsa_platform_data ap91_dsa_data = { -+ .nr_chips = 1, -+ .chip = &ap91_dsa_chip, -+}; -+ -+static void ap91_eth_set_port_name(unsigned port, const char *name) -+{ -+ if (port < 1 || port > 5) -+ return; -+ -+ if (name) -+ ap91_dsa_chip.port_names[port] = (char *) name; -+} -+ -+void __init ap91_eth_init(u8 *mac_addr, const char *port_names[]) -+{ -+ if (mac_addr) -+ ar71xx_set_mac_base(mac_addr); -+ -+ if (port_names) { -+ int i; -+ -+ for (i = 0; i < AP91_ETH_NUM_PORT_NAMES; i++) -+ ap91_eth_set_port_name(i + 1, port_names[i]); -+ } -+ -+ /* WAN port */ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ ar71xx_eth0_data.fifo_cfg1 = 0x0fff0000; -+ ar71xx_eth0_data.fifo_cfg2 = 0x00001fff; -+ ar71xx_eth0_data.fifo_cfg3 = 0x008001ff; -+ -+ /* LAN ports */ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.speed = SPEED_1000; -+ ar71xx_eth1_data.duplex = DUPLEX_FULL; -+ ar71xx_eth1_data.fifo_cfg1 = 0x0fff0000; -+ ar71xx_eth1_data.fifo_cfg2 = 0x00001fff; -+ ar71xx_eth1_data.fifo_cfg3 = 0x008001ff; -+ -+ ar71xx_add_device_mdio(0x0); -+ ar71xx_add_device_eth(1); -+ ar71xx_add_device_eth(0); -+ -+ ar71xx_add_device_dsa(1, &ap91_dsa_data); -+} -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/dev-ap91-eth.h linux-2.6.36/arch/mips/ar71xx/dev-ap91-eth.h ---- linux-2.6.36.orig/arch/mips/ar71xx/dev-ap91-eth.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/dev-ap91-eth.h 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,23 @@ -+/* -+ * Atheros AP91 reference board ethernet initialization -+ * -+ * Copyright (C) 2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_DEV_AP91_ETH_H -+#define _AR71XX_DEV_AP91_ETH_H -+ -+#define AP91_ETH_NUM_PORT_NAMES 4 -+ -+#if defined(CONFIG_AR71XX_DEV_AP91_ETH) -+void ap91_eth_init(u8 *mac_addr, const char *port_names[]) __init; -+#else -+static inline void ap91_eth_init(u8 *mac_addr) { } -+#endif -+ -+#endif /* _AR71XX_DEV_AP91_ETH_H */ -+ -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/dev-ap91-pci.c linux-2.6.36/arch/mips/ar71xx/dev-ap91-pci.c ---- linux-2.6.36.orig/arch/mips/ar71xx/dev-ap91-pci.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/dev-ap91-pci.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,114 @@ -+/* -+ * Atheros AP91 reference board PCI initialization -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include "dev-ap91-pci.h" -+ -+static struct ath9k_platform_data ap91_wmac_data; -+static char ap91_wmac_mac[6]; -+static int ap91_pci_fixup_enabled; -+ -+static struct ar71xx_pci_irq ap91_pci_irqs[] __initdata = { -+ { -+ .slot = 0, -+ .pin = 1, -+ .irq = AR71XX_PCI_IRQ_DEV0, -+ } -+}; -+ -+static int ap91_pci_plat_dev_init(struct pci_dev *dev) -+{ -+ switch(PCI_SLOT(dev->devfn)) { -+ case 0: -+ dev->dev.platform_data = &ap91_wmac_data; -+ break; -+ } -+ -+ return 0; -+} -+ -+static void ap91_pci_fixup(struct pci_dev *dev) -+{ -+ void __iomem *mem; -+ u16 *cal_data; -+ u16 cmd; -+ u32 val; -+ -+ if (!ap91_pci_fixup_enabled) -+ return; -+ -+ printk(KERN_INFO "PCI: fixup device %s\n", pci_name(dev)); -+ -+ cal_data = ap91_wmac_data.eeprom_data; -+ if (*cal_data != 0xa55a) { -+ printk(KERN_ERR "PCI: no calibration data found for %s\n", -+ pci_name(dev)); -+ return; -+ } -+ -+ mem = ioremap(AR71XX_PCI_MEM_BASE, 0x10000); -+ if (!mem) { -+ printk(KERN_ERR "PCI: ioremap error for device %s\n", -+ pci_name(dev)); -+ return; -+ } -+ -+ /* Setup the PCI device to allow access to the internal registers */ -+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0xffff); -+ pci_read_config_word(dev, PCI_COMMAND, &cmd); -+ cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; -+ pci_write_config_word(dev, PCI_COMMAND, cmd); -+ -+ /* set pointer to first reg address */ -+ cal_data += 3; -+ while (*cal_data != 0xffff) { -+ u32 reg; -+ reg = *cal_data++; -+ val = *cal_data++; -+ val |= (*cal_data++) << 16; -+ -+ __raw_writel(val, mem + reg); -+ udelay(100); -+ } -+ -+ pci_read_config_dword(dev, PCI_VENDOR_ID, &val); -+ dev->vendor = val & 0xffff; -+ dev->device = (val >> 16) & 0xffff; -+ -+ pci_read_config_dword(dev, PCI_CLASS_REVISION, &val); -+ dev->revision = val & 0xff; -+ dev->class = val >> 8; /* upper 3 bytes */ -+ -+ iounmap(mem); -+} -+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ap91_pci_fixup); -+ -+void __init ap91_pci_init(u8 *cal_data, u8 *mac_addr) -+{ -+ if (cal_data) -+ memcpy(ap91_wmac_data.eeprom_data, cal_data, -+ sizeof(ap91_wmac_data.eeprom_data)); -+ -+ if (mac_addr) { -+ memcpy(ap91_wmac_mac, mac_addr, sizeof(ap91_wmac_mac)); -+ ap91_wmac_data.macaddr = ap91_wmac_mac; -+ } -+ -+ ar71xx_pci_plat_dev_init = ap91_pci_plat_dev_init; -+ ar71xx_pci_init(ARRAY_SIZE(ap91_pci_irqs), ap91_pci_irqs); -+ -+ ap91_pci_fixup_enabled = 1; -+} -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/dev-ap91-pci.h linux-2.6.36/arch/mips/ar71xx/dev-ap91-pci.h ---- linux-2.6.36.orig/arch/mips/ar71xx/dev-ap91-pci.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/dev-ap91-pci.h 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,21 @@ -+/* -+ * Atheros AP91 reference board PCI initialization -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_DEV_AP91_PCI_H -+#define _AR71XX_DEV_AP91_PCI_H -+ -+#if defined(CONFIG_AR71XX_DEV_AP91_PCI) -+void ap91_pci_init(u8 *cal_data, u8 *mac_addr) __init; -+#else -+static inline void ap91_pci_init(u8 *cal_data, u8 *mac_addr) { } -+#endif -+ -+#endif /* _AR71XX_DEV_AP91_PCI_H */ -+ -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/dev-ap94-pci.c linux-2.6.36/arch/mips/ar71xx/dev-ap94-pci.c ---- linux-2.6.36.orig/arch/mips/ar71xx/dev-ap94-pci.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/dev-ap94-pci.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,159 @@ -+/* -+ * Atheros AP94 reference board PCI initialization -+ * -+ * Copyright (C) 2009-2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include "dev-ap94-pci.h" -+ -+static struct ath9k_platform_data ap94_wmac0_data; -+static struct ath9k_platform_data ap94_wmac1_data; -+static char ap94_wmac0_mac[6]; -+static char ap94_wmac1_mac[6]; -+static int ap94_pci_fixup_enabled; -+ -+static struct ar71xx_pci_irq ap94_pci_irqs[] __initdata = { -+ { -+ .slot = 0, -+ .pin = 1, -+ .irq = AR71XX_PCI_IRQ_DEV0, -+ }, { -+ .slot = 1, -+ .pin = 1, -+ .irq = AR71XX_PCI_IRQ_DEV1, -+ } -+}; -+ -+static int ap94_pci_plat_dev_init(struct pci_dev *dev) -+{ -+ switch(PCI_SLOT(dev->devfn)) { -+ case 17: -+ dev->dev.platform_data = &ap94_wmac0_data; -+ break; -+ -+ case 18: -+ dev->dev.platform_data = &ap94_wmac1_data; -+ break; -+ } -+ -+ return 0; -+} -+ -+static void ap94_pci_fixup(struct pci_dev *dev) -+{ -+ void __iomem *mem; -+ u16 *cal_data; -+ u16 cmd; -+ u32 bar0; -+ u32 val; -+ -+ if (!ap94_pci_fixup_enabled) -+ return; -+ -+ switch (PCI_SLOT(dev->devfn)) { -+ case 17: -+ cal_data = ap94_wmac0_data.eeprom_data; -+ break; -+ case 18: -+ cal_data = ap94_wmac1_data.eeprom_data; -+ break; -+ default: -+ return; -+ } -+ -+ if (*cal_data != 0xa55a) { -+ printk(KERN_ERR "PCI: no calibration data found for %s\n", -+ pci_name(dev)); -+ return; -+ } -+ -+ mem = ioremap(AR71XX_PCI_MEM_BASE, 0x10000); -+ if (!mem) { -+ printk(KERN_ERR "PCI: ioremap error for device %s\n", -+ pci_name(dev)); -+ return; -+ } -+ -+ printk(KERN_INFO "PCI: fixup device %s\n", pci_name(dev)); -+ -+ pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0); -+ -+ /* Setup the PCI device to allow access to the internal registers */ -+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, AR71XX_PCI_MEM_BASE); -+ pci_read_config_word(dev, PCI_COMMAND, &cmd); -+ cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; -+ pci_write_config_word(dev, PCI_COMMAND, cmd); -+ -+ /* set pointer to first reg address */ -+ cal_data += 3; -+ while (*cal_data != 0xffff) { -+ u32 reg; -+ reg = *cal_data++; -+ val = *cal_data++; -+ val |= (*cal_data++) << 16; -+ -+ __raw_writel(val, mem + reg); -+ udelay(100); -+ } -+ -+ pci_read_config_dword(dev, PCI_VENDOR_ID, &val); -+ dev->vendor = val & 0xffff; -+ dev->device = (val >> 16) & 0xffff; -+ -+ pci_read_config_dword(dev, PCI_CLASS_REVISION, &val); -+ dev->revision = val & 0xff; -+ dev->class = val >> 8; /* upper 3 bytes */ -+ -+ pci_read_config_word(dev, PCI_COMMAND, &cmd); -+ cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); -+ pci_write_config_word(dev, PCI_COMMAND, cmd); -+ -+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, bar0); -+ -+ iounmap(mem); -+} -+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ap94_pci_fixup); -+ -+void __init ap94_pci_enable_quirk_wndr3700(void) -+{ -+ ap94_wmac0_data.quirk_wndr3700 = 1; -+ ap94_wmac1_data.quirk_wndr3700 = 1; -+} -+ -+void __init ap94_pci_init(u8 *cal_data0, u8 *mac_addr0, -+ u8 *cal_data1, u8 *mac_addr1) -+{ -+ if (cal_data0) -+ memcpy(ap94_wmac0_data.eeprom_data, cal_data0, -+ sizeof(ap94_wmac0_data.eeprom_data)); -+ -+ if (cal_data1) -+ memcpy(ap94_wmac1_data.eeprom_data, cal_data1, -+ sizeof(ap94_wmac1_data.eeprom_data)); -+ -+ if (mac_addr0) { -+ memcpy(ap94_wmac0_mac, mac_addr0, sizeof(ap94_wmac0_mac)); -+ ap94_wmac0_data.macaddr = ap94_wmac0_mac; -+ } -+ -+ if (mac_addr1) { -+ memcpy(ap94_wmac1_mac, mac_addr1, sizeof(ap94_wmac1_mac)); -+ ap94_wmac1_data.macaddr = ap94_wmac1_mac; -+ } -+ -+ ar71xx_pci_plat_dev_init = ap94_pci_plat_dev_init; -+ ar71xx_pci_init(ARRAY_SIZE(ap94_pci_irqs), ap94_pci_irqs); -+ -+ ap94_pci_fixup_enabled = 1; -+} -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/dev-ap94-pci.h linux-2.6.36/arch/mips/ar71xx/dev-ap94-pci.h ---- linux-2.6.36.orig/arch/mips/ar71xx/dev-ap94-pci.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/dev-ap94-pci.h 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,28 @@ -+/* -+ * Atheros AP94 reference board PCI initialization -+ * -+ * Copyright (C) 2009-2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_DEV_AP94_PCI_H -+#define _AR71XX_DEV_AP94_PCI_H -+ -+#if defined(CONFIG_AR71XX_DEV_AP94_PCI) -+void ap94_pci_init(u8 *cal_data0, u8 *mac_addr0, -+ u8 *cal_data1, u8 *mac_addr1) __init; -+ -+void ap94_pci_enable_quirk_wndr3700(void) __init; -+ -+#else -+static inline void ap94_pci_init(u8 *cal_data0, u8 *mac_addr0, -+ u8 *cal_data1, u8 *mac_addr1) {} -+ -+static inline void ap94_pci_enable_quirk_wndr3700(void) {} -+#endif -+ -+#endif /* _AR71XX_DEV_AP94_PCI_H */ -+ -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/dev-ar913x-wmac.c linux-2.6.36/arch/mips/ar71xx/dev-ar913x-wmac.c ---- linux-2.6.36.orig/arch/mips/ar71xx/dev-ar913x-wmac.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/dev-ar913x-wmac.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,68 @@ -+/* -+ * Atheros AR913x SoC built-in WMAC device support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "dev-ar913x-wmac.h" -+ -+static struct ath9k_platform_data ar913x_wmac_data; -+static char ar913x_wmac_mac[6]; -+ -+static struct resource ar913x_wmac_resources[] = { -+ { -+ .start = AR91XX_WMAC_BASE, -+ .end = AR91XX_WMAC_BASE + AR91XX_WMAC_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+ }, { -+ .start = AR71XX_CPU_IRQ_IP2, -+ .end = AR71XX_CPU_IRQ_IP2, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct platform_device ar913x_wmac_device = { -+ .name = "ath9k", -+ .id = -1, -+ .resource = ar913x_wmac_resources, -+ .num_resources = ARRAY_SIZE(ar913x_wmac_resources), -+ .dev = { -+ .platform_data = &ar913x_wmac_data, -+ }, -+}; -+ -+void __init ar913x_add_device_wmac(u8 *cal_data, u8 *mac_addr) -+{ -+ if (cal_data) -+ memcpy(ar913x_wmac_data.eeprom_data, cal_data, -+ sizeof(ar913x_wmac_data.eeprom_data)); -+ -+ if (mac_addr) { -+ memcpy(ar913x_wmac_mac, mac_addr, sizeof(ar913x_wmac_mac)); -+ ar913x_wmac_data.macaddr = ar913x_wmac_mac; -+ } -+ -+ ar71xx_device_stop(RESET_MODULE_AMBA2WMAC); -+ mdelay(10); -+ -+ ar71xx_device_start(RESET_MODULE_AMBA2WMAC); -+ mdelay(10); -+ -+ platform_device_register(&ar913x_wmac_device); -+} -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/dev-ar913x-wmac.h linux-2.6.36/arch/mips/ar71xx/dev-ar913x-wmac.h ---- linux-2.6.36.orig/arch/mips/ar71xx/dev-ar913x-wmac.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/dev-ar913x-wmac.h 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,19 @@ -+/* -+ * Atheros AR913x SoC built-in WMAC device support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_DEV_AR913X_WMAC_H -+#define _AR71XX_DEV_AR913X_WMAC_H -+ -+void ar913x_add_device_wmac(u8 *cal_data, u8 *mac_addr) __init; -+ -+#endif /* _AR71XX_DEV_AR913X_WMAC_H */ -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/dev-dsa.c linux-2.6.36/arch/mips/ar71xx/dev-dsa.c ---- linux-2.6.36.orig/arch/mips/ar71xx/dev-dsa.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/dev-dsa.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,50 @@ -+/* -+ * Atheros AR71xx DSA switch device support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "devices.h" -+#include "dev-dsa.h" -+ -+static struct platform_device ar71xx_dsa_switch_device = { -+ .name = "dsa", -+ .id = 0, -+}; -+ -+void __init ar71xx_add_device_dsa(unsigned int id, -+ struct dsa_platform_data *d) -+{ -+ int i; -+ -+ switch (id) { -+ case 0: -+ d->netdev = &ar71xx_eth0_device.dev; -+ break; -+ case 1: -+ d->netdev = &ar71xx_eth1_device.dev; -+ break; -+ default: -+ printk(KERN_ERR -+ "ar71xx: invalid ethernet id %d for DSA switch\n", -+ id); -+ return; -+ } -+ -+ for (i = 0; i < d->nr_chips; i++) -+ d->chip[i].mii_bus = &ar71xx_mdio_device.dev; -+ -+ ar71xx_dsa_switch_device.dev.platform_data = d; -+ -+ platform_device_register(&ar71xx_dsa_switch_device); -+} -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/dev-dsa.h linux-2.6.36/arch/mips/ar71xx/dev-dsa.h ---- linux-2.6.36.orig/arch/mips/ar71xx/dev-dsa.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/dev-dsa.h 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,20 @@ -+/* -+ * Atheros AR71xx DSA switch device support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_DEV_DSA_H -+#define _AR71XX_DEV_DSA_H -+ -+#include -+ -+void ar71xx_add_device_dsa(unsigned int id, -+ struct dsa_platform_data *d) __init; -+ -+#endif /* _AR71XX_DEV_DSA_H */ -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/dev-gpio-buttons.c linux-2.6.36/arch/mips/ar71xx/dev-gpio-buttons.c ---- linux-2.6.36.orig/arch/mips/ar71xx/dev-gpio-buttons.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/dev-gpio-buttons.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,58 @@ -+/* -+ * Atheros AR71xx GPIO button support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include "linux/init.h" -+#include -+ -+#include "dev-gpio-buttons.h" -+ -+void __init ar71xx_add_device_gpio_buttons(int id, -+ unsigned poll_interval, -+ unsigned nbuttons, -+ struct gpio_button *buttons) -+{ -+ struct platform_device *pdev; -+ struct gpio_buttons_platform_data pdata; -+ struct gpio_button *p; -+ int err; -+ -+ p = kmalloc(nbuttons * sizeof(*p), GFP_KERNEL); -+ if (!p) -+ return; -+ -+ memcpy(p, buttons, nbuttons * sizeof(*p)); -+ -+ pdev = platform_device_alloc("gpio-buttons", id); -+ if (!pdev) -+ goto err_free_buttons; -+ -+ memset(&pdata, 0, sizeof(pdata)); -+ pdata.poll_interval = poll_interval; -+ pdata.nbuttons = nbuttons; -+ pdata.buttons = p; -+ -+ err = platform_device_add_data(pdev, &pdata, sizeof(pdata)); -+ if (err) -+ goto err_put_pdev; -+ -+ -+ err = platform_device_add(pdev); -+ if (err) -+ goto err_put_pdev; -+ -+ return; -+ -+err_put_pdev: -+ platform_device_put(pdev); -+ -+err_free_buttons: -+ kfree(p); -+} -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/dev-gpio-buttons.h linux-2.6.36/arch/mips/ar71xx/dev-gpio-buttons.h ---- linux-2.6.36.orig/arch/mips/ar71xx/dev-gpio-buttons.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/dev-gpio-buttons.h 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,25 @@ -+/* -+ * Atheros AR71xx GPIO button support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_DEV_GPIO_BUTTONS_H -+#define _AR71XX_DEV_GPIO_BUTTONS_H -+ -+#include -+#include -+ -+#include -+ -+void ar71xx_add_device_gpio_buttons(int id, -+ unsigned poll_interval, -+ unsigned nbuttons, -+ struct gpio_button *buttons) __init; -+ -+#endif /* _AR71XX_DEV_GPIO_BUTTONS_H */ -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/dev-leds-gpio.c linux-2.6.36/arch/mips/ar71xx/dev-leds-gpio.c ---- linux-2.6.36.orig/arch/mips/ar71xx/dev-leds-gpio.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/dev-leds-gpio.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,57 @@ -+/* -+ * Atheros AR71xx GPIO LED device support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+ -+#include "dev-leds-gpio.h" -+ -+void __init ar71xx_add_device_leds_gpio(int id, unsigned num_leds, -+ struct gpio_led *leds) -+{ -+ struct platform_device *pdev; -+ struct gpio_led_platform_data pdata; -+ struct gpio_led *p; -+ int err; -+ -+ p = kmalloc(num_leds * sizeof(*p), GFP_KERNEL); -+ if (!p) -+ return; -+ -+ memcpy(p, leds, num_leds * sizeof(*p)); -+ -+ pdev = platform_device_alloc("leds-gpio", id); -+ if (!pdev) -+ goto err_free_leds; -+ -+ memset(&pdata, 0, sizeof(pdata)); -+ pdata.num_leds = num_leds; -+ pdata.leds = p; -+ -+ err = platform_device_add_data(pdev, &pdata, sizeof(pdata)); -+ if (err) -+ goto err_put_pdev; -+ -+ err = platform_device_add(pdev); -+ if (err) -+ goto err_put_pdev; -+ -+ return; -+ -+err_put_pdev: -+ platform_device_put(pdev); -+ -+err_free_leds: -+ kfree(p); -+} -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/dev-leds-gpio.h linux-2.6.36/arch/mips/ar71xx/dev-leds-gpio.h ---- linux-2.6.36.orig/arch/mips/ar71xx/dev-leds-gpio.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/dev-leds-gpio.h 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,21 @@ -+/* -+ * Atheros AR71xx GPIO LED device support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_DEV_LEDS_GPIO_H -+#define _AR71XX_DEV_LEDS_GPIO_H -+ -+#include -+ -+void ar71xx_add_device_leds_gpio(int id, -+ unsigned num_leds, -+ struct gpio_led *leds) __init; -+ -+#endif /* _AR71XX_DEV_LEDS_GPIO_H */ -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/dev-m25p80.c linux-2.6.36/arch/mips/ar71xx/dev-m25p80.c ---- linux-2.6.36.orig/arch/mips/ar71xx/dev-m25p80.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/dev-m25p80.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,30 @@ -+/* -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+ -+#include "devices.h" -+#include "dev-m25p80.h" -+ -+static struct spi_board_info ar71xx_spi_info[] = { -+ { -+ .bus_num = 0, -+ .chip_select = 0, -+ .max_speed_hz = 25000000, -+ .modalias = "m25p80", -+ } -+}; -+ -+void __init ar71xx_add_device_m25p80(struct flash_platform_data *pdata) -+{ -+ ar71xx_spi_info[0].platform_data = pdata; -+ ar71xx_add_device_spi(NULL, ar71xx_spi_info, -+ ARRAY_SIZE(ar71xx_spi_info)); -+} -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/dev-m25p80.h linux-2.6.36/arch/mips/ar71xx/dev-m25p80.h ---- linux-2.6.36.orig/arch/mips/ar71xx/dev-m25p80.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/dev-m25p80.h 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,16 @@ -+/* -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_DEV_M25P80_H -+#define _AR71XX_DEV_M25P80_H -+ -+#include -+ -+void ar71xx_add_device_m25p80(struct flash_platform_data *pdata) __init; -+ -+#endif /* _AR71XX_DEV_M25P80_H */ -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/dev-pb42-pci.c linux-2.6.36/arch/mips/ar71xx/dev-pb42-pci.c ---- linux-2.6.36.orig/arch/mips/ar71xx/dev-pb42-pci.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/dev-pb42-pci.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,40 @@ -+/* -+ * Atheros PB42 reference board PCI initialization -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+ -+#include -+#include -+ -+#include "dev-pb42-pci.h" -+ -+static struct ar71xx_pci_irq pb42_pci_irqs[] __initdata = { -+ { -+ .slot = 0, -+ .pin = 1, -+ .irq = AR71XX_PCI_IRQ_DEV0, -+ }, { -+ .slot = 1, -+ .pin = 1, -+ .irq = AR71XX_PCI_IRQ_DEV1, -+ }, { -+ .slot = 2, -+ .pin = 1, -+ .irq = AR71XX_PCI_IRQ_DEV2, -+ } -+}; -+ -+void __init pb42_pci_init(void) -+{ -+ ar71xx_pci_init(ARRAY_SIZE(pb42_pci_irqs), pb42_pci_irqs); -+} -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/dev-pb42-pci.h linux-2.6.36/arch/mips/ar71xx/dev-pb42-pci.h ---- linux-2.6.36.orig/arch/mips/ar71xx/dev-pb42-pci.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/dev-pb42-pci.h 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,21 @@ -+/* -+ * Atheros PB42 reference board PCI initialization -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_DEV_PB42_PCI_H -+#define _AR71XX_DEV_PB42_PCI_H -+ -+#if defined(CONFIG_AR71XX_DEV_PB42_PCI) -+void pb42_pci_init(void) __init; -+#else -+static inline void pb42_pci_init(void) { } -+#endif -+ -+#endif /* _AR71XX_DEV_PB42_PCI_H */ -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/dev-pb9x-pci.c linux-2.6.36/arch/mips/ar71xx/dev-pb9x-pci.c ---- linux-2.6.36.orig/arch/mips/ar71xx/dev-pb9x-pci.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/dev-pb9x-pci.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,33 @@ -+/* -+ * Atheros PB9x reference board PCI initialization -+ * -+ * Copyright (C) 2010 Felix Fietkau -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+ -+#include -+#include -+ -+#include "dev-pb9x-pci.h" -+ -+static struct ar71xx_pci_irq pb9x_pci_irqs[] __initdata = { -+ { -+ .slot = 0, -+ .pin = 1, -+ .irq = AR71XX_PCI_IRQ_DEV0, -+ } -+}; -+ -+void __init pb9x_pci_init(void) -+{ -+ ar71xx_pci_init(ARRAY_SIZE(pb9x_pci_irqs), pb9x_pci_irqs); -+} -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/dev-pb9x-pci.h linux-2.6.36/arch/mips/ar71xx/dev-pb9x-pci.h ---- linux-2.6.36.orig/arch/mips/ar71xx/dev-pb9x-pci.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/dev-pb9x-pci.h 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,22 @@ -+/* -+ * Atheros PB9x reference board PCI initialization -+ * -+ * Copyright (C) 2010 Felix Fietkau -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_DEV_PB9X_PCI_H -+#define _AR71XX_DEV_PB9X_PCI_H -+ -+#if defined(CONFIG_AR71XX_DEV_PB9X_PCI) -+void pb9x_pci_init(void) __init; -+#else -+static inline void pb9x_pci_init(void) { } -+#endif -+ -+#endif /* _AR71XX_DEV_PB9X_PCI_H */ -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/dev-usb.c linux-2.6.36/arch/mips/ar71xx/dev-usb.c ---- linux-2.6.36.orig/arch/mips/ar71xx/dev-usb.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/dev-usb.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,181 @@ -+/* -+ * Atheros AR71xx USB host device support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include "dev-usb.h" -+ -+/* -+ * OHCI (USB full speed host controller) -+ */ -+static struct resource ar71xx_ohci_resources[] = { -+ [0] = { -+ .start = AR71XX_OHCI_BASE, -+ .end = AR71XX_OHCI_BASE + AR71XX_OHCI_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+ [1] = { -+ .start = AR71XX_MISC_IRQ_OHCI, -+ .end = AR71XX_MISC_IRQ_OHCI, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct resource ar7240_ohci_resources[] = { -+ [0] = { -+ .start = AR7240_OHCI_BASE, -+ .end = AR7240_OHCI_BASE + AR7240_OHCI_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+ [1] = { -+ .start = AR71XX_CPU_IRQ_USB, -+ .end = AR71XX_CPU_IRQ_USB, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static u64 ar71xx_ohci_dmamask = DMA_BIT_MASK(32); -+static struct platform_device ar71xx_ohci_device = { -+ .name = "ar71xx-ohci", -+ .id = -1, -+ .resource = ar71xx_ohci_resources, -+ .num_resources = ARRAY_SIZE(ar71xx_ohci_resources), -+ .dev = { -+ .dma_mask = &ar71xx_ohci_dmamask, -+ .coherent_dma_mask = DMA_BIT_MASK(32), -+ }, -+}; -+ -+/* -+ * EHCI (USB full speed host controller) -+ */ -+static struct resource ar71xx_ehci_resources[] = { -+ [0] = { -+ .start = AR71XX_EHCI_BASE, -+ .end = AR71XX_EHCI_BASE + AR71XX_EHCI_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+ [1] = { -+ .start = AR71XX_CPU_IRQ_USB, -+ .end = AR71XX_CPU_IRQ_USB, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static u64 ar71xx_ehci_dmamask = DMA_BIT_MASK(32); -+static struct ar71xx_ehci_platform_data ar71xx_ehci_data; -+ -+static struct platform_device ar71xx_ehci_device = { -+ .name = "ar71xx-ehci", -+ .id = -1, -+ .resource = ar71xx_ehci_resources, -+ .num_resources = ARRAY_SIZE(ar71xx_ehci_resources), -+ .dev = { -+ .dma_mask = &ar71xx_ehci_dmamask, -+ .coherent_dma_mask = DMA_BIT_MASK(32), -+ .platform_data = &ar71xx_ehci_data, -+ }, -+}; -+ -+#define AR71XX_USB_RESET_MASK \ -+ (RESET_MODULE_USB_HOST | RESET_MODULE_USB_PHY \ -+ | RESET_MODULE_USB_OHCI_DLL) -+ -+#define AR7240_USB_RESET_MASK \ -+ (RESET_MODULE_USB_HOST | RESET_MODULE_USB_OHCI_DLL_7240) -+ -+static void __init ar71xx_usb_setup(void) -+{ -+ ar71xx_device_stop(AR71XX_USB_RESET_MASK); -+ mdelay(1000); -+ ar71xx_device_start(AR71XX_USB_RESET_MASK); -+ -+ /* Turning on the Buff and Desc swap bits */ -+ ar71xx_usb_ctrl_wr(USB_CTRL_REG_CONFIG, 0xf0000); -+ -+ /* WAR for HW bug. Here it adjusts the duration between two SOFS */ -+ ar71xx_usb_ctrl_wr(USB_CTRL_REG_FLADJ, 0x20c00); -+ -+ mdelay(900); -+ -+ platform_device_register(&ar71xx_ohci_device); -+ platform_device_register(&ar71xx_ehci_device); -+} -+ -+static void __init ar7240_usb_setup(void) -+{ -+ ar71xx_device_stop(AR7240_USB_RESET_MASK); -+ mdelay(1000); -+ ar71xx_device_start(AR7240_USB_RESET_MASK); -+ -+ /* WAR for HW bug. Here it adjusts the duration between two SOFS */ -+ ar71xx_usb_ctrl_wr(USB_CTRL_REG_FLADJ, 0x3); -+ -+ if (ar71xx_soc == AR71XX_SOC_AR7241 || ar71xx_soc == AR71XX_SOC_AR7242) { -+ ar71xx_ehci_data.is_ar91xx = 1; -+ ar71xx_ehci_device.resource = ar7240_ohci_resources; -+ ar71xx_ehci_device.num_resources = ARRAY_SIZE(ar7240_ohci_resources); -+ platform_device_register(&ar71xx_ehci_device); -+ } else { -+ ar71xx_ohci_device.resource = ar7240_ohci_resources; -+ ar71xx_ohci_device.num_resources = ARRAY_SIZE(ar7240_ohci_resources); -+ platform_device_register(&ar71xx_ohci_device); -+ } -+} -+ -+static void __init ar91xx_usb_setup(void) -+{ -+ ar71xx_device_stop(RESET_MODULE_USBSUS_OVERRIDE); -+ mdelay(10); -+ -+ ar71xx_device_start(RESET_MODULE_USB_HOST); -+ mdelay(10); -+ -+ ar71xx_device_start(RESET_MODULE_USB_PHY); -+ mdelay(10); -+ -+ ar71xx_ehci_data.is_ar91xx = 1; -+ platform_device_register(&ar71xx_ehci_device); -+} -+ -+void __init ar71xx_add_device_usb(void) -+{ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7240: -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ ar7240_usb_setup(); -+ break; -+ -+ case AR71XX_SOC_AR7130: -+ case AR71XX_SOC_AR7141: -+ case AR71XX_SOC_AR7161: -+ ar71xx_usb_setup(); -+ break; -+ -+ case AR71XX_SOC_AR9130: -+ case AR71XX_SOC_AR9132: -+ ar91xx_usb_setup(); -+ break; -+ -+ default: -+ BUG(); -+ } -+} -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/dev-usb.h linux-2.6.36/arch/mips/ar71xx/dev-usb.h ---- linux-2.6.36.orig/arch/mips/ar71xx/dev-usb.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/dev-usb.h 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,17 @@ -+/* -+ * Atheros AR71xx USB host device support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_DEV_USB_H -+#define _AR71XX_DEV_USB_H -+ -+void ar71xx_add_device_usb(void) __init; -+ -+#endif /* _AR71XX_DEV_USB_H */ -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/devices.c linux-2.6.36/arch/mips/ar71xx/devices.c ---- linux-2.6.36.orig/arch/mips/ar71xx/devices.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/devices.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,575 @@ -+/* -+ * Atheros AR71xx SoC platform devices -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "devices.h" -+ -+static u8 ar71xx_mac_base[ETH_ALEN] __initdata; -+ -+static struct resource ar71xx_uart_resources[] = { -+ { -+ .start = AR71XX_UART_BASE, -+ .end = AR71XX_UART_BASE + AR71XX_UART_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+}; -+ -+#define AR71XX_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP) -+static struct plat_serial8250_port ar71xx_uart_data[] = { -+ { -+ .mapbase = AR71XX_UART_BASE, -+ .irq = AR71XX_MISC_IRQ_UART, -+ .flags = AR71XX_UART_FLAGS, -+ .iotype = UPIO_MEM32, -+ .regshift = 2, -+ }, { -+ /* terminating entry */ -+ } -+}; -+ -+static struct platform_device ar71xx_uart_device = { -+ .name = "serial8250", -+ .id = PLAT8250_DEV_PLATFORM, -+ .resource = ar71xx_uart_resources, -+ .num_resources = ARRAY_SIZE(ar71xx_uart_resources), -+ .dev = { -+ .platform_data = ar71xx_uart_data -+ }, -+}; -+ -+void __init ar71xx_add_device_uart(void) -+{ -+ ar71xx_uart_data[0].uartclk = ar71xx_ahb_freq; -+ platform_device_register(&ar71xx_uart_device); -+} -+ -+static struct resource ar71xx_mdio_resources[] = { -+ { -+ .name = "mdio_base", -+ .flags = IORESOURCE_MEM, -+ .start = AR71XX_GE0_BASE, -+ .end = AR71XX_GE0_BASE + 0x200 - 1, -+ } -+}; -+ -+static struct ag71xx_mdio_platform_data ar71xx_mdio_data; -+ -+struct platform_device ar71xx_mdio_device = { -+ .name = "ag71xx-mdio", -+ .id = -1, -+ .resource = ar71xx_mdio_resources, -+ .num_resources = ARRAY_SIZE(ar71xx_mdio_resources), -+ .dev = { -+ .platform_data = &ar71xx_mdio_data, -+ }, -+}; -+ -+void __init ar71xx_add_device_mdio(u32 phy_mask) -+{ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7240: -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ ar71xx_mdio_data.is_ar7240 = 1; -+ break; -+ default: -+ break; -+ } -+ -+ ar71xx_mdio_data.phy_mask = phy_mask; -+ -+ platform_device_register(&ar71xx_mdio_device); -+} -+ -+static void ar71xx_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift) -+{ -+ void __iomem *base; -+ u32 t; -+ -+ base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE); -+ -+ t = __raw_readl(base + cfg_reg); -+ t &= ~(3 << shift); -+ t |= (2 << shift); -+ __raw_writel(t, base + cfg_reg); -+ udelay(100); -+ -+ __raw_writel(pll_val, base + pll_reg); -+ -+ t |= (3 << shift); -+ __raw_writel(t, base + cfg_reg); -+ udelay(100); -+ -+ t &= ~(3 << shift); -+ __raw_writel(t, base + cfg_reg); -+ udelay(100); -+ -+ printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n", -+ (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg)); -+ -+ iounmap(base); -+} -+ -+struct ar71xx_eth_pll_data ar71xx_eth0_pll_data; -+struct ar71xx_eth_pll_data ar71xx_eth1_pll_data; -+ -+static u32 ar71xx_get_eth_pll(unsigned int mac, int speed) -+{ -+ struct ar71xx_eth_pll_data *pll_data; -+ u32 pll_val; -+ -+ switch (mac) { -+ case 0: -+ pll_data = &ar71xx_eth0_pll_data; -+ break; -+ case 1: -+ pll_data = &ar71xx_eth1_pll_data; -+ break; -+ default: -+ BUG(); -+ } -+ -+ switch (speed) { -+ case SPEED_10: -+ pll_val = pll_data->pll_10; -+ break; -+ case SPEED_100: -+ pll_val = pll_data->pll_100; -+ break; -+ case SPEED_1000: -+ pll_val = pll_data->pll_1000; -+ break; -+ default: -+ BUG(); -+ } -+ -+ return pll_val; -+} -+ -+static void ar71xx_set_pll_ge0(int speed) -+{ -+ u32 val = ar71xx_get_eth_pll(0, speed); -+ -+ ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK, -+ val, AR71XX_ETH0_PLL_SHIFT); -+} -+ -+static void ar71xx_set_pll_ge1(int speed) -+{ -+ u32 val = ar71xx_get_eth_pll(1, speed); -+ -+ ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK, -+ val, AR71XX_ETH1_PLL_SHIFT); -+} -+ -+static void ar724x_set_pll_ge0(int speed) -+{ -+ /* TODO */ -+} -+ -+static void ar724x_set_pll_ge1(int speed) -+{ -+ /* TODO */ -+} -+ -+static void ar91xx_set_pll_ge0(int speed) -+{ -+ u32 val = ar71xx_get_eth_pll(0, speed); -+ -+ ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH0_INT_CLOCK, -+ val, AR91XX_ETH0_PLL_SHIFT); -+} -+ -+static void ar91xx_set_pll_ge1(int speed) -+{ -+ u32 val = ar71xx_get_eth_pll(1, speed); -+ -+ ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH1_INT_CLOCK, -+ val, AR91XX_ETH1_PLL_SHIFT); -+} -+ -+static void ar71xx_ddr_flush_ge0(void) -+{ -+ ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE0); -+} -+ -+static void ar71xx_ddr_flush_ge1(void) -+{ -+ ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE1); -+} -+ -+static void ar724x_ddr_flush_ge0(void) -+{ -+ ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE0); -+} -+ -+static void ar724x_ddr_flush_ge1(void) -+{ -+ ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE1); -+} -+ -+static void ar91xx_ddr_flush_ge0(void) -+{ -+ ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0); -+} -+ -+static void ar91xx_ddr_flush_ge1(void) -+{ -+ ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE1); -+} -+ -+static struct resource ar71xx_eth0_resources[] = { -+ { -+ .name = "mac_base", -+ .flags = IORESOURCE_MEM, -+ .start = AR71XX_GE0_BASE, -+ .end = AR71XX_GE0_BASE + 0x200 - 1, -+ }, { -+ .name = "mii_ctrl", -+ .flags = IORESOURCE_MEM, -+ .start = AR71XX_MII_BASE + MII_REG_MII0_CTRL, -+ .end = AR71XX_MII_BASE + MII_REG_MII0_CTRL + 3, -+ }, { -+ .name = "mac_irq", -+ .flags = IORESOURCE_IRQ, -+ .start = AR71XX_CPU_IRQ_GE0, -+ .end = AR71XX_CPU_IRQ_GE0, -+ }, -+}; -+ -+struct ag71xx_platform_data ar71xx_eth0_data = { -+ .reset_bit = RESET_MODULE_GE0_MAC, -+}; -+ -+struct platform_device ar71xx_eth0_device = { -+ .name = "ag71xx", -+ .id = 0, -+ .resource = ar71xx_eth0_resources, -+ .num_resources = ARRAY_SIZE(ar71xx_eth0_resources), -+ .dev = { -+ .platform_data = &ar71xx_eth0_data, -+ }, -+}; -+ -+static struct resource ar71xx_eth1_resources[] = { -+ { -+ .name = "mac_base", -+ .flags = IORESOURCE_MEM, -+ .start = AR71XX_GE1_BASE, -+ .end = AR71XX_GE1_BASE + 0x200 - 1, -+ }, { -+ .name = "mii_ctrl", -+ .flags = IORESOURCE_MEM, -+ .start = AR71XX_MII_BASE + MII_REG_MII1_CTRL, -+ .end = AR71XX_MII_BASE + MII_REG_MII1_CTRL + 3, -+ }, { -+ .name = "mac_irq", -+ .flags = IORESOURCE_IRQ, -+ .start = AR71XX_CPU_IRQ_GE1, -+ .end = AR71XX_CPU_IRQ_GE1, -+ }, -+}; -+ -+struct ag71xx_platform_data ar71xx_eth1_data = { -+ .reset_bit = RESET_MODULE_GE1_MAC, -+}; -+ -+struct platform_device ar71xx_eth1_device = { -+ .name = "ag71xx", -+ .id = 1, -+ .resource = ar71xx_eth1_resources, -+ .num_resources = ARRAY_SIZE(ar71xx_eth1_resources), -+ .dev = { -+ .platform_data = &ar71xx_eth1_data, -+ }, -+}; -+ -+#define AR71XX_PLL_VAL_1000 0x00110000 -+#define AR71XX_PLL_VAL_100 0x00001099 -+#define AR71XX_PLL_VAL_10 0x00991099 -+ -+#define AR724X_PLL_VAL_1000 0x00110000 -+#define AR724X_PLL_VAL_100 0x00001099 -+#define AR724X_PLL_VAL_10 0x00991099 -+ -+#define AR91XX_PLL_VAL_1000 0x1a000000 -+#define AR91XX_PLL_VAL_100 0x13000a44 -+#define AR91XX_PLL_VAL_10 0x00441099 -+ -+static void __init ar71xx_init_eth_pll_data(unsigned int id) -+{ -+ struct ar71xx_eth_pll_data *pll_data; -+ u32 pll_10, pll_100, pll_1000; -+ -+ switch (id) { -+ case 0: -+ pll_data = &ar71xx_eth0_pll_data; -+ break; -+ case 1: -+ pll_data = &ar71xx_eth1_pll_data; -+ break; -+ default: -+ BUG(); -+ } -+ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7130: -+ case AR71XX_SOC_AR7141: -+ case AR71XX_SOC_AR7161: -+ pll_10 = AR71XX_PLL_VAL_10; -+ pll_100 = AR71XX_PLL_VAL_100; -+ pll_1000 = AR71XX_PLL_VAL_1000; -+ break; -+ -+ case AR71XX_SOC_AR7240: -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ pll_10 = AR724X_PLL_VAL_10; -+ pll_100 = AR724X_PLL_VAL_100; -+ pll_1000 = AR724X_PLL_VAL_1000; -+ break; -+ -+ case AR71XX_SOC_AR9130: -+ case AR71XX_SOC_AR9132: -+ pll_10 = AR91XX_PLL_VAL_10; -+ pll_100 = AR91XX_PLL_VAL_100; -+ pll_1000 = AR91XX_PLL_VAL_1000; -+ break; -+ default: -+ BUG(); -+ } -+ -+ if (!pll_data->pll_10) -+ pll_data->pll_10 = pll_10; -+ -+ if (!pll_data->pll_100) -+ pll_data->pll_100 = pll_100; -+ -+ if (!pll_data->pll_1000) -+ pll_data->pll_1000 = pll_1000; -+} -+ -+static int ar71xx_eth_instance __initdata; -+void __init ar71xx_add_device_eth(unsigned int id) -+{ -+ struct platform_device *pdev; -+ struct ag71xx_platform_data *pdata; -+ -+ ar71xx_init_eth_pll_data(id); -+ -+ switch (id) { -+ case 0: -+ switch (ar71xx_eth0_data.phy_if_mode) { -+ case PHY_INTERFACE_MODE_MII: -+ ar71xx_eth0_data.mii_if = MII0_CTRL_IF_MII; -+ break; -+ case PHY_INTERFACE_MODE_GMII: -+ ar71xx_eth0_data.mii_if = MII0_CTRL_IF_GMII; -+ break; -+ case PHY_INTERFACE_MODE_RGMII: -+ ar71xx_eth0_data.mii_if = MII0_CTRL_IF_RGMII; -+ break; -+ case PHY_INTERFACE_MODE_RMII: -+ ar71xx_eth0_data.mii_if = MII0_CTRL_IF_RMII; -+ break; -+ default: -+ printk(KERN_ERR "ar71xx: invalid PHY interface mode " -+ "for eth0\n"); -+ return; -+ } -+ pdev = &ar71xx_eth0_device; -+ break; -+ case 1: -+ switch (ar71xx_eth1_data.phy_if_mode) { -+ case PHY_INTERFACE_MODE_RMII: -+ ar71xx_eth1_data.mii_if = MII1_CTRL_IF_RMII; -+ break; -+ case PHY_INTERFACE_MODE_RGMII: -+ ar71xx_eth1_data.mii_if = MII1_CTRL_IF_RGMII; -+ break; -+ default: -+ printk(KERN_ERR "ar71xx: invalid PHY interface mode " -+ "for eth1\n"); -+ return; -+ } -+ pdev = &ar71xx_eth1_device; -+ break; -+ default: -+ printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id); -+ return; -+ } -+ -+ pdata = pdev->dev.platform_data; -+ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7130: -+ pdata->ddr_flush = id ? ar71xx_ddr_flush_ge1 -+ : ar71xx_ddr_flush_ge0; -+ pdata->set_pll = id ? ar71xx_set_pll_ge1 -+ : ar71xx_set_pll_ge0; -+ break; -+ -+ case AR71XX_SOC_AR7141: -+ case AR71XX_SOC_AR7161: -+ pdata->ddr_flush = id ? ar71xx_ddr_flush_ge1 -+ : ar71xx_ddr_flush_ge0; -+ pdata->set_pll = id ? ar71xx_set_pll_ge1 -+ : ar71xx_set_pll_ge0; -+ pdata->has_gbit = 1; -+ break; -+ -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ ar71xx_eth0_data.reset_bit |= AR724X_RESET_GE0_MDIO; -+ ar71xx_eth1_data.reset_bit |= AR724X_RESET_GE1_MDIO; -+ /* fall through */ -+ case AR71XX_SOC_AR7240: -+ pdata->ddr_flush = id ? ar724x_ddr_flush_ge1 -+ : ar724x_ddr_flush_ge0; -+ pdata->set_pll = id ? ar724x_set_pll_ge1 -+ : ar724x_set_pll_ge0; -+ pdata->is_ar724x = 1; -+ break; -+ -+ case AR71XX_SOC_AR9130: -+ pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1 -+ : ar91xx_ddr_flush_ge0; -+ pdata->set_pll = id ? ar91xx_set_pll_ge1 -+ : ar91xx_set_pll_ge0; -+ pdata->is_ar91xx = 1; -+ break; -+ -+ case AR71XX_SOC_AR9132: -+ pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1 -+ : ar91xx_ddr_flush_ge0; -+ pdata->set_pll = id ? ar91xx_set_pll_ge1 -+ : ar91xx_set_pll_ge0; -+ pdata->is_ar91xx = 1; -+ pdata->has_gbit = 1; -+ break; -+ -+ default: -+ BUG(); -+ } -+ -+ switch (pdata->phy_if_mode) { -+ case PHY_INTERFACE_MODE_GMII: -+ case PHY_INTERFACE_MODE_RGMII: -+ if (!pdata->has_gbit) { -+ printk(KERN_ERR "ar71xx: no gbit available on eth%d\n", -+ id); -+ return; -+ } -+ /* fallthrough */ -+ default: -+ break; -+ } -+ -+ if (is_valid_ether_addr(ar71xx_mac_base)) { -+ memcpy(pdata->mac_addr, ar71xx_mac_base, ETH_ALEN); -+ pdata->mac_addr[5] += ar71xx_eth_instance; -+ } else { -+ random_ether_addr(pdata->mac_addr); -+ printk(KERN_DEBUG -+ "ar71xx: using random MAC address for eth%d\n", -+ ar71xx_eth_instance); -+ } -+ -+ if (pdata->mii_bus_dev == NULL) -+ pdata->mii_bus_dev = &ar71xx_mdio_device.dev; -+ -+ /* Reset the device */ -+ ar71xx_device_stop(pdata->reset_bit); -+ mdelay(100); -+ -+ ar71xx_device_start(pdata->reset_bit); -+ mdelay(100); -+ -+ platform_device_register(pdev); -+ ar71xx_eth_instance++; -+} -+ -+static struct resource ar71xx_spi_resources[] = { -+ [0] = { -+ .start = AR71XX_SPI_BASE, -+ .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+}; -+ -+static struct platform_device ar71xx_spi_device = { -+ .name = "ar71xx-spi", -+ .id = -1, -+ .resource = ar71xx_spi_resources, -+ .num_resources = ARRAY_SIZE(ar71xx_spi_resources), -+}; -+ -+void __init ar71xx_add_device_spi(struct ar71xx_spi_platform_data *pdata, -+ struct spi_board_info const *info, -+ unsigned n) -+{ -+ spi_register_board_info(info, n); -+ ar71xx_spi_device.dev.platform_data = pdata; -+ platform_device_register(&ar71xx_spi_device); -+} -+ -+void __init ar71xx_add_device_wdt(void) -+{ -+ platform_device_register_simple("ar71xx-wdt", -1, NULL, 0); -+} -+ -+void __init ar71xx_set_mac_base(unsigned char *mac) -+{ -+ memcpy(ar71xx_mac_base, mac, ETH_ALEN); -+} -+ -+void __init ar71xx_parse_mac_addr(char *mac_str) -+{ -+ u8 tmp[ETH_ALEN]; -+ int t; -+ -+ t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", -+ &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]); -+ -+ if (t != ETH_ALEN) -+ t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx", -+ &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]); -+ -+ if (t == ETH_ALEN) -+ ar71xx_set_mac_base(tmp); -+ else -+ printk(KERN_DEBUG "ar71xx: failed to parse mac address " -+ "\"%s\"\n", mac_str); -+} -+ -+static int __init ar71xx_ethaddr_setup(char *str) -+{ -+ ar71xx_parse_mac_addr(str); -+ return 1; -+} -+__setup("ethaddr=", ar71xx_ethaddr_setup); -+ -+static int __init ar71xx_kmac_setup(char *str) -+{ -+ ar71xx_parse_mac_addr(str); -+ return 1; -+} -+__setup("kmac=", ar71xx_kmac_setup); -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/devices.h linux-2.6.36/arch/mips/ar71xx/devices.h ---- linux-2.6.36.orig/arch/mips/ar71xx/devices.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/devices.h 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,48 @@ -+/* -+ * Atheros AR71xx SoC device definitions -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef __AR71XX_DEVICES_H -+#define __AR71XX_DEVICES_H -+ -+#include -+ -+struct platform_device; -+ -+void ar71xx_add_device_spi(struct ar71xx_spi_platform_data *pdata, -+ struct spi_board_info const *info, -+ unsigned n) __init; -+ -+void ar71xx_set_mac_base(unsigned char *mac) __init; -+void ar71xx_parse_mac_addr(char *mac_str) __init; -+ -+struct ar71xx_eth_pll_data { -+ u32 pll_10; -+ u32 pll_100; -+ u32 pll_1000; -+}; -+ -+extern struct ar71xx_eth_pll_data ar71xx_eth0_pll_data; -+extern struct ar71xx_eth_pll_data ar71xx_eth1_pll_data; -+ -+extern struct ag71xx_platform_data ar71xx_eth0_data; -+extern struct ag71xx_platform_data ar71xx_eth1_data; -+extern struct platform_device ar71xx_eth0_device; -+extern struct platform_device ar71xx_eth1_device; -+void ar71xx_add_device_eth(unsigned int id) __init; -+ -+extern struct platform_device ar71xx_mdio_device; -+void ar71xx_add_device_mdio(u32 phy_mask) __init; -+ -+void ar71xx_add_device_uart(void) __init; -+ -+void ar71xx_add_device_wdt(void) __init; -+ -+#endif /* __AR71XX_DEVICES_H */ -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/early_printk.c linux-2.6.36/arch/mips/ar71xx/early_printk.c ---- linux-2.6.36.orig/arch/mips/ar71xx/early_printk.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/early_printk.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,30 @@ -+/* -+ * Atheros AR71xx SoC early printk support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+ -+#include -+ -+#define UART_READ(r) \ -+ __raw_readl((void __iomem *)(KSEG1ADDR(AR71XX_UART_BASE) + 4 * (r))) -+ -+#define UART_WRITE(r, v) \ -+ __raw_writel((v), (void __iomem *)(KSEG1ADDR(AR71XX_UART_BASE) + 4*(r))) -+ -+void prom_putchar(unsigned char ch) -+{ -+ while (((UART_READ(UART_LSR)) & UART_LSR_THRE) == 0); -+ UART_WRITE(UART_TX, ch); -+ while (((UART_READ(UART_LSR)) & UART_LSR_THRE) == 0); -+} -+ -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/gpio.c linux-2.6.36/arch/mips/ar71xx/gpio.c ---- linux-2.6.36.orig/arch/mips/ar71xx/gpio.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/gpio.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,182 @@ -+/* -+ * Atheros AR71xx SoC GPIO API support -+ * -+ * Copyright (C) 2008-2010 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+static DEFINE_SPINLOCK(ar71xx_gpio_lock); -+ -+unsigned long ar71xx_gpio_count; -+EXPORT_SYMBOL(ar71xx_gpio_count); -+ -+void __ar71xx_gpio_set_value(unsigned gpio, int value) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ -+ if (value) -+ __raw_writel(1 << gpio, base + GPIO_REG_SET); -+ else -+ __raw_writel(1 << gpio, base + GPIO_REG_CLEAR); -+} -+EXPORT_SYMBOL(__ar71xx_gpio_set_value); -+ -+int __ar71xx_gpio_get_value(unsigned gpio) -+{ -+ return (__raw_readl(ar71xx_gpio_base + GPIO_REG_IN) >> gpio) & 1; -+} -+EXPORT_SYMBOL(__ar71xx_gpio_get_value); -+ -+static int ar71xx_gpio_get_value(struct gpio_chip *chip, unsigned offset) -+{ -+ return __ar71xx_gpio_get_value(offset); -+} -+ -+static void ar71xx_gpio_set_value(struct gpio_chip *chip, -+ unsigned offset, int value) -+{ -+ __ar71xx_gpio_set_value(offset, value); -+} -+ -+static int ar71xx_gpio_direction_input(struct gpio_chip *chip, -+ unsigned offset) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&ar71xx_gpio_lock, flags); -+ -+ __raw_writel(__raw_readl(base + GPIO_REG_OE) & ~(1 << offset), -+ base + GPIO_REG_OE); -+ -+ spin_unlock_irqrestore(&ar71xx_gpio_lock, flags); -+ -+ return 0; -+} -+ -+static int ar71xx_gpio_direction_output(struct gpio_chip *chip, -+ unsigned offset, int value) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&ar71xx_gpio_lock, flags); -+ -+ if (value) -+ __raw_writel(1 << offset, base + GPIO_REG_SET); -+ else -+ __raw_writel(1 << offset, base + GPIO_REG_CLEAR); -+ -+ __raw_writel(__raw_readl(base + GPIO_REG_OE) | (1 << offset), -+ base + GPIO_REG_OE); -+ -+ spin_unlock_irqrestore(&ar71xx_gpio_lock, flags); -+ -+ return 0; -+} -+ -+static struct gpio_chip ar71xx_gpio_chip = { -+ .label = "ar71xx", -+ .get = ar71xx_gpio_get_value, -+ .set = ar71xx_gpio_set_value, -+ .direction_input = ar71xx_gpio_direction_input, -+ .direction_output = ar71xx_gpio_direction_output, -+ .base = 0, -+ .ngpio = AR71XX_GPIO_COUNT, -+}; -+ -+void ar71xx_gpio_function_enable(u32 mask) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&ar71xx_gpio_lock, flags); -+ -+ __raw_writel(__raw_readl(base + GPIO_REG_FUNC) | mask, -+ base + GPIO_REG_FUNC); -+ /* flush write */ -+ (void) __raw_readl(base + GPIO_REG_FUNC); -+ -+ spin_unlock_irqrestore(&ar71xx_gpio_lock, flags); -+} -+ -+void ar71xx_gpio_function_disable(u32 mask) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&ar71xx_gpio_lock, flags); -+ -+ __raw_writel(__raw_readl(base + GPIO_REG_FUNC) & ~mask, -+ base + GPIO_REG_FUNC); -+ /* flush write */ -+ (void) __raw_readl(base + GPIO_REG_FUNC); -+ -+ spin_unlock_irqrestore(&ar71xx_gpio_lock, flags); -+} -+ -+void ar71xx_gpio_function_setup(u32 set, u32 clear) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&ar71xx_gpio_lock, flags); -+ -+ __raw_writel((__raw_readl(base + GPIO_REG_FUNC) & ~clear) | set, -+ base + GPIO_REG_FUNC); -+ /* flush write */ -+ (void) __raw_readl(base + GPIO_REG_FUNC); -+ -+ spin_unlock_irqrestore(&ar71xx_gpio_lock, flags); -+} -+EXPORT_SYMBOL(ar71xx_gpio_function_setup); -+ -+void __init ar71xx_gpio_init(void) -+{ -+ int err; -+ -+ if (!request_mem_region(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE, -+ "AR71xx GPIO controller")) -+ panic("cannot allocate AR71xx GPIO registers page"); -+ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7130: -+ case AR71XX_SOC_AR7141: -+ case AR71XX_SOC_AR7161: -+ ar71xx_gpio_chip.ngpio = AR71XX_GPIO_COUNT; -+ break; -+ -+ case AR71XX_SOC_AR7240: -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ ar71xx_gpio_chip.ngpio = AR724X_GPIO_COUNT; -+ break; -+ -+ case AR71XX_SOC_AR9130: -+ case AR71XX_SOC_AR9132: -+ ar71xx_gpio_chip.ngpio = AR91XX_GPIO_COUNT; -+ break; -+ -+ default: -+ BUG(); -+ } -+ -+ err = gpiochip_add(&ar71xx_gpio_chip); -+ if (err) -+ panic("cannot add AR71xx GPIO chip, error=%d", err); -+} -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/irq.c linux-2.6.36/arch/mips/ar71xx/irq.c ---- linux-2.6.36.orig/arch/mips/ar71xx/irq.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/irq.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,295 @@ -+/* -+ * Atheros AR71xx SoC specific interrupt handling -+ * -+ * Copyright (C) 2008-2010 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include -+ -+static int ip2_flush_reg; -+ -+static void ar71xx_gpio_irq_dispatch(void) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ u32 pending; -+ -+ pending = __raw_readl(base + GPIO_REG_INT_PENDING) & -+ __raw_readl(base + GPIO_REG_INT_ENABLE); -+ -+ if (pending) -+ do_IRQ(AR71XX_GPIO_IRQ_BASE + fls(pending) - 1); -+ else -+ spurious_interrupt(); -+} -+ -+static void ar71xx_gpio_irq_unmask(unsigned int irq) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ u32 t; -+ -+ irq -= AR71XX_GPIO_IRQ_BASE; -+ -+ t = __raw_readl(base + GPIO_REG_INT_ENABLE); -+ __raw_writel(t | (1 << irq), base + GPIO_REG_INT_ENABLE); -+ -+ /* flush write */ -+ (void) __raw_readl(base + GPIO_REG_INT_ENABLE); -+} -+ -+static void ar71xx_gpio_irq_mask(unsigned int irq) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ u32 t; -+ -+ irq -= AR71XX_GPIO_IRQ_BASE; -+ -+ t = __raw_readl(base + GPIO_REG_INT_ENABLE); -+ __raw_writel(t & ~(1 << irq), base + GPIO_REG_INT_ENABLE); -+ -+ /* flush write */ -+ (void) __raw_readl(base + GPIO_REG_INT_ENABLE); -+} -+ -+#if 0 -+static int ar71xx_gpio_irq_set_type(unsigned int irq, unsigned int flow_type) -+{ -+ /* TODO: implement */ -+ return 0; -+} -+#else -+#define ar71xx_gpio_irq_set_type NULL -+#endif -+ -+static struct irq_chip ar71xx_gpio_irq_chip = { -+ .name = "AR71XX GPIO", -+ .unmask = ar71xx_gpio_irq_unmask, -+ .mask = ar71xx_gpio_irq_mask, -+ .mask_ack = ar71xx_gpio_irq_mask, -+ .set_type = ar71xx_gpio_irq_set_type, -+}; -+ -+static struct irqaction ar71xx_gpio_irqaction = { -+ .handler = no_action, -+ .name = "cascade [AR71XX GPIO]", -+}; -+ -+#define GPIO_IRQ_INIT_STATUS (IRQ_LEVEL | IRQ_TYPE_LEVEL_HIGH | IRQ_DISABLED) -+#define GPIO_INT_ALL 0xffff -+ -+static void __init ar71xx_gpio_irq_init(void) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ int i; -+ -+ __raw_writel(0, base + GPIO_REG_INT_ENABLE); -+ __raw_writel(0, base + GPIO_REG_INT_PENDING); -+ -+ /* setup type of all GPIO interrupts to level sensitive */ -+ __raw_writel(GPIO_INT_ALL, base + GPIO_REG_INT_TYPE); -+ -+ /* setup polarity of all GPIO interrupts to active high */ -+ __raw_writel(GPIO_INT_ALL, base + GPIO_REG_INT_POLARITY); -+ -+ for (i = AR71XX_GPIO_IRQ_BASE; -+ i < AR71XX_GPIO_IRQ_BASE + AR71XX_GPIO_IRQ_COUNT; i++) { -+ irq_desc[i].status = GPIO_IRQ_INIT_STATUS; -+ set_irq_chip_and_handler(i, &ar71xx_gpio_irq_chip, -+ handle_level_irq); -+ } -+ -+ setup_irq(AR71XX_MISC_IRQ_GPIO, &ar71xx_gpio_irqaction); -+} -+ -+static void ar71xx_misc_irq_dispatch(void) -+{ -+ u32 pending; -+ -+ pending = ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS) -+ & ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE); -+ -+ if (pending & MISC_INT_UART) -+ do_IRQ(AR71XX_MISC_IRQ_UART); -+ -+ else if (pending & MISC_INT_DMA) -+ do_IRQ(AR71XX_MISC_IRQ_DMA); -+ -+ else if (pending & MISC_INT_PERFC) -+ do_IRQ(AR71XX_MISC_IRQ_PERFC); -+ -+ else if (pending & MISC_INT_TIMER) -+ do_IRQ(AR71XX_MISC_IRQ_TIMER); -+ -+ else if (pending & MISC_INT_OHCI) -+ do_IRQ(AR71XX_MISC_IRQ_OHCI); -+ -+ else if (pending & MISC_INT_ERROR) -+ do_IRQ(AR71XX_MISC_IRQ_ERROR); -+ -+ else if (pending & MISC_INT_GPIO) -+ ar71xx_gpio_irq_dispatch(); -+ -+ else if (pending & MISC_INT_WDOG) -+ do_IRQ(AR71XX_MISC_IRQ_WDOG); -+ -+ else -+ spurious_interrupt(); -+} -+ -+static void ar71xx_misc_irq_unmask(unsigned int irq) -+{ -+ void __iomem *base = ar71xx_reset_base; -+ u32 t; -+ -+ irq -= AR71XX_MISC_IRQ_BASE; -+ -+ t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); -+ __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE); -+ -+ /* flush write */ -+ (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); -+} -+ -+static void ar71xx_misc_irq_mask(unsigned int irq) -+{ -+ void __iomem *base = ar71xx_reset_base; -+ u32 t; -+ -+ irq -= AR71XX_MISC_IRQ_BASE; -+ -+ t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); -+ __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE); -+ -+ /* flush write */ -+ (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); -+} -+ -+static void ar724x_misc_irq_ack(unsigned int irq) -+{ -+ void __iomem *base = ar71xx_reset_base; -+ u32 t; -+ -+ irq -= AR71XX_MISC_IRQ_BASE; -+ -+ t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS); -+ __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_STATUS); -+ -+ /* flush write */ -+ (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS); -+} -+ -+static struct irq_chip ar71xx_misc_irq_chip = { -+ .name = "AR71XX MISC", -+ .unmask = ar71xx_misc_irq_unmask, -+ .mask = ar71xx_misc_irq_mask, -+}; -+ -+static struct irqaction ar71xx_misc_irqaction = { -+ .handler = no_action, -+ .name = "cascade [AR71XX MISC]", -+}; -+ -+static void __init ar71xx_misc_irq_init(void) -+{ -+ void __iomem *base = ar71xx_reset_base; -+ int i; -+ -+ __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE); -+ __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS); -+ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7240: -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ ar71xx_misc_irq_chip.ack = ar724x_misc_irq_ack; -+ break; -+ default: -+ ar71xx_misc_irq_chip.mask_ack = ar71xx_misc_irq_mask; -+ break; -+ } -+ -+ for (i = AR71XX_MISC_IRQ_BASE; -+ i < AR71XX_MISC_IRQ_BASE + AR71XX_MISC_IRQ_COUNT; i++) { -+ irq_desc[i].status = IRQ_DISABLED; -+ set_irq_chip_and_handler(i, &ar71xx_misc_irq_chip, -+ handle_level_irq); -+ } -+ -+ setup_irq(AR71XX_CPU_IRQ_MISC, &ar71xx_misc_irqaction); -+} -+ -+asmlinkage void plat_irq_dispatch(void) -+{ -+ unsigned long pending; -+ -+ pending = read_c0_status() & read_c0_cause() & ST0_IM; -+ -+ if (pending & STATUSF_IP7) -+ do_IRQ(AR71XX_CPU_IRQ_TIMER); -+ -+ else if (pending & STATUSF_IP2) { -+ /* -+ * This IRQ is meant for a PCI device. Drivers for PCI devices -+ * typically allocate coherent DMA memory for the descriptor -+ * ring, however the DMA controller may still have some -+ * unsynchronized data in the FIFO. -+ * Issue a flush here to ensure that the driver sees the update. -+ */ -+ ar71xx_ddr_flush(ip2_flush_reg); -+ do_IRQ(AR71XX_CPU_IRQ_IP2); -+ } -+ -+ else if (pending & STATUSF_IP4) -+ do_IRQ(AR71XX_CPU_IRQ_GE0); -+ -+ else if (pending & STATUSF_IP5) -+ do_IRQ(AR71XX_CPU_IRQ_GE1); -+ -+ else if (pending & STATUSF_IP3) -+ do_IRQ(AR71XX_CPU_IRQ_USB); -+ -+ else if (pending & STATUSF_IP6) -+ ar71xx_misc_irq_dispatch(); -+ -+ else -+ spurious_interrupt(); -+} -+ -+void __init arch_init_irq(void) -+{ -+ switch(ar71xx_soc) { -+ case AR71XX_SOC_AR7240: -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ ip2_flush_reg = AR724X_DDR_REG_FLUSH_PCIE; -+ break; -+ case AR71XX_SOC_AR9130: -+ case AR71XX_SOC_AR9132: -+ ip2_flush_reg = AR91XX_DDR_REG_FLUSH_WMAC; -+ break; -+ default: -+ ip2_flush_reg = AR71XX_DDR_REG_FLUSH_PCI; -+ break; -+ } -+ mips_cpu_irq_init(); -+ -+ ar71xx_misc_irq_init(); -+ -+ cp0_perfcount_irq = AR71XX_MISC_IRQ_PERFC; -+ -+ ar71xx_gpio_irq_init(); -+} -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-ap81.c linux-2.6.36/arch/mips/ar71xx/mach-ap81.c ---- linux-2.6.36.orig/arch/mips/ar71xx/mach-ap81.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/mach-ap81.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,140 @@ -+/* -+ * Atheros AP81 board support -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * Copyright (C) 2009 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ar913x-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-usb.h" -+ -+#define AP81_GPIO_LED_STATUS 1 -+#define AP81_GPIO_LED_AOSS 3 -+#define AP81_GPIO_LED_WLAN 6 -+#define AP81_GPIO_LED_POWER 14 -+ -+#define AP81_GPIO_BTN_SW4 12 -+#define AP81_GPIO_BTN_SW1 21 -+ -+#define AP81_BUTTONS_POLL_INTERVAL 20 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition ap81_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x040000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "u-boot-env", -+ .offset = 0x040000, -+ .size = 0x010000, -+ } , { -+ .name = "rootfs", -+ .offset = 0x050000, -+ .size = 0x500000, -+ } , { -+ .name = "uImage", -+ .offset = 0x550000, -+ .size = 0x100000, -+ } , { -+ .name = "ART", -+ .offset = 0x650000, -+ .size = 0x1b0000, -+ .mask_flags = MTD_WRITEABLE, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data ap81_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = ap81_partitions, -+ .nr_parts = ARRAY_SIZE(ap81_partitions), -+#endif -+}; -+ -+static struct gpio_led ap81_leds_gpio[] __initdata = { -+ { -+ .name = "ap81:green:status", -+ .gpio = AP81_GPIO_LED_STATUS, -+ .active_low = 1, -+ }, { -+ .name = "ap81:amber:aoss", -+ .gpio = AP81_GPIO_LED_AOSS, -+ .active_low = 1, -+ }, { -+ .name = "ap81:green:wlan", -+ .gpio = AP81_GPIO_LED_WLAN, -+ .active_low = 1, -+ }, { -+ .name = "ap81:green:power", -+ .gpio = AP81_GPIO_LED_POWER, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_button ap81_gpio_buttons[] __initdata = { -+ { -+ .desc = "sw1", -+ .type = EV_KEY, -+ .code = BTN_0, -+ .threshold = 3, -+ .gpio = AP81_GPIO_BTN_SW1, -+ .active_low = 1, -+ } , { -+ .desc = "sw4", -+ .type = EV_KEY, -+ .code = BTN_1, -+ .threshold = 3, -+ .gpio = AP81_GPIO_BTN_SW4, -+ .active_low = 1, -+ } -+}; -+ -+static void __init ap81_setup(void) -+{ -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ -+ ar71xx_set_mac_base(eeprom); -+ ar71xx_add_device_mdio(0x0); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ ar71xx_eth0_data.has_ar8216 = 1; -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.phy_mask = 0x10; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_usb(); -+ -+ ar71xx_add_device_m25p80(&ap81_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ap81_leds_gpio), -+ ap81_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, AP81_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(ap81_gpio_buttons), -+ ap81_gpio_buttons); -+ -+ ar913x_add_device_wmac(eeprom, NULL); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_AP81, "AP81", "Atheros AP81", ap81_setup); -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-ap83.c linux-2.6.36/arch/mips/ar71xx/mach-ap83.c ---- linux-2.6.36.orig/arch/mips/ar71xx/mach-ap83.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/mach-ap83.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,266 @@ -+/* -+ * Atheros AP83 board support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-ar913x-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-usb.h" -+ -+#define AP83_GPIO_LED_WLAN 6 -+#define AP83_GPIO_LED_POWER 14 -+#define AP83_GPIO_LED_JUMPSTART 15 -+#define AP83_GPIO_BTN_JUMPSTART 12 -+#define AP83_GPIO_BTN_RESET 21 -+ -+#define AP83_050_GPIO_VSC7385_CS 1 -+#define AP83_050_GPIO_VSC7385_MISO 3 -+#define AP83_050_GPIO_VSC7385_MOSI 16 -+#define AP83_050_GPIO_VSC7385_SCK 17 -+ -+#define AP83_BUTTONS_POLL_INTERVAL 20 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition ap83_flash_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x040000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "u-boot-env", -+ .offset = 0x040000, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "kernel", -+ .offset = 0x060000, -+ .size = 0x140000, -+ } , { -+ .name = "rootfs", -+ .offset = 0x1a0000, -+ .size = 0x650000, -+ } , { -+ .name = "art", -+ .offset = 0x7f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "firmware", -+ .offset = 0x060000, -+ .size = 0x790000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct ar91xx_flash_platform_data ap83_flash_data = { -+ .width = 2, -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = ap83_flash_partitions, -+ .nr_parts = ARRAY_SIZE(ap83_flash_partitions), -+#endif -+}; -+ -+static struct resource ap83_flash_resources[] = { -+ [0] = { -+ .start = AR71XX_SPI_BASE, -+ .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+}; -+ -+static struct platform_device ap83_flash_device = { -+ .name = "ar91xx-flash", -+ .id = -1, -+ .resource = ap83_flash_resources, -+ .num_resources = ARRAY_SIZE(ap83_flash_resources), -+ .dev = { -+ .platform_data = &ap83_flash_data, -+ } -+}; -+ -+static struct gpio_led ap83_leds_gpio[] __initdata = { -+ { -+ .name = "ap83:green:jumpstart", -+ .gpio = AP83_GPIO_LED_JUMPSTART, -+ .active_low = 0, -+ }, { -+ .name = "ap83:green:power", -+ .gpio = AP83_GPIO_LED_POWER, -+ .active_low = 0, -+ }, { -+ .name = "ap83:green:wlan", -+ .gpio = AP83_GPIO_LED_WLAN, -+ .active_low = 0, -+ }, -+}; -+ -+static struct gpio_button ap83_gpio_buttons[] __initdata = { -+ { -+ .desc = "soft_reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = AP83_GPIO_BTN_RESET, -+ .active_low = 1, -+ } , { -+ .desc = "jumpstart", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = AP83_GPIO_BTN_JUMPSTART, -+ .active_low = 1, -+ } -+}; -+ -+static struct resource ap83_040_spi_resources[] = { -+ [0] = { -+ .start = AR71XX_SPI_BASE, -+ .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+}; -+ -+static struct platform_device ap83_040_spi_device = { -+ .name = "ap83-spi", -+ .id = 0, -+ .resource = ap83_040_spi_resources, -+ .num_resources = ARRAY_SIZE(ap83_040_spi_resources), -+}; -+ -+static struct spi_gpio_platform_data ap83_050_spi_data = { -+ .miso = AP83_050_GPIO_VSC7385_MISO, -+ .mosi = AP83_050_GPIO_VSC7385_MOSI, -+ .sck = AP83_050_GPIO_VSC7385_SCK, -+ .num_chipselect = 1, -+}; -+ -+static struct platform_device ap83_050_spi_device = { -+ .name = "spi_gpio", -+ .id = 0, -+ .dev = { -+ .platform_data = &ap83_050_spi_data, -+ } -+}; -+ -+static void ap83_vsc7385_reset(void) -+{ -+ ar71xx_device_stop(RESET_MODULE_GE1_PHY); -+ udelay(10); -+ ar71xx_device_start(RESET_MODULE_GE1_PHY); -+ mdelay(50); -+} -+ -+static struct vsc7385_platform_data ap83_vsc7385_data = { -+ .reset = ap83_vsc7385_reset, -+ .ucode_name = "vsc7385_ucode_ap83.bin", -+ .mac_cfg = { -+ .tx_ipg = 6, -+ .bit2 = 0, -+ .clk_sel = 3, -+ }, -+}; -+ -+static struct spi_board_info ap83_spi_info[] = { -+ { -+ .bus_num = 0, -+ .chip_select = 0, -+ .max_speed_hz = 25000000, -+ .modalias = "spi-vsc7385", -+ .platform_data = &ap83_vsc7385_data, -+ .controller_data = (void *) AP83_050_GPIO_VSC7385_CS, -+ } -+}; -+ -+static void __init ap83_generic_setup(void) -+{ -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ -+ ar71xx_set_mac_base(eeprom); -+ -+ ar71xx_add_device_mdio(0xfffffffe); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth0_data.phy_mask = 0x1; -+ -+ ar71xx_add_device_eth(0); -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth1_data.speed = SPEED_1000; -+ ar71xx_eth1_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_eth1_pll_data.pll_1000 = 0x1f000000; -+ -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ap83_leds_gpio), -+ ap83_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, AP83_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(ap83_gpio_buttons), -+ ap83_gpio_buttons); -+ -+ ar71xx_add_device_usb(); -+ -+ ar913x_add_device_wmac(eeprom, NULL); -+ -+ platform_device_register(&ap83_flash_device); -+ -+ spi_register_board_info(ap83_spi_info, ARRAY_SIZE(ap83_spi_info)); -+} -+ -+static void __init ap83_040_setup(void) -+{ -+ ap83_flash_data.is_shared=1; -+ ap83_generic_setup(); -+ platform_device_register(&ap83_040_spi_device); -+} -+ -+static void __init ap83_050_setup(void) -+{ -+ ap83_generic_setup(); -+ platform_device_register(&ap83_050_spi_device); -+} -+ -+static void __init ap83_setup(void) -+{ -+ u8 *board_id = (u8 *) KSEG1ADDR(0x1fff1244); -+ unsigned int board_version; -+ -+ board_version = (unsigned int)(board_id[0] - '0'); -+ board_version += ((unsigned int)(board_id[1] - '0')) * 10; -+ -+ switch (board_version) { -+ case 40: -+ ap83_040_setup(); -+ break; -+ case 50: -+ ap83_050_setup(); -+ break; -+ default: -+ printk(KERN_WARNING "AP83-%03u board is not yet supported\n", -+ board_version); -+ } -+} -+ -+MIPS_MACHINE(AR71XX_MACH_AP83, "AP83", "Atheros AP83", ap83_setup); -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-aw-nr580.c linux-2.6.36/arch/mips/ar71xx/mach-aw-nr580.c ---- linux-2.6.36.orig/arch/mips/ar71xx/mach-aw-nr580.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/mach-aw-nr580.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,101 @@ -+/* -+ * AzureWave AW-NR580 board support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-gpio-buttons.h" -+#include "dev-pb42-pci.h" -+#include "dev-leds-gpio.h" -+ -+#define AW_NR580_GPIO_LED_READY_RED 0 -+#define AW_NR580_GPIO_LED_WLAN 1 -+#define AW_NR580_GPIO_LED_READY_GREEN 2 -+#define AW_NR580_GPIO_LED_WPS_GREEN 4 -+#define AW_NR580_GPIO_LED_WPS_AMBER 5 -+ -+#define AW_NR580_GPIO_BTN_WPS 3 -+#define AW_NR580_GPIO_BTN_RESET 11 -+ -+#define AW_NR580_BUTTONS_POLL_INTERVAL 20 -+ -+static struct gpio_led aw_nr580_leds_gpio[] __initdata = { -+ { -+ .name = "aw-nr580:red:ready", -+ .gpio = AW_NR580_GPIO_LED_READY_RED, -+ .active_low = 0, -+ }, { -+ .name = "aw-nr580:green:ready", -+ .gpio = AW_NR580_GPIO_LED_READY_GREEN, -+ .active_low = 0, -+ }, { -+ .name = "aw-nr580:green:wps", -+ .gpio = AW_NR580_GPIO_LED_WPS_GREEN, -+ .active_low = 0, -+ }, { -+ .name = "aw-nr580:amber:wps", -+ .gpio = AW_NR580_GPIO_LED_WPS_AMBER, -+ .active_low = 0, -+ }, { -+ .name = "aw-nr580:green:wlan", -+ .gpio = AW_NR580_GPIO_LED_WLAN, -+ .active_low = 0, -+ } -+}; -+ -+static struct gpio_button aw_nr580_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = AW_NR580_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "wps", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = AW_NR580_GPIO_BTN_WPS, -+ .active_low = 1, -+ } -+}; -+ -+static void __init aw_nr580_setup(void) -+{ -+ ar71xx_add_device_mdio(0x0); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_add_device_eth(0); -+ -+ pb42_pci_init(); -+ -+ ar71xx_add_device_m25p80(NULL); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(aw_nr580_leds_gpio), -+ aw_nr580_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, AW_NR580_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(aw_nr580_gpio_buttons), -+ aw_nr580_gpio_buttons); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_AW_NR580, "AW-NR580", "AzureWave AW-NR580", -+ aw_nr580_setup); -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-dir-600-a1.c linux-2.6.36/arch/mips/ar71xx/mach-dir-600-a1.c ---- linux-2.6.36.orig/arch/mips/ar71xx/mach-dir-600-a1.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/mach-dir-600-a1.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,138 @@ -+/* -+ * D-Link DIR-600 rev. A1 board support -+ * -+ * Copyright (C) 2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ap91-eth.h" -+#include "dev-ap91-pci.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "nvram.h" -+ -+#define DIR_600_A1_GPIO_LED_WPS 0 -+#define DIR_600_A1_GPIO_LED_POWER_AMBER 1 -+#define DIR_600_A1_GPIO_LED_POWER_GREEN 6 -+ -+#define DIR_600_A1_GPIO_BTN_RESET 8 -+#define DIR_600_A1_GPIO_BTN_WPS 12 -+ -+#define DIR_600_A1_BUTTONS_POLL_INTERVAL 20 -+ -+#define DIR_600_A1_NVRAM_ADDR 0x1f030000 -+#define DIR_600_A1_NVRAM_SIZE 0x10000 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition dir_600_a1_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x030000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "nvram", -+ .offset = 0x030000, -+ .size = 0x010000, -+ }, { -+ .name = "kernel", -+ .offset = 0x040000, -+ .size = 0x0e0000, -+ }, { -+ .name = "rootfs", -+ .offset = 0x120000, -+ .size = 0x2c0000, -+ }, { -+ .name = "mac", -+ .offset = 0x3e0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "art", -+ .offset = 0x3f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "firmware", -+ .offset = 0x040000, -+ .size = 0x3a0000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data dir_600_a1_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = dir_600_a1_partitions, -+ .nr_parts = ARRAY_SIZE(dir_600_a1_partitions), -+#endif -+}; -+ -+static struct gpio_led dir_600_a1_leds_gpio[] __initdata = { -+ { -+ .name = "dir-600-a1:green:power", -+ .gpio = DIR_600_A1_GPIO_LED_POWER_GREEN, -+ }, { -+ .name = "dir-600-a1:amber:power", -+ .gpio = DIR_600_A1_GPIO_LED_POWER_AMBER, -+ }, { -+ .name = "dir-600-a1:blue:wps", -+ .gpio = DIR_600_A1_GPIO_LED_WPS, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_button dir_600_a1_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = DIR_600_A1_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "wps", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = DIR_600_A1_GPIO_BTN_WPS, -+ .active_low = 1, -+ } -+}; -+ -+static void __init dir_600_a1_setup(void) -+{ -+ const char *nvram = (char *) KSEG1ADDR(DIR_600_A1_NVRAM_ADDR); -+ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); -+ u8 mac_buff[6]; -+ u8 *mac = NULL; -+ -+ if (nvram_parse_mac_addr(nvram, DIR_600_A1_NVRAM_SIZE, -+ "lan_mac=", mac_buff) == 0) -+ mac = mac_buff; -+ -+ ar71xx_add_device_m25p80(&dir_600_a1_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(dir_600_a1_leds_gpio), -+ dir_600_a1_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, DIR_600_A1_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(dir_600_a1_gpio_buttons), -+ dir_600_a1_gpio_buttons); -+ -+ ap91_eth_init(mac, NULL); -+ ap91_pci_init(ee, mac); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_DIR_600_A1, "DIR-600-A1", "D-Link DIR-600 rev. A1", -+ dir_600_a1_setup); -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-dir-615-c1.c linux-2.6.36/arch/mips/ar71xx/mach-dir-615-c1.c ---- linux-2.6.36.orig/arch/mips/ar71xx/mach-dir-615-c1.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/mach-dir-615-c1.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,173 @@ -+/* -+ * D-Link DIR-615 rev C1 board support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ar913x-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "nvram.h" -+ -+#define DIR_615C1_GPIO_LED_ORANGE_STATUS 1 /* ORANGE:STATUS:TRICOLOR */ -+#define DIR_615C1_GPIO_LED_BLUE_WPS 3 /* BLUE:WPS */ -+#define DIR_615C1_GPIO_LED_GREEN_WAN 4 /* GREEN:WAN:TRICOLOR */ -+#define DIR_615C1_GPIO_LED_GREEN_WANCPU 5 /* GREEN:WAN:CPU:TRICOLOR */ -+#define DIR_615C1_GPIO_LED_GREEN_WLAN 6 /* GREEN:WLAN */ -+#define DIR_615C1_GPIO_LED_GREEN_STATUS 14 /* GREEN:STATUS:TRICOLOR */ -+#define DIR_615C1_GPIO_LED_ORANGE_WAN 15 /* ORANGE:WAN:TRICOLOR */ -+ -+/* buttons may need refinement */ -+ -+#define DIR_615C1_GPIO_BTN_WPS 12 -+#define DIR_615C1_GPIO_BTN_RESET 21 -+ -+#define DIR_615C1_BUTTONS_POLL_INTERVAL 20 -+ -+#define DIR_615C1_CONFIG_ADDR 0x1f020000 -+#define DIR_615C1_CONFIG_SIZE 0x10000 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition dir_615c1_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "config", -+ .offset = 0x020000, -+ .size = 0x010000, -+ } , { -+ .name = "kernel", -+ .offset = 0x030000, -+ .size = 0x0d0000, -+ } , { -+ .name = "rootfs", -+ .offset = 0x100000, -+ .size = 0x2f0000, -+ } , { -+ .name = "art", -+ .offset = 0x3f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "firmware", -+ .offset = 0x030000, -+ .size = 0x3c0000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data dir_615c1_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = dir_615c1_partitions, -+ .nr_parts = ARRAY_SIZE(dir_615c1_partitions), -+#endif -+}; -+ -+static struct gpio_led dir_615c1_leds_gpio[] __initdata = { -+ { -+ .name = "dir-615c1:orange:status", -+ .gpio = DIR_615C1_GPIO_LED_ORANGE_STATUS, -+ .active_low = 1, -+ }, { -+ .name = "dir-615c1:blue:wps", -+ .gpio = DIR_615C1_GPIO_LED_BLUE_WPS, -+ .active_low = 1, -+ }, { -+ .name = "dir-615c1:green:wan", -+ .gpio = DIR_615C1_GPIO_LED_GREEN_WAN, -+ .active_low = 1, -+ }, { -+ .name = "dir-615c1:green:wancpu", -+ .gpio = DIR_615C1_GPIO_LED_GREEN_WANCPU, -+ .active_low = 1, -+ }, { -+ .name = "dir-615c1:green:wlan", -+ .gpio = DIR_615C1_GPIO_LED_GREEN_WLAN, -+ .active_low = 1, -+ }, { -+ .name = "dir-615c1:green:status", -+ .gpio = DIR_615C1_GPIO_LED_GREEN_STATUS, -+ .active_low = 1, -+ }, { -+ .name = "dir-615c1:orange:wan", -+ .gpio = DIR_615C1_GPIO_LED_ORANGE_WAN, -+ .active_low = 1, -+ } -+ -+}; -+ -+static struct gpio_button dir_615c1_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = DIR_615C1_GPIO_BTN_RESET, -+ }, { -+ .desc = "wps", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = DIR_615C1_GPIO_BTN_WPS, -+ } -+}; -+ -+#define DIR_615C1_LAN_PHYMASK BIT(0) -+#define DIR_615C1_WAN_PHYMASK BIT(4) -+#define DIR_615C1_MDIO_MASK (~(DIR_615C1_LAN_PHYMASK | \ -+ DIR_615C1_WAN_PHYMASK)) -+ -+static void __init dir_615c1_setup(void) -+{ -+ const char *config = (char *) KSEG1ADDR(DIR_615C1_CONFIG_ADDR); -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ u8 mac[6]; -+ u8 *wlan_mac = NULL; -+ -+ if (nvram_parse_mac_addr(config, DIR_615C1_CONFIG_SIZE, -+ "lan_mac=", mac) == 0) { -+ ar71xx_set_mac_base(mac); -+ wlan_mac = mac; -+ } -+ -+ ar71xx_add_device_mdio(DIR_615C1_MDIO_MASK); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.phy_mask = DIR_615C1_LAN_PHYMASK; -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.phy_mask = DIR_615C1_WAN_PHYMASK; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_m25p80(&dir_615c1_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(dir_615c1_leds_gpio), -+ dir_615c1_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, DIR_615C1_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(dir_615c1_gpio_buttons), -+ dir_615c1_gpio_buttons); -+ -+ ar913x_add_device_wmac(eeprom, wlan_mac); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_DIR_615_C1, "DIR-615-C1", "D-Link DIR-615 rev. C1", -+ dir_615c1_setup); -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-dir-825-b1.c linux-2.6.36/arch/mips/ar71xx/mach-dir-825-b1.c ---- linux-2.6.36.orig/arch/mips/ar71xx/mach-dir-825-b1.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/mach-dir-825-b1.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,192 @@ -+/* -+ * D-Link DIR-825 rev. B1 board support -+ * -+ * Copyright (C) 2009 Lukas Kuna, Evkanet, s.r.o. -+ * -+ * based on mach-wndr3700.c -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ap94-pci.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-usb.h" -+ -+#define DIR825B1_GPIO_LED_BLUE_USB 0 -+#define DIR825B1_GPIO_LED_ORANGE_POWER 1 -+#define DIR825B1_GPIO_LED_BLUE_POWER 2 -+#define DIR825B1_GPIO_LED_BLUE_POWERSAVE 4 -+#define DIR825B1_GPIO_LED_ORANGE_PLANET 6 -+#define DIR825B1_GPIO_LED_BLUE_PLANET 11 -+ -+#define DIR825B1_GPIO_BTN_RESET 3 -+#define DIR825B1_GPIO_BTN_POWERSAVE 8 -+ -+#define DIR825B1_GPIO_RTL8366_SDA 5 -+#define DIR825B1_GPIO_RTL8366_SCK 7 -+ -+#define DIR825B1_BUTTONS_POLL_INTERVAL 20 -+ -+#define DIR825B1_CAL_LOCATION_0 0x1f661000 -+#define DIR825B1_CAL_LOCATION_1 0x1f665000 -+ -+#define DIR825B1_MAC_LOCATION_0 0x2ffa81b8 -+#define DIR825B1_MAC_LOCATION_1 0x2ffa8370 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition dir825b1_partitions[] = { -+ { -+ .name = "uboot", -+ .offset = 0, -+ .size = 0x040000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "config", -+ .offset = 0x040000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "firmware", -+ .offset = 0x050000, -+ .size = 0x610000, -+ } , { -+ .name = "caldata", -+ .offset = 0x660000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "unknown", -+ .offset = 0x670000, -+ .size = 0x190000, -+ .mask_flags = MTD_WRITEABLE, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data dir825b1_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = dir825b1_partitions, -+ .nr_parts = ARRAY_SIZE(dir825b1_partitions), -+#endif -+}; -+ -+static struct gpio_led dir825b1_leds_gpio[] __initdata = { -+ { -+ .name = "dir825b1:blue:usb", -+ .gpio = DIR825B1_GPIO_LED_BLUE_USB, -+ .active_low = 1, -+ }, { -+ .name = "dir825b1:orange:power", -+ .gpio = DIR825B1_GPIO_LED_ORANGE_POWER, -+ .active_low = 1, -+ }, { -+ .name = "dir825b1:blue:power", -+ .gpio = DIR825B1_GPIO_LED_BLUE_POWER, -+ .active_low = 1, -+ }, { -+ .name = "dir825b1:blue:powersave", -+ .gpio = DIR825B1_GPIO_LED_BLUE_POWERSAVE, -+ .active_low = 1, -+ }, { -+ .name = "dir825b1:orange:planet", -+ .gpio = DIR825B1_GPIO_LED_ORANGE_PLANET, -+ .active_low = 1, -+ }, { -+ .name = "dir825b1:blue:planet", -+ .gpio = DIR825B1_GPIO_LED_BLUE_PLANET, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_button dir825b1_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = DIR825B1_GPIO_BTN_RESET, -+ .active_low = 1, -+ } , { -+ .desc = "powersave", -+ .type = EV_KEY, -+ .code = BTN_1, -+ .threshold = 3, -+ .gpio = DIR825B1_GPIO_BTN_POWERSAVE, -+ .active_low = 1, -+ } -+}; -+ -+static struct rtl8366s_platform_data dir825b1_rtl8366s_data = { -+ .gpio_sda = DIR825B1_GPIO_RTL8366_SDA, -+ .gpio_sck = DIR825B1_GPIO_RTL8366_SCK, -+}; -+ -+static struct platform_device dir825b1_rtl8366s_device = { -+ .name = RTL8366S_DRIVER_NAME, -+ .id = -1, -+ .dev = { -+ .platform_data = &dir825b1_rtl8366s_data, -+ } -+}; -+ -+static void __init dir825b1_setup(void) -+{ -+ u8 mac[6], i; -+ -+ memcpy(mac, (u8*)KSEG1ADDR(DIR825B1_MAC_LOCATION_1), 6); -+ for(i = 5; i >= 3; i--) -+ if(++mac[i] != 0x00) break; -+ -+ ar71xx_set_mac_base(mac); -+ -+ ar71xx_add_device_mdio(0x0); -+ -+ ar71xx_eth0_data.mii_bus_dev = &dir825b1_rtl8366s_device.dev; -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth0_data.speed = SPEED_1000; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ ar71xx_eth0_pll_data.pll_1000 = 0x11110000; -+ -+ ar71xx_eth1_data.mii_bus_dev = &dir825b1_rtl8366s_device.dev; -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth1_data.phy_mask = 0x10; -+ ar71xx_eth1_pll_data.pll_1000 = 0x11110000; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_m25p80(&dir825b1_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(dir825b1_leds_gpio), -+ dir825b1_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, DIR825B1_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(dir825b1_gpio_buttons), -+ dir825b1_gpio_buttons); -+ -+ ar71xx_add_device_usb(); -+ -+ platform_device_register(&dir825b1_rtl8366s_device); -+ -+ ap94_pci_init((u8 *) KSEG1ADDR(DIR825B1_CAL_LOCATION_0), -+ (u8 *) KSEG1ADDR(DIR825B1_MAC_LOCATION_0), -+ (u8 *) KSEG1ADDR(DIR825B1_CAL_LOCATION_1), -+ (u8 *) KSEG1ADDR(DIR825B1_MAC_LOCATION_1)); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_DIR_825_B1, "DIR-825-B1", "D-Link DIR-825 rev. B1", -+ dir825b1_setup); -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-mzk-w04nu.c linux-2.6.36/arch/mips/ar71xx/mach-mzk-w04nu.c ---- linux-2.6.36.orig/arch/mips/ar71xx/mach-mzk-w04nu.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/mach-mzk-w04nu.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,165 @@ -+/* -+ * Planex MZK-W04NU board support -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-ar913x-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-m25p80.h" -+#include "dev-usb.h" -+ -+#define MZK_W04NU_GPIO_LED_USB 0 -+#define MZK_W04NU_GPIO_LED_STATUS 1 -+#define MZK_W04NU_GPIO_LED_WPS 3 -+#define MZK_W04NU_GPIO_LED_WLAN 6 -+#define MZK_W04NU_GPIO_LED_AP 15 -+#define MZK_W04NU_GPIO_LED_ROUTER 16 -+ -+#define MZK_W04NU_GPIO_BTN_APROUTER 5 -+#define MZK_W04NU_GPIO_BTN_WPS 12 -+#define MZK_W04NU_GPIO_BTN_RESET 21 -+ -+#define MZK_W04NU_BUTTONS_POLL_INTERVAL 20 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition mzk_w04nu_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x040000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "u-boot-env", -+ .offset = 0x040000, -+ .size = 0x010000, -+ } , { -+ .name = "kernel", -+ .offset = 0x050000, -+ .size = 0x160000, -+ } , { -+ .name = "rootfs", -+ .offset = 0x1b0000, -+ .size = 0x630000, -+ } , { -+ .name = "art", -+ .offset = 0x7e0000, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "firmware", -+ .offset = 0x050000, -+ .size = 0x790000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data mzk_w04nu_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = mzk_w04nu_partitions, -+ .nr_parts = ARRAY_SIZE(mzk_w04nu_partitions), -+#endif -+}; -+ -+static struct gpio_led mzk_w04nu_leds_gpio[] __initdata = { -+ { -+ .name = "mzk-w04nu:green:status", -+ .gpio = MZK_W04NU_GPIO_LED_STATUS, -+ .active_low = 1, -+ }, { -+ .name = "mzk-w04nu:blue:wps", -+ .gpio = MZK_W04NU_GPIO_LED_WPS, -+ .active_low = 1, -+ }, { -+ .name = "mzk-w04nu:green:wlan", -+ .gpio = MZK_W04NU_GPIO_LED_WLAN, -+ .active_low = 1, -+ }, { -+ .name = "mzk-w04nu:green:usb", -+ .gpio = MZK_W04NU_GPIO_LED_USB, -+ .active_low = 1, -+ }, { -+ .name = "mzk-w04nu:green:ap", -+ .gpio = MZK_W04NU_GPIO_LED_AP, -+ .active_low = 1, -+ }, { -+ .name = "mzk-w04nu:green:router", -+ .gpio = MZK_W04NU_GPIO_LED_ROUTER, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_button mzk_w04nu_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = MZK_W04NU_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "wps", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = MZK_W04NU_GPIO_BTN_WPS, -+ .active_low = 1, -+ }, { -+ .desc = "aprouter", -+ .type = EV_KEY, -+ .code = BTN_2, -+ .threshold = 3, -+ .gpio = MZK_W04NU_GPIO_BTN_APROUTER, -+ .active_low = 0, -+ } -+}; -+ -+#define MZK_W04NU_WAN_PHYMASK BIT(4) -+#define MZK_W04NU_MDIO_MASK (~MZK_W04NU_WAN_PHYMASK) -+ -+static void __init mzk_w04nu_setup(void) -+{ -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ -+ ar71xx_set_mac_base(eeprom); -+ -+ ar71xx_add_device_mdio(MZK_W04NU_MDIO_MASK); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ ar71xx_eth0_data.has_ar8216 = 1; -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.phy_mask = MZK_W04NU_WAN_PHYMASK; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_m25p80(&mzk_w04nu_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(mzk_w04nu_leds_gpio), -+ mzk_w04nu_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, MZK_W04NU_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(mzk_w04nu_gpio_buttons), -+ mzk_w04nu_gpio_buttons); -+ ar71xx_add_device_usb(); -+ -+ ar913x_add_device_wmac(eeprom, NULL); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_MZK_W04NU, "MZK-W04NU", "Planex MZK-W04NU", -+ mzk_w04nu_setup); -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-mzk-w300nh.c linux-2.6.36/arch/mips/ar71xx/mach-mzk-w300nh.c ---- linux-2.6.36.orig/arch/mips/ar71xx/mach-mzk-w300nh.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/mach-mzk-w300nh.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,158 @@ -+/* -+ * Planex MZK-W300NH board support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ar913x-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+ -+#define MZK_W300NH_GPIO_LED_STATUS 1 -+#define MZK_W300NH_GPIO_LED_WPS 3 -+#define MZK_W300NH_GPIO_LED_WLAN 6 -+#define MZK_W300NH_GPIO_LED_AP 15 -+#define MZK_W300NH_GPIO_LED_ROUTER 16 -+ -+#define MZK_W300NH_GPIO_BTN_APROUTER 5 -+#define MZK_W300NH_GPIO_BTN_WPS 12 -+#define MZK_W300NH_GPIO_BTN_RESET 21 -+ -+#define MZK_W04NU_BUTTONS_POLL_INTERVAL 20 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition mzk_w300nh_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x040000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "u-boot-env", -+ .offset = 0x040000, -+ .size = 0x010000, -+ } , { -+ .name = "kernel", -+ .offset = 0x050000, -+ .size = 0x160000, -+ } , { -+ .name = "rootfs", -+ .offset = 0x1b0000, -+ .size = 0x630000, -+ } , { -+ .name = "art", -+ .offset = 0x7e0000, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "firmware", -+ .offset = 0x050000, -+ .size = 0x790000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data mzk_w300nh_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = mzk_w300nh_partitions, -+ .nr_parts = ARRAY_SIZE(mzk_w300nh_partitions), -+#endif -+}; -+ -+static struct gpio_led mzk_w300nh_leds_gpio[] __initdata = { -+ { -+ .name = "mzk-w300nh:green:status", -+ .gpio = MZK_W300NH_GPIO_LED_STATUS, -+ .active_low = 1, -+ }, { -+ .name = "mzk-w300nh:blue:wps", -+ .gpio = MZK_W300NH_GPIO_LED_WPS, -+ .active_low = 1, -+ }, { -+ .name = "mzk-w300nh:green:wlan", -+ .gpio = MZK_W300NH_GPIO_LED_WLAN, -+ .active_low = 1, -+ }, { -+ .name = "mzk-w300nh:green:ap", -+ .gpio = MZK_W300NH_GPIO_LED_AP, -+ .active_low = 1, -+ }, { -+ .name = "mzk-w300nh:green:router", -+ .gpio = MZK_W300NH_GPIO_LED_ROUTER, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_button mzk_w300nh_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = MZK_W300NH_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "wps", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = MZK_W300NH_GPIO_BTN_WPS, -+ .active_low = 1, -+ }, { -+ .desc = "aprouter", -+ .type = EV_KEY, -+ .code = BTN_2, -+ .threshold = 3, -+ .gpio = MZK_W300NH_GPIO_BTN_APROUTER, -+ .active_low = 0, -+ } -+}; -+ -+#define MZK_W300NH_WAN_PHYMASK BIT(4) -+#define MZK_W300NH_MDIO_MASK (~MZK_W300NH_WAN_PHYMASK) -+ -+static void __init mzk_w300nh_setup(void) -+{ -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ -+ ar71xx_set_mac_base(eeprom); -+ -+ ar71xx_add_device_mdio(MZK_W300NH_MDIO_MASK); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ ar71xx_eth0_data.has_ar8216 = 1; -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.phy_mask = MZK_W300NH_WAN_PHYMASK; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_m25p80(&mzk_w300nh_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(mzk_w300nh_leds_gpio), -+ mzk_w300nh_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, MZK_W04NU_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(mzk_w300nh_gpio_buttons), -+ mzk_w300nh_gpio_buttons); -+ ar913x_add_device_wmac(eeprom, NULL); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_MZK_W300NH, "MZK-W300NH", "Planex MZK-W300NH", -+ mzk_w300nh_setup); -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-nbg460n.c linux-2.6.36/arch/mips/ar71xx/mach-nbg460n.c ---- linux-2.6.36.orig/arch/mips/ar71xx/mach-nbg460n.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/mach-nbg460n.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,222 @@ -+/* -+ * Zyxel NBG 460N/550N/550NH board support -+ * -+ * Copyright (C) 2010 Michael Kurz -+ * -+ * based on mach-tl-wr1043nd.c -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ar913x-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+ -+/* LEDs */ -+#define NBG460N_GPIO_LED_WPS 3 -+#define NBG460N_GPIO_LED_WAN 6 -+#define NBG460N_GPIO_LED_POWER 14 -+#define NBG460N_GPIO_LED_WLAN 15 -+ -+/* Buttons */ -+#define NBG460N_GPIO_BTN_WPS 12 -+#define NBG460N_GPIO_BTN_RESET 21 -+#define NBG460N_BUTTONS_POLL_INTERVAL 20 -+ -+/* RTC chip PCF8563 I2C interface */ -+#define NBG460N_GPIO_PCF8563_SDA 8 -+#define NBG460N_GPIO_PCF8563_SCK 7 -+ -+/* Switch configuration I2C interface */ -+#define NBG460N_GPIO_RTL8366_SDA 16 -+#define NBG460N_GPIO_RTL8366_SCK 18 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition nbg460n_partitions[] = { -+ { -+ .name = "Bootbase", -+ .offset = 0, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "U-Boot Config", -+ .offset = 0x010000, -+ .size = 0x030000, -+ } , { -+ .name = "U-Boot", -+ .offset = 0x040000, -+ .size = 0x030000, -+ } , { -+ .name = "linux", -+ .offset = 0x070000, -+ .size = 0x0e0000, -+ } , { -+ .name = "rootfs", -+ .offset = 0x150000, -+ .size = 0x2a0000, -+ } , { -+ .name = "CalibData", -+ .offset = 0x3f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "firmware", -+ .offset = 0x070000, -+ .size = 0x380000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data nbg460n_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = nbg460n_partitions, -+ .nr_parts = ARRAY_SIZE(nbg460n_partitions), -+#endif -+}; -+ -+static struct gpio_led nbg460n_leds_gpio[] __initdata = { -+ { -+ .name = "nbg460n:green:power", -+ .gpio = NBG460N_GPIO_LED_POWER, -+ .active_low = 0, -+ .default_trigger = "default-on", -+ }, { -+ .name = "nbg460n:green:wps", -+ .gpio = NBG460N_GPIO_LED_WPS, -+ .active_low = 0, -+ }, { -+ .name = "nbg460n:green:wlan", -+ .gpio = NBG460N_GPIO_LED_WLAN, -+ .active_low = 0, -+ }, { -+ /* Not really for controlling the LED, -+ when set low the LED blinks uncontrollable */ -+ .name = "nbg460n:green:wan", -+ .gpio = NBG460N_GPIO_LED_WAN, -+ .active_low = 0, -+ } -+}; -+ -+static struct gpio_button nbg460n_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = NBG460N_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "wps", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = NBG460N_GPIO_BTN_WPS, -+ .active_low = 1, -+ } -+}; -+ -+static struct i2c_gpio_platform_data nbg460n_i2c_device_platdata = { -+ .sda_pin = NBG460N_GPIO_PCF8563_SDA, -+ .scl_pin = NBG460N_GPIO_PCF8563_SCK, -+ .udelay = 10, -+}; -+ -+static struct platform_device nbg460n_i2c_device = { -+ .name = "i2c-gpio", -+ .id = -1, -+ .num_resources = 0, -+ .resource = NULL, -+ .dev = { -+ .platform_data = &nbg460n_i2c_device_platdata, -+ }, -+}; -+ -+static struct i2c_board_info nbg460n_i2c_devs[] __initdata = { -+ { -+ I2C_BOARD_INFO("pcf8563", 0x51), -+ }, -+}; -+ -+static void __devinit nbg460n_i2c_init(void) -+{ -+ /* The gpio interface */ -+ platform_device_register(&nbg460n_i2c_device); -+ /* I2C devices */ -+ i2c_register_board_info(0, nbg460n_i2c_devs, -+ ARRAY_SIZE(nbg460n_i2c_devs)); -+} -+ -+ -+static struct rtl8366s_platform_data nbg460n_rtl8366s_data = { -+ .gpio_sda = NBG460N_GPIO_RTL8366_SDA, -+ .gpio_sck = NBG460N_GPIO_RTL8366_SCK, -+}; -+ -+static struct platform_device nbg460n_rtl8366s_device = { -+ .name = RTL8366S_DRIVER_NAME, -+ .id = -1, -+ .dev = { -+ .platform_data = &nbg460n_rtl8366s_data, -+ } -+}; -+ -+static void __init nbg460n_setup(void) -+{ -+ /* end of bootloader sector contains mac address*/ -+ u8 *mac = (u8 *) KSEG1ADDR(0x1fc0fff8); -+ /* last sector contains wlan calib data */ -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ -+ ar71xx_set_mac_base(mac); -+ -+ /* LAN Port */ -+ ar71xx_eth0_data.mii_bus_dev = &nbg460n_rtl8366s_device.dev; -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth0_data.speed = SPEED_1000; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ -+ /* WAN Port */ -+ ar71xx_eth1_data.mii_bus_dev = &nbg460n_rtl8366s_device.dev; -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth1_data.phy_mask = 0x10; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ /* register the switch phy */ -+ platform_device_register(&nbg460n_rtl8366s_device); -+ -+ /* register flash */ -+ ar71xx_add_device_m25p80(&nbg460n_flash_data); -+ -+ ar913x_add_device_wmac(eeprom, mac); -+ -+ /* register RTC chip */ -+ nbg460n_i2c_init(); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(nbg460n_leds_gpio), -+ nbg460n_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, NBG460N_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(nbg460n_gpio_buttons), -+ nbg460n_gpio_buttons); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_NBG460N, "NBG460N", "Zyxel NBG460N/550N/550NH", nbg460n_setup); -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-pb42.c linux-2.6.36/arch/mips/ar71xx/mach-pb42.c ---- linux-2.6.36.orig/arch/mips/ar71xx/mach-pb42.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/mach-pb42.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,71 @@ -+/* -+ * Atheros PB42 board support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-gpio-buttons.h" -+#include "dev-pb42-pci.h" -+#include "dev-usb.h" -+ -+#define PB42_BUTTONS_POLL_INTERVAL 20 -+ -+#define PB42_GPIO_BTN_SW4 8 -+#define PB42_GPIO_BTN_SW5 3 -+ -+static struct gpio_button pb42_gpio_buttons[] __initdata = { -+ { -+ .desc = "sw4", -+ .type = EV_KEY, -+ .code = BTN_0, -+ .threshold = 3, -+ .gpio = PB42_GPIO_BTN_SW4, -+ .active_low = 1, -+ } , { -+ .desc = "sw5", -+ .type = EV_KEY, -+ .code = BTN_1, -+ .threshold = 3, -+ .gpio = PB42_GPIO_BTN_SW5, -+ .active_low = 1, -+ } -+}; -+ -+#define PB42_WAN_PHYMASK BIT(20) -+#define PB42_LAN_PHYMASK (BIT(16) | BIT(17) | BIT(18) | BIT(19)) -+#define PB42_MDIO_PHYMASK (PB42_LAN_PHYMASK | PB42_WAN_PHYMASK) -+ -+static void __init pb42_init(void) -+{ -+ ar71xx_add_device_m25p80(NULL); -+ -+ ar71xx_add_device_mdio(~PB42_MDIO_PHYMASK); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; -+ ar71xx_eth0_data.phy_mask = PB42_WAN_PHYMASK; -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.speed = SPEED_100; -+ ar71xx_eth1_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_gpio_buttons(-1, PB42_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(pb42_gpio_buttons), -+ pb42_gpio_buttons); -+ -+ pb42_pci_init(); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_PB42, "PB42", "Atheros PB42", pb42_init); -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-pb44.c linux-2.6.36/arch/mips/ar71xx/mach-pb44.c ---- linux-2.6.36.orig/arch/mips/ar71xx/mach-pb44.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/mach-pb44.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,207 @@ -+/* -+ * Atheros PB44 board support -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-pb42-pci.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-usb.h" -+ -+#define PB44_PCF8757_VSC7395_CS 0 -+#define PB44_PCF8757_STEREO_CS 1 -+#define PB44_PCF8757_SLIC_CS0 2 -+#define PB44_PCF8757_SLIC_TEST 3 -+#define PB44_PCF8757_SLIC_INT0 4 -+#define PB44_PCF8757_SLIC_INT1 5 -+#define PB44_PCF8757_SW_RESET 6 -+#define PB44_PCF8757_SW_JUMP 8 -+#define PB44_PCF8757_LED_JUMP1 9 -+#define PB44_PCF8757_LED_JUMP2 10 -+#define PB44_PCF8757_TP24 11 -+#define PB44_PCF8757_TP25 12 -+#define PB44_PCF8757_TP26 13 -+#define PB44_PCF8757_TP27 14 -+#define PB44_PCF8757_TP28 15 -+ -+#define PB44_GPIO_I2C_SCL 0 -+#define PB44_GPIO_I2C_SDA 1 -+ -+#define PB44_GPIO_EXP_BASE 16 -+#define PB44_GPIO_VSC7395_CS (PB44_GPIO_EXP_BASE + PB44_PCF8757_VSC7395_CS) -+#define PB44_GPIO_SW_RESET (PB44_GPIO_EXP_BASE + PB44_PCF8757_SW_RESET) -+#define PB44_GPIO_SW_JUMP (PB44_GPIO_EXP_BASE + PB44_PCF8757_SW_JUMP) -+#define PB44_GPIO_LED_JUMP1 (PB44_GPIO_EXP_BASE + PB44_PCF8757_LED_JUMP1) -+#define PB44_GPIO_LED_JUMP2 (PB44_GPIO_EXP_BASE + PB44_PCF8757_LED_JUMP2) -+ -+static struct i2c_gpio_platform_data pb44_i2c_gpio_data = { -+ .sda_pin = PB44_GPIO_I2C_SDA, -+ .scl_pin = PB44_GPIO_I2C_SCL, -+}; -+ -+static struct platform_device pb44_i2c_gpio_device = { -+ .name = "i2c-gpio", -+ .id = 0, -+ .dev = { -+ .platform_data = &pb44_i2c_gpio_data, -+ } -+}; -+ -+static struct pcf857x_platform_data pb44_pcf857x_data = { -+ .gpio_base = PB44_GPIO_EXP_BASE, -+}; -+ -+static struct i2c_board_info pb44_i2c_board_info[] __initdata = { -+ { -+ I2C_BOARD_INFO("pcf8575", 0x20), -+ .platform_data = &pb44_pcf857x_data, -+ }, -+}; -+ -+static struct gpio_led pb44_leds_gpio[] __initdata = { -+ { -+ .name = "pb44:amber:jump1", -+ .gpio = PB44_GPIO_LED_JUMP1, -+ .active_low = 1, -+ }, { -+ .name = "pb44:green:jump2", -+ .gpio = PB44_GPIO_LED_JUMP2, -+ .active_low = 1, -+ }, -+}; -+ -+static struct gpio_button pb44_gpio_buttons[] __initdata = { -+ { -+ .desc = "soft_reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = PB44_GPIO_SW_RESET, -+ .active_low = 1, -+ } , { -+ .desc = "jumpstart", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = PB44_GPIO_SW_JUMP, -+ .active_low = 1, -+ } -+}; -+ -+static void pb44_vsc7395_reset(void) -+{ -+ ar71xx_device_stop(RESET_MODULE_GE1_PHY); -+ udelay(10); -+ ar71xx_device_start(RESET_MODULE_GE1_PHY); -+ mdelay(50); -+} -+ -+static struct vsc7385_platform_data pb44_vsc7395_data = { -+ .reset = pb44_vsc7395_reset, -+ .ucode_name = "vsc7395_ucode_pb44.bin", -+ .mac_cfg = { -+ .tx_ipg = 6, -+ .bit2 = 1, -+ .clk_sel = 0, -+ }, -+}; -+ -+static struct spi_board_info pb44_spi_info[] = { -+ { -+ .bus_num = 0, -+ .chip_select = 0, -+ .max_speed_hz = 25000000, -+ .modalias = "m25p80", -+ }, { -+ .bus_num = 0, -+ .chip_select = 1, -+ .max_speed_hz = 25000000, -+ .modalias = "spi-vsc7385", -+ .platform_data = &pb44_vsc7395_data, -+ .controller_data = (void *) PB44_GPIO_VSC7395_CS, -+ }, -+}; -+ -+static struct resource pb44_spi_resources[] = { -+ [0] = { -+ .start = AR71XX_SPI_BASE, -+ .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+}; -+ -+static struct ar71xx_spi_platform_data pb44_spi_data = { -+ .bus_num = 0, -+ .num_chipselect = 2, -+}; -+ -+static struct platform_device pb44_spi_device = { -+ .name = "pb44-spi", -+ .id = -1, -+ .resource = pb44_spi_resources, -+ .num_resources = ARRAY_SIZE(pb44_spi_resources), -+ .dev = { -+ .platform_data = &pb44_spi_data, -+ }, -+}; -+ -+#define PB44_WAN_PHYMASK BIT(0) -+#define PB44_LAN_PHYMASK 0 -+#define PB44_MDIO_PHYMASK (PB44_LAN_PHYMASK | PB44_WAN_PHYMASK) -+ -+static void __init pb44_init(void) -+{ -+ ar71xx_add_device_mdio(~PB44_MDIO_PHYMASK); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth0_data.phy_mask = PB44_WAN_PHYMASK; -+ -+ ar71xx_add_device_eth(0); -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth1_data.speed = SPEED_1000; -+ ar71xx_eth1_data.duplex = DUPLEX_FULL; -+ ar71xx_eth1_pll_data.pll_1000 = 0x110000; -+ -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_usb(); -+ -+ pb42_pci_init(); -+ -+ i2c_register_board_info(0, pb44_i2c_board_info, -+ ARRAY_SIZE(pb44_i2c_board_info)); -+ -+ platform_device_register(&pb44_i2c_gpio_device); -+ -+ spi_register_board_info(pb44_spi_info, ARRAY_SIZE(pb44_spi_info)); -+ platform_device_register(&pb44_spi_device); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(pb44_leds_gpio), -+ pb44_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, 20, ARRAY_SIZE(pb44_gpio_buttons), -+ pb44_gpio_buttons); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_PB44, "PB44", "Atheros PB44", pb44_init); -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-pb92.c linux-2.6.36/arch/mips/ar71xx/mach-pb92.c ---- linux-2.6.36.orig/arch/mips/ar71xx/mach-pb92.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/mach-pb92.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,109 @@ -+/* -+ * Atheros PB92 board support -+ * -+ * Copyright (C) 2010 Felix Fietkau -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-gpio-buttons.h" -+#include "dev-pb9x-pci.h" -+#include "dev-usb.h" -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition pb92_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x040000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "u-boot-env", -+ .offset = 0x040000, -+ .size = 0x010000, -+ } , { -+ .name = "rootfs", -+ .offset = 0x050000, -+ .size = 0x2b0000, -+ } , { -+ .name = "uImage", -+ .offset = 0x300000, -+ .size = 0x0e0000, -+ } , { -+ .name = "ART", -+ .offset = 0x3e0000, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data pb92_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = pb92_partitions, -+ .nr_parts = ARRAY_SIZE(pb92_partitions), -+#endif -+}; -+ -+ -+#define PB92_BUTTONS_POLL_INTERVAL 20 -+ -+#define PB92_GPIO_BTN_SW4 8 -+#define PB92_GPIO_BTN_SW5 3 -+ -+static struct gpio_button pb92_gpio_buttons[] __initdata = { -+ { -+ .desc = "sw4", -+ .type = EV_KEY, -+ .code = BTN_0, -+ .threshold = 3, -+ .gpio = PB92_GPIO_BTN_SW4, -+ .active_low = 1, -+ } , { -+ .desc = "sw5", -+ .type = EV_KEY, -+ .code = BTN_1, -+ .threshold = 3, -+ .gpio = PB92_GPIO_BTN_SW5, -+ .active_low = 1, -+ } -+}; -+ -+static void __init pb92_init(void) -+{ -+ u8 *mac = (u8 *) KSEG1ADDR(0x1fff0000); -+ -+ ar71xx_set_mac_base(mac); -+ ar71xx_add_device_m25p80(&pb92_flash_data); -+ -+ ar71xx_add_device_mdio(~0); -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.speed = SPEED_1000; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.speed = SPEED_1000; -+ ar71xx_eth1_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_gpio_buttons(-1, PB92_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(pb92_gpio_buttons), -+ pb92_gpio_buttons); -+ -+ pb9x_pci_init(); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_PB92, "PB92", "Atheros PB92", pb92_init); -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-rb4xx.c linux-2.6.36/arch/mips/ar71xx/mach-rb4xx.c ---- linux-2.6.36.orig/arch/mips/ar71xx/mach-rb4xx.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/mach-rb4xx.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,290 @@ -+/* -+ * MikroTik RouterBOARD 4xx series support -+ * -+ * Copyright (C) 2008 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-usb.h" -+ -+#define RB4XX_GPIO_USER_LED 4 -+#define RB4XX_GPIO_RESET_SWITCH 7 -+ -+#define RB4XX_BUTTONS_POLL_INTERVAL 20 -+ -+static struct gpio_led rb4xx_leds_gpio[] __initdata = { -+ { -+ .name = "rb4xx:yellow:user", -+ .gpio = RB4XX_GPIO_USER_LED, -+ .active_low = 0, -+ }, -+}; -+ -+static struct gpio_button rb4xx_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset_switch", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = RB4XX_GPIO_RESET_SWITCH, -+ .active_low = 1, -+ } -+}; -+ -+static struct platform_device rb4xx_nand_device = { -+ .name = "rb4xx-nand", -+ .id = -1, -+}; -+ -+static struct ar71xx_pci_irq rb4xx_pci_irqs[] __initdata = { -+ { -+ .slot = 0, -+ .pin = 1, -+ .irq = AR71XX_PCI_IRQ_DEV2, -+ }, { -+ .slot = 1, -+ .pin = 1, -+ .irq = AR71XX_PCI_IRQ_DEV0, -+ }, { -+ .slot = 1, -+ .pin = 2, -+ .irq = AR71XX_PCI_IRQ_DEV1, -+ }, { -+ .slot = 2, -+ .pin = 1, -+ .irq = AR71XX_PCI_IRQ_DEV1, -+ }, { -+ .slot = 3, -+ .pin = 1, -+ .irq = AR71XX_PCI_IRQ_DEV2, -+ } -+}; -+ -+#if 0 -+/* -+ * SPI device support is experimental -+ */ -+static struct flash_platform_data rb4xx_flash_data = { -+ .type = "pm25lv512", -+}; -+ -+static struct spi_board_info rb4xx_spi_info[] = { -+ { -+ .bus_num = 0, -+ .chip_select = 0, -+ .max_speed_hz = 25000000, -+ .modalias = "m25p80", -+ .platform_data = &rb4xx_flash_data, -+ } -+}; -+ -+static struct mmc_spi_platform_data rb433_mmc_data = { -+ .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, -+}; -+ -+static struct spi_board_info rb433_spi_info[] = { -+ { -+ .bus_num = 0, -+ .chip_select = 0, -+ .max_speed_hz = 25000000, -+ .modalias = "m25p80", -+ .platform_data = &rb433_flash_data, -+ }, { -+ .bus_num = 0, -+ .chip_select = 2, -+ .max_speed_hz = 25000000, -+ .modalias = "mmc_spi", -+ .platform_data = &rb433_mmc_data, -+ } -+}; -+ -+static u32 rb433_spi_get_ioc_base(u8 chip_select, int cs_high, int is_on) -+{ -+ u32 ret; -+ -+ if (is_on == AR71XX_SPI_CS_INACTIVE) { -+ ret = SPI_IOC_CS0 | SPI_IOC_CS1; -+ } else { -+ if (cs_high) { -+ ret = SPI_IOC_CS0 | SPI_IOC_CS1; -+ } else { -+ if ((chip_select ^ 2) == 0) -+ ret = SPI_IOC_CS1 ^ (SPI_IOC_CS0 | SPI_IOC_CS1); -+ else -+ ret = SPI_IOC_CS0 ^ (SPI_IOC_CS0 | SPI_IOC_CS1); -+ } -+ } -+ -+ return ret; -+} -+ -+struct ar71xx_spi_platform_data rb433_spi_data = { -+ .bus_num = 0, -+ .num_chipselect = 3, -+ .get_ioc_base = rb433_spi_get_ioc_base, -+}; -+ -+static void rb4xx_add_device_spi(void) -+{ -+ ar71xx_add_device_spi(NULL, rb4xx_spi_info, ARRAY_SIZE(rb4xx_spi_info)); -+} -+ -+static void rb433_add_device_spi(void) -+{ -+ ar71xx_add_device_spi(&rb433_spi_data, rb433_spi_info, -+ ARRAY_SIZE(rb433_spi_info)); -+} -+#else -+static inline void rb4xx_add_device_spi(void) {} -+static inline void rb433_add_device_spi(void) {} -+#endif -+ -+static void __init rb4xx_generic_setup(void) -+{ -+ ar71xx_gpio_function_enable(AR71XX_GPIO_FUNC_SPI_CS1_EN | -+ AR71XX_GPIO_FUNC_SPI_CS2_EN); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(rb4xx_leds_gpio), -+ rb4xx_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, RB4XX_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(rb4xx_gpio_buttons), -+ rb4xx_gpio_buttons); -+ -+ platform_device_register(&rb4xx_nand_device); -+} -+ -+static void __init rb411_setup(void) -+{ -+ rb4xx_generic_setup(); -+ rb4xx_add_device_spi(); -+ -+ ar71xx_add_device_mdio(0xfffffffc); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; -+ ar71xx_eth0_data.phy_mask = 0x00000003; -+ -+ ar71xx_add_device_eth(0); -+ -+ ar71xx_pci_init(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_RB_411, "411", "MikroTik RouterBOARD 411/A/AH", -+ rb411_setup); -+ -+static void __init rb411u_setup(void) -+{ -+ rb411_setup(); -+ ar71xx_add_device_usb(); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_RB_411U, "411U", "MikroTik RouterBOARD 411U", -+ rb411u_setup); -+ -+static void __init rb433_setup(void) -+{ -+ rb4xx_generic_setup(); -+ rb433_add_device_spi(); -+ -+ ar71xx_add_device_mdio(0xffffffe9); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.phy_mask = 0x00000010; -+ -+ ar71xx_add_device_eth(1); -+ ar71xx_add_device_eth(0); -+ -+ ar71xx_pci_init(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_RB_433, "433", "MikroTik RouterBOARD 433/AH", -+ rb433_setup); -+ -+static void __init rb433u_setup(void) -+{ -+ rb433_setup(); -+ ar71xx_add_device_usb(); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_RB_433U, "433U", "MikroTik RouterBOARD 433UAH", -+ rb433u_setup); -+ -+static void __init rb450_generic_setup(int gige) -+{ -+ rb4xx_generic_setup(); -+ rb4xx_add_device_spi(); -+ -+ ar71xx_add_device_mdio(0xffffffe0); -+ -+ ar71xx_eth0_data.phy_if_mode = (gige) ? PHY_INTERFACE_MODE_RGMII : PHY_INTERFACE_MODE_MII; -+ ar71xx_eth0_data.phy_mask = (gige) ? (1 << 0) : 0; -+ ar71xx_eth0_data.speed = (gige) ? SPEED_1000 : SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_eth1_data.phy_if_mode = (gige) ? PHY_INTERFACE_MODE_RGMII : PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.phy_mask = 0x00000010; -+ -+ ar71xx_add_device_eth(1); -+ ar71xx_add_device_eth(0); -+} -+ -+static void __init rb450_setup(void) -+{ -+ rb450_generic_setup(0); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_RB_450, "450", "MikroTik RouterBOARD 450", -+ rb450_setup); -+ -+static void __init rb450g_setup(void) -+{ -+ rb450_generic_setup(1); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_RB_450G, "450G", "MikroTik RouterBOARD 450G", -+ rb450g_setup); -+ -+static void __init rb493_setup(void) -+{ -+ rb4xx_generic_setup(); -+ rb4xx_add_device_spi(); -+ -+ ar71xx_add_device_mdio(0x3fffff00); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.phy_mask = 0x00000001; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_pci_init(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_RB_493, "493", "MikroTik RouterBOARD 493/AH", -+ rb493_setup); -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-rb750.c linux-2.6.36/arch/mips/ar71xx/mach-rb750.c ---- linux-2.6.36.orig/arch/mips/ar71xx/mach-rb750.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/mach-rb750.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,133 @@ -+/* -+ * MikroTik RouterBOARD 750 support -+ * -+ * Copyright (C) 2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+ -+#include "machtype.h" -+#include "dev-ap91-eth.h" -+ -+static struct rb750_led_data rb750_leds[] = { -+ { -+ .name = "rb750:green:act", -+ .mask = RB750_LED_ACT, -+ .active_low = 1, -+ }, { -+ .name = "rb750:green:port1", -+ .mask = RB750_LED_PORT5, -+ .active_low = 1, -+ }, { -+ .name = "rb750:green:port2", -+ .mask = RB750_LED_PORT4, -+ .active_low = 1, -+ }, { -+ .name = "rb750:green:port3", -+ .mask = RB750_LED_PORT3, -+ .active_low = 1, -+ }, { -+ .name = "rb750:green:port4", -+ .mask = RB750_LED_PORT2, -+ .active_low = 1, -+ }, { -+ .name = "rb750:green:port5", -+ .mask = RB750_LED_PORT1, -+ .active_low = 1, -+ } -+}; -+ -+static struct rb750_led_platform_data rb750_leds_data = { -+ .num_leds = ARRAY_SIZE(rb750_leds), -+ .leds = rb750_leds, -+}; -+ -+static struct platform_device rb750_leds_device = { -+ .name = "leds-rb750", -+ .dev = { -+ .platform_data = &rb750_leds_data, -+ } -+}; -+ -+static const char *rb750_port_names[AP91_ETH_NUM_PORT_NAMES] __initdata = { -+ "port5", -+ "port4", -+ "port3", -+ "port2", -+}; -+ -+static struct platform_device rb750_nand_device = { -+ .name = "rb750-nand", -+ .id = -1, -+}; -+ -+int rb750_latch_change(u32 mask_clr, u32 mask_set) -+{ -+ static DEFINE_SPINLOCK(lock); -+ static u32 latch_set = RB750_LED_BITS | RB750_LVC573_LE; -+ static u32 latch_oe; -+ static u32 latch_clr; -+ unsigned long flags; -+ u32 t; -+ int ret = 0; -+ -+ spin_lock_irqsave(&lock, flags); -+ -+ if ((mask_clr & BIT(31)) != 0 && -+ (latch_set & RB750_LVC573_LE) == 0) { -+ goto unlock; -+ } -+ -+ latch_set = (latch_set | mask_set) & ~mask_clr; -+ latch_clr = (latch_clr | mask_clr) & ~mask_set; -+ -+ if (latch_oe == 0) -+ latch_oe = __raw_readl(ar71xx_gpio_base + GPIO_REG_OE); -+ -+ if (likely(latch_set & RB750_LVC573_LE)) { -+ void __iomem *base = ar71xx_gpio_base; -+ -+ t = __raw_readl(base + GPIO_REG_OE); -+ t |= mask_clr | latch_oe | mask_set; -+ -+ __raw_writel(t, base + GPIO_REG_OE); -+ __raw_writel(latch_clr, base + GPIO_REG_CLEAR); -+ __raw_writel(latch_set, base + GPIO_REG_SET); -+ } else if (mask_clr & RB750_LVC573_LE) { -+ void __iomem *base = ar71xx_gpio_base; -+ -+ latch_oe = __raw_readl(base + GPIO_REG_OE); -+ __raw_writel(RB750_LVC573_LE, base + GPIO_REG_CLEAR); -+ /* flush write */ -+ __raw_readl(base + GPIO_REG_CLEAR); -+ } -+ -+ ret = 1; -+ -+ unlock: -+ spin_unlock_irqrestore(&lock, flags); -+ return ret; -+} -+EXPORT_SYMBOL_GPL(rb750_latch_change); -+ -+static void __init rb750_setup(void) -+{ -+ ar71xx_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN | -+ AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN | -+ AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN | -+ AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN | -+ AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN); -+ -+ ap91_eth_init(NULL, rb750_port_names); -+ platform_device_register(&rb750_leds_device); -+ platform_device_register(&rb750_nand_device); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_RB_750, "750i", "MikroTik RouterBOARD 750", -+ rb750_setup); -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-tew-632brp.c linux-2.6.36/arch/mips/ar71xx/mach-tew-632brp.c ---- linux-2.6.36.orig/arch/mips/ar71xx/mach-tew-632brp.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/mach-tew-632brp.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,149 @@ -+/* -+ * TrendNET TEW-632BRP board support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ar913x-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "nvram.h" -+ -+#define TEW_632BRP_GPIO_LED_STATUS 1 -+#define TEW_632BRP_GPIO_LED_WPS 3 -+#define TEW_632BRP_GPIO_LED_WLAN 6 -+#define TEW_632BRP_GPIO_BTN_WPS 12 -+#define TEW_632BRP_GPIO_BTN_RESET 21 -+ -+#define TEW_632BRP_BUTTONS_POLL_INTERVAL 20 -+ -+#define TEW_632BRP_CONFIG_ADDR 0x1f020000 -+#define TEW_632BRP_CONFIG_SIZE 0x10000 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition tew_632brp_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "config", -+ .offset = 0x020000, -+ .size = 0x010000, -+ } , { -+ .name = "kernel", -+ .offset = 0x030000, -+ .size = 0x0d0000, -+ } , { -+ .name = "rootfs", -+ .offset = 0x100000, -+ .size = 0x2f0000, -+ } , { -+ .name = "art", -+ .offset = 0x3f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "firmware", -+ .offset = 0x030000, -+ .size = 0x3c0000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data tew_632brp_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = tew_632brp_partitions, -+ .nr_parts = ARRAY_SIZE(tew_632brp_partitions), -+#endif -+}; -+ -+static struct gpio_led tew_632brp_leds_gpio[] __initdata = { -+ { -+ .name = "tew-632brp:green:status", -+ .gpio = TEW_632BRP_GPIO_LED_STATUS, -+ .active_low = 1, -+ }, { -+ .name = "tew-632brp:blue:wps", -+ .gpio = TEW_632BRP_GPIO_LED_WPS, -+ .active_low = 1, -+ }, { -+ .name = "tew-632brp:green:wlan", -+ .gpio = TEW_632BRP_GPIO_LED_WLAN, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_button tew_632brp_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = TEW_632BRP_GPIO_BTN_RESET, -+ }, { -+ .desc = "wps", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = TEW_632BRP_GPIO_BTN_WPS, -+ } -+}; -+ -+#define TEW_632BRP_LAN_PHYMASK BIT(0) -+#define TEW_632BRP_WAN_PHYMASK BIT(4) -+#define TEW_632BRP_MDIO_MASK (~(TEW_632BRP_LAN_PHYMASK | \ -+ TEW_632BRP_WAN_PHYMASK)) -+ -+static void __init tew_632brp_setup(void) -+{ -+ const char *config = (char *) KSEG1ADDR(TEW_632BRP_CONFIG_ADDR); -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ u8 mac[6]; -+ u8 *wlan_mac = NULL; -+ -+ if (nvram_parse_mac_addr(config, TEW_632BRP_CONFIG_SIZE, -+ "lan_mac=", mac) == 0) { -+ ar71xx_set_mac_base(mac); -+ wlan_mac = mac; -+ } -+ -+ ar71xx_add_device_mdio(TEW_632BRP_MDIO_MASK); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.phy_mask = TEW_632BRP_LAN_PHYMASK; -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.phy_mask = TEW_632BRP_WAN_PHYMASK; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_m25p80(&tew_632brp_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(tew_632brp_leds_gpio), -+ tew_632brp_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, TEW_632BRP_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(tew_632brp_gpio_buttons), -+ tew_632brp_gpio_buttons); -+ -+ ar913x_add_device_wmac(eeprom, wlan_mac); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_TEW_632BRP, "TEW-632BRP", "TRENDnet TEW-632BRP", -+ tew_632brp_setup); -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-tl-wr1043nd.c linux-2.6.36/arch/mips/ar71xx/mach-tl-wr1043nd.c ---- linux-2.6.36.orig/arch/mips/ar71xx/mach-tl-wr1043nd.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/mach-tl-wr1043nd.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,156 @@ -+/* -+ * TP-LINK TL-WR1043ND board support -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ar913x-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-usb.h" -+ -+#define TL_WR1043ND_GPIO_LED_USB 1 -+#define TL_WR1043ND_GPIO_LED_SYSTEM 2 -+#define TL_WR1043ND_GPIO_LED_QSS 5 -+#define TL_WR1043ND_GPIO_LED_WLAN 9 -+ -+#define TL_WR1043ND_GPIO_BTN_RESET 3 -+#define TL_WR1043ND_GPIO_BTN_QSS 7 -+ -+#define TL_WR1043ND_GPIO_RTL8366_SDA 18 -+#define TL_WR1043ND_GPIO_RTL8366_SCK 19 -+ -+#define TL_WR1043ND_BUTTONS_POLL_INTERVAL 20 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition tl_wr1043nd_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "kernel", -+ .offset = 0x020000, -+ .size = 0x140000, -+ } , { -+ .name = "rootfs", -+ .offset = 0x160000, -+ .size = 0x690000, -+ } , { -+ .name = "art", -+ .offset = 0x7f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "firmware", -+ .offset = 0x020000, -+ .size = 0x7d0000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data tl_wr1043nd_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = tl_wr1043nd_partitions, -+ .nr_parts = ARRAY_SIZE(tl_wr1043nd_partitions), -+#endif -+}; -+ -+static struct gpio_led tl_wr1043nd_leds_gpio[] __initdata = { -+ { -+ .name = "tl-wr1043nd:green:usb", -+ .gpio = TL_WR1043ND_GPIO_LED_USB, -+ .active_low = 1, -+ }, { -+ .name = "tl-wr1043nd:green:system", -+ .gpio = TL_WR1043ND_GPIO_LED_SYSTEM, -+ .active_low = 1, -+ }, { -+ .name = "tl-wr1043nd:green:qss", -+ .gpio = TL_WR1043ND_GPIO_LED_QSS, -+ .active_low = 0, -+ }, { -+ .name = "tl-wr1043nd:green:wlan", -+ .gpio = TL_WR1043ND_GPIO_LED_WLAN, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_button tl_wr1043nd_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = TL_WR1043ND_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "qss", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = TL_WR1043ND_GPIO_BTN_QSS, -+ .active_low = 1, -+ } -+}; -+ -+static struct rtl8366rb_platform_data tl_wr1043nd_rtl8366rb_data = { -+ .gpio_sda = TL_WR1043ND_GPIO_RTL8366_SDA, -+ .gpio_sck = TL_WR1043ND_GPIO_RTL8366_SCK, -+}; -+ -+static struct platform_device tl_wr1043nd_rtl8366rb_device = { -+ .name = RTL8366RB_DRIVER_NAME, -+ .id = -1, -+ .dev = { -+ .platform_data = &tl_wr1043nd_rtl8366rb_data, -+ } -+}; -+ -+static void __init tl_wr1043nd_setup(void) -+{ -+ u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ -+ ar71xx_set_mac_base(mac); -+ -+ ar71xx_eth0_data.mii_bus_dev = &tl_wr1043nd_rtl8366rb_device.dev; -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth0_data.speed = SPEED_1000; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ ar71xx_eth0_pll_data.pll_1000 = 0x1a000000; -+ -+ ar71xx_add_device_eth(0); -+ -+ ar71xx_add_device_usb(); -+ -+ ar71xx_add_device_m25p80(&tl_wr1043nd_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(tl_wr1043nd_leds_gpio), -+ tl_wr1043nd_leds_gpio); -+ -+ platform_device_register(&tl_wr1043nd_rtl8366rb_device); -+ -+ ar71xx_add_device_gpio_buttons(-1, TL_WR1043ND_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(tl_wr1043nd_gpio_buttons), -+ tl_wr1043nd_gpio_buttons); -+ -+ ar913x_add_device_wmac(eeprom, mac); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_TL_WR1043ND, "TL-WR1043ND", "TP-LINK TL-WR1043ND", -+ tl_wr1043nd_setup); -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-tl-wr741nd.c linux-2.6.36/arch/mips/ar71xx/mach-tl-wr741nd.c ---- linux-2.6.36.orig/arch/mips/ar71xx/mach-tl-wr741nd.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/mach-tl-wr741nd.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,115 @@ -+/* -+ * TP-LINK TL-WR741ND board support -+ * -+ * Copyright (C) 2009-2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ap91-eth.h" -+#include "dev-ap91-pci.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+ -+#define TL_WR741ND_GPIO_LED_QSS 0 -+#define TL_WR741ND_GPIO_LED_SYSTEM 1 -+ -+#define TL_WR741ND_GPIO_BTN_RESET 11 -+#define TL_WR741ND_GPIO_BTN_QSS 12 -+ -+#define TL_WR741ND_BUTTONS_POLL_INTERVAL 20 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition tl_wr741nd_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "kernel", -+ .offset = 0x020000, -+ .size = 0x140000, -+ } , { -+ .name = "rootfs", -+ .offset = 0x160000, -+ .size = 0x290000, -+ } , { -+ .name = "art", -+ .offset = 0x3f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "firmware", -+ .offset = 0x020000, -+ .size = 0x3d0000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data tl_wr741nd_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = tl_wr741nd_partitions, -+ .nr_parts = ARRAY_SIZE(tl_wr741nd_partitions), -+#endif -+}; -+ -+static struct gpio_led tl_wr741nd_leds_gpio[] __initdata = { -+ { -+ .name = "tl-wr741nd:green:system", -+ .gpio = TL_WR741ND_GPIO_LED_SYSTEM, -+ .active_low = 1, -+ }, { -+ .name = "tl-wr741nd:green:qss", -+ .gpio = TL_WR741ND_GPIO_LED_QSS, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_button tl_wr741nd_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = TL_WR741ND_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "qss", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = TL_WR741ND_GPIO_BTN_QSS, -+ .active_low = 1, -+ } -+}; -+ -+static void __init tl_wr741nd_setup(void) -+{ -+ u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); -+ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); -+ -+ ar71xx_add_device_m25p80(&tl_wr741nd_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(tl_wr741nd_leds_gpio), -+ tl_wr741nd_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, TL_WR741ND_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(tl_wr741nd_gpio_buttons), -+ tl_wr741nd_gpio_buttons); -+ -+ ap91_eth_init(mac, NULL); -+ ap91_pci_init(ee, mac); -+} -+MIPS_MACHINE(AR71XX_MACH_TL_WR741ND, "TL-WR741ND", "TP-LINK TL-WR741ND", -+ tl_wr741nd_setup); -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-tl-wr841n.c linux-2.6.36/arch/mips/ar71xx/mach-tl-wr841n.c ---- linux-2.6.36.orig/arch/mips/ar71xx/mach-tl-wr841n.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/mach-tl-wr841n.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,143 @@ -+/* -+ * TP-LINK TL-WR841N board support -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-dsa.h" -+#include "dev-m25p80.h" -+#include "dev-gpio-buttons.h" -+#include "dev-pb42-pci.h" -+#include "dev-leds-gpio.h" -+ -+#define TL_WR841ND_V1_GPIO_LED_SYSTEM 2 -+#define TL_WR841ND_V1_GPIO_LED_QSS_GREEN 4 -+#define TL_WR841ND_V1_GPIO_LED_QSS_RED 5 -+ -+#define TL_WR841ND_V1_GPIO_BTN_RESET 3 -+#define TL_WR841ND_V1_GPIO_BTN_QSS 7 -+ -+#define TL_WR841ND_V1_BUTTONS_POLL_INTERVAL 20 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition tl_wr841n_v1_partitions[] = { -+ { -+ .name = "redboot", -+ .offset = 0, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "kernel", -+ .offset = 0x020000, -+ .size = 0x140000, -+ } , { -+ .name = "rootfs", -+ .offset = 0x160000, -+ .size = 0x280000, -+ } , { -+ .name = "config", -+ .offset = 0x3e0000, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "firmware", -+ .offset = 0x020000, -+ .size = 0x3c0000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data tl_wr841n_v1_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = tl_wr841n_v1_partitions, -+ .nr_parts = ARRAY_SIZE(tl_wr841n_v1_partitions), -+#endif -+}; -+ -+static struct gpio_led tl_wr841n_v1_leds_gpio[] __initdata = { -+ { -+ .name = "tl-wr841n:green:system", -+ .gpio = TL_WR841ND_V1_GPIO_LED_SYSTEM, -+ .active_low = 1, -+ }, { -+ .name = "tl-wr841n:red:qss", -+ .gpio = TL_WR841ND_V1_GPIO_LED_QSS_RED, -+ }, { -+ .name = "tl-wr841n:green:qss", -+ .gpio = TL_WR841ND_V1_GPIO_LED_QSS_GREEN, -+ } -+}; -+ -+static struct gpio_button tl_wr841n_v1_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = TL_WR841ND_V1_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "qss", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = TL_WR841ND_V1_GPIO_BTN_QSS, -+ .active_low = 1, -+ } -+}; -+ -+static struct dsa_chip_data tl_wr841n_v1_dsa_chip = { -+ .port_names[0] = "wan", -+ .port_names[1] = "lan1", -+ .port_names[2] = "lan2", -+ .port_names[3] = "lan3", -+ .port_names[4] = "lan4", -+ .port_names[5] = "cpu", -+}; -+ -+static struct dsa_platform_data tl_wr841n_v1_dsa_data = { -+ .nr_chips = 1, -+ .chip = &tl_wr841n_v1_dsa_chip, -+}; -+ -+static void __init tl_wr841n_v1_setup(void) -+{ -+ u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); -+ -+ ar71xx_set_mac_base(mac); -+ -+ ar71xx_add_device_mdio(0x0); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_add_device_eth(0); -+ -+ ar71xx_add_device_dsa(0, &tl_wr841n_v1_dsa_data); -+ -+ ar71xx_add_device_m25p80(&tl_wr841n_v1_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(tl_wr841n_v1_leds_gpio), -+ tl_wr841n_v1_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, TL_WR841ND_V1_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(tl_wr841n_v1_gpio_buttons), -+ tl_wr841n_v1_gpio_buttons); -+ -+ pb42_pci_init(); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_TL_WR841N_V1, "TL-WR841N-v1.5", "TP-LINK TL-WR841N v1", -+ tl_wr841n_v1_setup); -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-tl-wr941nd.c linux-2.6.36/arch/mips/ar71xx/mach-tl-wr941nd.c ---- linux-2.6.36.orig/arch/mips/ar71xx/mach-tl-wr941nd.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/mach-tl-wr941nd.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,142 @@ -+/* -+ * TP-LINK TL-WR941ND board support -+ * -+ * Copyright (C) 2009-2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-dsa.h" -+#include "dev-m25p80.h" -+#include "dev-ar913x-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+ -+#define TL_WR941ND_GPIO_LED_SYSTEM 2 -+#define TL_WR941ND_GPIO_LED_QSS_RED 4 -+#define TL_WR941ND_GPIO_LED_QSS_GREEN 5 -+ -+#define TL_WR941ND_GPIO_BTN_RESET 3 -+#define TL_WR941ND_GPIO_BTN_QSS 7 -+ -+#define TL_WR941ND_BUTTONS_POLL_INTERVAL 20 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition tl_wr941nd_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "kernel", -+ .offset = 0x020000, -+ .size = 0x140000, -+ } , { -+ .name = "rootfs", -+ .offset = 0x160000, -+ .size = 0x290000, -+ } , { -+ .name = "art", -+ .offset = 0x3f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "firmware", -+ .offset = 0x020000, -+ .size = 0x3d0000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data tl_wr941nd_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = tl_wr941nd_partitions, -+ .nr_parts = ARRAY_SIZE(tl_wr941nd_partitions), -+#endif -+}; -+ -+static struct gpio_led tl_wr941nd_leds_gpio[] __initdata = { -+ { -+ .name = "tl-wr941nd:green:system", -+ .gpio = TL_WR941ND_GPIO_LED_SYSTEM, -+ .active_low = 1, -+ }, { -+ .name = "tl-wr941nd:red:qss", -+ .gpio = TL_WR941ND_GPIO_LED_QSS_RED, -+ }, { -+ .name = "tl-wr941nd:green:qss", -+ .gpio = TL_WR941ND_GPIO_LED_QSS_GREEN, -+ } -+}; -+ -+static struct gpio_button tl_wr941nd_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = TL_WR941ND_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "qss", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = TL_WR941ND_GPIO_BTN_QSS, -+ .active_low = 1, -+ } -+}; -+ -+static struct dsa_chip_data tl_wr941nd_dsa_chip = { -+ .port_names[0] = "wan", -+ .port_names[1] = "lan1", -+ .port_names[2] = "lan2", -+ .port_names[3] = "lan3", -+ .port_names[4] = "lan4", -+ .port_names[5] = "cpu", -+}; -+ -+static struct dsa_platform_data tl_wr941nd_dsa_data = { -+ .nr_chips = 1, -+ .chip = &tl_wr941nd_dsa_chip, -+}; -+ -+static void __init tl_wr941nd_setup(void) -+{ -+ u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ -+ ar71xx_set_mac_base(mac); -+ -+ ar71xx_add_device_mdio(0x0); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_dsa(0, &tl_wr941nd_dsa_data); -+ -+ ar71xx_add_device_m25p80(&tl_wr941nd_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(tl_wr941nd_leds_gpio), -+ tl_wr941nd_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, TL_WR941ND_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(tl_wr941nd_gpio_buttons), -+ tl_wr941nd_gpio_buttons); -+ ar913x_add_device_wmac(eeprom, mac); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_TL_WR941ND, "TL-WR941ND", "TP-LINK TL-WR941ND", -+ tl_wr941nd_setup); -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-ubnt.c linux-2.6.36/arch/mips/ar71xx/mach-ubnt.c ---- linux-2.6.36.orig/arch/mips/ar71xx/mach-ubnt.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/mach-ubnt.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,281 @@ -+/* -+ * Ubiquiti RouterStation support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * Copyright (C) 2008 Ubiquiti -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ap91-pci.h" -+#include "dev-gpio-buttons.h" -+#include "dev-pb42-pci.h" -+#include "dev-leds-gpio.h" -+#include "dev-usb.h" -+ -+#define UBNT_RS_GPIO_LED_RF 2 -+#define UBNT_RS_GPIO_SW4 8 -+ -+#define UBNT_LS_SR71_GPIO_LED_D25 0 -+#define UBNT_LS_SR71_GPIO_LED_D26 1 -+#define UBNT_LS_SR71_GPIO_LED_D24 2 -+#define UBNT_LS_SR71_GPIO_LED_D23 4 -+#define UBNT_LS_SR71_GPIO_LED_D22 5 -+#define UBNT_LS_SR71_GPIO_LED_D27 6 -+#define UBNT_LS_SR71_GPIO_LED_D28 7 -+ -+#define UBNT_M_GPIO_LED_L1 0 -+#define UBNT_M_GPIO_LED_L2 1 -+#define UBNT_M_GPIO_LED_L3 11 -+#define UBNT_M_GPIO_LED_L4 7 -+#define UBNT_M_GPIO_BTN_RESET 12 -+ -+#define UBNT_BUTTONS_POLL_INTERVAL 20 -+ -+static struct gpio_led ubnt_rs_leds_gpio[] __initdata = { -+ { -+ .name = "ubnt:green:rf", -+ .gpio = UBNT_RS_GPIO_LED_RF, -+ .active_low = 0, -+ } -+}; -+ -+static struct gpio_led ubnt_ls_sr71_leds_gpio[] __initdata = { -+ { -+ .name = "ubnt:green:d22", -+ .gpio = UBNT_LS_SR71_GPIO_LED_D22, -+ .active_low = 0, -+ }, { -+ .name = "ubnt:green:d23", -+ .gpio = UBNT_LS_SR71_GPIO_LED_D23, -+ .active_low = 0, -+ }, { -+ .name = "ubnt:green:d24", -+ .gpio = UBNT_LS_SR71_GPIO_LED_D24, -+ .active_low = 0, -+ }, { -+ .name = "ubnt:red:d25", -+ .gpio = UBNT_LS_SR71_GPIO_LED_D25, -+ .active_low = 0, -+ }, { -+ .name = "ubnt:red:d26", -+ .gpio = UBNT_LS_SR71_GPIO_LED_D26, -+ .active_low = 0, -+ }, { -+ .name = "ubnt:green:d27", -+ .gpio = UBNT_LS_SR71_GPIO_LED_D27, -+ .active_low = 0, -+ }, { -+ .name = "ubnt:green:d28", -+ .gpio = UBNT_LS_SR71_GPIO_LED_D28, -+ .active_low = 0, -+ } -+}; -+ -+static struct gpio_led ubnt_m_leds_gpio[] __initdata = { -+ { -+ .name = "ubnt:red:link1", -+ .gpio = UBNT_M_GPIO_LED_L1, -+ .active_low = 0, -+ }, { -+ .name = "ubnt:orange:link2", -+ .gpio = UBNT_M_GPIO_LED_L2, -+ .active_low = 0, -+ }, { -+ .name = "ubnt:green:link3", -+ .gpio = UBNT_M_GPIO_LED_L3, -+ .active_low = 0, -+ }, { -+ .name = "ubnt:green:link4", -+ .gpio = UBNT_M_GPIO_LED_L4, -+ .active_low = 0, -+ } -+}; -+ -+static struct gpio_button ubnt_gpio_buttons[] __initdata = { -+ { -+ .desc = "sw4", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = UBNT_RS_GPIO_SW4, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_button ubnt_m_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = UBNT_M_GPIO_BTN_RESET, -+ .active_low = 1, -+ } -+}; -+ -+static void __init ubnt_generic_setup(void) -+{ -+ ar71xx_add_device_m25p80(NULL); -+ -+ ar71xx_add_device_gpio_buttons(-1, UBNT_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(ubnt_gpio_buttons), -+ ubnt_gpio_buttons); -+ -+ pb42_pci_init(); -+} -+ -+#define UBNT_RS_WAN_PHYMASK (1 << 20) -+#define UBNT_RS_LAN_PHYMASK ((1 << 16) | (1 << 17) | (1 << 18) | (1 << 19)) -+ -+static void __init ubnt_rs_setup(void) -+{ -+ ubnt_generic_setup(); -+ -+ ar71xx_add_device_mdio(~(UBNT_RS_WAN_PHYMASK | UBNT_RS_LAN_PHYMASK)); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; -+ ar71xx_eth0_data.phy_mask = UBNT_RS_WAN_PHYMASK; -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.speed = SPEED_100; -+ ar71xx_eth1_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_usb(); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ubnt_rs_leds_gpio), -+ ubnt_rs_leds_gpio); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_UBNT_RS, "UBNT-RS", "Ubiquiti RouterStation", -+ ubnt_rs_setup); -+ -+MIPS_MACHINE(AR71XX_MACH_UBNT_AR71XX, "Ubiquiti AR71xx-based board", -+ "Ubiquiti RouterStation", ubnt_rs_setup); -+ -+#define UBNT_RSPRO_WAN_PHYMASK (1 << 4) -+#define UBNT_RSPRO_LAN_PHYMASK ((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)) -+ -+static void __init ubnt_rspro_setup(void) -+{ -+ ubnt_generic_setup(); -+ -+ ar71xx_add_device_mdio(~(UBNT_RSPRO_WAN_PHYMASK | UBNT_RSPRO_LAN_PHYMASK)); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth0_data.phy_mask = UBNT_RSPRO_WAN_PHYMASK; -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth1_data.phy_mask = UBNT_RSPRO_LAN_PHYMASK; -+ ar71xx_eth1_data.speed = SPEED_1000; -+ ar71xx_eth1_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_usb(); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ubnt_rs_leds_gpio), -+ ubnt_rs_leds_gpio); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_UBNT_RSPRO, "UBNT-RSPRO", "Ubiquiti RouterStation Pro", -+ ubnt_rspro_setup); -+ -+static void __init ubnt_lsx_setup(void) -+{ -+ ubnt_generic_setup(); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_UBNT_LSX, "UBNT-LSX", "Ubiquiti LSX", ubnt_lsx_setup); -+ -+#define UBNT_LSSR71_PHY_MASK (1 << 1) -+ -+static void __init ubnt_lssr71_setup(void) -+{ -+ ubnt_generic_setup(); -+ -+ ar71xx_add_device_mdio(~UBNT_LSSR71_PHY_MASK); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; -+ ar71xx_eth0_data.phy_mask = UBNT_LSSR71_PHY_MASK; -+ -+ ar71xx_add_device_eth(0); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ubnt_ls_sr71_leds_gpio), -+ ubnt_ls_sr71_leds_gpio); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_UBNT_LSSR71, "UBNT-LS-SR71", "Ubiquiti LS-SR71", -+ ubnt_lssr71_setup); -+ -+static void __init ubnt_m_setup(void) -+{ -+ u8 *mac = (u8 *) KSEG1ADDR(0x1fff0000); -+ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); -+ -+ ar71xx_set_mac_base(mac); -+ -+ ar71xx_add_device_m25p80(NULL); -+ -+ ar71xx_add_device_mdio(~0); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ ar71xx_eth0_data.fifo_cfg1 = 0x0010ffff; -+ ar71xx_eth0_data.fifo_cfg2 = 0x015500aa; -+ ar71xx_eth0_data.fifo_cfg3 = 0x01f00140; -+ -+ ar71xx_add_device_eth(0); -+ -+ ap91_pci_init(ee, NULL); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ubnt_m_leds_gpio), -+ ubnt_m_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, UBNT_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(ubnt_m_gpio_buttons), -+ ubnt_m_gpio_buttons); -+} -+ -+static void __init ubnt_rocket_m_setup(void) -+{ -+ ubnt_m_setup(); -+ ar71xx_add_device_usb(); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_UBNT_BULLET_M, "UBNT-BM", "Ubiquiti Bullet M", -+ ubnt_m_setup); -+MIPS_MACHINE(AR71XX_MACH_UBNT_ROCKET_M, "UBNT-RM", "Ubiquiti Rocket M", -+ ubnt_rocket_m_setup); -+ -+/* TODO detect the second ethernet port and use one -+ init function for all Ubiquiti MIMO series products */ -+static void __init ubnt_nano_m_setup(void) -+{ -+ ubnt_m_setup(); -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.speed = SPEED_1000; -+ ar71xx_eth1_data.duplex = DUPLEX_FULL; -+ ar71xx_eth1_data.fifo_cfg1 = 0x0010ffff; -+ ar71xx_eth1_data.fifo_cfg2 = 0x015500aa; -+ ar71xx_eth1_data.fifo_cfg3 = 0x01f00140; -+ -+ ar71xx_add_device_eth(1); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_UBNT_NANO_M, "UBNT-NM", "Ubiquiti Nanostation M", -+ ubnt_nano_m_setup); -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-wndr3700.c linux-2.6.36/arch/mips/ar71xx/mach-wndr3700.c ---- linux-2.6.36.orig/arch/mips/ar71xx/mach-wndr3700.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/mach-wndr3700.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,209 @@ -+/* -+ * Netgear WNDR3700 board support -+ * -+ * Copyright (C) 2009 Marco Porsch -+ * Copyright (C) 2009-2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ap94-pci.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-usb.h" -+ -+#define WNDR3700_GPIO_LED_WPS_ORANGE 0 -+#define WNDR3700_GPIO_LED_POWER_ORANGE 1 -+#define WNDR3700_GPIO_LED_POWER_GREEN 2 -+#define WNDR3700_GPIO_LED_WPS_GREEN 4 -+#define WNDR3700_GPIO_LED_WAN_GREEN 6 -+ -+#define WNDR3700_GPIO_BTN_WPS 3 -+#define WNDR3700_GPIO_BTN_RESET 8 -+#define WNDR3700_GPIO_BTN_WIFI 11 -+ -+#define WNDR3700_GPIO_RTL8366_SDA 5 -+#define WNDR3700_GPIO_RTL8366_SCK 7 -+ -+#define WNDR3700_BUTTONS_POLL_INTERVAL 20 -+ -+#define WNDR3700_WMAC0_MAC_OFFSET 0 -+#define WNDR3700_WMAC1_MAC_OFFSET 0xc -+#define WNDR3700_CALDATA0_OFFSET 0x1000 -+#define WNDR3700_CALDATA1_OFFSET 0x5000 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition wndr3700_partitions[] = { -+ { -+ .name = "uboot", -+ .offset = 0, -+ .size = 0x050000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "env", -+ .offset = 0x050000, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "rootfs", -+ .offset = 0x070000, -+ .size = 0x720000, -+ } , { -+ .name = "config", -+ .offset = 0x790000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "config_bak", -+ .offset = 0x7a0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "pot", -+ .offset = 0x7b0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "traffic_meter", -+ .offset = 0x7c0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "language", -+ .offset = 0x7d0000, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "caldata", -+ .offset = 0x7f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data wndr3700_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = wndr3700_partitions, -+ .nr_parts = ARRAY_SIZE(wndr3700_partitions), -+#endif -+}; -+ -+static struct gpio_led wndr3700_leds_gpio[] __initdata = { -+ { -+ .name = "wndr3700:green:power", -+ .gpio = WNDR3700_GPIO_LED_POWER_GREEN, -+ .active_low = 1, -+ }, { -+ .name = "wndr3700:orange:power", -+ .gpio = WNDR3700_GPIO_LED_POWER_ORANGE, -+ .active_low = 1, -+ }, { -+ .name = "wndr3700:green:wps", -+ .gpio = WNDR3700_GPIO_LED_WPS_GREEN, -+ .active_low = 1, -+ }, { -+ .name = "wndr3700:orange:wps", -+ .gpio = WNDR3700_GPIO_LED_WPS_ORANGE, -+ .active_low = 1, -+ }, { -+ .name = "wndr3700:green:wan", -+ .gpio = WNDR3700_GPIO_LED_WAN_GREEN, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_button wndr3700_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = WNDR3700_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "wps", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = WNDR3700_GPIO_BTN_WPS, -+ .active_low = 1, -+ } , { -+ .desc = "wifi", -+ .type = EV_KEY, -+ .code = BTN_2, -+ .threshold = 3, -+ .gpio = WNDR3700_GPIO_BTN_WIFI, -+ .active_low = 1, -+ } -+}; -+ -+static struct rtl8366s_platform_data wndr3700_rtl8366s_data = { -+ .gpio_sda = WNDR3700_GPIO_RTL8366_SDA, -+ .gpio_sck = WNDR3700_GPIO_RTL8366_SCK, -+}; -+ -+static struct platform_device wndr3700_rtl8366s_device = { -+ .name = RTL8366S_DRIVER_NAME, -+ .id = -1, -+ .dev = { -+ .platform_data = &wndr3700_rtl8366s_data, -+ } -+}; -+ -+static void __init wndr3700_setup(void) -+{ -+ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); -+ -+ ar71xx_set_mac_base(art); -+ -+ ar71xx_eth0_pll_data.pll_1000 = 0x11110000; -+ ar71xx_eth0_data.mii_bus_dev = &wndr3700_rtl8366s_device.dev; -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth0_data.speed = SPEED_1000; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_eth1_pll_data.pll_1000 = 0x11110000; -+ ar71xx_eth1_data.mii_bus_dev = &wndr3700_rtl8366s_device.dev; -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth1_data.phy_mask = 0x10; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_usb(); -+ -+ ar71xx_add_device_m25p80(&wndr3700_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(wndr3700_leds_gpio), -+ wndr3700_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, WNDR3700_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(wndr3700_gpio_buttons), -+ wndr3700_gpio_buttons); -+ -+ platform_device_register(&wndr3700_rtl8366s_device); -+ platform_device_register_simple("wndr3700-led-usb", -1, NULL, 0); -+ -+ ap94_pci_enable_quirk_wndr3700(); -+ ap94_pci_init(art + WNDR3700_CALDATA0_OFFSET, -+ art + WNDR3700_WMAC0_MAC_OFFSET, -+ art + WNDR3700_CALDATA1_OFFSET, -+ art + WNDR3700_WMAC1_MAC_OFFSET); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_WNDR3700, "WNDR3700", "NETGEAR WNDR3700", -+ wndr3700_setup); -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-wnr2000.c linux-2.6.36/arch/mips/ar71xx/mach-wnr2000.c ---- linux-2.6.36.orig/arch/mips/ar71xx/mach-wnr2000.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/mach-wnr2000.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,148 @@ -+/* -+ * NETGEAR WNR2000 board support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * Copyright (C) 2008-2009 Andy Boyett -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ar913x-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+ -+#define WNR2000_GPIO_LED_PWR_GREEN 14 -+#define WNR2000_GPIO_LED_PWR_AMBER 7 -+#define WNR2000_GPIO_LED_WPS 4 -+#define WNR2000_GPIO_LED_WLAN 6 -+#define WNR2000_GPIO_BTN_RESET 21 -+#define WNR2000_GPIO_BTN_WPS 8 -+ -+#define WNR2000_BUTTONS_POLL_INTERVAL 20 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition wnr2000_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x040000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "u-boot-env", -+ .offset = 0x040000, -+ .size = 0x010000, -+ } , { -+ .name = "rootfs", -+ .offset = 0x050000, -+ .size = 0x240000, -+ } , { -+ .name = "user-config", -+ .offset = 0x290000, -+ .size = 0x010000, -+ } , { -+ .name = "uImage", -+ .offset = 0x2a0000, -+ .size = 0x120000, -+ } , { -+ .name = "language_table", -+ .offset = 0x3c0000, -+ .size = 0x020000, -+ } , { -+ .name = "rootfs_checksum", -+ .offset = 0x3e0000, -+ .size = 0x010000, -+ } , { -+ .name = "art", -+ .offset = 0x3f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data wnr2000_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = wnr2000_partitions, -+ .nr_parts = ARRAY_SIZE(wnr2000_partitions), -+#endif -+}; -+ -+static struct gpio_led wnr2000_leds_gpio[] __initdata = { -+ { -+ .name = "wnr2000:green:power", -+ .gpio = WNR2000_GPIO_LED_PWR_GREEN, -+ .active_low = 1, -+ }, { -+ .name = "wnr2000:amber:power", -+ .gpio = WNR2000_GPIO_LED_PWR_AMBER, -+ .active_low = 1, -+ }, { -+ .name = "wnr2000:green:wps", -+ .gpio = WNR2000_GPIO_LED_WPS, -+ .active_low = 1, -+ }, { -+ .name = "wnr2000:blue:wlan", -+ .gpio = WNR2000_GPIO_LED_WLAN, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_button wnr2000_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = WNR2000_GPIO_BTN_RESET, -+ }, { -+ .desc = "wps", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = WNR2000_GPIO_BTN_WPS, -+ } -+}; -+ -+static void __init wnr2000_setup(void) -+{ -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ -+ ar71xx_set_mac_base(eeprom); -+ ar71xx_add_device_mdio(0x0); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ ar71xx_eth0_data.has_ar8216 = 1; -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.phy_mask = 0x10; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_m25p80(&wnr2000_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(wnr2000_leds_gpio), -+ wnr2000_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, WNR2000_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(wnr2000_gpio_buttons), -+ wnr2000_gpio_buttons); -+ -+ -+ ar913x_add_device_wmac(eeprom, NULL); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_WNR2000, "WNR2000", "NETGEAR WNR2000", wnr2000_setup); -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-wp543.c linux-2.6.36/arch/mips/ar71xx/mach-wp543.c ---- linux-2.6.36.orig/arch/mips/ar71xx/mach-wp543.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/mach-wp543.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,99 @@ -+/* -+ * Compex WP543/WPJ543 board support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-pb42-pci.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-usb.h" -+ -+#define WP543_GPIO_SW6 2 -+#define WP543_GPIO_LED_1 3 -+#define WP543_GPIO_LED_2 4 -+#define WP543_GPIO_LED_WLAN 5 -+#define WP543_GPIO_LED_CONN 6 -+#define WP543_GPIO_LED_DIAG 7 -+#define WP543_GPIO_SW4 8 -+ -+#define WP543_BUTTONS_POLL_INTERVAL 20 -+ -+static struct gpio_led wp543_leds_gpio[] __initdata = { -+ { -+ .name = "wp543:green:led1", -+ .gpio = WP543_GPIO_LED_1, -+ .active_low = 1, -+ }, { -+ .name = "wp543:green:led2", -+ .gpio = WP543_GPIO_LED_2, -+ .active_low = 1, -+ }, { -+ .name = "wp543:green:wlan", -+ .gpio = WP543_GPIO_LED_WLAN, -+ .active_low = 1, -+ }, { -+ .name = "wp543:green:conn", -+ .gpio = WP543_GPIO_LED_CONN, -+ .active_low = 1, -+ }, { -+ .name = "wp543:green:diag", -+ .gpio = WP543_GPIO_LED_DIAG, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_button wp543_gpio_buttons[] __initdata = { -+ { -+ .desc = "sw6", -+ .type = EV_KEY, -+ .code = BTN_0, -+ .threshold = 3, -+ .gpio = WP543_GPIO_SW6, -+ }, { -+ .desc = "sw4", -+ .type = EV_KEY, -+ .code = BTN_1, -+ .threshold = 3, -+ .gpio = WP543_GPIO_SW4, -+ } -+}; -+ -+static void __init wp543_setup(void) -+{ -+ ar71xx_add_device_m25p80(NULL); -+ -+ ar71xx_add_device_mdio(0xfffffff7); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; -+ ar71xx_eth0_data.phy_mask = 0x08; -+ ar71xx_eth0_data.reset_bit = RESET_MODULE_GE0_MAC | -+ RESET_MODULE_GE0_PHY; -+ ar71xx_add_device_eth(0); -+ -+ ar71xx_add_device_usb(); -+ -+ pb42_pci_init(); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(wp543_leds_gpio), -+ wp543_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, WP543_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(wp543_gpio_buttons), -+ wp543_gpio_buttons); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_WP543, "WP543", "Compex WP543", wp543_setup); -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-wrt160nl.c linux-2.6.36/arch/mips/ar71xx/mach-wrt160nl.c ---- linux-2.6.36.orig/arch/mips/ar71xx/mach-wrt160nl.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/mach-wrt160nl.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,158 @@ -+/* -+ * Linksys WRT160NL board support -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ar913x-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-usb.h" -+#include "nvram.h" -+ -+#define WRT160NL_GPIO_LED_POWER 14 -+#define WRT160NL_GPIO_LED_WPS_AMBER 9 -+#define WRT160NL_GPIO_LED_WPS_BLUE 8 -+#define WRT160NL_GPIO_LED_WLAN 6 -+ -+#define WRT160NL_GPIO_BTN_WPS 7 -+#define WRT160NL_GPIO_BTN_RESET 21 -+ -+#define WRT160NL_BUTTONS_POLL_INTERVAL 20 -+ -+#define WRT160NL_NVRAM_ADDR 0x1f7e0000 -+#define WRT160NL_NVRAM_SIZE 0x10000 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition wrt160nl_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x040000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "kernel", -+ .offset = 0x040000, -+ .size = 0x0e0000, -+ } , { -+ .name = "filesytem", -+ .offset = 0x120000, -+ .size = 0x6c0000, -+ } , { -+ .name = "nvram", -+ .offset = 0x7e0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "ART", -+ .offset = 0x7f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "firmware", -+ .offset = 0x040000, -+ .size = 0x7a0000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data wrt160nl_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = wrt160nl_partitions, -+ .nr_parts = ARRAY_SIZE(wrt160nl_partitions), -+#endif -+}; -+ -+static struct gpio_led wrt160nl_leds_gpio[] __initdata = { -+ { -+ .name = "wrt160nl:blue:power", -+ .gpio = WRT160NL_GPIO_LED_POWER, -+ .active_low = 1, -+ .default_trigger = "default-on", -+ }, { -+ .name = "wrt160nl:amber:wps", -+ .gpio = WRT160NL_GPIO_LED_WPS_AMBER, -+ .active_low = 1, -+ }, { -+ .name = "wrt160nl:blue:wps", -+ .gpio = WRT160NL_GPIO_LED_WPS_BLUE, -+ .active_low = 1, -+ }, { -+ .name = "wrt160nl:blue:wlan", -+ .gpio = WRT160NL_GPIO_LED_WLAN, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_button wrt160nl_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = WRT160NL_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "wps", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = WRT160NL_GPIO_BTN_WPS, -+ .active_low = 1, -+ } -+}; -+ -+static void __init wrt160nl_setup(void) -+{ -+ const char *nvram = (char *) KSEG1ADDR(WRT160NL_NVRAM_ADDR); -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ u8 mac[6]; -+ -+ if (nvram_parse_mac_addr(nvram, WRT160NL_NVRAM_SIZE, -+ "lan_hwaddr=", mac) == 0) -+ ar71xx_set_mac_base(mac); -+ -+ ar71xx_add_device_mdio(0x0); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.phy_mask = 0x01; -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.phy_mask = 0x10; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_m25p80(&wrt160nl_flash_data); -+ -+ ar71xx_add_device_usb(); -+ -+ if (nvram_parse_mac_addr(nvram, WRT160NL_NVRAM_SIZE, -+ "wl0_hwaddr=", mac) == 0) -+ ar913x_add_device_wmac(eeprom, mac); -+ else -+ ar913x_add_device_wmac(eeprom, NULL); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(wrt160nl_leds_gpio), -+ wrt160nl_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, WRT160NL_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(wrt160nl_gpio_buttons), -+ wrt160nl_gpio_buttons); -+ -+} -+ -+MIPS_MACHINE(AR71XX_MACH_WRT160NL, "WRT160NL", "Linksys WRT160NL", -+ wrt160nl_setup); -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-wrt400n.c linux-2.6.36/arch/mips/ar71xx/mach-wrt400n.c ---- linux-2.6.36.orig/arch/mips/ar71xx/mach-wrt400n.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/mach-wrt400n.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,168 @@ -+/* -+ * Linksys WRT400N board support -+ * -+ * Copyright (C) 2009-2010 Gabor Juhos -+ * Copyright (C) 2009 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-ap94-pci.h" -+#include "dev-m25p80.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+ -+#define WRT400N_GPIO_LED_ORANGE 5 -+#define WRT400N_GPIO_LED_GREEN 4 -+#define WRT400N_GPIO_LED_POWER 1 -+#define WRT400N_GPIO_LED_WLAN 0 -+ -+#define WRT400N_GPIO_BTN_RESET 8 -+#define WRT400N_GPIO_BTN_WLSEC 3 -+ -+#define WRT400N_BUTTONS_POLL_INTERVAL 20 -+ -+#define WRT400N_MAC_ADDR_OFFSET 0x120c -+#define WRT400N_CALDATA0_OFFSET 0x1000 -+#define WRT400N_CALDATA1_OFFSET 0x5000 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition wrt400n_partitions[] = { -+ { -+ .name = "uboot", -+ .offset = 0, -+ .size = 0x030000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "env", -+ .offset = 0x030000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "linux", -+ .offset = 0x040000, -+ .size = 0x140000, -+ } , { -+ .name = "rootfs", -+ .offset = 0x180000, -+ .size = 0x630000, -+ } , { -+ .name = "nvram", -+ .offset = 0x7b0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "factory", -+ .offset = 0x7c0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "language", -+ .offset = 0x7d0000, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "caldata", -+ .offset = 0x7f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "firmware", -+ .offset = 0x040000, -+ .size = 0x770000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data wrt400n_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = wrt400n_partitions, -+ .nr_parts = ARRAY_SIZE(wrt400n_partitions), -+#endif -+}; -+ -+static struct gpio_led wrt400n_leds_gpio[] __initdata = { -+ { -+ .name = "wrt400n:green:status", -+ .gpio = WRT400N_GPIO_LED_GREEN, -+ .active_low = 1, -+ }, { -+ .name = "wrt400n:amber:aoss", -+ .gpio = WRT400N_GPIO_LED_ORANGE, -+ .active_low = 1, -+ }, { -+ .name = "wrt400n:green:wlan", -+ .gpio = WRT400N_GPIO_LED_WLAN, -+ .active_low = 1, -+ }, { -+ .name = "wrt400n:green:power", -+ .gpio = WRT400N_GPIO_LED_POWER, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_button wrt400n_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = WRT400N_GPIO_BTN_RESET, -+ .active_low = 1, -+ } , { -+ .desc = "wlsec", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = WRT400N_GPIO_BTN_WLSEC, -+ .active_low = 1, -+ } -+}; -+ -+static void __init wrt400n_setup(void) -+{ -+ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); -+ u8 mac[6]; -+ int i; -+ -+ memcpy(mac, art + WRT400N_MAC_ADDR_OFFSET, 6); -+ for (i = 5; i >= 3; i--) -+ if (++mac[i] != 0x00) break; -+ -+ ar71xx_set_mac_base(mac); -+ -+ ar71xx_add_device_mdio(0x0); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.phy_mask = 0x10; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_m25p80(&wrt400n_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(wrt400n_leds_gpio), -+ wrt400n_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, WRT400N_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(wrt400n_gpio_buttons), -+ wrt400n_gpio_buttons); -+ -+ ap94_pci_init(art + WRT400N_CALDATA0_OFFSET, NULL, -+ art + WRT400N_CALDATA1_OFFSET, NULL); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_WRT400N, "WRT400N", "Linksys WRT400N", wrt400n_setup); -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-wzr-hp-g300nh.c linux-2.6.36/arch/mips/ar71xx/mach-wzr-hp-g300nh.c ---- linux-2.6.36.orig/arch/mips/ar71xx/mach-wzr-hp-g300nh.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/mach-wzr-hp-g300nh.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,265 @@ -+/* -+ * Buffalo WZR-HP-G300NH board support -+ * -+ * Copyright (C) 2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-ar913x-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-usb.h" -+ -+#define WZRHPG300NH_GPIO_LED_USB 0 -+#define WZRHPG300NH_GPIO_LED_DIAG 1 -+#define WZRHPG300NH_GPIO_LED_WIRELESS 6 -+#define WZRHPG300NH_GPIO_LED_SECURITY 17 -+#define WZRHPG300NH_GPIO_LED_ROUTER 18 -+ -+#define WZRHPG300NH_GPIO_RTL8366_SDA 19 -+#define WZRHPG300NH_GPIO_RTL8366_SCK 20 -+ -+#define WZRHPG300NH_GPIO_74HC153_S0 9 -+#define WZRHPG300NH_GPIO_74HC153_S1 11 -+#define WZRHPG300NH_GPIO_74HC153_1Y 12 -+#define WZRHPG300NH_GPIO_74HC153_2Y 14 -+ -+#define WZRHPG300NH_GPIO_EXP_BASE 32 -+#define WZRHPG300NH_GPIO_BTN_AOSS (WZRHPG300NH_GPIO_EXP_BASE + 0) -+#define WZRHPG300NH_GPIO_BTN_RESET (WZRHPG300NH_GPIO_EXP_BASE + 1) -+#define WZRHPG300NH_GPIO_BTN_ROUTER_ON (WZRHPG300NH_GPIO_EXP_BASE + 2) -+#define WZRHPG300NH_GPIO_BTN_QOS_ON (WZRHPG300NH_GPIO_EXP_BASE + 3) -+#define WZRHPG300NH_GPIO_BTN_USB (WZRHPG300NH_GPIO_EXP_BASE + 5) -+#define WZRHPG300NH_GPIO_BTN_ROUTER_AUTO (WZRHPG300NH_GPIO_EXP_BASE + 6) -+#define WZRHPG300NH_GPIO_BTN_QOS_OFF (WZRHPG300NH_GPIO_EXP_BASE + 7) -+ -+#define WZRHPG300NH_BUTTONS_POLL_INTERVAL 20 -+ -+#define WZRHPG300NH_MAC_OFFSET 0x20c -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition wzrhpg300nh_flash_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x0040000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "u-boot-env", -+ .offset = 0x0040000, -+ .size = 0x0020000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "kernel", -+ .offset = 0x0060000, -+ .size = 0x0100000, -+ }, { -+ .name = "rootfs", -+ .offset = 0x0160000, -+ .size = 0x1e60000, -+ }, { -+ .name = "user_property", -+ .offset = 0x1fc0000, -+ .size = 0x0020000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "art", -+ .offset = 0x1fe0000, -+ .size = 0x0020000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "firmware", -+ .offset = 0x0060000, -+ .size = 0x1f60000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct ar91xx_flash_platform_data wzrhpg300nh_flash_data = { -+ .width = 2, -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = wzrhpg300nh_flash_partitions, -+ .nr_parts = ARRAY_SIZE(wzrhpg300nh_flash_partitions), -+#endif -+}; -+ -+#define WZRHPG300NH_FLASH_BASE 0x1e000000 -+#define WZRHPG300NH_FLASH_SIZE (32 * 1024 * 1024) -+ -+static struct resource wzrhpg300nh_flash_resources[] = { -+ [0] = { -+ .start = WZRHPG300NH_FLASH_BASE, -+ .end = WZRHPG300NH_FLASH_BASE + WZRHPG300NH_FLASH_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+}; -+ -+static struct platform_device wzrhpg300nh_flash_device = { -+ .name = "ar91xx-flash", -+ .id = -1, -+ .resource = wzrhpg300nh_flash_resources, -+ .num_resources = ARRAY_SIZE(wzrhpg300nh_flash_resources), -+ .dev = { -+ .platform_data = &wzrhpg300nh_flash_data, -+ } -+}; -+ -+static struct gpio_led wzrhpg300nh_leds_gpio[] __initdata = { -+ { -+ .name = "wzr-hp-g300nh:orange:security", -+ .gpio = WZRHPG300NH_GPIO_LED_SECURITY, -+ .active_low = 1, -+ }, { -+ .name = "wzr-hp-g300nh:green:wireless", -+ .gpio = WZRHPG300NH_GPIO_LED_WIRELESS, -+ .active_low = 1, -+ }, { -+ .name = "wzr-hp-g300nh:green:router", -+ .gpio = WZRHPG300NH_GPIO_LED_ROUTER, -+ .active_low = 1, -+ }, { -+ .name = "wzr-hp-g300nh:red:diag", -+ .gpio = WZRHPG300NH_GPIO_LED_DIAG, -+ .active_low = 1, -+ }, { -+ .name = "wzr-hp-g300nh:blue:usb", -+ .gpio = WZRHPG300NH_GPIO_LED_USB, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_button wzrhpg300nh_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = WZRHPG300NH_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "aoss", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = WZRHPG300NH_GPIO_BTN_AOSS, -+ .active_low = 1, -+ }, { -+ .desc = "usb", -+ .type = EV_KEY, -+ .code = BTN_2, -+ .threshold = 3, -+ .gpio = WZRHPG300NH_GPIO_BTN_USB, -+ .active_low = 1, -+ }, { -+ .desc = "qos_on", -+ .type = EV_KEY, -+ .code = BTN_3, -+ .threshold = 3, -+ .gpio = WZRHPG300NH_GPIO_BTN_QOS_ON, -+ .active_low = 0, -+ }, { -+ .desc = "qos_off", -+ .type = EV_KEY, -+ .code = BTN_4, -+ .threshold = 3, -+ .gpio = WZRHPG300NH_GPIO_BTN_QOS_OFF, -+ .active_low = 0, -+ }, { -+ .desc = "router_on", -+ .type = EV_KEY, -+ .code = BTN_5, -+ .threshold = 3, -+ .gpio = WZRHPG300NH_GPIO_BTN_ROUTER_ON, -+ .active_low = 0, -+ }, { -+ .desc = "router_auto", -+ .type = EV_KEY, -+ .code = BTN_6, -+ .threshold = 3, -+ .gpio = WZRHPG300NH_GPIO_BTN_ROUTER_AUTO, -+ .active_low = 0, -+ } -+}; -+ -+static struct nxp_74hc153_platform_data wzrhpg300nh_74hc153_data = { -+ .gpio_base = WZRHPG300NH_GPIO_EXP_BASE, -+ .gpio_pin_s0 = WZRHPG300NH_GPIO_74HC153_S0, -+ .gpio_pin_s1 = WZRHPG300NH_GPIO_74HC153_S1, -+ .gpio_pin_1y = WZRHPG300NH_GPIO_74HC153_1Y, -+ .gpio_pin_2y = WZRHPG300NH_GPIO_74HC153_2Y, -+}; -+ -+static struct platform_device wzrhpg300nh_74hc153_device = { -+ .name = NXP_74HC153_DRIVER_NAME, -+ .id = -1, -+ .dev = { -+ .platform_data = &wzrhpg300nh_74hc153_data, -+ } -+}; -+ -+static struct rtl8366s_platform_data wzrhpg300nh_rtl8366s_data = { -+ .gpio_sda = WZRHPG300NH_GPIO_RTL8366_SDA, -+ .gpio_sck = WZRHPG300NH_GPIO_RTL8366_SCK, -+}; -+ -+static struct platform_device wzrhpg300nh_rtl8366s_device = { -+ .name = RTL8366S_DRIVER_NAME, -+ .id = -1, -+ .dev = { -+ .platform_data = &wzrhpg300nh_rtl8366s_data, -+ } -+}; -+ -+static void __init wzrhpg300nh_setup(void) -+{ -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ -+ ar71xx_set_mac_base(eeprom + WZRHPG300NH_MAC_OFFSET); -+ -+ ar71xx_eth0_pll_data.pll_1000 = 0x1e000100; -+ ar71xx_eth0_data.mii_bus_dev = &wzrhpg300nh_rtl8366s_device.dev; -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth0_data.speed = SPEED_1000; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_eth1_pll_data.pll_1000 = 0x1e000100; -+ ar71xx_eth1_data.mii_bus_dev = &wzrhpg300nh_rtl8366s_device.dev; -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth1_data.phy_mask = 0x10; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_usb(); -+ ar913x_add_device_wmac(eeprom, NULL); -+ -+ platform_device_register(&wzrhpg300nh_74hc153_device); -+ platform_device_register(&wzrhpg300nh_flash_device); -+ platform_device_register(&wzrhpg300nh_rtl8366s_device); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(wzrhpg300nh_leds_gpio), -+ wzrhpg300nh_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, WZRHPG300NH_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(wzrhpg300nh_gpio_buttons), -+ wzrhpg300nh_gpio_buttons); -+ -+} -+ -+MIPS_MACHINE(AR71XX_MACH_WZR_HP_G300NH, "WZR-HP-G300NH", -+ "Buffalo WZR-HP-G300NH", wzrhpg300nh_setup); -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/machtype.h linux-2.6.36/arch/mips/ar71xx/machtype.h ---- linux-2.6.36.orig/arch/mips/ar71xx/machtype.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/machtype.h 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,60 @@ -+/* -+ * Atheros AR71xx machine type definitions -+ * -+ * Copyright (C) 2008-2010 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_MACHTYPE_H -+#define _AR71XX_MACHTYPE_H -+ -+#include -+ -+enum ar71xx_mach_type { -+ AR71XX_MACH_GENERIC = 0, -+ AR71XX_MACH_AP81, /* Atheros AP81 */ -+ AR71XX_MACH_AP83, /* Atheros AP83 */ -+ AR71XX_MACH_AW_NR580, /* AzureWave AW-NR580 */ -+ AR71XX_MACH_DIR_600_A1, /* D-Link DIR-600 rev. A1 */ -+ AR71XX_MACH_DIR_615_C1, /* D-Link DIR-615 rev. C1 */ -+ AR71XX_MACH_DIR_825_B1, /* D-Link DIR-825 rev. B1 */ -+ AR71XX_MACH_RB_411, /* MikroTik RouterBOARD 411/411A/411AH */ -+ AR71XX_MACH_RB_411U, /* MikroTik RouterBOARD 411U */ -+ AR71XX_MACH_RB_433, /* MikroTik RouterBOARD 433/433AH */ -+ AR71XX_MACH_RB_433U, /* MikroTik RouterBOARD 433UAH */ -+ AR71XX_MACH_RB_450, /* MikroTik RouterBOARD 450 */ -+ AR71XX_MACH_RB_450G, /* MikroTik RouterBOARD 450G */ -+ AR71XX_MACH_RB_493, /* Mikrotik RouterBOARD 493/493AH */ -+ AR71XX_MACH_RB_750, /* MikroTik RouterBOARD 750 */ -+ AR71XX_MACH_PB42, /* Atheros PB42 */ -+ AR71XX_MACH_PB44, /* Atheros PB44 */ -+ AR71XX_MACH_PB92, /* Atheros PB92 */ -+ AR71XX_MACH_MZK_W04NU, /* Planex MZK-W04NU */ -+ AR71XX_MACH_MZK_W300NH, /* Planex MZK-W300NH */ -+ AR71XX_MACH_NBG460N, /* Zyxel NBG460N/550N/550NH */ -+ AR71XX_MACH_TEW_632BRP, /* TRENDnet TEW-632BRP */ -+ AR71XX_MACH_TL_WR741ND, /* TP-LINK TL-WR741ND */ -+ AR71XX_MACH_TL_WR841N_V1, /* TP-LINK TL-WR841N v1 */ -+ AR71XX_MACH_TL_WR941ND, /* TP-LINK TL-WR941ND */ -+ AR71XX_MACH_TL_WR1043ND, /* TP-LINK TL-WR1041ND */ -+ AR71XX_MACH_UBNT_LSSR71, /* Ubiquiti LS-SR71 */ -+ AR71XX_MACH_UBNT_LSX, /* Ubiquiti LSX */ -+ AR71XX_MACH_UBNT_RS, /* Ubiquiti RouterStation */ -+ AR71XX_MACH_UBNT_AR71XX, /* Ubiquiti AR71xx-based board */ -+ AR71XX_MACH_UBNT_RSPRO, /* Ubiquiti RouterStation Pro */ -+ AR71XX_MACH_UBNT_BULLET_M, /* Ubiquiti Bullet M */ -+ AR71XX_MACH_UBNT_ROCKET_M, /* Ubiquiti Rocket M */ -+ AR71XX_MACH_UBNT_NANO_M, /* Ubiquiti NanoStation M */ -+ AR71XX_MACH_WNDR3700, /* NETGEAR WNDR3700 */ -+ AR71XX_MACH_WNR2000, /* NETGEAR WNR2000 */ -+ AR71XX_MACH_WP543, /* Compex WP543 */ -+ AR71XX_MACH_WRT160NL, /* Linksys WRT160NL */ -+ AR71XX_MACH_WRT400N, /* Linksys WRT400N */ -+ AR71XX_MACH_WZR_HP_G300NH, /* Buffalo WZR-HP-G300NH */ -+}; -+ -+#endif /* _AR71XX_MACHTYPE_H */ -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/nvram.c linux-2.6.36/arch/mips/ar71xx/nvram.c ---- linux-2.6.36.orig/arch/mips/ar71xx/nvram.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/nvram.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,75 @@ -+/* -+ * Atheros AR71xx minimal nvram support -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include "nvram.h" -+ -+char *nvram_find_var(const char *name, const char *buf, unsigned buf_len) -+{ -+ unsigned len = strlen(name); -+ char *cur, *last; -+ -+ if (buf_len == 0 || len == 0) -+ return NULL; -+ -+ if (buf_len < len) -+ return NULL; -+ -+ if (len == 1) -+ return memchr(buf, (int) *name, buf_len); -+ -+ last = (char *) buf + buf_len - len; -+ for (cur = (char *) buf; cur <= last; cur++) -+ if (cur[0] == name[0] && memcmp(cur, name, len) == 0) -+ return cur + len; -+ -+ return NULL; -+} -+ -+int nvram_parse_mac_addr(const char *nvram, unsigned nvram_len, -+ const char *name, char *mac) -+{ -+ char *buf; -+ char *mac_str; -+ int ret; -+ int t; -+ -+ buf = vmalloc(nvram_len); -+ if (!buf) -+ return -ENOMEM; -+ -+ memcpy(buf, nvram, nvram_len); -+ buf[nvram_len - 1] = '\0'; -+ -+ mac_str = nvram_find_var(name, buf, nvram_len); -+ if (!mac_str) { -+ ret = -EINVAL; -+ goto free; -+ } -+ -+ t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", -+ &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]); -+ -+ if (t != 6) { -+ ret = -EINVAL; -+ goto free; -+ } -+ -+ ret = 0; -+ -+ free: -+ vfree(buf); -+ return ret; -+} -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/nvram.h linux-2.6.36/arch/mips/ar71xx/nvram.h ---- linux-2.6.36.orig/arch/mips/ar71xx/nvram.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/nvram.h 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,19 @@ -+/* -+ * Atheros AR71xx minimal nvram support -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_NVRAM_H -+#define _AR71XX_NVRAM_H -+ -+char *nvram_find_var(const char *name, const char *buf, -+ unsigned buf_len) __init; -+int nvram_parse_mac_addr(const char *nvram, unsigned nvram_len, -+ const char *name, char *mac) __init; -+ -+#endif /* _AR71XX_NVRAM_H */ -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/pci.c linux-2.6.36/arch/mips/ar71xx/pci.c ---- linux-2.6.36.orig/arch/mips/ar71xx/pci.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/pci.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,93 @@ -+/* -+ * Atheros AR71xx PCI setup code -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+ -+#include -+ -+#include -+#include -+ -+unsigned ar71xx_pci_nr_irqs __initdata; -+struct ar71xx_pci_irq *ar71xx_pci_irq_map __initdata; -+ -+int (*ar71xx_pci_plat_dev_init)(struct pci_dev *dev); -+ -+static int ar71xx_be_handler(struct pt_regs *regs, int is_fixup) -+{ -+ int err = 0; -+ -+ err = ar71xx_pci_be_handler(is_fixup); -+ -+ return (is_fixup && !err) ? MIPS_BE_FIXUP : MIPS_BE_FATAL; -+} -+ -+int pcibios_plat_dev_init(struct pci_dev *dev) -+{ -+ if (ar71xx_pci_plat_dev_init) -+ return ar71xx_pci_plat_dev_init(dev); -+ -+ return 0; -+} -+ -+int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin) -+{ -+ int ret = 0; -+ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7130: -+ case AR71XX_SOC_AR7141: -+ case AR71XX_SOC_AR7161: -+ ret = ar71xx_pcibios_map_irq(dev, slot, pin); -+ break; -+ -+ case AR71XX_SOC_AR7240: -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ ret = ar724x_pcibios_map_irq(dev, slot, pin); -+ break; -+ -+ default: -+ break; -+ } -+ -+ return ret; -+} -+ -+int __init ar71xx_pci_init(unsigned nr_irqs, struct ar71xx_pci_irq *map) -+{ -+ int ret = 0; -+ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7130: -+ case AR71XX_SOC_AR7141: -+ case AR71XX_SOC_AR7161: -+ board_be_handler = ar71xx_be_handler; -+ ret = ar71xx_pcibios_init(); -+ break; -+ -+ case AR71XX_SOC_AR7240: -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ ret = ar724x_pcibios_init(); -+ break; -+ -+ default: -+ return 0; -+ } -+ -+ ar71xx_pci_nr_irqs = nr_irqs; -+ ar71xx_pci_irq_map = map; -+ -+ return ret; -+} -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/prom.c linux-2.6.36/arch/mips/ar71xx/prom.c ---- linux-2.6.36.orig/arch/mips/ar71xx/prom.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/prom.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,105 @@ -+/* -+ * Atheros AR71xx SoC specific prom routines -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include -+ -+static inline int is_valid_ram_addr(void *addr) -+{ -+ if (((u32) addr > KSEG0) && -+ ((u32) addr < (KSEG0 + AR71XX_MEM_SIZE_MAX))) -+ return 1; -+ -+ if (((u32) addr > KSEG1) && -+ ((u32) addr < (KSEG1 + AR71XX_MEM_SIZE_MAX))) -+ return 1; -+ -+ return 0; -+} -+ -+static void __init ar71xx_prom_append_cmdline(const char *name, -+ const char *value) -+{ -+ char buf[COMMAND_LINE_SIZE]; -+ -+ snprintf(buf, sizeof(buf), " %s=%s", name, value); -+ strlcat(arcs_cmdline, buf, sizeof(arcs_cmdline)); -+} -+ -+static void __init ar71xx_prom_find_env(char **envp, const char *name) -+{ -+ int len = strlen(name); -+ char **p; -+ -+ if (!is_valid_ram_addr(envp)) -+ return; -+ -+ for (p = envp; is_valid_ram_addr(*p); p++) { -+ if (strncmp(name, *p, len) == 0 && (*p)[len] == '=') { -+ ar71xx_prom_append_cmdline(name, *p + len + 1); -+ break; -+ } -+ -+ /* RedBoot env comes in pointer pairs - key, value */ -+ if (strncmp(name, *p, len) == 0 && (*p)[len] == 0) -+ if (is_valid_ram_addr(*(++p))) { -+ ar71xx_prom_append_cmdline(name, *p); -+ break; -+ } -+ } -+} -+ -+static int inline ar71xx_use__image_cmdline(void) { return 0; } -+ -+static __init void ar71xx_prom_init_cmdline(int argc, char **argv) -+{ -+ int i; -+ -+ if (ar71xx_use__image_cmdline()) -+ return; -+ -+ if (!is_valid_ram_addr(argv)) -+ return; -+ -+ for (i = 0; i < argc; i++) -+ if (is_valid_ram_addr(argv[i])) { -+ strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline)); -+ strlcat(arcs_cmdline, argv[i], sizeof(arcs_cmdline)); -+ } -+} -+ -+void __init prom_init(void) -+{ -+ char **envp; -+ -+ printk(KERN_DEBUG "prom: fw_arg0=%08x, fw_arg1=%08x, " -+ "fw_arg2=%08x, fw_arg3=%08x\n", -+ (unsigned int)fw_arg0, (unsigned int)fw_arg1, -+ (unsigned int)fw_arg2, (unsigned int)fw_arg3); -+ -+ -+ ar71xx_prom_init_cmdline(fw_arg0, (char **)fw_arg1); -+ -+ envp = (char **)fw_arg2; -+ ar71xx_prom_find_env(envp, "board"); -+} -+ -+void __init prom_free_prom_memory(void) -+{ -+ /* We do not have to prom memory to free */ -+} -diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/setup.c linux-2.6.36/arch/mips/ar71xx/setup.c ---- linux-2.6.36.orig/arch/mips/ar71xx/setup.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/ar71xx/setup.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,310 @@ -+/* -+ * Atheros AR71xx SoC specific setup -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+ -+#include -+#include /* for mips_hpt_frequency */ -+#include /* for _machine_{restart,halt} */ -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+ -+#define AR71XX_SYS_TYPE_LEN 64 -+#define AR71XX_BASE_FREQ 40000000 -+#define AR91XX_BASE_FREQ 5000000 -+#define AR724X_BASE_FREQ 5000000 -+ -+u32 ar71xx_cpu_freq; -+EXPORT_SYMBOL_GPL(ar71xx_cpu_freq); -+ -+u32 ar71xx_ahb_freq; -+EXPORT_SYMBOL_GPL(ar71xx_ahb_freq); -+ -+u32 ar71xx_ddr_freq; -+EXPORT_SYMBOL_GPL(ar71xx_ddr_freq); -+ -+enum ar71xx_soc_type ar71xx_soc; -+EXPORT_SYMBOL_GPL(ar71xx_soc); -+ -+static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN]; -+ -+static void ar71xx_restart(char *command) -+{ -+ ar71xx_device_stop(RESET_MODULE_FULL_CHIP); -+ for (;;) -+ if (cpu_wait) -+ cpu_wait(); -+} -+ -+static void ar71xx_halt(void) -+{ -+ while (1) -+ cpu_wait(); -+} -+ -+static void __init ar71xx_detect_mem_size(void) -+{ -+ unsigned long size; -+ -+ for (size = AR71XX_MEM_SIZE_MIN; size < AR71XX_MEM_SIZE_MAX; -+ size <<= 1 ) { -+ if (!memcmp(ar71xx_detect_mem_size, -+ ar71xx_detect_mem_size + size, 1024)) -+ break; -+ } -+ -+ add_memory_region(0, size, BOOT_MEM_RAM); -+} -+ -+static void __init ar71xx_detect_sys_type(void) -+{ -+ char *chip = "????"; -+ u32 id; -+ u32 major; -+ u32 minor; -+ u32 rev = 0; -+ -+ id = ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID); -+ major = id & REV_ID_MAJOR_MASK; -+ -+ switch (major) { -+ case REV_ID_MAJOR_AR71XX: -+ minor = id & AR71XX_REV_ID_MINOR_MASK; -+ rev = id >> AR71XX_REV_ID_REVISION_SHIFT; -+ rev &= AR71XX_REV_ID_REVISION_MASK; -+ switch (minor) { -+ case AR71XX_REV_ID_MINOR_AR7130: -+ ar71xx_soc = AR71XX_SOC_AR7130; -+ chip = "7130"; -+ break; -+ -+ case AR71XX_REV_ID_MINOR_AR7141: -+ ar71xx_soc = AR71XX_SOC_AR7141; -+ chip = "7141"; -+ break; -+ -+ case AR71XX_REV_ID_MINOR_AR7161: -+ ar71xx_soc = AR71XX_SOC_AR7161; -+ chip = "7161"; -+ break; -+ } -+ break; -+ -+ case REV_ID_MAJOR_AR7240: -+ ar71xx_soc = AR71XX_SOC_AR7240; -+ chip = "7240"; -+ rev = (id & AR724X_REV_ID_REVISION_MASK); -+ break; -+ -+ case REV_ID_MAJOR_AR7241: -+ ar71xx_soc = AR71XX_SOC_AR7241; -+ chip = "7241"; -+ rev = (id & AR724X_REV_ID_REVISION_MASK); -+ break; -+ -+ case REV_ID_MAJOR_AR7242: -+ ar71xx_soc = AR71XX_SOC_AR7242; -+ chip = "7242"; -+ rev = (id & AR724X_REV_ID_REVISION_MASK); -+ break; -+ -+ case REV_ID_MAJOR_AR913X: -+ minor = id & AR91XX_REV_ID_MINOR_MASK; -+ rev = id >> AR91XX_REV_ID_REVISION_SHIFT; -+ rev &= AR91XX_REV_ID_REVISION_MASK; -+ switch (minor) { -+ case AR91XX_REV_ID_MINOR_AR9130: -+ ar71xx_soc = AR71XX_SOC_AR9130; -+ chip = "9130"; -+ break; -+ -+ case AR91XX_REV_ID_MINOR_AR9132: -+ ar71xx_soc = AR71XX_SOC_AR9132; -+ chip = "9132"; -+ break; -+ } -+ break; -+ -+ default: -+ panic("ar71xx: unknown chip id:0x%08x\n", id); -+ } -+ -+ sprintf(ar71xx_sys_type, "Atheros AR%s rev %u", chip, rev); -+} -+ -+static void __init ar91xx_detect_sys_frequency(void) -+{ -+ u32 pll; -+ u32 freq; -+ u32 div; -+ -+ pll = ar71xx_pll_rr(AR91XX_PLL_REG_CPU_CONFIG); -+ -+ div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK); -+ freq = div * AR91XX_BASE_FREQ; -+ -+ ar71xx_cpu_freq = freq; -+ -+ div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1; -+ ar71xx_ddr_freq = freq / div; -+ -+ div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2; -+ ar71xx_ahb_freq = ar71xx_cpu_freq / div; -+} -+ -+static void __init ar71xx_detect_sys_frequency(void) -+{ -+ u32 pll; -+ u32 freq; -+ u32 div; -+ -+ pll = ar71xx_pll_rr(AR71XX_PLL_REG_CPU_CONFIG); -+ -+ div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1; -+ freq = div * AR71XX_BASE_FREQ; -+ -+ div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1; -+ ar71xx_cpu_freq = freq / div; -+ -+ div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1; -+ ar71xx_ddr_freq = freq / div; -+ -+ div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2; -+ ar71xx_ahb_freq = ar71xx_cpu_freq / div; -+} -+ -+static void __init ar724x_detect_sys_frequency(void) -+{ -+ u32 pll; -+ u32 freq; -+ u32 div; -+ -+ pll = ar71xx_pll_rr(AR724X_PLL_REG_CPU_CONFIG); -+ -+ div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK); -+ freq = div * AR724X_BASE_FREQ; -+ -+ div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK); -+ freq *= div; -+ -+ ar71xx_cpu_freq = freq; -+ -+ div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1; -+ ar71xx_ddr_freq = freq / div; -+ -+ div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2; -+ ar71xx_ahb_freq = ar71xx_cpu_freq / div; -+} -+ -+static void __init detect_sys_frequency(void) -+{ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7130: -+ case AR71XX_SOC_AR7141: -+ case AR71XX_SOC_AR7161: -+ ar71xx_detect_sys_frequency(); -+ break; -+ -+ case AR71XX_SOC_AR7240: -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ ar724x_detect_sys_frequency(); -+ break; -+ -+ case AR71XX_SOC_AR9130: -+ case AR71XX_SOC_AR9132: -+ ar91xx_detect_sys_frequency(); -+ break; -+ -+ default: -+ BUG(); -+ } -+} -+ -+const char *get_system_type(void) -+{ -+ return ar71xx_sys_type; -+} -+ -+unsigned int __cpuinit get_c0_compare_irq(void) -+{ -+ return CP0_LEGACY_COMPARE_IRQ; -+} -+ -+void __init plat_mem_setup(void) -+{ -+ set_io_port_base(KSEG1); -+ -+ ar71xx_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE, -+ AR71XX_DDR_CTRL_SIZE); -+ -+ ar71xx_pll_base = ioremap_nocache(AR71XX_PLL_BASE, -+ AR71XX_PLL_SIZE); -+ -+ ar71xx_reset_base = ioremap_nocache(AR71XX_RESET_BASE, -+ AR71XX_RESET_SIZE); -+ -+ ar71xx_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE); -+ -+ ar71xx_usb_ctrl_base = ioremap_nocache(AR71XX_USB_CTRL_BASE, -+ AR71XX_USB_CTRL_SIZE); -+ -+ ar71xx_detect_mem_size(); -+ ar71xx_detect_sys_type(); -+ detect_sys_frequency(); -+ -+ printk(KERN_INFO -+ "%s, CPU:%u.%03u MHz, AHB:%u.%03u MHz, DDR:%u.%03u MHz\n", -+ ar71xx_sys_type, -+ ar71xx_cpu_freq / 1000000, (ar71xx_cpu_freq / 1000) % 1000, -+ ar71xx_ahb_freq / 1000000, (ar71xx_ahb_freq / 1000) % 1000, -+ ar71xx_ddr_freq / 1000000, (ar71xx_ddr_freq / 1000) % 1000); -+ -+ _machine_restart = ar71xx_restart; -+ _machine_halt = ar71xx_halt; -+ pm_power_off = ar71xx_halt; -+} -+ -+void __init plat_time_init(void) -+{ -+ mips_hpt_frequency = ar71xx_cpu_freq / 2; -+} -+ -+__setup("board=", mips_machtype_setup); -+ -+static int __init ar71xx_machine_setup(void) -+{ -+ ar71xx_gpio_init(); -+ -+ ar71xx_add_device_uart(); -+ ar71xx_add_device_wdt(); -+ -+ mips_machine_setup(); -+ return 0; -+} -+ -+arch_initcall(ar71xx_machine_setup); -+ -+static void __init ar71xx_generic_init(void) -+{ -+ /* Nothing to do */ -+} -+ -+MIPS_MACHINE(AR71XX_MACH_GENERIC, "Generic", "Generic AR71xx board", -+ ar71xx_generic_init); -diff -Nur linux-2.6.36.orig/arch/mips/include/asm/mach-ar71xx/ar71xx.h linux-2.6.36/arch/mips/include/asm/mach-ar71xx/ar71xx.h ---- linux-2.6.36.orig/arch/mips/include/asm/mach-ar71xx/ar71xx.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/include/asm/mach-ar71xx/ar71xx.h 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,514 @@ -+/* -+ * Atheros AR71xx SoC specific definitions -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef __ASM_MACH_AR71XX_H -+#define __ASM_MACH_AR71XX_H -+ -+#include -+#include -+#include -+#include -+ -+#ifndef __ASSEMBLER__ -+ -+#define AR71XX_PCI_MEM_BASE 0x10000000 -+#define AR71XX_PCI_MEM_SIZE 0x08000000 -+#define AR71XX_APB_BASE 0x18000000 -+#define AR71XX_GE0_BASE 0x19000000 -+#define AR71XX_GE0_SIZE 0x01000000 -+#define AR71XX_GE1_BASE 0x1a000000 -+#define AR71XX_GE1_SIZE 0x01000000 -+#define AR71XX_EHCI_BASE 0x1b000000 -+#define AR71XX_EHCI_SIZE 0x01000000 -+#define AR71XX_OHCI_BASE 0x1c000000 -+#define AR71XX_OHCI_SIZE 0x01000000 -+#define AR7240_OHCI_BASE 0x1b000000 -+#define AR7240_OHCI_SIZE 0x01000000 -+#define AR71XX_SPI_BASE 0x1f000000 -+#define AR71XX_SPI_SIZE 0x01000000 -+ -+#define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000) -+#define AR71XX_DDR_CTRL_SIZE 0x10000 -+#define AR71XX_CPU_BASE (AR71XX_APB_BASE + 0x00010000) -+#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000) -+#define AR71XX_UART_SIZE 0x10000 -+#define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) -+#define AR71XX_USB_CTRL_SIZE 0x10000 -+#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000) -+#define AR71XX_GPIO_SIZE 0x10000 -+#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000) -+#define AR71XX_PLL_SIZE 0x10000 -+#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) -+#define AR71XX_RESET_SIZE 0x10000 -+#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000) -+#define AR71XX_MII_SIZE 0x10000 -+#define AR71XX_SLIC_BASE (AR71XX_APB_BASE + 0x00090000) -+#define AR71XX_SLIC_SIZE 0x10000 -+#define AR71XX_DMA_BASE (AR71XX_APB_BASE + 0x000A0000) -+#define AR71XX_DMA_SIZE 0x10000 -+#define AR71XX_STEREO_BASE (AR71XX_APB_BASE + 0x000B0000) -+#define AR71XX_STEREO_SIZE 0x10000 -+ -+#define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000C0000) -+#define AR724X_PCI_CRP_SIZE 0x100 -+ -+#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000F0000) -+#define AR724X_PCI_CTRL_SIZE 0x100 -+ -+#define AR91XX_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000) -+#define AR91XX_WMAC_SIZE 0x30000 -+ -+#define AR71XX_MEM_SIZE_MIN 0x0200000 -+#define AR71XX_MEM_SIZE_MAX 0x10000000 -+ -+#define AR71XX_CPU_IRQ_BASE 0 -+#define AR71XX_MISC_IRQ_BASE 8 -+#define AR71XX_MISC_IRQ_COUNT 8 -+#define AR71XX_GPIO_IRQ_BASE 16 -+#define AR71XX_GPIO_IRQ_COUNT 32 -+#define AR71XX_PCI_IRQ_BASE 48 -+#define AR71XX_PCI_IRQ_COUNT 8 -+ -+#define AR71XX_CPU_IRQ_IP2 (AR71XX_CPU_IRQ_BASE + 2) -+#define AR71XX_CPU_IRQ_USB (AR71XX_CPU_IRQ_BASE + 3) -+#define AR71XX_CPU_IRQ_GE0 (AR71XX_CPU_IRQ_BASE + 4) -+#define AR71XX_CPU_IRQ_GE1 (AR71XX_CPU_IRQ_BASE + 5) -+#define AR71XX_CPU_IRQ_MISC (AR71XX_CPU_IRQ_BASE + 6) -+#define AR71XX_CPU_IRQ_TIMER (AR71XX_CPU_IRQ_BASE + 7) -+ -+#define AR71XX_MISC_IRQ_TIMER (AR71XX_MISC_IRQ_BASE + 0) -+#define AR71XX_MISC_IRQ_ERROR (AR71XX_MISC_IRQ_BASE + 1) -+#define AR71XX_MISC_IRQ_GPIO (AR71XX_MISC_IRQ_BASE + 2) -+#define AR71XX_MISC_IRQ_UART (AR71XX_MISC_IRQ_BASE + 3) -+#define AR71XX_MISC_IRQ_WDOG (AR71XX_MISC_IRQ_BASE + 4) -+#define AR71XX_MISC_IRQ_PERFC (AR71XX_MISC_IRQ_BASE + 5) -+#define AR71XX_MISC_IRQ_OHCI (AR71XX_MISC_IRQ_BASE + 6) -+#define AR71XX_MISC_IRQ_DMA (AR71XX_MISC_IRQ_BASE + 7) -+ -+#define AR71XX_GPIO_IRQ(_x) (AR71XX_GPIO_IRQ_BASE + (_x)) -+ -+#define AR71XX_PCI_IRQ_DEV0 (AR71XX_PCI_IRQ_BASE + 0) -+#define AR71XX_PCI_IRQ_DEV1 (AR71XX_PCI_IRQ_BASE + 1) -+#define AR71XX_PCI_IRQ_DEV2 (AR71XX_PCI_IRQ_BASE + 2) -+#define AR71XX_PCI_IRQ_CORE (AR71XX_PCI_IRQ_BASE + 4) -+ -+extern u32 ar71xx_ahb_freq; -+extern u32 ar71xx_cpu_freq; -+extern u32 ar71xx_ddr_freq; -+ -+enum ar71xx_soc_type { -+ AR71XX_SOC_UNKNOWN, -+ AR71XX_SOC_AR7130, -+ AR71XX_SOC_AR7141, -+ AR71XX_SOC_AR7161, -+ AR71XX_SOC_AR7240, -+ AR71XX_SOC_AR7241, -+ AR71XX_SOC_AR7242, -+ AR71XX_SOC_AR9130, -+ AR71XX_SOC_AR9132 -+}; -+ -+extern enum ar71xx_soc_type ar71xx_soc; -+ -+/* -+ * PLL block -+ */ -+#define AR71XX_PLL_REG_CPU_CONFIG 0x00 -+#define AR71XX_PLL_REG_SEC_CONFIG 0x04 -+#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10 -+#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14 -+ -+#define AR71XX_PLL_DIV_SHIFT 3 -+#define AR71XX_PLL_DIV_MASK 0x1f -+#define AR71XX_CPU_DIV_SHIFT 16 -+#define AR71XX_CPU_DIV_MASK 0x3 -+#define AR71XX_DDR_DIV_SHIFT 18 -+#define AR71XX_DDR_DIV_MASK 0x3 -+#define AR71XX_AHB_DIV_SHIFT 20 -+#define AR71XX_AHB_DIV_MASK 0x7 -+ -+#define AR71XX_ETH0_PLL_SHIFT 17 -+#define AR71XX_ETH1_PLL_SHIFT 19 -+ -+#define AR724X_PLL_REG_CPU_CONFIG 0x00 -+#define AR724X_PLL_REG_PCIE_CONFIG 0x18 -+ -+#define AR724X_PLL_DIV_SHIFT 0 -+#define AR724X_PLL_DIV_MASK 0x3ff -+#define AR724X_PLL_REF_DIV_SHIFT 10 -+#define AR724X_PLL_REF_DIV_MASK 0xf -+#define AR724X_AHB_DIV_SHIFT 19 -+#define AR724X_AHB_DIV_MASK 0x1 -+#define AR724X_DDR_DIV_SHIFT 22 -+#define AR724X_DDR_DIV_MASK 0x3 -+ -+#define AR91XX_PLL_REG_CPU_CONFIG 0x00 -+#define AR91XX_PLL_REG_ETH_CONFIG 0x04 -+#define AR91XX_PLL_REG_ETH0_INT_CLOCK 0x14 -+#define AR91XX_PLL_REG_ETH1_INT_CLOCK 0x18 -+ -+#define AR91XX_PLL_DIV_SHIFT 0 -+#define AR91XX_PLL_DIV_MASK 0x3ff -+#define AR91XX_DDR_DIV_SHIFT 22 -+#define AR91XX_DDR_DIV_MASK 0x3 -+#define AR91XX_AHB_DIV_SHIFT 19 -+#define AR91XX_AHB_DIV_MASK 0x1 -+ -+#define AR91XX_ETH0_PLL_SHIFT 20 -+#define AR91XX_ETH1_PLL_SHIFT 22 -+ -+extern void __iomem *ar71xx_pll_base; -+ -+static inline void ar71xx_pll_wr(unsigned reg, u32 val) -+{ -+ __raw_writel(val, ar71xx_pll_base + reg); -+} -+ -+static inline u32 ar71xx_pll_rr(unsigned reg) -+{ -+ return __raw_readl(ar71xx_pll_base + reg); -+} -+ -+/* -+ * USB_CONFIG block -+ */ -+#define USB_CTRL_REG_FLADJ 0x00 -+#define USB_CTRL_REG_CONFIG 0x04 -+ -+extern void __iomem *ar71xx_usb_ctrl_base; -+ -+static inline void ar71xx_usb_ctrl_wr(unsigned reg, u32 val) -+{ -+ __raw_writel(val, ar71xx_usb_ctrl_base + reg); -+} -+ -+static inline u32 ar71xx_usb_ctrl_rr(unsigned reg) -+{ -+ return __raw_readl(ar71xx_usb_ctrl_base + reg); -+} -+ -+/* -+ * GPIO block -+ */ -+#define GPIO_REG_OE 0x00 -+#define GPIO_REG_IN 0x04 -+#define GPIO_REG_OUT 0x08 -+#define GPIO_REG_SET 0x0c -+#define GPIO_REG_CLEAR 0x10 -+#define GPIO_REG_INT_MODE 0x14 -+#define GPIO_REG_INT_TYPE 0x18 -+#define GPIO_REG_INT_POLARITY 0x1c -+#define GPIO_REG_INT_PENDING 0x20 -+#define GPIO_REG_INT_ENABLE 0x24 -+#define GPIO_REG_FUNC 0x28 -+ -+#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17) -+#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16) -+#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13) -+#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12) -+#define AR71XX_GPIO_FUNC_UART_EN BIT(8) -+#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4) -+#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0) -+ -+#define AR71XX_GPIO_COUNT 16 -+ -+#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19) -+#define AR724X_GPIO_FUNC_SPI_EN BIT(18) -+#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14) -+#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13) -+#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12) -+#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11) -+#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10) -+#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9) -+#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8) -+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) -+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) -+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) -+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) -+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) -+#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) -+#define AR724X_GPIO_FUNC_UART_EN BIT(1) -+#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0) -+ -+#define AR724X_GPIO_COUNT 18 -+ -+#define AR91XX_GPIO_FUNC_WMAC_LED_EN BIT(22) -+#define AR91XX_GPIO_FUNC_EXP_PORT_CS_EN BIT(21) -+#define AR91XX_GPIO_FUNC_I2S_REFCLKEN BIT(20) -+#define AR91XX_GPIO_FUNC_I2S_MCKEN BIT(19) -+#define AR91XX_GPIO_FUNC_I2S1_EN BIT(18) -+#define AR91XX_GPIO_FUNC_I2S0_EN BIT(17) -+#define AR91XX_GPIO_FUNC_SLIC_EN BIT(16) -+#define AR91XX_GPIO_FUNC_UART_RTSCTS_EN BIT(9) -+#define AR91XX_GPIO_FUNC_UART_EN BIT(8) -+#define AR91XX_GPIO_FUNC_USB_CLK_EN BIT(4) -+ -+#define AR91XX_GPIO_COUNT 22 -+ -+extern void __iomem *ar71xx_gpio_base; -+ -+static inline void ar71xx_gpio_wr(unsigned reg, u32 value) -+{ -+ __raw_writel(value, ar71xx_gpio_base + reg); -+} -+ -+static inline u32 ar71xx_gpio_rr(unsigned reg) -+{ -+ return __raw_readl(ar71xx_gpio_base + reg); -+} -+ -+void ar71xx_gpio_init(void) __init; -+void ar71xx_gpio_function_enable(u32 mask); -+void ar71xx_gpio_function_disable(u32 mask); -+void ar71xx_gpio_function_setup(u32 set, u32 clear); -+ -+/* -+ * DDR_CTRL block -+ */ -+#define AR71XX_DDR_REG_PCI_WIN0 0x7c -+#define AR71XX_DDR_REG_PCI_WIN1 0x80 -+#define AR71XX_DDR_REG_PCI_WIN2 0x84 -+#define AR71XX_DDR_REG_PCI_WIN3 0x88 -+#define AR71XX_DDR_REG_PCI_WIN4 0x8c -+#define AR71XX_DDR_REG_PCI_WIN5 0x90 -+#define AR71XX_DDR_REG_PCI_WIN6 0x94 -+#define AR71XX_DDR_REG_PCI_WIN7 0x98 -+#define AR71XX_DDR_REG_FLUSH_GE0 0x9c -+#define AR71XX_DDR_REG_FLUSH_GE1 0xa0 -+#define AR71XX_DDR_REG_FLUSH_USB 0xa4 -+#define AR71XX_DDR_REG_FLUSH_PCI 0xa8 -+ -+#define AR724X_DDR_REG_FLUSH_GE0 0x7c -+#define AR724X_DDR_REG_FLUSH_GE1 0x80 -+#define AR724X_DDR_REG_FLUSH_USB 0x84 -+#define AR724X_DDR_REG_FLUSH_PCIE 0x88 -+ -+#define AR91XX_DDR_REG_FLUSH_GE0 0x7c -+#define AR91XX_DDR_REG_FLUSH_GE1 0x80 -+#define AR91XX_DDR_REG_FLUSH_USB 0x84 -+#define AR91XX_DDR_REG_FLUSH_WMAC 0x88 -+ -+#define PCI_WIN0_OFFS 0x10000000 -+#define PCI_WIN1_OFFS 0x11000000 -+#define PCI_WIN2_OFFS 0x12000000 -+#define PCI_WIN3_OFFS 0x13000000 -+#define PCI_WIN4_OFFS 0x14000000 -+#define PCI_WIN5_OFFS 0x15000000 -+#define PCI_WIN6_OFFS 0x16000000 -+#define PCI_WIN7_OFFS 0x07000000 -+ -+extern void __iomem *ar71xx_ddr_base; -+ -+static inline void ar71xx_ddr_wr(unsigned reg, u32 val) -+{ -+ __raw_writel(val, ar71xx_ddr_base + reg); -+} -+ -+static inline u32 ar71xx_ddr_rr(unsigned reg) -+{ -+ return __raw_readl(ar71xx_ddr_base + reg); -+} -+ -+void ar71xx_ddr_flush(u32 reg); -+ -+/* -+ * PCI block -+ */ -+#define AR71XX_PCI_CFG_BASE (AR71XX_PCI_MEM_BASE + PCI_WIN7_OFFS + 0x10000) -+#define AR71XX_PCI_CFG_SIZE 0x100 -+ -+#define PCI_REG_CRP_AD_CBE 0x00 -+#define PCI_REG_CRP_WRDATA 0x04 -+#define PCI_REG_CRP_RDDATA 0x08 -+#define PCI_REG_CFG_AD 0x0c -+#define PCI_REG_CFG_CBE 0x10 -+#define PCI_REG_CFG_WRDATA 0x14 -+#define PCI_REG_CFG_RDDATA 0x18 -+#define PCI_REG_PCI_ERR 0x1c -+#define PCI_REG_PCI_ERR_ADDR 0x20 -+#define PCI_REG_AHB_ERR 0x24 -+#define PCI_REG_AHB_ERR_ADDR 0x28 -+ -+#define PCI_CRP_CMD_WRITE 0x00010000 -+#define PCI_CRP_CMD_READ 0x00000000 -+#define PCI_CFG_CMD_READ 0x0000000a -+#define PCI_CFG_CMD_WRITE 0x0000000b -+ -+#define PCI_IDSEL_ADL_START 17 -+ -+#define AR724X_PCI_CFG_BASE (AR71XX_PCI_MEM_BASE + 0x4000000) -+#define AR724X_PCI_CFG_SIZE 0x1000 -+ -+#define AR724X_PCI_REG_APP 0x00 -+#define AR724X_PCI_REG_RESET 0x18 -+#define AR724X_PCI_REG_INT_STATUS 0x4c -+#define AR724X_PCI_REG_INT_MASK 0x50 -+ -+#define AR724X_PCI_APP_LTSSM_ENABLE BIT(0) -+#define AR724X_PCI_RESET_LINK_UP BIT(0) -+ -+#define AR724X_PCI_INT_DEV0 BIT(14) -+ -+/* -+ * RESET block -+ */ -+#define AR71XX_RESET_REG_TIMER 0x00 -+#define AR71XX_RESET_REG_TIMER_RELOAD 0x04 -+#define AR71XX_RESET_REG_WDOG_CTRL 0x08 -+#define AR71XX_RESET_REG_WDOG 0x0c -+#define AR71XX_RESET_REG_MISC_INT_STATUS 0x10 -+#define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14 -+#define AR71XX_RESET_REG_PCI_INT_STATUS 0x18 -+#define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c -+#define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20 -+#define AR71XX_RESET_REG_RESET_MODULE 0x24 -+#define AR71XX_RESET_REG_PERFC_CTRL 0x2c -+#define AR71XX_RESET_REG_PERFC0 0x30 -+#define AR71XX_RESET_REG_PERFC1 0x34 -+#define AR71XX_RESET_REG_REV_ID 0x90 -+ -+#define AR91XX_RESET_REG_GLOBAL_INT_STATUS 0x18 -+#define AR91XX_RESET_REG_RESET_MODULE 0x1c -+#define AR91XX_RESET_REG_PERF_CTRL 0x20 -+#define AR91XX_RESET_REG_PERFC0 0x24 -+#define AR91XX_RESET_REG_PERFC1 0x28 -+ -+#define AR724X_RESET_REG_RESET_MODULE 0x1c -+ -+#define WDOG_CTRL_LAST_RESET BIT(31) -+#define WDOG_CTRL_ACTION_MASK 3 -+#define WDOG_CTRL_ACTION_NONE 0 /* no action */ -+#define WDOG_CTRL_ACTION_GPI 1 /* general purpose interrupt */ -+#define WDOG_CTRL_ACTION_NMI 2 /* NMI */ -+#define WDOG_CTRL_ACTION_FCR 3 /* full chip reset */ -+ -+#define MISC_INT_DMA BIT(7) -+#define MISC_INT_OHCI BIT(6) -+#define MISC_INT_PERFC BIT(5) -+#define MISC_INT_WDOG BIT(4) -+#define MISC_INT_UART BIT(3) -+#define MISC_INT_GPIO BIT(2) -+#define MISC_INT_ERROR BIT(1) -+#define MISC_INT_TIMER BIT(0) -+ -+#define PCI_INT_CORE BIT(4) -+#define PCI_INT_DEV2 BIT(2) -+#define PCI_INT_DEV1 BIT(1) -+#define PCI_INT_DEV0 BIT(0) -+ -+#define RESET_MODULE_EXTERNAL BIT(28) -+#define RESET_MODULE_FULL_CHIP BIT(24) -+#define RESET_MODULE_AMBA2WMAC BIT(22) -+#define RESET_MODULE_CPU_NMI BIT(21) -+#define RESET_MODULE_CPU_COLD BIT(20) -+#define RESET_MODULE_DMA BIT(19) -+#define RESET_MODULE_SLIC BIT(18) -+#define RESET_MODULE_STEREO BIT(17) -+#define RESET_MODULE_DDR BIT(16) -+#define RESET_MODULE_GE1_MAC BIT(13) -+#define RESET_MODULE_GE1_PHY BIT(12) -+#define RESET_MODULE_USBSUS_OVERRIDE BIT(10) -+#define RESET_MODULE_GE0_MAC BIT(9) -+#define RESET_MODULE_GE0_PHY BIT(8) -+#define RESET_MODULE_USB_OHCI_DLL BIT(6) -+#define RESET_MODULE_USB_HOST BIT(5) -+#define RESET_MODULE_USB_PHY BIT(4) -+#define RESET_MODULE_USB_OHCI_DLL_7240 BIT(3) -+#define RESET_MODULE_PCI_BUS BIT(1) -+#define RESET_MODULE_PCI_CORE BIT(0) -+ -+#define AR724X_RESET_GE1_MDIO BIT(23) -+#define AR724X_RESET_GE0_MDIO BIT(22) -+#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10) -+#define AR724X_RESET_PCIE_PHY BIT(7) -+#define AR724X_RESET_PCIE BIT(6) -+ -+#define REV_ID_MAJOR_MASK 0xfff0 -+#define REV_ID_MAJOR_AR71XX 0x00a0 -+#define REV_ID_MAJOR_AR913X 0x00b0 -+#define REV_ID_MAJOR_AR7240 0x00c0 -+#define REV_ID_MAJOR_AR7241 0x0100 -+#define REV_ID_MAJOR_AR7242 0x1100 -+ -+#define AR71XX_REV_ID_MINOR_MASK 0x3 -+#define AR71XX_REV_ID_MINOR_AR7130 0x0 -+#define AR71XX_REV_ID_MINOR_AR7141 0x1 -+#define AR71XX_REV_ID_MINOR_AR7161 0x2 -+#define AR71XX_REV_ID_REVISION_MASK 0x3 -+#define AR71XX_REV_ID_REVISION_SHIFT 2 -+ -+#define AR91XX_REV_ID_MINOR_MASK 0x3 -+#define AR91XX_REV_ID_MINOR_AR9130 0x0 -+#define AR91XX_REV_ID_MINOR_AR9132 0x1 -+#define AR91XX_REV_ID_REVISION_MASK 0x3 -+#define AR91XX_REV_ID_REVISION_SHIFT 2 -+ -+#define AR724X_REV_ID_REVISION_MASK 0x3 -+ -+extern void __iomem *ar71xx_reset_base; -+ -+static inline void ar71xx_reset_wr(unsigned reg, u32 val) -+{ -+ __raw_writel(val, ar71xx_reset_base + reg); -+} -+ -+static inline u32 ar71xx_reset_rr(unsigned reg) -+{ -+ return __raw_readl(ar71xx_reset_base + reg); -+} -+ -+void ar71xx_device_stop(u32 mask); -+void ar71xx_device_start(u32 mask); -+int ar71xx_device_stopped(u32 mask); -+ -+/* -+ * SPI block -+ */ -+#define SPI_REG_FS 0x00 /* Function Select */ -+#define SPI_REG_CTRL 0x04 /* SPI Control */ -+#define SPI_REG_IOC 0x08 /* SPI I/O Control */ -+#define SPI_REG_RDS 0x0c /* Read Data Shift */ -+ -+#define SPI_FS_GPIO BIT(0) /* Enable GPIO mode */ -+ -+#define SPI_CTRL_RD BIT(6) /* Remap Disable */ -+#define SPI_CTRL_DIV_MASK 0x3f -+ -+#define SPI_IOC_DO BIT(0) /* Data Out pin */ -+#define SPI_IOC_CLK BIT(8) /* CLK pin */ -+#define SPI_IOC_CS(n) BIT(16 + (n)) -+#define SPI_IOC_CS0 SPI_IOC_CS(0) -+#define SPI_IOC_CS1 SPI_IOC_CS(1) -+#define SPI_IOC_CS2 SPI_IOC_CS(2) -+#define SPI_IOC_CS_ALL (SPI_IOC_CS0 | SPI_IOC_CS1 | SPI_IOC_CS2) -+ -+void ar71xx_flash_acquire(void); -+void ar71xx_flash_release(void); -+ -+/* -+ * MII_CTRL block -+ */ -+#define MII_REG_MII0_CTRL 0x00 -+#define MII_REG_MII1_CTRL 0x04 -+ -+#define MII0_CTRL_IF_GMII 0 -+#define MII0_CTRL_IF_MII 1 -+#define MII0_CTRL_IF_RGMII 2 -+#define MII0_CTRL_IF_RMII 3 -+ -+#define MII1_CTRL_IF_RGMII 0 -+#define MII1_CTRL_IF_RMII 1 -+ -+#endif /* __ASSEMBLER__ */ -+ -+#endif /* __ASM_MACH_AR71XX_H */ -diff -Nur linux-2.6.36.orig/arch/mips/include/asm/mach-ar71xx/ar91xx_flash.h linux-2.6.36/arch/mips/include/asm/mach-ar71xx/ar91xx_flash.h ---- linux-2.6.36.orig/arch/mips/include/asm/mach-ar71xx/ar91xx_flash.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/include/asm/mach-ar71xx/ar91xx_flash.h 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,26 @@ -+/* -+ * AR91xx parallel flash driver platform data definitions -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef __AR91XX_FLASH_H -+#define __AR91XX_FLASH_H -+ -+struct mtd_partition; -+ -+struct ar91xx_flash_platform_data { -+ unsigned int width; -+ u8 is_shared:1; -+#ifdef CONFIG_MTD_PARTITIONS -+ unsigned int nr_parts; -+ struct mtd_partition *parts; -+#endif -+}; -+ -+#endif /* __AR91XX_FLASH_H */ -diff -Nur linux-2.6.36.orig/arch/mips/include/asm/mach-ar71xx/cpu-feature-overrides.h linux-2.6.36/arch/mips/include/asm/mach-ar71xx/cpu-feature-overrides.h ---- linux-2.6.36.orig/arch/mips/include/asm/mach-ar71xx/cpu-feature-overrides.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/include/asm/mach-ar71xx/cpu-feature-overrides.h 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,56 @@ -+/* -+ * Atheros AR71xx specific CPU feature overrides -+ * -+ * Copyright (C) 2008 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This file was derived from: include/asm-mips/cpu-features.h -+ * Copyright (C) 2003, 2004 Ralf Baechle -+ * Copyright (C) 2004 Maciej W. Rozycki -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ */ -+#ifndef __ASM_MACH_AR71XX_CPU_FEATURE_OVERRIDES_H -+#define __ASM_MACH_AR71XX_CPU_FEATURE_OVERRIDES_H -+ -+#define cpu_has_tlb 1 -+#define cpu_has_4kex 1 -+#define cpu_has_3k_cache 0 -+#define cpu_has_4k_cache 1 -+#define cpu_has_tx39_cache 0 -+#define cpu_has_sb1_cache 0 -+#define cpu_has_fpu 0 -+#define cpu_has_32fpr 0 -+#define cpu_has_counter 1 -+#define cpu_has_watch 1 -+#define cpu_has_divec 1 -+ -+#define cpu_has_prefetch 1 -+#define cpu_has_ejtag 1 -+#define cpu_has_llsc 1 -+ -+#define cpu_has_mips16 1 -+#define cpu_has_mdmx 0 -+#define cpu_has_mips3d 0 -+#define cpu_has_smartmips 0 -+ -+#define cpu_has_mips32r1 1 -+#define cpu_has_mips32r2 1 -+#define cpu_has_mips64r1 0 -+#define cpu_has_mips64r2 0 -+ -+#define cpu_has_dsp 0 -+#define cpu_has_mipsmt 0 -+ -+#define cpu_has_64bits 0 -+#define cpu_has_64bit_zero_reg 0 -+#define cpu_has_64bit_gp_regs 0 -+#define cpu_has_64bit_addresses 0 -+ -+#define cpu_dcache_line_size() 32 -+#define cpu_icache_line_size() 32 -+ -+#endif /* __ASM_MACH_AR71XX_CPU_FEATURE_OVERRIDES_H */ -diff -Nur linux-2.6.36.orig/arch/mips/include/asm/mach-ar71xx/gpio.h linux-2.6.36/arch/mips/include/asm/mach-ar71xx/gpio.h ---- linux-2.6.36.orig/arch/mips/include/asm/mach-ar71xx/gpio.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/include/asm/mach-ar71xx/gpio.h 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,53 @@ -+/* -+ * Atheros AR71xx GPIO API definitions -+ * -+ * Copyright (C) 2008 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ */ -+ -+#ifndef __ASM_MACH_AR71XX_GPIO_H -+#define __ASM_MACH_AR71XX_GPIO_H -+ -+#define ARCH_NR_GPIOS 64 -+#include -+ -+#include -+ -+extern unsigned long ar71xx_gpio_count; -+extern void __ar71xx_gpio_set_value(unsigned gpio, int value); -+extern int __ar71xx_gpio_get_value(unsigned gpio); -+ -+static inline int gpio_to_irq(unsigned gpio) -+{ -+ return AR71XX_GPIO_IRQ(gpio); -+} -+ -+static inline int irq_to_gpio(unsigned irq) -+{ -+ return irq - AR71XX_GPIO_IRQ_BASE; -+} -+ -+static inline int gpio_get_value(unsigned gpio) -+{ -+ if (gpio < ar71xx_gpio_count) -+ return __ar71xx_gpio_get_value(gpio); -+ -+ return __gpio_get_value(gpio); -+} -+ -+static inline void gpio_set_value(unsigned gpio, int value) -+{ -+ if (gpio < ar71xx_gpio_count) -+ __ar71xx_gpio_set_value(gpio, value); -+ else -+ __gpio_set_value(gpio, value); -+} -+ -+#define gpio_cansleep __gpio_cansleep -+ -+#endif /* __ASM_MACH_AR71XX_GPIO_H */ -diff -Nur linux-2.6.36.orig/arch/mips/include/asm/mach-ar71xx/irq.h linux-2.6.36/arch/mips/include/asm/mach-ar71xx/irq.h ---- linux-2.6.36.orig/arch/mips/include/asm/mach-ar71xx/irq.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/include/asm/mach-ar71xx/irq.h 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,17 @@ -+/* -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+#ifndef __ASM_MACH_AR71XX_IRQ_H -+#define __ASM_MACH_AR71XX_IRQ_H -+ -+#define MIPS_CPU_IRQ_BASE 0 -+#define NR_IRQS 56 -+ -+#include_next -+ -+#endif /* __ASM_MACH_AR71XX_IRQ_H */ -diff -Nur linux-2.6.36.orig/arch/mips/include/asm/mach-ar71xx/kernel-entry-init.h linux-2.6.36/arch/mips/include/asm/mach-ar71xx/kernel-entry-init.h ---- linux-2.6.36.orig/arch/mips/include/asm/mach-ar71xx/kernel-entry-init.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/include/asm/mach-ar71xx/kernel-entry-init.h 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,32 @@ -+/* -+ * Atheros AR71xx specific kernel entry setup -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ */ -+#ifndef __ASM_MACH_AR71XX_KERNEL_ENTRY_H -+#define __ASM_MACH_AR71XX_KERNEL_ENTRY_H -+ -+ /* -+ * Some bootloaders set the 'Kseg0 coherency algorithm' to -+ * 'Cacheable, noncoherent, write-through, no write allocate' -+ * and this cause performance issues. Let's go and change it to -+ * 'Cacheable, noncoherent, write-back, write allocate' -+ */ -+ .macro kernel_entry_setup -+ mfc0 t0, CP0_CONFIG -+ li t1, ~CONF_CM_CMASK -+ and t0, t1 -+ ori t0, CONF_CM_CACHABLE_NONCOHERENT -+ mtc0 t0, CP0_CONFIG -+ nop -+ .endm -+ -+ .macro smp_slave_setup -+ .endm -+ -+#endif /* __ASM_MACH_AR71XX_KERNEL_ENTRY_H */ -diff -Nur linux-2.6.36.orig/arch/mips/include/asm/mach-ar71xx/mach-rb750.h linux-2.6.36/arch/mips/include/asm/mach-ar71xx/mach-rb750.h ---- linux-2.6.36.orig/arch/mips/include/asm/mach-ar71xx/mach-rb750.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/include/asm/mach-ar71xx/mach-rb750.h 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,66 @@ -+/* -+ * MikroTik RouterBOARD 750 definitions -+ * -+ * Copyright (C) 2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+#ifndef _MACH_RB750_H -+#define _MACH_RB750_H -+ -+#include -+ -+#define RB750_GPIO_LVC573_LE 0 /* Latch enable on LVC573 */ -+#define RB750_GPIO_NAND_IO0 1 /* NAND I/O 0 */ -+#define RB750_GPIO_NAND_IO1 2 /* NAND I/O 1 */ -+#define RB750_GPIO_NAND_IO2 3 /* NAND I/O 2 */ -+#define RB750_GPIO_NAND_IO3 4 /* NAND I/O 3 */ -+#define RB750_GPIO_NAND_IO4 5 /* NAND I/O 4 */ -+#define RB750_GPIO_NAND_IO5 6 /* NAND I/O 5 */ -+#define RB750_GPIO_NAND_IO6 7 /* NAND I/O 6 */ -+#define RB750_GPIO_NAND_IO7 8 /* NAND I/O 7 */ -+#define RB750_GPIO_NAND_NCE 11 /* NAND Chip Enable (active low) */ -+#define RB750_GPIO_NAND_RDY 12 /* NAND Ready */ -+#define RB750_GPIO_NAND_CLE 14 /* NAND Command Latch Enable */ -+#define RB750_GPIO_NAND_ALE 15 /* NAND Address Latch Enable */ -+#define RB750_GPIO_NAND_NRE 16 /* NAND Read Enable (active low) */ -+#define RB750_GPIO_NAND_NWE 17 /* NAND Write Enable (active low) */ -+ -+#define RB750_GPIO_BTN_RESET 1 -+#define RB750_GPIO_SPI_CS0 2 -+#define RB750_GPIO_LED_ACT 12 -+#define RB750_GPIO_LED_PORT1 13 -+#define RB750_GPIO_LED_PORT2 14 -+#define RB750_GPIO_LED_PORT3 15 -+#define RB750_GPIO_LED_PORT4 16 -+#define RB750_GPIO_LED_PORT5 17 -+ -+#define RB750_LED_ACT BIT(RB750_GPIO_LED_ACT) -+#define RB750_LED_PORT1 BIT(RB750_GPIO_LED_PORT1) -+#define RB750_LED_PORT2 BIT(RB750_GPIO_LED_PORT2) -+#define RB750_LED_PORT3 BIT(RB750_GPIO_LED_PORT3) -+#define RB750_LED_PORT4 BIT(RB750_GPIO_LED_PORT4) -+#define RB750_LED_PORT5 BIT(RB750_GPIO_LED_PORT5) -+ -+#define RB750_LVC573_LE BIT(RB750_GPIO_LVC573_LE) -+ -+#define RB750_LED_BITS (RB750_LED_PORT1 | RB750_LED_PORT2 | RB750_LED_PORT3 | \ -+ RB750_LED_PORT4 | RB750_LED_PORT5 | RB750_LED_ACT) -+ -+struct rb750_led_data { -+ char *name; -+ char *default_trigger; -+ u32 mask; -+ int active_low; -+}; -+ -+struct rb750_led_platform_data { -+ int num_leds; -+ struct rb750_led_data *leds; -+}; -+ -+int rb750_latch_change(u32 mask_clr, u32 mask_set); -+ -+#endif /* _MACH_RB750_H */ -\ No newline at end of file -diff -Nur linux-2.6.36.orig/arch/mips/include/asm/mach-ar71xx/mangle-port.h linux-2.6.36/arch/mips/include/asm/mach-ar71xx/mangle-port.h ---- linux-2.6.36.orig/arch/mips/include/asm/mach-ar71xx/mangle-port.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/include/asm/mach-ar71xx/mangle-port.h 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,45 @@ -+/* -+ * Copyright (C) 2008 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This file was derived from: inlude/asm-mips/mach-generic/mangle-port.h -+ * Copyright (C) 2003, 2004 Ralf Baechle -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef __ASM_MACH_AR71XX_MANGLE_PORT_H -+#define __ASM_MACH_AR71XX_MANGLE_PORT_H -+ -+#define __swizzle_addr_b(port) ((port) ^ 3) -+#define __swizzle_addr_w(port) ((port) ^ 2) -+#define __swizzle_addr_l(port) (port) -+#define __swizzle_addr_q(port) (port) -+ -+#if defined(CONFIG_SWAP_IO_SPACE) -+ -+# define ioswabb(a, x) (x) -+# define __mem_ioswabb(a, x) (x) -+# define ioswabw(a, x) le16_to_cpu(x) -+# define __mem_ioswabw(a, x) (x) -+# define ioswabl(a, x) le32_to_cpu(x) -+# define __mem_ioswabl(a, x) (x) -+# define ioswabq(a, x) le64_to_cpu(x) -+# define __mem_ioswabq(a, x) (x) -+ -+#else -+ -+# define ioswabb(a, x) (x) -+# define __mem_ioswabb(a, x) (x) -+# define ioswabw(a, x) (x) -+# define __mem_ioswabw(a, x) cpu_to_le16(x) -+# define ioswabl(a, x) (x) -+# define __mem_ioswabl(a, x) cpu_to_le32(x) -+# define ioswabq(a, x) (x) -+# define __mem_ioswabq(a, x) cpu_to_le64(x) -+ -+#endif -+ -+#endif /* __ASM_MACH_AR71XX_MANGLE_PORT_H */ -diff -Nur linux-2.6.36.orig/arch/mips/include/asm/mach-ar71xx/pci.h linux-2.6.36/arch/mips/include/asm/mach-ar71xx/pci.h ---- linux-2.6.36.orig/arch/mips/include/asm/mach-ar71xx/pci.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/include/asm/mach-ar71xx/pci.h 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,39 @@ -+/* -+ * Atheros AR71xx SoC specific PCI definitions -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef __ASM_MACH_AR71XX_PCI_H -+#define __ASM_MACH_AR71XX_PCI_H -+ -+struct pci_dev; -+ -+struct ar71xx_pci_irq { -+ int irq; -+ u8 slot; -+ u8 pin; -+}; -+ -+extern int (*ar71xx_pci_plat_dev_init)(struct pci_dev *dev); -+extern unsigned ar71xx_pci_nr_irqs __initdata; -+extern struct ar71xx_pci_irq *ar71xx_pci_irq_map __initdata; -+ -+int ar71xx_pcibios_map_irq(const struct pci_dev *dev, -+ uint8_t slot, uint8_t pin) __init; -+int ar71xx_pcibios_init(void) __init; -+ -+int ar71xx_pci_be_handler(int is_fixup); -+ -+int ar724x_pcibios_map_irq(const struct pci_dev *dev, -+ uint8_t slot, uint8_t pin) __init; -+int ar724x_pcibios_init(void) __init; -+ -+int ar71xx_pci_init(unsigned nr_irqs, struct ar71xx_pci_irq *map) __init; -+ -+#endif /* __ASM_MACH_AR71XX_PCI_H */ -diff -Nur linux-2.6.36.orig/arch/mips/include/asm/mach-ar71xx/platform.h linux-2.6.36/arch/mips/include/asm/mach-ar71xx/platform.h ---- linux-2.6.36.orig/arch/mips/include/asm/mach-ar71xx/platform.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/include/asm/mach-ar71xx/platform.h 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,61 @@ -+/* -+ * Atheros AR71xx SoC specific platform data definitions -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef __ASM_MACH_AR71XX_PLATFORM_H -+#define __ASM_MACH_AR71XX_PLATFORM_H -+ -+#include -+#include -+#include -+#include -+ -+struct ag71xx_platform_data { -+ phy_interface_t phy_if_mode; -+ u32 phy_mask; -+ int speed; -+ int duplex; -+ u32 reset_bit; -+ u32 mii_if; -+ u8 mac_addr[ETH_ALEN]; -+ struct device *mii_bus_dev; -+ -+ u8 has_gbit:1; -+ u8 is_ar91xx:1; -+ u8 is_ar724x:1; -+ u8 has_ar8216:1; -+ -+ void (* ddr_flush)(void); -+ void (* set_pll)(int speed); -+ -+ u32 fifo_cfg1; -+ u32 fifo_cfg2; -+ u32 fifo_cfg3; -+}; -+ -+struct ag71xx_mdio_platform_data { -+ u32 phy_mask; -+ int is_ar7240; -+}; -+ -+struct ar71xx_ehci_platform_data { -+ u8 is_ar91xx; -+}; -+ -+struct ar71xx_spi_platform_data { -+ unsigned bus_num; -+ unsigned num_chipselect; -+ u32 (*get_ioc_base)(u8 chip_select, int cs_high, int is_on); -+}; -+ -+#define AR71XX_SPI_CS_INACTIVE 0 -+#define AR71XX_SPI_CS_ACTIVE 1 -+ -+#endif /* __ASM_MACH_AR71XX_PLATFORM_H */ -diff -Nur linux-2.6.36.orig/arch/mips/include/asm/mach-ar71xx/war.h linux-2.6.36/arch/mips/include/asm/mach-ar71xx/war.h ---- linux-2.6.36.orig/arch/mips/include/asm/mach-ar71xx/war.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/include/asm/mach-ar71xx/war.h 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,25 @@ -+/* -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle -+ */ -+#ifndef __ASM_MACH_AR71XX_WAR_H -+#define __ASM_MACH_AR71XX_WAR_H -+ -+#define R4600_V1_INDEX_ICACHEOP_WAR 0 -+#define R4600_V1_HIT_CACHEOP_WAR 0 -+#define R4600_V2_HIT_CACHEOP_WAR 0 -+#define R5432_CP0_INTERRUPT_WAR 0 -+#define BCM1250_M3_WAR 0 -+#define SIBYTE_1956_WAR 0 -+#define MIPS4K_ICACHE_REFILL_WAR 0 -+#define MIPS_CACHE_SYNC_WAR 0 -+#define TX49XX_ICACHE_INDEX_INV_WAR 0 -+#define RM9000_CDEX_SMP_WAR 0 -+#define ICACHE_REFILLS_WORKAROUND_WAR 0 -+#define R10000_LLSC_WAR 0 -+#define MIPS34K_MISSED_ITLB_WAR 0 -+ -+#endif /* __ASM_MACH_AR71XX_WAR_H */ -diff -Nur linux-2.6.36.orig/arch/mips/include/asm/mips_machine.h linux-2.6.36/arch/mips/include/asm/mips_machine.h ---- linux-2.6.36.orig/arch/mips/include/asm/mips_machine.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/include/asm/mips_machine.h 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,54 @@ -+/* -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ */ -+ -+#ifndef __ASM_MIPS_MACHINE_H -+#define __ASM_MIPS_MACHINE_H -+ -+#include -+#include -+ -+#include -+ -+struct mips_machine { -+ unsigned long mach_type; -+ char *mach_id; -+ char *mach_name; -+ void (*mach_setup)(void); -+ struct list_head list; -+}; -+ -+void mips_machine_register(struct mips_machine *) __init; -+void mips_machine_setup(void) __init; -+int mips_machtype_setup(char *id) __init; -+void mips_machine_set_name(char *name) __init; -+ -+extern char *mips_machine_name; -+ -+#define MIPS_MACHINE(_type, _id, _name, _setup) \ -+static const char machine_name_##_type[] __initconst \ -+ __aligned(1) = _name; \ -+static const char machine_id_##_type[] __initconst \ -+ __aligned(1) = _id; \ -+static struct mips_machine machine_##_type __initdata = \ -+{ \ -+ .mach_type = _type, \ -+ .mach_id = (char *) machine_id_##_type, \ -+ .mach_name = (char *) machine_name_##_type, \ -+ .mach_setup = _setup, \ -+}; \ -+ \ -+static int __init register_machine_##_type(void) \ -+{ \ -+ mips_machine_register(&machine_##_type); \ -+ return 0; \ -+} \ -+ \ -+pure_initcall(register_machine_##_type) -+ -+#endif /* __ASM_MIPS_MACHINE_H */ -diff -Nur linux-2.6.36.orig/arch/mips/include/asm/time.h linux-2.6.36/arch/mips/include/asm/time.h ---- linux-2.6.36.orig/arch/mips/include/asm/time.h 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/arch/mips/include/asm/time.h 2010-12-17 18:34:51.000000000 +0100 -@@ -52,6 +52,7 @@ - */ - #ifdef CONFIG_CEVT_R4K_LIB - extern unsigned int __weak get_c0_compare_int(void); -+extern unsigned int __weak get_c0_compare_irq(void); - extern int r4k_clockevent_init(void); - #endif - -diff -Nur linux-2.6.36.orig/arch/mips/kernel/Makefile linux-2.6.36/arch/mips/kernel/Makefile ---- linux-2.6.36.orig/arch/mips/kernel/Makefile 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/arch/mips/kernel/Makefile 2010-12-17 18:34:51.000000000 +0100 -@@ -94,6 +94,7 @@ - - obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o - obj-$(CONFIG_EARLY_PRINTK) += early_printk.o -+obj-$(CONFIG_MIPS_MACHINE) += mips_machine.o - obj-$(CONFIG_SPINLOCK_TEST) += spinlock_test.o - - CFLAGS_cpu-bugs64.o = $(shell if $(CC) $(KBUILD_CFLAGS) -Wa,-mdaddi -c -o /dev/null -xc /dev/null >/dev/null 2>&1; then echo "-DHAVE_AS_SET_DADDI"; fi) -diff -Nur linux-2.6.36.orig/arch/mips/kernel/mips_machine.c linux-2.6.36/arch/mips/kernel/mips_machine.c ---- linux-2.6.36.orig/arch/mips/kernel/mips_machine.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/kernel/mips_machine.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,121 @@ -+/* -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ */ -+#include -+#include -+#include -+ -+#include -+ -+static struct list_head mips_machines __initdata = -+ LIST_HEAD_INIT(mips_machines); -+static char *mips_machid __initdata; -+ -+char *mips_machine_name = "Unknown"; -+ -+static struct mips_machine * __init mips_machine_find(unsigned long machtype) -+{ -+ struct list_head *this; -+ -+ list_for_each(this, &mips_machines) { -+ struct mips_machine *mach; -+ -+ mach = list_entry(this, struct mips_machine, list); -+ if (mach->mach_type == machtype) -+ return mach; -+ } -+ -+ return NULL; -+} -+ -+void __init mips_machine_register(struct mips_machine *mach) -+{ -+ list_add_tail(&mach->list, &mips_machines); -+} -+ -+void __init mips_machine_set_name(char *name) -+{ -+ unsigned int len; -+ char *p; -+ -+ if (name == NULL) -+ return; -+ -+ len = strlen(name); -+ p = kmalloc(len + 1, GFP_KERNEL); -+ if (p) { -+ strncpy(p, name, len); -+ p[len] = '\0'; -+ mips_machine_name = p; -+ } else { -+ printk(KERN_WARNING "MIPS: no memory for machine_name\n"); -+ } -+} -+ -+void __init mips_machine_setup(void) -+{ -+ struct mips_machine *mach; -+ -+ mach = mips_machine_find(mips_machtype); -+ if (!mach) { -+ printk(KERN_WARNING "MIPS: no machine registered for " -+ "machtype %lu\n", mips_machtype); -+ return; -+ } -+ -+ mips_machine_set_name(mach->mach_name); -+ printk(KERN_NOTICE "MIPS: machine is %s\n", mips_machine_name); -+ -+ if (mach->mach_setup) -+ mach->mach_setup(); -+} -+ -+int __init mips_machtype_setup(char *id) -+{ -+ if (mips_machid == NULL) -+ mips_machid = id; -+ -+ return 1; -+} -+ -+__setup("machtype=", mips_machtype_setup); -+ -+static int __init mips_machtype_init(void) -+{ -+ struct list_head *this; -+ struct mips_machine *mach; -+ -+ if (mips_machid == NULL) -+ return 0; -+ -+ list_for_each(this, &mips_machines) { -+ mach = list_entry(this, struct mips_machine, list); -+ if (mach->mach_id == NULL) -+ continue; -+ -+ if (strcmp(mach->mach_id, mips_machid) == 0) { -+ mips_machtype = mach->mach_type; -+ return 0; -+ } -+ } -+ -+ printk(KERN_WARNING -+ "MIPS: no machine found for id: '%s', registered machines:\n", -+ mips_machid); -+ printk(KERN_WARNING "%32s %s\n", "id", "name"); -+ -+ list_for_each(this, &mips_machines) { -+ mach = list_entry(this, struct mips_machine, list); -+ printk(KERN_WARNING "%32s %s\n", -+ mach->mach_id ? mach->mach_id : "", mach->mach_name); -+ } -+ -+ return 0; -+} -+ -+core_initcall(mips_machtype_init); -diff -Nur linux-2.6.36.orig/arch/mips/kernel/proc.c linux-2.6.36/arch/mips/kernel/proc.c ---- linux-2.6.36.orig/arch/mips/kernel/proc.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/arch/mips/kernel/proc.c 2010-12-17 18:34:51.000000000 +0100 -@@ -12,6 +12,7 @@ - #include - #include - #include -+#include - - unsigned int vced_count, vcei_count; - -@@ -31,8 +32,12 @@ - /* - * For the first processor also print the system type - */ -- if (n == 0) -+ if (n == 0) { - seq_printf(m, "system type\t\t: %s\n", get_system_type()); -+#ifdef CONFIG_MIPS_MACHINE -+ seq_printf(m, "machine\t\t\t: %s\n", mips_machine_name); -+#endif -+ } - - seq_printf(m, "processor\t\t: %ld\n", n); - sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n", -diff -Nur linux-2.6.36.orig/arch/mips/kernel/traps.c linux-2.6.36/arch/mips/kernel/traps.c ---- linux-2.6.36.orig/arch/mips/kernel/traps.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/arch/mips/kernel/traps.c 2010-12-17 18:34:51.000000000 +0100 -@@ -52,6 +52,7 @@ - #include - #include - #include -+#include - #include - - extern void check_wait(void); -@@ -1539,6 +1540,8 @@ - if (cpu_has_mips_r2) { - cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP; - cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7; -+ if (get_c0_compare_irq) -+ cp0_compare_irq = get_c0_compare_irq(); - cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7; - if (cp0_perfcount_irq == cp0_compare_irq) - cp0_perfcount_irq = -1; -diff -Nur linux-2.6.36.orig/arch/mips/pci/Makefile linux-2.6.36/arch/mips/pci/Makefile ---- linux-2.6.36.orig/arch/mips/pci/Makefile 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/arch/mips/pci/Makefile 2010-12-17 18:34:51.000000000 +0100 -@@ -18,6 +18,7 @@ - obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o - obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \ - ops-bcm63xx.o -+obj-$(CONFIG_ATHEROS_AR71XX) += pci-ar71xx.o pci-ar724x.o - - # - # These are still pretty much in the old state, watch, go blind. -diff -Nur linux-2.6.36.orig/arch/mips/pci/pci-ar71xx.c linux-2.6.36/arch/mips/pci/pci-ar71xx.c ---- linux-2.6.36.orig/arch/mips/pci/pci-ar71xx.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/pci/pci-ar71xx.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,409 @@ -+/* -+ * Atheros AR71xx PCI host controller driver -+ * -+ * Copyright (C) 2008-2010 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#undef DEBUG -+#ifdef DEBUG -+#define DBG(fmt, args...) printk(KERN_DEBUG fmt, ## args) -+#else -+#define DBG(fmt, args...) -+#endif -+ -+#define AR71XX_PCI_DELAY 100 /* msecs */ -+ -+#if 0 -+#define PCI_IDSEL_BASE PCI_IDSEL_ADL_START -+#else -+#define PCI_IDSEL_BASE 0 -+#endif -+ -+static void __iomem *ar71xx_pcicfg_base; -+static DEFINE_SPINLOCK(ar71xx_pci_lock); -+static int ar71xx_pci_fixup_enable; -+ -+static inline void ar71xx_pci_delay(void) -+{ -+ mdelay(AR71XX_PCI_DELAY); -+} -+ -+/* Byte lane enable bits */ -+static u8 ble_table[4][4] = { -+ {0x0, 0xf, 0xf, 0xf}, -+ {0xe, 0xd, 0xb, 0x7}, -+ {0xc, 0xf, 0x3, 0xf}, -+ {0xf, 0xf, 0xf, 0xf}, -+}; -+ -+static inline u32 ar71xx_pci_get_ble(int where, int size, int local) -+{ -+ u32 t; -+ -+ t = ble_table[size & 3][where & 3]; -+ BUG_ON(t == 0xf); -+ t <<= (local) ? 20 : 4; -+ return t; -+} -+ -+static inline u32 ar71xx_pci_bus_addr(struct pci_bus *bus, unsigned int devfn, -+ int where) -+{ -+ u32 ret; -+ -+ if (!bus->number) { -+ /* type 0 */ -+ ret = (1 << (PCI_IDSEL_BASE + PCI_SLOT(devfn))) -+ | (PCI_FUNC(devfn) << 8) | (where & ~3); -+ } else { -+ /* type 1 */ -+ ret = (bus->number << 16) | (PCI_SLOT(devfn) << 11) -+ | (PCI_FUNC(devfn) << 8) | (where & ~3) | 1; -+ } -+ -+ return ret; -+} -+ -+int ar71xx_pci_be_handler(int is_fixup) -+{ -+ void __iomem *base = ar71xx_pcicfg_base; -+ u32 pci_err; -+ u32 ahb_err; -+ -+ pci_err = __raw_readl(base + PCI_REG_PCI_ERR) & 3; -+ if (pci_err) { -+ if (!is_fixup) -+ printk(KERN_ALERT "PCI error %d at PCI addr 0x%x\n", -+ pci_err, -+ __raw_readl(base + PCI_REG_PCI_ERR_ADDR)); -+ -+ __raw_writel(pci_err, base + PCI_REG_PCI_ERR); -+ } -+ -+ ahb_err = __raw_readl(base + PCI_REG_AHB_ERR) & 1; -+ if (ahb_err) { -+ if (!is_fixup) -+ printk(KERN_ALERT "AHB error at AHB address 0x%x\n", -+ __raw_readl(base + PCI_REG_AHB_ERR_ADDR)); -+ -+ __raw_writel(ahb_err, base + PCI_REG_AHB_ERR); -+ } -+ -+ return ((ahb_err | pci_err) ? 1 : 0); -+} -+ -+static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus, -+ unsigned int devfn, int where, int size, u32 cmd) -+{ -+ void __iomem *base = ar71xx_pcicfg_base; -+ u32 addr; -+ -+ addr = ar71xx_pci_bus_addr(bus, devfn, where); -+ -+ DBG("PCI: set cfgaddr: %02x:%02x.%01x/%02x:%01d, addr=%08x\n", -+ bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), -+ where, size, addr); -+ -+ __raw_writel(addr, base + PCI_REG_CFG_AD); -+ __raw_writel(cmd | ar71xx_pci_get_ble(where, size, 0), -+ base + PCI_REG_CFG_CBE); -+ -+ return ar71xx_pci_be_handler(1); -+} -+ -+static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, -+ int where, int size, u32 *value) -+{ -+ void __iomem *base = ar71xx_pcicfg_base; -+ static u32 mask[8] = {0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0}; -+ unsigned long flags; -+ u32 data; -+ int ret; -+ -+ ret = PCIBIOS_SUCCESSFUL; -+ -+ DBG("PCI: read config: %02x:%02x.%01x/%02x:%01d\n", bus->number, -+ PCI_SLOT(devfn), PCI_FUNC(devfn), where, size); -+ -+ spin_lock_irqsave(&ar71xx_pci_lock, flags); -+ -+ if (bus->number == 0 && devfn == 0) { -+ u32 t; -+ -+ t = PCI_CRP_CMD_READ | (where & ~3); -+ -+ __raw_writel(t, base + PCI_REG_CRP_AD_CBE); -+ data = __raw_readl(base + PCI_REG_CRP_RDDATA); -+ -+ DBG("PCI: rd local cfg, ad_cbe:%08x, data:%08x\n", t, data); -+ -+ } else { -+ int err; -+ -+ err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size, -+ PCI_CFG_CMD_READ); -+ -+ if (err == 0) { -+ data = __raw_readl(base + PCI_REG_CFG_RDDATA); -+ } else { -+ ret = PCIBIOS_DEVICE_NOT_FOUND; -+ data = ~0; -+ } -+ } -+ -+ spin_unlock_irqrestore(&ar71xx_pci_lock, flags); -+ -+ DBG("PCI: read config: data=%08x raw=%08x\n", -+ (data >> (8 * (where & 3))) & mask[size & 7], data); -+ -+ *value = (data >> (8 * (where & 3))) & mask[size & 7]; -+ -+ return ret; -+} -+ -+static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn, -+ int where, int size, u32 value) -+{ -+ void __iomem *base = ar71xx_pcicfg_base; -+ unsigned long flags; -+ int ret; -+ -+ DBG("PCI: write config: %02x:%02x.%01x/%02x:%01d value=%08x\n", -+ bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), -+ where, size, value); -+ -+ value = value << (8 * (where & 3)); -+ ret = PCIBIOS_SUCCESSFUL; -+ -+ spin_lock_irqsave(&ar71xx_pci_lock, flags); -+ if (bus->number == 0 && devfn == 0) { -+ u32 t; -+ -+ t = PCI_CRP_CMD_WRITE | (where & ~3); -+ t |= ar71xx_pci_get_ble(where, size, 1); -+ -+ DBG("PCI: wr local cfg, ad_cbe:%08x, value:%08x\n", t, value); -+ -+ __raw_writel(t, base + PCI_REG_CRP_AD_CBE); -+ __raw_writel(value, base + PCI_REG_CRP_WRDATA); -+ } else { -+ int err; -+ -+ err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size, -+ PCI_CFG_CMD_WRITE); -+ -+ if (err == 0) -+ __raw_writel(value, base + PCI_REG_CFG_WRDATA); -+ else -+ ret = PCIBIOS_DEVICE_NOT_FOUND; -+ } -+ spin_unlock_irqrestore(&ar71xx_pci_lock, flags); -+ -+ return ret; -+} -+ -+static void ar71xx_pci_fixup(struct pci_dev *dev) -+{ -+ u32 t; -+ -+ if (!ar71xx_pci_fixup_enable) -+ return; -+ -+ if (dev->bus->number != 0 || dev->devfn != 0) -+ return; -+ -+ DBG("PCI: fixup host controller %s (%04x:%04x)\n", pci_name(dev), -+ dev->vendor, dev->device); -+ -+ /* setup COMMAND register */ -+ t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE -+ | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK; -+ -+ pci_write_config_word(dev, PCI_COMMAND, t); -+} -+DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ar71xx_pci_fixup); -+ -+int __init ar71xx_pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, -+ uint8_t pin) -+{ -+ int irq = -1; -+ int i; -+ -+ slot -= PCI_IDSEL_ADL_START - PCI_IDSEL_BASE; -+ -+ for (i = 0; i < ar71xx_pci_nr_irqs; i++) { -+ struct ar71xx_pci_irq *entry; -+ -+ entry = &ar71xx_pci_irq_map[i]; -+ if (entry->slot == slot && entry->pin == pin) { -+ irq = entry->irq; -+ break; -+ } -+ } -+ -+ if (irq < 0) { -+ printk(KERN_ALERT "PCI: no irq found for pin%u@%s\n", -+ pin, pci_name((struct pci_dev *)dev)); -+ } else { -+ printk(KERN_INFO "PCI: mapping irq %d to pin%u@%s\n", -+ irq, pin, pci_name((struct pci_dev *)dev)); -+ } -+ -+ return irq; -+} -+ -+static struct pci_ops ar71xx_pci_ops = { -+ .read = ar71xx_pci_read_config, -+ .write = ar71xx_pci_write_config, -+}; -+ -+static struct resource ar71xx_pci_io_resource = { -+ .name = "PCI IO space", -+ .start = 0, -+ .end = 0, -+ .flags = IORESOURCE_IO, -+}; -+ -+static struct resource ar71xx_pci_mem_resource = { -+ .name = "PCI memory space", -+ .start = AR71XX_PCI_MEM_BASE, -+ .end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1, -+ .flags = IORESOURCE_MEM -+}; -+ -+static struct pci_controller ar71xx_pci_controller = { -+ .pci_ops = &ar71xx_pci_ops, -+ .mem_resource = &ar71xx_pci_mem_resource, -+ .io_resource = &ar71xx_pci_io_resource, -+}; -+ -+static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc) -+{ -+ void __iomem *base = ar71xx_reset_base; -+ u32 pending; -+ -+ pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) & -+ __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); -+ -+ if (pending & PCI_INT_DEV0) -+ generic_handle_irq(AR71XX_PCI_IRQ_DEV0); -+ -+ else if (pending & PCI_INT_DEV1) -+ generic_handle_irq(AR71XX_PCI_IRQ_DEV1); -+ -+ else if (pending & PCI_INT_DEV2) -+ generic_handle_irq(AR71XX_PCI_IRQ_DEV2); -+ -+ else if (pending & PCI_INT_CORE) -+ generic_handle_irq(AR71XX_PCI_IRQ_CORE); -+ -+ else -+ spurious_interrupt(); -+} -+ -+static void ar71xx_pci_irq_unmask(unsigned int irq) -+{ -+ void __iomem *base = ar71xx_reset_base; -+ u32 t; -+ -+ irq -= AR71XX_PCI_IRQ_BASE; -+ -+ t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); -+ __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); -+ -+ /* flush write */ -+ (void) __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); -+} -+ -+static void ar71xx_pci_irq_mask(unsigned int irq) -+{ -+ void __iomem *base = ar71xx_reset_base; -+ u32 t; -+ -+ irq -= AR71XX_PCI_IRQ_BASE; -+ -+ t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); -+ __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); -+ -+ /* flush write */ -+ (void) __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); -+} -+ -+static struct irq_chip ar71xx_pci_irq_chip = { -+ .name = "AR71XX PCI ", -+ .mask = ar71xx_pci_irq_mask, -+ .unmask = ar71xx_pci_irq_unmask, -+ .mask_ack = ar71xx_pci_irq_mask, -+}; -+ -+static void __init ar71xx_pci_irq_init(void) -+{ -+ void __iomem *base = ar71xx_reset_base; -+ int i; -+ -+ __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE); -+ __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS); -+ -+ for (i = AR71XX_PCI_IRQ_BASE; -+ i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) { -+ irq_desc[i].status = IRQ_DISABLED; -+ set_irq_chip_and_handler(i, &ar71xx_pci_irq_chip, -+ handle_level_irq); -+ } -+ -+ set_irq_chained_handler(AR71XX_CPU_IRQ_IP2, ar71xx_pci_irq_handler); -+} -+ -+int __init ar71xx_pcibios_init(void) -+{ -+ void __iomem *ddr_base = ar71xx_ddr_base; -+ -+ ar71xx_device_stop(RESET_MODULE_PCI_BUS | RESET_MODULE_PCI_CORE); -+ ar71xx_pci_delay(); -+ -+ ar71xx_device_start(RESET_MODULE_PCI_BUS | RESET_MODULE_PCI_CORE); -+ ar71xx_pci_delay(); -+ -+ ar71xx_pcicfg_base = ioremap_nocache(AR71XX_PCI_CFG_BASE, -+ AR71XX_PCI_CFG_SIZE); -+ if (ar71xx_pcicfg_base == NULL) -+ return -ENOMEM; -+ -+ __raw_writel(PCI_WIN0_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN0); -+ __raw_writel(PCI_WIN1_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN1); -+ __raw_writel(PCI_WIN2_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN2); -+ __raw_writel(PCI_WIN3_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN3); -+ __raw_writel(PCI_WIN4_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN4); -+ __raw_writel(PCI_WIN5_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN5); -+ __raw_writel(PCI_WIN6_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN6); -+ __raw_writel(PCI_WIN7_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN7); -+ -+ ar71xx_pci_delay(); -+ -+ /* clear bus errors */ -+ (void)ar71xx_pci_be_handler(1); -+ -+ ar71xx_pci_fixup_enable = 1; -+ ar71xx_pci_irq_init(); -+ register_pci_controller(&ar71xx_pci_controller); -+ -+ return 0; -+} -diff -Nur linux-2.6.36.orig/arch/mips/pci/pci-ar724x.c linux-2.6.36/arch/mips/pci/pci-ar724x.c ---- linux-2.6.36.orig/arch/mips/pci/pci-ar724x.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/pci/pci-ar724x.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,395 @@ -+/* -+ * Atheros AR724x PCI host controller driver -+ * -+ * Copyright (C) 2009-2010 Gabor Juhos -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#undef DEBUG -+#ifdef DEBUG -+#define DBG(fmt, args...) printk(KERN_INFO fmt, ## args) -+#else -+#define DBG(fmt, args...) -+#endif -+ -+static void __iomem *ar724x_pci_localcfg_base; -+static void __iomem *ar724x_pci_devcfg_base; -+static void __iomem *ar724x_pci_ctrl_base; -+static int ar724x_pci_fixup_enable; -+ -+static DEFINE_SPINLOCK(ar724x_pci_lock); -+ -+static void ar724x_pci_read(void __iomem *base, int where, int size, u32 *value) -+{ -+ unsigned long flags; -+ u32 data; -+ -+ spin_lock_irqsave(&ar724x_pci_lock, flags); -+ data = __raw_readl(base + (where & ~3)); -+ -+ switch (size) { -+ case 1: -+ if (where & 1) -+ data >>= 8; -+ if (where & 2) -+ data >>= 16; -+ data &= 0xFF; -+ break; -+ case 2: -+ if (where & 2) -+ data >>= 16; -+ data &= 0xFFFF; -+ break; -+ } -+ -+ *value = data; -+ spin_unlock_irqrestore(&ar724x_pci_lock, flags); -+} -+ -+static void ar724x_pci_write(void __iomem *base, int where, int size, u32 value) -+{ -+ unsigned long flags; -+ u32 data; -+ int s; -+ -+ spin_lock_irqsave(&ar724x_pci_lock, flags); -+ data = __raw_readl(base + (where & ~3)); -+ -+ switch (size) { -+ case 1: -+ s = ((where & 3) << 3); -+ data &= ~(0xFF << s); -+ data |= ((value & 0xFF) << s); -+ break; -+ case 2: -+ s = ((where & 2) << 3); -+ data &= ~(0xFFFF << s); -+ data |= ((value & 0xFFFF) << s); -+ break; -+ case 4: -+ data = value; -+ break; -+ } -+ -+ __raw_writel(data, base + (where & ~3)); -+ /* flush write */ -+ (void)__raw_readl(base + (where & ~3)); -+ spin_unlock_irqrestore(&ar724x_pci_lock, flags); -+} -+ -+static int ar724x_pci_read_config(struct pci_bus *bus, unsigned int devfn, -+ int where, int size, u32 *value) -+{ -+ -+ if (bus->number != 0 || devfn != 0) -+ return PCIBIOS_DEVICE_NOT_FOUND; -+ -+ ar724x_pci_read(ar724x_pci_devcfg_base, where, size, value); -+ -+ DBG("PCI: read config: %02x:%02x.%01x/%02x:%01d, value=%08x\n", -+ bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), -+ where, size, *value); -+ -+ /* -+ * WAR for BAR issue - We are unable to access the PCI device space -+ * if we set the BAR with proper base address -+ */ -+ if ((where == 0x10) && (size == 4)) { -+ if (ar71xx_soc == AR71XX_SOC_AR7240) -+ ar724x_pci_write(ar724x_pci_devcfg_base, where, size, 0xffff); -+ else -+ ar724x_pci_write(ar724x_pci_devcfg_base, where, size, 0x1000ffff); -+ } -+ -+ return PCIBIOS_SUCCESSFUL; -+} -+ -+static int ar724x_pci_write_config(struct pci_bus *bus, unsigned int devfn, -+ int where, int size, u32 value) -+{ -+ if (bus->number != 0 || devfn != 0) -+ return PCIBIOS_DEVICE_NOT_FOUND; -+ -+ DBG("PCI: write config: %02x:%02x.%01x/%02x:%01d, value=%08x\n", -+ bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), -+ where, size, value); -+ -+ ar724x_pci_write(ar724x_pci_devcfg_base, where, size, value); -+ -+ return PCIBIOS_SUCCESSFUL; -+} -+ -+static void ar724x_pci_fixup(struct pci_dev *dev) -+{ -+ u16 cmd; -+ -+ if (!ar724x_pci_fixup_enable) -+ return; -+ -+ if (dev->bus->number != 0 || dev->devfn != 0) -+ return; -+ -+ /* setup COMMAND register */ -+ pci_read_config_word(dev, PCI_COMMAND, &cmd); -+ cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | -+ PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | -+ PCI_COMMAND_FAST_BACK; -+ -+ pci_write_config_word(dev, PCI_COMMAND, cmd); -+} -+DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ar724x_pci_fixup); -+ -+int __init ar724x_pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, -+ uint8_t pin) -+{ -+ int irq = -1; -+ int i; -+ -+ for (i = 0; i < ar71xx_pci_nr_irqs; i++) { -+ struct ar71xx_pci_irq *entry; -+ entry = &ar71xx_pci_irq_map[i]; -+ -+ if (entry->slot == slot && entry->pin == pin) { -+ irq = entry->irq; -+ break; -+ } -+ } -+ -+ if (irq < 0) -+ printk(KERN_ALERT "PCI: no irq found for pin%u@%s\n", -+ pin, pci_name((struct pci_dev *)dev)); -+ else -+ printk(KERN_INFO "PCI: mapping irq %d to pin%u@%s\n", -+ irq, pin, pci_name((struct pci_dev *)dev)); -+ -+ return irq; -+} -+ -+static struct pci_ops ar724x_pci_ops = { -+ .read = ar724x_pci_read_config, -+ .write = ar724x_pci_write_config, -+}; -+ -+static struct resource ar724x_pci_io_resource = { -+ .name = "PCI IO space", -+ .start = 0, -+ .end = 0, -+ .flags = IORESOURCE_IO, -+}; -+ -+static struct resource ar724x_pci_mem_resource = { -+ .name = "PCI memory space", -+ .start = AR71XX_PCI_MEM_BASE, -+ .end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1, -+ .flags = IORESOURCE_MEM -+}; -+ -+static struct pci_controller ar724x_pci_controller = { -+ .pci_ops = &ar724x_pci_ops, -+ .mem_resource = &ar724x_pci_mem_resource, -+ .io_resource = &ar724x_pci_io_resource, -+}; -+ -+static void __init ar724x_pci_reset(void) -+{ -+ ar71xx_device_stop(AR724X_RESET_PCIE); -+ ar71xx_device_stop(AR724X_RESET_PCIE_PHY); -+ ar71xx_device_stop(AR724X_RESET_PCIE_PHY_SERIAL); -+ udelay(100); -+ -+ ar71xx_device_start(AR724X_RESET_PCIE_PHY_SERIAL); -+ udelay(100); -+ ar71xx_device_start(AR724X_RESET_PCIE_PHY); -+ ar71xx_device_start(AR724X_RESET_PCIE); -+} -+ -+static int __init ar724x_pci_setup(void) -+{ -+ void __iomem *base = ar724x_pci_ctrl_base; -+ u32 t; -+ -+ /* setup COMMAND register */ -+ t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE | -+ PCI_COMMAND_PARITY|PCI_COMMAND_SERR|PCI_COMMAND_FAST_BACK; -+ -+ ar724x_pci_write(ar724x_pci_localcfg_base, PCI_COMMAND, 4, t); -+ ar724x_pci_write(ar724x_pci_localcfg_base, 0x20, 4, 0x1ff01000); -+ ar724x_pci_write(ar724x_pci_localcfg_base, 0x24, 4, 0x1ff01000); -+ -+ t = __raw_readl(base + AR724X_PCI_REG_RESET); -+ if (t != 0x7) { -+ udelay(100000); -+ __raw_writel(0, base + AR724X_PCI_REG_RESET); -+ udelay(100); -+ __raw_writel(4, base + AR724X_PCI_REG_RESET); -+ udelay(100000); -+ } -+ -+ if (ar71xx_soc == AR71XX_SOC_AR7240) -+ t = AR724X_PCI_APP_LTSSM_ENABLE; -+ else -+ t = 0x1ffc1; -+ __raw_writel(t, base + AR724X_PCI_REG_APP); -+ /* flush write */ -+ (void) __raw_readl(base + AR724X_PCI_REG_APP); -+ udelay(1000); -+ -+ t = __raw_readl(base + AR724X_PCI_REG_RESET); -+ if ((t & AR724X_PCI_RESET_LINK_UP) == 0x0) { -+ printk(KERN_WARNING "PCI: no PCIe module found\n"); -+ return -ENODEV; -+ } -+ -+ if (ar71xx_soc == AR71XX_SOC_AR7241 || ar71xx_soc == AR71XX_SOC_AR7242) { -+ t = __raw_readl(base + AR724X_PCI_REG_APP); -+ t |= BIT(16); -+ __raw_writel(t, base + AR724X_PCI_REG_APP); -+ } -+ -+ return 0; -+} -+ -+static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc) -+{ -+ void __iomem *base = ar724x_pci_ctrl_base; -+ u32 pending; -+ -+ pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) & -+ __raw_readl(base + AR724X_PCI_REG_INT_MASK); -+ -+ if (pending & AR724X_PCI_INT_DEV0) -+ generic_handle_irq(AR71XX_PCI_IRQ_DEV0); -+ -+ else -+ spurious_interrupt(); -+} -+ -+static void ar724x_pci_irq_unmask(unsigned int irq) -+{ -+ void __iomem *base = ar724x_pci_ctrl_base; -+ u32 t; -+ -+ switch (irq) { -+ case AR71XX_PCI_IRQ_DEV0: -+ irq -= AR71XX_PCI_IRQ_BASE; -+ -+ t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); -+ __raw_writel(t | AR724X_PCI_INT_DEV0, -+ base + AR724X_PCI_REG_INT_MASK); -+ /* flush write */ -+ (void) __raw_readl(base + AR724X_PCI_REG_INT_MASK); -+ } -+} -+ -+static void ar724x_pci_irq_mask(unsigned int irq) -+{ -+ void __iomem *base = ar724x_pci_ctrl_base; -+ u32 t; -+ -+ switch (irq) { -+ case AR71XX_PCI_IRQ_DEV0: -+ irq -= AR71XX_PCI_IRQ_BASE; -+ -+ t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); -+ __raw_writel(t & ~AR724X_PCI_INT_DEV0, -+ base + AR724X_PCI_REG_INT_MASK); -+ -+ /* flush write */ -+ (void) __raw_readl(base + AR724X_PCI_REG_INT_MASK); -+ -+ t = __raw_readl(base + AR724X_PCI_REG_INT_STATUS); -+ __raw_writel(t | AR724X_PCI_INT_DEV0, -+ base + AR724X_PCI_REG_INT_STATUS); -+ -+ /* flush write */ -+ (void) __raw_readl(base + AR724X_PCI_REG_INT_STATUS); -+ } -+} -+ -+static struct irq_chip ar724x_pci_irq_chip = { -+ .name = "AR724X PCI ", -+ .mask = ar724x_pci_irq_mask, -+ .unmask = ar724x_pci_irq_unmask, -+ .mask_ack = ar724x_pci_irq_mask, -+}; -+ -+static void __init ar724x_pci_irq_init(void) -+{ -+ void __iomem *base = ar724x_pci_ctrl_base; -+ u32 t; -+ int i; -+ -+ t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE); -+ if (t & (AR724X_RESET_PCIE | AR724X_RESET_PCIE_PHY | -+ AR724X_RESET_PCIE_PHY_SERIAL)) { -+ return; -+ } -+ -+ __raw_writel(0, base + AR724X_PCI_REG_INT_MASK); -+ __raw_writel(0, base + AR724X_PCI_REG_INT_STATUS); -+ -+ for (i = AR71XX_PCI_IRQ_BASE; -+ i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) { -+ irq_desc[i].status = IRQ_DISABLED; -+ set_irq_chip_and_handler(i, &ar724x_pci_irq_chip, -+ handle_level_irq); -+ } -+ -+ set_irq_chained_handler(AR71XX_CPU_IRQ_IP2, ar724x_pci_irq_handler); -+} -+ -+int __init ar724x_pcibios_init(void) -+{ -+ int ret = -ENOMEM; -+ -+ ar724x_pci_localcfg_base = ioremap_nocache(AR724X_PCI_CRP_BASE, -+ AR724X_PCI_CRP_SIZE); -+ if (ar724x_pci_localcfg_base == NULL) -+ goto err; -+ -+ ar724x_pci_devcfg_base = ioremap_nocache(AR724X_PCI_CFG_BASE, -+ AR724X_PCI_CFG_SIZE); -+ if (ar724x_pci_devcfg_base == NULL) -+ goto err_unmap_localcfg; -+ -+ ar724x_pci_ctrl_base = ioremap_nocache(AR724X_PCI_CTRL_BASE, -+ AR724X_PCI_CTRL_SIZE); -+ if (ar724x_pci_ctrl_base == NULL) -+ goto err_unmap_devcfg; -+ -+ ar724x_pci_reset(); -+ ret = ar724x_pci_setup(); -+ if (ret) -+ goto err_unmap_ctrl; -+ -+ ar724x_pci_fixup_enable = 1; -+ ar724x_pci_irq_init(); -+ register_pci_controller(&ar724x_pci_controller); -+ -+ return 0; -+ -+ err_unmap_ctrl: -+ iounmap(ar724x_pci_ctrl_base); -+ err_unmap_devcfg: -+ iounmap(ar724x_pci_devcfg_base); -+ err_unmap_localcfg: -+ iounmap(ar724x_pci_localcfg_base); -+ err: -+ return ret; -+} -diff -Nur linux-2.6.36.orig/drivers/char/Kconfig linux-2.6.36/drivers/char/Kconfig ---- linux-2.6.36.orig/drivers/char/Kconfig 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/drivers/char/Kconfig 2010-12-17 18:34:51.000000000 +0100 -@@ -1032,6 +1032,14 @@ - - If compiled as a module, it will be called cs5535_gpio. - -+config GPIO_DEVICE -+ tristate "GPIO device support" -+ depends on GENERIC_GPIO -+ help -+ Say Y to enable Linux GPIO device support. This allows control of -+ GPIO pins using a character device -+ -+ - config RAW_DRIVER - tristate "RAW driver (/dev/raw/rawN)" - depends on BLOCK -diff -Nur linux-2.6.36.orig/drivers/char/Makefile linux-2.6.36/drivers/char/Makefile ---- linux-2.6.36.orig/drivers/char/Makefile 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/drivers/char/Makefile 2010-12-17 18:34:51.000000000 +0100 -@@ -98,6 +98,7 @@ - obj-$(CONFIG_PC8736x_GPIO) += pc8736x_gpio.o - obj-$(CONFIG_NSC_GPIO) += nsc_gpio.o - obj-$(CONFIG_CS5535_GPIO) += cs5535_gpio.o -+obj-$(CONFIG_GPIO_DEVICE) += gpio_dev.o - obj-$(CONFIG_GPIO_TB0219) += tb0219.o - obj-$(CONFIG_TELCLOCK) += tlclk.o - -diff -Nur linux-2.6.36.orig/drivers/gpio/nxp_74hc153.c linux-2.6.36/drivers/gpio/nxp_74hc153.c ---- linux-2.6.36.orig/drivers/gpio/nxp_74hc153.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/drivers/gpio/nxp_74hc153.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,246 @@ -+/* -+ * NXP 74HC153 - Dual 4-input multiplexer GPIO driver -+ * -+ * Copyright (C) 2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#define NXP_74HC153_NUM_GPIOS 8 -+#define NXP_74HC153_S0_MASK 0x1 -+#define NXP_74HC153_S1_MASK 0x2 -+#define NXP_74HC153_BANK_MASK 0x4 -+ -+struct nxp_74hc153_chip { -+ struct device *parent; -+ struct gpio_chip gpio_chip; -+ struct mutex lock; -+}; -+ -+static struct nxp_74hc153_chip *gpio_to_nxp(struct gpio_chip *gc) -+{ -+ return container_of(gc, struct nxp_74hc153_chip, gpio_chip); -+} -+ -+static int nxp_74hc153_direction_input(struct gpio_chip *gc, unsigned offset) -+{ -+ return 0; -+} -+ -+static int nxp_74hc153_direction_output(struct gpio_chip *gc, -+ unsigned offset, int val) -+{ -+ return -EINVAL; -+} -+ -+static int nxp_74hc153_get_value(struct gpio_chip *gc, unsigned offset) -+{ -+ struct nxp_74hc153_chip *nxp; -+ struct nxp_74hc153_platform_data *pdata; -+ unsigned s0; -+ unsigned s1; -+ unsigned pin; -+ int ret; -+ -+ nxp = gpio_to_nxp(gc); -+ pdata = nxp->parent->platform_data; -+ -+ s0 = !!(offset & NXP_74HC153_S0_MASK); -+ s1 = !!(offset & NXP_74HC153_S1_MASK); -+ pin = (offset & NXP_74HC153_BANK_MASK) ? pdata->gpio_pin_2y -+ : pdata->gpio_pin_1y; -+ -+ mutex_lock(&nxp->lock); -+ gpio_set_value(pdata->gpio_pin_s0, s0); -+ gpio_set_value(pdata->gpio_pin_s1, s1); -+ ret = gpio_get_value(pin); -+ mutex_unlock(&nxp->lock); -+ -+ return ret; -+} -+ -+static void nxp_74hc153_set_value(struct gpio_chip *gc, -+ unsigned offset, int val) -+{ -+ /* not supported */ -+} -+ -+static int __devinit nxp_74hc153_probe(struct platform_device *pdev) -+{ -+ struct nxp_74hc153_platform_data *pdata; -+ struct nxp_74hc153_chip *nxp; -+ struct gpio_chip *gc; -+ int err; -+ -+ pdata = pdev->dev.platform_data; -+ if (pdata == NULL) { -+ dev_dbg(&pdev->dev, "no platform data specified\n"); -+ return -EINVAL; -+ } -+ -+ nxp = kzalloc(sizeof(struct nxp_74hc153_chip), GFP_KERNEL); -+ if (nxp == NULL) { -+ dev_err(&pdev->dev, "no memory for private data\n"); -+ return -ENOMEM; -+ } -+ -+ err = gpio_request(pdata->gpio_pin_s0, dev_name(&pdev->dev)); -+ if (err) { -+ dev_err(&pdev->dev, "unable to claim gpio %u, err=%d\n", -+ pdata->gpio_pin_s0, err); -+ goto err_free_nxp; -+ } -+ -+ err = gpio_request(pdata->gpio_pin_s1, dev_name(&pdev->dev)); -+ if (err) { -+ dev_err(&pdev->dev, "unable to claim gpio %u, err=%d\n", -+ pdata->gpio_pin_s1, err); -+ goto err_free_s0; -+ } -+ -+ err = gpio_request(pdata->gpio_pin_1y, dev_name(&pdev->dev)); -+ if (err) { -+ dev_err(&pdev->dev, "unable to claim gpio %u, err=%d\n", -+ pdata->gpio_pin_1y, err); -+ goto err_free_s1; -+ } -+ -+ err = gpio_request(pdata->gpio_pin_2y, dev_name(&pdev->dev)); -+ if (err) { -+ dev_err(&pdev->dev, "unable to claim gpio %u, err=%d\n", -+ pdata->gpio_pin_2y, err); -+ goto err_free_1y; -+ } -+ -+ err = gpio_direction_output(pdata->gpio_pin_s0, 0); -+ if (err) { -+ dev_err(&pdev->dev, -+ "unable to set direction of gpio %u, err=%d\n", -+ pdata->gpio_pin_s0, err); -+ goto err_free_2y; -+ } -+ -+ err = gpio_direction_output(pdata->gpio_pin_s1, 0); -+ if (err) { -+ dev_err(&pdev->dev, -+ "unable to set direction of gpio %u, err=%d\n", -+ pdata->gpio_pin_s1, err); -+ goto err_free_2y; -+ } -+ -+ err = gpio_direction_input(pdata->gpio_pin_1y); -+ if (err) { -+ dev_err(&pdev->dev, -+ "unable to set direction of gpio %u, err=%d\n", -+ pdata->gpio_pin_1y, err); -+ goto err_free_2y; -+ } -+ -+ err = gpio_direction_input(pdata->gpio_pin_2y); -+ if (err) { -+ dev_err(&pdev->dev, -+ "unable to set direction of gpio %u, err=%d\n", -+ pdata->gpio_pin_2y, err); -+ goto err_free_2y; -+ } -+ -+ nxp->parent = &pdev->dev; -+ mutex_init(&nxp->lock); -+ -+ gc = &nxp->gpio_chip; -+ -+ gc->direction_input = nxp_74hc153_direction_input; -+ gc->direction_output = nxp_74hc153_direction_output; -+ gc->get = nxp_74hc153_get_value; -+ gc->set = nxp_74hc153_set_value; -+ gc->can_sleep = 1; -+ -+ gc->base = pdata->gpio_base; -+ gc->ngpio = NXP_74HC153_NUM_GPIOS; -+ gc->label = dev_name(nxp->parent); -+ gc->dev = nxp->parent; -+ gc->owner = THIS_MODULE; -+ -+ err = gpiochip_add(&nxp->gpio_chip); -+ if (err) { -+ dev_err(&pdev->dev, "unable to add gpio chip, err=%d\n", err); -+ goto err_free_2y; -+ } -+ -+ platform_set_drvdata(pdev, nxp); -+ return 0; -+ -+ err_free_2y: -+ gpio_free(pdata->gpio_pin_2y); -+ err_free_1y: -+ gpio_free(pdata->gpio_pin_1y); -+ err_free_s1: -+ gpio_free(pdata->gpio_pin_s1); -+ err_free_s0: -+ gpio_free(pdata->gpio_pin_s0); -+ err_free_nxp: -+ kfree(nxp); -+ return err; -+} -+ -+static int nxp_74hc153_remove(struct platform_device *pdev) -+{ -+ struct nxp_74hc153_chip *nxp = platform_get_drvdata(pdev); -+ struct nxp_74hc153_platform_data *pdata = pdev->dev.platform_data; -+ -+ if (nxp) { -+ int err; -+ -+ err = gpiochip_remove(&nxp->gpio_chip); -+ if (err) { -+ dev_err(&pdev->dev, -+ "unable to remove gpio chip, err=%d\n", -+ err); -+ return err; -+ } -+ -+ gpio_free(pdata->gpio_pin_2y); -+ gpio_free(pdata->gpio_pin_1y); -+ gpio_free(pdata->gpio_pin_s1); -+ gpio_free(pdata->gpio_pin_s0); -+ -+ kfree(nxp); -+ platform_set_drvdata(pdev, NULL); -+ } -+ -+ return 0; -+} -+ -+static struct platform_driver nxp_74hc153_driver = { -+ .probe = nxp_74hc153_probe, -+ .remove = __devexit_p(nxp_74hc153_remove), -+ .driver = { -+ .name = NXP_74HC153_DRIVER_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init nxp_74hc153_init(void) -+{ -+ return platform_driver_register(&nxp_74hc153_driver); -+} -+subsys_initcall(nxp_74hc153_init); -+ -+static void __exit nxp_74hc153_exit(void) -+{ -+ platform_driver_unregister(&nxp_74hc153_driver); -+} -+module_exit(nxp_74hc153_exit); -+ -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_DESCRIPTION("GPIO expander driver for NXP 74HC153"); -+MODULE_LICENSE("GPL v2"); -+MODULE_ALIAS("platform:" NXP_74HC153_DRIVER_NAME); -diff -Nur linux-2.6.36.orig/drivers/input/misc/Kconfig linux-2.6.36/drivers/input/misc/Kconfig ---- linux-2.6.36.orig/drivers/input/misc/Kconfig 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/drivers/input/misc/Kconfig 2010-12-17 18:34:51.000000000 +0100 -@@ -438,4 +438,20 @@ - To compile this driver as a module, choose M here: the - module will be called adxl34x-spi. - -+config INPUT_GPIO_BUTTONS -+ tristate "Polled GPIO buttons interface" -+ depends on GENERIC_GPIO -+ select INPUT_POLLDEV -+ help -+ This driver implements support for buttons connected -+ to GPIO pins of various CPUs (and some other chips). -+ -+ Say Y here if your device has buttons connected -+ directly to such GPIO pins. Your board-specific -+ setup logic must also provide a platform device, -+ with configuration data saying which GPIOs are used. -+ -+ To compile this driver as a module, choose M here: the -+ module will be called gpio-buttons. -+ - endif -diff -Nur linux-2.6.36.orig/drivers/input/misc/Makefile linux-2.6.36/drivers/input/misc/Makefile ---- linux-2.6.36.orig/drivers/input/misc/Makefile 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/drivers/input/misc/Makefile 2010-12-17 18:34:51.000000000 +0100 -@@ -41,4 +41,5 @@ - obj-$(CONFIG_INPUT_WISTRON_BTNS) += wistron_btns.o - obj-$(CONFIG_INPUT_WM831X_ON) += wm831x-on.o - obj-$(CONFIG_INPUT_YEALINK) += yealink.o -+obj-$(CONFIG_INPUT_GPIO_BUTTONS) += gpio_buttons.o - -diff -Nur linux-2.6.36.orig/drivers/input/misc/gpio_buttons.c linux-2.6.36/drivers/input/misc/gpio_buttons.c ---- linux-2.6.36.orig/drivers/input/misc/gpio_buttons.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/drivers/input/misc/gpio_buttons.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,216 @@ -+/* -+ * Driver for buttons on GPIO lines not capable of generating interrupts -+ * -+ * Copyright (C) 2007-2010 Gabor Juhos -+ * Copyright (C) 2010 Nuno Goncalves -+ * -+ * This file was based on: /drivers/input/misc/cobalt_btns.c -+ * Copyright (C) 2007 Yoichi Yuasa -+ * -+ * also was based on: /drivers/input/keyboard/gpio_keys.c -+ * Copyright 2005 Phil Blundell -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include -+ -+#define DRV_NAME "gpio-buttons" -+#define DRV_VERSION "0.1.2" -+#define PFX DRV_NAME ": " -+ -+struct gpio_button_data { -+ int last_state; -+ int count; -+}; -+ -+struct gpio_buttons_dev { -+ struct input_polled_dev *poll_dev; -+ struct gpio_buttons_platform_data *pdata; -+ struct gpio_button_data *data; -+}; -+ -+static void gpio_buttons_poll(struct input_polled_dev *dev) -+{ -+ struct gpio_buttons_dev *bdev = dev->private; -+ struct gpio_buttons_platform_data *pdata = bdev->pdata; -+ struct input_dev *input = dev->input; -+ int i; -+ -+ for (i = 0; i < bdev->pdata->nbuttons; i++) { -+ struct gpio_button *button = &pdata->buttons[i]; -+ unsigned int type = button->type ?: EV_KEY; -+ int state; -+ -+ if (bdev->data[i].count < button->threshold) { -+ bdev->data[i].count++; -+ continue; -+ } -+ -+ state = gpio_get_value(button->gpio) ? 1 : 0; -+ if (state != bdev->data[i].last_state) { -+ input_event(input, type, button->code, -+ !!(state ^ button->active_low)); -+ input_sync(input); -+ bdev->data[i].count = 0; -+ bdev->data[i].last_state = state; -+ } -+ } -+} -+ -+static int __devinit gpio_buttons_probe(struct platform_device *pdev) -+{ -+ struct gpio_buttons_platform_data *pdata = pdev->dev.platform_data; -+ struct gpio_buttons_dev *bdev; -+ struct input_polled_dev *poll_dev; -+ struct input_dev *input; -+ int error, i; -+ -+ if (!pdata) -+ return -ENXIO; -+ -+ bdev = kzalloc(sizeof(struct gpio_buttons_dev) + -+ sizeof(struct gpio_button_data) * pdata->nbuttons, -+ GFP_KERNEL); -+ if (!bdev) { -+ printk(KERN_ERR DRV_NAME "no memory for device\n"); -+ return -ENOMEM; -+ } -+ -+ bdev->data = (struct gpio_button_data *) &bdev[1]; -+ -+ poll_dev = input_allocate_polled_device(); -+ if (!poll_dev) { -+ printk(KERN_ERR DRV_NAME "no memory for polled device\n"); -+ error = -ENOMEM; -+ goto err_free_bdev; -+ } -+ -+ poll_dev->private = bdev; -+ poll_dev->poll = gpio_buttons_poll; -+ poll_dev->poll_interval = pdata->poll_interval; -+ -+ input = poll_dev->input; -+ -+ input->evbit[0] = BIT(EV_KEY); -+ input->name = pdev->name; -+ input->phys = "gpio-buttons/input0"; -+ input->dev.parent = &pdev->dev; -+ -+ input->id.bustype = BUS_HOST; -+ input->id.vendor = 0x0001; -+ input->id.product = 0x0001; -+ input->id.version = 0x0100; -+ -+ for (i = 0; i < pdata->nbuttons; i++) { -+ struct gpio_button *button = &pdata->buttons[i]; -+ unsigned int gpio = button->gpio; -+ unsigned int type = button->type ?: EV_KEY; -+ -+ error = gpio_request(gpio, button->desc ? -+ button->desc : DRV_NAME); -+ if (error) { -+ printk(KERN_ERR PFX "unable to claim gpio %u, " -+ "error %d\n", gpio, error); -+ goto err_free_gpio; -+ } -+ -+ error = gpio_direction_input(gpio); -+ if (error) { -+ printk(KERN_ERR PFX "unable to set direction on " -+ "gpio %u, error %d\n", gpio, error); -+ goto err_free_gpio; -+ } -+ -+ input_set_capability(input, type, button->code); -+ bdev->data[i].last_state = gpio_get_value(button->gpio) ? 1 : 0; -+ } -+ -+ bdev->poll_dev = poll_dev; -+ bdev->pdata = pdata; -+ platform_set_drvdata(pdev, bdev); -+ -+ error = input_register_polled_device(poll_dev); -+ if (error) { -+ printk(KERN_ERR PFX "unable to register polled device, " -+ "error %d\n", error); -+ goto err_free_gpio; -+ } -+ -+ return 0; -+ -+err_free_gpio: -+ for (i = i - 1; i >= 0; i--) -+ gpio_free(pdata->buttons[i].gpio); -+ -+ input_free_polled_device(poll_dev); -+ -+err_free_bdev: -+ kfree(bdev); -+ -+ platform_set_drvdata(pdev, NULL); -+ return error; -+} -+ -+static int __devexit gpio_buttons_remove(struct platform_device *pdev) -+{ -+ struct gpio_buttons_dev *bdev = platform_get_drvdata(pdev); -+ struct gpio_buttons_platform_data *pdata = bdev->pdata; -+ int i; -+ -+ input_unregister_polled_device(bdev->poll_dev); -+ -+ for (i = 0; i < pdata->nbuttons; i++) -+ gpio_free(pdata->buttons[i].gpio); -+ -+ input_free_polled_device(bdev->poll_dev); -+ -+ kfree(bdev); -+ platform_set_drvdata(pdev, NULL); -+ -+ return 0; -+} -+ -+static struct platform_driver gpio_buttons_driver = { -+ .probe = gpio_buttons_probe, -+ .remove = __devexit_p(gpio_buttons_remove), -+ .driver = { -+ .name = DRV_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init gpio_buttons_init(void) -+{ -+ printk(KERN_INFO DRV_NAME " driver version " DRV_VERSION "\n"); -+ return platform_driver_register(&gpio_buttons_driver); -+} -+ -+static void __exit gpio_buttons_exit(void) -+{ -+ platform_driver_unregister(&gpio_buttons_driver); -+} -+ -+module_init(gpio_buttons_init); -+module_exit(gpio_buttons_exit); -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_VERSION(DRV_VERSION); -+MODULE_DESCRIPTION("Polled buttons driver for CPU GPIOs"); -+ -diff -Nur linux-2.6.36.orig/drivers/leds/leds-rb750.c linux-2.6.36/drivers/leds/leds-rb750.c ---- linux-2.6.36.orig/drivers/leds/leds-rb750.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/drivers/leds/leds-rb750.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,140 @@ -+/* -+ * LED driver for the RouterBOARD 750 -+ * -+ * Copyright (C) 2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ */ -+#include -+#include -+#include -+#include -+ -+#include -+ -+#define DRV_NAME "leds-rb750" -+ -+struct rb750_led_dev { -+ struct led_classdev cdev; -+ u32 mask; -+ int active_low; -+}; -+ -+struct rb750_led_drvdata { -+ struct rb750_led_dev *led_devs; -+ int num_leds; -+}; -+ -+static inline struct rb750_led_dev *to_rbled(struct led_classdev *led_cdev) -+{ -+ return (struct rb750_led_dev *)container_of(led_cdev, -+ struct rb750_led_dev, cdev); -+} -+ -+static void rb750_led_brightness_set(struct led_classdev *led_cdev, -+ enum led_brightness value) -+{ -+ struct rb750_led_dev *rbled = to_rbled(led_cdev); -+ int level; -+ -+ level = (value == LED_OFF) ? 0 : 1; -+ level ^= rbled->active_low; -+ -+ if (level) -+ rb750_latch_change(0, rbled->mask); -+ else -+ rb750_latch_change(rbled->mask, 0); -+} -+ -+static int __devinit rb750_led_probe(struct platform_device *pdev) -+{ -+ struct rb750_led_platform_data *pdata; -+ struct rb750_led_drvdata *drvdata; -+ int ret = 0; -+ int i; -+ -+ pdata = pdev->dev.platform_data; -+ if (!pdata) -+ return -EINVAL; -+ -+ drvdata = kzalloc(sizeof(struct rb750_led_drvdata) + -+ sizeof(struct rb750_led_dev) * pdata->num_leds, -+ GFP_KERNEL); -+ if (!drvdata) -+ return -ENOMEM; -+ -+ drvdata->num_leds = pdata->num_leds; -+ drvdata->led_devs = (struct rb750_led_dev *) &drvdata[1]; -+ -+ for (i = 0; i < drvdata->num_leds; i++) { -+ struct rb750_led_dev *rbled = &drvdata->led_devs[i]; -+ struct rb750_led_data *led_data = &pdata->leds[i]; -+ -+ rbled->cdev.name = led_data->name; -+ rbled->cdev.default_trigger = led_data->default_trigger; -+ rbled->cdev.brightness_set = rb750_led_brightness_set; -+ rbled->cdev.brightness = LED_OFF; -+ -+ rbled->mask = led_data->mask; -+ rbled->active_low = !!led_data->active_low; -+ -+ ret = led_classdev_register(&pdev->dev, &rbled->cdev); -+ if (ret) -+ goto err; -+ } -+ -+ platform_set_drvdata(pdev, drvdata); -+ return 0; -+ -+ err: -+ for (i = i - 1; i >= 0; i--) -+ led_classdev_unregister(&drvdata->led_devs[i].cdev); -+ -+ kfree(drvdata); -+ return ret; -+} -+ -+static int __devexit rb750_led_remove(struct platform_device *pdev) -+{ -+ struct rb750_led_drvdata *drvdata; -+ int i; -+ -+ drvdata = platform_get_drvdata(pdev); -+ for (i = 0; i < drvdata->num_leds; i++) -+ led_classdev_unregister(&drvdata->led_devs[i].cdev); -+ -+ kfree(drvdata); -+ return 0; -+} -+ -+static struct platform_driver rb750_led_driver = { -+ .probe = rb750_led_probe, -+ .remove = __devexit_p(rb750_led_remove), -+ .driver = { -+ .name = DRV_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+MODULE_ALIAS("platform:leds-rb750"); -+ -+static int __init rb750_led_init(void) -+{ -+ return platform_driver_register(&rb750_led_driver); -+} -+ -+static void __exit rb750_led_exit(void) -+{ -+ platform_driver_unregister(&rb750_led_driver); -+} -+ -+module_init(rb750_led_init); -+module_exit(rb750_led_exit); -+ -+MODULE_DESCRIPTION(DRV_NAME); -+MODULE_DESCRIPTION("LED driver for the RouterBOARD 750"); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_LICENSE("GPL v2"); -diff -Nur linux-2.6.36.orig/drivers/leds/leds-wndr3700-usb.c linux-2.6.36/drivers/leds/leds-wndr3700-usb.c ---- linux-2.6.36.orig/drivers/leds/leds-wndr3700-usb.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/drivers/leds/leds-wndr3700-usb.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,75 @@ -+/* -+ * USB LED driver for the NETGEAR WNDR3700 -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+ -+#include -+ -+#define DRIVER_NAME "wndr3700-led-usb" -+ -+static void wndr3700_usb_led_set(struct led_classdev *cdev, -+ enum led_brightness brightness) -+{ -+ if (brightness) -+ ar71xx_device_start(RESET_MODULE_GE1_PHY); -+ else -+ ar71xx_device_stop(RESET_MODULE_GE1_PHY); -+} -+ -+static enum led_brightness wndr3700_usb_led_get(struct led_classdev *cdev) -+{ -+ return ar71xx_device_stopped(RESET_MODULE_GE1_PHY) ? LED_OFF : LED_FULL; -+} -+ -+static struct led_classdev wndr3700_usb_led = { -+ .name = "wndr3700:green:usb", -+ .brightness_set = wndr3700_usb_led_set, -+ .brightness_get = wndr3700_usb_led_get, -+}; -+ -+static int __devinit wndr3700_usb_led_probe(struct platform_device *pdev) -+{ -+ return led_classdev_register(&pdev->dev, &wndr3700_usb_led); -+} -+ -+static int __devexit wndr3700_usb_led_remove(struct platform_device *pdev) -+{ -+ led_classdev_unregister(&wndr3700_usb_led); -+ return 0; -+} -+ -+static struct platform_driver wndr3700_usb_led_driver = { -+ .probe = wndr3700_usb_led_probe, -+ .remove = __devexit_p(wndr3700_usb_led_remove), -+ .driver = { -+ .name = DRIVER_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init wndr3700_usb_led_init(void) -+{ -+ return platform_driver_register(&wndr3700_usb_led_driver); -+} -+ -+static void __exit wndr3700_usb_led_exit(void) -+{ -+ platform_driver_unregister(&wndr3700_usb_led_driver); -+} -+ -+module_init(wndr3700_usb_led_init); -+module_exit(wndr3700_usb_led_exit); -+ -+MODULE_DESCRIPTION("USB LED driver for the NETGEAR WNDR3700"); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_LICENSE("GPL v2"); -+MODULE_ALIAS("platform:" DRIVER_NAME); -diff -Nur linux-2.6.36.orig/drivers/mtd/maps/Kconfig linux-2.6.36/drivers/mtd/maps/Kconfig ---- linux-2.6.36.orig/drivers/mtd/maps/Kconfig 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/drivers/mtd/maps/Kconfig 2010-12-17 18:34:51.000000000 +0100 -@@ -251,6 +251,13 @@ - help - Support for flash chips on NETtel/SecureEdge/SnapGear boards. - -+config MTD_AR91XX_FLASH -+ tristate "Atheros AR91xx parallel flash support" -+ depends on ATHEROS_AR71XX -+ select MTD_COMPLEX_MAPPINGS -+ help -+ Parallel flash driver for the Atheros AR91xx based boards. -+ - config MTD_DILNETPC - tristate "CFI Flash device mapped on DIL/Net PC" - depends on X86 && MTD_CONCAT && MTD_PARTITIONS && MTD_CFI_INTELEXT && BROKEN -diff -Nur linux-2.6.36.orig/drivers/mtd/maps/Makefile linux-2.6.36/drivers/mtd/maps/Makefile ---- linux-2.6.36.orig/drivers/mtd/maps/Makefile 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/drivers/mtd/maps/Makefile 2010-12-17 18:34:51.000000000 +0100 -@@ -7,6 +7,7 @@ - endif - - # Chip mappings -+obj-$(CONFIG_MTD_AR91XX_FLASH) += ar91xx_flash.o - obj-$(CONFIG_MTD_CDB89712) += cdb89712.o - obj-$(CONFIG_MTD_ARM_INTEGRATOR)+= integrator-flash.o - obj-$(CONFIG_MTD_CFI_FLAGADM) += cfi_flagadm.o -diff -Nur linux-2.6.36.orig/drivers/mtd/maps/ar91xx_flash.c linux-2.6.36/drivers/mtd/maps/ar91xx_flash.c ---- linux-2.6.36.orig/drivers/mtd/maps/ar91xx_flash.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/drivers/mtd/maps/ar91xx_flash.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,310 @@ -+/* -+ * Parallel flash driver for the Atheros AR91xx SoC -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#define DRV_NAME "ar91xx-flash" -+ -+struct ar91xx_flash_info { -+ struct mtd_info *mtd; -+ struct map_info map; -+#ifdef CONFIG_MTD_PARTITIONS -+ int nr_parts; -+ struct mtd_partition *parts; -+#endif -+}; -+ -+static map_word ar91xx_flash_read(struct map_info *map, unsigned long ofs) -+{ -+ map_word val; -+ -+ if (map_bankwidth_is_1(map)) -+ val.x[0] = __raw_readb(map->virt + (ofs ^ 3)); -+ else if (map_bankwidth_is_2(map)) -+ val.x[0] = __raw_readw(map->virt + (ofs ^ 2)); -+ else -+ val = map_word_ff(map); -+ -+ return val; -+} -+ -+static void ar91xx_flash_write(struct map_info *map, map_word d, -+ unsigned long ofs) -+{ -+ if (map_bankwidth_is_1(map)) -+ __raw_writeb(d.x[0], map->virt + (ofs ^ 3)); -+ else if (map_bankwidth_is_2(map)) -+ __raw_writew(d.x[0], map->virt + (ofs ^ 2)); -+ -+ mb(); -+} -+ -+static map_word ar91xx_flash_read_lock(struct map_info *map, unsigned long ofs) -+{ -+ map_word ret; -+ -+ ar71xx_flash_acquire(); -+ ret = ar91xx_flash_read(map, ofs); -+ ar71xx_flash_release(); -+ -+ return ret; -+} -+ -+static void ar91xx_flash_write_lock(struct map_info *map, map_word d, -+ unsigned long ofs) -+{ -+ ar71xx_flash_acquire(); -+ ar91xx_flash_write(map, d, ofs); -+ ar71xx_flash_release(); -+} -+ -+static void ar91xx_flash_copy_from_lock(struct map_info *map, void *to, -+ unsigned long from, ssize_t len) -+{ -+ ar71xx_flash_acquire(); -+ inline_map_copy_from(map, to, from, len); -+ ar71xx_flash_release(); -+} -+ -+static void ar91xx_flash_copy_to_lock(struct map_info *map, unsigned long to, -+ const void *from, ssize_t len) -+{ -+ ar71xx_flash_acquire(); -+ inline_map_copy_to(map, to, from, len); -+ ar71xx_flash_release(); -+} -+ -+static int ar91xx_flash_remove(struct platform_device *pdev) -+{ -+ struct ar91xx_flash_platform_data *pdata; -+ struct ar91xx_flash_info *info; -+ -+ info = platform_get_drvdata(pdev); -+ if (info == NULL) -+ return 0; -+ -+ platform_set_drvdata(pdev, NULL); -+ -+ if (info->mtd == NULL) -+ return 0; -+ -+ pdata = pdev->dev.platform_data; -+#ifdef CONFIG_MTD_PARTITIONS -+ if (info->nr_parts) { -+ del_mtd_partitions(info->mtd); -+ kfree(info->parts); -+ } else if (pdata->nr_parts) { -+ del_mtd_partitions(info->mtd); -+ } else { -+ del_mtd_device(info->mtd); -+ } -+#else -+ del_mtd_device(info->mtd); -+#endif -+ map_destroy(info->mtd); -+ -+ return 0; -+} -+ -+static const char *rom_probe_types[] = { "cfi_probe", "jedec_probe", NULL }; -+#ifdef CONFIG_MTD_PARTITIONS -+static const char *part_probe_types[] = { "cmdlinepart", "RedBoot", NULL }; -+#endif -+ -+static int ar91xx_flash_probe(struct platform_device *pdev) -+{ -+ struct ar91xx_flash_platform_data *pdata; -+ struct ar91xx_flash_info *info; -+ struct resource *res; -+ struct resource *region; -+ const char **probe_type; -+ int err = 0; -+ -+ pdata = pdev->dev.platform_data; -+ if (pdata == NULL) -+ return -EINVAL; -+ -+ info = devm_kzalloc(&pdev->dev, sizeof(struct ar91xx_flash_info), -+ GFP_KERNEL); -+ if (info == NULL) { -+ err = -ENOMEM; -+ goto err_out; -+ } -+ -+ platform_set_drvdata(pdev, info); -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (res == NULL) { -+ err = -ENOENT; -+ goto err_out; -+ } -+ -+ dev_info(&pdev->dev, "%.8llx at %.8llx\n", -+ (unsigned long long)(res->end - res->start + 1), -+ (unsigned long long)res->start); -+ -+ region = devm_request_mem_region(&pdev->dev, -+ res->start, res->end - res->start + 1, -+ dev_name(&pdev->dev)); -+ if (region == NULL) { -+ dev_err(&pdev->dev, "could not reserve memory region\n"); -+ err = -ENOMEM; -+ goto err_out; -+ } -+ -+ info->map.name = dev_name(&pdev->dev); -+ info->map.phys = res->start; -+ info->map.size = res->end - res->start + 1; -+ info->map.bankwidth = pdata->width; -+ -+ info->map.virt = devm_ioremap(&pdev->dev, info->map.phys, -+ info->map.size); -+ if (info->map.virt == NULL) { -+ dev_err(&pdev->dev, "failed to ioremap flash region\n"); -+ err = -EIO; -+ goto err_out; -+ } -+ -+ simple_map_init(&info->map); -+ if (pdata->is_shared) { -+ info->map.read = ar91xx_flash_read_lock; -+ info->map.write = ar91xx_flash_write_lock; -+ info->map.copy_from = ar91xx_flash_copy_from_lock; -+ info->map.copy_to = ar91xx_flash_copy_to_lock; -+ } else { -+ info->map.read = ar91xx_flash_read; -+ info->map.write = ar91xx_flash_write; -+ } -+ -+ probe_type = rom_probe_types; -+ for (; info->mtd == NULL && *probe_type != NULL; probe_type++) -+ info->mtd = do_map_probe(*probe_type, &info->map); -+ -+ if (info->mtd == NULL) { -+ dev_err(&pdev->dev, "map_probe failed\n"); -+ err = -ENXIO; -+ goto err_out; -+ } -+ -+ info->mtd->owner = THIS_MODULE; -+ -+#ifdef CONFIG_MTD_PARTITIONS -+ if (pdata->nr_parts) { -+ dev_info(&pdev->dev, "using static partition mapping\n"); -+ add_mtd_partitions(info->mtd, pdata->parts, pdata->nr_parts); -+ return 0; -+ } -+ -+ err = parse_mtd_partitions(info->mtd, part_probe_types, -+ &info->parts, 0); -+ if (err > 0) { -+ add_mtd_partitions(info->mtd, info->parts, err); -+ return 0; -+ } -+#endif -+ -+ add_mtd_device(info->mtd); -+ return 0; -+ -+ err_out: -+ ar91xx_flash_remove(pdev); -+ return err; -+} -+ -+#ifdef CONFIG_PM -+static int ar91xx_flash_suspend(struct platform_device *dev, pm_message_t state) -+{ -+ struct ar91xx_flash_info *info = platform_get_drvdata(dev); -+ int ret = 0; -+ -+ if (info->mtd->suspend) -+ ret = info->mtd->suspend(info->mtd); -+ -+ if (ret) -+ goto fail; -+ -+ return 0; -+ -+ fail: -+ if (info->mtd->suspend) { -+ BUG_ON(!info->mtd->resume); -+ info->mtd->resume(info->mtd); -+ } -+ -+ return ret; -+} -+ -+static int ar91xx_flash_resume(struct platform_device *pdev) -+{ -+ struct ar91xx_flash_info *info = platform_get_drvdata(pdev); -+ -+ if (info->mtd->resume) -+ info->mtd->resume(info->mtd); -+ -+ return 0; -+} -+ -+static void ar91xx_flash_shutdown(struct platform_device *pdev) -+{ -+ struct ar91xx_flash_info *info = platform_get_drvdata(pdev); -+ -+ if (info->mtd->suspend && info->mtd->resume) -+ if (info->mtd->suspend(info->mtd) == 0) -+ info->mtd->resume(info->mtd); -+} -+#else -+#define ar91xx_flash_suspend NULL -+#define ar91xx_flash_resume NULL -+#define ar91xx_flash_shutdown NULL -+#endif -+ -+static struct platform_driver ar91xx_flash_driver = { -+ .probe = ar91xx_flash_probe, -+ .remove = ar91xx_flash_remove, -+ .suspend = ar91xx_flash_suspend, -+ .resume = ar91xx_flash_resume, -+ .shutdown = ar91xx_flash_shutdown, -+ .driver = { -+ .name = DRV_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init ar91xx_flash_init(void) -+{ -+ return platform_driver_register(&ar91xx_flash_driver); -+} -+ -+static void __exit ar91xx_flash_exit(void) -+{ -+ platform_driver_unregister(&ar91xx_flash_driver); -+} -+ -+module_init(ar91xx_flash_init); -+module_exit(ar91xx_flash_exit); -+ -+MODULE_LICENSE("GPL v2"); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_DESCRIPTION("Parallel flash driver for the Atheros AR91xx SoC"); -+MODULE_ALIAS("platform:" DRV_NAME); -diff -Nur linux-2.6.36.orig/drivers/mtd/nand/Kconfig linux-2.6.36/drivers/mtd/nand/Kconfig ---- linux-2.6.36.orig/drivers/mtd/nand/Kconfig 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/drivers/mtd/nand/Kconfig 2010-12-17 18:34:51.000000000 +0100 -@@ -531,4 +531,8 @@ - help - Enables support for NAND Flash on JZ4740 SoC based boards. - -+config MTD_NAND_RB4XX -+ tristate "NAND flash driver for RouterBoard 4xx series" -+ depends on MTD_NAND && AR71XX_MACH_RB4XX -+ - endif # MTD_NAND -diff -Nur linux-2.6.36.orig/drivers/mtd/nand/Makefile linux-2.6.36/drivers/mtd/nand/Makefile ---- linux-2.6.36.orig/drivers/mtd/nand/Makefile 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/drivers/mtd/nand/Makefile 2010-12-17 18:34:51.000000000 +0100 -@@ -32,6 +32,7 @@ - obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx_nand.o - obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o - obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o -+obj-$(CONFIG_MTD_NAND_RB4XX) += rb4xx_nand.o - obj-$(CONFIG_MTD_ALAUDA) += alauda.o - obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o - obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o -diff -Nur linux-2.6.36.orig/drivers/mtd/nand/rb4xx_nand.c linux-2.6.36/drivers/mtd/nand/rb4xx_nand.c ---- linux-2.6.36.orig/drivers/mtd/nand/rb4xx_nand.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/drivers/mtd/nand/rb4xx_nand.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,513 @@ -+/* -+ * NAND flash driver for the MikroTik RouterBoard 4xx series -+ * -+ * Copyright (C) 2008 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This file was based on the driver for Linux 2.6.22 published by -+ * MikroTik for their RouterBoard 4xx series devices. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#define DRV_NAME "rb4xx-nand" -+#define DRV_VERSION "0.1.10" -+#define DRV_DESC "NAND flash driver for RouterBoard 4xx series" -+ -+#define USE_FAST_READ 1 -+#define USE_FAST_WRITE 1 -+#undef RB4XX_NAND_DEBUG -+ -+#ifdef RB4XX_NAND_DEBUG -+#define DBG(fmt, arg...) printk(KERN_DEBUG DRV_NAME ": " fmt, ## arg) -+#else -+#define DBG(fmt, arg...) do {} while (0) -+#endif -+ -+#define RB4XX_NAND_GPIO_RDY 5 -+#define RB4XX_FLASH_HZ 33333334 -+#define RB4XX_NAND_HZ 33333334 -+ -+#define SPI_CTRL_FASTEST 0x40 -+#define SPI_CTRL_SAFE 0x43 /* 25 MHz for AHB 200 MHz */ -+#define SBIT_IOC_BASE SPI_IOC_CS1 -+#define SBIT_IOC_DO_SHIFT 0 -+#define SBIT_IOC_DO (1u << SBIT_IOC_DO_SHIFT) -+#define SBIT_IOC_DO2_SHIFT 18 -+#define SBIT_IOC_DO2 (1u << SBIT_IOC_DO2_SHIFT) -+ -+#define CPLD_CMD_WRITE_MULT 0x08 /* send cmd, n x send data, read data */ -+#define CPLD_CMD_WRITE_CFG 0x09 /* send cmd, n x send cfg */ -+#define CPLD_CMD_READ_MULT 0x0a /* send cmd, send idle, n x read data */ -+#define CPLD_CMD_READ_FAST 0x0b /* send cmd, 4 x idle, n x read data */ -+ -+#define CFG_BIT_nCE 0x80 -+#define CFG_BIT_CLE 0x40 -+#define CFG_BIT_ALE 0x20 -+#define CFG_BIT_FAN 0x10 -+#define CFG_BIT_nLED4 0x08 -+#define CFG_BIT_nLED3 0x04 -+#define CFG_BIT_nLED2 0x02 -+#define CFG_BIT_nLED1 0x01 -+ -+#define CFG_BIT_nLEDS \ -+ (CFG_BIT_nLED1 | CFG_BIT_nLED2 | CFG_BIT_nLED3 | CFG_BIT_nLED4) -+ -+struct rb4xx_nand_info { -+ struct nand_chip chip; -+ struct mtd_info mtd; -+}; -+ -+/* -+ * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader -+ * will not be able to find the kernel that we load. -+ */ -+static struct nand_ecclayout rb4xx_nand_ecclayout = { -+ .eccbytes = 6, -+ .eccpos = { 8, 9, 10, 13, 14, 15 }, -+ .oobavail = 9, -+ .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } } -+}; -+ -+static struct mtd_partition rb4xx_nand_partitions[] = { -+ { -+ .name = "booter", -+ .offset = 0, -+ .size = (256 * 1024), -+ .mask_flags = MTD_WRITEABLE, -+ }, -+ { -+ .name = "kernel", -+ .offset = (256 * 1024), -+ .size = (4 * 1024 * 1024) - (256 * 1024), -+ }, -+ { -+ .name = "rootfs", -+ .offset = MTDPART_OFS_NXTBLK, -+ .size = (1024*1024*64) - (1024*256) - (4 * 1024 * 1024) -+ }, -+ { -+ .name = "cfgfs", -+ .offset = (1024*1024*64) - (1024*256), -+ .size = (1024*256), -+ }, -+}; -+ -+#if USE_FAST_READ -+#define SPI_NDATA_BASE 0x00800000 -+static unsigned spi_ctrl_fread = SPI_CTRL_SAFE; -+static unsigned spi_ctrl_flash = SPI_CTRL_SAFE; -+extern unsigned mips_hpt_frequency; -+#endif -+ -+static inline unsigned rb4xx_spi_rreg(unsigned r) -+{ -+ return __raw_readl((void * __iomem)(KSEG1ADDR(AR71XX_SPI_BASE) + r)); -+} -+ -+static inline void rb4xx_spi_wreg(unsigned r, unsigned v) -+{ -+ __raw_writel(v, (void * __iomem)(KSEG1ADDR(AR71XX_SPI_BASE) + r)); -+} -+ -+static inline void do_spi_clk(int bit) -+{ -+ unsigned bval = SBIT_IOC_BASE | (bit & 1); -+ -+ rb4xx_spi_wreg(SPI_REG_IOC, bval); -+ rb4xx_spi_wreg(SPI_REG_IOC, bval | SPI_IOC_CLK); -+} -+ -+static void do_spi_byte(uint8_t byte) -+{ -+ do_spi_clk(byte >> 7); -+ do_spi_clk(byte >> 6); -+ do_spi_clk(byte >> 5); -+ do_spi_clk(byte >> 4); -+ do_spi_clk(byte >> 3); -+ do_spi_clk(byte >> 2); -+ do_spi_clk(byte >> 1); -+ do_spi_clk(byte); -+ -+ DBG("spi_byte sent 0x%02x got 0x%x\n", -+ byte, rb4xx_spi_rreg(SPI_REG_RDS)); -+} -+ -+#if USE_FAST_WRITE -+static inline void do_spi_clk_fast(int bit1, int bit2) -+{ -+ unsigned bval = (SBIT_IOC_BASE | -+ ((bit1 << SBIT_IOC_DO_SHIFT) & SBIT_IOC_DO) | -+ ((bit2 << SBIT_IOC_DO2_SHIFT) & SBIT_IOC_DO2)); -+ -+ rb4xx_spi_wreg(SPI_REG_IOC, bval); -+ rb4xx_spi_wreg(SPI_REG_IOC, bval | SPI_IOC_CLK); -+} -+ -+static inline void do_spi_byte_fast(uint8_t byte) -+{ -+ do_spi_clk_fast(byte >> 7, byte >> 6); -+ do_spi_clk_fast(byte >> 5, byte >> 4); -+ do_spi_clk_fast(byte >> 3, byte >> 2); -+ do_spi_clk_fast(byte >> 1, byte >> 0); -+ -+ DBG("spi_byte_fast sent 0x%02x got 0x%x\n", -+ byte, rb4xx_spi_rreg(SPI_REG_RDS)); -+} -+#else -+static inline void do_spi_byte_fast(uint8_t byte) -+{ -+ do_spi_byte(byte); -+} -+#endif /* USE_FAST_WRITE */ -+ -+static int do_spi_cmd(unsigned cmd, unsigned sendCnt, const uint8_t *sendData, -+ unsigned recvCnt, uint8_t *recvData, -+ const uint8_t *verifyData, int fastWrite) -+{ -+ unsigned i; -+ -+ DBG("SPI cmd 0x%x send %u recv %u\n", cmd, sendCnt, recvCnt); -+ -+ rb4xx_spi_wreg(SPI_REG_FS, SPI_FS_GPIO); -+ rb4xx_spi_wreg(SPI_REG_CTRL, SPI_CTRL_FASTEST); -+ -+ do_spi_byte(cmd); -+#if 0 -+ if (cmd == CPLD_CMD_READ_FAST) { -+ do_spi_byte(0x80); -+ do_spi_byte(0); -+ do_spi_byte(0); -+ } -+#endif -+ for (i = 0; i < sendCnt; ++i) { -+ if (fastWrite) -+ do_spi_byte_fast(sendData[i]); -+ else -+ do_spi_byte(sendData[i]); -+ } -+ -+ for (i = 0; i < recvCnt; ++i) { -+ if (fastWrite) -+ do_spi_byte_fast(0); -+ else -+ do_spi_byte(0); -+ -+ if (recvData) { -+ recvData[i] = rb4xx_spi_rreg(SPI_REG_RDS) & 0xff; -+ } else if (verifyData) { -+ if (verifyData[i] != (rb4xx_spi_rreg(SPI_REG_RDS) -+ & 0xff)) -+ break; -+ } -+ } -+ -+ rb4xx_spi_wreg(SPI_REG_IOC, SBIT_IOC_BASE | SPI_IOC_CS0); -+ rb4xx_spi_wreg(SPI_REG_CTRL, spi_ctrl_flash); -+ rb4xx_spi_wreg(SPI_REG_FS, 0); -+ -+ return i == recvCnt; -+} -+ -+static int got_write = 1; -+ -+static void rb4xx_nand_write_data(const uint8_t *byte, unsigned cnt) -+{ -+ do_spi_cmd(CPLD_CMD_WRITE_MULT, cnt, byte, 1, NULL, NULL, 1); -+ got_write = 1; -+} -+ -+static void rb4xx_nand_write_byte(uint8_t byte) -+{ -+ rb4xx_nand_write_data(&byte, 1); -+} -+ -+#if USE_FAST_READ -+static uint8_t *rb4xx_nand_read_getaddr(unsigned cnt) -+{ -+ static unsigned nboffset = 0x100000; -+ unsigned addr; -+ -+ if (got_write) { -+ nboffset = (nboffset + 31) & ~31; -+ if (nboffset >= 0x100000) /* 1MB */ -+ nboffset = 0; -+ -+ got_write = 0; -+ rb4xx_spi_wreg(SPI_REG_FS, SPI_FS_GPIO); -+ rb4xx_spi_wreg(SPI_REG_CTRL, spi_ctrl_fread); -+ rb4xx_spi_wreg(SPI_REG_FS, 0); -+ } -+ -+ addr = KSEG1ADDR(AR71XX_SPI_BASE + SPI_NDATA_BASE) + nboffset; -+ DBG("rb4xx_nand_read_getaddr 0x%x cnt 0x%x\n", addr, cnt); -+ -+ nboffset += cnt; -+ return (uint8_t *)addr; -+} -+ -+static void rb4xx_nand_read_data(uint8_t *buf, unsigned cnt) -+{ -+ unsigned size32 = cnt & ~31; -+ unsigned remain = cnt & 31; -+ -+ if (size32) { -+ uint8_t *addr = rb4xx_nand_read_getaddr(size32); -+ memcpy(buf, (void *)addr, size32); -+ } -+ -+ if (remain) { -+ do_spi_cmd(CPLD_CMD_READ_MULT, 1, buf, remain, -+ buf + size32, NULL, 0); -+ } -+} -+ -+static int rb4xx_nand_verify_data(const uint8_t *buf, unsigned cnt) -+{ -+ unsigned size32 = cnt & ~31; -+ unsigned remain = cnt & 31; -+ -+ if (size32) { -+ uint8_t *addr = rb4xx_nand_read_getaddr(size32); -+ if (memcmp(buf, (void *)addr, size32) != 0) -+ return 0; -+ } -+ -+ if (remain) { -+ return do_spi_cmd(CPLD_CMD_READ_MULT, 1, buf, remain, -+ NULL, buf + size32, 0); -+ } -+ return 1; -+} -+#else /* USE_FAST_READ */ -+static void rb4xx_nand_read_data(uint8_t *buf, unsigned cnt) -+{ -+ do_spi_cmd(CPLD_CMD_READ_MULT, 1, buf, cnt, buf, NULL, 0); -+} -+ -+static int rb4xx_nand_verify_data(const uint8_t *buf, unsigned cnt) -+{ -+ return do_spi_cmd(CPLD_CMD_READ_MULT, 1, buf, cnt, NULL, buf, 0); -+} -+#endif /* USE_FAST_READ */ -+ -+static void rb4xx_nand_write_cfg(uint8_t byte) -+{ -+ do_spi_cmd(CPLD_CMD_WRITE_CFG, 1, &byte, 0, NULL, NULL, 0); -+ got_write = 1; -+} -+ -+static int rb4xx_nand_dev_ready(struct mtd_info *mtd) -+{ -+ return gpio_get_value(RB4XX_NAND_GPIO_RDY); -+} -+ -+static void rb4xx_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, -+ unsigned int ctrl) -+{ -+ if (ctrl & NAND_CTRL_CHANGE) { -+ uint8_t cfg = CFG_BIT_nLEDS; -+ -+ cfg |= (ctrl & NAND_CLE) ? CFG_BIT_CLE : 0; -+ cfg |= (ctrl & NAND_ALE) ? CFG_BIT_ALE : 0; -+ cfg |= (ctrl & NAND_NCE) ? 0 : CFG_BIT_nCE; -+ -+ rb4xx_nand_write_cfg(cfg); -+ } -+ -+ if (cmd != NAND_CMD_NONE) -+ rb4xx_nand_write_byte(cmd); -+} -+ -+static uint8_t rb4xx_nand_read_byte(struct mtd_info *mtd) -+{ -+ uint8_t byte = 0; -+ -+ rb4xx_nand_read_data(&byte, 1); -+ return byte; -+} -+ -+static void rb4xx_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, -+ int len) -+{ -+ rb4xx_nand_write_data(buf, len); -+} -+ -+static void rb4xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, -+ int len) -+{ -+ rb4xx_nand_read_data(buf, len); -+} -+ -+static int rb4xx_nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, -+ int len) -+{ -+ if (!rb4xx_nand_verify_data(buf, len)) -+ return -EFAULT; -+ -+ return 0; -+} -+ -+static unsigned get_spi_ctrl(unsigned hz_max, const char *name) -+{ -+ unsigned div; -+ -+ div = (ar71xx_ahb_freq - 1) / (2 * hz_max); -+ /* -+ * CPU has a bug at (div == 0) - first bit read is random -+ */ -+ if (div == 0) -+ ++div; -+ -+ if (name) { -+ unsigned ahb_khz = (ar71xx_ahb_freq + 500) / 1000; -+ unsigned div_real = 2 * (div + 1); -+ printk(KERN_INFO "%s SPI clock %u kHz (AHB %u kHz / %u)\n", -+ name, -+ ahb_khz / div_real, -+ ahb_khz, div_real); -+ } -+ -+ return SPI_CTRL_FASTEST + div; -+} -+ -+static int __init rb4xx_nand_probe(struct platform_device *pdev) -+{ -+ struct rb4xx_nand_info *info; -+ int ret; -+ -+ printk(KERN_INFO DRV_DESC " version " DRV_VERSION "\n"); -+ -+ ret = gpio_request(RB4XX_NAND_GPIO_RDY, "NAND RDY"); -+ if (ret) { -+ printk(KERN_ERR "rb4xx-nand: gpio request failed\n"); -+ return ret; -+ } -+ -+ ret = gpio_direction_input(RB4XX_NAND_GPIO_RDY); -+ if (ret) { -+ printk(KERN_ERR "rb4xx-nand: unable to set input mode " -+ "on gpio%d\n", RB4XX_NAND_GPIO_RDY); -+ goto err_free_gpio; -+ } -+ -+ info = kzalloc(sizeof(*info), GFP_KERNEL); -+ if (!info) { -+ printk(KERN_ERR "rb4xx-nand: no memory for private data\n"); -+ ret = -ENOMEM; -+ goto err_free_gpio; -+ } -+ -+#if USE_FAST_READ -+ spi_ctrl_fread = get_spi_ctrl(RB4XX_NAND_HZ, "NAND"); -+#endif -+ spi_ctrl_flash = get_spi_ctrl(RB4XX_FLASH_HZ, "FLASH"); -+ -+ rb4xx_nand_write_cfg(CFG_BIT_nLEDS | CFG_BIT_nCE); -+ -+ info->chip.priv = &info; -+ info->mtd.priv = &info->chip; -+ info->mtd.owner = THIS_MODULE; -+ -+ info->chip.cmd_ctrl = rb4xx_nand_cmd_ctrl; -+ info->chip.dev_ready = rb4xx_nand_dev_ready; -+ info->chip.read_byte = rb4xx_nand_read_byte; -+ info->chip.write_buf = rb4xx_nand_write_buf; -+ info->chip.read_buf = rb4xx_nand_read_buf; -+ info->chip.verify_buf = rb4xx_nand_verify_buf; -+ -+ info->chip.chip_delay = 25; -+ info->chip.ecc.mode = NAND_ECC_SOFT; -+ info->chip.options |= NAND_NO_AUTOINCR; -+ -+ platform_set_drvdata(pdev, info); -+ -+ ret = nand_scan_ident(&info->mtd, 1, NULL); -+ if (ret) { -+ ret = -ENXIO; -+ goto err_free_info; -+ } -+ -+ if (info->mtd.writesize == 512) -+ info->chip.ecc.layout = &rb4xx_nand_ecclayout; -+ -+ ret = nand_scan_tail(&info->mtd); -+ if (ret) { -+ return -ENXIO; -+ goto err_set_drvdata; -+ } -+ -+#ifdef CONFIG_MTD_PARTITIONS -+ ret = add_mtd_partitions(&info->mtd, rb4xx_nand_partitions, -+ ARRAY_SIZE(rb4xx_nand_partitions)); -+#else -+ ret = add_mtd_device(&info->mtd); -+#endif -+ if (ret) -+ goto err_release_nand; -+ -+ return 0; -+ -+err_release_nand: -+ nand_release(&info->mtd); -+err_set_drvdata: -+ platform_set_drvdata(pdev, NULL); -+err_free_info: -+ kfree(info); -+err_free_gpio: -+ gpio_free(RB4XX_NAND_GPIO_RDY); -+ return ret; -+} -+ -+static int __devexit rb4xx_nand_remove(struct platform_device *pdev) -+{ -+ struct rb4xx_nand_info *info = platform_get_drvdata(pdev); -+ -+ nand_release(&info->mtd); -+ platform_set_drvdata(pdev, NULL); -+ kfree(info); -+ -+ return 0; -+} -+ -+static struct platform_driver rb4xx_nand_driver = { -+ .probe = rb4xx_nand_probe, -+ .remove = __devexit_p(rb4xx_nand_remove), -+ .driver = { -+ .name = DRV_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init rb4xx_nand_init(void) -+{ -+ return platform_driver_register(&rb4xx_nand_driver); -+} -+ -+static void __exit rb4xx_nand_exit(void) -+{ -+ platform_driver_unregister(&rb4xx_nand_driver); -+} -+ -+module_init(rb4xx_nand_init); -+module_exit(rb4xx_nand_exit); -+ -+MODULE_DESCRIPTION(DRV_DESC); -+MODULE_VERSION(DRV_VERSION); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_AUTHOR("Imre Kaloz "); -+MODULE_LICENSE("GPL v2"); -diff -Nur linux-2.6.36.orig/drivers/mtd/nand/rb750_nand.c linux-2.6.36/drivers/mtd/nand/rb750_nand.c ---- linux-2.6.36.orig/drivers/mtd/nand/rb750_nand.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/drivers/mtd/nand/rb750_nand.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,360 @@ -+/* -+ * NAND flash driver for the MikroTik RouterBOARD 750 -+ * -+ * Copyright (C) 2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#define DRV_NAME "rb750-nand" -+#define DRV_VERSION "0.1.0" -+#define DRV_DESC "NAND flash driver for the RouterBOARD 750" -+ -+#define RB750_NAND_IO0 BIT(RB750_GPIO_NAND_IO0) -+#define RB750_NAND_ALE BIT(RB750_GPIO_NAND_ALE) -+#define RB750_NAND_CLE BIT(RB750_GPIO_NAND_CLE) -+#define RB750_NAND_NRE BIT(RB750_GPIO_NAND_NRE) -+#define RB750_NAND_NWE BIT(RB750_GPIO_NAND_NWE) -+#define RB750_NAND_RDY BIT(RB750_GPIO_NAND_RDY) -+#define RB750_NAND_NCE BIT(RB750_GPIO_NAND_NCE) -+ -+#define RB750_NAND_DATA_SHIFT 1 -+#define RB750_NAND_DATA_BITS (0xff << RB750_NAND_DATA_SHIFT) -+#define RB750_NAND_INPUT_BITS (RB750_NAND_DATA_BITS | RB750_NAND_RDY) -+#define RB750_NAND_OUTPUT_BITS (RB750_NAND_ALE | RB750_NAND_CLE | \ -+ RB750_NAND_NRE | RB750_NAND_NWE | \ -+ RB750_NAND_NCE) -+ -+struct rb750_nand_info { -+ struct nand_chip chip; -+ struct mtd_info mtd; -+}; -+ -+/* -+ * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader -+ * will not be able to find the kernel that we load. -+ */ -+static struct nand_ecclayout rb750_nand_ecclayout = { -+ .eccbytes = 6, -+ .eccpos = { 8, 9, 10, 13, 14, 15 }, -+ .oobavail = 9, -+ .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } } -+}; -+ -+static struct mtd_partition rb750_nand_partitions[] = { -+ { -+ .name = "booter", -+ .offset = 0, -+ .size = (256 * 1024), -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "kernel", -+ .offset = (256 * 1024), -+ .size = (4 * 1024 * 1024) - (256 * 1024), -+ }, { -+ .name = "rootfs", -+ .offset = MTDPART_OFS_NXTBLK, -+ .size = MTDPART_SIZ_FULL, -+ }, -+}; -+ -+static void rb750_nand_write(const u8 *buf, unsigned len) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ u32 out; -+ unsigned i; -+ -+ /* set data lines to output mode */ -+ __raw_writel(__raw_readl(base + GPIO_REG_OE) | RB750_NAND_DATA_BITS, -+ base + GPIO_REG_OE); -+ -+ out = __raw_readl(base + GPIO_REG_OUT); -+ out &= ~(RB750_NAND_DATA_BITS | RB750_NAND_NWE); -+ for (i = 0; i != len; i++) { -+ u32 data; -+ -+ data = buf[i]; -+ data <<= RB750_NAND_DATA_SHIFT; -+ data |= out; -+ __raw_writel(data, base + GPIO_REG_OUT); -+ -+ __raw_writel(data | RB750_NAND_NWE, base + GPIO_REG_OUT); -+ /* flush write */ -+ __raw_readl(base + GPIO_REG_OUT); -+ } -+ -+ /* set data lines to input mode */ -+ __raw_writel(__raw_readl(base + GPIO_REG_OE) & ~RB750_NAND_DATA_BITS, -+ base + GPIO_REG_OE); -+ /* flush write */ -+ __raw_readl(base + GPIO_REG_OE); -+} -+ -+static int rb750_nand_read_verify(u8 *read_buf, unsigned len, -+ const u8 *verify_buf) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ unsigned i; -+ -+ for (i = 0; i < len; i++) { -+ u8 data; -+ -+ /* activate RE line */ -+ __raw_writel(RB750_NAND_NRE, base + GPIO_REG_CLEAR); -+ /* flush write */ -+ __raw_readl(base + GPIO_REG_CLEAR); -+ -+ /* read input lines */ -+ data = __raw_readl(base + GPIO_REG_IN) >> RB750_NAND_DATA_SHIFT; -+ -+ /* deactivate RE line */ -+ __raw_writel(RB750_NAND_NRE, base + GPIO_REG_SET); -+ -+ if (read_buf) -+ read_buf[i] = data; -+ else if (verify_buf && verify_buf[i] != data) -+ return -EFAULT; -+ } -+ -+ return 0; -+} -+ -+static void rb750_nand_select_chip(struct mtd_info *mtd, int chip) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ u32 func; -+ -+ func = __raw_readl(base + GPIO_REG_FUNC); -+ if (chip >= 0) { -+ /* disable latch */ -+ rb750_latch_change(RB750_LVC573_LE, 0); -+ -+ /* disable alternate functions */ -+ ar71xx_gpio_function_setup(AR724X_GPIO_FUNC_JTAG_DISABLE, -+ AR724X_GPIO_FUNC_SPI_EN); -+ -+ /* set input mode for data lines */ -+ __raw_writel(__raw_readl(base + GPIO_REG_OE) & -+ ~RB750_NAND_INPUT_BITS, -+ base + GPIO_REG_OE); -+ -+ /* deactivate RE and WE lines */ -+ __raw_writel(RB750_NAND_NRE | RB750_NAND_NWE, -+ base + GPIO_REG_SET); -+ /* flush write */ -+ (void) __raw_readl(base + GPIO_REG_SET); -+ -+ /* activate CE line */ -+ __raw_writel(RB750_NAND_NCE, base + GPIO_REG_CLEAR); -+ } else { -+ /* deactivate CE line */ -+ __raw_writel(RB750_NAND_NCE, base + GPIO_REG_SET); -+ /* flush write */ -+ (void) __raw_readl(base + GPIO_REG_SET); -+ -+ __raw_writel(__raw_readl(base + GPIO_REG_OE) | -+ RB750_NAND_IO0 | RB750_NAND_RDY, -+ base + GPIO_REG_OE); -+ -+ /* restore alternate functions */ -+ ar71xx_gpio_function_setup(AR724X_GPIO_FUNC_SPI_EN, -+ AR724X_GPIO_FUNC_JTAG_DISABLE); -+ -+ /* enable latch */ -+ rb750_latch_change(0, RB750_LVC573_LE); -+ } -+} -+ -+static int rb750_nand_dev_ready(struct mtd_info *mtd) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ -+ return !!(__raw_readl(base + GPIO_REG_IN) & RB750_NAND_RDY); -+} -+ -+static void rb750_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, -+ unsigned int ctrl) -+{ -+ if (ctrl & NAND_CTRL_CHANGE) { -+ void __iomem *base = ar71xx_gpio_base; -+ u32 t; -+ -+ t = __raw_readl(base + GPIO_REG_OUT); -+ -+ t &= ~(RB750_NAND_CLE | RB750_NAND_ALE); -+ t |= (ctrl & NAND_CLE) ? RB750_NAND_CLE : 0; -+ t |= (ctrl & NAND_ALE) ? RB750_NAND_ALE : 0; -+ -+ __raw_writel(t, base + GPIO_REG_OUT); -+ /* flush write */ -+ __raw_readl(base + GPIO_REG_OUT); -+ } -+ -+ if (cmd != NAND_CMD_NONE) { -+ u8 t = cmd; -+ rb750_nand_write(&t, 1); -+ } -+} -+ -+static u8 rb750_nand_read_byte(struct mtd_info *mtd) -+{ -+ u8 data = 0; -+ rb750_nand_read_verify(&data, 1, NULL); -+ return data; -+} -+ -+static void rb750_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len) -+{ -+ rb750_nand_read_verify(buf, len, NULL); -+} -+ -+static void rb750_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len) -+{ -+ rb750_nand_write(buf, len); -+} -+ -+static int rb750_nand_verify_buf(struct mtd_info *mtd, const u8 *buf, int len) -+{ -+ return rb750_nand_read_verify(NULL, len, buf); -+} -+ -+static void __init rb750_nand_gpio_init(void) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ u32 out; -+ -+ out = __raw_readl(base + GPIO_REG_OUT); -+ -+ /* setup output levels */ -+ __raw_writel(RB750_NAND_NCE | RB750_NAND_NRE | RB750_NAND_NWE, -+ base + GPIO_REG_SET); -+ -+ __raw_writel(RB750_NAND_ALE | RB750_NAND_CLE, -+ base + GPIO_REG_CLEAR); -+ -+ /* setup input lines */ -+ __raw_writel(__raw_readl(base + GPIO_REG_OE) & ~(RB750_NAND_INPUT_BITS), -+ base + GPIO_REG_OE); -+ -+ /* setup output lines */ -+ __raw_writel(__raw_readl(base + GPIO_REG_OE) | RB750_NAND_OUTPUT_BITS, -+ base + GPIO_REG_OE); -+ -+ rb750_latch_change(~out & RB750_NAND_IO0, out & RB750_NAND_IO0); -+} -+ -+static int __init rb750_nand_probe(struct platform_device *pdev) -+{ -+ struct rb750_nand_info *info; -+ int ret; -+ -+ printk(KERN_INFO DRV_DESC " version " DRV_VERSION "\n"); -+ -+ rb750_nand_gpio_init(); -+ -+ info = kzalloc(sizeof(*info), GFP_KERNEL); -+ if (!info) -+ return -ENOMEM; -+ -+ info->chip.priv = &info; -+ info->mtd.priv = &info->chip; -+ info->mtd.owner = THIS_MODULE; -+ -+ info->chip.select_chip = rb750_nand_select_chip; -+ info->chip.cmd_ctrl = rb750_nand_cmd_ctrl; -+ info->chip.dev_ready = rb750_nand_dev_ready; -+ info->chip.read_byte = rb750_nand_read_byte; -+ info->chip.write_buf = rb750_nand_write_buf; -+ info->chip.read_buf = rb750_nand_read_buf; -+ info->chip.verify_buf = rb750_nand_verify_buf; -+ -+ info->chip.chip_delay = 25; -+ info->chip.ecc.mode = NAND_ECC_SOFT; -+ info->chip.options |= NAND_NO_AUTOINCR; -+ -+ platform_set_drvdata(pdev, info); -+ -+ ret = nand_scan_ident(&info->mtd, 1); -+ if (ret) { -+ ret = -ENXIO; -+ goto err_free_info; -+ } -+ -+ if (info->mtd.writesize == 512) -+ info->chip.ecc.layout = &rb750_nand_ecclayout; -+ -+ ret = nand_scan_tail(&info->mtd); -+ if (ret) { -+ return -ENXIO; -+ goto err_set_drvdata; -+ } -+ -+#ifdef CONFIG_MTD_PARTITIONS -+ ret = add_mtd_partitions(&info->mtd, rb750_nand_partitions, -+ ARRAY_SIZE(rb750_nand_partitions)); -+#else -+ ret = add_mtd_device(&info->mtd); -+#endif -+ if (ret) -+ goto err_release_nand; -+ -+ return 0; -+ -+ err_release_nand: -+ nand_release(&info->mtd); -+ err_set_drvdata: -+ platform_set_drvdata(pdev, NULL); -+ err_free_info: -+ kfree(info); -+ return ret; -+} -+ -+static int __devexit rb750_nand_remove(struct platform_device *pdev) -+{ -+ struct rb750_nand_info *info = platform_get_drvdata(pdev); -+ -+ nand_release(&info->mtd); -+ platform_set_drvdata(pdev, NULL); -+ kfree(info); -+ -+ return 0; -+} -+ -+static struct platform_driver rb750_nand_driver = { -+ .probe = rb750_nand_probe, -+ .remove = __devexit_p(rb750_nand_remove), -+ .driver = { -+ .name = DRV_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init rb750_nand_init(void) -+{ -+ return platform_driver_register(&rb750_nand_driver); -+} -+ -+static void __exit rb750_nand_exit(void) -+{ -+ platform_driver_unregister(&rb750_nand_driver); -+} -+ -+module_init(rb750_nand_init); -+module_exit(rb750_nand_exit); -+ -+MODULE_DESCRIPTION(DRV_DESC); -+MODULE_VERSION(DRV_VERSION); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_LICENSE("GPL v2"); -diff -Nur linux-2.6.36.orig/drivers/mtd/wrt160nl_part.c linux-2.6.36/drivers/mtd/wrt160nl_part.c ---- linux-2.6.36.orig/drivers/mtd/wrt160nl_part.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/drivers/mtd/wrt160nl_part.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,181 @@ -+/* -+ * Copyright (C) 2009 Christian Daniel -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ * -+ * TRX flash partition table. -+ * Based on ar7 map by Felix Fietkau -+ * -+ */ -+ -+#include -+#include -+#include -+ -+#include -+#include -+ -+struct cybertan_header { -+ char magic[4]; -+ u8 res1[4]; -+ char fw_date[3]; -+ char fw_ver[3]; -+ char id[4]; -+ char hw_ver; -+ char unused; -+ u8 flags[2]; -+ u8 res2[10]; -+}; -+ -+#define TRX_PARTS 6 -+#define TRX_MAGIC 0x30524448 -+#define TRX_MAX_OFFSET 3 -+ -+struct trx_header { -+ uint32_t magic; /* "HDR0" */ -+ uint32_t len; /* Length of file including header */ -+ uint32_t crc32; /* 32-bit CRC from flag_version to end of file */ -+ uint32_t flag_version; /* 0:15 flags, 16:31 version */ -+ uint32_t offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */ -+}; -+ -+#define IH_MAGIC 0x27051956 /* Image Magic Number */ -+#define IH_NMLEN 32 /* Image Name Length */ -+ -+struct uimage_header { -+ uint32_t ih_magic; /* Image Header Magic Number */ -+ uint32_t ih_hcrc; /* Image Header CRC Checksum */ -+ uint32_t ih_time; /* Image Creation Timestamp */ -+ uint32_t ih_size; /* Image Data Size */ -+ uint32_t ih_load; /* Data» Load Address */ -+ uint32_t ih_ep; /* Entry Point Address */ -+ uint32_t ih_dcrc; /* Image Data CRC Checksum */ -+ uint8_t ih_os; /* Operating System */ -+ uint8_t ih_arch; /* CPU architecture */ -+ uint8_t ih_type; /* Image Type */ -+ uint8_t ih_comp; /* Compression Type */ -+ uint8_t ih_name[IH_NMLEN]; /* Image Name */ -+}; -+ -+struct wrt160nl_header { -+ struct cybertan_header cybertan; -+ struct trx_header trx; -+ struct uimage_header uimage; -+} __attribute__ ((packed)); -+ -+static struct mtd_partition trx_parts[TRX_PARTS]; -+ -+static int wrt160nl_parse_partitions(struct mtd_info *master, -+ struct mtd_partition **pparts, -+ unsigned long origin) -+{ -+ struct wrt160nl_header *header; -+ struct trx_header *theader; -+ struct uimage_header *uheader; -+ size_t retlen; -+ unsigned int kernel_len; -+ int ret; -+ -+ header = vmalloc(sizeof(*header)); -+ if (!header) { -+ return -ENOMEM; -+ goto out; -+ } -+ -+ ret = master->read(master, 4 * master->erasesize, sizeof(*header), -+ &retlen, (void *) header); -+ if (ret) -+ goto free_hdr; -+ -+ if (retlen != sizeof(*header)) { -+ ret = -EIO; -+ goto free_hdr; -+ } -+ -+ if (strncmp(header->cybertan.magic, "NL16", 4) != 0) { -+ printk(KERN_NOTICE "%s: no WRT160NL signature found\n", -+ master->name); -+ goto free_hdr; -+ } -+ -+ theader = &header->trx; -+ if (le32_to_cpu(theader->magic) != TRX_MAGIC) { -+ printk(KERN_NOTICE "%s: no TRX header found\n", master->name); -+ goto free_hdr; -+ } -+ -+ uheader = &header->uimage; -+ if (uheader->ih_magic != IH_MAGIC) { -+ printk(KERN_NOTICE "%s: no uImage found\n", master->name); -+ goto free_hdr; -+ } -+ -+ kernel_len = le32_to_cpu(theader->offsets[1]) + sizeof(struct cybertan_header); -+ -+ trx_parts[0].name = "u-boot"; -+ trx_parts[0].offset = 0; -+ trx_parts[0].size = 4 * master->erasesize; -+ trx_parts[0].mask_flags = MTD_WRITEABLE; -+ -+ trx_parts[1].name = "kernel"; -+ trx_parts[1].offset = trx_parts[0].offset + trx_parts[0].size; -+ trx_parts[1].size = kernel_len; -+ trx_parts[1].mask_flags = 0; -+ -+ trx_parts[2].name = "rootfs"; -+ trx_parts[2].offset = trx_parts[1].offset + trx_parts[1].size; -+ trx_parts[2].size = master->size - 6 * master->erasesize - trx_parts[1].size; -+ trx_parts[2].mask_flags = 0; -+ -+ trx_parts[3].name = "nvram"; -+ trx_parts[3].offset = master->size - 2 * master->erasesize; -+ trx_parts[3].size = master->erasesize; -+ trx_parts[3].mask_flags = MTD_WRITEABLE; -+ -+ trx_parts[4].name = "art"; -+ trx_parts[4].offset = master->size - master->erasesize; -+ trx_parts[4].size = master->erasesize; -+ trx_parts[4].mask_flags = MTD_WRITEABLE; -+ -+ trx_parts[5].name = "firmware"; -+ trx_parts[5].offset = 4 * master->erasesize; -+ trx_parts[5].size = master->size - 6 * master->erasesize; -+ trx_parts[5].mask_flags = 0; -+ -+ *pparts = trx_parts; -+ ret = TRX_PARTS; -+ -+ free_hdr: -+ vfree(header); -+ out: -+ return ret; -+} -+ -+static struct mtd_part_parser wrt160nl_parser = { -+ .owner = THIS_MODULE, -+ .parse_fn = wrt160nl_parse_partitions, -+ .name = "wrt160nl", -+}; -+ -+static int __init wrt160nl_parser_init(void) -+{ -+ return register_mtd_parser(&wrt160nl_parser); -+} -+ -+module_init(wrt160nl_parser_init); -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Christian Daniel "); -diff -Nur linux-2.6.36.orig/drivers/net/Kconfig linux-2.6.36/drivers/net/Kconfig ---- linux-2.6.36.orig/drivers/net/Kconfig 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/drivers/net/Kconfig 2010-12-17 18:34:51.000000000 +0100 -@@ -2045,6 +2045,8 @@ - - The safe and default value for this is N. - -+source drivers/net/ag71xx/Kconfig -+ - config DL2K - tristate "DL2000/TC902x-based Gigabit Ethernet support" - depends on PCI -diff -Nur linux-2.6.36.orig/drivers/net/Makefile linux-2.6.36/drivers/net/Makefile ---- linux-2.6.36.orig/drivers/net/Makefile 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/drivers/net/Makefile 2010-12-17 18:34:51.000000000 +0100 -@@ -109,6 +109,7 @@ - # end link order section - # - -+obj-$(CONFIG_AG71XX) += ag71xx/ - obj-$(CONFIG_SUNDANCE) += sundance.o - obj-$(CONFIG_HAMACHI) += hamachi.o - obj-$(CONFIG_NET) += Space.o loopback.o -diff -Nur linux-2.6.36.orig/drivers/net/ag71xx/Kconfig linux-2.6.36/drivers/net/ag71xx/Kconfig ---- linux-2.6.36.orig/drivers/net/ag71xx/Kconfig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/drivers/net/ag71xx/Kconfig 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,33 @@ -+config AG71XX -+ tristate "Atheros AR71xx built-in ethernet mac support" -+ depends on ATHEROS_AR71XX -+ select PHYLIB -+ help -+ If you wish to compile a kernel for AR71xx/91xx and enable -+ ethernet support, then you should always answer Y to this. -+ -+if AG71XX -+ -+config AG71XX_DEBUG -+ bool "Atheros AR71xx built-in ethernet driver debugging" -+ default n -+ help -+ Atheros AR71xx built-in ethernet driver debugging messages. -+ -+config AG71XX_DEBUG_FS -+ bool "Atheros AR71xx built-in ethernet driver debugfs support" -+ depends on DEBUG_FS -+ default n -+ help -+ Say Y, if you need access to various statistics provided by -+ the ag71xx driver. -+ -+config AG71XX_AR8216_SUPPORT -+ bool "special support for the Atheros AR8216 switch" -+ default n -+ default y if AR71XX_MACH_WNR2000 || AR71XX_MACH_MZK_W04NU -+ help -+ Say 'y' here if you want to enable special support for the -+ Atheros AR8216 switch found on some boards. -+ -+endif -diff -Nur linux-2.6.36.orig/drivers/net/ag71xx/Makefile linux-2.6.36/drivers/net/ag71xx/Makefile ---- linux-2.6.36.orig/drivers/net/ag71xx/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/drivers/net/ag71xx/Makefile 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,14 @@ -+# -+# Makefile for the Atheros AR71xx built-in ethernet macs -+# -+ -+ag71xx-y += ag71xx_main.o -+ag71xx-y += ag71xx_ethtool.o -+ag71xx-y += ag71xx_phy.o -+ag71xx-y += ag71xx_mdio.o -+ -+ag71xx-$(CONFIG_AG71XX_DEBUG_FS) += ag71xx_debugfs.o -+ag71xx-$(CONFIG_AG71XX_AR8216_SUPPORT) += ag71xx_ar8216.o -+ -+obj-$(CONFIG_AG71XX) += ag71xx.o -+ -diff -Nur linux-2.6.36.orig/drivers/net/ag71xx/ag71xx.h linux-2.6.36/drivers/net/ag71xx/ag71xx.h ---- linux-2.6.36.orig/drivers/net/ag71xx/ag71xx.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/drivers/net/ag71xx/ag71xx.h 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,500 @@ -+/* -+ * Atheros AR71xx built-in ethernet mac driver -+ * -+ * Copyright (C) 2008-2010 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Based on Atheros' AG7100 driver -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef __AG71XX_H -+#define __AG71XX_H -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include -+#include -+ -+#define ETH_FCS_LEN 4 -+ -+#define AG71XX_DRV_NAME "ag71xx" -+#define AG71XX_DRV_VERSION "0.5.35" -+ -+#define AG71XX_NAPI_WEIGHT 64 -+#define AG71XX_OOM_REFILL (1 + HZ/10) -+ -+#define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE) -+#define AG71XX_INT_TX (AG71XX_INT_TX_PS) -+#define AG71XX_INT_RX (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF) -+ -+#define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX) -+#define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL) -+ -+#define AG71XX_TX_FIFO_LEN 2048 -+#define AG71XX_TX_MTU_LEN 1536 -+#define AG71XX_RX_PKT_RESERVE 64 -+#define AG71XX_RX_PKT_SIZE \ -+ (AG71XX_RX_PKT_RESERVE + ETH_HLEN + ETH_FRAME_LEN + ETH_FCS_LEN) -+ -+#define AG71XX_TX_RING_SIZE 64 -+#define AG71XX_TX_THRES_STOP (AG71XX_TX_RING_SIZE - 4) -+#define AG71XX_TX_THRES_WAKEUP \ -+ (AG71XX_TX_RING_SIZE - (AG71XX_TX_RING_SIZE / 4)) -+ -+#define AG71XX_RX_RING_SIZE 128 -+ -+#ifdef CONFIG_AG71XX_DEBUG -+#define DBG(fmt, args...) printk(KERN_DEBUG fmt, ## args) -+#else -+#define DBG(fmt, args...) do {} while (0) -+#endif -+ -+#define ag71xx_assert(_cond) \ -+do { \ -+ if (_cond) \ -+ break; \ -+ printk("%s,%d: assertion failed\n", __FILE__, __LINE__); \ -+ BUG(); \ -+} while (0) -+ -+struct ag71xx_desc { -+ u32 data; -+ u32 ctrl; -+#define DESC_EMPTY BIT(31) -+#define DESC_MORE BIT(24) -+#define DESC_PKTLEN_M 0xfff -+ u32 next; -+ u32 pad; -+} __attribute__((aligned(4))); -+ -+struct ag71xx_buf { -+ struct sk_buff *skb; -+ struct ag71xx_desc *desc; -+ dma_addr_t dma_addr; -+ u32 pad; -+}; -+ -+struct ag71xx_ring { -+ struct ag71xx_buf *buf; -+ u8 *descs_cpu; -+ dma_addr_t descs_dma; -+ unsigned int desc_size; -+ unsigned int curr; -+ unsigned int dirty; -+ unsigned int size; -+}; -+ -+struct ag71xx_mdio { -+ struct mii_bus *mii_bus; -+ int mii_irq[PHY_MAX_ADDR]; -+ void __iomem *mdio_base; -+ struct ag71xx_mdio_platform_data *pdata; -+}; -+ -+struct ag71xx_int_stats { -+ unsigned long rx_pr; -+ unsigned long rx_be; -+ unsigned long rx_of; -+ unsigned long tx_ps; -+ unsigned long tx_be; -+ unsigned long tx_ur; -+ unsigned long total; -+}; -+ -+struct ag71xx_napi_stats { -+ unsigned long napi_calls; -+ unsigned long rx_count; -+ unsigned long rx_packets; -+ unsigned long rx_packets_max; -+ unsigned long tx_count; -+ unsigned long tx_packets; -+ unsigned long tx_packets_max; -+ -+ unsigned long rx[AG71XX_NAPI_WEIGHT + 1]; -+ unsigned long tx[AG71XX_NAPI_WEIGHT + 1]; -+}; -+ -+struct ag71xx_debug { -+ struct dentry *debugfs_dir; -+ struct dentry *debugfs_int_stats; -+ struct dentry *debugfs_napi_stats; -+ -+ struct ag71xx_int_stats int_stats; -+ struct ag71xx_napi_stats napi_stats; -+}; -+ -+struct ag71xx { -+ void __iomem *mac_base; -+ void __iomem *mii_ctrl; -+ -+ spinlock_t lock; -+ struct platform_device *pdev; -+ struct net_device *dev; -+ struct napi_struct napi; -+ u32 msg_enable; -+ -+ struct ag71xx_ring rx_ring; -+ struct ag71xx_ring tx_ring; -+ -+ struct mii_bus *mii_bus; -+ struct phy_device *phy_dev; -+ -+ unsigned int link; -+ unsigned int speed; -+ int duplex; -+ -+ struct work_struct restart_work; -+ struct timer_list oom_timer; -+ -+#ifdef CONFIG_AG71XX_DEBUG_FS -+ struct ag71xx_debug debug; -+#endif -+}; -+ -+extern struct ethtool_ops ag71xx_ethtool_ops; -+void ag71xx_link_adjust(struct ag71xx *ag); -+ -+int ag71xx_mdio_driver_init(void) __init; -+void ag71xx_mdio_driver_exit(void); -+ -+int ag71xx_phy_connect(struct ag71xx *ag); -+void ag71xx_phy_disconnect(struct ag71xx *ag); -+void ag71xx_phy_start(struct ag71xx *ag); -+void ag71xx_phy_stop(struct ag71xx *ag); -+ -+static inline struct ag71xx_platform_data *ag71xx_get_pdata(struct ag71xx *ag) -+{ -+ return ag->pdev->dev.platform_data; -+} -+ -+static inline int ag71xx_desc_empty(struct ag71xx_desc *desc) -+{ -+ return ((desc->ctrl & DESC_EMPTY) != 0); -+} -+ -+static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc) -+{ -+ return (desc->ctrl & DESC_PKTLEN_M); -+} -+ -+/* Register offsets */ -+#define AG71XX_REG_MAC_CFG1 0x0000 -+#define AG71XX_REG_MAC_CFG2 0x0004 -+#define AG71XX_REG_MAC_IPG 0x0008 -+#define AG71XX_REG_MAC_HDX 0x000c -+#define AG71XX_REG_MAC_MFL 0x0010 -+#define AG71XX_REG_MII_CFG 0x0020 -+#define AG71XX_REG_MII_CMD 0x0024 -+#define AG71XX_REG_MII_ADDR 0x0028 -+#define AG71XX_REG_MII_CTRL 0x002c -+#define AG71XX_REG_MII_STATUS 0x0030 -+#define AG71XX_REG_MII_IND 0x0034 -+#define AG71XX_REG_MAC_IFCTL 0x0038 -+#define AG71XX_REG_MAC_ADDR1 0x0040 -+#define AG71XX_REG_MAC_ADDR2 0x0044 -+#define AG71XX_REG_FIFO_CFG0 0x0048 -+#define AG71XX_REG_FIFO_CFG1 0x004c -+#define AG71XX_REG_FIFO_CFG2 0x0050 -+#define AG71XX_REG_FIFO_CFG3 0x0054 -+#define AG71XX_REG_FIFO_CFG4 0x0058 -+#define AG71XX_REG_FIFO_CFG5 0x005c -+#define AG71XX_REG_FIFO_RAM0 0x0060 -+#define AG71XX_REG_FIFO_RAM1 0x0064 -+#define AG71XX_REG_FIFO_RAM2 0x0068 -+#define AG71XX_REG_FIFO_RAM3 0x006c -+#define AG71XX_REG_FIFO_RAM4 0x0070 -+#define AG71XX_REG_FIFO_RAM5 0x0074 -+#define AG71XX_REG_FIFO_RAM6 0x0078 -+#define AG71XX_REG_FIFO_RAM7 0x007c -+ -+#define AG71XX_REG_TX_CTRL 0x0180 -+#define AG71XX_REG_TX_DESC 0x0184 -+#define AG71XX_REG_TX_STATUS 0x0188 -+#define AG71XX_REG_RX_CTRL 0x018c -+#define AG71XX_REG_RX_DESC 0x0190 -+#define AG71XX_REG_RX_STATUS 0x0194 -+#define AG71XX_REG_INT_ENABLE 0x0198 -+#define AG71XX_REG_INT_STATUS 0x019c -+ -+#define MAC_CFG1_TXE BIT(0) /* Tx Enable */ -+#define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */ -+#define MAC_CFG1_RXE BIT(2) /* Rx Enable */ -+#define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */ -+#define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */ -+#define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */ -+#define MAC_CFG1_LB BIT(8) /* Loopback mode */ -+#define MAC_CFG1_SR BIT(31) /* Soft Reset */ -+ -+#define MAC_CFG2_FDX BIT(0) -+#define MAC_CFG2_CRC_EN BIT(1) -+#define MAC_CFG2_PAD_CRC_EN BIT(2) -+#define MAC_CFG2_LEN_CHECK BIT(4) -+#define MAC_CFG2_HUGE_FRAME_EN BIT(5) -+#define MAC_CFG2_IF_1000 BIT(9) -+#define MAC_CFG2_IF_10_100 BIT(8) -+ -+#define FIFO_CFG0_WTM BIT(0) /* Watermark Module */ -+#define FIFO_CFG0_RXS BIT(1) /* Rx System Module */ -+#define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */ -+#define FIFO_CFG0_TXS BIT(3) /* Tx System Module */ -+#define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */ -+#define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \ -+ | FIFO_CFG0_TXS | FIFO_CFG0_TXF) -+ -+#define FIFO_CFG0_ENABLE_SHIFT 8 -+ -+#define FIFO_CFG4_DE BIT(0) /* Drop Event */ -+#define FIFO_CFG4_DV BIT(1) /* RX_DV Event */ -+#define FIFO_CFG4_FC BIT(2) /* False Carrier */ -+#define FIFO_CFG4_CE BIT(3) /* Code Error */ -+#define FIFO_CFG4_CR BIT(4) /* CRC error */ -+#define FIFO_CFG4_LM BIT(5) /* Length Mismatch */ -+#define FIFO_CFG4_LO BIT(6) /* Length out of range */ -+#define FIFO_CFG4_OK BIT(7) /* Packet is OK */ -+#define FIFO_CFG4_MC BIT(8) /* Multicast Packet */ -+#define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */ -+#define FIFO_CFG4_DR BIT(10) /* Dribble */ -+#define FIFO_CFG4_LE BIT(11) /* Long Event */ -+#define FIFO_CFG4_CF BIT(12) /* Control Frame */ -+#define FIFO_CFG4_PF BIT(13) /* Pause Frame */ -+#define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */ -+#define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */ -+#define FIFO_CFG4_FT BIT(16) /* Frame Truncated */ -+#define FIFO_CFG4_UC BIT(17) /* Unicast Packet */ -+ -+#define FIFO_CFG5_DE BIT(0) /* Drop Event */ -+#define FIFO_CFG5_DV BIT(1) /* RX_DV Event */ -+#define FIFO_CFG5_FC BIT(2) /* False Carrier */ -+#define FIFO_CFG5_CE BIT(3) /* Code Error */ -+#define FIFO_CFG5_LM BIT(4) /* Length Mismatch */ -+#define FIFO_CFG5_LO BIT(5) /* Length Out of Range */ -+#define FIFO_CFG5_OK BIT(6) /* Packet is OK */ -+#define FIFO_CFG5_MC BIT(7) /* Multicast Packet */ -+#define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */ -+#define FIFO_CFG5_DR BIT(9) /* Dribble */ -+#define FIFO_CFG5_CF BIT(10) /* Control Frame */ -+#define FIFO_CFG5_PF BIT(11) /* Pause Frame */ -+#define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */ -+#define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */ -+#define FIFO_CFG5_LE BIT(14) /* Long Event */ -+#define FIFO_CFG5_FT BIT(15) /* Frame Truncated */ -+#define FIFO_CFG5_16 BIT(16) /* unknown */ -+#define FIFO_CFG5_17 BIT(17) /* unknown */ -+#define FIFO_CFG5_SF BIT(18) /* Short Frame */ -+#define FIFO_CFG5_BM BIT(19) /* Byte Mode */ -+ -+#define AG71XX_INT_TX_PS BIT(0) -+#define AG71XX_INT_TX_UR BIT(1) -+#define AG71XX_INT_TX_BE BIT(3) -+#define AG71XX_INT_RX_PR BIT(4) -+#define AG71XX_INT_RX_OF BIT(6) -+#define AG71XX_INT_RX_BE BIT(7) -+ -+#define MAC_IFCTL_SPEED BIT(16) -+ -+#define MII_CFG_CLK_DIV_4 0 -+#define MII_CFG_CLK_DIV_6 2 -+#define MII_CFG_CLK_DIV_8 3 -+#define MII_CFG_CLK_DIV_10 4 -+#define MII_CFG_CLK_DIV_14 5 -+#define MII_CFG_CLK_DIV_20 6 -+#define MII_CFG_CLK_DIV_28 7 -+#define MII_CFG_RESET BIT(31) -+ -+#define MII_CMD_WRITE 0x0 -+#define MII_CMD_READ 0x1 -+#define MII_ADDR_SHIFT 8 -+#define MII_IND_BUSY BIT(0) -+#define MII_IND_INVALID BIT(2) -+ -+#define TX_CTRL_TXE BIT(0) /* Tx Enable */ -+ -+#define TX_STATUS_PS BIT(0) /* Packet Sent */ -+#define TX_STATUS_UR BIT(1) /* Tx Underrun */ -+#define TX_STATUS_BE BIT(3) /* Bus Error */ -+ -+#define RX_CTRL_RXE BIT(0) /* Rx Enable */ -+ -+#define RX_STATUS_PR BIT(0) /* Packet Received */ -+#define RX_STATUS_OF BIT(2) /* Rx Overflow */ -+#define RX_STATUS_BE BIT(3) /* Bus Error */ -+ -+#define MII_CTRL_IF_MASK 3 -+#define MII_CTRL_SPEED_SHIFT 4 -+#define MII_CTRL_SPEED_MASK 3 -+#define MII_CTRL_SPEED_10 0 -+#define MII_CTRL_SPEED_100 1 -+#define MII_CTRL_SPEED_1000 2 -+ -+static inline void ag71xx_check_reg_offset(struct ag71xx *ag, unsigned reg) -+{ -+ switch (reg) { -+ case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL: -+ case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS: -+ break; -+ -+ default: -+ BUG(); -+ } -+} -+ -+static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value) -+{ -+ ag71xx_check_reg_offset(ag, reg); -+ -+ __raw_writel(value, ag->mac_base + reg); -+ /* flush write */ -+ (void) __raw_readl(ag->mac_base + reg); -+} -+ -+static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg) -+{ -+ ag71xx_check_reg_offset(ag, reg); -+ -+ return __raw_readl(ag->mac_base + reg); -+} -+ -+static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask) -+{ -+ void __iomem *r; -+ -+ ag71xx_check_reg_offset(ag, reg); -+ -+ r = ag->mac_base + reg; -+ __raw_writel(__raw_readl(r) | mask, r); -+ /* flush write */ -+ (void)__raw_readl(r); -+} -+ -+static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask) -+{ -+ void __iomem *r; -+ -+ ag71xx_check_reg_offset(ag, reg); -+ -+ r = ag->mac_base + reg; -+ __raw_writel(__raw_readl(r) & ~mask, r); -+ /* flush write */ -+ (void) __raw_readl(r); -+} -+ -+static inline void ag71xx_int_enable(struct ag71xx *ag, u32 ints) -+{ -+ ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints); -+} -+ -+static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints) -+{ -+ ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints); -+} -+ -+static inline void ag71xx_mii_ctrl_wr(struct ag71xx *ag, u32 value) -+{ -+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); -+ -+ if (pdata->is_ar724x) -+ return; -+ -+ __raw_writel(value, ag->mii_ctrl); -+ -+ /* flush write */ -+ __raw_readl(ag->mii_ctrl); -+} -+ -+static inline u32 ag71xx_mii_ctrl_rr(struct ag71xx *ag) -+{ -+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); -+ -+ if (pdata->is_ar724x) -+ return 0xffffffff; -+ -+ return __raw_readl(ag->mii_ctrl); -+} -+ -+static void inline ag71xx_mii_ctrl_set_if(struct ag71xx *ag, -+ unsigned int mii_if) -+{ -+ u32 t; -+ -+ t = ag71xx_mii_ctrl_rr(ag); -+ t &= ~(MII_CTRL_IF_MASK); -+ t |= (mii_if & MII_CTRL_IF_MASK); -+ ag71xx_mii_ctrl_wr(ag, t); -+} -+ -+static void inline ag71xx_mii_ctrl_set_speed(struct ag71xx *ag, -+ unsigned int speed) -+{ -+ u32 t; -+ -+ t = ag71xx_mii_ctrl_rr(ag); -+ t &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT); -+ t |= (speed & MII_CTRL_SPEED_MASK) << MII_CTRL_SPEED_SHIFT; -+ ag71xx_mii_ctrl_wr(ag, t); -+} -+ -+#ifdef CONFIG_AG71XX_AR8216_SUPPORT -+void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb); -+int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb, -+ int pktlen); -+static inline int ag71xx_has_ar8216(struct ag71xx *ag) -+{ -+ return ag71xx_get_pdata(ag)->has_ar8216; -+} -+#else -+static inline void ag71xx_add_ar8216_header(struct ag71xx *ag, -+ struct sk_buff *skb) -+{ -+} -+ -+static inline int ag71xx_remove_ar8216_header(struct ag71xx *ag, -+ struct sk_buff *skb, -+ int pktlen) -+{ -+ return 0; -+} -+static inline int ag71xx_has_ar8216(struct ag71xx *ag) -+{ -+ return 0; -+} -+#endif -+ -+#ifdef CONFIG_AG71XX_DEBUG_FS -+int ag71xx_debugfs_root_init(void); -+void ag71xx_debugfs_root_exit(void); -+int ag71xx_debugfs_init(struct ag71xx *ag); -+void ag71xx_debugfs_exit(struct ag71xx *ag); -+void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, u32 status); -+void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, int rx, int tx); -+#else -+static inline int ag71xx_debugfs_root_init(void) { return 0; } -+static inline void ag71xx_debugfs_root_exit(void) {} -+static inline int ag71xx_debugfs_init(struct ag71xx *ag) { return 0; } -+static inline void ag71xx_debugfs_exit(struct ag71xx *ag) {} -+static inline void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, -+ u32 status) {} -+static inline void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, -+ int rx, int tx) {} -+#endif /* CONFIG_AG71XX_DEBUG_FS */ -+ -+#endif /* _AG71XX_H */ -diff -Nur linux-2.6.36.orig/drivers/net/ag71xx/ag71xx_ar8216.c linux-2.6.36/drivers/net/ag71xx/ag71xx_ar8216.c ---- linux-2.6.36.orig/drivers/net/ag71xx/ag71xx_ar8216.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/drivers/net/ag71xx/ag71xx_ar8216.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,44 @@ -+/* -+ * Atheros AR71xx built-in ethernet mac driver -+ * Special support for the Atheros ar8216 switch chip -+ * -+ * Copyright (C) 2009-2010 Gabor Juhos -+ * -+ * Based on Atheros' AG7100 driver -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include "ag71xx.h" -+ -+#define AR8216_PACKET_TYPE_MASK 0xf -+#define AR8216_PACKET_TYPE_NORMAL 0 -+ -+#define AR8216_HEADER_LEN 2 -+ -+void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb) -+{ -+ skb_push(skb, AR8216_HEADER_LEN); -+ skb->data[0] = 0x10; -+ skb->data[1] = 0x80; -+} -+ -+int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb, -+ int pktlen) -+{ -+ u8 type; -+ -+ type = skb->data[1] & AR8216_PACKET_TYPE_MASK; -+ switch (type) { -+ case AR8216_PACKET_TYPE_NORMAL: -+ break; -+ -+ default: -+ return -EINVAL; -+ } -+ -+ skb_pull(skb, AR8216_HEADER_LEN); -+ return 0; -+} -diff -Nur linux-2.6.36.orig/drivers/net/ag71xx/ag71xx_debugfs.c linux-2.6.36/drivers/net/ag71xx/ag71xx_debugfs.c ---- linux-2.6.36.orig/drivers/net/ag71xx/ag71xx_debugfs.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/drivers/net/ag71xx/ag71xx_debugfs.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,197 @@ -+/* -+ * Atheros AR71xx built-in ethernet mac driver -+ * -+ * Copyright (C) 2008-2010 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Based on Atheros' AG7100 driver -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+ -+#include "ag71xx.h" -+ -+static struct dentry *ag71xx_debugfs_root; -+ -+static int ag71xx_debugfs_generic_open(struct inode *inode, struct file *file) -+{ -+ file->private_data = inode->i_private; -+ return 0; -+} -+ -+void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, u32 status) -+{ -+ if (status) -+ ag->debug.int_stats.total++; -+ if (status & AG71XX_INT_TX_PS) -+ ag->debug.int_stats.tx_ps++; -+ if (status & AG71XX_INT_TX_UR) -+ ag->debug.int_stats.tx_ur++; -+ if (status & AG71XX_INT_TX_BE) -+ ag->debug.int_stats.tx_be++; -+ if (status & AG71XX_INT_RX_PR) -+ ag->debug.int_stats.rx_pr++; -+ if (status & AG71XX_INT_RX_OF) -+ ag->debug.int_stats.rx_of++; -+ if (status & AG71XX_INT_RX_BE) -+ ag->debug.int_stats.rx_be++; -+} -+ -+static ssize_t read_file_int_stats(struct file *file, char __user *user_buf, -+ size_t count, loff_t *ppos) -+{ -+#define PR_INT_STAT(_label, _field) \ -+ len += snprintf(buf + len, sizeof(buf) - len, \ -+ "%20s: %10lu\n", _label, ag->debug.int_stats._field); -+ -+ struct ag71xx *ag = file->private_data; -+ char buf[256]; -+ unsigned int len = 0; -+ -+ PR_INT_STAT("TX Packet Sent", tx_ps); -+ PR_INT_STAT("TX Underrun", tx_ur); -+ PR_INT_STAT("TX Bus Error", tx_be); -+ PR_INT_STAT("RX Packet Received", rx_pr); -+ PR_INT_STAT("RX Overflow", rx_of); -+ PR_INT_STAT("RX Bus Error", rx_be); -+ len += snprintf(buf + len, sizeof(buf) - len, "\n"); -+ PR_INT_STAT("Total", total); -+ -+ return simple_read_from_buffer(user_buf, count, ppos, buf, len); -+#undef PR_INT_STAT -+} -+ -+static const struct file_operations ag71xx_fops_int_stats = { -+ .open = ag71xx_debugfs_generic_open, -+ .read = read_file_int_stats, -+ .owner = THIS_MODULE -+}; -+ -+void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, int rx, int tx) -+{ -+ struct ag71xx_napi_stats *stats = &ag->debug.napi_stats; -+ -+ if (rx) { -+ stats->rx_count++; -+ stats->rx_packets += rx; -+ if (rx <= AG71XX_NAPI_WEIGHT) -+ stats->rx[rx]++; -+ if (rx > stats->rx_packets_max) -+ stats->rx_packets_max = rx; -+ } -+ -+ if (tx) { -+ stats->tx_count++; -+ stats->tx_packets += tx; -+ if (tx <= AG71XX_NAPI_WEIGHT) -+ stats->tx[tx]++; -+ if (tx > stats->tx_packets_max) -+ stats->tx_packets_max = tx; -+ } -+} -+ -+static ssize_t read_file_napi_stats(struct file *file, char __user *user_buf, -+ size_t count, loff_t *ppos) -+{ -+ struct ag71xx *ag = file->private_data; -+ struct ag71xx_napi_stats *stats = &ag->debug.napi_stats; -+ char buf[2048]; -+ unsigned int len = 0; -+ unsigned long rx_avg = 0; -+ unsigned long tx_avg = 0; -+ int i; -+ -+ if (stats->rx_count) -+ rx_avg = stats->rx_packets / stats->rx_count; -+ -+ if (stats->tx_count) -+ tx_avg = stats->tx_packets / stats->tx_count; -+ -+ len += snprintf(buf + len, sizeof(buf) - len, "%3s %10s %10s\n", -+ "len", "rx", "tx"); -+ -+ for (i = 1; i <= AG71XX_NAPI_WEIGHT; i++) -+ len += snprintf(buf + len, sizeof(buf) - len, -+ "%3d: %10lu %10lu\n", -+ i, stats->rx[i], stats->tx[i]); -+ -+ len += snprintf(buf + len, sizeof(buf) - len, "\n"); -+ -+ len += snprintf(buf + len, sizeof(buf) - len, "%3s: %10lu %10lu\n", -+ "sum", stats->rx_count, stats->tx_count); -+ len += snprintf(buf + len, sizeof(buf) - len, "%3s: %10lu %10lu\n", -+ "avg", rx_avg, tx_avg); -+ len += snprintf(buf + len, sizeof(buf) - len, "%3s: %10lu %10lu\n", -+ "max", stats->rx_packets_max, stats->tx_packets_max); -+ len += snprintf(buf + len, sizeof(buf) - len, "%3s: %10lu %10lu\n", -+ "pkt", stats->rx_packets, stats->tx_packets); -+ -+ return simple_read_from_buffer(user_buf, count, ppos, buf, len); -+} -+ -+static const struct file_operations ag71xx_fops_napi_stats = { -+ .open = ag71xx_debugfs_generic_open, -+ .read = read_file_napi_stats, -+ .owner = THIS_MODULE -+}; -+ -+void ag71xx_debugfs_exit(struct ag71xx *ag) -+{ -+ debugfs_remove(ag->debug.debugfs_napi_stats); -+ debugfs_remove(ag->debug.debugfs_int_stats); -+ debugfs_remove(ag->debug.debugfs_dir); -+} -+ -+int ag71xx_debugfs_init(struct ag71xx *ag) -+{ -+ ag->debug.debugfs_dir = debugfs_create_dir(ag->dev->name, -+ ag71xx_debugfs_root); -+ if (!ag->debug.debugfs_dir) -+ goto err; -+ -+ ag->debug.debugfs_int_stats = -+ debugfs_create_file("int_stats", -+ S_IRUGO, -+ ag->debug.debugfs_dir, -+ ag, -+ &ag71xx_fops_int_stats); -+ if (!ag->debug.debugfs_int_stats) -+ goto err; -+ -+ ag->debug.debugfs_napi_stats = -+ debugfs_create_file("napi_stats", -+ S_IRUGO, -+ ag->debug.debugfs_dir, -+ ag, -+ &ag71xx_fops_napi_stats); -+ if (!ag->debug.debugfs_napi_stats) -+ goto err; -+ -+ return 0; -+ -+ err: -+ ag71xx_debugfs_exit(ag); -+ return -ENOMEM; -+} -+ -+int ag71xx_debugfs_root_init(void) -+{ -+ if (ag71xx_debugfs_root) -+ return -EBUSY; -+ -+ ag71xx_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL); -+ if (!ag71xx_debugfs_root) -+ return -ENOENT; -+ -+ return 0; -+} -+ -+void ag71xx_debugfs_root_exit(void) -+{ -+ debugfs_remove(ag71xx_debugfs_root); -+ ag71xx_debugfs_root = NULL; -+} -diff -Nur linux-2.6.36.orig/drivers/net/ag71xx/ag71xx_ethtool.c linux-2.6.36/drivers/net/ag71xx/ag71xx_ethtool.c ---- linux-2.6.36.orig/drivers/net/ag71xx/ag71xx_ethtool.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/drivers/net/ag71xx/ag71xx_ethtool.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,71 @@ -+/* -+ * Atheros AR71xx built-in ethernet mac driver -+ * -+ * Copyright (C) 2008-2010 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Based on Atheros' AG7100 driver -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include "ag71xx.h" -+ -+static int ag71xx_ethtool_get_settings(struct net_device *dev, -+ struct ethtool_cmd *cmd) -+{ -+ struct ag71xx *ag = netdev_priv(dev); -+ struct phy_device *phydev = ag->phy_dev; -+ -+ if (!phydev) -+ return -ENODEV; -+ -+ return phy_ethtool_gset(phydev, cmd); -+} -+ -+static int ag71xx_ethtool_set_settings(struct net_device *dev, -+ struct ethtool_cmd *cmd) -+{ -+ struct ag71xx *ag = netdev_priv(dev); -+ struct phy_device *phydev = ag->phy_dev; -+ -+ if (!phydev) -+ return -ENODEV; -+ -+ return phy_ethtool_sset(phydev, cmd); -+} -+ -+static void ag71xx_ethtool_get_drvinfo(struct net_device *dev, -+ struct ethtool_drvinfo *info) -+{ -+ struct ag71xx *ag = netdev_priv(dev); -+ -+ strcpy(info->driver, ag->pdev->dev.driver->name); -+ strcpy(info->version, AG71XX_DRV_VERSION); -+ strcpy(info->bus_info, dev_name(&ag->pdev->dev)); -+} -+ -+static u32 ag71xx_ethtool_get_msglevel(struct net_device *dev) -+{ -+ struct ag71xx *ag = netdev_priv(dev); -+ -+ return ag->msg_enable; -+} -+ -+static void ag71xx_ethtool_set_msglevel(struct net_device *dev, u32 msg_level) -+{ -+ struct ag71xx *ag = netdev_priv(dev); -+ -+ ag->msg_enable = msg_level; -+} -+ -+struct ethtool_ops ag71xx_ethtool_ops = { -+ .set_settings = ag71xx_ethtool_set_settings, -+ .get_settings = ag71xx_ethtool_get_settings, -+ .get_drvinfo = ag71xx_ethtool_get_drvinfo, -+ .get_msglevel = ag71xx_ethtool_get_msglevel, -+ .set_msglevel = ag71xx_ethtool_set_msglevel, -+ .get_link = ethtool_op_get_link, -+}; -diff -Nur linux-2.6.36.orig/drivers/net/ag71xx/ag71xx_main.c linux-2.6.36/drivers/net/ag71xx/ag71xx_main.c ---- linux-2.6.36.orig/drivers/net/ag71xx/ag71xx_main.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/drivers/net/ag71xx/ag71xx_main.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,1184 @@ -+/* -+ * Atheros AR71xx built-in ethernet mac driver -+ * -+ * Copyright (C) 2008-2010 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Based on Atheros' AG7100 driver -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include "ag71xx.h" -+ -+#define AG71XX_DEFAULT_MSG_ENABLE \ -+ ( NETIF_MSG_DRV \ -+ | NETIF_MSG_PROBE \ -+ | NETIF_MSG_LINK \ -+ | NETIF_MSG_TIMER \ -+ | NETIF_MSG_IFDOWN \ -+ | NETIF_MSG_IFUP \ -+ | NETIF_MSG_RX_ERR \ -+ | NETIF_MSG_TX_ERR ) -+ -+static int ag71xx_msg_level = -1; -+ -+module_param_named(msg_level, ag71xx_msg_level, int, 0); -+MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); -+ -+static void ag71xx_dump_dma_regs(struct ag71xx *ag) -+{ -+ DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n", -+ ag->dev->name, -+ ag71xx_rr(ag, AG71XX_REG_TX_CTRL), -+ ag71xx_rr(ag, AG71XX_REG_TX_DESC), -+ ag71xx_rr(ag, AG71XX_REG_TX_STATUS)); -+ -+ DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n", -+ ag->dev->name, -+ ag71xx_rr(ag, AG71XX_REG_RX_CTRL), -+ ag71xx_rr(ag, AG71XX_REG_RX_DESC), -+ ag71xx_rr(ag, AG71XX_REG_RX_STATUS)); -+} -+ -+static void ag71xx_dump_regs(struct ag71xx *ag) -+{ -+ DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n", -+ ag->dev->name, -+ ag71xx_rr(ag, AG71XX_REG_MAC_CFG1), -+ ag71xx_rr(ag, AG71XX_REG_MAC_CFG2), -+ ag71xx_rr(ag, AG71XX_REG_MAC_IPG), -+ ag71xx_rr(ag, AG71XX_REG_MAC_HDX), -+ ag71xx_rr(ag, AG71XX_REG_MAC_MFL)); -+ DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n", -+ ag->dev->name, -+ ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL), -+ ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1), -+ ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2)); -+ DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n", -+ ag->dev->name, -+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0), -+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1), -+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2)); -+ DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n", -+ ag->dev->name, -+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3), -+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4), -+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5)); -+} -+ -+static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr) -+{ -+ DBG("%s: %s intr=%08x %s%s%s%s%s%s\n", -+ ag->dev->name, label, intr, -+ (intr & AG71XX_INT_TX_PS) ? "TXPS " : "", -+ (intr & AG71XX_INT_TX_UR) ? "TXUR " : "", -+ (intr & AG71XX_INT_TX_BE) ? "TXBE " : "", -+ (intr & AG71XX_INT_RX_PR) ? "RXPR " : "", -+ (intr & AG71XX_INT_RX_OF) ? "RXOF " : "", -+ (intr & AG71XX_INT_RX_BE) ? "RXBE " : ""); -+} -+ -+static void ag71xx_ring_free(struct ag71xx_ring *ring) -+{ -+ kfree(ring->buf); -+ -+ if (ring->descs_cpu) -+ dma_free_coherent(NULL, ring->size * ring->desc_size, -+ ring->descs_cpu, ring->descs_dma); -+} -+ -+static int ag71xx_ring_alloc(struct ag71xx_ring *ring, unsigned int size) -+{ -+ int err; -+ int i; -+ -+ ring->desc_size = sizeof(struct ag71xx_desc); -+ if (ring->desc_size % cache_line_size()) { -+ DBG("ag71xx: ring %p, desc size %u rounded to %u\n", -+ ring, ring->desc_size, -+ roundup(ring->desc_size, cache_line_size())); -+ ring->desc_size = roundup(ring->desc_size, cache_line_size()); -+ } -+ -+ ring->descs_cpu = dma_alloc_coherent(NULL, size * ring->desc_size, -+ &ring->descs_dma, GFP_ATOMIC); -+ if (!ring->descs_cpu) { -+ err = -ENOMEM; -+ goto err; -+ } -+ -+ ring->size = size; -+ -+ ring->buf = kzalloc(size * sizeof(*ring->buf), GFP_KERNEL); -+ if (!ring->buf) { -+ err = -ENOMEM; -+ goto err; -+ } -+ -+ for (i = 0; i < size; i++) { -+ ring->buf[i].desc = (struct ag71xx_desc *)&ring->descs_cpu[i * ring->desc_size]; -+ DBG("ag71xx: ring %p, desc %d at %p\n", -+ ring, i, ring->buf[i].desc); -+ } -+ -+ return 0; -+ -+ err: -+ return err; -+} -+ -+static void ag71xx_ring_tx_clean(struct ag71xx *ag) -+{ -+ struct ag71xx_ring *ring = &ag->tx_ring; -+ struct net_device *dev = ag->dev; -+ -+ while (ring->curr != ring->dirty) { -+ u32 i = ring->dirty % AG71XX_TX_RING_SIZE; -+ -+ if (!ag71xx_desc_empty(ring->buf[i].desc)) { -+ ring->buf[i].desc->ctrl = 0; -+ dev->stats.tx_errors++; -+ } -+ -+ if (ring->buf[i].skb) -+ dev_kfree_skb_any(ring->buf[i].skb); -+ -+ ring->buf[i].skb = NULL; -+ -+ ring->dirty++; -+ } -+ -+ /* flush descriptors */ -+ wmb(); -+ -+} -+ -+static void ag71xx_ring_tx_init(struct ag71xx *ag) -+{ -+ struct ag71xx_ring *ring = &ag->tx_ring; -+ int i; -+ -+ for (i = 0; i < AG71XX_TX_RING_SIZE; i++) { -+ ring->buf[i].desc->next = (u32) (ring->descs_dma + -+ ring->desc_size * ((i + 1) % AG71XX_TX_RING_SIZE)); -+ -+ ring->buf[i].desc->ctrl = DESC_EMPTY; -+ ring->buf[i].skb = NULL; -+ } -+ -+ /* flush descriptors */ -+ wmb(); -+ -+ ring->curr = 0; -+ ring->dirty = 0; -+} -+ -+static void ag71xx_ring_rx_clean(struct ag71xx *ag) -+{ -+ struct ag71xx_ring *ring = &ag->rx_ring; -+ int i; -+ -+ if (!ring->buf) -+ return; -+ -+ for (i = 0; i < AG71XX_RX_RING_SIZE; i++) -+ if (ring->buf[i].skb) { -+ dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr, -+ AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE); -+ kfree_skb(ring->buf[i].skb); -+ } -+} -+ -+static int ag71xx_rx_reserve(struct ag71xx *ag) -+{ -+ int reserve = 0; -+ -+ if (ag71xx_get_pdata(ag)->is_ar724x) { -+ if (!ag71xx_has_ar8216(ag)) -+ reserve = 2; -+ -+ if (ag->phy_dev) -+ reserve += 4 - (ag->phy_dev->pkt_align % 4); -+ -+ reserve %= 4; -+ } -+ -+ return reserve + AG71XX_RX_PKT_RESERVE; -+} -+ -+ -+static int ag71xx_ring_rx_init(struct ag71xx *ag) -+{ -+ struct ag71xx_ring *ring = &ag->rx_ring; -+ unsigned int reserve = ag71xx_rx_reserve(ag); -+ unsigned int i; -+ int ret; -+ -+ ret = 0; -+ for (i = 0; i < AG71XX_RX_RING_SIZE; i++) { -+ ring->buf[i].desc->next = (u32) (ring->descs_dma + -+ ring->desc_size * ((i + 1) % AG71XX_RX_RING_SIZE)); -+ -+ DBG("ag71xx: RX desc at %p, next is %08x\n", -+ ring->buf[i].desc, -+ ring->buf[i].desc->next); -+ } -+ -+ for (i = 0; i < AG71XX_RX_RING_SIZE; i++) { -+ struct sk_buff *skb; -+ dma_addr_t dma_addr; -+ -+ skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + reserve); -+ if (!skb) { -+ ret = -ENOMEM; -+ break; -+ } -+ -+ skb->dev = ag->dev; -+ skb_reserve(skb, reserve); -+ -+ dma_addr = dma_map_single(&ag->dev->dev, skb->data, -+ AG71XX_RX_PKT_SIZE, -+ DMA_FROM_DEVICE); -+ ring->buf[i].skb = skb; -+ ring->buf[i].dma_addr = dma_addr; -+ ring->buf[i].desc->data = (u32) dma_addr; -+ ring->buf[i].desc->ctrl = DESC_EMPTY; -+ } -+ -+ /* flush descriptors */ -+ wmb(); -+ -+ ring->curr = 0; -+ ring->dirty = 0; -+ -+ return ret; -+} -+ -+static int ag71xx_ring_rx_refill(struct ag71xx *ag) -+{ -+ struct ag71xx_ring *ring = &ag->rx_ring; -+ unsigned int reserve = ag71xx_rx_reserve(ag); -+ unsigned int count; -+ -+ count = 0; -+ for (; ring->curr - ring->dirty > 0; ring->dirty++) { -+ unsigned int i; -+ -+ i = ring->dirty % AG71XX_RX_RING_SIZE; -+ -+ if (ring->buf[i].skb == NULL) { -+ dma_addr_t dma_addr; -+ struct sk_buff *skb; -+ -+ skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + reserve); -+ if (skb == NULL) -+ break; -+ -+ skb_reserve(skb, reserve); -+ skb->dev = ag->dev; -+ -+ dma_addr = dma_map_single(&ag->dev->dev, skb->data, -+ AG71XX_RX_PKT_SIZE, -+ DMA_FROM_DEVICE); -+ -+ ring->buf[i].skb = skb; -+ ring->buf[i].dma_addr = dma_addr; -+ ring->buf[i].desc->data = (u32) dma_addr; -+ } -+ -+ ring->buf[i].desc->ctrl = DESC_EMPTY; -+ count++; -+ } -+ -+ /* flush descriptors */ -+ wmb(); -+ -+ DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count); -+ -+ return count; -+} -+ -+static int ag71xx_rings_init(struct ag71xx *ag) -+{ -+ int ret; -+ -+ ret = ag71xx_ring_alloc(&ag->tx_ring, AG71XX_TX_RING_SIZE); -+ if (ret) -+ return ret; -+ -+ ag71xx_ring_tx_init(ag); -+ -+ ret = ag71xx_ring_alloc(&ag->rx_ring, AG71XX_RX_RING_SIZE); -+ if (ret) -+ return ret; -+ -+ ret = ag71xx_ring_rx_init(ag); -+ return ret; -+} -+ -+static void ag71xx_rings_cleanup(struct ag71xx *ag) -+{ -+ ag71xx_ring_rx_clean(ag); -+ ag71xx_ring_free(&ag->rx_ring); -+ -+ ag71xx_ring_tx_clean(ag); -+ ag71xx_ring_free(&ag->tx_ring); -+} -+ -+static unsigned char *ag71xx_speed_str(struct ag71xx *ag) -+{ -+ switch (ag->speed) { -+ case SPEED_1000: -+ return "1000"; -+ case SPEED_100: -+ return "100"; -+ case SPEED_10: -+ return "10"; -+ } -+ -+ return "?"; -+} -+ -+void ag71xx_link_adjust(struct ag71xx *ag) -+{ -+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); -+ u32 cfg2; -+ u32 ifctl; -+ u32 fifo5; -+ u32 mii_speed; -+ -+ if (!ag->link) { -+ netif_carrier_off(ag->dev); -+ if (netif_msg_link(ag)) -+ printk(KERN_INFO "%s: link down\n", ag->dev->name); -+ return; -+ } -+ -+ cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2); -+ cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX); -+ cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0; -+ -+ ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL); -+ ifctl &= ~(MAC_IFCTL_SPEED); -+ -+ fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5); -+ fifo5 &= ~FIFO_CFG5_BM; -+ -+ switch (ag->speed) { -+ case SPEED_1000: -+ mii_speed = MII_CTRL_SPEED_1000; -+ cfg2 |= MAC_CFG2_IF_1000; -+ fifo5 |= FIFO_CFG5_BM; -+ break; -+ case SPEED_100: -+ mii_speed = MII_CTRL_SPEED_100; -+ cfg2 |= MAC_CFG2_IF_10_100; -+ ifctl |= MAC_IFCTL_SPEED; -+ break; -+ case SPEED_10: -+ mii_speed = MII_CTRL_SPEED_10; -+ cfg2 |= MAC_CFG2_IF_10_100; -+ break; -+ default: -+ BUG(); -+ return; -+ } -+ -+ if (pdata->is_ar91xx) -+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x00780fff); -+ else if (pdata->is_ar724x) -+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, pdata->fifo_cfg3); -+ else -+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x008001ff); -+ -+ if (pdata->set_pll) -+ pdata->set_pll(ag->speed); -+ -+ ag71xx_mii_ctrl_set_speed(ag, mii_speed); -+ -+ ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2); -+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5); -+ ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl); -+ -+ netif_carrier_on(ag->dev); -+ if (netif_msg_link(ag)) -+ printk(KERN_INFO "%s: link up (%sMbps/%s duplex)\n", -+ ag->dev->name, -+ ag71xx_speed_str(ag), -+ (DUPLEX_FULL == ag->duplex) ? "Full" : "Half"); -+ -+ DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n", -+ ag->dev->name, -+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0), -+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1), -+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2)); -+ -+ DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n", -+ ag->dev->name, -+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3), -+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4), -+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5)); -+ -+ DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x, mii_ctrl=%#x\n", -+ ag->dev->name, -+ ag71xx_rr(ag, AG71XX_REG_MAC_CFG2), -+ ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL), -+ ag71xx_mii_ctrl_rr(ag)); -+} -+ -+static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac) -+{ -+ u32 t; -+ -+ t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16) -+ | (((u32) mac[3]) << 8) | ((u32) mac[2]); -+ -+ ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t); -+ -+ t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16); -+ ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t); -+} -+ -+static void ag71xx_dma_reset(struct ag71xx *ag) -+{ -+ u32 val; -+ int i; -+ -+ ag71xx_dump_dma_regs(ag); -+ -+ /* stop RX and TX */ -+ ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0); -+ ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0); -+ -+ /* clear descriptor addresses */ -+ ag71xx_wr(ag, AG71XX_REG_TX_DESC, 0); -+ ag71xx_wr(ag, AG71XX_REG_RX_DESC, 0); -+ -+ /* clear pending RX/TX interrupts */ -+ for (i = 0; i < 256; i++) { -+ ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR); -+ ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS); -+ } -+ -+ /* clear pending errors */ -+ ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF); -+ ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR); -+ -+ val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS); -+ if (val) -+ printk(KERN_ALERT "%s: unable to clear DMA Rx status: %08x\n", -+ ag->dev->name, val); -+ -+ val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS); -+ -+ /* mask out reserved bits */ -+ val &= ~0xff000000; -+ -+ if (val) -+ printk(KERN_ALERT "%s: unable to clear DMA Tx status: %08x\n", -+ ag->dev->name, val); -+ -+ ag71xx_dump_dma_regs(ag); -+} -+ -+#define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \ -+ MAC_CFG1_SRX | MAC_CFG1_STX) -+ -+#define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT) -+ -+#define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \ -+ FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \ -+ FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \ -+ FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \ -+ FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \ -+ FIFO_CFG4_VT) -+ -+#define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \ -+ FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \ -+ FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \ -+ FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \ -+ FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \ -+ FIFO_CFG5_17 | FIFO_CFG5_SF) -+ -+static void ag71xx_hw_init(struct ag71xx *ag) -+{ -+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); -+ -+ ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR); -+ udelay(20); -+ -+ ar71xx_device_stop(pdata->reset_bit); -+ mdelay(100); -+ ar71xx_device_start(pdata->reset_bit); -+ mdelay(100); -+ -+ /* setup MAC configuration registers */ -+ if (pdata->is_ar724x) -+ ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, -+ MAC_CFG1_INIT | MAC_CFG1_TFC | MAC_CFG1_RFC); -+ else -+ ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT); -+ -+ ag71xx_sb(ag, AG71XX_REG_MAC_CFG2, -+ MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK); -+ -+ /* setup max frame length */ -+ ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN); -+ -+ /* setup MII interface type */ -+ ag71xx_mii_ctrl_set_if(ag, pdata->mii_if); -+ -+ /* setup FIFO configuration registers */ -+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT); -+ if (pdata->is_ar724x) { -+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1); -+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2); -+ } else { -+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000); -+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff); -+ } -+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT); -+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT); -+ -+ ag71xx_dma_reset(ag); -+} -+ -+static void ag71xx_hw_start(struct ag71xx *ag) -+{ -+ /* start RX engine */ -+ ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE); -+ -+ /* enable interrupts */ -+ ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT); -+} -+ -+static void ag71xx_hw_stop(struct ag71xx *ag) -+{ -+ /* disable all interrupts */ -+ ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0); -+ -+ ag71xx_dma_reset(ag); -+} -+ -+static int ag71xx_open(struct net_device *dev) -+{ -+ struct ag71xx *ag = netdev_priv(dev); -+ int ret; -+ -+ ret = ag71xx_rings_init(ag); -+ if (ret) -+ goto err; -+ -+ napi_enable(&ag->napi); -+ -+ netif_carrier_off(dev); -+ ag71xx_phy_start(ag); -+ -+ ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma); -+ ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma); -+ -+ ag71xx_hw_set_macaddr(ag, dev->dev_addr); -+ -+ ag71xx_hw_start(ag); -+ -+ netif_start_queue(dev); -+ -+ return 0; -+ -+ err: -+ ag71xx_rings_cleanup(ag); -+ return ret; -+} -+ -+static int ag71xx_stop(struct net_device *dev) -+{ -+ struct ag71xx *ag = netdev_priv(dev); -+ unsigned long flags; -+ -+ netif_carrier_off(dev); -+ ag71xx_phy_stop(ag); -+ -+ spin_lock_irqsave(&ag->lock, flags); -+ -+ netif_stop_queue(dev); -+ -+ ag71xx_hw_stop(ag); -+ -+ napi_disable(&ag->napi); -+ del_timer_sync(&ag->oom_timer); -+ -+ spin_unlock_irqrestore(&ag->lock, flags); -+ -+ ag71xx_rings_cleanup(ag); -+ -+ return 0; -+} -+ -+static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb, -+ struct net_device *dev) -+{ -+ struct ag71xx *ag = netdev_priv(dev); -+ struct ag71xx_ring *ring = &ag->tx_ring; -+ struct ag71xx_desc *desc; -+ dma_addr_t dma_addr; -+ int i; -+ -+ i = ring->curr % AG71XX_TX_RING_SIZE; -+ desc = ring->buf[i].desc; -+ -+ if (!ag71xx_desc_empty(desc)) -+ goto err_drop; -+ -+ if (ag71xx_has_ar8216(ag)) -+ ag71xx_add_ar8216_header(ag, skb); -+ -+ if (skb->len <= 0) { -+ DBG("%s: packet len is too small\n", ag->dev->name); -+ goto err_drop; -+ } -+ -+ dma_addr = dma_map_single(&dev->dev, skb->data, skb->len, -+ DMA_TO_DEVICE); -+ -+ ring->buf[i].skb = skb; -+ -+ /* setup descriptor fields */ -+ desc->data = (u32) dma_addr; -+ desc->ctrl = (skb->len & DESC_PKTLEN_M); -+ -+ /* flush descriptor */ -+ wmb(); -+ -+ ring->curr++; -+ if (ring->curr == (ring->dirty + AG71XX_TX_THRES_STOP)) { -+ DBG("%s: tx queue full\n", ag->dev->name); -+ netif_stop_queue(dev); -+ } -+ -+ DBG("%s: packet injected into TX queue\n", ag->dev->name); -+ -+ /* enable TX engine */ -+ ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE); -+ -+ return NETDEV_TX_OK; -+ -+ err_drop: -+ dev->stats.tx_dropped++; -+ -+ dev_kfree_skb(skb); -+ return NETDEV_TX_OK; -+} -+ -+static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) -+{ -+ struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_data; -+ struct ag71xx *ag = netdev_priv(dev); -+ int ret; -+ -+ switch (cmd) { -+ case SIOCETHTOOL: -+ if (ag->phy_dev == NULL) -+ break; -+ -+ spin_lock_irq(&ag->lock); -+ ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data); -+ spin_unlock_irq(&ag->lock); -+ return ret; -+ -+ case SIOCSIFHWADDR: -+ if (copy_from_user -+ (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr))) -+ return -EFAULT; -+ return 0; -+ -+ case SIOCGIFHWADDR: -+ if (copy_to_user -+ (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr))) -+ return -EFAULT; -+ return 0; -+ -+ case SIOCGMIIPHY: -+ case SIOCGMIIREG: -+ case SIOCSMIIREG: -+ if (ag->phy_dev == NULL) -+ break; -+ -+ return phy_mii_ioctl(ag->phy_dev, data, cmd); -+ -+ default: -+ break; -+ } -+ -+ return -EOPNOTSUPP; -+} -+ -+static void ag71xx_oom_timer_handler(unsigned long data) -+{ -+ struct net_device *dev = (struct net_device *) data; -+ struct ag71xx *ag = netdev_priv(dev); -+ -+ napi_schedule(&ag->napi); -+} -+ -+static void ag71xx_tx_timeout(struct net_device *dev) -+{ -+ struct ag71xx *ag = netdev_priv(dev); -+ -+ if (netif_msg_tx_err(ag)) -+ printk(KERN_DEBUG "%s: tx timeout\n", ag->dev->name); -+ -+ schedule_work(&ag->restart_work); -+} -+ -+static void ag71xx_restart_work_func(struct work_struct *work) -+{ -+ struct ag71xx *ag = container_of(work, struct ag71xx, restart_work); -+ -+ ag71xx_stop(ag->dev); -+ ag71xx_open(ag->dev); -+} -+ -+static int ag71xx_tx_packets(struct ag71xx *ag) -+{ -+ struct ag71xx_ring *ring = &ag->tx_ring; -+ int sent; -+ -+ DBG("%s: processing TX ring\n", ag->dev->name); -+ -+ sent = 0; -+ while (ring->dirty != ring->curr) { -+ unsigned int i = ring->dirty % AG71XX_TX_RING_SIZE; -+ struct ag71xx_desc *desc = ring->buf[i].desc; -+ struct sk_buff *skb = ring->buf[i].skb; -+ -+ if (!ag71xx_desc_empty(desc)) -+ break; -+ -+ ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS); -+ -+ ag->dev->stats.tx_bytes += skb->len; -+ ag->dev->stats.tx_packets++; -+ -+ dev_kfree_skb_any(skb); -+ ring->buf[i].skb = NULL; -+ -+ ring->dirty++; -+ sent++; -+ } -+ -+ DBG("%s: %d packets sent out\n", ag->dev->name, sent); -+ -+ if ((ring->curr - ring->dirty) < AG71XX_TX_THRES_WAKEUP) -+ netif_wake_queue(ag->dev); -+ -+ return sent; -+} -+ -+static int ag71xx_rx_packets(struct ag71xx *ag, int limit) -+{ -+ struct net_device *dev = ag->dev; -+ struct ag71xx_ring *ring = &ag->rx_ring; -+ int done = 0; -+ -+ DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n", -+ dev->name, limit, ring->curr, ring->dirty); -+ -+ while (done < limit) { -+ unsigned int i = ring->curr % AG71XX_RX_RING_SIZE; -+ struct ag71xx_desc *desc = ring->buf[i].desc; -+ struct sk_buff *skb; -+ int pktlen; -+ int err = 0; -+ -+ if (ag71xx_desc_empty(desc)) -+ break; -+ -+ if ((ring->dirty + AG71XX_RX_RING_SIZE) == ring->curr) { -+ ag71xx_assert(0); -+ break; -+ } -+ -+ ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR); -+ -+ skb = ring->buf[i].skb; -+ pktlen = ag71xx_desc_pktlen(desc); -+ pktlen -= ETH_FCS_LEN; -+ -+ dma_unmap_single(&dev->dev, ring->buf[i].dma_addr, -+ AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE); -+ -+ dev->last_rx = jiffies; -+ dev->stats.rx_packets++; -+ dev->stats.rx_bytes += pktlen; -+ -+ skb_put(skb, pktlen); -+ if (ag71xx_has_ar8216(ag)) -+ err = ag71xx_remove_ar8216_header(ag, skb, pktlen); -+ -+ if (err) { -+ dev->stats.rx_dropped++; -+ kfree_skb(skb); -+ } else { -+ skb->dev = dev; -+ skb->ip_summed = CHECKSUM_NONE; -+ if (ag->phy_dev) { -+ ag->phy_dev->netif_receive_skb(skb); -+ } else { -+ skb->protocol = eth_type_trans(skb, dev); -+ netif_receive_skb(skb); -+ } -+ } -+ -+ ring->buf[i].skb = NULL; -+ done++; -+ -+ ring->curr++; -+ } -+ -+ ag71xx_ring_rx_refill(ag); -+ -+ DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n", -+ dev->name, ring->curr, ring->dirty, done); -+ -+ return done; -+} -+ -+static int ag71xx_poll(struct napi_struct *napi, int limit) -+{ -+ struct ag71xx *ag = container_of(napi, struct ag71xx, napi); -+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); -+ struct net_device *dev = ag->dev; -+ struct ag71xx_ring *rx_ring; -+ unsigned long flags; -+ u32 status; -+ int tx_done; -+ int rx_done; -+ -+ pdata->ddr_flush(); -+ tx_done = ag71xx_tx_packets(ag); -+ -+ DBG("%s: processing RX ring\n", dev->name); -+ rx_done = ag71xx_rx_packets(ag, limit); -+ -+ ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done); -+ -+ rx_ring = &ag->rx_ring; -+ if (rx_ring->buf[rx_ring->dirty % AG71XX_RX_RING_SIZE].skb == NULL) -+ goto oom; -+ -+ status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS); -+ if (unlikely(status & RX_STATUS_OF)) { -+ ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF); -+ dev->stats.rx_fifo_errors++; -+ -+ /* restart RX */ -+ ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE); -+ } -+ -+ if (rx_done < limit) { -+ if (status & RX_STATUS_PR) -+ goto more; -+ -+ status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS); -+ if (status & TX_STATUS_PS) -+ goto more; -+ -+ DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n", -+ dev->name, rx_done, tx_done, limit); -+ -+ napi_complete(napi); -+ -+ /* enable interrupts */ -+ spin_lock_irqsave(&ag->lock, flags); -+ ag71xx_int_enable(ag, AG71XX_INT_POLL); -+ spin_unlock_irqrestore(&ag->lock, flags); -+ return rx_done; -+ } -+ -+ more: -+ DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n", -+ dev->name, rx_done, tx_done, limit); -+ return rx_done; -+ -+ oom: -+ if (netif_msg_rx_err(ag)) -+ printk(KERN_DEBUG "%s: out of memory\n", dev->name); -+ -+ mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL); -+ napi_complete(napi); -+ return 0; -+} -+ -+static irqreturn_t ag71xx_interrupt(int irq, void *dev_id) -+{ -+ struct net_device *dev = dev_id; -+ struct ag71xx *ag = netdev_priv(dev); -+ u32 status; -+ -+ status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS); -+ ag71xx_dump_intr(ag, "raw", status); -+ -+ if (unlikely(!status)) -+ return IRQ_NONE; -+ -+ if (unlikely(status & AG71XX_INT_ERR)) { -+ if (status & AG71XX_INT_TX_BE) { -+ ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE); -+ dev_err(&dev->dev, "TX BUS error\n"); -+ } -+ if (status & AG71XX_INT_RX_BE) { -+ ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE); -+ dev_err(&dev->dev, "RX BUS error\n"); -+ } -+ } -+ -+ if (likely(status & AG71XX_INT_POLL)) { -+ ag71xx_int_disable(ag, AG71XX_INT_POLL); -+ DBG("%s: enable polling mode\n", dev->name); -+ napi_schedule(&ag->napi); -+ } -+ -+ ag71xx_debugfs_update_int_stats(ag, status); -+ -+ return IRQ_HANDLED; -+} -+ -+static void ag71xx_set_multicast_list(struct net_device *dev) -+{ -+ /* TODO */ -+} -+ -+#ifdef CONFIG_NET_POLL_CONTROLLER -+/* -+ * Polling 'interrupt' - used by things like netconsole to send skbs -+ * without having to re-enable interrupts. It's not called while -+ * the interrupt routine is executing. -+ */ -+static void ag71xx_netpoll(struct net_device *dev) -+{ -+ disable_irq(dev->irq); -+ ag71xx_interrupt(dev->irq, dev); -+ enable_irq(dev->irq); -+} -+#endif -+ -+static const struct net_device_ops ag71xx_netdev_ops = { -+ .ndo_open = ag71xx_open, -+ .ndo_stop = ag71xx_stop, -+ .ndo_start_xmit = ag71xx_hard_start_xmit, -+ .ndo_set_multicast_list = ag71xx_set_multicast_list, -+ .ndo_do_ioctl = ag71xx_do_ioctl, -+ .ndo_tx_timeout = ag71xx_tx_timeout, -+ .ndo_change_mtu = eth_change_mtu, -+ .ndo_set_mac_address = eth_mac_addr, -+ .ndo_validate_addr = eth_validate_addr, -+#ifdef CONFIG_NET_POLL_CONTROLLER -+ .ndo_poll_controller = ag71xx_netpoll, -+#endif -+}; -+ -+static int __init ag71xx_probe(struct platform_device *pdev) -+{ -+ struct net_device *dev; -+ struct resource *res; -+ struct ag71xx *ag; -+ struct ag71xx_platform_data *pdata; -+ int err; -+ -+ pdata = pdev->dev.platform_data; -+ if (!pdata) { -+ dev_err(&pdev->dev, "no platform data specified\n"); -+ err = -ENXIO; -+ goto err_out; -+ } -+ -+ if (pdata->mii_bus_dev == NULL) { -+ dev_err(&pdev->dev, "no MII bus device specified\n"); -+ err = -EINVAL; -+ goto err_out; -+ } -+ -+ dev = alloc_etherdev(sizeof(*ag)); -+ if (!dev) { -+ dev_err(&pdev->dev, "alloc_etherdev failed\n"); -+ err = -ENOMEM; -+ goto err_out; -+ } -+ -+ SET_NETDEV_DEV(dev, &pdev->dev); -+ -+ ag = netdev_priv(dev); -+ ag->pdev = pdev; -+ ag->dev = dev; -+ ag->msg_enable = netif_msg_init(ag71xx_msg_level, -+ AG71XX_DEFAULT_MSG_ENABLE); -+ spin_lock_init(&ag->lock); -+ -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base"); -+ if (!res) { -+ dev_err(&pdev->dev, "no mac_base resource found\n"); -+ err = -ENXIO; -+ goto err_out; -+ } -+ -+ ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1); -+ if (!ag->mac_base) { -+ dev_err(&pdev->dev, "unable to ioremap mac_base\n"); -+ err = -ENOMEM; -+ goto err_free_dev; -+ } -+ -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mii_ctrl"); -+ if (!res) { -+ dev_err(&pdev->dev, "no mii_ctrl resource found\n"); -+ err = -ENXIO; -+ goto err_unmap_base; -+ } -+ -+ ag->mii_ctrl = ioremap_nocache(res->start, res->end - res->start + 1); -+ if (!ag->mii_ctrl) { -+ dev_err(&pdev->dev, "unable to ioremap mii_ctrl\n"); -+ err = -ENOMEM; -+ goto err_unmap_base; -+ } -+ -+ dev->irq = platform_get_irq(pdev, 0); -+ err = request_irq(dev->irq, ag71xx_interrupt, -+ IRQF_DISABLED | IRQF_SAMPLE_RANDOM, -+ dev->name, dev); -+ if (err) { -+ dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq); -+ goto err_unmap_mii_ctrl; -+ } -+ -+ dev->base_addr = (unsigned long)ag->mac_base; -+ dev->netdev_ops = &ag71xx_netdev_ops; -+ dev->ethtool_ops = &ag71xx_ethtool_ops; -+ -+ INIT_WORK(&ag->restart_work, ag71xx_restart_work_func); -+ -+ init_timer(&ag->oom_timer); -+ ag->oom_timer.data = (unsigned long) dev; -+ ag->oom_timer.function = ag71xx_oom_timer_handler; -+ -+ memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN); -+ -+ netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT); -+ -+ err = register_netdev(dev); -+ if (err) { -+ dev_err(&pdev->dev, "unable to register net device\n"); -+ goto err_free_irq; -+ } -+ -+ printk(KERN_INFO "%s: Atheros AG71xx at 0x%08lx, irq %d\n", -+ dev->name, dev->base_addr, dev->irq); -+ -+ ag71xx_dump_regs(ag); -+ -+ ag71xx_hw_init(ag); -+ -+ ag71xx_dump_regs(ag); -+ -+ err = ag71xx_phy_connect(ag); -+ if (err) -+ goto err_unregister_netdev; -+ -+ err = ag71xx_debugfs_init(ag); -+ if (err) -+ goto err_phy_disconnect; -+ -+ platform_set_drvdata(pdev, dev); -+ -+ return 0; -+ -+ err_phy_disconnect: -+ ag71xx_phy_disconnect(ag); -+ err_unregister_netdev: -+ unregister_netdev(dev); -+ err_free_irq: -+ free_irq(dev->irq, dev); -+ err_unmap_mii_ctrl: -+ iounmap(ag->mii_ctrl); -+ err_unmap_base: -+ iounmap(ag->mac_base); -+ err_free_dev: -+ kfree(dev); -+ err_out: -+ platform_set_drvdata(pdev, NULL); -+ return err; -+} -+ -+static int __exit ag71xx_remove(struct platform_device *pdev) -+{ -+ struct net_device *dev = platform_get_drvdata(pdev); -+ -+ if (dev) { -+ struct ag71xx *ag = netdev_priv(dev); -+ -+ ag71xx_debugfs_exit(ag); -+ ag71xx_phy_disconnect(ag); -+ unregister_netdev(dev); -+ free_irq(dev->irq, dev); -+ iounmap(ag->mii_ctrl); -+ iounmap(ag->mac_base); -+ kfree(dev); -+ platform_set_drvdata(pdev, NULL); -+ } -+ -+ return 0; -+} -+ -+static struct platform_driver ag71xx_driver = { -+ .probe = ag71xx_probe, -+ .remove = __exit_p(ag71xx_remove), -+ .driver = { -+ .name = AG71XX_DRV_NAME, -+ } -+}; -+ -+static int __init ag71xx_module_init(void) -+{ -+ int ret; -+ -+ ret = ag71xx_debugfs_root_init(); -+ if (ret) -+ goto err_out; -+ -+ ret = ag71xx_mdio_driver_init(); -+ if (ret) -+ goto err_debugfs_exit; -+ -+ ret = platform_driver_register(&ag71xx_driver); -+ if (ret) -+ goto err_mdio_exit; -+ -+ return 0; -+ -+ err_mdio_exit: -+ ag71xx_mdio_driver_exit(); -+ err_debugfs_exit: -+ ag71xx_debugfs_root_exit(); -+ err_out: -+ return ret; -+} -+ -+static void __exit ag71xx_module_exit(void) -+{ -+ platform_driver_unregister(&ag71xx_driver); -+ ag71xx_mdio_driver_exit(); -+ ag71xx_debugfs_root_exit(); -+} -+ -+module_init(ag71xx_module_init); -+module_exit(ag71xx_module_exit); -+ -+MODULE_VERSION(AG71XX_DRV_VERSION); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_AUTHOR("Imre Kaloz "); -+MODULE_LICENSE("GPL v2"); -+MODULE_ALIAS("platform:" AG71XX_DRV_NAME); -diff -Nur linux-2.6.36.orig/drivers/net/ag71xx/ag71xx_mdio.c linux-2.6.36/drivers/net/ag71xx/ag71xx_mdio.c ---- linux-2.6.36.orig/drivers/net/ag71xx/ag71xx_mdio.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/drivers/net/ag71xx/ag71xx_mdio.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,243 @@ -+/* -+ * Atheros AR71xx built-in ethernet mac driver -+ * -+ * Copyright (C) 2008-2010 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Based on Atheros' AG7100 driver -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include "ag71xx.h" -+ -+#define AG71XX_MDIO_RETRY 1000 -+#define AG71XX_MDIO_DELAY 5 -+ -+static inline void ag71xx_mdio_wr(struct ag71xx_mdio *am, unsigned reg, -+ u32 value) -+{ -+ void __iomem *r; -+ -+ r = am->mdio_base + reg; -+ __raw_writel(value, r); -+ -+ /* flush write */ -+ (void) __raw_readl(r); -+} -+ -+static inline u32 ag71xx_mdio_rr(struct ag71xx_mdio *am, unsigned reg) -+{ -+ return __raw_readl(am->mdio_base + reg); -+} -+ -+static void ag71xx_mdio_dump_regs(struct ag71xx_mdio *am) -+{ -+ DBG("%s: mii_cfg=%08x, mii_cmd=%08x, mii_addr=%08x\n", -+ am->mii_bus->name, -+ ag71xx_mdio_rr(am, AG71XX_REG_MII_CFG), -+ ag71xx_mdio_rr(am, AG71XX_REG_MII_CMD), -+ ag71xx_mdio_rr(am, AG71XX_REG_MII_ADDR)); -+ DBG("%s: mii_ctrl=%08x, mii_status=%08x, mii_ind=%08x\n", -+ am->mii_bus->name, -+ ag71xx_mdio_rr(am, AG71XX_REG_MII_CTRL), -+ ag71xx_mdio_rr(am, AG71XX_REG_MII_STATUS), -+ ag71xx_mdio_rr(am, AG71XX_REG_MII_IND)); -+} -+ -+static int ag71xx_mdio_mii_read(struct ag71xx_mdio *am, int addr, int reg) -+{ -+ int ret; -+ int i; -+ -+ ag71xx_mdio_wr(am, AG71XX_REG_MII_CMD, MII_CMD_WRITE); -+ ag71xx_mdio_wr(am, AG71XX_REG_MII_ADDR, -+ ((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff)); -+ ag71xx_mdio_wr(am, AG71XX_REG_MII_CMD, MII_CMD_READ); -+ -+ i = AG71XX_MDIO_RETRY; -+ while (ag71xx_mdio_rr(am, AG71XX_REG_MII_IND) & MII_IND_BUSY) { -+ if (i-- == 0) { -+ printk(KERN_ERR "%s: mii_read timed out\n", -+ am->mii_bus->name); -+ ret = 0xffff; -+ goto out; -+ } -+ udelay(AG71XX_MDIO_DELAY); -+ } -+ -+ ret = ag71xx_mdio_rr(am, AG71XX_REG_MII_STATUS) & 0xffff; -+ ag71xx_mdio_wr(am, AG71XX_REG_MII_CMD, MII_CMD_WRITE); -+ -+ DBG("mii_read: addr=%04x, reg=%04x, value=%04x\n", addr, reg, ret); -+ -+ out: -+ return ret; -+} -+ -+static void ag71xx_mdio_mii_write(struct ag71xx_mdio *am, -+ int addr, int reg, u16 val) -+{ -+ int i; -+ -+ DBG("mii_write: addr=%04x, reg=%04x, value=%04x\n", addr, reg, val); -+ -+ ag71xx_mdio_wr(am, AG71XX_REG_MII_ADDR, -+ ((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff)); -+ ag71xx_mdio_wr(am, AG71XX_REG_MII_CTRL, val); -+ -+ i = AG71XX_MDIO_RETRY; -+ while (ag71xx_mdio_rr(am, AG71XX_REG_MII_IND) & MII_IND_BUSY) { -+ if (i-- == 0) { -+ printk(KERN_ERR "%s: mii_write timed out\n", -+ am->mii_bus->name); -+ break; -+ } -+ udelay(AG71XX_MDIO_DELAY); -+ } -+} -+ -+static int ag71xx_mdio_reset(struct mii_bus *bus) -+{ -+ struct ag71xx_mdio *am = bus->priv; -+ u32 t; -+ -+ if (am->pdata->is_ar7240) -+ t = MII_CFG_CLK_DIV_6; -+ else -+ t = MII_CFG_CLK_DIV_28; -+ -+ ag71xx_mdio_wr(am, AG71XX_REG_MII_CFG, t | MII_CFG_RESET); -+ udelay(100); -+ -+ ag71xx_mdio_wr(am, AG71XX_REG_MII_CFG, t); -+ udelay(100); -+ -+ return 0; -+} -+ -+static int ag71xx_mdio_read(struct mii_bus *bus, int addr, int reg) -+{ -+ struct ag71xx_mdio *am = bus->priv; -+ -+ return ag71xx_mdio_mii_read(am, addr, reg); -+} -+ -+static int ag71xx_mdio_write(struct mii_bus *bus, int addr, int reg, u16 val) -+{ -+ struct ag71xx_mdio *am = bus->priv; -+ -+ ag71xx_mdio_mii_write(am, addr, reg, val); -+ return 0; -+} -+ -+static int __init ag71xx_mdio_probe(struct platform_device *pdev) -+{ -+ struct ag71xx_mdio_platform_data *pdata; -+ struct ag71xx_mdio *am; -+ struct resource *res; -+ int i; -+ int err; -+ -+ pdata = pdev->dev.platform_data; -+ if (!pdata) { -+ dev_err(&pdev->dev, "no platform data specified\n"); -+ return -EINVAL; -+ } -+ -+ am = kzalloc(sizeof(*am), GFP_KERNEL); -+ if (!am) { -+ err = -ENOMEM; -+ goto err_out; -+ } -+ -+ am->pdata = pdata; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (!res) { -+ dev_err(&pdev->dev, "no iomem resource found\n"); -+ err = -ENXIO; -+ goto err_out; -+ } -+ -+ am->mdio_base = ioremap_nocache(res->start, res->end - res->start + 1); -+ if (!am->mdio_base) { -+ dev_err(&pdev->dev, "unable to ioremap registers\n"); -+ err = -ENOMEM; -+ goto err_free_mdio; -+ } -+ -+ am->mii_bus = mdiobus_alloc(); -+ if (am->mii_bus == NULL) { -+ err = -ENOMEM; -+ goto err_iounmap; -+ } -+ -+ am->mii_bus->name = "ag71xx_mdio"; -+ am->mii_bus->read = ag71xx_mdio_read; -+ am->mii_bus->write = ag71xx_mdio_write; -+ am->mii_bus->reset = ag71xx_mdio_reset; -+ am->mii_bus->irq = am->mii_irq; -+ am->mii_bus->priv = am; -+ am->mii_bus->parent = &pdev->dev; -+ snprintf(am->mii_bus->id, MII_BUS_ID_SIZE, "%s", dev_name(&pdev->dev)); -+ am->mii_bus->phy_mask = pdata->phy_mask; -+ -+ for (i = 0; i < PHY_MAX_ADDR; i++) -+ am->mii_irq[i] = PHY_POLL; -+ -+ ag71xx_mdio_wr(am, AG71XX_REG_MAC_CFG1, 0); -+ -+ err = mdiobus_register(am->mii_bus); -+ if (err) -+ goto err_free_bus; -+ -+ ag71xx_mdio_dump_regs(am); -+ -+ platform_set_drvdata(pdev, am); -+ return 0; -+ -+ err_free_bus: -+ mdiobus_free(am->mii_bus); -+ err_iounmap: -+ iounmap(am->mdio_base); -+ err_free_mdio: -+ kfree(am); -+ err_out: -+ return err; -+} -+ -+static int __exit ag71xx_mdio_remove(struct platform_device *pdev) -+{ -+ struct ag71xx_mdio *am = platform_get_drvdata(pdev); -+ -+ if (am) { -+ mdiobus_unregister(am->mii_bus); -+ mdiobus_free(am->mii_bus); -+ iounmap(am->mdio_base); -+ kfree(am); -+ platform_set_drvdata(pdev, NULL); -+ } -+ -+ return 0; -+} -+ -+static struct platform_driver ag71xx_mdio_driver = { -+ .probe = ag71xx_mdio_probe, -+ .remove = __exit_p(ag71xx_mdio_remove), -+ .driver = { -+ .name = "ag71xx-mdio", -+ } -+}; -+ -+int ag71xx_mdio_driver_init(void) -+{ -+ return platform_driver_register(&ag71xx_mdio_driver); -+} -+ -+void ag71xx_mdio_driver_exit(void) -+{ -+ platform_driver_unregister(&ag71xx_mdio_driver); -+} -diff -Nur linux-2.6.36.orig/drivers/net/ag71xx/ag71xx_phy.c linux-2.6.36/drivers/net/ag71xx/ag71xx_phy.c ---- linux-2.6.36.orig/drivers/net/ag71xx/ag71xx_phy.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/drivers/net/ag71xx/ag71xx_phy.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,213 @@ -+/* -+ * Atheros AR71xx built-in ethernet mac driver -+ * -+ * Copyright (C) 2008-2010 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Based on Atheros' AG7100 driver -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include "ag71xx.h" -+ -+static void ag71xx_phy_link_adjust(struct net_device *dev) -+{ -+ struct ag71xx *ag = netdev_priv(dev); -+ struct phy_device *phydev = ag->phy_dev; -+ unsigned long flags; -+ int status_change = 0; -+ -+ spin_lock_irqsave(&ag->lock, flags); -+ -+ if (phydev->link) { -+ if (ag->duplex != phydev->duplex -+ || ag->speed != phydev->speed) { -+ status_change = 1; -+ } -+ } -+ -+ if (phydev->link != ag->link) -+ status_change = 1; -+ -+ ag->link = phydev->link; -+ ag->duplex = phydev->duplex; -+ ag->speed = phydev->speed; -+ -+ if (status_change) -+ ag71xx_link_adjust(ag); -+ -+ spin_unlock_irqrestore(&ag->lock, flags); -+} -+ -+void ag71xx_phy_start(struct ag71xx *ag) -+{ -+ if (ag->phy_dev) { -+ phy_start(ag->phy_dev); -+ } else { -+ ag->link = 1; -+ ag71xx_link_adjust(ag); -+ } -+} -+ -+void ag71xx_phy_stop(struct ag71xx *ag) -+{ -+ if (ag->phy_dev) { -+ phy_stop(ag->phy_dev); -+ } else { -+ ag->link = 0; -+ ag71xx_link_adjust(ag); -+ } -+} -+ -+static int ag71xx_phy_connect_fixed(struct ag71xx *ag) -+{ -+ struct net_device *dev = ag->dev; -+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); -+ int ret = 0; -+ -+ /* use fixed settings */ -+ switch (pdata->speed) { -+ case SPEED_10: -+ case SPEED_100: -+ case SPEED_1000: -+ break; -+ default: -+ printk(KERN_ERR "%s: invalid speed specified\n", dev->name); -+ ret = -EINVAL; -+ break; -+ } -+ -+ printk(KERN_DEBUG "%s: using fixed link parameters\n", dev->name); -+ -+ ag->duplex = pdata->duplex; -+ ag->speed = pdata->speed; -+ -+ return ret; -+} -+ -+static int ag71xx_phy_connect_multi(struct ag71xx *ag) -+{ -+ struct net_device *dev = ag->dev; -+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); -+ struct phy_device *phydev = NULL; -+ int phy_addr; -+ int ret = 0; -+ -+ for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { -+ if (!(pdata->phy_mask & (1 << phy_addr))) -+ continue; -+ -+ if (ag->mii_bus->phy_map[phy_addr] == NULL) -+ continue; -+ -+ DBG("%s: PHY found at %s, uid=%08x\n", -+ dev->name, -+ dev_name(&ag->mii_bus->phy_map[phy_addr]->dev), -+ ag->mii_bus->phy_map[phy_addr]->phy_id); -+ -+ if (phydev == NULL) -+ phydev = ag->mii_bus->phy_map[phy_addr]; -+ } -+ -+ if (!phydev) { -+ printk(KERN_ERR "%s: no PHY found with phy_mask=%08x\n", -+ dev->name, pdata->phy_mask); -+ return -ENODEV; -+ } -+ -+ ag->phy_dev = phy_connect(dev, dev_name(&phydev->dev), -+ &ag71xx_phy_link_adjust, 0, -+ pdata->phy_if_mode); -+ -+ if (IS_ERR(ag->phy_dev)) { -+ printk(KERN_ERR "%s: could not connect to PHY at %s\n", -+ dev->name, dev_name(&phydev->dev)); -+ return PTR_ERR(ag->phy_dev); -+ } -+ -+ /* mask with MAC supported features */ -+ if (pdata->has_gbit) -+ phydev->supported &= PHY_GBIT_FEATURES; -+ else -+ phydev->supported &= PHY_BASIC_FEATURES; -+ -+ phydev->advertising = phydev->supported; -+ -+ printk(KERN_DEBUG "%s: connected to PHY at %s [uid=%08x, driver=%s]\n", -+ dev->name, dev_name(&phydev->dev), -+ phydev->phy_id, phydev->drv->name); -+ -+ ag->link = 0; -+ ag->speed = 0; -+ ag->duplex = -1; -+ -+ return ret; -+} -+ -+static int dev_is_class(struct device *dev, void *class) -+{ -+ if (dev->class != NULL && !strcmp(dev->class->name, class)) -+ return 1; -+ -+ return 0; -+} -+ -+static struct device *dev_find_class(struct device *parent, char *class) -+{ -+ if (dev_is_class(parent, class)) { -+ get_device(parent); -+ return parent; -+ } -+ -+ return device_find_child(parent, class, dev_is_class); -+} -+ -+static struct mii_bus *dev_to_mii_bus(struct device *dev) -+{ -+ struct device *d; -+ -+ d = dev_find_class(dev, "mdio_bus"); -+ if (d != NULL) { -+ struct mii_bus *bus; -+ -+ bus = to_mii_bus(d); -+ put_device(d); -+ -+ return bus; -+ } -+ -+ return NULL; -+} -+ -+int ag71xx_phy_connect(struct ag71xx *ag) -+{ -+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); -+ -+ ag->mii_bus = dev_to_mii_bus(pdata->mii_bus_dev); -+ if (ag->mii_bus == NULL) { -+ printk(KERN_ERR "%s: unable to find MII bus on device '%s'\n", -+ ag->dev->name, dev_name(pdata->mii_bus_dev)); -+ return -ENODEV; -+ } -+ -+ /* Reset the mdio bus explicitly */ -+ if (ag->mii_bus->reset) { -+ mutex_lock(&ag->mii_bus->mdio_lock); -+ ag->mii_bus->reset(ag->mii_bus); -+ mutex_unlock(&ag->mii_bus->mdio_lock); -+ } -+ -+ if (pdata->phy_mask) -+ return ag71xx_phy_connect_multi(ag); -+ -+ return ag71xx_phy_connect_fixed(ag); -+} -+ -+void ag71xx_phy_disconnect(struct ag71xx *ag) -+{ -+ if (ag->phy_dev) -+ phy_disconnect(ag->phy_dev); -+} -diff -Nur linux-2.6.36.orig/drivers/net/phy/Kconfig linux-2.6.36/drivers/net/phy/Kconfig ---- linux-2.6.36.orig/drivers/net/phy/Kconfig 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/drivers/net/phy/Kconfig 2010-12-17 18:34:51.000000000 +0100 -@@ -93,6 +93,10 @@ - ---help--- - Supports the KSZ9021, VSC8201, KS8001 PHYs. - -+config IP175C_PHY -+ tristate "Driver for IC+ IP175C/IP178C switches" -+ select SWCONFIG -+ - config FIXED_PHY - bool "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs" - depends on PHYLIB=y -diff -Nur linux-2.6.36.orig/drivers/net/phy/phy.c linux-2.6.36/drivers/net/phy/phy.c ---- linux-2.6.36.orig/drivers/net/phy/phy.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/drivers/net/phy/phy.c 2010-12-17 18:34:51.000000000 +0100 -@@ -298,6 +298,50 @@ - } - EXPORT_SYMBOL(phy_ethtool_gset); - -+int phy_ethtool_ioctl(struct phy_device *phydev, void *useraddr) -+{ -+ u32 cmd; -+ int tmp; -+ struct ethtool_cmd ecmd = { ETHTOOL_GSET }; -+ struct ethtool_value edata = { ETHTOOL_GLINK }; -+ -+ if (get_user(cmd, (u32 *) useraddr)) -+ return -EFAULT; -+ -+ switch (cmd) { -+ case ETHTOOL_GSET: -+ phy_ethtool_gset(phydev, &ecmd); -+ if (copy_to_user(useraddr, &ecmd, sizeof(ecmd))) -+ return -EFAULT; -+ return 0; -+ -+ case ETHTOOL_SSET: -+ if (copy_from_user(&ecmd, useraddr, sizeof(ecmd))) -+ return -EFAULT; -+ return phy_ethtool_sset(phydev, &ecmd); -+ -+ case ETHTOOL_NWAY_RST: -+ /* if autoneg is off, it's an error */ -+ tmp = phy_read(phydev, MII_BMCR); -+ if (tmp & BMCR_ANENABLE) { -+ tmp |= (BMCR_ANRESTART); -+ phy_write(phydev, MII_BMCR, tmp); -+ return 0; -+ } -+ return -EINVAL; -+ -+ case ETHTOOL_GLINK: -+ edata.data = (phy_read(phydev, -+ MII_BMSR) & BMSR_LSTATUS) ? 1 : 0; -+ if (copy_to_user(useraddr, &edata, sizeof(edata))) -+ return -EFAULT; -+ return 0; -+ } -+ -+ return -EOPNOTSUPP; -+} -+EXPORT_SYMBOL(phy_ethtool_ioctl); -+ - /** - * phy_mii_ioctl - generic PHY MII ioctl interface - * @phydev: the phy_device struct -@@ -352,7 +396,7 @@ - } - - phy_write(phydev, mii_data->reg_num, val); -- -+ - if (mii_data->reg_num == MII_BMCR && - val & BMCR_RESET && - phydev->drv->config_init) { -@@ -471,7 +515,7 @@ - int idx; - - idx = phy_find_setting(phydev->speed, phydev->duplex); -- -+ - idx++; - - idx = phy_find_valid(idx, phydev->supported); -diff -Nur linux-2.6.36.orig/drivers/net/phy/phy_device.c linux-2.6.36/drivers/net/phy/phy_device.c ---- linux-2.6.36.orig/drivers/net/phy/phy_device.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/drivers/net/phy/phy_device.c 2010-12-17 18:34:51.000000000 +0100 -@@ -146,6 +146,18 @@ - } - EXPORT_SYMBOL(phy_scan_fixups); - -+static int generic_receive_skb(struct sk_buff *skb) -+{ -+ skb->protocol = eth_type_trans(skb, skb->dev); -+ return netif_receive_skb(skb); -+} -+ -+static int generic_rx(struct sk_buff *skb) -+{ -+ skb->protocol = eth_type_trans(skb, skb->dev); -+ return netif_rx(skb); -+} -+ - struct phy_device* phy_device_create(struct mii_bus *bus, int addr, int phy_id) - { - struct phy_device *dev; -@@ -176,6 +188,8 @@ - dev_set_name(&dev->dev, PHY_ID_FMT, bus->id, addr); - - dev->state = PHY_DOWN; -+ dev->netif_receive_skb = &generic_receive_skb; -+ dev->netif_rx = &generic_rx; - - mutex_init(&dev->lock); - INIT_DELAYED_WORK(&dev->state_queue, phy_state_machine); -diff -Nur linux-2.6.36.orig/drivers/spi/Kconfig linux-2.6.36/drivers/spi/Kconfig ---- linux-2.6.36.orig/drivers/spi/Kconfig 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/drivers/spi/Kconfig 2010-12-17 18:34:51.000000000 +0100 -@@ -53,6 +53,13 @@ - - comment "SPI Master Controller Drivers" - -+config SPI_AR71XX -+ tristate "Atheros AR71xx SPI Controller" -+ depends on SPI_MASTER && ATHEROS_AR71XX -+ select SPI_BITBANG -+ help -+ This is the SPI contoller driver for Atheros AR71xx. -+ - config SPI_ATMEL - tristate "Atmel SPI Controller" - depends on (ARCH_AT91 || AVR32) -diff -Nur linux-2.6.36.orig/drivers/spi/Makefile linux-2.6.36/drivers/spi/Makefile ---- linux-2.6.36.orig/drivers/spi/Makefile 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/drivers/spi/Makefile 2010-12-17 18:34:51.000000000 +0100 -@@ -11,6 +11,7 @@ - obj-$(CONFIG_SPI_MASTER) += spi.o - - # SPI master controller drivers (bus) -+obj-$(CONFIG_SPI_AR71XX) += ar71xx_spi.o - obj-$(CONFIG_SPI_ATMEL) += atmel_spi.o - obj-$(CONFIG_SPI_BFIN) += spi_bfin5xx.o - obj-$(CONFIG_SPI_BITBANG) += spi_bitbang.o -diff -Nur linux-2.6.36.orig/drivers/spi/ap83_spi.c linux-2.6.36/drivers/spi/ap83_spi.c ---- linux-2.6.36.orig/drivers/spi/ap83_spi.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/drivers/spi/ap83_spi.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,282 @@ -+/* -+ * Atheros AP83 board specific SPI Controller driver -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#define DRV_DESC "Atheros AP83 board SPI Controller driver" -+#define DRV_VERSION "0.1.0" -+#define DRV_NAME "ap83-spi" -+ -+#define AP83_SPI_CLK_HIGH (1 << 23) -+#define AP83_SPI_CLK_LOW 0 -+#define AP83_SPI_MOSI_HIGH (1 << 22) -+#define AP83_SPI_MOSI_LOW 0 -+ -+#define AP83_SPI_GPIO_CS 1 -+#define AP83_SPI_GPIO_MISO 3 -+ -+struct ap83_spi { -+ struct spi_bitbang bitbang; -+ void __iomem *base; -+ u32 addr; -+ -+ struct platform_device *pdev; -+}; -+ -+static inline u32 ap83_spi_rr(struct ap83_spi *sp, u32 reg) -+{ -+ return __raw_readl(sp->base + reg); -+} -+ -+static inline struct ap83_spi *spidev_to_sp(struct spi_device *spi) -+{ -+ return spi_master_get_devdata(spi->master); -+} -+ -+static inline void setsck(struct spi_device *spi, int val) -+{ -+ struct ap83_spi *sp = spidev_to_sp(spi); -+ -+ if (val) -+ sp->addr |= AP83_SPI_CLK_HIGH; -+ else -+ sp->addr &= ~AP83_SPI_CLK_HIGH; -+ -+ dev_dbg(&spi->dev, "addr=%08x, SCK set to %s\n", -+ sp->addr, (val) ? "HIGH" : "LOW"); -+ -+ ap83_spi_rr(sp, sp->addr); -+} -+ -+static inline void setmosi(struct spi_device *spi, int val) -+{ -+ struct ap83_spi *sp = spidev_to_sp(spi); -+ -+ if (val) -+ sp->addr |= AP83_SPI_MOSI_HIGH; -+ else -+ sp->addr &= ~AP83_SPI_MOSI_HIGH; -+ -+ dev_dbg(&spi->dev, "addr=%08x, MOSI set to %s\n", -+ sp->addr, (val) ? "HIGH" : "LOW"); -+ -+ ap83_spi_rr(sp, sp->addr); -+} -+ -+static inline u32 getmiso(struct spi_device *spi) -+{ -+ u32 ret; -+ -+ ret = gpio_get_value(AP83_SPI_GPIO_MISO) ? 1 : 0; -+ dev_dbg(&spi->dev, "get MISO: %d\n", ret); -+ -+ return ret; -+} -+ -+static inline void do_spidelay(struct spi_device *spi, unsigned nsecs) -+{ -+ ndelay(nsecs); -+} -+ -+static void ap83_spi_chipselect(struct spi_device *spi, int on) -+{ -+ struct ap83_spi *sp = spidev_to_sp(spi); -+ -+ dev_dbg(&spi->dev, "set CS to %d\n", (on) ? 0 : 1); -+ -+ if (on) { -+ ar71xx_flash_acquire(); -+ -+ sp->addr = 0; -+ ap83_spi_rr(sp, sp->addr); -+ -+ gpio_set_value(AP83_SPI_GPIO_CS, 0); -+ } else { -+ gpio_set_value(AP83_SPI_GPIO_CS, 1); -+ ar71xx_flash_release(); -+ } -+} -+ -+#define spidelay(nsecs) \ -+ do { \ -+ /* Steal the spi_device pointer from our caller. \ -+ * The bitbang-API should probably get fixed here... */ \ -+ do_spidelay(spi, nsecs); \ -+ } while (0) -+ -+#define EXPAND_BITBANG_TXRX -+#include -+ -+static u32 ap83_spi_txrx_mode0(struct spi_device *spi, -+ unsigned nsecs, u32 word, u8 bits) -+{ -+ dev_dbg(&spi->dev, "TXRX0 word=%08x, bits=%u\n", word, bits); -+ return bitbang_txrx_be_cpha0(spi, nsecs, 0, word, bits); -+} -+ -+static u32 ap83_spi_txrx_mode1(struct spi_device *spi, -+ unsigned nsecs, u32 word, u8 bits) -+{ -+ dev_dbg(&spi->dev, "TXRX1 word=%08x, bits=%u\n", word, bits); -+ return bitbang_txrx_be_cpha1(spi, nsecs, 0, word, bits); -+} -+ -+static u32 ap83_spi_txrx_mode2(struct spi_device *spi, -+ unsigned nsecs, u32 word, u8 bits) -+{ -+ dev_dbg(&spi->dev, "TXRX2 word=%08x, bits=%u\n", word, bits); -+ return bitbang_txrx_be_cpha0(spi, nsecs, 1, word, bits); -+} -+ -+static u32 ap83_spi_txrx_mode3(struct spi_device *spi, -+ unsigned nsecs, u32 word, u8 bits) -+{ -+ dev_dbg(&spi->dev, "TXRX3 word=%08x, bits=%u\n", word, bits); -+ return bitbang_txrx_be_cpha1(spi, nsecs, 1, word, bits); -+} -+ -+static int ap83_spi_probe(struct platform_device *pdev) -+{ -+ struct spi_master *master; -+ struct ap83_spi *sp; -+ struct ap83_spi_platform_data *pdata; -+ struct resource *r; -+ int ret; -+ -+ ret = gpio_request(AP83_SPI_GPIO_MISO, "spi-miso"); -+ if (ret) { -+ dev_err(&pdev->dev, "gpio request failed for MISO\n"); -+ return ret; -+ } -+ -+ ret = gpio_request(AP83_SPI_GPIO_CS, "spi-cs"); -+ if (ret) { -+ dev_err(&pdev->dev, "gpio request failed for CS\n"); -+ goto err_free_miso; -+ } -+ -+ ret = gpio_direction_input(AP83_SPI_GPIO_MISO); -+ if (ret) { -+ dev_err(&pdev->dev, "unable to set direction of MISO\n"); -+ goto err_free_cs; -+ } -+ -+ ret = gpio_direction_output(AP83_SPI_GPIO_CS, 0); -+ if (ret) { -+ dev_err(&pdev->dev, "unable to set direction of CS\n"); -+ goto err_free_cs; -+ } -+ -+ master = spi_alloc_master(&pdev->dev, sizeof(*sp)); -+ if (master == NULL) { -+ dev_err(&pdev->dev, "failed to allocate spi master\n"); -+ return -ENOMEM; -+ } -+ -+ sp = spi_master_get_devdata(master); -+ platform_set_drvdata(pdev, sp); -+ -+ pdata = pdev->dev.platform_data; -+ -+ sp->bitbang.master = spi_master_get(master); -+ sp->bitbang.chipselect = ap83_spi_chipselect; -+ sp->bitbang.txrx_word[SPI_MODE_0] = ap83_spi_txrx_mode0; -+ sp->bitbang.txrx_word[SPI_MODE_1] = ap83_spi_txrx_mode1; -+ sp->bitbang.txrx_word[SPI_MODE_2] = ap83_spi_txrx_mode2; -+ sp->bitbang.txrx_word[SPI_MODE_3] = ap83_spi_txrx_mode3; -+ -+ sp->bitbang.master->bus_num = pdev->id; -+ sp->bitbang.master->num_chipselect = 1; -+ -+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (r == NULL) { -+ ret = -ENOENT; -+ goto err_spi_put; -+ } -+ -+ sp->base = ioremap_nocache(r->start, r->end - r->start + 1); -+ if (!sp->base) { -+ ret = -ENXIO; -+ goto err_spi_put; -+ } -+ -+ ret = spi_bitbang_start(&sp->bitbang); -+ if (!ret) -+ goto err_unmap; -+ -+ dev_info(&pdev->dev, "AP83 SPI adapter at %08x\n", r->start); -+ -+ return 0; -+ -+ err_unmap: -+ iounmap(sp->base); -+ err_spi_put: -+ platform_set_drvdata(pdev, NULL); -+ spi_master_put(sp->bitbang.master); -+ -+ err_free_cs: -+ gpio_free(AP83_SPI_GPIO_CS); -+ err_free_miso: -+ gpio_free(AP83_SPI_GPIO_MISO); -+ return ret; -+} -+ -+static int ap83_spi_remove(struct platform_device *pdev) -+{ -+ struct ap83_spi *sp = platform_get_drvdata(pdev); -+ -+ spi_bitbang_stop(&sp->bitbang); -+ iounmap(sp->base); -+ platform_set_drvdata(pdev, NULL); -+ spi_master_put(sp->bitbang.master); -+ -+ return 0; -+} -+ -+static struct platform_driver ap83_spi_drv = { -+ .probe = ap83_spi_probe, -+ .remove = ap83_spi_remove, -+ .driver = { -+ .name = DRV_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init ap83_spi_init(void) -+{ -+ return platform_driver_register(&ap83_spi_drv); -+} -+module_init(ap83_spi_init); -+ -+static void __exit ap83_spi_exit(void) -+{ -+ platform_driver_unregister(&ap83_spi_drv); -+} -+module_exit(ap83_spi_exit); -+ -+MODULE_ALIAS("platform:" DRV_NAME); -+MODULE_DESCRIPTION(DRV_DESC); -+MODULE_VERSION(DRV_VERSION); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_LICENSE("GPL v2"); -diff -Nur linux-2.6.36.orig/drivers/spi/ar71xx_spi.c linux-2.6.36/drivers/spi/ar71xx_spi.c ---- linux-2.6.36.orig/drivers/spi/ar71xx_spi.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/drivers/spi/ar71xx_spi.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,283 @@ -+/* -+ * Atheros AR71xx SPI Controller driver -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#define DRV_DESC "Atheros AR71xx SPI Controller driver" -+#define DRV_VERSION "0.2.4" -+#define DRV_NAME "ar71xx-spi" -+ -+#undef PER_BIT_READ -+ -+struct ar71xx_spi { -+ struct spi_bitbang bitbang; -+ u32 ioc_base; -+ u32 reg_ctrl; -+ -+ void __iomem *base; -+ -+ struct platform_device *pdev; -+ u32 (*get_ioc_base)(u8 chip_select, int cs_high, -+ int is_on); -+}; -+ -+static inline u32 ar71xx_spi_rr(struct ar71xx_spi *sp, unsigned reg) -+{ -+ return __raw_readl(sp->base + reg); -+} -+ -+static inline void ar71xx_spi_wr(struct ar71xx_spi *sp, unsigned reg, u32 val) -+{ -+ __raw_writel(val, sp->base + reg); -+} -+ -+static inline struct ar71xx_spi *spidev_to_sp(struct spi_device *spi) -+{ -+ return spi_master_get_devdata(spi->master); -+} -+ -+static u32 ar71xx_spi_get_ioc_base(u8 chip_select, int cs_high, int is_on) -+{ -+ u32 ret; -+ -+ if (is_on == AR71XX_SPI_CS_INACTIVE) -+ ret = SPI_IOC_CS_ALL; -+ else -+ ret = SPI_IOC_CS_ALL & ~SPI_IOC_CS(chip_select); -+ -+ return ret; -+} -+ -+static void ar71xx_spi_chipselect(struct spi_device *spi, int value) -+{ -+ struct ar71xx_spi *sp = spidev_to_sp(spi); -+ void __iomem *base = sp->base; -+ u32 ioc_base; -+ -+ switch (value) { -+ case BITBANG_CS_INACTIVE: -+ ioc_base = sp->get_ioc_base(spi->chip_select, -+ (spi->mode & SPI_CS_HIGH) != 0, -+ AR71XX_SPI_CS_INACTIVE); -+ __raw_writel(ioc_base, base + SPI_REG_IOC); -+ break; -+ -+ case BITBANG_CS_ACTIVE: -+ ioc_base = sp->get_ioc_base(spi->chip_select, -+ (spi->mode & SPI_CS_HIGH) != 0, -+ AR71XX_SPI_CS_ACTIVE); -+ -+ __raw_writel(ioc_base, base + SPI_REG_IOC); -+ sp->ioc_base = ioc_base; -+ break; -+ } -+} -+ -+static void ar71xx_spi_setup_regs(struct spi_device *spi) -+{ -+ struct ar71xx_spi *sp = spidev_to_sp(spi); -+ -+ /* enable GPIO mode */ -+ ar71xx_spi_wr(sp, SPI_REG_FS, SPI_FS_GPIO); -+ -+ /* save CTRL register */ -+ sp->reg_ctrl = ar71xx_spi_rr(sp, SPI_REG_CTRL); -+ -+ /* TODO: setup speed? */ -+ ar71xx_spi_wr(sp, SPI_REG_CTRL, 0x43); -+} -+ -+static void ar71xx_spi_restore_regs(struct spi_device *spi) -+{ -+ struct ar71xx_spi *sp = spidev_to_sp(spi); -+ -+ /* restore CTRL register */ -+ ar71xx_spi_wr(sp, SPI_REG_CTRL, sp->reg_ctrl); -+ /* disable GPIO mode */ -+ ar71xx_spi_wr(sp, SPI_REG_FS, 0); -+} -+ -+static int ar71xx_spi_setup(struct spi_device *spi) -+{ -+ int status; -+ -+ if (spi->bits_per_word > 32) -+ return -EINVAL; -+ -+ if (!spi->controller_state) -+ ar71xx_spi_setup_regs(spi); -+ -+ status = spi_bitbang_setup(spi); -+ if (status && !spi->controller_state) -+ ar71xx_spi_restore_regs(spi); -+ -+ return status; -+} -+ -+static void ar71xx_spi_cleanup(struct spi_device *spi) -+{ -+ ar71xx_spi_restore_regs(spi); -+ spi_bitbang_cleanup(spi); -+} -+ -+static u32 ar71xx_spi_txrx_mode0(struct spi_device *spi, unsigned nsecs, -+ u32 word, u8 bits) -+{ -+ struct ar71xx_spi *sp = spidev_to_sp(spi); -+ void __iomem *base = sp->base; -+ u32 ioc = sp->ioc_base; -+ u32 ret; -+ -+ /* clock starts at inactive polarity */ -+ for (word <<= (32 - bits); likely(bits); bits--) { -+ u32 out; -+ -+ if (word & (1 << 31)) -+ out = ioc | SPI_IOC_DO; -+ else -+ out = ioc & ~SPI_IOC_DO; -+ -+ /* setup MSB (to slave) on trailing edge */ -+ __raw_writel(out, base + SPI_REG_IOC); -+ -+ __raw_writel(out | SPI_IOC_CLK, base + SPI_REG_IOC); -+ -+ word <<= 1; -+ -+#ifdef PER_BIT_READ -+ /* sample MSB (from slave) on leading edge */ -+ ret = __raw_readl(base + SPI_REG_RDS); -+ __raw_writel(out, base + SPI_REG_IOC); -+#endif -+ -+ } -+ -+#ifndef PER_BIT_READ -+ ret = __raw_readl(base + SPI_REG_RDS); -+#endif -+ return ret; -+} -+ -+static int ar71xx_spi_probe(struct platform_device *pdev) -+{ -+ struct spi_master *master; -+ struct ar71xx_spi *sp; -+ struct ar71xx_spi_platform_data *pdata; -+ struct resource *r; -+ int ret; -+ -+ master = spi_alloc_master(&pdev->dev, sizeof(*sp)); -+ if (master == NULL) { -+ dev_err(&pdev->dev, "failed to allocate spi master\n"); -+ return -ENOMEM; -+ } -+ -+ sp = spi_master_get_devdata(master); -+ platform_set_drvdata(pdev, sp); -+ -+ pdata = pdev->dev.platform_data; -+ -+ master->setup = ar71xx_spi_setup; -+ master->cleanup = ar71xx_spi_cleanup; -+ -+ sp->bitbang.master = spi_master_get(master); -+ sp->bitbang.chipselect = ar71xx_spi_chipselect; -+ sp->bitbang.txrx_word[SPI_MODE_0] = ar71xx_spi_txrx_mode0; -+ sp->bitbang.setup_transfer = spi_bitbang_setup_transfer; -+ -+ sp->get_ioc_base = ar71xx_spi_get_ioc_base; -+ if (pdata) { -+ sp->bitbang.master->bus_num = pdata->bus_num; -+ sp->bitbang.master->num_chipselect = pdata->num_chipselect; -+ if (pdata->get_ioc_base) -+ sp->get_ioc_base = pdata->get_ioc_base; -+ } else { -+ sp->bitbang.master->bus_num = 0; -+ sp->bitbang.master->num_chipselect = 3; -+ } -+ -+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (r == NULL) { -+ ret = -ENOENT; -+ goto err1; -+ } -+ -+ sp->base = ioremap_nocache(r->start, r->end - r->start + 1); -+ if (!sp->base) { -+ ret = -ENXIO; -+ goto err1; -+ } -+ -+ ret = spi_bitbang_start(&sp->bitbang); -+ if (!ret) -+ return 0; -+ -+ iounmap(sp->base); -+ err1: -+ platform_set_drvdata(pdev, NULL); -+ spi_master_put(sp->bitbang.master); -+ -+ return ret; -+} -+ -+static int ar71xx_spi_remove(struct platform_device *pdev) -+{ -+ struct ar71xx_spi *sp = platform_get_drvdata(pdev); -+ -+ spi_bitbang_stop(&sp->bitbang); -+ iounmap(sp->base); -+ platform_set_drvdata(pdev, NULL); -+ spi_master_put(sp->bitbang.master); -+ -+ return 0; -+} -+ -+static struct platform_driver ar71xx_spi_drv = { -+ .probe = ar71xx_spi_probe, -+ .remove = ar71xx_spi_remove, -+ .driver = { -+ .name = DRV_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init ar71xx_spi_init(void) -+{ -+ printk(KERN_INFO DRV_DESC " version " DRV_VERSION "\n"); -+ return platform_driver_register(&ar71xx_spi_drv); -+} -+module_init(ar71xx_spi_init); -+ -+static void __exit ar71xx_spi_exit(void) -+{ -+ platform_driver_unregister(&ar71xx_spi_drv); -+} -+module_exit(ar71xx_spi_exit); -+ -+MODULE_ALIAS("platform:" DRV_NAME); -+MODULE_DESCRIPTION(DRV_DESC); -+MODULE_VERSION(DRV_VERSION); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_AUTHOR("Imre Kaloz "); -+MODULE_LICENSE("GPL v2"); -diff -Nur linux-2.6.36.orig/drivers/spi/pb44_spi.c linux-2.6.36/drivers/spi/pb44_spi.c ---- linux-2.6.36.orig/drivers/spi/pb44_spi.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/drivers/spi/pb44_spi.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,299 @@ -+/* -+ * Atheros PB44 board SPI controller driver -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#define DRV_DESC "Atheros PB44 SPI Controller driver" -+#define DRV_VERSION "0.1.0" -+#define DRV_NAME "pb44-spi" -+ -+#undef PER_BIT_READ -+ -+struct ar71xx_spi { -+ struct spi_bitbang bitbang; -+ u32 ioc_base; -+ u32 reg_ctrl; -+ -+ void __iomem *base; -+ -+ struct platform_device *pdev; -+}; -+ -+static inline u32 pb44_spi_rr(struct ar71xx_spi *sp, unsigned reg) -+{ -+ return __raw_readl(sp->base + reg); -+} -+ -+static inline void pb44_spi_wr(struct ar71xx_spi *sp, unsigned reg, u32 val) -+{ -+ __raw_writel(val, sp->base + reg); -+} -+ -+static inline struct ar71xx_spi *spidev_to_sp(struct spi_device *spi) -+{ -+ return spi_master_get_devdata(spi->master); -+} -+ -+static void pb44_spi_chipselect(struct spi_device *spi, int is_active) -+{ -+ struct ar71xx_spi *sp = spidev_to_sp(spi); -+ int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active; -+ -+ if (is_active) { -+ /* set initial clock polarity */ -+ if (spi->mode & SPI_CPOL) -+ sp->ioc_base |= SPI_IOC_CLK; -+ else -+ sp->ioc_base &= ~SPI_IOC_CLK; -+ -+ pb44_spi_wr(sp, SPI_REG_IOC, sp->ioc_base); -+ } -+ -+ if (spi->chip_select) { -+ unsigned long gpio = (unsigned long) spi->controller_data; -+ -+ /* SPI is normally active-low */ -+ gpio_set_value(gpio, cs_high); -+ } else { -+ if (cs_high) -+ sp->ioc_base |= SPI_IOC_CS0; -+ else -+ sp->ioc_base &= ~SPI_IOC_CS0; -+ -+ pb44_spi_wr(sp, SPI_REG_IOC, sp->ioc_base); -+ } -+ -+} -+ -+static int pb44_spi_setup_cs(struct spi_device *spi) -+{ -+ struct ar71xx_spi *sp = spidev_to_sp(spi); -+ -+ /* enable GPIO mode */ -+ pb44_spi_wr(sp, SPI_REG_FS, SPI_FS_GPIO); -+ -+ /* save CTRL register */ -+ sp->reg_ctrl = pb44_spi_rr(sp, SPI_REG_CTRL); -+ sp->ioc_base = pb44_spi_rr(sp, SPI_REG_IOC); -+ -+ /* TODO: setup speed? */ -+ pb44_spi_wr(sp, SPI_REG_CTRL, 0x43); -+ -+ if (spi->chip_select) { -+ unsigned long gpio = (unsigned long) spi->controller_data; -+ int status = 0; -+ -+ status = gpio_request(gpio, dev_name(&spi->dev)); -+ if (status) -+ return status; -+ -+ status = gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH); -+ if (status) { -+ gpio_free(gpio); -+ return status; -+ } -+ } else { -+ if (spi->mode & SPI_CS_HIGH) -+ sp->ioc_base |= SPI_IOC_CS0; -+ else -+ sp->ioc_base &= ~SPI_IOC_CS0; -+ pb44_spi_wr(sp, SPI_REG_IOC, sp->ioc_base); -+ } -+ -+ return 0; -+} -+ -+static void pb44_spi_cleanup_cs(struct spi_device *spi) -+{ -+ struct ar71xx_spi *sp = spidev_to_sp(spi); -+ -+ if (spi->chip_select) { -+ unsigned long gpio = (unsigned long) spi->controller_data; -+ gpio_free(gpio); -+ } -+ -+ /* restore CTRL register */ -+ pb44_spi_wr(sp, SPI_REG_CTRL, sp->reg_ctrl); -+ /* disable GPIO mode */ -+ pb44_spi_wr(sp, SPI_REG_FS, 0); -+} -+ -+static int pb44_spi_setup(struct spi_device *spi) -+{ -+ int status = 0; -+ -+ if (spi->bits_per_word > 32) -+ return -EINVAL; -+ -+ if (!spi->controller_state) { -+ status = pb44_spi_setup_cs(spi); -+ if (status) -+ return status; -+ } -+ -+ status = spi_bitbang_setup(spi); -+ if (status && !spi->controller_state) -+ pb44_spi_cleanup_cs(spi); -+ -+ return status; -+} -+ -+static void pb44_spi_cleanup(struct spi_device *spi) -+{ -+ pb44_spi_cleanup_cs(spi); -+ spi_bitbang_cleanup(spi); -+} -+ -+static u32 pb44_spi_txrx_mode0(struct spi_device *spi, unsigned nsecs, -+ u32 word, u8 bits) -+{ -+ struct ar71xx_spi *sp = spidev_to_sp(spi); -+ u32 ioc = sp->ioc_base; -+ u32 ret; -+ -+ /* clock starts at inactive polarity */ -+ for (word <<= (32 - bits); likely(bits); bits--) { -+ u32 out; -+ -+ if (word & (1 << 31)) -+ out = ioc | SPI_IOC_DO; -+ else -+ out = ioc & ~SPI_IOC_DO; -+ -+ /* setup MSB (to slave) on trailing edge */ -+ pb44_spi_wr(sp, SPI_REG_IOC, out); -+ pb44_spi_wr(sp, SPI_REG_IOC, out | SPI_IOC_CLK); -+ -+ word <<= 1; -+ -+#ifdef PER_BIT_READ -+ /* sample MSB (from slave) on leading edge */ -+ ret = pb44_spi_rr(sp, SPI_REG_RDS); -+ pb44_spi_wr(sp, SPI_REG_IOC, out); -+#endif -+ } -+ -+#ifndef PER_BIT_READ -+ ret = pb44_spi_rr(sp, SPI_REG_RDS); -+#endif -+ return ret; -+} -+ -+static int pb44_spi_probe(struct platform_device *pdev) -+{ -+ struct spi_master *master; -+ struct ar71xx_spi *sp; -+ struct ar71xx_spi_platform_data *pdata; -+ struct resource *r; -+ int ret; -+ -+ master = spi_alloc_master(&pdev->dev, sizeof(*sp)); -+ if (master == NULL) { -+ dev_err(&pdev->dev, "failed to allocate spi master\n"); -+ return -ENOMEM; -+ } -+ -+ sp = spi_master_get_devdata(master); -+ platform_set_drvdata(pdev, sp); -+ -+ pdata = pdev->dev.platform_data; -+ -+ master->setup = pb44_spi_setup; -+ master->cleanup = pb44_spi_cleanup; -+ if (pdata) { -+ master->bus_num = pdata->bus_num; -+ master->num_chipselect = pdata->num_chipselect; -+ } else { -+ master->bus_num = 0; -+ master->num_chipselect = 1; -+ } -+ -+ sp->bitbang.master = spi_master_get(master); -+ sp->bitbang.chipselect = pb44_spi_chipselect; -+ sp->bitbang.txrx_word[SPI_MODE_0] = pb44_spi_txrx_mode0; -+ sp->bitbang.setup_transfer = spi_bitbang_setup_transfer; -+ sp->bitbang.flags = SPI_CS_HIGH; -+ -+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (r == NULL) { -+ ret = -ENOENT; -+ goto err1; -+ } -+ -+ sp->base = ioremap_nocache(r->start, r->end - r->start + 1); -+ if (!sp->base) { -+ ret = -ENXIO; -+ goto err1; -+ } -+ -+ ret = spi_bitbang_start(&sp->bitbang); -+ if (!ret) -+ return 0; -+ -+ iounmap(sp->base); -+ err1: -+ platform_set_drvdata(pdev, NULL); -+ spi_master_put(sp->bitbang.master); -+ -+ return ret; -+} -+ -+static int pb44_spi_remove(struct platform_device *pdev) -+{ -+ struct ar71xx_spi *sp = platform_get_drvdata(pdev); -+ -+ spi_bitbang_stop(&sp->bitbang); -+ iounmap(sp->base); -+ platform_set_drvdata(pdev, NULL); -+ spi_master_put(sp->bitbang.master); -+ -+ return 0; -+} -+ -+static struct platform_driver pb44_spi_drv = { -+ .probe = pb44_spi_probe, -+ .remove = pb44_spi_remove, -+ .driver = { -+ .name = DRV_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init pb44_spi_init(void) -+{ -+ return platform_driver_register(&pb44_spi_drv); -+} -+module_init(pb44_spi_init); -+ -+static void __exit pb44_spi_exit(void) -+{ -+ platform_driver_unregister(&pb44_spi_drv); -+} -+module_exit(pb44_spi_exit); -+ -+MODULE_ALIAS("platform:" DRV_NAME); -+MODULE_DESCRIPTION(DRV_DESC); -+MODULE_VERSION(DRV_VERSION); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_LICENSE("GPL v2"); -diff -Nur linux-2.6.36.orig/drivers/spi/spi_vsc7385.c linux-2.6.36/drivers/spi/spi_vsc7385.c ---- linux-2.6.36.orig/drivers/spi/spi_vsc7385.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/drivers/spi/spi_vsc7385.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,620 @@ -+/* -+ * SPI driver for the Vitesse VSC7385 ethernet switch -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define DRV_NAME "spi-vsc7385" -+#define DRV_DESC "Vitesse VSC7385 Gbit ethernet switch driver" -+#define DRV_VERSION "0.1.0" -+ -+#define VSC73XX_BLOCK_MAC 0x1 -+#define VSC73XX_BLOCK_2 0x2 -+#define VSC73XX_BLOCK_MII 0x3 -+#define VSC73XX_BLOCK_4 0x4 -+#define VSC73XX_BLOCK_5 0x5 -+#define VSC73XX_BLOCK_SYSTEM 0x7 -+ -+#define VSC73XX_SUBBLOCK_PORT_0 0 -+#define VSC73XX_SUBBLOCK_PORT_1 1 -+#define VSC73XX_SUBBLOCK_PORT_2 2 -+#define VSC73XX_SUBBLOCK_PORT_3 3 -+#define VSC73XX_SUBBLOCK_PORT_4 4 -+#define VSC73XX_SUBBLOCK_PORT_MAC 6 -+ -+/* MAC Block registers */ -+#define VSC73XX_MAC_CFG 0x0 -+#define VSC73XX_ADVPORTM 0x19 -+#define VSC73XX_RXOCT 0x50 -+#define VSC73XX_TXOCT 0x51 -+#define VSC73XX_C_RX0 0x52 -+#define VSC73XX_C_RX1 0x53 -+#define VSC73XX_C_RX2 0x54 -+#define VSC73XX_C_TX0 0x55 -+#define VSC73XX_C_TX1 0x56 -+#define VSC73XX_C_TX2 0x57 -+#define VSC73XX_C_CFG 0x58 -+ -+/* MAC_CFG register bits */ -+#define VSC73XX_MAC_CFG_WEXC_DIS (1 << 31) -+#define VSC73XX_MAC_CFG_PORT_RST (1 << 29) -+#define VSC73XX_MAC_CFG_TX_EN (1 << 28) -+#define VSC73XX_MAC_CFG_SEED_LOAD (1 << 27) -+#define VSC73XX_MAC_CFG_FDX (1 << 18) -+#define VSC73XX_MAC_CFG_GIGE (1 << 17) -+#define VSC73XX_MAC_CFG_RX_EN (1 << 16) -+#define VSC73XX_MAC_CFG_VLAN_DBLAWR (1 << 15) -+#define VSC73XX_MAC_CFG_VLAN_AWR (1 << 14) -+#define VSC73XX_MAC_CFG_100_BASE_T (1 << 13) -+#define VSC73XX_MAC_CFG_TX_IPG(x) (((x) & 0x1f) << 6) -+#define VSC73XX_MAC_CFG_MAC_RX_RST (1 << 5) -+#define VSC73XX_MAC_CFG_MAC_TX_RST (1 << 4) -+#define VSC73XX_MAC_CFG_BIT2 (1 << 2) -+#define VSC73XX_MAC_CFG_CLK_SEL(x) ((x) & 0x3) -+ -+/* ADVPORTM register bits */ -+#define VSC73XX_ADVPORTM_IFG_PPM (1 << 7) -+#define VSC73XX_ADVPORTM_EXC_COL_CONT (1 << 6) -+#define VSC73XX_ADVPORTM_EXT_PORT (1 << 5) -+#define VSC73XX_ADVPORTM_INV_GTX (1 << 4) -+#define VSC73XX_ADVPORTM_ENA_GTX (1 << 3) -+#define VSC73XX_ADVPORTM_DDR_MODE (1 << 2) -+#define VSC73XX_ADVPORTM_IO_LOOPBACK (1 << 1) -+#define VSC73XX_ADVPORTM_HOST_LOOPBACK (1 << 0) -+ -+/* MII Block registers */ -+#define VSC73XX_MII_STAT 0x0 -+#define VSC73XX_MII_CMD 0x1 -+#define VSC73XX_MII_DATA 0x2 -+ -+/* System Block registers */ -+#define VSC73XX_ICPU_SIPAD 0x01 -+#define VSC73XX_ICPU_CLOCK_DELAY 0x05 -+#define VSC73XX_ICPU_CTRL 0x10 -+#define VSC73XX_ICPU_ADDR 0x11 -+#define VSC73XX_ICPU_SRAM 0x12 -+#define VSC73XX_ICPU_MBOX_VAL 0x15 -+#define VSC73XX_ICPU_MBOX_SET 0x16 -+#define VSC73XX_ICPU_MBOX_CLR 0x17 -+#define VSC73XX_ICPU_CHIPID 0x18 -+#define VSC73XX_ICPU_GPIO 0x34 -+ -+#define VSC73XX_ICPU_CTRL_CLK_DIV (1 << 8) -+#define VSC73XX_ICPU_CTRL_SRST_HOLD (1 << 7) -+#define VSC73XX_ICPU_CTRL_BOOT_EN (1 << 3) -+#define VSC73XX_ICPU_CTRL_EXT_ACC_EN (1 << 2) -+#define VSC73XX_ICPU_CTRL_CLK_EN (1 << 1) -+#define VSC73XX_ICPU_CTRL_SRST (1 << 0) -+ -+#define VSC73XX_ICPU_CHIPID_ID_SHIFT 12 -+#define VSC73XX_ICPU_CHIPID_ID_MASK 0xffff -+#define VSC73XX_ICPU_CHIPID_REV_SHIFT 28 -+#define VSC73XX_ICPU_CHIPID_REV_MASK 0xf -+#define VSC73XX_ICPU_CHIPID_ID_7385 0x7385 -+#define VSC73XX_ICPU_CHIPID_ID_7395 0x7395 -+ -+#define VSC73XX_CMD_MODE_READ 0 -+#define VSC73XX_CMD_MODE_WRITE 1 -+#define VSC73XX_CMD_MODE_SHIFT 4 -+#define VSC73XX_CMD_BLOCK_SHIFT 5 -+#define VSC73XX_CMD_BLOCK_MASK 0x7 -+#define VSC73XX_CMD_SUBBLOCK_MASK 0xf -+ -+#define VSC7385_CLOCK_DELAY ((3 << 4) | 3) -+#define VSC7385_CLOCK_DELAY_MASK ((3 << 4) | 3) -+ -+#define VSC73XX_ICPU_CTRL_STOP (VSC73XX_ICPU_CTRL_SRST_HOLD | \ -+ VSC73XX_ICPU_CTRL_BOOT_EN | \ -+ VSC73XX_ICPU_CTRL_EXT_ACC_EN) -+ -+#define VSC73XX_ICPU_CTRL_START (VSC73XX_ICPU_CTRL_CLK_DIV | \ -+ VSC73XX_ICPU_CTRL_BOOT_EN | \ -+ VSC73XX_ICPU_CTRL_CLK_EN | \ -+ VSC73XX_ICPU_CTRL_SRST) -+ -+#define VSC7385_ADVPORTM_MASK (VSC73XX_ADVPORTM_IFG_PPM | \ -+ VSC73XX_ADVPORTM_EXC_COL_CONT | \ -+ VSC73XX_ADVPORTM_EXT_PORT | \ -+ VSC73XX_ADVPORTM_INV_GTX | \ -+ VSC73XX_ADVPORTM_ENA_GTX | \ -+ VSC73XX_ADVPORTM_DDR_MODE | \ -+ VSC73XX_ADVPORTM_IO_LOOPBACK | \ -+ VSC73XX_ADVPORTM_HOST_LOOPBACK) -+ -+#define VSC7385_ADVPORTM_INIT (VSC73XX_ADVPORTM_EXT_PORT | \ -+ VSC73XX_ADVPORTM_ENA_GTX | \ -+ VSC73XX_ADVPORTM_DDR_MODE) -+ -+#define VSC7385_MAC_CFG_RESET (VSC73XX_MAC_CFG_PORT_RST | \ -+ VSC73XX_MAC_CFG_MAC_RX_RST | \ -+ VSC73XX_MAC_CFG_MAC_TX_RST) -+ -+#define VSC73XX_MAC_CFG_INIT (VSC73XX_MAC_CFG_TX_EN | \ -+ VSC73XX_MAC_CFG_FDX | \ -+ VSC73XX_MAC_CFG_GIGE | \ -+ VSC73XX_MAC_CFG_RX_EN) -+ -+#define VSC73XX_RESET_DELAY 100 -+ -+struct vsc7385 { -+ struct spi_device *spi; -+ struct mutex lock; -+ struct vsc7385_platform_data *pdata; -+}; -+ -+static int vsc7385_is_addr_valid(u8 block, u8 subblock) -+{ -+ switch (block) { -+ case VSC73XX_BLOCK_MAC: -+ switch (subblock) { -+ case 0 ... 4: -+ case 6: -+ return 1; -+ } -+ break; -+ -+ case VSC73XX_BLOCK_2: -+ case VSC73XX_BLOCK_SYSTEM: -+ switch (subblock) { -+ case 0: -+ return 1; -+ } -+ break; -+ -+ case VSC73XX_BLOCK_MII: -+ case VSC73XX_BLOCK_4: -+ case VSC73XX_BLOCK_5: -+ switch (subblock) { -+ case 0 ... 1: -+ return 1; -+ } -+ break; -+ } -+ -+ return 0; -+} -+ -+static inline u8 vsc7385_make_addr(u8 mode, u8 block, u8 subblock) -+{ -+ u8 ret; -+ -+ ret = (block & VSC73XX_CMD_BLOCK_MASK) << VSC73XX_CMD_BLOCK_SHIFT; -+ ret |= (mode & 1) << VSC73XX_CMD_MODE_SHIFT; -+ ret |= subblock & VSC73XX_CMD_SUBBLOCK_MASK; -+ -+ return ret; -+} -+ -+static int vsc7385_read(struct vsc7385 *vsc, u8 block, u8 subblock, u8 reg, -+ u32 *value) -+{ -+ u8 cmd[4]; -+ u8 buf[4]; -+ struct spi_transfer t[2]; -+ struct spi_message m; -+ int err; -+ -+ if (!vsc7385_is_addr_valid(block, subblock)) -+ return -EINVAL; -+ -+ spi_message_init(&m); -+ -+ memset(&t, 0, sizeof(t)); -+ -+ t[0].tx_buf = cmd; -+ t[0].len = sizeof(cmd); -+ spi_message_add_tail(&t[0], &m); -+ -+ t[1].rx_buf = buf; -+ t[1].len = sizeof(buf); -+ spi_message_add_tail(&t[1], &m); -+ -+ cmd[0] = vsc7385_make_addr(VSC73XX_CMD_MODE_READ, block, subblock); -+ cmd[1] = reg; -+ cmd[2] = 0; -+ cmd[3] = 0; -+ -+ mutex_lock(&vsc->lock); -+ err = spi_sync(vsc->spi, &m); -+ mutex_unlock(&vsc->lock); -+ -+ if (err) -+ return err; -+ -+ *value = (((u32) buf[0]) << 24) | (((u32) buf[1]) << 16) | -+ (((u32) buf[2]) << 8) | ((u32) buf[3]); -+ -+ return 0; -+} -+ -+ -+static int vsc7385_write(struct vsc7385 *vsc, u8 block, u8 subblock, u8 reg, -+ u32 value) -+{ -+ u8 cmd[2]; -+ u8 buf[4]; -+ struct spi_transfer t[2]; -+ struct spi_message m; -+ int err; -+ -+ if (!vsc7385_is_addr_valid(block, subblock)) -+ return -EINVAL; -+ -+ spi_message_init(&m); -+ -+ memset(&t, 0, sizeof(t)); -+ -+ t[0].tx_buf = cmd; -+ t[0].len = sizeof(cmd); -+ spi_message_add_tail(&t[0], &m); -+ -+ t[1].tx_buf = buf; -+ t[1].len = sizeof(buf); -+ spi_message_add_tail(&t[1], &m); -+ -+ cmd[0] = vsc7385_make_addr(VSC73XX_CMD_MODE_WRITE, block, subblock); -+ cmd[1] = reg; -+ -+ buf[0] = (value >> 24) & 0xff; -+ buf[1] = (value >> 16) & 0xff; -+ buf[2] = (value >> 8) & 0xff; -+ buf[3] = value & 0xff; -+ -+ mutex_lock(&vsc->lock); -+ err = spi_sync(vsc->spi, &m); -+ mutex_unlock(&vsc->lock); -+ -+ return err; -+} -+ -+static inline int vsc7385_write_verify(struct vsc7385 *vsc, u8 block, -+ u8 subblock, u8 reg, u32 value, -+ u32 read_mask, u32 read_val) -+{ -+ struct spi_device *spi = vsc->spi; -+ u32 t; -+ int err; -+ -+ err = vsc7385_write(vsc, block, subblock, reg, value); -+ if (err) -+ return err; -+ -+ err = vsc7385_read(vsc, block, subblock, reg, &t); -+ if (err) -+ return err; -+ -+ if ((t & read_mask) != read_val) { -+ dev_err(&spi->dev, "register write error\n"); -+ return -EIO; -+ } -+ -+ return 0; -+} -+ -+static inline int vsc7385_set_clock_delay(struct vsc7385 *vsc, u32 val) -+{ -+ return vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, -+ VSC73XX_ICPU_CLOCK_DELAY, val); -+} -+ -+static inline int vsc7385_get_clock_delay(struct vsc7385 *vsc, u32 *val) -+{ -+ return vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, -+ VSC73XX_ICPU_CLOCK_DELAY, val); -+} -+ -+static inline int vsc7385_icpu_stop(struct vsc7385 *vsc) -+{ -+ return vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_ICPU_CTRL, -+ VSC73XX_ICPU_CTRL_STOP); -+} -+ -+static inline int vsc7385_icpu_start(struct vsc7385 *vsc) -+{ -+ return vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_ICPU_CTRL, -+ VSC73XX_ICPU_CTRL_START); -+} -+ -+static inline int vsc7385_icpu_reset(struct vsc7385 *vsc) -+{ -+ int rc; -+ -+ rc = vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_ICPU_ADDR, -+ 0x0000); -+ if (rc) -+ dev_err(&vsc->spi->dev, -+ "could not reset microcode, err=%d\n", rc); -+ -+ return rc; -+} -+ -+static int vsc7385_upload_ucode(struct vsc7385 *vsc) -+{ -+ struct spi_device *spi = vsc->spi; -+ const struct firmware *firmware; -+ char *ucode_name; -+ unsigned char *dp; -+ unsigned int curVal; -+ int i; -+ int diffs; -+ int rc; -+ -+ ucode_name = (vsc->pdata->ucode_name) ? vsc->pdata->ucode_name -+ : "vsc7385_ucode.bin"; -+ rc = request_firmware(&firmware, ucode_name, &spi->dev); -+ if (rc) { -+ dev_err(&spi->dev, "request_firmware failed, err=%d\n", -+ rc); -+ return rc; -+ } -+ -+ rc = vsc7385_icpu_stop(vsc); -+ if (rc) -+ goto out; -+ -+ rc = vsc7385_icpu_reset(vsc); -+ if (rc) -+ goto out; -+ -+ dev_info(&spi->dev, "uploading microcode...\n"); -+ -+ dp = (unsigned char *) firmware->data; -+ for (i = 0; i < firmware->size; i++) { -+ rc = vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, -+ VSC73XX_ICPU_SRAM, *dp++); -+ if (rc) { -+ dev_err(&spi->dev, "could not load microcode, err=%d\n", -+ rc); -+ goto out; -+ } -+ } -+ -+ rc = vsc7385_icpu_reset(vsc); -+ if (rc) -+ goto out; -+ -+ dev_info(&spi->dev, "verifying microcode...\n"); -+ -+ dp = (unsigned char *) firmware->data; -+ diffs = 0; -+ for (i = 0; i < firmware->size; i++) { -+ rc = vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, -+ VSC73XX_ICPU_SRAM, &curVal); -+ if (rc) { -+ dev_err(&spi->dev, "could not read microcode %d\n",rc); -+ goto out; -+ } -+ -+ if (curVal > 0xff) { -+ dev_err(&spi->dev, "bad val read: %04x : %02x %02x\n", -+ i, *dp, curVal); -+ rc = -EIO; -+ goto out; -+ } -+ -+ if ((curVal & 0xff) != *dp) { -+ diffs++; -+ dev_err(&spi->dev, "verify error: %04x : %02x %02x\n", -+ i, *dp, curVal); -+ -+ if (diffs > 4) -+ break; -+ } -+ dp++; -+ } -+ -+ if (diffs) { -+ dev_err(&spi->dev, "microcode verification failed\n"); -+ rc = -EIO; -+ goto out; -+ } -+ -+ dev_info(&spi->dev, "microcode uploaded\n"); -+ -+ rc = vsc7385_icpu_start(vsc); -+ -+ out: -+ release_firmware(firmware); -+ return rc; -+} -+ -+static int vsc7385_setup(struct vsc7385 *vsc) -+{ -+ struct vsc7385_platform_data *pdata = vsc->pdata; -+ u32 t; -+ int err; -+ -+ err = vsc7385_write_verify(vsc, VSC73XX_BLOCK_SYSTEM, 0, -+ VSC73XX_ICPU_CLOCK_DELAY, -+ VSC7385_CLOCK_DELAY, -+ VSC7385_CLOCK_DELAY_MASK, -+ VSC7385_CLOCK_DELAY); -+ if (err) -+ goto err; -+ -+ err = vsc7385_write_verify(vsc, VSC73XX_BLOCK_MAC, -+ VSC73XX_SUBBLOCK_PORT_MAC, VSC73XX_ADVPORTM, -+ VSC7385_ADVPORTM_INIT, -+ VSC7385_ADVPORTM_MASK, -+ VSC7385_ADVPORTM_INIT); -+ if (err) -+ goto err; -+ -+ err = vsc7385_write(vsc, VSC73XX_BLOCK_MAC, VSC73XX_SUBBLOCK_PORT_MAC, -+ VSC73XX_MAC_CFG, VSC7385_MAC_CFG_RESET); -+ if (err) -+ goto err; -+ -+ t = VSC73XX_MAC_CFG_INIT; -+ t |= VSC73XX_MAC_CFG_TX_IPG(pdata->mac_cfg.tx_ipg); -+ t |= VSC73XX_MAC_CFG_CLK_SEL(pdata->mac_cfg.clk_sel); -+ if (pdata->mac_cfg.bit2) -+ t |= VSC73XX_MAC_CFG_BIT2; -+ -+ err = vsc7385_write(vsc, VSC73XX_BLOCK_MAC, VSC73XX_SUBBLOCK_PORT_MAC, -+ VSC73XX_MAC_CFG, t); -+ if (err) -+ goto err; -+ -+ return 0; -+ -+ err: -+ return err; -+} -+ -+static int vsc7385_detect(struct vsc7385 *vsc) -+{ -+ struct spi_device *spi = vsc->spi; -+ u32 t; -+ u32 id; -+ u32 rev; -+ int err; -+ -+ err = vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, -+ VSC73XX_ICPU_MBOX_VAL, &t); -+ if (err) { -+ dev_err(&spi->dev, "unable to read mailbox, err=%d\n", err); -+ return err; -+ } -+ -+ if (t == 0xffffffff) { -+ dev_dbg(&spi->dev, "assert chip reset\n"); -+ if (vsc->pdata->reset) -+ vsc->pdata->reset(); -+ -+ } -+ -+ err = vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, -+ VSC73XX_ICPU_CHIPID, &t); -+ if (err) { -+ dev_err(&spi->dev, "unable to read chip id, err=%d\n", err); -+ return err; -+ } -+ -+ id = (t >> VSC73XX_ICPU_CHIPID_ID_SHIFT) & VSC73XX_ICPU_CHIPID_ID_MASK; -+ switch (id) { -+ case VSC73XX_ICPU_CHIPID_ID_7385: -+ case VSC73XX_ICPU_CHIPID_ID_7395: -+ break; -+ default: -+ dev_err(&spi->dev, "unsupported chip, id=%04x\n", id); -+ return -ENODEV; -+ } -+ -+ rev = (t >> VSC73XX_ICPU_CHIPID_REV_SHIFT) & -+ VSC73XX_ICPU_CHIPID_REV_MASK; -+ dev_info(&spi->dev, "VSC%04X (rev. %d) switch found \n", id, rev); -+ -+ return 0; -+} -+ -+static int __devinit vsc7385_probe(struct spi_device *spi) -+{ -+ struct vsc7385 *vsc; -+ struct vsc7385_platform_data *pdata; -+ int err; -+ -+ printk(KERN_INFO DRV_DESC " version " DRV_VERSION"\n"); -+ -+ pdata = spi->dev.platform_data; -+ if (!pdata) { -+ dev_err(&spi->dev, "no platform data specified\n"); -+ return-ENODEV; -+ } -+ -+ vsc = kzalloc(sizeof(*vsc), GFP_KERNEL); -+ if (!vsc) { -+ dev_err(&spi->dev, "no memory for private data\n"); -+ return-ENOMEM; -+ } -+ -+ mutex_init(&vsc->lock); -+ vsc->pdata = pdata; -+ vsc->spi = spi_dev_get(spi); -+ dev_set_drvdata(&spi->dev, vsc); -+ -+ spi->mode = SPI_MODE_0; -+ spi->bits_per_word = 8; -+ err = spi_setup(spi); -+ if (err) { -+ dev_err(&spi->dev, "spi_setup failed, err=%d \n", err); -+ goto err_drvdata; -+ } -+ -+ err = vsc7385_detect(vsc); -+ if (err) { -+ dev_err(&spi->dev, "no chip found, err=%d \n", err); -+ goto err_drvdata; -+ } -+ -+ err = vsc7385_upload_ucode(vsc); -+ if (err) -+ goto err_drvdata; -+ -+ err = vsc7385_setup(vsc); -+ if (err) -+ goto err_drvdata; -+ -+ return 0; -+ -+ err_drvdata: -+ dev_set_drvdata(&spi->dev, NULL); -+ kfree(vsc); -+ return err; -+} -+ -+static int __devexit vsc7385_remove(struct spi_device *spi) -+{ -+ struct vsc7385_data *vsc; -+ -+ vsc = dev_get_drvdata(&spi->dev); -+ dev_set_drvdata(&spi->dev, NULL); -+ kfree(vsc); -+ -+ return 0; -+} -+ -+static struct spi_driver vsc7385_driver = { -+ .driver = { -+ .name = DRV_NAME, -+ .bus = &spi_bus_type, -+ .owner = THIS_MODULE, -+ }, -+ .probe = vsc7385_probe, -+ .remove = __devexit_p(vsc7385_remove), -+}; -+ -+static int __init vsc7385_init(void) -+{ -+ return spi_register_driver(&vsc7385_driver); -+} -+module_init(vsc7385_init); -+ -+static void __exit vsc7385_exit(void) -+{ -+ spi_unregister_driver(&vsc7385_driver); -+} -+module_exit(vsc7385_exit); -+ -+MODULE_DESCRIPTION(DRV_DESC); -+MODULE_VERSION(DRV_VERSION); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_LICENSE("GPL v2"); -+ -diff -Nur linux-2.6.36.orig/drivers/usb/host/Kconfig linux-2.6.36/drivers/usb/host/Kconfig ---- linux-2.6.36.orig/drivers/usb/host/Kconfig 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/drivers/usb/host/Kconfig 2010-12-17 18:34:51.000000000 +0100 -@@ -112,6 +112,13 @@ - support both high speed and full speed devices, or high speed - devices only. - -+config USB_EHCI_AR71XX -+ bool "USB EHCI support for AR71xx" -+ depends on USB_EHCI_HCD && ATHEROS_AR71XX -+ default y -+ help -+ Support for Atheros AR71xx built-in EHCI controller -+ - config USB_EHCI_FSL - bool "Support for Freescale on-chip EHCI USB controller" - depends on USB_EHCI_HCD && FSL_SOC -@@ -225,6 +232,13 @@ - Enables support for the on-chip OHCI controller on - OMAP3 and later chips. - -+config USB_OHCI_AR71XX -+ bool "USB OHCI support for Atheros AR71xx" -+ depends on USB_OHCI_HCD && ATHEROS_AR71XX -+ default y -+ help -+ Support for Atheros AR71xx built-in OHCI controller -+ - config USB_OHCI_HCD_PPC_SOC - bool "OHCI support for on-chip PPC USB controller" - depends on USB_OHCI_HCD && (STB03xxx || PPC_MPC52xx) -diff -Nur linux-2.6.36.orig/drivers/usb/host/ehci-ar71xx.c linux-2.6.36/drivers/usb/host/ehci-ar71xx.c ---- linux-2.6.36.orig/drivers/usb/host/ehci-ar71xx.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/drivers/usb/host/ehci-ar71xx.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,242 @@ -+/* -+ * Bus Glue for Atheros AR71xx built-in EHCI controller. -+ * -+ * Copyright (C) 2008-2010 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * Copyright (C) 2007 Atheros Communications, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+extern int usb_disabled(void); -+ -+static int ehci_ar71xx_init(struct usb_hcd *hcd) -+{ -+ struct ehci_hcd *ehci = hcd_to_ehci(hcd); -+ int ret; -+ -+ ehci->caps = hcd->regs; -+ ehci->regs = hcd->regs + -+ HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); -+ ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); -+ -+ ehci->sbrn = 0x20; -+ ehci->has_synopsys_hc_bug = 1; -+ -+ ehci_reset(ehci); -+ -+ ret = ehci_init(hcd); -+ if (ret) -+ return ret; -+ -+ ehci_port_power(ehci, 0); -+ -+ return 0; -+} -+ -+static int ehci_ar91xx_init(struct usb_hcd *hcd) -+{ -+ struct ehci_hcd *ehci = hcd_to_ehci(hcd); -+ int ret; -+ -+ ehci->caps = hcd->regs + 0x100; -+ ehci->regs = hcd->regs + 0x100 + -+ HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); -+ ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); -+ -+ hcd->has_tt = 1; -+ ehci->sbrn = 0x20; -+ -+ ehci_reset(ehci); -+ -+ ret = ehci_init(hcd); -+ if (ret) -+ return ret; -+ -+ ehci_port_power(ehci, 0); -+ -+ return 0; -+} -+ -+static int ehci_ar71xx_probe(const struct hc_driver *driver, -+ struct usb_hcd **hcd_out, -+ struct platform_device *pdev) -+{ -+ struct usb_hcd *hcd; -+ struct resource *res; -+ int irq; -+ int ret; -+ -+ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); -+ if (!res) { -+ dev_dbg(&pdev->dev, "no IRQ specified for %s\n", -+ dev_name(&pdev->dev)); -+ return -ENODEV; -+ } -+ irq = res->start; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (!res) { -+ dev_dbg(&pdev->dev, "no base address specified for %s\n", -+ dev_name(&pdev->dev)); -+ return -ENODEV; -+ } -+ -+ hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev)); -+ if (!hcd) -+ return -ENOMEM; -+ -+ hcd->rsrc_start = res->start; -+ hcd->rsrc_len = res->end - res->start + 1; -+ -+ if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { -+ dev_dbg(&pdev->dev, "controller already in use\n"); -+ ret = -EBUSY; -+ goto err_put_hcd; -+ } -+ -+ hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); -+ if (!hcd->regs) { -+ dev_dbg(&pdev->dev, "error mapping memory\n"); -+ ret = -EFAULT; -+ goto err_release_region; -+ } -+ -+ ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED); -+ if (ret) -+ goto err_iounmap; -+ -+ return 0; -+ -+ err_iounmap: -+ iounmap(hcd->regs); -+ -+ err_release_region: -+ release_mem_region(hcd->rsrc_start, hcd->rsrc_len); -+ err_put_hcd: -+ usb_put_hcd(hcd); -+ return ret; -+} -+ -+static void ehci_ar71xx_remove(struct usb_hcd *hcd, -+ struct platform_device *pdev) -+{ -+ usb_remove_hcd(hcd); -+ iounmap(hcd->regs); -+ release_mem_region(hcd->rsrc_start, hcd->rsrc_len); -+ usb_put_hcd(hcd); -+} -+ -+static const struct hc_driver ehci_ar71xx_hc_driver = { -+ .description = hcd_name, -+ .product_desc = "Atheros AR71xx built-in EHCI controller", -+ .hcd_priv_size = sizeof(struct ehci_hcd), -+ -+ .irq = ehci_irq, -+ .flags = HCD_MEMORY | HCD_USB2, -+ -+ .reset = ehci_ar71xx_init, -+ .start = ehci_run, -+ .stop = ehci_stop, -+ .shutdown = ehci_shutdown, -+ -+ .urb_enqueue = ehci_urb_enqueue, -+ .urb_dequeue = ehci_urb_dequeue, -+ .endpoint_disable = ehci_endpoint_disable, -+ .endpoint_reset = ehci_endpoint_reset, -+ -+ .get_frame_number = ehci_get_frame, -+ -+ .hub_status_data = ehci_hub_status_data, -+ .hub_control = ehci_hub_control, -+#ifdef CONFIG_PM -+ .hub_suspend = ehci_hub_suspend, -+ .hub_resume = ehci_hub_resume, -+#endif -+ .relinquish_port = ehci_relinquish_port, -+ .port_handed_over = ehci_port_handed_over, -+ -+ .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, -+}; -+ -+static const struct hc_driver ehci_ar91xx_hc_driver = { -+ .description = hcd_name, -+ .product_desc = "Atheros AR91xx built-in EHCI controller", -+ .hcd_priv_size = sizeof(struct ehci_hcd), -+ .irq = ehci_irq, -+ .flags = HCD_MEMORY | HCD_USB2, -+ -+ .reset = ehci_ar91xx_init, -+ .start = ehci_run, -+ .stop = ehci_stop, -+ .shutdown = ehci_shutdown, -+ -+ .urb_enqueue = ehci_urb_enqueue, -+ .urb_dequeue = ehci_urb_dequeue, -+ .endpoint_disable = ehci_endpoint_disable, -+ .endpoint_reset = ehci_endpoint_reset, -+ -+ .get_frame_number = ehci_get_frame, -+ -+ .hub_status_data = ehci_hub_status_data, -+ .hub_control = ehci_hub_control, -+#ifdef CONFIG_PM -+ .hub_suspend = ehci_hub_suspend, -+ .hub_resume = ehci_hub_resume, -+#endif -+ .relinquish_port = ehci_relinquish_port, -+ .port_handed_over = ehci_port_handed_over, -+ -+ .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, -+}; -+ -+static int ehci_ar71xx_driver_probe(struct platform_device *pdev) -+{ -+ struct ar71xx_ehci_platform_data *pdata; -+ struct usb_hcd *hcd = NULL; -+ int ret; -+ -+ if (usb_disabled()) -+ return -ENODEV; -+ -+ pdata = pdev->dev.platform_data; -+ if (!pdata) { -+ dev_err(&pdev->dev, "no platform data specified for %s\n", -+ dev_name(&pdev->dev)); -+ return -ENODEV; -+ } -+ -+ if (pdata->is_ar91xx) -+ ret = ehci_ar71xx_probe(&ehci_ar91xx_hc_driver, &hcd, pdev); -+ else -+ ret = ehci_ar71xx_probe(&ehci_ar71xx_hc_driver, &hcd, pdev); -+ -+ return ret; -+} -+ -+static int ehci_ar71xx_driver_remove(struct platform_device *pdev) -+{ -+ struct usb_hcd *hcd = platform_get_drvdata(pdev); -+ -+ ehci_ar71xx_remove(hcd, pdev); -+ return 0; -+} -+ -+MODULE_ALIAS("platform:ar71xx-ehci"); -+ -+static struct platform_driver ehci_ar71xx_driver = { -+ .probe = ehci_ar71xx_driver_probe, -+ .remove = ehci_ar71xx_driver_remove, -+ .driver = { -+ .name = "ar71xx-ehci", -+ } -+}; -diff -Nur linux-2.6.36.orig/drivers/usb/host/ehci-hcd.c linux-2.6.36/drivers/usb/host/ehci-hcd.c ---- linux-2.6.36.orig/drivers/usb/host/ehci-hcd.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/drivers/usb/host/ehci-hcd.c 2010-12-17 18:34:51.000000000 +0100 -@@ -1197,6 +1197,11 @@ - #define PLATFORM_DRIVER ehci_atmel_driver - #endif - -+#ifdef CONFIG_USB_EHCI_AR71XX -+#include "ehci-ar71xx.c" -+#define PLATFORM_DRIVER ehci_ar71xx_driver -+#endif -+ - #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ - !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \ - !defined(XILINX_OF_PLATFORM_DRIVER) -diff -Nur linux-2.6.36.orig/drivers/usb/host/ohci-ar71xx.c linux-2.6.36/drivers/usb/host/ohci-ar71xx.c ---- linux-2.6.36.orig/drivers/usb/host/ohci-ar71xx.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/drivers/usb/host/ohci-ar71xx.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,165 @@ -+/* -+ * OHCI HCD (Host Controller Driver) for USB. -+ * -+ * Bus Glue for Atheros AR71xx built-in OHCI controller. -+ * -+ * Copyright (C) 2008 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * Copyright (C) 2007 Atheros Communications, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+extern int usb_disabled(void); -+ -+static int usb_hcd_ar71xx_probe(const struct hc_driver *driver, -+ struct platform_device *pdev) -+{ -+ struct usb_hcd *hcd; -+ struct resource *res; -+ int irq; -+ int ret; -+ -+ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); -+ if (!res) { -+ dev_dbg(&pdev->dev, "no IRQ specified for %s\n", -+ dev_name(&pdev->dev)); -+ return -ENODEV; -+ } -+ irq = res->start; -+ -+ hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev)); -+ if (!hcd) -+ return -ENOMEM; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (!res) { -+ dev_dbg(&pdev->dev, "no base address specified for %s\n", -+ dev_name(&pdev->dev)); -+ ret = -ENODEV; -+ goto err_put_hcd; -+ } -+ hcd->rsrc_start = res->start; -+ hcd->rsrc_len = res->end - res->start + 1; -+ -+ if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { -+ dev_dbg(&pdev->dev, "controller already in use\n"); -+ ret = -EBUSY; -+ goto err_put_hcd; -+ } -+ -+ hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); -+ if (!hcd->regs) { -+ dev_dbg(&pdev->dev, "error mapping memory\n"); -+ ret = -EFAULT; -+ goto err_release_region; -+ } -+ -+ ohci_hcd_init(hcd_to_ohci(hcd)); -+ -+ ret = usb_add_hcd(hcd, irq, IRQF_DISABLED); -+ if (ret) -+ goto err_stop_hcd; -+ -+ return 0; -+ -+ err_stop_hcd: -+ iounmap(hcd->regs); -+ err_release_region: -+ release_mem_region(hcd->rsrc_start, hcd->rsrc_len); -+ err_put_hcd: -+ usb_put_hcd(hcd); -+ return ret; -+} -+ -+void usb_hcd_ar71xx_remove(struct usb_hcd *hcd, struct platform_device *pdev) -+{ -+ usb_remove_hcd(hcd); -+ iounmap(hcd->regs); -+ release_mem_region(hcd->rsrc_start, hcd->rsrc_len); -+ usb_put_hcd(hcd); -+} -+ -+static int __devinit ohci_ar71xx_start(struct usb_hcd *hcd) -+{ -+ struct ohci_hcd *ohci = hcd_to_ohci(hcd); -+ int ret; -+ -+ ret = ohci_init(ohci); -+ if (ret < 0) -+ return ret; -+ -+ ret = ohci_run(ohci); -+ if (ret < 0) -+ goto err; -+ -+ return 0; -+ -+ err: -+ ohci_stop(hcd); -+ return ret; -+} -+ -+static const struct hc_driver ohci_ar71xx_hc_driver = { -+ .description = hcd_name, -+ .product_desc = "Atheros AR71xx built-in OHCI controller", -+ .hcd_priv_size = sizeof(struct ohci_hcd), -+ -+ .irq = ohci_irq, -+ .flags = HCD_USB11 | HCD_MEMORY, -+ -+ .start = ohci_ar71xx_start, -+ .stop = ohci_stop, -+ .shutdown = ohci_shutdown, -+ -+ .urb_enqueue = ohci_urb_enqueue, -+ .urb_dequeue = ohci_urb_dequeue, -+ .endpoint_disable = ohci_endpoint_disable, -+ -+ /* -+ * scheduling support -+ */ -+ .get_frame_number = ohci_get_frame, -+ -+ /* -+ * root hub support -+ */ -+ .hub_status_data = ohci_hub_status_data, -+ .hub_control = ohci_hub_control, -+ .start_port_reset = ohci_start_port_reset, -+}; -+ -+static int ohci_hcd_ar71xx_drv_probe(struct platform_device *pdev) -+{ -+ if (usb_disabled()) -+ return -ENODEV; -+ -+ return usb_hcd_ar71xx_probe(&ohci_ar71xx_hc_driver, pdev); -+} -+ -+static int ohci_hcd_ar71xx_drv_remove(struct platform_device *pdev) -+{ -+ struct usb_hcd *hcd = platform_get_drvdata(pdev); -+ -+ usb_hcd_ar71xx_remove(hcd, pdev); -+ return 0; -+} -+ -+MODULE_ALIAS("platform:ar71xx-ohci"); -+ -+static struct platform_driver ohci_hcd_ar71xx_driver = { -+ .probe = ohci_hcd_ar71xx_drv_probe, -+ .remove = ohci_hcd_ar71xx_drv_remove, -+ .shutdown = usb_hcd_platform_shutdown, -+ .driver = { -+ .name = "ar71xx-ohci", -+ .owner = THIS_MODULE, -+ }, -+}; -diff -Nur linux-2.6.36.orig/drivers/usb/host/ohci-hcd.c linux-2.6.36/drivers/usb/host/ohci-hcd.c ---- linux-2.6.36.orig/drivers/usb/host/ohci-hcd.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/drivers/usb/host/ohci-hcd.c 2010-12-17 18:34:51.000000000 +0100 -@@ -1100,6 +1100,11 @@ - #define PLATFORM_DRIVER ohci_hcd_jz4740_driver - #endif - -+#ifdef CONFIG_USB_OHCI_AR71XX -+#include "ohci-ar71xx.c" -+#define PLATFORM_DRIVER ohci_hcd_ar71xx_driver -+#endif -+ - #if !defined(PCI_DRIVER) && \ - !defined(PLATFORM_DRIVER) && \ - !defined(OMAP1_PLATFORM_DRIVER) && \ -diff -Nur linux-2.6.36.orig/drivers/watchdog/Kconfig linux-2.6.36/drivers/watchdog/Kconfig ---- linux-2.6.36.orig/drivers/watchdog/Kconfig 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/drivers/watchdog/Kconfig 2010-12-17 18:34:51.000000000 +0100 -@@ -916,6 +916,13 @@ - from the first interrupt, it is then only poked when the - device is written. - -+config AR71XX_WDT -+ tristate "Atheros AR71xx Watchdog Timer" -+ depends on ATHEROS_AR71XX -+ help -+ Hardware driver for the built-in watchdog timer on the Atheros -+ AR71xx SoCs. -+ - # PARISC Architecture - - # POWERPC Architecture -diff -Nur linux-2.6.36.orig/drivers/watchdog/Makefile linux-2.6.36/drivers/watchdog/Makefile ---- linux-2.6.36.orig/drivers/watchdog/Makefile 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/drivers/watchdog/Makefile 2010-12-17 18:34:51.000000000 +0100 -@@ -116,6 +116,7 @@ - obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o - obj-$(CONFIG_AR7_WDT) += ar7_wdt.o - obj-$(CONFIG_TXX9_WDT) += txx9wdt.o -+obj-$(CONFIG_AR71XX_WDT) += ar71xx_wdt.o - obj-$(CONFIG_OCTEON_WDT) += octeon-wdt.o - octeon-wdt-y := octeon-wdt-main.o octeon-wdt-nmi.o - -diff -Nur linux-2.6.36.orig/drivers/watchdog/ar71xx_wdt.c linux-2.6.36/drivers/watchdog/ar71xx_wdt.c ---- linux-2.6.36.orig/drivers/watchdog/ar71xx_wdt.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/drivers/watchdog/ar71xx_wdt.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,270 @@ -+/* -+ * Driver for the Atheros AR71xx SoC's built-in hardware watchdog timer. -+ * -+ * Copyright (C) 2008 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This driver was based on: drivers/watchdog/ixp4xx_wdt.c -+ * Author: Deepak Saxena -+ * Copyright 2004 (c) MontaVista, Software, Inc. -+ * -+ * which again was based on sa1100 driver, -+ * Copyright (C) 2000 Oleg Drokin -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#define DRV_NAME "ar71xx-wdt" -+#define DRV_DESC "Atheros AR71xx hardware watchdog driver" -+#define DRV_VERSION "0.1.0" -+ -+#define WDT_TIMEOUT 15 /* seconds */ -+ -+static int nowayout = WATCHDOG_NOWAYOUT; -+ -+#ifdef CONFIG_WATCHDOG_NOWAYOUT -+module_param(nowayout, int, 0); -+MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started " -+ "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); -+#endif -+ -+static unsigned long wdt_flags; -+ -+#define WDT_FLAGS_BUSY 0 -+#define WDT_FLAGS_EXPECT_CLOSE 1 -+ -+static int wdt_timeout = WDT_TIMEOUT; -+static int boot_status; -+static int max_timeout; -+ -+static void inline ar71xx_wdt_keepalive(void) -+{ -+ ar71xx_reset_wr(AR71XX_RESET_REG_WDOG, ar71xx_ahb_freq * wdt_timeout); -+} -+ -+static void inline ar71xx_wdt_enable(void) -+{ -+ printk(KERN_DEBUG DRV_NAME ": enabling watchdog timer\n"); -+ ar71xx_wdt_keepalive(); -+ ar71xx_reset_wr(AR71XX_RESET_REG_WDOG_CTRL, WDOG_CTRL_ACTION_FCR); -+} -+ -+static void inline ar71xx_wdt_disable(void) -+{ -+ printk(KERN_DEBUG DRV_NAME ": disabling watchdog timer\n"); -+ ar71xx_reset_wr(AR71XX_RESET_REG_WDOG_CTRL, WDOG_CTRL_ACTION_NONE); -+} -+ -+static int ar71xx_wdt_set_timeout(int val) -+{ -+ if (val < 1 || val > max_timeout) -+ return -EINVAL; -+ -+ wdt_timeout = val; -+ ar71xx_wdt_keepalive(); -+ -+ printk(KERN_DEBUG DRV_NAME ": timeout=%d secs\n", wdt_timeout); -+ -+ return 0; -+} -+ -+static int ar71xx_wdt_open(struct inode *inode, struct file *file) -+{ -+ if (test_and_set_bit(WDT_FLAGS_BUSY, &wdt_flags)) -+ return -EBUSY; -+ -+ clear_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags); -+ -+ ar71xx_wdt_enable(); -+ -+ return nonseekable_open(inode, file); -+} -+ -+static int ar71xx_wdt_release(struct inode *inode, struct file *file) -+{ -+ if (test_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags)) { -+ ar71xx_wdt_disable(); -+ } else { -+ printk(KERN_CRIT DRV_NAME ": device closed unexpectedly, " -+ "watchdog timer will not stop!\n"); -+ } -+ -+ clear_bit(WDT_FLAGS_BUSY, &wdt_flags); -+ clear_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags); -+ -+ return 0; -+} -+ -+static ssize_t ar71xx_wdt_write(struct file *file, const char *data, -+ size_t len, loff_t *ppos) -+{ -+ if (len) { -+ if (!nowayout) { -+ size_t i; -+ -+ clear_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags); -+ -+ for (i = 0; i != len; i++) { -+ char c; -+ -+ if (get_user(c, data + i)) -+ return -EFAULT; -+ -+ if (c == 'V') -+ set_bit(WDT_FLAGS_EXPECT_CLOSE, -+ &wdt_flags); -+ } -+ } -+ -+ ar71xx_wdt_keepalive(); -+ } -+ -+ return len; -+} -+ -+static struct watchdog_info ar71xx_wdt_info = { -+ .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | -+ WDIOF_MAGICCLOSE | WDIOF_CARDRESET, -+ .firmware_version = 0, -+ .identity = "AR71XX watchdog", -+}; -+ -+static int ar71xx_wdt_ioctl(struct inode *inode, struct file *file, -+ unsigned int cmd, unsigned long arg) -+{ -+ int t; -+ int ret; -+ -+ switch (cmd) { -+ case WDIOC_GETSUPPORT: -+ ret = copy_to_user((struct watchdog_info *)arg, -+ &ar71xx_wdt_info, -+ sizeof(&ar71xx_wdt_info)) ? -EFAULT : 0; -+ break; -+ -+ case WDIOC_GETSTATUS: -+ ret = put_user(0, (int *)arg) ? -EFAULT : 0; -+ break; -+ -+ case WDIOC_GETBOOTSTATUS: -+ ret = put_user(boot_status, (int *)arg) ? -EFAULT : 0; -+ break; -+ -+ case WDIOC_KEEPALIVE: -+ ar71xx_wdt_keepalive(); -+ ret = 0; -+ break; -+ -+ case WDIOC_SETTIMEOUT: -+ ret = get_user(t, (int *)arg) ? -EFAULT : 0; -+ if (ret) -+ break; -+ -+ ret = ar71xx_wdt_set_timeout(t); -+ if (ret) -+ break; -+ -+ /* fallthrough */ -+ case WDIOC_GETTIMEOUT: -+ ret = put_user(wdt_timeout, (int *)arg) ? -EFAULT : 0; -+ break; -+ -+ default: -+ ret = -ENOTTY; -+ break; -+ } -+ -+ return ret; -+} -+ -+static const struct file_operations ar71xx_wdt_fops = { -+ .owner = THIS_MODULE, -+ .write = ar71xx_wdt_write, -+ .ioctl = ar71xx_wdt_ioctl, -+ .open = ar71xx_wdt_open, -+ .release = ar71xx_wdt_release, -+}; -+ -+static struct miscdevice ar71xx_wdt_miscdev = { -+ .minor = WATCHDOG_MINOR, -+ .name = "watchdog", -+ .fops = &ar71xx_wdt_fops, -+}; -+ -+static int __devinit ar71xx_wdt_probe(struct platform_device *pdev) -+{ -+ int ret; -+ -+ max_timeout = (0xfffffffful / ar71xx_ahb_freq); -+ wdt_timeout = (max_timeout < WDT_TIMEOUT) ? max_timeout : WDT_TIMEOUT; -+ -+ boot_status = -+ (ar71xx_reset_rr(AR71XX_RESET_REG_WDOG_CTRL) & WDOG_CTRL_LAST_RESET) ? -+ WDIOF_CARDRESET : 0; -+ -+ ret = misc_register(&ar71xx_wdt_miscdev); -+ if (ret) -+ goto err_out; -+ -+ printk(KERN_INFO DRV_DESC " version " DRV_VERSION "\n"); -+ -+ printk(KERN_DEBUG DRV_NAME ": timeout=%d secs (max=%d)\n", -+ wdt_timeout, max_timeout); -+ -+ return 0; -+ -+err_out: -+ return ret; -+} -+ -+static int __devexit ar71xx_wdt_remove(struct platform_device *pdev) -+{ -+ misc_deregister(&ar71xx_wdt_miscdev); -+ return 0; -+} -+ -+static struct platform_driver ar71xx_wdt_driver = { -+ .probe = ar71xx_wdt_probe, -+ .remove = __devexit_p(ar71xx_wdt_remove), -+ .driver = { -+ .name = DRV_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init ar71xx_wdt_init(void) -+{ -+ return platform_driver_register(&ar71xx_wdt_driver); -+} -+module_init(ar71xx_wdt_init); -+ -+static void __exit ar71xx_wdt_exit(void) -+{ -+ platform_driver_unregister(&ar71xx_wdt_driver); -+} -+module_exit(ar71xx_wdt_exit); -+ -+MODULE_DESCRIPTION(DRV_DESC); -+MODULE_VERSION(DRV_VERSION); -+MODULE_AUTHOR("Gabor Juhos -- * Copyright (c) 2009 Imre Kaloz -+ * ath9k platform data defines - * -- * Permission to use, copy, modify, and/or distribute this software for any -- * purpose with or without fee is hereby granted, provided that the above -- * copyright notice and this permission notice appear in all copies. -+ * Copyright (C) 2008 Gabor Juhos - * -- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. - */ - - #ifndef _LINUX_ATH9K_PLATFORM_H -@@ -23,6 +15,9 @@ - - struct ath9k_platform_data { - u16 eeprom_data[ATH9K_PLAT_EEP_MAX_WORDS]; -+ u8 *macaddr; -+ -+ unsigned long quirk_wndr3700:1; - }; - - #endif /* _LINUX_ATH9K_PLATFORM_H */ -diff -Nur linux-2.6.36.orig/include/linux/gpio_buttons.h linux-2.6.36/include/linux/gpio_buttons.h ---- linux-2.6.36.orig/include/linux/gpio_buttons.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/include/linux/gpio_buttons.h 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,33 @@ -+/* -+ * Definitions for the GPIO buttons interface driver -+ * -+ * Copyright (C) 2007-2010 Gabor Juhos -+ * -+ * This file was based on: /include/linux/gpio_keys.h -+ * The original gpio_keys.h seems not to have a license. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ */ -+ -+#ifndef _GPIO_BUTTONS_H_ -+#define _GPIO_BUTTONS_H_ -+ -+struct gpio_button { -+ int gpio; /* GPIO line number */ -+ int active_low; -+ char *desc; /* button description */ -+ int type; /* input event type (EV_KEY, EV_SW) */ -+ int code; /* input event code (KEY_*, SW_*) */ -+ int threshold; /* count threshold */ -+}; -+ -+struct gpio_buttons_platform_data { -+ struct gpio_button *buttons; -+ int nbuttons; /* number of buttons */ -+ int poll_interval; /* polling interval */ -+}; -+ -+#endif /* _GPIO_BUTTONS_H_ */ -diff -Nur linux-2.6.36.orig/include/linux/gpio_dev.h linux-2.6.36/include/linux/gpio_dev.h ---- linux-2.6.36.orig/include/linux/gpio_dev.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/include/linux/gpio_dev.h 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,11 @@ -+#ifndef _GPIODEV_H__ -+#define _GPIODEV_H__ -+ -+#define IOC_GPIODEV_MAGIC 'B' -+#define GPIO_GET _IO(IOC_GPIODEV_MAGIC, 10) -+#define GPIO_SET _IO(IOC_GPIODEV_MAGIC, 11) -+#define GPIO_CLEAR _IO(IOC_GPIODEV_MAGIC, 12) -+#define GPIO_DIR_IN _IO(IOC_GPIODEV_MAGIC, 13) -+#define GPIO_DIR_OUT _IO(IOC_GPIODEV_MAGIC, 14) -+ -+#endif -diff -Nur linux-2.6.36.orig/include/linux/netdevice.h linux-2.6.36/include/linux/netdevice.h ---- linux-2.6.36.orig/include/linux/netdevice.h 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/include/linux/netdevice.h 2010-12-17 18:34:51.000000000 +0100 -@@ -949,6 +949,7 @@ - void *ax25_ptr; /* AX.25 specific data */ - struct wireless_dev *ieee80211_ptr; /* IEEE 802.11 specific data, - assign before registering */ -+ void *phy_ptr; /* PHY device specific data */ - - /* - * Cache line mostly used on receive path (including eth_type_trans()) -diff -Nur linux-2.6.36.orig/include/linux/nxp_74hc153.h linux-2.6.36/include/linux/nxp_74hc153.h ---- linux-2.6.36.orig/include/linux/nxp_74hc153.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/include/linux/nxp_74hc153.h 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,24 @@ -+/* -+ * NXP 74HC153 - Dual 4-input multiplexer defines -+ * -+ * Copyright (C) 2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#ifndef _NXP_74HC153_H -+#define _NXP_74HC153_H -+ -+#define NXP_74HC153_DRIVER_NAME "nxp-74hc153" -+ -+struct nxp_74hc153_platform_data { -+ unsigned gpio_base; -+ unsigned gpio_pin_s0; -+ unsigned gpio_pin_s1; -+ unsigned gpio_pin_1y; -+ unsigned gpio_pin_2y; -+}; -+ -+#endif /* _NXP_74HC153_H */ -diff -Nur linux-2.6.36.orig/include/linux/phy.h linux-2.6.36/include/linux/phy.h ---- linux-2.6.36.orig/include/linux/phy.h 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/include/linux/phy.h 2010-12-17 18:34:51.000000000 +0100 -@@ -332,6 +332,20 @@ - void (*adjust_link)(struct net_device *dev); - - void (*adjust_state)(struct net_device *dev); -+ -+ /* -+ * By default these point to the original functions -+ * with the same name. adding them to the phy_device -+ * allows the phy driver to override them for packet -+ * mangling if the ethernet driver supports it -+ * This is required to support some really horrible -+ * switches such as the Marvell 88E6060 -+ */ -+ int (*netif_receive_skb)(struct sk_buff *skb); -+ int (*netif_rx)(struct sk_buff *skb); -+ -+ /* alignment offset for packets */ -+ int pkt_align; - }; - #define to_phy_device(d) container_of(d, struct phy_device, dev) - -@@ -519,6 +533,7 @@ - void phy_stop_machine(struct phy_device *phydev); - int phy_ethtool_sset(struct phy_device *phydev, struct ethtool_cmd *cmd); - int phy_ethtool_gset(struct phy_device *phydev, struct ethtool_cmd *cmd); -+int phy_ethtool_ioctl(struct phy_device *phydev, void *useraddr); - int phy_mii_ioctl(struct phy_device *phydev, - struct ifreq *ifr, int cmd); - int phy_start_interrupts(struct phy_device *phydev); -diff -Nur linux-2.6.36.orig/include/linux/spi/vsc7385.h linux-2.6.36/include/linux/spi/vsc7385.h ---- linux-2.6.36.orig/include/linux/spi/vsc7385.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/include/linux/spi/vsc7385.h 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,19 @@ -+/* -+ * Platform data definition for the Vitesse VSC7385 ethernet switch driver -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+struct vsc7385_platform_data { -+ void (* reset)(void); -+ char *ucode_name; -+ struct { -+ u32 tx_ipg:5; -+ u32 bit2:1; -+ u32 clk_sel:3; -+ } mac_cfg; -+}; -diff -Nur linux-2.6.36.orig/net/dsa/ar7240.c linux-2.6.36/net/dsa/ar7240.c ---- linux-2.6.36.orig/net/dsa/ar7240.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/net/dsa/ar7240.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,736 @@ -+/* -+ * DSA driver for the built-in ethernet switch of the Atheros AR7240 SoC -+ * Copyright (c) 2010 Gabor Juhos -+ * -+ * This file was based on: -+ * net/dsa/mv88e6060.c - Driver for Marvell 88e6060 switch chips -+ * Copyright (c) 2008 Marvell Semiconductor -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "dsa_priv.h" -+ -+#define BITM(_count) (BIT(_count) - 1) -+ -+#define AR7240_REG_MASK_CTRL 0x00 -+#define AR7240_MASK_CTRL_REVISION_M BITM(8) -+#define AR7240_MASK_CTRL_VERSION_M BITM(8) -+#define AR7240_MASK_CTRL_VERSION_S 8 -+#define AR7240_MASK_CTRL_SOFT_RESET BIT(31) -+ -+#define AR7240_REG_MAC_ADDR0 0x20 -+#define AR7240_REG_MAC_ADDR1 0x24 -+ -+#define AR7240_REG_FLOOD_MASK 0x2c -+#define AR7240_FLOOD_MASK_BROAD_TO_CPU BIT(26) -+ -+#define AR7240_REG_GLOBAL_CTRL 0x30 -+#define AR7240_GLOBAL_CTRL_MTU_M BITM(12) -+ -+#define AR7240_REG_AT_CTRL 0x5c -+#define AR7240_AT_CTRL_ARP_EN BIT(20) -+ -+#define AR7240_REG_TAG_PRIORITY 0x70 -+ -+#define AR7240_REG_SERVICE_TAG 0x74 -+#define AR7240_SERVICE_TAG_M BITM(16) -+ -+#define AR7240_REG_CPU_PORT 0x78 -+#define AR7240_MIRROR_PORT_S 4 -+#define AR7240_CPU_PORT_EN BIT(8) -+ -+#define AR7240_REG_MIB_FUNCTION0 0x80 -+#define AR7240_MIB_TIMER_M BITM(16) -+#define AR7240_MIB_AT_HALF_EN BIT(16) -+#define AR7240_MIB_BUSY BIT(17) -+#define AR7240_MIB_FUNC_S 24 -+#define AR7240_MIB_FUNC_NO_OP 0x0 -+#define AR7240_MIB_FUNC_FLUSH 0x1 -+#define AR7240_MIB_FUNC_CAPTURE 0x3 -+ -+#define AR7240_REG_MDIO_CTRL 0x98 -+#define AR7240_MDIO_CTRL_DATA_M BITM(16) -+#define AR7240_MDIO_CTRL_REG_ADDR_S 16 -+#define AR7240_MDIO_CTRL_PHY_ADDR_S 21 -+#define AR7240_MDIO_CTRL_CMD_WRITE 0 -+#define AR7240_MDIO_CTRL_CMD_READ BIT(27) -+#define AR7240_MDIO_CTRL_MASTER_EN BIT(30) -+#define AR7240_MDIO_CTRL_BUSY BIT(31) -+ -+#define AR7240_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100) -+ -+#define AR7240_REG_PORT_STATUS(_port) (AR7240_REG_PORT_BASE((_port)) + 0x00) -+#define AR7240_PORT_STATUS_SPEED_M BITM(2) -+#define AR7240_PORT_STATUS_SPEED_10 0 -+#define AR7240_PORT_STATUS_SPEED_100 1 -+#define AR7240_PORT_STATUS_SPEED_1000 2 -+#define AR7240_PORT_STATUS_TXMAC BIT(2) -+#define AR7240_PORT_STATUS_RXMAC BIT(3) -+#define AR7240_PORT_STATUS_TXFLOW BIT(4) -+#define AR7240_PORT_STATUS_RXFLOW BIT(5) -+#define AR7240_PORT_STATUS_DUPLEX BIT(6) -+#define AR7240_PORT_STATUS_LINK_UP BIT(8) -+#define AR7240_PORT_STATUS_LINK_AUTO BIT(9) -+#define AR7240_PORT_STATUS_LINK_PAUSE BIT(10) -+ -+#define AR7240_REG_PORT_CTRL(_port) (AR7240_REG_PORT_BASE((_port)) + 0x04) -+#define AR7240_PORT_CTRL_STATE_M BITM(3) -+#define AR7240_PORT_CTRL_STATE_DISABLED 0 -+#define AR7240_PORT_CTRL_STATE_BLOCK 1 -+#define AR7240_PORT_CTRL_STATE_LISTEN 2 -+#define AR7240_PORT_CTRL_STATE_LEARN 3 -+#define AR7240_PORT_CTRL_STATE_FORWARD 4 -+#define AR7240_PORT_CTRL_LEARN_LOCK BIT(7) -+#define AR7240_PORT_CTRL_VLAN_MODE_S 8 -+#define AR7240_PORT_CTRL_VLAN_MODE_KEEP 0 -+#define AR7240_PORT_CTRL_VLAN_MODE_STRIP 1 -+#define AR7240_PORT_CTRL_VLAN_MODE_ADD 2 -+#define AR7240_PORT_CTRL_VLAN_MODE_DOUBLE_TAG 3 -+#define AR7240_PORT_CTRL_IGMP_SNOOP BIT(10) -+#define AR7240_PORT_CTRL_HEADER BIT(11) -+#define AR7240_PORT_CTRL_MAC_LOOP BIT(12) -+#define AR7240_PORT_CTRL_SINGLE_VLAN BIT(13) -+#define AR7240_PORT_CTRL_LEARN BIT(14) -+#define AR7240_PORT_CTRL_DOUBLE_TAG BIT(15) -+#define AR7240_PORT_CTRL_MIRROR_TX BIT(16) -+#define AR7240_PORT_CTRL_MIRROR_RX BIT(17) -+ -+#define AR7240_REG_PORT_VLAN(_port) (AR7240_REG_PORT_BASE((_port)) + 0x08) -+ -+#define AR7240_PORT_VLAN_DEFAULT_ID_S 0 -+#define AR7240_PORT_VLAN_DEST_PORTS_S 16 -+ -+#define AR7240_REG_STATS_BASE(_port) (0x20000 + (_port) * 0x100) -+ -+#define AR7240_STATS_RXBROAD 0x00 -+#define AR7240_STATS_RXPAUSE 0x04 -+#define AR7240_STATS_RXMULTI 0x08 -+#define AR7240_STATS_RXFCSERR 0x0c -+#define AR7240_STATS_RXALIGNERR 0x10 -+#define AR7240_STATS_RXRUNT 0x14 -+#define AR7240_STATS_RXFRAGMENT 0x18 -+#define AR7240_STATS_RX64BYTE 0x1c -+#define AR7240_STATS_RX128BYTE 0x20 -+#define AR7240_STATS_RX256BYTE 0x24 -+#define AR7240_STATS_RX512BYTE 0x28 -+#define AR7240_STATS_RX1024BYTE 0x2c -+#define AR7240_STATS_RX1518BYTE 0x30 -+#define AR7240_STATS_RXMAXBYTE 0x34 -+#define AR7240_STATS_RXTOOLONG 0x38 -+#define AR7240_STATS_RXGOODBYTE 0x3c -+#define AR7240_STATS_RXBADBYTE 0x44 -+#define AR7240_STATS_RXOVERFLOW 0x4c -+#define AR7240_STATS_FILTERED 0x50 -+#define AR7240_STATS_TXBROAD 0x54 -+#define AR7240_STATS_TXPAUSE 0x58 -+#define AR7240_STATS_TXMULTI 0x5c -+#define AR7240_STATS_TXUNDERRUN 0x60 -+#define AR7240_STATS_TX64BYTE 0x64 -+#define AR7240_STATS_TX128BYTE 0x68 -+#define AR7240_STATS_TX256BYTE 0x6c -+#define AR7240_STATS_TX512BYTE 0x70 -+#define AR7240_STATS_TX1024BYTE 0x74 -+#define AR7240_STATS_TX1518BYTE 0x78 -+#define AR7240_STATS_TXMAXBYTE 0x7c -+#define AR7240_STATS_TXOVERSIZE 0x80 -+#define AR7240_STATS_TXBYTE 0x84 -+#define AR7240_STATS_TXCOLLISION 0x8c -+#define AR7240_STATS_TXABORTCOL 0x90 -+#define AR7240_STATS_TXMULTICOL 0x94 -+#define AR7240_STATS_TXSINGLECOL 0x98 -+#define AR7240_STATS_TXEXCDEFER 0x9c -+#define AR7240_STATS_TXDEFER 0xa0 -+#define AR7240_STATS_TXLATECOL 0xa4 -+ -+#define AR7240_PORT_CPU 0 -+#define AR7240_NUM_PORTS 6 -+#define AR7240_NUM_PHYS 5 -+ -+#define AR7240_PHY_ID1 0x004d -+#define AR7240_PHY_ID2 0xd041 -+ -+#define AR7240_PORT_MASK(_port) BIT((_port)) -+#define AR7240_PORT_MASK_ALL BITM(AR7240_NUM_PORTS) -+#define AR7240_PORT_MASK_BUT(_port) (AR7240_PORT_MASK_ALL & ~BIT((_port))) -+ -+struct ar7240sw { -+ struct mii_bus *mii_bus; -+ struct mutex reg_mutex; -+ struct mutex stats_mutex; -+}; -+ -+struct ar7240sw_hw_stat { -+ char string[ETH_GSTRING_LEN]; -+ int sizeof_stat; -+ int reg; -+}; -+ -+static inline struct ar7240sw *dsa_to_ar7240sw(struct dsa_switch *ds) -+{ -+ return (struct ar7240sw *)(ds + 1); -+} -+ -+static inline void ar7240sw_init(struct ar7240sw *as, struct mii_bus *mii) -+{ -+ as->mii_bus = mii; -+ mutex_init(&as->reg_mutex); -+ mutex_init(&as->stats_mutex); -+} -+ -+static inline u16 mk_phy_addr(u32 reg) -+{ -+ return (0x17 & ((reg >> 4) | 0x10)); -+} -+ -+static inline u16 mk_phy_reg(u32 reg) -+{ -+ return ((reg << 1) & 0x1e); -+} -+ -+static inline u16 mk_high_addr(u32 reg) -+{ -+ return ((reg >> 7) & 0x1ff); -+} -+ -+static u32 __ar7240sw_reg_read(struct ar7240sw *as, u32 reg) -+{ -+ struct mii_bus *mii = as->mii_bus; -+ u16 phy_addr; -+ u16 phy_reg; -+ u32 hi, lo; -+ -+ reg = (reg & 0xfffffffc) >> 2; -+ -+ mdiobus_write(mii, 0x1f, 0x10, mk_high_addr(reg)); -+ -+ phy_addr = mk_phy_addr(reg); -+ phy_reg = mk_phy_reg(reg); -+ -+ lo = (u32) mdiobus_read(mii, phy_addr, phy_reg); -+ hi = (u32) mdiobus_read(mii, phy_addr, phy_reg + 1); -+ -+ return ((hi << 16) | lo); -+} -+ -+static void __ar7240sw_reg_write(struct ar7240sw *as, u32 reg, u32 val) -+{ -+ struct mii_bus *mii = as->mii_bus; -+ u16 phy_addr; -+ u16 phy_reg; -+ -+ reg = (reg & 0xfffffffc) >> 2; -+ -+ mdiobus_write(mii, 0x1f, 0x10, mk_high_addr(reg)); -+ -+ phy_addr = mk_phy_addr(reg); -+ phy_reg = mk_phy_reg(reg); -+ -+ mdiobus_write(mii, phy_addr, phy_reg + 1, (val >> 16)); -+ mdiobus_write(mii, phy_addr, phy_reg, (val & 0xffff)); -+} -+ -+static u32 ar7240sw_reg_read(struct ar7240sw *as, u32 reg_addr) -+{ -+ u32 ret; -+ -+ mutex_lock(&as->reg_mutex); -+ ret = __ar7240sw_reg_read(as, reg_addr); -+ mutex_unlock(&as->reg_mutex); -+ -+ return ret; -+} -+ -+static void ar7240sw_reg_write(struct ar7240sw *as, u32 reg_addr, u32 reg_val) -+{ -+ mutex_lock(&as->reg_mutex); -+ __ar7240sw_reg_write(as, reg_addr, reg_val); -+ mutex_unlock(&as->reg_mutex); -+} -+ -+static u32 ar7240sw_reg_rmw(struct ar7240sw *as, u32 reg, u32 mask, u32 val) -+{ -+ u32 t; -+ -+ mutex_lock(&as->reg_mutex); -+ t = __ar7240sw_reg_read(as, reg); -+ t &= ~mask; -+ t |= val; -+ __ar7240sw_reg_write(as, reg, t); -+ mutex_unlock(&as->reg_mutex); -+ -+ return t; -+} -+ -+static void ar7240sw_reg_set(struct ar7240sw *as, u32 reg, u32 val) -+{ -+ u32 t; -+ -+ mutex_lock(&as->reg_mutex); -+ t = __ar7240sw_reg_read(as, reg); -+ t |= val; -+ __ar7240sw_reg_write(as, reg, t); -+ mutex_unlock(&as->reg_mutex); -+} -+ -+static int ar7240sw_reg_wait(struct ar7240sw *as, u32 reg, u32 mask, u32 val, -+ unsigned timeout) -+{ -+ int i; -+ -+ for (i = 0; i < timeout; i++) { -+ u32 t; -+ -+ t = ar7240sw_reg_read(as, reg); -+ if ((t & mask) == val) -+ return 0; -+ -+ msleep(1); -+ } -+ -+ return -ETIMEDOUT; -+} -+ -+static u16 ar7240sw_phy_read(struct ar7240sw *as, unsigned phy_addr, -+ unsigned reg_addr) -+{ -+ u32 t; -+ int err; -+ -+ if (phy_addr >= AR7240_NUM_PHYS) -+ return 0xffff; -+ -+ t = (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) | -+ (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) | -+ AR7240_MDIO_CTRL_MASTER_EN | -+ AR7240_MDIO_CTRL_BUSY | -+ AR7240_MDIO_CTRL_CMD_READ; -+ -+ ar7240sw_reg_write(as, AR7240_REG_MDIO_CTRL, t); -+ err = ar7240sw_reg_wait(as, AR7240_REG_MDIO_CTRL, -+ AR7240_MDIO_CTRL_BUSY, 0, 5); -+ if (err) -+ return 0xffff; -+ -+ t = ar7240sw_reg_read(as, AR7240_REG_MDIO_CTRL); -+ return (t & AR7240_MDIO_CTRL_DATA_M); -+} -+ -+static int ar7240sw_phy_write(struct ar7240sw *as, unsigned phy_addr, -+ unsigned reg_addr, u16 reg_val) -+{ -+ u32 t; -+ int ret; -+ -+ if (phy_addr >= AR7240_NUM_PHYS) -+ return -EINVAL; -+ -+ t = (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) | -+ (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) | -+ AR7240_MDIO_CTRL_MASTER_EN | -+ AR7240_MDIO_CTRL_BUSY | -+ AR7240_MDIO_CTRL_CMD_WRITE | -+ reg_val; -+ -+ ar7240sw_reg_write(as, AR7240_REG_MDIO_CTRL, t); -+ ret = ar7240sw_reg_wait(as, AR7240_REG_MDIO_CTRL, -+ AR7240_MDIO_CTRL_BUSY, 0, 5); -+ return ret; -+} -+ -+static int ar7240sw_capture_stats(struct ar7240sw *as) -+{ -+ int ret; -+ -+ /* Capture the hardware statistics for all ports */ -+ ar7240sw_reg_write(as, AR7240_REG_MIB_FUNCTION0, -+ (AR7240_MIB_FUNC_CAPTURE << AR7240_MIB_FUNC_S)); -+ -+ /* Wait for the capturing to complete. */ -+ ret = ar7240sw_reg_wait(as, AR7240_REG_MIB_FUNCTION0, -+ AR7240_MIB_BUSY, 0, 10); -+ return ret; -+} -+ -+static void ar7240sw_disable_port(struct ar7240sw *as, unsigned port) -+{ -+ ar7240sw_reg_write(as, AR7240_REG_PORT_CTRL(port), -+ AR7240_PORT_CTRL_STATE_DISABLED); -+} -+ -+static int ar7240sw_reset(struct ar7240sw *as) -+{ -+ int ret; -+ int i; -+ -+ /* Set all ports to disabled state. */ -+ for (i = 0; i < AR7240_NUM_PORTS; i++) -+ ar7240sw_disable_port(as, i); -+ -+ /* Wait for transmit queues to drain. */ -+ msleep(2); -+ -+ /* Reset the switch. */ -+ ar7240sw_reg_write(as, AR7240_REG_MASK_CTRL, -+ AR7240_MASK_CTRL_SOFT_RESET); -+ -+ ret = ar7240sw_reg_wait(as, AR7240_REG_MASK_CTRL, -+ AR7240_MASK_CTRL_SOFT_RESET, 0, 1000); -+ return ret; -+} -+ -+static void ar7240sw_setup(struct ar7240sw *as) -+{ -+ /* Enable CPU port, and disable mirror port */ -+ ar7240sw_reg_write(as, AR7240_REG_CPU_PORT, -+ AR7240_CPU_PORT_EN | -+ (15 << AR7240_MIRROR_PORT_S)); -+ -+ /* Setup TAG priority mapping */ -+ ar7240sw_reg_write(as, AR7240_REG_TAG_PRIORITY, 0xfa50); -+ -+ /* Enable ARP frame acknowledge */ -+ ar7240sw_reg_set(as, AR7240_REG_AT_CTRL, AR7240_AT_CTRL_ARP_EN); -+ -+ /* Enable Broadcast frames transmitted to the CPU */ -+ ar7240sw_reg_set(as, AR7240_REG_FLOOD_MASK, -+ AR7240_FLOOD_MASK_BROAD_TO_CPU); -+ -+ /* setup MTU */ -+ ar7240sw_reg_rmw(as, AR7240_REG_GLOBAL_CTRL, AR7240_GLOBAL_CTRL_MTU_M, -+ 1536); -+ -+ /* setup Service TAG */ -+ ar7240sw_reg_rmw(as, AR7240_REG_SERVICE_TAG, AR7240_SERVICE_TAG_M, -+ ETH_P_QINQ); -+} -+ -+static void ar7240sw_setup_port(struct ar7240sw *as, unsigned port) -+{ -+ u32 ctrl; -+ u32 dest_ports; -+ u32 vlan; -+ -+ ctrl = AR7240_PORT_CTRL_STATE_FORWARD; -+ -+ if (port == AR7240_PORT_CPU) { -+ ar7240sw_reg_write(as, AR7240_REG_PORT_STATUS(port), -+ AR7240_PORT_STATUS_SPEED_1000 | -+ AR7240_PORT_STATUS_TXFLOW | -+ AR7240_PORT_STATUS_RXFLOW | -+ AR7240_PORT_STATUS_TXMAC | -+ AR7240_PORT_STATUS_RXMAC | -+ AR7240_PORT_STATUS_DUPLEX); -+ -+ /* allow the CPU port to talk to each of the 'real' ports */ -+ dest_ports = AR7240_PORT_MASK_BUT(port); -+ -+ /* remove service tag from ingress frames */ -+ ctrl |= AR7240_PORT_CTRL_DOUBLE_TAG; -+ } else { -+ ar7240sw_reg_write(as, AR7240_REG_PORT_STATUS(port), -+ AR7240_PORT_STATUS_LINK_AUTO); -+ -+ /* -+ * allow each of the 'real' ports to only talk to the CPU -+ * port. -+ */ -+ dest_ports = AR7240_PORT_MASK(port) | -+ AR7240_PORT_MASK(AR7240_PORT_CPU); -+ -+ /* add service tag to egress frames */ -+ ctrl |= (AR7240_PORT_CTRL_VLAN_MODE_DOUBLE_TAG << -+ AR7240_PORT_CTRL_VLAN_MODE_S); -+ } -+ -+ /* set default VID and and destination ports for this VLAN */ -+ vlan = port; -+ vlan |= (dest_ports << AR7240_PORT_VLAN_DEST_PORTS_S); -+ -+ ar7240sw_reg_write(as, AR7240_REG_PORT_CTRL(port), ctrl); -+ ar7240sw_reg_write(as, AR7240_REG_PORT_VLAN(port), vlan); -+} -+ -+static char *ar7240_dsa_probe(struct mii_bus *mii, int sw_addr) -+{ -+ struct ar7240sw as; -+ u32 ctrl; -+ u16 phy_id1; -+ u16 phy_id2; -+ u8 ver; -+ -+ ar7240sw_init(&as, mii); -+ -+ ctrl = ar7240sw_reg_read(&as, AR7240_REG_MASK_CTRL); -+ -+ ver = (ctrl >> AR7240_MASK_CTRL_VERSION_S) & AR7240_MASK_CTRL_VERSION_M; -+ if (ver != 1) { -+ pr_err("ar7240_dsa: unsupported chip, ctrl=%08x\n", ctrl); -+ return NULL; -+ } -+ -+ phy_id1 = ar7240sw_phy_read(&as, 0, MII_PHYSID1); -+ phy_id2 = ar7240sw_phy_read(&as, 0, MII_PHYSID2); -+ if (phy_id1 != AR7240_PHY_ID1 || phy_id2 != AR7240_PHY_ID2) { -+ pr_err("ar7240_dsa: unknown phy id '%04x:%04x'\n", -+ phy_id1, phy_id2); -+ return NULL; -+ } -+ -+ return "Atheros AR7240 built-in"; -+} -+ -+static int ar7240_dsa_setup(struct dsa_switch *ds) -+{ -+ struct ar7240sw *as = dsa_to_ar7240sw(ds); -+ int i; -+ int ret; -+ -+ ar7240sw_init(as, ds->master_mii_bus); -+ -+ ret = ar7240sw_reset(as); -+ if (ret) -+ return ret; -+ -+ ar7240sw_setup(as); -+ -+ for (i = 0; i < AR7240_NUM_PORTS; i++) { -+ if (dsa_is_cpu_port(ds, i) || (ds->phys_port_mask & (1 << i))) -+ ar7240sw_setup_port(as, i); -+ else -+ ar7240sw_disable_port(as, i); -+ } -+ -+ return 0; -+} -+ -+static int ar7240_dsa_set_addr(struct dsa_switch *ds, u8 *addr) -+{ -+ struct ar7240sw *as = dsa_to_ar7240sw(ds); -+ u32 t; -+ -+ t = (addr[4] << 8) | addr[5]; -+ ar7240sw_reg_write(as, AR7240_REG_MAC_ADDR0, t); -+ -+ t = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]; -+ ar7240sw_reg_write(as, AR7240_REG_MAC_ADDR1, t); -+ -+ return 0; -+} -+ -+static int ar7240_iort_to_phy_addr(int port) -+{ -+ if (port > 0 && port < AR7240_NUM_PORTS) -+ return port - 1; -+ -+ return -EINVAL; -+} -+ -+static int ar7240_dsa_phy_read(struct dsa_switch *ds, int port, int regnum) -+{ -+ struct ar7240sw *as = dsa_to_ar7240sw(ds); -+ int phy_addr; -+ -+ phy_addr = ar7240_iort_to_phy_addr(port); -+ if (phy_addr < 0) -+ return 0xffff; -+ -+ return ar7240sw_phy_read(as, phy_addr, regnum); -+} -+ -+static int ar7240_dsa_phy_write(struct dsa_switch *ds, int port, int regnum, -+ u16 val) -+{ -+ struct ar7240sw *as = dsa_to_ar7240sw(ds); -+ int phy_addr; -+ -+ phy_addr = ar7240_iort_to_phy_addr(port); -+ if (phy_addr < 0) -+ return 0xffff; -+ -+ return ar7240sw_phy_write(as, phy_addr, regnum, val); -+} -+ -+static const char *ar7240sw_speed_str(unsigned speed) -+{ -+ switch (speed) { -+ case AR7240_PORT_STATUS_SPEED_10: -+ return "10"; -+ case AR7240_PORT_STATUS_SPEED_100: -+ return "100"; -+ case AR7240_PORT_STATUS_SPEED_1000: -+ return "1000"; -+ } -+ -+ return "????"; -+} -+ -+static void ar7240_dsa_poll_link(struct dsa_switch *ds) -+{ -+ struct ar7240sw *as = dsa_to_ar7240sw(ds); -+ int i; -+ -+ for (i = 0; i < DSA_MAX_PORTS; i++) { -+ struct net_device *dev; -+ u32 status; -+ int link; -+ unsigned speed; -+ int duplex; -+ -+ dev = ds->ports[i]; -+ if (dev == NULL) -+ continue; -+ -+ link = 0; -+ if (dev->flags & IFF_UP) { -+ status = ar7240sw_reg_read(as, -+ AR7240_REG_PORT_STATUS(i)); -+ link = !!(status & AR7240_PORT_STATUS_LINK_UP); -+ } -+ -+ if (!link) { -+ if (netif_carrier_ok(dev)) { -+ pr_info("%s: link down\n", dev->name); -+ netif_carrier_off(dev); -+ } -+ continue; -+ } -+ -+ speed = (status & AR7240_PORT_STATUS_SPEED_M); -+ duplex = (status & AR7240_PORT_STATUS_DUPLEX) ? 1 : 0; -+ if (!netif_carrier_ok(dev)) { -+ pr_info("%s: link up, %sMb/s, %s duplex", -+ dev->name, -+ ar7240sw_speed_str(speed), -+ duplex ? "full" : "half"); -+ netif_carrier_on(dev); -+ } -+ } -+} -+ -+static const struct ar7240sw_hw_stat ar7240_hw_stats[] = { -+ { "rx_broadcast" , 4, AR7240_STATS_RXBROAD, }, -+ { "rx_pause" , 4, AR7240_STATS_RXPAUSE, }, -+ { "rx_multicast" , 4, AR7240_STATS_RXMULTI, }, -+ { "rx_fcs_error" , 4, AR7240_STATS_RXFCSERR, }, -+ { "rx_align_error" , 4, AR7240_STATS_RXALIGNERR, }, -+ { "rx_undersize" , 4, AR7240_STATS_RXRUNT, }, -+ { "rx_fragments" , 4, AR7240_STATS_RXFRAGMENT, }, -+ { "rx_64bytes" , 4, AR7240_STATS_RX64BYTE, }, -+ { "rx_65_127bytes" , 4, AR7240_STATS_RX128BYTE, }, -+ { "rx_128_255bytes" , 4, AR7240_STATS_RX256BYTE, }, -+ { "rx_256_511bytes" , 4, AR7240_STATS_RX512BYTE, }, -+ { "rx_512_1023bytes" , 4, AR7240_STATS_RX1024BYTE, }, -+ { "rx_1024_1518bytes" , 4, AR7240_STATS_RX1518BYTE, }, -+ { "rx_1519_max_bytes" , 4, AR7240_STATS_RXMAXBYTE, }, -+ { "rx_oversize" , 4, AR7240_STATS_RXTOOLONG, }, -+ { "rx_good_bytes" , 8, AR7240_STATS_RXGOODBYTE, }, -+ { "rx_bad_bytes" , 8, AR7240_STATS_RXBADBYTE, }, -+ { "rx_overflow" , 4, AR7240_STATS_RXOVERFLOW, }, -+ { "filtered" , 4, AR7240_STATS_FILTERED, }, -+ { "tx_broadcast" , 4, AR7240_STATS_TXBROAD, }, -+ { "tx_pause" , 4, AR7240_STATS_TXPAUSE, }, -+ { "tx_multicast" , 4, AR7240_STATS_TXMULTI, }, -+ { "tx_underrun" , 4, AR7240_STATS_TXUNDERRUN, }, -+ { "tx_64bytes" , 4, AR7240_STATS_TX64BYTE, }, -+ { "tx_65_127bytes" , 4, AR7240_STATS_TX128BYTE, }, -+ { "tx_128_255bytes" , 4, AR7240_STATS_TX256BYTE, }, -+ { "tx_256_511bytes" , 4, AR7240_STATS_TX512BYTE, }, -+ { "tx_512_1023bytes" , 4, AR7240_STATS_TX1024BYTE, }, -+ { "tx_1024_1518bytes" , 4, AR7240_STATS_TX1518BYTE, }, -+ { "tx_1519_max_bytes" , 4, AR7240_STATS_TXMAXBYTE, }, -+ { "tx_oversize" , 4, AR7240_STATS_TXOVERSIZE, }, -+ { "tx_bytes" , 8, AR7240_STATS_TXBYTE, }, -+ { "tx_collisions" , 4, AR7240_STATS_TXCOLLISION, }, -+ { "tx_abort_collisions" , 4, AR7240_STATS_TXABORTCOL, }, -+ { "tx_multi_collisions" , 4, AR7240_STATS_TXMULTICOL, }, -+ { "tx_single_collisions", 4, AR7240_STATS_TXSINGLECOL, }, -+ { "tx_excessive_deferred", 4, AR7240_STATS_TXEXCDEFER, }, -+ { "tx_deferred" , 4, AR7240_STATS_TXDEFER, }, -+ { "tx_late_collisions" , 4, AR7240_STATS_TXLATECOL, }, -+}; -+ -+static void ar7240_dsa_get_strings(struct dsa_switch *ds, int port, -+ uint8_t *data) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(ar7240_hw_stats); i++) { -+ memcpy(data + i * ETH_GSTRING_LEN, -+ ar7240_hw_stats[i].string, ETH_GSTRING_LEN); -+ } -+} -+ -+static void ar7240_dsa_get_ethtool_stats(struct dsa_switch *ds, int port, -+ uint64_t *data) -+{ -+ struct ar7240sw *as = dsa_to_ar7240sw(ds); -+ int err; -+ int i; -+ -+ mutex_lock(&as->stats_mutex); -+ -+ err = ar7240sw_capture_stats(as); -+ if (err) -+ goto unlock; -+ -+ for (i = 0; i < ARRAY_SIZE(ar7240_hw_stats); i++) { -+ const struct ar7240sw_hw_stat *s = &ar7240_hw_stats[i]; -+ u32 reg = AR7240_REG_STATS_BASE(port); -+ u32 low; -+ u32 high; -+ -+ low = ar7240sw_reg_read(as, reg + s->reg); -+ if (s->sizeof_stat == 8) -+ high = ar7240sw_reg_read(as, reg + s->reg); -+ else -+ high = 0; -+ -+ data[i] = (((u64) high) << 32) | low; -+ } -+ -+ unlock: -+ mutex_unlock(&as->stats_mutex); -+} -+ -+static int ar7240_dsa_get_sset_count(struct dsa_switch *ds) -+{ -+ return ARRAY_SIZE(ar7240_hw_stats); -+} -+ -+static struct dsa_switch_driver ar7240_dsa_driver = { -+ .tag_protocol = htons(ETH_P_QINQ), -+ .priv_size = sizeof(struct ar7240sw), -+ .probe = ar7240_dsa_probe, -+ .setup = ar7240_dsa_setup, -+ .set_addr = ar7240_dsa_set_addr, -+ .phy_read = ar7240_dsa_phy_read, -+ .phy_write = ar7240_dsa_phy_write, -+ .poll_link = ar7240_dsa_poll_link, -+ .get_strings = ar7240_dsa_get_strings, -+ .get_ethtool_stats = ar7240_dsa_get_ethtool_stats, -+ .get_sset_count = ar7240_dsa_get_sset_count, -+}; -+ -+int __init dsa_ar7240_init(void) -+{ -+ register_switch_driver(&ar7240_dsa_driver); -+ return 0; -+} -+module_init(dsa_ar7240_init); -+ -+void __exit dsa_ar7240_cleanup(void) -+{ -+ unregister_switch_driver(&ar7240_dsa_driver); -+} -+module_exit(dsa_ar7240_cleanup); -diff -Nur linux-2.6.36.orig/net/dsa/mv88e6063.c linux-2.6.36/net/dsa/mv88e6063.c ---- linux-2.6.36.orig/net/dsa/mv88e6063.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/net/dsa/mv88e6063.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,294 @@ -+/* -+ * net/dsa/mv88e6063.c - Driver for Marvell 88e6063 switch chips -+ * Copyright (c) 2009 Gabor Juhos -+ * -+ * This driver was base on: net/dsa/mv88e6060.c -+ * net/dsa/mv88e6063.c - Driver for Marvell 88e6060 switch chips -+ * Copyright (c) 2008-2009 Marvell Semiconductor -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ */ -+ -+#include -+#include -+#include -+#include "dsa_priv.h" -+ -+#define REG_BASE 0x10 -+#define REG_PHY(p) (REG_BASE + (p)) -+#define REG_PORT(p) (REG_BASE + 8 + (p)) -+#define REG_GLOBAL (REG_BASE + 0x0f) -+#define NUM_PORTS 7 -+ -+static int reg_read(struct dsa_switch *ds, int addr, int reg) -+{ -+ return mdiobus_read(ds->master_mii_bus, addr, reg); -+} -+ -+#define REG_READ(addr, reg) \ -+ ({ \ -+ int __ret; \ -+ \ -+ __ret = reg_read(ds, addr, reg); \ -+ if (__ret < 0) \ -+ return __ret; \ -+ __ret; \ -+ }) -+ -+ -+static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val) -+{ -+ return mdiobus_write(ds->master_mii_bus, addr, reg, val); -+} -+ -+#define REG_WRITE(addr, reg, val) \ -+ ({ \ -+ int __ret; \ -+ \ -+ __ret = reg_write(ds, addr, reg, val); \ -+ if (__ret < 0) \ -+ return __ret; \ -+ }) -+ -+static char *mv88e6063_probe(struct mii_bus *bus, int sw_addr) -+{ -+ int ret; -+ -+ ret = mdiobus_read(bus, REG_PORT(0), 0x03); -+ if (ret >= 0) { -+ ret &= 0xfff0; -+ if (ret == 0x1530) -+ return "Marvell 88E6063"; -+ } -+ -+ return NULL; -+} -+ -+static int mv88e6063_switch_reset(struct dsa_switch *ds) -+{ -+ int i; -+ int ret; -+ -+ /* -+ * Set all ports to the disabled state. -+ */ -+ for (i = 0; i < NUM_PORTS; i++) { -+ ret = REG_READ(REG_PORT(i), 0x04); -+ REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc); -+ } -+ -+ /* -+ * Wait for transmit queues to drain. -+ */ -+ msleep(2); -+ -+ /* -+ * Reset the switch. -+ */ -+ REG_WRITE(REG_GLOBAL, 0x0a, 0xa130); -+ -+ /* -+ * Wait up to one second for reset to complete. -+ */ -+ for (i = 0; i < 1000; i++) { -+ ret = REG_READ(REG_GLOBAL, 0x00); -+ if ((ret & 0x8000) == 0x0000) -+ break; -+ -+ msleep(1); -+ } -+ if (i == 1000) -+ return -ETIMEDOUT; -+ -+ return 0; -+} -+ -+static int mv88e6063_setup_global(struct dsa_switch *ds) -+{ -+ /* -+ * Disable discarding of frames with excessive collisions, -+ * set the maximum frame size to 1536 bytes, and mask all -+ * interrupt sources. -+ */ -+ REG_WRITE(REG_GLOBAL, 0x04, 0x0800); -+ -+ /* -+ * Enable automatic address learning, set the address -+ * database size to 1024 entries, and set the default aging -+ * time to 5 minutes. -+ */ -+ REG_WRITE(REG_GLOBAL, 0x0a, 0x2130); -+ -+ return 0; -+} -+ -+static int mv88e6063_setup_port(struct dsa_switch *ds, int p) -+{ -+ int addr = REG_PORT(p); -+ -+ /* -+ * Do not force flow control, disable Ingress and Egress -+ * Header tagging, disable VLAN tunneling, and set the port -+ * state to Forwarding. Additionally, if this is the CPU -+ * port, enable Ingress and Egress Trailer tagging mode. -+ */ -+ REG_WRITE(addr, 0x04, dsa_is_cpu_port(ds, p) ? 0x4103 : 0x0003); -+ -+ /* -+ * Port based VLAN map: give each port its own address -+ * database, allow the CPU port to talk to each of the 'real' -+ * ports, and allow each of the 'real' ports to only talk to -+ * the CPU port. -+ */ -+ REG_WRITE(addr, 0x06, -+ ((p & 0xf) << 12) | -+ (dsa_is_cpu_port(ds, p) ? -+ ds->phys_port_mask : -+ (1 << ds->dst->cpu_port))); -+ -+ /* -+ * Port Association Vector: when learning source addresses -+ * of packets, add the address to the address database using -+ * a port bitmap that has only the bit for this port set and -+ * the other bits clear. -+ */ -+ REG_WRITE(addr, 0x0b, 1 << p); -+ -+ return 0; -+} -+ -+static int mv88e6063_setup(struct dsa_switch *ds) -+{ -+ int i; -+ int ret; -+ -+ ret = mv88e6063_switch_reset(ds); -+ if (ret < 0) -+ return ret; -+ -+ /* @@@ initialise atu */ -+ -+ ret = mv88e6063_setup_global(ds); -+ if (ret < 0) -+ return ret; -+ -+ for (i = 0; i < NUM_PORTS; i++) { -+ ret = mv88e6063_setup_port(ds, i); -+ if (ret < 0) -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static int mv88e6063_set_addr(struct dsa_switch *ds, u8 *addr) -+{ -+ REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) | addr[1]); -+ REG_WRITE(REG_GLOBAL, 0x02, (addr[2] << 8) | addr[3]); -+ REG_WRITE(REG_GLOBAL, 0x03, (addr[4] << 8) | addr[5]); -+ -+ return 0; -+} -+ -+static int mv88e6063_port_to_phy_addr(int port) -+{ -+ if (port >= 0 && port <= NUM_PORTS) -+ return REG_PHY(port); -+ return -1; -+} -+ -+static int mv88e6063_phy_read(struct dsa_switch *ds, int port, int regnum) -+{ -+ int addr; -+ -+ addr = mv88e6063_port_to_phy_addr(port); -+ if (addr == -1) -+ return 0xffff; -+ -+ return reg_read(ds, addr, regnum); -+} -+ -+static int -+mv88e6063_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val) -+{ -+ int addr; -+ -+ addr = mv88e6063_port_to_phy_addr(port); -+ if (addr == -1) -+ return 0xffff; -+ -+ return reg_write(ds, addr, regnum, val); -+} -+ -+static void mv88e6063_poll_link(struct dsa_switch *ds) -+{ -+ int i; -+ -+ for (i = 0; i < DSA_MAX_PORTS; i++) { -+ struct net_device *dev; -+ int uninitialized_var(port_status); -+ int link; -+ int speed; -+ int duplex; -+ int fc; -+ -+ dev = ds->ports[i]; -+ if (dev == NULL) -+ continue; -+ -+ link = 0; -+ if (dev->flags & IFF_UP) { -+ port_status = reg_read(ds, REG_PORT(i), 0x00); -+ if (port_status < 0) -+ continue; -+ -+ link = !!(port_status & 0x1000); -+ } -+ -+ if (!link) { -+ if (netif_carrier_ok(dev)) { -+ printk(KERN_INFO "%s: link down\n", dev->name); -+ netif_carrier_off(dev); -+ } -+ continue; -+ } -+ -+ speed = (port_status & 0x0100) ? 100 : 10; -+ duplex = (port_status & 0x0200) ? 1 : 0; -+ fc = ((port_status & 0xc000) == 0xc000) ? 1 : 0; -+ -+ if (!netif_carrier_ok(dev)) { -+ printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, " -+ "flow control %sabled\n", dev->name, -+ speed, duplex ? "full" : "half", -+ fc ? "en" : "dis"); -+ netif_carrier_on(dev); -+ } -+ } -+} -+ -+static struct dsa_switch_driver mv88e6063_switch_driver = { -+ .tag_protocol = htons(ETH_P_TRAILER), -+ .probe = mv88e6063_probe, -+ .setup = mv88e6063_setup, -+ .set_addr = mv88e6063_set_addr, -+ .phy_read = mv88e6063_phy_read, -+ .phy_write = mv88e6063_phy_write, -+ .poll_link = mv88e6063_poll_link, -+}; -+ -+static int __init mv88e6063_init(void) -+{ -+ register_switch_driver(&mv88e6063_switch_driver); -+ return 0; -+} -+module_init(mv88e6063_init); -+ -+static void __exit mv88e6063_cleanup(void) -+{ -+ unregister_switch_driver(&mv88e6063_switch_driver); -+} -+module_exit(mv88e6063_cleanup); -diff -Nur linux-2.6.36.orig/net/dsa/tag_qinq.c linux-2.6.36/net/dsa/tag_qinq.c ---- linux-2.6.36.orig/net/dsa/tag_qinq.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/net/dsa/tag_qinq.c 2010-12-17 18:34:51.000000000 +0100 -@@ -0,0 +1,127 @@ -+/* -+ * net/dsa/tag_qinq.c - QinQ tag format handling -+ * Copyright (c) 2010 Gabor Juhos -+ * -+ * This file was based on: -+ * net/dsa/tag_edsa.c - Ethertype DSA tagging -+ * Copyright (c) 2008-2009 Marvell Semiconductor -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include "dsa_priv.h" -+ -+netdev_tx_t qinq_xmit(struct sk_buff *skb, struct net_device *dev) -+{ -+ struct dsa_slave_priv *p = netdev_priv(dev); -+ struct vlan_ethhdr *veth; -+ unsigned int len; -+ int ret; -+ -+ if (skb_cow_head(skb, VLAN_HLEN) < 0) -+ goto out_free_skb; -+ -+ veth = (struct vlan_ethhdr *)skb_push(skb, VLAN_HLEN); -+ -+ /* Move the mac addresses to the beginning of the new header. */ -+ memmove(skb->data, skb->data + VLAN_HLEN, 2 * VLAN_ETH_ALEN); -+ skb->mac_header -= VLAN_HLEN; -+ -+ /* setup VLAN header fields */ -+ veth->h_vlan_proto = htons(ETH_P_QINQ); -+ veth->h_vlan_TCI = htons(p->port); -+ -+ len = skb->len; -+ skb->protocol = htons(ETH_P_QINQ); -+ skb->dev = p->parent->dst->master_netdev; -+ -+ ret = dev_queue_xmit(skb); -+ if (unlikely(ret != NET_XMIT_SUCCESS)) -+ goto out_dropped; -+ -+ dev->stats.tx_packets++; -+ dev->stats.tx_bytes += len; -+ -+ return NETDEV_TX_OK; -+ -+ out_free_skb: -+ kfree_skb(skb); -+ out_dropped: -+ dev->stats.tx_dropped++; -+ return NETDEV_TX_OK; -+} -+ -+static int qinq_rcv(struct sk_buff *skb, struct net_device *dev, -+ struct packet_type *pt, struct net_device *orig_dev) -+{ -+ struct dsa_switch_tree *dst; -+ struct dsa_switch *ds; -+ struct vlan_hdr *vhdr; -+ int source_port; -+ -+ dst = dev->dsa_ptr; -+ if (unlikely(dst == NULL)) -+ goto out_drop; -+ ds = dst->ds[0]; -+ -+ skb = skb_unshare(skb, GFP_ATOMIC); -+ if (skb == NULL) -+ goto out; -+ -+ if (unlikely(!pskb_may_pull(skb, VLAN_HLEN))) -+ goto out_drop; -+ -+ vhdr = (struct vlan_hdr *)skb->data; -+ source_port = ntohs(vhdr->h_vlan_TCI) & VLAN_VID_MASK; -+ if (source_port >= DSA_MAX_PORTS || ds->ports[source_port] == NULL) -+ goto out_drop; -+ -+ /* Remove the outermost VLAN tag and update checksum. */ -+ skb_pull_rcsum(skb, VLAN_HLEN); -+ memmove(skb->data - ETH_HLEN, -+ skb->data - ETH_HLEN - VLAN_HLEN, -+ 2 * ETH_ALEN); -+ -+ skb->dev = ds->ports[source_port]; -+ skb_push(skb, ETH_HLEN); -+ skb->pkt_type = PACKET_HOST; -+ skb->protocol = eth_type_trans(skb, skb->dev); -+ -+ skb->dev->stats.rx_packets++; -+ skb->dev->stats.rx_bytes += skb->len; -+ -+ netif_receive_skb(skb); -+ -+ return 0; -+ -+ out_drop: -+ kfree_skb(skb); -+ out: -+ return 0; -+} -+ -+static struct packet_type qinq_packet_type __read_mostly = { -+ .type = cpu_to_be16(ETH_P_QINQ), -+ .func = qinq_rcv, -+}; -+ -+static int __init qinq_init_module(void) -+{ -+ dev_add_pack(&qinq_packet_type); -+ return 0; -+} -+module_init(qinq_init_module); -+ -+static void __exit qinq_cleanup_module(void) -+{ -+ dev_remove_pack(&qinq_packet_type); -+} -+module_exit(qinq_cleanup_module); diff --git a/target/linux/patches/2.6.36/aufs2.patch b/target/linux/patches/2.6.36/aufs2.patch deleted file mode 100644 index e9e5fc277..000000000 --- a/target/linux/patches/2.6.36/aufs2.patch +++ /dev/null @@ -1,33532 +0,0 @@ -diff -Nur linux-2.6.36.orig/fs/Kconfig linux-2.6.36/fs/Kconfig ---- linux-2.6.36.orig/fs/Kconfig 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/fs/Kconfig 2011-01-10 19:52:38.000000000 +0100 -@@ -189,6 +189,7 @@ - source "fs/sysv/Kconfig" - source "fs/ufs/Kconfig" - source "fs/exofs/Kconfig" -+source "fs/aufs/Kconfig" - - endif # MISC_FILESYSTEMS - -diff -Nur linux-2.6.36.orig/fs/Makefile linux-2.6.36/fs/Makefile ---- linux-2.6.36.orig/fs/Makefile 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/fs/Makefile 2011-01-10 19:52:38.000000000 +0100 -@@ -126,3 +126,4 @@ - obj-$(CONFIG_GFS2_FS) += gfs2/ - obj-$(CONFIG_EXOFS_FS) += exofs/ - obj-$(CONFIG_CEPH_FS) += ceph/ -+obj-$(CONFIG_AUFS_FS) += aufs/ -diff -Nur linux-2.6.36.orig/fs/aufs/Kconfig linux-2.6.36/fs/aufs/Kconfig ---- linux-2.6.36.orig/fs/aufs/Kconfig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/Kconfig 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,180 @@ -+config AUFS_FS -+ tristate "Aufs (Advanced multi layered unification filesystem) support" -+ depends on EXPERIMENTAL -+ help -+ Aufs is a stackable unification filesystem such as Unionfs, -+ which unifies several directories and provides a merged single -+ directory. -+ In the early days, aufs was entirely re-designed and -+ re-implemented Unionfs Version 1.x series. Introducing many -+ original ideas, approaches and improvements, it becomes totally -+ different from Unionfs while keeping the basic features. -+ -+if AUFS_FS -+choice -+ prompt "Maximum number of branches" -+ default AUFS_BRANCH_MAX_127 -+ help -+ Specifies the maximum number of branches (or member directories) -+ in a single aufs. The larger value consumes more system -+ resources and has a minor impact to performance. -+config AUFS_BRANCH_MAX_127 -+ bool "127" -+ help -+ Specifies the maximum number of branches (or member directories) -+ in a single aufs. The larger value consumes more system -+ resources and has a minor impact to performance. -+config AUFS_BRANCH_MAX_511 -+ bool "511" -+ help -+ Specifies the maximum number of branches (or member directories) -+ in a single aufs. The larger value consumes more system -+ resources and has a minor impact to performance. -+config AUFS_BRANCH_MAX_1023 -+ bool "1023" -+ help -+ Specifies the maximum number of branches (or member directories) -+ in a single aufs. The larger value consumes more system -+ resources and has a minor impact to performance. -+config AUFS_BRANCH_MAX_32767 -+ bool "32767" -+ help -+ Specifies the maximum number of branches (or member directories) -+ in a single aufs. The larger value consumes more system -+ resources and has a minor impact to performance. -+endchoice -+ -+config AUFS_SBILIST -+ bool -+ depends on AUFS_MAGIC_SYSRQ || PROC_FS -+ default y -+ help -+ Automatic configuration for internal use. -+ When aufs supports Magic SysRq or /proc, enabled automatically. -+ -+config AUFS_HNOTIFY -+ bool "Detect direct branch access (bypassing aufs)" -+ help -+ If you want to modify files on branches directly, eg. bypassing aufs, -+ and want aufs to detect the changes of them fully, then enable this -+ option and use 'udba=notify' mount option. -+ Currently there is only one available configuration, "fsnotify". -+ It will have a negative impact to the performance. -+ See detail in aufs.5. -+ -+choice -+ prompt "method" if AUFS_HNOTIFY -+ default AUFS_HFSNOTIFY -+config AUFS_HFSNOTIFY -+ bool "fsnotify" -+ select FSNOTIFY -+endchoice -+ -+config AUFS_EXPORT -+ bool "NFS-exportable aufs" -+ depends on (AUFS_FS = y && EXPORTFS = y) || (AUFS_FS = m && EXPORTFS) -+ help -+ If you want to export your mounted aufs via NFS, then enable this -+ option. There are several requirements for this configuration. -+ See detail in aufs.5. -+ -+config AUFS_INO_T_64 -+ bool -+ depends on AUFS_EXPORT -+ depends on 64BIT && !(ALPHA || S390) -+ default y -+ help -+ Automatic configuration for internal use. -+ /* typedef unsigned long/int __kernel_ino_t */ -+ /* alpha and s390x are int */ -+ -+config AUFS_RDU -+ bool "Readdir in userspace" -+ help -+ Aufs has two methods to provide a merged view for a directory, -+ by a user-space library and by kernel-space natively. The latter -+ is always enabled but sometimes large and slow. -+ If you enable this option, install the library in aufs2-util -+ package, and set some environment variables for your readdir(3), -+ then the work will be handled in user-space which generally -+ shows better performance in most cases. -+ See detail in aufs.5. -+ -+config AUFS_SP_IATTR -+ bool "Respect the attributes (mtime/ctime mainly) of special files" -+ help -+ When you write something to a special file, some attributes of it -+ (mtime/ctime mainly) may be updated. Generally such updates are -+ less important (actually some device drivers and NFS ignore -+ it). But some applications (such like test program) requires -+ such updates. If you need these updates, then enable this -+ configuration which introduces some overhead. -+ Currently this configuration handles FIFO only. -+ -+config AUFS_SHWH -+ bool "Show whiteouts" -+ help -+ If you want to make the whiteouts in aufs visible, then enable -+ this option and specify 'shwh' mount option. Although it may -+ sounds like philosophy or something, but in technically it -+ simply shows the name of whiteout with keeping its behaviour. -+ -+config AUFS_BR_RAMFS -+ bool "Ramfs (initramfs/rootfs) as an aufs branch" -+ help -+ If you want to use ramfs as an aufs branch fs, then enable this -+ option. Generally tmpfs is recommended. -+ Aufs prohibited them to be a branch fs by default, because -+ initramfs becomes unusable after switch_root or something -+ generally. If you sets initramfs as an aufs branch and boot your -+ system by switch_root, you will meet a problem easily since the -+ files in initramfs may be inaccessible. -+ Unless you are going to use ramfs as an aufs branch fs without -+ switch_root or something, leave it N. -+ -+config AUFS_BR_FUSE -+ bool "Fuse fs as an aufs branch" -+ depends on FUSE_FS -+ select AUFS_POLL -+ help -+ If you want to use fuse-based userspace filesystem as an aufs -+ branch fs, then enable this option. -+ It implements the internal poll(2) operation which is -+ implemented by fuse only (curretnly). -+ -+config AUFS_POLL -+ bool -+ help -+ Automatic configuration for internal use. -+ -+config AUFS_BR_HFSPLUS -+ bool "Hfsplus as an aufs branch" -+ depends on HFSPLUS_FS -+ default y -+ help -+ If you want to use hfsplus fs as an aufs branch fs, then enable -+ this option. This option introduces a small overhead at -+ copying-up a file on hfsplus. -+ -+config AUFS_BDEV_LOOP -+ bool -+ depends on BLK_DEV_LOOP -+ default y -+ help -+ Automatic configuration for internal use. -+ Convert =[ym] into =y. -+ -+config AUFS_DEBUG -+ bool "Debug aufs" -+ help -+ Enable this to compile aufs internal debug code. -+ It will have a negative impact to the performance. -+ -+config AUFS_MAGIC_SYSRQ -+ bool -+ depends on AUFS_DEBUG && MAGIC_SYSRQ -+ default y -+ help -+ Automatic configuration for internal use. -+ When aufs supports Magic SysRq, enabled automatically. -+endif -diff -Nur linux-2.6.36.orig/fs/aufs/Makefile linux-2.6.36/fs/aufs/Makefile ---- linux-2.6.36.orig/fs/aufs/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/Makefile 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,38 @@ -+ -+include ${src}/magic.mk -+ifeq (${CONFIG_AUFS_FS},m) -+include ${src}/conf.mk -+endif -+-include ${src}/priv_def.mk -+ -+# cf. include/linux/kernel.h -+# enable pr_debug -+ccflags-y += -DDEBUG -+# sparse doesn't allow spaces -+ccflags-y += -D'pr_fmt(fmt)=AUFS_NAME"\040%s:%d:%s[%d]:\040"fmt,__func__,__LINE__,current->comm,current->pid' -+ -+obj-$(CONFIG_AUFS_FS) += aufs.o -+aufs-y := module.o sbinfo.o super.o branch.o xino.o sysaufs.o opts.o \ -+ wkq.o vfsub.o dcsub.o \ -+ cpup.o whout.o wbr_policy.o \ -+ dinfo.o dentry.o \ -+ dynop.o \ -+ finfo.o file.o f_op.o \ -+ dir.o vdir.o \ -+ iinfo.o inode.o i_op.o i_op_add.o i_op_del.o i_op_ren.o \ -+ ioctl.o -+ -+# all are boolean -+aufs-$(CONFIG_PROC_FS) += procfs.o plink.o -+aufs-$(CONFIG_SYSFS) += sysfs.o -+aufs-$(CONFIG_DEBUG_FS) += dbgaufs.o -+aufs-$(CONFIG_AUFS_BDEV_LOOP) += loop.o -+aufs-$(CONFIG_AUFS_HNOTIFY) += hnotify.o -+aufs-$(CONFIG_AUFS_HFSNOTIFY) += hfsnotify.o -+aufs-$(CONFIG_AUFS_EXPORT) += export.o -+aufs-$(CONFIG_AUFS_POLL) += poll.o -+aufs-$(CONFIG_AUFS_RDU) += rdu.o -+aufs-$(CONFIG_AUFS_SP_IATTR) += f_op_sp.o -+aufs-$(CONFIG_AUFS_BR_HFSPLUS) += hfsplus.o -+aufs-$(CONFIG_AUFS_DEBUG) += debug.o -+aufs-$(CONFIG_AUFS_MAGIC_SYSRQ) += sysrq.o -diff -Nur linux-2.6.36.orig/fs/aufs/aufs.h linux-2.6.36/fs/aufs/aufs.h ---- linux-2.6.36.orig/fs/aufs/aufs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/aufs.h 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,61 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * all header files -+ */ -+ -+#ifndef __AUFS_H__ -+#define __AUFS_H__ -+ -+#ifdef __KERNEL__ -+ -+#define AuStub(type, name, body, ...) \ -+ static inline type name(__VA_ARGS__) { body; } -+ -+#define AuStubVoid(name, ...) \ -+ AuStub(void, name, , __VA_ARGS__) -+#define AuStubInt0(name, ...) \ -+ AuStub(int, name, return 0, __VA_ARGS__) -+ -+#include "debug.h" -+ -+#include "branch.h" -+#include "cpup.h" -+#include "dcsub.h" -+#include "dbgaufs.h" -+#include "dentry.h" -+#include "dir.h" -+#include "dynop.h" -+#include "file.h" -+#include "fstype.h" -+#include "inode.h" -+#include "loop.h" -+#include "module.h" -+/* never include ./mtx.h */ -+#include "opts.h" -+#include "rwsem.h" -+#include "spl.h" -+#include "super.h" -+#include "sysaufs.h" -+#include "vfsub.h" -+#include "whout.h" -+#include "wkq.h" -+ -+#endif /* __KERNEL__ */ -+#endif /* __AUFS_H__ */ -diff -Nur linux-2.6.36.orig/fs/aufs/branch.c linux-2.6.36/fs/aufs/branch.c ---- linux-2.6.36.orig/fs/aufs/branch.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/branch.c 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,1071 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * branch management -+ */ -+ -+#include -+#include -+#include "aufs.h" -+ -+/* -+ * free a single branch -+ */ -+static void au_br_do_free(struct au_branch *br) -+{ -+ int i; -+ struct au_wbr *wbr; -+ struct au_dykey **key; -+ -+ au_hnotify_fin_br(br); -+ -+ if (br->br_xino.xi_file) -+ fput(br->br_xino.xi_file); -+ mutex_destroy(&br->br_xino.xi_nondir_mtx); -+ -+ AuDebugOn(atomic_read(&br->br_count)); -+ -+ wbr = br->br_wbr; -+ if (wbr) { -+ for (i = 0; i < AuBrWh_Last; i++) -+ dput(wbr->wbr_wh[i]); -+ AuDebugOn(atomic_read(&wbr->wbr_wh_running)); -+ AuRwDestroy(&wbr->wbr_wh_rwsem); -+ } -+ -+ key = br->br_dykey; -+ for (i = 0; i < AuBrDynOp; i++, key++) -+ if (*key) -+ au_dy_put(*key); -+ else -+ break; -+ -+ mntput(br->br_mnt); -+ kfree(wbr); -+ kfree(br); -+} -+ -+/* -+ * frees all branches -+ */ -+void au_br_free(struct au_sbinfo *sbinfo) -+{ -+ aufs_bindex_t bmax; -+ struct au_branch **br; -+ -+ AuRwMustWriteLock(&sbinfo->si_rwsem); -+ -+ bmax = sbinfo->si_bend + 1; -+ br = sbinfo->si_branch; -+ while (bmax--) -+ au_br_do_free(*br++); -+} -+ -+/* -+ * find the index of a branch which is specified by @br_id. -+ */ -+int au_br_index(struct super_block *sb, aufs_bindex_t br_id) -+{ -+ aufs_bindex_t bindex, bend; -+ -+ bend = au_sbend(sb); -+ for (bindex = 0; bindex <= bend; bindex++) -+ if (au_sbr_id(sb, bindex) == br_id) -+ return bindex; -+ return -1; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * add a branch -+ */ -+ -+static int test_overlap(struct super_block *sb, struct dentry *h_adding, -+ struct dentry *h_root) -+{ -+ if (unlikely(h_adding == h_root -+ || au_test_loopback_overlap(sb, h_adding))) -+ return 1; -+ if (h_adding->d_sb != h_root->d_sb) -+ return 0; -+ return au_test_subdir(h_adding, h_root) -+ || au_test_subdir(h_root, h_adding); -+} -+ -+/* -+ * returns a newly allocated branch. @new_nbranch is a number of branches -+ * after adding a branch. -+ */ -+static struct au_branch *au_br_alloc(struct super_block *sb, int new_nbranch, -+ int perm) -+{ -+ struct au_branch *add_branch; -+ struct dentry *root; -+ int err; -+ -+ err = -ENOMEM; -+ root = sb->s_root; -+ add_branch = kmalloc(sizeof(*add_branch), GFP_NOFS); -+ if (unlikely(!add_branch)) -+ goto out; -+ -+ err = au_hnotify_init_br(add_branch, perm); -+ if (unlikely(err)) -+ goto out_br; -+ -+ add_branch->br_wbr = NULL; -+ if (au_br_writable(perm)) { -+ /* may be freed separately at changing the branch permission */ -+ add_branch->br_wbr = kmalloc(sizeof(*add_branch->br_wbr), -+ GFP_NOFS); -+ if (unlikely(!add_branch->br_wbr)) -+ goto out_hnotify; -+ } -+ -+ err = au_sbr_realloc(au_sbi(sb), new_nbranch); -+ if (!err) -+ err = au_di_realloc(au_di(root), new_nbranch); -+ if (!err) -+ err = au_ii_realloc(au_ii(root->d_inode), new_nbranch); -+ if (!err) -+ return add_branch; /* success */ -+ -+ kfree(add_branch->br_wbr); -+ -+out_hnotify: -+ au_hnotify_fin_br(add_branch); -+out_br: -+ kfree(add_branch); -+out: -+ return ERR_PTR(err); -+} -+ -+/* -+ * test if the branch permission is legal or not. -+ */ -+static int test_br(struct inode *inode, int brperm, char *path) -+{ -+ int err; -+ -+ err = (au_br_writable(brperm) && IS_RDONLY(inode)); -+ if (!err) -+ goto out; -+ -+ err = -EINVAL; -+ pr_err("write permission for readonly mount or inode, %s\n", path); -+ -+out: -+ return err; -+} -+ -+/* -+ * returns: -+ * 0: success, the caller will add it -+ * plus: success, it is already unified, the caller should ignore it -+ * minus: error -+ */ -+static int test_add(struct super_block *sb, struct au_opt_add *add, int remount) -+{ -+ int err; -+ aufs_bindex_t bend, bindex; -+ struct dentry *root; -+ struct inode *inode, *h_inode; -+ -+ root = sb->s_root; -+ bend = au_sbend(sb); -+ if (unlikely(bend >= 0 -+ && au_find_dbindex(root, add->path.dentry) >= 0)) { -+ err = 1; -+ if (!remount) { -+ err = -EINVAL; -+ pr_err("%s duplicated\n", add->pathname); -+ } -+ goto out; -+ } -+ -+ err = -ENOSPC; /* -E2BIG; */ -+ if (unlikely(AUFS_BRANCH_MAX <= add->bindex -+ || AUFS_BRANCH_MAX - 1 <= bend)) { -+ pr_err("number of branches exceeded %s\n", add->pathname); -+ goto out; -+ } -+ -+ err = -EDOM; -+ if (unlikely(add->bindex < 0 || bend + 1 < add->bindex)) { -+ pr_err("bad index %d\n", add->bindex); -+ goto out; -+ } -+ -+ inode = add->path.dentry->d_inode; -+ err = -ENOENT; -+ if (unlikely(!inode->i_nlink)) { -+ pr_err("no existence %s\n", add->pathname); -+ goto out; -+ } -+ -+ err = -EINVAL; -+ if (unlikely(inode->i_sb == sb)) { -+ pr_err("%s must be outside\n", add->pathname); -+ goto out; -+ } -+ -+ if (unlikely(au_test_fs_unsuppoted(inode->i_sb))) { -+ pr_err("unsupported filesystem, %s (%s)\n", -+ add->pathname, au_sbtype(inode->i_sb)); -+ goto out; -+ } -+ -+ err = test_br(add->path.dentry->d_inode, add->perm, add->pathname); -+ if (unlikely(err)) -+ goto out; -+ -+ if (bend < 0) -+ return 0; /* success */ -+ -+ err = -EINVAL; -+ for (bindex = 0; bindex <= bend; bindex++) -+ if (unlikely(test_overlap(sb, add->path.dentry, -+ au_h_dptr(root, bindex)))) { -+ pr_err("%s is overlapped\n", add->pathname); -+ goto out; -+ } -+ -+ err = 0; -+ if (au_opt_test(au_mntflags(sb), WARN_PERM)) { -+ h_inode = au_h_dptr(root, 0)->d_inode; -+ if ((h_inode->i_mode & S_IALLUGO) != (inode->i_mode & S_IALLUGO) -+ || h_inode->i_uid != inode->i_uid -+ || h_inode->i_gid != inode->i_gid) -+ pr_warning("uid/gid/perm %s %u/%u/0%o, %u/%u/0%o\n", -+ add->pathname, -+ inode->i_uid, inode->i_gid, -+ (inode->i_mode & S_IALLUGO), -+ h_inode->i_uid, h_inode->i_gid, -+ (h_inode->i_mode & S_IALLUGO)); -+ } -+ -+out: -+ return err; -+} -+ -+/* -+ * initialize or clean the whiteouts for an adding branch -+ */ -+static int au_br_init_wh(struct super_block *sb, struct au_branch *br, -+ int new_perm, struct dentry *h_root) -+{ -+ int err, old_perm; -+ aufs_bindex_t bindex; -+ struct mutex *h_mtx; -+ struct au_wbr *wbr; -+ struct au_hinode *hdir; -+ -+ wbr = br->br_wbr; -+ old_perm = br->br_perm; -+ br->br_perm = new_perm; -+ hdir = NULL; -+ h_mtx = NULL; -+ bindex = au_br_index(sb, br->br_id); -+ if (0 <= bindex) { -+ hdir = au_hi(sb->s_root->d_inode, bindex); -+ au_hn_imtx_lock_nested(hdir, AuLsc_I_PARENT); -+ } else { -+ h_mtx = &h_root->d_inode->i_mutex; -+ mutex_lock_nested(h_mtx, AuLsc_I_PARENT); -+ } -+ if (!wbr) -+ err = au_wh_init(h_root, br, sb); -+ else { -+ wbr_wh_write_lock(wbr); -+ err = au_wh_init(h_root, br, sb); -+ wbr_wh_write_unlock(wbr); -+ } -+ if (hdir) -+ au_hn_imtx_unlock(hdir); -+ else -+ mutex_unlock(h_mtx); -+ br->br_perm = old_perm; -+ -+ if (!err && wbr && !au_br_writable(new_perm)) { -+ kfree(wbr); -+ br->br_wbr = NULL; -+ } -+ -+ return err; -+} -+ -+static int au_wbr_init(struct au_branch *br, struct super_block *sb, -+ int perm, struct path *path) -+{ -+ int err; -+ struct kstatfs kst; -+ struct au_wbr *wbr; -+ struct dentry *h_dentry; -+ -+ wbr = br->br_wbr; -+ au_rw_init(&wbr->wbr_wh_rwsem); -+ memset(wbr->wbr_wh, 0, sizeof(wbr->wbr_wh)); -+ atomic_set(&wbr->wbr_wh_running, 0); -+ wbr->wbr_bytes = 0; -+ -+ /* -+ * a limit for rmdir/rename a dir -+ * cf. AUFS_MAX_NAMELEN in include/linux/aufs_type.h -+ */ -+ err = vfs_statfs(path, &kst); -+ if (unlikely(err)) -+ goto out; -+ err = -EINVAL; -+ h_dentry = path->dentry; -+ if (kst.f_namelen >= NAME_MAX) -+ err = au_br_init_wh(sb, br, perm, h_dentry); -+ else -+ pr_err("%.*s(%s), unsupported namelen %ld\n", -+ AuDLNPair(h_dentry), au_sbtype(h_dentry->d_sb), -+ kst.f_namelen); -+ -+out: -+ return err; -+} -+ -+/* intialize a new branch */ -+static int au_br_init(struct au_branch *br, struct super_block *sb, -+ struct au_opt_add *add) -+{ -+ int err; -+ -+ err = 0; -+ memset(&br->br_xino, 0, sizeof(br->br_xino)); -+ mutex_init(&br->br_xino.xi_nondir_mtx); -+ br->br_perm = add->perm; -+ br->br_mnt = add->path.mnt; /* set first, mntget() later */ -+ spin_lock_init(&br->br_dykey_lock); -+ memset(br->br_dykey, 0, sizeof(br->br_dykey)); -+ atomic_set(&br->br_count, 0); -+ br->br_xino_upper = AUFS_XINO_TRUNC_INIT; -+ atomic_set(&br->br_xino_running, 0); -+ br->br_id = au_new_br_id(sb); -+ AuDebugOn(br->br_id < 0); -+ -+ if (au_br_writable(add->perm)) { -+ err = au_wbr_init(br, sb, add->perm, &add->path); -+ if (unlikely(err)) -+ goto out_err; -+ } -+ -+ if (au_opt_test(au_mntflags(sb), XINO)) { -+ err = au_xino_br(sb, br, add->path.dentry->d_inode->i_ino, -+ au_sbr(sb, 0)->br_xino.xi_file, /*do_test*/1); -+ if (unlikely(err)) { -+ AuDebugOn(br->br_xino.xi_file); -+ goto out_err; -+ } -+ } -+ -+ sysaufs_br_init(br); -+ mntget(add->path.mnt); -+ goto out; /* success */ -+ -+out_err: -+ br->br_mnt = NULL; -+out: -+ return err; -+} -+ -+static void au_br_do_add_brp(struct au_sbinfo *sbinfo, aufs_bindex_t bindex, -+ struct au_branch *br, aufs_bindex_t bend, -+ aufs_bindex_t amount) -+{ -+ struct au_branch **brp; -+ -+ AuRwMustWriteLock(&sbinfo->si_rwsem); -+ -+ brp = sbinfo->si_branch + bindex; -+ memmove(brp + 1, brp, sizeof(*brp) * amount); -+ *brp = br; -+ sbinfo->si_bend++; -+ if (unlikely(bend < 0)) -+ sbinfo->si_bend = 0; -+} -+ -+static void au_br_do_add_hdp(struct au_dinfo *dinfo, aufs_bindex_t bindex, -+ aufs_bindex_t bend, aufs_bindex_t amount) -+{ -+ struct au_hdentry *hdp; -+ -+ AuRwMustWriteLock(&dinfo->di_rwsem); -+ -+ hdp = dinfo->di_hdentry + bindex; -+ memmove(hdp + 1, hdp, sizeof(*hdp) * amount); -+ au_h_dentry_init(hdp); -+ dinfo->di_bend++; -+ if (unlikely(bend < 0)) -+ dinfo->di_bstart = 0; -+} -+ -+static void au_br_do_add_hip(struct au_iinfo *iinfo, aufs_bindex_t bindex, -+ aufs_bindex_t bend, aufs_bindex_t amount) -+{ -+ struct au_hinode *hip; -+ -+ AuRwMustWriteLock(&iinfo->ii_rwsem); -+ -+ hip = iinfo->ii_hinode + bindex; -+ memmove(hip + 1, hip, sizeof(*hip) * amount); -+ hip->hi_inode = NULL; -+ au_hn_init(hip); -+ iinfo->ii_bend++; -+ if (unlikely(bend < 0)) -+ iinfo->ii_bstart = 0; -+} -+ -+static void au_br_do_add(struct super_block *sb, struct dentry *h_dentry, -+ struct au_branch *br, aufs_bindex_t bindex) -+{ -+ struct dentry *root; -+ struct inode *root_inode; -+ aufs_bindex_t bend, amount; -+ -+ root = sb->s_root; -+ root_inode = root->d_inode; -+ bend = au_sbend(sb); -+ amount = bend + 1 - bindex; -+ au_br_do_add_brp(au_sbi(sb), bindex, br, bend, amount); -+ au_br_do_add_hdp(au_di(root), bindex, bend, amount); -+ au_br_do_add_hip(au_ii(root_inode), bindex, bend, amount); -+ au_set_h_dptr(root, bindex, dget(h_dentry)); -+ au_set_h_iptr(root_inode, bindex, au_igrab(h_dentry->d_inode), -+ /*flags*/0); -+} -+ -+int au_br_add(struct super_block *sb, struct au_opt_add *add, int remount) -+{ -+ int err; -+ aufs_bindex_t bend, add_bindex; -+ struct dentry *root, *h_dentry; -+ struct inode *root_inode; -+ struct au_branch *add_branch; -+ -+ root = sb->s_root; -+ root_inode = root->d_inode; -+ IMustLock(root_inode); -+ err = test_add(sb, add, remount); -+ if (unlikely(err < 0)) -+ goto out; -+ if (err) { -+ err = 0; -+ goto out; /* success */ -+ } -+ -+ bend = au_sbend(sb); -+ add_branch = au_br_alloc(sb, bend + 2, add->perm); -+ err = PTR_ERR(add_branch); -+ if (IS_ERR(add_branch)) -+ goto out; -+ -+ err = au_br_init(add_branch, sb, add); -+ if (unlikely(err)) { -+ au_br_do_free(add_branch); -+ goto out; -+ } -+ -+ add_bindex = add->bindex; -+ h_dentry = add->path.dentry; -+ if (!remount) -+ au_br_do_add(sb, h_dentry, add_branch, add_bindex); -+ else { -+ sysaufs_brs_del(sb, add_bindex); -+ au_br_do_add(sb, h_dentry, add_branch, add_bindex); -+ sysaufs_brs_add(sb, add_bindex); -+ } -+ -+ if (!add_bindex) { -+ au_cpup_attr_all(root_inode, /*force*/1); -+ sb->s_maxbytes = h_dentry->d_sb->s_maxbytes; -+ } else -+ au_add_nlink(root_inode, h_dentry->d_inode); -+ -+ /* -+ * this test/set prevents aufs from handling unnecesary notify events -+ * of xino files, in a case of re-adding a writable branch which was -+ * once detached from aufs. -+ */ -+ if (au_xino_brid(sb) < 0 -+ && au_br_writable(add_branch->br_perm) -+ && !au_test_fs_bad_xino(h_dentry->d_sb) -+ && add_branch->br_xino.xi_file -+ && add_branch->br_xino.xi_file->f_dentry->d_parent == h_dentry) -+ au_xino_brid_set(sb, add_branch->br_id); -+ -+out: -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * delete a branch -+ */ -+ -+/* to show the line number, do not make it inlined function */ -+#define AuVerbose(do_info, fmt, ...) do { \ -+ if (do_info) \ -+ pr_info(fmt, ##__VA_ARGS__); \ -+} while (0) -+ -+/* -+ * test if the branch is deletable or not. -+ */ -+static int test_dentry_busy(struct dentry *root, aufs_bindex_t bindex, -+ unsigned int sigen, const unsigned int verbose) -+{ -+ int err, i, j, ndentry; -+ aufs_bindex_t bstart, bend; -+ struct au_dcsub_pages dpages; -+ struct au_dpage *dpage; -+ struct dentry *d; -+ struct inode *inode; -+ -+ err = au_dpages_init(&dpages, GFP_NOFS); -+ if (unlikely(err)) -+ goto out; -+ err = au_dcsub_pages(&dpages, root, NULL, NULL); -+ if (unlikely(err)) -+ goto out_dpages; -+ -+ for (i = 0; !err && i < dpages.ndpage; i++) { -+ dpage = dpages.dpages + i; -+ ndentry = dpage->ndentry; -+ for (j = 0; !err && j < ndentry; j++) { -+ d = dpage->dentries[j]; -+ AuDebugOn(!atomic_read(&d->d_count)); -+ if (!au_digen_test(d, sigen)) { -+ di_read_lock_child(d, AuLock_IR); -+ if (unlikely(au_dbrange_test(d))) { -+ di_read_unlock(d, AuLock_IR); -+ continue; -+ } -+ } else { -+ di_write_lock_child(d); -+ if (unlikely(au_dbrange_test(d))) { -+ di_write_unlock(d); -+ continue; -+ } -+ err = au_reval_dpath(d, sigen); -+ if (!err) -+ di_downgrade_lock(d, AuLock_IR); -+ else { -+ di_write_unlock(d); -+ break; -+ } -+ } -+ -+ /* AuDbgDentry(d); */ -+ inode = d->d_inode; -+ bstart = au_dbstart(d); -+ bend = au_dbend(d); -+ if (bstart <= bindex -+ && bindex <= bend -+ && au_h_dptr(d, bindex) -+ && ((inode && !S_ISDIR(inode->i_mode)) -+ || bstart == bend)) { -+ err = -EBUSY; -+ AuVerbose(verbose, "busy %.*s\n", AuDLNPair(d)); -+ AuDbgDentry(d); -+ } -+ di_read_unlock(d, AuLock_IR); -+ } -+ } -+ -+out_dpages: -+ au_dpages_free(&dpages); -+out: -+ return err; -+} -+ -+static int test_inode_busy(struct super_block *sb, aufs_bindex_t bindex, -+ unsigned int sigen, const unsigned int verbose) -+{ -+ int err; -+ unsigned long long max, ull; -+ struct inode *i, **array; -+ aufs_bindex_t bstart, bend; -+ -+ array = au_iarray_alloc(sb, &max); -+ err = PTR_ERR(array); -+ if (IS_ERR(array)) -+ goto out; -+ -+ err = 0; -+ AuDbg("b%d\n", bindex); -+ for (ull = 0; !err && ull < max; ull++) { -+ i = array[ull]; -+ if (i->i_ino == AUFS_ROOT_INO) -+ continue; -+ -+ /* AuDbgInode(i); */ -+ if (au_iigen(i) == sigen) -+ ii_read_lock_child(i); -+ else { -+ ii_write_lock_child(i); -+ err = au_refresh_hinode_self(i); -+ au_iigen_dec(i); -+ if (!err) -+ ii_downgrade_lock(i); -+ else { -+ ii_write_unlock(i); -+ break; -+ } -+ } -+ -+ bstart = au_ibstart(i); -+ bend = au_ibend(i); -+ if (bstart <= bindex -+ && bindex <= bend -+ && au_h_iptr(i, bindex) -+ && (!S_ISDIR(i->i_mode) || bstart == bend)) { -+ err = -EBUSY; -+ AuVerbose(verbose, "busy i%lu\n", i->i_ino); -+ AuDbgInode(i); -+ } -+ ii_read_unlock(i); -+ } -+ au_iarray_free(array, max); -+ -+out: -+ return err; -+} -+ -+static int test_children_busy(struct dentry *root, aufs_bindex_t bindex, -+ const unsigned int verbose) -+{ -+ int err; -+ unsigned int sigen; -+ -+ sigen = au_sigen(root->d_sb); -+ DiMustNoWaiters(root); -+ IiMustNoWaiters(root->d_inode); -+ di_write_unlock(root); -+ err = test_dentry_busy(root, bindex, sigen, verbose); -+ if (!err) -+ err = test_inode_busy(root->d_sb, bindex, sigen, verbose); -+ di_write_lock_child(root); /* aufs_write_lock() calls ..._child() */ -+ -+ return err; -+} -+ -+static void au_br_do_del_brp(struct au_sbinfo *sbinfo, -+ const aufs_bindex_t bindex, -+ const aufs_bindex_t bend) -+{ -+ struct au_branch **brp, **p; -+ -+ AuRwMustWriteLock(&sbinfo->si_rwsem); -+ -+ brp = sbinfo->si_branch + bindex; -+ if (bindex < bend) -+ memmove(brp, brp + 1, sizeof(*brp) * (bend - bindex)); -+ sbinfo->si_branch[0 + bend] = NULL; -+ sbinfo->si_bend--; -+ -+ p = krealloc(sbinfo->si_branch, sizeof(*p) * bend, GFP_NOFS); -+ if (p) -+ sbinfo->si_branch = p; -+ /* harmless error */ -+} -+ -+static void au_br_do_del_hdp(struct au_dinfo *dinfo, const aufs_bindex_t bindex, -+ const aufs_bindex_t bend) -+{ -+ struct au_hdentry *hdp, *p; -+ -+ AuRwMustWriteLock(&dinfo->di_rwsem); -+ -+ hdp = dinfo->di_hdentry; -+ if (bindex < bend) -+ memmove(hdp + bindex, hdp + bindex + 1, -+ sizeof(*hdp) * (bend - bindex)); -+ hdp[0 + bend].hd_dentry = NULL; -+ dinfo->di_bend--; -+ -+ p = krealloc(hdp, sizeof(*p) * bend, GFP_NOFS); -+ if (p) -+ dinfo->di_hdentry = p; -+ /* harmless error */ -+} -+ -+static void au_br_do_del_hip(struct au_iinfo *iinfo, const aufs_bindex_t bindex, -+ const aufs_bindex_t bend) -+{ -+ struct au_hinode *hip, *p; -+ -+ AuRwMustWriteLock(&iinfo->ii_rwsem); -+ -+ hip = iinfo->ii_hinode + bindex; -+ if (bindex < bend) -+ memmove(hip, hip + 1, sizeof(*hip) * (bend - bindex)); -+ iinfo->ii_hinode[0 + bend].hi_inode = NULL; -+ au_hn_init(iinfo->ii_hinode + bend); -+ iinfo->ii_bend--; -+ -+ p = krealloc(iinfo->ii_hinode, sizeof(*p) * bend, GFP_NOFS); -+ if (p) -+ iinfo->ii_hinode = p; -+ /* harmless error */ -+} -+ -+static void au_br_do_del(struct super_block *sb, aufs_bindex_t bindex, -+ struct au_branch *br) -+{ -+ aufs_bindex_t bend; -+ struct au_sbinfo *sbinfo; -+ struct dentry *root; -+ struct inode *inode; -+ -+ SiMustWriteLock(sb); -+ -+ root = sb->s_root; -+ inode = root->d_inode; -+ sbinfo = au_sbi(sb); -+ bend = sbinfo->si_bend; -+ -+ dput(au_h_dptr(root, bindex)); -+ au_hiput(au_hi(inode, bindex)); -+ au_br_do_free(br); -+ -+ au_br_do_del_brp(sbinfo, bindex, bend); -+ au_br_do_del_hdp(au_di(root), bindex, bend); -+ au_br_do_del_hip(au_ii(inode), bindex, bend); -+} -+ -+int au_br_del(struct super_block *sb, struct au_opt_del *del, int remount) -+{ -+ int err, rerr, i; -+ unsigned int mnt_flags; -+ aufs_bindex_t bindex, bend, br_id; -+ unsigned char do_wh, verbose; -+ struct au_branch *br; -+ struct au_wbr *wbr; -+ -+ err = 0; -+ bindex = au_find_dbindex(sb->s_root, del->h_path.dentry); -+ if (bindex < 0) { -+ if (remount) -+ goto out; /* success */ -+ err = -ENOENT; -+ pr_err("%s no such branch\n", del->pathname); -+ goto out; -+ } -+ AuDbg("bindex b%d\n", bindex); -+ -+ err = -EBUSY; -+ mnt_flags = au_mntflags(sb); -+ verbose = !!au_opt_test(mnt_flags, VERBOSE); -+ bend = au_sbend(sb); -+ if (unlikely(!bend)) { -+ AuVerbose(verbose, "no more branches left\n"); -+ goto out; -+ } -+ br = au_sbr(sb, bindex); -+ i = atomic_read(&br->br_count); -+ if (unlikely(i)) { -+ AuVerbose(verbose, "%d file(s) opened\n", i); -+ goto out; -+ } -+ -+ wbr = br->br_wbr; -+ do_wh = wbr && (wbr->wbr_whbase || wbr->wbr_plink || wbr->wbr_orph); -+ if (do_wh) { -+ /* instead of WbrWhMustWriteLock(wbr) */ -+ SiMustWriteLock(sb); -+ for (i = 0; i < AuBrWh_Last; i++) { -+ dput(wbr->wbr_wh[i]); -+ wbr->wbr_wh[i] = NULL; -+ } -+ } -+ -+ err = test_children_busy(sb->s_root, bindex, verbose); -+ if (unlikely(err)) { -+ if (do_wh) -+ goto out_wh; -+ goto out; -+ } -+ -+ err = 0; -+ br_id = br->br_id; -+ if (!remount) -+ au_br_do_del(sb, bindex, br); -+ else { -+ sysaufs_brs_del(sb, bindex); -+ au_br_do_del(sb, bindex, br); -+ sysaufs_brs_add(sb, bindex); -+ } -+ -+ if (!bindex) { -+ au_cpup_attr_all(sb->s_root->d_inode, /*force*/1); -+ sb->s_maxbytes = au_sbr_sb(sb, 0)->s_maxbytes; -+ } else -+ au_sub_nlink(sb->s_root->d_inode, del->h_path.dentry->d_inode); -+ if (au_opt_test(mnt_flags, PLINK)) -+ au_plink_half_refresh(sb, br_id); -+ -+ if (au_xino_brid(sb) == br_id) -+ au_xino_brid_set(sb, -1); -+ goto out; /* success */ -+ -+out_wh: -+ /* revert */ -+ rerr = au_br_init_wh(sb, br, br->br_perm, del->h_path.dentry); -+ if (rerr) -+ pr_warning("failed re-creating base whiteout, %s. (%d)\n", -+ del->pathname, rerr); -+out: -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * change a branch permission -+ */ -+ -+static void au_warn_ima(void) -+{ -+#ifdef CONFIG_IMA -+ /* since it doesn't support mark_files_ro() */ -+ AuWarn1("RW -> RO makes IMA to produce wrong message\n"); -+#endif -+} -+ -+static int do_need_sigen_inc(int a, int b) -+{ -+ return au_br_whable(a) && !au_br_whable(b); -+} -+ -+static int need_sigen_inc(int old, int new) -+{ -+ return do_need_sigen_inc(old, new) -+ || do_need_sigen_inc(new, old); -+} -+ -+static unsigned long long au_farray_cb(void *a, -+ unsigned long long max __maybe_unused, -+ void *arg) -+{ -+ unsigned long long n; -+ struct file **p, *f; -+ struct super_block *sb = arg; -+ -+ n = 0; -+ p = a; -+ lg_global_lock(files_lglock); -+ do_file_list_for_each_entry(sb, f) { -+ if (au_fi(f) -+ && !special_file(f->f_dentry->d_inode->i_mode)) { -+ get_file(f); -+ *p++ = f; -+ n++; -+ AuDebugOn(n > max); -+ } -+ } while_file_list_for_each_entry; -+ lg_global_unlock(files_lglock); -+ -+ return n; -+} -+ -+static struct file **au_farray_alloc(struct super_block *sb, -+ unsigned long long *max) -+{ -+ *max = atomic_long_read(&au_sbi(sb)->si_nfiles); -+ return au_array_alloc(max, au_farray_cb, sb); -+} -+ -+static void au_farray_free(struct file **a, unsigned long long max) -+{ -+ unsigned long long ull; -+ -+ for (ull = 0; ull < max; ull++) -+ if (a[ull]) -+ fput(a[ull]); -+ au_array_free(a); -+} -+ -+static int au_br_mod_files_ro(struct super_block *sb, aufs_bindex_t bindex) -+{ -+ int err, do_warn; -+ unsigned long long ull, max; -+ aufs_bindex_t br_id; -+ struct file *file, *hf, **array; -+ struct inode *inode; -+ struct au_hfile *hfile; -+ -+ array = au_farray_alloc(sb, &max); -+ err = PTR_ERR(array); -+ if (IS_ERR(array)) -+ goto out; -+ -+ do_warn = 0; -+ br_id = au_sbr_id(sb, bindex); -+ for (ull = 0; ull < max; ull++) { -+ file = array[ull]; -+ -+ /* AuDbg("%.*s\n", AuDLNPair(file->f_dentry)); */ -+ fi_read_lock(file); -+ if (unlikely(au_test_mmapped(file))) { -+ err = -EBUSY; -+ AuDbgFile(file); -+ FiMustNoWaiters(file); -+ fi_read_unlock(file); -+ goto out_array; -+ } -+ -+ inode = file->f_dentry->d_inode; -+ hfile = &au_fi(file)->fi_htop; -+ hf = hfile->hf_file; -+ if (!S_ISREG(inode->i_mode) -+ || !(file->f_mode & FMODE_WRITE) -+ || hfile->hf_br->br_id != br_id -+ || !(hf->f_mode & FMODE_WRITE)) -+ array[ull] = NULL; -+ else { -+ do_warn = 1; -+ get_file(file); -+ } -+ -+ FiMustNoWaiters(file); -+ fi_read_unlock(file); -+ fput(file); -+ } -+ -+ err = 0; -+ if (do_warn) -+ au_warn_ima(); -+ -+ for (ull = 0; ull < max; ull++) { -+ file = array[ull]; -+ if (!file) -+ continue; -+ -+ /* todo: already flushed? */ -+ /* cf. fs/super.c:mark_files_ro() */ -+ /* fi_read_lock(file); */ -+ hfile = &au_fi(file)->fi_htop; -+ hf = hfile->hf_file; -+ /* fi_read_unlock(file); */ -+ spin_lock(&hf->f_lock); -+ hf->f_mode &= ~FMODE_WRITE; -+ spin_unlock(&hf->f_lock); -+ if (!file_check_writeable(hf)) { -+ file_release_write(hf); -+ mnt_drop_write(hf->f_vfsmnt); -+ } -+ } -+ -+out_array: -+ au_farray_free(array, max); -+out: -+ AuTraceErr(err); -+ return err; -+} -+ -+int au_br_mod(struct super_block *sb, struct au_opt_mod *mod, int remount, -+ int *do_refresh) -+{ -+ int err, rerr; -+ aufs_bindex_t bindex; -+ struct path path; -+ struct dentry *root; -+ struct au_branch *br; -+ -+ root = sb->s_root; -+ bindex = au_find_dbindex(root, mod->h_root); -+ if (bindex < 0) { -+ if (remount) -+ return 0; /* success */ -+ err = -ENOENT; -+ pr_err("%s no such branch\n", mod->path); -+ goto out; -+ } -+ AuDbg("bindex b%d\n", bindex); -+ -+ err = test_br(mod->h_root->d_inode, mod->perm, mod->path); -+ if (unlikely(err)) -+ goto out; -+ -+ br = au_sbr(sb, bindex); -+ if (br->br_perm == mod->perm) -+ return 0; /* success */ -+ -+ if (au_br_writable(br->br_perm)) { -+ /* remove whiteout base */ -+ err = au_br_init_wh(sb, br, mod->perm, mod->h_root); -+ if (unlikely(err)) -+ goto out; -+ -+ if (!au_br_writable(mod->perm)) { -+ /* rw --> ro, file might be mmapped */ -+ DiMustNoWaiters(root); -+ IiMustNoWaiters(root->d_inode); -+ di_write_unlock(root); -+ err = au_br_mod_files_ro(sb, bindex); -+ /* aufs_write_lock() calls ..._child() */ -+ di_write_lock_child(root); -+ -+ if (unlikely(err)) { -+ rerr = -ENOMEM; -+ br->br_wbr = kmalloc(sizeof(*br->br_wbr), -+ GFP_NOFS); -+ if (br->br_wbr) { -+ path.mnt = br->br_mnt; -+ path.dentry = mod->h_root; -+ rerr = au_wbr_init(br, sb, br->br_perm, -+ &path); -+ } -+ if (unlikely(rerr)) { -+ AuIOErr("nested error %d (%d)\n", -+ rerr, err); -+ br->br_perm = mod->perm; -+ } -+ } -+ } -+ } else if (au_br_writable(mod->perm)) { -+ /* ro --> rw */ -+ err = -ENOMEM; -+ br->br_wbr = kmalloc(sizeof(*br->br_wbr), GFP_NOFS); -+ if (br->br_wbr) { -+ path.mnt = br->br_mnt; -+ path.dentry = mod->h_root; -+ err = au_wbr_init(br, sb, mod->perm, &path); -+ if (unlikely(err)) { -+ kfree(br->br_wbr); -+ br->br_wbr = NULL; -+ } -+ } -+ } -+ -+ if (!err) { -+ *do_refresh |= need_sigen_inc(br->br_perm, mod->perm); -+ br->br_perm = mod->perm; -+ } -+ -+out: -+ AuTraceErr(err); -+ return err; -+} -diff -Nur linux-2.6.36.orig/fs/aufs/branch.h linux-2.6.36/fs/aufs/branch.h ---- linux-2.6.36.orig/fs/aufs/branch.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/branch.h 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,229 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * branch filesystems and xino for them -+ */ -+ -+#ifndef __AUFS_BRANCH_H__ -+#define __AUFS_BRANCH_H__ -+ -+#ifdef __KERNEL__ -+ -+#include -+#include -+#include -+#include "dynop.h" -+#include "rwsem.h" -+#include "super.h" -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* a xino file */ -+struct au_xino_file { -+ struct file *xi_file; -+ struct mutex xi_nondir_mtx; -+ -+ /* todo: make xino files an array to support huge inode number */ -+ -+#ifdef CONFIG_DEBUG_FS -+ struct dentry *xi_dbgaufs; -+#endif -+}; -+ -+/* members for writable branch only */ -+enum {AuBrWh_BASE, AuBrWh_PLINK, AuBrWh_ORPH, AuBrWh_Last}; -+struct au_wbr { -+ struct au_rwsem wbr_wh_rwsem; -+ struct dentry *wbr_wh[AuBrWh_Last]; -+ atomic_t wbr_wh_running; -+#define wbr_whbase wbr_wh[AuBrWh_BASE] /* whiteout base */ -+#define wbr_plink wbr_wh[AuBrWh_PLINK] /* pseudo-link dir */ -+#define wbr_orph wbr_wh[AuBrWh_ORPH] /* dir for orphans */ -+ -+ /* mfs mode */ -+ unsigned long long wbr_bytes; -+}; -+ -+/* ext2 has 3 types of operations at least, ext3 has 4 */ -+#define AuBrDynOp (AuDyLast * 4) -+ -+/* protected by superblock rwsem */ -+struct au_branch { -+ struct au_xino_file br_xino; -+ -+ aufs_bindex_t br_id; -+ -+ int br_perm; -+ struct vfsmount *br_mnt; -+ spinlock_t br_dykey_lock; -+ struct au_dykey *br_dykey[AuBrDynOp]; -+ atomic_t br_count; -+ -+ struct au_wbr *br_wbr; -+ -+ /* xino truncation */ -+ blkcnt_t br_xino_upper; /* watermark in blocks */ -+ atomic_t br_xino_running; -+ -+#ifdef CONFIG_AUFS_HFSNOTIFY -+ struct fsnotify_group *br_hfsn_group; -+ struct fsnotify_ops br_hfsn_ops; -+#endif -+ -+#ifdef CONFIG_SYSFS -+ /* an entry under sysfs per mount-point */ -+ char br_name[8]; -+ struct attribute br_attr; -+#endif -+}; -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* branch permission and attribute */ -+enum { -+ AuBrPerm_RW, /* writable, linkable wh */ -+ AuBrPerm_RO, /* readonly, no wh */ -+ AuBrPerm_RR, /* natively readonly, no wh */ -+ -+ AuBrPerm_RWNoLinkWH, /* un-linkable whiteouts */ -+ -+ AuBrPerm_ROWH, /* whiteout-able */ -+ AuBrPerm_RRWH, /* whiteout-able */ -+ -+ AuBrPerm_Last -+}; -+ -+static inline int au_br_writable(int brperm) -+{ -+ return brperm == AuBrPerm_RW || brperm == AuBrPerm_RWNoLinkWH; -+} -+ -+static inline int au_br_whable(int brperm) -+{ -+ return brperm == AuBrPerm_RW -+ || brperm == AuBrPerm_ROWH -+ || brperm == AuBrPerm_RRWH; -+} -+ -+static inline int au_br_rdonly(struct au_branch *br) -+{ -+ return ((br->br_mnt->mnt_sb->s_flags & MS_RDONLY) -+ || !au_br_writable(br->br_perm)) -+ ? -EROFS : 0; -+} -+ -+static inline int au_br_hnotifyable(int brperm __maybe_unused) -+{ -+#ifdef CONFIG_AUFS_HNOTIFY -+ return brperm != AuBrPerm_RR && brperm != AuBrPerm_RRWH; -+#else -+ return 0; -+#endif -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* branch.c */ -+struct au_sbinfo; -+void au_br_free(struct au_sbinfo *sinfo); -+int au_br_index(struct super_block *sb, aufs_bindex_t br_id); -+struct au_opt_add; -+int au_br_add(struct super_block *sb, struct au_opt_add *add, int remount); -+struct au_opt_del; -+int au_br_del(struct super_block *sb, struct au_opt_del *del, int remount); -+struct au_opt_mod; -+int au_br_mod(struct super_block *sb, struct au_opt_mod *mod, int remount, -+ int *do_refresh); -+ -+/* xino.c */ -+static const loff_t au_loff_max = LLONG_MAX; -+ -+int au_xib_trunc(struct super_block *sb); -+ssize_t xino_fread(au_readf_t func, struct file *file, void *buf, size_t size, -+ loff_t *pos); -+ssize_t xino_fwrite(au_writef_t func, struct file *file, void *buf, size_t size, -+ loff_t *pos); -+struct file *au_xino_create2(struct file *base_file, struct file *copy_src); -+struct file *au_xino_create(struct super_block *sb, char *fname, int silent); -+ino_t au_xino_new_ino(struct super_block *sb); -+void au_xino_delete_inode(struct inode *inode, const int unlinked); -+int au_xino_write(struct super_block *sb, aufs_bindex_t bindex, ino_t h_ino, -+ ino_t ino); -+int au_xino_read(struct super_block *sb, aufs_bindex_t bindex, ino_t h_ino, -+ ino_t *ino); -+int au_xino_br(struct super_block *sb, struct au_branch *br, ino_t hino, -+ struct file *base_file, int do_test); -+int au_xino_trunc(struct super_block *sb, aufs_bindex_t bindex); -+ -+struct au_opt_xino; -+int au_xino_set(struct super_block *sb, struct au_opt_xino *xino, int remount); -+void au_xino_clr(struct super_block *sb); -+struct file *au_xino_def(struct super_block *sb); -+int au_xino_path(struct seq_file *seq, struct file *file); -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* Superblock to branch */ -+static inline -+aufs_bindex_t au_sbr_id(struct super_block *sb, aufs_bindex_t bindex) -+{ -+ return au_sbr(sb, bindex)->br_id; -+} -+ -+static inline -+struct vfsmount *au_sbr_mnt(struct super_block *sb, aufs_bindex_t bindex) -+{ -+ return au_sbr(sb, bindex)->br_mnt; -+} -+ -+static inline -+struct super_block *au_sbr_sb(struct super_block *sb, aufs_bindex_t bindex) -+{ -+ return au_sbr_mnt(sb, bindex)->mnt_sb; -+} -+ -+static inline void au_sbr_put(struct super_block *sb, aufs_bindex_t bindex) -+{ -+ atomic_dec(&au_sbr(sb, bindex)->br_count); -+} -+ -+static inline int au_sbr_perm(struct super_block *sb, aufs_bindex_t bindex) -+{ -+ return au_sbr(sb, bindex)->br_perm; -+} -+ -+static inline int au_sbr_whable(struct super_block *sb, aufs_bindex_t bindex) -+{ -+ return au_br_whable(au_sbr_perm(sb, bindex)); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * wbr_wh_read_lock, wbr_wh_write_lock -+ * wbr_wh_read_unlock, wbr_wh_write_unlock, wbr_wh_downgrade_lock -+ */ -+AuSimpleRwsemFuncs(wbr_wh, struct au_wbr *wbr, &wbr->wbr_wh_rwsem); -+ -+#define WbrWhMustNoWaiters(wbr) AuRwMustNoWaiters(&wbr->wbr_wh_rwsem) -+#define WbrWhMustAnyLock(wbr) AuRwMustAnyLock(&wbr->wbr_wh_rwsem) -+#define WbrWhMustWriteLock(wbr) AuRwMustWriteLock(&wbr->wbr_wh_rwsem) -+ -+#endif /* __KERNEL__ */ -+#endif /* __AUFS_BRANCH_H__ */ -diff -Nur linux-2.6.36.orig/fs/aufs/conf.mk linux-2.6.36/fs/aufs/conf.mk ---- linux-2.6.36.orig/fs/aufs/conf.mk 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/conf.mk 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,37 @@ -+ -+AuConfStr = CONFIG_AUFS_FS=${CONFIG_AUFS_FS} -+ -+define AuConf -+ifdef ${1} -+AuConfStr += ${1}=${${1}} -+endif -+endef -+ -+AuConfAll = BRANCH_MAX_127 BRANCH_MAX_511 BRANCH_MAX_1023 BRANCH_MAX_32767 \ -+ SBILIST \ -+ HNOTIFY HFSNOTIFY \ -+ EXPORT INO_T_64 \ -+ RDU \ -+ SP_IATTR \ -+ SHWH \ -+ BR_RAMFS \ -+ BR_FUSE POLL \ -+ BR_HFSPLUS \ -+ BDEV_LOOP \ -+ DEBUG MAGIC_SYSRQ -+$(foreach i, ${AuConfAll}, \ -+ $(eval $(call AuConf,CONFIG_AUFS_${i}))) -+ -+AuConfName = ${obj}/conf.str -+${AuConfName}.tmp: FORCE -+ @echo ${AuConfStr} | tr ' ' '\n' | sed -e 's/^/"/' -e 's/$$/\\n"/' > $@ -+${AuConfName}: ${AuConfName}.tmp -+ @diff -q $< $@ > /dev/null 2>&1 || { \ -+ echo ' GEN ' $@; \ -+ cp -p $< $@; \ -+ } -+FORCE: -+clean-files += ${AuConfName} ${AuConfName}.tmp -+${obj}/sysfs.o: ${AuConfName} -+ -+-include ${srctree}/${src}/conf_priv.mk -diff -Nur linux-2.6.36.orig/fs/aufs/cpup.c linux-2.6.36/fs/aufs/cpup.c ---- linux-2.6.36.orig/fs/aufs/cpup.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/cpup.c 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,1063 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * copy-up functions, see wbr_policy.c for copy-down -+ */ -+ -+#include -+#include -+#include -+#include -+#include "aufs.h" -+ -+void au_cpup_attr_flags(struct inode *dst, struct inode *src) -+{ -+ const unsigned int mask = S_DEAD | S_SWAPFILE | S_PRIVATE -+ | S_NOATIME | S_NOCMTIME; -+ -+ dst->i_flags |= src->i_flags & ~mask; -+ if (au_test_fs_notime(dst->i_sb)) -+ dst->i_flags |= S_NOATIME | S_NOCMTIME; -+} -+ -+void au_cpup_attr_timesizes(struct inode *inode) -+{ -+ struct inode *h_inode; -+ -+ h_inode = au_h_iptr(inode, au_ibstart(inode)); -+ fsstack_copy_attr_times(inode, h_inode); -+ fsstack_copy_inode_size(inode, h_inode); -+} -+ -+void au_cpup_attr_nlink(struct inode *inode, int force) -+{ -+ struct inode *h_inode; -+ struct super_block *sb; -+ aufs_bindex_t bindex, bend; -+ -+ sb = inode->i_sb; -+ bindex = au_ibstart(inode); -+ h_inode = au_h_iptr(inode, bindex); -+ if (!force -+ && !S_ISDIR(h_inode->i_mode) -+ && au_opt_test(au_mntflags(sb), PLINK) -+ && au_plink_test(inode)) -+ return; -+ -+ inode->i_nlink = h_inode->i_nlink; -+ -+ /* -+ * fewer nlink makes find(1) noisy, but larger nlink doesn't. -+ * it may includes whplink directory. -+ */ -+ if (S_ISDIR(h_inode->i_mode)) { -+ bend = au_ibend(inode); -+ for (bindex++; bindex <= bend; bindex++) { -+ h_inode = au_h_iptr(inode, bindex); -+ if (h_inode) -+ au_add_nlink(inode, h_inode); -+ } -+ } -+} -+ -+void au_cpup_attr_changeable(struct inode *inode) -+{ -+ struct inode *h_inode; -+ -+ h_inode = au_h_iptr(inode, au_ibstart(inode)); -+ inode->i_mode = h_inode->i_mode; -+ inode->i_uid = h_inode->i_uid; -+ inode->i_gid = h_inode->i_gid; -+ au_cpup_attr_timesizes(inode); -+ au_cpup_attr_flags(inode, h_inode); -+} -+ -+void au_cpup_igen(struct inode *inode, struct inode *h_inode) -+{ -+ struct au_iinfo *iinfo = au_ii(inode); -+ -+ IiMustWriteLock(inode); -+ -+ iinfo->ii_higen = h_inode->i_generation; -+ iinfo->ii_hsb1 = h_inode->i_sb; -+} -+ -+void au_cpup_attr_all(struct inode *inode, int force) -+{ -+ struct inode *h_inode; -+ -+ h_inode = au_h_iptr(inode, au_ibstart(inode)); -+ au_cpup_attr_changeable(inode); -+ if (inode->i_nlink > 0) -+ au_cpup_attr_nlink(inode, force); -+ inode->i_rdev = h_inode->i_rdev; -+ inode->i_blkbits = h_inode->i_blkbits; -+ au_cpup_igen(inode, h_inode); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* Note: dt_dentry and dt_h_dentry are not dget/dput-ed */ -+ -+/* keep the timestamps of the parent dir when cpup */ -+void au_dtime_store(struct au_dtime *dt, struct dentry *dentry, -+ struct path *h_path) -+{ -+ struct inode *h_inode; -+ -+ dt->dt_dentry = dentry; -+ dt->dt_h_path = *h_path; -+ h_inode = h_path->dentry->d_inode; -+ dt->dt_atime = h_inode->i_atime; -+ dt->dt_mtime = h_inode->i_mtime; -+ /* smp_mb(); */ -+} -+ -+void au_dtime_revert(struct au_dtime *dt) -+{ -+ struct iattr attr; -+ int err; -+ -+ attr.ia_atime = dt->dt_atime; -+ attr.ia_mtime = dt->dt_mtime; -+ attr.ia_valid = ATTR_FORCE | ATTR_MTIME | ATTR_MTIME_SET -+ | ATTR_ATIME | ATTR_ATIME_SET; -+ -+ err = vfsub_notify_change(&dt->dt_h_path, &attr); -+ if (unlikely(err)) -+ pr_warning("restoring timestamps failed(%d). ignored\n", err); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static noinline_for_stack -+int cpup_iattr(struct dentry *dst, aufs_bindex_t bindex, struct dentry *h_src) -+{ -+ int err, sbits; -+ struct iattr ia; -+ struct path h_path; -+ struct inode *h_isrc, *h_idst; -+ -+ h_path.dentry = au_h_dptr(dst, bindex); -+ h_idst = h_path.dentry->d_inode; -+ h_path.mnt = au_sbr_mnt(dst->d_sb, bindex); -+ h_isrc = h_src->d_inode; -+ ia.ia_valid = ATTR_FORCE | ATTR_UID | ATTR_GID -+ | ATTR_ATIME | ATTR_MTIME -+ | ATTR_ATIME_SET | ATTR_MTIME_SET; -+ ia.ia_uid = h_isrc->i_uid; -+ ia.ia_gid = h_isrc->i_gid; -+ ia.ia_atime = h_isrc->i_atime; -+ ia.ia_mtime = h_isrc->i_mtime; -+ if (h_idst->i_mode != h_isrc->i_mode -+ && !S_ISLNK(h_idst->i_mode)) { -+ ia.ia_valid |= ATTR_MODE; -+ ia.ia_mode = h_isrc->i_mode; -+ } -+ sbits = !!(h_isrc->i_mode & (S_ISUID | S_ISGID)); -+ au_cpup_attr_flags(h_idst, h_isrc); -+ err = vfsub_notify_change(&h_path, &ia); -+ -+ /* is this nfs only? */ -+ if (!err && sbits && au_test_nfs(h_path.dentry->d_sb)) { -+ ia.ia_valid = ATTR_FORCE | ATTR_MODE; -+ ia.ia_mode = h_isrc->i_mode; -+ err = vfsub_notify_change(&h_path, &ia); -+ } -+ -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int au_do_copy_file(struct file *dst, struct file *src, loff_t len, -+ char *buf, unsigned long blksize) -+{ -+ int err; -+ size_t sz, rbytes, wbytes; -+ unsigned char all_zero; -+ char *p, *zp; -+ struct mutex *h_mtx; -+ /* reduce stack usage */ -+ struct iattr *ia; -+ -+ zp = page_address(ZERO_PAGE(0)); -+ if (unlikely(!zp)) -+ return -ENOMEM; /* possible? */ -+ -+ err = 0; -+ all_zero = 0; -+ while (len) { -+ AuDbg("len %lld\n", len); -+ sz = blksize; -+ if (len < blksize) -+ sz = len; -+ -+ rbytes = 0; -+ /* todo: signal_pending? */ -+ while (!rbytes || err == -EAGAIN || err == -EINTR) { -+ rbytes = vfsub_read_k(src, buf, sz, &src->f_pos); -+ err = rbytes; -+ } -+ if (unlikely(err < 0)) -+ break; -+ -+ all_zero = 0; -+ if (len >= rbytes && rbytes == blksize) -+ all_zero = !memcmp(buf, zp, rbytes); -+ if (!all_zero) { -+ wbytes = rbytes; -+ p = buf; -+ while (wbytes) { -+ size_t b; -+ -+ b = vfsub_write_k(dst, p, wbytes, &dst->f_pos); -+ err = b; -+ /* todo: signal_pending? */ -+ if (unlikely(err == -EAGAIN || err == -EINTR)) -+ continue; -+ if (unlikely(err < 0)) -+ break; -+ wbytes -= b; -+ p += b; -+ } -+ } else { -+ loff_t res; -+ -+ AuLabel(hole); -+ res = vfsub_llseek(dst, rbytes, SEEK_CUR); -+ err = res; -+ if (unlikely(res < 0)) -+ break; -+ } -+ len -= rbytes; -+ err = 0; -+ } -+ -+ /* the last block may be a hole */ -+ if (!err && all_zero) { -+ AuLabel(last hole); -+ -+ err = 1; -+ if (au_test_nfs(dst->f_dentry->d_sb)) { -+ /* nfs requires this step to make last hole */ -+ /* is this only nfs? */ -+ do { -+ /* todo: signal_pending? */ -+ err = vfsub_write_k(dst, "\0", 1, &dst->f_pos); -+ } while (err == -EAGAIN || err == -EINTR); -+ if (err == 1) -+ dst->f_pos--; -+ } -+ -+ if (err == 1) { -+ ia = (void *)buf; -+ ia->ia_size = dst->f_pos; -+ ia->ia_valid = ATTR_SIZE | ATTR_FILE; -+ ia->ia_file = dst; -+ h_mtx = &dst->f_dentry->d_inode->i_mutex; -+ mutex_lock_nested(h_mtx, AuLsc_I_CHILD2); -+ err = vfsub_notify_change(&dst->f_path, ia); -+ mutex_unlock(h_mtx); -+ } -+ } -+ -+ return err; -+} -+ -+int au_copy_file(struct file *dst, struct file *src, loff_t len) -+{ -+ int err; -+ unsigned long blksize; -+ unsigned char do_kfree; -+ char *buf; -+ -+ err = -ENOMEM; -+ blksize = dst->f_dentry->d_sb->s_blocksize; -+ if (!blksize || PAGE_SIZE < blksize) -+ blksize = PAGE_SIZE; -+ AuDbg("blksize %lu\n", blksize); -+ do_kfree = (blksize != PAGE_SIZE && blksize >= sizeof(struct iattr *)); -+ if (do_kfree) -+ buf = kmalloc(blksize, GFP_NOFS); -+ else -+ buf = (void *)__get_free_page(GFP_NOFS); -+ if (unlikely(!buf)) -+ goto out; -+ -+ if (len > (1 << 22)) -+ AuDbg("copying a large file %lld\n", (long long)len); -+ -+ src->f_pos = 0; -+ dst->f_pos = 0; -+ err = au_do_copy_file(dst, src, len, buf, blksize); -+ if (do_kfree) -+ kfree(buf); -+ else -+ free_page((unsigned long)buf); -+ -+out: -+ return err; -+} -+ -+/* -+ * to support a sparse file which is opened with O_APPEND, -+ * we need to close the file. -+ */ -+static int au_cp_regular(struct dentry *dentry, aufs_bindex_t bdst, -+ aufs_bindex_t bsrc, loff_t len) -+{ -+ int err, i; -+ enum { SRC, DST }; -+ struct { -+ aufs_bindex_t bindex; -+ unsigned int flags; -+ struct dentry *dentry; -+ struct file *file; -+ void *label, *label_file; -+ } *f, file[] = { -+ { -+ .bindex = bsrc, -+ .flags = O_RDONLY | O_NOATIME | O_LARGEFILE, -+ .file = NULL, -+ .label = &&out, -+ .label_file = &&out_src -+ }, -+ { -+ .bindex = bdst, -+ .flags = O_WRONLY | O_NOATIME | O_LARGEFILE, -+ .file = NULL, -+ .label = &&out_src, -+ .label_file = &&out_dst -+ } -+ }; -+ struct super_block *sb; -+ -+ /* bsrc branch can be ro/rw. */ -+ sb = dentry->d_sb; -+ f = file; -+ for (i = 0; i < 2; i++, f++) { -+ f->dentry = au_h_dptr(dentry, f->bindex); -+ f->file = au_h_open(dentry, f->bindex, f->flags, /*file*/NULL); -+ err = PTR_ERR(f->file); -+ if (IS_ERR(f->file)) -+ goto *f->label; -+ err = -EINVAL; -+ if (unlikely(!f->file->f_op)) -+ goto *f->label_file; -+ } -+ -+ /* try stopping to update while we copyup */ -+ IMustLock(file[SRC].dentry->d_inode); -+ err = au_copy_file(file[DST].file, file[SRC].file, len); -+ -+out_dst: -+ fput(file[DST].file); -+ au_sbr_put(sb, file[DST].bindex); -+out_src: -+ fput(file[SRC].file); -+ au_sbr_put(sb, file[SRC].bindex); -+out: -+ return err; -+} -+ -+static int au_do_cpup_regular(struct dentry *dentry, aufs_bindex_t bdst, -+ aufs_bindex_t bsrc, loff_t len, -+ struct inode *h_dir, struct path *h_path) -+{ -+ int err, rerr; -+ loff_t l; -+ -+ err = 0; -+ l = i_size_read(au_h_iptr(dentry->d_inode, bsrc)); -+ if (len == -1 || l < len) -+ len = l; -+ if (len) -+ err = au_cp_regular(dentry, bdst, bsrc, len); -+ if (!err) -+ goto out; /* success */ -+ -+ rerr = vfsub_unlink(h_dir, h_path, /*force*/0); -+ if (rerr) { -+ AuIOErr("failed unlinking cpup-ed %.*s(%d, %d)\n", -+ AuDLNPair(h_path->dentry), err, rerr); -+ err = -EIO; -+ } -+ -+out: -+ return err; -+} -+ -+static int au_do_cpup_symlink(struct path *h_path, struct dentry *h_src, -+ struct inode *h_dir) -+{ -+ int err, symlen; -+ mm_segment_t old_fs; -+ union { -+ char *k; -+ char __user *u; -+ } sym; -+ -+ err = -ENOSYS; -+ if (unlikely(!h_src->d_inode->i_op->readlink)) -+ goto out; -+ -+ err = -ENOMEM; -+ sym.k = __getname_gfp(GFP_NOFS); -+ if (unlikely(!sym.k)) -+ goto out; -+ -+ old_fs = get_fs(); -+ set_fs(KERNEL_DS); -+ symlen = h_src->d_inode->i_op->readlink(h_src, sym.u, PATH_MAX); -+ err = symlen; -+ set_fs(old_fs); -+ -+ if (symlen > 0) { -+ sym.k[symlen] = 0; -+ err = vfsub_symlink(h_dir, h_path, sym.k); -+ } -+ __putname(sym.k); -+ -+out: -+ return err; -+} -+ -+/* return with the lower dst inode is locked */ -+static noinline_for_stack -+int cpup_entry(struct dentry *dentry, aufs_bindex_t bdst, -+ aufs_bindex_t bsrc, loff_t len, unsigned int flags, -+ struct dentry *dst_parent) -+{ -+ int err; -+ umode_t mode; -+ unsigned int mnt_flags; -+ unsigned char isdir; -+ const unsigned char do_dt = !!au_ftest_cpup(flags, DTIME); -+ struct au_dtime dt; -+ struct path h_path; -+ struct dentry *h_src, *h_dst, *h_parent; -+ struct inode *h_inode, *h_dir; -+ struct super_block *sb; -+ -+ /* bsrc branch can be ro/rw. */ -+ h_src = au_h_dptr(dentry, bsrc); -+ h_inode = h_src->d_inode; -+ AuDebugOn(h_inode != au_h_iptr(dentry->d_inode, bsrc)); -+ -+ /* try stopping to be referenced while we are creating */ -+ h_dst = au_h_dptr(dentry, bdst); -+ h_parent = h_dst->d_parent; /* dir inode is locked */ -+ h_dir = h_parent->d_inode; -+ IMustLock(h_dir); -+ AuDebugOn(h_parent != h_dst->d_parent); -+ -+ sb = dentry->d_sb; -+ h_path.mnt = au_sbr_mnt(sb, bdst); -+ if (do_dt) { -+ h_path.dentry = h_parent; -+ au_dtime_store(&dt, dst_parent, &h_path); -+ } -+ h_path.dentry = h_dst; -+ -+ isdir = 0; -+ mode = h_inode->i_mode; -+ switch (mode & S_IFMT) { -+ case S_IFREG: -+ /* try stopping to update while we are referencing */ -+ IMustLock(h_inode); -+ err = vfsub_create(h_dir, &h_path, mode | S_IWUSR); -+ if (!err) -+ err = au_do_cpup_regular -+ (dentry, bdst, bsrc, len, -+ au_h_iptr(dst_parent->d_inode, bdst), &h_path); -+ break; -+ case S_IFDIR: -+ isdir = 1; -+ err = vfsub_mkdir(h_dir, &h_path, mode); -+ if (!err) { -+ /* -+ * strange behaviour from the users view, -+ * particularry setattr case -+ */ -+ if (au_ibstart(dst_parent->d_inode) == bdst) -+ au_cpup_attr_nlink(dst_parent->d_inode, -+ /*force*/1); -+ au_cpup_attr_nlink(dentry->d_inode, /*force*/1); -+ } -+ break; -+ case S_IFLNK: -+ err = au_do_cpup_symlink(&h_path, h_src, h_dir); -+ break; -+ case S_IFCHR: -+ case S_IFBLK: -+ AuDebugOn(!capable(CAP_MKNOD)); -+ /*FALLTHROUGH*/ -+ case S_IFIFO: -+ case S_IFSOCK: -+ err = vfsub_mknod(h_dir, &h_path, mode, h_inode->i_rdev); -+ break; -+ default: -+ AuIOErr("Unknown inode type 0%o\n", mode); -+ err = -EIO; -+ } -+ -+ mnt_flags = au_mntflags(sb); -+ if (!au_opt_test(mnt_flags, UDBA_NONE) -+ && !isdir -+ && au_opt_test(mnt_flags, XINO) -+ && h_inode->i_nlink == 1 -+ /* todo: unnecessary? */ -+ /* && dentry->d_inode->i_nlink == 1 */ -+ && bdst < bsrc -+ && !au_ftest_cpup(flags, KEEPLINO)) -+ au_xino_write(sb, bsrc, h_inode->i_ino, /*ino*/0); -+ /* ignore this error */ -+ -+ if (do_dt) -+ au_dtime_revert(&dt); -+ return err; -+} -+ -+/* -+ * copyup the @dentry from @bsrc to @bdst. -+ * the caller must set the both of lower dentries. -+ * @len is for truncating when it is -1 copyup the entire file. -+ * in link/rename cases, @dst_parent may be different from the real one. -+ */ -+static int au_cpup_single(struct dentry *dentry, aufs_bindex_t bdst, -+ aufs_bindex_t bsrc, loff_t len, unsigned int flags, -+ struct dentry *dst_parent) -+{ -+ int err, rerr; -+ aufs_bindex_t old_ibstart; -+ unsigned char isdir, plink; -+ struct au_dtime dt; -+ struct path h_path; -+ struct dentry *h_src, *h_dst, *h_parent; -+ struct inode *dst_inode, *h_dir, *inode; -+ struct super_block *sb; -+ -+ AuDebugOn(bsrc <= bdst); -+ -+ sb = dentry->d_sb; -+ h_path.mnt = au_sbr_mnt(sb, bdst); -+ h_dst = au_h_dptr(dentry, bdst); -+ h_parent = h_dst->d_parent; /* dir inode is locked */ -+ h_dir = h_parent->d_inode; -+ IMustLock(h_dir); -+ -+ h_src = au_h_dptr(dentry, bsrc); -+ inode = dentry->d_inode; -+ -+ if (!dst_parent) -+ dst_parent = dget_parent(dentry); -+ else -+ dget(dst_parent); -+ -+ plink = !!au_opt_test(au_mntflags(sb), PLINK); -+ dst_inode = au_h_iptr(inode, bdst); -+ if (dst_inode) { -+ if (unlikely(!plink)) { -+ err = -EIO; -+ AuIOErr("hi%lu(i%lu) exists on b%d " -+ "but plink is disabled\n", -+ dst_inode->i_ino, inode->i_ino, bdst); -+ goto out; -+ } -+ -+ if (dst_inode->i_nlink) { -+ const int do_dt = au_ftest_cpup(flags, DTIME); -+ -+ h_src = au_plink_lkup(inode, bdst); -+ err = PTR_ERR(h_src); -+ if (IS_ERR(h_src)) -+ goto out; -+ if (unlikely(!h_src->d_inode)) { -+ err = -EIO; -+ AuIOErr("i%lu exists on a upper branch " -+ "but not pseudo-linked\n", -+ inode->i_ino); -+ dput(h_src); -+ goto out; -+ } -+ -+ if (do_dt) { -+ h_path.dentry = h_parent; -+ au_dtime_store(&dt, dst_parent, &h_path); -+ } -+ h_path.dentry = h_dst; -+ err = vfsub_link(h_src, h_dir, &h_path); -+ if (do_dt) -+ au_dtime_revert(&dt); -+ dput(h_src); -+ goto out; -+ } else -+ /* todo: cpup_wh_file? */ -+ /* udba work */ -+ au_update_ibrange(inode, /*do_put_zero*/1); -+ } -+ -+ old_ibstart = au_ibstart(inode); -+ err = cpup_entry(dentry, bdst, bsrc, len, flags, dst_parent); -+ if (unlikely(err)) -+ goto out; -+ dst_inode = h_dst->d_inode; -+ mutex_lock_nested(&dst_inode->i_mutex, AuLsc_I_CHILD2); -+ -+ err = cpup_iattr(dentry, bdst, h_src); -+ isdir = S_ISDIR(dst_inode->i_mode); -+ if (!err) { -+ if (bdst < old_ibstart) { -+ if (S_ISREG(inode->i_mode)) { -+ err = au_dy_iaop(inode, bdst, dst_inode); -+ if (unlikely(err)) -+ goto out_rev; -+ } -+ au_set_ibstart(inode, bdst); -+ } -+ au_set_h_iptr(inode, bdst, au_igrab(dst_inode), -+ au_hi_flags(inode, isdir)); -+ mutex_unlock(&dst_inode->i_mutex); -+ if (!isdir -+ && h_src->d_inode->i_nlink > 1 -+ && plink) -+ au_plink_append(inode, bdst, h_dst); -+ goto out; /* success */ -+ } -+ -+ /* revert */ -+out_rev: -+ h_path.dentry = h_parent; -+ mutex_unlock(&dst_inode->i_mutex); -+ au_dtime_store(&dt, dst_parent, &h_path); -+ h_path.dentry = h_dst; -+ if (!isdir) -+ rerr = vfsub_unlink(h_dir, &h_path, /*force*/0); -+ else -+ rerr = vfsub_rmdir(h_dir, &h_path); -+ au_dtime_revert(&dt); -+ if (rerr) { -+ AuIOErr("failed removing broken entry(%d, %d)\n", err, rerr); -+ err = -EIO; -+ } -+ -+out: -+ dput(dst_parent); -+ return err; -+} -+ -+struct au_cpup_single_args { -+ int *errp; -+ struct dentry *dentry; -+ aufs_bindex_t bdst, bsrc; -+ loff_t len; -+ unsigned int flags; -+ struct dentry *dst_parent; -+}; -+ -+static void au_call_cpup_single(void *args) -+{ -+ struct au_cpup_single_args *a = args; -+ *a->errp = au_cpup_single(a->dentry, a->bdst, a->bsrc, a->len, -+ a->flags, a->dst_parent); -+} -+ -+int au_sio_cpup_single(struct dentry *dentry, aufs_bindex_t bdst, -+ aufs_bindex_t bsrc, loff_t len, unsigned int flags, -+ struct dentry *dst_parent) -+{ -+ int err, wkq_err; -+ umode_t mode; -+ struct dentry *h_dentry; -+ -+ h_dentry = au_h_dptr(dentry, bsrc); -+ mode = h_dentry->d_inode->i_mode & S_IFMT; -+ if ((mode != S_IFCHR && mode != S_IFBLK) -+ || capable(CAP_MKNOD)) -+ err = au_cpup_single(dentry, bdst, bsrc, len, flags, -+ dst_parent); -+ else { -+ struct au_cpup_single_args args = { -+ .errp = &err, -+ .dentry = dentry, -+ .bdst = bdst, -+ .bsrc = bsrc, -+ .len = len, -+ .flags = flags, -+ .dst_parent = dst_parent -+ }; -+ wkq_err = au_wkq_wait(au_call_cpup_single, &args); -+ if (unlikely(wkq_err)) -+ err = wkq_err; -+ } -+ -+ return err; -+} -+ -+/* -+ * copyup the @dentry from the first active lower branch to @bdst, -+ * using au_cpup_single(). -+ */ -+static int au_cpup_simple(struct dentry *dentry, aufs_bindex_t bdst, loff_t len, -+ unsigned int flags) -+{ -+ int err; -+ aufs_bindex_t bsrc, bend; -+ -+ bend = au_dbend(dentry); -+ for (bsrc = bdst + 1; bsrc <= bend; bsrc++) -+ if (au_h_dptr(dentry, bsrc)) -+ break; -+ -+ err = au_lkup_neg(dentry, bdst); -+ if (!err) { -+ err = au_cpup_single(dentry, bdst, bsrc, len, flags, NULL); -+ if (!err) -+ return 0; /* success */ -+ -+ /* revert */ -+ au_set_h_dptr(dentry, bdst, NULL); -+ au_set_dbstart(dentry, bsrc); -+ } -+ -+ return err; -+} -+ -+struct au_cpup_simple_args { -+ int *errp; -+ struct dentry *dentry; -+ aufs_bindex_t bdst; -+ loff_t len; -+ unsigned int flags; -+}; -+ -+static void au_call_cpup_simple(void *args) -+{ -+ struct au_cpup_simple_args *a = args; -+ *a->errp = au_cpup_simple(a->dentry, a->bdst, a->len, a->flags); -+} -+ -+int au_sio_cpup_simple(struct dentry *dentry, aufs_bindex_t bdst, loff_t len, -+ unsigned int flags) -+{ -+ int err, wkq_err; -+ unsigned char do_sio; -+ struct dentry *parent; -+ struct inode *h_dir; -+ -+ parent = dget_parent(dentry); -+ h_dir = au_h_iptr(parent->d_inode, bdst); -+ do_sio = !!au_test_h_perm_sio(h_dir, MAY_EXEC | MAY_WRITE); -+ if (!do_sio) { -+ /* -+ * testing CAP_MKNOD is for generic fs, -+ * but CAP_FSETID is for xfs only, currently. -+ */ -+ umode_t mode = dentry->d_inode->i_mode; -+ do_sio = (((mode & (S_IFCHR | S_IFBLK)) -+ && !capable(CAP_MKNOD)) -+ || ((mode & (S_ISUID | S_ISGID)) -+ && !capable(CAP_FSETID))); -+ } -+ if (!do_sio) -+ err = au_cpup_simple(dentry, bdst, len, flags); -+ else { -+ struct au_cpup_simple_args args = { -+ .errp = &err, -+ .dentry = dentry, -+ .bdst = bdst, -+ .len = len, -+ .flags = flags -+ }; -+ wkq_err = au_wkq_wait(au_call_cpup_simple, &args); -+ if (unlikely(wkq_err)) -+ err = wkq_err; -+ } -+ -+ dput(parent); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * copyup the deleted file for writing. -+ */ -+static int au_do_cpup_wh(struct dentry *dentry, aufs_bindex_t bdst, -+ struct dentry *wh_dentry, struct file *file, -+ loff_t len) -+{ -+ int err; -+ aufs_bindex_t bstart; -+ struct au_dinfo *dinfo; -+ struct dentry *h_d_dst, *h_d_start; -+ struct au_hdentry *hdp; -+ -+ dinfo = au_di(dentry); -+ AuRwMustWriteLock(&dinfo->di_rwsem); -+ -+ bstart = dinfo->di_bstart; -+ hdp = dinfo->di_hdentry; -+ h_d_dst = hdp[0 + bdst].hd_dentry; -+ dinfo->di_bstart = bdst; -+ hdp[0 + bdst].hd_dentry = wh_dentry; -+ if (file) { -+ h_d_start = hdp[0 + bstart].hd_dentry; -+ hdp[0 + bstart].hd_dentry = au_hf_top(file)->f_dentry; -+ } -+ err = au_cpup_single(dentry, bdst, bstart, len, !AuCpup_DTIME, -+ /*h_parent*/NULL); -+ if (file) { -+ if (!err) -+ err = au_reopen_nondir(file); -+ hdp[0 + bstart].hd_dentry = h_d_start; -+ } -+ hdp[0 + bdst].hd_dentry = h_d_dst; -+ dinfo->di_bstart = bstart; -+ -+ return err; -+} -+ -+static int au_cpup_wh(struct dentry *dentry, aufs_bindex_t bdst, loff_t len, -+ struct file *file) -+{ -+ int err; -+ struct au_dtime dt; -+ struct dentry *parent, *h_parent, *wh_dentry; -+ struct au_branch *br; -+ struct path h_path; -+ -+ br = au_sbr(dentry->d_sb, bdst); -+ parent = dget_parent(dentry); -+ h_parent = au_h_dptr(parent, bdst); -+ wh_dentry = au_whtmp_lkup(h_parent, br, &dentry->d_name); -+ err = PTR_ERR(wh_dentry); -+ if (IS_ERR(wh_dentry)) -+ goto out; -+ -+ h_path.dentry = h_parent; -+ h_path.mnt = br->br_mnt; -+ au_dtime_store(&dt, parent, &h_path); -+ err = au_do_cpup_wh(dentry, bdst, wh_dentry, file, len); -+ if (unlikely(err)) -+ goto out_wh; -+ -+ dget(wh_dentry); -+ h_path.dentry = wh_dentry; -+ if (!S_ISDIR(wh_dentry->d_inode->i_mode)) -+ err = vfsub_unlink(h_parent->d_inode, &h_path, /*force*/0); -+ else -+ err = vfsub_rmdir(h_parent->d_inode, &h_path); -+ if (unlikely(err)) { -+ AuIOErr("failed remove copied-up tmp file %.*s(%d)\n", -+ AuDLNPair(wh_dentry), err); -+ err = -EIO; -+ } -+ au_dtime_revert(&dt); -+ au_set_hi_wh(dentry->d_inode, bdst, wh_dentry); -+ -+out_wh: -+ dput(wh_dentry); -+out: -+ dput(parent); -+ return err; -+} -+ -+struct au_cpup_wh_args { -+ int *errp; -+ struct dentry *dentry; -+ aufs_bindex_t bdst; -+ loff_t len; -+ struct file *file; -+}; -+ -+static void au_call_cpup_wh(void *args) -+{ -+ struct au_cpup_wh_args *a = args; -+ *a->errp = au_cpup_wh(a->dentry, a->bdst, a->len, a->file); -+} -+ -+int au_sio_cpup_wh(struct dentry *dentry, aufs_bindex_t bdst, loff_t len, -+ struct file *file) -+{ -+ int err, wkq_err; -+ struct dentry *parent, *h_orph, *h_parent, *h_dentry; -+ struct inode *dir, *h_dir, *h_tmpdir, *h_inode; -+ struct au_wbr *wbr; -+ -+ parent = dget_parent(dentry); -+ dir = parent->d_inode; -+ h_orph = NULL; -+ h_parent = NULL; -+ h_dir = au_igrab(au_h_iptr(dir, bdst)); -+ h_tmpdir = h_dir; -+ if (!h_dir->i_nlink) { -+ wbr = au_sbr(dentry->d_sb, bdst)->br_wbr; -+ h_orph = wbr->wbr_orph; -+ -+ h_parent = dget(au_h_dptr(parent, bdst)); -+ au_set_h_dptr(parent, bdst, dget(h_orph)); -+ h_tmpdir = h_orph->d_inode; -+ au_set_h_iptr(dir, bdst, au_igrab(h_tmpdir), /*flags*/0); -+ -+ /* this temporary unlock is safe */ -+ if (file) -+ h_dentry = au_hf_top(file)->f_dentry; -+ else -+ h_dentry = au_h_dptr(dentry, au_dbstart(dentry)); -+ h_inode = h_dentry->d_inode; -+ IMustLock(h_inode); -+ mutex_unlock(&h_inode->i_mutex); -+ mutex_lock_nested(&h_tmpdir->i_mutex, AuLsc_I_PARENT3); -+ mutex_lock_nested(&h_inode->i_mutex, AuLsc_I_CHILD); -+ /* todo: au_h_open_pre()? */ -+ } -+ -+ if (!au_test_h_perm_sio(h_tmpdir, MAY_EXEC | MAY_WRITE)) -+ err = au_cpup_wh(dentry, bdst, len, file); -+ else { -+ struct au_cpup_wh_args args = { -+ .errp = &err, -+ .dentry = dentry, -+ .bdst = bdst, -+ .len = len, -+ .file = file -+ }; -+ wkq_err = au_wkq_wait(au_call_cpup_wh, &args); -+ if (unlikely(wkq_err)) -+ err = wkq_err; -+ } -+ -+ if (h_orph) { -+ mutex_unlock(&h_tmpdir->i_mutex); -+ /* todo: au_h_open_post()? */ -+ au_set_h_iptr(dir, bdst, au_igrab(h_dir), /*flags*/0); -+ au_set_h_dptr(parent, bdst, h_parent); -+ } -+ iput(h_dir); -+ dput(parent); -+ -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * generic routine for both of copy-up and copy-down. -+ */ -+/* cf. revalidate function in file.c */ -+int au_cp_dirs(struct dentry *dentry, aufs_bindex_t bdst, -+ int (*cp)(struct dentry *dentry, aufs_bindex_t bdst, -+ struct dentry *h_parent, void *arg), -+ void *arg) -+{ -+ int err; -+ struct au_pin pin; -+ struct dentry *d, *parent, *h_parent, *real_parent; -+ -+ err = 0; -+ parent = dget_parent(dentry); -+ if (IS_ROOT(parent)) -+ goto out; -+ -+ au_pin_init(&pin, dentry, bdst, AuLsc_DI_PARENT2, AuLsc_I_PARENT2, -+ au_opt_udba(dentry->d_sb), AuPin_MNT_WRITE); -+ -+ /* do not use au_dpage */ -+ real_parent = parent; -+ while (1) { -+ dput(parent); -+ parent = dget_parent(dentry); -+ h_parent = au_h_dptr(parent, bdst); -+ if (h_parent) -+ goto out; /* success */ -+ -+ /* find top dir which is necessary to cpup */ -+ do { -+ d = parent; -+ dput(parent); -+ parent = dget_parent(d); -+ di_read_lock_parent3(parent, !AuLock_IR); -+ h_parent = au_h_dptr(parent, bdst); -+ di_read_unlock(parent, !AuLock_IR); -+ } while (!h_parent); -+ -+ if (d != real_parent) -+ di_write_lock_child3(d); -+ -+ /* somebody else might create while we were sleeping */ -+ if (!au_h_dptr(d, bdst) || !au_h_dptr(d, bdst)->d_inode) { -+ if (au_h_dptr(d, bdst)) -+ au_update_dbstart(d); -+ -+ au_pin_set_dentry(&pin, d); -+ err = au_do_pin(&pin); -+ if (!err) { -+ err = cp(d, bdst, h_parent, arg); -+ au_unpin(&pin); -+ } -+ } -+ -+ if (d != real_parent) -+ di_write_unlock(d); -+ if (unlikely(err)) -+ break; -+ } -+ -+out: -+ dput(parent); -+ return err; -+} -+ -+static int au_cpup_dir(struct dentry *dentry, aufs_bindex_t bdst, -+ struct dentry *h_parent __maybe_unused , -+ void *arg __maybe_unused) -+{ -+ return au_sio_cpup_simple(dentry, bdst, -1, AuCpup_DTIME); -+} -+ -+int au_cpup_dirs(struct dentry *dentry, aufs_bindex_t bdst) -+{ -+ return au_cp_dirs(dentry, bdst, au_cpup_dir, NULL); -+} -+ -+int au_test_and_cpup_dirs(struct dentry *dentry, aufs_bindex_t bdst) -+{ -+ int err; -+ struct dentry *parent; -+ struct inode *dir; -+ -+ parent = dget_parent(dentry); -+ dir = parent->d_inode; -+ err = 0; -+ if (au_h_iptr(dir, bdst)) -+ goto out; -+ -+ di_read_unlock(parent, AuLock_IR); -+ di_write_lock_parent(parent); -+ /* someone else might change our inode while we were sleeping */ -+ if (!au_h_iptr(dir, bdst)) -+ err = au_cpup_dirs(dentry, bdst); -+ di_downgrade_lock(parent, AuLock_IR); -+ -+out: -+ dput(parent); -+ return err; -+} -diff -Nur linux-2.6.36.orig/fs/aufs/cpup.h linux-2.6.36/fs/aufs/cpup.h ---- linux-2.6.36.orig/fs/aufs/cpup.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/cpup.h 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,83 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * copy-up/down functions -+ */ -+ -+#ifndef __AUFS_CPUP_H__ -+#define __AUFS_CPUP_H__ -+ -+#ifdef __KERNEL__ -+ -+#include -+#include -+#include -+ -+struct inode; -+struct file; -+ -+void au_cpup_attr_flags(struct inode *dst, struct inode *src); -+void au_cpup_attr_timesizes(struct inode *inode); -+void au_cpup_attr_nlink(struct inode *inode, int force); -+void au_cpup_attr_changeable(struct inode *inode); -+void au_cpup_igen(struct inode *inode, struct inode *h_inode); -+void au_cpup_attr_all(struct inode *inode, int force); -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* cpup flags */ -+#define AuCpup_DTIME 1 /* do dtime_store/revert */ -+#define AuCpup_KEEPLINO (1 << 1) /* do not clear the lower xino, -+ for link(2) */ -+#define au_ftest_cpup(flags, name) ((flags) & AuCpup_##name) -+#define au_fset_cpup(flags, name) \ -+ do { (flags) |= AuCpup_##name; } while (0) -+#define au_fclr_cpup(flags, name) \ -+ do { (flags) &= ~AuCpup_##name; } while (0) -+ -+int au_copy_file(struct file *dst, struct file *src, loff_t len); -+int au_sio_cpup_single(struct dentry *dentry, aufs_bindex_t bdst, -+ aufs_bindex_t bsrc, loff_t len, unsigned int flags, -+ struct dentry *dst_parent); -+int au_sio_cpup_simple(struct dentry *dentry, aufs_bindex_t bdst, loff_t len, -+ unsigned int flags); -+int au_sio_cpup_wh(struct dentry *dentry, aufs_bindex_t bdst, loff_t len, -+ struct file *file); -+ -+int au_cp_dirs(struct dentry *dentry, aufs_bindex_t bdst, -+ int (*cp)(struct dentry *dentry, aufs_bindex_t bdst, -+ struct dentry *h_parent, void *arg), -+ void *arg); -+int au_cpup_dirs(struct dentry *dentry, aufs_bindex_t bdst); -+int au_test_and_cpup_dirs(struct dentry *dentry, aufs_bindex_t bdst); -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* keep timestamps when copyup */ -+struct au_dtime { -+ struct dentry *dt_dentry; -+ struct path dt_h_path; -+ struct timespec dt_atime, dt_mtime; -+}; -+void au_dtime_store(struct au_dtime *dt, struct dentry *dentry, -+ struct path *h_path); -+void au_dtime_revert(struct au_dtime *dt); -+ -+#endif /* __KERNEL__ */ -+#endif /* __AUFS_CPUP_H__ */ -diff -Nur linux-2.6.36.orig/fs/aufs/dbgaufs.c linux-2.6.36/fs/aufs/dbgaufs.c ---- linux-2.6.36.orig/fs/aufs/dbgaufs.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/dbgaufs.c 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,334 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * debugfs interface -+ */ -+ -+#include -+#include "aufs.h" -+ -+#ifndef CONFIG_SYSFS -+#error DEBUG_FS depends upon SYSFS -+#endif -+ -+static struct dentry *dbgaufs; -+static const mode_t dbgaufs_mode = S_IRUSR | S_IRGRP | S_IROTH; -+ -+/* 20 is max digits length of ulong 64 */ -+struct dbgaufs_arg { -+ int n; -+ char a[20 * 4]; -+}; -+ -+/* -+ * common function for all XINO files -+ */ -+static int dbgaufs_xi_release(struct inode *inode __maybe_unused, -+ struct file *file) -+{ -+ kfree(file->private_data); -+ return 0; -+} -+ -+static int dbgaufs_xi_open(struct file *xf, struct file *file, int do_fcnt) -+{ -+ int err; -+ struct kstat st; -+ struct dbgaufs_arg *p; -+ -+ err = -ENOMEM; -+ p = kmalloc(sizeof(*p), GFP_NOFS); -+ if (unlikely(!p)) -+ goto out; -+ -+ err = 0; -+ p->n = 0; -+ file->private_data = p; -+ if (!xf) -+ goto out; -+ -+ err = vfs_getattr(xf->f_vfsmnt, xf->f_dentry, &st); -+ if (!err) { -+ if (do_fcnt) -+ p->n = snprintf -+ (p->a, sizeof(p->a), "%ld, %llux%lu %lld\n", -+ (long)file_count(xf), st.blocks, st.blksize, -+ (long long)st.size); -+ else -+ p->n = snprintf(p->a, sizeof(p->a), "%llux%lu %lld\n", -+ st.blocks, st.blksize, -+ (long long)st.size); -+ AuDebugOn(p->n >= sizeof(p->a)); -+ } else { -+ p->n = snprintf(p->a, sizeof(p->a), "err %d\n", err); -+ err = 0; -+ } -+ -+out: -+ return err; -+ -+} -+ -+static ssize_t dbgaufs_xi_read(struct file *file, char __user *buf, -+ size_t count, loff_t *ppos) -+{ -+ struct dbgaufs_arg *p; -+ -+ p = file->private_data; -+ return simple_read_from_buffer(buf, count, ppos, p->a, p->n); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int dbgaufs_xib_open(struct inode *inode, struct file *file) -+{ -+ int err; -+ struct au_sbinfo *sbinfo; -+ struct super_block *sb; -+ -+ sbinfo = inode->i_private; -+ sb = sbinfo->si_sb; -+ si_noflush_read_lock(sb); -+ err = dbgaufs_xi_open(sbinfo->si_xib, file, /*do_fcnt*/0); -+ si_read_unlock(sb); -+ return err; -+} -+ -+static const struct file_operations dbgaufs_xib_fop = { -+ .owner = THIS_MODULE, -+ .open = dbgaufs_xib_open, -+ .release = dbgaufs_xi_release, -+ .read = dbgaufs_xi_read -+}; -+ -+/* ---------------------------------------------------------------------- */ -+ -+#define DbgaufsXi_PREFIX "xi" -+ -+static int dbgaufs_xino_open(struct inode *inode, struct file *file) -+{ -+ int err; -+ long l; -+ struct au_sbinfo *sbinfo; -+ struct super_block *sb; -+ struct file *xf; -+ struct qstr *name; -+ -+ err = -ENOENT; -+ xf = NULL; -+ name = &file->f_dentry->d_name; -+ if (unlikely(name->len < sizeof(DbgaufsXi_PREFIX) -+ || memcmp(name->name, DbgaufsXi_PREFIX, -+ sizeof(DbgaufsXi_PREFIX) - 1))) -+ goto out; -+ err = strict_strtol(name->name + sizeof(DbgaufsXi_PREFIX) - 1, 10, &l); -+ if (unlikely(err)) -+ goto out; -+ -+ sbinfo = inode->i_private; -+ sb = sbinfo->si_sb; -+ si_noflush_read_lock(sb); -+ if (l <= au_sbend(sb)) { -+ xf = au_sbr(sb, (aufs_bindex_t)l)->br_xino.xi_file; -+ err = dbgaufs_xi_open(xf, file, /*do_fcnt*/1); -+ } else -+ err = -ENOENT; -+ si_read_unlock(sb); -+ -+out: -+ return err; -+} -+ -+static const struct file_operations dbgaufs_xino_fop = { -+ .owner = THIS_MODULE, -+ .open = dbgaufs_xino_open, -+ .release = dbgaufs_xi_release, -+ .read = dbgaufs_xi_read -+}; -+ -+void dbgaufs_brs_del(struct super_block *sb, aufs_bindex_t bindex) -+{ -+ aufs_bindex_t bend; -+ struct au_branch *br; -+ struct au_xino_file *xi; -+ -+ if (!au_sbi(sb)->si_dbgaufs) -+ return; -+ -+ bend = au_sbend(sb); -+ for (; bindex <= bend; bindex++) { -+ br = au_sbr(sb, bindex); -+ xi = &br->br_xino; -+ if (xi->xi_dbgaufs) { -+ debugfs_remove(xi->xi_dbgaufs); -+ xi->xi_dbgaufs = NULL; -+ } -+ } -+} -+ -+void dbgaufs_brs_add(struct super_block *sb, aufs_bindex_t bindex) -+{ -+ struct au_sbinfo *sbinfo; -+ struct dentry *parent; -+ struct au_branch *br; -+ struct au_xino_file *xi; -+ aufs_bindex_t bend; -+ char name[sizeof(DbgaufsXi_PREFIX) + 5]; /* "xi" bindex NULL */ -+ -+ sbinfo = au_sbi(sb); -+ parent = sbinfo->si_dbgaufs; -+ if (!parent) -+ return; -+ -+ bend = au_sbend(sb); -+ for (; bindex <= bend; bindex++) { -+ snprintf(name, sizeof(name), DbgaufsXi_PREFIX "%d", bindex); -+ br = au_sbr(sb, bindex); -+ xi = &br->br_xino; -+ AuDebugOn(xi->xi_dbgaufs); -+ xi->xi_dbgaufs = debugfs_create_file(name, dbgaufs_mode, parent, -+ sbinfo, &dbgaufs_xino_fop); -+ /* ignore an error */ -+ if (unlikely(!xi->xi_dbgaufs)) -+ AuWarn1("failed %s under debugfs\n", name); -+ } -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+#ifdef CONFIG_AUFS_EXPORT -+static int dbgaufs_xigen_open(struct inode *inode, struct file *file) -+{ -+ int err; -+ struct au_sbinfo *sbinfo; -+ struct super_block *sb; -+ -+ sbinfo = inode->i_private; -+ sb = sbinfo->si_sb; -+ si_noflush_read_lock(sb); -+ err = dbgaufs_xi_open(sbinfo->si_xigen, file, /*do_fcnt*/0); -+ si_read_unlock(sb); -+ return err; -+} -+ -+static const struct file_operations dbgaufs_xigen_fop = { -+ .owner = THIS_MODULE, -+ .open = dbgaufs_xigen_open, -+ .release = dbgaufs_xi_release, -+ .read = dbgaufs_xi_read -+}; -+ -+static int dbgaufs_xigen_init(struct au_sbinfo *sbinfo) -+{ -+ int err; -+ -+ /* -+ * This function is a dynamic '__init' fucntion actually, -+ * so the tiny check for si_rwsem is unnecessary. -+ */ -+ /* AuRwMustWriteLock(&sbinfo->si_rwsem); */ -+ -+ err = -EIO; -+ sbinfo->si_dbgaufs_xigen = debugfs_create_file -+ ("xigen", dbgaufs_mode, sbinfo->si_dbgaufs, sbinfo, -+ &dbgaufs_xigen_fop); -+ if (sbinfo->si_dbgaufs_xigen) -+ err = 0; -+ -+ return err; -+} -+#else -+static int dbgaufs_xigen_init(struct au_sbinfo *sbinfo) -+{ -+ return 0; -+} -+#endif /* CONFIG_AUFS_EXPORT */ -+ -+/* ---------------------------------------------------------------------- */ -+ -+void dbgaufs_si_fin(struct au_sbinfo *sbinfo) -+{ -+ /* -+ * This function is a dynamic '__init' fucntion actually, -+ * so the tiny check for si_rwsem is unnecessary. -+ */ -+ /* AuRwMustWriteLock(&sbinfo->si_rwsem); */ -+ -+ debugfs_remove_recursive(sbinfo->si_dbgaufs); -+ sbinfo->si_dbgaufs = NULL; -+ kobject_put(&sbinfo->si_kobj); -+} -+ -+int dbgaufs_si_init(struct au_sbinfo *sbinfo) -+{ -+ int err; -+ char name[SysaufsSiNameLen]; -+ -+ /* -+ * This function is a dynamic '__init' fucntion actually, -+ * so the tiny check for si_rwsem is unnecessary. -+ */ -+ /* AuRwMustWriteLock(&sbinfo->si_rwsem); */ -+ -+ err = -ENOENT; -+ if (!dbgaufs) { -+ AuErr1("/debug/aufs is uninitialized\n"); -+ goto out; -+ } -+ -+ err = -EIO; -+ sysaufs_name(sbinfo, name); -+ sbinfo->si_dbgaufs = debugfs_create_dir(name, dbgaufs); -+ if (unlikely(!sbinfo->si_dbgaufs)) -+ goto out; -+ kobject_get(&sbinfo->si_kobj); -+ -+ sbinfo->si_dbgaufs_xib = debugfs_create_file -+ ("xib", dbgaufs_mode, sbinfo->si_dbgaufs, sbinfo, -+ &dbgaufs_xib_fop); -+ if (unlikely(!sbinfo->si_dbgaufs_xib)) -+ goto out_dir; -+ -+ err = dbgaufs_xigen_init(sbinfo); -+ if (!err) -+ goto out; /* success */ -+ -+out_dir: -+ dbgaufs_si_fin(sbinfo); -+out: -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+void dbgaufs_fin(void) -+{ -+ debugfs_remove(dbgaufs); -+} -+ -+int __init dbgaufs_init(void) -+{ -+ int err; -+ -+ err = -EIO; -+ dbgaufs = debugfs_create_dir(AUFS_NAME, NULL); -+ if (dbgaufs) -+ err = 0; -+ return err; -+} -diff -Nur linux-2.6.36.orig/fs/aufs/dbgaufs.h linux-2.6.36/fs/aufs/dbgaufs.h ---- linux-2.6.36.orig/fs/aufs/dbgaufs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/dbgaufs.h 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,52 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * debugfs interface -+ */ -+ -+#ifndef __DBGAUFS_H__ -+#define __DBGAUFS_H__ -+ -+#ifdef __KERNEL__ -+ -+#include -+#include -+ -+struct super_block; -+struct au_sbinfo; -+ -+#ifdef CONFIG_DEBUG_FS -+/* dbgaufs.c */ -+void dbgaufs_brs_del(struct super_block *sb, aufs_bindex_t bindex); -+void dbgaufs_brs_add(struct super_block *sb, aufs_bindex_t bindex); -+void dbgaufs_si_fin(struct au_sbinfo *sbinfo); -+int dbgaufs_si_init(struct au_sbinfo *sbinfo); -+void dbgaufs_fin(void); -+int __init dbgaufs_init(void); -+#else -+AuStubVoid(dbgaufs_brs_del, struct super_block *sb, aufs_bindex_t bindex) -+AuStubVoid(dbgaufs_brs_add, struct super_block *sb, aufs_bindex_t bindex) -+AuStubVoid(dbgaufs_si_fin, struct au_sbinfo *sbinfo) -+AuStubInt0(dbgaufs_si_init, struct au_sbinfo *sbinfo) -+AuStubVoid(dbgaufs_fin, void) -+AuStubInt0(__init dbgaufs_init, void) -+#endif /* CONFIG_DEBUG_FS */ -+ -+#endif /* __KERNEL__ */ -+#endif /* __DBGAUFS_H__ */ -diff -Nur linux-2.6.36.orig/fs/aufs/dcsub.c linux-2.6.36/fs/aufs/dcsub.c ---- linux-2.6.36.orig/fs/aufs/dcsub.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/dcsub.c 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,210 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * sub-routines for dentry cache -+ */ -+ -+#include "aufs.h" -+ -+static void au_dpage_free(struct au_dpage *dpage) -+{ -+ int i; -+ struct dentry **p; -+ -+ p = dpage->dentries; -+ for (i = 0; i < dpage->ndentry; i++) -+ dput(*p++); -+ free_page((unsigned long)dpage->dentries); -+} -+ -+int au_dpages_init(struct au_dcsub_pages *dpages, gfp_t gfp) -+{ -+ int err; -+ void *p; -+ -+ err = -ENOMEM; -+ dpages->dpages = kmalloc(sizeof(*dpages->dpages), gfp); -+ if (unlikely(!dpages->dpages)) -+ goto out; -+ -+ p = (void *)__get_free_page(gfp); -+ if (unlikely(!p)) -+ goto out_dpages; -+ -+ dpages->dpages[0].ndentry = 0; -+ dpages->dpages[0].dentries = p; -+ dpages->ndpage = 1; -+ return 0; /* success */ -+ -+out_dpages: -+ kfree(dpages->dpages); -+out: -+ return err; -+} -+ -+void au_dpages_free(struct au_dcsub_pages *dpages) -+{ -+ int i; -+ struct au_dpage *p; -+ -+ p = dpages->dpages; -+ for (i = 0; i < dpages->ndpage; i++) -+ au_dpage_free(p++); -+ kfree(dpages->dpages); -+} -+ -+static int au_dpages_append(struct au_dcsub_pages *dpages, -+ struct dentry *dentry, gfp_t gfp) -+{ -+ int err, sz; -+ struct au_dpage *dpage; -+ void *p; -+ -+ dpage = dpages->dpages + dpages->ndpage - 1; -+ sz = PAGE_SIZE / sizeof(dentry); -+ if (unlikely(dpage->ndentry >= sz)) { -+ AuLabel(new dpage); -+ err = -ENOMEM; -+ sz = dpages->ndpage * sizeof(*dpages->dpages); -+ p = au_kzrealloc(dpages->dpages, sz, -+ sz + sizeof(*dpages->dpages), gfp); -+ if (unlikely(!p)) -+ goto out; -+ -+ dpages->dpages = p; -+ dpage = dpages->dpages + dpages->ndpage; -+ p = (void *)__get_free_page(gfp); -+ if (unlikely(!p)) -+ goto out; -+ -+ dpage->ndentry = 0; -+ dpage->dentries = p; -+ dpages->ndpage++; -+ } -+ -+ /* d_count can be zero */ -+ dpage->dentries[dpage->ndentry++] = dget_locked(dentry); -+ return 0; /* success */ -+ -+out: -+ return err; -+} -+ -+int au_dcsub_pages(struct au_dcsub_pages *dpages, struct dentry *root, -+ au_dpages_test test, void *arg) -+{ -+ int err; -+ struct dentry *this_parent = root; -+ struct list_head *next; -+ struct super_block *sb = root->d_sb; -+ -+ err = 0; -+ spin_lock(&dcache_lock); -+repeat: -+ next = this_parent->d_subdirs.next; -+resume: -+ if (this_parent->d_sb == sb -+ && !IS_ROOT(this_parent) -+ && au_di(this_parent) -+ && (!test || test(this_parent, arg))) { -+ err = au_dpages_append(dpages, this_parent, GFP_ATOMIC); -+ if (unlikely(err)) -+ goto out; -+ } -+ -+ while (next != &this_parent->d_subdirs) { -+ struct list_head *tmp = next; -+ struct dentry *dentry = list_entry(tmp, struct dentry, -+ d_u.d_child); -+ next = tmp->next; -+ if (!list_empty(&dentry->d_subdirs)) { -+ this_parent = dentry; -+ goto repeat; -+ } -+ if (dentry->d_sb == sb -+ && au_di(dentry) -+ && (!test || test(dentry, arg))) { -+ err = au_dpages_append(dpages, dentry, GFP_ATOMIC); -+ if (unlikely(err)) -+ goto out; -+ } -+ } -+ -+ if (this_parent != root) { -+ next = this_parent->d_u.d_child.next; -+ this_parent = this_parent->d_parent; /* dcache_lock is locked */ -+ goto resume; -+ } -+out: -+ spin_unlock(&dcache_lock); -+ return err; -+} -+ -+int au_dcsub_pages_rev(struct au_dcsub_pages *dpages, struct dentry *dentry, -+ int do_include, au_dpages_test test, void *arg) -+{ -+ int err; -+ -+ err = 0; -+ spin_lock(&dcache_lock); -+ if (do_include && (!test || test(dentry, arg))) { -+ err = au_dpages_append(dpages, dentry, GFP_ATOMIC); -+ if (unlikely(err)) -+ goto out; -+ } -+ while (!IS_ROOT(dentry)) { -+ dentry = dentry->d_parent; /* dcache_lock is locked */ -+ if (!test || test(dentry, arg)) { -+ err = au_dpages_append(dpages, dentry, GFP_ATOMIC); -+ if (unlikely(err)) -+ break; -+ } -+ } -+ -+out: -+ spin_unlock(&dcache_lock); -+ -+ return err; -+} -+ -+static inline int au_dcsub_dpages_aufs(struct dentry *dentry, void *arg) -+{ -+ return au_di(dentry) && dentry->d_sb == arg; -+} -+ -+int au_dcsub_pages_rev_aufs(struct au_dcsub_pages *dpages, -+ struct dentry *dentry, int do_include) -+{ -+ return au_dcsub_pages_rev(dpages, dentry, do_include, -+ au_dcsub_dpages_aufs, dentry->d_sb); -+} -+ -+int au_test_subdir(struct dentry *d1, struct dentry *d2) -+{ -+ struct path path[2] = { -+ { -+ .dentry = d1 -+ }, -+ { -+ .dentry = d2 -+ } -+ }; -+ -+ return path_is_under(path + 0, path + 1); -+} -diff -Nur linux-2.6.36.orig/fs/aufs/dcsub.h linux-2.6.36/fs/aufs/dcsub.h ---- linux-2.6.36.orig/fs/aufs/dcsub.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/dcsub.h 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,100 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * sub-routines for dentry cache -+ */ -+ -+#ifndef __AUFS_DCSUB_H__ -+#define __AUFS_DCSUB_H__ -+ -+#ifdef __KERNEL__ -+ -+#include -+#include -+#include -+ -+struct dentry; -+ -+struct au_dpage { -+ int ndentry; -+ struct dentry **dentries; -+}; -+ -+struct au_dcsub_pages { -+ int ndpage; -+ struct au_dpage *dpages; -+}; -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* dcsub.c */ -+int au_dpages_init(struct au_dcsub_pages *dpages, gfp_t gfp); -+void au_dpages_free(struct au_dcsub_pages *dpages); -+typedef int (*au_dpages_test)(struct dentry *dentry, void *arg); -+int au_dcsub_pages(struct au_dcsub_pages *dpages, struct dentry *root, -+ au_dpages_test test, void *arg); -+int au_dcsub_pages_rev(struct au_dcsub_pages *dpages, struct dentry *dentry, -+ int do_include, au_dpages_test test, void *arg); -+int au_dcsub_pages_rev_aufs(struct au_dcsub_pages *dpages, -+ struct dentry *dentry, int do_include); -+int au_test_subdir(struct dentry *d1, struct dentry *d2); -+ -+/* ---------------------------------------------------------------------- */ -+ -+static inline int au_d_removed(struct dentry *d) -+{ -+ return !IS_ROOT(d) && d_unhashed(d); -+} -+ -+static inline int au_d_hashed_positive(struct dentry *d) -+{ -+ int err; -+ struct inode *inode = d->d_inode; -+ err = 0; -+ if (unlikely(d_unhashed(d) || !inode || !inode->i_nlink)) -+ err = -ENOENT; -+ return err; -+} -+ -+static inline int au_d_alive(struct dentry *d) -+{ -+ int err; -+ struct inode *inode; -+ err = 0; -+ if (!IS_ROOT(d)) -+ err = au_d_hashed_positive(d); -+ else { -+ inode = d->d_inode; -+ if (unlikely(au_d_removed(d) || !inode || !inode->i_nlink)) -+ err = -ENOENT; -+ } -+ return err; -+} -+ -+static inline int au_alive_dir(struct dentry *d) -+{ -+ int err; -+ err = au_d_alive(d); -+ if (unlikely(err || IS_DEADDIR(d->d_inode))) -+ err = -ENOENT; -+ return err; -+} -+ -+#endif /* __KERNEL__ */ -+#endif /* __AUFS_DCSUB_H__ */ -diff -Nur linux-2.6.36.orig/fs/aufs/debug.c linux-2.6.36/fs/aufs/debug.c ---- linux-2.6.36.orig/fs/aufs/debug.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/debug.c 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,468 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * debug print functions -+ */ -+ -+#include -+#include -+#include "aufs.h" -+ -+int aufs_debug; -+MODULE_PARM_DESC(debug, "debug print"); -+module_param_named(debug, aufs_debug, int, S_IRUGO | S_IWUSR | S_IWGRP); -+ -+char *au_plevel = KERN_DEBUG; -+#define dpri(fmt, ...) do { \ -+ if ((au_plevel \ -+ && strcmp(au_plevel, KERN_DEBUG)) \ -+ || au_debug_test()) \ -+ printk("%s" fmt, au_plevel, ##__VA_ARGS__); \ -+} while (0) -+ -+/* ---------------------------------------------------------------------- */ -+ -+void au_dpri_whlist(struct au_nhash *whlist) -+{ -+ unsigned long ul, n; -+ struct hlist_head *head; -+ struct au_vdir_wh *tpos; -+ struct hlist_node *pos; -+ -+ n = whlist->nh_num; -+ head = whlist->nh_head; -+ for (ul = 0; ul < n; ul++) { -+ hlist_for_each_entry(tpos, pos, head, wh_hash) -+ dpri("b%d, %.*s, %d\n", -+ tpos->wh_bindex, -+ tpos->wh_str.len, tpos->wh_str.name, -+ tpos->wh_str.len); -+ head++; -+ } -+} -+ -+void au_dpri_vdir(struct au_vdir *vdir) -+{ -+ unsigned long ul; -+ union au_vdir_deblk_p p; -+ unsigned char *o; -+ -+ if (!vdir || IS_ERR(vdir)) { -+ dpri("err %ld\n", PTR_ERR(vdir)); -+ return; -+ } -+ -+ dpri("deblk %u, nblk %lu, deblk %p, last{%lu, %p}, ver %lu\n", -+ vdir->vd_deblk_sz, vdir->vd_nblk, vdir->vd_deblk, -+ vdir->vd_last.ul, vdir->vd_last.p.deblk, vdir->vd_version); -+ for (ul = 0; ul < vdir->vd_nblk; ul++) { -+ p.deblk = vdir->vd_deblk[ul]; -+ o = p.deblk; -+ dpri("[%lu]: %p\n", ul, o); -+ } -+} -+ -+static int do_pri_inode(aufs_bindex_t bindex, struct inode *inode, -+ struct dentry *wh) -+{ -+ char *n = NULL; -+ int l = 0; -+ -+ if (!inode || IS_ERR(inode)) { -+ dpri("i%d: err %ld\n", bindex, PTR_ERR(inode)); -+ return -1; -+ } -+ -+ /* the type of i_blocks depends upon CONFIG_LSF */ -+ BUILD_BUG_ON(sizeof(inode->i_blocks) != sizeof(unsigned long) -+ && sizeof(inode->i_blocks) != sizeof(u64)); -+ if (wh) { -+ n = (void *)wh->d_name.name; -+ l = wh->d_name.len; -+ } -+ -+ dpri("i%d: i%lu, %s, cnt %d, nl %u, 0%o, sz %llu, blk %llu," -+ " ct %lld, np %lu, st 0x%lx, f 0x%x, v %llu, g %x%s%.*s\n", -+ bindex, -+ inode->i_ino, inode->i_sb ? au_sbtype(inode->i_sb) : "??", -+ atomic_read(&inode->i_count), inode->i_nlink, inode->i_mode, -+ i_size_read(inode), (unsigned long long)inode->i_blocks, -+ (long long)timespec_to_ns(&inode->i_ctime) & 0x0ffff, -+ inode->i_mapping ? inode->i_mapping->nrpages : 0, -+ inode->i_state, inode->i_flags, inode->i_version, -+ inode->i_generation, -+ l ? ", wh " : "", l, n); -+ return 0; -+} -+ -+void au_dpri_inode(struct inode *inode) -+{ -+ struct au_iinfo *iinfo; -+ aufs_bindex_t bindex; -+ int err; -+ -+ err = do_pri_inode(-1, inode, NULL); -+ if (err || !au_test_aufs(inode->i_sb)) -+ return; -+ -+ iinfo = au_ii(inode); -+ if (!iinfo) -+ return; -+ dpri("i-1: bstart %d, bend %d, gen %d\n", -+ iinfo->ii_bstart, iinfo->ii_bend, au_iigen(inode)); -+ if (iinfo->ii_bstart < 0) -+ return; -+ for (bindex = iinfo->ii_bstart; bindex <= iinfo->ii_bend; bindex++) -+ do_pri_inode(bindex, iinfo->ii_hinode[0 + bindex].hi_inode, -+ iinfo->ii_hinode[0 + bindex].hi_whdentry); -+} -+ -+static int do_pri_dentry(aufs_bindex_t bindex, struct dentry *dentry) -+{ -+ struct dentry *wh = NULL; -+ -+ if (!dentry || IS_ERR(dentry)) { -+ dpri("d%d: err %ld\n", bindex, PTR_ERR(dentry)); -+ return -1; -+ } -+ /* do not call dget_parent() here */ -+ dpri("d%d: %.*s?/%.*s, %s, cnt %d, flags 0x%x\n", -+ bindex, -+ AuDLNPair(dentry->d_parent), AuDLNPair(dentry), -+ dentry->d_sb ? au_sbtype(dentry->d_sb) : "??", -+ atomic_read(&dentry->d_count), dentry->d_flags); -+ if (bindex >= 0 && dentry->d_inode && au_test_aufs(dentry->d_sb)) { -+ struct au_iinfo *iinfo = au_ii(dentry->d_inode); -+ if (iinfo) -+ wh = iinfo->ii_hinode[0 + bindex].hi_whdentry; -+ } -+ do_pri_inode(bindex, dentry->d_inode, wh); -+ return 0; -+} -+ -+void au_dpri_dentry(struct dentry *dentry) -+{ -+ struct au_dinfo *dinfo; -+ aufs_bindex_t bindex; -+ int err; -+ struct au_hdentry *hdp; -+ -+ err = do_pri_dentry(-1, dentry); -+ if (err || !au_test_aufs(dentry->d_sb)) -+ return; -+ -+ dinfo = au_di(dentry); -+ if (!dinfo) -+ return; -+ dpri("d-1: bstart %d, bend %d, bwh %d, bdiropq %d, gen %d\n", -+ dinfo->di_bstart, dinfo->di_bend, -+ dinfo->di_bwh, dinfo->di_bdiropq, au_digen(dentry)); -+ if (dinfo->di_bstart < 0) -+ return; -+ hdp = dinfo->di_hdentry; -+ for (bindex = dinfo->di_bstart; bindex <= dinfo->di_bend; bindex++) -+ do_pri_dentry(bindex, hdp[0 + bindex].hd_dentry); -+} -+ -+static int do_pri_file(aufs_bindex_t bindex, struct file *file) -+{ -+ char a[32]; -+ -+ if (!file || IS_ERR(file)) { -+ dpri("f%d: err %ld\n", bindex, PTR_ERR(file)); -+ return -1; -+ } -+ a[0] = 0; -+ if (bindex < 0 -+ && file->f_dentry -+ && au_test_aufs(file->f_dentry->d_sb) -+ && au_fi(file)) -+ snprintf(a, sizeof(a), ", gen %d, mmapped %d", -+ au_figen(file), !!au_fi(file)->fi_hvmop); -+ dpri("f%d: mode 0x%x, flags 0%o, cnt %ld, v %llu, pos %llu%s\n", -+ bindex, file->f_mode, file->f_flags, (long)file_count(file), -+ file->f_version, file->f_pos, a); -+ if (file->f_dentry) -+ do_pri_dentry(bindex, file->f_dentry); -+ return 0; -+} -+ -+void au_dpri_file(struct file *file) -+{ -+ struct au_finfo *finfo; -+ struct au_fidir *fidir; -+ struct au_hfile *hfile; -+ aufs_bindex_t bindex; -+ int err; -+ -+ err = do_pri_file(-1, file); -+ if (err || !file->f_dentry || !au_test_aufs(file->f_dentry->d_sb)) -+ return; -+ -+ finfo = au_fi(file); -+ if (!finfo) -+ return; -+ if (finfo->fi_btop < 0) -+ return; -+ fidir = finfo->fi_hdir; -+ if (!fidir) -+ do_pri_file(finfo->fi_btop, finfo->fi_htop.hf_file); -+ else -+ for (bindex = finfo->fi_btop; -+ bindex >= 0 && bindex <= fidir->fd_bbot; -+ bindex++) { -+ hfile = fidir->fd_hfile + bindex; -+ do_pri_file(bindex, hfile ? hfile->hf_file : NULL); -+ } -+} -+ -+static int do_pri_br(aufs_bindex_t bindex, struct au_branch *br) -+{ -+ struct vfsmount *mnt; -+ struct super_block *sb; -+ -+ if (!br || IS_ERR(br)) -+ goto out; -+ mnt = br->br_mnt; -+ if (!mnt || IS_ERR(mnt)) -+ goto out; -+ sb = mnt->mnt_sb; -+ if (!sb || IS_ERR(sb)) -+ goto out; -+ -+ dpri("s%d: {perm 0x%x, cnt %d, wbr %p}, " -+ "%s, dev 0x%02x%02x, flags 0x%lx, cnt %d, active %d, " -+ "xino %d\n", -+ bindex, br->br_perm, atomic_read(&br->br_count), br->br_wbr, -+ au_sbtype(sb), MAJOR(sb->s_dev), MINOR(sb->s_dev), -+ sb->s_flags, sb->s_count, -+ atomic_read(&sb->s_active), !!br->br_xino.xi_file); -+ return 0; -+ -+out: -+ dpri("s%d: err %ld\n", bindex, PTR_ERR(br)); -+ return -1; -+} -+ -+void au_dpri_sb(struct super_block *sb) -+{ -+ struct au_sbinfo *sbinfo; -+ aufs_bindex_t bindex; -+ int err; -+ /* to reuduce stack size */ -+ struct { -+ struct vfsmount mnt; -+ struct au_branch fake; -+ } *a; -+ -+ /* this function can be called from magic sysrq */ -+ a = kzalloc(sizeof(*a), GFP_ATOMIC); -+ if (unlikely(!a)) { -+ dpri("no memory\n"); -+ return; -+ } -+ -+ a->mnt.mnt_sb = sb; -+ a->fake.br_perm = 0; -+ a->fake.br_mnt = &a->mnt; -+ a->fake.br_xino.xi_file = NULL; -+ atomic_set(&a->fake.br_count, 0); -+ smp_mb(); /* atomic_set */ -+ err = do_pri_br(-1, &a->fake); -+ kfree(a); -+ dpri("dev 0x%x\n", sb->s_dev); -+ if (err || !au_test_aufs(sb)) -+ return; -+ -+ sbinfo = au_sbi(sb); -+ if (!sbinfo) -+ return; -+ dpri("nw %d, gen %u, kobj %d\n", -+ atomic_read(&sbinfo->si_nowait.nw_len), sbinfo->si_generation, -+ atomic_read(&sbinfo->si_kobj.kref.refcount)); -+ for (bindex = 0; bindex <= sbinfo->si_bend; bindex++) -+ do_pri_br(bindex, sbinfo->si_branch[0 + bindex]); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+void au_dbg_sleep_jiffy(int jiffy) -+{ -+ while (jiffy) -+ jiffy = schedule_timeout_uninterruptible(jiffy); -+} -+ -+void au_dbg_iattr(struct iattr *ia) -+{ -+#define AuBit(name) if (ia->ia_valid & ATTR_ ## name) \ -+ dpri(#name "\n") -+ AuBit(MODE); -+ AuBit(UID); -+ AuBit(GID); -+ AuBit(SIZE); -+ AuBit(ATIME); -+ AuBit(MTIME); -+ AuBit(CTIME); -+ AuBit(ATIME_SET); -+ AuBit(MTIME_SET); -+ AuBit(FORCE); -+ AuBit(ATTR_FLAG); -+ AuBit(KILL_SUID); -+ AuBit(KILL_SGID); -+ AuBit(FILE); -+ AuBit(KILL_PRIV); -+ AuBit(OPEN); -+ AuBit(TIMES_SET); -+#undef AuBit -+ dpri("ia_file %p\n", ia->ia_file); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+void __au_dbg_verify_dinode(struct dentry *dentry, const char *func, int line) -+{ -+ struct inode *h_inode, *inode = dentry->d_inode; -+ struct dentry *h_dentry; -+ aufs_bindex_t bindex, bend, bi; -+ -+ if (!inode /* || au_di(dentry)->di_lsc == AuLsc_DI_TMP */) -+ return; -+ -+ bend = au_dbend(dentry); -+ bi = au_ibend(inode); -+ if (bi < bend) -+ bend = bi; -+ bindex = au_dbstart(dentry); -+ bi = au_ibstart(inode); -+ if (bi > bindex) -+ bindex = bi; -+ -+ for (; bindex <= bend; bindex++) { -+ h_dentry = au_h_dptr(dentry, bindex); -+ if (!h_dentry) -+ continue; -+ h_inode = au_h_iptr(inode, bindex); -+ if (unlikely(h_inode != h_dentry->d_inode)) { -+ int old = au_debug_test(); -+ if (!old) -+ au_debug(1); -+ AuDbg("b%d, %s:%d\n", bindex, func, line); -+ AuDbgDentry(dentry); -+ AuDbgInode(inode); -+ if (!old) -+ au_debug(0); -+ BUG(); -+ } -+ } -+} -+ -+void au_dbg_verify_dir_parent(struct dentry *dentry, unsigned int sigen) -+{ -+ struct dentry *parent; -+ -+ parent = dget_parent(dentry); -+ AuDebugOn(!S_ISDIR(dentry->d_inode->i_mode)); -+ AuDebugOn(IS_ROOT(dentry)); -+ AuDebugOn(au_digen_test(parent, sigen)); -+ dput(parent); -+} -+ -+void au_dbg_verify_nondir_parent(struct dentry *dentry, unsigned int sigen) -+{ -+ struct dentry *parent; -+ struct inode *inode; -+ -+ parent = dget_parent(dentry); -+ inode = dentry->d_inode; -+ AuDebugOn(inode && S_ISDIR(dentry->d_inode->i_mode)); -+ AuDebugOn(au_digen_test(parent, sigen)); -+ dput(parent); -+} -+ -+void au_dbg_verify_gen(struct dentry *parent, unsigned int sigen) -+{ -+ int err, i, j; -+ struct au_dcsub_pages dpages; -+ struct au_dpage *dpage; -+ struct dentry **dentries; -+ -+ err = au_dpages_init(&dpages, GFP_NOFS); -+ AuDebugOn(err); -+ err = au_dcsub_pages_rev_aufs(&dpages, parent, /*do_include*/1); -+ AuDebugOn(err); -+ for (i = dpages.ndpage - 1; !err && i >= 0; i--) { -+ dpage = dpages.dpages + i; -+ dentries = dpage->dentries; -+ for (j = dpage->ndentry - 1; !err && j >= 0; j--) -+ AuDebugOn(au_digen_test(dentries[j], sigen)); -+ } -+ au_dpages_free(&dpages); -+} -+ -+void au_dbg_verify_kthread(void) -+{ -+ if (current->flags & PF_WQ_WORKER) { -+ au_dbg_blocked(); -+ WARN_ON(1); -+ } -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+void au_debug_sbinfo_init(struct au_sbinfo *sbinfo __maybe_unused) -+{ -+#ifdef AuForceNoPlink -+ au_opt_clr(sbinfo->si_mntflags, PLINK); -+#endif -+#ifdef AuForceNoXino -+ au_opt_clr(sbinfo->si_mntflags, XINO); -+#endif -+#ifdef AuForceNoRefrof -+ au_opt_clr(sbinfo->si_mntflags, REFROF); -+#endif -+#ifdef AuForceHnotify -+ au_opt_set_udba(sbinfo->si_mntflags, UDBA_HNOTIFY); -+#endif -+#ifdef AuForceRd0 -+ sbinfo->si_rdblk = 0; -+ sbinfo->si_rdhash = 0; -+#endif -+} -+ -+int __init au_debug_init(void) -+{ -+ aufs_bindex_t bindex; -+ struct au_vdir_destr destr; -+ -+ bindex = -1; -+ AuDebugOn(bindex >= 0); -+ -+ destr.len = -1; -+ AuDebugOn(destr.len < NAME_MAX); -+ -+#ifdef CONFIG_4KSTACKS -+ pr_warning("CONFIG_4KSTACKS is defined.\n"); -+#endif -+ -+#ifdef AuForceNoBrs -+ sysaufs_brs = 0; -+#endif -+ -+ return 0; -+} -diff -Nur linux-2.6.36.orig/fs/aufs/debug.h linux-2.6.36/fs/aufs/debug.h ---- linux-2.6.36.orig/fs/aufs/debug.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/debug.h 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,245 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * debug print functions -+ */ -+ -+#ifndef __AUFS_DEBUG_H__ -+#define __AUFS_DEBUG_H__ -+ -+#ifdef __KERNEL__ -+ -+#include -+#include -+/* #include */ -+#include -+#include -+#include -+/* #include */ -+#include -+/* #include */ -+#include -+#include -+ -+#include -+ -+#ifdef CONFIG_AUFS_DEBUG -+#define AuDebugOn(a) BUG_ON(a) -+ -+/* module parameter */ -+extern int aufs_debug; -+static inline void au_debug(int n) -+{ -+ aufs_debug = n; -+ smp_mb(); -+} -+ -+static inline int au_debug_test(void) -+{ -+ return aufs_debug; -+} -+#else -+#define AuDebugOn(a) do {} while (0) -+AuStubVoid(au_debug, int n) -+AuStubInt0(au_debug_test, void) -+#endif /* CONFIG_AUFS_DEBUG */ -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* debug print */ -+ -+#define AuDbg(fmt, ...) do { \ -+ if (au_debug_test()) \ -+ pr_debug("DEBUG: " fmt, ##__VA_ARGS__); \ -+} while (0) -+#define AuLabel(l) AuDbg(#l "\n") -+#define AuIOErr(fmt, ...) pr_err("I/O Error, " fmt, ##__VA_ARGS__) -+#define AuWarn1(fmt, ...) do { \ -+ static unsigned char _c; \ -+ if (!_c++) \ -+ pr_warning(fmt, ##__VA_ARGS__); \ -+} while (0) -+ -+#define AuErr1(fmt, ...) do { \ -+ static unsigned char _c; \ -+ if (!_c++) \ -+ pr_err(fmt, ##__VA_ARGS__); \ -+} while (0) -+ -+#define AuIOErr1(fmt, ...) do { \ -+ static unsigned char _c; \ -+ if (!_c++) \ -+ AuIOErr(fmt, ##__VA_ARGS__); \ -+} while (0) -+ -+#define AuUnsupportMsg "This operation is not supported." \ -+ " Please report this application to aufs-users ML." -+#define AuUnsupport(fmt, ...) do { \ -+ pr_err(AuUnsupportMsg "\n" fmt, ##__VA_ARGS__); \ -+ dump_stack(); \ -+} while (0) -+ -+#define AuTraceErr(e) do { \ -+ if (unlikely((e) < 0)) \ -+ AuDbg("err %d\n", (int)(e)); \ -+} while (0) -+ -+#define AuTraceErrPtr(p) do { \ -+ if (IS_ERR(p)) \ -+ AuDbg("err %ld\n", PTR_ERR(p)); \ -+} while (0) -+ -+/* dirty macros for debug print, use with "%.*s" and caution */ -+#define AuLNPair(qstr) (qstr)->len, (qstr)->name -+#define AuDLNPair(d) AuLNPair(&(d)->d_name) -+ -+/* ---------------------------------------------------------------------- */ -+ -+struct au_sbinfo; -+struct au_finfo; -+struct dentry; -+#ifdef CONFIG_AUFS_DEBUG -+extern char *au_plevel; -+struct au_nhash; -+void au_dpri_whlist(struct au_nhash *whlist); -+struct au_vdir; -+void au_dpri_vdir(struct au_vdir *vdir); -+struct inode; -+void au_dpri_inode(struct inode *inode); -+void au_dpri_dentry(struct dentry *dentry); -+struct file; -+void au_dpri_file(struct file *filp); -+struct super_block; -+void au_dpri_sb(struct super_block *sb); -+ -+void au_dbg_sleep_jiffy(int jiffy); -+struct iattr; -+void au_dbg_iattr(struct iattr *ia); -+ -+#define au_dbg_verify_dinode(d) __au_dbg_verify_dinode(d, __func__, __LINE__) -+void __au_dbg_verify_dinode(struct dentry *dentry, const char *func, int line); -+void au_dbg_verify_dir_parent(struct dentry *dentry, unsigned int sigen); -+void au_dbg_verify_nondir_parent(struct dentry *dentry, unsigned int sigen); -+void au_dbg_verify_gen(struct dentry *parent, unsigned int sigen); -+void au_dbg_verify_kthread(void); -+ -+int __init au_debug_init(void); -+void au_debug_sbinfo_init(struct au_sbinfo *sbinfo); -+#define AuDbgWhlist(w) do { \ -+ AuDbg(#w "\n"); \ -+ au_dpri_whlist(w); \ -+} while (0) -+ -+#define AuDbgVdir(v) do { \ -+ AuDbg(#v "\n"); \ -+ au_dpri_vdir(v); \ -+} while (0) -+ -+#define AuDbgInode(i) do { \ -+ AuDbg(#i "\n"); \ -+ au_dpri_inode(i); \ -+} while (0) -+ -+#define AuDbgDentry(d) do { \ -+ AuDbg(#d "\n"); \ -+ au_dpri_dentry(d); \ -+} while (0) -+ -+#define AuDbgFile(f) do { \ -+ AuDbg(#f "\n"); \ -+ au_dpri_file(f); \ -+} while (0) -+ -+#define AuDbgSb(sb) do { \ -+ AuDbg(#sb "\n"); \ -+ au_dpri_sb(sb); \ -+} while (0) -+ -+#define AuDbgSleep(sec) do { \ -+ AuDbg("sleep %d sec\n", sec); \ -+ ssleep(sec); \ -+} while (0) -+ -+#define AuDbgSleepJiffy(jiffy) do { \ -+ AuDbg("sleep %d jiffies\n", jiffy); \ -+ au_dbg_sleep_jiffy(jiffy); \ -+} while (0) -+ -+#define AuDbgIAttr(ia) do { \ -+ AuDbg("ia_valid 0x%x\n", (ia)->ia_valid); \ -+ au_dbg_iattr(ia); \ -+} while (0) -+ -+#define AuDbgSym(addr) do { \ -+ char sym[KSYM_SYMBOL_LEN]; \ -+ sprint_symbol(sym, (unsigned long)addr); \ -+ AuDbg("%s\n", sym); \ -+} while (0) -+ -+#define AuInfoSym(addr) do { \ -+ char sym[KSYM_SYMBOL_LEN]; \ -+ sprint_symbol(sym, (unsigned long)addr); \ -+ AuInfo("%s\n", sym); \ -+} while (0) -+#else -+AuStubVoid(au_dbg_verify_dinode, struct dentry *dentry) -+AuStubVoid(au_dbg_verify_dir_parent, struct dentry *dentry, unsigned int sigen) -+AuStubVoid(au_dbg_verify_nondir_parent, struct dentry *dentry, -+ unsigned int sigen) -+AuStubVoid(au_dbg_verify_gen, struct dentry *parent, unsigned int sigen) -+AuStubVoid(au_dbg_verify_kthread, void) -+AuStubInt0(__init au_debug_init, void) -+AuStubVoid(au_debug_sbinfo_init, struct au_sbinfo *sbinfo) -+ -+#define AuDbgWhlist(w) do {} while (0) -+#define AuDbgVdir(v) do {} while (0) -+#define AuDbgInode(i) do {} while (0) -+#define AuDbgDentry(d) do {} while (0) -+#define AuDbgFile(f) do {} while (0) -+#define AuDbgSb(sb) do {} while (0) -+#define AuDbgSleep(sec) do {} while (0) -+#define AuDbgSleepJiffy(jiffy) do {} while (0) -+#define AuDbgIAttr(ia) do {} while (0) -+#define AuDbgSym(addr) do {} while (0) -+#define AuInfoSym(addr) do {} while (0) -+#endif /* CONFIG_AUFS_DEBUG */ -+ -+/* ---------------------------------------------------------------------- */ -+ -+#ifdef CONFIG_AUFS_MAGIC_SYSRQ -+int __init au_sysrq_init(void); -+void au_sysrq_fin(void); -+ -+#ifdef CONFIG_HW_CONSOLE -+#define au_dbg_blocked() do { \ -+ WARN_ON(1); \ -+ handle_sysrq('w'); \ -+} while (0) -+#else -+AuStubVoid(au_dbg_blocked, void) -+#endif -+ -+#else -+AuStubInt0(__init au_sysrq_init, void) -+AuStubVoid(au_sysrq_fin, void) -+AuStubVoid(au_dbg_blocked, void) -+#endif /* CONFIG_AUFS_MAGIC_SYSRQ */ -+ -+#endif /* __KERNEL__ */ -+#endif /* __AUFS_DEBUG_H__ */ -diff -Nur linux-2.6.36.orig/fs/aufs/dentry.c linux-2.6.36/fs/aufs/dentry.c ---- linux-2.6.36.orig/fs/aufs/dentry.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/dentry.c 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,1131 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * lookup and dentry operations -+ */ -+ -+#include -+#include "aufs.h" -+ -+static void au_h_nd(struct nameidata *h_nd, struct nameidata *nd) -+{ -+ if (nd) { -+ *h_nd = *nd; -+ -+ /* -+ * gave up supporting LOOKUP_CREATE/OPEN for lower fs, -+ * due to whiteout and branch permission. -+ */ -+ h_nd->flags &= ~(/*LOOKUP_PARENT |*/ LOOKUP_OPEN | LOOKUP_CREATE -+ | LOOKUP_FOLLOW | LOOKUP_EXCL); -+ /* unnecessary? */ -+ h_nd->intent.open.file = NULL; -+ } else -+ memset(h_nd, 0, sizeof(*h_nd)); -+} -+ -+struct au_lkup_one_args { -+ struct dentry **errp; -+ struct qstr *name; -+ struct dentry *h_parent; -+ struct au_branch *br; -+ struct nameidata *nd; -+}; -+ -+struct dentry *au_lkup_one(struct qstr *name, struct dentry *h_parent, -+ struct au_branch *br, struct nameidata *nd) -+{ -+ struct dentry *h_dentry; -+ int err; -+ struct nameidata h_nd; -+ -+ if (au_test_fs_null_nd(h_parent->d_sb)) -+ return vfsub_lookup_one_len(name->name, h_parent, name->len); -+ -+ au_h_nd(&h_nd, nd); -+ h_nd.path.dentry = h_parent; -+ h_nd.path.mnt = br->br_mnt; -+ -+ err = __lookup_one_len(name->name, &h_nd.last, NULL, name->len); -+ h_dentry = ERR_PTR(err); -+ if (!err) { -+ path_get(&h_nd.path); -+ h_dentry = vfsub_lookup_hash(&h_nd); -+ path_put(&h_nd.path); -+ } -+ -+ AuTraceErrPtr(h_dentry); -+ return h_dentry; -+} -+ -+static void au_call_lkup_one(void *args) -+{ -+ struct au_lkup_one_args *a = args; -+ *a->errp = au_lkup_one(a->name, a->h_parent, a->br, a->nd); -+} -+ -+#define AuLkup_ALLOW_NEG 1 -+#define au_ftest_lkup(flags, name) ((flags) & AuLkup_##name) -+#define au_fset_lkup(flags, name) \ -+ do { (flags) |= AuLkup_##name; } while (0) -+#define au_fclr_lkup(flags, name) \ -+ do { (flags) &= ~AuLkup_##name; } while (0) -+ -+struct au_do_lookup_args { -+ unsigned int flags; -+ mode_t type; -+ struct nameidata *nd; -+}; -+ -+/* -+ * returns positive/negative dentry, NULL or an error. -+ * NULL means whiteout-ed or not-found. -+ */ -+static struct dentry* -+au_do_lookup(struct dentry *h_parent, struct dentry *dentry, -+ aufs_bindex_t bindex, struct qstr *wh_name, -+ struct au_do_lookup_args *args) -+{ -+ struct dentry *h_dentry; -+ struct inode *h_inode, *inode; -+ struct au_branch *br; -+ int wh_found, opq; -+ unsigned char wh_able; -+ const unsigned char allow_neg = !!au_ftest_lkup(args->flags, ALLOW_NEG); -+ -+ wh_found = 0; -+ br = au_sbr(dentry->d_sb, bindex); -+ wh_able = !!au_br_whable(br->br_perm); -+ if (wh_able) -+ wh_found = au_wh_test(h_parent, wh_name, br, /*try_sio*/0); -+ h_dentry = ERR_PTR(wh_found); -+ if (!wh_found) -+ goto real_lookup; -+ if (unlikely(wh_found < 0)) -+ goto out; -+ -+ /* We found a whiteout */ -+ /* au_set_dbend(dentry, bindex); */ -+ au_set_dbwh(dentry, bindex); -+ if (!allow_neg) -+ return NULL; /* success */ -+ -+real_lookup: -+ h_dentry = au_lkup_one(&dentry->d_name, h_parent, br, args->nd); -+ if (IS_ERR(h_dentry)) -+ goto out; -+ -+ h_inode = h_dentry->d_inode; -+ if (!h_inode) { -+ if (!allow_neg) -+ goto out_neg; -+ } else if (wh_found -+ || (args->type && args->type != (h_inode->i_mode & S_IFMT))) -+ goto out_neg; -+ -+ if (au_dbend(dentry) <= bindex) -+ au_set_dbend(dentry, bindex); -+ if (au_dbstart(dentry) < 0 || bindex < au_dbstart(dentry)) -+ au_set_dbstart(dentry, bindex); -+ au_set_h_dptr(dentry, bindex, h_dentry); -+ -+ inode = dentry->d_inode; -+ if (!h_inode || !S_ISDIR(h_inode->i_mode) || !wh_able -+ || (inode && !S_ISDIR(inode->i_mode))) -+ goto out; /* success */ -+ -+ mutex_lock_nested(&h_inode->i_mutex, AuLsc_I_CHILD); -+ opq = au_diropq_test(h_dentry, br); -+ mutex_unlock(&h_inode->i_mutex); -+ if (opq > 0) -+ au_set_dbdiropq(dentry, bindex); -+ else if (unlikely(opq < 0)) { -+ au_set_h_dptr(dentry, bindex, NULL); -+ h_dentry = ERR_PTR(opq); -+ } -+ goto out; -+ -+out_neg: -+ dput(h_dentry); -+ h_dentry = NULL; -+out: -+ return h_dentry; -+} -+ -+static int au_test_shwh(struct super_block *sb, const struct qstr *name) -+{ -+ if (unlikely(!au_opt_test(au_mntflags(sb), SHWH) -+ && !strncmp(name->name, AUFS_WH_PFX, AUFS_WH_PFX_LEN))) -+ return -EPERM; -+ return 0; -+} -+ -+/* -+ * returns the number of lower positive dentries, -+ * otherwise an error. -+ * can be called at unlinking with @type is zero. -+ */ -+int au_lkup_dentry(struct dentry *dentry, aufs_bindex_t bstart, mode_t type, -+ struct nameidata *nd) -+{ -+ int npositive, err; -+ aufs_bindex_t bindex, btail, bdiropq; -+ unsigned char isdir; -+ struct qstr whname; -+ struct au_do_lookup_args args = { -+ .flags = 0, -+ .type = type, -+ .nd = nd -+ }; -+ const struct qstr *name = &dentry->d_name; -+ struct dentry *parent; -+ struct inode *inode; -+ -+ err = au_test_shwh(dentry->d_sb, name); -+ if (unlikely(err)) -+ goto out; -+ -+ err = au_wh_name_alloc(&whname, name); -+ if (unlikely(err)) -+ goto out; -+ -+ inode = dentry->d_inode; -+ isdir = !!(inode && S_ISDIR(inode->i_mode)); -+ if (!type) -+ au_fset_lkup(args.flags, ALLOW_NEG); -+ -+ npositive = 0; -+ parent = dget_parent(dentry); -+ btail = au_dbtaildir(parent); -+ for (bindex = bstart; bindex <= btail; bindex++) { -+ struct dentry *h_parent, *h_dentry; -+ struct inode *h_inode, *h_dir; -+ -+ h_dentry = au_h_dptr(dentry, bindex); -+ if (h_dentry) { -+ if (h_dentry->d_inode) -+ npositive++; -+ if (type != S_IFDIR) -+ break; -+ continue; -+ } -+ h_parent = au_h_dptr(parent, bindex); -+ if (!h_parent) -+ continue; -+ h_dir = h_parent->d_inode; -+ if (!h_dir || !S_ISDIR(h_dir->i_mode)) -+ continue; -+ -+ mutex_lock_nested(&h_dir->i_mutex, AuLsc_I_PARENT); -+ h_dentry = au_do_lookup(h_parent, dentry, bindex, &whname, -+ &args); -+ mutex_unlock(&h_dir->i_mutex); -+ err = PTR_ERR(h_dentry); -+ if (IS_ERR(h_dentry)) -+ goto out_parent; -+ au_fclr_lkup(args.flags, ALLOW_NEG); -+ -+ if (au_dbwh(dentry) >= 0) -+ break; -+ if (!h_dentry) -+ continue; -+ h_inode = h_dentry->d_inode; -+ if (!h_inode) -+ continue; -+ npositive++; -+ if (!args.type) -+ args.type = h_inode->i_mode & S_IFMT; -+ if (args.type != S_IFDIR) -+ break; -+ else if (isdir) { -+ /* the type of lower may be different */ -+ bdiropq = au_dbdiropq(dentry); -+ if (bdiropq >= 0 && bdiropq <= bindex) -+ break; -+ } -+ } -+ -+ if (npositive) { -+ AuLabel(positive); -+ au_update_dbstart(dentry); -+ } -+ err = npositive; -+ if (unlikely(!au_opt_test(au_mntflags(dentry->d_sb), UDBA_NONE) -+ && au_dbstart(dentry) < 0)) { -+ err = -EIO; -+ AuIOErr("both of real entry and whiteout found, %.*s, err %d\n", -+ AuDLNPair(dentry), err); -+ } -+ -+out_parent: -+ dput(parent); -+ kfree(whname.name); -+out: -+ return err; -+} -+ -+struct dentry *au_sio_lkup_one(struct qstr *name, struct dentry *parent, -+ struct au_branch *br) -+{ -+ struct dentry *dentry; -+ int wkq_err; -+ -+ if (!au_test_h_perm_sio(parent->d_inode, MAY_EXEC)) -+ dentry = au_lkup_one(name, parent, br, /*nd*/NULL); -+ else { -+ struct au_lkup_one_args args = { -+ .errp = &dentry, -+ .name = name, -+ .h_parent = parent, -+ .br = br, -+ .nd = NULL -+ }; -+ -+ wkq_err = au_wkq_wait(au_call_lkup_one, &args); -+ if (unlikely(wkq_err)) -+ dentry = ERR_PTR(wkq_err); -+ } -+ -+ return dentry; -+} -+ -+/* -+ * lookup @dentry on @bindex which should be negative. -+ */ -+int au_lkup_neg(struct dentry *dentry, aufs_bindex_t bindex) -+{ -+ int err; -+ struct dentry *parent, *h_parent, *h_dentry; -+ -+ parent = dget_parent(dentry); -+ h_parent = au_h_dptr(parent, bindex); -+ h_dentry = au_sio_lkup_one(&dentry->d_name, h_parent, -+ au_sbr(dentry->d_sb, bindex)); -+ err = PTR_ERR(h_dentry); -+ if (IS_ERR(h_dentry)) -+ goto out; -+ if (unlikely(h_dentry->d_inode)) { -+ err = -EIO; -+ AuIOErr("%.*s should be negative on b%d.\n", -+ AuDLNPair(h_dentry), bindex); -+ dput(h_dentry); -+ goto out; -+ } -+ -+ err = 0; -+ if (bindex < au_dbstart(dentry)) -+ au_set_dbstart(dentry, bindex); -+ if (au_dbend(dentry) < bindex) -+ au_set_dbend(dentry, bindex); -+ au_set_h_dptr(dentry, bindex, h_dentry); -+ -+out: -+ dput(parent); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* subset of struct inode */ -+struct au_iattr { -+ unsigned long i_ino; -+ /* unsigned int i_nlink; */ -+ uid_t i_uid; -+ gid_t i_gid; -+ u64 i_version; -+/* -+ loff_t i_size; -+ blkcnt_t i_blocks; -+*/ -+ umode_t i_mode; -+}; -+ -+static void au_iattr_save(struct au_iattr *ia, struct inode *h_inode) -+{ -+ ia->i_ino = h_inode->i_ino; -+ /* ia->i_nlink = h_inode->i_nlink; */ -+ ia->i_uid = h_inode->i_uid; -+ ia->i_gid = h_inode->i_gid; -+ ia->i_version = h_inode->i_version; -+/* -+ ia->i_size = h_inode->i_size; -+ ia->i_blocks = h_inode->i_blocks; -+*/ -+ ia->i_mode = (h_inode->i_mode & S_IFMT); -+} -+ -+static int au_iattr_test(struct au_iattr *ia, struct inode *h_inode) -+{ -+ return ia->i_ino != h_inode->i_ino -+ /* || ia->i_nlink != h_inode->i_nlink */ -+ || ia->i_uid != h_inode->i_uid -+ || ia->i_gid != h_inode->i_gid -+ || ia->i_version != h_inode->i_version -+/* -+ || ia->i_size != h_inode->i_size -+ || ia->i_blocks != h_inode->i_blocks -+*/ -+ || ia->i_mode != (h_inode->i_mode & S_IFMT); -+} -+ -+static int au_h_verify_dentry(struct dentry *h_dentry, struct dentry *h_parent, -+ struct au_branch *br) -+{ -+ int err; -+ struct au_iattr ia; -+ struct inode *h_inode; -+ struct dentry *h_d; -+ struct super_block *h_sb; -+ -+ err = 0; -+ memset(&ia, -1, sizeof(ia)); -+ h_sb = h_dentry->d_sb; -+ h_inode = h_dentry->d_inode; -+ if (h_inode) -+ au_iattr_save(&ia, h_inode); -+ else if (au_test_nfs(h_sb) || au_test_fuse(h_sb)) -+ /* nfs d_revalidate may return 0 for negative dentry */ -+ /* fuse d_revalidate always return 0 for negative dentry */ -+ goto out; -+ -+ /* main purpose is namei.c:cached_lookup() and d_revalidate */ -+ h_d = au_lkup_one(&h_dentry->d_name, h_parent, br, /*nd*/NULL); -+ err = PTR_ERR(h_d); -+ if (IS_ERR(h_d)) -+ goto out; -+ -+ err = 0; -+ if (unlikely(h_d != h_dentry -+ || h_d->d_inode != h_inode -+ || (h_inode && au_iattr_test(&ia, h_inode)))) -+ err = au_busy_or_stale(); -+ dput(h_d); -+ -+out: -+ AuTraceErr(err); -+ return err; -+} -+ -+int au_h_verify(struct dentry *h_dentry, unsigned int udba, struct inode *h_dir, -+ struct dentry *h_parent, struct au_branch *br) -+{ -+ int err; -+ -+ err = 0; -+ if (udba == AuOpt_UDBA_REVAL) { -+ IMustLock(h_dir); -+ err = (h_dentry->d_parent->d_inode != h_dir); -+ } else if (udba == AuOpt_UDBA_HNOTIFY) -+ err = au_h_verify_dentry(h_dentry, h_parent, br); -+ -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int au_do_refresh_hdentry(struct dentry *dentry, struct dentry *parent) -+{ -+ int err; -+ aufs_bindex_t new_bindex, bindex, bend, bwh, bdiropq; -+ struct au_hdentry tmp, *p, *q; -+ struct au_dinfo *dinfo; -+ struct super_block *sb; -+ -+ DiMustWriteLock(dentry); -+ -+ sb = dentry->d_sb; -+ dinfo = au_di(dentry); -+ bend = dinfo->di_bend; -+ bwh = dinfo->di_bwh; -+ bdiropq = dinfo->di_bdiropq; -+ p = dinfo->di_hdentry + dinfo->di_bstart; -+ for (bindex = dinfo->di_bstart; bindex <= bend; bindex++, p++) { -+ if (!p->hd_dentry) -+ continue; -+ -+ new_bindex = au_br_index(sb, p->hd_id); -+ if (new_bindex == bindex) -+ continue; -+ -+ if (dinfo->di_bwh == bindex) -+ bwh = new_bindex; -+ if (dinfo->di_bdiropq == bindex) -+ bdiropq = new_bindex; -+ if (new_bindex < 0) { -+ au_hdput(p); -+ p->hd_dentry = NULL; -+ continue; -+ } -+ -+ /* swap two lower dentries, and loop again */ -+ q = dinfo->di_hdentry + new_bindex; -+ tmp = *q; -+ *q = *p; -+ *p = tmp; -+ if (tmp.hd_dentry) { -+ bindex--; -+ p--; -+ } -+ } -+ -+ dinfo->di_bwh = -1; -+ if (bwh >= 0 && bwh <= au_sbend(sb) && au_sbr_whable(sb, bwh)) -+ dinfo->di_bwh = bwh; -+ -+ dinfo->di_bdiropq = -1; -+ if (bdiropq >= 0 -+ && bdiropq <= au_sbend(sb) -+ && au_sbr_whable(sb, bdiropq)) -+ dinfo->di_bdiropq = bdiropq; -+ -+ err = -EIO; -+ dinfo->di_bstart = -1; -+ dinfo->di_bend = -1; -+ bend = au_dbend(parent); -+ p = dinfo->di_hdentry; -+ for (bindex = 0; bindex <= bend; bindex++, p++) -+ if (p->hd_dentry) { -+ dinfo->di_bstart = bindex; -+ break; -+ } -+ -+ if (dinfo->di_bstart >= 0) { -+ p = dinfo->di_hdentry + bend; -+ for (bindex = bend; bindex >= 0; bindex--, p--) -+ if (p->hd_dentry) { -+ dinfo->di_bend = bindex; -+ err = 0; -+ break; -+ } -+ } -+ -+ return err; -+} -+ -+static void au_do_hide(struct dentry *dentry) -+{ -+ struct inode *inode; -+ -+ inode = dentry->d_inode; -+ if (inode) { -+ if (!S_ISDIR(inode->i_mode)) { -+ if (inode->i_nlink && !d_unhashed(dentry)) -+ drop_nlink(inode); -+ } else { -+ clear_nlink(inode); -+ /* stop next lookup */ -+ inode->i_flags |= S_DEAD; -+ } -+ smp_mb(); /* necessary? */ -+ } -+ d_drop(dentry); -+} -+ -+static int au_hide_children(struct dentry *parent) -+{ -+ int err, i, j, ndentry; -+ struct au_dcsub_pages dpages; -+ struct au_dpage *dpage; -+ struct dentry *dentry; -+ -+ err = au_dpages_init(&dpages, GFP_NOFS); -+ if (unlikely(err)) -+ goto out; -+ err = au_dcsub_pages(&dpages, parent, NULL, NULL); -+ if (unlikely(err)) -+ goto out_dpages; -+ -+ /* in reverse order */ -+ for (i = dpages.ndpage - 1; i >= 0; i--) { -+ dpage = dpages.dpages + i; -+ ndentry = dpage->ndentry; -+ for (j = ndentry - 1; j >= 0; j--) { -+ dentry = dpage->dentries[j]; -+ if (dentry != parent) -+ au_do_hide(dentry); -+ } -+ } -+ -+out_dpages: -+ au_dpages_free(&dpages); -+out: -+ return err; -+} -+ -+static void au_hide(struct dentry *dentry) -+{ -+ int err; -+ struct inode *inode; -+ -+ AuDbgDentry(dentry); -+ inode = dentry->d_inode; -+ if (inode && S_ISDIR(inode->i_mode)) { -+ /* shrink_dcache_parent(dentry); */ -+ err = au_hide_children(dentry); -+ if (unlikely(err)) -+ AuIOErr("%.*s, failed hiding children, ignored %d\n", -+ AuDLNPair(dentry), err); -+ } -+ au_do_hide(dentry); -+} -+ -+/* -+ * By adding a dirty branch, a cached dentry may be affected in various ways. -+ * -+ * a dirty branch is added -+ * - on the top of layers -+ * - in the middle of layers -+ * - to the bottom of layers -+ * -+ * on the added branch there exists -+ * - a whiteout -+ * - a diropq -+ * - a same named entry -+ * + exist -+ * * negative --> positive -+ * * positive --> positive -+ * - type is unchanged -+ * - type is changed -+ * + doesn't exist -+ * * negative --> negative -+ * * positive --> negative (rejected by au_br_del() for non-dir case) -+ * - none -+ */ -+static int au_refresh_by_dinfo(struct dentry *dentry, struct au_dinfo *dinfo, -+ struct au_dinfo *tmp) -+{ -+ int err; -+ aufs_bindex_t bindex, bend; -+ struct { -+ struct dentry *dentry; -+ struct inode *inode; -+ mode_t mode; -+ } orig_h, tmp_h; -+ struct au_hdentry *hd; -+ struct inode *inode, *h_inode; -+ struct dentry *h_dentry; -+ -+ err = 0; -+ AuDebugOn(dinfo->di_bstart < 0); -+ orig_h.dentry = dinfo->di_hdentry[dinfo->di_bstart].hd_dentry; -+ orig_h.inode = orig_h.dentry->d_inode; -+ orig_h.mode = 0; -+ if (orig_h.inode) -+ orig_h.mode = orig_h.inode->i_mode & S_IFMT; -+ memset(&tmp_h, 0, sizeof(tmp_h)); -+ if (tmp->di_bstart >= 0) { -+ tmp_h.dentry = tmp->di_hdentry[tmp->di_bstart].hd_dentry; -+ tmp_h.inode = tmp_h.dentry->d_inode; -+ if (tmp_h.inode) -+ tmp_h.mode = tmp_h.inode->i_mode & S_IFMT; -+ } -+ -+ inode = dentry->d_inode; -+ if (!orig_h.inode) { -+ AuDbg("nagative originally\n"); -+ if (inode) { -+ au_hide(dentry); -+ goto out; -+ } -+ AuDebugOn(inode); -+ AuDebugOn(dinfo->di_bstart != dinfo->di_bend); -+ AuDebugOn(dinfo->di_bdiropq != -1); -+ -+ if (!tmp_h.inode) { -+ AuDbg("negative --> negative\n"); -+ /* should have only one negative lower */ -+ if (tmp->di_bstart >= 0 -+ && tmp->di_bstart < dinfo->di_bstart) { -+ AuDebugOn(tmp->di_bstart != tmp->di_bend); -+ AuDebugOn(dinfo->di_bstart != dinfo->di_bend); -+ au_set_h_dptr(dentry, dinfo->di_bstart, NULL); -+ au_di_cp(dinfo, tmp); -+ hd = tmp->di_hdentry + tmp->di_bstart; -+ au_set_h_dptr(dentry, tmp->di_bstart, -+ dget(hd->hd_dentry)); -+ } -+ au_dbg_verify_dinode(dentry); -+ } else { -+ AuDbg("negative --> positive\n"); -+ /* -+ * similar to the behaviour of creating with bypassing -+ * aufs. -+ * unhash it in order to force an error in the -+ * succeeding create operation. -+ * we should not set S_DEAD here. -+ */ -+ d_drop(dentry); -+ /* au_di_swap(tmp, dinfo); */ -+ au_dbg_verify_dinode(dentry); -+ } -+ } else { -+ AuDbg("positive originally\n"); -+ /* inode may be NULL */ -+ AuDebugOn(inode && (inode->i_mode & S_IFMT) != orig_h.mode); -+ if (!tmp_h.inode) { -+ AuDbg("positive --> negative\n"); -+ /* or bypassing aufs */ -+ au_hide(dentry); -+ if (tmp->di_bwh >= 0 && tmp->di_bwh <= dinfo->di_bstart) -+ dinfo->di_bwh = tmp->di_bwh; -+ if (inode) -+ err = au_refresh_hinode_self(inode); -+ au_dbg_verify_dinode(dentry); -+ } else if (orig_h.mode == tmp_h.mode) { -+ AuDbg("positive --> positive, same type\n"); -+ if (!S_ISDIR(orig_h.mode) -+ && dinfo->di_bstart > tmp->di_bstart) { -+ /* -+ * similar to the behaviour of removing and -+ * creating. -+ */ -+ au_hide(dentry); -+ if (inode) -+ err = au_refresh_hinode_self(inode); -+ au_dbg_verify_dinode(dentry); -+ } else { -+ /* fill empty slots */ -+ if (dinfo->di_bstart > tmp->di_bstart) -+ dinfo->di_bstart = tmp->di_bstart; -+ if (dinfo->di_bend < tmp->di_bend) -+ dinfo->di_bend = tmp->di_bend; -+ dinfo->di_bwh = tmp->di_bwh; -+ dinfo->di_bdiropq = tmp->di_bdiropq; -+ hd = tmp->di_hdentry; -+ bend = dinfo->di_bend; -+ for (bindex = tmp->di_bstart; bindex <= bend; -+ bindex++) { -+ if (au_h_dptr(dentry, bindex)) -+ continue; -+ h_dentry = hd[bindex].hd_dentry; -+ if (!h_dentry) -+ continue; -+ h_inode = h_dentry->d_inode; -+ AuDebugOn(!h_inode); -+ AuDebugOn(orig_h.mode -+ != (h_inode->i_mode -+ & S_IFMT)); -+ au_set_h_dptr(dentry, bindex, -+ dget(h_dentry)); -+ } -+ err = au_refresh_hinode(inode, dentry); -+ au_dbg_verify_dinode(dentry); -+ } -+ } else { -+ AuDbg("positive --> positive, different type\n"); -+ /* similar to the behaviour of removing and creating */ -+ au_hide(dentry); -+ if (inode) -+ err = au_refresh_hinode_self(inode); -+ au_dbg_verify_dinode(dentry); -+ } -+ } -+ -+out: -+ return err; -+} -+ -+int au_refresh_dentry(struct dentry *dentry, struct dentry *parent) -+{ -+ int err, ebrange; -+ unsigned int sigen; -+ struct au_dinfo *dinfo, *tmp; -+ struct super_block *sb; -+ struct inode *inode; -+ -+ DiMustWriteLock(dentry); -+ AuDebugOn(IS_ROOT(dentry)); -+ AuDebugOn(!parent->d_inode); -+ -+ sb = dentry->d_sb; -+ inode = dentry->d_inode; -+ sigen = au_sigen(sb); -+ err = au_digen_test(parent, sigen); -+ if (unlikely(err)) -+ goto out; -+ -+ dinfo = au_di(dentry); -+ err = au_di_realloc(dinfo, au_sbend(sb) + 1); -+ if (unlikely(err)) -+ goto out; -+ ebrange = au_dbrange_test(dentry); -+ if (!ebrange) -+ ebrange = au_do_refresh_hdentry(dentry, parent); -+ -+ if (d_unhashed(dentry) || ebrange) { -+ AuDebugOn(au_dbstart(dentry) < 0 && au_dbend(dentry) >= 0); -+ if (inode) -+ err = au_refresh_hinode_self(inode); -+ au_dbg_verify_dinode(dentry); -+ if (!err) -+ goto out_dgen; /* success */ -+ goto out; -+ } -+ -+ /* temporary dinfo */ -+ AuDbgDentry(dentry); -+ err = -ENOMEM; -+ tmp = au_di_alloc(sb, AuLsc_DI_TMP); -+ if (unlikely(!tmp)) -+ goto out; -+ au_di_swap(tmp, dinfo); -+ /* returns the number of positive dentries */ -+ /* -+ * if current working dir is removed, it returns an error. -+ * but the dentry is legal. -+ */ -+ err = au_lkup_dentry(dentry, /*bstart*/0, /*type*/0, /*nd*/NULL); -+ AuDbgDentry(dentry); -+ au_di_swap(tmp, dinfo); -+ if (err == -ENOENT) -+ err = 0; -+ if (err >= 0) { -+ /* compare/refresh by dinfo */ -+ AuDbgDentry(dentry); -+ err = au_refresh_by_dinfo(dentry, dinfo, tmp); -+ au_dbg_verify_dinode(dentry); -+ AuTraceErr(err); -+ } -+ au_rw_write_unlock(&tmp->di_rwsem); -+ au_di_free(tmp); -+ if (unlikely(err)) -+ goto out; -+ -+out_dgen: -+ au_update_digen(dentry); -+out: -+ if (unlikely(err && !(dentry->d_flags & DCACHE_NFSFS_RENAMED))) { -+ AuIOErr("failed refreshing %.*s, %d\n", -+ AuDLNPair(dentry), err); -+ AuDbgDentry(dentry); -+ } -+ AuTraceErr(err); -+ return err; -+} -+ -+static noinline_for_stack -+int au_do_h_d_reval(struct dentry *h_dentry, struct nameidata *nd, -+ struct dentry *dentry, aufs_bindex_t bindex) -+{ -+ int err, valid; -+ int (*reval)(struct dentry *, struct nameidata *); -+ -+ err = 0; -+ reval = NULL; -+ if (h_dentry->d_op) -+ reval = h_dentry->d_op->d_revalidate; -+ if (!reval) -+ goto out; -+ -+ AuDbg("b%d\n", bindex); -+ if (au_test_fs_null_nd(h_dentry->d_sb)) -+ /* it may return tri-state */ -+ valid = reval(h_dentry, NULL); -+ else { -+ struct nameidata h_nd; -+ int locked; -+ struct dentry *parent; -+ -+ au_h_nd(&h_nd, nd); -+ parent = nd->path.dentry; -+ locked = (nd && nd->path.dentry != dentry); -+ if (locked) -+ di_read_lock_parent(parent, AuLock_IR); -+ BUG_ON(bindex > au_dbend(parent)); -+ h_nd.path.dentry = au_h_dptr(parent, bindex); -+ BUG_ON(!h_nd.path.dentry); -+ h_nd.path.mnt = au_sbr(parent->d_sb, bindex)->br_mnt; -+ path_get(&h_nd.path); -+ valid = reval(h_dentry, &h_nd); -+ path_put(&h_nd.path); -+ if (locked) -+ di_read_unlock(parent, AuLock_IR); -+ } -+ -+ if (unlikely(valid < 0)) -+ err = valid; -+ else if (!valid) -+ err = -EINVAL; -+ -+out: -+ AuTraceErr(err); -+ return err; -+} -+ -+/* todo: remove this */ -+static int h_d_revalidate(struct dentry *dentry, struct inode *inode, -+ struct nameidata *nd, int do_udba) -+{ -+ int err; -+ umode_t mode, h_mode; -+ aufs_bindex_t bindex, btail, bstart, ibs, ibe; -+ unsigned char plus, unhashed, is_root, h_plus; -+ struct inode *h_inode, *h_cached_inode; -+ struct dentry *h_dentry; -+ struct qstr *name, *h_name; -+ -+ err = 0; -+ plus = 0; -+ mode = 0; -+ ibs = -1; -+ ibe = -1; -+ unhashed = !!d_unhashed(dentry); -+ is_root = !!IS_ROOT(dentry); -+ name = &dentry->d_name; -+ -+ /* -+ * Theoretically, REVAL test should be unnecessary in case of -+ * {FS,I}NOTIFY. -+ * But {fs,i}notify doesn't fire some necessary events, -+ * IN_ATTRIB for atime/nlink/pageio -+ * IN_DELETE for NFS dentry -+ * Let's do REVAL test too. -+ */ -+ if (do_udba && inode) { -+ mode = (inode->i_mode & S_IFMT); -+ plus = (inode->i_nlink > 0); -+ ibs = au_ibstart(inode); -+ ibe = au_ibend(inode); -+ } -+ -+ bstart = au_dbstart(dentry); -+ btail = bstart; -+ if (inode && S_ISDIR(inode->i_mode)) -+ btail = au_dbtaildir(dentry); -+ for (bindex = bstart; bindex <= btail; bindex++) { -+ h_dentry = au_h_dptr(dentry, bindex); -+ if (!h_dentry) -+ continue; -+ -+ AuDbg("b%d, %.*s\n", bindex, AuDLNPair(h_dentry)); -+ h_name = &h_dentry->d_name; -+ if (unlikely(do_udba -+ && !is_root -+ && (unhashed != !!d_unhashed(h_dentry) -+ || name->len != h_name->len -+ || memcmp(name->name, h_name->name, name->len)) -+ )) { -+ AuDbg("unhash 0x%x 0x%x, %.*s %.*s\n", -+ unhashed, d_unhashed(h_dentry), -+ AuDLNPair(dentry), AuDLNPair(h_dentry)); -+ goto err; -+ } -+ -+ err = au_do_h_d_reval(h_dentry, nd, dentry, bindex); -+ if (unlikely(err)) -+ /* do not goto err, to keep the errno */ -+ break; -+ -+ /* todo: plink too? */ -+ if (!do_udba) -+ continue; -+ -+ /* UDBA tests */ -+ h_inode = h_dentry->d_inode; -+ if (unlikely(!!inode != !!h_inode)) -+ goto err; -+ -+ h_plus = plus; -+ h_mode = mode; -+ h_cached_inode = h_inode; -+ if (h_inode) { -+ h_mode = (h_inode->i_mode & S_IFMT); -+ h_plus = (h_inode->i_nlink > 0); -+ } -+ if (inode && ibs <= bindex && bindex <= ibe) -+ h_cached_inode = au_h_iptr(inode, bindex); -+ -+ if (unlikely(plus != h_plus -+ || mode != h_mode -+ || h_cached_inode != h_inode)) -+ goto err; -+ continue; -+ -+ err: -+ err = -EINVAL; -+ break; -+ } -+ -+ return err; -+} -+ -+/* todo: consolidate with do_refresh() and au_reval_for_attr() */ -+static int simple_reval_dpath(struct dentry *dentry, unsigned int sigen) -+{ -+ int err; -+ struct dentry *parent; -+ -+ if (!au_digen_test(dentry, sigen)) -+ return 0; -+ -+ parent = dget_parent(dentry); -+ di_read_lock_parent(parent, AuLock_IR); -+ AuDebugOn(au_digen_test(parent, sigen)); -+ au_dbg_verify_gen(parent, sigen); -+ err = au_refresh_dentry(dentry, parent); -+ di_read_unlock(parent, AuLock_IR); -+ dput(parent); -+ AuTraceErr(err); -+ return err; -+} -+ -+int au_reval_dpath(struct dentry *dentry, unsigned int sigen) -+{ -+ int err; -+ struct dentry *d, *parent; -+ struct inode *inode; -+ -+ if (!au_ftest_si(au_sbi(dentry->d_sb), FAILED_REFRESH_DIR)) -+ return simple_reval_dpath(dentry, sigen); -+ -+ /* slow loop, keep it simple and stupid */ -+ /* cf: au_cpup_dirs() */ -+ err = 0; -+ parent = NULL; -+ while (au_digen_test(dentry, sigen)) { -+ d = dentry; -+ while (1) { -+ dput(parent); -+ parent = dget_parent(d); -+ if (!au_digen_test(parent, sigen)) -+ break; -+ d = parent; -+ } -+ -+ inode = d->d_inode; -+ if (d != dentry) -+ di_write_lock_child2(d); -+ -+ /* someone might update our dentry while we were sleeping */ -+ if (au_digen_test(d, sigen)) { -+ /* -+ * todo: consolidate with simple_reval_dpath(), -+ * do_refresh() and au_reval_for_attr(). -+ */ -+ di_read_lock_parent(parent, AuLock_IR); -+ err = au_refresh_dentry(d, parent); -+ di_read_unlock(parent, AuLock_IR); -+ } -+ -+ if (d != dentry) -+ di_write_unlock(d); -+ dput(parent); -+ if (unlikely(err)) -+ break; -+ } -+ -+ return err; -+} -+ -+/* -+ * if valid returns 1, otherwise 0. -+ */ -+static int aufs_d_revalidate(struct dentry *dentry, struct nameidata *nd) -+{ -+ int valid, err; -+ unsigned int sigen; -+ unsigned char do_udba; -+ struct super_block *sb; -+ struct inode *inode; -+ -+ valid = 0; -+ if (unlikely(!au_di(dentry))) -+ goto out; -+ -+ valid = 1; -+ sb = dentry->d_sb; -+ inode = dentry->d_inode; -+ /* -+ * todo: very ugly -+ * i_mutex of parent dir may be held, -+ * but we should not return 'invalid' due to busy. -+ */ -+ err = aufs_read_lock(dentry, AuLock_FLUSH | AuLock_DW | AuLock_NOPLM); -+ if (unlikely(err)) { -+ valid = err; -+ AuTraceErr(err); -+ goto out; -+ } -+ if (unlikely(au_dbrange_test(dentry))) { -+ err = -EINVAL; -+ AuTraceErr(err); -+ goto out_dgrade; -+ } -+ -+ sigen = au_sigen(sb); -+ if (au_digen_test(dentry, sigen)) { -+ AuDebugOn(IS_ROOT(dentry)); -+ err = au_reval_dpath(dentry, sigen); -+ if (unlikely(err)) { -+ AuTraceErr(err); -+ goto out_dgrade; -+ } -+ } -+ di_downgrade_lock(dentry, AuLock_IR); -+ -+ err = -EINVAL; -+ if (inode && (IS_DEADDIR(inode) || !inode->i_nlink)) -+ goto out_inval; -+ -+ do_udba = !au_opt_test(au_mntflags(sb), UDBA_NONE); -+ if (do_udba && inode) { -+ aufs_bindex_t bstart = au_ibstart(inode); -+ struct inode *h_inode; -+ -+ if (bstart >= 0) { -+ h_inode = au_h_iptr(inode, bstart); -+ if (h_inode && au_test_higen(inode, h_inode)) -+ goto out_inval; -+ } -+ } -+ -+ err = h_d_revalidate(dentry, inode, nd, do_udba); -+ if (unlikely(!err && do_udba && au_dbstart(dentry) < 0)) { -+ err = -EIO; -+ AuDbg("both of real entry and whiteout found, %.*s, err %d\n", -+ AuDLNPair(dentry), err); -+ } -+ goto out_inval; -+ -+out_dgrade: -+ di_downgrade_lock(dentry, AuLock_IR); -+out_inval: -+ aufs_read_unlock(dentry, AuLock_IR); -+ AuTraceErr(err); -+ valid = !err; -+out: -+ if (!valid) { -+ AuDbg("%.*s invalid, %d\n", AuDLNPair(dentry), valid); -+ d_drop(dentry); -+ } -+ return valid; -+} -+ -+static void aufs_d_release(struct dentry *dentry) -+{ -+ if (au_di(dentry)) { -+ au_di_fin(dentry); -+ au_hn_di_reinit(dentry); -+ } -+} -+ -+const struct dentry_operations aufs_dop = { -+ .d_revalidate = aufs_d_revalidate, -+ .d_release = aufs_d_release -+}; -diff -Nur linux-2.6.36.orig/fs/aufs/dentry.h linux-2.6.36/fs/aufs/dentry.h ---- linux-2.6.36.orig/fs/aufs/dentry.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/dentry.h 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,237 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * lookup and dentry operations -+ */ -+ -+#ifndef __AUFS_DENTRY_H__ -+#define __AUFS_DENTRY_H__ -+ -+#ifdef __KERNEL__ -+ -+#include -+#include -+#include "rwsem.h" -+ -+struct au_hdentry { -+ struct dentry *hd_dentry; -+ aufs_bindex_t hd_id; -+}; -+ -+struct au_dinfo { -+ atomic_t di_generation; -+ -+ struct au_rwsem di_rwsem; -+ aufs_bindex_t di_bstart, di_bend, di_bwh, di_bdiropq; -+ struct au_hdentry *di_hdentry; -+} ____cacheline_aligned_in_smp; -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* dentry.c */ -+extern const struct dentry_operations aufs_dop; -+struct au_branch; -+struct dentry *au_lkup_one(struct qstr *name, struct dentry *h_parent, -+ struct au_branch *br, struct nameidata *nd); -+struct dentry *au_sio_lkup_one(struct qstr *name, struct dentry *parent, -+ struct au_branch *br); -+int au_h_verify(struct dentry *h_dentry, unsigned int udba, struct inode *h_dir, -+ struct dentry *h_parent, struct au_branch *br); -+ -+int au_lkup_dentry(struct dentry *dentry, aufs_bindex_t bstart, mode_t type, -+ struct nameidata *nd); -+int au_lkup_neg(struct dentry *dentry, aufs_bindex_t bindex); -+int au_refresh_dentry(struct dentry *dentry, struct dentry *parent); -+int au_reval_dpath(struct dentry *dentry, unsigned int sigen); -+ -+/* dinfo.c */ -+void au_di_init_once(void *_di); -+struct au_dinfo *au_di_alloc(struct super_block *sb, unsigned int lsc); -+void au_di_free(struct au_dinfo *dinfo); -+void au_di_swap(struct au_dinfo *a, struct au_dinfo *b); -+void au_di_cp(struct au_dinfo *dst, struct au_dinfo *src); -+int au_di_init(struct dentry *dentry); -+void au_di_fin(struct dentry *dentry); -+int au_di_realloc(struct au_dinfo *dinfo, int nbr); -+ -+void di_read_lock(struct dentry *d, int flags, unsigned int lsc); -+void di_read_unlock(struct dentry *d, int flags); -+void di_downgrade_lock(struct dentry *d, int flags); -+void di_write_lock(struct dentry *d, unsigned int lsc); -+void di_write_unlock(struct dentry *d); -+void di_write_lock2_child(struct dentry *d1, struct dentry *d2, int isdir); -+void di_write_lock2_parent(struct dentry *d1, struct dentry *d2, int isdir); -+void di_write_unlock2(struct dentry *d1, struct dentry *d2); -+ -+struct dentry *au_h_dptr(struct dentry *dentry, aufs_bindex_t bindex); -+aufs_bindex_t au_dbtail(struct dentry *dentry); -+aufs_bindex_t au_dbtaildir(struct dentry *dentry); -+ -+void au_set_h_dptr(struct dentry *dentry, aufs_bindex_t bindex, -+ struct dentry *h_dentry); -+int au_digen_test(struct dentry *dentry, unsigned int sigen); -+int au_dbrange_test(struct dentry *dentry); -+void au_update_digen(struct dentry *dentry); -+void au_update_dbrange(struct dentry *dentry, int do_put_zero); -+void au_update_dbstart(struct dentry *dentry); -+void au_update_dbend(struct dentry *dentry); -+int au_find_dbindex(struct dentry *dentry, struct dentry *h_dentry); -+ -+/* ---------------------------------------------------------------------- */ -+ -+static inline struct au_dinfo *au_di(struct dentry *dentry) -+{ -+ return dentry->d_fsdata; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* lock subclass for dinfo */ -+enum { -+ AuLsc_DI_CHILD, /* child first */ -+ AuLsc_DI_CHILD2, /* rename(2), link(2), and cpup at hnotify */ -+ AuLsc_DI_CHILD3, /* copyup dirs */ -+ AuLsc_DI_PARENT, -+ AuLsc_DI_PARENT2, -+ AuLsc_DI_PARENT3, -+ AuLsc_DI_TMP /* temp for replacing dinfo */ -+}; -+ -+/* -+ * di_read_lock_child, di_write_lock_child, -+ * di_read_lock_child2, di_write_lock_child2, -+ * di_read_lock_child3, di_write_lock_child3, -+ * di_read_lock_parent, di_write_lock_parent, -+ * di_read_lock_parent2, di_write_lock_parent2, -+ * di_read_lock_parent3, di_write_lock_parent3, -+ */ -+#define AuReadLockFunc(name, lsc) \ -+static inline void di_read_lock_##name(struct dentry *d, int flags) \ -+{ di_read_lock(d, flags, AuLsc_DI_##lsc); } -+ -+#define AuWriteLockFunc(name, lsc) \ -+static inline void di_write_lock_##name(struct dentry *d) \ -+{ di_write_lock(d, AuLsc_DI_##lsc); } -+ -+#define AuRWLockFuncs(name, lsc) \ -+ AuReadLockFunc(name, lsc) \ -+ AuWriteLockFunc(name, lsc) -+ -+AuRWLockFuncs(child, CHILD); -+AuRWLockFuncs(child2, CHILD2); -+AuRWLockFuncs(child3, CHILD3); -+AuRWLockFuncs(parent, PARENT); -+AuRWLockFuncs(parent2, PARENT2); -+AuRWLockFuncs(parent3, PARENT3); -+ -+#undef AuReadLockFunc -+#undef AuWriteLockFunc -+#undef AuRWLockFuncs -+ -+#define DiMustNoWaiters(d) AuRwMustNoWaiters(&au_di(d)->di_rwsem) -+#define DiMustAnyLock(d) AuRwMustAnyLock(&au_di(d)->di_rwsem) -+#define DiMustWriteLock(d) AuRwMustWriteLock(&au_di(d)->di_rwsem) -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* todo: memory barrier? */ -+static inline unsigned int au_digen(struct dentry *d) -+{ -+ return atomic_read(&au_di(d)->di_generation); -+} -+ -+static inline void au_h_dentry_init(struct au_hdentry *hdentry) -+{ -+ hdentry->hd_dentry = NULL; -+} -+ -+static inline void au_hdput(struct au_hdentry *hd) -+{ -+ if (hd) -+ dput(hd->hd_dentry); -+} -+ -+static inline aufs_bindex_t au_dbstart(struct dentry *dentry) -+{ -+ DiMustAnyLock(dentry); -+ return au_di(dentry)->di_bstart; -+} -+ -+static inline aufs_bindex_t au_dbend(struct dentry *dentry) -+{ -+ DiMustAnyLock(dentry); -+ return au_di(dentry)->di_bend; -+} -+ -+static inline aufs_bindex_t au_dbwh(struct dentry *dentry) -+{ -+ DiMustAnyLock(dentry); -+ return au_di(dentry)->di_bwh; -+} -+ -+static inline aufs_bindex_t au_dbdiropq(struct dentry *dentry) -+{ -+ DiMustAnyLock(dentry); -+ return au_di(dentry)->di_bdiropq; -+} -+ -+/* todo: hard/soft set? */ -+static inline void au_set_dbstart(struct dentry *dentry, aufs_bindex_t bindex) -+{ -+ DiMustWriteLock(dentry); -+ au_di(dentry)->di_bstart = bindex; -+} -+ -+static inline void au_set_dbend(struct dentry *dentry, aufs_bindex_t bindex) -+{ -+ DiMustWriteLock(dentry); -+ au_di(dentry)->di_bend = bindex; -+} -+ -+static inline void au_set_dbwh(struct dentry *dentry, aufs_bindex_t bindex) -+{ -+ DiMustWriteLock(dentry); -+ /* dbwh can be outside of bstart - bend range */ -+ au_di(dentry)->di_bwh = bindex; -+} -+ -+static inline void au_set_dbdiropq(struct dentry *dentry, aufs_bindex_t bindex) -+{ -+ DiMustWriteLock(dentry); -+ au_di(dentry)->di_bdiropq = bindex; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+#ifdef CONFIG_AUFS_HNOTIFY -+static inline void au_digen_dec(struct dentry *d) -+{ -+ atomic_dec(&au_di(d)->di_generation); -+} -+ -+static inline void au_hn_di_reinit(struct dentry *dentry) -+{ -+ dentry->d_fsdata = NULL; -+} -+#else -+AuStubVoid(au_hn_di_reinit, struct dentry *dentry __maybe_unused) -+#endif /* CONFIG_AUFS_HNOTIFY */ -+ -+#endif /* __KERNEL__ */ -+#endif /* __AUFS_DENTRY_H__ */ -diff -Nur linux-2.6.36.orig/fs/aufs/dinfo.c linux-2.6.36/fs/aufs/dinfo.c ---- linux-2.6.36.orig/fs/aufs/dinfo.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/dinfo.c 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,494 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * dentry private data -+ */ -+ -+#include "aufs.h" -+ -+void au_di_init_once(void *_dinfo) -+{ -+ struct au_dinfo *dinfo = _dinfo; -+ static struct lock_class_key aufs_di; -+ -+ au_rw_init(&dinfo->di_rwsem); -+ au_rw_class(&dinfo->di_rwsem, &aufs_di); -+} -+ -+struct au_dinfo *au_di_alloc(struct super_block *sb, unsigned int lsc) -+{ -+ struct au_dinfo *dinfo; -+ int nbr, i; -+ -+ dinfo = au_cache_alloc_dinfo(); -+ if (unlikely(!dinfo)) -+ goto out; -+ -+ nbr = au_sbend(sb) + 1; -+ if (nbr <= 0) -+ nbr = 1; -+ dinfo->di_hdentry = kcalloc(nbr, sizeof(*dinfo->di_hdentry), GFP_NOFS); -+ if (dinfo->di_hdentry) { -+ au_rw_write_lock_nested(&dinfo->di_rwsem, lsc); -+ dinfo->di_bstart = -1; -+ dinfo->di_bend = -1; -+ dinfo->di_bwh = -1; -+ dinfo->di_bdiropq = -1; -+ for (i = 0; i < nbr; i++) -+ dinfo->di_hdentry[i].hd_id = -1; -+ goto out; -+ } -+ -+ au_cache_free_dinfo(dinfo); -+ dinfo = NULL; -+ -+out: -+ return dinfo; -+} -+ -+void au_di_free(struct au_dinfo *dinfo) -+{ -+ struct au_hdentry *p; -+ aufs_bindex_t bend, bindex; -+ -+ /* dentry may not be revalidated */ -+ bindex = dinfo->di_bstart; -+ if (bindex >= 0) { -+ bend = dinfo->di_bend; -+ p = dinfo->di_hdentry + bindex; -+ while (bindex++ <= bend) -+ au_hdput(p++); -+ } -+ kfree(dinfo->di_hdentry); -+ au_cache_free_dinfo(dinfo); -+} -+ -+void au_di_swap(struct au_dinfo *a, struct au_dinfo *b) -+{ -+ struct au_hdentry *p; -+ aufs_bindex_t bi; -+ -+ AuRwMustWriteLock(&a->di_rwsem); -+ AuRwMustWriteLock(&b->di_rwsem); -+ -+#define DiSwap(v, name) \ -+ do { \ -+ v = a->di_##name; \ -+ a->di_##name = b->di_##name; \ -+ b->di_##name = v; \ -+ } while (0) -+ -+ DiSwap(p, hdentry); -+ DiSwap(bi, bstart); -+ DiSwap(bi, bend); -+ DiSwap(bi, bwh); -+ DiSwap(bi, bdiropq); -+ /* smp_mb(); */ -+ -+#undef DiSwap -+} -+ -+void au_di_cp(struct au_dinfo *dst, struct au_dinfo *src) -+{ -+ AuRwMustWriteLock(&dst->di_rwsem); -+ AuRwMustWriteLock(&src->di_rwsem); -+ -+ dst->di_bstart = src->di_bstart; -+ dst->di_bend = src->di_bend; -+ dst->di_bwh = src->di_bwh; -+ dst->di_bdiropq = src->di_bdiropq; -+ /* smp_mb(); */ -+} -+ -+int au_di_init(struct dentry *dentry) -+{ -+ int err; -+ struct super_block *sb; -+ struct au_dinfo *dinfo; -+ -+ err = 0; -+ sb = dentry->d_sb; -+ dinfo = au_di_alloc(sb, AuLsc_DI_CHILD); -+ if (dinfo) { -+ atomic_set(&dinfo->di_generation, au_sigen(sb)); -+ /* smp_mb(); */ /* atomic_set */ -+ dentry->d_op = &aufs_dop; -+ dentry->d_fsdata = dinfo; -+ } else -+ err = -ENOMEM; -+ -+ return err; -+} -+ -+void au_di_fin(struct dentry *dentry) -+{ -+ struct au_dinfo *dinfo; -+ -+ dinfo = au_di(dentry); -+ AuRwDestroy(&dinfo->di_rwsem); -+ au_di_free(dinfo); -+} -+ -+int au_di_realloc(struct au_dinfo *dinfo, int nbr) -+{ -+ int err, sz; -+ struct au_hdentry *hdp; -+ -+ AuRwMustWriteLock(&dinfo->di_rwsem); -+ -+ err = -ENOMEM; -+ sz = sizeof(*hdp) * (dinfo->di_bend + 1); -+ if (!sz) -+ sz = sizeof(*hdp); -+ hdp = au_kzrealloc(dinfo->di_hdentry, sz, sizeof(*hdp) * nbr, GFP_NOFS); -+ if (hdp) { -+ dinfo->di_hdentry = hdp; -+ err = 0; -+ } -+ -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static void do_ii_write_lock(struct inode *inode, unsigned int lsc) -+{ -+ switch (lsc) { -+ case AuLsc_DI_CHILD: -+ ii_write_lock_child(inode); -+ break; -+ case AuLsc_DI_CHILD2: -+ ii_write_lock_child2(inode); -+ break; -+ case AuLsc_DI_CHILD3: -+ ii_write_lock_child3(inode); -+ break; -+ case AuLsc_DI_PARENT: -+ ii_write_lock_parent(inode); -+ break; -+ case AuLsc_DI_PARENT2: -+ ii_write_lock_parent2(inode); -+ break; -+ case AuLsc_DI_PARENT3: -+ ii_write_lock_parent3(inode); -+ break; -+ default: -+ BUG(); -+ } -+} -+ -+static void do_ii_read_lock(struct inode *inode, unsigned int lsc) -+{ -+ switch (lsc) { -+ case AuLsc_DI_CHILD: -+ ii_read_lock_child(inode); -+ break; -+ case AuLsc_DI_CHILD2: -+ ii_read_lock_child2(inode); -+ break; -+ case AuLsc_DI_CHILD3: -+ ii_read_lock_child3(inode); -+ break; -+ case AuLsc_DI_PARENT: -+ ii_read_lock_parent(inode); -+ break; -+ case AuLsc_DI_PARENT2: -+ ii_read_lock_parent2(inode); -+ break; -+ case AuLsc_DI_PARENT3: -+ ii_read_lock_parent3(inode); -+ break; -+ default: -+ BUG(); -+ } -+} -+ -+void di_read_lock(struct dentry *d, int flags, unsigned int lsc) -+{ -+ au_rw_read_lock_nested(&au_di(d)->di_rwsem, lsc); -+ if (d->d_inode) { -+ if (au_ftest_lock(flags, IW)) -+ do_ii_write_lock(d->d_inode, lsc); -+ else if (au_ftest_lock(flags, IR)) -+ do_ii_read_lock(d->d_inode, lsc); -+ } -+} -+ -+void di_read_unlock(struct dentry *d, int flags) -+{ -+ if (d->d_inode) { -+ if (au_ftest_lock(flags, IW)) { -+ au_dbg_verify_dinode(d); -+ ii_write_unlock(d->d_inode); -+ } else if (au_ftest_lock(flags, IR)) { -+ au_dbg_verify_dinode(d); -+ ii_read_unlock(d->d_inode); -+ } -+ } -+ au_rw_read_unlock(&au_di(d)->di_rwsem); -+} -+ -+void di_downgrade_lock(struct dentry *d, int flags) -+{ -+ if (d->d_inode && au_ftest_lock(flags, IR)) -+ ii_downgrade_lock(d->d_inode); -+ au_rw_dgrade_lock(&au_di(d)->di_rwsem); -+} -+ -+void di_write_lock(struct dentry *d, unsigned int lsc) -+{ -+ au_rw_write_lock_nested(&au_di(d)->di_rwsem, lsc); -+ if (d->d_inode) -+ do_ii_write_lock(d->d_inode, lsc); -+} -+ -+void di_write_unlock(struct dentry *d) -+{ -+ au_dbg_verify_dinode(d); -+ if (d->d_inode) -+ ii_write_unlock(d->d_inode); -+ au_rw_write_unlock(&au_di(d)->di_rwsem); -+} -+ -+void di_write_lock2_child(struct dentry *d1, struct dentry *d2, int isdir) -+{ -+ AuDebugOn(d1 == d2 -+ || d1->d_inode == d2->d_inode -+ || d1->d_sb != d2->d_sb); -+ -+ if (isdir && au_test_subdir(d1, d2)) { -+ di_write_lock_child(d1); -+ di_write_lock_child2(d2); -+ } else { -+ /* there should be no races */ -+ di_write_lock_child(d2); -+ di_write_lock_child2(d1); -+ } -+} -+ -+void di_write_lock2_parent(struct dentry *d1, struct dentry *d2, int isdir) -+{ -+ AuDebugOn(d1 == d2 -+ || d1->d_inode == d2->d_inode -+ || d1->d_sb != d2->d_sb); -+ -+ if (isdir && au_test_subdir(d1, d2)) { -+ di_write_lock_parent(d1); -+ di_write_lock_parent2(d2); -+ } else { -+ /* there should be no races */ -+ di_write_lock_parent(d2); -+ di_write_lock_parent2(d1); -+ } -+} -+ -+void di_write_unlock2(struct dentry *d1, struct dentry *d2) -+{ -+ di_write_unlock(d1); -+ if (d1->d_inode == d2->d_inode) -+ au_rw_write_unlock(&au_di(d2)->di_rwsem); -+ else -+ di_write_unlock(d2); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+struct dentry *au_h_dptr(struct dentry *dentry, aufs_bindex_t bindex) -+{ -+ struct dentry *d; -+ -+ DiMustAnyLock(dentry); -+ -+ if (au_dbstart(dentry) < 0 || bindex < au_dbstart(dentry)) -+ return NULL; -+ AuDebugOn(bindex < 0); -+ d = au_di(dentry)->di_hdentry[0 + bindex].hd_dentry; -+ AuDebugOn(d && (atomic_read(&d->d_count) <= 0)); -+ return d; -+} -+ -+aufs_bindex_t au_dbtail(struct dentry *dentry) -+{ -+ aufs_bindex_t bend, bwh; -+ -+ bend = au_dbend(dentry); -+ if (0 <= bend) { -+ bwh = au_dbwh(dentry); -+ if (!bwh) -+ return bwh; -+ if (0 < bwh && bwh < bend) -+ return bwh - 1; -+ } -+ return bend; -+} -+ -+aufs_bindex_t au_dbtaildir(struct dentry *dentry) -+{ -+ aufs_bindex_t bend, bopq; -+ -+ bend = au_dbtail(dentry); -+ if (0 <= bend) { -+ bopq = au_dbdiropq(dentry); -+ if (0 <= bopq && bopq < bend) -+ bend = bopq; -+ } -+ return bend; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+void au_set_h_dptr(struct dentry *dentry, aufs_bindex_t bindex, -+ struct dentry *h_dentry) -+{ -+ struct au_hdentry *hd = au_di(dentry)->di_hdentry + bindex; -+ struct au_branch *br; -+ -+ DiMustWriteLock(dentry); -+ -+ au_hdput(hd); -+ hd->hd_dentry = h_dentry; -+ if (h_dentry) { -+ br = au_sbr(dentry->d_sb, bindex); -+ hd->hd_id = br->br_id; -+ } -+} -+ -+int au_dbrange_test(struct dentry *dentry) -+{ -+ int err; -+ aufs_bindex_t bstart, bend; -+ -+ err = 0; -+ bstart = au_dbstart(dentry); -+ bend = au_dbend(dentry); -+ if (bstart >= 0) -+ AuDebugOn(bend < 0 && bstart > bend); -+ else { -+ err = -EIO; -+ AuDebugOn(bend >= 0); -+ } -+ -+ return err; -+} -+ -+int au_digen_test(struct dentry *dentry, unsigned int sigen) -+{ -+ int err; -+ -+ err = 0; -+ if (unlikely(au_digen(dentry) != sigen -+ || au_iigen_test(dentry->d_inode, sigen))) -+ err = -EIO; -+ -+ return err; -+} -+ -+void au_update_digen(struct dentry *dentry) -+{ -+ atomic_set(&au_di(dentry)->di_generation, au_sigen(dentry->d_sb)); -+ /* smp_mb(); */ /* atomic_set */ -+} -+ -+void au_update_dbrange(struct dentry *dentry, int do_put_zero) -+{ -+ struct au_dinfo *dinfo; -+ struct dentry *h_d; -+ struct au_hdentry *hdp; -+ -+ DiMustWriteLock(dentry); -+ -+ dinfo = au_di(dentry); -+ if (!dinfo || dinfo->di_bstart < 0) -+ return; -+ -+ hdp = dinfo->di_hdentry; -+ if (do_put_zero) { -+ aufs_bindex_t bindex, bend; -+ -+ bend = dinfo->di_bend; -+ for (bindex = dinfo->di_bstart; bindex <= bend; bindex++) { -+ h_d = hdp[0 + bindex].hd_dentry; -+ if (h_d && !h_d->d_inode) -+ au_set_h_dptr(dentry, bindex, NULL); -+ } -+ } -+ -+ dinfo->di_bstart = -1; -+ while (++dinfo->di_bstart <= dinfo->di_bend) -+ if (hdp[0 + dinfo->di_bstart].hd_dentry) -+ break; -+ if (dinfo->di_bstart > dinfo->di_bend) { -+ dinfo->di_bstart = -1; -+ dinfo->di_bend = -1; -+ return; -+ } -+ -+ dinfo->di_bend++; -+ while (0 <= --dinfo->di_bend) -+ if (hdp[0 + dinfo->di_bend].hd_dentry) -+ break; -+ AuDebugOn(dinfo->di_bstart > dinfo->di_bend || dinfo->di_bend < 0); -+} -+ -+void au_update_dbstart(struct dentry *dentry) -+{ -+ aufs_bindex_t bindex, bend; -+ struct dentry *h_dentry; -+ -+ bend = au_dbend(dentry); -+ for (bindex = au_dbstart(dentry); bindex <= bend; bindex++) { -+ h_dentry = au_h_dptr(dentry, bindex); -+ if (!h_dentry) -+ continue; -+ if (h_dentry->d_inode) { -+ au_set_dbstart(dentry, bindex); -+ return; -+ } -+ au_set_h_dptr(dentry, bindex, NULL); -+ } -+} -+ -+void au_update_dbend(struct dentry *dentry) -+{ -+ aufs_bindex_t bindex, bstart; -+ struct dentry *h_dentry; -+ -+ bstart = au_dbstart(dentry); -+ for (bindex = au_dbend(dentry); bindex >= bstart; bindex--) { -+ h_dentry = au_h_dptr(dentry, bindex); -+ if (!h_dentry) -+ continue; -+ if (h_dentry->d_inode) { -+ au_set_dbend(dentry, bindex); -+ return; -+ } -+ au_set_h_dptr(dentry, bindex, NULL); -+ } -+} -+ -+int au_find_dbindex(struct dentry *dentry, struct dentry *h_dentry) -+{ -+ aufs_bindex_t bindex, bend; -+ -+ bend = au_dbend(dentry); -+ for (bindex = au_dbstart(dentry); bindex <= bend; bindex++) -+ if (au_h_dptr(dentry, bindex) == h_dentry) -+ return bindex; -+ return -1; -+} -diff -Nur linux-2.6.36.orig/fs/aufs/dir.c linux-2.6.36/fs/aufs/dir.c ---- linux-2.6.36.orig/fs/aufs/dir.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/dir.c 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,648 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * directory operations -+ */ -+ -+#include -+#include -+#include "aufs.h" -+ -+void au_add_nlink(struct inode *dir, struct inode *h_dir) -+{ -+ AuDebugOn(!S_ISDIR(dir->i_mode) || !S_ISDIR(h_dir->i_mode)); -+ -+ dir->i_nlink += h_dir->i_nlink - 2; -+ if (h_dir->i_nlink < 2) -+ dir->i_nlink += 2; -+} -+ -+void au_sub_nlink(struct inode *dir, struct inode *h_dir) -+{ -+ AuDebugOn(!S_ISDIR(dir->i_mode) || !S_ISDIR(h_dir->i_mode)); -+ -+ dir->i_nlink -= h_dir->i_nlink - 2; -+ if (h_dir->i_nlink < 2) -+ dir->i_nlink -= 2; -+} -+ -+loff_t au_dir_size(struct file *file, struct dentry *dentry) -+{ -+ loff_t sz; -+ aufs_bindex_t bindex, bend; -+ struct file *h_file; -+ struct dentry *h_dentry; -+ -+ sz = 0; -+ if (file) { -+ AuDebugOn(!file->f_dentry); -+ AuDebugOn(!file->f_dentry->d_inode); -+ AuDebugOn(!S_ISDIR(file->f_dentry->d_inode->i_mode)); -+ -+ bend = au_fbend_dir(file); -+ for (bindex = au_fbstart(file); -+ bindex <= bend && sz < KMALLOC_MAX_SIZE; -+ bindex++) { -+ h_file = au_hf_dir(file, bindex); -+ if (h_file -+ && h_file->f_dentry -+ && h_file->f_dentry->d_inode) -+ sz += i_size_read(h_file->f_dentry->d_inode); -+ } -+ } else { -+ AuDebugOn(!dentry); -+ AuDebugOn(!dentry->d_inode); -+ AuDebugOn(!S_ISDIR(dentry->d_inode->i_mode)); -+ -+ bend = au_dbtaildir(dentry); -+ for (bindex = au_dbstart(dentry); -+ bindex <= bend && sz < KMALLOC_MAX_SIZE; -+ bindex++) { -+ h_dentry = au_h_dptr(dentry, bindex); -+ if (h_dentry && h_dentry->d_inode) -+ sz += i_size_read(h_dentry->d_inode); -+ } -+ } -+ if (sz < KMALLOC_MAX_SIZE) -+ sz = roundup_pow_of_two(sz); -+ if (sz > KMALLOC_MAX_SIZE) -+ sz = KMALLOC_MAX_SIZE; -+ else if (sz < NAME_MAX) { -+ BUILD_BUG_ON(AUFS_RDBLK_DEF < NAME_MAX); -+ sz = AUFS_RDBLK_DEF; -+ } -+ return sz; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int reopen_dir(struct file *file) -+{ -+ int err; -+ unsigned int flags; -+ aufs_bindex_t bindex, btail, bstart; -+ struct dentry *dentry, *h_dentry; -+ struct file *h_file; -+ -+ /* open all lower dirs */ -+ dentry = file->f_dentry; -+ bstart = au_dbstart(dentry); -+ for (bindex = au_fbstart(file); bindex < bstart; bindex++) -+ au_set_h_fptr(file, bindex, NULL); -+ au_set_fbstart(file, bstart); -+ -+ btail = au_dbtaildir(dentry); -+ for (bindex = au_fbend_dir(file); btail < bindex; bindex--) -+ au_set_h_fptr(file, bindex, NULL); -+ au_set_fbend_dir(file, btail); -+ -+ flags = vfsub_file_flags(file); -+ for (bindex = bstart; bindex <= btail; bindex++) { -+ h_dentry = au_h_dptr(dentry, bindex); -+ if (!h_dentry) -+ continue; -+ h_file = au_hf_dir(file, bindex); -+ if (h_file) -+ continue; -+ -+ h_file = au_h_open(dentry, bindex, flags, file); -+ err = PTR_ERR(h_file); -+ if (IS_ERR(h_file)) -+ goto out; /* close all? */ -+ au_set_h_fptr(file, bindex, h_file); -+ } -+ au_update_figen(file); -+ /* todo: necessary? */ -+ /* file->f_ra = h_file->f_ra; */ -+ err = 0; -+ -+out: -+ return err; -+} -+ -+static int do_open_dir(struct file *file, int flags) -+{ -+ int err; -+ aufs_bindex_t bindex, btail; -+ struct dentry *dentry, *h_dentry; -+ struct file *h_file; -+ -+ FiMustWriteLock(file); -+ -+ dentry = file->f_dentry; -+ err = au_alive_dir(dentry); -+ if (unlikely(err)) -+ goto out; -+ -+ file->f_version = dentry->d_inode->i_version; -+ bindex = au_dbstart(dentry); -+ au_set_fbstart(file, bindex); -+ btail = au_dbtaildir(dentry); -+ au_set_fbend_dir(file, btail); -+ for (; !err && bindex <= btail; bindex++) { -+ h_dentry = au_h_dptr(dentry, bindex); -+ if (!h_dentry) -+ continue; -+ -+ h_file = au_h_open(dentry, bindex, flags, file); -+ if (IS_ERR(h_file)) { -+ err = PTR_ERR(h_file); -+ break; -+ } -+ au_set_h_fptr(file, bindex, h_file); -+ } -+ au_update_figen(file); -+ /* todo: necessary? */ -+ /* file->f_ra = h_file->f_ra; */ -+ if (!err) -+ return 0; /* success */ -+ -+ /* close all */ -+ for (bindex = au_fbstart(file); bindex <= btail; bindex++) -+ au_set_h_fptr(file, bindex, NULL); -+ au_set_fbstart(file, -1); -+ au_set_fbend_dir(file, -1); -+ -+out: -+ return err; -+} -+ -+static int aufs_open_dir(struct inode *inode __maybe_unused, -+ struct file *file) -+{ -+ int err; -+ struct super_block *sb; -+ struct au_fidir *fidir; -+ -+ err = -ENOMEM; -+ sb = file->f_dentry->d_sb; -+ si_read_lock(sb, AuLock_FLUSH); -+ fidir = au_fidir_alloc(sb); -+ if (fidir) { -+ err = au_do_open(file, do_open_dir, fidir); -+ if (unlikely(err)) -+ kfree(fidir); -+ } -+ si_read_unlock(sb); -+ return err; -+} -+ -+static int aufs_release_dir(struct inode *inode __maybe_unused, -+ struct file *file) -+{ -+ struct au_vdir *vdir_cache; -+ struct super_block *sb; -+ struct au_finfo *finfo; -+ struct au_fidir *fidir; -+ aufs_bindex_t bindex, bend; -+ -+ sb = file->f_dentry->d_sb; -+ finfo = au_fi(file); -+ fidir = finfo->fi_hdir; -+ if (fidir) { -+ /* remove me from sb->s_files */ -+ file_sb_list_del(file); -+ -+ vdir_cache = fidir->fd_vdir_cache; /* lock-free */ -+ if (vdir_cache) -+ au_vdir_free(vdir_cache); -+ -+ bindex = finfo->fi_btop; -+ if (bindex >= 0) { -+ /* -+ * calls fput() instead of filp_close(), -+ * since no dnotify or lock for the lower file. -+ */ -+ bend = fidir->fd_bbot; -+ for (; bindex <= bend; bindex++) -+ au_set_h_fptr(file, bindex, NULL); -+ } -+ kfree(fidir); -+ finfo->fi_hdir = NULL; -+ } -+ au_finfo_fin(file); -+ return 0; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int au_do_flush_dir(struct file *file, fl_owner_t id) -+{ -+ int err; -+ aufs_bindex_t bindex, bend; -+ struct file *h_file; -+ -+ err = 0; -+ bend = au_fbend_dir(file); -+ for (bindex = au_fbstart(file); !err && bindex <= bend; bindex++) { -+ h_file = au_hf_dir(file, bindex); -+ if (h_file) -+ err = vfsub_flush(h_file, id); -+ } -+ return err; -+} -+ -+static int aufs_flush_dir(struct file *file, fl_owner_t id) -+{ -+ return au_do_flush(file, id, au_do_flush_dir); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int au_do_fsync_dir_no_file(struct dentry *dentry, int datasync) -+{ -+ int err; -+ aufs_bindex_t bend, bindex; -+ struct inode *inode; -+ struct super_block *sb; -+ -+ err = 0; -+ sb = dentry->d_sb; -+ inode = dentry->d_inode; -+ IMustLock(inode); -+ bend = au_dbend(dentry); -+ for (bindex = au_dbstart(dentry); !err && bindex <= bend; bindex++) { -+ struct path h_path; -+ struct inode *h_inode; -+ -+ if (au_test_ro(sb, bindex, inode)) -+ continue; -+ h_path.dentry = au_h_dptr(dentry, bindex); -+ if (!h_path.dentry) -+ continue; -+ h_inode = h_path.dentry->d_inode; -+ if (!h_inode) -+ continue; -+ -+ /* no mnt_want_write() */ -+ /* cf. fs/nsfd/vfs.c and fs/nfsd/nfs4recover.c */ -+ /* todo: inotiry fired? */ -+ h_path.mnt = au_sbr_mnt(sb, bindex); -+ mutex_lock(&h_inode->i_mutex); -+ err = filemap_fdatawrite(h_inode->i_mapping); -+ AuDebugOn(!h_inode->i_fop); -+ if (!err && h_inode->i_fop->fsync) -+ err = h_inode->i_fop->fsync(NULL, datasync); -+ if (!err) -+ err = filemap_fdatawrite(h_inode->i_mapping); -+ if (!err) -+ vfsub_update_h_iattr(&h_path, /*did*/NULL); /*ignore*/ -+ mutex_unlock(&h_inode->i_mutex); -+ } -+ -+ return err; -+} -+ -+static int au_do_fsync_dir(struct file *file, int datasync) -+{ -+ int err; -+ aufs_bindex_t bend, bindex; -+ struct file *h_file; -+ struct super_block *sb; -+ struct inode *inode; -+ struct mutex *h_mtx; -+ -+ err = au_reval_and_lock_fdi(file, reopen_dir, /*wlock*/1); -+ if (unlikely(err)) -+ goto out; -+ -+ sb = file->f_dentry->d_sb; -+ inode = file->f_dentry->d_inode; -+ bend = au_fbend_dir(file); -+ for (bindex = au_fbstart(file); !err && bindex <= bend; bindex++) { -+ h_file = au_hf_dir(file, bindex); -+ if (!h_file || au_test_ro(sb, bindex, inode)) -+ continue; -+ -+ err = vfs_fsync(h_file, datasync); -+ if (!err) { -+ h_mtx = &h_file->f_dentry->d_inode->i_mutex; -+ mutex_lock(h_mtx); -+ vfsub_update_h_iattr(&h_file->f_path, /*did*/NULL); -+ /*ignore*/ -+ mutex_unlock(h_mtx); -+ } -+ } -+ -+out: -+ return err; -+} -+ -+/* -+ * @file may be NULL -+ */ -+static int aufs_fsync_dir(struct file *file, int datasync) -+{ -+ int err; -+ struct dentry *dentry; -+ struct super_block *sb; -+ -+ dentry = file->f_dentry; -+ IMustLock(dentry->d_inode); -+ -+ err = 0; -+ sb = dentry->d_sb; -+ si_noflush_read_lock(sb); -+ if (file) -+ err = au_do_fsync_dir(file, datasync); -+ else { -+ di_write_lock_child(dentry); -+ err = au_do_fsync_dir_no_file(dentry, datasync); -+ } -+ au_cpup_attr_timesizes(dentry->d_inode); -+ di_write_unlock(dentry); -+ if (file) -+ fi_write_unlock(file); -+ -+ si_read_unlock(sb); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int aufs_readdir(struct file *file, void *dirent, filldir_t filldir) -+{ -+ int err; -+ struct dentry *dentry; -+ struct inode *inode; -+ struct super_block *sb; -+ -+ dentry = file->f_dentry; -+ inode = dentry->d_inode; -+ IMustLock(inode); -+ -+ sb = dentry->d_sb; -+ si_read_lock(sb, AuLock_FLUSH); -+ err = au_reval_and_lock_fdi(file, reopen_dir, /*wlock*/1); -+ if (unlikely(err)) -+ goto out; -+ err = au_alive_dir(dentry); -+ if (!err) -+ err = au_vdir_init(file); -+ di_downgrade_lock(dentry, AuLock_IR); -+ if (unlikely(err)) -+ goto out_unlock; -+ -+ if (!au_test_nfsd()) { -+ err = au_vdir_fill_de(file, dirent, filldir); -+ fsstack_copy_attr_atime(inode, -+ au_h_iptr(inode, au_ibstart(inode))); -+ } else { -+ /* -+ * nfsd filldir may call lookup_one_len(), vfs_getattr(), -+ * encode_fh() and others. -+ */ -+ struct inode *h_inode = au_h_iptr(inode, au_ibstart(inode)); -+ -+ di_read_unlock(dentry, AuLock_IR); -+ si_read_unlock(sb); -+ err = au_vdir_fill_de(file, dirent, filldir); -+ fsstack_copy_attr_atime(inode, h_inode); -+ fi_write_unlock(file); -+ -+ AuTraceErr(err); -+ return err; -+ } -+ -+out_unlock: -+ di_read_unlock(dentry, AuLock_IR); -+ fi_write_unlock(file); -+out: -+ si_read_unlock(sb); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+#define AuTestEmpty_WHONLY 1 -+#define AuTestEmpty_CALLED (1 << 1) -+#define AuTestEmpty_SHWH (1 << 2) -+#define au_ftest_testempty(flags, name) ((flags) & AuTestEmpty_##name) -+#define au_fset_testempty(flags, name) \ -+ do { (flags) |= AuTestEmpty_##name; } while (0) -+#define au_fclr_testempty(flags, name) \ -+ do { (flags) &= ~AuTestEmpty_##name; } while (0) -+ -+#ifndef CONFIG_AUFS_SHWH -+#undef AuTestEmpty_SHWH -+#define AuTestEmpty_SHWH 0 -+#endif -+ -+struct test_empty_arg { -+ struct au_nhash *whlist; -+ unsigned int flags; -+ int err; -+ aufs_bindex_t bindex; -+}; -+ -+static int test_empty_cb(void *__arg, const char *__name, int namelen, -+ loff_t offset __maybe_unused, u64 ino, -+ unsigned int d_type) -+{ -+ struct test_empty_arg *arg = __arg; -+ char *name = (void *)__name; -+ -+ arg->err = 0; -+ au_fset_testempty(arg->flags, CALLED); -+ /* smp_mb(); */ -+ if (name[0] == '.' -+ && (namelen == 1 || (name[1] == '.' && namelen == 2))) -+ goto out; /* success */ -+ -+ if (namelen <= AUFS_WH_PFX_LEN -+ || memcmp(name, AUFS_WH_PFX, AUFS_WH_PFX_LEN)) { -+ if (au_ftest_testempty(arg->flags, WHONLY) -+ && !au_nhash_test_known_wh(arg->whlist, name, namelen)) -+ arg->err = -ENOTEMPTY; -+ goto out; -+ } -+ -+ name += AUFS_WH_PFX_LEN; -+ namelen -= AUFS_WH_PFX_LEN; -+ if (!au_nhash_test_known_wh(arg->whlist, name, namelen)) -+ arg->err = au_nhash_append_wh -+ (arg->whlist, name, namelen, ino, d_type, arg->bindex, -+ au_ftest_testempty(arg->flags, SHWH)); -+ -+out: -+ /* smp_mb(); */ -+ AuTraceErr(arg->err); -+ return arg->err; -+} -+ -+static int do_test_empty(struct dentry *dentry, struct test_empty_arg *arg) -+{ -+ int err; -+ struct file *h_file; -+ -+ h_file = au_h_open(dentry, arg->bindex, -+ O_RDONLY | O_NONBLOCK | O_DIRECTORY | O_LARGEFILE, -+ /*file*/NULL); -+ err = PTR_ERR(h_file); -+ if (IS_ERR(h_file)) -+ goto out; -+ -+ err = 0; -+ if (!au_opt_test(au_mntflags(dentry->d_sb), UDBA_NONE) -+ && !h_file->f_dentry->d_inode->i_nlink) -+ goto out_put; -+ -+ do { -+ arg->err = 0; -+ au_fclr_testempty(arg->flags, CALLED); -+ /* smp_mb(); */ -+ err = vfsub_readdir(h_file, test_empty_cb, arg); -+ if (err >= 0) -+ err = arg->err; -+ } while (!err && au_ftest_testempty(arg->flags, CALLED)); -+ -+out_put: -+ fput(h_file); -+ au_sbr_put(dentry->d_sb, arg->bindex); -+out: -+ return err; -+} -+ -+struct do_test_empty_args { -+ int *errp; -+ struct dentry *dentry; -+ struct test_empty_arg *arg; -+}; -+ -+static void call_do_test_empty(void *args) -+{ -+ struct do_test_empty_args *a = args; -+ *a->errp = do_test_empty(a->dentry, a->arg); -+} -+ -+static int sio_test_empty(struct dentry *dentry, struct test_empty_arg *arg) -+{ -+ int err, wkq_err; -+ struct dentry *h_dentry; -+ struct inode *h_inode; -+ -+ h_dentry = au_h_dptr(dentry, arg->bindex); -+ h_inode = h_dentry->d_inode; -+ mutex_lock_nested(&h_inode->i_mutex, AuLsc_I_CHILD); -+ err = au_test_h_perm_sio(h_inode, MAY_EXEC | MAY_READ); -+ mutex_unlock(&h_inode->i_mutex); -+ if (!err) -+ err = do_test_empty(dentry, arg); -+ else { -+ struct do_test_empty_args args = { -+ .errp = &err, -+ .dentry = dentry, -+ .arg = arg -+ }; -+ unsigned int flags = arg->flags; -+ -+ wkq_err = au_wkq_wait(call_do_test_empty, &args); -+ if (unlikely(wkq_err)) -+ err = wkq_err; -+ arg->flags = flags; -+ } -+ -+ return err; -+} -+ -+int au_test_empty_lower(struct dentry *dentry) -+{ -+ int err; -+ unsigned int rdhash; -+ aufs_bindex_t bindex, bstart, btail; -+ struct au_nhash whlist; -+ struct test_empty_arg arg; -+ -+ SiMustAnyLock(dentry->d_sb); -+ -+ rdhash = au_sbi(dentry->d_sb)->si_rdhash; -+ if (!rdhash) -+ rdhash = au_rdhash_est(au_dir_size(/*file*/NULL, dentry)); -+ err = au_nhash_alloc(&whlist, rdhash, GFP_NOFS); -+ if (unlikely(err)) -+ goto out; -+ -+ arg.flags = 0; -+ arg.whlist = &whlist; -+ bstart = au_dbstart(dentry); -+ if (au_opt_test(au_mntflags(dentry->d_sb), SHWH)) -+ au_fset_testempty(arg.flags, SHWH); -+ arg.bindex = bstart; -+ err = do_test_empty(dentry, &arg); -+ if (unlikely(err)) -+ goto out_whlist; -+ -+ au_fset_testempty(arg.flags, WHONLY); -+ btail = au_dbtaildir(dentry); -+ for (bindex = bstart + 1; !err && bindex <= btail; bindex++) { -+ struct dentry *h_dentry; -+ -+ h_dentry = au_h_dptr(dentry, bindex); -+ if (h_dentry && h_dentry->d_inode) { -+ arg.bindex = bindex; -+ err = do_test_empty(dentry, &arg); -+ } -+ } -+ -+out_whlist: -+ au_nhash_wh_free(&whlist); -+out: -+ return err; -+} -+ -+int au_test_empty(struct dentry *dentry, struct au_nhash *whlist) -+{ -+ int err; -+ struct test_empty_arg arg; -+ aufs_bindex_t bindex, btail; -+ -+ err = 0; -+ arg.whlist = whlist; -+ arg.flags = AuTestEmpty_WHONLY; -+ if (au_opt_test(au_mntflags(dentry->d_sb), SHWH)) -+ au_fset_testempty(arg.flags, SHWH); -+ btail = au_dbtaildir(dentry); -+ for (bindex = au_dbstart(dentry); !err && bindex <= btail; bindex++) { -+ struct dentry *h_dentry; -+ -+ h_dentry = au_h_dptr(dentry, bindex); -+ if (h_dentry && h_dentry->d_inode) { -+ arg.bindex = bindex; -+ err = sio_test_empty(dentry, &arg); -+ } -+ } -+ -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+const struct file_operations aufs_dir_fop = { -+ .owner = THIS_MODULE, -+ .read = generic_read_dir, -+ .readdir = aufs_readdir, -+ .unlocked_ioctl = aufs_ioctl_dir, -+#ifdef CONFIG_COMPAT -+ .compat_ioctl = aufs_compat_ioctl_dir, -+#endif -+ .open = aufs_open_dir, -+ .release = aufs_release_dir, -+ .flush = aufs_flush_dir, -+ .fsync = aufs_fsync_dir -+}; -diff -Nur linux-2.6.36.orig/fs/aufs/dir.h linux-2.6.36/fs/aufs/dir.h ---- linux-2.6.36.orig/fs/aufs/dir.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/dir.h 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,138 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * directory operations -+ */ -+ -+#ifndef __AUFS_DIR_H__ -+#define __AUFS_DIR_H__ -+ -+#ifdef __KERNEL__ -+ -+#include -+#include -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* need to be faster and smaller */ -+ -+struct au_nhash { -+ unsigned int nh_num; -+ struct hlist_head *nh_head; -+}; -+ -+struct au_vdir_destr { -+ unsigned char len; -+ unsigned char name[0]; -+} __packed; -+ -+struct au_vdir_dehstr { -+ struct hlist_node hash; -+ struct au_vdir_destr *str; -+} ____cacheline_aligned_in_smp; -+ -+struct au_vdir_de { -+ ino_t de_ino; -+ unsigned char de_type; -+ /* caution: packed */ -+ struct au_vdir_destr de_str; -+} __packed; -+ -+struct au_vdir_wh { -+ struct hlist_node wh_hash; -+#ifdef CONFIG_AUFS_SHWH -+ ino_t wh_ino; -+ aufs_bindex_t wh_bindex; -+ unsigned char wh_type; -+#else -+ aufs_bindex_t wh_bindex; -+#endif -+ /* caution: packed */ -+ struct au_vdir_destr wh_str; -+} __packed; -+ -+union au_vdir_deblk_p { -+ unsigned char *deblk; -+ struct au_vdir_de *de; -+}; -+ -+struct au_vdir { -+ unsigned char **vd_deblk; -+ unsigned long vd_nblk; -+ struct { -+ unsigned long ul; -+ union au_vdir_deblk_p p; -+ } vd_last; -+ -+ unsigned long vd_version; -+ unsigned int vd_deblk_sz; -+ unsigned long vd_jiffy; -+} ____cacheline_aligned_in_smp; -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* dir.c */ -+extern const struct file_operations aufs_dir_fop; -+void au_add_nlink(struct inode *dir, struct inode *h_dir); -+void au_sub_nlink(struct inode *dir, struct inode *h_dir); -+loff_t au_dir_size(struct file *file, struct dentry *dentry); -+int au_test_empty_lower(struct dentry *dentry); -+int au_test_empty(struct dentry *dentry, struct au_nhash *whlist); -+ -+/* vdir.c */ -+unsigned int au_rdhash_est(loff_t sz); -+int au_nhash_alloc(struct au_nhash *nhash, unsigned int num_hash, gfp_t gfp); -+void au_nhash_wh_free(struct au_nhash *whlist); -+int au_nhash_test_longer_wh(struct au_nhash *whlist, aufs_bindex_t btgt, -+ int limit); -+int au_nhash_test_known_wh(struct au_nhash *whlist, char *name, int nlen); -+int au_nhash_append_wh(struct au_nhash *whlist, char *name, int nlen, ino_t ino, -+ unsigned int d_type, aufs_bindex_t bindex, -+ unsigned char shwh); -+void au_vdir_free(struct au_vdir *vdir); -+int au_vdir_init(struct file *file); -+int au_vdir_fill_de(struct file *file, void *dirent, filldir_t filldir); -+ -+/* ioctl.c */ -+long aufs_ioctl_dir(struct file *file, unsigned int cmd, unsigned long arg); -+ -+#ifdef CONFIG_AUFS_RDU -+/* rdu.c */ -+long au_rdu_ioctl(struct file *file, unsigned int cmd, unsigned long arg); -+#ifdef CONFIG_COMPAT -+long au_rdu_compat_ioctl(struct file *file, unsigned int cmd, -+ unsigned long arg); -+#endif -+#else -+static inline long au_rdu_ioctl(struct file *file, unsigned int cmd, -+ unsigned long arg) -+{ -+ return -EINVAL; -+} -+#ifdef CONFIG_COMPAT -+static inline long au_rdu_compat_ioctl(struct file *file, unsigned int cmd, -+ unsigned long arg) -+{ -+ return -EINVAL; -+} -+#endif -+#endif -+ -+#endif /* __KERNEL__ */ -+#endif /* __AUFS_DIR_H__ */ -diff -Nur linux-2.6.36.orig/fs/aufs/dynop.c linux-2.6.36/fs/aufs/dynop.c ---- linux-2.6.36.orig/fs/aufs/dynop.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/dynop.c 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,425 @@ -+/* -+ * Copyright (C) 2010-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * dynamically customizable operations for regular files -+ */ -+ -+#include "aufs.h" -+ -+#define DyPrSym(key) AuDbgSym(key->dk_op.dy_hop) -+ -+/* -+ * How large will these lists be? -+ * Usually just a few elements, 20-30 at most for each, I guess. -+ */ -+static struct au_splhead dynop[AuDyLast]; -+ -+static struct au_dykey *dy_gfind_get(struct au_splhead *spl, const void *h_op) -+{ -+ struct au_dykey *key, *tmp; -+ struct list_head *head; -+ -+ key = NULL; -+ head = &spl->head; -+ rcu_read_lock(); -+ list_for_each_entry_rcu(tmp, head, dk_list) -+ if (tmp->dk_op.dy_hop == h_op) { -+ key = tmp; -+ kref_get(&key->dk_kref); -+ break; -+ } -+ rcu_read_unlock(); -+ -+ return key; -+} -+ -+static struct au_dykey *dy_bradd(struct au_branch *br, struct au_dykey *key) -+{ -+ struct au_dykey **k, *found; -+ const void *h_op = key->dk_op.dy_hop; -+ int i; -+ -+ found = NULL; -+ k = br->br_dykey; -+ for (i = 0; i < AuBrDynOp; i++) -+ if (k[i]) { -+ if (k[i]->dk_op.dy_hop == h_op) { -+ found = k[i]; -+ break; -+ } -+ } else -+ break; -+ if (!found) { -+ spin_lock(&br->br_dykey_lock); -+ for (; i < AuBrDynOp; i++) -+ if (k[i]) { -+ if (k[i]->dk_op.dy_hop == h_op) { -+ found = k[i]; -+ break; -+ } -+ } else { -+ k[i] = key; -+ break; -+ } -+ spin_unlock(&br->br_dykey_lock); -+ BUG_ON(i == AuBrDynOp); /* expand the array */ -+ } -+ -+ return found; -+} -+ -+/* kref_get() if @key is already added */ -+static struct au_dykey *dy_gadd(struct au_splhead *spl, struct au_dykey *key) -+{ -+ struct au_dykey *tmp, *found; -+ struct list_head *head; -+ const void *h_op = key->dk_op.dy_hop; -+ -+ found = NULL; -+ head = &spl->head; -+ spin_lock(&spl->spin); -+ list_for_each_entry(tmp, head, dk_list) -+ if (tmp->dk_op.dy_hop == h_op) { -+ kref_get(&tmp->dk_kref); -+ found = tmp; -+ break; -+ } -+ if (!found) -+ list_add_rcu(&key->dk_list, head); -+ spin_unlock(&spl->spin); -+ -+ if (!found) -+ DyPrSym(key); -+ return found; -+} -+ -+static void dy_free_rcu(struct rcu_head *rcu) -+{ -+ struct au_dykey *key; -+ -+ key = container_of(rcu, struct au_dykey, dk_rcu); -+ DyPrSym(key); -+ kfree(key); -+} -+ -+static void dy_free(struct kref *kref) -+{ -+ struct au_dykey *key; -+ struct au_splhead *spl; -+ -+ key = container_of(kref, struct au_dykey, dk_kref); -+ spl = dynop + key->dk_op.dy_type; -+ au_spl_del_rcu(&key->dk_list, spl); -+ call_rcu(&key->dk_rcu, dy_free_rcu); -+} -+ -+void au_dy_put(struct au_dykey *key) -+{ -+ kref_put(&key->dk_kref, dy_free); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+#define DyDbgSize(cnt, op) AuDebugOn(cnt != sizeof(op)/sizeof(void *)) -+ -+#ifdef CONFIG_AUFS_DEBUG -+#define DyDbgDeclare(cnt) unsigned int cnt = 0 -+#define DyDbgInc(cnt) do { cnt++; } while (0) -+#else -+#define DyDbgDeclare(cnt) do {} while (0) -+#define DyDbgInc(cnt) do {} while (0) -+#endif -+ -+#define DySet(func, dst, src, h_op, h_sb) do { \ -+ DyDbgInc(cnt); \ -+ if (h_op->func) { \ -+ if (src.func) \ -+ dst.func = src.func; \ -+ else \ -+ AuDbg("%s %s\n", au_sbtype(h_sb), #func); \ -+ } \ -+} while (0) -+ -+#define DySetForce(func, dst, src) do { \ -+ AuDebugOn(!src.func); \ -+ DyDbgInc(cnt); \ -+ dst.func = src.func; \ -+} while (0) -+ -+#define DySetAop(func) \ -+ DySet(func, dyaop->da_op, aufs_aop, h_aop, h_sb) -+#define DySetAopForce(func) \ -+ DySetForce(func, dyaop->da_op, aufs_aop) -+ -+static void dy_aop(struct au_dykey *key, const void *h_op, -+ struct super_block *h_sb __maybe_unused) -+{ -+ struct au_dyaop *dyaop = (void *)key; -+ const struct address_space_operations *h_aop = h_op; -+ DyDbgDeclare(cnt); -+ -+ AuDbg("%s\n", au_sbtype(h_sb)); -+ -+ DySetAop(writepage); -+ DySetAopForce(readpage); /* force */ -+ DySetAop(sync_page); -+ DySetAop(writepages); -+ DySetAop(set_page_dirty); -+ DySetAop(readpages); -+ DySetAop(write_begin); -+ DySetAop(write_end); -+ DySetAop(bmap); -+ DySetAop(invalidatepage); -+ DySetAop(releasepage); -+ /* these two will be changed according to an aufs mount option */ -+ DySetAop(direct_IO); -+ DySetAop(get_xip_mem); -+ DySetAop(migratepage); -+ DySetAop(launder_page); -+ DySetAop(is_partially_uptodate); -+ DySetAop(error_remove_page); -+ -+ DyDbgSize(cnt, *h_aop); -+ dyaop->da_get_xip_mem = h_aop->get_xip_mem; -+} -+ -+#define DySetVmop(func) \ -+ DySet(func, dyvmop->dv_op, aufs_vm_ops, h_vmop, h_sb) -+#define DySetVmopForce(func) \ -+ DySetForce(func, dyvmop->dv_op, aufs_vm_ops) -+ -+static void dy_vmop(struct au_dykey *key, const void *h_op, -+ struct super_block *h_sb __maybe_unused) -+{ -+ struct au_dyvmop *dyvmop = (void *)key; -+ const struct vm_operations_struct *h_vmop = h_op; -+ DyDbgDeclare(cnt); -+ -+ AuDbg("%s\n", au_sbtype(h_sb)); -+ -+ DySetVmop(open); -+ DySetVmop(close); -+ DySetVmop(fault); -+ DySetVmop(page_mkwrite); -+ DySetVmop(access); -+#ifdef CONFIG_NUMA -+ DySetVmop(set_policy); -+ DySetVmop(get_policy); -+ DySetVmop(migrate); -+#endif -+ -+ DyDbgSize(cnt, *h_vmop); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static void dy_bug(struct kref *kref) -+{ -+ BUG(); -+} -+ -+static struct au_dykey *dy_get(struct au_dynop *op, struct au_branch *br) -+{ -+ struct au_dykey *key, *old; -+ struct au_splhead *spl; -+ struct op { -+ unsigned int sz; -+ void (*set)(struct au_dykey *key, const void *h_op, -+ struct super_block *h_sb __maybe_unused); -+ }; -+ static const struct op a[] = { -+ [AuDy_AOP] = { -+ .sz = sizeof(struct au_dyaop), -+ .set = dy_aop -+ }, -+ [AuDy_VMOP] = { -+ .sz = sizeof(struct au_dyvmop), -+ .set = dy_vmop -+ } -+ }; -+ const struct op *p; -+ -+ spl = dynop + op->dy_type; -+ key = dy_gfind_get(spl, op->dy_hop); -+ if (key) -+ goto out_add; /* success */ -+ -+ p = a + op->dy_type; -+ key = kzalloc(p->sz, GFP_NOFS); -+ if (unlikely(!key)) { -+ key = ERR_PTR(-ENOMEM); -+ goto out; -+ } -+ -+ key->dk_op.dy_hop = op->dy_hop; -+ kref_init(&key->dk_kref); -+ p->set(key, op->dy_hop, br->br_mnt->mnt_sb); -+ old = dy_gadd(spl, key); -+ if (old) { -+ kfree(key); -+ key = old; -+ } -+ -+out_add: -+ old = dy_bradd(br, key); -+ if (old) -+ /* its ref-count should never be zero here */ -+ kref_put(&key->dk_kref, dy_bug); -+out: -+ return key; -+} -+ -+/* ---------------------------------------------------------------------- */ -+/* -+ * Aufs prohibits O_DIRECT by defaut even if the branch supports it. -+ * This behaviour is neccessary to return an error from open(O_DIRECT) instead -+ * of the succeeding I/O. The dio mount option enables O_DIRECT and makes -+ * open(O_DIRECT) always succeed, but the succeeding I/O may return an error. -+ * See the aufs manual in detail. -+ * -+ * To keep this behaviour, aufs has to set NULL to ->get_xip_mem too, and the -+ * performance of fadvise() and madvise() may be affected. -+ */ -+static void dy_adx(struct au_dyaop *dyaop, int do_dx) -+{ -+ if (!do_dx) { -+ dyaop->da_op.direct_IO = NULL; -+ dyaop->da_op.get_xip_mem = NULL; -+ } else { -+ dyaop->da_op.direct_IO = aufs_aop.direct_IO; -+ dyaop->da_op.get_xip_mem = aufs_aop.get_xip_mem; -+ if (!dyaop->da_get_xip_mem) -+ dyaop->da_op.get_xip_mem = NULL; -+ } -+} -+ -+static struct au_dyaop *dy_aget(struct au_branch *br, -+ const struct address_space_operations *h_aop, -+ int do_dx) -+{ -+ struct au_dyaop *dyaop; -+ struct au_dynop op; -+ -+ op.dy_type = AuDy_AOP; -+ op.dy_haop = h_aop; -+ dyaop = (void *)dy_get(&op, br); -+ if (IS_ERR(dyaop)) -+ goto out; -+ dy_adx(dyaop, do_dx); -+ -+out: -+ return dyaop; -+} -+ -+int au_dy_iaop(struct inode *inode, aufs_bindex_t bindex, -+ struct inode *h_inode) -+{ -+ int err, do_dx; -+ struct super_block *sb; -+ struct au_branch *br; -+ struct au_dyaop *dyaop; -+ -+ AuDebugOn(!S_ISREG(h_inode->i_mode)); -+ IiMustWriteLock(inode); -+ -+ sb = inode->i_sb; -+ br = au_sbr(sb, bindex); -+ do_dx = !!au_opt_test(au_mntflags(sb), DIO); -+ dyaop = dy_aget(br, h_inode->i_mapping->a_ops, do_dx); -+ err = PTR_ERR(dyaop); -+ if (IS_ERR(dyaop)) -+ /* unnecessary to call dy_fput() */ -+ goto out; -+ -+ err = 0; -+ inode->i_mapping->a_ops = &dyaop->da_op; -+ -+out: -+ return err; -+} -+ -+/* -+ * Is it safe to replace a_ops during the inode/file is in operation? -+ * Yes, I hope so. -+ */ -+int au_dy_irefresh(struct inode *inode) -+{ -+ int err; -+ aufs_bindex_t bstart; -+ struct inode *h_inode; -+ -+ err = 0; -+ if (S_ISREG(inode->i_mode)) { -+ bstart = au_ibstart(inode); -+ h_inode = au_h_iptr(inode, bstart); -+ err = au_dy_iaop(inode, bstart, h_inode); -+ } -+ return err; -+} -+ -+void au_dy_arefresh(int do_dx) -+{ -+ struct au_splhead *spl; -+ struct list_head *head; -+ struct au_dykey *key; -+ -+ spl = dynop + AuDy_AOP; -+ head = &spl->head; -+ spin_lock(&spl->spin); -+ list_for_each_entry(key, head, dk_list) -+ dy_adx((void *)key, do_dx); -+ spin_unlock(&spl->spin); -+} -+ -+const struct vm_operations_struct * -+au_dy_vmop(struct file *file, struct au_branch *br, -+ const struct vm_operations_struct *h_vmop) -+{ -+ struct au_dyvmop *dyvmop; -+ struct au_dynop op; -+ -+ op.dy_type = AuDy_VMOP; -+ op.dy_hvmop = h_vmop; -+ dyvmop = (void *)dy_get(&op, br); -+ if (IS_ERR(dyvmop)) -+ return (void *)dyvmop; -+ return &dyvmop->dv_op; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+void __init au_dy_init(void) -+{ -+ int i; -+ -+ /* make sure that 'struct au_dykey *' can be any type */ -+ BUILD_BUG_ON(offsetof(struct au_dyaop, da_key)); -+ BUILD_BUG_ON(offsetof(struct au_dyvmop, dv_key)); -+ -+ for (i = 0; i < AuDyLast; i++) -+ au_spl_init(dynop + i); -+} -+ -+void au_dy_fin(void) -+{ -+ int i; -+ -+ for (i = 0; i < AuDyLast; i++) -+ WARN_ON(!list_empty(&dynop[i].head)); -+} -diff -Nur linux-2.6.36.orig/fs/aufs/dynop.h linux-2.6.36/fs/aufs/dynop.h ---- linux-2.6.36.orig/fs/aufs/dynop.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/dynop.h 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,89 @@ -+/* -+ * Copyright (C) 2010-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * dynamically customizable operations (for regular files only) -+ */ -+ -+#ifndef __AUFS_DYNOP_H__ -+#define __AUFS_DYNOP_H__ -+ -+#ifdef __KERNEL__ -+ -+#include -+#include -+#include -+#include -+#include "inode.h" -+ -+enum {AuDy_AOP, AuDy_VMOP, AuDyLast}; -+ -+struct au_dynop { -+ int dy_type; -+ union { -+ const void *dy_hop; -+ const struct address_space_operations *dy_haop; -+ const struct vm_operations_struct *dy_hvmop; -+ }; -+}; -+ -+struct au_dykey { -+ union { -+ struct list_head dk_list; -+ struct rcu_head dk_rcu; -+ }; -+ struct au_dynop dk_op; -+ -+ /* -+ * during I am in the branch local array, kref is gotten. when the -+ * branch is removed, kref is put. -+ */ -+ struct kref dk_kref; -+}; -+ -+/* stop unioning since their sizes are very different from each other */ -+struct au_dyaop { -+ struct au_dykey da_key; -+ struct address_space_operations da_op; /* not const */ -+ int (*da_get_xip_mem)(struct address_space *, pgoff_t, int, -+ void **, unsigned long *); -+}; -+ -+struct au_dyvmop { -+ struct au_dykey dv_key; -+ struct vm_operations_struct dv_op; /* not const */ -+}; -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* dynop.c */ -+struct au_branch; -+void au_dy_put(struct au_dykey *key); -+int au_dy_iaop(struct inode *inode, aufs_bindex_t bindex, -+ struct inode *h_inode); -+int au_dy_irefresh(struct inode *inode); -+void au_dy_arefresh(int do_dio); -+const struct vm_operations_struct * -+au_dy_vmop(struct file *file, struct au_branch *br, -+ const struct vm_operations_struct *h_vmop); -+ -+void __init au_dy_init(void); -+void au_dy_fin(void); -+ -+#endif /* __KERNEL__ */ -+#endif /* __AUFS_DYNOP_H__ */ -diff -Nur linux-2.6.36.orig/fs/aufs/export.c linux-2.6.36/fs/aufs/export.c ---- linux-2.6.36.orig/fs/aufs/export.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/export.c 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,798 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * export via nfs -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "aufs.h" -+ -+union conv { -+#ifdef CONFIG_AUFS_INO_T_64 -+ __u32 a[2]; -+#else -+ __u32 a[1]; -+#endif -+ ino_t ino; -+}; -+ -+static ino_t decode_ino(__u32 *a) -+{ -+ union conv u; -+ -+ BUILD_BUG_ON(sizeof(u.ino) != sizeof(u.a)); -+ u.a[0] = a[0]; -+#ifdef CONFIG_AUFS_INO_T_64 -+ u.a[1] = a[1]; -+#endif -+ return u.ino; -+} -+ -+static void encode_ino(__u32 *a, ino_t ino) -+{ -+ union conv u; -+ -+ u.ino = ino; -+ a[0] = u.a[0]; -+#ifdef CONFIG_AUFS_INO_T_64 -+ a[1] = u.a[1]; -+#endif -+} -+ -+/* NFS file handle */ -+enum { -+ Fh_br_id, -+ Fh_sigen, -+#ifdef CONFIG_AUFS_INO_T_64 -+ /* support 64bit inode number */ -+ Fh_ino1, -+ Fh_ino2, -+ Fh_dir_ino1, -+ Fh_dir_ino2, -+#else -+ Fh_ino1, -+ Fh_dir_ino1, -+#endif -+ Fh_igen, -+ Fh_h_type, -+ Fh_tail, -+ -+ Fh_ino = Fh_ino1, -+ Fh_dir_ino = Fh_dir_ino1 -+}; -+ -+static int au_test_anon(struct dentry *dentry) -+{ -+ return !!(dentry->d_flags & DCACHE_DISCONNECTED); -+} -+ -+/* ---------------------------------------------------------------------- */ -+/* inode generation external table */ -+ -+void au_xigen_inc(struct inode *inode) -+{ -+ loff_t pos; -+ ssize_t sz; -+ __u32 igen; -+ struct super_block *sb; -+ struct au_sbinfo *sbinfo; -+ -+ sb = inode->i_sb; -+ AuDebugOn(!au_opt_test(au_mntflags(sb), XINO)); -+ -+ sbinfo = au_sbi(sb); -+ pos = inode->i_ino; -+ pos *= sizeof(igen); -+ igen = inode->i_generation + 1; -+ sz = xino_fwrite(sbinfo->si_xwrite, sbinfo->si_xigen, &igen, -+ sizeof(igen), &pos); -+ if (sz == sizeof(igen)) -+ return; /* success */ -+ -+ if (unlikely(sz >= 0)) -+ AuIOErr("xigen error (%zd)\n", sz); -+} -+ -+int au_xigen_new(struct inode *inode) -+{ -+ int err; -+ loff_t pos; -+ ssize_t sz; -+ struct super_block *sb; -+ struct au_sbinfo *sbinfo; -+ struct file *file; -+ -+ err = 0; -+ /* todo: dirty, at mount time */ -+ if (inode->i_ino == AUFS_ROOT_INO) -+ goto out; -+ sb = inode->i_sb; -+ SiMustAnyLock(sb); -+ if (unlikely(!au_opt_test(au_mntflags(sb), XINO))) -+ goto out; -+ -+ err = -EFBIG; -+ pos = inode->i_ino; -+ if (unlikely(au_loff_max / sizeof(inode->i_generation) - 1 < pos)) { -+ AuIOErr1("too large i%lld\n", pos); -+ goto out; -+ } -+ pos *= sizeof(inode->i_generation); -+ -+ err = 0; -+ sbinfo = au_sbi(sb); -+ file = sbinfo->si_xigen; -+ BUG_ON(!file); -+ -+ if (i_size_read(file->f_dentry->d_inode) -+ < pos + sizeof(inode->i_generation)) { -+ inode->i_generation = atomic_inc_return(&sbinfo->si_xigen_next); -+ sz = xino_fwrite(sbinfo->si_xwrite, file, &inode->i_generation, -+ sizeof(inode->i_generation), &pos); -+ } else -+ sz = xino_fread(sbinfo->si_xread, file, &inode->i_generation, -+ sizeof(inode->i_generation), &pos); -+ if (sz == sizeof(inode->i_generation)) -+ goto out; /* success */ -+ -+ err = sz; -+ if (unlikely(sz >= 0)) { -+ err = -EIO; -+ AuIOErr("xigen error (%zd)\n", sz); -+ } -+ -+out: -+ return err; -+} -+ -+int au_xigen_set(struct super_block *sb, struct file *base) -+{ -+ int err; -+ struct au_sbinfo *sbinfo; -+ struct file *file; -+ -+ SiMustWriteLock(sb); -+ -+ sbinfo = au_sbi(sb); -+ file = au_xino_create2(base, sbinfo->si_xigen); -+ err = PTR_ERR(file); -+ if (IS_ERR(file)) -+ goto out; -+ err = 0; -+ if (sbinfo->si_xigen) -+ fput(sbinfo->si_xigen); -+ sbinfo->si_xigen = file; -+ -+out: -+ return err; -+} -+ -+void au_xigen_clr(struct super_block *sb) -+{ -+ struct au_sbinfo *sbinfo; -+ -+ SiMustWriteLock(sb); -+ -+ sbinfo = au_sbi(sb); -+ if (sbinfo->si_xigen) { -+ fput(sbinfo->si_xigen); -+ sbinfo->si_xigen = NULL; -+ } -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static struct dentry *decode_by_ino(struct super_block *sb, ino_t ino, -+ ino_t dir_ino) -+{ -+ struct dentry *dentry, *d; -+ struct inode *inode; -+ unsigned int sigen; -+ -+ dentry = NULL; -+ inode = ilookup(sb, ino); -+ if (!inode) -+ goto out; -+ -+ dentry = ERR_PTR(-ESTALE); -+ sigen = au_sigen(sb); -+ if (unlikely(is_bad_inode(inode) -+ || IS_DEADDIR(inode) -+ || sigen != au_iigen(inode))) -+ goto out_iput; -+ -+ dentry = NULL; -+ if (!dir_ino || S_ISDIR(inode->i_mode)) -+ dentry = d_find_alias(inode); -+ else { -+ spin_lock(&dcache_lock); -+ list_for_each_entry(d, &inode->i_dentry, d_alias) -+ if (!au_test_anon(d) -+ && d->d_parent->d_inode->i_ino == dir_ino) { -+ dentry = dget_locked(d); -+ break; -+ } -+ spin_unlock(&dcache_lock); -+ } -+ if (unlikely(dentry && au_digen_test(dentry, sigen))) { -+ dput(dentry); -+ dentry = ERR_PTR(-ESTALE); -+ } -+ -+out_iput: -+ iput(inode); -+out: -+ return dentry; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* todo: dirty? */ -+/* if exportfs_decode_fh() passed vfsmount*, we could be happy */ -+ -+struct au_compare_mnt_args { -+ /* input */ -+ struct super_block *sb; -+ -+ /* output */ -+ struct vfsmount *mnt; -+}; -+ -+static int au_compare_mnt(struct vfsmount *mnt, void *arg) -+{ -+ struct au_compare_mnt_args *a = arg; -+ -+ if (mnt->mnt_sb != a->sb) -+ return 0; -+ a->mnt = mntget(mnt); -+ return 1; -+} -+ -+static struct vfsmount *au_mnt_get(struct super_block *sb) -+{ -+ int err; -+ struct au_compare_mnt_args args = { -+ .sb = sb -+ }; -+ struct mnt_namespace *ns; -+ -+ br_read_lock(vfsmount_lock); -+ /* no get/put ?? */ -+ AuDebugOn(!current->nsproxy); -+ ns = current->nsproxy->mnt_ns; -+ AuDebugOn(!ns); -+ err = iterate_mounts(au_compare_mnt, &args, ns->root); -+ br_read_unlock(vfsmount_lock); -+ AuDebugOn(!err); -+ AuDebugOn(!args.mnt); -+ return args.mnt; -+} -+ -+struct au_nfsd_si_lock { -+ unsigned int sigen; -+ aufs_bindex_t bindex, br_id; -+ unsigned char force_lock; -+}; -+ -+static int si_nfsd_read_lock(struct super_block *sb, -+ struct au_nfsd_si_lock *nsi_lock) -+{ -+ int err; -+ aufs_bindex_t bindex; -+ -+ si_read_lock(sb, AuLock_FLUSH); -+ -+ /* branch id may be wrapped around */ -+ err = 0; -+ bindex = au_br_index(sb, nsi_lock->br_id); -+ if (bindex >= 0 && nsi_lock->sigen + AUFS_BRANCH_MAX > au_sigen(sb)) -+ goto out; /* success */ -+ -+ err = -ESTALE; -+ bindex = -1; -+ if (!nsi_lock->force_lock) -+ si_read_unlock(sb); -+ -+out: -+ nsi_lock->bindex = bindex; -+ return err; -+} -+ -+struct find_name_by_ino { -+ int called, found; -+ ino_t ino; -+ char *name; -+ int namelen; -+}; -+ -+static int -+find_name_by_ino(void *arg, const char *name, int namelen, loff_t offset, -+ u64 ino, unsigned int d_type) -+{ -+ struct find_name_by_ino *a = arg; -+ -+ a->called++; -+ if (a->ino != ino) -+ return 0; -+ -+ memcpy(a->name, name, namelen); -+ a->namelen = namelen; -+ a->found = 1; -+ return 1; -+} -+ -+static struct dentry *au_lkup_by_ino(struct path *path, ino_t ino, -+ struct au_nfsd_si_lock *nsi_lock) -+{ -+ struct dentry *dentry, *parent; -+ struct file *file; -+ struct inode *dir; -+ struct find_name_by_ino arg; -+ int err; -+ -+ parent = path->dentry; -+ if (nsi_lock) -+ si_read_unlock(parent->d_sb); -+ file = vfsub_dentry_open(path, au_dir_roflags); -+ dentry = (void *)file; -+ if (IS_ERR(file)) -+ goto out; -+ -+ dentry = ERR_PTR(-ENOMEM); -+ arg.name = __getname_gfp(GFP_NOFS); -+ if (unlikely(!arg.name)) -+ goto out_file; -+ arg.ino = ino; -+ arg.found = 0; -+ do { -+ arg.called = 0; -+ /* smp_mb(); */ -+ err = vfsub_readdir(file, find_name_by_ino, &arg); -+ } while (!err && !arg.found && arg.called); -+ dentry = ERR_PTR(err); -+ if (unlikely(err)) -+ goto out_name; -+ dentry = ERR_PTR(-ENOENT); -+ if (!arg.found) -+ goto out_name; -+ -+ /* do not call au_lkup_one() */ -+ dir = parent->d_inode; -+ mutex_lock(&dir->i_mutex); -+ dentry = vfsub_lookup_one_len(arg.name, parent, arg.namelen); -+ mutex_unlock(&dir->i_mutex); -+ AuTraceErrPtr(dentry); -+ if (IS_ERR(dentry)) -+ goto out_name; -+ AuDebugOn(au_test_anon(dentry)); -+ if (unlikely(!dentry->d_inode)) { -+ dput(dentry); -+ dentry = ERR_PTR(-ENOENT); -+ } -+ -+out_name: -+ __putname(arg.name); -+out_file: -+ fput(file); -+out: -+ if (unlikely(nsi_lock -+ && si_nfsd_read_lock(parent->d_sb, nsi_lock) < 0)) -+ if (!IS_ERR(dentry)) { -+ dput(dentry); -+ dentry = ERR_PTR(-ESTALE); -+ } -+ AuTraceErrPtr(dentry); -+ return dentry; -+} -+ -+static struct dentry *decode_by_dir_ino(struct super_block *sb, ino_t ino, -+ ino_t dir_ino, -+ struct au_nfsd_si_lock *nsi_lock) -+{ -+ struct dentry *dentry; -+ struct path path; -+ -+ if (dir_ino != AUFS_ROOT_INO) { -+ path.dentry = decode_by_ino(sb, dir_ino, 0); -+ dentry = path.dentry; -+ if (!path.dentry || IS_ERR(path.dentry)) -+ goto out; -+ AuDebugOn(au_test_anon(path.dentry)); -+ } else -+ path.dentry = dget(sb->s_root); -+ -+ path.mnt = au_mnt_get(sb); -+ dentry = au_lkup_by_ino(&path, ino, nsi_lock); -+ path_put(&path); -+ -+out: -+ AuTraceErrPtr(dentry); -+ return dentry; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int h_acceptable(void *expv, struct dentry *dentry) -+{ -+ return 1; -+} -+ -+static char *au_build_path(struct dentry *h_parent, struct path *h_rootpath, -+ char *buf, int len, struct super_block *sb) -+{ -+ char *p; -+ int n; -+ struct path path; -+ -+ p = d_path(h_rootpath, buf, len); -+ if (IS_ERR(p)) -+ goto out; -+ n = strlen(p); -+ -+ path.mnt = h_rootpath->mnt; -+ path.dentry = h_parent; -+ p = d_path(&path, buf, len); -+ if (IS_ERR(p)) -+ goto out; -+ if (n != 1) -+ p += n; -+ -+ path.mnt = au_mnt_get(sb); -+ path.dentry = sb->s_root; -+ p = d_path(&path, buf, len - strlen(p)); -+ mntput(path.mnt); -+ if (IS_ERR(p)) -+ goto out; -+ if (n != 1) -+ p[strlen(p)] = '/'; -+ -+out: -+ AuTraceErrPtr(p); -+ return p; -+} -+ -+static -+struct dentry *decode_by_path(struct super_block *sb, ino_t ino, __u32 *fh, -+ int fh_len, struct au_nfsd_si_lock *nsi_lock) -+{ -+ struct dentry *dentry, *h_parent, *root; -+ struct super_block *h_sb; -+ char *pathname, *p; -+ struct vfsmount *h_mnt; -+ struct au_branch *br; -+ int err; -+ struct path path; -+ -+ br = au_sbr(sb, nsi_lock->bindex); -+ h_mnt = br->br_mnt; -+ h_sb = h_mnt->mnt_sb; -+ /* todo: call lower fh_to_dentry()? fh_to_parent()? */ -+ h_parent = exportfs_decode_fh(h_mnt, (void *)(fh + Fh_tail), -+ fh_len - Fh_tail, fh[Fh_h_type], -+ h_acceptable, /*context*/NULL); -+ dentry = h_parent; -+ if (unlikely(!h_parent || IS_ERR(h_parent))) { -+ AuWarn1("%s decode_fh failed, %ld\n", -+ au_sbtype(h_sb), PTR_ERR(h_parent)); -+ goto out; -+ } -+ dentry = NULL; -+ if (unlikely(au_test_anon(h_parent))) { -+ AuWarn1("%s decode_fh returned a disconnected dentry\n", -+ au_sbtype(h_sb)); -+ goto out_h_parent; -+ } -+ -+ dentry = ERR_PTR(-ENOMEM); -+ pathname = (void *)__get_free_page(GFP_NOFS); -+ if (unlikely(!pathname)) -+ goto out_h_parent; -+ -+ root = sb->s_root; -+ path.mnt = h_mnt; -+ di_read_lock_parent(root, !AuLock_IR); -+ path.dentry = au_h_dptr(root, nsi_lock->bindex); -+ di_read_unlock(root, !AuLock_IR); -+ p = au_build_path(h_parent, &path, pathname, PAGE_SIZE, sb); -+ dentry = (void *)p; -+ if (IS_ERR(p)) -+ goto out_pathname; -+ -+ si_read_unlock(sb); -+ err = vfsub_kern_path(p, LOOKUP_FOLLOW | LOOKUP_DIRECTORY, &path); -+ dentry = ERR_PTR(err); -+ if (unlikely(err)) -+ goto out_relock; -+ -+ dentry = ERR_PTR(-ENOENT); -+ AuDebugOn(au_test_anon(path.dentry)); -+ if (unlikely(!path.dentry->d_inode)) -+ goto out_path; -+ -+ if (ino != path.dentry->d_inode->i_ino) -+ dentry = au_lkup_by_ino(&path, ino, /*nsi_lock*/NULL); -+ else -+ dentry = dget(path.dentry); -+ -+out_path: -+ path_put(&path); -+out_relock: -+ if (unlikely(si_nfsd_read_lock(sb, nsi_lock) < 0)) -+ if (!IS_ERR(dentry)) { -+ dput(dentry); -+ dentry = ERR_PTR(-ESTALE); -+ } -+out_pathname: -+ free_page((unsigned long)pathname); -+out_h_parent: -+ dput(h_parent); -+out: -+ AuTraceErrPtr(dentry); -+ return dentry; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static struct dentry * -+aufs_fh_to_dentry(struct super_block *sb, struct fid *fid, int fh_len, -+ int fh_type) -+{ -+ struct dentry *dentry; -+ __u32 *fh = fid->raw; -+ struct au_branch *br; -+ ino_t ino, dir_ino; -+ struct au_nfsd_si_lock nsi_lock = { -+ .force_lock = 0 -+ }; -+ -+ dentry = ERR_PTR(-ESTALE); -+ /* it should never happen, but the file handle is unreliable */ -+ if (unlikely(fh_len < Fh_tail)) -+ goto out; -+ nsi_lock.sigen = fh[Fh_sigen]; -+ nsi_lock.br_id = fh[Fh_br_id]; -+ -+ /* branch id may be wrapped around */ -+ br = NULL; -+ if (unlikely(si_nfsd_read_lock(sb, &nsi_lock))) -+ goto out; -+ nsi_lock.force_lock = 1; -+ -+ /* is this inode still cached? */ -+ ino = decode_ino(fh + Fh_ino); -+ /* it should never happen */ -+ if (unlikely(ino == AUFS_ROOT_INO)) -+ goto out; -+ -+ dir_ino = decode_ino(fh + Fh_dir_ino); -+ dentry = decode_by_ino(sb, ino, dir_ino); -+ if (IS_ERR(dentry)) -+ goto out_unlock; -+ if (dentry) -+ goto accept; -+ -+ /* is the parent dir cached? */ -+ br = au_sbr(sb, nsi_lock.bindex); -+ atomic_inc(&br->br_count); -+ dentry = decode_by_dir_ino(sb, ino, dir_ino, &nsi_lock); -+ if (IS_ERR(dentry)) -+ goto out_unlock; -+ if (dentry) -+ goto accept; -+ -+ /* lookup path */ -+ dentry = decode_by_path(sb, ino, fh, fh_len, &nsi_lock); -+ if (IS_ERR(dentry)) -+ goto out_unlock; -+ if (unlikely(!dentry)) -+ /* todo?: make it ESTALE */ -+ goto out_unlock; -+ -+accept: -+ if (!au_digen_test(dentry, au_sigen(sb)) -+ && dentry->d_inode->i_generation == fh[Fh_igen]) -+ goto out_unlock; /* success */ -+ -+ dput(dentry); -+ dentry = ERR_PTR(-ESTALE); -+out_unlock: -+ if (br) -+ atomic_dec(&br->br_count); -+ si_read_unlock(sb); -+out: -+ AuTraceErrPtr(dentry); -+ return dentry; -+} -+ -+#if 0 /* reserved for future use */ -+/* support subtreecheck option */ -+static struct dentry *aufs_fh_to_parent(struct super_block *sb, struct fid *fid, -+ int fh_len, int fh_type) -+{ -+ struct dentry *parent; -+ __u32 *fh = fid->raw; -+ ino_t dir_ino; -+ -+ dir_ino = decode_ino(fh + Fh_dir_ino); -+ parent = decode_by_ino(sb, dir_ino, 0); -+ if (IS_ERR(parent)) -+ goto out; -+ if (!parent) -+ parent = decode_by_path(sb, au_br_index(sb, fh[Fh_br_id]), -+ dir_ino, fh, fh_len); -+ -+out: -+ AuTraceErrPtr(parent); -+ return parent; -+} -+#endif -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int aufs_encode_fh(struct dentry *dentry, __u32 *fh, int *max_len, -+ int connectable) -+{ -+ int err; -+ aufs_bindex_t bindex, bend; -+ struct super_block *sb, *h_sb; -+ struct inode *inode; -+ struct dentry *parent, *h_parent; -+ struct au_branch *br; -+ -+ AuDebugOn(au_test_anon(dentry)); -+ -+ parent = NULL; -+ err = -ENOSPC; -+ if (unlikely(*max_len <= Fh_tail)) { -+ AuWarn1("NFSv2 client (max_len %d)?\n", *max_len); -+ goto out; -+ } -+ -+ err = FILEID_ROOT; -+ if (IS_ROOT(dentry)) { -+ AuDebugOn(dentry->d_inode->i_ino != AUFS_ROOT_INO); -+ goto out; -+ } -+ -+ h_parent = NULL; -+ err = aufs_read_lock(dentry, AuLock_FLUSH | AuLock_IR | AuLock_GEN); -+ if (unlikely(err)) -+ goto out; -+ -+ inode = dentry->d_inode; -+ AuDebugOn(!inode); -+ sb = dentry->d_sb; -+#ifdef CONFIG_AUFS_DEBUG -+ if (unlikely(!au_opt_test(au_mntflags(sb), XINO))) -+ AuWarn1("NFS-exporting requires xino\n"); -+#endif -+ err = -EIO; -+ parent = dget_parent(dentry); -+ di_read_lock_parent(parent, !AuLock_IR); -+ bend = au_dbtaildir(parent); -+ for (bindex = au_dbstart(parent); bindex <= bend; bindex++) { -+ h_parent = au_h_dptr(parent, bindex); -+ if (h_parent) { -+ dget(h_parent); -+ break; -+ } -+ } -+ if (unlikely(!h_parent)) -+ goto out_unlock; -+ -+ err = -EPERM; -+ br = au_sbr(sb, bindex); -+ h_sb = br->br_mnt->mnt_sb; -+ if (unlikely(!h_sb->s_export_op)) { -+ AuErr1("%s branch is not exportable\n", au_sbtype(h_sb)); -+ goto out_dput; -+ } -+ -+ fh[Fh_br_id] = br->br_id; -+ fh[Fh_sigen] = au_sigen(sb); -+ encode_ino(fh + Fh_ino, inode->i_ino); -+ encode_ino(fh + Fh_dir_ino, parent->d_inode->i_ino); -+ fh[Fh_igen] = inode->i_generation; -+ -+ *max_len -= Fh_tail; -+ fh[Fh_h_type] = exportfs_encode_fh(h_parent, (void *)(fh + Fh_tail), -+ max_len, -+ /*connectable or subtreecheck*/0); -+ err = fh[Fh_h_type]; -+ *max_len += Fh_tail; -+ /* todo: macros? */ -+ if (err != 255) -+ err = 99; -+ else -+ AuWarn1("%s encode_fh failed\n", au_sbtype(h_sb)); -+ -+out_dput: -+ dput(h_parent); -+out_unlock: -+ di_read_unlock(parent, !AuLock_IR); -+ dput(parent); -+ aufs_read_unlock(dentry, AuLock_IR); -+out: -+ if (unlikely(err < 0)) -+ err = 255; -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int aufs_commit_metadata(struct inode *inode) -+{ -+ int err; -+ aufs_bindex_t bindex; -+ struct super_block *sb; -+ struct inode *h_inode; -+ int (*f)(struct inode *inode); -+ -+ sb = inode->i_sb; -+ si_read_lock(sb, AuLock_FLUSH | AuLock_NOPLMW); -+ ii_write_lock_child(inode); -+ bindex = au_ibstart(inode); -+ AuDebugOn(bindex < 0); -+ h_inode = au_h_iptr(inode, bindex); -+ -+ f = h_inode->i_sb->s_export_op->commit_metadata; -+ if (f) -+ err = f(h_inode); -+ else { -+ struct writeback_control wbc = { -+ .sync_mode = WB_SYNC_ALL, -+ .nr_to_write = 0 /* metadata only */ -+ }; -+ -+ err = sync_inode(h_inode, &wbc); -+ } -+ -+ au_cpup_attr_timesizes(inode); -+ ii_write_unlock(inode); -+ si_read_unlock(sb); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static struct export_operations aufs_export_op = { -+ .fh_to_dentry = aufs_fh_to_dentry, -+ /* .fh_to_parent = aufs_fh_to_parent, */ -+ .encode_fh = aufs_encode_fh, -+ .commit_metadata = aufs_commit_metadata -+}; -+ -+void au_export_init(struct super_block *sb) -+{ -+ struct au_sbinfo *sbinfo; -+ __u32 u; -+ -+ sb->s_export_op = &aufs_export_op; -+ sbinfo = au_sbi(sb); -+ sbinfo->si_xigen = NULL; -+ get_random_bytes(&u, sizeof(u)); -+ BUILD_BUG_ON(sizeof(u) != sizeof(int)); -+ atomic_set(&sbinfo->si_xigen_next, u); -+} -diff -Nur linux-2.6.36.orig/fs/aufs/f_op.c linux-2.6.36/fs/aufs/f_op.c ---- linux-2.6.36.orig/fs/aufs/f_op.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/f_op.c 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,906 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * file and vm operations -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include "aufs.h" -+ -+int au_do_open_nondir(struct file *file, int flags) -+{ -+ int err; -+ aufs_bindex_t bindex; -+ struct file *h_file; -+ struct dentry *dentry; -+ struct au_finfo *finfo; -+ -+ FiMustWriteLock(file); -+ -+ dentry = file->f_dentry; -+ err = au_d_alive(dentry); -+ if (unlikely(err)) -+ goto out; -+ -+ finfo = au_fi(file); -+ memset(&finfo->fi_htop, 0, sizeof(finfo->fi_htop)); -+ finfo->fi_hvmop = NULL; -+ bindex = au_dbstart(dentry); -+ h_file = au_h_open(dentry, bindex, flags, file); -+ if (IS_ERR(h_file)) -+ err = PTR_ERR(h_file); -+ else { -+ au_set_fbstart(file, bindex); -+ au_set_h_fptr(file, bindex, h_file); -+ au_update_figen(file); -+ /* todo: necessary? */ -+ /* file->f_ra = h_file->f_ra; */ -+ } -+ -+out: -+ return err; -+} -+ -+static int aufs_open_nondir(struct inode *inode __maybe_unused, -+ struct file *file) -+{ -+ int err; -+ struct super_block *sb; -+ -+ AuDbg("%.*s, f_ flags 0x%x, f_mode 0x%x\n", -+ AuDLNPair(file->f_dentry), vfsub_file_flags(file), -+ file->f_mode); -+ -+ sb = file->f_dentry->d_sb; -+ si_read_lock(sb, AuLock_FLUSH); -+ err = au_do_open(file, au_do_open_nondir, /*fidir*/NULL); -+ si_read_unlock(sb); -+ return err; -+} -+ -+int aufs_release_nondir(struct inode *inode __maybe_unused, struct file *file) -+{ -+ struct au_finfo *finfo; -+ aufs_bindex_t bindex; -+ -+ finfo = au_fi(file); -+ bindex = finfo->fi_btop; -+ if (bindex >= 0) { -+ /* remove me from sb->s_files */ -+ file_sb_list_del(file); -+ au_set_h_fptr(file, bindex, NULL); -+ } -+ -+ au_finfo_fin(file); -+ return 0; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int au_do_flush_nondir(struct file *file, fl_owner_t id) -+{ -+ int err; -+ struct file *h_file; -+ -+ err = 0; -+ h_file = au_hf_top(file); -+ if (h_file) -+ err = vfsub_flush(h_file, id); -+ return err; -+} -+ -+static int aufs_flush_nondir(struct file *file, fl_owner_t id) -+{ -+ return au_do_flush(file, id, au_do_flush_nondir); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static ssize_t aufs_read(struct file *file, char __user *buf, size_t count, -+ loff_t *ppos) -+{ -+ ssize_t err; -+ struct dentry *dentry; -+ struct file *h_file; -+ struct super_block *sb; -+ -+ dentry = file->f_dentry; -+ sb = dentry->d_sb; -+ si_read_lock(sb, AuLock_FLUSH | AuLock_NOPLMW); -+ err = au_reval_and_lock_fdi(file, au_reopen_nondir, /*wlock*/0); -+ if (unlikely(err)) -+ goto out; -+ -+ h_file = au_hf_top(file); -+ err = vfsub_read_u(h_file, buf, count, ppos); -+ /* todo: necessary? */ -+ /* file->f_ra = h_file->f_ra; */ -+ fsstack_copy_attr_atime(dentry->d_inode, h_file->f_dentry->d_inode); -+ -+ di_read_unlock(dentry, AuLock_IR); -+ fi_read_unlock(file); -+out: -+ si_read_unlock(sb); -+ return err; -+} -+ -+/* -+ * todo: very ugly -+ * it locks both of i_mutex and si_rwsem for read in safe. -+ * if the plink maintenance mode continues forever (that is the problem), -+ * may loop forever. -+ */ -+static void au_mtx_and_read_lock(struct inode *inode) -+{ -+ int err; -+ struct super_block *sb = inode->i_sb; -+ -+ while (1) { -+ mutex_lock(&inode->i_mutex); -+ err = si_read_lock(sb, AuLock_FLUSH | AuLock_NOPLM); -+ if (!err) -+ break; -+ mutex_unlock(&inode->i_mutex); -+ si_read_lock(sb, AuLock_NOPLMW); -+ si_read_unlock(sb); -+ } -+} -+ -+static ssize_t aufs_write(struct file *file, const char __user *ubuf, -+ size_t count, loff_t *ppos) -+{ -+ ssize_t err; -+ struct au_pin pin; -+ struct dentry *dentry; -+ struct inode *inode; -+ struct file *h_file; -+ char __user *buf = (char __user *)ubuf; -+ -+ dentry = file->f_dentry; -+ inode = dentry->d_inode; -+ au_mtx_and_read_lock(inode); -+ -+ err = au_reval_and_lock_fdi(file, au_reopen_nondir, /*wlock*/1); -+ if (unlikely(err)) -+ goto out; -+ -+ err = au_ready_to_write(file, -1, &pin); -+ di_downgrade_lock(dentry, AuLock_IR); -+ if (unlikely(err)) -+ goto out_unlock; -+ -+ h_file = au_hf_top(file); -+ au_unpin(&pin); -+ err = vfsub_write_u(h_file, buf, count, ppos); -+ au_cpup_attr_timesizes(inode); -+ inode->i_mode = h_file->f_dentry->d_inode->i_mode; -+ -+out_unlock: -+ di_read_unlock(dentry, AuLock_IR); -+ fi_write_unlock(file); -+out: -+ si_read_unlock(inode->i_sb); -+ mutex_unlock(&inode->i_mutex); -+ return err; -+} -+ -+static ssize_t au_do_aio(struct file *h_file, int rw, struct kiocb *kio, -+ const struct iovec *iov, unsigned long nv, loff_t pos) -+{ -+ ssize_t err; -+ struct file *file; -+ ssize_t (*func)(struct kiocb *, const struct iovec *, unsigned long, -+ loff_t); -+ -+ err = security_file_permission(h_file, rw); -+ if (unlikely(err)) -+ goto out; -+ -+ err = -ENOSYS; -+ func = NULL; -+ if (rw == MAY_READ) -+ func = h_file->f_op->aio_read; -+ else if (rw == MAY_WRITE) -+ func = h_file->f_op->aio_write; -+ if (func) { -+ file = kio->ki_filp; -+ kio->ki_filp = h_file; -+ err = func(kio, iov, nv, pos); -+ kio->ki_filp = file; -+ } else -+ /* currently there is no such fs */ -+ WARN_ON_ONCE(1); -+ -+out: -+ return err; -+} -+ -+static ssize_t aufs_aio_read(struct kiocb *kio, const struct iovec *iov, -+ unsigned long nv, loff_t pos) -+{ -+ ssize_t err; -+ struct file *file, *h_file; -+ struct dentry *dentry; -+ struct super_block *sb; -+ -+ file = kio->ki_filp; -+ dentry = file->f_dentry; -+ sb = dentry->d_sb; -+ si_read_lock(sb, AuLock_FLUSH | AuLock_NOPLMW); -+ err = au_reval_and_lock_fdi(file, au_reopen_nondir, /*wlock*/0); -+ if (unlikely(err)) -+ goto out; -+ -+ h_file = au_hf_top(file); -+ err = au_do_aio(h_file, MAY_READ, kio, iov, nv, pos); -+ /* todo: necessary? */ -+ /* file->f_ra = h_file->f_ra; */ -+ fsstack_copy_attr_atime(dentry->d_inode, h_file->f_dentry->d_inode); -+ di_read_unlock(dentry, AuLock_IR); -+ fi_read_unlock(file); -+ -+out: -+ si_read_unlock(sb); -+ return err; -+} -+ -+static ssize_t aufs_aio_write(struct kiocb *kio, const struct iovec *iov, -+ unsigned long nv, loff_t pos) -+{ -+ ssize_t err; -+ struct au_pin pin; -+ struct dentry *dentry; -+ struct inode *inode; -+ struct file *file, *h_file; -+ -+ file = kio->ki_filp; -+ dentry = file->f_dentry; -+ inode = dentry->d_inode; -+ au_mtx_and_read_lock(inode); -+ -+ err = au_reval_and_lock_fdi(file, au_reopen_nondir, /*wlock*/1); -+ if (unlikely(err)) -+ goto out; -+ -+ err = au_ready_to_write(file, -1, &pin); -+ di_downgrade_lock(dentry, AuLock_IR); -+ if (unlikely(err)) -+ goto out_unlock; -+ -+ au_unpin(&pin); -+ h_file = au_hf_top(file); -+ err = au_do_aio(h_file, MAY_WRITE, kio, iov, nv, pos); -+ au_cpup_attr_timesizes(inode); -+ inode->i_mode = h_file->f_dentry->d_inode->i_mode; -+ -+out_unlock: -+ di_read_unlock(dentry, AuLock_IR); -+ fi_write_unlock(file); -+out: -+ si_read_unlock(inode->i_sb); -+ mutex_unlock(&inode->i_mutex); -+ return err; -+} -+ -+static ssize_t aufs_splice_read(struct file *file, loff_t *ppos, -+ struct pipe_inode_info *pipe, size_t len, -+ unsigned int flags) -+{ -+ ssize_t err; -+ struct file *h_file; -+ struct dentry *dentry; -+ struct super_block *sb; -+ -+ dentry = file->f_dentry; -+ sb = dentry->d_sb; -+ si_read_lock(sb, AuLock_FLUSH | AuLock_NOPLMW); -+ err = au_reval_and_lock_fdi(file, au_reopen_nondir, /*wlock*/0); -+ if (unlikely(err)) -+ goto out; -+ -+ err = -EINVAL; -+ h_file = au_hf_top(file); -+ if (au_test_loopback_kthread()) { -+ file->f_mapping = h_file->f_mapping; -+ smp_mb(); /* unnecessary? */ -+ } -+ err = vfsub_splice_to(h_file, ppos, pipe, len, flags); -+ /* todo: necessasry? */ -+ /* file->f_ra = h_file->f_ra; */ -+ fsstack_copy_attr_atime(dentry->d_inode, h_file->f_dentry->d_inode); -+ -+ di_read_unlock(dentry, AuLock_IR); -+ fi_read_unlock(file); -+ -+out: -+ si_read_unlock(sb); -+ return err; -+} -+ -+static ssize_t -+aufs_splice_write(struct pipe_inode_info *pipe, struct file *file, loff_t *ppos, -+ size_t len, unsigned int flags) -+{ -+ ssize_t err; -+ struct au_pin pin; -+ struct dentry *dentry; -+ struct inode *inode; -+ struct file *h_file; -+ -+ dentry = file->f_dentry; -+ inode = dentry->d_inode; -+ au_mtx_and_read_lock(inode); -+ err = au_reval_and_lock_fdi(file, au_reopen_nondir, /*wlock*/1); -+ if (unlikely(err)) -+ goto out; -+ -+ err = au_ready_to_write(file, -1, &pin); -+ di_downgrade_lock(dentry, AuLock_IR); -+ if (unlikely(err)) -+ goto out_unlock; -+ -+ h_file = au_hf_top(file); -+ au_unpin(&pin); -+ err = vfsub_splice_from(pipe, h_file, ppos, len, flags); -+ au_cpup_attr_timesizes(inode); -+ inode->i_mode = h_file->f_dentry->d_inode->i_mode; -+ -+out_unlock: -+ di_read_unlock(dentry, AuLock_IR); -+ fi_write_unlock(file); -+out: -+ si_read_unlock(inode->i_sb); -+ mutex_unlock(&inode->i_mutex); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static struct file *au_safe_file(struct vm_area_struct *vma) -+{ -+ struct file *file; -+ -+ file = vma->vm_file; -+ if (au_fi(file) && au_test_aufs(file->f_dentry->d_sb)) -+ return file; -+ return NULL; -+} -+ -+static void au_reset_file(struct vm_area_struct *vma, struct file *file) -+{ -+ vma->vm_file = file; -+ /* smp_mb(); */ /* flush vm_file */ -+} -+ -+static int aufs_fault(struct vm_area_struct *vma, struct vm_fault *vmf) -+{ -+ int err; -+ static DECLARE_WAIT_QUEUE_HEAD(wq); -+ struct file *file, *h_file; -+ struct au_finfo *finfo; -+ -+ /* todo: non-robr mode, user vm_file as it is? */ -+ wait_event(wq, (file = au_safe_file(vma))); -+ -+ /* do not revalidate, no si lock */ -+ finfo = au_fi(file); -+ AuDebugOn(finfo->fi_hdir); -+ h_file = finfo->fi_htop.hf_file; -+ AuDebugOn(!h_file || !finfo->fi_hvmop); -+ -+ mutex_lock(&finfo->fi_vm_mtx); -+ vma->vm_file = h_file; -+ err = finfo->fi_hvmop->fault(vma, vmf); -+ /* todo: necessary? */ -+ /* file->f_ra = h_file->f_ra; */ -+ au_reset_file(vma, file); -+ mutex_unlock(&finfo->fi_vm_mtx); -+#if 0 /* def CONFIG_SMP */ -+ /* wake_up_nr(&wq, online_cpu - 1); */ -+ wake_up_all(&wq); -+#else -+ wake_up(&wq); -+#endif -+ -+ return err; -+} -+ -+static int aufs_page_mkwrite(struct vm_area_struct *vma, struct vm_fault *vmf) -+{ -+ int err; -+ static DECLARE_WAIT_QUEUE_HEAD(wq); -+ struct file *file, *h_file; -+ struct au_finfo *finfo; -+ -+ wait_event(wq, (file = au_safe_file(vma))); -+ -+ finfo = au_fi(file); -+ AuDebugOn(finfo->fi_hdir); -+ h_file = finfo->fi_htop.hf_file; -+ AuDebugOn(!h_file || !finfo->fi_hvmop); -+ -+ mutex_lock(&finfo->fi_vm_mtx); -+ vma->vm_file = h_file; -+ err = finfo->fi_hvmop->page_mkwrite(vma, vmf); -+ au_reset_file(vma, file); -+ mutex_unlock(&finfo->fi_vm_mtx); -+ wake_up(&wq); -+ -+ return err; -+} -+ -+static void aufs_vm_close(struct vm_area_struct *vma) -+{ -+ static DECLARE_WAIT_QUEUE_HEAD(wq); -+ struct file *file, *h_file; -+ struct au_finfo *finfo; -+ -+ wait_event(wq, (file = au_safe_file(vma))); -+ -+ finfo = au_fi(file); -+ AuDebugOn(finfo->fi_hdir); -+ h_file = finfo->fi_htop.hf_file; -+ AuDebugOn(!h_file || !finfo->fi_hvmop); -+ -+ mutex_lock(&finfo->fi_vm_mtx); -+ vma->vm_file = h_file; -+ finfo->fi_hvmop->close(vma); -+ au_reset_file(vma, file); -+ mutex_unlock(&finfo->fi_vm_mtx); -+ wake_up(&wq); -+} -+ -+const struct vm_operations_struct aufs_vm_ops = { -+ .close = aufs_vm_close, -+ .fault = aufs_fault, -+ .page_mkwrite = aufs_page_mkwrite -+}; -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* cf. linux/include/linux/mman.h: calc_vm_prot_bits() */ -+#define AuConv_VM_PROT(f, b) _calc_vm_trans(f, VM_##b, PROT_##b) -+ -+static unsigned long au_arch_prot_conv(unsigned long flags) -+{ -+ /* currently ppc64 only */ -+#ifdef CONFIG_PPC64 -+ /* cf. linux/arch/powerpc/include/asm/mman.h */ -+ AuDebugOn(arch_calc_vm_prot_bits(-1) != VM_SAO); -+ return AuConv_VM_PROT(flags, SAO); -+#else -+ AuDebugOn(arch_calc_vm_prot_bits(-1)); -+ return 0; -+#endif -+} -+ -+static unsigned long au_prot_conv(unsigned long flags) -+{ -+ return AuConv_VM_PROT(flags, READ) -+ | AuConv_VM_PROT(flags, WRITE) -+ | AuConv_VM_PROT(flags, EXEC) -+ | au_arch_prot_conv(flags); -+} -+ -+/* cf. linux/include/linux/mman.h: calc_vm_flag_bits() */ -+#define AuConv_VM_MAP(f, b) _calc_vm_trans(f, VM_##b, MAP_##b) -+ -+static unsigned long au_flag_conv(unsigned long flags) -+{ -+ return AuConv_VM_MAP(flags, GROWSDOWN) -+ | AuConv_VM_MAP(flags, DENYWRITE) -+ | AuConv_VM_MAP(flags, EXECUTABLE) -+ | AuConv_VM_MAP(flags, LOCKED); -+} -+ -+static struct vm_operations_struct * -+au_hvmop(struct file *h_file, struct vm_area_struct *vma, unsigned long *flags) -+{ -+ struct vm_operations_struct *h_vmop; -+ unsigned long prot; -+ int err; -+ -+ h_vmop = ERR_PTR(-ENODEV); -+ if (!h_file->f_op || !h_file->f_op->mmap) -+ goto out; -+ -+ prot = au_prot_conv(vma->vm_flags); -+ err = security_file_mmap(h_file, /*reqprot*/prot, prot, -+ au_flag_conv(vma->vm_flags), vma->vm_start, 0); -+ h_vmop = ERR_PTR(err); -+ if (unlikely(err)) -+ goto out; -+ -+ err = h_file->f_op->mmap(h_file, vma); -+ h_vmop = ERR_PTR(err); -+ if (unlikely(err)) -+ goto out; -+ -+ /* oops, it became 'const' */ -+ h_vmop = (struct vm_operations_struct *)vma->vm_ops; -+ *flags = vma->vm_flags; -+ err = do_munmap(current->mm, vma->vm_start, -+ vma->vm_end - vma->vm_start); -+ if (unlikely(err)) { -+ AuIOErr("failed internal unmapping %.*s, %d\n", -+ AuDLNPair(h_file->f_dentry), err); -+ h_vmop = ERR_PTR(-EIO); -+ } -+ -+out: -+ return h_vmop; -+} -+ -+/* -+ * This is another ugly approach to keep the lock order, particularly -+ * mm->mmap_sem and aufs rwsem. The previous approach was reverted and you can -+ * find it in git-log, if you want. -+ * -+ * native readdir: i_mutex, copy_to_user, mmap_sem -+ * aufs readdir: i_mutex, rwsem, nested-i_mutex, copy_to_user, mmap_sem -+ * -+ * Before aufs_mmap() mmap_sem is acquired already, but aufs_mmap() has to -+ * acquire aufs rwsem. It introduces a circular locking dependency. -+ * To address this problem, aufs_mmap() delegates the part which requires aufs -+ * rwsem to its internal workqueue. -+ */ -+ -+/* very ugly approach */ -+#include "mtx.h" -+ -+struct au_mmap_pre_args { -+ /* input */ -+ struct file *file; -+ struct vm_area_struct *vma; -+ -+ /* output */ -+ int *errp; -+ struct file *h_file; -+ struct au_branch *br; -+ int mmapped; -+}; -+ -+static int au_mmap_pre(struct file *file, struct vm_area_struct *vma, -+ struct file **h_file, struct au_branch **br, -+ int *mmapped) -+{ -+ int err; -+ aufs_bindex_t bstart; -+ const unsigned char wlock -+ = !!(file->f_mode & FMODE_WRITE) && (vma->vm_flags & VM_SHARED); -+ struct dentry *dentry; -+ struct super_block *sb; -+ -+ dentry = file->f_dentry; -+ sb = dentry->d_sb; -+ si_read_lock(sb, AuLock_NOPLMW); -+ err = au_reval_and_lock_fdi(file, au_reopen_nondir, /*wlock*/1); -+ if (unlikely(err)) -+ goto out; -+ -+ *mmapped = !!au_test_mmapped(file); -+ if (wlock) { -+ struct au_pin pin; -+ -+ err = au_ready_to_write(file, -1, &pin); -+ di_write_unlock(dentry); -+ if (unlikely(err)) -+ goto out_unlock; -+ au_unpin(&pin); -+ } else -+ di_write_unlock(dentry); -+ bstart = au_fbstart(file); -+ *br = au_sbr(sb, bstart); -+ *h_file = au_hf_top(file); -+ get_file(*h_file); -+ au_fi_mmap_lock(file); -+ -+out_unlock: -+ fi_write_unlock(file); -+out: -+ si_read_unlock(sb); -+ return err; -+} -+ -+static void au_call_mmap_pre(void *args) -+{ -+ struct au_mmap_pre_args *a = args; -+ *a->errp = au_mmap_pre(a->file, a->vma, &a->h_file, &a->br, -+ &a->mmapped); -+} -+ -+static int aufs_mmap(struct file *file, struct vm_area_struct *vma) -+{ -+ int err, wkq_err; -+ unsigned long h_vmflags; -+ struct au_finfo *finfo; -+ struct dentry *h_dentry; -+ struct vm_operations_struct *h_vmop, *vmop; -+ struct au_mmap_pre_args args = { -+ .file = file, -+ .vma = vma, -+ .errp = &err -+ }; -+ -+ wkq_err = au_wkq_wait_pre(au_call_mmap_pre, &args); -+ if (unlikely(wkq_err)) -+ err = wkq_err; -+ if (unlikely(err)) -+ goto out; -+ finfo = au_fi(file); -+ mutex_set_owner(&finfo->fi_mmap); -+ -+ h_dentry = args.h_file->f_dentry; -+ if (!args.mmapped && au_test_fs_bad_mapping(h_dentry->d_sb)) { -+ /* -+ * by this assignment, f_mapping will differs from aufs inode -+ * i_mapping. -+ * if someone else mixes the use of f_dentry->d_inode and -+ * f_mapping->host, then a problem may arise. -+ */ -+ file->f_mapping = args.h_file->f_mapping; -+ } -+ -+ /* always try this internal mmap to get vma flags */ -+ h_vmflags = 0; /* gcc warning */ -+ h_vmop = au_hvmop(args.h_file, vma, &h_vmflags); -+ err = PTR_ERR(h_vmop); -+ if (IS_ERR(h_vmop)) -+ goto out_unlock; -+ AuDebugOn(args.mmapped && h_vmop != finfo->fi_hvmop); -+ -+ vmop = (void *)au_dy_vmop(file, args.br, h_vmop); -+ err = PTR_ERR(vmop); -+ if (IS_ERR(vmop)) -+ goto out_unlock; -+ -+ /* -+ * unnecessary to handle MAP_DENYWRITE and deny_write_access()? -+ * currently MAP_DENYWRITE from userspace is ignored, but elf loader -+ * sets it. when FMODE_EXEC is set (by open_exec() or sys_uselib()), -+ * both of the aufs file and the lower file is deny_write_access()-ed. -+ * finally I hope we can skip handlling MAP_DENYWRITE here. -+ */ -+ err = generic_file_mmap(file, vma); -+ if (unlikely(err)) -+ goto out_unlock; -+ -+ vma->vm_ops = vmop; -+ vma->vm_flags = h_vmflags; -+ if (!args.mmapped) -+ finfo->fi_hvmop = h_vmop; -+ -+ vfsub_file_accessed(args.h_file); -+ /* update without lock, I don't think it a problem */ -+ fsstack_copy_attr_atime(file->f_dentry->d_inode, h_dentry->d_inode); -+ -+out_unlock: -+ au_fi_mmap_unlock(file); -+ fput(args.h_file); -+out: -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int aufs_fsync_nondir(struct file *file, int datasync) -+{ -+ int err; -+ struct au_pin pin; -+ struct dentry *dentry; -+ struct inode *inode; -+ struct file *h_file; -+ struct super_block *sb; -+ -+ dentry = file->f_dentry; -+ inode = dentry->d_inode; -+ IMustLock(file->f_mapping->host); -+ if (inode != file->f_mapping->host) { -+ mutex_unlock(&file->f_mapping->host->i_mutex); -+ mutex_lock(&inode->i_mutex); -+ } -+ IMustLock(inode); -+ -+ sb = dentry->d_sb; -+ err = si_read_lock(sb, AuLock_FLUSH | AuLock_NOPLM); -+ if (unlikely(err)) -+ goto out; -+ -+ err = 0; /* -EBADF; */ /* posix? */ -+ if (unlikely(!(file->f_mode & FMODE_WRITE))) -+ goto out_si; -+ err = au_reval_and_lock_fdi(file, au_reopen_nondir, /*wlock*/1); -+ if (unlikely(err)) -+ goto out_si; -+ -+ err = au_ready_to_write(file, -1, &pin); -+ di_downgrade_lock(dentry, AuLock_IR); -+ if (unlikely(err)) -+ goto out_unlock; -+ au_unpin(&pin); -+ -+ err = -EINVAL; -+ h_file = au_hf_top(file); -+ if (h_file->f_op && h_file->f_op->fsync) { -+ struct mutex *h_mtx; -+ -+ /* -+ * no filemap_fdatawrite() since aufs file has no its own -+ * mapping, but dir. -+ */ -+ h_mtx = &h_file->f_dentry->d_inode->i_mutex; -+ mutex_lock_nested(h_mtx, AuLsc_I_CHILD); -+ err = h_file->f_op->fsync(h_file, datasync); -+ if (!err) -+ vfsub_update_h_iattr(&h_file->f_path, /*did*/NULL); -+ /*ignore*/ -+ au_cpup_attr_timesizes(inode); -+ mutex_unlock(h_mtx); -+ } -+ -+out_unlock: -+ di_read_unlock(dentry, AuLock_IR); -+ fi_write_unlock(file); -+out_si: -+ si_read_unlock(sb); -+out: -+ if (inode != file->f_mapping->host) { -+ mutex_unlock(&inode->i_mutex); -+ mutex_lock(&file->f_mapping->host->i_mutex); -+ } -+ return err; -+} -+ -+/* no one supports this operation, currently */ -+#if 0 -+static int aufs_aio_fsync_nondir(struct kiocb *kio, int datasync) -+{ -+ int err; -+ struct au_pin pin; -+ struct dentry *dentry; -+ struct inode *inode; -+ struct file *file, *h_file; -+ -+ file = kio->ki_filp; -+ dentry = file->f_dentry; -+ inode = dentry->d_inode; -+ au_mtx_and_read_lock(inode); -+ -+ err = 0; /* -EBADF; */ /* posix? */ -+ if (unlikely(!(file->f_mode & FMODE_WRITE))) -+ goto out; -+ err = au_reval_and_lock_fdi(file, au_reopen_nondir, /*wlock*/1); -+ if (unlikely(err)) -+ goto out; -+ -+ err = au_ready_to_write(file, -1, &pin); -+ di_downgrade_lock(dentry, AuLock_IR); -+ if (unlikely(err)) -+ goto out_unlock; -+ au_unpin(&pin); -+ -+ err = -ENOSYS; -+ h_file = au_hf_top(file); -+ if (h_file->f_op && h_file->f_op->aio_fsync) { -+ struct dentry *h_d; -+ struct mutex *h_mtx; -+ -+ h_d = h_file->f_dentry; -+ h_mtx = &h_d->d_inode->i_mutex; -+ if (!is_sync_kiocb(kio)) { -+ get_file(h_file); -+ fput(file); -+ } -+ kio->ki_filp = h_file; -+ err = h_file->f_op->aio_fsync(kio, datasync); -+ mutex_lock_nested(h_mtx, AuLsc_I_CHILD); -+ if (!err) -+ vfsub_update_h_iattr(&h_file->f_path, /*did*/NULL); -+ /*ignore*/ -+ au_cpup_attr_timesizes(inode); -+ mutex_unlock(h_mtx); -+ } -+ -+out_unlock: -+ di_read_unlock(dentry, AuLock_IR); -+ fi_write_unlock(file); -+out: -+ si_read_unlock(inode->sb); -+ mutex_unlock(&inode->i_mutex); -+ return err; -+} -+#endif -+ -+static int aufs_fasync(int fd, struct file *file, int flag) -+{ -+ int err; -+ struct file *h_file; -+ struct dentry *dentry; -+ struct super_block *sb; -+ -+ dentry = file->f_dentry; -+ sb = dentry->d_sb; -+ si_read_lock(sb, AuLock_FLUSH | AuLock_NOPLMW); -+ err = au_reval_and_lock_fdi(file, au_reopen_nondir, /*wlock*/0); -+ if (unlikely(err)) -+ goto out; -+ -+ h_file = au_hf_top(file); -+ if (h_file->f_op && h_file->f_op->fasync) -+ err = h_file->f_op->fasync(fd, h_file, flag); -+ -+ di_read_unlock(dentry, AuLock_IR); -+ fi_read_unlock(file); -+ -+out: -+ si_read_unlock(sb); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* no one supports this operation, currently */ -+#if 0 -+static ssize_t aufs_sendpage(struct file *file, struct page *page, int offset, -+ size_t len, loff_t *pos , int more) -+{ -+} -+#endif -+ -+/* ---------------------------------------------------------------------- */ -+ -+const struct file_operations aufs_file_fop = { -+ .owner = THIS_MODULE, -+ /* -+ * while generic_file_llseek/_unlocked() don't use BKL, -+ * don't use it since it operates file->f_mapping->host. -+ * in aufs, it may be a real file and may confuse users by UDBA. -+ */ -+ /* .llseek = generic_file_llseek, */ -+ -+ .read = aufs_read, -+ .write = aufs_write, -+ .aio_read = aufs_aio_read, -+ .aio_write = aufs_aio_write, -+#ifdef CONFIG_AUFS_POLL -+ .poll = aufs_poll, -+#endif -+ .unlocked_ioctl = aufs_ioctl_nondir, -+#ifdef CONFIG_COMPAT -+ .compat_ioctl = aufs_ioctl_nondir, /* same */ -+#endif -+ .mmap = aufs_mmap, -+ .open = aufs_open_nondir, -+ .flush = aufs_flush_nondir, -+ .release = aufs_release_nondir, -+ .fsync = aufs_fsync_nondir, -+ /* .aio_fsync = aufs_aio_fsync_nondir, */ -+ .fasync = aufs_fasync, -+ /* .sendpage = aufs_sendpage, */ -+ .splice_write = aufs_splice_write, -+ .splice_read = aufs_splice_read, -+#if 0 -+ .aio_splice_write = aufs_aio_splice_write, -+ .aio_splice_read = aufs_aio_splice_read -+#endif -+}; -diff -Nur linux-2.6.36.orig/fs/aufs/f_op_sp.c linux-2.6.36/fs/aufs/f_op_sp.c ---- linux-2.6.36.orig/fs/aufs/f_op_sp.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/f_op_sp.c 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,299 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * file operations for special files. -+ * while they exist in aufs virtually, -+ * their file I/O is handled out of aufs. -+ */ -+ -+#include -+#include "aufs.h" -+ -+static ssize_t aufs_aio_read_sp(struct kiocb *kio, const struct iovec *iov, -+ unsigned long nv, loff_t pos) -+{ -+ ssize_t err; -+ aufs_bindex_t bstart; -+ unsigned char wbr; -+ struct file *file, *h_file; -+ struct super_block *sb; -+ -+ file = kio->ki_filp; -+ sb = file->f_dentry->d_sb; -+ si_read_lock(sb, AuLock_FLUSH); -+ fi_read_lock(file); -+ bstart = au_fbstart(file); -+ h_file = au_hf_top(file); -+ fi_read_unlock(file); -+ wbr = !!au_br_writable(au_sbr(sb, bstart)->br_perm); -+ si_read_unlock(sb); -+ -+ /* do not change the file in kio */ -+ AuDebugOn(!h_file->f_op || !h_file->f_op->aio_read); -+ err = h_file->f_op->aio_read(kio, iov, nv, pos); -+ if (err > 0 && wbr) -+ file_accessed(h_file); -+ -+ return err; -+} -+ -+static ssize_t aufs_aio_write_sp(struct kiocb *kio, const struct iovec *iov, -+ unsigned long nv, loff_t pos) -+{ -+ ssize_t err; -+ aufs_bindex_t bstart; -+ unsigned char wbr; -+ struct super_block *sb; -+ struct file *file, *h_file; -+ -+ file = kio->ki_filp; -+ sb = file->f_dentry->d_sb; -+ si_read_lock(sb, AuLock_FLUSH); -+ fi_read_lock(file); -+ bstart = au_fbstart(file); -+ h_file = au_hf_top(file); -+ fi_read_unlock(file); -+ wbr = !!au_br_writable(au_sbr(sb, bstart)->br_perm); -+ si_read_unlock(sb); -+ -+ /* do not change the file in kio */ -+ AuDebugOn(!h_file->f_op || !h_file->f_op->aio_write); -+ err = h_file->f_op->aio_write(kio, iov, nv, pos); -+ if (err > 0 && wbr) -+ file_update_time(h_file); -+ -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int aufs_release_sp(struct inode *inode, struct file *file) -+{ -+ int err; -+ struct file *h_file; -+ -+ fi_read_lock(file); -+ h_file = au_hf_top(file); -+ fi_read_unlock(file); -+ /* close this fifo in aufs */ -+ err = h_file->f_op->release(inode, file); /* ignore */ -+ aufs_release_nondir(inode, file); /* ignore */ -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* currently, support only FIFO */ -+enum { -+ AuSp_FIFO, AuSp_FIFO_R, AuSp_FIFO_W, AuSp_FIFO_RW, -+ /* AuSp_SOCK, AuSp_CHR, AuSp_BLK, */ -+ AuSp_Last -+}; -+static int aufs_open_sp(struct inode *inode, struct file *file); -+static struct au_sp_fop { -+ int done; -+ struct file_operations fop; /* not 'const' */ -+ spinlock_t spin; -+} au_sp_fop[AuSp_Last] = { -+ [AuSp_FIFO] = { -+ .fop = { -+ .owner = THIS_MODULE, -+ .open = aufs_open_sp -+ } -+ } -+}; -+ -+static void au_init_fop_sp(struct file *file) -+{ -+ struct au_sp_fop *p; -+ int i; -+ struct file *h_file; -+ -+ p = au_sp_fop; -+ if (unlikely(!p->done)) { -+ /* initialize first time only */ -+ static DEFINE_SPINLOCK(spin); -+ -+ spin_lock(&spin); -+ if (!p->done) { -+ BUILD_BUG_ON(sizeof(au_sp_fop)/sizeof(*au_sp_fop) -+ != AuSp_Last); -+ for (i = 0; i < AuSp_Last; i++) -+ spin_lock_init(&p[i].spin); -+ p->done = 1; -+ } -+ spin_unlock(&spin); -+ } -+ -+ switch (file->f_mode & (FMODE_READ | FMODE_WRITE)) { -+ case FMODE_READ: -+ i = AuSp_FIFO_R; -+ break; -+ case FMODE_WRITE: -+ i = AuSp_FIFO_W; -+ break; -+ case FMODE_READ | FMODE_WRITE: -+ i = AuSp_FIFO_RW; -+ break; -+ default: -+ BUG(); -+ } -+ -+ p += i; -+ if (unlikely(!p->done)) { -+ /* initialize first time only */ -+ h_file = au_hf_top(file); -+ spin_lock(&p->spin); -+ if (!p->done) { -+ p->fop = *h_file->f_op; -+ p->fop.owner = THIS_MODULE; -+ if (p->fop.aio_read) -+ p->fop.aio_read = aufs_aio_read_sp; -+ if (p->fop.aio_write) -+ p->fop.aio_write = aufs_aio_write_sp; -+ p->fop.release = aufs_release_sp; -+ p->done = 1; -+ } -+ spin_unlock(&p->spin); -+ } -+ file->f_op = &p->fop; -+} -+ -+static int au_cpup_sp(struct dentry *dentry) -+{ -+ int err; -+ aufs_bindex_t bcpup; -+ struct au_pin pin; -+ struct au_wr_dir_args wr_dir_args = { -+ .force_btgt = -1, -+ .flags = 0 -+ }; -+ -+ AuDbg("%.*s\n", AuDLNPair(dentry)); -+ -+ di_read_unlock(dentry, AuLock_IR); -+ di_write_lock_child(dentry); -+ err = au_wr_dir(dentry, /*src_dentry*/NULL, &wr_dir_args); -+ if (unlikely(err < 0)) -+ goto out; -+ bcpup = err; -+ err = 0; -+ if (bcpup == au_dbstart(dentry)) -+ goto out; /* success */ -+ -+ err = au_pin(&pin, dentry, bcpup, au_opt_udba(dentry->d_sb), -+ AuPin_MNT_WRITE); -+ if (!err) { -+ err = au_sio_cpup_simple(dentry, bcpup, -1, AuCpup_DTIME); -+ au_unpin(&pin); -+ } -+ -+out: -+ di_downgrade_lock(dentry, AuLock_IR); -+ return err; -+} -+ -+static int au_do_open_sp(struct file *file, int flags) -+{ -+ int err; -+ struct dentry *dentry; -+ struct super_block *sb; -+ struct file *h_file; -+ struct inode *h_inode; -+ -+ dentry = file->f_dentry; -+ AuDbg("%.*s\n", AuDLNPair(dentry)); -+ -+ /* -+ * try copying-up. -+ * operate on the ro branch is not an error. -+ */ -+ au_cpup_sp(dentry); /* ignore */ -+ -+ /* prepare h_file */ -+ err = au_do_open_nondir(file, vfsub_file_flags(file)); -+ if (unlikely(err)) -+ goto out; -+ -+ sb = dentry->d_sb; -+ h_file = au_hf_top(file); -+ h_inode = h_file->f_dentry->d_inode; -+ di_read_unlock(dentry, AuLock_IR); -+ fi_write_unlock(file); -+ si_read_unlock(sb); -+ /* open this fifo in aufs */ -+ err = h_inode->i_fop->open(file->f_dentry->d_inode, file); -+ si_noflush_read_lock(sb); -+ fi_write_lock(file); -+ di_read_lock_child(dentry, AuLock_IR); -+ if (!err) -+ au_init_fop_sp(file); -+ -+out: -+ return err; -+} -+ -+static int aufs_open_sp(struct inode *inode, struct file *file) -+{ -+ int err; -+ struct super_block *sb; -+ -+ sb = file->f_dentry->d_sb; -+ si_read_lock(sb, AuLock_FLUSH); -+ err = au_do_open(file, au_do_open_sp, /*fidir*/NULL); -+ si_read_unlock(sb); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+void au_init_special_fop(struct inode *inode, umode_t mode, dev_t rdev) -+{ -+ init_special_inode(inode, mode, rdev); -+ -+ switch (mode & S_IFMT) { -+ case S_IFIFO: -+ inode->i_fop = &au_sp_fop[AuSp_FIFO].fop; -+ /*FALLTHROUGH*/ -+ case S_IFCHR: -+ case S_IFBLK: -+ case S_IFSOCK: -+ break; -+ default: -+ AuDebugOn(1); -+ } -+} -+ -+int au_special_file(umode_t mode) -+{ -+ int ret; -+ -+ ret = 0; -+ switch (mode & S_IFMT) { -+ case S_IFIFO: -+#if 0 -+ case S_IFCHR: -+ case S_IFBLK: -+ case S_IFSOCK: -+#endif -+ ret = 1; -+ } -+ -+ return ret; -+} -diff -Nur linux-2.6.36.orig/fs/aufs/file.c linux-2.6.36/fs/aufs/file.c ---- linux-2.6.36.orig/fs/aufs/file.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/file.c 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,676 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * handling file/dir, and address_space operation -+ */ -+ -+#include -+#include -+#include -+#include -+#include "aufs.h" -+ -+/* drop flags for writing */ -+unsigned int au_file_roflags(unsigned int flags) -+{ -+ flags &= ~(O_WRONLY | O_RDWR | O_APPEND | O_CREAT | O_TRUNC); -+ flags |= O_RDONLY | O_NOATIME; -+ return flags; -+} -+ -+/* common functions to regular file and dir */ -+struct file *au_h_open(struct dentry *dentry, aufs_bindex_t bindex, int flags, -+ struct file *file) -+{ -+ struct file *h_file; -+ struct dentry *h_dentry; -+ struct inode *h_inode; -+ struct super_block *sb; -+ struct au_branch *br; -+ struct path h_path; -+ int err, exec_flag; -+ -+ /* a race condition can happen between open and unlink/rmdir */ -+ h_file = ERR_PTR(-ENOENT); -+ h_dentry = au_h_dptr(dentry, bindex); -+ if (au_test_nfsd() && !h_dentry) -+ goto out; -+ h_inode = h_dentry->d_inode; -+ if (au_test_nfsd() && !h_inode) -+ goto out; -+ if (unlikely((!d_unhashed(dentry) && au_d_removed(h_dentry)) -+ || !h_inode -+ /* || !dentry->d_inode->i_nlink */ -+ )) -+ goto out; -+ -+ sb = dentry->d_sb; -+ br = au_sbr(sb, bindex); -+ h_file = ERR_PTR(-EACCES); -+ exec_flag = flags & vfsub_fmode_to_uint(FMODE_EXEC); -+ if (exec_flag && (br->br_mnt->mnt_flags & MNT_NOEXEC)) -+ goto out; -+ -+ /* drop flags for writing */ -+ if (au_test_ro(sb, bindex, dentry->d_inode)) -+ flags = au_file_roflags(flags); -+ flags &= ~O_CREAT; -+ atomic_inc(&br->br_count); -+ h_path.dentry = h_dentry; -+ h_path.mnt = br->br_mnt; -+ if (!au_special_file(h_inode->i_mode)) -+ h_file = vfsub_dentry_open(&h_path, flags); -+ else { -+ /* this block depends upon the configuration */ -+ di_read_unlock(dentry, AuLock_IR); -+ fi_write_unlock(file); -+ si_read_unlock(sb); -+ h_file = vfsub_dentry_open(&h_path, flags); -+ si_noflush_read_lock(sb); -+ fi_write_lock(file); -+ di_read_lock_child(dentry, AuLock_IR); -+ } -+ if (IS_ERR(h_file)) -+ goto out_br; -+ -+ if (exec_flag) { -+ err = deny_write_access(h_file); -+ if (unlikely(err)) { -+ fput(h_file); -+ h_file = ERR_PTR(err); -+ goto out_br; -+ } -+ } -+ fsnotify_open(h_file); -+ goto out; /* success */ -+ -+out_br: -+ atomic_dec(&br->br_count); -+out: -+ return h_file; -+} -+ -+int au_do_open(struct file *file, int (*open)(struct file *file, int flags), -+ struct au_fidir *fidir) -+{ -+ int err; -+ struct dentry *dentry; -+ -+ err = au_finfo_init(file, fidir); -+ if (unlikely(err)) -+ goto out; -+ -+ dentry = file->f_dentry; -+ di_read_lock_child(dentry, AuLock_IR); -+ err = open(file, vfsub_file_flags(file)); -+ di_read_unlock(dentry, AuLock_IR); -+ -+ fi_write_unlock(file); -+ if (unlikely(err)) { -+ au_fi(file)->fi_hdir = NULL; -+ au_finfo_fin(file); -+ } -+ -+out: -+ return err; -+} -+ -+int au_reopen_nondir(struct file *file) -+{ -+ int err; -+ aufs_bindex_t bstart; -+ struct dentry *dentry; -+ struct file *h_file, *h_file_tmp; -+ -+ dentry = file->f_dentry; -+ AuDebugOn(au_special_file(dentry->d_inode->i_mode)); -+ bstart = au_dbstart(dentry); -+ h_file_tmp = NULL; -+ if (au_fbstart(file) == bstart) { -+ h_file = au_hf_top(file); -+ if (file->f_mode == h_file->f_mode) -+ return 0; /* success */ -+ h_file_tmp = h_file; -+ get_file(h_file_tmp); -+ au_set_h_fptr(file, bstart, NULL); -+ } -+ AuDebugOn(au_fi(file)->fi_hdir); -+ AuDebugOn(au_fbstart(file) < bstart); -+ -+ h_file = au_h_open(dentry, bstart, vfsub_file_flags(file) & ~O_TRUNC, -+ file); -+ err = PTR_ERR(h_file); -+ if (IS_ERR(h_file)) -+ goto out; /* todo: close all? */ -+ -+ err = 0; -+ au_set_fbstart(file, bstart); -+ au_set_h_fptr(file, bstart, h_file); -+ au_update_figen(file); -+ /* todo: necessary? */ -+ /* file->f_ra = h_file->f_ra; */ -+ -+out: -+ if (h_file_tmp) -+ fput(h_file_tmp); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int au_reopen_wh(struct file *file, aufs_bindex_t btgt, -+ struct dentry *hi_wh) -+{ -+ int err; -+ aufs_bindex_t bstart; -+ struct au_dinfo *dinfo; -+ struct dentry *h_dentry; -+ struct au_hdentry *hdp; -+ -+ dinfo = au_di(file->f_dentry); -+ AuRwMustWriteLock(&dinfo->di_rwsem); -+ -+ bstart = dinfo->di_bstart; -+ dinfo->di_bstart = btgt; -+ hdp = dinfo->di_hdentry; -+ h_dentry = hdp[0 + btgt].hd_dentry; -+ hdp[0 + btgt].hd_dentry = hi_wh; -+ err = au_reopen_nondir(file); -+ hdp[0 + btgt].hd_dentry = h_dentry; -+ dinfo->di_bstart = bstart; -+ -+ return err; -+} -+ -+static int au_ready_to_write_wh(struct file *file, loff_t len, -+ aufs_bindex_t bcpup) -+{ -+ int err; -+ struct inode *inode, *h_inode; -+ struct dentry *dentry, *h_dentry, *hi_wh; -+ -+ dentry = file->f_dentry; -+ au_update_dbstart(dentry); -+ inode = dentry->d_inode; -+ h_inode = NULL; -+ if (au_dbstart(dentry) <= bcpup && au_dbend(dentry) >= bcpup) { -+ h_dentry = au_h_dptr(dentry, bcpup); -+ if (h_dentry) -+ h_inode = h_dentry->d_inode; -+ } -+ hi_wh = au_hi_wh(inode, bcpup); -+ if (!hi_wh && !h_inode) -+ err = au_sio_cpup_wh(dentry, bcpup, len, file); -+ else -+ /* already copied-up after unlink */ -+ err = au_reopen_wh(file, bcpup, hi_wh); -+ -+ if (!err -+ && inode->i_nlink > 1 -+ && au_opt_test(au_mntflags(dentry->d_sb), PLINK)) -+ au_plink_append(inode, bcpup, au_h_dptr(dentry, bcpup)); -+ -+ return err; -+} -+ -+/* -+ * prepare the @file for writing. -+ */ -+int au_ready_to_write(struct file *file, loff_t len, struct au_pin *pin) -+{ -+ int err; -+ aufs_bindex_t bstart, bcpup, dbstart; -+ struct dentry *dentry, *parent, *h_dentry; -+ struct inode *h_inode, *inode; -+ struct super_block *sb; -+ struct file *h_file; -+ -+ dentry = file->f_dentry; -+ sb = dentry->d_sb; -+ inode = dentry->d_inode; -+ AuDebugOn(au_special_file(inode->i_mode)); -+ bstart = au_fbstart(file); -+ err = au_test_ro(sb, bstart, inode); -+ if (!err && (au_hf_top(file)->f_mode & FMODE_WRITE)) { -+ err = au_pin(pin, dentry, bstart, AuOpt_UDBA_NONE, /*flags*/0); -+ goto out; -+ } -+ -+ /* need to cpup or reopen */ -+ parent = dget_parent(dentry); -+ di_write_lock_parent(parent); -+ err = AuWbrCopyup(au_sbi(sb), dentry); -+ bcpup = err; -+ if (unlikely(err < 0)) -+ goto out_dgrade; -+ err = 0; -+ -+ if (!d_unhashed(dentry) && !au_h_dptr(parent, bcpup)) { -+ err = au_cpup_dirs(dentry, bcpup); -+ if (unlikely(err)) -+ goto out_dgrade; -+ } -+ -+ err = au_pin(pin, dentry, bcpup, AuOpt_UDBA_NONE, -+ AuPin_DI_LOCKED | AuPin_MNT_WRITE); -+ if (unlikely(err)) -+ goto out_dgrade; -+ -+ h_dentry = au_hf_top(file)->f_dentry; -+ h_inode = h_dentry->d_inode; -+ dbstart = au_dbstart(dentry); -+ if (dbstart <= bcpup) { -+ h_dentry = au_h_dptr(dentry, bcpup); -+ AuDebugOn(!h_dentry); -+ h_inode = h_dentry->d_inode; -+ AuDebugOn(!h_inode); -+ bstart = bcpup; -+ } -+ -+ if (dbstart <= bcpup /* just reopen */ -+ || !d_unhashed(dentry) /* copyup and reopen */ -+ ) { -+ mutex_lock_nested(&h_inode->i_mutex, AuLsc_I_CHILD); -+ h_file = au_h_open_pre(dentry, bstart); -+ if (IS_ERR(h_file)) { -+ err = PTR_ERR(h_file); -+ h_file = NULL; -+ } else { -+ di_downgrade_lock(parent, AuLock_IR); -+ if (dbstart > bcpup) -+ err = au_sio_cpup_simple(dentry, bcpup, len, -+ AuCpup_DTIME); -+ if (!err) -+ err = au_reopen_nondir(file); -+ } -+ mutex_unlock(&h_inode->i_mutex); -+ au_h_open_post(dentry, bstart, h_file); -+ } else { /* copyup as wh and reopen */ -+ /* -+ * since writable hfsplus branch is not supported, -+ * h_open_pre/post() are unnecessary. -+ */ -+ mutex_lock_nested(&h_inode->i_mutex, AuLsc_I_CHILD); -+ err = au_ready_to_write_wh(file, len, bcpup); -+ di_downgrade_lock(parent, AuLock_IR); -+ mutex_unlock(&h_inode->i_mutex); -+ } -+ -+ if (!err) { -+ au_pin_set_parent_lflag(pin, /*lflag*/0); -+ goto out_dput; /* success */ -+ } -+ au_unpin(pin); -+ goto out_unlock; -+ -+out_dgrade: -+ di_downgrade_lock(parent, AuLock_IR); -+out_unlock: -+ di_read_unlock(parent, AuLock_IR); -+out_dput: -+ dput(parent); -+out: -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+int au_do_flush(struct file *file, fl_owner_t id, -+ int (*flush)(struct file *file, fl_owner_t id)) -+{ -+ int err; -+ struct dentry *dentry; -+ struct super_block *sb; -+ struct inode *inode; -+ -+ dentry = file->f_dentry; -+ sb = dentry->d_sb; -+ inode = dentry->d_inode; -+ si_noflush_read_lock(sb); -+ fi_read_lock(file); -+ ii_read_lock_child(inode); -+ -+ err = flush(file, id); -+ au_cpup_attr_timesizes(inode); -+ -+ ii_read_unlock(inode); -+ fi_read_unlock(file); -+ si_read_unlock(sb); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int au_file_refresh_by_inode(struct file *file, int *need_reopen) -+{ -+ int err; -+ aufs_bindex_t bstart; -+ struct au_pin pin; -+ struct au_finfo *finfo; -+ struct dentry *dentry, *parent, *hi_wh; -+ struct inode *inode; -+ struct super_block *sb; -+ -+ FiMustWriteLock(file); -+ -+ err = 0; -+ finfo = au_fi(file); -+ dentry = file->f_dentry; -+ sb = dentry->d_sb; -+ inode = dentry->d_inode; -+ bstart = au_ibstart(inode); -+ if (bstart == finfo->fi_btop || IS_ROOT(dentry)) -+ goto out; -+ -+ parent = dget_parent(dentry); -+ if (au_test_ro(sb, bstart, inode)) { -+ di_read_lock_parent(parent, !AuLock_IR); -+ err = AuWbrCopyup(au_sbi(sb), dentry); -+ bstart = err; -+ di_read_unlock(parent, !AuLock_IR); -+ if (unlikely(err < 0)) -+ goto out_parent; -+ err = 0; -+ } -+ -+ di_read_lock_parent(parent, AuLock_IR); -+ hi_wh = au_hi_wh(inode, bstart); -+ if (!S_ISDIR(inode->i_mode) -+ && au_opt_test(au_mntflags(sb), PLINK) -+ && au_plink_test(inode) -+ && !d_unhashed(dentry)) { -+ err = au_test_and_cpup_dirs(dentry, bstart); -+ if (unlikely(err)) -+ goto out_unlock; -+ -+ /* always superio. */ -+ err = au_pin(&pin, dentry, bstart, AuOpt_UDBA_NONE, -+ AuPin_DI_LOCKED | AuPin_MNT_WRITE); -+ if (!err) -+ err = au_sio_cpup_simple(dentry, bstart, -1, -+ AuCpup_DTIME); -+ au_unpin(&pin); -+ } else if (hi_wh) { -+ /* already copied-up after unlink */ -+ err = au_reopen_wh(file, bstart, hi_wh); -+ *need_reopen = 0; -+ } -+ -+out_unlock: -+ di_read_unlock(parent, AuLock_IR); -+out_parent: -+ dput(parent); -+out: -+ return err; -+} -+ -+static void au_do_refresh_dir(struct file *file) -+{ -+ aufs_bindex_t bindex, bend, new_bindex, brid; -+ struct au_hfile *p, tmp, *q; -+ struct au_finfo *finfo; -+ struct super_block *sb; -+ struct au_fidir *fidir; -+ -+ FiMustWriteLock(file); -+ -+ sb = file->f_dentry->d_sb; -+ finfo = au_fi(file); -+ fidir = finfo->fi_hdir; -+ AuDebugOn(!fidir); -+ p = fidir->fd_hfile + finfo->fi_btop; -+ brid = p->hf_br->br_id; -+ bend = fidir->fd_bbot; -+ for (bindex = finfo->fi_btop; bindex <= bend; bindex++, p++) { -+ if (!p->hf_file) -+ continue; -+ -+ new_bindex = au_br_index(sb, p->hf_br->br_id); -+ if (new_bindex == bindex) -+ continue; -+ if (new_bindex < 0) { -+ au_set_h_fptr(file, bindex, NULL); -+ continue; -+ } -+ -+ /* swap two lower inode, and loop again */ -+ q = fidir->fd_hfile + new_bindex; -+ tmp = *q; -+ *q = *p; -+ *p = tmp; -+ if (tmp.hf_file) { -+ bindex--; -+ p--; -+ } -+ } -+ -+ p = fidir->fd_hfile; -+ if (!au_test_mmapped(file) && !au_d_removed(file->f_dentry)) { -+ bend = au_sbend(sb); -+ for (finfo->fi_btop = 0; finfo->fi_btop <= bend; -+ finfo->fi_btop++, p++) -+ if (p->hf_file) { -+ if (p->hf_file->f_dentry -+ && p->hf_file->f_dentry->d_inode) -+ break; -+ else -+ au_hfput(p, file); -+ } -+ } else { -+ bend = au_br_index(sb, brid); -+ for (finfo->fi_btop = 0; finfo->fi_btop < bend; -+ finfo->fi_btop++, p++) -+ if (p->hf_file) -+ au_hfput(p, file); -+ bend = au_sbend(sb); -+ } -+ -+ p = fidir->fd_hfile + bend; -+ for (fidir->fd_bbot = bend; fidir->fd_bbot >= finfo->fi_btop; -+ fidir->fd_bbot--, p--) -+ if (p->hf_file) { -+ if (p->hf_file->f_dentry -+ && p->hf_file->f_dentry->d_inode) -+ break; -+ else -+ au_hfput(p, file); -+ } -+ AuDebugOn(fidir->fd_bbot < finfo->fi_btop); -+} -+ -+/* -+ * after branch manipulating, refresh the file. -+ */ -+static int refresh_file(struct file *file, int (*reopen)(struct file *file)) -+{ -+ int err, need_reopen; -+ aufs_bindex_t bend, bindex; -+ struct dentry *dentry; -+ struct au_finfo *finfo; -+ struct au_hfile *hfile; -+ -+ dentry = file->f_dentry; -+ finfo = au_fi(file); -+ if (!finfo->fi_hdir) { -+ hfile = &finfo->fi_htop; -+ AuDebugOn(!hfile->hf_file); -+ bindex = au_br_index(dentry->d_sb, hfile->hf_br->br_id); -+ AuDebugOn(bindex < 0); -+ if (bindex != finfo->fi_btop) -+ au_set_fbstart(file, bindex); -+ } else { -+ err = au_fidir_realloc(finfo, au_sbend(dentry->d_sb) + 1); -+ if (unlikely(err)) -+ goto out; -+ au_do_refresh_dir(file); -+ } -+ -+ err = 0; -+ need_reopen = 1; -+ if (!au_test_mmapped(file)) -+ err = au_file_refresh_by_inode(file, &need_reopen); -+ if (!err && need_reopen && !au_d_removed(dentry)) -+ err = reopen(file); -+ if (!err) { -+ au_update_figen(file); -+ goto out; /* success */ -+ } -+ -+ /* error, close all lower files */ -+ if (finfo->fi_hdir) { -+ bend = au_fbend_dir(file); -+ for (bindex = au_fbstart(file); bindex <= bend; bindex++) -+ au_set_h_fptr(file, bindex, NULL); -+ } -+ -+out: -+ return err; -+} -+ -+/* common function to regular file and dir */ -+int au_reval_and_lock_fdi(struct file *file, int (*reopen)(struct file *file), -+ int wlock) -+{ -+ int err; -+ unsigned int sigen, figen; -+ aufs_bindex_t bstart; -+ unsigned char pseudo_link; -+ struct dentry *dentry; -+ struct inode *inode; -+ -+ err = 0; -+ dentry = file->f_dentry; -+ inode = dentry->d_inode; -+ AuDebugOn(au_special_file(inode->i_mode)); -+ sigen = au_sigen(dentry->d_sb); -+ fi_write_lock(file); -+ figen = au_figen(file); -+ di_write_lock_child(dentry); -+ bstart = au_dbstart(dentry); -+ pseudo_link = (bstart != au_ibstart(inode)); -+ if (sigen == figen && !pseudo_link && au_fbstart(file) == bstart) { -+ if (!wlock) { -+ di_downgrade_lock(dentry, AuLock_IR); -+ fi_downgrade_lock(file); -+ } -+ goto out; /* success */ -+ } -+ -+ AuDbg("sigen %d, figen %d\n", sigen, figen); -+ if (au_digen_test(dentry, sigen)) { -+ err = au_reval_dpath(dentry, sigen); -+ AuDebugOn(!err && au_digen_test(dentry, sigen)); -+ } -+ -+ if (!err) -+ err = refresh_file(file, reopen); -+ if (!err) { -+ if (!wlock) { -+ di_downgrade_lock(dentry, AuLock_IR); -+ fi_downgrade_lock(file); -+ } -+ } else { -+ di_write_unlock(dentry); -+ fi_write_unlock(file); -+ } -+ -+out: -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* cf. aufs_nopage() */ -+/* for madvise(2) */ -+static int aufs_readpage(struct file *file __maybe_unused, struct page *page) -+{ -+ unlock_page(page); -+ return 0; -+} -+ -+/* it will never be called, but necessary to support O_DIRECT */ -+static ssize_t aufs_direct_IO(int rw, struct kiocb *iocb, -+ const struct iovec *iov, loff_t offset, -+ unsigned long nr_segs) -+{ BUG(); return 0; } -+ -+/* -+ * it will never be called, but madvise and fadvise behaves differently -+ * when get_xip_mem is defined -+ */ -+static int aufs_get_xip_mem(struct address_space *mapping, pgoff_t pgoff, -+ int create, void **kmem, unsigned long *pfn) -+{ BUG(); return 0; } -+ -+/* they will never be called. */ -+#ifdef CONFIG_AUFS_DEBUG -+static int aufs_write_begin(struct file *file, struct address_space *mapping, -+ loff_t pos, unsigned len, unsigned flags, -+ struct page **pagep, void **fsdata) -+{ AuUnsupport(); return 0; } -+static int aufs_write_end(struct file *file, struct address_space *mapping, -+ loff_t pos, unsigned len, unsigned copied, -+ struct page *page, void *fsdata) -+{ AuUnsupport(); return 0; } -+static int aufs_writepage(struct page *page, struct writeback_control *wbc) -+{ AuUnsupport(); return 0; } -+static void aufs_sync_page(struct page *page) -+{ AuUnsupport(); } -+ -+static int aufs_set_page_dirty(struct page *page) -+{ AuUnsupport(); return 0; } -+static void aufs_invalidatepage(struct page *page, unsigned long offset) -+{ AuUnsupport(); } -+static int aufs_releasepage(struct page *page, gfp_t gfp) -+{ AuUnsupport(); return 0; } -+static int aufs_migratepage(struct address_space *mapping, struct page *newpage, -+ struct page *page) -+{ AuUnsupport(); return 0; } -+static int aufs_launder_page(struct page *page) -+{ AuUnsupport(); return 0; } -+static int aufs_is_partially_uptodate(struct page *page, -+ read_descriptor_t *desc, -+ unsigned long from) -+{ AuUnsupport(); return 0; } -+static int aufs_error_remove_page(struct address_space *mapping, -+ struct page *page) -+{ AuUnsupport(); return 0; } -+#endif /* CONFIG_AUFS_DEBUG */ -+ -+const struct address_space_operations aufs_aop = { -+ .readpage = aufs_readpage, -+ .direct_IO = aufs_direct_IO, -+ .get_xip_mem = aufs_get_xip_mem, -+#ifdef CONFIG_AUFS_DEBUG -+ .writepage = aufs_writepage, -+ .sync_page = aufs_sync_page, -+ /* no writepages, because of writepage */ -+ .set_page_dirty = aufs_set_page_dirty, -+ /* no readpages, because of readpage */ -+ .write_begin = aufs_write_begin, -+ .write_end = aufs_write_end, -+ /* no bmap, no block device */ -+ .invalidatepage = aufs_invalidatepage, -+ .releasepage = aufs_releasepage, -+ .migratepage = aufs_migratepage, -+ .launder_page = aufs_launder_page, -+ .is_partially_uptodate = aufs_is_partially_uptodate, -+ .error_remove_page = aufs_error_remove_page -+#endif /* CONFIG_AUFS_DEBUG */ -+}; -diff -Nur linux-2.6.36.orig/fs/aufs/file.h linux-2.6.36/fs/aufs/file.h ---- linux-2.6.36.orig/fs/aufs/file.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/file.h 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,238 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * file operations -+ */ -+ -+#ifndef __AUFS_FILE_H__ -+#define __AUFS_FILE_H__ -+ -+#ifdef __KERNEL__ -+ -+#include -+#include -+#include -+#include "rwsem.h" -+ -+struct au_branch; -+struct au_hfile { -+ struct file *hf_file; -+ struct au_branch *hf_br; -+}; -+ -+struct au_vdir; -+struct au_fidir { -+ aufs_bindex_t fd_bbot; -+ aufs_bindex_t fd_nent; -+ struct au_vdir *fd_vdir_cache; -+ struct au_hfile fd_hfile[]; -+}; -+ -+static inline int au_fidir_sz(int nent) -+{ -+ AuDebugOn(nent < 0); -+ return sizeof(struct au_fidir) + sizeof(struct au_hfile) * nent; -+} -+ -+struct au_finfo { -+ atomic_t fi_generation; -+ -+ struct au_rwsem fi_rwsem; -+ aufs_bindex_t fi_btop; -+ -+ /* do not union them */ -+ struct { /* for non-dir */ -+ struct au_hfile fi_htop; -+ struct vm_operations_struct *fi_hvmop; -+ struct mutex fi_vm_mtx; -+ struct mutex fi_mmap; -+ }; -+ struct au_fidir *fi_hdir; /* for dir only */ -+} ____cacheline_aligned_in_smp; -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* file.c */ -+extern const struct address_space_operations aufs_aop; -+unsigned int au_file_roflags(unsigned int flags); -+struct file *au_h_open(struct dentry *dentry, aufs_bindex_t bindex, int flags, -+ struct file *file); -+int au_do_open(struct file *file, int (*open)(struct file *file, int flags), -+ struct au_fidir *fidir); -+int au_reopen_nondir(struct file *file); -+struct au_pin; -+int au_ready_to_write(struct file *file, loff_t len, struct au_pin *pin); -+int au_reval_and_lock_fdi(struct file *file, int (*reopen)(struct file *file), -+ int wlock); -+int au_do_flush(struct file *file, fl_owner_t id, -+ int (*flush)(struct file *file, fl_owner_t id)); -+ -+/* poll.c */ -+#ifdef CONFIG_AUFS_POLL -+unsigned int aufs_poll(struct file *file, poll_table *wait); -+#endif -+ -+#ifdef CONFIG_AUFS_BR_HFSPLUS -+/* hfsplus.c */ -+struct file *au_h_open_pre(struct dentry *dentry, aufs_bindex_t bindex); -+void au_h_open_post(struct dentry *dentry, aufs_bindex_t bindex, -+ struct file *h_file); -+#else -+static inline -+struct file *au_h_open_pre(struct dentry *dentry, aufs_bindex_t bindex) -+{ -+ return NULL; -+} -+ -+AuStubVoid(au_h_open_post, struct dentry *dentry, aufs_bindex_t bindex, -+ struct file *h_file); -+#endif -+ -+/* f_op.c */ -+extern const struct file_operations aufs_file_fop; -+extern const struct vm_operations_struct aufs_vm_ops; -+int au_do_open_nondir(struct file *file, int flags); -+int aufs_release_nondir(struct inode *inode __maybe_unused, struct file *file); -+ -+#ifdef CONFIG_AUFS_SP_IATTR -+/* f_op_sp.c */ -+int au_special_file(umode_t mode); -+void au_init_special_fop(struct inode *inode, umode_t mode, dev_t rdev); -+#else -+AuStubInt0(au_special_file, umode_t mode) -+static inline void au_init_special_fop(struct inode *inode, umode_t mode, -+ dev_t rdev) -+{ -+ init_special_inode(inode, mode, rdev); -+} -+#endif -+ -+/* finfo.c */ -+void au_hfput(struct au_hfile *hf, struct file *file); -+void au_set_h_fptr(struct file *file, aufs_bindex_t bindex, -+ struct file *h_file); -+ -+void au_update_figen(struct file *file); -+void au_fi_mmap_lock(struct file *file); -+void au_fi_mmap_unlock(struct file *file); -+struct au_fidir *au_fidir_alloc(struct super_block *sb); -+int au_fidir_realloc(struct au_finfo *finfo, int nbr); -+ -+void au_fi_init_once(void *_fi); -+void au_finfo_fin(struct file *file); -+int au_finfo_init(struct file *file, struct au_fidir *fidir); -+ -+/* ioctl.c */ -+long aufs_ioctl_nondir(struct file *file, unsigned int cmd, unsigned long arg); -+#ifdef CONFIG_COMPAT -+long aufs_compat_ioctl_dir(struct file *file, unsigned int cmd, -+ unsigned long arg); -+#endif -+ -+/* ---------------------------------------------------------------------- */ -+ -+static inline struct au_finfo *au_fi(struct file *file) -+{ -+ return file->private_data; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * fi_read_lock, fi_write_lock, -+ * fi_read_unlock, fi_write_unlock, fi_downgrade_lock -+ */ -+AuSimpleRwsemFuncs(fi, struct file *f, &au_fi(f)->fi_rwsem); -+ -+#define FiMustNoWaiters(f) AuRwMustNoWaiters(&au_fi(f)->fi_rwsem) -+#define FiMustAnyLock(f) AuRwMustAnyLock(&au_fi(f)->fi_rwsem) -+#define FiMustWriteLock(f) AuRwMustWriteLock(&au_fi(f)->fi_rwsem) -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* todo: hard/soft set? */ -+static inline aufs_bindex_t au_fbstart(struct file *file) -+{ -+ FiMustAnyLock(file); -+ return au_fi(file)->fi_btop; -+} -+ -+static inline aufs_bindex_t au_fbend_dir(struct file *file) -+{ -+ FiMustAnyLock(file); -+ AuDebugOn(!au_fi(file)->fi_hdir); -+ return au_fi(file)->fi_hdir->fd_bbot; -+} -+ -+static inline struct au_vdir *au_fvdir_cache(struct file *file) -+{ -+ FiMustAnyLock(file); -+ AuDebugOn(!au_fi(file)->fi_hdir); -+ return au_fi(file)->fi_hdir->fd_vdir_cache; -+} -+ -+static inline void au_set_fbstart(struct file *file, aufs_bindex_t bindex) -+{ -+ FiMustWriteLock(file); -+ au_fi(file)->fi_btop = bindex; -+} -+ -+static inline void au_set_fbend_dir(struct file *file, aufs_bindex_t bindex) -+{ -+ FiMustWriteLock(file); -+ AuDebugOn(!au_fi(file)->fi_hdir); -+ au_fi(file)->fi_hdir->fd_bbot = bindex; -+} -+ -+static inline void au_set_fvdir_cache(struct file *file, -+ struct au_vdir *vdir_cache) -+{ -+ FiMustWriteLock(file); -+ AuDebugOn(!au_fi(file)->fi_hdir); -+ au_fi(file)->fi_hdir->fd_vdir_cache = vdir_cache; -+} -+ -+static inline struct file *au_hf_top(struct file *file) -+{ -+ FiMustAnyLock(file); -+ AuDebugOn(au_fi(file)->fi_hdir); -+ return au_fi(file)->fi_htop.hf_file; -+} -+ -+static inline struct file *au_hf_dir(struct file *file, aufs_bindex_t bindex) -+{ -+ FiMustAnyLock(file); -+ AuDebugOn(!au_fi(file)->fi_hdir); -+ return au_fi(file)->fi_hdir->fd_hfile[0 + bindex].hf_file; -+} -+ -+/* todo: memory barrier? */ -+static inline unsigned int au_figen(struct file *f) -+{ -+ return atomic_read(&au_fi(f)->fi_generation); -+} -+ -+static inline int au_test_mmapped(struct file *f) -+{ -+ FiMustAnyLock(f); -+ return !!(au_fi(f)->fi_hvmop); -+} -+ -+#endif /* __KERNEL__ */ -+#endif /* __AUFS_FILE_H__ */ -diff -Nur linux-2.6.36.orig/fs/aufs/finfo.c linux-2.6.36/fs/aufs/finfo.c ---- linux-2.6.36.orig/fs/aufs/finfo.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/finfo.c 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,174 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * file private data -+ */ -+ -+#include -+#include "aufs.h" -+ -+void au_hfput(struct au_hfile *hf, struct file *file) -+{ -+ /* todo: direct access f_flags */ -+ if (vfsub_file_flags(file) & vfsub_fmode_to_uint(FMODE_EXEC)) -+ allow_write_access(hf->hf_file); -+ fput(hf->hf_file); -+ hf->hf_file = NULL; -+ atomic_dec(&hf->hf_br->br_count); -+ hf->hf_br = NULL; -+} -+ -+void au_set_h_fptr(struct file *file, aufs_bindex_t bindex, struct file *val) -+{ -+ struct au_finfo *finfo = au_fi(file); -+ struct au_hfile *hf; -+ struct au_fidir *fidir; -+ -+ fidir = finfo->fi_hdir; -+ if (!fidir) { -+ AuDebugOn(finfo->fi_btop != bindex); -+ hf = &finfo->fi_htop; -+ } else -+ hf = fidir->fd_hfile + bindex; -+ -+ if (hf && hf->hf_file) -+ au_hfput(hf, file); -+ if (val) { -+ FiMustWriteLock(file); -+ hf->hf_file = val; -+ hf->hf_br = au_sbr(file->f_dentry->d_sb, bindex); -+ } -+} -+ -+void au_update_figen(struct file *file) -+{ -+ atomic_set(&au_fi(file)->fi_generation, au_digen(file->f_dentry)); -+ /* smp_mb(); */ /* atomic_set */ -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+void au_fi_mmap_lock(struct file *file) -+{ -+ FiMustWriteLock(file); -+ lockdep_off(); -+ mutex_lock(&au_fi(file)->fi_mmap); -+ lockdep_on(); -+} -+ -+void au_fi_mmap_unlock(struct file *file) -+{ -+ lockdep_off(); -+ mutex_unlock(&au_fi(file)->fi_mmap); -+ lockdep_on(); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+struct au_fidir *au_fidir_alloc(struct super_block *sb) -+{ -+ struct au_fidir *fidir; -+ int nbr; -+ -+ nbr = au_sbend(sb) + 1; -+ if (nbr < 2) -+ nbr = 2; /* initial allocate for 2 branches */ -+ fidir = kzalloc(au_fidir_sz(nbr), GFP_NOFS); -+ if (fidir) { -+ fidir->fd_bbot = -1; -+ fidir->fd_nent = nbr; -+ fidir->fd_vdir_cache = NULL; -+ } -+ -+ return fidir; -+} -+ -+int au_fidir_realloc(struct au_finfo *finfo, int nbr) -+{ -+ int err; -+ struct au_fidir *fidir, *p; -+ -+ AuRwMustWriteLock(&finfo->fi_rwsem); -+ fidir = finfo->fi_hdir; -+ AuDebugOn(!fidir); -+ -+ err = -ENOMEM; -+ p = au_kzrealloc(fidir, au_fidir_sz(fidir->fd_nent), au_fidir_sz(nbr), -+ GFP_NOFS); -+ if (p) { -+ p->fd_nent = nbr; -+ finfo->fi_hdir = p; -+ err = 0; -+ } -+ -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+void au_finfo_fin(struct file *file) -+{ -+ struct au_finfo *finfo; -+ -+ au_nfiles_dec(file->f_dentry->d_sb); -+ -+ finfo = au_fi(file); -+ AuDebugOn(finfo->fi_hdir); -+ AuRwDestroy(&finfo->fi_rwsem); -+ au_cache_free_finfo(finfo); -+} -+ -+void au_fi_init_once(void *_finfo) -+{ -+ struct au_finfo *finfo = _finfo; -+ static struct lock_class_key aufs_fi, aufs_fi_vm, aufs_fi_mmap; -+ -+ au_rw_init(&finfo->fi_rwsem); -+ au_rw_class(&finfo->fi_rwsem, &aufs_fi); -+ mutex_init(&finfo->fi_vm_mtx); -+ lockdep_set_class(&finfo->fi_vm_mtx, &aufs_fi_vm); -+ mutex_init(&finfo->fi_mmap); -+ lockdep_set_class(&finfo->fi_mmap, &aufs_fi_mmap); -+} -+ -+int au_finfo_init(struct file *file, struct au_fidir *fidir) -+{ -+ int err; -+ struct au_finfo *finfo; -+ struct dentry *dentry; -+ -+ err = -ENOMEM; -+ dentry = file->f_dentry; -+ finfo = au_cache_alloc_finfo(); -+ if (unlikely(!finfo)) -+ goto out; -+ -+ err = 0; -+ au_nfiles_inc(dentry->d_sb); -+ au_rw_write_lock(&finfo->fi_rwsem); -+ finfo->fi_btop = -1; -+ finfo->fi_hdir = fidir; -+ atomic_set(&finfo->fi_generation, au_digen(dentry)); -+ /* smp_mb(); */ /* atomic_set */ -+ -+ file->private_data = finfo; -+ -+out: -+ return err; -+} -diff -Nur linux-2.6.36.orig/fs/aufs/fstype.h linux-2.6.36/fs/aufs/fstype.h ---- linux-2.6.36.orig/fs/aufs/fstype.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/fstype.h 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,497 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * judging filesystem type -+ */ -+ -+#ifndef __AUFS_FSTYPE_H__ -+#define __AUFS_FSTYPE_H__ -+ -+#ifdef __KERNEL__ -+ -+#include -+#include -+#include -+#include -+ -+static inline int au_test_aufs(struct super_block *sb) -+{ -+ return sb->s_magic == AUFS_SUPER_MAGIC; -+} -+ -+static inline const char *au_sbtype(struct super_block *sb) -+{ -+ return sb->s_type->name; -+} -+ -+static inline int au_test_iso9660(struct super_block *sb __maybe_unused) -+{ -+#if defined(CONFIG_ROMFS_FS) || defined(CONFIG_ROMFS_FS_MODULE) -+ return sb->s_magic == ROMFS_MAGIC; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_romfs(struct super_block *sb __maybe_unused) -+{ -+#if defined(CONFIG_ISO9660_FS) || defined(CONFIG_ISO9660_FS_MODULE) -+ return sb->s_magic == ISOFS_SUPER_MAGIC; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_cramfs(struct super_block *sb __maybe_unused) -+{ -+#if defined(CONFIG_CRAMFS) || defined(CONFIG_CRAMFS_MODULE) -+ return sb->s_magic == CRAMFS_MAGIC; -+#endif -+ return 0; -+} -+ -+static inline int au_test_nfs(struct super_block *sb __maybe_unused) -+{ -+#if defined(CONFIG_NFS_FS) || defined(CONFIG_NFS_FS_MODULE) -+ return sb->s_magic == NFS_SUPER_MAGIC; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_fuse(struct super_block *sb __maybe_unused) -+{ -+#if defined(CONFIG_FUSE_FS) || defined(CONFIG_FUSE_FS_MODULE) -+ return sb->s_magic == FUSE_SUPER_MAGIC; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_xfs(struct super_block *sb __maybe_unused) -+{ -+#if defined(CONFIG_XFS_FS) || defined(CONFIG_XFS_FS_MODULE) -+ return sb->s_magic == XFS_SB_MAGIC; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_tmpfs(struct super_block *sb __maybe_unused) -+{ -+#ifdef CONFIG_TMPFS -+ return sb->s_magic == TMPFS_MAGIC; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_ecryptfs(struct super_block *sb __maybe_unused) -+{ -+#if defined(CONFIG_ECRYPT_FS) || defined(CONFIG_ECRYPT_FS_MODULE) -+ return !strcmp(au_sbtype(sb), "ecryptfs"); -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_smbfs(struct super_block *sb __maybe_unused) -+{ -+#if defined(CONFIG_SMB_FS) || defined(CONFIG_SMB_FS_MODULE) -+ return sb->s_magic == SMB_SUPER_MAGIC; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_ocfs2(struct super_block *sb __maybe_unused) -+{ -+#if defined(CONFIG_OCFS2_FS) || defined(CONFIG_OCFS2_FS_MODULE) -+ return sb->s_magic == OCFS2_SUPER_MAGIC; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_ocfs2_dlmfs(struct super_block *sb __maybe_unused) -+{ -+#if defined(CONFIG_OCFS2_FS_O2CB) || defined(CONFIG_OCFS2_FS_O2CB_MODULE) -+ return sb->s_magic == DLMFS_MAGIC; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_coda(struct super_block *sb __maybe_unused) -+{ -+#if defined(CONFIG_CODA_FS) || defined(CONFIG_CODA_FS_MODULE) -+ return sb->s_magic == CODA_SUPER_MAGIC; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_v9fs(struct super_block *sb __maybe_unused) -+{ -+#if defined(CONFIG_9P_FS) || defined(CONFIG_9P_FS_MODULE) -+ return sb->s_magic == V9FS_MAGIC; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_ext4(struct super_block *sb __maybe_unused) -+{ -+#if defined(CONFIG_EXT4DEV_FS) || defined(CONFIG_EXT4DEV_FS_MODULE) -+ return sb->s_magic == EXT4_SUPER_MAGIC; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_sysv(struct super_block *sb __maybe_unused) -+{ -+#if defined(CONFIG_SYSV_FS) || defined(CONFIG_SYSV_FS_MODULE) -+ return !strcmp(au_sbtype(sb), "sysv"); -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_ramfs(struct super_block *sb) -+{ -+ return sb->s_magic == RAMFS_MAGIC; -+} -+ -+static inline int au_test_ubifs(struct super_block *sb __maybe_unused) -+{ -+#if defined(CONFIG_UBIFS_FS) || defined(CONFIG_UBIFS_FS_MODULE) -+ return sb->s_magic == UBIFS_SUPER_MAGIC; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_procfs(struct super_block *sb __maybe_unused) -+{ -+#ifdef CONFIG_PROC_FS -+ return sb->s_magic == PROC_SUPER_MAGIC; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_sysfs(struct super_block *sb __maybe_unused) -+{ -+#ifdef CONFIG_SYSFS -+ return sb->s_magic == SYSFS_MAGIC; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_configfs(struct super_block *sb __maybe_unused) -+{ -+#if defined(CONFIG_CONFIGFS_FS) || defined(CONFIG_CONFIGFS_FS_MODULE) -+ return sb->s_magic == CONFIGFS_MAGIC; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_minix(struct super_block *sb __maybe_unused) -+{ -+#if defined(CONFIG_MINIX_FS) || defined(CONFIG_MINIX_FS_MODULE) -+ return sb->s_magic == MINIX3_SUPER_MAGIC -+ || sb->s_magic == MINIX2_SUPER_MAGIC -+ || sb->s_magic == MINIX2_SUPER_MAGIC2 -+ || sb->s_magic == MINIX_SUPER_MAGIC -+ || sb->s_magic == MINIX_SUPER_MAGIC2; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_cifs(struct super_block *sb __maybe_unused) -+{ -+#if defined(CONFIG_CIFS_FS) || defined(CONFIGCIFS_FS_MODULE) -+ return sb->s_magic == CIFS_MAGIC_NUMBER; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_fat(struct super_block *sb __maybe_unused) -+{ -+#if defined(CONFIG_FAT_FS) || defined(CONFIG_FAT_FS_MODULE) -+ return sb->s_magic == MSDOS_SUPER_MAGIC; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_msdos(struct super_block *sb) -+{ -+ return au_test_fat(sb); -+} -+ -+static inline int au_test_vfat(struct super_block *sb) -+{ -+ return au_test_fat(sb); -+} -+ -+static inline int au_test_securityfs(struct super_block *sb __maybe_unused) -+{ -+#ifdef CONFIG_SECURITYFS -+ return sb->s_magic == SECURITYFS_MAGIC; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_squashfs(struct super_block *sb __maybe_unused) -+{ -+#if defined(CONFIG_SQUASHFS) || defined(CONFIG_SQUASHFS_MODULE) -+ return sb->s_magic == SQUASHFS_MAGIC; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_btrfs(struct super_block *sb __maybe_unused) -+{ -+#if defined(CONFIG_BTRFS_FS) || defined(CONFIG_BTRFS_FS_MODULE) -+ return sb->s_magic == BTRFS_SUPER_MAGIC; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_xenfs(struct super_block *sb __maybe_unused) -+{ -+#if defined(CONFIG_XENFS) || defined(CONFIG_XENFS_MODULE) -+ return sb->s_magic == XENFS_SUPER_MAGIC; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_debugfs(struct super_block *sb __maybe_unused) -+{ -+#ifdef CONFIG_DEBUG_FS -+ return sb->s_magic == DEBUGFS_MAGIC; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_nilfs(struct super_block *sb __maybe_unused) -+{ -+#if defined(CONFIG_NILFS) || defined(CONFIG_NILFS_MODULE) -+ return sb->s_magic == NILFS_SUPER_MAGIC; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_hfsplus(struct super_block *sb __maybe_unused) -+{ -+#if defined(CONFIG_HFSPLUS_FS) || defined(CONFIG_HFSPLUS_FS_MODULE) -+ return sb->s_magic == HFSPLUS_SUPER_MAGIC; -+#else -+ return 0; -+#endif -+} -+ -+/* ---------------------------------------------------------------------- */ -+/* -+ * they can't be an aufs branch. -+ */ -+static inline int au_test_fs_unsuppoted(struct super_block *sb) -+{ -+ return -+#ifndef CONFIG_AUFS_BR_RAMFS -+ au_test_ramfs(sb) || -+#endif -+ au_test_procfs(sb) -+ || au_test_sysfs(sb) -+ || au_test_configfs(sb) -+ || au_test_debugfs(sb) -+ || au_test_securityfs(sb) -+ || au_test_xenfs(sb) -+ || au_test_ecryptfs(sb) -+ /* || !strcmp(au_sbtype(sb), "unionfs") */ -+ || au_test_aufs(sb); /* will be supported in next version */ -+} -+ -+/* -+ * If the filesystem supports NFS-export, then it has to support NULL as -+ * a nameidata parameter for ->create(), ->lookup() and ->d_revalidate(). -+ * We can apply this principle when we handle a lower filesystem. -+ */ -+static inline int au_test_fs_null_nd(struct super_block *sb) -+{ -+ return !!sb->s_export_op; -+} -+ -+static inline int au_test_fs_remote(struct super_block *sb) -+{ -+ return !au_test_tmpfs(sb) -+#ifdef CONFIG_AUFS_BR_RAMFS -+ && !au_test_ramfs(sb) -+#endif -+ && !(sb->s_type->fs_flags & FS_REQUIRES_DEV); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * Note: these functions (below) are created after reading ->getattr() in all -+ * filesystems under linux/fs. it means we have to do so in every update... -+ */ -+ -+/* -+ * some filesystems require getattr to refresh the inode attributes before -+ * referencing. -+ * in most cases, we can rely on the inode attribute in NFS (or every remote fs) -+ * and leave the work for d_revalidate() -+ */ -+static inline int au_test_fs_refresh_iattr(struct super_block *sb) -+{ -+ return au_test_nfs(sb) -+ || au_test_fuse(sb) -+ /* || au_test_smbfs(sb) */ /* untested */ -+ /* || au_test_ocfs2(sb) */ /* untested */ -+ /* || au_test_btrfs(sb) */ /* untested */ -+ /* || au_test_coda(sb) */ /* untested */ -+ /* || au_test_v9fs(sb) */ /* untested */ -+ ; -+} -+ -+/* -+ * filesystems which don't maintain i_size or i_blocks. -+ */ -+static inline int au_test_fs_bad_iattr_size(struct super_block *sb) -+{ -+ return au_test_xfs(sb) -+ || au_test_btrfs(sb) -+ || au_test_ubifs(sb) -+ || au_test_hfsplus(sb) /* maintained, but incorrect */ -+ /* || au_test_ext4(sb) */ /* untested */ -+ /* || au_test_ocfs2(sb) */ /* untested */ -+ /* || au_test_ocfs2_dlmfs(sb) */ /* untested */ -+ /* || au_test_sysv(sb) */ /* untested */ -+ /* || au_test_minix(sb) */ /* untested */ -+ ; -+} -+ -+/* -+ * filesystems which don't store the correct value in some of their inode -+ * attributes. -+ */ -+static inline int au_test_fs_bad_iattr(struct super_block *sb) -+{ -+ return au_test_fs_bad_iattr_size(sb) -+ /* || au_test_cifs(sb) */ /* untested */ -+ || au_test_fat(sb) -+ || au_test_msdos(sb) -+ || au_test_vfat(sb); -+} -+ -+/* they don't check i_nlink in link(2) */ -+static inline int au_test_fs_no_limit_nlink(struct super_block *sb) -+{ -+ return au_test_tmpfs(sb) -+#ifdef CONFIG_AUFS_BR_RAMFS -+ || au_test_ramfs(sb) -+#endif -+ || au_test_ubifs(sb) -+ || au_test_btrfs(sb) -+ || au_test_hfsplus(sb); -+} -+ -+/* -+ * filesystems which sets S_NOATIME and S_NOCMTIME. -+ */ -+static inline int au_test_fs_notime(struct super_block *sb) -+{ -+ return au_test_nfs(sb) -+ || au_test_fuse(sb) -+ || au_test_ubifs(sb) -+ /* || au_test_cifs(sb) */ /* untested */ -+ ; -+} -+ -+/* -+ * filesystems which requires replacing i_mapping. -+ */ -+static inline int au_test_fs_bad_mapping(struct super_block *sb) -+{ -+ return au_test_fuse(sb) -+ || au_test_ubifs(sb); -+} -+ -+/* temporary support for i#1 in cramfs */ -+static inline int au_test_fs_unique_ino(struct inode *inode) -+{ -+ if (au_test_cramfs(inode->i_sb)) -+ return inode->i_ino != 1; -+ return 1; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * the filesystem where the xino files placed must support i/o after unlink and -+ * maintain i_size and i_blocks. -+ */ -+static inline int au_test_fs_bad_xino(struct super_block *sb) -+{ -+ return au_test_fs_remote(sb) -+ || au_test_fs_bad_iattr_size(sb) -+#ifdef CONFIG_AUFS_BR_RAMFS -+ || !(au_test_ramfs(sb) || au_test_fs_null_nd(sb)) -+#else -+ || !au_test_fs_null_nd(sb) /* to keep xino code simple */ -+#endif -+ /* don't want unnecessary work for xino */ -+ || au_test_aufs(sb) -+ || au_test_ecryptfs(sb) -+ || au_test_nilfs(sb); -+} -+ -+static inline int au_test_fs_trunc_xino(struct super_block *sb) -+{ -+ return au_test_tmpfs(sb) -+ || au_test_ramfs(sb); -+} -+ -+/* -+ * test if the @sb is real-readonly. -+ */ -+static inline int au_test_fs_rr(struct super_block *sb) -+{ -+ return au_test_squashfs(sb) -+ || au_test_iso9660(sb) -+ || au_test_cramfs(sb) -+ || au_test_romfs(sb); -+} -+ -+#endif /* __KERNEL__ */ -+#endif /* __AUFS_FSTYPE_H__ */ -diff -Nur linux-2.6.36.orig/fs/aufs/hfsnotify.c linux-2.6.36/fs/aufs/hfsnotify.c ---- linux-2.6.36.orig/fs/aufs/hfsnotify.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/hfsnotify.c 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,247 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * fsnotify for the lower directories -+ */ -+ -+#include "aufs.h" -+ -+/* FS_IN_IGNORED is unnecessary */ -+static const __u32 AuHfsnMask = (FS_MOVED_TO | FS_MOVED_FROM | FS_DELETE -+ | FS_CREATE | FS_EVENT_ON_CHILD); -+static DECLARE_WAIT_QUEUE_HEAD(au_hfsn_wq); -+ -+static void au_hfsn_free_mark(struct fsnotify_mark *mark) -+{ -+ struct au_hnotify *hn = container_of(mark, struct au_hnotify, -+ hn_mark); -+ AuDbg("here\n"); -+ hn->hn_mark_dead = 1; -+ smp_mb(); -+ wake_up_all(&au_hfsn_wq); -+} -+ -+static int au_hfsn_alloc(struct au_hinode *hinode) -+{ -+ struct au_hnotify *hn; -+ struct super_block *sb; -+ struct au_branch *br; -+ struct fsnotify_mark *mark; -+ aufs_bindex_t bindex; -+ -+ hn = hinode->hi_notify; -+ sb = hn->hn_aufs_inode->i_sb; -+ bindex = au_br_index(sb, hinode->hi_id); -+ br = au_sbr(sb, bindex); -+ hn->hn_mark_dead = 0; -+ mark = &hn->hn_mark; -+ fsnotify_init_mark(mark, au_hfsn_free_mark); -+ mark->mask = AuHfsnMask; -+ /* -+ * by udba rename or rmdir, aufs assign a new inode to the known -+ * h_inode, so specify 1 to allow dups. -+ */ -+ return fsnotify_add_mark(mark, br->br_hfsn_group, hinode->hi_inode, -+ /*mnt*/NULL, /*allow_dups*/1); -+} -+ -+static void au_hfsn_free(struct au_hinode *hinode) -+{ -+ struct au_hnotify *hn; -+ struct fsnotify_mark *mark; -+ -+ hn = hinode->hi_notify; -+ mark = &hn->hn_mark; -+ fsnotify_destroy_mark(mark); -+ fsnotify_put_mark(mark); -+ -+ /* TODO: bad approach */ -+ wait_event(au_hfsn_wq, hn->hn_mark_dead); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static void au_hfsn_ctl(struct au_hinode *hinode, int do_set) -+{ -+ struct fsnotify_mark *mark; -+ -+ mark = &hinode->hi_notify->hn_mark; -+ spin_lock(&mark->lock); -+ if (do_set) { -+ AuDebugOn(mark->mask & AuHfsnMask); -+ mark->mask |= AuHfsnMask; -+ } else { -+ AuDebugOn(!(mark->mask & AuHfsnMask)); -+ mark->mask &= ~AuHfsnMask; -+ } -+ spin_unlock(&mark->lock); -+ /* fsnotify_recalc_inode_mask(hinode->hi_inode); */ -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* #define AuDbgHnotify */ -+#ifdef AuDbgHnotify -+static char *au_hfsn_name(u32 mask) -+{ -+#ifdef CONFIG_AUFS_DEBUG -+#define test_ret(flag) if (mask & flag) \ -+ return #flag; -+ test_ret(FS_ACCESS); -+ test_ret(FS_MODIFY); -+ test_ret(FS_ATTRIB); -+ test_ret(FS_CLOSE_WRITE); -+ test_ret(FS_CLOSE_NOWRITE); -+ test_ret(FS_OPEN); -+ test_ret(FS_MOVED_FROM); -+ test_ret(FS_MOVED_TO); -+ test_ret(FS_CREATE); -+ test_ret(FS_DELETE); -+ test_ret(FS_DELETE_SELF); -+ test_ret(FS_MOVE_SELF); -+ test_ret(FS_UNMOUNT); -+ test_ret(FS_Q_OVERFLOW); -+ test_ret(FS_IN_IGNORED); -+ test_ret(FS_IN_ISDIR); -+ test_ret(FS_IN_ONESHOT); -+ test_ret(FS_EVENT_ON_CHILD); -+ return ""; -+#undef test_ret -+#else -+ return "??"; -+#endif -+} -+#endif -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int au_hfsn_handle_event(struct fsnotify_group *group, -+ struct fsnotify_mark *inode_mark, -+ struct fsnotify_mark *vfsmount_mark, -+ struct fsnotify_event *event) -+{ -+ int err; -+ struct au_hnotify *hnotify; -+ struct inode *h_dir, *h_inode; -+ __u32 mask; -+ struct qstr h_child_qstr = { -+ .name = event->file_name, -+ .len = event->name_len -+ }; -+ -+ AuDebugOn(event->data_type != FSNOTIFY_EVENT_INODE); -+ -+ err = 0; -+ /* if FS_UNMOUNT happens, there must be another bug */ -+ mask = event->mask; -+ AuDebugOn(mask & FS_UNMOUNT); -+ if (mask & (FS_IN_IGNORED | FS_UNMOUNT)) -+ goto out; -+ -+ h_dir = event->to_tell; -+ h_inode = event->inode; -+#ifdef AuDbgHnotify -+ au_debug(1); -+ if (1 || h_child_qstr.len != sizeof(AUFS_XINO_FNAME) - 1 -+ || strncmp(h_child_qstr.name, AUFS_XINO_FNAME, h_child_qstr.len)) { -+ AuDbg("i%lu, mask 0x%x %s, hcname %.*s, hi%lu\n", -+ h_dir->i_ino, mask, au_hfsn_name(mask), -+ AuLNPair(&h_child_qstr), h_inode ? h_inode->i_ino : 0); -+ /* WARN_ON(1); */ -+ } -+ au_debug(0); -+#endif -+ -+ AuDebugOn(!inode_mark); -+ hnotify = container_of(inode_mark, struct au_hnotify, hn_mark); -+ err = au_hnotify(h_dir, hnotify, mask, &h_child_qstr, h_inode); -+ -+out: -+ return err; -+} -+ -+/* isn't it waste to ask every registered 'group'? */ -+/* copied from linux/fs/notify/inotify/inotify_fsnotiry.c */ -+/* it should be exported to modules */ -+static bool au_hfsn_should_send_event(struct fsnotify_group *group, -+ struct inode *h_inode, -+ struct fsnotify_mark *inode_mark, -+ struct fsnotify_mark *vfsmount_mark, -+ __u32 mask, void *data, int data_type) -+{ -+ mask = (mask & ~FS_EVENT_ON_CHILD); -+ return inode_mark->mask & mask; -+} -+ -+static struct fsnotify_ops au_hfsn_ops = { -+ .should_send_event = au_hfsn_should_send_event, -+ .handle_event = au_hfsn_handle_event -+}; -+ -+/* ---------------------------------------------------------------------- */ -+ -+static void au_hfsn_fin_br(struct au_branch *br) -+{ -+ if (br->br_hfsn_group) -+ fsnotify_put_group(br->br_hfsn_group); -+} -+ -+static int au_hfsn_init_br(struct au_branch *br, int perm) -+{ -+ br->br_hfsn_group = NULL; -+ br->br_hfsn_ops = au_hfsn_ops; -+ return 0; -+} -+ -+static int au_hfsn_reset_br(unsigned int udba, struct au_branch *br, int perm) -+{ -+ int err; -+ -+ err = 0; -+ if (udba != AuOpt_UDBA_HNOTIFY -+ || !au_br_hnotifyable(perm)) { -+ au_hfsn_fin_br(br); -+ br->br_hfsn_group = NULL; -+ goto out; -+ } -+ -+ if (br->br_hfsn_group) -+ goto out; -+ -+ br->br_hfsn_group = fsnotify_alloc_group(&br->br_hfsn_ops); -+ if (IS_ERR(br->br_hfsn_group)) { -+ err = PTR_ERR(br->br_hfsn_group); -+ pr_err("fsnotify_alloc_group() failed, %d\n", err); -+ br->br_hfsn_group = NULL; -+ } -+ -+out: -+ AuTraceErr(err); -+ return err; -+} -+ -+const struct au_hnotify_op au_hnotify_op = { -+ .ctl = au_hfsn_ctl, -+ .alloc = au_hfsn_alloc, -+ .free = au_hfsn_free, -+ -+ .reset_br = au_hfsn_reset_br, -+ .fin_br = au_hfsn_fin_br, -+ .init_br = au_hfsn_init_br -+}; -diff -Nur linux-2.6.36.orig/fs/aufs/hfsplus.c linux-2.6.36/fs/aufs/hfsplus.c ---- linux-2.6.36.orig/fs/aufs/hfsplus.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/hfsplus.c 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,58 @@ -+/* -+ * Copyright (C) 2010-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * special support for filesystems which aqucires an inode mutex -+ * at final closing a file, eg, hfsplus. -+ * -+ * This trick is very simple and stupid, just to open the file before really -+ * neceeary open to tell hfsplus that this is not the final closing. -+ * The caller should call au_h_open_pre() after acquiring the inode mutex, -+ * and au_h_open_post() after releasing it. -+ */ -+ -+#include -+#include "aufs.h" -+ -+struct file *au_h_open_pre(struct dentry *dentry, aufs_bindex_t bindex) -+{ -+ struct file *h_file; -+ struct dentry *h_dentry; -+ -+ h_dentry = au_h_dptr(dentry, bindex); -+ AuDebugOn(!h_dentry); -+ AuDebugOn(!h_dentry->d_inode); -+ IMustLock(h_dentry->d_inode); -+ -+ h_file = NULL; -+ if (au_test_hfsplus(h_dentry->d_sb) -+ && S_ISREG(h_dentry->d_inode->i_mode)) -+ h_file = au_h_open(dentry, bindex, -+ O_RDONLY | O_NOATIME | O_LARGEFILE, -+ /*file*/NULL); -+ return h_file; -+} -+ -+void au_h_open_post(struct dentry *dentry, aufs_bindex_t bindex, -+ struct file *h_file) -+{ -+ if (h_file) { -+ fput(h_file); -+ au_sbr_put(dentry->d_sb, bindex); -+ } -+} -diff -Nur linux-2.6.36.orig/fs/aufs/hnotify.c linux-2.6.36/fs/aufs/hnotify.c ---- linux-2.6.36.orig/fs/aufs/hnotify.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/hnotify.c 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,694 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * abstraction to notify the direct changes on lower directories -+ */ -+ -+#include "aufs.h" -+ -+int au_hn_alloc(struct au_hinode *hinode, struct inode *inode) -+{ -+ int err; -+ struct au_hnotify *hn; -+ -+ err = -ENOMEM; -+ hn = au_cache_alloc_hnotify(); -+ if (hn) { -+ hn->hn_aufs_inode = inode; -+ hinode->hi_notify = hn; -+ err = au_hnotify_op.alloc(hinode); -+ AuTraceErr(err); -+ if (unlikely(err)) { -+ hinode->hi_notify = NULL; -+ au_cache_free_hnotify(hn); -+ /* -+ * The upper dir was removed by udba, but the same named -+ * dir left. In this case, aufs assignes a new inode -+ * number and set the monitor again. -+ * For the lower dir, the old monitnor is still left. -+ */ -+ if (err == -EEXIST) -+ err = 0; -+ } -+ } -+ -+ AuTraceErr(err); -+ return err; -+} -+ -+void au_hn_free(struct au_hinode *hinode) -+{ -+ struct au_hnotify *hn; -+ -+ hn = hinode->hi_notify; -+ if (hn) { -+ au_hnotify_op.free(hinode); -+ au_cache_free_hnotify(hn); -+ hinode->hi_notify = NULL; -+ } -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+void au_hn_ctl(struct au_hinode *hinode, int do_set) -+{ -+ if (hinode->hi_notify) -+ au_hnotify_op.ctl(hinode, do_set); -+} -+ -+void au_hn_reset(struct inode *inode, unsigned int flags) -+{ -+ aufs_bindex_t bindex, bend; -+ struct inode *hi; -+ struct dentry *iwhdentry; -+ -+ bend = au_ibend(inode); -+ for (bindex = au_ibstart(inode); bindex <= bend; bindex++) { -+ hi = au_h_iptr(inode, bindex); -+ if (!hi) -+ continue; -+ -+ /* mutex_lock_nested(&hi->i_mutex, AuLsc_I_CHILD); */ -+ iwhdentry = au_hi_wh(inode, bindex); -+ if (iwhdentry) -+ dget(iwhdentry); -+ au_igrab(hi); -+ au_set_h_iptr(inode, bindex, NULL, 0); -+ au_set_h_iptr(inode, bindex, au_igrab(hi), -+ flags & ~AuHi_XINO); -+ iput(hi); -+ dput(iwhdentry); -+ /* mutex_unlock(&hi->i_mutex); */ -+ } -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int hn_xino(struct inode *inode, struct inode *h_inode) -+{ -+ int err; -+ aufs_bindex_t bindex, bend, bfound, bstart; -+ struct inode *h_i; -+ -+ err = 0; -+ if (unlikely(inode->i_ino == AUFS_ROOT_INO)) { -+ pr_warning("branch root dir was changed\n"); -+ goto out; -+ } -+ -+ bfound = -1; -+ bend = au_ibend(inode); -+ bstart = au_ibstart(inode); -+#if 0 /* reserved for future use */ -+ if (bindex == bend) { -+ /* keep this ino in rename case */ -+ goto out; -+ } -+#endif -+ for (bindex = bstart; bindex <= bend; bindex++) -+ if (au_h_iptr(inode, bindex) == h_inode) { -+ bfound = bindex; -+ break; -+ } -+ if (bfound < 0) -+ goto out; -+ -+ for (bindex = bstart; bindex <= bend; bindex++) { -+ h_i = au_h_iptr(inode, bindex); -+ if (!h_i) -+ continue; -+ -+ err = au_xino_write(inode->i_sb, bindex, h_i->i_ino, /*ino*/0); -+ /* ignore this error */ -+ /* bad action? */ -+ } -+ -+ /* children inode number will be broken */ -+ -+out: -+ AuTraceErr(err); -+ return err; -+} -+ -+static int hn_gen_tree(struct dentry *dentry) -+{ -+ int err, i, j, ndentry; -+ struct au_dcsub_pages dpages; -+ struct au_dpage *dpage; -+ struct dentry **dentries; -+ -+ err = au_dpages_init(&dpages, GFP_NOFS); -+ if (unlikely(err)) -+ goto out; -+ err = au_dcsub_pages(&dpages, dentry, NULL, NULL); -+ if (unlikely(err)) -+ goto out_dpages; -+ -+ for (i = 0; i < dpages.ndpage; i++) { -+ dpage = dpages.dpages + i; -+ dentries = dpage->dentries; -+ ndentry = dpage->ndentry; -+ for (j = 0; j < ndentry; j++) { -+ struct dentry *d; -+ -+ d = dentries[j]; -+ if (IS_ROOT(d)) -+ continue; -+ -+ au_digen_dec(d); -+ if (d->d_inode) -+ /* todo: reset children xino? -+ cached children only? */ -+ au_iigen_dec(d->d_inode); -+ } -+ } -+ -+out_dpages: -+ au_dpages_free(&dpages); -+ -+ /* discard children */ -+ dentry_unhash(dentry); -+ dput(dentry); -+out: -+ return err; -+} -+ -+/* -+ * return 0 if processed. -+ */ -+static int hn_gen_by_inode(char *name, unsigned int nlen, struct inode *inode, -+ const unsigned int isdir) -+{ -+ int err; -+ struct dentry *d; -+ struct qstr *dname; -+ -+ err = 1; -+ if (unlikely(inode->i_ino == AUFS_ROOT_INO)) { -+ pr_warning("branch root dir was changed\n"); -+ err = 0; -+ goto out; -+ } -+ -+ if (!isdir) { -+ AuDebugOn(!name); -+ au_iigen_dec(inode); -+ spin_lock(&dcache_lock); -+ list_for_each_entry(d, &inode->i_dentry, d_alias) { -+ dname = &d->d_name; -+ if (dname->len != nlen -+ && memcmp(dname->name, name, nlen)) -+ continue; -+ err = 0; -+ au_digen_dec(d); -+ break; -+ } -+ spin_unlock(&dcache_lock); -+ } else { -+ au_fset_si(au_sbi(inode->i_sb), FAILED_REFRESH_DIR); -+ d = d_find_alias(inode); -+ if (!d) { -+ au_iigen_dec(inode); -+ goto out; -+ } -+ -+ dname = &d->d_name; -+ if (dname->len == nlen && !memcmp(dname->name, name, nlen)) -+ err = hn_gen_tree(d); -+ dput(d); -+ } -+ -+out: -+ AuTraceErr(err); -+ return err; -+} -+ -+static int hn_gen_by_name(struct dentry *dentry, const unsigned int isdir) -+{ -+ int err; -+ struct inode *inode; -+ -+ inode = dentry->d_inode; -+ if (IS_ROOT(dentry) -+ /* || (inode && inode->i_ino == AUFS_ROOT_INO) */ -+ ) { -+ pr_warning("branch root dir was changed\n"); -+ return 0; -+ } -+ -+ err = 0; -+ if (!isdir) { -+ au_digen_dec(dentry); -+ if (inode) -+ au_iigen_dec(inode); -+ } else { -+ au_fset_si(au_sbi(dentry->d_sb), FAILED_REFRESH_DIR); -+ if (inode) -+ err = hn_gen_tree(dentry); -+ } -+ -+ AuTraceErr(err); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* hnotify job flags */ -+#define AuHnJob_XINO0 1 -+#define AuHnJob_GEN (1 << 1) -+#define AuHnJob_DIRENT (1 << 2) -+#define AuHnJob_ISDIR (1 << 3) -+#define AuHnJob_TRYXINO0 (1 << 4) -+#define AuHnJob_MNTPNT (1 << 5) -+#define au_ftest_hnjob(flags, name) ((flags) & AuHnJob_##name) -+#define au_fset_hnjob(flags, name) \ -+ do { (flags) |= AuHnJob_##name; } while (0) -+#define au_fclr_hnjob(flags, name) \ -+ do { (flags) &= ~AuHnJob_##name; } while (0) -+ -+enum { -+ AuHn_CHILD, -+ AuHn_PARENT, -+ AuHnLast -+}; -+ -+struct au_hnotify_args { -+ struct inode *h_dir, *dir, *h_child_inode; -+ u32 mask; -+ unsigned int flags[AuHnLast]; -+ unsigned int h_child_nlen; -+ char h_child_name[]; -+}; -+ -+struct hn_job_args { -+ unsigned int flags; -+ struct inode *inode, *h_inode, *dir, *h_dir; -+ struct dentry *dentry; -+ char *h_name; -+ int h_nlen; -+}; -+ -+static int hn_job(struct hn_job_args *a) -+{ -+ const unsigned int isdir = au_ftest_hnjob(a->flags, ISDIR); -+ -+ /* reset xino */ -+ if (au_ftest_hnjob(a->flags, XINO0) && a->inode) -+ hn_xino(a->inode, a->h_inode); /* ignore this error */ -+ -+ if (au_ftest_hnjob(a->flags, TRYXINO0) -+ && a->inode -+ && a->h_inode) { -+ mutex_lock_nested(&a->h_inode->i_mutex, AuLsc_I_CHILD); -+ if (!a->h_inode->i_nlink) -+ hn_xino(a->inode, a->h_inode); /* ignore this error */ -+ mutex_unlock(&a->h_inode->i_mutex); -+ } -+ -+ /* make the generation obsolete */ -+ if (au_ftest_hnjob(a->flags, GEN)) { -+ int err = -1; -+ if (a->inode) -+ err = hn_gen_by_inode(a->h_name, a->h_nlen, a->inode, -+ isdir); -+ if (err && a->dentry) -+ hn_gen_by_name(a->dentry, isdir); -+ /* ignore this error */ -+ } -+ -+ /* make dir entries obsolete */ -+ if (au_ftest_hnjob(a->flags, DIRENT) && a->inode) { -+ struct au_vdir *vdir; -+ -+ vdir = au_ivdir(a->inode); -+ if (vdir) -+ vdir->vd_jiffy = 0; -+ /* IMustLock(a->inode); */ -+ /* a->inode->i_version++; */ -+ } -+ -+ /* can do nothing but warn */ -+ if (au_ftest_hnjob(a->flags, MNTPNT) -+ && a->dentry -+ && d_mountpoint(a->dentry)) -+ pr_warning("mount-point %.*s is removed or renamed\n", -+ AuDLNPair(a->dentry)); -+ -+ return 0; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static struct dentry *lookup_wlock_by_name(char *name, unsigned int nlen, -+ struct inode *dir) -+{ -+ struct dentry *dentry, *d, *parent; -+ struct qstr *dname; -+ -+ parent = d_find_alias(dir); -+ if (!parent) -+ return NULL; -+ -+ dentry = NULL; -+ spin_lock(&dcache_lock); -+ list_for_each_entry(d, &parent->d_subdirs, d_u.d_child) { -+ /* AuDbg("%.*s\n", AuDLNPair(d)); */ -+ dname = &d->d_name; -+ if (dname->len != nlen || memcmp(dname->name, name, nlen)) -+ continue; -+ if (au_di(d)) -+ au_digen_dec(d); -+ else -+ continue; -+ if (!atomic_read(&d->d_count)) -+ continue; -+ -+ dentry = dget(d); -+ break; -+ } -+ spin_unlock(&dcache_lock); -+ dput(parent); -+ -+ if (dentry) -+ di_write_lock_child(dentry); -+ -+ return dentry; -+} -+ -+static struct inode *lookup_wlock_by_ino(struct super_block *sb, -+ aufs_bindex_t bindex, ino_t h_ino) -+{ -+ struct inode *inode; -+ ino_t ino; -+ int err; -+ -+ inode = NULL; -+ err = au_xino_read(sb, bindex, h_ino, &ino); -+ if (!err && ino) -+ inode = ilookup(sb, ino); -+ if (!inode) -+ goto out; -+ -+ if (unlikely(inode->i_ino == AUFS_ROOT_INO)) { -+ pr_warning("wrong root branch\n"); -+ iput(inode); -+ inode = NULL; -+ goto out; -+ } -+ -+ ii_write_lock_child(inode); -+ -+out: -+ return inode; -+} -+ -+static void au_hn_bh(void *_args) -+{ -+ struct au_hnotify_args *a = _args; -+ struct super_block *sb; -+ aufs_bindex_t bindex, bend, bfound; -+ unsigned char xino, try_iput; -+ int err; -+ struct inode *inode; -+ ino_t h_ino; -+ struct hn_job_args args; -+ struct dentry *dentry; -+ struct au_sbinfo *sbinfo; -+ -+ AuDebugOn(!_args); -+ AuDebugOn(!a->h_dir); -+ AuDebugOn(!a->dir); -+ AuDebugOn(!a->mask); -+ AuDbg("mask 0x%x, i%lu, hi%lu, hci%lu\n", -+ a->mask, a->dir->i_ino, a->h_dir->i_ino, -+ a->h_child_inode ? a->h_child_inode->i_ino : 0); -+ -+ inode = NULL; -+ dentry = NULL; -+ /* -+ * do not lock a->dir->i_mutex here -+ * because of d_revalidate() may cause a deadlock. -+ */ -+ sb = a->dir->i_sb; -+ AuDebugOn(!sb); -+ sbinfo = au_sbi(sb); -+ AuDebugOn(!sbinfo); -+ si_write_lock(sb, AuLock_NOPLMW); -+ -+ ii_read_lock_parent(a->dir); -+ bfound = -1; -+ bend = au_ibend(a->dir); -+ for (bindex = au_ibstart(a->dir); bindex <= bend; bindex++) -+ if (au_h_iptr(a->dir, bindex) == a->h_dir) { -+ bfound = bindex; -+ break; -+ } -+ ii_read_unlock(a->dir); -+ if (unlikely(bfound < 0)) -+ goto out; -+ -+ xino = !!au_opt_test(au_mntflags(sb), XINO); -+ h_ino = 0; -+ if (a->h_child_inode) -+ h_ino = a->h_child_inode->i_ino; -+ -+ if (a->h_child_nlen -+ && (au_ftest_hnjob(a->flags[AuHn_CHILD], GEN) -+ || au_ftest_hnjob(a->flags[AuHn_CHILD], MNTPNT))) -+ dentry = lookup_wlock_by_name(a->h_child_name, a->h_child_nlen, -+ a->dir); -+ try_iput = 0; -+ if (dentry) -+ inode = dentry->d_inode; -+ if (xino && !inode && h_ino -+ && (au_ftest_hnjob(a->flags[AuHn_CHILD], XINO0) -+ || au_ftest_hnjob(a->flags[AuHn_CHILD], TRYXINO0) -+ || au_ftest_hnjob(a->flags[AuHn_CHILD], GEN))) { -+ inode = lookup_wlock_by_ino(sb, bfound, h_ino); -+ try_iput = 1; -+ } -+ -+ args.flags = a->flags[AuHn_CHILD]; -+ args.dentry = dentry; -+ args.inode = inode; -+ args.h_inode = a->h_child_inode; -+ args.dir = a->dir; -+ args.h_dir = a->h_dir; -+ args.h_name = a->h_child_name; -+ args.h_nlen = a->h_child_nlen; -+ err = hn_job(&args); -+ if (dentry) { -+ if (au_di(dentry)) -+ di_write_unlock(dentry); -+ dput(dentry); -+ } -+ if (inode && try_iput) { -+ ii_write_unlock(inode); -+ iput(inode); -+ } -+ -+ ii_write_lock_parent(a->dir); -+ args.flags = a->flags[AuHn_PARENT]; -+ args.dentry = NULL; -+ args.inode = a->dir; -+ args.h_inode = a->h_dir; -+ args.dir = NULL; -+ args.h_dir = NULL; -+ args.h_name = NULL; -+ args.h_nlen = 0; -+ err = hn_job(&args); -+ ii_write_unlock(a->dir); -+ -+out: -+ iput(a->h_child_inode); -+ iput(a->h_dir); -+ iput(a->dir); -+ si_write_unlock(sb); -+ au_nwt_done(&sbinfo->si_nowait); -+ kfree(a); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+int au_hnotify(struct inode *h_dir, struct au_hnotify *hnotify, u32 mask, -+ struct qstr *h_child_qstr, struct inode *h_child_inode) -+{ -+ int err, len; -+ unsigned int flags[AuHnLast]; -+ unsigned char isdir, isroot, wh; -+ struct inode *dir; -+ struct au_hnotify_args *args; -+ char *p, *h_child_name; -+ -+ err = 0; -+ AuDebugOn(!hnotify || !hnotify->hn_aufs_inode); -+ dir = igrab(hnotify->hn_aufs_inode); -+ if (!dir) -+ goto out; -+ -+ isroot = (dir->i_ino == AUFS_ROOT_INO); -+ wh = 0; -+ h_child_name = (void *)h_child_qstr->name; -+ len = h_child_qstr->len; -+ if (h_child_name) { -+ if (len > AUFS_WH_PFX_LEN -+ && !memcmp(h_child_name, AUFS_WH_PFX, AUFS_WH_PFX_LEN)) { -+ h_child_name += AUFS_WH_PFX_LEN; -+ len -= AUFS_WH_PFX_LEN; -+ wh = 1; -+ } -+ } -+ -+ isdir = 0; -+ if (h_child_inode) -+ isdir = !!S_ISDIR(h_child_inode->i_mode); -+ flags[AuHn_PARENT] = AuHnJob_ISDIR; -+ flags[AuHn_CHILD] = 0; -+ if (isdir) -+ flags[AuHn_CHILD] = AuHnJob_ISDIR; -+ au_fset_hnjob(flags[AuHn_PARENT], DIRENT); -+ au_fset_hnjob(flags[AuHn_CHILD], GEN); -+ switch (mask & FS_EVENTS_POSS_ON_CHILD) { -+ case FS_MOVED_FROM: -+ case FS_MOVED_TO: -+ au_fset_hnjob(flags[AuHn_CHILD], XINO0); -+ au_fset_hnjob(flags[AuHn_CHILD], MNTPNT); -+ /*FALLTHROUGH*/ -+ case FS_CREATE: -+ AuDebugOn(!h_child_name || !h_child_inode); -+ break; -+ -+ case FS_DELETE: -+ /* -+ * aufs never be able to get this child inode. -+ * revalidation should be in d_revalidate() -+ * by checking i_nlink, i_generation or d_unhashed(). -+ */ -+ AuDebugOn(!h_child_name); -+ au_fset_hnjob(flags[AuHn_CHILD], TRYXINO0); -+ au_fset_hnjob(flags[AuHn_CHILD], MNTPNT); -+ break; -+ -+ default: -+ AuDebugOn(1); -+ } -+ -+ if (wh) -+ h_child_inode = NULL; -+ -+ err = -ENOMEM; -+ /* iput() and kfree() will be called in au_hnotify() */ -+ args = kmalloc(sizeof(*args) + len + 1, GFP_NOFS); -+ if (unlikely(!args)) { -+ AuErr1("no memory\n"); -+ iput(dir); -+ goto out; -+ } -+ args->flags[AuHn_PARENT] = flags[AuHn_PARENT]; -+ args->flags[AuHn_CHILD] = flags[AuHn_CHILD]; -+ args->mask = mask; -+ args->dir = dir; -+ args->h_dir = igrab(h_dir); -+ if (h_child_inode) -+ h_child_inode = igrab(h_child_inode); /* can be NULL */ -+ args->h_child_inode = h_child_inode; -+ args->h_child_nlen = len; -+ if (len) { -+ p = (void *)args; -+ p += sizeof(*args); -+ memcpy(p, h_child_name, len); -+ p[len] = 0; -+ } -+ -+ err = au_wkq_nowait(au_hn_bh, args, dir->i_sb); -+ if (unlikely(err)) { -+ pr_err("wkq %d\n", err); -+ iput(args->h_child_inode); -+ iput(args->h_dir); -+ iput(args->dir); -+ kfree(args); -+ } -+ -+out: -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+int au_hnotify_reset_br(unsigned int udba, struct au_branch *br, int perm) -+{ -+ int err; -+ -+ AuDebugOn(!(udba & AuOptMask_UDBA)); -+ -+ err = 0; -+ if (au_hnotify_op.reset_br) -+ err = au_hnotify_op.reset_br(udba, br, perm); -+ -+ return err; -+} -+ -+int au_hnotify_init_br(struct au_branch *br, int perm) -+{ -+ int err; -+ -+ err = 0; -+ if (au_hnotify_op.init_br) -+ err = au_hnotify_op.init_br(br, perm); -+ -+ return err; -+} -+ -+void au_hnotify_fin_br(struct au_branch *br) -+{ -+ if (au_hnotify_op.fin_br) -+ au_hnotify_op.fin_br(br); -+} -+ -+static void au_hn_destroy_cache(void) -+{ -+ kmem_cache_destroy(au_cachep[AuCache_HNOTIFY]); -+ au_cachep[AuCache_HNOTIFY] = NULL; -+} -+ -+int __init au_hnotify_init(void) -+{ -+ int err; -+ -+ err = -ENOMEM; -+ au_cachep[AuCache_HNOTIFY] = AuCache(au_hnotify); -+ if (au_cachep[AuCache_HNOTIFY]) { -+ err = 0; -+ if (au_hnotify_op.init) -+ err = au_hnotify_op.init(); -+ if (unlikely(err)) -+ au_hn_destroy_cache(); -+ } -+ AuTraceErr(err); -+ return err; -+} -+ -+void au_hnotify_fin(void) -+{ -+ if (au_hnotify_op.fin) -+ au_hnotify_op.fin(); -+ /* cf. au_cache_fin() */ -+ if (au_cachep[AuCache_HNOTIFY]) -+ au_hn_destroy_cache(); -+} -diff -Nur linux-2.6.36.orig/fs/aufs/i_op.c linux-2.6.36/fs/aufs/i_op.c ---- linux-2.6.36.orig/fs/aufs/i_op.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/i_op.c 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,971 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * inode operations (except add/del/rename) -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include "aufs.h" -+ -+static int h_permission(struct inode *h_inode, int mask, -+ struct vfsmount *h_mnt, int brperm) -+{ -+ int err; -+ const unsigned char write_mask = !!(mask & (MAY_WRITE | MAY_APPEND)); -+ -+ err = -EACCES; -+ if ((write_mask && IS_IMMUTABLE(h_inode)) -+ || ((mask & MAY_EXEC) -+ && S_ISREG(h_inode->i_mode) -+ && ((h_mnt->mnt_flags & MNT_NOEXEC) -+ || !(h_inode->i_mode & S_IXUGO)))) -+ goto out; -+ -+ /* -+ * - skip the lower fs test in the case of write to ro branch. -+ * - nfs dir permission write check is optimized, but a policy for -+ * link/rename requires a real check. -+ */ -+ if ((write_mask && !au_br_writable(brperm)) -+ || (au_test_nfs(h_inode->i_sb) && S_ISDIR(h_inode->i_mode) -+ && write_mask && !(mask & MAY_READ)) -+ || !h_inode->i_op->permission) { -+ /* AuLabel(generic_permission); */ -+ err = generic_permission(h_inode, mask, -+ h_inode->i_op->check_acl); -+ } else { -+ /* AuLabel(h_inode->permission); */ -+ err = h_inode->i_op->permission(h_inode, mask); -+ AuTraceErr(err); -+ } -+ -+ if (!err) -+ err = devcgroup_inode_permission(h_inode, mask); -+ if (!err) -+ err = security_inode_permission(h_inode, mask); -+ -+#if 0 -+ if (!err) { -+ /* todo: do we need to call ima_path_check()? */ -+ struct path h_path = { -+ .dentry = -+ .mnt = h_mnt -+ }; -+ err = ima_path_check(&h_path, -+ mask & (MAY_READ | MAY_WRITE | MAY_EXEC), -+ IMA_COUNT_LEAVE); -+ } -+#endif -+ -+out: -+ return err; -+} -+ -+static int aufs_permission(struct inode *inode, int mask) -+{ -+ int err; -+ aufs_bindex_t bindex, bend; -+ const unsigned char isdir = !!S_ISDIR(inode->i_mode), -+ write_mask = !!(mask & (MAY_WRITE | MAY_APPEND)); -+ struct inode *h_inode; -+ struct super_block *sb; -+ struct au_branch *br; -+ -+ sb = inode->i_sb; -+ si_read_lock(sb, AuLock_FLUSH); -+ ii_read_lock_child(inode); -+#if 0 -+ err = au_iigen_test(inode, au_sigen(sb)); -+ if (unlikely(err)) -+ goto out; -+#endif -+ -+ if (!isdir || write_mask) { -+ err = au_busy_or_stale(); -+ h_inode = au_h_iptr(inode, au_ibstart(inode)); -+ if (unlikely(!h_inode -+ || (h_inode->i_mode & S_IFMT) -+ != (inode->i_mode & S_IFMT))) -+ goto out; -+ -+ err = 0; -+ bindex = au_ibstart(inode); -+ br = au_sbr(sb, bindex); -+ err = h_permission(h_inode, mask, br->br_mnt, br->br_perm); -+ if (write_mask -+ && !err -+ && !special_file(h_inode->i_mode)) { -+ /* test whether the upper writable branch exists */ -+ err = -EROFS; -+ for (; bindex >= 0; bindex--) -+ if (!au_br_rdonly(au_sbr(sb, bindex))) { -+ err = 0; -+ break; -+ } -+ } -+ goto out; -+ } -+ -+ /* non-write to dir */ -+ err = 0; -+ bend = au_ibend(inode); -+ for (bindex = au_ibstart(inode); !err && bindex <= bend; bindex++) { -+ h_inode = au_h_iptr(inode, bindex); -+ if (h_inode) { -+ err = au_busy_or_stale(); -+ if (unlikely(!S_ISDIR(h_inode->i_mode))) -+ break; -+ -+ br = au_sbr(sb, bindex); -+ err = h_permission(h_inode, mask, br->br_mnt, -+ br->br_perm); -+ } -+ } -+ -+out: -+ ii_read_unlock(inode); -+ si_read_unlock(sb); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static struct dentry *aufs_lookup(struct inode *dir, struct dentry *dentry, -+ struct nameidata *nd) -+{ -+ struct dentry *ret, *parent; -+ struct inode *inode; -+ struct super_block *sb; -+ int err, npositive; -+ -+ IMustLock(dir); -+ -+ sb = dir->i_sb; -+ err = si_read_lock(sb, AuLock_FLUSH | AuLock_NOPLM); -+ ret = ERR_PTR(err); -+ if (unlikely(err)) -+ goto out; -+ -+ ret = ERR_PTR(-ENAMETOOLONG); -+ if (unlikely(dentry->d_name.len > AUFS_MAX_NAMELEN)) -+ goto out_si; -+ err = au_di_init(dentry); -+ ret = ERR_PTR(err); -+ if (unlikely(err)) -+ goto out_si; -+ -+ npositive = 0; /* suppress a warning */ -+ parent = dentry->d_parent; /* dir inode is locked */ -+ di_read_lock_parent(parent, AuLock_IR); -+ err = au_alive_dir(parent); -+ if (!err) -+ err = au_digen_test(parent, au_sigen(sb)); -+ if (!err) { -+ npositive = au_lkup_dentry(dentry, au_dbstart(parent), -+ /*type*/0, nd); -+ err = npositive; -+ } -+ di_read_unlock(parent, AuLock_IR); -+ ret = ERR_PTR(err); -+ if (unlikely(err < 0)) -+ goto out_unlock; -+ -+ inode = NULL; -+ if (npositive) { -+ inode = au_new_inode(dentry, /*must_new*/0); -+ ret = (void *)inode; -+ } -+ if (IS_ERR(inode)) -+ goto out_unlock; -+ -+ ret = d_splice_alias(inode, dentry); -+ if (unlikely(IS_ERR(ret) && inode)) { -+ ii_write_unlock(inode); -+ iput(inode); -+ } -+ -+out_unlock: -+ di_write_unlock(dentry); -+out_si: -+ si_read_unlock(sb); -+out: -+ return ret; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int au_wr_dir_cpup(struct dentry *dentry, struct dentry *parent, -+ const unsigned char add_entry, aufs_bindex_t bcpup, -+ aufs_bindex_t bstart) -+{ -+ int err; -+ struct dentry *h_parent; -+ struct inode *h_dir; -+ -+ if (add_entry) -+ IMustLock(parent->d_inode); -+ else -+ di_write_lock_parent(parent); -+ -+ err = 0; -+ if (!au_h_dptr(parent, bcpup)) { -+ if (bstart < bcpup) -+ err = au_cpdown_dirs(dentry, bcpup); -+ else -+ err = au_cpup_dirs(dentry, bcpup); -+ } -+ if (!err && add_entry) { -+ h_parent = au_h_dptr(parent, bcpup); -+ h_dir = h_parent->d_inode; -+ mutex_lock_nested(&h_dir->i_mutex, AuLsc_I_PARENT); -+ err = au_lkup_neg(dentry, bcpup); -+ /* todo: no unlock here */ -+ mutex_unlock(&h_dir->i_mutex); -+ -+ AuDbg("bcpup %d\n", bcpup); -+ if (!err) { -+ if (!dentry->d_inode) -+ au_set_h_dptr(dentry, bstart, NULL); -+ au_update_dbrange(dentry, /*do_put_zero*/0); -+ } -+ } -+ -+ if (!add_entry) -+ di_write_unlock(parent); -+ if (!err) -+ err = bcpup; /* success */ -+ -+ AuTraceErr(err); -+ return err; -+} -+ -+/* -+ * decide the branch and the parent dir where we will create a new entry. -+ * returns new bindex or an error. -+ * copyup the parent dir if needed. -+ */ -+int au_wr_dir(struct dentry *dentry, struct dentry *src_dentry, -+ struct au_wr_dir_args *args) -+{ -+ int err; -+ aufs_bindex_t bcpup, bstart, src_bstart; -+ const unsigned char add_entry = !!au_ftest_wrdir(args->flags, -+ ADD_ENTRY); -+ struct super_block *sb; -+ struct dentry *parent; -+ struct au_sbinfo *sbinfo; -+ -+ sb = dentry->d_sb; -+ sbinfo = au_sbi(sb); -+ parent = dget_parent(dentry); -+ bstart = au_dbstart(dentry); -+ bcpup = bstart; -+ if (args->force_btgt < 0) { -+ if (src_dentry) { -+ src_bstart = au_dbstart(src_dentry); -+ if (src_bstart < bstart) -+ bcpup = src_bstart; -+ } else if (add_entry) { -+ err = AuWbrCreate(sbinfo, dentry, -+ au_ftest_wrdir(args->flags, ISDIR)); -+ bcpup = err; -+ } -+ -+ if (bcpup < 0 || au_test_ro(sb, bcpup, dentry->d_inode)) { -+ if (add_entry) -+ err = AuWbrCopyup(sbinfo, dentry); -+ else { -+ if (!IS_ROOT(dentry)) { -+ di_read_lock_parent(parent, !AuLock_IR); -+ err = AuWbrCopyup(sbinfo, dentry); -+ di_read_unlock(parent, !AuLock_IR); -+ } else -+ err = AuWbrCopyup(sbinfo, dentry); -+ } -+ bcpup = err; -+ if (unlikely(err < 0)) -+ goto out; -+ } -+ } else { -+ bcpup = args->force_btgt; -+ AuDebugOn(au_test_ro(sb, bcpup, dentry->d_inode)); -+ } -+ -+ AuDbg("bstart %d, bcpup %d\n", bstart, bcpup); -+ err = bcpup; -+ if (bcpup == bstart) -+ goto out; /* success */ -+ -+ /* copyup the new parent into the branch we process */ -+ err = au_wr_dir_cpup(dentry, parent, add_entry, bcpup, bstart); -+ if (err >= 0) { -+ if (!dentry->d_inode) { -+ au_set_h_dptr(dentry, bstart, NULL); -+ au_set_dbstart(dentry, bcpup); -+ au_set_dbend(dentry, bcpup); -+ } -+ AuDebugOn(add_entry && !au_h_dptr(dentry, bcpup)); -+ } -+ -+out: -+ dput(parent); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+struct dentry *au_pinned_h_parent(struct au_pin *pin) -+{ -+ if (pin && pin->parent) -+ return au_h_dptr(pin->parent, pin->bindex); -+ return NULL; -+} -+ -+void au_unpin(struct au_pin *p) -+{ -+ if (p->h_mnt && au_ftest_pin(p->flags, MNT_WRITE)) -+ mnt_drop_write(p->h_mnt); -+ if (!p->hdir) -+ return; -+ -+ au_hn_imtx_unlock(p->hdir); -+ if (!au_ftest_pin(p->flags, DI_LOCKED)) -+ di_read_unlock(p->parent, AuLock_IR); -+ iput(p->hdir->hi_inode); -+ dput(p->parent); -+ p->parent = NULL; -+ p->hdir = NULL; -+ p->h_mnt = NULL; -+} -+ -+int au_do_pin(struct au_pin *p) -+{ -+ int err; -+ struct super_block *sb; -+ struct dentry *h_dentry, *h_parent; -+ struct au_branch *br; -+ struct inode *h_dir; -+ -+ err = 0; -+ sb = p->dentry->d_sb; -+ br = au_sbr(sb, p->bindex); -+ if (IS_ROOT(p->dentry)) { -+ if (au_ftest_pin(p->flags, MNT_WRITE)) { -+ p->h_mnt = br->br_mnt; -+ err = mnt_want_write(p->h_mnt); -+ if (unlikely(err)) { -+ au_fclr_pin(p->flags, MNT_WRITE); -+ goto out_err; -+ } -+ } -+ goto out; -+ } -+ -+ h_dentry = NULL; -+ if (p->bindex <= au_dbend(p->dentry)) -+ h_dentry = au_h_dptr(p->dentry, p->bindex); -+ -+ p->parent = dget_parent(p->dentry); -+ if (!au_ftest_pin(p->flags, DI_LOCKED)) -+ di_read_lock(p->parent, AuLock_IR, p->lsc_di); -+ -+ h_dir = NULL; -+ h_parent = au_h_dptr(p->parent, p->bindex); -+ p->hdir = au_hi(p->parent->d_inode, p->bindex); -+ if (p->hdir) -+ h_dir = p->hdir->hi_inode; -+ -+ /* -+ * udba case, or -+ * if DI_LOCKED is not set, then p->parent may be different -+ * and h_parent can be NULL. -+ */ -+ if (unlikely(!p->hdir || !h_dir || !h_parent)) { -+ err = -EBUSY; -+ if (!au_ftest_pin(p->flags, DI_LOCKED)) -+ di_read_unlock(p->parent, AuLock_IR); -+ dput(p->parent); -+ p->parent = NULL; -+ goto out_err; -+ } -+ -+ au_igrab(h_dir); -+ au_hn_imtx_lock_nested(p->hdir, p->lsc_hi); -+ -+ if (unlikely(p->hdir->hi_inode != h_parent->d_inode)) { -+ err = -EBUSY; -+ goto out_unpin; -+ } -+ if (h_dentry) { -+ err = au_h_verify(h_dentry, p->udba, h_dir, h_parent, br); -+ if (unlikely(err)) { -+ au_fclr_pin(p->flags, MNT_WRITE); -+ goto out_unpin; -+ } -+ } -+ -+ if (au_ftest_pin(p->flags, MNT_WRITE)) { -+ p->h_mnt = br->br_mnt; -+ err = mnt_want_write(p->h_mnt); -+ if (unlikely(err)) { -+ au_fclr_pin(p->flags, MNT_WRITE); -+ goto out_unpin; -+ } -+ } -+ goto out; /* success */ -+ -+out_unpin: -+ au_unpin(p); -+out_err: -+ pr_err("err %d\n", err); -+ err = au_busy_or_stale(); -+out: -+ return err; -+} -+ -+void au_pin_init(struct au_pin *p, struct dentry *dentry, -+ aufs_bindex_t bindex, int lsc_di, int lsc_hi, -+ unsigned int udba, unsigned char flags) -+{ -+ p->dentry = dentry; -+ p->udba = udba; -+ p->lsc_di = lsc_di; -+ p->lsc_hi = lsc_hi; -+ p->flags = flags; -+ p->bindex = bindex; -+ -+ p->parent = NULL; -+ p->hdir = NULL; -+ p->h_mnt = NULL; -+} -+ -+int au_pin(struct au_pin *pin, struct dentry *dentry, aufs_bindex_t bindex, -+ unsigned int udba, unsigned char flags) -+{ -+ au_pin_init(pin, dentry, bindex, AuLsc_DI_PARENT, AuLsc_I_PARENT2, -+ udba, flags); -+ return au_do_pin(pin); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * ->setattr() and ->getattr() are called in various cases. -+ * chmod, stat: dentry is revalidated. -+ * fchmod, fstat: file and dentry are not revalidated, additionally they may be -+ * unhashed. -+ * for ->setattr(), ia->ia_file is passed from ftruncate only. -+ */ -+/* todo: consolidate with do_refresh() and simple_reval_dpath() */ -+static int au_reval_for_attr(struct dentry *dentry, unsigned int sigen) -+{ -+ int err; -+ struct inode *inode; -+ struct dentry *parent; -+ -+ err = 0; -+ inode = dentry->d_inode; -+ if (au_digen_test(dentry, sigen)) { -+ parent = dget_parent(dentry); -+ di_read_lock_parent(parent, AuLock_IR); -+ err = au_refresh_dentry(dentry, parent); -+ di_read_unlock(parent, AuLock_IR); -+ dput(parent); -+ } -+ -+ AuTraceErr(err); -+ return err; -+} -+ -+#define AuIcpup_DID_CPUP 1 -+#define au_ftest_icpup(flags, name) ((flags) & AuIcpup_##name) -+#define au_fset_icpup(flags, name) \ -+ do { (flags) |= AuIcpup_##name; } while (0) -+#define au_fclr_icpup(flags, name) \ -+ do { (flags) &= ~AuIcpup_##name; } while (0) -+ -+struct au_icpup_args { -+ unsigned char flags; -+ unsigned char pin_flags; -+ aufs_bindex_t btgt; -+ unsigned int udba; -+ struct au_pin pin; -+ struct path h_path; -+ struct inode *h_inode; -+}; -+ -+static int au_pin_and_icpup(struct dentry *dentry, struct iattr *ia, -+ struct au_icpup_args *a) -+{ -+ int err; -+ loff_t sz; -+ aufs_bindex_t bstart, ibstart; -+ struct dentry *hi_wh, *parent; -+ struct inode *inode; -+ struct file *h_file; -+ struct au_wr_dir_args wr_dir_args = { -+ .force_btgt = -1, -+ .flags = 0 -+ }; -+ -+ bstart = au_dbstart(dentry); -+ inode = dentry->d_inode; -+ if (S_ISDIR(inode->i_mode)) -+ au_fset_wrdir(wr_dir_args.flags, ISDIR); -+ /* plink or hi_wh() case */ -+ ibstart = au_ibstart(inode); -+ if (bstart != ibstart && !au_test_ro(inode->i_sb, ibstart, inode)) -+ wr_dir_args.force_btgt = ibstart; -+ err = au_wr_dir(dentry, /*src_dentry*/NULL, &wr_dir_args); -+ if (unlikely(err < 0)) -+ goto out; -+ a->btgt = err; -+ if (err != bstart) -+ au_fset_icpup(a->flags, DID_CPUP); -+ -+ err = 0; -+ a->pin_flags = AuPin_MNT_WRITE; -+ parent = NULL; -+ if (!IS_ROOT(dentry)) { -+ au_fset_pin(a->pin_flags, DI_LOCKED); -+ parent = dget_parent(dentry); -+ di_write_lock_parent(parent); -+ } -+ -+ err = au_pin(&a->pin, dentry, a->btgt, a->udba, a->pin_flags); -+ if (unlikely(err)) -+ goto out_parent; -+ -+ a->h_path.dentry = au_h_dptr(dentry, bstart); -+ a->h_inode = a->h_path.dentry->d_inode; -+ mutex_lock_nested(&a->h_inode->i_mutex, AuLsc_I_CHILD); -+ sz = -1; -+ if ((ia->ia_valid & ATTR_SIZE) && ia->ia_size < i_size_read(a->h_inode)) -+ sz = ia->ia_size; -+ -+ h_file = NULL; -+ hi_wh = NULL; -+ if (au_ftest_icpup(a->flags, DID_CPUP) && au_d_removed(dentry)) { -+ hi_wh = au_hi_wh(inode, a->btgt); -+ if (!hi_wh) { -+ err = au_sio_cpup_wh(dentry, a->btgt, sz, /*file*/NULL); -+ if (unlikely(err)) -+ goto out_unlock; -+ hi_wh = au_hi_wh(inode, a->btgt); -+ /* todo: revalidate hi_wh? */ -+ } -+ } -+ -+ if (parent) { -+ au_pin_set_parent_lflag(&a->pin, /*lflag*/0); -+ di_downgrade_lock(parent, AuLock_IR); -+ dput(parent); -+ parent = NULL; -+ } -+ if (!au_ftest_icpup(a->flags, DID_CPUP)) -+ goto out; /* success */ -+ -+ if (!d_unhashed(dentry)) { -+ h_file = au_h_open_pre(dentry, bstart); -+ if (IS_ERR(h_file)) { -+ err = PTR_ERR(h_file); -+ h_file = NULL; -+ } else -+ err = au_sio_cpup_simple(dentry, a->btgt, sz, -+ AuCpup_DTIME); -+ if (!err) -+ a->h_path.dentry = au_h_dptr(dentry, a->btgt); -+ } else if (!hi_wh) -+ a->h_path.dentry = au_h_dptr(dentry, a->btgt); -+ else -+ a->h_path.dentry = hi_wh; /* do not dget here */ -+ -+out_unlock: -+ mutex_unlock(&a->h_inode->i_mutex); -+ au_h_open_post(dentry, bstart, h_file); -+ a->h_inode = a->h_path.dentry->d_inode; -+ if (!err) { -+ mutex_lock_nested(&a->h_inode->i_mutex, AuLsc_I_CHILD); -+ goto out; /* success */ -+ } -+ -+ au_unpin(&a->pin); -+out_parent: -+ if (parent) { -+ di_write_unlock(parent); -+ dput(parent); -+ } -+out: -+ return err; -+} -+ -+static int aufs_setattr(struct dentry *dentry, struct iattr *ia) -+{ -+ int err; -+ struct inode *inode; -+ struct super_block *sb; -+ struct file *file; -+ struct au_icpup_args *a; -+ -+ inode = dentry->d_inode; -+ IMustLock(inode); -+ -+ err = -ENOMEM; -+ a = kzalloc(sizeof(*a), GFP_NOFS); -+ if (unlikely(!a)) -+ goto out; -+ -+ if (ia->ia_valid & (ATTR_KILL_SUID | ATTR_KILL_SGID)) -+ ia->ia_valid &= ~ATTR_MODE; -+ -+ file = NULL; -+ sb = dentry->d_sb; -+ err = si_read_lock(sb, AuLock_FLUSH | AuLock_NOPLM); -+ if (unlikely(err)) -+ goto out_kfree; -+ -+ if (ia->ia_valid & ATTR_FILE) { -+ /* currently ftruncate(2) only */ -+ AuDebugOn(!S_ISREG(inode->i_mode)); -+ file = ia->ia_file; -+ err = au_reval_and_lock_fdi(file, au_reopen_nondir, /*wlock*/1); -+ if (unlikely(err)) -+ goto out_si; -+ ia->ia_file = au_hf_top(file); -+ a->udba = AuOpt_UDBA_NONE; -+ } else { -+ /* fchmod() doesn't pass ia_file */ -+ a->udba = au_opt_udba(sb); -+ /* no au_d_removed(), to set UDBA_NONE for root */ -+ if (d_unhashed(dentry)) -+ a->udba = AuOpt_UDBA_NONE; -+ di_write_lock_child(dentry); -+ if (a->udba != AuOpt_UDBA_NONE) { -+ AuDebugOn(IS_ROOT(dentry)); -+ err = au_reval_for_attr(dentry, au_sigen(sb)); -+ if (unlikely(err)) -+ goto out_dentry; -+ } -+ } -+ -+ err = au_pin_and_icpup(dentry, ia, a); -+ if (unlikely(err < 0)) -+ goto out_dentry; -+ if (au_ftest_icpup(a->flags, DID_CPUP)) { -+ ia->ia_file = NULL; -+ ia->ia_valid &= ~ATTR_FILE; -+ } -+ -+ a->h_path.mnt = au_sbr_mnt(sb, a->btgt); -+ if ((ia->ia_valid & (ATTR_MODE | ATTR_CTIME)) -+ == (ATTR_MODE | ATTR_CTIME)) { -+ err = security_path_chmod(a->h_path.dentry, a->h_path.mnt, -+ ia->ia_mode); -+ if (unlikely(err)) -+ goto out_unlock; -+ } else if ((ia->ia_valid & (ATTR_UID | ATTR_GID)) -+ && (ia->ia_valid & ATTR_CTIME)) { -+ err = security_path_chown(&a->h_path, ia->ia_uid, ia->ia_gid); -+ if (unlikely(err)) -+ goto out_unlock; -+ } -+ -+ if (ia->ia_valid & ATTR_SIZE) { -+ struct file *f; -+ -+ if (ia->ia_size < i_size_read(inode)) -+ /* unmap only */ -+ truncate_setsize(inode, ia->ia_size); -+ -+ f = NULL; -+ if (ia->ia_valid & ATTR_FILE) -+ f = ia->ia_file; -+ mutex_unlock(&a->h_inode->i_mutex); -+ err = vfsub_trunc(&a->h_path, ia->ia_size, ia->ia_valid, f); -+ mutex_lock_nested(&a->h_inode->i_mutex, AuLsc_I_CHILD); -+ } else -+ err = vfsub_notify_change(&a->h_path, ia); -+ if (!err) -+ au_cpup_attr_changeable(inode); -+ -+out_unlock: -+ mutex_unlock(&a->h_inode->i_mutex); -+ au_unpin(&a->pin); -+ if (unlikely(err)) -+ au_update_dbstart(dentry); -+out_dentry: -+ di_write_unlock(dentry); -+ if (file) { -+ fi_write_unlock(file); -+ ia->ia_file = file; -+ ia->ia_valid |= ATTR_FILE; -+ } -+out_si: -+ si_read_unlock(sb); -+out_kfree: -+ kfree(a); -+out: -+ AuTraceErr(err); -+ return err; -+} -+ -+static void au_refresh_iattr(struct inode *inode, struct kstat *st, -+ unsigned int nlink) -+{ -+ inode->i_mode = st->mode; -+ inode->i_uid = st->uid; -+ inode->i_gid = st->gid; -+ inode->i_atime = st->atime; -+ inode->i_mtime = st->mtime; -+ inode->i_ctime = st->ctime; -+ -+ au_cpup_attr_nlink(inode, /*force*/0); -+ if (S_ISDIR(inode->i_mode)) { -+ inode->i_nlink -= nlink; -+ inode->i_nlink += st->nlink; -+ } -+ -+ spin_lock(&inode->i_lock); -+ inode->i_blocks = st->blocks; -+ i_size_write(inode, st->size); -+ spin_unlock(&inode->i_lock); -+} -+ -+static int aufs_getattr(struct vfsmount *mnt __maybe_unused, -+ struct dentry *dentry, struct kstat *st) -+{ -+ int err; -+ unsigned int mnt_flags; -+ aufs_bindex_t bindex; -+ unsigned char udba_none, positive; -+ struct super_block *sb, *h_sb; -+ struct inode *inode; -+ struct vfsmount *h_mnt; -+ struct dentry *h_dentry; -+ -+ sb = dentry->d_sb; -+ inode = dentry->d_inode; -+ err = si_read_lock(sb, AuLock_FLUSH | AuLock_NOPLM); -+ if (unlikely(err)) -+ goto out; -+ mnt_flags = au_mntflags(sb); -+ udba_none = !!au_opt_test(mnt_flags, UDBA_NONE); -+ -+ /* support fstat(2) */ -+ if (!au_d_removed(dentry) && !udba_none) { -+ unsigned int sigen = au_sigen(sb); -+ err = au_digen_test(dentry, sigen); -+ if (!err) { -+ di_read_lock_child(dentry, AuLock_IR); -+ err = au_dbrange_test(dentry); -+ if (unlikely(err)) -+ goto out_unlock; -+ } else { -+ AuDebugOn(IS_ROOT(dentry)); -+ di_write_lock_child(dentry); -+ err = au_dbrange_test(dentry); -+ if (!err) -+ err = au_reval_for_attr(dentry, sigen); -+ di_downgrade_lock(dentry, AuLock_IR); -+ if (unlikely(err)) -+ goto out_unlock; -+ } -+ } else -+ di_read_lock_child(dentry, AuLock_IR); -+ -+ bindex = au_ibstart(inode); -+ h_mnt = au_sbr_mnt(sb, bindex); -+ h_sb = h_mnt->mnt_sb; -+ if (!au_test_fs_bad_iattr(h_sb) && udba_none) -+ goto out_fill; /* success */ -+ -+ h_dentry = NULL; -+ if (au_dbstart(dentry) == bindex) -+ h_dentry = dget(au_h_dptr(dentry, bindex)); -+ else if (au_opt_test(mnt_flags, PLINK) && au_plink_test(inode)) { -+ h_dentry = au_plink_lkup(inode, bindex); -+ if (IS_ERR(h_dentry)) -+ goto out_fill; /* pretending success */ -+ } -+ /* illegally overlapped or something */ -+ if (unlikely(!h_dentry)) -+ goto out_fill; /* pretending success */ -+ -+ positive = !!h_dentry->d_inode; -+ if (positive) -+ err = vfs_getattr(h_mnt, h_dentry, st); -+ dput(h_dentry); -+ if (!err) { -+ if (positive) -+ au_refresh_iattr(inode, st, h_dentry->d_inode->i_nlink); -+ goto out_fill; /* success */ -+ } -+ AuTraceErr(err); -+ goto out_unlock; -+ -+out_fill: -+ generic_fillattr(inode, st); -+out_unlock: -+ di_read_unlock(dentry, AuLock_IR); -+ si_read_unlock(sb); -+out: -+ AuTraceErr(err); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int h_readlink(struct dentry *dentry, int bindex, char __user *buf, -+ int bufsiz) -+{ -+ int err; -+ struct super_block *sb; -+ struct dentry *h_dentry; -+ -+ err = -EINVAL; -+ h_dentry = au_h_dptr(dentry, bindex); -+ if (unlikely(!h_dentry->d_inode->i_op->readlink)) -+ goto out; -+ -+ err = security_inode_readlink(h_dentry); -+ if (unlikely(err)) -+ goto out; -+ -+ sb = dentry->d_sb; -+ if (!au_test_ro(sb, bindex, dentry->d_inode)) { -+ vfsub_touch_atime(au_sbr_mnt(sb, bindex), h_dentry); -+ fsstack_copy_attr_atime(dentry->d_inode, h_dentry->d_inode); -+ } -+ err = h_dentry->d_inode->i_op->readlink(h_dentry, buf, bufsiz); -+ -+out: -+ return err; -+} -+ -+static int aufs_readlink(struct dentry *dentry, char __user *buf, int bufsiz) -+{ -+ int err; -+ -+ err = aufs_read_lock(dentry, AuLock_IR | AuLock_GEN); -+ if (unlikely(err)) -+ goto out; -+ err = au_d_hashed_positive(dentry); -+ if (!err) -+ err = h_readlink(dentry, au_dbstart(dentry), buf, bufsiz); -+ aufs_read_unlock(dentry, AuLock_IR); -+ -+out: -+ return err; -+} -+ -+static void *aufs_follow_link(struct dentry *dentry, struct nameidata *nd) -+{ -+ int err; -+ mm_segment_t old_fs; -+ union { -+ char *k; -+ char __user *u; -+ } buf; -+ -+ err = -ENOMEM; -+ buf.k = __getname_gfp(GFP_NOFS); -+ if (unlikely(!buf.k)) -+ goto out; -+ -+ err = aufs_read_lock(dentry, AuLock_IR | AuLock_GEN); -+ if (unlikely(err)) -+ goto out_name; -+ -+ err = au_d_hashed_positive(dentry); -+ if (!err) { -+ old_fs = get_fs(); -+ set_fs(KERNEL_DS); -+ err = h_readlink(dentry, au_dbstart(dentry), buf.u, PATH_MAX); -+ set_fs(old_fs); -+ } -+ aufs_read_unlock(dentry, AuLock_IR); -+ -+ if (err >= 0) { -+ buf.k[err] = 0; -+ /* will be freed by put_link */ -+ nd_set_link(nd, buf.k); -+ return NULL; /* success */ -+ } -+ -+out_name: -+ __putname(buf.k); -+out: -+ path_put(&nd->path); -+ AuTraceErr(err); -+ return ERR_PTR(err); -+} -+ -+static void aufs_put_link(struct dentry *dentry __maybe_unused, -+ struct nameidata *nd, void *cookie __maybe_unused) -+{ -+ __putname(nd_get_link(nd)); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static void aufs_truncate_range(struct inode *inode __maybe_unused, -+ loff_t start __maybe_unused, -+ loff_t end __maybe_unused) -+{ -+ AuUnsupport(); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+struct inode_operations aufs_symlink_iop = { -+ .permission = aufs_permission, -+ .setattr = aufs_setattr, -+ .getattr = aufs_getattr, -+ .readlink = aufs_readlink, -+ .follow_link = aufs_follow_link, -+ .put_link = aufs_put_link -+}; -+ -+struct inode_operations aufs_dir_iop = { -+ .create = aufs_create, -+ .lookup = aufs_lookup, -+ .link = aufs_link, -+ .unlink = aufs_unlink, -+ .symlink = aufs_symlink, -+ .mkdir = aufs_mkdir, -+ .rmdir = aufs_rmdir, -+ .mknod = aufs_mknod, -+ .rename = aufs_rename, -+ -+ .permission = aufs_permission, -+ .setattr = aufs_setattr, -+ .getattr = aufs_getattr -+}; -+ -+struct inode_operations aufs_iop = { -+ .permission = aufs_permission, -+ .setattr = aufs_setattr, -+ .getattr = aufs_getattr, -+ .truncate_range = aufs_truncate_range -+}; -diff -Nur linux-2.6.36.orig/fs/aufs/i_op_add.c linux-2.6.36/fs/aufs/i_op_add.c ---- linux-2.6.36.orig/fs/aufs/i_op_add.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/i_op_add.c 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,702 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * inode operations (add entry) -+ */ -+ -+#include "aufs.h" -+ -+/* -+ * final procedure of adding a new entry, except link(2). -+ * remove whiteout, instantiate, copyup the parent dir's times and size -+ * and update version. -+ * if it failed, re-create the removed whiteout. -+ */ -+static int epilog(struct inode *dir, aufs_bindex_t bindex, -+ struct dentry *wh_dentry, struct dentry *dentry) -+{ -+ int err, rerr; -+ aufs_bindex_t bwh; -+ struct path h_path; -+ struct inode *inode, *h_dir; -+ struct dentry *wh; -+ -+ bwh = -1; -+ if (wh_dentry) { -+ h_dir = wh_dentry->d_parent->d_inode; /* dir inode is locked */ -+ IMustLock(h_dir); -+ AuDebugOn(au_h_iptr(dir, bindex) != h_dir); -+ bwh = au_dbwh(dentry); -+ h_path.dentry = wh_dentry; -+ h_path.mnt = au_sbr_mnt(dir->i_sb, bindex); -+ err = au_wh_unlink_dentry(au_h_iptr(dir, bindex), &h_path, -+ dentry); -+ if (unlikely(err)) -+ goto out; -+ } -+ -+ inode = au_new_inode(dentry, /*must_new*/1); -+ if (!IS_ERR(inode)) { -+ d_instantiate(dentry, inode); -+ dir = dentry->d_parent->d_inode; /* dir inode is locked */ -+ IMustLock(dir); -+ if (au_ibstart(dir) == au_dbstart(dentry)) -+ au_cpup_attr_timesizes(dir); -+ dir->i_version++; -+ return 0; /* success */ -+ } -+ -+ err = PTR_ERR(inode); -+ if (!wh_dentry) -+ goto out; -+ -+ /* revert */ -+ /* dir inode is locked */ -+ wh = au_wh_create(dentry, bwh, wh_dentry->d_parent); -+ rerr = PTR_ERR(wh); -+ if (IS_ERR(wh)) { -+ AuIOErr("%.*s reverting whiteout failed(%d, %d)\n", -+ AuDLNPair(dentry), err, rerr); -+ err = -EIO; -+ } else -+ dput(wh); -+ -+out: -+ return err; -+} -+ -+static int au_d_may_add(struct dentry *dentry) -+{ -+ int err; -+ -+ err = 0; -+ if (unlikely(d_unhashed(dentry))) -+ err = -ENOENT; -+ if (unlikely(dentry->d_inode)) -+ err = -EEXIST; -+ return err; -+} -+ -+/* -+ * simple tests for the adding inode operations. -+ * following the checks in vfs, plus the parent-child relationship. -+ */ -+int au_may_add(struct dentry *dentry, aufs_bindex_t bindex, -+ struct dentry *h_parent, int isdir) -+{ -+ int err; -+ umode_t h_mode; -+ struct dentry *h_dentry; -+ struct inode *h_inode; -+ -+ err = -ENAMETOOLONG; -+ if (unlikely(dentry->d_name.len > AUFS_MAX_NAMELEN)) -+ goto out; -+ -+ h_dentry = au_h_dptr(dentry, bindex); -+ h_inode = h_dentry->d_inode; -+ if (!dentry->d_inode) { -+ err = -EEXIST; -+ if (unlikely(h_inode)) -+ goto out; -+ } else { -+ /* rename(2) case */ -+ err = -EIO; -+ if (unlikely(!h_inode || !h_inode->i_nlink)) -+ goto out; -+ -+ h_mode = h_inode->i_mode; -+ if (!isdir) { -+ err = -EISDIR; -+ if (unlikely(S_ISDIR(h_mode))) -+ goto out; -+ } else if (unlikely(!S_ISDIR(h_mode))) { -+ err = -ENOTDIR; -+ goto out; -+ } -+ } -+ -+ err = 0; -+ /* expected parent dir is locked */ -+ if (unlikely(h_parent != h_dentry->d_parent)) -+ err = -EIO; -+ -+out: -+ AuTraceErr(err); -+ return err; -+} -+ -+/* -+ * initial procedure of adding a new entry. -+ * prepare writable branch and the parent dir, lock it, -+ * and lookup whiteout for the new entry. -+ */ -+static struct dentry* -+lock_hdir_lkup_wh(struct dentry *dentry, struct au_dtime *dt, -+ struct dentry *src_dentry, struct au_pin *pin, -+ struct au_wr_dir_args *wr_dir_args) -+{ -+ struct dentry *wh_dentry, *h_parent; -+ struct super_block *sb; -+ struct au_branch *br; -+ int err; -+ unsigned int udba; -+ aufs_bindex_t bcpup; -+ -+ AuDbg("%.*s\n", AuDLNPair(dentry)); -+ -+ err = au_wr_dir(dentry, src_dentry, wr_dir_args); -+ bcpup = err; -+ wh_dentry = ERR_PTR(err); -+ if (unlikely(err < 0)) -+ goto out; -+ -+ sb = dentry->d_sb; -+ udba = au_opt_udba(sb); -+ err = au_pin(pin, dentry, bcpup, udba, -+ AuPin_DI_LOCKED | AuPin_MNT_WRITE); -+ wh_dentry = ERR_PTR(err); -+ if (unlikely(err)) -+ goto out; -+ -+ h_parent = au_pinned_h_parent(pin); -+ if (udba != AuOpt_UDBA_NONE -+ && au_dbstart(dentry) == bcpup) -+ err = au_may_add(dentry, bcpup, h_parent, -+ au_ftest_wrdir(wr_dir_args->flags, ISDIR)); -+ else if (unlikely(dentry->d_name.len > AUFS_MAX_NAMELEN)) -+ err = -ENAMETOOLONG; -+ wh_dentry = ERR_PTR(err); -+ if (unlikely(err)) -+ goto out_unpin; -+ -+ br = au_sbr(sb, bcpup); -+ if (dt) { -+ struct path tmp = { -+ .dentry = h_parent, -+ .mnt = br->br_mnt -+ }; -+ au_dtime_store(dt, au_pinned_parent(pin), &tmp); -+ } -+ -+ wh_dentry = NULL; -+ if (bcpup != au_dbwh(dentry)) -+ goto out; /* success */ -+ -+ wh_dentry = au_wh_lkup(h_parent, &dentry->d_name, br); -+ -+out_unpin: -+ if (IS_ERR(wh_dentry)) -+ au_unpin(pin); -+out: -+ return wh_dentry; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+enum { Mknod, Symlink, Creat }; -+struct simple_arg { -+ int type; -+ union { -+ struct { -+ int mode; -+ struct nameidata *nd; -+ } c; -+ struct { -+ const char *symname; -+ } s; -+ struct { -+ int mode; -+ dev_t dev; -+ } m; -+ } u; -+}; -+ -+static int add_simple(struct inode *dir, struct dentry *dentry, -+ struct simple_arg *arg) -+{ -+ int err; -+ aufs_bindex_t bstart; -+ unsigned char created; -+ struct au_dtime dt; -+ struct au_pin pin; -+ struct path h_path; -+ struct dentry *wh_dentry, *parent; -+ struct inode *h_dir; -+ struct au_wr_dir_args wr_dir_args = { -+ .force_btgt = -1, -+ .flags = AuWrDir_ADD_ENTRY -+ }; -+ -+ AuDbg("%.*s\n", AuDLNPair(dentry)); -+ IMustLock(dir); -+ -+ parent = dentry->d_parent; /* dir inode is locked */ -+ err = aufs_read_lock(dentry, AuLock_DW | AuLock_GEN); -+ if (unlikely(err)) -+ goto out; -+ err = au_d_may_add(dentry); -+ if (unlikely(err)) -+ goto out_unlock; -+ di_write_lock_parent(parent); -+ wh_dentry = lock_hdir_lkup_wh(dentry, &dt, /*src_dentry*/NULL, &pin, -+ &wr_dir_args); -+ err = PTR_ERR(wh_dentry); -+ if (IS_ERR(wh_dentry)) -+ goto out_parent; -+ -+ bstart = au_dbstart(dentry); -+ h_path.dentry = au_h_dptr(dentry, bstart); -+ h_path.mnt = au_sbr_mnt(dentry->d_sb, bstart); -+ h_dir = au_pinned_h_dir(&pin); -+ switch (arg->type) { -+ case Creat: -+ err = vfsub_create(h_dir, &h_path, arg->u.c.mode); -+ break; -+ case Symlink: -+ err = vfsub_symlink(h_dir, &h_path, arg->u.s.symname); -+ break; -+ case Mknod: -+ err = vfsub_mknod(h_dir, &h_path, arg->u.m.mode, arg->u.m.dev); -+ break; -+ default: -+ BUG(); -+ } -+ created = !err; -+ if (!err) -+ err = epilog(dir, bstart, wh_dentry, dentry); -+ -+ /* revert */ -+ if (unlikely(created && err && h_path.dentry->d_inode)) { -+ int rerr; -+ rerr = vfsub_unlink(h_dir, &h_path, /*force*/0); -+ if (rerr) { -+ AuIOErr("%.*s revert failure(%d, %d)\n", -+ AuDLNPair(dentry), err, rerr); -+ err = -EIO; -+ } -+ au_dtime_revert(&dt); -+ } -+ -+ au_unpin(&pin); -+ dput(wh_dentry); -+ -+out_parent: -+ di_write_unlock(parent); -+out_unlock: -+ if (unlikely(err)) { -+ au_update_dbstart(dentry); -+ d_drop(dentry); -+ } -+ aufs_read_unlock(dentry, AuLock_DW); -+out: -+ return err; -+} -+ -+int aufs_mknod(struct inode *dir, struct dentry *dentry, int mode, dev_t dev) -+{ -+ struct simple_arg arg = { -+ .type = Mknod, -+ .u.m = { -+ .mode = mode, -+ .dev = dev -+ } -+ }; -+ return add_simple(dir, dentry, &arg); -+} -+ -+int aufs_symlink(struct inode *dir, struct dentry *dentry, const char *symname) -+{ -+ struct simple_arg arg = { -+ .type = Symlink, -+ .u.s.symname = symname -+ }; -+ return add_simple(dir, dentry, &arg); -+} -+ -+int aufs_create(struct inode *dir, struct dentry *dentry, int mode, -+ struct nameidata *nd) -+{ -+ struct simple_arg arg = { -+ .type = Creat, -+ .u.c = { -+ .mode = mode, -+ .nd = nd -+ } -+ }; -+ return add_simple(dir, dentry, &arg); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+struct au_link_args { -+ aufs_bindex_t bdst, bsrc; -+ struct au_pin pin; -+ struct path h_path; -+ struct dentry *src_parent, *parent; -+}; -+ -+static int au_cpup_before_link(struct dentry *src_dentry, -+ struct au_link_args *a) -+{ -+ int err; -+ struct dentry *h_src_dentry; -+ struct mutex *h_mtx; -+ struct file *h_file; -+ -+ di_read_lock_parent(a->src_parent, AuLock_IR); -+ err = au_test_and_cpup_dirs(src_dentry, a->bdst); -+ if (unlikely(err)) -+ goto out; -+ -+ h_src_dentry = au_h_dptr(src_dentry, a->bsrc); -+ h_mtx = &h_src_dentry->d_inode->i_mutex; -+ err = au_pin(&a->pin, src_dentry, a->bdst, -+ au_opt_udba(src_dentry->d_sb), -+ AuPin_DI_LOCKED | AuPin_MNT_WRITE); -+ if (unlikely(err)) -+ goto out; -+ mutex_lock_nested(h_mtx, AuLsc_I_CHILD); -+ h_file = au_h_open_pre(src_dentry, a->bsrc); -+ if (IS_ERR(h_file)) { -+ err = PTR_ERR(h_file); -+ h_file = NULL; -+ } else -+ err = au_sio_cpup_simple(src_dentry, a->bdst, a->bsrc, -+ AuCpup_DTIME /* | AuCpup_KEEPLINO */); -+ mutex_unlock(h_mtx); -+ au_h_open_post(src_dentry, a->bsrc, h_file); -+ au_unpin(&a->pin); -+ -+out: -+ di_read_unlock(a->src_parent, AuLock_IR); -+ return err; -+} -+ -+static int au_cpup_or_link(struct dentry *src_dentry, struct au_link_args *a) -+{ -+ int err; -+ unsigned char plink; -+ struct inode *h_inode, *inode; -+ struct dentry *h_src_dentry; -+ struct super_block *sb; -+ struct file *h_file; -+ -+ plink = 0; -+ h_inode = NULL; -+ sb = src_dentry->d_sb; -+ inode = src_dentry->d_inode; -+ if (au_ibstart(inode) <= a->bdst) -+ h_inode = au_h_iptr(inode, a->bdst); -+ if (!h_inode || !h_inode->i_nlink) { -+ /* copyup src_dentry as the name of dentry. */ -+ au_set_dbstart(src_dentry, a->bdst); -+ au_set_h_dptr(src_dentry, a->bdst, dget(a->h_path.dentry)); -+ h_inode = au_h_dptr(src_dentry, a->bsrc)->d_inode; -+ mutex_lock_nested(&h_inode->i_mutex, AuLsc_I_CHILD); -+ h_file = au_h_open_pre(src_dentry, a->bsrc); -+ if (IS_ERR(h_file)) { -+ err = PTR_ERR(h_file); -+ h_file = NULL; -+ } else -+ err = au_sio_cpup_single(src_dentry, a->bdst, a->bsrc, -+ -1, AuCpup_KEEPLINO, -+ a->parent); -+ mutex_unlock(&h_inode->i_mutex); -+ au_h_open_post(src_dentry, a->bsrc, h_file); -+ au_set_h_dptr(src_dentry, a->bdst, NULL); -+ au_set_dbstart(src_dentry, a->bsrc); -+ } else { -+ /* the inode of src_dentry already exists on a.bdst branch */ -+ h_src_dentry = d_find_alias(h_inode); -+ if (!h_src_dentry && au_plink_test(inode)) { -+ plink = 1; -+ h_src_dentry = au_plink_lkup(inode, a->bdst); -+ err = PTR_ERR(h_src_dentry); -+ if (IS_ERR(h_src_dentry)) -+ goto out; -+ -+ if (unlikely(!h_src_dentry->d_inode)) { -+ dput(h_src_dentry); -+ h_src_dentry = NULL; -+ } -+ -+ } -+ if (h_src_dentry) { -+ err = vfsub_link(h_src_dentry, au_pinned_h_dir(&a->pin), -+ &a->h_path); -+ dput(h_src_dentry); -+ } else { -+ AuIOErr("no dentry found for hi%lu on b%d\n", -+ h_inode->i_ino, a->bdst); -+ err = -EIO; -+ } -+ } -+ -+ if (!err && !plink) -+ au_plink_append(inode, a->bdst, a->h_path.dentry); -+ -+out: -+ return err; -+} -+ -+int aufs_link(struct dentry *src_dentry, struct inode *dir, -+ struct dentry *dentry) -+{ -+ int err, rerr; -+ struct au_dtime dt; -+ struct au_link_args *a; -+ struct dentry *wh_dentry, *h_src_dentry; -+ struct inode *inode; -+ struct super_block *sb; -+ struct au_wr_dir_args wr_dir_args = { -+ /* .force_btgt = -1, */ -+ .flags = AuWrDir_ADD_ENTRY -+ }; -+ -+ IMustLock(dir); -+ inode = src_dentry->d_inode; -+ IMustLock(inode); -+ -+ err = -ENOMEM; -+ a = kzalloc(sizeof(*a), GFP_NOFS); -+ if (unlikely(!a)) -+ goto out; -+ -+ a->parent = dentry->d_parent; /* dir inode is locked */ -+ err = aufs_read_and_write_lock2(dentry, src_dentry, -+ AuLock_NOPLM | AuLock_GEN); -+ if (unlikely(err)) -+ goto out_kfree; -+ err = au_d_hashed_positive(src_dentry); -+ if (unlikely(err)) -+ goto out_unlock; -+ err = au_d_may_add(dentry); -+ if (unlikely(err)) -+ goto out_unlock; -+ -+ a->src_parent = dget_parent(src_dentry); -+ wr_dir_args.force_btgt = au_dbstart(src_dentry); -+ -+ di_write_lock_parent(a->parent); -+ wr_dir_args.force_btgt = au_wbr(dentry, wr_dir_args.force_btgt); -+ wh_dentry = lock_hdir_lkup_wh(dentry, &dt, src_dentry, &a->pin, -+ &wr_dir_args); -+ err = PTR_ERR(wh_dentry); -+ if (IS_ERR(wh_dentry)) -+ goto out_parent; -+ -+ err = 0; -+ sb = dentry->d_sb; -+ a->bdst = au_dbstart(dentry); -+ a->h_path.dentry = au_h_dptr(dentry, a->bdst); -+ a->h_path.mnt = au_sbr_mnt(sb, a->bdst); -+ a->bsrc = au_dbstart(src_dentry); -+ if (au_opt_test(au_mntflags(sb), PLINK)) { -+ if (a->bdst < a->bsrc -+ /* && h_src_dentry->d_sb != a->h_path.dentry->d_sb */) -+ err = au_cpup_or_link(src_dentry, a); -+ else { -+ h_src_dentry = au_h_dptr(src_dentry, a->bdst); -+ err = vfsub_link(h_src_dentry, au_pinned_h_dir(&a->pin), -+ &a->h_path); -+ } -+ } else { -+ /* -+ * copyup src_dentry to the branch we process, -+ * and then link(2) to it. -+ */ -+ if (a->bdst < a->bsrc -+ /* && h_src_dentry->d_sb != a->h_path.dentry->d_sb */) { -+ au_unpin(&a->pin); -+ di_write_unlock(a->parent); -+ err = au_cpup_before_link(src_dentry, a); -+ di_write_lock_parent(a->parent); -+ if (!err) -+ err = au_pin(&a->pin, dentry, a->bdst, -+ au_opt_udba(sb), -+ AuPin_DI_LOCKED | AuPin_MNT_WRITE); -+ if (unlikely(err)) -+ goto out_wh; -+ } -+ if (!err) { -+ h_src_dentry = au_h_dptr(src_dentry, a->bdst); -+ err = -ENOENT; -+ if (h_src_dentry && h_src_dentry->d_inode) -+ err = vfsub_link(h_src_dentry, -+ au_pinned_h_dir(&a->pin), -+ &a->h_path); -+ } -+ } -+ if (unlikely(err)) -+ goto out_unpin; -+ -+ if (wh_dentry) { -+ a->h_path.dentry = wh_dentry; -+ err = au_wh_unlink_dentry(au_pinned_h_dir(&a->pin), &a->h_path, -+ dentry); -+ if (unlikely(err)) -+ goto out_revert; -+ } -+ -+ dir->i_version++; -+ if (au_ibstart(dir) == au_dbstart(dentry)) -+ au_cpup_attr_timesizes(dir); -+ inc_nlink(inode); -+ inode->i_ctime = dir->i_ctime; -+ d_instantiate(dentry, au_igrab(inode)); -+ if (d_unhashed(a->h_path.dentry)) -+ /* some filesystem calls d_drop() */ -+ d_drop(dentry); -+ goto out_unpin; /* success */ -+ -+out_revert: -+ rerr = vfsub_unlink(au_pinned_h_dir(&a->pin), &a->h_path, /*force*/0); -+ if (unlikely(rerr)) { -+ AuIOErr("%.*s reverting failed(%d, %d)\n", -+ AuDLNPair(dentry), err, rerr); -+ err = -EIO; -+ } -+ au_dtime_revert(&dt); -+out_unpin: -+ au_unpin(&a->pin); -+out_wh: -+ dput(wh_dentry); -+out_parent: -+ di_write_unlock(a->parent); -+ dput(a->src_parent); -+out_unlock: -+ if (unlikely(err)) { -+ au_update_dbstart(dentry); -+ d_drop(dentry); -+ } -+ aufs_read_and_write_unlock2(dentry, src_dentry); -+out_kfree: -+ kfree(a); -+out: -+ return err; -+} -+ -+int aufs_mkdir(struct inode *dir, struct dentry *dentry, int mode) -+{ -+ int err, rerr; -+ aufs_bindex_t bindex; -+ unsigned char diropq; -+ struct path h_path; -+ struct dentry *wh_dentry, *parent, *opq_dentry; -+ struct mutex *h_mtx; -+ struct super_block *sb; -+ struct { -+ struct au_pin pin; -+ struct au_dtime dt; -+ } *a; /* reduce the stack usage */ -+ struct au_wr_dir_args wr_dir_args = { -+ .force_btgt = -1, -+ .flags = AuWrDir_ADD_ENTRY | AuWrDir_ISDIR -+ }; -+ -+ IMustLock(dir); -+ -+ err = -ENOMEM; -+ a = kmalloc(sizeof(*a), GFP_NOFS); -+ if (unlikely(!a)) -+ goto out; -+ -+ err = aufs_read_lock(dentry, AuLock_DW | AuLock_GEN); -+ if (unlikely(err)) -+ goto out_free; -+ err = au_d_may_add(dentry); -+ if (unlikely(err)) -+ goto out_unlock; -+ -+ parent = dentry->d_parent; /* dir inode is locked */ -+ di_write_lock_parent(parent); -+ wh_dentry = lock_hdir_lkup_wh(dentry, &a->dt, /*src_dentry*/NULL, -+ &a->pin, &wr_dir_args); -+ err = PTR_ERR(wh_dentry); -+ if (IS_ERR(wh_dentry)) -+ goto out_parent; -+ -+ sb = dentry->d_sb; -+ bindex = au_dbstart(dentry); -+ h_path.dentry = au_h_dptr(dentry, bindex); -+ h_path.mnt = au_sbr_mnt(sb, bindex); -+ err = vfsub_mkdir(au_pinned_h_dir(&a->pin), &h_path, mode); -+ if (unlikely(err)) -+ goto out_unpin; -+ -+ /* make the dir opaque */ -+ diropq = 0; -+ h_mtx = &h_path.dentry->d_inode->i_mutex; -+ if (wh_dentry -+ || au_opt_test(au_mntflags(sb), ALWAYS_DIROPQ)) { -+ mutex_lock_nested(h_mtx, AuLsc_I_CHILD); -+ opq_dentry = au_diropq_create(dentry, bindex); -+ mutex_unlock(h_mtx); -+ err = PTR_ERR(opq_dentry); -+ if (IS_ERR(opq_dentry)) -+ goto out_dir; -+ dput(opq_dentry); -+ diropq = 1; -+ } -+ -+ err = epilog(dir, bindex, wh_dentry, dentry); -+ if (!err) { -+ inc_nlink(dir); -+ goto out_unpin; /* success */ -+ } -+ -+ /* revert */ -+ if (diropq) { -+ AuLabel(revert opq); -+ mutex_lock_nested(h_mtx, AuLsc_I_CHILD); -+ rerr = au_diropq_remove(dentry, bindex); -+ mutex_unlock(h_mtx); -+ if (rerr) { -+ AuIOErr("%.*s reverting diropq failed(%d, %d)\n", -+ AuDLNPair(dentry), err, rerr); -+ err = -EIO; -+ } -+ } -+ -+out_dir: -+ AuLabel(revert dir); -+ rerr = vfsub_rmdir(au_pinned_h_dir(&a->pin), &h_path); -+ if (rerr) { -+ AuIOErr("%.*s reverting dir failed(%d, %d)\n", -+ AuDLNPair(dentry), err, rerr); -+ err = -EIO; -+ } -+ au_dtime_revert(&a->dt); -+out_unpin: -+ au_unpin(&a->pin); -+ dput(wh_dentry); -+out_parent: -+ di_write_unlock(parent); -+out_unlock: -+ if (unlikely(err)) { -+ au_update_dbstart(dentry); -+ d_drop(dentry); -+ } -+ aufs_read_unlock(dentry, AuLock_DW); -+out_free: -+ kfree(a); -+out: -+ return err; -+} -diff -Nur linux-2.6.36.orig/fs/aufs/i_op_del.c linux-2.6.36/fs/aufs/i_op_del.c ---- linux-2.6.36.orig/fs/aufs/i_op_del.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/i_op_del.c 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,481 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * inode operations (del entry) -+ */ -+ -+#include "aufs.h" -+ -+/* -+ * decide if a new whiteout for @dentry is necessary or not. -+ * when it is necessary, prepare the parent dir for the upper branch whose -+ * branch index is @bcpup for creation. the actual creation of the whiteout will -+ * be done by caller. -+ * return value: -+ * 0: wh is unnecessary -+ * plus: wh is necessary -+ * minus: error -+ */ -+int au_wr_dir_need_wh(struct dentry *dentry, int isdir, aufs_bindex_t *bcpup) -+{ -+ int need_wh, err; -+ aufs_bindex_t bstart; -+ struct super_block *sb; -+ -+ sb = dentry->d_sb; -+ bstart = au_dbstart(dentry); -+ if (*bcpup < 0) { -+ *bcpup = bstart; -+ if (au_test_ro(sb, bstart, dentry->d_inode)) { -+ err = AuWbrCopyup(au_sbi(sb), dentry); -+ *bcpup = err; -+ if (unlikely(err < 0)) -+ goto out; -+ } -+ } else -+ AuDebugOn(bstart < *bcpup -+ || au_test_ro(sb, *bcpup, dentry->d_inode)); -+ AuDbg("bcpup %d, bstart %d\n", *bcpup, bstart); -+ -+ if (*bcpup != bstart) { -+ err = au_cpup_dirs(dentry, *bcpup); -+ if (unlikely(err)) -+ goto out; -+ need_wh = 1; -+ } else { -+ struct au_dinfo *dinfo, *tmp; -+ -+ need_wh = -ENOMEM; -+ dinfo = au_di(dentry); -+ tmp = au_di_alloc(sb, AuLsc_DI_TMP); -+ if (tmp) { -+ au_di_cp(tmp, dinfo); -+ au_di_swap(tmp, dinfo); -+ /* returns the number of positive dentries */ -+ need_wh = au_lkup_dentry(dentry, bstart + 1, /*type*/0, -+ /*nd*/NULL); -+ au_di_swap(tmp, dinfo); -+ au_rw_write_unlock(&tmp->di_rwsem); -+ au_di_free(tmp); -+ } -+ } -+ AuDbg("need_wh %d\n", need_wh); -+ err = need_wh; -+ -+out: -+ return err; -+} -+ -+/* -+ * simple tests for the del-entry operations. -+ * following the checks in vfs, plus the parent-child relationship. -+ */ -+int au_may_del(struct dentry *dentry, aufs_bindex_t bindex, -+ struct dentry *h_parent, int isdir) -+{ -+ int err; -+ umode_t h_mode; -+ struct dentry *h_dentry, *h_latest; -+ struct inode *h_inode; -+ -+ h_dentry = au_h_dptr(dentry, bindex); -+ h_inode = h_dentry->d_inode; -+ if (dentry->d_inode) { -+ err = -ENOENT; -+ if (unlikely(!h_inode || !h_inode->i_nlink)) -+ goto out; -+ -+ h_mode = h_inode->i_mode; -+ if (!isdir) { -+ err = -EISDIR; -+ if (unlikely(S_ISDIR(h_mode))) -+ goto out; -+ } else if (unlikely(!S_ISDIR(h_mode))) { -+ err = -ENOTDIR; -+ goto out; -+ } -+ } else { -+ /* rename(2) case */ -+ err = -EIO; -+ if (unlikely(h_inode)) -+ goto out; -+ } -+ -+ err = -ENOENT; -+ /* expected parent dir is locked */ -+ if (unlikely(h_parent != h_dentry->d_parent)) -+ goto out; -+ err = 0; -+ -+ /* -+ * rmdir a dir may break the consistency on some filesystem. -+ * let's try heavy test. -+ */ -+ err = -EACCES; -+ if (unlikely(au_test_h_perm(h_parent->d_inode, MAY_EXEC | MAY_WRITE))) -+ goto out; -+ -+ h_latest = au_sio_lkup_one(&dentry->d_name, h_parent, -+ au_sbr(dentry->d_sb, bindex)); -+ err = -EIO; -+ if (IS_ERR(h_latest)) -+ goto out; -+ if (h_latest == h_dentry) -+ err = 0; -+ dput(h_latest); -+ -+out: -+ return err; -+} -+ -+/* -+ * decide the branch where we operate for @dentry. the branch index will be set -+ * @rbcpup. after diciding it, 'pin' it and store the timestamps of the parent -+ * dir for reverting. -+ * when a new whiteout is necessary, create it. -+ */ -+static struct dentry* -+lock_hdir_create_wh(struct dentry *dentry, int isdir, aufs_bindex_t *rbcpup, -+ struct au_dtime *dt, struct au_pin *pin) -+{ -+ struct dentry *wh_dentry; -+ struct super_block *sb; -+ struct path h_path; -+ int err, need_wh; -+ unsigned int udba; -+ aufs_bindex_t bcpup; -+ -+ need_wh = au_wr_dir_need_wh(dentry, isdir, rbcpup); -+ wh_dentry = ERR_PTR(need_wh); -+ if (unlikely(need_wh < 0)) -+ goto out; -+ -+ sb = dentry->d_sb; -+ udba = au_opt_udba(sb); -+ bcpup = *rbcpup; -+ err = au_pin(pin, dentry, bcpup, udba, -+ AuPin_DI_LOCKED | AuPin_MNT_WRITE); -+ wh_dentry = ERR_PTR(err); -+ if (unlikely(err)) -+ goto out; -+ -+ h_path.dentry = au_pinned_h_parent(pin); -+ if (udba != AuOpt_UDBA_NONE -+ && au_dbstart(dentry) == bcpup) { -+ err = au_may_del(dentry, bcpup, h_path.dentry, isdir); -+ wh_dentry = ERR_PTR(err); -+ if (unlikely(err)) -+ goto out_unpin; -+ } -+ -+ h_path.mnt = au_sbr_mnt(sb, bcpup); -+ au_dtime_store(dt, au_pinned_parent(pin), &h_path); -+ wh_dentry = NULL; -+ if (!need_wh) -+ goto out; /* success, no need to create whiteout */ -+ -+ wh_dentry = au_wh_create(dentry, bcpup, h_path.dentry); -+ if (IS_ERR(wh_dentry)) -+ goto out_unpin; -+ -+ /* returns with the parent is locked and wh_dentry is dget-ed */ -+ goto out; /* success */ -+ -+out_unpin: -+ au_unpin(pin); -+out: -+ return wh_dentry; -+} -+ -+/* -+ * when removing a dir, rename it to a unique temporary whiteout-ed name first -+ * in order to be revertible and save time for removing many child whiteouts -+ * under the dir. -+ * returns 1 when there are too many child whiteout and caller should remove -+ * them asynchronously. returns 0 when the number of children is enough small to -+ * remove now or the branch fs is a remote fs. -+ * otherwise return an error. -+ */ -+static int renwh_and_rmdir(struct dentry *dentry, aufs_bindex_t bindex, -+ struct au_nhash *whlist, struct inode *dir) -+{ -+ int rmdir_later, err, dirwh; -+ struct dentry *h_dentry; -+ struct super_block *sb; -+ -+ sb = dentry->d_sb; -+ SiMustAnyLock(sb); -+ h_dentry = au_h_dptr(dentry, bindex); -+ err = au_whtmp_ren(h_dentry, au_sbr(sb, bindex)); -+ if (unlikely(err)) -+ goto out; -+ -+ /* stop monitoring */ -+ au_hn_free(au_hi(dentry->d_inode, bindex)); -+ -+ if (!au_test_fs_remote(h_dentry->d_sb)) { -+ dirwh = au_sbi(sb)->si_dirwh; -+ rmdir_later = (dirwh <= 1); -+ if (!rmdir_later) -+ rmdir_later = au_nhash_test_longer_wh(whlist, bindex, -+ dirwh); -+ if (rmdir_later) -+ return rmdir_later; -+ } -+ -+ err = au_whtmp_rmdir(dir, bindex, h_dentry, whlist); -+ if (unlikely(err)) { -+ AuIOErr("rmdir %.*s, b%d failed, %d. ignored\n", -+ AuDLNPair(h_dentry), bindex, err); -+ err = 0; -+ } -+ -+out: -+ AuTraceErr(err); -+ return err; -+} -+ -+/* -+ * final procedure for deleting a entry. -+ * maintain dentry and iattr. -+ */ -+static void epilog(struct inode *dir, struct dentry *dentry, -+ aufs_bindex_t bindex) -+{ -+ struct inode *inode; -+ -+ inode = dentry->d_inode; -+ d_drop(dentry); -+ inode->i_ctime = dir->i_ctime; -+ -+ if (au_ibstart(dir) == bindex) -+ au_cpup_attr_timesizes(dir); -+ dir->i_version++; -+} -+ -+/* -+ * when an error happened, remove the created whiteout and revert everything. -+ */ -+static int do_revert(int err, struct inode *dir, aufs_bindex_t bindex, -+ aufs_bindex_t bwh, struct dentry *wh_dentry, -+ struct dentry *dentry, struct au_dtime *dt) -+{ -+ int rerr; -+ struct path h_path = { -+ .dentry = wh_dentry, -+ .mnt = au_sbr_mnt(dir->i_sb, bindex) -+ }; -+ -+ rerr = au_wh_unlink_dentry(au_h_iptr(dir, bindex), &h_path, dentry); -+ if (!rerr) { -+ au_set_dbwh(dentry, bwh); -+ au_dtime_revert(dt); -+ return 0; -+ } -+ -+ AuIOErr("%.*s reverting whiteout failed(%d, %d)\n", -+ AuDLNPair(dentry), err, rerr); -+ return -EIO; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+int aufs_unlink(struct inode *dir, struct dentry *dentry) -+{ -+ int err; -+ aufs_bindex_t bwh, bindex, bstart; -+ struct au_dtime dt; -+ struct au_pin pin; -+ struct path h_path; -+ struct inode *inode, *h_dir; -+ struct dentry *parent, *wh_dentry; -+ -+ IMustLock(dir); -+ -+ err = aufs_read_lock(dentry, AuLock_DW | AuLock_GEN); -+ if (unlikely(err)) -+ goto out; -+ err = au_d_hashed_positive(dentry); -+ if (unlikely(err)) -+ goto out_unlock; -+ inode = dentry->d_inode; -+ IMustLock(inode); -+ err = -EISDIR; -+ if (unlikely(S_ISDIR(inode->i_mode))) -+ goto out_unlock; /* possible? */ -+ -+ bstart = au_dbstart(dentry); -+ bwh = au_dbwh(dentry); -+ bindex = -1; -+ parent = dentry->d_parent; /* dir inode is locked */ -+ di_write_lock_parent(parent); -+ wh_dentry = lock_hdir_create_wh(dentry, /*isdir*/0, &bindex, &dt, &pin); -+ err = PTR_ERR(wh_dentry); -+ if (IS_ERR(wh_dentry)) -+ goto out_parent; -+ -+ h_path.mnt = au_sbr_mnt(dentry->d_sb, bstart); -+ h_path.dentry = au_h_dptr(dentry, bstart); -+ dget(h_path.dentry); -+ if (bindex == bstart) { -+ h_dir = au_pinned_h_dir(&pin); -+ err = vfsub_unlink(h_dir, &h_path, /*force*/0); -+ } else { -+ /* dir inode is locked */ -+ h_dir = wh_dentry->d_parent->d_inode; -+ IMustLock(h_dir); -+ err = 0; -+ } -+ -+ if (!err) { -+ vfsub_drop_nlink(inode); -+ epilog(dir, dentry, bindex); -+ -+ /* update target timestamps */ -+ if (bindex == bstart) { -+ vfsub_update_h_iattr(&h_path, /*did*/NULL); /*ignore*/ -+ inode->i_ctime = h_path.dentry->d_inode->i_ctime; -+ } else -+ /* todo: this timestamp may be reverted later */ -+ inode->i_ctime = h_dir->i_ctime; -+ goto out_unpin; /* success */ -+ } -+ -+ /* revert */ -+ if (wh_dentry) { -+ int rerr; -+ -+ rerr = do_revert(err, dir, bindex, bwh, wh_dentry, dentry, &dt); -+ if (rerr) -+ err = rerr; -+ } -+ -+out_unpin: -+ au_unpin(&pin); -+ dput(wh_dentry); -+ dput(h_path.dentry); -+out_parent: -+ di_write_unlock(parent); -+out_unlock: -+ aufs_read_unlock(dentry, AuLock_DW); -+out: -+ return err; -+} -+ -+int aufs_rmdir(struct inode *dir, struct dentry *dentry) -+{ -+ int err, rmdir_later; -+ aufs_bindex_t bwh, bindex, bstart; -+ struct au_dtime dt; -+ struct au_pin pin; -+ struct inode *inode; -+ struct dentry *parent, *wh_dentry, *h_dentry; -+ struct au_whtmp_rmdir *args; -+ -+ IMustLock(dir); -+ -+ err = aufs_read_lock(dentry, AuLock_DW | AuLock_FLUSH | AuLock_GEN); -+ if (unlikely(err)) -+ goto out; -+ -+ /* VFS already unhashes it */ -+ inode = dentry->d_inode; -+ err = -ENOENT; -+ if (unlikely(!inode || !inode->i_nlink -+ || IS_DEADDIR(inode))) -+ goto out_unlock; -+ IMustLock(inode); -+ err = -ENOTDIR; -+ if (unlikely(!S_ISDIR(inode->i_mode))) -+ goto out_unlock; /* possible? */ -+ -+ err = -ENOMEM; -+ args = au_whtmp_rmdir_alloc(dir->i_sb, GFP_NOFS); -+ if (unlikely(!args)) -+ goto out_unlock; -+ -+ parent = dentry->d_parent; /* dir inode is locked */ -+ di_write_lock_parent(parent); -+ err = au_test_empty(dentry, &args->whlist); -+ if (unlikely(err)) -+ goto out_parent; -+ -+ bstart = au_dbstart(dentry); -+ bwh = au_dbwh(dentry); -+ bindex = -1; -+ wh_dentry = lock_hdir_create_wh(dentry, /*isdir*/1, &bindex, &dt, &pin); -+ err = PTR_ERR(wh_dentry); -+ if (IS_ERR(wh_dentry)) -+ goto out_parent; -+ -+ h_dentry = au_h_dptr(dentry, bstart); -+ dget(h_dentry); -+ rmdir_later = 0; -+ if (bindex == bstart) { -+ err = renwh_and_rmdir(dentry, bstart, &args->whlist, dir); -+ if (err > 0) { -+ rmdir_later = err; -+ err = 0; -+ } -+ } else { -+ /* stop monitoring */ -+ au_hn_free(au_hi(inode, bstart)); -+ -+ /* dir inode is locked */ -+ IMustLock(wh_dentry->d_parent->d_inode); -+ err = 0; -+ } -+ -+ if (!err) { -+ vfsub_dead_dir(inode); -+ au_set_dbdiropq(dentry, -1); -+ epilog(dir, dentry, bindex); -+ -+ if (rmdir_later) { -+ au_whtmp_kick_rmdir(dir, bstart, h_dentry, args); -+ args = NULL; -+ } -+ -+ goto out_unpin; /* success */ -+ } -+ -+ /* revert */ -+ AuLabel(revert); -+ if (wh_dentry) { -+ int rerr; -+ -+ rerr = do_revert(err, dir, bindex, bwh, wh_dentry, dentry, &dt); -+ if (rerr) -+ err = rerr; -+ } -+ -+out_unpin: -+ au_unpin(&pin); -+ dput(wh_dentry); -+ dput(h_dentry); -+out_parent: -+ di_write_unlock(parent); -+ if (args) -+ au_whtmp_rmdir_free(args); -+out_unlock: -+ aufs_read_unlock(dentry, AuLock_DW); -+out: -+ AuTraceErr(err); -+ return err; -+} -diff -Nur linux-2.6.36.orig/fs/aufs/i_op_ren.c linux-2.6.36/fs/aufs/i_op_ren.c ---- linux-2.6.36.orig/fs/aufs/i_op_ren.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/i_op_ren.c 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,1017 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * inode operation (rename entry) -+ * todo: this is crazy monster -+ */ -+ -+#include "aufs.h" -+ -+enum { AuSRC, AuDST, AuSrcDst }; -+enum { AuPARENT, AuCHILD, AuParentChild }; -+ -+#define AuRen_ISDIR 1 -+#define AuRen_ISSAMEDIR (1 << 1) -+#define AuRen_WHSRC (1 << 2) -+#define AuRen_WHDST (1 << 3) -+#define AuRen_MNT_WRITE (1 << 4) -+#define AuRen_DT_DSTDIR (1 << 5) -+#define AuRen_DIROPQ (1 << 6) -+#define AuRen_CPUP (1 << 7) -+#define au_ftest_ren(flags, name) ((flags) & AuRen_##name) -+#define au_fset_ren(flags, name) \ -+ do { (flags) |= AuRen_##name; } while (0) -+#define au_fclr_ren(flags, name) \ -+ do { (flags) &= ~AuRen_##name; } while (0) -+ -+struct au_ren_args { -+ struct { -+ struct dentry *dentry, *h_dentry, *parent, *h_parent, -+ *wh_dentry; -+ struct inode *dir, *inode; -+ struct au_hinode *hdir; -+ struct au_dtime dt[AuParentChild]; -+ aufs_bindex_t bstart; -+ } sd[AuSrcDst]; -+ -+#define src_dentry sd[AuSRC].dentry -+#define src_dir sd[AuSRC].dir -+#define src_inode sd[AuSRC].inode -+#define src_h_dentry sd[AuSRC].h_dentry -+#define src_parent sd[AuSRC].parent -+#define src_h_parent sd[AuSRC].h_parent -+#define src_wh_dentry sd[AuSRC].wh_dentry -+#define src_hdir sd[AuSRC].hdir -+#define src_h_dir sd[AuSRC].hdir->hi_inode -+#define src_dt sd[AuSRC].dt -+#define src_bstart sd[AuSRC].bstart -+ -+#define dst_dentry sd[AuDST].dentry -+#define dst_dir sd[AuDST].dir -+#define dst_inode sd[AuDST].inode -+#define dst_h_dentry sd[AuDST].h_dentry -+#define dst_parent sd[AuDST].parent -+#define dst_h_parent sd[AuDST].h_parent -+#define dst_wh_dentry sd[AuDST].wh_dentry -+#define dst_hdir sd[AuDST].hdir -+#define dst_h_dir sd[AuDST].hdir->hi_inode -+#define dst_dt sd[AuDST].dt -+#define dst_bstart sd[AuDST].bstart -+ -+ struct dentry *h_trap; -+ struct au_branch *br; -+ struct au_hinode *src_hinode; -+ struct path h_path; -+ struct au_nhash whlist; -+ aufs_bindex_t btgt, src_bwh, src_bdiropq; -+ -+ unsigned int flags; -+ -+ struct au_whtmp_rmdir *thargs; -+ struct dentry *h_dst; -+}; -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * functions for reverting. -+ * when an error happened in a single rename systemcall, we should revert -+ * everything as if nothing happend. -+ * we don't need to revert the copied-up/down the parent dir since they are -+ * harmless. -+ */ -+ -+#define RevertFailure(fmt, ...) do { \ -+ AuIOErr("revert failure: " fmt " (%d, %d)\n", \ -+ ##__VA_ARGS__, err, rerr); \ -+ err = -EIO; \ -+} while (0) -+ -+static void au_ren_rev_diropq(int err, struct au_ren_args *a) -+{ -+ int rerr; -+ -+ au_hn_imtx_lock_nested(a->src_hinode, AuLsc_I_CHILD); -+ rerr = au_diropq_remove(a->src_dentry, a->btgt); -+ au_hn_imtx_unlock(a->src_hinode); -+ au_set_dbdiropq(a->src_dentry, a->src_bdiropq); -+ if (rerr) -+ RevertFailure("remove diropq %.*s", AuDLNPair(a->src_dentry)); -+} -+ -+static void au_ren_rev_rename(int err, struct au_ren_args *a) -+{ -+ int rerr; -+ -+ a->h_path.dentry = au_lkup_one(&a->src_dentry->d_name, a->src_h_parent, -+ a->br, /*nd*/NULL); -+ rerr = PTR_ERR(a->h_path.dentry); -+ if (IS_ERR(a->h_path.dentry)) { -+ RevertFailure("au_lkup_one %.*s", AuDLNPair(a->src_dentry)); -+ return; -+ } -+ -+ rerr = vfsub_rename(a->dst_h_dir, -+ au_h_dptr(a->src_dentry, a->btgt), -+ a->src_h_dir, &a->h_path); -+ d_drop(a->h_path.dentry); -+ dput(a->h_path.dentry); -+ /* au_set_h_dptr(a->src_dentry, a->btgt, NULL); */ -+ if (rerr) -+ RevertFailure("rename %.*s", AuDLNPair(a->src_dentry)); -+} -+ -+static void au_ren_rev_cpup(int err, struct au_ren_args *a) -+{ -+ int rerr; -+ -+ a->h_path.dentry = a->dst_h_dentry; -+ rerr = vfsub_unlink(a->dst_h_dir, &a->h_path, /*force*/0); -+ au_set_h_dptr(a->src_dentry, a->btgt, NULL); -+ au_set_dbstart(a->src_dentry, a->src_bstart); -+ if (rerr) -+ RevertFailure("unlink %.*s", AuDLNPair(a->dst_h_dentry)); -+} -+ -+static void au_ren_rev_whtmp(int err, struct au_ren_args *a) -+{ -+ int rerr; -+ -+ a->h_path.dentry = au_lkup_one(&a->dst_dentry->d_name, a->dst_h_parent, -+ a->br, /*nd*/NULL); -+ rerr = PTR_ERR(a->h_path.dentry); -+ if (IS_ERR(a->h_path.dentry)) { -+ RevertFailure("lookup %.*s", AuDLNPair(a->dst_dentry)); -+ return; -+ } -+ if (a->h_path.dentry->d_inode) { -+ d_drop(a->h_path.dentry); -+ dput(a->h_path.dentry); -+ return; -+ } -+ -+ rerr = vfsub_rename(a->dst_h_dir, a->h_dst, a->dst_h_dir, &a->h_path); -+ d_drop(a->h_path.dentry); -+ dput(a->h_path.dentry); -+ if (!rerr) -+ au_set_h_dptr(a->dst_dentry, a->btgt, dget(a->h_dst)); -+ else -+ RevertFailure("rename %.*s", AuDLNPair(a->h_dst)); -+} -+ -+static void au_ren_rev_whsrc(int err, struct au_ren_args *a) -+{ -+ int rerr; -+ -+ a->h_path.dentry = a->src_wh_dentry; -+ rerr = au_wh_unlink_dentry(a->src_h_dir, &a->h_path, a->src_dentry); -+ au_set_dbwh(a->src_dentry, a->src_bwh); -+ if (rerr) -+ RevertFailure("unlink %.*s", AuDLNPair(a->src_wh_dentry)); -+} -+#undef RevertFailure -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * when we have to copyup the renaming entry, do it with the rename-target name -+ * in order to minimize the cost (the later actual rename is unnecessary). -+ * otherwise rename it on the target branch. -+ */ -+static int au_ren_or_cpup(struct au_ren_args *a) -+{ -+ int err; -+ struct dentry *d; -+ -+ d = a->src_dentry; -+ if (au_dbstart(d) == a->btgt) { -+ a->h_path.dentry = a->dst_h_dentry; -+ if (au_ftest_ren(a->flags, DIROPQ) -+ && au_dbdiropq(d) == a->btgt) -+ au_fclr_ren(a->flags, DIROPQ); -+ AuDebugOn(au_dbstart(d) != a->btgt); -+ err = vfsub_rename(a->src_h_dir, au_h_dptr(d, a->btgt), -+ a->dst_h_dir, &a->h_path); -+ } else { -+ struct mutex *h_mtx = &a->src_h_dentry->d_inode->i_mutex; -+ struct file *h_file; -+ -+ au_fset_ren(a->flags, CPUP); -+ mutex_lock_nested(h_mtx, AuLsc_I_CHILD); -+ au_set_dbstart(d, a->btgt); -+ au_set_h_dptr(d, a->btgt, dget(a->dst_h_dentry)); -+ h_file = au_h_open_pre(d, a->src_bstart); -+ if (IS_ERR(h_file)) { -+ err = PTR_ERR(h_file); -+ h_file = NULL; -+ } else -+ err = au_sio_cpup_single(d, a->btgt, a->src_bstart, -1, -+ !AuCpup_DTIME, a->dst_parent); -+ mutex_unlock(h_mtx); -+ au_h_open_post(d, a->src_bstart, h_file); -+ if (!err) { -+ d = a->dst_dentry; -+ au_set_h_dptr(d, a->btgt, NULL); -+ au_update_dbstart(d); -+ } else { -+ au_set_h_dptr(d, a->btgt, NULL); -+ au_set_dbstart(d, a->src_bstart); -+ } -+ } -+ if (!err && a->h_dst) -+ /* it will be set to dinfo later */ -+ dget(a->h_dst); -+ -+ return err; -+} -+ -+/* cf. aufs_rmdir() */ -+static int au_ren_del_whtmp(struct au_ren_args *a) -+{ -+ int err; -+ struct inode *dir; -+ -+ dir = a->dst_dir; -+ SiMustAnyLock(dir->i_sb); -+ if (!au_nhash_test_longer_wh(&a->whlist, a->btgt, -+ au_sbi(dir->i_sb)->si_dirwh) -+ || au_test_fs_remote(a->h_dst->d_sb)) { -+ err = au_whtmp_rmdir(dir, a->btgt, a->h_dst, &a->whlist); -+ if (unlikely(err)) -+ pr_warning("failed removing whtmp dir %.*s (%d), " -+ "ignored.\n", AuDLNPair(a->h_dst), err); -+ } else { -+ au_nhash_wh_free(&a->thargs->whlist); -+ a->thargs->whlist = a->whlist; -+ a->whlist.nh_num = 0; -+ au_whtmp_kick_rmdir(dir, a->btgt, a->h_dst, a->thargs); -+ dput(a->h_dst); -+ a->thargs = NULL; -+ } -+ -+ return 0; -+} -+ -+/* make it 'opaque' dir. */ -+static int au_ren_diropq(struct au_ren_args *a) -+{ -+ int err; -+ struct dentry *diropq; -+ -+ err = 0; -+ a->src_bdiropq = au_dbdiropq(a->src_dentry); -+ a->src_hinode = au_hi(a->src_inode, a->btgt); -+ au_hn_imtx_lock_nested(a->src_hinode, AuLsc_I_CHILD); -+ diropq = au_diropq_create(a->src_dentry, a->btgt); -+ au_hn_imtx_unlock(a->src_hinode); -+ if (IS_ERR(diropq)) -+ err = PTR_ERR(diropq); -+ dput(diropq); -+ -+ return err; -+} -+ -+static int do_rename(struct au_ren_args *a) -+{ -+ int err; -+ struct dentry *d, *h_d; -+ -+ /* prepare workqueue args for asynchronous rmdir */ -+ h_d = a->dst_h_dentry; -+ if (au_ftest_ren(a->flags, ISDIR) && h_d->d_inode) { -+ err = -ENOMEM; -+ a->thargs = au_whtmp_rmdir_alloc(a->src_dentry->d_sb, GFP_NOFS); -+ if (unlikely(!a->thargs)) -+ goto out; -+ a->h_dst = dget(h_d); -+ } -+ -+ /* create whiteout for src_dentry */ -+ if (au_ftest_ren(a->flags, WHSRC)) { -+ a->src_bwh = au_dbwh(a->src_dentry); -+ AuDebugOn(a->src_bwh >= 0); -+ a->src_wh_dentry -+ = au_wh_create(a->src_dentry, a->btgt, a->src_h_parent); -+ err = PTR_ERR(a->src_wh_dentry); -+ if (IS_ERR(a->src_wh_dentry)) -+ goto out_thargs; -+ } -+ -+ /* lookup whiteout for dentry */ -+ if (au_ftest_ren(a->flags, WHDST)) { -+ h_d = au_wh_lkup(a->dst_h_parent, &a->dst_dentry->d_name, -+ a->br); -+ err = PTR_ERR(h_d); -+ if (IS_ERR(h_d)) -+ goto out_whsrc; -+ if (!h_d->d_inode) -+ dput(h_d); -+ else -+ a->dst_wh_dentry = h_d; -+ } -+ -+ /* rename dentry to tmpwh */ -+ if (a->thargs) { -+ err = au_whtmp_ren(a->dst_h_dentry, a->br); -+ if (unlikely(err)) -+ goto out_whdst; -+ -+ d = a->dst_dentry; -+ au_set_h_dptr(d, a->btgt, NULL); -+ err = au_lkup_neg(d, a->btgt); -+ if (unlikely(err)) -+ goto out_whtmp; -+ a->dst_h_dentry = au_h_dptr(d, a->btgt); -+ } -+ -+ /* cpup src */ -+ if (a->dst_h_dentry->d_inode && a->src_bstart != a->btgt) { -+ struct mutex *h_mtx = &a->src_h_dentry->d_inode->i_mutex; -+ struct file *h_file; -+ -+ mutex_lock_nested(h_mtx, AuLsc_I_CHILD); -+ AuDebugOn(au_dbstart(a->src_dentry) != a->src_bstart); -+ h_file = au_h_open_pre(a->src_dentry, a->src_bstart); -+ if (IS_ERR(h_file)) { -+ err = PTR_ERR(h_file); -+ h_file = NULL; -+ } else -+ err = au_sio_cpup_simple(a->src_dentry, a->btgt, -1, -+ !AuCpup_DTIME); -+ mutex_unlock(h_mtx); -+ au_h_open_post(a->src_dentry, a->src_bstart, h_file); -+ if (unlikely(err)) -+ goto out_whtmp; -+ } -+ -+ /* rename by vfs_rename or cpup */ -+ d = a->dst_dentry; -+ if (au_ftest_ren(a->flags, ISDIR) -+ && (a->dst_wh_dentry -+ || au_dbdiropq(d) == a->btgt -+ /* hide the lower to keep xino */ -+ || a->btgt < au_dbend(d) -+ || au_opt_test(au_mntflags(d->d_sb), ALWAYS_DIROPQ))) -+ au_fset_ren(a->flags, DIROPQ); -+ err = au_ren_or_cpup(a); -+ if (unlikely(err)) -+ /* leave the copied-up one */ -+ goto out_whtmp; -+ -+ /* make dir opaque */ -+ if (au_ftest_ren(a->flags, DIROPQ)) { -+ err = au_ren_diropq(a); -+ if (unlikely(err)) -+ goto out_rename; -+ } -+ -+ /* update target timestamps */ -+ AuDebugOn(au_dbstart(a->src_dentry) != a->btgt); -+ a->h_path.dentry = au_h_dptr(a->src_dentry, a->btgt); -+ vfsub_update_h_iattr(&a->h_path, /*did*/NULL); /*ignore*/ -+ a->src_inode->i_ctime = a->h_path.dentry->d_inode->i_ctime; -+ -+ /* remove whiteout for dentry */ -+ if (a->dst_wh_dentry) { -+ a->h_path.dentry = a->dst_wh_dentry; -+ err = au_wh_unlink_dentry(a->dst_h_dir, &a->h_path, -+ a->dst_dentry); -+ if (unlikely(err)) -+ goto out_diropq; -+ } -+ -+ /* remove whtmp */ -+ if (a->thargs) -+ au_ren_del_whtmp(a); /* ignore this error */ -+ -+ err = 0; -+ goto out_success; -+ -+out_diropq: -+ if (au_ftest_ren(a->flags, DIROPQ)) -+ au_ren_rev_diropq(err, a); -+out_rename: -+ if (!au_ftest_ren(a->flags, CPUP)) -+ au_ren_rev_rename(err, a); -+ else -+ au_ren_rev_cpup(err, a); -+ dput(a->h_dst); -+out_whtmp: -+ if (a->thargs) -+ au_ren_rev_whtmp(err, a); -+out_whdst: -+ dput(a->dst_wh_dentry); -+ a->dst_wh_dentry = NULL; -+out_whsrc: -+ if (a->src_wh_dentry) -+ au_ren_rev_whsrc(err, a); -+out_success: -+ dput(a->src_wh_dentry); -+ dput(a->dst_wh_dentry); -+out_thargs: -+ if (a->thargs) { -+ dput(a->h_dst); -+ au_whtmp_rmdir_free(a->thargs); -+ a->thargs = NULL; -+ } -+out: -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * test if @dentry dir can be rename destination or not. -+ * success means, it is a logically empty dir. -+ */ -+static int may_rename_dstdir(struct dentry *dentry, struct au_nhash *whlist) -+{ -+ return au_test_empty(dentry, whlist); -+} -+ -+/* -+ * test if @dentry dir can be rename source or not. -+ * if it can, return 0 and @children is filled. -+ * success means, -+ * - it is a logically empty dir. -+ * - or, it exists on writable branch and has no children including whiteouts -+ * on the lower branch. -+ */ -+static int may_rename_srcdir(struct dentry *dentry, aufs_bindex_t btgt) -+{ -+ int err; -+ unsigned int rdhash; -+ aufs_bindex_t bstart; -+ -+ bstart = au_dbstart(dentry); -+ if (bstart != btgt) { -+ struct au_nhash whlist; -+ -+ SiMustAnyLock(dentry->d_sb); -+ rdhash = au_sbi(dentry->d_sb)->si_rdhash; -+ if (!rdhash) -+ rdhash = au_rdhash_est(au_dir_size(/*file*/NULL, -+ dentry)); -+ err = au_nhash_alloc(&whlist, rdhash, GFP_NOFS); -+ if (unlikely(err)) -+ goto out; -+ err = au_test_empty(dentry, &whlist); -+ au_nhash_wh_free(&whlist); -+ goto out; -+ } -+ -+ if (bstart == au_dbtaildir(dentry)) -+ return 0; /* success */ -+ -+ err = au_test_empty_lower(dentry); -+ -+out: -+ if (err == -ENOTEMPTY) { -+ AuWarn1("renaming dir who has child(ren) on multiple branches," -+ " is not supported\n"); -+ err = -EXDEV; -+ } -+ return err; -+} -+ -+/* side effect: sets whlist and h_dentry */ -+static int au_ren_may_dir(struct au_ren_args *a) -+{ -+ int err; -+ unsigned int rdhash; -+ struct dentry *d; -+ -+ d = a->dst_dentry; -+ SiMustAnyLock(d->d_sb); -+ -+ err = 0; -+ if (au_ftest_ren(a->flags, ISDIR) && a->dst_inode) { -+ rdhash = au_sbi(d->d_sb)->si_rdhash; -+ if (!rdhash) -+ rdhash = au_rdhash_est(au_dir_size(/*file*/NULL, d)); -+ err = au_nhash_alloc(&a->whlist, rdhash, GFP_NOFS); -+ if (unlikely(err)) -+ goto out; -+ -+ au_set_dbstart(d, a->dst_bstart); -+ err = may_rename_dstdir(d, &a->whlist); -+ au_set_dbstart(d, a->btgt); -+ } -+ a->dst_h_dentry = au_h_dptr(d, au_dbstart(d)); -+ if (unlikely(err)) -+ goto out; -+ -+ d = a->src_dentry; -+ a->src_h_dentry = au_h_dptr(d, au_dbstart(d)); -+ if (au_ftest_ren(a->flags, ISDIR)) { -+ err = may_rename_srcdir(d, a->btgt); -+ if (unlikely(err)) { -+ au_nhash_wh_free(&a->whlist); -+ a->whlist.nh_num = 0; -+ } -+ } -+out: -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * simple tests for rename. -+ * following the checks in vfs, plus the parent-child relationship. -+ */ -+static int au_may_ren(struct au_ren_args *a) -+{ -+ int err, isdir; -+ struct inode *h_inode; -+ -+ if (a->src_bstart == a->btgt) { -+ err = au_may_del(a->src_dentry, a->btgt, a->src_h_parent, -+ au_ftest_ren(a->flags, ISDIR)); -+ if (unlikely(err)) -+ goto out; -+ err = -EINVAL; -+ if (unlikely(a->src_h_dentry == a->h_trap)) -+ goto out; -+ } -+ -+ err = 0; -+ if (a->dst_bstart != a->btgt) -+ goto out; -+ -+ err = -EIO; -+ h_inode = a->dst_h_dentry->d_inode; -+ isdir = !!au_ftest_ren(a->flags, ISDIR); -+ if (!a->dst_dentry->d_inode) { -+ if (unlikely(h_inode)) -+ goto out; -+ err = au_may_add(a->dst_dentry, a->btgt, a->dst_h_parent, -+ isdir); -+ } else { -+ if (unlikely(!h_inode || !h_inode->i_nlink)) -+ goto out; -+ err = au_may_del(a->dst_dentry, a->btgt, a->dst_h_parent, -+ isdir); -+ if (unlikely(err)) -+ goto out; -+ err = -ENOTEMPTY; -+ if (unlikely(a->dst_h_dentry == a->h_trap)) -+ goto out; -+ err = 0; -+ } -+ -+out: -+ if (unlikely(err == -ENOENT || err == -EEXIST)) -+ err = -EIO; -+ AuTraceErr(err); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * locking order -+ * (VFS) -+ * - src_dir and dir by lock_rename() -+ * - inode if exitsts -+ * (aufs) -+ * - lock all -+ * + src_dentry and dentry by aufs_read_and_write_lock2() which calls, -+ * + si_read_lock -+ * + di_write_lock2_child() -+ * + di_write_lock_child() -+ * + ii_write_lock_child() -+ * + di_write_lock_child2() -+ * + ii_write_lock_child2() -+ * + src_parent and parent -+ * + di_write_lock_parent() -+ * + ii_write_lock_parent() -+ * + di_write_lock_parent2() -+ * + ii_write_lock_parent2() -+ * + lower src_dir and dir by vfsub_lock_rename() -+ * + verify the every relationships between child and parent. if any -+ * of them failed, unlock all and return -EBUSY. -+ */ -+static void au_ren_unlock(struct au_ren_args *a) -+{ -+ struct super_block *sb; -+ -+ sb = a->dst_dentry->d_sb; -+ if (au_ftest_ren(a->flags, MNT_WRITE)) -+ mnt_drop_write(a->br->br_mnt); -+ vfsub_unlock_rename(a->src_h_parent, a->src_hdir, -+ a->dst_h_parent, a->dst_hdir); -+} -+ -+static int au_ren_lock(struct au_ren_args *a) -+{ -+ int err; -+ unsigned int udba; -+ -+ err = 0; -+ a->src_h_parent = au_h_dptr(a->src_parent, a->btgt); -+ a->src_hdir = au_hi(a->src_dir, a->btgt); -+ a->dst_h_parent = au_h_dptr(a->dst_parent, a->btgt); -+ a->dst_hdir = au_hi(a->dst_dir, a->btgt); -+ a->h_trap = vfsub_lock_rename(a->src_h_parent, a->src_hdir, -+ a->dst_h_parent, a->dst_hdir); -+ udba = au_opt_udba(a->src_dentry->d_sb); -+ if (unlikely(a->src_hdir->hi_inode != a->src_h_parent->d_inode -+ || a->dst_hdir->hi_inode != a->dst_h_parent->d_inode)) -+ err = au_busy_or_stale(); -+ if (!err && au_dbstart(a->src_dentry) == a->btgt) -+ err = au_h_verify(a->src_h_dentry, udba, -+ a->src_h_parent->d_inode, a->src_h_parent, -+ a->br); -+ if (!err && au_dbstart(a->dst_dentry) == a->btgt) -+ err = au_h_verify(a->dst_h_dentry, udba, -+ a->dst_h_parent->d_inode, a->dst_h_parent, -+ a->br); -+ if (!err) { -+ err = mnt_want_write(a->br->br_mnt); -+ if (unlikely(err)) -+ goto out_unlock; -+ au_fset_ren(a->flags, MNT_WRITE); -+ goto out; /* success */ -+ } -+ -+ err = au_busy_or_stale(); -+ -+out_unlock: -+ au_ren_unlock(a); -+out: -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static void au_ren_refresh_dir(struct au_ren_args *a) -+{ -+ struct inode *dir; -+ -+ dir = a->dst_dir; -+ dir->i_version++; -+ if (au_ftest_ren(a->flags, ISDIR)) { -+ /* is this updating defined in POSIX? */ -+ au_cpup_attr_timesizes(a->src_inode); -+ au_cpup_attr_nlink(dir, /*force*/1); -+ } -+ -+ if (au_ibstart(dir) == a->btgt) -+ au_cpup_attr_timesizes(dir); -+ -+ if (au_ftest_ren(a->flags, ISSAMEDIR)) -+ return; -+ -+ dir = a->src_dir; -+ dir->i_version++; -+ if (au_ftest_ren(a->flags, ISDIR)) -+ au_cpup_attr_nlink(dir, /*force*/1); -+ if (au_ibstart(dir) == a->btgt) -+ au_cpup_attr_timesizes(dir); -+} -+ -+static void au_ren_refresh(struct au_ren_args *a) -+{ -+ aufs_bindex_t bend, bindex; -+ struct dentry *d, *h_d; -+ struct inode *i, *h_i; -+ struct super_block *sb; -+ -+ d = a->dst_dentry; -+ d_drop(d); -+ if (a->h_dst) -+ /* already dget-ed by au_ren_or_cpup() */ -+ au_set_h_dptr(d, a->btgt, a->h_dst); -+ -+ i = a->dst_inode; -+ if (i) { -+ if (!au_ftest_ren(a->flags, ISDIR)) -+ vfsub_drop_nlink(i); -+ else { -+ vfsub_dead_dir(i); -+ au_cpup_attr_timesizes(i); -+ } -+ au_update_dbrange(d, /*do_put_zero*/1); -+ } else { -+ bend = a->btgt; -+ for (bindex = au_dbstart(d); bindex < bend; bindex++) -+ au_set_h_dptr(d, bindex, NULL); -+ bend = au_dbend(d); -+ for (bindex = a->btgt + 1; bindex <= bend; bindex++) -+ au_set_h_dptr(d, bindex, NULL); -+ au_update_dbrange(d, /*do_put_zero*/0); -+ } -+ -+ d = a->src_dentry; -+ au_set_dbwh(d, -1); -+ bend = au_dbend(d); -+ for (bindex = a->btgt + 1; bindex <= bend; bindex++) { -+ h_d = au_h_dptr(d, bindex); -+ if (h_d) -+ au_set_h_dptr(d, bindex, NULL); -+ } -+ au_set_dbend(d, a->btgt); -+ -+ sb = d->d_sb; -+ i = a->src_inode; -+ if (au_opt_test(au_mntflags(sb), PLINK) && au_plink_test(i)) -+ return; /* success */ -+ -+ bend = au_ibend(i); -+ for (bindex = a->btgt + 1; bindex <= bend; bindex++) { -+ h_i = au_h_iptr(i, bindex); -+ if (h_i) { -+ au_xino_write(sb, bindex, h_i->i_ino, /*ino*/0); -+ /* ignore this error */ -+ au_set_h_iptr(i, bindex, NULL, 0); -+ } -+ } -+ au_set_ibend(i, a->btgt); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* mainly for link(2) and rename(2) */ -+int au_wbr(struct dentry *dentry, aufs_bindex_t btgt) -+{ -+ aufs_bindex_t bdiropq, bwh; -+ struct dentry *parent; -+ struct au_branch *br; -+ -+ parent = dentry->d_parent; -+ IMustLock(parent->d_inode); /* dir is locked */ -+ -+ bdiropq = au_dbdiropq(parent); -+ bwh = au_dbwh(dentry); -+ br = au_sbr(dentry->d_sb, btgt); -+ if (au_br_rdonly(br) -+ || (0 <= bdiropq && bdiropq < btgt) -+ || (0 <= bwh && bwh < btgt)) -+ btgt = -1; -+ -+ AuDbg("btgt %d\n", btgt); -+ return btgt; -+} -+ -+/* sets src_bstart, dst_bstart and btgt */ -+static int au_ren_wbr(struct au_ren_args *a) -+{ -+ int err; -+ struct au_wr_dir_args wr_dir_args = { -+ /* .force_btgt = -1, */ -+ .flags = AuWrDir_ADD_ENTRY -+ }; -+ -+ a->src_bstart = au_dbstart(a->src_dentry); -+ a->dst_bstart = au_dbstart(a->dst_dentry); -+ if (au_ftest_ren(a->flags, ISDIR)) -+ au_fset_wrdir(wr_dir_args.flags, ISDIR); -+ wr_dir_args.force_btgt = a->src_bstart; -+ if (a->dst_inode && a->dst_bstart < a->src_bstart) -+ wr_dir_args.force_btgt = a->dst_bstart; -+ wr_dir_args.force_btgt = au_wbr(a->dst_dentry, wr_dir_args.force_btgt); -+ err = au_wr_dir(a->dst_dentry, a->src_dentry, &wr_dir_args); -+ a->btgt = err; -+ -+ return err; -+} -+ -+static void au_ren_dt(struct au_ren_args *a) -+{ -+ a->h_path.dentry = a->src_h_parent; -+ au_dtime_store(a->src_dt + AuPARENT, a->src_parent, &a->h_path); -+ if (!au_ftest_ren(a->flags, ISSAMEDIR)) { -+ a->h_path.dentry = a->dst_h_parent; -+ au_dtime_store(a->dst_dt + AuPARENT, a->dst_parent, &a->h_path); -+ } -+ -+ au_fclr_ren(a->flags, DT_DSTDIR); -+ if (!au_ftest_ren(a->flags, ISDIR)) -+ return; -+ -+ a->h_path.dentry = a->src_h_dentry; -+ au_dtime_store(a->src_dt + AuCHILD, a->src_dentry, &a->h_path); -+ if (a->dst_h_dentry->d_inode) { -+ au_fset_ren(a->flags, DT_DSTDIR); -+ a->h_path.dentry = a->dst_h_dentry; -+ au_dtime_store(a->dst_dt + AuCHILD, a->dst_dentry, &a->h_path); -+ } -+} -+ -+static void au_ren_rev_dt(int err, struct au_ren_args *a) -+{ -+ struct dentry *h_d; -+ struct mutex *h_mtx; -+ -+ au_dtime_revert(a->src_dt + AuPARENT); -+ if (!au_ftest_ren(a->flags, ISSAMEDIR)) -+ au_dtime_revert(a->dst_dt + AuPARENT); -+ -+ if (au_ftest_ren(a->flags, ISDIR) && err != -EIO) { -+ h_d = a->src_dt[AuCHILD].dt_h_path.dentry; -+ h_mtx = &h_d->d_inode->i_mutex; -+ mutex_lock_nested(h_mtx, AuLsc_I_CHILD); -+ au_dtime_revert(a->src_dt + AuCHILD); -+ mutex_unlock(h_mtx); -+ -+ if (au_ftest_ren(a->flags, DT_DSTDIR)) { -+ h_d = a->dst_dt[AuCHILD].dt_h_path.dentry; -+ h_mtx = &h_d->d_inode->i_mutex; -+ mutex_lock_nested(h_mtx, AuLsc_I_CHILD); -+ au_dtime_revert(a->dst_dt + AuCHILD); -+ mutex_unlock(h_mtx); -+ } -+ } -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+int aufs_rename(struct inode *_src_dir, struct dentry *_src_dentry, -+ struct inode *_dst_dir, struct dentry *_dst_dentry) -+{ -+ int err, flags; -+ /* reduce stack space */ -+ struct au_ren_args *a; -+ -+ AuDbg("%.*s, %.*s\n", AuDLNPair(_src_dentry), AuDLNPair(_dst_dentry)); -+ IMustLock(_src_dir); -+ IMustLock(_dst_dir); -+ -+ err = -ENOMEM; -+ BUILD_BUG_ON(sizeof(*a) > PAGE_SIZE); -+ a = kzalloc(sizeof(*a), GFP_NOFS); -+ if (unlikely(!a)) -+ goto out; -+ -+ a->src_dir = _src_dir; -+ a->src_dentry = _src_dentry; -+ a->src_inode = a->src_dentry->d_inode; -+ a->src_parent = a->src_dentry->d_parent; /* dir inode is locked */ -+ a->dst_dir = _dst_dir; -+ a->dst_dentry = _dst_dentry; -+ a->dst_inode = a->dst_dentry->d_inode; -+ a->dst_parent = a->dst_dentry->d_parent; /* dir inode is locked */ -+ if (a->dst_inode) { -+ IMustLock(a->dst_inode); -+ au_igrab(a->dst_inode); -+ } -+ -+ err = -ENOTDIR; -+ flags = AuLock_FLUSH | AuLock_NOPLM | AuLock_GEN; -+ if (S_ISDIR(a->src_inode->i_mode)) { -+ au_fset_ren(a->flags, ISDIR); -+ if (unlikely(a->dst_inode && !S_ISDIR(a->dst_inode->i_mode))) -+ goto out_free; -+ err = aufs_read_and_write_lock2(a->dst_dentry, a->src_dentry, -+ AuLock_DIR | flags); -+ } else -+ err = aufs_read_and_write_lock2(a->dst_dentry, a->src_dentry, -+ flags); -+ if (unlikely(err)) -+ goto out_free; -+ -+ err = au_d_hashed_positive(a->src_dentry); -+ if (unlikely(err)) -+ goto out_unlock; -+ err = -ENOENT; -+ if (a->dst_inode) { -+ /* -+ * If it is a dir, VFS unhash dst_dentry before this -+ * function. It means we cannot rely upon d_unhashed(). -+ */ -+ if (unlikely(!a->dst_inode->i_nlink)) -+ goto out_unlock; -+ if (!S_ISDIR(a->dst_inode->i_mode)) { -+ err = au_d_hashed_positive(a->dst_dentry); -+ if (unlikely(err)) -+ goto out_unlock; -+ } else if (unlikely(IS_DEADDIR(a->dst_inode))) -+ goto out_unlock; -+ } else if (unlikely(d_unhashed(a->dst_dentry))) -+ goto out_unlock; -+ -+ au_fset_ren(a->flags, ISSAMEDIR); /* temporary */ -+ di_write_lock_parent(a->dst_parent); -+ -+ /* which branch we process */ -+ err = au_ren_wbr(a); -+ if (unlikely(err < 0)) -+ goto out_parent; -+ a->br = au_sbr(a->dst_dentry->d_sb, a->btgt); -+ a->h_path.mnt = a->br->br_mnt; -+ -+ /* are they available to be renamed */ -+ err = au_ren_may_dir(a); -+ if (unlikely(err)) -+ goto out_children; -+ -+ /* prepare the writable parent dir on the same branch */ -+ if (a->dst_bstart == a->btgt) { -+ au_fset_ren(a->flags, WHDST); -+ } else { -+ err = au_cpup_dirs(a->dst_dentry, a->btgt); -+ if (unlikely(err)) -+ goto out_children; -+ } -+ -+ if (a->src_dir != a->dst_dir) { -+ /* -+ * this temporary unlock is safe, -+ * because both dir->i_mutex are locked. -+ */ -+ di_write_unlock(a->dst_parent); -+ di_write_lock_parent(a->src_parent); -+ err = au_wr_dir_need_wh(a->src_dentry, -+ au_ftest_ren(a->flags, ISDIR), -+ &a->btgt); -+ di_write_unlock(a->src_parent); -+ di_write_lock2_parent(a->src_parent, a->dst_parent, /*isdir*/1); -+ au_fclr_ren(a->flags, ISSAMEDIR); -+ } else -+ err = au_wr_dir_need_wh(a->src_dentry, -+ au_ftest_ren(a->flags, ISDIR), -+ &a->btgt); -+ if (unlikely(err < 0)) -+ goto out_children; -+ if (err) -+ au_fset_ren(a->flags, WHSRC); -+ -+ /* lock them all */ -+ err = au_ren_lock(a); -+ if (unlikely(err)) -+ goto out_children; -+ -+ if (!au_opt_test(au_mntflags(a->dst_dir->i_sb), UDBA_NONE)) -+ err = au_may_ren(a); -+ else if (unlikely(a->dst_dentry->d_name.len > AUFS_MAX_NAMELEN)) -+ err = -ENAMETOOLONG; -+ if (unlikely(err)) -+ goto out_hdir; -+ -+ /* store timestamps to be revertible */ -+ au_ren_dt(a); -+ -+ /* here we go */ -+ err = do_rename(a); -+ if (unlikely(err)) -+ goto out_dt; -+ -+ /* update dir attributes */ -+ au_ren_refresh_dir(a); -+ -+ /* dput/iput all lower dentries */ -+ au_ren_refresh(a); -+ -+ goto out_hdir; /* success */ -+ -+out_dt: -+ au_ren_rev_dt(err, a); -+out_hdir: -+ au_ren_unlock(a); -+out_children: -+ au_nhash_wh_free(&a->whlist); -+ if (err && a->dst_inode && a->dst_bstart != a->btgt) { -+ AuDbg("bstart %d, btgt %d\n", a->dst_bstart, a->btgt); -+ au_set_h_dptr(a->dst_dentry, a->btgt, NULL); -+ au_set_dbstart(a->dst_dentry, a->dst_bstart); -+ } -+out_parent: -+ if (!err) -+ d_move(a->src_dentry, a->dst_dentry); -+ else { -+ au_update_dbstart(a->dst_dentry); -+ if (!a->dst_inode) -+ d_drop(a->dst_dentry); -+ } -+ if (au_ftest_ren(a->flags, ISSAMEDIR)) -+ di_write_unlock(a->dst_parent); -+ else -+ di_write_unlock2(a->src_parent, a->dst_parent); -+out_unlock: -+ aufs_read_and_write_unlock2(a->dst_dentry, a->src_dentry); -+out_free: -+ iput(a->dst_inode); -+ if (a->thargs) -+ au_whtmp_rmdir_free(a->thargs); -+ kfree(a); -+out: -+ AuTraceErr(err); -+ return err; -+} -diff -Nur linux-2.6.36.orig/fs/aufs/iinfo.c linux-2.6.36/fs/aufs/iinfo.c ---- linux-2.6.36.orig/fs/aufs/iinfo.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/iinfo.c 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,263 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * inode private data -+ */ -+ -+#include "aufs.h" -+ -+struct inode *au_h_iptr(struct inode *inode, aufs_bindex_t bindex) -+{ -+ struct inode *h_inode; -+ -+ IiMustAnyLock(inode); -+ -+ h_inode = au_ii(inode)->ii_hinode[0 + bindex].hi_inode; -+ AuDebugOn(h_inode && atomic_read(&h_inode->i_count) <= 0); -+ return h_inode; -+} -+ -+/* todo: hard/soft set? */ -+void au_hiput(struct au_hinode *hinode) -+{ -+ au_hn_free(hinode); -+ dput(hinode->hi_whdentry); -+ iput(hinode->hi_inode); -+} -+ -+unsigned int au_hi_flags(struct inode *inode, int isdir) -+{ -+ unsigned int flags; -+ const unsigned int mnt_flags = au_mntflags(inode->i_sb); -+ -+ flags = 0; -+ if (au_opt_test(mnt_flags, XINO)) -+ au_fset_hi(flags, XINO); -+ if (isdir && au_opt_test(mnt_flags, UDBA_HNOTIFY)) -+ au_fset_hi(flags, HNOTIFY); -+ return flags; -+} -+ -+void au_set_h_iptr(struct inode *inode, aufs_bindex_t bindex, -+ struct inode *h_inode, unsigned int flags) -+{ -+ struct au_hinode *hinode; -+ struct inode *hi; -+ struct au_iinfo *iinfo = au_ii(inode); -+ -+ IiMustWriteLock(inode); -+ -+ hinode = iinfo->ii_hinode + bindex; -+ hi = hinode->hi_inode; -+ AuDebugOn(h_inode && atomic_read(&h_inode->i_count) <= 0); -+ -+ if (hi) -+ au_hiput(hinode); -+ hinode->hi_inode = h_inode; -+ if (h_inode) { -+ int err; -+ struct super_block *sb = inode->i_sb; -+ struct au_branch *br; -+ -+ AuDebugOn(inode->i_mode -+ && (h_inode->i_mode & S_IFMT) -+ != (inode->i_mode & S_IFMT)); -+ if (bindex == iinfo->ii_bstart) -+ au_cpup_igen(inode, h_inode); -+ br = au_sbr(sb, bindex); -+ hinode->hi_id = br->br_id; -+ if (au_ftest_hi(flags, XINO)) { -+ err = au_xino_write(sb, bindex, h_inode->i_ino, -+ inode->i_ino); -+ if (unlikely(err)) -+ AuIOErr1("failed au_xino_write() %d\n", err); -+ } -+ -+ if (au_ftest_hi(flags, HNOTIFY) -+ && au_br_hnotifyable(br->br_perm)) { -+ err = au_hn_alloc(hinode, inode); -+ if (unlikely(err)) -+ AuIOErr1("au_hn_alloc() %d\n", err); -+ } -+ } -+} -+ -+void au_set_hi_wh(struct inode *inode, aufs_bindex_t bindex, -+ struct dentry *h_wh) -+{ -+ struct au_hinode *hinode; -+ -+ IiMustWriteLock(inode); -+ -+ hinode = au_ii(inode)->ii_hinode + bindex; -+ AuDebugOn(hinode->hi_whdentry); -+ hinode->hi_whdentry = h_wh; -+} -+ -+void au_update_iigen(struct inode *inode) -+{ -+ atomic_set(&au_ii(inode)->ii_generation, au_sigen(inode->i_sb)); -+ /* smp_mb(); */ /* atomic_set */ -+} -+ -+/* it may be called at remount time, too */ -+void au_update_ibrange(struct inode *inode, int do_put_zero) -+{ -+ struct au_iinfo *iinfo; -+ aufs_bindex_t bindex, bend; -+ -+ iinfo = au_ii(inode); -+ if (!iinfo) -+ return; -+ -+ IiMustWriteLock(inode); -+ -+ if (do_put_zero && iinfo->ii_bstart >= 0) { -+ for (bindex = iinfo->ii_bstart; bindex <= iinfo->ii_bend; -+ bindex++) { -+ struct inode *h_i; -+ -+ h_i = iinfo->ii_hinode[0 + bindex].hi_inode; -+ if (h_i && !h_i->i_nlink) -+ au_set_h_iptr(inode, bindex, NULL, 0); -+ } -+ } -+ -+ iinfo->ii_bstart = -1; -+ iinfo->ii_bend = -1; -+ bend = au_sbend(inode->i_sb); -+ for (bindex = 0; bindex <= bend; bindex++) -+ if (iinfo->ii_hinode[0 + bindex].hi_inode) { -+ iinfo->ii_bstart = bindex; -+ break; -+ } -+ if (iinfo->ii_bstart >= 0) -+ for (bindex = bend; bindex >= iinfo->ii_bstart; bindex--) -+ if (iinfo->ii_hinode[0 + bindex].hi_inode) { -+ iinfo->ii_bend = bindex; -+ break; -+ } -+ AuDebugOn(iinfo->ii_bstart > iinfo->ii_bend); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+void au_icntnr_init_once(void *_c) -+{ -+ struct au_icntnr *c = _c; -+ struct au_iinfo *iinfo = &c->iinfo; -+ static struct lock_class_key aufs_ii; -+ -+ au_rw_init(&iinfo->ii_rwsem); -+ au_rw_class(&iinfo->ii_rwsem, &aufs_ii); -+ inode_init_once(&c->vfs_inode); -+} -+ -+int au_iinfo_init(struct inode *inode) -+{ -+ struct au_iinfo *iinfo; -+ struct super_block *sb; -+ int nbr, i; -+ -+ sb = inode->i_sb; -+ iinfo = &(container_of(inode, struct au_icntnr, vfs_inode)->iinfo); -+ nbr = au_sbend(sb) + 1; -+ if (unlikely(nbr <= 0)) -+ nbr = 1; -+ iinfo->ii_hinode = kcalloc(nbr, sizeof(*iinfo->ii_hinode), GFP_NOFS); -+ if (iinfo->ii_hinode) { -+ au_ninodes_inc(sb); -+ for (i = 0; i < nbr; i++) -+ iinfo->ii_hinode[i].hi_id = -1; -+ -+ atomic_set(&iinfo->ii_generation, au_sigen(sb)); -+ /* smp_mb(); */ /* atomic_set */ -+ iinfo->ii_bstart = -1; -+ iinfo->ii_bend = -1; -+ iinfo->ii_vdir = NULL; -+ return 0; -+ } -+ return -ENOMEM; -+} -+ -+int au_ii_realloc(struct au_iinfo *iinfo, int nbr) -+{ -+ int err, sz; -+ struct au_hinode *hip; -+ -+ AuRwMustWriteLock(&iinfo->ii_rwsem); -+ -+ err = -ENOMEM; -+ sz = sizeof(*hip) * (iinfo->ii_bend + 1); -+ if (!sz) -+ sz = sizeof(*hip); -+ hip = au_kzrealloc(iinfo->ii_hinode, sz, sizeof(*hip) * nbr, GFP_NOFS); -+ if (hip) { -+ iinfo->ii_hinode = hip; -+ err = 0; -+ } -+ -+ return err; -+} -+ -+void au_iinfo_fin(struct inode *inode) -+{ -+ struct au_iinfo *iinfo; -+ struct au_hinode *hi; -+ struct super_block *sb; -+ aufs_bindex_t bindex, bend; -+ const unsigned char unlinked = !inode->i_nlink; -+ -+ iinfo = au_ii(inode); -+ /* bad_inode case */ -+ if (!iinfo) -+ return; -+ -+ sb = inode->i_sb; -+ au_ninodes_dec(sb); -+ if (si_pid_test(sb)) -+ au_xino_delete_inode(inode, unlinked); -+ else { -+ /* -+ * it is safe to hide the dependency between sbinfo and -+ * sb->s_umount. -+ */ -+ lockdep_off(); -+ si_noflush_read_lock(sb); -+ au_xino_delete_inode(inode, unlinked); -+ si_read_unlock(sb); -+ lockdep_on(); -+ } -+ -+ if (iinfo->ii_vdir) -+ au_vdir_free(iinfo->ii_vdir); -+ -+ bindex = iinfo->ii_bstart; -+ if (bindex >= 0) { -+ hi = iinfo->ii_hinode + bindex; -+ bend = iinfo->ii_bend; -+ while (bindex++ <= bend) { -+ if (hi->hi_inode) -+ au_hiput(hi); -+ hi++; -+ } -+ } -+ kfree(iinfo->ii_hinode); -+ AuRwDestroy(&iinfo->ii_rwsem); -+} -diff -Nur linux-2.6.36.orig/fs/aufs/inode.c linux-2.6.36/fs/aufs/inode.c ---- linux-2.6.36.orig/fs/aufs/inode.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/inode.c 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,471 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * inode functions -+ */ -+ -+#include "aufs.h" -+ -+struct inode *au_igrab(struct inode *inode) -+{ -+ if (inode) { -+ AuDebugOn(!atomic_read(&inode->i_count)); -+ atomic_inc(&inode->i_count); -+ } -+ return inode; -+} -+ -+static void au_refresh_hinode_attr(struct inode *inode, int do_version) -+{ -+ au_cpup_attr_all(inode, /*force*/0); -+ au_update_iigen(inode); -+ if (do_version) -+ inode->i_version++; -+} -+ -+static int au_ii_refresh(struct inode *inode, int *update) -+{ -+ int err, e; -+ umode_t type; -+ aufs_bindex_t bindex, new_bindex; -+ struct super_block *sb; -+ struct au_iinfo *iinfo; -+ struct au_hinode *p, *q, tmp; -+ -+ IiMustWriteLock(inode); -+ -+ *update = 0; -+ sb = inode->i_sb; -+ type = inode->i_mode & S_IFMT; -+ iinfo = au_ii(inode); -+ err = au_ii_realloc(iinfo, au_sbend(sb) + 1); -+ if (unlikely(err)) -+ goto out; -+ -+ AuDebugOn(iinfo->ii_bstart < 0); -+ p = iinfo->ii_hinode + iinfo->ii_bstart; -+ for (bindex = iinfo->ii_bstart; bindex <= iinfo->ii_bend; -+ bindex++, p++) { -+ if (!p->hi_inode) -+ continue; -+ -+ AuDebugOn(type != (p->hi_inode->i_mode & S_IFMT)); -+ new_bindex = au_br_index(sb, p->hi_id); -+ if (new_bindex == bindex) -+ continue; -+ -+ if (new_bindex < 0) { -+ *update = 1; -+ au_hiput(p); -+ p->hi_inode = NULL; -+ continue; -+ } -+ -+ if (new_bindex < iinfo->ii_bstart) -+ iinfo->ii_bstart = new_bindex; -+ if (iinfo->ii_bend < new_bindex) -+ iinfo->ii_bend = new_bindex; -+ /* swap two lower inode, and loop again */ -+ q = iinfo->ii_hinode + new_bindex; -+ tmp = *q; -+ *q = *p; -+ *p = tmp; -+ if (tmp.hi_inode) { -+ bindex--; -+ p--; -+ } -+ } -+ au_update_ibrange(inode, /*do_put_zero*/0); -+ e = au_dy_irefresh(inode); -+ if (unlikely(e && !err)) -+ err = e; -+ -+out: -+ AuTraceErr(err); -+ return err; -+} -+ -+int au_refresh_hinode_self(struct inode *inode) -+{ -+ int err, update; -+ -+ err = au_ii_refresh(inode, &update); -+ if (!err) -+ au_refresh_hinode_attr(inode, update && S_ISDIR(inode->i_mode)); -+ -+ AuTraceErr(err); -+ return err; -+} -+ -+int au_refresh_hinode(struct inode *inode, struct dentry *dentry) -+{ -+ int err, e, update; -+ unsigned int flags; -+ umode_t mode; -+ aufs_bindex_t bindex, bend; -+ unsigned char isdir; -+ struct au_hinode *p; -+ struct au_iinfo *iinfo; -+ -+ err = au_ii_refresh(inode, &update); -+ if (unlikely(err)) -+ goto out; -+ -+ update = 0; -+ iinfo = au_ii(inode); -+ p = iinfo->ii_hinode + iinfo->ii_bstart; -+ mode = (inode->i_mode & S_IFMT); -+ isdir = S_ISDIR(mode); -+ flags = au_hi_flags(inode, isdir); -+ bend = au_dbend(dentry); -+ for (bindex = au_dbstart(dentry); bindex <= bend; bindex++) { -+ struct inode *h_i; -+ struct dentry *h_d; -+ -+ h_d = au_h_dptr(dentry, bindex); -+ if (!h_d || !h_d->d_inode) -+ continue; -+ -+ AuDebugOn(mode != (h_d->d_inode->i_mode & S_IFMT)); -+ if (iinfo->ii_bstart <= bindex && bindex <= iinfo->ii_bend) { -+ h_i = au_h_iptr(inode, bindex); -+ if (h_i) { -+ if (h_i == h_d->d_inode) -+ continue; -+ err = -EIO; -+ break; -+ } -+ } -+ if (bindex < iinfo->ii_bstart) -+ iinfo->ii_bstart = bindex; -+ if (iinfo->ii_bend < bindex) -+ iinfo->ii_bend = bindex; -+ au_set_h_iptr(inode, bindex, au_igrab(h_d->d_inode), flags); -+ update = 1; -+ } -+ au_update_ibrange(inode, /*do_put_zero*/0); -+ e = au_dy_irefresh(inode); -+ if (unlikely(e && !err)) -+ err = e; -+ if (!err) -+ au_refresh_hinode_attr(inode, update && isdir); -+ -+out: -+ AuTraceErr(err); -+ return err; -+} -+ -+static int set_inode(struct inode *inode, struct dentry *dentry) -+{ -+ int err; -+ unsigned int flags; -+ umode_t mode; -+ aufs_bindex_t bindex, bstart, btail; -+ unsigned char isdir; -+ struct dentry *h_dentry; -+ struct inode *h_inode; -+ struct au_iinfo *iinfo; -+ -+ IiMustWriteLock(inode); -+ -+ err = 0; -+ isdir = 0; -+ bstart = au_dbstart(dentry); -+ h_inode = au_h_dptr(dentry, bstart)->d_inode; -+ mode = h_inode->i_mode; -+ switch (mode & S_IFMT) { -+ case S_IFREG: -+ btail = au_dbtail(dentry); -+ inode->i_op = &aufs_iop; -+ inode->i_fop = &aufs_file_fop; -+ err = au_dy_iaop(inode, bstart, h_inode); -+ if (unlikely(err)) -+ goto out; -+ break; -+ case S_IFDIR: -+ isdir = 1; -+ btail = au_dbtaildir(dentry); -+ inode->i_op = &aufs_dir_iop; -+ inode->i_fop = &aufs_dir_fop; -+ break; -+ case S_IFLNK: -+ btail = au_dbtail(dentry); -+ inode->i_op = &aufs_symlink_iop; -+ break; -+ case S_IFBLK: -+ case S_IFCHR: -+ case S_IFIFO: -+ case S_IFSOCK: -+ btail = au_dbtail(dentry); -+ inode->i_op = &aufs_iop; -+ au_init_special_fop(inode, mode, h_inode->i_rdev); -+ break; -+ default: -+ AuIOErr("Unknown file type 0%o\n", mode); -+ err = -EIO; -+ goto out; -+ } -+ -+ /* do not set hnotify for whiteouted dirs (SHWH mode) */ -+ flags = au_hi_flags(inode, isdir); -+ if (au_opt_test(au_mntflags(dentry->d_sb), SHWH) -+ && au_ftest_hi(flags, HNOTIFY) -+ && dentry->d_name.len > AUFS_WH_PFX_LEN -+ && !memcmp(dentry->d_name.name, AUFS_WH_PFX, AUFS_WH_PFX_LEN)) -+ au_fclr_hi(flags, HNOTIFY); -+ iinfo = au_ii(inode); -+ iinfo->ii_bstart = bstart; -+ iinfo->ii_bend = btail; -+ for (bindex = bstart; bindex <= btail; bindex++) { -+ h_dentry = au_h_dptr(dentry, bindex); -+ if (h_dentry) -+ au_set_h_iptr(inode, bindex, -+ au_igrab(h_dentry->d_inode), flags); -+ } -+ au_cpup_attr_all(inode, /*force*/1); -+ -+out: -+ return err; -+} -+ -+/* -+ * successful returns with iinfo write_locked -+ * minus: errno -+ * zero: success, matched -+ * plus: no error, but unmatched -+ */ -+static int reval_inode(struct inode *inode, struct dentry *dentry) -+{ -+ int err; -+ aufs_bindex_t bindex, bend; -+ struct inode *h_inode, *h_dinode; -+ -+ /* -+ * before this function, if aufs got any iinfo lock, it must be only -+ * one, the parent dir. -+ * it can happen by UDBA and the obsoleted inode number. -+ */ -+ err = -EIO; -+ if (unlikely(inode->i_ino == parent_ino(dentry))) -+ goto out; -+ -+ err = 1; -+ ii_write_lock_new_child(inode); -+ h_dinode = au_h_dptr(dentry, au_dbstart(dentry))->d_inode; -+ bend = au_ibend(inode); -+ for (bindex = au_ibstart(inode); bindex <= bend; bindex++) { -+ h_inode = au_h_iptr(inode, bindex); -+ if (h_inode && h_inode == h_dinode) { -+ err = 0; -+ if (au_iigen_test(inode, au_digen(dentry))) -+ err = au_refresh_hinode(inode, dentry); -+ break; -+ } -+ } -+ -+ if (unlikely(err)) -+ ii_write_unlock(inode); -+out: -+ return err; -+} -+ -+int au_ino(struct super_block *sb, aufs_bindex_t bindex, ino_t h_ino, -+ unsigned int d_type, ino_t *ino) -+{ -+ int err; -+ struct mutex *mtx; -+ -+ /* prevent hardlinked inode number from race condition */ -+ mtx = NULL; -+ if (d_type != DT_DIR) { -+ mtx = &au_sbr(sb, bindex)->br_xino.xi_nondir_mtx; -+ mutex_lock(mtx); -+ } -+ err = au_xino_read(sb, bindex, h_ino, ino); -+ if (unlikely(err)) -+ goto out; -+ -+ if (!*ino) { -+ err = -EIO; -+ *ino = au_xino_new_ino(sb); -+ if (unlikely(!*ino)) -+ goto out; -+ err = au_xino_write(sb, bindex, h_ino, *ino); -+ if (unlikely(err)) -+ goto out; -+ } -+ -+out: -+ if (mtx) -+ mutex_unlock(mtx); -+ return err; -+} -+ -+/* successful returns with iinfo write_locked */ -+/* todo: return with unlocked? */ -+struct inode *au_new_inode(struct dentry *dentry, int must_new) -+{ -+ struct inode *inode, *h_inode; -+ struct dentry *h_dentry; -+ struct super_block *sb; -+ struct mutex *mtx; -+ ino_t h_ino, ino; -+ int err; -+ aufs_bindex_t bstart; -+ -+ sb = dentry->d_sb; -+ bstart = au_dbstart(dentry); -+ h_dentry = au_h_dptr(dentry, bstart); -+ h_inode = h_dentry->d_inode; -+ h_ino = h_inode->i_ino; -+ -+ /* -+ * stop 'race'-ing between hardlinks under different -+ * parents. -+ */ -+ mtx = NULL; -+ if (!S_ISDIR(h_inode->i_mode)) -+ mtx = &au_sbr(sb, bstart)->br_xino.xi_nondir_mtx; -+ -+new_ino: -+ if (mtx) -+ mutex_lock(mtx); -+ err = au_xino_read(sb, bstart, h_ino, &ino); -+ inode = ERR_PTR(err); -+ if (unlikely(err)) -+ goto out; -+ -+ if (!ino) { -+ ino = au_xino_new_ino(sb); -+ if (unlikely(!ino)) { -+ inode = ERR_PTR(-EIO); -+ goto out; -+ } -+ } -+ -+ AuDbg("i%lu\n", (unsigned long)ino); -+ inode = au_iget_locked(sb, ino); -+ err = PTR_ERR(inode); -+ if (IS_ERR(inode)) -+ goto out; -+ -+ AuDbg("%lx, new %d\n", inode->i_state, !!(inode->i_state & I_NEW)); -+ if (inode->i_state & I_NEW) { -+ ii_write_lock_new_child(inode); -+ err = set_inode(inode, dentry); -+ if (!err) { -+ unlock_new_inode(inode); -+ goto out; /* success */ -+ } -+ -+ /* -+ * iget_failed() calls iput(), but we need to call -+ * ii_write_unlock() after iget_failed(). so dirty hack for -+ * i_count. -+ */ -+ atomic_inc(&inode->i_count); -+ iget_failed(inode); -+ ii_write_unlock(inode); -+ au_xino_write(sb, bstart, h_ino, /*ino*/0); -+ /* ignore this error */ -+ goto out_iput; -+ } else if (!must_new && !IS_DEADDIR(inode) && inode->i_nlink) { -+ /* -+ * horrible race condition between lookup, readdir and copyup -+ * (or something). -+ */ -+ if (mtx) -+ mutex_unlock(mtx); -+ err = reval_inode(inode, dentry); -+ if (unlikely(err < 0)) { -+ mtx = NULL; -+ goto out_iput; -+ } -+ -+ if (!err) { -+ mtx = NULL; -+ goto out; /* success */ -+ } else if (mtx) -+ mutex_lock(mtx); -+ } -+ -+ if (unlikely(au_test_fs_unique_ino(h_dentry->d_inode))) -+ AuWarn1("Warning: Un-notified UDBA or repeatedly renamed dir," -+ " b%d, %s, %.*s, hi%lu, i%lu.\n", -+ bstart, au_sbtype(h_dentry->d_sb), AuDLNPair(dentry), -+ (unsigned long)h_ino, (unsigned long)ino); -+ ino = 0; -+ err = au_xino_write(sb, bstart, h_ino, /*ino*/0); -+ if (!err) { -+ iput(inode); -+ if (mtx) -+ mutex_unlock(mtx); -+ goto new_ino; -+ } -+ -+out_iput: -+ iput(inode); -+ inode = ERR_PTR(err); -+out: -+ if (mtx) -+ mutex_unlock(mtx); -+ return inode; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+int au_test_ro(struct super_block *sb, aufs_bindex_t bindex, -+ struct inode *inode) -+{ -+ int err; -+ -+ err = au_br_rdonly(au_sbr(sb, bindex)); -+ -+ /* pseudo-link after flushed may happen out of bounds */ -+ if (!err -+ && inode -+ && au_ibstart(inode) <= bindex -+ && bindex <= au_ibend(inode)) { -+ /* -+ * permission check is unnecessary since vfsub routine -+ * will be called later -+ */ -+ struct inode *hi = au_h_iptr(inode, bindex); -+ if (hi) -+ err = IS_IMMUTABLE(hi) ? -EROFS : 0; -+ } -+ -+ return err; -+} -+ -+int au_test_h_perm(struct inode *h_inode, int mask) -+{ -+ if (!current_fsuid()) -+ return 0; -+ return inode_permission(h_inode, mask); -+} -+ -+int au_test_h_perm_sio(struct inode *h_inode, int mask) -+{ -+ if (au_test_nfs(h_inode->i_sb) -+ && (mask & MAY_WRITE) -+ && S_ISDIR(h_inode->i_mode)) -+ mask |= MAY_READ; /* force permission check */ -+ return au_test_h_perm(h_inode, mask); -+} -diff -Nur linux-2.6.36.orig/fs/aufs/inode.h linux-2.6.36/fs/aufs/inode.h ---- linux-2.6.36.orig/fs/aufs/inode.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/inode.h 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,546 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * inode operations -+ */ -+ -+#ifndef __AUFS_INODE_H__ -+#define __AUFS_INODE_H__ -+ -+#ifdef __KERNEL__ -+ -+#include -+#include -+#include -+#include "rwsem.h" -+ -+struct vfsmount; -+ -+struct au_hnotify { -+#ifdef CONFIG_AUFS_HNOTIFY -+#ifdef CONFIG_AUFS_HFSNOTIFY -+ /* never use fsnotify_add_vfsmount_mark() */ -+ struct fsnotify_mark hn_mark; -+ int hn_mark_dead; -+#endif -+ struct inode *hn_aufs_inode; /* no get/put */ -+#endif -+} ____cacheline_aligned_in_smp; -+ -+struct au_hinode { -+ struct inode *hi_inode; -+ aufs_bindex_t hi_id; -+#ifdef CONFIG_AUFS_HNOTIFY -+ struct au_hnotify *hi_notify; -+#endif -+ -+ /* reference to the copied-up whiteout with get/put */ -+ struct dentry *hi_whdentry; -+}; -+ -+struct au_vdir; -+struct au_iinfo { -+ atomic_t ii_generation; -+ struct super_block *ii_hsb1; /* no get/put */ -+ -+ struct au_rwsem ii_rwsem; -+ aufs_bindex_t ii_bstart, ii_bend; -+ __u32 ii_higen; -+ struct au_hinode *ii_hinode; -+ struct au_vdir *ii_vdir; -+}; -+ -+struct au_icntnr { -+ struct au_iinfo iinfo; -+ struct inode vfs_inode; -+} ____cacheline_aligned_in_smp; -+ -+/* au_pin flags */ -+#define AuPin_DI_LOCKED 1 -+#define AuPin_MNT_WRITE (1 << 1) -+#define au_ftest_pin(flags, name) ((flags) & AuPin_##name) -+#define au_fset_pin(flags, name) \ -+ do { (flags) |= AuPin_##name; } while (0) -+#define au_fclr_pin(flags, name) \ -+ do { (flags) &= ~AuPin_##name; } while (0) -+ -+struct au_pin { -+ /* input */ -+ struct dentry *dentry; -+ unsigned int udba; -+ unsigned char lsc_di, lsc_hi, flags; -+ aufs_bindex_t bindex; -+ -+ /* output */ -+ struct dentry *parent; -+ struct au_hinode *hdir; -+ struct vfsmount *h_mnt; -+}; -+ -+/* ---------------------------------------------------------------------- */ -+ -+static inline struct au_iinfo *au_ii(struct inode *inode) -+{ -+ struct au_iinfo *iinfo; -+ -+ iinfo = &(container_of(inode, struct au_icntnr, vfs_inode)->iinfo); -+ if (iinfo->ii_hinode) -+ return iinfo; -+ return NULL; /* debugging bad_inode case */ -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* inode.c */ -+struct inode *au_igrab(struct inode *inode); -+int au_refresh_hinode_self(struct inode *inode); -+int au_refresh_hinode(struct inode *inode, struct dentry *dentry); -+int au_ino(struct super_block *sb, aufs_bindex_t bindex, ino_t h_ino, -+ unsigned int d_type, ino_t *ino); -+struct inode *au_new_inode(struct dentry *dentry, int must_new); -+int au_test_ro(struct super_block *sb, aufs_bindex_t bindex, -+ struct inode *inode); -+int au_test_h_perm(struct inode *h_inode, int mask); -+int au_test_h_perm_sio(struct inode *h_inode, int mask); -+ -+static inline int au_wh_ino(struct super_block *sb, aufs_bindex_t bindex, -+ ino_t h_ino, unsigned int d_type, ino_t *ino) -+{ -+#ifdef CONFIG_AUFS_SHWH -+ return au_ino(sb, bindex, h_ino, d_type, ino); -+#else -+ return 0; -+#endif -+} -+ -+/* i_op.c */ -+extern struct inode_operations aufs_iop, aufs_symlink_iop, aufs_dir_iop; -+ -+/* au_wr_dir flags */ -+#define AuWrDir_ADD_ENTRY 1 -+#define AuWrDir_ISDIR (1 << 1) -+#define au_ftest_wrdir(flags, name) ((flags) & AuWrDir_##name) -+#define au_fset_wrdir(flags, name) \ -+ do { (flags) |= AuWrDir_##name; } while (0) -+#define au_fclr_wrdir(flags, name) \ -+ do { (flags) &= ~AuWrDir_##name; } while (0) -+ -+struct au_wr_dir_args { -+ aufs_bindex_t force_btgt; -+ unsigned char flags; -+}; -+int au_wr_dir(struct dentry *dentry, struct dentry *src_dentry, -+ struct au_wr_dir_args *args); -+ -+struct dentry *au_pinned_h_parent(struct au_pin *pin); -+void au_pin_init(struct au_pin *pin, struct dentry *dentry, -+ aufs_bindex_t bindex, int lsc_di, int lsc_hi, -+ unsigned int udba, unsigned char flags); -+int au_pin(struct au_pin *pin, struct dentry *dentry, aufs_bindex_t bindex, -+ unsigned int udba, unsigned char flags) __must_check; -+int au_do_pin(struct au_pin *pin) __must_check; -+void au_unpin(struct au_pin *pin); -+ -+/* i_op_add.c */ -+int au_may_add(struct dentry *dentry, aufs_bindex_t bindex, -+ struct dentry *h_parent, int isdir); -+int aufs_mknod(struct inode *dir, struct dentry *dentry, int mode, dev_t dev); -+int aufs_symlink(struct inode *dir, struct dentry *dentry, const char *symname); -+int aufs_create(struct inode *dir, struct dentry *dentry, int mode, -+ struct nameidata *nd); -+int aufs_link(struct dentry *src_dentry, struct inode *dir, -+ struct dentry *dentry); -+int aufs_mkdir(struct inode *dir, struct dentry *dentry, int mode); -+ -+/* i_op_del.c */ -+int au_wr_dir_need_wh(struct dentry *dentry, int isdir, aufs_bindex_t *bcpup); -+int au_may_del(struct dentry *dentry, aufs_bindex_t bindex, -+ struct dentry *h_parent, int isdir); -+int aufs_unlink(struct inode *dir, struct dentry *dentry); -+int aufs_rmdir(struct inode *dir, struct dentry *dentry); -+ -+/* i_op_ren.c */ -+int au_wbr(struct dentry *dentry, aufs_bindex_t btgt); -+int aufs_rename(struct inode *src_dir, struct dentry *src_dentry, -+ struct inode *dir, struct dentry *dentry); -+ -+/* iinfo.c */ -+struct inode *au_h_iptr(struct inode *inode, aufs_bindex_t bindex); -+void au_hiput(struct au_hinode *hinode); -+void au_set_hi_wh(struct inode *inode, aufs_bindex_t bindex, -+ struct dentry *h_wh); -+unsigned int au_hi_flags(struct inode *inode, int isdir); -+ -+/* hinode flags */ -+#define AuHi_XINO 1 -+#define AuHi_HNOTIFY (1 << 1) -+#define au_ftest_hi(flags, name) ((flags) & AuHi_##name) -+#define au_fset_hi(flags, name) \ -+ do { (flags) |= AuHi_##name; } while (0) -+#define au_fclr_hi(flags, name) \ -+ do { (flags) &= ~AuHi_##name; } while (0) -+ -+#ifndef CONFIG_AUFS_HNOTIFY -+#undef AuHi_HNOTIFY -+#define AuHi_HNOTIFY 0 -+#endif -+ -+void au_set_h_iptr(struct inode *inode, aufs_bindex_t bindex, -+ struct inode *h_inode, unsigned int flags); -+ -+void au_update_iigen(struct inode *inode); -+void au_update_ibrange(struct inode *inode, int do_put_zero); -+ -+void au_icntnr_init_once(void *_c); -+int au_iinfo_init(struct inode *inode); -+void au_iinfo_fin(struct inode *inode); -+int au_ii_realloc(struct au_iinfo *iinfo, int nbr); -+ -+#ifdef CONFIG_PROC_FS -+/* plink.c */ -+int au_plink_maint(struct super_block *sb, int flags); -+void au_plink_maint_leave(struct au_sbinfo *sbinfo); -+int au_plink_maint_enter(struct super_block *sb); -+#ifdef CONFIG_AUFS_DEBUG -+void au_plink_list(struct super_block *sb); -+#else -+AuStubVoid(au_plink_list, struct super_block *sb) -+#endif -+int au_plink_test(struct inode *inode); -+struct dentry *au_plink_lkup(struct inode *inode, aufs_bindex_t bindex); -+void au_plink_append(struct inode *inode, aufs_bindex_t bindex, -+ struct dentry *h_dentry); -+void au_plink_put(struct super_block *sb, int verbose); -+void au_plink_clean(struct super_block *sb, int verbose); -+void au_plink_half_refresh(struct super_block *sb, aufs_bindex_t br_id); -+#else -+AuStubInt0(au_plink_maint, struct super_block *sb, int flags); -+AuStubVoid(au_plink_maint_leave, struct au_sbinfo *sbinfo); -+AuStubInt0(au_plink_maint_enter, struct super_block *sb); -+AuStubVoid(au_plink_list, struct super_block *sb); -+AuStubInt0(au_plink_test, struct inode *inode); -+AuStub(struct dentry *, au_plink_lkup, return NULL, -+ struct inode *inode, aufs_bindex_t bindex); -+AuStubVoid(au_plink_append, struct inode *inode, aufs_bindex_t bindex, -+ struct dentry *h_dentry); -+AuStubVoid(au_plink_put, struct super_block *sb, int verbose); -+AuStubVoid(au_plink_clean, struct super_block *sb, int verbose); -+AuStubVoid(au_plink_half_refresh, struct super_block *sb, aufs_bindex_t br_id); -+#endif /* CONFIG_PROC_FS */ -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* lock subclass for iinfo */ -+enum { -+ AuLsc_II_CHILD, /* child first */ -+ AuLsc_II_CHILD2, /* rename(2), link(2), and cpup at hnotify */ -+ AuLsc_II_CHILD3, /* copyup dirs */ -+ AuLsc_II_PARENT, /* see AuLsc_I_PARENT in vfsub.h */ -+ AuLsc_II_PARENT2, -+ AuLsc_II_PARENT3, /* copyup dirs */ -+ AuLsc_II_NEW_CHILD -+}; -+ -+/* -+ * ii_read_lock_child, ii_write_lock_child, -+ * ii_read_lock_child2, ii_write_lock_child2, -+ * ii_read_lock_child3, ii_write_lock_child3, -+ * ii_read_lock_parent, ii_write_lock_parent, -+ * ii_read_lock_parent2, ii_write_lock_parent2, -+ * ii_read_lock_parent3, ii_write_lock_parent3, -+ * ii_read_lock_new_child, ii_write_lock_new_child, -+ */ -+#define AuReadLockFunc(name, lsc) \ -+static inline void ii_read_lock_##name(struct inode *i) \ -+{ \ -+ au_rw_read_lock_nested(&au_ii(i)->ii_rwsem, AuLsc_II_##lsc); \ -+} -+ -+#define AuWriteLockFunc(name, lsc) \ -+static inline void ii_write_lock_##name(struct inode *i) \ -+{ \ -+ au_rw_write_lock_nested(&au_ii(i)->ii_rwsem, AuLsc_II_##lsc); \ -+} -+ -+#define AuRWLockFuncs(name, lsc) \ -+ AuReadLockFunc(name, lsc) \ -+ AuWriteLockFunc(name, lsc) -+ -+AuRWLockFuncs(child, CHILD); -+AuRWLockFuncs(child2, CHILD2); -+AuRWLockFuncs(child3, CHILD3); -+AuRWLockFuncs(parent, PARENT); -+AuRWLockFuncs(parent2, PARENT2); -+AuRWLockFuncs(parent3, PARENT3); -+AuRWLockFuncs(new_child, NEW_CHILD); -+ -+#undef AuReadLockFunc -+#undef AuWriteLockFunc -+#undef AuRWLockFuncs -+ -+/* -+ * ii_read_unlock, ii_write_unlock, ii_downgrade_lock -+ */ -+AuSimpleUnlockRwsemFuncs(ii, struct inode *i, &au_ii(i)->ii_rwsem); -+ -+#define IiMustNoWaiters(i) AuRwMustNoWaiters(&au_ii(i)->ii_rwsem) -+#define IiMustAnyLock(i) AuRwMustAnyLock(&au_ii(i)->ii_rwsem) -+#define IiMustWriteLock(i) AuRwMustWriteLock(&au_ii(i)->ii_rwsem) -+ -+/* ---------------------------------------------------------------------- */ -+ -+static inline void au_icntnr_init(struct au_icntnr *c) -+{ -+#ifdef CONFIG_AUFS_DEBUG -+ c->vfs_inode.i_mode = 0; -+#endif -+} -+ -+static inline unsigned int au_iigen(struct inode *inode) -+{ -+ return atomic_read(&au_ii(inode)->ii_generation); -+} -+ -+/* tiny test for inode number */ -+/* tmpfs generation is too rough */ -+static inline int au_test_higen(struct inode *inode, struct inode *h_inode) -+{ -+ struct au_iinfo *iinfo; -+ -+ iinfo = au_ii(inode); -+ AuRwMustAnyLock(&iinfo->ii_rwsem); -+ return !(iinfo->ii_hsb1 == h_inode->i_sb -+ && iinfo->ii_higen == h_inode->i_generation); -+} -+ -+static inline void au_iigen_dec(struct inode *inode) -+{ -+ atomic_dec(&au_ii(inode)->ii_generation); -+} -+ -+static inline int au_iigen_test(struct inode *inode, unsigned int sigen) -+{ -+ int err; -+ -+ err = 0; -+ if (unlikely(inode && au_iigen(inode) != sigen)) -+ err = -EIO; -+ -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static inline aufs_bindex_t au_ii_br_id(struct inode *inode, -+ aufs_bindex_t bindex) -+{ -+ IiMustAnyLock(inode); -+ return au_ii(inode)->ii_hinode[0 + bindex].hi_id; -+} -+ -+static inline aufs_bindex_t au_ibstart(struct inode *inode) -+{ -+ IiMustAnyLock(inode); -+ return au_ii(inode)->ii_bstart; -+} -+ -+static inline aufs_bindex_t au_ibend(struct inode *inode) -+{ -+ IiMustAnyLock(inode); -+ return au_ii(inode)->ii_bend; -+} -+ -+static inline struct au_vdir *au_ivdir(struct inode *inode) -+{ -+ IiMustAnyLock(inode); -+ return au_ii(inode)->ii_vdir; -+} -+ -+static inline struct dentry *au_hi_wh(struct inode *inode, aufs_bindex_t bindex) -+{ -+ IiMustAnyLock(inode); -+ return au_ii(inode)->ii_hinode[0 + bindex].hi_whdentry; -+} -+ -+static inline void au_set_ibstart(struct inode *inode, aufs_bindex_t bindex) -+{ -+ IiMustWriteLock(inode); -+ au_ii(inode)->ii_bstart = bindex; -+} -+ -+static inline void au_set_ibend(struct inode *inode, aufs_bindex_t bindex) -+{ -+ IiMustWriteLock(inode); -+ au_ii(inode)->ii_bend = bindex; -+} -+ -+static inline void au_set_ivdir(struct inode *inode, struct au_vdir *vdir) -+{ -+ IiMustWriteLock(inode); -+ au_ii(inode)->ii_vdir = vdir; -+} -+ -+static inline struct au_hinode *au_hi(struct inode *inode, aufs_bindex_t bindex) -+{ -+ IiMustAnyLock(inode); -+ return au_ii(inode)->ii_hinode + bindex; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static inline struct dentry *au_pinned_parent(struct au_pin *pin) -+{ -+ if (pin) -+ return pin->parent; -+ return NULL; -+} -+ -+static inline struct inode *au_pinned_h_dir(struct au_pin *pin) -+{ -+ if (pin && pin->hdir) -+ return pin->hdir->hi_inode; -+ return NULL; -+} -+ -+static inline struct au_hinode *au_pinned_hdir(struct au_pin *pin) -+{ -+ if (pin) -+ return pin->hdir; -+ return NULL; -+} -+ -+static inline void au_pin_set_dentry(struct au_pin *pin, struct dentry *dentry) -+{ -+ if (pin) -+ pin->dentry = dentry; -+} -+ -+static inline void au_pin_set_parent_lflag(struct au_pin *pin, -+ unsigned char lflag) -+{ -+ if (pin) { -+ if (lflag) -+ au_fset_pin(pin->flags, DI_LOCKED); -+ else -+ au_fclr_pin(pin->flags, DI_LOCKED); -+ } -+} -+ -+static inline void au_pin_set_parent(struct au_pin *pin, struct dentry *parent) -+{ -+ if (pin) { -+ dput(pin->parent); -+ pin->parent = dget(parent); -+ } -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+struct au_branch; -+#ifdef CONFIG_AUFS_HNOTIFY -+struct au_hnotify_op { -+ void (*ctl)(struct au_hinode *hinode, int do_set); -+ int (*alloc)(struct au_hinode *hinode); -+ void (*free)(struct au_hinode *hinode); -+ -+ void (*fin)(void); -+ int (*init)(void); -+ -+ int (*reset_br)(unsigned int udba, struct au_branch *br, int perm); -+ void (*fin_br)(struct au_branch *br); -+ int (*init_br)(struct au_branch *br, int perm); -+}; -+ -+/* hnotify.c */ -+int au_hn_alloc(struct au_hinode *hinode, struct inode *inode); -+void au_hn_free(struct au_hinode *hinode); -+void au_hn_ctl(struct au_hinode *hinode, int do_set); -+void au_hn_reset(struct inode *inode, unsigned int flags); -+int au_hnotify(struct inode *h_dir, struct au_hnotify *hnotify, u32 mask, -+ struct qstr *h_child_qstr, struct inode *h_child_inode); -+int au_hnotify_reset_br(unsigned int udba, struct au_branch *br, int perm); -+int au_hnotify_init_br(struct au_branch *br, int perm); -+void au_hnotify_fin_br(struct au_branch *br); -+int __init au_hnotify_init(void); -+void au_hnotify_fin(void); -+ -+/* hfsnotify.c */ -+extern const struct au_hnotify_op au_hnotify_op; -+ -+static inline -+void au_hn_init(struct au_hinode *hinode) -+{ -+ hinode->hi_notify = NULL; -+} -+ -+#else -+static inline -+int au_hn_alloc(struct au_hinode *hinode __maybe_unused, -+ struct inode *inode __maybe_unused) -+{ -+ return -EOPNOTSUPP; -+} -+ -+AuStubVoid(au_hn_free, struct au_hinode *hinode __maybe_unused) -+AuStubVoid(au_hn_ctl, struct au_hinode *hinode __maybe_unused, -+ int do_set __maybe_unused) -+AuStubVoid(au_hn_reset, struct inode *inode __maybe_unused, -+ unsigned int flags __maybe_unused) -+AuStubInt0(au_hnotify_reset_br, unsigned int udba __maybe_unused, -+ struct au_branch *br __maybe_unused, -+ int perm __maybe_unused) -+AuStubInt0(au_hnotify_init_br, struct au_branch *br __maybe_unused, -+ int perm __maybe_unused) -+AuStubVoid(au_hnotify_fin_br, struct au_branch *br __maybe_unused) -+AuStubInt0(__init au_hnotify_init, void) -+AuStubVoid(au_hnotify_fin, void) -+AuStubVoid(au_hn_init, struct au_hinode *hinode __maybe_unused) -+#endif /* CONFIG_AUFS_HNOTIFY */ -+ -+static inline void au_hn_suspend(struct au_hinode *hdir) -+{ -+ au_hn_ctl(hdir, /*do_set*/0); -+} -+ -+static inline void au_hn_resume(struct au_hinode *hdir) -+{ -+ au_hn_ctl(hdir, /*do_set*/1); -+} -+ -+static inline void au_hn_imtx_lock(struct au_hinode *hdir) -+{ -+ mutex_lock(&hdir->hi_inode->i_mutex); -+ au_hn_suspend(hdir); -+} -+ -+static inline void au_hn_imtx_lock_nested(struct au_hinode *hdir, -+ unsigned int sc __maybe_unused) -+{ -+ mutex_lock_nested(&hdir->hi_inode->i_mutex, sc); -+ au_hn_suspend(hdir); -+} -+ -+static inline void au_hn_imtx_unlock(struct au_hinode *hdir) -+{ -+ au_hn_resume(hdir); -+ mutex_unlock(&hdir->hi_inode->i_mutex); -+} -+ -+#endif /* __KERNEL__ */ -+#endif /* __AUFS_INODE_H__ */ -diff -Nur linux-2.6.36.orig/fs/aufs/ioctl.c linux-2.6.36/fs/aufs/ioctl.c ---- linux-2.6.36.orig/fs/aufs/ioctl.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/ioctl.c 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,150 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * ioctl -+ * plink-management and readdir in userspace. -+ * assist the pathconf(3) wrapper library. -+ */ -+ -+#include -+#include "aufs.h" -+ -+static int au_wbr_fd(struct path *path) -+{ -+ int err, fd; -+ aufs_bindex_t wbi, bindex, bend; -+ struct file *h_file; -+ struct super_block *sb; -+ struct dentry *root; -+ struct au_branch *wbr; -+ -+ err = get_unused_fd(); -+ if (unlikely(err < 0)) -+ goto out; -+ fd = err; -+ -+ wbi = 0; -+ sb = path->dentry->d_sb; -+ root = sb->s_root; -+ aufs_read_lock(root, AuLock_IR); -+ wbr = au_sbr(sb, wbi); -+ if (!(path->mnt->mnt_flags & MNT_READONLY) -+ && !au_br_writable(wbr->br_perm)) { -+ bend = au_sbend(sb); -+ for (bindex = 1; bindex <= bend; bindex++) { -+ wbr = au_sbr(sb, bindex); -+ if (au_br_writable(wbr->br_perm)) { -+ wbi = bindex; -+ break; -+ } -+ } -+ wbr = au_sbr(sb, wbi); -+ } -+ AuDbg("wbi %d\n", wbi); -+ h_file = au_h_open(root, wbi, O_RDONLY | O_DIRECTORY | O_LARGEFILE, -+ NULL); -+ aufs_read_unlock(root, AuLock_IR); -+ err = PTR_ERR(h_file); -+ if (IS_ERR(h_file)) -+ goto out_fd; -+ -+ atomic_dec(&wbr->br_count); /* cf. au_h_open() */ -+ fd_install(fd, h_file); -+ err = fd; -+ goto out; /* success */ -+ -+out_fd: -+ put_unused_fd(fd); -+out: -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+long aufs_ioctl_dir(struct file *file, unsigned int cmd, unsigned long arg) -+{ -+ long err; -+ -+ switch (cmd) { -+ case AUFS_CTL_RDU: -+ case AUFS_CTL_RDU_INO: -+ err = au_rdu_ioctl(file, cmd, arg); -+ break; -+ -+ case AUFS_CTL_WBR_FD: -+ err = au_wbr_fd(&file->f_path); -+ break; -+ -+ default: -+ /* do not call the lower */ -+ AuDbg("0x%x\n", cmd); -+ err = -ENOTTY; -+ } -+ -+ AuTraceErr(err); -+ return err; -+} -+ -+long aufs_ioctl_nondir(struct file *file, unsigned int cmd, unsigned long arg) -+{ -+ long err; -+ -+ switch (cmd) { -+ case AUFS_CTL_WBR_FD: -+ err = au_wbr_fd(&file->f_path); -+ break; -+ -+ default: -+ /* do not call the lower */ -+ AuDbg("0x%x\n", cmd); -+ err = -ENOTTY; -+ } -+ -+ AuTraceErr(err); -+ return err; -+} -+ -+#ifdef CONFIG_COMPAT -+long aufs_compat_ioctl_dir(struct file *file, unsigned int cmd, -+ unsigned long arg) -+{ -+ long err; -+ -+ switch (cmd) { -+ case AUFS_CTL_RDU: -+ case AUFS_CTL_RDU_INO: -+ err = au_rdu_compat_ioctl(file, cmd, arg); -+ break; -+ -+ default: -+ err = aufs_ioctl_dir(file, cmd, arg); -+ } -+ -+ AuTraceErr(err); -+ return err; -+} -+ -+#if 0 /* unused yet */ -+long aufs_compat_ioctl_nondir(struct file *file, unsigned int cmd, -+ unsigned long arg) -+{ -+ return aufs_ioctl_nondir(file, cmd, (unsigned long)compat_ptr(arg)); -+} -+#endif -+#endif -diff -Nur linux-2.6.36.orig/fs/aufs/loop.c linux-2.6.36/fs/aufs/loop.c ---- linux-2.6.36.orig/fs/aufs/loop.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/loop.c 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,63 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * support for loopback block device as a branch -+ */ -+ -+#include -+#include "aufs.h" -+ -+/* -+ * test if two lower dentries have overlapping branches. -+ */ -+int au_test_loopback_overlap(struct super_block *sb, struct dentry *h_adding) -+{ -+ struct super_block *h_sb; -+ struct loop_device *l; -+ -+ h_sb = h_adding->d_sb; -+ if (MAJOR(h_sb->s_dev) != LOOP_MAJOR) -+ return 0; -+ -+ l = h_sb->s_bdev->bd_disk->private_data; -+ h_adding = l->lo_backing_file->f_dentry; -+ /* -+ * h_adding can be local NFS. -+ * in this case aufs cannot detect the loop. -+ */ -+ if (unlikely(h_adding->d_sb == sb)) -+ return 1; -+ return !!au_test_subdir(h_adding, sb->s_root); -+} -+ -+/* true if a kernel thread named 'loop[0-9].*' accesses a file */ -+int au_test_loopback_kthread(void) -+{ -+ int ret; -+ struct task_struct *tsk = current; -+ -+ ret = 0; -+ if (tsk->flags & PF_KTHREAD) { -+ const char c = tsk->comm[4]; -+ ret = ('0' <= c && c <= '9' -+ && !strncmp(tsk->comm, "loop", 4)); -+ } -+ -+ return ret; -+} -diff -Nur linux-2.6.36.orig/fs/aufs/loop.h linux-2.6.36/fs/aufs/loop.h ---- linux-2.6.36.orig/fs/aufs/loop.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/loop.h 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,42 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * support for loopback mount as a branch -+ */ -+ -+#ifndef __AUFS_LOOP_H__ -+#define __AUFS_LOOP_H__ -+ -+#ifdef __KERNEL__ -+ -+struct dentry; -+struct super_block; -+ -+#ifdef CONFIG_AUFS_BDEV_LOOP -+/* loop.c */ -+int au_test_loopback_overlap(struct super_block *sb, struct dentry *h_adding); -+int au_test_loopback_kthread(void); -+#else -+AuStubInt0(au_test_loopback_overlap, struct super_block *sb, -+ struct dentry *h_adding) -+AuStubInt0(au_test_loopback_kthread, void) -+#endif /* BLK_DEV_LOOP */ -+ -+#endif /* __KERNEL__ */ -+#endif /* __AUFS_LOOP_H__ */ -diff -Nur linux-2.6.36.orig/fs/aufs/magic.mk linux-2.6.36/fs/aufs/magic.mk ---- linux-2.6.36.orig/fs/aufs/magic.mk 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/magic.mk 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,54 @@ -+ -+# defined in ${srctree}/fs/fuse/inode.c -+# tristate -+ifdef CONFIG_FUSE_FS -+ccflags-y += -DFUSE_SUPER_MAGIC=0x65735546 -+endif -+ -+# defined in ${srctree}/fs/ocfs2/ocfs2_fs.h -+# tristate -+ifdef CONFIG_OCFS2_FS -+ccflags-y += -DOCFS2_SUPER_MAGIC=0x7461636f -+endif -+ -+# defined in ${srctree}/fs/ocfs2/dlm/userdlm.h -+# tristate -+ifdef CONFIG_OCFS2_FS_O2CB -+ccflags-y += -DDLMFS_MAGIC=0x76a9f425 -+endif -+ -+# defined in ${srctree}/fs/cifs/cifsfs.c -+# tristate -+ifdef CONFIG_CIFS_FS -+ccflags-y += -DCIFS_MAGIC_NUMBER=0xFF534D42 -+endif -+ -+# defined in ${srctree}/fs/xfs/xfs_sb.h -+# tristate -+ifdef CONFIG_XFS_FS -+ccflags-y += -DXFS_SB_MAGIC=0x58465342 -+endif -+ -+# defined in ${srctree}/fs/configfs/mount.c -+# tristate -+ifdef CONFIG_CONFIGFS_FS -+ccflags-y += -DCONFIGFS_MAGIC=0x62656570 -+endif -+ -+# defined in ${srctree}/fs/9p/v9fs.h -+# tristate -+ifdef CONFIG_9P_FS -+ccflags-y += -DV9FS_MAGIC=0x01021997 -+endif -+ -+# defined in ${srctree}/fs/ubifs/ubifs.h -+# tristate -+ifdef CONFIG_UBIFS_FS -+ccflags-y += -DUBIFS_SUPER_MAGIC=0x24051905 -+endif -+ -+# defined in ${srctree}/fs/hfsplus/hfsplus_raw.h -+# tristate -+ifdef CONFIG_HFSPLUS_FS -+ccflags-y += -DHFSPLUS_SUPER_MAGIC=0x482b -+endif -diff -Nur linux-2.6.36.orig/fs/aufs/module.c linux-2.6.36/fs/aufs/module.c ---- linux-2.6.36.orig/fs/aufs/module.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/module.c 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,182 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * module global variables and operations -+ */ -+ -+#include -+#include -+#include "aufs.h" -+ -+void *au_kzrealloc(void *p, unsigned int nused, unsigned int new_sz, gfp_t gfp) -+{ -+ if (new_sz <= nused) -+ return p; -+ -+ p = krealloc(p, new_sz, gfp); -+ if (p) -+ memset(p + nused, 0, new_sz - nused); -+ return p; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * aufs caches -+ */ -+struct kmem_cache *au_cachep[AuCache_Last]; -+static int __init au_cache_init(void) -+{ -+ au_cachep[AuCache_DINFO] = AuCacheCtor(au_dinfo, au_di_init_once); -+ if (au_cachep[AuCache_DINFO]) -+ au_cachep[AuCache_ICNTNR] = AuCacheCtor(au_icntnr, -+ au_icntnr_init_once); -+ if (au_cachep[AuCache_ICNTNR]) -+ au_cachep[AuCache_FINFO] = AuCacheCtor(au_finfo, -+ au_fi_init_once); -+ if (au_cachep[AuCache_FINFO]) -+ au_cachep[AuCache_VDIR] = AuCache(au_vdir); -+ if (au_cachep[AuCache_VDIR]) -+ au_cachep[AuCache_DEHSTR] = AuCache(au_vdir_dehstr); -+ if (au_cachep[AuCache_DEHSTR]) -+ return 0; -+ -+ return -ENOMEM; -+} -+ -+static void au_cache_fin(void) -+{ -+ int i; -+ -+ /* including AuCache_HNOTIFY */ -+ for (i = 0; i < AuCache_Last; i++) -+ if (au_cachep[i]) { -+ kmem_cache_destroy(au_cachep[i]); -+ au_cachep[i] = NULL; -+ } -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+int au_dir_roflags; -+ -+#ifdef CONFIG_AUFS_SBILIST -+struct au_splhead au_sbilist; -+#endif -+ -+/* -+ * functions for module interface. -+ */ -+MODULE_LICENSE("GPL"); -+/* MODULE_LICENSE("GPL v2"); */ -+MODULE_AUTHOR("Junjiro R. Okajima "); -+MODULE_DESCRIPTION(AUFS_NAME -+ " -- Advanced multi layered unification filesystem"); -+MODULE_VERSION(AUFS_VERSION); -+ -+/* this module parameter has no meaning when SYSFS is disabled */ -+int sysaufs_brs = 1; -+MODULE_PARM_DESC(brs, "use /fs/aufs/si_*/brN"); -+module_param_named(brs, sysaufs_brs, int, S_IRUGO); -+ -+/* ---------------------------------------------------------------------- */ -+ -+static char au_esc_chars[0x20 + 3]; /* 0x01-0x20, backslash, del, and NULL */ -+ -+int au_seq_path(struct seq_file *seq, struct path *path) -+{ -+ return seq_path(seq, path, au_esc_chars); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int __init aufs_init(void) -+{ -+ int err, i; -+ char *p; -+ -+ p = au_esc_chars; -+ for (i = 1; i <= ' '; i++) -+ *p++ = i; -+ *p++ = '\\'; -+ *p++ = '\x7f'; -+ *p = 0; -+ -+ au_dir_roflags = au_file_roflags(O_DIRECTORY | O_LARGEFILE); -+ -+ au_sbilist_init(); -+ sysaufs_brs_init(); -+ au_debug_init(); -+ au_dy_init(); -+ err = sysaufs_init(); -+ if (unlikely(err)) -+ goto out; -+ err = au_procfs_init(); -+ if (unlikely(err)) -+ goto out_sysaufs; -+ err = au_wkq_init(); -+ if (unlikely(err)) -+ goto out_procfs; -+ err = au_hnotify_init(); -+ if (unlikely(err)) -+ goto out_wkq; -+ err = au_sysrq_init(); -+ if (unlikely(err)) -+ goto out_hin; -+ err = au_cache_init(); -+ if (unlikely(err)) -+ goto out_sysrq; -+ err = register_filesystem(&aufs_fs_type); -+ if (unlikely(err)) -+ goto out_cache; -+ /* since we define pr_fmt, call printk directly */ -+ printk(KERN_INFO AUFS_NAME " " AUFS_VERSION "\n"); -+ goto out; /* success */ -+ -+out_cache: -+ au_cache_fin(); -+out_sysrq: -+ au_sysrq_fin(); -+out_hin: -+ au_hnotify_fin(); -+out_wkq: -+ au_wkq_fin(); -+out_procfs: -+ au_procfs_fin(); -+out_sysaufs: -+ sysaufs_fin(); -+ au_dy_fin(); -+out: -+ return err; -+} -+ -+static void __exit aufs_exit(void) -+{ -+ unregister_filesystem(&aufs_fs_type); -+ au_cache_fin(); -+ au_sysrq_fin(); -+ au_hnotify_fin(); -+ au_wkq_fin(); -+ au_procfs_fin(); -+ sysaufs_fin(); -+ au_dy_fin(); -+} -+ -+module_init(aufs_init); -+module_exit(aufs_exit); -diff -Nur linux-2.6.36.orig/fs/aufs/module.h linux-2.6.36/fs/aufs/module.h ---- linux-2.6.36.orig/fs/aufs/module.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/module.h 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,91 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * module initialization and module-global -+ */ -+ -+#ifndef __AUFS_MODULE_H__ -+#define __AUFS_MODULE_H__ -+ -+#ifdef __KERNEL__ -+ -+#include -+ -+struct path; -+struct seq_file; -+ -+/* module parameters */ -+extern int sysaufs_brs; -+ -+/* ---------------------------------------------------------------------- */ -+ -+extern int au_dir_roflags; -+ -+void *au_kzrealloc(void *p, unsigned int nused, unsigned int new_sz, gfp_t gfp); -+int au_seq_path(struct seq_file *seq, struct path *path); -+ -+#ifdef CONFIG_PROC_FS -+/* procfs.c */ -+int __init au_procfs_init(void); -+void au_procfs_fin(void); -+#else -+AuStubInt0(au_procfs_init, void); -+AuStubVoid(au_procfs_fin, void); -+#endif -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* kmem cache */ -+enum { -+ AuCache_DINFO, -+ AuCache_ICNTNR, -+ AuCache_FINFO, -+ AuCache_VDIR, -+ AuCache_DEHSTR, -+#ifdef CONFIG_AUFS_HNOTIFY -+ AuCache_HNOTIFY, -+#endif -+ AuCache_Last -+}; -+ -+#define AuCacheFlags (SLAB_RECLAIM_ACCOUNT | SLAB_MEM_SPREAD) -+#define AuCache(type) KMEM_CACHE(type, AuCacheFlags) -+#define AuCacheCtor(type, ctor) \ -+ kmem_cache_create(#type, sizeof(struct type), \ -+ __alignof__(struct type), AuCacheFlags, ctor) -+ -+extern struct kmem_cache *au_cachep[]; -+ -+#define AuCacheFuncs(name, index) \ -+static inline struct au_##name *au_cache_alloc_##name(void) \ -+{ return kmem_cache_alloc(au_cachep[AuCache_##index], GFP_NOFS); } \ -+static inline void au_cache_free_##name(struct au_##name *p) \ -+{ kmem_cache_free(au_cachep[AuCache_##index], p); } -+ -+AuCacheFuncs(dinfo, DINFO); -+AuCacheFuncs(icntnr, ICNTNR); -+AuCacheFuncs(finfo, FINFO); -+AuCacheFuncs(vdir, VDIR); -+AuCacheFuncs(vdir_dehstr, DEHSTR); -+#ifdef CONFIG_AUFS_HNOTIFY -+AuCacheFuncs(hnotify, HNOTIFY); -+#endif -+ -+#endif /* __KERNEL__ */ -+#endif /* __AUFS_MODULE_H__ */ -diff -Nur linux-2.6.36.orig/fs/aufs/mtx.h linux-2.6.36/fs/aufs/mtx.h ---- linux-2.6.36.orig/fs/aufs/mtx.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/mtx.h 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,48 @@ -+/* -+ * Copyright (C) 2010-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * very ugly approach for aufs_mmap() -+ * never include this file from other than f_op.c. -+ * see f_op.c in detail. -+ */ -+ -+#ifndef __AUFS_MTX_H__ -+#define __AUFS_MTX_H__ -+ -+#ifdef __KERNEL__ -+ -+/* copied from ../kernel/mutex{,-debug}.h */ -+struct mutex; -+struct thread_info; -+#ifdef CONFIG_DEBUG_MUTEXES -+static inline void mutex_set_owner(struct mutex *lock) -+{ -+ lock->owner = current_thread_info(); -+} -+#else -+static inline void mutex_set_owner(struct mutex *lock) -+{ -+#ifdef CONFIG_SMP -+ lock->owner = current_thread_info(); -+#endif -+} -+#endif -+ -+#endif /* __KERNEL__ */ -+#endif /* __AUFS_MTX_H__ */ -diff -Nur linux-2.6.36.orig/fs/aufs/opts.c linux-2.6.36/fs/aufs/opts.c ---- linux-2.6.36.orig/fs/aufs/opts.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/opts.c 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,1595 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * mount options/flags -+ */ -+ -+#include -+#include -+#include -+#include /* a distribution requires */ -+#include -+#include "aufs.h" -+ -+/* ---------------------------------------------------------------------- */ -+ -+enum { -+ Opt_br, -+ Opt_add, Opt_del, Opt_mod, Opt_reorder, Opt_append, Opt_prepend, -+ Opt_idel, Opt_imod, Opt_ireorder, -+ Opt_dirwh, Opt_rdcache, Opt_rdblk, Opt_rdhash, Opt_rendir, -+ Opt_rdblk_def, Opt_rdhash_def, -+ Opt_xino, Opt_zxino, Opt_noxino, -+ Opt_trunc_xino, Opt_trunc_xino_v, Opt_notrunc_xino, -+ Opt_trunc_xino_path, Opt_itrunc_xino, -+ Opt_trunc_xib, Opt_notrunc_xib, -+ Opt_shwh, Opt_noshwh, -+ Opt_plink, Opt_noplink, Opt_list_plink, -+ Opt_udba, -+ Opt_dio, Opt_nodio, -+ /* Opt_lock, Opt_unlock, */ -+ Opt_cmd, Opt_cmd_args, -+ Opt_diropq_a, Opt_diropq_w, -+ Opt_warn_perm, Opt_nowarn_perm, -+ Opt_wbr_copyup, Opt_wbr_create, -+ Opt_refrof, Opt_norefrof, -+ Opt_verbose, Opt_noverbose, -+ Opt_sum, Opt_nosum, Opt_wsum, -+ Opt_tail, Opt_ignore, Opt_ignore_silent, Opt_err -+}; -+ -+static match_table_t options = { -+ {Opt_br, "br=%s"}, -+ {Opt_br, "br:%s"}, -+ -+ {Opt_add, "add=%d:%s"}, -+ {Opt_add, "add:%d:%s"}, -+ {Opt_add, "ins=%d:%s"}, -+ {Opt_add, "ins:%d:%s"}, -+ {Opt_append, "append=%s"}, -+ {Opt_append, "append:%s"}, -+ {Opt_prepend, "prepend=%s"}, -+ {Opt_prepend, "prepend:%s"}, -+ -+ {Opt_del, "del=%s"}, -+ {Opt_del, "del:%s"}, -+ /* {Opt_idel, "idel:%d"}, */ -+ {Opt_mod, "mod=%s"}, -+ {Opt_mod, "mod:%s"}, -+ /* {Opt_imod, "imod:%d:%s"}, */ -+ -+ {Opt_dirwh, "dirwh=%d"}, -+ -+ {Opt_xino, "xino=%s"}, -+ {Opt_noxino, "noxino"}, -+ {Opt_trunc_xino, "trunc_xino"}, -+ {Opt_trunc_xino_v, "trunc_xino_v=%d:%d"}, -+ {Opt_notrunc_xino, "notrunc_xino"}, -+ {Opt_trunc_xino_path, "trunc_xino=%s"}, -+ {Opt_itrunc_xino, "itrunc_xino=%d"}, -+ /* {Opt_zxino, "zxino=%s"}, */ -+ {Opt_trunc_xib, "trunc_xib"}, -+ {Opt_notrunc_xib, "notrunc_xib"}, -+ -+#ifdef CONFIG_PROC_FS -+ {Opt_plink, "plink"}, -+#else -+ {Opt_ignore_silent, "plink"}, -+#endif -+ -+ {Opt_noplink, "noplink"}, -+ -+#ifdef CONFIG_AUFS_DEBUG -+ {Opt_list_plink, "list_plink"}, -+#endif -+ -+ {Opt_udba, "udba=%s"}, -+ -+ {Opt_dio, "dio"}, -+ {Opt_nodio, "nodio"}, -+ -+ {Opt_diropq_a, "diropq=always"}, -+ {Opt_diropq_a, "diropq=a"}, -+ {Opt_diropq_w, "diropq=whiteouted"}, -+ {Opt_diropq_w, "diropq=w"}, -+ -+ {Opt_warn_perm, "warn_perm"}, -+ {Opt_nowarn_perm, "nowarn_perm"}, -+ -+ /* keep them temporary */ -+ {Opt_ignore_silent, "coo=%s"}, -+ {Opt_ignore_silent, "nodlgt"}, -+ {Opt_ignore_silent, "nodirperm1"}, -+ {Opt_ignore_silent, "clean_plink"}, -+ -+#ifdef CONFIG_AUFS_SHWH -+ {Opt_shwh, "shwh"}, -+#endif -+ {Opt_noshwh, "noshwh"}, -+ -+ {Opt_rendir, "rendir=%d"}, -+ -+ {Opt_refrof, "refrof"}, -+ {Opt_norefrof, "norefrof"}, -+ -+ {Opt_verbose, "verbose"}, -+ {Opt_verbose, "v"}, -+ {Opt_noverbose, "noverbose"}, -+ {Opt_noverbose, "quiet"}, -+ {Opt_noverbose, "q"}, -+ {Opt_noverbose, "silent"}, -+ -+ {Opt_sum, "sum"}, -+ {Opt_nosum, "nosum"}, -+ {Opt_wsum, "wsum"}, -+ -+ {Opt_rdcache, "rdcache=%d"}, -+ {Opt_rdblk, "rdblk=%d"}, -+ {Opt_rdblk_def, "rdblk=def"}, -+ {Opt_rdhash, "rdhash=%d"}, -+ {Opt_rdhash_def, "rdhash=def"}, -+ -+ {Opt_wbr_create, "create=%s"}, -+ {Opt_wbr_create, "create_policy=%s"}, -+ {Opt_wbr_copyup, "cpup=%s"}, -+ {Opt_wbr_copyup, "copyup=%s"}, -+ {Opt_wbr_copyup, "copyup_policy=%s"}, -+ -+ /* internal use for the scripts */ -+ {Opt_ignore_silent, "si=%s"}, -+ -+ {Opt_br, "dirs=%s"}, -+ {Opt_ignore, "debug=%d"}, -+ {Opt_ignore, "delete=whiteout"}, -+ {Opt_ignore, "delete=all"}, -+ {Opt_ignore, "imap=%s"}, -+ -+ /* temporary workaround, due to old mount(8)? */ -+ {Opt_ignore_silent, "relatime"}, -+ -+ {Opt_err, NULL} -+}; -+ -+/* ---------------------------------------------------------------------- */ -+ -+static const char *au_parser_pattern(int val, struct match_token *token) -+{ -+ while (token->pattern) { -+ if (token->token == val) -+ return token->pattern; -+ token++; -+ } -+ BUG(); -+ return "??"; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static match_table_t brperms = { -+ {AuBrPerm_RO, AUFS_BRPERM_RO}, -+ {AuBrPerm_RR, AUFS_BRPERM_RR}, -+ {AuBrPerm_RW, AUFS_BRPERM_RW}, -+ -+ {AuBrPerm_ROWH, AUFS_BRPERM_ROWH}, -+ {AuBrPerm_RRWH, AUFS_BRPERM_RRWH}, -+ {AuBrPerm_RWNoLinkWH, AUFS_BRPERM_RWNLWH}, -+ -+ {AuBrPerm_ROWH, "nfsro"}, -+ {AuBrPerm_RO, NULL} -+}; -+ -+static int noinline_for_stack br_perm_val(char *perm) -+{ -+ int val; -+ substring_t args[MAX_OPT_ARGS]; -+ -+ val = match_token(perm, brperms, args); -+ return val; -+} -+ -+const char *au_optstr_br_perm(int brperm) -+{ -+ return au_parser_pattern(brperm, (void *)brperms); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static match_table_t udbalevel = { -+ {AuOpt_UDBA_REVAL, "reval"}, -+ {AuOpt_UDBA_NONE, "none"}, -+#ifdef CONFIG_AUFS_HNOTIFY -+ {AuOpt_UDBA_HNOTIFY, "notify"}, /* abstraction */ -+#ifdef CONFIG_AUFS_HFSNOTIFY -+ {AuOpt_UDBA_HNOTIFY, "fsnotify"}, -+#endif -+#endif -+ {-1, NULL} -+}; -+ -+static int noinline_for_stack udba_val(char *str) -+{ -+ substring_t args[MAX_OPT_ARGS]; -+ -+ return match_token(str, udbalevel, args); -+} -+ -+const char *au_optstr_udba(int udba) -+{ -+ return au_parser_pattern(udba, (void *)udbalevel); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static match_table_t au_wbr_create_policy = { -+ {AuWbrCreate_TDP, "tdp"}, -+ {AuWbrCreate_TDP, "top-down-parent"}, -+ {AuWbrCreate_RR, "rr"}, -+ {AuWbrCreate_RR, "round-robin"}, -+ {AuWbrCreate_MFS, "mfs"}, -+ {AuWbrCreate_MFS, "most-free-space"}, -+ {AuWbrCreate_MFSV, "mfs:%d"}, -+ {AuWbrCreate_MFSV, "most-free-space:%d"}, -+ -+ {AuWbrCreate_MFSRR, "mfsrr:%d"}, -+ {AuWbrCreate_MFSRRV, "mfsrr:%d:%d"}, -+ {AuWbrCreate_PMFS, "pmfs"}, -+ {AuWbrCreate_PMFSV, "pmfs:%d"}, -+ -+ {-1, NULL} -+}; -+ -+/* -+ * cf. linux/lib/parser.c and cmdline.c -+ * gave up calling memparse() since it uses simple_strtoull() instead of -+ * strict_...(). -+ */ -+static int noinline_for_stack -+au_match_ull(substring_t *s, unsigned long long *result) -+{ -+ int err; -+ unsigned int len; -+ char a[32]; -+ -+ err = -ERANGE; -+ len = s->to - s->from; -+ if (len + 1 <= sizeof(a)) { -+ memcpy(a, s->from, len); -+ a[len] = '\0'; -+ err = strict_strtoull(a, 0, result); -+ } -+ return err; -+} -+ -+static int au_wbr_mfs_wmark(substring_t *arg, char *str, -+ struct au_opt_wbr_create *create) -+{ -+ int err; -+ unsigned long long ull; -+ -+ err = 0; -+ if (!au_match_ull(arg, &ull)) -+ create->mfsrr_watermark = ull; -+ else { -+ pr_err("bad integer in %s\n", str); -+ err = -EINVAL; -+ } -+ -+ return err; -+} -+ -+static int au_wbr_mfs_sec(substring_t *arg, char *str, -+ struct au_opt_wbr_create *create) -+{ -+ int n, err; -+ -+ err = 0; -+ if (!match_int(arg, &n) && 0 <= n && n <= AUFS_MFS_MAX_SEC) -+ create->mfs_second = n; -+ else { -+ pr_err("bad integer in %s\n", str); -+ err = -EINVAL; -+ } -+ -+ return err; -+} -+ -+static int noinline_for_stack -+au_wbr_create_val(char *str, struct au_opt_wbr_create *create) -+{ -+ int err, e; -+ substring_t args[MAX_OPT_ARGS]; -+ -+ err = match_token(str, au_wbr_create_policy, args); -+ create->wbr_create = err; -+ switch (err) { -+ case AuWbrCreate_MFSRRV: -+ e = au_wbr_mfs_wmark(&args[0], str, create); -+ if (!e) -+ e = au_wbr_mfs_sec(&args[1], str, create); -+ if (unlikely(e)) -+ err = e; -+ break; -+ case AuWbrCreate_MFSRR: -+ e = au_wbr_mfs_wmark(&args[0], str, create); -+ if (unlikely(e)) { -+ err = e; -+ break; -+ } -+ /*FALLTHROUGH*/ -+ case AuWbrCreate_MFS: -+ case AuWbrCreate_PMFS: -+ create->mfs_second = AUFS_MFS_DEF_SEC; -+ break; -+ case AuWbrCreate_MFSV: -+ case AuWbrCreate_PMFSV: -+ e = au_wbr_mfs_sec(&args[0], str, create); -+ if (unlikely(e)) -+ err = e; -+ break; -+ } -+ -+ return err; -+} -+ -+const char *au_optstr_wbr_create(int wbr_create) -+{ -+ return au_parser_pattern(wbr_create, (void *)au_wbr_create_policy); -+} -+ -+static match_table_t au_wbr_copyup_policy = { -+ {AuWbrCopyup_TDP, "tdp"}, -+ {AuWbrCopyup_TDP, "top-down-parent"}, -+ {AuWbrCopyup_BUP, "bup"}, -+ {AuWbrCopyup_BUP, "bottom-up-parent"}, -+ {AuWbrCopyup_BU, "bu"}, -+ {AuWbrCopyup_BU, "bottom-up"}, -+ {-1, NULL} -+}; -+ -+static int noinline_for_stack au_wbr_copyup_val(char *str) -+{ -+ substring_t args[MAX_OPT_ARGS]; -+ -+ return match_token(str, au_wbr_copyup_policy, args); -+} -+ -+const char *au_optstr_wbr_copyup(int wbr_copyup) -+{ -+ return au_parser_pattern(wbr_copyup, (void *)au_wbr_copyup_policy); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static const int lkup_dirflags = LOOKUP_FOLLOW | LOOKUP_DIRECTORY; -+ -+static void dump_opts(struct au_opts *opts) -+{ -+#ifdef CONFIG_AUFS_DEBUG -+ /* reduce stack space */ -+ union { -+ struct au_opt_add *add; -+ struct au_opt_del *del; -+ struct au_opt_mod *mod; -+ struct au_opt_xino *xino; -+ struct au_opt_xino_itrunc *xino_itrunc; -+ struct au_opt_wbr_create *create; -+ } u; -+ struct au_opt *opt; -+ -+ opt = opts->opt; -+ while (opt->type != Opt_tail) { -+ switch (opt->type) { -+ case Opt_add: -+ u.add = &opt->add; -+ AuDbg("add {b%d, %s, 0x%x, %p}\n", -+ u.add->bindex, u.add->pathname, u.add->perm, -+ u.add->path.dentry); -+ break; -+ case Opt_del: -+ case Opt_idel: -+ u.del = &opt->del; -+ AuDbg("del {%s, %p}\n", -+ u.del->pathname, u.del->h_path.dentry); -+ break; -+ case Opt_mod: -+ case Opt_imod: -+ u.mod = &opt->mod; -+ AuDbg("mod {%s, 0x%x, %p}\n", -+ u.mod->path, u.mod->perm, u.mod->h_root); -+ break; -+ case Opt_append: -+ u.add = &opt->add; -+ AuDbg("append {b%d, %s, 0x%x, %p}\n", -+ u.add->bindex, u.add->pathname, u.add->perm, -+ u.add->path.dentry); -+ break; -+ case Opt_prepend: -+ u.add = &opt->add; -+ AuDbg("prepend {b%d, %s, 0x%x, %p}\n", -+ u.add->bindex, u.add->pathname, u.add->perm, -+ u.add->path.dentry); -+ break; -+ case Opt_dirwh: -+ AuDbg("dirwh %d\n", opt->dirwh); -+ break; -+ case Opt_rdcache: -+ AuDbg("rdcache %d\n", opt->rdcache); -+ break; -+ case Opt_rdblk: -+ AuDbg("rdblk %u\n", opt->rdblk); -+ break; -+ case Opt_rdblk_def: -+ AuDbg("rdblk_def\n"); -+ break; -+ case Opt_rdhash: -+ AuDbg("rdhash %u\n", opt->rdhash); -+ break; -+ case Opt_rdhash_def: -+ AuDbg("rdhash_def\n"); -+ break; -+ case Opt_xino: -+ u.xino = &opt->xino; -+ AuDbg("xino {%s %.*s}\n", -+ u.xino->path, -+ AuDLNPair(u.xino->file->f_dentry)); -+ break; -+ case Opt_trunc_xino: -+ AuLabel(trunc_xino); -+ break; -+ case Opt_notrunc_xino: -+ AuLabel(notrunc_xino); -+ break; -+ case Opt_trunc_xino_path: -+ case Opt_itrunc_xino: -+ u.xino_itrunc = &opt->xino_itrunc; -+ AuDbg("trunc_xino %d\n", u.xino_itrunc->bindex); -+ break; -+ -+ case Opt_noxino: -+ AuLabel(noxino); -+ break; -+ case Opt_trunc_xib: -+ AuLabel(trunc_xib); -+ break; -+ case Opt_notrunc_xib: -+ AuLabel(notrunc_xib); -+ break; -+ case Opt_shwh: -+ AuLabel(shwh); -+ break; -+ case Opt_noshwh: -+ AuLabel(noshwh); -+ break; -+ case Opt_plink: -+ AuLabel(plink); -+ break; -+ case Opt_noplink: -+ AuLabel(noplink); -+ break; -+ case Opt_list_plink: -+ AuLabel(list_plink); -+ break; -+ case Opt_udba: -+ AuDbg("udba %d, %s\n", -+ opt->udba, au_optstr_udba(opt->udba)); -+ break; -+ case Opt_dio: -+ AuLabel(dio); -+ break; -+ case Opt_nodio: -+ AuLabel(nodio); -+ break; -+ case Opt_diropq_a: -+ AuLabel(diropq_a); -+ break; -+ case Opt_diropq_w: -+ AuLabel(diropq_w); -+ break; -+ case Opt_warn_perm: -+ AuLabel(warn_perm); -+ break; -+ case Opt_nowarn_perm: -+ AuLabel(nowarn_perm); -+ break; -+ case Opt_refrof: -+ AuLabel(refrof); -+ break; -+ case Opt_norefrof: -+ AuLabel(norefrof); -+ break; -+ case Opt_verbose: -+ AuLabel(verbose); -+ break; -+ case Opt_noverbose: -+ AuLabel(noverbose); -+ break; -+ case Opt_sum: -+ AuLabel(sum); -+ break; -+ case Opt_nosum: -+ AuLabel(nosum); -+ break; -+ case Opt_wsum: -+ AuLabel(wsum); -+ break; -+ case Opt_wbr_create: -+ u.create = &opt->wbr_create; -+ AuDbg("create %d, %s\n", u.create->wbr_create, -+ au_optstr_wbr_create(u.create->wbr_create)); -+ switch (u.create->wbr_create) { -+ case AuWbrCreate_MFSV: -+ case AuWbrCreate_PMFSV: -+ AuDbg("%d sec\n", u.create->mfs_second); -+ break; -+ case AuWbrCreate_MFSRR: -+ AuDbg("%llu watermark\n", -+ u.create->mfsrr_watermark); -+ break; -+ case AuWbrCreate_MFSRRV: -+ AuDbg("%llu watermark, %d sec\n", -+ u.create->mfsrr_watermark, -+ u.create->mfs_second); -+ break; -+ } -+ break; -+ case Opt_wbr_copyup: -+ AuDbg("copyup %d, %s\n", opt->wbr_copyup, -+ au_optstr_wbr_copyup(opt->wbr_copyup)); -+ break; -+ default: -+ BUG(); -+ } -+ opt++; -+ } -+#endif -+} -+ -+void au_opts_free(struct au_opts *opts) -+{ -+ struct au_opt *opt; -+ -+ opt = opts->opt; -+ while (opt->type != Opt_tail) { -+ switch (opt->type) { -+ case Opt_add: -+ case Opt_append: -+ case Opt_prepend: -+ path_put(&opt->add.path); -+ break; -+ case Opt_del: -+ case Opt_idel: -+ path_put(&opt->del.h_path); -+ break; -+ case Opt_mod: -+ case Opt_imod: -+ dput(opt->mod.h_root); -+ break; -+ case Opt_xino: -+ fput(opt->xino.file); -+ break; -+ } -+ opt++; -+ } -+} -+ -+static int opt_add(struct au_opt *opt, char *opt_str, unsigned long sb_flags, -+ aufs_bindex_t bindex) -+{ -+ int err; -+ struct au_opt_add *add = &opt->add; -+ char *p; -+ -+ add->bindex = bindex; -+ add->perm = AuBrPerm_Last; -+ add->pathname = opt_str; -+ p = strchr(opt_str, '='); -+ if (p) { -+ *p++ = 0; -+ if (*p) -+ add->perm = br_perm_val(p); -+ } -+ -+ err = vfsub_kern_path(add->pathname, lkup_dirflags, &add->path); -+ if (!err) { -+ if (!p) { -+ add->perm = AuBrPerm_RO; -+ if (au_test_fs_rr(add->path.dentry->d_sb)) -+ add->perm = AuBrPerm_RR; -+ else if (!bindex && !(sb_flags & MS_RDONLY)) -+ add->perm = AuBrPerm_RW; -+ } -+ opt->type = Opt_add; -+ goto out; -+ } -+ pr_err("lookup failed %s (%d)\n", add->pathname, err); -+ err = -EINVAL; -+ -+out: -+ return err; -+} -+ -+static int au_opts_parse_del(struct au_opt_del *del, substring_t args[]) -+{ -+ int err; -+ -+ del->pathname = args[0].from; -+ AuDbg("del path %s\n", del->pathname); -+ -+ err = vfsub_kern_path(del->pathname, lkup_dirflags, &del->h_path); -+ if (unlikely(err)) -+ pr_err("lookup failed %s (%d)\n", del->pathname, err); -+ -+ return err; -+} -+ -+#if 0 /* reserved for future use */ -+static int au_opts_parse_idel(struct super_block *sb, aufs_bindex_t bindex, -+ struct au_opt_del *del, substring_t args[]) -+{ -+ int err; -+ struct dentry *root; -+ -+ err = -EINVAL; -+ root = sb->s_root; -+ aufs_read_lock(root, AuLock_FLUSH); -+ if (bindex < 0 || au_sbend(sb) < bindex) { -+ pr_err("out of bounds, %d\n", bindex); -+ goto out; -+ } -+ -+ err = 0; -+ del->h_path.dentry = dget(au_h_dptr(root, bindex)); -+ del->h_path.mnt = mntget(au_sbr_mnt(sb, bindex)); -+ -+out: -+ aufs_read_unlock(root, !AuLock_IR); -+ return err; -+} -+#endif -+ -+static int noinline_for_stack -+au_opts_parse_mod(struct au_opt_mod *mod, substring_t args[]) -+{ -+ int err; -+ struct path path; -+ char *p; -+ -+ err = -EINVAL; -+ mod->path = args[0].from; -+ p = strchr(mod->path, '='); -+ if (unlikely(!p)) { -+ pr_err("no permssion %s\n", args[0].from); -+ goto out; -+ } -+ -+ *p++ = 0; -+ err = vfsub_kern_path(mod->path, lkup_dirflags, &path); -+ if (unlikely(err)) { -+ pr_err("lookup failed %s (%d)\n", mod->path, err); -+ goto out; -+ } -+ -+ mod->perm = br_perm_val(p); -+ AuDbg("mod path %s, perm 0x%x, %s\n", mod->path, mod->perm, p); -+ mod->h_root = dget(path.dentry); -+ path_put(&path); -+ -+out: -+ return err; -+} -+ -+#if 0 /* reserved for future use */ -+static int au_opts_parse_imod(struct super_block *sb, aufs_bindex_t bindex, -+ struct au_opt_mod *mod, substring_t args[]) -+{ -+ int err; -+ struct dentry *root; -+ -+ err = -EINVAL; -+ root = sb->s_root; -+ aufs_read_lock(root, AuLock_FLUSH); -+ if (bindex < 0 || au_sbend(sb) < bindex) { -+ pr_err("out of bounds, %d\n", bindex); -+ goto out; -+ } -+ -+ err = 0; -+ mod->perm = br_perm_val(args[1].from); -+ AuDbg("mod path %s, perm 0x%x, %s\n", -+ mod->path, mod->perm, args[1].from); -+ mod->h_root = dget(au_h_dptr(root, bindex)); -+ -+out: -+ aufs_read_unlock(root, !AuLock_IR); -+ return err; -+} -+#endif -+ -+static int au_opts_parse_xino(struct super_block *sb, struct au_opt_xino *xino, -+ substring_t args[]) -+{ -+ int err; -+ struct file *file; -+ -+ file = au_xino_create(sb, args[0].from, /*silent*/0); -+ err = PTR_ERR(file); -+ if (IS_ERR(file)) -+ goto out; -+ -+ err = -EINVAL; -+ if (unlikely(file->f_dentry->d_sb == sb)) { -+ fput(file); -+ pr_err("%s must be outside\n", args[0].from); -+ goto out; -+ } -+ -+ err = 0; -+ xino->file = file; -+ xino->path = args[0].from; -+ -+out: -+ return err; -+} -+ -+static int noinline_for_stack -+au_opts_parse_xino_itrunc_path(struct super_block *sb, -+ struct au_opt_xino_itrunc *xino_itrunc, -+ substring_t args[]) -+{ -+ int err; -+ aufs_bindex_t bend, bindex; -+ struct path path; -+ struct dentry *root; -+ -+ err = vfsub_kern_path(args[0].from, lkup_dirflags, &path); -+ if (unlikely(err)) { -+ pr_err("lookup failed %s (%d)\n", args[0].from, err); -+ goto out; -+ } -+ -+ xino_itrunc->bindex = -1; -+ root = sb->s_root; -+ aufs_read_lock(root, AuLock_FLUSH); -+ bend = au_sbend(sb); -+ for (bindex = 0; bindex <= bend; bindex++) { -+ if (au_h_dptr(root, bindex) == path.dentry) { -+ xino_itrunc->bindex = bindex; -+ break; -+ } -+ } -+ aufs_read_unlock(root, !AuLock_IR); -+ path_put(&path); -+ -+ if (unlikely(xino_itrunc->bindex < 0)) { -+ pr_err("no such branch %s\n", args[0].from); -+ err = -EINVAL; -+ } -+ -+out: -+ return err; -+} -+ -+/* called without aufs lock */ -+int au_opts_parse(struct super_block *sb, char *str, struct au_opts *opts) -+{ -+ int err, n, token; -+ aufs_bindex_t bindex; -+ unsigned char skipped; -+ struct dentry *root; -+ struct au_opt *opt, *opt_tail; -+ char *opt_str; -+ /* reduce the stack space */ -+ union { -+ struct au_opt_xino_itrunc *xino_itrunc; -+ struct au_opt_wbr_create *create; -+ } u; -+ struct { -+ substring_t args[MAX_OPT_ARGS]; -+ } *a; -+ -+ err = -ENOMEM; -+ a = kmalloc(sizeof(*a), GFP_NOFS); -+ if (unlikely(!a)) -+ goto out; -+ -+ root = sb->s_root; -+ err = 0; -+ bindex = 0; -+ opt = opts->opt; -+ opt_tail = opt + opts->max_opt - 1; -+ opt->type = Opt_tail; -+ while (!err && (opt_str = strsep(&str, ",")) && *opt_str) { -+ err = -EINVAL; -+ skipped = 0; -+ token = match_token(opt_str, options, a->args); -+ switch (token) { -+ case Opt_br: -+ err = 0; -+ while (!err && (opt_str = strsep(&a->args[0].from, ":")) -+ && *opt_str) { -+ err = opt_add(opt, opt_str, opts->sb_flags, -+ bindex++); -+ if (unlikely(!err && ++opt > opt_tail)) { -+ err = -E2BIG; -+ break; -+ } -+ opt->type = Opt_tail; -+ skipped = 1; -+ } -+ break; -+ case Opt_add: -+ if (unlikely(match_int(&a->args[0], &n))) { -+ pr_err("bad integer in %s\n", opt_str); -+ break; -+ } -+ bindex = n; -+ err = opt_add(opt, a->args[1].from, opts->sb_flags, -+ bindex); -+ if (!err) -+ opt->type = token; -+ break; -+ case Opt_append: -+ err = opt_add(opt, a->args[0].from, opts->sb_flags, -+ /*dummy bindex*/1); -+ if (!err) -+ opt->type = token; -+ break; -+ case Opt_prepend: -+ err = opt_add(opt, a->args[0].from, opts->sb_flags, -+ /*bindex*/0); -+ if (!err) -+ opt->type = token; -+ break; -+ case Opt_del: -+ err = au_opts_parse_del(&opt->del, a->args); -+ if (!err) -+ opt->type = token; -+ break; -+#if 0 /* reserved for future use */ -+ case Opt_idel: -+ del->pathname = "(indexed)"; -+ if (unlikely(match_int(&args[0], &n))) { -+ pr_err("bad integer in %s\n", opt_str); -+ break; -+ } -+ err = au_opts_parse_idel(sb, n, &opt->del, a->args); -+ if (!err) -+ opt->type = token; -+ break; -+#endif -+ case Opt_mod: -+ err = au_opts_parse_mod(&opt->mod, a->args); -+ if (!err) -+ opt->type = token; -+ break; -+#ifdef IMOD /* reserved for future use */ -+ case Opt_imod: -+ u.mod->path = "(indexed)"; -+ if (unlikely(match_int(&a->args[0], &n))) { -+ pr_err("bad integer in %s\n", opt_str); -+ break; -+ } -+ err = au_opts_parse_imod(sb, n, &opt->mod, a->args); -+ if (!err) -+ opt->type = token; -+ break; -+#endif -+ case Opt_xino: -+ err = au_opts_parse_xino(sb, &opt->xino, a->args); -+ if (!err) -+ opt->type = token; -+ break; -+ -+ case Opt_trunc_xino_path: -+ err = au_opts_parse_xino_itrunc_path -+ (sb, &opt->xino_itrunc, a->args); -+ if (!err) -+ opt->type = token; -+ break; -+ -+ case Opt_itrunc_xino: -+ u.xino_itrunc = &opt->xino_itrunc; -+ if (unlikely(match_int(&a->args[0], &n))) { -+ pr_err("bad integer in %s\n", opt_str); -+ break; -+ } -+ u.xino_itrunc->bindex = n; -+ aufs_read_lock(root, AuLock_FLUSH); -+ if (n < 0 || au_sbend(sb) < n) { -+ pr_err("out of bounds, %d\n", n); -+ aufs_read_unlock(root, !AuLock_IR); -+ break; -+ } -+ aufs_read_unlock(root, !AuLock_IR); -+ err = 0; -+ opt->type = token; -+ break; -+ -+ case Opt_dirwh: -+ if (unlikely(match_int(&a->args[0], &opt->dirwh))) -+ break; -+ err = 0; -+ opt->type = token; -+ break; -+ -+ case Opt_rdcache: -+ if (unlikely(match_int(&a->args[0], &n))) { -+ pr_err("bad integer in %s\n", opt_str); -+ break; -+ } -+ if (unlikely(n > AUFS_RDCACHE_MAX)) { -+ pr_err("rdcache must be smaller than %d\n", -+ AUFS_RDCACHE_MAX); -+ break; -+ } -+ opt->rdcache = n; -+ err = 0; -+ opt->type = token; -+ break; -+ case Opt_rdblk: -+ if (unlikely(match_int(&a->args[0], &n) -+ || n < 0 -+ || n > KMALLOC_MAX_SIZE)) { -+ pr_err("bad integer in %s\n", opt_str); -+ break; -+ } -+ if (unlikely(n && n < NAME_MAX)) { -+ pr_err("rdblk must be larger than %d\n", -+ NAME_MAX); -+ break; -+ } -+ opt->rdblk = n; -+ err = 0; -+ opt->type = token; -+ break; -+ case Opt_rdhash: -+ if (unlikely(match_int(&a->args[0], &n) -+ || n < 0 -+ || n * sizeof(struct hlist_head) -+ > KMALLOC_MAX_SIZE)) { -+ pr_err("bad integer in %s\n", opt_str); -+ break; -+ } -+ opt->rdhash = n; -+ err = 0; -+ opt->type = token; -+ break; -+ -+ case Opt_trunc_xino: -+ case Opt_notrunc_xino: -+ case Opt_noxino: -+ case Opt_trunc_xib: -+ case Opt_notrunc_xib: -+ case Opt_shwh: -+ case Opt_noshwh: -+ case Opt_plink: -+ case Opt_noplink: -+ case Opt_list_plink: -+ case Opt_dio: -+ case Opt_nodio: -+ case Opt_diropq_a: -+ case Opt_diropq_w: -+ case Opt_warn_perm: -+ case Opt_nowarn_perm: -+ case Opt_refrof: -+ case Opt_norefrof: -+ case Opt_verbose: -+ case Opt_noverbose: -+ case Opt_sum: -+ case Opt_nosum: -+ case Opt_wsum: -+ case Opt_rdblk_def: -+ case Opt_rdhash_def: -+ err = 0; -+ opt->type = token; -+ break; -+ -+ case Opt_udba: -+ opt->udba = udba_val(a->args[0].from); -+ if (opt->udba >= 0) { -+ err = 0; -+ opt->type = token; -+ } else -+ pr_err("wrong value, %s\n", opt_str); -+ break; -+ -+ case Opt_wbr_create: -+ u.create = &opt->wbr_create; -+ u.create->wbr_create -+ = au_wbr_create_val(a->args[0].from, u.create); -+ if (u.create->wbr_create >= 0) { -+ err = 0; -+ opt->type = token; -+ } else -+ pr_err("wrong value, %s\n", opt_str); -+ break; -+ case Opt_wbr_copyup: -+ opt->wbr_copyup = au_wbr_copyup_val(a->args[0].from); -+ if (opt->wbr_copyup >= 0) { -+ err = 0; -+ opt->type = token; -+ } else -+ pr_err("wrong value, %s\n", opt_str); -+ break; -+ -+ case Opt_ignore: -+ pr_warning("ignored %s\n", opt_str); -+ /*FALLTHROUGH*/ -+ case Opt_ignore_silent: -+ skipped = 1; -+ err = 0; -+ break; -+ case Opt_err: -+ pr_err("unknown option %s\n", opt_str); -+ break; -+ } -+ -+ if (!err && !skipped) { -+ if (unlikely(++opt > opt_tail)) { -+ err = -E2BIG; -+ opt--; -+ opt->type = Opt_tail; -+ break; -+ } -+ opt->type = Opt_tail; -+ } -+ } -+ -+ kfree(a); -+ dump_opts(opts); -+ if (unlikely(err)) -+ au_opts_free(opts); -+ -+out: -+ return err; -+} -+ -+static int au_opt_wbr_create(struct super_block *sb, -+ struct au_opt_wbr_create *create) -+{ -+ int err; -+ struct au_sbinfo *sbinfo; -+ -+ SiMustWriteLock(sb); -+ -+ err = 1; /* handled */ -+ sbinfo = au_sbi(sb); -+ if (sbinfo->si_wbr_create_ops->fin) { -+ err = sbinfo->si_wbr_create_ops->fin(sb); -+ if (!err) -+ err = 1; -+ } -+ -+ sbinfo->si_wbr_create = create->wbr_create; -+ sbinfo->si_wbr_create_ops = au_wbr_create_ops + create->wbr_create; -+ switch (create->wbr_create) { -+ case AuWbrCreate_MFSRRV: -+ case AuWbrCreate_MFSRR: -+ sbinfo->si_wbr_mfs.mfsrr_watermark = create->mfsrr_watermark; -+ /*FALLTHROUGH*/ -+ case AuWbrCreate_MFS: -+ case AuWbrCreate_MFSV: -+ case AuWbrCreate_PMFS: -+ case AuWbrCreate_PMFSV: -+ sbinfo->si_wbr_mfs.mfs_expire -+ = msecs_to_jiffies(create->mfs_second * MSEC_PER_SEC); -+ break; -+ } -+ -+ if (sbinfo->si_wbr_create_ops->init) -+ sbinfo->si_wbr_create_ops->init(sb); /* ignore */ -+ -+ return err; -+} -+ -+/* -+ * returns, -+ * plus: processed without an error -+ * zero: unprocessed -+ */ -+static int au_opt_simple(struct super_block *sb, struct au_opt *opt, -+ struct au_opts *opts) -+{ -+ int err; -+ struct au_sbinfo *sbinfo; -+ -+ SiMustWriteLock(sb); -+ -+ err = 1; /* handled */ -+ sbinfo = au_sbi(sb); -+ switch (opt->type) { -+ case Opt_udba: -+ sbinfo->si_mntflags &= ~AuOptMask_UDBA; -+ sbinfo->si_mntflags |= opt->udba; -+ opts->given_udba |= opt->udba; -+ break; -+ -+ case Opt_plink: -+ au_opt_set(sbinfo->si_mntflags, PLINK); -+ break; -+ case Opt_noplink: -+ if (au_opt_test(sbinfo->si_mntflags, PLINK)) -+ au_plink_put(sb, /*verbose*/1); -+ au_opt_clr(sbinfo->si_mntflags, PLINK); -+ break; -+ case Opt_list_plink: -+ if (au_opt_test(sbinfo->si_mntflags, PLINK)) -+ au_plink_list(sb); -+ break; -+ -+ case Opt_dio: -+ au_opt_set(sbinfo->si_mntflags, DIO); -+ au_fset_opts(opts->flags, REFRESH_DYAOP); -+ break; -+ case Opt_nodio: -+ au_opt_clr(sbinfo->si_mntflags, DIO); -+ au_fset_opts(opts->flags, REFRESH_DYAOP); -+ break; -+ -+ case Opt_diropq_a: -+ au_opt_set(sbinfo->si_mntflags, ALWAYS_DIROPQ); -+ break; -+ case Opt_diropq_w: -+ au_opt_clr(sbinfo->si_mntflags, ALWAYS_DIROPQ); -+ break; -+ -+ case Opt_warn_perm: -+ au_opt_set(sbinfo->si_mntflags, WARN_PERM); -+ break; -+ case Opt_nowarn_perm: -+ au_opt_clr(sbinfo->si_mntflags, WARN_PERM); -+ break; -+ -+ case Opt_refrof: -+ au_opt_set(sbinfo->si_mntflags, REFROF); -+ break; -+ case Opt_norefrof: -+ au_opt_clr(sbinfo->si_mntflags, REFROF); -+ break; -+ -+ case Opt_verbose: -+ au_opt_set(sbinfo->si_mntflags, VERBOSE); -+ break; -+ case Opt_noverbose: -+ au_opt_clr(sbinfo->si_mntflags, VERBOSE); -+ break; -+ -+ case Opt_sum: -+ au_opt_set(sbinfo->si_mntflags, SUM); -+ break; -+ case Opt_wsum: -+ au_opt_clr(sbinfo->si_mntflags, SUM); -+ au_opt_set(sbinfo->si_mntflags, SUM_W); -+ case Opt_nosum: -+ au_opt_clr(sbinfo->si_mntflags, SUM); -+ au_opt_clr(sbinfo->si_mntflags, SUM_W); -+ break; -+ -+ case Opt_wbr_create: -+ err = au_opt_wbr_create(sb, &opt->wbr_create); -+ break; -+ case Opt_wbr_copyup: -+ sbinfo->si_wbr_copyup = opt->wbr_copyup; -+ sbinfo->si_wbr_copyup_ops = au_wbr_copyup_ops + opt->wbr_copyup; -+ break; -+ -+ case Opt_dirwh: -+ sbinfo->si_dirwh = opt->dirwh; -+ break; -+ -+ case Opt_rdcache: -+ sbinfo->si_rdcache -+ = msecs_to_jiffies(opt->rdcache * MSEC_PER_SEC); -+ break; -+ case Opt_rdblk: -+ sbinfo->si_rdblk = opt->rdblk; -+ break; -+ case Opt_rdblk_def: -+ sbinfo->si_rdblk = AUFS_RDBLK_DEF; -+ break; -+ case Opt_rdhash: -+ sbinfo->si_rdhash = opt->rdhash; -+ break; -+ case Opt_rdhash_def: -+ sbinfo->si_rdhash = AUFS_RDHASH_DEF; -+ break; -+ -+ case Opt_shwh: -+ au_opt_set(sbinfo->si_mntflags, SHWH); -+ break; -+ case Opt_noshwh: -+ au_opt_clr(sbinfo->si_mntflags, SHWH); -+ break; -+ -+ case Opt_trunc_xino: -+ au_opt_set(sbinfo->si_mntflags, TRUNC_XINO); -+ break; -+ case Opt_notrunc_xino: -+ au_opt_clr(sbinfo->si_mntflags, TRUNC_XINO); -+ break; -+ -+ case Opt_trunc_xino_path: -+ case Opt_itrunc_xino: -+ err = au_xino_trunc(sb, opt->xino_itrunc.bindex); -+ if (!err) -+ err = 1; -+ break; -+ -+ case Opt_trunc_xib: -+ au_fset_opts(opts->flags, TRUNC_XIB); -+ break; -+ case Opt_notrunc_xib: -+ au_fclr_opts(opts->flags, TRUNC_XIB); -+ break; -+ -+ default: -+ err = 0; -+ break; -+ } -+ -+ return err; -+} -+ -+/* -+ * returns tri-state. -+ * plus: processed without an error -+ * zero: unprocessed -+ * minus: error -+ */ -+static int au_opt_br(struct super_block *sb, struct au_opt *opt, -+ struct au_opts *opts) -+{ -+ int err, do_refresh; -+ -+ err = 0; -+ switch (opt->type) { -+ case Opt_append: -+ opt->add.bindex = au_sbend(sb) + 1; -+ if (opt->add.bindex < 0) -+ opt->add.bindex = 0; -+ goto add; -+ case Opt_prepend: -+ opt->add.bindex = 0; -+ add: -+ case Opt_add: -+ err = au_br_add(sb, &opt->add, -+ au_ftest_opts(opts->flags, REMOUNT)); -+ if (!err) { -+ err = 1; -+ au_fset_opts(opts->flags, REFRESH); -+ } -+ break; -+ -+ case Opt_del: -+ case Opt_idel: -+ err = au_br_del(sb, &opt->del, -+ au_ftest_opts(opts->flags, REMOUNT)); -+ if (!err) { -+ err = 1; -+ au_fset_opts(opts->flags, TRUNC_XIB); -+ au_fset_opts(opts->flags, REFRESH); -+ } -+ break; -+ -+ case Opt_mod: -+ case Opt_imod: -+ err = au_br_mod(sb, &opt->mod, -+ au_ftest_opts(opts->flags, REMOUNT), -+ &do_refresh); -+ if (!err) { -+ err = 1; -+ if (do_refresh) -+ au_fset_opts(opts->flags, REFRESH); -+ } -+ break; -+ } -+ -+ return err; -+} -+ -+static int au_opt_xino(struct super_block *sb, struct au_opt *opt, -+ struct au_opt_xino **opt_xino, -+ struct au_opts *opts) -+{ -+ int err; -+ aufs_bindex_t bend, bindex; -+ struct dentry *root, *parent, *h_root; -+ -+ err = 0; -+ switch (opt->type) { -+ case Opt_xino: -+ err = au_xino_set(sb, &opt->xino, -+ !!au_ftest_opts(opts->flags, REMOUNT)); -+ if (unlikely(err)) -+ break; -+ -+ *opt_xino = &opt->xino; -+ au_xino_brid_set(sb, -1); -+ -+ /* safe d_parent access */ -+ parent = opt->xino.file->f_dentry->d_parent; -+ root = sb->s_root; -+ bend = au_sbend(sb); -+ for (bindex = 0; bindex <= bend; bindex++) { -+ h_root = au_h_dptr(root, bindex); -+ if (h_root == parent) { -+ au_xino_brid_set(sb, au_sbr_id(sb, bindex)); -+ break; -+ } -+ } -+ break; -+ -+ case Opt_noxino: -+ au_xino_clr(sb); -+ au_xino_brid_set(sb, -1); -+ *opt_xino = (void *)-1; -+ break; -+ } -+ -+ return err; -+} -+ -+int au_opts_verify(struct super_block *sb, unsigned long sb_flags, -+ unsigned int pending) -+{ -+ int err; -+ aufs_bindex_t bindex, bend; -+ unsigned char do_plink, skip, do_free; -+ struct au_branch *br; -+ struct au_wbr *wbr; -+ struct dentry *root; -+ struct inode *dir, *h_dir; -+ struct au_sbinfo *sbinfo; -+ struct au_hinode *hdir; -+ -+ SiMustAnyLock(sb); -+ -+ sbinfo = au_sbi(sb); -+ AuDebugOn(!(sbinfo->si_mntflags & AuOptMask_UDBA)); -+ -+ if (!(sb_flags & MS_RDONLY)) { -+ if (unlikely(!au_br_writable(au_sbr_perm(sb, 0)))) -+ pr_warning("first branch should be rw\n"); -+ if (unlikely(au_opt_test(sbinfo->si_mntflags, SHWH))) -+ pr_warning("shwh should be used with ro\n"); -+ } -+ -+ if (au_opt_test((sbinfo->si_mntflags | pending), UDBA_HNOTIFY) -+ && !au_opt_test(sbinfo->si_mntflags, XINO)) -+ pr_warning("udba=*notify requires xino\n"); -+ -+ err = 0; -+ root = sb->s_root; -+ dir = root->d_inode; -+ do_plink = !!au_opt_test(sbinfo->si_mntflags, PLINK); -+ bend = au_sbend(sb); -+ for (bindex = 0; !err && bindex <= bend; bindex++) { -+ skip = 0; -+ h_dir = au_h_iptr(dir, bindex); -+ br = au_sbr(sb, bindex); -+ do_free = 0; -+ -+ wbr = br->br_wbr; -+ if (wbr) -+ wbr_wh_read_lock(wbr); -+ -+ switch (br->br_perm) { -+ case AuBrPerm_RO: -+ case AuBrPerm_ROWH: -+ case AuBrPerm_RR: -+ case AuBrPerm_RRWH: -+ do_free = !!wbr; -+ skip = (!wbr -+ || (!wbr->wbr_whbase -+ && !wbr->wbr_plink -+ && !wbr->wbr_orph)); -+ break; -+ -+ case AuBrPerm_RWNoLinkWH: -+ /* skip = (!br->br_whbase && !br->br_orph); */ -+ skip = (!wbr || !wbr->wbr_whbase); -+ if (skip && wbr) { -+ if (do_plink) -+ skip = !!wbr->wbr_plink; -+ else -+ skip = !wbr->wbr_plink; -+ } -+ break; -+ -+ case AuBrPerm_RW: -+ /* skip = (br->br_whbase && br->br_ohph); */ -+ skip = (wbr && wbr->wbr_whbase); -+ if (skip) { -+ if (do_plink) -+ skip = !!wbr->wbr_plink; -+ else -+ skip = !wbr->wbr_plink; -+ } -+ break; -+ -+ default: -+ BUG(); -+ } -+ if (wbr) -+ wbr_wh_read_unlock(wbr); -+ -+ if (skip) -+ continue; -+ -+ hdir = au_hi(dir, bindex); -+ au_hn_imtx_lock_nested(hdir, AuLsc_I_PARENT); -+ if (wbr) -+ wbr_wh_write_lock(wbr); -+ err = au_wh_init(au_h_dptr(root, bindex), br, sb); -+ if (wbr) -+ wbr_wh_write_unlock(wbr); -+ au_hn_imtx_unlock(hdir); -+ -+ if (!err && do_free) { -+ kfree(wbr); -+ br->br_wbr = NULL; -+ } -+ } -+ -+ return err; -+} -+ -+int au_opts_mount(struct super_block *sb, struct au_opts *opts) -+{ -+ int err; -+ unsigned int tmp; -+ aufs_bindex_t bindex, bend; -+ struct au_opt *opt; -+ struct au_opt_xino *opt_xino, xino; -+ struct au_sbinfo *sbinfo; -+ struct au_branch *br; -+ -+ SiMustWriteLock(sb); -+ -+ err = 0; -+ opt_xino = NULL; -+ opt = opts->opt; -+ while (err >= 0 && opt->type != Opt_tail) -+ err = au_opt_simple(sb, opt++, opts); -+ if (err > 0) -+ err = 0; -+ else if (unlikely(err < 0)) -+ goto out; -+ -+ /* disable xino and udba temporary */ -+ sbinfo = au_sbi(sb); -+ tmp = sbinfo->si_mntflags; -+ au_opt_clr(sbinfo->si_mntflags, XINO); -+ au_opt_set_udba(sbinfo->si_mntflags, UDBA_REVAL); -+ -+ opt = opts->opt; -+ while (err >= 0 && opt->type != Opt_tail) -+ err = au_opt_br(sb, opt++, opts); -+ if (err > 0) -+ err = 0; -+ else if (unlikely(err < 0)) -+ goto out; -+ -+ bend = au_sbend(sb); -+ if (unlikely(bend < 0)) { -+ err = -EINVAL; -+ pr_err("no branches\n"); -+ goto out; -+ } -+ -+ if (au_opt_test(tmp, XINO)) -+ au_opt_set(sbinfo->si_mntflags, XINO); -+ opt = opts->opt; -+ while (!err && opt->type != Opt_tail) -+ err = au_opt_xino(sb, opt++, &opt_xino, opts); -+ if (unlikely(err)) -+ goto out; -+ -+ err = au_opts_verify(sb, sb->s_flags, tmp); -+ if (unlikely(err)) -+ goto out; -+ -+ /* restore xino */ -+ if (au_opt_test(tmp, XINO) && !opt_xino) { -+ xino.file = au_xino_def(sb); -+ err = PTR_ERR(xino.file); -+ if (IS_ERR(xino.file)) -+ goto out; -+ -+ err = au_xino_set(sb, &xino, /*remount*/0); -+ fput(xino.file); -+ if (unlikely(err)) -+ goto out; -+ } -+ -+ /* restore udba */ -+ tmp &= AuOptMask_UDBA; -+ sbinfo->si_mntflags &= ~AuOptMask_UDBA; -+ sbinfo->si_mntflags |= tmp; -+ bend = au_sbend(sb); -+ for (bindex = 0; bindex <= bend; bindex++) { -+ br = au_sbr(sb, bindex); -+ err = au_hnotify_reset_br(tmp, br, br->br_perm); -+ if (unlikely(err)) -+ AuIOErr("hnotify failed on br %d, %d, ignored\n", -+ bindex, err); -+ /* go on even if err */ -+ } -+ if (au_opt_test(tmp, UDBA_HNOTIFY)) { -+ struct inode *dir = sb->s_root->d_inode; -+ au_hn_reset(dir, au_hi_flags(dir, /*isdir*/1) & ~AuHi_XINO); -+ } -+ -+out: -+ return err; -+} -+ -+int au_opts_remount(struct super_block *sb, struct au_opts *opts) -+{ -+ int err, rerr; -+ struct inode *dir; -+ struct au_opt_xino *opt_xino; -+ struct au_opt *opt; -+ struct au_sbinfo *sbinfo; -+ -+ SiMustWriteLock(sb); -+ -+ dir = sb->s_root->d_inode; -+ sbinfo = au_sbi(sb); -+ err = 0; -+ opt_xino = NULL; -+ opt = opts->opt; -+ while (err >= 0 && opt->type != Opt_tail) { -+ err = au_opt_simple(sb, opt, opts); -+ if (!err) -+ err = au_opt_br(sb, opt, opts); -+ if (!err) -+ err = au_opt_xino(sb, opt, &opt_xino, opts); -+ opt++; -+ } -+ if (err > 0) -+ err = 0; -+ AuTraceErr(err); -+ /* go on even err */ -+ -+ rerr = au_opts_verify(sb, opts->sb_flags, /*pending*/0); -+ if (unlikely(rerr && !err)) -+ err = rerr; -+ -+ if (au_ftest_opts(opts->flags, TRUNC_XIB)) { -+ rerr = au_xib_trunc(sb); -+ if (unlikely(rerr && !err)) -+ err = rerr; -+ } -+ -+ /* will be handled by the caller */ -+ if (!au_ftest_opts(opts->flags, REFRESH) -+ && (opts->given_udba || au_opt_test(sbinfo->si_mntflags, XINO))) -+ au_fset_opts(opts->flags, REFRESH); -+ -+ AuDbg("status 0x%x\n", opts->flags); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+unsigned int au_opt_udba(struct super_block *sb) -+{ -+ return au_mntflags(sb) & AuOptMask_UDBA; -+} -diff -Nur linux-2.6.36.orig/fs/aufs/opts.h linux-2.6.36/fs/aufs/opts.h ---- linux-2.6.36.orig/fs/aufs/opts.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/opts.h 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,210 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * mount options/flags -+ */ -+ -+#ifndef __AUFS_OPTS_H__ -+#define __AUFS_OPTS_H__ -+ -+#ifdef __KERNEL__ -+ -+#include -+#include -+ -+struct file; -+struct super_block; -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* mount flags */ -+#define AuOpt_XINO 1 /* external inode number bitmap -+ and translation table */ -+#define AuOpt_TRUNC_XINO (1 << 1) /* truncate xino files */ -+#define AuOpt_UDBA_NONE (1 << 2) /* users direct branch access */ -+#define AuOpt_UDBA_REVAL (1 << 3) -+#define AuOpt_UDBA_HNOTIFY (1 << 4) -+#define AuOpt_SHWH (1 << 5) /* show whiteout */ -+#define AuOpt_PLINK (1 << 6) /* pseudo-link */ -+#define AuOpt_DIRPERM1 (1 << 7) /* unimplemented */ -+#define AuOpt_REFROF (1 << 8) /* unimplemented */ -+#define AuOpt_ALWAYS_DIROPQ (1 << 9) /* policy to creating diropq */ -+#define AuOpt_SUM (1 << 10) /* summation for statfs(2) */ -+#define AuOpt_SUM_W (1 << 11) /* unimplemented */ -+#define AuOpt_WARN_PERM (1 << 12) /* warn when add-branch */ -+#define AuOpt_VERBOSE (1 << 13) /* busy inode when del-branch */ -+#define AuOpt_DIO (1 << 14) /* direct io */ -+ -+#ifndef CONFIG_AUFS_HNOTIFY -+#undef AuOpt_UDBA_HNOTIFY -+#define AuOpt_UDBA_HNOTIFY 0 -+#endif -+#ifndef CONFIG_AUFS_SHWH -+#undef AuOpt_SHWH -+#define AuOpt_SHWH 0 -+#endif -+ -+#define AuOpt_Def (AuOpt_XINO \ -+ | AuOpt_UDBA_REVAL \ -+ | AuOpt_PLINK \ -+ /* | AuOpt_DIRPERM1 */ \ -+ | AuOpt_WARN_PERM) -+#define AuOptMask_UDBA (AuOpt_UDBA_NONE \ -+ | AuOpt_UDBA_REVAL \ -+ | AuOpt_UDBA_HNOTIFY) -+ -+#define au_opt_test(flags, name) (flags & AuOpt_##name) -+#define au_opt_set(flags, name) do { \ -+ BUILD_BUG_ON(AuOpt_##name & AuOptMask_UDBA); \ -+ ((flags) |= AuOpt_##name); \ -+} while (0) -+#define au_opt_set_udba(flags, name) do { \ -+ (flags) &= ~AuOptMask_UDBA; \ -+ ((flags) |= AuOpt_##name); \ -+} while (0) -+#define au_opt_clr(flags, name) do { \ -+ ((flags) &= ~AuOpt_##name); \ -+} while (0) -+ -+static inline unsigned int au_opts_plink(unsigned int mntflags) -+{ -+#ifdef CONFIG_PROC_FS -+ return mntflags; -+#else -+ return mntflags & ~AuOpt_PLINK; -+#endif -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* policies to select one among multiple writable branches */ -+enum { -+ AuWbrCreate_TDP, /* top down parent */ -+ AuWbrCreate_RR, /* round robin */ -+ AuWbrCreate_MFS, /* most free space */ -+ AuWbrCreate_MFSV, /* mfs with seconds */ -+ AuWbrCreate_MFSRR, /* mfs then rr */ -+ AuWbrCreate_MFSRRV, /* mfs then rr with seconds */ -+ AuWbrCreate_PMFS, /* parent and mfs */ -+ AuWbrCreate_PMFSV, /* parent and mfs with seconds */ -+ -+ AuWbrCreate_Def = AuWbrCreate_TDP -+}; -+ -+enum { -+ AuWbrCopyup_TDP, /* top down parent */ -+ AuWbrCopyup_BUP, /* bottom up parent */ -+ AuWbrCopyup_BU, /* bottom up */ -+ -+ AuWbrCopyup_Def = AuWbrCopyup_TDP -+}; -+ -+/* ---------------------------------------------------------------------- */ -+ -+struct au_opt_add { -+ aufs_bindex_t bindex; -+ char *pathname; -+ int perm; -+ struct path path; -+}; -+ -+struct au_opt_del { -+ char *pathname; -+ struct path h_path; -+}; -+ -+struct au_opt_mod { -+ char *path; -+ int perm; -+ struct dentry *h_root; -+}; -+ -+struct au_opt_xino { -+ char *path; -+ struct file *file; -+}; -+ -+struct au_opt_xino_itrunc { -+ aufs_bindex_t bindex; -+}; -+ -+struct au_opt_wbr_create { -+ int wbr_create; -+ int mfs_second; -+ unsigned long long mfsrr_watermark; -+}; -+ -+struct au_opt { -+ int type; -+ union { -+ struct au_opt_xino xino; -+ struct au_opt_xino_itrunc xino_itrunc; -+ struct au_opt_add add; -+ struct au_opt_del del; -+ struct au_opt_mod mod; -+ int dirwh; -+ int rdcache; -+ unsigned int rdblk; -+ unsigned int rdhash; -+ int udba; -+ struct au_opt_wbr_create wbr_create; -+ int wbr_copyup; -+ }; -+}; -+ -+/* opts flags */ -+#define AuOpts_REMOUNT 1 -+#define AuOpts_REFRESH (1 << 1) -+#define AuOpts_TRUNC_XIB (1 << 2) -+#define AuOpts_REFRESH_DYAOP (1 << 3) -+#define au_ftest_opts(flags, name) ((flags) & AuOpts_##name) -+#define au_fset_opts(flags, name) \ -+ do { (flags) |= AuOpts_##name; } while (0) -+#define au_fclr_opts(flags, name) \ -+ do { (flags) &= ~AuOpts_##name; } while (0) -+ -+struct au_opts { -+ struct au_opt *opt; -+ int max_opt; -+ -+ unsigned int given_udba; -+ unsigned int flags; -+ unsigned long sb_flags; -+}; -+ -+/* ---------------------------------------------------------------------- */ -+ -+const char *au_optstr_br_perm(int brperm); -+const char *au_optstr_udba(int udba); -+const char *au_optstr_wbr_copyup(int wbr_copyup); -+const char *au_optstr_wbr_create(int wbr_create); -+ -+void au_opts_free(struct au_opts *opts); -+int au_opts_parse(struct super_block *sb, char *str, struct au_opts *opts); -+int au_opts_verify(struct super_block *sb, unsigned long sb_flags, -+ unsigned int pending); -+int au_opts_mount(struct super_block *sb, struct au_opts *opts); -+int au_opts_remount(struct super_block *sb, struct au_opts *opts); -+ -+unsigned int au_opt_udba(struct super_block *sb); -+ -+/* ---------------------------------------------------------------------- */ -+ -+#endif /* __KERNEL__ */ -+#endif /* __AUFS_OPTS_H__ */ -diff -Nur linux-2.6.36.orig/fs/aufs/plink.c linux-2.6.36/fs/aufs/plink.c ---- linux-2.6.36.orig/fs/aufs/plink.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/plink.c 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,515 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * pseudo-link -+ */ -+ -+#include "aufs.h" -+ -+/* -+ * the pseudo-link maintenance mode. -+ * during a user process maintains the pseudo-links, -+ * prohibit adding a new plink and branch manipulation. -+ * -+ * Flags -+ * NOPLM: -+ * For entry functions which will handle plink, and i_mutex is already held -+ * in VFS. -+ * They cannot wait and should return an error at once. -+ * Callers has to check the error. -+ * NOPLMW: -+ * For entry functions which will handle plink, but i_mutex is not held -+ * in VFS. -+ * They can wait the plink maintenance mode to finish. -+ * -+ * They behave like F_SETLK and F_SETLKW. -+ * If the caller never handle plink, then both flags are unnecessary. -+ */ -+ -+int au_plink_maint(struct super_block *sb, int flags) -+{ -+ int err; -+ pid_t pid, ppid; -+ struct au_sbinfo *sbi; -+ -+ SiMustAnyLock(sb); -+ -+ err = 0; -+ if (!au_opt_test(au_mntflags(sb), PLINK)) -+ goto out; -+ -+ sbi = au_sbi(sb); -+ pid = sbi->si_plink_maint_pid; -+ if (!pid || pid == current->pid) -+ goto out; -+ -+ /* todo: it highly depends upon /sbin/mount.aufs */ -+ rcu_read_lock(); -+ ppid = task_pid_vnr(rcu_dereference(current->real_parent)); -+ rcu_read_unlock(); -+ if (pid == ppid) -+ goto out; -+ -+ if (au_ftest_lock(flags, NOPLMW)) { -+ /* if there is no i_mutex lock in VFS, we don't need to wait */ -+ /* AuDebugOn(!lockdep_depth(current)); */ -+ while (sbi->si_plink_maint_pid) { -+ si_read_unlock(sb); -+ /* gave up wake_up_bit() */ -+ wait_event(sbi->si_plink_wq, !sbi->si_plink_maint_pid); -+ -+ if (au_ftest_lock(flags, FLUSH)) -+ au_nwt_flush(&sbi->si_nowait); -+ si_noflush_read_lock(sb); -+ } -+ } else if (au_ftest_lock(flags, NOPLM)) { -+ AuDbg("ppid %d, pid %d\n", ppid, pid); -+ err = -EAGAIN; -+ } -+ -+out: -+ return err; -+} -+ -+void au_plink_maint_leave(struct au_sbinfo *sbinfo) -+{ -+ spin_lock(&sbinfo->si_plink_maint_lock); -+ sbinfo->si_plink_maint_pid = 0; -+ spin_unlock(&sbinfo->si_plink_maint_lock); -+ wake_up_all(&sbinfo->si_plink_wq); -+} -+ -+int au_plink_maint_enter(struct super_block *sb) -+{ -+ int err; -+ struct au_sbinfo *sbinfo; -+ -+ err = 0; -+ sbinfo = au_sbi(sb); -+ /* make sure i am the only one in this fs */ -+ si_write_lock(sb, AuLock_FLUSH); -+ if (au_opt_test(au_mntflags(sb), PLINK)) { -+ spin_lock(&sbinfo->si_plink_maint_lock); -+ if (!sbinfo->si_plink_maint_pid) -+ sbinfo->si_plink_maint_pid = current->pid; -+ else -+ err = -EBUSY; -+ spin_unlock(&sbinfo->si_plink_maint_lock); -+ } -+ si_write_unlock(sb); -+ -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+struct pseudo_link { -+ union { -+ struct list_head list; -+ struct rcu_head rcu; -+ }; -+ struct inode *inode; -+}; -+ -+#ifdef CONFIG_AUFS_DEBUG -+void au_plink_list(struct super_block *sb) -+{ -+ struct au_sbinfo *sbinfo; -+ struct list_head *plink_list; -+ struct pseudo_link *plink; -+ -+ SiMustAnyLock(sb); -+ -+ sbinfo = au_sbi(sb); -+ AuDebugOn(!au_opt_test(au_mntflags(sb), PLINK)); -+ AuDebugOn(au_plink_maint(sb, AuLock_NOPLM)); -+ -+ plink_list = &sbinfo->si_plink.head; -+ rcu_read_lock(); -+ list_for_each_entry_rcu(plink, plink_list, list) -+ AuDbg("%lu\n", plink->inode->i_ino); -+ rcu_read_unlock(); -+} -+#endif -+ -+/* is the inode pseudo-linked? */ -+int au_plink_test(struct inode *inode) -+{ -+ int found; -+ struct au_sbinfo *sbinfo; -+ struct list_head *plink_list; -+ struct pseudo_link *plink; -+ -+ sbinfo = au_sbi(inode->i_sb); -+ AuRwMustAnyLock(&sbinfo->si_rwsem); -+ AuDebugOn(!au_opt_test(au_mntflags(inode->i_sb), PLINK)); -+ AuDebugOn(au_plink_maint(inode->i_sb, AuLock_NOPLM)); -+ -+ found = 0; -+ plink_list = &sbinfo->si_plink.head; -+ rcu_read_lock(); -+ list_for_each_entry_rcu(plink, plink_list, list) -+ if (plink->inode == inode) { -+ found = 1; -+ break; -+ } -+ rcu_read_unlock(); -+ return found; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * generate a name for plink. -+ * the file will be stored under AUFS_WH_PLINKDIR. -+ */ -+/* 20 is max digits length of ulong 64 */ -+#define PLINK_NAME_LEN ((20 + 1) * 2) -+ -+static int plink_name(char *name, int len, struct inode *inode, -+ aufs_bindex_t bindex) -+{ -+ int rlen; -+ struct inode *h_inode; -+ -+ h_inode = au_h_iptr(inode, bindex); -+ rlen = snprintf(name, len, "%lu.%lu", inode->i_ino, h_inode->i_ino); -+ return rlen; -+} -+ -+struct au_do_plink_lkup_args { -+ struct dentry **errp; -+ struct qstr *tgtname; -+ struct dentry *h_parent; -+ struct au_branch *br; -+}; -+ -+static struct dentry *au_do_plink_lkup(struct qstr *tgtname, -+ struct dentry *h_parent, -+ struct au_branch *br) -+{ -+ struct dentry *h_dentry; -+ struct mutex *h_mtx; -+ -+ h_mtx = &h_parent->d_inode->i_mutex; -+ mutex_lock_nested(h_mtx, AuLsc_I_CHILD2); -+ h_dentry = au_lkup_one(tgtname, h_parent, br, /*nd*/NULL); -+ mutex_unlock(h_mtx); -+ return h_dentry; -+} -+ -+static void au_call_do_plink_lkup(void *args) -+{ -+ struct au_do_plink_lkup_args *a = args; -+ *a->errp = au_do_plink_lkup(a->tgtname, a->h_parent, a->br); -+} -+ -+/* lookup the plink-ed @inode under the branch at @bindex */ -+struct dentry *au_plink_lkup(struct inode *inode, aufs_bindex_t bindex) -+{ -+ struct dentry *h_dentry, *h_parent; -+ struct au_branch *br; -+ struct inode *h_dir; -+ int wkq_err; -+ char a[PLINK_NAME_LEN]; -+ struct qstr tgtname = { -+ .name = a -+ }; -+ -+ AuDebugOn(au_plink_maint(inode->i_sb, AuLock_NOPLM)); -+ -+ br = au_sbr(inode->i_sb, bindex); -+ h_parent = br->br_wbr->wbr_plink; -+ h_dir = h_parent->d_inode; -+ tgtname.len = plink_name(a, sizeof(a), inode, bindex); -+ -+ if (current_fsuid()) { -+ struct au_do_plink_lkup_args args = { -+ .errp = &h_dentry, -+ .tgtname = &tgtname, -+ .h_parent = h_parent, -+ .br = br -+ }; -+ -+ wkq_err = au_wkq_wait(au_call_do_plink_lkup, &args); -+ if (unlikely(wkq_err)) -+ h_dentry = ERR_PTR(wkq_err); -+ } else -+ h_dentry = au_do_plink_lkup(&tgtname, h_parent, br); -+ -+ return h_dentry; -+} -+ -+/* create a pseudo-link */ -+static int do_whplink(struct qstr *tgt, struct dentry *h_parent, -+ struct dentry *h_dentry, struct au_branch *br) -+{ -+ int err; -+ struct path h_path = { -+ .mnt = br->br_mnt -+ }; -+ struct inode *h_dir; -+ -+ h_dir = h_parent->d_inode; -+ mutex_lock_nested(&h_dir->i_mutex, AuLsc_I_CHILD2); -+again: -+ h_path.dentry = au_lkup_one(tgt, h_parent, br, /*nd*/NULL); -+ err = PTR_ERR(h_path.dentry); -+ if (IS_ERR(h_path.dentry)) -+ goto out; -+ -+ err = 0; -+ /* wh.plink dir is not monitored */ -+ /* todo: is it really safe? */ -+ if (h_path.dentry->d_inode -+ && h_path.dentry->d_inode != h_dentry->d_inode) { -+ err = vfsub_unlink(h_dir, &h_path, /*force*/0); -+ dput(h_path.dentry); -+ h_path.dentry = NULL; -+ if (!err) -+ goto again; -+ } -+ if (!err && !h_path.dentry->d_inode) -+ err = vfsub_link(h_dentry, h_dir, &h_path); -+ dput(h_path.dentry); -+ -+out: -+ mutex_unlock(&h_dir->i_mutex); -+ return err; -+} -+ -+struct do_whplink_args { -+ int *errp; -+ struct qstr *tgt; -+ struct dentry *h_parent; -+ struct dentry *h_dentry; -+ struct au_branch *br; -+}; -+ -+static void call_do_whplink(void *args) -+{ -+ struct do_whplink_args *a = args; -+ *a->errp = do_whplink(a->tgt, a->h_parent, a->h_dentry, a->br); -+} -+ -+static int whplink(struct dentry *h_dentry, struct inode *inode, -+ aufs_bindex_t bindex, struct au_branch *br) -+{ -+ int err, wkq_err; -+ struct au_wbr *wbr; -+ struct dentry *h_parent; -+ struct inode *h_dir; -+ char a[PLINK_NAME_LEN]; -+ struct qstr tgtname = { -+ .name = a -+ }; -+ -+ wbr = au_sbr(inode->i_sb, bindex)->br_wbr; -+ h_parent = wbr->wbr_plink; -+ h_dir = h_parent->d_inode; -+ tgtname.len = plink_name(a, sizeof(a), inode, bindex); -+ -+ /* always superio. */ -+ if (current_fsuid()) { -+ struct do_whplink_args args = { -+ .errp = &err, -+ .tgt = &tgtname, -+ .h_parent = h_parent, -+ .h_dentry = h_dentry, -+ .br = br -+ }; -+ wkq_err = au_wkq_wait(call_do_whplink, &args); -+ if (unlikely(wkq_err)) -+ err = wkq_err; -+ } else -+ err = do_whplink(&tgtname, h_parent, h_dentry, br); -+ -+ return err; -+} -+ -+/* free a single plink */ -+static void do_put_plink(struct pseudo_link *plink, int do_del) -+{ -+ if (do_del) -+ list_del(&plink->list); -+ iput(plink->inode); -+ kfree(plink); -+} -+ -+static void do_put_plink_rcu(struct rcu_head *rcu) -+{ -+ struct pseudo_link *plink; -+ -+ plink = container_of(rcu, struct pseudo_link, rcu); -+ iput(plink->inode); -+ kfree(plink); -+} -+ -+/* -+ * create a new pseudo-link for @h_dentry on @bindex. -+ * the linked inode is held in aufs @inode. -+ */ -+void au_plink_append(struct inode *inode, aufs_bindex_t bindex, -+ struct dentry *h_dentry) -+{ -+ struct super_block *sb; -+ struct au_sbinfo *sbinfo; -+ struct list_head *plink_list; -+ struct pseudo_link *plink, *tmp; -+ int found, err, cnt; -+ -+ sb = inode->i_sb; -+ sbinfo = au_sbi(sb); -+ AuDebugOn(!au_opt_test(au_mntflags(sb), PLINK)); -+ AuDebugOn(au_plink_maint(sb, AuLock_NOPLM)); -+ -+ cnt = 0; -+ found = 0; -+ plink_list = &sbinfo->si_plink.head; -+ rcu_read_lock(); -+ list_for_each_entry_rcu(plink, plink_list, list) { -+ cnt++; -+ if (plink->inode == inode) { -+ found = 1; -+ break; -+ } -+ } -+ rcu_read_unlock(); -+ if (found) -+ return; -+ -+ tmp = kmalloc(sizeof(*plink), GFP_NOFS); -+ if (tmp) -+ tmp->inode = au_igrab(inode); -+ else { -+ err = -ENOMEM; -+ goto out; -+ } -+ -+ spin_lock(&sbinfo->si_plink.spin); -+ list_for_each_entry(plink, plink_list, list) { -+ if (plink->inode == inode) { -+ found = 1; -+ break; -+ } -+ } -+ if (!found) -+ list_add_rcu(&tmp->list, plink_list); -+ spin_unlock(&sbinfo->si_plink.spin); -+ if (!found) { -+ cnt++; -+ WARN_ONCE(cnt > AUFS_PLINK_WARN, -+ "unexpectedly many pseudo links, %d\n", cnt); -+ err = whplink(h_dentry, inode, bindex, au_sbr(sb, bindex)); -+ } else { -+ do_put_plink(tmp, 0); -+ return; -+ } -+ -+out: -+ if (unlikely(err)) { -+ pr_warning("err %d, damaged pseudo link.\n", err); -+ if (tmp) { -+ au_spl_del_rcu(&tmp->list, &sbinfo->si_plink); -+ call_rcu(&tmp->rcu, do_put_plink_rcu); -+ } -+ } -+} -+ -+/* free all plinks */ -+void au_plink_put(struct super_block *sb, int verbose) -+{ -+ struct au_sbinfo *sbinfo; -+ struct list_head *plink_list; -+ struct pseudo_link *plink, *tmp; -+ -+ SiMustWriteLock(sb); -+ -+ sbinfo = au_sbi(sb); -+ AuDebugOn(!au_opt_test(au_mntflags(sb), PLINK)); -+ AuDebugOn(au_plink_maint(sb, AuLock_NOPLM)); -+ -+ plink_list = &sbinfo->si_plink.head; -+ /* no spin_lock since sbinfo is write-locked */ -+ WARN(verbose && !list_empty(plink_list), "pseudo-link is not flushed"); -+ list_for_each_entry_safe(plink, tmp, plink_list, list) -+ do_put_plink(plink, 0); -+ INIT_LIST_HEAD(plink_list); -+} -+ -+void au_plink_clean(struct super_block *sb, int verbose) -+{ -+ struct dentry *root; -+ -+ root = sb->s_root; -+ aufs_write_lock(root); -+ if (au_opt_test(au_mntflags(sb), PLINK)) -+ au_plink_put(sb, verbose); -+ aufs_write_unlock(root); -+} -+ -+/* free the plinks on a branch specified by @br_id */ -+void au_plink_half_refresh(struct super_block *sb, aufs_bindex_t br_id) -+{ -+ struct au_sbinfo *sbinfo; -+ struct list_head *plink_list; -+ struct pseudo_link *plink, *tmp; -+ struct inode *inode; -+ aufs_bindex_t bstart, bend, bindex; -+ unsigned char do_put; -+ -+ SiMustWriteLock(sb); -+ -+ sbinfo = au_sbi(sb); -+ AuDebugOn(!au_opt_test(au_mntflags(sb), PLINK)); -+ AuDebugOn(au_plink_maint(sb, AuLock_NOPLM)); -+ -+ plink_list = &sbinfo->si_plink.head; -+ /* no spin_lock since sbinfo is write-locked */ -+ list_for_each_entry_safe(plink, tmp, plink_list, list) { -+ do_put = 0; -+ inode = au_igrab(plink->inode); -+ ii_write_lock_child(inode); -+ bstart = au_ibstart(inode); -+ bend = au_ibend(inode); -+ if (bstart >= 0) { -+ for (bindex = bstart; bindex <= bend; bindex++) { -+ if (!au_h_iptr(inode, bindex) -+ || au_ii_br_id(inode, bindex) != br_id) -+ continue; -+ au_set_h_iptr(inode, bindex, NULL, 0); -+ do_put = 1; -+ break; -+ } -+ } else -+ do_put_plink(plink, 1); -+ -+ if (do_put) { -+ for (bindex = bstart; bindex <= bend; bindex++) -+ if (au_h_iptr(inode, bindex)) { -+ do_put = 0; -+ break; -+ } -+ if (do_put) -+ do_put_plink(plink, 1); -+ } -+ ii_write_unlock(inode); -+ iput(inode); -+ } -+} -diff -Nur linux-2.6.36.orig/fs/aufs/poll.c linux-2.6.36/fs/aufs/poll.c ---- linux-2.6.36.orig/fs/aufs/poll.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/poll.c 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,56 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * poll operation -+ * There is only one filesystem which implements ->poll operation, currently. -+ */ -+ -+#include "aufs.h" -+ -+unsigned int aufs_poll(struct file *file, poll_table *wait) -+{ -+ unsigned int mask; -+ int err; -+ struct file *h_file; -+ struct dentry *dentry; -+ struct super_block *sb; -+ -+ /* We should pretend an error happened. */ -+ mask = POLLERR /* | POLLIN | POLLOUT */; -+ dentry = file->f_dentry; -+ sb = dentry->d_sb; -+ si_read_lock(sb, AuLock_FLUSH | AuLock_NOPLMW); -+ err = au_reval_and_lock_fdi(file, au_reopen_nondir, /*wlock*/0); -+ if (unlikely(err)) -+ goto out; -+ -+ /* it is not an error if h_file has no operation */ -+ mask = DEFAULT_POLLMASK; -+ h_file = au_hf_top(file); -+ if (h_file->f_op && h_file->f_op->poll) -+ mask = h_file->f_op->poll(h_file, wait); -+ -+ di_read_unlock(dentry, AuLock_IR); -+ fi_read_unlock(file); -+ -+out: -+ si_read_unlock(sb); -+ AuTraceErr((int)mask); -+ return mask; -+} -diff -Nur linux-2.6.36.orig/fs/aufs/procfs.c linux-2.6.36/fs/aufs/procfs.c ---- linux-2.6.36.orig/fs/aufs/procfs.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/procfs.c 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,169 @@ -+/* -+ * Copyright (C) 2010-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * procfs interfaces -+ */ -+ -+#include -+#include "aufs.h" -+ -+static int au_procfs_plm_release(struct inode *inode, struct file *file) -+{ -+ struct au_sbinfo *sbinfo; -+ -+ sbinfo = file->private_data; -+ if (sbinfo) { -+ au_plink_maint_leave(sbinfo); -+ kobject_put(&sbinfo->si_kobj); -+ } -+ -+ return 0; -+} -+ -+static void au_procfs_plm_write_clean(struct file *file) -+{ -+ struct au_sbinfo *sbinfo; -+ -+ sbinfo = file->private_data; -+ if (sbinfo) -+ au_plink_clean(sbinfo->si_sb, /*verbose*/0); -+} -+ -+static int au_procfs_plm_write_si(struct file *file, unsigned long id) -+{ -+ int err; -+ struct super_block *sb; -+ struct au_sbinfo *sbinfo; -+ -+ err = -EBUSY; -+ if (unlikely(file->private_data)) -+ goto out; -+ -+ sb = NULL; -+ spin_lock(&au_sbilist.spin); -+ list_for_each_entry(sbinfo, &au_sbilist.head, si_list) -+ if (id == sysaufs_si_id(sbinfo)) { -+ kobject_get(&sbinfo->si_kobj); -+ sb = sbinfo->si_sb; -+ break; -+ } -+ spin_unlock(&au_sbilist.spin); -+ -+ err = -EINVAL; -+ if (unlikely(!sb)) -+ goto out; -+ -+ err = au_plink_maint_enter(sb); -+ if (!err) -+ /* keep kobject_get() */ -+ file->private_data = sbinfo; -+ else -+ kobject_put(&sbinfo->si_kobj); -+out: -+ return err; -+} -+ -+/* -+ * Accept a valid "si=xxxx" only. -+ * Once it is accepted successfully, accept "clean" too. -+ */ -+static ssize_t au_procfs_plm_write(struct file *file, const char __user *ubuf, -+ size_t count, loff_t *ppos) -+{ -+ ssize_t err; -+ unsigned long id; -+ /* last newline is allowed */ -+ char buf[3 + sizeof(unsigned long) * 2 + 1]; -+ -+ err = -EACCES; -+ if (unlikely(!capable(CAP_SYS_ADMIN))) -+ goto out; -+ -+ err = -EINVAL; -+ if (unlikely(count > sizeof(buf))) -+ goto out; -+ -+ err = copy_from_user(buf, ubuf, count); -+ if (unlikely(err)) { -+ err = -EFAULT; -+ goto out; -+ } -+ buf[count] = 0; -+ -+ err = -EINVAL; -+ if (!strcmp("clean", buf)) { -+ au_procfs_plm_write_clean(file); -+ goto out_success; -+ } else if (unlikely(strncmp("si=", buf, 3))) -+ goto out; -+ -+ err = strict_strtoul(buf + 3, 16, &id); -+ if (unlikely(err)) -+ goto out; -+ -+ err = au_procfs_plm_write_si(file, id); -+ if (unlikely(err)) -+ goto out; -+ -+out_success: -+ err = count; /* success */ -+out: -+ return err; -+} -+ -+static const struct file_operations au_procfs_plm_fop = { -+ .write = au_procfs_plm_write, -+ .release = au_procfs_plm_release, -+ .owner = THIS_MODULE -+}; -+ -+/* ---------------------------------------------------------------------- */ -+ -+static struct proc_dir_entry *au_procfs_dir; -+ -+void au_procfs_fin(void) -+{ -+ remove_proc_entry(AUFS_PLINK_MAINT_NAME, au_procfs_dir); -+ remove_proc_entry(AUFS_PLINK_MAINT_DIR, NULL); -+} -+ -+int __init au_procfs_init(void) -+{ -+ int err; -+ struct proc_dir_entry *entry; -+ -+ err = -ENOMEM; -+ au_procfs_dir = proc_mkdir(AUFS_PLINK_MAINT_DIR, NULL); -+ if (unlikely(!au_procfs_dir)) -+ goto out; -+ -+ entry = proc_create(AUFS_PLINK_MAINT_NAME, S_IFREG | S_IWUSR, -+ au_procfs_dir, &au_procfs_plm_fop); -+ if (unlikely(!entry)) -+ goto out_dir; -+ -+ err = 0; -+ goto out; /* success */ -+ -+ -+out_dir: -+ remove_proc_entry(AUFS_PLINK_MAINT_DIR, NULL); -+out: -+ return err; -+} -diff -Nur linux-2.6.36.orig/fs/aufs/rdu.c linux-2.6.36/fs/aufs/rdu.c ---- linux-2.6.36.orig/fs/aufs/rdu.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/rdu.c 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,383 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * readdir in userspace. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include "aufs.h" -+ -+/* bits for struct aufs_rdu.flags */ -+#define AuRdu_CALLED 1 -+#define AuRdu_CONT (1 << 1) -+#define AuRdu_FULL (1 << 2) -+#define au_ftest_rdu(flags, name) ((flags) & AuRdu_##name) -+#define au_fset_rdu(flags, name) \ -+ do { (flags) |= AuRdu_##name; } while (0) -+#define au_fclr_rdu(flags, name) \ -+ do { (flags) &= ~AuRdu_##name; } while (0) -+ -+struct au_rdu_arg { -+ struct aufs_rdu *rdu; -+ union au_rdu_ent_ul ent; -+ unsigned long end; -+ -+ struct super_block *sb; -+ int err; -+}; -+ -+static int au_rdu_fill(void *__arg, const char *name, int nlen, -+ loff_t offset, u64 h_ino, unsigned int d_type) -+{ -+ int err, len; -+ struct au_rdu_arg *arg = __arg; -+ struct aufs_rdu *rdu = arg->rdu; -+ struct au_rdu_ent ent; -+ -+ err = 0; -+ arg->err = 0; -+ au_fset_rdu(rdu->cookie.flags, CALLED); -+ len = au_rdu_len(nlen); -+ if (arg->ent.ul + len < arg->end) { -+ ent.ino = h_ino; -+ ent.bindex = rdu->cookie.bindex; -+ ent.type = d_type; -+ ent.nlen = nlen; -+ if (unlikely(nlen > AUFS_MAX_NAMELEN)) -+ ent.type = DT_UNKNOWN; -+ -+ err = -EFAULT; -+ if (copy_to_user(arg->ent.e, &ent, sizeof(ent))) -+ goto out; -+ if (copy_to_user(arg->ent.e->name, name, nlen)) -+ goto out; -+ /* the terminating NULL */ -+ if (__put_user(0, arg->ent.e->name + nlen)) -+ goto out; -+ err = 0; -+ /* AuDbg("%p, %.*s\n", arg->ent.p, nlen, name); */ -+ arg->ent.ul += len; -+ rdu->rent++; -+ } else { -+ err = -EFAULT; -+ au_fset_rdu(rdu->cookie.flags, FULL); -+ rdu->full = 1; -+ rdu->tail = arg->ent; -+ } -+ -+out: -+ /* AuTraceErr(err); */ -+ return err; -+} -+ -+static int au_rdu_do(struct file *h_file, struct au_rdu_arg *arg) -+{ -+ int err; -+ loff_t offset; -+ struct au_rdu_cookie *cookie = &arg->rdu->cookie; -+ -+ offset = vfsub_llseek(h_file, cookie->h_pos, SEEK_SET); -+ err = offset; -+ if (unlikely(offset != cookie->h_pos)) -+ goto out; -+ -+ err = 0; -+ do { -+ arg->err = 0; -+ au_fclr_rdu(cookie->flags, CALLED); -+ /* smp_mb(); */ -+ err = vfsub_readdir(h_file, au_rdu_fill, arg); -+ if (err >= 0) -+ err = arg->err; -+ } while (!err -+ && au_ftest_rdu(cookie->flags, CALLED) -+ && !au_ftest_rdu(cookie->flags, FULL)); -+ cookie->h_pos = h_file->f_pos; -+ -+out: -+ AuTraceErr(err); -+ return err; -+} -+ -+static int au_rdu(struct file *file, struct aufs_rdu *rdu) -+{ -+ int err; -+ aufs_bindex_t bend; -+ struct au_rdu_arg arg; -+ struct dentry *dentry; -+ struct inode *inode; -+ struct file *h_file; -+ struct au_rdu_cookie *cookie = &rdu->cookie; -+ -+ err = !access_ok(VERIFY_WRITE, rdu->ent.e, rdu->sz); -+ if (unlikely(err)) { -+ err = -EFAULT; -+ AuTraceErr(err); -+ goto out; -+ } -+ rdu->rent = 0; -+ rdu->tail = rdu->ent; -+ rdu->full = 0; -+ arg.rdu = rdu; -+ arg.ent = rdu->ent; -+ arg.end = arg.ent.ul; -+ arg.end += rdu->sz; -+ -+ err = -ENOTDIR; -+ if (unlikely(!file->f_op || !file->f_op->readdir)) -+ goto out; -+ -+ err = security_file_permission(file, MAY_READ); -+ AuTraceErr(err); -+ if (unlikely(err)) -+ goto out; -+ -+ dentry = file->f_dentry; -+ inode = dentry->d_inode; -+#if 1 -+ mutex_lock(&inode->i_mutex); -+#else -+ err = mutex_lock_killable(&inode->i_mutex); -+ AuTraceErr(err); -+ if (unlikely(err)) -+ goto out; -+#endif -+ -+ arg.sb = inode->i_sb; -+ err = si_read_lock(arg.sb, AuLock_FLUSH | AuLock_NOPLM); -+ if (unlikely(err)) -+ goto out_mtx; -+ err = au_alive_dir(dentry); -+ if (unlikely(err)) -+ goto out_si; -+ /* todo: reval? */ -+ fi_read_lock(file); -+ -+ err = -EAGAIN; -+ if (unlikely(au_ftest_rdu(cookie->flags, CONT) -+ && cookie->generation != au_figen(file))) -+ goto out_unlock; -+ -+ err = 0; -+ if (!rdu->blk) { -+ rdu->blk = au_sbi(arg.sb)->si_rdblk; -+ if (!rdu->blk) -+ rdu->blk = au_dir_size(file, /*dentry*/NULL); -+ } -+ bend = au_fbstart(file); -+ if (cookie->bindex < bend) -+ cookie->bindex = bend; -+ bend = au_fbend_dir(file); -+ /* AuDbg("b%d, b%d\n", cookie->bindex, bend); */ -+ for (; !err && cookie->bindex <= bend; -+ cookie->bindex++, cookie->h_pos = 0) { -+ h_file = au_hf_dir(file, cookie->bindex); -+ if (!h_file) -+ continue; -+ -+ au_fclr_rdu(cookie->flags, FULL); -+ err = au_rdu_do(h_file, &arg); -+ AuTraceErr(err); -+ if (unlikely(au_ftest_rdu(cookie->flags, FULL) || err)) -+ break; -+ } -+ AuDbg("rent %llu\n", rdu->rent); -+ -+ if (!err && !au_ftest_rdu(cookie->flags, CONT)) { -+ rdu->shwh = !!au_opt_test(au_sbi(arg.sb)->si_mntflags, SHWH); -+ au_fset_rdu(cookie->flags, CONT); -+ cookie->generation = au_figen(file); -+ } -+ -+ ii_read_lock_child(inode); -+ fsstack_copy_attr_atime(inode, au_h_iptr(inode, au_ibstart(inode))); -+ ii_read_unlock(inode); -+ -+out_unlock: -+ fi_read_unlock(file); -+out_si: -+ si_read_unlock(arg.sb); -+out_mtx: -+ mutex_unlock(&inode->i_mutex); -+out: -+ AuTraceErr(err); -+ return err; -+} -+ -+static int au_rdu_ino(struct file *file, struct aufs_rdu *rdu) -+{ -+ int err; -+ ino_t ino; -+ unsigned long long nent; -+ union au_rdu_ent_ul *u; -+ struct au_rdu_ent ent; -+ struct super_block *sb; -+ -+ err = 0; -+ nent = rdu->nent; -+ u = &rdu->ent; -+ sb = file->f_dentry->d_sb; -+ si_read_lock(sb, AuLock_FLUSH); -+ while (nent-- > 0) { -+ err = copy_from_user(&ent, u->e, sizeof(ent)); -+ if (!err) -+ err = !access_ok(VERIFY_WRITE, &u->e->ino, sizeof(ino)); -+ if (unlikely(err)) { -+ err = -EFAULT; -+ AuTraceErr(err); -+ break; -+ } -+ -+ /* AuDbg("b%d, i%llu\n", ent.bindex, ent.ino); */ -+ if (!ent.wh) -+ err = au_ino(sb, ent.bindex, ent.ino, ent.type, &ino); -+ else -+ err = au_wh_ino(sb, ent.bindex, ent.ino, ent.type, -+ &ino); -+ if (unlikely(err)) { -+ AuTraceErr(err); -+ break; -+ } -+ -+ err = __put_user(ino, &u->e->ino); -+ if (unlikely(err)) { -+ err = -EFAULT; -+ AuTraceErr(err); -+ break; -+ } -+ u->ul += au_rdu_len(ent.nlen); -+ } -+ si_read_unlock(sb); -+ -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int au_rdu_verify(struct aufs_rdu *rdu) -+{ -+ AuDbg("rdu{%llu, %p, %u | %u | %llu, %u, %u | " -+ "%llu, b%d, 0x%x, g%u}\n", -+ rdu->sz, rdu->ent.e, rdu->verify[AufsCtlRduV_SZ], -+ rdu->blk, -+ rdu->rent, rdu->shwh, rdu->full, -+ rdu->cookie.h_pos, rdu->cookie.bindex, rdu->cookie.flags, -+ rdu->cookie.generation); -+ -+ if (rdu->verify[AufsCtlRduV_SZ] == sizeof(*rdu)) -+ return 0; -+ -+ AuDbg("%u:%u\n", -+ rdu->verify[AufsCtlRduV_SZ], (unsigned int)sizeof(*rdu)); -+ return -EINVAL; -+} -+ -+long au_rdu_ioctl(struct file *file, unsigned int cmd, unsigned long arg) -+{ -+ long err, e; -+ struct aufs_rdu rdu; -+ void __user *p = (void __user *)arg; -+ -+ err = copy_from_user(&rdu, p, sizeof(rdu)); -+ if (unlikely(err)) { -+ err = -EFAULT; -+ AuTraceErr(err); -+ goto out; -+ } -+ err = au_rdu_verify(&rdu); -+ if (unlikely(err)) -+ goto out; -+ -+ switch (cmd) { -+ case AUFS_CTL_RDU: -+ err = au_rdu(file, &rdu); -+ if (unlikely(err)) -+ break; -+ -+ e = copy_to_user(p, &rdu, sizeof(rdu)); -+ if (unlikely(e)) { -+ err = -EFAULT; -+ AuTraceErr(err); -+ } -+ break; -+ case AUFS_CTL_RDU_INO: -+ err = au_rdu_ino(file, &rdu); -+ break; -+ -+ default: -+ /* err = -ENOTTY; */ -+ err = -EINVAL; -+ } -+ -+out: -+ AuTraceErr(err); -+ return err; -+} -+ -+#ifdef CONFIG_COMPAT -+long au_rdu_compat_ioctl(struct file *file, unsigned int cmd, unsigned long arg) -+{ -+ long err, e; -+ struct aufs_rdu rdu; -+ void __user *p = compat_ptr(arg); -+ -+ /* todo: get_user()? */ -+ err = copy_from_user(&rdu, p, sizeof(rdu)); -+ if (unlikely(err)) { -+ err = -EFAULT; -+ AuTraceErr(err); -+ goto out; -+ } -+ rdu.ent.e = compat_ptr(rdu.ent.ul); -+ err = au_rdu_verify(&rdu); -+ if (unlikely(err)) -+ goto out; -+ -+ switch (cmd) { -+ case AUFS_CTL_RDU: -+ err = au_rdu(file, &rdu); -+ if (unlikely(err)) -+ break; -+ -+ rdu.ent.ul = ptr_to_compat(rdu.ent.e); -+ rdu.tail.ul = ptr_to_compat(rdu.tail.e); -+ e = copy_to_user(p, &rdu, sizeof(rdu)); -+ if (unlikely(e)) { -+ err = -EFAULT; -+ AuTraceErr(err); -+ } -+ break; -+ case AUFS_CTL_RDU_INO: -+ err = au_rdu_ino(file, &rdu); -+ break; -+ -+ default: -+ /* err = -ENOTTY; */ -+ err = -EINVAL; -+ } -+ -+out: -+ AuTraceErr(err); -+ return err; -+} -+#endif -diff -Nur linux-2.6.36.orig/fs/aufs/rwsem.h linux-2.6.36/fs/aufs/rwsem.h ---- linux-2.6.36.orig/fs/aufs/rwsem.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/rwsem.h 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,189 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * simple read-write semaphore wrappers -+ */ -+ -+#ifndef __AUFS_RWSEM_H__ -+#define __AUFS_RWSEM_H__ -+ -+#ifdef __KERNEL__ -+ -+#include -+#include "debug.h" -+ -+struct au_rwsem { -+ struct rw_semaphore rwsem; -+#ifdef CONFIG_AUFS_DEBUG -+ /* just for debugging, not almighty counter */ -+ atomic_t rcnt, wcnt; -+#endif -+}; -+ -+#ifdef CONFIG_AUFS_DEBUG -+#define AuDbgCntInit(rw) do { \ -+ atomic_set(&(rw)->rcnt, 0); \ -+ atomic_set(&(rw)->wcnt, 0); \ -+ smp_mb(); /* atomic set */ \ -+} while (0) -+ -+#define AuDbgRcntInc(rw) atomic_inc(&(rw)->rcnt) -+#define AuDbgRcntDec(rw) WARN_ON(atomic_dec_return(&(rw)->rcnt) < 0) -+#define AuDbgWcntInc(rw) atomic_inc(&(rw)->wcnt) -+#define AuDbgWcntDec(rw) WARN_ON(atomic_dec_return(&(rw)->wcnt) < 0) -+#else -+#define AuDbgCntInit(rw) do {} while (0) -+#define AuDbgRcntInc(rw) do {} while (0) -+#define AuDbgRcntDec(rw) do {} while (0) -+#define AuDbgWcntInc(rw) do {} while (0) -+#define AuDbgWcntDec(rw) do {} while (0) -+#endif /* CONFIG_AUFS_DEBUG */ -+ -+/* to debug easier, do not make them inlined functions */ -+#define AuRwMustNoWaiters(rw) AuDebugOn(!list_empty(&(rw)->rwsem.wait_list)) -+/* rwsem_is_locked() is unusable */ -+#define AuRwMustReadLock(rw) AuDebugOn(atomic_read(&(rw)->rcnt) <= 0) -+#define AuRwMustWriteLock(rw) AuDebugOn(atomic_read(&(rw)->wcnt) <= 0) -+#define AuRwMustAnyLock(rw) AuDebugOn(atomic_read(&(rw)->rcnt) <= 0 \ -+ && atomic_read(&(rw)->wcnt) <= 0) -+#define AuRwDestroy(rw) AuDebugOn(atomic_read(&(rw)->rcnt) \ -+ || atomic_read(&(rw)->wcnt)) -+ -+#define au_rw_class(rw, key) lockdep_set_class(&(rw)->rwsem, key) -+ -+static inline void au_rw_init(struct au_rwsem *rw) -+{ -+ AuDbgCntInit(rw); -+ init_rwsem(&rw->rwsem); -+} -+ -+static inline void au_rw_init_wlock(struct au_rwsem *rw) -+{ -+ au_rw_init(rw); -+ down_write(&rw->rwsem); -+ AuDbgWcntInc(rw); -+} -+ -+static inline void au_rw_init_wlock_nested(struct au_rwsem *rw, -+ unsigned int lsc) -+{ -+ au_rw_init(rw); -+ down_write_nested(&rw->rwsem, lsc); -+ AuDbgWcntInc(rw); -+} -+ -+static inline void au_rw_read_lock(struct au_rwsem *rw) -+{ -+ down_read(&rw->rwsem); -+ AuDbgRcntInc(rw); -+} -+ -+static inline void au_rw_read_lock_nested(struct au_rwsem *rw, unsigned int lsc) -+{ -+ down_read_nested(&rw->rwsem, lsc); -+ AuDbgRcntInc(rw); -+} -+ -+static inline void au_rw_read_unlock(struct au_rwsem *rw) -+{ -+ AuRwMustReadLock(rw); -+ AuDbgRcntDec(rw); -+ up_read(&rw->rwsem); -+} -+ -+static inline void au_rw_dgrade_lock(struct au_rwsem *rw) -+{ -+ AuRwMustWriteLock(rw); -+ AuDbgRcntInc(rw); -+ AuDbgWcntDec(rw); -+ downgrade_write(&rw->rwsem); -+} -+ -+static inline void au_rw_write_lock(struct au_rwsem *rw) -+{ -+ down_write(&rw->rwsem); -+ AuDbgWcntInc(rw); -+} -+ -+static inline void au_rw_write_lock_nested(struct au_rwsem *rw, -+ unsigned int lsc) -+{ -+ down_write_nested(&rw->rwsem, lsc); -+ AuDbgWcntInc(rw); -+} -+ -+static inline void au_rw_write_unlock(struct au_rwsem *rw) -+{ -+ AuRwMustWriteLock(rw); -+ AuDbgWcntDec(rw); -+ up_write(&rw->rwsem); -+} -+ -+/* why is not _nested version defined */ -+static inline int au_rw_read_trylock(struct au_rwsem *rw) -+{ -+ int ret = down_read_trylock(&rw->rwsem); -+ if (ret) -+ AuDbgRcntInc(rw); -+ return ret; -+} -+ -+static inline int au_rw_write_trylock(struct au_rwsem *rw) -+{ -+ int ret = down_write_trylock(&rw->rwsem); -+ if (ret) -+ AuDbgWcntInc(rw); -+ return ret; -+} -+ -+#undef AuDbgCntInit -+#undef AuDbgRcntInc -+#undef AuDbgRcntDec -+#undef AuDbgWcntInc -+#undef AuDbgWcntDec -+ -+#define AuSimpleLockRwsemFuncs(prefix, param, rwsem) \ -+static inline void prefix##_read_lock(param) \ -+{ au_rw_read_lock(rwsem); } \ -+static inline void prefix##_write_lock(param) \ -+{ au_rw_write_lock(rwsem); } \ -+static inline int prefix##_read_trylock(param) \ -+{ return au_rw_read_trylock(rwsem); } \ -+static inline int prefix##_write_trylock(param) \ -+{ return au_rw_write_trylock(rwsem); } -+/* why is not _nested version defined */ -+/* static inline void prefix##_read_trylock_nested(param, lsc) -+{ au_rw_read_trylock_nested(rwsem, lsc)); } -+static inline void prefix##_write_trylock_nestd(param, lsc) -+{ au_rw_write_trylock_nested(rwsem, lsc); } */ -+ -+#define AuSimpleUnlockRwsemFuncs(prefix, param, rwsem) \ -+static inline void prefix##_read_unlock(param) \ -+{ au_rw_read_unlock(rwsem); } \ -+static inline void prefix##_write_unlock(param) \ -+{ au_rw_write_unlock(rwsem); } \ -+static inline void prefix##_downgrade_lock(param) \ -+{ au_rw_dgrade_lock(rwsem); } -+ -+#define AuSimpleRwsemFuncs(prefix, param, rwsem) \ -+ AuSimpleLockRwsemFuncs(prefix, param, rwsem) \ -+ AuSimpleUnlockRwsemFuncs(prefix, param, rwsem) -+ -+#endif /* __KERNEL__ */ -+#endif /* __AUFS_RWSEM_H__ */ -diff -Nur linux-2.6.36.orig/fs/aufs/sbinfo.c linux-2.6.36/fs/aufs/sbinfo.c ---- linux-2.6.36.orig/fs/aufs/sbinfo.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/sbinfo.c 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,345 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * superblock private data -+ */ -+ -+#include -+#include "aufs.h" -+ -+/* -+ * they are necessary regardless sysfs is disabled. -+ */ -+void au_si_free(struct kobject *kobj) -+{ -+ struct au_sbinfo *sbinfo; -+ char *locked __maybe_unused; /* debug only */ -+ -+ sbinfo = container_of(kobj, struct au_sbinfo, si_kobj); -+ AuDebugOn(!list_empty(&sbinfo->si_plink.head)); -+ AuDebugOn(atomic_read(&sbinfo->si_nowait.nw_len)); -+ -+ au_rw_write_lock(&sbinfo->si_rwsem); -+ au_br_free(sbinfo); -+ au_rw_write_unlock(&sbinfo->si_rwsem); -+ -+ AuDebugOn(radix_tree_gang_lookup -+ (&sbinfo->au_si_pid.tree, (void **)&locked, -+ /*first_index*/PID_MAX_DEFAULT - 1, -+ /*max_items*/sizeof(locked)/sizeof(*locked))); -+ -+ kfree(sbinfo->si_branch); -+ kfree(sbinfo->au_si_pid.bitmap); -+ mutex_destroy(&sbinfo->si_xib_mtx); -+ AuRwDestroy(&sbinfo->si_rwsem); -+ -+ kfree(sbinfo); -+} -+ -+int au_si_alloc(struct super_block *sb) -+{ -+ int err; -+ struct au_sbinfo *sbinfo; -+ static struct lock_class_key aufs_si; -+ -+ err = -ENOMEM; -+ sbinfo = kzalloc(sizeof(*sbinfo), GFP_NOFS); -+ if (unlikely(!sbinfo)) -+ goto out; -+ -+ BUILD_BUG_ON(sizeof(unsigned long) != -+ sizeof(*sbinfo->au_si_pid.bitmap)); -+ sbinfo->au_si_pid.bitmap = kcalloc(BITS_TO_LONGS(PID_MAX_DEFAULT), -+ sizeof(*sbinfo->au_si_pid.bitmap), -+ GFP_NOFS); -+ if (unlikely(!sbinfo->au_si_pid.bitmap)) -+ goto out_sbinfo; -+ -+ /* will be reallocated separately */ -+ sbinfo->si_branch = kzalloc(sizeof(*sbinfo->si_branch), GFP_NOFS); -+ if (unlikely(!sbinfo->si_branch)) -+ goto out_pidmap; -+ -+ err = sysaufs_si_init(sbinfo); -+ if (unlikely(err)) -+ goto out_br; -+ -+ au_nwt_init(&sbinfo->si_nowait); -+ au_rw_init_wlock(&sbinfo->si_rwsem); -+ au_rw_class(&sbinfo->si_rwsem, &aufs_si); -+ spin_lock_init(&sbinfo->au_si_pid.tree_lock); -+ INIT_RADIX_TREE(&sbinfo->au_si_pid.tree, GFP_ATOMIC | __GFP_NOFAIL); -+ -+ atomic_long_set(&sbinfo->si_ninodes, 0); -+ atomic_long_set(&sbinfo->si_nfiles, 0); -+ -+ sbinfo->si_bend = -1; -+ -+ sbinfo->si_wbr_copyup = AuWbrCopyup_Def; -+ sbinfo->si_wbr_create = AuWbrCreate_Def; -+ sbinfo->si_wbr_copyup_ops = au_wbr_copyup_ops + sbinfo->si_wbr_copyup; -+ sbinfo->si_wbr_create_ops = au_wbr_create_ops + sbinfo->si_wbr_create; -+ -+ sbinfo->si_mntflags = au_opts_plink(AuOpt_Def); -+ -+ mutex_init(&sbinfo->si_xib_mtx); -+ sbinfo->si_xino_brid = -1; -+ /* leave si_xib_last_pindex and si_xib_next_bit */ -+ -+ sbinfo->si_rdcache = msecs_to_jiffies(AUFS_RDCACHE_DEF * MSEC_PER_SEC); -+ sbinfo->si_rdblk = AUFS_RDBLK_DEF; -+ sbinfo->si_rdhash = AUFS_RDHASH_DEF; -+ sbinfo->si_dirwh = AUFS_DIRWH_DEF; -+ -+ au_spl_init(&sbinfo->si_plink); -+ init_waitqueue_head(&sbinfo->si_plink_wq); -+ spin_lock_init(&sbinfo->si_plink_maint_lock); -+ -+ /* leave other members for sysaufs and si_mnt. */ -+ sbinfo->si_sb = sb; -+ sb->s_fs_info = sbinfo; -+ si_pid_set(sb); -+ au_debug_sbinfo_init(sbinfo); -+ return 0; /* success */ -+ -+out_br: -+ kfree(sbinfo->si_branch); -+out_pidmap: -+ kfree(sbinfo->au_si_pid.bitmap); -+out_sbinfo: -+ kfree(sbinfo); -+out: -+ return err; -+} -+ -+int au_sbr_realloc(struct au_sbinfo *sbinfo, int nbr) -+{ -+ int err, sz; -+ struct au_branch **brp; -+ -+ AuRwMustWriteLock(&sbinfo->si_rwsem); -+ -+ err = -ENOMEM; -+ sz = sizeof(*brp) * (sbinfo->si_bend + 1); -+ if (unlikely(!sz)) -+ sz = sizeof(*brp); -+ brp = au_kzrealloc(sbinfo->si_branch, sz, sizeof(*brp) * nbr, GFP_NOFS); -+ if (brp) { -+ sbinfo->si_branch = brp; -+ err = 0; -+ } -+ -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+unsigned int au_sigen_inc(struct super_block *sb) -+{ -+ unsigned int gen; -+ -+ SiMustWriteLock(sb); -+ -+ gen = ++au_sbi(sb)->si_generation; -+ au_update_digen(sb->s_root); -+ au_update_iigen(sb->s_root->d_inode); -+ sb->s_root->d_inode->i_version++; -+ return gen; -+} -+ -+aufs_bindex_t au_new_br_id(struct super_block *sb) -+{ -+ aufs_bindex_t br_id; -+ int i; -+ struct au_sbinfo *sbinfo; -+ -+ SiMustWriteLock(sb); -+ -+ sbinfo = au_sbi(sb); -+ for (i = 0; i <= AUFS_BRANCH_MAX; i++) { -+ br_id = ++sbinfo->si_last_br_id; -+ AuDebugOn(br_id < 0); -+ if (br_id && au_br_index(sb, br_id) < 0) -+ return br_id; -+ } -+ -+ return -1; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* it is ok that new 'nwt' tasks are appended while we are sleeping */ -+int si_read_lock(struct super_block *sb, int flags) -+{ -+ int err; -+ -+ err = 0; -+ if (au_ftest_lock(flags, FLUSH)) -+ au_nwt_flush(&au_sbi(sb)->si_nowait); -+ -+ si_noflush_read_lock(sb); -+ err = au_plink_maint(sb, flags); -+ if (unlikely(err)) -+ si_read_unlock(sb); -+ -+ return err; -+} -+ -+int si_write_lock(struct super_block *sb, int flags) -+{ -+ int err; -+ -+ if (au_ftest_lock(flags, FLUSH)) -+ au_nwt_flush(&au_sbi(sb)->si_nowait); -+ -+ si_noflush_write_lock(sb); -+ err = au_plink_maint(sb, flags); -+ if (unlikely(err)) -+ si_write_unlock(sb); -+ -+ return err; -+} -+ -+/* dentry and super_block lock. call at entry point */ -+int aufs_read_lock(struct dentry *dentry, int flags) -+{ -+ int err; -+ struct super_block *sb; -+ -+ sb = dentry->d_sb; -+ err = si_read_lock(sb, flags); -+ if (unlikely(err)) -+ goto out; -+ -+ if (au_ftest_lock(flags, DW)) -+ di_write_lock_child(dentry); -+ else -+ di_read_lock_child(dentry, flags); -+ -+ if (au_ftest_lock(flags, GEN)) { -+ err = au_digen_test(dentry, au_sigen(sb)); -+ AuDebugOn(!err && au_dbrange_test(dentry)); -+ if (unlikely(err)) -+ aufs_read_unlock(dentry, flags); -+ } -+ -+out: -+ return err; -+} -+ -+void aufs_read_unlock(struct dentry *dentry, int flags) -+{ -+ if (au_ftest_lock(flags, DW)) -+ di_write_unlock(dentry); -+ else -+ di_read_unlock(dentry, flags); -+ si_read_unlock(dentry->d_sb); -+} -+ -+void aufs_write_lock(struct dentry *dentry) -+{ -+ si_write_lock(dentry->d_sb, AuLock_FLUSH | AuLock_NOPLMW); -+ di_write_lock_child(dentry); -+} -+ -+void aufs_write_unlock(struct dentry *dentry) -+{ -+ di_write_unlock(dentry); -+ si_write_unlock(dentry->d_sb); -+} -+ -+int aufs_read_and_write_lock2(struct dentry *d1, struct dentry *d2, int flags) -+{ -+ int err; -+ unsigned int sigen; -+ struct super_block *sb; -+ -+ sb = d1->d_sb; -+ err = si_read_lock(sb, flags); -+ if (unlikely(err)) -+ goto out; -+ -+ di_write_lock2_child(d1, d2, au_ftest_lock(flags, DIR)); -+ -+ if (au_ftest_lock(flags, GEN)) { -+ sigen = au_sigen(sb); -+ err = au_digen_test(d1, sigen); -+ AuDebugOn(!err && au_dbrange_test(d1)); -+ if (!err) { -+ err = au_digen_test(d2, sigen); -+ AuDebugOn(!err && au_dbrange_test(d2)); -+ } -+ if (unlikely(err)) -+ aufs_read_and_write_unlock2(d1, d2); -+ } -+ -+out: -+ return err; -+} -+ -+void aufs_read_and_write_unlock2(struct dentry *d1, struct dentry *d2) -+{ -+ di_write_unlock2(d1, d2); -+ si_read_unlock(d1->d_sb); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+int si_pid_test_slow(struct super_block *sb) -+{ -+ void *p; -+ -+ rcu_read_lock(); -+ p = radix_tree_lookup(&au_sbi(sb)->au_si_pid.tree, current->pid); -+ rcu_read_unlock(); -+ -+ return (long)p; -+} -+ -+void si_pid_set_slow(struct super_block *sb) -+{ -+ int err; -+ struct au_sbinfo *sbinfo; -+ -+ AuDebugOn(si_pid_test_slow(sb)); -+ -+ sbinfo = au_sbi(sb); -+ err = radix_tree_preload(GFP_NOFS | __GFP_NOFAIL); -+ AuDebugOn(err); -+ spin_lock(&sbinfo->au_si_pid.tree_lock); -+ err = radix_tree_insert(&sbinfo->au_si_pid.tree, current->pid, -+ (void *)1); -+ spin_unlock(&sbinfo->au_si_pid.tree_lock); -+ AuDebugOn(err); -+ radix_tree_preload_end(); -+} -+ -+void si_pid_clr_slow(struct super_block *sb) -+{ -+ void *p; -+ struct au_sbinfo *sbinfo; -+ -+ AuDebugOn(!si_pid_test_slow(sb)); -+ -+ sbinfo = au_sbi(sb); -+ spin_lock(&sbinfo->au_si_pid.tree_lock); -+ p = radix_tree_delete(&sbinfo->au_si_pid.tree, current->pid); -+ spin_unlock(&sbinfo->au_si_pid.tree_lock); -+ AuDebugOn(1 != (long)p); -+} -diff -Nur linux-2.6.36.orig/fs/aufs/spl.h linux-2.6.36/fs/aufs/spl.h ---- linux-2.6.36.orig/fs/aufs/spl.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/spl.h 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,66 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * simple list protected by a spinlock -+ */ -+ -+#ifndef __AUFS_SPL_H__ -+#define __AUFS_SPL_H__ -+ -+#ifdef __KERNEL__ -+ -+#include -+#include -+#include -+ -+struct au_splhead { -+ spinlock_t spin; -+ struct list_head head; -+}; -+ -+static inline void au_spl_init(struct au_splhead *spl) -+{ -+ spin_lock_init(&spl->spin); -+ INIT_LIST_HEAD(&spl->head); -+} -+ -+static inline void au_spl_add(struct list_head *list, struct au_splhead *spl) -+{ -+ spin_lock(&spl->spin); -+ list_add(list, &spl->head); -+ spin_unlock(&spl->spin); -+} -+ -+static inline void au_spl_del(struct list_head *list, struct au_splhead *spl) -+{ -+ spin_lock(&spl->spin); -+ list_del(list); -+ spin_unlock(&spl->spin); -+} -+ -+static inline void au_spl_del_rcu(struct list_head *list, -+ struct au_splhead *spl) -+{ -+ spin_lock(&spl->spin); -+ list_del_rcu(list); -+ spin_unlock(&spl->spin); -+} -+ -+#endif /* __KERNEL__ */ -+#endif /* __AUFS_SPL_H__ */ -diff -Nur linux-2.6.36.orig/fs/aufs/super.c linux-2.6.36/fs/aufs/super.c ---- linux-2.6.36.orig/fs/aufs/super.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/super.c 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,913 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * mount and super_block operations -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "aufs.h" -+ -+/* -+ * super_operations -+ */ -+static struct inode *aufs_alloc_inode(struct super_block *sb __maybe_unused) -+{ -+ struct au_icntnr *c; -+ -+ c = au_cache_alloc_icntnr(); -+ if (c) { -+ au_icntnr_init(c); -+ c->vfs_inode.i_version = 1; /* sigen(sb); */ -+ c->iinfo.ii_hinode = NULL; -+ return &c->vfs_inode; -+ } -+ return NULL; -+} -+ -+static void aufs_destroy_inode(struct inode *inode) -+{ -+ au_iinfo_fin(inode); -+ au_cache_free_icntnr(container_of(inode, struct au_icntnr, vfs_inode)); -+} -+ -+struct inode *au_iget_locked(struct super_block *sb, ino_t ino) -+{ -+ struct inode *inode; -+ int err; -+ -+ inode = iget_locked(sb, ino); -+ if (unlikely(!inode)) { -+ inode = ERR_PTR(-ENOMEM); -+ goto out; -+ } -+ if (!(inode->i_state & I_NEW)) -+ goto out; -+ -+ err = au_xigen_new(inode); -+ if (!err) -+ err = au_iinfo_init(inode); -+ if (!err) -+ inode->i_version++; -+ else { -+ iget_failed(inode); -+ inode = ERR_PTR(err); -+ } -+ -+out: -+ /* never return NULL */ -+ AuDebugOn(!inode); -+ AuTraceErrPtr(inode); -+ return inode; -+} -+ -+/* lock free root dinfo */ -+static int au_show_brs(struct seq_file *seq, struct super_block *sb) -+{ -+ int err; -+ aufs_bindex_t bindex, bend; -+ struct path path; -+ struct au_hdentry *hdp; -+ struct au_branch *br; -+ -+ err = 0; -+ bend = au_sbend(sb); -+ hdp = au_di(sb->s_root)->di_hdentry; -+ for (bindex = 0; !err && bindex <= bend; bindex++) { -+ br = au_sbr(sb, bindex); -+ path.mnt = br->br_mnt; -+ path.dentry = hdp[bindex].hd_dentry; -+ err = au_seq_path(seq, &path); -+ if (err > 0) -+ err = seq_printf(seq, "=%s", -+ au_optstr_br_perm(br->br_perm)); -+ if (!err && bindex != bend) -+ err = seq_putc(seq, ':'); -+ } -+ -+ return err; -+} -+ -+static void au_show_wbr_create(struct seq_file *m, int v, -+ struct au_sbinfo *sbinfo) -+{ -+ const char *pat; -+ -+ AuRwMustAnyLock(&sbinfo->si_rwsem); -+ -+ seq_printf(m, ",create="); -+ pat = au_optstr_wbr_create(v); -+ switch (v) { -+ case AuWbrCreate_TDP: -+ case AuWbrCreate_RR: -+ case AuWbrCreate_MFS: -+ case AuWbrCreate_PMFS: -+ seq_printf(m, pat); -+ break; -+ case AuWbrCreate_MFSV: -+ seq_printf(m, /*pat*/"mfs:%lu", -+ jiffies_to_msecs(sbinfo->si_wbr_mfs.mfs_expire) -+ / MSEC_PER_SEC); -+ break; -+ case AuWbrCreate_PMFSV: -+ seq_printf(m, /*pat*/"pmfs:%lu", -+ jiffies_to_msecs(sbinfo->si_wbr_mfs.mfs_expire) -+ / MSEC_PER_SEC); -+ break; -+ case AuWbrCreate_MFSRR: -+ seq_printf(m, /*pat*/"mfsrr:%llu", -+ sbinfo->si_wbr_mfs.mfsrr_watermark); -+ break; -+ case AuWbrCreate_MFSRRV: -+ seq_printf(m, /*pat*/"mfsrr:%llu:%lu", -+ sbinfo->si_wbr_mfs.mfsrr_watermark, -+ jiffies_to_msecs(sbinfo->si_wbr_mfs.mfs_expire) -+ / MSEC_PER_SEC); -+ break; -+ } -+} -+ -+static int au_show_xino(struct seq_file *seq, struct vfsmount *mnt) -+{ -+#ifdef CONFIG_SYSFS -+ return 0; -+#else -+ int err; -+ const int len = sizeof(AUFS_XINO_FNAME) - 1; -+ aufs_bindex_t bindex, brid; -+ struct super_block *sb; -+ struct qstr *name; -+ struct file *f; -+ struct dentry *d, *h_root; -+ struct au_hdentry *hdp; -+ -+ AuRwMustAnyLock(&sbinfo->si_rwsem); -+ -+ err = 0; -+ sb = mnt->mnt_sb; -+ f = au_sbi(sb)->si_xib; -+ if (!f) -+ goto out; -+ -+ /* stop printing the default xino path on the first writable branch */ -+ h_root = NULL; -+ brid = au_xino_brid(sb); -+ if (brid >= 0) { -+ bindex = au_br_index(sb, brid); -+ hdp = au_di(sb->s_root)->di_hdentry; -+ h_root = hdp[0 + bindex].hd_dentry; -+ } -+ d = f->f_dentry; -+ name = &d->d_name; -+ /* safe ->d_parent because the file is unlinked */ -+ if (d->d_parent == h_root -+ && name->len == len -+ && !memcmp(name->name, AUFS_XINO_FNAME, len)) -+ goto out; -+ -+ seq_puts(seq, ",xino="); -+ err = au_xino_path(seq, f); -+ -+out: -+ return err; -+#endif -+} -+ -+/* seq_file will re-call me in case of too long string */ -+static int aufs_show_options(struct seq_file *m, struct vfsmount *mnt) -+{ -+ int err; -+ unsigned int mnt_flags, v; -+ struct super_block *sb; -+ struct au_sbinfo *sbinfo; -+ -+#define AuBool(name, str) do { \ -+ v = au_opt_test(mnt_flags, name); \ -+ if (v != au_opt_test(AuOpt_Def, name)) \ -+ seq_printf(m, ",%s" #str, v ? "" : "no"); \ -+} while (0) -+ -+#define AuStr(name, str) do { \ -+ v = mnt_flags & AuOptMask_##name; \ -+ if (v != (AuOpt_Def & AuOptMask_##name)) \ -+ seq_printf(m, "," #str "=%s", au_optstr_##str(v)); \ -+} while (0) -+ -+#define AuUInt(name, str, val) do { \ -+ if (val != AUFS_##name##_DEF) \ -+ seq_printf(m, "," #str "=%u", val); \ -+} while (0) -+ -+ /* lock free root dinfo */ -+ sb = mnt->mnt_sb; -+ si_noflush_read_lock(sb); -+ sbinfo = au_sbi(sb); -+ seq_printf(m, ",si=%lx", sysaufs_si_id(sbinfo)); -+ -+ mnt_flags = au_mntflags(sb); -+ if (au_opt_test(mnt_flags, XINO)) { -+ err = au_show_xino(m, mnt); -+ if (unlikely(err)) -+ goto out; -+ } else -+ seq_puts(m, ",noxino"); -+ -+ AuBool(TRUNC_XINO, trunc_xino); -+ AuStr(UDBA, udba); -+ AuBool(SHWH, shwh); -+ AuBool(PLINK, plink); -+ AuBool(DIO, dio); -+ /* AuBool(DIRPERM1, dirperm1); */ -+ /* AuBool(REFROF, refrof); */ -+ -+ v = sbinfo->si_wbr_create; -+ if (v != AuWbrCreate_Def) -+ au_show_wbr_create(m, v, sbinfo); -+ -+ v = sbinfo->si_wbr_copyup; -+ if (v != AuWbrCopyup_Def) -+ seq_printf(m, ",cpup=%s", au_optstr_wbr_copyup(v)); -+ -+ v = au_opt_test(mnt_flags, ALWAYS_DIROPQ); -+ if (v != au_opt_test(AuOpt_Def, ALWAYS_DIROPQ)) -+ seq_printf(m, ",diropq=%c", v ? 'a' : 'w'); -+ -+ AuUInt(DIRWH, dirwh, sbinfo->si_dirwh); -+ -+ v = jiffies_to_msecs(sbinfo->si_rdcache) / MSEC_PER_SEC; -+ AuUInt(RDCACHE, rdcache, v); -+ -+ AuUInt(RDBLK, rdblk, sbinfo->si_rdblk); -+ AuUInt(RDHASH, rdhash, sbinfo->si_rdhash); -+ -+ AuBool(SUM, sum); -+ /* AuBool(SUM_W, wsum); */ -+ AuBool(WARN_PERM, warn_perm); -+ AuBool(VERBOSE, verbose); -+ -+out: -+ /* be sure to print "br:" last */ -+ if (!sysaufs_brs) { -+ seq_puts(m, ",br:"); -+ au_show_brs(m, sb); -+ } -+ si_read_unlock(sb); -+ return 0; -+ -+#undef AuBool -+#undef AuStr -+#undef AuUInt -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* sum mode which returns the summation for statfs(2) */ -+ -+static u64 au_add_till_max(u64 a, u64 b) -+{ -+ u64 old; -+ -+ old = a; -+ a += b; -+ if (old < a) -+ return a; -+ return ULLONG_MAX; -+} -+ -+static int au_statfs_sum(struct super_block *sb, struct kstatfs *buf) -+{ -+ int err; -+ u64 blocks, bfree, bavail, files, ffree; -+ aufs_bindex_t bend, bindex, i; -+ unsigned char shared; -+ struct path h_path; -+ struct super_block *h_sb; -+ -+ blocks = 0; -+ bfree = 0; -+ bavail = 0; -+ files = 0; -+ ffree = 0; -+ -+ err = 0; -+ bend = au_sbend(sb); -+ for (bindex = bend; bindex >= 0; bindex--) { -+ h_path.mnt = au_sbr_mnt(sb, bindex); -+ h_sb = h_path.mnt->mnt_sb; -+ shared = 0; -+ for (i = bindex + 1; !shared && i <= bend; i++) -+ shared = (au_sbr_sb(sb, i) == h_sb); -+ if (shared) -+ continue; -+ -+ /* sb->s_root for NFS is unreliable */ -+ h_path.dentry = h_path.mnt->mnt_root; -+ err = vfs_statfs(&h_path, buf); -+ if (unlikely(err)) -+ goto out; -+ -+ blocks = au_add_till_max(blocks, buf->f_blocks); -+ bfree = au_add_till_max(bfree, buf->f_bfree); -+ bavail = au_add_till_max(bavail, buf->f_bavail); -+ files = au_add_till_max(files, buf->f_files); -+ ffree = au_add_till_max(ffree, buf->f_ffree); -+ } -+ -+ buf->f_blocks = blocks; -+ buf->f_bfree = bfree; -+ buf->f_bavail = bavail; -+ buf->f_files = files; -+ buf->f_ffree = ffree; -+ -+out: -+ return err; -+} -+ -+static int aufs_statfs(struct dentry *dentry, struct kstatfs *buf) -+{ -+ int err; -+ struct path h_path; -+ struct super_block *sb; -+ -+ /* lock free root dinfo */ -+ sb = dentry->d_sb; -+ si_noflush_read_lock(sb); -+ if (!au_opt_test(au_mntflags(sb), SUM)) { -+ /* sb->s_root for NFS is unreliable */ -+ h_path.mnt = au_sbr_mnt(sb, 0); -+ h_path.dentry = h_path.mnt->mnt_root; -+ err = vfs_statfs(&h_path, buf); -+ } else -+ err = au_statfs_sum(sb, buf); -+ si_read_unlock(sb); -+ -+ if (!err) { -+ buf->f_type = AUFS_SUPER_MAGIC; -+ buf->f_namelen = AUFS_MAX_NAMELEN; -+ memset(&buf->f_fsid, 0, sizeof(buf->f_fsid)); -+ } -+ /* buf->f_bsize = buf->f_blocks = buf->f_bfree = buf->f_bavail = -1; */ -+ -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* final actions when unmounting a file system */ -+static void aufs_put_super(struct super_block *sb) -+{ -+ struct au_sbinfo *sbinfo; -+ -+ sbinfo = au_sbi(sb); -+ if (!sbinfo) -+ return; -+ -+ dbgaufs_si_fin(sbinfo); -+ kobject_put(&sbinfo->si_kobj); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+void au_array_free(void *array) -+{ -+ if (array) { -+ if (!is_vmalloc_addr(array)) -+ kfree(array); -+ else -+ vfree(array); -+ } -+} -+ -+void *au_array_alloc(unsigned long long *hint, au_arraycb_t cb, void *arg) -+{ -+ void *array; -+ unsigned long long n; -+ -+ array = NULL; -+ n = 0; -+ if (!*hint) -+ goto out; -+ -+ if (*hint > ULLONG_MAX / sizeof(array)) { -+ array = ERR_PTR(-EMFILE); -+ pr_err("hint %llu\n", *hint); -+ goto out; -+ } -+ -+ array = kmalloc(sizeof(array) * *hint, GFP_NOFS); -+ if (unlikely(!array)) -+ array = vmalloc(sizeof(array) * *hint); -+ if (unlikely(!array)) { -+ array = ERR_PTR(-ENOMEM); -+ goto out; -+ } -+ -+ n = cb(array, *hint, arg); -+ AuDebugOn(n > *hint); -+ -+out: -+ *hint = n; -+ return array; -+} -+ -+static unsigned long long au_iarray_cb(void *a, -+ unsigned long long max __maybe_unused, -+ void *arg) -+{ -+ unsigned long long n; -+ struct inode **p, *inode; -+ struct list_head *head; -+ -+ n = 0; -+ p = a; -+ head = arg; -+ spin_lock(&inode_lock); -+ list_for_each_entry(inode, head, i_sb_list) { -+ if (!is_bad_inode(inode) -+ && au_ii(inode)->ii_bstart >= 0) { -+ au_igrab(inode); -+ *p++ = inode; -+ n++; -+ AuDebugOn(n > max); -+ } -+ } -+ spin_unlock(&inode_lock); -+ -+ return n; -+} -+ -+struct inode **au_iarray_alloc(struct super_block *sb, unsigned long long *max) -+{ -+ *max = atomic_long_read(&au_sbi(sb)->si_ninodes); -+ return au_array_alloc(max, au_iarray_cb, &sb->s_inodes); -+} -+ -+void au_iarray_free(struct inode **a, unsigned long long max) -+{ -+ unsigned long long ull; -+ -+ for (ull = 0; ull < max; ull++) -+ iput(a[ull]); -+ au_array_free(a); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * refresh dentry and inode at remount time. -+ */ -+/* todo: consolidate with simple_reval_dpath() and au_reval_for_attr() */ -+static int au_do_refresh(struct dentry *dentry, unsigned int dir_flags, -+ struct dentry *parent) -+{ -+ int err; -+ -+ di_write_lock_child(dentry); -+ di_read_lock_parent(parent, AuLock_IR); -+ err = au_refresh_dentry(dentry, parent); -+ if (!err && dir_flags) -+ au_hn_reset(dentry->d_inode, dir_flags); -+ di_read_unlock(parent, AuLock_IR); -+ di_write_unlock(dentry); -+ -+ return err; -+} -+ -+static int au_do_refresh_d(struct dentry *dentry, unsigned int sigen, -+ struct au_sbinfo *sbinfo, -+ const unsigned int dir_flags) -+{ -+ int err; -+ struct dentry *parent; -+ struct inode *inode; -+ -+ err = 0; -+ parent = dget_parent(dentry); -+ if (!au_digen_test(parent, sigen) && au_digen_test(dentry, sigen)) { -+ inode = dentry->d_inode; -+ if (inode) { -+ if (!S_ISDIR(inode->i_mode)) -+ err = au_do_refresh(dentry, /*dir_flags*/0, -+ parent); -+ else { -+ err = au_do_refresh(dentry, dir_flags, parent); -+ if (unlikely(err)) -+ au_fset_si(sbinfo, FAILED_REFRESH_DIR); -+ } -+ } else -+ err = au_do_refresh(dentry, /*dir_flags*/0, parent); -+ AuDbgDentry(dentry); -+ } -+ dput(parent); -+ -+ AuTraceErr(err); -+ return err; -+} -+ -+static int au_refresh_d(struct super_block *sb) -+{ -+ int err, i, j, ndentry, e; -+ unsigned int sigen; -+ struct au_dcsub_pages dpages; -+ struct au_dpage *dpage; -+ struct dentry **dentries, *d; -+ struct au_sbinfo *sbinfo; -+ struct dentry *root = sb->s_root; -+ const unsigned int dir_flags = au_hi_flags(root->d_inode, /*isdir*/1); -+ -+ err = au_dpages_init(&dpages, GFP_NOFS); -+ if (unlikely(err)) -+ goto out; -+ err = au_dcsub_pages(&dpages, root, NULL, NULL); -+ if (unlikely(err)) -+ goto out_dpages; -+ -+ sigen = au_sigen(sb); -+ sbinfo = au_sbi(sb); -+ for (i = 0; i < dpages.ndpage; i++) { -+ dpage = dpages.dpages + i; -+ dentries = dpage->dentries; -+ ndentry = dpage->ndentry; -+ for (j = 0; j < ndentry; j++) { -+ d = dentries[j]; -+ e = au_do_refresh_d(d, sigen, sbinfo, dir_flags); -+ if (unlikely(e && !err)) -+ err = e; -+ /* go on even err */ -+ } -+ } -+ -+out_dpages: -+ au_dpages_free(&dpages); -+out: -+ return err; -+} -+ -+static int au_refresh_i(struct super_block *sb) -+{ -+ int err, e; -+ unsigned int sigen; -+ unsigned long long max, ull; -+ struct inode *inode, **array; -+ -+ array = au_iarray_alloc(sb, &max); -+ err = PTR_ERR(array); -+ if (IS_ERR(array)) -+ goto out; -+ -+ err = 0; -+ sigen = au_sigen(sb); -+ for (ull = 0; ull < max; ull++) { -+ inode = array[ull]; -+ if (au_iigen(inode) != sigen) { -+ ii_write_lock_child(inode); -+ e = au_refresh_hinode_self(inode); -+ ii_write_unlock(inode); -+ if (unlikely(e)) { -+ pr_err("error %d, i%lu\n", e, inode->i_ino); -+ if (!err) -+ err = e; -+ /* go on even if err */ -+ } -+ } -+ } -+ -+ au_iarray_free(array, max); -+ -+out: -+ return err; -+} -+ -+static void au_remount_refresh(struct super_block *sb) -+{ -+ int err, e; -+ unsigned int udba; -+ aufs_bindex_t bindex, bend; -+ struct dentry *root; -+ struct inode *inode; -+ struct au_branch *br; -+ -+ au_sigen_inc(sb); -+ au_fclr_si(au_sbi(sb), FAILED_REFRESH_DIR); -+ -+ root = sb->s_root; -+ DiMustNoWaiters(root); -+ inode = root->d_inode; -+ IiMustNoWaiters(inode); -+ -+ udba = au_opt_udba(sb); -+ bend = au_sbend(sb); -+ for (bindex = 0; bindex <= bend; bindex++) { -+ br = au_sbr(sb, bindex); -+ err = au_hnotify_reset_br(udba, br, br->br_perm); -+ if (unlikely(err)) -+ AuIOErr("hnotify failed on br %d, %d, ignored\n", -+ bindex, err); -+ /* go on even if err */ -+ } -+ au_hn_reset(inode, au_hi_flags(inode, /*isdir*/1)); -+ -+ di_write_unlock(root); -+ err = au_refresh_d(sb); -+ e = au_refresh_i(sb); -+ if (unlikely(e && !err)) -+ err = e; -+ /* aufs_write_lock() calls ..._child() */ -+ di_write_lock_child(root); -+ -+ au_cpup_attr_all(inode, /*force*/1); -+ -+ if (unlikely(err)) -+ AuIOErr("refresh failed, ignored, %d\n", err); -+} -+ -+/* stop extra interpretation of errno in mount(8), and strange error messages */ -+static int cvt_err(int err) -+{ -+ AuTraceErr(err); -+ -+ switch (err) { -+ case -ENOENT: -+ case -ENOTDIR: -+ case -EEXIST: -+ case -EIO: -+ err = -EINVAL; -+ } -+ return err; -+} -+ -+static int aufs_remount_fs(struct super_block *sb, int *flags, char *data) -+{ -+ int err, do_dx; -+ unsigned int mntflags; -+ struct au_opts opts; -+ struct dentry *root; -+ struct inode *inode; -+ struct au_sbinfo *sbinfo; -+ -+ err = 0; -+ root = sb->s_root; -+ if (!data || !*data) { -+ err = si_write_lock(sb, AuLock_FLUSH | AuLock_NOPLM); -+ if (!err) { -+ di_write_lock_child(root); -+ err = au_opts_verify(sb, *flags, /*pending*/0); -+ aufs_write_unlock(root); -+ } -+ goto out; -+ } -+ -+ err = -ENOMEM; -+ memset(&opts, 0, sizeof(opts)); -+ opts.opt = (void *)__get_free_page(GFP_NOFS); -+ if (unlikely(!opts.opt)) -+ goto out; -+ opts.max_opt = PAGE_SIZE / sizeof(*opts.opt); -+ opts.flags = AuOpts_REMOUNT; -+ opts.sb_flags = *flags; -+ -+ /* parse it before aufs lock */ -+ err = au_opts_parse(sb, data, &opts); -+ if (unlikely(err)) -+ goto out_opts; -+ -+ sbinfo = au_sbi(sb); -+ inode = root->d_inode; -+ mutex_lock(&inode->i_mutex); -+ err = si_write_lock(sb, AuLock_FLUSH | AuLock_NOPLM); -+ if (unlikely(err)) -+ goto out_mtx; -+ di_write_lock_child(root); -+ -+ /* au_opts_remount() may return an error */ -+ err = au_opts_remount(sb, &opts); -+ au_opts_free(&opts); -+ -+ if (au_ftest_opts(opts.flags, REFRESH)) -+ au_remount_refresh(sb); -+ -+ if (au_ftest_opts(opts.flags, REFRESH_DYAOP)) { -+ mntflags = au_mntflags(sb); -+ do_dx = !!au_opt_test(mntflags, DIO); -+ au_dy_arefresh(do_dx); -+ } -+ -+ aufs_write_unlock(root); -+ -+out_mtx: -+ mutex_unlock(&inode->i_mutex); -+out_opts: -+ free_page((unsigned long)opts.opt); -+out: -+ err = cvt_err(err); -+ AuTraceErr(err); -+ return err; -+} -+ -+static const struct super_operations aufs_sop = { -+ .alloc_inode = aufs_alloc_inode, -+ .destroy_inode = aufs_destroy_inode, -+ /* always deleting, no clearing */ -+ .drop_inode = generic_delete_inode, -+ .show_options = aufs_show_options, -+ .statfs = aufs_statfs, -+ .put_super = aufs_put_super, -+ .remount_fs = aufs_remount_fs -+}; -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int alloc_root(struct super_block *sb) -+{ -+ int err; -+ struct inode *inode; -+ struct dentry *root; -+ -+ err = -ENOMEM; -+ inode = au_iget_locked(sb, AUFS_ROOT_INO); -+ err = PTR_ERR(inode); -+ if (IS_ERR(inode)) -+ goto out; -+ -+ inode->i_op = &aufs_dir_iop; -+ inode->i_fop = &aufs_dir_fop; -+ inode->i_mode = S_IFDIR; -+ inode->i_nlink = 2; -+ unlock_new_inode(inode); -+ -+ root = d_alloc_root(inode); -+ if (unlikely(!root)) -+ goto out_iput; -+ err = PTR_ERR(root); -+ if (IS_ERR(root)) -+ goto out_iput; -+ -+ err = au_di_init(root); -+ if (!err) { -+ sb->s_root = root; -+ return 0; /* success */ -+ } -+ dput(root); -+ goto out; /* do not iput */ -+ -+out_iput: -+ iget_failed(inode); -+out: -+ return err; -+ -+} -+ -+static int aufs_fill_super(struct super_block *sb, void *raw_data, -+ int silent __maybe_unused) -+{ -+ int err; -+ struct au_opts opts; -+ struct dentry *root; -+ struct inode *inode; -+ char *arg = raw_data; -+ -+ if (unlikely(!arg || !*arg)) { -+ err = -EINVAL; -+ pr_err("no arg\n"); -+ goto out; -+ } -+ -+ err = -ENOMEM; -+ memset(&opts, 0, sizeof(opts)); -+ opts.opt = (void *)__get_free_page(GFP_NOFS); -+ if (unlikely(!opts.opt)) -+ goto out; -+ opts.max_opt = PAGE_SIZE / sizeof(*opts.opt); -+ opts.sb_flags = sb->s_flags; -+ -+ err = au_si_alloc(sb); -+ if (unlikely(err)) -+ goto out_opts; -+ -+ /* all timestamps always follow the ones on the branch */ -+ sb->s_flags |= MS_NOATIME | MS_NODIRATIME; -+ sb->s_op = &aufs_sop; -+ sb->s_magic = AUFS_SUPER_MAGIC; -+ sb->s_maxbytes = 0; -+ au_export_init(sb); -+ -+ err = alloc_root(sb); -+ if (unlikely(err)) { -+ si_write_unlock(sb); -+ goto out_info; -+ } -+ root = sb->s_root; -+ inode = root->d_inode; -+ -+ /* -+ * actually we can parse options regardless aufs lock here. -+ * but at remount time, parsing must be done before aufs lock. -+ * so we follow the same rule. -+ */ -+ ii_write_lock_parent(inode); -+ aufs_write_unlock(root); -+ err = au_opts_parse(sb, arg, &opts); -+ if (unlikely(err)) -+ goto out_root; -+ -+ /* lock vfs_inode first, then aufs. */ -+ mutex_lock(&inode->i_mutex); -+ aufs_write_lock(root); -+ err = au_opts_mount(sb, &opts); -+ au_opts_free(&opts); -+ aufs_write_unlock(root); -+ mutex_unlock(&inode->i_mutex); -+ if (!err) -+ goto out_opts; /* success */ -+ -+out_root: -+ dput(root); -+ sb->s_root = NULL; -+out_info: -+ kobject_put(&au_sbi(sb)->si_kobj); -+ sb->s_fs_info = NULL; -+out_opts: -+ free_page((unsigned long)opts.opt); -+out: -+ AuTraceErr(err); -+ err = cvt_err(err); -+ AuTraceErr(err); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int aufs_get_sb(struct file_system_type *fs_type, int flags, -+ const char *dev_name __maybe_unused, void *raw_data, -+ struct vfsmount *mnt) -+{ -+ int err; -+ struct super_block *sb; -+ -+ /* all timestamps always follow the ones on the branch */ -+ /* mnt->mnt_flags |= MNT_NOATIME | MNT_NODIRATIME; */ -+ err = get_sb_nodev(fs_type, flags, raw_data, aufs_fill_super, mnt); -+ if (!err) { -+ sb = mnt->mnt_sb; -+ si_write_lock(sb, !AuLock_FLUSH); -+ sysaufs_brs_add(sb, 0); -+ si_write_unlock(sb); -+ au_sbilist_add(sb); -+ } -+ return err; -+} -+ -+static void aufs_kill_sb(struct super_block *sb) -+{ -+ struct au_sbinfo *sbinfo; -+ -+ sbinfo = au_sbi(sb); -+ if (sbinfo) { -+ au_sbilist_del(sb); -+ aufs_write_lock(sb->s_root); -+ if (sbinfo->si_wbr_create_ops->fin) -+ sbinfo->si_wbr_create_ops->fin(sb); -+ if (au_opt_test(sbinfo->si_mntflags, UDBA_HNOTIFY)) { -+ au_opt_set_udba(sbinfo->si_mntflags, UDBA_NONE); -+ au_remount_refresh(sb); -+ } -+ if (au_opt_test(sbinfo->si_mntflags, PLINK)) -+ au_plink_put(sb, /*verbose*/1); -+ au_xino_clr(sb); -+ aufs_write_unlock(sb->s_root); -+ au_nwt_flush(&sbinfo->si_nowait); -+ } -+ generic_shutdown_super(sb); -+} -+ -+struct file_system_type aufs_fs_type = { -+ .name = AUFS_FSTYPE, -+ .fs_flags = -+ FS_RENAME_DOES_D_MOVE /* a race between rename and others */ -+ | FS_REVAL_DOT, /* for NFS branch and udba */ -+ .get_sb = aufs_get_sb, -+ .kill_sb = aufs_kill_sb, -+ /* no need to __module_get() and module_put(). */ -+ .owner = THIS_MODULE, -+}; -diff -Nur linux-2.6.36.orig/fs/aufs/super.h linux-2.6.36/fs/aufs/super.h ---- linux-2.6.36.orig/fs/aufs/super.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/super.h 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,527 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * super_block operations -+ */ -+ -+#ifndef __AUFS_SUPER_H__ -+#define __AUFS_SUPER_H__ -+ -+#ifdef __KERNEL__ -+ -+#include -+#include -+#include "rwsem.h" -+#include "spl.h" -+#include "wkq.h" -+ -+typedef ssize_t (*au_readf_t)(struct file *, char __user *, size_t, loff_t *); -+typedef ssize_t (*au_writef_t)(struct file *, const char __user *, size_t, -+ loff_t *); -+ -+/* policies to select one among multiple writable branches */ -+struct au_wbr_copyup_operations { -+ int (*copyup)(struct dentry *dentry); -+}; -+ -+struct au_wbr_create_operations { -+ int (*create)(struct dentry *dentry, int isdir); -+ int (*init)(struct super_block *sb); -+ int (*fin)(struct super_block *sb); -+}; -+ -+struct au_wbr_mfs { -+ struct mutex mfs_lock; /* protect this structure */ -+ unsigned long mfs_jiffy; -+ unsigned long mfs_expire; -+ aufs_bindex_t mfs_bindex; -+ -+ unsigned long long mfsrr_bytes; -+ unsigned long long mfsrr_watermark; -+}; -+ -+struct au_branch; -+struct au_sbinfo { -+ /* nowait tasks in the system-wide workqueue */ -+ struct au_nowait_tasks si_nowait; -+ -+ /* -+ * tried sb->s_umount, but failed due to the dependecy between i_mutex. -+ * rwsem for au_sbinfo is necessary. -+ */ -+ struct au_rwsem si_rwsem; -+ -+ /* prevent recursive locking in deleting inode */ -+ struct { -+ unsigned long *bitmap; -+ spinlock_t tree_lock; -+ struct radix_tree_root tree; -+ } au_si_pid; -+ -+ /* -+ * dirty approach to protect sb->sb_inodes and ->s_files from remount. -+ */ -+ atomic_long_t si_ninodes, si_nfiles; -+ -+ /* branch management */ -+ unsigned int si_generation; -+ -+ /* see above flags */ -+ unsigned char au_si_status; -+ -+ aufs_bindex_t si_bend; -+ -+ /* dirty trick to keep br_id plus */ -+ unsigned int si_last_br_id : -+ sizeof(aufs_bindex_t) * BITS_PER_BYTE - 1; -+ struct au_branch **si_branch; -+ -+ /* policy to select a writable branch */ -+ unsigned char si_wbr_copyup; -+ unsigned char si_wbr_create; -+ struct au_wbr_copyup_operations *si_wbr_copyup_ops; -+ struct au_wbr_create_operations *si_wbr_create_ops; -+ -+ /* round robin */ -+ atomic_t si_wbr_rr_next; -+ -+ /* most free space */ -+ struct au_wbr_mfs si_wbr_mfs; -+ -+ /* mount flags */ -+ /* include/asm-ia64/siginfo.h defines a macro named si_flags */ -+ unsigned int si_mntflags; -+ -+ /* external inode number (bitmap and translation table) */ -+ au_readf_t si_xread; -+ au_writef_t si_xwrite; -+ struct file *si_xib; -+ struct mutex si_xib_mtx; /* protect xib members */ -+ unsigned long *si_xib_buf; -+ unsigned long si_xib_last_pindex; -+ int si_xib_next_bit; -+ aufs_bindex_t si_xino_brid; -+ /* reserved for future use */ -+ /* unsigned long long si_xib_limit; */ /* Max xib file size */ -+ -+#ifdef CONFIG_AUFS_EXPORT -+ /* i_generation */ -+ struct file *si_xigen; -+ atomic_t si_xigen_next; -+#endif -+ -+ /* vdir parameters */ -+ unsigned long si_rdcache; /* max cache time in jiffies */ -+ unsigned int si_rdblk; /* deblk size */ -+ unsigned int si_rdhash; /* hash size */ -+ -+ /* -+ * If the number of whiteouts are larger than si_dirwh, leave all of -+ * them after au_whtmp_ren to reduce the cost of rmdir(2). -+ * future fsck.aufs or kernel thread will remove them later. -+ * Otherwise, remove all whiteouts and the dir in rmdir(2). -+ */ -+ unsigned int si_dirwh; -+ -+ /* -+ * rename(2) a directory with all children. -+ */ -+ /* reserved for future use */ -+ /* int si_rendir; */ -+ -+ /* pseudo_link list */ -+ struct au_splhead si_plink; -+ wait_queue_head_t si_plink_wq; -+ spinlock_t si_plink_maint_lock; -+ pid_t si_plink_maint_pid; -+ -+ /* -+ * sysfs and lifetime management. -+ * this is not a small structure and it may be a waste of memory in case -+ * of sysfs is disabled, particulary when many aufs-es are mounted. -+ * but using sysfs is majority. -+ */ -+ struct kobject si_kobj; -+#ifdef CONFIG_DEBUG_FS -+ struct dentry *si_dbgaufs, *si_dbgaufs_xib; -+#ifdef CONFIG_AUFS_EXPORT -+ struct dentry *si_dbgaufs_xigen; -+#endif -+#endif -+ -+#ifdef CONFIG_AUFS_SBILIST -+ struct list_head si_list; -+#endif -+ -+ /* dirty, necessary for unmounting, sysfs and sysrq */ -+ struct super_block *si_sb; -+}; -+ -+/* sbinfo status flags */ -+/* -+ * set true when refresh_dirs() failed at remount time. -+ * then try refreshing dirs at access time again. -+ * if it is false, refreshing dirs at access time is unnecesary -+ */ -+#define AuSi_FAILED_REFRESH_DIR 1 -+static inline unsigned char au_do_ftest_si(struct au_sbinfo *sbi, -+ unsigned int flag) -+{ -+ AuRwMustAnyLock(&sbi->si_rwsem); -+ return sbi->au_si_status & flag; -+} -+#define au_ftest_si(sbinfo, name) au_do_ftest_si(sbinfo, AuSi_##name) -+#define au_fset_si(sbinfo, name) do { \ -+ AuRwMustWriteLock(&(sbinfo)->si_rwsem); \ -+ (sbinfo)->au_si_status |= AuSi_##name; \ -+} while (0) -+#define au_fclr_si(sbinfo, name) do { \ -+ AuRwMustWriteLock(&(sbinfo)->si_rwsem); \ -+ (sbinfo)->au_si_status &= ~AuSi_##name; \ -+} while (0) -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* policy to select one among writable branches */ -+#define AuWbrCopyup(sbinfo, ...) \ -+ ((sbinfo)->si_wbr_copyup_ops->copyup(__VA_ARGS__)) -+#define AuWbrCreate(sbinfo, ...) \ -+ ((sbinfo)->si_wbr_create_ops->create(__VA_ARGS__)) -+ -+/* flags for si_read_lock()/aufs_read_lock()/di_read_lock() */ -+#define AuLock_DW 1 /* write-lock dentry */ -+#define AuLock_IR (1 << 1) /* read-lock inode */ -+#define AuLock_IW (1 << 2) /* write-lock inode */ -+#define AuLock_FLUSH (1 << 3) /* wait for 'nowait' tasks */ -+#define AuLock_DIR (1 << 4) /* target is a dir */ -+#define AuLock_NOPLM (1 << 5) /* return err in plm mode */ -+#define AuLock_NOPLMW (1 << 6) /* wait for plm mode ends */ -+#define AuLock_GEN (1 << 7) /* test digen/iigen */ -+#define au_ftest_lock(flags, name) ((flags) & AuLock_##name) -+#define au_fset_lock(flags, name) \ -+ do { (flags) |= AuLock_##name; } while (0) -+#define au_fclr_lock(flags, name) \ -+ do { (flags) &= ~AuLock_##name; } while (0) -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* super.c */ -+extern struct file_system_type aufs_fs_type; -+struct inode *au_iget_locked(struct super_block *sb, ino_t ino); -+typedef unsigned long long (*au_arraycb_t)(void *array, unsigned long long max, -+ void *arg); -+void au_array_free(void *array); -+void *au_array_alloc(unsigned long long *hint, au_arraycb_t cb, void *arg); -+struct inode **au_iarray_alloc(struct super_block *sb, unsigned long long *max); -+void au_iarray_free(struct inode **a, unsigned long long max); -+ -+/* sbinfo.c */ -+void au_si_free(struct kobject *kobj); -+int au_si_alloc(struct super_block *sb); -+int au_sbr_realloc(struct au_sbinfo *sbinfo, int nbr); -+ -+unsigned int au_sigen_inc(struct super_block *sb); -+aufs_bindex_t au_new_br_id(struct super_block *sb); -+ -+int si_read_lock(struct super_block *sb, int flags); -+int si_write_lock(struct super_block *sb, int flags); -+int aufs_read_lock(struct dentry *dentry, int flags); -+void aufs_read_unlock(struct dentry *dentry, int flags); -+void aufs_write_lock(struct dentry *dentry); -+void aufs_write_unlock(struct dentry *dentry); -+int aufs_read_and_write_lock2(struct dentry *d1, struct dentry *d2, int flags); -+void aufs_read_and_write_unlock2(struct dentry *d1, struct dentry *d2); -+ -+int si_pid_test_slow(struct super_block *sb); -+void si_pid_set_slow(struct super_block *sb); -+void si_pid_clr_slow(struct super_block *sb); -+ -+/* wbr_policy.c */ -+extern struct au_wbr_copyup_operations au_wbr_copyup_ops[]; -+extern struct au_wbr_create_operations au_wbr_create_ops[]; -+int au_cpdown_dirs(struct dentry *dentry, aufs_bindex_t bdst); -+ -+/* ---------------------------------------------------------------------- */ -+ -+static inline struct au_sbinfo *au_sbi(struct super_block *sb) -+{ -+ return sb->s_fs_info; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+#ifdef CONFIG_AUFS_EXPORT -+void au_export_init(struct super_block *sb); -+ -+static inline int au_test_nfsd(void) -+{ -+ struct task_struct *tsk = current; -+ -+ return (tsk->flags & PF_KTHREAD) -+ && !strcmp(tsk->comm, "nfsd"); -+} -+ -+void au_xigen_inc(struct inode *inode); -+int au_xigen_new(struct inode *inode); -+int au_xigen_set(struct super_block *sb, struct file *base); -+void au_xigen_clr(struct super_block *sb); -+ -+static inline int au_busy_or_stale(void) -+{ -+ if (!au_test_nfsd()) -+ return -EBUSY; -+ return -ESTALE; -+} -+#else -+AuStubVoid(au_export_init, struct super_block *sb) -+AuStubInt0(au_test_nfsd, void) -+AuStubVoid(au_xigen_inc, struct inode *inode) -+AuStubInt0(au_xigen_new, struct inode *inode) -+AuStubInt0(au_xigen_set, struct super_block *sb, struct file *base) -+AuStubVoid(au_xigen_clr, struct super_block *sb) -+static inline int au_busy_or_stale(void) -+{ -+ return -EBUSY; -+} -+#endif /* CONFIG_AUFS_EXPORT */ -+ -+/* ---------------------------------------------------------------------- */ -+ -+#ifdef CONFIG_AUFS_SBILIST -+/* module.c */ -+extern struct au_splhead au_sbilist; -+ -+static inline void au_sbilist_init(void) -+{ -+ au_spl_init(&au_sbilist); -+} -+ -+static inline void au_sbilist_add(struct super_block *sb) -+{ -+ au_spl_add(&au_sbi(sb)->si_list, &au_sbilist); -+} -+ -+static inline void au_sbilist_del(struct super_block *sb) -+{ -+ au_spl_del(&au_sbi(sb)->si_list, &au_sbilist); -+} -+#else -+AuStubVoid(au_sbilist_init, void) -+AuStubVoid(au_sbilist_add, struct super_block*) -+AuStubVoid(au_sbilist_del, struct super_block*) -+#endif -+ -+/* ---------------------------------------------------------------------- */ -+ -+static inline void dbgaufs_si_null(struct au_sbinfo *sbinfo) -+{ -+ /* -+ * This function is a dynamic '__init' fucntion actually, -+ * so the tiny check for si_rwsem is unnecessary. -+ */ -+ /* AuRwMustWriteLock(&sbinfo->si_rwsem); */ -+#ifdef CONFIG_DEBUG_FS -+ sbinfo->si_dbgaufs = NULL; -+ sbinfo->si_dbgaufs_xib = NULL; -+#ifdef CONFIG_AUFS_EXPORT -+ sbinfo->si_dbgaufs_xigen = NULL; -+#endif -+#endif -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static inline pid_t si_pid_bit(void) -+{ -+ /* the origin of pid is 1, but the bitmap's is 0 */ -+ return current->pid - 1; -+} -+ -+static inline int si_pid_test(struct super_block *sb) -+{ -+ pid_t bit = si_pid_bit(); -+ if (bit < PID_MAX_DEFAULT) -+ return test_bit(bit, au_sbi(sb)->au_si_pid.bitmap); -+ else -+ return si_pid_test_slow(sb); -+} -+ -+static inline void si_pid_set(struct super_block *sb) -+{ -+ pid_t bit = si_pid_bit(); -+ if (bit < PID_MAX_DEFAULT) { -+ AuDebugOn(test_bit(bit, au_sbi(sb)->au_si_pid.bitmap)); -+ set_bit(bit, au_sbi(sb)->au_si_pid.bitmap); -+ /* smp_mb(); */ -+ } else -+ si_pid_set_slow(sb); -+} -+ -+static inline void si_pid_clr(struct super_block *sb) -+{ -+ pid_t bit = si_pid_bit(); -+ if (bit < PID_MAX_DEFAULT) { -+ AuDebugOn(!test_bit(bit, au_sbi(sb)->au_si_pid.bitmap)); -+ clear_bit(bit, au_sbi(sb)->au_si_pid.bitmap); -+ /* smp_mb(); */ -+ } else -+ si_pid_clr_slow(sb); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* lock superblock. mainly for entry point functions */ -+/* -+ * __si_read_lock, __si_write_lock, -+ * __si_read_unlock, __si_write_unlock, __si_downgrade_lock -+ */ -+AuSimpleRwsemFuncs(__si, struct super_block *sb, &au_sbi(sb)->si_rwsem); -+ -+#define SiMustNoWaiters(sb) AuRwMustNoWaiters(&au_sbi(sb)->si_rwsem) -+#define SiMustAnyLock(sb) AuRwMustAnyLock(&au_sbi(sb)->si_rwsem) -+#define SiMustWriteLock(sb) AuRwMustWriteLock(&au_sbi(sb)->si_rwsem) -+ -+static inline void si_noflush_read_lock(struct super_block *sb) -+{ -+ __si_read_lock(sb); -+ si_pid_set(sb); -+} -+ -+static inline int si_noflush_read_trylock(struct super_block *sb) -+{ -+ int locked = __si_read_trylock(sb); -+ if (locked) -+ si_pid_set(sb); -+ return locked; -+} -+ -+static inline void si_noflush_write_lock(struct super_block *sb) -+{ -+ __si_write_lock(sb); -+ si_pid_set(sb); -+} -+ -+static inline int si_noflush_write_trylock(struct super_block *sb) -+{ -+ int locked = __si_write_trylock(sb); -+ if (locked) -+ si_pid_set(sb); -+ return locked; -+} -+ -+#if 0 /* unused */ -+static inline int si_read_trylock(struct super_block *sb, int flags) -+{ -+ if (au_ftest_lock(flags, FLUSH)) -+ au_nwt_flush(&au_sbi(sb)->si_nowait); -+ return si_noflush_read_trylock(sb); -+} -+#endif -+ -+static inline void si_read_unlock(struct super_block *sb) -+{ -+ si_pid_clr(sb); -+ __si_read_unlock(sb); -+} -+ -+#if 0 /* unused */ -+static inline int si_write_trylock(struct super_block *sb, int flags) -+{ -+ if (au_ftest_lock(flags, FLUSH)) -+ au_nwt_flush(&au_sbi(sb)->si_nowait); -+ return si_noflush_write_trylock(sb); -+} -+#endif -+ -+static inline void si_write_unlock(struct super_block *sb) -+{ -+ si_pid_clr(sb); -+ __si_write_unlock(sb); -+} -+ -+#if 0 /* unused */ -+static inline void si_downgrade_lock(struct super_block *sb) -+{ -+ __si_downgrade_lock(sb); -+} -+#endif -+ -+/* ---------------------------------------------------------------------- */ -+ -+static inline aufs_bindex_t au_sbend(struct super_block *sb) -+{ -+ SiMustAnyLock(sb); -+ return au_sbi(sb)->si_bend; -+} -+ -+static inline unsigned int au_mntflags(struct super_block *sb) -+{ -+ SiMustAnyLock(sb); -+ return au_sbi(sb)->si_mntflags; -+} -+ -+static inline unsigned int au_sigen(struct super_block *sb) -+{ -+ SiMustAnyLock(sb); -+ return au_sbi(sb)->si_generation; -+} -+ -+static inline void au_ninodes_inc(struct super_block *sb) -+{ -+ atomic_long_inc(&au_sbi(sb)->si_ninodes); -+} -+ -+static inline void au_ninodes_dec(struct super_block *sb) -+{ -+ AuDebugOn(!atomic_long_read(&au_sbi(sb)->si_ninodes)); -+ atomic_long_dec(&au_sbi(sb)->si_ninodes); -+} -+ -+static inline void au_nfiles_inc(struct super_block *sb) -+{ -+ atomic_long_inc(&au_sbi(sb)->si_nfiles); -+} -+ -+static inline void au_nfiles_dec(struct super_block *sb) -+{ -+ AuDebugOn(!atomic_long_read(&au_sbi(sb)->si_nfiles)); -+ atomic_long_dec(&au_sbi(sb)->si_nfiles); -+} -+ -+static inline struct au_branch *au_sbr(struct super_block *sb, -+ aufs_bindex_t bindex) -+{ -+ SiMustAnyLock(sb); -+ return au_sbi(sb)->si_branch[0 + bindex]; -+} -+ -+static inline void au_xino_brid_set(struct super_block *sb, aufs_bindex_t brid) -+{ -+ SiMustWriteLock(sb); -+ au_sbi(sb)->si_xino_brid = brid; -+} -+ -+static inline aufs_bindex_t au_xino_brid(struct super_block *sb) -+{ -+ SiMustAnyLock(sb); -+ return au_sbi(sb)->si_xino_brid; -+} -+ -+#endif /* __KERNEL__ */ -+#endif /* __AUFS_SUPER_H__ */ -diff -Nur linux-2.6.36.orig/fs/aufs/sysaufs.c linux-2.6.36/fs/aufs/sysaufs.c ---- linux-2.6.36.orig/fs/aufs/sysaufs.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/sysaufs.c 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,107 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * sysfs interface and lifetime management -+ * they are necessary regardless sysfs is disabled. -+ */ -+ -+#include -+#include -+#include -+#include "aufs.h" -+ -+unsigned long sysaufs_si_mask; -+struct kset *sysaufs_kset; -+ -+#define AuSiAttr(_name) { \ -+ .attr = { .name = __stringify(_name), .mode = 0444 }, \ -+ .show = sysaufs_si_##_name, \ -+} -+ -+static struct sysaufs_si_attr sysaufs_si_attr_xi_path = AuSiAttr(xi_path); -+struct attribute *sysaufs_si_attrs[] = { -+ &sysaufs_si_attr_xi_path.attr, -+ NULL, -+}; -+ -+static const struct sysfs_ops au_sbi_ops = { -+ .show = sysaufs_si_show -+}; -+ -+static struct kobj_type au_sbi_ktype = { -+ .release = au_si_free, -+ .sysfs_ops = &au_sbi_ops, -+ .default_attrs = sysaufs_si_attrs -+}; -+ -+/* ---------------------------------------------------------------------- */ -+ -+int sysaufs_si_init(struct au_sbinfo *sbinfo) -+{ -+ int err; -+ -+ sbinfo->si_kobj.kset = sysaufs_kset; -+ /* cf. sysaufs_name() */ -+ err = kobject_init_and_add -+ (&sbinfo->si_kobj, &au_sbi_ktype, /*&sysaufs_kset->kobj*/NULL, -+ SysaufsSiNamePrefix "%lx", sysaufs_si_id(sbinfo)); -+ -+ dbgaufs_si_null(sbinfo); -+ if (!err) { -+ err = dbgaufs_si_init(sbinfo); -+ if (unlikely(err)) -+ kobject_put(&sbinfo->si_kobj); -+ } -+ return err; -+} -+ -+void sysaufs_fin(void) -+{ -+ dbgaufs_fin(); -+ sysfs_remove_group(&sysaufs_kset->kobj, sysaufs_attr_group); -+ kset_unregister(sysaufs_kset); -+} -+ -+int __init sysaufs_init(void) -+{ -+ int err; -+ -+ do { -+ get_random_bytes(&sysaufs_si_mask, sizeof(sysaufs_si_mask)); -+ } while (!sysaufs_si_mask); -+ -+ err = -EINVAL; -+ sysaufs_kset = kset_create_and_add(AUFS_NAME, NULL, fs_kobj); -+ if (unlikely(!sysaufs_kset)) -+ goto out; -+ err = PTR_ERR(sysaufs_kset); -+ if (IS_ERR(sysaufs_kset)) -+ goto out; -+ err = sysfs_create_group(&sysaufs_kset->kobj, sysaufs_attr_group); -+ if (unlikely(err)) { -+ kset_unregister(sysaufs_kset); -+ goto out; -+ } -+ -+ err = dbgaufs_init(); -+ if (unlikely(err)) -+ sysaufs_fin(); -+out: -+ return err; -+} -diff -Nur linux-2.6.36.orig/fs/aufs/sysaufs.h linux-2.6.36/fs/aufs/sysaufs.h ---- linux-2.6.36.orig/fs/aufs/sysaufs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/sysaufs.h 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,105 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * sysfs interface and mount lifetime management -+ */ -+ -+#ifndef __SYSAUFS_H__ -+#define __SYSAUFS_H__ -+ -+#ifdef __KERNEL__ -+ -+#include -+#include -+#include "module.h" -+ -+struct super_block; -+struct au_sbinfo; -+ -+struct sysaufs_si_attr { -+ struct attribute attr; -+ int (*show)(struct seq_file *seq, struct super_block *sb); -+}; -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* sysaufs.c */ -+extern unsigned long sysaufs_si_mask; -+extern struct kset *sysaufs_kset; -+extern struct attribute *sysaufs_si_attrs[]; -+int sysaufs_si_init(struct au_sbinfo *sbinfo); -+int __init sysaufs_init(void); -+void sysaufs_fin(void); -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* some people doesn't like to show a pointer in kernel */ -+static inline unsigned long sysaufs_si_id(struct au_sbinfo *sbinfo) -+{ -+ return sysaufs_si_mask ^ (unsigned long)sbinfo; -+} -+ -+#define SysaufsSiNamePrefix "si_" -+#define SysaufsSiNameLen (sizeof(SysaufsSiNamePrefix) + 16) -+static inline void sysaufs_name(struct au_sbinfo *sbinfo, char *name) -+{ -+ snprintf(name, SysaufsSiNameLen, SysaufsSiNamePrefix "%lx", -+ sysaufs_si_id(sbinfo)); -+} -+ -+struct au_branch; -+#ifdef CONFIG_SYSFS -+/* sysfs.c */ -+extern struct attribute_group *sysaufs_attr_group; -+ -+int sysaufs_si_xi_path(struct seq_file *seq, struct super_block *sb); -+ssize_t sysaufs_si_show(struct kobject *kobj, struct attribute *attr, -+ char *buf); -+ -+void sysaufs_br_init(struct au_branch *br); -+void sysaufs_brs_add(struct super_block *sb, aufs_bindex_t bindex); -+void sysaufs_brs_del(struct super_block *sb, aufs_bindex_t bindex); -+ -+#define sysaufs_brs_init() do {} while (0) -+ -+#else -+#define sysaufs_attr_group NULL -+ -+AuStubInt0(sysaufs_si_xi_path, struct seq_file *seq, struct super_block *sb) -+ -+static inline -+ssize_t sysaufs_si_show(struct kobject *kobj, struct attribute *attr, -+ char *buf) -+{ -+ return 0; -+} -+ -+AuStubVoid(sysaufs_br_init, struct au_branch *br) -+AuStubVoid(sysaufs_brs_add, struct super_block *sb, aufs_bindex_t bindex) -+AuStubVoid(sysaufs_brs_del, struct super_block *sb, aufs_bindex_t bindex) -+ -+static inline void sysaufs_brs_init(void) -+{ -+ sysaufs_brs = 0; -+} -+ -+#endif /* CONFIG_SYSFS */ -+ -+#endif /* __KERNEL__ */ -+#endif /* __SYSAUFS_H__ */ -diff -Nur linux-2.6.36.orig/fs/aufs/sysfs.c linux-2.6.36/fs/aufs/sysfs.c ---- linux-2.6.36.orig/fs/aufs/sysfs.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/sysfs.c 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,250 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * sysfs interface -+ */ -+ -+#include -+#include -+#include -+#include -+#include "aufs.h" -+ -+#ifdef CONFIG_AUFS_FS_MODULE -+/* this entry violates the "one line per file" policy of sysfs */ -+static ssize_t config_show(struct kobject *kobj, struct kobj_attribute *attr, -+ char *buf) -+{ -+ ssize_t err; -+ static char *conf = -+/* this file is generated at compiling */ -+#include "conf.str" -+ ; -+ -+ err = snprintf(buf, PAGE_SIZE, conf); -+ if (unlikely(err >= PAGE_SIZE)) -+ err = -EFBIG; -+ return err; -+} -+ -+static struct kobj_attribute au_config_attr = __ATTR_RO(config); -+#endif -+ -+static struct attribute *au_attr[] = { -+#ifdef CONFIG_AUFS_FS_MODULE -+ &au_config_attr.attr, -+#endif -+ NULL, /* need to NULL terminate the list of attributes */ -+}; -+ -+static struct attribute_group sysaufs_attr_group_body = { -+ .attrs = au_attr -+}; -+ -+struct attribute_group *sysaufs_attr_group = &sysaufs_attr_group_body; -+ -+/* ---------------------------------------------------------------------- */ -+ -+int sysaufs_si_xi_path(struct seq_file *seq, struct super_block *sb) -+{ -+ int err; -+ -+ SiMustAnyLock(sb); -+ -+ err = 0; -+ if (au_opt_test(au_mntflags(sb), XINO)) { -+ err = au_xino_path(seq, au_sbi(sb)->si_xib); -+ seq_putc(seq, '\n'); -+ } -+ return err; -+} -+ -+/* -+ * the lifetime of branch is independent from the entry under sysfs. -+ * sysfs handles the lifetime of the entry, and never call ->show() after it is -+ * unlinked. -+ */ -+static int sysaufs_si_br(struct seq_file *seq, struct super_block *sb, -+ aufs_bindex_t bindex) -+{ -+ struct path path; -+ struct dentry *root; -+ struct au_branch *br; -+ -+ AuDbg("b%d\n", bindex); -+ -+ root = sb->s_root; -+ di_read_lock_parent(root, !AuLock_IR); -+ br = au_sbr(sb, bindex); -+ path.mnt = br->br_mnt; -+ path.dentry = au_h_dptr(root, bindex); -+ au_seq_path(seq, &path); -+ di_read_unlock(root, !AuLock_IR); -+ seq_printf(seq, "=%s\n", au_optstr_br_perm(br->br_perm)); -+ return 0; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static struct seq_file *au_seq(char *p, ssize_t len) -+{ -+ struct seq_file *seq; -+ -+ seq = kzalloc(sizeof(*seq), GFP_NOFS); -+ if (seq) { -+ /* mutex_init(&seq.lock); */ -+ seq->buf = p; -+ seq->size = len; -+ return seq; /* success */ -+ } -+ -+ seq = ERR_PTR(-ENOMEM); -+ return seq; -+} -+ -+#define SysaufsBr_PREFIX "br" -+ -+/* todo: file size may exceed PAGE_SIZE */ -+ssize_t sysaufs_si_show(struct kobject *kobj, struct attribute *attr, -+ char *buf) -+{ -+ ssize_t err; -+ long l; -+ aufs_bindex_t bend; -+ struct au_sbinfo *sbinfo; -+ struct super_block *sb; -+ struct seq_file *seq; -+ char *name; -+ struct attribute **cattr; -+ -+ sbinfo = container_of(kobj, struct au_sbinfo, si_kobj); -+ sb = sbinfo->si_sb; -+ -+ /* -+ * prevent a race condition between sysfs and aufs. -+ * for instance, sysfs_file_read() calls sysfs_get_active_two() which -+ * prohibits maintaining the sysfs entries. -+ * hew we acquire read lock after sysfs_get_active_two(). -+ * on the other hand, the remount process may maintain the sysfs/aufs -+ * entries after acquiring write lock. -+ * it can cause a deadlock. -+ * simply we gave up processing read here. -+ */ -+ err = -EBUSY; -+ if (unlikely(!si_noflush_read_trylock(sb))) -+ goto out; -+ -+ seq = au_seq(buf, PAGE_SIZE); -+ err = PTR_ERR(seq); -+ if (IS_ERR(seq)) -+ goto out_unlock; -+ -+ name = (void *)attr->name; -+ cattr = sysaufs_si_attrs; -+ while (*cattr) { -+ if (!strcmp(name, (*cattr)->name)) { -+ err = container_of(*cattr, struct sysaufs_si_attr, attr) -+ ->show(seq, sb); -+ goto out_seq; -+ } -+ cattr++; -+ } -+ -+ bend = au_sbend(sb); -+ if (!strncmp(name, SysaufsBr_PREFIX, sizeof(SysaufsBr_PREFIX) - 1)) { -+ name += sizeof(SysaufsBr_PREFIX) - 1; -+ err = strict_strtol(name, 10, &l); -+ if (!err) { -+ if (l <= bend) -+ err = sysaufs_si_br(seq, sb, (aufs_bindex_t)l); -+ else -+ err = -ENOENT; -+ } -+ goto out_seq; -+ } -+ BUG(); -+ -+out_seq: -+ if (!err) { -+ err = seq->count; -+ /* sysfs limit */ -+ if (unlikely(err == PAGE_SIZE)) -+ err = -EFBIG; -+ } -+ kfree(seq); -+out_unlock: -+ si_read_unlock(sb); -+out: -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+void sysaufs_br_init(struct au_branch *br) -+{ -+ struct attribute *attr = &br->br_attr; -+ -+ sysfs_attr_init(attr); -+ attr->name = br->br_name; -+ attr->mode = S_IRUGO; -+} -+ -+void sysaufs_brs_del(struct super_block *sb, aufs_bindex_t bindex) -+{ -+ struct au_branch *br; -+ struct kobject *kobj; -+ aufs_bindex_t bend; -+ -+ dbgaufs_brs_del(sb, bindex); -+ -+ if (!sysaufs_brs) -+ return; -+ -+ kobj = &au_sbi(sb)->si_kobj; -+ bend = au_sbend(sb); -+ for (; bindex <= bend; bindex++) { -+ br = au_sbr(sb, bindex); -+ sysfs_remove_file(kobj, &br->br_attr); -+ } -+} -+ -+void sysaufs_brs_add(struct super_block *sb, aufs_bindex_t bindex) -+{ -+ int err; -+ aufs_bindex_t bend; -+ struct kobject *kobj; -+ struct au_branch *br; -+ -+ dbgaufs_brs_add(sb, bindex); -+ -+ if (!sysaufs_brs) -+ return; -+ -+ kobj = &au_sbi(sb)->si_kobj; -+ bend = au_sbend(sb); -+ for (; bindex <= bend; bindex++) { -+ br = au_sbr(sb, bindex); -+ snprintf(br->br_name, sizeof(br->br_name), SysaufsBr_PREFIX -+ "%d", bindex); -+ err = sysfs_create_file(kobj, &br->br_attr); -+ if (unlikely(err)) -+ pr_warning("failed %s under sysfs(%d)\n", -+ br->br_name, err); -+ } -+} -diff -Nur linux-2.6.36.orig/fs/aufs/sysrq.c linux-2.6.36/fs/aufs/sysrq.c ---- linux-2.6.36.orig/fs/aufs/sysrq.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/sysrq.c 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,148 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * magic sysrq hanlder -+ */ -+ -+#include -+#include -+#include -+/* #include */ -+#include -+#include "aufs.h" -+ -+/* ---------------------------------------------------------------------- */ -+ -+static void sysrq_sb(struct super_block *sb) -+{ -+ char *plevel; -+ struct au_sbinfo *sbinfo; -+ struct file *file; -+ -+ plevel = au_plevel; -+ au_plevel = KERN_WARNING; -+ -+ sbinfo = au_sbi(sb); -+ /* since we define pr_fmt, call printk directly */ -+ printk(KERN_WARNING "si=%lx\n", sysaufs_si_id(sbinfo)); -+ printk(KERN_WARNING AUFS_NAME ": superblock\n"); -+ au_dpri_sb(sb); -+ -+#if 0 -+ printk(KERN_WARNING AUFS_NAME ": root dentry\n"); -+ au_dpri_dentry(sb->s_root); -+ printk(KERN_WARNING AUFS_NAME ": root inode\n"); -+ au_dpri_inode(sb->s_root->d_inode); -+#endif -+ -+#if 0 -+ do { -+ int err, i, j, ndentry; -+ struct au_dcsub_pages dpages; -+ struct au_dpage *dpage; -+ -+ err = au_dpages_init(&dpages, GFP_ATOMIC); -+ if (unlikely(err)) -+ break; -+ err = au_dcsub_pages(&dpages, sb->s_root, NULL, NULL); -+ if (!err) -+ for (i = 0; i < dpages.ndpage; i++) { -+ dpage = dpages.dpages + i; -+ ndentry = dpage->ndentry; -+ for (j = 0; j < ndentry; j++) -+ au_dpri_dentry(dpage->dentries[j]); -+ } -+ au_dpages_free(&dpages); -+ } while (0); -+#endif -+ -+#if 1 -+ { -+ struct inode *i; -+ printk(KERN_WARNING AUFS_NAME ": isolated inode\n"); -+ spin_lock(&inode_lock); -+ list_for_each_entry(i, &sb->s_inodes, i_sb_list) -+ if (1 || list_empty(&i->i_dentry)) -+ au_dpri_inode(i); -+ spin_unlock(&inode_lock); -+ } -+#endif -+ printk(KERN_WARNING AUFS_NAME ": files\n"); -+ lg_global_lock(files_lglock); -+ do_file_list_for_each_entry(sb, file) { -+ umode_t mode; -+ mode = file->f_dentry->d_inode->i_mode; -+ if (!special_file(mode) || au_special_file(mode)) -+ au_dpri_file(file); -+ } while_file_list_for_each_entry; -+ lg_global_unlock(files_lglock); -+ printk(KERN_WARNING AUFS_NAME ": done\n"); -+ -+ au_plevel = plevel; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* module parameter */ -+static char *aufs_sysrq_key = "a"; -+module_param_named(sysrq, aufs_sysrq_key, charp, S_IRUGO); -+MODULE_PARM_DESC(sysrq, "MagicSysRq key for " AUFS_NAME); -+ -+static void au_sysrq(int key __maybe_unused) -+{ -+ struct au_sbinfo *sbinfo; -+ -+ lockdep_off(); -+ spin_lock(&au_sbilist.spin); -+ list_for_each_entry(sbinfo, &au_sbilist.head, si_list) -+ sysrq_sb(sbinfo->si_sb); -+ spin_unlock(&au_sbilist.spin); -+ lockdep_on(); -+} -+ -+static struct sysrq_key_op au_sysrq_op = { -+ .handler = au_sysrq, -+ .help_msg = "Aufs", -+ .action_msg = "Aufs", -+ .enable_mask = SYSRQ_ENABLE_DUMP -+}; -+ -+/* ---------------------------------------------------------------------- */ -+ -+int __init au_sysrq_init(void) -+{ -+ int err; -+ char key; -+ -+ err = -1; -+ key = *aufs_sysrq_key; -+ if ('a' <= key && key <= 'z') -+ err = register_sysrq_key(key, &au_sysrq_op); -+ if (unlikely(err)) -+ pr_err("err %d, sysrq=%c\n", err, key); -+ return err; -+} -+ -+void au_sysrq_fin(void) -+{ -+ int err; -+ err = unregister_sysrq_key(*aufs_sysrq_key, &au_sysrq_op); -+ if (unlikely(err)) -+ pr_err("err %d (ignored)\n", err); -+} -diff -Nur linux-2.6.36.orig/fs/aufs/vdir.c linux-2.6.36/fs/aufs/vdir.c ---- linux-2.6.36.orig/fs/aufs/vdir.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/vdir.c 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,886 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * virtual or vertical directory -+ */ -+ -+#include -+#include "aufs.h" -+ -+static unsigned int calc_size(int nlen) -+{ -+ return ALIGN(sizeof(struct au_vdir_de) + nlen, sizeof(ino_t)); -+} -+ -+static int set_deblk_end(union au_vdir_deblk_p *p, -+ union au_vdir_deblk_p *deblk_end) -+{ -+ if (calc_size(0) <= deblk_end->deblk - p->deblk) { -+ p->de->de_str.len = 0; -+ /* smp_mb(); */ -+ return 0; -+ } -+ return -1; /* error */ -+} -+ -+/* returns true or false */ -+static int is_deblk_end(union au_vdir_deblk_p *p, -+ union au_vdir_deblk_p *deblk_end) -+{ -+ if (calc_size(0) <= deblk_end->deblk - p->deblk) -+ return !p->de->de_str.len; -+ return 1; -+} -+ -+static unsigned char *last_deblk(struct au_vdir *vdir) -+{ -+ return vdir->vd_deblk[vdir->vd_nblk - 1]; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* estimate the apropriate size for name hash table */ -+unsigned int au_rdhash_est(loff_t sz) -+{ -+ unsigned int n; -+ -+ n = UINT_MAX; -+ sz >>= 10; -+ if (sz < n) -+ n = sz; -+ if (sz < AUFS_RDHASH_DEF) -+ n = AUFS_RDHASH_DEF; -+ /* pr_info("n %u\n", n); */ -+ return n; -+} -+ -+/* -+ * the allocated memory has to be freed by -+ * au_nhash_wh_free() or au_nhash_de_free(). -+ */ -+int au_nhash_alloc(struct au_nhash *nhash, unsigned int num_hash, gfp_t gfp) -+{ -+ struct hlist_head *head; -+ unsigned int u; -+ -+ head = kmalloc(sizeof(*nhash->nh_head) * num_hash, gfp); -+ if (head) { -+ nhash->nh_num = num_hash; -+ nhash->nh_head = head; -+ for (u = 0; u < num_hash; u++) -+ INIT_HLIST_HEAD(head++); -+ return 0; /* success */ -+ } -+ -+ return -ENOMEM; -+} -+ -+static void nhash_count(struct hlist_head *head) -+{ -+#if 0 -+ unsigned long n; -+ struct hlist_node *pos; -+ -+ n = 0; -+ hlist_for_each(pos, head) -+ n++; -+ pr_info("%lu\n", n); -+#endif -+} -+ -+static void au_nhash_wh_do_free(struct hlist_head *head) -+{ -+ struct au_vdir_wh *tpos; -+ struct hlist_node *pos, *node; -+ -+ hlist_for_each_entry_safe(tpos, pos, node, head, wh_hash) { -+ /* hlist_del(pos); */ -+ kfree(tpos); -+ } -+} -+ -+static void au_nhash_de_do_free(struct hlist_head *head) -+{ -+ struct au_vdir_dehstr *tpos; -+ struct hlist_node *pos, *node; -+ -+ hlist_for_each_entry_safe(tpos, pos, node, head, hash) { -+ /* hlist_del(pos); */ -+ au_cache_free_vdir_dehstr(tpos); -+ } -+} -+ -+static void au_nhash_do_free(struct au_nhash *nhash, -+ void (*free)(struct hlist_head *head)) -+{ -+ unsigned int n; -+ struct hlist_head *head; -+ -+ n = nhash->nh_num; -+ if (!n) -+ return; -+ -+ head = nhash->nh_head; -+ while (n-- > 0) { -+ nhash_count(head); -+ free(head++); -+ } -+ kfree(nhash->nh_head); -+} -+ -+void au_nhash_wh_free(struct au_nhash *whlist) -+{ -+ au_nhash_do_free(whlist, au_nhash_wh_do_free); -+} -+ -+static void au_nhash_de_free(struct au_nhash *delist) -+{ -+ au_nhash_do_free(delist, au_nhash_de_do_free); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+int au_nhash_test_longer_wh(struct au_nhash *whlist, aufs_bindex_t btgt, -+ int limit) -+{ -+ int num; -+ unsigned int u, n; -+ struct hlist_head *head; -+ struct au_vdir_wh *tpos; -+ struct hlist_node *pos; -+ -+ num = 0; -+ n = whlist->nh_num; -+ head = whlist->nh_head; -+ for (u = 0; u < n; u++, head++) -+ hlist_for_each_entry(tpos, pos, head, wh_hash) -+ if (tpos->wh_bindex == btgt && ++num > limit) -+ return 1; -+ return 0; -+} -+ -+static struct hlist_head *au_name_hash(struct au_nhash *nhash, -+ unsigned char *name, -+ unsigned int len) -+{ -+ unsigned int v; -+ /* const unsigned int magic_bit = 12; */ -+ -+ AuDebugOn(!nhash->nh_num || !nhash->nh_head); -+ -+ v = 0; -+ while (len--) -+ v += *name++; -+ /* v = hash_long(v, magic_bit); */ -+ v %= nhash->nh_num; -+ return nhash->nh_head + v; -+} -+ -+static int au_nhash_test_name(struct au_vdir_destr *str, const char *name, -+ int nlen) -+{ -+ return str->len == nlen && !memcmp(str->name, name, nlen); -+} -+ -+/* returns found or not */ -+int au_nhash_test_known_wh(struct au_nhash *whlist, char *name, int nlen) -+{ -+ struct hlist_head *head; -+ struct au_vdir_wh *tpos; -+ struct hlist_node *pos; -+ struct au_vdir_destr *str; -+ -+ head = au_name_hash(whlist, name, nlen); -+ hlist_for_each_entry(tpos, pos, head, wh_hash) { -+ str = &tpos->wh_str; -+ AuDbg("%.*s\n", str->len, str->name); -+ if (au_nhash_test_name(str, name, nlen)) -+ return 1; -+ } -+ return 0; -+} -+ -+/* returns found(true) or not */ -+static int test_known(struct au_nhash *delist, char *name, int nlen) -+{ -+ struct hlist_head *head; -+ struct au_vdir_dehstr *tpos; -+ struct hlist_node *pos; -+ struct au_vdir_destr *str; -+ -+ head = au_name_hash(delist, name, nlen); -+ hlist_for_each_entry(tpos, pos, head, hash) { -+ str = tpos->str; -+ AuDbg("%.*s\n", str->len, str->name); -+ if (au_nhash_test_name(str, name, nlen)) -+ return 1; -+ } -+ return 0; -+} -+ -+static void au_shwh_init_wh(struct au_vdir_wh *wh, ino_t ino, -+ unsigned char d_type) -+{ -+#ifdef CONFIG_AUFS_SHWH -+ wh->wh_ino = ino; -+ wh->wh_type = d_type; -+#endif -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+int au_nhash_append_wh(struct au_nhash *whlist, char *name, int nlen, ino_t ino, -+ unsigned int d_type, aufs_bindex_t bindex, -+ unsigned char shwh) -+{ -+ int err; -+ struct au_vdir_destr *str; -+ struct au_vdir_wh *wh; -+ -+ AuDbg("%.*s\n", nlen, name); -+ AuDebugOn(!whlist->nh_num || !whlist->nh_head); -+ -+ err = -ENOMEM; -+ wh = kmalloc(sizeof(*wh) + nlen, GFP_NOFS); -+ if (unlikely(!wh)) -+ goto out; -+ -+ err = 0; -+ wh->wh_bindex = bindex; -+ if (shwh) -+ au_shwh_init_wh(wh, ino, d_type); -+ str = &wh->wh_str; -+ str->len = nlen; -+ memcpy(str->name, name, nlen); -+ hlist_add_head(&wh->wh_hash, au_name_hash(whlist, name, nlen)); -+ /* smp_mb(); */ -+ -+out: -+ return err; -+} -+ -+static int append_deblk(struct au_vdir *vdir) -+{ -+ int err; -+ unsigned long ul; -+ const unsigned int deblk_sz = vdir->vd_deblk_sz; -+ union au_vdir_deblk_p p, deblk_end; -+ unsigned char **o; -+ -+ err = -ENOMEM; -+ o = krealloc(vdir->vd_deblk, sizeof(*o) * (vdir->vd_nblk + 1), -+ GFP_NOFS); -+ if (unlikely(!o)) -+ goto out; -+ -+ vdir->vd_deblk = o; -+ p.deblk = kmalloc(deblk_sz, GFP_NOFS); -+ if (p.deblk) { -+ ul = vdir->vd_nblk++; -+ vdir->vd_deblk[ul] = p.deblk; -+ vdir->vd_last.ul = ul; -+ vdir->vd_last.p.deblk = p.deblk; -+ deblk_end.deblk = p.deblk + deblk_sz; -+ err = set_deblk_end(&p, &deblk_end); -+ } -+ -+out: -+ return err; -+} -+ -+static int append_de(struct au_vdir *vdir, char *name, int nlen, ino_t ino, -+ unsigned int d_type, struct au_nhash *delist) -+{ -+ int err; -+ unsigned int sz; -+ const unsigned int deblk_sz = vdir->vd_deblk_sz; -+ union au_vdir_deblk_p p, *room, deblk_end; -+ struct au_vdir_dehstr *dehstr; -+ -+ p.deblk = last_deblk(vdir); -+ deblk_end.deblk = p.deblk + deblk_sz; -+ room = &vdir->vd_last.p; -+ AuDebugOn(room->deblk < p.deblk || deblk_end.deblk <= room->deblk -+ || !is_deblk_end(room, &deblk_end)); -+ -+ sz = calc_size(nlen); -+ if (unlikely(sz > deblk_end.deblk - room->deblk)) { -+ err = append_deblk(vdir); -+ if (unlikely(err)) -+ goto out; -+ -+ p.deblk = last_deblk(vdir); -+ deblk_end.deblk = p.deblk + deblk_sz; -+ /* smp_mb(); */ -+ AuDebugOn(room->deblk != p.deblk); -+ } -+ -+ err = -ENOMEM; -+ dehstr = au_cache_alloc_vdir_dehstr(); -+ if (unlikely(!dehstr)) -+ goto out; -+ -+ dehstr->str = &room->de->de_str; -+ hlist_add_head(&dehstr->hash, au_name_hash(delist, name, nlen)); -+ room->de->de_ino = ino; -+ room->de->de_type = d_type; -+ room->de->de_str.len = nlen; -+ memcpy(room->de->de_str.name, name, nlen); -+ -+ err = 0; -+ room->deblk += sz; -+ if (unlikely(set_deblk_end(room, &deblk_end))) -+ err = append_deblk(vdir); -+ /* smp_mb(); */ -+ -+out: -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+void au_vdir_free(struct au_vdir *vdir) -+{ -+ unsigned char **deblk; -+ -+ deblk = vdir->vd_deblk; -+ while (vdir->vd_nblk--) -+ kfree(*deblk++); -+ kfree(vdir->vd_deblk); -+ au_cache_free_vdir(vdir); -+} -+ -+static struct au_vdir *alloc_vdir(struct file *file) -+{ -+ struct au_vdir *vdir; -+ struct super_block *sb; -+ int err; -+ -+ sb = file->f_dentry->d_sb; -+ SiMustAnyLock(sb); -+ -+ err = -ENOMEM; -+ vdir = au_cache_alloc_vdir(); -+ if (unlikely(!vdir)) -+ goto out; -+ -+ vdir->vd_deblk = kzalloc(sizeof(*vdir->vd_deblk), GFP_NOFS); -+ if (unlikely(!vdir->vd_deblk)) -+ goto out_free; -+ -+ vdir->vd_deblk_sz = au_sbi(sb)->si_rdblk; -+ if (!vdir->vd_deblk_sz) { -+ /* estimate the apropriate size for deblk */ -+ vdir->vd_deblk_sz = au_dir_size(file, /*dentry*/NULL); -+ /* pr_info("vd_deblk_sz %u\n", vdir->vd_deblk_sz); */ -+ } -+ vdir->vd_nblk = 0; -+ vdir->vd_version = 0; -+ vdir->vd_jiffy = 0; -+ err = append_deblk(vdir); -+ if (!err) -+ return vdir; /* success */ -+ -+ kfree(vdir->vd_deblk); -+ -+out_free: -+ au_cache_free_vdir(vdir); -+out: -+ vdir = ERR_PTR(err); -+ return vdir; -+} -+ -+static int reinit_vdir(struct au_vdir *vdir) -+{ -+ int err; -+ union au_vdir_deblk_p p, deblk_end; -+ -+ while (vdir->vd_nblk > 1) { -+ kfree(vdir->vd_deblk[vdir->vd_nblk - 1]); -+ /* vdir->vd_deblk[vdir->vd_nblk - 1] = NULL; */ -+ vdir->vd_nblk--; -+ } -+ p.deblk = vdir->vd_deblk[0]; -+ deblk_end.deblk = p.deblk + vdir->vd_deblk_sz; -+ err = set_deblk_end(&p, &deblk_end); -+ /* keep vd_dblk_sz */ -+ vdir->vd_last.ul = 0; -+ vdir->vd_last.p.deblk = vdir->vd_deblk[0]; -+ vdir->vd_version = 0; -+ vdir->vd_jiffy = 0; -+ /* smp_mb(); */ -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+#define AuFillVdir_CALLED 1 -+#define AuFillVdir_WHABLE (1 << 1) -+#define AuFillVdir_SHWH (1 << 2) -+#define au_ftest_fillvdir(flags, name) ((flags) & AuFillVdir_##name) -+#define au_fset_fillvdir(flags, name) \ -+ do { (flags) |= AuFillVdir_##name; } while (0) -+#define au_fclr_fillvdir(flags, name) \ -+ do { (flags) &= ~AuFillVdir_##name; } while (0) -+ -+#ifndef CONFIG_AUFS_SHWH -+#undef AuFillVdir_SHWH -+#define AuFillVdir_SHWH 0 -+#endif -+ -+struct fillvdir_arg { -+ struct file *file; -+ struct au_vdir *vdir; -+ struct au_nhash delist; -+ struct au_nhash whlist; -+ aufs_bindex_t bindex; -+ unsigned int flags; -+ int err; -+}; -+ -+static int fillvdir(void *__arg, const char *__name, int nlen, -+ loff_t offset __maybe_unused, u64 h_ino, -+ unsigned int d_type) -+{ -+ struct fillvdir_arg *arg = __arg; -+ char *name = (void *)__name; -+ struct super_block *sb; -+ ino_t ino; -+ const unsigned char shwh = !!au_ftest_fillvdir(arg->flags, SHWH); -+ -+ arg->err = 0; -+ sb = arg->file->f_dentry->d_sb; -+ au_fset_fillvdir(arg->flags, CALLED); -+ /* smp_mb(); */ -+ if (nlen <= AUFS_WH_PFX_LEN -+ || memcmp(name, AUFS_WH_PFX, AUFS_WH_PFX_LEN)) { -+ if (test_known(&arg->delist, name, nlen) -+ || au_nhash_test_known_wh(&arg->whlist, name, nlen)) -+ goto out; /* already exists or whiteouted */ -+ -+ sb = arg->file->f_dentry->d_sb; -+ arg->err = au_ino(sb, arg->bindex, h_ino, d_type, &ino); -+ if (!arg->err) { -+ if (unlikely(nlen > AUFS_MAX_NAMELEN)) -+ d_type = DT_UNKNOWN; -+ arg->err = append_de(arg->vdir, name, nlen, ino, -+ d_type, &arg->delist); -+ } -+ } else if (au_ftest_fillvdir(arg->flags, WHABLE)) { -+ name += AUFS_WH_PFX_LEN; -+ nlen -= AUFS_WH_PFX_LEN; -+ if (au_nhash_test_known_wh(&arg->whlist, name, nlen)) -+ goto out; /* already whiteouted */ -+ -+ if (shwh) -+ arg->err = au_wh_ino(sb, arg->bindex, h_ino, d_type, -+ &ino); -+ if (!arg->err) { -+ if (nlen <= AUFS_MAX_NAMELEN + AUFS_WH_PFX_LEN) -+ d_type = DT_UNKNOWN; -+ arg->err = au_nhash_append_wh -+ (&arg->whlist, name, nlen, ino, d_type, -+ arg->bindex, shwh); -+ } -+ } -+ -+out: -+ if (!arg->err) -+ arg->vdir->vd_jiffy = jiffies; -+ /* smp_mb(); */ -+ AuTraceErr(arg->err); -+ return arg->err; -+} -+ -+static int au_handle_shwh(struct super_block *sb, struct au_vdir *vdir, -+ struct au_nhash *whlist, struct au_nhash *delist) -+{ -+#ifdef CONFIG_AUFS_SHWH -+ int err; -+ unsigned int nh, u; -+ struct hlist_head *head; -+ struct au_vdir_wh *tpos; -+ struct hlist_node *pos, *n; -+ char *p, *o; -+ struct au_vdir_destr *destr; -+ -+ AuDebugOn(!au_opt_test(au_mntflags(sb), SHWH)); -+ -+ err = -ENOMEM; -+ o = p = __getname_gfp(GFP_NOFS); -+ if (unlikely(!p)) -+ goto out; -+ -+ err = 0; -+ nh = whlist->nh_num; -+ memcpy(p, AUFS_WH_PFX, AUFS_WH_PFX_LEN); -+ p += AUFS_WH_PFX_LEN; -+ for (u = 0; u < nh; u++) { -+ head = whlist->nh_head + u; -+ hlist_for_each_entry_safe(tpos, pos, n, head, wh_hash) { -+ destr = &tpos->wh_str; -+ memcpy(p, destr->name, destr->len); -+ err = append_de(vdir, o, destr->len + AUFS_WH_PFX_LEN, -+ tpos->wh_ino, tpos->wh_type, delist); -+ if (unlikely(err)) -+ break; -+ } -+ } -+ -+ __putname(o); -+ -+out: -+ AuTraceErr(err); -+ return err; -+#else -+ return 0; -+#endif -+} -+ -+static int au_do_read_vdir(struct fillvdir_arg *arg) -+{ -+ int err; -+ unsigned int rdhash; -+ loff_t offset; -+ aufs_bindex_t bend, bindex, bstart; -+ unsigned char shwh; -+ struct file *hf, *file; -+ struct super_block *sb; -+ -+ file = arg->file; -+ sb = file->f_dentry->d_sb; -+ SiMustAnyLock(sb); -+ -+ rdhash = au_sbi(sb)->si_rdhash; -+ if (!rdhash) -+ rdhash = au_rdhash_est(au_dir_size(file, /*dentry*/NULL)); -+ err = au_nhash_alloc(&arg->delist, rdhash, GFP_NOFS); -+ if (unlikely(err)) -+ goto out; -+ err = au_nhash_alloc(&arg->whlist, rdhash, GFP_NOFS); -+ if (unlikely(err)) -+ goto out_delist; -+ -+ err = 0; -+ arg->flags = 0; -+ shwh = 0; -+ if (au_opt_test(au_mntflags(sb), SHWH)) { -+ shwh = 1; -+ au_fset_fillvdir(arg->flags, SHWH); -+ } -+ bstart = au_fbstart(file); -+ bend = au_fbend_dir(file); -+ for (bindex = bstart; !err && bindex <= bend; bindex++) { -+ hf = au_hf_dir(file, bindex); -+ if (!hf) -+ continue; -+ -+ offset = vfsub_llseek(hf, 0, SEEK_SET); -+ err = offset; -+ if (unlikely(offset)) -+ break; -+ -+ arg->bindex = bindex; -+ au_fclr_fillvdir(arg->flags, WHABLE); -+ if (shwh -+ || (bindex != bend -+ && au_br_whable(au_sbr_perm(sb, bindex)))) -+ au_fset_fillvdir(arg->flags, WHABLE); -+ do { -+ arg->err = 0; -+ au_fclr_fillvdir(arg->flags, CALLED); -+ /* smp_mb(); */ -+ err = vfsub_readdir(hf, fillvdir, arg); -+ if (err >= 0) -+ err = arg->err; -+ } while (!err && au_ftest_fillvdir(arg->flags, CALLED)); -+ } -+ -+ if (!err && shwh) -+ err = au_handle_shwh(sb, arg->vdir, &arg->whlist, &arg->delist); -+ -+ au_nhash_wh_free(&arg->whlist); -+ -+out_delist: -+ au_nhash_de_free(&arg->delist); -+out: -+ return err; -+} -+ -+static int read_vdir(struct file *file, int may_read) -+{ -+ int err; -+ unsigned long expire; -+ unsigned char do_read; -+ struct fillvdir_arg arg; -+ struct inode *inode; -+ struct au_vdir *vdir, *allocated; -+ -+ err = 0; -+ inode = file->f_dentry->d_inode; -+ IMustLock(inode); -+ SiMustAnyLock(inode->i_sb); -+ -+ allocated = NULL; -+ do_read = 0; -+ expire = au_sbi(inode->i_sb)->si_rdcache; -+ vdir = au_ivdir(inode); -+ if (!vdir) { -+ do_read = 1; -+ vdir = alloc_vdir(file); -+ err = PTR_ERR(vdir); -+ if (IS_ERR(vdir)) -+ goto out; -+ err = 0; -+ allocated = vdir; -+ } else if (may_read -+ && (inode->i_version != vdir->vd_version -+ || time_after(jiffies, vdir->vd_jiffy + expire))) { -+ do_read = 1; -+ err = reinit_vdir(vdir); -+ if (unlikely(err)) -+ goto out; -+ } -+ -+ if (!do_read) -+ return 0; /* success */ -+ -+ arg.file = file; -+ arg.vdir = vdir; -+ err = au_do_read_vdir(&arg); -+ if (!err) { -+ /* file->f_pos = 0; */ -+ vdir->vd_version = inode->i_version; -+ vdir->vd_last.ul = 0; -+ vdir->vd_last.p.deblk = vdir->vd_deblk[0]; -+ if (allocated) -+ au_set_ivdir(inode, allocated); -+ } else if (allocated) -+ au_vdir_free(allocated); -+ -+out: -+ return err; -+} -+ -+static int copy_vdir(struct au_vdir *tgt, struct au_vdir *src) -+{ -+ int err, rerr; -+ unsigned long ul, n; -+ const unsigned int deblk_sz = src->vd_deblk_sz; -+ -+ AuDebugOn(tgt->vd_nblk != 1); -+ -+ err = -ENOMEM; -+ if (tgt->vd_nblk < src->vd_nblk) { -+ unsigned char **p; -+ -+ p = krealloc(tgt->vd_deblk, sizeof(*p) * src->vd_nblk, -+ GFP_NOFS); -+ if (unlikely(!p)) -+ goto out; -+ tgt->vd_deblk = p; -+ } -+ -+ if (tgt->vd_deblk_sz != deblk_sz) { -+ unsigned char *p; -+ -+ tgt->vd_deblk_sz = deblk_sz; -+ p = krealloc(tgt->vd_deblk[0], deblk_sz, GFP_NOFS); -+ if (unlikely(!p)) -+ goto out; -+ tgt->vd_deblk[0] = p; -+ } -+ memcpy(tgt->vd_deblk[0], src->vd_deblk[0], deblk_sz); -+ tgt->vd_version = src->vd_version; -+ tgt->vd_jiffy = src->vd_jiffy; -+ -+ n = src->vd_nblk; -+ for (ul = 1; ul < n; ul++) { -+ tgt->vd_deblk[ul] = kmemdup(src->vd_deblk[ul], deblk_sz, -+ GFP_NOFS); -+ if (unlikely(!tgt->vd_deblk[ul])) -+ goto out; -+ tgt->vd_nblk++; -+ } -+ tgt->vd_nblk = n; -+ tgt->vd_last.ul = tgt->vd_last.ul; -+ tgt->vd_last.p.deblk = tgt->vd_deblk[tgt->vd_last.ul]; -+ tgt->vd_last.p.deblk += src->vd_last.p.deblk -+ - src->vd_deblk[src->vd_last.ul]; -+ /* smp_mb(); */ -+ return 0; /* success */ -+ -+out: -+ rerr = reinit_vdir(tgt); -+ BUG_ON(rerr); -+ return err; -+} -+ -+int au_vdir_init(struct file *file) -+{ -+ int err; -+ struct inode *inode; -+ struct au_vdir *vdir_cache, *allocated; -+ -+ err = read_vdir(file, !file->f_pos); -+ if (unlikely(err)) -+ goto out; -+ -+ allocated = NULL; -+ vdir_cache = au_fvdir_cache(file); -+ if (!vdir_cache) { -+ vdir_cache = alloc_vdir(file); -+ err = PTR_ERR(vdir_cache); -+ if (IS_ERR(vdir_cache)) -+ goto out; -+ allocated = vdir_cache; -+ } else if (!file->f_pos && vdir_cache->vd_version != file->f_version) { -+ err = reinit_vdir(vdir_cache); -+ if (unlikely(err)) -+ goto out; -+ } else -+ return 0; /* success */ -+ -+ inode = file->f_dentry->d_inode; -+ err = copy_vdir(vdir_cache, au_ivdir(inode)); -+ if (!err) { -+ file->f_version = inode->i_version; -+ if (allocated) -+ au_set_fvdir_cache(file, allocated); -+ } else if (allocated) -+ au_vdir_free(allocated); -+ -+out: -+ return err; -+} -+ -+static loff_t calc_offset(struct au_vdir *vdir) -+{ -+ loff_t offset; -+ union au_vdir_deblk_p p; -+ -+ p.deblk = vdir->vd_deblk[vdir->vd_last.ul]; -+ offset = vdir->vd_last.p.deblk - p.deblk; -+ offset += vdir->vd_deblk_sz * vdir->vd_last.ul; -+ return offset; -+} -+ -+/* returns true or false */ -+static int seek_vdir(struct file *file) -+{ -+ int valid; -+ unsigned int deblk_sz; -+ unsigned long ul, n; -+ loff_t offset; -+ union au_vdir_deblk_p p, deblk_end; -+ struct au_vdir *vdir_cache; -+ -+ valid = 1; -+ vdir_cache = au_fvdir_cache(file); -+ offset = calc_offset(vdir_cache); -+ AuDbg("offset %lld\n", offset); -+ if (file->f_pos == offset) -+ goto out; -+ -+ vdir_cache->vd_last.ul = 0; -+ vdir_cache->vd_last.p.deblk = vdir_cache->vd_deblk[0]; -+ if (!file->f_pos) -+ goto out; -+ -+ valid = 0; -+ deblk_sz = vdir_cache->vd_deblk_sz; -+ ul = div64_u64(file->f_pos, deblk_sz); -+ AuDbg("ul %lu\n", ul); -+ if (ul >= vdir_cache->vd_nblk) -+ goto out; -+ -+ n = vdir_cache->vd_nblk; -+ for (; ul < n; ul++) { -+ p.deblk = vdir_cache->vd_deblk[ul]; -+ deblk_end.deblk = p.deblk + deblk_sz; -+ offset = ul; -+ offset *= deblk_sz; -+ while (!is_deblk_end(&p, &deblk_end) && offset < file->f_pos) { -+ unsigned int l; -+ -+ l = calc_size(p.de->de_str.len); -+ offset += l; -+ p.deblk += l; -+ } -+ if (!is_deblk_end(&p, &deblk_end)) { -+ valid = 1; -+ vdir_cache->vd_last.ul = ul; -+ vdir_cache->vd_last.p = p; -+ break; -+ } -+ } -+ -+out: -+ /* smp_mb(); */ -+ AuTraceErr(!valid); -+ return valid; -+} -+ -+int au_vdir_fill_de(struct file *file, void *dirent, filldir_t filldir) -+{ -+ int err; -+ unsigned int l, deblk_sz; -+ union au_vdir_deblk_p deblk_end; -+ struct au_vdir *vdir_cache; -+ struct au_vdir_de *de; -+ -+ vdir_cache = au_fvdir_cache(file); -+ if (!seek_vdir(file)) -+ return 0; -+ -+ deblk_sz = vdir_cache->vd_deblk_sz; -+ while (1) { -+ deblk_end.deblk = vdir_cache->vd_deblk[vdir_cache->vd_last.ul]; -+ deblk_end.deblk += deblk_sz; -+ while (!is_deblk_end(&vdir_cache->vd_last.p, &deblk_end)) { -+ de = vdir_cache->vd_last.p.de; -+ AuDbg("%.*s, off%lld, i%lu, dt%d\n", -+ de->de_str.len, de->de_str.name, file->f_pos, -+ (unsigned long)de->de_ino, de->de_type); -+ err = filldir(dirent, de->de_str.name, de->de_str.len, -+ file->f_pos, de->de_ino, de->de_type); -+ if (unlikely(err)) { -+ AuTraceErr(err); -+ /* todo: ignore the error caused by udba? */ -+ /* return err; */ -+ return 0; -+ } -+ -+ l = calc_size(de->de_str.len); -+ vdir_cache->vd_last.p.deblk += l; -+ file->f_pos += l; -+ } -+ if (vdir_cache->vd_last.ul < vdir_cache->vd_nblk - 1) { -+ vdir_cache->vd_last.ul++; -+ vdir_cache->vd_last.p.deblk -+ = vdir_cache->vd_deblk[vdir_cache->vd_last.ul]; -+ file->f_pos = deblk_sz * vdir_cache->vd_last.ul; -+ continue; -+ } -+ break; -+ } -+ -+ /* smp_mb(); */ -+ return 0; -+} -diff -Nur linux-2.6.36.orig/fs/aufs/vfsub.c linux-2.6.36/fs/aufs/vfsub.c ---- linux-2.6.36.orig/fs/aufs/vfsub.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/vfsub.c 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,790 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * sub-routines for VFS -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include "aufs.h" -+ -+int vfsub_update_h_iattr(struct path *h_path, int *did) -+{ -+ int err; -+ struct kstat st; -+ struct super_block *h_sb; -+ -+ /* for remote fs, leave work for its getattr or d_revalidate */ -+ /* for bad i_attr fs, handle them in aufs_getattr() */ -+ /* still some fs may acquire i_mutex. we need to skip them */ -+ err = 0; -+ if (!did) -+ did = &err; -+ h_sb = h_path->dentry->d_sb; -+ *did = (!au_test_fs_remote(h_sb) && au_test_fs_refresh_iattr(h_sb)); -+ if (*did) -+ err = vfs_getattr(h_path->mnt, h_path->dentry, &st); -+ -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int au_conv_oflags(int flags) -+{ -+ int mask = 0; -+ -+#ifdef CONFIG_IMA -+ fmode_t fmode; -+ -+ /* mask = MAY_OPEN; */ -+ fmode = OPEN_FMODE(flags); -+ if (fmode & FMODE_READ) -+ mask |= MAY_READ; -+ if ((fmode & FMODE_WRITE) -+ || (flags & O_TRUNC)) -+ mask |= MAY_WRITE; -+ /* -+ * if (flags & O_APPEND) -+ * mask |= MAY_APPEND; -+ */ -+ if (flags & vfsub_fmode_to_uint(FMODE_EXEC)) -+ mask |= MAY_EXEC; -+ -+ AuDbg("flags 0x%x, mask 0x%x\n", flags, mask); -+#endif -+ -+ return mask; -+} -+ -+struct file *vfsub_dentry_open(struct path *path, int flags) -+{ -+ struct file *file; -+ int err; -+ -+ path_get(path); -+ file = dentry_open(path->dentry, path->mnt, -+ flags /* | vfsub_fmode_to_uint(FMODE_NONOTIFY) */, -+ current_cred()); -+ if (IS_ERR(file)) -+ goto out; -+ -+ err = ima_file_check(file, au_conv_oflags(flags)); -+ if (unlikely(err)) { -+ fput(file); -+ file = ERR_PTR(err); -+ } -+out: -+ return file; -+} -+ -+struct file *vfsub_filp_open(const char *path, int oflags, int mode) -+{ -+ struct file *file; -+ -+ file = filp_open(path, -+ oflags /* | vfsub_fmode_to_uint(FMODE_NONOTIFY) */, -+ mode); -+ if (IS_ERR(file)) -+ goto out; -+ vfsub_update_h_iattr(&file->f_path, /*did*/NULL); /*ignore*/ -+ -+out: -+ return file; -+} -+ -+int vfsub_kern_path(const char *name, unsigned int flags, struct path *path) -+{ -+ int err; -+ -+ err = kern_path(name, flags, path); -+ if (!err && path->dentry->d_inode) -+ vfsub_update_h_iattr(path, /*did*/NULL); /*ignore*/ -+ return err; -+} -+ -+struct dentry *vfsub_lookup_one_len(const char *name, struct dentry *parent, -+ int len) -+{ -+ struct path path = { -+ .mnt = NULL -+ }; -+ -+ /* VFS checks it too, but by WARN_ON_ONCE() */ -+ IMustLock(parent->d_inode); -+ -+ path.dentry = lookup_one_len(name, parent, len); -+ if (IS_ERR(path.dentry)) -+ goto out; -+ if (path.dentry->d_inode) -+ vfsub_update_h_iattr(&path, /*did*/NULL); /*ignore*/ -+ -+out: -+ AuTraceErrPtr(path.dentry); -+ return path.dentry; -+} -+ -+struct dentry *vfsub_lookup_hash(struct nameidata *nd) -+{ -+ struct path path = { -+ .mnt = nd->path.mnt -+ }; -+ -+ IMustLock(nd->path.dentry->d_inode); -+ -+ path.dentry = lookup_hash(nd); -+ if (IS_ERR(path.dentry)) -+ goto out; -+ if (path.dentry->d_inode) -+ vfsub_update_h_iattr(&path, /*did*/NULL); /*ignore*/ -+ -+out: -+ AuTraceErrPtr(path.dentry); -+ return path.dentry; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+struct dentry *vfsub_lock_rename(struct dentry *d1, struct au_hinode *hdir1, -+ struct dentry *d2, struct au_hinode *hdir2) -+{ -+ struct dentry *d; -+ -+ d = lock_rename(d1, d2); -+ au_hn_suspend(hdir1); -+ if (hdir1 != hdir2) -+ au_hn_suspend(hdir2); -+ -+ return d; -+} -+ -+void vfsub_unlock_rename(struct dentry *d1, struct au_hinode *hdir1, -+ struct dentry *d2, struct au_hinode *hdir2) -+{ -+ au_hn_resume(hdir1); -+ if (hdir1 != hdir2) -+ au_hn_resume(hdir2); -+ unlock_rename(d1, d2); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+int vfsub_create(struct inode *dir, struct path *path, int mode) -+{ -+ int err; -+ struct dentry *d; -+ -+ IMustLock(dir); -+ -+ d = path->dentry; -+ path->dentry = d->d_parent; -+ err = security_path_mknod(path, d, mode, 0); -+ path->dentry = d; -+ if (unlikely(err)) -+ goto out; -+ -+ if (au_test_fs_null_nd(dir->i_sb)) -+ err = vfs_create(dir, path->dentry, mode, NULL); -+ else { -+ struct nameidata h_nd; -+ -+ memset(&h_nd, 0, sizeof(h_nd)); -+ h_nd.flags = LOOKUP_CREATE; -+ h_nd.intent.open.flags = O_CREAT -+ | vfsub_fmode_to_uint(FMODE_READ); -+ h_nd.intent.open.create_mode = mode; -+ h_nd.path.dentry = path->dentry->d_parent; -+ h_nd.path.mnt = path->mnt; -+ path_get(&h_nd.path); -+ err = vfs_create(dir, path->dentry, mode, &h_nd); -+ path_put(&h_nd.path); -+ } -+ -+ if (!err) { -+ struct path tmp = *path; -+ int did; -+ -+ vfsub_update_h_iattr(&tmp, &did); -+ if (did) { -+ tmp.dentry = path->dentry->d_parent; -+ vfsub_update_h_iattr(&tmp, /*did*/NULL); -+ } -+ /*ignore*/ -+ } -+ -+out: -+ return err; -+} -+ -+int vfsub_symlink(struct inode *dir, struct path *path, const char *symname) -+{ -+ int err; -+ struct dentry *d; -+ -+ IMustLock(dir); -+ -+ d = path->dentry; -+ path->dentry = d->d_parent; -+ err = security_path_symlink(path, d, symname); -+ path->dentry = d; -+ if (unlikely(err)) -+ goto out; -+ -+ err = vfs_symlink(dir, path->dentry, symname); -+ if (!err) { -+ struct path tmp = *path; -+ int did; -+ -+ vfsub_update_h_iattr(&tmp, &did); -+ if (did) { -+ tmp.dentry = path->dentry->d_parent; -+ vfsub_update_h_iattr(&tmp, /*did*/NULL); -+ } -+ /*ignore*/ -+ } -+ -+out: -+ return err; -+} -+ -+int vfsub_mknod(struct inode *dir, struct path *path, int mode, dev_t dev) -+{ -+ int err; -+ struct dentry *d; -+ -+ IMustLock(dir); -+ -+ d = path->dentry; -+ path->dentry = d->d_parent; -+ err = security_path_mknod(path, d, mode, dev); -+ path->dentry = d; -+ if (unlikely(err)) -+ goto out; -+ -+ err = vfs_mknod(dir, path->dentry, mode, dev); -+ if (!err) { -+ struct path tmp = *path; -+ int did; -+ -+ vfsub_update_h_iattr(&tmp, &did); -+ if (did) { -+ tmp.dentry = path->dentry->d_parent; -+ vfsub_update_h_iattr(&tmp, /*did*/NULL); -+ } -+ /*ignore*/ -+ } -+ -+out: -+ return err; -+} -+ -+static int au_test_nlink(struct inode *inode) -+{ -+ const unsigned int link_max = UINT_MAX >> 1; /* rough margin */ -+ -+ if (!au_test_fs_no_limit_nlink(inode->i_sb) -+ || inode->i_nlink < link_max) -+ return 0; -+ return -EMLINK; -+} -+ -+int vfsub_link(struct dentry *src_dentry, struct inode *dir, struct path *path) -+{ -+ int err; -+ struct dentry *d; -+ -+ IMustLock(dir); -+ -+ err = au_test_nlink(src_dentry->d_inode); -+ if (unlikely(err)) -+ return err; -+ -+ d = path->dentry; -+ path->dentry = d->d_parent; -+ err = security_path_link(src_dentry, path, d); -+ path->dentry = d; -+ if (unlikely(err)) -+ goto out; -+ -+ err = vfs_link(src_dentry, dir, path->dentry); -+ if (!err) { -+ struct path tmp = *path; -+ int did; -+ -+ /* fuse has different memory inode for the same inumber */ -+ vfsub_update_h_iattr(&tmp, &did); -+ if (did) { -+ tmp.dentry = path->dentry->d_parent; -+ vfsub_update_h_iattr(&tmp, /*did*/NULL); -+ tmp.dentry = src_dentry; -+ vfsub_update_h_iattr(&tmp, /*did*/NULL); -+ } -+ /*ignore*/ -+ } -+ -+out: -+ return err; -+} -+ -+int vfsub_rename(struct inode *src_dir, struct dentry *src_dentry, -+ struct inode *dir, struct path *path) -+{ -+ int err; -+ struct path tmp = { -+ .mnt = path->mnt -+ }; -+ struct dentry *d; -+ -+ IMustLock(dir); -+ IMustLock(src_dir); -+ -+ d = path->dentry; -+ path->dentry = d->d_parent; -+ tmp.dentry = src_dentry->d_parent; -+ err = security_path_rename(&tmp, src_dentry, path, d); -+ path->dentry = d; -+ if (unlikely(err)) -+ goto out; -+ -+ err = vfs_rename(src_dir, src_dentry, dir, path->dentry); -+ if (!err) { -+ int did; -+ -+ tmp.dentry = d->d_parent; -+ vfsub_update_h_iattr(&tmp, &did); -+ if (did) { -+ tmp.dentry = src_dentry; -+ vfsub_update_h_iattr(&tmp, /*did*/NULL); -+ tmp.dentry = src_dentry->d_parent; -+ vfsub_update_h_iattr(&tmp, /*did*/NULL); -+ } -+ /*ignore*/ -+ } -+ -+out: -+ return err; -+} -+ -+int vfsub_mkdir(struct inode *dir, struct path *path, int mode) -+{ -+ int err; -+ struct dentry *d; -+ -+ IMustLock(dir); -+ -+ d = path->dentry; -+ path->dentry = d->d_parent; -+ err = security_path_mkdir(path, d, mode); -+ path->dentry = d; -+ if (unlikely(err)) -+ goto out; -+ -+ err = vfs_mkdir(dir, path->dentry, mode); -+ if (!err) { -+ struct path tmp = *path; -+ int did; -+ -+ vfsub_update_h_iattr(&tmp, &did); -+ if (did) { -+ tmp.dentry = path->dentry->d_parent; -+ vfsub_update_h_iattr(&tmp, /*did*/NULL); -+ } -+ /*ignore*/ -+ } -+ -+out: -+ return err; -+} -+ -+int vfsub_rmdir(struct inode *dir, struct path *path) -+{ -+ int err; -+ struct dentry *d; -+ -+ IMustLock(dir); -+ -+ d = path->dentry; -+ path->dentry = d->d_parent; -+ err = security_path_rmdir(path, d); -+ path->dentry = d; -+ if (unlikely(err)) -+ goto out; -+ -+ err = vfs_rmdir(dir, path->dentry); -+ if (!err) { -+ struct path tmp = { -+ .dentry = path->dentry->d_parent, -+ .mnt = path->mnt -+ }; -+ -+ vfsub_update_h_iattr(&tmp, /*did*/NULL); /*ignore*/ -+ } -+ -+out: -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+ssize_t vfsub_read_u(struct file *file, char __user *ubuf, size_t count, -+ loff_t *ppos) -+{ -+ ssize_t err; -+ -+ err = vfs_read(file, ubuf, count, ppos); -+ if (err >= 0) -+ vfsub_update_h_iattr(&file->f_path, /*did*/NULL); /*ignore*/ -+ return err; -+} -+ -+/* todo: kernel_read()? */ -+ssize_t vfsub_read_k(struct file *file, void *kbuf, size_t count, -+ loff_t *ppos) -+{ -+ ssize_t err; -+ mm_segment_t oldfs; -+ union { -+ void *k; -+ char __user *u; -+ } buf; -+ -+ buf.k = kbuf; -+ oldfs = get_fs(); -+ set_fs(KERNEL_DS); -+ err = vfsub_read_u(file, buf.u, count, ppos); -+ set_fs(oldfs); -+ return err; -+} -+ -+ssize_t vfsub_write_u(struct file *file, const char __user *ubuf, size_t count, -+ loff_t *ppos) -+{ -+ ssize_t err; -+ -+ err = vfs_write(file, ubuf, count, ppos); -+ if (err >= 0) -+ vfsub_update_h_iattr(&file->f_path, /*did*/NULL); /*ignore*/ -+ return err; -+} -+ -+ssize_t vfsub_write_k(struct file *file, void *kbuf, size_t count, loff_t *ppos) -+{ -+ ssize_t err; -+ mm_segment_t oldfs; -+ union { -+ void *k; -+ const char __user *u; -+ } buf; -+ -+ buf.k = kbuf; -+ oldfs = get_fs(); -+ set_fs(KERNEL_DS); -+ err = vfsub_write_u(file, buf.u, count, ppos); -+ set_fs(oldfs); -+ return err; -+} -+ -+int vfsub_flush(struct file *file, fl_owner_t id) -+{ -+ int err; -+ -+ err = 0; -+ if (file->f_op && file->f_op->flush) { -+ err = file->f_op->flush(file, id); -+ if (!err) -+ vfsub_update_h_iattr(&file->f_path, /*did*/NULL); -+ /*ignore*/ -+ } -+ return err; -+} -+ -+int vfsub_readdir(struct file *file, filldir_t filldir, void *arg) -+{ -+ int err; -+ -+ err = vfs_readdir(file, filldir, arg); -+ if (err >= 0) -+ vfsub_update_h_iattr(&file->f_path, /*did*/NULL); /*ignore*/ -+ return err; -+} -+ -+long vfsub_splice_to(struct file *in, loff_t *ppos, -+ struct pipe_inode_info *pipe, size_t len, -+ unsigned int flags) -+{ -+ long err; -+ -+ err = do_splice_to(in, ppos, pipe, len, flags); -+ file_accessed(in); -+ if (err >= 0) -+ vfsub_update_h_iattr(&in->f_path, /*did*/NULL); /*ignore*/ -+ return err; -+} -+ -+long vfsub_splice_from(struct pipe_inode_info *pipe, struct file *out, -+ loff_t *ppos, size_t len, unsigned int flags) -+{ -+ long err; -+ -+ err = do_splice_from(pipe, out, ppos, len, flags); -+ if (err >= 0) -+ vfsub_update_h_iattr(&out->f_path, /*did*/NULL); /*ignore*/ -+ return err; -+} -+ -+/* cf. open.c:do_sys_truncate() and do_sys_ftruncate() */ -+int vfsub_trunc(struct path *h_path, loff_t length, unsigned int attr, -+ struct file *h_file) -+{ -+ int err; -+ struct inode *h_inode; -+ -+ h_inode = h_path->dentry->d_inode; -+ if (!h_file) { -+ err = mnt_want_write(h_path->mnt); -+ if (err) -+ goto out; -+ err = inode_permission(h_inode, MAY_WRITE); -+ if (err) -+ goto out_mnt; -+ err = get_write_access(h_inode); -+ if (err) -+ goto out_mnt; -+ err = break_lease(h_inode, O_WRONLY); -+ if (err) -+ goto out_inode; -+ } -+ -+ err = locks_verify_truncate(h_inode, h_file, length); -+ if (!err) -+ err = security_path_truncate(h_path); -+ if (!err) -+ err = do_truncate(h_path->dentry, length, attr, h_file); -+ -+out_inode: -+ if (!h_file) -+ put_write_access(h_inode); -+out_mnt: -+ if (!h_file) -+ mnt_drop_write(h_path->mnt); -+out: -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+struct au_vfsub_mkdir_args { -+ int *errp; -+ struct inode *dir; -+ struct path *path; -+ int mode; -+}; -+ -+static void au_call_vfsub_mkdir(void *args) -+{ -+ struct au_vfsub_mkdir_args *a = args; -+ *a->errp = vfsub_mkdir(a->dir, a->path, a->mode); -+} -+ -+int vfsub_sio_mkdir(struct inode *dir, struct path *path, int mode) -+{ -+ int err, do_sio, wkq_err; -+ -+ do_sio = au_test_h_perm_sio(dir, MAY_EXEC | MAY_WRITE); -+ if (!do_sio) -+ err = vfsub_mkdir(dir, path, mode); -+ else { -+ struct au_vfsub_mkdir_args args = { -+ .errp = &err, -+ .dir = dir, -+ .path = path, -+ .mode = mode -+ }; -+ wkq_err = au_wkq_wait(au_call_vfsub_mkdir, &args); -+ if (unlikely(wkq_err)) -+ err = wkq_err; -+ } -+ -+ return err; -+} -+ -+struct au_vfsub_rmdir_args { -+ int *errp; -+ struct inode *dir; -+ struct path *path; -+}; -+ -+static void au_call_vfsub_rmdir(void *args) -+{ -+ struct au_vfsub_rmdir_args *a = args; -+ *a->errp = vfsub_rmdir(a->dir, a->path); -+} -+ -+int vfsub_sio_rmdir(struct inode *dir, struct path *path) -+{ -+ int err, do_sio, wkq_err; -+ -+ do_sio = au_test_h_perm_sio(dir, MAY_EXEC | MAY_WRITE); -+ if (!do_sio) -+ err = vfsub_rmdir(dir, path); -+ else { -+ struct au_vfsub_rmdir_args args = { -+ .errp = &err, -+ .dir = dir, -+ .path = path -+ }; -+ wkq_err = au_wkq_wait(au_call_vfsub_rmdir, &args); -+ if (unlikely(wkq_err)) -+ err = wkq_err; -+ } -+ -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+struct notify_change_args { -+ int *errp; -+ struct path *path; -+ struct iattr *ia; -+}; -+ -+static void call_notify_change(void *args) -+{ -+ struct notify_change_args *a = args; -+ struct inode *h_inode; -+ -+ h_inode = a->path->dentry->d_inode; -+ IMustLock(h_inode); -+ -+ *a->errp = -EPERM; -+ if (!IS_IMMUTABLE(h_inode) && !IS_APPEND(h_inode)) { -+ *a->errp = notify_change(a->path->dentry, a->ia); -+ if (!*a->errp) -+ vfsub_update_h_iattr(a->path, /*did*/NULL); /*ignore*/ -+ } -+ AuTraceErr(*a->errp); -+} -+ -+int vfsub_notify_change(struct path *path, struct iattr *ia) -+{ -+ int err; -+ struct notify_change_args args = { -+ .errp = &err, -+ .path = path, -+ .ia = ia -+ }; -+ -+ call_notify_change(&args); -+ -+ return err; -+} -+ -+int vfsub_sio_notify_change(struct path *path, struct iattr *ia) -+{ -+ int err, wkq_err; -+ struct notify_change_args args = { -+ .errp = &err, -+ .path = path, -+ .ia = ia -+ }; -+ -+ wkq_err = au_wkq_wait(call_notify_change, &args); -+ if (unlikely(wkq_err)) -+ err = wkq_err; -+ -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+struct unlink_args { -+ int *errp; -+ struct inode *dir; -+ struct path *path; -+}; -+ -+static void call_unlink(void *args) -+{ -+ struct unlink_args *a = args; -+ struct dentry *d = a->path->dentry; -+ struct inode *h_inode; -+ const int stop_sillyrename = (au_test_nfs(d->d_sb) -+ && atomic_read(&d->d_count) == 1); -+ -+ IMustLock(a->dir); -+ -+ a->path->dentry = d->d_parent; -+ *a->errp = security_path_unlink(a->path, d); -+ a->path->dentry = d; -+ if (unlikely(*a->errp)) -+ return; -+ -+ if (!stop_sillyrename) -+ dget(d); -+ h_inode = d->d_inode; -+ if (h_inode) -+ atomic_inc(&h_inode->i_count); -+ -+ *a->errp = vfs_unlink(a->dir, d); -+ if (!*a->errp) { -+ struct path tmp = { -+ .dentry = d->d_parent, -+ .mnt = a->path->mnt -+ }; -+ vfsub_update_h_iattr(&tmp, /*did*/NULL); /*ignore*/ -+ } -+ -+ if (!stop_sillyrename) -+ dput(d); -+ if (h_inode) -+ iput(h_inode); -+ -+ AuTraceErr(*a->errp); -+} -+ -+/* -+ * @dir: must be locked. -+ * @dentry: target dentry. -+ */ -+int vfsub_unlink(struct inode *dir, struct path *path, int force) -+{ -+ int err; -+ struct unlink_args args = { -+ .errp = &err, -+ .dir = dir, -+ .path = path -+ }; -+ -+ if (!force) -+ call_unlink(&args); -+ else { -+ int wkq_err; -+ -+ wkq_err = au_wkq_wait(call_unlink, &args); -+ if (unlikely(wkq_err)) -+ err = wkq_err; -+ } -+ -+ return err; -+} -diff -Nur linux-2.6.36.orig/fs/aufs/vfsub.h linux-2.6.36/fs/aufs/vfsub.h ---- linux-2.6.36.orig/fs/aufs/vfsub.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/vfsub.h 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,226 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * sub-routines for VFS -+ */ -+ -+#ifndef __AUFS_VFSUB_H__ -+#define __AUFS_VFSUB_H__ -+ -+#ifdef __KERNEL__ -+ -+#include -+#include -+#include "debug.h" -+ -+/* copied from linux/fs/internal.h */ -+DECLARE_BRLOCK(vfsmount_lock); -+extern void file_sb_list_del(struct file *f); -+ -+/* copied from linux/fs/file_table.c */ -+DECLARE_LGLOCK(files_lglock); -+#ifdef CONFIG_SMP -+/* -+ * These macros iterate all files on all CPUs for a given superblock. -+ * files_lglock must be held globally. -+ */ -+#define do_file_list_for_each_entry(__sb, __file) \ -+{ \ -+ int i; \ -+ for_each_possible_cpu(i) { \ -+ struct list_head *list; \ -+ list = per_cpu_ptr((__sb)->s_files, i); \ -+ list_for_each_entry((__file), list, f_u.fu_list) -+ -+#define while_file_list_for_each_entry \ -+ } \ -+} -+ -+#else -+ -+#define do_file_list_for_each_entry(__sb, __file) \ -+{ \ -+ struct list_head *list; \ -+ list = &(sb)->s_files; \ -+ list_for_each_entry((__file), list, f_u.fu_list) -+ -+#define while_file_list_for_each_entry \ -+} -+#endif -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* lock subclass for lower inode */ -+/* default MAX_LOCKDEP_SUBCLASSES(8) is not enough */ -+/* reduce? gave up. */ -+enum { -+ AuLsc_I_Begin = I_MUTEX_QUOTA, /* 4 */ -+ AuLsc_I_PARENT, /* lower inode, parent first */ -+ AuLsc_I_PARENT2, /* copyup dirs */ -+ AuLsc_I_PARENT3, /* copyup wh */ -+ AuLsc_I_CHILD, -+ AuLsc_I_CHILD2, -+ AuLsc_I_End -+}; -+ -+/* to debug easier, do not make them inlined functions */ -+#define MtxMustLock(mtx) AuDebugOn(!mutex_is_locked(mtx)) -+#define IMustLock(i) MtxMustLock(&(i)->i_mutex) -+ -+/* ---------------------------------------------------------------------- */ -+ -+static inline void vfsub_drop_nlink(struct inode *inode) -+{ -+ AuDebugOn(!inode->i_nlink); -+ drop_nlink(inode); -+} -+ -+static inline void vfsub_dead_dir(struct inode *inode) -+{ -+ AuDebugOn(!S_ISDIR(inode->i_mode)); -+ inode->i_flags |= S_DEAD; -+ clear_nlink(inode); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+int vfsub_update_h_iattr(struct path *h_path, int *did); -+struct file *vfsub_dentry_open(struct path *path, int flags); -+struct file *vfsub_filp_open(const char *path, int oflags, int mode); -+int vfsub_kern_path(const char *name, unsigned int flags, struct path *path); -+struct dentry *vfsub_lookup_one_len(const char *name, struct dentry *parent, -+ int len); -+struct dentry *vfsub_lookup_hash(struct nameidata *nd); -+ -+/* ---------------------------------------------------------------------- */ -+ -+struct au_hinode; -+struct dentry *vfsub_lock_rename(struct dentry *d1, struct au_hinode *hdir1, -+ struct dentry *d2, struct au_hinode *hdir2); -+void vfsub_unlock_rename(struct dentry *d1, struct au_hinode *hdir1, -+ struct dentry *d2, struct au_hinode *hdir2); -+ -+int vfsub_create(struct inode *dir, struct path *path, int mode); -+int vfsub_symlink(struct inode *dir, struct path *path, -+ const char *symname); -+int vfsub_mknod(struct inode *dir, struct path *path, int mode, dev_t dev); -+int vfsub_link(struct dentry *src_dentry, struct inode *dir, -+ struct path *path); -+int vfsub_rename(struct inode *src_hdir, struct dentry *src_dentry, -+ struct inode *hdir, struct path *path); -+int vfsub_mkdir(struct inode *dir, struct path *path, int mode); -+int vfsub_rmdir(struct inode *dir, struct path *path); -+ -+/* ---------------------------------------------------------------------- */ -+ -+ssize_t vfsub_read_u(struct file *file, char __user *ubuf, size_t count, -+ loff_t *ppos); -+ssize_t vfsub_read_k(struct file *file, void *kbuf, size_t count, -+ loff_t *ppos); -+ssize_t vfsub_write_u(struct file *file, const char __user *ubuf, size_t count, -+ loff_t *ppos); -+ssize_t vfsub_write_k(struct file *file, void *kbuf, size_t count, -+ loff_t *ppos); -+int vfsub_flush(struct file *file, fl_owner_t id); -+int vfsub_readdir(struct file *file, filldir_t filldir, void *arg); -+ -+static inline unsigned int vfsub_file_flags(struct file *file) -+{ -+ unsigned int flags; -+ -+ spin_lock(&file->f_lock); -+ flags = file->f_flags; -+ spin_unlock(&file->f_lock); -+ -+ return flags; -+} -+ -+static inline void vfsub_file_accessed(struct file *h_file) -+{ -+ file_accessed(h_file); -+ vfsub_update_h_iattr(&h_file->f_path, /*did*/NULL); /*ignore*/ -+} -+ -+static inline void vfsub_touch_atime(struct vfsmount *h_mnt, -+ struct dentry *h_dentry) -+{ -+ struct path h_path = { -+ .dentry = h_dentry, -+ .mnt = h_mnt -+ }; -+ touch_atime(h_mnt, h_dentry); -+ vfsub_update_h_iattr(&h_path, /*did*/NULL); /*ignore*/ -+} -+ -+long vfsub_splice_to(struct file *in, loff_t *ppos, -+ struct pipe_inode_info *pipe, size_t len, -+ unsigned int flags); -+long vfsub_splice_from(struct pipe_inode_info *pipe, struct file *out, -+ loff_t *ppos, size_t len, unsigned int flags); -+int vfsub_trunc(struct path *h_path, loff_t length, unsigned int attr, -+ struct file *h_file); -+ -+/* ---------------------------------------------------------------------- */ -+ -+static inline loff_t vfsub_llseek(struct file *file, loff_t offset, int origin) -+{ -+ loff_t err; -+ -+ err = vfs_llseek(file, offset, origin); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* dirty workaround for strict type of fmode_t */ -+union vfsub_fmu { -+ fmode_t fm; -+ unsigned int ui; -+}; -+ -+static inline unsigned int vfsub_fmode_to_uint(fmode_t fm) -+{ -+ union vfsub_fmu u = { -+ .fm = fm -+ }; -+ -+ BUILD_BUG_ON(sizeof(u.fm) != sizeof(u.ui)); -+ -+ return u.ui; -+} -+ -+static inline fmode_t vfsub_uint_to_fmode(unsigned int ui) -+{ -+ union vfsub_fmu u = { -+ .ui = ui -+ }; -+ -+ return u.fm; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+int vfsub_sio_mkdir(struct inode *dir, struct path *path, int mode); -+int vfsub_sio_rmdir(struct inode *dir, struct path *path); -+int vfsub_sio_notify_change(struct path *path, struct iattr *ia); -+int vfsub_notify_change(struct path *path, struct iattr *ia); -+int vfsub_unlink(struct inode *dir, struct path *path, int force); -+ -+#endif /* __KERNEL__ */ -+#endif /* __AUFS_VFSUB_H__ */ -diff -Nur linux-2.6.36.orig/fs/aufs/wbr_policy.c linux-2.6.36/fs/aufs/wbr_policy.c ---- linux-2.6.36.orig/fs/aufs/wbr_policy.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/wbr_policy.c 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,700 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * policies for selecting one among multiple writable branches -+ */ -+ -+#include -+#include "aufs.h" -+ -+/* subset of cpup_attr() */ -+static noinline_for_stack -+int au_cpdown_attr(struct path *h_path, struct dentry *h_src) -+{ -+ int err, sbits; -+ struct iattr ia; -+ struct inode *h_isrc; -+ -+ h_isrc = h_src->d_inode; -+ ia.ia_valid = ATTR_FORCE | ATTR_MODE | ATTR_UID | ATTR_GID; -+ ia.ia_mode = h_isrc->i_mode; -+ ia.ia_uid = h_isrc->i_uid; -+ ia.ia_gid = h_isrc->i_gid; -+ sbits = !!(ia.ia_mode & (S_ISUID | S_ISGID)); -+ au_cpup_attr_flags(h_path->dentry->d_inode, h_isrc); -+ err = vfsub_sio_notify_change(h_path, &ia); -+ -+ /* is this nfs only? */ -+ if (!err && sbits && au_test_nfs(h_path->dentry->d_sb)) { -+ ia.ia_valid = ATTR_FORCE | ATTR_MODE; -+ ia.ia_mode = h_isrc->i_mode; -+ err = vfsub_sio_notify_change(h_path, &ia); -+ } -+ -+ return err; -+} -+ -+#define AuCpdown_PARENT_OPQ 1 -+#define AuCpdown_WHED (1 << 1) -+#define AuCpdown_MADE_DIR (1 << 2) -+#define AuCpdown_DIROPQ (1 << 3) -+#define au_ftest_cpdown(flags, name) ((flags) & AuCpdown_##name) -+#define au_fset_cpdown(flags, name) \ -+ do { (flags) |= AuCpdown_##name; } while (0) -+#define au_fclr_cpdown(flags, name) \ -+ do { (flags) &= ~AuCpdown_##name; } while (0) -+ -+struct au_cpdown_dir_args { -+ struct dentry *parent; -+ unsigned int flags; -+}; -+ -+static int au_cpdown_dir_opq(struct dentry *dentry, aufs_bindex_t bdst, -+ struct au_cpdown_dir_args *a) -+{ -+ int err; -+ struct dentry *opq_dentry; -+ -+ opq_dentry = au_diropq_create(dentry, bdst); -+ err = PTR_ERR(opq_dentry); -+ if (IS_ERR(opq_dentry)) -+ goto out; -+ dput(opq_dentry); -+ au_fset_cpdown(a->flags, DIROPQ); -+ -+out: -+ return err; -+} -+ -+static int au_cpdown_dir_wh(struct dentry *dentry, struct dentry *h_parent, -+ struct inode *dir, aufs_bindex_t bdst) -+{ -+ int err; -+ struct path h_path; -+ struct au_branch *br; -+ -+ br = au_sbr(dentry->d_sb, bdst); -+ h_path.dentry = au_wh_lkup(h_parent, &dentry->d_name, br); -+ err = PTR_ERR(h_path.dentry); -+ if (IS_ERR(h_path.dentry)) -+ goto out; -+ -+ err = 0; -+ if (h_path.dentry->d_inode) { -+ h_path.mnt = br->br_mnt; -+ err = au_wh_unlink_dentry(au_h_iptr(dir, bdst), &h_path, -+ dentry); -+ } -+ dput(h_path.dentry); -+ -+out: -+ return err; -+} -+ -+static int au_cpdown_dir(struct dentry *dentry, aufs_bindex_t bdst, -+ struct dentry *h_parent, void *arg) -+{ -+ int err, rerr; -+ aufs_bindex_t bopq, bstart; -+ struct path h_path; -+ struct dentry *parent; -+ struct inode *h_dir, *h_inode, *inode, *dir; -+ struct au_cpdown_dir_args *args = arg; -+ -+ bstart = au_dbstart(dentry); -+ /* dentry is di-locked */ -+ parent = dget_parent(dentry); -+ dir = parent->d_inode; -+ h_dir = h_parent->d_inode; -+ AuDebugOn(h_dir != au_h_iptr(dir, bdst)); -+ IMustLock(h_dir); -+ -+ err = au_lkup_neg(dentry, bdst); -+ if (unlikely(err < 0)) -+ goto out; -+ h_path.dentry = au_h_dptr(dentry, bdst); -+ h_path.mnt = au_sbr_mnt(dentry->d_sb, bdst); -+ err = vfsub_sio_mkdir(au_h_iptr(dir, bdst), &h_path, -+ S_IRWXU | S_IRUGO | S_IXUGO); -+ if (unlikely(err)) -+ goto out_put; -+ au_fset_cpdown(args->flags, MADE_DIR); -+ -+ bopq = au_dbdiropq(dentry); -+ au_fclr_cpdown(args->flags, WHED); -+ au_fclr_cpdown(args->flags, DIROPQ); -+ if (au_dbwh(dentry) == bdst) -+ au_fset_cpdown(args->flags, WHED); -+ if (!au_ftest_cpdown(args->flags, PARENT_OPQ) && bopq <= bdst) -+ au_fset_cpdown(args->flags, PARENT_OPQ); -+ h_inode = h_path.dentry->d_inode; -+ mutex_lock_nested(&h_inode->i_mutex, AuLsc_I_CHILD); -+ if (au_ftest_cpdown(args->flags, WHED)) { -+ err = au_cpdown_dir_opq(dentry, bdst, args); -+ if (unlikely(err)) { -+ mutex_unlock(&h_inode->i_mutex); -+ goto out_dir; -+ } -+ } -+ -+ err = au_cpdown_attr(&h_path, au_h_dptr(dentry, bstart)); -+ mutex_unlock(&h_inode->i_mutex); -+ if (unlikely(err)) -+ goto out_opq; -+ -+ if (au_ftest_cpdown(args->flags, WHED)) { -+ err = au_cpdown_dir_wh(dentry, h_parent, dir, bdst); -+ if (unlikely(err)) -+ goto out_opq; -+ } -+ -+ inode = dentry->d_inode; -+ if (au_ibend(inode) < bdst) -+ au_set_ibend(inode, bdst); -+ au_set_h_iptr(inode, bdst, au_igrab(h_inode), -+ au_hi_flags(inode, /*isdir*/1)); -+ goto out; /* success */ -+ -+ /* revert */ -+out_opq: -+ if (au_ftest_cpdown(args->flags, DIROPQ)) { -+ mutex_lock_nested(&h_inode->i_mutex, AuLsc_I_CHILD); -+ rerr = au_diropq_remove(dentry, bdst); -+ mutex_unlock(&h_inode->i_mutex); -+ if (unlikely(rerr)) { -+ AuIOErr("failed removing diropq for %.*s b%d (%d)\n", -+ AuDLNPair(dentry), bdst, rerr); -+ err = -EIO; -+ goto out; -+ } -+ } -+out_dir: -+ if (au_ftest_cpdown(args->flags, MADE_DIR)) { -+ rerr = vfsub_sio_rmdir(au_h_iptr(dir, bdst), &h_path); -+ if (unlikely(rerr)) { -+ AuIOErr("failed removing %.*s b%d (%d)\n", -+ AuDLNPair(dentry), bdst, rerr); -+ err = -EIO; -+ } -+ } -+out_put: -+ au_set_h_dptr(dentry, bdst, NULL); -+ if (au_dbend(dentry) == bdst) -+ au_update_dbend(dentry); -+out: -+ dput(parent); -+ return err; -+} -+ -+int au_cpdown_dirs(struct dentry *dentry, aufs_bindex_t bdst) -+{ -+ int err; -+ struct au_cpdown_dir_args args = { -+ .parent = dget_parent(dentry), -+ .flags = 0 -+ }; -+ -+ err = au_cp_dirs(dentry, bdst, au_cpdown_dir, &args); -+ dput(args.parent); -+ -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* policies for create */ -+ -+static int au_wbr_nonopq(struct dentry *dentry, aufs_bindex_t bindex) -+{ -+ int err, i, j, ndentry; -+ aufs_bindex_t bopq; -+ struct au_dcsub_pages dpages; -+ struct au_dpage *dpage; -+ struct dentry **dentries, *parent, *d; -+ -+ err = au_dpages_init(&dpages, GFP_NOFS); -+ if (unlikely(err)) -+ goto out; -+ parent = dget_parent(dentry); -+ err = au_dcsub_pages_rev_aufs(&dpages, parent, /*do_include*/0); -+ if (unlikely(err)) -+ goto out_free; -+ -+ err = bindex; -+ for (i = 0; i < dpages.ndpage; i++) { -+ dpage = dpages.dpages + i; -+ dentries = dpage->dentries; -+ ndentry = dpage->ndentry; -+ for (j = 0; j < ndentry; j++) { -+ d = dentries[j]; -+ di_read_lock_parent2(d, !AuLock_IR); -+ bopq = au_dbdiropq(d); -+ di_read_unlock(d, !AuLock_IR); -+ if (bopq >= 0 && bopq < err) -+ err = bopq; -+ } -+ } -+ -+out_free: -+ dput(parent); -+ au_dpages_free(&dpages); -+out: -+ return err; -+} -+ -+static int au_wbr_bu(struct super_block *sb, aufs_bindex_t bindex) -+{ -+ for (; bindex >= 0; bindex--) -+ if (!au_br_rdonly(au_sbr(sb, bindex))) -+ return bindex; -+ return -EROFS; -+} -+ -+/* top down parent */ -+static int au_wbr_create_tdp(struct dentry *dentry, int isdir __maybe_unused) -+{ -+ int err; -+ aufs_bindex_t bstart, bindex; -+ struct super_block *sb; -+ struct dentry *parent, *h_parent; -+ -+ sb = dentry->d_sb; -+ bstart = au_dbstart(dentry); -+ err = bstart; -+ if (!au_br_rdonly(au_sbr(sb, bstart))) -+ goto out; -+ -+ err = -EROFS; -+ parent = dget_parent(dentry); -+ for (bindex = au_dbstart(parent); bindex < bstart; bindex++) { -+ h_parent = au_h_dptr(parent, bindex); -+ if (!h_parent || !h_parent->d_inode) -+ continue; -+ -+ if (!au_br_rdonly(au_sbr(sb, bindex))) { -+ err = bindex; -+ break; -+ } -+ } -+ dput(parent); -+ -+ /* bottom up here */ -+ if (unlikely(err < 0)) { -+ err = au_wbr_bu(sb, bstart - 1); -+ if (err >= 0) -+ err = au_wbr_nonopq(dentry, err); -+ } -+ -+out: -+ AuDbg("b%d\n", err); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* an exception for the policy other than tdp */ -+static int au_wbr_create_exp(struct dentry *dentry) -+{ -+ int err; -+ aufs_bindex_t bwh, bdiropq; -+ struct dentry *parent; -+ -+ err = -1; -+ bwh = au_dbwh(dentry); -+ parent = dget_parent(dentry); -+ bdiropq = au_dbdiropq(parent); -+ if (bwh >= 0) { -+ if (bdiropq >= 0) -+ err = min(bdiropq, bwh); -+ else -+ err = bwh; -+ AuDbg("%d\n", err); -+ } else if (bdiropq >= 0) { -+ err = bdiropq; -+ AuDbg("%d\n", err); -+ } -+ dput(parent); -+ -+ if (err >= 0) -+ err = au_wbr_nonopq(dentry, err); -+ -+ if (err >= 0 && au_br_rdonly(au_sbr(dentry->d_sb, err))) -+ err = -1; -+ -+ AuDbg("%d\n", err); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* round robin */ -+static int au_wbr_create_init_rr(struct super_block *sb) -+{ -+ int err; -+ -+ err = au_wbr_bu(sb, au_sbend(sb)); -+ atomic_set(&au_sbi(sb)->si_wbr_rr_next, -err); /* less important */ -+ /* smp_mb(); */ -+ -+ AuDbg("b%d\n", err); -+ return err; -+} -+ -+static int au_wbr_create_rr(struct dentry *dentry, int isdir) -+{ -+ int err, nbr; -+ unsigned int u; -+ aufs_bindex_t bindex, bend; -+ struct super_block *sb; -+ atomic_t *next; -+ -+ err = au_wbr_create_exp(dentry); -+ if (err >= 0) -+ goto out; -+ -+ sb = dentry->d_sb; -+ next = &au_sbi(sb)->si_wbr_rr_next; -+ bend = au_sbend(sb); -+ nbr = bend + 1; -+ for (bindex = 0; bindex <= bend; bindex++) { -+ if (!isdir) { -+ err = atomic_dec_return(next) + 1; -+ /* modulo for 0 is meaningless */ -+ if (unlikely(!err)) -+ err = atomic_dec_return(next) + 1; -+ } else -+ err = atomic_read(next); -+ AuDbg("%d\n", err); -+ u = err; -+ err = u % nbr; -+ AuDbg("%d\n", err); -+ if (!au_br_rdonly(au_sbr(sb, err))) -+ break; -+ err = -EROFS; -+ } -+ -+ if (err >= 0) -+ err = au_wbr_nonopq(dentry, err); -+ -+out: -+ AuDbg("%d\n", err); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* most free space */ -+static void au_mfs(struct dentry *dentry) -+{ -+ struct super_block *sb; -+ struct au_branch *br; -+ struct au_wbr_mfs *mfs; -+ aufs_bindex_t bindex, bend; -+ int err; -+ unsigned long long b, bavail; -+ struct path h_path; -+ /* reduce the stack usage */ -+ struct kstatfs *st; -+ -+ st = kmalloc(sizeof(*st), GFP_NOFS); -+ if (unlikely(!st)) { -+ AuWarn1("failed updating mfs(%d), ignored\n", -ENOMEM); -+ return; -+ } -+ -+ bavail = 0; -+ sb = dentry->d_sb; -+ mfs = &au_sbi(sb)->si_wbr_mfs; -+ MtxMustLock(&mfs->mfs_lock); -+ mfs->mfs_bindex = -EROFS; -+ mfs->mfsrr_bytes = 0; -+ bend = au_sbend(sb); -+ for (bindex = 0; bindex <= bend; bindex++) { -+ br = au_sbr(sb, bindex); -+ if (au_br_rdonly(br)) -+ continue; -+ -+ /* sb->s_root for NFS is unreliable */ -+ h_path.mnt = br->br_mnt; -+ h_path.dentry = h_path.mnt->mnt_root; -+ err = vfs_statfs(&h_path, st); -+ if (unlikely(err)) { -+ AuWarn1("failed statfs, b%d, %d\n", bindex, err); -+ continue; -+ } -+ -+ /* when the available size is equal, select the lower one */ -+ BUILD_BUG_ON(sizeof(b) < sizeof(st->f_bavail) -+ || sizeof(b) < sizeof(st->f_bsize)); -+ b = st->f_bavail * st->f_bsize; -+ br->br_wbr->wbr_bytes = b; -+ if (b >= bavail) { -+ bavail = b; -+ mfs->mfs_bindex = bindex; -+ mfs->mfs_jiffy = jiffies; -+ } -+ } -+ -+ mfs->mfsrr_bytes = bavail; -+ AuDbg("b%d\n", mfs->mfs_bindex); -+ kfree(st); -+} -+ -+static int au_wbr_create_mfs(struct dentry *dentry, int isdir __maybe_unused) -+{ -+ int err; -+ struct super_block *sb; -+ struct au_wbr_mfs *mfs; -+ -+ err = au_wbr_create_exp(dentry); -+ if (err >= 0) -+ goto out; -+ -+ sb = dentry->d_sb; -+ mfs = &au_sbi(sb)->si_wbr_mfs; -+ mutex_lock(&mfs->mfs_lock); -+ if (time_after(jiffies, mfs->mfs_jiffy + mfs->mfs_expire) -+ || mfs->mfs_bindex < 0 -+ || au_br_rdonly(au_sbr(sb, mfs->mfs_bindex))) -+ au_mfs(dentry); -+ mutex_unlock(&mfs->mfs_lock); -+ err = mfs->mfs_bindex; -+ -+ if (err >= 0) -+ err = au_wbr_nonopq(dentry, err); -+ -+out: -+ AuDbg("b%d\n", err); -+ return err; -+} -+ -+static int au_wbr_create_init_mfs(struct super_block *sb) -+{ -+ struct au_wbr_mfs *mfs; -+ -+ mfs = &au_sbi(sb)->si_wbr_mfs; -+ mutex_init(&mfs->mfs_lock); -+ mfs->mfs_jiffy = 0; -+ mfs->mfs_bindex = -EROFS; -+ -+ return 0; -+} -+ -+static int au_wbr_create_fin_mfs(struct super_block *sb __maybe_unused) -+{ -+ mutex_destroy(&au_sbi(sb)->si_wbr_mfs.mfs_lock); -+ return 0; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* most free space and then round robin */ -+static int au_wbr_create_mfsrr(struct dentry *dentry, int isdir) -+{ -+ int err; -+ struct au_wbr_mfs *mfs; -+ -+ err = au_wbr_create_mfs(dentry, isdir); -+ if (err >= 0) { -+ mfs = &au_sbi(dentry->d_sb)->si_wbr_mfs; -+ mutex_lock(&mfs->mfs_lock); -+ if (mfs->mfsrr_bytes < mfs->mfsrr_watermark) -+ err = au_wbr_create_rr(dentry, isdir); -+ mutex_unlock(&mfs->mfs_lock); -+ } -+ -+ AuDbg("b%d\n", err); -+ return err; -+} -+ -+static int au_wbr_create_init_mfsrr(struct super_block *sb) -+{ -+ int err; -+ -+ au_wbr_create_init_mfs(sb); /* ignore */ -+ err = au_wbr_create_init_rr(sb); -+ -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* top down parent and most free space */ -+static int au_wbr_create_pmfs(struct dentry *dentry, int isdir) -+{ -+ int err, e2; -+ unsigned long long b; -+ aufs_bindex_t bindex, bstart, bend; -+ struct super_block *sb; -+ struct dentry *parent, *h_parent; -+ struct au_branch *br; -+ -+ err = au_wbr_create_tdp(dentry, isdir); -+ if (unlikely(err < 0)) -+ goto out; -+ parent = dget_parent(dentry); -+ bstart = au_dbstart(parent); -+ bend = au_dbtaildir(parent); -+ if (bstart == bend) -+ goto out_parent; /* success */ -+ -+ e2 = au_wbr_create_mfs(dentry, isdir); -+ if (e2 < 0) -+ goto out_parent; /* success */ -+ -+ /* when the available size is equal, select upper one */ -+ sb = dentry->d_sb; -+ br = au_sbr(sb, err); -+ b = br->br_wbr->wbr_bytes; -+ AuDbg("b%d, %llu\n", err, b); -+ -+ for (bindex = bstart; bindex <= bend; bindex++) { -+ h_parent = au_h_dptr(parent, bindex); -+ if (!h_parent || !h_parent->d_inode) -+ continue; -+ -+ br = au_sbr(sb, bindex); -+ if (!au_br_rdonly(br) && br->br_wbr->wbr_bytes > b) { -+ b = br->br_wbr->wbr_bytes; -+ err = bindex; -+ AuDbg("b%d, %llu\n", err, b); -+ } -+ } -+ -+ if (err >= 0) -+ err = au_wbr_nonopq(dentry, err); -+ -+out_parent: -+ dput(parent); -+out: -+ AuDbg("b%d\n", err); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* policies for copyup */ -+ -+/* top down parent */ -+static int au_wbr_copyup_tdp(struct dentry *dentry) -+{ -+ return au_wbr_create_tdp(dentry, /*isdir, anything is ok*/0); -+} -+ -+/* bottom up parent */ -+static int au_wbr_copyup_bup(struct dentry *dentry) -+{ -+ int err; -+ aufs_bindex_t bindex, bstart; -+ struct dentry *parent, *h_parent; -+ struct super_block *sb; -+ -+ err = -EROFS; -+ sb = dentry->d_sb; -+ parent = dget_parent(dentry); -+ bstart = au_dbstart(parent); -+ for (bindex = au_dbstart(dentry); bindex >= bstart; bindex--) { -+ h_parent = au_h_dptr(parent, bindex); -+ if (!h_parent || !h_parent->d_inode) -+ continue; -+ -+ if (!au_br_rdonly(au_sbr(sb, bindex))) { -+ err = bindex; -+ break; -+ } -+ } -+ dput(parent); -+ -+ /* bottom up here */ -+ if (unlikely(err < 0)) -+ err = au_wbr_bu(sb, bstart - 1); -+ -+ AuDbg("b%d\n", err); -+ return err; -+} -+ -+/* bottom up */ -+static int au_wbr_copyup_bu(struct dentry *dentry) -+{ -+ int err; -+ aufs_bindex_t bstart; -+ -+ bstart = au_dbstart(dentry); -+ err = au_wbr_bu(dentry->d_sb, bstart); -+ AuDbg("b%d\n", err); -+ if (err > bstart) -+ err = au_wbr_nonopq(dentry, err); -+ -+ AuDbg("b%d\n", err); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+struct au_wbr_copyup_operations au_wbr_copyup_ops[] = { -+ [AuWbrCopyup_TDP] = { -+ .copyup = au_wbr_copyup_tdp -+ }, -+ [AuWbrCopyup_BUP] = { -+ .copyup = au_wbr_copyup_bup -+ }, -+ [AuWbrCopyup_BU] = { -+ .copyup = au_wbr_copyup_bu -+ } -+}; -+ -+struct au_wbr_create_operations au_wbr_create_ops[] = { -+ [AuWbrCreate_TDP] = { -+ .create = au_wbr_create_tdp -+ }, -+ [AuWbrCreate_RR] = { -+ .create = au_wbr_create_rr, -+ .init = au_wbr_create_init_rr -+ }, -+ [AuWbrCreate_MFS] = { -+ .create = au_wbr_create_mfs, -+ .init = au_wbr_create_init_mfs, -+ .fin = au_wbr_create_fin_mfs -+ }, -+ [AuWbrCreate_MFSV] = { -+ .create = au_wbr_create_mfs, -+ .init = au_wbr_create_init_mfs, -+ .fin = au_wbr_create_fin_mfs -+ }, -+ [AuWbrCreate_MFSRR] = { -+ .create = au_wbr_create_mfsrr, -+ .init = au_wbr_create_init_mfsrr, -+ .fin = au_wbr_create_fin_mfs -+ }, -+ [AuWbrCreate_MFSRRV] = { -+ .create = au_wbr_create_mfsrr, -+ .init = au_wbr_create_init_mfsrr, -+ .fin = au_wbr_create_fin_mfs -+ }, -+ [AuWbrCreate_PMFS] = { -+ .create = au_wbr_create_pmfs, -+ .init = au_wbr_create_init_mfs, -+ .fin = au_wbr_create_fin_mfs -+ }, -+ [AuWbrCreate_PMFSV] = { -+ .create = au_wbr_create_pmfs, -+ .init = au_wbr_create_init_mfs, -+ .fin = au_wbr_create_fin_mfs -+ } -+}; -diff -Nur linux-2.6.36.orig/fs/aufs/whout.c linux-2.6.36/fs/aufs/whout.c ---- linux-2.6.36.orig/fs/aufs/whout.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/whout.c 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,1062 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * whiteout for logical deletion and opaque directory -+ */ -+ -+#include -+#include "aufs.h" -+ -+#define WH_MASK S_IRUGO -+ -+/* -+ * If a directory contains this file, then it is opaque. We start with the -+ * .wh. flag so that it is blocked by lookup. -+ */ -+static struct qstr diropq_name = { -+ .name = AUFS_WH_DIROPQ, -+ .len = sizeof(AUFS_WH_DIROPQ) - 1 -+}; -+ -+/* -+ * generate whiteout name, which is NOT terminated by NULL. -+ * @name: original d_name.name -+ * @len: original d_name.len -+ * @wh: whiteout qstr -+ * returns zero when succeeds, otherwise error. -+ * succeeded value as wh->name should be freed by kfree(). -+ */ -+int au_wh_name_alloc(struct qstr *wh, const struct qstr *name) -+{ -+ char *p; -+ -+ if (unlikely(name->len > PATH_MAX - AUFS_WH_PFX_LEN)) -+ return -ENAMETOOLONG; -+ -+ wh->len = name->len + AUFS_WH_PFX_LEN; -+ p = kmalloc(wh->len, GFP_NOFS); -+ wh->name = p; -+ if (p) { -+ memcpy(p, AUFS_WH_PFX, AUFS_WH_PFX_LEN); -+ memcpy(p + AUFS_WH_PFX_LEN, name->name, name->len); -+ /* smp_mb(); */ -+ return 0; -+ } -+ return -ENOMEM; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * test if the @wh_name exists under @h_parent. -+ * @try_sio specifies the necessary of super-io. -+ */ -+int au_wh_test(struct dentry *h_parent, struct qstr *wh_name, -+ struct au_branch *br, int try_sio) -+{ -+ int err; -+ struct dentry *wh_dentry; -+ -+ if (!try_sio) -+ wh_dentry = au_lkup_one(wh_name, h_parent, br, /*nd*/NULL); -+ else -+ wh_dentry = au_sio_lkup_one(wh_name, h_parent, br); -+ err = PTR_ERR(wh_dentry); -+ if (IS_ERR(wh_dentry)) -+ goto out; -+ -+ err = 0; -+ if (!wh_dentry->d_inode) -+ goto out_wh; /* success */ -+ -+ err = 1; -+ if (S_ISREG(wh_dentry->d_inode->i_mode)) -+ goto out_wh; /* success */ -+ -+ err = -EIO; -+ AuIOErr("%.*s Invalid whiteout entry type 0%o.\n", -+ AuDLNPair(wh_dentry), wh_dentry->d_inode->i_mode); -+ -+out_wh: -+ dput(wh_dentry); -+out: -+ return err; -+} -+ -+/* -+ * test if the @h_dentry sets opaque or not. -+ */ -+int au_diropq_test(struct dentry *h_dentry, struct au_branch *br) -+{ -+ int err; -+ struct inode *h_dir; -+ -+ h_dir = h_dentry->d_inode; -+ err = au_wh_test(h_dentry, &diropq_name, br, -+ au_test_h_perm_sio(h_dir, MAY_EXEC)); -+ return err; -+} -+ -+/* -+ * returns a negative dentry whose name is unique and temporary. -+ */ -+struct dentry *au_whtmp_lkup(struct dentry *h_parent, struct au_branch *br, -+ struct qstr *prefix) -+{ -+ struct dentry *dentry; -+ int i; -+ char defname[NAME_MAX - AUFS_MAX_NAMELEN + DNAME_INLINE_LEN_MIN + 1], -+ *name, *p; -+ /* strict atomic_t is unnecessary here */ -+ static unsigned short cnt; -+ struct qstr qs; -+ -+ BUILD_BUG_ON(sizeof(cnt) * 2 > AUFS_WH_TMP_LEN); -+ -+ name = defname; -+ qs.len = sizeof(defname) - DNAME_INLINE_LEN_MIN + prefix->len - 1; -+ if (unlikely(prefix->len > DNAME_INLINE_LEN_MIN)) { -+ dentry = ERR_PTR(-ENAMETOOLONG); -+ if (unlikely(qs.len > NAME_MAX)) -+ goto out; -+ dentry = ERR_PTR(-ENOMEM); -+ name = kmalloc(qs.len + 1, GFP_NOFS); -+ if (unlikely(!name)) -+ goto out; -+ } -+ -+ /* doubly whiteout-ed */ -+ memcpy(name, AUFS_WH_PFX AUFS_WH_PFX, AUFS_WH_PFX_LEN * 2); -+ p = name + AUFS_WH_PFX_LEN * 2; -+ memcpy(p, prefix->name, prefix->len); -+ p += prefix->len; -+ *p++ = '.'; -+ AuDebugOn(name + qs.len + 1 - p <= AUFS_WH_TMP_LEN); -+ -+ qs.name = name; -+ for (i = 0; i < 3; i++) { -+ sprintf(p, "%.*x", AUFS_WH_TMP_LEN, cnt++); -+ dentry = au_sio_lkup_one(&qs, h_parent, br); -+ if (IS_ERR(dentry) || !dentry->d_inode) -+ goto out_name; -+ dput(dentry); -+ } -+ /* pr_warning("could not get random name\n"); */ -+ dentry = ERR_PTR(-EEXIST); -+ AuDbg("%.*s\n", AuLNPair(&qs)); -+ BUG(); -+ -+out_name: -+ if (name != defname) -+ kfree(name); -+out: -+ AuTraceErrPtr(dentry); -+ return dentry; -+} -+ -+/* -+ * rename the @h_dentry on @br to the whiteouted temporary name. -+ */ -+int au_whtmp_ren(struct dentry *h_dentry, struct au_branch *br) -+{ -+ int err; -+ struct path h_path = { -+ .mnt = br->br_mnt -+ }; -+ struct inode *h_dir; -+ struct dentry *h_parent; -+ -+ h_parent = h_dentry->d_parent; /* dir inode is locked */ -+ h_dir = h_parent->d_inode; -+ IMustLock(h_dir); -+ -+ h_path.dentry = au_whtmp_lkup(h_parent, br, &h_dentry->d_name); -+ err = PTR_ERR(h_path.dentry); -+ if (IS_ERR(h_path.dentry)) -+ goto out; -+ -+ /* under the same dir, no need to lock_rename() */ -+ err = vfsub_rename(h_dir, h_dentry, h_dir, &h_path); -+ AuTraceErr(err); -+ dput(h_path.dentry); -+ -+out: -+ AuTraceErr(err); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+/* -+ * functions for removing a whiteout -+ */ -+ -+static int do_unlink_wh(struct inode *h_dir, struct path *h_path) -+{ -+ int force; -+ -+ /* -+ * forces superio when the dir has a sticky bit. -+ * this may be a violation of unix fs semantics. -+ */ -+ force = (h_dir->i_mode & S_ISVTX) -+ && h_path->dentry->d_inode->i_uid != current_fsuid(); -+ return vfsub_unlink(h_dir, h_path, force); -+} -+ -+int au_wh_unlink_dentry(struct inode *h_dir, struct path *h_path, -+ struct dentry *dentry) -+{ -+ int err; -+ -+ err = do_unlink_wh(h_dir, h_path); -+ if (!err && dentry) -+ au_set_dbwh(dentry, -1); -+ -+ return err; -+} -+ -+static int unlink_wh_name(struct dentry *h_parent, struct qstr *wh, -+ struct au_branch *br) -+{ -+ int err; -+ struct path h_path = { -+ .mnt = br->br_mnt -+ }; -+ -+ err = 0; -+ h_path.dentry = au_lkup_one(wh, h_parent, br, /*nd*/NULL); -+ if (IS_ERR(h_path.dentry)) -+ err = PTR_ERR(h_path.dentry); -+ else { -+ if (h_path.dentry->d_inode -+ && S_ISREG(h_path.dentry->d_inode->i_mode)) -+ err = do_unlink_wh(h_parent->d_inode, &h_path); -+ dput(h_path.dentry); -+ } -+ -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+/* -+ * initialize/clean whiteout for a branch -+ */ -+ -+static void au_wh_clean(struct inode *h_dir, struct path *whpath, -+ const int isdir) -+{ -+ int err; -+ -+ if (!whpath->dentry->d_inode) -+ return; -+ -+ err = mnt_want_write(whpath->mnt); -+ if (!err) { -+ if (isdir) -+ err = vfsub_rmdir(h_dir, whpath); -+ else -+ err = vfsub_unlink(h_dir, whpath, /*force*/0); -+ mnt_drop_write(whpath->mnt); -+ } -+ if (unlikely(err)) -+ pr_warning("failed removing %.*s (%d), ignored.\n", -+ AuDLNPair(whpath->dentry), err); -+} -+ -+static int test_linkable(struct dentry *h_root) -+{ -+ struct inode *h_dir = h_root->d_inode; -+ -+ if (h_dir->i_op->link) -+ return 0; -+ -+ pr_err("%.*s (%s) doesn't support link(2), use noplink and rw+nolwh\n", -+ AuDLNPair(h_root), au_sbtype(h_root->d_sb)); -+ return -ENOSYS; -+} -+ -+/* todo: should this mkdir be done in /sbin/mount.aufs helper? */ -+static int au_whdir(struct inode *h_dir, struct path *path) -+{ -+ int err; -+ -+ err = -EEXIST; -+ if (!path->dentry->d_inode) { -+ int mode = S_IRWXU; -+ -+ if (au_test_nfs(path->dentry->d_sb)) -+ mode |= S_IXUGO; -+ err = mnt_want_write(path->mnt); -+ if (!err) { -+ err = vfsub_mkdir(h_dir, path, mode); -+ mnt_drop_write(path->mnt); -+ } -+ } else if (S_ISDIR(path->dentry->d_inode->i_mode)) -+ err = 0; -+ else -+ pr_err("unknown %.*s exists\n", AuDLNPair(path->dentry)); -+ -+ return err; -+} -+ -+struct au_wh_base { -+ const struct qstr *name; -+ struct dentry *dentry; -+}; -+ -+static void au_wh_init_ro(struct inode *h_dir, struct au_wh_base base[], -+ struct path *h_path) -+{ -+ h_path->dentry = base[AuBrWh_BASE].dentry; -+ au_wh_clean(h_dir, h_path, /*isdir*/0); -+ h_path->dentry = base[AuBrWh_PLINK].dentry; -+ au_wh_clean(h_dir, h_path, /*isdir*/1); -+ h_path->dentry = base[AuBrWh_ORPH].dentry; -+ au_wh_clean(h_dir, h_path, /*isdir*/1); -+} -+ -+/* -+ * returns tri-state, -+ * minus: error, caller should print the mesage -+ * zero: succuess -+ * plus: error, caller should NOT print the mesage -+ */ -+static int au_wh_init_rw_nolink(struct dentry *h_root, struct au_wbr *wbr, -+ int do_plink, struct au_wh_base base[], -+ struct path *h_path) -+{ -+ int err; -+ struct inode *h_dir; -+ -+ h_dir = h_root->d_inode; -+ h_path->dentry = base[AuBrWh_BASE].dentry; -+ au_wh_clean(h_dir, h_path, /*isdir*/0); -+ h_path->dentry = base[AuBrWh_PLINK].dentry; -+ if (do_plink) { -+ err = test_linkable(h_root); -+ if (unlikely(err)) { -+ err = 1; -+ goto out; -+ } -+ -+ err = au_whdir(h_dir, h_path); -+ if (unlikely(err)) -+ goto out; -+ wbr->wbr_plink = dget(base[AuBrWh_PLINK].dentry); -+ } else -+ au_wh_clean(h_dir, h_path, /*isdir*/1); -+ h_path->dentry = base[AuBrWh_ORPH].dentry; -+ err = au_whdir(h_dir, h_path); -+ if (unlikely(err)) -+ goto out; -+ wbr->wbr_orph = dget(base[AuBrWh_ORPH].dentry); -+ -+out: -+ return err; -+} -+ -+/* -+ * for the moment, aufs supports the branch filesystem which does not support -+ * link(2). testing on FAT which does not support i_op->setattr() fully either, -+ * copyup failed. finally, such filesystem will not be used as the writable -+ * branch. -+ * -+ * returns tri-state, see above. -+ */ -+static int au_wh_init_rw(struct dentry *h_root, struct au_wbr *wbr, -+ int do_plink, struct au_wh_base base[], -+ struct path *h_path) -+{ -+ int err; -+ struct inode *h_dir; -+ -+ WbrWhMustWriteLock(wbr); -+ -+ err = test_linkable(h_root); -+ if (unlikely(err)) { -+ err = 1; -+ goto out; -+ } -+ -+ /* -+ * todo: should this create be done in /sbin/mount.aufs helper? -+ */ -+ err = -EEXIST; -+ h_dir = h_root->d_inode; -+ if (!base[AuBrWh_BASE].dentry->d_inode) { -+ err = mnt_want_write(h_path->mnt); -+ if (!err) { -+ h_path->dentry = base[AuBrWh_BASE].dentry; -+ err = vfsub_create(h_dir, h_path, WH_MASK); -+ mnt_drop_write(h_path->mnt); -+ } -+ } else if (S_ISREG(base[AuBrWh_BASE].dentry->d_inode->i_mode)) -+ err = 0; -+ else -+ pr_err("unknown %.*s/%.*s exists\n", -+ AuDLNPair(h_root), AuDLNPair(base[AuBrWh_BASE].dentry)); -+ if (unlikely(err)) -+ goto out; -+ -+ h_path->dentry = base[AuBrWh_PLINK].dentry; -+ if (do_plink) { -+ err = au_whdir(h_dir, h_path); -+ if (unlikely(err)) -+ goto out; -+ wbr->wbr_plink = dget(base[AuBrWh_PLINK].dentry); -+ } else -+ au_wh_clean(h_dir, h_path, /*isdir*/1); -+ wbr->wbr_whbase = dget(base[AuBrWh_BASE].dentry); -+ -+ h_path->dentry = base[AuBrWh_ORPH].dentry; -+ err = au_whdir(h_dir, h_path); -+ if (unlikely(err)) -+ goto out; -+ wbr->wbr_orph = dget(base[AuBrWh_ORPH].dentry); -+ -+out: -+ return err; -+} -+ -+/* -+ * initialize the whiteout base file/dir for @br. -+ */ -+int au_wh_init(struct dentry *h_root, struct au_branch *br, -+ struct super_block *sb) -+{ -+ int err, i; -+ const unsigned char do_plink -+ = !!au_opt_test(au_mntflags(sb), PLINK); -+ struct path path = { -+ .mnt = br->br_mnt -+ }; -+ struct inode *h_dir; -+ struct au_wbr *wbr = br->br_wbr; -+ static const struct qstr base_name[] = { -+ [AuBrWh_BASE] = { -+ .name = AUFS_BASE_NAME, -+ .len = sizeof(AUFS_BASE_NAME) - 1 -+ }, -+ [AuBrWh_PLINK] = { -+ .name = AUFS_PLINKDIR_NAME, -+ .len = sizeof(AUFS_PLINKDIR_NAME) - 1 -+ }, -+ [AuBrWh_ORPH] = { -+ .name = AUFS_ORPHDIR_NAME, -+ .len = sizeof(AUFS_ORPHDIR_NAME) - 1 -+ } -+ }; -+ struct au_wh_base base[] = { -+ [AuBrWh_BASE] = { -+ .name = base_name + AuBrWh_BASE, -+ .dentry = NULL -+ }, -+ [AuBrWh_PLINK] = { -+ .name = base_name + AuBrWh_PLINK, -+ .dentry = NULL -+ }, -+ [AuBrWh_ORPH] = { -+ .name = base_name + AuBrWh_ORPH, -+ .dentry = NULL -+ } -+ }; -+ -+ if (wbr) -+ WbrWhMustWriteLock(wbr); -+ -+ for (i = 0; i < AuBrWh_Last; i++) { -+ /* doubly whiteouted */ -+ struct dentry *d; -+ -+ d = au_wh_lkup(h_root, (void *)base[i].name, br); -+ err = PTR_ERR(d); -+ if (IS_ERR(d)) -+ goto out; -+ -+ base[i].dentry = d; -+ AuDebugOn(wbr -+ && wbr->wbr_wh[i] -+ && wbr->wbr_wh[i] != base[i].dentry); -+ } -+ -+ if (wbr) -+ for (i = 0; i < AuBrWh_Last; i++) { -+ dput(wbr->wbr_wh[i]); -+ wbr->wbr_wh[i] = NULL; -+ } -+ -+ err = 0; -+ switch (br->br_perm) { -+ case AuBrPerm_RO: -+ case AuBrPerm_ROWH: -+ case AuBrPerm_RR: -+ case AuBrPerm_RRWH: -+ h_dir = h_root->d_inode; -+ au_wh_init_ro(h_dir, base, &path); -+ break; -+ -+ case AuBrPerm_RWNoLinkWH: -+ err = au_wh_init_rw_nolink(h_root, wbr, do_plink, base, &path); -+ if (err > 0) -+ goto out; -+ else if (err) -+ goto out_err; -+ break; -+ -+ case AuBrPerm_RW: -+ err = au_wh_init_rw(h_root, wbr, do_plink, base, &path); -+ if (err > 0) -+ goto out; -+ else if (err) -+ goto out_err; -+ break; -+ -+ default: -+ BUG(); -+ } -+ goto out; /* success */ -+ -+out_err: -+ pr_err("an error(%d) on the writable branch %.*s(%s)\n", -+ err, AuDLNPair(h_root), au_sbtype(h_root->d_sb)); -+out: -+ for (i = 0; i < AuBrWh_Last; i++) -+ dput(base[i].dentry); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+/* -+ * whiteouts are all hard-linked usually. -+ * when its link count reaches a ceiling, we create a new whiteout base -+ * asynchronously. -+ */ -+ -+struct reinit_br_wh { -+ struct super_block *sb; -+ struct au_branch *br; -+}; -+ -+static void reinit_br_wh(void *arg) -+{ -+ int err; -+ aufs_bindex_t bindex; -+ struct path h_path; -+ struct reinit_br_wh *a = arg; -+ struct au_wbr *wbr; -+ struct inode *dir; -+ struct dentry *h_root; -+ struct au_hinode *hdir; -+ -+ err = 0; -+ wbr = a->br->br_wbr; -+ /* big aufs lock */ -+ si_noflush_write_lock(a->sb); -+ if (!au_br_writable(a->br->br_perm)) -+ goto out; -+ bindex = au_br_index(a->sb, a->br->br_id); -+ if (unlikely(bindex < 0)) -+ goto out; -+ -+ di_read_lock_parent(a->sb->s_root, AuLock_IR); -+ dir = a->sb->s_root->d_inode; -+ hdir = au_hi(dir, bindex); -+ h_root = au_h_dptr(a->sb->s_root, bindex); -+ -+ au_hn_imtx_lock_nested(hdir, AuLsc_I_PARENT); -+ wbr_wh_write_lock(wbr); -+ err = au_h_verify(wbr->wbr_whbase, au_opt_udba(a->sb), hdir->hi_inode, -+ h_root, a->br); -+ if (!err) { -+ err = mnt_want_write(a->br->br_mnt); -+ if (!err) { -+ h_path.dentry = wbr->wbr_whbase; -+ h_path.mnt = a->br->br_mnt; -+ err = vfsub_unlink(hdir->hi_inode, &h_path, /*force*/0); -+ mnt_drop_write(a->br->br_mnt); -+ } -+ } else { -+ pr_warning("%.*s is moved, ignored\n", -+ AuDLNPair(wbr->wbr_whbase)); -+ err = 0; -+ } -+ dput(wbr->wbr_whbase); -+ wbr->wbr_whbase = NULL; -+ if (!err) -+ err = au_wh_init(h_root, a->br, a->sb); -+ wbr_wh_write_unlock(wbr); -+ au_hn_imtx_unlock(hdir); -+ di_read_unlock(a->sb->s_root, AuLock_IR); -+ -+out: -+ if (wbr) -+ atomic_dec(&wbr->wbr_wh_running); -+ atomic_dec(&a->br->br_count); -+ si_write_unlock(a->sb); -+ au_nwt_done(&au_sbi(a->sb)->si_nowait); -+ kfree(arg); -+ if (unlikely(err)) -+ AuIOErr("err %d\n", err); -+} -+ -+static void kick_reinit_br_wh(struct super_block *sb, struct au_branch *br) -+{ -+ int do_dec, wkq_err; -+ struct reinit_br_wh *arg; -+ -+ do_dec = 1; -+ if (atomic_inc_return(&br->br_wbr->wbr_wh_running) != 1) -+ goto out; -+ -+ /* ignore ENOMEM */ -+ arg = kmalloc(sizeof(*arg), GFP_NOFS); -+ if (arg) { -+ /* -+ * dec(wh_running), kfree(arg) and dec(br_count) -+ * in reinit function -+ */ -+ arg->sb = sb; -+ arg->br = br; -+ atomic_inc(&br->br_count); -+ wkq_err = au_wkq_nowait(reinit_br_wh, arg, sb); -+ if (unlikely(wkq_err)) { -+ atomic_dec(&br->br_wbr->wbr_wh_running); -+ atomic_dec(&br->br_count); -+ kfree(arg); -+ } -+ do_dec = 0; -+ } -+ -+out: -+ if (do_dec) -+ atomic_dec(&br->br_wbr->wbr_wh_running); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * create the whiteout @wh. -+ */ -+static int link_or_create_wh(struct super_block *sb, aufs_bindex_t bindex, -+ struct dentry *wh) -+{ -+ int err; -+ struct path h_path = { -+ .dentry = wh -+ }; -+ struct au_branch *br; -+ struct au_wbr *wbr; -+ struct dentry *h_parent; -+ struct inode *h_dir; -+ -+ h_parent = wh->d_parent; /* dir inode is locked */ -+ h_dir = h_parent->d_inode; -+ IMustLock(h_dir); -+ -+ br = au_sbr(sb, bindex); -+ h_path.mnt = br->br_mnt; -+ wbr = br->br_wbr; -+ wbr_wh_read_lock(wbr); -+ if (wbr->wbr_whbase) { -+ err = vfsub_link(wbr->wbr_whbase, h_dir, &h_path); -+ if (!err || err != -EMLINK) -+ goto out; -+ -+ /* link count full. re-initialize br_whbase. */ -+ kick_reinit_br_wh(sb, br); -+ } -+ -+ /* return this error in this context */ -+ err = vfsub_create(h_dir, &h_path, WH_MASK); -+ -+out: -+ wbr_wh_read_unlock(wbr); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * create or remove the diropq. -+ */ -+static struct dentry *do_diropq(struct dentry *dentry, aufs_bindex_t bindex, -+ unsigned int flags) -+{ -+ struct dentry *opq_dentry, *h_dentry; -+ struct super_block *sb; -+ struct au_branch *br; -+ int err; -+ -+ sb = dentry->d_sb; -+ br = au_sbr(sb, bindex); -+ h_dentry = au_h_dptr(dentry, bindex); -+ opq_dentry = au_lkup_one(&diropq_name, h_dentry, br, /*nd*/NULL); -+ if (IS_ERR(opq_dentry)) -+ goto out; -+ -+ if (au_ftest_diropq(flags, CREATE)) { -+ err = link_or_create_wh(sb, bindex, opq_dentry); -+ if (!err) { -+ au_set_dbdiropq(dentry, bindex); -+ goto out; /* success */ -+ } -+ } else { -+ struct path tmp = { -+ .dentry = opq_dentry, -+ .mnt = br->br_mnt -+ }; -+ err = do_unlink_wh(au_h_iptr(dentry->d_inode, bindex), &tmp); -+ if (!err) -+ au_set_dbdiropq(dentry, -1); -+ } -+ dput(opq_dentry); -+ opq_dentry = ERR_PTR(err); -+ -+out: -+ return opq_dentry; -+} -+ -+struct do_diropq_args { -+ struct dentry **errp; -+ struct dentry *dentry; -+ aufs_bindex_t bindex; -+ unsigned int flags; -+}; -+ -+static void call_do_diropq(void *args) -+{ -+ struct do_diropq_args *a = args; -+ *a->errp = do_diropq(a->dentry, a->bindex, a->flags); -+} -+ -+struct dentry *au_diropq_sio(struct dentry *dentry, aufs_bindex_t bindex, -+ unsigned int flags) -+{ -+ struct dentry *diropq, *h_dentry; -+ -+ h_dentry = au_h_dptr(dentry, bindex); -+ if (!au_test_h_perm_sio(h_dentry->d_inode, MAY_EXEC | MAY_WRITE)) -+ diropq = do_diropq(dentry, bindex, flags); -+ else { -+ int wkq_err; -+ struct do_diropq_args args = { -+ .errp = &diropq, -+ .dentry = dentry, -+ .bindex = bindex, -+ .flags = flags -+ }; -+ -+ wkq_err = au_wkq_wait(call_do_diropq, &args); -+ if (unlikely(wkq_err)) -+ diropq = ERR_PTR(wkq_err); -+ } -+ -+ return diropq; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * lookup whiteout dentry. -+ * @h_parent: lower parent dentry which must exist and be locked -+ * @base_name: name of dentry which will be whiteouted -+ * returns dentry for whiteout. -+ */ -+struct dentry *au_wh_lkup(struct dentry *h_parent, struct qstr *base_name, -+ struct au_branch *br) -+{ -+ int err; -+ struct qstr wh_name; -+ struct dentry *wh_dentry; -+ -+ err = au_wh_name_alloc(&wh_name, base_name); -+ wh_dentry = ERR_PTR(err); -+ if (!err) { -+ wh_dentry = au_lkup_one(&wh_name, h_parent, br, /*nd*/NULL); -+ kfree(wh_name.name); -+ } -+ return wh_dentry; -+} -+ -+/* -+ * link/create a whiteout for @dentry on @bindex. -+ */ -+struct dentry *au_wh_create(struct dentry *dentry, aufs_bindex_t bindex, -+ struct dentry *h_parent) -+{ -+ struct dentry *wh_dentry; -+ struct super_block *sb; -+ int err; -+ -+ sb = dentry->d_sb; -+ wh_dentry = au_wh_lkup(h_parent, &dentry->d_name, au_sbr(sb, bindex)); -+ if (!IS_ERR(wh_dentry) && !wh_dentry->d_inode) { -+ err = link_or_create_wh(sb, bindex, wh_dentry); -+ if (!err) -+ au_set_dbwh(dentry, bindex); -+ else { -+ dput(wh_dentry); -+ wh_dentry = ERR_PTR(err); -+ } -+ } -+ -+ return wh_dentry; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* Delete all whiteouts in this directory on branch bindex. */ -+static int del_wh_children(struct dentry *h_dentry, struct au_nhash *whlist, -+ aufs_bindex_t bindex, struct au_branch *br) -+{ -+ int err; -+ unsigned long ul, n; -+ struct qstr wh_name; -+ char *p; -+ struct hlist_head *head; -+ struct au_vdir_wh *tpos; -+ struct hlist_node *pos; -+ struct au_vdir_destr *str; -+ -+ err = -ENOMEM; -+ p = __getname_gfp(GFP_NOFS); -+ wh_name.name = p; -+ if (unlikely(!wh_name.name)) -+ goto out; -+ -+ err = 0; -+ memcpy(p, AUFS_WH_PFX, AUFS_WH_PFX_LEN); -+ p += AUFS_WH_PFX_LEN; -+ n = whlist->nh_num; -+ head = whlist->nh_head; -+ for (ul = 0; !err && ul < n; ul++, head++) { -+ hlist_for_each_entry(tpos, pos, head, wh_hash) { -+ if (tpos->wh_bindex != bindex) -+ continue; -+ -+ str = &tpos->wh_str; -+ if (str->len + AUFS_WH_PFX_LEN <= PATH_MAX) { -+ memcpy(p, str->name, str->len); -+ wh_name.len = AUFS_WH_PFX_LEN + str->len; -+ err = unlink_wh_name(h_dentry, &wh_name, br); -+ if (!err) -+ continue; -+ break; -+ } -+ AuIOErr("whiteout name too long %.*s\n", -+ str->len, str->name); -+ err = -EIO; -+ break; -+ } -+ } -+ __putname(wh_name.name); -+ -+out: -+ return err; -+} -+ -+struct del_wh_children_args { -+ int *errp; -+ struct dentry *h_dentry; -+ struct au_nhash *whlist; -+ aufs_bindex_t bindex; -+ struct au_branch *br; -+}; -+ -+static void call_del_wh_children(void *args) -+{ -+ struct del_wh_children_args *a = args; -+ *a->errp = del_wh_children(a->h_dentry, a->whlist, a->bindex, a->br); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+struct au_whtmp_rmdir *au_whtmp_rmdir_alloc(struct super_block *sb, gfp_t gfp) -+{ -+ struct au_whtmp_rmdir *whtmp; -+ int err; -+ unsigned int rdhash; -+ -+ SiMustAnyLock(sb); -+ -+ whtmp = kmalloc(sizeof(*whtmp), gfp); -+ if (unlikely(!whtmp)) { -+ whtmp = ERR_PTR(-ENOMEM); -+ goto out; -+ } -+ -+ whtmp->dir = NULL; -+ whtmp->br = NULL; -+ whtmp->wh_dentry = NULL; -+ /* no estimation for dir size */ -+ rdhash = au_sbi(sb)->si_rdhash; -+ if (!rdhash) -+ rdhash = AUFS_RDHASH_DEF; -+ err = au_nhash_alloc(&whtmp->whlist, rdhash, gfp); -+ if (unlikely(err)) { -+ kfree(whtmp); -+ whtmp = ERR_PTR(err); -+ } -+ -+out: -+ return whtmp; -+} -+ -+void au_whtmp_rmdir_free(struct au_whtmp_rmdir *whtmp) -+{ -+ if (whtmp->br) -+ atomic_dec(&whtmp->br->br_count); -+ dput(whtmp->wh_dentry); -+ iput(whtmp->dir); -+ au_nhash_wh_free(&whtmp->whlist); -+ kfree(whtmp); -+} -+ -+/* -+ * rmdir the whiteouted temporary named dir @h_dentry. -+ * @whlist: whiteouted children. -+ */ -+int au_whtmp_rmdir(struct inode *dir, aufs_bindex_t bindex, -+ struct dentry *wh_dentry, struct au_nhash *whlist) -+{ -+ int err; -+ struct path h_tmp; -+ struct inode *wh_inode, *h_dir; -+ struct au_branch *br; -+ -+ h_dir = wh_dentry->d_parent->d_inode; /* dir inode is locked */ -+ IMustLock(h_dir); -+ -+ br = au_sbr(dir->i_sb, bindex); -+ wh_inode = wh_dentry->d_inode; -+ mutex_lock_nested(&wh_inode->i_mutex, AuLsc_I_CHILD); -+ -+ /* -+ * someone else might change some whiteouts while we were sleeping. -+ * it means this whlist may have an obsoleted entry. -+ */ -+ if (!au_test_h_perm_sio(wh_inode, MAY_EXEC | MAY_WRITE)) -+ err = del_wh_children(wh_dentry, whlist, bindex, br); -+ else { -+ int wkq_err; -+ struct del_wh_children_args args = { -+ .errp = &err, -+ .h_dentry = wh_dentry, -+ .whlist = whlist, -+ .bindex = bindex, -+ .br = br -+ }; -+ -+ wkq_err = au_wkq_wait(call_del_wh_children, &args); -+ if (unlikely(wkq_err)) -+ err = wkq_err; -+ } -+ mutex_unlock(&wh_inode->i_mutex); -+ -+ if (!err) { -+ h_tmp.dentry = wh_dentry; -+ h_tmp.mnt = br->br_mnt; -+ err = vfsub_rmdir(h_dir, &h_tmp); -+ } -+ -+ if (!err) { -+ if (au_ibstart(dir) == bindex) { -+ /* todo: dir->i_mutex is necessary */ -+ au_cpup_attr_timesizes(dir); -+ vfsub_drop_nlink(dir); -+ } -+ return 0; /* success */ -+ } -+ -+ pr_warning("failed removing %.*s(%d), ignored\n", -+ AuDLNPair(wh_dentry), err); -+ return err; -+} -+ -+static void call_rmdir_whtmp(void *args) -+{ -+ int err; -+ aufs_bindex_t bindex; -+ struct au_whtmp_rmdir *a = args; -+ struct super_block *sb; -+ struct dentry *h_parent; -+ struct inode *h_dir; -+ struct au_hinode *hdir; -+ -+ /* rmdir by nfsd may cause deadlock with this i_mutex */ -+ /* mutex_lock(&a->dir->i_mutex); */ -+ err = -EROFS; -+ sb = a->dir->i_sb; -+ si_read_lock(sb, !AuLock_FLUSH); -+ if (!au_br_writable(a->br->br_perm)) -+ goto out; -+ bindex = au_br_index(sb, a->br->br_id); -+ if (unlikely(bindex < 0)) -+ goto out; -+ -+ err = -EIO; -+ ii_write_lock_parent(a->dir); -+ h_parent = dget_parent(a->wh_dentry); -+ h_dir = h_parent->d_inode; -+ hdir = au_hi(a->dir, bindex); -+ au_hn_imtx_lock_nested(hdir, AuLsc_I_PARENT); -+ err = au_h_verify(a->wh_dentry, au_opt_udba(sb), h_dir, h_parent, -+ a->br); -+ if (!err) { -+ err = mnt_want_write(a->br->br_mnt); -+ if (!err) { -+ err = au_whtmp_rmdir(a->dir, bindex, a->wh_dentry, -+ &a->whlist); -+ mnt_drop_write(a->br->br_mnt); -+ } -+ } -+ au_hn_imtx_unlock(hdir); -+ dput(h_parent); -+ ii_write_unlock(a->dir); -+ -+out: -+ /* mutex_unlock(&a->dir->i_mutex); */ -+ au_whtmp_rmdir_free(a); -+ si_read_unlock(sb); -+ au_nwt_done(&au_sbi(sb)->si_nowait); -+ if (unlikely(err)) -+ AuIOErr("err %d\n", err); -+} -+ -+void au_whtmp_kick_rmdir(struct inode *dir, aufs_bindex_t bindex, -+ struct dentry *wh_dentry, struct au_whtmp_rmdir *args) -+{ -+ int wkq_err; -+ struct super_block *sb; -+ -+ IMustLock(dir); -+ -+ /* all post-process will be done in do_rmdir_whtmp(). */ -+ sb = dir->i_sb; -+ args->dir = au_igrab(dir); -+ args->br = au_sbr(sb, bindex); -+ atomic_inc(&args->br->br_count); -+ args->wh_dentry = dget(wh_dentry); -+ wkq_err = au_wkq_nowait(call_rmdir_whtmp, args, sb); -+ if (unlikely(wkq_err)) { -+ pr_warning("rmdir error %.*s (%d), ignored\n", -+ AuDLNPair(wh_dentry), wkq_err); -+ au_whtmp_rmdir_free(args); -+ } -+} -diff -Nur linux-2.6.36.orig/fs/aufs/whout.h linux-2.6.36/fs/aufs/whout.h ---- linux-2.6.36.orig/fs/aufs/whout.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/whout.h 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,89 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * whiteout for logical deletion and opaque directory -+ */ -+ -+#ifndef __AUFS_WHOUT_H__ -+#define __AUFS_WHOUT_H__ -+ -+#ifdef __KERNEL__ -+ -+#include -+#include "dir.h" -+ -+/* whout.c */ -+int au_wh_name_alloc(struct qstr *wh, const struct qstr *name); -+struct au_branch; -+int au_wh_test(struct dentry *h_parent, struct qstr *wh_name, -+ struct au_branch *br, int try_sio); -+int au_diropq_test(struct dentry *h_dentry, struct au_branch *br); -+struct dentry *au_whtmp_lkup(struct dentry *h_parent, struct au_branch *br, -+ struct qstr *prefix); -+int au_whtmp_ren(struct dentry *h_dentry, struct au_branch *br); -+int au_wh_unlink_dentry(struct inode *h_dir, struct path *h_path, -+ struct dentry *dentry); -+int au_wh_init(struct dentry *h_parent, struct au_branch *br, -+ struct super_block *sb); -+ -+/* diropq flags */ -+#define AuDiropq_CREATE 1 -+#define au_ftest_diropq(flags, name) ((flags) & AuDiropq_##name) -+#define au_fset_diropq(flags, name) \ -+ do { (flags) |= AuDiropq_##name; } while (0) -+#define au_fclr_diropq(flags, name) \ -+ do { (flags) &= ~AuDiropq_##name; } while (0) -+ -+struct dentry *au_diropq_sio(struct dentry *dentry, aufs_bindex_t bindex, -+ unsigned int flags); -+struct dentry *au_wh_lkup(struct dentry *h_parent, struct qstr *base_name, -+ struct au_branch *br); -+struct dentry *au_wh_create(struct dentry *dentry, aufs_bindex_t bindex, -+ struct dentry *h_parent); -+ -+/* real rmdir for the whiteout-ed dir */ -+struct au_whtmp_rmdir { -+ struct inode *dir; -+ struct au_branch *br; -+ struct dentry *wh_dentry; -+ struct au_nhash whlist; -+}; -+ -+struct au_whtmp_rmdir *au_whtmp_rmdir_alloc(struct super_block *sb, gfp_t gfp); -+void au_whtmp_rmdir_free(struct au_whtmp_rmdir *whtmp); -+int au_whtmp_rmdir(struct inode *dir, aufs_bindex_t bindex, -+ struct dentry *wh_dentry, struct au_nhash *whlist); -+void au_whtmp_kick_rmdir(struct inode *dir, aufs_bindex_t bindex, -+ struct dentry *wh_dentry, struct au_whtmp_rmdir *args); -+ -+/* ---------------------------------------------------------------------- */ -+ -+static inline struct dentry *au_diropq_create(struct dentry *dentry, -+ aufs_bindex_t bindex) -+{ -+ return au_diropq_sio(dentry, bindex, AuDiropq_CREATE); -+} -+ -+static inline int au_diropq_remove(struct dentry *dentry, aufs_bindex_t bindex) -+{ -+ return PTR_ERR(au_diropq_sio(dentry, bindex, !AuDiropq_CREATE)); -+} -+ -+#endif /* __KERNEL__ */ -+#endif /* __AUFS_WHOUT_H__ */ -diff -Nur linux-2.6.36.orig/fs/aufs/wkq.c linux-2.6.36/fs/aufs/wkq.c ---- linux-2.6.36.orig/fs/aufs/wkq.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/wkq.c 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,236 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * workqueue for asynchronous/super-io operations -+ * todo: try new dredential scheme -+ */ -+ -+#include -+#include "aufs.h" -+ -+/* internal workqueue named AUFS_WKQ_NAME and AUFS_WKQ_PRE_NAME */ -+enum { -+ AuWkq_INORMAL, -+ AuWkq_IPRE -+}; -+ -+static struct { -+ char *name; -+ struct workqueue_struct *wkq; -+} au_wkq[] = { -+ [AuWkq_INORMAL] = { -+ .name = AUFS_WKQ_NAME -+ }, -+ [AuWkq_IPRE] = { -+ .name = AUFS_WKQ_PRE_NAME -+ } -+}; -+ -+struct au_wkinfo { -+ struct work_struct wk; -+ struct kobject *kobj; -+ -+ unsigned int flags; /* see wkq.h */ -+ -+ au_wkq_func_t func; -+ void *args; -+ -+ struct completion *comp; -+}; -+ -+/* ---------------------------------------------------------------------- */ -+ -+static void wkq_func(struct work_struct *wk) -+{ -+ struct au_wkinfo *wkinfo = container_of(wk, struct au_wkinfo, wk); -+ -+ AuDebugOn(current_fsuid()); -+ AuDebugOn(rlimit(RLIMIT_FSIZE) != RLIM_INFINITY); -+ -+ wkinfo->func(wkinfo->args); -+ if (au_ftest_wkq(wkinfo->flags, WAIT)) -+ complete(wkinfo->comp); -+ else { -+ kobject_put(wkinfo->kobj); -+ module_put(THIS_MODULE); -+ kfree(wkinfo); -+ } -+} -+ -+/* -+ * Since struct completion is large, try allocating it dynamically. -+ */ -+#if defined(CONFIG_4KSTACKS) || defined(AuTest4KSTACKS) -+#define AuWkqCompDeclare(name) struct completion *comp = NULL -+ -+static int au_wkq_comp_alloc(struct au_wkinfo *wkinfo, struct completion **comp) -+{ -+ *comp = kmalloc(sizeof(**comp), GFP_NOFS); -+ if (*comp) { -+ init_completion(*comp); -+ wkinfo->comp = *comp; -+ return 0; -+ } -+ return -ENOMEM; -+} -+ -+static void au_wkq_comp_free(struct completion *comp) -+{ -+ kfree(comp); -+} -+ -+#else -+ -+/* no braces */ -+#define AuWkqCompDeclare(name) \ -+ DECLARE_COMPLETION_ONSTACK(_ ## name); \ -+ struct completion *comp = &_ ## name -+ -+static int au_wkq_comp_alloc(struct au_wkinfo *wkinfo, struct completion **comp) -+{ -+ wkinfo->comp = *comp; -+ return 0; -+} -+ -+static void au_wkq_comp_free(struct completion *comp __maybe_unused) -+{ -+ /* empty */ -+} -+#endif /* 4KSTACKS */ -+ -+static void au_wkq_run(struct au_wkinfo *wkinfo, unsigned int flags) -+{ -+ struct workqueue_struct *wkq; -+ -+ au_dbg_verify_kthread(); -+ if (flags & AuWkq_WAIT) { -+ INIT_WORK_ON_STACK(&wkinfo->wk, wkq_func); -+ wkq = au_wkq[AuWkq_INORMAL].wkq; -+ if (flags & AuWkq_PRE) -+ wkq = au_wkq[AuWkq_IPRE].wkq; -+ queue_work(wkq, &wkinfo->wk); -+ } else { -+ INIT_WORK(&wkinfo->wk, wkq_func); -+ schedule_work(&wkinfo->wk); -+ } -+} -+ -+/* -+ * Be careful. It is easy to make deadlock happen. -+ * processA: lock, wkq and wait -+ * processB: wkq and wait, lock in wkq -+ * --> deadlock -+ */ -+int au_wkq_do_wait(unsigned int flags, au_wkq_func_t func, void *args) -+{ -+ int err; -+ AuWkqCompDeclare(comp); -+ struct au_wkinfo wkinfo = { -+ .flags = flags, -+ .func = func, -+ .args = args -+ }; -+ -+ err = au_wkq_comp_alloc(&wkinfo, &comp); -+ if (!err) { -+ au_wkq_run(&wkinfo, flags); -+ /* no timeout, no interrupt */ -+ wait_for_completion(wkinfo.comp); -+ au_wkq_comp_free(comp); -+ destroy_work_on_stack(&wkinfo.wk); -+ } -+ -+ return err; -+ -+} -+ -+/* -+ * Note: dget/dput() in func for aufs dentries are not supported. It will be a -+ * problem in a concurrent umounting. -+ */ -+int au_wkq_nowait(au_wkq_func_t func, void *args, struct super_block *sb) -+{ -+ int err; -+ struct au_wkinfo *wkinfo; -+ -+ atomic_inc(&au_sbi(sb)->si_nowait.nw_len); -+ -+ /* -+ * wkq_func() must free this wkinfo. -+ * it highly depends upon the implementation of workqueue. -+ */ -+ err = 0; -+ wkinfo = kmalloc(sizeof(*wkinfo), GFP_NOFS); -+ if (wkinfo) { -+ wkinfo->kobj = &au_sbi(sb)->si_kobj; -+ wkinfo->flags = !AuWkq_WAIT; -+ wkinfo->func = func; -+ wkinfo->args = args; -+ wkinfo->comp = NULL; -+ kobject_get(wkinfo->kobj); -+ __module_get(THIS_MODULE); -+ -+ au_wkq_run(wkinfo, !AuWkq_WAIT); -+ } else { -+ err = -ENOMEM; -+ au_nwt_done(&au_sbi(sb)->si_nowait); -+ } -+ -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+void au_nwt_init(struct au_nowait_tasks *nwt) -+{ -+ atomic_set(&nwt->nw_len, 0); -+ /* smp_mb(); */ /* atomic_set */ -+ init_waitqueue_head(&nwt->nw_wq); -+} -+ -+void au_wkq_fin(void) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(au_wkq); i++) -+ if (au_wkq[i].wkq) -+ destroy_workqueue(au_wkq[i].wkq); -+} -+ -+int __init au_wkq_init(void) -+{ -+ int err, i; -+ -+ err = 0; -+ for (i = 0; !err && i < ARRAY_SIZE(au_wkq); i++) { -+ BUILD_BUG_ON(!WQ_RESCUER); -+ au_wkq[i].wkq = alloc_workqueue(au_wkq[i].name, !WQ_RESCUER, -+ WQ_DFL_ACTIVE); -+ if (IS_ERR(au_wkq[i].wkq)) -+ err = PTR_ERR(au_wkq[i].wkq); -+ else if (!au_wkq[i].wkq) -+ err = -ENOMEM; -+ if (unlikely(err)) -+ au_wkq[i].wkq = NULL; -+ } -+ if (unlikely(err)) -+ au_wkq_fin(); -+ -+ return err; -+} -diff -Nur linux-2.6.36.orig/fs/aufs/wkq.h linux-2.6.36/fs/aufs/wkq.h ---- linux-2.6.36.orig/fs/aufs/wkq.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/wkq.h 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,90 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * workqueue for asynchronous/super-io operations -+ * todo: try new credentials management scheme -+ */ -+ -+#ifndef __AUFS_WKQ_H__ -+#define __AUFS_WKQ_H__ -+ -+#ifdef __KERNEL__ -+ -+#include -+#include -+#include -+ -+struct super_block; -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * in the next operation, wait for the 'nowait' tasks in system-wide workqueue -+ */ -+struct au_nowait_tasks { -+ atomic_t nw_len; -+ wait_queue_head_t nw_wq; -+}; -+ -+/* ---------------------------------------------------------------------- */ -+ -+typedef void (*au_wkq_func_t)(void *args); -+ -+/* wkq flags */ -+#define AuWkq_WAIT 1 -+#define AuWkq_PRE (1 << 1) -+#define au_ftest_wkq(flags, name) ((flags) & AuWkq_##name) -+#define au_fset_wkq(flags, name) \ -+ do { (flags) |= AuWkq_##name; } while (0) -+#define au_fclr_wkq(flags, name) \ -+ do { (flags) &= ~AuWkq_##name; } while (0) -+ -+/* wkq.c */ -+int au_wkq_do_wait(unsigned int flags, au_wkq_func_t func, void *args); -+int au_wkq_nowait(au_wkq_func_t func, void *args, struct super_block *sb); -+void au_nwt_init(struct au_nowait_tasks *nwt); -+int __init au_wkq_init(void); -+void au_wkq_fin(void); -+ -+/* ---------------------------------------------------------------------- */ -+ -+static inline int au_wkq_wait_pre(au_wkq_func_t func, void *args) -+{ -+ return au_wkq_do_wait(AuWkq_WAIT | AuWkq_PRE, func, args); -+} -+ -+static inline int au_wkq_wait(au_wkq_func_t func, void *args) -+{ -+ return au_wkq_do_wait(AuWkq_WAIT, func, args); -+} -+ -+static inline void au_nwt_done(struct au_nowait_tasks *nwt) -+{ -+ if (atomic_dec_and_test(&nwt->nw_len)) -+ wake_up_all(&nwt->nw_wq); -+} -+ -+static inline int au_nwt_flush(struct au_nowait_tasks *nwt) -+{ -+ wait_event(nwt->nw_wq, !atomic_read(&nwt->nw_len)); -+ return 0; -+} -+ -+#endif /* __KERNEL__ */ -+#endif /* __AUFS_WKQ_H__ */ -diff -Nur linux-2.6.36.orig/fs/aufs/xino.c linux-2.6.36/fs/aufs/xino.c ---- linux-2.6.36.orig/fs/aufs/xino.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/aufs/xino.c 2011-01-10 19:24:41.000000000 +0100 -@@ -0,0 +1,1265 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * external inode number translation table and bitmap -+ */ -+ -+#include -+#include -+#include -+#include "aufs.h" -+ -+ssize_t xino_fread(au_readf_t func, struct file *file, void *kbuf, size_t size, -+ loff_t *pos) -+{ -+ ssize_t err; -+ mm_segment_t oldfs; -+ union { -+ void *k; -+ char __user *u; -+ } buf; -+ -+ buf.k = kbuf; -+ oldfs = get_fs(); -+ set_fs(KERNEL_DS); -+ do { -+ /* todo: signal_pending? */ -+ err = func(file, buf.u, size, pos); -+ } while (err == -EAGAIN || err == -EINTR); -+ set_fs(oldfs); -+ -+#if 0 /* reserved for future use */ -+ if (err > 0) -+ fsnotify_access(file->f_dentry); -+#endif -+ -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static ssize_t do_xino_fwrite(au_writef_t func, struct file *file, void *kbuf, -+ size_t size, loff_t *pos) -+{ -+ ssize_t err; -+ mm_segment_t oldfs; -+ union { -+ void *k; -+ const char __user *u; -+ } buf; -+ -+ buf.k = kbuf; -+ oldfs = get_fs(); -+ set_fs(KERNEL_DS); -+ do { -+ /* todo: signal_pending? */ -+ err = func(file, buf.u, size, pos); -+ } while (err == -EAGAIN || err == -EINTR); -+ set_fs(oldfs); -+ -+#if 0 /* reserved for future use */ -+ if (err > 0) -+ fsnotify_modify(file->f_dentry); -+#endif -+ -+ return err; -+} -+ -+struct do_xino_fwrite_args { -+ ssize_t *errp; -+ au_writef_t func; -+ struct file *file; -+ void *buf; -+ size_t size; -+ loff_t *pos; -+}; -+ -+static void call_do_xino_fwrite(void *args) -+{ -+ struct do_xino_fwrite_args *a = args; -+ *a->errp = do_xino_fwrite(a->func, a->file, a->buf, a->size, a->pos); -+} -+ -+ssize_t xino_fwrite(au_writef_t func, struct file *file, void *buf, size_t size, -+ loff_t *pos) -+{ -+ ssize_t err; -+ -+ /* todo: signal block and no wkq? */ -+ if (rlimit(RLIMIT_FSIZE) == RLIM_INFINITY) { -+ lockdep_off(); -+ err = do_xino_fwrite(func, file, buf, size, pos); -+ lockdep_on(); -+ } else { -+ /* -+ * it breaks RLIMIT_FSIZE and normal user's limit, -+ * users should care about quota and real 'filesystem full.' -+ */ -+ int wkq_err; -+ struct do_xino_fwrite_args args = { -+ .errp = &err, -+ .func = func, -+ .file = file, -+ .buf = buf, -+ .size = size, -+ .pos = pos -+ }; -+ -+ wkq_err = au_wkq_wait(call_do_xino_fwrite, &args); -+ if (unlikely(wkq_err)) -+ err = wkq_err; -+ } -+ -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * create a new xinofile at the same place/path as @base_file. -+ */ -+struct file *au_xino_create2(struct file *base_file, struct file *copy_src) -+{ -+ struct file *file; -+ struct dentry *base, *parent; -+ struct inode *dir; -+ struct qstr *name; -+ struct path path; -+ int err; -+ -+ base = base_file->f_dentry; -+ parent = base->d_parent; /* dir inode is locked */ -+ dir = parent->d_inode; -+ IMustLock(dir); -+ -+ file = ERR_PTR(-EINVAL); -+ name = &base->d_name; -+ path.dentry = vfsub_lookup_one_len(name->name, parent, name->len); -+ if (IS_ERR(path.dentry)) { -+ file = (void *)path.dentry; -+ pr_err("%.*s lookup err %ld\n", -+ AuLNPair(name), PTR_ERR(path.dentry)); -+ goto out; -+ } -+ -+ /* no need to mnt_want_write() since we call dentry_open() later */ -+ err = vfs_create(dir, path.dentry, S_IRUGO | S_IWUGO, NULL); -+ if (unlikely(err)) { -+ file = ERR_PTR(err); -+ pr_err("%.*s create err %d\n", AuLNPair(name), err); -+ goto out_dput; -+ } -+ -+ path.mnt = base_file->f_vfsmnt; -+ file = vfsub_dentry_open(&path, -+ O_RDWR | O_CREAT | O_EXCL | O_LARGEFILE -+ /* | FMODE_NONOTIFY */); -+ if (IS_ERR(file)) { -+ pr_err("%.*s open err %ld\n", AuLNPair(name), PTR_ERR(file)); -+ goto out_dput; -+ } -+ -+ err = vfsub_unlink(dir, &file->f_path, /*force*/0); -+ if (unlikely(err)) { -+ pr_err("%.*s unlink err %d\n", AuLNPair(name), err); -+ goto out_fput; -+ } -+ -+ if (copy_src) { -+ /* no one can touch copy_src xino */ -+ err = au_copy_file(file, copy_src, -+ i_size_read(copy_src->f_dentry->d_inode)); -+ if (unlikely(err)) { -+ pr_err("%.*s copy err %d\n", AuLNPair(name), err); -+ goto out_fput; -+ } -+ } -+ goto out_dput; /* success */ -+ -+out_fput: -+ fput(file); -+ file = ERR_PTR(err); -+out_dput: -+ dput(path.dentry); -+out: -+ return file; -+} -+ -+struct au_xino_lock_dir { -+ struct au_hinode *hdir; -+ struct dentry *parent; -+ struct mutex *mtx; -+}; -+ -+static void au_xino_lock_dir(struct super_block *sb, struct file *xino, -+ struct au_xino_lock_dir *ldir) -+{ -+ aufs_bindex_t brid, bindex; -+ -+ ldir->hdir = NULL; -+ bindex = -1; -+ brid = au_xino_brid(sb); -+ if (brid >= 0) -+ bindex = au_br_index(sb, brid); -+ if (bindex >= 0) { -+ ldir->hdir = au_hi(sb->s_root->d_inode, bindex); -+ au_hn_imtx_lock_nested(ldir->hdir, AuLsc_I_PARENT); -+ } else { -+ ldir->parent = dget_parent(xino->f_dentry); -+ ldir->mtx = &ldir->parent->d_inode->i_mutex; -+ mutex_lock_nested(ldir->mtx, AuLsc_I_PARENT); -+ } -+} -+ -+static void au_xino_unlock_dir(struct au_xino_lock_dir *ldir) -+{ -+ if (ldir->hdir) -+ au_hn_imtx_unlock(ldir->hdir); -+ else { -+ mutex_unlock(ldir->mtx); -+ dput(ldir->parent); -+ } -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* trucate xino files asynchronously */ -+ -+int au_xino_trunc(struct super_block *sb, aufs_bindex_t bindex) -+{ -+ int err; -+ aufs_bindex_t bi, bend; -+ struct au_branch *br; -+ struct file *new_xino, *file; -+ struct super_block *h_sb; -+ struct au_xino_lock_dir ldir; -+ -+ err = -EINVAL; -+ bend = au_sbend(sb); -+ if (unlikely(bindex < 0 || bend < bindex)) -+ goto out; -+ br = au_sbr(sb, bindex); -+ file = br->br_xino.xi_file; -+ if (!file) -+ goto out; -+ -+ au_xino_lock_dir(sb, file, &ldir); -+ /* mnt_want_write() is unnecessary here */ -+ new_xino = au_xino_create2(file, file); -+ au_xino_unlock_dir(&ldir); -+ err = PTR_ERR(new_xino); -+ if (IS_ERR(new_xino)) -+ goto out; -+ err = 0; -+ fput(file); -+ br->br_xino.xi_file = new_xino; -+ -+ h_sb = br->br_mnt->mnt_sb; -+ for (bi = 0; bi <= bend; bi++) { -+ if (unlikely(bi == bindex)) -+ continue; -+ br = au_sbr(sb, bi); -+ if (br->br_mnt->mnt_sb != h_sb) -+ continue; -+ -+ fput(br->br_xino.xi_file); -+ br->br_xino.xi_file = new_xino; -+ get_file(new_xino); -+ } -+ -+out: -+ return err; -+} -+ -+struct xino_do_trunc_args { -+ struct super_block *sb; -+ struct au_branch *br; -+}; -+ -+static void xino_do_trunc(void *_args) -+{ -+ struct xino_do_trunc_args *args = _args; -+ struct super_block *sb; -+ struct au_branch *br; -+ struct inode *dir; -+ int err; -+ aufs_bindex_t bindex; -+ -+ err = 0; -+ sb = args->sb; -+ dir = sb->s_root->d_inode; -+ br = args->br; -+ -+ si_noflush_write_lock(sb); -+ ii_read_lock_parent(dir); -+ bindex = au_br_index(sb, br->br_id); -+ err = au_xino_trunc(sb, bindex); -+ if (!err -+ && br->br_xino.xi_file->f_dentry->d_inode->i_blocks -+ >= br->br_xino_upper) -+ br->br_xino_upper += AUFS_XINO_TRUNC_STEP; -+ -+ ii_read_unlock(dir); -+ if (unlikely(err)) -+ pr_warning("err b%d, (%d)\n", bindex, err); -+ atomic_dec(&br->br_xino_running); -+ atomic_dec(&br->br_count); -+ si_write_unlock(sb); -+ au_nwt_done(&au_sbi(sb)->si_nowait); -+ kfree(args); -+} -+ -+static void xino_try_trunc(struct super_block *sb, struct au_branch *br) -+{ -+ struct xino_do_trunc_args *args; -+ int wkq_err; -+ -+ if (br->br_xino.xi_file->f_dentry->d_inode->i_blocks -+ < br->br_xino_upper) -+ return; -+ -+ if (atomic_inc_return(&br->br_xino_running) > 1) -+ goto out; -+ -+ /* lock and kfree() will be called in trunc_xino() */ -+ args = kmalloc(sizeof(*args), GFP_NOFS); -+ if (unlikely(!args)) { -+ AuErr1("no memory\n"); -+ goto out_args; -+ } -+ -+ atomic_inc(&br->br_count); -+ args->sb = sb; -+ args->br = br; -+ wkq_err = au_wkq_nowait(xino_do_trunc, args, sb); -+ if (!wkq_err) -+ return; /* success */ -+ -+ pr_err("wkq %d\n", wkq_err); -+ atomic_dec(&br->br_count); -+ -+out_args: -+ kfree(args); -+out: -+ atomic_dec(&br->br_xino_running); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int au_xino_do_write(au_writef_t write, struct file *file, -+ ino_t h_ino, ino_t ino) -+{ -+ loff_t pos; -+ ssize_t sz; -+ -+ pos = h_ino; -+ if (unlikely(au_loff_max / sizeof(ino) - 1 < pos)) { -+ AuIOErr1("too large hi%lu\n", (unsigned long)h_ino); -+ return -EFBIG; -+ } -+ pos *= sizeof(ino); -+ sz = xino_fwrite(write, file, &ino, sizeof(ino), &pos); -+ if (sz == sizeof(ino)) -+ return 0; /* success */ -+ -+ AuIOErr("write failed (%zd)\n", sz); -+ return -EIO; -+} -+ -+/* -+ * write @ino to the xinofile for the specified branch{@sb, @bindex} -+ * at the position of @h_ino. -+ * even if @ino is zero, it is written to the xinofile and means no entry. -+ * if the size of the xino file on a specific filesystem exceeds the watermark, -+ * try truncating it. -+ */ -+int au_xino_write(struct super_block *sb, aufs_bindex_t bindex, ino_t h_ino, -+ ino_t ino) -+{ -+ int err; -+ unsigned int mnt_flags; -+ struct au_branch *br; -+ -+ BUILD_BUG_ON(sizeof(long long) != sizeof(au_loff_max) -+ || ((loff_t)-1) > 0); -+ SiMustAnyLock(sb); -+ -+ mnt_flags = au_mntflags(sb); -+ if (!au_opt_test(mnt_flags, XINO)) -+ return 0; -+ -+ br = au_sbr(sb, bindex); -+ err = au_xino_do_write(au_sbi(sb)->si_xwrite, br->br_xino.xi_file, -+ h_ino, ino); -+ if (!err) { -+ if (au_opt_test(mnt_flags, TRUNC_XINO) -+ && au_test_fs_trunc_xino(br->br_mnt->mnt_sb)) -+ xino_try_trunc(sb, br); -+ return 0; /* success */ -+ } -+ -+ AuIOErr("write failed (%d)\n", err); -+ return -EIO; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* aufs inode number bitmap */ -+ -+static const int page_bits = (int)PAGE_SIZE * BITS_PER_BYTE; -+static ino_t xib_calc_ino(unsigned long pindex, int bit) -+{ -+ ino_t ino; -+ -+ AuDebugOn(bit < 0 || page_bits <= bit); -+ ino = AUFS_FIRST_INO + pindex * page_bits + bit; -+ return ino; -+} -+ -+static void xib_calc_bit(ino_t ino, unsigned long *pindex, int *bit) -+{ -+ AuDebugOn(ino < AUFS_FIRST_INO); -+ ino -= AUFS_FIRST_INO; -+ *pindex = ino / page_bits; -+ *bit = ino % page_bits; -+} -+ -+static int xib_pindex(struct super_block *sb, unsigned long pindex) -+{ -+ int err; -+ loff_t pos; -+ ssize_t sz; -+ struct au_sbinfo *sbinfo; -+ struct file *xib; -+ unsigned long *p; -+ -+ sbinfo = au_sbi(sb); -+ MtxMustLock(&sbinfo->si_xib_mtx); -+ AuDebugOn(pindex > ULONG_MAX / PAGE_SIZE -+ || !au_opt_test(sbinfo->si_mntflags, XINO)); -+ -+ if (pindex == sbinfo->si_xib_last_pindex) -+ return 0; -+ -+ xib = sbinfo->si_xib; -+ p = sbinfo->si_xib_buf; -+ pos = sbinfo->si_xib_last_pindex; -+ pos *= PAGE_SIZE; -+ sz = xino_fwrite(sbinfo->si_xwrite, xib, p, PAGE_SIZE, &pos); -+ if (unlikely(sz != PAGE_SIZE)) -+ goto out; -+ -+ pos = pindex; -+ pos *= PAGE_SIZE; -+ if (i_size_read(xib->f_dentry->d_inode) >= pos + PAGE_SIZE) -+ sz = xino_fread(sbinfo->si_xread, xib, p, PAGE_SIZE, &pos); -+ else { -+ memset(p, 0, PAGE_SIZE); -+ sz = xino_fwrite(sbinfo->si_xwrite, xib, p, PAGE_SIZE, &pos); -+ } -+ if (sz == PAGE_SIZE) { -+ sbinfo->si_xib_last_pindex = pindex; -+ return 0; /* success */ -+ } -+ -+out: -+ AuIOErr1("write failed (%zd)\n", sz); -+ err = sz; -+ if (sz >= 0) -+ err = -EIO; -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static void au_xib_clear_bit(struct inode *inode) -+{ -+ int err, bit; -+ unsigned long pindex; -+ struct super_block *sb; -+ struct au_sbinfo *sbinfo; -+ -+ AuDebugOn(inode->i_nlink); -+ -+ sb = inode->i_sb; -+ xib_calc_bit(inode->i_ino, &pindex, &bit); -+ AuDebugOn(page_bits <= bit); -+ sbinfo = au_sbi(sb); -+ mutex_lock(&sbinfo->si_xib_mtx); -+ err = xib_pindex(sb, pindex); -+ if (!err) { -+ clear_bit(bit, sbinfo->si_xib_buf); -+ sbinfo->si_xib_next_bit = bit; -+ } -+ mutex_unlock(&sbinfo->si_xib_mtx); -+} -+ -+/* for s_op->delete_inode() */ -+void au_xino_delete_inode(struct inode *inode, const int unlinked) -+{ -+ int err; -+ unsigned int mnt_flags; -+ aufs_bindex_t bindex, bend, bi; -+ unsigned char try_trunc; -+ struct au_iinfo *iinfo; -+ struct super_block *sb; -+ struct au_hinode *hi; -+ struct inode *h_inode; -+ struct au_branch *br; -+ au_writef_t xwrite; -+ -+ sb = inode->i_sb; -+ mnt_flags = au_mntflags(sb); -+ if (!au_opt_test(mnt_flags, XINO) -+ || inode->i_ino == AUFS_ROOT_INO) -+ return; -+ -+ if (unlinked) { -+ au_xigen_inc(inode); -+ au_xib_clear_bit(inode); -+ } -+ -+ iinfo = au_ii(inode); -+ if (!iinfo) -+ return; -+ -+ bindex = iinfo->ii_bstart; -+ if (bindex < 0) -+ return; -+ -+ xwrite = au_sbi(sb)->si_xwrite; -+ try_trunc = !!au_opt_test(mnt_flags, TRUNC_XINO); -+ hi = iinfo->ii_hinode + bindex; -+ bend = iinfo->ii_bend; -+ for (; bindex <= bend; bindex++, hi++) { -+ h_inode = hi->hi_inode; -+ if (!h_inode -+ || (!unlinked && h_inode->i_nlink)) -+ continue; -+ -+ /* inode may not be revalidated */ -+ bi = au_br_index(sb, hi->hi_id); -+ if (bi < 0) -+ continue; -+ -+ br = au_sbr(sb, bi); -+ err = au_xino_do_write(xwrite, br->br_xino.xi_file, -+ h_inode->i_ino, /*ino*/0); -+ if (!err && try_trunc -+ && au_test_fs_trunc_xino(br->br_mnt->mnt_sb)) -+ xino_try_trunc(sb, br); -+ } -+} -+ -+/* get an unused inode number from bitmap */ -+ino_t au_xino_new_ino(struct super_block *sb) -+{ -+ ino_t ino; -+ unsigned long *p, pindex, ul, pend; -+ struct au_sbinfo *sbinfo; -+ struct file *file; -+ int free_bit, err; -+ -+ if (!au_opt_test(au_mntflags(sb), XINO)) -+ return iunique(sb, AUFS_FIRST_INO); -+ -+ sbinfo = au_sbi(sb); -+ mutex_lock(&sbinfo->si_xib_mtx); -+ p = sbinfo->si_xib_buf; -+ free_bit = sbinfo->si_xib_next_bit; -+ if (free_bit < page_bits && !test_bit(free_bit, p)) -+ goto out; /* success */ -+ free_bit = find_first_zero_bit(p, page_bits); -+ if (free_bit < page_bits) -+ goto out; /* success */ -+ -+ pindex = sbinfo->si_xib_last_pindex; -+ for (ul = pindex - 1; ul < ULONG_MAX; ul--) { -+ err = xib_pindex(sb, ul); -+ if (unlikely(err)) -+ goto out_err; -+ free_bit = find_first_zero_bit(p, page_bits); -+ if (free_bit < page_bits) -+ goto out; /* success */ -+ } -+ -+ file = sbinfo->si_xib; -+ pend = i_size_read(file->f_dentry->d_inode) / PAGE_SIZE; -+ for (ul = pindex + 1; ul <= pend; ul++) { -+ err = xib_pindex(sb, ul); -+ if (unlikely(err)) -+ goto out_err; -+ free_bit = find_first_zero_bit(p, page_bits); -+ if (free_bit < page_bits) -+ goto out; /* success */ -+ } -+ BUG(); -+ -+out: -+ set_bit(free_bit, p); -+ sbinfo->si_xib_next_bit = free_bit + 1; -+ pindex = sbinfo->si_xib_last_pindex; -+ mutex_unlock(&sbinfo->si_xib_mtx); -+ ino = xib_calc_ino(pindex, free_bit); -+ AuDbg("i%lu\n", (unsigned long)ino); -+ return ino; -+out_err: -+ mutex_unlock(&sbinfo->si_xib_mtx); -+ AuDbg("i0\n"); -+ return 0; -+} -+ -+/* -+ * read @ino from xinofile for the specified branch{@sb, @bindex} -+ * at the position of @h_ino. -+ * if @ino does not exist and @do_new is true, get new one. -+ */ -+int au_xino_read(struct super_block *sb, aufs_bindex_t bindex, ino_t h_ino, -+ ino_t *ino) -+{ -+ int err; -+ ssize_t sz; -+ loff_t pos; -+ struct file *file; -+ struct au_sbinfo *sbinfo; -+ -+ *ino = 0; -+ if (!au_opt_test(au_mntflags(sb), XINO)) -+ return 0; /* no xino */ -+ -+ err = 0; -+ sbinfo = au_sbi(sb); -+ pos = h_ino; -+ if (unlikely(au_loff_max / sizeof(*ino) - 1 < pos)) { -+ AuIOErr1("too large hi%lu\n", (unsigned long)h_ino); -+ return -EFBIG; -+ } -+ pos *= sizeof(*ino); -+ -+ file = au_sbr(sb, bindex)->br_xino.xi_file; -+ if (i_size_read(file->f_dentry->d_inode) < pos + sizeof(*ino)) -+ return 0; /* no ino */ -+ -+ sz = xino_fread(sbinfo->si_xread, file, ino, sizeof(*ino), &pos); -+ if (sz == sizeof(*ino)) -+ return 0; /* success */ -+ -+ err = sz; -+ if (unlikely(sz >= 0)) { -+ err = -EIO; -+ AuIOErr("xino read error (%zd)\n", sz); -+ } -+ -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* create and set a new xino file */ -+ -+struct file *au_xino_create(struct super_block *sb, char *fname, int silent) -+{ -+ struct file *file; -+ struct dentry *h_parent, *d; -+ struct inode *h_dir; -+ int err; -+ -+ /* -+ * at mount-time, and the xino file is the default path, -+ * hnotify is disabled so we have no notify events to ignore. -+ * when a user specified the xino, we cannot get au_hdir to be ignored. -+ */ -+ file = vfsub_filp_open(fname, O_RDWR | O_CREAT | O_EXCL | O_LARGEFILE -+ /* | FMODE_NONOTIFY */, -+ S_IRUGO | S_IWUGO); -+ if (IS_ERR(file)) { -+ if (!silent) -+ pr_err("open %s(%ld)\n", fname, PTR_ERR(file)); -+ return file; -+ } -+ -+ /* keep file count */ -+ h_parent = dget_parent(file->f_dentry); -+ h_dir = h_parent->d_inode; -+ mutex_lock_nested(&h_dir->i_mutex, AuLsc_I_PARENT); -+ /* mnt_want_write() is unnecessary here */ -+ err = vfsub_unlink(h_dir, &file->f_path, /*force*/0); -+ mutex_unlock(&h_dir->i_mutex); -+ dput(h_parent); -+ if (unlikely(err)) { -+ if (!silent) -+ pr_err("unlink %s(%d)\n", fname, err); -+ goto out; -+ } -+ -+ err = -EINVAL; -+ d = file->f_dentry; -+ if (unlikely(sb == d->d_sb)) { -+ if (!silent) -+ pr_err("%s must be outside\n", fname); -+ goto out; -+ } -+ if (unlikely(au_test_fs_bad_xino(d->d_sb))) { -+ if (!silent) -+ pr_err("xino doesn't support %s(%s)\n", -+ fname, au_sbtype(d->d_sb)); -+ goto out; -+ } -+ return file; /* success */ -+ -+out: -+ fput(file); -+ file = ERR_PTR(err); -+ return file; -+} -+ -+/* -+ * find another branch who is on the same filesystem of the specified -+ * branch{@btgt}. search until @bend. -+ */ -+static int is_sb_shared(struct super_block *sb, aufs_bindex_t btgt, -+ aufs_bindex_t bend) -+{ -+ aufs_bindex_t bindex; -+ struct super_block *tgt_sb = au_sbr_sb(sb, btgt); -+ -+ for (bindex = 0; bindex < btgt; bindex++) -+ if (unlikely(tgt_sb == au_sbr_sb(sb, bindex))) -+ return bindex; -+ for (bindex++; bindex <= bend; bindex++) -+ if (unlikely(tgt_sb == au_sbr_sb(sb, bindex))) -+ return bindex; -+ return -1; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * initialize the xinofile for the specified branch @br -+ * at the place/path where @base_file indicates. -+ * test whether another branch is on the same filesystem or not, -+ * if @do_test is true. -+ */ -+int au_xino_br(struct super_block *sb, struct au_branch *br, ino_t h_ino, -+ struct file *base_file, int do_test) -+{ -+ int err; -+ ino_t ino; -+ aufs_bindex_t bend, bindex; -+ struct au_branch *shared_br, *b; -+ struct file *file; -+ struct super_block *tgt_sb; -+ -+ shared_br = NULL; -+ bend = au_sbend(sb); -+ if (do_test) { -+ tgt_sb = br->br_mnt->mnt_sb; -+ for (bindex = 0; bindex <= bend; bindex++) { -+ b = au_sbr(sb, bindex); -+ if (tgt_sb == b->br_mnt->mnt_sb) { -+ shared_br = b; -+ break; -+ } -+ } -+ } -+ -+ if (!shared_br || !shared_br->br_xino.xi_file) { -+ struct au_xino_lock_dir ldir; -+ -+ au_xino_lock_dir(sb, base_file, &ldir); -+ /* mnt_want_write() is unnecessary here */ -+ file = au_xino_create2(base_file, NULL); -+ au_xino_unlock_dir(&ldir); -+ err = PTR_ERR(file); -+ if (IS_ERR(file)) -+ goto out; -+ br->br_xino.xi_file = file; -+ } else { -+ br->br_xino.xi_file = shared_br->br_xino.xi_file; -+ get_file(br->br_xino.xi_file); -+ } -+ -+ ino = AUFS_ROOT_INO; -+ err = au_xino_do_write(au_sbi(sb)->si_xwrite, br->br_xino.xi_file, -+ h_ino, ino); -+ if (unlikely(err)) { -+ fput(br->br_xino.xi_file); -+ br->br_xino.xi_file = NULL; -+ } -+ -+out: -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* trucate a xino bitmap file */ -+ -+/* todo: slow */ -+static int do_xib_restore(struct super_block *sb, struct file *file, void *page) -+{ -+ int err, bit; -+ ssize_t sz; -+ unsigned long pindex; -+ loff_t pos, pend; -+ struct au_sbinfo *sbinfo; -+ au_readf_t func; -+ ino_t *ino; -+ unsigned long *p; -+ -+ err = 0; -+ sbinfo = au_sbi(sb); -+ MtxMustLock(&sbinfo->si_xib_mtx); -+ p = sbinfo->si_xib_buf; -+ func = sbinfo->si_xread; -+ pend = i_size_read(file->f_dentry->d_inode); -+ pos = 0; -+ while (pos < pend) { -+ sz = xino_fread(func, file, page, PAGE_SIZE, &pos); -+ err = sz; -+ if (unlikely(sz <= 0)) -+ goto out; -+ -+ err = 0; -+ for (ino = page; sz > 0; ino++, sz -= sizeof(ino)) { -+ if (unlikely(*ino < AUFS_FIRST_INO)) -+ continue; -+ -+ xib_calc_bit(*ino, &pindex, &bit); -+ AuDebugOn(page_bits <= bit); -+ err = xib_pindex(sb, pindex); -+ if (!err) -+ set_bit(bit, p); -+ else -+ goto out; -+ } -+ } -+ -+out: -+ return err; -+} -+ -+static int xib_restore(struct super_block *sb) -+{ -+ int err; -+ aufs_bindex_t bindex, bend; -+ void *page; -+ -+ err = -ENOMEM; -+ page = (void *)__get_free_page(GFP_NOFS); -+ if (unlikely(!page)) -+ goto out; -+ -+ err = 0; -+ bend = au_sbend(sb); -+ for (bindex = 0; !err && bindex <= bend; bindex++) -+ if (!bindex || is_sb_shared(sb, bindex, bindex - 1) < 0) -+ err = do_xib_restore -+ (sb, au_sbr(sb, bindex)->br_xino.xi_file, page); -+ else -+ AuDbg("b%d\n", bindex); -+ free_page((unsigned long)page); -+ -+out: -+ return err; -+} -+ -+int au_xib_trunc(struct super_block *sb) -+{ -+ int err; -+ ssize_t sz; -+ loff_t pos; -+ struct au_xino_lock_dir ldir; -+ struct au_sbinfo *sbinfo; -+ unsigned long *p; -+ struct file *file; -+ -+ SiMustWriteLock(sb); -+ -+ err = 0; -+ sbinfo = au_sbi(sb); -+ if (!au_opt_test(sbinfo->si_mntflags, XINO)) -+ goto out; -+ -+ file = sbinfo->si_xib; -+ if (i_size_read(file->f_dentry->d_inode) <= PAGE_SIZE) -+ goto out; -+ -+ au_xino_lock_dir(sb, file, &ldir); -+ /* mnt_want_write() is unnecessary here */ -+ file = au_xino_create2(sbinfo->si_xib, NULL); -+ au_xino_unlock_dir(&ldir); -+ err = PTR_ERR(file); -+ if (IS_ERR(file)) -+ goto out; -+ fput(sbinfo->si_xib); -+ sbinfo->si_xib = file; -+ -+ p = sbinfo->si_xib_buf; -+ memset(p, 0, PAGE_SIZE); -+ pos = 0; -+ sz = xino_fwrite(sbinfo->si_xwrite, sbinfo->si_xib, p, PAGE_SIZE, &pos); -+ if (unlikely(sz != PAGE_SIZE)) { -+ err = sz; -+ AuIOErr("err %d\n", err); -+ if (sz >= 0) -+ err = -EIO; -+ goto out; -+ } -+ -+ mutex_lock(&sbinfo->si_xib_mtx); -+ /* mnt_want_write() is unnecessary here */ -+ err = xib_restore(sb); -+ mutex_unlock(&sbinfo->si_xib_mtx); -+ -+out: -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * xino mount option handlers -+ */ -+static au_readf_t find_readf(struct file *h_file) -+{ -+ const struct file_operations *fop = h_file->f_op; -+ -+ if (fop) { -+ if (fop->read) -+ return fop->read; -+ if (fop->aio_read) -+ return do_sync_read; -+ } -+ return ERR_PTR(-ENOSYS); -+} -+ -+static au_writef_t find_writef(struct file *h_file) -+{ -+ const struct file_operations *fop = h_file->f_op; -+ -+ if (fop) { -+ if (fop->write) -+ return fop->write; -+ if (fop->aio_write) -+ return do_sync_write; -+ } -+ return ERR_PTR(-ENOSYS); -+} -+ -+/* xino bitmap */ -+static void xino_clear_xib(struct super_block *sb) -+{ -+ struct au_sbinfo *sbinfo; -+ -+ SiMustWriteLock(sb); -+ -+ sbinfo = au_sbi(sb); -+ sbinfo->si_xread = NULL; -+ sbinfo->si_xwrite = NULL; -+ if (sbinfo->si_xib) -+ fput(sbinfo->si_xib); -+ sbinfo->si_xib = NULL; -+ free_page((unsigned long)sbinfo->si_xib_buf); -+ sbinfo->si_xib_buf = NULL; -+} -+ -+static int au_xino_set_xib(struct super_block *sb, struct file *base) -+{ -+ int err; -+ loff_t pos; -+ struct au_sbinfo *sbinfo; -+ struct file *file; -+ -+ SiMustWriteLock(sb); -+ -+ sbinfo = au_sbi(sb); -+ file = au_xino_create2(base, sbinfo->si_xib); -+ err = PTR_ERR(file); -+ if (IS_ERR(file)) -+ goto out; -+ if (sbinfo->si_xib) -+ fput(sbinfo->si_xib); -+ sbinfo->si_xib = file; -+ sbinfo->si_xread = find_readf(file); -+ sbinfo->si_xwrite = find_writef(file); -+ -+ err = -ENOMEM; -+ if (!sbinfo->si_xib_buf) -+ sbinfo->si_xib_buf = (void *)get_zeroed_page(GFP_NOFS); -+ if (unlikely(!sbinfo->si_xib_buf)) -+ goto out_unset; -+ -+ sbinfo->si_xib_last_pindex = 0; -+ sbinfo->si_xib_next_bit = 0; -+ if (i_size_read(file->f_dentry->d_inode) < PAGE_SIZE) { -+ pos = 0; -+ err = xino_fwrite(sbinfo->si_xwrite, file, sbinfo->si_xib_buf, -+ PAGE_SIZE, &pos); -+ if (unlikely(err != PAGE_SIZE)) -+ goto out_free; -+ } -+ err = 0; -+ goto out; /* success */ -+ -+out_free: -+ free_page((unsigned long)sbinfo->si_xib_buf); -+ sbinfo->si_xib_buf = NULL; -+ if (err >= 0) -+ err = -EIO; -+out_unset: -+ fput(sbinfo->si_xib); -+ sbinfo->si_xib = NULL; -+ sbinfo->si_xread = NULL; -+ sbinfo->si_xwrite = NULL; -+out: -+ return err; -+} -+ -+/* xino for each branch */ -+static void xino_clear_br(struct super_block *sb) -+{ -+ aufs_bindex_t bindex, bend; -+ struct au_branch *br; -+ -+ bend = au_sbend(sb); -+ for (bindex = 0; bindex <= bend; bindex++) { -+ br = au_sbr(sb, bindex); -+ if (!br || !br->br_xino.xi_file) -+ continue; -+ -+ fput(br->br_xino.xi_file); -+ br->br_xino.xi_file = NULL; -+ } -+} -+ -+static int au_xino_set_br(struct super_block *sb, struct file *base) -+{ -+ int err; -+ ino_t ino; -+ aufs_bindex_t bindex, bend, bshared; -+ struct { -+ struct file *old, *new; -+ } *fpair, *p; -+ struct au_branch *br; -+ struct inode *inode; -+ au_writef_t writef; -+ -+ SiMustWriteLock(sb); -+ -+ err = -ENOMEM; -+ bend = au_sbend(sb); -+ fpair = kcalloc(bend + 1, sizeof(*fpair), GFP_NOFS); -+ if (unlikely(!fpair)) -+ goto out; -+ -+ inode = sb->s_root->d_inode; -+ ino = AUFS_ROOT_INO; -+ writef = au_sbi(sb)->si_xwrite; -+ for (bindex = 0, p = fpair; bindex <= bend; bindex++, p++) { -+ br = au_sbr(sb, bindex); -+ bshared = is_sb_shared(sb, bindex, bindex - 1); -+ if (bshared >= 0) { -+ /* shared xino */ -+ *p = fpair[bshared]; -+ get_file(p->new); -+ } -+ -+ if (!p->new) { -+ /* new xino */ -+ p->old = br->br_xino.xi_file; -+ p->new = au_xino_create2(base, br->br_xino.xi_file); -+ err = PTR_ERR(p->new); -+ if (IS_ERR(p->new)) { -+ p->new = NULL; -+ goto out_pair; -+ } -+ } -+ -+ err = au_xino_do_write(writef, p->new, -+ au_h_iptr(inode, bindex)->i_ino, ino); -+ if (unlikely(err)) -+ goto out_pair; -+ } -+ -+ for (bindex = 0, p = fpair; bindex <= bend; bindex++, p++) { -+ br = au_sbr(sb, bindex); -+ if (br->br_xino.xi_file) -+ fput(br->br_xino.xi_file); -+ get_file(p->new); -+ br->br_xino.xi_file = p->new; -+ } -+ -+out_pair: -+ for (bindex = 0, p = fpair; bindex <= bend; bindex++, p++) -+ if (p->new) -+ fput(p->new); -+ else -+ break; -+ kfree(fpair); -+out: -+ return err; -+} -+ -+void au_xino_clr(struct super_block *sb) -+{ -+ struct au_sbinfo *sbinfo; -+ -+ au_xigen_clr(sb); -+ xino_clear_xib(sb); -+ xino_clear_br(sb); -+ sbinfo = au_sbi(sb); -+ /* lvalue, do not call au_mntflags() */ -+ au_opt_clr(sbinfo->si_mntflags, XINO); -+} -+ -+int au_xino_set(struct super_block *sb, struct au_opt_xino *xino, int remount) -+{ -+ int err, skip; -+ struct dentry *parent, *cur_parent; -+ struct qstr *dname, *cur_name; -+ struct file *cur_xino; -+ struct inode *dir; -+ struct au_sbinfo *sbinfo; -+ -+ SiMustWriteLock(sb); -+ -+ err = 0; -+ sbinfo = au_sbi(sb); -+ parent = dget_parent(xino->file->f_dentry); -+ if (remount) { -+ skip = 0; -+ dname = &xino->file->f_dentry->d_name; -+ cur_xino = sbinfo->si_xib; -+ if (cur_xino) { -+ cur_parent = dget_parent(cur_xino->f_dentry); -+ cur_name = &cur_xino->f_dentry->d_name; -+ skip = (cur_parent == parent -+ && dname->len == cur_name->len -+ && !memcmp(dname->name, cur_name->name, -+ dname->len)); -+ dput(cur_parent); -+ } -+ if (skip) -+ goto out; -+ } -+ -+ au_opt_set(sbinfo->si_mntflags, XINO); -+ dir = parent->d_inode; -+ mutex_lock_nested(&dir->i_mutex, AuLsc_I_PARENT); -+ /* mnt_want_write() is unnecessary here */ -+ err = au_xino_set_xib(sb, xino->file); -+ if (!err) -+ err = au_xigen_set(sb, xino->file); -+ if (!err) -+ err = au_xino_set_br(sb, xino->file); -+ mutex_unlock(&dir->i_mutex); -+ if (!err) -+ goto out; /* success */ -+ -+ /* reset all */ -+ AuIOErr("failed creating xino(%d).\n", err); -+ -+out: -+ dput(parent); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * create a xinofile at the default place/path. -+ */ -+struct file *au_xino_def(struct super_block *sb) -+{ -+ struct file *file; -+ char *page, *p; -+ struct au_branch *br; -+ struct super_block *h_sb; -+ struct path path; -+ aufs_bindex_t bend, bindex, bwr; -+ -+ br = NULL; -+ bend = au_sbend(sb); -+ bwr = -1; -+ for (bindex = 0; bindex <= bend; bindex++) { -+ br = au_sbr(sb, bindex); -+ if (au_br_writable(br->br_perm) -+ && !au_test_fs_bad_xino(br->br_mnt->mnt_sb)) { -+ bwr = bindex; -+ break; -+ } -+ } -+ -+ if (bwr >= 0) { -+ file = ERR_PTR(-ENOMEM); -+ page = __getname_gfp(GFP_NOFS); -+ if (unlikely(!page)) -+ goto out; -+ path.mnt = br->br_mnt; -+ path.dentry = au_h_dptr(sb->s_root, bwr); -+ p = d_path(&path, page, PATH_MAX - sizeof(AUFS_XINO_FNAME)); -+ file = (void *)p; -+ if (!IS_ERR(p)) { -+ strcat(p, "/" AUFS_XINO_FNAME); -+ AuDbg("%s\n", p); -+ file = au_xino_create(sb, p, /*silent*/0); -+ if (!IS_ERR(file)) -+ au_xino_brid_set(sb, br->br_id); -+ } -+ __putname(page); -+ } else { -+ file = au_xino_create(sb, AUFS_XINO_DEFPATH, /*silent*/0); -+ if (IS_ERR(file)) -+ goto out; -+ h_sb = file->f_dentry->d_sb; -+ if (unlikely(au_test_fs_bad_xino(h_sb))) { -+ pr_err("xino doesn't support %s(%s)\n", -+ AUFS_XINO_DEFPATH, au_sbtype(h_sb)); -+ fput(file); -+ file = ERR_PTR(-EINVAL); -+ } -+ if (!IS_ERR(file)) -+ au_xino_brid_set(sb, -1); -+ } -+ -+out: -+ return file; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+int au_xino_path(struct seq_file *seq, struct file *file) -+{ -+ int err; -+ -+ err = au_seq_path(seq, &file->f_path); -+ if (unlikely(err < 0)) -+ goto out; -+ -+ err = 0; -+#define Deleted "\\040(deleted)" -+ seq->count -= sizeof(Deleted) - 1; -+ AuDebugOn(memcmp(seq->buf + seq->count, Deleted, -+ sizeof(Deleted) - 1)); -+#undef Deleted -+ -+out: -+ return err; -+} -diff -Nur linux-2.6.36.orig/fs/file_table.c linux-2.6.36/fs/file_table.c ---- linux-2.6.36.orig/fs/file_table.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/fs/file_table.c 2011-01-10 19:52:38.000000000 +0100 -@@ -394,6 +394,8 @@ - } - } - -+EXPORT_SYMBOL(file_sb_list_del); -+ - #ifdef CONFIG_SMP - - /* -diff -Nur linux-2.6.36.orig/fs/inode.c linux-2.6.36/fs/inode.c ---- linux-2.6.36.orig/fs/inode.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/fs/inode.c 2011-01-10 19:52:38.000000000 +0100 -@@ -83,6 +83,7 @@ - * the i_state of an inode while it is in use.. - */ - DEFINE_SPINLOCK(inode_lock); -+EXPORT_SYMBOL(inode_lock); - - /* - * iprune_sem provides exclusion between the kswapd or try_to_free_pages -diff -Nur linux-2.6.36.orig/fs/namei.c linux-2.6.36/fs/namei.c ---- linux-2.6.36.orig/fs/namei.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/fs/namei.c 2011-01-10 19:52:38.000000000 +0100 -@@ -347,6 +347,7 @@ - - return 0; - } -+EXPORT_SYMBOL(deny_write_access); - - /** - * path_get - get a reference to a path -@@ -1159,7 +1160,7 @@ - * needs parent already locked. Doesn't follow mounts. - * SMP-safe. - */ --static struct dentry *lookup_hash(struct nameidata *nd) -+struct dentry *lookup_hash(struct nameidata *nd) - { - int err; - -@@ -1168,8 +1169,9 @@ - return ERR_PTR(err); - return __lookup_hash(&nd->last, nd->path.dentry, nd); - } -+EXPORT_SYMBOL(lookup_hash); - --static int __lookup_one_len(const char *name, struct qstr *this, -+int __lookup_one_len(const char *name, struct qstr *this, - struct dentry *base, int len) - { - unsigned long hash; -@@ -1190,6 +1192,7 @@ - this->hash = end_name_hash(hash); - return 0; - } -+EXPORT_SYMBOL(__lookup_one_len); - - /** - * lookup_one_len - filesystem helper to lookup single pathname component -diff -Nur linux-2.6.36.orig/fs/namei.c.orig linux-2.6.36/fs/namei.c.orig ---- linux-2.6.36.orig/fs/namei.c.orig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/namei.c.orig 2011-01-10 19:52:38.000000000 +0100 -@@ -0,0 +1,2921 @@ -+/* -+ * linux/fs/namei.c -+ * -+ * Copyright (C) 1991, 1992 Linus Torvalds -+ */ -+ -+/* -+ * Some corrections by tytso. -+ */ -+ -+/* [Feb 1997 T. Schoebel-Theuer] Complete rewrite of the pathname -+ * lookup logic. -+ */ -+/* [Feb-Apr 2000, AV] Rewrite to the new namespace architecture. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "internal.h" -+ -+/* [Feb-1997 T. Schoebel-Theuer] -+ * Fundamental changes in the pathname lookup mechanisms (namei) -+ * were necessary because of omirr. The reason is that omirr needs -+ * to know the _real_ pathname, not the user-supplied one, in case -+ * of symlinks (and also when transname replacements occur). -+ * -+ * The new code replaces the old recursive symlink resolution with -+ * an iterative one (in case of non-nested symlink chains). It does -+ * this with calls to _follow_link(). -+ * As a side effect, dir_namei(), _namei() and follow_link() are now -+ * replaced with a single function lookup_dentry() that can handle all -+ * the special cases of the former code. -+ * -+ * With the new dcache, the pathname is stored at each inode, at least as -+ * long as the refcount of the inode is positive. As a side effect, the -+ * size of the dcache depends on the inode cache and thus is dynamic. -+ * -+ * [29-Apr-1998 C. Scott Ananian] Updated above description of symlink -+ * resolution to correspond with current state of the code. -+ * -+ * Note that the symlink resolution is not *completely* iterative. -+ * There is still a significant amount of tail- and mid- recursion in -+ * the algorithm. Also, note that _readlink() is not used in -+ * lookup_dentry(): lookup_dentry() on the result of _readlink() -+ * may return different results than _follow_link(). Many virtual -+ * filesystems (including /proc) exhibit this behavior. -+ */ -+ -+/* [24-Feb-97 T. Schoebel-Theuer] Side effects caused by new implementation: -+ * New symlink semantics: when open() is called with flags O_CREAT | O_EXCL -+ * and the name already exists in form of a symlink, try to create the new -+ * name indicated by the symlink. The old code always complained that the -+ * name already exists, due to not following the symlink even if its target -+ * is nonexistent. The new semantics affects also mknod() and link() when -+ * the name is a symlink pointing to a non-existant name. -+ * -+ * I don't know which semantics is the right one, since I have no access -+ * to standards. But I found by trial that HP-UX 9.0 has the full "new" -+ * semantics implemented, while SunOS 4.1.1 and Solaris (SunOS 5.4) have the -+ * "old" one. Personally, I think the new semantics is much more logical. -+ * Note that "ln old new" where "new" is a symlink pointing to a non-existing -+ * file does succeed in both HP-UX and SunOs, but not in Solaris -+ * and in the old Linux semantics. -+ */ -+ -+/* [16-Dec-97 Kevin Buhr] For security reasons, we change some symlink -+ * semantics. See the comments in "open_namei" and "do_link" below. -+ * -+ * [10-Sep-98 Alan Modra] Another symlink change. -+ */ -+ -+/* [Feb-Apr 2000 AV] Complete rewrite. Rules for symlinks: -+ * inside the path - always follow. -+ * in the last component in creation/removal/renaming - never follow. -+ * if LOOKUP_FOLLOW passed - follow. -+ * if the pathname has trailing slashes - follow. -+ * otherwise - don't follow. -+ * (applied in that order). -+ * -+ * [Jun 2000 AV] Inconsistent behaviour of open() in case if flags==O_CREAT -+ * restored for 2.4. This is the last surviving part of old 4.2BSD bug. -+ * During the 2.4 we need to fix the userland stuff depending on it - -+ * hopefully we will be able to get rid of that wart in 2.5. So far only -+ * XEmacs seems to be relying on it... -+ */ -+/* -+ * [Sep 2001 AV] Single-semaphore locking scheme (kudos to David Holland) -+ * implemented. Let's see if raised priority of ->s_vfs_rename_mutex gives -+ * any extra contention... -+ */ -+ -+/* In order to reduce some races, while at the same time doing additional -+ * checking and hopefully speeding things up, we copy filenames to the -+ * kernel data space before using them.. -+ * -+ * POSIX.1 2.4: an empty pathname is invalid (ENOENT). -+ * PATH_MAX includes the nul terminator --RR. -+ */ -+static int do_getname(const char __user *filename, char *page) -+{ -+ int retval; -+ unsigned long len = PATH_MAX; -+ -+ if (!segment_eq(get_fs(), KERNEL_DS)) { -+ if ((unsigned long) filename >= TASK_SIZE) -+ return -EFAULT; -+ if (TASK_SIZE - (unsigned long) filename < PATH_MAX) -+ len = TASK_SIZE - (unsigned long) filename; -+ } -+ -+ retval = strncpy_from_user(page, filename, len); -+ if (retval > 0) { -+ if (retval < len) -+ return 0; -+ return -ENAMETOOLONG; -+ } else if (!retval) -+ retval = -ENOENT; -+ return retval; -+} -+ -+char * getname(const char __user * filename) -+{ -+ char *tmp, *result; -+ -+ result = ERR_PTR(-ENOMEM); -+ tmp = __getname(); -+ if (tmp) { -+ int retval = do_getname(filename, tmp); -+ -+ result = tmp; -+ if (retval < 0) { -+ __putname(tmp); -+ result = ERR_PTR(retval); -+ } -+ } -+ audit_getname(result); -+ return result; -+} -+ -+#ifdef CONFIG_AUDITSYSCALL -+void putname(const char *name) -+{ -+ if (unlikely(!audit_dummy_context())) -+ audit_putname(name); -+ else -+ __putname(name); -+} -+EXPORT_SYMBOL(putname); -+#endif -+ -+/* -+ * This does basic POSIX ACL permission checking -+ */ -+static int acl_permission_check(struct inode *inode, int mask, -+ int (*check_acl)(struct inode *inode, int mask)) -+{ -+ umode_t mode = inode->i_mode; -+ -+ mask &= MAY_READ | MAY_WRITE | MAY_EXEC; -+ -+ if (current_fsuid() == inode->i_uid) -+ mode >>= 6; -+ else { -+ if (IS_POSIXACL(inode) && (mode & S_IRWXG) && check_acl) { -+ int error = check_acl(inode, mask); -+ if (error != -EAGAIN) -+ return error; -+ } -+ -+ if (in_group_p(inode->i_gid)) -+ mode >>= 3; -+ } -+ -+ /* -+ * If the DACs are ok we don't need any capability check. -+ */ -+ if ((mask & ~mode) == 0) -+ return 0; -+ return -EACCES; -+} -+ -+/** -+ * generic_permission - check for access rights on a Posix-like filesystem -+ * @inode: inode to check access rights for -+ * @mask: right to check for (%MAY_READ, %MAY_WRITE, %MAY_EXEC) -+ * @check_acl: optional callback to check for Posix ACLs -+ * -+ * Used to check for read/write/execute permissions on a file. -+ * We use "fsuid" for this, letting us set arbitrary permissions -+ * for filesystem access without changing the "normal" uids which -+ * are used for other things.. -+ */ -+int generic_permission(struct inode *inode, int mask, -+ int (*check_acl)(struct inode *inode, int mask)) -+{ -+ int ret; -+ -+ /* -+ * Do the basic POSIX ACL permission checks. -+ */ -+ ret = acl_permission_check(inode, mask, check_acl); -+ if (ret != -EACCES) -+ return ret; -+ -+ /* -+ * Read/write DACs are always overridable. -+ * Executable DACs are overridable if at least one exec bit is set. -+ */ -+ if (!(mask & MAY_EXEC) || execute_ok(inode)) -+ if (capable(CAP_DAC_OVERRIDE)) -+ return 0; -+ -+ /* -+ * Searching includes executable on directories, else just read. -+ */ -+ mask &= MAY_READ | MAY_WRITE | MAY_EXEC; -+ if (mask == MAY_READ || (S_ISDIR(inode->i_mode) && !(mask & MAY_WRITE))) -+ if (capable(CAP_DAC_READ_SEARCH)) -+ return 0; -+ -+ return -EACCES; -+} -+ -+/** -+ * inode_permission - check for access rights to a given inode -+ * @inode: inode to check permission on -+ * @mask: right to check for (%MAY_READ, %MAY_WRITE, %MAY_EXEC) -+ * -+ * Used to check for read/write/execute permissions on an inode. -+ * We use "fsuid" for this, letting us set arbitrary permissions -+ * for filesystem access without changing the "normal" uids which -+ * are used for other things. -+ */ -+int inode_permission(struct inode *inode, int mask) -+{ -+ int retval; -+ -+ if (mask & MAY_WRITE) { -+ umode_t mode = inode->i_mode; -+ -+ /* -+ * Nobody gets write access to a read-only fs. -+ */ -+ if (IS_RDONLY(inode) && -+ (S_ISREG(mode) || S_ISDIR(mode) || S_ISLNK(mode))) -+ return -EROFS; -+ -+ /* -+ * Nobody gets write access to an immutable file. -+ */ -+ if (IS_IMMUTABLE(inode)) -+ return -EACCES; -+ } -+ -+ if (inode->i_op->permission) -+ retval = inode->i_op->permission(inode, mask); -+ else -+ retval = generic_permission(inode, mask, inode->i_op->check_acl); -+ -+ if (retval) -+ return retval; -+ -+ retval = devcgroup_inode_permission(inode, mask); -+ if (retval) -+ return retval; -+ -+ return security_inode_permission(inode, mask); -+} -+ -+/** -+ * file_permission - check for additional access rights to a given file -+ * @file: file to check access rights for -+ * @mask: right to check for (%MAY_READ, %MAY_WRITE, %MAY_EXEC) -+ * -+ * Used to check for read/write/execute permissions on an already opened -+ * file. -+ * -+ * Note: -+ * Do not use this function in new code. All access checks should -+ * be done using inode_permission(). -+ */ -+int file_permission(struct file *file, int mask) -+{ -+ return inode_permission(file->f_path.dentry->d_inode, mask); -+} -+ -+/* -+ * get_write_access() gets write permission for a file. -+ * put_write_access() releases this write permission. -+ * This is used for regular files. -+ * We cannot support write (and maybe mmap read-write shared) accesses and -+ * MAP_DENYWRITE mmappings simultaneously. The i_writecount field of an inode -+ * can have the following values: -+ * 0: no writers, no VM_DENYWRITE mappings -+ * < 0: (-i_writecount) vm_area_structs with VM_DENYWRITE set exist -+ * > 0: (i_writecount) users are writing to the file. -+ * -+ * Normally we operate on that counter with atomic_{inc,dec} and it's safe -+ * except for the cases where we don't hold i_writecount yet. Then we need to -+ * use {get,deny}_write_access() - these functions check the sign and refuse -+ * to do the change if sign is wrong. Exclusion between them is provided by -+ * the inode->i_lock spinlock. -+ */ -+ -+int get_write_access(struct inode * inode) -+{ -+ spin_lock(&inode->i_lock); -+ if (atomic_read(&inode->i_writecount) < 0) { -+ spin_unlock(&inode->i_lock); -+ return -ETXTBSY; -+ } -+ atomic_inc(&inode->i_writecount); -+ spin_unlock(&inode->i_lock); -+ -+ return 0; -+} -+ -+int deny_write_access(struct file * file) -+{ -+ struct inode *inode = file->f_path.dentry->d_inode; -+ -+ spin_lock(&inode->i_lock); -+ if (atomic_read(&inode->i_writecount) > 0) { -+ spin_unlock(&inode->i_lock); -+ return -ETXTBSY; -+ } -+ atomic_dec(&inode->i_writecount); -+ spin_unlock(&inode->i_lock); -+ -+ return 0; -+} -+EXPORT_SYMBOL(deny_write_access); -+ -+/** -+ * path_get - get a reference to a path -+ * @path: path to get the reference to -+ * -+ * Given a path increment the reference count to the dentry and the vfsmount. -+ */ -+void path_get(struct path *path) -+{ -+ mntget(path->mnt); -+ dget(path->dentry); -+} -+EXPORT_SYMBOL(path_get); -+ -+/** -+ * path_put - put a reference to a path -+ * @path: path to put the reference to -+ * -+ * Given a path decrement the reference count to the dentry and the vfsmount. -+ */ -+void path_put(struct path *path) -+{ -+ dput(path->dentry); -+ mntput(path->mnt); -+} -+EXPORT_SYMBOL(path_put); -+ -+/** -+ * release_open_intent - free up open intent resources -+ * @nd: pointer to nameidata -+ */ -+void release_open_intent(struct nameidata *nd) -+{ -+ if (nd->intent.open.file->f_path.dentry == NULL) -+ put_filp(nd->intent.open.file); -+ else -+ fput(nd->intent.open.file); -+} -+ -+static inline struct dentry * -+do_revalidate(struct dentry *dentry, struct nameidata *nd) -+{ -+ int status = dentry->d_op->d_revalidate(dentry, nd); -+ if (unlikely(status <= 0)) { -+ /* -+ * The dentry failed validation. -+ * If d_revalidate returned 0 attempt to invalidate -+ * the dentry otherwise d_revalidate is asking us -+ * to return a fail status. -+ */ -+ if (!status) { -+ if (!d_invalidate(dentry)) { -+ dput(dentry); -+ dentry = NULL; -+ } -+ } else { -+ dput(dentry); -+ dentry = ERR_PTR(status); -+ } -+ } -+ return dentry; -+} -+ -+/* -+ * force_reval_path - force revalidation of a dentry -+ * -+ * In some situations the path walking code will trust dentries without -+ * revalidating them. This causes problems for filesystems that depend on -+ * d_revalidate to handle file opens (e.g. NFSv4). When FS_REVAL_DOT is set -+ * (which indicates that it's possible for the dentry to go stale), force -+ * a d_revalidate call before proceeding. -+ * -+ * Returns 0 if the revalidation was successful. If the revalidation fails, -+ * either return the error returned by d_revalidate or -ESTALE if the -+ * revalidation it just returned 0. If d_revalidate returns 0, we attempt to -+ * invalidate the dentry. It's up to the caller to handle putting references -+ * to the path if necessary. -+ */ -+static int -+force_reval_path(struct path *path, struct nameidata *nd) -+{ -+ int status; -+ struct dentry *dentry = path->dentry; -+ -+ /* -+ * only check on filesystems where it's possible for the dentry to -+ * become stale. It's assumed that if this flag is set then the -+ * d_revalidate op will also be defined. -+ */ -+ if (!(dentry->d_sb->s_type->fs_flags & FS_REVAL_DOT)) -+ return 0; -+ -+ status = dentry->d_op->d_revalidate(dentry, nd); -+ if (status > 0) -+ return 0; -+ -+ if (!status) { -+ d_invalidate(dentry); -+ status = -ESTALE; -+ } -+ return status; -+} -+ -+/* -+ * Short-cut version of permission(), for calling on directories -+ * during pathname resolution. Combines parts of permission() -+ * and generic_permission(), and tests ONLY for MAY_EXEC permission. -+ * -+ * If appropriate, check DAC only. If not appropriate, or -+ * short-cut DAC fails, then call ->permission() to do more -+ * complete permission check. -+ */ -+static int exec_permission(struct inode *inode) -+{ -+ int ret; -+ -+ if (inode->i_op->permission) { -+ ret = inode->i_op->permission(inode, MAY_EXEC); -+ if (!ret) -+ goto ok; -+ return ret; -+ } -+ ret = acl_permission_check(inode, MAY_EXEC, inode->i_op->check_acl); -+ if (!ret) -+ goto ok; -+ -+ if (capable(CAP_DAC_OVERRIDE) || capable(CAP_DAC_READ_SEARCH)) -+ goto ok; -+ -+ return ret; -+ok: -+ return security_inode_permission(inode, MAY_EXEC); -+} -+ -+static __always_inline void set_root(struct nameidata *nd) -+{ -+ if (!nd->root.mnt) -+ get_fs_root(current->fs, &nd->root); -+} -+ -+static int link_path_walk(const char *, struct nameidata *); -+ -+static __always_inline int __vfs_follow_link(struct nameidata *nd, const char *link) -+{ -+ if (IS_ERR(link)) -+ goto fail; -+ -+ if (*link == '/') { -+ set_root(nd); -+ path_put(&nd->path); -+ nd->path = nd->root; -+ path_get(&nd->root); -+ } -+ -+ return link_path_walk(link, nd); -+fail: -+ path_put(&nd->path); -+ return PTR_ERR(link); -+} -+ -+static void path_put_conditional(struct path *path, struct nameidata *nd) -+{ -+ dput(path->dentry); -+ if (path->mnt != nd->path.mnt) -+ mntput(path->mnt); -+} -+ -+static inline void path_to_nameidata(struct path *path, struct nameidata *nd) -+{ -+ dput(nd->path.dentry); -+ if (nd->path.mnt != path->mnt) { -+ mntput(nd->path.mnt); -+ nd->path.mnt = path->mnt; -+ } -+ nd->path.dentry = path->dentry; -+} -+ -+static __always_inline int -+__do_follow_link(struct path *path, struct nameidata *nd, void **p) -+{ -+ int error; -+ struct dentry *dentry = path->dentry; -+ -+ touch_atime(path->mnt, dentry); -+ nd_set_link(nd, NULL); -+ -+ if (path->mnt != nd->path.mnt) { -+ path_to_nameidata(path, nd); -+ dget(dentry); -+ } -+ mntget(path->mnt); -+ nd->last_type = LAST_BIND; -+ *p = dentry->d_inode->i_op->follow_link(dentry, nd); -+ error = PTR_ERR(*p); -+ if (!IS_ERR(*p)) { -+ char *s = nd_get_link(nd); -+ error = 0; -+ if (s) -+ error = __vfs_follow_link(nd, s); -+ else if (nd->last_type == LAST_BIND) { -+ error = force_reval_path(&nd->path, nd); -+ if (error) -+ path_put(&nd->path); -+ } -+ } -+ return error; -+} -+ -+/* -+ * This limits recursive symlink follows to 8, while -+ * limiting consecutive symlinks to 40. -+ * -+ * Without that kind of total limit, nasty chains of consecutive -+ * symlinks can cause almost arbitrarily long lookups. -+ */ -+static inline int do_follow_link(struct path *path, struct nameidata *nd) -+{ -+ void *cookie; -+ int err = -ELOOP; -+ if (current->link_count >= MAX_NESTED_LINKS) -+ goto loop; -+ if (current->total_link_count >= 40) -+ goto loop; -+ BUG_ON(nd->depth >= MAX_NESTED_LINKS); -+ cond_resched(); -+ err = security_inode_follow_link(path->dentry, nd); -+ if (err) -+ goto loop; -+ current->link_count++; -+ current->total_link_count++; -+ nd->depth++; -+ err = __do_follow_link(path, nd, &cookie); -+ if (!IS_ERR(cookie) && path->dentry->d_inode->i_op->put_link) -+ path->dentry->d_inode->i_op->put_link(path->dentry, nd, cookie); -+ path_put(path); -+ current->link_count--; -+ nd->depth--; -+ return err; -+loop: -+ path_put_conditional(path, nd); -+ path_put(&nd->path); -+ return err; -+} -+ -+int follow_up(struct path *path) -+{ -+ struct vfsmount *parent; -+ struct dentry *mountpoint; -+ -+ br_read_lock(vfsmount_lock); -+ parent = path->mnt->mnt_parent; -+ if (parent == path->mnt) { -+ br_read_unlock(vfsmount_lock); -+ return 0; -+ } -+ mntget(parent); -+ mountpoint = dget(path->mnt->mnt_mountpoint); -+ br_read_unlock(vfsmount_lock); -+ dput(path->dentry); -+ path->dentry = mountpoint; -+ mntput(path->mnt); -+ path->mnt = parent; -+ return 1; -+} -+ -+/* no need for dcache_lock, as serialization is taken care in -+ * namespace.c -+ */ -+static int __follow_mount(struct path *path) -+{ -+ int res = 0; -+ while (d_mountpoint(path->dentry)) { -+ struct vfsmount *mounted = lookup_mnt(path); -+ if (!mounted) -+ break; -+ dput(path->dentry); -+ if (res) -+ mntput(path->mnt); -+ path->mnt = mounted; -+ path->dentry = dget(mounted->mnt_root); -+ res = 1; -+ } -+ return res; -+} -+ -+static void follow_mount(struct path *path) -+{ -+ while (d_mountpoint(path->dentry)) { -+ struct vfsmount *mounted = lookup_mnt(path); -+ if (!mounted) -+ break; -+ dput(path->dentry); -+ mntput(path->mnt); -+ path->mnt = mounted; -+ path->dentry = dget(mounted->mnt_root); -+ } -+} -+ -+/* no need for dcache_lock, as serialization is taken care in -+ * namespace.c -+ */ -+int follow_down(struct path *path) -+{ -+ struct vfsmount *mounted; -+ -+ mounted = lookup_mnt(path); -+ if (mounted) { -+ dput(path->dentry); -+ mntput(path->mnt); -+ path->mnt = mounted; -+ path->dentry = dget(mounted->mnt_root); -+ return 1; -+ } -+ return 0; -+} -+ -+static __always_inline void follow_dotdot(struct nameidata *nd) -+{ -+ set_root(nd); -+ -+ while(1) { -+ struct dentry *old = nd->path.dentry; -+ -+ if (nd->path.dentry == nd->root.dentry && -+ nd->path.mnt == nd->root.mnt) { -+ break; -+ } -+ if (nd->path.dentry != nd->path.mnt->mnt_root) { -+ /* rare case of legitimate dget_parent()... */ -+ nd->path.dentry = dget_parent(nd->path.dentry); -+ dput(old); -+ break; -+ } -+ if (!follow_up(&nd->path)) -+ break; -+ } -+ follow_mount(&nd->path); -+} -+ -+/* -+ * Allocate a dentry with name and parent, and perform a parent -+ * directory ->lookup on it. Returns the new dentry, or ERR_PTR -+ * on error. parent->d_inode->i_mutex must be held. d_lookup must -+ * have verified that no child exists while under i_mutex. -+ */ -+static struct dentry *d_alloc_and_lookup(struct dentry *parent, -+ struct qstr *name, struct nameidata *nd) -+{ -+ struct inode *inode = parent->d_inode; -+ struct dentry *dentry; -+ struct dentry *old; -+ -+ /* Don't create child dentry for a dead directory. */ -+ if (unlikely(IS_DEADDIR(inode))) -+ return ERR_PTR(-ENOENT); -+ -+ dentry = d_alloc(parent, name); -+ if (unlikely(!dentry)) -+ return ERR_PTR(-ENOMEM); -+ -+ old = inode->i_op->lookup(inode, dentry, nd); -+ if (unlikely(old)) { -+ dput(dentry); -+ dentry = old; -+ } -+ return dentry; -+} -+ -+/* -+ * It's more convoluted than I'd like it to be, but... it's still fairly -+ * small and for now I'd prefer to have fast path as straight as possible. -+ * It _is_ time-critical. -+ */ -+static int do_lookup(struct nameidata *nd, struct qstr *name, -+ struct path *path) -+{ -+ struct vfsmount *mnt = nd->path.mnt; -+ struct dentry *dentry, *parent; -+ struct inode *dir; -+ /* -+ * See if the low-level filesystem might want -+ * to use its own hash.. -+ */ -+ if (nd->path.dentry->d_op && nd->path.dentry->d_op->d_hash) { -+ int err = nd->path.dentry->d_op->d_hash(nd->path.dentry, name); -+ if (err < 0) -+ return err; -+ } -+ -+ /* -+ * Rename seqlock is not required here because in the off chance -+ * of a false negative due to a concurrent rename, we're going to -+ * do the non-racy lookup, below. -+ */ -+ dentry = __d_lookup(nd->path.dentry, name); -+ if (!dentry) -+ goto need_lookup; -+found: -+ if (dentry->d_op && dentry->d_op->d_revalidate) -+ goto need_revalidate; -+done: -+ path->mnt = mnt; -+ path->dentry = dentry; -+ __follow_mount(path); -+ return 0; -+ -+need_lookup: -+ parent = nd->path.dentry; -+ dir = parent->d_inode; -+ -+ mutex_lock(&dir->i_mutex); -+ /* -+ * First re-do the cached lookup just in case it was created -+ * while we waited for the directory semaphore, or the first -+ * lookup failed due to an unrelated rename. -+ * -+ * This could use version numbering or similar to avoid unnecessary -+ * cache lookups, but then we'd have to do the first lookup in the -+ * non-racy way. However in the common case here, everything should -+ * be hot in cache, so would it be a big win? -+ */ -+ dentry = d_lookup(parent, name); -+ if (likely(!dentry)) { -+ dentry = d_alloc_and_lookup(parent, name, nd); -+ mutex_unlock(&dir->i_mutex); -+ if (IS_ERR(dentry)) -+ goto fail; -+ goto done; -+ } -+ /* -+ * Uhhuh! Nasty case: the cache was re-populated while -+ * we waited on the semaphore. Need to revalidate. -+ */ -+ mutex_unlock(&dir->i_mutex); -+ goto found; -+ -+need_revalidate: -+ dentry = do_revalidate(dentry, nd); -+ if (!dentry) -+ goto need_lookup; -+ if (IS_ERR(dentry)) -+ goto fail; -+ goto done; -+ -+fail: -+ return PTR_ERR(dentry); -+} -+ -+/* -+ * This is a temporary kludge to deal with "automount" symlinks; proper -+ * solution is to trigger them on follow_mount(), so that do_lookup() -+ * would DTRT. To be killed before 2.6.34-final. -+ */ -+static inline int follow_on_final(struct inode *inode, unsigned lookup_flags) -+{ -+ return inode && unlikely(inode->i_op->follow_link) && -+ ((lookup_flags & LOOKUP_FOLLOW) || S_ISDIR(inode->i_mode)); -+} -+ -+/* -+ * Name resolution. -+ * This is the basic name resolution function, turning a pathname into -+ * the final dentry. We expect 'base' to be positive and a directory. -+ * -+ * Returns 0 and nd will have valid dentry and mnt on success. -+ * Returns error and drops reference to input namei data on failure. -+ */ -+static int link_path_walk(const char *name, struct nameidata *nd) -+{ -+ struct path next; -+ struct inode *inode; -+ int err; -+ unsigned int lookup_flags = nd->flags; -+ -+ while (*name=='/') -+ name++; -+ if (!*name) -+ goto return_reval; -+ -+ inode = nd->path.dentry->d_inode; -+ if (nd->depth) -+ lookup_flags = LOOKUP_FOLLOW | (nd->flags & LOOKUP_CONTINUE); -+ -+ /* At this point we know we have a real path component. */ -+ for(;;) { -+ unsigned long hash; -+ struct qstr this; -+ unsigned int c; -+ -+ nd->flags |= LOOKUP_CONTINUE; -+ err = exec_permission(inode); -+ if (err) -+ break; -+ -+ this.name = name; -+ c = *(const unsigned char *)name; -+ -+ hash = init_name_hash(); -+ do { -+ name++; -+ hash = partial_name_hash(c, hash); -+ c = *(const unsigned char *)name; -+ } while (c && (c != '/')); -+ this.len = name - (const char *) this.name; -+ this.hash = end_name_hash(hash); -+ -+ /* remove trailing slashes? */ -+ if (!c) -+ goto last_component; -+ while (*++name == '/'); -+ if (!*name) -+ goto last_with_slashes; -+ -+ /* -+ * "." and ".." are special - ".." especially so because it has -+ * to be able to know about the current root directory and -+ * parent relationships. -+ */ -+ if (this.name[0] == '.') switch (this.len) { -+ default: -+ break; -+ case 2: -+ if (this.name[1] != '.') -+ break; -+ follow_dotdot(nd); -+ inode = nd->path.dentry->d_inode; -+ /* fallthrough */ -+ case 1: -+ continue; -+ } -+ /* This does the actual lookups.. */ -+ err = do_lookup(nd, &this, &next); -+ if (err) -+ break; -+ -+ err = -ENOENT; -+ inode = next.dentry->d_inode; -+ if (!inode) -+ goto out_dput; -+ -+ if (inode->i_op->follow_link) { -+ err = do_follow_link(&next, nd); -+ if (err) -+ goto return_err; -+ err = -ENOENT; -+ inode = nd->path.dentry->d_inode; -+ if (!inode) -+ break; -+ } else -+ path_to_nameidata(&next, nd); -+ err = -ENOTDIR; -+ if (!inode->i_op->lookup) -+ break; -+ continue; -+ /* here ends the main loop */ -+ -+last_with_slashes: -+ lookup_flags |= LOOKUP_FOLLOW | LOOKUP_DIRECTORY; -+last_component: -+ /* Clear LOOKUP_CONTINUE iff it was previously unset */ -+ nd->flags &= lookup_flags | ~LOOKUP_CONTINUE; -+ if (lookup_flags & LOOKUP_PARENT) -+ goto lookup_parent; -+ if (this.name[0] == '.') switch (this.len) { -+ default: -+ break; -+ case 2: -+ if (this.name[1] != '.') -+ break; -+ follow_dotdot(nd); -+ inode = nd->path.dentry->d_inode; -+ /* fallthrough */ -+ case 1: -+ goto return_reval; -+ } -+ err = do_lookup(nd, &this, &next); -+ if (err) -+ break; -+ inode = next.dentry->d_inode; -+ if (follow_on_final(inode, lookup_flags)) { -+ err = do_follow_link(&next, nd); -+ if (err) -+ goto return_err; -+ inode = nd->path.dentry->d_inode; -+ } else -+ path_to_nameidata(&next, nd); -+ err = -ENOENT; -+ if (!inode) -+ break; -+ if (lookup_flags & LOOKUP_DIRECTORY) { -+ err = -ENOTDIR; -+ if (!inode->i_op->lookup) -+ break; -+ } -+ goto return_base; -+lookup_parent: -+ nd->last = this; -+ nd->last_type = LAST_NORM; -+ if (this.name[0] != '.') -+ goto return_base; -+ if (this.len == 1) -+ nd->last_type = LAST_DOT; -+ else if (this.len == 2 && this.name[1] == '.') -+ nd->last_type = LAST_DOTDOT; -+ else -+ goto return_base; -+return_reval: -+ /* -+ * We bypassed the ordinary revalidation routines. -+ * We may need to check the cached dentry for staleness. -+ */ -+ if (nd->path.dentry && nd->path.dentry->d_sb && -+ (nd->path.dentry->d_sb->s_type->fs_flags & FS_REVAL_DOT)) { -+ err = -ESTALE; -+ /* Note: we do not d_invalidate() */ -+ if (!nd->path.dentry->d_op->d_revalidate( -+ nd->path.dentry, nd)) -+ break; -+ } -+return_base: -+ return 0; -+out_dput: -+ path_put_conditional(&next, nd); -+ break; -+ } -+ path_put(&nd->path); -+return_err: -+ return err; -+} -+ -+static int path_walk(const char *name, struct nameidata *nd) -+{ -+ struct path save = nd->path; -+ int result; -+ -+ current->total_link_count = 0; -+ -+ /* make sure the stuff we saved doesn't go away */ -+ path_get(&save); -+ -+ result = link_path_walk(name, nd); -+ if (result == -ESTALE) { -+ /* nd->path had been dropped */ -+ current->total_link_count = 0; -+ nd->path = save; -+ path_get(&nd->path); -+ nd->flags |= LOOKUP_REVAL; -+ result = link_path_walk(name, nd); -+ } -+ -+ path_put(&save); -+ -+ return result; -+} -+ -+static int path_init(int dfd, const char *name, unsigned int flags, struct nameidata *nd) -+{ -+ int retval = 0; -+ int fput_needed; -+ struct file *file; -+ -+ nd->last_type = LAST_ROOT; /* if there are only slashes... */ -+ nd->flags = flags; -+ nd->depth = 0; -+ nd->root.mnt = NULL; -+ -+ if (*name=='/') { -+ set_root(nd); -+ nd->path = nd->root; -+ path_get(&nd->root); -+ } else if (dfd == AT_FDCWD) { -+ get_fs_pwd(current->fs, &nd->path); -+ } else { -+ struct dentry *dentry; -+ -+ file = fget_light(dfd, &fput_needed); -+ retval = -EBADF; -+ if (!file) -+ goto out_fail; -+ -+ dentry = file->f_path.dentry; -+ -+ retval = -ENOTDIR; -+ if (!S_ISDIR(dentry->d_inode->i_mode)) -+ goto fput_fail; -+ -+ retval = file_permission(file, MAY_EXEC); -+ if (retval) -+ goto fput_fail; -+ -+ nd->path = file->f_path; -+ path_get(&file->f_path); -+ -+ fput_light(file, fput_needed); -+ } -+ return 0; -+ -+fput_fail: -+ fput_light(file, fput_needed); -+out_fail: -+ return retval; -+} -+ -+/* Returns 0 and nd will be valid on success; Retuns error, otherwise. */ -+static int do_path_lookup(int dfd, const char *name, -+ unsigned int flags, struct nameidata *nd) -+{ -+ int retval = path_init(dfd, name, flags, nd); -+ if (!retval) -+ retval = path_walk(name, nd); -+ if (unlikely(!retval && !audit_dummy_context() && nd->path.dentry && -+ nd->path.dentry->d_inode)) -+ audit_inode(name, nd->path.dentry); -+ if (nd->root.mnt) { -+ path_put(&nd->root); -+ nd->root.mnt = NULL; -+ } -+ return retval; -+} -+ -+int path_lookup(const char *name, unsigned int flags, -+ struct nameidata *nd) -+{ -+ return do_path_lookup(AT_FDCWD, name, flags, nd); -+} -+ -+int kern_path(const char *name, unsigned int flags, struct path *path) -+{ -+ struct nameidata nd; -+ int res = do_path_lookup(AT_FDCWD, name, flags, &nd); -+ if (!res) -+ *path = nd.path; -+ return res; -+} -+ -+/** -+ * vfs_path_lookup - lookup a file path relative to a dentry-vfsmount pair -+ * @dentry: pointer to dentry of the base directory -+ * @mnt: pointer to vfs mount of the base directory -+ * @name: pointer to file name -+ * @flags: lookup flags -+ * @nd: pointer to nameidata -+ */ -+int vfs_path_lookup(struct dentry *dentry, struct vfsmount *mnt, -+ const char *name, unsigned int flags, -+ struct nameidata *nd) -+{ -+ int retval; -+ -+ /* same as do_path_lookup */ -+ nd->last_type = LAST_ROOT; -+ nd->flags = flags; -+ nd->depth = 0; -+ -+ nd->path.dentry = dentry; -+ nd->path.mnt = mnt; -+ path_get(&nd->path); -+ nd->root = nd->path; -+ path_get(&nd->root); -+ -+ retval = path_walk(name, nd); -+ if (unlikely(!retval && !audit_dummy_context() && nd->path.dentry && -+ nd->path.dentry->d_inode)) -+ audit_inode(name, nd->path.dentry); -+ -+ path_put(&nd->root); -+ nd->root.mnt = NULL; -+ -+ return retval; -+} -+ -+static struct dentry *__lookup_hash(struct qstr *name, -+ struct dentry *base, struct nameidata *nd) -+{ -+ struct dentry *dentry; -+ struct inode *inode; -+ int err; -+ -+ inode = base->d_inode; -+ -+ /* -+ * See if the low-level filesystem might want -+ * to use its own hash.. -+ */ -+ if (base->d_op && base->d_op->d_hash) { -+ err = base->d_op->d_hash(base, name); -+ dentry = ERR_PTR(err); -+ if (err < 0) -+ goto out; -+ } -+ -+ /* -+ * Don't bother with __d_lookup: callers are for creat as -+ * well as unlink, so a lot of the time it would cost -+ * a double lookup. -+ */ -+ dentry = d_lookup(base, name); -+ -+ if (dentry && dentry->d_op && dentry->d_op->d_revalidate) -+ dentry = do_revalidate(dentry, nd); -+ -+ if (!dentry) -+ dentry = d_alloc_and_lookup(base, name, nd); -+out: -+ return dentry; -+} -+ -+/* -+ * Restricted form of lookup. Doesn't follow links, single-component only, -+ * needs parent already locked. Doesn't follow mounts. -+ * SMP-safe. -+ */ -+static struct dentry *lookup_hash(struct nameidata *nd) -+{ -+ int err; -+ -+ err = exec_permission(nd->path.dentry->d_inode); -+ if (err) -+ return ERR_PTR(err); -+ return __lookup_hash(&nd->last, nd->path.dentry, nd); -+} -+EXPORT_SYMBOL(lookup_hash); -+ -+static int __lookup_one_len(const char *name, struct qstr *this, -+ struct dentry *base, int len) -+{ -+ unsigned long hash; -+ unsigned int c; -+ -+ this->name = name; -+ this->len = len; -+ if (!len) -+ return -EACCES; -+ -+ hash = init_name_hash(); -+ while (len--) { -+ c = *(const unsigned char *)name++; -+ if (c == '/' || c == '\0') -+ return -EACCES; -+ hash = partial_name_hash(c, hash); -+ } -+ this->hash = end_name_hash(hash); -+ return 0; -+} -+EXPORT_SYMBOL(__lookup_one_len); -+ -+/** -+ * lookup_one_len - filesystem helper to lookup single pathname component -+ * @name: pathname component to lookup -+ * @base: base directory to lookup from -+ * @len: maximum length @len should be interpreted to -+ * -+ * Note that this routine is purely a helper for filesystem usage and should -+ * not be called by generic code. Also note that by using this function the -+ * nameidata argument is passed to the filesystem methods and a filesystem -+ * using this helper needs to be prepared for that. -+ */ -+struct dentry *lookup_one_len(const char *name, struct dentry *base, int len) -+{ -+ int err; -+ struct qstr this; -+ -+ WARN_ON_ONCE(!mutex_is_locked(&base->d_inode->i_mutex)); -+ -+ err = __lookup_one_len(name, &this, base, len); -+ if (err) -+ return ERR_PTR(err); -+ -+ err = exec_permission(base->d_inode); -+ if (err) -+ return ERR_PTR(err); -+ return __lookup_hash(&this, base, NULL); -+} -+ -+int user_path_at(int dfd, const char __user *name, unsigned flags, -+ struct path *path) -+{ -+ struct nameidata nd; -+ char *tmp = getname(name); -+ int err = PTR_ERR(tmp); -+ if (!IS_ERR(tmp)) { -+ -+ BUG_ON(flags & LOOKUP_PARENT); -+ -+ err = do_path_lookup(dfd, tmp, flags, &nd); -+ putname(tmp); -+ if (!err) -+ *path = nd.path; -+ } -+ return err; -+} -+ -+static int user_path_parent(int dfd, const char __user *path, -+ struct nameidata *nd, char **name) -+{ -+ char *s = getname(path); -+ int error; -+ -+ if (IS_ERR(s)) -+ return PTR_ERR(s); -+ -+ error = do_path_lookup(dfd, s, LOOKUP_PARENT, nd); -+ if (error) -+ putname(s); -+ else -+ *name = s; -+ -+ return error; -+} -+ -+/* -+ * It's inline, so penalty for filesystems that don't use sticky bit is -+ * minimal. -+ */ -+static inline int check_sticky(struct inode *dir, struct inode *inode) -+{ -+ uid_t fsuid = current_fsuid(); -+ -+ if (!(dir->i_mode & S_ISVTX)) -+ return 0; -+ if (inode->i_uid == fsuid) -+ return 0; -+ if (dir->i_uid == fsuid) -+ return 0; -+ return !capable(CAP_FOWNER); -+} -+ -+/* -+ * Check whether we can remove a link victim from directory dir, check -+ * whether the type of victim is right. -+ * 1. We can't do it if dir is read-only (done in permission()) -+ * 2. We should have write and exec permissions on dir -+ * 3. We can't remove anything from append-only dir -+ * 4. We can't do anything with immutable dir (done in permission()) -+ * 5. If the sticky bit on dir is set we should either -+ * a. be owner of dir, or -+ * b. be owner of victim, or -+ * c. have CAP_FOWNER capability -+ * 6. If the victim is append-only or immutable we can't do antyhing with -+ * links pointing to it. -+ * 7. If we were asked to remove a directory and victim isn't one - ENOTDIR. -+ * 8. If we were asked to remove a non-directory and victim isn't one - EISDIR. -+ * 9. We can't remove a root or mountpoint. -+ * 10. We don't allow removal of NFS sillyrenamed files; it's handled by -+ * nfs_async_unlink(). -+ */ -+static int may_delete(struct inode *dir,struct dentry *victim,int isdir) -+{ -+ int error; -+ -+ if (!victim->d_inode) -+ return -ENOENT; -+ -+ BUG_ON(victim->d_parent->d_inode != dir); -+ audit_inode_child(victim, dir); -+ -+ error = inode_permission(dir, MAY_WRITE | MAY_EXEC); -+ if (error) -+ return error; -+ if (IS_APPEND(dir)) -+ return -EPERM; -+ if (check_sticky(dir, victim->d_inode)||IS_APPEND(victim->d_inode)|| -+ IS_IMMUTABLE(victim->d_inode) || IS_SWAPFILE(victim->d_inode)) -+ return -EPERM; -+ if (isdir) { -+ if (!S_ISDIR(victim->d_inode->i_mode)) -+ return -ENOTDIR; -+ if (IS_ROOT(victim)) -+ return -EBUSY; -+ } else if (S_ISDIR(victim->d_inode->i_mode)) -+ return -EISDIR; -+ if (IS_DEADDIR(dir)) -+ return -ENOENT; -+ if (victim->d_flags & DCACHE_NFSFS_RENAMED) -+ return -EBUSY; -+ return 0; -+} -+ -+/* Check whether we can create an object with dentry child in directory -+ * dir. -+ * 1. We can't do it if child already exists (open has special treatment for -+ * this case, but since we are inlined it's OK) -+ * 2. We can't do it if dir is read-only (done in permission()) -+ * 3. We should have write and exec permissions on dir -+ * 4. We can't do it if dir is immutable (done in permission()) -+ */ -+static inline int may_create(struct inode *dir, struct dentry *child) -+{ -+ if (child->d_inode) -+ return -EEXIST; -+ if (IS_DEADDIR(dir)) -+ return -ENOENT; -+ return inode_permission(dir, MAY_WRITE | MAY_EXEC); -+} -+ -+/* -+ * p1 and p2 should be directories on the same fs. -+ */ -+struct dentry *lock_rename(struct dentry *p1, struct dentry *p2) -+{ -+ struct dentry *p; -+ -+ if (p1 == p2) { -+ mutex_lock_nested(&p1->d_inode->i_mutex, I_MUTEX_PARENT); -+ return NULL; -+ } -+ -+ mutex_lock(&p1->d_inode->i_sb->s_vfs_rename_mutex); -+ -+ p = d_ancestor(p2, p1); -+ if (p) { -+ mutex_lock_nested(&p2->d_inode->i_mutex, I_MUTEX_PARENT); -+ mutex_lock_nested(&p1->d_inode->i_mutex, I_MUTEX_CHILD); -+ return p; -+ } -+ -+ p = d_ancestor(p1, p2); -+ if (p) { -+ mutex_lock_nested(&p1->d_inode->i_mutex, I_MUTEX_PARENT); -+ mutex_lock_nested(&p2->d_inode->i_mutex, I_MUTEX_CHILD); -+ return p; -+ } -+ -+ mutex_lock_nested(&p1->d_inode->i_mutex, I_MUTEX_PARENT); -+ mutex_lock_nested(&p2->d_inode->i_mutex, I_MUTEX_CHILD); -+ return NULL; -+} -+ -+void unlock_rename(struct dentry *p1, struct dentry *p2) -+{ -+ mutex_unlock(&p1->d_inode->i_mutex); -+ if (p1 != p2) { -+ mutex_unlock(&p2->d_inode->i_mutex); -+ mutex_unlock(&p1->d_inode->i_sb->s_vfs_rename_mutex); -+ } -+} -+ -+int vfs_create(struct inode *dir, struct dentry *dentry, int mode, -+ struct nameidata *nd) -+{ -+ int error = may_create(dir, dentry); -+ -+ if (error) -+ return error; -+ -+ if (!dir->i_op->create) -+ return -EACCES; /* shouldn't it be ENOSYS? */ -+ mode &= S_IALLUGO; -+ mode |= S_IFREG; -+ error = security_inode_create(dir, dentry, mode); -+ if (error) -+ return error; -+ error = dir->i_op->create(dir, dentry, mode, nd); -+ if (!error) -+ fsnotify_create(dir, dentry); -+ return error; -+} -+ -+int may_open(struct path *path, int acc_mode, int flag) -+{ -+ struct dentry *dentry = path->dentry; -+ struct inode *inode = dentry->d_inode; -+ int error; -+ -+ if (!inode) -+ return -ENOENT; -+ -+ switch (inode->i_mode & S_IFMT) { -+ case S_IFLNK: -+ return -ELOOP; -+ case S_IFDIR: -+ if (acc_mode & MAY_WRITE) -+ return -EISDIR; -+ break; -+ case S_IFBLK: -+ case S_IFCHR: -+ if (path->mnt->mnt_flags & MNT_NODEV) -+ return -EACCES; -+ /*FALLTHRU*/ -+ case S_IFIFO: -+ case S_IFSOCK: -+ flag &= ~O_TRUNC; -+ break; -+ } -+ -+ error = inode_permission(inode, acc_mode); -+ if (error) -+ return error; -+ -+ /* -+ * An append-only file must be opened in append mode for writing. -+ */ -+ if (IS_APPEND(inode)) { -+ if ((flag & O_ACCMODE) != O_RDONLY && !(flag & O_APPEND)) -+ return -EPERM; -+ if (flag & O_TRUNC) -+ return -EPERM; -+ } -+ -+ /* O_NOATIME can only be set by the owner or superuser */ -+ if (flag & O_NOATIME && !is_owner_or_cap(inode)) -+ return -EPERM; -+ -+ /* -+ * Ensure there are no outstanding leases on the file. -+ */ -+ return break_lease(inode, flag); -+} -+ -+static int handle_truncate(struct path *path) -+{ -+ struct inode *inode = path->dentry->d_inode; -+ int error = get_write_access(inode); -+ if (error) -+ return error; -+ /* -+ * Refuse to truncate files with mandatory locks held on them. -+ */ -+ error = locks_verify_locked(inode); -+ if (!error) -+ error = security_path_truncate(path); -+ if (!error) { -+ error = do_truncate(path->dentry, 0, -+ ATTR_MTIME|ATTR_CTIME|ATTR_OPEN, -+ NULL); -+ } -+ put_write_access(inode); -+ return error; -+} -+ -+/* -+ * Be careful about ever adding any more callers of this -+ * function. Its flags must be in the namei format, not -+ * what get passed to sys_open(). -+ */ -+static int __open_namei_create(struct nameidata *nd, struct path *path, -+ int open_flag, int mode) -+{ -+ int error; -+ struct dentry *dir = nd->path.dentry; -+ -+ if (!IS_POSIXACL(dir->d_inode)) -+ mode &= ~current_umask(); -+ error = security_path_mknod(&nd->path, path->dentry, mode, 0); -+ if (error) -+ goto out_unlock; -+ error = vfs_create(dir->d_inode, path->dentry, mode, nd); -+out_unlock: -+ mutex_unlock(&dir->d_inode->i_mutex); -+ dput(nd->path.dentry); -+ nd->path.dentry = path->dentry; -+ if (error) -+ return error; -+ /* Don't check for write permission, don't truncate */ -+ return may_open(&nd->path, 0, open_flag & ~O_TRUNC); -+} -+ -+/* -+ * Note that while the flag value (low two bits) for sys_open means: -+ * 00 - read-only -+ * 01 - write-only -+ * 10 - read-write -+ * 11 - special -+ * it is changed into -+ * 00 - no permissions needed -+ * 01 - read-permission -+ * 10 - write-permission -+ * 11 - read-write -+ * for the internal routines (ie open_namei()/follow_link() etc) -+ * This is more logical, and also allows the 00 "no perm needed" -+ * to be used for symlinks (where the permissions are checked -+ * later). -+ * -+*/ -+static inline int open_to_namei_flags(int flag) -+{ -+ if ((flag+1) & O_ACCMODE) -+ flag++; -+ return flag; -+} -+ -+static int open_will_truncate(int flag, struct inode *inode) -+{ -+ /* -+ * We'll never write to the fs underlying -+ * a device file. -+ */ -+ if (special_file(inode->i_mode)) -+ return 0; -+ return (flag & O_TRUNC); -+} -+ -+static struct file *finish_open(struct nameidata *nd, -+ int open_flag, int acc_mode) -+{ -+ struct file *filp; -+ int will_truncate; -+ int error; -+ -+ will_truncate = open_will_truncate(open_flag, nd->path.dentry->d_inode); -+ if (will_truncate) { -+ error = mnt_want_write(nd->path.mnt); -+ if (error) -+ goto exit; -+ } -+ error = may_open(&nd->path, acc_mode, open_flag); -+ if (error) { -+ if (will_truncate) -+ mnt_drop_write(nd->path.mnt); -+ goto exit; -+ } -+ filp = nameidata_to_filp(nd); -+ if (!IS_ERR(filp)) { -+ error = ima_file_check(filp, acc_mode); -+ if (error) { -+ fput(filp); -+ filp = ERR_PTR(error); -+ } -+ } -+ if (!IS_ERR(filp)) { -+ if (will_truncate) { -+ error = handle_truncate(&nd->path); -+ if (error) { -+ fput(filp); -+ filp = ERR_PTR(error); -+ } -+ } -+ } -+ /* -+ * It is now safe to drop the mnt write -+ * because the filp has had a write taken -+ * on its behalf. -+ */ -+ if (will_truncate) -+ mnt_drop_write(nd->path.mnt); -+ return filp; -+ -+exit: -+ if (!IS_ERR(nd->intent.open.file)) -+ release_open_intent(nd); -+ path_put(&nd->path); -+ return ERR_PTR(error); -+} -+ -+static struct file *do_last(struct nameidata *nd, struct path *path, -+ int open_flag, int acc_mode, -+ int mode, const char *pathname) -+{ -+ struct dentry *dir = nd->path.dentry; -+ struct file *filp; -+ int error = -EISDIR; -+ -+ switch (nd->last_type) { -+ case LAST_DOTDOT: -+ follow_dotdot(nd); -+ dir = nd->path.dentry; -+ case LAST_DOT: -+ if (nd->path.mnt->mnt_sb->s_type->fs_flags & FS_REVAL_DOT) { -+ if (!dir->d_op->d_revalidate(dir, nd)) { -+ error = -ESTALE; -+ goto exit; -+ } -+ } -+ /* fallthrough */ -+ case LAST_ROOT: -+ if (open_flag & O_CREAT) -+ goto exit; -+ /* fallthrough */ -+ case LAST_BIND: -+ audit_inode(pathname, dir); -+ goto ok; -+ } -+ -+ /* trailing slashes? */ -+ if (nd->last.name[nd->last.len]) { -+ if (open_flag & O_CREAT) -+ goto exit; -+ nd->flags |= LOOKUP_DIRECTORY | LOOKUP_FOLLOW; -+ } -+ -+ /* just plain open? */ -+ if (!(open_flag & O_CREAT)) { -+ error = do_lookup(nd, &nd->last, path); -+ if (error) -+ goto exit; -+ error = -ENOENT; -+ if (!path->dentry->d_inode) -+ goto exit_dput; -+ if (path->dentry->d_inode->i_op->follow_link) -+ return NULL; -+ error = -ENOTDIR; -+ if (nd->flags & LOOKUP_DIRECTORY) { -+ if (!path->dentry->d_inode->i_op->lookup) -+ goto exit_dput; -+ } -+ path_to_nameidata(path, nd); -+ audit_inode(pathname, nd->path.dentry); -+ goto ok; -+ } -+ -+ /* OK, it's O_CREAT */ -+ mutex_lock(&dir->d_inode->i_mutex); -+ -+ path->dentry = lookup_hash(nd); -+ path->mnt = nd->path.mnt; -+ -+ error = PTR_ERR(path->dentry); -+ if (IS_ERR(path->dentry)) { -+ mutex_unlock(&dir->d_inode->i_mutex); -+ goto exit; -+ } -+ -+ if (IS_ERR(nd->intent.open.file)) { -+ error = PTR_ERR(nd->intent.open.file); -+ goto exit_mutex_unlock; -+ } -+ -+ /* Negative dentry, just create the file */ -+ if (!path->dentry->d_inode) { -+ /* -+ * This write is needed to ensure that a -+ * ro->rw transition does not occur between -+ * the time when the file is created and when -+ * a permanent write count is taken through -+ * the 'struct file' in nameidata_to_filp(). -+ */ -+ error = mnt_want_write(nd->path.mnt); -+ if (error) -+ goto exit_mutex_unlock; -+ error = __open_namei_create(nd, path, open_flag, mode); -+ if (error) { -+ mnt_drop_write(nd->path.mnt); -+ goto exit; -+ } -+ filp = nameidata_to_filp(nd); -+ mnt_drop_write(nd->path.mnt); -+ if (!IS_ERR(filp)) { -+ error = ima_file_check(filp, acc_mode); -+ if (error) { -+ fput(filp); -+ filp = ERR_PTR(error); -+ } -+ } -+ return filp; -+ } -+ -+ /* -+ * It already exists. -+ */ -+ mutex_unlock(&dir->d_inode->i_mutex); -+ audit_inode(pathname, path->dentry); -+ -+ error = -EEXIST; -+ if (open_flag & O_EXCL) -+ goto exit_dput; -+ -+ if (__follow_mount(path)) { -+ error = -ELOOP; -+ if (open_flag & O_NOFOLLOW) -+ goto exit_dput; -+ } -+ -+ error = -ENOENT; -+ if (!path->dentry->d_inode) -+ goto exit_dput; -+ -+ if (path->dentry->d_inode->i_op->follow_link) -+ return NULL; -+ -+ path_to_nameidata(path, nd); -+ error = -EISDIR; -+ if (S_ISDIR(path->dentry->d_inode->i_mode)) -+ goto exit; -+ok: -+ filp = finish_open(nd, open_flag, acc_mode); -+ return filp; -+ -+exit_mutex_unlock: -+ mutex_unlock(&dir->d_inode->i_mutex); -+exit_dput: -+ path_put_conditional(path, nd); -+exit: -+ if (!IS_ERR(nd->intent.open.file)) -+ release_open_intent(nd); -+ path_put(&nd->path); -+ return ERR_PTR(error); -+} -+ -+/* -+ * Note that the low bits of the passed in "open_flag" -+ * are not the same as in the local variable "flag". See -+ * open_to_namei_flags() for more details. -+ */ -+struct file *do_filp_open(int dfd, const char *pathname, -+ int open_flag, int mode, int acc_mode) -+{ -+ struct file *filp; -+ struct nameidata nd; -+ int error; -+ struct path path; -+ int count = 0; -+ int flag = open_to_namei_flags(open_flag); -+ int force_reval = 0; -+ -+ if (!(open_flag & O_CREAT)) -+ mode = 0; -+ -+ /* -+ * O_SYNC is implemented as __O_SYNC|O_DSYNC. As many places only -+ * check for O_DSYNC if the need any syncing at all we enforce it's -+ * always set instead of having to deal with possibly weird behaviour -+ * for malicious applications setting only __O_SYNC. -+ */ -+ if (open_flag & __O_SYNC) -+ open_flag |= O_DSYNC; -+ -+ if (!acc_mode) -+ acc_mode = MAY_OPEN | ACC_MODE(open_flag); -+ -+ /* O_TRUNC implies we need access checks for write permissions */ -+ if (open_flag & O_TRUNC) -+ acc_mode |= MAY_WRITE; -+ -+ /* Allow the LSM permission hook to distinguish append -+ access from general write access. */ -+ if (open_flag & O_APPEND) -+ acc_mode |= MAY_APPEND; -+ -+ /* find the parent */ -+reval: -+ error = path_init(dfd, pathname, LOOKUP_PARENT, &nd); -+ if (error) -+ return ERR_PTR(error); -+ if (force_reval) -+ nd.flags |= LOOKUP_REVAL; -+ -+ current->total_link_count = 0; -+ error = link_path_walk(pathname, &nd); -+ if (error) { -+ filp = ERR_PTR(error); -+ goto out; -+ } -+ if (unlikely(!audit_dummy_context()) && (open_flag & O_CREAT)) -+ audit_inode(pathname, nd.path.dentry); -+ -+ /* -+ * We have the parent and last component. -+ */ -+ -+ error = -ENFILE; -+ filp = get_empty_filp(); -+ if (filp == NULL) -+ goto exit_parent; -+ nd.intent.open.file = filp; -+ filp->f_flags = open_flag; -+ nd.intent.open.flags = flag; -+ nd.intent.open.create_mode = mode; -+ nd.flags &= ~LOOKUP_PARENT; -+ nd.flags |= LOOKUP_OPEN; -+ if (open_flag & O_CREAT) { -+ nd.flags |= LOOKUP_CREATE; -+ if (open_flag & O_EXCL) -+ nd.flags |= LOOKUP_EXCL; -+ } -+ if (open_flag & O_DIRECTORY) -+ nd.flags |= LOOKUP_DIRECTORY; -+ if (!(open_flag & O_NOFOLLOW)) -+ nd.flags |= LOOKUP_FOLLOW; -+ filp = do_last(&nd, &path, open_flag, acc_mode, mode, pathname); -+ while (unlikely(!filp)) { /* trailing symlink */ -+ struct path holder; -+ struct inode *inode = path.dentry->d_inode; -+ void *cookie; -+ error = -ELOOP; -+ /* S_ISDIR part is a temporary automount kludge */ -+ if (!(nd.flags & LOOKUP_FOLLOW) && !S_ISDIR(inode->i_mode)) -+ goto exit_dput; -+ if (count++ == 32) -+ goto exit_dput; -+ /* -+ * This is subtle. Instead of calling do_follow_link() we do -+ * the thing by hands. The reason is that this way we have zero -+ * link_count and path_walk() (called from ->follow_link) -+ * honoring LOOKUP_PARENT. After that we have the parent and -+ * last component, i.e. we are in the same situation as after -+ * the first path_walk(). Well, almost - if the last component -+ * is normal we get its copy stored in nd->last.name and we will -+ * have to putname() it when we are done. Procfs-like symlinks -+ * just set LAST_BIND. -+ */ -+ nd.flags |= LOOKUP_PARENT; -+ error = security_inode_follow_link(path.dentry, &nd); -+ if (error) -+ goto exit_dput; -+ error = __do_follow_link(&path, &nd, &cookie); -+ if (unlikely(error)) { -+ /* nd.path had been dropped */ -+ if (!IS_ERR(cookie) && inode->i_op->put_link) -+ inode->i_op->put_link(path.dentry, &nd, cookie); -+ path_put(&path); -+ release_open_intent(&nd); -+ filp = ERR_PTR(error); -+ goto out; -+ } -+ holder = path; -+ nd.flags &= ~LOOKUP_PARENT; -+ filp = do_last(&nd, &path, open_flag, acc_mode, mode, pathname); -+ if (inode->i_op->put_link) -+ inode->i_op->put_link(holder.dentry, &nd, cookie); -+ path_put(&holder); -+ } -+out: -+ if (nd.root.mnt) -+ path_put(&nd.root); -+ if (filp == ERR_PTR(-ESTALE) && !force_reval) { -+ force_reval = 1; -+ goto reval; -+ } -+ return filp; -+ -+exit_dput: -+ path_put_conditional(&path, &nd); -+ if (!IS_ERR(nd.intent.open.file)) -+ release_open_intent(&nd); -+exit_parent: -+ path_put(&nd.path); -+ filp = ERR_PTR(error); -+ goto out; -+} -+ -+/** -+ * filp_open - open file and return file pointer -+ * -+ * @filename: path to open -+ * @flags: open flags as per the open(2) second argument -+ * @mode: mode for the new file if O_CREAT is set, else ignored -+ * -+ * This is the helper to open a file from kernelspace if you really -+ * have to. But in generally you should not do this, so please move -+ * along, nothing to see here.. -+ */ -+struct file *filp_open(const char *filename, int flags, int mode) -+{ -+ return do_filp_open(AT_FDCWD, filename, flags, mode, 0); -+} -+EXPORT_SYMBOL(filp_open); -+ -+/** -+ * lookup_create - lookup a dentry, creating it if it doesn't exist -+ * @nd: nameidata info -+ * @is_dir: directory flag -+ * -+ * Simple function to lookup and return a dentry and create it -+ * if it doesn't exist. Is SMP-safe. -+ * -+ * Returns with nd->path.dentry->d_inode->i_mutex locked. -+ */ -+struct dentry *lookup_create(struct nameidata *nd, int is_dir) -+{ -+ struct dentry *dentry = ERR_PTR(-EEXIST); -+ -+ mutex_lock_nested(&nd->path.dentry->d_inode->i_mutex, I_MUTEX_PARENT); -+ /* -+ * Yucky last component or no last component at all? -+ * (foo/., foo/.., /////) -+ */ -+ if (nd->last_type != LAST_NORM) -+ goto fail; -+ nd->flags &= ~LOOKUP_PARENT; -+ nd->flags |= LOOKUP_CREATE | LOOKUP_EXCL; -+ nd->intent.open.flags = O_EXCL; -+ -+ /* -+ * Do the final lookup. -+ */ -+ dentry = lookup_hash(nd); -+ if (IS_ERR(dentry)) -+ goto fail; -+ -+ if (dentry->d_inode) -+ goto eexist; -+ /* -+ * Special case - lookup gave negative, but... we had foo/bar/ -+ * From the vfs_mknod() POV we just have a negative dentry - -+ * all is fine. Let's be bastards - you had / on the end, you've -+ * been asking for (non-existent) directory. -ENOENT for you. -+ */ -+ if (unlikely(!is_dir && nd->last.name[nd->last.len])) { -+ dput(dentry); -+ dentry = ERR_PTR(-ENOENT); -+ } -+ return dentry; -+eexist: -+ dput(dentry); -+ dentry = ERR_PTR(-EEXIST); -+fail: -+ return dentry; -+} -+EXPORT_SYMBOL_GPL(lookup_create); -+ -+int vfs_mknod(struct inode *dir, struct dentry *dentry, int mode, dev_t dev) -+{ -+ int error = may_create(dir, dentry); -+ -+ if (error) -+ return error; -+ -+ if ((S_ISCHR(mode) || S_ISBLK(mode)) && !capable(CAP_MKNOD)) -+ return -EPERM; -+ -+ if (!dir->i_op->mknod) -+ return -EPERM; -+ -+ error = devcgroup_inode_mknod(mode, dev); -+ if (error) -+ return error; -+ -+ error = security_inode_mknod(dir, dentry, mode, dev); -+ if (error) -+ return error; -+ -+ error = dir->i_op->mknod(dir, dentry, mode, dev); -+ if (!error) -+ fsnotify_create(dir, dentry); -+ return error; -+} -+ -+static int may_mknod(mode_t mode) -+{ -+ switch (mode & S_IFMT) { -+ case S_IFREG: -+ case S_IFCHR: -+ case S_IFBLK: -+ case S_IFIFO: -+ case S_IFSOCK: -+ case 0: /* zero mode translates to S_IFREG */ -+ return 0; -+ case S_IFDIR: -+ return -EPERM; -+ default: -+ return -EINVAL; -+ } -+} -+ -+SYSCALL_DEFINE4(mknodat, int, dfd, const char __user *, filename, int, mode, -+ unsigned, dev) -+{ -+ int error; -+ char *tmp; -+ struct dentry *dentry; -+ struct nameidata nd; -+ -+ if (S_ISDIR(mode)) -+ return -EPERM; -+ -+ error = user_path_parent(dfd, filename, &nd, &tmp); -+ if (error) -+ return error; -+ -+ dentry = lookup_create(&nd, 0); -+ if (IS_ERR(dentry)) { -+ error = PTR_ERR(dentry); -+ goto out_unlock; -+ } -+ if (!IS_POSIXACL(nd.path.dentry->d_inode)) -+ mode &= ~current_umask(); -+ error = may_mknod(mode); -+ if (error) -+ goto out_dput; -+ error = mnt_want_write(nd.path.mnt); -+ if (error) -+ goto out_dput; -+ error = security_path_mknod(&nd.path, dentry, mode, dev); -+ if (error) -+ goto out_drop_write; -+ switch (mode & S_IFMT) { -+ case 0: case S_IFREG: -+ error = vfs_create(nd.path.dentry->d_inode,dentry,mode,&nd); -+ break; -+ case S_IFCHR: case S_IFBLK: -+ error = vfs_mknod(nd.path.dentry->d_inode,dentry,mode, -+ new_decode_dev(dev)); -+ break; -+ case S_IFIFO: case S_IFSOCK: -+ error = vfs_mknod(nd.path.dentry->d_inode,dentry,mode,0); -+ break; -+ } -+out_drop_write: -+ mnt_drop_write(nd.path.mnt); -+out_dput: -+ dput(dentry); -+out_unlock: -+ mutex_unlock(&nd.path.dentry->d_inode->i_mutex); -+ path_put(&nd.path); -+ putname(tmp); -+ -+ return error; -+} -+ -+SYSCALL_DEFINE3(mknod, const char __user *, filename, int, mode, unsigned, dev) -+{ -+ return sys_mknodat(AT_FDCWD, filename, mode, dev); -+} -+ -+int vfs_mkdir(struct inode *dir, struct dentry *dentry, int mode) -+{ -+ int error = may_create(dir, dentry); -+ -+ if (error) -+ return error; -+ -+ if (!dir->i_op->mkdir) -+ return -EPERM; -+ -+ mode &= (S_IRWXUGO|S_ISVTX); -+ error = security_inode_mkdir(dir, dentry, mode); -+ if (error) -+ return error; -+ -+ error = dir->i_op->mkdir(dir, dentry, mode); -+ if (!error) -+ fsnotify_mkdir(dir, dentry); -+ return error; -+} -+ -+SYSCALL_DEFINE3(mkdirat, int, dfd, const char __user *, pathname, int, mode) -+{ -+ int error = 0; -+ char * tmp; -+ struct dentry *dentry; -+ struct nameidata nd; -+ -+ error = user_path_parent(dfd, pathname, &nd, &tmp); -+ if (error) -+ goto out_err; -+ -+ dentry = lookup_create(&nd, 1); -+ error = PTR_ERR(dentry); -+ if (IS_ERR(dentry)) -+ goto out_unlock; -+ -+ if (!IS_POSIXACL(nd.path.dentry->d_inode)) -+ mode &= ~current_umask(); -+ error = mnt_want_write(nd.path.mnt); -+ if (error) -+ goto out_dput; -+ error = security_path_mkdir(&nd.path, dentry, mode); -+ if (error) -+ goto out_drop_write; -+ error = vfs_mkdir(nd.path.dentry->d_inode, dentry, mode); -+out_drop_write: -+ mnt_drop_write(nd.path.mnt); -+out_dput: -+ dput(dentry); -+out_unlock: -+ mutex_unlock(&nd.path.dentry->d_inode->i_mutex); -+ path_put(&nd.path); -+ putname(tmp); -+out_err: -+ return error; -+} -+ -+SYSCALL_DEFINE2(mkdir, const char __user *, pathname, int, mode) -+{ -+ return sys_mkdirat(AT_FDCWD, pathname, mode); -+} -+ -+/* -+ * We try to drop the dentry early: we should have -+ * a usage count of 2 if we're the only user of this -+ * dentry, and if that is true (possibly after pruning -+ * the dcache), then we drop the dentry now. -+ * -+ * A low-level filesystem can, if it choses, legally -+ * do a -+ * -+ * if (!d_unhashed(dentry)) -+ * return -EBUSY; -+ * -+ * if it cannot handle the case of removing a directory -+ * that is still in use by something else.. -+ */ -+void dentry_unhash(struct dentry *dentry) -+{ -+ dget(dentry); -+ shrink_dcache_parent(dentry); -+ spin_lock(&dcache_lock); -+ spin_lock(&dentry->d_lock); -+ if (atomic_read(&dentry->d_count) == 2) -+ __d_drop(dentry); -+ spin_unlock(&dentry->d_lock); -+ spin_unlock(&dcache_lock); -+} -+ -+int vfs_rmdir(struct inode *dir, struct dentry *dentry) -+{ -+ int error = may_delete(dir, dentry, 1); -+ -+ if (error) -+ return error; -+ -+ if (!dir->i_op->rmdir) -+ return -EPERM; -+ -+ mutex_lock(&dentry->d_inode->i_mutex); -+ dentry_unhash(dentry); -+ if (d_mountpoint(dentry)) -+ error = -EBUSY; -+ else { -+ error = security_inode_rmdir(dir, dentry); -+ if (!error) { -+ error = dir->i_op->rmdir(dir, dentry); -+ if (!error) { -+ dentry->d_inode->i_flags |= S_DEAD; -+ dont_mount(dentry); -+ } -+ } -+ } -+ mutex_unlock(&dentry->d_inode->i_mutex); -+ if (!error) { -+ d_delete(dentry); -+ } -+ dput(dentry); -+ -+ return error; -+} -+ -+static long do_rmdir(int dfd, const char __user *pathname) -+{ -+ int error = 0; -+ char * name; -+ struct dentry *dentry; -+ struct nameidata nd; -+ -+ error = user_path_parent(dfd, pathname, &nd, &name); -+ if (error) -+ return error; -+ -+ switch(nd.last_type) { -+ case LAST_DOTDOT: -+ error = -ENOTEMPTY; -+ goto exit1; -+ case LAST_DOT: -+ error = -EINVAL; -+ goto exit1; -+ case LAST_ROOT: -+ error = -EBUSY; -+ goto exit1; -+ } -+ -+ nd.flags &= ~LOOKUP_PARENT; -+ -+ mutex_lock_nested(&nd.path.dentry->d_inode->i_mutex, I_MUTEX_PARENT); -+ dentry = lookup_hash(&nd); -+ error = PTR_ERR(dentry); -+ if (IS_ERR(dentry)) -+ goto exit2; -+ error = mnt_want_write(nd.path.mnt); -+ if (error) -+ goto exit3; -+ error = security_path_rmdir(&nd.path, dentry); -+ if (error) -+ goto exit4; -+ error = vfs_rmdir(nd.path.dentry->d_inode, dentry); -+exit4: -+ mnt_drop_write(nd.path.mnt); -+exit3: -+ dput(dentry); -+exit2: -+ mutex_unlock(&nd.path.dentry->d_inode->i_mutex); -+exit1: -+ path_put(&nd.path); -+ putname(name); -+ return error; -+} -+ -+SYSCALL_DEFINE1(rmdir, const char __user *, pathname) -+{ -+ return do_rmdir(AT_FDCWD, pathname); -+} -+ -+int vfs_unlink(struct inode *dir, struct dentry *dentry) -+{ -+ int error = may_delete(dir, dentry, 0); -+ -+ if (error) -+ return error; -+ -+ if (!dir->i_op->unlink) -+ return -EPERM; -+ -+ mutex_lock(&dentry->d_inode->i_mutex); -+ if (d_mountpoint(dentry)) -+ error = -EBUSY; -+ else { -+ error = security_inode_unlink(dir, dentry); -+ if (!error) { -+ error = dir->i_op->unlink(dir, dentry); -+ if (!error) -+ dont_mount(dentry); -+ } -+ } -+ mutex_unlock(&dentry->d_inode->i_mutex); -+ -+ /* We don't d_delete() NFS sillyrenamed files--they still exist. */ -+ if (!error && !(dentry->d_flags & DCACHE_NFSFS_RENAMED)) { -+ fsnotify_link_count(dentry->d_inode); -+ d_delete(dentry); -+ } -+ -+ return error; -+} -+ -+/* -+ * Make sure that the actual truncation of the file will occur outside its -+ * directory's i_mutex. Truncate can take a long time if there is a lot of -+ * writeout happening, and we don't want to prevent access to the directory -+ * while waiting on the I/O. -+ */ -+static long do_unlinkat(int dfd, const char __user *pathname) -+{ -+ int error; -+ char *name; -+ struct dentry *dentry; -+ struct nameidata nd; -+ struct inode *inode = NULL; -+ -+ error = user_path_parent(dfd, pathname, &nd, &name); -+ if (error) -+ return error; -+ -+ error = -EISDIR; -+ if (nd.last_type != LAST_NORM) -+ goto exit1; -+ -+ nd.flags &= ~LOOKUP_PARENT; -+ -+ mutex_lock_nested(&nd.path.dentry->d_inode->i_mutex, I_MUTEX_PARENT); -+ dentry = lookup_hash(&nd); -+ error = PTR_ERR(dentry); -+ if (!IS_ERR(dentry)) { -+ /* Why not before? Because we want correct error value */ -+ if (nd.last.name[nd.last.len]) -+ goto slashes; -+ inode = dentry->d_inode; -+ if (inode) -+ atomic_inc(&inode->i_count); -+ error = mnt_want_write(nd.path.mnt); -+ if (error) -+ goto exit2; -+ error = security_path_unlink(&nd.path, dentry); -+ if (error) -+ goto exit3; -+ error = vfs_unlink(nd.path.dentry->d_inode, dentry); -+exit3: -+ mnt_drop_write(nd.path.mnt); -+ exit2: -+ dput(dentry); -+ } -+ mutex_unlock(&nd.path.dentry->d_inode->i_mutex); -+ if (inode) -+ iput(inode); /* truncate the inode here */ -+exit1: -+ path_put(&nd.path); -+ putname(name); -+ return error; -+ -+slashes: -+ error = !dentry->d_inode ? -ENOENT : -+ S_ISDIR(dentry->d_inode->i_mode) ? -EISDIR : -ENOTDIR; -+ goto exit2; -+} -+ -+SYSCALL_DEFINE3(unlinkat, int, dfd, const char __user *, pathname, int, flag) -+{ -+ if ((flag & ~AT_REMOVEDIR) != 0) -+ return -EINVAL; -+ -+ if (flag & AT_REMOVEDIR) -+ return do_rmdir(dfd, pathname); -+ -+ return do_unlinkat(dfd, pathname); -+} -+ -+SYSCALL_DEFINE1(unlink, const char __user *, pathname) -+{ -+ return do_unlinkat(AT_FDCWD, pathname); -+} -+ -+int vfs_symlink(struct inode *dir, struct dentry *dentry, const char *oldname) -+{ -+ int error = may_create(dir, dentry); -+ -+ if (error) -+ return error; -+ -+ if (!dir->i_op->symlink) -+ return -EPERM; -+ -+ error = security_inode_symlink(dir, dentry, oldname); -+ if (error) -+ return error; -+ -+ error = dir->i_op->symlink(dir, dentry, oldname); -+ if (!error) -+ fsnotify_create(dir, dentry); -+ return error; -+} -+ -+SYSCALL_DEFINE3(symlinkat, const char __user *, oldname, -+ int, newdfd, const char __user *, newname) -+{ -+ int error; -+ char *from; -+ char *to; -+ struct dentry *dentry; -+ struct nameidata nd; -+ -+ from = getname(oldname); -+ if (IS_ERR(from)) -+ return PTR_ERR(from); -+ -+ error = user_path_parent(newdfd, newname, &nd, &to); -+ if (error) -+ goto out_putname; -+ -+ dentry = lookup_create(&nd, 0); -+ error = PTR_ERR(dentry); -+ if (IS_ERR(dentry)) -+ goto out_unlock; -+ -+ error = mnt_want_write(nd.path.mnt); -+ if (error) -+ goto out_dput; -+ error = security_path_symlink(&nd.path, dentry, from); -+ if (error) -+ goto out_drop_write; -+ error = vfs_symlink(nd.path.dentry->d_inode, dentry, from); -+out_drop_write: -+ mnt_drop_write(nd.path.mnt); -+out_dput: -+ dput(dentry); -+out_unlock: -+ mutex_unlock(&nd.path.dentry->d_inode->i_mutex); -+ path_put(&nd.path); -+ putname(to); -+out_putname: -+ putname(from); -+ return error; -+} -+ -+SYSCALL_DEFINE2(symlink, const char __user *, oldname, const char __user *, newname) -+{ -+ return sys_symlinkat(oldname, AT_FDCWD, newname); -+} -+ -+int vfs_link(struct dentry *old_dentry, struct inode *dir, struct dentry *new_dentry) -+{ -+ struct inode *inode = old_dentry->d_inode; -+ int error; -+ -+ if (!inode) -+ return -ENOENT; -+ -+ error = may_create(dir, new_dentry); -+ if (error) -+ return error; -+ -+ if (dir->i_sb != inode->i_sb) -+ return -EXDEV; -+ -+ /* -+ * A link to an append-only or immutable file cannot be created. -+ */ -+ if (IS_APPEND(inode) || IS_IMMUTABLE(inode)) -+ return -EPERM; -+ if (!dir->i_op->link) -+ return -EPERM; -+ if (S_ISDIR(inode->i_mode)) -+ return -EPERM; -+ -+ error = security_inode_link(old_dentry, dir, new_dentry); -+ if (error) -+ return error; -+ -+ mutex_lock(&inode->i_mutex); -+ error = dir->i_op->link(old_dentry, dir, new_dentry); -+ mutex_unlock(&inode->i_mutex); -+ if (!error) -+ fsnotify_link(dir, inode, new_dentry); -+ return error; -+} -+ -+/* -+ * Hardlinks are often used in delicate situations. We avoid -+ * security-related surprises by not following symlinks on the -+ * newname. --KAB -+ * -+ * We don't follow them on the oldname either to be compatible -+ * with linux 2.0, and to avoid hard-linking to directories -+ * and other special files. --ADM -+ */ -+SYSCALL_DEFINE5(linkat, int, olddfd, const char __user *, oldname, -+ int, newdfd, const char __user *, newname, int, flags) -+{ -+ struct dentry *new_dentry; -+ struct nameidata nd; -+ struct path old_path; -+ int error; -+ char *to; -+ -+ if ((flags & ~AT_SYMLINK_FOLLOW) != 0) -+ return -EINVAL; -+ -+ error = user_path_at(olddfd, oldname, -+ flags & AT_SYMLINK_FOLLOW ? LOOKUP_FOLLOW : 0, -+ &old_path); -+ if (error) -+ return error; -+ -+ error = user_path_parent(newdfd, newname, &nd, &to); -+ if (error) -+ goto out; -+ error = -EXDEV; -+ if (old_path.mnt != nd.path.mnt) -+ goto out_release; -+ new_dentry = lookup_create(&nd, 0); -+ error = PTR_ERR(new_dentry); -+ if (IS_ERR(new_dentry)) -+ goto out_unlock; -+ error = mnt_want_write(nd.path.mnt); -+ if (error) -+ goto out_dput; -+ error = security_path_link(old_path.dentry, &nd.path, new_dentry); -+ if (error) -+ goto out_drop_write; -+ error = vfs_link(old_path.dentry, nd.path.dentry->d_inode, new_dentry); -+out_drop_write: -+ mnt_drop_write(nd.path.mnt); -+out_dput: -+ dput(new_dentry); -+out_unlock: -+ mutex_unlock(&nd.path.dentry->d_inode->i_mutex); -+out_release: -+ path_put(&nd.path); -+ putname(to); -+out: -+ path_put(&old_path); -+ -+ return error; -+} -+ -+SYSCALL_DEFINE2(link, const char __user *, oldname, const char __user *, newname) -+{ -+ return sys_linkat(AT_FDCWD, oldname, AT_FDCWD, newname, 0); -+} -+ -+/* -+ * The worst of all namespace operations - renaming directory. "Perverted" -+ * doesn't even start to describe it. Somebody in UCB had a heck of a trip... -+ * Problems: -+ * a) we can get into loop creation. Check is done in is_subdir(). -+ * b) race potential - two innocent renames can create a loop together. -+ * That's where 4.4 screws up. Current fix: serialization on -+ * sb->s_vfs_rename_mutex. We might be more accurate, but that's another -+ * story. -+ * c) we have to lock _three_ objects - parents and victim (if it exists). -+ * And that - after we got ->i_mutex on parents (until then we don't know -+ * whether the target exists). Solution: try to be smart with locking -+ * order for inodes. We rely on the fact that tree topology may change -+ * only under ->s_vfs_rename_mutex _and_ that parent of the object we -+ * move will be locked. Thus we can rank directories by the tree -+ * (ancestors first) and rank all non-directories after them. -+ * That works since everybody except rename does "lock parent, lookup, -+ * lock child" and rename is under ->s_vfs_rename_mutex. -+ * HOWEVER, it relies on the assumption that any object with ->lookup() -+ * has no more than 1 dentry. If "hybrid" objects will ever appear, -+ * we'd better make sure that there's no link(2) for them. -+ * d) some filesystems don't support opened-but-unlinked directories, -+ * either because of layout or because they are not ready to deal with -+ * all cases correctly. The latter will be fixed (taking this sort of -+ * stuff into VFS), but the former is not going away. Solution: the same -+ * trick as in rmdir(). -+ * e) conversion from fhandle to dentry may come in the wrong moment - when -+ * we are removing the target. Solution: we will have to grab ->i_mutex -+ * in the fhandle_to_dentry code. [FIXME - current nfsfh.c relies on -+ * ->i_mutex on parents, which works but leads to some truly excessive -+ * locking]. -+ */ -+static int vfs_rename_dir(struct inode *old_dir, struct dentry *old_dentry, -+ struct inode *new_dir, struct dentry *new_dentry) -+{ -+ int error = 0; -+ struct inode *target; -+ -+ /* -+ * If we are going to change the parent - check write permissions, -+ * we'll need to flip '..'. -+ */ -+ if (new_dir != old_dir) { -+ error = inode_permission(old_dentry->d_inode, MAY_WRITE); -+ if (error) -+ return error; -+ } -+ -+ error = security_inode_rename(old_dir, old_dentry, new_dir, new_dentry); -+ if (error) -+ return error; -+ -+ target = new_dentry->d_inode; -+ if (target) -+ mutex_lock(&target->i_mutex); -+ if (d_mountpoint(old_dentry)||d_mountpoint(new_dentry)) -+ error = -EBUSY; -+ else { -+ if (target) -+ dentry_unhash(new_dentry); -+ error = old_dir->i_op->rename(old_dir, old_dentry, new_dir, new_dentry); -+ } -+ if (target) { -+ if (!error) { -+ target->i_flags |= S_DEAD; -+ dont_mount(new_dentry); -+ } -+ mutex_unlock(&target->i_mutex); -+ if (d_unhashed(new_dentry)) -+ d_rehash(new_dentry); -+ dput(new_dentry); -+ } -+ if (!error) -+ if (!(old_dir->i_sb->s_type->fs_flags & FS_RENAME_DOES_D_MOVE)) -+ d_move(old_dentry,new_dentry); -+ return error; -+} -+ -+static int vfs_rename_other(struct inode *old_dir, struct dentry *old_dentry, -+ struct inode *new_dir, struct dentry *new_dentry) -+{ -+ struct inode *target; -+ int error; -+ -+ error = security_inode_rename(old_dir, old_dentry, new_dir, new_dentry); -+ if (error) -+ return error; -+ -+ dget(new_dentry); -+ target = new_dentry->d_inode; -+ if (target) -+ mutex_lock(&target->i_mutex); -+ if (d_mountpoint(old_dentry)||d_mountpoint(new_dentry)) -+ error = -EBUSY; -+ else -+ error = old_dir->i_op->rename(old_dir, old_dentry, new_dir, new_dentry); -+ if (!error) { -+ if (target) -+ dont_mount(new_dentry); -+ if (!(old_dir->i_sb->s_type->fs_flags & FS_RENAME_DOES_D_MOVE)) -+ d_move(old_dentry, new_dentry); -+ } -+ if (target) -+ mutex_unlock(&target->i_mutex); -+ dput(new_dentry); -+ return error; -+} -+ -+int vfs_rename(struct inode *old_dir, struct dentry *old_dentry, -+ struct inode *new_dir, struct dentry *new_dentry) -+{ -+ int error; -+ int is_dir = S_ISDIR(old_dentry->d_inode->i_mode); -+ const unsigned char *old_name; -+ -+ if (old_dentry->d_inode == new_dentry->d_inode) -+ return 0; -+ -+ error = may_delete(old_dir, old_dentry, is_dir); -+ if (error) -+ return error; -+ -+ if (!new_dentry->d_inode) -+ error = may_create(new_dir, new_dentry); -+ else -+ error = may_delete(new_dir, new_dentry, is_dir); -+ if (error) -+ return error; -+ -+ if (!old_dir->i_op->rename) -+ return -EPERM; -+ -+ old_name = fsnotify_oldname_init(old_dentry->d_name.name); -+ -+ if (is_dir) -+ error = vfs_rename_dir(old_dir,old_dentry,new_dir,new_dentry); -+ else -+ error = vfs_rename_other(old_dir,old_dentry,new_dir,new_dentry); -+ if (!error) -+ fsnotify_move(old_dir, new_dir, old_name, is_dir, -+ new_dentry->d_inode, old_dentry); -+ fsnotify_oldname_free(old_name); -+ -+ return error; -+} -+ -+SYSCALL_DEFINE4(renameat, int, olddfd, const char __user *, oldname, -+ int, newdfd, const char __user *, newname) -+{ -+ struct dentry *old_dir, *new_dir; -+ struct dentry *old_dentry, *new_dentry; -+ struct dentry *trap; -+ struct nameidata oldnd, newnd; -+ char *from; -+ char *to; -+ int error; -+ -+ error = user_path_parent(olddfd, oldname, &oldnd, &from); -+ if (error) -+ goto exit; -+ -+ error = user_path_parent(newdfd, newname, &newnd, &to); -+ if (error) -+ goto exit1; -+ -+ error = -EXDEV; -+ if (oldnd.path.mnt != newnd.path.mnt) -+ goto exit2; -+ -+ old_dir = oldnd.path.dentry; -+ error = -EBUSY; -+ if (oldnd.last_type != LAST_NORM) -+ goto exit2; -+ -+ new_dir = newnd.path.dentry; -+ if (newnd.last_type != LAST_NORM) -+ goto exit2; -+ -+ oldnd.flags &= ~LOOKUP_PARENT; -+ newnd.flags &= ~LOOKUP_PARENT; -+ newnd.flags |= LOOKUP_RENAME_TARGET; -+ -+ trap = lock_rename(new_dir, old_dir); -+ -+ old_dentry = lookup_hash(&oldnd); -+ error = PTR_ERR(old_dentry); -+ if (IS_ERR(old_dentry)) -+ goto exit3; -+ /* source must exist */ -+ error = -ENOENT; -+ if (!old_dentry->d_inode) -+ goto exit4; -+ /* unless the source is a directory trailing slashes give -ENOTDIR */ -+ if (!S_ISDIR(old_dentry->d_inode->i_mode)) { -+ error = -ENOTDIR; -+ if (oldnd.last.name[oldnd.last.len]) -+ goto exit4; -+ if (newnd.last.name[newnd.last.len]) -+ goto exit4; -+ } -+ /* source should not be ancestor of target */ -+ error = -EINVAL; -+ if (old_dentry == trap) -+ goto exit4; -+ new_dentry = lookup_hash(&newnd); -+ error = PTR_ERR(new_dentry); -+ if (IS_ERR(new_dentry)) -+ goto exit4; -+ /* target should not be an ancestor of source */ -+ error = -ENOTEMPTY; -+ if (new_dentry == trap) -+ goto exit5; -+ -+ error = mnt_want_write(oldnd.path.mnt); -+ if (error) -+ goto exit5; -+ error = security_path_rename(&oldnd.path, old_dentry, -+ &newnd.path, new_dentry); -+ if (error) -+ goto exit6; -+ error = vfs_rename(old_dir->d_inode, old_dentry, -+ new_dir->d_inode, new_dentry); -+exit6: -+ mnt_drop_write(oldnd.path.mnt); -+exit5: -+ dput(new_dentry); -+exit4: -+ dput(old_dentry); -+exit3: -+ unlock_rename(new_dir, old_dir); -+exit2: -+ path_put(&newnd.path); -+ putname(to); -+exit1: -+ path_put(&oldnd.path); -+ putname(from); -+exit: -+ return error; -+} -+ -+SYSCALL_DEFINE2(rename, const char __user *, oldname, const char __user *, newname) -+{ -+ return sys_renameat(AT_FDCWD, oldname, AT_FDCWD, newname); -+} -+ -+int vfs_readlink(struct dentry *dentry, char __user *buffer, int buflen, const char *link) -+{ -+ int len; -+ -+ len = PTR_ERR(link); -+ if (IS_ERR(link)) -+ goto out; -+ -+ len = strlen(link); -+ if (len > (unsigned) buflen) -+ len = buflen; -+ if (copy_to_user(buffer, link, len)) -+ len = -EFAULT; -+out: -+ return len; -+} -+ -+/* -+ * A helper for ->readlink(). This should be used *ONLY* for symlinks that -+ * have ->follow_link() touching nd only in nd_set_link(). Using (or not -+ * using) it for any given inode is up to filesystem. -+ */ -+int generic_readlink(struct dentry *dentry, char __user *buffer, int buflen) -+{ -+ struct nameidata nd; -+ void *cookie; -+ int res; -+ -+ nd.depth = 0; -+ cookie = dentry->d_inode->i_op->follow_link(dentry, &nd); -+ if (IS_ERR(cookie)) -+ return PTR_ERR(cookie); -+ -+ res = vfs_readlink(dentry, buffer, buflen, nd_get_link(&nd)); -+ if (dentry->d_inode->i_op->put_link) -+ dentry->d_inode->i_op->put_link(dentry, &nd, cookie); -+ return res; -+} -+ -+int vfs_follow_link(struct nameidata *nd, const char *link) -+{ -+ return __vfs_follow_link(nd, link); -+} -+ -+/* get the link contents into pagecache */ -+static char *page_getlink(struct dentry * dentry, struct page **ppage) -+{ -+ char *kaddr; -+ struct page *page; -+ struct address_space *mapping = dentry->d_inode->i_mapping; -+ page = read_mapping_page(mapping, 0, NULL); -+ if (IS_ERR(page)) -+ return (char*)page; -+ *ppage = page; -+ kaddr = kmap(page); -+ nd_terminate_link(kaddr, dentry->d_inode->i_size, PAGE_SIZE - 1); -+ return kaddr; -+} -+ -+int page_readlink(struct dentry *dentry, char __user *buffer, int buflen) -+{ -+ struct page *page = NULL; -+ char *s = page_getlink(dentry, &page); -+ int res = vfs_readlink(dentry,buffer,buflen,s); -+ if (page) { -+ kunmap(page); -+ page_cache_release(page); -+ } -+ return res; -+} -+ -+void *page_follow_link_light(struct dentry *dentry, struct nameidata *nd) -+{ -+ struct page *page = NULL; -+ nd_set_link(nd, page_getlink(dentry, &page)); -+ return page; -+} -+ -+void page_put_link(struct dentry *dentry, struct nameidata *nd, void *cookie) -+{ -+ struct page *page = cookie; -+ -+ if (page) { -+ kunmap(page); -+ page_cache_release(page); -+ } -+} -+ -+/* -+ * The nofs argument instructs pagecache_write_begin to pass AOP_FLAG_NOFS -+ */ -+int __page_symlink(struct inode *inode, const char *symname, int len, int nofs) -+{ -+ struct address_space *mapping = inode->i_mapping; -+ struct page *page; -+ void *fsdata; -+ int err; -+ char *kaddr; -+ unsigned int flags = AOP_FLAG_UNINTERRUPTIBLE; -+ if (nofs) -+ flags |= AOP_FLAG_NOFS; -+ -+retry: -+ err = pagecache_write_begin(NULL, mapping, 0, len-1, -+ flags, &page, &fsdata); -+ if (err) -+ goto fail; -+ -+ kaddr = kmap_atomic(page, KM_USER0); -+ memcpy(kaddr, symname, len-1); -+ kunmap_atomic(kaddr, KM_USER0); -+ -+ err = pagecache_write_end(NULL, mapping, 0, len-1, len-1, -+ page, fsdata); -+ if (err < 0) -+ goto fail; -+ if (err < len-1) -+ goto retry; -+ -+ mark_inode_dirty(inode); -+ return 0; -+fail: -+ return err; -+} -+ -+int page_symlink(struct inode *inode, const char *symname, int len) -+{ -+ return __page_symlink(inode, symname, len, -+ !(mapping_gfp_mask(inode->i_mapping) & __GFP_FS)); -+} -+ -+const struct inode_operations page_symlink_inode_operations = { -+ .readlink = generic_readlink, -+ .follow_link = page_follow_link_light, -+ .put_link = page_put_link, -+}; -+ -+EXPORT_SYMBOL(user_path_at); -+EXPORT_SYMBOL(follow_down); -+EXPORT_SYMBOL(follow_up); -+EXPORT_SYMBOL(get_write_access); /* binfmt_aout */ -+EXPORT_SYMBOL(getname); -+EXPORT_SYMBOL(lock_rename); -+EXPORT_SYMBOL(lookup_one_len); -+EXPORT_SYMBOL(page_follow_link_light); -+EXPORT_SYMBOL(page_put_link); -+EXPORT_SYMBOL(page_readlink); -+EXPORT_SYMBOL(__page_symlink); -+EXPORT_SYMBOL(page_symlink); -+EXPORT_SYMBOL(page_symlink_inode_operations); -+EXPORT_SYMBOL(path_lookup); -+EXPORT_SYMBOL(kern_path); -+EXPORT_SYMBOL(vfs_path_lookup); -+EXPORT_SYMBOL(inode_permission); -+EXPORT_SYMBOL(file_permission); -+EXPORT_SYMBOL(unlock_rename); -+EXPORT_SYMBOL(vfs_create); -+EXPORT_SYMBOL(vfs_follow_link); -+EXPORT_SYMBOL(vfs_link); -+EXPORT_SYMBOL(vfs_mkdir); -+EXPORT_SYMBOL(vfs_mknod); -+EXPORT_SYMBOL(generic_permission); -+EXPORT_SYMBOL(vfs_readlink); -+EXPORT_SYMBOL(vfs_rename); -+EXPORT_SYMBOL(vfs_rmdir); -+EXPORT_SYMBOL(vfs_symlink); -+EXPORT_SYMBOL(vfs_unlink); -+EXPORT_SYMBOL(dentry_unhash); -+EXPORT_SYMBOL(generic_readlink); -diff -Nur linux-2.6.36.orig/fs/namespace.c linux-2.6.36/fs/namespace.c ---- linux-2.6.36.orig/fs/namespace.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/fs/namespace.c 2011-01-10 19:52:38.000000000 +0100 -@@ -1322,6 +1322,7 @@ - } - return 0; - } -+EXPORT_SYMBOL(iterate_mounts); - - static void cleanup_group_ids(struct vfsmount *mnt, struct vfsmount *end) - { -diff -Nur linux-2.6.36.orig/fs/notify/group.c linux-2.6.36/fs/notify/group.c ---- linux-2.6.36.orig/fs/notify/group.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/fs/notify/group.c 2011-01-10 19:52:38.000000000 +0100 -@@ -22,6 +22,7 @@ - #include - #include - #include -+#include - - #include - #include "fsnotify.h" -@@ -70,6 +71,7 @@ - if (atomic_dec_and_test(&group->refcnt)) - fsnotify_destroy_group(group); - } -+EXPORT_SYMBOL(fsnotify_put_group); - - /* - * Create a new fsnotify_group and hold a reference for the group returned. -@@ -102,3 +104,4 @@ - - return group; - } -+EXPORT_SYMBOL(fsnotify_alloc_group); -diff -Nur linux-2.6.36.orig/fs/notify/mark.c linux-2.6.36/fs/notify/mark.c ---- linux-2.6.36.orig/fs/notify/mark.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/fs/notify/mark.c 2011-01-10 19:52:38.000000000 +0100 -@@ -113,6 +113,7 @@ - if (atomic_dec_and_test(&mark->refcnt)) - mark->free_mark(mark); - } -+EXPORT_SYMBOL(fsnotify_put_mark); - - /* - * Any time a mark is getting freed we end up here. -@@ -190,6 +191,7 @@ - if (unlikely(atomic_dec_and_test(&group->num_marks))) - fsnotify_final_destroy_group(group); - } -+EXPORT_SYMBOL(fsnotify_destroy_mark); - - void fsnotify_set_mark_mask_locked(struct fsnotify_mark *mark, __u32 mask) - { -@@ -277,6 +279,7 @@ - - return ret; - } -+EXPORT_SYMBOL(fsnotify_add_mark); - - /* - * clear any marks in a group in which mark->flags & flags is true -@@ -332,6 +335,7 @@ - atomic_set(&mark->refcnt, 1); - mark->free_mark = free_mark; - } -+EXPORT_SYMBOL(fsnotify_init_mark); - - static int fsnotify_mark_destroy(void *ignored) - { -diff -Nur linux-2.6.36.orig/fs/open.c linux-2.6.36/fs/open.c ---- linux-2.6.36.orig/fs/open.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/fs/open.c 2011-01-10 19:52:38.000000000 +0100 -@@ -60,6 +60,7 @@ - mutex_unlock(&dentry->d_inode->i_mutex); - return ret; - } -+EXPORT_SYMBOL(do_truncate); - - static long do_sys_truncate(const char __user *pathname, loff_t length) - { -diff -Nur linux-2.6.36.orig/fs/splice.c linux-2.6.36/fs/splice.c ---- linux-2.6.36.orig/fs/splice.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/fs/splice.c 2011-01-10 19:52:38.000000000 +0100 -@@ -1092,8 +1092,8 @@ - /* - * Attempt to initiate a splice from pipe to file. - */ --static long do_splice_from(struct pipe_inode_info *pipe, struct file *out, -- loff_t *ppos, size_t len, unsigned int flags) -+long do_splice_from(struct pipe_inode_info *pipe, struct file *out, -+ loff_t *ppos, size_t len, unsigned int flags) - { - ssize_t (*splice_write)(struct pipe_inode_info *, struct file *, - loff_t *, size_t, unsigned int); -@@ -1116,13 +1116,14 @@ - - return splice_write(pipe, out, ppos, len, flags); - } -+EXPORT_SYMBOL(do_splice_from); - - /* - * Attempt to initiate a splice from a file to a pipe. - */ --static long do_splice_to(struct file *in, loff_t *ppos, -- struct pipe_inode_info *pipe, size_t len, -- unsigned int flags) -+long do_splice_to(struct file *in, loff_t *ppos, -+ struct pipe_inode_info *pipe, size_t len, -+ unsigned int flags) - { - ssize_t (*splice_read)(struct file *, loff_t *, - struct pipe_inode_info *, size_t, unsigned int); -@@ -1142,6 +1143,7 @@ - - return splice_read(in, ppos, pipe, len, flags); - } -+EXPORT_SYMBOL(do_splice_to); - - /** - * splice_direct_to_actor - splices data directly between two non-pipes -diff -Nur linux-2.6.36.orig/fs/splice.c.orig linux-2.6.36/fs/splice.c.orig ---- linux-2.6.36.orig/fs/splice.c.orig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/splice.c.orig 2011-01-10 19:52:38.000000000 +0100 -@@ -0,0 +1,2076 @@ -+/* -+ * "splice": joining two ropes together by interweaving their strands. -+ * -+ * This is the "extended pipe" functionality, where a pipe is used as -+ * an arbitrary in-memory buffer. Think of a pipe as a small kernel -+ * buffer that you can use to transfer data from one end to the other. -+ * -+ * The traditional unix read/write is extended with a "splice()" operation -+ * that transfers data buffers to or from a pipe buffer. -+ * -+ * Named by Larry McVoy, original implementation from Linus, extended by -+ * Jens to support splicing to files, network, direct splicing, etc and -+ * fixing lots of bugs. -+ * -+ * Copyright (C) 2005-2006 Jens Axboe -+ * Copyright (C) 2005-2006 Linus Torvalds -+ * Copyright (C) 2006 Ingo Molnar -+ * -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* -+ * Attempt to steal a page from a pipe buffer. This should perhaps go into -+ * a vm helper function, it's already simplified quite a bit by the -+ * addition of remove_mapping(). If success is returned, the caller may -+ * attempt to reuse this page for another destination. -+ */ -+static int page_cache_pipe_buf_steal(struct pipe_inode_info *pipe, -+ struct pipe_buffer *buf) -+{ -+ struct page *page = buf->page; -+ struct address_space *mapping; -+ -+ lock_page(page); -+ -+ mapping = page_mapping(page); -+ if (mapping) { -+ WARN_ON(!PageUptodate(page)); -+ -+ /* -+ * At least for ext2 with nobh option, we need to wait on -+ * writeback completing on this page, since we'll remove it -+ * from the pagecache. Otherwise truncate wont wait on the -+ * page, allowing the disk blocks to be reused by someone else -+ * before we actually wrote our data to them. fs corruption -+ * ensues. -+ */ -+ wait_on_page_writeback(page); -+ -+ if (page_has_private(page) && -+ !try_to_release_page(page, GFP_KERNEL)) -+ goto out_unlock; -+ -+ /* -+ * If we succeeded in removing the mapping, set LRU flag -+ * and return good. -+ */ -+ if (remove_mapping(mapping, page)) { -+ buf->flags |= PIPE_BUF_FLAG_LRU; -+ return 0; -+ } -+ } -+ -+ /* -+ * Raced with truncate or failed to remove page from current -+ * address space, unlock and return failure. -+ */ -+out_unlock: -+ unlock_page(page); -+ return 1; -+} -+ -+static void page_cache_pipe_buf_release(struct pipe_inode_info *pipe, -+ struct pipe_buffer *buf) -+{ -+ page_cache_release(buf->page); -+ buf->flags &= ~PIPE_BUF_FLAG_LRU; -+} -+ -+/* -+ * Check whether the contents of buf is OK to access. Since the content -+ * is a page cache page, IO may be in flight. -+ */ -+static int page_cache_pipe_buf_confirm(struct pipe_inode_info *pipe, -+ struct pipe_buffer *buf) -+{ -+ struct page *page = buf->page; -+ int err; -+ -+ if (!PageUptodate(page)) { -+ lock_page(page); -+ -+ /* -+ * Page got truncated/unhashed. This will cause a 0-byte -+ * splice, if this is the first page. -+ */ -+ if (!page->mapping) { -+ err = -ENODATA; -+ goto error; -+ } -+ -+ /* -+ * Uh oh, read-error from disk. -+ */ -+ if (!PageUptodate(page)) { -+ err = -EIO; -+ goto error; -+ } -+ -+ /* -+ * Page is ok afterall, we are done. -+ */ -+ unlock_page(page); -+ } -+ -+ return 0; -+error: -+ unlock_page(page); -+ return err; -+} -+ -+static const struct pipe_buf_operations page_cache_pipe_buf_ops = { -+ .can_merge = 0, -+ .map = generic_pipe_buf_map, -+ .unmap = generic_pipe_buf_unmap, -+ .confirm = page_cache_pipe_buf_confirm, -+ .release = page_cache_pipe_buf_release, -+ .steal = page_cache_pipe_buf_steal, -+ .get = generic_pipe_buf_get, -+}; -+ -+static int user_page_pipe_buf_steal(struct pipe_inode_info *pipe, -+ struct pipe_buffer *buf) -+{ -+ if (!(buf->flags & PIPE_BUF_FLAG_GIFT)) -+ return 1; -+ -+ buf->flags |= PIPE_BUF_FLAG_LRU; -+ return generic_pipe_buf_steal(pipe, buf); -+} -+ -+static const struct pipe_buf_operations user_page_pipe_buf_ops = { -+ .can_merge = 0, -+ .map = generic_pipe_buf_map, -+ .unmap = generic_pipe_buf_unmap, -+ .confirm = generic_pipe_buf_confirm, -+ .release = page_cache_pipe_buf_release, -+ .steal = user_page_pipe_buf_steal, -+ .get = generic_pipe_buf_get, -+}; -+ -+/** -+ * splice_to_pipe - fill passed data into a pipe -+ * @pipe: pipe to fill -+ * @spd: data to fill -+ * -+ * Description: -+ * @spd contains a map of pages and len/offset tuples, along with -+ * the struct pipe_buf_operations associated with these pages. This -+ * function will link that data to the pipe. -+ * -+ */ -+ssize_t splice_to_pipe(struct pipe_inode_info *pipe, -+ struct splice_pipe_desc *spd) -+{ -+ unsigned int spd_pages = spd->nr_pages; -+ int ret, do_wakeup, page_nr; -+ -+ ret = 0; -+ do_wakeup = 0; -+ page_nr = 0; -+ -+ pipe_lock(pipe); -+ -+ for (;;) { -+ if (!pipe->readers) { -+ send_sig(SIGPIPE, current, 0); -+ if (!ret) -+ ret = -EPIPE; -+ break; -+ } -+ -+ if (pipe->nrbufs < pipe->buffers) { -+ int newbuf = (pipe->curbuf + pipe->nrbufs) & (pipe->buffers - 1); -+ struct pipe_buffer *buf = pipe->bufs + newbuf; -+ -+ buf->page = spd->pages[page_nr]; -+ buf->offset = spd->partial[page_nr].offset; -+ buf->len = spd->partial[page_nr].len; -+ buf->private = spd->partial[page_nr].private; -+ buf->ops = spd->ops; -+ if (spd->flags & SPLICE_F_GIFT) -+ buf->flags |= PIPE_BUF_FLAG_GIFT; -+ -+ pipe->nrbufs++; -+ page_nr++; -+ ret += buf->len; -+ -+ if (pipe->inode) -+ do_wakeup = 1; -+ -+ if (!--spd->nr_pages) -+ break; -+ if (pipe->nrbufs < pipe->buffers) -+ continue; -+ -+ break; -+ } -+ -+ if (spd->flags & SPLICE_F_NONBLOCK) { -+ if (!ret) -+ ret = -EAGAIN; -+ break; -+ } -+ -+ if (signal_pending(current)) { -+ if (!ret) -+ ret = -ERESTARTSYS; -+ break; -+ } -+ -+ if (do_wakeup) { -+ smp_mb(); -+ if (waitqueue_active(&pipe->wait)) -+ wake_up_interruptible_sync(&pipe->wait); -+ kill_fasync(&pipe->fasync_readers, SIGIO, POLL_IN); -+ do_wakeup = 0; -+ } -+ -+ pipe->waiting_writers++; -+ pipe_wait(pipe); -+ pipe->waiting_writers--; -+ } -+ -+ pipe_unlock(pipe); -+ -+ if (do_wakeup) { -+ smp_mb(); -+ if (waitqueue_active(&pipe->wait)) -+ wake_up_interruptible(&pipe->wait); -+ kill_fasync(&pipe->fasync_readers, SIGIO, POLL_IN); -+ } -+ -+ while (page_nr < spd_pages) -+ spd->spd_release(spd, page_nr++); -+ -+ return ret; -+} -+ -+static void spd_release_page(struct splice_pipe_desc *spd, unsigned int i) -+{ -+ page_cache_release(spd->pages[i]); -+} -+ -+/* -+ * Check if we need to grow the arrays holding pages and partial page -+ * descriptions. -+ */ -+int splice_grow_spd(struct pipe_inode_info *pipe, struct splice_pipe_desc *spd) -+{ -+ if (pipe->buffers <= PIPE_DEF_BUFFERS) -+ return 0; -+ -+ spd->pages = kmalloc(pipe->buffers * sizeof(struct page *), GFP_KERNEL); -+ spd->partial = kmalloc(pipe->buffers * sizeof(struct partial_page), GFP_KERNEL); -+ -+ if (spd->pages && spd->partial) -+ return 0; -+ -+ kfree(spd->pages); -+ kfree(spd->partial); -+ return -ENOMEM; -+} -+ -+void splice_shrink_spd(struct pipe_inode_info *pipe, -+ struct splice_pipe_desc *spd) -+{ -+ if (pipe->buffers <= PIPE_DEF_BUFFERS) -+ return; -+ -+ kfree(spd->pages); -+ kfree(spd->partial); -+} -+ -+static int -+__generic_file_splice_read(struct file *in, loff_t *ppos, -+ struct pipe_inode_info *pipe, size_t len, -+ unsigned int flags) -+{ -+ struct address_space *mapping = in->f_mapping; -+ unsigned int loff, nr_pages, req_pages; -+ struct page *pages[PIPE_DEF_BUFFERS]; -+ struct partial_page partial[PIPE_DEF_BUFFERS]; -+ struct page *page; -+ pgoff_t index, end_index; -+ loff_t isize; -+ int error, page_nr; -+ struct splice_pipe_desc spd = { -+ .pages = pages, -+ .partial = partial, -+ .flags = flags, -+ .ops = &page_cache_pipe_buf_ops, -+ .spd_release = spd_release_page, -+ }; -+ -+ if (splice_grow_spd(pipe, &spd)) -+ return -ENOMEM; -+ -+ index = *ppos >> PAGE_CACHE_SHIFT; -+ loff = *ppos & ~PAGE_CACHE_MASK; -+ req_pages = (len + loff + PAGE_CACHE_SIZE - 1) >> PAGE_CACHE_SHIFT; -+ nr_pages = min(req_pages, pipe->buffers); -+ -+ /* -+ * Lookup the (hopefully) full range of pages we need. -+ */ -+ spd.nr_pages = find_get_pages_contig(mapping, index, nr_pages, spd.pages); -+ index += spd.nr_pages; -+ -+ /* -+ * If find_get_pages_contig() returned fewer pages than we needed, -+ * readahead/allocate the rest and fill in the holes. -+ */ -+ if (spd.nr_pages < nr_pages) -+ page_cache_sync_readahead(mapping, &in->f_ra, in, -+ index, req_pages - spd.nr_pages); -+ -+ error = 0; -+ while (spd.nr_pages < nr_pages) { -+ /* -+ * Page could be there, find_get_pages_contig() breaks on -+ * the first hole. -+ */ -+ page = find_get_page(mapping, index); -+ if (!page) { -+ /* -+ * page didn't exist, allocate one. -+ */ -+ page = page_cache_alloc_cold(mapping); -+ if (!page) -+ break; -+ -+ error = add_to_page_cache_lru(page, mapping, index, -+ GFP_KERNEL); -+ if (unlikely(error)) { -+ page_cache_release(page); -+ if (error == -EEXIST) -+ continue; -+ break; -+ } -+ /* -+ * add_to_page_cache() locks the page, unlock it -+ * to avoid convoluting the logic below even more. -+ */ -+ unlock_page(page); -+ } -+ -+ spd.pages[spd.nr_pages++] = page; -+ index++; -+ } -+ -+ /* -+ * Now loop over the map and see if we need to start IO on any -+ * pages, fill in the partial map, etc. -+ */ -+ index = *ppos >> PAGE_CACHE_SHIFT; -+ nr_pages = spd.nr_pages; -+ spd.nr_pages = 0; -+ for (page_nr = 0; page_nr < nr_pages; page_nr++) { -+ unsigned int this_len; -+ -+ if (!len) -+ break; -+ -+ /* -+ * this_len is the max we'll use from this page -+ */ -+ this_len = min_t(unsigned long, len, PAGE_CACHE_SIZE - loff); -+ page = spd.pages[page_nr]; -+ -+ if (PageReadahead(page)) -+ page_cache_async_readahead(mapping, &in->f_ra, in, -+ page, index, req_pages - page_nr); -+ -+ /* -+ * If the page isn't uptodate, we may need to start io on it -+ */ -+ if (!PageUptodate(page)) { -+ lock_page(page); -+ -+ /* -+ * Page was truncated, or invalidated by the -+ * filesystem. Redo the find/create, but this time the -+ * page is kept locked, so there's no chance of another -+ * race with truncate/invalidate. -+ */ -+ if (!page->mapping) { -+ unlock_page(page); -+ page = find_or_create_page(mapping, index, -+ mapping_gfp_mask(mapping)); -+ -+ if (!page) { -+ error = -ENOMEM; -+ break; -+ } -+ page_cache_release(spd.pages[page_nr]); -+ spd.pages[page_nr] = page; -+ } -+ /* -+ * page was already under io and is now done, great -+ */ -+ if (PageUptodate(page)) { -+ unlock_page(page); -+ goto fill_it; -+ } -+ -+ /* -+ * need to read in the page -+ */ -+ error = mapping->a_ops->readpage(in, page); -+ if (unlikely(error)) { -+ /* -+ * We really should re-lookup the page here, -+ * but it complicates things a lot. Instead -+ * lets just do what we already stored, and -+ * we'll get it the next time we are called. -+ */ -+ if (error == AOP_TRUNCATED_PAGE) -+ error = 0; -+ -+ break; -+ } -+ } -+fill_it: -+ /* -+ * i_size must be checked after PageUptodate. -+ */ -+ isize = i_size_read(mapping->host); -+ end_index = (isize - 1) >> PAGE_CACHE_SHIFT; -+ if (unlikely(!isize || index > end_index)) -+ break; -+ -+ /* -+ * if this is the last page, see if we need to shrink -+ * the length and stop -+ */ -+ if (end_index == index) { -+ unsigned int plen; -+ -+ /* -+ * max good bytes in this page -+ */ -+ plen = ((isize - 1) & ~PAGE_CACHE_MASK) + 1; -+ if (plen <= loff) -+ break; -+ -+ /* -+ * force quit after adding this page -+ */ -+ this_len = min(this_len, plen - loff); -+ len = this_len; -+ } -+ -+ spd.partial[page_nr].offset = loff; -+ spd.partial[page_nr].len = this_len; -+ len -= this_len; -+ loff = 0; -+ spd.nr_pages++; -+ index++; -+ } -+ -+ /* -+ * Release any pages at the end, if we quit early. 'page_nr' is how far -+ * we got, 'nr_pages' is how many pages are in the map. -+ */ -+ while (page_nr < nr_pages) -+ page_cache_release(spd.pages[page_nr++]); -+ in->f_ra.prev_pos = (loff_t)index << PAGE_CACHE_SHIFT; -+ -+ if (spd.nr_pages) -+ error = splice_to_pipe(pipe, &spd); -+ -+ splice_shrink_spd(pipe, &spd); -+ return error; -+} -+ -+/** -+ * generic_file_splice_read - splice data from file to a pipe -+ * @in: file to splice from -+ * @ppos: position in @in -+ * @pipe: pipe to splice to -+ * @len: number of bytes to splice -+ * @flags: splice modifier flags -+ * -+ * Description: -+ * Will read pages from given file and fill them into a pipe. Can be -+ * used as long as the address_space operations for the source implements -+ * a readpage() hook. -+ * -+ */ -+ssize_t generic_file_splice_read(struct file *in, loff_t *ppos, -+ struct pipe_inode_info *pipe, size_t len, -+ unsigned int flags) -+{ -+ loff_t isize, left; -+ int ret; -+ -+ isize = i_size_read(in->f_mapping->host); -+ if (unlikely(*ppos >= isize)) -+ return 0; -+ -+ left = isize - *ppos; -+ if (unlikely(left < len)) -+ len = left; -+ -+ ret = __generic_file_splice_read(in, ppos, pipe, len, flags); -+ if (ret > 0) { -+ *ppos += ret; -+ file_accessed(in); -+ } -+ -+ return ret; -+} -+EXPORT_SYMBOL(generic_file_splice_read); -+ -+static const struct pipe_buf_operations default_pipe_buf_ops = { -+ .can_merge = 0, -+ .map = generic_pipe_buf_map, -+ .unmap = generic_pipe_buf_unmap, -+ .confirm = generic_pipe_buf_confirm, -+ .release = generic_pipe_buf_release, -+ .steal = generic_pipe_buf_steal, -+ .get = generic_pipe_buf_get, -+}; -+ -+static ssize_t kernel_readv(struct file *file, const struct iovec *vec, -+ unsigned long vlen, loff_t offset) -+{ -+ mm_segment_t old_fs; -+ loff_t pos = offset; -+ ssize_t res; -+ -+ old_fs = get_fs(); -+ set_fs(get_ds()); -+ /* The cast to a user pointer is valid due to the set_fs() */ -+ res = vfs_readv(file, (const struct iovec __user *)vec, vlen, &pos); -+ set_fs(old_fs); -+ -+ return res; -+} -+ -+static ssize_t kernel_write(struct file *file, const char *buf, size_t count, -+ loff_t pos) -+{ -+ mm_segment_t old_fs; -+ ssize_t res; -+ -+ old_fs = get_fs(); -+ set_fs(get_ds()); -+ /* The cast to a user pointer is valid due to the set_fs() */ -+ res = vfs_write(file, (const char __user *)buf, count, &pos); -+ set_fs(old_fs); -+ -+ return res; -+} -+ -+ssize_t default_file_splice_read(struct file *in, loff_t *ppos, -+ struct pipe_inode_info *pipe, size_t len, -+ unsigned int flags) -+{ -+ unsigned int nr_pages; -+ unsigned int nr_freed; -+ size_t offset; -+ struct page *pages[PIPE_DEF_BUFFERS]; -+ struct partial_page partial[PIPE_DEF_BUFFERS]; -+ struct iovec *vec, __vec[PIPE_DEF_BUFFERS]; -+ ssize_t res; -+ size_t this_len; -+ int error; -+ int i; -+ struct splice_pipe_desc spd = { -+ .pages = pages, -+ .partial = partial, -+ .flags = flags, -+ .ops = &default_pipe_buf_ops, -+ .spd_release = spd_release_page, -+ }; -+ -+ if (splice_grow_spd(pipe, &spd)) -+ return -ENOMEM; -+ -+ res = -ENOMEM; -+ vec = __vec; -+ if (pipe->buffers > PIPE_DEF_BUFFERS) { -+ vec = kmalloc(pipe->buffers * sizeof(struct iovec), GFP_KERNEL); -+ if (!vec) -+ goto shrink_ret; -+ } -+ -+ offset = *ppos & ~PAGE_CACHE_MASK; -+ nr_pages = (len + offset + PAGE_CACHE_SIZE - 1) >> PAGE_CACHE_SHIFT; -+ -+ for (i = 0; i < nr_pages && i < pipe->buffers && len; i++) { -+ struct page *page; -+ -+ page = alloc_page(GFP_USER); -+ error = -ENOMEM; -+ if (!page) -+ goto err; -+ -+ this_len = min_t(size_t, len, PAGE_CACHE_SIZE - offset); -+ vec[i].iov_base = (void __user *) page_address(page); -+ vec[i].iov_len = this_len; -+ spd.pages[i] = page; -+ spd.nr_pages++; -+ len -= this_len; -+ offset = 0; -+ } -+ -+ res = kernel_readv(in, vec, spd.nr_pages, *ppos); -+ if (res < 0) { -+ error = res; -+ goto err; -+ } -+ -+ error = 0; -+ if (!res) -+ goto err; -+ -+ nr_freed = 0; -+ for (i = 0; i < spd.nr_pages; i++) { -+ this_len = min_t(size_t, vec[i].iov_len, res); -+ spd.partial[i].offset = 0; -+ spd.partial[i].len = this_len; -+ if (!this_len) { -+ __free_page(spd.pages[i]); -+ spd.pages[i] = NULL; -+ nr_freed++; -+ } -+ res -= this_len; -+ } -+ spd.nr_pages -= nr_freed; -+ -+ res = splice_to_pipe(pipe, &spd); -+ if (res > 0) -+ *ppos += res; -+ -+shrink_ret: -+ if (vec != __vec) -+ kfree(vec); -+ splice_shrink_spd(pipe, &spd); -+ return res; -+ -+err: -+ for (i = 0; i < spd.nr_pages; i++) -+ __free_page(spd.pages[i]); -+ -+ res = error; -+ goto shrink_ret; -+} -+EXPORT_SYMBOL(default_file_splice_read); -+ -+/* -+ * Send 'sd->len' bytes to socket from 'sd->file' at position 'sd->pos' -+ * using sendpage(). Return the number of bytes sent. -+ */ -+static int pipe_to_sendpage(struct pipe_inode_info *pipe, -+ struct pipe_buffer *buf, struct splice_desc *sd) -+{ -+ struct file *file = sd->u.file; -+ loff_t pos = sd->pos; -+ int ret, more; -+ -+ ret = buf->ops->confirm(pipe, buf); -+ if (!ret) { -+ more = (sd->flags & SPLICE_F_MORE) || sd->len < sd->total_len; -+ if (file->f_op && file->f_op->sendpage) -+ ret = file->f_op->sendpage(file, buf->page, buf->offset, -+ sd->len, &pos, more); -+ else -+ ret = -EINVAL; -+ } -+ -+ return ret; -+} -+ -+/* -+ * This is a little more tricky than the file -> pipe splicing. There are -+ * basically three cases: -+ * -+ * - Destination page already exists in the address space and there -+ * are users of it. For that case we have no other option that -+ * copying the data. Tough luck. -+ * - Destination page already exists in the address space, but there -+ * are no users of it. Make sure it's uptodate, then drop it. Fall -+ * through to last case. -+ * - Destination page does not exist, we can add the pipe page to -+ * the page cache and avoid the copy. -+ * -+ * If asked to move pages to the output file (SPLICE_F_MOVE is set in -+ * sd->flags), we attempt to migrate pages from the pipe to the output -+ * file address space page cache. This is possible if no one else has -+ * the pipe page referenced outside of the pipe and page cache. If -+ * SPLICE_F_MOVE isn't set, or we cannot move the page, we simply create -+ * a new page in the output file page cache and fill/dirty that. -+ */ -+int pipe_to_file(struct pipe_inode_info *pipe, struct pipe_buffer *buf, -+ struct splice_desc *sd) -+{ -+ struct file *file = sd->u.file; -+ struct address_space *mapping = file->f_mapping; -+ unsigned int offset, this_len; -+ struct page *page; -+ void *fsdata; -+ int ret; -+ -+ /* -+ * make sure the data in this buffer is uptodate -+ */ -+ ret = buf->ops->confirm(pipe, buf); -+ if (unlikely(ret)) -+ return ret; -+ -+ offset = sd->pos & ~PAGE_CACHE_MASK; -+ -+ this_len = sd->len; -+ if (this_len + offset > PAGE_CACHE_SIZE) -+ this_len = PAGE_CACHE_SIZE - offset; -+ -+ ret = pagecache_write_begin(file, mapping, sd->pos, this_len, -+ AOP_FLAG_UNINTERRUPTIBLE, &page, &fsdata); -+ if (unlikely(ret)) -+ goto out; -+ -+ if (buf->page != page) { -+ /* -+ * Careful, ->map() uses KM_USER0! -+ */ -+ char *src = buf->ops->map(pipe, buf, 1); -+ char *dst = kmap_atomic(page, KM_USER1); -+ -+ memcpy(dst + offset, src + buf->offset, this_len); -+ flush_dcache_page(page); -+ kunmap_atomic(dst, KM_USER1); -+ buf->ops->unmap(pipe, buf, src); -+ } -+ ret = pagecache_write_end(file, mapping, sd->pos, this_len, this_len, -+ page, fsdata); -+out: -+ return ret; -+} -+EXPORT_SYMBOL(pipe_to_file); -+ -+static void wakeup_pipe_writers(struct pipe_inode_info *pipe) -+{ -+ smp_mb(); -+ if (waitqueue_active(&pipe->wait)) -+ wake_up_interruptible(&pipe->wait); -+ kill_fasync(&pipe->fasync_writers, SIGIO, POLL_OUT); -+} -+ -+/** -+ * splice_from_pipe_feed - feed available data from a pipe to a file -+ * @pipe: pipe to splice from -+ * @sd: information to @actor -+ * @actor: handler that splices the data -+ * -+ * Description: -+ * This function loops over the pipe and calls @actor to do the -+ * actual moving of a single struct pipe_buffer to the desired -+ * destination. It returns when there's no more buffers left in -+ * the pipe or if the requested number of bytes (@sd->total_len) -+ * have been copied. It returns a positive number (one) if the -+ * pipe needs to be filled with more data, zero if the required -+ * number of bytes have been copied and -errno on error. -+ * -+ * This, together with splice_from_pipe_{begin,end,next}, may be -+ * used to implement the functionality of __splice_from_pipe() when -+ * locking is required around copying the pipe buffers to the -+ * destination. -+ */ -+int splice_from_pipe_feed(struct pipe_inode_info *pipe, struct splice_desc *sd, -+ splice_actor *actor) -+{ -+ int ret; -+ -+ while (pipe->nrbufs) { -+ struct pipe_buffer *buf = pipe->bufs + pipe->curbuf; -+ const struct pipe_buf_operations *ops = buf->ops; -+ -+ sd->len = buf->len; -+ if (sd->len > sd->total_len) -+ sd->len = sd->total_len; -+ -+ ret = actor(pipe, buf, sd); -+ if (ret <= 0) { -+ if (ret == -ENODATA) -+ ret = 0; -+ return ret; -+ } -+ buf->offset += ret; -+ buf->len -= ret; -+ -+ sd->num_spliced += ret; -+ sd->len -= ret; -+ sd->pos += ret; -+ sd->total_len -= ret; -+ -+ if (!buf->len) { -+ buf->ops = NULL; -+ ops->release(pipe, buf); -+ pipe->curbuf = (pipe->curbuf + 1) & (pipe->buffers - 1); -+ pipe->nrbufs--; -+ if (pipe->inode) -+ sd->need_wakeup = true; -+ } -+ -+ if (!sd->total_len) -+ return 0; -+ } -+ -+ return 1; -+} -+EXPORT_SYMBOL(splice_from_pipe_feed); -+ -+/** -+ * splice_from_pipe_next - wait for some data to splice from -+ * @pipe: pipe to splice from -+ * @sd: information about the splice operation -+ * -+ * Description: -+ * This function will wait for some data and return a positive -+ * value (one) if pipe buffers are available. It will return zero -+ * or -errno if no more data needs to be spliced. -+ */ -+int splice_from_pipe_next(struct pipe_inode_info *pipe, struct splice_desc *sd) -+{ -+ while (!pipe->nrbufs) { -+ if (!pipe->writers) -+ return 0; -+ -+ if (!pipe->waiting_writers && sd->num_spliced) -+ return 0; -+ -+ if (sd->flags & SPLICE_F_NONBLOCK) -+ return -EAGAIN; -+ -+ if (signal_pending(current)) -+ return -ERESTARTSYS; -+ -+ if (sd->need_wakeup) { -+ wakeup_pipe_writers(pipe); -+ sd->need_wakeup = false; -+ } -+ -+ pipe_wait(pipe); -+ } -+ -+ return 1; -+} -+EXPORT_SYMBOL(splice_from_pipe_next); -+ -+/** -+ * splice_from_pipe_begin - start splicing from pipe -+ * @sd: information about the splice operation -+ * -+ * Description: -+ * This function should be called before a loop containing -+ * splice_from_pipe_next() and splice_from_pipe_feed() to -+ * initialize the necessary fields of @sd. -+ */ -+void splice_from_pipe_begin(struct splice_desc *sd) -+{ -+ sd->num_spliced = 0; -+ sd->need_wakeup = false; -+} -+EXPORT_SYMBOL(splice_from_pipe_begin); -+ -+/** -+ * splice_from_pipe_end - finish splicing from pipe -+ * @pipe: pipe to splice from -+ * @sd: information about the splice operation -+ * -+ * Description: -+ * This function will wake up pipe writers if necessary. It should -+ * be called after a loop containing splice_from_pipe_next() and -+ * splice_from_pipe_feed(). -+ */ -+void splice_from_pipe_end(struct pipe_inode_info *pipe, struct splice_desc *sd) -+{ -+ if (sd->need_wakeup) -+ wakeup_pipe_writers(pipe); -+} -+EXPORT_SYMBOL(splice_from_pipe_end); -+ -+/** -+ * __splice_from_pipe - splice data from a pipe to given actor -+ * @pipe: pipe to splice from -+ * @sd: information to @actor -+ * @actor: handler that splices the data -+ * -+ * Description: -+ * This function does little more than loop over the pipe and call -+ * @actor to do the actual moving of a single struct pipe_buffer to -+ * the desired destination. See pipe_to_file, pipe_to_sendpage, or -+ * pipe_to_user. -+ * -+ */ -+ssize_t __splice_from_pipe(struct pipe_inode_info *pipe, struct splice_desc *sd, -+ splice_actor *actor) -+{ -+ int ret; -+ -+ splice_from_pipe_begin(sd); -+ do { -+ ret = splice_from_pipe_next(pipe, sd); -+ if (ret > 0) -+ ret = splice_from_pipe_feed(pipe, sd, actor); -+ } while (ret > 0); -+ splice_from_pipe_end(pipe, sd); -+ -+ return sd->num_spliced ? sd->num_spliced : ret; -+} -+EXPORT_SYMBOL(__splice_from_pipe); -+ -+/** -+ * splice_from_pipe - splice data from a pipe to a file -+ * @pipe: pipe to splice from -+ * @out: file to splice to -+ * @ppos: position in @out -+ * @len: how many bytes to splice -+ * @flags: splice modifier flags -+ * @actor: handler that splices the data -+ * -+ * Description: -+ * See __splice_from_pipe. This function locks the pipe inode, -+ * otherwise it's identical to __splice_from_pipe(). -+ * -+ */ -+ssize_t splice_from_pipe(struct pipe_inode_info *pipe, struct file *out, -+ loff_t *ppos, size_t len, unsigned int flags, -+ splice_actor *actor) -+{ -+ ssize_t ret; -+ struct splice_desc sd = { -+ .total_len = len, -+ .flags = flags, -+ .pos = *ppos, -+ .u.file = out, -+ }; -+ -+ pipe_lock(pipe); -+ ret = __splice_from_pipe(pipe, &sd, actor); -+ pipe_unlock(pipe); -+ -+ return ret; -+} -+ -+/** -+ * generic_file_splice_write - splice data from a pipe to a file -+ * @pipe: pipe info -+ * @out: file to write to -+ * @ppos: position in @out -+ * @len: number of bytes to splice -+ * @flags: splice modifier flags -+ * -+ * Description: -+ * Will either move or copy pages (determined by @flags options) from -+ * the given pipe inode to the given file. -+ * -+ */ -+ssize_t -+generic_file_splice_write(struct pipe_inode_info *pipe, struct file *out, -+ loff_t *ppos, size_t len, unsigned int flags) -+{ -+ struct address_space *mapping = out->f_mapping; -+ struct inode *inode = mapping->host; -+ struct splice_desc sd = { -+ .total_len = len, -+ .flags = flags, -+ .pos = *ppos, -+ .u.file = out, -+ }; -+ ssize_t ret; -+ -+ pipe_lock(pipe); -+ -+ splice_from_pipe_begin(&sd); -+ do { -+ ret = splice_from_pipe_next(pipe, &sd); -+ if (ret <= 0) -+ break; -+ -+ mutex_lock_nested(&inode->i_mutex, I_MUTEX_CHILD); -+ ret = file_remove_suid(out); -+ if (!ret) { -+ file_update_time(out); -+ ret = splice_from_pipe_feed(pipe, &sd, pipe_to_file); -+ } -+ mutex_unlock(&inode->i_mutex); -+ } while (ret > 0); -+ splice_from_pipe_end(pipe, &sd); -+ -+ pipe_unlock(pipe); -+ -+ if (sd.num_spliced) -+ ret = sd.num_spliced; -+ -+ if (ret > 0) { -+ unsigned long nr_pages; -+ int err; -+ -+ nr_pages = (ret + PAGE_CACHE_SIZE - 1) >> PAGE_CACHE_SHIFT; -+ -+ err = generic_write_sync(out, *ppos, ret); -+ if (err) -+ ret = err; -+ else -+ *ppos += ret; -+ balance_dirty_pages_ratelimited_nr(mapping, nr_pages); -+ } -+ -+ return ret; -+} -+ -+EXPORT_SYMBOL(generic_file_splice_write); -+ -+static int write_pipe_buf(struct pipe_inode_info *pipe, struct pipe_buffer *buf, -+ struct splice_desc *sd) -+{ -+ int ret; -+ void *data; -+ -+ ret = buf->ops->confirm(pipe, buf); -+ if (ret) -+ return ret; -+ -+ data = buf->ops->map(pipe, buf, 0); -+ ret = kernel_write(sd->u.file, data + buf->offset, sd->len, sd->pos); -+ buf->ops->unmap(pipe, buf, data); -+ -+ return ret; -+} -+ -+static ssize_t default_file_splice_write(struct pipe_inode_info *pipe, -+ struct file *out, loff_t *ppos, -+ size_t len, unsigned int flags) -+{ -+ ssize_t ret; -+ -+ ret = splice_from_pipe(pipe, out, ppos, len, flags, write_pipe_buf); -+ if (ret > 0) -+ *ppos += ret; -+ -+ return ret; -+} -+ -+/** -+ * generic_splice_sendpage - splice data from a pipe to a socket -+ * @pipe: pipe to splice from -+ * @out: socket to write to -+ * @ppos: position in @out -+ * @len: number of bytes to splice -+ * @flags: splice modifier flags -+ * -+ * Description: -+ * Will send @len bytes from the pipe to a network socket. No data copying -+ * is involved. -+ * -+ */ -+ssize_t generic_splice_sendpage(struct pipe_inode_info *pipe, struct file *out, -+ loff_t *ppos, size_t len, unsigned int flags) -+{ -+ return splice_from_pipe(pipe, out, ppos, len, flags, pipe_to_sendpage); -+} -+ -+EXPORT_SYMBOL(generic_splice_sendpage); -+ -+/* -+ * Attempt to initiate a splice from pipe to file. -+ */ -+static long do_splice_from(struct pipe_inode_info *pipe, struct file *out, -+ loff_t *ppos, size_t len, unsigned int flags) -+{ -+ ssize_t (*splice_write)(struct pipe_inode_info *, struct file *, -+ loff_t *, size_t, unsigned int); -+ int ret; -+ -+ if (unlikely(!(out->f_mode & FMODE_WRITE))) -+ return -EBADF; -+ -+ if (unlikely(out->f_flags & O_APPEND)) -+ return -EINVAL; -+ -+ ret = rw_verify_area(WRITE, out, ppos, len); -+ if (unlikely(ret < 0)) -+ return ret; -+ -+ if (out->f_op && out->f_op->splice_write) -+ splice_write = out->f_op->splice_write; -+ else -+ splice_write = default_file_splice_write; -+ -+ return splice_write(pipe, out, ppos, len, flags); -+} -+EXPORT_SYMBOL(do_splice_from); -+ -+/* -+ * Attempt to initiate a splice from a file to a pipe. -+ */ -+static long do_splice_to(struct file *in, loff_t *ppos, -+ struct pipe_inode_info *pipe, size_t len, -+ unsigned int flags) -+{ -+ ssize_t (*splice_read)(struct file *, loff_t *, -+ struct pipe_inode_info *, size_t, unsigned int); -+ int ret; -+ -+ if (unlikely(!(in->f_mode & FMODE_READ))) -+ return -EBADF; -+ -+ ret = rw_verify_area(READ, in, ppos, len); -+ if (unlikely(ret < 0)) -+ return ret; -+ -+ if (in->f_op && in->f_op->splice_read) -+ splice_read = in->f_op->splice_read; -+ else -+ splice_read = default_file_splice_read; -+ -+ return splice_read(in, ppos, pipe, len, flags); -+} -+EXPORT_SYMBOL(do_splice_to); -+ -+/** -+ * splice_direct_to_actor - splices data directly between two non-pipes -+ * @in: file to splice from -+ * @sd: actor information on where to splice to -+ * @actor: handles the data splicing -+ * -+ * Description: -+ * This is a special case helper to splice directly between two -+ * points, without requiring an explicit pipe. Internally an allocated -+ * pipe is cached in the process, and reused during the lifetime of -+ * that process. -+ * -+ */ -+ssize_t splice_direct_to_actor(struct file *in, struct splice_desc *sd, -+ splice_direct_actor *actor) -+{ -+ struct pipe_inode_info *pipe; -+ long ret, bytes; -+ umode_t i_mode; -+ size_t len; -+ int i, flags; -+ -+ /* -+ * We require the input being a regular file, as we don't want to -+ * randomly drop data for eg socket -> socket splicing. Use the -+ * piped splicing for that! -+ */ -+ i_mode = in->f_path.dentry->d_inode->i_mode; -+ if (unlikely(!S_ISREG(i_mode) && !S_ISBLK(i_mode))) -+ return -EINVAL; -+ -+ /* -+ * neither in nor out is a pipe, setup an internal pipe attached to -+ * 'out' and transfer the wanted data from 'in' to 'out' through that -+ */ -+ pipe = current->splice_pipe; -+ if (unlikely(!pipe)) { -+ pipe = alloc_pipe_info(NULL); -+ if (!pipe) -+ return -ENOMEM; -+ -+ /* -+ * We don't have an immediate reader, but we'll read the stuff -+ * out of the pipe right after the splice_to_pipe(). So set -+ * PIPE_READERS appropriately. -+ */ -+ pipe->readers = 1; -+ -+ current->splice_pipe = pipe; -+ } -+ -+ /* -+ * Do the splice. -+ */ -+ ret = 0; -+ bytes = 0; -+ len = sd->total_len; -+ flags = sd->flags; -+ -+ /* -+ * Don't block on output, we have to drain the direct pipe. -+ */ -+ sd->flags &= ~SPLICE_F_NONBLOCK; -+ -+ while (len) { -+ size_t read_len; -+ loff_t pos = sd->pos, prev_pos = pos; -+ -+ ret = do_splice_to(in, &pos, pipe, len, flags); -+ if (unlikely(ret <= 0)) -+ goto out_release; -+ -+ read_len = ret; -+ sd->total_len = read_len; -+ -+ /* -+ * NOTE: nonblocking mode only applies to the input. We -+ * must not do the output in nonblocking mode as then we -+ * could get stuck data in the internal pipe: -+ */ -+ ret = actor(pipe, sd); -+ if (unlikely(ret <= 0)) { -+ sd->pos = prev_pos; -+ goto out_release; -+ } -+ -+ bytes += ret; -+ len -= ret; -+ sd->pos = pos; -+ -+ if (ret < read_len) { -+ sd->pos = prev_pos + ret; -+ goto out_release; -+ } -+ } -+ -+done: -+ pipe->nrbufs = pipe->curbuf = 0; -+ file_accessed(in); -+ return bytes; -+ -+out_release: -+ /* -+ * If we did an incomplete transfer we must release -+ * the pipe buffers in question: -+ */ -+ for (i = 0; i < pipe->buffers; i++) { -+ struct pipe_buffer *buf = pipe->bufs + i; -+ -+ if (buf->ops) { -+ buf->ops->release(pipe, buf); -+ buf->ops = NULL; -+ } -+ } -+ -+ if (!bytes) -+ bytes = ret; -+ -+ goto done; -+} -+EXPORT_SYMBOL(splice_direct_to_actor); -+ -+static int direct_splice_actor(struct pipe_inode_info *pipe, -+ struct splice_desc *sd) -+{ -+ struct file *file = sd->u.file; -+ -+ return do_splice_from(pipe, file, &file->f_pos, sd->total_len, -+ sd->flags); -+} -+ -+/** -+ * do_splice_direct - splices data directly between two files -+ * @in: file to splice from -+ * @ppos: input file offset -+ * @out: file to splice to -+ * @len: number of bytes to splice -+ * @flags: splice modifier flags -+ * -+ * Description: -+ * For use by do_sendfile(). splice can easily emulate sendfile, but -+ * doing it in the application would incur an extra system call -+ * (splice in + splice out, as compared to just sendfile()). So this helper -+ * can splice directly through a process-private pipe. -+ * -+ */ -+long do_splice_direct(struct file *in, loff_t *ppos, struct file *out, -+ size_t len, unsigned int flags) -+{ -+ struct splice_desc sd = { -+ .len = len, -+ .total_len = len, -+ .flags = flags, -+ .pos = *ppos, -+ .u.file = out, -+ }; -+ long ret; -+ -+ ret = splice_direct_to_actor(in, &sd, direct_splice_actor); -+ if (ret > 0) -+ *ppos = sd.pos; -+ -+ return ret; -+} -+ -+static int splice_pipe_to_pipe(struct pipe_inode_info *ipipe, -+ struct pipe_inode_info *opipe, -+ size_t len, unsigned int flags); -+/* -+ * After the inode slimming patch, i_pipe/i_bdev/i_cdev share the same -+ * location, so checking ->i_pipe is not enough to verify that this is a -+ * pipe. -+ */ -+static inline struct pipe_inode_info *pipe_info(struct inode *inode) -+{ -+ if (S_ISFIFO(inode->i_mode)) -+ return inode->i_pipe; -+ -+ return NULL; -+} -+ -+/* -+ * Determine where to splice to/from. -+ */ -+static long do_splice(struct file *in, loff_t __user *off_in, -+ struct file *out, loff_t __user *off_out, -+ size_t len, unsigned int flags) -+{ -+ struct pipe_inode_info *ipipe; -+ struct pipe_inode_info *opipe; -+ loff_t offset, *off; -+ long ret; -+ -+ ipipe = pipe_info(in->f_path.dentry->d_inode); -+ opipe = pipe_info(out->f_path.dentry->d_inode); -+ -+ if (ipipe && opipe) { -+ if (off_in || off_out) -+ return -ESPIPE; -+ -+ if (!(in->f_mode & FMODE_READ)) -+ return -EBADF; -+ -+ if (!(out->f_mode & FMODE_WRITE)) -+ return -EBADF; -+ -+ /* Splicing to self would be fun, but... */ -+ if (ipipe == opipe) -+ return -EINVAL; -+ -+ return splice_pipe_to_pipe(ipipe, opipe, len, flags); -+ } -+ -+ if (ipipe) { -+ if (off_in) -+ return -ESPIPE; -+ if (off_out) { -+ if (!(out->f_mode & FMODE_PWRITE)) -+ return -EINVAL; -+ if (copy_from_user(&offset, off_out, sizeof(loff_t))) -+ return -EFAULT; -+ off = &offset; -+ } else -+ off = &out->f_pos; -+ -+ ret = do_splice_from(ipipe, out, off, len, flags); -+ -+ if (off_out && copy_to_user(off_out, off, sizeof(loff_t))) -+ ret = -EFAULT; -+ -+ return ret; -+ } -+ -+ if (opipe) { -+ if (off_out) -+ return -ESPIPE; -+ if (off_in) { -+ if (!(in->f_mode & FMODE_PREAD)) -+ return -EINVAL; -+ if (copy_from_user(&offset, off_in, sizeof(loff_t))) -+ return -EFAULT; -+ off = &offset; -+ } else -+ off = &in->f_pos; -+ -+ ret = do_splice_to(in, off, opipe, len, flags); -+ -+ if (off_in && copy_to_user(off_in, off, sizeof(loff_t))) -+ ret = -EFAULT; -+ -+ return ret; -+ } -+ -+ return -EINVAL; -+} -+ -+/* -+ * Map an iov into an array of pages and offset/length tupples. With the -+ * partial_page structure, we can map several non-contiguous ranges into -+ * our ones pages[] map instead of splitting that operation into pieces. -+ * Could easily be exported as a generic helper for other users, in which -+ * case one would probably want to add a 'max_nr_pages' parameter as well. -+ */ -+static int get_iovec_page_array(const struct iovec __user *iov, -+ unsigned int nr_vecs, struct page **pages, -+ struct partial_page *partial, int aligned, -+ unsigned int pipe_buffers) -+{ -+ int buffers = 0, error = 0; -+ -+ while (nr_vecs) { -+ unsigned long off, npages; -+ struct iovec entry; -+ void __user *base; -+ size_t len; -+ int i; -+ -+ error = -EFAULT; -+ if (copy_from_user(&entry, iov, sizeof(entry))) -+ break; -+ -+ base = entry.iov_base; -+ len = entry.iov_len; -+ -+ /* -+ * Sanity check this iovec. 0 read succeeds. -+ */ -+ error = 0; -+ if (unlikely(!len)) -+ break; -+ error = -EFAULT; -+ if (!access_ok(VERIFY_READ, base, len)) -+ break; -+ -+ /* -+ * Get this base offset and number of pages, then map -+ * in the user pages. -+ */ -+ off = (unsigned long) base & ~PAGE_MASK; -+ -+ /* -+ * If asked for alignment, the offset must be zero and the -+ * length a multiple of the PAGE_SIZE. -+ */ -+ error = -EINVAL; -+ if (aligned && (off || len & ~PAGE_MASK)) -+ break; -+ -+ npages = (off + len + PAGE_SIZE - 1) >> PAGE_SHIFT; -+ if (npages > pipe_buffers - buffers) -+ npages = pipe_buffers - buffers; -+ -+ error = get_user_pages_fast((unsigned long)base, npages, -+ 0, &pages[buffers]); -+ -+ if (unlikely(error <= 0)) -+ break; -+ -+ /* -+ * Fill this contiguous range into the partial page map. -+ */ -+ for (i = 0; i < error; i++) { -+ const int plen = min_t(size_t, len, PAGE_SIZE - off); -+ -+ partial[buffers].offset = off; -+ partial[buffers].len = plen; -+ -+ off = 0; -+ len -= plen; -+ buffers++; -+ } -+ -+ /* -+ * We didn't complete this iov, stop here since it probably -+ * means we have to move some of this into a pipe to -+ * be able to continue. -+ */ -+ if (len) -+ break; -+ -+ /* -+ * Don't continue if we mapped fewer pages than we asked for, -+ * or if we mapped the max number of pages that we have -+ * room for. -+ */ -+ if (error < npages || buffers == pipe_buffers) -+ break; -+ -+ nr_vecs--; -+ iov++; -+ } -+ -+ if (buffers) -+ return buffers; -+ -+ return error; -+} -+ -+static int pipe_to_user(struct pipe_inode_info *pipe, struct pipe_buffer *buf, -+ struct splice_desc *sd) -+{ -+ char *src; -+ int ret; -+ -+ ret = buf->ops->confirm(pipe, buf); -+ if (unlikely(ret)) -+ return ret; -+ -+ /* -+ * See if we can use the atomic maps, by prefaulting in the -+ * pages and doing an atomic copy -+ */ -+ if (!fault_in_pages_writeable(sd->u.userptr, sd->len)) { -+ src = buf->ops->map(pipe, buf, 1); -+ ret = __copy_to_user_inatomic(sd->u.userptr, src + buf->offset, -+ sd->len); -+ buf->ops->unmap(pipe, buf, src); -+ if (!ret) { -+ ret = sd->len; -+ goto out; -+ } -+ } -+ -+ /* -+ * No dice, use slow non-atomic map and copy -+ */ -+ src = buf->ops->map(pipe, buf, 0); -+ -+ ret = sd->len; -+ if (copy_to_user(sd->u.userptr, src + buf->offset, sd->len)) -+ ret = -EFAULT; -+ -+ buf->ops->unmap(pipe, buf, src); -+out: -+ if (ret > 0) -+ sd->u.userptr += ret; -+ return ret; -+} -+ -+/* -+ * For lack of a better implementation, implement vmsplice() to userspace -+ * as a simple copy of the pipes pages to the user iov. -+ */ -+static long vmsplice_to_user(struct file *file, const struct iovec __user *iov, -+ unsigned long nr_segs, unsigned int flags) -+{ -+ struct pipe_inode_info *pipe; -+ struct splice_desc sd; -+ ssize_t size; -+ int error; -+ long ret; -+ -+ pipe = pipe_info(file->f_path.dentry->d_inode); -+ if (!pipe) -+ return -EBADF; -+ -+ pipe_lock(pipe); -+ -+ error = ret = 0; -+ while (nr_segs) { -+ void __user *base; -+ size_t len; -+ -+ /* -+ * Get user address base and length for this iovec. -+ */ -+ error = get_user(base, &iov->iov_base); -+ if (unlikely(error)) -+ break; -+ error = get_user(len, &iov->iov_len); -+ if (unlikely(error)) -+ break; -+ -+ /* -+ * Sanity check this iovec. 0 read succeeds. -+ */ -+ if (unlikely(!len)) -+ break; -+ if (unlikely(!base)) { -+ error = -EFAULT; -+ break; -+ } -+ -+ if (unlikely(!access_ok(VERIFY_WRITE, base, len))) { -+ error = -EFAULT; -+ break; -+ } -+ -+ sd.len = 0; -+ sd.total_len = len; -+ sd.flags = flags; -+ sd.u.userptr = base; -+ sd.pos = 0; -+ -+ size = __splice_from_pipe(pipe, &sd, pipe_to_user); -+ if (size < 0) { -+ if (!ret) -+ ret = size; -+ -+ break; -+ } -+ -+ ret += size; -+ -+ if (size < len) -+ break; -+ -+ nr_segs--; -+ iov++; -+ } -+ -+ pipe_unlock(pipe); -+ -+ if (!ret) -+ ret = error; -+ -+ return ret; -+} -+ -+/* -+ * vmsplice splices a user address range into a pipe. It can be thought of -+ * as splice-from-memory, where the regular splice is splice-from-file (or -+ * to file). In both cases the output is a pipe, naturally. -+ */ -+static long vmsplice_to_pipe(struct file *file, const struct iovec __user *iov, -+ unsigned long nr_segs, unsigned int flags) -+{ -+ struct pipe_inode_info *pipe; -+ struct page *pages[PIPE_DEF_BUFFERS]; -+ struct partial_page partial[PIPE_DEF_BUFFERS]; -+ struct splice_pipe_desc spd = { -+ .pages = pages, -+ .partial = partial, -+ .flags = flags, -+ .ops = &user_page_pipe_buf_ops, -+ .spd_release = spd_release_page, -+ }; -+ long ret; -+ -+ pipe = pipe_info(file->f_path.dentry->d_inode); -+ if (!pipe) -+ return -EBADF; -+ -+ if (splice_grow_spd(pipe, &spd)) -+ return -ENOMEM; -+ -+ spd.nr_pages = get_iovec_page_array(iov, nr_segs, spd.pages, -+ spd.partial, flags & SPLICE_F_GIFT, -+ pipe->buffers); -+ if (spd.nr_pages <= 0) -+ ret = spd.nr_pages; -+ else -+ ret = splice_to_pipe(pipe, &spd); -+ -+ splice_shrink_spd(pipe, &spd); -+ return ret; -+} -+ -+/* -+ * Note that vmsplice only really supports true splicing _from_ user memory -+ * to a pipe, not the other way around. Splicing from user memory is a simple -+ * operation that can be supported without any funky alignment restrictions -+ * or nasty vm tricks. We simply map in the user memory and fill them into -+ * a pipe. The reverse isn't quite as easy, though. There are two possible -+ * solutions for that: -+ * -+ * - memcpy() the data internally, at which point we might as well just -+ * do a regular read() on the buffer anyway. -+ * - Lots of nasty vm tricks, that are neither fast nor flexible (it -+ * has restriction limitations on both ends of the pipe). -+ * -+ * Currently we punt and implement it as a normal copy, see pipe_to_user(). -+ * -+ */ -+SYSCALL_DEFINE4(vmsplice, int, fd, const struct iovec __user *, iov, -+ unsigned long, nr_segs, unsigned int, flags) -+{ -+ struct file *file; -+ long error; -+ int fput; -+ -+ if (unlikely(nr_segs > UIO_MAXIOV)) -+ return -EINVAL; -+ else if (unlikely(!nr_segs)) -+ return 0; -+ -+ error = -EBADF; -+ file = fget_light(fd, &fput); -+ if (file) { -+ if (file->f_mode & FMODE_WRITE) -+ error = vmsplice_to_pipe(file, iov, nr_segs, flags); -+ else if (file->f_mode & FMODE_READ) -+ error = vmsplice_to_user(file, iov, nr_segs, flags); -+ -+ fput_light(file, fput); -+ } -+ -+ return error; -+} -+ -+SYSCALL_DEFINE6(splice, int, fd_in, loff_t __user *, off_in, -+ int, fd_out, loff_t __user *, off_out, -+ size_t, len, unsigned int, flags) -+{ -+ long error; -+ struct file *in, *out; -+ int fput_in, fput_out; -+ -+ if (unlikely(!len)) -+ return 0; -+ -+ error = -EBADF; -+ in = fget_light(fd_in, &fput_in); -+ if (in) { -+ if (in->f_mode & FMODE_READ) { -+ out = fget_light(fd_out, &fput_out); -+ if (out) { -+ if (out->f_mode & FMODE_WRITE) -+ error = do_splice(in, off_in, -+ out, off_out, -+ len, flags); -+ fput_light(out, fput_out); -+ } -+ } -+ -+ fput_light(in, fput_in); -+ } -+ -+ return error; -+} -+ -+/* -+ * Make sure there's data to read. Wait for input if we can, otherwise -+ * return an appropriate error. -+ */ -+static int ipipe_prep(struct pipe_inode_info *pipe, unsigned int flags) -+{ -+ int ret; -+ -+ /* -+ * Check ->nrbufs without the inode lock first. This function -+ * is speculative anyways, so missing one is ok. -+ */ -+ if (pipe->nrbufs) -+ return 0; -+ -+ ret = 0; -+ pipe_lock(pipe); -+ -+ while (!pipe->nrbufs) { -+ if (signal_pending(current)) { -+ ret = -ERESTARTSYS; -+ break; -+ } -+ if (!pipe->writers) -+ break; -+ if (!pipe->waiting_writers) { -+ if (flags & SPLICE_F_NONBLOCK) { -+ ret = -EAGAIN; -+ break; -+ } -+ } -+ pipe_wait(pipe); -+ } -+ -+ pipe_unlock(pipe); -+ return ret; -+} -+ -+/* -+ * Make sure there's writeable room. Wait for room if we can, otherwise -+ * return an appropriate error. -+ */ -+static int opipe_prep(struct pipe_inode_info *pipe, unsigned int flags) -+{ -+ int ret; -+ -+ /* -+ * Check ->nrbufs without the inode lock first. This function -+ * is speculative anyways, so missing one is ok. -+ */ -+ if (pipe->nrbufs < pipe->buffers) -+ return 0; -+ -+ ret = 0; -+ pipe_lock(pipe); -+ -+ while (pipe->nrbufs >= pipe->buffers) { -+ if (!pipe->readers) { -+ send_sig(SIGPIPE, current, 0); -+ ret = -EPIPE; -+ break; -+ } -+ if (flags & SPLICE_F_NONBLOCK) { -+ ret = -EAGAIN; -+ break; -+ } -+ if (signal_pending(current)) { -+ ret = -ERESTARTSYS; -+ break; -+ } -+ pipe->waiting_writers++; -+ pipe_wait(pipe); -+ pipe->waiting_writers--; -+ } -+ -+ pipe_unlock(pipe); -+ return ret; -+} -+ -+/* -+ * Splice contents of ipipe to opipe. -+ */ -+static int splice_pipe_to_pipe(struct pipe_inode_info *ipipe, -+ struct pipe_inode_info *opipe, -+ size_t len, unsigned int flags) -+{ -+ struct pipe_buffer *ibuf, *obuf; -+ int ret = 0, nbuf; -+ bool input_wakeup = false; -+ -+ -+retry: -+ ret = ipipe_prep(ipipe, flags); -+ if (ret) -+ return ret; -+ -+ ret = opipe_prep(opipe, flags); -+ if (ret) -+ return ret; -+ -+ /* -+ * Potential ABBA deadlock, work around it by ordering lock -+ * grabbing by pipe info address. Otherwise two different processes -+ * could deadlock (one doing tee from A -> B, the other from B -> A). -+ */ -+ pipe_double_lock(ipipe, opipe); -+ -+ do { -+ if (!opipe->readers) { -+ send_sig(SIGPIPE, current, 0); -+ if (!ret) -+ ret = -EPIPE; -+ break; -+ } -+ -+ if (!ipipe->nrbufs && !ipipe->writers) -+ break; -+ -+ /* -+ * Cannot make any progress, because either the input -+ * pipe is empty or the output pipe is full. -+ */ -+ if (!ipipe->nrbufs || opipe->nrbufs >= opipe->buffers) { -+ /* Already processed some buffers, break */ -+ if (ret) -+ break; -+ -+ if (flags & SPLICE_F_NONBLOCK) { -+ ret = -EAGAIN; -+ break; -+ } -+ -+ /* -+ * We raced with another reader/writer and haven't -+ * managed to process any buffers. A zero return -+ * value means EOF, so retry instead. -+ */ -+ pipe_unlock(ipipe); -+ pipe_unlock(opipe); -+ goto retry; -+ } -+ -+ ibuf = ipipe->bufs + ipipe->curbuf; -+ nbuf = (opipe->curbuf + opipe->nrbufs) & (opipe->buffers - 1); -+ obuf = opipe->bufs + nbuf; -+ -+ if (len >= ibuf->len) { -+ /* -+ * Simply move the whole buffer from ipipe to opipe -+ */ -+ *obuf = *ibuf; -+ ibuf->ops = NULL; -+ opipe->nrbufs++; -+ ipipe->curbuf = (ipipe->curbuf + 1) & (ipipe->buffers - 1); -+ ipipe->nrbufs--; -+ input_wakeup = true; -+ } else { -+ /* -+ * Get a reference to this pipe buffer, -+ * so we can copy the contents over. -+ */ -+ ibuf->ops->get(ipipe, ibuf); -+ *obuf = *ibuf; -+ -+ /* -+ * Don't inherit the gift flag, we need to -+ * prevent multiple steals of this page. -+ */ -+ obuf->flags &= ~PIPE_BUF_FLAG_GIFT; -+ -+ obuf->len = len; -+ opipe->nrbufs++; -+ ibuf->offset += obuf->len; -+ ibuf->len -= obuf->len; -+ } -+ ret += obuf->len; -+ len -= obuf->len; -+ } while (len); -+ -+ pipe_unlock(ipipe); -+ pipe_unlock(opipe); -+ -+ /* -+ * If we put data in the output pipe, wakeup any potential readers. -+ */ -+ if (ret > 0) { -+ smp_mb(); -+ if (waitqueue_active(&opipe->wait)) -+ wake_up_interruptible(&opipe->wait); -+ kill_fasync(&opipe->fasync_readers, SIGIO, POLL_IN); -+ } -+ if (input_wakeup) -+ wakeup_pipe_writers(ipipe); -+ -+ return ret; -+} -+ -+/* -+ * Link contents of ipipe to opipe. -+ */ -+static int link_pipe(struct pipe_inode_info *ipipe, -+ struct pipe_inode_info *opipe, -+ size_t len, unsigned int flags) -+{ -+ struct pipe_buffer *ibuf, *obuf; -+ int ret = 0, i = 0, nbuf; -+ -+ /* -+ * Potential ABBA deadlock, work around it by ordering lock -+ * grabbing by pipe info address. Otherwise two different processes -+ * could deadlock (one doing tee from A -> B, the other from B -> A). -+ */ -+ pipe_double_lock(ipipe, opipe); -+ -+ do { -+ if (!opipe->readers) { -+ send_sig(SIGPIPE, current, 0); -+ if (!ret) -+ ret = -EPIPE; -+ break; -+ } -+ -+ /* -+ * If we have iterated all input buffers or ran out of -+ * output room, break. -+ */ -+ if (i >= ipipe->nrbufs || opipe->nrbufs >= opipe->buffers) -+ break; -+ -+ ibuf = ipipe->bufs + ((ipipe->curbuf + i) & (ipipe->buffers-1)); -+ nbuf = (opipe->curbuf + opipe->nrbufs) & (opipe->buffers - 1); -+ -+ /* -+ * Get a reference to this pipe buffer, -+ * so we can copy the contents over. -+ */ -+ ibuf->ops->get(ipipe, ibuf); -+ -+ obuf = opipe->bufs + nbuf; -+ *obuf = *ibuf; -+ -+ /* -+ * Don't inherit the gift flag, we need to -+ * prevent multiple steals of this page. -+ */ -+ obuf->flags &= ~PIPE_BUF_FLAG_GIFT; -+ -+ if (obuf->len > len) -+ obuf->len = len; -+ -+ opipe->nrbufs++; -+ ret += obuf->len; -+ len -= obuf->len; -+ i++; -+ } while (len); -+ -+ /* -+ * return EAGAIN if we have the potential of some data in the -+ * future, otherwise just return 0 -+ */ -+ if (!ret && ipipe->waiting_writers && (flags & SPLICE_F_NONBLOCK)) -+ ret = -EAGAIN; -+ -+ pipe_unlock(ipipe); -+ pipe_unlock(opipe); -+ -+ /* -+ * If we put data in the output pipe, wakeup any potential readers. -+ */ -+ if (ret > 0) { -+ smp_mb(); -+ if (waitqueue_active(&opipe->wait)) -+ wake_up_interruptible(&opipe->wait); -+ kill_fasync(&opipe->fasync_readers, SIGIO, POLL_IN); -+ } -+ -+ return ret; -+} -+ -+/* -+ * This is a tee(1) implementation that works on pipes. It doesn't copy -+ * any data, it simply references the 'in' pages on the 'out' pipe. -+ * The 'flags' used are the SPLICE_F_* variants, currently the only -+ * applicable one is SPLICE_F_NONBLOCK. -+ */ -+static long do_tee(struct file *in, struct file *out, size_t len, -+ unsigned int flags) -+{ -+ struct pipe_inode_info *ipipe = pipe_info(in->f_path.dentry->d_inode); -+ struct pipe_inode_info *opipe = pipe_info(out->f_path.dentry->d_inode); -+ int ret = -EINVAL; -+ -+ /* -+ * Duplicate the contents of ipipe to opipe without actually -+ * copying the data. -+ */ -+ if (ipipe && opipe && ipipe != opipe) { -+ /* -+ * Keep going, unless we encounter an error. The ipipe/opipe -+ * ordering doesn't really matter. -+ */ -+ ret = ipipe_prep(ipipe, flags); -+ if (!ret) { -+ ret = opipe_prep(opipe, flags); -+ if (!ret) -+ ret = link_pipe(ipipe, opipe, len, flags); -+ } -+ } -+ -+ return ret; -+} -+ -+SYSCALL_DEFINE4(tee, int, fdin, int, fdout, size_t, len, unsigned int, flags) -+{ -+ struct file *in; -+ int error, fput_in; -+ -+ if (unlikely(!len)) -+ return 0; -+ -+ error = -EBADF; -+ in = fget_light(fdin, &fput_in); -+ if (in) { -+ if (in->f_mode & FMODE_READ) { -+ int fput_out; -+ struct file *out = fget_light(fdout, &fput_out); -+ -+ if (out) { -+ if (out->f_mode & FMODE_WRITE) -+ error = do_tee(in, out, len, flags); -+ fput_light(out, fput_out); -+ } -+ } -+ fput_light(in, fput_in); -+ } -+ -+ return error; -+} -diff -Nur linux-2.6.36.orig/security/commoncap.c linux-2.6.36/security/commoncap.c ---- linux-2.6.36.orig/security/commoncap.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/security/commoncap.c 2011-01-10 19:52:38.000000000 +0100 -@@ -951,3 +951,4 @@ - } - return ret; - } -+EXPORT_SYMBOL(cap_file_mmap); -diff -Nur linux-2.6.36.orig/security/device_cgroup.c linux-2.6.36/security/device_cgroup.c ---- linux-2.6.36.orig/security/device_cgroup.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/security/device_cgroup.c 2011-01-10 19:52:38.000000000 +0100 -@@ -515,6 +515,7 @@ - - return -EPERM; - } -+EXPORT_SYMBOL(devcgroup_inode_permission); - - int devcgroup_inode_mknod(int mode, dev_t dev) - { -diff -Nur linux-2.6.36.orig/security/security.c linux-2.6.36/security/security.c ---- linux-2.6.36.orig/security/security.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/security/security.c 2011-01-10 19:52:38.000000000 +0100 -@@ -376,6 +376,7 @@ - return 0; - return security_ops->path_mkdir(dir, dentry, mode); - } -+EXPORT_SYMBOL(security_path_mkdir); - - int security_path_rmdir(struct path *dir, struct dentry *dentry) - { -@@ -383,6 +384,7 @@ - return 0; - return security_ops->path_rmdir(dir, dentry); - } -+EXPORT_SYMBOL(security_path_rmdir); - - int security_path_unlink(struct path *dir, struct dentry *dentry) - { -@@ -390,6 +392,7 @@ - return 0; - return security_ops->path_unlink(dir, dentry); - } -+EXPORT_SYMBOL(security_path_unlink); - - int security_path_symlink(struct path *dir, struct dentry *dentry, - const char *old_name) -@@ -398,6 +401,7 @@ - return 0; - return security_ops->path_symlink(dir, dentry, old_name); - } -+EXPORT_SYMBOL(security_path_symlink); - - int security_path_link(struct dentry *old_dentry, struct path *new_dir, - struct dentry *new_dentry) -@@ -406,6 +410,7 @@ - return 0; - return security_ops->path_link(old_dentry, new_dir, new_dentry); - } -+EXPORT_SYMBOL(security_path_link); - - int security_path_rename(struct path *old_dir, struct dentry *old_dentry, - struct path *new_dir, struct dentry *new_dentry) -@@ -416,6 +421,7 @@ - return security_ops->path_rename(old_dir, old_dentry, new_dir, - new_dentry); - } -+EXPORT_SYMBOL(security_path_rename); - - int security_path_truncate(struct path *path) - { -@@ -423,6 +429,7 @@ - return 0; - return security_ops->path_truncate(path); - } -+EXPORT_SYMBOL(security_path_truncate); - - int security_path_chmod(struct dentry *dentry, struct vfsmount *mnt, - mode_t mode) -@@ -431,6 +438,7 @@ - return 0; - return security_ops->path_chmod(dentry, mnt, mode); - } -+EXPORT_SYMBOL(security_path_chmod); - - int security_path_chown(struct path *path, uid_t uid, gid_t gid) - { -@@ -438,6 +446,7 @@ - return 0; - return security_ops->path_chown(path, uid, gid); - } -+EXPORT_SYMBOL(security_path_chown); - - int security_path_chroot(struct path *path) - { -@@ -514,6 +523,7 @@ - return 0; - return security_ops->inode_readlink(dentry); - } -+EXPORT_SYMBOL(security_inode_readlink); - - int security_inode_follow_link(struct dentry *dentry, struct nameidata *nd) - { -@@ -528,6 +538,7 @@ - return 0; - return security_ops->inode_permission(inode, mask); - } -+EXPORT_SYMBOL(security_inode_permission); - - int security_inode_setattr(struct dentry *dentry, struct iattr *attr) - { -@@ -627,6 +638,7 @@ - - return fsnotify_perm(file, mask); - } -+EXPORT_SYMBOL(security_file_permission); - - int security_file_alloc(struct file *file) - { -@@ -654,6 +666,7 @@ - return ret; - return ima_file_mmap(file, prot); - } -+EXPORT_SYMBOL(security_file_mmap); - - int security_file_mprotect(struct vm_area_struct *vma, unsigned long reqprot, - unsigned long prot) diff --git a/target/linux/patches/2.6.36/brcm.patch b/target/linux/patches/2.6.36/brcm.patch deleted file mode 100644 index 10a9a4947..000000000 --- a/target/linux/patches/2.6.36/brcm.patch +++ /dev/null @@ -1,169 +0,0 @@ ---- linux-2.6.36.orig/arch/mips/bcm47xx/Makefile 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/arch/mips/bcm47xx/Makefile 2010-12-22 16:39:15.000000000 +0100 -@@ -3,4 +3,4 @@ - # under Linux. - # - --obj-y := gpio.o irq.o nvram.o prom.o serial.o setup.o time.o wgt634u.o -+obj-y := gpio.o irq.o nvram.o prom.o serial.o setup.o time.o platform.o ---- /dev/null Fri Jan 7 17:21:57 2011 -+++ linux-2.6.36/arch/mips/bcm47xx/platform.c Fri Jan 7 17:21:42 2011 -@@ -0,0 +1,147 @@ -+/* -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 2010, 2011 Waldemar Brodkorb -+ * Copyright © 2007, 2011 Thorsten Glaser -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#define NVRAM_FLASH_SIZE 0x10000 -+#define CFGFS_FLASH_SIZE (64 * 1024) -+ -+static struct mtd_partition bcm47xx_partitions[] = { -+#define SLOT_CFE 0 -+ { -+ .name = "cfe", -+ .offset = 0, -+ .size = 0x40000, /* 256k */ -+ .mask_flags = MTD_WRITEABLE /* force read-only */ -+ }, -+#define SLOT_LINUX 1 -+ { -+ .name = "linux", -+ .offset = 0, -+ .size = 0, -+ }, -+#define SLOT_ROOTFS 2 -+ { -+ .name = "rootfs", -+ .offset = 0, -+ .size = 0, -+ }, -+#define SLOT_CFGFS 3 -+ { -+ .name = "cfgfs", -+ .offset = 0, -+ .size = 0, -+ }, -+#define SLOT_NVRAM 4 -+ { -+ .name = "nvram", -+ .offset = 0, -+ .size = 0, -+ }, -+}; -+ -+static struct physmap_flash_data bcm47xx_flash_data = { -+ .parts = bcm47xx_partitions, -+ .nr_parts = ARRAY_SIZE(bcm47xx_partitions) -+}; -+ -+static struct resource bcm47xx_flash_resource = { -+ .flags = IORESOURCE_MEM, -+}; -+ -+static struct platform_device bcm47xx_flash = { -+ .name = "physmap-flash", -+ .id = 0, -+ .dev = { .platform_data = &bcm47xx_flash_data, }, -+ .resource = &bcm47xx_flash_resource, -+ .num_resources = 1, -+}; -+ -+static struct platform_device *bcm47xx_devices[] __initdata = { -+ &bcm47xx_flash, -+}; -+ -+struct bcm47xx_trx_header { -+#define BCM47XX_TRX_MAGIC 0x30524448 -+ u32 magic; -+ u32 len; -+ u32 crc32; -+ u32 flag_version; -+ u32 offsets[3]; -+}; -+ -+#define UPTODOWN(slot, psize) do { \ -+ posn -= psize; left -= psize; \ -+ bcm47xx_partitions[slot].offset = posn; \ -+ bcm47xx_partitions[slot].size = psize; \ -+} while (/* CONSTCOND */ 0) -+ -+static int __init bcm47xx_register_devices(void) -+{ -+ u32 flash_size; -+ size_t left, posn; -+ struct ssb_mipscore *mcore = &ssb_bcm47xx.mipscore; -+ struct bcm47xx_trx_header *trx_hdr; -+ -+ trx_hdr = (void *)KSEG1ADDR(mcore->flash_window + 0x40000); -+ -+ /* devices might have 2, 4 or 8 MB flash size */ -+#ifdef BCM47XX_OVERRIDE_FLASHSIZE -+ flash_size = BCM47XX_OVERRIDE_FLASHSIZE; -+ mcore->flash_window_size = flash_size; -+#define BCM47XX_OVERRODE_FLASHSIZE " (overridden)" -+#else -+ flash_size = mcore->flash_window_size; -+#define BCM47XX_OVERRODE_FLASHSIZE "" -+#endif -+ printk(KERN_INFO "FLASH SIZE%s: %x\n", BCM47XX_OVERRODE_FLASHSIZE, -+ flash_size); -+ -+ left = flash_size - 0x40000; -+ posn = flash_size; -+ UPTODOWN(SLOT_NVRAM, NVRAM_FLASH_SIZE); -+ UPTODOWN(SLOT_CFGFS, CFGFS_FLASH_SIZE); -+ bcm47xx_partitions[SLOT_LINUX].offset = 0x40000; -+ bcm47xx_partitions[SLOT_LINUX].size = left; -+ -+ if (trx_hdr->magic == BCM47XX_TRX_MAGIC) { -+ bcm47xx_partitions[SLOT_ROOTFS].offset = -+ bcm47xx_partitions[SLOT_LINUX].offset + -+ trx_hdr->offsets[1]; -+ bcm47xx_partitions[SLOT_ROOTFS].size = -+ bcm47xx_partitions[SLOT_LINUX].size - -+ trx_hdr->offsets[1]; -+ } else -+ printk("bcm47xx/platform: no TRX header found\n"); -+ -+ printk(KERN_INFO "=== Flash map dump ===\n"); -+ for (posn = 0; posn < bcm47xx_flash_data.nr_parts; ++posn) -+ printk(KERN_INFO " #%u %08X @%08X '%s'\n", -+ (unsigned int)posn, -+ (unsigned int)bcm47xx_partitions[posn].size, -+ (unsigned int)bcm47xx_partitions[posn].offset, -+ bcm47xx_partitions[posn].name); -+ printk(KERN_INFO "=== Hope this works, have a nice day\n"); -+ -+ bcm47xx_flash_data.width = mcore->flash_buswidth; -+ bcm47xx_flash_resource.start = mcore->flash_window; -+ bcm47xx_flash_resource.end = mcore->flash_window -+ + mcore->flash_window_size -+ - 1; -+ return platform_add_devices(bcm47xx_devices, -+ ARRAY_SIZE(bcm47xx_devices)); -+} -+ -+device_initcall(bcm47xx_register_devices); ---- linux-2.6.36.orig/drivers/ssb/driver_mipscore.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/drivers/ssb/driver_mipscore.c 2010-12-22 16:38:53.000000000 +0100 -@@ -193,7 +193,7 @@ - mcore->flash_buswidth = 2; - if (bus->chipco.dev) { - mcore->flash_window = 0x1c000000; -- mcore->flash_window_size = 0x02000000; -+ mcore->flash_window_size = 0x00800000; - if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG) - & SSB_CHIPCO_CFG_DS16) == 0) - mcore->flash_buswidth = 1; diff --git a/target/linux/patches/2.6.36/bsd-compatibility.patch b/target/linux/patches/2.6.36/bsd-compatibility.patch deleted file mode 100644 index 9e91a62de..000000000 --- a/target/linux/patches/2.6.36/bsd-compatibility.patch +++ /dev/null @@ -1,2512 +0,0 @@ -diff -Nur linux-2.6.36.orig/scripts/Makefile.lib linux-2.6.36/scripts/Makefile.lib ---- linux-2.6.36.orig/scripts/Makefile.lib 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/scripts/Makefile.lib 2010-11-28 18:34:22.000000000 +0100 -@@ -216,7 +216,12 @@ - size_append = printf $(shell \ - dec_size=0; \ - for F in $1; do \ -- fsize=$$(stat -c "%s" $$F); \ -+ if stat -qs .>/dev/null 2>&1; then \ -+ statcmd='stat -f %z'; \ -+ else \ -+ statcmd='stat -c %s'; \ -+ fi; \ -+ fsize=$$($$statcmd $$F); \ - dec_size=$$(expr $$dec_size + $$fsize); \ - done; \ - printf "%08x\n" $$dec_size | \ -diff -Nur linux-2.6.36.orig/scripts/mod/mk_elfconfig.c linux-2.6.36/scripts/mod/mk_elfconfig.c ---- linux-2.6.36.orig/scripts/mod/mk_elfconfig.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/scripts/mod/mk_elfconfig.c 2010-11-28 18:33:24.000000000 +0100 -@@ -1,7 +1,18 @@ - #include - #include - #include --#include -+ -+#define EI_NIDENT (16) -+#define ELFMAG "\177ELF" -+ -+#define SELFMAG 4 -+#define EI_CLASS 4 -+#define ELFCLASS32 1 /* 32-bit objects */ -+#define ELFCLASS64 2 /* 64-bit objects */ -+ -+#define EI_DATA 5 /* Data encoding byte index */ -+#define ELFDATA2LSB 1 /* 2's complement, little endian */ -+#define ELFDATA2MSB 2 /* 2's complement, big endian */ - - int - main(int argc, char **argv) -diff -Nur linux-2.6.36.orig/scripts/mod/modpost.h linux-2.6.36/scripts/mod/modpost.h ---- linux-2.6.36.orig/scripts/mod/modpost.h 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/scripts/mod/modpost.h 2010-11-28 18:33:24.000000000 +0100 -@@ -7,7 +7,2453 @@ - #include - #include - #include --#include -+ -+ -+/* This file defines standard ELF types, structures, and macros. -+ Copyright (C) 1995-1999,2000,2001,2002,2003 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#ifndef _ELF_H -+#define _ELF_H 1 -+ -+__BEGIN_DECLS -+ -+/* Standard ELF types. */ -+ -+#include -+ -+/* Type for a 16-bit quantity. */ -+typedef uint16_t Elf32_Half; -+typedef uint16_t Elf64_Half; -+ -+/* Types for signed and unsigned 32-bit quantities. */ -+typedef uint32_t Elf32_Word; -+typedef int32_t Elf32_Sword; -+typedef uint32_t Elf64_Word; -+typedef int32_t Elf64_Sword; -+ -+/* Types for signed and unsigned 64-bit quantities. */ -+typedef uint64_t Elf32_Xword; -+typedef int64_t Elf32_Sxword; -+typedef uint64_t Elf64_Xword; -+typedef int64_t Elf64_Sxword; -+ -+/* Type of addresses. */ -+typedef uint32_t Elf32_Addr; -+typedef uint64_t Elf64_Addr; -+ -+/* Type of file offsets. */ -+typedef uint32_t Elf32_Off; -+typedef uint64_t Elf64_Off; -+ -+/* Type for section indices, which are 16-bit quantities. */ -+typedef uint16_t Elf32_Section; -+typedef uint16_t Elf64_Section; -+ -+/* Type for version symbol information. */ -+typedef Elf32_Half Elf32_Versym; -+typedef Elf64_Half Elf64_Versym; -+ -+ -+/* The ELF file header. This appears at the start of every ELF file. */ -+ -+#define EI_NIDENT (16) -+ -+typedef struct -+{ -+ unsigned char e_ident[EI_NIDENT]; /* Magic number and other info */ -+ Elf32_Half e_type; /* Object file type */ -+ Elf32_Half e_machine; /* Architecture */ -+ Elf32_Word e_version; /* Object file version */ -+ Elf32_Addr e_entry; /* Entry point virtual address */ -+ Elf32_Off e_phoff; /* Program header table file offset */ -+ Elf32_Off e_shoff; /* Section header table file offset */ -+ Elf32_Word e_flags; /* Processor-specific flags */ -+ Elf32_Half e_ehsize; /* ELF header size in bytes */ -+ Elf32_Half e_phentsize; /* Program header table entry size */ -+ Elf32_Half e_phnum; /* Program header table entry count */ -+ Elf32_Half e_shentsize; /* Section header table entry size */ -+ Elf32_Half e_shnum; /* Section header table entry count */ -+ Elf32_Half e_shstrndx; /* Section header string table index */ -+} Elf32_Ehdr; -+ -+typedef struct -+{ -+ unsigned char e_ident[EI_NIDENT]; /* Magic number and other info */ -+ Elf64_Half e_type; /* Object file type */ -+ Elf64_Half e_machine; /* Architecture */ -+ Elf64_Word e_version; /* Object file version */ -+ Elf64_Addr e_entry; /* Entry point virtual address */ -+ Elf64_Off e_phoff; /* Program header table file offset */ -+ Elf64_Off e_shoff; /* Section header table file offset */ -+ Elf64_Word e_flags; /* Processor-specific flags */ -+ Elf64_Half e_ehsize; /* ELF header size in bytes */ -+ Elf64_Half e_phentsize; /* Program header table entry size */ -+ Elf64_Half e_phnum; /* Program header table entry count */ -+ Elf64_Half e_shentsize; /* Section header table entry size */ -+ Elf64_Half e_shnum; /* Section header table entry count */ -+ Elf64_Half e_shstrndx; /* Section header string table index */ -+} Elf64_Ehdr; -+ -+/* Fields in the e_ident array. The EI_* macros are indices into the -+ array. The macros under each EI_* macro are the values the byte -+ may have. */ -+ -+#define EI_MAG0 0 /* File identification byte 0 index */ -+#define ELFMAG0 0x7f /* Magic number byte 0 */ -+ -+#define EI_MAG1 1 /* File identification byte 1 index */ -+#define ELFMAG1 'E' /* Magic number byte 1 */ -+ -+#define EI_MAG2 2 /* File identification byte 2 index */ -+#define ELFMAG2 'L' /* Magic number byte 2 */ -+ -+#define EI_MAG3 3 /* File identification byte 3 index */ -+#define ELFMAG3 'F' /* Magic number byte 3 */ -+ -+/* Conglomeration of the identification bytes, for easy testing as a word. */ -+#define ELFMAG "\177ELF" -+#define SELFMAG 4 -+ -+#define EI_CLASS 4 /* File class byte index */ -+#define ELFCLASSNONE 0 /* Invalid class */ -+#define ELFCLASS32 1 /* 32-bit objects */ -+#define ELFCLASS64 2 /* 64-bit objects */ -+#define ELFCLASSNUM 3 -+ -+#define EI_DATA 5 /* Data encoding byte index */ -+#define ELFDATANONE 0 /* Invalid data encoding */ -+#define ELFDATA2LSB 1 /* 2's complement, little endian */ -+#define ELFDATA2MSB 2 /* 2's complement, big endian */ -+#define ELFDATANUM 3 -+ -+#define EI_VERSION 6 /* File version byte index */ -+ /* Value must be EV_CURRENT */ -+ -+#define EI_OSABI 7 /* OS ABI identification */ -+#define ELFOSABI_NONE 0 /* UNIX System V ABI */ -+#define ELFOSABI_SYSV 0 /* Alias. */ -+#define ELFOSABI_HPUX 1 /* HP-UX */ -+#define ELFOSABI_NETBSD 2 /* NetBSD. */ -+#define ELFOSABI_LINUX 3 /* Linux. */ -+#define ELFOSABI_SOLARIS 6 /* Sun Solaris. */ -+#define ELFOSABI_AIX 7 /* IBM AIX. */ -+#define ELFOSABI_IRIX 8 /* SGI Irix. */ -+#define ELFOSABI_FREEBSD 9 /* FreeBSD. */ -+#define ELFOSABI_TRU64 10 /* Compaq TRU64 UNIX. */ -+#define ELFOSABI_MODESTO 11 /* Novell Modesto. */ -+#define ELFOSABI_OPENBSD 12 /* OpenBSD. */ -+#define ELFOSABI_ARM 97 /* ARM */ -+#define ELFOSABI_STANDALONE 255 /* Standalone (embedded) application */ -+ -+#define EI_ABIVERSION 8 /* ABI version */ -+ -+#define EI_PAD 9 /* Byte index of padding bytes */ -+ -+/* Legal values for e_type (object file type). */ -+ -+#define ET_NONE 0 /* No file type */ -+#define ET_REL 1 /* Relocatable file */ -+#define ET_EXEC 2 /* Executable file */ -+#define ET_DYN 3 /* Shared object file */ -+#define ET_CORE 4 /* Core file */ -+#define ET_NUM 5 /* Number of defined types */ -+#define ET_LOOS 0xfe00 /* OS-specific range start */ -+#define ET_HIOS 0xfeff /* OS-specific range end */ -+#define ET_LOPROC 0xff00 /* Processor-specific range start */ -+#define ET_HIPROC 0xffff /* Processor-specific range end */ -+ -+/* Legal values for e_machine (architecture). */ -+ -+#define EM_NONE 0 /* No machine */ -+#define EM_M32 1 /* AT&T WE 32100 */ -+#define EM_SPARC 2 /* SUN SPARC */ -+#define EM_386 3 /* Intel 80386 */ -+#define EM_68K 4 /* Motorola m68k family */ -+#define EM_88K 5 /* Motorola m88k family */ -+#define EM_860 7 /* Intel 80860 */ -+#define EM_MIPS 8 /* MIPS R3000 big-endian */ -+#define EM_S370 9 /* IBM System/370 */ -+#define EM_MIPS_RS3_LE 10 /* MIPS R3000 little-endian */ -+ -+#define EM_PARISC 15 /* HPPA */ -+#define EM_VPP500 17 /* Fujitsu VPP500 */ -+#define EM_SPARC32PLUS 18 /* Sun's "v8plus" */ -+#define EM_960 19 /* Intel 80960 */ -+#define EM_PPC 20 /* PowerPC */ -+#define EM_PPC64 21 /* PowerPC 64-bit */ -+#define EM_S390 22 /* IBM S390 */ -+ -+#define EM_V800 36 /* NEC V800 series */ -+#define EM_FR20 37 /* Fujitsu FR20 */ -+#define EM_RH32 38 /* TRW RH-32 */ -+#define EM_RCE 39 /* Motorola RCE */ -+#define EM_ARM 40 /* ARM */ -+#define EM_FAKE_ALPHA 41 /* Digital Alpha */ -+#define EM_SH 42 /* Hitachi SH */ -+#define EM_SPARCV9 43 /* SPARC v9 64-bit */ -+#define EM_TRICORE 44 /* Siemens Tricore */ -+#define EM_ARC 45 /* Argonaut RISC Core */ -+#define EM_H8_300 46 /* Hitachi H8/300 */ -+#define EM_H8_300H 47 /* Hitachi H8/300H */ -+#define EM_H8S 48 /* Hitachi H8S */ -+#define EM_H8_500 49 /* Hitachi H8/500 */ -+#define EM_IA_64 50 /* Intel Merced */ -+#define EM_MIPS_X 51 /* Stanford MIPS-X */ -+#define EM_COLDFIRE 52 /* Motorola Coldfire */ -+#define EM_68HC12 53 /* Motorola M68HC12 */ -+#define EM_MMA 54 /* Fujitsu MMA Multimedia Accelerator*/ -+#define EM_PCP 55 /* Siemens PCP */ -+#define EM_NCPU 56 /* Sony nCPU embeeded RISC */ -+#define EM_NDR1 57 /* Denso NDR1 microprocessor */ -+#define EM_STARCORE 58 /* Motorola Start*Core processor */ -+#define EM_ME16 59 /* Toyota ME16 processor */ -+#define EM_ST100 60 /* STMicroelectronic ST100 processor */ -+#define EM_TINYJ 61 /* Advanced Logic Corp. Tinyj emb.fam*/ -+#define EM_X86_64 62 /* AMD x86-64 architecture */ -+#define EM_PDSP 63 /* Sony DSP Processor */ -+ -+#define EM_FX66 66 /* Siemens FX66 microcontroller */ -+#define EM_ST9PLUS 67 /* STMicroelectronics ST9+ 8/16 mc */ -+#define EM_ST7 68 /* STmicroelectronics ST7 8 bit mc */ -+#define EM_68HC16 69 /* Motorola MC68HC16 microcontroller */ -+#define EM_68HC11 70 /* Motorola MC68HC11 microcontroller */ -+#define EM_68HC08 71 /* Motorola MC68HC08 microcontroller */ -+#define EM_68HC05 72 /* Motorola MC68HC05 microcontroller */ -+#define EM_SVX 73 /* Silicon Graphics SVx */ -+#define EM_ST19 74 /* STMicroelectronics ST19 8 bit mc */ -+#define EM_VAX 75 /* Digital VAX */ -+#define EM_CRIS 76 /* Axis Communications 32-bit embedded processor */ -+#define EM_JAVELIN 77 /* Infineon Technologies 32-bit embedded processor */ -+#define EM_FIREPATH 78 /* Element 14 64-bit DSP Processor */ -+#define EM_ZSP 79 /* LSI Logic 16-bit DSP Processor */ -+#define EM_MMIX 80 /* Donald Knuth's educational 64-bit processor */ -+#define EM_HUANY 81 /* Harvard University machine-independent object files */ -+#define EM_PRISM 82 /* SiTera Prism */ -+#define EM_AVR 83 /* Atmel AVR 8-bit microcontroller */ -+#define EM_FR30 84 /* Fujitsu FR30 */ -+#define EM_D10V 85 /* Mitsubishi D10V */ -+#define EM_D30V 86 /* Mitsubishi D30V */ -+#define EM_V850 87 /* NEC v850 */ -+#define EM_M32R 88 /* Mitsubishi M32R */ -+#define EM_MN10300 89 /* Matsushita MN10300 */ -+#define EM_MN10200 90 /* Matsushita MN10200 */ -+#define EM_PJ 91 /* picoJava */ -+#define EM_OPENRISC 92 /* OpenRISC 32-bit embedded processor */ -+#define EM_ARC_A5 93 /* ARC Cores Tangent-A5 */ -+#define EM_XTENSA 94 /* Tensilica Xtensa Architecture */ -+#define EM_NUM 95 -+ -+/* If it is necessary to assign new unofficial EM_* values, please -+ pick large random numbers (0x8523, 0xa7f2, etc.) to minimize the -+ chances of collision with official or non-GNU unofficial values. */ -+ -+#define EM_ALPHA 0x9026 -+ -+/* Legal values for e_version (version). */ -+ -+#define EV_NONE 0 /* Invalid ELF version */ -+#define EV_CURRENT 1 /* Current version */ -+#define EV_NUM 2 -+ -+/* Section header. */ -+ -+typedef struct -+{ -+ Elf32_Word sh_name; /* Section name (string tbl index) */ -+ Elf32_Word sh_type; /* Section type */ -+ Elf32_Word sh_flags; /* Section flags */ -+ Elf32_Addr sh_addr; /* Section virtual addr at execution */ -+ Elf32_Off sh_offset; /* Section file offset */ -+ Elf32_Word sh_size; /* Section size in bytes */ -+ Elf32_Word sh_link; /* Link to another section */ -+ Elf32_Word sh_info; /* Additional section information */ -+ Elf32_Word sh_addralign; /* Section alignment */ -+ Elf32_Word sh_entsize; /* Entry size if section holds table */ -+} Elf32_Shdr; -+ -+typedef struct -+{ -+ Elf64_Word sh_name; /* Section name (string tbl index) */ -+ Elf64_Word sh_type; /* Section type */ -+ Elf64_Xword sh_flags; /* Section flags */ -+ Elf64_Addr sh_addr; /* Section virtual addr at execution */ -+ Elf64_Off sh_offset; /* Section file offset */ -+ Elf64_Xword sh_size; /* Section size in bytes */ -+ Elf64_Word sh_link; /* Link to another section */ -+ Elf64_Word sh_info; /* Additional section information */ -+ Elf64_Xword sh_addralign; /* Section alignment */ -+ Elf64_Xword sh_entsize; /* Entry size if section holds table */ -+} Elf64_Shdr; -+ -+/* Special section indices. */ -+ -+#define SHN_UNDEF 0 /* Undefined section */ -+#define SHN_LORESERVE 0xff00 /* Start of reserved indices */ -+#define SHN_LOPROC 0xff00 /* Start of processor-specific */ -+#define SHN_HIPROC 0xff1f /* End of processor-specific */ -+#define SHN_LOOS 0xff20 /* Start of OS-specific */ -+#define SHN_HIOS 0xff3f /* End of OS-specific */ -+#define SHN_ABS 0xfff1 /* Associated symbol is absolute */ -+#define SHN_COMMON 0xfff2 /* Associated symbol is common */ -+#define SHN_XINDEX 0xffff /* Index is in extra table. */ -+#define SHN_HIRESERVE 0xffff /* End of reserved indices */ -+ -+/* Legal values for sh_type (section type). */ -+ -+#define SHT_NULL 0 /* Section header table entry unused */ -+#define SHT_PROGBITS 1 /* Program data */ -+#define SHT_SYMTAB 2 /* Symbol table */ -+#define SHT_STRTAB 3 /* String table */ -+#define SHT_RELA 4 /* Relocation entries with addends */ -+#define SHT_HASH 5 /* Symbol hash table */ -+#define SHT_DYNAMIC 6 /* Dynamic linking information */ -+#define SHT_NOTE 7 /* Notes */ -+#define SHT_NOBITS 8 /* Program space with no data (bss) */ -+#define SHT_REL 9 /* Relocation entries, no addends */ -+#define SHT_SHLIB 10 /* Reserved */ -+#define SHT_DYNSYM 11 /* Dynamic linker symbol table */ -+#define SHT_INIT_ARRAY 14 /* Array of constructors */ -+#define SHT_FINI_ARRAY 15 /* Array of destructors */ -+#define SHT_PREINIT_ARRAY 16 /* Array of pre-constructors */ -+#define SHT_GROUP 17 /* Section group */ -+#define SHT_SYMTAB_SHNDX 18 /* Extended section indeces */ -+#define SHT_NUM 19 /* Number of defined types. */ -+#define SHT_LOOS 0x60000000 /* Start OS-specific */ -+#define SHT_GNU_LIBLIST 0x6ffffff7 /* Prelink library list */ -+#define SHT_CHECKSUM 0x6ffffff8 /* Checksum for DSO content. */ -+#define SHT_LOSUNW 0x6ffffffa /* Sun-specific low bound. */ -+#define SHT_SUNW_move 0x6ffffffa -+#define SHT_SUNW_COMDAT 0x6ffffffb -+#define SHT_SUNW_syminfo 0x6ffffffc -+#define SHT_GNU_verdef 0x6ffffffd /* Version definition section. */ -+#define SHT_GNU_verneed 0x6ffffffe /* Version needs section. */ -+#define SHT_GNU_versym 0x6fffffff /* Version symbol table. */ -+#define SHT_HISUNW 0x6fffffff /* Sun-specific high bound. */ -+#define SHT_HIOS 0x6fffffff /* End OS-specific type */ -+#define SHT_LOPROC 0x70000000 /* Start of processor-specific */ -+#define SHT_HIPROC 0x7fffffff /* End of processor-specific */ -+#define SHT_LOUSER 0x80000000 /* Start of application-specific */ -+#define SHT_HIUSER 0x8fffffff /* End of application-specific */ -+ -+/* Legal values for sh_flags (section flags). */ -+ -+#define SHF_WRITE (1 << 0) /* Writable */ -+#define SHF_ALLOC (1 << 1) /* Occupies memory during execution */ -+#define SHF_EXECINSTR (1 << 2) /* Executable */ -+#define SHF_MERGE (1 << 4) /* Might be merged */ -+#define SHF_STRINGS (1 << 5) /* Contains nul-terminated strings */ -+#define SHF_INFO_LINK (1 << 6) /* `sh_info' contains SHT index */ -+#define SHF_LINK_ORDER (1 << 7) /* Preserve order after combining */ -+#define SHF_OS_NONCONFORMING (1 << 8) /* Non-standard OS specific handling -+ required */ -+#define SHF_GROUP (1 << 9) /* Section is member of a group. */ -+#define SHF_TLS (1 << 10) /* Section hold thread-local data. */ -+#define SHF_MASKOS 0x0ff00000 /* OS-specific. */ -+#define SHF_MASKPROC 0xf0000000 /* Processor-specific */ -+ -+/* Section group handling. */ -+#define GRP_COMDAT 0x1 /* Mark group as COMDAT. */ -+ -+/* Symbol table entry. */ -+ -+typedef struct -+{ -+ Elf32_Word st_name; /* Symbol name (string tbl index) */ -+ Elf32_Addr st_value; /* Symbol value */ -+ Elf32_Word st_size; /* Symbol size */ -+ unsigned char st_info; /* Symbol type and binding */ -+ unsigned char st_other; /* Symbol visibility */ -+ Elf32_Section st_shndx; /* Section index */ -+} Elf32_Sym; -+ -+typedef struct -+{ -+ Elf64_Word st_name; /* Symbol name (string tbl index) */ -+ unsigned char st_info; /* Symbol type and binding */ -+ unsigned char st_other; /* Symbol visibility */ -+ Elf64_Section st_shndx; /* Section index */ -+ Elf64_Addr st_value; /* Symbol value */ -+ Elf64_Xword st_size; /* Symbol size */ -+} Elf64_Sym; -+ -+/* The syminfo section if available contains additional information about -+ every dynamic symbol. */ -+ -+typedef struct -+{ -+ Elf32_Half si_boundto; /* Direct bindings, symbol bound to */ -+ Elf32_Half si_flags; /* Per symbol flags */ -+} Elf32_Syminfo; -+ -+typedef struct -+{ -+ Elf64_Half si_boundto; /* Direct bindings, symbol bound to */ -+ Elf64_Half si_flags; /* Per symbol flags */ -+} Elf64_Syminfo; -+ -+/* Possible values for si_boundto. */ -+#define SYMINFO_BT_SELF 0xffff /* Symbol bound to self */ -+#define SYMINFO_BT_PARENT 0xfffe /* Symbol bound to parent */ -+#define SYMINFO_BT_LOWRESERVE 0xff00 /* Beginning of reserved entries */ -+ -+/* Possible bitmasks for si_flags. */ -+#define SYMINFO_FLG_DIRECT 0x0001 /* Direct bound symbol */ -+#define SYMINFO_FLG_PASSTHRU 0x0002 /* Pass-thru symbol for translator */ -+#define SYMINFO_FLG_COPY 0x0004 /* Symbol is a copy-reloc */ -+#define SYMINFO_FLG_LAZYLOAD 0x0008 /* Symbol bound to object to be lazy -+ loaded */ -+/* Syminfo version values. */ -+#define SYMINFO_NONE 0 -+#define SYMINFO_CURRENT 1 -+#define SYMINFO_NUM 2 -+ -+ -+/* How to extract and insert information held in the st_info field. */ -+ -+#define ELF32_ST_BIND(val) (((unsigned char) (val)) >> 4) -+#define ELF32_ST_TYPE(val) ((val) & 0xf) -+#define ELF32_ST_INFO(bind, type) (((bind) << 4) + ((type) & 0xf)) -+ -+/* Both Elf32_Sym and Elf64_Sym use the same one-byte st_info field. */ -+#define ELF64_ST_BIND(val) ELF32_ST_BIND (val) -+#define ELF64_ST_TYPE(val) ELF32_ST_TYPE (val) -+#define ELF64_ST_INFO(bind, type) ELF32_ST_INFO ((bind), (type)) -+ -+/* Legal values for ST_BIND subfield of st_info (symbol binding). */ -+ -+#define STB_LOCAL 0 /* Local symbol */ -+#define STB_GLOBAL 1 /* Global symbol */ -+#define STB_WEAK 2 /* Weak symbol */ -+#define STB_NUM 3 /* Number of defined types. */ -+#define STB_LOOS 10 /* Start of OS-specific */ -+#define STB_HIOS 12 /* End of OS-specific */ -+#define STB_LOPROC 13 /* Start of processor-specific */ -+#define STB_HIPROC 15 /* End of processor-specific */ -+ -+/* Legal values for ST_TYPE subfield of st_info (symbol type). */ -+ -+#define STT_NOTYPE 0 /* Symbol type is unspecified */ -+#define STT_OBJECT 1 /* Symbol is a data object */ -+#define STT_FUNC 2 /* Symbol is a code object */ -+#define STT_SECTION 3 /* Symbol associated with a section */ -+#define STT_FILE 4 /* Symbol's name is file name */ -+#define STT_COMMON 5 /* Symbol is a common data object */ -+#define STT_TLS 6 /* Symbol is thread-local data object*/ -+#define STT_NUM 7 /* Number of defined types. */ -+#define STT_LOOS 10 /* Start of OS-specific */ -+#define STT_HIOS 12 /* End of OS-specific */ -+#define STT_LOPROC 13 /* Start of processor-specific */ -+#define STT_HIPROC 15 /* End of processor-specific */ -+ -+ -+/* Symbol table indices are found in the hash buckets and chain table -+ of a symbol hash table section. This special index value indicates -+ the end of a chain, meaning no further symbols are found in that bucket. */ -+ -+#define STN_UNDEF 0 /* End of a chain. */ -+ -+ -+/* How to extract and insert information held in the st_other field. */ -+ -+#define ELF32_ST_VISIBILITY(o) ((o) & 0x03) -+ -+/* For ELF64 the definitions are the same. */ -+#define ELF64_ST_VISIBILITY(o) ELF32_ST_VISIBILITY (o) -+ -+/* Symbol visibility specification encoded in the st_other field. */ -+#define STV_DEFAULT 0 /* Default symbol visibility rules */ -+#define STV_INTERNAL 1 /* Processor specific hidden class */ -+#define STV_HIDDEN 2 /* Sym unavailable in other modules */ -+#define STV_PROTECTED 3 /* Not preemptible, not exported */ -+ -+ -+/* Relocation table entry without addend (in section of type SHT_REL). */ -+ -+typedef struct -+{ -+ Elf32_Addr r_offset; /* Address */ -+ Elf32_Word r_info; /* Relocation type and symbol index */ -+} Elf32_Rel; -+ -+/* I have seen two different definitions of the Elf64_Rel and -+ Elf64_Rela structures, so we'll leave them out until Novell (or -+ whoever) gets their act together. */ -+/* The following, at least, is used on Sparc v9, MIPS, and Alpha. */ -+ -+typedef struct -+{ -+ Elf64_Addr r_offset; /* Address */ -+ Elf64_Xword r_info; /* Relocation type and symbol index */ -+} Elf64_Rel; -+ -+/* Relocation table entry with addend (in section of type SHT_RELA). */ -+ -+typedef struct -+{ -+ Elf32_Addr r_offset; /* Address */ -+ Elf32_Word r_info; /* Relocation type and symbol index */ -+ Elf32_Sword r_addend; /* Addend */ -+} Elf32_Rela; -+ -+typedef struct -+{ -+ Elf64_Addr r_offset; /* Address */ -+ Elf64_Xword r_info; /* Relocation type and symbol index */ -+ Elf64_Sxword r_addend; /* Addend */ -+} Elf64_Rela; -+ -+/* How to extract and insert information held in the r_info field. */ -+ -+#define ELF32_R_SYM(val) ((val) >> 8) -+#define ELF32_R_TYPE(val) ((val) & 0xff) -+#define ELF32_R_INFO(sym, type) (((sym) << 8) + ((type) & 0xff)) -+ -+#define ELF64_R_SYM(i) ((i) >> 32) -+#define ELF64_R_TYPE(i) ((i) & 0xffffffff) -+#define ELF64_R_INFO(sym,type) ((((Elf64_Xword) (sym)) << 32) + (type)) -+ -+/* Program segment header. */ -+ -+typedef struct -+{ -+ Elf32_Word p_type; /* Segment type */ -+ Elf32_Off p_offset; /* Segment file offset */ -+ Elf32_Addr p_vaddr; /* Segment virtual address */ -+ Elf32_Addr p_paddr; /* Segment physical address */ -+ Elf32_Word p_filesz; /* Segment size in file */ -+ Elf32_Word p_memsz; /* Segment size in memory */ -+ Elf32_Word p_flags; /* Segment flags */ -+ Elf32_Word p_align; /* Segment alignment */ -+} Elf32_Phdr; -+ -+typedef struct -+{ -+ Elf64_Word p_type; /* Segment type */ -+ Elf64_Word p_flags; /* Segment flags */ -+ Elf64_Off p_offset; /* Segment file offset */ -+ Elf64_Addr p_vaddr; /* Segment virtual address */ -+ Elf64_Addr p_paddr; /* Segment physical address */ -+ Elf64_Xword p_filesz; /* Segment size in file */ -+ Elf64_Xword p_memsz; /* Segment size in memory */ -+ Elf64_Xword p_align; /* Segment alignment */ -+} Elf64_Phdr; -+ -+/* Legal values for p_type (segment type). */ -+ -+#define PT_NULL 0 /* Program header table entry unused */ -+#define PT_LOAD 1 /* Loadable program segment */ -+#define PT_DYNAMIC 2 /* Dynamic linking information */ -+#define PT_INTERP 3 /* Program interpreter */ -+#define PT_NOTE 4 /* Auxiliary information */ -+#define PT_SHLIB 5 /* Reserved */ -+#define PT_PHDR 6 /* Entry for header table itself */ -+#define PT_TLS 7 /* Thread-local storage segment */ -+#define PT_NUM 8 /* Number of defined types */ -+#define PT_LOOS 0x60000000 /* Start of OS-specific */ -+#define PT_GNU_EH_FRAME 0x6474e550 /* GCC .eh_frame_hdr segment */ -+#define PT_GNU_STACK 0x6474e551 /* Indicates stack executability */ -+#define PT_LOSUNW 0x6ffffffa -+#define PT_SUNWBSS 0x6ffffffa /* Sun Specific segment */ -+#define PT_SUNWSTACK 0x6ffffffb /* Stack segment */ -+#define PT_HISUNW 0x6fffffff -+#define PT_HIOS 0x6fffffff /* End of OS-specific */ -+#define PT_LOPROC 0x70000000 /* Start of processor-specific */ -+#define PT_HIPROC 0x7fffffff /* End of processor-specific */ -+ -+/* Legal values for p_flags (segment flags). */ -+ -+#define PF_X (1 << 0) /* Segment is executable */ -+#define PF_W (1 << 1) /* Segment is writable */ -+#define PF_R (1 << 2) /* Segment is readable */ -+#define PF_MASKOS 0x0ff00000 /* OS-specific */ -+#define PF_MASKPROC 0xf0000000 /* Processor-specific */ -+ -+/* Legal values for note segment descriptor types for core files. */ -+ -+#define NT_PRSTATUS 1 /* Contains copy of prstatus struct */ -+#define NT_FPREGSET 2 /* Contains copy of fpregset struct */ -+#define NT_PRPSINFO 3 /* Contains copy of prpsinfo struct */ -+#define NT_PRXREG 4 /* Contains copy of prxregset struct */ -+#define NT_TASKSTRUCT 4 /* Contains copy of task structure */ -+#define NT_PLATFORM 5 /* String from sysinfo(SI_PLATFORM) */ -+#define NT_AUXV 6 /* Contains copy of auxv array */ -+#define NT_GWINDOWS 7 /* Contains copy of gwindows struct */ -+#define NT_ASRS 8 /* Contains copy of asrset struct */ -+#define NT_PSTATUS 10 /* Contains copy of pstatus struct */ -+#define NT_PSINFO 13 /* Contains copy of psinfo struct */ -+#define NT_PRCRED 14 /* Contains copy of prcred struct */ -+#define NT_UTSNAME 15 /* Contains copy of utsname struct */ -+#define NT_LWPSTATUS 16 /* Contains copy of lwpstatus struct */ -+#define NT_LWPSINFO 17 /* Contains copy of lwpinfo struct */ -+#define NT_PRFPXREG 20 /* Contains copy of fprxregset struct*/ -+ -+/* Legal values for the note segment descriptor types for object files. */ -+ -+#define NT_VERSION 1 /* Contains a version string. */ -+ -+ -+/* Dynamic section entry. */ -+ -+typedef struct -+{ -+ Elf32_Sword d_tag; /* Dynamic entry type */ -+ union -+ { -+ Elf32_Word d_val; /* Integer value */ -+ Elf32_Addr d_ptr; /* Address value */ -+ } d_un; -+} Elf32_Dyn; -+ -+typedef struct -+{ -+ Elf64_Sxword d_tag; /* Dynamic entry type */ -+ union -+ { -+ Elf64_Xword d_val; /* Integer value */ -+ Elf64_Addr d_ptr; /* Address value */ -+ } d_un; -+} Elf64_Dyn; -+ -+/* Legal values for d_tag (dynamic entry type). */ -+ -+#define DT_NULL 0 /* Marks end of dynamic section */ -+#define DT_NEEDED 1 /* Name of needed library */ -+#define DT_PLTRELSZ 2 /* Size in bytes of PLT relocs */ -+#define DT_PLTGOT 3 /* Processor defined value */ -+#define DT_HASH 4 /* Address of symbol hash table */ -+#define DT_STRTAB 5 /* Address of string table */ -+#define DT_SYMTAB 6 /* Address of symbol table */ -+#define DT_RELA 7 /* Address of Rela relocs */ -+#define DT_RELASZ 8 /* Total size of Rela relocs */ -+#define DT_RELAENT 9 /* Size of one Rela reloc */ -+#define DT_STRSZ 10 /* Size of string table */ -+#define DT_SYMENT 11 /* Size of one symbol table entry */ -+#define DT_INIT 12 /* Address of init function */ -+#define DT_FINI 13 /* Address of termination function */ -+#define DT_SONAME 14 /* Name of shared object */ -+#define DT_RPATH 15 /* Library search path (deprecated) */ -+#define DT_SYMBOLIC 16 /* Start symbol search here */ -+#define DT_REL 17 /* Address of Rel relocs */ -+#define DT_RELSZ 18 /* Total size of Rel relocs */ -+#define DT_RELENT 19 /* Size of one Rel reloc */ -+#define DT_PLTREL 20 /* Type of reloc in PLT */ -+#define DT_DEBUG 21 /* For debugging; unspecified */ -+#define DT_TEXTREL 22 /* Reloc might modify .text */ -+#define DT_JMPREL 23 /* Address of PLT relocs */ -+#define DT_BIND_NOW 24 /* Process relocations of object */ -+#define DT_INIT_ARRAY 25 /* Array with addresses of init fct */ -+#define DT_FINI_ARRAY 26 /* Array with addresses of fini fct */ -+#define DT_INIT_ARRAYSZ 27 /* Size in bytes of DT_INIT_ARRAY */ -+#define DT_FINI_ARRAYSZ 28 /* Size in bytes of DT_FINI_ARRAY */ -+#define DT_RUNPATH 29 /* Library search path */ -+#define DT_FLAGS 30 /* Flags for the object being loaded */ -+#define DT_ENCODING 32 /* Start of encoded range */ -+#define DT_PREINIT_ARRAY 32 /* Array with addresses of preinit fct*/ -+#define DT_PREINIT_ARRAYSZ 33 /* size in bytes of DT_PREINIT_ARRAY */ -+#define DT_NUM 34 /* Number used */ -+#define DT_LOOS 0x6000000d /* Start of OS-specific */ -+#define DT_HIOS 0x6ffff000 /* End of OS-specific */ -+#define DT_LOPROC 0x70000000 /* Start of processor-specific */ -+#define DT_HIPROC 0x7fffffff /* End of processor-specific */ -+#define DT_PROCNUM DT_MIPS_NUM /* Most used by any processor */ -+ -+/* DT_* entries which fall between DT_VALRNGHI & DT_VALRNGLO use the -+ Dyn.d_un.d_val field of the Elf*_Dyn structure. This follows Sun's -+ approach. */ -+#define DT_VALRNGLO 0x6ffffd00 -+#define DT_GNU_PRELINKED 0x6ffffdf5 /* Prelinking timestamp */ -+#define DT_GNU_CONFLICTSZ 0x6ffffdf6 /* Size of conflict section */ -+#define DT_GNU_LIBLISTSZ 0x6ffffdf7 /* Size of library list */ -+#define DT_CHECKSUM 0x6ffffdf8 -+#define DT_PLTPADSZ 0x6ffffdf9 -+#define DT_MOVEENT 0x6ffffdfa -+#define DT_MOVESZ 0x6ffffdfb -+#define DT_FEATURE_1 0x6ffffdfc /* Feature selection (DTF_*). */ -+#define DT_POSFLAG_1 0x6ffffdfd /* Flags for DT_* entries, effecting -+ the following DT_* entry. */ -+#define DT_SYMINSZ 0x6ffffdfe /* Size of syminfo table (in bytes) */ -+#define DT_SYMINENT 0x6ffffdff /* Entry size of syminfo */ -+#define DT_VALRNGHI 0x6ffffdff -+#define DT_VALTAGIDX(tag) (DT_VALRNGHI - (tag)) /* Reverse order! */ -+#define DT_VALNUM 12 -+ -+/* DT_* entries which fall between DT_ADDRRNGHI & DT_ADDRRNGLO use the -+ Dyn.d_un.d_ptr field of the Elf*_Dyn structure. -+ -+ If any adjustment is made to the ELF object after it has been -+ built these entries will need to be adjusted. */ -+#define DT_ADDRRNGLO 0x6ffffe00 -+#define DT_GNU_CONFLICT 0x6ffffef8 /* Start of conflict section */ -+#define DT_GNU_LIBLIST 0x6ffffef9 /* Library list */ -+#define DT_CONFIG 0x6ffffefa /* Configuration information. */ -+#define DT_DEPAUDIT 0x6ffffefb /* Dependency auditing. */ -+#define DT_AUDIT 0x6ffffefc /* Object auditing. */ -+#define DT_PLTPAD 0x6ffffefd /* PLT padding. */ -+#define DT_MOVETAB 0x6ffffefe /* Move table. */ -+#define DT_SYMINFO 0x6ffffeff /* Syminfo table. */ -+#define DT_ADDRRNGHI 0x6ffffeff -+#define DT_ADDRTAGIDX(tag) (DT_ADDRRNGHI - (tag)) /* Reverse order! */ -+#define DT_ADDRNUM 10 -+ -+/* The versioning entry types. The next are defined as part of the -+ GNU extension. */ -+#define DT_VERSYM 0x6ffffff0 -+ -+#define DT_RELACOUNT 0x6ffffff9 -+#define DT_RELCOUNT 0x6ffffffa -+ -+/* These were chosen by Sun. */ -+#define DT_FLAGS_1 0x6ffffffb /* State flags, see DF_1_* below. */ -+#define DT_VERDEF 0x6ffffffc /* Address of version definition -+ table */ -+#define DT_VERDEFNUM 0x6ffffffd /* Number of version definitions */ -+#define DT_VERNEED 0x6ffffffe /* Address of table with needed -+ versions */ -+#define DT_VERNEEDNUM 0x6fffffff /* Number of needed versions */ -+#define DT_VERSIONTAGIDX(tag) (DT_VERNEEDNUM - (tag)) /* Reverse order! */ -+#define DT_VERSIONTAGNUM 16 -+ -+/* Sun added these machine-independent extensions in the "processor-specific" -+ range. Be compatible. */ -+#define DT_AUXILIARY 0x7ffffffd /* Shared object to load before self */ -+#define DT_FILTER 0x7fffffff /* Shared object to get values from */ -+#define DT_EXTRATAGIDX(tag) ((Elf32_Word)-((Elf32_Sword) (tag) <<1>>1)-1) -+#define DT_EXTRANUM 3 -+ -+/* Values of `d_un.d_val' in the DT_FLAGS entry. */ -+#define DF_ORIGIN 0x00000001 /* Object may use DF_ORIGIN */ -+#define DF_SYMBOLIC 0x00000002 /* Symbol resolutions starts here */ -+#define DF_TEXTREL 0x00000004 /* Object contains text relocations */ -+#define DF_BIND_NOW 0x00000008 /* No lazy binding for this object */ -+#define DF_STATIC_TLS 0x00000010 /* Module uses the static TLS model */ -+ -+/* State flags selectable in the `d_un.d_val' element of the DT_FLAGS_1 -+ entry in the dynamic section. */ -+#define DF_1_NOW 0x00000001 /* Set RTLD_NOW for this object. */ -+#define DF_1_GLOBAL 0x00000002 /* Set RTLD_GLOBAL for this object. */ -+#define DF_1_GROUP 0x00000004 /* Set RTLD_GROUP for this object. */ -+#define DF_1_NODELETE 0x00000008 /* Set RTLD_NODELETE for this object.*/ -+#define DF_1_LOADFLTR 0x00000010 /* Trigger filtee loading at runtime.*/ -+#define DF_1_INITFIRST 0x00000020 /* Set RTLD_INITFIRST for this object*/ -+#define DF_1_NOOPEN 0x00000040 /* Set RTLD_NOOPEN for this object. */ -+#define DF_1_ORIGIN 0x00000080 /* $ORIGIN must be handled. */ -+#define DF_1_DIRECT 0x00000100 /* Direct binding enabled. */ -+#define DF_1_TRANS 0x00000200 -+#define DF_1_INTERPOSE 0x00000400 /* Object is used to interpose. */ -+#define DF_1_NODEFLIB 0x00000800 /* Ignore default lib search path. */ -+#define DF_1_NODUMP 0x00001000 /* Object can't be dldump'ed. */ -+#define DF_1_CONFALT 0x00002000 /* Configuration alternative created.*/ -+#define DF_1_ENDFILTEE 0x00004000 /* Filtee terminates filters search. */ -+#define DF_1_DISPRELDNE 0x00008000 /* Disp reloc applied at build time. */ -+#define DF_1_DISPRELPND 0x00010000 /* Disp reloc applied at run-time. */ -+ -+/* Flags for the feature selection in DT_FEATURE_1. */ -+#define DTF_1_PARINIT 0x00000001 -+#define DTF_1_CONFEXP 0x00000002 -+ -+/* Flags in the DT_POSFLAG_1 entry effecting only the next DT_* entry. */ -+#define DF_P1_LAZYLOAD 0x00000001 /* Lazyload following object. */ -+#define DF_P1_GROUPPERM 0x00000002 /* Symbols from next object are not -+ generally available. */ -+ -+/* Version definition sections. */ -+ -+typedef struct -+{ -+ Elf32_Half vd_version; /* Version revision */ -+ Elf32_Half vd_flags; /* Version information */ -+ Elf32_Half vd_ndx; /* Version Index */ -+ Elf32_Half vd_cnt; /* Number of associated aux entries */ -+ Elf32_Word vd_hash; /* Version name hash value */ -+ Elf32_Word vd_aux; /* Offset in bytes to verdaux array */ -+ Elf32_Word vd_next; /* Offset in bytes to next verdef -+ entry */ -+} Elf32_Verdef; -+ -+typedef struct -+{ -+ Elf64_Half vd_version; /* Version revision */ -+ Elf64_Half vd_flags; /* Version information */ -+ Elf64_Half vd_ndx; /* Version Index */ -+ Elf64_Half vd_cnt; /* Number of associated aux entries */ -+ Elf64_Word vd_hash; /* Version name hash value */ -+ Elf64_Word vd_aux; /* Offset in bytes to verdaux array */ -+ Elf64_Word vd_next; /* Offset in bytes to next verdef -+ entry */ -+} Elf64_Verdef; -+ -+ -+/* Legal values for vd_version (version revision). */ -+#define VER_DEF_NONE 0 /* No version */ -+#define VER_DEF_CURRENT 1 /* Current version */ -+#define VER_DEF_NUM 2 /* Given version number */ -+ -+/* Legal values for vd_flags (version information flags). */ -+#define VER_FLG_BASE 0x1 /* Version definition of file itself */ -+#define VER_FLG_WEAK 0x2 /* Weak version identifier */ -+ -+/* Versym symbol index values. */ -+#define VER_NDX_LOCAL 0 /* Symbol is local. */ -+#define VER_NDX_GLOBAL 1 /* Symbol is global. */ -+#define VER_NDX_LORESERVE 0xff00 /* Beginning of reserved entries. */ -+#define VER_NDX_ELIMINATE 0xff01 /* Symbol is to be eliminated. */ -+ -+/* Auxialiary version information. */ -+ -+typedef struct -+{ -+ Elf32_Word vda_name; /* Version or dependency names */ -+ Elf32_Word vda_next; /* Offset in bytes to next verdaux -+ entry */ -+} Elf32_Verdaux; -+ -+typedef struct -+{ -+ Elf64_Word vda_name; /* Version or dependency names */ -+ Elf64_Word vda_next; /* Offset in bytes to next verdaux -+ entry */ -+} Elf64_Verdaux; -+ -+ -+/* Version dependency section. */ -+ -+typedef struct -+{ -+ Elf32_Half vn_version; /* Version of structure */ -+ Elf32_Half vn_cnt; /* Number of associated aux entries */ -+ Elf32_Word vn_file; /* Offset of filename for this -+ dependency */ -+ Elf32_Word vn_aux; /* Offset in bytes to vernaux array */ -+ Elf32_Word vn_next; /* Offset in bytes to next verneed -+ entry */ -+} Elf32_Verneed; -+ -+typedef struct -+{ -+ Elf64_Half vn_version; /* Version of structure */ -+ Elf64_Half vn_cnt; /* Number of associated aux entries */ -+ Elf64_Word vn_file; /* Offset of filename for this -+ dependency */ -+ Elf64_Word vn_aux; /* Offset in bytes to vernaux array */ -+ Elf64_Word vn_next; /* Offset in bytes to next verneed -+ entry */ -+} Elf64_Verneed; -+ -+ -+/* Legal values for vn_version (version revision). */ -+#define VER_NEED_NONE 0 /* No version */ -+#define VER_NEED_CURRENT 1 /* Current version */ -+#define VER_NEED_NUM 2 /* Given version number */ -+ -+/* Auxiliary needed version information. */ -+ -+typedef struct -+{ -+ Elf32_Word vna_hash; /* Hash value of dependency name */ -+ Elf32_Half vna_flags; /* Dependency specific information */ -+ Elf32_Half vna_other; /* Unused */ -+ Elf32_Word vna_name; /* Dependency name string offset */ -+ Elf32_Word vna_next; /* Offset in bytes to next vernaux -+ entry */ -+} Elf32_Vernaux; -+ -+typedef struct -+{ -+ Elf64_Word vna_hash; /* Hash value of dependency name */ -+ Elf64_Half vna_flags; /* Dependency specific information */ -+ Elf64_Half vna_other; /* Unused */ -+ Elf64_Word vna_name; /* Dependency name string offset */ -+ Elf64_Word vna_next; /* Offset in bytes to next vernaux -+ entry */ -+} Elf64_Vernaux; -+ -+ -+/* Legal values for vna_flags. */ -+#define VER_FLG_WEAK 0x2 /* Weak version identifier */ -+ -+ -+/* Auxiliary vector. */ -+ -+/* This vector is normally only used by the program interpreter. The -+ usual definition in an ABI supplement uses the name auxv_t. The -+ vector is not usually defined in a standard file, but it -+ can't hurt. We rename it to avoid conflicts. The sizes of these -+ types are an arrangement between the exec server and the program -+ interpreter, so we don't fully specify them here. */ -+ -+typedef struct -+{ -+ int a_type; /* Entry type */ -+ union -+ { -+ long int a_val; /* Integer value */ -+ void *a_ptr; /* Pointer value */ -+ void (*a_fcn) (void); /* Function pointer value */ -+ } a_un; -+} Elf32_auxv_t; -+ -+typedef struct -+{ -+ long int a_type; /* Entry type */ -+ union -+ { -+ long int a_val; /* Integer value */ -+ void *a_ptr; /* Pointer value */ -+ void (*a_fcn) (void); /* Function pointer value */ -+ } a_un; -+} Elf64_auxv_t; -+ -+/* Legal values for a_type (entry type). */ -+ -+#define AT_NULL 0 /* End of vector */ -+#define AT_IGNORE 1 /* Entry should be ignored */ -+#define AT_EXECFD 2 /* File descriptor of program */ -+#define AT_PHDR 3 /* Program headers for program */ -+#define AT_PHENT 4 /* Size of program header entry */ -+#define AT_PHNUM 5 /* Number of program headers */ -+#define AT_PAGESZ 6 /* System page size */ -+#define AT_BASE 7 /* Base address of interpreter */ -+#define AT_FLAGS 8 /* Flags */ -+#define AT_ENTRY 9 /* Entry point of program */ -+#define AT_NOTELF 10 /* Program is not ELF */ -+#define AT_UID 11 /* Real uid */ -+#define AT_EUID 12 /* Effective uid */ -+#define AT_GID 13 /* Real gid */ -+#define AT_EGID 14 /* Effective gid */ -+#define AT_CLKTCK 17 /* Frequency of times() */ -+ -+/* Some more special a_type values describing the hardware. */ -+#define AT_PLATFORM 15 /* String identifying platform. */ -+#define AT_HWCAP 16 /* Machine dependent hints about -+ processor capabilities. */ -+ -+/* This entry gives some information about the FPU initialization -+ performed by the kernel. */ -+#define AT_FPUCW 18 /* Used FPU control word. */ -+ -+/* Cache block sizes. */ -+#define AT_DCACHEBSIZE 19 /* Data cache block size. */ -+#define AT_ICACHEBSIZE 20 /* Instruction cache block size. */ -+#define AT_UCACHEBSIZE 21 /* Unified cache block size. */ -+ -+/* A special ignored value for PPC, used by the kernel to control the -+ interpretation of the AUXV. Must be > 16. */ -+#define AT_IGNOREPPC 22 /* Entry should be ignored. */ -+ -+#define AT_SECURE 23 /* Boolean, was exec setuid-like? */ -+ -+/* Pointer to the global system page used for system calls and other -+ nice things. */ -+#define AT_SYSINFO 32 -+#define AT_SYSINFO_EHDR 33 -+ -+ -+/* Note section contents. Each entry in the note section begins with -+ a header of a fixed form. */ -+ -+typedef struct -+{ -+ Elf32_Word n_namesz; /* Length of the note's name. */ -+ Elf32_Word n_descsz; /* Length of the note's descriptor. */ -+ Elf32_Word n_type; /* Type of the note. */ -+} Elf32_Nhdr; -+ -+typedef struct -+{ -+ Elf64_Word n_namesz; /* Length of the note's name. */ -+ Elf64_Word n_descsz; /* Length of the note's descriptor. */ -+ Elf64_Word n_type; /* Type of the note. */ -+} Elf64_Nhdr; -+ -+/* Known names of notes. */ -+ -+/* Solaris entries in the note section have this name. */ -+#define ELF_NOTE_SOLARIS "SUNW Solaris" -+ -+/* Note entries for GNU systems have this name. */ -+#define ELF_NOTE_GNU "GNU" -+ -+ -+/* Defined types of notes for Solaris. */ -+ -+/* Value of descriptor (one word) is desired pagesize for the binary. */ -+#define ELF_NOTE_PAGESIZE_HINT 1 -+ -+ -+/* Defined note types for GNU systems. */ -+ -+/* ABI information. The descriptor consists of words: -+ word 0: OS descriptor -+ word 1: major version of the ABI -+ word 2: minor version of the ABI -+ word 3: subminor version of the ABI -+*/ -+#define ELF_NOTE_ABI 1 -+ -+/* Known OSes. These value can appear in word 0 of an ELF_NOTE_ABI -+ note section entry. */ -+#define ELF_NOTE_OS_LINUX 0 -+#define ELF_NOTE_OS_GNU 1 -+#define ELF_NOTE_OS_SOLARIS2 2 -+#define ELF_NOTE_OS_FREEBSD 3 -+ -+ -+/* Move records. */ -+typedef struct -+{ -+ Elf32_Xword m_value; /* Symbol value. */ -+ Elf32_Word m_info; /* Size and index. */ -+ Elf32_Word m_poffset; /* Symbol offset. */ -+ Elf32_Half m_repeat; /* Repeat count. */ -+ Elf32_Half m_stride; /* Stride info. */ -+} Elf32_Move; -+ -+typedef struct -+{ -+ Elf64_Xword m_value; /* Symbol value. */ -+ Elf64_Xword m_info; /* Size and index. */ -+ Elf64_Xword m_poffset; /* Symbol offset. */ -+ Elf64_Half m_repeat; /* Repeat count. */ -+ Elf64_Half m_stride; /* Stride info. */ -+} Elf64_Move; -+ -+/* Macro to construct move records. */ -+#define ELF32_M_SYM(info) ((info) >> 8) -+#define ELF32_M_SIZE(info) ((unsigned char) (info)) -+#define ELF32_M_INFO(sym, size) (((sym) << 8) + (unsigned char) (size)) -+ -+#define ELF64_M_SYM(info) ELF32_M_SYM (info) -+#define ELF64_M_SIZE(info) ELF32_M_SIZE (info) -+#define ELF64_M_INFO(sym, size) ELF32_M_INFO (sym, size) -+ -+ -+/* Motorola 68k specific definitions. */ -+ -+/* Values for Elf32_Ehdr.e_flags. */ -+#define EF_CPU32 0x00810000 -+ -+/* m68k relocs. */ -+ -+#define R_68K_NONE 0 /* No reloc */ -+#define R_68K_32 1 /* Direct 32 bit */ -+#define R_68K_16 2 /* Direct 16 bit */ -+#define R_68K_8 3 /* Direct 8 bit */ -+#define R_68K_PC32 4 /* PC relative 32 bit */ -+#define R_68K_PC16 5 /* PC relative 16 bit */ -+#define R_68K_PC8 6 /* PC relative 8 bit */ -+#define R_68K_GOT32 7 /* 32 bit PC relative GOT entry */ -+#define R_68K_GOT16 8 /* 16 bit PC relative GOT entry */ -+#define R_68K_GOT8 9 /* 8 bit PC relative GOT entry */ -+#define R_68K_GOT32O 10 /* 32 bit GOT offset */ -+#define R_68K_GOT16O 11 /* 16 bit GOT offset */ -+#define R_68K_GOT8O 12 /* 8 bit GOT offset */ -+#define R_68K_PLT32 13 /* 32 bit PC relative PLT address */ -+#define R_68K_PLT16 14 /* 16 bit PC relative PLT address */ -+#define R_68K_PLT8 15 /* 8 bit PC relative PLT address */ -+#define R_68K_PLT32O 16 /* 32 bit PLT offset */ -+#define R_68K_PLT16O 17 /* 16 bit PLT offset */ -+#define R_68K_PLT8O 18 /* 8 bit PLT offset */ -+#define R_68K_COPY 19 /* Copy symbol at runtime */ -+#define R_68K_GLOB_DAT 20 /* Create GOT entry */ -+#define R_68K_JMP_SLOT 21 /* Create PLT entry */ -+#define R_68K_RELATIVE 22 /* Adjust by program base */ -+/* Keep this the last entry. */ -+#define R_68K_NUM 23 -+ -+/* Intel 80386 specific definitions. */ -+ -+/* i386 relocs. */ -+ -+#define R_386_NONE 0 /* No reloc */ -+#define R_386_32 1 /* Direct 32 bit */ -+#define R_386_PC32 2 /* PC relative 32 bit */ -+#define R_386_GOT32 3 /* 32 bit GOT entry */ -+#define R_386_PLT32 4 /* 32 bit PLT address */ -+#define R_386_COPY 5 /* Copy symbol at runtime */ -+#define R_386_GLOB_DAT 6 /* Create GOT entry */ -+#define R_386_JMP_SLOT 7 /* Create PLT entry */ -+#define R_386_RELATIVE 8 /* Adjust by program base */ -+#define R_386_GOTOFF 9 /* 32 bit offset to GOT */ -+#define R_386_GOTPC 10 /* 32 bit PC relative offset to GOT */ -+#define R_386_32PLT 11 -+#define R_386_TLS_TPOFF 14 /* Offset in static TLS block */ -+#define R_386_TLS_IE 15 /* Address of GOT entry for static TLS -+ block offset */ -+#define R_386_TLS_GOTIE 16 /* GOT entry for static TLS block -+ offset */ -+#define R_386_TLS_LE 17 /* Offset relative to static TLS -+ block */ -+#define R_386_TLS_GD 18 /* Direct 32 bit for GNU version of -+ general dynamic thread local data */ -+#define R_386_TLS_LDM 19 /* Direct 32 bit for GNU version of -+ local dynamic thread local data -+ in LE code */ -+#define R_386_16 20 -+#define R_386_PC16 21 -+#define R_386_8 22 -+#define R_386_PC8 23 -+#define R_386_TLS_GD_32 24 /* Direct 32 bit for general dynamic -+ thread local data */ -+#define R_386_TLS_GD_PUSH 25 /* Tag for pushl in GD TLS code */ -+#define R_386_TLS_GD_CALL 26 /* Relocation for call to -+ __tls_get_addr() */ -+#define R_386_TLS_GD_POP 27 /* Tag for popl in GD TLS code */ -+#define R_386_TLS_LDM_32 28 /* Direct 32 bit for local dynamic -+ thread local data in LE code */ -+#define R_386_TLS_LDM_PUSH 29 /* Tag for pushl in LDM TLS code */ -+#define R_386_TLS_LDM_CALL 30 /* Relocation for call to -+ __tls_get_addr() in LDM code */ -+#define R_386_TLS_LDM_POP 31 /* Tag for popl in LDM TLS code */ -+#define R_386_TLS_LDO_32 32 /* Offset relative to TLS block */ -+#define R_386_TLS_IE_32 33 /* GOT entry for negated static TLS -+ block offset */ -+#define R_386_TLS_LE_32 34 /* Negated offset relative to static -+ TLS block */ -+#define R_386_TLS_DTPMOD32 35 /* ID of module containing symbol */ -+#define R_386_TLS_DTPOFF32 36 /* Offset in TLS block */ -+#define R_386_TLS_TPOFF32 37 /* Negated offset in static TLS block */ -+/* Keep this the last entry. */ -+#define R_386_NUM 38 -+ -+/* SUN SPARC specific definitions. */ -+ -+/* Legal values for ST_TYPE subfield of st_info (symbol type). */ -+ -+#define STT_REGISTER 13 /* Global register reserved to app. */ -+ -+/* Values for Elf64_Ehdr.e_flags. */ -+ -+#define EF_SPARCV9_MM 3 -+#define EF_SPARCV9_TSO 0 -+#define EF_SPARCV9_PSO 1 -+#define EF_SPARCV9_RMO 2 -+#define EF_SPARC_LEDATA 0x800000 /* little endian data */ -+#define EF_SPARC_EXT_MASK 0xFFFF00 -+#define EF_SPARC_32PLUS 0x000100 /* generic V8+ features */ -+#define EF_SPARC_SUN_US1 0x000200 /* Sun UltraSPARC1 extensions */ -+#define EF_SPARC_HAL_R1 0x000400 /* HAL R1 extensions */ -+#define EF_SPARC_SUN_US3 0x000800 /* Sun UltraSPARCIII extensions */ -+ -+/* SPARC relocs. */ -+ -+#define R_SPARC_NONE 0 /* No reloc */ -+#define R_SPARC_8 1 /* Direct 8 bit */ -+#define R_SPARC_16 2 /* Direct 16 bit */ -+#define R_SPARC_32 3 /* Direct 32 bit */ -+#define R_SPARC_DISP8 4 /* PC relative 8 bit */ -+#define R_SPARC_DISP16 5 /* PC relative 16 bit */ -+#define R_SPARC_DISP32 6 /* PC relative 32 bit */ -+#define R_SPARC_WDISP30 7 /* PC relative 30 bit shifted */ -+#define R_SPARC_WDISP22 8 /* PC relative 22 bit shifted */ -+#define R_SPARC_HI22 9 /* High 22 bit */ -+#define R_SPARC_22 10 /* Direct 22 bit */ -+#define R_SPARC_13 11 /* Direct 13 bit */ -+#define R_SPARC_LO10 12 /* Truncated 10 bit */ -+#define R_SPARC_GOT10 13 /* Truncated 10 bit GOT entry */ -+#define R_SPARC_GOT13 14 /* 13 bit GOT entry */ -+#define R_SPARC_GOT22 15 /* 22 bit GOT entry shifted */ -+#define R_SPARC_PC10 16 /* PC relative 10 bit truncated */ -+#define R_SPARC_PC22 17 /* PC relative 22 bit shifted */ -+#define R_SPARC_WPLT30 18 /* 30 bit PC relative PLT address */ -+#define R_SPARC_COPY 19 /* Copy symbol at runtime */ -+#define R_SPARC_GLOB_DAT 20 /* Create GOT entry */ -+#define R_SPARC_JMP_SLOT 21 /* Create PLT entry */ -+#define R_SPARC_RELATIVE 22 /* Adjust by program base */ -+#define R_SPARC_UA32 23 /* Direct 32 bit unaligned */ -+ -+/* Additional Sparc64 relocs. */ -+ -+#define R_SPARC_PLT32 24 /* Direct 32 bit ref to PLT entry */ -+#define R_SPARC_HIPLT22 25 /* High 22 bit PLT entry */ -+#define R_SPARC_LOPLT10 26 /* Truncated 10 bit PLT entry */ -+#define R_SPARC_PCPLT32 27 /* PC rel 32 bit ref to PLT entry */ -+#define R_SPARC_PCPLT22 28 /* PC rel high 22 bit PLT entry */ -+#define R_SPARC_PCPLT10 29 /* PC rel trunc 10 bit PLT entry */ -+#define R_SPARC_10 30 /* Direct 10 bit */ -+#define R_SPARC_11 31 /* Direct 11 bit */ -+#define R_SPARC_64 32 /* Direct 64 bit */ -+#define R_SPARC_OLO10 33 /* 10bit with secondary 13bit addend */ -+#define R_SPARC_HH22 34 /* Top 22 bits of direct 64 bit */ -+#define R_SPARC_HM10 35 /* High middle 10 bits of ... */ -+#define R_SPARC_LM22 36 /* Low middle 22 bits of ... */ -+#define R_SPARC_PC_HH22 37 /* Top 22 bits of pc rel 64 bit */ -+#define R_SPARC_PC_HM10 38 /* High middle 10 bit of ... */ -+#define R_SPARC_PC_LM22 39 /* Low miggle 22 bits of ... */ -+#define R_SPARC_WDISP16 40 /* PC relative 16 bit shifted */ -+#define R_SPARC_WDISP19 41 /* PC relative 19 bit shifted */ -+#define R_SPARC_7 43 /* Direct 7 bit */ -+#define R_SPARC_5 44 /* Direct 5 bit */ -+#define R_SPARC_6 45 /* Direct 6 bit */ -+#define R_SPARC_DISP64 46 /* PC relative 64 bit */ -+#define R_SPARC_PLT64 47 /* Direct 64 bit ref to PLT entry */ -+#define R_SPARC_HIX22 48 /* High 22 bit complemented */ -+#define R_SPARC_LOX10 49 /* Truncated 11 bit complemented */ -+#define R_SPARC_H44 50 /* Direct high 12 of 44 bit */ -+#define R_SPARC_M44 51 /* Direct mid 22 of 44 bit */ -+#define R_SPARC_L44 52 /* Direct low 10 of 44 bit */ -+#define R_SPARC_REGISTER 53 /* Global register usage */ -+#define R_SPARC_UA64 54 /* Direct 64 bit unaligned */ -+#define R_SPARC_UA16 55 /* Direct 16 bit unaligned */ -+#define R_SPARC_TLS_GD_HI22 56 -+#define R_SPARC_TLS_GD_LO10 57 -+#define R_SPARC_TLS_GD_ADD 58 -+#define R_SPARC_TLS_GD_CALL 59 -+#define R_SPARC_TLS_LDM_HI22 60 -+#define R_SPARC_TLS_LDM_LO10 61 -+#define R_SPARC_TLS_LDM_ADD 62 -+#define R_SPARC_TLS_LDM_CALL 63 -+#define R_SPARC_TLS_LDO_HIX22 64 -+#define R_SPARC_TLS_LDO_LOX10 65 -+#define R_SPARC_TLS_LDO_ADD 66 -+#define R_SPARC_TLS_IE_HI22 67 -+#define R_SPARC_TLS_IE_LO10 68 -+#define R_SPARC_TLS_IE_LD 69 -+#define R_SPARC_TLS_IE_LDX 70 -+#define R_SPARC_TLS_IE_ADD 71 -+#define R_SPARC_TLS_LE_HIX22 72 -+#define R_SPARC_TLS_LE_LOX10 73 -+#define R_SPARC_TLS_DTPMOD32 74 -+#define R_SPARC_TLS_DTPMOD64 75 -+#define R_SPARC_TLS_DTPOFF32 76 -+#define R_SPARC_TLS_DTPOFF64 77 -+#define R_SPARC_TLS_TPOFF32 78 -+#define R_SPARC_TLS_TPOFF64 79 -+/* Keep this the last entry. */ -+#define R_SPARC_NUM 80 -+ -+/* For Sparc64, legal values for d_tag of Elf64_Dyn. */ -+ -+#define DT_SPARC_REGISTER 0x70000001 -+#define DT_SPARC_NUM 2 -+ -+/* Bits present in AT_HWCAP, primarily for Sparc32. */ -+ -+#define HWCAP_SPARC_FLUSH 1 /* The cpu supports flush insn. */ -+#define HWCAP_SPARC_STBAR 2 -+#define HWCAP_SPARC_SWAP 4 -+#define HWCAP_SPARC_MULDIV 8 -+#define HWCAP_SPARC_V9 16 /* The cpu is v9, so v8plus is ok. */ -+#define HWCAP_SPARC_ULTRA3 32 -+ -+/* MIPS R3000 specific definitions. */ -+ -+/* Legal values for e_flags field of Elf32_Ehdr. */ -+ -+#define EF_MIPS_NOREORDER 1 /* A .noreorder directive was used */ -+#define EF_MIPS_PIC 2 /* Contains PIC code */ -+#define EF_MIPS_CPIC 4 /* Uses PIC calling sequence */ -+#define EF_MIPS_XGOT 8 -+#define EF_MIPS_64BIT_WHIRL 16 -+#define EF_MIPS_ABI2 32 -+#define EF_MIPS_ABI_ON32 64 -+#define EF_MIPS_ARCH 0xf0000000 /* MIPS architecture level */ -+ -+/* Legal values for MIPS architecture level. */ -+ -+#define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ -+#define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ -+#define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ -+#define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ -+#define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ -+#define EF_MIPS_ARCH_32 0x60000000 /* MIPS32 code. */ -+#define EF_MIPS_ARCH_64 0x70000000 /* MIPS64 code. */ -+ -+/* The following are non-official names and should not be used. */ -+ -+#define E_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ -+#define E_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ -+#define E_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ -+#define E_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ -+#define E_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ -+#define E_MIPS_ARCH_32 0x60000000 /* MIPS32 code. */ -+#define E_MIPS_ARCH_64 0x70000000 /* MIPS64 code. */ -+ -+/* Special section indices. */ -+ -+#define SHN_MIPS_ACOMMON 0xff00 /* Allocated common symbols */ -+#define SHN_MIPS_TEXT 0xff01 /* Allocated test symbols. */ -+#define SHN_MIPS_DATA 0xff02 /* Allocated data symbols. */ -+#define SHN_MIPS_SCOMMON 0xff03 /* Small common symbols */ -+#define SHN_MIPS_SUNDEFINED 0xff04 /* Small undefined symbols */ -+ -+/* Legal values for sh_type field of Elf32_Shdr. */ -+ -+#define SHT_MIPS_LIBLIST 0x70000000 /* Shared objects used in link */ -+#define SHT_MIPS_MSYM 0x70000001 -+#define SHT_MIPS_CONFLICT 0x70000002 /* Conflicting symbols */ -+#define SHT_MIPS_GPTAB 0x70000003 /* Global data area sizes */ -+#define SHT_MIPS_UCODE 0x70000004 /* Reserved for SGI/MIPS compilers */ -+#define SHT_MIPS_DEBUG 0x70000005 /* MIPS ECOFF debugging information*/ -+#define SHT_MIPS_REGINFO 0x70000006 /* Register usage information */ -+#define SHT_MIPS_PACKAGE 0x70000007 -+#define SHT_MIPS_PACKSYM 0x70000008 -+#define SHT_MIPS_RELD 0x70000009 -+#define SHT_MIPS_IFACE 0x7000000b -+#define SHT_MIPS_CONTENT 0x7000000c -+#define SHT_MIPS_OPTIONS 0x7000000d /* Miscellaneous options. */ -+#define SHT_MIPS_SHDR 0x70000010 -+#define SHT_MIPS_FDESC 0x70000011 -+#define SHT_MIPS_EXTSYM 0x70000012 -+#define SHT_MIPS_DENSE 0x70000013 -+#define SHT_MIPS_PDESC 0x70000014 -+#define SHT_MIPS_LOCSYM 0x70000015 -+#define SHT_MIPS_AUXSYM 0x70000016 -+#define SHT_MIPS_OPTSYM 0x70000017 -+#define SHT_MIPS_LOCSTR 0x70000018 -+#define SHT_MIPS_LINE 0x70000019 -+#define SHT_MIPS_RFDESC 0x7000001a -+#define SHT_MIPS_DELTASYM 0x7000001b -+#define SHT_MIPS_DELTAINST 0x7000001c -+#define SHT_MIPS_DELTACLASS 0x7000001d -+#define SHT_MIPS_DWARF 0x7000001e /* DWARF debugging information. */ -+#define SHT_MIPS_DELTADECL 0x7000001f -+#define SHT_MIPS_SYMBOL_LIB 0x70000020 -+#define SHT_MIPS_EVENTS 0x70000021 /* Event section. */ -+#define SHT_MIPS_TRANSLATE 0x70000022 -+#define SHT_MIPS_PIXIE 0x70000023 -+#define SHT_MIPS_XLATE 0x70000024 -+#define SHT_MIPS_XLATE_DEBUG 0x70000025 -+#define SHT_MIPS_WHIRL 0x70000026 -+#define SHT_MIPS_EH_REGION 0x70000027 -+#define SHT_MIPS_XLATE_OLD 0x70000028 -+#define SHT_MIPS_PDR_EXCEPTION 0x70000029 -+ -+/* Legal values for sh_flags field of Elf32_Shdr. */ -+ -+#define SHF_MIPS_GPREL 0x10000000 /* Must be part of global data area */ -+#define SHF_MIPS_MERGE 0x20000000 -+#define SHF_MIPS_ADDR 0x40000000 -+#define SHF_MIPS_STRINGS 0x80000000 -+#define SHF_MIPS_NOSTRIP 0x08000000 -+#define SHF_MIPS_LOCAL 0x04000000 -+#define SHF_MIPS_NAMES 0x02000000 -+#define SHF_MIPS_NODUPE 0x01000000 -+ -+ -+/* Symbol tables. */ -+ -+/* MIPS specific values for `st_other'. */ -+#define STO_MIPS_DEFAULT 0x0 -+#define STO_MIPS_INTERNAL 0x1 -+#define STO_MIPS_HIDDEN 0x2 -+#define STO_MIPS_PROTECTED 0x3 -+#define STO_MIPS_SC_ALIGN_UNUSED 0xff -+ -+/* MIPS specific values for `st_info'. */ -+#define STB_MIPS_SPLIT_COMMON 13 -+ -+/* Entries found in sections of type SHT_MIPS_GPTAB. */ -+ -+typedef union -+{ -+ struct -+ { -+ Elf32_Word gt_current_g_value; /* -G value used for compilation */ -+ Elf32_Word gt_unused; /* Not used */ -+ } gt_header; /* First entry in section */ -+ struct -+ { -+ Elf32_Word gt_g_value; /* If this value were used for -G */ -+ Elf32_Word gt_bytes; /* This many bytes would be used */ -+ } gt_entry; /* Subsequent entries in section */ -+} Elf32_gptab; -+ -+/* Entry found in sections of type SHT_MIPS_REGINFO. */ -+ -+typedef struct -+{ -+ Elf32_Word ri_gprmask; /* General registers used */ -+ Elf32_Word ri_cprmask[4]; /* Coprocessor registers used */ -+ Elf32_Sword ri_gp_value; /* $gp register value */ -+} Elf32_RegInfo; -+ -+/* Entries found in sections of type SHT_MIPS_OPTIONS. */ -+ -+typedef struct -+{ -+ unsigned char kind; /* Determines interpretation of the -+ variable part of descriptor. */ -+ unsigned char size; /* Size of descriptor, including header. */ -+ Elf32_Section section; /* Section header index of section affected, -+ 0 for global options. */ -+ Elf32_Word info; /* Kind-specific information. */ -+} Elf_Options; -+ -+/* Values for `kind' field in Elf_Options. */ -+ -+#define ODK_NULL 0 /* Undefined. */ -+#define ODK_REGINFO 1 /* Register usage information. */ -+#define ODK_EXCEPTIONS 2 /* Exception processing options. */ -+#define ODK_PAD 3 /* Section padding options. */ -+#define ODK_HWPATCH 4 /* Hardware workarounds performed */ -+#define ODK_FILL 5 /* record the fill value used by the linker. */ -+#define ODK_TAGS 6 /* reserve space for desktop tools to write. */ -+#define ODK_HWAND 7 /* HW workarounds. 'AND' bits when merging. */ -+#define ODK_HWOR 8 /* HW workarounds. 'OR' bits when merging. */ -+ -+/* Values for `info' in Elf_Options for ODK_EXCEPTIONS entries. */ -+ -+#define OEX_FPU_MIN 0x1f /* FPE's which MUST be enabled. */ -+#define OEX_FPU_MAX 0x1f00 /* FPE's which MAY be enabled. */ -+#define OEX_PAGE0 0x10000 /* page zero must be mapped. */ -+#define OEX_SMM 0x20000 /* Force sequential memory mode? */ -+#define OEX_FPDBUG 0x40000 /* Force floating point debug mode? */ -+#define OEX_PRECISEFP OEX_FPDBUG -+#define OEX_DISMISS 0x80000 /* Dismiss invalid address faults? */ -+ -+#define OEX_FPU_INVAL 0x10 -+#define OEX_FPU_DIV0 0x08 -+#define OEX_FPU_OFLO 0x04 -+#define OEX_FPU_UFLO 0x02 -+#define OEX_FPU_INEX 0x01 -+ -+/* Masks for `info' in Elf_Options for an ODK_HWPATCH entry. */ -+ -+#define OHW_R4KEOP 0x1 /* R4000 end-of-page patch. */ -+#define OHW_R8KPFETCH 0x2 /* may need R8000 prefetch patch. */ -+#define OHW_R5KEOP 0x4 /* R5000 end-of-page patch. */ -+#define OHW_R5KCVTL 0x8 /* R5000 cvt.[ds].l bug. clean=1. */ -+ -+#define OPAD_PREFIX 0x1 -+#define OPAD_POSTFIX 0x2 -+#define OPAD_SYMBOL 0x4 -+ -+/* Entry found in `.options' section. */ -+ -+typedef struct -+{ -+ Elf32_Word hwp_flags1; /* Extra flags. */ -+ Elf32_Word hwp_flags2; /* Extra flags. */ -+} Elf_Options_Hw; -+ -+/* Masks for `info' in ElfOptions for ODK_HWAND and ODK_HWOR entries. */ -+ -+#define OHWA0_R4KEOP_CHECKED 0x00000001 -+#define OHWA1_R4KEOP_CLEAN 0x00000002 -+ -+/* MIPS relocs. */ -+ -+#define R_MIPS_NONE 0 /* No reloc */ -+#define R_MIPS_16 1 /* Direct 16 bit */ -+#define R_MIPS_32 2 /* Direct 32 bit */ -+#define R_MIPS_REL32 3 /* PC relative 32 bit */ -+#define R_MIPS_26 4 /* Direct 26 bit shifted */ -+#define R_MIPS_HI16 5 /* High 16 bit */ -+#define R_MIPS_LO16 6 /* Low 16 bit */ -+#define R_MIPS_GPREL16 7 /* GP relative 16 bit */ -+#define R_MIPS_LITERAL 8 /* 16 bit literal entry */ -+#define R_MIPS_GOT16 9 /* 16 bit GOT entry */ -+#define R_MIPS_PC16 10 /* PC relative 16 bit */ -+#define R_MIPS_CALL16 11 /* 16 bit GOT entry for function */ -+#define R_MIPS_GPREL32 12 /* GP relative 32 bit */ -+ -+#define R_MIPS_SHIFT5 16 -+#define R_MIPS_SHIFT6 17 -+#define R_MIPS_64 18 -+#define R_MIPS_GOT_DISP 19 -+#define R_MIPS_GOT_PAGE 20 -+#define R_MIPS_GOT_OFST 21 -+#define R_MIPS_GOT_HI16 22 -+#define R_MIPS_GOT_LO16 23 -+#define R_MIPS_SUB 24 -+#define R_MIPS_INSERT_A 25 -+#define R_MIPS_INSERT_B 26 -+#define R_MIPS_DELETE 27 -+#define R_MIPS_HIGHER 28 -+#define R_MIPS_HIGHEST 29 -+#define R_MIPS_CALL_HI16 30 -+#define R_MIPS_CALL_LO16 31 -+#define R_MIPS_SCN_DISP 32 -+#define R_MIPS_REL16 33 -+#define R_MIPS_ADD_IMMEDIATE 34 -+#define R_MIPS_PJUMP 35 -+#define R_MIPS_RELGOT 36 -+#define R_MIPS_JALR 37 -+/* Keep this the last entry. */ -+#define R_MIPS_NUM 38 -+ -+/* Legal values for p_type field of Elf32_Phdr. */ -+ -+#define PT_MIPS_REGINFO 0x70000000 /* Register usage information */ -+#define PT_MIPS_RTPROC 0x70000001 /* Runtime procedure table. */ -+#define PT_MIPS_OPTIONS 0x70000002 -+ -+/* Special program header types. */ -+ -+#define PF_MIPS_LOCAL 0x10000000 -+ -+/* Legal values for d_tag field of Elf32_Dyn. */ -+ -+#define DT_MIPS_RLD_VERSION 0x70000001 /* Runtime linker interface version */ -+#define DT_MIPS_TIME_STAMP 0x70000002 /* Timestamp */ -+#define DT_MIPS_ICHECKSUM 0x70000003 /* Checksum */ -+#define DT_MIPS_IVERSION 0x70000004 /* Version string (string tbl index) */ -+#define DT_MIPS_FLAGS 0x70000005 /* Flags */ -+#define DT_MIPS_BASE_ADDRESS 0x70000006 /* Base address */ -+#define DT_MIPS_MSYM 0x70000007 -+#define DT_MIPS_CONFLICT 0x70000008 /* Address of CONFLICT section */ -+#define DT_MIPS_LIBLIST 0x70000009 /* Address of LIBLIST section */ -+#define DT_MIPS_LOCAL_GOTNO 0x7000000a /* Number of local GOT entries */ -+#define DT_MIPS_CONFLICTNO 0x7000000b /* Number of CONFLICT entries */ -+#define DT_MIPS_LIBLISTNO 0x70000010 /* Number of LIBLIST entries */ -+#define DT_MIPS_SYMTABNO 0x70000011 /* Number of DYNSYM entries */ -+#define DT_MIPS_UNREFEXTNO 0x70000012 /* First external DYNSYM */ -+#define DT_MIPS_GOTSYM 0x70000013 /* First GOT entry in DYNSYM */ -+#define DT_MIPS_HIPAGENO 0x70000014 /* Number of GOT page table entries */ -+#define DT_MIPS_RLD_MAP 0x70000016 /* Address of run time loader map. */ -+#define DT_MIPS_DELTA_CLASS 0x70000017 /* Delta C++ class definition. */ -+#define DT_MIPS_DELTA_CLASS_NO 0x70000018 /* Number of entries in -+ DT_MIPS_DELTA_CLASS. */ -+#define DT_MIPS_DELTA_INSTANCE 0x70000019 /* Delta C++ class instances. */ -+#define DT_MIPS_DELTA_INSTANCE_NO 0x7000001a /* Number of entries in -+ DT_MIPS_DELTA_INSTANCE. */ -+#define DT_MIPS_DELTA_RELOC 0x7000001b /* Delta relocations. */ -+#define DT_MIPS_DELTA_RELOC_NO 0x7000001c /* Number of entries in -+ DT_MIPS_DELTA_RELOC. */ -+#define DT_MIPS_DELTA_SYM 0x7000001d /* Delta symbols that Delta -+ relocations refer to. */ -+#define DT_MIPS_DELTA_SYM_NO 0x7000001e /* Number of entries in -+ DT_MIPS_DELTA_SYM. */ -+#define DT_MIPS_DELTA_CLASSSYM 0x70000020 /* Delta symbols that hold the -+ class declaration. */ -+#define DT_MIPS_DELTA_CLASSSYM_NO 0x70000021 /* Number of entries in -+ DT_MIPS_DELTA_CLASSSYM. */ -+#define DT_MIPS_CXX_FLAGS 0x70000022 /* Flags indicating for C++ flavor. */ -+#define DT_MIPS_PIXIE_INIT 0x70000023 -+#define DT_MIPS_SYMBOL_LIB 0x70000024 -+#define DT_MIPS_LOCALPAGE_GOTIDX 0x70000025 -+#define DT_MIPS_LOCAL_GOTIDX 0x70000026 -+#define DT_MIPS_HIDDEN_GOTIDX 0x70000027 -+#define DT_MIPS_PROTECTED_GOTIDX 0x70000028 -+#define DT_MIPS_OPTIONS 0x70000029 /* Address of .options. */ -+#define DT_MIPS_INTERFACE 0x7000002a /* Address of .interface. */ -+#define DT_MIPS_DYNSTR_ALIGN 0x7000002b -+#define DT_MIPS_INTERFACE_SIZE 0x7000002c /* Size of the .interface section. */ -+#define DT_MIPS_RLD_TEXT_RESOLVE_ADDR 0x7000002d /* Address of rld_text_rsolve -+ function stored in GOT. */ -+#define DT_MIPS_PERF_SUFFIX 0x7000002e /* Default suffix of dso to be added -+ by rld on dlopen() calls. */ -+#define DT_MIPS_COMPACT_SIZE 0x7000002f /* (O32)Size of compact rel section. */ -+#define DT_MIPS_GP_VALUE 0x70000030 /* GP value for aux GOTs. */ -+#define DT_MIPS_AUX_DYNAMIC 0x70000031 /* Address of aux .dynamic. */ -+#define DT_MIPS_NUM 0x32 -+ -+/* Legal values for DT_MIPS_FLAGS Elf32_Dyn entry. */ -+ -+#define RHF_NONE 0 /* No flags */ -+#define RHF_QUICKSTART (1 << 0) /* Use quickstart */ -+#define RHF_NOTPOT (1 << 1) /* Hash size not power of 2 */ -+#define RHF_NO_LIBRARY_REPLACEMENT (1 << 2) /* Ignore LD_LIBRARY_PATH */ -+#define RHF_NO_MOVE (1 << 3) -+#define RHF_SGI_ONLY (1 << 4) -+#define RHF_GUARANTEE_INIT (1 << 5) -+#define RHF_DELTA_C_PLUS_PLUS (1 << 6) -+#define RHF_GUARANTEE_START_INIT (1 << 7) -+#define RHF_PIXIE (1 << 8) -+#define RHF_DEFAULT_DELAY_LOAD (1 << 9) -+#define RHF_REQUICKSTART (1 << 10) -+#define RHF_REQUICKSTARTED (1 << 11) -+#define RHF_CORD (1 << 12) -+#define RHF_NO_UNRES_UNDEF (1 << 13) -+#define RHF_RLD_ORDER_SAFE (1 << 14) -+ -+/* Entries found in sections of type SHT_MIPS_LIBLIST. */ -+ -+typedef struct -+{ -+ Elf32_Word l_name; /* Name (string table index) */ -+ Elf32_Word l_time_stamp; /* Timestamp */ -+ Elf32_Word l_checksum; /* Checksum */ -+ Elf32_Word l_version; /* Interface version */ -+ Elf32_Word l_flags; /* Flags */ -+} Elf32_Lib; -+ -+typedef struct -+{ -+ Elf64_Word l_name; /* Name (string table index) */ -+ Elf64_Word l_time_stamp; /* Timestamp */ -+ Elf64_Word l_checksum; /* Checksum */ -+ Elf64_Word l_version; /* Interface version */ -+ Elf64_Word l_flags; /* Flags */ -+} Elf64_Lib; -+ -+ -+/* Legal values for l_flags. */ -+ -+#define LL_NONE 0 -+#define LL_EXACT_MATCH (1 << 0) /* Require exact match */ -+#define LL_IGNORE_INT_VER (1 << 1) /* Ignore interface version */ -+#define LL_REQUIRE_MINOR (1 << 2) -+#define LL_EXPORTS (1 << 3) -+#define LL_DELAY_LOAD (1 << 4) -+#define LL_DELTA (1 << 5) -+ -+/* Entries found in sections of type SHT_MIPS_CONFLICT. */ -+ -+typedef Elf32_Addr Elf32_Conflict; -+ -+ -+/* HPPA specific definitions. */ -+ -+/* Legal values for e_flags field of Elf32_Ehdr. */ -+ -+#define EF_PARISC_TRAPNIL 0x00010000 /* Trap nil pointer dereference. */ -+#define EF_PARISC_EXT 0x00020000 /* Program uses arch. extensions. */ -+#define EF_PARISC_LSB 0x00040000 /* Program expects little endian. */ -+#define EF_PARISC_WIDE 0x00080000 /* Program expects wide mode. */ -+#define EF_PARISC_NO_KABP 0x00100000 /* No kernel assisted branch -+ prediction. */ -+#define EF_PARISC_LAZYSWAP 0x00400000 /* Allow lazy swapping. */ -+#define EF_PARISC_ARCH 0x0000ffff /* Architecture version. */ -+ -+/* Defined values for `e_flags & EF_PARISC_ARCH' are: */ -+ -+#define EFA_PARISC_1_0 0x020b /* PA-RISC 1.0 big-endian. */ -+#define EFA_PARISC_1_1 0x0210 /* PA-RISC 1.1 big-endian. */ -+#define EFA_PARISC_2_0 0x0214 /* PA-RISC 2.0 big-endian. */ -+ -+/* Additional section indeces. */ -+ -+#define SHN_PARISC_ANSI_COMMON 0xff00 /* Section for tenatively declared -+ symbols in ANSI C. */ -+#define SHN_PARISC_HUGE_COMMON 0xff01 /* Common blocks in huge model. */ -+ -+/* Legal values for sh_type field of Elf32_Shdr. */ -+ -+#define SHT_PARISC_EXT 0x70000000 /* Contains product specific ext. */ -+#define SHT_PARISC_UNWIND 0x70000001 /* Unwind information. */ -+#define SHT_PARISC_DOC 0x70000002 /* Debug info for optimized code. */ -+ -+/* Legal values for sh_flags field of Elf32_Shdr. */ -+ -+#define SHF_PARISC_SHORT 0x20000000 /* Section with short addressing. */ -+#define SHF_PARISC_HUGE 0x40000000 /* Section far from gp. */ -+#define SHF_PARISC_SBP 0x80000000 /* Static branch prediction code. */ -+ -+/* Legal values for ST_TYPE subfield of st_info (symbol type). */ -+ -+#define STT_PARISC_MILLICODE 13 /* Millicode function entry point. */ -+ -+#define STT_HP_OPAQUE (STT_LOOS + 0x1) -+#define STT_HP_STUB (STT_LOOS + 0x2) -+ -+/* HPPA relocs. */ -+ -+#define R_PARISC_NONE 0 /* No reloc. */ -+#define R_PARISC_DIR32 1 /* Direct 32-bit reference. */ -+#define R_PARISC_DIR21L 2 /* Left 21 bits of eff. address. */ -+#define R_PARISC_DIR17R 3 /* Right 17 bits of eff. address. */ -+#define R_PARISC_DIR17F 4 /* 17 bits of eff. address. */ -+#define R_PARISC_DIR14R 6 /* Right 14 bits of eff. address. */ -+#define R_PARISC_PCREL32 9 /* 32-bit rel. address. */ -+#define R_PARISC_PCREL21L 10 /* Left 21 bits of rel. address. */ -+#define R_PARISC_PCREL17R 11 /* Right 17 bits of rel. address. */ -+#define R_PARISC_PCREL17F 12 /* 17 bits of rel. address. */ -+#define R_PARISC_PCREL14R 14 /* Right 14 bits of rel. address. */ -+#define R_PARISC_DPREL21L 18 /* Left 21 bits of rel. address. */ -+#define R_PARISC_DPREL14R 22 /* Right 14 bits of rel. address. */ -+#define R_PARISC_GPREL21L 26 /* GP-relative, left 21 bits. */ -+#define R_PARISC_GPREL14R 30 /* GP-relative, right 14 bits. */ -+#define R_PARISC_LTOFF21L 34 /* LT-relative, left 21 bits. */ -+#define R_PARISC_LTOFF14R 38 /* LT-relative, right 14 bits. */ -+#define R_PARISC_SECREL32 41 /* 32 bits section rel. address. */ -+#define R_PARISC_SEGBASE 48 /* No relocation, set segment base. */ -+#define R_PARISC_SEGREL32 49 /* 32 bits segment rel. address. */ -+#define R_PARISC_PLTOFF21L 50 /* PLT rel. address, left 21 bits. */ -+#define R_PARISC_PLTOFF14R 54 /* PLT rel. address, right 14 bits. */ -+#define R_PARISC_LTOFF_FPTR32 57 /* 32 bits LT-rel. function pointer. */ -+#define R_PARISC_LTOFF_FPTR21L 58 /* LT-rel. fct ptr, left 21 bits. */ -+#define R_PARISC_LTOFF_FPTR14R 62 /* LT-rel. fct ptr, right 14 bits. */ -+#define R_PARISC_FPTR64 64 /* 64 bits function address. */ -+#define R_PARISC_PLABEL32 65 /* 32 bits function address. */ -+#define R_PARISC_PCREL64 72 /* 64 bits PC-rel. address. */ -+#define R_PARISC_PCREL22F 74 /* 22 bits PC-rel. address. */ -+#define R_PARISC_PCREL14WR 75 /* PC-rel. address, right 14 bits. */ -+#define R_PARISC_PCREL14DR 76 /* PC rel. address, right 14 bits. */ -+#define R_PARISC_PCREL16F 77 /* 16 bits PC-rel. address. */ -+#define R_PARISC_PCREL16WF 78 /* 16 bits PC-rel. address. */ -+#define R_PARISC_PCREL16DF 79 /* 16 bits PC-rel. address. */ -+#define R_PARISC_DIR64 80 /* 64 bits of eff. address. */ -+#define R_PARISC_DIR14WR 83 /* 14 bits of eff. address. */ -+#define R_PARISC_DIR14DR 84 /* 14 bits of eff. address. */ -+#define R_PARISC_DIR16F 85 /* 16 bits of eff. address. */ -+#define R_PARISC_DIR16WF 86 /* 16 bits of eff. address. */ -+#define R_PARISC_DIR16DF 87 /* 16 bits of eff. address. */ -+#define R_PARISC_GPREL64 88 /* 64 bits of GP-rel. address. */ -+#define R_PARISC_GPREL14WR 91 /* GP-rel. address, right 14 bits. */ -+#define R_PARISC_GPREL14DR 92 /* GP-rel. address, right 14 bits. */ -+#define R_PARISC_GPREL16F 93 /* 16 bits GP-rel. address. */ -+#define R_PARISC_GPREL16WF 94 /* 16 bits GP-rel. address. */ -+#define R_PARISC_GPREL16DF 95 /* 16 bits GP-rel. address. */ -+#define R_PARISC_LTOFF64 96 /* 64 bits LT-rel. address. */ -+#define R_PARISC_LTOFF14WR 99 /* LT-rel. address, right 14 bits. */ -+#define R_PARISC_LTOFF14DR 100 /* LT-rel. address, right 14 bits. */ -+#define R_PARISC_LTOFF16F 101 /* 16 bits LT-rel. address. */ -+#define R_PARISC_LTOFF16WF 102 /* 16 bits LT-rel. address. */ -+#define R_PARISC_LTOFF16DF 103 /* 16 bits LT-rel. address. */ -+#define R_PARISC_SECREL64 104 /* 64 bits section rel. address. */ -+#define R_PARISC_SEGREL64 112 /* 64 bits segment rel. address. */ -+#define R_PARISC_PLTOFF14WR 115 /* PLT-rel. address, right 14 bits. */ -+#define R_PARISC_PLTOFF14DR 116 /* PLT-rel. address, right 14 bits. */ -+#define R_PARISC_PLTOFF16F 117 /* 16 bits LT-rel. address. */ -+#define R_PARISC_PLTOFF16WF 118 /* 16 bits PLT-rel. address. */ -+#define R_PARISC_PLTOFF16DF 119 /* 16 bits PLT-rel. address. */ -+#define R_PARISC_LTOFF_FPTR64 120 /* 64 bits LT-rel. function ptr. */ -+#define R_PARISC_LTOFF_FPTR14WR 123 /* LT-rel. fct. ptr., right 14 bits. */ -+#define R_PARISC_LTOFF_FPTR14DR 124 /* LT-rel. fct. ptr., right 14 bits. */ -+#define R_PARISC_LTOFF_FPTR16F 125 /* 16 bits LT-rel. function ptr. */ -+#define R_PARISC_LTOFF_FPTR16WF 126 /* 16 bits LT-rel. function ptr. */ -+#define R_PARISC_LTOFF_FPTR16DF 127 /* 16 bits LT-rel. function ptr. */ -+#define R_PARISC_LORESERVE 128 -+#define R_PARISC_COPY 128 /* Copy relocation. */ -+#define R_PARISC_IPLT 129 /* Dynamic reloc, imported PLT */ -+#define R_PARISC_EPLT 130 /* Dynamic reloc, exported PLT */ -+#define R_PARISC_TPREL32 153 /* 32 bits TP-rel. address. */ -+#define R_PARISC_TPREL21L 154 /* TP-rel. address, left 21 bits. */ -+#define R_PARISC_TPREL14R 158 /* TP-rel. address, right 14 bits. */ -+#define R_PARISC_LTOFF_TP21L 162 /* LT-TP-rel. address, left 21 bits. */ -+#define R_PARISC_LTOFF_TP14R 166 /* LT-TP-rel. address, right 14 bits.*/ -+#define R_PARISC_LTOFF_TP14F 167 /* 14 bits LT-TP-rel. address. */ -+#define R_PARISC_TPREL64 216 /* 64 bits TP-rel. address. */ -+#define R_PARISC_TPREL14WR 219 /* TP-rel. address, right 14 bits. */ -+#define R_PARISC_TPREL14DR 220 /* TP-rel. address, right 14 bits. */ -+#define R_PARISC_TPREL16F 221 /* 16 bits TP-rel. address. */ -+#define R_PARISC_TPREL16WF 222 /* 16 bits TP-rel. address. */ -+#define R_PARISC_TPREL16DF 223 /* 16 bits TP-rel. address. */ -+#define R_PARISC_LTOFF_TP64 224 /* 64 bits LT-TP-rel. address. */ -+#define R_PARISC_LTOFF_TP14WR 227 /* LT-TP-rel. address, right 14 bits.*/ -+#define R_PARISC_LTOFF_TP14DR 228 /* LT-TP-rel. address, right 14 bits.*/ -+#define R_PARISC_LTOFF_TP16F 229 /* 16 bits LT-TP-rel. address. */ -+#define R_PARISC_LTOFF_TP16WF 230 /* 16 bits LT-TP-rel. address. */ -+#define R_PARISC_LTOFF_TP16DF 231 /* 16 bits LT-TP-rel. address. */ -+#define R_PARISC_HIRESERVE 255 -+ -+/* Legal values for p_type field of Elf32_Phdr/Elf64_Phdr. */ -+ -+#define PT_HP_TLS (PT_LOOS + 0x0) -+#define PT_HP_CORE_NONE (PT_LOOS + 0x1) -+#define PT_HP_CORE_VERSION (PT_LOOS + 0x2) -+#define PT_HP_CORE_KERNEL (PT_LOOS + 0x3) -+#define PT_HP_CORE_COMM (PT_LOOS + 0x4) -+#define PT_HP_CORE_PROC (PT_LOOS + 0x5) -+#define PT_HP_CORE_LOADABLE (PT_LOOS + 0x6) -+#define PT_HP_CORE_STACK (PT_LOOS + 0x7) -+#define PT_HP_CORE_SHM (PT_LOOS + 0x8) -+#define PT_HP_CORE_MMF (PT_LOOS + 0x9) -+#define PT_HP_PARALLEL (PT_LOOS + 0x10) -+#define PT_HP_FASTBIND (PT_LOOS + 0x11) -+#define PT_HP_OPT_ANNOT (PT_LOOS + 0x12) -+#define PT_HP_HSL_ANNOT (PT_LOOS + 0x13) -+#define PT_HP_STACK (PT_LOOS + 0x14) -+ -+#define PT_PARISC_ARCHEXT 0x70000000 -+#define PT_PARISC_UNWIND 0x70000001 -+ -+/* Legal values for p_flags field of Elf32_Phdr/Elf64_Phdr. */ -+ -+#define PF_PARISC_SBP 0x08000000 -+ -+#define PF_HP_PAGE_SIZE 0x00100000 -+#define PF_HP_FAR_SHARED 0x00200000 -+#define PF_HP_NEAR_SHARED 0x00400000 -+#define PF_HP_CODE 0x01000000 -+#define PF_HP_MODIFY 0x02000000 -+#define PF_HP_LAZYSWAP 0x04000000 -+#define PF_HP_SBP 0x08000000 -+ -+ -+/* Alpha specific definitions. */ -+ -+/* Legal values for e_flags field of Elf64_Ehdr. */ -+ -+#define EF_ALPHA_32BIT 1 /* All addresses must be < 2GB. */ -+#define EF_ALPHA_CANRELAX 2 /* Relocations for relaxing exist. */ -+ -+/* Legal values for sh_type field of Elf64_Shdr. */ -+ -+/* These two are primerily concerned with ECOFF debugging info. */ -+#define SHT_ALPHA_DEBUG 0x70000001 -+#define SHT_ALPHA_REGINFO 0x70000002 -+ -+/* Legal values for sh_flags field of Elf64_Shdr. */ -+ -+#define SHF_ALPHA_GPREL 0x10000000 -+ -+/* Legal values for st_other field of Elf64_Sym. */ -+#define STO_ALPHA_NOPV 0x80 /* No PV required. */ -+#define STO_ALPHA_STD_GPLOAD 0x88 /* PV only used for initial ldgp. */ -+ -+/* Alpha relocs. */ -+ -+#define R_ALPHA_NONE 0 /* No reloc */ -+#define R_ALPHA_REFLONG 1 /* Direct 32 bit */ -+#define R_ALPHA_REFQUAD 2 /* Direct 64 bit */ -+#define R_ALPHA_GPREL32 3 /* GP relative 32 bit */ -+#define R_ALPHA_LITERAL 4 /* GP relative 16 bit w/optimization */ -+#define R_ALPHA_LITUSE 5 /* Optimization hint for LITERAL */ -+#define R_ALPHA_GPDISP 6 /* Add displacement to GP */ -+#define R_ALPHA_BRADDR 7 /* PC+4 relative 23 bit shifted */ -+#define R_ALPHA_HINT 8 /* PC+4 relative 16 bit shifted */ -+#define R_ALPHA_SREL16 9 /* PC relative 16 bit */ -+#define R_ALPHA_SREL32 10 /* PC relative 32 bit */ -+#define R_ALPHA_SREL64 11 /* PC relative 64 bit */ -+#define R_ALPHA_GPRELHIGH 17 /* GP relative 32 bit, high 16 bits */ -+#define R_ALPHA_GPRELLOW 18 /* GP relative 32 bit, low 16 bits */ -+#define R_ALPHA_GPREL16 19 /* GP relative 16 bit */ -+#define R_ALPHA_COPY 24 /* Copy symbol at runtime */ -+#define R_ALPHA_GLOB_DAT 25 /* Create GOT entry */ -+#define R_ALPHA_JMP_SLOT 26 /* Create PLT entry */ -+#define R_ALPHA_RELATIVE 27 /* Adjust by program base */ -+#define R_ALPHA_TLS_GD_HI 28 -+#define R_ALPHA_TLSGD 29 -+#define R_ALPHA_TLS_LDM 30 -+#define R_ALPHA_DTPMOD64 31 -+#define R_ALPHA_GOTDTPREL 32 -+#define R_ALPHA_DTPREL64 33 -+#define R_ALPHA_DTPRELHI 34 -+#define R_ALPHA_DTPRELLO 35 -+#define R_ALPHA_DTPREL16 36 -+#define R_ALPHA_GOTTPREL 37 -+#define R_ALPHA_TPREL64 38 -+#define R_ALPHA_TPRELHI 39 -+#define R_ALPHA_TPRELLO 40 -+#define R_ALPHA_TPREL16 41 -+/* Keep this the last entry. */ -+#define R_ALPHA_NUM 46 -+ -+/* Magic values of the LITUSE relocation addend. */ -+#define LITUSE_ALPHA_ADDR 0 -+#define LITUSE_ALPHA_BASE 1 -+#define LITUSE_ALPHA_BYTOFF 2 -+#define LITUSE_ALPHA_JSR 3 -+#define LITUSE_ALPHA_TLS_GD 4 -+#define LITUSE_ALPHA_TLS_LDM 5 -+ -+ -+/* PowerPC specific declarations */ -+ -+/* Values for Elf32/64_Ehdr.e_flags. */ -+#define EF_PPC_EMB 0x80000000 /* PowerPC embedded flag */ -+ -+/* Cygnus local bits below */ -+#define EF_PPC_RELOCATABLE 0x00010000 /* PowerPC -mrelocatable flag*/ -+#define EF_PPC_RELOCATABLE_LIB 0x00008000 /* PowerPC -mrelocatable-lib -+ flag */ -+ -+/* PowerPC relocations defined by the ABIs */ -+#define R_PPC_NONE 0 -+#define R_PPC_ADDR32 1 /* 32bit absolute address */ -+#define R_PPC_ADDR24 2 /* 26bit address, 2 bits ignored. */ -+#define R_PPC_ADDR16 3 /* 16bit absolute address */ -+#define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */ -+#define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */ -+#define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */ -+#define R_PPC_ADDR14 7 /* 16bit address, 2 bits ignored */ -+#define R_PPC_ADDR14_BRTAKEN 8 -+#define R_PPC_ADDR14_BRNTAKEN 9 -+#define R_PPC_REL24 10 /* PC relative 26 bit */ -+#define R_PPC_REL14 11 /* PC relative 16 bit */ -+#define R_PPC_REL14_BRTAKEN 12 -+#define R_PPC_REL14_BRNTAKEN 13 -+#define R_PPC_GOT16 14 -+#define R_PPC_GOT16_LO 15 -+#define R_PPC_GOT16_HI 16 -+#define R_PPC_GOT16_HA 17 -+#define R_PPC_PLTREL24 18 -+#define R_PPC_COPY 19 -+#define R_PPC_GLOB_DAT 20 -+#define R_PPC_JMP_SLOT 21 -+#define R_PPC_RELATIVE 22 -+#define R_PPC_LOCAL24PC 23 -+#define R_PPC_UADDR32 24 -+#define R_PPC_UADDR16 25 -+#define R_PPC_REL32 26 -+#define R_PPC_PLT32 27 -+#define R_PPC_PLTREL32 28 -+#define R_PPC_PLT16_LO 29 -+#define R_PPC_PLT16_HI 30 -+#define R_PPC_PLT16_HA 31 -+#define R_PPC_SDAREL16 32 -+#define R_PPC_SECTOFF 33 -+#define R_PPC_SECTOFF_LO 34 -+#define R_PPC_SECTOFF_HI 35 -+#define R_PPC_SECTOFF_HA 36 -+ -+/* PowerPC relocations defined for the TLS access ABI. */ -+#define R_PPC_TLS 67 /* none (sym+add)@tls */ -+#define R_PPC_DTPMOD32 68 /* word32 (sym+add)@dtpmod */ -+#define R_PPC_TPREL16 69 /* half16* (sym+add)@tprel */ -+#define R_PPC_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */ -+#define R_PPC_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */ -+#define R_PPC_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */ -+#define R_PPC_TPREL32 73 /* word32 (sym+add)@tprel */ -+#define R_PPC_DTPREL16 74 /* half16* (sym+add)@dtprel */ -+#define R_PPC_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */ -+#define R_PPC_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */ -+#define R_PPC_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */ -+#define R_PPC_DTPREL32 78 /* word32 (sym+add)@dtprel */ -+#define R_PPC_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */ -+#define R_PPC_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */ -+#define R_PPC_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */ -+#define R_PPC_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */ -+#define R_PPC_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */ -+#define R_PPC_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */ -+#define R_PPC_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */ -+#define R_PPC_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */ -+#define R_PPC_GOT_TPREL16 87 /* half16* (sym+add)@got@tprel */ -+#define R_PPC_GOT_TPREL16_LO 88 /* half16 (sym+add)@got@tprel@l */ -+#define R_PPC_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */ -+#define R_PPC_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */ -+#define R_PPC_GOT_DTPREL16 91 /* half16* (sym+add)@got@dtprel */ -+#define R_PPC_GOT_DTPREL16_LO 92 /* half16* (sym+add)@got@dtprel@l */ -+#define R_PPC_GOT_DTPREL16_HI 93 /* half16* (sym+add)@got@dtprel@h */ -+#define R_PPC_GOT_DTPREL16_HA 94 /* half16* (sym+add)@got@dtprel@ha */ -+ -+/* Keep this the last entry. */ -+#define R_PPC_NUM 95 -+ -+/* The remaining relocs are from the Embedded ELF ABI, and are not -+ in the SVR4 ELF ABI. */ -+#define R_PPC_EMB_NADDR32 101 -+#define R_PPC_EMB_NADDR16 102 -+#define R_PPC_EMB_NADDR16_LO 103 -+#define R_PPC_EMB_NADDR16_HI 104 -+#define R_PPC_EMB_NADDR16_HA 105 -+#define R_PPC_EMB_SDAI16 106 -+#define R_PPC_EMB_SDA2I16 107 -+#define R_PPC_EMB_SDA2REL 108 -+#define R_PPC_EMB_SDA21 109 /* 16 bit offset in SDA */ -+#define R_PPC_EMB_MRKREF 110 -+#define R_PPC_EMB_RELSEC16 111 -+#define R_PPC_EMB_RELST_LO 112 -+#define R_PPC_EMB_RELST_HI 113 -+#define R_PPC_EMB_RELST_HA 114 -+#define R_PPC_EMB_BIT_FLD 115 -+#define R_PPC_EMB_RELSDA 116 /* 16 bit relative offset in SDA */ -+ -+/* Diab tool relocations. */ -+#define R_PPC_DIAB_SDA21_LO 180 /* like EMB_SDA21, but lower 16 bit */ -+#define R_PPC_DIAB_SDA21_HI 181 /* like EMB_SDA21, but high 16 bit */ -+#define R_PPC_DIAB_SDA21_HA 182 /* like EMB_SDA21, adjusted high 16 */ -+#define R_PPC_DIAB_RELSDA_LO 183 /* like EMB_RELSDA, but lower 16 bit */ -+#define R_PPC_DIAB_RELSDA_HI 184 /* like EMB_RELSDA, but high 16 bit */ -+#define R_PPC_DIAB_RELSDA_HA 185 /* like EMB_RELSDA, adjusted high 16 */ -+ -+/* This is a phony reloc to handle any old fashioned TOC16 references -+ that may still be in object files. */ -+#define R_PPC_TOC16 255 -+ -+ -+/* PowerPC64 relocations defined by the ABIs */ -+#define R_PPC64_NONE R_PPC_NONE -+#define R_PPC64_ADDR32 R_PPC_ADDR32 /* 32bit absolute address */ -+#define R_PPC64_ADDR24 R_PPC_ADDR24 /* 26bit address, word aligned */ -+#define R_PPC64_ADDR16 R_PPC_ADDR16 /* 16bit absolute address */ -+#define R_PPC64_ADDR16_LO R_PPC_ADDR16_LO /* lower 16bits of address */ -+#define R_PPC64_ADDR16_HI R_PPC_ADDR16_HI /* high 16bits of address. */ -+#define R_PPC64_ADDR16_HA R_PPC_ADDR16_HA /* adjusted high 16bits. */ -+#define R_PPC64_ADDR14 R_PPC_ADDR14 /* 16bit address, word aligned */ -+#define R_PPC64_ADDR14_BRTAKEN R_PPC_ADDR14_BRTAKEN -+#define R_PPC64_ADDR14_BRNTAKEN R_PPC_ADDR14_BRNTAKEN -+#define R_PPC64_REL24 R_PPC_REL24 /* PC-rel. 26 bit, word aligned */ -+#define R_PPC64_REL14 R_PPC_REL14 /* PC relative 16 bit */ -+#define R_PPC64_REL14_BRTAKEN R_PPC_REL14_BRTAKEN -+#define R_PPC64_REL14_BRNTAKEN R_PPC_REL14_BRNTAKEN -+#define R_PPC64_GOT16 R_PPC_GOT16 -+#define R_PPC64_GOT16_LO R_PPC_GOT16_LO -+#define R_PPC64_GOT16_HI R_PPC_GOT16_HI -+#define R_PPC64_GOT16_HA R_PPC_GOT16_HA -+ -+#define R_PPC64_COPY R_PPC_COPY -+#define R_PPC64_GLOB_DAT R_PPC_GLOB_DAT -+#define R_PPC64_JMP_SLOT R_PPC_JMP_SLOT -+#define R_PPC64_RELATIVE R_PPC_RELATIVE -+ -+#define R_PPC64_UADDR32 R_PPC_UADDR32 -+#define R_PPC64_UADDR16 R_PPC_UADDR16 -+#define R_PPC64_REL32 R_PPC_REL32 -+#define R_PPC64_PLT32 R_PPC_PLT32 -+#define R_PPC64_PLTREL32 R_PPC_PLTREL32 -+#define R_PPC64_PLT16_LO R_PPC_PLT16_LO -+#define R_PPC64_PLT16_HI R_PPC_PLT16_HI -+#define R_PPC64_PLT16_HA R_PPC_PLT16_HA -+ -+#define R_PPC64_SECTOFF R_PPC_SECTOFF -+#define R_PPC64_SECTOFF_LO R_PPC_SECTOFF_LO -+#define R_PPC64_SECTOFF_HI R_PPC_SECTOFF_HI -+#define R_PPC64_SECTOFF_HA R_PPC_SECTOFF_HA -+#define R_PPC64_ADDR30 37 /* word30 (S + A - P) >> 2 */ -+#define R_PPC64_ADDR64 38 /* doubleword64 S + A */ -+#define R_PPC64_ADDR16_HIGHER 39 /* half16 #higher(S + A) */ -+#define R_PPC64_ADDR16_HIGHERA 40 /* half16 #highera(S + A) */ -+#define R_PPC64_ADDR16_HIGHEST 41 /* half16 #highest(S + A) */ -+#define R_PPC64_ADDR16_HIGHESTA 42 /* half16 #highesta(S + A) */ -+#define R_PPC64_UADDR64 43 /* doubleword64 S + A */ -+#define R_PPC64_REL64 44 /* doubleword64 S + A - P */ -+#define R_PPC64_PLT64 45 /* doubleword64 L + A */ -+#define R_PPC64_PLTREL64 46 /* doubleword64 L + A - P */ -+#define R_PPC64_TOC16 47 /* half16* S + A - .TOC */ -+#define R_PPC64_TOC16_LO 48 /* half16 #lo(S + A - .TOC.) */ -+#define R_PPC64_TOC16_HI 49 /* half16 #hi(S + A - .TOC.) */ -+#define R_PPC64_TOC16_HA 50 /* half16 #ha(S + A - .TOC.) */ -+#define R_PPC64_TOC 51 /* doubleword64 .TOC */ -+#define R_PPC64_PLTGOT16 52 /* half16* M + A */ -+#define R_PPC64_PLTGOT16_LO 53 /* half16 #lo(M + A) */ -+#define R_PPC64_PLTGOT16_HI 54 /* half16 #hi(M + A) */ -+#define R_PPC64_PLTGOT16_HA 55 /* half16 #ha(M + A) */ -+ -+#define R_PPC64_ADDR16_DS 56 /* half16ds* (S + A) >> 2 */ -+#define R_PPC64_ADDR16_LO_DS 57 /* half16ds #lo(S + A) >> 2 */ -+#define R_PPC64_GOT16_DS 58 /* half16ds* (G + A) >> 2 */ -+#define R_PPC64_GOT16_LO_DS 59 /* half16ds #lo(G + A) >> 2 */ -+#define R_PPC64_PLT16_LO_DS 60 /* half16ds #lo(L + A) >> 2 */ -+#define R_PPC64_SECTOFF_DS 61 /* half16ds* (R + A) >> 2 */ -+#define R_PPC64_SECTOFF_LO_DS 62 /* half16ds #lo(R + A) >> 2 */ -+#define R_PPC64_TOC16_DS 63 /* half16ds* (S + A - .TOC.) >> 2 */ -+#define R_PPC64_TOC16_LO_DS 64 /* half16ds #lo(S + A - .TOC.) >> 2 */ -+#define R_PPC64_PLTGOT16_DS 65 /* half16ds* (M + A) >> 2 */ -+#define R_PPC64_PLTGOT16_LO_DS 66 /* half16ds #lo(M + A) >> 2 */ -+ -+/* PowerPC64 relocations defined for the TLS access ABI. */ -+#define R_PPC64_TLS 67 /* none (sym+add)@tls */ -+#define R_PPC64_DTPMOD64 68 /* doubleword64 (sym+add)@dtpmod */ -+#define R_PPC64_TPREL16 69 /* half16* (sym+add)@tprel */ -+#define R_PPC64_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */ -+#define R_PPC64_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */ -+#define R_PPC64_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */ -+#define R_PPC64_TPREL64 73 /* doubleword64 (sym+add)@tprel */ -+#define R_PPC64_DTPREL16 74 /* half16* (sym+add)@dtprel */ -+#define R_PPC64_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */ -+#define R_PPC64_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */ -+#define R_PPC64_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */ -+#define R_PPC64_DTPREL64 78 /* doubleword64 (sym+add)@dtprel */ -+#define R_PPC64_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */ -+#define R_PPC64_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */ -+#define R_PPC64_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */ -+#define R_PPC64_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */ -+#define R_PPC64_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */ -+#define R_PPC64_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */ -+#define R_PPC64_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */ -+#define R_PPC64_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */ -+#define R_PPC64_GOT_TPREL16_DS 87 /* half16ds* (sym+add)@got@tprel */ -+#define R_PPC64_GOT_TPREL16_LO_DS 88 /* half16ds (sym+add)@got@tprel@l */ -+#define R_PPC64_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */ -+#define R_PPC64_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */ -+#define R_PPC64_GOT_DTPREL16_DS 91 /* half16ds* (sym+add)@got@dtprel */ -+#define R_PPC64_GOT_DTPREL16_LO_DS 92 /* half16ds (sym+add)@got@dtprel@l */ -+#define R_PPC64_GOT_DTPREL16_HI 93 /* half16 (sym+add)@got@dtprel@h */ -+#define R_PPC64_GOT_DTPREL16_HA 94 /* half16 (sym+add)@got@dtprel@ha */ -+#define R_PPC64_TPREL16_DS 95 /* half16ds* (sym+add)@tprel */ -+#define R_PPC64_TPREL16_LO_DS 96 /* half16ds (sym+add)@tprel@l */ -+#define R_PPC64_TPREL16_HIGHER 97 /* half16 (sym+add)@tprel@higher */ -+#define R_PPC64_TPREL16_HIGHERA 98 /* half16 (sym+add)@tprel@highera */ -+#define R_PPC64_TPREL16_HIGHEST 99 /* half16 (sym+add)@tprel@highest */ -+#define R_PPC64_TPREL16_HIGHESTA 100 /* half16 (sym+add)@tprel@highesta */ -+#define R_PPC64_DTPREL16_DS 101 /* half16ds* (sym+add)@dtprel */ -+#define R_PPC64_DTPREL16_LO_DS 102 /* half16ds (sym+add)@dtprel@l */ -+#define R_PPC64_DTPREL16_HIGHER 103 /* half16 (sym+add)@dtprel@higher */ -+#define R_PPC64_DTPREL16_HIGHERA 104 /* half16 (sym+add)@dtprel@highera */ -+#define R_PPC64_DTPREL16_HIGHEST 105 /* half16 (sym+add)@dtprel@highest */ -+#define R_PPC64_DTPREL16_HIGHESTA 106 /* half16 (sym+add)@dtprel@highesta */ -+ -+/* Keep this the last entry. */ -+#define R_PPC64_NUM 107 -+ -+/* PowerPC64 specific values for the Dyn d_tag field. */ -+#define DT_PPC64_GLINK (DT_LOPROC + 0) -+#define DT_PPC64_NUM 1 -+ -+ -+/* ARM specific declarations */ -+ -+/* Processor specific flags for the ELF header e_flags field. */ -+#define EF_ARM_RELEXEC 0x01 -+#define EF_ARM_HASENTRY 0x02 -+#define EF_ARM_INTERWORK 0x04 -+#define EF_ARM_APCS_26 0x08 -+#define EF_ARM_APCS_FLOAT 0x10 -+#define EF_ARM_PIC 0x20 -+#define EF_ARM_ALIGN8 0x40 /* 8-bit structure alignment is in use */ -+#define EF_ARM_NEW_ABI 0x80 -+#define EF_ARM_OLD_ABI 0x100 -+ -+/* Other constants defined in the ARM ELF spec. version B-01. */ -+/* NB. These conflict with values defined above. */ -+#define EF_ARM_SYMSARESORTED 0x04 -+#define EF_ARM_DYNSYMSUSESEGIDX 0x08 -+#define EF_ARM_MAPSYMSFIRST 0x10 -+#define EF_ARM_EABIMASK 0XFF000000 -+ -+#define EF_ARM_EABI_VERSION(flags) ((flags) & EF_ARM_EABIMASK) -+#define EF_ARM_EABI_UNKNOWN 0x00000000 -+#define EF_ARM_EABI_VER1 0x01000000 -+#define EF_ARM_EABI_VER2 0x02000000 -+ -+/* Additional symbol types for Thumb */ -+#define STT_ARM_TFUNC 0xd -+ -+/* ARM-specific values for sh_flags */ -+#define SHF_ARM_ENTRYSECT 0x10000000 /* Section contains an entry point */ -+#define SHF_ARM_COMDEF 0x80000000 /* Section may be multiply defined -+ in the input to a link step */ -+ -+/* ARM-specific program header flags */ -+#define PF_ARM_SB 0x10000000 /* Segment contains the location -+ addressed by the static base */ -+ -+/* ARM relocs. */ -+#define R_ARM_NONE 0 /* No reloc */ -+#define R_ARM_PC24 1 /* PC relative 26 bit branch */ -+#define R_ARM_ABS32 2 /* Direct 32 bit */ -+#define R_ARM_REL32 3 /* PC relative 32 bit */ -+#define R_ARM_PC13 4 -+#define R_ARM_ABS16 5 /* Direct 16 bit */ -+#define R_ARM_ABS12 6 /* Direct 12 bit */ -+#define R_ARM_THM_ABS5 7 -+#define R_ARM_ABS8 8 /* Direct 8 bit */ -+#define R_ARM_SBREL32 9 -+#define R_ARM_THM_PC22 10 -+#define R_ARM_THM_PC8 11 -+#define R_ARM_AMP_VCALL9 12 -+#define R_ARM_SWI24 13 -+#define R_ARM_THM_SWI8 14 -+#define R_ARM_XPC25 15 -+#define R_ARM_THM_XPC22 16 -+#define R_ARM_COPY 20 /* Copy symbol at runtime */ -+#define R_ARM_GLOB_DAT 21 /* Create GOT entry */ -+#define R_ARM_JUMP_SLOT 22 /* Create PLT entry */ -+#define R_ARM_RELATIVE 23 /* Adjust by program base */ -+#define R_ARM_GOTOFF 24 /* 32 bit offset to GOT */ -+#define R_ARM_GOTPC 25 /* 32 bit PC relative offset to GOT */ -+#define R_ARM_GOT32 26 /* 32 bit GOT entry */ -+#define R_ARM_PLT32 27 /* 32 bit PLT address */ -+#define R_ARM_ALU_PCREL_7_0 32 -+#define R_ARM_ALU_PCREL_15_8 33 -+#define R_ARM_ALU_PCREL_23_15 34 -+#define R_ARM_LDR_SBREL_11_0 35 -+#define R_ARM_ALU_SBREL_19_12 36 -+#define R_ARM_ALU_SBREL_27_20 37 -+#define R_ARM_GNU_VTENTRY 100 -+#define R_ARM_GNU_VTINHERIT 101 -+#define R_ARM_THM_PC11 102 /* thumb unconditional branch */ -+#define R_ARM_THM_PC9 103 /* thumb conditional branch */ -+#define R_ARM_RXPC25 249 -+#define R_ARM_RSBREL32 250 -+#define R_ARM_THM_RPC22 251 -+#define R_ARM_RREL32 252 -+#define R_ARM_RABS22 253 -+#define R_ARM_RPC24 254 -+#define R_ARM_RBASE 255 -+/* Keep this the last entry. */ -+#define R_ARM_NUM 256 -+ -+/* IA-64 specific declarations. */ -+ -+/* Processor specific flags for the Ehdr e_flags field. */ -+#define EF_IA_64_MASKOS 0x0000000f /* os-specific flags */ -+#define EF_IA_64_ABI64 0x00000010 /* 64-bit ABI */ -+#define EF_IA_64_ARCH 0xff000000 /* arch. version mask */ -+ -+/* Processor specific values for the Phdr p_type field. */ -+#define PT_IA_64_ARCHEXT (PT_LOPROC + 0) /* arch extension bits */ -+#define PT_IA_64_UNWIND (PT_LOPROC + 1) /* ia64 unwind bits */ -+ -+/* Processor specific flags for the Phdr p_flags field. */ -+#define PF_IA_64_NORECOV 0x80000000 /* spec insns w/o recovery */ -+ -+/* Processor specific values for the Shdr sh_type field. */ -+#define SHT_IA_64_EXT (SHT_LOPROC + 0) /* extension bits */ -+#define SHT_IA_64_UNWIND (SHT_LOPROC + 1) /* unwind bits */ -+ -+/* Processor specific flags for the Shdr sh_flags field. */ -+#define SHF_IA_64_SHORT 0x10000000 /* section near gp */ -+#define SHF_IA_64_NORECOV 0x20000000 /* spec insns w/o recovery */ -+ -+/* Processor specific values for the Dyn d_tag field. */ -+#define DT_IA_64_PLT_RESERVE (DT_LOPROC + 0) -+#define DT_IA_64_NUM 1 -+ -+/* IA-64 relocations. */ -+#define R_IA64_NONE 0x00 /* none */ -+#define R_IA64_IMM14 0x21 /* symbol + addend, add imm14 */ -+#define R_IA64_IMM22 0x22 /* symbol + addend, add imm22 */ -+#define R_IA64_IMM64 0x23 /* symbol + addend, mov imm64 */ -+#define R_IA64_DIR32MSB 0x24 /* symbol + addend, data4 MSB */ -+#define R_IA64_DIR32LSB 0x25 /* symbol + addend, data4 LSB */ -+#define R_IA64_DIR64MSB 0x26 /* symbol + addend, data8 MSB */ -+#define R_IA64_DIR64LSB 0x27 /* symbol + addend, data8 LSB */ -+#define R_IA64_GPREL22 0x2a /* @gprel(sym + add), add imm22 */ -+#define R_IA64_GPREL64I 0x2b /* @gprel(sym + add), mov imm64 */ -+#define R_IA64_GPREL32MSB 0x2c /* @gprel(sym + add), data4 MSB */ -+#define R_IA64_GPREL32LSB 0x2d /* @gprel(sym + add), data4 LSB */ -+#define R_IA64_GPREL64MSB 0x2e /* @gprel(sym + add), data8 MSB */ -+#define R_IA64_GPREL64LSB 0x2f /* @gprel(sym + add), data8 LSB */ -+#define R_IA64_LTOFF22 0x32 /* @ltoff(sym + add), add imm22 */ -+#define R_IA64_LTOFF64I 0x33 /* @ltoff(sym + add), mov imm64 */ -+#define R_IA64_PLTOFF22 0x3a /* @pltoff(sym + add), add imm22 */ -+#define R_IA64_PLTOFF64I 0x3b /* @pltoff(sym + add), mov imm64 */ -+#define R_IA64_PLTOFF64MSB 0x3e /* @pltoff(sym + add), data8 MSB */ -+#define R_IA64_PLTOFF64LSB 0x3f /* @pltoff(sym + add), data8 LSB */ -+#define R_IA64_FPTR64I 0x43 /* @fptr(sym + add), mov imm64 */ -+#define R_IA64_FPTR32MSB 0x44 /* @fptr(sym + add), data4 MSB */ -+#define R_IA64_FPTR32LSB 0x45 /* @fptr(sym + add), data4 LSB */ -+#define R_IA64_FPTR64MSB 0x46 /* @fptr(sym + add), data8 MSB */ -+#define R_IA64_FPTR64LSB 0x47 /* @fptr(sym + add), data8 LSB */ -+#define R_IA64_PCREL60B 0x48 /* @pcrel(sym + add), brl */ -+#define R_IA64_PCREL21B 0x49 /* @pcrel(sym + add), ptb, call */ -+#define R_IA64_PCREL21M 0x4a /* @pcrel(sym + add), chk.s */ -+#define R_IA64_PCREL21F 0x4b /* @pcrel(sym + add), fchkf */ -+#define R_IA64_PCREL32MSB 0x4c /* @pcrel(sym + add), data4 MSB */ -+#define R_IA64_PCREL32LSB 0x4d /* @pcrel(sym + add), data4 LSB */ -+#define R_IA64_PCREL64MSB 0x4e /* @pcrel(sym + add), data8 MSB */ -+#define R_IA64_PCREL64LSB 0x4f /* @pcrel(sym + add), data8 LSB */ -+#define R_IA64_LTOFF_FPTR22 0x52 /* @ltoff(@fptr(s+a)), imm22 */ -+#define R_IA64_LTOFF_FPTR64I 0x53 /* @ltoff(@fptr(s+a)), imm64 */ -+#define R_IA64_LTOFF_FPTR32MSB 0x54 /* @ltoff(@fptr(s+a)), data4 MSB */ -+#define R_IA64_LTOFF_FPTR32LSB 0x55 /* @ltoff(@fptr(s+a)), data4 LSB */ -+#define R_IA64_LTOFF_FPTR64MSB 0x56 /* @ltoff(@fptr(s+a)), data8 MSB */ -+#define R_IA64_LTOFF_FPTR64LSB 0x57 /* @ltoff(@fptr(s+a)), data8 LSB */ -+#define R_IA64_SEGREL32MSB 0x5c /* @segrel(sym + add), data4 MSB */ -+#define R_IA64_SEGREL32LSB 0x5d /* @segrel(sym + add), data4 LSB */ -+#define R_IA64_SEGREL64MSB 0x5e /* @segrel(sym + add), data8 MSB */ -+#define R_IA64_SEGREL64LSB 0x5f /* @segrel(sym + add), data8 LSB */ -+#define R_IA64_SECREL32MSB 0x64 /* @secrel(sym + add), data4 MSB */ -+#define R_IA64_SECREL32LSB 0x65 /* @secrel(sym + add), data4 LSB */ -+#define R_IA64_SECREL64MSB 0x66 /* @secrel(sym + add), data8 MSB */ -+#define R_IA64_SECREL64LSB 0x67 /* @secrel(sym + add), data8 LSB */ -+#define R_IA64_REL32MSB 0x6c /* data 4 + REL */ -+#define R_IA64_REL32LSB 0x6d /* data 4 + REL */ -+#define R_IA64_REL64MSB 0x6e /* data 8 + REL */ -+#define R_IA64_REL64LSB 0x6f /* data 8 + REL */ -+#define R_IA64_LTV32MSB 0x74 /* symbol + addend, data4 MSB */ -+#define R_IA64_LTV32LSB 0x75 /* symbol + addend, data4 LSB */ -+#define R_IA64_LTV64MSB 0x76 /* symbol + addend, data8 MSB */ -+#define R_IA64_LTV64LSB 0x77 /* symbol + addend, data8 LSB */ -+#define R_IA64_PCREL21BI 0x79 /* @pcrel(sym + add), 21bit inst */ -+#define R_IA64_PCREL22 0x7a /* @pcrel(sym + add), 22bit inst */ -+#define R_IA64_PCREL64I 0x7b /* @pcrel(sym + add), 64bit inst */ -+#define R_IA64_IPLTMSB 0x80 /* dynamic reloc, imported PLT, MSB */ -+#define R_IA64_IPLTLSB 0x81 /* dynamic reloc, imported PLT, LSB */ -+#define R_IA64_COPY 0x84 /* copy relocation */ -+#define R_IA64_SUB 0x85 /* Addend and symbol difference */ -+#define R_IA64_LTOFF22X 0x86 /* LTOFF22, relaxable. */ -+#define R_IA64_LDXMOV 0x87 /* Use of LTOFF22X. */ -+#define R_IA64_TPREL14 0x91 /* @tprel(sym + add), imm14 */ -+#define R_IA64_TPREL22 0x92 /* @tprel(sym + add), imm22 */ -+#define R_IA64_TPREL64I 0x93 /* @tprel(sym + add), imm64 */ -+#define R_IA64_TPREL64MSB 0x96 /* @tprel(sym + add), data8 MSB */ -+#define R_IA64_TPREL64LSB 0x97 /* @tprel(sym + add), data8 LSB */ -+#define R_IA64_LTOFF_TPREL22 0x9a /* @ltoff(@tprel(s+a)), imm2 */ -+#define R_IA64_DTPMOD64MSB 0xa6 /* @dtpmod(sym + add), data8 MSB */ -+#define R_IA64_DTPMOD64LSB 0xa7 /* @dtpmod(sym + add), data8 LSB */ -+#define R_IA64_LTOFF_DTPMOD22 0xaa /* @ltoff(@dtpmod(sym + add)), imm22 */ -+#define R_IA64_DTPREL14 0xb1 /* @dtprel(sym + add), imm14 */ -+#define R_IA64_DTPREL22 0xb2 /* @dtprel(sym + add), imm22 */ -+#define R_IA64_DTPREL64I 0xb3 /* @dtprel(sym + add), imm64 */ -+#define R_IA64_DTPREL32MSB 0xb4 /* @dtprel(sym + add), data4 MSB */ -+#define R_IA64_DTPREL32LSB 0xb5 /* @dtprel(sym + add), data4 LSB */ -+#define R_IA64_DTPREL64MSB 0xb6 /* @dtprel(sym + add), data8 MSB */ -+#define R_IA64_DTPREL64LSB 0xb7 /* @dtprel(sym + add), data8 LSB */ -+#define R_IA64_LTOFF_DTPREL22 0xba /* @ltoff(@dtprel(s+a)), imm22 */ -+ -+/* SH specific declarations */ -+ -+/* SH relocs. */ -+#define R_SH_NONE 0 -+#define R_SH_DIR32 1 -+#define R_SH_REL32 2 -+#define R_SH_DIR8WPN 3 -+#define R_SH_IND12W 4 -+#define R_SH_DIR8WPL 5 -+#define R_SH_DIR8WPZ 6 -+#define R_SH_DIR8BP 7 -+#define R_SH_DIR8W 8 -+#define R_SH_DIR8L 9 -+#define R_SH_SWITCH16 25 -+#define R_SH_SWITCH32 26 -+#define R_SH_USES 27 -+#define R_SH_COUNT 28 -+#define R_SH_ALIGN 29 -+#define R_SH_CODE 30 -+#define R_SH_DATA 31 -+#define R_SH_LABEL 32 -+#define R_SH_SWITCH8 33 -+#define R_SH_GNU_VTINHERIT 34 -+#define R_SH_GNU_VTENTRY 35 -+#define R_SH_TLS_GD_32 144 -+#define R_SH_TLS_LD_32 145 -+#define R_SH_TLS_LDO_32 146 -+#define R_SH_TLS_IE_32 147 -+#define R_SH_TLS_LE_32 148 -+#define R_SH_TLS_DTPMOD32 149 -+#define R_SH_TLS_DTPOFF32 150 -+#define R_SH_TLS_TPOFF32 151 -+#define R_SH_GOT32 160 -+#define R_SH_PLT32 161 -+#define R_SH_COPY 162 -+#define R_SH_GLOB_DAT 163 -+#define R_SH_JMP_SLOT 164 -+#define R_SH_RELATIVE 165 -+#define R_SH_GOTOFF 166 -+#define R_SH_GOTPC 167 -+/* Keep this the last entry. */ -+#define R_SH_NUM 256 -+ -+/* Additional s390 relocs */ -+ -+#define R_390_NONE 0 /* No reloc. */ -+#define R_390_8 1 /* Direct 8 bit. */ -+#define R_390_12 2 /* Direct 12 bit. */ -+#define R_390_16 3 /* Direct 16 bit. */ -+#define R_390_32 4 /* Direct 32 bit. */ -+#define R_390_PC32 5 /* PC relative 32 bit. */ -+#define R_390_GOT12 6 /* 12 bit GOT offset. */ -+#define R_390_GOT32 7 /* 32 bit GOT offset. */ -+#define R_390_PLT32 8 /* 32 bit PC relative PLT address. */ -+#define R_390_COPY 9 /* Copy symbol at runtime. */ -+#define R_390_GLOB_DAT 10 /* Create GOT entry. */ -+#define R_390_JMP_SLOT 11 /* Create PLT entry. */ -+#define R_390_RELATIVE 12 /* Adjust by program base. */ -+#define R_390_GOTOFF32 13 /* 32 bit offset to GOT. */ -+#define R_390_GOTPC 14 /* 32 bit PC relative offset to GOT. */ -+#define R_390_GOT16 15 /* 16 bit GOT offset. */ -+#define R_390_PC16 16 /* PC relative 16 bit. */ -+#define R_390_PC16DBL 17 /* PC relative 16 bit shifted by 1. */ -+#define R_390_PLT16DBL 18 /* 16 bit PC rel. PLT shifted by 1. */ -+#define R_390_PC32DBL 19 /* PC relative 32 bit shifted by 1. */ -+#define R_390_PLT32DBL 20 /* 32 bit PC rel. PLT shifted by 1. */ -+#define R_390_GOTPCDBL 21 /* 32 bit PC rel. GOT shifted by 1. */ -+#define R_390_64 22 /* Direct 64 bit. */ -+#define R_390_PC64 23 /* PC relative 64 bit. */ -+#define R_390_GOT64 24 /* 64 bit GOT offset. */ -+#define R_390_PLT64 25 /* 64 bit PC relative PLT address. */ -+#define R_390_GOTENT 26 /* 32 bit PC rel. to GOT entry >> 1. */ -+#define R_390_GOTOFF16 27 /* 16 bit offset to GOT. */ -+#define R_390_GOTOFF64 28 /* 64 bit offset to GOT. */ -+#define R_390_GOTPLT12 29 /* 12 bit offset to jump slot. */ -+#define R_390_GOTPLT16 30 /* 16 bit offset to jump slot. */ -+#define R_390_GOTPLT32 31 /* 32 bit offset to jump slot. */ -+#define R_390_GOTPLT64 32 /* 64 bit offset to jump slot. */ -+#define R_390_GOTPLTENT 33 /* 32 bit rel. offset to jump slot. */ -+#define R_390_PLTOFF16 34 /* 16 bit offset from GOT to PLT. */ -+#define R_390_PLTOFF32 35 /* 32 bit offset from GOT to PLT. */ -+#define R_390_PLTOFF64 36 /* 16 bit offset from GOT to PLT. */ -+#define R_390_TLS_LOAD 37 /* Tag for load insn in TLS code. */ -+#define R_390_TLS_GDCALL 38 /* Tag for function call in general -+ dynamic TLS code. */ -+#define R_390_TLS_LDCALL 39 /* Tag for function call in local -+ dynamic TLS code. */ -+#define R_390_TLS_GD32 40 /* Direct 32 bit for general dynamic -+ thread local data. */ -+#define R_390_TLS_GD64 41 /* Direct 64 bit for general dynamic -+ thread local data. */ -+#define R_390_TLS_GOTIE12 42 /* 12 bit GOT offset for static TLS -+ block offset. */ -+#define R_390_TLS_GOTIE32 43 /* 32 bit GOT offset for static TLS -+ block offset. */ -+#define R_390_TLS_GOTIE64 44 /* 64 bit GOT offset for static TLS -+ block offset. */ -+#define R_390_TLS_LDM32 45 /* Direct 32 bit for local dynamic -+ thread local data in LE code. */ -+#define R_390_TLS_LDM64 46 /* Direct 64 bit for local dynamic -+ thread local data in LE code. */ -+#define R_390_TLS_IE32 47 /* 32 bit address of GOT entry for -+ negated static TLS block offset. */ -+#define R_390_TLS_IE64 48 /* 64 bit address of GOT entry for -+ negated static TLS block offset. */ -+#define R_390_TLS_IEENT 49 /* 32 bit rel. offset to GOT entry for -+ negated static TLS block offset. */ -+#define R_390_TLS_LE32 50 /* 32 bit negated offset relative to -+ static TLS block. */ -+#define R_390_TLS_LE64 51 /* 64 bit negated offset relative to -+ static TLS block. */ -+#define R_390_TLS_LDO32 52 /* 32 bit offset relative to TLS -+ block. */ -+#define R_390_TLS_LDO64 53 /* 64 bit offset relative to TLS -+ block. */ -+#define R_390_TLS_DTPMOD 54 /* ID of module containing symbol. */ -+#define R_390_TLS_DTPOFF 55 /* Offset in TLS block. */ -+#define R_390_TLS_TPOFF 56 /* Negated offset in static TLS -+ block. */ -+ -+/* Keep this the last entry. */ -+#define R_390_NUM 57 -+ -+/* CRIS relocations. */ -+#define R_CRIS_NONE 0 -+#define R_CRIS_8 1 -+#define R_CRIS_16 2 -+#define R_CRIS_32 3 -+#define R_CRIS_8_PCREL 4 -+#define R_CRIS_16_PCREL 5 -+#define R_CRIS_32_PCREL 6 -+#define R_CRIS_GNU_VTINHERIT 7 -+#define R_CRIS_GNU_VTENTRY 8 -+#define R_CRIS_COPY 9 -+#define R_CRIS_GLOB_DAT 10 -+#define R_CRIS_JUMP_SLOT 11 -+#define R_CRIS_RELATIVE 12 -+#define R_CRIS_16_GOT 13 -+#define R_CRIS_32_GOT 14 -+#define R_CRIS_16_GOTPLT 15 -+#define R_CRIS_32_GOTPLT 16 -+#define R_CRIS_32_GOTREL 17 -+#define R_CRIS_32_PLT_GOTREL 18 -+#define R_CRIS_32_PLT_PCREL 19 -+ -+#define R_CRIS_NUM 20 -+ -+/* AMD x86-64 relocations. */ -+#define R_X86_64_NONE 0 /* No reloc */ -+#define R_X86_64_64 1 /* Direct 64 bit */ -+#define R_X86_64_PC32 2 /* PC relative 32 bit signed */ -+#define R_X86_64_GOT32 3 /* 32 bit GOT entry */ -+#define R_X86_64_PLT32 4 /* 32 bit PLT address */ -+#define R_X86_64_COPY 5 /* Copy symbol at runtime */ -+#define R_X86_64_GLOB_DAT 6 /* Create GOT entry */ -+#define R_X86_64_JUMP_SLOT 7 /* Create PLT entry */ -+#define R_X86_64_RELATIVE 8 /* Adjust by program base */ -+#define R_X86_64_GOTPCREL 9 /* 32 bit signed PC relative -+ offset to GOT */ -+#define R_X86_64_32 10 /* Direct 32 bit zero extended */ -+#define R_X86_64_32S 11 /* Direct 32 bit sign extended */ -+#define R_X86_64_16 12 /* Direct 16 bit zero extended */ -+#define R_X86_64_PC16 13 /* 16 bit sign extended pc relative */ -+#define R_X86_64_8 14 /* Direct 8 bit sign extended */ -+#define R_X86_64_PC8 15 /* 8 bit sign extended pc relative */ -+#define R_X86_64_DTPMOD64 16 /* ID of module containing symbol */ -+#define R_X86_64_DTPOFF64 17 /* Offset in module's TLS block */ -+#define R_X86_64_TPOFF64 18 /* Offset in initial TLS block */ -+#define R_X86_64_TLSGD 19 /* 32 bit signed PC relative offset -+ to two GOT entries for GD symbol */ -+#define R_X86_64_TLSLD 20 /* 32 bit signed PC relative offset -+ to two GOT entries for LD symbol */ -+#define R_X86_64_DTPOFF32 21 /* Offset in TLS block */ -+#define R_X86_64_GOTTPOFF 22 /* 32 bit signed PC relative offset -+ to GOT entry for IE symbol */ -+#define R_X86_64_TPOFF32 23 /* Offset in initial TLS block */ -+ -+#define R_X86_64_NUM 24 -+ -+__END_DECLS -+ -+#endif /* elf.h */ - - #include "elfconfig.h" - -@@ -195,3 +2641,4 @@ - void fatal(const char *fmt, ...); - void warn(const char *fmt, ...); - void merror(const char *fmt, ...); -+ -diff -Nur linux-2.6.36.orig/scripts/mod/sumversion.c linux-2.6.36/scripts/mod/sumversion.c ---- linux-2.6.36.orig/scripts/mod/sumversion.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/scripts/mod/sumversion.c 2010-11-28 18:33:24.000000000 +0100 -@@ -1,4 +1,4 @@ --#include -+/* #include */ - #ifdef __sun__ - #include - #else diff --git a/target/linux/patches/2.6.36/cc-abstract.patch b/target/linux/patches/2.6.36/cc-abstract.patch deleted file mode 100644 index dc5d87f0d..000000000 --- a/target/linux/patches/2.6.36/cc-abstract.patch +++ /dev/null @@ -1,14 +0,0 @@ -diff -Nur linux-2.6.32.orig/Makefile linux-2.6.32/Makefile ---- linux-2.6.32.orig/Makefile Thu Dec 3 04:50:57 2009 -+++ linux-2.6.32/Makefile Fri Dec 18 20:53:57 2009 -@@ -219,8 +219,8 @@ - else if [ -x /bin/bash ]; then echo /bin/bash; \ - else echo sh; fi ; fi) - --HOSTCC = gcc --HOSTCXX = g++ -+HOSTCC ?= gcc -+HOSTCXX ?= g++ - HOSTCFLAGS = -Wall -Wmissing-prototypes -Wstrict-prototypes -O2 -fomit-frame-pointer - HOSTCXXFLAGS = -O2 - diff --git a/target/linux/patches/2.6.36/cris.patch b/target/linux/patches/2.6.36/cris.patch deleted file mode 100644 index 6be88fc18..000000000 --- a/target/linux/patches/2.6.36/cris.patch +++ /dev/null @@ -1,5736 +0,0 @@ -diff -Nur linux-2.6.36.orig/arch/cris/Kconfig linux-2.6.36/arch/cris/Kconfig ---- linux-2.6.36.orig/arch/cris/Kconfig 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/arch/cris/Kconfig 2010-12-28 20:35:16.000000000 +0100 -@@ -177,6 +177,12 @@ - help - Size of DRAM (decimal in MB) typically 2, 8 or 16. - -+config ETRAX_MTD_SIZE -+ hex "MTD size (hex)" -+ default "0x00800000" -+ help -+ Size of MTD device typically 4 or 8 MB. -+ - config ETRAX_VMEM_SIZE - int "Video memory size (dec, in MB)" - depends on ETRAX_ARCH_V32 && !ETRAXFS -@@ -282,7 +288,7 @@ - select MTD_CFI_AMDSTD - select MTD_JEDECPROBE if ETRAX_ARCH_V32 - select MTD_CHAR -- select MTD_BLOCK -+ select MTD_BLOCK_RO - select MTD_PARTITIONS - select MTD_CONCAT - select MTD_COMPLEX_MAPPINGS -@@ -671,6 +677,11 @@ - - source "drivers/ide/Kconfig" - -+#mysteriously part of this standard linux driver was removed from cris build! - info@crisos.org -+source "drivers/scsi/Kconfig" -+ -+source "drivers/media/Kconfig" -+ - source "drivers/net/Kconfig" - - source "drivers/i2c/Kconfig" -@@ -686,6 +697,8 @@ - - source "fs/Kconfig" - -+source "sound/Kconfig" -+ - source "drivers/usb/Kconfig" - - source "drivers/uwb/Kconfig" -diff -Nur linux-2.6.36.orig/arch/cris/Makefile linux-2.6.36/arch/cris/Makefile ---- linux-2.6.36.orig/arch/cris/Makefile 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/arch/cris/Makefile 2010-12-28 20:35:00.000000000 +0100 -@@ -40,10 +40,10 @@ - - LD = $(CROSS_COMPILE)ld -mcrislinux - --OBJCOPYFLAGS := -O binary -R .note -R .comment -S -+OBJCOPYFLAGS := -O binary -R .bss -R .note -R .note.gnu.build-id -R .comment -S - - KBUILD_AFLAGS += -mlinux -march=$(arch-y) $(inc) --KBUILD_CFLAGS += -mlinux -march=$(arch-y) -pipe $(inc) -+KBUILD_CFLAGS += -mlinux -march=$(arch-y) -pipe -fno-peephole2 $(inc) - KBUILD_CPPFLAGS += $(inc) - - ifdef CONFIG_FRAME_POINTER -diff -Nur linux-2.6.36.orig/arch/cris/arch-v10/drivers/axisflashmap.c linux-2.6.36/arch/cris/arch-v10/drivers/axisflashmap.c ---- linux-2.6.36.orig/arch/cris/arch-v10/drivers/axisflashmap.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/arch/cris/arch-v10/drivers/axisflashmap.c 2010-12-28 20:35:00.000000000 +0100 -@@ -113,7 +113,7 @@ - - /* If no partition-table was found, we use this default-set. */ - #define MAX_PARTITIONS 7 --#define NUM_DEFAULT_PARTITIONS 3 -+#define NUM_DEFAULT_PARTITIONS 4 - - /* - * Default flash size is 2MB. CONFIG_ETRAX_PTABLE_SECTOR is most likely the -@@ -122,19 +122,24 @@ - */ - static struct mtd_partition axis_default_partitions[NUM_DEFAULT_PARTITIONS] = { - { -- .name = "boot firmware", -- .size = CONFIG_ETRAX_PTABLE_SECTOR, -+ .name = "kernel", -+ .size = 0x00, - .offset = 0 - }, - { -- .name = "kernel", -- .size = 0x200000 - (6 * CONFIG_ETRAX_PTABLE_SECTOR), -- .offset = CONFIG_ETRAX_PTABLE_SECTOR -+ .name = "rootfs", -+ .size = 0x200000 , -+ .offset = 0x200000 - }, - { -- .name = "filesystem", -- .size = 5 * CONFIG_ETRAX_PTABLE_SECTOR, -- .offset = 0x200000 - (5 * CONFIG_ETRAX_PTABLE_SECTOR) -+ .name = "cfgfs", -+ .size = 0x20000 , -+ .offset = CONFIG_ETRAX_MTD_SIZE - 0x20000 -+ }, -+ { -+ .name = "linux", -+ .size = CONFIG_ETRAX_MTD_SIZE - 0x20000, -+ .offset = 0 - } - }; - -@@ -281,6 +286,11 @@ - struct partitiontable_entry *ptable; - int use_default_ptable = 1; /* Until proven otherwise. */ - const char pmsg[] = " /dev/flash%d at 0x%08x, size 0x%08x\n"; -+ unsigned int kernel_part_size = 0; -+ unsigned char *flash_mem = (unsigned char*)(FLASH_CACHED_ADDR); -+ unsigned int flash_scan_count = 0; -+ const char *part_magic = "ACME_PART_MAGIC"; -+ unsigned int magic_len = strlen(part_magic); - - if (!(mymtd = flash_probe())) { - /* There's no reason to use this module if no flash chip can -@@ -292,6 +302,31 @@ - mymtd->name, mymtd->size); - axisflash_mtd = mymtd; - } -+ /* scan flash to findout where out partition starts */ -+ -+ printk(KERN_INFO "Scanning flash for end of kernel magic\n"); -+ for(flash_scan_count = 0; flash_scan_count < 100000; flash_scan_count++){ -+ if(strncmp(&flash_mem[flash_scan_count], part_magic, magic_len - 1) == 0) -+ { -+ kernel_part_size = flash_mem[flash_scan_count + magic_len ]; -+ kernel_part_size <<= 8; -+ kernel_part_size += flash_mem[flash_scan_count + magic_len + 2]; -+ kernel_part_size <<= 8; -+ kernel_part_size += flash_mem[flash_scan_count + magic_len + 1]; -+ kernel_part_size <<= 8; -+ kernel_part_size += flash_mem[flash_scan_count + magic_len + 3]; -+ printk(KERN_INFO "Kernel ends at 0x%.08X\n", kernel_part_size); -+ flash_scan_count = 1100000; -+ } -+ } -+ -+ -+ if(kernel_part_size){ -+ kernel_part_size = (kernel_part_size & 0xffff0000); -+ axis_default_partitions[0].size = kernel_part_size; -+ axis_default_partitions[1].size = mymtd->size - axis_default_partitions[0].size - axis_default_partitions[2].size; -+ axis_default_partitions[1].offset = axis_default_partitions[0].size; -+ } - - if (mymtd) { - mymtd->owner = THIS_MODULE; -@@ -360,21 +395,6 @@ - use_default_ptable = !ptable_ok; - } - -- if (romfs_in_flash) { -- /* Add an overlapping device for the root partition (romfs). */ -- -- axis_partitions[pidx].name = "romfs"; -- axis_partitions[pidx].size = romfs_length; -- axis_partitions[pidx].offset = romfs_start - FLASH_CACHED_ADDR; -- axis_partitions[pidx].mask_flags |= MTD_WRITEABLE; -- -- printk(KERN_INFO -- " Adding readonly flash partition for romfs image:\n"); -- printk(pmsg, pidx, axis_partitions[pidx].offset, -- axis_partitions[pidx].size); -- pidx++; -- } -- - #ifdef CONFIG_ETRAX_AXISFLASHMAP_MTD0WHOLE - if (mymtd) { - main_partition.size = mymtd->size; -@@ -397,36 +417,6 @@ - if (err) - panic("axisflashmap could not add MTD partitions!\n"); - } -- -- if (!romfs_in_flash) { -- /* Create an RAM device for the root partition (romfs). */ -- --#if !defined(CONFIG_MTD_MTDRAM) || (CONFIG_MTDRAM_TOTAL_SIZE != 0) || (CONFIG_MTDRAM_ABS_POS != 0) -- /* No use trying to boot this kernel from RAM. Panic! */ -- printk(KERN_EMERG "axisflashmap: Cannot create an MTD RAM " -- "device due to kernel (mis)configuration!\n"); -- panic("This kernel cannot boot from RAM!\n"); --#else -- struct mtd_info *mtd_ram; -- -- mtd_ram = kmalloc(sizeof(struct mtd_info), GFP_KERNEL); -- if (!mtd_ram) -- panic("axisflashmap couldn't allocate memory for " -- "mtd_info!\n"); -- -- printk(KERN_INFO " Adding RAM partition for romfs image:\n"); -- printk(pmsg, pidx, (unsigned)romfs_start, -- (unsigned)romfs_length); -- -- err = mtdram_init_device(mtd_ram, -- (void *)romfs_start, -- romfs_length, -- "romfs"); -- if (err) -- panic("axisflashmap could not initialize MTD RAM " -- "device!\n"); --#endif -- } - return err; - } - -diff -Nur linux-2.6.36.orig/arch/cris/arch-v10/drivers/ds1302.c linux-2.6.36/arch/cris/arch-v10/drivers/ds1302.c ---- linux-2.6.36.orig/arch/cris/arch-v10/drivers/ds1302.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/arch/cris/arch-v10/drivers/ds1302.c 2010-12-28 20:35:00.000000000 +0100 -@@ -22,6 +22,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -499,6 +500,10 @@ - return 0; - } - -+#ifdef CONFIG_SYSFS -+static struct class *rtc_class; -+#endif -+ - static int __init ds1302_register(void) - { - ds1302_init(); -@@ -507,6 +512,12 @@ - ds1302_name, RTC_MAJOR_NR); - return -1; - } -+ #ifdef CONFIG_SYSFS -+ rtc_class = class_create(THIS_MODULE, "rtc"); -+ class_device_create(rtc_class, NULL, MKDEV(RTC_MAJOR_NR, 0), -+ NULL, "rtc"); -+ #endif -+ - return 0; - - } -diff -Nur linux-2.6.36.orig/arch/cris/arch-v10/drivers/gpio.c linux-2.6.36/arch/cris/arch-v10/drivers/gpio.c ---- linux-2.6.36.orig/arch/cris/arch-v10/drivers/gpio.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/arch/cris/arch-v10/drivers/gpio.c 2010-12-28 20:35:00.000000000 +0100 -@@ -20,6 +20,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -797,6 +798,10 @@ - - /* main driver initialization routine, called from mem.c */ - -+#ifdef CONFIG_SYSFS -+static struct class *gpio_class; -+#endif -+ - static int __init gpio_init(void) - { - int res; -@@ -810,6 +815,13 @@ - return res; - } - -+#ifdef CONFIG_SYSFS -+ gpio_class = class_create(THIS_MODULE, "gpio"); -+ device_create(gpio_class, NULL, MKDEV(GPIO_MAJOR, 0), NULL, "gpioa"); -+ device_create(gpio_class, NULL, MKDEV(GPIO_MAJOR, 1), NULL, "gpiob"); -+ device_create(gpio_class, NULL, MKDEV(GPIO_MAJOR, 2), NULL, "leds"); -+ device_create(gpio_class, NULL, MKDEV(GPIO_MAJOR, 3), NULL, "gpiog"); -+#endif - /* Clear all leds */ - #if defined (CONFIG_ETRAX_CSP0_LEDS) || defined (CONFIG_ETRAX_PA_LEDS) || defined (CONFIG_ETRAX_PB_LEDS) - CRIS_LED_NETWORK_SET(0); -diff -Nur linux-2.6.36.orig/arch/cris/arch-v10/lib/hw_settings.S linux-2.6.36/arch/cris/arch-v10/lib/hw_settings.S ---- linux-2.6.36.orig/arch/cris/arch-v10/lib/hw_settings.S 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/arch/cris/arch-v10/lib/hw_settings.S 2010-12-28 20:35:00.000000000 +0100 -@@ -58,3 +58,5 @@ - .dword R_PORT_PB_SET - .dword PB_SET_VALUE - .dword 0 ; No more register values -+ .ascii "ACME_PART_MAGIC" -+ .dword 0xdeadc0de -diff -Nur linux-2.6.36.orig/arch/cris/arch-v10/mm/init.c linux-2.6.36/arch/cris/arch-v10/mm/init.c ---- linux-2.6.36.orig/arch/cris/arch-v10/mm/init.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/arch/cris/arch-v10/mm/init.c 2010-12-28 20:35:00.000000000 +0100 -@@ -184,6 +184,9 @@ - - free_area_init_node(0, zones_size, PAGE_OFFSET >> PAGE_SHIFT, 0); - } -+void free_initrd_mem(unsigned long start, unsigned long end) -+{ -+} - - /* Initialize remaps of some I/O-ports. It is important that this - * is called before any driver is initialized. -diff -Nur linux-2.6.36.orig/arch/cris/boot/Makefile linux-2.6.36/arch/cris/boot/Makefile ---- linux-2.6.36.orig/arch/cris/boot/Makefile 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/arch/cris/boot/Makefile 2010-12-28 20:35:00.000000000 +0100 -@@ -5,7 +5,7 @@ - objcopyflags-$(CONFIG_ETRAX_ARCH_V10) += -R .note -R .comment - objcopyflags-$(CONFIG_ETRAX_ARCH_V32) += --remove-section=.bss --remove-section=.note.gnu.build-id - --OBJCOPYFLAGS = -O binary $(objcopyflags-y) -+#OBJCOPYFLAGS = -O binary $(objcopyflags-y) - - - subdir- := compressed rescue -@@ -17,7 +17,6 @@ - - $(obj)/compressed/vmlinux: $(obj)/Image FORCE - $(Q)$(MAKE) $(build)=$(obj)/compressed $@ -- $(Q)$(MAKE) $(build)=$(obj)/rescue $(obj)/rescue/rescue.bin - - $(obj)/zImage: $(obj)/compressed/vmlinux - @cp $< $@ -diff -Nur linux-2.6.36.orig/arch/cris/boot/compressed/Makefile linux-2.6.36/arch/cris/boot/compressed/Makefile ---- linux-2.6.36.orig/arch/cris/boot/compressed/Makefile 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/arch/cris/boot/compressed/Makefile 2010-12-28 20:35:00.000000000 +0100 -@@ -18,7 +18,7 @@ - OBJECTS-$(CONFIG_ETRAX_ARCH_V32) = $(obj)/head_v32.o - OBJECTS-$(CONFIG_ETRAX_ARCH_V10) = $(obj)/head_v10.o - OBJECTS= $(OBJECTS-y) $(obj)/misc.o --OBJCOPYFLAGS = -O binary --remove-section=.bss -+#OBJCOPYFLAGS = -O binary --remove-section=.bss - - quiet_cmd_image = BUILD $@ - cmd_image = cat $(obj)/decompress.bin $(obj)/piggy.gz > $@ -diff -Nur linux-2.6.36.orig/arch/cris/mm/init.c linux-2.6.36/arch/cris/mm/init.c ---- linux-2.6.36.orig/arch/cris/mm/init.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/arch/cris/mm/init.c 2010-12-28 20:35:11.000000000 +0100 -@@ -81,3 +81,10 @@ - printk (KERN_INFO "Freeing unused kernel memory: %luk freed\n", - (unsigned long)((&__init_end - &__init_begin) >> 10)); - } -+ -+#ifdef CONFIG_BLK_DEV_INITRD -+void free_initrd_mem(unsigned long start, unsigned long end) -+{ -+ return 0; -+} -+#endif -diff -Nur linux-2.6.36.orig/drivers/net/cris/eth_v10.c linux-2.6.36/drivers/net/cris/eth_v10.c ---- linux-2.6.36.orig/drivers/net/cris/eth_v10.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/drivers/net/cris/eth_v10.c 2010-12-28 20:35:00.000000000 +0100 -@@ -1718,7 +1718,7 @@ - static void - e100_netpoll(struct net_device* netdev) - { -- e100rxtx_interrupt(NETWORK_DMA_TX_IRQ_NBR, netdev, NULL); -+ e100rxtx_interrupt(NETWORK_DMA_TX_IRQ_NBR, netdev); - } - #endif - -diff -Nur linux-2.6.36.orig/drivers/serial/crisv10.c linux-2.6.36/drivers/serial/crisv10.c ---- linux-2.6.36.orig/drivers/serial/crisv10.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/drivers/serial/crisv10.c 2010-12-28 20:35:00.000000000 +0100 -@@ -13,6 +13,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -27,6 +28,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -4426,6 +4428,7 @@ - #endif - }; - -+static struct class *rs_class; - static int __init rs_init(void) - { - int i; -@@ -4559,6 +4562,24 @@ - #endif - #endif /* CONFIG_SVINTO_SIM */ - -+ rs_class = class_create(THIS_MODULE, "rs_tty"); -+#ifdef CONFIG_ETRAX_SERIAL_PORT0 -+ device_create(rs_class, NULL, -+ MKDEV(TTY_MAJOR, 64), NULL, "ttyS0"); -+#endif -+#ifdef CONFIG_ETRAX_SERIAL_PORT1 -+ device_create(rs_class, NULL, -+ MKDEV(TTY_MAJOR, 65), NULL, "ttyS1"); -+#endif -+#ifdef CONFIG_ETRAX_SERIAL_PORT2 -+ device_create(rs_class, NULL, -+ MKDEV(TTY_MAJOR, 66), NULL, "ttyS2"); -+#endif -+#ifdef CONFIG_ETRAX_SERIAL_PORT3 -+ device_create(rs_class, NULL, -+ MKDEV(TTY_MAJOR, 67), NULL, "ttyS3"); -+#endif -+ - return 0; - } - -diff -Nur linux-2.6.36.orig/drivers/usb/Makefile linux-2.6.36/drivers/usb/Makefile ---- linux-2.6.36.orig/drivers/usb/Makefile 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/drivers/usb/Makefile 2010-12-28 20:35:00.000000000 +0100 -@@ -21,6 +21,7 @@ - obj-$(CONFIG_USB_R8A66597_HCD) += host/ - obj-$(CONFIG_USB_HWA_HCD) += host/ - obj-$(CONFIG_USB_ISP1760_HCD) += host/ -+obj-$(CONFIG_ETRAX_USB_HOST) += host/ - obj-$(CONFIG_USB_IMX21_HCD) += host/ - - obj-$(CONFIG_USB_C67X00_HCD) += c67x00/ -diff -Nur linux-2.6.36.orig/drivers/usb/host/Makefile linux-2.6.36/drivers/usb/host/Makefile ---- linux-2.6.36.orig/drivers/usb/host/Makefile 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/drivers/usb/host/Makefile 2010-12-28 20:35:00.000000000 +0100 -@@ -32,5 +32,6 @@ - obj-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o - obj-$(CONFIG_USB_ISP1760_HCD) += isp1760.o - obj-$(CONFIG_USB_HWA_HCD) += hwa-hc.o -+obj-$(CONFIG_ETRAX_USB_HOST) += hc-crisv10.o - obj-$(CONFIG_USB_IMX21_HCD) += imx21-hcd.o - -diff -Nur linux-2.6.36.orig/drivers/usb/host/hc-cris-dbg.h linux-2.6.36/drivers/usb/host/hc-cris-dbg.h ---- linux-2.6.36.orig/drivers/usb/host/hc-cris-dbg.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/drivers/usb/host/hc-cris-dbg.h 2010-12-28 20:35:00.000000000 +0100 -@@ -0,0 +1,146 @@ -+ -+/* macros for debug output */ -+ -+#define warn(fmt, args...) \ -+ printk(KERN_INFO "crisv10 warn: ");printk(fmt, ## args) -+ -+#define hcd_dbg(hcd, fmt, args...) \ -+ dev_info(hcd->self.controller, fmt, ## args) -+#define hcd_err(hcd, fmt, args...) \ -+ dev_err(hcd->self.controller, fmt, ## args) -+#define hcd_info(hcd, fmt, args...) \ -+ dev_info(hcd->self.controller, fmt, ## args) -+#define hcd_warn(hcd, fmt, args...) \ -+ dev_warn(hcd->self.controller, fmt, ## args) -+ -+/* -+#define devdrv_dbg(fmt, args...) \ -+ printk(KERN_INFO "usb_devdrv dbg: ");printk(fmt, ## args) -+*/ -+#define devdrv_dbg(fmt, args...) {} -+ -+#define devdrv_err(fmt, args...) \ -+ printk(KERN_ERR "usb_devdrv error: ");printk(fmt, ## args) -+#define devdrv_info(fmt, args...) \ -+ printk(KERN_INFO "usb_devdrv: ");printk(fmt, ## args) -+ -+#define irq_dbg(fmt, args...) \ -+ printk(KERN_INFO "crisv10_irq dbg: ");printk(fmt, ## args) -+#define irq_err(fmt, args...) \ -+ printk(KERN_ERR "crisv10_irq error: ");printk(fmt, ## args) -+#define irq_warn(fmt, args...) \ -+ printk(KERN_INFO "crisv10_irq warn: ");printk(fmt, ## args) -+#define irq_info(fmt, args...) \ -+ printk(KERN_INFO "crisv10_hcd: ");printk(fmt, ## args) -+ -+/* -+#define rh_dbg(fmt, args...) \ -+ printk(KERN_DEBUG "crisv10_rh dbg: ");printk(fmt, ## args) -+*/ -+#define rh_dbg(fmt, args...) {} -+ -+#define rh_err(fmt, args...) \ -+ printk(KERN_ERR "crisv10_rh error: ");printk(fmt, ## args) -+#define rh_warn(fmt, args...) \ -+ printk(KERN_INFO "crisv10_rh warning: ");printk(fmt, ## args) -+#define rh_info(fmt, args...) \ -+ printk(KERN_INFO "crisv10_rh: ");printk(fmt, ## args) -+ -+/* -+#define tc_dbg(fmt, args...) \ -+ printk(KERN_INFO "crisv10_tc dbg: ");printk(fmt, ## args) -+*/ -+#define tc_dbg(fmt, args...) {while(0){}} -+ -+#define tc_err(fmt, args...) \ -+ printk(KERN_ERR "crisv10_tc error: ");printk(fmt, ## args) -+/* -+#define tc_warn(fmt, args...) \ -+ printk(KERN_INFO "crisv10_tc warning: ");printk(fmt, ## args) -+*/ -+#define tc_warn(fmt, args...) {while(0){}} -+ -+#define tc_info(fmt, args...) \ -+ printk(KERN_INFO "crisv10_tc: ");printk(fmt, ## args) -+ -+ -+/* Debug print-outs for various traffic types */ -+ -+#define intr_warn(fmt, args...) \ -+ printk(KERN_INFO "crisv10_intr warning: ");printk(fmt, ## args) -+ -+#define intr_dbg(fmt, args...) \ -+ printk(KERN_DEBUG "crisv10_intr dbg: ");printk(fmt, ## args) -+/* -+#define intr_dbg(fmt, args...) {while(0){}} -+*/ -+ -+ -+#define isoc_err(fmt, args...) \ -+ printk(KERN_ERR "crisv10_isoc error: ");printk(fmt, ## args) -+/* -+#define isoc_warn(fmt, args...) \ -+ printk(KERN_INFO "crisv10_isoc warning: ");printk(fmt, ## args) -+*/ -+#define isoc_warn(fmt, args...) {while(0){}} -+ -+/* -+#define isoc_dbg(fmt, args...) \ -+ printk(KERN_INFO "crisv10_isoc dbg: ");printk(fmt, ## args) -+*/ -+#define isoc_dbg(fmt, args...) {while(0){}} -+ -+/* -+#define timer_warn(fmt, args...) \ -+ printk(KERN_INFO "crisv10_timer warning: ");printk(fmt, ## args) -+*/ -+#define timer_warn(fmt, args...) {while(0){}} -+ -+/* -+#define timer_dbg(fmt, args...) \ -+ printk(KERN_INFO "crisv10_timer dbg: ");printk(fmt, ## args) -+*/ -+#define timer_dbg(fmt, args...) {while(0){}} -+ -+ -+/* Debug printouts for events related to late finishing of URBs */ -+ -+#define late_dbg(fmt, args...) \ -+ printk(KERN_INFO "crisv10_late dbg: ");printk(fmt, ## args) -+/* -+#define late_dbg(fmt, args...) {while(0){}} -+*/ -+ -+#define late_warn(fmt, args...) \ -+ printk(KERN_INFO "crisv10_late warning: ");printk(fmt, ## args) -+/* -+#define errno_dbg(fmt, args...) \ -+ printk(KERN_INFO "crisv10_errno dbg: ");printk(fmt, ## args) -+*/ -+#define errno_dbg(fmt, args...) {while(0){}} -+ -+ -+#define dma_dbg(fmt, args...) \ -+ printk(KERN_INFO "crisv10_dma dbg: ");printk(fmt, ## args) -+#define dma_err(fmt, args...) \ -+ printk(KERN_ERR "crisv10_dma error: ");printk(fmt, ## args) -+#define dma_warn(fmt, args...) \ -+ printk(KERN_INFO "crisv10_dma warning: ");printk(fmt, ## args) -+#define dma_info(fmt, args...) \ -+ printk(KERN_INFO "crisv10_dma: ");printk(fmt, ## args) -+ -+ -+ -+#define str_dir(pipe) \ -+ (usb_pipeout(pipe) ? "out" : "in") -+#define str_type(pipe) \ -+ ({ \ -+ char *s = "?"; \ -+ switch (usb_pipetype(pipe)) { \ -+ case PIPE_ISOCHRONOUS: s = "iso"; break; \ -+ case PIPE_INTERRUPT: s = "intr"; break; \ -+ case PIPE_CONTROL: s = "ctrl"; break; \ -+ case PIPE_BULK: s = "bulk"; break; \ -+ }; \ -+ s; \ -+ }) -diff -Nur linux-2.6.36.orig/drivers/usb/host/hc-crisv10.c linux-2.6.36/drivers/usb/host/hc-crisv10.c ---- linux-2.6.36.orig/drivers/usb/host/hc-crisv10.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/drivers/usb/host/hc-crisv10.c 2010-12-28 20:35:00.000000000 +0100 -@@ -0,0 +1,4801 @@ -+/* -+ * -+ * ETRAX 100LX USB Host Controller Driver -+ * -+ * Copyright (C) 2005, 2006 Axis Communications AB -+ * -+ * Author: Konrad Eriksson -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+ -+#include "hc-crisv10.h" -+#include "hc-cris-dbg.h" -+ -+ -+/***************************************************************************/ -+/***************************************************************************/ -+/* Host Controller settings */ -+/***************************************************************************/ -+/***************************************************************************/ -+ -+#define VERSION "1.00 hinko.4" -+#define COPYRIGHT "(c) 2005, 2006 Axis Communications AB" -+#define DESCRIPTION "ETRAX 100LX USB Host Controller" -+ -+#define ETRAX_USB_HC_IRQ USB_HC_IRQ_NBR -+#define ETRAX_USB_RX_IRQ USB_DMA_RX_IRQ_NBR -+#define ETRAX_USB_TX_IRQ USB_DMA_TX_IRQ_NBR -+ -+/* Number of physical ports in Etrax 100LX */ -+#define USB_ROOT_HUB_PORTS 2 -+ -+const char hc_name[] = "hc-crisv10"; -+const char product_desc[] = DESCRIPTION; -+ -+/* The number of epids is, among other things, used for pre-allocating -+ ctrl, bulk and isoc EP descriptors (one for each epid). -+ Assumed to be > 1 when initiating the DMA lists. */ -+#define NBR_OF_EPIDS 32 -+ -+/* Support interrupt traffic intervals up to 128 ms. */ -+#define MAX_INTR_INTERVAL 128 -+ -+/* If periodic traffic (intr or isoc) is to be used, then one entry in the EP -+ table must be "invalid". By this we mean that we shouldn't care about epid -+ attentions for this epid, or at least handle them differently from epid -+ attentions for "valid" epids. This define determines which one to use -+ (don't change it). */ -+#define INVALID_EPID 31 -+/* A special epid for the bulk dummys. */ -+#define DUMMY_EPID 30 -+ -+/* Module settings */ -+ -+MODULE_DESCRIPTION(DESCRIPTION); -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Konrad Eriksson "); -+ -+ -+/* Module parameters */ -+ -+/* 0 = No ports enabled -+ 1 = Only port 1 enabled (on board ethernet on devboard) -+ 2 = Only port 2 enabled (external connector on devboard) -+ 3 = Both ports enabled -+*/ -+static unsigned int ports = 3; -+module_param(ports, uint, S_IRUGO); -+MODULE_PARM_DESC(ports, "Bitmask indicating USB ports to use"); -+ -+ -+/***************************************************************************/ -+/***************************************************************************/ -+/* Shared global variables for this module */ -+/***************************************************************************/ -+/***************************************************************************/ -+ -+/* EP descriptor lists for non period transfers. Must be 32-bit aligned. */ -+static volatile struct USB_EP_Desc TxBulkEPList[NBR_OF_EPIDS] __attribute__ ((aligned (4))); -+ -+static volatile struct USB_EP_Desc TxCtrlEPList[NBR_OF_EPIDS] __attribute__ ((aligned (4))); -+ -+/* EP descriptor lists for period transfers. Must be 32-bit aligned. */ -+static volatile struct USB_EP_Desc TxIntrEPList[MAX_INTR_INTERVAL] __attribute__ ((aligned (4))); -+static volatile struct USB_SB_Desc TxIntrSB_zout __attribute__ ((aligned (4))); -+ -+static volatile struct USB_EP_Desc TxIsocEPList[NBR_OF_EPIDS] __attribute__ ((aligned (4))); -+static volatile struct USB_SB_Desc TxIsocSB_zout __attribute__ ((aligned (4))); -+ -+//static volatile struct USB_SB_Desc TxIsocSBList[NBR_OF_EPIDS] __attribute__ ((aligned (4))); -+ -+/* After each enabled bulk EP IN we put two disabled EP descriptors with the eol flag set, -+ causing the DMA to stop the DMA channel. The first of these two has the intr flag set, which -+ gives us a dma8_sub0_descr interrupt. When we receive this, we advance the DMA one step in the -+ EP list and then restart the bulk channel, thus forcing a switch between bulk EP descriptors -+ in each frame. */ -+static volatile struct USB_EP_Desc TxBulkDummyEPList[NBR_OF_EPIDS][2] __attribute__ ((aligned (4))); -+ -+/* List of URB pointers, where each points to the active URB for a epid. -+ For Bulk, Ctrl and Intr this means which URB that currently is added to -+ DMA lists (Isoc URBs are all directly added to DMA lists). As soon as -+ URB has completed is the queue examined and the first URB in queue is -+ removed and moved to the activeUrbList while its state change to STARTED and -+ its transfer(s) gets added to DMA list (exception Isoc where URBs enter -+ state STARTED directly and added transfers added to DMA lists). */ -+static struct urb *activeUrbList[NBR_OF_EPIDS]; -+ -+/* Additional software state info for each epid */ -+static struct etrax_epid epid_state[NBR_OF_EPIDS]; -+ -+/* Timer handles for bulk traffic timer used to avoid DMA bug where DMA stops -+ even if there is new data waiting to be processed */ -+static struct timer_list bulk_start_timer = TIMER_INITIALIZER(NULL, 0, 0); -+static struct timer_list bulk_eot_timer = TIMER_INITIALIZER(NULL, 0, 0); -+ -+/* We want the start timer to expire before the eot timer, because the former -+ might start traffic, thus making it unnecessary for the latter to time -+ out. */ -+#define BULK_START_TIMER_INTERVAL (HZ/50) /* 20 ms */ -+#define BULK_EOT_TIMER_INTERVAL (HZ/16) /* 60 ms */ -+ -+/* Delay before a URB completion happen when it's scheduled to be delayed */ -+#define LATER_TIMER_DELAY (HZ/50) /* 20 ms */ -+ -+/* Simplifying macros for checking software state info of a epid */ -+/* ----------------------------------------------------------------------- */ -+#define epid_inuse(epid) epid_state[epid].inuse -+#define epid_out_traffic(epid) epid_state[epid].out_traffic -+#define epid_isoc(epid) (epid_state[epid].type == PIPE_ISOCHRONOUS ? 1 : 0) -+#define epid_intr(epid) (epid_state[epid].type == PIPE_INTERRUPT ? 1 : 0) -+ -+ -+/***************************************************************************/ -+/***************************************************************************/ -+/* DEBUG FUNCTIONS */ -+/***************************************************************************/ -+/***************************************************************************/ -+/* Note that these functions are always available in their "__" variants, -+ for use in error situations. The "__" missing variants are controlled by -+ the USB_DEBUG_DESC/USB_DEBUG_URB macros. */ -+static void __dump_urb(struct urb* purb) -+{ -+ struct crisv10_urb_priv *urb_priv = purb->hcpriv; -+ int urb_num = -1; -+ if(urb_priv) { -+ urb_num = urb_priv->urb_num; -+ } -+ printk("\nURB:0x%x[%d]\n", (unsigned int)purb, urb_num); -+ printk("dev :0x%08lx\n", (unsigned long)purb->dev); -+ printk("pipe :0x%08x\n", purb->pipe); -+ printk("status :%d\n", purb->status); -+ printk("transfer_flags :0x%08x\n", purb->transfer_flags); -+ printk("transfer_buffer :0x%08lx\n", (unsigned long)purb->transfer_buffer); -+ printk("transfer_buffer_length:%d\n", purb->transfer_buffer_length); -+ printk("actual_length :%d\n", purb->actual_length); -+ printk("setup_packet :0x%08lx\n", (unsigned long)purb->setup_packet); -+ printk("start_frame :%d\n", purb->start_frame); -+ printk("number_of_packets :%d\n", purb->number_of_packets); -+ printk("interval :%d\n", purb->interval); -+ printk("error_count :%d\n", purb->error_count); -+ printk("context :0x%08lx\n", (unsigned long)purb->context); -+ printk("complete :0x%08lx\n\n", (unsigned long)purb->complete); -+} -+ -+static void __dump_in_desc(volatile struct USB_IN_Desc *in) -+{ -+ printk("\nUSB_IN_Desc at 0x%08lx\n", (unsigned long)in); -+ printk(" sw_len : 0x%04x (%d)\n", in->sw_len, in->sw_len); -+ printk(" command : 0x%04x\n", in->command); -+ printk(" next : 0x%08lx\n", in->next); -+ printk(" buf : 0x%08lx\n", in->buf); -+ printk(" hw_len : 0x%04x (%d)\n", in->hw_len, in->hw_len); -+ printk(" status : 0x%04x\n\n", in->status); -+} -+ -+static void __dump_sb_desc(volatile struct USB_SB_Desc *sb) -+{ -+ char tt = (sb->command & 0x30) >> 4; -+ char *tt_string; -+ -+ switch (tt) { -+ case 0: -+ tt_string = "zout"; -+ break; -+ case 1: -+ tt_string = "in"; -+ break; -+ case 2: -+ tt_string = "out"; -+ break; -+ case 3: -+ tt_string = "setup"; -+ break; -+ default: -+ tt_string = "unknown (weird)"; -+ } -+ -+ printk(" USB_SB_Desc at 0x%08lx ", (unsigned long)sb); -+ printk(" command:0x%04x (", sb->command); -+ printk("rem:%d ", (sb->command & 0x3f00) >> 8); -+ printk("full:%d ", (sb->command & 0x40) >> 6); -+ printk("tt:%d(%s) ", tt, tt_string); -+ printk("intr:%d ", (sb->command & 0x8) >> 3); -+ printk("eot:%d ", (sb->command & 0x2) >> 1); -+ printk("eol:%d)", sb->command & 0x1); -+ printk(" sw_len:0x%04x(%d)", sb->sw_len, sb->sw_len); -+ printk(" next:0x%08lx", sb->next); -+ printk(" buf:0x%08lx\n", sb->buf); -+} -+ -+ -+static void __dump_ep_desc(volatile struct USB_EP_Desc *ep) -+{ -+ printk("USB_EP_Desc at 0x%08lx ", (unsigned long)ep); -+ printk(" command:0x%04x (", ep->command); -+ printk("ep_id:%d ", (ep->command & 0x1f00) >> 8); -+ printk("enable:%d ", (ep->command & 0x10) >> 4); -+ printk("intr:%d ", (ep->command & 0x8) >> 3); -+ printk("eof:%d ", (ep->command & 0x2) >> 1); -+ printk("eol:%d)", ep->command & 0x1); -+ printk(" hw_len:0x%04x(%d)", ep->hw_len, ep->hw_len); -+ printk(" next:0x%08lx", ep->next); -+ printk(" sub:0x%08lx\n", ep->sub); -+} -+ -+static inline void __dump_ep_list(int pipe_type) -+{ -+ volatile struct USB_EP_Desc *ep; -+ volatile struct USB_EP_Desc *first_ep; -+ volatile struct USB_SB_Desc *sb; -+ -+ switch (pipe_type) -+ { -+ case PIPE_BULK: -+ first_ep = &TxBulkEPList[0]; -+ break; -+ case PIPE_CONTROL: -+ first_ep = &TxCtrlEPList[0]; -+ break; -+ case PIPE_INTERRUPT: -+ first_ep = &TxIntrEPList[0]; -+ break; -+ case PIPE_ISOCHRONOUS: -+ first_ep = &TxIsocEPList[0]; -+ break; -+ default: -+ warn("Cannot dump unknown traffic type"); -+ return; -+ } -+ ep = first_ep; -+ -+ printk("\n\nDumping EP list...\n\n"); -+ -+ do { -+ __dump_ep_desc(ep); -+ /* Cannot phys_to_virt on 0 as it turns into 80000000, which is != 0. */ -+ sb = ep->sub ? phys_to_virt(ep->sub) : 0; -+ while (sb) { -+ __dump_sb_desc(sb); -+ sb = sb->next ? phys_to_virt(sb->next) : 0; -+ } -+ ep = (volatile struct USB_EP_Desc *)(phys_to_virt(ep->next)); -+ -+ } while (ep != first_ep); -+} -+ -+static inline void __dump_ept_data(int epid) -+{ -+ unsigned long flags; -+ __u32 r_usb_ept_data; -+ -+ if (epid < 0 || epid > 31) { -+ printk("Cannot dump ept data for invalid epid %d\n", epid); -+ return; -+ } -+ -+ local_irq_save(flags); -+ *R_USB_EPT_INDEX = IO_FIELD(R_USB_EPT_INDEX, value, epid); -+ nop(); -+ r_usb_ept_data = *R_USB_EPT_DATA; -+ local_irq_restore(flags); -+ -+ printk(" R_USB_EPT_DATA = 0x%x for epid %d :\n", r_usb_ept_data, epid); -+ if (r_usb_ept_data == 0) { -+ /* No need for more detailed printing. */ -+ return; -+ } -+ printk(" valid : %d\n", (r_usb_ept_data & 0x80000000) >> 31); -+ printk(" hold : %d\n", (r_usb_ept_data & 0x40000000) >> 30); -+ printk(" error_count_in : %d\n", (r_usb_ept_data & 0x30000000) >> 28); -+ printk(" t_in : %d\n", (r_usb_ept_data & 0x08000000) >> 27); -+ printk(" low_speed : %d\n", (r_usb_ept_data & 0x04000000) >> 26); -+ printk(" port : %d\n", (r_usb_ept_data & 0x03000000) >> 24); -+ printk(" error_code : %d\n", (r_usb_ept_data & 0x00c00000) >> 22); -+ printk(" t_out : %d\n", (r_usb_ept_data & 0x00200000) >> 21); -+ printk(" error_count_out : %d\n", (r_usb_ept_data & 0x00180000) >> 19); -+ printk(" max_len : %d\n", (r_usb_ept_data & 0x0003f800) >> 11); -+ printk(" ep : %d\n", (r_usb_ept_data & 0x00000780) >> 7); -+ printk(" dev : %d\n", (r_usb_ept_data & 0x0000003f)); -+} -+ -+static inline void __dump_ept_data_iso(int epid) -+{ -+ unsigned long flags; -+ __u32 ept_data; -+ -+ if (epid < 0 || epid > 31) { -+ printk("Cannot dump ept data for invalid epid %d\n", epid); -+ return; -+ } -+ -+ local_irq_save(flags); -+ *R_USB_EPT_INDEX = IO_FIELD(R_USB_EPT_INDEX, value, epid); -+ nop(); -+ ept_data = *R_USB_EPT_DATA_ISO; -+ local_irq_restore(flags); -+ -+ printk(" R_USB_EPT_DATA = 0x%x for epid %d :\n", ept_data, epid); -+ if (ept_data == 0) { -+ /* No need for more detailed printing. */ -+ return; -+ } -+ printk(" valid : %d\n", IO_EXTRACT(R_USB_EPT_DATA_ISO, valid, -+ ept_data)); -+ printk(" port : %d\n", IO_EXTRACT(R_USB_EPT_DATA_ISO, port, -+ ept_data)); -+ printk(" error_code : %d\n", IO_EXTRACT(R_USB_EPT_DATA_ISO, error_code, -+ ept_data)); -+ printk(" max_len : %d\n", IO_EXTRACT(R_USB_EPT_DATA_ISO, max_len, -+ ept_data)); -+ printk(" ep : %d\n", IO_EXTRACT(R_USB_EPT_DATA_ISO, ep, -+ ept_data)); -+ printk(" dev : %d\n", IO_EXTRACT(R_USB_EPT_DATA_ISO, dev, -+ ept_data)); -+} -+ -+static inline void __dump_ept_data_list(void) -+{ -+ int i; -+ -+ printk("Dumping the whole R_USB_EPT_DATA list\n"); -+ -+ for (i = 0; i < 32; i++) { -+ __dump_ept_data(i); -+ } -+} -+ -+static void debug_epid(int epid) { -+ int i; -+ -+ if(epid_isoc(epid)) { -+ __dump_ept_data_iso(epid); -+ } else { -+ __dump_ept_data(epid); -+ } -+ -+ printk("Bulk:\n"); -+ for(i = 0; i < 32; i++) { -+ if(IO_EXTRACT(USB_EP_command, epid, TxBulkEPList[i].command) == -+ epid) { -+ printk("%d: ", i); __dump_ep_desc(&(TxBulkEPList[i])); -+ } -+ } -+ -+ printk("Ctrl:\n"); -+ for(i = 0; i < 32; i++) { -+ if(IO_EXTRACT(USB_EP_command, epid, TxCtrlEPList[i].command) == -+ epid) { -+ printk("%d: ", i); __dump_ep_desc(&(TxCtrlEPList[i])); -+ } -+ } -+ -+ printk("Intr:\n"); -+ for(i = 0; i < MAX_INTR_INTERVAL; i++) { -+ if(IO_EXTRACT(USB_EP_command, epid, TxIntrEPList[i].command) == -+ epid) { -+ printk("%d: ", i); __dump_ep_desc(&(TxIntrEPList[i])); -+ } -+ } -+ -+ printk("Isoc:\n"); -+ for(i = 0; i < 32; i++) { -+ if(IO_EXTRACT(USB_EP_command, epid, TxIsocEPList[i].command) == -+ epid) { -+ printk("%d: ", i); __dump_ep_desc(&(TxIsocEPList[i])); -+ } -+ } -+ -+ __dump_ept_data_list(); -+ __dump_ep_list(PIPE_INTERRUPT); -+ printk("\n\n"); -+} -+ -+ -+ -+char* hcd_status_to_str(__u8 bUsbStatus) { -+ static char hcd_status_str[128]; -+ hcd_status_str[0] = '\0'; -+ if(bUsbStatus & IO_STATE(R_USB_STATUS, ourun, yes)) { -+ strcat(hcd_status_str, "ourun "); -+ } -+ if(bUsbStatus & IO_STATE(R_USB_STATUS, perror, yes)) { -+ strcat(hcd_status_str, "perror "); -+ } -+ if(bUsbStatus & IO_STATE(R_USB_STATUS, device_mode, yes)) { -+ strcat(hcd_status_str, "device_mode "); -+ } -+ if(bUsbStatus & IO_STATE(R_USB_STATUS, host_mode, yes)) { -+ strcat(hcd_status_str, "host_mode "); -+ } -+ if(bUsbStatus & IO_STATE(R_USB_STATUS, started, yes)) { -+ strcat(hcd_status_str, "started "); -+ } -+ if(bUsbStatus & IO_STATE(R_USB_STATUS, running, yes)) { -+ strcat(hcd_status_str, "running "); -+ } -+ return hcd_status_str; -+} -+ -+ -+char* sblist_to_str(struct USB_SB_Desc* sb_desc) { -+ static char sblist_to_str_buff[128]; -+ char tmp[32], tmp2[32]; -+ sblist_to_str_buff[0] = '\0'; -+ while(sb_desc != NULL) { -+ switch(IO_EXTRACT(USB_SB_command, tt, sb_desc->command)) { -+ case 0: sprintf(tmp, "zout"); break; -+ case 1: sprintf(tmp, "in"); break; -+ case 2: sprintf(tmp, "out"); break; -+ case 3: sprintf(tmp, "setup"); break; -+ } -+ sprintf(tmp2, "(%s %d)", tmp, sb_desc->sw_len); -+ strcat(sblist_to_str_buff, tmp2); -+ if(sb_desc->next != 0) { -+ sb_desc = phys_to_virt(sb_desc->next); -+ } else { -+ sb_desc = NULL; -+ } -+ } -+ return sblist_to_str_buff; -+} -+ -+char* port_status_to_str(__u16 wPortStatus) { -+ static char port_status_str[128]; -+ port_status_str[0] = '\0'; -+ if(wPortStatus & IO_STATE(R_USB_RH_PORT_STATUS_1, connected, yes)) { -+ strcat(port_status_str, "connected "); -+ } -+ if(wPortStatus & IO_STATE(R_USB_RH_PORT_STATUS_1, enabled, yes)) { -+ strcat(port_status_str, "enabled "); -+ } -+ if(wPortStatus & IO_STATE(R_USB_RH_PORT_STATUS_1, suspended, yes)) { -+ strcat(port_status_str, "suspended "); -+ } -+ if(wPortStatus & IO_STATE(R_USB_RH_PORT_STATUS_1, reset, yes)) { -+ strcat(port_status_str, "reset "); -+ } -+ if(wPortStatus & IO_STATE(R_USB_RH_PORT_STATUS_1, speed, full)) { -+ strcat(port_status_str, "full-speed "); -+ } else { -+ strcat(port_status_str, "low-speed "); -+ } -+ return port_status_str; -+} -+ -+ -+char* endpoint_to_str(struct usb_endpoint_descriptor *ed) { -+ static char endpoint_to_str_buff[128]; -+ char tmp[32]; -+ int epnum = ed->bEndpointAddress & 0x0F; -+ int dir = ed->bEndpointAddress & 0x80; -+ int type = ed->bmAttributes & 0x03; -+ endpoint_to_str_buff[0] = '\0'; -+ sprintf(endpoint_to_str_buff, "ep:%d ", epnum); -+ switch(type) { -+ case 0: -+ sprintf(tmp, " ctrl"); -+ break; -+ case 1: -+ sprintf(tmp, " isoc"); -+ break; -+ case 2: -+ sprintf(tmp, " bulk"); -+ break; -+ case 3: -+ sprintf(tmp, " intr"); -+ break; -+ } -+ strcat(endpoint_to_str_buff, tmp); -+ if(dir) { -+ sprintf(tmp, " in"); -+ } else { -+ sprintf(tmp, " out"); -+ } -+ strcat(endpoint_to_str_buff, tmp); -+ -+ return endpoint_to_str_buff; -+} -+ -+/* Debug helper functions for Transfer Controller */ -+char* pipe_to_str(unsigned int pipe) { -+ static char pipe_to_str_buff[128]; -+ char tmp[64]; -+ sprintf(pipe_to_str_buff, "dir:%s", str_dir(pipe)); -+ sprintf(tmp, " type:%s", str_type(pipe)); -+ strcat(pipe_to_str_buff, tmp); -+ -+ sprintf(tmp, " dev:%d", usb_pipedevice(pipe)); -+ strcat(pipe_to_str_buff, tmp); -+ sprintf(tmp, " ep:%d", usb_pipeendpoint(pipe)); -+ strcat(pipe_to_str_buff, tmp); -+ return pipe_to_str_buff; -+} -+ -+ -+#define USB_DEBUG_DESC 1 -+ -+#ifdef USB_DEBUG_DESC -+#define dump_in_desc(x) __dump_in_desc(x) -+#define dump_sb_desc(...) __dump_sb_desc(...) -+#define dump_ep_desc(x) __dump_ep_desc(x) -+#define dump_ept_data(x) __dump_ept_data(x) -+#else -+#define dump_in_desc(...) do {} while (0) -+#define dump_sb_desc(...) do {} while (0) -+#define dump_ep_desc(...) do {} while (0) -+#endif -+ -+ -+/* Uncomment this to enable massive function call trace -+ #define USB_DEBUG_TRACE */ -+//#define USB_DEBUG_TRACE 1 -+ -+#ifdef USB_DEBUG_TRACE -+#define DBFENTER (printk(": Entering: %s\n", __FUNCTION__)) -+#define DBFEXIT (printk(": Exiting: %s\n", __FUNCTION__)) -+#else -+#define DBFENTER do {} while (0) -+#define DBFEXIT do {} while (0) -+#endif -+ -+#define CHECK_ALIGN(x) if (((__u32)(x)) & 0x00000003) \ -+{panic("Alignment check (DWORD) failed at %s:%s:%d\n", __FILE__, __FUNCTION__, __LINE__);} -+ -+/* Most helpful debugging aid */ -+#define ASSERT(expr) ((void) ((expr) ? 0 : (err("assert failed at: %s %d",__FUNCTION__, __LINE__)))) -+ -+ -+/***************************************************************************/ -+/***************************************************************************/ -+/* Forward declarations */ -+/***************************************************************************/ -+/***************************************************************************/ -+void crisv10_hcd_epid_attn_irq(struct crisv10_irq_reg *reg); -+void crisv10_hcd_port_status_irq(struct crisv10_irq_reg *reg); -+void crisv10_hcd_ctl_status_irq(struct crisv10_irq_reg *reg); -+void crisv10_hcd_isoc_eof_irq(struct crisv10_irq_reg *reg); -+ -+void rh_port_status_change(__u16[]); -+int rh_clear_port_feature(__u8, __u16); -+int rh_set_port_feature(__u8, __u16); -+static void rh_disable_port(unsigned int port); -+ -+static void check_finished_bulk_tx_epids(struct usb_hcd *hcd, -+ int timer); -+ -+//static int tc_setup_epid(struct usb_host_endpoint *ep, struct urb *urb, -+// int mem_flags); -+static int tc_setup_epid(struct urb *urb, int mem_flags); -+static void tc_free_epid(struct usb_host_endpoint *ep); -+static int tc_allocate_epid(void); -+static void tc_finish_urb(struct usb_hcd *hcd, struct urb *urb, int status); -+static void tc_finish_urb_later(struct usb_hcd *hcd, struct urb *urb, -+ int status); -+ -+static int urb_priv_create(struct usb_hcd *hcd, struct urb *urb, int epid, -+ int mem_flags); -+static void urb_priv_free(struct usb_hcd *hcd, struct urb *urb); -+ -+static inline struct urb *urb_list_first(int epid); -+static inline void urb_list_add(struct urb *urb, int epid, -+ int mem_flags); -+static inline urb_entry_t *urb_list_entry(struct urb *urb, int epid); -+static inline void urb_list_del(struct urb *urb, int epid); -+static inline void urb_list_move_last(struct urb *urb, int epid); -+static inline struct urb *urb_list_next(struct urb *urb, int epid); -+ -+int create_sb_for_urb(struct urb *urb, int mem_flags); -+int init_intr_urb(struct urb *urb, int mem_flags); -+ -+static inline void etrax_epid_set(__u8 index, __u32 data); -+static inline void etrax_epid_clear_error(__u8 index); -+static inline void etrax_epid_set_toggle(__u8 index, __u8 dirout, -+ __u8 toggle); -+static inline __u8 etrax_epid_get_toggle(__u8 index, __u8 dirout); -+static inline __u32 etrax_epid_get(__u8 index); -+ -+/* We're accessing the same register position in Etrax so -+ when we do full access the internal difference doesn't matter */ -+#define etrax_epid_iso_set(index, data) etrax_epid_set(index, data) -+#define etrax_epid_iso_get(index) etrax_epid_get(index) -+ -+ -+//static void tc_dma_process_isoc_urb(struct urb *urb); -+static void tc_dma_process_queue(int epid); -+static void tc_dma_unlink_intr_urb(struct urb *urb); -+static irqreturn_t tc_dma_tx_interrupt(int irq, void *vhc); -+static irqreturn_t tc_dma_rx_interrupt(int irq, void *vhc); -+ -+static void tc_bulk_start_timer_func(unsigned long dummy); -+static void tc_bulk_eot_timer_func(unsigned long dummy); -+ -+ -+/*************************************************************/ -+/*************************************************************/ -+/* Host Controler Driver block */ -+/*************************************************************/ -+/*************************************************************/ -+ -+/* HCD operations */ -+static irqreturn_t crisv10_hcd_top_irq(int irq, void*); -+static int crisv10_hcd_reset(struct usb_hcd *); -+static int crisv10_hcd_start(struct usb_hcd *); -+static void crisv10_hcd_stop(struct usb_hcd *); -+#ifdef CONFIG_PM -+static int crisv10_hcd_suspend(struct device *, u32, u32); -+static int crisv10_hcd_resume(struct device *, u32); -+#endif /* CONFIG_PM */ -+static int crisv10_hcd_get_frame(struct usb_hcd *); -+ -+//static int tc_urb_enqueue(struct usb_hcd *, struct usb_host_endpoint *ep, struct urb *, gfp_t mem_flags); -+static int tc_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags); -+//static int tc_urb_dequeue(struct usb_hcd *, struct urb *); -+static int tc_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status); -+static void tc_endpoint_disable(struct usb_hcd *, struct usb_host_endpoint *ep); -+ -+static int rh_status_data_request(struct usb_hcd *, char *); -+static int rh_control_request(struct usb_hcd *, u16, u16, u16, char*, u16); -+ -+#ifdef CONFIG_PM -+static int crisv10_hcd_hub_suspend(struct usb_hcd *); -+static int crisv10_hcd_hub_resume(struct usb_hcd *); -+#endif /* CONFIG_PM */ -+#ifdef CONFIG_USB_OTG -+static int crisv10_hcd_start_port_reset(struct usb_hcd *, unsigned); -+#endif /* CONFIG_USB_OTG */ -+ -+/* host controller driver interface */ -+static const struct hc_driver crisv10_hc_driver = -+ { -+ .description = hc_name, -+ .product_desc = product_desc, -+ .hcd_priv_size = sizeof(struct crisv10_hcd), -+ -+ /* Attaching IRQ handler manualy in probe() */ -+ /* .irq = crisv10_hcd_irq, */ -+ -+ .flags = HCD_USB11, -+ -+ /* called to init HCD and root hub */ -+ .reset = crisv10_hcd_reset, -+ .start = crisv10_hcd_start, -+ -+ /* cleanly make HCD stop writing memory and doing I/O */ -+ .stop = crisv10_hcd_stop, -+ -+ /* return current frame number */ -+ .get_frame_number = crisv10_hcd_get_frame, -+ -+ -+ /* Manage i/o requests via the Transfer Controller */ -+ .urb_enqueue = tc_urb_enqueue, -+ .urb_dequeue = tc_urb_dequeue, -+ -+ /* hw synch, freeing endpoint resources that urb_dequeue can't */ -+ .endpoint_disable = tc_endpoint_disable, -+ -+ -+ /* Root Hub support */ -+ .hub_status_data = rh_status_data_request, -+ .hub_control = rh_control_request, -+#ifdef CONFIG_PM -+ .hub_suspend = rh_suspend_request, -+ .hub_resume = rh_resume_request, -+#endif /* CONFIG_PM */ -+#ifdef CONFIG_USB_OTG -+ .start_port_reset = crisv10_hcd_start_port_reset, -+#endif /* CONFIG_USB_OTG */ -+ }; -+ -+ -+/* -+ * conversion between pointers to a hcd and the corresponding -+ * crisv10_hcd -+ */ -+ -+static inline struct crisv10_hcd *hcd_to_crisv10_hcd(struct usb_hcd *hcd) -+{ -+ return (struct crisv10_hcd *) hcd->hcd_priv; -+} -+ -+static inline struct usb_hcd *crisv10_hcd_to_hcd(struct crisv10_hcd *hcd) -+{ -+ return container_of((void *) hcd, struct usb_hcd, hcd_priv); -+} -+ -+/* check if specified port is in use */ -+static inline int port_in_use(unsigned int port) -+{ -+ return ports & (1 << port); -+} -+ -+/* number of ports in use */ -+static inline unsigned int num_ports(void) -+{ -+ unsigned int i, num = 0; -+ for (i = 0; i < USB_ROOT_HUB_PORTS; i++) -+ if (port_in_use(i)) -+ num++; -+ return num; -+} -+ -+/* map hub port number to the port number used internally by the HC */ -+static inline unsigned int map_port(unsigned int port) -+{ -+ unsigned int i, num = 0; -+ for (i = 0; i < USB_ROOT_HUB_PORTS; i++) -+ if (port_in_use(i)) -+ if (++num == port) -+ return i; -+ return -1; -+} -+ -+/* size of descriptors in slab cache */ -+#ifndef MAX -+#define MAX(x, y) ((x) > (y) ? (x) : (y)) -+#endif -+ -+ -+/******************************************************************/ -+/* Hardware Interrupt functions */ -+/******************************************************************/ -+ -+/* Fast interrupt handler for HC */ -+static irqreturn_t crisv10_hcd_top_irq(int irq, void *vcd) -+{ -+ struct usb_hcd *hcd = vcd; -+ struct crisv10_irq_reg reg; -+ __u32 irq_mask; -+ unsigned long flags; -+ -+ DBFENTER; -+ -+ ASSERT(hcd != NULL); -+ reg.hcd = hcd; -+ -+ /* Turn of other interrupts while handling these sensitive cases */ -+ local_irq_save(flags); -+ -+ /* Read out which interrupts that are flaged */ -+ irq_mask = *R_USB_IRQ_MASK_READ; -+ reg.r_usb_irq_mask_read = irq_mask; -+ -+ /* Reading R_USB_STATUS clears the ctl_status interrupt. Note that -+ R_USB_STATUS must be read before R_USB_EPID_ATTN since reading the latter -+ clears the ourun and perror fields of R_USB_STATUS. */ -+ reg.r_usb_status = *R_USB_STATUS; -+ -+ /* Reading R_USB_EPID_ATTN clears the iso_eof, bulk_eot and epid_attn -+ interrupts. */ -+ reg.r_usb_epid_attn = *R_USB_EPID_ATTN; -+ -+ /* Reading R_USB_RH_PORT_STATUS_1 and R_USB_RH_PORT_STATUS_2 clears the -+ port_status interrupt. */ -+ reg.r_usb_rh_port_status_1 = *R_USB_RH_PORT_STATUS_1; -+ reg.r_usb_rh_port_status_2 = *R_USB_RH_PORT_STATUS_2; -+ -+ /* Reading R_USB_FM_NUMBER clears the sof interrupt. */ -+ /* Note: the lower 11 bits contain the actual frame number, sent with each -+ sof. */ -+ reg.r_usb_fm_number = *R_USB_FM_NUMBER; -+ -+ /* Interrupts are handled in order of priority. */ -+ if (irq_mask & IO_MASK(R_USB_IRQ_MASK_READ, port_status)) { -+ crisv10_hcd_port_status_irq(®); -+ } -+ if (irq_mask & IO_MASK(R_USB_IRQ_MASK_READ, epid_attn)) { -+ crisv10_hcd_epid_attn_irq(®); -+ } -+ if (irq_mask & IO_MASK(R_USB_IRQ_MASK_READ, ctl_status)) { -+ crisv10_hcd_ctl_status_irq(®); -+ } -+ if (irq_mask & IO_MASK(R_USB_IRQ_MASK_READ, iso_eof)) { -+ crisv10_hcd_isoc_eof_irq(®); -+ } -+ if (irq_mask & IO_MASK(R_USB_IRQ_MASK_READ, bulk_eot)) { -+ /* Update/restart the bulk start timer since obviously the channel is -+ running. */ -+ mod_timer(&bulk_start_timer, jiffies + BULK_START_TIMER_INTERVAL); -+ /* Update/restart the bulk eot timer since we just received an bulk eot -+ interrupt. */ -+ mod_timer(&bulk_eot_timer, jiffies + BULK_EOT_TIMER_INTERVAL); -+ -+ /* Check for finished bulk transfers on epids */ -+ check_finished_bulk_tx_epids(hcd, 0); -+ } -+ local_irq_restore(flags); -+ -+ DBFEXIT; -+ return IRQ_HANDLED; -+} -+ -+ -+void crisv10_hcd_epid_attn_irq(struct crisv10_irq_reg *reg) { -+ struct usb_hcd *hcd = reg->hcd; -+ struct crisv10_urb_priv *urb_priv; -+ int epid; -+ DBFENTER; -+ -+ for (epid = 0; epid < NBR_OF_EPIDS; epid++) { -+ if (test_bit(epid, (void *)®->r_usb_epid_attn)) { -+ struct urb *urb; -+ __u32 ept_data; -+ int error_code; -+ -+ if (epid == DUMMY_EPID || epid == INVALID_EPID) { -+ /* We definitely don't care about these ones. Besides, they are -+ always disabled, so any possible disabling caused by the -+ epid attention interrupt is irrelevant. */ -+ warn("Got epid_attn for INVALID_EPID or DUMMY_EPID (%d).", epid); -+ continue; -+ } -+ -+ if(!epid_inuse(epid)) { -+ irq_err("Epid attention on epid:%d that isn't in use\n", epid); -+ printk("R_USB_STATUS: 0x%x\n", reg->r_usb_status); -+ debug_epid(epid); -+ continue; -+ } -+ -+ /* Note that although there are separate R_USB_EPT_DATA and -+ R_USB_EPT_DATA_ISO registers, they are located at the same address and -+ are of the same size. In other words, this read should be ok for isoc -+ also. */ -+ ept_data = etrax_epid_get(epid); -+ error_code = IO_EXTRACT(R_USB_EPT_DATA, error_code, ept_data); -+ -+ /* Get the active URB for this epid. We blatantly assume -+ that only this URB could have caused the epid attention. */ -+ urb = activeUrbList[epid]; -+ if (urb == NULL) { -+ irq_err("Attention on epid:%d error:%d with no active URB.\n", -+ epid, error_code); -+ printk("R_USB_STATUS: 0x%x\n", reg->r_usb_status); -+ debug_epid(epid); -+ continue; -+ } -+ -+ urb_priv = (struct crisv10_urb_priv *)urb->hcpriv; -+ ASSERT(urb_priv); -+ -+ /* Using IO_STATE_VALUE on R_USB_EPT_DATA should be ok for isoc also. */ -+ if (error_code == IO_STATE_VALUE(R_USB_EPT_DATA, error_code, no_error)) { -+ -+ /* Isoc traffic doesn't have error_count_in/error_count_out. */ -+ if ((usb_pipetype(urb->pipe) != PIPE_ISOCHRONOUS) && -+ (IO_EXTRACT(R_USB_EPT_DATA, error_count_in, ept_data) == 3 || -+ IO_EXTRACT(R_USB_EPT_DATA, error_count_out, ept_data) == 3)) { -+ /* Check if URB allready is marked for late-finish, we can get -+ several 3rd error for Intr traffic when a device is unplugged */ -+ if(urb_priv->later_data == NULL) { -+ /* 3rd error. */ -+ irq_warn("3rd error for epid:%d (%s %s) URB:0x%x[%d]\n", epid, -+ str_dir(urb->pipe), str_type(urb->pipe), -+ (unsigned int)urb, urb_priv->urb_num); -+ -+ tc_finish_urb_later(hcd, urb, -EPROTO); -+ } -+ -+ } else if (reg->r_usb_status & IO_MASK(R_USB_STATUS, perror)) { -+ irq_warn("Perror for epid:%d\n", epid); -+ printk("FM_NUMBER: %d\n", reg->r_usb_fm_number & 0x7ff); -+ printk("R_USB_STATUS: 0x%x\n", reg->r_usb_status); -+ __dump_urb(urb); -+ debug_epid(epid); -+ -+ if (!(ept_data & IO_MASK(R_USB_EPT_DATA, valid))) { -+ /* invalid ep_id */ -+ panic("Perror because of invalid epid." -+ " Deconfigured too early?"); -+ } else { -+ /* past eof1, near eof, zout transfer, setup transfer */ -+ /* Dump the urb and the relevant EP descriptor. */ -+ panic("Something wrong with DMA descriptor contents." -+ " Too much traffic inserted?"); -+ } -+ } else if (reg->r_usb_status & IO_MASK(R_USB_STATUS, ourun)) { -+ /* buffer ourun */ -+ printk("FM_NUMBER: %d\n", reg->r_usb_fm_number & 0x7ff); -+ printk("R_USB_STATUS: 0x%x\n", reg->r_usb_status); -+ __dump_urb(urb); -+ debug_epid(epid); -+ -+ panic("Buffer overrun/underrun for epid:%d. DMA too busy?", epid); -+ } else { -+ irq_warn("Attention on epid:%d (%s %s) with no error code\n", epid, -+ str_dir(urb->pipe), str_type(urb->pipe)); -+ printk("R_USB_STATUS: 0x%x\n", reg->r_usb_status); -+ __dump_urb(urb); -+ debug_epid(epid); -+ } -+ -+ } else if (error_code == IO_STATE_VALUE(R_USB_EPT_DATA, error_code, -+ stall)) { -+ /* Not really a protocol error, just says that the endpoint gave -+ a stall response. Note that error_code cannot be stall for isoc. */ -+ if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { -+ panic("Isoc traffic cannot stall"); -+ } -+ -+ tc_dbg("Stall for epid:%d (%s %s) URB:0x%x\n", epid, -+ str_dir(urb->pipe), str_type(urb->pipe), (unsigned int)urb); -+ tc_finish_urb(hcd, urb, -EPIPE); -+ -+ } else if (error_code == IO_STATE_VALUE(R_USB_EPT_DATA, error_code, -+ bus_error)) { -+ /* Two devices responded to a transaction request. Must be resolved -+ by software. FIXME: Reset ports? */ -+ panic("Bus error for epid %d." -+ " Two devices responded to transaction request\n", -+ epid); -+ -+ } else if (error_code == IO_STATE_VALUE(R_USB_EPT_DATA, error_code, -+ buffer_error)) { -+ /* DMA overrun or underrun. */ -+ irq_warn("Buffer overrun/underrun for epid:%d (%s %s)\n", epid, -+ str_dir(urb->pipe), str_type(urb->pipe)); -+ -+ /* It seems that error_code = buffer_error in -+ R_USB_EPT_DATA/R_USB_EPT_DATA_ISO and ourun = yes in R_USB_STATUS -+ are the same error. */ -+ tc_finish_urb(hcd, urb, -EPROTO); -+ } else { -+ irq_warn("Unknown attention on epid:%d (%s %s)\n", epid, -+ str_dir(urb->pipe), str_type(urb->pipe)); -+ dump_ept_data(epid); -+ } -+ } -+ } -+ DBFEXIT; -+} -+ -+void crisv10_hcd_port_status_irq(struct crisv10_irq_reg *reg) -+{ -+ __u16 port_reg[USB_ROOT_HUB_PORTS]; -+ DBFENTER; -+ port_reg[0] = reg->r_usb_rh_port_status_1; -+ port_reg[1] = reg->r_usb_rh_port_status_2; -+ rh_port_status_change(port_reg); -+ DBFEXIT; -+} -+ -+void crisv10_hcd_isoc_eof_irq(struct crisv10_irq_reg *reg) -+{ -+ int epid; -+ struct urb *urb; -+ struct crisv10_urb_priv *urb_priv; -+ -+ DBFENTER; -+ -+ for (epid = 0; epid < NBR_OF_EPIDS - 1; epid++) { -+ -+ /* Only check epids that are in use, is valid and has SB list */ -+ if (!epid_inuse(epid) || epid == INVALID_EPID || -+ TxIsocEPList[epid].sub == 0 || epid == DUMMY_EPID) { -+ /* Nothing here to see. */ -+ continue; -+ } -+ ASSERT(epid_isoc(epid)); -+ -+ /* Get the active URB for this epid (if any). */ -+ urb = activeUrbList[epid]; -+ if (urb == 0) { -+ isoc_warn("Ignoring NULL urb for epid:%d\n", epid); -+ continue; -+ } -+ if(!epid_out_traffic(epid)) { -+ /* Sanity check. */ -+ ASSERT(usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS); -+ -+ urb_priv = (struct crisv10_urb_priv *)urb->hcpriv; -+ ASSERT(urb_priv); -+ -+ if (urb_priv->urb_state == NOT_STARTED) { -+ /* If ASAP is not set and urb->start_frame is the current frame, -+ start the transfer. */ -+ if (!(urb->transfer_flags & URB_ISO_ASAP) && -+ (urb->start_frame == (*R_USB_FM_NUMBER & 0x7ff))) { -+ /* EP should not be enabled if we're waiting for start_frame */ -+ ASSERT((TxIsocEPList[epid].command & -+ IO_STATE(USB_EP_command, enable, yes)) == 0); -+ -+ isoc_warn("Enabling isoc IN EP descr for epid %d\n", epid); -+ TxIsocEPList[epid].command |= IO_STATE(USB_EP_command, enable, yes); -+ -+ /* This urb is now active. */ -+ urb_priv->urb_state = STARTED; -+ continue; -+ } -+ } -+ } -+ } -+ -+ DBFEXIT; -+} -+ -+void crisv10_hcd_ctl_status_irq(struct crisv10_irq_reg *reg) -+{ -+ struct crisv10_hcd* crisv10_hcd = hcd_to_crisv10_hcd(reg->hcd); -+ -+ DBFENTER; -+ ASSERT(crisv10_hcd); -+ -+ irq_dbg("ctr_status_irq, controller status: %s\n", -+ hcd_status_to_str(reg->r_usb_status)); -+ -+ /* FIXME: What should we do if we get ourun or perror? Dump the EP and SB -+ list for the corresponding epid? */ -+ if (reg->r_usb_status & IO_MASK(R_USB_STATUS, ourun)) { -+ panic("USB controller got ourun."); -+ } -+ if (reg->r_usb_status & IO_MASK(R_USB_STATUS, perror)) { -+ -+ /* Before, etrax_usb_do_intr_recover was called on this epid if it was -+ an interrupt pipe. I don't see how re-enabling all EP descriptors -+ will help if there was a programming error. */ -+ panic("USB controller got perror."); -+ } -+ -+ /* Keep track of USB Controller, if it's running or not */ -+ if(reg->r_usb_status & IO_STATE(R_USB_STATUS, running, yes)) { -+ crisv10_hcd->running = 1; -+ } else { -+ crisv10_hcd->running = 0; -+ } -+ -+ if (reg->r_usb_status & IO_MASK(R_USB_STATUS, device_mode)) { -+ /* We should never operate in device mode. */ -+ panic("USB controller in device mode."); -+ } -+ -+ /* Set the flag to avoid getting "Unlink after no-IRQ? Controller is probably -+ using the wrong IRQ" from hcd_unlink_urb() in drivers/usb/core/hcd.c */ -+ set_bit(HCD_FLAG_SAW_IRQ, ®->hcd->flags); -+ -+ DBFEXIT; -+} -+ -+ -+/******************************************************************/ -+/* Host Controller interface functions */ -+/******************************************************************/ -+ -+static inline void crisv10_ready_wait(void) { -+ volatile int timeout = 10000; -+ /* Check the busy bit of USB controller in Etrax */ -+ while((*R_USB_COMMAND & IO_MASK(R_USB_COMMAND, busy)) && -+ (timeout-- > 0)); -+ if(timeout == 0) { -+ warn("Timeout while waiting for USB controller to be idle\n"); -+ } -+} -+ -+/* reset host controller */ -+static int crisv10_hcd_reset(struct usb_hcd *hcd) -+{ -+ DBFENTER; -+ hcd_dbg(hcd, "reset\n"); -+ -+ -+ /* Reset the USB interface. */ -+ /* -+ *R_USB_COMMAND = -+ IO_STATE(R_USB_COMMAND, port_sel, nop) | -+ IO_STATE(R_USB_COMMAND, port_cmd, reset) | -+ IO_STATE(R_USB_COMMAND, ctrl_cmd, reset); -+ nop(); -+ */ -+ DBFEXIT; -+ return 0; -+} -+ -+/* start host controller */ -+static int crisv10_hcd_start(struct usb_hcd *hcd) -+{ -+ DBFENTER; -+ hcd_dbg(hcd, "start\n"); -+ -+ crisv10_ready_wait(); -+ -+ /* Start processing of USB traffic. */ -+ *R_USB_COMMAND = -+ IO_STATE(R_USB_COMMAND, port_sel, nop) | -+ IO_STATE(R_USB_COMMAND, port_cmd, reset) | -+ IO_STATE(R_USB_COMMAND, ctrl_cmd, host_run); -+ -+ nop(); -+ -+ hcd->state = HC_STATE_RUNNING; -+ -+ DBFEXIT; -+ return 0; -+} -+ -+/* stop host controller */ -+static void crisv10_hcd_stop(struct usb_hcd *hcd) -+{ -+ DBFENTER; -+ hcd_dbg(hcd, "stop\n"); -+ crisv10_hcd_reset(hcd); -+ DBFEXIT; -+} -+ -+/* return the current frame number */ -+static int crisv10_hcd_get_frame(struct usb_hcd *hcd) -+{ -+ DBFENTER; -+ DBFEXIT; -+ return (*R_USB_FM_NUMBER & 0x7ff); -+} -+ -+#ifdef CONFIG_USB_OTG -+ -+static int crisv10_hcd_start_port_reset(struct usb_hcd *hcd, unsigned port) -+{ -+ return 0; /* no-op for now */ -+} -+ -+#endif /* CONFIG_USB_OTG */ -+ -+ -+/******************************************************************/ -+/* Root Hub functions */ -+/******************************************************************/ -+ -+/* root hub status */ -+static const struct usb_hub_status rh_hub_status = -+ { -+ .wHubStatus = 0, -+ .wHubChange = 0, -+ }; -+ -+/* root hub descriptor */ -+static const u8 rh_hub_descr[] = -+ { -+ 0x09, /* bDescLength */ -+ 0x29, /* bDescriptorType */ -+ USB_ROOT_HUB_PORTS, /* bNbrPorts */ -+ 0x00, /* wHubCharacteristics */ -+ 0x00, -+ 0x01, /* bPwrOn2pwrGood */ -+ 0x00, /* bHubContrCurrent */ -+ 0x00, /* DeviceRemovable */ -+ 0xff /* PortPwrCtrlMask */ -+ }; -+ -+/* Actual holder of root hub status*/ -+struct crisv10_rh rh; -+ -+/* Initialize root hub data structures (called from dvdrv_hcd_probe()) */ -+int rh_init(void) { -+ int i; -+ /* Reset port status flags */ -+ for (i = 0; i < USB_ROOT_HUB_PORTS; i++) { -+ rh.wPortChange[i] = 0; -+ rh.wPortStatusPrev[i] = 0; -+ } -+ return 0; -+} -+ -+#define RH_FEAT_MASK ((1<lock); -+ for (i = 1; i <= crisv10_hcd->num_ports; i++) { -+ if (rh.wPortChange[map_port(i)]) { -+ *buf |= (1 << i); -+ rh_dbg("rh_status_data_request, change on port %d: %s Current Status: %s\n", i, -+ port_status_to_str(rh.wPortChange[map_port(i)]), -+ port_status_to_str(rh.wPortStatusPrev[map_port(i)])); -+ } -+ } -+ spin_unlock(&crisv10_hcd->lock); -+ -+// DBFEXIT; -+ -+ return *buf == 0 ? 0 : 1; -+} -+ -+/* Handle a control request for the root hub (called from hcd_driver) */ -+static int rh_control_request(struct usb_hcd *hcd, -+ u16 typeReq, -+ u16 wValue, -+ u16 wIndex, -+ char *buf, -+ u16 wLength) { -+ -+ struct crisv10_hcd *crisv10_hcd = hcd_to_crisv10_hcd(hcd); -+ int retval = 0; -+ int len; -+ DBFENTER; -+ -+ switch (typeReq) { -+ case GetHubDescriptor: -+ rh_dbg("GetHubDescriptor\n"); -+ len = min_t(unsigned int, sizeof rh_hub_descr, wLength); -+ memcpy(buf, rh_hub_descr, len); -+ buf[2] = crisv10_hcd->num_ports; -+ break; -+ case GetHubStatus: -+ rh_dbg("GetHubStatus\n"); -+ len = min_t(unsigned int, sizeof rh_hub_status, wLength); -+ memcpy(buf, &rh_hub_status, len); -+ break; -+ case GetPortStatus: -+ if (!wIndex || wIndex > crisv10_hcd->num_ports) -+ goto error; -+ rh_dbg("GetportStatus, port:%d change:%s status:%s\n", wIndex, -+ port_status_to_str(rh.wPortChange[map_port(wIndex)]), -+ port_status_to_str(rh.wPortStatusPrev[map_port(wIndex)])); -+ *(u16 *) buf = cpu_to_le16(rh.wPortStatusPrev[map_port(wIndex)]); -+ *(u16 *) (buf + 2) = cpu_to_le16(rh.wPortChange[map_port(wIndex)]); -+ break; -+ case SetHubFeature: -+ rh_dbg("SetHubFeature\n"); -+ case ClearHubFeature: -+ rh_dbg("ClearHubFeature\n"); -+ switch (wValue) { -+ case C_HUB_OVER_CURRENT: -+ case C_HUB_LOCAL_POWER: -+ rh_warn("Not implemented hub request:%d \n", typeReq); -+ /* not implemented */ -+ break; -+ default: -+ goto error; -+ } -+ break; -+ case SetPortFeature: -+ if (!wIndex || wIndex > crisv10_hcd->num_ports) -+ goto error; -+ if(rh_set_port_feature(map_port(wIndex), wValue)) -+ goto error; -+ break; -+ case ClearPortFeature: -+ if (!wIndex || wIndex > crisv10_hcd->num_ports) -+ goto error; -+ if(rh_clear_port_feature(map_port(wIndex), wValue)) -+ goto error; -+ break; -+ default: -+ rh_warn("Unknown hub request: %d\n", typeReq); -+ error: -+ retval = -EPIPE; -+ } -+ DBFEXIT; -+ return retval; -+} -+ -+int rh_set_port_feature(__u8 bPort, __u16 wFeature) { -+ __u8 bUsbCommand = 0; -+ switch(wFeature) { -+ case USB_PORT_FEAT_RESET: -+ rh_dbg("SetPortFeature: reset\n"); -+ bUsbCommand |= IO_STATE(R_USB_COMMAND, port_cmd, reset); -+ goto set; -+ break; -+ case USB_PORT_FEAT_SUSPEND: -+ rh_dbg("SetPortFeature: suspend\n"); -+ bUsbCommand |= IO_STATE(R_USB_COMMAND, port_cmd, suspend); -+ goto set; -+ break; -+ case USB_PORT_FEAT_POWER: -+ rh_dbg("SetPortFeature: power\n"); -+ break; -+ case USB_PORT_FEAT_C_CONNECTION: -+ rh_dbg("SetPortFeature: c_connection\n"); -+ break; -+ case USB_PORT_FEAT_C_RESET: -+ rh_dbg("SetPortFeature: c_reset\n"); -+ break; -+ case USB_PORT_FEAT_C_OVER_CURRENT: -+ rh_dbg("SetPortFeature: c_over_current\n"); -+ break; -+ -+ set: -+ /* Select which port via the port_sel field */ -+ bUsbCommand |= IO_FIELD(R_USB_COMMAND, port_sel, bPort+1); -+ -+ /* Make sure the controller isn't busy. */ -+ crisv10_ready_wait(); -+ /* Send out the actual command to the USB controller */ -+ *R_USB_COMMAND = bUsbCommand; -+ -+ /* If port reset then also bring USB controller into running state */ -+ if(wFeature == USB_PORT_FEAT_RESET) { -+ /* Wait a while for controller to first become started after port reset */ -+ udelay(12000); /* 12ms blocking wait */ -+ -+ /* Make sure the controller isn't busy. */ -+ crisv10_ready_wait(); -+ -+ /* If all enabled ports were disabled the host controller goes down into -+ started mode, so we need to bring it back into the running state. -+ (This is safe even if it's already in the running state.) */ -+ *R_USB_COMMAND = -+ IO_STATE(R_USB_COMMAND, port_sel, nop) | -+ IO_STATE(R_USB_COMMAND, port_cmd, reset) | -+ IO_STATE(R_USB_COMMAND, ctrl_cmd, host_run); -+ } -+ -+ break; -+ default: -+ rh_dbg("SetPortFeature: unknown feature\n"); -+ return -1; -+ } -+ return 0; -+} -+ -+int rh_clear_port_feature(__u8 bPort, __u16 wFeature) { -+ switch(wFeature) { -+ case USB_PORT_FEAT_ENABLE: -+ rh_dbg("ClearPortFeature: enable\n"); -+ rh_disable_port(bPort); -+ break; -+ case USB_PORT_FEAT_SUSPEND: -+ rh_dbg("ClearPortFeature: suspend\n"); -+ break; -+ case USB_PORT_FEAT_POWER: -+ rh_dbg("ClearPortFeature: power\n"); -+ break; -+ -+ case USB_PORT_FEAT_C_ENABLE: -+ rh_dbg("ClearPortFeature: c_enable\n"); -+ goto clear; -+ case USB_PORT_FEAT_C_SUSPEND: -+ rh_dbg("ClearPortFeature: c_suspend\n"); -+ goto clear; -+ case USB_PORT_FEAT_C_CONNECTION: -+ rh_dbg("ClearPortFeature: c_connection\n"); -+ goto clear; -+ case USB_PORT_FEAT_C_OVER_CURRENT: -+ rh_dbg("ClearPortFeature: c_over_current\n"); -+ goto clear; -+ case USB_PORT_FEAT_C_RESET: -+ rh_dbg("ClearPortFeature: c_reset\n"); -+ goto clear; -+ clear: -+ rh.wPortChange[bPort] &= ~(1 << (wFeature - 16)); -+ break; -+ default: -+ rh_dbg("ClearPortFeature: unknown feature\n"); -+ return -1; -+ } -+ return 0; -+} -+ -+ -+#ifdef CONFIG_PM -+/* Handle a suspend request for the root hub (called from hcd_driver) */ -+static int rh_suspend_request(struct usb_hcd *hcd) -+{ -+ return 0; /* no-op for now */ -+} -+ -+/* Handle a resume request for the root hub (called from hcd_driver) */ -+static int rh_resume_request(struct usb_hcd *hcd) -+{ -+ return 0; /* no-op for now */ -+} -+#endif /* CONFIG_PM */ -+ -+ -+ -+/* Wrapper function for workaround port disable registers in USB controller */ -+static void rh_disable_port(unsigned int port) { -+ volatile int timeout = 10000; -+ volatile char* usb_portx_disable; -+ switch(port) { -+ case 0: -+ usb_portx_disable = R_USB_PORT1_DISABLE; -+ break; -+ case 1: -+ usb_portx_disable = R_USB_PORT2_DISABLE; -+ break; -+ default: -+ /* Invalid port index */ -+ return; -+ } -+ /* Set disable flag in special register */ -+ *usb_portx_disable = IO_STATE(R_USB_PORT1_DISABLE, disable, yes); -+ /* Wait until not enabled anymore */ -+ while((rh.wPortStatusPrev[port] & -+ IO_STATE(R_USB_RH_PORT_STATUS_1, enabled, yes)) && -+ (timeout-- > 0)); -+ if(timeout == 0) { -+ warn("Timeout while waiting for port %d to become disabled\n", port); -+ } -+ /* clear disable flag in special register */ -+ *usb_portx_disable = IO_STATE(R_USB_PORT1_DISABLE, disable, no); -+ rh_info("Physical port %d disabled\n", port+1); -+} -+ -+ -+/******************************************************************/ -+/* Transfer Controller (TC) functions */ -+/******************************************************************/ -+ -+/* FIXME: Should RX_BUF_SIZE be a config option, or maybe we should adjust it -+ dynamically? -+ To adjust it dynamically we would have to get an interrupt when we reach -+ the end of the rx descriptor list, or when we get close to the end, and -+ then allocate more descriptors. */ -+#define NBR_OF_RX_DESC 512 -+#define RX_DESC_BUF_SIZE 1024 -+#define RX_BUF_SIZE (NBR_OF_RX_DESC * RX_DESC_BUF_SIZE) -+ -+ -+/* Local variables for Transfer Controller */ -+/* --------------------------------------- */ -+ -+/* This is a circular (double-linked) list of the active urbs for each epid. -+ The head is never removed, and new urbs are linked onto the list as -+ urb_entry_t elements. Don't reference urb_list directly; use the wrapper -+ functions instead (which includes spin_locks) */ -+static struct list_head urb_list[NBR_OF_EPIDS]; -+ -+/* Read about the need and usage of this lock in submit_ctrl_urb. */ -+/* Lock for URB lists for each EPID */ -+static spinlock_t urb_list_lock; -+ -+/* Lock for EPID array register (R_USB_EPT_x) in Etrax */ -+static spinlock_t etrax_epid_lock; -+ -+/* Lock for dma8 sub0 handling */ -+static spinlock_t etrax_dma8_sub0_lock; -+ -+/* DMA IN cache bug. Align the DMA IN buffers to 32 bytes, i.e. a cache line. -+ Since RX_DESC_BUF_SIZE is 1024 is a multiple of 32, all rx buffers will be -+ cache aligned. */ -+static volatile unsigned char RxBuf[RX_BUF_SIZE] __attribute__ ((aligned (32))); -+static volatile struct USB_IN_Desc RxDescList[NBR_OF_RX_DESC] __attribute__ ((aligned (4))); -+ -+/* Pointers into RxDescList. */ -+static volatile struct USB_IN_Desc *myNextRxDesc; -+static volatile struct USB_IN_Desc *myLastRxDesc; -+ -+/* A zout transfer makes a memory access at the address of its buf pointer, -+ which means that setting this buf pointer to 0 will cause an access to the -+ flash. In addition to this, setting sw_len to 0 results in a 16/32 bytes -+ (depending on DMA burst size) transfer. -+ Instead, we set it to 1, and point it to this buffer. */ -+static int zout_buffer[4] __attribute__ ((aligned (4))); -+ -+/* Cache for allocating new EP and SB descriptors. */ -+//static kmem_cache_t *usb_desc_cache; -+static struct kmem_cache *usb_desc_cache; -+ -+/* Cache for the data allocated in the isoc descr top half. */ -+//static kmem_cache_t *isoc_compl_cache; -+static struct kmem_cache *isoc_compl_cache; -+ -+/* Cache for the data allocated when delayed finishing of URBs */ -+//static kmem_cache_t *later_data_cache; -+static struct kmem_cache *later_data_cache; -+ -+/* Counter to keep track of how many Isoc EP we have sat up. Used to enable -+ and disable iso_eof interrupt. We only need these interrupts when we have -+ Isoc data endpoints (consumes CPU cycles). -+ FIXME: This could be more fine granular, so this interrupt is only enabled -+ when we have a In Isoc URB not URB_ISO_ASAP flaged queued. */ -+static int isoc_epid_counter; -+ -+/* Protecting wrapper functions for R_USB_EPT_x */ -+/* -------------------------------------------- */ -+static inline void etrax_epid_set(__u8 index, __u32 data) { -+ unsigned long flags; -+ spin_lock_irqsave(&etrax_epid_lock, flags); -+ *R_USB_EPT_INDEX = IO_FIELD(R_USB_EPT_INDEX, value, index); -+ nop(); -+ *R_USB_EPT_DATA = data; -+ spin_unlock_irqrestore(&etrax_epid_lock, flags); -+} -+ -+static inline void etrax_epid_clear_error(__u8 index) { -+ unsigned long flags; -+ spin_lock_irqsave(&etrax_epid_lock, flags); -+ *R_USB_EPT_INDEX = IO_FIELD(R_USB_EPT_INDEX, value, index); -+ nop(); -+ *R_USB_EPT_DATA &= -+ ~(IO_MASK(R_USB_EPT_DATA, error_count_in) | -+ IO_MASK(R_USB_EPT_DATA, error_count_out) | -+ IO_MASK(R_USB_EPT_DATA, error_code)); -+ spin_unlock_irqrestore(&etrax_epid_lock, flags); -+} -+ -+static inline void etrax_epid_set_toggle(__u8 index, __u8 dirout, -+ __u8 toggle) { -+ unsigned long flags; -+ spin_lock_irqsave(&etrax_epid_lock, flags); -+ *R_USB_EPT_INDEX = IO_FIELD(R_USB_EPT_INDEX, value, index); -+ nop(); -+ if(dirout) { -+ *R_USB_EPT_DATA &= ~IO_MASK(R_USB_EPT_DATA, t_out); -+ *R_USB_EPT_DATA |= IO_FIELD(R_USB_EPT_DATA, t_out, toggle); -+ } else { -+ *R_USB_EPT_DATA &= ~IO_MASK(R_USB_EPT_DATA, t_in); -+ *R_USB_EPT_DATA |= IO_FIELD(R_USB_EPT_DATA, t_in, toggle); -+ } -+ spin_unlock_irqrestore(&etrax_epid_lock, flags); -+} -+ -+static inline __u8 etrax_epid_get_toggle(__u8 index, __u8 dirout) { -+ unsigned long flags; -+ __u8 toggle; -+ spin_lock_irqsave(&etrax_epid_lock, flags); -+ *R_USB_EPT_INDEX = IO_FIELD(R_USB_EPT_INDEX, value, index); -+ nop(); -+ if (dirout) { -+ toggle = IO_EXTRACT(R_USB_EPT_DATA, t_out, *R_USB_EPT_DATA); -+ } else { -+ toggle = IO_EXTRACT(R_USB_EPT_DATA, t_in, *R_USB_EPT_DATA); -+ } -+ spin_unlock_irqrestore(&etrax_epid_lock, flags); -+ return toggle; -+} -+ -+ -+static inline __u32 etrax_epid_get(__u8 index) { -+ unsigned long flags; -+ __u32 data; -+ spin_lock_irqsave(&etrax_epid_lock, flags); -+ *R_USB_EPT_INDEX = IO_FIELD(R_USB_EPT_INDEX, value, index); -+ nop(); -+ data = *R_USB_EPT_DATA; -+ spin_unlock_irqrestore(&etrax_epid_lock, flags); -+ return data; -+} -+ -+ -+ -+ -+/* Main functions for Transfer Controller */ -+/* -------------------------------------- */ -+ -+/* Init structs, memories and lists used by Transfer Controller */ -+int tc_init(struct usb_hcd *hcd) { -+ int i; -+ /* Clear software state info for all epids */ -+ memset(epid_state, 0, sizeof(struct etrax_epid) * NBR_OF_EPIDS); -+ -+ /* Set Invalid and Dummy as being in use and disabled */ -+ epid_state[INVALID_EPID].inuse = 1; -+ epid_state[DUMMY_EPID].inuse = 1; -+ epid_state[INVALID_EPID].disabled = 1; -+ epid_state[DUMMY_EPID].disabled = 1; -+ -+ /* Clear counter for how many Isoc epids we have sat up */ -+ isoc_epid_counter = 0; -+ -+ /* Initialize the urb list by initiating a head for each list. -+ Also reset list hodling active URB for each epid */ -+ for (i = 0; i < NBR_OF_EPIDS; i++) { -+ INIT_LIST_HEAD(&urb_list[i]); -+ activeUrbList[i] = NULL; -+ } -+ -+ /* Init lock for URB lists */ -+ spin_lock_init(&urb_list_lock); -+ /* Init lock for Etrax R_USB_EPT register */ -+ spin_lock_init(&etrax_epid_lock); -+ /* Init lock for Etrax dma8 sub0 handling */ -+ spin_lock_init(&etrax_dma8_sub0_lock); -+ -+ /* We use kmem_cache_* to make sure that all DMA desc. are dword aligned */ -+ -+ /* Note that we specify sizeof(struct USB_EP_Desc) as the size, but also -+ allocate SB descriptors from this cache. This is ok since -+ sizeof(struct USB_EP_Desc) == sizeof(struct USB_SB_Desc). */ -+// usb_desc_cache = kmem_cache_create("usb_desc_cache", -+// sizeof(struct USB_EP_Desc), 0, -+// SLAB_HWCACHE_ALIGN, 0, 0); -+ usb_desc_cache = kmem_cache_create( -+ "usb_desc_cache", -+ sizeof(struct USB_EP_Desc), -+ 0, -+ SLAB_HWCACHE_ALIGN, -+ NULL); -+ if(usb_desc_cache == NULL) { -+ return -ENOMEM; -+ } -+ -+ /* Create slab cache for speedy allocation of memory for isoc bottom-half -+ interrupt handling */ -+// isoc_compl_cache = -+// kmem_cache_create("isoc_compl_cache", -+// sizeof(struct crisv10_isoc_complete_data), -+// 0, SLAB_HWCACHE_ALIGN, 0, 0); -+ isoc_compl_cache = kmem_cache_create( -+ "isoc_compl_cache", -+ sizeof(struct crisv10_isoc_complete_data), -+ 0, -+ SLAB_HWCACHE_ALIGN, -+ NULL -+ ); -+ -+ if(isoc_compl_cache == NULL) { -+ return -ENOMEM; -+ } -+ -+ /* Create slab cache for speedy allocation of memory for later URB finish -+ struct */ -+// later_data_cache = -+// kmem_cache_create("later_data_cache", -+// sizeof(struct urb_later_data), -+// 0, SLAB_HWCACHE_ALIGN, 0, 0); -+ -+ later_data_cache = kmem_cache_create( -+ "later_data_cache", -+ sizeof(struct urb_later_data), -+ 0, -+ SLAB_HWCACHE_ALIGN, -+ NULL -+ ); -+ -+ if(later_data_cache == NULL) { -+ return -ENOMEM; -+ } -+ -+ -+ /* Initiate the bulk start timer. */ -+ init_timer(&bulk_start_timer); -+ bulk_start_timer.expires = jiffies + BULK_START_TIMER_INTERVAL; -+ bulk_start_timer.function = tc_bulk_start_timer_func; -+ add_timer(&bulk_start_timer); -+ -+ -+ /* Initiate the bulk eot timer. */ -+ init_timer(&bulk_eot_timer); -+ bulk_eot_timer.expires = jiffies + BULK_EOT_TIMER_INTERVAL; -+ bulk_eot_timer.function = tc_bulk_eot_timer_func; -+ bulk_eot_timer.data = (unsigned long)hcd; -+ add_timer(&bulk_eot_timer); -+ -+ return 0; -+} -+ -+/* Uninitialize all resources used by Transfer Controller */ -+void tc_destroy(void) { -+ -+ /* Destroy all slab cache */ -+ kmem_cache_destroy(usb_desc_cache); -+ kmem_cache_destroy(isoc_compl_cache); -+ kmem_cache_destroy(later_data_cache); -+ -+ /* Remove timers */ -+ del_timer(&bulk_start_timer); -+ del_timer(&bulk_eot_timer); -+} -+ -+static void restart_dma8_sub0(void) { -+ unsigned long flags; -+ spin_lock_irqsave(&etrax_dma8_sub0_lock, flags); -+ /* Verify that the dma is not running */ -+ if ((*R_DMA_CH8_SUB0_CMD & IO_MASK(R_DMA_CH8_SUB0_CMD, cmd)) == 0) { -+ struct USB_EP_Desc *ep = (struct USB_EP_Desc *)phys_to_virt(*R_DMA_CH8_SUB0_EP); -+ while (DUMMY_EPID == IO_EXTRACT(USB_EP_command, epid, ep->command)) { -+ ep = (struct USB_EP_Desc *)phys_to_virt(ep->next); -+ } -+ /* Advance the DMA to the next EP descriptor that is not a DUMMY_EPID. -+ * ep->next is already a physical address. virt_to_phys is needed, see -+ * http://mhonarc.axis.se/dev-etrax/msg08630.html -+ */ -+ //*R_DMA_CH8_SUB0_EP = ep->next; -+ *R_DMA_CH8_SUB0_EP = virt_to_phys(ep); -+ /* Restart the DMA */ -+ *R_DMA_CH8_SUB0_CMD = IO_STATE(R_DMA_CH8_SUB0_CMD, cmd, start); -+ } -+ spin_unlock_irqrestore(&etrax_dma8_sub0_lock, flags); -+} -+ -+/* queue an URB with the transfer controller (called from hcd_driver) */ -+//static int tc_urb_enqueue(struct usb_hcd *hcd, -+// struct usb_host_endpoint *ep, -+// struct urb *urb, -+// gfp_t mem_flags) { -+static int tc_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags) -+{ -+ int epid; -+ int retval; -+// int bustime = 0; -+ int maxpacket; -+ unsigned long flags; -+ struct crisv10_urb_priv *urb_priv; -+ struct crisv10_hcd* crisv10_hcd = hcd_to_crisv10_hcd(hcd); -+ DBFENTER; -+ -+ if(!(crisv10_hcd->running)) { -+ /* The USB Controller is not running, probably because no device is -+ attached. No idea to enqueue URBs then */ -+ tc_warn("Rejected enqueueing of URB:0x%x because no dev attached\n", -+ (unsigned int)urb); -+ return -ENOENT; -+ } -+ -+ maxpacket = usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)); -+ -+ /* hinko ignore usb_pipeisoc */ -+#if 0 -+ /* Special case check for In Isoc transfers. Specification states that each -+ In Isoc transfer consists of one packet and therefore it should fit into -+ the transfer-buffer of an URB. -+ We do the check here to be sure (an invalid scenario can be produced with -+ parameters to the usbtest suite) */ -+ if(usb_pipeisoc(urb->pipe) && usb_pipein(urb->pipe) && -+ (urb->transfer_buffer_length < maxpacket)) { -+ tc_err("Submit In Isoc URB with buffer length:%d to pipe with maxpacketlen: %d\n", urb->transfer_buffer_length, maxpacket); -+ return -EMSGSIZE; -+ } -+ -+ /* Check if there is enough bandwidth for periodic transfer */ -+ if(usb_pipeint(urb->pipe) || usb_pipeisoc(urb->pipe)) { -+ /* only check (and later claim) if not already claimed */ -+ if (urb->bandwidth == 0) { -+ bustime = usb_check_bandwidth(urb->dev, urb); -+ if (bustime < 0) { -+ tc_err("Not enough periodic bandwidth\n"); -+ return -ENOSPC; -+ } -+ } -+ } -+#endif -+ -+ /* Check if there is a epid for URBs destination, if not this function -+ set up one. */ -+ //epid = tc_setup_epid(ep, urb, mem_flags); -+ epid = tc_setup_epid(urb, mem_flags); -+ if (epid < 0) { -+ tc_err("Failed setup epid:%d for URB:0x%x\n", epid, (unsigned int)urb); -+ DBFEXIT; -+ return -ENOMEM; -+ } -+ -+ if(urb == activeUrbList[epid]) { -+ tc_err("Resubmition of allready active URB:0x%x\n", (unsigned int)urb); -+ return -ENXIO; -+ } -+ -+ if(urb_list_entry(urb, epid)) { -+ tc_err("Resubmition of allready queued URB:0x%x\n", (unsigned int)urb); -+ return -ENXIO; -+ } -+ -+ /* If we actively have flaged endpoint as disabled then refuse submition */ -+ if(epid_state[epid].disabled) { -+ return -ENOENT; -+ } -+ -+ /* Allocate and init HC-private data for URB */ -+ if(urb_priv_create(hcd, urb, epid, mem_flags) != 0) { -+ DBFEXIT; -+ return -ENOMEM; -+ } -+ urb_priv = urb->hcpriv; -+ -+ tc_dbg("Enqueue URB:0x%x[%d] epid:%d (%s) bufflen:%d\n", -+ (unsigned int)urb, urb_priv->urb_num, epid, -+ pipe_to_str(urb->pipe), urb->transfer_buffer_length); -+ -+ /* Create and link SBs required for this URB */ -+ retval = create_sb_for_urb(urb, mem_flags); -+ if(retval != 0) { -+ tc_err("Failed to create SBs for URB:0x%x[%d]\n", (unsigned int)urb, -+ urb_priv->urb_num); -+ urb_priv_free(hcd, urb); -+ DBFEXIT; -+ return retval; -+ } -+ -+ /* Init intr EP pool if this URB is a INTR transfer. This pool is later -+ used when inserting EPs in the TxIntrEPList. We do the alloc here -+ so we can't run out of memory later */ -+ if(usb_pipeint(urb->pipe)) { -+ retval = init_intr_urb(urb, mem_flags); -+ if(retval != 0) { -+ tc_warn("Failed to init Intr URB\n"); -+ urb_priv_free(hcd, urb); -+ DBFEXIT; -+ return retval; -+ } -+ } -+ -+ /* Disable other access when inserting USB */ -+ -+ /* BUG on sleeping inside int disabled if using local_irq_save/local_irq_restore -+ * her - because urb_list_add() and tc_dma_process_queue() save irqs again !??! -+ */ -+// local_irq_save(flags); -+ -+ /* hinko ignore usb_pipeisoc */ -+#if 0 -+ /* Claim bandwidth, if needed */ -+ if(bustime) { -+ usb_claim_bandwidth(urb->dev, urb, bustime, 0); -+ } -+ -+ /* Add URB to EP queue */ -+ urb_list_add(urb, epid, mem_flags); -+ -+ if(usb_pipeisoc(urb->pipe)) { -+ /* Special processing of Isoc URBs. */ -+ tc_dma_process_isoc_urb(urb); -+ } else { -+ /* Process EP queue for rest of the URB types (Bulk, Ctrl, Intr) */ -+ tc_dma_process_queue(epid); -+ } -+#endif -+ /* Add URB to EP queue */ -+ urb_list_add(urb, epid, mem_flags); -+ -+ /*hinko link/unlink urb -> ep */ -+ spin_lock_irqsave(&crisv10_hcd->lock, flags); -+ //spin_lock(&crisv10_hcd->lock); -+ retval = usb_hcd_link_urb_to_ep(hcd, urb); -+ if (retval) { -+ spin_unlock_irqrestore(&crisv10_hcd->lock, flags); -+ tc_warn("Failed to link urb to ep\n"); -+ urb_priv_free(hcd, urb); -+ DBFEXIT; -+ return retval; -+ } -+ spin_unlock_irqrestore(&crisv10_hcd->lock, flags); -+ //spin_unlock(&crisv10_hcd->lock); -+ -+ /* Process EP queue for rest of the URB types (Bulk, Ctrl, Intr) */ -+ tc_dma_process_queue(epid); -+ -+// local_irq_restore(flags); -+ -+ DBFEXIT; -+ return 0; -+} -+ -+/* remove an URB from the transfer controller queues (called from hcd_driver)*/ -+//static int tc_urb_dequeue(struct usb_hcd *hcd, struct urb *urb) -+static int tc_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) -+{ -+ struct crisv10_urb_priv *urb_priv; -+ unsigned long flags; -+ int epid; -+ -+ DBFENTER; -+ /* Disable interrupts here since a descriptor interrupt for the isoc epid -+ will modify the sb list. This could possibly be done more granular, but -+ urb_dequeue should not be used frequently anyway. -+ */ -+ local_irq_save(flags); -+ -+ urb_priv = urb->hcpriv; -+ -+ if (!urb_priv) { -+ /* This happens if a device driver calls unlink on an urb that -+ was never submitted (lazy driver) or if the urb was completed -+ while dequeue was being called. */ -+ tc_warn("Dequeing of not enqueued URB:0x%x\n", (unsigned int)urb); -+ local_irq_restore(flags); -+ return 0; -+ } -+ epid = urb_priv->epid; -+ -+ tc_warn("Dequeing %s URB:0x%x[%d] (%s %s epid:%d) status:%d %s\n", -+ (urb == activeUrbList[epid]) ? "active" : "queued", -+ (unsigned int)urb, urb_priv->urb_num, str_dir(urb->pipe), -+ str_type(urb->pipe), epid, urb->status, -+ (urb_priv->later_data) ? "later-sched" : ""); -+ -+ /* For Bulk, Ctrl and Intr are only one URB active at a time. So any URB -+ that isn't active can be dequeued by just removing it from the queue */ -+ if(usb_pipebulk(urb->pipe) || usb_pipecontrol(urb->pipe) || -+ usb_pipeint(urb->pipe)) { -+ -+ /* Check if URB haven't gone further than the queue */ -+ if(urb != activeUrbList[epid]) { -+ ASSERT(urb_priv->later_data == NULL); -+ tc_warn("Dequeing URB:0x%x[%d] (%s %s epid:%d) from queue" -+ " (not active)\n", (unsigned int)urb, urb_priv->urb_num, -+ str_dir(urb->pipe), str_type(urb->pipe), epid); -+ -+ /* Finish the URB with error status from USB core */ -+ tc_finish_urb(hcd, urb, urb->status); -+ local_irq_restore(flags); -+ return 0; -+ } -+ } -+ -+ /* Set URB status to Unlink for handling when interrupt comes. */ -+ urb_priv->urb_state = UNLINK; -+ -+ /* Differentiate dequeing of Bulk and Ctrl from Isoc and Intr */ -+ switch(usb_pipetype(urb->pipe)) { -+ case PIPE_BULK: -+ /* Check if EP still is enabled */ -+ if (TxBulkEPList[epid].command & IO_MASK(USB_EP_command, enable)) { -+ /* The EP was enabled, disable it. */ -+ TxBulkEPList[epid].command &= ~IO_MASK(USB_EP_command, enable); -+ } -+ /* Kicking dummy list out of the party. */ -+ TxBulkEPList[epid].next = virt_to_phys(&TxBulkEPList[(epid + 1) % NBR_OF_EPIDS]); -+ break; -+ case PIPE_CONTROL: -+ /* Check if EP still is enabled */ -+ if (TxCtrlEPList[epid].command & IO_MASK(USB_EP_command, enable)) { -+ /* The EP was enabled, disable it. */ -+ TxCtrlEPList[epid].command &= ~IO_MASK(USB_EP_command, enable); -+ } -+ break; -+ case PIPE_ISOCHRONOUS: -+ /* Disabling, busy-wait and unlinking of Isoc SBs will be done in -+ finish_isoc_urb(). Because there might the case when URB is dequeued -+ but there are other valid URBs waiting */ -+ -+ /* Check if In Isoc EP still is enabled */ -+ if (TxIsocEPList[epid].command & IO_MASK(USB_EP_command, enable)) { -+ /* The EP was enabled, disable it. */ -+ TxIsocEPList[epid].command &= ~IO_MASK(USB_EP_command, enable); -+ } -+ break; -+ case PIPE_INTERRUPT: -+ /* Special care is taken for interrupt URBs. EPs are unlinked in -+ tc_finish_urb */ -+ break; -+ default: -+ break; -+ } -+ -+ /* Asynchronous unlink, finish the URB later from scheduled or other -+ event (data finished, error) */ -+ tc_finish_urb_later(hcd, urb, urb->status); -+ -+ local_irq_restore(flags); -+ DBFEXIT; -+ return 0; -+} -+ -+ -+static void tc_sync_finish_epid(struct usb_hcd *hcd, int epid) { -+ volatile int timeout = 10000; -+ struct urb* urb; -+ struct crisv10_urb_priv* urb_priv; -+ unsigned long flags; -+ -+ volatile struct USB_EP_Desc *first_ep; /* First EP in the list. */ -+ volatile struct USB_EP_Desc *curr_ep; /* Current EP, the iterator. */ -+ volatile struct USB_EP_Desc *next_ep; /* The EP after current. */ -+ -+ int type = epid_state[epid].type; -+ -+ /* Setting this flag will cause enqueue() to return -ENOENT for new -+ submitions on this endpoint and finish_urb() wont process queue further */ -+ epid_state[epid].disabled = 1; -+ -+ switch(type) { -+ case PIPE_BULK: -+ /* Check if EP still is enabled */ -+ if (TxBulkEPList[epid].command & IO_MASK(USB_EP_command, enable)) { -+ /* The EP was enabled, disable it. */ -+ TxBulkEPList[epid].command &= ~IO_MASK(USB_EP_command, enable); -+ tc_warn("sync_finish: Disabling EP for epid:%d\n", epid); -+ -+ /* Do busy-wait until DMA not using this EP descriptor anymore */ -+ while((*R_DMA_CH8_SUB0_EP == -+ virt_to_phys(&TxBulkEPList[epid])) && -+ (timeout-- > 0)); -+ if(timeout == 0) { -+ warn("Timeout while waiting for DMA-TX-Bulk to leave EP for" -+ " epid:%d\n", epid); -+ } -+ } -+ break; -+ -+ case PIPE_CONTROL: -+ /* Check if EP still is enabled */ -+ if (TxCtrlEPList[epid].command & IO_MASK(USB_EP_command, enable)) { -+ /* The EP was enabled, disable it. */ -+ TxCtrlEPList[epid].command &= ~IO_MASK(USB_EP_command, enable); -+ tc_warn("sync_finish: Disabling EP for epid:%d\n", epid); -+ -+ /* Do busy-wait until DMA not using this EP descriptor anymore */ -+ while((*R_DMA_CH8_SUB1_EP == -+ virt_to_phys(&TxCtrlEPList[epid])) && -+ (timeout-- > 0)); -+ if(timeout == 0) { -+ warn("Timeout while waiting for DMA-TX-Ctrl to leave EP for" -+ " epid:%d\n", epid); -+ } -+ } -+ break; -+ -+ case PIPE_INTERRUPT: -+ local_irq_save(flags); -+ /* Disable all Intr EPs belonging to epid */ -+ first_ep = &TxIntrEPList[0]; -+ curr_ep = first_ep; -+ do { -+ next_ep = (struct USB_EP_Desc *)phys_to_virt(curr_ep->next); -+ if (IO_EXTRACT(USB_EP_command, epid, next_ep->command) == epid) { -+ /* Disable EP */ -+ next_ep->command &= ~IO_MASK(USB_EP_command, enable); -+ } -+ curr_ep = phys_to_virt(curr_ep->next); -+ } while (curr_ep != first_ep); -+ -+ local_irq_restore(flags); -+ break; -+ -+ case PIPE_ISOCHRONOUS: -+ /* Check if EP still is enabled */ -+ if (TxIsocEPList[epid].command & IO_MASK(USB_EP_command, enable)) { -+ tc_warn("sync_finish: Disabling Isoc EP for epid:%d\n", epid); -+ /* The EP was enabled, disable it. */ -+ TxIsocEPList[epid].command &= ~IO_MASK(USB_EP_command, enable); -+ -+ while((*R_DMA_CH8_SUB3_EP == virt_to_phys(&TxIsocEPList[epid])) && -+ (timeout-- > 0)); -+ if(timeout == 0) { -+ warn("Timeout while waiting for DMA-TX-Isoc to leave EP for" -+ " epid:%d\n", epid); -+ } -+ } -+ break; -+ } -+ -+ local_irq_save(flags); -+ -+ /* Finish if there is active URB for this endpoint */ -+ if(activeUrbList[epid] != NULL) { -+ urb = activeUrbList[epid]; -+ urb_priv = urb->hcpriv; -+ ASSERT(urb_priv); -+ tc_warn("Sync finish %s URB:0x%x[%d] (%s %s epid:%d) status:%d %s\n", -+ (urb == activeUrbList[epid]) ? "active" : "queued", -+ (unsigned int)urb, urb_priv->urb_num, str_dir(urb->pipe), -+ str_type(urb->pipe), epid, urb->status, -+ (urb_priv->later_data) ? "later-sched" : ""); -+ -+ tc_finish_urb(hcd, activeUrbList[epid], -ENOENT); -+ ASSERT(activeUrbList[epid] == NULL); -+ } -+ -+ /* Finish any queued URBs for this endpoint. There won't be any resubmitions -+ because epid_disabled causes enqueue() to fail for this endpoint */ -+ while((urb = urb_list_first(epid)) != NULL) { -+ urb_priv = urb->hcpriv; -+ ASSERT(urb_priv); -+ -+ tc_warn("Sync finish %s URB:0x%x[%d] (%s %s epid:%d) status:%d %s\n", -+ (urb == activeUrbList[epid]) ? "active" : "queued", -+ (unsigned int)urb, urb_priv->urb_num, str_dir(urb->pipe), -+ str_type(urb->pipe), epid, urb->status, -+ (urb_priv->later_data) ? "later-sched" : ""); -+ -+ tc_finish_urb(hcd, urb, -ENOENT); -+ } -+ epid_state[epid].disabled = 0; -+ local_irq_restore(flags); -+} -+ -+/* free resources associated with an endpoint (called from hcd_driver) */ -+static void tc_endpoint_disable(struct usb_hcd *hcd, -+ struct usb_host_endpoint *ep) { -+ DBFENTER; -+ /* Only free epid if it has been allocated. We get two endpoint_disable -+ requests for ctrl endpoints so ignore the second one */ -+ if(ep->hcpriv != NULL) { -+ struct crisv10_ep_priv *ep_priv = ep->hcpriv; -+ int epid = ep_priv->epid; -+ tc_warn("endpoint_disable ep:0x%x ep-priv:0x%x (%s) (epid:%d freed)\n", -+ (unsigned int)ep, (unsigned int)ep->hcpriv, -+ endpoint_to_str(&(ep->desc)), epid); -+ -+ tc_sync_finish_epid(hcd, epid); -+ -+ ASSERT(activeUrbList[epid] == NULL); -+ ASSERT(list_empty(&urb_list[epid])); -+ -+ tc_free_epid(ep); -+ } else { -+ tc_dbg("endpoint_disable ep:0x%x ep-priv:0x%x (%s)\n", (unsigned int)ep, -+ (unsigned int)ep->hcpriv, endpoint_to_str(&(ep->desc))); -+ } -+ DBFEXIT; -+} -+ -+//static void tc_finish_urb_later_proc(void *data) { -+static void tc_finish_urb_later_proc(struct work_struct *work) { -+ unsigned long flags; -+ //struct urb_later_data* uld = (struct urb_later_data*)data; -+ struct urb_later_data* uld = container_of(work, struct urb_later_data, ws.work); -+ local_irq_save(flags); -+ if(uld->urb == NULL) { -+ late_dbg("Later finish of URB = NULL (allready finished)\n"); -+ } else { -+ struct crisv10_urb_priv* urb_priv = uld->urb->hcpriv; -+ ASSERT(urb_priv); -+ if(urb_priv->urb_num == uld->urb_num) { -+ late_dbg("Later finish of URB:0x%x[%d]\n", (unsigned int)(uld->urb), -+ urb_priv->urb_num); -+ if(uld->status != uld->urb->status) { -+ errno_dbg("Later-finish URB with status:%d, later-status:%d\n", -+ uld->urb->status, uld->status); -+ } -+ if(uld != urb_priv->later_data) { -+ panic("Scheduled uld not same as URBs uld\n"); -+ } -+ tc_finish_urb(uld->hcd, uld->urb, uld->status); -+ } else { -+ late_warn("Ignoring later finish of URB:0x%x[%d]" -+ ", urb_num doesn't match current URB:0x%x[%d]", -+ (unsigned int)(uld->urb), uld->urb_num, -+ (unsigned int)(uld->urb), urb_priv->urb_num); -+ } -+ } -+ local_irq_restore(flags); -+ kmem_cache_free(later_data_cache, uld); -+} -+ -+static void tc_finish_urb_later(struct usb_hcd *hcd, struct urb *urb, -+ int status) { -+ struct crisv10_urb_priv *urb_priv = urb->hcpriv; -+ struct urb_later_data* uld; -+ -+ ASSERT(urb_priv); -+ -+ if(urb_priv->later_data != NULL) { -+ /* Later-finish allready scheduled for this URB, just update status to -+ return when finishing later */ -+ errno_dbg("Later-finish schedule change URB status:%d with new" -+ " status:%d\n", urb_priv->later_data->status, status); -+ -+ urb_priv->later_data->status = status; -+ return; -+ } -+ -+ uld = kmem_cache_alloc(later_data_cache, GFP_ATOMIC); -+ ASSERT(uld); -+ -+ uld->hcd = hcd; -+ uld->urb = urb; -+ uld->urb_num = urb_priv->urb_num; -+ uld->status = status; -+ -+ //INIT_WORK(&uld->ws, tc_finish_urb_later_proc, uld); -+ INIT_DELAYED_WORK(&uld->ws, tc_finish_urb_later_proc); -+ urb_priv->later_data = uld; -+ -+ /* Schedule the finishing of the URB to happen later */ -+ schedule_delayed_work(&uld->ws, LATER_TIMER_DELAY); -+} -+ -+ /* hinko ignore usb_pipeisoc */ -+#if 0 -+static void tc_finish_isoc_urb(struct usb_hcd *hcd, struct urb *urb, -+ int status); -+#endif -+ -+static void tc_finish_urb(struct usb_hcd *hcd, struct urb *urb, int status) { -+ struct crisv10_hcd* crisv10_hcd = hcd_to_crisv10_hcd(hcd); -+ struct crisv10_urb_priv *urb_priv = urb->hcpriv; -+ int epid; -+ char toggle; -+ int urb_num; -+ unsigned long flags; -+ -+ DBFENTER; -+ ASSERT(urb_priv != NULL); -+ epid = urb_priv->epid; -+ urb_num = urb_priv->urb_num; -+ -+ if(urb != activeUrbList[epid]) { -+ if(urb_list_entry(urb, epid)) { -+ /* Remove this URB from the list. Only happens when URB are finished -+ before having been processed (dequeing) */ -+ urb_list_del(urb, epid); -+ } else { -+ tc_warn("Finishing of URB:0x%x[%d] neither active or in queue for" -+ " epid:%d\n", (unsigned int)urb, urb_num, epid); -+ } -+ } -+ -+ /* Cancel any pending later-finish of this URB */ -+ if(urb_priv->later_data) { -+ urb_priv->later_data->urb = NULL; -+ } -+ -+ /* For an IN pipe, we always set the actual length, regardless of whether -+ there was an error or not (which means the device driver can use the data -+ if it wants to). */ -+ if(usb_pipein(urb->pipe)) { -+ urb->actual_length = urb_priv->rx_offset; -+ } else { -+ /* Set actual_length for OUT urbs also; the USB mass storage driver seems -+ to want that. */ -+ if (status == 0 && urb->status == -EINPROGRESS) { -+ urb->actual_length = urb->transfer_buffer_length; -+ } else { -+ /* We wouldn't know of any partial writes if there was an error. */ -+ urb->actual_length = 0; -+ } -+ } -+ -+ -+ /* URB status mangling */ -+ if(urb->status == -EINPROGRESS) { -+ /* The USB core hasn't changed the status, let's set our finish status */ -+ urb->status = status; -+ -+ if ((status == 0) && (urb->transfer_flags & URB_SHORT_NOT_OK) && -+ usb_pipein(urb->pipe) && -+ (urb->actual_length != urb->transfer_buffer_length)) { -+ /* URB_SHORT_NOT_OK means that short reads (shorter than the endpoint's -+ max length) is to be treated as an error. */ -+ errno_dbg("Finishing URB:0x%x[%d] with SHORT_NOT_OK flag and short" -+ " data:%d\n", (unsigned int)urb, urb_num, -+ urb->actual_length); -+ urb->status = -EREMOTEIO; -+ } -+ -+ if(urb_priv->urb_state == UNLINK) { -+ /* URB has been requested to be unlinked asynchronously */ -+ urb->status = -ECONNRESET; -+ errno_dbg("Fixing unlink status of URB:0x%x[%d] to:%d\n", -+ (unsigned int)urb, urb_num, urb->status); -+ } -+ } else { -+ /* The USB Core wants to signal some error via the URB, pass it through */ -+ } -+ -+ /* hinko ignore usb_pipeisoc */ -+#if 0 -+ /* use completely different finish function for Isoc URBs */ -+ if(usb_pipeisoc(urb->pipe)) { -+ tc_finish_isoc_urb(hcd, urb, status); -+ return; -+ } -+#endif -+ -+ /* Do special unlinking of EPs for Intr traffic */ -+ if(usb_pipeint(urb->pipe)) { -+ tc_dma_unlink_intr_urb(urb); -+ } -+ -+ /* hinko ignore usb_pipeisoc */ -+#if 0 -+ /* Release allocated bandwidth for periodic transfers */ -+ if(usb_pipeint(urb->pipe) || usb_pipeisoc(urb->pipe)) -+ usb_release_bandwidth(urb->dev, urb, 0); -+#endif -+ -+ /* This URB is active on EP */ -+ if(urb == activeUrbList[epid]) { -+ /* We need to fiddle with the toggle bits because the hardware doesn't do -+ it for us. */ -+ toggle = etrax_epid_get_toggle(epid, usb_pipeout(urb->pipe)); -+ usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), -+ usb_pipeout(urb->pipe), toggle); -+ -+ /* Checks for Ctrl and Bulk EPs */ -+ switch(usb_pipetype(urb->pipe)) { -+ case PIPE_BULK: -+ /* Check so Bulk EP realy is disabled before finishing active URB */ -+ ASSERT((TxBulkEPList[epid].command & IO_MASK(USB_EP_command, enable)) == -+ IO_STATE(USB_EP_command, enable, no)); -+ /* Disable sub-pointer for EP to avoid next tx_interrupt() to -+ process Bulk EP. */ -+ TxBulkEPList[epid].sub = 0; -+ /* No need to wait for the DMA before changing the next pointer. -+ The modulo NBR_OF_EPIDS isn't actually necessary, since we will never use -+ the last one (INVALID_EPID) for actual traffic. */ -+ TxBulkEPList[epid].next = -+ virt_to_phys(&TxBulkEPList[(epid + 1) % NBR_OF_EPIDS]); -+ break; -+ case PIPE_CONTROL: -+ /* Check so Ctrl EP realy is disabled before finishing active URB */ -+ ASSERT((TxCtrlEPList[epid].command & IO_MASK(USB_EP_command, enable)) == -+ IO_STATE(USB_EP_command, enable, no)); -+ /* Disable sub-pointer for EP to avoid next tx_interrupt() to -+ process Ctrl EP. */ -+ TxCtrlEPList[epid].sub = 0; -+ break; -+ } -+ } -+ -+ /* Free HC-private URB data*/ -+ urb_priv_free(hcd, urb); -+ -+ if(urb->status) { -+ errno_dbg("finish_urb (URB:0x%x[%d] %s %s) (data:%d) status:%d\n", -+ (unsigned int)urb, urb_num, str_dir(urb->pipe), -+ str_type(urb->pipe), urb->actual_length, urb->status); -+ } else { -+ tc_dbg("finish_urb (URB:0x%x[%d] %s %s) (data:%d) status:%d\n", -+ (unsigned int)urb, urb_num, str_dir(urb->pipe), -+ str_type(urb->pipe), urb->actual_length, urb->status); -+ } -+ -+ /* If we just finished an active URB, clear active pointer. */ -+ if (urb == activeUrbList[epid]) { -+ /* Make URB not active on EP anymore */ -+ activeUrbList[epid] = NULL; -+ -+ if(urb->status == 0) { -+ /* URB finished sucessfully, process queue to see if there are any more -+ URBs waiting before we call completion function.*/ -+ if(crisv10_hcd->running) { -+ /* Only process queue if USB controller is running */ -+ tc_dma_process_queue(epid); -+ } else { -+ tc_warn("No processing of queue for epid:%d, USB Controller not" -+ " running\n", epid); -+ } -+ } -+ } -+ -+ /* Hand the URB from HCD to its USB device driver, using its completion -+ functions */ -+// usb_hcd_giveback_urb (hcd, urb); -+ /** -+ * usb_hcd_unlink_urb_from_ep - remove an URB from its endpoint queue -+ * @hcd: host controller to which @urb was submitted -+ * @urb: URB being unlinked -+ * -+ * Host controller drivers should call this routine before calling -+ * usb_hcd_giveback_urb(). The HCD's private spinlock must be held and -+ * interrupts must be disabled. The actions carried out here are required -+ * for URB completion. -+ */ -+ -+ /*hinko link/unlink urb -> ep */ -+ //spin_lock(&crisv10_hcd->lock); -+ spin_lock_irqsave(&crisv10_hcd->lock, flags); -+ usb_hcd_unlink_urb_from_ep(hcd, urb); -+ usb_hcd_giveback_urb(hcd, urb, status); -+ //spin_unlock(&crisv10_hcd->lock); -+ spin_unlock_irqrestore(&crisv10_hcd->lock, flags); -+ -+ /* Check the queue once more if the URB returned with error, because we -+ didn't do it before the completion function because the specification -+ states that the queue should not restart until all it's unlinked -+ URBs have been fully retired, with the completion functions run */ -+ if(crisv10_hcd->running) { -+ /* Only process queue if USB controller is running */ -+ tc_dma_process_queue(epid); -+ } else { -+ tc_warn("No processing of queue for epid:%d, USB Controller not running\n", -+ epid); -+ } -+ -+ DBFEXIT; -+} -+ -+ /* hinko ignore usb_pipeisoc */ -+#if 0 -+static void tc_finish_isoc_urb(struct usb_hcd *hcd, struct urb *urb, -+ int status) { -+ struct crisv10_urb_priv *urb_priv = urb->hcpriv; -+ int epid, i; -+ volatile int timeout = 10000; -+ -+ ASSERT(urb_priv); -+ epid = urb_priv->epid; -+ -+ ASSERT(usb_pipeisoc(urb->pipe)); -+ -+ /* Set that all isoc packets have status and length set before -+ completing the urb. */ -+ for (i = urb_priv->isoc_packet_counter; i < urb->number_of_packets; i++){ -+ urb->iso_frame_desc[i].actual_length = 0; -+ urb->iso_frame_desc[i].status = -EPROTO; -+ } -+ -+ /* Check if the URB is currently active (done or error) */ -+ if(urb == activeUrbList[epid]) { -+ /* Check if there are another In Isoc URB queued for this epid */ -+ if (!list_empty(&urb_list[epid])&& !epid_state[epid].disabled) { -+ /* Move it from queue to active and mark it started so Isoc transfers -+ won't be interrupted. -+ All Isoc URBs data transfers are already added to DMA lists so we -+ don't have to insert anything in DMA lists here. */ -+ activeUrbList[epid] = urb_list_first(epid); -+ ((struct crisv10_urb_priv *)(activeUrbList[epid]->hcpriv))->urb_state = -+ STARTED; -+ urb_list_del(activeUrbList[epid], epid); -+ -+ if(urb->status) { -+ errno_dbg("finish_isoc_urb (URB:0x%x[%d] %s %s) (%d of %d packets)" -+ " status:%d, new waiting URB:0x%x[%d]\n", -+ (unsigned int)urb, urb_priv->urb_num, str_dir(urb->pipe), -+ str_type(urb->pipe), urb_priv->isoc_packet_counter, -+ urb->number_of_packets, urb->status, -+ (unsigned int)activeUrbList[epid], -+ ((struct crisv10_urb_priv *)(activeUrbList[epid]->hcpriv))->urb_num); -+ } -+ -+ } else { /* No other URB queued for this epid */ -+ if(urb->status) { -+ errno_dbg("finish_isoc_urb (URB:0x%x[%d] %s %s) (%d of %d packets)" -+ " status:%d, no new URB waiting\n", -+ (unsigned int)urb, urb_priv->urb_num, str_dir(urb->pipe), -+ str_type(urb->pipe), urb_priv->isoc_packet_counter, -+ urb->number_of_packets, urb->status); -+ } -+ -+ /* Check if EP is still enabled, then shut it down. */ -+ if (TxIsocEPList[epid].command & IO_MASK(USB_EP_command, enable)) { -+ isoc_dbg("Isoc EP enabled for epid:%d, disabling it\n", epid); -+ -+ /* Should only occur for In Isoc EPs where SB isn't consumed. */ -+ ASSERT(usb_pipein(urb->pipe)); -+ -+ /* Disable it and wait for it to stop */ -+ TxIsocEPList[epid].command &= ~IO_MASK(USB_EP_command, enable); -+ -+ /* Ah, the luxury of busy-wait. */ -+ while((*R_DMA_CH8_SUB3_EP == virt_to_phys(&TxIsocEPList[epid])) && -+ (timeout-- > 0)); -+ if(timeout == 0) { -+ warn("Timeout while waiting for DMA-TX-Isoc to leave EP for epid:%d\n", epid); -+ } -+ } -+ -+ /* Unlink SB to say that epid is finished. */ -+ TxIsocEPList[epid].sub = 0; -+ TxIsocEPList[epid].hw_len = 0; -+ -+ /* No URB active for EP anymore */ -+ activeUrbList[epid] = NULL; -+ } -+ } else { /* Finishing of not active URB (queued up with SBs thought) */ -+ isoc_warn("finish_isoc_urb (URB:0x%x %s) (%d of %d packets) status:%d," -+ " SB queued but not active\n", -+ (unsigned int)urb, str_dir(urb->pipe), -+ urb_priv->isoc_packet_counter, urb->number_of_packets, -+ urb->status); -+ if(usb_pipeout(urb->pipe)) { -+ /* Finishing of not yet active Out Isoc URB needs unlinking of SBs. */ -+ struct USB_SB_Desc *iter_sb, *prev_sb, *next_sb; -+ -+ iter_sb = TxIsocEPList[epid].sub ? -+ phys_to_virt(TxIsocEPList[epid].sub) : 0; -+ prev_sb = 0; -+ -+ /* SB that is linked before this URBs first SB */ -+ while (iter_sb && (iter_sb != urb_priv->first_sb)) { -+ prev_sb = iter_sb; -+ iter_sb = iter_sb->next ? phys_to_virt(iter_sb->next) : 0; -+ } -+ -+ if (iter_sb == 0) { -+ /* Unlink of the URB currently being transmitted. */ -+ prev_sb = 0; -+ iter_sb = TxIsocEPList[epid].sub ? phys_to_virt(TxIsocEPList[epid].sub) : 0; -+ } -+ -+ while (iter_sb && (iter_sb != urb_priv->last_sb)) { -+ iter_sb = iter_sb->next ? phys_to_virt(iter_sb->next) : 0; -+ } -+ -+ if (iter_sb) { -+ next_sb = iter_sb->next ? phys_to_virt(iter_sb->next) : 0; -+ } else { -+ /* This should only happen if the DMA has completed -+ processing the SB list for this EP while interrupts -+ are disabled. */ -+ isoc_dbg("Isoc urb not found, already sent?\n"); -+ next_sb = 0; -+ } -+ if (prev_sb) { -+ prev_sb->next = next_sb ? virt_to_phys(next_sb) : 0; -+ } else { -+ TxIsocEPList[epid].sub = next_sb ? virt_to_phys(next_sb) : 0; -+ } -+ } -+ } -+ -+ /* Free HC-private URB data*/ -+ urb_priv_free(hcd, urb); -+ -+ usb_release_bandwidth(urb->dev, urb, 0); -+ -+ /* Hand the URB from HCD to its USB device driver, using its completion -+ functions */ -+ usb_hcd_giveback_urb (hcd, urb); -+} -+#endif -+ -+static __u32 urb_num = 0; -+ -+/* allocate and initialize URB private data */ -+static int urb_priv_create(struct usb_hcd *hcd, struct urb *urb, int epid, -+ int mem_flags) { -+ struct crisv10_urb_priv *urb_priv; -+ -+ urb_priv = kmalloc(sizeof *urb_priv, mem_flags); -+ if (!urb_priv) -+ return -ENOMEM; -+ memset(urb_priv, 0, sizeof *urb_priv); -+ -+ urb_priv->epid = epid; -+ urb_priv->urb_state = NOT_STARTED; -+ -+ urb->hcpriv = urb_priv; -+ /* Assign URB a sequence number, and increment counter */ -+ urb_priv->urb_num = urb_num; -+ urb_num++; -+ return 0; -+} -+ -+/* free URB private data */ -+static void urb_priv_free(struct usb_hcd *hcd, struct urb *urb) { -+ int i; -+ struct crisv10_urb_priv *urb_priv = urb->hcpriv; -+ ASSERT(urb_priv != 0); -+ -+ /* Check it has any SBs linked that needs to be freed*/ -+ if(urb_priv->first_sb != NULL) { -+ struct USB_SB_Desc *next_sb, *first_sb, *last_sb; -+ int i = 0; -+ first_sb = urb_priv->first_sb; -+ last_sb = urb_priv->last_sb; -+ ASSERT(last_sb); -+ while(first_sb != last_sb) { -+ next_sb = (struct USB_SB_Desc *)phys_to_virt(first_sb->next); -+ kmem_cache_free(usb_desc_cache, first_sb); -+ first_sb = next_sb; -+ i++; -+ } -+ kmem_cache_free(usb_desc_cache, last_sb); -+ i++; -+ } -+ -+ /* Check if it has any EPs in its Intr pool that also needs to be freed */ -+ if(urb_priv->intr_ep_pool_length > 0) { -+ for(i = 0; i < urb_priv->intr_ep_pool_length; i++) { -+ kfree(urb_priv->intr_ep_pool[i]); -+ } -+ /* -+ tc_dbg("Freed %d EPs from URB:0x%x EP pool\n", -+ urb_priv->intr_ep_pool_length, (unsigned int)urb); -+ */ -+ } -+ -+ kfree(urb_priv); -+ urb->hcpriv = NULL; -+} -+ -+static int ep_priv_create(struct usb_host_endpoint *ep, int mem_flags) { -+ struct crisv10_ep_priv *ep_priv; -+ -+ ep_priv = kmalloc(sizeof *ep_priv, mem_flags); -+ if (!ep_priv) -+ return -ENOMEM; -+ memset(ep_priv, 0, sizeof *ep_priv); -+ -+ ep->hcpriv = ep_priv; -+ return 0; -+} -+ -+static void ep_priv_free(struct usb_host_endpoint *ep) { -+ struct crisv10_ep_priv *ep_priv = ep->hcpriv; -+ ASSERT(ep_priv); -+ kfree(ep_priv); -+ ep->hcpriv = NULL; -+} -+ -+/* EPID handling functions, managing EP-list in Etrax through wrappers */ -+/* ------------------------------------------------------------------- */ -+ -+/* Sets up a new EPID for an endpoint or returns existing if found */ -+//static int tc_setup_epid(struct usb_host_endpoint *ep, struct urb *urb, -+// int mem_flags) { -+static int tc_setup_epid(struct urb *urb, int mem_flags) -+{ -+ int epid; -+ char devnum, endpoint, out_traffic, slow; -+ int maxlen; -+ __u32 epid_data; -+ struct usb_host_endpoint *ep = urb->ep; -+ struct crisv10_ep_priv *ep_priv = ep->hcpriv; -+ -+ DBFENTER; -+ -+ /* Check if a valid epid already is setup for this endpoint */ -+ if(ep_priv != NULL) { -+ return ep_priv->epid; -+ } -+ -+ /* We must find and initiate a new epid for this urb. */ -+ epid = tc_allocate_epid(); -+ -+ if (epid == -1) { -+ /* Failed to allocate a new epid. */ -+ DBFEXIT; -+ return epid; -+ } -+ -+ /* We now have a new epid to use. Claim it. */ -+ epid_state[epid].inuse = 1; -+ -+ /* Init private data for new endpoint */ -+ if(ep_priv_create(ep, mem_flags) != 0) { -+ return -ENOMEM; -+ } -+ ep_priv = ep->hcpriv; -+ ep_priv->epid = epid; -+ -+ devnum = usb_pipedevice(urb->pipe); -+ endpoint = usb_pipeendpoint(urb->pipe); -+ slow = (urb->dev->speed == USB_SPEED_LOW); -+ maxlen = usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)); -+ -+ if (usb_pipetype(urb->pipe) == PIPE_CONTROL) { -+ /* We want both IN and OUT control traffic to be put on the same -+ EP/SB list. */ -+ out_traffic = 1; -+ } else { -+ out_traffic = usb_pipeout(urb->pipe); -+ } -+ -+ if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { -+ epid_data = IO_STATE(R_USB_EPT_DATA_ISO, valid, yes) | -+ /* FIXME: Change any to the actual port? */ -+ IO_STATE(R_USB_EPT_DATA_ISO, port, any) | -+ IO_FIELD(R_USB_EPT_DATA_ISO, max_len, maxlen) | -+ IO_FIELD(R_USB_EPT_DATA_ISO, ep, endpoint) | -+ IO_FIELD(R_USB_EPT_DATA_ISO, dev, devnum); -+ etrax_epid_iso_set(epid, epid_data); -+ } else { -+ epid_data = IO_STATE(R_USB_EPT_DATA, valid, yes) | -+ IO_FIELD(R_USB_EPT_DATA, low_speed, slow) | -+ /* FIXME: Change any to the actual port? */ -+ IO_STATE(R_USB_EPT_DATA, port, any) | -+ IO_FIELD(R_USB_EPT_DATA, max_len, maxlen) | -+ IO_FIELD(R_USB_EPT_DATA, ep, endpoint) | -+ IO_FIELD(R_USB_EPT_DATA, dev, devnum); -+ etrax_epid_set(epid, epid_data); -+ } -+ -+ epid_state[epid].out_traffic = out_traffic; -+ epid_state[epid].type = usb_pipetype(urb->pipe); -+ -+ tc_warn("Setting up ep:0x%x epid:%d (addr:%d endp:%d max_len:%d %s %s %s)\n", -+ (unsigned int)ep, epid, devnum, endpoint, maxlen, -+ str_type(urb->pipe), out_traffic ? "out" : "in", -+ slow ? "low" : "full"); -+ -+ /* Enable Isoc eof interrupt if we set up the first Isoc epid */ -+ if(usb_pipeisoc(urb->pipe)) { -+ isoc_epid_counter++; -+ if(isoc_epid_counter == 1) { -+ isoc_warn("Enabled Isoc eof interrupt\n"); -+ *R_USB_IRQ_MASK_SET |= IO_STATE(R_USB_IRQ_MASK_SET, iso_eof, set); -+ } -+ } -+ -+ DBFEXIT; -+ return epid; -+} -+ -+static void tc_free_epid(struct usb_host_endpoint *ep) { -+ unsigned long flags; -+ struct crisv10_ep_priv *ep_priv = ep->hcpriv; -+ int epid; -+ volatile int timeout = 10000; -+ -+ DBFENTER; -+ -+ if (ep_priv == NULL) { -+ tc_warn("Trying to free unused epid on ep:0x%x\n", (unsigned int)ep); -+ DBFEXIT; -+ return; -+ } -+ -+ epid = ep_priv->epid; -+ -+ /* Disable Isoc eof interrupt if we free the last Isoc epid */ -+ if(epid_isoc(epid)) { -+ ASSERT(isoc_epid_counter > 0); -+ isoc_epid_counter--; -+ if(isoc_epid_counter == 0) { -+ *R_USB_IRQ_MASK_SET &= ~IO_STATE(R_USB_IRQ_MASK_SET, iso_eof, set); -+ isoc_warn("Disabled Isoc eof interrupt\n"); -+ } -+ } -+ -+ /* Take lock manualy instead of in epid_x_x wrappers, -+ because we need to be polling here */ -+ spin_lock_irqsave(&etrax_epid_lock, flags); -+ -+ *R_USB_EPT_INDEX = IO_FIELD(R_USB_EPT_INDEX, value, epid); -+ nop(); -+ while((*R_USB_EPT_DATA & IO_MASK(R_USB_EPT_DATA, hold)) && -+ (timeout-- > 0)); -+ if(timeout == 0) { -+ warn("Timeout while waiting for epid:%d to drop hold\n", epid); -+ } -+ /* This will, among other things, set the valid field to 0. */ -+ *R_USB_EPT_DATA = 0; -+ spin_unlock_irqrestore(&etrax_epid_lock, flags); -+ -+ /* Free resource in software state info list */ -+ epid_state[epid].inuse = 0; -+ -+ /* Free private endpoint data */ -+ ep_priv_free(ep); -+ -+ DBFEXIT; -+} -+ -+static int tc_allocate_epid(void) { -+ int i; -+ DBFENTER; -+ for (i = 0; i < NBR_OF_EPIDS; i++) { -+ if (!epid_inuse(i)) { -+ DBFEXIT; -+ return i; -+ } -+ } -+ -+ tc_warn("Found no free epids\n"); -+ DBFEXIT; -+ return -1; -+} -+ -+ -+/* Wrappers around the list functions (include/linux/list.h). */ -+/* ---------------------------------------------------------- */ -+static inline int __urb_list_empty(int epid) { -+ int retval; -+ retval = list_empty(&urb_list[epid]); -+ return retval; -+} -+ -+/* Returns first urb for this epid, or NULL if list is empty. */ -+static inline struct urb *urb_list_first(int epid) { -+ unsigned long flags; -+ struct urb *first_urb = 0; -+ spin_lock_irqsave(&urb_list_lock, flags); -+ if (!__urb_list_empty(epid)) { -+ /* Get the first urb (i.e. head->next). */ -+ urb_entry_t *urb_entry = list_entry((&urb_list[epid])->next, urb_entry_t, list); -+ first_urb = urb_entry->urb; -+ } -+ spin_unlock_irqrestore(&urb_list_lock, flags); -+ return first_urb; -+} -+ -+/* Adds an urb_entry last in the list for this epid. */ -+static inline void urb_list_add(struct urb *urb, int epid, int mem_flags) { -+ unsigned long flags; -+ urb_entry_t *urb_entry = (urb_entry_t *)kmalloc(sizeof(urb_entry_t), mem_flags); -+ ASSERT(urb_entry); -+ -+ urb_entry->urb = urb; -+ spin_lock_irqsave(&urb_list_lock, flags); -+ list_add_tail(&urb_entry->list, &urb_list[epid]); -+ spin_unlock_irqrestore(&urb_list_lock, flags); -+} -+ -+/* Search through the list for an element that contains this urb. (The list -+ is expected to be short and the one we are about to delete will often be -+ the first in the list.) -+ Should be protected by spin_locks in calling function */ -+static inline urb_entry_t *__urb_list_entry(struct urb *urb, int epid) { -+ struct list_head *entry; -+ struct list_head *tmp; -+ urb_entry_t *urb_entry; -+ -+ list_for_each_safe(entry, tmp, &urb_list[epid]) { -+ urb_entry = list_entry(entry, urb_entry_t, list); -+ ASSERT(urb_entry); -+ ASSERT(urb_entry->urb); -+ -+ if (urb_entry->urb == urb) { -+ return urb_entry; -+ } -+ } -+ return 0; -+} -+ -+/* Same function as above but for global use. Protects list by spinlock */ -+static inline urb_entry_t *urb_list_entry(struct urb *urb, int epid) { -+ unsigned long flags; -+ urb_entry_t *urb_entry; -+ spin_lock_irqsave(&urb_list_lock, flags); -+ urb_entry = __urb_list_entry(urb, epid); -+ spin_unlock_irqrestore(&urb_list_lock, flags); -+ return (urb_entry); -+} -+ -+/* Delete an urb from the list. */ -+static inline void urb_list_del(struct urb *urb, int epid) { -+ unsigned long flags; -+ urb_entry_t *urb_entry; -+ -+ /* Delete entry and free. */ -+ spin_lock_irqsave(&urb_list_lock, flags); -+ urb_entry = __urb_list_entry(urb, epid); -+ ASSERT(urb_entry); -+ -+ list_del(&urb_entry->list); -+ spin_unlock_irqrestore(&urb_list_lock, flags); -+ kfree(urb_entry); -+} -+ -+/* Move an urb to the end of the list. */ -+static inline void urb_list_move_last(struct urb *urb, int epid) { -+ unsigned long flags; -+ urb_entry_t *urb_entry; -+ -+ spin_lock_irqsave(&urb_list_lock, flags); -+ urb_entry = __urb_list_entry(urb, epid); -+ ASSERT(urb_entry); -+ -+ list_del(&urb_entry->list); -+ list_add_tail(&urb_entry->list, &urb_list[epid]); -+ spin_unlock_irqrestore(&urb_list_lock, flags); -+} -+ -+/* Get the next urb in the list. */ -+static inline struct urb *urb_list_next(struct urb *urb, int epid) { -+ unsigned long flags; -+ urb_entry_t *urb_entry; -+ -+ spin_lock_irqsave(&urb_list_lock, flags); -+ urb_entry = __urb_list_entry(urb, epid); -+ ASSERT(urb_entry); -+ -+ if (urb_entry->list.next != &urb_list[epid]) { -+ struct list_head *elem = urb_entry->list.next; -+ urb_entry = list_entry(elem, urb_entry_t, list); -+ spin_unlock_irqrestore(&urb_list_lock, flags); -+ return urb_entry->urb; -+ } else { -+ spin_unlock_irqrestore(&urb_list_lock, flags); -+ return NULL; -+ } -+} -+ -+struct USB_EP_Desc* create_ep(int epid, struct USB_SB_Desc* sb_desc, -+ int mem_flags) { -+ struct USB_EP_Desc *ep_desc; -+ ep_desc = (struct USB_EP_Desc *) kmem_cache_alloc(usb_desc_cache, mem_flags); -+ if(ep_desc == NULL) -+ return NULL; -+ memset(ep_desc, 0, sizeof(struct USB_EP_Desc)); -+ -+ ep_desc->hw_len = 0; -+ ep_desc->command = (IO_FIELD(USB_EP_command, epid, epid) | -+ IO_STATE(USB_EP_command, enable, yes)); -+ if(sb_desc == NULL) { -+ ep_desc->sub = 0; -+ } else { -+ ep_desc->sub = virt_to_phys(sb_desc); -+ } -+ return ep_desc; -+} -+ -+#define TT_ZOUT 0 -+#define TT_IN 1 -+#define TT_OUT 2 -+#define TT_SETUP 3 -+ -+#define CMD_EOL IO_STATE(USB_SB_command, eol, yes) -+#define CMD_INTR IO_STATE(USB_SB_command, intr, yes) -+#define CMD_FULL IO_STATE(USB_SB_command, full, yes) -+ -+/* Allocation and setup of a generic SB. Used to create SETUP, OUT and ZOUT -+ SBs. Also used by create_sb_in() to avoid same allocation procedure at two -+ places */ -+struct USB_SB_Desc* create_sb(struct USB_SB_Desc* sb_prev, int tt, void* data, -+ int datalen, int mem_flags) { -+ struct USB_SB_Desc *sb_desc; -+ sb_desc = (struct USB_SB_Desc*)kmem_cache_alloc(usb_desc_cache, mem_flags); -+ if(sb_desc == NULL) -+ return NULL; -+ memset(sb_desc, 0, sizeof(struct USB_SB_Desc)); -+ -+ sb_desc->command = IO_FIELD(USB_SB_command, tt, tt) | -+ IO_STATE(USB_SB_command, eot, yes); -+ -+ sb_desc->sw_len = datalen; -+ if(data != NULL) { -+ sb_desc->buf = virt_to_phys(data); -+ } else { -+ sb_desc->buf = 0; -+ } -+ if(sb_prev != NULL) { -+ sb_prev->next = virt_to_phys(sb_desc); -+ } -+ return sb_desc; -+} -+ -+/* Creates a copy of an existing SB by allocation space for it and copy -+ settings */ -+struct USB_SB_Desc* create_sb_copy(struct USB_SB_Desc* sb_orig, int mem_flags) { -+ struct USB_SB_Desc *sb_desc; -+ sb_desc = (struct USB_SB_Desc*)kmem_cache_alloc(usb_desc_cache, mem_flags); -+ if(sb_desc == NULL) -+ return NULL; -+ -+ memcpy(sb_desc, sb_orig, sizeof(struct USB_SB_Desc)); -+ return sb_desc; -+} -+ -+/* A specific create_sb function for creation of in SBs. This is due to -+ that datalen in In SBs shows how many packets we are expecting. It also -+ sets up the rem field to show if how many bytes we expect in last packet -+ if it's not a full one */ -+struct USB_SB_Desc* create_sb_in(struct USB_SB_Desc* sb_prev, int datalen, -+ int maxlen, int mem_flags) { -+ struct USB_SB_Desc *sb_desc; -+ sb_desc = create_sb(sb_prev, TT_IN, NULL, -+ datalen ? (datalen - 1) / maxlen + 1 : 0, mem_flags); -+ if(sb_desc == NULL) -+ return NULL; -+ sb_desc->command |= IO_FIELD(USB_SB_command, rem, datalen % maxlen); -+ return sb_desc; -+} -+ -+void set_sb_cmds(struct USB_SB_Desc *sb_desc, __u16 flags) { -+ sb_desc->command |= flags; -+} -+ -+int create_sb_for_urb(struct urb *urb, int mem_flags) { -+ int is_out = !usb_pipein(urb->pipe); -+ int type = usb_pipetype(urb->pipe); -+ int maxlen = usb_maxpacket(urb->dev, urb->pipe, is_out); -+ int buf_len = urb->transfer_buffer_length; -+ void *buf = buf_len > 0 ? urb->transfer_buffer : NULL; -+ struct USB_SB_Desc *sb_desc = NULL; -+ -+ struct crisv10_urb_priv *urb_priv = (struct crisv10_urb_priv *)urb->hcpriv; -+ ASSERT(urb_priv != NULL); -+ -+ switch(type) { -+ case PIPE_CONTROL: -+ /* Setup stage */ -+ sb_desc = create_sb(NULL, TT_SETUP, urb->setup_packet, 8, mem_flags); -+ if(sb_desc == NULL) -+ return -ENOMEM; -+ set_sb_cmds(sb_desc, CMD_FULL); -+ -+ /* Attach first SB to URB */ -+ urb_priv->first_sb = sb_desc; -+ -+ if (is_out) { /* Out Control URB */ -+ /* If this Control OUT transfer has an optional data stage we add -+ an OUT token before the mandatory IN (status) token */ -+ if ((buf_len > 0) && buf) { -+ sb_desc = create_sb(sb_desc, TT_OUT, buf, buf_len, mem_flags); -+ if(sb_desc == NULL) -+ return -ENOMEM; -+ set_sb_cmds(sb_desc, CMD_FULL); -+ } -+ -+ /* Status stage */ -+ /* The data length has to be exactly 1. This is due to a requirement -+ of the USB specification that a host must be prepared to receive -+ data in the status phase */ -+ sb_desc = create_sb(sb_desc, TT_IN, NULL, 1, mem_flags); -+ if(sb_desc == NULL) -+ return -ENOMEM; -+ } else { /* In control URB */ -+ /* Data stage */ -+ sb_desc = create_sb_in(sb_desc, buf_len, maxlen, mem_flags); -+ if(sb_desc == NULL) -+ return -ENOMEM; -+ -+ /* Status stage */ -+ /* Read comment at zout_buffer declaration for an explanation to this. */ -+ sb_desc = create_sb(sb_desc, TT_ZOUT, &zout_buffer[0], 1, mem_flags); -+ if(sb_desc == NULL) -+ return -ENOMEM; -+ /* Set descriptor interrupt flag for in URBs so we can finish URB after -+ zout-packet has been sent */ -+ set_sb_cmds(sb_desc, CMD_INTR | CMD_FULL); -+ } -+ /* Set end-of-list flag in last SB */ -+ set_sb_cmds(sb_desc, CMD_EOL); -+ /* Attach last SB to URB */ -+ urb_priv->last_sb = sb_desc; -+ break; -+ -+ case PIPE_BULK: -+ if (is_out) { /* Out Bulk URB */ -+ sb_desc = create_sb(NULL, TT_OUT, buf, buf_len, mem_flags); -+ if(sb_desc == NULL) -+ return -ENOMEM; -+ /* The full field is set to yes, even if we don't actually check that -+ this is a full-length transfer (i.e., that transfer_buffer_length % -+ maxlen = 0). -+ Setting full prevents the USB controller from sending an empty packet -+ in that case. However, if URB_ZERO_PACKET was set we want that. */ -+ if (!(urb->transfer_flags & URB_ZERO_PACKET)) { -+ set_sb_cmds(sb_desc, CMD_FULL); -+ } -+ } else { /* In Bulk URB */ -+ sb_desc = create_sb_in(NULL, buf_len, maxlen, mem_flags); -+ if(sb_desc == NULL) -+ return -ENOMEM; -+ } -+ /* Set end-of-list flag for last SB */ -+ set_sb_cmds(sb_desc, CMD_EOL); -+ -+ /* Attach SB to URB */ -+ urb_priv->first_sb = sb_desc; -+ urb_priv->last_sb = sb_desc; -+ break; -+ -+ case PIPE_INTERRUPT: -+ if(is_out) { /* Out Intr URB */ -+ sb_desc = create_sb(NULL, TT_OUT, buf, buf_len, mem_flags); -+ if(sb_desc == NULL) -+ return -ENOMEM; -+ -+ /* The full field is set to yes, even if we don't actually check that -+ this is a full-length transfer (i.e., that transfer_buffer_length % -+ maxlen = 0). -+ Setting full prevents the USB controller from sending an empty packet -+ in that case. However, if URB_ZERO_PACKET was set we want that. */ -+ if (!(urb->transfer_flags & URB_ZERO_PACKET)) { -+ set_sb_cmds(sb_desc, CMD_FULL); -+ } -+ /* Only generate TX interrupt if it's a Out URB*/ -+ set_sb_cmds(sb_desc, CMD_INTR); -+ -+ } else { /* In Intr URB */ -+ sb_desc = create_sb_in(NULL, buf_len, maxlen, mem_flags); -+ if(sb_desc == NULL) -+ return -ENOMEM; -+ } -+ /* Set end-of-list flag for last SB */ -+ set_sb_cmds(sb_desc, CMD_EOL); -+ -+ /* Attach SB to URB */ -+ urb_priv->first_sb = sb_desc; -+ urb_priv->last_sb = sb_desc; -+ -+ break; -+ case PIPE_ISOCHRONOUS: -+ if(is_out) { /* Out Isoc URB */ -+ int i; -+ if(urb->number_of_packets == 0) { -+ tc_err("Can't create SBs for Isoc URB with zero packets\n"); -+ return -EPIPE; -+ } -+ /* Create one SB descriptor for each packet and link them together. */ -+ for(i = 0; i < urb->number_of_packets; i++) { -+ if (urb->iso_frame_desc[i].length > 0) { -+ -+ sb_desc = create_sb(sb_desc, TT_OUT, urb->transfer_buffer + -+ urb->iso_frame_desc[i].offset, -+ urb->iso_frame_desc[i].length, mem_flags); -+ if(sb_desc == NULL) -+ return -ENOMEM; -+ -+ /* Check if it's a full length packet */ -+ if (urb->iso_frame_desc[i].length == -+ usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe))) { -+ set_sb_cmds(sb_desc, CMD_FULL); -+ } -+ -+ } else { /* zero length packet */ -+ sb_desc = create_sb(sb_desc, TT_ZOUT, &zout_buffer[0], 1, mem_flags); -+ if(sb_desc == NULL) -+ return -ENOMEM; -+ set_sb_cmds(sb_desc, CMD_FULL); -+ } -+ /* Attach first SB descriptor to URB */ -+ if (i == 0) { -+ urb_priv->first_sb = sb_desc; -+ } -+ } -+ /* Set interrupt and end-of-list flags in last SB */ -+ set_sb_cmds(sb_desc, CMD_INTR | CMD_EOL); -+ /* Attach last SB descriptor to URB */ -+ urb_priv->last_sb = sb_desc; -+ tc_dbg("Created %d out SBs for Isoc URB:0x%x\n", -+ urb->number_of_packets, (unsigned int)urb); -+ } else { /* In Isoc URB */ -+ /* Actual number of packets is not relevant for periodic in traffic as -+ long as it is more than zero. Set to 1 always. */ -+ sb_desc = create_sb(sb_desc, TT_IN, NULL, 1, mem_flags); -+ if(sb_desc == NULL) -+ return -ENOMEM; -+ /* Set end-of-list flags for SB */ -+ set_sb_cmds(sb_desc, CMD_EOL); -+ -+ /* Attach SB to URB */ -+ urb_priv->first_sb = sb_desc; -+ urb_priv->last_sb = sb_desc; -+ } -+ break; -+ default: -+ tc_err("Unknown pipe-type\n"); -+ return -EPIPE; -+ break; -+ } -+ return 0; -+} -+ -+int init_intr_urb(struct urb *urb, int mem_flags) { -+ struct crisv10_urb_priv *urb_priv = (struct crisv10_urb_priv *)urb->hcpriv; -+ struct USB_EP_Desc* ep_desc; -+ int interval; -+ int i; -+ int ep_count; -+ -+ ASSERT(urb_priv != NULL); -+ ASSERT(usb_pipeint(urb->pipe)); -+ /* We can't support interval longer than amount of eof descriptors in -+ TxIntrEPList */ -+ if(urb->interval > MAX_INTR_INTERVAL) { -+ tc_err("Interrupt interval %dms too big (max: %dms)\n", urb->interval, -+ MAX_INTR_INTERVAL); -+ return -EINVAL; -+ } -+ -+ /* We assume that the SB descriptors already have been setup */ -+ ASSERT(urb_priv->first_sb != NULL); -+ -+ /* Round of the interval to 2^n, it is obvious that this code favours -+ smaller numbers, but that is actually a good thing */ -+ /* FIXME: The "rounding error" for larger intervals will be quite -+ large. For in traffic this shouldn't be a problem since it will only -+ mean that we "poll" more often. */ -+ interval = urb->interval; -+ for (i = 0; interval; i++) { -+ interval = interval >> 1; -+ } -+ urb_priv->interval = 1 << (i - 1); -+ -+ /* We can only have max interval for Out Interrupt due to that we can only -+ handle one linked in EP for a certain epid in the Intr descr array at the -+ time. The USB Controller in the Etrax 100LX continues to process Intr EPs -+ so we have no way of knowing which one that caused the actual transfer if -+ we have several linked in. */ -+ if(usb_pipeout(urb->pipe)) { -+ urb_priv->interval = MAX_INTR_INTERVAL; -+ } -+ -+ /* Calculate amount of EPs needed */ -+ ep_count = MAX_INTR_INTERVAL / urb_priv->interval; -+ -+ for(i = 0; i < ep_count; i++) { -+ ep_desc = create_ep(urb_priv->epid, urb_priv->first_sb, mem_flags); -+ if(ep_desc == NULL) { -+ /* Free any descriptors that we may have allocated before failure */ -+ while(i > 0) { -+ i--; -+ kfree(urb_priv->intr_ep_pool[i]); -+ } -+ return -ENOMEM; -+ } -+ urb_priv->intr_ep_pool[i] = ep_desc; -+ } -+ urb_priv->intr_ep_pool_length = ep_count; -+ return 0; -+} -+ -+/* DMA RX/TX functions */ -+/* ----------------------- */ -+ -+static void tc_dma_init_rx_list(void) { -+ int i; -+ -+ /* Setup descriptor list except last one */ -+ for (i = 0; i < (NBR_OF_RX_DESC - 1); i++) { -+ RxDescList[i].sw_len = RX_DESC_BUF_SIZE; -+ RxDescList[i].command = 0; -+ RxDescList[i].next = virt_to_phys(&RxDescList[i + 1]); -+ RxDescList[i].buf = virt_to_phys(RxBuf + (i * RX_DESC_BUF_SIZE)); -+ RxDescList[i].hw_len = 0; -+ RxDescList[i].status = 0; -+ -+ /* DMA IN cache bug. (struct etrax_dma_descr has the same layout as -+ USB_IN_Desc for the relevant fields.) */ -+ prepare_rx_descriptor((struct etrax_dma_descr*)&RxDescList[i]); -+ -+ } -+ /* Special handling of last descriptor */ -+ RxDescList[i].sw_len = RX_DESC_BUF_SIZE; -+ RxDescList[i].command = IO_STATE(USB_IN_command, eol, yes); -+ RxDescList[i].next = virt_to_phys(&RxDescList[0]); -+ RxDescList[i].buf = virt_to_phys(RxBuf + (i * RX_DESC_BUF_SIZE)); -+ RxDescList[i].hw_len = 0; -+ RxDescList[i].status = 0; -+ -+ /* Setup list pointers that show progress in list */ -+ myNextRxDesc = &RxDescList[0]; -+ myLastRxDesc = &RxDescList[NBR_OF_RX_DESC - 1]; -+ -+ flush_etrax_cache(); -+ /* Point DMA to first descriptor in list and start it */ -+ *R_DMA_CH9_FIRST = virt_to_phys(myNextRxDesc); -+ *R_DMA_CH9_CMD = IO_STATE(R_DMA_CH9_CMD, cmd, start); -+} -+ -+ -+static void tc_dma_init_tx_bulk_list(void) { -+ int i; -+ volatile struct USB_EP_Desc *epDescr; -+ -+ for (i = 0; i < (NBR_OF_EPIDS - 1); i++) { -+ epDescr = &(TxBulkEPList[i]); -+ CHECK_ALIGN(epDescr); -+ epDescr->hw_len = 0; -+ epDescr->command = IO_FIELD(USB_EP_command, epid, i); -+ epDescr->sub = 0; -+ epDescr->next = virt_to_phys(&TxBulkEPList[i + 1]); -+ -+ /* Initiate two EPs, disabled and with the eol flag set. No need for any -+ preserved epid. */ -+ -+ /* The first one has the intr flag set so we get an interrupt when the DMA -+ channel is about to become disabled. */ -+ CHECK_ALIGN(&TxBulkDummyEPList[i][0]); -+ TxBulkDummyEPList[i][0].hw_len = 0; -+ TxBulkDummyEPList[i][0].command = (IO_FIELD(USB_EP_command, epid, DUMMY_EPID) | -+ IO_STATE(USB_EP_command, eol, yes) | -+ IO_STATE(USB_EP_command, intr, yes)); -+ TxBulkDummyEPList[i][0].sub = 0; -+ TxBulkDummyEPList[i][0].next = virt_to_phys(&TxBulkDummyEPList[i][1]); -+ -+ /* The second one. */ -+ CHECK_ALIGN(&TxBulkDummyEPList[i][1]); -+ TxBulkDummyEPList[i][1].hw_len = 0; -+ TxBulkDummyEPList[i][1].command = (IO_FIELD(USB_EP_command, epid, DUMMY_EPID) | -+ IO_STATE(USB_EP_command, eol, yes)); -+ TxBulkDummyEPList[i][1].sub = 0; -+ /* The last dummy's next pointer is the same as the current EP's next pointer. */ -+ TxBulkDummyEPList[i][1].next = virt_to_phys(&TxBulkEPList[i + 1]); -+ } -+ -+ /* Special handling of last descr in list, make list circular */ -+ epDescr = &TxBulkEPList[i]; -+ CHECK_ALIGN(epDescr); -+ epDescr->hw_len = 0; -+ epDescr->command = IO_STATE(USB_EP_command, eol, yes) | -+ IO_FIELD(USB_EP_command, epid, i); -+ epDescr->sub = 0; -+ epDescr->next = virt_to_phys(&TxBulkEPList[0]); -+ -+ /* Init DMA sub-channel pointers to last item in each list */ -+ *R_DMA_CH8_SUB0_EP = virt_to_phys(&TxBulkEPList[i]); -+ /* No point in starting the bulk channel yet. -+ *R_DMA_CH8_SUB0_CMD = IO_STATE(R_DMA_CH8_SUB0_CMD, cmd, start); */ -+} -+ -+static void tc_dma_init_tx_ctrl_list(void) { -+ int i; -+ volatile struct USB_EP_Desc *epDescr; -+ -+ for (i = 0; i < (NBR_OF_EPIDS - 1); i++) { -+ epDescr = &(TxCtrlEPList[i]); -+ CHECK_ALIGN(epDescr); -+ epDescr->hw_len = 0; -+ epDescr->command = IO_FIELD(USB_EP_command, epid, i); -+ epDescr->sub = 0; -+ epDescr->next = virt_to_phys(&TxCtrlEPList[i + 1]); -+ } -+ /* Special handling of last descr in list, make list circular */ -+ epDescr = &TxCtrlEPList[i]; -+ CHECK_ALIGN(epDescr); -+ epDescr->hw_len = 0; -+ epDescr->command = IO_STATE(USB_EP_command, eol, yes) | -+ IO_FIELD(USB_EP_command, epid, i); -+ epDescr->sub = 0; -+ epDescr->next = virt_to_phys(&TxCtrlEPList[0]); -+ -+ /* Init DMA sub-channel pointers to last item in each list */ -+ *R_DMA_CH8_SUB1_EP = virt_to_phys(&TxCtrlEPList[i]); -+ /* No point in starting the ctrl channel yet. -+ *R_DMA_CH8_SUB1_CMD = IO_STATE(R_DMA_CH8_SUB0_CMD, cmd, start); */ -+} -+ -+ -+static void tc_dma_init_tx_intr_list(void) { -+ int i; -+ -+ TxIntrSB_zout.sw_len = 1; -+ TxIntrSB_zout.next = 0; -+ TxIntrSB_zout.buf = virt_to_phys(&zout_buffer[0]); -+ TxIntrSB_zout.command = (IO_FIELD(USB_SB_command, rem, 0) | -+ IO_STATE(USB_SB_command, tt, zout) | -+ IO_STATE(USB_SB_command, full, yes) | -+ IO_STATE(USB_SB_command, eot, yes) | -+ IO_STATE(USB_SB_command, eol, yes)); -+ -+ for (i = 0; i < (MAX_INTR_INTERVAL - 1); i++) { -+ CHECK_ALIGN(&TxIntrEPList[i]); -+ TxIntrEPList[i].hw_len = 0; -+ TxIntrEPList[i].command = -+ (IO_STATE(USB_EP_command, eof, yes) | -+ IO_STATE(USB_EP_command, enable, yes) | -+ IO_FIELD(USB_EP_command, epid, INVALID_EPID)); -+ TxIntrEPList[i].sub = virt_to_phys(&TxIntrSB_zout); -+ TxIntrEPList[i].next = virt_to_phys(&TxIntrEPList[i + 1]); -+ } -+ -+ /* Special handling of last descr in list, make list circular */ -+ CHECK_ALIGN(&TxIntrEPList[i]); -+ TxIntrEPList[i].hw_len = 0; -+ TxIntrEPList[i].command = -+ (IO_STATE(USB_EP_command, eof, yes) | -+ IO_STATE(USB_EP_command, eol, yes) | -+ IO_STATE(USB_EP_command, enable, yes) | -+ IO_FIELD(USB_EP_command, epid, INVALID_EPID)); -+ TxIntrEPList[i].sub = virt_to_phys(&TxIntrSB_zout); -+ TxIntrEPList[i].next = virt_to_phys(&TxIntrEPList[0]); -+ -+ intr_dbg("Initiated Intr EP descriptor list\n"); -+ -+ -+ /* Connect DMA 8 sub-channel 2 to first in list */ -+ *R_DMA_CH8_SUB2_EP = virt_to_phys(&TxIntrEPList[0]); -+} -+ -+static void tc_dma_init_tx_isoc_list(void) { -+ int i; -+ -+ DBFENTER; -+ -+ /* Read comment at zout_buffer declaration for an explanation to this. */ -+ TxIsocSB_zout.sw_len = 1; -+ TxIsocSB_zout.next = 0; -+ TxIsocSB_zout.buf = virt_to_phys(&zout_buffer[0]); -+ TxIsocSB_zout.command = (IO_FIELD(USB_SB_command, rem, 0) | -+ IO_STATE(USB_SB_command, tt, zout) | -+ IO_STATE(USB_SB_command, full, yes) | -+ IO_STATE(USB_SB_command, eot, yes) | -+ IO_STATE(USB_SB_command, eol, yes)); -+ -+ /* The last isochronous EP descriptor is a dummy. */ -+ for (i = 0; i < (NBR_OF_EPIDS - 1); i++) { -+ CHECK_ALIGN(&TxIsocEPList[i]); -+ TxIsocEPList[i].hw_len = 0; -+ TxIsocEPList[i].command = IO_FIELD(USB_EP_command, epid, i); -+ TxIsocEPList[i].sub = 0; -+ TxIsocEPList[i].next = virt_to_phys(&TxIsocEPList[i + 1]); -+ } -+ -+ CHECK_ALIGN(&TxIsocEPList[i]); -+ TxIsocEPList[i].hw_len = 0; -+ -+ /* Must enable the last EP descr to get eof interrupt. */ -+ TxIsocEPList[i].command = (IO_STATE(USB_EP_command, enable, yes) | -+ IO_STATE(USB_EP_command, eof, yes) | -+ IO_STATE(USB_EP_command, eol, yes) | -+ IO_FIELD(USB_EP_command, epid, INVALID_EPID)); -+ TxIsocEPList[i].sub = virt_to_phys(&TxIsocSB_zout); -+ TxIsocEPList[i].next = virt_to_phys(&TxIsocEPList[0]); -+ -+ *R_DMA_CH8_SUB3_EP = virt_to_phys(&TxIsocEPList[0]); -+ *R_DMA_CH8_SUB3_CMD = IO_STATE(R_DMA_CH8_SUB3_CMD, cmd, start); -+} -+ -+static int tc_dma_init(struct usb_hcd *hcd) { -+ tc_dma_init_rx_list(); -+ tc_dma_init_tx_bulk_list(); -+ tc_dma_init_tx_ctrl_list(); -+ tc_dma_init_tx_intr_list(); -+ tc_dma_init_tx_isoc_list(); -+ -+ if (cris_request_dma(USB_TX_DMA_NBR, -+ "ETRAX 100LX built-in USB (Tx)", -+ DMA_VERBOSE_ON_ERROR, -+ dma_usb)) { -+ err("Could not allocate DMA ch 8 for USB"); -+ return -EBUSY; -+ } -+ -+ if (cris_request_dma(USB_RX_DMA_NBR, -+ "ETRAX 100LX built-in USB (Rx)", -+ DMA_VERBOSE_ON_ERROR, -+ dma_usb)) { -+ err("Could not allocate DMA ch 9 for USB"); -+ return -EBUSY; -+ } -+ -+ *R_IRQ_MASK2_SET = -+ /* Note that these interrupts are not used. */ -+ IO_STATE(R_IRQ_MASK2_SET, dma8_sub0_descr, set) | -+ /* Sub channel 1 (ctrl) descr. interrupts are used. */ -+ IO_STATE(R_IRQ_MASK2_SET, dma8_sub1_descr, set) | -+ IO_STATE(R_IRQ_MASK2_SET, dma8_sub2_descr, set) | -+ /* Sub channel 3 (isoc) descr. interrupts are used. */ -+ IO_STATE(R_IRQ_MASK2_SET, dma8_sub3_descr, set); -+ -+ /* Note that the dma9_descr interrupt is not used. */ -+ *R_IRQ_MASK2_SET = -+ IO_STATE(R_IRQ_MASK2_SET, dma9_eop, set) | -+ IO_STATE(R_IRQ_MASK2_SET, dma9_descr, set); -+ -+ if (request_irq(ETRAX_USB_RX_IRQ, tc_dma_rx_interrupt, 0, -+ "ETRAX 100LX built-in USB (Rx)", hcd)) { -+ err("Could not allocate IRQ %d for USB", ETRAX_USB_RX_IRQ); -+ return -EBUSY; -+ } -+ -+ if (request_irq(ETRAX_USB_TX_IRQ, tc_dma_tx_interrupt, 0, -+ "ETRAX 100LX built-in USB (Tx)", hcd)) { -+ err("Could not allocate IRQ %d for USB", ETRAX_USB_TX_IRQ); -+ return -EBUSY; -+ } -+ -+ return 0; -+} -+ -+static void tc_dma_destroy(void) { -+ free_irq(ETRAX_USB_RX_IRQ, NULL); -+ free_irq(ETRAX_USB_TX_IRQ, NULL); -+ -+ cris_free_dma(USB_TX_DMA_NBR, "ETRAX 100LX built-in USB (Tx)"); -+ cris_free_dma(USB_RX_DMA_NBR, "ETRAX 100LX built-in USB (Rx)"); -+ -+} -+ -+static void tc_dma_link_intr_urb(struct urb *urb); -+ -+/* Handle processing of Bulk, Ctrl and Intr queues */ -+static void tc_dma_process_queue(int epid) { -+ struct urb *urb; -+ struct crisv10_urb_priv *urb_priv = urb->hcpriv; -+ unsigned long flags; -+ char toggle; -+ -+ if(epid_state[epid].disabled) { -+ /* Don't process any URBs on a disabled endpoint */ -+ return; -+ } -+ -+ /* Do not disturb us while fiddling with EPs and epids */ -+ local_irq_save(flags); -+ -+ /* For bulk, Ctrl and Intr can we only have one URB active at a time for -+ a specific EP. */ -+ if(activeUrbList[epid] != NULL) { -+ /* An URB is already active on EP, skip checking queue */ -+ local_irq_restore(flags); -+ return; -+ } -+ -+ urb = urb_list_first(epid); -+ if(urb == NULL) { -+ /* No URB waiting in EP queue. Nothing do to */ -+ local_irq_restore(flags); -+ return; -+ } -+ -+ urb_priv = urb->hcpriv; -+ ASSERT(urb_priv != NULL); -+ ASSERT(urb_priv->urb_state == NOT_STARTED); -+ ASSERT(!usb_pipeisoc(urb->pipe)); -+ -+ /* Remove this URB from the queue and move it to active */ -+ activeUrbList[epid] = urb; -+ urb_list_del(urb, epid); -+ -+ urb_priv->urb_state = STARTED; -+ -+ /* Reset error counters (regardless of which direction this traffic is). */ -+ etrax_epid_clear_error(epid); -+ -+ /* Special handling of Intr EP lists */ -+ if(usb_pipeint(urb->pipe)) { -+ tc_dma_link_intr_urb(urb); -+ local_irq_restore(flags); -+ return; -+ } -+ -+ /* Software must preset the toggle bits for Bulk and Ctrl */ -+ if(usb_pipecontrol(urb->pipe)) { -+ /* Toggle bits are initialized only during setup transaction in a -+ CTRL transfer */ -+ etrax_epid_set_toggle(epid, 0, 0); -+ etrax_epid_set_toggle(epid, 1, 0); -+ } else { -+ toggle = usb_gettoggle(urb->dev, usb_pipeendpoint(urb->pipe), -+ usb_pipeout(urb->pipe)); -+ etrax_epid_set_toggle(epid, usb_pipeout(urb->pipe), toggle); -+ } -+ -+ tc_dbg("Added SBs from (URB:0x%x %s %s) to epid %d: %s\n", -+ (unsigned int)urb, str_dir(urb->pipe), str_type(urb->pipe), epid, -+ sblist_to_str(urb_priv->first_sb)); -+ -+ /* We start the DMA sub channel without checking if it's running or not, -+ because: -+ 1) If it's already running, issuing the start command is a nop. -+ 2) We avoid a test-and-set race condition. */ -+ switch(usb_pipetype(urb->pipe)) { -+ case PIPE_BULK: -+ /* Assert that the EP descriptor is disabled. */ -+ ASSERT(!(TxBulkEPList[epid].command & IO_MASK(USB_EP_command, enable))); -+ -+ /* Set up and enable the EP descriptor. */ -+ TxBulkEPList[epid].sub = virt_to_phys(urb_priv->first_sb); -+ TxBulkEPList[epid].hw_len = 0; -+ TxBulkEPList[epid].command |= IO_STATE(USB_EP_command, enable, yes); -+ -+ /* Check if the dummy list is already with us (if several urbs were queued). */ -+ if (usb_pipein(urb->pipe) && (TxBulkEPList[epid].next != virt_to_phys(&TxBulkDummyEPList[epid][0]))) { -+ tc_dbg("Inviting dummy list to the party for urb 0x%lx, epid %d", -+ (unsigned long)urb, epid); -+ -+ /* We don't need to check if the DMA is at this EP or not before changing the -+ next pointer, since we will do it in one 32-bit write (EP descriptors are -+ 32-bit aligned). */ -+ TxBulkEPList[epid].next = virt_to_phys(&TxBulkDummyEPList[epid][0]); -+ } -+ -+ restart_dma8_sub0(); -+ -+ /* Update/restart the bulk start timer since we just started the channel.*/ -+ mod_timer(&bulk_start_timer, jiffies + BULK_START_TIMER_INTERVAL); -+ /* Update/restart the bulk eot timer since we just inserted traffic. */ -+ mod_timer(&bulk_eot_timer, jiffies + BULK_EOT_TIMER_INTERVAL); -+ break; -+ case PIPE_CONTROL: -+ /* Assert that the EP descriptor is disabled. */ -+ ASSERT(!(TxCtrlEPList[epid].command & IO_MASK(USB_EP_command, enable))); -+ -+ /* Set up and enable the EP descriptor. */ -+ TxCtrlEPList[epid].sub = virt_to_phys(urb_priv->first_sb); -+ TxCtrlEPList[epid].hw_len = 0; -+ TxCtrlEPList[epid].command |= IO_STATE(USB_EP_command, enable, yes); -+ -+ *R_DMA_CH8_SUB1_CMD = IO_STATE(R_DMA_CH8_SUB1_CMD, cmd, start); -+ break; -+ } -+ local_irq_restore(flags); -+} -+ -+static void tc_dma_link_intr_urb(struct urb *urb) { -+ struct crisv10_urb_priv *urb_priv = urb->hcpriv; -+ volatile struct USB_EP_Desc *tmp_ep; -+ struct USB_EP_Desc *ep_desc; -+ int i = 0, epid; -+ int pool_idx = 0; -+ -+ ASSERT(urb_priv != NULL); -+ epid = urb_priv->epid; -+ ASSERT(urb_priv->interval > 0); -+ ASSERT(urb_priv->intr_ep_pool_length > 0); -+ -+ tmp_ep = &TxIntrEPList[0]; -+ -+ /* Only insert one EP descriptor in list for Out Intr URBs. -+ We can only handle Out Intr with interval of 128ms because -+ it's not possible to insert several Out Intr EPs because they -+ are not consumed by the DMA. */ -+ if(usb_pipeout(urb->pipe)) { -+ ep_desc = urb_priv->intr_ep_pool[0]; -+ ASSERT(ep_desc); -+ ep_desc->next = tmp_ep->next; -+ tmp_ep->next = virt_to_phys(ep_desc); -+ i++; -+ } else { -+ /* Loop through Intr EP descriptor list and insert EP for URB at -+ specified interval */ -+ do { -+ /* Each EP descriptor with eof flag sat signals a new frame */ -+ if (tmp_ep->command & IO_MASK(USB_EP_command, eof)) { -+ /* Insert a EP from URBs EP pool at correct interval */ -+ if ((i % urb_priv->interval) == 0) { -+ ep_desc = urb_priv->intr_ep_pool[pool_idx]; -+ ASSERT(ep_desc); -+ ep_desc->next = tmp_ep->next; -+ tmp_ep->next = virt_to_phys(ep_desc); -+ pool_idx++; -+ ASSERT(pool_idx <= urb_priv->intr_ep_pool_length); -+ } -+ i++; -+ } -+ tmp_ep = (struct USB_EP_Desc *)phys_to_virt(tmp_ep->next); -+ } while(tmp_ep != &TxIntrEPList[0]); -+ } -+ -+ intr_dbg("Added SBs to intr epid %d: %s interval:%d (%d EP)\n", epid, -+ sblist_to_str(urb_priv->first_sb), urb_priv->interval, pool_idx); -+ -+ /* We start the DMA sub channel without checking if it's running or not, -+ because: -+ 1) If it's already running, issuing the start command is a nop. -+ 2) We avoid a test-and-set race condition. */ -+ *R_DMA_CH8_SUB2_CMD = IO_STATE(R_DMA_CH8_SUB2_CMD, cmd, start); -+} -+ -+ /* hinko ignore usb_pipeisoc */ -+#if 0 -+static void tc_dma_process_isoc_urb(struct urb *urb) { -+ unsigned long flags; -+ struct crisv10_urb_priv *urb_priv = urb->hcpriv; -+ int epid; -+ -+ /* Do not disturb us while fiddling with EPs and epids */ -+ local_irq_save(flags); -+ -+ ASSERT(urb_priv); -+ ASSERT(urb_priv->first_sb); -+ epid = urb_priv->epid; -+ -+ if(activeUrbList[epid] == NULL) { -+ /* EP is idle, so make this URB active */ -+ activeUrbList[epid] = urb; -+ urb_list_del(urb, epid); -+ ASSERT(TxIsocEPList[epid].sub == 0); -+ ASSERT(!(TxIsocEPList[epid].command & -+ IO_STATE(USB_EP_command, enable, yes))); -+ -+ /* Differentiate between In and Out Isoc. Because In SBs are not consumed*/ -+ if(usb_pipein(urb->pipe)) { -+ /* Each EP for In Isoc will have only one SB descriptor, setup when -+ submitting the first active urb. We do it here by copying from URBs -+ pre-allocated SB. */ -+ memcpy((void *)&(TxIsocSBList[epid]), urb_priv->first_sb, -+ sizeof(TxIsocSBList[epid])); -+ TxIsocEPList[epid].hw_len = 0; -+ TxIsocEPList[epid].sub = virt_to_phys(&(TxIsocSBList[epid])); -+ } else { -+ /* For Out Isoc we attach the pre-allocated list of SBs for the URB */ -+ TxIsocEPList[epid].hw_len = 0; -+ TxIsocEPList[epid].sub = virt_to_phys(urb_priv->first_sb); -+ -+ isoc_dbg("Attached first URB:0x%x[%d] to epid:%d first_sb:0x%x" -+ " last_sb::0x%x\n", -+ (unsigned int)urb, urb_priv->urb_num, epid, -+ (unsigned int)(urb_priv->first_sb), -+ (unsigned int)(urb_priv->last_sb)); -+ } -+ -+ if (urb->transfer_flags & URB_ISO_ASAP) { -+ /* The isoc transfer should be started as soon as possible. The -+ start_frame field is a return value if URB_ISO_ASAP was set. Comparing -+ R_USB_FM_NUMBER with a USB Chief trace shows that the first isoc IN -+ token is sent 2 frames later. I'm not sure how this affects usage of -+ the start_frame field by the device driver, or how it affects things -+ when USB_ISO_ASAP is not set, so therefore there's no compensation for -+ the 2 frame "lag" here. */ -+ urb->start_frame = (*R_USB_FM_NUMBER & 0x7ff); -+ TxIsocEPList[epid].command |= IO_STATE(USB_EP_command, enable, yes); -+ urb_priv->urb_state = STARTED; -+ isoc_dbg("URB_ISO_ASAP set, urb->start_frame set to %d\n", -+ urb->start_frame); -+ } else { -+ /* Not started yet. */ -+ urb_priv->urb_state = NOT_STARTED; -+ isoc_warn("urb_priv->urb_state set to NOT_STARTED for URB:0x%x\n", -+ (unsigned int)urb); -+ } -+ -+ } else { -+ /* An URB is already active on the EP. Leave URB in queue and let -+ finish_isoc_urb process it after current active URB */ -+ ASSERT(TxIsocEPList[epid].sub != 0); -+ -+ if(usb_pipein(urb->pipe)) { -+ /* Because there already is a active In URB on this epid we do nothing -+ and the finish_isoc_urb() function will handle switching to next URB*/ -+ -+ } else { /* For Out Isoc, insert new URBs traffic last in SB-list. */ -+ struct USB_SB_Desc *temp_sb_desc; -+ -+ /* Set state STARTED to all Out Isoc URBs added to SB list because we -+ don't know how many of them that are finished before descr interrupt*/ -+ urb_priv->urb_state = STARTED; -+ -+ /* Find end of current SB list by looking for SB with eol flag sat */ -+ temp_sb_desc = phys_to_virt(TxIsocEPList[epid].sub); -+ while ((temp_sb_desc->command & IO_MASK(USB_SB_command, eol)) != -+ IO_STATE(USB_SB_command, eol, yes)) { -+ ASSERT(temp_sb_desc->next); -+ temp_sb_desc = phys_to_virt(temp_sb_desc->next); -+ } -+ -+ isoc_dbg("Appended URB:0x%x[%d] (first:0x%x last:0x%x) to epid:%d" -+ " sub:0x%x eol:0x%x\n", -+ (unsigned int)urb, urb_priv->urb_num, -+ (unsigned int)(urb_priv->first_sb), -+ (unsigned int)(urb_priv->last_sb), epid, -+ (unsigned int)phys_to_virt(TxIsocEPList[epid].sub), -+ (unsigned int)temp_sb_desc); -+ -+ /* Next pointer must be set before eol is removed. */ -+ temp_sb_desc->next = virt_to_phys(urb_priv->first_sb); -+ /* Clear the previous end of list flag since there is a new in the -+ added SB descriptor list. */ -+ temp_sb_desc->command &= ~IO_MASK(USB_SB_command, eol); -+ -+ if (!(TxIsocEPList[epid].command & IO_MASK(USB_EP_command, enable))) { -+ __u32 epid_data; -+ /* 8.8.5 in Designer's Reference says we should check for and correct -+ any errors in the EP here. That should not be necessary if -+ epid_attn is handled correctly, so we assume all is ok. */ -+ epid_data = etrax_epid_iso_get(epid); -+ if (IO_EXTRACT(R_USB_EPT_DATA, error_code, epid_data) != -+ IO_STATE_VALUE(R_USB_EPT_DATA, error_code, no_error)) { -+ isoc_err("Disabled Isoc EP with error:%d on epid:%d when appending" -+ " URB:0x%x[%d]\n", -+ IO_EXTRACT(R_USB_EPT_DATA, error_code, epid_data), epid, -+ (unsigned int)urb, urb_priv->urb_num); -+ } -+ -+ /* The SB list was exhausted. */ -+ if (virt_to_phys(urb_priv->last_sb) != TxIsocEPList[epid].sub) { -+ /* The new sublist did not get processed before the EP was -+ disabled. Setup the EP again. */ -+ -+ if(virt_to_phys(temp_sb_desc) == TxIsocEPList[epid].sub) { -+ isoc_dbg("EP for epid:%d stoped at SB:0x%x before newly inserted" -+ ", restarting from this URBs SB:0x%x\n", -+ epid, (unsigned int)temp_sb_desc, -+ (unsigned int)(urb_priv->first_sb)); -+ TxIsocEPList[epid].hw_len = 0; -+ TxIsocEPList[epid].sub = virt_to_phys(urb_priv->first_sb); -+ urb->start_frame = (*R_USB_FM_NUMBER & 0x7ff); -+ /* Enable the EP again so data gets processed this time */ -+ TxIsocEPList[epid].command |= -+ IO_STATE(USB_EP_command, enable, yes); -+ -+ } else { -+ /* The EP has been disabled but not at end this URB (god knows -+ where). This should generate an epid_attn so we should not be -+ here */ -+ isoc_warn("EP was disabled on sb:0x%x before SB list for" -+ " URB:0x%x[%d] got processed\n", -+ (unsigned int)phys_to_virt(TxIsocEPList[epid].sub), -+ (unsigned int)urb, urb_priv->urb_num); -+ } -+ } else { -+ /* This might happend if we are slow on this function and isn't -+ an error. */ -+ isoc_dbg("EP was disabled and finished with SBs from appended" -+ " URB:0x%x[%d]\n", (unsigned int)urb, urb_priv->urb_num); -+ } -+ } -+ } -+ } -+ -+ /* Start the DMA sub channel */ -+ *R_DMA_CH8_SUB3_CMD = IO_STATE(R_DMA_CH8_SUB3_CMD, cmd, start); -+ -+ local_irq_restore(flags); -+} -+#endif -+ -+static void tc_dma_unlink_intr_urb(struct urb *urb) { -+ struct crisv10_urb_priv *urb_priv = urb->hcpriv; -+ volatile struct USB_EP_Desc *first_ep; /* First EP in the list. */ -+ volatile struct USB_EP_Desc *curr_ep; /* Current EP, the iterator. */ -+ volatile struct USB_EP_Desc *next_ep; /* The EP after current. */ -+ volatile struct USB_EP_Desc *unlink_ep; /* The one we should remove from -+ the list. */ -+ int count = 0; -+ volatile int timeout = 10000; -+ int epid; -+ -+ /* Read 8.8.4 in Designer's Reference, "Removing an EP Descriptor from the -+ List". */ -+ ASSERT(urb_priv); -+ ASSERT(urb_priv->intr_ep_pool_length > 0); -+ epid = urb_priv->epid; -+ -+ /* First disable all Intr EPs belonging to epid for this URB */ -+ first_ep = &TxIntrEPList[0]; -+ curr_ep = first_ep; -+ do { -+ next_ep = (struct USB_EP_Desc *)phys_to_virt(curr_ep->next); -+ if (IO_EXTRACT(USB_EP_command, epid, next_ep->command) == epid) { -+ /* Disable EP */ -+ next_ep->command &= ~IO_MASK(USB_EP_command, enable); -+ } -+ curr_ep = phys_to_virt(curr_ep->next); -+ } while (curr_ep != first_ep); -+ -+ -+ /* Now unlink all EPs belonging to this epid from Descr list */ -+ first_ep = &TxIntrEPList[0]; -+ curr_ep = first_ep; -+ do { -+ next_ep = (struct USB_EP_Desc *)phys_to_virt(curr_ep->next); -+ if (IO_EXTRACT(USB_EP_command, epid, next_ep->command) == epid) { -+ /* This is the one we should unlink. */ -+ unlink_ep = next_ep; -+ -+ /* Actually unlink the EP from the DMA list. */ -+ curr_ep->next = unlink_ep->next; -+ -+ /* Wait until the DMA is no longer at this descriptor. */ -+ while((*R_DMA_CH8_SUB2_EP == virt_to_phys(unlink_ep)) && -+ (timeout-- > 0)); -+ if(timeout == 0) { -+ warn("Timeout while waiting for DMA-TX-Intr to leave unlink EP\n"); -+ } -+ -+ count++; -+ } -+ curr_ep = phys_to_virt(curr_ep->next); -+ } while (curr_ep != first_ep); -+ -+ if(count != urb_priv->intr_ep_pool_length) { -+ intr_warn("Unlinked %d of %d Intr EPs for URB:0x%x[%d]\n", count, -+ urb_priv->intr_ep_pool_length, (unsigned int)urb, -+ urb_priv->urb_num); -+ } else { -+ intr_dbg("Unlinked %d of %d interrupt EPs for URB:0x%x\n", count, -+ urb_priv->intr_ep_pool_length, (unsigned int)urb); -+ } -+} -+ -+static void check_finished_bulk_tx_epids(struct usb_hcd *hcd, -+ int timer) { -+ unsigned long flags; -+ int epid; -+ struct urb *urb; -+ struct crisv10_urb_priv * urb_priv; -+ __u32 epid_data; -+ -+ /* Protect TxEPList */ -+ local_irq_save(flags); -+ -+ for (epid = 0; epid < NBR_OF_EPIDS; epid++) { -+ /* A finished EP descriptor is disabled and has a valid sub pointer */ -+ if (!(TxBulkEPList[epid].command & IO_MASK(USB_EP_command, enable)) && -+ (TxBulkEPList[epid].sub != 0)) { -+ -+ /* Get the active URB for this epid */ -+ urb = activeUrbList[epid]; -+ /* Sanity checks */ -+ ASSERT(urb); -+ urb_priv = (struct crisv10_urb_priv *)urb->hcpriv; -+ ASSERT(urb_priv); -+ -+ /* Only handle finished out Bulk EPs here, -+ and let RX interrupt take care of the rest */ -+ if(!epid_out_traffic(epid)) { -+ continue; -+ } -+ -+ if(timer) { -+ tc_warn("Found finished %s Bulk epid:%d URB:0x%x[%d] from timeout\n", -+ epid_out_traffic(epid) ? "Out" : "In", epid, (unsigned int)urb, -+ urb_priv->urb_num); -+ } else { -+ tc_dbg("Found finished %s Bulk epid:%d URB:0x%x[%d] from interrupt\n", -+ epid_out_traffic(epid) ? "Out" : "In", epid, (unsigned int)urb, -+ urb_priv->urb_num); -+ } -+ -+ if(urb_priv->urb_state == UNLINK) { -+ /* This Bulk URB is requested to be unlinked, that means that the EP -+ has been disabled and we might not have sent all data */ -+ tc_finish_urb(hcd, urb, urb->status); -+ continue; -+ } -+ -+ ASSERT(urb_priv->urb_state == STARTED); -+ if (phys_to_virt(TxBulkEPList[epid].sub) != urb_priv->last_sb) { -+ tc_err("Endpoint got disabled before reaching last sb\n"); -+ } -+ -+ epid_data = etrax_epid_get(epid); -+ if (IO_EXTRACT(R_USB_EPT_DATA, error_code, epid_data) == -+ IO_STATE_VALUE(R_USB_EPT_DATA, error_code, no_error)) { -+ /* This means that the endpoint has no error, is disabled -+ and had inserted traffic, i.e. transfer successfully completed. */ -+ tc_finish_urb(hcd, urb, 0); -+ } else { -+ /* Shouldn't happen. We expect errors to be caught by epid -+ attention. */ -+ tc_err("Found disabled bulk EP desc (epid:%d error:%d)\n", -+ epid, IO_EXTRACT(R_USB_EPT_DATA, error_code, epid_data)); -+ } -+ } else { -+ tc_dbg("Ignoring In Bulk epid:%d, let RX interrupt handle it\n", epid); -+ } -+ } -+ -+ local_irq_restore(flags); -+} -+ -+static void check_finished_ctrl_tx_epids(struct usb_hcd *hcd) { -+ unsigned long flags; -+ int epid; -+ struct urb *urb; -+ struct crisv10_urb_priv * urb_priv; -+ __u32 epid_data; -+ -+ /* Protect TxEPList */ -+ local_irq_save(flags); -+ -+ for (epid = 0; epid < NBR_OF_EPIDS; epid++) { -+ if(epid == DUMMY_EPID) -+ continue; -+ -+ /* A finished EP descriptor is disabled and has a valid sub pointer */ -+ if (!(TxCtrlEPList[epid].command & IO_MASK(USB_EP_command, enable)) && -+ (TxCtrlEPList[epid].sub != 0)) { -+ -+ /* Get the active URB for this epid */ -+ urb = activeUrbList[epid]; -+ -+ if(urb == NULL) { -+ tc_warn("Found finished Ctrl epid:%d with no active URB\n", epid); -+ continue; -+ } -+ -+ /* Sanity checks */ -+ ASSERT(usb_pipein(urb->pipe)); -+ urb_priv = (struct crisv10_urb_priv *)urb->hcpriv; -+ ASSERT(urb_priv); -+ if (phys_to_virt(TxCtrlEPList[epid].sub) != urb_priv->last_sb) { -+ tc_err("Endpoint got disabled before reaching last sb\n"); -+ } -+ -+ epid_data = etrax_epid_get(epid); -+ if (IO_EXTRACT(R_USB_EPT_DATA, error_code, epid_data) == -+ IO_STATE_VALUE(R_USB_EPT_DATA, error_code, no_error)) { -+ /* This means that the endpoint has no error, is disabled -+ and had inserted traffic, i.e. transfer successfully completed. */ -+ -+ /* Check if RX-interrupt for In Ctrl has been processed before -+ finishing the URB */ -+ if(urb_priv->ctrl_rx_done) { -+ tc_dbg("Finishing In Ctrl URB:0x%x[%d] in tx_interrupt\n", -+ (unsigned int)urb, urb_priv->urb_num); -+ tc_finish_urb(hcd, urb, 0); -+ } else { -+ /* If we get zout descriptor interrupt before RX was done for a -+ In Ctrl transfer, then we flag that and it will be finished -+ in the RX-Interrupt */ -+ urb_priv->ctrl_zout_done = 1; -+ tc_dbg("Got zout descr interrupt before RX interrupt\n"); -+ } -+ } else { -+ /* Shouldn't happen. We expect errors to be caught by epid -+ attention. */ -+ tc_err("Found disabled Ctrl EP desc (epid:%d URB:0x%x[%d]) error_code:%d\n", epid, (unsigned int)urb, urb_priv->urb_num, IO_EXTRACT(R_USB_EPT_DATA, error_code, epid_data)); -+ __dump_ep_desc(&(TxCtrlEPList[epid])); -+ __dump_ept_data(epid); -+ } -+ } -+ } -+ local_irq_restore(flags); -+} -+ -+ /* hinko ignore usb_pipeisoc */ -+#if 0 -+/* This function goes through all epids that are setup for Out Isoc transfers -+ and marks (isoc_out_done) all queued URBs that the DMA has finished -+ transfer for. -+ No URB completetion is done here to make interrupt routine return quickly. -+ URBs are completed later with help of complete_isoc_bottom_half() that -+ becomes schedules when this functions is finished. */ -+static void check_finished_isoc_tx_epids(void) { -+ unsigned long flags; -+ int epid; -+ struct urb *urb; -+ struct crisv10_urb_priv * urb_priv; -+ struct USB_SB_Desc* sb_desc; -+ int epid_done; -+ -+ /* Protect TxIsocEPList */ -+ local_irq_save(flags); -+ -+ for (epid = 0; epid < NBR_OF_EPIDS; epid++) { -+ if (TxIsocEPList[epid].sub == 0 || epid == INVALID_EPID || -+ !epid_out_traffic(epid)) { -+ /* Nothing here to see. */ -+ continue; -+ } -+ ASSERT(epid_inuse(epid)); -+ ASSERT(epid_isoc(epid)); -+ -+ sb_desc = phys_to_virt(TxIsocEPList[epid].sub); -+ /* Find the last descriptor of the currently active URB for this ep. -+ This is the first descriptor in the sub list marked for a descriptor -+ interrupt. */ -+ while (sb_desc && !IO_EXTRACT(USB_SB_command, intr, sb_desc->command)) { -+ sb_desc = sb_desc->next ? phys_to_virt(sb_desc->next) : 0; -+ } -+ ASSERT(sb_desc); -+ -+ isoc_dbg("Descr IRQ checking epid:%d sub:0x%x intr:0x%x\n", -+ epid, (unsigned int)phys_to_virt(TxIsocEPList[epid].sub), -+ (unsigned int)sb_desc); -+ -+ urb = activeUrbList[epid]; -+ if(urb == NULL) { -+ isoc_err("Isoc Descr irq on epid:%d with no active URB\n", epid); -+ continue; -+ } -+ -+ epid_done = 0; -+ while(urb && !epid_done) { -+ /* Sanity check. */ -+ ASSERT(usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS); -+ ASSERT(usb_pipeout(urb->pipe)); -+ -+ urb_priv = (struct crisv10_urb_priv *)urb->hcpriv; -+ ASSERT(urb_priv); -+ ASSERT(urb_priv->urb_state == STARTED || -+ urb_priv->urb_state == UNLINK); -+ -+ if (sb_desc != urb_priv->last_sb) { -+ /* This urb has been sent. */ -+ urb_priv->isoc_out_done = 1; -+ -+ } else { /* Found URB that has last_sb as the interrupt reason */ -+ -+ /* Check if EP has been disabled, meaning that all transfers are done*/ -+ if(!(TxIsocEPList[epid].command & IO_MASK(USB_EP_command, enable))) { -+ ASSERT((sb_desc->command & IO_MASK(USB_SB_command, eol)) == -+ IO_STATE(USB_SB_command, eol, yes)); -+ ASSERT(sb_desc->next == 0); -+ urb_priv->isoc_out_done = 1; -+ } else { -+ isoc_dbg("Skipping URB:0x%x[%d] because EP not disabled yet\n", -+ (unsigned int)urb, urb_priv->urb_num); -+ } -+ /* Stop looking any further in queue */ -+ epid_done = 1; -+ } -+ -+ if (!epid_done) { -+ if(urb == activeUrbList[epid]) { -+ urb = urb_list_first(epid); -+ } else { -+ urb = urb_list_next(urb, epid); -+ } -+ } -+ } /* END: while(urb && !epid_done) */ -+ } -+ -+ local_irq_restore(flags); -+} -+ -+ -+/* This is where the Out Isoc URBs are realy completed. This function is -+ scheduled from tc_dma_tx_interrupt() when one or more Out Isoc transfers -+ are done. This functions completes all URBs earlier marked with -+ isoc_out_done by fast interrupt routine check_finished_isoc_tx_epids() */ -+ -+static void complete_isoc_bottom_half(void *data) { -+ struct crisv10_isoc_complete_data *comp_data; -+ struct usb_iso_packet_descriptor *packet; -+ struct crisv10_urb_priv * urb_priv; -+ unsigned long flags; -+ struct urb* urb; -+ int epid_done; -+ int epid; -+ int i; -+ -+ comp_data = (struct crisv10_isoc_complete_data*)data; -+ -+ local_irq_save(flags); -+ -+ for (epid = 0; epid < NBR_OF_EPIDS - 1; epid++) { -+ if(!epid_inuse(epid) || !epid_isoc(epid) || !epid_out_traffic(epid) || epid == DUMMY_EPID) { -+ /* Only check valid Out Isoc epids */ -+ continue; -+ } -+ -+ isoc_dbg("Isoc bottom-half checking epid:%d, sub:0x%x\n", epid, -+ (unsigned int)phys_to_virt(TxIsocEPList[epid].sub)); -+ -+ /* The descriptor interrupt handler has marked all transmitted Out Isoc -+ URBs with isoc_out_done. Now we traverse all epids and for all that -+ have out Isoc traffic we traverse its URB list and complete the -+ transmitted URBs. */ -+ epid_done = 0; -+ while (!epid_done) { -+ -+ /* Get the active urb (if any) */ -+ urb = activeUrbList[epid]; -+ if (urb == 0) { -+ isoc_dbg("No active URB on epid:%d anymore\n", epid); -+ epid_done = 1; -+ continue; -+ } -+ -+ /* Sanity check. */ -+ ASSERT(usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS); -+ ASSERT(usb_pipeout(urb->pipe)); -+ -+ urb_priv = (struct crisv10_urb_priv *)urb->hcpriv; -+ ASSERT(urb_priv); -+ -+ if (!(urb_priv->isoc_out_done)) { -+ /* We have reached URB that isn't flaged done yet, stop traversing. */ -+ isoc_dbg("Stoped traversing Out Isoc URBs on epid:%d" -+ " before not yet flaged URB:0x%x[%d]\n", -+ epid, (unsigned int)urb, urb_priv->urb_num); -+ epid_done = 1; -+ continue; -+ } -+ -+ /* This urb has been sent. */ -+ isoc_dbg("Found URB:0x%x[%d] that is flaged isoc_out_done\n", -+ (unsigned int)urb, urb_priv->urb_num); -+ -+ /* Set ok on transfered packets for this URB and finish it */ -+ for (i = 0; i < urb->number_of_packets; i++) { -+ packet = &urb->iso_frame_desc[i]; -+ packet->status = 0; -+ packet->actual_length = packet->length; -+ } -+ urb_priv->isoc_packet_counter = urb->number_of_packets; -+ tc_finish_urb(comp_data->hcd, urb, 0); -+ -+ } /* END: while(!epid_done) */ -+ } /* END: for(epid...) */ -+ -+ local_irq_restore(flags); -+ kmem_cache_free(isoc_compl_cache, comp_data); -+} -+#endif -+ -+static void check_finished_intr_tx_epids(struct usb_hcd *hcd) { -+ unsigned long flags; -+ int epid; -+ struct urb *urb; -+ struct crisv10_urb_priv * urb_priv; -+ volatile struct USB_EP_Desc *curr_ep; /* Current EP, the iterator. */ -+ volatile struct USB_EP_Desc *next_ep; /* The EP after current. */ -+ -+ /* Protect TxintrEPList */ -+ local_irq_save(flags); -+ -+ for (epid = 0; epid < NBR_OF_EPIDS; epid++) { -+ if(!epid_inuse(epid) || !epid_intr(epid) || !epid_out_traffic(epid)) { -+ /* Nothing to see on this epid. Only check valid Out Intr epids */ -+ continue; -+ } -+ -+ urb = activeUrbList[epid]; -+ if(urb == 0) { -+ intr_warn("Found Out Intr epid:%d with no active URB\n", epid); -+ continue; -+ } -+ -+ /* Sanity check. */ -+ ASSERT(usb_pipetype(urb->pipe) == PIPE_INTERRUPT); -+ ASSERT(usb_pipeout(urb->pipe)); -+ -+ urb_priv = (struct crisv10_urb_priv *)urb->hcpriv; -+ ASSERT(urb_priv); -+ -+ /* Go through EPs between first and second sof-EP. It's here Out Intr EPs -+ are inserted.*/ -+ curr_ep = &TxIntrEPList[0]; -+ do { -+ next_ep = (struct USB_EP_Desc *)phys_to_virt(curr_ep->next); -+ if(next_ep == urb_priv->intr_ep_pool[0]) { -+ /* We found the Out Intr EP for this epid */ -+ -+ /* Disable it so it doesn't get processed again */ -+ next_ep->command &= ~IO_MASK(USB_EP_command, enable); -+ -+ /* Finish the active Out Intr URB with status OK */ -+ tc_finish_urb(hcd, urb, 0); -+ } -+ curr_ep = phys_to_virt(curr_ep->next); -+ } while (curr_ep != &TxIntrEPList[1]); -+ -+ } -+ local_irq_restore(flags); -+} -+ -+/* Interrupt handler for DMA8/IRQ24 with subchannels (called from hardware intr) */ -+static irqreturn_t tc_dma_tx_interrupt(int irq, void *vhc) { -+ struct usb_hcd *hcd = (struct usb_hcd*)vhc; -+ ASSERT(hcd); -+ -+ if (*R_IRQ_READ2 & IO_MASK(R_IRQ_READ2, dma8_sub0_descr)) { -+ /* Clear this interrupt */ -+ *R_DMA_CH8_SUB0_CLR_INTR = IO_STATE(R_DMA_CH8_SUB0_CLR_INTR, clr_descr, do); -+ restart_dma8_sub0(); -+ } -+ -+ if (*R_IRQ_READ2 & IO_MASK(R_IRQ_READ2, dma8_sub1_descr)) { -+ /* Clear this interrupt */ -+ *R_DMA_CH8_SUB1_CLR_INTR = IO_STATE(R_DMA_CH8_SUB1_CLR_INTR, clr_descr, do); -+ check_finished_ctrl_tx_epids(hcd); -+ } -+ -+ if (*R_IRQ_READ2 & IO_MASK(R_IRQ_READ2, dma8_sub2_descr)) { -+ /* Clear this interrupt */ -+ *R_DMA_CH8_SUB2_CLR_INTR = IO_STATE(R_DMA_CH8_SUB2_CLR_INTR, clr_descr, do); -+ check_finished_intr_tx_epids(hcd); -+ } -+ -+ /* hinko ignore usb_pipeisoc */ -+#if 0 -+ if (*R_IRQ_READ2 & IO_MASK(R_IRQ_READ2, dma8_sub3_descr)) { -+ struct crisv10_isoc_complete_data* comp_data; -+ -+ /* Flag done Out Isoc for later completion */ -+ check_finished_isoc_tx_epids(); -+ -+ /* Clear this interrupt */ -+ *R_DMA_CH8_SUB3_CLR_INTR = IO_STATE(R_DMA_CH8_SUB3_CLR_INTR, clr_descr, do); -+ /* Schedule bottom half of Out Isoc completion function. This function -+ finishes the URBs marked with isoc_out_done */ -+ comp_data = (struct crisv10_isoc_complete_data*) -+ kmem_cache_alloc(isoc_compl_cache, GFP_ATOMIC); -+ ASSERT(comp_data != NULL); -+ comp_data ->hcd = hcd; -+ -+ //INIT_WORK(&comp_data->usb_bh, complete_isoc_bottom_half, comp_data); -+ INIT_WORK(&comp_data->usb_bh, complete_isoc_bottom_half); -+ schedule_work(&comp_data->usb_bh); -+ } -+#endif -+ -+ return IRQ_HANDLED; -+} -+ -+/* Interrupt handler for DMA9/IRQ25 (called from hardware intr) */ -+static irqreturn_t tc_dma_rx_interrupt(int irq, void *vhc) { -+ unsigned long flags; -+ struct urb *urb; -+ struct usb_hcd *hcd = (struct usb_hcd*)vhc; -+ struct crisv10_urb_priv *urb_priv; -+ int epid = 0; -+ int real_error; -+ -+ ASSERT(hcd); -+ -+ /* Clear this interrupt. */ -+ *R_DMA_CH9_CLR_INTR = IO_STATE(R_DMA_CH9_CLR_INTR, clr_eop, do); -+ -+ /* Custom clear interrupt for this interrupt */ -+ /* The reason we cli here is that we call the driver's callback functions. */ -+ local_irq_save(flags); -+ -+ /* Note that this while loop assumes that all packets span only -+ one rx descriptor. */ -+ while(myNextRxDesc->status & IO_MASK(USB_IN_status, eop)) { -+ epid = IO_EXTRACT(USB_IN_status, epid, myNextRxDesc->status); -+ /* Get the active URB for this epid */ -+ urb = activeUrbList[epid]; -+ -+ ASSERT(epid_inuse(epid)); -+ if (!urb) { -+ dma_err("No urb for epid %d in rx interrupt\n", epid); -+ goto skip_out; -+ } -+ -+ /* Check if any errors on epid */ -+ real_error = 0; -+ if (myNextRxDesc->status & IO_MASK(USB_IN_status, error)) { -+ __u32 r_usb_ept_data; -+ -+ if (usb_pipeisoc(urb->pipe)) { -+ r_usb_ept_data = etrax_epid_iso_get(epid); -+ if((r_usb_ept_data & IO_MASK(R_USB_EPT_DATA_ISO, valid)) && -+ (IO_EXTRACT(R_USB_EPT_DATA_ISO, error_code, r_usb_ept_data) == 0) && -+ (myNextRxDesc->status & IO_MASK(USB_IN_status, nodata))) { -+ /* Not an error, just a failure to receive an expected iso -+ in packet in this frame. This is not documented -+ in the designers reference. Continue processing. -+ */ -+ } else real_error = 1; -+ } else real_error = 1; -+ } -+ -+ if(real_error) { -+ dma_err("Error in RX descr on epid:%d for URB 0x%x", -+ epid, (unsigned int)urb); -+ dump_ept_data(epid); -+ dump_in_desc(myNextRxDesc); -+ goto skip_out; -+ } -+ -+ urb_priv = (struct crisv10_urb_priv *)urb->hcpriv; -+ ASSERT(urb_priv); -+ ASSERT(urb_priv->urb_state == STARTED || -+ urb_priv->urb_state == UNLINK); -+ -+ if ((usb_pipetype(urb->pipe) == PIPE_BULK) || -+ (usb_pipetype(urb->pipe) == PIPE_CONTROL) || -+ (usb_pipetype(urb->pipe) == PIPE_INTERRUPT)) { -+ -+ /* We get nodata for empty data transactions, and the rx descriptor's -+ hw_len field is not valid in that case. No data to copy in other -+ words. */ -+ if (myNextRxDesc->status & IO_MASK(USB_IN_status, nodata)) { -+ /* No data to copy */ -+ } else { -+ /* -+ dma_dbg("Processing RX for URB:0x%x epid:%d (data:%d ofs:%d)\n", -+ (unsigned int)urb, epid, myNextRxDesc->hw_len, -+ urb_priv->rx_offset); -+ */ -+ /* Only copy data if URB isn't flaged to be unlinked*/ -+ if(urb_priv->urb_state != UNLINK) { -+ /* Make sure the data fits in the buffer. */ -+ if(urb_priv->rx_offset + myNextRxDesc->hw_len -+ <= urb->transfer_buffer_length) { -+ -+ /* Copy the data to URBs buffer */ -+ memcpy(urb->transfer_buffer + urb_priv->rx_offset, -+ phys_to_virt(myNextRxDesc->buf), myNextRxDesc->hw_len); -+ urb_priv->rx_offset += myNextRxDesc->hw_len; -+ } else { -+ /* Signal overflow when returning URB */ -+ urb->status = -EOVERFLOW; -+ tc_finish_urb_later(hcd, urb, urb->status); -+ } -+ } -+ } -+ -+ /* Check if it was the last packet in the transfer */ -+ if (myNextRxDesc->status & IO_MASK(USB_IN_status, eot)) { -+ /* Special handling for In Ctrl URBs. */ -+ if(usb_pipecontrol(urb->pipe) && usb_pipein(urb->pipe) && -+ !(urb_priv->ctrl_zout_done)) { -+ /* Flag that RX part of Ctrl transfer is done. Because zout descr -+ interrupt hasn't happend yet will the URB be finished in the -+ TX-Interrupt. */ -+ urb_priv->ctrl_rx_done = 1; -+ tc_dbg("Not finishing In Ctrl URB:0x%x from rx_interrupt, waiting" -+ " for zout\n", (unsigned int)urb); -+ } else { -+ tc_finish_urb(hcd, urb, 0); -+ } -+ } -+ } else { /* ISOC RX */ -+ /* -+ isoc_dbg("Processing RX for epid:%d (URB:0x%x) ISOC pipe\n", -+ epid, (unsigned int)urb); -+ */ -+ -+ struct usb_iso_packet_descriptor *packet; -+ -+ if (urb_priv->urb_state == UNLINK) { -+ isoc_warn("Ignoring Isoc Rx data for urb being unlinked.\n"); -+ goto skip_out; -+ } else if (urb_priv->urb_state == NOT_STARTED) { -+ isoc_err("What? Got Rx data for Isoc urb that isn't started?\n"); -+ goto skip_out; -+ } -+ -+ packet = &urb->iso_frame_desc[urb_priv->isoc_packet_counter]; -+ ASSERT(packet); -+ packet->status = 0; -+ -+ if (myNextRxDesc->status & IO_MASK(USB_IN_status, nodata)) { -+ /* We get nodata for empty data transactions, and the rx descriptor's -+ hw_len field is not valid in that case. We copy 0 bytes however to -+ stay in synch. */ -+ packet->actual_length = 0; -+ } else { -+ packet->actual_length = myNextRxDesc->hw_len; -+ /* Make sure the data fits in the buffer. */ -+ ASSERT(packet->actual_length <= packet->length); -+ memcpy(urb->transfer_buffer + packet->offset, -+ phys_to_virt(myNextRxDesc->buf), packet->actual_length); -+ if(packet->actual_length > 0) -+ isoc_dbg("Copied %d bytes, packet %d for URB:0x%x[%d]\n", -+ packet->actual_length, urb_priv->isoc_packet_counter, -+ (unsigned int)urb, urb_priv->urb_num); -+ } -+ -+ /* Increment the packet counter. */ -+ urb_priv->isoc_packet_counter++; -+ -+ /* Note that we don't care about the eot field in the rx descriptor's -+ status. It will always be set for isoc traffic. */ -+ if (urb->number_of_packets == urb_priv->isoc_packet_counter) { -+ /* Complete the urb with status OK. */ -+ tc_finish_urb(hcd, urb, 0); -+ } -+ } -+ -+ skip_out: -+ myNextRxDesc->status = 0; -+ myNextRxDesc->command |= IO_MASK(USB_IN_command, eol); -+ myLastRxDesc->command &= ~IO_MASK(USB_IN_command, eol); -+ myLastRxDesc = myNextRxDesc; -+ myNextRxDesc = phys_to_virt(myNextRxDesc->next); -+ flush_etrax_cache(); -+ *R_DMA_CH9_CMD = IO_STATE(R_DMA_CH9_CMD, cmd, restart); -+ } -+ -+ local_irq_restore(flags); -+ -+ return IRQ_HANDLED; -+} -+ -+static void tc_bulk_start_timer_func(unsigned long dummy) { -+ /* We might enable an EP descriptor behind the current DMA position when -+ it's about to decide that there are no more bulk traffic and it should -+ stop the bulk channel. -+ Therefore we periodically check if the bulk channel is stopped and there -+ is an enabled bulk EP descriptor, in which case we start the bulk -+ channel. */ -+ -+ if (!(*R_DMA_CH8_SUB0_CMD & IO_MASK(R_DMA_CH8_SUB0_CMD, cmd))) { -+ int epid; -+ -+ timer_dbg("bulk_start_timer: Bulk DMA channel not running.\n"); -+ -+ for (epid = 0; epid < NBR_OF_EPIDS; epid++) { -+ if (TxBulkEPList[epid].command & IO_MASK(USB_EP_command, enable)) { -+ timer_warn("Found enabled EP for epid %d, starting bulk channel.\n", -+ epid); -+ restart_dma8_sub0(); -+ -+ /* Restart the bulk eot timer since we just started the bulk channel.*/ -+ mod_timer(&bulk_eot_timer, jiffies + BULK_EOT_TIMER_INTERVAL); -+ -+ /* No need to search any further. */ -+ break; -+ } -+ } -+ } else { -+ timer_dbg("bulk_start_timer: Bulk DMA channel running.\n"); -+ } -+} -+ -+static void tc_bulk_eot_timer_func(unsigned long dummy) { -+ struct usb_hcd *hcd = (struct usb_hcd*)dummy; -+ ASSERT(hcd); -+ /* Because of a race condition in the top half, we might miss a bulk eot. -+ This timer "simulates" a bulk eot if we don't get one for a while, -+ hopefully correcting the situation. */ -+ timer_dbg("bulk_eot_timer timed out.\n"); -+ check_finished_bulk_tx_epids(hcd, 1); -+} -+ -+ -+/*************************************************************/ -+/*************************************************************/ -+/* Device driver block */ -+/*************************************************************/ -+/*************************************************************/ -+ -+/* Forward declarations for device driver functions */ -+static int devdrv_hcd_probe(struct device *); -+static int devdrv_hcd_remove(struct device *); -+#ifdef CONFIG_PM -+static int devdrv_hcd_suspend(struct device *, u32, u32); -+static int devdrv_hcd_resume(struct device *, u32); -+#endif /* CONFIG_PM */ -+ -+/* the device */ -+static struct platform_device *devdrv_hc_platform_device; -+ -+/* device driver interface */ -+static struct device_driver devdrv_hc_device_driver = { -+ .name = (char *) hc_name, -+ .bus = &platform_bus_type, -+ -+ .probe = devdrv_hcd_probe, -+ .remove = devdrv_hcd_remove, -+ -+#ifdef CONFIG_PM -+ .suspend = devdrv_hcd_suspend, -+ .resume = devdrv_hcd_resume, -+#endif /* CONFIG_PM */ -+}; -+ -+/* initialize the host controller and driver */ -+static int __init_or_module devdrv_hcd_probe(struct device *dev) -+{ -+ struct usb_hcd *hcd; -+ struct crisv10_hcd *crisv10_hcd; -+ int retval; -+ int rev_maj, rev_min; -+ -+ /* Check DMA burst length */ -+ if(IO_EXTRACT(R_BUS_CONFIG, dma_burst, *R_BUS_CONFIG) != -+ IO_STATE(R_BUS_CONFIG, dma_burst, burst32)) { -+ devdrv_err("Invalid DMA burst length in Etrax 100LX," -+ " needs to be 32\n"); -+ return -EPERM; -+ } -+ -+ hcd = usb_create_hcd(&crisv10_hc_driver, dev, dev_name(dev)); -+ if (!hcd) -+ return -ENOMEM; -+ -+ crisv10_hcd = hcd_to_crisv10_hcd(hcd); -+ spin_lock_init(&crisv10_hcd->lock); -+ crisv10_hcd->num_ports = num_ports(); -+ crisv10_hcd->running = 0; -+ -+ dev_set_drvdata(dev, crisv10_hcd); -+ -+ devdrv_dbg("ETRAX USB IRQs HC:%d RX:%d TX:%d\n", ETRAX_USB_HC_IRQ, -+ ETRAX_USB_RX_IRQ, ETRAX_USB_TX_IRQ); -+ -+ /* Print out chip version read from registers */ -+ rev_maj = *R_USB_REVISION & IO_MASK(R_USB_REVISION, major); -+ rev_min = *R_USB_REVISION & IO_MASK(R_USB_REVISION, minor); -+ if(rev_min == 0) { -+ devdrv_info("Etrax 100LX USB Revision %d v1,2\n", rev_maj); -+ } else { -+ devdrv_info("Etrax 100LX USB Revision %d v%d\n", rev_maj, rev_min); -+ } -+ -+ devdrv_info("Bulk timer interval, start:%d eot:%d\n", -+ BULK_START_TIMER_INTERVAL, -+ BULK_EOT_TIMER_INTERVAL); -+ -+ -+ /* Init root hub data structures */ -+ if(rh_init()) { -+ devdrv_err("Failed init data for Root Hub\n"); -+ retval = -ENOMEM; -+ } -+ -+ if(port_in_use(0)) { -+ if (cris_request_io_interface(if_usb_1, "ETRAX100LX USB-HCD")) { -+ printk(KERN_CRIT "usb-host: request IO interface usb1 failed"); -+ retval = -EBUSY; -+ goto out; -+ } -+ devdrv_info("Claimed interface for USB physical port 1\n"); -+ } -+ if(port_in_use(1)) { -+ if (cris_request_io_interface(if_usb_2, "ETRAX100LX USB-HCD")) { -+ /* Free first interface if second failed to be claimed */ -+ if(port_in_use(0)) { -+ cris_free_io_interface(if_usb_1); -+ } -+ printk(KERN_CRIT "usb-host: request IO interface usb2 failed"); -+ retval = -EBUSY; -+ goto out; -+ } -+ devdrv_info("Claimed interface for USB physical port 2\n"); -+ } -+ -+ /* Init transfer controller structs and locks */ -+ if((retval = tc_init(hcd)) != 0) { -+ goto out; -+ } -+ -+ /* Attach interrupt functions for DMA and init DMA controller */ -+ if((retval = tc_dma_init(hcd)) != 0) { -+ goto out; -+ } -+ -+ /* Attach the top IRQ handler for USB controller interrupts */ -+ if (request_irq(ETRAX_USB_HC_IRQ, crisv10_hcd_top_irq, 0, -+ "ETRAX 100LX built-in USB (HC)", hcd)) { -+ err("Could not allocate IRQ %d for USB", ETRAX_USB_HC_IRQ); -+ retval = -EBUSY; -+ goto out; -+ } -+ -+ /* iso_eof is only enabled when isoc traffic is running. */ -+ *R_USB_IRQ_MASK_SET = -+ /* IO_STATE(R_USB_IRQ_MASK_SET, iso_eof, set) | */ -+ IO_STATE(R_USB_IRQ_MASK_SET, bulk_eot, set) | -+ IO_STATE(R_USB_IRQ_MASK_SET, epid_attn, set) | -+ IO_STATE(R_USB_IRQ_MASK_SET, port_status, set) | -+ IO_STATE(R_USB_IRQ_MASK_SET, ctl_status, set); -+ -+ -+ crisv10_ready_wait(); -+ /* Reset the USB interface. */ -+ *R_USB_COMMAND = -+ IO_STATE(R_USB_COMMAND, port_sel, nop) | -+ IO_STATE(R_USB_COMMAND, port_cmd, reset) | -+ IO_STATE(R_USB_COMMAND, ctrl_cmd, reset); -+ -+ /* Designer's Reference, p. 8 - 10 says we should Initate R_USB_FM_PSTART to -+ 0x2A30 (10800), to guarantee that control traffic gets 10% of the -+ bandwidth, and periodic transfer may allocate the rest (90%). -+ This doesn't work though. -+ The value 11960 is chosen to be just after the SOF token, with a couple -+ of bit times extra for possible bit stuffing. */ -+ *R_USB_FM_PSTART = IO_FIELD(R_USB_FM_PSTART, value, 11960); -+ -+ crisv10_ready_wait(); -+ /* Configure the USB interface as a host controller. */ -+ *R_USB_COMMAND = -+ IO_STATE(R_USB_COMMAND, port_sel, nop) | -+ IO_STATE(R_USB_COMMAND, port_cmd, reset) | -+ IO_STATE(R_USB_COMMAND, ctrl_cmd, host_config); -+ -+ -+ /* Check so controller not busy before enabling ports */ -+ crisv10_ready_wait(); -+ -+ /* Enable selected USB ports */ -+ if(port_in_use(0)) { -+ *R_USB_PORT1_DISABLE = IO_STATE(R_USB_PORT1_DISABLE, disable, no); -+ } else { -+ *R_USB_PORT1_DISABLE = IO_STATE(R_USB_PORT1_DISABLE, disable, yes); -+ } -+ if(port_in_use(1)) { -+ *R_USB_PORT2_DISABLE = IO_STATE(R_USB_PORT2_DISABLE, disable, no); -+ } else { -+ *R_USB_PORT2_DISABLE = IO_STATE(R_USB_PORT2_DISABLE, disable, yes); -+ } -+ -+ crisv10_ready_wait(); -+ /* Start processing of USB traffic. */ -+ *R_USB_COMMAND = -+ IO_STATE(R_USB_COMMAND, port_sel, nop) | -+ IO_STATE(R_USB_COMMAND, port_cmd, reset) | -+ IO_STATE(R_USB_COMMAND, ctrl_cmd, host_run); -+ -+ /* Do not continue probing initialization before USB interface is done */ -+ crisv10_ready_wait(); -+ -+ /* Register our Host Controller to USB Core -+ * Finish the remaining parts of generic HCD initialization: allocate the -+ * buffers of consistent memory, register the bus -+ * and call the driver's reset() and start() routines. */ -+ retval = usb_add_hcd(hcd, ETRAX_USB_HC_IRQ, IRQF_DISABLED); -+ if (retval != 0) { -+ devdrv_err("Failed registering HCD driver\n"); -+ goto out; -+ } -+ -+ return 0; -+ -+ out: -+ devdrv_hcd_remove(dev); -+ return retval; -+} -+ -+ -+/* cleanup after the host controller and driver */ -+static int __init_or_module devdrv_hcd_remove(struct device *dev) -+{ -+ struct crisv10_hcd *crisv10_hcd = dev_get_drvdata(dev); -+ struct usb_hcd *hcd; -+ -+ if (!crisv10_hcd) -+ return 0; -+ hcd = crisv10_hcd_to_hcd(crisv10_hcd); -+ -+ -+ /* Stop USB Controller in Etrax 100LX */ -+ crisv10_hcd_reset(hcd); -+ -+ usb_remove_hcd(hcd); -+ devdrv_dbg("Removed HCD from USB Core\n"); -+ -+ /* Free USB Controller IRQ */ -+ free_irq(ETRAX_USB_HC_IRQ, NULL); -+ -+ /* Free resources */ -+ tc_dma_destroy(); -+ tc_destroy(); -+ -+ -+ if(port_in_use(0)) { -+ cris_free_io_interface(if_usb_1); -+ } -+ if(port_in_use(1)) { -+ cris_free_io_interface(if_usb_2); -+ } -+ -+ devdrv_dbg("Freed all claimed resources\n"); -+ -+ return 0; -+} -+ -+ -+#ifdef CONFIG_PM -+ -+static int devdrv_hcd_suspend(struct usb_hcd *hcd, u32 state, u32 level) -+{ -+ return 0; /* no-op for now */ -+} -+ -+static int devdrv_hcd_resume(struct usb_hcd *hcd, u32 level) -+{ -+ return 0; /* no-op for now */ -+} -+ -+#endif /* CONFIG_PM */ -+ -+ -+ -+/*************************************************************/ -+/*************************************************************/ -+/* Module block */ -+/*************************************************************/ -+/*************************************************************/ -+ -+/* register driver */ -+static int __init module_hcd_init(void) -+{ -+ -+ if (usb_disabled()) -+ return -ENODEV; -+ -+ /* Here we select enabled ports by following defines created from -+ menuconfig */ -+#ifndef CONFIG_ETRAX_USB_HOST_PORT1 -+ ports &= ~(1<<0); -+#endif -+#ifndef CONFIG_ETRAX_USB_HOST_PORT2 -+ ports &= ~(1<<1); -+#endif -+ -+ printk(KERN_INFO "%s version "VERSION" "COPYRIGHT"\n", product_desc); -+ -+ devdrv_hc_platform_device = -+ platform_device_register_simple((char *) hc_name, 0, NULL, 0); -+ -+ if (IS_ERR(devdrv_hc_platform_device)) -+ return PTR_ERR(devdrv_hc_platform_device); -+ return driver_register(&devdrv_hc_device_driver); -+ /* -+ * Note that we do not set the DMA mask for the device, -+ * i.e. we pretend that we will use PIO, since no specific -+ * allocation routines are needed for DMA buffers. This will -+ * cause the HCD buffer allocation routines to fall back to -+ * kmalloc(). -+ */ -+} -+ -+/* unregister driver */ -+static void __exit module_hcd_exit(void) -+{ -+ driver_unregister(&devdrv_hc_device_driver); -+} -+ -+ -+/* Module hooks */ -+module_init(module_hcd_init); -+module_exit(module_hcd_exit); -diff -Nur linux-2.6.36.orig/drivers/usb/host/hc-crisv10.h linux-2.6.36/drivers/usb/host/hc-crisv10.h ---- linux-2.6.36.orig/drivers/usb/host/hc-crisv10.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/drivers/usb/host/hc-crisv10.h 2010-12-28 20:35:00.000000000 +0100 -@@ -0,0 +1,331 @@ -+#ifndef __LINUX_ETRAX_USB_H -+#define __LINUX_ETRAX_USB_H -+ -+#include -+#include -+ -+struct USB_IN_Desc { -+ volatile __u16 sw_len; -+ volatile __u16 command; -+ volatile unsigned long next; -+ volatile unsigned long buf; -+ volatile __u16 hw_len; -+ volatile __u16 status; -+}; -+ -+struct USB_SB_Desc { -+ volatile __u16 sw_len; -+ volatile __u16 command; -+ volatile unsigned long next; -+ volatile unsigned long buf; -+}; -+ -+struct USB_EP_Desc { -+ volatile __u16 hw_len; -+ volatile __u16 command; -+ volatile unsigned long sub; -+ volatile unsigned long next; -+}; -+ -+ -+/* Root Hub port status struct */ -+struct crisv10_rh { -+ volatile __u16 wPortChange[2]; -+ volatile __u16 wPortStatusPrev[2]; -+}; -+ -+/* HCD description */ -+struct crisv10_hcd { -+ spinlock_t lock; -+ __u8 num_ports; -+ __u8 running; -+}; -+ -+ -+/* Endpoint HC private data description */ -+struct crisv10_ep_priv { -+ int epid; -+}; -+ -+/* Additional software state info for a USB Controller epid */ -+struct etrax_epid { -+ __u8 inuse; /* !0 = setup in Etrax and used for a endpoint */ -+ __u8 disabled; /* !0 = Temporarly disabled to avoid resubmission */ -+ __u8 type; /* Setup as: PIPE_BULK, PIPE_CONTROL ... */ -+ __u8 out_traffic; /* !0 = This epid is for out traffic */ -+}; -+ -+/* Struct to hold information of scheduled later URB completion */ -+struct urb_later_data { -+// struct work_struct ws; -+ struct delayed_work ws; -+ struct usb_hcd *hcd; -+ struct urb *urb; -+ int urb_num; -+ int status; -+}; -+ -+ -+typedef enum { -+ STARTED, -+ NOT_STARTED, -+ UNLINK, -+} crisv10_urb_state_t; -+ -+ -+struct crisv10_urb_priv { -+ /* Sequence number for this URB. Every new submited URB gets this from -+ a incrementing counter. Used when a URB is scheduled for later finish to -+ be sure that the intended URB hasn't already been completed (device -+ drivers has a tendency to reuse URBs once they are completed, causing us -+ to not be able to single old ones out only based on the URB pointer.) */ -+ __u32 urb_num; -+ -+ /* The first_sb field is used for freeing all SB descriptors belonging -+ to an urb. The corresponding ep descriptor's sub pointer cannot be -+ used for this since the DMA advances the sub pointer as it processes -+ the sb list. */ -+ struct USB_SB_Desc *first_sb; -+ -+ /* The last_sb field referes to the last SB descriptor that belongs to -+ this urb. This is important to know so we can free the SB descriptors -+ that ranges between first_sb and last_sb. */ -+ struct USB_SB_Desc *last_sb; -+ -+ /* The rx_offset field is used in ctrl and bulk traffic to keep track -+ of the offset in the urb's transfer_buffer where incoming data should be -+ copied to. */ -+ __u32 rx_offset; -+ -+ /* Counter used in isochronous transfers to keep track of the -+ number of packets received/transmitted. */ -+ __u32 isoc_packet_counter; -+ -+ /* Flag that marks if this Isoc Out URB has finished it's transfer. Used -+ because several URBs can be finished before list is processed */ -+ __u8 isoc_out_done; -+ -+ /* This field is used to pass information about the urb's current state -+ between the various interrupt handlers (thus marked volatile). */ -+ volatile crisv10_urb_state_t urb_state; -+ -+ /* In Ctrl transfers consist of (at least) 3 packets: SETUP, IN and ZOUT. -+ When DMA8 sub-channel 2 has processed the SB list for this sequence we -+ get a interrupt. We also get a interrupt for In transfers and which -+ one of these interrupts that comes first depends of data size and device. -+ To be sure that we have got both interrupts before we complete the URB -+ we have these to flags that shows which part that has completed. -+ We can then check when we get one of the interrupts that if the other has -+ occured it's safe for us to complete the URB, otherwise we set appropriate -+ flag and do the completion when we get the other interrupt. */ -+ volatile unsigned char ctrl_zout_done; -+ volatile unsigned char ctrl_rx_done; -+ -+ /* Connection between the submitted urb and ETRAX epid number */ -+ __u8 epid; -+ -+ /* The rx_data_list field is used for periodic traffic, to hold -+ received data for later processing in the the complete_urb functions, -+ where the data us copied to the urb's transfer_buffer. Basically, we -+ use this intermediate storage because we don't know when it's safe to -+ reuse the transfer_buffer (FIXME?). */ -+ struct list_head rx_data_list; -+ -+ -+ /* The interval time rounded up to closest 2^N */ -+ int interval; -+ -+ /* Pool of EP descriptors needed if it's a INTR transfer. -+ Amount of EPs in pool correspons to how many INTR that should -+ be inserted in TxIntrEPList (max 128, defined by MAX_INTR_INTERVAL) */ -+ struct USB_EP_Desc* intr_ep_pool[128]; -+ -+ /* The mount of EPs allocated for this INTR URB */ -+ int intr_ep_pool_length; -+ -+ /* Pointer to info struct if URB is scheduled to be finished later */ -+ struct urb_later_data* later_data; -+}; -+ -+ -+/* This struct is for passing data from the top half to the bottom half irq -+ handlers */ -+struct crisv10_irq_reg { -+ struct usb_hcd* hcd; -+ __u32 r_usb_epid_attn; -+ __u8 r_usb_status; -+ __u16 r_usb_rh_port_status_1; -+ __u16 r_usb_rh_port_status_2; -+ __u32 r_usb_irq_mask_read; -+ __u32 r_usb_fm_number; -+ struct work_struct usb_bh; -+}; -+ -+ -+/* This struct is for passing data from the isoc top half to the isoc bottom -+ half. */ -+struct crisv10_isoc_complete_data { -+ struct usb_hcd *hcd; -+ struct urb *urb; -+ struct work_struct usb_bh; -+}; -+ -+/* Entry item for URB lists for each endpint */ -+typedef struct urb_entry -+{ -+ struct urb *urb; -+ struct list_head list; -+} urb_entry_t; -+ -+/* --------------------------------------------------------------------------- -+ Virtual Root HUB -+ ------------------------------------------------------------------------- */ -+/* destination of request */ -+#define RH_INTERFACE 0x01 -+#define RH_ENDPOINT 0x02 -+#define RH_OTHER 0x03 -+ -+#define RH_CLASS 0x20 -+#define RH_VENDOR 0x40 -+ -+/* Requests: bRequest << 8 | bmRequestType */ -+#define RH_GET_STATUS 0x0080 -+#define RH_CLEAR_FEATURE 0x0100 -+#define RH_SET_FEATURE 0x0300 -+#define RH_SET_ADDRESS 0x0500 -+#define RH_GET_DESCRIPTOR 0x0680 -+#define RH_SET_DESCRIPTOR 0x0700 -+#define RH_GET_CONFIGURATION 0x0880 -+#define RH_SET_CONFIGURATION 0x0900 -+#define RH_GET_STATE 0x0280 -+#define RH_GET_INTERFACE 0x0A80 -+#define RH_SET_INTERFACE 0x0B00 -+#define RH_SYNC_FRAME 0x0C80 -+/* Our Vendor Specific Request */ -+#define RH_SET_EP 0x2000 -+ -+ -+/* Hub port features */ -+#define RH_PORT_CONNECTION 0x00 -+#define RH_PORT_ENABLE 0x01 -+#define RH_PORT_SUSPEND 0x02 -+#define RH_PORT_OVER_CURRENT 0x03 -+#define RH_PORT_RESET 0x04 -+#define RH_PORT_POWER 0x08 -+#define RH_PORT_LOW_SPEED 0x09 -+#define RH_C_PORT_CONNECTION 0x10 -+#define RH_C_PORT_ENABLE 0x11 -+#define RH_C_PORT_SUSPEND 0x12 -+#define RH_C_PORT_OVER_CURRENT 0x13 -+#define RH_C_PORT_RESET 0x14 -+ -+/* Hub features */ -+#define RH_C_HUB_LOCAL_POWER 0x00 -+#define RH_C_HUB_OVER_CURRENT 0x01 -+ -+#define RH_DEVICE_REMOTE_WAKEUP 0x00 -+#define RH_ENDPOINT_STALL 0x01 -+ -+/* Our Vendor Specific feature */ -+#define RH_REMOVE_EP 0x00 -+ -+ -+#define RH_ACK 0x01 -+#define RH_REQ_ERR -1 -+#define RH_NACK 0x00 -+ -+/* Field definitions for */ -+ -+#define USB_IN_command__eol__BITNR 0 /* command macros */ -+#define USB_IN_command__eol__WIDTH 1 -+#define USB_IN_command__eol__no 0 -+#define USB_IN_command__eol__yes 1 -+ -+#define USB_IN_command__intr__BITNR 3 -+#define USB_IN_command__intr__WIDTH 1 -+#define USB_IN_command__intr__no 0 -+#define USB_IN_command__intr__yes 1 -+ -+#define USB_IN_status__eop__BITNR 1 /* status macros. */ -+#define USB_IN_status__eop__WIDTH 1 -+#define USB_IN_status__eop__no 0 -+#define USB_IN_status__eop__yes 1 -+ -+#define USB_IN_status__eot__BITNR 5 -+#define USB_IN_status__eot__WIDTH 1 -+#define USB_IN_status__eot__no 0 -+#define USB_IN_status__eot__yes 1 -+ -+#define USB_IN_status__error__BITNR 6 -+#define USB_IN_status__error__WIDTH 1 -+#define USB_IN_status__error__no 0 -+#define USB_IN_status__error__yes 1 -+ -+#define USB_IN_status__nodata__BITNR 7 -+#define USB_IN_status__nodata__WIDTH 1 -+#define USB_IN_status__nodata__no 0 -+#define USB_IN_status__nodata__yes 1 -+ -+#define USB_IN_status__epid__BITNR 8 -+#define USB_IN_status__epid__WIDTH 5 -+ -+#define USB_EP_command__eol__BITNR 0 -+#define USB_EP_command__eol__WIDTH 1 -+#define USB_EP_command__eol__no 0 -+#define USB_EP_command__eol__yes 1 -+ -+#define USB_EP_command__eof__BITNR 1 -+#define USB_EP_command__eof__WIDTH 1 -+#define USB_EP_command__eof__no 0 -+#define USB_EP_command__eof__yes 1 -+ -+#define USB_EP_command__intr__BITNR 3 -+#define USB_EP_command__intr__WIDTH 1 -+#define USB_EP_command__intr__no 0 -+#define USB_EP_command__intr__yes 1 -+ -+#define USB_EP_command__enable__BITNR 4 -+#define USB_EP_command__enable__WIDTH 1 -+#define USB_EP_command__enable__no 0 -+#define USB_EP_command__enable__yes 1 -+ -+#define USB_EP_command__hw_valid__BITNR 5 -+#define USB_EP_command__hw_valid__WIDTH 1 -+#define USB_EP_command__hw_valid__no 0 -+#define USB_EP_command__hw_valid__yes 1 -+ -+#define USB_EP_command__epid__BITNR 8 -+#define USB_EP_command__epid__WIDTH 5 -+ -+#define USB_SB_command__eol__BITNR 0 /* command macros. */ -+#define USB_SB_command__eol__WIDTH 1 -+#define USB_SB_command__eol__no 0 -+#define USB_SB_command__eol__yes 1 -+ -+#define USB_SB_command__eot__BITNR 1 -+#define USB_SB_command__eot__WIDTH 1 -+#define USB_SB_command__eot__no 0 -+#define USB_SB_command__eot__yes 1 -+ -+#define USB_SB_command__intr__BITNR 3 -+#define USB_SB_command__intr__WIDTH 1 -+#define USB_SB_command__intr__no 0 -+#define USB_SB_command__intr__yes 1 -+ -+#define USB_SB_command__tt__BITNR 4 -+#define USB_SB_command__tt__WIDTH 2 -+#define USB_SB_command__tt__zout 0 -+#define USB_SB_command__tt__in 1 -+#define USB_SB_command__tt__out 2 -+#define USB_SB_command__tt__setup 3 -+ -+ -+#define USB_SB_command__rem__BITNR 8 -+#define USB_SB_command__rem__WIDTH 6 -+ -+#define USB_SB_command__full__BITNR 6 -+#define USB_SB_command__full__WIDTH 1 -+#define USB_SB_command__full__no 0 -+#define USB_SB_command__full__yes 1 -+ -+#endif -diff -Nur linux-2.6.36.orig/lib/klist.c linux-2.6.36/lib/klist.c ---- linux-2.6.36.orig/lib/klist.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/lib/klist.c 2010-12-28 20:35:00.000000000 +0100 -@@ -60,7 +60,7 @@ - { - knode->n_klist = klist; - /* no knode deserves to start its life dead */ -- WARN_ON(knode_dead(knode)); -+ //WARN_ON(knode_dead(knode)); - } - - static void knode_kill(struct klist_node *knode) diff --git a/target/linux/patches/2.6.36/cygwin-compat.patch b/target/linux/patches/2.6.36/cygwin-compat.patch deleted file mode 100644 index 17258e565..000000000 --- a/target/linux/patches/2.6.36/cygwin-compat.patch +++ /dev/null @@ -1,14 +0,0 @@ -diff -Nur linux-2.6.30.orig/scripts/mod/file2alias.c linux-2.6.30/scripts/mod/file2alias.c ---- linux-2.6.30.orig/scripts/mod/file2alias.c 2009-06-10 05:05:27.000000000 +0200 -+++ linux-2.6.30/scripts/mod/file2alias.c 2009-06-11 09:17:10.000000000 +0200 -@@ -29,7 +29,11 @@ - - #include - -+#ifdef __CYGWIN__ -+typedef __uint32_t __u32; -+#else - typedef uint32_t __u32; -+#endif - typedef uint16_t __u16; - typedef unsigned char __u8; diff --git a/target/linux/patches/2.6.36/drm-kconfig.patch b/target/linux/patches/2.6.36/drm-kconfig.patch deleted file mode 100644 index aad193c97..000000000 --- a/target/linux/patches/2.6.36/drm-kconfig.patch +++ /dev/null @@ -1,34 +0,0 @@ -diff -Nur linux-2.6.36.orig/drivers/gpu/drm/Kconfig linux-2.6.36/drivers/gpu/drm/Kconfig ---- linux-2.6.36.orig/drivers/gpu/drm/Kconfig 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/drivers/gpu/drm/Kconfig 2010-11-24 23:08:39.707247343 +0100 -@@ -79,21 +79,6 @@ - selected, the module will be called i810. AGP support is required - for this driver to work. - --choice -- prompt "Intel 830M, 845G, 852GM, 855GM, 865G" -- depends on DRM && AGP && AGP_INTEL -- optional -- --config DRM_I830 -- tristate "i830 driver" -- help -- Choose this option if you have a system that has Intel 830M, 845G, -- 852GM, 855GM or 865G integrated graphics. If M is selected, the -- module will be called i830. AGP support is required for this driver -- to work. This driver is used by the older X releases X.org 6.7 and -- XFree86 4.3. If unsure, build this and i915 as modules and the X server -- will load the correct one. -- - config DRM_I915 - tristate "i915 driver" - depends on AGP_INTEL -@@ -127,8 +112,6 @@ - the driver to bind to PCI devices, which precludes loading things - like intelfb. - --endchoice -- - config DRM_MGA - tristate "Matrox g200/g400" - depends on DRM && PCI diff --git a/target/linux/patches/2.6.36/exmap.patch b/target/linux/patches/2.6.36/exmap.patch deleted file mode 100644 index 012e4794e..000000000 --- a/target/linux/patches/2.6.36/exmap.patch +++ /dev/null @@ -1,11 +0,0 @@ -diff -Nur linux-2.6.32.orig/kernel/pid.c linux-2.6.32/kernel/pid.c ---- linux-2.6.32.orig/kernel/pid.c 2009-12-03 04:51:21.000000000 +0100 -+++ linux-2.6.32/kernel/pid.c 2009-12-06 01:04:41.000000000 +0100 -@@ -387,6 +387,7 @@ - { - return find_task_by_pid_ns(vnr, current->nsproxy->pid_ns); - } -+EXPORT_SYMBOL(find_task_by_vpid); - - struct pid *get_task_pid(struct task_struct *task, enum pid_type type) - { diff --git a/target/linux/patches/2.6.36/foxg20.patch b/target/linux/patches/2.6.36/foxg20.patch deleted file mode 100644 index 9a7d7afa0..000000000 --- a/target/linux/patches/2.6.36/foxg20.patch +++ /dev/null @@ -1,522 +0,0 @@ -diff -Nur linux-2.6.36.orig/arch/arm/Kconfig linux-2.6.36/arch/arm/Kconfig ---- linux-2.6.36.orig/arch/arm/Kconfig 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/arch/arm/Kconfig 2010-12-25 17:49:20.000000000 +0100 -@@ -21,6 +21,8 @@ - select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) - select HAVE_GENERIC_DMA_COHERENT - select HAVE_KERNEL_GZIP -+ select HAVE_KERNEL_BZIP2 -+ select HAVE_KERNEL_LZMA - select HAVE_KERNEL_LZO - select HAVE_KERNEL_LZMA - select HAVE_PERF_EVENTS -diff -Nur linux-2.6.36.orig/arch/arm/include/asm/setup.h linux-2.6.36/arch/arm/include/asm/setup.h ---- linux-2.6.36.orig/arch/arm/include/asm/setup.h 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/arch/arm/include/asm/setup.h 2010-12-25 17:49:20.000000000 +0100 -@@ -18,6 +18,8 @@ - - #define COMMAND_LINE_SIZE 1024 - -+const char *get_system_type(void); -+ - /* The list ends with an ATAG_NONE node. */ - #define ATAG_NONE 0x00000000 - -diff -Nur linux-2.6.36.orig/arch/arm/kernel/setup.c linux-2.6.36/arch/arm/kernel/setup.c ---- linux-2.6.36.orig/arch/arm/kernel/setup.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/arch/arm/kernel/setup.c 2010-12-25 17:49:20.000000000 +0100 -@@ -899,8 +899,12 @@ - - static int c_show(struct seq_file *m, void *v) - { -+ unsigned long n = (unsigned long) v - 1; - int i; - -+ if (n == 0) -+ seq_printf(m, "system type\t\t: %s\n", get_system_type()); -+ - seq_printf(m, "Processor\t: %s rev %d (%s)\n", - cpu_name, read_cpuid_id() & 15, elf_platform); - -diff -Nur linux-2.6.36.orig/arch/arm/mach-at91/Kconfig linux-2.6.36/arch/arm/mach-at91/Kconfig ---- linux-2.6.36.orig/arch/arm/mach-at91/Kconfig 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/arch/arm/mach-at91/Kconfig 2010-12-25 17:49:20.000000000 +0100 -@@ -364,6 +364,15 @@ - evaluation board. - - -+config MACH_FOXG20 -+ bool "Acme Systems FOX G20" -+ select HAVE_AT91_DATAFLASH_CARD -+ select HAVE_NAND_ATMEL_BUSWIDTH_16 -+ depends on ARCH_AT91SAM9G20 -+ help -+ Select this if you are using Acme Systems -+ FOX Board G20 -+ - endif - - if (ARCH_AT91SAM9260 || ARCH_AT91SAM9G20) -diff -Nur linux-2.6.36.orig/arch/arm/mach-at91/Makefile linux-2.6.36/arch/arm/mach-at91/Makefile ---- linux-2.6.36.orig/arch/arm/mach-at91/Makefile 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/arch/arm/mach-at91/Makefile 2010-12-25 17:49:20.000000000 +0100 -@@ -72,6 +72,9 @@ - # AT91SAM9G45 board-specific support - obj-$(CONFIG_MACH_AT91SAM9G45EKES) += board-sam9m10g45ek.o - -+# FOXG20 board-specific support -+obj-$(CONFIG_MACH_FOXG20) += board-foxg20.o -+ - # AT91CAP9 board-specific support - obj-$(CONFIG_MACH_AT91CAP9ADK) += board-cap9adk.o - -diff -Nur linux-2.6.36.orig/arch/arm/mach-at91/at91sam9260_devices.c linux-2.6.36/arch/arm/mach-at91/at91sam9260_devices.c ---- linux-2.6.36.orig/arch/arm/mach-at91/at91sam9260_devices.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/arch/arm/mach-at91/at91sam9260_devices.c 2010-12-25 17:49:20.000000000 +0100 -@@ -454,7 +454,15 @@ - .sda_is_open_drain = 1, - .scl_pin = AT91_PIN_PA24, - .scl_is_open_drain = 1, -+#if defined(CONFIG_MACH_FOXG20) -+ /* Some I2C devices are limited to 100 kHz and i2c-gpio.h -+ * says "frequency is (500 / udelay) kHz" so 5 is best (and is -+ * used in i2c-gpio.c) -+ */ -+ .udelay = 5, /* ~100 kHz */ -+#else - .udelay = 2, /* ~100 kHz */ -+#endif - }; - - static struct platform_device at91sam9260_twi_device = { -diff -Nur linux-2.6.36.orig/arch/arm/mach-at91/board-foxg20.c linux-2.6.36/arch/arm/mach-at91/board-foxg20.c ---- linux-2.6.36.orig/arch/arm/mach-at91/board-foxg20.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/arm/mach-at91/board-foxg20.c 2010-12-25 17:49:20.000000000 +0100 -@@ -0,0 +1,376 @@ -+/* -+ * Copyright (C) 2005 SAN People -+ * Copyright (C) 2008 Atmel -+ * Copyright (C) 2010 Lee McLoughlin - lee@lmmrtech.com -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+#include "sam9_smc.h" -+#include "generic.h" -+ -+/* -+ * The FOX hardware comes as the "Netus" board with just the cpu, ram, -+ * dataflash and two header connectors. This is plugged into the Fox board -+ * which provides the ethernet, usb, rtc, leds, switch, ... -+ * Other version of the Fox board are planned which could contain -+ * both NAND and sound (WM8731). -+ * -+ * By default USART4 and USART5 are not enabled (freeing up those pins -+ * for general use) -+ * -+ * Note: Enabling the NAND without a NAND device present doesn't cause -+ * any issues as on boot the probe will fail. -+ */ -+/* #define FOXG20_NAND */ -+/* #define FOXG20_WM8731 */ -+/* #define FOX_USART4 */ -+/* #define FOX_USART5 */ -+ -+const char *get_system_type(void) -+{ -+ return "FoxBoard FOXG20"; -+} -+ -+static void __init foxg20_map_io(void) -+{ -+ /* Initialize processor: 18.432 MHz crystal */ -+ at91sam9260_initialize(18432000); -+ -+ /* DBGU on ttyS0. (Rx & Tx only) */ -+ at91_register_uart(0, 0, 0); -+ -+ /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ -+ at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS -+ | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD -+ | ATMEL_UART_RI); -+ -+ /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ -+ at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); -+ -+ /* USART2 on ttyS3. (Rx & Tx only) */ -+ at91_register_uart(AT91SAM9260_ID_US2, 3, 0); -+ -+ /* USART3 on ttyS4. (Rx, Tx, RTS, CTS) */ -+ at91_register_uart(AT91SAM9260_ID_US3, 4, ATMEL_UART_CTS | ATMEL_UART_RTS); -+ -+#if defined(FOX_USART4) -+ /* USART4 on ttyS5. (Rx & Tx only) */ -+ at91_register_uart(AT91SAM9260_ID_US4, 5, 0); -+#endif -+ -+#if defined(FOX_USART5) -+ /* USART5 on ttyS6. (Rx & Tx only) */ -+ at91_register_uart(AT91SAM9260_ID_US5, 6, 0); -+#endif -+ -+ /* set serial console to ttyS0 (ie, DBGU) */ -+ at91_set_serial_console(0); -+} -+ -+static void __init foxg20_init_irq(void) -+{ -+ at91sam9260_init_interrupts(NULL); -+} -+ -+ -+/* -+ * USB Host port -+ */ -+static struct at91_usbh_data __initdata foxg20_usbh_data = { -+ .ports = 2, -+}; -+ -+/* -+ * USB Device port -+ */ -+static struct at91_udc_data __initdata foxg20_udc_data = { -+ .vbus_pin = AT91_PIN_PC6, -+ .pullup_pin = 0, /* pull-up driven by UDC */ -+}; -+ -+ -+/* -+ * SPI devices. -+ */ -+static struct spi_board_info foxg20_spi_devices[] = { -+#if !defined(CONFIG_MMC_AT91) -+ { -+ .modalias = "mtd_dataflash", -+ .chip_select = 1, -+ .max_speed_hz = 15 * 1000 * 1000, -+ .bus_num = 0, -+ }, -+#endif -+}; -+ -+ -+/* -+ * MACB Ethernet device -+ */ -+static struct at91_eth_data __initdata foxg20_macb_data = { -+ .phy_irq_pin = AT91_PIN_PA7, -+ .is_rmii = 1, -+}; -+ -+ -+#ifdef FOXG20_NAND -+/* The Fox doesn't have NAND memory */ -+/* -+ * NAND flash -+ */ -+static struct mtd_partition __initdata foxg20_nand_partition[] = { -+ { -+ .name = "Bootstrap", -+ .offset = 0, -+ .size = 4 * SZ_1M, -+ }, -+ { -+ .name = "Partition 1", -+ .offset = MTDPART_OFS_NXTBLK, -+ .size = 60 * SZ_1M, -+ }, -+ { -+ .name = "Partition 2", -+ .offset = MTDPART_OFS_NXTBLK, -+ .size = MTDPART_SIZ_FULL, -+ }, -+}; -+ -+static struct mtd_partition * __init nand_partitions(int size, int *num_partitions) -+{ -+ *num_partitions = ARRAY_SIZE(foxg20_nand_partition); -+ return foxg20_nand_partition; -+} -+ -+/* det_pin is not connected */ -+static struct atmel_nand_data __initdata foxg20_nand_data = { -+ .ale = 21, -+ .cle = 22, -+ .rdy_pin = AT91_PIN_PC13, -+ .enable_pin = AT91_PIN_PC14, -+ .partition_info = nand_partitions, -+#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16) -+ .bus_width_16 = 1, -+#else -+ .bus_width_16 = 0, -+#endif -+}; -+ -+static struct sam9_smc_config __initdata foxg20_nand_smc_config = { -+ .ncs_read_setup = 0, -+ .nrd_setup = 2, -+ .ncs_write_setup = 0, -+ .nwe_setup = 2, -+ -+ .ncs_read_pulse = 4, -+ .nrd_pulse = 4, -+ .ncs_write_pulse = 4, -+ .nwe_pulse = 4, -+ -+ .read_cycle = 7, -+ .write_cycle = 7, -+ -+ .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE, -+ .tdf_cycles = 3, -+}; -+ -+static void __init foxg20_add_device_nand(void) -+{ -+ /* setup bus-width (8 or 16) */ -+ if (foxg20_nand_data.bus_width_16) -+ foxg20_nand_smc_config.mode |= AT91_SMC_DBW_16; -+ else -+ foxg20_nand_smc_config.mode |= AT91_SMC_DBW_8; -+ -+ /* configure chip-select 3 (NAND) */ -+ sam9_smc_configure(3, &foxg20_nand_smc_config); -+ -+ at91_add_device_nand(&foxg20_nand_data); -+} -+#endif -+ -+ -+/* -+ * MCI (SD/MMC) -+ * det_pin, wp_pin and vcc_pin are not connected -+ */ -+static struct at91_mmc_data __initdata foxg20_mmc_data = { -+ .slot_b = 1, -+ .wire4 = 1, -+}; -+ -+ -+/* -+ * LEDs -+ */ -+static struct gpio_led foxg20_leds[] = { -+ { /* user led, red */ -+ .name = "user_led", -+ .gpio = AT91_PIN_PC7, -+ .active_low = 0, -+ .default_trigger = "heartbeat", -+ }, -+}; -+ -+ -+/* -+ * GPIO Buttons -+ */ -+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) -+static struct gpio_keys_button foxg20_buttons[] = { -+ { -+ .gpio = AT91_PIN_PC4, -+ .code = BTN_1, -+ .desc = "Button 1", -+ .active_low = 1, -+ .wakeup = 1, -+ }, -+}; -+ -+static struct gpio_keys_platform_data foxg20_button_data = { -+ .buttons = foxg20_buttons, -+ .nbuttons = ARRAY_SIZE(foxg20_buttons), -+}; -+ -+static struct platform_device foxg20_button_device = { -+ .name = "gpio-keys", -+ .id = -1, -+ .num_resources = 0, -+ .dev = { -+ .platform_data = &foxg20_button_data, -+ } -+}; -+ -+static void __init foxg20_add_device_buttons(void) -+{ -+ at91_set_gpio_input(AT91_PIN_PC4, 1); /* btn1 */ -+ at91_set_deglitch(AT91_PIN_PC4, 1); -+ -+ platform_device_register(&foxg20_button_device); -+} -+#else -+static void __init foxg20_add_device_buttons(void) {} -+#endif -+ -+ -+#if !defined(FOXG20_WM8731) -+#if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE) -+static struct w1_gpio_platform_data w1_gpio_pdata = { -+ /* If you choose to use a pin other than PB16 it needs to be 3.3V */ -+ .pin = AT91_PIN_PB16, -+ .is_open_drain = 1, -+}; -+ -+static struct platform_device w1_device = { -+ .name = "w1-gpio", -+ .id = -1, -+ .dev.platform_data = &w1_gpio_pdata, -+}; -+ -+static void __init at91_add_device_w1(void) -+{ -+ at91_set_GPIO_periph(w1_gpio_pdata.pin, 1); -+ at91_set_multi_drive(w1_gpio_pdata.pin, 1); -+ platform_device_register(&w1_device); -+} -+ -+#endif -+#endif -+ -+ -+static struct i2c_board_info __initdata foxg20_i2c_devices[] = { -+ { -+ I2C_BOARD_INFO("24c512", 0x50), -+#ifdef FOXG20_WM8731 -+ I2C_BOARD_INFO("wm8731", 0x1b), -+#endif -+ }, -+}; -+ -+ -+static void __init foxg20_board_init(void) -+{ -+ /* Serial */ -+ at91_add_device_serial(); -+ /* USB Host */ -+ at91_add_device_usbh(&foxg20_usbh_data); -+ /* USB Device */ -+ at91_add_device_udc(&foxg20_udc_data); -+ /* SPI */ -+ at91_add_device_spi(foxg20_spi_devices, ARRAY_SIZE(foxg20_spi_devices)); -+#ifdef FOXG20_NAND -+ /* The Fox doesn't have NAND memory */ -+ /* NAND */ -+ foxg20_add_device_nand(); -+#endif -+ /* Ethernet */ -+ at91_add_device_eth(&foxg20_macb_data); -+ /* MMC */ -+ at91_add_device_mmc(0, &foxg20_mmc_data); -+ /* I2C */ -+ at91_add_device_i2c(foxg20_i2c_devices, ARRAY_SIZE(foxg20_i2c_devices)); -+ /* LEDs */ -+ at91_gpio_leds(foxg20_leds, ARRAY_SIZE(foxg20_leds)); -+ /* Push Buttons */ -+ foxg20_add_device_buttons(); -+#ifdef FOXG20_WM8731 -+ /* The Fox doesn't have this sound chip */ -+ /* PCK0 provides MCLK to the WM8731 */ -+ at91_set_B_periph(AT91_PIN_PC1, 0); -+ /* SSC (for WM8731) */ -+ at91_add_device_ssc(AT91SAM9260_ID_SSC, ATMEL_SSC_TX); -+#else -+#if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE) -+ at91_add_device_w1(); -+#endif -+#endif -+} -+ -+MACHINE_START(AT91SAM9G20EK, "Acme Systems FOXG20") -+ /* Maintainer: Lee McLoughlin */ -+ .phys_io = AT91_BASE_SYS, -+ .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, -+ .boot_params = AT91_SDRAM_BASE + 0x100, -+ .timer = &at91sam926x_timer, -+ .map_io = foxg20_map_io, -+ .init_irq = foxg20_init_irq, -+ .init_machine = foxg20_board_init, -+MACHINE_END -diff -Nur linux-2.6.36.orig/drivers/mmc/host/Kconfig linux-2.6.36/drivers/mmc/host/Kconfig ---- linux-2.6.36.orig/drivers/mmc/host/Kconfig 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/drivers/mmc/host/Kconfig 2010-12-25 19:15:17.000000000 +0100 -@@ -208,12 +208,12 @@ - - If unsure, say N. - --choice -- prompt "Atmel SD/MMC Driver" -- depends on AVR32 || ARCH_AT91 -- default MMC_ATMELMCI if AVR32 -- help -- Choose which driver to use for the Atmel MCI Silicon -+#choice -+# prompt "Atmel SD/MMC Driver" -+# depends on AVR32 || ARCH_AT91 -+# default MMC_ATMELMCI if AVR32 -+# help -+# Choose which driver to use for the Atmel MCI Silicon - - config MMC_AT91 - tristate "AT91 SD/MMC Card Interface support" -@@ -223,17 +223,17 @@ - - If unsure, say N. - --config MMC_ATMELMCI -- tristate "Atmel Multimedia Card Interface support" -- depends on AVR32 || ARCH_AT91 -- help -- This selects the Atmel Multimedia Card Interface driver. If -- you have an AT32 (AVR32) or AT91 platform with a Multimedia -- Card slot, say Y or M here. -- -- If unsure, say N. -- --endchoice -+#config MMC_ATMELMCI -+# tristate "Atmel Multimedia Card Interface support" -+# depends on AVR32 || ARCH_AT91 -+# help -+# This selects the Atmel Multimedia Card Interface driver. If -+# you have an AT32 (AVR32) or AT91 platform with a Multimedia -+# Card slot, say Y or M here. -+# -+# If unsure, say N. -+# -+#endchoice - - config MMC_ATMELMCI_DMA - bool "Atmel MCI DMA support (EXPERIMENTAL)" diff --git a/target/linux/patches/2.6.36/freebsd-compat.patch b/target/linux/patches/2.6.36/freebsd-compat.patch deleted file mode 100644 index 051fdc63e..000000000 --- a/target/linux/patches/2.6.36/freebsd-compat.patch +++ /dev/null @@ -1,11 +0,0 @@ -diff -Nur linux-2.6.30.orig/arch/x86/boot/tools/build.c linux-2.6.30/arch/x86/boot/tools/build.c ---- linux-2.6.30.orig/arch/x86/boot/tools/build.c 2009-06-10 05:05:27.000000000 +0200 -+++ linux-2.6.30/arch/x86/boot/tools/build.c 2009-06-11 09:18:50.000000000 +0200 -@@ -29,7 +29,6 @@ - #include - #include - #include --#include - #include - #include - #include diff --git a/target/linux/patches/2.6.36/gemalto.patch b/target/linux/patches/2.6.36/gemalto.patch deleted file mode 100644 index 9461d0317..000000000 --- a/target/linux/patches/2.6.36/gemalto.patch +++ /dev/null @@ -1,11 +0,0 @@ -diff -Nur linux-2.6.36.orig/drivers/serial/serial_cs.c linux-2.6.36/drivers/serial/serial_cs.c ---- linux-2.6.36.orig/drivers/serial/serial_cs.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/drivers/serial/serial_cs.c 2010-12-13 23:03:40.000000000 +0100 -@@ -794,6 +794,7 @@ - PCMCIA_DEVICE_MANF_CARD(0x0137, 0x0025), - PCMCIA_DEVICE_MANF_CARD(0x0137, 0x0045), - PCMCIA_DEVICE_MANF_CARD(0x0137, 0x0052), -+ PCMCIA_DEVICE_MANF_CARD(0x0157, 0x0100), /* Gemalto SCR */ - PCMCIA_DEVICE_MANF_CARD(0x016c, 0x0006), /* Psion 56K+Fax */ - PCMCIA_DEVICE_MANF_CARD(0x0200, 0x0001), /* MultiMobile */ - PCMCIA_DEVICE_PROD_ID134("ADV", "TECH", "COMpad-32/85", 0x67459937, 0x916d02ba, 0x8fbe92ae), diff --git a/target/linux/patches/2.6.36/lemote.patch b/target/linux/patches/2.6.36/lemote.patch deleted file mode 100644 index a03c5867b..000000000 --- a/target/linux/patches/2.6.36/lemote.patch +++ /dev/null @@ -1,4267 +0,0 @@ -diff -Nur linux-2.6.36.orig/arch/mips/Kconfig linux-2.6.36/arch/mips/Kconfig ---- linux-2.6.36.orig/arch/mips/Kconfig 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/arch/mips/Kconfig 2010-12-17 23:12:59.000000000 +0100 -@@ -205,7 +205,7 @@ - - config MACH_LOONGSON - bool "Loongson family of machines" -- select SYS_SUPPORTS_ZBOOT -+ select SYS_SUPPORTS_ZBOOT_UART16550 - help - This enables the support of Loongson family of machines. - -@@ -1093,6 +1093,8 @@ - bool "Loongson 2E" - depends on SYS_HAS_CPU_LOONGSON2E - select CPU_LOONGSON2 -+ select GENERIC_GPIO -+ select ARCH_REQUIRE_GPIOLIB - help - The Loongson 2E processor implements the MIPS III instruction set - with many extensions. -@@ -2012,6 +2014,18 @@ - source "kernel/time/Kconfig" - - # -+# High Resolution sched_clock() Configuration -+# -+ -+config CPU_HAS_FIXED_C0_COUNT -+ bool -+ -+config CPU_SUPPORTS_HR_SCHED_CLOCK -+ bool -+ depends on CPU_HAS_FIXED_C0_COUNT || !CPU_FREQ -+ default y -+ -+# - # Timer Interrupt Frequency Configuration - # - -diff -Nur linux-2.6.36.orig/arch/mips/include/asm/dma-mapping.h linux-2.6.36/arch/mips/include/asm/dma-mapping.h ---- linux-2.6.36.orig/arch/mips/include/asm/dma-mapping.h 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/arch/mips/include/asm/dma-mapping.h 2010-12-17 23:12:59.000000000 +0100 -@@ -65,4 +65,8 @@ - extern void dma_cache_sync(struct device *dev, void *vaddr, size_t size, - enum dma_data_direction direction); - -+#define ARCH_HAS_DMA_MMAP_COHERENT -+extern int dma_mmap_coherent(struct device *dev, struct vm_area_struct *vma, -+ void *cpu_addr, dma_addr_t handle, size_t size); -+ - #endif /* _ASM_DMA_MAPPING_H */ -diff -Nur linux-2.6.36.orig/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h linux-2.6.36/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h ---- linux-2.6.36.orig/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h 2010-12-17 23:12:59.000000000 +0100 -@@ -255,21 +255,12 @@ - * IDE STANDARD - */ - #define IDE_CAP 0x00 --#define IDE_CONFIG 0x01 --#define IDE_SMI 0x02 --#define IDE_ERROR 0x03 --#define IDE_PM 0x04 --#define IDE_DIAG 0x05 -- --/* -- * IDE SPEC. -- */ - #define IDE_IO_BAR 0x08 - #define IDE_CFG 0x10 - #define IDE_DTC 0x12 - #define IDE_CAST 0x13 - #define IDE_ETC 0x14 --#define IDE_INTERNAL_PM 0x15 -+#define IDE_PM 0x15 - - /* - * ACC STANDARD -@@ -301,5 +292,40 @@ - /* GPIO : I/O SPACE; REG : 32BITS */ - #define GPIOL_OUT_VAL 0x00 - #define GPIOL_OUT_EN 0x04 -+#define GPIOL_OUT_AUX1_SEL 0x10 -+/* SMB : I/O SPACE, REG : 8BITS WIDTH */ -+#define SMB_SDA 0x00 -+#define SMB_STS 0x01 -+#define SMB_STS_SLVSTP (1 << 7) -+#define SMB_STS_SDAST (1 << 6) -+#define SMB_STS_BER (1 << 5) -+#define SMB_STS_NEGACK (1 << 4) -+#define SMB_STS_STASTR (1 << 3) -+#define SMB_STS_NMATCH (1 << 2) -+#define SMB_STS_MASTER (1 << 1) -+#define SMB_STS_XMIT (1 << 0) -+#define SMB_CTRL_STS 0x02 -+#define SMB_CSTS_TGSTL (1 << 5) -+#define SMB_CSTS_TSDA (1 << 4) -+#define SMB_CSTS_GCMTCH (1 << 3) -+#define SMB_CSTS_MATCH (1 << 2) -+#define SMB_CSTS_BB (1 << 1) -+#define SMB_CSTS_BUSY (1 << 0) -+#define SMB_CTRL1 0x03 -+#define SMB_CTRL1_STASTRE (1 << 7) -+#define SMB_CTRL1_NMINTE (1 << 6) -+#define SMB_CTRL1_GCMEN (1 << 5) -+#define SMB_CTRL1_ACK (1 << 4) -+#define SMB_CTRL1_RSVD (1 << 3) -+#define SMB_CTRL1_INTEN (1 << 2) -+#define SMB_CTRL1_STOP (1 << 1) -+#define SMB_CTRL1_START (1 << 0) -+#define SMB_ADDR 0x04 -+#define SMB_ADDR_SAEN (1 << 7) -+#define SMB_CONTROLLER_ADDR (0xef << 0) -+#define SMB_CTRL2 0x05 -+#define SMB_FREQ (0x20 << 1) -+#define SMB_ENABLE (0x01 << 0) -+#define SMB_CTRL3 0x06 - - #endif /* _CS5536_H */ -diff -Nur linux-2.6.36.orig/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h linux-2.6.36/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h ---- linux-2.6.36.orig/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h 2010-12-17 23:12:59.000000000 +0100 -@@ -32,4 +32,9 @@ - #define MFGPT0_CNT (MFGPT_BASE + 4) - #define MFGPT0_SETUP (MFGPT_BASE + 6) - -+#define MFGPT2_CMP1 (MFGPT_BASE + 0x10) -+#define MFGPT2_CMP2 (MFGPT_BASE + 0x12) -+#define MFGPT2_CNT (MFGPT_BASE + 0x14) -+#define MFGPT2_SETUP (MFGPT_BASE + 0x16) -+ - #endif /*!_CS5536_MFGPT_H */ -diff -Nur linux-2.6.36.orig/arch/mips/include/asm/mach-loongson/ec_kb3310b.h linux-2.6.36/arch/mips/include/asm/mach-loongson/ec_kb3310b.h ---- linux-2.6.36.orig/arch/mips/include/asm/mach-loongson/ec_kb3310b.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/include/asm/mach-loongson/ec_kb3310b.h 2010-12-17 23:12:59.000000000 +0100 -@@ -0,0 +1,191 @@ -+/* -+ * KB3310B Embedded Controller -+ * -+ * Copyright (C) 2008 Lemote Inc. -+ * Author: liujl , 2008-03-14 -+ * Copyright (C) 2009 Lemote Inc. -+ * Author: Wu Zhangjin -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ */ -+ -+#ifndef _EC_KB3310B_H -+#define _EC_KB3310B_H -+ -+extern unsigned char ec_read(unsigned short addr); -+extern void ec_write(unsigned short addr, unsigned char val); -+extern int ec_query_seq(unsigned char cmd); -+extern int ec_query_event_num(void); -+extern int ec_get_event_num(void); -+ -+typedef int (*sci_handler) (int status); -+extern sci_handler yeeloong_report_lid_status; -+ -+#define SCI_IRQ_NUM 0x0A -+ -+/* -+ * The following registers are determined by the EC index configuration. -+ * 1, fill the PORT_HIGH as EC register high part. -+ * 2, fill the PORT_LOW as EC register low part. -+ * 3, fill the PORT_DATA as EC register write data or get the data from it. -+ */ -+#define EC_IO_PORT_HIGH 0x0381 -+#define EC_IO_PORT_LOW 0x0382 -+#define EC_IO_PORT_DATA 0x0383 -+ -+/* -+ * EC delay time is 500us for register and status access -+ */ -+#define EC_REG_DELAY 500 /* unit : us */ -+#define EC_CMD_TIMEOUT 0x1000 -+ -+/* -+ * EC access port for SCI communication -+ */ -+#define EC_CMD_PORT 0x66 -+#define EC_STS_PORT 0x66 -+#define EC_DAT_PORT 0x62 -+#define CMD_INIT_IDLE_MODE 0xdd -+#define CMD_EXIT_IDLE_MODE 0xdf -+#define CMD_INIT_RESET_MODE 0xd8 -+#define CMD_REBOOT_SYSTEM 0x8c -+#define CMD_GET_EVENT_NUM 0x84 -+#define CMD_PROGRAM_PIECE 0xda -+ -+/* Temperature & Fan registers */ -+#define REG_TEMPERATURE_VALUE 0xF458 -+#define REG_FAN_AUTO_MAN_SWITCH 0xF459 -+#define BIT_FAN_AUTO 0 -+#define BIT_FAN_MANUAL 1 -+#define REG_FAN_CONTROL 0xF4D2 -+#define BIT_FAN_CONTROL_ON (1 << 0) -+#define BIT_FAN_CONTROL_OFF (0 << 0) -+#define REG_FAN_STATUS 0xF4DA -+#define BIT_FAN_STATUS_ON (1 << 0) -+#define BIT_FAN_STATUS_OFF (0 << 0) -+#define REG_FAN_SPEED_HIGH 0xFE22 -+#define REG_FAN_SPEED_LOW 0xFE23 -+#define REG_FAN_SPEED_LEVEL 0xF4CC -+/* Fan speed divider */ -+#define FAN_SPEED_DIVIDER 480000 /* (60*1000*1000/62.5/2)*/ -+ -+/* Battery registers */ -+#define REG_BAT_DESIGN_CAP_HIGH 0xF77D -+#define REG_BAT_DESIGN_CAP_LOW 0xF77E -+#define REG_BAT_FULLCHG_CAP_HIGH 0xF780 -+#define REG_BAT_FULLCHG_CAP_LOW 0xF781 -+#define REG_BAT_DESIGN_VOL_HIGH 0xF782 -+#define REG_BAT_DESIGN_VOL_LOW 0xF783 -+#define REG_BAT_CURRENT_HIGH 0xF784 -+#define REG_BAT_CURRENT_LOW 0xF785 -+#define REG_BAT_VOLTAGE_HIGH 0xF786 -+#define REG_BAT_VOLTAGE_LOW 0xF787 -+#define REG_BAT_TEMPERATURE_HIGH 0xF788 -+#define REG_BAT_TEMPERATURE_LOW 0xF789 -+#define REG_BAT_RELATIVE_CAP_HIGH 0xF492 -+#define REG_BAT_RELATIVE_CAP_LOW 0xF493 -+#define REG_BAT_VENDOR 0xF4C4 -+#define FLAG_BAT_VENDOR_SANYO 0x01 -+#define FLAG_BAT_VENDOR_SIMPLO 0x02 -+#define REG_BAT_CELL_COUNT 0xF4C6 -+#define FLAG_BAT_CELL_3S1P 0x03 -+#define FLAG_BAT_CELL_3S2P 0x06 -+#define REG_BAT_CHARGE 0xF4A2 -+#define FLAG_BAT_CHARGE_DISCHARGE 0x01 -+#define FLAG_BAT_CHARGE_CHARGE 0x02 -+#define FLAG_BAT_CHARGE_ACPOWER 0x00 -+#define REG_BAT_STATUS 0xF4B0 -+#define BIT_BAT_STATUS_LOW (1 << 5) -+#define BIT_BAT_STATUS_DESTROY (1 << 2) -+#define BIT_BAT_STATUS_FULL (1 << 1) -+#define BIT_BAT_STATUS_IN (1 << 0) -+#define REG_BAT_CHARGE_STATUS 0xF4B1 -+#define BIT_BAT_CHARGE_STATUS_OVERTEMP (1 << 2) -+#define BIT_BAT_CHARGE_STATUS_PRECHG (1 << 1) -+#define REG_BAT_STATE 0xF482 -+#define BIT_BAT_STATE_CHARGING (1 << 1) -+#define BIT_BAT_STATE_DISCHARGING (1 << 0) -+#define REG_BAT_POWER 0xF440 -+#define BIT_BAT_POWER_S3 (1 << 2) -+#define BIT_BAT_POWER_ON (1 << 1) -+#define BIT_BAT_POWER_ACIN (1 << 0) -+ -+/* Audio: rd/wr */ -+#define REG_AUDIO_VOLUME 0xF46C -+#define REG_AUDIO_MUTE 0xF4E7 -+#define REG_AUDIO_BEEP 0xF4D0 -+/* USB port power or not: rd/wr */ -+#define REG_USB0_FLAG 0xF461 -+#define REG_USB1_FLAG 0xF462 -+#define REG_USB2_FLAG 0xF463 -+#define BIT_USB_FLAG_ON 1 -+#define BIT_USB_FLAG_OFF 0 -+/* LID */ -+#define REG_LID_DETECT 0xF4BD -+#define BIT_LID_DETECT_ON 1 -+#define BIT_LID_DETECT_OFF 0 -+/* CRT */ -+#define REG_CRT_DETECT 0xF4AD -+#define BIT_CRT_DETECT_PLUG 1 -+#define BIT_CRT_DETECT_UNPLUG 0 -+/* LCD backlight brightness adjust: 9 levels */ -+#define REG_DISPLAY_BRIGHTNESS 0xF4F5 -+/* Black screen Status */ -+#define BIT_DISPLAY_LCD_ON 1 -+#define BIT_DISPLAY_LCD_OFF 0 -+/* LCD backlight control: off/restore */ -+#define REG_BACKLIGHT_CTRL 0xF7BD -+#define BIT_BACKLIGHT_ON 1 -+#define BIT_BACKLIGHT_OFF 0 -+/* Reset the machine auto-clear: rd/wr */ -+#define REG_RESET 0xF4EC -+#define BIT_RESET_ON 1 -+/* Light the led: rd/wr */ -+#define REG_LED 0xF4C8 -+#define BIT_LED_RED_POWER (1 << 0) -+#define BIT_LED_ORANGE_POWER (1 << 1) -+#define BIT_LED_GREEN_CHARGE (1 << 2) -+#define BIT_LED_RED_CHARGE (1 << 3) -+#define BIT_LED_NUMLOCK (1 << 4) -+/* Test led mode, all led on/off */ -+#define REG_LED_TEST 0xF4C2 -+#define BIT_LED_TEST_IN 1 -+#define BIT_LED_TEST_OUT 0 -+/* Camera on/off */ -+#define REG_CAMERA_STATUS 0xF46A -+#define BIT_CAMERA_STATUS_ON 1 -+#define BIT_CAMERA_STATUS_OFF 0 -+#define REG_CAMERA_CONTROL 0xF7B7 -+#define BIT_CAMERA_CONTROL_OFF 0 -+#define BIT_CAMERA_CONTROL_ON 1 -+/* Wlan Status */ -+#define REG_WLAN 0xF4FA -+#define BIT_WLAN_ON 1 -+#define BIT_WLAN_OFF 0 -+#define REG_DISPLAY_LCD 0xF79F -+ -+/* SCI Event Number from EC */ -+enum { -+ EVENT_LID = 0x23, /* Turn on/off LID */ -+ EVENT_SWITCHVIDEOMODE, /* Fn+F3 for display switch */ -+ EVENT_SLEEP, /* Fn+F1 for entering sleep mode */ -+ EVENT_OVERTEMP, /* Over-temperature happened */ -+ EVENT_CRT_DETECT, /* CRT is connected */ -+ EVENT_CAMERA, /* Camera on/off */ -+ EVENT_USB_OC2, /* USB2 Over Current occurred */ -+ EVENT_USB_OC0, /* USB0 Over Current occurred */ -+ EVENT_DISPLAYTOGGLE, /* Fn+F2, Turn on/off backlight */ -+ EVENT_AUDIO_MUTE, /* Fn+F4, Mute on/off */ -+ EVENT_DISPLAY_BRIGHTNESS,/* Fn+^/V, LCD backlight brightness adjust */ -+ EVENT_AC_BAT, /* AC & Battery relative issue */ -+ EVENT_AUDIO_VOLUME, /* Fn+<|>, Volume adjust */ -+ EVENT_WLAN, /* Wlan on/off */ -+}; -+ -+#define EVENT_START EVENT_LID -+#define EVENT_END EVENT_WLAN -+ -+#endif /* !_EC_KB3310B_H */ -diff -Nur linux-2.6.36.orig/arch/mips/include/asm/mach-loongson/loongson.h linux-2.6.36/arch/mips/include/asm/mach-loongson/loongson.h ---- linux-2.6.36.orig/arch/mips/include/asm/mach-loongson/loongson.h 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/arch/mips/include/asm/mach-loongson/loongson.h 2010-12-17 23:12:59.000000000 +0100 -@@ -42,6 +42,12 @@ - #endif - } - -+/* -+ * Copy kernel command line from arcs_cmdline -+ */ -+#include -+extern char loongson_cmdline[COMMAND_LINE_SIZE]; -+ - /* irq operation functions */ - extern void bonito_irqdispatch(void); - extern void __init bonito_irq_init(void); -diff -Nur linux-2.6.36.orig/arch/mips/kernel/csrc-r4k.c linux-2.6.36/arch/mips/kernel/csrc-r4k.c ---- linux-2.6.36.orig/arch/mips/kernel/csrc-r4k.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/arch/mips/kernel/csrc-r4k.c 2010-12-17 23:12:59.000000000 +0100 -@@ -6,10 +6,66 @@ - * Copyright (C) 2007 by Ralf Baechle - */ - #include -+#include - #include -+#include - - #include - -+#ifdef CONFIG_CPU_SUPPORTS_HR_SCHED_CLOCK -+/* -+ * MIPS sched_clock implementation. -+ * -+ * Because the hardware timer period is quite short and because cnt32_to_63() -+ * needs to be called at least once per half period to work properly, a kernel -+ * timer is set up to ensure this requirement is always met. -+ * -+ * Please refer to include/linux/cnt32_to_63.h and arch/arm/plat-orion/time.c -+ */ -+#define CLOCK2NS_SCALE_FACTOR 8 -+ -+static unsigned long clock2ns_scale __read_mostly; -+ -+unsigned long long notrace sched_clock(void) -+{ -+ unsigned long long v = cnt32_to_63(read_c0_count()); -+ return (v * clock2ns_scale) >> CLOCK2NS_SCALE_FACTOR; -+} -+ -+static struct timer_list cnt32_to_63_keepwarm_timer; -+ -+static void cnt32_to_63_keepwarm(unsigned long data) -+{ -+ mod_timer(&cnt32_to_63_keepwarm_timer, round_jiffies(jiffies + data)); -+ sched_clock(); -+} -+#endif -+ -+static inline void setup_hres_sched_clock(unsigned long clock) -+{ -+#ifdef CONFIG_CPU_SUPPORTS_HR_SCHED_CLOCK -+ unsigned long long v; -+ unsigned long data; -+ -+ v = NSEC_PER_SEC; -+ v <<= CLOCK2NS_SCALE_FACTOR; -+ v += clock/2; -+ do_div(v, clock); -+ /* -+ * We want an even value to automatically clear the top bit -+ * returned by cnt32_to_63() without an additional run time -+ * instruction. So if the LSB is 1 then round it up. -+ */ -+ if (v & 1) -+ v++; -+ clock2ns_scale = v; -+ -+ data = 0x80000000UL / clock * HZ; -+ setup_timer(&cnt32_to_63_keepwarm_timer, cnt32_to_63_keepwarm, data); -+ mod_timer(&cnt32_to_63_keepwarm_timer, round_jiffies(jiffies + data)); -+#endif -+} -+ - static cycle_t c0_hpt_read(struct clocksource *cs) - { - return read_c0_count(); -@@ -27,6 +83,8 @@ - if (!cpu_has_counter || !mips_hpt_frequency) - return -ENXIO; - -+ setup_hres_sched_clock(mips_hpt_frequency); -+ - /* Calculate a somewhat reasonable rating value */ - clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000; - -diff -Nur linux-2.6.36.orig/arch/mips/kernel/time.c linux-2.6.36/arch/mips/kernel/time.c ---- linux-2.6.36.orig/arch/mips/kernel/time.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/arch/mips/kernel/time.c 2010-12-17 23:12:59.000000000 +0100 -@@ -119,6 +119,11 @@ - - void __init time_init(void) - { -+#ifdef CONFIG_HR_SCHED_CLOCK -+ if (!mips_clockevent_init() || !cpu_has_mfc0_count_bug()) -+ write_c0_count(0); -+#endif -+ - plat_time_init(); - - if (!mips_clockevent_init() || !cpu_has_mfc0_count_bug()) -diff -Nur linux-2.6.36.orig/arch/mips/loongson/common/cmdline.c linux-2.6.36/arch/mips/loongson/common/cmdline.c ---- linux-2.6.36.orig/arch/mips/loongson/common/cmdline.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/arch/mips/loongson/common/cmdline.c 2010-12-17 23:12:59.000000000 +0100 -@@ -17,10 +17,15 @@ - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -+#include - #include - - #include - -+/* the kernel command line copied from arcs_cmdline */ -+char loongson_cmdline[COMMAND_LINE_SIZE]; -+EXPORT_SYMBOL(loongson_cmdline); -+ - void __init prom_init_cmdline(void) - { - int prom_argc; -@@ -50,4 +55,26 @@ - strcat(arcs_cmdline, " root=/dev/hda1"); - - prom_init_machtype(); -+ -+ /* append machine specific command line */ -+ switch (mips_machtype) { -+ case MACH_LEMOTE_LL2F: -+ if ((strstr(arcs_cmdline, "video=")) == NULL) -+ strcat(arcs_cmdline, " video=sisfb:1360x768-16@60"); -+ break; -+ case MACH_LEMOTE_FL2F: -+ if ((strstr(arcs_cmdline, "ide_core.ignore_cable=")) == NULL) -+ strcat(arcs_cmdline, " ide_core.ignore_cable=0"); -+ break; -+ case MACH_LEMOTE_ML2F7: -+ /* Mengloong-2F has a 800x480 screen */ -+ if ((strstr(arcs_cmdline, "vga=")) == NULL) -+ strcat(arcs_cmdline, " vga=0x313"); -+ break; -+ default: -+ break; -+ } -+ -+ /* copy arcs_cmdline into loongson_cmdline */ -+ strncpy(loongson_cmdline, arcs_cmdline, COMMAND_LINE_SIZE); - } -diff -Nur linux-2.6.36.orig/arch/mips/loongson/common/cs5536/cs5536_acc.c linux-2.6.36/arch/mips/loongson/common/cs5536/cs5536_acc.c ---- linux-2.6.36.orig/arch/mips/loongson/common/cs5536/cs5536_acc.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/arch/mips/loongson/common/cs5536/cs5536_acc.c 2010-12-17 23:12:59.000000000 +0100 -@@ -18,7 +18,7 @@ - - void pci_acc_write_reg(int reg, u32 value) - { -- u32 hi = 0, lo = value; -+ u32 hi, lo; - - switch (reg) { - case PCI_COMMAND: -@@ -66,75 +66,73 @@ - u32 pci_acc_read_reg(int reg) - { - u32 hi, lo; -- u32 conf_data = 0; -+ u32 cfg = 0; - - switch (reg) { - case PCI_VENDOR_ID: -- conf_data = -- CFG_PCI_VENDOR_ID(CS5536_ACC_DEVICE_ID, CS5536_VENDOR_ID); -+ cfg = CFG_PCI_VENDOR_ID(CS5536_ACC_DEVICE_ID, -+ CS5536_VENDOR_ID); - break; - case PCI_COMMAND: - _rdmsr(GLIU_MSR_REG(GLIU_IOD_BM1), &hi, &lo); - if (((lo & 0xfff00000) || (hi & 0x000000ff)) - && ((hi & 0xf0000000) == 0xa0000000)) -- conf_data |= PCI_COMMAND_IO; -+ cfg |= PCI_COMMAND_IO; - _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo); - if ((lo & 0x300) == 0x300) -- conf_data |= PCI_COMMAND_MASTER; -+ cfg |= PCI_COMMAND_MASTER; - break; - case PCI_STATUS: -- conf_data |= PCI_STATUS_66MHZ; -- conf_data |= PCI_STATUS_FAST_BACK; -+ cfg |= PCI_STATUS_66MHZ; -+ cfg |= PCI_STATUS_FAST_BACK; - _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); - if (lo & SB_PARE_ERR_FLAG) -- conf_data |= PCI_STATUS_PARITY; -- conf_data |= PCI_STATUS_DEVSEL_MEDIUM; -+ cfg |= PCI_STATUS_PARITY; -+ cfg |= PCI_STATUS_DEVSEL_MEDIUM; - break; - case PCI_CLASS_REVISION: - _rdmsr(ACC_MSR_REG(ACC_CAP), &hi, &lo); -- conf_data = lo & 0x000000ff; -- conf_data |= (CS5536_ACC_CLASS_CODE << 8); -+ cfg = lo & 0x000000ff; -+ cfg |= (CS5536_ACC_CLASS_CODE << 8); - break; - case PCI_CACHE_LINE_SIZE: -- conf_data = -- CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, -- PCI_NORMAL_LATENCY_TIMER); -+ cfg = CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, -+ PCI_NORMAL_LATENCY_TIMER); - break; - case PCI_BAR0_REG: - _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); - if (lo & SOFT_BAR_ACC_FLAG) { -- conf_data = CS5536_ACC_RANGE | -+ cfg = CS5536_ACC_RANGE | - PCI_BASE_ADDRESS_SPACE_IO; - lo &= ~SOFT_BAR_ACC_FLAG; - _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); - } else { - _rdmsr(GLIU_MSR_REG(GLIU_IOD_BM1), &hi, &lo); -- conf_data = (hi & 0x000000ff) << 12; -- conf_data |= (lo & 0xfff00000) >> 20; -- conf_data |= 0x01; -- conf_data &= ~0x02; -+ cfg = (hi & 0x000000ff) << 12; -+ cfg |= (lo & 0xfff00000) >> 20; -+ cfg |= 0x01; -+ cfg &= ~0x02; - } - break; - case PCI_CARDBUS_CIS: -- conf_data = PCI_CARDBUS_CIS_POINTER; -+ cfg = PCI_CARDBUS_CIS_POINTER; - break; - case PCI_SUBSYSTEM_VENDOR_ID: -- conf_data = -- CFG_PCI_VENDOR_ID(CS5536_ACC_SUB_ID, CS5536_SUB_VENDOR_ID); -+ cfg = CFG_PCI_VENDOR_ID(CS5536_ACC_SUB_ID, -+ CS5536_SUB_VENDOR_ID); - break; - case PCI_ROM_ADDRESS: -- conf_data = PCI_EXPANSION_ROM_BAR; -+ cfg = PCI_EXPANSION_ROM_BAR; - break; - case PCI_CAPABILITY_LIST: -- conf_data = PCI_CAPLIST_USB_POINTER; -+ cfg = PCI_CAPLIST_USB_POINTER; - break; - case PCI_INTERRUPT_LINE: -- conf_data = -- CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_ACC_INTR); -+ cfg = CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_ACC_INTR); - break; - default: - break; - } - -- return conf_data; -+ return cfg; - } -diff -Nur linux-2.6.36.orig/arch/mips/loongson/common/cs5536/cs5536_ehci.c linux-2.6.36/arch/mips/loongson/common/cs5536/cs5536_ehci.c ---- linux-2.6.36.orig/arch/mips/loongson/common/cs5536/cs5536_ehci.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/arch/mips/loongson/common/cs5536/cs5536_ehci.c 2010-12-17 23:12:59.000000000 +0100 -@@ -18,7 +18,7 @@ - - void pci_ehci_write_reg(int reg, u32 value) - { -- u32 hi = 0, lo = value; -+ u32 hi, lo; - - switch (reg) { - case PCI_COMMAND: -@@ -78,83 +78,81 @@ - - u32 pci_ehci_read_reg(int reg) - { -- u32 conf_data = 0; -+ u32 cfg = 0; - u32 hi, lo; - - switch (reg) { - case PCI_VENDOR_ID: -- conf_data = -- CFG_PCI_VENDOR_ID(CS5536_EHCI_DEVICE_ID, CS5536_VENDOR_ID); -+ cfg = CFG_PCI_VENDOR_ID(CS5536_EHCI_DEVICE_ID, -+ CS5536_VENDOR_ID); - break; - case PCI_COMMAND: - _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); - if (hi & PCI_COMMAND_MASTER) -- conf_data |= PCI_COMMAND_MASTER; -+ cfg |= PCI_COMMAND_MASTER; - if (hi & PCI_COMMAND_MEMORY) -- conf_data |= PCI_COMMAND_MEMORY; -+ cfg |= PCI_COMMAND_MEMORY; - break; - case PCI_STATUS: -- conf_data |= PCI_STATUS_66MHZ; -- conf_data |= PCI_STATUS_FAST_BACK; -+ cfg |= PCI_STATUS_66MHZ; -+ cfg |= PCI_STATUS_FAST_BACK; - _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); - if (lo & SB_PARE_ERR_FLAG) -- conf_data |= PCI_STATUS_PARITY; -- conf_data |= PCI_STATUS_DEVSEL_MEDIUM; -+ cfg |= PCI_STATUS_PARITY; -+ cfg |= PCI_STATUS_DEVSEL_MEDIUM; - break; - case PCI_CLASS_REVISION: - _rdmsr(USB_MSR_REG(USB_CAP), &hi, &lo); -- conf_data = lo & 0x000000ff; -- conf_data |= (CS5536_EHCI_CLASS_CODE << 8); -+ cfg = lo & 0x000000ff; -+ cfg |= (CS5536_EHCI_CLASS_CODE << 8); - break; - case PCI_CACHE_LINE_SIZE: -- conf_data = -- CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, -- PCI_NORMAL_LATENCY_TIMER); -+ cfg = CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, -+ PCI_NORMAL_LATENCY_TIMER); - break; - case PCI_BAR0_REG: - _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); - if (lo & SOFT_BAR_EHCI_FLAG) { -- conf_data = CS5536_EHCI_RANGE | -+ cfg = CS5536_EHCI_RANGE | - PCI_BASE_ADDRESS_SPACE_MEMORY; - lo &= ~SOFT_BAR_EHCI_FLAG; - _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); - } else { - _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); -- conf_data = lo & 0xfffff000; -+ cfg = lo & 0xfffff000; - } - break; - case PCI_CARDBUS_CIS: -- conf_data = PCI_CARDBUS_CIS_POINTER; -+ cfg = PCI_CARDBUS_CIS_POINTER; - break; - case PCI_SUBSYSTEM_VENDOR_ID: -- conf_data = -- CFG_PCI_VENDOR_ID(CS5536_EHCI_SUB_ID, CS5536_SUB_VENDOR_ID); -+ cfg = CFG_PCI_VENDOR_ID(CS5536_EHCI_SUB_ID, -+ CS5536_SUB_VENDOR_ID); - break; - case PCI_ROM_ADDRESS: -- conf_data = PCI_EXPANSION_ROM_BAR; -+ cfg = PCI_EXPANSION_ROM_BAR; - break; - case PCI_CAPABILITY_LIST: -- conf_data = PCI_CAPLIST_USB_POINTER; -+ cfg = PCI_CAPLIST_USB_POINTER; - break; - case PCI_INTERRUPT_LINE: -- conf_data = -- CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR); -+ cfg = CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR); - break; - case PCI_EHCI_LEGSMIEN_REG: - _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); -- conf_data = (hi & 0x003f0000) >> 16; -+ cfg = (hi & 0x003f0000) >> 16; - break; - case PCI_EHCI_LEGSMISTS_REG: - _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); -- conf_data = (hi & 0x3f000000) >> 24; -+ cfg = (hi & 0x3f000000) >> 24; - break; - case PCI_EHCI_FLADJ_REG: - _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); -- conf_data = hi & 0x00003f00; -+ cfg = hi & 0x00003f00; - break; - default: - break; - } - -- return conf_data; -+ return cfg; - } -diff -Nur linux-2.6.36.orig/arch/mips/loongson/common/cs5536/cs5536_ide.c linux-2.6.36/arch/mips/loongson/common/cs5536/cs5536_ide.c ---- linux-2.6.36.orig/arch/mips/loongson/common/cs5536/cs5536_ide.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/arch/mips/loongson/common/cs5536/cs5536_ide.c 2010-12-17 23:12:59.000000000 +0100 -@@ -18,7 +18,7 @@ - - void pci_ide_write_reg(int reg, u32 value) - { -- u32 hi = 0, lo = value; -+ u32 hi, lo; - - switch (reg) { - case PCI_COMMAND: -@@ -72,26 +72,16 @@ - _wrmsr(IDE_MSR_REG(IDE_CFG), hi, lo); - } - break; -- case PCI_IDE_DTC_REG: -- _rdmsr(IDE_MSR_REG(IDE_DTC), &hi, &lo); -- lo = value; -- _wrmsr(IDE_MSR_REG(IDE_DTC), hi, lo); -- break; -- case PCI_IDE_CAST_REG: -- _rdmsr(IDE_MSR_REG(IDE_CAST), &hi, &lo); -- lo = value; -- _wrmsr(IDE_MSR_REG(IDE_CAST), hi, lo); -- break; -- case PCI_IDE_ETC_REG: -- _rdmsr(IDE_MSR_REG(IDE_ETC), &hi, &lo); -- lo = value; -- _wrmsr(IDE_MSR_REG(IDE_ETC), hi, lo); -- break; -- case PCI_IDE_PM_REG: -- _rdmsr(IDE_MSR_REG(IDE_INTERNAL_PM), &hi, &lo); -- lo = value; -- _wrmsr(IDE_MSR_REG(IDE_INTERNAL_PM), hi, lo); -- break; -+#define SET_PCI_IDE_REG(r) \ -+ case PCI_IDE_##r##_REG: \ -+ _rdmsr(IDE_MSR_REG(IDE_##r), &hi, &lo); \ -+ lo = value; \ -+ _wrmsr(IDE_MSR_REG(IDE_##r), hi, lo); \ -+ break; -+ SET_PCI_IDE_REG(DTC) -+ SET_PCI_IDE_REG(CAST) -+ SET_PCI_IDE_REG(ETC) -+ SET_PCI_IDE_REG(PM) - default: - break; - } -@@ -99,94 +89,82 @@ - - u32 pci_ide_read_reg(int reg) - { -- u32 conf_data = 0; -+ u32 cfg = 0; - u32 hi, lo; - - switch (reg) { - case PCI_VENDOR_ID: -- conf_data = -- CFG_PCI_VENDOR_ID(CS5536_IDE_DEVICE_ID, CS5536_VENDOR_ID); -+ cfg = CFG_PCI_VENDOR_ID(CS5536_IDE_DEVICE_ID, -+ CS5536_VENDOR_ID); - break; - case PCI_COMMAND: - _rdmsr(IDE_MSR_REG(IDE_IO_BAR), &hi, &lo); - if (lo & 0xfffffff0) -- conf_data |= PCI_COMMAND_IO; -+ cfg |= PCI_COMMAND_IO; - _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo); - if ((lo & 0x30) == 0x30) -- conf_data |= PCI_COMMAND_MASTER; -+ cfg |= PCI_COMMAND_MASTER; - break; - case PCI_STATUS: -- conf_data |= PCI_STATUS_66MHZ; -- conf_data |= PCI_STATUS_FAST_BACK; -+ cfg |= PCI_STATUS_66MHZ; -+ cfg |= PCI_STATUS_FAST_BACK; - _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); - if (lo & SB_PARE_ERR_FLAG) -- conf_data |= PCI_STATUS_PARITY; -- conf_data |= PCI_STATUS_DEVSEL_MEDIUM; -+ cfg |= PCI_STATUS_PARITY; -+ cfg |= PCI_STATUS_DEVSEL_MEDIUM; - break; - case PCI_CLASS_REVISION: - _rdmsr(IDE_MSR_REG(IDE_CAP), &hi, &lo); -- conf_data = lo & 0x000000ff; -- conf_data |= (CS5536_IDE_CLASS_CODE << 8); -+ cfg = lo & 0x000000ff; -+ cfg |= (CS5536_IDE_CLASS_CODE << 8); - break; - case PCI_CACHE_LINE_SIZE: - _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo); - hi &= 0x000000f8; -- conf_data = CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, hi); -+ cfg = CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, hi); - break; - case PCI_BAR4_REG: - _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); - if (lo & SOFT_BAR_IDE_FLAG) { -- conf_data = CS5536_IDE_RANGE | -+ cfg = CS5536_IDE_RANGE | - PCI_BASE_ADDRESS_SPACE_IO; - lo &= ~SOFT_BAR_IDE_FLAG; - _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); - } else { - _rdmsr(IDE_MSR_REG(IDE_IO_BAR), &hi, &lo); -- conf_data = lo & 0xfffffff0; -- conf_data |= 0x01; -- conf_data &= ~0x02; -+ cfg = lo & 0xfffffff0; -+ cfg |= 0x01; -+ cfg &= ~0x02; - } - break; - case PCI_CARDBUS_CIS: -- conf_data = PCI_CARDBUS_CIS_POINTER; -+ cfg = PCI_CARDBUS_CIS_POINTER; - break; - case PCI_SUBSYSTEM_VENDOR_ID: -- conf_data = -- CFG_PCI_VENDOR_ID(CS5536_IDE_SUB_ID, CS5536_SUB_VENDOR_ID); -+ cfg = CFG_PCI_VENDOR_ID(CS5536_IDE_SUB_ID, -+ CS5536_SUB_VENDOR_ID); - break; - case PCI_ROM_ADDRESS: -- conf_data = PCI_EXPANSION_ROM_BAR; -+ cfg = PCI_EXPANSION_ROM_BAR; - break; - case PCI_CAPABILITY_LIST: -- conf_data = PCI_CAPLIST_POINTER; -+ cfg = PCI_CAPLIST_POINTER; - break; - case PCI_INTERRUPT_LINE: -- conf_data = -- CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_IDE_INTR); -- break; -- case PCI_IDE_CFG_REG: -- _rdmsr(IDE_MSR_REG(IDE_CFG), &hi, &lo); -- conf_data = lo; -- break; -- case PCI_IDE_DTC_REG: -- _rdmsr(IDE_MSR_REG(IDE_DTC), &hi, &lo); -- conf_data = lo; -- break; -- case PCI_IDE_CAST_REG: -- _rdmsr(IDE_MSR_REG(IDE_CAST), &hi, &lo); -- conf_data = lo; -- break; -- case PCI_IDE_ETC_REG: -- _rdmsr(IDE_MSR_REG(IDE_ETC), &hi, &lo); -- conf_data = lo; -- break; -- case PCI_IDE_PM_REG: -- _rdmsr(IDE_MSR_REG(IDE_INTERNAL_PM), &hi, &lo); -- conf_data = lo; -+ cfg = CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_IDE_INTR); - break; -+#define GET_PCI_IDE_REG(r) \ -+ case PCI_IDE_##r##_REG: \ -+ _rdmsr(IDE_MSR_REG(IDE_##r), &hi, &cfg); \ -+ break; -+ GET_PCI_IDE_REG(CFG) -+ GET_PCI_IDE_REG(DTC) -+ GET_PCI_IDE_REG(CAST) -+ GET_PCI_IDE_REG(ETC) -+ GET_PCI_IDE_REG(PM) - default: - break; - } - -- return conf_data; -+ return cfg; - } -diff -Nur linux-2.6.36.orig/arch/mips/loongson/common/cs5536/cs5536_ohci.c linux-2.6.36/arch/mips/loongson/common/cs5536/cs5536_ohci.c ---- linux-2.6.36.orig/arch/mips/loongson/common/cs5536/cs5536_ohci.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/arch/mips/loongson/common/cs5536/cs5536_ohci.c 2010-12-17 23:12:59.000000000 +0100 -@@ -18,7 +18,7 @@ - - void pci_ohci_write_reg(int reg, u32 value) - { -- u32 hi = 0, lo = value; -+ u32 hi, lo; - - switch (reg) { - case PCI_COMMAND: -@@ -73,77 +73,75 @@ - - u32 pci_ohci_read_reg(int reg) - { -- u32 conf_data = 0; -+ u32 cfg = 0; - u32 hi, lo; - - switch (reg) { - case PCI_VENDOR_ID: -- conf_data = -- CFG_PCI_VENDOR_ID(CS5536_OHCI_DEVICE_ID, CS5536_VENDOR_ID); -+ cfg = CFG_PCI_VENDOR_ID(CS5536_OHCI_DEVICE_ID, -+ CS5536_VENDOR_ID); - break; - case PCI_COMMAND: - _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo); - if (hi & PCI_COMMAND_MASTER) -- conf_data |= PCI_COMMAND_MASTER; -+ cfg |= PCI_COMMAND_MASTER; - if (hi & PCI_COMMAND_MEMORY) -- conf_data |= PCI_COMMAND_MEMORY; -+ cfg |= PCI_COMMAND_MEMORY; - break; - case PCI_STATUS: -- conf_data |= PCI_STATUS_66MHZ; -- conf_data |= PCI_STATUS_FAST_BACK; -+ cfg |= PCI_STATUS_66MHZ; -+ cfg |= PCI_STATUS_FAST_BACK; - _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); - if (lo & SB_PARE_ERR_FLAG) -- conf_data |= PCI_STATUS_PARITY; -- conf_data |= PCI_STATUS_DEVSEL_MEDIUM; -+ cfg |= PCI_STATUS_PARITY; -+ cfg |= PCI_STATUS_DEVSEL_MEDIUM; - break; - case PCI_CLASS_REVISION: - _rdmsr(USB_MSR_REG(USB_CAP), &hi, &lo); -- conf_data = lo & 0x000000ff; -- conf_data |= (CS5536_OHCI_CLASS_CODE << 8); -+ cfg = lo & 0x000000ff; -+ cfg |= (CS5536_OHCI_CLASS_CODE << 8); - break; - case PCI_CACHE_LINE_SIZE: -- conf_data = -- CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, -- PCI_NORMAL_LATENCY_TIMER); -+ cfg = CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, -+ PCI_NORMAL_LATENCY_TIMER); - break; - case PCI_BAR0_REG: - _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); - if (lo & SOFT_BAR_OHCI_FLAG) { -- conf_data = CS5536_OHCI_RANGE | -+ cfg = CS5536_OHCI_RANGE | - PCI_BASE_ADDRESS_SPACE_MEMORY; - lo &= ~SOFT_BAR_OHCI_FLAG; - _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); - } else { - _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo); -- conf_data = lo & 0xffffff00; -- conf_data &= ~0x0000000f; /* 32bit mem */ -+ cfg = lo & 0xffffff00; -+ cfg &= ~0x0000000f; /* 32bit mem */ - } - break; - case PCI_CARDBUS_CIS: -- conf_data = PCI_CARDBUS_CIS_POINTER; -+ cfg = PCI_CARDBUS_CIS_POINTER; - break; - case PCI_SUBSYSTEM_VENDOR_ID: -- conf_data = -- CFG_PCI_VENDOR_ID(CS5536_OHCI_SUB_ID, CS5536_SUB_VENDOR_ID); -+ cfg = CFG_PCI_VENDOR_ID(CS5536_OHCI_SUB_ID, -+ CS5536_SUB_VENDOR_ID); - break; - case PCI_ROM_ADDRESS: -- conf_data = PCI_EXPANSION_ROM_BAR; -+ cfg = PCI_EXPANSION_ROM_BAR; - break; - case PCI_CAPABILITY_LIST: -- conf_data = PCI_CAPLIST_USB_POINTER; -+ cfg = PCI_CAPLIST_USB_POINTER; - break; - case PCI_INTERRUPT_LINE: -- conf_data = -- CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR); -+ cfg = CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR); - break; - case PCI_OHCI_INT_REG: - _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo); - if ((lo & 0x00000f00) == CS5536_USB_INTR) -- conf_data = 1; -+ cfg = 1; - break; - default: - break; - } - -- return conf_data; -+ return cfg; - } -diff -Nur linux-2.6.36.orig/arch/mips/loongson/common/mtd.c linux-2.6.36/arch/mips/loongson/common/mtd.c ---- linux-2.6.36.orig/arch/mips/loongson/common/mtd.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/loongson/common/mtd.c 2010-12-17 23:12:59.000000000 +0100 -@@ -0,0 +1,91 @@ -+/* -+ * Driver for flushing/dumping ROM of PMON on loongson family machines -+ * -+ * Copyright (C) 2008-2009 Lemote Inc. -+ * Author: Yan Hua -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include -+ -+#define FLASH_PHYS_ADDR LOONGSON_BOOT_BASE -+#define FLASH_SIZE 0x080000 -+ -+#define FLASH_PARTITION0_ADDR 0x00000000 -+#define FLASH_PARTITION0_SIZE 0x00080000 -+ -+struct map_info flash_map = { -+ .name = "flash device", -+ .size = FLASH_SIZE, -+ .bankwidth = 1, -+}; -+ -+struct mtd_partition flash_parts[] = { -+ { -+ .name = "Bootloader", -+ .offset = FLASH_PARTITION0_ADDR, -+ .size = FLASH_PARTITION0_SIZE}, -+}; -+ -+#define PARTITION_COUNT ARRAY_SIZE(flash_parts) -+ -+static struct mtd_info *mymtd; -+ -+int __init init_flash(void) -+{ -+ printk(KERN_NOTICE "flash device: %x at %x\n", -+ FLASH_SIZE, FLASH_PHYS_ADDR); -+ -+ flash_map.phys = FLASH_PHYS_ADDR; -+ flash_map.virt = ioremap(FLASH_PHYS_ADDR, FLASH_SIZE); -+ -+ if (!flash_map.virt) { -+ printk(KERN_NOTICE "Failed to ioremap\n"); -+ return -EIO; -+ } -+ -+ simple_map_init(&flash_map); -+ -+ mymtd = do_map_probe("cfi_probe", &flash_map); -+ if (mymtd) { -+ add_mtd_partitions(mymtd, flash_parts, PARTITION_COUNT); -+ printk(KERN_NOTICE "pmon flash device initialized\n"); -+ return 0; -+ } -+ -+ iounmap((void *)flash_map.virt); -+ return -ENXIO; -+} -+ -+static void __exit cleanup_flash(void) -+{ -+ if (mymtd) { -+ del_mtd_partitions(mymtd); -+ map_destroy(mymtd); -+ } -+ if (flash_map.virt) { -+ iounmap((void *)flash_map.virt); -+ flash_map.virt = 0; -+ } -+} -+ -+module_init(init_flash); -+module_exit(cleanup_flash); -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Yanhua "); -+MODULE_DESCRIPTION("MTD driver for pmon flushing/dumping"); -diff -Nur linux-2.6.36.orig/arch/mips/loongson/lemote-2f/Makefile linux-2.6.36/arch/mips/loongson/lemote-2f/Makefile ---- linux-2.6.36.orig/arch/mips/loongson/lemote-2f/Makefile 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/arch/mips/loongson/lemote-2f/Makefile 2010-12-17 23:12:59.000000000 +0100 -@@ -2,7 +2,7 @@ - # Makefile for lemote loongson2f family machines - # - --obj-y += machtype.o irq.o reset.o ec_kb3310b.o -+obj-y += machtype.o irq.o reset.o ec_kb3310b.o platform.o - - # - # Suspend Support -diff -Nur linux-2.6.36.orig/arch/mips/loongson/lemote-2f/ec_kb3310b.c linux-2.6.36/arch/mips/loongson/lemote-2f/ec_kb3310b.c ---- linux-2.6.36.orig/arch/mips/loongson/lemote-2f/ec_kb3310b.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/arch/mips/loongson/lemote-2f/ec_kb3310b.c 2010-12-17 23:12:59.000000000 +0100 -@@ -14,7 +14,7 @@ - #include - #include - --#include "ec_kb3310b.h" -+#include - - static DEFINE_SPINLOCK(index_access_lock); - static DEFINE_SPINLOCK(port_access_lock); -@@ -78,12 +78,9 @@ - spin_unlock_irqrestore(&port_access_lock, flags); - - if (timeout <= 0) { -- printk(KERN_ERR "%s: deadable error : timeout...\n", __func__); -+ pr_err("%s: deadable error : timeout...\n", __func__); - ret = -EINVAL; -- } else -- printk(KERN_INFO -- "(%x/%d)ec issued command %d status : 0x%x\n", -- timeout, EC_CMD_TIMEOUT - timeout, cmd, status); -+ } - - return ret; - } -@@ -118,8 +115,7 @@ - udelay(EC_REG_DELAY); - } - if (timeout <= 0) { -- pr_info("%s: get event number timeout.\n", __func__); -- -+ pr_err("%s: get event number timeout.\n", __func__); - return -EINVAL; - } - value = inb(EC_DAT_PORT); -diff -Nur linux-2.6.36.orig/arch/mips/loongson/lemote-2f/ec_kb3310b.h linux-2.6.36/arch/mips/loongson/lemote-2f/ec_kb3310b.h ---- linux-2.6.36.orig/arch/mips/loongson/lemote-2f/ec_kb3310b.h 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/arch/mips/loongson/lemote-2f/ec_kb3310b.h 1970-01-01 01:00:00.000000000 +0100 -@@ -1,188 +0,0 @@ --/* -- * KB3310B Embedded Controller -- * -- * Copyright (C) 2008 Lemote Inc. -- * Author: liujl , 2008-03-14 -- * -- * This program is free software; you can redistribute it and/or modify -- * it under the terms of the GNU General Public License as published by -- * the Free Software Foundation; either version 2 of the License, or -- * (at your option) any later version. -- */ -- --#ifndef _EC_KB3310B_H --#define _EC_KB3310B_H -- --extern unsigned char ec_read(unsigned short addr); --extern void ec_write(unsigned short addr, unsigned char val); --extern int ec_query_seq(unsigned char cmd); --extern int ec_query_event_num(void); --extern int ec_get_event_num(void); -- --typedef int (*sci_handler) (int status); --extern sci_handler yeeloong_report_lid_status; -- --#define SCI_IRQ_NUM 0x0A -- --/* -- * The following registers are determined by the EC index configuration. -- * 1, fill the PORT_HIGH as EC register high part. -- * 2, fill the PORT_LOW as EC register low part. -- * 3, fill the PORT_DATA as EC register write data or get the data from it. -- */ --#define EC_IO_PORT_HIGH 0x0381 --#define EC_IO_PORT_LOW 0x0382 --#define EC_IO_PORT_DATA 0x0383 -- --/* -- * EC delay time is 500us for register and status access -- */ --#define EC_REG_DELAY 500 /* unit : us */ --#define EC_CMD_TIMEOUT 0x1000 -- --/* -- * EC access port for SCI communication -- */ --#define EC_CMD_PORT 0x66 --#define EC_STS_PORT 0x66 --#define EC_DAT_PORT 0x62 --#define CMD_INIT_IDLE_MODE 0xdd --#define CMD_EXIT_IDLE_MODE 0xdf --#define CMD_INIT_RESET_MODE 0xd8 --#define CMD_REBOOT_SYSTEM 0x8c --#define CMD_GET_EVENT_NUM 0x84 --#define CMD_PROGRAM_PIECE 0xda -- --/* temperature & fan registers */ --#define REG_TEMPERATURE_VALUE 0xF458 --#define REG_FAN_AUTO_MAN_SWITCH 0xF459 --#define BIT_FAN_AUTO 0 --#define BIT_FAN_MANUAL 1 --#define REG_FAN_CONTROL 0xF4D2 --#define BIT_FAN_CONTROL_ON (1 << 0) --#define BIT_FAN_CONTROL_OFF (0 << 0) --#define REG_FAN_STATUS 0xF4DA --#define BIT_FAN_STATUS_ON (1 << 0) --#define BIT_FAN_STATUS_OFF (0 << 0) --#define REG_FAN_SPEED_HIGH 0xFE22 --#define REG_FAN_SPEED_LOW 0xFE23 --#define REG_FAN_SPEED_LEVEL 0xF4CC --/* fan speed divider */ --#define FAN_SPEED_DIVIDER 480000 /* (60*1000*1000/62.5/2)*/ -- --/* battery registers */ --#define REG_BAT_DESIGN_CAP_HIGH 0xF77D --#define REG_BAT_DESIGN_CAP_LOW 0xF77E --#define REG_BAT_FULLCHG_CAP_HIGH 0xF780 --#define REG_BAT_FULLCHG_CAP_LOW 0xF781 --#define REG_BAT_DESIGN_VOL_HIGH 0xF782 --#define REG_BAT_DESIGN_VOL_LOW 0xF783 --#define REG_BAT_CURRENT_HIGH 0xF784 --#define REG_BAT_CURRENT_LOW 0xF785 --#define REG_BAT_VOLTAGE_HIGH 0xF786 --#define REG_BAT_VOLTAGE_LOW 0xF787 --#define REG_BAT_TEMPERATURE_HIGH 0xF788 --#define REG_BAT_TEMPERATURE_LOW 0xF789 --#define REG_BAT_RELATIVE_CAP_HIGH 0xF492 --#define REG_BAT_RELATIVE_CAP_LOW 0xF493 --#define REG_BAT_VENDOR 0xF4C4 --#define FLAG_BAT_VENDOR_SANYO 0x01 --#define FLAG_BAT_VENDOR_SIMPLO 0x02 --#define REG_BAT_CELL_COUNT 0xF4C6 --#define FLAG_BAT_CELL_3S1P 0x03 --#define FLAG_BAT_CELL_3S2P 0x06 --#define REG_BAT_CHARGE 0xF4A2 --#define FLAG_BAT_CHARGE_DISCHARGE 0x01 --#define FLAG_BAT_CHARGE_CHARGE 0x02 --#define FLAG_BAT_CHARGE_ACPOWER 0x00 --#define REG_BAT_STATUS 0xF4B0 --#define BIT_BAT_STATUS_LOW (1 << 5) --#define BIT_BAT_STATUS_DESTROY (1 << 2) --#define BIT_BAT_STATUS_FULL (1 << 1) --#define BIT_BAT_STATUS_IN (1 << 0) --#define REG_BAT_CHARGE_STATUS 0xF4B1 --#define BIT_BAT_CHARGE_STATUS_OVERTEMP (1 << 2) --#define BIT_BAT_CHARGE_STATUS_PRECHG (1 << 1) --#define REG_BAT_STATE 0xF482 --#define BIT_BAT_STATE_CHARGING (1 << 1) --#define BIT_BAT_STATE_DISCHARGING (1 << 0) --#define REG_BAT_POWER 0xF440 --#define BIT_BAT_POWER_S3 (1 << 2) --#define BIT_BAT_POWER_ON (1 << 1) --#define BIT_BAT_POWER_ACIN (1 << 0) -- --/* other registers */ --/* Audio: rd/wr */ --#define REG_AUDIO_VOLUME 0xF46C --#define REG_AUDIO_MUTE 0xF4E7 --#define REG_AUDIO_BEEP 0xF4D0 --/* USB port power or not: rd/wr */ --#define REG_USB0_FLAG 0xF461 --#define REG_USB1_FLAG 0xF462 --#define REG_USB2_FLAG 0xF463 --#define BIT_USB_FLAG_ON 1 --#define BIT_USB_FLAG_OFF 0 --/* LID */ --#define REG_LID_DETECT 0xF4BD --#define BIT_LID_DETECT_ON 1 --#define BIT_LID_DETECT_OFF 0 --/* CRT */ --#define REG_CRT_DETECT 0xF4AD --#define BIT_CRT_DETECT_PLUG 1 --#define BIT_CRT_DETECT_UNPLUG 0 --/* LCD backlight brightness adjust: 9 levels */ --#define REG_DISPLAY_BRIGHTNESS 0xF4F5 --/* Black screen Status */ --#define BIT_DISPLAY_LCD_ON 1 --#define BIT_DISPLAY_LCD_OFF 0 --/* LCD backlight control: off/restore */ --#define REG_BACKLIGHT_CTRL 0xF7BD --#define BIT_BACKLIGHT_ON 1 --#define BIT_BACKLIGHT_OFF 0 --/* Reset the machine auto-clear: rd/wr */ --#define REG_RESET 0xF4EC --#define BIT_RESET_ON 1 --/* Light the led: rd/wr */ --#define REG_LED 0xF4C8 --#define BIT_LED_RED_POWER (1 << 0) --#define BIT_LED_ORANGE_POWER (1 << 1) --#define BIT_LED_GREEN_CHARGE (1 << 2) --#define BIT_LED_RED_CHARGE (1 << 3) --#define BIT_LED_NUMLOCK (1 << 4) --/* Test led mode, all led on/off */ --#define REG_LED_TEST 0xF4C2 --#define BIT_LED_TEST_IN 1 --#define BIT_LED_TEST_OUT 0 --/* Camera on/off */ --#define REG_CAMERA_STATUS 0xF46A --#define BIT_CAMERA_STATUS_ON 1 --#define BIT_CAMERA_STATUS_OFF 0 --#define REG_CAMERA_CONTROL 0xF7B7 --#define BIT_CAMERA_CONTROL_OFF 0 --#define BIT_CAMERA_CONTROL_ON 1 --/* Wlan Status */ --#define REG_WLAN 0xF4FA --#define BIT_WLAN_ON 1 --#define BIT_WLAN_OFF 0 --#define REG_DISPLAY_LCD 0xF79F -- --/* SCI Event Number from EC */ --enum { -- EVENT_LID = 0x23, /* LID open/close */ -- EVENT_DISPLAY_TOGGLE, /* Fn+F3 for display switch */ -- EVENT_SLEEP, /* Fn+F1 for entering sleep mode */ -- EVENT_OVERTEMP, /* Over-temperature happened */ -- EVENT_CRT_DETECT, /* CRT is connected */ -- EVENT_CAMERA, /* Camera on/off */ -- EVENT_USB_OC2, /* USB2 Over Current occurred */ -- EVENT_USB_OC0, /* USB0 Over Current occurred */ -- EVENT_BLACK_SCREEN, /* Turn on/off backlight */ -- EVENT_AUDIO_MUTE, /* Mute on/off */ -- EVENT_DISPLAY_BRIGHTNESS,/* LCD backlight brightness adjust */ -- EVENT_AC_BAT, /* AC & Battery relative issue */ -- EVENT_AUDIO_VOLUME, /* Volume adjust */ -- EVENT_WLAN, /* Wlan on/off */ -- EVENT_END --}; -- --#endif /* !_EC_KB3310B_H */ -diff -Nur linux-2.6.36.orig/arch/mips/loongson/lemote-2f/platform.c linux-2.6.36/arch/mips/loongson/lemote-2f/platform.c ---- linux-2.6.36.orig/arch/mips/loongson/lemote-2f/platform.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/arch/mips/loongson/lemote-2f/platform.c 2010-12-17 23:12:59.000000000 +0100 -@@ -0,0 +1,48 @@ -+/* -+ * Copyright (C) 2009 Lemote Inc. -+ * Author: Wu Zhangjin, wuzhangjin@gmail.com -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ */ -+ -+#include -+#include -+ -+#include -+ -+static struct platform_device yeeloong_pdev = { -+ .name = "yeeloong_laptop", -+ .id = -1, -+}; -+ -+static struct platform_device lynloong_pdev = { -+ .name = "lynloong_pc", -+ .id = -1, -+}; -+ -+static int __init lemote2f_platform_init(void) -+{ -+ struct platform_device *pdev = NULL; -+ -+ switch (mips_machtype) { -+ case MACH_LEMOTE_YL2F89: -+ pdev = &yeeloong_pdev; -+ break; -+ case MACH_LEMOTE_LL2F: -+ pdev = &lynloong_pdev; -+ break; -+ default: -+ break; -+ -+ } -+ -+ if (pdev != NULL) -+ return platform_device_register(pdev); -+ -+ return -ENODEV; -+} -+ -+arch_initcall(lemote2f_platform_init); -diff -Nur linux-2.6.36.orig/arch/mips/loongson/lemote-2f/pm.c linux-2.6.36/arch/mips/loongson/lemote-2f/pm.c ---- linux-2.6.36.orig/arch/mips/loongson/lemote-2f/pm.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/arch/mips/loongson/lemote-2f/pm.c 2010-12-17 23:12:59.000000000 +0100 -@@ -23,7 +23,7 @@ - #include - - #include --#include "ec_kb3310b.h" -+#include - - #define I8042_KBD_IRQ 1 - #define I8042_CTR_KBDINT 0x01 -@@ -100,7 +100,7 @@ - if (irq < 0) - return 0; - -- printk(KERN_INFO "%s: irq = %d\n", __func__, irq); -+ pr_info("%s: irq = %d\n", __func__, irq); - - if (irq == I8042_KBD_IRQ) - return 1; -diff -Nur linux-2.6.36.orig/arch/mips/loongson/lemote-2f/reset.c linux-2.6.36/arch/mips/loongson/lemote-2f/reset.c ---- linux-2.6.36.orig/arch/mips/loongson/lemote-2f/reset.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/arch/mips/loongson/lemote-2f/reset.c 2010-12-17 23:12:59.000000000 +0100 -@@ -20,7 +20,7 @@ - #include - - #include --#include "ec_kb3310b.h" -+#include - - static void reset_cpu(void) - { -diff -Nur linux-2.6.36.orig/arch/mips/mm/dma-default.c linux-2.6.36/arch/mips/mm/dma-default.c ---- linux-2.6.36.orig/arch/mips/mm/dma-default.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/arch/mips/mm/dma-default.c 2010-12-17 23:12:59.000000000 +0100 -@@ -380,3 +380,16 @@ - } - - EXPORT_SYMBOL(dma_cache_sync); -+ -+int __weak dma_mmap_coherent(struct device *dev, struct vm_area_struct *vma, -+ void *cpu_addr, dma_addr_t handle, size_t size) -+{ -+ struct page *pg; -+ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); -+ cpu_addr = (void *)dma_addr_to_virt(dev, handle); -+ pg = virt_to_page(cpu_addr); -+ return remap_pfn_range(vma, vma->vm_start, -+ page_to_pfn(pg) + vma->vm_pgoff, -+ size, vma->vm_page_prot); -+} -+EXPORT_SYMBOL(dma_mmap_coherent); -diff -Nur linux-2.6.36.orig/drivers/ide/ide-iops.c linux-2.6.36/drivers/ide/ide-iops.c ---- linux-2.6.36.orig/drivers/ide/ide-iops.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/drivers/ide/ide-iops.c 2010-12-17 23:12:59.000000000 +0100 -@@ -27,6 +27,8 @@ - #include - #include - -+#include -+ - void SELECT_MASK(ide_drive_t *drive, int mask) - { - const struct ide_port_ops *port_ops = drive->hwif->port_ops; -@@ -300,6 +302,9 @@ - { - const char **list, *m = (char *)&drive->id[ATA_ID_PROD]; - -+ if (mips_machtype != MACH_LEMOTE_YL2F89) -+ return; -+ - for (list = nien_quirk_list; *list != NULL; list++) - if (strstr(m, *list) != NULL) { - drive->dev_flags |= IDE_DFLAG_NIEN_QUIRK; -diff -Nur linux-2.6.36.orig/drivers/platform/Kconfig linux-2.6.36/drivers/platform/Kconfig ---- linux-2.6.36.orig/drivers/platform/Kconfig 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/drivers/platform/Kconfig 2010-12-17 23:12:59.000000000 +0100 -@@ -1,3 +1,7 @@ - if X86 - source "drivers/platform/x86/Kconfig" - endif -+ -+if MIPS -+source "drivers/platform/mips/Kconfig" -+endif -diff -Nur linux-2.6.36.orig/drivers/platform/Makefile linux-2.6.36/drivers/platform/Makefile ---- linux-2.6.36.orig/drivers/platform/Makefile 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/drivers/platform/Makefile 2010-12-17 23:12:59.000000000 +0100 -@@ -3,3 +3,4 @@ - # - - obj-$(CONFIG_X86) += x86/ -+obj-$(CONFIG_MIPS) += mips/ -diff -Nur linux-2.6.36.orig/drivers/platform/mips/Kconfig linux-2.6.36/drivers/platform/mips/Kconfig ---- linux-2.6.36.orig/drivers/platform/mips/Kconfig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/drivers/platform/mips/Kconfig 2010-12-17 23:12:59.000000000 +0100 -@@ -0,0 +1,43 @@ -+# -+# MIPS Platform Specific Drivers -+# -+ -+menuconfig MIPS_PLATFORM_DEVICES -+ bool "MIPS Platform Specific Device Drivers" -+ default y -+ help -+ Say Y here to get to see options for device drivers of various -+ MIPS platforms, including vendor-specific netbook/laptop/pc extension -+ drivers. This option alone does not add any kernel code. -+ -+ If you say N, all options in this submenu will be skipped and disabled. -+ -+if MIPS_PLATFORM_DEVICES -+ -+config LEMOTE_YEELOONG2F -+ tristate "Lemote YeeLoong Laptop" -+ depends on LEMOTE_MACH2F -+ select BACKLIGHT_CLASS_DEVICE -+ select POWER_SUPPLY -+ select HWMON -+ select VIDEO_OUTPUT_CONTROL -+ select INPUT_SPARSEKMAP -+ depends on INPUT -+ help -+ YeeLoong netbook is a mini laptop made by Lemote, which is basically -+ compatible to FuLoong2F mini PC, but it has an extra Embedded -+ Controller(kb3310b) for battery, hotkey, backlight, temperature and -+ fan management. -+ -+config LEMOTE_LYNLOONG2F -+ tristate "Lemote LynLoong PC" -+ depends on LEMOTE_MACH2F -+ select BACKLIGHT_CLASS_DEVICE -+ select VIDEO_OUTPUT_CONTROL -+ help -+ LynLoong PC is an AllINONE machine made by Lemote, which is basically -+ compatible to FuLoong2F Mini PC, the only difference is that it has a -+ size-fixed screen: 1360x768 with sisfb video driver. and also, it has -+ its own specific suspend support. -+ -+endif # MIPS_PLATFORM_DEVICES -diff -Nur linux-2.6.36.orig/drivers/platform/mips/Makefile linux-2.6.36/drivers/platform/mips/Makefile ---- linux-2.6.36.orig/drivers/platform/mips/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/drivers/platform/mips/Makefile 2010-12-17 23:12:59.000000000 +0100 -@@ -0,0 +1,7 @@ -+# -+# Makefile for MIPS Platform-Specific Drivers -+# -+ -+obj-$(CONFIG_LEMOTE_YEELOONG2F) += yeeloong_laptop.o -+ -+obj-$(CONFIG_LEMOTE_LYNLOONG2F) += lynloong_pc.o -diff -Nur linux-2.6.36.orig/drivers/platform/mips/lynloong_pc.c linux-2.6.36/drivers/platform/mips/lynloong_pc.c ---- linux-2.6.36.orig/drivers/platform/mips/lynloong_pc.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/drivers/platform/mips/lynloong_pc.c 2010-12-17 23:12:59.000000000 +0100 -@@ -0,0 +1,513 @@ -+/* -+ * Driver for LynLoong PC extras -+ * -+ * Copyright (C) 2009 Lemote Inc. -+ * Author: Wu Zhangjin , Xiang Yu -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include /* for backlight subdriver */ -+#include -+#include /* for video output subdriver */ -+#include /* for suspend support */ -+ -+#include -+#include -+ -+#include -+ -+static u32 gpio_base, mfgpt_base; -+ -+static void set_gpio_reg_high(int gpio, int reg) -+{ -+ u32 val; -+ -+ val = inl(gpio_base + reg); -+ val |= (1 << gpio); -+ val &= ~(1 << (16 + gpio)); -+ outl(val, gpio_base + reg); -+ mmiowb(); -+} -+ -+static void set_gpio_reg_low(int gpio, int reg) -+{ -+ u32 val; -+ -+ val = inl(gpio_base + reg); -+ val |= (1 << (16 + gpio)); -+ val &= ~(1 << gpio); -+ outl(val, gpio_base + reg); -+ mmiowb(); -+} -+ -+static void set_gpio_output_low(int gpio) -+{ -+ set_gpio_reg_high(gpio, GPIOL_OUT_EN); -+ set_gpio_reg_low(gpio, GPIOL_OUT_VAL); -+} -+ -+static void set_gpio_output_high(int gpio) -+{ -+ set_gpio_reg_high(gpio, GPIOL_OUT_EN); -+ set_gpio_reg_high(gpio, GPIOL_OUT_VAL); -+} -+ -+/* backlight subdriver */ -+ -+#define MAX_BRIGHTNESS 100 -+#define DEFAULT_BRIGHTNESS 50 -+#define MIN_BRIGHTNESS 0 -+static unsigned int level; -+ -+DEFINE_SPINLOCK(backlight_lock); -+/* Tune the brightness */ -+static void setup_mfgpt2(void) -+{ -+ unsigned long flags; -+ -+ spin_lock_irqsave(&backlight_lock, flags); -+ -+ /* Set MFGPT2 comparator 1,2 */ -+ outw(MAX_BRIGHTNESS-level, MFGPT2_CMP1); -+ outw(MAX_BRIGHTNESS, MFGPT2_CMP2); -+ /* Clear MFGPT2 UP COUNTER */ -+ outw(0, MFGPT2_CNT); -+ /* Enable counter, compare mode, 32k */ -+ outw(0x8280, MFGPT2_SETUP); -+ -+ spin_unlock_irqrestore(&backlight_lock, flags); -+} -+ -+static int lynloong_set_brightness(struct backlight_device *bd) -+{ -+ level = (bd->props.fb_blank == FB_BLANK_UNBLANK && -+ bd->props.power == FB_BLANK_UNBLANK) ? -+ bd->props.brightness : 0; -+ -+ if (level > MAX_BRIGHTNESS) -+ level = MAX_BRIGHTNESS; -+ else if (level < MIN_BRIGHTNESS) -+ level = MIN_BRIGHTNESS; -+ -+ setup_mfgpt2(); -+ -+ return 0; -+} -+ -+static int lynloong_get_brightness(struct backlight_device *bd) -+{ -+ return level; -+} -+ -+static struct backlight_ops backlight_ops = { -+ .get_brightness = lynloong_get_brightness, -+ .update_status = lynloong_set_brightness, -+}; -+ -+static struct backlight_device *lynloong_backlight_dev; -+ -+static int lynloong_backlight_init(void) -+{ -+ int ret; -+ u32 hi; -+ struct backlight_properties props; -+ -+ /* Get gpio_base */ -+ _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_GPIO), &hi, &gpio_base); -+ /* Get mfgpt_base */ -+ _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), &hi, &mfgpt_base); -+ /* Get gpio_base */ -+ _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_GPIO), &hi, &gpio_base); -+ -+ /* Select for mfgpt */ -+ set_gpio_reg_high(7, GPIOL_OUT_AUX1_SEL); -+ /* Enable brightness controlling */ -+ set_gpio_output_high(7); -+ -+ memset(&props, 0, sizeof(struct backlight_properties)); -+ props.max_brightness = MAX_BRIGHTNESS; -+ lynloong_backlight_dev = backlight_device_register("backlight0", NULL, -+ NULL, &backlight_ops, &props); -+ -+ if (IS_ERR(lynloong_backlight_dev)) { -+ ret = PTR_ERR(lynloong_backlight_dev); -+ return ret; -+ } -+ -+ lynloong_backlight_dev->props.brightness = DEFAULT_BRIGHTNESS; -+ backlight_update_status(lynloong_backlight_dev); -+ -+ return 0; -+} -+ -+static void lynloong_backlight_exit(void) -+{ -+ if (lynloong_backlight_dev) { -+ backlight_device_unregister(lynloong_backlight_dev); -+ lynloong_backlight_dev = NULL; -+ } -+ /* Disable brightness controlling */ -+ set_gpio_output_low(7); -+} -+ -+/* video output driver */ -+static int vo_status = 1; -+ -+static int lcd_video_output_get(struct output_device *od) -+{ -+ return vo_status; -+} -+ -+static int lcd_video_output_set(struct output_device *od) -+{ -+ int i; -+ unsigned long status; -+ -+ status = !!od->request_state; -+ -+ if (status == 0) { -+ /* Set the current status as off */ -+ vo_status = 0; -+ /* Turn off the backlight */ -+ set_gpio_output_low(11); -+ for (i = 0; i < 0x500; i++) -+ delay(); -+ /* Turn off the LCD */ -+ set_gpio_output_high(8); -+ } else { -+ /* Turn on the LCD */ -+ set_gpio_output_low(8); -+ for (i = 0; i < 0x500; i++) -+ delay(); -+ /* Turn on the backlight */ -+ set_gpio_output_high(11); -+ /* Set the current status as on */ -+ vo_status = 1; -+ } -+ -+ return 0; -+} -+ -+static struct output_properties lcd_output_properties = { -+ .set_state = lcd_video_output_set, -+ .get_status = lcd_video_output_get, -+}; -+ -+static struct output_device *lcd_output_dev; -+ -+static void lynloong_lcd_vo_set(int status) -+{ -+ lcd_output_dev->request_state = status; -+ lcd_video_output_set(lcd_output_dev); -+} -+ -+static int lynloong_vo_init(void) -+{ -+ int ret; -+ -+ /* Register video output device: lcd */ -+ lcd_output_dev = video_output_register("LCD", NULL, NULL, -+ &lcd_output_properties); -+ -+ if (IS_ERR(lcd_output_dev)) { -+ ret = PTR_ERR(lcd_output_dev); -+ lcd_output_dev = NULL; -+ return ret; -+ } -+ /* Ensure LCD is on by default */ -+ lynloong_lcd_vo_set(1); -+ -+ return 0; -+} -+ -+static void lynloong_vo_exit(void) -+{ -+ if (lcd_output_dev) { -+ video_output_unregister(lcd_output_dev); -+ lcd_output_dev = NULL; -+ } -+} -+ -+/* suspend support */ -+ -+#ifdef CONFIG_PM -+ -+static u32 smb_base; -+ -+/* I2C operations */ -+ -+static int i2c_wait(void) -+{ -+ char c; -+ int i; -+ -+ udelay(1000); -+ for (i = 0; i < 20; i++) { -+ c = inb(smb_base | SMB_STS); -+ if (c & (SMB_STS_BER | SMB_STS_NEGACK)) -+ return -1; -+ if (c & SMB_STS_SDAST) -+ return 0; -+ udelay(100); -+ } -+ return -2; -+} -+ -+static void i2c_read_single(int addr, int regNo, char *value) -+{ -+ unsigned char c; -+ -+ /* Start condition */ -+ c = inb(smb_base | SMB_CTRL1); -+ outb(c | SMB_CTRL1_START, smb_base | SMB_CTRL1); -+ i2c_wait(); -+ -+ /* Send slave address */ -+ outb(addr & 0xfe, smb_base | SMB_SDA); -+ i2c_wait(); -+ -+ /* Acknowledge smbus */ -+ c = inb(smb_base | SMB_CTRL1); -+ outb(c | SMB_CTRL1_ACK, smb_base | SMB_CTRL1); -+ -+ /* Send register index */ -+ outb(regNo, smb_base | SMB_SDA); -+ i2c_wait(); -+ -+ /* Acknowledge smbus */ -+ c = inb(smb_base | SMB_CTRL1); -+ outb(c | SMB_CTRL1_ACK, smb_base | SMB_CTRL1); -+ -+ /* Start condition again */ -+ c = inb(smb_base | SMB_CTRL1); -+ outb(c | SMB_CTRL1_START, smb_base | SMB_CTRL1); -+ i2c_wait(); -+ -+ /* Send salve address again */ -+ outb(1 | addr, smb_base | SMB_SDA); -+ i2c_wait(); -+ -+ /* Acknowledge smbus */ -+ c = inb(smb_base | SMB_CTRL1); -+ outb(c | SMB_CTRL1_ACK, smb_base | SMB_CTRL1); -+ -+ /* Read data */ -+ *value = inb(smb_base | SMB_SDA); -+ -+ /* Stop condition */ -+ outb(SMB_CTRL1_STOP, smb_base | SMB_CTRL1); -+ i2c_wait(); -+} -+ -+static void i2c_write_single(int addr, int regNo, char value) -+{ -+ unsigned char c; -+ -+ /* Start condition */ -+ c = inb(smb_base | SMB_CTRL1); -+ outb(c | SMB_CTRL1_START, smb_base | SMB_CTRL1); -+ i2c_wait(); -+ /* Send slave address */ -+ outb(addr & 0xfe, smb_base | SMB_SDA); -+ i2c_wait();; -+ -+ /* Send register index */ -+ outb(regNo, smb_base | SMB_SDA); -+ i2c_wait(); -+ -+ /* Write data */ -+ outb(value, smb_base | SMB_SDA); -+ i2c_wait(); -+ /* Stop condition */ -+ outb(SMB_CTRL1_STOP, smb_base | SMB_CTRL1); -+ i2c_wait(); -+} -+ -+static void stop_clock(int clk_reg, int clk_sel) -+{ -+ u8 value; -+ -+ i2c_read_single(0xd3, clk_reg, &value); -+ value &= ~(1 << clk_sel); -+ i2c_write_single(0xd2, clk_reg, value); -+} -+ -+static void enable_clock(int clk_reg, int clk_sel) -+{ -+ u8 value; -+ -+ i2c_read_single(0xd3, clk_reg, &value); -+ value |= (1 << clk_sel); -+ i2c_write_single(0xd2, clk_reg, value); -+} -+ -+static char cached_clk_freq; -+static char cached_pci_fixed_freq; -+ -+static void decrease_clk_freq(void) -+{ -+ char value; -+ -+ i2c_read_single(0xd3, 1, &value); -+ cached_clk_freq = value; -+ -+ /* Select frequency by software */ -+ value |= (1 << 1); -+ /* CPU, 3V66, PCI : 100, 66, 33(1) */ -+ value |= (1 << 2); -+ i2c_write_single(0xd2, 1, value); -+ -+ /* Cache the pci frequency */ -+ i2c_read_single(0xd3, 14, &value); -+ cached_pci_fixed_freq = value; -+ -+ /* Enable PCI fix mode */ -+ value |= (1 << 5); -+ /* 3V66, PCI : 64MHz, 32MHz */ -+ value |= (1 << 3); -+ i2c_write_single(0xd2, 14, value); -+ -+} -+ -+static void resume_clk_freq(void) -+{ -+ i2c_write_single(0xd2, 1, cached_clk_freq); -+ i2c_write_single(0xd2, 14, cached_pci_fixed_freq); -+} -+ -+static void stop_clocks(void) -+{ -+ /* CPU Clock Register */ -+ stop_clock(2, 5); /* not used */ -+ stop_clock(2, 6); /* not used */ -+ stop_clock(2, 7); /* not used */ -+ -+ /* PCI Clock Register */ -+ stop_clock(3, 1); /* 8100 */ -+ stop_clock(3, 5); /* SIS */ -+ stop_clock(3, 0); /* not used */ -+ stop_clock(3, 6); /* not used */ -+ -+ /* PCI 48M Clock Register */ -+ stop_clock(4, 6); /* USB grounding */ -+ stop_clock(4, 5); /* REF(5536_14M) */ -+ -+ /* 3V66 Control Register */ -+ stop_clock(5, 0); /* VCH_CLK..., grounding */ -+} -+ -+static void enable_clocks(void) -+{ -+ enable_clock(3, 1); /* 8100 */ -+ enable_clock(3, 5); /* SIS */ -+ -+ enable_clock(4, 6); -+ enable_clock(4, 5); /* REF(5536_14M) */ -+ -+ enable_clock(5, 0); /* VCH_CLOCK, grounding */ -+} -+ -+static int lynloong_suspend(struct device *dev) -+{ -+ /* Disable AMP */ -+ set_gpio_output_high(6); -+ /* Turn off LCD */ -+ lynloong_lcd_vo_set(0); -+ -+ /* Stop the clocks of some devices */ -+ stop_clocks(); -+ -+ /* Decrease the external clock frequency */ -+ decrease_clk_freq(); -+ -+ return 0; -+} -+ -+static int lynloong_resume(struct device *dev) -+{ -+ /* Turn on the LCD */ -+ lynloong_lcd_vo_set(1); -+ -+ /* Resume clock frequency, enable the relative clocks */ -+ resume_clk_freq(); -+ enable_clocks(); -+ -+ /* Enable AMP */ -+ set_gpio_output_low(6); -+ -+ return 0; -+} -+ -+static const SIMPLE_DEV_PM_OPS(lynloong_pm_ops, lynloong_suspend, -+ lynloong_resume); -+#endif /* !CONFIG_PM */ -+ -+static struct platform_device_id platform_device_ids[] = { -+ { -+ .name = "lynloong_pc", -+ }, -+ {} -+}; -+ -+MODULE_DEVICE_TABLE(platform, platform_device_ids); -+ -+static struct platform_driver platform_driver = { -+ .driver = { -+ .name = "lynloong_pc", -+ .owner = THIS_MODULE, -+#ifdef CONFIG_PM -+ .pm = &lynloong_pm_ops, -+#endif -+ }, -+ .id_table = platform_device_ids, -+}; -+ -+static int __init lynloong_init(void) -+{ -+ int ret; -+ -+ pr_info("Load LynLoong Platform Specific Driver.\n"); -+ -+ /* Register platform stuff */ -+ ret = platform_driver_register(&platform_driver); -+ if (ret) { -+ pr_err("Fail to register lynloong platform driver.\n"); -+ return ret; -+ } -+ -+ ret = lynloong_backlight_init(); -+ if (ret) { -+ pr_err("Fail to register lynloong backlight driver.\n"); -+ return ret; -+ } -+ -+ ret = lynloong_vo_init(); -+ if (ret) { -+ pr_err("Fail to register lynloong backlight driver.\n"); -+ lynloong_vo_exit(); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static void __exit lynloong_exit(void) -+{ -+ lynloong_vo_exit(); -+ lynloong_backlight_exit(); -+ platform_driver_unregister(&platform_driver); -+ -+ pr_info("Unload LynLoong Platform Specific Driver.\n"); -+} -+ -+module_init(lynloong_init); -+module_exit(lynloong_exit); -+ -+MODULE_AUTHOR("Wu Zhangjin ; Xiang Yu "); -+MODULE_DESCRIPTION("LynLoong PC driver"); -+MODULE_LICENSE("GPL"); -diff -Nur linux-2.6.36.orig/drivers/platform/mips/yeeloong_ecrom.c linux-2.6.36/drivers/platform/mips/yeeloong_ecrom.c ---- linux-2.6.36.orig/drivers/platform/mips/yeeloong_ecrom.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/drivers/platform/mips/yeeloong_ecrom.c 2010-12-17 23:12:59.000000000 +0100 -@@ -0,0 +1,943 @@ -+/* -+ * Driver for flushing/dumping ROM of EC on YeeLoong laptop -+ * -+ * Copyright (C) 2009 Lemote Inc. -+ * Author: liujl -+ * -+ * NOTE : -+ * The EC resources accessing and programming are supported. -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include -+ -+#define EC_MISC_DEV "ec_misc" -+#define EC_IOC_MAGIC 'E' -+ -+/* ec registers range */ -+#define EC_MAX_REGADDR 0xFFFF -+#define EC_MIN_REGADDR 0xF000 -+#define EC_RAM_ADDR 0xF800 -+ -+/* version burned address */ -+#define VER_ADDR 0xf7a1 -+#define VER_MAX_SIZE 7 -+#define EC_ROM_MAX_SIZE 0x10000 -+ -+/* ec internal register */ -+#define REG_POWER_MODE 0xF710 -+#define FLAG_NORMAL_MODE 0x00 -+#define FLAG_IDLE_MODE 0x01 -+#define FLAG_RESET_MODE 0x02 -+ -+/* ec update program flag */ -+#define PROGRAM_FLAG_NONE 0x00 -+#define PROGRAM_FLAG_IE 0x01 -+#define PROGRAM_FLAG_ROM 0x02 -+ -+/* XBI relative registers */ -+#define REG_XBISEG0 0xFEA0 -+#define REG_XBISEG1 0xFEA1 -+#define REG_XBIRSV2 0xFEA2 -+#define REG_XBIRSV3 0xFEA3 -+#define REG_XBIRSV4 0xFEA4 -+#define REG_XBICFG 0xFEA5 -+#define REG_XBICS 0xFEA6 -+#define REG_XBIWE 0xFEA7 -+#define REG_XBISPIA0 0xFEA8 -+#define REG_XBISPIA1 0xFEA9 -+#define REG_XBISPIA2 0xFEAA -+#define REG_XBISPIDAT 0xFEAB -+#define REG_XBISPICMD 0xFEAC -+#define REG_XBISPICFG 0xFEAD -+#define REG_XBISPIDATR 0xFEAE -+#define REG_XBISPICFG2 0xFEAF -+ -+/* commands definition for REG_XBISPICMD */ -+#define SPICMD_WRITE_STATUS 0x01 -+#define SPICMD_BYTE_PROGRAM 0x02 -+#define SPICMD_READ_BYTE 0x03 -+#define SPICMD_WRITE_DISABLE 0x04 -+#define SPICMD_READ_STATUS 0x05 -+#define SPICMD_WRITE_ENABLE 0x06 -+#define SPICMD_HIGH_SPEED_READ 0x0B -+#define SPICMD_POWER_DOWN 0xB9 -+#define SPICMD_SST_EWSR 0x50 -+#define SPICMD_SST_SEC_ERASE 0x20 -+#define SPICMD_SST_BLK_ERASE 0x52 -+#define SPICMD_SST_CHIP_ERASE 0x60 -+#define SPICMD_FRDO 0x3B -+#define SPICMD_SEC_ERASE 0xD7 -+#define SPICMD_BLK_ERASE 0xD8 -+#define SPICMD_CHIP_ERASE 0xC7 -+ -+/* bits definition for REG_XBISPICFG */ -+#define SPICFG_AUTO_CHECK 0x01 -+#define SPICFG_SPI_BUSY 0x02 -+#define SPICFG_DUMMY_READ 0x04 -+#define SPICFG_EN_SPICMD 0x08 -+#define SPICFG_LOW_SPICS 0x10 -+#define SPICFG_EN_SHORT_READ 0x20 -+#define SPICFG_EN_OFFSET_READ 0x40 -+#define SPICFG_EN_FAST_READ 0x80 -+ -+/* watchdog timer registers */ -+#define REG_WDTCFG 0xfe80 -+#define REG_WDTPF 0xfe81 -+#define REG_WDT 0xfe82 -+ -+/* lpc configure register */ -+#define REG_LPCCFG 0xfe95 -+ -+/* 8051 reg */ -+#define REG_PXCFG 0xff14 -+ -+/* Fan register in KB3310 */ -+#define REG_ECFAN_SPEED_LEVEL 0xf4e4 -+#define REG_ECFAN_SWITCH 0xf4d2 -+ -+/* the ec flash rom id number */ -+#define EC_ROM_PRODUCT_ID_SPANSION 0x01 -+#define EC_ROM_PRODUCT_ID_MXIC 0xC2 -+#define EC_ROM_PRODUCT_ID_AMIC 0x37 -+#define EC_ROM_PRODUCT_ID_EONIC 0x1C -+ -+/* misc ioctl operations */ -+#define IOCTL_RDREG _IOR(EC_IOC_MAGIC, 1, int) -+#define IOCTL_WRREG _IOW(EC_IOC_MAGIC, 2, int) -+#define IOCTL_READ_EC _IOR(EC_IOC_MAGIC, 3, int) -+#define IOCTL_PROGRAM_IE _IOW(EC_IOC_MAGIC, 4, int) -+#define IOCTL_PROGRAM_EC _IOW(EC_IOC_MAGIC, 5, int) -+ -+/* start address for programming of EC content or IE */ -+/* ec running code start address */ -+#define EC_START_ADDR 0x00000000 -+/* ec information element storing address */ -+#define IE_START_ADDR 0x00020000 -+ -+/* EC state */ -+#define EC_STATE_IDLE 0x00 /* ec in idle state */ -+#define EC_STATE_BUSY 0x01 /* ec in busy state */ -+ -+/* timeout value for programming */ -+#define EC_FLASH_TIMEOUT 0x1000 /* ec program timeout */ -+/* command checkout timeout including cmd to port or state flag check */ -+#define EC_CMD_TIMEOUT 0x1000 -+#define EC_SPICMD_STANDARD_TIMEOUT (4 * 1000) /* unit : us */ -+#define EC_MAX_DELAY_UNIT (10) /* every time for polling */ -+#define SPI_FINISH_WAIT_TIME 10 -+/* EC content max size */ -+#define EC_CONTENT_MAX_SIZE (64 * 1024) -+#define IE_CONTENT_MAX_SIZE (0x100000 - IE_START_ADDR) -+ -+/* the register operation access struct */ -+struct ec_reg { -+ u32 addr; /* the address of kb3310 registers */ -+ u8 val; /* the register value */ -+}; -+ -+struct ec_info { -+ u32 start_addr; -+ u32 size; -+ u8 *buf; -+}; -+ -+/* open for using rom protection action */ -+#define EC_ROM_PROTECTION -+ -+/* enable the chip reset mode */ -+static int ec_init_reset_mode(void) -+{ -+ int timeout; -+ unsigned char status = 0; -+ int ret = 0; -+ -+ /* make chip goto reset mode */ -+ ret = ec_query_seq(CMD_INIT_RESET_MODE); -+ if (ret < 0) { -+ printk(KERN_ERR "ec init reset mode failed.\n"); -+ goto out; -+ } -+ -+ /* make the action take active */ -+ timeout = EC_CMD_TIMEOUT; -+ status = ec_read(REG_POWER_MODE) & FLAG_RESET_MODE; -+ while (timeout--) { -+ if (status) { -+ udelay(EC_REG_DELAY); -+ break; -+ } -+ status = ec_read(REG_POWER_MODE) & FLAG_RESET_MODE; -+ udelay(EC_REG_DELAY); -+ } -+ if (timeout <= 0) { -+ printk(KERN_ERR "ec rom fixup : can't check reset status.\n"); -+ ret = -EINVAL; -+ } else -+ printk(KERN_INFO "(%d/%d)reset 0xf710 : 0x%x\n", timeout, -+ EC_CMD_TIMEOUT - timeout, status); -+ -+ /* set MCU to reset mode */ -+ udelay(EC_REG_DELAY); -+ status = ec_read(REG_PXCFG); -+ status |= (1 << 0); -+ ec_write(REG_PXCFG, status); -+ udelay(EC_REG_DELAY); -+ -+ /* disable FWH/LPC */ -+ udelay(EC_REG_DELAY); -+ status = ec_read(REG_LPCCFG); -+ status &= ~(1 << 7); -+ ec_write(REG_LPCCFG, status); -+ udelay(EC_REG_DELAY); -+ -+ printk(KERN_INFO "entering reset mode ok..............\n"); -+ -+ out: -+ return ret; -+} -+ -+/* make ec exit from reset mode */ -+static void ec_exit_reset_mode(void) -+{ -+ unsigned char regval; -+ -+ udelay(EC_REG_DELAY); -+ regval = ec_read(REG_LPCCFG); -+ regval |= (1 << 7); -+ ec_write(REG_LPCCFG, regval); -+ regval = ec_read(REG_PXCFG); -+ regval &= ~(1 << 0); -+ ec_write(REG_PXCFG, regval); -+ printk(KERN_INFO "exit reset mode ok..................\n"); -+ -+ return; -+} -+ -+/* make ec disable WDD */ -+static void ec_disable_WDD(void) -+{ -+ unsigned char status; -+ -+ udelay(EC_REG_DELAY); -+ status = ec_read(REG_WDTCFG); -+ ec_write(REG_WDTPF, 0x03); -+ ec_write(REG_WDTCFG, (status & 0x80) | 0x48); -+ printk(KERN_INFO "Disable WDD ok..................\n"); -+ -+ return; -+} -+ -+/* make ec enable WDD */ -+static void ec_enable_WDD(void) -+{ -+ unsigned char status; -+ -+ udelay(EC_REG_DELAY); -+ status = ec_read(REG_WDTCFG); -+ ec_write(REG_WDT, 0x28); /* set WDT 5sec(0x28) */ -+ ec_write(REG_WDTCFG, (status & 0x80) | 0x03); -+ printk(KERN_INFO "Enable WDD ok..................\n"); -+ -+ return; -+} -+ -+/* make ec goto idle mode */ -+static int ec_init_idle_mode(void) -+{ -+ int timeout; -+ unsigned char status = 0; -+ int ret = 0; -+ -+ ec_query_seq(CMD_INIT_IDLE_MODE); -+ -+ /* make the action take active */ -+ timeout = EC_CMD_TIMEOUT; -+ status = ec_read(REG_POWER_MODE) & FLAG_IDLE_MODE; -+ while (timeout--) { -+ if (status) { -+ udelay(EC_REG_DELAY); -+ break; -+ } -+ status = ec_read(REG_POWER_MODE) & FLAG_IDLE_MODE; -+ udelay(EC_REG_DELAY); -+ } -+ if (timeout <= 0) { -+ printk(KERN_ERR "ec rom fixup : can't check out the status.\n"); -+ ret = -EINVAL; -+ } else -+ printk(KERN_INFO "(%d/%d)0xf710 : 0x%x\n", timeout, -+ EC_CMD_TIMEOUT - timeout, ec_read(REG_POWER_MODE)); -+ -+ printk(KERN_INFO "entering idle mode ok...................\n"); -+ -+ return ret; -+} -+ -+/* make ec exit from idle mode */ -+static int ec_exit_idle_mode(void) -+{ -+ -+ ec_query_seq(CMD_EXIT_IDLE_MODE); -+ -+ printk(KERN_INFO "exit idle mode ok...................\n"); -+ -+ return 0; -+} -+ -+static int ec_instruction_cycle(void) -+{ -+ unsigned long timeout; -+ int ret = 0; -+ -+ timeout = EC_FLASH_TIMEOUT; -+ while (timeout-- >= 0) { -+ if (!(ec_read(REG_XBISPICFG) & SPICFG_SPI_BUSY)) -+ break; -+ } -+ if (timeout <= 0) { -+ printk(KERN_ERR -+ "EC_INSTRUCTION_CYCLE : timeout for check flag.\n"); -+ ret = -EINVAL; -+ goto out; -+ } -+ -+ out: -+ return ret; -+} -+ -+/* To see if the ec is in busy state or not. */ -+static inline int ec_flash_busy(unsigned long timeout) -+{ -+ /* assurance the first command be going to rom */ -+ if (ec_instruction_cycle() < 0) -+ return EC_STATE_BUSY; -+#if 1 -+ timeout = timeout / EC_MAX_DELAY_UNIT; -+ while (timeout-- > 0) { -+ /* check the rom's status of busy flag */ -+ ec_write(REG_XBISPICMD, SPICMD_READ_STATUS); -+ if (ec_instruction_cycle() < 0) -+ return EC_STATE_BUSY; -+ if ((ec_read(REG_XBISPIDAT) & 0x01) == 0x00) -+ return EC_STATE_IDLE; -+ udelay(EC_MAX_DELAY_UNIT); -+ } -+ if (timeout <= 0) { -+ printk(KERN_ERR -+ "EC_FLASH_BUSY : timeout for check rom flag.\n"); -+ return EC_STATE_BUSY; -+ } -+#else -+ /* check the rom's status of busy flag */ -+ ec_write(REG_XBISPICMD, SPICMD_READ_STATUS); -+ if (ec_instruction_cycle() < 0) -+ return EC_STATE_BUSY; -+ -+ timeout = timeout / EC_MAX_DELAY_UNIT; -+ while (timeout-- > 0) { -+ if ((ec_read(REG_XBISPIDAT) & 0x01) == 0x00) -+ return EC_STATE_IDLE; -+ udelay(EC_MAX_DELAY_UNIT); -+ } -+ if (timeout <= 0) { -+ printk(KERN_ERR -+ "EC_FLASH_BUSY : timeout for check rom flag.\n"); -+ return EC_STATE_BUSY; -+ } -+#endif -+ -+ return EC_STATE_IDLE; -+} -+ -+static int rom_instruction_cycle(unsigned char cmd) -+{ -+ unsigned long timeout = 0; -+ -+ switch (cmd) { -+ case SPICMD_READ_STATUS: -+ case SPICMD_WRITE_ENABLE: -+ case SPICMD_WRITE_DISABLE: -+ case SPICMD_READ_BYTE: -+ case SPICMD_HIGH_SPEED_READ: -+ timeout = 0; -+ break; -+ case SPICMD_WRITE_STATUS: -+ timeout = 300 * 1000; -+ break; -+ case SPICMD_BYTE_PROGRAM: -+ timeout = 5 * 1000; -+ break; -+ case SPICMD_SST_SEC_ERASE: -+ case SPICMD_SEC_ERASE: -+ timeout = 1000 * 1000; -+ break; -+ case SPICMD_SST_BLK_ERASE: -+ case SPICMD_BLK_ERASE: -+ timeout = 3 * 1000 * 1000; -+ break; -+ case SPICMD_SST_CHIP_ERASE: -+ case SPICMD_CHIP_ERASE: -+ timeout = 20 * 1000 * 1000; -+ break; -+ default: -+ timeout = EC_SPICMD_STANDARD_TIMEOUT; -+ } -+ if (timeout == 0) -+ return ec_instruction_cycle(); -+ if (timeout < EC_SPICMD_STANDARD_TIMEOUT) -+ timeout = EC_SPICMD_STANDARD_TIMEOUT; -+ -+ return ec_flash_busy(timeout); -+} -+ -+/* delay for start/stop action */ -+static void delay_spi(int n) -+{ -+ while (n--) -+ inb(EC_IO_PORT_HIGH); -+} -+ -+/* start the action to spi rom function */ -+static void ec_start_spi(void) -+{ -+ unsigned char val; -+ -+ delay_spi(SPI_FINISH_WAIT_TIME); -+ val = ec_read(REG_XBISPICFG) | SPICFG_EN_SPICMD | SPICFG_AUTO_CHECK; -+ ec_write(REG_XBISPICFG, val); -+ delay_spi(SPI_FINISH_WAIT_TIME); -+} -+ -+/* stop the action to spi rom function */ -+static void ec_stop_spi(void) -+{ -+ unsigned char val; -+ -+ delay_spi(SPI_FINISH_WAIT_TIME); -+ val = -+ ec_read(REG_XBISPICFG) & (~(SPICFG_EN_SPICMD | SPICFG_AUTO_CHECK)); -+ ec_write(REG_XBISPICFG, val); -+ delay_spi(SPI_FINISH_WAIT_TIME); -+} -+ -+/* read one byte from xbi interface */ -+static int ec_read_byte(unsigned int addr, unsigned char *byte) -+{ -+ int ret = 0; -+ -+ /* enable spicmd writing. */ -+ ec_start_spi(); -+ -+ /* enable write spi flash */ -+ ec_write(REG_XBISPICMD, SPICMD_WRITE_ENABLE); -+ if (rom_instruction_cycle(SPICMD_WRITE_ENABLE) == EC_STATE_BUSY) { -+ printk(KERN_ERR "EC_READ_BYTE : SPICMD_WRITE_ENABLE failed.\n"); -+ ret = -EINVAL; -+ goto out; -+ } -+ -+ /* write the address */ -+ ec_write(REG_XBISPIA2, (addr & 0xff0000) >> 16); -+ ec_write(REG_XBISPIA1, (addr & 0x00ff00) >> 8); -+ ec_write(REG_XBISPIA0, (addr & 0x0000ff) >> 0); -+ /* start action */ -+ ec_write(REG_XBISPICMD, SPICMD_HIGH_SPEED_READ); -+ if (rom_instruction_cycle(SPICMD_HIGH_SPEED_READ) == EC_STATE_BUSY) { -+ printk(KERN_ERR -+ "EC_READ_BYTE : SPICMD_HIGH_SPEED_READ failed.\n"); -+ ret = -EINVAL; -+ goto out; -+ } -+ -+ *byte = ec_read(REG_XBISPIDAT); -+ -+ out: -+ /* disable spicmd writing. */ -+ ec_stop_spi(); -+ -+ return ret; -+} -+ -+/* write one byte to ec rom */ -+static int ec_write_byte(unsigned int addr, unsigned char byte) -+{ -+ int ret = 0; -+ -+ /* enable spicmd writing. */ -+ ec_start_spi(); -+ -+ /* enable write spi flash */ -+ ec_write(REG_XBISPICMD, SPICMD_WRITE_ENABLE); -+ if (rom_instruction_cycle(SPICMD_WRITE_ENABLE) == EC_STATE_BUSY) { -+ printk(KERN_ERR -+ "EC_WRITE_BYTE : SPICMD_WRITE_ENABLE failed.\n"); -+ ret = -EINVAL; -+ goto out; -+ } -+ -+ /* write the address */ -+ ec_write(REG_XBISPIA2, (addr & 0xff0000) >> 16); -+ ec_write(REG_XBISPIA1, (addr & 0x00ff00) >> 8); -+ ec_write(REG_XBISPIA0, (addr & 0x0000ff) >> 0); -+ ec_write(REG_XBISPIDAT, byte); -+ /* start action */ -+ ec_write(REG_XBISPICMD, SPICMD_BYTE_PROGRAM); -+ if (rom_instruction_cycle(SPICMD_BYTE_PROGRAM) == EC_STATE_BUSY) { -+ printk(KERN_ERR -+ "EC_WRITE_BYTE : SPICMD_BYTE_PROGRAM failed.\n"); -+ ret = -EINVAL; -+ goto out; -+ } -+ -+ out: -+ /* disable spicmd writing. */ -+ ec_stop_spi(); -+ -+ return ret; -+} -+ -+/* unprotect SPI ROM */ -+/* EC_ROM_unprotect function code */ -+static int EC_ROM_unprotect(void) -+{ -+ unsigned char status; -+ -+ /* enable write spi flash */ -+ ec_write(REG_XBISPICMD, SPICMD_WRITE_ENABLE); -+ if (rom_instruction_cycle(SPICMD_WRITE_ENABLE) == EC_STATE_BUSY) { -+ printk(KERN_ERR -+ "EC_UNIT_ERASE : SPICMD_WRITE_ENABLE failed.\n"); -+ return 1; -+ } -+ -+ /* unprotect the status register of rom */ -+ ec_write(REG_XBISPICMD, SPICMD_READ_STATUS); -+ if (rom_instruction_cycle(SPICMD_READ_STATUS) == EC_STATE_BUSY) { -+ printk(KERN_ERR "EC_UNIT_ERASE : SPICMD_READ_STATUS failed.\n"); -+ return 1; -+ } -+ status = ec_read(REG_XBISPIDAT); -+ ec_write(REG_XBISPIDAT, status & 0x02); -+ if (ec_instruction_cycle() < 0) { -+ printk(KERN_ERR "EC_UNIT_ERASE : write status value failed.\n"); -+ return 1; -+ } -+ -+ ec_write(REG_XBISPICMD, SPICMD_WRITE_STATUS); -+ if (rom_instruction_cycle(SPICMD_WRITE_STATUS) == EC_STATE_BUSY) { -+ printk(KERN_ERR -+ "EC_UNIT_ERASE : SPICMD_WRITE_STATUS failed.\n"); -+ return 1; -+ } -+ -+ /* enable write spi flash */ -+ ec_write(REG_XBISPICMD, SPICMD_WRITE_ENABLE); -+ if (rom_instruction_cycle(SPICMD_WRITE_ENABLE) == EC_STATE_BUSY) { -+ printk(KERN_ERR -+ "EC_UNIT_ERASE : SPICMD_WRITE_ENABLE failed.\n"); -+ return 1; -+ } -+ -+ return 0; -+} -+ -+/* erase one block or chip or sector as needed */ -+static int ec_unit_erase(unsigned char erase_cmd, unsigned int addr) -+{ -+ unsigned char status; -+ int ret = 0, i = 0; -+ int unprotect_count = 3; -+ int check_flag = 0; -+ -+ /* enable spicmd writing. */ -+ ec_start_spi(); -+ -+#ifdef EC_ROM_PROTECTION -+ /* added for re-check SPICMD_READ_STATUS */ -+ while (unprotect_count-- > 0) { -+ if (EC_ROM_unprotect()) { -+ ret = -EINVAL; -+ goto out; -+ } -+ -+ /* first time:500ms --> 5.5sec -->10.5sec */ -+ for (i = 0; i < ((2 - unprotect_count) * 100 + 10); i++) -+ udelay(50000); -+ ec_write(REG_XBISPICMD, SPICMD_READ_STATUS); -+ if (rom_instruction_cycle(SPICMD_READ_STATUS) -+ == EC_STATE_BUSY) { -+ printk(KERN_ERR -+ "EC_PROGRAM_ROM : SPICMD_READ_STATUS failed.\n"); -+ } else { -+ status = ec_read(REG_XBISPIDAT); -+ printk(KERN_INFO "Read unprotect status : 0x%x\n", -+ status); -+ if ((status & 0x1C) == 0x00) { -+ printk(KERN_INFO -+ "Read unprotect status OK1 : 0x%x\n", -+ status & 0x1C); -+ check_flag = 1; -+ break; -+ } -+ } -+ } -+ -+ if (!check_flag) { -+ printk(KERN_INFO "SPI ROM unprotect fail.\n"); -+ return 1; -+ } -+#endif -+ -+ /* block address fill */ -+ if (erase_cmd == SPICMD_BLK_ERASE) { -+ ec_write(REG_XBISPIA2, (addr & 0x00ff0000) >> 16); -+ ec_write(REG_XBISPIA1, (addr & 0x0000ff00) >> 8); -+ ec_write(REG_XBISPIA0, (addr & 0x000000ff) >> 0); -+ } -+ -+ /* erase the whole chip first */ -+ ec_write(REG_XBISPICMD, erase_cmd); -+ if (rom_instruction_cycle(erase_cmd) == EC_STATE_BUSY) { -+ printk(KERN_ERR "EC_UNIT_ERASE : erase failed.\n"); -+ ret = -EINVAL; -+ goto out; -+ } -+ -+ out: -+ /* disable spicmd writing. */ -+ ec_stop_spi(); -+ -+ return ret; -+} -+ -+/* update the whole rom content with H/W mode -+ * PLEASE USING ec_unit_erase() FIRSTLY -+ */ -+static int ec_program_rom(struct ec_info *info, int flag) -+{ -+ unsigned int addr = 0; -+ unsigned long size = 0; -+ unsigned char *ptr = NULL; -+ unsigned char data; -+ unsigned char val = 0; -+ int ret = 0; -+ int i, j; -+ unsigned char status; -+ -+ /* modify for program serial No. -+ * set IE_START_ADDR & use idle mode, -+ * disable WDD -+ */ -+ if (flag == PROGRAM_FLAG_ROM) { -+ ret = ec_init_reset_mode(); -+ addr = info->start_addr + EC_START_ADDR; -+ printk(KERN_INFO "PROGRAM_FLAG_ROM..............\n"); -+ } else if (flag == PROGRAM_FLAG_IE) { -+ ret = ec_init_idle_mode(); -+ ec_disable_WDD(); -+ addr = info->start_addr + IE_START_ADDR; -+ printk(KERN_INFO "PROGRAM_FLAG_IE..............\n"); -+ } else { -+ return 0; -+ } -+ -+ if (ret < 0) { -+ if (flag == PROGRAM_FLAG_IE) -+ ec_enable_WDD(); -+ return ret; -+ } -+ -+ size = info->size; -+ ptr = info->buf; -+ printk(KERN_INFO "starting update ec ROM..............\n"); -+ -+ ret = ec_unit_erase(SPICMD_BLK_ERASE, addr); -+ if (ret) { -+ printk(KERN_ERR "program ec : erase block failed.\n"); -+ goto out; -+ } -+ printk(KERN_ERR "program ec : erase block OK.\n"); -+ -+ i = 0; -+ while (i < size) { -+ data = *(ptr + i); -+ ec_write_byte(addr, data); -+ ec_read_byte(addr, &val); -+ if (val != data) { -+ ec_write_byte(addr, data); -+ ec_read_byte(addr, &val); -+ if (val != data) { -+ printk(KERN_INFO -+ "EC : Second flash program failed at:\t"); -+ printk(KERN_INFO -+ "addr : 0x%x, source : 0x%x, dest: 0x%x\n", -+ addr, data, val); -+ printk(KERN_INFO "This should not happen... STOP\n"); -+ break; -+ } -+ } -+ i++; -+ addr++; -+ } -+ -+#ifdef EC_ROM_PROTECTION -+ /* we should start spi access firstly */ -+ ec_start_spi(); -+ -+ /* enable write spi flash */ -+ ec_write(REG_XBISPICMD, SPICMD_WRITE_ENABLE); -+ if (rom_instruction_cycle(SPICMD_WRITE_ENABLE) == EC_STATE_BUSY) { -+ printk(KERN_ERR -+ "EC_PROGRAM_ROM : SPICMD_WRITE_ENABLE failed.\n"); -+ goto out1; -+ } -+ -+ /* protect the status register of rom */ -+ ec_write(REG_XBISPICMD, SPICMD_READ_STATUS); -+ if (rom_instruction_cycle(SPICMD_READ_STATUS) == EC_STATE_BUSY) { -+ printk(KERN_ERR -+ "EC_PROGRAM_ROM : SPICMD_READ_STATUS failed.\n"); -+ goto out1; -+ } -+ status = ec_read(REG_XBISPIDAT); -+ -+ ec_write(REG_XBISPIDAT, status | 0x1C); -+ if (ec_instruction_cycle() < 0) { -+ printk(KERN_ERR -+ "EC_PROGRAM_ROM : write status value failed.\n"); -+ goto out1; -+ } -+ -+ ec_write(REG_XBISPICMD, SPICMD_WRITE_STATUS); -+ if (rom_instruction_cycle(SPICMD_WRITE_STATUS) == EC_STATE_BUSY) { -+ printk(KERN_ERR -+ "EC_PROGRAM_ROM : SPICMD_WRITE_STATUS failed.\n"); -+ goto out1; -+ } -+#endif -+ -+ /* disable the write action to spi rom */ -+ ec_write(REG_XBISPICMD, SPICMD_WRITE_DISABLE); -+ if (rom_instruction_cycle(SPICMD_WRITE_DISABLE) == EC_STATE_BUSY) { -+ printk(KERN_ERR -+ "EC_PROGRAM_ROM : SPICMD_WRITE_DISABLE failed.\n"); -+ goto out1; -+ } -+ -+ out1: -+ /* we should stop spi access firstly */ -+ ec_stop_spi(); -+ out: -+ /* for security */ -+ for (j = 0; j < 2000; j++) -+ udelay(1000); -+ -+ /* modify for program serial No. -+ * after program No exit idle mode -+ * and enable WDD -+ */ -+ if (flag == PROGRAM_FLAG_ROM) { -+ /* exit from the reset mode */ -+ ec_exit_reset_mode(); -+ } else { -+ /* ec exit from idle mode */ -+ ret = ec_exit_idle_mode(); -+ ec_enable_WDD(); -+ if (ret < 0) -+ return ret; -+ } -+ -+ return 0; -+} -+ -+/* ioctl */ -+static int misc_ioctl(struct inode *inode, struct file *filp, u_int cmd, -+ u_long arg) -+{ -+ struct ec_info ecinfo; -+ void __user *ptr = (void __user *)arg; -+ struct ec_reg *ecreg = (struct ec_reg *)(filp->private_data); -+ int ret = 0; -+ -+ switch (cmd) { -+ case IOCTL_RDREG: -+ ret = copy_from_user(ecreg, ptr, sizeof(struct ec_reg)); -+ if (ret) { -+ printk(KERN_ERR "reg read : copy from user error.\n"); -+ return -EFAULT; -+ } -+ if ((ecreg->addr > EC_MAX_REGADDR) -+ || (ecreg->addr < EC_MIN_REGADDR)) { -+ printk(KERN_ERR -+ "reg read : out of register address range.\n"); -+ return -EINVAL; -+ } -+ ecreg->val = ec_read(ecreg->addr); -+ ret = copy_to_user(ptr, ecreg, sizeof(struct ec_reg)); -+ if (ret) { -+ printk(KERN_ERR "reg read : copy to user error.\n"); -+ return -EFAULT; -+ } -+ break; -+ case IOCTL_WRREG: -+ ret = copy_from_user(ecreg, ptr, sizeof(struct ec_reg)); -+ if (ret) { -+ printk(KERN_ERR "reg write : copy from user error.\n"); -+ return -EFAULT; -+ } -+ if ((ecreg->addr > EC_MAX_REGADDR) -+ || (ecreg->addr < EC_MIN_REGADDR)) { -+ printk(KERN_ERR -+ "reg write : out of register address range.\n"); -+ return -EINVAL; -+ } -+ ec_write(ecreg->addr, ecreg->val); -+ break; -+ case IOCTL_READ_EC: -+ ret = copy_from_user(ecreg, ptr, sizeof(struct ec_reg)); -+ if (ret) { -+ printk(KERN_ERR "spi read : copy from user error.\n"); -+ return -EFAULT; -+ } -+ if ((ecreg->addr > EC_RAM_ADDR) -+ && (ecreg->addr < EC_MAX_REGADDR)) { -+ printk(KERN_ERR -+ "spi read : out of register address range.\n"); -+ return -EINVAL; -+ } -+ ec_read_byte(ecreg->addr, &(ecreg->val)); -+ ret = copy_to_user(ptr, ecreg, sizeof(struct ec_reg)); -+ if (ret) { -+ printk(KERN_ERR "spi read : copy to user error.\n"); -+ return -EFAULT; -+ } -+ break; -+ case IOCTL_PROGRAM_IE: -+ ecinfo.start_addr = EC_START_ADDR; -+ ecinfo.size = EC_CONTENT_MAX_SIZE; -+ ecinfo.buf = (u8 *) kmalloc(ecinfo.size, GFP_KERNEL); -+ if (ecinfo.buf == NULL) { -+ printk(KERN_ERR "program ie : kmalloc failed.\n"); -+ return -ENOMEM; -+ } -+ ret = copy_from_user(ecinfo.buf, (u8 *) ptr, ecinfo.size); -+ if (ret) { -+ printk(KERN_ERR "program ie : copy from user error.\n"); -+ kfree(ecinfo.buf); -+ ecinfo.buf = NULL; -+ return -EFAULT; -+ } -+ -+ /* use ec_program_rom to write serial No */ -+ ec_program_rom(&ecinfo, PROGRAM_FLAG_IE); -+ -+ kfree(ecinfo.buf); -+ ecinfo.buf = NULL; -+ break; -+ case IOCTL_PROGRAM_EC: -+ ecinfo.start_addr = EC_START_ADDR; -+ if (get_user((ecinfo.size), (u32 *) ptr)) { -+ printk(KERN_ERR "program ec : get user error.\n"); -+ return -EFAULT; -+ } -+ if ((ecinfo.size) > EC_CONTENT_MAX_SIZE) { -+ printk(KERN_ERR "program ec : size out of limited.\n"); -+ return -EINVAL; -+ } -+ ecinfo.buf = (u8 *) kmalloc(ecinfo.size, GFP_KERNEL); -+ if (ecinfo.buf == NULL) { -+ printk(KERN_ERR "program ec : kmalloc failed.\n"); -+ return -ENOMEM; -+ } -+ ret = copy_from_user(ecinfo.buf, ((u8 *) ptr + 4), ecinfo.size); -+ if (ret) { -+ printk(KERN_ERR "program ec : copy from user error.\n"); -+ kfree(ecinfo.buf); -+ ecinfo.buf = NULL; -+ return -EFAULT; -+ } -+ -+ ec_program_rom(&ecinfo, PROGRAM_FLAG_ROM); -+ -+ kfree(ecinfo.buf); -+ ecinfo.buf = NULL; -+ break; -+ -+ default: -+ break; -+ } -+ -+ return 0; -+} -+ -+static long misc_compat_ioctl(struct file *file, unsigned int cmd, -+ unsigned long arg) -+{ -+ return misc_ioctl(file->f_dentry->d_inode, file, cmd, arg); -+} -+ -+static int misc_open(struct inode *inode, struct file *filp) -+{ -+ struct ec_reg *ecreg = NULL; -+ ecreg = kmalloc(sizeof(struct ec_reg), GFP_KERNEL); -+ if (ecreg) -+ filp->private_data = ecreg; -+ -+ return ecreg ? 0 : -ENOMEM; -+} -+ -+static int misc_release(struct inode *inode, struct file *filp) -+{ -+ struct ec_reg *ecreg = (struct ec_reg *)(filp->private_data); -+ -+ filp->private_data = NULL; -+ kfree(ecreg); -+ -+ return 0; -+} -+ -+static const struct file_operations ecmisc_fops = { -+ .open = misc_open, -+ .release = misc_release, -+ .read = NULL, -+ .write = NULL, -+#ifdef CONFIG_64BIT -+ .compat_ioctl = misc_compat_ioctl, -+#else -+ .ioctl = misc_ioctl, -+#endif -+}; -+ -+static struct miscdevice ecmisc_device = { -+ .minor = MISC_DYNAMIC_MINOR, -+ .name = EC_MISC_DEV, -+ .fops = &ecmisc_fops -+}; -+ -+static int __init ecmisc_init(void) -+{ -+ int ret; -+ -+ printk(KERN_INFO "EC misc device init.\n"); -+ ret = misc_register(&ecmisc_device); -+ -+ return ret; -+} -+ -+static void __exit ecmisc_exit(void) -+{ -+ printk(KERN_INFO "EC misc device exit.\n"); -+ misc_deregister(&ecmisc_device); -+} -+ -+module_init(ecmisc_init); -+module_exit(ecmisc_exit); -+ -+MODULE_AUTHOR("liujl "); -+MODULE_DESCRIPTION("Driver for flushing/dumping ROM of EC on YeeLoong laptop"); -+MODULE_LICENSE("GPL"); -diff -Nur linux-2.6.36.orig/drivers/platform/mips/yeeloong_laptop.c linux-2.6.36/drivers/platform/mips/yeeloong_laptop.c ---- linux-2.6.36.orig/drivers/platform/mips/yeeloong_laptop.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/drivers/platform/mips/yeeloong_laptop.c 2010-12-17 23:12:59.000000000 +0100 -@@ -0,0 +1,1200 @@ -+/* -+ * Driver for YeeLoong laptop extras -+ * -+ * Copyright (C) 2009 Lemote Inc. -+ * Author: Wu Zhangjin , Liu Junliang -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include /* for backlight subdriver */ -+#include -+#include /* for hwmon subdriver */ -+#include -+#include /* for video output subdriver */ -+#include /* for hotkey subdriver */ -+#include -+#include -+#include -+#include /* for AC & Battery subdriver */ -+ -+#include -+ -+#include /* for loongson_cmdline */ -+#include -+ -+/* common function */ -+#define EC_VER_LEN 64 -+ -+static int ec_version_before(char *version) -+{ -+ char *p, ec_ver[EC_VER_LEN]; -+ -+ p = strstr(loongson_cmdline, "EC_VER="); -+ if (!p) -+ memset(ec_ver, 0, EC_VER_LEN); -+ else { -+ strncpy(ec_ver, p, EC_VER_LEN); -+ p = strstr(ec_ver, " "); -+ if (p) -+ *p = '\0'; -+ } -+ -+ return (strncasecmp(ec_ver, version, 64) < 0); -+} -+ -+/* backlight subdriver */ -+#define MAX_BRIGHTNESS 8 -+ -+static int yeeloong_set_brightness(struct backlight_device *bd) -+{ -+ unsigned int level, current_level; -+ static unsigned int old_level; -+ -+ level = (bd->props.fb_blank == FB_BLANK_UNBLANK && -+ bd->props.power == FB_BLANK_UNBLANK) ? -+ bd->props.brightness : 0; -+ -+ level = SENSORS_LIMIT(level, 0, MAX_BRIGHTNESS); -+ -+ /* Avoid to modify the brightness when EC is tuning it */ -+ if (old_level != level) { -+ current_level = ec_read(REG_DISPLAY_BRIGHTNESS); -+ if (old_level == current_level) -+ ec_write(REG_DISPLAY_BRIGHTNESS, level); -+ old_level = level; -+ } -+ -+ return 0; -+} -+ -+static int yeeloong_get_brightness(struct backlight_device *bd) -+{ -+ return ec_read(REG_DISPLAY_BRIGHTNESS); -+} -+ -+static struct backlight_ops backlight_ops = { -+ .get_brightness = yeeloong_get_brightness, -+ .update_status = yeeloong_set_brightness, -+}; -+ -+static struct backlight_device *yeeloong_backlight_dev; -+ -+static int yeeloong_backlight_init(void) -+{ -+ int ret; -+ struct backlight_properties props; -+ -+ memset(&props, 0, sizeof(struct backlight_properties)); -+ props.max_brightness = MAX_BRIGHTNESS; -+ yeeloong_backlight_dev = backlight_device_register("backlight0", NULL, -+ NULL, &backlight_ops, &props); -+ -+ if (IS_ERR(yeeloong_backlight_dev)) { -+ ret = PTR_ERR(yeeloong_backlight_dev); -+ yeeloong_backlight_dev = NULL; -+ return ret; -+ } -+ -+ yeeloong_backlight_dev->props.brightness = -+ yeeloong_get_brightness(yeeloong_backlight_dev); -+ backlight_update_status(yeeloong_backlight_dev); -+ -+ return 0; -+} -+ -+static void yeeloong_backlight_exit(void) -+{ -+ if (yeeloong_backlight_dev) { -+ backlight_device_unregister(yeeloong_backlight_dev); -+ yeeloong_backlight_dev = NULL; -+ } -+} -+ -+/* AC & Battery subdriver */ -+ -+static struct power_supply yeeloong_ac, yeeloong_bat; -+ -+#define AC_OFFLINE 0 -+#define AC_ONLINE 1 -+ -+static int yeeloong_get_ac_props(struct power_supply *psy, -+ enum power_supply_property psp, -+ union power_supply_propval *val) -+{ -+ switch (psp) { -+ case POWER_SUPPLY_PROP_ONLINE: -+ val->intval = ((ec_read(REG_BAT_POWER)) & BIT_BAT_POWER_ACIN) ? -+ AC_ONLINE : AC_OFFLINE; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+static enum power_supply_property yeeloong_ac_props[] = { -+ POWER_SUPPLY_PROP_ONLINE, -+}; -+ -+static struct power_supply yeeloong_ac = { -+ .name = "yeeloong-ac", -+ .type = POWER_SUPPLY_TYPE_MAINS, -+ .properties = yeeloong_ac_props, -+ .num_properties = ARRAY_SIZE(yeeloong_ac_props), -+ .get_property = yeeloong_get_ac_props, -+}; -+ -+#define BAT_CAP_CRITICAL 5 -+#define BAT_CAP_HIGH 99 -+ -+#define get_bat_info(type) \ -+ ((ec_read(REG_BAT_##type##_HIGH) << 8) | \ -+ (ec_read(REG_BAT_##type##_LOW))) -+ -+static int yeeloong_bat_get_ex_property(enum power_supply_property psp, -+ union power_supply_propval *val) -+{ -+ int bat_in, curr_cap, cap_level, status, charge, health; -+ -+ status = ec_read(REG_BAT_STATUS); -+ bat_in = status & BIT_BAT_STATUS_IN; -+ curr_cap = get_bat_info(RELATIVE_CAP); -+ if (status & BIT_BAT_STATUS_FULL) -+ curr_cap = 100; -+ -+ switch (psp) { -+ case POWER_SUPPLY_PROP_PRESENT: -+ val->intval = bat_in; -+ break; -+ case POWER_SUPPLY_PROP_CAPACITY: -+ val->intval = curr_cap; -+ break; -+ case POWER_SUPPLY_PROP_CAPACITY_LEVEL: -+ cap_level = POWER_SUPPLY_CAPACITY_LEVEL_NORMAL; -+ if (status & BIT_BAT_STATUS_LOW) { -+ cap_level = POWER_SUPPLY_CAPACITY_LEVEL_LOW; -+ if (curr_cap <= BAT_CAP_CRITICAL) -+ cap_level = -+ POWER_SUPPLY_CAPACITY_LEVEL_CRITICAL; -+ } else if (status & BIT_BAT_STATUS_FULL) { -+ cap_level = POWER_SUPPLY_CAPACITY_LEVEL_FULL; -+ if (curr_cap >= BAT_CAP_HIGH) -+ cap_level = POWER_SUPPLY_CAPACITY_LEVEL_HIGH; -+ } else if (status & BIT_BAT_STATUS_DESTROY) -+ cap_level = POWER_SUPPLY_CAPACITY_LEVEL_UNKNOWN; -+ val->intval = cap_level; -+ break; -+ case POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW: -+ /* seconds */ -+ val->intval = bat_in ? (curr_cap - 3) * 54 + 142 : 0; -+ break; -+ case POWER_SUPPLY_PROP_STATUS: -+ if (!bat_in) -+ charge = POWER_SUPPLY_STATUS_UNKNOWN; -+ else { -+ if (status & BIT_BAT_STATUS_FULL) { -+ val->intval = POWER_SUPPLY_STATUS_FULL; -+ break; -+ } -+ -+ charge = ec_read(REG_BAT_CHARGE); -+ if (charge & FLAG_BAT_CHARGE_DISCHARGE) -+ charge = POWER_SUPPLY_STATUS_DISCHARGING; -+ else if (charge & FLAG_BAT_CHARGE_CHARGE) -+ charge = POWER_SUPPLY_STATUS_CHARGING; -+ else -+ charge = POWER_SUPPLY_STATUS_NOT_CHARGING; -+ } -+ val->intval = charge; -+ break; -+ case POWER_SUPPLY_PROP_HEALTH: -+ if (!bat_in) /* no battery present */ -+ health = POWER_SUPPLY_HEALTH_UNKNOWN; -+ else { /* Assume it is good */ -+ health = POWER_SUPPLY_HEALTH_GOOD; -+ if (status & -+ (BIT_BAT_STATUS_DESTROY | BIT_BAT_STATUS_LOW)) -+ health = POWER_SUPPLY_HEALTH_DEAD; -+ if (ec_read(REG_BAT_CHARGE_STATUS) & -+ BIT_BAT_CHARGE_STATUS_OVERTEMP) -+ health = POWER_SUPPLY_HEALTH_OVERHEAT; -+ } -+ val->intval = health; -+ break; -+ case POWER_SUPPLY_PROP_CHARGE_NOW: /* 1/100(%)*1000 µAh */ -+ val->intval = curr_cap * get_bat_info(FULLCHG_CAP) * 10; -+ break; -+ default: -+ return -EINVAL; -+ } -+ return 0; -+} -+ -+static int get_battery_temp(void) -+{ -+ int value; -+ -+ value = get_bat_info(TEMPERATURE); -+ -+ return value * 1000; -+} -+ -+static int get_battery_current(void) -+{ -+ s16 value; -+ -+ value = get_bat_info(CURRENT); -+ -+ return -value; -+} -+ -+static int get_battery_voltage(void) -+{ -+ int value; -+ -+ value = get_bat_info(VOLTAGE); -+ -+ return value; -+} -+ -+static int yeeloong_get_bat_props(struct power_supply *psy, -+ enum power_supply_property psp, -+ union power_supply_propval *val) -+{ -+ switch (psp) { -+ /* Fixed information */ -+ case POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN: -+ val->intval = get_bat_info(DESIGN_VOL) * 1000; /* mV -> µV */ -+ break; -+ case POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN: -+ val->intval = get_bat_info(DESIGN_CAP) * 1000; /* mAh->µAh */ -+ break; -+ case POWER_SUPPLY_PROP_CHARGE_FULL: -+ val->intval = get_bat_info(FULLCHG_CAP) * 1000; /* µAh */ -+ break; -+ case POWER_SUPPLY_PROP_MANUFACTURER: -+ val->strval = (ec_read(REG_BAT_VENDOR) == -+ FLAG_BAT_VENDOR_SANYO) ? "SANYO" : "SIMPLO"; -+ break; -+ /* Dynamic information */ -+ case POWER_SUPPLY_PROP_CURRENT_NOW: -+ val->intval = get_battery_current() * 1000; /* mA -> µA */ -+ break; -+ case POWER_SUPPLY_PROP_VOLTAGE_NOW: -+ val->intval = get_battery_voltage() * 1000; /* mV -> µV */ -+ break; -+ case POWER_SUPPLY_PROP_TEMP: -+ val->intval = get_battery_temp(); /* Celcius */ -+ break; -+ /* Dynamic but related information */ -+ default: -+ return yeeloong_bat_get_ex_property(psp, val); -+ } -+ -+ return 0; -+} -+ -+static enum power_supply_property yeeloong_bat_props[] = { -+ POWER_SUPPLY_PROP_STATUS, -+ POWER_SUPPLY_PROP_PRESENT, -+ POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN, -+ POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN, -+ POWER_SUPPLY_PROP_CHARGE_FULL, -+ POWER_SUPPLY_PROP_CHARGE_NOW, -+ POWER_SUPPLY_PROP_CURRENT_NOW, -+ POWER_SUPPLY_PROP_VOLTAGE_NOW, -+ POWER_SUPPLY_PROP_HEALTH, -+ POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW, -+ POWER_SUPPLY_PROP_CAPACITY, -+ POWER_SUPPLY_PROP_CAPACITY_LEVEL, -+ POWER_SUPPLY_PROP_TEMP, -+ POWER_SUPPLY_PROP_MANUFACTURER, -+}; -+ -+static struct power_supply yeeloong_bat = { -+ .name = "yeeloong-bat", -+ .type = POWER_SUPPLY_TYPE_BATTERY, -+ .properties = yeeloong_bat_props, -+ .num_properties = ARRAY_SIZE(yeeloong_bat_props), -+ .get_property = yeeloong_get_bat_props, -+}; -+ -+static int ac_bat_initialized; -+ -+static int yeeloong_bat_init(void) -+{ -+ int ret; -+ -+ ret = power_supply_register(NULL, &yeeloong_ac); -+ if (ret) -+ return ret; -+ ret = power_supply_register(NULL, &yeeloong_bat); -+ if (ret) { -+ power_supply_unregister(&yeeloong_ac); -+ return ret; -+ } -+ ac_bat_initialized = 1; -+ -+ return 0; -+} -+ -+static void yeeloong_bat_exit(void) -+{ -+ ac_bat_initialized = 0; -+ -+ power_supply_unregister(&yeeloong_ac); -+ power_supply_unregister(&yeeloong_bat); -+} -+/* hwmon subdriver */ -+ -+#define MIN_FAN_SPEED 0 -+#define MAX_FAN_SPEED 3 -+ -+static int get_fan_pwm_enable(void) -+{ -+ int level, mode; -+ -+ level = ec_read(REG_FAN_SPEED_LEVEL); -+ mode = ec_read(REG_FAN_AUTO_MAN_SWITCH); -+ -+ if (level == MAX_FAN_SPEED && mode == BIT_FAN_MANUAL) -+ mode = 0; -+ else if (mode == BIT_FAN_MANUAL) -+ mode = 1; -+ else -+ mode = 2; -+ -+ return mode; -+} -+ -+static void set_fan_pwm_enable(int mode) -+{ -+ switch (mode) { -+ case 0: -+ /* fullspeed */ -+ ec_write(REG_FAN_AUTO_MAN_SWITCH, BIT_FAN_MANUAL); -+ ec_write(REG_FAN_SPEED_LEVEL, MAX_FAN_SPEED); -+ break; -+ case 1: -+ ec_write(REG_FAN_AUTO_MAN_SWITCH, BIT_FAN_MANUAL); -+ break; -+ case 2: -+ ec_write(REG_FAN_AUTO_MAN_SWITCH, BIT_FAN_AUTO); -+ break; -+ default: -+ break; -+ } -+} -+ -+static int get_fan_pwm(void) -+{ -+ return ec_read(REG_FAN_SPEED_LEVEL); -+} -+ -+static void set_fan_pwm(int value) -+{ -+ int mode; -+ -+ mode = ec_read(REG_FAN_AUTO_MAN_SWITCH); -+ if (mode != BIT_FAN_MANUAL) -+ return; -+ -+ value = SENSORS_LIMIT(value, 0, 3); -+ -+ /* We must ensure the fan is on */ -+ if (value > 0) -+ ec_write(REG_FAN_CONTROL, BIT_FAN_CONTROL_ON); -+ -+ ec_write(REG_FAN_SPEED_LEVEL, value); -+} -+ -+static int get_fan_rpm(void) -+{ -+ int value; -+ -+ value = FAN_SPEED_DIVIDER / -+ (((ec_read(REG_FAN_SPEED_HIGH) & 0x0f) << 8) | -+ ec_read(REG_FAN_SPEED_LOW)); -+ -+ return value; -+} -+ -+static int get_cpu_temp(void) -+{ -+ s8 value; -+ -+ value = ec_read(REG_TEMPERATURE_VALUE); -+ -+ return value * 1000; -+} -+ -+static int get_cpu_temp_max(void) -+{ -+ return 60 * 1000; -+} -+ -+static int get_battery_temp_alarm(void) -+{ -+ int status; -+ -+ status = (ec_read(REG_BAT_CHARGE_STATUS) & -+ BIT_BAT_CHARGE_STATUS_OVERTEMP); -+ -+ return !!status; -+} -+ -+static ssize_t store_sys_hwmon(void (*set) (int), const char *buf, size_t count) -+{ -+ int ret; -+ unsigned long value; -+ -+ if (!count) -+ return 0; -+ -+ ret = strict_strtoul(buf, 10, &value); -+ if (ret) -+ return ret; -+ -+ set(value); -+ -+ return count; -+} -+ -+static ssize_t show_sys_hwmon(int (*get) (void), char *buf) -+{ -+ return sprintf(buf, "%d\n", get()); -+} -+ -+#define CREATE_SENSOR_ATTR(_name, _mode, _set, _get) \ -+ static ssize_t show_##_name(struct device *dev, \ -+ struct device_attribute *attr, \ -+ char *buf) \ -+ { \ -+ return show_sys_hwmon(_set, buf); \ -+ } \ -+ static ssize_t store_##_name(struct device *dev, \ -+ struct device_attribute *attr, \ -+ const char *buf, size_t count) \ -+ { \ -+ return store_sys_hwmon(_get, buf, count); \ -+ } \ -+ static SENSOR_DEVICE_ATTR(_name, _mode, show_##_name, store_##_name, 0); -+ -+CREATE_SENSOR_ATTR(fan1_input, S_IRUGO, get_fan_rpm, NULL); -+CREATE_SENSOR_ATTR(pwm1, S_IRUGO | S_IWUSR, get_fan_pwm, set_fan_pwm); -+CREATE_SENSOR_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, get_fan_pwm_enable, -+ set_fan_pwm_enable); -+CREATE_SENSOR_ATTR(temp1_input, S_IRUGO, get_cpu_temp, NULL); -+CREATE_SENSOR_ATTR(temp1_max, S_IRUGO, get_cpu_temp_max, NULL); -+CREATE_SENSOR_ATTR(temp2_input, S_IRUGO, get_battery_temp, NULL); -+CREATE_SENSOR_ATTR(temp2_max_alarm, S_IRUGO, get_battery_temp_alarm, NULL); -+CREATE_SENSOR_ATTR(curr1_input, S_IRUGO, get_battery_current, NULL); -+CREATE_SENSOR_ATTR(in1_input, S_IRUGO, get_battery_voltage, NULL); -+ -+static ssize_t -+show_name(struct device *dev, struct device_attribute *attr, char *buf) -+{ -+ return sprintf(buf, "yeeloong\n"); -+} -+ -+static SENSOR_DEVICE_ATTR(name, S_IRUGO, show_name, NULL, 0); -+ -+static struct attribute *hwmon_attributes[] = { -+ &sensor_dev_attr_pwm1.dev_attr.attr, -+ &sensor_dev_attr_pwm1_enable.dev_attr.attr, -+ &sensor_dev_attr_fan1_input.dev_attr.attr, -+ &sensor_dev_attr_temp1_input.dev_attr.attr, -+ &sensor_dev_attr_temp1_max.dev_attr.attr, -+ &sensor_dev_attr_temp2_input.dev_attr.attr, -+ &sensor_dev_attr_temp2_max_alarm.dev_attr.attr, -+ &sensor_dev_attr_curr1_input.dev_attr.attr, -+ &sensor_dev_attr_in1_input.dev_attr.attr, -+ &sensor_dev_attr_name.dev_attr.attr, -+ NULL -+}; -+ -+static struct attribute_group hwmon_attribute_group = { -+ .attrs = hwmon_attributes -+}; -+ -+static struct device *yeeloong_hwmon_dev; -+ -+static int yeeloong_hwmon_init(void) -+{ -+ int ret; -+ -+ yeeloong_hwmon_dev = hwmon_device_register(NULL); -+ if (IS_ERR(yeeloong_hwmon_dev)) { -+ pr_err("Fail to register yeeloong hwmon device\n"); -+ yeeloong_hwmon_dev = NULL; -+ return PTR_ERR(yeeloong_hwmon_dev); -+ } -+ ret = sysfs_create_group(&yeeloong_hwmon_dev->kobj, -+ &hwmon_attribute_group); -+ if (ret) { -+ hwmon_device_unregister(yeeloong_hwmon_dev); -+ yeeloong_hwmon_dev = NULL; -+ return ret; -+ } -+ /* ensure fan is set to auto mode */ -+ set_fan_pwm_enable(2); -+ -+ return 0; -+} -+ -+static void yeeloong_hwmon_exit(void) -+{ -+ if (yeeloong_hwmon_dev) { -+ sysfs_remove_group(&yeeloong_hwmon_dev->kobj, -+ &hwmon_attribute_group); -+ hwmon_device_unregister(yeeloong_hwmon_dev); -+ yeeloong_hwmon_dev = NULL; -+ } -+} -+ -+/* video output subdriver */ -+ -+static int lcd_video_output_get(struct output_device *od) -+{ -+ return ec_read(REG_DISPLAY_LCD); -+} -+ -+#define LCD 0 -+#define CRT 1 -+ -+static void display_vo_set(int display, int on) -+{ -+ int addr; -+ unsigned long value; -+ -+ addr = (display == LCD) ? 0x31 : 0x21; -+ -+ outb(addr, 0x3c4); -+ value = inb(0x3c5); -+ -+ if (display == LCD) -+ value |= (on ? 0x03 : 0x02); -+ else { -+ if (on) -+ clear_bit(7, &value); -+ else -+ set_bit(7, &value); -+ } -+ -+ outb(addr, 0x3c4); -+ outb(value, 0x3c5); -+} -+ -+static int lcd_video_output_set(struct output_device *od) -+{ -+ unsigned long status; -+ -+ status = !!od->request_state; -+ -+ display_vo_set(LCD, status); -+ ec_write(REG_BACKLIGHT_CTRL, status); -+ -+ return 0; -+} -+ -+static struct output_properties lcd_output_properties = { -+ .set_state = lcd_video_output_set, -+ .get_status = lcd_video_output_get, -+}; -+ -+static int crt_video_output_get(struct output_device *od) -+{ -+ return ec_read(REG_CRT_DETECT); -+} -+ -+static int crt_video_output_set(struct output_device *od) -+{ -+ unsigned long status; -+ -+ status = !!od->request_state; -+ -+ if (ec_read(REG_CRT_DETECT) == BIT_CRT_DETECT_PLUG) -+ display_vo_set(CRT, status); -+ -+ return 0; -+} -+ -+static struct output_properties crt_output_properties = { -+ .set_state = crt_video_output_set, -+ .get_status = crt_video_output_get, -+}; -+ -+static struct output_device *lcd_output_dev, *crt_output_dev; -+ -+static void yeeloong_lcd_vo_set(int status) -+{ -+ lcd_output_dev->request_state = status; -+ lcd_video_output_set(lcd_output_dev); -+} -+ -+static void yeeloong_crt_vo_set(int status) -+{ -+ crt_output_dev->request_state = status; -+ crt_video_output_set(crt_output_dev); -+} -+ -+static int yeeloong_vo_init(void) -+{ -+ int ret; -+ -+ /* Register video output device: lcd, crt */ -+ lcd_output_dev = video_output_register("LCD", NULL, NULL, -+ &lcd_output_properties); -+ -+ if (IS_ERR(lcd_output_dev)) { -+ ret = PTR_ERR(lcd_output_dev); -+ lcd_output_dev = NULL; -+ return ret; -+ } -+ /* Ensure LCD is on by default */ -+ yeeloong_lcd_vo_set(BIT_DISPLAY_LCD_ON); -+ -+ crt_output_dev = video_output_register("CRT", NULL, NULL, -+ &crt_output_properties); -+ -+ if (IS_ERR(crt_output_dev)) { -+ ret = PTR_ERR(crt_output_dev); -+ crt_output_dev = NULL; -+ return ret; -+ } -+ -+ /* Turn off CRT by default, and will be enabled when the CRT -+ * connectting event reported by SCI */ -+ yeeloong_crt_vo_set(BIT_CRT_DETECT_UNPLUG); -+ -+ return 0; -+} -+ -+static void yeeloong_vo_exit(void) -+{ -+ if (lcd_output_dev) { -+ video_output_unregister(lcd_output_dev); -+ lcd_output_dev = NULL; -+ } -+ if (crt_output_dev) { -+ video_output_unregister(crt_output_dev); -+ crt_output_dev = NULL; -+ } -+} -+ -+/* hotkey subdriver */ -+ -+static struct input_dev *yeeloong_hotkey_dev; -+ -+static const struct key_entry yeeloong_keymap[] = { -+ {KE_SW, EVENT_LID, { SW_LID } }, -+ {KE_KEY, EVENT_CAMERA, { KEY_CAMERA } }, /* Fn + ESC */ -+ {KE_KEY, EVENT_SLEEP, { KEY_SLEEP } }, /* Fn + F1 */ -+ {KE_KEY, EVENT_DISPLAYTOGGLE, { KEY_DISPLAYTOGGLE } }, /* Fn + F2 */ -+ {KE_KEY, EVENT_SWITCHVIDEOMODE, { KEY_SWITCHVIDEOMODE } }, /* Fn + F3 */ -+ {KE_KEY, EVENT_AUDIO_MUTE, { KEY_MUTE } }, /* Fn + F4 */ -+ {KE_KEY, EVENT_WLAN, { KEY_WLAN } }, /* Fn + F5 */ -+ {KE_KEY, EVENT_DISPLAY_BRIGHTNESS, { KEY_BRIGHTNESSUP } }, /* Fn + up */ -+ {KE_KEY, EVENT_DISPLAY_BRIGHTNESS, { KEY_BRIGHTNESSDOWN } }, /* Fn + down */ -+ {KE_KEY, EVENT_AUDIO_VOLUME, { KEY_VOLUMEUP } }, /* Fn + right */ -+ {KE_KEY, EVENT_AUDIO_VOLUME, { KEY_VOLUMEDOWN } }, /* Fn + left */ -+ {KE_END, 0} -+}; -+ -+static struct key_entry *get_event_key_entry(int event, int status) -+{ -+ struct key_entry *ke; -+ static int old_brightness_status = -1; -+ static int old_volume_status = -1; -+ -+ ke = sparse_keymap_entry_from_scancode(yeeloong_hotkey_dev, event); -+ if (!ke) -+ return NULL; -+ -+ switch (event) { -+ case EVENT_DISPLAY_BRIGHTNESS: -+ /* current status > old one, means up */ -+ if ((status < old_brightness_status) || (0 == status)) -+ ke++; -+ old_brightness_status = status; -+ break; -+ case EVENT_AUDIO_VOLUME: -+ if ((status < old_volume_status) || (0 == status)) -+ ke++; -+ old_volume_status = status; -+ break; -+ default: -+ break; -+ } -+ -+ return ke; -+} -+ -+static int report_lid_switch(int status) -+{ -+ input_report_switch(yeeloong_hotkey_dev, SW_LID, !status); -+ input_sync(yeeloong_hotkey_dev); -+ -+ return status; -+} -+ -+static int crt_detect_handler(int status) -+{ -+ if (status) { -+ yeeloong_crt_vo_set(BIT_CRT_DETECT_PLUG); -+ yeeloong_lcd_vo_set(BIT_DISPLAY_LCD_OFF); -+ } else { -+ yeeloong_lcd_vo_set(BIT_DISPLAY_LCD_ON); -+ yeeloong_crt_vo_set(BIT_CRT_DETECT_UNPLUG); -+ } -+ return status; -+} -+ -+static int displaytoggle_handler(int status) -+{ -+ /* EC(>=PQ1D26) does this job for us, we can not do it again, -+ * otherwise, the brightness will not resume to the normal level! */ -+ if (ec_version_before("EC_VER=PQ1D26")) -+ yeeloong_lcd_vo_set(status); -+ -+ return status; -+} -+ -+static int switchvideomode_handler(int status) -+{ -+ static int video_output_status; -+ -+ /* Only enable switch video output button -+ * when CRT is connected */ -+ if (ec_read(REG_CRT_DETECT) == BIT_CRT_DETECT_UNPLUG) -+ return 0; -+ /* 0. no CRT connected: LCD on, CRT off -+ * 1. BOTH on -+ * 2. LCD off, CRT on -+ * 3. BOTH off -+ * 4. LCD on, CRT off -+ */ -+ video_output_status++; -+ if (video_output_status > 4) -+ video_output_status = 1; -+ -+ switch (video_output_status) { -+ case 1: -+ yeeloong_lcd_vo_set(BIT_DISPLAY_LCD_ON); -+ yeeloong_crt_vo_set(BIT_CRT_DETECT_PLUG); -+ break; -+ case 2: -+ yeeloong_lcd_vo_set(BIT_DISPLAY_LCD_OFF); -+ yeeloong_crt_vo_set(BIT_CRT_DETECT_PLUG); -+ break; -+ case 3: -+ yeeloong_lcd_vo_set(BIT_DISPLAY_LCD_OFF); -+ yeeloong_crt_vo_set(BIT_CRT_DETECT_UNPLUG); -+ break; -+ case 4: -+ yeeloong_lcd_vo_set(BIT_DISPLAY_LCD_ON); -+ yeeloong_crt_vo_set(BIT_CRT_DETECT_UNPLUG); -+ break; -+ default: -+ /* Ensure LCD is on */ -+ yeeloong_lcd_vo_set(BIT_DISPLAY_LCD_ON); -+ break; -+ } -+ return video_output_status; -+} -+ -+static int camera_handler(int status) -+{ -+ int value; -+ -+ value = ec_read(REG_CAMERA_CONTROL); -+ ec_write(REG_CAMERA_CONTROL, value | (1 << 1)); -+ -+ return status; -+} -+ -+static int usb2_handler(int status) -+{ -+ pr_emerg("USB2 Over Current occurred\n"); -+ -+ return status; -+} -+ -+static int usb0_handler(int status) -+{ -+ pr_emerg("USB0 Over Current occurred\n"); -+ -+ return status; -+} -+ -+static int ac_bat_handler(int status) -+{ -+ if (ac_bat_initialized) { -+ power_supply_changed(&yeeloong_ac); -+ power_supply_changed(&yeeloong_bat); -+ } -+ return status; -+} -+ -+static void do_event_action(int event) -+{ -+ sci_handler handler; -+ int reg, status; -+ struct key_entry *ke; -+ -+ reg = 0; -+ handler = NULL; -+ -+ switch (event) { -+ case EVENT_LID: -+ reg = REG_LID_DETECT; -+ break; -+ case EVENT_SWITCHVIDEOMODE: -+ handler = switchvideomode_handler; -+ break; -+ case EVENT_CRT_DETECT: -+ reg = REG_CRT_DETECT; -+ handler = crt_detect_handler; -+ break; -+ case EVENT_CAMERA: -+ reg = REG_CAMERA_STATUS; -+ handler = camera_handler; -+ break; -+ case EVENT_USB_OC2: -+ reg = REG_USB2_FLAG; -+ handler = usb2_handler; -+ break; -+ case EVENT_USB_OC0: -+ reg = REG_USB0_FLAG; -+ handler = usb0_handler; -+ break; -+ case EVENT_DISPLAYTOGGLE: -+ reg = REG_DISPLAY_LCD; -+ handler = displaytoggle_handler; -+ break; -+ case EVENT_AUDIO_MUTE: -+ reg = REG_AUDIO_MUTE; -+ break; -+ case EVENT_DISPLAY_BRIGHTNESS: -+ reg = REG_DISPLAY_BRIGHTNESS; -+ break; -+ case EVENT_AUDIO_VOLUME: -+ reg = REG_AUDIO_VOLUME; -+ break; -+ case EVENT_AC_BAT: -+ handler = ac_bat_handler; -+ break; -+ default: -+ break; -+ } -+ -+ if (reg != 0) -+ status = ec_read(reg); -+ -+ if (handler != NULL) -+ status = handler(status); -+ -+ pr_info("%s: event: %d status: %d\n", __func__, event, status); -+ -+ /* Report current key to user-space */ -+ ke = get_event_key_entry(event, status); -+ if (ke) { -+ if (ke->keycode == SW_LID) -+ report_lid_switch(status); -+ else -+ sparse_keymap_report_entry(yeeloong_hotkey_dev, ke, 1, -+ true); -+ } -+} -+ -+/* -+ * SCI(system control interrupt) main interrupt routine -+ * -+ * We will do the query and get event number together so the interrupt routine -+ * should be longer than 120us now at least 3ms elpase for it. -+ */ -+static irqreturn_t sci_irq_handler(int irq, void *dev_id) -+{ -+ int ret, event; -+ -+ if (SCI_IRQ_NUM != irq) -+ return IRQ_NONE; -+ -+ /* Query the event number */ -+ ret = ec_query_event_num(); -+ if (ret < 0) -+ return IRQ_NONE; -+ -+ event = ec_get_event_num(); -+ if (event < EVENT_START || event > EVENT_END) -+ return IRQ_NONE; -+ -+ /* Execute corresponding actions */ -+ do_event_action(event); -+ -+ return IRQ_HANDLED; -+} -+ -+/* -+ * Config and init some msr and gpio register properly. -+ */ -+static int sci_irq_init(void) -+{ -+ u32 hi, lo; -+ u32 gpio_base; -+ unsigned long flags; -+ int ret; -+ -+ /* Get gpio base */ -+ _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_GPIO), &hi, &lo); -+ gpio_base = lo & 0xff00; -+ -+ /* Filter the former kb3310 interrupt for security */ -+ ret = ec_query_event_num(); -+ if (ret) -+ return ret; -+ -+ /* For filtering next number interrupt */ -+ udelay(10000); -+ -+ /* Set gpio native registers and msrs for GPIO27 SCI EVENT PIN -+ * gpio : -+ * input, pull-up, no-invert, event-count and value 0, -+ * no-filter, no edge mode -+ * gpio27 map to Virtual gpio0 -+ * msr : -+ * no primary and lpc -+ * Unrestricted Z input to IG10 from Virtual gpio 0. -+ */ -+ local_irq_save(flags); -+ _rdmsr(0x80000024, &hi, &lo); -+ lo &= ~(1 << 10); -+ _wrmsr(0x80000024, hi, lo); -+ _rdmsr(0x80000025, &hi, &lo); -+ lo &= ~(1 << 10); -+ _wrmsr(0x80000025, hi, lo); -+ _rdmsr(0x80000023, &hi, &lo); -+ lo |= (0x0a << 0); -+ _wrmsr(0x80000023, hi, lo); -+ local_irq_restore(flags); -+ -+ /* Set gpio27 as sci interrupt -+ * -+ * input, pull-up, no-fliter, no-negedge, invert -+ * the sci event is just about 120us -+ */ -+ asm(".set noreorder\n"); -+ /* input enable */ -+ outl(0x00000800, (gpio_base | 0xA0)); -+ /* revert the input */ -+ outl(0x00000800, (gpio_base | 0xA4)); -+ /* event-int enable */ -+ outl(0x00000800, (gpio_base | 0xB8)); -+ asm(".set reorder\n"); -+ -+ return 0; -+} -+ -+static struct irqaction sci_irqaction = { -+ .handler = sci_irq_handler, -+ .name = "sci", -+ .flags = IRQF_SHARED, -+}; -+ -+static int yeeloong_hotkey_init(void) -+{ -+ int ret; -+ -+ ret = sci_irq_init(); -+ if (ret) -+ return -EFAULT; -+ -+ ret = setup_irq(SCI_IRQ_NUM, &sci_irqaction); -+ if (ret) -+ return -EFAULT; -+ -+ yeeloong_hotkey_dev = input_allocate_device(); -+ -+ if (!yeeloong_hotkey_dev) { -+ remove_irq(SCI_IRQ_NUM, &sci_irqaction); -+ return -ENOMEM; -+ } -+ -+ yeeloong_hotkey_dev->name = "HotKeys"; -+ yeeloong_hotkey_dev->phys = "button/input0"; -+ yeeloong_hotkey_dev->id.bustype = BUS_HOST; -+ yeeloong_hotkey_dev->dev.parent = NULL; -+ -+ ret = sparse_keymap_setup(yeeloong_hotkey_dev, yeeloong_keymap, NULL); -+ if (ret) { -+ pr_err("Fail to setup input device keymap\n"); -+ input_free_device(yeeloong_hotkey_dev); -+ return ret; -+ } -+ -+ ret = input_register_device(yeeloong_hotkey_dev); -+ if (ret) { -+ sparse_keymap_free(yeeloong_hotkey_dev); -+ input_free_device(yeeloong_hotkey_dev); -+ return ret; -+ } -+ -+ /* Update the current status of LID */ -+ report_lid_switch(BIT_LID_DETECT_ON); -+ -+#ifdef CONFIG_LOONGSON_SUSPEND -+ /* Install the real yeeloong_report_lid_status for pm.c */ -+ yeeloong_report_lid_status = report_lid_switch; -+#endif -+ -+ return 0; -+} -+ -+static void yeeloong_hotkey_exit(void) -+{ -+ /* Free irq */ -+ remove_irq(SCI_IRQ_NUM, &sci_irqaction); -+ -+#ifdef CONFIG_LOONGSON_SUSPEND -+ /* Uninstall yeeloong_report_lid_status for pm.c */ -+ if (yeeloong_report_lid_status == report_lid_switch) -+ yeeloong_report_lid_status = NULL; -+#endif -+ -+ if (yeeloong_hotkey_dev) { -+ sparse_keymap_free(yeeloong_hotkey_dev); -+ input_unregister_device(yeeloong_hotkey_dev); -+ yeeloong_hotkey_dev = NULL; -+ } -+} -+ -+#ifdef CONFIG_PM -+static void usb_ports_set(int status) -+{ -+ status = !!status; -+ -+ ec_write(REG_USB0_FLAG, status); -+ ec_write(REG_USB1_FLAG, status); -+ ec_write(REG_USB2_FLAG, status); -+} -+ -+static int yeeloong_suspend(struct device *dev) -+ -+{ -+ if (ec_version_before("EC_VER=PQ1D27")) -+ yeeloong_lcd_vo_set(BIT_DISPLAY_LCD_OFF); -+ yeeloong_crt_vo_set(BIT_CRT_DETECT_UNPLUG); -+ usb_ports_set(BIT_USB_FLAG_OFF); -+ -+ return 0; -+} -+ -+static int yeeloong_resume(struct device *dev) -+{ -+ if (ec_version_before("EC_VER=PQ1D27")) -+ yeeloong_lcd_vo_set(BIT_DISPLAY_LCD_ON); -+ yeeloong_crt_vo_set(BIT_CRT_DETECT_PLUG); -+ usb_ports_set(BIT_USB_FLAG_ON); -+ -+ return 0; -+} -+ -+static const SIMPLE_DEV_PM_OPS(yeeloong_pm_ops, yeeloong_suspend, -+ yeeloong_resume); -+#endif -+ -+static struct platform_device_id platform_device_ids[] = { -+ { -+ .name = "yeeloong_laptop", -+ }, -+ {} -+}; -+ -+MODULE_DEVICE_TABLE(platform, platform_device_ids); -+ -+static struct platform_driver platform_driver = { -+ .driver = { -+ .name = "yeeloong_laptop", -+ .owner = THIS_MODULE, -+#ifdef CONFIG_PM -+ .pm = &yeeloong_pm_ops, -+#endif -+ }, -+ .id_table = platform_device_ids, -+}; -+ -+static int __init yeeloong_init(void) -+{ -+ int ret; -+ -+ pr_info("Load YeeLoong Laptop Platform Specific Driver.\n"); -+ -+ /* Register platform stuff */ -+ ret = platform_driver_register(&platform_driver); -+ if (ret) { -+ pr_err("Fail to register yeeloong platform driver.\n"); -+ return ret; -+ } -+ -+ ret = yeeloong_backlight_init(); -+ if (ret) { -+ pr_err("Fail to register yeeloong backlight driver.\n"); -+ yeeloong_backlight_exit(); -+ return ret; -+ } -+ -+ ret = yeeloong_bat_init(); -+ if (ret) { -+ pr_err("Fail to register yeeloong battery driver.\n"); -+ yeeloong_bat_exit(); -+ return ret; -+ } -+ -+ ret = yeeloong_hwmon_init(); -+ if (ret) { -+ pr_err("Fail to register yeeloong hwmon driver.\n"); -+ yeeloong_hwmon_exit(); -+ return ret; -+ } -+ -+ ret = yeeloong_vo_init(); -+ if (ret) { -+ pr_err("Fail to register yeeloong video output driver.\n"); -+ yeeloong_vo_exit(); -+ return ret; -+ } -+ -+ ret = yeeloong_hotkey_init(); -+ if (ret) { -+ pr_err("Fail to register yeeloong hotkey driver.\n"); -+ yeeloong_hotkey_exit(); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static void __exit yeeloong_exit(void) -+{ -+ yeeloong_hotkey_exit(); -+ yeeloong_vo_exit(); -+ yeeloong_hwmon_exit(); -+ yeeloong_bat_exit(); -+ yeeloong_backlight_exit(); -+ platform_driver_unregister(&platform_driver); -+ -+ pr_info("Unload YeeLoong Platform Specific Driver.\n"); -+} -+ -+module_init(yeeloong_init); -+module_exit(yeeloong_exit); -+ -+MODULE_AUTHOR("Wu Zhangjin ; Liu Junliang "); -+MODULE_DESCRIPTION("YeeLoong laptop driver"); -+MODULE_LICENSE("GPL"); -diff -Nur linux-2.6.36.orig/drivers/staging/sm7xx/smtcfb.c linux-2.6.36/drivers/staging/sm7xx/smtcfb.c ---- linux-2.6.36.orig/drivers/staging/sm7xx/smtcfb.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/drivers/staging/sm7xx/smtcfb.c 2010-12-17 23:12:59.000000000 +0100 -@@ -12,6 +12,8 @@ - * License. See the file COPYING in the main directory of this archive for - * more details. - * -+ * - Remove the buggy 2D support for Lynx, 2010/01/06, Wu Zhangjin -+ * - * Version 0.10.26192.21.01 - * - Add PowerPC/Big endian support - * - Add 2D support for Lynx -@@ -107,6 +109,7 @@ - {"0x307", 1280, 1024, 8}, - - {"0x311", 640, 480, 16}, -+ {"0x313", 800, 480, 16}, - {"0x314", 800, 600, 16}, - {"0x317", 1024, 768, 16}, - {"0x31A", 1280, 1024, 16}, -diff -Nur linux-2.6.36.orig/drivers/usb/host/ohci-hcd.c linux-2.6.36/drivers/usb/host/ohci-hcd.c ---- linux-2.6.36.orig/drivers/usb/host/ohci-hcd.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/drivers/usb/host/ohci-hcd.c 2010-12-17 23:12:59.000000000 +0100 -@@ -832,9 +832,13 @@ - } - - if (ints & OHCI_INTR_WDH) { -- spin_lock (&ohci->lock); -- dl_done_list (ohci); -- spin_unlock (&ohci->lock); -+ if (ohci->hcca->done_head == 0) { -+ ints &= ~OHCI_INTR_WDH; -+ } else { -+ spin_lock (&ohci->lock); -+ dl_done_list (ohci); -+ spin_unlock (&ohci->lock); -+ } - } - - if (quirk_zfmicro(ohci) && (ints & OHCI_INTR_SF)) { -diff -Nur linux-2.6.36.orig/net/rfkill/core.c linux-2.6.36/net/rfkill/core.c ---- linux-2.6.36.orig/net/rfkill/core.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/net/rfkill/core.c 2010-12-17 23:12:59.000000000 +0100 -@@ -112,7 +112,7 @@ - static DEFINE_MUTEX(rfkill_global_mutex); - static LIST_HEAD(rfkill_fds); /* list of open fds of /dev/rfkill */ - --static unsigned int rfkill_default_state = 1; -+static unsigned int rfkill_default_state; /* default: 0 = radio off */ - module_param_named(default_state, rfkill_default_state, uint, 0444); - MODULE_PARM_DESC(default_state, - "Default initial state for all radio types, 0 = radio off"); diff --git a/target/linux/patches/2.6.36/mtd-root.patch b/target/linux/patches/2.6.36/mtd-root.patch deleted file mode 100644 index 4775c0e8e..000000000 --- a/target/linux/patches/2.6.36/mtd-root.patch +++ /dev/null @@ -1,62 +0,0 @@ -diff -Nur linux-2.6.36.orig/drivers/mtd/Kconfig linux-2.6.36/drivers/mtd/Kconfig ---- linux-2.6.36.orig/drivers/mtd/Kconfig 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/drivers/mtd/Kconfig 2010-11-09 13:26:44.923745421 +0100 -@@ -53,6 +53,11 @@ - devices. Partitioning on NFTL 'devices' is a different - that's the - 'normal' form of partitioning used on a block device. - -+config MTD_ROOTFS_ROOT_DEV -+ bool "Automatically set 'rootfs' partition to be root filesystem" -+ depends on MTD_PARTITIONS -+ default y -+ - config MTD_REDBOOT_PARTS - tristate "RedBoot partition table parsing" - depends on MTD_PARTITIONS -diff -Nur linux-2.6.36.orig/drivers/mtd/mtdpart.c linux-2.6.36/drivers/mtd/mtdpart.c ---- linux-2.6.36.orig/drivers/mtd/mtdpart.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/drivers/mtd/mtdpart.c 2010-11-09 13:27:26.703745576 +0100 -@@ -29,6 +29,7 @@ - #include - #include - #include -+#include - - /* Our partition linked list */ - static LIST_HEAD(mtd_partitions); -@@ -46,7 +47,7 @@ - * the pointer to that structure with this macro. - */ - #define PART(x) ((struct mtd_part *)(x)) -- -+#define IS_PART(mtd) (mtd->read == part_read) - - /* - * MTD methods which simply translate the effective address and pass through -@@ -539,14 +540,23 @@ - { - struct mtd_part *slave; - uint64_t cur_offset = 0; -- int i; -+ int i, j; - - printk(KERN_NOTICE "Creating %d MTD partitions on \"%s\":\n", nbparts, master->name); - -- for (i = 0; i < nbparts; i++) { -- slave = add_one_partition(master, parts + i, i, cur_offset); -+ for (i = 0, j = 0; i < nbparts; i++) { -+ slave = add_one_partition(master, parts + i, j++, cur_offset); - if (!slave) - return -ENOMEM; -+ if (!strcmp(parts[i].name, "rootfs")) { -+#ifdef CONFIG_MTD_ROOTFS_ROOT_DEV -+ if (ROOT_DEV == 0) { -+ printk(KERN_NOTICE "mtd: partition \"rootfs\" " -+ "set to be root filesystem\n"); -+ ROOT_DEV = MKDEV(MTD_BLOCK_MAJOR, slave->mtd.index); -+ } -+#endif -+ } - cur_offset = slave->offset + slave->mtd.size; - } - diff --git a/target/linux/patches/2.6.36/ocf-20100325.patch b/target/linux/patches/2.6.36/ocf-20100325.patch deleted file mode 100644 index bb4e537d5..000000000 --- a/target/linux/patches/2.6.36/ocf-20100325.patch +++ /dev/null @@ -1,87545 +0,0 @@ -diff -Nur linux-2.6.36.orig/crypto/Kconfig linux-2.6.36/crypto/Kconfig ---- linux-2.6.36.orig/crypto/Kconfig 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/crypto/Kconfig 2010-11-09 20:28:04.004996902 +0100 -@@ -845,3 +845,6 @@ - source "drivers/crypto/Kconfig" - - endif # if CRYPTO -+ -+source "crypto/ocf/Kconfig" -+ -diff -Nur linux-2.6.36.orig/crypto/Makefile linux-2.6.36/crypto/Makefile ---- linux-2.6.36.orig/crypto/Makefile 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/crypto/Makefile 2010-11-09 20:28:04.014995662 +0100 -@@ -86,6 +86,8 @@ - obj-$(CONFIG_CRYPTO_TEST) += tcrypt.o - obj-$(CONFIG_CRYPTO_GHASH) += ghash-generic.o - -+obj-$(CONFIG_OCF_OCF) += ocf/ -+ - # - # generic algorithms and the async_tx api - # -diff -Nur linux-2.6.36.orig/crypto/ocf/c7108/aes-7108.c linux-2.6.36/crypto/ocf/c7108/aes-7108.c ---- linux-2.6.36.orig/crypto/ocf/c7108/aes-7108.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/c7108/aes-7108.c 2010-11-09 20:28:04.061247304 +0100 -@@ -0,0 +1,839 @@ -+/* -+ * Copyright (C) 2006 Micronas USA -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored in part by the Defense Advanced Research Projects -+ * Agency (DARPA) and Air Force Research Laboratory, Air Force -+ * Materiel Command, USAF, under agreement number F30602-01-2-0537. -+ * -+ */ -+ -+//#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+//#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* Runtime mode */ -+static int c7108_crypto_mode = C7108_AES_CTRL_MODE_CTR; -+//static int c7108_crypto_mode = C7108_AES_CTRL_MODE_CBC; -+ -+static int32_t c7108_id = -1; -+static struct cipher_7108 **c7108_sessions = NULL; -+static u_int32_t c7108_sesnum = 0; -+static unsigned long iobar; -+ -+/* Crypto entry points */ -+static int c7108_process(void *, struct cryptop *, int); -+static int c7108_newsession(void *, u_int32_t *, struct cryptoini *); -+static int c7108_freesession(void *, u_int64_t); -+ -+/* Globals */ -+static int debug = 0; -+static spinlock_t csr_mutex; -+ -+/* Generic controller-based lock */ -+#define AES_LOCK()\ -+ spin_lock(&csr_mutex) -+#define AES_UNLOCK()\ -+ spin_unlock(&csr_mutex) -+ -+/* 7108 AES register access */ -+#define c7108_reg_wr8(a,d) iowrite8(d, (void*)(iobar+(a))) -+#define c7108_reg_wr16(a,d) iowrite16(d, (void*)(iobar+(a))) -+#define c7108_reg_wr32(a,d) iowrite32(d, (void*)(iobar+(a))) -+#define c7108_reg_rd8(a) ioread8((void*)(iobar+(a))) -+#define c7108_reg_rd16(a) ioread16((void*)(iobar+(a))) -+#define c7108_reg_rd32(a) ioread32((void*)(iobar+(a))) -+ -+static int -+c7108_xlate_key(int klen, u8* k8ptr, u32* k32ptr) -+{ -+ int i, nw=0; -+ nw = ((klen >= 256) ? 8 : (klen >= 192) ? 6 : 4); -+ for ( i = 0; i < nw; i++) { -+ k32ptr[i] = (k8ptr[i+3] << 24) | (k8ptr[i+2] << 16) | -+ (k8ptr[i+1] << 8) | k8ptr[i]; -+ -+ } -+ return 0; -+} -+ -+static int -+c7108_cache_key(int klen, u32* k32ptr, u8* k8ptr) -+{ -+ int i, nb=0; -+ u8* ptr = (u8*)k32ptr; -+ nb = ((klen >= 256) ? 32 : (klen >= 192) ? 24 : 16); -+ for ( i = 0; i < nb; i++) -+ k8ptr[i] = ptr[i]; -+ return 0; -+} -+ -+static int -+c7108_aes_setup_dma(u32 src, u32 dst, u32 len) -+{ -+ if (len < 16) { -+ printk("len < 16\n"); -+ return -10; -+ } -+ if (len % 16) { -+ printk("len not multiple of 16\n"); -+ return -11; -+ } -+ c7108_reg_wr16(C7108_AES_DMA_SRC0_LO, (u16) src); -+ c7108_reg_wr16(C7108_AES_DMA_SRC0_HI, (u16)((src & 0xffff0000) >> 16)); -+ c7108_reg_wr16(C7108_AES_DMA_DST0_LO, (u16) dst); -+ c7108_reg_wr16(C7108_AES_DMA_DST0_HI, (u16)((dst & 0xffff0000) >> 16)); -+ c7108_reg_wr16(C7108_AES_DMA_LEN, (u16) ((len / 16) - 1)); -+ -+ return 0; -+} -+ -+static int -+c7108_aes_set_hw_iv(u8 iv[16]) -+{ -+ c7108_reg_wr16(C7108_AES_IV0_LO, (u16) ((iv[1] << 8) | iv[0])); -+ c7108_reg_wr16(C7108_AES_IV0_HI, (u16) ((iv[3] << 8) | iv[2])); -+ c7108_reg_wr16(C7108_AES_IV1_LO, (u16) ((iv[5] << 8) | iv[4])); -+ c7108_reg_wr16(C7108_AES_IV1_HI, (u16) ((iv[7] << 8) | iv[6])); -+ c7108_reg_wr16(C7108_AES_IV2_LO, (u16) ((iv[9] << 8) | iv[8])); -+ c7108_reg_wr16(C7108_AES_IV2_HI, (u16) ((iv[11] << 8) | iv[10])); -+ c7108_reg_wr16(C7108_AES_IV3_LO, (u16) ((iv[13] << 8) | iv[12])); -+ c7108_reg_wr16(C7108_AES_IV3_HI, (u16) ((iv[15] << 8) | iv[14])); -+ -+ return 0; -+} -+ -+static void -+c7108_aes_read_dkey(u32 * dkey) -+{ -+ dkey[0] = (c7108_reg_rd16(C7108_AES_EKEY0_HI) << 16) | -+ c7108_reg_rd16(C7108_AES_EKEY0_LO); -+ dkey[1] = (c7108_reg_rd16(C7108_AES_EKEY1_HI) << 16) | -+ c7108_reg_rd16(C7108_AES_EKEY1_LO); -+ dkey[2] = (c7108_reg_rd16(C7108_AES_EKEY2_HI) << 16) | -+ c7108_reg_rd16(C7108_AES_EKEY2_LO); -+ dkey[3] = (c7108_reg_rd16(C7108_AES_EKEY3_HI) << 16) | -+ c7108_reg_rd16(C7108_AES_EKEY3_LO); -+ dkey[4] = (c7108_reg_rd16(C7108_AES_EKEY4_HI) << 16) | -+ c7108_reg_rd16(C7108_AES_EKEY4_LO); -+ dkey[5] = (c7108_reg_rd16(C7108_AES_EKEY5_HI) << 16) | -+ c7108_reg_rd16(C7108_AES_EKEY5_LO); -+ dkey[6] = (c7108_reg_rd16(C7108_AES_EKEY6_HI) << 16) | -+ c7108_reg_rd16(C7108_AES_EKEY6_LO); -+ dkey[7] = (c7108_reg_rd16(C7108_AES_EKEY7_HI) << 16) | -+ c7108_reg_rd16(C7108_AES_EKEY7_LO); -+} -+ -+static int -+c7108_aes_cipher(int op, -+ u32 dst, -+ u32 src, -+ u32 len, -+ int klen, -+ u16 mode, -+ u32 key[8], -+ u8 iv[16]) -+{ -+ int rv = 0, cnt=0; -+ u16 ctrl = 0, stat = 0; -+ -+ AES_LOCK(); -+ -+ /* Setup key length */ -+ if (klen == 128) { -+ ctrl |= C7108_AES_KEY_LEN_128; -+ } else if (klen == 192) { -+ ctrl |= C7108_AES_KEY_LEN_192; -+ } else if (klen == 256) { -+ ctrl |= C7108_AES_KEY_LEN_256; -+ } else { -+ AES_UNLOCK(); -+ return -3; -+ } -+ -+ /* Check opcode */ -+ if (C7108_AES_ENCRYPT == op) { -+ ctrl |= C7108_AES_ENCRYPT; -+ } else if (C7108_AES_DECRYPT == op) { -+ ctrl |= C7108_AES_DECRYPT; -+ } else { -+ AES_UNLOCK(); -+ return -4; -+ } -+ -+ /* check mode */ -+ if ( (mode != C7108_AES_CTRL_MODE_CBC) && -+ (mode != C7108_AES_CTRL_MODE_CFB) && -+ (mode != C7108_AES_CTRL_MODE_OFB) && -+ (mode != C7108_AES_CTRL_MODE_CTR) && -+ (mode != C7108_AES_CTRL_MODE_ECB) ) { -+ AES_UNLOCK(); -+ return -5; -+ } -+ -+ /* Now set mode */ -+ ctrl |= mode; -+ -+ /* For CFB, OFB, and CTR, neither backward key -+ * expansion nor key inversion is required. -+ */ -+ if ( (C7108_AES_DECRYPT == op) && -+ (C7108_AES_CTRL_MODE_CBC == mode || -+ C7108_AES_CTRL_MODE_ECB == mode ) ){ -+ -+ /* Program Key */ -+ c7108_reg_wr16(C7108_AES_KEY0_LO, (u16) key[4]); -+ c7108_reg_wr16(C7108_AES_KEY0_HI, (u16) (key[4] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY1_LO, (u16) key[5]); -+ c7108_reg_wr16(C7108_AES_KEY1_HI, (u16) (key[5] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY2_LO, (u16) key[6]); -+ c7108_reg_wr16(C7108_AES_KEY2_HI, (u16) (key[6] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY3_LO, (u16) key[7]); -+ c7108_reg_wr16(C7108_AES_KEY3_HI, (u16) (key[7] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY6_LO, (u16) key[2]); -+ c7108_reg_wr16(C7108_AES_KEY6_HI, (u16) (key[2] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY7_LO, (u16) key[3]); -+ c7108_reg_wr16(C7108_AES_KEY7_HI, (u16) (key[3] >> 16)); -+ -+ -+ if (192 == klen) { -+ c7108_reg_wr16(C7108_AES_KEY4_LO, (u16) key[7]); -+ c7108_reg_wr16(C7108_AES_KEY4_HI, (u16) (key[7] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY5_LO, (u16) key[7]); -+ c7108_reg_wr16(C7108_AES_KEY5_HI, (u16) (key[7] >> 16)); -+ -+ } else if (256 == klen) { -+ /* 256 */ -+ c7108_reg_wr16(C7108_AES_KEY4_LO, (u16) key[0]); -+ c7108_reg_wr16(C7108_AES_KEY4_HI, (u16) (key[0] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY5_LO, (u16) key[1]); -+ c7108_reg_wr16(C7108_AES_KEY5_HI, (u16) (key[1] >> 16)); -+ -+ } -+ -+ } else { -+ /* Program Key */ -+ c7108_reg_wr16(C7108_AES_KEY0_LO, (u16) key[0]); -+ c7108_reg_wr16(C7108_AES_KEY0_HI, (u16) (key[0] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY1_LO, (u16) key[1]); -+ c7108_reg_wr16(C7108_AES_KEY1_HI, (u16) (key[1] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY2_LO, (u16) key[2]); -+ c7108_reg_wr16(C7108_AES_KEY2_HI, (u16) (key[2] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY3_LO, (u16) key[3]); -+ c7108_reg_wr16(C7108_AES_KEY3_HI, (u16) (key[3] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY4_LO, (u16) key[4]); -+ c7108_reg_wr16(C7108_AES_KEY4_HI, (u16) (key[4] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY5_LO, (u16) key[5]); -+ c7108_reg_wr16(C7108_AES_KEY5_HI, (u16) (key[5] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY6_LO, (u16) key[6]); -+ c7108_reg_wr16(C7108_AES_KEY6_HI, (u16) (key[6] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY7_LO, (u16) key[7]); -+ c7108_reg_wr16(C7108_AES_KEY7_HI, (u16) (key[7] >> 16)); -+ -+ } -+ -+ /* Set IV always */ -+ c7108_aes_set_hw_iv(iv); -+ -+ /* Program DMA addresses */ -+ if ((rv = c7108_aes_setup_dma(src, dst, len)) < 0) { -+ AES_UNLOCK(); -+ return rv; -+ } -+ -+ -+ /* Start AES cipher */ -+ c7108_reg_wr16(C7108_AES_CTRL, ctrl | C7108_AES_GO); -+ -+ //printk("Ctrl: 0x%x\n", ctrl | C7108_AES_GO); -+ do { -+ /* TODO: interrupt mode */ -+ // printk("aes_stat=0x%x\n", stat); -+ //udelay(100); -+ } while ((cnt++ < 1000000) && -+ !((stat=c7108_reg_rd16(C7108_AES_CTRL))&C7108_AES_OP_DONE)); -+ -+ -+ if ((mode == C7108_AES_CTRL_MODE_ECB)|| -+ (mode == C7108_AES_CTRL_MODE_CBC)) { -+ /* Save out key when the lock is held ... */ -+ c7108_aes_read_dkey(key); -+ } -+ -+ AES_UNLOCK(); -+ return 0; -+ -+} -+ -+/* -+ * Generate a new crypto device session. -+ */ -+static int -+c7108_newsession(void *arg, u_int32_t *sid, struct cryptoini *cri) -+{ -+ struct cipher_7108 **swd; -+ u_int32_t i; -+ char *algo; -+ int mode, xfm_type; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid == NULL || cri == NULL) { -+ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ if (c7108_sessions) { -+ for (i = 1; i < c7108_sesnum; i++) -+ if (c7108_sessions[i] == NULL) -+ break; -+ } else -+ i = 1; /* NB: to silence compiler warning */ -+ -+ if (c7108_sessions == NULL || i == c7108_sesnum) { -+ if (c7108_sessions == NULL) { -+ i = 1; /* We leave c7108_sessions[0] empty */ -+ c7108_sesnum = CRYPTO_SW_SESSIONS; -+ } else -+ c7108_sesnum *= 2; -+ -+ swd = kmalloc(c7108_sesnum * sizeof(struct cipher_7108 *), -+ GFP_ATOMIC); -+ if (swd == NULL) { -+ /* Reset session number */ -+ if (c7108_sesnum == CRYPTO_SW_SESSIONS) -+ c7108_sesnum = 0; -+ else -+ c7108_sesnum /= 2; -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memset(swd, 0, c7108_sesnum * sizeof(struct cipher_7108 *)); -+ -+ /* Copy existing sessions */ -+ if (c7108_sessions) { -+ memcpy(swd, c7108_sessions, -+ (c7108_sesnum / 2) * sizeof(struct cipher_7108 *)); -+ kfree(c7108_sessions); -+ } -+ -+ c7108_sessions = swd; -+ -+ } -+ -+ swd = &c7108_sessions[i]; -+ *sid = i; -+ -+ while (cri) { -+ *swd = (struct cipher_7108 *) -+ kmalloc(sizeof(struct cipher_7108), GFP_ATOMIC); -+ if (*swd == NULL) { -+ c7108_freesession(NULL, i); -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memset(*swd, 0, sizeof(struct cipher_7108)); -+ -+ algo = NULL; -+ mode = 0; -+ xfm_type = HW_TYPE_CIPHER; -+ -+ switch (cri->cri_alg) { -+ -+ case CRYPTO_AES_CBC: -+ algo = "aes"; -+ mode = CRYPTO_TFM_MODE_CBC; -+ c7108_crypto_mode = C7108_AES_CTRL_MODE_CBC; -+ break; -+#if 0 -+ case CRYPTO_AES_CTR: -+ algo = "aes_ctr"; -+ mode = CRYPTO_TFM_MODE_CBC; -+ c7108_crypto_mode = C7108_AES_CTRL_MODE_CTR; -+ break; -+ case CRYPTO_AES_ECB: -+ algo = "aes_ecb"; -+ mode = CRYPTO_TFM_MODE_CBC; -+ c7108_crypto_mode = C7108_AES_CTRL_MODE_ECB; -+ break; -+ case CRYPTO_AES_OFB: -+ algo = "aes_ofb"; -+ mode = CRYPTO_TFM_MODE_CBC; -+ c7108_crypto_mode = C7108_AES_CTRL_MODE_OFB; -+ break; -+ case CRYPTO_AES_CFB: -+ algo = "aes_cfb"; -+ mode = CRYPTO_TFM_MODE_CBC; -+ c7108_crypto_mode = C7108_AES_CTRL_MODE_CFB; -+ break; -+#endif -+ default: -+ printk("unsupported crypto algorithm: %d\n", -+ cri->cri_alg); -+ return -EINVAL; -+ break; -+ } -+ -+ -+ if (!algo || !*algo) { -+ printk("cypher_7108_crypto: Unknown algo 0x%x\n", -+ cri->cri_alg); -+ c7108_freesession(NULL, i); -+ return EINVAL; -+ } -+ -+ if (xfm_type == HW_TYPE_CIPHER) { -+ if (debug) { -+ dprintk("%s key:", __FUNCTION__); -+ for (i = 0; i < (cri->cri_klen + 7) / 8; i++) -+ dprintk("%s0x%02x", (i % 8) ? " " : "\n ", -+ cri->cri_key[i]); -+ dprintk("\n"); -+ } -+ -+ } else if (xfm_type == SW_TYPE_HMAC || -+ xfm_type == SW_TYPE_HASH) { -+ printk("cypher_7108_crypto: HMAC unsupported!\n"); -+ return -EINVAL; -+ c7108_freesession(NULL, i); -+ } else { -+ printk("cypher_7108_crypto: " -+ "Unhandled xfm_type %d\n", xfm_type); -+ c7108_freesession(NULL, i); -+ return EINVAL; -+ } -+ -+ (*swd)->cri_alg = cri->cri_alg; -+ (*swd)->xfm_type = xfm_type; -+ -+ cri = cri->cri_next; -+ swd = &((*swd)->next); -+ } -+ return 0; -+} -+ -+/* -+ * Free a session. -+ */ -+static int -+c7108_freesession(void *arg, u_int64_t tid) -+{ -+ struct cipher_7108 *swd; -+ u_int32_t sid = CRYPTO_SESID2LID(tid); -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid > c7108_sesnum || c7108_sessions == NULL || -+ c7108_sessions[sid] == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return(EINVAL); -+ } -+ -+ /* Silently accept and return */ -+ if (sid == 0) -+ return(0); -+ -+ while ((swd = c7108_sessions[sid]) != NULL) { -+ c7108_sessions[sid] = swd->next; -+ kfree(swd); -+ } -+ return 0; -+} -+ -+/* -+ * Process a hardware request. -+ */ -+static int -+c7108_process(void *arg, struct cryptop *crp, int hint) -+{ -+ struct cryptodesc *crd; -+ struct cipher_7108 *sw; -+ u_int32_t lid; -+ int type; -+ u32 hwkey[8]; -+ -+#define SCATTERLIST_MAX 16 -+ struct scatterlist sg[SCATTERLIST_MAX]; -+ int sg_num, sg_len, skip; -+ struct sk_buff *skb = NULL; -+ struct uio *uiop = NULL; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ /* Sanity check */ -+ if (crp == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ crp->crp_etype = 0; -+ -+ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ lid = crp->crp_sid & 0xffffffff; -+ if (lid >= c7108_sesnum || lid == 0 || c7108_sessions == NULL || -+ c7108_sessions[lid] == NULL) { -+ crp->crp_etype = ENOENT; -+ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); -+ goto done; -+ } -+ -+ /* -+ * do some error checking outside of the loop for SKB and IOV -+ * processing this leaves us with valid skb or uiop pointers -+ * for later -+ */ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ skb = (struct sk_buff *) crp->crp_buf; -+ if (skb_shinfo(skb)->nr_frags >= SCATTERLIST_MAX) { -+ printk("%s,%d: %d nr_frags > SCATTERLIST_MAX", -+ __FILE__, __LINE__, -+ skb_shinfo(skb)->nr_frags); -+ goto done; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ uiop = (struct uio *) crp->crp_buf; -+ if (uiop->uio_iovcnt > SCATTERLIST_MAX) { -+ printk("%s,%d: %d uio_iovcnt > SCATTERLIST_MAX", -+ __FILE__, __LINE__, -+ uiop->uio_iovcnt); -+ goto done; -+ } -+ } -+ -+ /* Go through crypto descriptors, processing as we go */ -+ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { -+ /* -+ * Find the crypto context. -+ * -+ * XXX Note that the logic here prevents us from having -+ * XXX the same algorithm multiple times in a session -+ * XXX (or rather, we can but it won't give us the right -+ * XXX results). To do that, we'd need some way of differentiating -+ * XXX between the various instances of an algorithm (so we can -+ * XXX locate the correct crypto context). -+ */ -+ for (sw = c7108_sessions[lid]; -+ sw && sw->cri_alg != crd->crd_alg; -+ sw = sw->next) -+ ; -+ -+ /* No such context ? */ -+ if (sw == NULL) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ goto done; -+ } -+ -+ skip = crd->crd_skip; -+ -+ /* -+ * setup the SG list skip from the start of the buffer -+ */ -+ memset(sg, 0, sizeof(sg)); -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ int i, len; -+ type = CRYPTO_BUF_SKBUF; -+ -+ sg_num = 0; -+ sg_len = 0; -+ -+ if (skip < skb_headlen(skb)) { -+ //sg[sg_num].page = virt_to_page(skb->data + skip); -+ //sg[sg_num].offset = offset_in_page(skb->data + skip); -+ len = skb_headlen(skb) - skip; -+ if (len + sg_len > crd->crd_len) -+ len = crd->crd_len - sg_len; -+ //sg[sg_num].length = len; -+ sg_set_page(&sg[sg_num], virt_to_page(skb->data + skip), len, offset_in_page(skb->data + skip)); -+ sg_len += sg[sg_num].length; -+ sg_num++; -+ skip = 0; -+ } else -+ skip -= skb_headlen(skb); -+ -+ for (i = 0; sg_len < crd->crd_len && -+ i < skb_shinfo(skb)->nr_frags && -+ sg_num < SCATTERLIST_MAX; i++) { -+ if (skip < skb_shinfo(skb)->frags[i].size) { -+ //sg[sg_num].page = skb_shinfo(skb)->frags[i].page; -+ //sg[sg_num].offset = skb_shinfo(skb)->frags[i].page_offset + skip; -+ len = skb_shinfo(skb)->frags[i].size - skip; -+ if (len + sg_len > crd->crd_len) -+ len = crd->crd_len - sg_len; -+ //sg[sg_num].length = len; -+ sg_set_page(&sg[sg_num], skb_shinfo(skb)->frags[i].page, len, skb_shinfo(skb)->frags[i].page_offset + skip); -+ sg_len += sg[sg_num].length; -+ sg_num++; -+ skip = 0; -+ } else -+ skip -= skb_shinfo(skb)->frags[i].size; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ int len; -+ type = CRYPTO_BUF_IOV; -+ sg_len = 0; -+ for (sg_num = 0; sg_len < crd->crd_len && -+ sg_num < uiop->uio_iovcnt && -+ sg_num < SCATTERLIST_MAX; sg_num++) { -+ if (skip < uiop->uio_iov[sg_num].iov_len) { -+ //sg[sg_num].page = virt_to_page(uiop->uio_iov[sg_num].iov_base+skip); -+ //sg[sg_num].offset = offset_in_page(uiop->uio_iov[sg_num].iov_base+skip); -+ len = uiop->uio_iov[sg_num].iov_len - skip; -+ if (len + sg_len > crd->crd_len) -+ len = crd->crd_len - sg_len; -+ //sg[sg_num].length = len; -+ sg_set_page(&sg[sg_num], virt_to_page(uiop->uio_iov[sg_num].iov_base+skip), len, offset_in_page(uiop->uio_iov[sg_num].iov_base+skip)); -+ sg_len += sg[sg_num].length; -+ skip = 0; -+ } else -+ skip -= uiop->uio_iov[sg_num].iov_len; -+ } -+ } else { -+ type = CRYPTO_BUF_CONTIG; -+ //sg[0].page = virt_to_page(crp->crp_buf + skip); -+ //sg[0].offset = offset_in_page(crp->crp_buf + skip); -+ sg_len = (crp->crp_ilen - skip); -+ if (sg_len > crd->crd_len) -+ sg_len = crd->crd_len; -+ //sg[0].length = sg_len; -+ sg_set_page(&sg[0], virt_to_page(crp->crp_buf + skip), sg_len, offset_in_page(crp->crp_buf + skip)); -+ sg_num = 1; -+ } -+ -+ -+ switch (sw->xfm_type) { -+ -+ case HW_TYPE_CIPHER: { -+ -+ unsigned char iv[64]; -+ unsigned char *ivp = iv; -+ int i; -+ int ivsize = 16; /* fixed for AES */ -+ int blocksize = 16; /* fixed for AES */ -+ -+ if (sg_len < blocksize) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: EINVAL len %d < %d\n", -+ __FILE__, __LINE__, -+ sg_len, -+ blocksize); -+ goto done; -+ } -+ -+ if (ivsize > sizeof(iv)) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ goto done; -+ } -+ -+ if (crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ -+ -+ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { -+ ivp = crd->crd_iv; -+ } else { -+ get_random_bytes(ivp, ivsize); -+ } -+ /* -+ * do we have to copy the IV back to the buffer ? -+ */ -+ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { -+ crypto_copyback(crp->crp_buf, -+ crd->crd_inject, -+ ivsize, -+ (caddr_t)ivp); -+ } -+ -+ c7108_xlate_key(crd->crd_klen, -+ (u8*)crd->crd_key, (u32*)hwkey); -+ -+ /* Encrypt SG list */ -+ for (i = 0; i < sg_num; i++) { -+ sg[i].dma_address = -+ dma_map_single(NULL, -+ kmap(sg_page(&sg[i])) + sg[i].offset, sg_len, DMA_BIDIRECTIONAL); -+#if 0 -+ printk("sg[%d]:0x%08x, off 0x%08x " -+ "kmap 0x%08x phys 0x%08x\n", -+ i, sg[i].page, sg[i].offset, -+ kmap(sg[i].page) + sg[i].offset, -+ sg[i].dma_address); -+#endif -+ c7108_aes_cipher(C7108_AES_ENCRYPT, -+ sg[i].dma_address, -+ sg[i].dma_address, -+ sg_len, -+ crd->crd_klen, -+ c7108_crypto_mode, -+ hwkey, -+ ivp); -+ -+ if ((c7108_crypto_mode == C7108_AES_CTRL_MODE_CBC)|| -+ (c7108_crypto_mode == C7108_AES_CTRL_MODE_ECB)) { -+ /* Read back expanded key and cache it in key -+ * context. -+ * NOTE: for ECB/CBC modes only (not CTR, CFB, OFB) -+ * where you set the key once. -+ */ -+ c7108_cache_key(crd->crd_klen, -+ (u32*)hwkey, (u8*)crd->crd_key); -+#if 0 -+ printk("%s expanded key:", __FUNCTION__); -+ for (i = 0; i < (crd->crd_klen + 7) / 8; i++) -+ printk("%s0x%02x", (i % 8) ? " " : "\n ", -+ crd->crd_key[i]); -+ printk("\n"); -+#endif -+ } -+ } -+ } -+ else { /*decrypt */ -+ -+ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { -+ ivp = crd->crd_iv; -+ } else { -+ crypto_copydata(crp->crp_buf, crd->crd_inject, -+ ivsize, (caddr_t)ivp); -+ } -+ -+ c7108_xlate_key(crd->crd_klen, -+ (u8*)crd->crd_key, (u32*)hwkey); -+ -+ /* Decrypt SG list */ -+ for (i = 0; i < sg_num; i++) { -+ sg[i].dma_address = -+ dma_map_single(NULL, -+ kmap(sg_page(&sg[i])) + sg[i].offset, -+ sg_len, DMA_BIDIRECTIONAL); -+ -+#if 0 -+ printk("sg[%d]:0x%08x, off 0x%08x " -+ "kmap 0x%08x phys 0x%08x\n", -+ i, sg[i].page, sg[i].offset, -+ kmap(sg[i].page) + sg[i].offset, -+ sg[i].dma_address); -+#endif -+ c7108_aes_cipher(C7108_AES_DECRYPT, -+ sg[i].dma_address, -+ sg[i].dma_address, -+ sg_len, -+ crd->crd_klen, -+ c7108_crypto_mode, -+ hwkey, -+ ivp); -+ } -+ } -+ } break; -+ case SW_TYPE_HMAC: -+ case SW_TYPE_HASH: -+ crp->crp_etype = EINVAL; -+ goto done; -+ break; -+ -+ case SW_TYPE_COMP: -+ crp->crp_etype = EINVAL; -+ goto done; -+ break; -+ -+ default: -+ /* Unknown/unsupported algorithm */ -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ } -+ -+done: -+ crypto_done(crp); -+ return 0; -+} -+ -+static struct { -+ softc_device_decl sc_dev; -+} a7108dev; -+ -+static device_method_t a7108_methods = { -+/* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, c7108_newsession), -+ DEVMETHOD(cryptodev_freesession, c7108_freesession), -+ DEVMETHOD(cryptodev_process, c7108_process), -+ DEVMETHOD(cryptodev_kprocess, NULL) -+}; -+ -+static int -+cypher_7108_crypto_init(void) -+{ -+ dprintk("%s(%p)\n", __FUNCTION__, cypher_7108_crypto_init); -+ -+ iobar = (unsigned long)ioremap(CCU_AES_REG_BASE, 0x4000); -+ printk("7108: AES @ 0x%08x (0x%08x phys) %s mode\n", -+ iobar, CCU_AES_REG_BASE, -+ c7108_crypto_mode & C7108_AES_CTRL_MODE_CBC ? "CBC" : -+ c7108_crypto_mode & C7108_AES_CTRL_MODE_ECB ? "ECB" : -+ c7108_crypto_mode & C7108_AES_CTRL_MODE_CTR ? "CTR" : -+ c7108_crypto_mode & C7108_AES_CTRL_MODE_CFB ? "CFB" : -+ c7108_crypto_mode & C7108_AES_CTRL_MODE_OFB ? "OFB" : "???"); -+ csr_mutex = SPIN_LOCK_UNLOCKED; -+ -+ memset(&a7108dev, 0, sizeof(a7108dev)); -+ softc_device_init(&a7108dev, "aes7108", 0, a7108_methods); -+ -+ c7108_id = crypto_get_driverid(softc_get_device(&a7108dev), CRYPTOCAP_F_HARDWARE); -+ if (c7108_id < 0) -+ panic("7108: crypto device cannot initialize!"); -+ -+// crypto_register(c7108_id, CRYPTO_AES_CBC, 0, 0, c7108_newsession, c7108_freesession, c7108_process, NULL); -+ crypto_register(c7108_id, CRYPTO_AES_CBC, 0, 0); -+ -+ return(0); -+} -+ -+static void -+cypher_7108_crypto_exit(void) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ crypto_unregister_all(c7108_id); -+ c7108_id = -1; -+} -+ -+module_init(cypher_7108_crypto_init); -+module_exit(cypher_7108_crypto_exit); -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_DESCRIPTION("Cypher 7108 Crypto (OCF module for kernel crypto)"); -diff -Nur linux-2.6.36.orig/crypto/ocf/c7108/aes-7108.h linux-2.6.36/crypto/ocf/c7108/aes-7108.h ---- linux-2.6.36.orig/crypto/ocf/c7108/aes-7108.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/c7108/aes-7108.h 2010-11-09 20:28:04.102495305 +0100 -@@ -0,0 +1,134 @@ -+/* -+ * Copyright (C) 2006 Micronas USA -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored in part by the Defense Advanced Research Projects -+ * Agency (DARPA) and Air Force Research Laboratory, Air Force -+ * Materiel Command, USAF, under agreement number F30602-01-2-0537. -+ * -+ */ -+ -+#ifndef __AES_7108_H__ -+#define __AES_7108_H__ -+ -+/* Cypher 7108 AES Controller Hardware */ -+#define CCU_REG_BASE 0x1b500000 -+#define CCU_AES_REG_BASE (CCU_REG_BASE + 0x100) -+#define C7108_AES_KEY0_LO (0x0000) -+#define C7108_AES_KEY0_HI (0x0004) -+#define C7108_AES_KEY1_LO (0x0008) -+#define C7108_AES_KEY1_HI (0x000c) -+#define C7108_AES_KEY2_LO (0x0010) -+#define C7108_AES_KEY2_HI (0x0014) -+#define C7108_AES_KEY3_LO (0x0018) -+#define C7108_AES_KEY3_HI (0x001c) -+#define C7108_AES_KEY4_LO (0x0020) -+#define C7108_AES_KEY4_HI (0x0024) -+#define C7108_AES_KEY5_LO (0x0028) -+#define C7108_AES_KEY5_HI (0x002c) -+#define C7108_AES_KEY6_LO (0x0030) -+#define C7108_AES_KEY6_HI (0x0034) -+#define C7108_AES_KEY7_LO (0x0038) -+#define C7108_AES_KEY7_HI (0x003c) -+#define C7108_AES_IV0_LO (0x0040) -+#define C7108_AES_IV0_HI (0x0044) -+#define C7108_AES_IV1_LO (0x0048) -+#define C7108_AES_IV1_HI (0x004c) -+#define C7108_AES_IV2_LO (0x0050) -+#define C7108_AES_IV2_HI (0x0054) -+#define C7108_AES_IV3_LO (0x0058) -+#define C7108_AES_IV3_HI (0x005c) -+ -+#define C7108_AES_DMA_SRC0_LO (0x0068) /* Bits 0:15 */ -+#define C7108_AES_DMA_SRC0_HI (0x006c) /* Bits 27:16 */ -+#define C7108_AES_DMA_DST0_LO (0x0070) /* Bits 0:15 */ -+#define C7108_AES_DMA_DST0_HI (0x0074) /* Bits 27:16 */ -+#define C7108_AES_DMA_LEN (0x0078) /*Bytes:(Count+1)x16 */ -+ -+/* AES/Copy engine control register */ -+#define C7108_AES_CTRL (0x007c) /* AES control */ -+#define C7108_AES_CTRL_RS (1<<0) /* Which set of src/dst to use */ -+ -+/* AES Cipher mode, controlled by setting Bits 2:0 */ -+#define C7108_AES_CTRL_MODE_CBC 0 -+#define C7108_AES_CTRL_MODE_CFB (1<<0) -+#define C7108_AES_CTRL_MODE_OFB (1<<1) -+#define C7108_AES_CTRL_MODE_CTR ((1<<0)|(1<<1)) -+#define C7108_AES_CTRL_MODE_ECB (1<<2) -+ -+/* AES Key length , Bits 5:4 */ -+#define C7108_AES_KEY_LEN_128 0 /* 00 */ -+#define C7108_AES_KEY_LEN_192 (1<<4) /* 01 */ -+#define C7108_AES_KEY_LEN_256 (1<<5) /* 10 */ -+ -+/* AES Operation (crypt/decrypt), Bit 3 */ -+#define C7108_AES_DECRYPT (1<<3) /* Clear for encrypt */ -+#define C7108_AES_ENCRYPT 0 -+#define C7108_AES_INTR (1<<13) /* Set on done trans from 0->1*/ -+#define C7108_AES_GO (1<<14) /* Run */ -+#define C7108_AES_OP_DONE (1<<15) /* Set when complete */ -+ -+ -+/* Expanded key registers */ -+#define C7108_AES_EKEY0_LO (0x0080) -+#define C7108_AES_EKEY0_HI (0x0084) -+#define C7108_AES_EKEY1_LO (0x0088) -+#define C7108_AES_EKEY1_HI (0x008c) -+#define C7108_AES_EKEY2_LO (0x0090) -+#define C7108_AES_EKEY2_HI (0x0094) -+#define C7108_AES_EKEY3_LO (0x0098) -+#define C7108_AES_EKEY3_HI (0x009c) -+#define C7108_AES_EKEY4_LO (0x00a0) -+#define C7108_AES_EKEY4_HI (0x00a4) -+#define C7108_AES_EKEY5_LO (0x00a8) -+#define C7108_AES_EKEY5_HI (0x00ac) -+#define C7108_AES_EKEY6_LO (0x00b0) -+#define C7108_AES_EKEY6_HI (0x00b4) -+#define C7108_AES_EKEY7_LO (0x00b8) -+#define C7108_AES_EKEY7_HI (0x00bc) -+#define C7108_AES_OK (0x00fc) /* Reset: "OK" */ -+ -+#define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK) -+ -+/* Software session entry */ -+ -+#define HW_TYPE_CIPHER 0 -+#define SW_TYPE_HMAC 1 -+#define SW_TYPE_AUTH2 2 -+#define SW_TYPE_HASH 3 -+#define SW_TYPE_COMP 4 -+ -+struct cipher_7108 { -+ int xfm_type; -+ int cri_alg; -+ union { -+ struct { -+ char sw_key[HMAC_BLOCK_LEN]; -+ int sw_klen; -+ int sw_authlen; -+ } hmac; -+ } u; -+ struct cipher_7108 *next; -+}; -+ -+ -+ -+#endif /* __C7108_AES_7108_H__ */ -diff -Nur linux-2.6.36.orig/crypto/ocf/c7108/Makefile linux-2.6.36/crypto/ocf/c7108/Makefile ---- linux-2.6.36.orig/crypto/ocf/c7108/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/c7108/Makefile 2010-11-09 20:28:04.152495478 +0100 -@@ -0,0 +1,12 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+obj-$(CONFIG_OCF_C7108) += aes-7108.o -+ -+obj ?= . -+EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/Config.in linux-2.6.36/crypto/ocf/Config.in ---- linux-2.6.36.orig/crypto/ocf/Config.in 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/Config.in 2010-11-09 20:28:04.191247583 +0100 -@@ -0,0 +1,36 @@ -+############################################################################# -+ -+mainmenu_option next_comment -+comment 'OCF Configuration' -+tristate 'OCF (Open Cryptograhic Framework)' CONFIG_OCF_OCF -+dep_mbool ' enable fips RNG checks (fips check on RNG data before use)' \ -+ CONFIG_OCF_FIPS $CONFIG_OCF_OCF -+dep_mbool ' enable harvesting entropy for /dev/random' \ -+ CONFIG_OCF_RANDOMHARVEST $CONFIG_OCF_OCF -+dep_tristate ' cryptodev (user space support)' \ -+ CONFIG_OCF_CRYPTODEV $CONFIG_OCF_OCF -+dep_tristate ' cryptosoft (software crypto engine)' \ -+ CONFIG_OCF_CRYPTOSOFT $CONFIG_OCF_OCF -+dep_tristate ' safenet (HW crypto engine)' \ -+ CONFIG_OCF_SAFE $CONFIG_OCF_OCF -+dep_tristate ' IXP4xx (HW crypto engine)' \ -+ CONFIG_OCF_IXP4XX $CONFIG_OCF_OCF -+dep_mbool ' Enable IXP4xx HW to perform SHA1 and MD5 hashing (very slow)' \ -+ CONFIG_OCF_IXP4XX_SHA1_MD5 $CONFIG_OCF_IXP4XX -+dep_tristate ' hifn (HW crypto engine)' \ -+ CONFIG_OCF_HIFN $CONFIG_OCF_OCF -+dep_tristate ' talitos (HW crypto engine)' \ -+ CONFIG_OCF_TALITOS $CONFIG_OCF_OCF -+dep_tristate ' pasemi (HW crypto engine)' \ -+ CONFIG_OCF_PASEMI $CONFIG_OCF_OCF -+dep_tristate ' ep80579 (HW crypto engine)' \ -+ CONFIG_OCF_EP80579 $CONFIG_OCF_OCF -+dep_tristate ' Micronas c7108 (HW crypto engine)' \ -+ CONFIG_OCF_C7108 $CONFIG_OCF_OCF -+dep_tristate ' ocfnull (does no crypto)' \ -+ CONFIG_OCF_OCFNULL $CONFIG_OCF_OCF -+dep_tristate ' ocf-bench (HW crypto in-kernel benchmark)' \ -+ CONFIG_OCF_BENCH $CONFIG_OCF_OCF -+endmenu -+ -+############################################################################# -diff -Nur linux-2.6.36.orig/crypto/ocf/criov.c linux-2.6.36/crypto/ocf/criov.c ---- linux-2.6.36.orig/crypto/ocf/criov.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/criov.c 2010-11-09 20:28:04.232050075 +0100 -@@ -0,0 +1,215 @@ -+/* $OpenBSD: criov.c,v 1.9 2002/01/29 15:48:29 jason Exp $ */ -+ -+/* -+ * Linux port done by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * The license and original author are listed below. -+ * -+ * Copyright (c) 1999 Theo de Raadt -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+__FBSDID("$FreeBSD: src/sys/opencrypto/criov.c,v 1.5 2006/06/04 22:15:13 pjd Exp $"); -+ */ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+/* -+ * This macro is only for avoiding code duplication, as we need to skip -+ * given number of bytes in the same way in three functions below. -+ */ -+#define CUIO_SKIP() do { \ -+ KASSERT(off >= 0, ("%s: off %d < 0", __func__, off)); \ -+ KASSERT(len >= 0, ("%s: len %d < 0", __func__, len)); \ -+ while (off > 0) { \ -+ KASSERT(iol >= 0, ("%s: empty in skip", __func__)); \ -+ if (off < iov->iov_len) \ -+ break; \ -+ off -= iov->iov_len; \ -+ iol--; \ -+ iov++; \ -+ } \ -+} while (0) -+ -+void -+cuio_copydata(struct uio* uio, int off, int len, caddr_t cp) -+{ -+ struct iovec *iov = uio->uio_iov; -+ int iol = uio->uio_iovcnt; -+ unsigned count; -+ -+ CUIO_SKIP(); -+ while (len > 0) { -+ KASSERT(iol >= 0, ("%s: empty", __func__)); -+ count = min((int)(iov->iov_len - off), len); -+ memcpy(cp, ((caddr_t)iov->iov_base) + off, count); -+ len -= count; -+ cp += count; -+ off = 0; -+ iol--; -+ iov++; -+ } -+} -+ -+void -+cuio_copyback(struct uio* uio, int off, int len, caddr_t cp) -+{ -+ struct iovec *iov = uio->uio_iov; -+ int iol = uio->uio_iovcnt; -+ unsigned count; -+ -+ CUIO_SKIP(); -+ while (len > 0) { -+ KASSERT(iol >= 0, ("%s: empty", __func__)); -+ count = min((int)(iov->iov_len - off), len); -+ memcpy(((caddr_t)iov->iov_base) + off, cp, count); -+ len -= count; -+ cp += count; -+ off = 0; -+ iol--; -+ iov++; -+ } -+} -+ -+/* -+ * Return a pointer to iov/offset of location in iovec list. -+ */ -+struct iovec * -+cuio_getptr(struct uio *uio, int loc, int *off) -+{ -+ struct iovec *iov = uio->uio_iov; -+ int iol = uio->uio_iovcnt; -+ -+ while (loc >= 0) { -+ /* Normal end of search */ -+ if (loc < iov->iov_len) { -+ *off = loc; -+ return (iov); -+ } -+ -+ loc -= iov->iov_len; -+ if (iol == 0) { -+ if (loc == 0) { -+ /* Point at the end of valid data */ -+ *off = iov->iov_len; -+ return (iov); -+ } else -+ return (NULL); -+ } else { -+ iov++, iol--; -+ } -+ } -+ -+ return (NULL); -+} -+ -+EXPORT_SYMBOL(cuio_copyback); -+EXPORT_SYMBOL(cuio_copydata); -+EXPORT_SYMBOL(cuio_getptr); -+ -+ -+static void -+skb_copy_bits_back(struct sk_buff *skb, int offset, caddr_t cp, int len) -+{ -+ int i; -+ if (offset < skb_headlen(skb)) { -+ memcpy(skb->data + offset, cp, min_t(int, skb_headlen(skb), len)); -+ len -= skb_headlen(skb); -+ cp += skb_headlen(skb); -+ } -+ offset -= skb_headlen(skb); -+ for (i = 0; len > 0 && i < skb_shinfo(skb)->nr_frags; i++) { -+ if (offset < skb_shinfo(skb)->frags[i].size) { -+ memcpy(page_address(skb_shinfo(skb)->frags[i].page) + -+ skb_shinfo(skb)->frags[i].page_offset, -+ cp, min_t(int, skb_shinfo(skb)->frags[i].size, len)); -+ len -= skb_shinfo(skb)->frags[i].size; -+ cp += skb_shinfo(skb)->frags[i].size; -+ } -+ offset -= skb_shinfo(skb)->frags[i].size; -+ } -+} -+ -+void -+crypto_copyback(int flags, caddr_t buf, int off, int size, caddr_t in) -+{ -+ -+ if ((flags & CRYPTO_F_SKBUF) != 0) -+ skb_copy_bits_back((struct sk_buff *)buf, off, in, size); -+ else if ((flags & CRYPTO_F_IOV) != 0) -+ cuio_copyback((struct uio *)buf, off, size, in); -+ else -+ bcopy(in, buf + off, size); -+} -+ -+void -+crypto_copydata(int flags, caddr_t buf, int off, int size, caddr_t out) -+{ -+ -+ if ((flags & CRYPTO_F_SKBUF) != 0) -+ skb_copy_bits((struct sk_buff *)buf, off, out, size); -+ else if ((flags & CRYPTO_F_IOV) != 0) -+ cuio_copydata((struct uio *)buf, off, size, out); -+ else -+ bcopy(buf + off, out, size); -+} -+ -+int -+crypto_apply(int flags, caddr_t buf, int off, int len, -+ int (*f)(void *, void *, u_int), void *arg) -+{ -+#if 0 -+ int error; -+ -+ if ((flags & CRYPTO_F_SKBUF) != 0) -+ error = XXXXXX((struct mbuf *)buf, off, len, f, arg); -+ else if ((flags & CRYPTO_F_IOV) != 0) -+ error = cuio_apply((struct uio *)buf, off, len, f, arg); -+ else -+ error = (*f)(arg, buf + off, len); -+ return (error); -+#else -+ KASSERT(0, ("crypto_apply not implemented!\n")); -+#endif -+ return 0; -+} -+ -+EXPORT_SYMBOL(crypto_copyback); -+EXPORT_SYMBOL(crypto_copydata); -+EXPORT_SYMBOL(crypto_apply); -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/crypto.c linux-2.6.36/crypto/ocf/crypto.c ---- linux-2.6.36.orig/crypto/ocf/crypto.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/crypto.c 2010-11-09 20:28:04.272495385 +0100 -@@ -0,0 +1,1784 @@ -+/*- -+ * Linux port done by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * The license and original author are listed below. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * Copyright (c) 2002-2006 Sam Leffler. All rights reserved. -+ * -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#if 0 -+#include -+__FBSDID("$FreeBSD: src/sys/opencrypto/crypto.c,v 1.27 2007/03/21 03:42:51 sam Exp $"); -+#endif -+ -+/* -+ * Cryptographic Subsystem. -+ * -+ * This code is derived from the Openbsd Cryptographic Framework (OCF) -+ * that has the copyright shown below. Very little of the original -+ * code remains. -+ */ -+/*- -+ * The author of this code is Angelos D. Keromytis (angelos@cis.upenn.edu) -+ * -+ * This code was written by Angelos D. Keromytis in Athens, Greece, in -+ * February 2000. Network Security Technologies Inc. (NSTI) kindly -+ * supported the development of this code. -+ * -+ * Copyright (c) 2000, 2001 Angelos D. Keromytis -+ * -+ * Permission to use, copy, and modify this software with or without fee -+ * is hereby granted, provided that this entire notice is included in -+ * all source code copies of any software which is or includes a copy or -+ * modification of this software. -+ * -+ * THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR -+ * IMPLIED WARRANTY. IN PARTICULAR, NONE OF THE AUTHORS MAKES ANY -+ * REPRESENTATION OR WARRANTY OF ANY KIND CONCERNING THE -+ * MERCHANTABILITY OF THIS SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR -+ * PURPOSE. -+ * -+__FBSDID("$FreeBSD: src/sys/opencrypto/crypto.c,v 1.16 2005/01/07 02:29:16 imp Exp $"); -+ */ -+ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* -+ * keep track of whether or not we have been initialised, a big -+ * issue if we are linked into the kernel and a driver gets started before -+ * us -+ */ -+static int crypto_initted = 0; -+ -+/* -+ * Crypto drivers register themselves by allocating a slot in the -+ * crypto_drivers table with crypto_get_driverid() and then registering -+ * each algorithm they support with crypto_register() and crypto_kregister(). -+ */ -+ -+/* -+ * lock on driver table -+ * we track its state as spin_is_locked does not do anything on non-SMP boxes -+ */ -+static spinlock_t crypto_drivers_lock; -+static int crypto_drivers_locked; /* for non-SMP boxes */ -+ -+#define CRYPTO_DRIVER_LOCK() \ -+ ({ \ -+ spin_lock_irqsave(&crypto_drivers_lock, d_flags); \ -+ crypto_drivers_locked = 1; \ -+ dprintk("%s,%d: DRIVER_LOCK()\n", __FILE__, __LINE__); \ -+ }) -+#define CRYPTO_DRIVER_UNLOCK() \ -+ ({ \ -+ dprintk("%s,%d: DRIVER_UNLOCK()\n", __FILE__, __LINE__); \ -+ crypto_drivers_locked = 0; \ -+ spin_unlock_irqrestore(&crypto_drivers_lock, d_flags); \ -+ }) -+#define CRYPTO_DRIVER_ASSERT() \ -+ ({ \ -+ if (!crypto_drivers_locked) { \ -+ dprintk("%s,%d: DRIVER_ASSERT!\n", __FILE__, __LINE__); \ -+ } \ -+ }) -+ -+/* -+ * Crypto device/driver capabilities structure. -+ * -+ * Synchronization: -+ * (d) - protected by CRYPTO_DRIVER_LOCK() -+ * (q) - protected by CRYPTO_Q_LOCK() -+ * Not tagged fields are read-only. -+ */ -+struct cryptocap { -+ device_t cc_dev; /* (d) device/driver */ -+ u_int32_t cc_sessions; /* (d) # of sessions */ -+ u_int32_t cc_koperations; /* (d) # os asym operations */ -+ /* -+ * Largest possible operator length (in bits) for each type of -+ * encryption algorithm. XXX not used -+ */ -+ u_int16_t cc_max_op_len[CRYPTO_ALGORITHM_MAX + 1]; -+ u_int8_t cc_alg[CRYPTO_ALGORITHM_MAX + 1]; -+ u_int8_t cc_kalg[CRK_ALGORITHM_MAX + 1]; -+ -+ int cc_flags; /* (d) flags */ -+#define CRYPTOCAP_F_CLEANUP 0x80000000 /* needs resource cleanup */ -+ int cc_qblocked; /* (q) symmetric q blocked */ -+ int cc_kqblocked; /* (q) asymmetric q blocked */ -+ -+ int cc_unqblocked; /* (q) symmetric q blocked */ -+ int cc_unkqblocked; /* (q) asymmetric q blocked */ -+}; -+static struct cryptocap *crypto_drivers = NULL; -+static int crypto_drivers_num = 0; -+ -+/* -+ * There are two queues for crypto requests; one for symmetric (e.g. -+ * cipher) operations and one for asymmetric (e.g. MOD)operations. -+ * A single mutex is used to lock access to both queues. We could -+ * have one per-queue but having one simplifies handling of block/unblock -+ * operations. -+ */ -+static int crp_sleep = 0; -+static LIST_HEAD(crp_q); /* request queues */ -+static LIST_HEAD(crp_kq); -+ -+static spinlock_t crypto_q_lock; -+ -+int crypto_all_qblocked = 0; /* protect with Q_LOCK */ -+module_param(crypto_all_qblocked, int, 0444); -+MODULE_PARM_DESC(crypto_all_qblocked, "Are all crypto queues blocked"); -+ -+int crypto_all_kqblocked = 0; /* protect with Q_LOCK */ -+module_param(crypto_all_kqblocked, int, 0444); -+MODULE_PARM_DESC(crypto_all_kqblocked, "Are all asym crypto queues blocked"); -+ -+#define CRYPTO_Q_LOCK() \ -+ ({ \ -+ spin_lock_irqsave(&crypto_q_lock, q_flags); \ -+ dprintk("%s,%d: Q_LOCK()\n", __FILE__, __LINE__); \ -+ }) -+#define CRYPTO_Q_UNLOCK() \ -+ ({ \ -+ dprintk("%s,%d: Q_UNLOCK()\n", __FILE__, __LINE__); \ -+ spin_unlock_irqrestore(&crypto_q_lock, q_flags); \ -+ }) -+ -+/* -+ * There are two queues for processing completed crypto requests; one -+ * for the symmetric and one for the asymmetric ops. We only need one -+ * but have two to avoid type futzing (cryptop vs. cryptkop). A single -+ * mutex is used to lock access to both queues. Note that this lock -+ * must be separate from the lock on request queues to insure driver -+ * callbacks don't generate lock order reversals. -+ */ -+static LIST_HEAD(crp_ret_q); /* callback queues */ -+static LIST_HEAD(crp_ret_kq); -+ -+static spinlock_t crypto_ret_q_lock; -+#define CRYPTO_RETQ_LOCK() \ -+ ({ \ -+ spin_lock_irqsave(&crypto_ret_q_lock, r_flags); \ -+ dprintk("%s,%d: RETQ_LOCK\n", __FILE__, __LINE__); \ -+ }) -+#define CRYPTO_RETQ_UNLOCK() \ -+ ({ \ -+ dprintk("%s,%d: RETQ_UNLOCK\n", __FILE__, __LINE__); \ -+ spin_unlock_irqrestore(&crypto_ret_q_lock, r_flags); \ -+ }) -+#define CRYPTO_RETQ_EMPTY() (list_empty(&crp_ret_q) && list_empty(&crp_ret_kq)) -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) -+static kmem_cache_t *cryptop_zone; -+static kmem_cache_t *cryptodesc_zone; -+#else -+static struct kmem_cache *cryptop_zone; -+static struct kmem_cache *cryptodesc_zone; -+#endif -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) -+#include -+#define kill_proc(p,s,v) send_sig(s,find_task_by_vpid(p),0) -+#endif -+ -+#define debug crypto_debug -+int crypto_debug = 0; -+module_param(crypto_debug, int, 0644); -+MODULE_PARM_DESC(crypto_debug, "Enable debug"); -+EXPORT_SYMBOL(crypto_debug); -+ -+/* -+ * Maximum number of outstanding crypto requests before we start -+ * failing requests. We need this to prevent DOS when too many -+ * requests are arriving for us to keep up. Otherwise we will -+ * run the system out of memory. Since crypto is slow, we are -+ * usually the bottleneck that needs to say, enough is enough. -+ * -+ * We cannot print errors when this condition occurs, we are already too -+ * slow, printing anything will just kill us -+ */ -+ -+static int crypto_q_cnt = 0; -+module_param(crypto_q_cnt, int, 0444); -+MODULE_PARM_DESC(crypto_q_cnt, -+ "Current number of outstanding crypto requests"); -+ -+static int crypto_q_max = 1000; -+module_param(crypto_q_max, int, 0644); -+MODULE_PARM_DESC(crypto_q_max, -+ "Maximum number of outstanding crypto requests"); -+ -+#define bootverbose crypto_verbose -+static int crypto_verbose = 0; -+module_param(crypto_verbose, int, 0644); -+MODULE_PARM_DESC(crypto_verbose, -+ "Enable verbose crypto startup"); -+ -+int crypto_usercrypto = 1; /* userland may do crypto reqs */ -+module_param(crypto_usercrypto, int, 0644); -+MODULE_PARM_DESC(crypto_usercrypto, -+ "Enable/disable user-mode access to crypto support"); -+ -+int crypto_userasymcrypto = 1; /* userland may do asym crypto reqs */ -+module_param(crypto_userasymcrypto, int, 0644); -+MODULE_PARM_DESC(crypto_userasymcrypto, -+ "Enable/disable user-mode access to asymmetric crypto support"); -+ -+int crypto_devallowsoft = 0; /* only use hardware crypto */ -+module_param(crypto_devallowsoft, int, 0644); -+MODULE_PARM_DESC(crypto_devallowsoft, -+ "Enable/disable use of software crypto support"); -+ -+/* -+ * This parameter controls the maximum number of crypto operations to -+ * do consecutively in the crypto kernel thread before scheduling to allow -+ * other processes to run. Without it, it is possible to get into a -+ * situation where the crypto thread never allows any other processes to run. -+ * Default to 1000 which should be less than one second. -+ */ -+static int crypto_max_loopcount = 1000; -+module_param(crypto_max_loopcount, int, 0644); -+MODULE_PARM_DESC(crypto_max_loopcount, -+ "Maximum number of crypto ops to do before yielding to other processes"); -+ -+static pid_t cryptoproc = (pid_t) -1; -+static struct completion cryptoproc_exited; -+static DECLARE_WAIT_QUEUE_HEAD(cryptoproc_wait); -+static pid_t cryptoretproc = (pid_t) -1; -+static struct completion cryptoretproc_exited; -+static DECLARE_WAIT_QUEUE_HEAD(cryptoretproc_wait); -+ -+static int crypto_proc(void *arg); -+static int crypto_ret_proc(void *arg); -+static int crypto_invoke(struct cryptocap *cap, struct cryptop *crp, int hint); -+static int crypto_kinvoke(struct cryptkop *krp, int flags); -+static void crypto_exit(void); -+static int crypto_init(void); -+ -+static struct cryptostats cryptostats; -+ -+static struct cryptocap * -+crypto_checkdriver(u_int32_t hid) -+{ -+ if (crypto_drivers == NULL) -+ return NULL; -+ return (hid >= crypto_drivers_num ? NULL : &crypto_drivers[hid]); -+} -+ -+/* -+ * Compare a driver's list of supported algorithms against another -+ * list; return non-zero if all algorithms are supported. -+ */ -+static int -+driver_suitable(const struct cryptocap *cap, const struct cryptoini *cri) -+{ -+ const struct cryptoini *cr; -+ -+ /* See if all the algorithms are supported. */ -+ for (cr = cri; cr; cr = cr->cri_next) -+ if (cap->cc_alg[cr->cri_alg] == 0) -+ return 0; -+ return 1; -+} -+ -+/* -+ * Select a driver for a new session that supports the specified -+ * algorithms and, optionally, is constrained according to the flags. -+ * The algorithm we use here is pretty stupid; just use the -+ * first driver that supports all the algorithms we need. If there -+ * are multiple drivers we choose the driver with the fewest active -+ * sessions. We prefer hardware-backed drivers to software ones. -+ * -+ * XXX We need more smarts here (in real life too, but that's -+ * XXX another story altogether). -+ */ -+static struct cryptocap * -+crypto_select_driver(const struct cryptoini *cri, int flags) -+{ -+ struct cryptocap *cap, *best; -+ int match, hid; -+ -+ CRYPTO_DRIVER_ASSERT(); -+ -+ /* -+ * Look first for hardware crypto devices if permitted. -+ */ -+ if (flags & CRYPTOCAP_F_HARDWARE) -+ match = CRYPTOCAP_F_HARDWARE; -+ else -+ match = CRYPTOCAP_F_SOFTWARE; -+ best = NULL; -+again: -+ for (hid = 0; hid < crypto_drivers_num; hid++) { -+ cap = &crypto_drivers[hid]; -+ /* -+ * If it's not initialized, is in the process of -+ * going away, or is not appropriate (hardware -+ * or software based on match), then skip. -+ */ -+ if (cap->cc_dev == NULL || -+ (cap->cc_flags & CRYPTOCAP_F_CLEANUP) || -+ (cap->cc_flags & match) == 0) -+ continue; -+ -+ /* verify all the algorithms are supported. */ -+ if (driver_suitable(cap, cri)) { -+ if (best == NULL || -+ cap->cc_sessions < best->cc_sessions) -+ best = cap; -+ } -+ } -+ if (best != NULL) -+ return best; -+ if (match == CRYPTOCAP_F_HARDWARE && (flags & CRYPTOCAP_F_SOFTWARE)) { -+ /* sort of an Algol 68-style for loop */ -+ match = CRYPTOCAP_F_SOFTWARE; -+ goto again; -+ } -+ return best; -+} -+ -+/* -+ * Create a new session. The crid argument specifies a crypto -+ * driver to use or constraints on a driver to select (hardware -+ * only, software only, either). Whatever driver is selected -+ * must be capable of the requested crypto algorithms. -+ */ -+int -+crypto_newsession(u_int64_t *sid, struct cryptoini *cri, int crid) -+{ -+ struct cryptocap *cap; -+ u_int32_t hid, lid; -+ int err; -+ unsigned long d_flags; -+ -+ CRYPTO_DRIVER_LOCK(); -+ if ((crid & (CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE)) == 0) { -+ /* -+ * Use specified driver; verify it is capable. -+ */ -+ cap = crypto_checkdriver(crid); -+ if (cap != NULL && !driver_suitable(cap, cri)) -+ cap = NULL; -+ } else { -+ /* -+ * No requested driver; select based on crid flags. -+ */ -+ cap = crypto_select_driver(cri, crid); -+ /* -+ * if NULL then can't do everything in one session. -+ * XXX Fix this. We need to inject a "virtual" session -+ * XXX layer right about here. -+ */ -+ } -+ if (cap != NULL) { -+ /* Call the driver initialization routine. */ -+ hid = cap - crypto_drivers; -+ lid = hid; /* Pass the driver ID. */ -+ cap->cc_sessions++; -+ CRYPTO_DRIVER_UNLOCK(); -+ err = CRYPTODEV_NEWSESSION(cap->cc_dev, &lid, cri); -+ CRYPTO_DRIVER_LOCK(); -+ if (err == 0) { -+ (*sid) = (cap->cc_flags & 0xff000000) -+ | (hid & 0x00ffffff); -+ (*sid) <<= 32; -+ (*sid) |= (lid & 0xffffffff); -+ } else -+ cap->cc_sessions--; -+ } else -+ err = EINVAL; -+ CRYPTO_DRIVER_UNLOCK(); -+ return err; -+} -+ -+static void -+crypto_remove(struct cryptocap *cap) -+{ -+ CRYPTO_DRIVER_ASSERT(); -+ if (cap->cc_sessions == 0 && cap->cc_koperations == 0) -+ bzero(cap, sizeof(*cap)); -+} -+ -+/* -+ * Delete an existing session (or a reserved session on an unregistered -+ * driver). -+ */ -+int -+crypto_freesession(u_int64_t sid) -+{ -+ struct cryptocap *cap; -+ u_int32_t hid; -+ int err = 0; -+ unsigned long d_flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ CRYPTO_DRIVER_LOCK(); -+ -+ if (crypto_drivers == NULL) { -+ err = EINVAL; -+ goto done; -+ } -+ -+ /* Determine two IDs. */ -+ hid = CRYPTO_SESID2HID(sid); -+ -+ if (hid >= crypto_drivers_num) { -+ dprintk("%s - INVALID DRIVER NUM %d\n", __FUNCTION__, hid); -+ err = ENOENT; -+ goto done; -+ } -+ cap = &crypto_drivers[hid]; -+ -+ if (cap->cc_dev) { -+ CRYPTO_DRIVER_UNLOCK(); -+ /* Call the driver cleanup routine, if available, unlocked. */ -+ err = CRYPTODEV_FREESESSION(cap->cc_dev, sid); -+ CRYPTO_DRIVER_LOCK(); -+ } -+ -+ if (cap->cc_sessions) -+ cap->cc_sessions--; -+ -+ if (cap->cc_flags & CRYPTOCAP_F_CLEANUP) -+ crypto_remove(cap); -+ -+done: -+ CRYPTO_DRIVER_UNLOCK(); -+ return err; -+} -+ -+/* -+ * Return an unused driver id. Used by drivers prior to registering -+ * support for the algorithms they handle. -+ */ -+int32_t -+crypto_get_driverid(device_t dev, int flags) -+{ -+ struct cryptocap *newdrv; -+ int i; -+ unsigned long d_flags; -+ -+ if ((flags & (CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE)) == 0) { -+ printf("%s: no flags specified when registering driver\n", -+ device_get_nameunit(dev)); -+ return -1; -+ } -+ -+ CRYPTO_DRIVER_LOCK(); -+ -+ for (i = 0; i < crypto_drivers_num; i++) { -+ if (crypto_drivers[i].cc_dev == NULL && -+ (crypto_drivers[i].cc_flags & CRYPTOCAP_F_CLEANUP) == 0) { -+ break; -+ } -+ } -+ -+ /* Out of entries, allocate some more. */ -+ if (i == crypto_drivers_num) { -+ /* Be careful about wrap-around. */ -+ if (2 * crypto_drivers_num <= crypto_drivers_num) { -+ CRYPTO_DRIVER_UNLOCK(); -+ printk("crypto: driver count wraparound!\n"); -+ return -1; -+ } -+ -+ newdrv = kmalloc(2 * crypto_drivers_num * sizeof(struct cryptocap), -+ GFP_KERNEL); -+ if (newdrv == NULL) { -+ CRYPTO_DRIVER_UNLOCK(); -+ printk("crypto: no space to expand driver table!\n"); -+ return -1; -+ } -+ -+ memcpy(newdrv, crypto_drivers, -+ crypto_drivers_num * sizeof(struct cryptocap)); -+ memset(&newdrv[crypto_drivers_num], 0, -+ crypto_drivers_num * sizeof(struct cryptocap)); -+ -+ crypto_drivers_num *= 2; -+ -+ kfree(crypto_drivers); -+ crypto_drivers = newdrv; -+ } -+ -+ /* NB: state is zero'd on free */ -+ crypto_drivers[i].cc_sessions = 1; /* Mark */ -+ crypto_drivers[i].cc_dev = dev; -+ crypto_drivers[i].cc_flags = flags; -+ if (bootverbose) -+ printf("crypto: assign %s driver id %u, flags %u\n", -+ device_get_nameunit(dev), i, flags); -+ -+ CRYPTO_DRIVER_UNLOCK(); -+ -+ return i; -+} -+ -+/* -+ * Lookup a driver by name. We match against the full device -+ * name and unit, and against just the name. The latter gives -+ * us a simple widlcarding by device name. On success return the -+ * driver/hardware identifier; otherwise return -1. -+ */ -+int -+crypto_find_driver(const char *match) -+{ -+ int i, len = strlen(match); -+ unsigned long d_flags; -+ -+ CRYPTO_DRIVER_LOCK(); -+ for (i = 0; i < crypto_drivers_num; i++) { -+ device_t dev = crypto_drivers[i].cc_dev; -+ if (dev == NULL || -+ (crypto_drivers[i].cc_flags & CRYPTOCAP_F_CLEANUP)) -+ continue; -+ if (strncmp(match, device_get_nameunit(dev), len) == 0 || -+ strncmp(match, device_get_name(dev), len) == 0) -+ break; -+ } -+ CRYPTO_DRIVER_UNLOCK(); -+ return i < crypto_drivers_num ? i : -1; -+} -+ -+/* -+ * Return the device_t for the specified driver or NULL -+ * if the driver identifier is invalid. -+ */ -+device_t -+crypto_find_device_byhid(int hid) -+{ -+ struct cryptocap *cap = crypto_checkdriver(hid); -+ return cap != NULL ? cap->cc_dev : NULL; -+} -+ -+/* -+ * Return the device/driver capabilities. -+ */ -+int -+crypto_getcaps(int hid) -+{ -+ struct cryptocap *cap = crypto_checkdriver(hid); -+ return cap != NULL ? cap->cc_flags : 0; -+} -+ -+/* -+ * Register support for a key-related algorithm. This routine -+ * is called once for each algorithm supported a driver. -+ */ -+int -+crypto_kregister(u_int32_t driverid, int kalg, u_int32_t flags) -+{ -+ struct cryptocap *cap; -+ int err; -+ unsigned long d_flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ CRYPTO_DRIVER_LOCK(); -+ -+ cap = crypto_checkdriver(driverid); -+ if (cap != NULL && -+ (CRK_ALGORITM_MIN <= kalg && kalg <= CRK_ALGORITHM_MAX)) { -+ /* -+ * XXX Do some performance testing to determine placing. -+ * XXX We probably need an auxiliary data structure that -+ * XXX describes relative performances. -+ */ -+ -+ cap->cc_kalg[kalg] = flags | CRYPTO_ALG_FLAG_SUPPORTED; -+ if (bootverbose) -+ printf("crypto: %s registers key alg %u flags %u\n" -+ , device_get_nameunit(cap->cc_dev) -+ , kalg -+ , flags -+ ); -+ err = 0; -+ } else -+ err = EINVAL; -+ -+ CRYPTO_DRIVER_UNLOCK(); -+ return err; -+} -+ -+/* -+ * Register support for a non-key-related algorithm. This routine -+ * is called once for each such algorithm supported by a driver. -+ */ -+int -+crypto_register(u_int32_t driverid, int alg, u_int16_t maxoplen, -+ u_int32_t flags) -+{ -+ struct cryptocap *cap; -+ int err; -+ unsigned long d_flags; -+ -+ dprintk("%s(id=0x%x, alg=%d, maxoplen=%d, flags=0x%x)\n", __FUNCTION__, -+ driverid, alg, maxoplen, flags); -+ -+ CRYPTO_DRIVER_LOCK(); -+ -+ cap = crypto_checkdriver(driverid); -+ /* NB: algorithms are in the range [1..max] */ -+ if (cap != NULL && -+ (CRYPTO_ALGORITHM_MIN <= alg && alg <= CRYPTO_ALGORITHM_MAX)) { -+ /* -+ * XXX Do some performance testing to determine placing. -+ * XXX We probably need an auxiliary data structure that -+ * XXX describes relative performances. -+ */ -+ -+ cap->cc_alg[alg] = flags | CRYPTO_ALG_FLAG_SUPPORTED; -+ cap->cc_max_op_len[alg] = maxoplen; -+ if (bootverbose) -+ printf("crypto: %s registers alg %u flags %u maxoplen %u\n" -+ , device_get_nameunit(cap->cc_dev) -+ , alg -+ , flags -+ , maxoplen -+ ); -+ cap->cc_sessions = 0; /* Unmark */ -+ err = 0; -+ } else -+ err = EINVAL; -+ -+ CRYPTO_DRIVER_UNLOCK(); -+ return err; -+} -+ -+static void -+driver_finis(struct cryptocap *cap) -+{ -+ u_int32_t ses, kops; -+ -+ CRYPTO_DRIVER_ASSERT(); -+ -+ ses = cap->cc_sessions; -+ kops = cap->cc_koperations; -+ bzero(cap, sizeof(*cap)); -+ if (ses != 0 || kops != 0) { -+ /* -+ * If there are pending sessions, -+ * just mark as invalid. -+ */ -+ cap->cc_flags |= CRYPTOCAP_F_CLEANUP; -+ cap->cc_sessions = ses; -+ cap->cc_koperations = kops; -+ } -+} -+ -+/* -+ * Unregister a crypto driver. If there are pending sessions using it, -+ * leave enough information around so that subsequent calls using those -+ * sessions will correctly detect the driver has been unregistered and -+ * reroute requests. -+ */ -+int -+crypto_unregister(u_int32_t driverid, int alg) -+{ -+ struct cryptocap *cap; -+ int i, err; -+ unsigned long d_flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ CRYPTO_DRIVER_LOCK(); -+ -+ cap = crypto_checkdriver(driverid); -+ if (cap != NULL && -+ (CRYPTO_ALGORITHM_MIN <= alg && alg <= CRYPTO_ALGORITHM_MAX) && -+ cap->cc_alg[alg] != 0) { -+ cap->cc_alg[alg] = 0; -+ cap->cc_max_op_len[alg] = 0; -+ -+ /* Was this the last algorithm ? */ -+ for (i = 1; i <= CRYPTO_ALGORITHM_MAX; i++) -+ if (cap->cc_alg[i] != 0) -+ break; -+ -+ if (i == CRYPTO_ALGORITHM_MAX + 1) -+ driver_finis(cap); -+ err = 0; -+ } else -+ err = EINVAL; -+ CRYPTO_DRIVER_UNLOCK(); -+ return err; -+} -+ -+/* -+ * Unregister all algorithms associated with a crypto driver. -+ * If there are pending sessions using it, leave enough information -+ * around so that subsequent calls using those sessions will -+ * correctly detect the driver has been unregistered and reroute -+ * requests. -+ */ -+int -+crypto_unregister_all(u_int32_t driverid) -+{ -+ struct cryptocap *cap; -+ int err; -+ unsigned long d_flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ CRYPTO_DRIVER_LOCK(); -+ cap = crypto_checkdriver(driverid); -+ if (cap != NULL) { -+ driver_finis(cap); -+ err = 0; -+ } else -+ err = EINVAL; -+ CRYPTO_DRIVER_UNLOCK(); -+ -+ return err; -+} -+ -+/* -+ * Clear blockage on a driver. The what parameter indicates whether -+ * the driver is now ready for cryptop's and/or cryptokop's. -+ */ -+int -+crypto_unblock(u_int32_t driverid, int what) -+{ -+ struct cryptocap *cap; -+ int err; -+ unsigned long q_flags; -+ -+ CRYPTO_Q_LOCK(); -+ cap = crypto_checkdriver(driverid); -+ if (cap != NULL) { -+ if (what & CRYPTO_SYMQ) { -+ cap->cc_qblocked = 0; -+ cap->cc_unqblocked = 0; -+ crypto_all_qblocked = 0; -+ } -+ if (what & CRYPTO_ASYMQ) { -+ cap->cc_kqblocked = 0; -+ cap->cc_unkqblocked = 0; -+ crypto_all_kqblocked = 0; -+ } -+ if (crp_sleep) -+ wake_up_interruptible(&cryptoproc_wait); -+ err = 0; -+ } else -+ err = EINVAL; -+ CRYPTO_Q_UNLOCK(); //DAVIDM should this be a driver lock -+ -+ return err; -+} -+ -+/* -+ * Add a crypto request to a queue, to be processed by the kernel thread. -+ */ -+int -+crypto_dispatch(struct cryptop *crp) -+{ -+ struct cryptocap *cap; -+ int result = -1; -+ unsigned long q_flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ cryptostats.cs_ops++; -+ -+ CRYPTO_Q_LOCK(); -+ if (crypto_q_cnt >= crypto_q_max) { -+ CRYPTO_Q_UNLOCK(); -+ cryptostats.cs_drops++; -+ return ENOMEM; -+ } -+ crypto_q_cnt++; -+ -+ /* make sure we are starting a fresh run on this crp. */ -+ crp->crp_flags &= ~CRYPTO_F_DONE; -+ crp->crp_etype = 0; -+ -+ /* -+ * Caller marked the request to be processed immediately; dispatch -+ * it directly to the driver unless the driver is currently blocked. -+ */ -+ if ((crp->crp_flags & CRYPTO_F_BATCH) == 0) { -+ int hid = CRYPTO_SESID2HID(crp->crp_sid); -+ cap = crypto_checkdriver(hid); -+ /* Driver cannot disappear when there is an active session. */ -+ KASSERT(cap != NULL, ("%s: Driver disappeared.", __func__)); -+ if (!cap->cc_qblocked) { -+ crypto_all_qblocked = 0; -+ crypto_drivers[hid].cc_unqblocked = 1; -+ CRYPTO_Q_UNLOCK(); -+ result = crypto_invoke(cap, crp, 0); -+ CRYPTO_Q_LOCK(); -+ if (result == ERESTART) -+ if (crypto_drivers[hid].cc_unqblocked) -+ crypto_drivers[hid].cc_qblocked = 1; -+ crypto_drivers[hid].cc_unqblocked = 0; -+ } -+ } -+ if (result == ERESTART) { -+ /* -+ * The driver ran out of resources, mark the -+ * driver ``blocked'' for cryptop's and put -+ * the request back in the queue. It would -+ * best to put the request back where we got -+ * it but that's hard so for now we put it -+ * at the front. This should be ok; putting -+ * it at the end does not work. -+ */ -+ list_add(&crp->crp_next, &crp_q); -+ cryptostats.cs_blocks++; -+ result = 0; -+ } else if (result == -1) { -+ TAILQ_INSERT_TAIL(&crp_q, crp, crp_next); -+ result = 0; -+ } -+ if (crp_sleep) -+ wake_up_interruptible(&cryptoproc_wait); -+ CRYPTO_Q_UNLOCK(); -+ return result; -+} -+ -+/* -+ * Add an asymetric crypto request to a queue, -+ * to be processed by the kernel thread. -+ */ -+int -+crypto_kdispatch(struct cryptkop *krp) -+{ -+ int error; -+ unsigned long q_flags; -+ -+ cryptostats.cs_kops++; -+ -+ error = crypto_kinvoke(krp, krp->krp_crid); -+ if (error == ERESTART) { -+ CRYPTO_Q_LOCK(); -+ TAILQ_INSERT_TAIL(&crp_kq, krp, krp_next); -+ if (crp_sleep) -+ wake_up_interruptible(&cryptoproc_wait); -+ CRYPTO_Q_UNLOCK(); -+ error = 0; -+ } -+ return error; -+} -+ -+/* -+ * Verify a driver is suitable for the specified operation. -+ */ -+static __inline int -+kdriver_suitable(const struct cryptocap *cap, const struct cryptkop *krp) -+{ -+ return (cap->cc_kalg[krp->krp_op] & CRYPTO_ALG_FLAG_SUPPORTED) != 0; -+} -+ -+/* -+ * Select a driver for an asym operation. The driver must -+ * support the necessary algorithm. The caller can constrain -+ * which device is selected with the flags parameter. The -+ * algorithm we use here is pretty stupid; just use the first -+ * driver that supports the algorithms we need. If there are -+ * multiple suitable drivers we choose the driver with the -+ * fewest active operations. We prefer hardware-backed -+ * drivers to software ones when either may be used. -+ */ -+static struct cryptocap * -+crypto_select_kdriver(const struct cryptkop *krp, int flags) -+{ -+ struct cryptocap *cap, *best, *blocked; -+ int match, hid; -+ -+ CRYPTO_DRIVER_ASSERT(); -+ -+ /* -+ * Look first for hardware crypto devices if permitted. -+ */ -+ if (flags & CRYPTOCAP_F_HARDWARE) -+ match = CRYPTOCAP_F_HARDWARE; -+ else -+ match = CRYPTOCAP_F_SOFTWARE; -+ best = NULL; -+ blocked = NULL; -+again: -+ for (hid = 0; hid < crypto_drivers_num; hid++) { -+ cap = &crypto_drivers[hid]; -+ /* -+ * If it's not initialized, is in the process of -+ * going away, or is not appropriate (hardware -+ * or software based on match), then skip. -+ */ -+ if (cap->cc_dev == NULL || -+ (cap->cc_flags & CRYPTOCAP_F_CLEANUP) || -+ (cap->cc_flags & match) == 0) -+ continue; -+ -+ /* verify all the algorithms are supported. */ -+ if (kdriver_suitable(cap, krp)) { -+ if (best == NULL || -+ cap->cc_koperations < best->cc_koperations) -+ best = cap; -+ } -+ } -+ if (best != NULL) -+ return best; -+ if (match == CRYPTOCAP_F_HARDWARE && (flags & CRYPTOCAP_F_SOFTWARE)) { -+ /* sort of an Algol 68-style for loop */ -+ match = CRYPTOCAP_F_SOFTWARE; -+ goto again; -+ } -+ return best; -+} -+ -+/* -+ * Dispatch an assymetric crypto request. -+ */ -+static int -+crypto_kinvoke(struct cryptkop *krp, int crid) -+{ -+ struct cryptocap *cap = NULL; -+ int error; -+ unsigned long d_flags; -+ -+ KASSERT(krp != NULL, ("%s: krp == NULL", __func__)); -+ KASSERT(krp->krp_callback != NULL, -+ ("%s: krp->crp_callback == NULL", __func__)); -+ -+ CRYPTO_DRIVER_LOCK(); -+ if ((crid & (CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE)) == 0) { -+ cap = crypto_checkdriver(crid); -+ if (cap != NULL) { -+ /* -+ * Driver present, it must support the necessary -+ * algorithm and, if s/w drivers are excluded, -+ * it must be registered as hardware-backed. -+ */ -+ if (!kdriver_suitable(cap, krp) || -+ (!crypto_devallowsoft && -+ (cap->cc_flags & CRYPTOCAP_F_HARDWARE) == 0)) -+ cap = NULL; -+ } -+ } else { -+ /* -+ * No requested driver; select based on crid flags. -+ */ -+ if (!crypto_devallowsoft) /* NB: disallow s/w drivers */ -+ crid &= ~CRYPTOCAP_F_SOFTWARE; -+ cap = crypto_select_kdriver(krp, crid); -+ } -+ if (cap != NULL && !cap->cc_kqblocked) { -+ krp->krp_hid = cap - crypto_drivers; -+ cap->cc_koperations++; -+ CRYPTO_DRIVER_UNLOCK(); -+ error = CRYPTODEV_KPROCESS(cap->cc_dev, krp, 0); -+ CRYPTO_DRIVER_LOCK(); -+ if (error == ERESTART) { -+ cap->cc_koperations--; -+ CRYPTO_DRIVER_UNLOCK(); -+ return (error); -+ } -+ /* return the actual device used */ -+ krp->krp_crid = krp->krp_hid; -+ } else { -+ /* -+ * NB: cap is !NULL if device is blocked; in -+ * that case return ERESTART so the operation -+ * is resubmitted if possible. -+ */ -+ error = (cap == NULL) ? ENODEV : ERESTART; -+ } -+ CRYPTO_DRIVER_UNLOCK(); -+ -+ if (error) { -+ krp->krp_status = error; -+ crypto_kdone(krp); -+ } -+ return 0; -+} -+ -+ -+/* -+ * Dispatch a crypto request to the appropriate crypto devices. -+ */ -+static int -+crypto_invoke(struct cryptocap *cap, struct cryptop *crp, int hint) -+{ -+ KASSERT(crp != NULL, ("%s: crp == NULL", __func__)); -+ KASSERT(crp->crp_callback != NULL, -+ ("%s: crp->crp_callback == NULL", __func__)); -+ KASSERT(crp->crp_desc != NULL, ("%s: crp->crp_desc == NULL", __func__)); -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+#ifdef CRYPTO_TIMING -+ if (crypto_timing) -+ crypto_tstat(&cryptostats.cs_invoke, &crp->crp_tstamp); -+#endif -+ if (cap->cc_flags & CRYPTOCAP_F_CLEANUP) { -+ struct cryptodesc *crd; -+ u_int64_t nid; -+ -+ /* -+ * Driver has unregistered; migrate the session and return -+ * an error to the caller so they'll resubmit the op. -+ * -+ * XXX: What if there are more already queued requests for this -+ * session? -+ */ -+ crypto_freesession(crp->crp_sid); -+ -+ for (crd = crp->crp_desc; crd->crd_next; crd = crd->crd_next) -+ crd->CRD_INI.cri_next = &(crd->crd_next->CRD_INI); -+ -+ /* XXX propagate flags from initial session? */ -+ if (crypto_newsession(&nid, &(crp->crp_desc->CRD_INI), -+ CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE) == 0) -+ crp->crp_sid = nid; -+ -+ crp->crp_etype = EAGAIN; -+ crypto_done(crp); -+ return 0; -+ } else { -+ /* -+ * Invoke the driver to process the request. -+ */ -+ return CRYPTODEV_PROCESS(cap->cc_dev, crp, hint); -+ } -+} -+ -+/* -+ * Release a set of crypto descriptors. -+ */ -+void -+crypto_freereq(struct cryptop *crp) -+{ -+ struct cryptodesc *crd; -+ -+ if (crp == NULL) -+ return; -+ -+#ifdef DIAGNOSTIC -+ { -+ struct cryptop *crp2; -+ unsigned long q_flags; -+ -+ CRYPTO_Q_LOCK(); -+ TAILQ_FOREACH(crp2, &crp_q, crp_next) { -+ KASSERT(crp2 != crp, -+ ("Freeing cryptop from the crypto queue (%p).", -+ crp)); -+ } -+ CRYPTO_Q_UNLOCK(); -+ CRYPTO_RETQ_LOCK(); -+ TAILQ_FOREACH(crp2, &crp_ret_q, crp_next) { -+ KASSERT(crp2 != crp, -+ ("Freeing cryptop from the return queue (%p).", -+ crp)); -+ } -+ CRYPTO_RETQ_UNLOCK(); -+ } -+#endif -+ -+ while ((crd = crp->crp_desc) != NULL) { -+ crp->crp_desc = crd->crd_next; -+ kmem_cache_free(cryptodesc_zone, crd); -+ } -+ kmem_cache_free(cryptop_zone, crp); -+} -+ -+/* -+ * Acquire a set of crypto descriptors. -+ */ -+struct cryptop * -+crypto_getreq(int num) -+{ -+ struct cryptodesc *crd; -+ struct cryptop *crp; -+ -+ crp = kmem_cache_alloc(cryptop_zone, SLAB_ATOMIC); -+ if (crp != NULL) { -+ memset(crp, 0, sizeof(*crp)); -+ INIT_LIST_HEAD(&crp->crp_next); -+ init_waitqueue_head(&crp->crp_waitq); -+ while (num--) { -+ crd = kmem_cache_alloc(cryptodesc_zone, SLAB_ATOMIC); -+ if (crd == NULL) { -+ crypto_freereq(crp); -+ return NULL; -+ } -+ memset(crd, 0, sizeof(*crd)); -+ crd->crd_next = crp->crp_desc; -+ crp->crp_desc = crd; -+ } -+ } -+ return crp; -+} -+ -+/* -+ * Invoke the callback on behalf of the driver. -+ */ -+void -+crypto_done(struct cryptop *crp) -+{ -+ unsigned long q_flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if ((crp->crp_flags & CRYPTO_F_DONE) == 0) { -+ crp->crp_flags |= CRYPTO_F_DONE; -+ CRYPTO_Q_LOCK(); -+ crypto_q_cnt--; -+ CRYPTO_Q_UNLOCK(); -+ } else -+ printk("crypto: crypto_done op already done, flags 0x%x", -+ crp->crp_flags); -+ if (crp->crp_etype != 0) -+ cryptostats.cs_errs++; -+ /* -+ * CBIMM means unconditionally do the callback immediately; -+ * CBIFSYNC means do the callback immediately only if the -+ * operation was done synchronously. Both are used to avoid -+ * doing extraneous context switches; the latter is mostly -+ * used with the software crypto driver. -+ */ -+ if ((crp->crp_flags & CRYPTO_F_CBIMM) || -+ ((crp->crp_flags & CRYPTO_F_CBIFSYNC) && -+ (CRYPTO_SESID2CAPS(crp->crp_sid) & CRYPTOCAP_F_SYNC))) { -+ /* -+ * Do the callback directly. This is ok when the -+ * callback routine does very little (e.g. the -+ * /dev/crypto callback method just does a wakeup). -+ */ -+ crp->crp_callback(crp); -+ } else { -+ unsigned long r_flags; -+ /* -+ * Normal case; queue the callback for the thread. -+ */ -+ CRYPTO_RETQ_LOCK(); -+ if (CRYPTO_RETQ_EMPTY()) -+ wake_up_interruptible(&cryptoretproc_wait);/* shared wait channel */ -+ TAILQ_INSERT_TAIL(&crp_ret_q, crp, crp_next); -+ CRYPTO_RETQ_UNLOCK(); -+ } -+} -+ -+/* -+ * Invoke the callback on behalf of the driver. -+ */ -+void -+crypto_kdone(struct cryptkop *krp) -+{ -+ struct cryptocap *cap; -+ unsigned long d_flags; -+ -+ if ((krp->krp_flags & CRYPTO_KF_DONE) != 0) -+ printk("crypto: crypto_kdone op already done, flags 0x%x", -+ krp->krp_flags); -+ krp->krp_flags |= CRYPTO_KF_DONE; -+ if (krp->krp_status != 0) -+ cryptostats.cs_kerrs++; -+ -+ CRYPTO_DRIVER_LOCK(); -+ /* XXX: What if driver is loaded in the meantime? */ -+ if (krp->krp_hid < crypto_drivers_num) { -+ cap = &crypto_drivers[krp->krp_hid]; -+ cap->cc_koperations--; -+ KASSERT(cap->cc_koperations >= 0, ("cc_koperations < 0")); -+ if (cap->cc_flags & CRYPTOCAP_F_CLEANUP) -+ crypto_remove(cap); -+ } -+ CRYPTO_DRIVER_UNLOCK(); -+ -+ /* -+ * CBIMM means unconditionally do the callback immediately; -+ * This is used to avoid doing extraneous context switches -+ */ -+ if ((krp->krp_flags & CRYPTO_KF_CBIMM)) { -+ /* -+ * Do the callback directly. This is ok when the -+ * callback routine does very little (e.g. the -+ * /dev/crypto callback method just does a wakeup). -+ */ -+ krp->krp_callback(krp); -+ } else { -+ unsigned long r_flags; -+ /* -+ * Normal case; queue the callback for the thread. -+ */ -+ CRYPTO_RETQ_LOCK(); -+ if (CRYPTO_RETQ_EMPTY()) -+ wake_up_interruptible(&cryptoretproc_wait);/* shared wait channel */ -+ TAILQ_INSERT_TAIL(&crp_ret_kq, krp, krp_next); -+ CRYPTO_RETQ_UNLOCK(); -+ } -+} -+ -+int -+crypto_getfeat(int *featp) -+{ -+ int hid, kalg, feat = 0; -+ unsigned long d_flags; -+ -+ CRYPTO_DRIVER_LOCK(); -+ for (hid = 0; hid < crypto_drivers_num; hid++) { -+ const struct cryptocap *cap = &crypto_drivers[hid]; -+ -+ if ((cap->cc_flags & CRYPTOCAP_F_SOFTWARE) && -+ !crypto_devallowsoft) { -+ continue; -+ } -+ for (kalg = 0; kalg < CRK_ALGORITHM_MAX; kalg++) -+ if (cap->cc_kalg[kalg] & CRYPTO_ALG_FLAG_SUPPORTED) -+ feat |= 1 << kalg; -+ } -+ CRYPTO_DRIVER_UNLOCK(); -+ *featp = feat; -+ return (0); -+} -+ -+/* -+ * Crypto thread, dispatches crypto requests. -+ */ -+static int -+crypto_proc(void *arg) -+{ -+ struct cryptop *crp, *submit; -+ struct cryptkop *krp, *krpp; -+ struct cryptocap *cap; -+ u_int32_t hid; -+ int result, hint; -+ unsigned long q_flags; -+ int loopcount = 0; -+ -+ ocf_daemonize("crypto"); -+ -+ CRYPTO_Q_LOCK(); -+ for (;;) { -+ /* -+ * we need to make sure we don't get into a busy loop with nothing -+ * to do, the two crypto_all_*blocked vars help us find out when -+ * we are all full and can do nothing on any driver or Q. If so we -+ * wait for an unblock. -+ */ -+ crypto_all_qblocked = !list_empty(&crp_q); -+ -+ /* -+ * Find the first element in the queue that can be -+ * processed and look-ahead to see if multiple ops -+ * are ready for the same driver. -+ */ -+ submit = NULL; -+ hint = 0; -+ list_for_each_entry(crp, &crp_q, crp_next) { -+ hid = CRYPTO_SESID2HID(crp->crp_sid); -+ cap = crypto_checkdriver(hid); -+ /* -+ * Driver cannot disappear when there is an active -+ * session. -+ */ -+ KASSERT(cap != NULL, ("%s:%u Driver disappeared.", -+ __func__, __LINE__)); -+ if (cap == NULL || cap->cc_dev == NULL) { -+ /* Op needs to be migrated, process it. */ -+ if (submit == NULL) -+ submit = crp; -+ break; -+ } -+ if (!cap->cc_qblocked) { -+ if (submit != NULL) { -+ /* -+ * We stop on finding another op, -+ * regardless whether its for the same -+ * driver or not. We could keep -+ * searching the queue but it might be -+ * better to just use a per-driver -+ * queue instead. -+ */ -+ if (CRYPTO_SESID2HID(submit->crp_sid) == hid) -+ hint = CRYPTO_HINT_MORE; -+ break; -+ } else { -+ submit = crp; -+ if ((submit->crp_flags & CRYPTO_F_BATCH) == 0) -+ break; -+ /* keep scanning for more are q'd */ -+ } -+ } -+ } -+ if (submit != NULL) { -+ hid = CRYPTO_SESID2HID(submit->crp_sid); -+ crypto_all_qblocked = 0; -+ list_del(&submit->crp_next); -+ crypto_drivers[hid].cc_unqblocked = 1; -+ cap = crypto_checkdriver(hid); -+ CRYPTO_Q_UNLOCK(); -+ KASSERT(cap != NULL, ("%s:%u Driver disappeared.", -+ __func__, __LINE__)); -+ result = crypto_invoke(cap, submit, hint); -+ CRYPTO_Q_LOCK(); -+ if (result == ERESTART) { -+ /* -+ * The driver ran out of resources, mark the -+ * driver ``blocked'' for cryptop's and put -+ * the request back in the queue. It would -+ * best to put the request back where we got -+ * it but that's hard so for now we put it -+ * at the front. This should be ok; putting -+ * it at the end does not work. -+ */ -+ /* XXX validate sid again? */ -+ list_add(&submit->crp_next, &crp_q); -+ cryptostats.cs_blocks++; -+ if (crypto_drivers[hid].cc_unqblocked) -+ crypto_drivers[hid].cc_qblocked=0; -+ crypto_drivers[hid].cc_unqblocked=0; -+ } -+ crypto_drivers[hid].cc_unqblocked = 0; -+ } -+ -+ crypto_all_kqblocked = !list_empty(&crp_kq); -+ -+ /* As above, but for key ops */ -+ krp = NULL; -+ list_for_each_entry(krpp, &crp_kq, krp_next) { -+ cap = crypto_checkdriver(krpp->krp_hid); -+ if (cap == NULL || cap->cc_dev == NULL) { -+ /* -+ * Operation needs to be migrated, invalidate -+ * the assigned device so it will reselect a -+ * new one below. Propagate the original -+ * crid selection flags if supplied. -+ */ -+ krp->krp_hid = krp->krp_crid & -+ (CRYPTOCAP_F_SOFTWARE|CRYPTOCAP_F_HARDWARE); -+ if (krp->krp_hid == 0) -+ krp->krp_hid = -+ CRYPTOCAP_F_SOFTWARE|CRYPTOCAP_F_HARDWARE; -+ break; -+ } -+ if (!cap->cc_kqblocked) { -+ krp = krpp; -+ break; -+ } -+ } -+ if (krp != NULL) { -+ crypto_all_kqblocked = 0; -+ list_del(&krp->krp_next); -+ crypto_drivers[krp->krp_hid].cc_kqblocked = 1; -+ CRYPTO_Q_UNLOCK(); -+ result = crypto_kinvoke(krp, krp->krp_hid); -+ CRYPTO_Q_LOCK(); -+ if (result == ERESTART) { -+ /* -+ * The driver ran out of resources, mark the -+ * driver ``blocked'' for cryptkop's and put -+ * the request back in the queue. It would -+ * best to put the request back where we got -+ * it but that's hard so for now we put it -+ * at the front. This should be ok; putting -+ * it at the end does not work. -+ */ -+ /* XXX validate sid again? */ -+ list_add(&krp->krp_next, &crp_kq); -+ cryptostats.cs_kblocks++; -+ } else -+ crypto_drivers[krp->krp_hid].cc_kqblocked = 0; -+ } -+ -+ if (submit == NULL && krp == NULL) { -+ /* -+ * Nothing more to be processed. Sleep until we're -+ * woken because there are more ops to process. -+ * This happens either by submission or by a driver -+ * becoming unblocked and notifying us through -+ * crypto_unblock. Note that when we wakeup we -+ * start processing each queue again from the -+ * front. It's not clear that it's important to -+ * preserve this ordering since ops may finish -+ * out of order if dispatched to different devices -+ * and some become blocked while others do not. -+ */ -+ dprintk("%s - sleeping (qe=%d qb=%d kqe=%d kqb=%d)\n", -+ __FUNCTION__, -+ list_empty(&crp_q), crypto_all_qblocked, -+ list_empty(&crp_kq), crypto_all_kqblocked); -+ loopcount = 0; -+ CRYPTO_Q_UNLOCK(); -+ crp_sleep = 1; -+ wait_event_interruptible(cryptoproc_wait, -+ !(list_empty(&crp_q) || crypto_all_qblocked) || -+ !(list_empty(&crp_kq) || crypto_all_kqblocked) || -+ cryptoproc == (pid_t) -1); -+ crp_sleep = 0; -+ if (signal_pending (current)) { -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ spin_lock_irq(¤t->sigmask_lock); -+#endif -+ flush_signals(current); -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ spin_unlock_irq(¤t->sigmask_lock); -+#endif -+ } -+ CRYPTO_Q_LOCK(); -+ dprintk("%s - awake\n", __FUNCTION__); -+ if (cryptoproc == (pid_t) -1) -+ break; -+ cryptostats.cs_intrs++; -+ } else if (loopcount > crypto_max_loopcount) { -+ /* -+ * Give other processes a chance to run if we've -+ * been using the CPU exclusively for a while. -+ */ -+ loopcount = 0; -+ schedule(); -+ } -+ loopcount++; -+ } -+ CRYPTO_Q_UNLOCK(); -+ complete_and_exit(&cryptoproc_exited, 0); -+} -+ -+/* -+ * Crypto returns thread, does callbacks for processed crypto requests. -+ * Callbacks are done here, rather than in the crypto drivers, because -+ * callbacks typically are expensive and would slow interrupt handling. -+ */ -+static int -+crypto_ret_proc(void *arg) -+{ -+ struct cryptop *crpt; -+ struct cryptkop *krpt; -+ unsigned long r_flags; -+ -+ ocf_daemonize("crypto_ret"); -+ -+ CRYPTO_RETQ_LOCK(); -+ for (;;) { -+ /* Harvest return q's for completed ops */ -+ crpt = NULL; -+ if (!list_empty(&crp_ret_q)) -+ crpt = list_entry(crp_ret_q.next, typeof(*crpt), crp_next); -+ if (crpt != NULL) -+ list_del(&crpt->crp_next); -+ -+ krpt = NULL; -+ if (!list_empty(&crp_ret_kq)) -+ krpt = list_entry(crp_ret_kq.next, typeof(*krpt), krp_next); -+ if (krpt != NULL) -+ list_del(&krpt->krp_next); -+ -+ if (crpt != NULL || krpt != NULL) { -+ CRYPTO_RETQ_UNLOCK(); -+ /* -+ * Run callbacks unlocked. -+ */ -+ if (crpt != NULL) -+ crpt->crp_callback(crpt); -+ if (krpt != NULL) -+ krpt->krp_callback(krpt); -+ CRYPTO_RETQ_LOCK(); -+ } else { -+ /* -+ * Nothing more to be processed. Sleep until we're -+ * woken because there are more returns to process. -+ */ -+ dprintk("%s - sleeping\n", __FUNCTION__); -+ CRYPTO_RETQ_UNLOCK(); -+ wait_event_interruptible(cryptoretproc_wait, -+ cryptoretproc == (pid_t) -1 || -+ !list_empty(&crp_ret_q) || -+ !list_empty(&crp_ret_kq)); -+ if (signal_pending (current)) { -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ spin_lock_irq(¤t->sigmask_lock); -+#endif -+ flush_signals(current); -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ spin_unlock_irq(¤t->sigmask_lock); -+#endif -+ } -+ CRYPTO_RETQ_LOCK(); -+ dprintk("%s - awake\n", __FUNCTION__); -+ if (cryptoretproc == (pid_t) -1) { -+ dprintk("%s - EXITING!\n", __FUNCTION__); -+ break; -+ } -+ cryptostats.cs_rets++; -+ } -+ } -+ CRYPTO_RETQ_UNLOCK(); -+ complete_and_exit(&cryptoretproc_exited, 0); -+} -+ -+ -+#if 0 /* should put this into /proc or something */ -+static void -+db_show_drivers(void) -+{ -+ int hid; -+ -+ db_printf("%12s %4s %4s %8s %2s %2s\n" -+ , "Device" -+ , "Ses" -+ , "Kops" -+ , "Flags" -+ , "QB" -+ , "KB" -+ ); -+ for (hid = 0; hid < crypto_drivers_num; hid++) { -+ const struct cryptocap *cap = &crypto_drivers[hid]; -+ if (cap->cc_dev == NULL) -+ continue; -+ db_printf("%-12s %4u %4u %08x %2u %2u\n" -+ , device_get_nameunit(cap->cc_dev) -+ , cap->cc_sessions -+ , cap->cc_koperations -+ , cap->cc_flags -+ , cap->cc_qblocked -+ , cap->cc_kqblocked -+ ); -+ } -+} -+ -+DB_SHOW_COMMAND(crypto, db_show_crypto) -+{ -+ struct cryptop *crp; -+ -+ db_show_drivers(); -+ db_printf("\n"); -+ -+ db_printf("%4s %8s %4s %4s %4s %4s %8s %8s\n", -+ "HID", "Caps", "Ilen", "Olen", "Etype", "Flags", -+ "Desc", "Callback"); -+ TAILQ_FOREACH(crp, &crp_q, crp_next) { -+ db_printf("%4u %08x %4u %4u %4u %04x %8p %8p\n" -+ , (int) CRYPTO_SESID2HID(crp->crp_sid) -+ , (int) CRYPTO_SESID2CAPS(crp->crp_sid) -+ , crp->crp_ilen, crp->crp_olen -+ , crp->crp_etype -+ , crp->crp_flags -+ , crp->crp_desc -+ , crp->crp_callback -+ ); -+ } -+ if (!TAILQ_EMPTY(&crp_ret_q)) { -+ db_printf("\n%4s %4s %4s %8s\n", -+ "HID", "Etype", "Flags", "Callback"); -+ TAILQ_FOREACH(crp, &crp_ret_q, crp_next) { -+ db_printf("%4u %4u %04x %8p\n" -+ , (int) CRYPTO_SESID2HID(crp->crp_sid) -+ , crp->crp_etype -+ , crp->crp_flags -+ , crp->crp_callback -+ ); -+ } -+ } -+} -+ -+DB_SHOW_COMMAND(kcrypto, db_show_kcrypto) -+{ -+ struct cryptkop *krp; -+ -+ db_show_drivers(); -+ db_printf("\n"); -+ -+ db_printf("%4s %5s %4s %4s %8s %4s %8s\n", -+ "Op", "Status", "#IP", "#OP", "CRID", "HID", "Callback"); -+ TAILQ_FOREACH(krp, &crp_kq, krp_next) { -+ db_printf("%4u %5u %4u %4u %08x %4u %8p\n" -+ , krp->krp_op -+ , krp->krp_status -+ , krp->krp_iparams, krp->krp_oparams -+ , krp->krp_crid, krp->krp_hid -+ , krp->krp_callback -+ ); -+ } -+ if (!TAILQ_EMPTY(&crp_ret_q)) { -+ db_printf("%4s %5s %8s %4s %8s\n", -+ "Op", "Status", "CRID", "HID", "Callback"); -+ TAILQ_FOREACH(krp, &crp_ret_kq, krp_next) { -+ db_printf("%4u %5u %08x %4u %8p\n" -+ , krp->krp_op -+ , krp->krp_status -+ , krp->krp_crid, krp->krp_hid -+ , krp->krp_callback -+ ); -+ } -+ } -+} -+#endif -+ -+ -+static int -+crypto_init(void) -+{ -+ int error; -+ -+ dprintk("%s(%p)\n", __FUNCTION__, (void *) crypto_init); -+ -+ if (crypto_initted) -+ return 0; -+ crypto_initted = 1; -+ -+ spin_lock_init(&crypto_drivers_lock); -+ spin_lock_init(&crypto_q_lock); -+ spin_lock_init(&crypto_ret_q_lock); -+ -+ cryptop_zone = kmem_cache_create("cryptop", sizeof(struct cryptop), -+ 0, SLAB_HWCACHE_ALIGN, NULL -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) -+ , NULL -+#endif -+ ); -+ -+ cryptodesc_zone = kmem_cache_create("cryptodesc", sizeof(struct cryptodesc), -+ 0, SLAB_HWCACHE_ALIGN, NULL -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) -+ , NULL -+#endif -+ ); -+ -+ if (cryptodesc_zone == NULL || cryptop_zone == NULL) { -+ printk("crypto: crypto_init cannot setup crypto zones\n"); -+ error = ENOMEM; -+ goto bad; -+ } -+ -+ crypto_drivers_num = CRYPTO_DRIVERS_INITIAL; -+ crypto_drivers = kmalloc(crypto_drivers_num * sizeof(struct cryptocap), -+ GFP_KERNEL); -+ if (crypto_drivers == NULL) { -+ printk("crypto: crypto_init cannot setup crypto drivers\n"); -+ error = ENOMEM; -+ goto bad; -+ } -+ -+ memset(crypto_drivers, 0, crypto_drivers_num * sizeof(struct cryptocap)); -+ -+ init_completion(&cryptoproc_exited); -+ init_completion(&cryptoretproc_exited); -+ -+ cryptoproc = 0; /* to avoid race condition where proc runs first */ -+ cryptoproc = kernel_thread(crypto_proc, NULL, CLONE_FS|CLONE_FILES); -+ if (cryptoproc < 0) { -+ error = cryptoproc; -+ printk("crypto: crypto_init cannot start crypto thread; error %d", -+ error); -+ goto bad; -+ } -+ -+ cryptoretproc = 0; /* to avoid race condition where proc runs first */ -+ cryptoretproc = kernel_thread(crypto_ret_proc, NULL, CLONE_FS|CLONE_FILES); -+ if (cryptoretproc < 0) { -+ error = cryptoretproc; -+ printk("crypto: crypto_init cannot start cryptoret thread; error %d", -+ error); -+ goto bad; -+ } -+ -+ return 0; -+bad: -+ crypto_exit(); -+ return error; -+} -+ -+ -+static void -+crypto_exit(void) -+{ -+ pid_t p; -+ unsigned long d_flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ /* -+ * Terminate any crypto threads. -+ */ -+ -+ CRYPTO_DRIVER_LOCK(); -+ p = cryptoproc; -+ cryptoproc = (pid_t) -1; -+ kill_proc(p, SIGTERM, 1); -+ wake_up_interruptible(&cryptoproc_wait); -+ CRYPTO_DRIVER_UNLOCK(); -+ -+ wait_for_completion(&cryptoproc_exited); -+ -+ CRYPTO_DRIVER_LOCK(); -+ p = cryptoretproc; -+ cryptoretproc = (pid_t) -1; -+ kill_proc(p, SIGTERM, 1); -+ wake_up_interruptible(&cryptoretproc_wait); -+ CRYPTO_DRIVER_UNLOCK(); -+ -+ wait_for_completion(&cryptoretproc_exited); -+ -+ /* XXX flush queues??? */ -+ -+ /* -+ * Reclaim dynamically allocated resources. -+ */ -+ if (crypto_drivers != NULL) -+ kfree(crypto_drivers); -+ -+ if (cryptodesc_zone != NULL) -+ kmem_cache_destroy(cryptodesc_zone); -+ if (cryptop_zone != NULL) -+ kmem_cache_destroy(cryptop_zone); -+} -+ -+ -+EXPORT_SYMBOL(crypto_newsession); -+EXPORT_SYMBOL(crypto_freesession); -+EXPORT_SYMBOL(crypto_get_driverid); -+EXPORT_SYMBOL(crypto_kregister); -+EXPORT_SYMBOL(crypto_register); -+EXPORT_SYMBOL(crypto_unregister); -+EXPORT_SYMBOL(crypto_unregister_all); -+EXPORT_SYMBOL(crypto_unblock); -+EXPORT_SYMBOL(crypto_dispatch); -+EXPORT_SYMBOL(crypto_kdispatch); -+EXPORT_SYMBOL(crypto_freereq); -+EXPORT_SYMBOL(crypto_getreq); -+EXPORT_SYMBOL(crypto_done); -+EXPORT_SYMBOL(crypto_kdone); -+EXPORT_SYMBOL(crypto_getfeat); -+EXPORT_SYMBOL(crypto_userasymcrypto); -+EXPORT_SYMBOL(crypto_getcaps); -+EXPORT_SYMBOL(crypto_find_driver); -+EXPORT_SYMBOL(crypto_find_device_byhid); -+ -+module_init(crypto_init); -+module_exit(crypto_exit); -+ -+MODULE_LICENSE("BSD"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("OCF (OpenBSD Cryptographic Framework)"); -diff -Nur linux-2.6.36.orig/crypto/ocf/cryptocteon/cavium_crypto.c linux-2.6.36/crypto/ocf/cryptocteon/cavium_crypto.c ---- linux-2.6.36.orig/crypto/ocf/cryptocteon/cavium_crypto.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/cryptocteon/cavium_crypto.c 2010-11-09 20:28:04.311245450 +0100 -@@ -0,0 +1,2283 @@ -+/* -+ * Copyright (c) 2009 David McCullough -+ * -+ * Copyright (c) 2003-2007 Cavium Networks (support@cavium.com). All rights -+ * reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * 1. Redistributions of source code must retain the above copyright notice, -+ * this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright notice, -+ * this list of conditions and the following disclaimer in the documentation -+ * and/or other materials provided with the distribution. -+ * 3. All advertising materials mentioning features or use of this software -+ * must display the following acknowledgement: -+ * This product includes software developed by Cavium Networks -+ * 4. Cavium Networks' name may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * This Software, including technical data, may be subject to U.S. export -+ * control laws, including the U.S. Export Administration Act and its -+ * associated regulations, and may be subject to export or import regulations -+ * in other countries. You warrant that You will comply strictly in all -+ * respects with all such regulations and acknowledge that you have the -+ * responsibility to obtain licenses to export, re-export or import the -+ * Software. -+ * -+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" AND -+ * WITH ALL FAULTS AND CAVIUM MAKES NO PROMISES, REPRESENTATIONS OR WARRANTIES, -+ * EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO THE -+ * SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR -+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM -+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, -+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF -+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR -+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR -+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. -+*/ -+/****************************************************************************/ -+ -+#include -+#include -+#include "octeon-asm.h" -+ -+/****************************************************************************/ -+ -+extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *); -+extern void octeon_crypto_disable(struct octeon_cop2_state *, unsigned long); -+ -+#define SG_INIT(s, p, i, l) \ -+ { \ -+ (i) = 0; \ -+ (l) = (s)[0].length; \ -+ (p) = (typeof(p)) sg_virt((s)); \ -+ CVMX_PREFETCH0((p)); \ -+ } -+ -+#define SG_CONSUME(s, p, i, l) \ -+ { \ -+ (p)++; \ -+ (l) -= sizeof(*(p)); \ -+ if ((l) < 0) { \ -+ dprintk("%s, %d: l = %d\n", __FILE__, __LINE__, l); \ -+ } else if ((l) == 0) { \ -+ (i)++; \ -+ (l) = (s)[0].length; \ -+ (p) = (typeof(p)) sg_virt(s); \ -+ CVMX_PREFETCH0((p)); \ -+ } \ -+ } -+ -+#define ESP_HEADER_LENGTH 8 -+#define DES_CBC_IV_LENGTH 8 -+#define AES_CBC_IV_LENGTH 16 -+#define ESP_HMAC_LEN 12 -+ -+#define ESP_HEADER_LENGTH 8 -+#define DES_CBC_IV_LENGTH 8 -+ -+/****************************************************************************/ -+ -+#define CVM_LOAD_SHA_UNIT(dat, next) { \ -+ if (next == 0) { \ -+ next = 1; \ -+ CVMX_MT_HSH_DAT (dat, 0); \ -+ } else if (next == 1) { \ -+ next = 2; \ -+ CVMX_MT_HSH_DAT (dat, 1); \ -+ } else if (next == 2) { \ -+ next = 3; \ -+ CVMX_MT_HSH_DAT (dat, 2); \ -+ } else if (next == 3) { \ -+ next = 4; \ -+ CVMX_MT_HSH_DAT (dat, 3); \ -+ } else if (next == 4) { \ -+ next = 5; \ -+ CVMX_MT_HSH_DAT (dat, 4); \ -+ } else if (next == 5) { \ -+ next = 6; \ -+ CVMX_MT_HSH_DAT (dat, 5); \ -+ } else if (next == 6) { \ -+ next = 7; \ -+ CVMX_MT_HSH_DAT (dat, 6); \ -+ } else { \ -+ CVMX_MT_HSH_STARTSHA (dat); \ -+ next = 0; \ -+ } \ -+} -+ -+#define CVM_LOAD2_SHA_UNIT(dat1, dat2, next) { \ -+ if (next == 0) { \ -+ CVMX_MT_HSH_DAT (dat1, 0); \ -+ CVMX_MT_HSH_DAT (dat2, 1); \ -+ next = 2; \ -+ } else if (next == 1) { \ -+ CVMX_MT_HSH_DAT (dat1, 1); \ -+ CVMX_MT_HSH_DAT (dat2, 2); \ -+ next = 3; \ -+ } else if (next == 2) { \ -+ CVMX_MT_HSH_DAT (dat1, 2); \ -+ CVMX_MT_HSH_DAT (dat2, 3); \ -+ next = 4; \ -+ } else if (next == 3) { \ -+ CVMX_MT_HSH_DAT (dat1, 3); \ -+ CVMX_MT_HSH_DAT (dat2, 4); \ -+ next = 5; \ -+ } else if (next == 4) { \ -+ CVMX_MT_HSH_DAT (dat1, 4); \ -+ CVMX_MT_HSH_DAT (dat2, 5); \ -+ next = 6; \ -+ } else if (next == 5) { \ -+ CVMX_MT_HSH_DAT (dat1, 5); \ -+ CVMX_MT_HSH_DAT (dat2, 6); \ -+ next = 7; \ -+ } else if (next == 6) { \ -+ CVMX_MT_HSH_DAT (dat1, 6); \ -+ CVMX_MT_HSH_STARTSHA (dat2); \ -+ next = 0; \ -+ } else { \ -+ CVMX_MT_HSH_STARTSHA (dat1); \ -+ CVMX_MT_HSH_DAT (dat2, 0); \ -+ next = 1; \ -+ } \ -+} -+ -+/****************************************************************************/ -+ -+#define CVM_LOAD_MD5_UNIT(dat, next) { \ -+ if (next == 0) { \ -+ next = 1; \ -+ CVMX_MT_HSH_DAT (dat, 0); \ -+ } else if (next == 1) { \ -+ next = 2; \ -+ CVMX_MT_HSH_DAT (dat, 1); \ -+ } else if (next == 2) { \ -+ next = 3; \ -+ CVMX_MT_HSH_DAT (dat, 2); \ -+ } else if (next == 3) { \ -+ next = 4; \ -+ CVMX_MT_HSH_DAT (dat, 3); \ -+ } else if (next == 4) { \ -+ next = 5; \ -+ CVMX_MT_HSH_DAT (dat, 4); \ -+ } else if (next == 5) { \ -+ next = 6; \ -+ CVMX_MT_HSH_DAT (dat, 5); \ -+ } else if (next == 6) { \ -+ next = 7; \ -+ CVMX_MT_HSH_DAT (dat, 6); \ -+ } else { \ -+ CVMX_MT_HSH_STARTMD5 (dat); \ -+ next = 0; \ -+ } \ -+} -+ -+#define CVM_LOAD2_MD5_UNIT(dat1, dat2, next) { \ -+ if (next == 0) { \ -+ CVMX_MT_HSH_DAT (dat1, 0); \ -+ CVMX_MT_HSH_DAT (dat2, 1); \ -+ next = 2; \ -+ } else if (next == 1) { \ -+ CVMX_MT_HSH_DAT (dat1, 1); \ -+ CVMX_MT_HSH_DAT (dat2, 2); \ -+ next = 3; \ -+ } else if (next == 2) { \ -+ CVMX_MT_HSH_DAT (dat1, 2); \ -+ CVMX_MT_HSH_DAT (dat2, 3); \ -+ next = 4; \ -+ } else if (next == 3) { \ -+ CVMX_MT_HSH_DAT (dat1, 3); \ -+ CVMX_MT_HSH_DAT (dat2, 4); \ -+ next = 5; \ -+ } else if (next == 4) { \ -+ CVMX_MT_HSH_DAT (dat1, 4); \ -+ CVMX_MT_HSH_DAT (dat2, 5); \ -+ next = 6; \ -+ } else if (next == 5) { \ -+ CVMX_MT_HSH_DAT (dat1, 5); \ -+ CVMX_MT_HSH_DAT (dat2, 6); \ -+ next = 7; \ -+ } else if (next == 6) { \ -+ CVMX_MT_HSH_DAT (dat1, 6); \ -+ CVMX_MT_HSH_STARTMD5 (dat2); \ -+ next = 0; \ -+ } else { \ -+ CVMX_MT_HSH_STARTMD5 (dat1); \ -+ CVMX_MT_HSH_DAT (dat2, 0); \ -+ next = 1; \ -+ } \ -+} -+ -+/****************************************************************************/ -+ -+static inline uint64_t -+swap64(uint64_t a) -+{ -+ return ((a >> 56) | -+ (((a >> 48) & 0xfful) << 8) | -+ (((a >> 40) & 0xfful) << 16) | -+ (((a >> 32) & 0xfful) << 24) | -+ (((a >> 24) & 0xfful) << 32) | -+ (((a >> 16) & 0xfful) << 40) | -+ (((a >> 8) & 0xfful) << 48) | (((a >> 0) & 0xfful) << 56)); -+} -+ -+/****************************************************************************/ -+ -+void -+octo_calc_hash(__u8 auth, unsigned char *key, uint64_t *inner, uint64_t *outer) -+{ -+ uint8_t hash_key[64]; -+ uint64_t *key1; -+ register uint64_t xor1 = 0x3636363636363636ULL; -+ register uint64_t xor2 = 0x5c5c5c5c5c5c5c5cULL; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ memset(hash_key, 0, sizeof(hash_key)); -+ memcpy(hash_key, (uint8_t *) key, (auth ? 20 : 16)); -+ key1 = (uint64_t *) hash_key; -+ flags = octeon_crypto_enable(&state); -+ if (auth) { -+ CVMX_MT_HSH_IV(0x67452301EFCDAB89ULL, 0); -+ CVMX_MT_HSH_IV(0x98BADCFE10325476ULL, 1); -+ CVMX_MT_HSH_IV(0xC3D2E1F000000000ULL, 2); -+ } else { -+ CVMX_MT_HSH_IV(0x0123456789ABCDEFULL, 0); -+ CVMX_MT_HSH_IV(0xFEDCBA9876543210ULL, 1); -+ } -+ -+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 0); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 1); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 2); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 3); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 4); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 5); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 6); -+ key1++; -+ if (auth) -+ CVMX_MT_HSH_STARTSHA((*key1 ^ xor1)); -+ else -+ CVMX_MT_HSH_STARTMD5((*key1 ^ xor1)); -+ -+ CVMX_MF_HSH_IV(inner[0], 0); -+ CVMX_MF_HSH_IV(inner[1], 1); -+ if (auth) { -+ inner[2] = 0; -+ CVMX_MF_HSH_IV(((uint64_t *) inner)[2], 2); -+ } -+ -+ memset(hash_key, 0, sizeof(hash_key)); -+ memcpy(hash_key, (uint8_t *) key, (auth ? 20 : 16)); -+ key1 = (uint64_t *) hash_key; -+ if (auth) { -+ CVMX_MT_HSH_IV(0x67452301EFCDAB89ULL, 0); -+ CVMX_MT_HSH_IV(0x98BADCFE10325476ULL, 1); -+ CVMX_MT_HSH_IV(0xC3D2E1F000000000ULL, 2); -+ } else { -+ CVMX_MT_HSH_IV(0x0123456789ABCDEFULL, 0); -+ CVMX_MT_HSH_IV(0xFEDCBA9876543210ULL, 1); -+ } -+ -+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 0); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 1); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 2); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 3); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 4); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 5); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 6); -+ key1++; -+ if (auth) -+ CVMX_MT_HSH_STARTSHA((*key1 ^ xor2)); -+ else -+ CVMX_MT_HSH_STARTMD5((*key1 ^ xor2)); -+ -+ CVMX_MF_HSH_IV(outer[0], 0); -+ CVMX_MF_HSH_IV(outer[1], 1); -+ if (auth) { -+ outer[2] = 0; -+ CVMX_MF_HSH_IV(outer[2], 2); -+ } -+ octeon_crypto_disable(&state, flags); -+ return; -+} -+ -+/****************************************************************************/ -+/* DES functions */ -+ -+int -+octo_des_cbc_encrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ uint64_t *data; -+ int data_i, data_l; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x7) || (crypt_off + crypt_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load 3DES Key */ -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ if (od->octo_encklen == 24) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ } else if (od->octo_encklen == 8) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ -+ CVMX_MT_3DES_IV(* (uint64_t *) ivp); -+ -+ while (crypt_off > 0) { -+ SG_CONSUME(sg, data, data_i, data_l); -+ crypt_off -= 8; -+ } -+ -+ while (crypt_len > 0) { -+ CVMX_MT_3DES_ENC_CBC(*data); -+ CVMX_MF_3DES_RESULT(*data); -+ SG_CONSUME(sg, data, data_i, data_l); -+ crypt_len -= 8; -+ } -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+ -+int -+octo_des_cbc_decrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ uint64_t *data; -+ int data_i, data_l; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x7) || (crypt_off + crypt_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load 3DES Key */ -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ if (od->octo_encklen == 24) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ } else if (od->octo_encklen == 8) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ -+ CVMX_MT_3DES_IV(* (uint64_t *) ivp); -+ -+ while (crypt_off > 0) { -+ SG_CONSUME(sg, data, data_i, data_l); -+ crypt_off -= 8; -+ } -+ -+ while (crypt_len > 0) { -+ CVMX_MT_3DES_DEC_CBC(*data); -+ CVMX_MF_3DES_RESULT(*data); -+ SG_CONSUME(sg, data, data_i, data_l); -+ crypt_len -= 8; -+ } -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+/****************************************************************************/ -+/* AES functions */ -+ -+int -+octo_aes_cbc_encrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ uint64_t *data, *pdata; -+ int data_i, data_l; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x7) || (crypt_off + crypt_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load AES Key */ -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ -+ if (od->octo_encklen == 16) { -+ CVMX_MT_AES_KEY(0x0, 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 24) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 32) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); -+ -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); -+ -+ while (crypt_off > 0) { -+ SG_CONSUME(sg, data, data_i, data_l); -+ crypt_off -= 8; -+ } -+ -+ while (crypt_len > 0) { -+ pdata = data; -+ CVMX_MT_AES_ENC_CBC0(*data); -+ SG_CONSUME(sg, data, data_i, data_l); -+ CVMX_MT_AES_ENC_CBC1(*data); -+ CVMX_MF_AES_RESULT(*pdata, 0); -+ CVMX_MF_AES_RESULT(*data, 1); -+ SG_CONSUME(sg, data, data_i, data_l); -+ crypt_len -= 16; -+ } -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+ -+int -+octo_aes_cbc_decrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ uint64_t *data, *pdata; -+ int data_i, data_l; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x7) || (crypt_off + crypt_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load AES Key */ -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ -+ if (od->octo_encklen == 16) { -+ CVMX_MT_AES_KEY(0x0, 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 24) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 32) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); -+ -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); -+ -+ while (crypt_off > 0) { -+ SG_CONSUME(sg, data, data_i, data_l); -+ crypt_off -= 8; -+ } -+ -+ while (crypt_len > 0) { -+ pdata = data; -+ CVMX_MT_AES_DEC_CBC0(*data); -+ SG_CONSUME(sg, data, data_i, data_l); -+ CVMX_MT_AES_DEC_CBC1(*data); -+ CVMX_MF_AES_RESULT(*pdata, 0); -+ CVMX_MF_AES_RESULT(*data, 1); -+ SG_CONSUME(sg, data, data_i, data_l); -+ crypt_len -= 16; -+ } -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+/****************************************************************************/ -+/* MD5 */ -+ -+int -+octo_null_md5_encrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ uint64_t *data; -+ uint64_t tmp1, tmp2; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || -+ (auth_off & 0x7) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data, data_i, data_l); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* Load MD5 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ -+ while (auth_off > 0) { -+ SG_CONSUME(sg, data, data_i, data_l); -+ auth_off -= 8; -+ } -+ -+ while (auth_len > 0) { -+ CVM_LOAD_MD5_UNIT(*data, next); -+ auth_len -= 8; -+ SG_CONSUME(sg, data, data_i, data_l); -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_MD5_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVMX_ES64(tmp1, ((alen + 64) << 3)); -+ CVM_LOAD_MD5_UNIT(tmp1, next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_ES64(tmp1, ((64 + 16) << 3)); -+ CVMX_MT_HSH_STARTMD5(tmp1); -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data, data_i, data_l); -+ icv_off -= 8; -+ } -+ CVMX_MF_HSH_IV(*data, 0); -+ SG_CONSUME(sg, data, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *(uint32_t *)data = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+/****************************************************************************/ -+/* SHA1 */ -+ -+int -+octo_null_sha1_encrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ uint64_t *data; -+ uint64_t tmp1, tmp2, tmp3; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || -+ (auth_off & 0x7) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data, data_i, data_l); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* Load SHA1 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); -+ -+ while (auth_off > 0) { -+ SG_CONSUME(sg, data, data_i, data_l); -+ auth_off -= 8; -+ } -+ -+ while (auth_len > 0) { -+ CVM_LOAD_SHA_UNIT(*data, next); -+ auth_len -= 8; -+ SG_CONSUME(sg, data, data_i, data_l); -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_MD5_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ tmp3 = 0; -+ CVMX_MF_HSH_IV(tmp3, 2); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ tmp3 |= 0x0000000080000000; -+ CVMX_MT_HSH_DAT(tmp3, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data, data_i, data_l); -+ icv_off -= 8; -+ } -+ CVMX_MF_HSH_IV(*data, 0); -+ SG_CONSUME(sg, data, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *(uint32_t *)data = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+/****************************************************************************/ -+/* DES MD5 */ -+ -+int -+octo_des_cbc_md5_encrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ union { -+ uint32_t data32[2]; -+ uint64_t data64[1]; -+ } mydata; -+ uint64_t *data = &mydata.data64[0]; -+ uint32_t *data32; -+ uint64_t tmp1, tmp2; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || -+ (crypt_len & 0x7) || -+ (auth_len & 0x7) || -+ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data32, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load 3DES Key */ -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ if (od->octo_encklen == 24) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ } else if (od->octo_encklen == 8) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ -+ CVMX_MT_3DES_IV(* (uint64_t *) ivp); -+ -+ /* Load MD5 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ -+ while (crypt_off > 0 && auth_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ crypt_off -= 4; -+ auth_off -= 4; -+ } -+ -+ while (crypt_len > 0 || auth_len > 0) { -+ uint32_t *first = data32; -+ mydata.data32[0] = *first; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata.data32[1] = *data32; -+ if (crypt_off <= 0) { -+ if (crypt_len > 0) { -+ CVMX_MT_3DES_ENC_CBC(*data); -+ CVMX_MF_3DES_RESULT(*data); -+ crypt_len -= 8; -+ } -+ } else -+ crypt_off -= 8; -+ if (auth_off <= 0) { -+ if (auth_len > 0) { -+ CVM_LOAD_MD5_UNIT(*data, next); -+ auth_len -= 8; -+ } -+ } else -+ auth_off -= 8; -+ *first = mydata.data32[0]; -+ *data32 = mydata.data32[1]; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_MD5_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVMX_ES64(tmp1, ((alen + 64) << 3)); -+ CVM_LOAD_MD5_UNIT(tmp1, next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_ES64(tmp1, ((64 + 16) << 3)); -+ CVMX_MT_HSH_STARTMD5(tmp1); -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data32, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ icv_off -= 4; -+ } -+ CVMX_MF_HSH_IV(tmp1, 0); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ SG_CONSUME(sg, data32, data_i, data_l); -+ *data32 = (uint32_t) tmp1; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+int -+octo_des_cbc_md5_decrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ union { -+ uint32_t data32[2]; -+ uint64_t data64[1]; -+ } mydata; -+ uint64_t *data = &mydata.data64[0]; -+ uint32_t *data32; -+ uint64_t tmp1, tmp2; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || -+ (crypt_len & 0x7) || -+ (auth_len & 0x7) || -+ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data32, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load 3DES Key */ -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ if (od->octo_encklen == 24) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ } else if (od->octo_encklen == 8) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ -+ CVMX_MT_3DES_IV(* (uint64_t *) ivp); -+ -+ /* Load MD5 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ -+ while (crypt_off > 0 && auth_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ crypt_off -= 4; -+ auth_off -= 4; -+ } -+ -+ while (crypt_len > 0 || auth_len > 0) { -+ uint32_t *first = data32; -+ mydata.data32[0] = *first; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata.data32[1] = *data32; -+ if (auth_off <= 0) { -+ if (auth_len > 0) { -+ CVM_LOAD_MD5_UNIT(*data, next); -+ auth_len -= 8; -+ } -+ } else -+ auth_off -= 8; -+ if (crypt_off <= 0) { -+ if (crypt_len > 0) { -+ CVMX_MT_3DES_DEC_CBC(*data); -+ CVMX_MF_3DES_RESULT(*data); -+ crypt_len -= 8; -+ } -+ } else -+ crypt_off -= 8; -+ *first = mydata.data32[0]; -+ *data32 = mydata.data32[1]; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_MD5_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVMX_ES64(tmp1, ((alen + 64) << 3)); -+ CVM_LOAD_MD5_UNIT(tmp1, next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_ES64(tmp1, ((64 + 16) << 3)); -+ CVMX_MT_HSH_STARTMD5(tmp1); -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data32, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ icv_off -= 4; -+ } -+ CVMX_MF_HSH_IV(tmp1, 0); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ SG_CONSUME(sg, data32, data_i, data_l); -+ *data32 = (uint32_t) tmp1; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+/****************************************************************************/ -+/* DES SHA */ -+ -+int -+octo_des_cbc_sha1_encrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ union { -+ uint32_t data32[2]; -+ uint64_t data64[1]; -+ } mydata; -+ uint64_t *data = &mydata.data64[0]; -+ uint32_t *data32; -+ uint64_t tmp1, tmp2, tmp3; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || -+ (crypt_len & 0x7) || -+ (auth_len & 0x7) || -+ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data32, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load 3DES Key */ -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ if (od->octo_encklen == 24) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ } else if (od->octo_encklen == 8) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ -+ CVMX_MT_3DES_IV(* (uint64_t *) ivp); -+ -+ /* Load SHA1 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); -+ -+ while (crypt_off > 0 && auth_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ crypt_off -= 4; -+ auth_off -= 4; -+ } -+ -+ while (crypt_len > 0 || auth_len > 0) { -+ uint32_t *first = data32; -+ mydata.data32[0] = *first; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata.data32[1] = *data32; -+ if (crypt_off <= 0) { -+ if (crypt_len > 0) { -+ CVMX_MT_3DES_ENC_CBC(*data); -+ CVMX_MF_3DES_RESULT(*data); -+ crypt_len -= 8; -+ } -+ } else -+ crypt_off -= 8; -+ if (auth_off <= 0) { -+ if (auth_len > 0) { -+ CVM_LOAD_SHA_UNIT(*data, next); -+ auth_len -= 8; -+ } -+ } else -+ auth_off -= 8; -+ *first = mydata.data32[0]; -+ *data32 = mydata.data32[1]; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_SHA_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ tmp3 = 0; -+ CVMX_MF_HSH_IV(tmp3, 2); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ tmp3 |= 0x0000000080000000; -+ CVMX_MT_HSH_DAT(tmp3, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data32, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ icv_off -= 4; -+ } -+ CVMX_MF_HSH_IV(tmp1, 0); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ SG_CONSUME(sg, data32, data_i, data_l); -+ *data32 = (uint32_t) tmp1; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+int -+octo_des_cbc_sha1_decrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ union { -+ uint32_t data32[2]; -+ uint64_t data64[1]; -+ } mydata; -+ uint64_t *data = &mydata.data64[0]; -+ uint32_t *data32; -+ uint64_t tmp1, tmp2, tmp3; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || -+ (crypt_len & 0x7) || -+ (auth_len & 0x7) || -+ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data32, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load 3DES Key */ -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ if (od->octo_encklen == 24) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ } else if (od->octo_encklen == 8) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ -+ CVMX_MT_3DES_IV(* (uint64_t *) ivp); -+ -+ /* Load SHA1 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); -+ -+ while (crypt_off > 0 && auth_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ crypt_off -= 4; -+ auth_off -= 4; -+ } -+ -+ while (crypt_len > 0 || auth_len > 0) { -+ uint32_t *first = data32; -+ mydata.data32[0] = *first; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata.data32[1] = *data32; -+ if (auth_off <= 0) { -+ if (auth_len > 0) { -+ CVM_LOAD_SHA_UNIT(*data, next); -+ auth_len -= 8; -+ } -+ } else -+ auth_off -= 8; -+ if (crypt_off <= 0) { -+ if (crypt_len > 0) { -+ CVMX_MT_3DES_DEC_CBC(*data); -+ CVMX_MF_3DES_RESULT(*data); -+ crypt_len -= 8; -+ } -+ } else -+ crypt_off -= 8; -+ *first = mydata.data32[0]; -+ *data32 = mydata.data32[1]; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_SHA_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ tmp3 = 0; -+ CVMX_MF_HSH_IV(tmp3, 2); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ tmp3 |= 0x0000000080000000; -+ CVMX_MT_HSH_DAT(tmp3, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); -+ /* save the HMAC */ -+ SG_INIT(sg, data32, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ icv_off -= 4; -+ } -+ CVMX_MF_HSH_IV(tmp1, 0); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ SG_CONSUME(sg, data32, data_i, data_l); -+ *data32 = (uint32_t) tmp1; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+/****************************************************************************/ -+/* AES MD5 */ -+ -+int -+octo_aes_cbc_md5_encrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ union { -+ uint32_t data32[2]; -+ uint64_t data64[1]; -+ } mydata[2]; -+ uint64_t *pdata = &mydata[0].data64[0]; -+ uint64_t *data = &mydata[1].data64[0]; -+ uint32_t *data32; -+ uint64_t tmp1, tmp2; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || -+ (crypt_len & 0x7) || -+ (auth_len & 0x7) || -+ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data32, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load AES Key */ -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ -+ if (od->octo_encklen == 16) { -+ CVMX_MT_AES_KEY(0x0, 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 24) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 32) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); -+ -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); -+ -+ /* Load MD5 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ -+ while (crypt_off > 0 && auth_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ crypt_off -= 4; -+ auth_off -= 4; -+ } -+ -+ /* align auth and crypt */ -+ while (crypt_off > 0 && auth_len > 0) { -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVM_LOAD_MD5_UNIT(*pdata, next); -+ crypt_off -= 8; -+ auth_len -= 8; -+ } -+ -+ while (crypt_len > 0) { -+ uint32_t *pdata32[3]; -+ -+ pdata32[0] = data32; -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ -+ pdata32[1] = data32; -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ -+ pdata32[2] = data32; -+ mydata[1].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ -+ mydata[1].data32[1] = *data32; -+ -+ CVMX_MT_AES_ENC_CBC0(*pdata); -+ CVMX_MT_AES_ENC_CBC1(*data); -+ CVMX_MF_AES_RESULT(*pdata, 0); -+ CVMX_MF_AES_RESULT(*data, 1); -+ crypt_len -= 16; -+ -+ if (auth_len > 0) { -+ CVM_LOAD_MD5_UNIT(*pdata, next); -+ auth_len -= 8; -+ } -+ if (auth_len > 0) { -+ CVM_LOAD_MD5_UNIT(*data, next); -+ auth_len -= 8; -+ } -+ -+ *pdata32[0] = mydata[0].data32[0]; -+ *pdata32[1] = mydata[0].data32[1]; -+ *pdata32[2] = mydata[1].data32[0]; -+ *data32 = mydata[1].data32[1]; -+ -+ SG_CONSUME(sg, data32, data_i, data_l); -+ } -+ -+ /* finish any left over hashing */ -+ while (auth_len > 0) { -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVM_LOAD_MD5_UNIT(*pdata, next); -+ auth_len -= 8; -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_MD5_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVMX_ES64(tmp1, ((alen + 64) << 3)); -+ CVM_LOAD_MD5_UNIT(tmp1, next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_ES64(tmp1, ((64 + 16) << 3)); -+ CVMX_MT_HSH_STARTMD5(tmp1); -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data32, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ icv_off -= 4; -+ } -+ CVMX_MF_HSH_IV(tmp1, 0); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ SG_CONSUME(sg, data32, data_i, data_l); -+ *data32 = (uint32_t) tmp1; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+int -+octo_aes_cbc_md5_decrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ union { -+ uint32_t data32[2]; -+ uint64_t data64[1]; -+ } mydata[2]; -+ uint64_t *pdata = &mydata[0].data64[0]; -+ uint64_t *data = &mydata[1].data64[0]; -+ uint32_t *data32; -+ uint64_t tmp1, tmp2; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || -+ (crypt_len & 0x7) || -+ (auth_len & 0x7) || -+ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data32, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load AES Key */ -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ -+ if (od->octo_encklen == 16) { -+ CVMX_MT_AES_KEY(0x0, 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 24) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 32) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); -+ -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); -+ -+ /* Load MD5 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ -+ while (crypt_off > 0 && auth_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ crypt_off -= 4; -+ auth_off -= 4; -+ } -+ -+ /* align auth and crypt */ -+ while (crypt_off > 0 && auth_len > 0) { -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVM_LOAD_MD5_UNIT(*pdata, next); -+ crypt_off -= 8; -+ auth_len -= 8; -+ } -+ -+ while (crypt_len > 0) { -+ uint32_t *pdata32[3]; -+ -+ pdata32[0] = data32; -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ pdata32[1] = data32; -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ pdata32[2] = data32; -+ mydata[1].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[1].data32[1] = *data32; -+ -+ if (auth_len > 0) { -+ CVM_LOAD_MD5_UNIT(*pdata, next); -+ auth_len -= 8; -+ } -+ -+ if (auth_len > 0) { -+ CVM_LOAD_MD5_UNIT(*data, next); -+ auth_len -= 8; -+ } -+ -+ CVMX_MT_AES_DEC_CBC0(*pdata); -+ CVMX_MT_AES_DEC_CBC1(*data); -+ CVMX_MF_AES_RESULT(*pdata, 0); -+ CVMX_MF_AES_RESULT(*data, 1); -+ crypt_len -= 16; -+ -+ *pdata32[0] = mydata[0].data32[0]; -+ *pdata32[1] = mydata[0].data32[1]; -+ *pdata32[2] = mydata[1].data32[0]; -+ *data32 = mydata[1].data32[1]; -+ -+ SG_CONSUME(sg, data32, data_i, data_l); -+ } -+ -+ /* finish left over hash if any */ -+ while (auth_len > 0) { -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVM_LOAD_MD5_UNIT(*pdata, next); -+ auth_len -= 8; -+ } -+ -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_MD5_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVMX_ES64(tmp1, ((alen + 64) << 3)); -+ CVM_LOAD_MD5_UNIT(tmp1, next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_ES64(tmp1, ((64 + 16) << 3)); -+ CVMX_MT_HSH_STARTMD5(tmp1); -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data32, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ icv_off -= 4; -+ } -+ CVMX_MF_HSH_IV(tmp1, 0); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ SG_CONSUME(sg, data32, data_i, data_l); -+ *data32 = (uint32_t) tmp1; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+/****************************************************************************/ -+/* AES SHA1 */ -+ -+int -+octo_aes_cbc_sha1_encrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ union { -+ uint32_t data32[2]; -+ uint64_t data64[1]; -+ } mydata[2]; -+ uint64_t *pdata = &mydata[0].data64[0]; -+ uint64_t *data = &mydata[1].data64[0]; -+ uint32_t *data32; -+ uint64_t tmp1, tmp2, tmp3; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s(a_off=%d a_len=%d c_off=%d c_len=%d icv_off=%d)\n", -+ __FUNCTION__, auth_off, auth_len, crypt_off, crypt_len, icv_off); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || -+ (crypt_len & 0x7) || -+ (auth_len & 0x7) || -+ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data32, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load AES Key */ -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ -+ if (od->octo_encklen == 16) { -+ CVMX_MT_AES_KEY(0x0, 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 24) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 32) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); -+ -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); -+ -+ /* Load SHA IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); -+ -+ while (crypt_off > 0 && auth_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ crypt_off -= 4; -+ auth_off -= 4; -+ } -+ -+ /* align auth and crypt */ -+ while (crypt_off > 0 && auth_len > 0) { -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVM_LOAD_SHA_UNIT(*pdata, next); -+ crypt_off -= 8; -+ auth_len -= 8; -+ } -+ -+ while (crypt_len > 0) { -+ uint32_t *pdata32[3]; -+ -+ pdata32[0] = data32; -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ pdata32[1] = data32; -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ pdata32[2] = data32; -+ mydata[1].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[1].data32[1] = *data32; -+ -+ CVMX_MT_AES_ENC_CBC0(*pdata); -+ CVMX_MT_AES_ENC_CBC1(*data); -+ CVMX_MF_AES_RESULT(*pdata, 0); -+ CVMX_MF_AES_RESULT(*data, 1); -+ crypt_len -= 16; -+ -+ if (auth_len > 0) { -+ CVM_LOAD_SHA_UNIT(*pdata, next); -+ auth_len -= 8; -+ } -+ if (auth_len > 0) { -+ CVM_LOAD_SHA_UNIT(*data, next); -+ auth_len -= 8; -+ } -+ -+ *pdata32[0] = mydata[0].data32[0]; -+ *pdata32[1] = mydata[0].data32[1]; -+ *pdata32[2] = mydata[1].data32[0]; -+ *data32 = mydata[1].data32[1]; -+ -+ SG_CONSUME(sg, data32, data_i, data_l); -+ } -+ -+ /* finish and hashing */ -+ while (auth_len > 0) { -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVM_LOAD_SHA_UNIT(*pdata, next); -+ auth_len -= 8; -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_SHA_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ tmp3 = 0; -+ CVMX_MF_HSH_IV(tmp3, 2); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ tmp3 |= 0x0000000080000000; -+ CVMX_MT_HSH_DAT(tmp3, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_MD5_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data32, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ icv_off -= 4; -+ } -+ CVMX_MF_HSH_IV(tmp1, 0); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ SG_CONSUME(sg, data32, data_i, data_l); -+ *data32 = (uint32_t) tmp1; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+int -+octo_aes_cbc_sha1_decrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ union { -+ uint32_t data32[2]; -+ uint64_t data64[1]; -+ } mydata[2]; -+ uint64_t *pdata = &mydata[0].data64[0]; -+ uint64_t *data = &mydata[1].data64[0]; -+ uint32_t *data32; -+ uint64_t tmp1, tmp2, tmp3; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s(a_off=%d a_len=%d c_off=%d c_len=%d icv_off=%d)\n", -+ __FUNCTION__, auth_off, auth_len, crypt_off, crypt_len, icv_off); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || -+ (crypt_len & 0x7) || -+ (auth_len & 0x7) || -+ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data32, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load AES Key */ -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ -+ if (od->octo_encklen == 16) { -+ CVMX_MT_AES_KEY(0x0, 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 24) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 32) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); -+ -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); -+ -+ /* Load SHA1 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); -+ -+ while (crypt_off > 0 && auth_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ crypt_off -= 4; -+ auth_off -= 4; -+ } -+ -+ /* align auth and crypt */ -+ while (crypt_off > 0 && auth_len > 0) { -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVM_LOAD_SHA_UNIT(*pdata, next); -+ crypt_off -= 8; -+ auth_len -= 8; -+ } -+ -+ while (crypt_len > 0) { -+ uint32_t *pdata32[3]; -+ -+ pdata32[0] = data32; -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ pdata32[1] = data32; -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ pdata32[2] = data32; -+ mydata[1].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[1].data32[1] = *data32; -+ -+ if (auth_len > 0) { -+ CVM_LOAD_SHA_UNIT(*pdata, next); -+ auth_len -= 8; -+ } -+ if (auth_len > 0) { -+ CVM_LOAD_SHA_UNIT(*data, next); -+ auth_len -= 8; -+ } -+ -+ CVMX_MT_AES_DEC_CBC0(*pdata); -+ CVMX_MT_AES_DEC_CBC1(*data); -+ CVMX_MF_AES_RESULT(*pdata, 0); -+ CVMX_MF_AES_RESULT(*data, 1); -+ crypt_len -= 16; -+ -+ *pdata32[0] = mydata[0].data32[0]; -+ *pdata32[1] = mydata[0].data32[1]; -+ *pdata32[2] = mydata[1].data32[0]; -+ *data32 = mydata[1].data32[1]; -+ -+ SG_CONSUME(sg, data32, data_i, data_l); -+ } -+ -+ /* finish and leftover hashing */ -+ while (auth_len > 0) { -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVM_LOAD_SHA_UNIT(*pdata, next); -+ auth_len -= 8; -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_SHA_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ tmp3 = 0; -+ CVMX_MF_HSH_IV(tmp3, 2); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ tmp3 |= 0x0000000080000000; -+ CVMX_MT_HSH_DAT(tmp3, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_MD5_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data32, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ icv_off -= 4; -+ } -+ CVMX_MF_HSH_IV(tmp1, 0); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ SG_CONSUME(sg, data32, data_i, data_l); -+ *data32 = (uint32_t) tmp1; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+/****************************************************************************/ -diff -Nur linux-2.6.36.orig/crypto/ocf/cryptocteon/cryptocteon.c linux-2.6.36/crypto/ocf/cryptocteon/cryptocteon.c ---- linux-2.6.36.orig/crypto/ocf/cryptocteon/cryptocteon.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/cryptocteon/cryptocteon.c 2010-11-09 20:28:04.371247488 +0100 -@@ -0,0 +1,574 @@ -+/* -+ * Octeon Crypto for OCF -+ * -+ * Written by David McCullough -+ * Copyright (C) 2009-2010 David McCullough -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ * --------------------------------------------------------------------------- -+ */ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+struct { -+ softc_device_decl sc_dev; -+} octo_softc; -+ -+#define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK) -+ -+struct octo_sess { -+ int octo_encalg; -+ #define MAX_CIPHER_KEYLEN 64 -+ char octo_enckey[MAX_CIPHER_KEYLEN]; -+ int octo_encklen; -+ -+ int octo_macalg; -+ #define MAX_HASH_KEYLEN 64 -+ char octo_mackey[MAX_HASH_KEYLEN]; -+ int octo_macklen; -+ int octo_mackey_set; -+ -+ int octo_mlen; -+ int octo_ivsize; -+ -+#if 0 -+ int (*octo_decrypt)(struct scatterlist *sg, int sg_len, -+ uint8_t *key, int key_len, uint8_t * iv, -+ uint64_t *hminner, uint64_t *hmouter); -+ -+ int (*octo_encrypt)(struct scatterlist *sg, int sg_len, -+ uint8_t *key, int key_len, uint8_t * iv, -+ uint64_t *hminner, uint64_t *hmouter); -+#else -+ int (*octo_encrypt)(struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp); -+ int (*octo_decrypt)(struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp); -+#endif -+ -+ uint64_t octo_hminner[3]; -+ uint64_t octo_hmouter[3]; -+}; -+ -+int32_t octo_id = -1; -+module_param(octo_id, int, 0444); -+MODULE_PARM_DESC(octo_id, "Read-Only OCF ID for cryptocteon driver"); -+ -+static struct octo_sess **octo_sessions = NULL; -+static u_int32_t octo_sesnum = 0; -+ -+static int octo_process(device_t, struct cryptop *, int); -+static int octo_newsession(device_t, u_int32_t *, struct cryptoini *); -+static int octo_freesession(device_t, u_int64_t); -+ -+static device_method_t octo_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, octo_newsession), -+ DEVMETHOD(cryptodev_freesession,octo_freesession), -+ DEVMETHOD(cryptodev_process, octo_process), -+}; -+ -+#define debug octo_debug -+int octo_debug = 0; -+module_param(octo_debug, int, 0644); -+MODULE_PARM_DESC(octo_debug, "Enable debug"); -+ -+ -+#include "cavium_crypto.c" -+ -+ -+/* -+ * Generate a new octo session. We artifically limit it to a single -+ * hash/cipher or hash-cipher combo just to make it easier, most callers -+ * do not expect more than this anyway. -+ */ -+static int -+octo_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) -+{ -+ struct cryptoini *c, *encini = NULL, *macini = NULL; -+ struct octo_sess **ocd; -+ int i; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid == NULL || cri == NULL) { -+ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ /* -+ * To keep it simple, we only handle hash, cipher or hash/cipher in a -+ * session, you cannot currently do multiple ciphers/hashes in one -+ * session even though it would be possibel to code this driver to -+ * handle it. -+ */ -+ for (i = 0, c = cri; c && i < 2; i++) { -+ if (c->cri_alg == CRYPTO_MD5_HMAC || -+ c->cri_alg == CRYPTO_SHA1_HMAC || -+ c->cri_alg == CRYPTO_NULL_HMAC) { -+ if (macini) { -+ break; -+ } -+ macini = c; -+ } -+ if (c->cri_alg == CRYPTO_DES_CBC || -+ c->cri_alg == CRYPTO_3DES_CBC || -+ c->cri_alg == CRYPTO_AES_CBC || -+ c->cri_alg == CRYPTO_NULL_CBC) { -+ if (encini) { -+ break; -+ } -+ encini = c; -+ } -+ c = c->cri_next; -+ } -+ if (!macini && !encini) { -+ dprintk("%s,%d - EINVAL bad cipher/hash or combination\n", -+ __FILE__, __LINE__); -+ return EINVAL; -+ } -+ if (c) { -+ dprintk("%s,%d - EINVAL cannot handle chained cipher/hash combos\n", -+ __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ /* -+ * So we have something we can do, lets setup the session -+ */ -+ -+ if (octo_sessions) { -+ for (i = 1; i < octo_sesnum; i++) -+ if (octo_sessions[i] == NULL) -+ break; -+ } else -+ i = 1; /* NB: to silence compiler warning */ -+ -+ if (octo_sessions == NULL || i == octo_sesnum) { -+ if (octo_sessions == NULL) { -+ i = 1; /* We leave octo_sessions[0] empty */ -+ octo_sesnum = CRYPTO_SW_SESSIONS; -+ } else -+ octo_sesnum *= 2; -+ -+ ocd = kmalloc(octo_sesnum * sizeof(struct octo_sess *), SLAB_ATOMIC); -+ if (ocd == NULL) { -+ /* Reset session number */ -+ if (octo_sesnum == CRYPTO_SW_SESSIONS) -+ octo_sesnum = 0; -+ else -+ octo_sesnum /= 2; -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memset(ocd, 0, octo_sesnum * sizeof(struct octo_sess *)); -+ -+ /* Copy existing sessions */ -+ if (octo_sessions) { -+ memcpy(ocd, octo_sessions, -+ (octo_sesnum / 2) * sizeof(struct octo_sess *)); -+ kfree(octo_sessions); -+ } -+ -+ octo_sessions = ocd; -+ } -+ -+ ocd = &octo_sessions[i]; -+ *sid = i; -+ -+ -+ *ocd = (struct octo_sess *) kmalloc(sizeof(struct octo_sess), SLAB_ATOMIC); -+ if (*ocd == NULL) { -+ octo_freesession(NULL, i); -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memset(*ocd, 0, sizeof(struct octo_sess)); -+ -+ if (encini && encini->cri_key) { -+ (*ocd)->octo_encklen = (encini->cri_klen + 7) / 8; -+ memcpy((*ocd)->octo_enckey, encini->cri_key, (*ocd)->octo_encklen); -+ } -+ -+ if (macini && macini->cri_key) { -+ (*ocd)->octo_macklen = (macini->cri_klen + 7) / 8; -+ memcpy((*ocd)->octo_mackey, macini->cri_key, (*ocd)->octo_macklen); -+ } -+ -+ (*ocd)->octo_mlen = 0; -+ if (encini && encini->cri_mlen) -+ (*ocd)->octo_mlen = encini->cri_mlen; -+ else if (macini && macini->cri_mlen) -+ (*ocd)->octo_mlen = macini->cri_mlen; -+ else -+ (*ocd)->octo_mlen = 12; -+ -+ /* -+ * point c at the enc if it exists, otherwise the mac -+ */ -+ c = encini ? encini : macini; -+ -+ switch (c->cri_alg) { -+ case CRYPTO_DES_CBC: -+ case CRYPTO_3DES_CBC: -+ (*ocd)->octo_ivsize = 8; -+ switch (macini ? macini->cri_alg : -1) { -+ case CRYPTO_MD5_HMAC: -+ (*ocd)->octo_encrypt = octo_des_cbc_md5_encrypt; -+ (*ocd)->octo_decrypt = octo_des_cbc_md5_decrypt; -+ octo_calc_hash(0, macini->cri_key, (*ocd)->octo_hminner, -+ (*ocd)->octo_hmouter); -+ break; -+ case CRYPTO_SHA1_HMAC: -+ (*ocd)->octo_encrypt = octo_des_cbc_sha1_encrypt; -+ (*ocd)->octo_decrypt = octo_des_cbc_sha1_encrypt; -+ octo_calc_hash(1, macini->cri_key, (*ocd)->octo_hminner, -+ (*ocd)->octo_hmouter); -+ break; -+ case -1: -+ (*ocd)->octo_encrypt = octo_des_cbc_encrypt; -+ (*ocd)->octo_decrypt = octo_des_cbc_decrypt; -+ break; -+ default: -+ octo_freesession(NULL, i); -+ dprintk("%s,%d: EINVALn", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ break; -+ case CRYPTO_AES_CBC: -+ (*ocd)->octo_ivsize = 16; -+ switch (macini ? macini->cri_alg : -1) { -+ case CRYPTO_MD5_HMAC: -+ (*ocd)->octo_encrypt = octo_aes_cbc_md5_encrypt; -+ (*ocd)->octo_decrypt = octo_aes_cbc_md5_decrypt; -+ octo_calc_hash(0, macini->cri_key, (*ocd)->octo_hminner, -+ (*ocd)->octo_hmouter); -+ break; -+ case CRYPTO_SHA1_HMAC: -+ (*ocd)->octo_encrypt = octo_aes_cbc_sha1_encrypt; -+ (*ocd)->octo_decrypt = octo_aes_cbc_sha1_decrypt; -+ octo_calc_hash(1, macini->cri_key, (*ocd)->octo_hminner, -+ (*ocd)->octo_hmouter); -+ break; -+ case -1: -+ (*ocd)->octo_encrypt = octo_aes_cbc_encrypt; -+ (*ocd)->octo_decrypt = octo_aes_cbc_decrypt; -+ break; -+ default: -+ octo_freesession(NULL, i); -+ dprintk("%s,%d: EINVALn", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ break; -+ case CRYPTO_MD5_HMAC: -+ (*ocd)->octo_encrypt = octo_null_md5_encrypt; -+ (*ocd)->octo_decrypt = octo_null_md5_encrypt; -+ octo_calc_hash(0, macini->cri_key, (*ocd)->octo_hminner, -+ (*ocd)->octo_hmouter); -+ break; -+ case CRYPTO_SHA1_HMAC: -+ (*ocd)->octo_encrypt = octo_null_sha1_encrypt; -+ (*ocd)->octo_decrypt = octo_null_sha1_encrypt; -+ octo_calc_hash(1, macini->cri_key, (*ocd)->octo_hminner, -+ (*ocd)->octo_hmouter); -+ break; -+ default: -+ octo_freesession(NULL, i); -+ dprintk("%s,%d: EINVALn", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ (*ocd)->octo_encalg = encini ? encini->cri_alg : -1; -+ (*ocd)->octo_macalg = macini ? macini->cri_alg : -1; -+ -+ return 0; -+} -+ -+/* -+ * Free a session. -+ */ -+static int -+octo_freesession(device_t dev, u_int64_t tid) -+{ -+ u_int32_t sid = CRYPTO_SESID2LID(tid); -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid > octo_sesnum || octo_sessions == NULL || -+ octo_sessions[sid] == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return(EINVAL); -+ } -+ -+ /* Silently accept and return */ -+ if (sid == 0) -+ return(0); -+ -+ if (octo_sessions[sid]) -+ kfree(octo_sessions[sid]); -+ octo_sessions[sid] = NULL; -+ return 0; -+} -+ -+/* -+ * Process a request. -+ */ -+static int -+octo_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ struct cryptodesc *crd; -+ struct octo_sess *od; -+ u_int32_t lid; -+#define SCATTERLIST_MAX 16 -+ struct scatterlist sg[SCATTERLIST_MAX]; -+ int sg_num, sg_len; -+ struct sk_buff *skb = NULL; -+ struct uio *uiop = NULL; -+ struct cryptodesc *enccrd = NULL, *maccrd = NULL; -+ unsigned char *ivp = NULL; -+ unsigned char iv_data[HASH_MAX_LEN]; -+ int auth_off = 0, auth_len = 0, crypt_off = 0, crypt_len = 0, icv_off = 0; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ /* Sanity check */ -+ if (crp == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ crp->crp_etype = 0; -+ -+ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ lid = crp->crp_sid & 0xffffffff; -+ if (lid >= octo_sesnum || lid == 0 || octo_sessions == NULL || -+ octo_sessions[lid] == NULL) { -+ crp->crp_etype = ENOENT; -+ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); -+ goto done; -+ } -+ od = octo_sessions[lid]; -+ -+ /* -+ * do some error checking outside of the loop for SKB and IOV processing -+ * this leaves us with valid skb or uiop pointers for later -+ */ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ skb = (struct sk_buff *) crp->crp_buf; -+ if (skb_shinfo(skb)->nr_frags >= SCATTERLIST_MAX) { -+ printk("%s,%d: %d nr_frags > SCATTERLIST_MAX", __FILE__, __LINE__, -+ skb_shinfo(skb)->nr_frags); -+ goto done; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ uiop = (struct uio *) crp->crp_buf; -+ if (uiop->uio_iovcnt > SCATTERLIST_MAX) { -+ printk("%s,%d: %d uio_iovcnt > SCATTERLIST_MAX", __FILE__, __LINE__, -+ uiop->uio_iovcnt); -+ goto done; -+ } -+ } -+ -+ /* point our enccrd and maccrd appropriately */ -+ crd = crp->crp_desc; -+ if (crd->crd_alg == od->octo_encalg) enccrd = crd; -+ if (crd->crd_alg == od->octo_macalg) maccrd = crd; -+ crd = crd->crd_next; -+ if (crd) { -+ if (crd->crd_alg == od->octo_encalg) enccrd = crd; -+ if (crd->crd_alg == od->octo_macalg) maccrd = crd; -+ crd = crd->crd_next; -+ } -+ if (crd) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: ENOENT - descriptors do not match session\n", -+ __FILE__, __LINE__); -+ goto done; -+ } -+ -+ if (enccrd) { -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) { -+ ivp = enccrd->crd_iv; -+ } else { -+ ivp = iv_data; -+ crypto_copydata(crp->crp_flags, crp->crp_buf, -+ enccrd->crd_inject, od->octo_ivsize, (caddr_t) ivp); -+ } -+ -+ if (maccrd) { -+ auth_off = maccrd->crd_skip; -+ auth_len = maccrd->crd_len; -+ icv_off = maccrd->crd_inject; -+ } -+ -+ crypt_off = enccrd->crd_skip; -+ crypt_len = enccrd->crd_len; -+ } else { /* if (maccrd) */ -+ auth_off = maccrd->crd_skip; -+ auth_len = maccrd->crd_len; -+ icv_off = maccrd->crd_inject; -+ } -+ -+ -+ /* -+ * setup the SG list to cover the buffer -+ */ -+ memset(sg, 0, sizeof(sg)); -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ int i, len; -+ -+ sg_num = 0; -+ sg_len = 0; -+ -+ len = skb_headlen(skb); -+ sg_set_page(&sg[sg_num], virt_to_page(skb->data), len, -+ offset_in_page(skb->data)); -+ sg_len += len; -+ sg_num++; -+ -+ for (i = 0; i < skb_shinfo(skb)->nr_frags && sg_num < SCATTERLIST_MAX; -+ i++) { -+ len = skb_shinfo(skb)->frags[i].size; -+ sg_set_page(&sg[sg_num], skb_shinfo(skb)->frags[i].page, -+ len, skb_shinfo(skb)->frags[i].page_offset); -+ sg_len += len; -+ sg_num++; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ int len; -+ -+ sg_len = 0; -+ for (sg_num = 0; sg_len < crp->crp_ilen && -+ sg_num < uiop->uio_iovcnt && -+ sg_num < SCATTERLIST_MAX; sg_num++) { -+ len = uiop->uio_iov[sg_num].iov_len; -+ sg_set_page(&sg[sg_num], -+ virt_to_page(uiop->uio_iov[sg_num].iov_base), len, -+ offset_in_page(uiop->uio_iov[sg_num].iov_base)); -+ sg_len += len; -+ } -+ } else { -+ sg_len = crp->crp_ilen; -+ sg_set_page(&sg[0], virt_to_page(crp->crp_buf), sg_len, -+ offset_in_page(crp->crp_buf)); -+ sg_num = 1; -+ } -+ -+ -+ /* -+ * setup a new explicit key -+ */ -+ if (enccrd) { -+ if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) { -+ od->octo_encklen = (enccrd->crd_klen + 7) / 8; -+ memcpy(od->octo_enckey, enccrd->crd_key, od->octo_encklen); -+ } -+ } -+ if (maccrd) { -+ if (maccrd->crd_flags & CRD_F_KEY_EXPLICIT) { -+ od->octo_macklen = (maccrd->crd_klen + 7) / 8; -+ memcpy(od->octo_mackey, maccrd->crd_key, od->octo_macklen); -+ od->octo_mackey_set = 0; -+ } -+ if (!od->octo_mackey_set) { -+ octo_calc_hash(maccrd->crd_alg == CRYPTO_MD5_HMAC ? 0 : 1, -+ maccrd->crd_key, od->octo_hminner, od->octo_hmouter); -+ od->octo_mackey_set = 1; -+ } -+ } -+ -+ -+ if (!enccrd || (enccrd->crd_flags & CRD_F_ENCRYPT)) -+ (*od->octo_encrypt)(od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ else -+ (*od->octo_decrypt)(od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ -+done: -+ crypto_done(crp); -+ return 0; -+} -+ -+static int -+cryptocteon_init(void) -+{ -+ dprintk("%s(%p)\n", __FUNCTION__, cryptocteon_init); -+ -+ softc_device_init(&octo_softc, "cryptocteon", 0, octo_methods); -+ -+ octo_id = crypto_get_driverid(softc_get_device(&octo_softc), -+ CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SYNC); -+ if (octo_id < 0) { -+ printk("Cryptocteon device cannot initialize!"); -+ return -ENODEV; -+ } -+ -+ crypto_register(octo_id, CRYPTO_MD5_HMAC, 0,0); -+ crypto_register(octo_id, CRYPTO_SHA1_HMAC, 0,0); -+ //crypto_register(octo_id, CRYPTO_MD5, 0,0); -+ //crypto_register(octo_id, CRYPTO_SHA1, 0,0); -+ crypto_register(octo_id, CRYPTO_DES_CBC, 0,0); -+ crypto_register(octo_id, CRYPTO_3DES_CBC, 0,0); -+ crypto_register(octo_id, CRYPTO_AES_CBC, 0,0); -+ -+ return(0); -+} -+ -+static void -+cryptocteon_exit(void) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ crypto_unregister_all(octo_id); -+ octo_id = -1; -+} -+ -+module_init(cryptocteon_init); -+module_exit(cryptocteon_exit); -+ -+MODULE_LICENSE("BSD"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("Cryptocteon (OCF module for Cavium OCTEON crypto)"); -diff -Nur linux-2.6.36.orig/crypto/ocf/cryptocteon/Makefile linux-2.6.36/crypto/ocf/cryptocteon/Makefile ---- linux-2.6.36.orig/crypto/ocf/cryptocteon/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/cryptocteon/Makefile 2010-11-09 20:28:04.411246358 +0100 -@@ -0,0 +1,17 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+obj-$(CONFIG_OCF_CRYPTOCTEON) += cryptocteon.o -+ -+obj ?= . -+EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ -+ -+ifdef CONFIG_OCF_CRYPTOCTEON -+# you need the cavium crypto component installed -+EXTRA_CFLAGS += -I$(ROOTDIR)/prop/include -+endif -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/cryptodev.c linux-2.6.36/crypto/ocf/cryptodev.c ---- linux-2.6.36.orig/crypto/ocf/cryptodev.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/cryptodev.c 2010-11-09 20:29:09.284996310 +0100 -@@ -0,0 +1,1060 @@ -+/* $OpenBSD: cryptodev.c,v 1.52 2002/06/19 07:22:46 deraadt Exp $ */ -+ -+/*- -+ * Linux port done by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * The license and original author are listed below. -+ * -+ * Copyright (c) 2001 Theo de Raadt -+ * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored in part by the Defense Advanced Research Projects -+ * Agency (DARPA) and Air Force Research Laboratory, Air Force -+ * Materiel Command, USAF, under agreement number F30602-01-2-0537. -+ * -+__FBSDID("$FreeBSD: src/sys/opencrypto/cryptodev.c,v 1.34 2007/05/09 19:37:02 gnn Exp $"); -+ */ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+extern asmlinkage long sys_dup(unsigned int fildes); -+ -+#define debug cryptodev_debug -+int cryptodev_debug = 0; -+module_param(cryptodev_debug, int, 0644); -+MODULE_PARM_DESC(cryptodev_debug, "Enable cryptodev debug"); -+ -+struct csession_info { -+ u_int16_t blocksize; -+ u_int16_t minkey, maxkey; -+ -+ u_int16_t keysize; -+ /* u_int16_t hashsize; */ -+ u_int16_t authsize; -+ u_int16_t authkey; -+ /* u_int16_t ctxsize; */ -+}; -+ -+struct csession { -+ struct list_head list; -+ u_int64_t sid; -+ u_int32_t ses; -+ -+ wait_queue_head_t waitq; -+ -+ u_int32_t cipher; -+ -+ u_int32_t mac; -+ -+ caddr_t key; -+ int keylen; -+ u_char tmp_iv[EALG_MAX_BLOCK_LEN]; -+ -+ caddr_t mackey; -+ int mackeylen; -+ -+ struct csession_info info; -+ -+ struct iovec iovec; -+ struct uio uio; -+ int error; -+}; -+ -+struct fcrypt { -+ struct list_head csessions; -+ int sesn; -+}; -+ -+static struct csession *csefind(struct fcrypt *, u_int); -+static int csedelete(struct fcrypt *, struct csession *); -+static struct csession *cseadd(struct fcrypt *, struct csession *); -+static struct csession *csecreate(struct fcrypt *, u_int64_t, -+ struct cryptoini *crie, struct cryptoini *cria, struct csession_info *); -+static int csefree(struct csession *); -+ -+static int cryptodev_op(struct csession *, struct crypt_op *); -+static int cryptodev_key(struct crypt_kop *); -+static int cryptodev_find(struct crypt_find_op *); -+ -+static int cryptodev_cb(void *); -+static int cryptodev_open(struct inode *inode, struct file *filp); -+ -+/* -+ * Check a crypto identifier to see if it requested -+ * a valid crid and it's capabilities match. -+ */ -+static int -+checkcrid(int crid) -+{ -+ int hid = crid & ~(CRYPTOCAP_F_SOFTWARE | CRYPTOCAP_F_HARDWARE); -+ int typ = crid & (CRYPTOCAP_F_SOFTWARE | CRYPTOCAP_F_HARDWARE); -+ int caps = 0; -+ -+ /* if the user hasn't selected a driver, then just call newsession */ -+ if (hid == 0 && typ != 0) -+ return 0; -+ -+ caps = crypto_getcaps(hid); -+ -+ /* didn't find anything with capabilities */ -+ if (caps == 0) { -+ dprintk("%s: hid=%x typ=%x not matched\n", __FUNCTION__, hid, typ); -+ return EINVAL; -+ } -+ -+ /* the user didn't specify SW or HW, so the driver is ok */ -+ if (typ == 0) -+ return 0; -+ -+ /* if the type specified didn't match */ -+ if (typ != (caps & (CRYPTOCAP_F_SOFTWARE | CRYPTOCAP_F_HARDWARE))) { -+ dprintk("%s: hid=%x typ=%x caps=%x not matched\n", __FUNCTION__, -+ hid, typ, caps); -+ return EINVAL; -+ } -+ -+ return 0; -+} -+ -+static int -+cryptodev_op(struct csession *cse, struct crypt_op *cop) -+{ -+ struct cryptop *crp = NULL; -+ struct cryptodesc *crde = NULL, *crda = NULL; -+ int error = 0; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (cop->len > CRYPTO_MAX_DATA_LEN) { -+ dprintk("%s: %d > %d\n", __FUNCTION__, cop->len, CRYPTO_MAX_DATA_LEN); -+ return (E2BIG); -+ } -+ -+ if (cse->info.blocksize && (cop->len % cse->info.blocksize) != 0) { -+ dprintk("%s: blocksize=%d len=%d\n", __FUNCTION__, cse->info.blocksize, -+ cop->len); -+ return (EINVAL); -+ } -+ -+ cse->uio.uio_iov = &cse->iovec; -+ cse->uio.uio_iovcnt = 1; -+ cse->uio.uio_offset = 0; -+#if 0 -+ cse->uio.uio_resid = cop->len; -+ cse->uio.uio_segflg = UIO_SYSSPACE; -+ cse->uio.uio_rw = UIO_WRITE; -+ cse->uio.uio_td = td; -+#endif -+ cse->uio.uio_iov[0].iov_len = cop->len; -+ if (cse->info.authsize) -+ cse->uio.uio_iov[0].iov_len += cse->info.authsize; -+ cse->uio.uio_iov[0].iov_base = kmalloc(cse->uio.uio_iov[0].iov_len, -+ GFP_KERNEL); -+ -+ if (cse->uio.uio_iov[0].iov_base == NULL) { -+ dprintk("%s: iov_base kmalloc(%d) failed\n", __FUNCTION__, -+ (int)cse->uio.uio_iov[0].iov_len); -+ return (ENOMEM); -+ } -+ -+ crp = crypto_getreq((cse->info.blocksize != 0) + (cse->info.authsize != 0)); -+ if (crp == NULL) { -+ dprintk("%s: ENOMEM\n", __FUNCTION__); -+ error = ENOMEM; -+ goto bail; -+ } -+ -+ if (cse->info.authsize && cse->info.blocksize) { -+ if (cop->op == COP_ENCRYPT) { -+ crde = crp->crp_desc; -+ crda = crde->crd_next; -+ } else { -+ crda = crp->crp_desc; -+ crde = crda->crd_next; -+ } -+ } else if (cse->info.authsize) { -+ crda = crp->crp_desc; -+ } else if (cse->info.blocksize) { -+ crde = crp->crp_desc; -+ } else { -+ dprintk("%s: bad request\n", __FUNCTION__); -+ error = EINVAL; -+ goto bail; -+ } -+ -+ if ((error = copy_from_user(cse->uio.uio_iov[0].iov_base, cop->src, -+ cop->len))) { -+ dprintk("%s: bad copy\n", __FUNCTION__); -+ goto bail; -+ } -+ -+ if (crda) { -+ crda->crd_skip = 0; -+ crda->crd_len = cop->len; -+ crda->crd_inject = cop->len; -+ -+ crda->crd_alg = cse->mac; -+ crda->crd_key = cse->mackey; -+ crda->crd_klen = cse->mackeylen * 8; -+ } -+ -+ if (crde) { -+ if (cop->op == COP_ENCRYPT) -+ crde->crd_flags |= CRD_F_ENCRYPT; -+ else -+ crde->crd_flags &= ~CRD_F_ENCRYPT; -+ crde->crd_len = cop->len; -+ crde->crd_inject = 0; -+ -+ crde->crd_alg = cse->cipher; -+ crde->crd_key = cse->key; -+ crde->crd_klen = cse->keylen * 8; -+ } -+ -+ crp->crp_ilen = cse->uio.uio_iov[0].iov_len; -+ crp->crp_flags = CRYPTO_F_IOV | CRYPTO_F_CBIMM -+ | (cop->flags & COP_F_BATCH); -+ crp->crp_buf = (caddr_t)&cse->uio; -+ crp->crp_callback = (int (*) (struct cryptop *)) cryptodev_cb; -+ crp->crp_sid = cse->sid; -+ crp->crp_opaque = (void *)cse; -+ -+ if (cop->iv) { -+ if (crde == NULL) { -+ error = EINVAL; -+ dprintk("%s no crde\n", __FUNCTION__); -+ goto bail; -+ } -+ if (cse->cipher == CRYPTO_ARC4) { /* XXX use flag? */ -+ error = EINVAL; -+ dprintk("%s arc4 with IV\n", __FUNCTION__); -+ goto bail; -+ } -+ if ((error = copy_from_user(cse->tmp_iv, cop->iv, -+ cse->info.blocksize))) { -+ dprintk("%s bad iv copy\n", __FUNCTION__); -+ goto bail; -+ } -+ memcpy(crde->crd_iv, cse->tmp_iv, cse->info.blocksize); -+ crde->crd_flags |= CRD_F_IV_EXPLICIT | CRD_F_IV_PRESENT; -+ crde->crd_skip = 0; -+ } else if (cse->cipher == CRYPTO_ARC4) { /* XXX use flag? */ -+ crde->crd_skip = 0; -+ } else if (crde) { -+ crde->crd_flags |= CRD_F_IV_PRESENT; -+ crde->crd_skip = cse->info.blocksize; -+ crde->crd_len -= cse->info.blocksize; -+ } -+ -+ if (cop->mac && crda == NULL) { -+ error = EINVAL; -+ dprintk("%s no crda\n", __FUNCTION__); -+ goto bail; -+ } -+ -+ /* -+ * Let the dispatch run unlocked, then, interlock against the -+ * callback before checking if the operation completed and going -+ * to sleep. This insures drivers don't inherit our lock which -+ * results in a lock order reversal between crypto_dispatch forced -+ * entry and the crypto_done callback into us. -+ */ -+ error = crypto_dispatch(crp); -+ if (error) { -+ dprintk("%s error in crypto_dispatch\n", __FUNCTION__); -+ goto bail; -+ } -+ -+ dprintk("%s about to WAIT\n", __FUNCTION__); -+ /* -+ * we really need to wait for driver to complete to maintain -+ * state, luckily interrupts will be remembered -+ */ -+ do { -+ error = wait_event_interruptible(crp->crp_waitq, -+ ((crp->crp_flags & CRYPTO_F_DONE) != 0)); -+ /* -+ * we can't break out of this loop or we will leave behind -+ * a huge mess, however, staying here means if your driver -+ * is broken user applications can hang and not be killed. -+ * The solution, fix your driver :-) -+ */ -+ if (error) { -+ schedule(); -+ error = 0; -+ } -+ } while ((crp->crp_flags & CRYPTO_F_DONE) == 0); -+ dprintk("%s finished WAITING error=%d\n", __FUNCTION__, error); -+ -+ if (crp->crp_etype != 0) { -+ error = crp->crp_etype; -+ dprintk("%s error in crp processing\n", __FUNCTION__); -+ goto bail; -+ } -+ -+ if (cse->error) { -+ error = cse->error; -+ dprintk("%s error in cse processing\n", __FUNCTION__); -+ goto bail; -+ } -+ -+ if (cop->dst && (error = copy_to_user(cop->dst, -+ cse->uio.uio_iov[0].iov_base, cop->len))) { -+ dprintk("%s bad dst copy\n", __FUNCTION__); -+ goto bail; -+ } -+ -+ if (cop->mac && -+ (error=copy_to_user(cop->mac, -+ (caddr_t)cse->uio.uio_iov[0].iov_base + cop->len, -+ cse->info.authsize))) { -+ dprintk("%s bad mac copy\n", __FUNCTION__); -+ goto bail; -+ } -+ -+bail: -+ if (crp) -+ crypto_freereq(crp); -+ if (cse->uio.uio_iov[0].iov_base) -+ kfree(cse->uio.uio_iov[0].iov_base); -+ -+ return (error); -+} -+ -+static int -+cryptodev_cb(void *op) -+{ -+ struct cryptop *crp = (struct cryptop *) op; -+ struct csession *cse = (struct csession *)crp->crp_opaque; -+ int error; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ error = crp->crp_etype; -+ if (error == EAGAIN) { -+ crp->crp_flags &= ~CRYPTO_F_DONE; -+#ifdef NOTYET -+ /* -+ * DAVIDM I am fairly sure that we should turn this into a batch -+ * request to stop bad karma/lockup, revisit -+ */ -+ crp->crp_flags |= CRYPTO_F_BATCH; -+#endif -+ return crypto_dispatch(crp); -+ } -+ if (error != 0 || (crp->crp_flags & CRYPTO_F_DONE)) { -+ cse->error = error; -+ wake_up_interruptible(&crp->crp_waitq); -+ } -+ return (0); -+} -+ -+static int -+cryptodevkey_cb(void *op) -+{ -+ struct cryptkop *krp = (struct cryptkop *) op; -+ dprintk("%s()\n", __FUNCTION__); -+ wake_up_interruptible(&krp->krp_waitq); -+ return (0); -+} -+ -+static int -+cryptodev_key(struct crypt_kop *kop) -+{ -+ struct cryptkop *krp = NULL; -+ int error = EINVAL; -+ int in, out, size, i; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (kop->crk_iparams + kop->crk_oparams > CRK_MAXPARAM) { -+ dprintk("%s params too big\n", __FUNCTION__); -+ return (EFBIG); -+ } -+ -+ in = kop->crk_iparams; -+ out = kop->crk_oparams; -+ switch (kop->crk_op) { -+ case CRK_MOD_EXP: -+ if (in == 3 && out == 1) -+ break; -+ return (EINVAL); -+ case CRK_MOD_EXP_CRT: -+ if (in == 6 && out == 1) -+ break; -+ return (EINVAL); -+ case CRK_DSA_SIGN: -+ if (in == 5 && out == 2) -+ break; -+ return (EINVAL); -+ case CRK_DSA_VERIFY: -+ if (in == 7 && out == 0) -+ break; -+ return (EINVAL); -+ case CRK_DH_COMPUTE_KEY: -+ if (in == 3 && out == 1) -+ break; -+ return (EINVAL); -+ default: -+ return (EINVAL); -+ } -+ -+ krp = (struct cryptkop *)kmalloc(sizeof *krp, GFP_KERNEL); -+ if (!krp) -+ return (ENOMEM); -+ bzero(krp, sizeof *krp); -+ krp->krp_op = kop->crk_op; -+ krp->krp_status = kop->crk_status; -+ krp->krp_iparams = kop->crk_iparams; -+ krp->krp_oparams = kop->crk_oparams; -+ krp->krp_crid = kop->crk_crid; -+ krp->krp_status = 0; -+ krp->krp_flags = CRYPTO_KF_CBIMM; -+ krp->krp_callback = (int (*) (struct cryptkop *)) cryptodevkey_cb; -+ init_waitqueue_head(&krp->krp_waitq); -+ -+ for (i = 0; i < CRK_MAXPARAM; i++) -+ krp->krp_param[i].crp_nbits = kop->crk_param[i].crp_nbits; -+ for (i = 0; i < krp->krp_iparams + krp->krp_oparams; i++) { -+ size = (krp->krp_param[i].crp_nbits + 7) / 8; -+ if (size == 0) -+ continue; -+ krp->krp_param[i].crp_p = (caddr_t) kmalloc(size, GFP_KERNEL); -+ if (i >= krp->krp_iparams) -+ continue; -+ error = copy_from_user(krp->krp_param[i].crp_p, -+ kop->crk_param[i].crp_p, size); -+ if (error) -+ goto fail; -+ } -+ -+ error = crypto_kdispatch(krp); -+ if (error) -+ goto fail; -+ -+ do { -+ error = wait_event_interruptible(krp->krp_waitq, -+ ((krp->krp_flags & CRYPTO_KF_DONE) != 0)); -+ /* -+ * we can't break out of this loop or we will leave behind -+ * a huge mess, however, staying here means if your driver -+ * is broken user applications can hang and not be killed. -+ * The solution, fix your driver :-) -+ */ -+ if (error) { -+ schedule(); -+ error = 0; -+ } -+ } while ((krp->krp_flags & CRYPTO_KF_DONE) == 0); -+ -+ dprintk("%s finished WAITING error=%d\n", __FUNCTION__, error); -+ -+ kop->crk_crid = krp->krp_crid; /* device that did the work */ -+ if (krp->krp_status != 0) { -+ error = krp->krp_status; -+ goto fail; -+ } -+ -+ for (i = krp->krp_iparams; i < krp->krp_iparams + krp->krp_oparams; i++) { -+ size = (krp->krp_param[i].crp_nbits + 7) / 8; -+ if (size == 0) -+ continue; -+ error = copy_to_user(kop->crk_param[i].crp_p, krp->krp_param[i].crp_p, -+ size); -+ if (error) -+ goto fail; -+ } -+ -+fail: -+ if (krp) { -+ kop->crk_status = krp->krp_status; -+ for (i = 0; i < CRK_MAXPARAM; i++) { -+ if (krp->krp_param[i].crp_p) -+ kfree(krp->krp_param[i].crp_p); -+ } -+ kfree(krp); -+ } -+ return (error); -+} -+ -+static int -+cryptodev_find(struct crypt_find_op *find) -+{ -+ device_t dev; -+ -+ if (find->crid != -1) { -+ dev = crypto_find_device_byhid(find->crid); -+ if (dev == NULL) -+ return (ENOENT); -+ strlcpy(find->name, device_get_nameunit(dev), -+ sizeof(find->name)); -+ } else { -+ find->crid = crypto_find_driver(find->name); -+ if (find->crid == -1) -+ return (ENOENT); -+ } -+ return (0); -+} -+ -+static struct csession * -+csefind(struct fcrypt *fcr, u_int ses) -+{ -+ struct csession *cse; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ list_for_each_entry(cse, &fcr->csessions, list) -+ if (cse->ses == ses) -+ return (cse); -+ return (NULL); -+} -+ -+static int -+csedelete(struct fcrypt *fcr, struct csession *cse_del) -+{ -+ struct csession *cse; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ list_for_each_entry(cse, &fcr->csessions, list) { -+ if (cse == cse_del) { -+ list_del(&cse->list); -+ return (1); -+ } -+ } -+ return (0); -+} -+ -+static struct csession * -+cseadd(struct fcrypt *fcr, struct csession *cse) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ list_add_tail(&cse->list, &fcr->csessions); -+ cse->ses = fcr->sesn++; -+ return (cse); -+} -+ -+static struct csession * -+csecreate(struct fcrypt *fcr, u_int64_t sid, struct cryptoini *crie, -+ struct cryptoini *cria, struct csession_info *info) -+{ -+ struct csession *cse; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ cse = (struct csession *) kmalloc(sizeof(struct csession), GFP_KERNEL); -+ if (cse == NULL) -+ return NULL; -+ memset(cse, 0, sizeof(struct csession)); -+ -+ INIT_LIST_HEAD(&cse->list); -+ init_waitqueue_head(&cse->waitq); -+ -+ cse->key = crie->cri_key; -+ cse->keylen = crie->cri_klen/8; -+ cse->mackey = cria->cri_key; -+ cse->mackeylen = cria->cri_klen/8; -+ cse->sid = sid; -+ cse->cipher = crie->cri_alg; -+ cse->mac = cria->cri_alg; -+ cse->info = *info; -+ cseadd(fcr, cse); -+ return (cse); -+} -+ -+static int -+csefree(struct csession *cse) -+{ -+ int error; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ error = crypto_freesession(cse->sid); -+ if (cse->key) -+ kfree(cse->key); -+ if (cse->mackey) -+ kfree(cse->mackey); -+ kfree(cse); -+ return(error); -+} -+ -+static int -+cryptodev_ioctl( -+ struct inode *inode, -+ struct file *filp, -+ unsigned int cmd, -+ unsigned long arg) -+{ -+ struct cryptoini cria, crie; -+ struct fcrypt *fcr = filp->private_data; -+ struct csession *cse; -+ struct csession_info info; -+ struct session2_op sop; -+ struct crypt_op cop; -+ struct crypt_kop kop; -+ struct crypt_find_op fop; -+ u_int64_t sid; -+ u_int32_t ses = 0; -+ int feat, fd, error = 0, crid; -+ mm_segment_t fs; -+ -+ dprintk("%s(cmd=%x arg=%lx)\n", __FUNCTION__, cmd, arg); -+ -+ switch (cmd) { -+ -+ case CRIOGET: { -+ dprintk("%s(CRIOGET)\n", __FUNCTION__); -+ fs = get_fs(); -+ set_fs(get_ds()); -+ for (fd = 0; fd < files_fdtable(current->files)->max_fds; fd++) -+ if (files_fdtable(current->files)->fd[fd] == filp) -+ break; -+ fd = sys_dup(fd); -+ set_fs(fs); -+ put_user(fd, (int *) arg); -+ return IS_ERR_VALUE(fd) ? fd : 0; -+ } -+ -+#define CIOCGSESSSTR (cmd == CIOCGSESSION ? "CIOCGSESSION" : "CIOCGSESSION2") -+ case CIOCGSESSION: -+ case CIOCGSESSION2: -+ dprintk("%s(%s)\n", __FUNCTION__, CIOCGSESSSTR); -+ memset(&crie, 0, sizeof(crie)); -+ memset(&cria, 0, sizeof(cria)); -+ memset(&info, 0, sizeof(info)); -+ memset(&sop, 0, sizeof(sop)); -+ -+ if (copy_from_user(&sop, (void*)arg, (cmd == CIOCGSESSION) ? -+ sizeof(struct session_op) : sizeof(sop))) { -+ dprintk("%s(%s) - bad copy\n", __FUNCTION__, CIOCGSESSSTR); -+ error = EFAULT; -+ goto bail; -+ } -+ -+ switch (sop.cipher) { -+ case 0: -+ dprintk("%s(%s) - no cipher\n", __FUNCTION__, CIOCGSESSSTR); -+ break; -+ case CRYPTO_NULL_CBC: -+ info.blocksize = NULL_BLOCK_LEN; -+ info.minkey = NULL_MIN_KEY_LEN; -+ info.maxkey = NULL_MAX_KEY_LEN; -+ break; -+ case CRYPTO_DES_CBC: -+ info.blocksize = DES_BLOCK_LEN; -+ info.minkey = DES_MIN_KEY_LEN; -+ info.maxkey = DES_MAX_KEY_LEN; -+ break; -+ case CRYPTO_3DES_CBC: -+ info.blocksize = DES3_BLOCK_LEN; -+ info.minkey = DES3_MIN_KEY_LEN; -+ info.maxkey = DES3_MAX_KEY_LEN; -+ break; -+ case CRYPTO_BLF_CBC: -+ info.blocksize = BLOWFISH_BLOCK_LEN; -+ info.minkey = BLOWFISH_MIN_KEY_LEN; -+ info.maxkey = BLOWFISH_MAX_KEY_LEN; -+ break; -+ case CRYPTO_CAST_CBC: -+ info.blocksize = CAST128_BLOCK_LEN; -+ info.minkey = CAST128_MIN_KEY_LEN; -+ info.maxkey = CAST128_MAX_KEY_LEN; -+ break; -+ case CRYPTO_SKIPJACK_CBC: -+ info.blocksize = SKIPJACK_BLOCK_LEN; -+ info.minkey = SKIPJACK_MIN_KEY_LEN; -+ info.maxkey = SKIPJACK_MAX_KEY_LEN; -+ break; -+ case CRYPTO_AES_CBC: -+ info.blocksize = AES_BLOCK_LEN; -+ info.minkey = AES_MIN_KEY_LEN; -+ info.maxkey = AES_MAX_KEY_LEN; -+ break; -+ case CRYPTO_ARC4: -+ info.blocksize = ARC4_BLOCK_LEN; -+ info.minkey = ARC4_MIN_KEY_LEN; -+ info.maxkey = ARC4_MAX_KEY_LEN; -+ break; -+ case CRYPTO_CAMELLIA_CBC: -+ info.blocksize = CAMELLIA_BLOCK_LEN; -+ info.minkey = CAMELLIA_MIN_KEY_LEN; -+ info.maxkey = CAMELLIA_MAX_KEY_LEN; -+ break; -+ default: -+ dprintk("%s(%s) - bad cipher\n", __FUNCTION__, CIOCGSESSSTR); -+ error = EINVAL; -+ goto bail; -+ } -+ -+ switch (sop.mac) { -+ case 0: -+ dprintk("%s(%s) - no mac\n", __FUNCTION__, CIOCGSESSSTR); -+ break; -+ case CRYPTO_NULL_HMAC: -+ info.authsize = NULL_HASH_LEN; -+ break; -+ case CRYPTO_MD5: -+ info.authsize = MD5_HASH_LEN; -+ break; -+ case CRYPTO_SHA1: -+ info.authsize = SHA1_HASH_LEN; -+ break; -+ case CRYPTO_SHA2_256: -+ info.authsize = SHA2_256_HASH_LEN; -+ break; -+ case CRYPTO_SHA2_384: -+ info.authsize = SHA2_384_HASH_LEN; -+ break; -+ case CRYPTO_SHA2_512: -+ info.authsize = SHA2_512_HASH_LEN; -+ break; -+ case CRYPTO_RIPEMD160: -+ info.authsize = RIPEMD160_HASH_LEN; -+ break; -+ case CRYPTO_MD5_HMAC: -+ info.authsize = MD5_HASH_LEN; -+ info.authkey = 16; -+ break; -+ case CRYPTO_SHA1_HMAC: -+ info.authsize = SHA1_HASH_LEN; -+ info.authkey = 20; -+ break; -+ case CRYPTO_SHA2_256_HMAC: -+ info.authsize = SHA2_256_HASH_LEN; -+ info.authkey = 32; -+ break; -+ case CRYPTO_SHA2_384_HMAC: -+ info.authsize = SHA2_384_HASH_LEN; -+ info.authkey = 48; -+ break; -+ case CRYPTO_SHA2_512_HMAC: -+ info.authsize = SHA2_512_HASH_LEN; -+ info.authkey = 64; -+ break; -+ case CRYPTO_RIPEMD160_HMAC: -+ info.authsize = RIPEMD160_HASH_LEN; -+ info.authkey = 20; -+ break; -+ default: -+ dprintk("%s(%s) - bad mac\n", __FUNCTION__, CIOCGSESSSTR); -+ error = EINVAL; -+ goto bail; -+ } -+ -+ if (info.blocksize) { -+ crie.cri_alg = sop.cipher; -+ crie.cri_klen = sop.keylen * 8; -+ if ((info.maxkey && sop.keylen > info.maxkey) || -+ sop.keylen < info.minkey) { -+ dprintk("%s(%s) - bad key\n", __FUNCTION__, CIOCGSESSSTR); -+ error = EINVAL; -+ goto bail; -+ } -+ -+ crie.cri_key = (u_int8_t *) kmalloc(crie.cri_klen/8+1, GFP_KERNEL); -+ if (copy_from_user(crie.cri_key, sop.key, -+ crie.cri_klen/8)) { -+ dprintk("%s(%s) - bad copy\n", __FUNCTION__, CIOCGSESSSTR); -+ error = EFAULT; -+ goto bail; -+ } -+ if (info.authsize) -+ crie.cri_next = &cria; -+ } -+ -+ if (info.authsize) { -+ cria.cri_alg = sop.mac; -+ cria.cri_klen = sop.mackeylen * 8; -+ if (info.authkey && sop.mackeylen != info.authkey) { -+ dprintk("%s(%s) - mackeylen %d != %d\n", __FUNCTION__, -+ CIOCGSESSSTR, sop.mackeylen, info.authkey); -+ error = EINVAL; -+ goto bail; -+ } -+ -+ if (cria.cri_klen) { -+ cria.cri_key = (u_int8_t *) kmalloc(cria.cri_klen/8,GFP_KERNEL); -+ if (copy_from_user(cria.cri_key, sop.mackey, -+ cria.cri_klen / 8)) { -+ dprintk("%s(%s) - bad copy\n", __FUNCTION__, CIOCGSESSSTR); -+ error = EFAULT; -+ goto bail; -+ } -+ } -+ } -+ -+ /* NB: CIOGSESSION2 has the crid */ -+ if (cmd == CIOCGSESSION2) { -+ crid = sop.crid; -+ error = checkcrid(crid); -+ if (error) { -+ dprintk("%s(%s) - checkcrid %x\n", __FUNCTION__, -+ CIOCGSESSSTR, error); -+ goto bail; -+ } -+ } else { -+ /* allow either HW or SW to be used */ -+ crid = CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE; -+ } -+ error = crypto_newsession(&sid, (info.blocksize ? &crie : &cria), crid); -+ if (error) { -+ dprintk("%s(%s) - newsession %d\n",__FUNCTION__,CIOCGSESSSTR,error); -+ goto bail; -+ } -+ -+ cse = csecreate(fcr, sid, &crie, &cria, &info); -+ if (cse == NULL) { -+ crypto_freesession(sid); -+ error = EINVAL; -+ dprintk("%s(%s) - csecreate failed\n", __FUNCTION__, CIOCGSESSSTR); -+ goto bail; -+ } -+ sop.ses = cse->ses; -+ -+ if (cmd == CIOCGSESSION2) { -+ /* return hardware/driver id */ -+ sop.crid = CRYPTO_SESID2HID(cse->sid); -+ } -+ -+ if (copy_to_user((void*)arg, &sop, (cmd == CIOCGSESSION) ? -+ sizeof(struct session_op) : sizeof(sop))) { -+ dprintk("%s(%s) - bad copy\n", __FUNCTION__, CIOCGSESSSTR); -+ error = EFAULT; -+ } -+bail: -+ if (error) { -+ dprintk("%s(%s) - bail %d\n", __FUNCTION__, CIOCGSESSSTR, error); -+ if (crie.cri_key) -+ kfree(crie.cri_key); -+ if (cria.cri_key) -+ kfree(cria.cri_key); -+ } -+ break; -+ case CIOCFSESSION: -+ dprintk("%s(CIOCFSESSION)\n", __FUNCTION__); -+ get_user(ses, (uint32_t*)arg); -+ cse = csefind(fcr, ses); -+ if (cse == NULL) { -+ error = EINVAL; -+ dprintk("%s(CIOCFSESSION) - Fail %d\n", __FUNCTION__, error); -+ break; -+ } -+ csedelete(fcr, cse); -+ error = csefree(cse); -+ break; -+ case CIOCCRYPT: -+ dprintk("%s(CIOCCRYPT)\n", __FUNCTION__); -+ if(copy_from_user(&cop, (void*)arg, sizeof(cop))) { -+ dprintk("%s(CIOCCRYPT) - bad copy\n", __FUNCTION__); -+ error = EFAULT; -+ goto bail; -+ } -+ cse = csefind(fcr, cop.ses); -+ if (cse == NULL) { -+ error = EINVAL; -+ dprintk("%s(CIOCCRYPT) - Fail %d\n", __FUNCTION__, error); -+ break; -+ } -+ error = cryptodev_op(cse, &cop); -+ if(copy_to_user((void*)arg, &cop, sizeof(cop))) { -+ dprintk("%s(CIOCCRYPT) - bad return copy\n", __FUNCTION__); -+ error = EFAULT; -+ goto bail; -+ } -+ break; -+ case CIOCKEY: -+ case CIOCKEY2: -+ dprintk("%s(CIOCKEY)\n", __FUNCTION__); -+ if (!crypto_userasymcrypto) -+ return (EPERM); /* XXX compat? */ -+ if(copy_from_user(&kop, (void*)arg, sizeof(kop))) { -+ dprintk("%s(CIOCKEY) - bad copy\n", __FUNCTION__); -+ error = EFAULT; -+ goto bail; -+ } -+ if (cmd == CIOCKEY) { -+ /* NB: crypto core enforces s/w driver use */ -+ kop.crk_crid = -+ CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE; -+ } -+ error = cryptodev_key(&kop); -+ if(copy_to_user((void*)arg, &kop, sizeof(kop))) { -+ dprintk("%s(CIOCGKEY) - bad return copy\n", __FUNCTION__); -+ error = EFAULT; -+ goto bail; -+ } -+ break; -+ case CIOCASYMFEAT: -+ dprintk("%s(CIOCASYMFEAT)\n", __FUNCTION__); -+ if (!crypto_userasymcrypto) { -+ /* -+ * NB: if user asym crypto operations are -+ * not permitted return "no algorithms" -+ * so well-behaved applications will just -+ * fallback to doing them in software. -+ */ -+ feat = 0; -+ } else -+ error = crypto_getfeat(&feat); -+ if (!error) { -+ error = copy_to_user((void*)arg, &feat, sizeof(feat)); -+ } -+ break; -+ case CIOCFINDDEV: -+ if (copy_from_user(&fop, (void*)arg, sizeof(fop))) { -+ dprintk("%s(CIOCFINDDEV) - bad copy\n", __FUNCTION__); -+ error = EFAULT; -+ goto bail; -+ } -+ error = cryptodev_find(&fop); -+ if (copy_to_user((void*)arg, &fop, sizeof(fop))) { -+ dprintk("%s(CIOCFINDDEV) - bad return copy\n", __FUNCTION__); -+ error = EFAULT; -+ goto bail; -+ } -+ break; -+ default: -+ dprintk("%s(unknown ioctl 0x%x)\n", __FUNCTION__, cmd); -+ error = EINVAL; -+ break; -+ } -+ return(-error); -+} -+ -+#ifdef HAVE_UNLOCKED_IOCTL -+static long -+cryptodev_unlocked_ioctl( -+ struct file *filp, -+ unsigned int cmd, -+ unsigned long arg) -+{ -+ return cryptodev_ioctl(NULL, filp, cmd, arg); -+} -+#endif -+ -+static int -+cryptodev_open(struct inode *inode, struct file *filp) -+{ -+ struct fcrypt *fcr; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (filp->private_data) { -+ printk("cryptodev: Private data already exists !\n"); -+ return(0); -+ } -+ -+ fcr = kmalloc(sizeof(*fcr), GFP_KERNEL); -+ if (!fcr) { -+ dprintk("%s() - malloc failed\n", __FUNCTION__); -+ return(-ENOMEM); -+ } -+ memset(fcr, 0, sizeof(*fcr)); -+ -+ INIT_LIST_HEAD(&fcr->csessions); -+ filp->private_data = fcr; -+ return(0); -+} -+ -+static int -+cryptodev_release(struct inode *inode, struct file *filp) -+{ -+ struct fcrypt *fcr = filp->private_data; -+ struct csession *cse, *tmp; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (!filp) { -+ printk("cryptodev: No private data on release\n"); -+ return(0); -+ } -+ -+ list_for_each_entry_safe(cse, tmp, &fcr->csessions, list) { -+ list_del(&cse->list); -+ (void)csefree(cse); -+ } -+ filp->private_data = NULL; -+ kfree(fcr); -+ return(0); -+} -+ -+static struct file_operations cryptodev_fops = { -+ .owner = THIS_MODULE, -+ .open = cryptodev_open, -+ .release = cryptodev_release, -+#ifdef HAVE_UNLOCKED_IOCTL -+ .unlocked_ioctl = cryptodev_unlocked_ioctl, -+#endif -+}; -+ -+static struct miscdevice cryptodev = { -+ .minor = CRYPTODEV_MINOR, -+ .name = "crypto", -+ .fops = &cryptodev_fops, -+}; -+ -+static int __init -+cryptodev_init(void) -+{ -+ int rc; -+ -+ dprintk("%s(%p)\n", __FUNCTION__, cryptodev_init); -+ rc = misc_register(&cryptodev); -+ if (rc) { -+ printk(KERN_ERR "cryptodev: registration of /dev/crypto failed\n"); -+ return(rc); -+ } -+ -+ return(0); -+} -+ -+static void __exit -+cryptodev_exit(void) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ misc_deregister(&cryptodev); -+} -+ -+module_init(cryptodev_init); -+module_exit(cryptodev_exit); -+ -+MODULE_LICENSE("BSD"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("Cryptodev (user interface to OCF)"); -diff -Nur linux-2.6.36.orig/crypto/ocf/cryptodev.h linux-2.6.36/crypto/ocf/cryptodev.h ---- linux-2.6.36.orig/crypto/ocf/cryptodev.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/cryptodev.h 2010-11-09 20:28:04.492495480 +0100 -@@ -0,0 +1,479 @@ -+/* $FreeBSD: src/sys/opencrypto/cryptodev.h,v 1.25 2007/05/09 19:37:02 gnn Exp $ */ -+/* $OpenBSD: cryptodev.h,v 1.31 2002/06/11 11:14:29 beck Exp $ */ -+ -+/*- -+ * Linux port done by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * The license and original author are listed below. -+ * -+ * The author of this code is Angelos D. Keromytis (angelos@cis.upenn.edu) -+ * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting -+ * -+ * This code was written by Angelos D. Keromytis in Athens, Greece, in -+ * February 2000. Network Security Technologies Inc. (NSTI) kindly -+ * supported the development of this code. -+ * -+ * Copyright (c) 2000 Angelos D. Keromytis -+ * -+ * Permission to use, copy, and modify this software with or without fee -+ * is hereby granted, provided that this entire notice is included in -+ * all source code copies of any software which is or includes a copy or -+ * modification of this software. -+ * -+ * THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR -+ * IMPLIED WARRANTY. IN PARTICULAR, NONE OF THE AUTHORS MAKES ANY -+ * REPRESENTATION OR WARRANTY OF ANY KIND CONCERNING THE -+ * MERCHANTABILITY OF THIS SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR -+ * PURPOSE. -+ * -+ * Copyright (c) 2001 Theo de Raadt -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored in part by the Defense Advanced Research Projects -+ * Agency (DARPA) and Air Force Research Laboratory, Air Force -+ * Materiel Command, USAF, under agreement number F30602-01-2-0537. -+ * -+ */ -+ -+#ifndef _CRYPTO_CRYPTO_H_ -+#define _CRYPTO_CRYPTO_H_ -+ -+/* Some initial values */ -+#define CRYPTO_DRIVERS_INITIAL 4 -+#define CRYPTO_SW_SESSIONS 32 -+ -+/* Hash values */ -+#define NULL_HASH_LEN 0 -+#define MD5_HASH_LEN 16 -+#define SHA1_HASH_LEN 20 -+#define RIPEMD160_HASH_LEN 20 -+#define SHA2_256_HASH_LEN 32 -+#define SHA2_384_HASH_LEN 48 -+#define SHA2_512_HASH_LEN 64 -+#define MD5_KPDK_HASH_LEN 16 -+#define SHA1_KPDK_HASH_LEN 20 -+/* Maximum hash algorithm result length */ -+#define HASH_MAX_LEN SHA2_512_HASH_LEN /* Keep this updated */ -+ -+/* HMAC values */ -+#define NULL_HMAC_BLOCK_LEN 1 -+#define MD5_HMAC_BLOCK_LEN 64 -+#define SHA1_HMAC_BLOCK_LEN 64 -+#define RIPEMD160_HMAC_BLOCK_LEN 64 -+#define SHA2_256_HMAC_BLOCK_LEN 64 -+#define SHA2_384_HMAC_BLOCK_LEN 128 -+#define SHA2_512_HMAC_BLOCK_LEN 128 -+/* Maximum HMAC block length */ -+#define HMAC_MAX_BLOCK_LEN SHA2_512_HMAC_BLOCK_LEN /* Keep this updated */ -+#define HMAC_IPAD_VAL 0x36 -+#define HMAC_OPAD_VAL 0x5C -+ -+/* Encryption algorithm block sizes */ -+#define NULL_BLOCK_LEN 1 -+#define DES_BLOCK_LEN 8 -+#define DES3_BLOCK_LEN 8 -+#define BLOWFISH_BLOCK_LEN 8 -+#define SKIPJACK_BLOCK_LEN 8 -+#define CAST128_BLOCK_LEN 8 -+#define RIJNDAEL128_BLOCK_LEN 16 -+#define AES_BLOCK_LEN RIJNDAEL128_BLOCK_LEN -+#define CAMELLIA_BLOCK_LEN 16 -+#define ARC4_BLOCK_LEN 1 -+#define EALG_MAX_BLOCK_LEN AES_BLOCK_LEN /* Keep this updated */ -+ -+/* Encryption algorithm min and max key sizes */ -+#define NULL_MIN_KEY_LEN 0 -+#define NULL_MAX_KEY_LEN 0 -+#define DES_MIN_KEY_LEN 8 -+#define DES_MAX_KEY_LEN 8 -+#define DES3_MIN_KEY_LEN 24 -+#define DES3_MAX_KEY_LEN 24 -+#define BLOWFISH_MIN_KEY_LEN 4 -+#define BLOWFISH_MAX_KEY_LEN 56 -+#define SKIPJACK_MIN_KEY_LEN 10 -+#define SKIPJACK_MAX_KEY_LEN 10 -+#define CAST128_MIN_KEY_LEN 5 -+#define CAST128_MAX_KEY_LEN 16 -+#define RIJNDAEL128_MIN_KEY_LEN 16 -+#define RIJNDAEL128_MAX_KEY_LEN 32 -+#define AES_MIN_KEY_LEN RIJNDAEL128_MIN_KEY_LEN -+#define AES_MAX_KEY_LEN RIJNDAEL128_MAX_KEY_LEN -+#define CAMELLIA_MIN_KEY_LEN 16 -+#define CAMELLIA_MAX_KEY_LEN 32 -+#define ARC4_MIN_KEY_LEN 1 -+#define ARC4_MAX_KEY_LEN 256 -+ -+/* Max size of data that can be processed */ -+#define CRYPTO_MAX_DATA_LEN 64*1024 - 1 -+ -+#define CRYPTO_ALGORITHM_MIN 1 -+#define CRYPTO_DES_CBC 1 -+#define CRYPTO_3DES_CBC 2 -+#define CRYPTO_BLF_CBC 3 -+#define CRYPTO_CAST_CBC 4 -+#define CRYPTO_SKIPJACK_CBC 5 -+#define CRYPTO_MD5_HMAC 6 -+#define CRYPTO_SHA1_HMAC 7 -+#define CRYPTO_RIPEMD160_HMAC 8 -+#define CRYPTO_MD5_KPDK 9 -+#define CRYPTO_SHA1_KPDK 10 -+#define CRYPTO_RIJNDAEL128_CBC 11 /* 128 bit blocksize */ -+#define CRYPTO_AES_CBC 11 /* 128 bit blocksize -- the same as above */ -+#define CRYPTO_ARC4 12 -+#define CRYPTO_MD5 13 -+#define CRYPTO_SHA1 14 -+#define CRYPTO_NULL_HMAC 15 -+#define CRYPTO_NULL_CBC 16 -+#define CRYPTO_DEFLATE_COMP 17 /* Deflate compression algorithm */ -+#define CRYPTO_SHA2_256_HMAC 18 -+#define CRYPTO_SHA2_384_HMAC 19 -+#define CRYPTO_SHA2_512_HMAC 20 -+#define CRYPTO_CAMELLIA_CBC 21 -+#define CRYPTO_SHA2_256 22 -+#define CRYPTO_SHA2_384 23 -+#define CRYPTO_SHA2_512 24 -+#define CRYPTO_RIPEMD160 25 -+#define CRYPTO_ALGORITHM_MAX 25 /* Keep updated - see below */ -+ -+/* Algorithm flags */ -+#define CRYPTO_ALG_FLAG_SUPPORTED 0x01 /* Algorithm is supported */ -+#define CRYPTO_ALG_FLAG_RNG_ENABLE 0x02 /* Has HW RNG for DH/DSA */ -+#define CRYPTO_ALG_FLAG_DSA_SHA 0x04 /* Can do SHA on msg */ -+ -+/* -+ * Crypto driver/device flags. They can set in the crid -+ * parameter when creating a session or submitting a key -+ * op to affect the device/driver assigned. If neither -+ * of these are specified then the crid is assumed to hold -+ * the driver id of an existing (and suitable) device that -+ * must be used to satisfy the request. -+ */ -+#define CRYPTO_FLAG_HARDWARE 0x01000000 /* hardware accelerated */ -+#define CRYPTO_FLAG_SOFTWARE 0x02000000 /* software implementation */ -+ -+/* NB: deprecated */ -+struct session_op { -+ u_int32_t cipher; /* ie. CRYPTO_DES_CBC */ -+ u_int32_t mac; /* ie. CRYPTO_MD5_HMAC */ -+ -+ u_int32_t keylen; /* cipher key */ -+ caddr_t key; -+ int mackeylen; /* mac key */ -+ caddr_t mackey; -+ -+ u_int32_t ses; /* returns: session # */ -+}; -+ -+struct session2_op { -+ u_int32_t cipher; /* ie. CRYPTO_DES_CBC */ -+ u_int32_t mac; /* ie. CRYPTO_MD5_HMAC */ -+ -+ u_int32_t keylen; /* cipher key */ -+ caddr_t key; -+ int mackeylen; /* mac key */ -+ caddr_t mackey; -+ -+ u_int32_t ses; /* returns: session # */ -+ int crid; /* driver id + flags (rw) */ -+ int pad[4]; /* for future expansion */ -+}; -+ -+struct crypt_op { -+ u_int32_t ses; -+ u_int16_t op; /* i.e. COP_ENCRYPT */ -+#define COP_NONE 0 -+#define COP_ENCRYPT 1 -+#define COP_DECRYPT 2 -+ u_int16_t flags; -+#define COP_F_BATCH 0x0008 /* Batch op if possible */ -+ u_int len; -+ caddr_t src, dst; /* become iov[] inside kernel */ -+ caddr_t mac; /* must be big enough for chosen MAC */ -+ caddr_t iv; -+}; -+ -+/* -+ * Parameters for looking up a crypto driver/device by -+ * device name or by id. The latter are returned for -+ * created sessions (crid) and completed key operations. -+ */ -+struct crypt_find_op { -+ int crid; /* driver id + flags */ -+ char name[32]; /* device/driver name */ -+}; -+ -+/* bignum parameter, in packed bytes, ... */ -+struct crparam { -+ caddr_t crp_p; -+ u_int crp_nbits; -+}; -+ -+#define CRK_MAXPARAM 8 -+ -+struct crypt_kop { -+ u_int crk_op; /* ie. CRK_MOD_EXP or other */ -+ u_int crk_status; /* return status */ -+ u_short crk_iparams; /* # of input parameters */ -+ u_short crk_oparams; /* # of output parameters */ -+ u_int crk_crid; /* NB: only used by CIOCKEY2 (rw) */ -+ struct crparam crk_param[CRK_MAXPARAM]; -+}; -+#define CRK_ALGORITM_MIN 0 -+#define CRK_MOD_EXP 0 -+#define CRK_MOD_EXP_CRT 1 -+#define CRK_DSA_SIGN 2 -+#define CRK_DSA_VERIFY 3 -+#define CRK_DH_COMPUTE_KEY 4 -+#define CRK_ALGORITHM_MAX 4 /* Keep updated - see below */ -+ -+#define CRF_MOD_EXP (1 << CRK_MOD_EXP) -+#define CRF_MOD_EXP_CRT (1 << CRK_MOD_EXP_CRT) -+#define CRF_DSA_SIGN (1 << CRK_DSA_SIGN) -+#define CRF_DSA_VERIFY (1 << CRK_DSA_VERIFY) -+#define CRF_DH_COMPUTE_KEY (1 << CRK_DH_COMPUTE_KEY) -+ -+/* -+ * done against open of /dev/crypto, to get a cloned descriptor. -+ * Please use F_SETFD against the cloned descriptor. -+ */ -+#define CRIOGET _IOWR('c', 100, u_int32_t) -+#define CRIOASYMFEAT CIOCASYMFEAT -+#define CRIOFINDDEV CIOCFINDDEV -+ -+/* the following are done against the cloned descriptor */ -+#define CIOCGSESSION _IOWR('c', 101, struct session_op) -+#define CIOCFSESSION _IOW('c', 102, u_int32_t) -+#define CIOCCRYPT _IOWR('c', 103, struct crypt_op) -+#define CIOCKEY _IOWR('c', 104, struct crypt_kop) -+#define CIOCASYMFEAT _IOR('c', 105, u_int32_t) -+#define CIOCGSESSION2 _IOWR('c', 106, struct session2_op) -+#define CIOCKEY2 _IOWR('c', 107, struct crypt_kop) -+#define CIOCFINDDEV _IOWR('c', 108, struct crypt_find_op) -+ -+struct cryptotstat { -+ struct timespec acc; /* total accumulated time */ -+ struct timespec min; /* min time */ -+ struct timespec max; /* max time */ -+ u_int32_t count; /* number of observations */ -+}; -+ -+struct cryptostats { -+ u_int32_t cs_ops; /* symmetric crypto ops submitted */ -+ u_int32_t cs_errs; /* symmetric crypto ops that failed */ -+ u_int32_t cs_kops; /* asymetric/key ops submitted */ -+ u_int32_t cs_kerrs; /* asymetric/key ops that failed */ -+ u_int32_t cs_intrs; /* crypto swi thread activations */ -+ u_int32_t cs_rets; /* crypto return thread activations */ -+ u_int32_t cs_blocks; /* symmetric op driver block */ -+ u_int32_t cs_kblocks; /* symmetric op driver block */ -+ /* -+ * When CRYPTO_TIMING is defined at compile time and the -+ * sysctl debug.crypto is set to 1, the crypto system will -+ * accumulate statistics about how long it takes to process -+ * crypto requests at various points during processing. -+ */ -+ struct cryptotstat cs_invoke; /* crypto_dipsatch -> crypto_invoke */ -+ struct cryptotstat cs_done; /* crypto_invoke -> crypto_done */ -+ struct cryptotstat cs_cb; /* crypto_done -> callback */ -+ struct cryptotstat cs_finis; /* callback -> callback return */ -+ -+ u_int32_t cs_drops; /* crypto ops dropped due to congestion */ -+}; -+ -+#ifdef __KERNEL__ -+ -+/* Standard initialization structure beginning */ -+struct cryptoini { -+ int cri_alg; /* Algorithm to use */ -+ int cri_klen; /* Key length, in bits */ -+ int cri_mlen; /* Number of bytes we want from the -+ entire hash. 0 means all. */ -+ caddr_t cri_key; /* key to use */ -+ u_int8_t cri_iv[EALG_MAX_BLOCK_LEN]; /* IV to use */ -+ struct cryptoini *cri_next; -+}; -+ -+/* Describe boundaries of a single crypto operation */ -+struct cryptodesc { -+ int crd_skip; /* How many bytes to ignore from start */ -+ int crd_len; /* How many bytes to process */ -+ int crd_inject; /* Where to inject results, if applicable */ -+ int crd_flags; -+ -+#define CRD_F_ENCRYPT 0x01 /* Set when doing encryption */ -+#define CRD_F_IV_PRESENT 0x02 /* When encrypting, IV is already in -+ place, so don't copy. */ -+#define CRD_F_IV_EXPLICIT 0x04 /* IV explicitly provided */ -+#define CRD_F_DSA_SHA_NEEDED 0x08 /* Compute SHA-1 of buffer for DSA */ -+#define CRD_F_KEY_EXPLICIT 0x10 /* Key explicitly provided */ -+#define CRD_F_COMP 0x0f /* Set when doing compression */ -+ -+ struct cryptoini CRD_INI; /* Initialization/context data */ -+#define crd_iv CRD_INI.cri_iv -+#define crd_key CRD_INI.cri_key -+#define crd_alg CRD_INI.cri_alg -+#define crd_klen CRD_INI.cri_klen -+#define crd_mlen CRD_INI.cri_mlen -+ -+ struct cryptodesc *crd_next; -+}; -+ -+/* Structure describing complete operation */ -+struct cryptop { -+ struct list_head crp_next; -+ wait_queue_head_t crp_waitq; -+ -+ u_int64_t crp_sid; /* Session ID */ -+ int crp_ilen; /* Input data total length */ -+ int crp_olen; /* Result total length */ -+ -+ int crp_etype; /* -+ * Error type (zero means no error). -+ * All error codes except EAGAIN -+ * indicate possible data corruption (as in, -+ * the data have been touched). On all -+ * errors, the crp_sid may have changed -+ * (reset to a new one), so the caller -+ * should always check and use the new -+ * value on future requests. -+ */ -+ int crp_flags; -+ -+#define CRYPTO_F_SKBUF 0x0001 /* Input/output are skbuf chains */ -+#define CRYPTO_F_IOV 0x0002 /* Input/output are uio */ -+#define CRYPTO_F_REL 0x0004 /* Must return data in same place */ -+#define CRYPTO_F_BATCH 0x0008 /* Batch op if possible */ -+#define CRYPTO_F_CBIMM 0x0010 /* Do callback immediately */ -+#define CRYPTO_F_DONE 0x0020 /* Operation completed */ -+#define CRYPTO_F_CBIFSYNC 0x0040 /* Do CBIMM if op is synchronous */ -+ -+ caddr_t crp_buf; /* Data to be processed */ -+ caddr_t crp_opaque; /* Opaque pointer, passed along */ -+ struct cryptodesc *crp_desc; /* Linked list of processing descriptors */ -+ -+ int (*crp_callback)(struct cryptop *); /* Callback function */ -+}; -+ -+#define CRYPTO_BUF_CONTIG 0x0 -+#define CRYPTO_BUF_IOV 0x1 -+#define CRYPTO_BUF_SKBUF 0x2 -+ -+#define CRYPTO_OP_DECRYPT 0x0 -+#define CRYPTO_OP_ENCRYPT 0x1 -+ -+/* -+ * Hints passed to process methods. -+ */ -+#define CRYPTO_HINT_MORE 0x1 /* more ops coming shortly */ -+ -+struct cryptkop { -+ struct list_head krp_next; -+ wait_queue_head_t krp_waitq; -+ -+ int krp_flags; -+#define CRYPTO_KF_DONE 0x0001 /* Operation completed */ -+#define CRYPTO_KF_CBIMM 0x0002 /* Do callback immediately */ -+ -+ u_int krp_op; /* ie. CRK_MOD_EXP or other */ -+ u_int krp_status; /* return status */ -+ u_short krp_iparams; /* # of input parameters */ -+ u_short krp_oparams; /* # of output parameters */ -+ u_int krp_crid; /* desired device, etc. */ -+ u_int32_t krp_hid; -+ struct crparam krp_param[CRK_MAXPARAM]; /* kvm */ -+ int (*krp_callback)(struct cryptkop *); -+}; -+ -+#include -+ -+/* -+ * Session ids are 64 bits. The lower 32 bits contain a "local id" which -+ * is a driver-private session identifier. The upper 32 bits contain a -+ * "hardware id" used by the core crypto code to identify the driver and -+ * a copy of the driver's capabilities that can be used by client code to -+ * optimize operation. -+ */ -+#define CRYPTO_SESID2HID(_sid) (((_sid) >> 32) & 0x00ffffff) -+#define CRYPTO_SESID2CAPS(_sid) (((_sid) >> 32) & 0xff000000) -+#define CRYPTO_SESID2LID(_sid) (((u_int32_t) (_sid)) & 0xffffffff) -+ -+extern int crypto_newsession(u_int64_t *sid, struct cryptoini *cri, int hard); -+extern int crypto_freesession(u_int64_t sid); -+#define CRYPTOCAP_F_HARDWARE CRYPTO_FLAG_HARDWARE -+#define CRYPTOCAP_F_SOFTWARE CRYPTO_FLAG_SOFTWARE -+#define CRYPTOCAP_F_SYNC 0x04000000 /* operates synchronously */ -+extern int32_t crypto_get_driverid(device_t dev, int flags); -+extern int crypto_find_driver(const char *); -+extern device_t crypto_find_device_byhid(int hid); -+extern int crypto_getcaps(int hid); -+extern int crypto_register(u_int32_t driverid, int alg, u_int16_t maxoplen, -+ u_int32_t flags); -+extern int crypto_kregister(u_int32_t, int, u_int32_t); -+extern int crypto_unregister(u_int32_t driverid, int alg); -+extern int crypto_unregister_all(u_int32_t driverid); -+extern int crypto_dispatch(struct cryptop *crp); -+extern int crypto_kdispatch(struct cryptkop *); -+#define CRYPTO_SYMQ 0x1 -+#define CRYPTO_ASYMQ 0x2 -+extern int crypto_unblock(u_int32_t, int); -+extern void crypto_done(struct cryptop *crp); -+extern void crypto_kdone(struct cryptkop *); -+extern int crypto_getfeat(int *); -+ -+extern void crypto_freereq(struct cryptop *crp); -+extern struct cryptop *crypto_getreq(int num); -+ -+extern int crypto_usercrypto; /* userland may do crypto requests */ -+extern int crypto_userasymcrypto; /* userland may do asym crypto reqs */ -+extern int crypto_devallowsoft; /* only use hardware crypto */ -+ -+/* -+ * random number support, crypto_unregister_all will unregister -+ */ -+extern int crypto_rregister(u_int32_t driverid, -+ int (*read_random)(void *arg, u_int32_t *buf, int len), void *arg); -+extern int crypto_runregister_all(u_int32_t driverid); -+ -+/* -+ * Crypto-related utility routines used mainly by drivers. -+ * -+ * XXX these don't really belong here; but for now they're -+ * kept apart from the rest of the system. -+ */ -+struct uio; -+extern void cuio_copydata(struct uio* uio, int off, int len, caddr_t cp); -+extern void cuio_copyback(struct uio* uio, int off, int len, caddr_t cp); -+extern struct iovec *cuio_getptr(struct uio *uio, int loc, int *off); -+ -+extern void crypto_copyback(int flags, caddr_t buf, int off, int size, -+ caddr_t in); -+extern void crypto_copydata(int flags, caddr_t buf, int off, int size, -+ caddr_t out); -+extern int crypto_apply(int flags, caddr_t buf, int off, int len, -+ int (*f)(void *, void *, u_int), void *arg); -+ -+#endif /* __KERNEL__ */ -+#endif /* _CRYPTO_CRYPTO_H_ */ -diff -Nur linux-2.6.36.orig/crypto/ocf/cryptosoft.c linux-2.6.36/crypto/ocf/cryptosoft.c ---- linux-2.6.36.orig/crypto/ocf/cryptosoft.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/cryptosoft.c 2010-11-09 20:28:04.532495450 +0100 -@@ -0,0 +1,1210 @@ -+/* -+ * An OCF module that uses the linux kernel cryptoapi, based on the -+ * original cryptosoft for BSD by Angelos D. Keromytis (angelos@cis.upenn.edu) -+ * but is mostly unrecognisable, -+ * -+ * Written by David McCullough -+ * Copyright (C) 2004-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * ALTERNATIVELY, provided that this notice is retained in full, this product -+ * may be distributed under the terms of the GNU General Public License (GPL), -+ * in which case the provisions of the GPL apply INSTEAD OF those given above. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ * --------------------------------------------------------------------------- -+ */ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,10) -+#include -+#endif -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29) -+#include -+#endif -+ -+#include -+#include -+ -+struct { -+ softc_device_decl sc_dev; -+} swcr_softc; -+ -+#define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK) -+ -+#define SW_TYPE_CIPHER 0x01 -+#define SW_TYPE_HMAC 0x02 -+#define SW_TYPE_HASH 0x04 -+#define SW_TYPE_COMP 0x08 -+#define SW_TYPE_BLKCIPHER 0x10 -+#define SW_TYPE_ALG_MASK 0x1f -+ -+#define SW_TYPE_ASYNC 0x8000 -+ -+/* We change some of the above if we have an async interface */ -+ -+#define SW_TYPE_ALG_AMASK (SW_TYPE_ALG_MASK | SW_TYPE_ASYNC) -+ -+#define SW_TYPE_ABLKCIPHER (SW_TYPE_BLKCIPHER | SW_TYPE_ASYNC) -+#define SW_TYPE_AHASH (SW_TYPE_HASH | SW_TYPE_ASYNC) -+#define SW_TYPE_AHMAC (SW_TYPE_HMAC | SW_TYPE_ASYNC) -+ -+#define SCATTERLIST_MAX 16 -+ -+struct swcr_data { -+ int sw_type; -+ int sw_alg; -+ struct crypto_tfm *sw_tfm; -+ union { -+ struct { -+ char *sw_key; -+ int sw_klen; -+ int sw_mlen; -+ } hmac; -+ void *sw_comp_buf; -+ } u; -+ struct swcr_data *sw_next; -+}; -+ -+struct swcr_req { -+ struct swcr_data *sw_head; -+ struct swcr_data *sw; -+ struct cryptop *crp; -+ struct cryptodesc *crd; -+ struct scatterlist sg[SCATTERLIST_MAX]; -+ unsigned char iv[EALG_MAX_BLOCK_LEN]; -+ char result[HASH_MAX_LEN]; -+ void *crypto_req; -+}; -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) -+static kmem_cache_t *swcr_req_cache; -+#else -+static struct kmem_cache *swcr_req_cache; -+#endif -+ -+#ifndef CRYPTO_TFM_MODE_CBC -+/* -+ * As of linux-2.6.21 this is no longer defined, and presumably no longer -+ * needed to be passed into the crypto core code. -+ */ -+#define CRYPTO_TFM_MODE_CBC 0 -+#define CRYPTO_TFM_MODE_ECB 0 -+#endif -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) -+ /* -+ * Linux 2.6.19 introduced a new Crypto API, setup macro's to convert new -+ * API into old API. -+ */ -+ -+ /* Symmetric/Block Cipher */ -+ struct blkcipher_desc -+ { -+ struct crypto_tfm *tfm; -+ void *info; -+ }; -+ #define ecb(X) #X , CRYPTO_TFM_MODE_ECB -+ #define cbc(X) #X , CRYPTO_TFM_MODE_CBC -+ #define crypto_has_blkcipher(X, Y, Z) crypto_alg_available(X, 0) -+ #define crypto_blkcipher_cast(X) X -+ #define crypto_blkcipher_tfm(X) X -+ #define crypto_alloc_blkcipher(X, Y, Z) crypto_alloc_tfm(X, mode) -+ #define crypto_blkcipher_ivsize(X) crypto_tfm_alg_ivsize(X) -+ #define crypto_blkcipher_blocksize(X) crypto_tfm_alg_blocksize(X) -+ #define crypto_blkcipher_setkey(X, Y, Z) crypto_cipher_setkey(X, Y, Z) -+ #define crypto_blkcipher_encrypt_iv(W, X, Y, Z) \ -+ crypto_cipher_encrypt_iv((W)->tfm, X, Y, Z, (u8 *)((W)->info)) -+ #define crypto_blkcipher_decrypt_iv(W, X, Y, Z) \ -+ crypto_cipher_decrypt_iv((W)->tfm, X, Y, Z, (u8 *)((W)->info)) -+ #define crypto_blkcipher_set_flags(x, y) /* nop */ -+ -+ /* Hash/HMAC/Digest */ -+ struct hash_desc -+ { -+ struct crypto_tfm *tfm; -+ }; -+ #define hmac(X) #X , 0 -+ #define crypto_has_hash(X, Y, Z) crypto_alg_available(X, 0) -+ #define crypto_hash_cast(X) X -+ #define crypto_hash_tfm(X) X -+ #define crypto_alloc_hash(X, Y, Z) crypto_alloc_tfm(X, mode) -+ #define crypto_hash_digestsize(X) crypto_tfm_alg_digestsize(X) -+ #define crypto_hash_digest(W, X, Y, Z) \ -+ crypto_digest_digest((W)->tfm, X, sg_num, Z) -+ -+ /* Asymmetric Cipher */ -+ #define crypto_has_cipher(X, Y, Z) crypto_alg_available(X, 0) -+ -+ /* Compression */ -+ #define crypto_has_comp(X, Y, Z) crypto_alg_available(X, 0) -+ #define crypto_comp_tfm(X) X -+ #define crypto_comp_cast(X) X -+ #define crypto_alloc_comp(X, Y, Z) crypto_alloc_tfm(X, mode) -+ #define plain(X) #X , 0 -+#else -+ #define ecb(X) "ecb(" #X ")" , 0 -+ #define cbc(X) "cbc(" #X ")" , 0 -+ #define hmac(X) "hmac(" #X ")" , 0 -+ #define plain(X) #X , 0 -+#endif /* if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) */ -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22) -+/* no ablkcipher in older kernels */ -+#define crypto_alloc_ablkcipher(a,b,c) (NULL) -+#define crypto_ablkcipher_tfm(x) ((struct crypto_tfm *)(x)) -+#define crypto_ablkcipher_set_flags(a, b) /* nop */ -+#define crypto_ablkcipher_setkey(x, y, z) (-EINVAL) -+#define crypto_has_ablkcipher(a,b,c) (0) -+#else -+#define HAVE_ABLKCIPHER -+#endif -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,32) -+/* no ahash in older kernels */ -+#define crypto_ahash_tfm(x) ((struct crypto_tfm *)(x)) -+#define crypto_alloc_ahash(a,b,c) (NULL) -+#define crypto_ahash_digestsize(x) 0 -+#else -+#define HAVE_AHASH -+#endif -+ -+struct crypto_details { -+ char *alg_name; -+ int mode; -+ int sw_type; -+}; -+ -+static struct crypto_details crypto_details[] = { -+ [CRYPTO_DES_CBC] = { cbc(des), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_3DES_CBC] = { cbc(des3_ede), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_BLF_CBC] = { cbc(blowfish), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_CAST_CBC] = { cbc(cast5), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_SKIPJACK_CBC] = { cbc(skipjack), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_MD5_HMAC] = { hmac(md5), SW_TYPE_HMAC, }, -+ [CRYPTO_SHA1_HMAC] = { hmac(sha1), SW_TYPE_HMAC, }, -+ [CRYPTO_RIPEMD160_HMAC] = { hmac(ripemd160), SW_TYPE_HMAC, }, -+ [CRYPTO_MD5_KPDK] = { plain(md5-kpdk), SW_TYPE_HASH, }, -+ [CRYPTO_SHA1_KPDK] = { plain(sha1-kpdk), SW_TYPE_HASH, }, -+ [CRYPTO_AES_CBC] = { cbc(aes), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_ARC4] = { ecb(arc4), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_MD5] = { plain(md5), SW_TYPE_HASH, }, -+ [CRYPTO_SHA1] = { plain(sha1), SW_TYPE_HASH, }, -+ [CRYPTO_NULL_HMAC] = { hmac(digest_null), SW_TYPE_HMAC, }, -+ [CRYPTO_NULL_CBC] = { cbc(cipher_null), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_DEFLATE_COMP] = { plain(deflate), SW_TYPE_COMP, }, -+ [CRYPTO_SHA2_256_HMAC] = { hmac(sha256), SW_TYPE_HMAC, }, -+ [CRYPTO_SHA2_384_HMAC] = { hmac(sha384), SW_TYPE_HMAC, }, -+ [CRYPTO_SHA2_512_HMAC] = { hmac(sha512), SW_TYPE_HMAC, }, -+ [CRYPTO_CAMELLIA_CBC] = { cbc(camellia), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_SHA2_256] = { plain(sha256), SW_TYPE_HASH, }, -+ [CRYPTO_SHA2_384] = { plain(sha384), SW_TYPE_HASH, }, -+ [CRYPTO_SHA2_512] = { plain(sha512), SW_TYPE_HASH, }, -+ [CRYPTO_RIPEMD160] = { plain(ripemd160), SW_TYPE_HASH, }, -+}; -+ -+int32_t swcr_id = -1; -+module_param(swcr_id, int, 0444); -+MODULE_PARM_DESC(swcr_id, "Read-Only OCF ID for cryptosoft driver"); -+ -+int swcr_fail_if_compression_grows = 1; -+module_param(swcr_fail_if_compression_grows, int, 0644); -+MODULE_PARM_DESC(swcr_fail_if_compression_grows, -+ "Treat compression that results in more data as a failure"); -+ -+int swcr_no_ahash = 0; -+module_param(swcr_no_ahash, int, 0644); -+MODULE_PARM_DESC(swcr_no_ahash, -+ "Do not use async hash/hmac even if available"); -+ -+int swcr_no_ablk = 0; -+module_param(swcr_no_ablk, int, 0644); -+MODULE_PARM_DESC(swcr_no_ablk, -+ "Do not use async blk ciphers even if available"); -+ -+static struct swcr_data **swcr_sessions = NULL; -+static u_int32_t swcr_sesnum = 0; -+ -+static int swcr_process(device_t, struct cryptop *, int); -+static int swcr_newsession(device_t, u_int32_t *, struct cryptoini *); -+static int swcr_freesession(device_t, u_int64_t); -+ -+static device_method_t swcr_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, swcr_newsession), -+ DEVMETHOD(cryptodev_freesession,swcr_freesession), -+ DEVMETHOD(cryptodev_process, swcr_process), -+}; -+ -+#define debug swcr_debug -+int swcr_debug = 0; -+module_param(swcr_debug, int, 0644); -+MODULE_PARM_DESC(swcr_debug, "Enable debug"); -+ -+static void swcr_process_req(struct swcr_req *req); -+ -+/* -+ * Generate a new software session. -+ */ -+static int -+swcr_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) -+{ -+ struct swcr_data **swd; -+ u_int32_t i; -+ int error; -+ char *algo; -+ int mode; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid == NULL || cri == NULL) { -+ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ if (swcr_sessions) { -+ for (i = 1; i < swcr_sesnum; i++) -+ if (swcr_sessions[i] == NULL) -+ break; -+ } else -+ i = 1; /* NB: to silence compiler warning */ -+ -+ if (swcr_sessions == NULL || i == swcr_sesnum) { -+ if (swcr_sessions == NULL) { -+ i = 1; /* We leave swcr_sessions[0] empty */ -+ swcr_sesnum = CRYPTO_SW_SESSIONS; -+ } else -+ swcr_sesnum *= 2; -+ -+ swd = kmalloc(swcr_sesnum * sizeof(struct swcr_data *), SLAB_ATOMIC); -+ if (swd == NULL) { -+ /* Reset session number */ -+ if (swcr_sesnum == CRYPTO_SW_SESSIONS) -+ swcr_sesnum = 0; -+ else -+ swcr_sesnum /= 2; -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memset(swd, 0, swcr_sesnum * sizeof(struct swcr_data *)); -+ -+ /* Copy existing sessions */ -+ if (swcr_sessions) { -+ memcpy(swd, swcr_sessions, -+ (swcr_sesnum / 2) * sizeof(struct swcr_data *)); -+ kfree(swcr_sessions); -+ } -+ -+ swcr_sessions = swd; -+ } -+ -+ swd = &swcr_sessions[i]; -+ *sid = i; -+ -+ while (cri) { -+ *swd = (struct swcr_data *) kmalloc(sizeof(struct swcr_data), -+ SLAB_ATOMIC); -+ if (*swd == NULL) { -+ swcr_freesession(NULL, i); -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memset(*swd, 0, sizeof(struct swcr_data)); -+ -+ if (cri->cri_alg < 0 || -+ cri->cri_alg>=sizeof(crypto_details)/sizeof(crypto_details[0])){ -+ printk("cryptosoft: Unknown algorithm 0x%x\n", cri->cri_alg); -+ swcr_freesession(NULL, i); -+ return EINVAL; -+ } -+ -+ algo = crypto_details[cri->cri_alg].alg_name; -+ if (!algo || !*algo) { -+ printk("cryptosoft: Unsupported algorithm 0x%x\n", cri->cri_alg); -+ swcr_freesession(NULL, i); -+ return EINVAL; -+ } -+ -+ mode = crypto_details[cri->cri_alg].mode; -+ (*swd)->sw_type = crypto_details[cri->cri_alg].sw_type; -+ (*swd)->sw_alg = cri->cri_alg; -+ -+ /* Algorithm specific configuration */ -+ switch (cri->cri_alg) { -+ case CRYPTO_NULL_CBC: -+ cri->cri_klen = 0; /* make it work with crypto API */ -+ break; -+ default: -+ break; -+ } -+ -+ if ((*swd)->sw_type & SW_TYPE_BLKCIPHER) { -+ dprintk("%s crypto_alloc_*blkcipher(%s, 0x%x)\n", __FUNCTION__, -+ algo, mode); -+ -+ /* try async first */ -+ (*swd)->sw_tfm = swcr_no_ablk ? NULL : -+ crypto_ablkcipher_tfm(crypto_alloc_ablkcipher(algo, 0, 0)); -+ if ((*swd)->sw_tfm) { -+ dprintk("%s %s cipher is async\n", __FUNCTION__, algo); -+ (*swd)->sw_type |= SW_TYPE_ASYNC; -+ } else { -+ dprintk("%s %s cipher is sync\n", __FUNCTION__, algo); -+ (*swd)->sw_tfm = crypto_blkcipher_tfm( -+ crypto_alloc_blkcipher(algo, 0, CRYPTO_ALG_ASYNC)); -+ } -+ if (!(*swd)->sw_tfm) { -+ dprintk("cryptosoft: crypto_alloc_blkcipher failed(%s, 0x%x)\n", -+ algo,mode); -+ swcr_freesession(NULL, i); -+ return EINVAL; -+ } -+ -+ if (debug) { -+ dprintk("%s key:cri->cri_klen=%d,(cri->cri_klen + 7)/8=%d", -+ __FUNCTION__, cri->cri_klen, (cri->cri_klen + 7) / 8); -+ for (i = 0; i < (cri->cri_klen + 7) / 8; i++) -+ dprintk("%s0x%x", (i % 8) ? " " : "\n ", -+ cri->cri_key[i] & 0xff); -+ dprintk("\n"); -+ } -+ if ((*swd)->sw_type & SW_TYPE_ASYNC) { -+ /* OCF doesn't enforce keys */ -+ crypto_ablkcipher_set_flags( -+ __crypto_ablkcipher_cast((*swd)->sw_tfm), -+ CRYPTO_TFM_REQ_WEAK_KEY); -+ error = crypto_ablkcipher_setkey( -+ __crypto_ablkcipher_cast((*swd)->sw_tfm), -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ } else { -+ /* OCF doesn't enforce keys */ -+ crypto_blkcipher_set_flags( -+ crypto_blkcipher_cast((*swd)->sw_tfm), -+ CRYPTO_TFM_REQ_WEAK_KEY); -+ error = crypto_blkcipher_setkey( -+ crypto_blkcipher_cast((*swd)->sw_tfm), -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ } -+ if (error) { -+ printk("cryptosoft: setkey failed %d (crt_flags=0x%x)\n", error, -+ (*swd)->sw_tfm->crt_flags); -+ swcr_freesession(NULL, i); -+ return error; -+ } -+ } else if ((*swd)->sw_type & (SW_TYPE_HMAC | SW_TYPE_HASH)) { -+ dprintk("%s crypto_alloc_*hash(%s, 0x%x)\n", __FUNCTION__, -+ algo, mode); -+ -+ /* try async first */ -+ (*swd)->sw_tfm = swcr_no_ahash ? NULL : -+ crypto_ahash_tfm(crypto_alloc_ahash(algo, 0, 0)); -+ if ((*swd)->sw_tfm) { -+ dprintk("%s %s hash is async\n", __FUNCTION__, algo); -+ (*swd)->sw_type |= SW_TYPE_ASYNC; -+ } else { -+ dprintk("%s %s hash is sync\n", __FUNCTION__, algo); -+ (*swd)->sw_tfm = crypto_hash_tfm( -+ crypto_alloc_hash(algo, 0, CRYPTO_ALG_ASYNC)); -+ } -+ -+ if (!(*swd)->sw_tfm) { -+ dprintk("cryptosoft: crypto_alloc_hash failed(%s,0x%x)\n", -+ algo, mode); -+ swcr_freesession(NULL, i); -+ return EINVAL; -+ } -+ -+ (*swd)->u.hmac.sw_klen = (cri->cri_klen + 7) / 8; -+ (*swd)->u.hmac.sw_key = (char *)kmalloc((*swd)->u.hmac.sw_klen, -+ SLAB_ATOMIC); -+ if ((*swd)->u.hmac.sw_key == NULL) { -+ swcr_freesession(NULL, i); -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memcpy((*swd)->u.hmac.sw_key, cri->cri_key, (*swd)->u.hmac.sw_klen); -+ if (cri->cri_mlen) { -+ (*swd)->u.hmac.sw_mlen = cri->cri_mlen; -+ } else if ((*swd)->sw_type & SW_TYPE_ASYNC) { -+ (*swd)->u.hmac.sw_mlen = crypto_ahash_digestsize( -+ __crypto_ahash_cast((*swd)->sw_tfm)); -+ } else { -+ (*swd)->u.hmac.sw_mlen = crypto_hash_digestsize( -+ crypto_hash_cast((*swd)->sw_tfm)); -+ } -+ } else if ((*swd)->sw_type & SW_TYPE_COMP) { -+ (*swd)->sw_tfm = crypto_comp_tfm( -+ crypto_alloc_comp(algo, 0, CRYPTO_ALG_ASYNC)); -+ if (!(*swd)->sw_tfm) { -+ dprintk("cryptosoft: crypto_alloc_comp failed(%s,0x%x)\n", -+ algo, mode); -+ swcr_freesession(NULL, i); -+ return EINVAL; -+ } -+ (*swd)->u.sw_comp_buf = kmalloc(CRYPTO_MAX_DATA_LEN, SLAB_ATOMIC); -+ if ((*swd)->u.sw_comp_buf == NULL) { -+ swcr_freesession(NULL, i); -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ } else { -+ printk("cryptosoft: Unhandled sw_type %d\n", (*swd)->sw_type); -+ swcr_freesession(NULL, i); -+ return EINVAL; -+ } -+ -+ cri = cri->cri_next; -+ swd = &((*swd)->sw_next); -+ } -+ return 0; -+} -+ -+/* -+ * Free a session. -+ */ -+static int -+swcr_freesession(device_t dev, u_int64_t tid) -+{ -+ struct swcr_data *swd; -+ u_int32_t sid = CRYPTO_SESID2LID(tid); -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid > swcr_sesnum || swcr_sessions == NULL || -+ swcr_sessions[sid] == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return(EINVAL); -+ } -+ -+ /* Silently accept and return */ -+ if (sid == 0) -+ return(0); -+ -+ while ((swd = swcr_sessions[sid]) != NULL) { -+ swcr_sessions[sid] = swd->sw_next; -+ if (swd->sw_tfm) { -+ switch (swd->sw_type & SW_TYPE_ALG_AMASK) { -+#ifdef HAVE_AHASH -+ case SW_TYPE_AHMAC: -+ case SW_TYPE_AHASH: -+ crypto_free_ahash(__crypto_ahash_cast(swd->sw_tfm)); -+ break; -+#endif -+#ifdef HAVE_ABLKCIPHER -+ case SW_TYPE_ABLKCIPHER: -+ crypto_free_ablkcipher(__crypto_ablkcipher_cast(swd->sw_tfm)); -+ break; -+#endif -+ case SW_TYPE_BLKCIPHER: -+ crypto_free_blkcipher(crypto_blkcipher_cast(swd->sw_tfm)); -+ break; -+ case SW_TYPE_HMAC: -+ case SW_TYPE_HASH: -+ crypto_free_hash(crypto_hash_cast(swd->sw_tfm)); -+ break; -+ case SW_TYPE_COMP: -+ crypto_free_comp(crypto_comp_cast(swd->sw_tfm)); -+ default: -+ crypto_free_tfm(swd->sw_tfm); -+ break; -+ } -+ swd->sw_tfm = NULL; -+ } -+ if (swd->sw_type & SW_TYPE_COMP) { -+ if (swd->u.sw_comp_buf) -+ kfree(swd->u.sw_comp_buf); -+ } else { -+ if (swd->u.hmac.sw_key) -+ kfree(swd->u.hmac.sw_key); -+ } -+ kfree(swd); -+ } -+ return 0; -+} -+ -+#if defined(HAVE_ABLKCIPHER) || defined(HAVE_AHASH) -+/* older kernels had no async interface */ -+ -+static void swcr_process_callback(struct crypto_async_request *creq, int err) -+{ -+ struct swcr_req *req = creq->data; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (err) { -+ if (err == -EINPROGRESS) -+ return; -+ dprintk("%s() fail %d\n", __FUNCTION__, -err); -+ req->crp->crp_etype = -err; -+ goto done; -+ } -+ -+ switch (req->sw->sw_type & SW_TYPE_ALG_AMASK) { -+ case SW_TYPE_AHMAC: -+ case SW_TYPE_AHASH: -+ crypto_copyback(req->crp->crp_flags, req->crp->crp_buf, -+ req->crd->crd_inject, req->sw->u.hmac.sw_mlen, req->result); -+ ahash_request_free(req->crypto_req); -+ break; -+ case SW_TYPE_ABLKCIPHER: -+ ablkcipher_request_free(req->crypto_req); -+ break; -+ default: -+ req->crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ req->crd = req->crd->crd_next; -+ if (req->crd) { -+ swcr_process_req(req); -+ return; -+ } -+ -+done: -+ dprintk("%s crypto_done %p\n", __FUNCTION__, req); -+ crypto_done(req->crp); -+ kmem_cache_free(swcr_req_cache, req); -+} -+#endif /* defined(HAVE_ABLKCIPHER) || defined(HAVE_AHASH) */ -+ -+ -+static void swcr_process_req(struct swcr_req *req) -+{ -+ struct swcr_data *sw; -+ struct cryptop *crp = req->crp; -+ struct cryptodesc *crd = req->crd; -+ struct sk_buff *skb = (struct sk_buff *) crp->crp_buf; -+ struct uio *uiop = (struct uio *) crp->crp_buf; -+ int sg_num, sg_len, skip; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ /* -+ * Find the crypto context. -+ * -+ * XXX Note that the logic here prevents us from having -+ * XXX the same algorithm multiple times in a session -+ * XXX (or rather, we can but it won't give us the right -+ * XXX results). To do that, we'd need some way of differentiating -+ * XXX between the various instances of an algorithm (so we can -+ * XXX locate the correct crypto context). -+ */ -+ for (sw = req->sw_head; sw && sw->sw_alg != crd->crd_alg; sw = sw->sw_next) -+ ; -+ -+ /* No such context ? */ -+ if (sw == NULL) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ goto done; -+ } -+ -+ req->sw = sw; -+ skip = crd->crd_skip; -+ -+ /* -+ * setup the SG list skip from the start of the buffer -+ */ -+ memset(req->sg, 0, sizeof(req->sg)); -+ sg_init_table(req->sg, SCATTERLIST_MAX); -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ int i, len; -+ -+ sg_num = 0; -+ sg_len = 0; -+ -+ if (skip < skb_headlen(skb)) { -+ len = skb_headlen(skb) - skip; -+ if (len + sg_len > crd->crd_len) -+ len = crd->crd_len - sg_len; -+ sg_set_page(&req->sg[sg_num], -+ virt_to_page(skb->data + skip), len, -+ offset_in_page(skb->data + skip)); -+ sg_len += len; -+ sg_num++; -+ skip = 0; -+ } else -+ skip -= skb_headlen(skb); -+ -+ for (i = 0; sg_len < crd->crd_len && -+ i < skb_shinfo(skb)->nr_frags && -+ sg_num < SCATTERLIST_MAX; i++) { -+ if (skip < skb_shinfo(skb)->frags[i].size) { -+ len = skb_shinfo(skb)->frags[i].size - skip; -+ if (len + sg_len > crd->crd_len) -+ len = crd->crd_len - sg_len; -+ sg_set_page(&req->sg[sg_num], -+ skb_shinfo(skb)->frags[i].page, -+ len, -+ skb_shinfo(skb)->frags[i].page_offset + skip); -+ sg_len += len; -+ sg_num++; -+ skip = 0; -+ } else -+ skip -= skb_shinfo(skb)->frags[i].size; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ int len; -+ -+ sg_len = 0; -+ for (sg_num = 0; sg_len < crd->crd_len && -+ sg_num < uiop->uio_iovcnt && -+ sg_num < SCATTERLIST_MAX; sg_num++) { -+ if (skip <= uiop->uio_iov[sg_num].iov_len) { -+ len = uiop->uio_iov[sg_num].iov_len - skip; -+ if (len + sg_len > crd->crd_len) -+ len = crd->crd_len - sg_len; -+ sg_set_page(&req->sg[sg_num], -+ virt_to_page(uiop->uio_iov[sg_num].iov_base+skip), -+ len, -+ offset_in_page(uiop->uio_iov[sg_num].iov_base+skip)); -+ sg_len += len; -+ skip = 0; -+ } else -+ skip -= uiop->uio_iov[sg_num].iov_len; -+ } -+ } else { -+ sg_len = (crp->crp_ilen - skip); -+ if (sg_len > crd->crd_len) -+ sg_len = crd->crd_len; -+ sg_set_page(&req->sg[0], virt_to_page(crp->crp_buf + skip), -+ sg_len, offset_in_page(crp->crp_buf + skip)); -+ sg_num = 1; -+ } -+ -+ switch (sw->sw_type & SW_TYPE_ALG_AMASK) { -+ -+#ifdef HAVE_AHASH -+ case SW_TYPE_AHMAC: -+ case SW_TYPE_AHASH: -+ { -+ int ret; -+ -+ /* check we have room for the result */ -+ if (crp->crp_ilen - crd->crd_inject < sw->u.hmac.sw_mlen) { -+ dprintk("cryptosoft: EINVAL crp_ilen=%d, len=%d, inject=%d " -+ "digestsize=%d\n", crp->crp_ilen, crd->crd_skip + sg_len, -+ crd->crd_inject, sw->u.hmac.sw_mlen); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ req->crypto_req = -+ ahash_request_alloc(__crypto_ahash_cast(sw->sw_tfm),GFP_KERNEL); -+ if (!req->crypto_req) { -+ crp->crp_etype = ENOMEM; -+ dprintk("%s,%d: ENOMEM ahash_request_alloc", __FILE__, __LINE__); -+ goto done; -+ } -+ -+ ahash_request_set_callback(req->crypto_req, -+ CRYPTO_TFM_REQ_MAY_BACKLOG, swcr_process_callback, req); -+ -+ memset(req->result, 0, sizeof(req->result)); -+ -+ if (sw->sw_type & SW_TYPE_AHMAC) -+ crypto_ahash_setkey(__crypto_ahash_cast(sw->sw_tfm), -+ sw->u.hmac.sw_key, sw->u.hmac.sw_klen); -+ ahash_request_set_crypt(req->crypto_req, req->sg, req->result, sg_len); -+ ret = crypto_ahash_digest(req->crypto_req); -+ switch (ret) { -+ case -EINPROGRESS: -+ case -EBUSY: -+ return; -+ default: -+ case 0: -+ dprintk("hash OP %s %d\n", ret ? "failed" : "success", ret); -+ crp->crp_etype = ret; -+ ahash_request_free(req->crypto_req); -+ goto done; -+ } -+ } break; -+#endif /* HAVE_AHASH */ -+ -+#ifdef HAVE_ABLKCIPHER -+ case SW_TYPE_ABLKCIPHER: { -+ int ret; -+ unsigned char *ivp = req->iv; -+ int ivsize = -+ crypto_ablkcipher_ivsize(__crypto_ablkcipher_cast(sw->sw_tfm)); -+ -+ if (sg_len < crypto_ablkcipher_blocksize( -+ __crypto_ablkcipher_cast(sw->sw_tfm))) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: EINVAL len %d < %d\n", __FILE__, __LINE__, -+ sg_len, crypto_ablkcipher_blocksize( -+ __crypto_ablkcipher_cast(sw->sw_tfm))); -+ goto done; -+ } -+ -+ if (ivsize > sizeof(req->iv)) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ goto done; -+ } -+ -+ req->crypto_req = ablkcipher_request_alloc( -+ __crypto_ablkcipher_cast(sw->sw_tfm), GFP_KERNEL); -+ if (!req->crypto_req) { -+ crp->crp_etype = ENOMEM; -+ dprintk("%s,%d: ENOMEM ablkcipher_request_alloc", -+ __FILE__, __LINE__); -+ goto done; -+ } -+ -+ ablkcipher_request_set_callback(req->crypto_req, -+ CRYPTO_TFM_REQ_MAY_BACKLOG, swcr_process_callback, req); -+ -+ if (crd->crd_flags & CRD_F_KEY_EXPLICIT) { -+ int i, error; -+ -+ if (debug) { -+ dprintk("%s key:", __FUNCTION__); -+ for (i = 0; i < (crd->crd_klen + 7) / 8; i++) -+ dprintk("%s0x%x", (i % 8) ? " " : "\n ", -+ crd->crd_key[i] & 0xff); -+ dprintk("\n"); -+ } -+ /* OCF doesn't enforce keys */ -+ crypto_ablkcipher_set_flags(__crypto_ablkcipher_cast(sw->sw_tfm), -+ CRYPTO_TFM_REQ_WEAK_KEY); -+ error = crypto_ablkcipher_setkey( -+ __crypto_ablkcipher_cast(sw->sw_tfm), crd->crd_key, -+ (crd->crd_klen + 7) / 8); -+ if (error) { -+ dprintk("cryptosoft: setkey failed %d (crt_flags=0x%x)\n", -+ error, sw->sw_tfm->crt_flags); -+ crp->crp_etype = -error; -+ } -+ } -+ -+ if (crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ -+ -+ if (crd->crd_flags & CRD_F_IV_EXPLICIT) -+ ivp = crd->crd_iv; -+ else -+ get_random_bytes(ivp, ivsize); -+ /* -+ * do we have to copy the IV back to the buffer ? -+ */ -+ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, ivsize, (caddr_t)ivp); -+ } -+ ablkcipher_request_set_crypt(req->crypto_req, req->sg, req->sg, -+ sg_len, ivp); -+ ret = crypto_ablkcipher_encrypt(req->crypto_req); -+ -+ } else { /*decrypt */ -+ -+ if (crd->crd_flags & CRD_F_IV_EXPLICIT) -+ ivp = crd->crd_iv; -+ else -+ crypto_copydata(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, ivsize, (caddr_t)ivp); -+ ablkcipher_request_set_crypt(req->crypto_req, req->sg, req->sg, -+ sg_len, ivp); -+ ret = crypto_ablkcipher_decrypt(req->crypto_req); -+ } -+ -+ switch (ret) { -+ case -EINPROGRESS: -+ case -EBUSY: -+ return; -+ default: -+ case 0: -+ dprintk("crypto OP %s %d\n", ret ? "failed" : "success", ret); -+ crp->crp_etype = ret; -+ goto done; -+ } -+ } break; -+#endif /* HAVE_ABLKCIPHER */ -+ -+ case SW_TYPE_BLKCIPHER: { -+ unsigned char iv[EALG_MAX_BLOCK_LEN]; -+ unsigned char *ivp = iv; -+ struct blkcipher_desc desc; -+ int ivsize = crypto_blkcipher_ivsize(crypto_blkcipher_cast(sw->sw_tfm)); -+ -+ if (sg_len < crypto_blkcipher_blocksize( -+ crypto_blkcipher_cast(sw->sw_tfm))) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: EINVAL len %d < %d\n", __FILE__, __LINE__, -+ sg_len, crypto_blkcipher_blocksize( -+ crypto_blkcipher_cast(sw->sw_tfm))); -+ goto done; -+ } -+ -+ if (ivsize > sizeof(iv)) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ goto done; -+ } -+ -+ if (crd->crd_flags & CRD_F_KEY_EXPLICIT) { -+ int i, error; -+ -+ if (debug) { -+ dprintk("%s key:", __FUNCTION__); -+ for (i = 0; i < (crd->crd_klen + 7) / 8; i++) -+ dprintk("%s0x%x", (i % 8) ? " " : "\n ", -+ crd->crd_key[i] & 0xff); -+ dprintk("\n"); -+ } -+ /* OCF doesn't enforce keys */ -+ crypto_blkcipher_set_flags(crypto_blkcipher_cast(sw->sw_tfm), -+ CRYPTO_TFM_REQ_WEAK_KEY); -+ error = crypto_blkcipher_setkey( -+ crypto_blkcipher_cast(sw->sw_tfm), crd->crd_key, -+ (crd->crd_klen + 7) / 8); -+ if (error) { -+ dprintk("cryptosoft: setkey failed %d (crt_flags=0x%x)\n", -+ error, sw->sw_tfm->crt_flags); -+ crp->crp_etype = -error; -+ } -+ } -+ -+ memset(&desc, 0, sizeof(desc)); -+ desc.tfm = crypto_blkcipher_cast(sw->sw_tfm); -+ -+ if (crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ -+ -+ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { -+ ivp = crd->crd_iv; -+ } else { -+ get_random_bytes(ivp, ivsize); -+ } -+ /* -+ * do we have to copy the IV back to the buffer ? -+ */ -+ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, ivsize, (caddr_t)ivp); -+ } -+ desc.info = ivp; -+ crypto_blkcipher_encrypt_iv(&desc, req->sg, req->sg, sg_len); -+ -+ } else { /*decrypt */ -+ -+ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { -+ ivp = crd->crd_iv; -+ } else { -+ crypto_copydata(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, ivsize, (caddr_t)ivp); -+ } -+ desc.info = ivp; -+ crypto_blkcipher_decrypt_iv(&desc, req->sg, req->sg, sg_len); -+ } -+ } break; -+ -+ case SW_TYPE_HMAC: -+ case SW_TYPE_HASH: -+ { -+ char result[HASH_MAX_LEN]; -+ struct hash_desc desc; -+ -+ /* check we have room for the result */ -+ if (crp->crp_ilen - crd->crd_inject < sw->u.hmac.sw_mlen) { -+ dprintk("cryptosoft: EINVAL crp_ilen=%d, len=%d, inject=%d " -+ "digestsize=%d\n", crp->crp_ilen, crd->crd_skip + sg_len, -+ crd->crd_inject, sw->u.hmac.sw_mlen); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ memset(&desc, 0, sizeof(desc)); -+ desc.tfm = crypto_hash_cast(sw->sw_tfm); -+ -+ memset(result, 0, sizeof(result)); -+ -+ if (sw->sw_type & SW_TYPE_HMAC) { -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) -+ crypto_hmac(sw->sw_tfm, sw->u.hmac.sw_key, &sw->u.hmac.sw_klen, -+ req->sg, sg_num, result); -+#else -+ crypto_hash_setkey(desc.tfm, sw->u.hmac.sw_key, -+ sw->u.hmac.sw_klen); -+ crypto_hash_digest(&desc, req->sg, sg_len, result); -+#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) */ -+ -+ } else { /* SW_TYPE_HASH */ -+ crypto_hash_digest(&desc, req->sg, sg_len, result); -+ } -+ -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, sw->u.hmac.sw_mlen, result); -+ } -+ break; -+ -+ case SW_TYPE_COMP: { -+ void *ibuf = NULL; -+ void *obuf = sw->u.sw_comp_buf; -+ int ilen = sg_len, olen = CRYPTO_MAX_DATA_LEN; -+ int ret = 0; -+ -+ /* -+ * we need to use an additional copy if there is more than one -+ * input chunk since the kernel comp routines do not handle -+ * SG yet. Otherwise we just use the input buffer as is. -+ * Rather than allocate another buffer we just split the tmp -+ * buffer we already have. -+ * Perhaps we should just use zlib directly ? -+ */ -+ if (sg_num > 1) { -+ int blk; -+ -+ ibuf = obuf; -+ for (blk = 0; blk < sg_num; blk++) { -+ memcpy(obuf, sg_virt(&req->sg[blk]), -+ req->sg[blk].length); -+ obuf += req->sg[blk].length; -+ } -+ olen -= sg_len; -+ } else -+ ibuf = sg_virt(&req->sg[0]); -+ -+ if (crd->crd_flags & CRD_F_ENCRYPT) { /* compress */ -+ ret = crypto_comp_compress(crypto_comp_cast(sw->sw_tfm), -+ ibuf, ilen, obuf, &olen); -+ if (!ret && olen > crd->crd_len) { -+ dprintk("cryptosoft: ERANGE compress %d into %d\n", -+ crd->crd_len, olen); -+ if (swcr_fail_if_compression_grows) -+ ret = ERANGE; -+ } -+ } else { /* decompress */ -+ ret = crypto_comp_decompress(crypto_comp_cast(sw->sw_tfm), -+ ibuf, ilen, obuf, &olen); -+ if (!ret && (olen + crd->crd_inject) > crp->crp_olen) { -+ dprintk("cryptosoft: ETOOSMALL decompress %d into %d, " -+ "space for %d,at offset %d\n", -+ crd->crd_len, olen, crp->crp_olen, crd->crd_inject); -+ ret = ETOOSMALL; -+ } -+ } -+ if (ret) -+ dprintk("%s,%d: ret = %d\n", __FILE__, __LINE__, ret); -+ -+ /* -+ * on success copy result back, -+ * linux crpyto API returns -errno, we need to fix that -+ */ -+ crp->crp_etype = ret < 0 ? -ret : ret; -+ if (ret == 0) { -+ /* copy back the result and return it's size */ -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, olen, obuf); -+ crp->crp_olen = olen; -+ } -+ -+ -+ } break; -+ -+ default: -+ /* Unknown/unsupported algorithm */ -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+done: -+ crypto_done(crp); -+ kmem_cache_free(swcr_req_cache, req); -+} -+ -+ -+/* -+ * Process a crypto request. -+ */ -+static int -+swcr_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ struct swcr_req *req = NULL; -+ u_int32_t lid; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ /* Sanity check */ -+ if (crp == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ crp->crp_etype = 0; -+ -+ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ lid = crp->crp_sid & 0xffffffff; -+ if (lid >= swcr_sesnum || lid == 0 || swcr_sessions == NULL || -+ swcr_sessions[lid] == NULL) { -+ crp->crp_etype = ENOENT; -+ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); -+ goto done; -+ } -+ -+ /* -+ * do some error checking outside of the loop for SKB and IOV processing -+ * this leaves us with valid skb or uiop pointers for later -+ */ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ struct sk_buff *skb = (struct sk_buff *) crp->crp_buf; -+ if (skb_shinfo(skb)->nr_frags >= SCATTERLIST_MAX) { -+ printk("%s,%d: %d nr_frags > SCATTERLIST_MAX", __FILE__, __LINE__, -+ skb_shinfo(skb)->nr_frags); -+ goto done; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ struct uio *uiop = (struct uio *) crp->crp_buf; -+ if (uiop->uio_iovcnt > SCATTERLIST_MAX) { -+ printk("%s,%d: %d uio_iovcnt > SCATTERLIST_MAX", __FILE__, __LINE__, -+ uiop->uio_iovcnt); -+ goto done; -+ } -+ } -+ -+ /* -+ * setup a new request ready for queuing -+ */ -+ req = kmem_cache_alloc(swcr_req_cache, SLAB_ATOMIC); -+ if (req == NULL) { -+ dprintk("%s,%d: ENOMEM\n", __FILE__, __LINE__); -+ crp->crp_etype = ENOMEM; -+ goto done; -+ } -+ memset(req, 0, sizeof(*req)); -+ -+ req->sw_head = swcr_sessions[lid]; -+ req->crp = crp; -+ req->crd = crp->crp_desc; -+ -+ swcr_process_req(req); -+ return 0; -+ -+done: -+ crypto_done(crp); -+ if (req) -+ kmem_cache_free(swcr_req_cache, req); -+ return 0; -+} -+ -+ -+static int -+cryptosoft_init(void) -+{ -+ int i, sw_type, mode; -+ char *algo; -+ -+ dprintk("%s(%p)\n", __FUNCTION__, cryptosoft_init); -+ -+ swcr_req_cache = kmem_cache_create("cryptosoft_req", -+ sizeof(struct swcr_req), 0, SLAB_HWCACHE_ALIGN, NULL -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) -+ , NULL -+#endif -+ ); -+ if (!swcr_req_cache) { -+ printk("cryptosoft: failed to create request cache\n"); -+ return -ENOENT; -+ } -+ -+ softc_device_init(&swcr_softc, "cryptosoft", 0, swcr_methods); -+ -+ swcr_id = crypto_get_driverid(softc_get_device(&swcr_softc), -+ CRYPTOCAP_F_SOFTWARE | CRYPTOCAP_F_SYNC); -+ if (swcr_id < 0) { -+ printk("cryptosoft: Software crypto device cannot initialize!"); -+ return -ENODEV; -+ } -+ -+#define REGISTER(alg) \ -+ crypto_register(swcr_id, alg, 0,0) -+ -+ for (i = 0; i < sizeof(crypto_details)/sizeof(crypto_details[0]); i++) { -+ int found; -+ -+ algo = crypto_details[i].alg_name; -+ if (!algo || !*algo) { -+ dprintk("%s:Algorithm %d not supported\n", __FUNCTION__, i); -+ continue; -+ } -+ -+ mode = crypto_details[i].mode; -+ sw_type = crypto_details[i].sw_type; -+ -+ found = 0; -+ switch (sw_type & SW_TYPE_ALG_MASK) { -+ case SW_TYPE_CIPHER: -+ found = crypto_has_cipher(algo, 0, CRYPTO_ALG_ASYNC); -+ break; -+ case SW_TYPE_HMAC: -+ found = crypto_has_hash(algo, 0, swcr_no_ahash?CRYPTO_ALG_ASYNC:0); -+ break; -+ case SW_TYPE_HASH: -+ found = crypto_has_hash(algo, 0, swcr_no_ahash?CRYPTO_ALG_ASYNC:0); -+ break; -+ case SW_TYPE_COMP: -+ found = crypto_has_comp(algo, 0, CRYPTO_ALG_ASYNC); -+ break; -+ case SW_TYPE_BLKCIPHER: -+ found = crypto_has_blkcipher(algo, 0, CRYPTO_ALG_ASYNC); -+ if (!found && !swcr_no_ablk) -+ found = crypto_has_ablkcipher(algo, 0, 0); -+ break; -+ } -+ if (found) { -+ REGISTER(i); -+ } else { -+ dprintk("%s:Algorithm Type %d not supported (algorithm %d:'%s')\n", -+ __FUNCTION__, sw_type, i, algo); -+ } -+ } -+ return 0; -+} -+ -+static void -+cryptosoft_exit(void) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ crypto_unregister_all(swcr_id); -+ swcr_id = -1; -+ kmem_cache_destroy(swcr_req_cache); -+} -+ -+late_initcall(cryptosoft_init); -+module_exit(cryptosoft_exit); -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("Cryptosoft (OCF module for kernel crypto)"); -diff -Nur linux-2.6.36.orig/crypto/ocf/ep80579/icp_asym.c linux-2.6.36/crypto/ocf/ep80579/icp_asym.c ---- linux-2.6.36.orig/crypto/ocf/ep80579/icp_asym.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/ep80579/icp_asym.c 2010-11-09 20:28:04.572486503 +0100 -@@ -0,0 +1,1334 @@ -+/*************************************************************************** -+ * -+ * This file is provided under a dual BSD/GPLv2 license. When using or -+ * redistributing this file, you may do so under either license. -+ * -+ * GPL LICENSE SUMMARY -+ * -+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of version 2 of the GNU General Public License as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. -+ * The full GNU General Public License is included in this distribution -+ * in the file called LICENSE.GPL. -+ * -+ * Contact Information: -+ * Intel Corporation -+ * -+ * BSD LICENSE -+ * -+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * * Neither the name of Intel Corporation nor the names of its -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * -+ * version: Security.L.1.0.2-229 -+ * -+ ***************************************************************************/ -+ -+#include "icp_ocf.h" -+ -+/*The following define values (containing the word 'INDEX') are used to find -+the index of each input buffer of the crypto_kop struct (see OCF cryptodev.h). -+These values were found through analysis of the OCF OpenSSL patch. If the -+calling program uses different input buffer positions, these defines will have -+to be changed.*/ -+ -+/*DIFFIE HELLMAN buffer index values*/ -+#define ICP_DH_KRP_PARAM_PRIME_INDEX (0) -+#define ICP_DH_KRP_PARAM_BASE_INDEX (1) -+#define ICP_DH_KRP_PARAM_PRIVATE_VALUE_INDEX (2) -+#define ICP_DH_KRP_PARAM_RESULT_INDEX (3) -+ -+/*MOD EXP buffer index values*/ -+#define ICP_MOD_EXP_KRP_PARAM_BASE_INDEX (0) -+#define ICP_MOD_EXP_KRP_PARAM_EXPONENT_INDEX (1) -+#define ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX (2) -+#define ICP_MOD_EXP_KRP_PARAM_RESULT_INDEX (3) -+ -+/*MOD EXP CRT buffer index values*/ -+#define ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_P_INDEX (0) -+#define ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_Q_INDEX (1) -+#define ICP_MOD_EXP_CRT_KRP_PARAM_I_INDEX (2) -+#define ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DP_INDEX (3) -+#define ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DQ_INDEX (4) -+#define ICP_MOD_EXP_CRT_KRP_PARAM_COEFF_QINV_INDEX (5) -+#define ICP_MOD_EXP_CRT_KRP_PARAM_RESULT_INDEX (6) -+ -+/*DSA sign buffer index values*/ -+#define ICP_DSA_SIGN_KRP_PARAM_DGST_INDEX (0) -+#define ICP_DSA_SIGN_KRP_PARAM_PRIME_P_INDEX (1) -+#define ICP_DSA_SIGN_KRP_PARAM_PRIME_Q_INDEX (2) -+#define ICP_DSA_SIGN_KRP_PARAM_G_INDEX (3) -+#define ICP_DSA_SIGN_KRP_PARAM_X_INDEX (4) -+#define ICP_DSA_SIGN_KRP_PARAM_R_RESULT_INDEX (5) -+#define ICP_DSA_SIGN_KRP_PARAM_S_RESULT_INDEX (6) -+ -+/*DSA verify buffer index values*/ -+#define ICP_DSA_VERIFY_KRP_PARAM_DGST_INDEX (0) -+#define ICP_DSA_VERIFY_KRP_PARAM_PRIME_P_INDEX (1) -+#define ICP_DSA_VERIFY_KRP_PARAM_PRIME_Q_INDEX (2) -+#define ICP_DSA_VERIFY_KRP_PARAM_G_INDEX (3) -+#define ICP_DSA_VERIFY_KRP_PARAM_PUBKEY_INDEX (4) -+#define ICP_DSA_VERIFY_KRP_PARAM_SIG_R_INDEX (5) -+#define ICP_DSA_VERIFY_KRP_PARAM_SIG_S_INDEX (6) -+ -+/*DSA sign prime Q vs random number K size check values*/ -+#define DONT_RUN_LESS_THAN_CHECK (0) -+#define FAIL_A_IS_GREATER_THAN_B (1) -+#define FAIL_A_IS_EQUAL_TO_B (1) -+#define SUCCESS_A_IS_LESS_THAN_B (0) -+#define DSA_SIGN_RAND_GEN_VAL_CHECK_MAX_ITERATIONS (500) -+ -+/* We need to set a cryptokp success value just in case it is set or allocated -+ and not set to zero outside of this module */ -+#define CRYPTO_OP_SUCCESS (0) -+ -+/*Function to compute Diffie Hellman (DH) phase 1 or phase 2 key values*/ -+static int icp_ocfDrvDHComputeKey(struct cryptkop *krp); -+ -+/*Function to compute a Modular Exponentiation (Mod Exp)*/ -+static int icp_ocfDrvModExp(struct cryptkop *krp); -+ -+/*Function to compute a Mod Exp using the Chinease Remainder Theorem*/ -+static int icp_ocfDrvModExpCRT(struct cryptkop *krp); -+ -+/*Helper function to compute whether the first big number argument is less than -+ the second big number argument */ -+static int -+icp_ocfDrvCheckALessThanB(CpaFlatBuffer * pK, CpaFlatBuffer * pQ, int *doCheck); -+ -+/*Function to sign an input with DSA R and S keys*/ -+static int icp_ocfDrvDsaSign(struct cryptkop *krp); -+ -+/*Function to Verify a DSA buffer signature*/ -+static int icp_ocfDrvDsaVerify(struct cryptkop *krp); -+ -+/*Callback function for DH operation*/ -+static void -+icp_ocfDrvDhP1CallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, CpaFlatBuffer * pLocalOctetStringPV); -+ -+/*Callback function for ME operation*/ -+static void -+icp_ocfDrvModExpCallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, CpaFlatBuffer * pResult); -+ -+/*Callback function for ME CRT operation*/ -+static void -+icp_ocfDrvModExpCRTCallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, CpaFlatBuffer * pOutputData); -+ -+/*Callback function for DSA sign operation*/ -+static void -+icp_ocfDrvDsaRSSignCallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, -+ CpaBoolean protocolStatus, -+ CpaFlatBuffer * pR, CpaFlatBuffer * pS); -+ -+/*Callback function for DSA Verify operation*/ -+static void -+icp_ocfDrvDsaVerifyCallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, CpaBoolean verifyStatus); -+ -+/* Name : icp_ocfDrvPkeProcess -+ * -+ * Description : This function will choose which PKE process to follow -+ * based on the input arguments -+ */ -+int icp_ocfDrvPkeProcess(icp_device_t dev, struct cryptkop *krp, int hint) -+{ -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ -+ if (NULL == krp) { -+ DPRINTK("%s(): Invalid input parameters, cryptkop = %p\n", -+ __FUNCTION__, krp); -+ return EINVAL; -+ } -+ -+ if (CPA_TRUE == icp_atomic_read(&icp_ocfDrvIsExiting)) { -+ krp->krp_status = ECANCELED; -+ return ECANCELED; -+ } -+ -+ switch (krp->krp_op) { -+ case CRK_DH_COMPUTE_KEY: -+ DPRINTK("%s() doing DH_COMPUTE_KEY\n", __FUNCTION__); -+ lacStatus = icp_ocfDrvDHComputeKey(krp); -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): icp_ocfDrvDHComputeKey failed " -+ "(%d).\n", __FUNCTION__, lacStatus); -+ krp->krp_status = ECANCELED; -+ return ECANCELED; -+ } -+ -+ break; -+ -+ case CRK_MOD_EXP: -+ DPRINTK("%s() doing MOD_EXP \n", __FUNCTION__); -+ lacStatus = icp_ocfDrvModExp(krp); -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): icp_ocfDrvModExp failed (%d).\n", -+ __FUNCTION__, lacStatus); -+ krp->krp_status = ECANCELED; -+ return ECANCELED; -+ } -+ -+ break; -+ -+ case CRK_MOD_EXP_CRT: -+ DPRINTK("%s() doing MOD_EXP_CRT \n", __FUNCTION__); -+ lacStatus = icp_ocfDrvModExpCRT(krp); -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): icp_ocfDrvModExpCRT " -+ "failed (%d).\n", __FUNCTION__, lacStatus); -+ krp->krp_status = ECANCELED; -+ return ECANCELED; -+ } -+ -+ break; -+ -+ case CRK_DSA_SIGN: -+ DPRINTK("%s() doing DSA_SIGN \n", __FUNCTION__); -+ lacStatus = icp_ocfDrvDsaSign(krp); -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): icp_ocfDrvDsaSign " -+ "failed (%d).\n", __FUNCTION__, lacStatus); -+ krp->krp_status = ECANCELED; -+ return ECANCELED; -+ } -+ -+ break; -+ -+ case CRK_DSA_VERIFY: -+ DPRINTK("%s() doing DSA_VERIFY \n", __FUNCTION__); -+ lacStatus = icp_ocfDrvDsaVerify(krp); -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): icp_ocfDrvDsaVerify " -+ "failed (%d).\n", __FUNCTION__, lacStatus); -+ krp->krp_status = ECANCELED; -+ return ECANCELED; -+ } -+ -+ break; -+ -+ default: -+ EPRINTK("%s(): Asymettric function not " -+ "supported (%d).\n", __FUNCTION__, krp->krp_op); -+ krp->krp_status = EOPNOTSUPP; -+ return EOPNOTSUPP; -+ } -+ -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+} -+ -+/* Name : icp_ocfDrvSwapBytes -+ * -+ * Description : This function is used to swap the byte order of a buffer. -+ * It has been seen that in general we are passed little endian byte order -+ * buffers, but LAC only accepts big endian byte order buffers. -+ */ -+static void inline icp_ocfDrvSwapBytes(u_int8_t * num, u_int32_t buff_len_bytes) -+{ -+ -+ int i; -+ u_int8_t *end_ptr; -+ u_int8_t hold_val; -+ -+ end_ptr = num + (buff_len_bytes - 1); -+ buff_len_bytes = buff_len_bytes >> 1; -+ for (i = 0; i < buff_len_bytes; i++) { -+ hold_val = *num; -+ *num = *end_ptr; -+ num++; -+ *end_ptr = hold_val; -+ end_ptr--; -+ } -+} -+ -+/* Name : icp_ocfDrvDHComputeKey -+ * -+ * Description : This function will map Diffie Hellman calls from OCF -+ * to the LAC API. OCF uses this function for Diffie Hellman Phase1 and -+ * Phase2. LAC has a separate Diffie Hellman Phase2 call, however both phases -+ * break down to a modular exponentiation. -+ */ -+static int icp_ocfDrvDHComputeKey(struct cryptkop *krp) -+{ -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ void *callbackTag = NULL; -+ CpaCyDhPhase1KeyGenOpData *pPhase1OpData = NULL; -+ CpaFlatBuffer *pLocalOctetStringPV = NULL; -+ uint32_t dh_prime_len_bytes = 0, dh_prime_len_bits = 0; -+ -+ /* Input checks - check prime is a multiple of 8 bits to allow for -+ allocation later */ -+ dh_prime_len_bits = -+ (krp->krp_param[ICP_DH_KRP_PARAM_PRIME_INDEX].crp_nbits); -+ -+ /* LAC can reject prime lengths based on prime key sizes, we just -+ need to make sure we can allocate space for the base and -+ exponent buffers correctly */ -+ if ((dh_prime_len_bits % NUM_BITS_IN_BYTE) != 0) { -+ APRINTK("%s(): Warning Prime number buffer size is not a " -+ "multiple of 8 bits\n", __FUNCTION__); -+ } -+ -+ /* Result storage space should be the same size as the prime as this -+ value can take up the same amount of storage space */ -+ if (dh_prime_len_bits != -+ krp->krp_param[ICP_DH_KRP_PARAM_RESULT_INDEX].crp_nbits) { -+ DPRINTK("%s(): Return Buffer must be the same size " -+ "as the Prime buffer\n", __FUNCTION__); -+ krp->krp_status = EINVAL; -+ return EINVAL; -+ } -+ /* Switch to size in bytes */ -+ BITS_TO_BYTES(dh_prime_len_bytes, dh_prime_len_bits); -+ -+ callbackTag = krp; -+ -+/*All allocations are set to ICP_M_NOWAIT due to the possibility of getting -+called in interrupt context*/ -+ pPhase1OpData = icp_kmem_cache_zalloc(drvDH_zone, ICP_M_NOWAIT); -+ if (NULL == pPhase1OpData) { -+ APRINTK("%s():Failed to get memory for key gen data\n", -+ __FUNCTION__); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ pLocalOctetStringPV = -+ icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); -+ if (NULL == pLocalOctetStringPV) { -+ APRINTK("%s():Failed to get memory for pLocalOctetStringPV\n", -+ __FUNCTION__); -+ ICP_CACHE_FREE(drvDH_zone, pPhase1OpData); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ /* Link parameters */ -+ pPhase1OpData->primeP.pData = -+ krp->krp_param[ICP_DH_KRP_PARAM_PRIME_INDEX].crp_p; -+ -+ pPhase1OpData->primeP.dataLenInBytes = dh_prime_len_bytes; -+ -+ icp_ocfDrvSwapBytes(pPhase1OpData->primeP.pData, dh_prime_len_bytes); -+ -+ pPhase1OpData->baseG.pData = -+ krp->krp_param[ICP_DH_KRP_PARAM_BASE_INDEX].crp_p; -+ -+ BITS_TO_BYTES(pPhase1OpData->baseG.dataLenInBytes, -+ krp->krp_param[ICP_DH_KRP_PARAM_BASE_INDEX].crp_nbits); -+ -+ icp_ocfDrvSwapBytes(pPhase1OpData->baseG.pData, -+ pPhase1OpData->baseG.dataLenInBytes); -+ -+ pPhase1OpData->privateValueX.pData = -+ krp->krp_param[ICP_DH_KRP_PARAM_PRIVATE_VALUE_INDEX].crp_p; -+ -+ BITS_TO_BYTES(pPhase1OpData->privateValueX.dataLenInBytes, -+ krp->krp_param[ICP_DH_KRP_PARAM_PRIVATE_VALUE_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(pPhase1OpData->privateValueX.pData, -+ pPhase1OpData->privateValueX.dataLenInBytes); -+ -+ /* Output parameters */ -+ pLocalOctetStringPV->pData = -+ krp->krp_param[ICP_DH_KRP_PARAM_RESULT_INDEX].crp_p; -+ -+ BITS_TO_BYTES(pLocalOctetStringPV->dataLenInBytes, -+ krp->krp_param[ICP_DH_KRP_PARAM_RESULT_INDEX].crp_nbits); -+ -+ lacStatus = cpaCyDhKeyGenPhase1(CPA_INSTANCE_HANDLE_SINGLE, -+ icp_ocfDrvDhP1CallBack, -+ callbackTag, pPhase1OpData, -+ pLocalOctetStringPV); -+ -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): DH Phase 1 Key Gen failed (%d).\n", -+ __FUNCTION__, lacStatus); -+ icp_ocfDrvFreeFlatBuffer(pLocalOctetStringPV); -+ ICP_CACHE_FREE(drvDH_zone, pPhase1OpData); -+ } -+ -+ return lacStatus; -+} -+ -+/* Name : icp_ocfDrvModExp -+ * -+ * Description : This function will map ordinary Modular Exponentiation calls -+ * from OCF to the LAC API. -+ * -+ */ -+static int icp_ocfDrvModExp(struct cryptkop *krp) -+{ -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ void *callbackTag = NULL; -+ CpaCyLnModExpOpData *pModExpOpData = NULL; -+ CpaFlatBuffer *pResult = NULL; -+ -+ if ((krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX].crp_nbits % -+ NUM_BITS_IN_BYTE) != 0) { -+ DPRINTK("%s(): Warning - modulus buffer size (%d) is not a " -+ "multiple of 8 bits\n", __FUNCTION__, -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX]. -+ crp_nbits); -+ } -+ -+ /* Result storage space should be the same size as the prime as this -+ value can take up the same amount of storage space */ -+ if (krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX].crp_nbits > -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_RESULT_INDEX].crp_nbits) { -+ APRINTK("%s(): Return Buffer size must be the same or" -+ " greater than the Modulus buffer\n", __FUNCTION__); -+ krp->krp_status = EINVAL; -+ return EINVAL; -+ } -+ -+ callbackTag = krp; -+ -+ pModExpOpData = icp_kmem_cache_zalloc(drvLnModExp_zone, ICP_M_NOWAIT); -+ if (NULL == pModExpOpData) { -+ APRINTK("%s():Failed to get memory for key gen data\n", -+ __FUNCTION__); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ pResult = icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); -+ if (NULL == pResult) { -+ APRINTK("%s():Failed to get memory for ModExp result\n", -+ __FUNCTION__); -+ ICP_CACHE_FREE(drvLnModExp_zone, pModExpOpData); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ /* Link parameters */ -+ pModExpOpData->modulus.pData = -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX].crp_p; -+ BITS_TO_BYTES(pModExpOpData->modulus.dataLenInBytes, -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(pModExpOpData->modulus.pData, -+ pModExpOpData->modulus.dataLenInBytes); -+ -+ DPRINTK("%s : base (%d)\n", __FUNCTION__, krp-> -+ krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX].crp_nbits); -+ pModExpOpData->base.pData = -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX].crp_p; -+ BITS_TO_BYTES(pModExpOpData->base.dataLenInBytes, -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX]. -+ crp_nbits); -+ icp_ocfDrvSwapBytes(pModExpOpData->base.pData, -+ pModExpOpData->base.dataLenInBytes); -+ -+ pModExpOpData->exponent.pData = -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_EXPONENT_INDEX].crp_p; -+ BITS_TO_BYTES(pModExpOpData->exponent.dataLenInBytes, -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_EXPONENT_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(pModExpOpData->exponent.pData, -+ pModExpOpData->exponent.dataLenInBytes); -+ /* Output parameters */ -+ pResult->pData = -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_RESULT_INDEX].crp_p, -+ BITS_TO_BYTES(pResult->dataLenInBytes, -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_RESULT_INDEX]. -+ crp_nbits); -+ -+ lacStatus = cpaCyLnModExp(CPA_INSTANCE_HANDLE_SINGLE, -+ icp_ocfDrvModExpCallBack, -+ callbackTag, pModExpOpData, pResult); -+ -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): Mod Exp Operation failed (%d).\n", -+ __FUNCTION__, lacStatus); -+ krp->krp_status = ECANCELED; -+ icp_ocfDrvFreeFlatBuffer(pResult); -+ ICP_CACHE_FREE(drvLnModExp_zone, pModExpOpData); -+ } -+ -+ return lacStatus; -+} -+ -+/* Name : icp_ocfDrvModExpCRT -+ * -+ * Description : This function will map ordinary Modular Exponentiation Chinese -+ * Remainder Theorem implementaion calls from OCF to the LAC API. -+ * -+ * Note : Mod Exp CRT for this driver is accelerated through LAC RSA type 2 -+ * decrypt operation. Therefore P and Q input values must always be prime -+ * numbers. Although basic primality checks are done in LAC, it is up to the -+ * user to do any correct prime number checking before passing the inputs. -+ */ -+static int icp_ocfDrvModExpCRT(struct cryptkop *krp) -+{ -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ CpaCyRsaDecryptOpData *rsaDecryptOpData = NULL; -+ void *callbackTag = NULL; -+ CpaFlatBuffer *pOutputData = NULL; -+ -+ /*Parameter input checks are all done by LAC, no need to repeat -+ them here. */ -+ callbackTag = krp; -+ -+ rsaDecryptOpData = -+ icp_kmem_cache_zalloc(drvRSADecrypt_zone, ICP_M_NOWAIT); -+ if (NULL == rsaDecryptOpData) { -+ APRINTK("%s():Failed to get memory" -+ " for MOD EXP CRT Op data struct\n", __FUNCTION__); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ rsaDecryptOpData->pRecipientPrivateKey -+ = icp_kmem_cache_zalloc(drvRSAPrivateKey_zone, ICP_M_NOWAIT); -+ if (NULL == rsaDecryptOpData->pRecipientPrivateKey) { -+ APRINTK("%s():Failed to get memory for MOD EXP CRT" -+ " private key values struct\n", __FUNCTION__); -+ ICP_CACHE_FREE(drvRSADecrypt_zone, rsaDecryptOpData); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ version = CPA_CY_RSA_VERSION_TWO_PRIME; -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRepType = CPA_CY_RSA_PRIVATE_KEY_REP_TYPE_2; -+ -+ pOutputData = icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); -+ if (NULL == pOutputData) { -+ APRINTK("%s():Failed to get memory" -+ " for MOD EXP CRT output data\n", __FUNCTION__); -+ ICP_CACHE_FREE(drvRSAPrivateKey_zone, -+ rsaDecryptOpData->pRecipientPrivateKey); -+ ICP_CACHE_FREE(drvRSADecrypt_zone, rsaDecryptOpData); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ version = CPA_CY_RSA_VERSION_TWO_PRIME; -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRepType = CPA_CY_RSA_PRIVATE_KEY_REP_TYPE_2; -+ -+ /* Link parameters */ -+ rsaDecryptOpData->inputData.pData = -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_I_INDEX].crp_p; -+ BITS_TO_BYTES(rsaDecryptOpData->inputData.dataLenInBytes, -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_I_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(rsaDecryptOpData->inputData.pData, -+ rsaDecryptOpData->inputData.dataLenInBytes); -+ -+ rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2.prime1P.pData = -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_P_INDEX].crp_p; -+ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2. -+ prime1P.dataLenInBytes, -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_P_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.prime1P.pData, -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.prime1P.dataLenInBytes); -+ -+ rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2.prime2Q.pData = -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_Q_INDEX].crp_p; -+ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2. -+ prime2Q.dataLenInBytes, -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_Q_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.prime2Q.pData, -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.prime2Q.dataLenInBytes); -+ -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.exponent1Dp.pData = -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DP_INDEX].crp_p; -+ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2. -+ exponent1Dp.dataLenInBytes, -+ krp-> -+ krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DP_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.exponent1Dp.pData, -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.exponent1Dp.dataLenInBytes); -+ -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.exponent2Dq.pData = -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DQ_INDEX].crp_p; -+ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.exponent2Dq.dataLenInBytes, -+ krp-> -+ krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DQ_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.exponent2Dq.pData, -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.exponent2Dq.dataLenInBytes); -+ -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.coefficientQInv.pData = -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_COEFF_QINV_INDEX].crp_p; -+ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.coefficientQInv.dataLenInBytes, -+ krp-> -+ krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_COEFF_QINV_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.coefficientQInv.pData, -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.coefficientQInv.dataLenInBytes); -+ -+ /* Output Parameter */ -+ pOutputData->pData = -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_RESULT_INDEX].crp_p; -+ BITS_TO_BYTES(pOutputData->dataLenInBytes, -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_RESULT_INDEX]. -+ crp_nbits); -+ -+ lacStatus = cpaCyRsaDecrypt(CPA_INSTANCE_HANDLE_SINGLE, -+ icp_ocfDrvModExpCRTCallBack, -+ callbackTag, rsaDecryptOpData, pOutputData); -+ -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): Mod Exp CRT Operation failed (%d).\n", -+ __FUNCTION__, lacStatus); -+ krp->krp_status = ECANCELED; -+ icp_ocfDrvFreeFlatBuffer(pOutputData); -+ ICP_CACHE_FREE(drvRSAPrivateKey_zone, -+ rsaDecryptOpData->pRecipientPrivateKey); -+ ICP_CACHE_FREE(drvRSADecrypt_zone, rsaDecryptOpData); -+ } -+ -+ return lacStatus; -+} -+ -+/* Name : icp_ocfDrvCheckALessThanB -+ * -+ * Description : This function will check whether the first argument is less -+ * than the second. It is used to check whether the DSA RS sign Random K -+ * value is less than the Prime Q value (as defined in the specification) -+ * -+ */ -+static int -+icp_ocfDrvCheckALessThanB(CpaFlatBuffer * pK, CpaFlatBuffer * pQ, int *doCheck) -+{ -+ -+ uint8_t *MSB_K = pK->pData; -+ uint8_t *MSB_Q = pQ->pData; -+ uint32_t buffer_lengths_in_bytes = pQ->dataLenInBytes; -+ -+ if (DONT_RUN_LESS_THAN_CHECK == *doCheck) { -+ return FAIL_A_IS_GREATER_THAN_B; -+ } -+ -+/*Check MSBs -+if A == B, check next MSB -+if A > B, return A_IS_GREATER_THAN_B -+if A < B, return A_IS_LESS_THAN_B (success) -+*/ -+ while (*MSB_K == *MSB_Q) { -+ MSB_K++; -+ MSB_Q++; -+ -+ buffer_lengths_in_bytes--; -+ if (0 == buffer_lengths_in_bytes) { -+ DPRINTK("%s() Buffers have equal value!!\n", -+ __FUNCTION__); -+ return FAIL_A_IS_EQUAL_TO_B; -+ } -+ -+ } -+ -+ if (*MSB_K < *MSB_Q) { -+ return SUCCESS_A_IS_LESS_THAN_B; -+ } else { -+ return FAIL_A_IS_GREATER_THAN_B; -+ } -+ -+} -+ -+/* Name : icp_ocfDrvDsaSign -+ * -+ * Description : This function will map DSA RS Sign from OCF to the LAC API. -+ * -+ * NOTE: From looking at OCF patch to OpenSSL and even the number of input -+ * parameters, OCF expects us to generate the random seed value. This value -+ * is generated and passed to LAC, however the number is discared in the -+ * callback and not returned to the user. -+ */ -+static int icp_ocfDrvDsaSign(struct cryptkop *krp) -+{ -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ CpaCyDsaRSSignOpData *dsaRsSignOpData = NULL; -+ void *callbackTag = NULL; -+ CpaCyRandGenOpData randGenOpData; -+ int primeQSizeInBytes = 0; -+ int doCheck = 0; -+ CpaFlatBuffer randData; -+ CpaBoolean protocolStatus = CPA_FALSE; -+ CpaFlatBuffer *pR = NULL; -+ CpaFlatBuffer *pS = NULL; -+ -+ callbackTag = krp; -+ -+ BITS_TO_BYTES(primeQSizeInBytes, -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_Q_INDEX]. -+ crp_nbits); -+ -+ if (DSA_RS_SIGN_PRIMEQ_SIZE_IN_BYTES != primeQSizeInBytes) { -+ APRINTK("%s(): DSA PRIME Q size not equal to the " -+ "FIPS defined 20bytes, = %d\n", -+ __FUNCTION__, primeQSizeInBytes); -+ krp->krp_status = EDOM; -+ return EDOM; -+ } -+ -+ dsaRsSignOpData = -+ icp_kmem_cache_zalloc(drvDSARSSign_zone, ICP_M_NOWAIT); -+ if (NULL == dsaRsSignOpData) { -+ APRINTK("%s():Failed to get memory" -+ " for DSA RS Sign Op data struct\n", __FUNCTION__); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ dsaRsSignOpData->K.pData = -+ icp_kmem_cache_alloc(drvDSARSSignKValue_zone, ICP_M_NOWAIT); -+ -+ if (NULL == dsaRsSignOpData->K.pData) { -+ APRINTK("%s():Failed to get memory" -+ " for DSA RS Sign Op Random value\n", __FUNCTION__); -+ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ pR = icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); -+ if (NULL == pR) { -+ APRINTK("%s():Failed to get memory" -+ " for DSA signature R\n", __FUNCTION__); -+ ICP_CACHE_FREE(drvDSARSSignKValue_zone, -+ dsaRsSignOpData->K.pData); -+ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ pS = icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); -+ if (NULL == pS) { -+ APRINTK("%s():Failed to get memory" -+ " for DSA signature S\n", __FUNCTION__); -+ icp_ocfDrvFreeFlatBuffer(pR); -+ ICP_CACHE_FREE(drvDSARSSignKValue_zone, -+ dsaRsSignOpData->K.pData); -+ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ /*link prime number parameter for ease of processing */ -+ dsaRsSignOpData->P.pData = -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_P_INDEX].crp_p; -+ BITS_TO_BYTES(dsaRsSignOpData->P.dataLenInBytes, -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_P_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(dsaRsSignOpData->P.pData, -+ dsaRsSignOpData->P.dataLenInBytes); -+ -+ dsaRsSignOpData->Q.pData = -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_Q_INDEX].crp_p; -+ BITS_TO_BYTES(dsaRsSignOpData->Q.dataLenInBytes, -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_Q_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(dsaRsSignOpData->Q.pData, -+ dsaRsSignOpData->Q.dataLenInBytes); -+ -+ /*generate random number with equal buffer size to Prime value Q, -+ but value less than Q */ -+ dsaRsSignOpData->K.dataLenInBytes = dsaRsSignOpData->Q.dataLenInBytes; -+ -+ randGenOpData.generateBits = CPA_TRUE; -+ randGenOpData.lenInBytes = dsaRsSignOpData->K.dataLenInBytes; -+ -+ icp_ocfDrvPtrAndLenToFlatBuffer(dsaRsSignOpData->K.pData, -+ dsaRsSignOpData->K.dataLenInBytes, -+ &randData); -+ -+ doCheck = 0; -+ while (icp_ocfDrvCheckALessThanB(&(dsaRsSignOpData->K), -+ &(dsaRsSignOpData->Q), &doCheck)) { -+ -+ if (CPA_STATUS_SUCCESS -+ != cpaCyRandGen(CPA_INSTANCE_HANDLE_SINGLE, -+ NULL, NULL, &randGenOpData, &randData)) { -+ APRINTK("%s(): ERROR - Failed to generate DSA RS Sign K" -+ "value\n", __FUNCTION__); -+ icp_ocfDrvFreeFlatBuffer(pS); -+ icp_ocfDrvFreeFlatBuffer(pR); -+ ICP_CACHE_FREE(drvDSARSSignKValue_zone, -+ dsaRsSignOpData->K.pData); -+ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); -+ krp->krp_status = EAGAIN; -+ return EAGAIN; -+ } -+ -+ doCheck++; -+ if (DSA_SIGN_RAND_GEN_VAL_CHECK_MAX_ITERATIONS == doCheck) { -+ APRINTK("%s(): ERROR - Failed to find DSA RS Sign K " -+ "value less than Q value\n", __FUNCTION__); -+ icp_ocfDrvFreeFlatBuffer(pS); -+ icp_ocfDrvFreeFlatBuffer(pR); -+ ICP_CACHE_FREE(drvDSARSSignKValue_zone, -+ dsaRsSignOpData->K.pData); -+ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); -+ krp->krp_status = EAGAIN; -+ return EAGAIN; -+ } -+ -+ } -+ /*Rand Data - no need to swap bytes for pK */ -+ -+ /* Link parameters */ -+ dsaRsSignOpData->G.pData = -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_G_INDEX].crp_p; -+ BITS_TO_BYTES(dsaRsSignOpData->G.dataLenInBytes, -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_G_INDEX].crp_nbits); -+ -+ icp_ocfDrvSwapBytes(dsaRsSignOpData->G.pData, -+ dsaRsSignOpData->G.dataLenInBytes); -+ -+ dsaRsSignOpData->X.pData = -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_X_INDEX].crp_p; -+ BITS_TO_BYTES(dsaRsSignOpData->X.dataLenInBytes, -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_X_INDEX].crp_nbits); -+ icp_ocfDrvSwapBytes(dsaRsSignOpData->X.pData, -+ dsaRsSignOpData->X.dataLenInBytes); -+ -+ /*OpenSSL dgst parameter is left in big endian byte order, -+ therefore no byte swap is required */ -+ dsaRsSignOpData->M.pData = -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_DGST_INDEX].crp_p; -+ BITS_TO_BYTES(dsaRsSignOpData->M.dataLenInBytes, -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_DGST_INDEX]. -+ crp_nbits); -+ -+ /* Output Parameters */ -+ pS->pData = krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_S_RESULT_INDEX].crp_p; -+ BITS_TO_BYTES(pS->dataLenInBytes, -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_S_RESULT_INDEX]. -+ crp_nbits); -+ -+ pR->pData = krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_R_RESULT_INDEX].crp_p; -+ BITS_TO_BYTES(pR->dataLenInBytes, -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_R_RESULT_INDEX]. -+ crp_nbits); -+ -+ lacStatus = cpaCyDsaSignRS(CPA_INSTANCE_HANDLE_SINGLE, -+ icp_ocfDrvDsaRSSignCallBack, -+ callbackTag, dsaRsSignOpData, -+ &protocolStatus, pR, pS); -+ -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): DSA RS Sign Operation failed (%d).\n", -+ __FUNCTION__, lacStatus); -+ krp->krp_status = ECANCELED; -+ icp_ocfDrvFreeFlatBuffer(pS); -+ icp_ocfDrvFreeFlatBuffer(pR); -+ ICP_CACHE_FREE(drvDSARSSignKValue_zone, -+ dsaRsSignOpData->K.pData); -+ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); -+ } -+ -+ return lacStatus; -+} -+ -+/* Name : icp_ocfDrvDsaVerify -+ * -+ * Description : This function will map DSA RS Verify from OCF to the LAC API. -+ * -+ */ -+static int icp_ocfDrvDsaVerify(struct cryptkop *krp) -+{ -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ CpaCyDsaVerifyOpData *dsaVerifyOpData = NULL; -+ void *callbackTag = NULL; -+ CpaBoolean verifyStatus = CPA_FALSE; -+ -+ callbackTag = krp; -+ -+ dsaVerifyOpData = -+ icp_kmem_cache_zalloc(drvDSAVerify_zone, ICP_M_NOWAIT); -+ if (NULL == dsaVerifyOpData) { -+ APRINTK("%s():Failed to get memory" -+ " for DSA Verify Op data struct\n", __FUNCTION__); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ /* Link parameters */ -+ dsaVerifyOpData->P.pData = -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PRIME_P_INDEX].crp_p; -+ BITS_TO_BYTES(dsaVerifyOpData->P.dataLenInBytes, -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PRIME_P_INDEX]. -+ crp_nbits); -+ icp_ocfDrvSwapBytes(dsaVerifyOpData->P.pData, -+ dsaVerifyOpData->P.dataLenInBytes); -+ -+ dsaVerifyOpData->Q.pData = -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PRIME_Q_INDEX].crp_p; -+ BITS_TO_BYTES(dsaVerifyOpData->Q.dataLenInBytes, -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PRIME_Q_INDEX]. -+ crp_nbits); -+ icp_ocfDrvSwapBytes(dsaVerifyOpData->Q.pData, -+ dsaVerifyOpData->Q.dataLenInBytes); -+ -+ dsaVerifyOpData->G.pData = -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_G_INDEX].crp_p; -+ BITS_TO_BYTES(dsaVerifyOpData->G.dataLenInBytes, -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_G_INDEX]. -+ crp_nbits); -+ icp_ocfDrvSwapBytes(dsaVerifyOpData->G.pData, -+ dsaVerifyOpData->G.dataLenInBytes); -+ -+ dsaVerifyOpData->Y.pData = -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PUBKEY_INDEX].crp_p; -+ BITS_TO_BYTES(dsaVerifyOpData->Y.dataLenInBytes, -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PUBKEY_INDEX]. -+ crp_nbits); -+ icp_ocfDrvSwapBytes(dsaVerifyOpData->Y.pData, -+ dsaVerifyOpData->Y.dataLenInBytes); -+ -+ /*OpenSSL dgst parameter is left in big endian byte order, -+ therefore no byte swap is required */ -+ dsaVerifyOpData->M.pData = -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_DGST_INDEX].crp_p; -+ BITS_TO_BYTES(dsaVerifyOpData->M.dataLenInBytes, -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_DGST_INDEX]. -+ crp_nbits); -+ -+ dsaVerifyOpData->R.pData = -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_SIG_R_INDEX].crp_p; -+ BITS_TO_BYTES(dsaVerifyOpData->R.dataLenInBytes, -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_SIG_R_INDEX]. -+ crp_nbits); -+ icp_ocfDrvSwapBytes(dsaVerifyOpData->R.pData, -+ dsaVerifyOpData->R.dataLenInBytes); -+ -+ dsaVerifyOpData->S.pData = -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_SIG_S_INDEX].crp_p; -+ BITS_TO_BYTES(dsaVerifyOpData->S.dataLenInBytes, -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_SIG_S_INDEX]. -+ crp_nbits); -+ icp_ocfDrvSwapBytes(dsaVerifyOpData->S.pData, -+ dsaVerifyOpData->S.dataLenInBytes); -+ -+ lacStatus = cpaCyDsaVerify(CPA_INSTANCE_HANDLE_SINGLE, -+ icp_ocfDrvDsaVerifyCallBack, -+ callbackTag, dsaVerifyOpData, &verifyStatus); -+ -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): DSA Verify Operation failed (%d).\n", -+ __FUNCTION__, lacStatus); -+ ICP_CACHE_FREE(drvDSAVerify_zone, dsaVerifyOpData); -+ krp->krp_status = ECANCELED; -+ } -+ -+ return lacStatus; -+} -+ -+/* Name : icp_ocfDrvDhP1Callback -+ * -+ * Description : When this function returns it signifies that the LAC -+ * component has completed the DH operation. -+ */ -+static void -+icp_ocfDrvDhP1CallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, CpaFlatBuffer * pLocalOctetStringPV) -+{ -+ struct cryptkop *krp = NULL; -+ CpaCyDhPhase1KeyGenOpData *pPhase1OpData = NULL; -+ -+ if (NULL == callbackTag) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "callbackTag data is NULL\n", __FUNCTION__); -+ return; -+ } -+ krp = (struct cryptkop *)callbackTag; -+ -+ if (NULL == pOpData) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "Operation Data is NULL\n", __FUNCTION__); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ pPhase1OpData = (CpaCyDhPhase1KeyGenOpData *) pOpData; -+ -+ if (NULL == pLocalOctetStringPV) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "pLocalOctetStringPV Data is NULL\n", __FUNCTION__); -+ memset(pPhase1OpData, 0, sizeof(CpaCyDhPhase1KeyGenOpData)); -+ ICP_CACHE_FREE(drvDH_zone, pPhase1OpData); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ -+ if (CPA_STATUS_SUCCESS == status) { -+ krp->krp_status = CRYPTO_OP_SUCCESS; -+ } else { -+ APRINTK("%s(): Diffie Hellman Phase1 Key Gen failed - " -+ "Operation Status = %d\n", __FUNCTION__, status); -+ krp->krp_status = ECANCELED; -+ } -+ -+ icp_ocfDrvSwapBytes(pLocalOctetStringPV->pData, -+ pLocalOctetStringPV->dataLenInBytes); -+ -+ icp_ocfDrvFreeFlatBuffer(pLocalOctetStringPV); -+ memset(pPhase1OpData, 0, sizeof(CpaCyDhPhase1KeyGenOpData)); -+ ICP_CACHE_FREE(drvDH_zone, pPhase1OpData); -+ -+ crypto_kdone(krp); -+ -+ return; -+} -+ -+/* Name : icp_ocfDrvModExpCallBack -+ * -+ * Description : When this function returns it signifies that the LAC -+ * component has completed the Mod Exp operation. -+ */ -+static void -+icp_ocfDrvModExpCallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpdata, CpaFlatBuffer * pResult) -+{ -+ struct cryptkop *krp = NULL; -+ CpaCyLnModExpOpData *pLnModExpOpData = NULL; -+ -+ if (NULL == callbackTag) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "callbackTag data is NULL\n", __FUNCTION__); -+ return; -+ } -+ krp = (struct cryptkop *)callbackTag; -+ -+ if (NULL == pOpdata) { -+ DPRINTK("%s(): Invalid Mod Exp input parameters - " -+ "Operation Data is NULL\n", __FUNCTION__); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ pLnModExpOpData = (CpaCyLnModExpOpData *) pOpdata; -+ -+ if (NULL == pResult) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "pResult data is NULL\n", __FUNCTION__); -+ krp->krp_status = ECANCELED; -+ memset(pLnModExpOpData, 0, sizeof(CpaCyLnModExpOpData)); -+ ICP_CACHE_FREE(drvLnModExp_zone, pLnModExpOpData); -+ crypto_kdone(krp); -+ return; -+ } -+ -+ if (CPA_STATUS_SUCCESS == status) { -+ krp->krp_status = CRYPTO_OP_SUCCESS; -+ } else { -+ APRINTK("%s(): LAC Mod Exp Operation failed - " -+ "Operation Status = %d\n", __FUNCTION__, status); -+ krp->krp_status = ECANCELED; -+ } -+ -+ icp_ocfDrvSwapBytes(pResult->pData, pResult->dataLenInBytes); -+ -+ /*switch base size value back to original */ -+ if (pLnModExpOpData->base.pData == -+ (uint8_t *) & (krp-> -+ krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX]. -+ crp_nbits)) { -+ *((uint32_t *) pLnModExpOpData->base.pData) = -+ ntohl(*((uint32_t *) pLnModExpOpData->base.pData)); -+ } -+ icp_ocfDrvFreeFlatBuffer(pResult); -+ memset(pLnModExpOpData, 0, sizeof(CpaCyLnModExpOpData)); -+ ICP_CACHE_FREE(drvLnModExp_zone, pLnModExpOpData); -+ -+ crypto_kdone(krp); -+ -+ return; -+ -+} -+ -+/* Name : icp_ocfDrvModExpCRTCallBack -+ * -+ * Description : When this function returns it signifies that the LAC -+ * component has completed the Mod Exp CRT operation. -+ */ -+static void -+icp_ocfDrvModExpCRTCallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, CpaFlatBuffer * pOutputData) -+{ -+ struct cryptkop *krp = NULL; -+ CpaCyRsaDecryptOpData *pDecryptData = NULL; -+ -+ if (NULL == callbackTag) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "callbackTag data is NULL\n", __FUNCTION__); -+ return; -+ } -+ -+ krp = (struct cryptkop *)callbackTag; -+ -+ if (NULL == pOpData) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "Operation Data is NULL\n", __FUNCTION__); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ pDecryptData = (CpaCyRsaDecryptOpData *) pOpData; -+ -+ if (NULL == pOutputData) { -+ DPRINTK("%s(): Invalid input parameter - " -+ "pOutputData is NULL\n", __FUNCTION__); -+ memset(pDecryptData->pRecipientPrivateKey, 0, -+ sizeof(CpaCyRsaPrivateKey)); -+ ICP_CACHE_FREE(drvRSAPrivateKey_zone, -+ pDecryptData->pRecipientPrivateKey); -+ memset(pDecryptData, 0, sizeof(CpaCyRsaDecryptOpData)); -+ ICP_CACHE_FREE(drvRSADecrypt_zone, pDecryptData); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ -+ if (CPA_STATUS_SUCCESS == status) { -+ krp->krp_status = CRYPTO_OP_SUCCESS; -+ } else { -+ APRINTK("%s(): LAC Mod Exp CRT operation failed - " -+ "Operation Status = %d\n", __FUNCTION__, status); -+ krp->krp_status = ECANCELED; -+ } -+ -+ icp_ocfDrvSwapBytes(pOutputData->pData, pOutputData->dataLenInBytes); -+ -+ icp_ocfDrvFreeFlatBuffer(pOutputData); -+ memset(pDecryptData->pRecipientPrivateKey, 0, -+ sizeof(CpaCyRsaPrivateKey)); -+ ICP_CACHE_FREE(drvRSAPrivateKey_zone, -+ pDecryptData->pRecipientPrivateKey); -+ memset(pDecryptData, 0, sizeof(CpaCyRsaDecryptOpData)); -+ ICP_CACHE_FREE(drvRSADecrypt_zone, pDecryptData); -+ -+ crypto_kdone(krp); -+ -+ return; -+} -+ -+/* Name : icp_ocfDrvDsaRSSignCallBack -+ * -+ * Description : When this function returns it signifies that the LAC -+ * component has completed the DSA RS sign operation. -+ */ -+static void -+icp_ocfDrvDsaRSSignCallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, -+ CpaBoolean protocolStatus, -+ CpaFlatBuffer * pR, CpaFlatBuffer * pS) -+{ -+ struct cryptkop *krp = NULL; -+ CpaCyDsaRSSignOpData *pSignData = NULL; -+ -+ if (NULL == callbackTag) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "callbackTag data is NULL\n", __FUNCTION__); -+ return; -+ } -+ -+ krp = (struct cryptkop *)callbackTag; -+ -+ if (NULL == pOpData) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "Operation Data is NULL\n", __FUNCTION__); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ pSignData = (CpaCyDsaRSSignOpData *) pOpData; -+ -+ if (NULL == pR) { -+ DPRINTK("%s(): Invalid input parameter - " -+ "pR sign is NULL\n", __FUNCTION__); -+ icp_ocfDrvFreeFlatBuffer(pS); -+ ICP_CACHE_FREE(drvDSARSSign_zone, pSignData); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ -+ if (NULL == pS) { -+ DPRINTK("%s(): Invalid input parameter - " -+ "pS sign is NULL\n", __FUNCTION__); -+ icp_ocfDrvFreeFlatBuffer(pR); -+ ICP_CACHE_FREE(drvDSARSSign_zone, pSignData); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ -+ if (CPA_STATUS_SUCCESS != status) { -+ APRINTK("%s(): LAC DSA RS Sign operation failed - " -+ "Operation Status = %d\n", __FUNCTION__, status); -+ krp->krp_status = ECANCELED; -+ } else { -+ krp->krp_status = CRYPTO_OP_SUCCESS; -+ -+ if (CPA_TRUE != protocolStatus) { -+ DPRINTK("%s(): LAC DSA RS Sign operation failed due " -+ "to protocol error\n", __FUNCTION__); -+ krp->krp_status = EIO; -+ } -+ } -+ -+ /* Swap bytes only when the callback status is successful and -+ protocolStatus is set to true */ -+ if (CPA_STATUS_SUCCESS == status && CPA_TRUE == protocolStatus) { -+ icp_ocfDrvSwapBytes(pR->pData, pR->dataLenInBytes); -+ icp_ocfDrvSwapBytes(pS->pData, pS->dataLenInBytes); -+ } -+ -+ icp_ocfDrvFreeFlatBuffer(pR); -+ icp_ocfDrvFreeFlatBuffer(pS); -+ memset(pSignData->K.pData, 0, pSignData->K.dataLenInBytes); -+ ICP_CACHE_FREE(drvDSARSSignKValue_zone, pSignData->K.pData); -+ memset(pSignData, 0, sizeof(CpaCyDsaRSSignOpData)); -+ ICP_CACHE_FREE(drvDSARSSign_zone, pSignData); -+ crypto_kdone(krp); -+ -+ return; -+} -+ -+/* Name : icp_ocfDrvDsaVerifyCallback -+ * -+ * Description : When this function returns it signifies that the LAC -+ * component has completed the DSA Verify operation. -+ */ -+static void -+icp_ocfDrvDsaVerifyCallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, CpaBoolean verifyStatus) -+{ -+ -+ struct cryptkop *krp = NULL; -+ CpaCyDsaVerifyOpData *pVerData = NULL; -+ -+ if (NULL == callbackTag) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "callbackTag data is NULL\n", __FUNCTION__); -+ return; -+ } -+ -+ krp = (struct cryptkop *)callbackTag; -+ -+ if (NULL == pOpData) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "Operation Data is NULL\n", __FUNCTION__); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ pVerData = (CpaCyDsaVerifyOpData *) pOpData; -+ -+ if (CPA_STATUS_SUCCESS != status) { -+ APRINTK("%s(): LAC DSA Verify operation failed - " -+ "Operation Status = %d\n", __FUNCTION__, status); -+ krp->krp_status = ECANCELED; -+ } else { -+ krp->krp_status = CRYPTO_OP_SUCCESS; -+ -+ if (CPA_TRUE != verifyStatus) { -+ DPRINTK("%s(): DSA signature invalid\n", __FUNCTION__); -+ krp->krp_status = EIO; -+ } -+ } -+ -+ /* Swap bytes only when the callback status is successful and -+ verifyStatus is set to true */ -+ /*Just swapping back the key values for now. Possibly all -+ swapped buffers need to be reverted */ -+ if (CPA_STATUS_SUCCESS == status && CPA_TRUE == verifyStatus) { -+ icp_ocfDrvSwapBytes(pVerData->R.pData, -+ pVerData->R.dataLenInBytes); -+ icp_ocfDrvSwapBytes(pVerData->S.pData, -+ pVerData->S.dataLenInBytes); -+ } -+ -+ memset(pVerData, 0, sizeof(CpaCyDsaVerifyOpData)); -+ ICP_CACHE_FREE(drvDSAVerify_zone, pVerData); -+ crypto_kdone(krp); -+ -+ return; -+} -diff -Nur linux-2.6.36.orig/crypto/ocf/ep80579/icp_common.c linux-2.6.36/crypto/ocf/ep80579/icp_common.c ---- linux-2.6.36.orig/crypto/ocf/ep80579/icp_common.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/ep80579/icp_common.c 2010-11-09 20:28:04.612495446 +0100 -@@ -0,0 +1,773 @@ -+/************************************************************************* -+ * -+ * This file is provided under a dual BSD/GPLv2 license. When using or -+ * redistributing this file, you may do so under either license. -+ * -+ * GPL LICENSE SUMMARY -+ * -+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of version 2 of the GNU General Public License as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. -+ * The full GNU General Public License is included in this distribution -+ * in the file called LICENSE.GPL. -+ * -+ * Contact Information: -+ * Intel Corporation -+ * -+ * BSD LICENSE -+ * -+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * * Neither the name of Intel Corporation nor the names of its -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * -+ * version: Security.L.1.0.2-229 -+ * -+ ***************************************************************************/ -+ -+/* -+ * An OCF module that uses Intel® QuickAssist Integrated Accelerator to do the -+ * crypto. -+ * -+ * This driver requires the ICP Access Library that is available from Intel in -+ * order to operate. -+ */ -+ -+#include "icp_ocf.h" -+ -+#define ICP_OCF_COMP_NAME "ICP_OCF" -+#define ICP_OCF_VER_MAIN (2) -+#define ICP_OCF_VER_MJR (1) -+#define ICP_OCF_VER_MNR (0) -+ -+#define MAX_DEREG_RETRIES (100) -+#define DEFAULT_DEREG_RETRIES (10) -+#define DEFAULT_DEREG_DELAY_IN_JIFFIES (10) -+ -+/* This defines the maximum number of sessions possible between OCF -+ and the OCF EP80579 Driver. If set to zero, there is no limit. */ -+#define DEFAULT_OCF_TO_DRV_MAX_SESSION_COUNT (0) -+#define NUM_SUPPORTED_CAPABILITIES (21) -+ -+/*Slab zone names*/ -+#define ICP_SESSION_DATA_NAME "icp_ocf.SesDat" -+#define ICP_OP_DATA_NAME "icp_ocf.OpDat" -+#define ICP_DH_NAME "icp_ocf.DH" -+#define ICP_MODEXP_NAME "icp_ocf.ModExp" -+#define ICP_RSA_DECRYPT_NAME "icp_ocf.RSAdec" -+#define ICP_RSA_PKEY_NAME "icp_ocf.RSApk" -+#define ICP_DSA_SIGN_NAME "icp_ocf.DSAsg" -+#define ICP_DSA_VER_NAME "icp_ocf.DSAver" -+#define ICP_RAND_VAL_NAME "icp_ocf.DSArnd" -+#define ICP_FLAT_BUFF_NAME "icp_ocf.FB" -+ -+/*Slabs zones*/ -+icp_kmem_cache drvSessionData_zone = NULL; -+icp_kmem_cache drvOpData_zone = NULL; -+icp_kmem_cache drvDH_zone = NULL; -+icp_kmem_cache drvLnModExp_zone = NULL; -+icp_kmem_cache drvRSADecrypt_zone = NULL; -+icp_kmem_cache drvRSAPrivateKey_zone = NULL; -+icp_kmem_cache drvDSARSSign_zone = NULL; -+icp_kmem_cache drvDSARSSignKValue_zone = NULL; -+icp_kmem_cache drvDSAVerify_zone = NULL; -+ -+/*Slab zones for flatbuffers and bufferlist*/ -+icp_kmem_cache drvFlatBuffer_zone = NULL; -+ -+static inline int icp_cache_null_check(void) -+{ -+ return (drvSessionData_zone && drvOpData_zone -+ && drvDH_zone && drvLnModExp_zone && drvRSADecrypt_zone -+ && drvRSAPrivateKey_zone && drvDSARSSign_zone -+ && drvDSARSSign_zone && drvDSARSSignKValue_zone -+ && drvDSAVerify_zone && drvFlatBuffer_zone); -+} -+ -+/*Function to free all allocated slab caches before exiting the module*/ -+static void icp_ocfDrvFreeCaches(void); -+ -+int32_t icp_ocfDrvDriverId = INVALID_DRIVER_ID; -+ -+/* Module parameter - gives the number of times LAC deregistration shall be -+ re-tried */ -+int num_dereg_retries = DEFAULT_DEREG_RETRIES; -+ -+/* Module parameter - gives the delay time in jiffies before a LAC session -+ shall be attempted to be deregistered again */ -+int dereg_retry_delay_in_jiffies = DEFAULT_DEREG_DELAY_IN_JIFFIES; -+ -+/* Module parameter - gives the maximum number of sessions possible between -+ OCF and the OCF EP80579 Driver. If set to zero, there is no limit.*/ -+int max_sessions = DEFAULT_OCF_TO_DRV_MAX_SESSION_COUNT; -+ -+/* This is set when the module is removed from the system, no further -+ processing can take place if this is set */ -+icp_atomic_t icp_ocfDrvIsExiting = ICP_ATOMIC_INIT(0); -+ -+/* This is used to show how many lac sessions were not deregistered*/ -+icp_atomic_t lac_session_failed_dereg_count = ICP_ATOMIC_INIT(0); -+ -+/* This is used to track the number of registered sessions between OCF and -+ * and the OCF EP80579 driver, when max_session is set to value other than -+ * zero. This ensures that the max_session set for the OCF and the driver -+ * is equal to the LAC registered sessions */ -+icp_atomic_t num_ocf_to_drv_registered_sessions = ICP_ATOMIC_INIT(0); -+ -+/* Head of linked list used to store session data */ -+icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead; -+icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead_FreeMemList; -+ -+icp_spinlock_t icp_ocfDrvSymSessInfoListSpinlock; -+ -+/*Below pointer is only used in linux, FreeBSD uses the name to -+create its own variable name*/ -+icp_workqueue *icp_ocfDrvFreeLacSessionWorkQ = NULL; -+ICP_WORKQUEUE_DEFINE_THREAD(icp_ocfDrvFreeLacSessionWorkQ); -+ -+struct icp_drvBuffListInfo defBuffListInfo; -+ -+/* Name : icp_ocfDrvInit -+ * -+ * Description : This function will register all the symmetric and asymmetric -+ * functionality that will be accelerated by the hardware. It will also -+ * get a unique driver ID from the OCF and initialise all slab caches -+ */ -+ICP_MODULE_INIT_FUNC(icp_ocfDrvInit) -+{ -+ int ocfStatus = 0; -+ -+ IPRINTK("=== %s ver %d.%d.%d ===\n", ICP_OCF_COMP_NAME, -+ ICP_OCF_VER_MAIN, ICP_OCF_VER_MJR, ICP_OCF_VER_MNR); -+ -+ if (MAX_DEREG_RETRIES < num_dereg_retries) { -+ EPRINTK("Session deregistration retry count set to greater " -+ "than %d", MAX_DEREG_RETRIES); -+ icp_module_return_code(EINVAL); -+ } -+ -+ /* Initialize and Start the Cryptographic component */ -+ if (CPA_STATUS_SUCCESS != -+ cpaCyStartInstance(CPA_INSTANCE_HANDLE_SINGLE)) { -+ EPRINTK("Failed to initialize and start the instance " -+ "of the Cryptographic component.\n"); -+ return icp_module_return_code(EINVAL); -+ } -+ -+ icp_spin_lock_init(&icp_ocfDrvSymSessInfoListSpinlock); -+ -+ /* Set the default size of BufferList to allocate */ -+ memset(&defBuffListInfo, 0, sizeof(struct icp_drvBuffListInfo)); -+ if (ICP_OCF_DRV_STATUS_SUCCESS != -+ icp_ocfDrvBufferListMemInfo(ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS, -+ &defBuffListInfo)) { -+ EPRINTK("Failed to get bufferlist memory info.\n"); -+ return icp_module_return_code(ENOMEM); -+ } -+ -+ /*Register OCF EP80579 Driver with OCF */ -+ icp_ocfDrvDriverId = ICP_CRYPTO_GET_DRIVERID(); -+ -+ if (icp_ocfDrvDriverId < 0) { -+ EPRINTK("%s : ICP driver failed to register with OCF!\n", -+ __FUNCTION__); -+ return icp_module_return_code(ENODEV); -+ } -+ -+ /*Create all the slab caches used by the OCF EP80579 Driver */ -+ drvSessionData_zone = -+ ICP_CACHE_CREATE(ICP_SESSION_DATA_NAME, struct icp_drvSessionData); -+ -+ /* -+ * Allocation of the OpData includes the allocation space for meta data. -+ * The memory after the opData structure is reserved for this meta data. -+ */ -+ drvOpData_zone = -+ icp_kmem_cache_create(ICP_OP_DATA_NAME, -+ sizeof(struct icp_drvOpData) + -+ defBuffListInfo.metaSize, -+ ICP_KERNEL_CACHE_ALIGN, -+ ICP_KERNEL_CACHE_NOINIT); -+ -+ drvDH_zone = ICP_CACHE_CREATE(ICP_DH_NAME, CpaCyDhPhase1KeyGenOpData); -+ -+ drvLnModExp_zone = -+ ICP_CACHE_CREATE(ICP_MODEXP_NAME, CpaCyLnModExpOpData); -+ -+ drvRSADecrypt_zone = -+ ICP_CACHE_CREATE(ICP_RSA_DECRYPT_NAME, CpaCyRsaDecryptOpData); -+ -+ drvRSAPrivateKey_zone = -+ ICP_CACHE_CREATE(ICP_RSA_PKEY_NAME, CpaCyRsaPrivateKey); -+ -+ drvDSARSSign_zone = -+ ICP_CACHE_CREATE(ICP_DSA_SIGN_NAME, CpaCyDsaRSSignOpData); -+ -+ /*too awkward to use a macro here */ -+ drvDSARSSignKValue_zone = -+ ICP_CACHE_CREATE(ICP_RAND_VAL_NAME, -+ DSA_RS_SIGN_PRIMEQ_SIZE_IN_BYTES); -+ -+ drvDSAVerify_zone = -+ ICP_CACHE_CREATE(ICP_DSA_VER_NAME, CpaCyDsaVerifyOpData); -+ -+ drvFlatBuffer_zone = -+ ICP_CACHE_CREATE(ICP_FLAT_BUFF_NAME, CpaFlatBuffer); -+ -+ if (0 == icp_cache_null_check()) { -+ icp_ocfDrvFreeCaches(); -+ EPRINTK("%s() line %d: Not enough memory!\n", -+ __FUNCTION__, __LINE__); -+ return ENOMEM; -+ } -+ -+ /* Register the ICP symmetric crypto support. */ -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_NULL_CBC, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_DES_CBC, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_3DES_CBC, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_AES_CBC, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_ARC4, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_MD5, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_MD5_HMAC, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA1, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA1_HMAC, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_256, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_256_HMAC, -+ ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_384, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_384_HMAC, -+ ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_512, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_512_HMAC, -+ ocfStatus); -+ -+ /* Register the ICP asymmetric algorithm support */ -+ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_DH_COMPUTE_KEY, -+ ocfStatus); -+ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_MOD_EXP, ocfStatus); -+ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_MOD_EXP_CRT, ocfStatus); -+ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_DSA_SIGN, ocfStatus); -+ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_DSA_VERIFY, ocfStatus); -+ -+ /* Register the ICP random number generator support */ -+ ICP_REG_RAND_WITH_OCF(icp_ocfDrvDriverId, -+ icp_ocfDrvReadRandom, NULL, ocfStatus); -+ -+ if (OCF_ZERO_FUNCTIONALITY_REGISTERED == ocfStatus) { -+ DPRINTK("%s: Failed to register any device capabilities\n", -+ __FUNCTION__); -+ icp_ocfDrvFreeCaches(); -+ icp_ocfDrvDriverId = INVALID_DRIVER_ID; -+ return icp_module_return_code(ECANCELED); -+ } -+ -+ DPRINTK("%s: Registered %d of %d device capabilities\n", -+ __FUNCTION__, ocfStatus, NUM_SUPPORTED_CAPABILITIES); -+ -+ /*Session data linked list used during module exit */ -+ ICP_INIT_LIST_HEAD(&icp_ocfDrvGlobalSymListHead); -+ ICP_INIT_LIST_HEAD(&icp_ocfDrvGlobalSymListHead_FreeMemList); -+ -+ ICP_WORKQUEUE_CREATE(icp_ocfDrvFreeLacSessionWorkQ, "icpwq"); -+ if (ICP_WORKQUEUE_NULL_CHECK(icp_ocfDrvFreeLacSessionWorkQ)) { -+ EPRINTK("%s: Failed to create single " -+ "thread workqueue\n", __FUNCTION__); -+ icp_ocfDrvFreeCaches(); -+ icp_ocfDrvDriverId = INVALID_DRIVER_ID; -+ return icp_module_return_code(ENOMEM); -+ } -+ -+ return icp_module_return_code(0); -+} -+ -+/* Name : icp_ocfDrvExit -+ * -+ * Description : This function will deregister all the symmetric sessions -+ * registered with the LAC component. It will also deregister all symmetric -+ * and asymmetric functionality that can be accelerated by the hardware via OCF -+ * and random number generation if it is enabled. -+ */ -+ICP_MODULE_EXIT_FUNC(icp_ocfDrvExit) -+{ -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ struct icp_drvSessionData *sessionData = NULL; -+ struct icp_drvSessionData *tempSessionData = NULL; -+ int i, remaining_delay_time_in_jiffies = 0; -+ -+ /* For FreeBSD the invariant macro below makes function to return */ -+ /* with EBUSY value in the case of any session which has been regi- */ -+ /* stered with LAC not being deregistered. */ -+ /* The Linux implementation is empty since it is purely to compensate */ -+ /* for a limitation of the FreeBSD 7.1 Opencrypto framework. */ -+ -+ ICP_MODULE_EXIT_INV(); -+ -+ /* There is a possibility of a process or new session command being */ -+ /* sent before this variable is incremented. The aim of this variable */ -+ /* is to stop a loop of calls creating a deadlock situation which */ -+ /* would prevent the driver from exiting. */ -+ icp_atomic_set(&icp_ocfDrvIsExiting, 1); -+ -+ /*Existing sessions will be routed to another driver after these calls */ -+ crypto_unregister_all(icp_ocfDrvDriverId); -+ crypto_runregister_all(icp_ocfDrvDriverId); -+ -+ if (ICP_WORKQUEUE_NULL_CHECK(icp_ocfDrvFreeLacSessionWorkQ)) { -+ DPRINTK("%s: workqueue already " -+ "destroyed, therefore module exit " -+ " function already called. Exiting.\n", __FUNCTION__); -+ return ICP_MODULE_EXIT_FUNC_RETURN_VAL; -+ } -+ /*If any sessions are waiting to be deregistered, do that. This also -+ flushes the work queue */ -+ ICP_WORKQUEUE_DESTROY(icp_ocfDrvFreeLacSessionWorkQ); -+ -+ /*ENTER CRITICAL SECTION */ -+ icp_spin_lockbh_lock(&icp_ocfDrvSymSessInfoListSpinlock); -+ -+ ICP_LIST_FOR_EACH_ENTRY_SAFE(tempSessionData, sessionData, -+ &icp_ocfDrvGlobalSymListHead, listNode) { -+ for (i = 0; i < num_dereg_retries; i++) { -+ /*No harm if bad input - LAC will handle error cases */ -+ if (ICP_SESSION_RUNNING == tempSessionData->inUse) { -+ lacStatus = -+ cpaCySymRemoveSession -+ (CPA_INSTANCE_HANDLE_SINGLE, -+ tempSessionData->sessHandle); -+ if (CPA_STATUS_SUCCESS == lacStatus) { -+ /* Succesfully deregistered */ -+ break; -+ } else if (CPA_STATUS_RETRY != lacStatus) { -+ icp_atomic_inc -+ (&lac_session_failed_dereg_count); -+ break; -+ } -+ -+ /*schedule_timout returns the time left for completion if -+ * this task is set to TASK_INTERRUPTIBLE */ -+ remaining_delay_time_in_jiffies = -+ dereg_retry_delay_in_jiffies; -+ while (0 > remaining_delay_time_in_jiffies) { -+ remaining_delay_time_in_jiffies = -+ icp_schedule_timeout -+ (&icp_ocfDrvSymSessInfoListSpinlock, -+ remaining_delay_time_in_jiffies); -+ } -+ -+ DPRINTK -+ ("%s(): Retry %d to deregistrate the session\n", -+ __FUNCTION__, i); -+ } -+ } -+ -+ /*remove from current list */ -+ ICP_LIST_DEL(tempSessionData, listNode); -+ /*add to free mem linked list */ -+ ICP_LIST_ADD(tempSessionData, -+ &icp_ocfDrvGlobalSymListHead_FreeMemList, -+ listNode); -+ -+ } -+ -+ /*EXIT CRITICAL SECTION */ -+ icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock); -+ -+ /*set back to initial values */ -+ sessionData = NULL; -+ /*still have a reference in our list! */ -+ tempSessionData = NULL; -+ /*free memory */ -+ -+ ICP_LIST_FOR_EACH_ENTRY_SAFE(tempSessionData, sessionData, -+ &icp_ocfDrvGlobalSymListHead_FreeMemList, -+ listNode) { -+ -+ ICP_LIST_DEL(tempSessionData, listNode); -+ /* Free allocated CpaCySymSessionCtx */ -+ if (NULL != tempSessionData->sessHandle) { -+ icp_kfree(tempSessionData->sessHandle); -+ } -+ memset(tempSessionData, 0, sizeof(struct icp_drvSessionData)); -+ ICP_CACHE_FREE(drvSessionData_zone, tempSessionData); -+ } -+ -+ if (0 != icp_atomic_read(&lac_session_failed_dereg_count)) { -+ DPRINTK("%s(): %d LAC sessions were not deregistered " -+ "correctly. This is not a clean exit! \n", -+ __FUNCTION__, -+ icp_atomic_read(&lac_session_failed_dereg_count)); -+ } -+ -+ icp_ocfDrvFreeCaches(); -+ icp_ocfDrvDriverId = INVALID_DRIVER_ID; -+ -+ icp_spin_lock_destroy(&icp_ocfDrvSymSessInfoListSpinlock); -+ -+ /* Shutdown the Cryptographic component */ -+ lacStatus = cpaCyStopInstance(CPA_INSTANCE_HANDLE_SINGLE); -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ DPRINTK("%s(): Failed to stop instance of the " -+ "Cryptographic component.(status == %d)\n", -+ __FUNCTION__, lacStatus); -+ } -+ -+ return ICP_MODULE_EXIT_FUNC_RETURN_VAL; -+} -+ -+/* Name : icp_ocfDrvFreeCaches -+ * -+ * Description : This function deregisters all slab caches -+ */ -+static void icp_ocfDrvFreeCaches(void) -+{ -+ icp_atomic_set(&icp_ocfDrvIsExiting, 1); -+ -+ /*Sym Zones */ -+ ICP_CACHE_DESTROY(drvSessionData_zone); -+ ICP_CACHE_DESTROY(drvOpData_zone); -+ -+ /*Asym zones */ -+ ICP_CACHE_DESTROY(drvDH_zone); -+ ICP_CACHE_DESTROY(drvLnModExp_zone); -+ ICP_CACHE_DESTROY(drvRSADecrypt_zone); -+ ICP_CACHE_DESTROY(drvRSAPrivateKey_zone); -+ ICP_CACHE_DESTROY(drvDSARSSignKValue_zone); -+ ICP_CACHE_DESTROY(drvDSARSSign_zone); -+ ICP_CACHE_DESTROY(drvDSAVerify_zone); -+ -+ /*FlatBuffer and BufferList Zones */ -+ ICP_CACHE_DESTROY(drvFlatBuffer_zone); -+ -+} -+ -+/* Name : icp_ocfDrvDeregRetry -+ * -+ * Description : This function will try to farm the session deregistration -+ * off to a work queue. If it fails, nothing more can be done and it -+ * returns an error -+ */ -+int icp_ocfDrvDeregRetry(CpaCySymSessionCtx sessionToDeregister) -+{ -+ struct icp_ocfDrvFreeLacSession *workstore = NULL; -+ -+ DPRINTK("%s(): Retry - Deregistering session (%p)\n", -+ __FUNCTION__, sessionToDeregister); -+ -+ /*make sure the session is not available to be allocated during this -+ process */ -+ icp_atomic_inc(&lac_session_failed_dereg_count); -+ -+ /*Farm off to work queue */ -+ workstore = -+ icp_kmalloc(sizeof(struct icp_ocfDrvFreeLacSession), ICP_M_NOWAIT); -+ if (NULL == workstore) { -+ DPRINTK("%s(): unable to free session - no memory available " -+ "for work queue\n", __FUNCTION__); -+ return ENOMEM; -+ } -+ -+ workstore->sessionToDeregister = sessionToDeregister; -+ -+ icp_init_work(&(workstore->work), -+ icp_ocfDrvDeferedFreeLacSessionTaskFn, workstore); -+ -+ ICP_WORKQUEUE_ENQUEUE(icp_ocfDrvFreeLacSessionWorkQ, -+ &(workstore->work)); -+ -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+ -+} -+ -+/* Name : icp_ocfDrvDeferedFreeLacSessionProcess -+ * -+ * Description : This function will retry (module input parameter) -+ * 'num_dereg_retries' times to deregister any symmetric session that recieves a -+ * CPA_STATUS_RETRY message from the LAC component. This function is run in -+ * Thread context because it is called from a worker thread -+ */ -+void icp_ocfDrvDeferedFreeLacSessionProcess(void *arg) -+{ -+ struct icp_ocfDrvFreeLacSession *workstore = NULL; -+ CpaCySymSessionCtx sessionToDeregister = NULL; -+ int i = 0; -+ int remaining_delay_time_in_jiffies = 0; -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ -+ workstore = (struct icp_ocfDrvFreeLacSession *)arg; -+ if (NULL == workstore) { -+ DPRINTK("%s() function called with null parameter \n", -+ __FUNCTION__); -+ return; -+ } -+ -+ sessionToDeregister = workstore->sessionToDeregister; -+ icp_kfree(workstore); -+ -+ /*if exiting, give deregistration one more blast only */ -+ if (icp_atomic_read(&icp_ocfDrvIsExiting) == CPA_TRUE) { -+ lacStatus = cpaCySymRemoveSession(CPA_INSTANCE_HANDLE_SINGLE, -+ sessionToDeregister); -+ -+ if (lacStatus != CPA_STATUS_SUCCESS) { -+ DPRINTK("%s() Failed to Dereg LAC session %p " -+ "during module exit\n", __FUNCTION__, -+ sessionToDeregister); -+ return; -+ } -+ -+ icp_atomic_dec(&lac_session_failed_dereg_count); -+ return; -+ } -+ -+ for (i = 0; i <= num_dereg_retries; i++) { -+ lacStatus = cpaCySymRemoveSession(CPA_INSTANCE_HANDLE_SINGLE, -+ sessionToDeregister); -+ -+ if (lacStatus == CPA_STATUS_SUCCESS) { -+ icp_atomic_dec(&lac_session_failed_dereg_count); -+ return; -+ } -+ if (lacStatus != CPA_STATUS_RETRY) { -+ DPRINTK("%s() Failed to deregister session - lacStatus " -+ " = %d", __FUNCTION__, lacStatus); -+ break; -+ } -+ -+ /*schedule_timout returns the time left for completion if this -+ task is set to TASK_INTERRUPTIBLE */ -+ remaining_delay_time_in_jiffies = dereg_retry_delay_in_jiffies; -+ while (0 < remaining_delay_time_in_jiffies) { -+ remaining_delay_time_in_jiffies = -+ icp_schedule_timeout(NULL, -+ remaining_delay_time_in_jiffies); -+ } -+ -+ } -+ -+ DPRINTK("%s(): Unable to deregister session\n", __FUNCTION__); -+ DPRINTK("%s(): Number of unavailable LAC sessions = %d\n", __FUNCTION__, -+ icp_atomic_read(&lac_session_failed_dereg_count)); -+} -+ -+/* Name : icp_ocfDrvPtrAndLenToFlatBuffer -+ * -+ * Description : This function converts a "pointer and length" buffer -+ * structure to Fredericksburg Flat Buffer (CpaFlatBuffer) format. -+ * -+ * This function assumes that the data passed in are valid. -+ */ -+inline void -+icp_ocfDrvPtrAndLenToFlatBuffer(void *pData, uint32_t len, -+ CpaFlatBuffer * pFlatBuffer) -+{ -+ pFlatBuffer->pData = pData; -+ pFlatBuffer->dataLenInBytes = len; -+} -+ -+/* Name : icp_ocfDrvPtrAndLenToBufferList -+ * -+ * Description : This function converts a "pointer and length" buffer -+ * structure to Fredericksburg Scatter/Gather Buffer (CpaBufferList) format. -+ * -+ * This function assumes that the data passed in are valid. -+ */ -+inline void -+icp_ocfDrvPtrAndLenToBufferList(void *pDataIn, uint32_t length, -+ CpaBufferList * pBufferList) -+{ -+ pBufferList->numBuffers = 1; -+ pBufferList->pBuffers->pData = pDataIn; -+ pBufferList->pBuffers->dataLenInBytes = length; -+} -+ -+/* Name : icp_ocfDrvBufferListToPtrAndLen -+ * -+ * Description : This function converts Fredericksburg Scatter/Gather Buffer -+ * (CpaBufferList) format to a "pointer and length" buffer structure. -+ * -+ * This function assumes that the data passed in are valid. -+ */ -+inline void -+icp_ocfDrvBufferListToPtrAndLen(CpaBufferList * pBufferList, -+ void **ppDataOut, uint32_t * pLength) -+{ -+ *ppDataOut = pBufferList->pBuffers->pData; -+ *pLength = pBufferList->pBuffers->dataLenInBytes; -+} -+ -+/* Name : icp_ocfDrvBufferListMemInfo -+ * -+ * Description : This function will set the number of flat buffers in -+ * bufferlist, the size of memory to allocate for the pPrivateMetaData -+ * member of the CpaBufferList. -+ */ -+int -+icp_ocfDrvBufferListMemInfo(uint16_t numBuffers, -+ struct icp_drvBuffListInfo *buffListInfo) -+{ -+ buffListInfo->numBuffers = numBuffers; -+ -+ if (CPA_STATUS_SUCCESS != -+ cpaCyBufferListGetMetaSize(CPA_INSTANCE_HANDLE_SINGLE, -+ buffListInfo->numBuffers, -+ &(buffListInfo->metaSize))) { -+ EPRINTK("%s() Failed to get buffer list meta size.\n", -+ __FUNCTION__); -+ return ICP_OCF_DRV_STATUS_FAIL; -+ } -+ -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+} -+ -+/* Name : icp_ocfDrvFreeFlatBuffer -+ * -+ * Description : This function will deallocate flat buffer. -+ */ -+inline void icp_ocfDrvFreeFlatBuffer(CpaFlatBuffer * pFlatBuffer) -+{ -+ if (pFlatBuffer != NULL) { -+ memset(pFlatBuffer, 0, sizeof(CpaFlatBuffer)); -+ ICP_CACHE_FREE(drvFlatBuffer_zone, pFlatBuffer); -+ } -+} -+ -+/* Name : icp_ocfDrvAllocMetaData -+ * -+ * Description : This function will allocate memory for the -+ * pPrivateMetaData member of CpaBufferList. -+ */ -+inline int -+icp_ocfDrvAllocMetaData(CpaBufferList * pBufferList, -+ struct icp_drvOpData *pOpData) -+{ -+ Cpa32U metaSize = 0; -+ -+ if (pBufferList->numBuffers <= ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) { -+ uint8_t *pOpDataStartAddr = (uint8_t *) pOpData; -+ -+ if (0 == defBuffListInfo.metaSize) { -+ pBufferList->pPrivateMetaData = NULL; -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+ } -+ /* -+ * The meta data allocation has been included as part of the -+ * op data. It has been pre-allocated in memory just after the -+ * icp_drvOpData structure. -+ */ -+ pBufferList->pPrivateMetaData = (void *)(pOpDataStartAddr + -+ sizeof(struct -+ icp_drvOpData)); -+ } else { -+ if (CPA_STATUS_SUCCESS != -+ cpaCyBufferListGetMetaSize(CPA_INSTANCE_HANDLE_SINGLE, -+ pBufferList->numBuffers, -+ &metaSize)) { -+ EPRINTK("%s() Failed to get buffer list meta size.\n", -+ __FUNCTION__); -+ return ICP_OCF_DRV_STATUS_FAIL; -+ } -+ -+ if (0 == metaSize) { -+ pBufferList->pPrivateMetaData = NULL; -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+ } -+ -+ pBufferList->pPrivateMetaData = -+ icp_kmalloc(metaSize, ICP_M_NOWAIT); -+ } -+ if (NULL == pBufferList->pPrivateMetaData) { -+ EPRINTK("%s() Failed to allocate pPrivateMetaData.\n", -+ __FUNCTION__); -+ return ICP_OCF_DRV_STATUS_FAIL; -+ } -+ -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+} -+ -+/* Name : icp_ocfDrvFreeMetaData -+ * -+ * Description : This function will deallocate pPrivateMetaData memory. -+ */ -+inline void icp_ocfDrvFreeMetaData(CpaBufferList * pBufferList) -+{ -+ if (NULL == pBufferList->pPrivateMetaData) { -+ return; -+ } -+ -+ /* -+ * Only free the meta data if the BufferList has more than -+ * ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS number of buffers. -+ * Otherwise, the meta data shall be freed when the icp_drvOpData is -+ * freed. -+ */ -+ if (ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS < pBufferList->numBuffers) { -+ icp_kfree(pBufferList->pPrivateMetaData); -+ } -+} -+ -+/* Module declaration, init and exit functions */ -+ICP_DECLARE_MODULE(icp_ocf, icp_ocfDrvInit, icp_ocfDrvExit); -+ICP_MODULE_DESCRIPTION("OCF Driver for Intel Quick Assist crypto acceleration"); -+ICP_MODULE_VERSION(icp_ocf, ICP_OCF_VER_MJR); -+ICP_MODULE_LICENSE("Dual BSD/GPL"); -+ICP_MODULE_AUTHOR("Intel"); -+ -+/* Module parameters */ -+ICP_MODULE_PARAM_INT(icp_ocf, num_dereg_retries, -+ "Number of times to retry LAC Sym Session Deregistration. " -+ "Default 10, Max 100"); -+ICP_MODULE_PARAM_INT(icp_ocf, dereg_retry_delay_in_jiffies, "Delay in jiffies " -+ "(added to a schedule() function call) before a LAC Sym " -+ "Session Dereg is retried. Default 10"); -+ICP_MODULE_PARAM_INT(icp_ocf, max_sessions, -+ "This sets the maximum number of sessions " -+ "between OCF and this driver. If this value is set to zero," -+ "max session count checking is disabled. Default is zero(0)"); -+ -+/* Module dependencies */ -+#define MODULE_MIN_VER 1 -+#define CRYPTO_MAX_VER 3 -+#define LAC_MAX_VER 2 -+ -+ICP_MODULE_DEPEND(icp_ocf, crypto, MODULE_MIN_VER, MODULE_MIN_VER, -+ CRYPTO_MAX_VER); -+ICP_MODULE_DEPEND(icp_ocf, cryptodev, MODULE_MIN_VER, MODULE_MIN_VER, -+ CRYPTO_MAX_VER); -+ICP_MODULE_DEPEND(icp_ocf, icp_crypto, MODULE_MIN_VER, MODULE_MIN_VER, -+ LAC_MAX_VER); -diff -Nur linux-2.6.36.orig/crypto/ocf/ep80579/icp_ocf.h linux-2.6.36/crypto/ocf/ep80579/icp_ocf.h ---- linux-2.6.36.orig/crypto/ocf/ep80579/icp_ocf.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/ep80579/icp_ocf.h 2010-11-09 20:28:04.662495462 +0100 -@@ -0,0 +1,376 @@ -+/*************************************************************************** -+ * -+ * This file is provided under a dual BSD/GPLv2 license. When using or -+ * redistributing this file, you may do so under either license. -+ * -+ * GPL LICENSE SUMMARY -+ * -+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of version 2 of the GNU General Public License as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. -+ * The full GNU General Public License is included in this distribution -+ * in the file called LICENSE.GPL. -+ * -+ * Contact Information: -+ * Intel Corporation -+ * -+ * BSD LICENSE -+ * -+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * * Neither the name of Intel Corporation nor the names of its -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * -+ * version: Security.L.1.0.2-229 -+ * -+ ***************************************************************************/ -+ -+/* -+ * OCF driver header file for the Intel ICP processor. -+ */ -+ -+#ifndef ICP_OCF_H_ -+#define ICP_OCF_H_ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "icp_os.h" -+ -+#define NUM_BITS_IN_BYTE (8) -+#define NUM_BITS_IN_BYTE_MINUS_ONE (NUM_BITS_IN_BYTE -1) -+#define INVALID_DRIVER_ID (-1) -+#define RETURN_RAND_NUM_GEN_FAILED (-1) -+ -+/*This is the max block cipher initialisation vector*/ -+#define MAX_IV_LEN_IN_BYTES (20) -+/*This is used to check whether the OCF to this driver session limit has -+ been disabled*/ -+#define NO_OCF_TO_DRV_MAX_SESSIONS (0) -+ -+/*OCF values mapped here*/ -+#define ICP_SHA1_DIGEST_SIZE_IN_BYTES (SHA1_HASH_LEN) -+#define ICP_SHA256_DIGEST_SIZE_IN_BYTES (SHA2_256_HASH_LEN) -+#define ICP_SHA384_DIGEST_SIZE_IN_BYTES (SHA2_384_HASH_LEN) -+#define ICP_SHA512_DIGEST_SIZE_IN_BYTES (SHA2_512_HASH_LEN) -+#define ICP_MD5_DIGEST_SIZE_IN_BYTES (MD5_HASH_LEN) -+#define ARC4_COUNTER_LEN (ARC4_BLOCK_LEN) -+ -+#define OCF_REGISTRATION_STATUS_SUCCESS (0) -+#define OCF_ZERO_FUNCTIONALITY_REGISTERED (0) -+#define ICP_OCF_DRV_NO_CRYPTO_PROCESS_ERROR (0) -+#define ICP_OCF_DRV_STATUS_SUCCESS (0) -+#define ICP_OCF_DRV_STATUS_FAIL (1) -+ -+/*Turn on/off debug options*/ -+#define ICP_OCF_PRINT_DEBUG_MESSAGES (0) -+#define ICP_OCF_PRINT_KERN_ALERT (1) -+#define ICP_OCF_PRINT_KERN_ERRS (1) -+ -+#if ICP_OCF_PRINT_DEBUG_MESSAGES == 1 -+#define DPRINTK(args...) \ -+{ \ -+ ICP_IPRINTK(args); \ -+} -+ -+#else //ICP_OCF_PRINT_DEBUG_MESSAGES == 1 -+ -+#define DPRINTK(args...) -+ -+#endif //ICP_OCF_PRINT_DEBUG_MESSAGES == 1 -+ -+#if ICP_OCF_PRINT_KERN_ALERT == 1 -+#define APRINTK(args...) \ -+{ \ -+ ICP_APRINTK(args); \ -+} -+ -+#else //ICP_OCF_PRINT_KERN_ALERT == 1 -+ -+#define APRINTK(args...) -+ -+#endif //ICP_OCF_PRINT_KERN_ALERT == 1 -+ -+#if ICP_OCF_PRINT_KERN_ERRS == 1 -+#define EPRINTK(args...) \ -+{ \ -+ ICP_EPRINTK(args); \ -+} -+ -+#else //ICP_OCF_PRINT_KERN_ERRS == 1 -+ -+#define EPRINTK(args...) -+ -+#endif //ICP_OCF_PRINT_KERN_ERRS == 1 -+ -+#define IPRINTK(args...) \ -+{ \ -+ ICP_IPRINTK(args); \ -+} -+ -+/*DSA Prime Q size in bytes (as defined in the standard) */ -+#define DSA_RS_SIGN_PRIMEQ_SIZE_IN_BYTES (20) -+ -+#define BITS_TO_BYTES(bytes, bits) \ -+ bytes = (bits + NUM_BITS_IN_BYTE_MINUS_ONE) / NUM_BITS_IN_BYTE -+ -+typedef enum { -+ ICP_OCF_DRV_ALG_CIPHER = 0, -+ ICP_OCF_DRV_ALG_HASH -+} icp_ocf_drv_alg_type_t; -+ -+typedef ICP_LIST_HEAD(icp_drvSessionListHead_s, -+ icp_drvSessionData) icp_drvSessionListHead_t; -+ -+/*Values used to derisk chances of performs being called against -+deregistered sessions (for which the slab page has been reclaimed) -+This is not a fix - since page frames are reclaimed from a slab, one cannot -+rely on that memory not being re-used by another app.*/ -+typedef enum { -+ ICP_SESSION_INITIALISED = 0x5C5C5C, -+ ICP_SESSION_RUNNING = 0x005C00, -+ ICP_SESSION_DEREGISTERED = 0xC5C5C5 -+} usage_derisk; -+ -+/* This struct is required for deferred session -+ deregistration as a work queue function can -+ only have one argument*/ -+struct icp_ocfDrvFreeLacSession { -+ CpaCySymSessionCtx sessionToDeregister; -+ icp_workstruct work; -+}; -+ -+/* -+This is the OCF<->OCF_DRV session object: -+ -+1.listNode -+ The first member is a listNode. These session objects are added to a linked -+ list in order to make it easier to remove them all at session exit time. -+ -+2.inUse -+ The second member is used to give the session object state and derisk the -+ possibility of OCF batch calls executing against a deregistered session (as -+ described above). -+ -+3.sessHandle -+ The third member is a LAC<->OCF_DRV session handle (initialised with the first -+ perform request for that session). -+ -+4.lacSessCtx -+ The fourth is the LAC session context. All the parameters for this structure -+ are only known when the first perform request for this session occurs. That is -+ why the OCF EP80579 Driver only registers a new LAC session at perform time -+*/ -+struct icp_drvSessionData { -+ ICP_LIST_ENTRY(icp_drvSessionData) listNode; -+ usage_derisk inUse; -+ CpaCySymSessionCtx sessHandle; -+ CpaCySymSessionSetupData lacSessCtx; -+}; -+ -+/* These are all defined in icp_common.c */ -+extern icp_atomic_t lac_session_failed_dereg_count; -+extern icp_atomic_t icp_ocfDrvIsExiting; -+extern icp_atomic_t num_ocf_to_drv_registered_sessions; -+ -+extern int32_t icp_ocfDrvDriverId; -+ -+extern icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead; -+extern icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead_FreeMemList; -+extern icp_workqueue *icp_ocfDrvFreeLacSessionWorkQ; -+extern icp_spinlock_t icp_ocfDrvSymSessInfoListSpinlock; -+ -+/*Slab zones for symettric functionality, instantiated in icp_common.c*/ -+extern icp_kmem_cache drvSessionData_zone; -+extern icp_kmem_cache drvOpData_zone; -+ -+/*Slabs zones for asymettric functionality, instantiated in icp_common.c*/ -+extern icp_kmem_cache drvDH_zone; -+extern icp_kmem_cache drvLnModExp_zone; -+extern icp_kmem_cache drvRSADecrypt_zone; -+extern icp_kmem_cache drvRSAPrivateKey_zone; -+extern icp_kmem_cache drvDSARSSign_zone; -+extern icp_kmem_cache drvDSARSSignKValue_zone; -+extern icp_kmem_cache drvDSAVerify_zone; -+ -+/* Module parameters defined in icp_cpmmon.c*/ -+ -+/* Module parameters - gives the number of times LAC deregistration shall be -+ re-tried */ -+extern int num_dereg_retries; -+ -+/* Module parameter - gives the delay time in jiffies before a LAC session -+ shall be attempted to be deregistered again */ -+extern int dereg_retry_delay_in_jiffies; -+ -+/* Module parameter - gives the maximum number of sessions possible between -+ OCF and the OCF EP80579 Driver. If set to zero, there is no limit.*/ -+extern int max_sessions; -+ -+/*Slab zones for flatbuffers and bufferlist*/ -+extern icp_kmem_cache drvFlatBuffer_zone; -+ -+#define ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS (16) -+ -+struct icp_drvBuffListInfo { -+ Cpa16U numBuffers; -+ Cpa32U metaSize; -+ Cpa32U metaOffset; -+ Cpa32U buffListSize; -+}; -+ -+extern struct icp_drvBuffListInfo defBuffListInfo; -+ -+/* This struct is used to keep a reference to the relevant node in the list -+ of sessionData structs, to the buffer type required by OCF and to the OCF -+ provided crp struct that needs to be returned. All this info is needed in -+ the callback function.*/ -+struct icp_drvOpData { -+ CpaCySymOpData lacOpData; -+ uint32_t digestSizeInBytes; -+ struct cryptop *crp; -+ uint8_t bufferType; -+ uint8_t ivData[MAX_IV_LEN_IN_BYTES]; -+ uint16_t numBufferListArray; -+ CpaBufferList srcBuffer; -+ CpaFlatBuffer bufferListArray[ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS]; -+ CpaBoolean verifyResult; -+}; -+ -+/* Create a new session between OCF and this driver*/ -+int icp_ocfDrvNewSession(icp_device_t dev, uint32_t * sild, -+ struct cryptoini *cri); -+ -+/* Free a session between this driver and the Quick Assist Framework*/ -+int icp_ocfDrvFreeLACSession(icp_device_t dev, uint64_t sid); -+ -+/* Defer freeing a Quick Assist session*/ -+void icp_ocfDrvDeferedFreeLacSessionProcess(void *arg); -+ -+/* Process OCF cryptographic request for a symmetric algorithm*/ -+int icp_ocfDrvSymProcess(icp_device_t dev, struct cryptop *crp, int hint); -+ -+/* Process OCF cryptographic request for an asymmetric algorithm*/ -+int icp_ocfDrvPkeProcess(icp_device_t dev, struct cryptkop *krp, int hint); -+ -+/* Populate a buffer with random data*/ -+int icp_ocfDrvReadRandom(void *arg, uint32_t * buf, int maxwords); -+ -+/* Retry Quick Assist session deregistration*/ -+int icp_ocfDrvDeregRetry(CpaCySymSessionCtx sessionToDeregister); -+ -+/* Convert an OS scatter gather list to a CPA buffer list*/ -+int icp_ocfDrvPacketBuffToBufferList(icp_packet_buffer_t * pPacketBuffer, -+ CpaBufferList * bufferList); -+ -+/* Convert a CPA buffer list to an OS scatter gather list*/ -+int icp_ocfDrvBufferListToPacketBuff(CpaBufferList * bufferList, -+ icp_packet_buffer_t ** pPacketBuffer); -+ -+/* Get the number of buffers in an OS scatter gather list*/ -+uint16_t icp_ocfDrvGetPacketBuffFrags(icp_packet_buffer_t * pPacketBuffer); -+ -+/* Convert a single OS buffer to a CPA Flat Buffer*/ -+void icp_ocfDrvSinglePacketBuffToFlatBuffer(icp_packet_buffer_t * pPacketBuffer, -+ CpaFlatBuffer * pFlatBuffer); -+ -+/* Add pointer and length to a CPA Flat Buffer structure*/ -+void icp_ocfDrvPtrAndLenToFlatBuffer(void *pData, uint32_t len, -+ CpaFlatBuffer * pFlatBuffer); -+ -+/* Convert pointer and length values to a CPA buffer list*/ -+void icp_ocfDrvPtrAndLenToBufferList(void *pDataIn, uint32_t length, -+ CpaBufferList * pBufferList); -+ -+/* Convert a CPA buffer list to pointer and length values*/ -+void icp_ocfDrvBufferListToPtrAndLen(CpaBufferList * pBufferList, -+ void **ppDataOut, uint32_t * pLength); -+ -+/* Set the number of flat buffers in bufferlist and the size of memory -+ to allocate for the pPrivateMetaData member of the CpaBufferList.*/ -+int icp_ocfDrvBufferListMemInfo(uint16_t numBuffers, -+ struct icp_drvBuffListInfo *buffListInfo); -+ -+/* Find pointer position of the digest within an OS scatter gather list*/ -+uint8_t *icp_ocfDrvPacketBufferDigestPointerFind(struct icp_drvOpData -+ *drvOpData, -+ int offsetInBytes, -+ uint32_t digestSizeInBytes); -+ -+/*This top level function is used to find a pointer to where a digest is -+ stored/needs to be inserted. */ -+uint8_t *icp_ocfDrvDigestPointerFind(struct icp_drvOpData *drvOpData, -+ struct cryptodesc *crp_desc); -+ -+/* Free a CPA flat buffer*/ -+void icp_ocfDrvFreeFlatBuffer(CpaFlatBuffer * pFlatBuffer); -+ -+/* This function will allocate memory for the pPrivateMetaData -+ member of CpaBufferList. */ -+int icp_ocfDrvAllocMetaData(CpaBufferList * pBufferList, -+ struct icp_drvOpData *pOpData); -+ -+/* Free data allocated for the pPrivateMetaData -+ member of CpaBufferList.*/ -+void icp_ocfDrvFreeMetaData(CpaBufferList * pBufferList); -+ -+#define ICP_CACHE_CREATE(cache_ID, cache_name) \ -+ icp_kmem_cache_create(cache_ID, sizeof(cache_name),ICP_KERNEL_CACHE_ALIGN,\ -+ ICP_KERNEL_CACHE_NOINIT) -+ -+#define ICP_CACHE_FREE(args...) \ -+ icp_kmem_cache_free (args) -+ -+#define ICP_CACHE_DESTROY(slab_zone)\ -+{\ -+ if(NULL != slab_zone){\ -+ icp_kmem_cache_destroy(slab_zone);\ -+ slab_zone = NULL;\ -+ }\ -+} -+ -+#endif -+/* ICP_OCF_H_ */ -diff -Nur linux-2.6.36.orig/crypto/ocf/ep80579/icp_sym.c linux-2.6.36/crypto/ocf/ep80579/icp_sym.c ---- linux-2.6.36.orig/crypto/ocf/ep80579/icp_sym.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/ep80579/icp_sym.c 2010-11-09 20:28:04.702495471 +0100 -@@ -0,0 +1,1153 @@ -+/*************************************************************************** -+ * -+ * This file is provided under a dual BSD/GPLv2 license. When using or -+ * redistributing this file, you may do so under either license. -+ * -+ * GPL LICENSE SUMMARY -+ * -+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of version 2 of the GNU General Public License as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. -+ * The full GNU General Public License is included in this distribution -+ * in the file called LICENSE.GPL. -+ * -+ * Contact Information: -+ * Intel Corporation -+ * -+ * BSD LICENSE -+ * -+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * * Neither the name of Intel Corporation nor the names of its -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * -+ * version: Security.L.1.0.2-229 -+ * -+ ***************************************************************************/ -+/* -+ * An OCF module that uses the API for Intel® QuickAssist Technology to do the -+ * cryptography. -+ * -+ * This driver requires the ICP Access Library that is available from Intel in -+ * order to operate. -+ */ -+ -+#include "icp_ocf.h" -+ -+/*This is the call back function for all symmetric cryptographic processes. -+ Its main functionality is to free driver crypto operation structure and to -+ call back to OCF*/ -+static void -+icp_ocfDrvSymCallBack(void *callbackTag, -+ CpaStatus status, -+ const CpaCySymOp operationType, -+ void *pOpData, -+ CpaBufferList * pDstBuffer, CpaBoolean verifyResult); -+ -+/*This function is used to extract crypto processing information from the OCF -+ inputs, so as that it may be passed onto LAC*/ -+static int -+icp_ocfDrvProcessDataSetup(struct icp_drvOpData *drvOpData, -+ struct cryptodesc *crp_desc); -+ -+/*This function checks whether the crp_desc argument pertains to a digest or a -+ cipher operation*/ -+static int icp_ocfDrvAlgCheck(struct cryptodesc *crp_desc); -+ -+/*This function copies all the passed in session context information and stores -+ it in a LAC context structure*/ -+static int -+icp_ocfDrvAlgorithmSetup(struct cryptoini *cri, -+ CpaCySymSessionSetupData * lacSessCtx); -+ -+/*This function is used to free an OCF->OCF_DRV session object*/ -+static void icp_ocfDrvFreeOCFSession(struct icp_drvSessionData *sessionData); -+ -+/*max IOV buffs supported in a UIO structure*/ -+#define NUM_IOV_SUPPORTED (1) -+ -+/* Name : icp_ocfDrvSymCallBack -+ * -+ * Description : When this function returns it signifies that the LAC -+ * component has completed the relevant symmetric operation. -+ * -+ * Notes : The callbackTag is a pointer to an icp_drvOpData. This memory -+ * object was passed to LAC for the cryptographic processing and contains all -+ * the relevant information for cleaning up buffer handles etc. so that the -+ * OCF EP80579 Driver portion of this crypto operation can be fully completed. -+ */ -+static void -+icp_ocfDrvSymCallBack(void *callbackTag, -+ CpaStatus status, -+ const CpaCySymOp operationType, -+ void *pOpData, -+ CpaBufferList * pDstBuffer, CpaBoolean verifyResult) -+{ -+ struct cryptop *crp = NULL; -+ struct icp_drvOpData *temp_drvOpData = -+ (struct icp_drvOpData *)callbackTag; -+ uint64_t *tempBasePtr = NULL; -+ uint32_t tempLen = 0; -+ -+ if (NULL == temp_drvOpData) { -+ DPRINTK("%s(): The callback from the LAC component" -+ " has failed due to Null userOpaque data" -+ "(status == %d).\n", __FUNCTION__, status); -+ DPRINTK("%s(): Unable to call OCF back! \n", __FUNCTION__); -+ return; -+ } -+ -+ crp = temp_drvOpData->crp; -+ crp->crp_etype = ICP_OCF_DRV_NO_CRYPTO_PROCESS_ERROR; -+ -+ if (NULL == pOpData) { -+ DPRINTK("%s(): The callback from the LAC component" -+ " has failed due to Null Symmetric Op data" -+ "(status == %d).\n", __FUNCTION__, status); -+ crp->crp_etype = ECANCELED; -+ crypto_done(crp); -+ return; -+ } -+ -+ if (NULL == pDstBuffer) { -+ DPRINTK("%s(): The callback from the LAC component" -+ " has failed due to Null Dst Bufferlist data" -+ "(status == %d).\n", __FUNCTION__, status); -+ crp->crp_etype = ECANCELED; -+ crypto_done(crp); -+ return; -+ } -+ -+ if (CPA_STATUS_SUCCESS == status) { -+ -+ if (temp_drvOpData->bufferType == ICP_CRYPTO_F_PACKET_BUF) { -+ if (ICP_OCF_DRV_STATUS_SUCCESS != -+ icp_ocfDrvBufferListToPacketBuff(pDstBuffer, -+ (icp_packet_buffer_t -+ **) -+ & (crp->crp_buf))) { -+ EPRINTK("%s(): BufferList to SkBuff " -+ "conversion error.\n", __FUNCTION__); -+ crp->crp_etype = EPERM; -+ } -+ } else { -+ icp_ocfDrvBufferListToPtrAndLen(pDstBuffer, -+ (void **)&tempBasePtr, -+ &tempLen); -+ crp->crp_olen = (int)tempLen; -+ } -+ -+ } else { -+ DPRINTK("%s(): The callback from the LAC component has failed" -+ "(status == %d).\n", __FUNCTION__, status); -+ -+ crp->crp_etype = ECANCELED; -+ } -+ -+ if (temp_drvOpData->numBufferListArray > -+ ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) { -+ icp_kfree(pDstBuffer->pBuffers); -+ } -+ icp_ocfDrvFreeMetaData(pDstBuffer); -+ ICP_CACHE_FREE(drvOpData_zone, temp_drvOpData); -+ -+ /* Invoke the OCF callback function */ -+ crypto_done(crp); -+ -+ return; -+} -+ -+/* Name : icp_ocfDrvNewSession -+ * -+ * Description : This function will create a new Driver<->OCF session -+ * -+ * Notes : LAC session registration happens during the first perform call. -+ * That is the first time we know all information about a given session. -+ */ -+int icp_ocfDrvNewSession(icp_device_t dev, uint32_t * sid, -+ struct cryptoini *cri) -+{ -+ struct icp_drvSessionData *sessionData = NULL; -+ uint32_t delete_session = 0; -+ -+ /* The SID passed in should be our driver ID. We can return the */ -+ /* local ID (LID) which is a unique identifier which we can use */ -+ /* to differentiate between the encrypt/decrypt LAC session handles */ -+ if (NULL == sid) { -+ EPRINTK("%s(): Invalid input parameters - NULL sid.\n", -+ __FUNCTION__); -+ return EINVAL; -+ } -+ -+ if (NULL == cri) { -+ EPRINTK("%s(): Invalid input parameters - NULL cryptoini.\n", -+ __FUNCTION__); -+ return EINVAL; -+ } -+ -+ if (icp_ocfDrvDriverId != *sid) { -+ EPRINTK("%s(): Invalid input parameters - bad driver ID\n", -+ __FUNCTION__); -+ EPRINTK("\t sid = 0x08%p \n \t cri = 0x08%p \n", sid, cri); -+ return EINVAL; -+ } -+ -+ sessionData = icp_kmem_cache_zalloc(drvSessionData_zone, ICP_M_NOWAIT); -+ if (NULL == sessionData) { -+ DPRINTK("%s():No memory for Session Data\n", __FUNCTION__); -+ return ENOMEM; -+ } -+ -+ /*ENTER CRITICAL SECTION */ -+ icp_spin_lockbh_lock(&icp_ocfDrvSymSessInfoListSpinlock); -+ /*put this check in the spinlock so no new sessions can be added to the -+ linked list when we are exiting */ -+ if (CPA_TRUE == icp_atomic_read(&icp_ocfDrvIsExiting)) { -+ delete_session++; -+ -+ } else if (NO_OCF_TO_DRV_MAX_SESSIONS != max_sessions) { -+ if (icp_atomic_read(&num_ocf_to_drv_registered_sessions) >= -+ (max_sessions - -+ icp_atomic_read(&lac_session_failed_dereg_count))) { -+ delete_session++; -+ } else { -+ icp_atomic_inc(&num_ocf_to_drv_registered_sessions); -+ /* Add to session data linked list */ -+ ICP_LIST_ADD(sessionData, &icp_ocfDrvGlobalSymListHead, -+ listNode); -+ } -+ -+ } else if (NO_OCF_TO_DRV_MAX_SESSIONS == max_sessions) { -+ ICP_LIST_ADD(sessionData, &icp_ocfDrvGlobalSymListHead, -+ listNode); -+ } -+ -+ sessionData->inUse = ICP_SESSION_INITIALISED; -+ -+ /*EXIT CRITICAL SECTION */ -+ icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock); -+ -+ if (delete_session) { -+ DPRINTK("%s():No Session handles available\n", __FUNCTION__); -+ ICP_CACHE_FREE(drvSessionData_zone, sessionData); -+ return EPERM; -+ } -+ -+ if (ICP_OCF_DRV_STATUS_SUCCESS != -+ icp_ocfDrvAlgorithmSetup(cri, &(sessionData->lacSessCtx))) { -+ DPRINTK("%s():algorithm not supported\n", __FUNCTION__); -+ icp_ocfDrvFreeOCFSession(sessionData); -+ return EINVAL; -+ } -+ -+ if (cri->cri_next) { -+ if (cri->cri_next->cri_next != NULL) { -+ DPRINTK("%s():only two chained algorithms supported\n", -+ __FUNCTION__); -+ icp_ocfDrvFreeOCFSession(sessionData); -+ return EPERM; -+ } -+ -+ if (ICP_OCF_DRV_STATUS_SUCCESS != -+ icp_ocfDrvAlgorithmSetup(cri->cri_next, -+ &(sessionData->lacSessCtx))) { -+ DPRINTK("%s():second algorithm not supported\n", -+ __FUNCTION__); -+ icp_ocfDrvFreeOCFSession(sessionData); -+ return EINVAL; -+ } -+ -+ sessionData->lacSessCtx.symOperation = -+ CPA_CY_SYM_OP_ALGORITHM_CHAINING; -+ } -+ -+ *sid = (uint32_t) sessionData; -+ -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+} -+ -+/* Name : icp_ocfDrvAlgorithmSetup -+ * -+ * Description : This function builds the session context data from the -+ * information supplied through OCF. Algorithm chain order and whether the -+ * session is Encrypt/Decrypt can only be found out at perform time however, so -+ * the session is registered with LAC at that time. -+ */ -+static int -+icp_ocfDrvAlgorithmSetup(struct cryptoini *cri, -+ CpaCySymSessionSetupData * lacSessCtx) -+{ -+ -+ lacSessCtx->sessionPriority = CPA_CY_PRIORITY_NORMAL; -+ -+ switch (cri->cri_alg) { -+ -+ case CRYPTO_NULL_CBC: -+ DPRINTK("%s(): NULL CBC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; -+ lacSessCtx->cipherSetupData.cipherAlgorithm = -+ CPA_CY_SYM_CIPHER_NULL; -+ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; -+ break; -+ -+ case CRYPTO_DES_CBC: -+ DPRINTK("%s(): DES CBC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; -+ lacSessCtx->cipherSetupData.cipherAlgorithm = -+ CPA_CY_SYM_CIPHER_DES_CBC; -+ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; -+ break; -+ -+ case CRYPTO_3DES_CBC: -+ DPRINTK("%s(): 3DES CBC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; -+ lacSessCtx->cipherSetupData.cipherAlgorithm = -+ CPA_CY_SYM_CIPHER_3DES_CBC; -+ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; -+ break; -+ -+ case CRYPTO_AES_CBC: -+ DPRINTK("%s(): AES CBC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; -+ lacSessCtx->cipherSetupData.cipherAlgorithm = -+ CPA_CY_SYM_CIPHER_AES_CBC; -+ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; -+ break; -+ -+ case CRYPTO_ARC4: -+ DPRINTK("%s(): ARC4\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; -+ lacSessCtx->cipherSetupData.cipherAlgorithm = -+ CPA_CY_SYM_CIPHER_ARC4; -+ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; -+ break; -+ -+ case CRYPTO_SHA1: -+ DPRINTK("%s(): SHA1\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_SHA1; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_SHA1_DIGEST_SIZE_IN_BYTES); -+ -+ break; -+ -+ case CRYPTO_SHA1_HMAC: -+ DPRINTK("%s(): SHA1_HMAC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_SHA1; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_SHA1_DIGEST_SIZE_IN_BYTES); -+ lacSessCtx->hashSetupData.authModeSetupData.authKey = -+ cri->cri_key; -+ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; -+ -+ break; -+ -+ case CRYPTO_SHA2_256: -+ DPRINTK("%s(): SHA256\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = -+ CPA_CY_SYM_HASH_SHA256; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_SHA256_DIGEST_SIZE_IN_BYTES); -+ -+ break; -+ -+ case CRYPTO_SHA2_256_HMAC: -+ DPRINTK("%s(): SHA256_HMAC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = -+ CPA_CY_SYM_HASH_SHA256; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_SHA256_DIGEST_SIZE_IN_BYTES); -+ lacSessCtx->hashSetupData.authModeSetupData.authKey = -+ cri->cri_key; -+ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; -+ -+ break; -+ -+ case CRYPTO_SHA2_384: -+ DPRINTK("%s(): SHA384\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = -+ CPA_CY_SYM_HASH_SHA384; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_SHA384_DIGEST_SIZE_IN_BYTES); -+ -+ break; -+ -+ case CRYPTO_SHA2_384_HMAC: -+ DPRINTK("%s(): SHA384_HMAC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = -+ CPA_CY_SYM_HASH_SHA384; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_SHA384_DIGEST_SIZE_IN_BYTES); -+ lacSessCtx->hashSetupData.authModeSetupData.authKey = -+ cri->cri_key; -+ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; -+ -+ break; -+ -+ case CRYPTO_SHA2_512: -+ DPRINTK("%s(): SHA512\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = -+ CPA_CY_SYM_HASH_SHA512; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_SHA512_DIGEST_SIZE_IN_BYTES); -+ -+ break; -+ -+ case CRYPTO_SHA2_512_HMAC: -+ DPRINTK("%s(): SHA512_HMAC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = -+ CPA_CY_SYM_HASH_SHA512; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_SHA512_DIGEST_SIZE_IN_BYTES); -+ lacSessCtx->hashSetupData.authModeSetupData.authKey = -+ cri->cri_key; -+ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; -+ -+ break; -+ -+ case CRYPTO_MD5: -+ DPRINTK("%s(): MD5\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_MD5; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_MD5_DIGEST_SIZE_IN_BYTES); -+ -+ break; -+ -+ case CRYPTO_MD5_HMAC: -+ DPRINTK("%s(): MD5_HMAC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_MD5; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_MD5_DIGEST_SIZE_IN_BYTES); -+ lacSessCtx->hashSetupData.authModeSetupData.authKey = -+ cri->cri_key; -+ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; -+ -+ break; -+ -+ default: -+ DPRINTK("%s(): ALG Setup FAIL\n", __FUNCTION__); -+ return ICP_OCF_DRV_STATUS_FAIL; -+ } -+ -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+} -+ -+/* Name : icp_ocfDrvFreeOCFSession -+ * -+ * Description : This function deletes all existing Session data representing -+ * the Cryptographic session established between OCF and this driver. This -+ * also includes freeing the memory allocated for the session context. The -+ * session object is also removed from the session linked list. -+ */ -+static void icp_ocfDrvFreeOCFSession(struct icp_drvSessionData *sessionData) -+{ -+ -+ sessionData->inUse = ICP_SESSION_DEREGISTERED; -+ -+ /*ENTER CRITICAL SECTION */ -+ icp_spin_lockbh_lock(&icp_ocfDrvSymSessInfoListSpinlock); -+ -+ if (CPA_TRUE == icp_atomic_read(&icp_ocfDrvIsExiting)) { -+ /*If the Driver is exiting, allow that process to -+ handle any deletions */ -+ /*EXIT CRITICAL SECTION */ -+ icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock); -+ return; -+ } -+ -+ icp_atomic_dec(&num_ocf_to_drv_registered_sessions); -+ -+ ICP_LIST_DEL(sessionData, listNode); -+ -+ /*EXIT CRITICAL SECTION */ -+ icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock); -+ -+ if (NULL != sessionData->sessHandle) { -+ icp_kfree(sessionData->sessHandle); -+ } -+ ICP_CACHE_FREE(drvSessionData_zone, sessionData); -+} -+ -+/* Name : icp_ocfDrvFreeLACSession -+ * -+ * Description : This attempts to deregister a LAC session. If it fails, the -+ * deregistation retry function is called. -+ */ -+int icp_ocfDrvFreeLACSession(icp_device_t dev, uint64_t sid) -+{ -+ CpaCySymSessionCtx sessionToDeregister = NULL; -+ struct icp_drvSessionData *sessionData = NULL; -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ int retval = 0; -+ -+ sessionData = (struct icp_drvSessionData *)CRYPTO_SESID2LID(sid); -+ if (NULL == sessionData) { -+ EPRINTK("%s(): OCF Free session called with Null Session ID.\n", -+ __FUNCTION__); -+ return EINVAL; -+ } -+ -+ sessionToDeregister = sessionData->sessHandle; -+ -+ if ((ICP_SESSION_INITIALISED != sessionData->inUse) && -+ (ICP_SESSION_RUNNING != sessionData->inUse) && -+ (ICP_SESSION_DEREGISTERED != sessionData->inUse)) { -+ DPRINTK("%s() Session not initialised.\n", __FUNCTION__); -+ return EINVAL; -+ } -+ -+ if (ICP_SESSION_RUNNING == sessionData->inUse) { -+ lacStatus = cpaCySymRemoveSession(CPA_INSTANCE_HANDLE_SINGLE, -+ sessionToDeregister); -+ if (CPA_STATUS_RETRY == lacStatus) { -+ if (ICP_OCF_DRV_STATUS_SUCCESS != -+ icp_ocfDrvDeregRetry(&sessionToDeregister)) { -+ /* the retry function increments the -+ dereg failed count */ -+ DPRINTK("%s(): LAC failed to deregister the " -+ "session. (localSessionId= %p)\n", -+ __FUNCTION__, sessionToDeregister); -+ retval = EPERM; -+ } -+ -+ } else if (CPA_STATUS_SUCCESS != lacStatus) { -+ DPRINTK("%s(): LAC failed to deregister the session. " -+ "localSessionId= %p, lacStatus = %d\n", -+ __FUNCTION__, sessionToDeregister, lacStatus); -+ icp_atomic_inc(&lac_session_failed_dereg_count); -+ retval = EPERM; -+ } -+ } else { -+ DPRINTK("%s() Session not registered with LAC.\n", -+ __FUNCTION__); -+ } -+ -+ icp_ocfDrvFreeOCFSession(sessionData); -+ return retval; -+ -+} -+ -+/* Name : icp_ocfDrvAlgCheck -+ * -+ * Description : This function checks whether the cryptodesc argument pertains -+ * to a sym or hash function -+ */ -+static int icp_ocfDrvAlgCheck(struct cryptodesc *crp_desc) -+{ -+ -+ if (crp_desc->crd_alg == CRYPTO_3DES_CBC || -+ crp_desc->crd_alg == CRYPTO_AES_CBC || -+ crp_desc->crd_alg == CRYPTO_DES_CBC || -+ crp_desc->crd_alg == CRYPTO_NULL_CBC || -+ crp_desc->crd_alg == CRYPTO_ARC4) { -+ return ICP_OCF_DRV_ALG_CIPHER; -+ } -+ -+ return ICP_OCF_DRV_ALG_HASH; -+} -+ -+/* Name : icp_ocfDrvSymProcess -+ * -+ * Description : This function will map symmetric functionality calls from OCF -+ * to the LAC API. It will also allocate memory to store the session context. -+ * -+ * Notes: If it is the first perform call for a given session, then a LAC -+ * session is registered. After the session is registered, no checks as -+ * to whether session paramaters have changed (e.g. alg chain order) are -+ * done. -+ */ -+int icp_ocfDrvSymProcess(icp_device_t dev, struct cryptop *crp, int hint) -+{ -+ struct icp_drvSessionData *sessionData = NULL; -+ struct icp_drvOpData *drvOpData = NULL; -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ Cpa32U sessionCtxSizeInBytes = 0; -+ -+ if (NULL == crp) { -+ DPRINTK("%s(): Invalid input parameters, cryptop is NULL\n", -+ __FUNCTION__); -+ return EINVAL; -+ } -+ -+ if (NULL == crp->crp_desc) { -+ DPRINTK("%s(): Invalid input parameters, no crp_desc attached " -+ "to crp\n", __FUNCTION__); -+ crp->crp_etype = EINVAL; -+ return EINVAL; -+ } -+ -+ if (NULL == crp->crp_buf) { -+ DPRINTK("%s(): Invalid input parameters, no buffer attached " -+ "to crp\n", __FUNCTION__); -+ crp->crp_etype = EINVAL; -+ return EINVAL; -+ } -+ -+ if (CPA_TRUE == icp_atomic_read(&icp_ocfDrvIsExiting)) { -+ crp->crp_etype = EFAULT; -+ return EFAULT; -+ } -+ -+ sessionData = (struct icp_drvSessionData *) -+ (CRYPTO_SESID2LID(crp->crp_sid)); -+ if (NULL == sessionData) { -+ DPRINTK("%s(): Invalid input parameters, Null Session ID \n", -+ __FUNCTION__); -+ crp->crp_etype = EINVAL; -+ return EINVAL; -+ } -+ -+/*If we get a request against a deregisted session, cancel operation*/ -+ if (ICP_SESSION_DEREGISTERED == sessionData->inUse) { -+ DPRINTK("%s(): Session ID %d was deregistered \n", -+ __FUNCTION__, (int)(CRYPTO_SESID2LID(crp->crp_sid))); -+ crp->crp_etype = EFAULT; -+ return EFAULT; -+ } -+ -+/*If none of the session states are set, then the session structure was either -+ not initialised properly or we are reading from a freed memory area (possible -+ due to OCF batch mode not removing queued requests against deregistered -+ sessions*/ -+ if (ICP_SESSION_INITIALISED != sessionData->inUse && -+ ICP_SESSION_RUNNING != sessionData->inUse) { -+ DPRINTK("%s(): Session - ID %d - not properly initialised or " -+ "memory freed back to the kernel \n", -+ __FUNCTION__, (int)(CRYPTO_SESID2LID(crp->crp_sid))); -+ crp->crp_etype = EINVAL; -+ return EINVAL; -+ } -+ -+ /*For the below checks, remember error checking is already done in LAC. -+ We're not validating inputs subsequent to registration */ -+ if (sessionData->inUse == ICP_SESSION_INITIALISED) { -+ DPRINTK("%s(): Initialising session\n", __FUNCTION__); -+ -+ if (NULL != crp->crp_desc->crd_next) { -+ if (ICP_OCF_DRV_ALG_CIPHER == -+ icp_ocfDrvAlgCheck(crp->crp_desc)) { -+ -+ sessionData->lacSessCtx.algChainOrder = -+ CPA_CY_SYM_ALG_CHAIN_ORDER_CIPHER_THEN_HASH; -+ -+ if (crp->crp_desc->crd_flags & CRD_F_ENCRYPT) { -+ sessionData->lacSessCtx.cipherSetupData. -+ cipherDirection = -+ CPA_CY_SYM_CIPHER_DIRECTION_ENCRYPT; -+ } else { -+ sessionData->lacSessCtx.cipherSetupData. -+ cipherDirection = -+ CPA_CY_SYM_CIPHER_DIRECTION_DECRYPT; -+ } -+ } else { -+ sessionData->lacSessCtx.algChainOrder = -+ CPA_CY_SYM_ALG_CHAIN_ORDER_HASH_THEN_CIPHER; -+ -+ if (crp->crp_desc->crd_next->crd_flags & -+ CRD_F_ENCRYPT) { -+ sessionData->lacSessCtx.cipherSetupData. -+ cipherDirection = -+ CPA_CY_SYM_CIPHER_DIRECTION_ENCRYPT; -+ } else { -+ sessionData->lacSessCtx.cipherSetupData. -+ cipherDirection = -+ CPA_CY_SYM_CIPHER_DIRECTION_DECRYPT; -+ } -+ -+ } -+ -+ } else if (ICP_OCF_DRV_ALG_CIPHER == -+ icp_ocfDrvAlgCheck(crp->crp_desc)) { -+ if (crp->crp_desc->crd_flags & CRD_F_ENCRYPT) { -+ sessionData->lacSessCtx.cipherSetupData. -+ cipherDirection = -+ CPA_CY_SYM_CIPHER_DIRECTION_ENCRYPT; -+ } else { -+ sessionData->lacSessCtx.cipherSetupData. -+ cipherDirection = -+ CPA_CY_SYM_CIPHER_DIRECTION_DECRYPT; -+ } -+ -+ } -+ -+ /*No action required for standalone Auth here */ -+ -+ /* Allocate memory for SymSessionCtx before the Session Registration */ -+ lacStatus = -+ cpaCySymSessionCtxGetSize(CPA_INSTANCE_HANDLE_SINGLE, -+ &(sessionData->lacSessCtx), -+ &sessionCtxSizeInBytes); -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): cpaCySymSessionCtxGetSize failed - %d\n", -+ __FUNCTION__, lacStatus); -+ crp->crp_etype = EINVAL; -+ return EINVAL; -+ } -+ sessionData->sessHandle = -+ icp_kmalloc(sessionCtxSizeInBytes, ICP_M_NOWAIT); -+ if (NULL == sessionData->sessHandle) { -+ EPRINTK -+ ("%s(): Failed to get memory for SymSessionCtx\n", -+ __FUNCTION__); -+ crp->crp_etype = ENOMEM; -+ return ENOMEM; -+ } -+ -+ lacStatus = cpaCySymInitSession(CPA_INSTANCE_HANDLE_SINGLE, -+ icp_ocfDrvSymCallBack, -+ &(sessionData->lacSessCtx), -+ sessionData->sessHandle); -+ -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): cpaCySymInitSession failed -%d \n", -+ __FUNCTION__, lacStatus); -+ crp->crp_etype = EFAULT; -+ return EFAULT; -+ } -+ -+ sessionData->inUse = ICP_SESSION_RUNNING; -+ } -+ -+ drvOpData = icp_kmem_cache_zalloc(drvOpData_zone, ICP_M_NOWAIT); -+ if (NULL == drvOpData) { -+ EPRINTK("%s():Failed to get memory for drvOpData\n", -+ __FUNCTION__); -+ crp->crp_etype = ENOMEM; -+ return ENOMEM; -+ } -+ -+ drvOpData->lacOpData.pSessionCtx = sessionData->sessHandle; -+ drvOpData->digestSizeInBytes = sessionData->lacSessCtx.hashSetupData. -+ digestResultLenInBytes; -+ drvOpData->crp = crp; -+ -+ /* Set the default buffer list array memory allocation */ -+ drvOpData->srcBuffer.pBuffers = drvOpData->bufferListArray; -+ drvOpData->numBufferListArray = ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS; -+ -+ if (ICP_OCF_DRV_STATUS_SUCCESS != -+ icp_ocfDrvProcessDataSetup(drvOpData, drvOpData->crp->crp_desc)) { -+ crp->crp_etype = EINVAL; -+ goto err; -+ } -+ -+ if (drvOpData->crp->crp_desc->crd_next != NULL) { -+ if (icp_ocfDrvProcessDataSetup(drvOpData, drvOpData->crp-> -+ crp_desc->crd_next)) { -+ crp->crp_etype = EINVAL; -+ goto err; -+ } -+ -+ } -+ -+ /* -+ * Allocate buffer list array memory if the data fragment is more than -+ * the default number (ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) and not -+ * calculated already -+ */ -+ if (crp->crp_flags & ICP_CRYPTO_F_PACKET_BUF) { -+ if (NULL == drvOpData->lacOpData.pDigestResult) { -+ drvOpData->numBufferListArray = -+ icp_ocfDrvGetPacketBuffFrags((icp_packet_buffer_t *) -+ crp->crp_buf); -+ } -+ -+ if (ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS < -+ drvOpData->numBufferListArray) { -+ DPRINTK("%s() numBufferListArray more than default\n", -+ __FUNCTION__); -+ drvOpData->srcBuffer.pBuffers = NULL; -+ drvOpData->srcBuffer.pBuffers = -+ icp_kmalloc(drvOpData->numBufferListArray * -+ sizeof(CpaFlatBuffer), ICP_M_NOWAIT); -+ if (NULL == drvOpData->srcBuffer.pBuffers) { -+ EPRINTK("%s() Failed to get memory for " -+ "pBuffers\n", __FUNCTION__); -+ ICP_CACHE_FREE(drvOpData_zone, drvOpData); -+ crp->crp_etype = ENOMEM; -+ return ENOMEM; -+ } -+ } -+ } -+ -+ /* -+ * Check the type of buffer structure we got and convert it into -+ * CpaBufferList format. -+ */ -+ if (crp->crp_flags & ICP_CRYPTO_F_PACKET_BUF) { -+ if (ICP_OCF_DRV_STATUS_SUCCESS != -+ icp_ocfDrvPacketBuffToBufferList((icp_packet_buffer_t *) -+ crp->crp_buf, -+ &(drvOpData->srcBuffer))) { -+ EPRINTK("%s():Failed to translate from packet buffer " -+ "to bufferlist\n", __FUNCTION__); -+ crp->crp_etype = EINVAL; -+ goto err; -+ } -+ -+ drvOpData->bufferType = ICP_CRYPTO_F_PACKET_BUF; -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ /* OCF only supports IOV of one entry. */ -+ if (NUM_IOV_SUPPORTED == -+ ((struct uio *)(crp->crp_buf))->uio_iovcnt) { -+ -+ icp_ocfDrvPtrAndLenToBufferList(((struct uio *)(crp-> -+ crp_buf))-> -+ uio_iov[0].iov_base, -+ ((struct uio *)(crp-> -+ crp_buf))-> -+ uio_iov[0].iov_len, -+ &(drvOpData-> -+ srcBuffer)); -+ -+ drvOpData->bufferType = CRYPTO_F_IOV; -+ -+ } else { -+ DPRINTK("%s():Unable to handle IOVs with lengths of " -+ "greater than one!\n", __FUNCTION__); -+ crp->crp_etype = EINVAL; -+ goto err; -+ } -+ -+ } else { -+ icp_ocfDrvPtrAndLenToBufferList(crp->crp_buf, -+ crp->crp_ilen, -+ &(drvOpData->srcBuffer)); -+ -+ drvOpData->bufferType = CRYPTO_BUF_CONTIG; -+ } -+ -+ /* Allocate srcBuffer's private meta data */ -+ if (ICP_OCF_DRV_STATUS_SUCCESS != -+ icp_ocfDrvAllocMetaData(&(drvOpData->srcBuffer), drvOpData)) { -+ EPRINTK("%s() icp_ocfDrvAllocMetaData failed\n", __FUNCTION__); -+ memset(&(drvOpData->lacOpData), 0, sizeof(CpaCySymOpData)); -+ crp->crp_etype = EINVAL; -+ goto err; -+ } -+ -+ /* Perform "in-place" crypto operation */ -+ lacStatus = cpaCySymPerformOp(CPA_INSTANCE_HANDLE_SINGLE, -+ (void *)drvOpData, -+ &(drvOpData->lacOpData), -+ &(drvOpData->srcBuffer), -+ &(drvOpData->srcBuffer), -+ &(drvOpData->verifyResult)); -+ if (CPA_STATUS_RETRY == lacStatus) { -+ DPRINTK("%s(): cpaCySymPerformOp retry, lacStatus = %d\n", -+ __FUNCTION__, lacStatus); -+ memset(&(drvOpData->lacOpData), 0, sizeof(CpaCySymOpData)); -+ crp->crp_etype = ERESTART; -+ goto err; -+ } -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): cpaCySymPerformOp failed, lacStatus = %d\n", -+ __FUNCTION__, lacStatus); -+ memset(&(drvOpData->lacOpData), 0, sizeof(CpaCySymOpData)); -+ crp->crp_etype = EINVAL; -+ goto err; -+ } -+ -+ return 0; //OCF success status value -+ -+ err: -+ if (drvOpData->numBufferListArray > ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) { -+ icp_kfree(drvOpData->srcBuffer.pBuffers); -+ } -+ icp_ocfDrvFreeMetaData(&(drvOpData->srcBuffer)); -+ ICP_CACHE_FREE(drvOpData_zone, drvOpData); -+ -+ return crp->crp_etype; -+} -+ -+/* Name : icp_ocfDrvProcessDataSetup -+ * -+ * Description : This function will setup all the cryptographic operation data -+ * that is required by LAC to execute the operation. -+ */ -+static int icp_ocfDrvProcessDataSetup(struct icp_drvOpData *drvOpData, -+ struct cryptodesc *crp_desc) -+{ -+ CpaCyRandGenOpData randGenOpData; -+ CpaFlatBuffer randData; -+ -+ drvOpData->lacOpData.packetType = CPA_CY_SYM_PACKET_TYPE_FULL; -+ -+ /* Convert from the cryptop to the ICP LAC crypto parameters */ -+ switch (crp_desc->crd_alg) { -+ case CRYPTO_NULL_CBC: -+ drvOpData->lacOpData. -+ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; -+ drvOpData->lacOpData. -+ messageLenToCipherInBytes = crp_desc->crd_len; -+ drvOpData->verifyResult = CPA_FALSE; -+ drvOpData->lacOpData.ivLenInBytes = NULL_BLOCK_LEN; -+ break; -+ case CRYPTO_DES_CBC: -+ drvOpData->lacOpData. -+ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; -+ drvOpData->lacOpData. -+ messageLenToCipherInBytes = crp_desc->crd_len; -+ drvOpData->verifyResult = CPA_FALSE; -+ drvOpData->lacOpData.ivLenInBytes = DES_BLOCK_LEN; -+ break; -+ case CRYPTO_3DES_CBC: -+ drvOpData->lacOpData. -+ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; -+ drvOpData->lacOpData. -+ messageLenToCipherInBytes = crp_desc->crd_len; -+ drvOpData->verifyResult = CPA_FALSE; -+ drvOpData->lacOpData.ivLenInBytes = DES3_BLOCK_LEN; -+ break; -+ case CRYPTO_ARC4: -+ drvOpData->lacOpData. -+ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; -+ drvOpData->lacOpData. -+ messageLenToCipherInBytes = crp_desc->crd_len; -+ drvOpData->verifyResult = CPA_FALSE; -+ drvOpData->lacOpData.ivLenInBytes = ARC4_COUNTER_LEN; -+ break; -+ case CRYPTO_AES_CBC: -+ drvOpData->lacOpData. -+ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; -+ drvOpData->lacOpData. -+ messageLenToCipherInBytes = crp_desc->crd_len; -+ drvOpData->verifyResult = CPA_FALSE; -+ drvOpData->lacOpData.ivLenInBytes = RIJNDAEL128_BLOCK_LEN; -+ break; -+ case CRYPTO_SHA1: -+ case CRYPTO_SHA1_HMAC: -+ case CRYPTO_SHA2_256: -+ case CRYPTO_SHA2_256_HMAC: -+ case CRYPTO_SHA2_384: -+ case CRYPTO_SHA2_384_HMAC: -+ case CRYPTO_SHA2_512: -+ case CRYPTO_SHA2_512_HMAC: -+ case CRYPTO_MD5: -+ case CRYPTO_MD5_HMAC: -+ drvOpData->lacOpData. -+ hashStartSrcOffsetInBytes = crp_desc->crd_skip; -+ drvOpData->lacOpData. -+ messageLenToHashInBytes = crp_desc->crd_len; -+ drvOpData->lacOpData. -+ pDigestResult = -+ icp_ocfDrvDigestPointerFind(drvOpData, crp_desc); -+ -+ if (NULL == drvOpData->lacOpData.pDigestResult) { -+ DPRINTK("%s(): ERROR - could not calculate " -+ "Digest Result memory address\n", __FUNCTION__); -+ return ICP_OCF_DRV_STATUS_FAIL; -+ } -+ -+ drvOpData->lacOpData.digestVerify = CPA_FALSE; -+ break; -+ default: -+ DPRINTK("%s(): Crypto process error - algorithm not " -+ "found \n", __FUNCTION__); -+ return ICP_OCF_DRV_STATUS_FAIL; -+ } -+ -+ /* Figure out what the IV is supposed to be */ -+ if ((crp_desc->crd_alg == CRYPTO_DES_CBC) || -+ (crp_desc->crd_alg == CRYPTO_3DES_CBC) || -+ (crp_desc->crd_alg == CRYPTO_AES_CBC)) { -+ /*ARC4 doesn't use an IV */ -+ if (crp_desc->crd_flags & CRD_F_IV_EXPLICIT) { -+ /* Explicit IV provided to OCF */ -+ drvOpData->lacOpData.pIv = crp_desc->crd_iv; -+ } else { -+ /* IV is not explicitly provided to OCF */ -+ -+ /* Point the LAC OP Data IV pointer to our allocated -+ storage location for this session. */ -+ drvOpData->lacOpData.pIv = drvOpData->ivData; -+ -+ if ((crp_desc->crd_flags & CRD_F_ENCRYPT) && -+ ((crp_desc->crd_flags & CRD_F_IV_PRESENT) == 0)) { -+ -+ /* Encrypting - need to create IV */ -+ randGenOpData.generateBits = CPA_TRUE; -+ randGenOpData.lenInBytes = MAX_IV_LEN_IN_BYTES; -+ -+ icp_ocfDrvPtrAndLenToFlatBuffer((Cpa8U *) -+ drvOpData-> -+ ivData, -+ MAX_IV_LEN_IN_BYTES, -+ &randData); -+ -+ if (CPA_STATUS_SUCCESS != -+ cpaCyRandGen(CPA_INSTANCE_HANDLE_SINGLE, -+ NULL, NULL, -+ &randGenOpData, &randData)) { -+ DPRINTK("%s(): ERROR - Failed to" -+ " generate" -+ " Initialisation Vector\n", -+ __FUNCTION__); -+ return ICP_OCF_DRV_STATUS_FAIL; -+ } -+ -+ crypto_copyback(drvOpData->crp-> -+ crp_flags, -+ drvOpData->crp->crp_buf, -+ crp_desc->crd_inject, -+ drvOpData->lacOpData. -+ ivLenInBytes, -+ (caddr_t) (drvOpData->lacOpData. -+ pIv)); -+ } else { -+ /* Reading IV from buffer */ -+ crypto_copydata(drvOpData->crp-> -+ crp_flags, -+ drvOpData->crp->crp_buf, -+ crp_desc->crd_inject, -+ drvOpData->lacOpData. -+ ivLenInBytes, -+ (caddr_t) (drvOpData->lacOpData. -+ pIv)); -+ } -+ -+ } -+ -+ } -+ -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+} -+ -+/* Name : icp_ocfDrvDigestPointerFind -+ * -+ * Description : This function is used to find the memory address of where the -+ * digest information shall be stored in. Input buffer types are an skbuff, iov -+ * or flat buffer. The address is found using the buffer data start address and -+ * an offset. -+ * -+ * Note: In the case of a linux skbuff, the digest address may exist within -+ * a memory space linked to from the start buffer. These linked memory spaces -+ * must be traversed by the data length offset in order to find the digest start -+ * address. Whether there is enough space for the digest must also be checked. -+ */ -+uint8_t *icp_ocfDrvDigestPointerFind(struct icp_drvOpData * drvOpData, -+ struct cryptodesc * crp_desc) -+{ -+ -+ int offsetInBytes = crp_desc->crd_inject; -+ uint32_t digestSizeInBytes = drvOpData->digestSizeInBytes; -+ uint8_t *flat_buffer_base = NULL; -+ int flat_buffer_length = 0; -+ -+ if (drvOpData->crp->crp_flags & ICP_CRYPTO_F_PACKET_BUF) { -+ -+ return icp_ocfDrvPacketBufferDigestPointerFind(drvOpData, -+ offsetInBytes, -+ digestSizeInBytes); -+ -+ } else { -+ /* IOV or flat buffer */ -+ if (drvOpData->crp->crp_flags & CRYPTO_F_IOV) { -+ /*single IOV check has already been done */ -+ flat_buffer_base = ((struct uio *) -+ (drvOpData->crp->crp_buf))-> -+ uio_iov[0].iov_base; -+ flat_buffer_length = ((struct uio *) -+ (drvOpData->crp->crp_buf))-> -+ uio_iov[0].iov_len; -+ } else { -+ flat_buffer_base = (uint8_t *) drvOpData->crp->crp_buf; -+ flat_buffer_length = drvOpData->crp->crp_ilen; -+ } -+ -+ if (flat_buffer_length < (offsetInBytes + digestSizeInBytes)) { -+ DPRINTK("%s() Not enough space for Digest " -+ "(IOV/Flat Buffer) \n", __FUNCTION__); -+ return NULL; -+ } else { -+ return (uint8_t *) (flat_buffer_base + offsetInBytes); -+ } -+ } -+ DPRINTK("%s() Should not reach this point\n", __FUNCTION__); -+ return NULL; -+} -diff -Nur linux-2.6.36.orig/crypto/ocf/ep80579/Makefile linux-2.6.36/crypto/ocf/ep80579/Makefile ---- linux-2.6.36.orig/crypto/ocf/ep80579/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/ep80579/Makefile 2010-11-09 20:28:04.742495461 +0100 -@@ -0,0 +1,119 @@ -+######################################################################### -+# -+# Targets supported -+# all - builds everything and installs -+# install - identical to all -+# depend - build dependencies -+# clean - clears derived objects except the .depend files -+# distclean- clears all derived objects and the .depend file -+# -+# @par -+# This file is provided under a dual BSD/GPLv2 license. When using or -+# redistributing this file, you may do so under either license. -+# -+# GPL LICENSE SUMMARY -+# -+# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+# -+# This program is free software; you can redistribute it and/or modify -+# it under the terms of version 2 of the GNU General Public License as -+# published by the Free Software Foundation. -+# -+# This program is distributed in the hope that it will be useful, but -+# WITHOUT ANY WARRANTY; without even the implied warranty of -+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+# General Public License for more details. -+# -+# You should have received a copy of the GNU General Public License -+# along with this program; if not, write to the Free Software -+# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. -+# The full GNU General Public License is included in this distribution -+# in the file called LICENSE.GPL. -+# -+# Contact Information: -+# Intel Corporation -+# -+# BSD LICENSE -+# -+# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+# All rights reserved. -+# -+# Redistribution and use in source and binary forms, with or without -+# modification, are permitted provided that the following conditions -+# are met: -+# -+# * Redistributions of source code must retain the above copyright -+# notice, this list of conditions and the following disclaimer. -+# * Redistributions in binary form must reproduce the above copyright -+# notice, this list of conditions and the following disclaimer in -+# the documentation and/or other materials provided with the -+# distribution. -+# * Neither the name of Intel Corporation nor the names of its -+# contributors may be used to endorse or promote products derived -+# from this software without specific prior written permission. -+# -+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+# -+# -+# version: Security.L.1.0.2-229 -+############################################################################ -+ -+ -+####################Common variables and definitions######################## -+ -+ifndef ICP_ROOT -+$(warning ICP_ROOT is undefined. Please set the path to EP80579 release package directory \ -+ "-> setenv ICP_ROOT ") -+all fastdep: -+ : -+else -+ -+ifndef KERNEL_SOURCE_ROOT -+$(error KERNEL_SOURCE_ROOT is undefined. Please set the path to the kernel source directory \ -+ "-> setenv KERNEL_SOURCE_ROOT ") -+endif -+ -+# Ensure The ENV_DIR environmental var is defined. -+ifndef ICP_ENV_DIR -+$(error ICP_ENV_DIR is undefined. Please set the path to EP80579 driver environment.mk file \ -+ "-> setenv ICP_ENV_DIR ") -+endif -+ -+#Add your project environment Makefile -+include ${ICP_ENV_DIR}/environment.mk -+ -+#include the makefile with all the default and common Make variable definitions -+include ${ICP_BUILDSYSTEM_PATH}/build_files/common.mk -+ -+#Add the name for the executable, Library or Module output definitions -+OUTPUT_NAME= icp_ocf -+ -+# List of Source Files to be compiled -+SOURCES= icp_common.c icp_sym.c icp_asym.c icp_ocf_linux.c -+ -+#common includes between all supported OSes -+INCLUDES= -I ${ICP_API_DIR} -I${ICP_LAC_API} \ -+-I${ICP_OCF_SRC_DIR} -+ -+# The location of the os level makefile needs to be changed. -+include ${ICP_ENV_DIR}/${ICP_OS}_${ICP_OS_LEVEL}.mk -+ -+# On the line directly below list the outputs you wish to build for, -+# e.g "lib_static lib_shared exe module" as shown below -+install: module -+ -+###################Include rules makefiles######################## -+include ${ICP_BUILDSYSTEM_PATH}/build_files/rules.mk -+###################End of Rules inclusion######################### -+ -+endif -diff -Nur linux-2.6.36.orig/crypto/ocf/hifn/hifn7751.c linux-2.6.36/crypto/ocf/hifn/hifn7751.c ---- linux-2.6.36.orig/crypto/ocf/hifn/hifn7751.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/hifn/hifn7751.c 2010-11-09 20:28:04.752495537 +0100 -@@ -0,0 +1,2976 @@ -+/* $OpenBSD: hifn7751.c,v 1.120 2002/05/17 00:33:34 deraadt Exp $ */ -+ -+/*- -+ * Invertex AEON / Hifn 7751 driver -+ * Copyright (c) 1999 Invertex Inc. All rights reserved. -+ * Copyright (c) 1999 Theo de Raadt -+ * Copyright (c) 2000-2001 Network Security Technologies, Inc. -+ * http://www.netsec.net -+ * Copyright (c) 2003 Hifn Inc. -+ * -+ * This driver is based on a previous driver by Invertex, for which they -+ * requested: Please send any comments, feedback, bug-fixes, or feature -+ * requests to software@invertex.com. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored in part by the Defense Advanced Research Projects -+ * Agency (DARPA) and Air Force Research Laboratory, Air Force -+ * Materiel Command, USAF, under agreement number F30602-01-2-0537. -+ * -+ * -+__FBSDID("$FreeBSD: src/sys/dev/hifn/hifn7751.c,v 1.40 2007/03/21 03:42:49 sam Exp $"); -+ */ -+ -+/* -+ * Driver for various Hifn encryption processors. -+ */ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+ -+#if 1 -+#define DPRINTF(a...) if (hifn_debug) { \ -+ printk("%s: ", sc ? \ -+ device_get_nameunit(sc->sc_dev) : "hifn"); \ -+ printk(a); \ -+ } else -+#else -+#define DPRINTF(a...) -+#endif -+ -+static inline int -+pci_get_revid(struct pci_dev *dev) -+{ -+ u8 rid = 0; -+ pci_read_config_byte(dev, PCI_REVISION_ID, &rid); -+ return rid; -+} -+ -+static struct hifn_stats hifnstats; -+ -+#define debug hifn_debug -+int hifn_debug = 0; -+module_param(hifn_debug, int, 0644); -+MODULE_PARM_DESC(hifn_debug, "Enable debug"); -+ -+int hifn_maxbatch = 1; -+module_param(hifn_maxbatch, int, 0644); -+MODULE_PARM_DESC(hifn_maxbatch, "max ops to batch w/o interrupt"); -+ -+int hifn_cache_linesize = 0x10; -+module_param(hifn_cache_linesize, int, 0444); -+MODULE_PARM_DESC(hifn_cache_linesize, "PCI config cache line size"); -+ -+#ifdef MODULE_PARM -+char *hifn_pllconfig = NULL; -+MODULE_PARM(hifn_pllconfig, "s"); -+#else -+char hifn_pllconfig[32]; /* This setting is RO after loading */ -+module_param_string(hifn_pllconfig, hifn_pllconfig, 32, 0444); -+#endif -+MODULE_PARM_DESC(hifn_pllconfig, "PLL config, ie., pci66, ext33, ..."); -+ -+#ifdef HIFN_VULCANDEV -+#include -+#include -+ -+static struct cdevsw vulcanpk_cdevsw; /* forward declaration */ -+#endif -+ -+/* -+ * Prototypes and count for the pci_device structure -+ */ -+static int hifn_probe(struct pci_dev *dev, const struct pci_device_id *ent); -+static void hifn_remove(struct pci_dev *dev); -+ -+static int hifn_newsession(device_t, u_int32_t *, struct cryptoini *); -+static int hifn_freesession(device_t, u_int64_t); -+static int hifn_process(device_t, struct cryptop *, int); -+ -+static device_method_t hifn_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, hifn_newsession), -+ DEVMETHOD(cryptodev_freesession,hifn_freesession), -+ DEVMETHOD(cryptodev_process, hifn_process), -+}; -+ -+static void hifn_reset_board(struct hifn_softc *, int); -+static void hifn_reset_puc(struct hifn_softc *); -+static void hifn_puc_wait(struct hifn_softc *); -+static int hifn_enable_crypto(struct hifn_softc *); -+static void hifn_set_retry(struct hifn_softc *sc); -+static void hifn_init_dma(struct hifn_softc *); -+static void hifn_init_pci_registers(struct hifn_softc *); -+static int hifn_sramsize(struct hifn_softc *); -+static int hifn_dramsize(struct hifn_softc *); -+static int hifn_ramtype(struct hifn_softc *); -+static void hifn_sessions(struct hifn_softc *); -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) -+static irqreturn_t hifn_intr(int irq, void *arg); -+#else -+static irqreturn_t hifn_intr(int irq, void *arg, struct pt_regs *regs); -+#endif -+static u_int hifn_write_command(struct hifn_command *, u_int8_t *); -+static u_int32_t hifn_next_signature(u_int32_t a, u_int cnt); -+static void hifn_callback(struct hifn_softc *, struct hifn_command *, u_int8_t *); -+static int hifn_crypto(struct hifn_softc *, struct hifn_command *, struct cryptop *, int); -+static int hifn_readramaddr(struct hifn_softc *, int, u_int8_t *); -+static int hifn_writeramaddr(struct hifn_softc *, int, u_int8_t *); -+static int hifn_dmamap_load_src(struct hifn_softc *, struct hifn_command *); -+static int hifn_dmamap_load_dst(struct hifn_softc *, struct hifn_command *); -+static int hifn_init_pubrng(struct hifn_softc *); -+static void hifn_tick(unsigned long arg); -+static void hifn_abort(struct hifn_softc *); -+static void hifn_alloc_slot(struct hifn_softc *, int *, int *, int *, int *); -+ -+static void hifn_write_reg_0(struct hifn_softc *, bus_size_t, u_int32_t); -+static void hifn_write_reg_1(struct hifn_softc *, bus_size_t, u_int32_t); -+ -+#ifdef CONFIG_OCF_RANDOMHARVEST -+static int hifn_read_random(void *arg, u_int32_t *buf, int len); -+#endif -+ -+#define HIFN_MAX_CHIPS 8 -+static struct hifn_softc *hifn_chip_idx[HIFN_MAX_CHIPS]; -+ -+static __inline u_int32_t -+READ_REG_0(struct hifn_softc *sc, bus_size_t reg) -+{ -+ u_int32_t v = readl(sc->sc_bar0 + reg); -+ sc->sc_bar0_lastreg = (bus_size_t) -1; -+ return (v); -+} -+#define WRITE_REG_0(sc, reg, val) hifn_write_reg_0(sc, reg, val) -+ -+static __inline u_int32_t -+READ_REG_1(struct hifn_softc *sc, bus_size_t reg) -+{ -+ u_int32_t v = readl(sc->sc_bar1 + reg); -+ sc->sc_bar1_lastreg = (bus_size_t) -1; -+ return (v); -+} -+#define WRITE_REG_1(sc, reg, val) hifn_write_reg_1(sc, reg, val) -+ -+/* -+ * map in a given buffer (great on some arches :-) -+ */ -+ -+static int -+pci_map_uio(struct hifn_softc *sc, struct hifn_operand *buf, struct uio *uio) -+{ -+ struct iovec *iov = uio->uio_iov; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ buf->mapsize = 0; -+ for (buf->nsegs = 0; buf->nsegs < uio->uio_iovcnt; ) { -+ buf->segs[buf->nsegs].ds_addr = pci_map_single(sc->sc_pcidev, -+ iov->iov_base, iov->iov_len, -+ PCI_DMA_BIDIRECTIONAL); -+ buf->segs[buf->nsegs].ds_len = iov->iov_len; -+ buf->mapsize += iov->iov_len; -+ iov++; -+ buf->nsegs++; -+ } -+ /* identify this buffer by the first segment */ -+ buf->map = (void *) buf->segs[0].ds_addr; -+ return(0); -+} -+ -+/* -+ * map in a given sk_buff -+ */ -+ -+static int -+pci_map_skb(struct hifn_softc *sc,struct hifn_operand *buf,struct sk_buff *skb) -+{ -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ buf->mapsize = 0; -+ -+ buf->segs[0].ds_addr = pci_map_single(sc->sc_pcidev, -+ skb->data, skb_headlen(skb), PCI_DMA_BIDIRECTIONAL); -+ buf->segs[0].ds_len = skb_headlen(skb); -+ buf->mapsize += buf->segs[0].ds_len; -+ -+ buf->nsegs = 1; -+ -+ for (i = 0; i < skb_shinfo(skb)->nr_frags; ) { -+ buf->segs[buf->nsegs].ds_len = skb_shinfo(skb)->frags[i].size; -+ buf->segs[buf->nsegs].ds_addr = pci_map_single(sc->sc_pcidev, -+ page_address(skb_shinfo(skb)->frags[i].page) + -+ skb_shinfo(skb)->frags[i].page_offset, -+ buf->segs[buf->nsegs].ds_len, PCI_DMA_BIDIRECTIONAL); -+ buf->mapsize += buf->segs[buf->nsegs].ds_len; -+ buf->nsegs++; -+ } -+ -+ /* identify this buffer by the first segment */ -+ buf->map = (void *) buf->segs[0].ds_addr; -+ return(0); -+} -+ -+/* -+ * map in a given contiguous buffer -+ */ -+ -+static int -+pci_map_buf(struct hifn_softc *sc,struct hifn_operand *buf, void *b, int len) -+{ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ buf->mapsize = 0; -+ buf->segs[0].ds_addr = pci_map_single(sc->sc_pcidev, -+ b, len, PCI_DMA_BIDIRECTIONAL); -+ buf->segs[0].ds_len = len; -+ buf->mapsize += buf->segs[0].ds_len; -+ buf->nsegs = 1; -+ -+ /* identify this buffer by the first segment */ -+ buf->map = (void *) buf->segs[0].ds_addr; -+ return(0); -+} -+ -+#if 0 /* not needed at this time */ -+static void -+pci_sync_iov(struct hifn_softc *sc, struct hifn_operand *buf) -+{ -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ for (i = 0; i < buf->nsegs; i++) -+ pci_dma_sync_single_for_cpu(sc->sc_pcidev, buf->segs[i].ds_addr, -+ buf->segs[i].ds_len, PCI_DMA_BIDIRECTIONAL); -+} -+#endif -+ -+static void -+pci_unmap_buf(struct hifn_softc *sc, struct hifn_operand *buf) -+{ -+ int i; -+ DPRINTF("%s()\n", __FUNCTION__); -+ for (i = 0; i < buf->nsegs; i++) { -+ pci_unmap_single(sc->sc_pcidev, buf->segs[i].ds_addr, -+ buf->segs[i].ds_len, PCI_DMA_BIDIRECTIONAL); -+ buf->segs[i].ds_addr = 0; -+ buf->segs[i].ds_len = 0; -+ } -+ buf->nsegs = 0; -+ buf->mapsize = 0; -+ buf->map = 0; -+} -+ -+static const char* -+hifn_partname(struct hifn_softc *sc) -+{ -+ /* XXX sprintf numbers when not decoded */ -+ switch (pci_get_vendor(sc->sc_pcidev)) { -+ case PCI_VENDOR_HIFN: -+ switch (pci_get_device(sc->sc_pcidev)) { -+ case PCI_PRODUCT_HIFN_6500: return "Hifn 6500"; -+ case PCI_PRODUCT_HIFN_7751: return "Hifn 7751"; -+ case PCI_PRODUCT_HIFN_7811: return "Hifn 7811"; -+ case PCI_PRODUCT_HIFN_7951: return "Hifn 7951"; -+ case PCI_PRODUCT_HIFN_7955: return "Hifn 7955"; -+ case PCI_PRODUCT_HIFN_7956: return "Hifn 7956"; -+ } -+ return "Hifn unknown-part"; -+ case PCI_VENDOR_INVERTEX: -+ switch (pci_get_device(sc->sc_pcidev)) { -+ case PCI_PRODUCT_INVERTEX_AEON: return "Invertex AEON"; -+ } -+ return "Invertex unknown-part"; -+ case PCI_VENDOR_NETSEC: -+ switch (pci_get_device(sc->sc_pcidev)) { -+ case PCI_PRODUCT_NETSEC_7751: return "NetSec 7751"; -+ } -+ return "NetSec unknown-part"; -+ } -+ return "Unknown-vendor unknown-part"; -+} -+ -+static u_int -+checkmaxmin(struct pci_dev *dev, const char *what, u_int v, u_int min, u_int max) -+{ -+ struct hifn_softc *sc = pci_get_drvdata(dev); -+ if (v > max) { -+ device_printf(sc->sc_dev, "Warning, %s %u out of range, " -+ "using max %u\n", what, v, max); -+ v = max; -+ } else if (v < min) { -+ device_printf(sc->sc_dev, "Warning, %s %u out of range, " -+ "using min %u\n", what, v, min); -+ v = min; -+ } -+ return v; -+} -+ -+/* -+ * Select PLL configuration for 795x parts. This is complicated in -+ * that we cannot determine the optimal parameters without user input. -+ * The reference clock is derived from an external clock through a -+ * multiplier. The external clock is either the host bus (i.e. PCI) -+ * or an external clock generator. When using the PCI bus we assume -+ * the clock is either 33 or 66 MHz; for an external source we cannot -+ * tell the speed. -+ * -+ * PLL configuration is done with a string: "pci" for PCI bus, or "ext" -+ * for an external source, followed by the frequency. We calculate -+ * the appropriate multiplier and PLL register contents accordingly. -+ * When no configuration is given we default to "pci66" since that -+ * always will allow the card to work. If a card is using the PCI -+ * bus clock and in a 33MHz slot then it will be operating at half -+ * speed until the correct information is provided. -+ * -+ * We use a default setting of "ext66" because according to Mike Ham -+ * of HiFn, almost every board in existence has an external crystal -+ * populated at 66Mhz. Using PCI can be a problem on modern motherboards, -+ * because PCI33 can have clocks from 0 to 33Mhz, and some have -+ * non-PCI-compliant spread-spectrum clocks, which can confuse the pll. -+ */ -+static void -+hifn_getpllconfig(struct pci_dev *dev, u_int *pll) -+{ -+ const char *pllspec = hifn_pllconfig; -+ u_int freq, mul, fl, fh; -+ u_int32_t pllconfig; -+ char *nxt; -+ -+ if (pllspec == NULL) -+ pllspec = "ext66"; -+ fl = 33, fh = 66; -+ pllconfig = 0; -+ if (strncmp(pllspec, "ext", 3) == 0) { -+ pllspec += 3; -+ pllconfig |= HIFN_PLL_REF_SEL; -+ switch (pci_get_device(dev)) { -+ case PCI_PRODUCT_HIFN_7955: -+ case PCI_PRODUCT_HIFN_7956: -+ fl = 20, fh = 100; -+ break; -+#ifdef notyet -+ case PCI_PRODUCT_HIFN_7954: -+ fl = 20, fh = 66; -+ break; -+#endif -+ } -+ } else if (strncmp(pllspec, "pci", 3) == 0) -+ pllspec += 3; -+ freq = strtoul(pllspec, &nxt, 10); -+ if (nxt == pllspec) -+ freq = 66; -+ else -+ freq = checkmaxmin(dev, "frequency", freq, fl, fh); -+ /* -+ * Calculate multiplier. We target a Fck of 266 MHz, -+ * allowing only even values, possibly rounded down. -+ * Multipliers > 8 must set the charge pump current. -+ */ -+ mul = checkmaxmin(dev, "PLL divisor", (266 / freq) &~ 1, 2, 12); -+ pllconfig |= (mul / 2 - 1) << HIFN_PLL_ND_SHIFT; -+ if (mul > 8) -+ pllconfig |= HIFN_PLL_IS; -+ *pll = pllconfig; -+} -+ -+/* -+ * Attach an interface that successfully probed. -+ */ -+static int -+hifn_probe(struct pci_dev *dev, const struct pci_device_id *ent) -+{ -+ struct hifn_softc *sc = NULL; -+ char rbase; -+ u_int16_t ena, rev; -+ int rseg, rc; -+ unsigned long mem_start, mem_len; -+ static int num_chips = 0; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (pci_enable_device(dev) < 0) -+ return(-ENODEV); -+ -+ if (pci_set_mwi(dev)) -+ return(-ENODEV); -+ -+ if (!dev->irq) { -+ printk("hifn: found device with no IRQ assigned. check BIOS settings!"); -+ pci_disable_device(dev); -+ return(-ENODEV); -+ } -+ -+ sc = (struct hifn_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); -+ if (!sc) -+ return(-ENOMEM); -+ memset(sc, 0, sizeof(*sc)); -+ -+ softc_device_init(sc, "hifn", num_chips, hifn_methods); -+ -+ sc->sc_pcidev = dev; -+ sc->sc_irq = -1; -+ sc->sc_cid = -1; -+ sc->sc_num = num_chips++; -+ if (sc->sc_num < HIFN_MAX_CHIPS) -+ hifn_chip_idx[sc->sc_num] = sc; -+ -+ pci_set_drvdata(sc->sc_pcidev, sc); -+ -+ spin_lock_init(&sc->sc_mtx); -+ -+ /* XXX handle power management */ -+ -+ /* -+ * The 7951 and 795x have a random number generator and -+ * public key support; note this. -+ */ -+ if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && -+ (pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 || -+ pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 || -+ pci_get_device(dev) == PCI_PRODUCT_HIFN_7956)) -+ sc->sc_flags = HIFN_HAS_RNG | HIFN_HAS_PUBLIC; -+ /* -+ * The 7811 has a random number generator and -+ * we also note it's identity 'cuz of some quirks. -+ */ -+ if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && -+ pci_get_device(dev) == PCI_PRODUCT_HIFN_7811) -+ sc->sc_flags |= HIFN_IS_7811 | HIFN_HAS_RNG; -+ -+ /* -+ * The 795x parts support AES. -+ */ -+ if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && -+ (pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 || -+ pci_get_device(dev) == PCI_PRODUCT_HIFN_7956)) { -+ sc->sc_flags |= HIFN_IS_7956 | HIFN_HAS_AES; -+ /* -+ * Select PLL configuration. This depends on the -+ * bus and board design and must be manually configured -+ * if the default setting is unacceptable. -+ */ -+ hifn_getpllconfig(dev, &sc->sc_pllconfig); -+ } -+ -+ /* -+ * Setup PCI resources. Note that we record the bus -+ * tag and handle for each register mapping, this is -+ * used by the READ_REG_0, WRITE_REG_0, READ_REG_1, -+ * and WRITE_REG_1 macros throughout the driver. -+ */ -+ mem_start = pci_resource_start(sc->sc_pcidev, 0); -+ mem_len = pci_resource_len(sc->sc_pcidev, 0); -+ sc->sc_bar0 = (ocf_iomem_t) ioremap(mem_start, mem_len); -+ if (!sc->sc_bar0) { -+ device_printf(sc->sc_dev, "cannot map bar%d register space\n", 0); -+ goto fail; -+ } -+ sc->sc_bar0_lastreg = (bus_size_t) -1; -+ -+ mem_start = pci_resource_start(sc->sc_pcidev, 1); -+ mem_len = pci_resource_len(sc->sc_pcidev, 1); -+ sc->sc_bar1 = (ocf_iomem_t) ioremap(mem_start, mem_len); -+ if (!sc->sc_bar1) { -+ device_printf(sc->sc_dev, "cannot map bar%d register space\n", 1); -+ goto fail; -+ } -+ sc->sc_bar1_lastreg = (bus_size_t) -1; -+ -+ /* fix up the bus size */ -+ if (pci_set_dma_mask(dev, DMA_32BIT_MASK)) { -+ device_printf(sc->sc_dev, "No usable DMA configuration, aborting.\n"); -+ goto fail; -+ } -+ if (pci_set_consistent_dma_mask(dev, DMA_32BIT_MASK)) { -+ device_printf(sc->sc_dev, -+ "No usable consistent DMA configuration, aborting.\n"); -+ goto fail; -+ } -+ -+ hifn_set_retry(sc); -+ -+ /* -+ * Setup the area where the Hifn DMA's descriptors -+ * and associated data structures. -+ */ -+ sc->sc_dma = (struct hifn_dma *) pci_alloc_consistent(dev, -+ sizeof(*sc->sc_dma), -+ &sc->sc_dma_physaddr); -+ if (!sc->sc_dma) { -+ device_printf(sc->sc_dev, "cannot alloc sc_dma\n"); -+ goto fail; -+ } -+ bzero(sc->sc_dma, sizeof(*sc->sc_dma)); -+ -+ /* -+ * Reset the board and do the ``secret handshake'' -+ * to enable the crypto support. Then complete the -+ * initialization procedure by setting up the interrupt -+ * and hooking in to the system crypto support so we'll -+ * get used for system services like the crypto device, -+ * IPsec, RNG device, etc. -+ */ -+ hifn_reset_board(sc, 0); -+ -+ if (hifn_enable_crypto(sc) != 0) { -+ device_printf(sc->sc_dev, "crypto enabling failed\n"); -+ goto fail; -+ } -+ hifn_reset_puc(sc); -+ -+ hifn_init_dma(sc); -+ hifn_init_pci_registers(sc); -+ -+ pci_set_master(sc->sc_pcidev); -+ -+ /* XXX can't dynamically determine ram type for 795x; force dram */ -+ if (sc->sc_flags & HIFN_IS_7956) -+ sc->sc_drammodel = 1; -+ else if (hifn_ramtype(sc)) -+ goto fail; -+ -+ if (sc->sc_drammodel == 0) -+ hifn_sramsize(sc); -+ else -+ hifn_dramsize(sc); -+ -+ /* -+ * Workaround for NetSec 7751 rev A: half ram size because two -+ * of the address lines were left floating -+ */ -+ if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC && -+ pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751 && -+ pci_get_revid(dev) == 0x61) /*XXX???*/ -+ sc->sc_ramsize >>= 1; -+ -+ /* -+ * Arrange the interrupt line. -+ */ -+ rc = request_irq(dev->irq, hifn_intr, IRQF_SHARED, "hifn", sc); -+ if (rc) { -+ device_printf(sc->sc_dev, "could not map interrupt: %d\n", rc); -+ goto fail; -+ } -+ sc->sc_irq = dev->irq; -+ -+ hifn_sessions(sc); -+ -+ /* -+ * NB: Keep only the low 16 bits; this masks the chip id -+ * from the 7951. -+ */ -+ rev = READ_REG_1(sc, HIFN_1_REVID) & 0xffff; -+ -+ rseg = sc->sc_ramsize / 1024; -+ rbase = 'K'; -+ if (sc->sc_ramsize >= (1024 * 1024)) { -+ rbase = 'M'; -+ rseg /= 1024; -+ } -+ device_printf(sc->sc_dev, "%s, rev %u, %d%cB %cram", -+ hifn_partname(sc), rev, -+ rseg, rbase, sc->sc_drammodel ? 'd' : 's'); -+ if (sc->sc_flags & HIFN_IS_7956) -+ printf(", pll=0x%x<%s clk, %ux mult>", -+ sc->sc_pllconfig, -+ sc->sc_pllconfig & HIFN_PLL_REF_SEL ? "ext" : "pci", -+ 2 + 2*((sc->sc_pllconfig & HIFN_PLL_ND) >> 11)); -+ printf("\n"); -+ -+ sc->sc_cid = crypto_get_driverid(softc_get_device(sc),CRYPTOCAP_F_HARDWARE); -+ if (sc->sc_cid < 0) { -+ device_printf(sc->sc_dev, "could not get crypto driver id\n"); -+ goto fail; -+ } -+ -+ WRITE_REG_0(sc, HIFN_0_PUCNFG, -+ READ_REG_0(sc, HIFN_0_PUCNFG) | HIFN_PUCNFG_CHIPID); -+ ena = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; -+ -+ switch (ena) { -+ case HIFN_PUSTAT_ENA_2: -+ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0); -+ if (sc->sc_flags & HIFN_HAS_AES) -+ crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); -+ /*FALLTHROUGH*/ -+ case HIFN_PUSTAT_ENA_1: -+ crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); -+ break; -+ } -+ -+ if (sc->sc_flags & (HIFN_HAS_PUBLIC | HIFN_HAS_RNG)) -+ hifn_init_pubrng(sc); -+ -+ init_timer(&sc->sc_tickto); -+ sc->sc_tickto.function = hifn_tick; -+ sc->sc_tickto.data = (unsigned long) sc->sc_num; -+ mod_timer(&sc->sc_tickto, jiffies + HZ); -+ -+ return (0); -+ -+fail: -+ if (sc->sc_cid >= 0) -+ crypto_unregister_all(sc->sc_cid); -+ if (sc->sc_irq != -1) -+ free_irq(sc->sc_irq, sc); -+ if (sc->sc_dma) { -+ /* Turn off DMA polling */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | -+ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); -+ -+ pci_free_consistent(sc->sc_pcidev, -+ sizeof(*sc->sc_dma), -+ sc->sc_dma, sc->sc_dma_physaddr); -+ } -+ kfree(sc); -+ return (-ENXIO); -+} -+ -+/* -+ * Detach an interface that successfully probed. -+ */ -+static void -+hifn_remove(struct pci_dev *dev) -+{ -+ struct hifn_softc *sc = pci_get_drvdata(dev); -+ unsigned long l_flags; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ KASSERT(sc != NULL, ("hifn_detach: null software carrier!")); -+ -+ /* disable interrupts */ -+ HIFN_LOCK(sc); -+ WRITE_REG_1(sc, HIFN_1_DMA_IER, 0); -+ HIFN_UNLOCK(sc); -+ -+ /*XXX other resources */ -+ del_timer_sync(&sc->sc_tickto); -+ -+ /* Turn off DMA polling */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | -+ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); -+ -+ crypto_unregister_all(sc->sc_cid); -+ -+ free_irq(sc->sc_irq, sc); -+ -+ pci_free_consistent(sc->sc_pcidev, sizeof(*sc->sc_dma), -+ sc->sc_dma, sc->sc_dma_physaddr); -+} -+ -+ -+static int -+hifn_init_pubrng(struct hifn_softc *sc) -+{ -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if ((sc->sc_flags & HIFN_IS_7811) == 0) { -+ /* Reset 7951 public key/rng engine */ -+ WRITE_REG_1(sc, HIFN_1_PUB_RESET, -+ READ_REG_1(sc, HIFN_1_PUB_RESET) | HIFN_PUBRST_RESET); -+ -+ for (i = 0; i < 100; i++) { -+ DELAY(1000); -+ if ((READ_REG_1(sc, HIFN_1_PUB_RESET) & -+ HIFN_PUBRST_RESET) == 0) -+ break; -+ } -+ -+ if (i == 100) { -+ device_printf(sc->sc_dev, "public key init failed\n"); -+ return (1); -+ } -+ } -+ -+ /* Enable the rng, if available */ -+#ifdef CONFIG_OCF_RANDOMHARVEST -+ if (sc->sc_flags & HIFN_HAS_RNG) { -+ if (sc->sc_flags & HIFN_IS_7811) { -+ u_int32_t r; -+ r = READ_REG_1(sc, HIFN_1_7811_RNGENA); -+ if (r & HIFN_7811_RNGENA_ENA) { -+ r &= ~HIFN_7811_RNGENA_ENA; -+ WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); -+ } -+ WRITE_REG_1(sc, HIFN_1_7811_RNGCFG, -+ HIFN_7811_RNGCFG_DEFL); -+ r |= HIFN_7811_RNGENA_ENA; -+ WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); -+ } else -+ WRITE_REG_1(sc, HIFN_1_RNG_CONFIG, -+ READ_REG_1(sc, HIFN_1_RNG_CONFIG) | -+ HIFN_RNGCFG_ENA); -+ -+ sc->sc_rngfirst = 1; -+ crypto_rregister(sc->sc_cid, hifn_read_random, sc); -+ } -+#endif -+ -+ /* Enable public key engine, if available */ -+ if (sc->sc_flags & HIFN_HAS_PUBLIC) { -+ WRITE_REG_1(sc, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE); -+ sc->sc_dmaier |= HIFN_DMAIER_PUBDONE; -+ WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); -+#ifdef HIFN_VULCANDEV -+ sc->sc_pkdev = make_dev(&vulcanpk_cdevsw, 0, -+ UID_ROOT, GID_WHEEL, 0666, -+ "vulcanpk"); -+ sc->sc_pkdev->si_drv1 = sc; -+#endif -+ } -+ -+ return (0); -+} -+ -+#ifdef CONFIG_OCF_RANDOMHARVEST -+static int -+hifn_read_random(void *arg, u_int32_t *buf, int len) -+{ -+ struct hifn_softc *sc = (struct hifn_softc *) arg; -+ u_int32_t sts; -+ int i, rc = 0; -+ -+ if (len <= 0) -+ return rc; -+ -+ if (sc->sc_flags & HIFN_IS_7811) { -+ /* ONLY VALID ON 7811!!!! */ -+ for (i = 0; i < 5; i++) { -+ sts = READ_REG_1(sc, HIFN_1_7811_RNGSTS); -+ if (sts & HIFN_7811_RNGSTS_UFL) { -+ device_printf(sc->sc_dev, -+ "RNG underflow: disabling\n"); -+ /* DAVIDM perhaps return -1 */ -+ break; -+ } -+ if ((sts & HIFN_7811_RNGSTS_RDY) == 0) -+ break; -+ -+ /* -+ * There are at least two words in the RNG FIFO -+ * at this point. -+ */ -+ if (rc < len) -+ buf[rc++] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); -+ if (rc < len) -+ buf[rc++] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); -+ } -+ } else -+ buf[rc++] = READ_REG_1(sc, HIFN_1_RNG_DATA); -+ -+ /* NB: discard first data read */ -+ if (sc->sc_rngfirst) { -+ sc->sc_rngfirst = 0; -+ rc = 0; -+ } -+ -+ return(rc); -+} -+#endif /* CONFIG_OCF_RANDOMHARVEST */ -+ -+static void -+hifn_puc_wait(struct hifn_softc *sc) -+{ -+ int i; -+ int reg = HIFN_0_PUCTRL; -+ -+ if (sc->sc_flags & HIFN_IS_7956) { -+ reg = HIFN_0_PUCTRL2; -+ } -+ -+ for (i = 5000; i > 0; i--) { -+ DELAY(1); -+ if (!(READ_REG_0(sc, reg) & HIFN_PUCTRL_RESET)) -+ break; -+ } -+ if (!i) -+ device_printf(sc->sc_dev, "proc unit did not reset(0x%x)\n", -+ READ_REG_0(sc, HIFN_0_PUCTRL)); -+} -+ -+/* -+ * Reset the processing unit. -+ */ -+static void -+hifn_reset_puc(struct hifn_softc *sc) -+{ -+ /* Reset processing unit */ -+ int reg = HIFN_0_PUCTRL; -+ -+ if (sc->sc_flags & HIFN_IS_7956) { -+ reg = HIFN_0_PUCTRL2; -+ } -+ WRITE_REG_0(sc, reg, HIFN_PUCTRL_DMAENA); -+ -+ hifn_puc_wait(sc); -+} -+ -+/* -+ * Set the Retry and TRDY registers; note that we set them to -+ * zero because the 7811 locks up when forced to retry (section -+ * 3.6 of "Specification Update SU-0014-04". Not clear if we -+ * should do this for all Hifn parts, but it doesn't seem to hurt. -+ */ -+static void -+hifn_set_retry(struct hifn_softc *sc) -+{ -+ DPRINTF("%s()\n", __FUNCTION__); -+ /* NB: RETRY only responds to 8-bit reads/writes */ -+ pci_write_config_byte(sc->sc_pcidev, HIFN_RETRY_TIMEOUT, 0); -+ pci_write_config_dword(sc->sc_pcidev, HIFN_TRDY_TIMEOUT, 0); -+ /* piggy back the cache line setting here */ -+ pci_write_config_byte(sc->sc_pcidev, PCI_CACHE_LINE_SIZE, hifn_cache_linesize); -+} -+ -+/* -+ * Resets the board. Values in the regesters are left as is -+ * from the reset (i.e. initial values are assigned elsewhere). -+ */ -+static void -+hifn_reset_board(struct hifn_softc *sc, int full) -+{ -+ u_int32_t reg; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ /* -+ * Set polling in the DMA configuration register to zero. 0x7 avoids -+ * resetting the board and zeros out the other fields. -+ */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | -+ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); -+ -+ /* -+ * Now that polling has been disabled, we have to wait 1 ms -+ * before resetting the board. -+ */ -+ DELAY(1000); -+ -+ /* Reset the DMA unit */ -+ if (full) { -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE); -+ DELAY(1000); -+ } else { -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, -+ HIFN_DMACNFG_MODE | HIFN_DMACNFG_MSTRESET); -+ hifn_reset_puc(sc); -+ } -+ -+ KASSERT(sc->sc_dma != NULL, ("hifn_reset_board: null DMA tag!")); -+ bzero(sc->sc_dma, sizeof(*sc->sc_dma)); -+ -+ /* Bring dma unit out of reset */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | -+ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); -+ -+ hifn_puc_wait(sc); -+ hifn_set_retry(sc); -+ -+ if (sc->sc_flags & HIFN_IS_7811) { -+ for (reg = 0; reg < 1000; reg++) { -+ if (READ_REG_1(sc, HIFN_1_7811_MIPSRST) & -+ HIFN_MIPSRST_CRAMINIT) -+ break; -+ DELAY(1000); -+ } -+ if (reg == 1000) -+ device_printf(sc->sc_dev, ": cram init timeout\n"); -+ } else { -+ /* set up DMA configuration register #2 */ -+ /* turn off all PK and BAR0 swaps */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG2, -+ (3 << HIFN_DMACNFG2_INIT_WRITE_BURST_SHIFT)| -+ (3 << HIFN_DMACNFG2_INIT_READ_BURST_SHIFT)| -+ (2 << HIFN_DMACNFG2_TGT_WRITE_BURST_SHIFT)| -+ (2 << HIFN_DMACNFG2_TGT_READ_BURST_SHIFT)); -+ } -+} -+ -+static u_int32_t -+hifn_next_signature(u_int32_t a, u_int cnt) -+{ -+ int i; -+ u_int32_t v; -+ -+ for (i = 0; i < cnt; i++) { -+ -+ /* get the parity */ -+ v = a & 0x80080125; -+ v ^= v >> 16; -+ v ^= v >> 8; -+ v ^= v >> 4; -+ v ^= v >> 2; -+ v ^= v >> 1; -+ -+ a = (v & 1) ^ (a << 1); -+ } -+ -+ return a; -+} -+ -+ -+/* -+ * Checks to see if crypto is already enabled. If crypto isn't enable, -+ * "hifn_enable_crypto" is called to enable it. The check is important, -+ * as enabling crypto twice will lock the board. -+ */ -+static int -+hifn_enable_crypto(struct hifn_softc *sc) -+{ -+ u_int32_t dmacfg, ramcfg, encl, addr, i; -+ char offtbl[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00 }; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ ramcfg = READ_REG_0(sc, HIFN_0_PUCNFG); -+ dmacfg = READ_REG_1(sc, HIFN_1_DMA_CNFG); -+ -+ /* -+ * The RAM config register's encrypt level bit needs to be set before -+ * every read performed on the encryption level register. -+ */ -+ WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); -+ -+ encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; -+ -+ /* -+ * Make sure we don't re-unlock. Two unlocks kills chip until the -+ * next reboot. -+ */ -+ if (encl == HIFN_PUSTAT_ENA_1 || encl == HIFN_PUSTAT_ENA_2) { -+#ifdef HIFN_DEBUG -+ if (hifn_debug) -+ device_printf(sc->sc_dev, -+ "Strong crypto already enabled!\n"); -+#endif -+ goto report; -+ } -+ -+ if (encl != 0 && encl != HIFN_PUSTAT_ENA_0) { -+#ifdef HIFN_DEBUG -+ if (hifn_debug) -+ device_printf(sc->sc_dev, -+ "Unknown encryption level 0x%x\n", encl); -+#endif -+ return 1; -+ } -+ -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_UNLOCK | -+ HIFN_DMACNFG_MSTRESET | HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); -+ DELAY(1000); -+ addr = READ_REG_1(sc, HIFN_UNLOCK_SECRET1); -+ DELAY(1000); -+ WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, 0); -+ DELAY(1000); -+ -+ for (i = 0; i <= 12; i++) { -+ addr = hifn_next_signature(addr, offtbl[i] + 0x101); -+ WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, addr); -+ -+ DELAY(1000); -+ } -+ -+ WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); -+ encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; -+ -+#ifdef HIFN_DEBUG -+ if (hifn_debug) { -+ if (encl != HIFN_PUSTAT_ENA_1 && encl != HIFN_PUSTAT_ENA_2) -+ device_printf(sc->sc_dev, "Engine is permanently " -+ "locked until next system reset!\n"); -+ else -+ device_printf(sc->sc_dev, "Engine enabled " -+ "successfully!\n"); -+ } -+#endif -+ -+report: -+ WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg); -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, dmacfg); -+ -+ switch (encl) { -+ case HIFN_PUSTAT_ENA_1: -+ case HIFN_PUSTAT_ENA_2: -+ break; -+ case HIFN_PUSTAT_ENA_0: -+ default: -+ device_printf(sc->sc_dev, "disabled\n"); -+ break; -+ } -+ -+ return 0; -+} -+ -+/* -+ * Give initial values to the registers listed in the "Register Space" -+ * section of the HIFN Software Development reference manual. -+ */ -+static void -+hifn_init_pci_registers(struct hifn_softc *sc) -+{ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ /* write fixed values needed by the Initialization registers */ -+ WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA); -+ WRITE_REG_0(sc, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD); -+ WRITE_REG_0(sc, HIFN_0_PUIER, HIFN_PUIER_DSTOVER); -+ -+ /* write all 4 ring address registers */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CRAR, sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, cmdr[0])); -+ WRITE_REG_1(sc, HIFN_1_DMA_SRAR, sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, srcr[0])); -+ WRITE_REG_1(sc, HIFN_1_DMA_DRAR, sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, dstr[0])); -+ WRITE_REG_1(sc, HIFN_1_DMA_RRAR, sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, resr[0])); -+ -+ DELAY(2000); -+ -+ /* write status register */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CSR, -+ HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS | -+ HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS | -+ HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST | -+ HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER | -+ HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST | -+ HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER | -+ HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST | -+ HIFN_DMACSR_S_WAIT | -+ HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST | -+ HIFN_DMACSR_C_WAIT | -+ HIFN_DMACSR_ENGINE | -+ ((sc->sc_flags & HIFN_HAS_PUBLIC) ? -+ HIFN_DMACSR_PUBDONE : 0) | -+ ((sc->sc_flags & HIFN_IS_7811) ? -+ HIFN_DMACSR_ILLW | HIFN_DMACSR_ILLR : 0)); -+ -+ sc->sc_d_busy = sc->sc_r_busy = sc->sc_s_busy = sc->sc_c_busy = 0; -+ sc->sc_dmaier |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT | -+ HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER | -+ HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT | -+ ((sc->sc_flags & HIFN_IS_7811) ? -+ HIFN_DMAIER_ILLW | HIFN_DMAIER_ILLR : 0); -+ sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; -+ WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); -+ -+ -+ if (sc->sc_flags & HIFN_IS_7956) { -+ u_int32_t pll; -+ -+ WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING | -+ HIFN_PUCNFG_TCALLPHASES | -+ HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32); -+ -+ /* turn off the clocks and insure bypass is set */ -+ pll = READ_REG_1(sc, HIFN_1_PLL); -+ pll = (pll &~ (HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL)) -+ | HIFN_PLL_BP | HIFN_PLL_MBSET; -+ WRITE_REG_1(sc, HIFN_1_PLL, pll); -+ DELAY(10*1000); /* 10ms */ -+ -+ /* change configuration */ -+ pll = (pll &~ HIFN_PLL_CONFIG) | sc->sc_pllconfig; -+ WRITE_REG_1(sc, HIFN_1_PLL, pll); -+ DELAY(10*1000); /* 10ms */ -+ -+ /* disable bypass */ -+ pll &= ~HIFN_PLL_BP; -+ WRITE_REG_1(sc, HIFN_1_PLL, pll); -+ /* enable clocks with new configuration */ -+ pll |= HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL; -+ WRITE_REG_1(sc, HIFN_1_PLL, pll); -+ } else { -+ WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING | -+ HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES | -+ HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 | -+ (sc->sc_drammodel ? HIFN_PUCNFG_DRAM : HIFN_PUCNFG_SRAM)); -+ } -+ -+ WRITE_REG_0(sc, HIFN_0_PUISR, HIFN_PUISR_DSTOVER); -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | -+ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST | -+ ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) | -+ ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL)); -+} -+ -+/* -+ * The maximum number of sessions supported by the card -+ * is dependent on the amount of context ram, which -+ * encryption algorithms are enabled, and how compression -+ * is configured. This should be configured before this -+ * routine is called. -+ */ -+static void -+hifn_sessions(struct hifn_softc *sc) -+{ -+ u_int32_t pucnfg; -+ int ctxsize; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ pucnfg = READ_REG_0(sc, HIFN_0_PUCNFG); -+ -+ if (pucnfg & HIFN_PUCNFG_COMPSING) { -+ if (pucnfg & HIFN_PUCNFG_ENCCNFG) -+ ctxsize = 128; -+ else -+ ctxsize = 512; -+ /* -+ * 7955/7956 has internal context memory of 32K -+ */ -+ if (sc->sc_flags & HIFN_IS_7956) -+ sc->sc_maxses = 32768 / ctxsize; -+ else -+ sc->sc_maxses = 1 + -+ ((sc->sc_ramsize - 32768) / ctxsize); -+ } else -+ sc->sc_maxses = sc->sc_ramsize / 16384; -+ -+ if (sc->sc_maxses > 2048) -+ sc->sc_maxses = 2048; -+} -+ -+/* -+ * Determine ram type (sram or dram). Board should be just out of a reset -+ * state when this is called. -+ */ -+static int -+hifn_ramtype(struct hifn_softc *sc) -+{ -+ u_int8_t data[8], dataexpect[8]; -+ int i; -+ -+ for (i = 0; i < sizeof(data); i++) -+ data[i] = dataexpect[i] = 0x55; -+ if (hifn_writeramaddr(sc, 0, data)) -+ return (-1); -+ if (hifn_readramaddr(sc, 0, data)) -+ return (-1); -+ if (bcmp(data, dataexpect, sizeof(data)) != 0) { -+ sc->sc_drammodel = 1; -+ return (0); -+ } -+ -+ for (i = 0; i < sizeof(data); i++) -+ data[i] = dataexpect[i] = 0xaa; -+ if (hifn_writeramaddr(sc, 0, data)) -+ return (-1); -+ if (hifn_readramaddr(sc, 0, data)) -+ return (-1); -+ if (bcmp(data, dataexpect, sizeof(data)) != 0) { -+ sc->sc_drammodel = 1; -+ return (0); -+ } -+ -+ return (0); -+} -+ -+#define HIFN_SRAM_MAX (32 << 20) -+#define HIFN_SRAM_STEP_SIZE 16384 -+#define HIFN_SRAM_GRANULARITY (HIFN_SRAM_MAX / HIFN_SRAM_STEP_SIZE) -+ -+static int -+hifn_sramsize(struct hifn_softc *sc) -+{ -+ u_int32_t a; -+ u_int8_t data[8]; -+ u_int8_t dataexpect[sizeof(data)]; -+ int32_t i; -+ -+ for (i = 0; i < sizeof(data); i++) -+ data[i] = dataexpect[i] = i ^ 0x5a; -+ -+ for (i = HIFN_SRAM_GRANULARITY - 1; i >= 0; i--) { -+ a = i * HIFN_SRAM_STEP_SIZE; -+ bcopy(&i, data, sizeof(i)); -+ hifn_writeramaddr(sc, a, data); -+ } -+ -+ for (i = 0; i < HIFN_SRAM_GRANULARITY; i++) { -+ a = i * HIFN_SRAM_STEP_SIZE; -+ bcopy(&i, dataexpect, sizeof(i)); -+ if (hifn_readramaddr(sc, a, data) < 0) -+ return (0); -+ if (bcmp(data, dataexpect, sizeof(data)) != 0) -+ return (0); -+ sc->sc_ramsize = a + HIFN_SRAM_STEP_SIZE; -+ } -+ -+ return (0); -+} -+ -+/* -+ * XXX For dram boards, one should really try all of the -+ * HIFN_PUCNFG_DSZ_*'s. This just assumes that PUCNFG -+ * is already set up correctly. -+ */ -+static int -+hifn_dramsize(struct hifn_softc *sc) -+{ -+ u_int32_t cnfg; -+ -+ if (sc->sc_flags & HIFN_IS_7956) { -+ /* -+ * 7955/7956 have a fixed internal ram of only 32K. -+ */ -+ sc->sc_ramsize = 32768; -+ } else { -+ cnfg = READ_REG_0(sc, HIFN_0_PUCNFG) & -+ HIFN_PUCNFG_DRAMMASK; -+ sc->sc_ramsize = 1 << ((cnfg >> 13) + 18); -+ } -+ return (0); -+} -+ -+static void -+hifn_alloc_slot(struct hifn_softc *sc, int *cmdp, int *srcp, int *dstp, int *resp) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (dma->cmdi == HIFN_D_CMD_RSIZE) { -+ dma->cmdi = 0; -+ dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); -+ wmb(); -+ dma->cmdr[HIFN_D_CMD_RSIZE].l |= htole32(HIFN_D_VALID); -+ HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, -+ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); -+ } -+ *cmdp = dma->cmdi++; -+ dma->cmdk = dma->cmdi; -+ -+ if (dma->srci == HIFN_D_SRC_RSIZE) { -+ dma->srci = 0; -+ dma->srcr[HIFN_D_SRC_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); -+ wmb(); -+ dma->srcr[HIFN_D_SRC_RSIZE].l |= htole32(HIFN_D_VALID); -+ HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, -+ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); -+ } -+ *srcp = dma->srci++; -+ dma->srck = dma->srci; -+ -+ if (dma->dsti == HIFN_D_DST_RSIZE) { -+ dma->dsti = 0; -+ dma->dstr[HIFN_D_DST_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); -+ wmb(); -+ dma->dstr[HIFN_D_DST_RSIZE].l |= htole32(HIFN_D_VALID); -+ HIFN_DSTR_SYNC(sc, HIFN_D_DST_RSIZE, -+ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); -+ } -+ *dstp = dma->dsti++; -+ dma->dstk = dma->dsti; -+ -+ if (dma->resi == HIFN_D_RES_RSIZE) { -+ dma->resi = 0; -+ dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); -+ wmb(); -+ dma->resr[HIFN_D_RES_RSIZE].l |= htole32(HIFN_D_VALID); -+ HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, -+ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); -+ } -+ *resp = dma->resi++; -+ dma->resk = dma->resi; -+} -+ -+static int -+hifn_writeramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ hifn_base_command_t wc; -+ const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; -+ int r, cmdi, resi, srci, dsti; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ wc.masks = htole16(3 << 13); -+ wc.session_num = htole16(addr >> 14); -+ wc.total_source_count = htole16(8); -+ wc.total_dest_count = htole16(addr & 0x3fff); -+ -+ hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); -+ -+ WRITE_REG_1(sc, HIFN_1_DMA_CSR, -+ HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | -+ HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); -+ -+ /* build write command */ -+ bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); -+ *(hifn_base_command_t *)dma->command_bufs[cmdi] = wc; -+ bcopy(data, &dma->test_src, sizeof(dma->test_src)); -+ -+ dma->srcr[srci].p = htole32(sc->sc_dma_physaddr -+ + offsetof(struct hifn_dma, test_src)); -+ dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr -+ + offsetof(struct hifn_dma, test_dst)); -+ -+ dma->cmdr[cmdi].l = htole32(16 | masks); -+ dma->srcr[srci].l = htole32(8 | masks); -+ dma->dstr[dsti].l = htole32(4 | masks); -+ dma->resr[resi].l = htole32(4 | masks); -+ -+ for (r = 10000; r >= 0; r--) { -+ DELAY(10); -+ if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) -+ break; -+ } -+ if (r == 0) { -+ device_printf(sc->sc_dev, "writeramaddr -- " -+ "result[%d](addr %d) still valid\n", resi, addr); -+ r = -1; -+ return (-1); -+ } else -+ r = 0; -+ -+ WRITE_REG_1(sc, HIFN_1_DMA_CSR, -+ HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | -+ HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); -+ -+ return (r); -+} -+ -+static int -+hifn_readramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ hifn_base_command_t rc; -+ const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; -+ int r, cmdi, srci, dsti, resi; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ rc.masks = htole16(2 << 13); -+ rc.session_num = htole16(addr >> 14); -+ rc.total_source_count = htole16(addr & 0x3fff); -+ rc.total_dest_count = htole16(8); -+ -+ hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); -+ -+ WRITE_REG_1(sc, HIFN_1_DMA_CSR, -+ HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | -+ HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); -+ -+ bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); -+ *(hifn_base_command_t *)dma->command_bufs[cmdi] = rc; -+ -+ dma->srcr[srci].p = htole32(sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, test_src)); -+ dma->test_src = 0; -+ dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, test_dst)); -+ dma->test_dst = 0; -+ dma->cmdr[cmdi].l = htole32(8 | masks); -+ dma->srcr[srci].l = htole32(8 | masks); -+ dma->dstr[dsti].l = htole32(8 | masks); -+ dma->resr[resi].l = htole32(HIFN_MAX_RESULT | masks); -+ -+ for (r = 10000; r >= 0; r--) { -+ DELAY(10); -+ if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) -+ break; -+ } -+ if (r == 0) { -+ device_printf(sc->sc_dev, "readramaddr -- " -+ "result[%d](addr %d) still valid\n", resi, addr); -+ r = -1; -+ } else { -+ r = 0; -+ bcopy(&dma->test_dst, data, sizeof(dma->test_dst)); -+ } -+ -+ WRITE_REG_1(sc, HIFN_1_DMA_CSR, -+ HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | -+ HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); -+ -+ return (r); -+} -+ -+/* -+ * Initialize the descriptor rings. -+ */ -+static void -+hifn_init_dma(struct hifn_softc *sc) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ hifn_set_retry(sc); -+ -+ /* initialize static pointer values */ -+ for (i = 0; i < HIFN_D_CMD_RSIZE; i++) -+ dma->cmdr[i].p = htole32(sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, command_bufs[i][0])); -+ for (i = 0; i < HIFN_D_RES_RSIZE; i++) -+ dma->resr[i].p = htole32(sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, result_bufs[i][0])); -+ -+ dma->cmdr[HIFN_D_CMD_RSIZE].p = -+ htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, cmdr[0])); -+ dma->srcr[HIFN_D_SRC_RSIZE].p = -+ htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, srcr[0])); -+ dma->dstr[HIFN_D_DST_RSIZE].p = -+ htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, dstr[0])); -+ dma->resr[HIFN_D_RES_RSIZE].p = -+ htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, resr[0])); -+ -+ dma->cmdu = dma->srcu = dma->dstu = dma->resu = 0; -+ dma->cmdi = dma->srci = dma->dsti = dma->resi = 0; -+ dma->cmdk = dma->srck = dma->dstk = dma->resk = 0; -+} -+ -+/* -+ * Writes out the raw command buffer space. Returns the -+ * command buffer size. -+ */ -+static u_int -+hifn_write_command(struct hifn_command *cmd, u_int8_t *buf) -+{ -+ struct hifn_softc *sc = NULL; -+ u_int8_t *buf_pos; -+ hifn_base_command_t *base_cmd; -+ hifn_mac_command_t *mac_cmd; -+ hifn_crypt_command_t *cry_cmd; -+ int using_mac, using_crypt, len, ivlen; -+ u_int32_t dlen, slen; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ buf_pos = buf; -+ using_mac = cmd->base_masks & HIFN_BASE_CMD_MAC; -+ using_crypt = cmd->base_masks & HIFN_BASE_CMD_CRYPT; -+ -+ base_cmd = (hifn_base_command_t *)buf_pos; -+ base_cmd->masks = htole16(cmd->base_masks); -+ slen = cmd->src_mapsize; -+ if (cmd->sloplen) -+ dlen = cmd->dst_mapsize - cmd->sloplen + sizeof(u_int32_t); -+ else -+ dlen = cmd->dst_mapsize; -+ base_cmd->total_source_count = htole16(slen & HIFN_BASE_CMD_LENMASK_LO); -+ base_cmd->total_dest_count = htole16(dlen & HIFN_BASE_CMD_LENMASK_LO); -+ dlen >>= 16; -+ slen >>= 16; -+ base_cmd->session_num = htole16( -+ ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) | -+ ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M)); -+ buf_pos += sizeof(hifn_base_command_t); -+ -+ if (using_mac) { -+ mac_cmd = (hifn_mac_command_t *)buf_pos; -+ dlen = cmd->maccrd->crd_len; -+ mac_cmd->source_count = htole16(dlen & 0xffff); -+ dlen >>= 16; -+ mac_cmd->masks = htole16(cmd->mac_masks | -+ ((dlen << HIFN_MAC_CMD_SRCLEN_S) & HIFN_MAC_CMD_SRCLEN_M)); -+ mac_cmd->header_skip = htole16(cmd->maccrd->crd_skip); -+ mac_cmd->reserved = 0; -+ buf_pos += sizeof(hifn_mac_command_t); -+ } -+ -+ if (using_crypt) { -+ cry_cmd = (hifn_crypt_command_t *)buf_pos; -+ dlen = cmd->enccrd->crd_len; -+ cry_cmd->source_count = htole16(dlen & 0xffff); -+ dlen >>= 16; -+ cry_cmd->masks = htole16(cmd->cry_masks | -+ ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) & HIFN_CRYPT_CMD_SRCLEN_M)); -+ cry_cmd->header_skip = htole16(cmd->enccrd->crd_skip); -+ cry_cmd->reserved = 0; -+ buf_pos += sizeof(hifn_crypt_command_t); -+ } -+ -+ if (using_mac && cmd->mac_masks & HIFN_MAC_CMD_NEW_KEY) { -+ bcopy(cmd->mac, buf_pos, HIFN_MAC_KEY_LENGTH); -+ buf_pos += HIFN_MAC_KEY_LENGTH; -+ } -+ -+ if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_KEY) { -+ switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) { -+ case HIFN_CRYPT_CMD_ALG_3DES: -+ bcopy(cmd->ck, buf_pos, HIFN_3DES_KEY_LENGTH); -+ buf_pos += HIFN_3DES_KEY_LENGTH; -+ break; -+ case HIFN_CRYPT_CMD_ALG_DES: -+ bcopy(cmd->ck, buf_pos, HIFN_DES_KEY_LENGTH); -+ buf_pos += HIFN_DES_KEY_LENGTH; -+ break; -+ case HIFN_CRYPT_CMD_ALG_RC4: -+ len = 256; -+ do { -+ int clen; -+ -+ clen = MIN(cmd->cklen, len); -+ bcopy(cmd->ck, buf_pos, clen); -+ len -= clen; -+ buf_pos += clen; -+ } while (len > 0); -+ bzero(buf_pos, 4); -+ buf_pos += 4; -+ break; -+ case HIFN_CRYPT_CMD_ALG_AES: -+ /* -+ * AES keys are variable 128, 192 and -+ * 256 bits (16, 24 and 32 bytes). -+ */ -+ bcopy(cmd->ck, buf_pos, cmd->cklen); -+ buf_pos += cmd->cklen; -+ break; -+ } -+ } -+ -+ if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_IV) { -+ switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) { -+ case HIFN_CRYPT_CMD_ALG_AES: -+ ivlen = HIFN_AES_IV_LENGTH; -+ break; -+ default: -+ ivlen = HIFN_IV_LENGTH; -+ break; -+ } -+ bcopy(cmd->iv, buf_pos, ivlen); -+ buf_pos += ivlen; -+ } -+ -+ if ((cmd->base_masks & (HIFN_BASE_CMD_MAC|HIFN_BASE_CMD_CRYPT)) == 0) { -+ bzero(buf_pos, 8); -+ buf_pos += 8; -+ } -+ -+ return (buf_pos - buf); -+} -+ -+static int -+hifn_dmamap_aligned(struct hifn_operand *op) -+{ -+ struct hifn_softc *sc = NULL; -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ for (i = 0; i < op->nsegs; i++) { -+ if (op->segs[i].ds_addr & 3) -+ return (0); -+ if ((i != (op->nsegs - 1)) && (op->segs[i].ds_len & 3)) -+ return (0); -+ } -+ return (1); -+} -+ -+static __inline int -+hifn_dmamap_dstwrap(struct hifn_softc *sc, int idx) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ -+ if (++idx == HIFN_D_DST_RSIZE) { -+ dma->dstr[idx].l = htole32(HIFN_D_VALID | HIFN_D_JUMP | -+ HIFN_D_MASKDONEIRQ); -+ HIFN_DSTR_SYNC(sc, idx, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ idx = 0; -+ } -+ return (idx); -+} -+ -+static int -+hifn_dmamap_load_dst(struct hifn_softc *sc, struct hifn_command *cmd) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ struct hifn_operand *dst = &cmd->dst; -+ u_int32_t p, l; -+ int idx, used = 0, i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ idx = dma->dsti; -+ for (i = 0; i < dst->nsegs - 1; i++) { -+ dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); -+ dma->dstr[idx].l = htole32(HIFN_D_MASKDONEIRQ | dst->segs[i].ds_len); -+ wmb(); -+ dma->dstr[idx].l |= htole32(HIFN_D_VALID); -+ HIFN_DSTR_SYNC(sc, idx, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ used++; -+ -+ idx = hifn_dmamap_dstwrap(sc, idx); -+ } -+ -+ if (cmd->sloplen == 0) { -+ p = dst->segs[i].ds_addr; -+ l = HIFN_D_MASKDONEIRQ | HIFN_D_LAST | -+ dst->segs[i].ds_len; -+ } else { -+ p = sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, slop[cmd->slopidx]); -+ l = HIFN_D_MASKDONEIRQ | HIFN_D_LAST | -+ sizeof(u_int32_t); -+ -+ if ((dst->segs[i].ds_len - cmd->sloplen) != 0) { -+ dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); -+ dma->dstr[idx].l = htole32(HIFN_D_MASKDONEIRQ | -+ (dst->segs[i].ds_len - cmd->sloplen)); -+ wmb(); -+ dma->dstr[idx].l |= htole32(HIFN_D_VALID); -+ HIFN_DSTR_SYNC(sc, idx, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ used++; -+ -+ idx = hifn_dmamap_dstwrap(sc, idx); -+ } -+ } -+ dma->dstr[idx].p = htole32(p); -+ dma->dstr[idx].l = htole32(l); -+ wmb(); -+ dma->dstr[idx].l |= htole32(HIFN_D_VALID); -+ HIFN_DSTR_SYNC(sc, idx, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ used++; -+ -+ idx = hifn_dmamap_dstwrap(sc, idx); -+ -+ dma->dsti = idx; -+ dma->dstu += used; -+ return (idx); -+} -+ -+static __inline int -+hifn_dmamap_srcwrap(struct hifn_softc *sc, int idx) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ -+ if (++idx == HIFN_D_SRC_RSIZE) { -+ dma->srcr[idx].l = htole32(HIFN_D_VALID | -+ HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); -+ HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, -+ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); -+ idx = 0; -+ } -+ return (idx); -+} -+ -+static int -+hifn_dmamap_load_src(struct hifn_softc *sc, struct hifn_command *cmd) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ struct hifn_operand *src = &cmd->src; -+ int idx, i; -+ u_int32_t last = 0; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ idx = dma->srci; -+ for (i = 0; i < src->nsegs; i++) { -+ if (i == src->nsegs - 1) -+ last = HIFN_D_LAST; -+ -+ dma->srcr[idx].p = htole32(src->segs[i].ds_addr); -+ dma->srcr[idx].l = htole32(src->segs[i].ds_len | -+ HIFN_D_MASKDONEIRQ | last); -+ wmb(); -+ dma->srcr[idx].l |= htole32(HIFN_D_VALID); -+ HIFN_SRCR_SYNC(sc, idx, -+ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); -+ -+ idx = hifn_dmamap_srcwrap(sc, idx); -+ } -+ dma->srci = idx; -+ dma->srcu += src->nsegs; -+ return (idx); -+} -+ -+ -+static int -+hifn_crypto( -+ struct hifn_softc *sc, -+ struct hifn_command *cmd, -+ struct cryptop *crp, -+ int hint) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ u_int32_t cmdlen, csr; -+ int cmdi, resi, err = 0; -+ unsigned long l_flags; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ /* -+ * need 1 cmd, and 1 res -+ * -+ * NB: check this first since it's easy. -+ */ -+ HIFN_LOCK(sc); -+ if ((dma->cmdu + 1) > HIFN_D_CMD_RSIZE || -+ (dma->resu + 1) > HIFN_D_RES_RSIZE) { -+#ifdef HIFN_DEBUG -+ if (hifn_debug) { -+ device_printf(sc->sc_dev, -+ "cmd/result exhaustion, cmdu %u resu %u\n", -+ dma->cmdu, dma->resu); -+ } -+#endif -+ hifnstats.hst_nomem_cr++; -+ sc->sc_needwakeup |= CRYPTO_SYMQ; -+ HIFN_UNLOCK(sc); -+ return (ERESTART); -+ } -+ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ if (pci_map_skb(sc, &cmd->src, cmd->src_skb)) { -+ hifnstats.hst_nomem_load++; -+ err = ENOMEM; -+ goto err_srcmap1; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ if (pci_map_uio(sc, &cmd->src, cmd->src_io)) { -+ hifnstats.hst_nomem_load++; -+ err = ENOMEM; -+ goto err_srcmap1; -+ } -+ } else { -+ if (pci_map_buf(sc, &cmd->src, cmd->src_buf, crp->crp_ilen)) { -+ hifnstats.hst_nomem_load++; -+ err = ENOMEM; -+ goto err_srcmap1; -+ } -+ } -+ -+ if (hifn_dmamap_aligned(&cmd->src)) { -+ cmd->sloplen = cmd->src_mapsize & 3; -+ cmd->dst = cmd->src; -+ } else { -+ if (crp->crp_flags & CRYPTO_F_IOV) { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ err = EINVAL; -+ goto err_srcmap; -+ } else if (crp->crp_flags & CRYPTO_F_SKBUF) { -+#ifdef NOTYET -+ int totlen, len; -+ struct mbuf *m, *m0, *mlast; -+ -+ KASSERT(cmd->dst_m == cmd->src_m, -+ ("hifn_crypto: dst_m initialized improperly")); -+ hifnstats.hst_unaligned++; -+ /* -+ * Source is not aligned on a longword boundary. -+ * Copy the data to insure alignment. If we fail -+ * to allocate mbufs or clusters while doing this -+ * we return ERESTART so the operation is requeued -+ * at the crypto later, but only if there are -+ * ops already posted to the hardware; otherwise we -+ * have no guarantee that we'll be re-entered. -+ */ -+ totlen = cmd->src_mapsize; -+ if (cmd->src_m->m_flags & M_PKTHDR) { -+ len = MHLEN; -+ MGETHDR(m0, M_DONTWAIT, MT_DATA); -+ if (m0 && !m_dup_pkthdr(m0, cmd->src_m, M_DONTWAIT)) { -+ m_free(m0); -+ m0 = NULL; -+ } -+ } else { -+ len = MLEN; -+ MGET(m0, M_DONTWAIT, MT_DATA); -+ } -+ if (m0 == NULL) { -+ hifnstats.hst_nomem_mbuf++; -+ err = dma->cmdu ? ERESTART : ENOMEM; -+ goto err_srcmap; -+ } -+ if (totlen >= MINCLSIZE) { -+ MCLGET(m0, M_DONTWAIT); -+ if ((m0->m_flags & M_EXT) == 0) { -+ hifnstats.hst_nomem_mcl++; -+ err = dma->cmdu ? ERESTART : ENOMEM; -+ m_freem(m0); -+ goto err_srcmap; -+ } -+ len = MCLBYTES; -+ } -+ totlen -= len; -+ m0->m_pkthdr.len = m0->m_len = len; -+ mlast = m0; -+ -+ while (totlen > 0) { -+ MGET(m, M_DONTWAIT, MT_DATA); -+ if (m == NULL) { -+ hifnstats.hst_nomem_mbuf++; -+ err = dma->cmdu ? ERESTART : ENOMEM; -+ m_freem(m0); -+ goto err_srcmap; -+ } -+ len = MLEN; -+ if (totlen >= MINCLSIZE) { -+ MCLGET(m, M_DONTWAIT); -+ if ((m->m_flags & M_EXT) == 0) { -+ hifnstats.hst_nomem_mcl++; -+ err = dma->cmdu ? ERESTART : ENOMEM; -+ mlast->m_next = m; -+ m_freem(m0); -+ goto err_srcmap; -+ } -+ len = MCLBYTES; -+ } -+ -+ m->m_len = len; -+ m0->m_pkthdr.len += len; -+ totlen -= len; -+ -+ mlast->m_next = m; -+ mlast = m; -+ } -+ cmd->dst_m = m0; -+#else -+ device_printf(sc->sc_dev, -+ "%s,%d: CRYPTO_F_SKBUF unaligned not implemented\n", -+ __FILE__, __LINE__); -+ err = EINVAL; -+ goto err_srcmap; -+#endif -+ } else { -+ device_printf(sc->sc_dev, -+ "%s,%d: unaligned contig buffers not implemented\n", -+ __FILE__, __LINE__); -+ err = EINVAL; -+ goto err_srcmap; -+ } -+ } -+ -+ if (cmd->dst_map == NULL) { -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ if (pci_map_skb(sc, &cmd->dst, cmd->dst_skb)) { -+ hifnstats.hst_nomem_map++; -+ err = ENOMEM; -+ goto err_dstmap1; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ if (pci_map_uio(sc, &cmd->dst, cmd->dst_io)) { -+ hifnstats.hst_nomem_load++; -+ err = ENOMEM; -+ goto err_dstmap1; -+ } -+ } else { -+ if (pci_map_buf(sc, &cmd->dst, cmd->dst_buf, crp->crp_ilen)) { -+ hifnstats.hst_nomem_load++; -+ err = ENOMEM; -+ goto err_dstmap1; -+ } -+ } -+ } -+ -+#ifdef HIFN_DEBUG -+ if (hifn_debug) { -+ device_printf(sc->sc_dev, -+ "Entering cmd: stat %8x ien %8x u %d/%d/%d/%d n %d/%d\n", -+ READ_REG_1(sc, HIFN_1_DMA_CSR), -+ READ_REG_1(sc, HIFN_1_DMA_IER), -+ dma->cmdu, dma->srcu, dma->dstu, dma->resu, -+ cmd->src_nsegs, cmd->dst_nsegs); -+ } -+#endif -+ -+#if 0 -+ if (cmd->src_map == cmd->dst_map) { -+ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, -+ BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); -+ } else { -+ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, -+ BUS_DMASYNC_PREWRITE); -+ bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, -+ BUS_DMASYNC_PREREAD); -+ } -+#endif -+ -+ /* -+ * need N src, and N dst -+ */ -+ if ((dma->srcu + cmd->src_nsegs) > HIFN_D_SRC_RSIZE || -+ (dma->dstu + cmd->dst_nsegs + 1) > HIFN_D_DST_RSIZE) { -+#ifdef HIFN_DEBUG -+ if (hifn_debug) { -+ device_printf(sc->sc_dev, -+ "src/dst exhaustion, srcu %u+%u dstu %u+%u\n", -+ dma->srcu, cmd->src_nsegs, -+ dma->dstu, cmd->dst_nsegs); -+ } -+#endif -+ hifnstats.hst_nomem_sd++; -+ err = ERESTART; -+ goto err_dstmap; -+ } -+ -+ if (dma->cmdi == HIFN_D_CMD_RSIZE) { -+ dma->cmdi = 0; -+ dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); -+ wmb(); -+ dma->cmdr[HIFN_D_CMD_RSIZE].l |= htole32(HIFN_D_VALID); -+ HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, -+ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); -+ } -+ cmdi = dma->cmdi++; -+ cmdlen = hifn_write_command(cmd, dma->command_bufs[cmdi]); -+ HIFN_CMD_SYNC(sc, cmdi, BUS_DMASYNC_PREWRITE); -+ -+ /* .p for command/result already set */ -+ dma->cmdr[cmdi].l = htole32(cmdlen | HIFN_D_LAST | -+ HIFN_D_MASKDONEIRQ); -+ wmb(); -+ dma->cmdr[cmdi].l |= htole32(HIFN_D_VALID); -+ HIFN_CMDR_SYNC(sc, cmdi, -+ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); -+ dma->cmdu++; -+ -+ /* -+ * We don't worry about missing an interrupt (which a "command wait" -+ * interrupt salvages us from), unless there is more than one command -+ * in the queue. -+ */ -+ if (dma->cmdu > 1) { -+ sc->sc_dmaier |= HIFN_DMAIER_C_WAIT; -+ WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); -+ } -+ -+ hifnstats.hst_ipackets++; -+ hifnstats.hst_ibytes += cmd->src_mapsize; -+ -+ hifn_dmamap_load_src(sc, cmd); -+ -+ /* -+ * Unlike other descriptors, we don't mask done interrupt from -+ * result descriptor. -+ */ -+#ifdef HIFN_DEBUG -+ if (hifn_debug) -+ device_printf(sc->sc_dev, "load res\n"); -+#endif -+ if (dma->resi == HIFN_D_RES_RSIZE) { -+ dma->resi = 0; -+ dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); -+ wmb(); -+ dma->resr[HIFN_D_RES_RSIZE].l |= htole32(HIFN_D_VALID); -+ HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ } -+ resi = dma->resi++; -+ KASSERT(dma->hifn_commands[resi] == NULL, -+ ("hifn_crypto: command slot %u busy", resi)); -+ dma->hifn_commands[resi] = cmd; -+ HIFN_RES_SYNC(sc, resi, BUS_DMASYNC_PREREAD); -+ if ((hint & CRYPTO_HINT_MORE) && sc->sc_curbatch < hifn_maxbatch) { -+ dma->resr[resi].l = htole32(HIFN_MAX_RESULT | -+ HIFN_D_LAST | HIFN_D_MASKDONEIRQ); -+ wmb(); -+ dma->resr[resi].l |= htole32(HIFN_D_VALID); -+ sc->sc_curbatch++; -+ if (sc->sc_curbatch > hifnstats.hst_maxbatch) -+ hifnstats.hst_maxbatch = sc->sc_curbatch; -+ hifnstats.hst_totbatch++; -+ } else { -+ dma->resr[resi].l = htole32(HIFN_MAX_RESULT | HIFN_D_LAST); -+ wmb(); -+ dma->resr[resi].l |= htole32(HIFN_D_VALID); -+ sc->sc_curbatch = 0; -+ } -+ HIFN_RESR_SYNC(sc, resi, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ dma->resu++; -+ -+ if (cmd->sloplen) -+ cmd->slopidx = resi; -+ -+ hifn_dmamap_load_dst(sc, cmd); -+ -+ csr = 0; -+ if (sc->sc_c_busy == 0) { -+ csr |= HIFN_DMACSR_C_CTRL_ENA; -+ sc->sc_c_busy = 1; -+ } -+ if (sc->sc_s_busy == 0) { -+ csr |= HIFN_DMACSR_S_CTRL_ENA; -+ sc->sc_s_busy = 1; -+ } -+ if (sc->sc_r_busy == 0) { -+ csr |= HIFN_DMACSR_R_CTRL_ENA; -+ sc->sc_r_busy = 1; -+ } -+ if (sc->sc_d_busy == 0) { -+ csr |= HIFN_DMACSR_D_CTRL_ENA; -+ sc->sc_d_busy = 1; -+ } -+ if (csr) -+ WRITE_REG_1(sc, HIFN_1_DMA_CSR, csr); -+ -+#ifdef HIFN_DEBUG -+ if (hifn_debug) { -+ device_printf(sc->sc_dev, "command: stat %8x ier %8x\n", -+ READ_REG_1(sc, HIFN_1_DMA_CSR), -+ READ_REG_1(sc, HIFN_1_DMA_IER)); -+ } -+#endif -+ -+ sc->sc_active = 5; -+ HIFN_UNLOCK(sc); -+ KASSERT(err == 0, ("hifn_crypto: success with error %u", err)); -+ return (err); /* success */ -+ -+err_dstmap: -+ if (cmd->src_map != cmd->dst_map) -+ pci_unmap_buf(sc, &cmd->dst); -+err_dstmap1: -+err_srcmap: -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ if (cmd->src_skb != cmd->dst_skb) -+#ifdef NOTYET -+ m_freem(cmd->dst_m); -+#else -+ device_printf(sc->sc_dev, -+ "%s,%d: CRYPTO_F_SKBUF src != dst not implemented\n", -+ __FILE__, __LINE__); -+#endif -+ } -+ pci_unmap_buf(sc, &cmd->src); -+err_srcmap1: -+ HIFN_UNLOCK(sc); -+ return (err); -+} -+ -+static void -+hifn_tick(unsigned long arg) -+{ -+ struct hifn_softc *sc; -+ unsigned long l_flags; -+ -+ if (arg >= HIFN_MAX_CHIPS) -+ return; -+ sc = hifn_chip_idx[arg]; -+ if (!sc) -+ return; -+ -+ HIFN_LOCK(sc); -+ if (sc->sc_active == 0) { -+ struct hifn_dma *dma = sc->sc_dma; -+ u_int32_t r = 0; -+ -+ if (dma->cmdu == 0 && sc->sc_c_busy) { -+ sc->sc_c_busy = 0; -+ r |= HIFN_DMACSR_C_CTRL_DIS; -+ } -+ if (dma->srcu == 0 && sc->sc_s_busy) { -+ sc->sc_s_busy = 0; -+ r |= HIFN_DMACSR_S_CTRL_DIS; -+ } -+ if (dma->dstu == 0 && sc->sc_d_busy) { -+ sc->sc_d_busy = 0; -+ r |= HIFN_DMACSR_D_CTRL_DIS; -+ } -+ if (dma->resu == 0 && sc->sc_r_busy) { -+ sc->sc_r_busy = 0; -+ r |= HIFN_DMACSR_R_CTRL_DIS; -+ } -+ if (r) -+ WRITE_REG_1(sc, HIFN_1_DMA_CSR, r); -+ } else -+ sc->sc_active--; -+ HIFN_UNLOCK(sc); -+ mod_timer(&sc->sc_tickto, jiffies + HZ); -+} -+ -+static irqreturn_t -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) -+hifn_intr(int irq, void *arg) -+#else -+hifn_intr(int irq, void *arg, struct pt_regs *regs) -+#endif -+{ -+ struct hifn_softc *sc = arg; -+ struct hifn_dma *dma; -+ u_int32_t dmacsr, restart; -+ int i, u; -+ unsigned long l_flags; -+ -+ dmacsr = READ_REG_1(sc, HIFN_1_DMA_CSR); -+ -+ /* Nothing in the DMA unit interrupted */ -+ if ((dmacsr & sc->sc_dmaier) == 0) -+ return IRQ_NONE; -+ -+ HIFN_LOCK(sc); -+ -+ dma = sc->sc_dma; -+ -+#ifdef HIFN_DEBUG -+ if (hifn_debug) { -+ device_printf(sc->sc_dev, -+ "irq: stat %08x ien %08x damier %08x i %d/%d/%d/%d k %d/%d/%d/%d u %d/%d/%d/%d\n", -+ dmacsr, READ_REG_1(sc, HIFN_1_DMA_IER), sc->sc_dmaier, -+ dma->cmdi, dma->srci, dma->dsti, dma->resi, -+ dma->cmdk, dma->srck, dma->dstk, dma->resk, -+ dma->cmdu, dma->srcu, dma->dstu, dma->resu); -+ } -+#endif -+ -+ WRITE_REG_1(sc, HIFN_1_DMA_CSR, dmacsr & sc->sc_dmaier); -+ -+ if ((sc->sc_flags & HIFN_HAS_PUBLIC) && -+ (dmacsr & HIFN_DMACSR_PUBDONE)) -+ WRITE_REG_1(sc, HIFN_1_PUB_STATUS, -+ READ_REG_1(sc, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE); -+ -+ restart = dmacsr & (HIFN_DMACSR_D_OVER | HIFN_DMACSR_R_OVER); -+ if (restart) -+ device_printf(sc->sc_dev, "overrun %x\n", dmacsr); -+ -+ if (sc->sc_flags & HIFN_IS_7811) { -+ if (dmacsr & HIFN_DMACSR_ILLR) -+ device_printf(sc->sc_dev, "illegal read\n"); -+ if (dmacsr & HIFN_DMACSR_ILLW) -+ device_printf(sc->sc_dev, "illegal write\n"); -+ } -+ -+ restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT | -+ HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT); -+ if (restart) { -+ device_printf(sc->sc_dev, "abort, resetting.\n"); -+ hifnstats.hst_abort++; -+ hifn_abort(sc); -+ HIFN_UNLOCK(sc); -+ return IRQ_HANDLED; -+ } -+ -+ if ((dmacsr & HIFN_DMACSR_C_WAIT) && (dma->cmdu == 0)) { -+ /* -+ * If no slots to process and we receive a "waiting on -+ * command" interrupt, we disable the "waiting on command" -+ * (by clearing it). -+ */ -+ sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; -+ WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); -+ } -+ -+ /* clear the rings */ -+ i = dma->resk; u = dma->resu; -+ while (u != 0) { -+ HIFN_RESR_SYNC(sc, i, -+ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); -+ if (dma->resr[i].l & htole32(HIFN_D_VALID)) { -+ HIFN_RESR_SYNC(sc, i, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ break; -+ } -+ -+ if (i != HIFN_D_RES_RSIZE) { -+ struct hifn_command *cmd; -+ u_int8_t *macbuf = NULL; -+ -+ HIFN_RES_SYNC(sc, i, BUS_DMASYNC_POSTREAD); -+ cmd = dma->hifn_commands[i]; -+ KASSERT(cmd != NULL, -+ ("hifn_intr: null command slot %u", i)); -+ dma->hifn_commands[i] = NULL; -+ -+ if (cmd->base_masks & HIFN_BASE_CMD_MAC) { -+ macbuf = dma->result_bufs[i]; -+ macbuf += 12; -+ } -+ -+ hifn_callback(sc, cmd, macbuf); -+ hifnstats.hst_opackets++; -+ u--; -+ } -+ -+ if (++i == (HIFN_D_RES_RSIZE + 1)) -+ i = 0; -+ } -+ dma->resk = i; dma->resu = u; -+ -+ i = dma->srck; u = dma->srcu; -+ while (u != 0) { -+ if (i == HIFN_D_SRC_RSIZE) -+ i = 0; -+ HIFN_SRCR_SYNC(sc, i, -+ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); -+ if (dma->srcr[i].l & htole32(HIFN_D_VALID)) { -+ HIFN_SRCR_SYNC(sc, i, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ break; -+ } -+ i++, u--; -+ } -+ dma->srck = i; dma->srcu = u; -+ -+ i = dma->cmdk; u = dma->cmdu; -+ while (u != 0) { -+ HIFN_CMDR_SYNC(sc, i, -+ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); -+ if (dma->cmdr[i].l & htole32(HIFN_D_VALID)) { -+ HIFN_CMDR_SYNC(sc, i, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ break; -+ } -+ if (i != HIFN_D_CMD_RSIZE) { -+ u--; -+ HIFN_CMD_SYNC(sc, i, BUS_DMASYNC_POSTWRITE); -+ } -+ if (++i == (HIFN_D_CMD_RSIZE + 1)) -+ i = 0; -+ } -+ dma->cmdk = i; dma->cmdu = u; -+ -+ HIFN_UNLOCK(sc); -+ -+ if (sc->sc_needwakeup) { /* XXX check high watermark */ -+ int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); -+#ifdef HIFN_DEBUG -+ if (hifn_debug) -+ device_printf(sc->sc_dev, -+ "wakeup crypto (%x) u %d/%d/%d/%d\n", -+ sc->sc_needwakeup, -+ dma->cmdu, dma->srcu, dma->dstu, dma->resu); -+#endif -+ sc->sc_needwakeup &= ~wakeup; -+ crypto_unblock(sc->sc_cid, wakeup); -+ } -+ -+ return IRQ_HANDLED; -+} -+ -+/* -+ * Allocate a new 'session' and return an encoded session id. 'sidp' -+ * contains our registration id, and should contain an encoded session -+ * id on successful allocation. -+ */ -+static int -+hifn_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) -+{ -+ struct hifn_softc *sc = device_get_softc(dev); -+ struct cryptoini *c; -+ int mac = 0, cry = 0, sesn; -+ struct hifn_session *ses = NULL; -+ unsigned long l_flags; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ KASSERT(sc != NULL, ("hifn_newsession: null softc")); -+ if (sidp == NULL || cri == NULL || sc == NULL) { -+ DPRINTF("%s,%d: %s - EINVAL\n", __FILE__, __LINE__, __FUNCTION__); -+ return (EINVAL); -+ } -+ -+ HIFN_LOCK(sc); -+ if (sc->sc_sessions == NULL) { -+ ses = sc->sc_sessions = (struct hifn_session *)kmalloc(sizeof(*ses), -+ SLAB_ATOMIC); -+ if (ses == NULL) { -+ HIFN_UNLOCK(sc); -+ return (ENOMEM); -+ } -+ sesn = 0; -+ sc->sc_nsessions = 1; -+ } else { -+ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { -+ if (!sc->sc_sessions[sesn].hs_used) { -+ ses = &sc->sc_sessions[sesn]; -+ break; -+ } -+ } -+ -+ if (ses == NULL) { -+ sesn = sc->sc_nsessions; -+ ses = (struct hifn_session *)kmalloc((sesn + 1) * sizeof(*ses), -+ SLAB_ATOMIC); -+ if (ses == NULL) { -+ HIFN_UNLOCK(sc); -+ return (ENOMEM); -+ } -+ bcopy(sc->sc_sessions, ses, sesn * sizeof(*ses)); -+ bzero(sc->sc_sessions, sesn * sizeof(*ses)); -+ kfree(sc->sc_sessions); -+ sc->sc_sessions = ses; -+ ses = &sc->sc_sessions[sesn]; -+ sc->sc_nsessions++; -+ } -+ } -+ HIFN_UNLOCK(sc); -+ -+ bzero(ses, sizeof(*ses)); -+ ses->hs_used = 1; -+ -+ for (c = cri; c != NULL; c = c->cri_next) { -+ switch (c->cri_alg) { -+ case CRYPTO_MD5: -+ case CRYPTO_SHA1: -+ case CRYPTO_MD5_HMAC: -+ case CRYPTO_SHA1_HMAC: -+ if (mac) { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ return (EINVAL); -+ } -+ mac = 1; -+ ses->hs_mlen = c->cri_mlen; -+ if (ses->hs_mlen == 0) { -+ switch (c->cri_alg) { -+ case CRYPTO_MD5: -+ case CRYPTO_MD5_HMAC: -+ ses->hs_mlen = 16; -+ break; -+ case CRYPTO_SHA1: -+ case CRYPTO_SHA1_HMAC: -+ ses->hs_mlen = 20; -+ break; -+ } -+ } -+ break; -+ case CRYPTO_DES_CBC: -+ case CRYPTO_3DES_CBC: -+ case CRYPTO_AES_CBC: -+ /* XXX this may read fewer, does it matter? */ -+ read_random(ses->hs_iv, -+ c->cri_alg == CRYPTO_AES_CBC ? -+ HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH); -+ /*FALLTHROUGH*/ -+ case CRYPTO_ARC4: -+ if (cry) { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ return (EINVAL); -+ } -+ cry = 1; -+ break; -+ default: -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ return (EINVAL); -+ } -+ } -+ if (mac == 0 && cry == 0) { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ return (EINVAL); -+ } -+ -+ *sidp = HIFN_SID(device_get_unit(sc->sc_dev), sesn); -+ -+ return (0); -+} -+ -+/* -+ * Deallocate a session. -+ * XXX this routine should run a zero'd mac/encrypt key into context ram. -+ * XXX to blow away any keys already stored there. -+ */ -+static int -+hifn_freesession(device_t dev, u_int64_t tid) -+{ -+ struct hifn_softc *sc = device_get_softc(dev); -+ int session, error; -+ u_int32_t sid = CRYPTO_SESID2LID(tid); -+ unsigned long l_flags; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ KASSERT(sc != NULL, ("hifn_freesession: null softc")); -+ if (sc == NULL) { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ return (EINVAL); -+ } -+ -+ HIFN_LOCK(sc); -+ session = HIFN_SESSION(sid); -+ if (session < sc->sc_nsessions) { -+ bzero(&sc->sc_sessions[session], sizeof(struct hifn_session)); -+ error = 0; -+ } else { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ error = EINVAL; -+ } -+ HIFN_UNLOCK(sc); -+ -+ return (error); -+} -+ -+static int -+hifn_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ struct hifn_softc *sc = device_get_softc(dev); -+ struct hifn_command *cmd = NULL; -+ int session, err, ivlen; -+ struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (crp == NULL || crp->crp_callback == NULL) { -+ hifnstats.hst_invalid++; -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ return (EINVAL); -+ } -+ session = HIFN_SESSION(crp->crp_sid); -+ -+ if (sc == NULL || session >= sc->sc_nsessions) { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ err = EINVAL; -+ goto errout; -+ } -+ -+ cmd = kmalloc(sizeof(struct hifn_command), SLAB_ATOMIC); -+ if (cmd == NULL) { -+ hifnstats.hst_nomem++; -+ err = ENOMEM; -+ goto errout; -+ } -+ memset(cmd, 0, sizeof(*cmd)); -+ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ cmd->src_skb = (struct sk_buff *)crp->crp_buf; -+ cmd->dst_skb = (struct sk_buff *)crp->crp_buf; -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ cmd->src_io = (struct uio *)crp->crp_buf; -+ cmd->dst_io = (struct uio *)crp->crp_buf; -+ } else { -+ cmd->src_buf = crp->crp_buf; -+ cmd->dst_buf = crp->crp_buf; -+ } -+ -+ crd1 = crp->crp_desc; -+ if (crd1 == NULL) { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ err = EINVAL; -+ goto errout; -+ } -+ crd2 = crd1->crd_next; -+ -+ if (crd2 == NULL) { -+ if (crd1->crd_alg == CRYPTO_MD5_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1 || -+ crd1->crd_alg == CRYPTO_MD5) { -+ maccrd = crd1; -+ enccrd = NULL; -+ } else if (crd1->crd_alg == CRYPTO_DES_CBC || -+ crd1->crd_alg == CRYPTO_3DES_CBC || -+ crd1->crd_alg == CRYPTO_AES_CBC || -+ crd1->crd_alg == CRYPTO_ARC4) { -+ if ((crd1->crd_flags & CRD_F_ENCRYPT) == 0) -+ cmd->base_masks |= HIFN_BASE_CMD_DECODE; -+ maccrd = NULL; -+ enccrd = crd1; -+ } else { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ err = EINVAL; -+ goto errout; -+ } -+ } else { -+ if ((crd1->crd_alg == CRYPTO_MD5_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1_HMAC || -+ crd1->crd_alg == CRYPTO_MD5 || -+ crd1->crd_alg == CRYPTO_SHA1) && -+ (crd2->crd_alg == CRYPTO_DES_CBC || -+ crd2->crd_alg == CRYPTO_3DES_CBC || -+ crd2->crd_alg == CRYPTO_AES_CBC || -+ crd2->crd_alg == CRYPTO_ARC4) && -+ ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { -+ cmd->base_masks = HIFN_BASE_CMD_DECODE; -+ maccrd = crd1; -+ enccrd = crd2; -+ } else if ((crd1->crd_alg == CRYPTO_DES_CBC || -+ crd1->crd_alg == CRYPTO_ARC4 || -+ crd1->crd_alg == CRYPTO_3DES_CBC || -+ crd1->crd_alg == CRYPTO_AES_CBC) && -+ (crd2->crd_alg == CRYPTO_MD5_HMAC || -+ crd2->crd_alg == CRYPTO_SHA1_HMAC || -+ crd2->crd_alg == CRYPTO_MD5 || -+ crd2->crd_alg == CRYPTO_SHA1) && -+ (crd1->crd_flags & CRD_F_ENCRYPT)) { -+ enccrd = crd1; -+ maccrd = crd2; -+ } else { -+ /* -+ * We cannot order the 7751 as requested -+ */ -+ DPRINTF("%s,%d: %s %d,%d,%d - EINVAL\n",__FILE__,__LINE__,__FUNCTION__, crd1->crd_alg, crd2->crd_alg, crd1->crd_flags & CRD_F_ENCRYPT); -+ err = EINVAL; -+ goto errout; -+ } -+ } -+ -+ if (enccrd) { -+ cmd->enccrd = enccrd; -+ cmd->base_masks |= HIFN_BASE_CMD_CRYPT; -+ switch (enccrd->crd_alg) { -+ case CRYPTO_ARC4: -+ cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_RC4; -+ break; -+ case CRYPTO_DES_CBC: -+ cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_DES | -+ HIFN_CRYPT_CMD_MODE_CBC | -+ HIFN_CRYPT_CMD_NEW_IV; -+ break; -+ case CRYPTO_3DES_CBC: -+ cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_3DES | -+ HIFN_CRYPT_CMD_MODE_CBC | -+ HIFN_CRYPT_CMD_NEW_IV; -+ break; -+ case CRYPTO_AES_CBC: -+ cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_AES | -+ HIFN_CRYPT_CMD_MODE_CBC | -+ HIFN_CRYPT_CMD_NEW_IV; -+ break; -+ default: -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ err = EINVAL; -+ goto errout; -+ } -+ if (enccrd->crd_alg != CRYPTO_ARC4) { -+ ivlen = ((enccrd->crd_alg == CRYPTO_AES_CBC) ? -+ HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH); -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) { -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) -+ bcopy(enccrd->crd_iv, cmd->iv, ivlen); -+ else -+ bcopy(sc->sc_sessions[session].hs_iv, -+ cmd->iv, ivlen); -+ -+ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) -+ == 0) { -+ crypto_copyback(crp->crp_flags, -+ crp->crp_buf, enccrd->crd_inject, -+ ivlen, cmd->iv); -+ } -+ } else { -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) -+ bcopy(enccrd->crd_iv, cmd->iv, ivlen); -+ else { -+ crypto_copydata(crp->crp_flags, -+ crp->crp_buf, enccrd->crd_inject, -+ ivlen, cmd->iv); -+ } -+ } -+ } -+ -+ if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) -+ cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY; -+ cmd->ck = enccrd->crd_key; -+ cmd->cklen = enccrd->crd_klen >> 3; -+ cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY; -+ -+ /* -+ * Need to specify the size for the AES key in the masks. -+ */ -+ if ((cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) == -+ HIFN_CRYPT_CMD_ALG_AES) { -+ switch (cmd->cklen) { -+ case 16: -+ cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_128; -+ break; -+ case 24: -+ cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_192; -+ break; -+ case 32: -+ cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_256; -+ break; -+ default: -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ err = EINVAL; -+ goto errout; -+ } -+ } -+ } -+ -+ if (maccrd) { -+ cmd->maccrd = maccrd; -+ cmd->base_masks |= HIFN_BASE_CMD_MAC; -+ -+ switch (maccrd->crd_alg) { -+ case CRYPTO_MD5: -+ cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | -+ HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | -+ HIFN_MAC_CMD_POS_IPSEC; -+ break; -+ case CRYPTO_MD5_HMAC: -+ cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | -+ HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | -+ HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; -+ break; -+ case CRYPTO_SHA1: -+ cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | -+ HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | -+ HIFN_MAC_CMD_POS_IPSEC; -+ break; -+ case CRYPTO_SHA1_HMAC: -+ cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | -+ HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | -+ HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; -+ break; -+ } -+ -+ if (maccrd->crd_alg == CRYPTO_SHA1_HMAC || -+ maccrd->crd_alg == CRYPTO_MD5_HMAC) { -+ cmd->mac_masks |= HIFN_MAC_CMD_NEW_KEY; -+ bcopy(maccrd->crd_key, cmd->mac, maccrd->crd_klen >> 3); -+ bzero(cmd->mac + (maccrd->crd_klen >> 3), -+ HIFN_MAC_KEY_LENGTH - (maccrd->crd_klen >> 3)); -+ } -+ } -+ -+ cmd->crp = crp; -+ cmd->session_num = session; -+ cmd->softc = sc; -+ -+ err = hifn_crypto(sc, cmd, crp, hint); -+ if (!err) { -+ return 0; -+ } else if (err == ERESTART) { -+ /* -+ * There weren't enough resources to dispatch the request -+ * to the part. Notify the caller so they'll requeue this -+ * request and resubmit it again soon. -+ */ -+#ifdef HIFN_DEBUG -+ if (hifn_debug) -+ device_printf(sc->sc_dev, "requeue request\n"); -+#endif -+ kfree(cmd); -+ sc->sc_needwakeup |= CRYPTO_SYMQ; -+ return (err); -+ } -+ -+errout: -+ if (cmd != NULL) -+ kfree(cmd); -+ if (err == EINVAL) -+ hifnstats.hst_invalid++; -+ else -+ hifnstats.hst_nomem++; -+ crp->crp_etype = err; -+ crypto_done(crp); -+ return (err); -+} -+ -+static void -+hifn_abort(struct hifn_softc *sc) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ struct hifn_command *cmd; -+ struct cryptop *crp; -+ int i, u; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ i = dma->resk; u = dma->resu; -+ while (u != 0) { -+ cmd = dma->hifn_commands[i]; -+ KASSERT(cmd != NULL, ("hifn_abort: null command slot %u", i)); -+ dma->hifn_commands[i] = NULL; -+ crp = cmd->crp; -+ -+ if ((dma->resr[i].l & htole32(HIFN_D_VALID)) == 0) { -+ /* Salvage what we can. */ -+ u_int8_t *macbuf; -+ -+ if (cmd->base_masks & HIFN_BASE_CMD_MAC) { -+ macbuf = dma->result_bufs[i]; -+ macbuf += 12; -+ } else -+ macbuf = NULL; -+ hifnstats.hst_opackets++; -+ hifn_callback(sc, cmd, macbuf); -+ } else { -+#if 0 -+ if (cmd->src_map == cmd->dst_map) { -+ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, -+ BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); -+ } else { -+ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, -+ BUS_DMASYNC_POSTWRITE); -+ bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, -+ BUS_DMASYNC_POSTREAD); -+ } -+#endif -+ -+ if (cmd->src_skb != cmd->dst_skb) { -+#ifdef NOTYET -+ m_freem(cmd->src_m); -+ crp->crp_buf = (caddr_t)cmd->dst_m; -+#else -+ device_printf(sc->sc_dev, -+ "%s,%d: CRYPTO_F_SKBUF src != dst not implemented\n", -+ __FILE__, __LINE__); -+#endif -+ } -+ -+ /* non-shared buffers cannot be restarted */ -+ if (cmd->src_map != cmd->dst_map) { -+ /* -+ * XXX should be EAGAIN, delayed until -+ * after the reset. -+ */ -+ crp->crp_etype = ENOMEM; -+ pci_unmap_buf(sc, &cmd->dst); -+ } else -+ crp->crp_etype = ENOMEM; -+ -+ pci_unmap_buf(sc, &cmd->src); -+ -+ kfree(cmd); -+ if (crp->crp_etype != EAGAIN) -+ crypto_done(crp); -+ } -+ -+ if (++i == HIFN_D_RES_RSIZE) -+ i = 0; -+ u--; -+ } -+ dma->resk = i; dma->resu = u; -+ -+ hifn_reset_board(sc, 1); -+ hifn_init_dma(sc); -+ hifn_init_pci_registers(sc); -+} -+ -+static void -+hifn_callback(struct hifn_softc *sc, struct hifn_command *cmd, u_int8_t *macbuf) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ struct cryptop *crp = cmd->crp; -+ struct cryptodesc *crd; -+ int i, u, ivlen; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+#if 0 -+ if (cmd->src_map == cmd->dst_map) { -+ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, -+ BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); -+ } else { -+ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, -+ BUS_DMASYNC_POSTWRITE); -+ bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, -+ BUS_DMASYNC_POSTREAD); -+ } -+#endif -+ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ if (cmd->src_skb != cmd->dst_skb) { -+#ifdef NOTYET -+ crp->crp_buf = (caddr_t)cmd->dst_m; -+ totlen = cmd->src_mapsize; -+ for (m = cmd->dst_m; m != NULL; m = m->m_next) { -+ if (totlen < m->m_len) { -+ m->m_len = totlen; -+ totlen = 0; -+ } else -+ totlen -= m->m_len; -+ } -+ cmd->dst_m->m_pkthdr.len = cmd->src_m->m_pkthdr.len; -+ m_freem(cmd->src_m); -+#else -+ device_printf(sc->sc_dev, -+ "%s,%d: CRYPTO_F_SKBUF src != dst not implemented\n", -+ __FILE__, __LINE__); -+#endif -+ } -+ } -+ -+ if (cmd->sloplen != 0) { -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ cmd->src_mapsize - cmd->sloplen, cmd->sloplen, -+ (caddr_t)&dma->slop[cmd->slopidx]); -+ } -+ -+ i = dma->dstk; u = dma->dstu; -+ while (u != 0) { -+ if (i == HIFN_D_DST_RSIZE) -+ i = 0; -+#if 0 -+ bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, -+ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); -+#endif -+ if (dma->dstr[i].l & htole32(HIFN_D_VALID)) { -+#if 0 -+ bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+#endif -+ break; -+ } -+ i++, u--; -+ } -+ dma->dstk = i; dma->dstu = u; -+ -+ hifnstats.hst_obytes += cmd->dst_mapsize; -+ -+ if ((cmd->base_masks & (HIFN_BASE_CMD_CRYPT | HIFN_BASE_CMD_DECODE)) == -+ HIFN_BASE_CMD_CRYPT) { -+ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { -+ if (crd->crd_alg != CRYPTO_DES_CBC && -+ crd->crd_alg != CRYPTO_3DES_CBC && -+ crd->crd_alg != CRYPTO_AES_CBC) -+ continue; -+ ivlen = ((crd->crd_alg == CRYPTO_AES_CBC) ? -+ HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH); -+ crypto_copydata(crp->crp_flags, crp->crp_buf, -+ crd->crd_skip + crd->crd_len - ivlen, ivlen, -+ cmd->softc->sc_sessions[cmd->session_num].hs_iv); -+ break; -+ } -+ } -+ -+ if (macbuf != NULL) { -+ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { -+ int len; -+ -+ if (crd->crd_alg != CRYPTO_MD5 && -+ crd->crd_alg != CRYPTO_SHA1 && -+ crd->crd_alg != CRYPTO_MD5_HMAC && -+ crd->crd_alg != CRYPTO_SHA1_HMAC) { -+ continue; -+ } -+ len = cmd->softc->sc_sessions[cmd->session_num].hs_mlen; -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, len, macbuf); -+ break; -+ } -+ } -+ -+ if (cmd->src_map != cmd->dst_map) -+ pci_unmap_buf(sc, &cmd->dst); -+ pci_unmap_buf(sc, &cmd->src); -+ kfree(cmd); -+ crypto_done(crp); -+} -+ -+/* -+ * 7811 PB3 rev/2 parts lock-up on burst writes to Group 0 -+ * and Group 1 registers; avoid conditions that could create -+ * burst writes by doing a read in between the writes. -+ * -+ * NB: The read we interpose is always to the same register; -+ * we do this because reading from an arbitrary (e.g. last) -+ * register may not always work. -+ */ -+static void -+hifn_write_reg_0(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) -+{ -+ if (sc->sc_flags & HIFN_IS_7811) { -+ if (sc->sc_bar0_lastreg == reg - 4) -+ readl(sc->sc_bar0 + HIFN_0_PUCNFG); -+ sc->sc_bar0_lastreg = reg; -+ } -+ writel(val, sc->sc_bar0 + reg); -+} -+ -+static void -+hifn_write_reg_1(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) -+{ -+ if (sc->sc_flags & HIFN_IS_7811) { -+ if (sc->sc_bar1_lastreg == reg - 4) -+ readl(sc->sc_bar1 + HIFN_1_REVID); -+ sc->sc_bar1_lastreg = reg; -+ } -+ writel(val, sc->sc_bar1 + reg); -+} -+ -+ -+static struct pci_device_id hifn_pci_tbl[] = { -+ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7951, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7955, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7956, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ { PCI_VENDOR_NETSEC, PCI_PRODUCT_NETSEC_7751, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ { PCI_VENDOR_INVERTEX, PCI_PRODUCT_INVERTEX_AEON, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7811, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ /* -+ * Other vendors share this PCI ID as well, such as -+ * http://www.powercrypt.com, and obviously they also -+ * use the same key. -+ */ -+ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7751, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ { 0, 0, 0, 0, 0, 0, } -+}; -+MODULE_DEVICE_TABLE(pci, hifn_pci_tbl); -+ -+static struct pci_driver hifn_driver = { -+ .name = "hifn", -+ .id_table = hifn_pci_tbl, -+ .probe = hifn_probe, -+ .remove = hifn_remove, -+ /* add PM stuff here one day */ -+}; -+ -+static int __init hifn_init (void) -+{ -+ struct hifn_softc *sc = NULL; -+ int rc; -+ -+ DPRINTF("%s(%p)\n", __FUNCTION__, hifn_init); -+ -+ rc = pci_register_driver(&hifn_driver); -+ pci_register_driver_compat(&hifn_driver, rc); -+ -+ return rc; -+} -+ -+static void __exit hifn_exit (void) -+{ -+ pci_unregister_driver(&hifn_driver); -+} -+ -+module_init(hifn_init); -+module_exit(hifn_exit); -+ -+MODULE_LICENSE("BSD"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("OCF driver for hifn PCI crypto devices"); -diff -Nur linux-2.6.36.orig/crypto/ocf/hifn/hifn7751reg.h linux-2.6.36/crypto/ocf/hifn/hifn7751reg.h ---- linux-2.6.36.orig/crypto/ocf/hifn/hifn7751reg.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/hifn/hifn7751reg.h 2010-11-09 20:28:04.792495416 +0100 -@@ -0,0 +1,540 @@ -+/* $FreeBSD: src/sys/dev/hifn/hifn7751reg.h,v 1.7 2007/03/21 03:42:49 sam Exp $ */ -+/* $OpenBSD: hifn7751reg.h,v 1.35 2002/04/08 17:49:42 jason Exp $ */ -+ -+/*- -+ * Invertex AEON / Hifn 7751 driver -+ * Copyright (c) 1999 Invertex Inc. All rights reserved. -+ * Copyright (c) 1999 Theo de Raadt -+ * Copyright (c) 2000-2001 Network Security Technologies, Inc. -+ * http://www.netsec.net -+ * -+ * Please send any comments, feedback, bug-fixes, or feature requests to -+ * software@invertex.com. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored in part by the Defense Advanced Research Projects -+ * Agency (DARPA) and Air Force Research Laboratory, Air Force -+ * Materiel Command, USAF, under agreement number F30602-01-2-0537. -+ * -+ */ -+#ifndef __HIFN_H__ -+#define __HIFN_H__ -+ -+/* -+ * Some PCI configuration space offset defines. The names were made -+ * identical to the names used by the Linux kernel. -+ */ -+#define HIFN_BAR0 PCIR_BAR(0) /* PUC register map */ -+#define HIFN_BAR1 PCIR_BAR(1) /* DMA register map */ -+#define HIFN_TRDY_TIMEOUT 0x40 -+#define HIFN_RETRY_TIMEOUT 0x41 -+ -+/* -+ * PCI vendor and device identifiers -+ * (the names are preserved from their OpenBSD source). -+ */ -+#define PCI_VENDOR_HIFN 0x13a3 /* Hifn */ -+#define PCI_PRODUCT_HIFN_7751 0x0005 /* 7751 */ -+#define PCI_PRODUCT_HIFN_6500 0x0006 /* 6500 */ -+#define PCI_PRODUCT_HIFN_7811 0x0007 /* 7811 */ -+#define PCI_PRODUCT_HIFN_7855 0x001f /* 7855 */ -+#define PCI_PRODUCT_HIFN_7951 0x0012 /* 7951 */ -+#define PCI_PRODUCT_HIFN_7955 0x0020 /* 7954/7955 */ -+#define PCI_PRODUCT_HIFN_7956 0x001d /* 7956 */ -+ -+#define PCI_VENDOR_INVERTEX 0x14e1 /* Invertex */ -+#define PCI_PRODUCT_INVERTEX_AEON 0x0005 /* AEON */ -+ -+#define PCI_VENDOR_NETSEC 0x1660 /* NetSec */ -+#define PCI_PRODUCT_NETSEC_7751 0x7751 /* 7751 */ -+ -+/* -+ * The values below should multiple of 4 -- and be large enough to handle -+ * any command the driver implements. -+ * -+ * MAX_COMMAND = base command + mac command + encrypt command + -+ * mac-key + rc4-key -+ * MAX_RESULT = base result + mac result + mac + encrypt result -+ * -+ * -+ */ -+#define HIFN_MAX_COMMAND (8 + 8 + 8 + 64 + 260) -+#define HIFN_MAX_RESULT (8 + 4 + 20 + 4) -+ -+/* -+ * hifn_desc_t -+ * -+ * Holds an individual descriptor for any of the rings. -+ */ -+typedef struct hifn_desc { -+ volatile u_int32_t l; /* length and status bits */ -+ volatile u_int32_t p; -+} hifn_desc_t; -+ -+/* -+ * Masks for the "length" field of struct hifn_desc. -+ */ -+#define HIFN_D_LENGTH 0x0000ffff /* length bit mask */ -+#define HIFN_D_MASKDONEIRQ 0x02000000 /* mask the done interrupt */ -+#define HIFN_D_DESTOVER 0x04000000 /* destination overflow */ -+#define HIFN_D_OVER 0x08000000 /* overflow */ -+#define HIFN_D_LAST 0x20000000 /* last descriptor in chain */ -+#define HIFN_D_JUMP 0x40000000 /* jump descriptor */ -+#define HIFN_D_VALID 0x80000000 /* valid bit */ -+ -+ -+/* -+ * Processing Unit Registers (offset from BASEREG0) -+ */ -+#define HIFN_0_PUDATA 0x00 /* Processing Unit Data */ -+#define HIFN_0_PUCTRL 0x04 /* Processing Unit Control */ -+#define HIFN_0_PUISR 0x08 /* Processing Unit Interrupt Status */ -+#define HIFN_0_PUCNFG 0x0c /* Processing Unit Configuration */ -+#define HIFN_0_PUIER 0x10 /* Processing Unit Interrupt Enable */ -+#define HIFN_0_PUSTAT 0x14 /* Processing Unit Status/Chip ID */ -+#define HIFN_0_FIFOSTAT 0x18 /* FIFO Status */ -+#define HIFN_0_FIFOCNFG 0x1c /* FIFO Configuration */ -+#define HIFN_0_PUCTRL2 0x28 /* Processing Unit Control (2nd map) */ -+#define HIFN_0_MUTE1 0x80 -+#define HIFN_0_MUTE2 0x90 -+#define HIFN_0_SPACESIZE 0x100 /* Register space size */ -+ -+/* Processing Unit Control Register (HIFN_0_PUCTRL) */ -+#define HIFN_PUCTRL_CLRSRCFIFO 0x0010 /* clear source fifo */ -+#define HIFN_PUCTRL_STOP 0x0008 /* stop pu */ -+#define HIFN_PUCTRL_LOCKRAM 0x0004 /* lock ram */ -+#define HIFN_PUCTRL_DMAENA 0x0002 /* enable dma */ -+#define HIFN_PUCTRL_RESET 0x0001 /* Reset processing unit */ -+ -+/* Processing Unit Interrupt Status Register (HIFN_0_PUISR) */ -+#define HIFN_PUISR_CMDINVAL 0x8000 /* Invalid command interrupt */ -+#define HIFN_PUISR_DATAERR 0x4000 /* Data error interrupt */ -+#define HIFN_PUISR_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ -+#define HIFN_PUISR_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ -+#define HIFN_PUISR_DSTOVER 0x0200 /* Destination overrun interrupt */ -+#define HIFN_PUISR_SRCCMD 0x0080 /* Source command interrupt */ -+#define HIFN_PUISR_SRCCTX 0x0040 /* Source context interrupt */ -+#define HIFN_PUISR_SRCDATA 0x0020 /* Source data interrupt */ -+#define HIFN_PUISR_DSTDATA 0x0010 /* Destination data interrupt */ -+#define HIFN_PUISR_DSTRESULT 0x0004 /* Destination result interrupt */ -+ -+/* Processing Unit Configuration Register (HIFN_0_PUCNFG) */ -+#define HIFN_PUCNFG_DRAMMASK 0xe000 /* DRAM size mask */ -+#define HIFN_PUCNFG_DSZ_256K 0x0000 /* 256k dram */ -+#define HIFN_PUCNFG_DSZ_512K 0x2000 /* 512k dram */ -+#define HIFN_PUCNFG_DSZ_1M 0x4000 /* 1m dram */ -+#define HIFN_PUCNFG_DSZ_2M 0x6000 /* 2m dram */ -+#define HIFN_PUCNFG_DSZ_4M 0x8000 /* 4m dram */ -+#define HIFN_PUCNFG_DSZ_8M 0xa000 /* 8m dram */ -+#define HIFN_PUNCFG_DSZ_16M 0xc000 /* 16m dram */ -+#define HIFN_PUCNFG_DSZ_32M 0xe000 /* 32m dram */ -+#define HIFN_PUCNFG_DRAMREFRESH 0x1800 /* DRAM refresh rate mask */ -+#define HIFN_PUCNFG_DRFR_512 0x0000 /* 512 divisor of ECLK */ -+#define HIFN_PUCNFG_DRFR_256 0x0800 /* 256 divisor of ECLK */ -+#define HIFN_PUCNFG_DRFR_128 0x1000 /* 128 divisor of ECLK */ -+#define HIFN_PUCNFG_TCALLPHASES 0x0200 /* your guess is as good as mine... */ -+#define HIFN_PUCNFG_TCDRVTOTEM 0x0100 /* your guess is as good as mine... */ -+#define HIFN_PUCNFG_BIGENDIAN 0x0080 /* DMA big endian mode */ -+#define HIFN_PUCNFG_BUS32 0x0040 /* Bus width 32bits */ -+#define HIFN_PUCNFG_BUS16 0x0000 /* Bus width 16 bits */ -+#define HIFN_PUCNFG_CHIPID 0x0020 /* Allow chipid from PUSTAT */ -+#define HIFN_PUCNFG_DRAM 0x0010 /* Context RAM is DRAM */ -+#define HIFN_PUCNFG_SRAM 0x0000 /* Context RAM is SRAM */ -+#define HIFN_PUCNFG_COMPSING 0x0004 /* Enable single compression context */ -+#define HIFN_PUCNFG_ENCCNFG 0x0002 /* Encryption configuration */ -+ -+/* Processing Unit Interrupt Enable Register (HIFN_0_PUIER) */ -+#define HIFN_PUIER_CMDINVAL 0x8000 /* Invalid command interrupt */ -+#define HIFN_PUIER_DATAERR 0x4000 /* Data error interrupt */ -+#define HIFN_PUIER_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ -+#define HIFN_PUIER_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ -+#define HIFN_PUIER_DSTOVER 0x0200 /* Destination overrun interrupt */ -+#define HIFN_PUIER_SRCCMD 0x0080 /* Source command interrupt */ -+#define HIFN_PUIER_SRCCTX 0x0040 /* Source context interrupt */ -+#define HIFN_PUIER_SRCDATA 0x0020 /* Source data interrupt */ -+#define HIFN_PUIER_DSTDATA 0x0010 /* Destination data interrupt */ -+#define HIFN_PUIER_DSTRESULT 0x0004 /* Destination result interrupt */ -+ -+/* Processing Unit Status Register/Chip ID (HIFN_0_PUSTAT) */ -+#define HIFN_PUSTAT_CMDINVAL 0x8000 /* Invalid command interrupt */ -+#define HIFN_PUSTAT_DATAERR 0x4000 /* Data error interrupt */ -+#define HIFN_PUSTAT_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ -+#define HIFN_PUSTAT_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ -+#define HIFN_PUSTAT_DSTOVER 0x0200 /* Destination overrun interrupt */ -+#define HIFN_PUSTAT_SRCCMD 0x0080 /* Source command interrupt */ -+#define HIFN_PUSTAT_SRCCTX 0x0040 /* Source context interrupt */ -+#define HIFN_PUSTAT_SRCDATA 0x0020 /* Source data interrupt */ -+#define HIFN_PUSTAT_DSTDATA 0x0010 /* Destination data interrupt */ -+#define HIFN_PUSTAT_DSTRESULT 0x0004 /* Destination result interrupt */ -+#define HIFN_PUSTAT_CHIPREV 0x00ff /* Chip revision mask */ -+#define HIFN_PUSTAT_CHIPENA 0xff00 /* Chip enabled mask */ -+#define HIFN_PUSTAT_ENA_2 0x1100 /* Level 2 enabled */ -+#define HIFN_PUSTAT_ENA_1 0x1000 /* Level 1 enabled */ -+#define HIFN_PUSTAT_ENA_0 0x3000 /* Level 0 enabled */ -+#define HIFN_PUSTAT_REV_2 0x0020 /* 7751 PT6/2 */ -+#define HIFN_PUSTAT_REV_3 0x0030 /* 7751 PT6/3 */ -+ -+/* FIFO Status Register (HIFN_0_FIFOSTAT) */ -+#define HIFN_FIFOSTAT_SRC 0x7f00 /* Source FIFO available */ -+#define HIFN_FIFOSTAT_DST 0x007f /* Destination FIFO available */ -+ -+/* FIFO Configuration Register (HIFN_0_FIFOCNFG) */ -+#define HIFN_FIFOCNFG_THRESHOLD 0x0400 /* must be written as this value */ -+ -+/* -+ * DMA Interface Registers (offset from BASEREG1) -+ */ -+#define HIFN_1_DMA_CRAR 0x0c /* DMA Command Ring Address */ -+#define HIFN_1_DMA_SRAR 0x1c /* DMA Source Ring Address */ -+#define HIFN_1_DMA_RRAR 0x2c /* DMA Result Ring Address */ -+#define HIFN_1_DMA_DRAR 0x3c /* DMA Destination Ring Address */ -+#define HIFN_1_DMA_CSR 0x40 /* DMA Status and Control */ -+#define HIFN_1_DMA_IER 0x44 /* DMA Interrupt Enable */ -+#define HIFN_1_DMA_CNFG 0x48 /* DMA Configuration */ -+#define HIFN_1_PLL 0x4c /* 7955/7956: PLL config */ -+#define HIFN_1_7811_RNGENA 0x60 /* 7811: rng enable */ -+#define HIFN_1_7811_RNGCFG 0x64 /* 7811: rng config */ -+#define HIFN_1_7811_RNGDAT 0x68 /* 7811: rng data */ -+#define HIFN_1_7811_RNGSTS 0x6c /* 7811: rng status */ -+#define HIFN_1_DMA_CNFG2 0x6c /* 7955/7956: dma config #2 */ -+#define HIFN_1_7811_MIPSRST 0x94 /* 7811: MIPS reset */ -+#define HIFN_1_REVID 0x98 /* Revision ID */ -+ -+#define HIFN_1_PUB_RESET 0x204 /* Public/RNG Reset */ -+#define HIFN_1_PUB_BASE 0x300 /* Public Base Address */ -+#define HIFN_1_PUB_OPLEN 0x304 /* 7951-compat Public Operand Length */ -+#define HIFN_1_PUB_OP 0x308 /* 7951-compat Public Operand */ -+#define HIFN_1_PUB_STATUS 0x30c /* 7951-compat Public Status */ -+#define HIFN_1_PUB_IEN 0x310 /* Public Interrupt enable */ -+#define HIFN_1_RNG_CONFIG 0x314 /* RNG config */ -+#define HIFN_1_RNG_DATA 0x318 /* RNG data */ -+#define HIFN_1_PUB_MODE 0x320 /* PK mode */ -+#define HIFN_1_PUB_FIFO_OPLEN 0x380 /* first element of oplen fifo */ -+#define HIFN_1_PUB_FIFO_OP 0x384 /* first element of op fifo */ -+#define HIFN_1_PUB_MEM 0x400 /* start of Public key memory */ -+#define HIFN_1_PUB_MEMEND 0xbff /* end of Public key memory */ -+ -+/* DMA Status and Control Register (HIFN_1_DMA_CSR) */ -+#define HIFN_DMACSR_D_CTRLMASK 0xc0000000 /* Destinition Ring Control */ -+#define HIFN_DMACSR_D_CTRL_NOP 0x00000000 /* Dest. Control: no-op */ -+#define HIFN_DMACSR_D_CTRL_DIS 0x40000000 /* Dest. Control: disable */ -+#define HIFN_DMACSR_D_CTRL_ENA 0x80000000 /* Dest. Control: enable */ -+#define HIFN_DMACSR_D_ABORT 0x20000000 /* Destinition Ring PCIAbort */ -+#define HIFN_DMACSR_D_DONE 0x10000000 /* Destinition Ring Done */ -+#define HIFN_DMACSR_D_LAST 0x08000000 /* Destinition Ring Last */ -+#define HIFN_DMACSR_D_WAIT 0x04000000 /* Destinition Ring Waiting */ -+#define HIFN_DMACSR_D_OVER 0x02000000 /* Destinition Ring Overflow */ -+#define HIFN_DMACSR_R_CTRL 0x00c00000 /* Result Ring Control */ -+#define HIFN_DMACSR_R_CTRL_NOP 0x00000000 /* Result Control: no-op */ -+#define HIFN_DMACSR_R_CTRL_DIS 0x00400000 /* Result Control: disable */ -+#define HIFN_DMACSR_R_CTRL_ENA 0x00800000 /* Result Control: enable */ -+#define HIFN_DMACSR_R_ABORT 0x00200000 /* Result Ring PCI Abort */ -+#define HIFN_DMACSR_R_DONE 0x00100000 /* Result Ring Done */ -+#define HIFN_DMACSR_R_LAST 0x00080000 /* Result Ring Last */ -+#define HIFN_DMACSR_R_WAIT 0x00040000 /* Result Ring Waiting */ -+#define HIFN_DMACSR_R_OVER 0x00020000 /* Result Ring Overflow */ -+#define HIFN_DMACSR_S_CTRL 0x0000c000 /* Source Ring Control */ -+#define HIFN_DMACSR_S_CTRL_NOP 0x00000000 /* Source Control: no-op */ -+#define HIFN_DMACSR_S_CTRL_DIS 0x00004000 /* Source Control: disable */ -+#define HIFN_DMACSR_S_CTRL_ENA 0x00008000 /* Source Control: enable */ -+#define HIFN_DMACSR_S_ABORT 0x00002000 /* Source Ring PCI Abort */ -+#define HIFN_DMACSR_S_DONE 0x00001000 /* Source Ring Done */ -+#define HIFN_DMACSR_S_LAST 0x00000800 /* Source Ring Last */ -+#define HIFN_DMACSR_S_WAIT 0x00000400 /* Source Ring Waiting */ -+#define HIFN_DMACSR_ILLW 0x00000200 /* Illegal write (7811 only) */ -+#define HIFN_DMACSR_ILLR 0x00000100 /* Illegal read (7811 only) */ -+#define HIFN_DMACSR_C_CTRL 0x000000c0 /* Command Ring Control */ -+#define HIFN_DMACSR_C_CTRL_NOP 0x00000000 /* Command Control: no-op */ -+#define HIFN_DMACSR_C_CTRL_DIS 0x00000040 /* Command Control: disable */ -+#define HIFN_DMACSR_C_CTRL_ENA 0x00000080 /* Command Control: enable */ -+#define HIFN_DMACSR_C_ABORT 0x00000020 /* Command Ring PCI Abort */ -+#define HIFN_DMACSR_C_DONE 0x00000010 /* Command Ring Done */ -+#define HIFN_DMACSR_C_LAST 0x00000008 /* Command Ring Last */ -+#define HIFN_DMACSR_C_WAIT 0x00000004 /* Command Ring Waiting */ -+#define HIFN_DMACSR_PUBDONE 0x00000002 /* Public op done (7951 only) */ -+#define HIFN_DMACSR_ENGINE 0x00000001 /* Command Ring Engine IRQ */ -+ -+/* DMA Interrupt Enable Register (HIFN_1_DMA_IER) */ -+#define HIFN_DMAIER_D_ABORT 0x20000000 /* Destination Ring PCIAbort */ -+#define HIFN_DMAIER_D_DONE 0x10000000 /* Destination Ring Done */ -+#define HIFN_DMAIER_D_LAST 0x08000000 /* Destination Ring Last */ -+#define HIFN_DMAIER_D_WAIT 0x04000000 /* Destination Ring Waiting */ -+#define HIFN_DMAIER_D_OVER 0x02000000 /* Destination Ring Overflow */ -+#define HIFN_DMAIER_R_ABORT 0x00200000 /* Result Ring PCI Abort */ -+#define HIFN_DMAIER_R_DONE 0x00100000 /* Result Ring Done */ -+#define HIFN_DMAIER_R_LAST 0x00080000 /* Result Ring Last */ -+#define HIFN_DMAIER_R_WAIT 0x00040000 /* Result Ring Waiting */ -+#define HIFN_DMAIER_R_OVER 0x00020000 /* Result Ring Overflow */ -+#define HIFN_DMAIER_S_ABORT 0x00002000 /* Source Ring PCI Abort */ -+#define HIFN_DMAIER_S_DONE 0x00001000 /* Source Ring Done */ -+#define HIFN_DMAIER_S_LAST 0x00000800 /* Source Ring Last */ -+#define HIFN_DMAIER_S_WAIT 0x00000400 /* Source Ring Waiting */ -+#define HIFN_DMAIER_ILLW 0x00000200 /* Illegal write (7811 only) */ -+#define HIFN_DMAIER_ILLR 0x00000100 /* Illegal read (7811 only) */ -+#define HIFN_DMAIER_C_ABORT 0x00000020 /* Command Ring PCI Abort */ -+#define HIFN_DMAIER_C_DONE 0x00000010 /* Command Ring Done */ -+#define HIFN_DMAIER_C_LAST 0x00000008 /* Command Ring Last */ -+#define HIFN_DMAIER_C_WAIT 0x00000004 /* Command Ring Waiting */ -+#define HIFN_DMAIER_PUBDONE 0x00000002 /* public op done (7951 only) */ -+#define HIFN_DMAIER_ENGINE 0x00000001 /* Engine IRQ */ -+ -+/* DMA Configuration Register (HIFN_1_DMA_CNFG) */ -+#define HIFN_DMACNFG_BIGENDIAN 0x10000000 /* big endian mode */ -+#define HIFN_DMACNFG_POLLFREQ 0x00ff0000 /* Poll frequency mask */ -+#define HIFN_DMACNFG_UNLOCK 0x00000800 -+#define HIFN_DMACNFG_POLLINVAL 0x00000700 /* Invalid Poll Scalar */ -+#define HIFN_DMACNFG_LAST 0x00000010 /* Host control LAST bit */ -+#define HIFN_DMACNFG_MODE 0x00000004 /* DMA mode */ -+#define HIFN_DMACNFG_DMARESET 0x00000002 /* DMA Reset # */ -+#define HIFN_DMACNFG_MSTRESET 0x00000001 /* Master Reset # */ -+ -+/* DMA Configuration Register (HIFN_1_DMA_CNFG2) */ -+#define HIFN_DMACNFG2_PKSWAP32 (1 << 19) /* swap the OPLEN/OP reg */ -+#define HIFN_DMACNFG2_PKSWAP8 (1 << 18) /* swap the bits of OPLEN/OP */ -+#define HIFN_DMACNFG2_BAR0_SWAP32 (1<<17) /* swap the bytes of BAR0 */ -+#define HIFN_DMACNFG2_BAR1_SWAP8 (1<<16) /* swap the bits of BAR0 */ -+#define HIFN_DMACNFG2_INIT_WRITE_BURST_SHIFT 12 -+#define HIFN_DMACNFG2_INIT_READ_BURST_SHIFT 8 -+#define HIFN_DMACNFG2_TGT_WRITE_BURST_SHIFT 4 -+#define HIFN_DMACNFG2_TGT_READ_BURST_SHIFT 0 -+ -+/* 7811 RNG Enable Register (HIFN_1_7811_RNGENA) */ -+#define HIFN_7811_RNGENA_ENA 0x00000001 /* enable RNG */ -+ -+/* 7811 RNG Config Register (HIFN_1_7811_RNGCFG) */ -+#define HIFN_7811_RNGCFG_PRE1 0x00000f00 /* first prescalar */ -+#define HIFN_7811_RNGCFG_OPRE 0x00000080 /* output prescalar */ -+#define HIFN_7811_RNGCFG_DEFL 0x00000f80 /* 2 words/ 1/100 sec */ -+ -+/* 7811 RNG Status Register (HIFN_1_7811_RNGSTS) */ -+#define HIFN_7811_RNGSTS_RDY 0x00004000 /* two numbers in FIFO */ -+#define HIFN_7811_RNGSTS_UFL 0x00001000 /* rng underflow */ -+ -+/* 7811 MIPS Reset Register (HIFN_1_7811_MIPSRST) */ -+#define HIFN_MIPSRST_BAR2SIZE 0xffff0000 /* sdram size */ -+#define HIFN_MIPSRST_GPRAMINIT 0x00008000 /* gpram can be accessed */ -+#define HIFN_MIPSRST_CRAMINIT 0x00004000 /* ctxram can be accessed */ -+#define HIFN_MIPSRST_LED2 0x00000400 /* external LED2 */ -+#define HIFN_MIPSRST_LED1 0x00000200 /* external LED1 */ -+#define HIFN_MIPSRST_LED0 0x00000100 /* external LED0 */ -+#define HIFN_MIPSRST_MIPSDIS 0x00000004 /* disable MIPS */ -+#define HIFN_MIPSRST_MIPSRST 0x00000002 /* warm reset MIPS */ -+#define HIFN_MIPSRST_MIPSCOLD 0x00000001 /* cold reset MIPS */ -+ -+/* Public key reset register (HIFN_1_PUB_RESET) */ -+#define HIFN_PUBRST_RESET 0x00000001 /* reset public/rng unit */ -+ -+/* Public operation register (HIFN_1_PUB_OP) */ -+#define HIFN_PUBOP_AOFFSET 0x0000003e /* A offset */ -+#define HIFN_PUBOP_BOFFSET 0x00000fc0 /* B offset */ -+#define HIFN_PUBOP_MOFFSET 0x0003f000 /* M offset */ -+#define HIFN_PUBOP_OP_MASK 0x003c0000 /* Opcode: */ -+#define HIFN_PUBOP_OP_NOP 0x00000000 /* NOP */ -+#define HIFN_PUBOP_OP_ADD 0x00040000 /* ADD */ -+#define HIFN_PUBOP_OP_ADDC 0x00080000 /* ADD w/carry */ -+#define HIFN_PUBOP_OP_SUB 0x000c0000 /* SUB */ -+#define HIFN_PUBOP_OP_SUBC 0x00100000 /* SUB w/carry */ -+#define HIFN_PUBOP_OP_MODADD 0x00140000 /* Modular ADD */ -+#define HIFN_PUBOP_OP_MODSUB 0x00180000 /* Modular SUB */ -+#define HIFN_PUBOP_OP_INCA 0x001c0000 /* INC A */ -+#define HIFN_PUBOP_OP_DECA 0x00200000 /* DEC A */ -+#define HIFN_PUBOP_OP_MULT 0x00240000 /* MULT */ -+#define HIFN_PUBOP_OP_MODMULT 0x00280000 /* Modular MULT */ -+#define HIFN_PUBOP_OP_MODRED 0x002c0000 /* Modular Red */ -+#define HIFN_PUBOP_OP_MODEXP 0x00300000 /* Modular Exp */ -+ -+/* Public operand length register (HIFN_1_PUB_OPLEN) */ -+#define HIFN_PUBOPLEN_MODLEN 0x0000007f -+#define HIFN_PUBOPLEN_EXPLEN 0x0003ff80 -+#define HIFN_PUBOPLEN_REDLEN 0x003c0000 -+ -+/* Public status register (HIFN_1_PUB_STATUS) */ -+#define HIFN_PUBSTS_DONE 0x00000001 /* operation done */ -+#define HIFN_PUBSTS_CARRY 0x00000002 /* carry */ -+#define HIFN_PUBSTS_FIFO_EMPTY 0x00000100 /* fifo empty */ -+#define HIFN_PUBSTS_FIFO_FULL 0x00000200 /* fifo full */ -+#define HIFN_PUBSTS_FIFO_OVFL 0x00000400 /* fifo overflow */ -+#define HIFN_PUBSTS_FIFO_WRITE 0x000f0000 /* fifo write */ -+#define HIFN_PUBSTS_FIFO_READ 0x0f000000 /* fifo read */ -+ -+/* Public interrupt enable register (HIFN_1_PUB_IEN) */ -+#define HIFN_PUBIEN_DONE 0x00000001 /* operation done interrupt */ -+ -+/* Random number generator config register (HIFN_1_RNG_CONFIG) */ -+#define HIFN_RNGCFG_ENA 0x00000001 /* enable rng */ -+ -+/* -+ * Register offsets in register set 1 -+ */ -+ -+#define HIFN_UNLOCK_SECRET1 0xf4 -+#define HIFN_UNLOCK_SECRET2 0xfc -+ -+/* -+ * PLL config register -+ * -+ * This register is present only on 7954/7955/7956 parts. It must be -+ * programmed according to the bus interface method used by the h/w. -+ * Note that the parts require a stable clock. Since the PCI clock -+ * may vary the reference clock must usually be used. To avoid -+ * overclocking the core logic, setup must be done carefully, refer -+ * to the driver for details. The exact multiplier required varies -+ * by part and system configuration; refer to the Hifn documentation. -+ */ -+#define HIFN_PLL_REF_SEL 0x00000001 /* REF/HBI clk selection */ -+#define HIFN_PLL_BP 0x00000002 /* bypass (used during setup) */ -+/* bit 2 reserved */ -+#define HIFN_PLL_PK_CLK_SEL 0x00000008 /* public key clk select */ -+#define HIFN_PLL_PE_CLK_SEL 0x00000010 /* packet engine clk select */ -+/* bits 5-9 reserved */ -+#define HIFN_PLL_MBSET 0x00000400 /* must be set to 1 */ -+#define HIFN_PLL_ND 0x00003800 /* Fpll_ref multiplier select */ -+#define HIFN_PLL_ND_SHIFT 11 -+#define HIFN_PLL_ND_2 0x00000000 /* 2x */ -+#define HIFN_PLL_ND_4 0x00000800 /* 4x */ -+#define HIFN_PLL_ND_6 0x00001000 /* 6x */ -+#define HIFN_PLL_ND_8 0x00001800 /* 8x */ -+#define HIFN_PLL_ND_10 0x00002000 /* 10x */ -+#define HIFN_PLL_ND_12 0x00002800 /* 12x */ -+/* bits 14-15 reserved */ -+#define HIFN_PLL_IS 0x00010000 /* charge pump current select */ -+/* bits 17-31 reserved */ -+ -+/* -+ * Board configuration specifies only these bits. -+ */ -+#define HIFN_PLL_CONFIG (HIFN_PLL_IS|HIFN_PLL_ND|HIFN_PLL_REF_SEL) -+ -+/* -+ * Public Key Engine Mode Register -+ */ -+#define HIFN_PKMODE_HOSTINVERT (1 << 0) /* HOST INVERT */ -+#define HIFN_PKMODE_ENHANCED (1 << 1) /* Enable enhanced mode */ -+ -+ -+/********************************************************************* -+ * Structs for board commands -+ * -+ *********************************************************************/ -+ -+/* -+ * Structure to help build up the command data structure. -+ */ -+typedef struct hifn_base_command { -+ volatile u_int16_t masks; -+ volatile u_int16_t session_num; -+ volatile u_int16_t total_source_count; -+ volatile u_int16_t total_dest_count; -+} hifn_base_command_t; -+ -+#define HIFN_BASE_CMD_MAC 0x0400 -+#define HIFN_BASE_CMD_CRYPT 0x0800 -+#define HIFN_BASE_CMD_DECODE 0x2000 -+#define HIFN_BASE_CMD_SRCLEN_M 0xc000 -+#define HIFN_BASE_CMD_SRCLEN_S 14 -+#define HIFN_BASE_CMD_DSTLEN_M 0x3000 -+#define HIFN_BASE_CMD_DSTLEN_S 12 -+#define HIFN_BASE_CMD_LENMASK_HI 0x30000 -+#define HIFN_BASE_CMD_LENMASK_LO 0x0ffff -+ -+/* -+ * Structure to help build up the command data structure. -+ */ -+typedef struct hifn_crypt_command { -+ volatile u_int16_t masks; -+ volatile u_int16_t header_skip; -+ volatile u_int16_t source_count; -+ volatile u_int16_t reserved; -+} hifn_crypt_command_t; -+ -+#define HIFN_CRYPT_CMD_ALG_MASK 0x0003 /* algorithm: */ -+#define HIFN_CRYPT_CMD_ALG_DES 0x0000 /* DES */ -+#define HIFN_CRYPT_CMD_ALG_3DES 0x0001 /* 3DES */ -+#define HIFN_CRYPT_CMD_ALG_RC4 0x0002 /* RC4 */ -+#define HIFN_CRYPT_CMD_ALG_AES 0x0003 /* AES */ -+#define HIFN_CRYPT_CMD_MODE_MASK 0x0018 /* Encrypt mode: */ -+#define HIFN_CRYPT_CMD_MODE_ECB 0x0000 /* ECB */ -+#define HIFN_CRYPT_CMD_MODE_CBC 0x0008 /* CBC */ -+#define HIFN_CRYPT_CMD_MODE_CFB 0x0010 /* CFB */ -+#define HIFN_CRYPT_CMD_MODE_OFB 0x0018 /* OFB */ -+#define HIFN_CRYPT_CMD_CLR_CTX 0x0040 /* clear context */ -+#define HIFN_CRYPT_CMD_NEW_KEY 0x0800 /* expect new key */ -+#define HIFN_CRYPT_CMD_NEW_IV 0x1000 /* expect new iv */ -+ -+#define HIFN_CRYPT_CMD_SRCLEN_M 0xc000 -+#define HIFN_CRYPT_CMD_SRCLEN_S 14 -+ -+#define HIFN_CRYPT_CMD_KSZ_MASK 0x0600 /* AES key size: */ -+#define HIFN_CRYPT_CMD_KSZ_128 0x0000 /* 128 bit */ -+#define HIFN_CRYPT_CMD_KSZ_192 0x0200 /* 192 bit */ -+#define HIFN_CRYPT_CMD_KSZ_256 0x0400 /* 256 bit */ -+ -+/* -+ * Structure to help build up the command data structure. -+ */ -+typedef struct hifn_mac_command { -+ volatile u_int16_t masks; -+ volatile u_int16_t header_skip; -+ volatile u_int16_t source_count; -+ volatile u_int16_t reserved; -+} hifn_mac_command_t; -+ -+#define HIFN_MAC_CMD_ALG_MASK 0x0001 -+#define HIFN_MAC_CMD_ALG_SHA1 0x0000 -+#define HIFN_MAC_CMD_ALG_MD5 0x0001 -+#define HIFN_MAC_CMD_MODE_MASK 0x000c -+#define HIFN_MAC_CMD_MODE_HMAC 0x0000 -+#define HIFN_MAC_CMD_MODE_SSL_MAC 0x0004 -+#define HIFN_MAC_CMD_MODE_HASH 0x0008 -+#define HIFN_MAC_CMD_MODE_FULL 0x0004 -+#define HIFN_MAC_CMD_TRUNC 0x0010 -+#define HIFN_MAC_CMD_RESULT 0x0020 -+#define HIFN_MAC_CMD_APPEND 0x0040 -+#define HIFN_MAC_CMD_SRCLEN_M 0xc000 -+#define HIFN_MAC_CMD_SRCLEN_S 14 -+ -+/* -+ * MAC POS IPsec initiates authentication after encryption on encodes -+ * and before decryption on decodes. -+ */ -+#define HIFN_MAC_CMD_POS_IPSEC 0x0200 -+#define HIFN_MAC_CMD_NEW_KEY 0x0800 -+ -+/* -+ * The poll frequency and poll scalar defines are unshifted values used -+ * to set fields in the DMA Configuration Register. -+ */ -+#ifndef HIFN_POLL_FREQUENCY -+#define HIFN_POLL_FREQUENCY 0x1 -+#endif -+ -+#ifndef HIFN_POLL_SCALAR -+#define HIFN_POLL_SCALAR 0x0 -+#endif -+ -+#define HIFN_MAX_SEGLEN 0xffff /* maximum dma segment len */ -+#define HIFN_MAX_DMALEN 0x3ffff /* maximum dma length */ -+#endif /* __HIFN_H__ */ -diff -Nur linux-2.6.36.orig/crypto/ocf/hifn/hifn7751var.h linux-2.6.36/crypto/ocf/hifn/hifn7751var.h ---- linux-2.6.36.orig/crypto/ocf/hifn/hifn7751var.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/hifn/hifn7751var.h 2010-11-09 20:28:04.832495385 +0100 -@@ -0,0 +1,369 @@ -+/* $FreeBSD: src/sys/dev/hifn/hifn7751var.h,v 1.9 2007/03/21 03:42:49 sam Exp $ */ -+/* $OpenBSD: hifn7751var.h,v 1.42 2002/04/08 17:49:42 jason Exp $ */ -+ -+/*- -+ * Invertex AEON / Hifn 7751 driver -+ * Copyright (c) 1999 Invertex Inc. All rights reserved. -+ * Copyright (c) 1999 Theo de Raadt -+ * Copyright (c) 2000-2001 Network Security Technologies, Inc. -+ * http://www.netsec.net -+ * -+ * Please send any comments, feedback, bug-fixes, or feature requests to -+ * software@invertex.com. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored in part by the Defense Advanced Research Projects -+ * Agency (DARPA) and Air Force Research Laboratory, Air Force -+ * Materiel Command, USAF, under agreement number F30602-01-2-0537. -+ * -+ */ -+ -+#ifndef __HIFN7751VAR_H__ -+#define __HIFN7751VAR_H__ -+ -+#ifdef __KERNEL__ -+ -+/* -+ * Some configurable values for the driver. By default command+result -+ * descriptor rings are the same size. The src+dst descriptor rings -+ * are sized at 3.5x the number of potential commands. Slower parts -+ * (e.g. 7951) tend to run out of src descriptors; faster parts (7811) -+ * src+cmd/result descriptors. It's not clear that increasing the size -+ * of the descriptor rings helps performance significantly as other -+ * factors tend to come into play (e.g. copying misaligned packets). -+ */ -+#define HIFN_D_CMD_RSIZE 24 /* command descriptors */ -+#define HIFN_D_SRC_RSIZE ((HIFN_D_CMD_RSIZE * 7) / 2) /* source descriptors */ -+#define HIFN_D_RES_RSIZE HIFN_D_CMD_RSIZE /* result descriptors */ -+#define HIFN_D_DST_RSIZE HIFN_D_SRC_RSIZE /* destination descriptors */ -+ -+/* -+ * Length values for cryptography -+ */ -+#define HIFN_DES_KEY_LENGTH 8 -+#define HIFN_3DES_KEY_LENGTH 24 -+#define HIFN_MAX_CRYPT_KEY_LENGTH HIFN_3DES_KEY_LENGTH -+#define HIFN_IV_LENGTH 8 -+#define HIFN_AES_IV_LENGTH 16 -+#define HIFN_MAX_IV_LENGTH HIFN_AES_IV_LENGTH -+ -+/* -+ * Length values for authentication -+ */ -+#define HIFN_MAC_KEY_LENGTH 64 -+#define HIFN_MD5_LENGTH 16 -+#define HIFN_SHA1_LENGTH 20 -+#define HIFN_MAC_TRUNC_LENGTH 12 -+ -+#define MAX_SCATTER 64 -+ -+/* -+ * Data structure to hold all 4 rings and any other ring related data. -+ */ -+struct hifn_dma { -+ /* -+ * Descriptor rings. We add +1 to the size to accomidate the -+ * jump descriptor. -+ */ -+ struct hifn_desc cmdr[HIFN_D_CMD_RSIZE+1]; -+ struct hifn_desc srcr[HIFN_D_SRC_RSIZE+1]; -+ struct hifn_desc dstr[HIFN_D_DST_RSIZE+1]; -+ struct hifn_desc resr[HIFN_D_RES_RSIZE+1]; -+ -+ struct hifn_command *hifn_commands[HIFN_D_RES_RSIZE]; -+ -+ u_char command_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_COMMAND]; -+ u_char result_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_RESULT]; -+ u_int32_t slop[HIFN_D_CMD_RSIZE]; -+ -+ u_int64_t test_src, test_dst; -+ -+ /* -+ * Our current positions for insertion and removal from the desriptor -+ * rings. -+ */ -+ int cmdi, srci, dsti, resi; -+ volatile int cmdu, srcu, dstu, resu; -+ int cmdk, srck, dstk, resk; -+}; -+ -+struct hifn_session { -+ int hs_used; -+ int hs_mlen; -+ u_int8_t hs_iv[HIFN_MAX_IV_LENGTH]; -+}; -+ -+#define HIFN_RING_SYNC(sc, r, i, f) \ -+ /* DAVIDM bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, (f)) */ -+ -+#define HIFN_CMDR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), cmdr, (i), (f)) -+#define HIFN_RESR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), resr, (i), (f)) -+#define HIFN_SRCR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), srcr, (i), (f)) -+#define HIFN_DSTR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), dstr, (i), (f)) -+ -+#define HIFN_CMD_SYNC(sc, i, f) \ -+ /* DAVIDM bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, (f)) */ -+ -+#define HIFN_RES_SYNC(sc, i, f) \ -+ /* DAVIDM bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, (f)) */ -+ -+typedef int bus_size_t; -+ -+/* -+ * Holds data specific to a single HIFN board. -+ */ -+struct hifn_softc { -+ softc_device_decl sc_dev; -+ -+ struct pci_dev *sc_pcidev; /* PCI device pointer */ -+ spinlock_t sc_mtx; /* per-instance lock */ -+ -+ int sc_num; /* for multiple devs */ -+ -+ ocf_iomem_t sc_bar0; -+ bus_size_t sc_bar0_lastreg;/* bar0 last reg written */ -+ ocf_iomem_t sc_bar1; -+ bus_size_t sc_bar1_lastreg;/* bar1 last reg written */ -+ -+ int sc_irq; -+ -+ u_int32_t sc_dmaier; -+ u_int32_t sc_drammodel; /* 1=dram, 0=sram */ -+ u_int32_t sc_pllconfig; /* 7954/7955/7956 PLL config */ -+ -+ struct hifn_dma *sc_dma; -+ dma_addr_t sc_dma_physaddr;/* physical address of sc_dma */ -+ -+ int sc_dmansegs; -+ int32_t sc_cid; -+ int sc_maxses; -+ int sc_nsessions; -+ struct hifn_session *sc_sessions; -+ int sc_ramsize; -+ int sc_flags; -+#define HIFN_HAS_RNG 0x1 /* includes random number generator */ -+#define HIFN_HAS_PUBLIC 0x2 /* includes public key support */ -+#define HIFN_HAS_AES 0x4 /* includes AES support */ -+#define HIFN_IS_7811 0x8 /* Hifn 7811 part */ -+#define HIFN_IS_7956 0x10 /* Hifn 7956/7955 don't have SDRAM */ -+ -+ struct timer_list sc_tickto; /* for managing DMA */ -+ -+ int sc_rngfirst; -+ int sc_rnghz; /* RNG polling frequency */ -+ -+ int sc_c_busy; /* command ring busy */ -+ int sc_s_busy; /* source data ring busy */ -+ int sc_d_busy; /* destination data ring busy */ -+ int sc_r_busy; /* result ring busy */ -+ int sc_active; /* for initial countdown */ -+ int sc_needwakeup; /* ops q'd wating on resources */ -+ int sc_curbatch; /* # ops submitted w/o int */ -+ int sc_suspended; -+#ifdef HIFN_VULCANDEV -+ struct cdev *sc_pkdev; -+#endif -+}; -+ -+#define HIFN_LOCK(_sc) spin_lock_irqsave(&(_sc)->sc_mtx, l_flags) -+#define HIFN_UNLOCK(_sc) spin_unlock_irqrestore(&(_sc)->sc_mtx, l_flags) -+ -+/* -+ * hifn_command_t -+ * -+ * This is the control structure used to pass commands to hifn_encrypt(). -+ * -+ * flags -+ * ----- -+ * Flags is the bitwise "or" values for command configuration. A single -+ * encrypt direction needs to be set: -+ * -+ * HIFN_ENCODE or HIFN_DECODE -+ * -+ * To use cryptography, a single crypto algorithm must be included: -+ * -+ * HIFN_CRYPT_3DES or HIFN_CRYPT_DES -+ * -+ * To use authentication is used, a single MAC algorithm must be included: -+ * -+ * HIFN_MAC_MD5 or HIFN_MAC_SHA1 -+ * -+ * By default MD5 uses a 16 byte hash and SHA-1 uses a 20 byte hash. -+ * If the value below is set, hash values are truncated or assumed -+ * truncated to 12 bytes: -+ * -+ * HIFN_MAC_TRUNC -+ * -+ * Keys for encryption and authentication can be sent as part of a command, -+ * or the last key value used with a particular session can be retrieved -+ * and used again if either of these flags are not specified. -+ * -+ * HIFN_CRYPT_NEW_KEY, HIFN_MAC_NEW_KEY -+ * -+ * session_num -+ * ----------- -+ * A number between 0 and 2048 (for DRAM models) or a number between -+ * 0 and 768 (for SRAM models). Those who don't want to use session -+ * numbers should leave value at zero and send a new crypt key and/or -+ * new MAC key on every command. If you use session numbers and -+ * don't send a key with a command, the last key sent for that same -+ * session number will be used. -+ * -+ * Warning: Using session numbers and multiboard at the same time -+ * is currently broken. -+ * -+ * mbuf -+ * ---- -+ * Either fill in the mbuf pointer and npa=0 or -+ * fill packp[] and packl[] and set npa to > 0 -+ * -+ * mac_header_skip -+ * --------------- -+ * The number of bytes of the source_buf that are skipped over before -+ * authentication begins. This must be a number between 0 and 2^16-1 -+ * and can be used by IPsec implementers to skip over IP headers. -+ * *** Value ignored if authentication not used *** -+ * -+ * crypt_header_skip -+ * ----------------- -+ * The number of bytes of the source_buf that are skipped over before -+ * the cryptographic operation begins. This must be a number between 0 -+ * and 2^16-1. For IPsec, this number will always be 8 bytes larger -+ * than the auth_header_skip (to skip over the ESP header). -+ * *** Value ignored if cryptography not used *** -+ * -+ */ -+struct hifn_operand { -+ union { -+ struct sk_buff *skb; -+ struct uio *io; -+ unsigned char *buf; -+ } u; -+ void *map; -+ bus_size_t mapsize; -+ int nsegs; -+ struct { -+ dma_addr_t ds_addr; -+ int ds_len; -+ } segs[MAX_SCATTER]; -+}; -+ -+struct hifn_command { -+ u_int16_t session_num; -+ u_int16_t base_masks, cry_masks, mac_masks; -+ u_int8_t iv[HIFN_MAX_IV_LENGTH], *ck, mac[HIFN_MAC_KEY_LENGTH]; -+ int cklen; -+ int sloplen, slopidx; -+ -+ struct hifn_operand src; -+ struct hifn_operand dst; -+ -+ struct hifn_softc *softc; -+ struct cryptop *crp; -+ struct cryptodesc *enccrd, *maccrd; -+}; -+ -+#define src_skb src.u.skb -+#define src_io src.u.io -+#define src_map src.map -+#define src_mapsize src.mapsize -+#define src_segs src.segs -+#define src_nsegs src.nsegs -+#define src_buf src.u.buf -+ -+#define dst_skb dst.u.skb -+#define dst_io dst.u.io -+#define dst_map dst.map -+#define dst_mapsize dst.mapsize -+#define dst_segs dst.segs -+#define dst_nsegs dst.nsegs -+#define dst_buf dst.u.buf -+ -+/* -+ * Return values for hifn_crypto() -+ */ -+#define HIFN_CRYPTO_SUCCESS 0 -+#define HIFN_CRYPTO_BAD_INPUT (-1) -+#define HIFN_CRYPTO_RINGS_FULL (-2) -+ -+/************************************************************************** -+ * -+ * Function: hifn_crypto -+ * -+ * Purpose: Called by external drivers to begin an encryption on the -+ * HIFN board. -+ * -+ * Blocking/Non-blocking Issues -+ * ============================ -+ * The driver cannot block in hifn_crypto (no calls to tsleep) currently. -+ * hifn_crypto() returns HIFN_CRYPTO_RINGS_FULL if there is not enough -+ * room in any of the rings for the request to proceed. -+ * -+ * Return Values -+ * ============= -+ * 0 for success, negative values on error -+ * -+ * Defines for negative error codes are: -+ * -+ * HIFN_CRYPTO_BAD_INPUT : The passed in command had invalid settings. -+ * HIFN_CRYPTO_RINGS_FULL : All DMA rings were full and non-blocking -+ * behaviour was requested. -+ * -+ *************************************************************************/ -+ -+/* -+ * Convert back and forth from 'sid' to 'card' and 'session' -+ */ -+#define HIFN_CARD(sid) (((sid) & 0xf0000000) >> 28) -+#define HIFN_SESSION(sid) ((sid) & 0x000007ff) -+#define HIFN_SID(crd,ses) (((crd) << 28) | ((ses) & 0x7ff)) -+ -+#endif /* _KERNEL */ -+ -+struct hifn_stats { -+ u_int64_t hst_ibytes; -+ u_int64_t hst_obytes; -+ u_int32_t hst_ipackets; -+ u_int32_t hst_opackets; -+ u_int32_t hst_invalid; -+ u_int32_t hst_nomem; /* malloc or one of hst_nomem_* */ -+ u_int32_t hst_abort; -+ u_int32_t hst_noirq; /* IRQ for no reason */ -+ u_int32_t hst_totbatch; /* ops submitted w/o interrupt */ -+ u_int32_t hst_maxbatch; /* max ops submitted together */ -+ u_int32_t hst_unaligned; /* unaligned src caused copy */ -+ /* -+ * The following divides hst_nomem into more specific buckets. -+ */ -+ u_int32_t hst_nomem_map; /* bus_dmamap_create failed */ -+ u_int32_t hst_nomem_load; /* bus_dmamap_load_* failed */ -+ u_int32_t hst_nomem_mbuf; /* MGET* failed */ -+ u_int32_t hst_nomem_mcl; /* MCLGET* failed */ -+ u_int32_t hst_nomem_cr; /* out of command/result descriptor */ -+ u_int32_t hst_nomem_sd; /* out of src/dst descriptors */ -+}; -+ -+#endif /* __HIFN7751VAR_H__ */ -diff -Nur linux-2.6.36.orig/crypto/ocf/hifn/hifnHIPP.c linux-2.6.36/crypto/ocf/hifn/hifnHIPP.c ---- linux-2.6.36.orig/crypto/ocf/hifn/hifnHIPP.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/hifn/hifnHIPP.c 2010-11-09 20:28:04.881244876 +0100 -@@ -0,0 +1,420 @@ -+/*- -+ * Driver for Hifn HIPP-I/II chipset -+ * Copyright (c) 2006 Michael Richardson -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored by Hifn Inc. -+ * -+ */ -+ -+/* -+ * Driver for various Hifn encryption processors. -+ */ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "hifnHIPPreg.h" -+#include "hifnHIPPvar.h" -+ -+#if 1 -+#define DPRINTF(a...) if (hipp_debug) { \ -+ printk("%s: ", sc ? \ -+ device_get_nameunit(sc->sc_dev) : "hifn"); \ -+ printk(a); \ -+ } else -+#else -+#define DPRINTF(a...) -+#endif -+ -+typedef int bus_size_t; -+ -+static inline int -+pci_get_revid(struct pci_dev *dev) -+{ -+ u8 rid = 0; -+ pci_read_config_byte(dev, PCI_REVISION_ID, &rid); -+ return rid; -+} -+ -+#define debug hipp_debug -+int hipp_debug = 0; -+module_param(hipp_debug, int, 0644); -+MODULE_PARM_DESC(hipp_debug, "Enable debug"); -+ -+int hipp_maxbatch = 1; -+module_param(hipp_maxbatch, int, 0644); -+MODULE_PARM_DESC(hipp_maxbatch, "max ops to batch w/o interrupt"); -+ -+static int hipp_probe(struct pci_dev *dev, const struct pci_device_id *ent); -+static void hipp_remove(struct pci_dev *dev); -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) -+static irqreturn_t hipp_intr(int irq, void *arg); -+#else -+static irqreturn_t hipp_intr(int irq, void *arg, struct pt_regs *regs); -+#endif -+ -+static int hipp_num_chips = 0; -+static struct hipp_softc *hipp_chip_idx[HIPP_MAX_CHIPS]; -+ -+static int hipp_newsession(device_t, u_int32_t *, struct cryptoini *); -+static int hipp_freesession(device_t, u_int64_t); -+static int hipp_process(device_t, struct cryptop *, int); -+ -+static device_method_t hipp_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, hipp_newsession), -+ DEVMETHOD(cryptodev_freesession,hipp_freesession), -+ DEVMETHOD(cryptodev_process, hipp_process), -+}; -+ -+static __inline u_int32_t -+READ_REG(struct hipp_softc *sc, unsigned int barno, bus_size_t reg) -+{ -+ u_int32_t v = readl(sc->sc_bar[barno] + reg); -+ //sc->sc_bar0_lastreg = (bus_size_t) -1; -+ return (v); -+} -+static __inline void -+WRITE_REG(struct hipp_softc *sc, unsigned int barno, bus_size_t reg, u_int32_t val) -+{ -+ writel(val, sc->sc_bar[barno] + reg); -+} -+ -+#define READ_REG_0(sc, reg) READ_REG(sc, 0, reg) -+#define WRITE_REG_0(sc, reg, val) WRITE_REG(sc,0, reg, val) -+#define READ_REG_1(sc, reg) READ_REG(sc, 1, reg) -+#define WRITE_REG_1(sc, reg, val) WRITE_REG(sc,1, reg, val) -+ -+static int -+hipp_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) -+{ -+ return EINVAL; -+} -+ -+static int -+hipp_freesession(device_t dev, u_int64_t tid) -+{ -+ return EINVAL; -+} -+ -+static int -+hipp_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ return EINVAL; -+} -+ -+static const char* -+hipp_partname(struct hipp_softc *sc, char buf[128], size_t blen) -+{ -+ char *n = NULL; -+ -+ switch (pci_get_vendor(sc->sc_pcidev)) { -+ case PCI_VENDOR_HIFN: -+ switch (pci_get_device(sc->sc_pcidev)) { -+ case PCI_PRODUCT_HIFN_7855: n = "Hifn 7855"; -+ case PCI_PRODUCT_HIFN_8155: n = "Hifn 8155"; -+ case PCI_PRODUCT_HIFN_6500: n = "Hifn 6500"; -+ } -+ } -+ -+ if(n==NULL) { -+ snprintf(buf, blen, "VID=%02x,PID=%02x", -+ pci_get_vendor(sc->sc_pcidev), -+ pci_get_device(sc->sc_pcidev)); -+ } else { -+ buf[0]='\0'; -+ strncat(buf, n, blen); -+ } -+ return buf; -+} -+ -+struct hipp_fs_entry { -+ struct attribute attr; -+ /* other stuff */ -+}; -+ -+ -+static ssize_t -+cryptoid_show(struct device *dev, -+ struct device_attribute *attr, -+ char *buf) -+{ -+ struct hipp_softc *sc; -+ -+ sc = pci_get_drvdata(to_pci_dev (dev)); -+ return sprintf (buf, "%d\n", sc->sc_cid); -+} -+ -+struct device_attribute hipp_dev_cryptoid = __ATTR_RO(cryptoid); -+ -+/* -+ * Attach an interface that successfully probed. -+ */ -+static int -+hipp_probe(struct pci_dev *dev, const struct pci_device_id *ent) -+{ -+ struct hipp_softc *sc = NULL; -+ int i; -+ //char rbase; -+ //u_int16_t ena; -+ int rev; -+ //int rseg; -+ int rc; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (pci_enable_device(dev) < 0) -+ return(-ENODEV); -+ -+ if (pci_set_mwi(dev)) -+ return(-ENODEV); -+ -+ if (!dev->irq) { -+ printk("hifn: found device with no IRQ assigned. check BIOS settings!"); -+ pci_disable_device(dev); -+ return(-ENODEV); -+ } -+ -+ sc = (struct hipp_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); -+ if (!sc) -+ return(-ENOMEM); -+ memset(sc, 0, sizeof(*sc)); -+ -+ softc_device_init(sc, "hifn-hipp", hipp_num_chips, hipp_methods); -+ -+ sc->sc_pcidev = dev; -+ sc->sc_irq = -1; -+ sc->sc_cid = -1; -+ sc->sc_num = hipp_num_chips++; -+ -+ if (sc->sc_num < HIPP_MAX_CHIPS) -+ hipp_chip_idx[sc->sc_num] = sc; -+ -+ pci_set_drvdata(sc->sc_pcidev, sc); -+ -+ spin_lock_init(&sc->sc_mtx); -+ -+ /* -+ * Setup PCI resources. -+ * The READ_REG_0, WRITE_REG_0, READ_REG_1, -+ * and WRITE_REG_1 macros throughout the driver are used -+ * to permit better debugging. -+ */ -+ for(i=0; i<4; i++) { -+ unsigned long mem_start, mem_len; -+ mem_start = pci_resource_start(sc->sc_pcidev, i); -+ mem_len = pci_resource_len(sc->sc_pcidev, i); -+ sc->sc_barphy[i] = (caddr_t)mem_start; -+ sc->sc_bar[i] = (ocf_iomem_t) ioremap(mem_start, mem_len); -+ if (!sc->sc_bar[i]) { -+ device_printf(sc->sc_dev, "cannot map bar%d register space\n", i); -+ goto fail; -+ } -+ } -+ -+ //hipp_reset_board(sc, 0); -+ pci_set_master(sc->sc_pcidev); -+ -+ /* -+ * Arrange the interrupt line. -+ */ -+ rc = request_irq(dev->irq, hipp_intr, IRQF_SHARED, "hifn", sc); -+ if (rc) { -+ device_printf(sc->sc_dev, "could not map interrupt: %d\n", rc); -+ goto fail; -+ } -+ sc->sc_irq = dev->irq; -+ -+ rev = READ_REG_1(sc, HIPP_1_REVID) & 0xffff; -+ -+ { -+ char b[32]; -+ device_printf(sc->sc_dev, "%s, rev %u", -+ hipp_partname(sc, b, sizeof(b)), rev); -+ } -+ -+#if 0 -+ if (sc->sc_flags & HIFN_IS_7956) -+ printf(", pll=0x%x<%s clk, %ux mult>", -+ sc->sc_pllconfig, -+ sc->sc_pllconfig & HIFN_PLL_REF_SEL ? "ext" : "pci", -+ 2 + 2*((sc->sc_pllconfig & HIFN_PLL_ND) >> 11)); -+#endif -+ printf("\n"); -+ -+ sc->sc_cid = crypto_get_driverid(softc_get_device(sc),CRYPTOCAP_F_HARDWARE); -+ if (sc->sc_cid < 0) { -+ device_printf(sc->sc_dev, "could not get crypto driver id\n"); -+ goto fail; -+ } -+ -+#if 0 /* cannot work with a non-GPL module */ -+ /* make a sysfs entry to let the world know what entry we got */ -+ sysfs_create_file(&sc->sc_pcidev->dev.kobj, &hipp_dev_cryptoid.attr); -+#endif -+ -+#if 0 -+ init_timer(&sc->sc_tickto); -+ sc->sc_tickto.function = hifn_tick; -+ sc->sc_tickto.data = (unsigned long) sc->sc_num; -+ mod_timer(&sc->sc_tickto, jiffies + HZ); -+#endif -+ -+#if 0 /* no code here yet ?? */ -+ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); -+#endif -+ -+ return (0); -+ -+fail: -+ if (sc->sc_cid >= 0) -+ crypto_unregister_all(sc->sc_cid); -+ if (sc->sc_irq != -1) -+ free_irq(sc->sc_irq, sc); -+ -+#if 0 -+ if (sc->sc_dma) { -+ /* Turn off DMA polling */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | -+ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); -+ -+ pci_free_consistent(sc->sc_pcidev, -+ sizeof(*sc->sc_dma), -+ sc->sc_dma, sc->sc_dma_physaddr); -+ } -+#endif -+ kfree(sc); -+ return (-ENXIO); -+} -+ -+/* -+ * Detach an interface that successfully probed. -+ */ -+static void -+hipp_remove(struct pci_dev *dev) -+{ -+ struct hipp_softc *sc = pci_get_drvdata(dev); -+ unsigned long l_flags; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ /* disable interrupts */ -+ HIPP_LOCK(sc); -+ -+#if 0 -+ WRITE_REG_1(sc, HIFN_1_DMA_IER, 0); -+ HIFN_UNLOCK(sc); -+ -+ /*XXX other resources */ -+ del_timer_sync(&sc->sc_tickto); -+ -+ /* Turn off DMA polling */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | -+ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); -+#endif -+ -+ crypto_unregister_all(sc->sc_cid); -+ -+ free_irq(sc->sc_irq, sc); -+ -+#if 0 -+ pci_free_consistent(sc->sc_pcidev, sizeof(*sc->sc_dma), -+ sc->sc_dma, sc->sc_dma_physaddr); -+#endif -+} -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) -+static irqreturn_t hipp_intr(int irq, void *arg) -+#else -+static irqreturn_t hipp_intr(int irq, void *arg, struct pt_regs *regs) -+#endif -+{ -+ struct hipp_softc *sc = arg; -+ -+ sc = sc; /* shut up compiler */ -+ -+ return IRQ_HANDLED; -+} -+ -+static struct pci_device_id hipp_pci_tbl[] = { -+ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7855, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_8155, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+}; -+MODULE_DEVICE_TABLE(pci, hipp_pci_tbl); -+ -+static struct pci_driver hipp_driver = { -+ .name = "hipp", -+ .id_table = hipp_pci_tbl, -+ .probe = hipp_probe, -+ .remove = hipp_remove, -+ /* add PM stuff here one day */ -+}; -+ -+static int __init hipp_init (void) -+{ -+ struct hipp_softc *sc = NULL; -+ int rc; -+ -+ DPRINTF("%s(%p)\n", __FUNCTION__, hipp_init); -+ -+ rc = pci_register_driver(&hipp_driver); -+ pci_register_driver_compat(&hipp_driver, rc); -+ -+ return rc; -+} -+ -+static void __exit hipp_exit (void) -+{ -+ pci_unregister_driver(&hipp_driver); -+} -+ -+module_init(hipp_init); -+module_exit(hipp_exit); -+ -+MODULE_LICENSE("BSD"); -+MODULE_AUTHOR("Michael Richardson "); -+MODULE_DESCRIPTION("OCF driver for hifn HIPP-I/II PCI crypto devices"); -diff -Nur linux-2.6.36.orig/crypto/ocf/hifn/hifnHIPPreg.h linux-2.6.36/crypto/ocf/hifn/hifnHIPPreg.h ---- linux-2.6.36.orig/crypto/ocf/hifn/hifnHIPPreg.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/hifn/hifnHIPPreg.h 2010-11-09 20:28:04.922495399 +0100 -@@ -0,0 +1,46 @@ -+/*- -+ * Hifn HIPP-I/HIPP-II (7855/8155) driver. -+ * Copyright (c) 2006 Michael Richardson -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored by Hifn inc. -+ * -+ */ -+ -+#ifndef __HIFNHIPP_H__ -+#define __HIFNHIPP_H__ -+ -+/* -+ * PCI vendor and device identifiers -+ */ -+#define PCI_VENDOR_HIFN 0x13a3 /* Hifn */ -+#define PCI_PRODUCT_HIFN_6500 0x0006 /* 6500 */ -+#define PCI_PRODUCT_HIFN_7855 0x001f /* 7855 */ -+#define PCI_PRODUCT_HIFN_8155 0x999 /* XXX 8155 */ -+ -+#define HIPP_1_REVID 0x01 /* BOGUS */ -+ -+#endif /* __HIPP_H__ */ -diff -Nur linux-2.6.36.orig/crypto/ocf/hifn/hifnHIPPvar.h linux-2.6.36/crypto/ocf/hifn/hifnHIPPvar.h ---- linux-2.6.36.orig/crypto/ocf/hifn/hifnHIPPvar.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/hifn/hifnHIPPvar.h 2010-11-09 20:28:04.964807923 +0100 -@@ -0,0 +1,93 @@ -+/* -+ * Hifn HIPP-I/HIPP-II (7855/8155) driver. -+ * Copyright (c) 2006 Michael Richardson * -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored by Hifn inc. -+ * -+ */ -+ -+#ifndef __HIFNHIPPVAR_H__ -+#define __HIFNHIPPVAR_H__ -+ -+#define HIPP_MAX_CHIPS 8 -+ -+/* -+ * Holds data specific to a single Hifn HIPP-I board. -+ */ -+struct hipp_softc { -+ softc_device_decl sc_dev; -+ -+ struct pci_dev *sc_pcidev; /* device backpointer */ -+ ocf_iomem_t sc_bar[5]; -+ caddr_t sc_barphy[5]; /* physical address */ -+ int sc_num; /* for multiple devs */ -+ spinlock_t sc_mtx; /* per-instance lock */ -+ int32_t sc_cid; -+ int sc_irq; -+ -+#if 0 -+ -+ u_int32_t sc_dmaier; -+ u_int32_t sc_drammodel; /* 1=dram, 0=sram */ -+ u_int32_t sc_pllconfig; /* 7954/7955/7956 PLL config */ -+ -+ struct hifn_dma *sc_dma; -+ dma_addr_t sc_dma_physaddr;/* physical address of sc_dma */ -+ -+ int sc_dmansegs; -+ int sc_maxses; -+ int sc_nsessions; -+ struct hifn_session *sc_sessions; -+ int sc_ramsize; -+ int sc_flags; -+#define HIFN_HAS_RNG 0x1 /* includes random number generator */ -+#define HIFN_HAS_PUBLIC 0x2 /* includes public key support */ -+#define HIFN_HAS_AES 0x4 /* includes AES support */ -+#define HIFN_IS_7811 0x8 /* Hifn 7811 part */ -+#define HIFN_IS_7956 0x10 /* Hifn 7956/7955 don't have SDRAM */ -+ -+ struct timer_list sc_tickto; /* for managing DMA */ -+ -+ int sc_rngfirst; -+ int sc_rnghz; /* RNG polling frequency */ -+ -+ int sc_c_busy; /* command ring busy */ -+ int sc_s_busy; /* source data ring busy */ -+ int sc_d_busy; /* destination data ring busy */ -+ int sc_r_busy; /* result ring busy */ -+ int sc_active; /* for initial countdown */ -+ int sc_needwakeup; /* ops q'd wating on resources */ -+ int sc_curbatch; /* # ops submitted w/o int */ -+ int sc_suspended; -+ struct miscdevice sc_miscdev; -+#endif -+}; -+ -+#define HIPP_LOCK(_sc) spin_lock_irqsave(&(_sc)->sc_mtx, l_flags) -+#define HIPP_UNLOCK(_sc) spin_unlock_irqrestore(&(_sc)->sc_mtx, l_flags) -+ -+#endif /* __HIFNHIPPVAR_H__ */ -diff -Nur linux-2.6.36.orig/crypto/ocf/hifn/Makefile linux-2.6.36/crypto/ocf/hifn/Makefile ---- linux-2.6.36.orig/crypto/ocf/hifn/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/hifn/Makefile 2010-11-09 20:28:05.002825564 +0100 -@@ -0,0 +1,13 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+obj-$(CONFIG_OCF_HIFN) += hifn7751.o -+obj-$(CONFIG_OCF_HIFNHIPP) += hifnHIPP.o -+ -+obj ?= . -+EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/ixp4xx/ixp4xx.c linux-2.6.36/crypto/ocf/ixp4xx/ixp4xx.c ---- linux-2.6.36.orig/crypto/ocf/ixp4xx/ixp4xx.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/ixp4xx/ixp4xx.c 2010-11-09 20:28:05.051258556 +0100 -@@ -0,0 +1,1324 @@ -+/* -+ * An OCF module that uses Intels IXP CryptACC API to do the crypto. -+ * This driver requires the IXP400 Access Library that is available -+ * from Intel in order to operate (or compile). -+ * -+ * Written by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * ALTERNATIVELY, provided that this notice is retained in full, this product -+ * may be distributed under the terms of the GNU General Public License (GPL), -+ * in which case the provisions of the GPL apply INSTEAD OF those given above. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ */ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#ifndef IX_MBUF_PRIV -+#define IX_MBUF_PRIV(x) ((x)->priv) -+#endif -+ -+struct ixp_data; -+ -+struct ixp_q { -+ struct list_head ixp_q_list; -+ struct ixp_data *ixp_q_data; -+ struct cryptop *ixp_q_crp; -+ struct cryptodesc *ixp_q_ccrd; -+ struct cryptodesc *ixp_q_acrd; -+ IX_MBUF ixp_q_mbuf; -+ UINT8 *ixp_hash_dest; /* Location for hash in client buffer */ -+ UINT8 *ixp_hash_src; /* Location of hash in internal buffer */ -+ unsigned char ixp_q_iv_data[IX_CRYPTO_ACC_MAX_CIPHER_IV_LENGTH]; -+ unsigned char *ixp_q_iv; -+}; -+ -+struct ixp_data { -+ int ixp_registered; /* is the context registered */ -+ int ixp_crd_flags; /* detect direction changes */ -+ -+ int ixp_cipher_alg; -+ int ixp_auth_alg; -+ -+ UINT32 ixp_ctx_id; -+ UINT32 ixp_hash_key_id; /* used when hashing */ -+ IxCryptoAccCtx ixp_ctx; -+ IX_MBUF ixp_pri_mbuf; -+ IX_MBUF ixp_sec_mbuf; -+ -+ struct work_struct ixp_pending_work; -+ struct work_struct ixp_registration_work; -+ struct list_head ixp_q; /* unprocessed requests */ -+}; -+ -+#ifdef __ixp46X -+ -+#define MAX_IOP_SIZE 64 /* words */ -+#define MAX_OOP_SIZE 128 -+ -+#define MAX_PARAMS 3 -+ -+struct ixp_pkq { -+ struct list_head pkq_list; -+ struct cryptkop *pkq_krp; -+ -+ IxCryptoAccPkeEauInOperands pkq_op; -+ IxCryptoAccPkeEauOpResult pkq_result; -+ -+ UINT32 pkq_ibuf0[MAX_IOP_SIZE]; -+ UINT32 pkq_ibuf1[MAX_IOP_SIZE]; -+ UINT32 pkq_ibuf2[MAX_IOP_SIZE]; -+ UINT32 pkq_obuf[MAX_OOP_SIZE]; -+}; -+ -+static LIST_HEAD(ixp_pkq); /* current PK wait list */ -+static struct ixp_pkq *ixp_pk_cur; -+static spinlock_t ixp_pkq_lock; -+ -+#endif /* __ixp46X */ -+ -+static int ixp_blocked = 0; -+ -+static int32_t ixp_id = -1; -+static struct ixp_data **ixp_sessions = NULL; -+static u_int32_t ixp_sesnum = 0; -+ -+static int ixp_process(device_t, struct cryptop *, int); -+static int ixp_newsession(device_t, u_int32_t *, struct cryptoini *); -+static int ixp_freesession(device_t, u_int64_t); -+#ifdef __ixp46X -+static int ixp_kprocess(device_t, struct cryptkop *krp, int hint); -+#endif -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) -+static kmem_cache_t *qcache; -+#else -+static struct kmem_cache *qcache; -+#endif -+ -+#define debug ixp_debug -+static int ixp_debug = 0; -+module_param(ixp_debug, int, 0644); -+MODULE_PARM_DESC(ixp_debug, "Enable debug"); -+ -+static int ixp_init_crypto = 1; -+module_param(ixp_init_crypto, int, 0444); /* RO after load/boot */ -+MODULE_PARM_DESC(ixp_init_crypto, "Call ixCryptoAccInit (default is 1)"); -+ -+static void ixp_process_pending(void *arg); -+static void ixp_registration(void *arg); -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void ixp_process_pending_wq(struct work_struct *work); -+static void ixp_registration_wq(struct work_struct *work); -+#endif -+ -+/* -+ * dummy device structure -+ */ -+ -+static struct { -+ softc_device_decl sc_dev; -+} ixpdev; -+ -+static device_method_t ixp_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, ixp_newsession), -+ DEVMETHOD(cryptodev_freesession,ixp_freesession), -+ DEVMETHOD(cryptodev_process, ixp_process), -+#ifdef __ixp46X -+ DEVMETHOD(cryptodev_kprocess, ixp_kprocess), -+#endif -+}; -+ -+/* -+ * Generate a new software session. -+ */ -+static int -+ixp_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) -+{ -+ struct ixp_data *ixp; -+ u_int32_t i; -+#define AUTH_LEN(cri, def) \ -+ (cri->cri_mlen ? cri->cri_mlen : (def)) -+ -+ dprintk("%s():alg %d\n", __FUNCTION__,cri->cri_alg); -+ if (sid == NULL || cri == NULL) { -+ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ if (ixp_sessions) { -+ for (i = 1; i < ixp_sesnum; i++) -+ if (ixp_sessions[i] == NULL) -+ break; -+ } else -+ i = 1; /* NB: to silence compiler warning */ -+ -+ if (ixp_sessions == NULL || i == ixp_sesnum) { -+ struct ixp_data **ixpd; -+ -+ if (ixp_sessions == NULL) { -+ i = 1; /* We leave ixp_sessions[0] empty */ -+ ixp_sesnum = CRYPTO_SW_SESSIONS; -+ } else -+ ixp_sesnum *= 2; -+ -+ ixpd = kmalloc(ixp_sesnum * sizeof(struct ixp_data *), SLAB_ATOMIC); -+ if (ixpd == NULL) { -+ /* Reset session number */ -+ if (ixp_sesnum == CRYPTO_SW_SESSIONS) -+ ixp_sesnum = 0; -+ else -+ ixp_sesnum /= 2; -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memset(ixpd, 0, ixp_sesnum * sizeof(struct ixp_data *)); -+ -+ /* Copy existing sessions */ -+ if (ixp_sessions) { -+ memcpy(ixpd, ixp_sessions, -+ (ixp_sesnum / 2) * sizeof(struct ixp_data *)); -+ kfree(ixp_sessions); -+ } -+ -+ ixp_sessions = ixpd; -+ } -+ -+ ixp_sessions[i] = (struct ixp_data *) kmalloc(sizeof(struct ixp_data), -+ SLAB_ATOMIC); -+ if (ixp_sessions[i] == NULL) { -+ ixp_freesession(NULL, i); -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ -+ *sid = i; -+ -+ ixp = ixp_sessions[i]; -+ memset(ixp, 0, sizeof(*ixp)); -+ -+ ixp->ixp_cipher_alg = -1; -+ ixp->ixp_auth_alg = -1; -+ ixp->ixp_ctx_id = -1; -+ INIT_LIST_HEAD(&ixp->ixp_q); -+ -+ ixp->ixp_ctx.useDifferentSrcAndDestMbufs = 0; -+ -+ while (cri) { -+ switch (cri->cri_alg) { -+ case CRYPTO_DES_CBC: -+ ixp->ixp_cipher_alg = cri->cri_alg; -+ ixp->ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_DES; -+ ixp->ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; -+ ixp->ixp_ctx.cipherCtx.cipherKeyLen = (cri->cri_klen + 7) / 8; -+ ixp->ixp_ctx.cipherCtx.cipherBlockLen = IX_CRYPTO_ACC_DES_BLOCK_64; -+ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen = -+ IX_CRYPTO_ACC_DES_IV_64; -+ memcpy(ixp->ixp_ctx.cipherCtx.key.cipherKey, -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ break; -+ -+ case CRYPTO_3DES_CBC: -+ ixp->ixp_cipher_alg = cri->cri_alg; -+ ixp->ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_3DES; -+ ixp->ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; -+ ixp->ixp_ctx.cipherCtx.cipherKeyLen = (cri->cri_klen + 7) / 8; -+ ixp->ixp_ctx.cipherCtx.cipherBlockLen = IX_CRYPTO_ACC_DES_BLOCK_64; -+ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen = -+ IX_CRYPTO_ACC_DES_IV_64; -+ memcpy(ixp->ixp_ctx.cipherCtx.key.cipherKey, -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ break; -+ -+ case CRYPTO_RIJNDAEL128_CBC: -+ ixp->ixp_cipher_alg = cri->cri_alg; -+ ixp->ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_AES; -+ ixp->ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; -+ ixp->ixp_ctx.cipherCtx.cipherKeyLen = (cri->cri_klen + 7) / 8; -+ ixp->ixp_ctx.cipherCtx.cipherBlockLen = 16; -+ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen = 16; -+ memcpy(ixp->ixp_ctx.cipherCtx.key.cipherKey, -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ break; -+ -+ case CRYPTO_MD5: -+ case CRYPTO_MD5_HMAC: -+ ixp->ixp_auth_alg = cri->cri_alg; -+ ixp->ixp_ctx.authCtx.authAlgo = IX_CRYPTO_ACC_AUTH_MD5; -+ ixp->ixp_ctx.authCtx.authDigestLen = AUTH_LEN(cri, MD5_HASH_LEN); -+ ixp->ixp_ctx.authCtx.aadLen = 0; -+ /* Only MD5_HMAC needs a key */ -+ if (cri->cri_alg == CRYPTO_MD5_HMAC) { -+ ixp->ixp_ctx.authCtx.authKeyLen = (cri->cri_klen + 7) / 8; -+ if (ixp->ixp_ctx.authCtx.authKeyLen > -+ sizeof(ixp->ixp_ctx.authCtx.key.authKey)) { -+ printk( -+ "ixp4xx: Invalid key length for MD5_HMAC - %d bits\n", -+ cri->cri_klen); -+ ixp_freesession(NULL, i); -+ return EINVAL; -+ } -+ memcpy(ixp->ixp_ctx.authCtx.key.authKey, -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ } -+ break; -+ -+ case CRYPTO_SHA1: -+ case CRYPTO_SHA1_HMAC: -+ ixp->ixp_auth_alg = cri->cri_alg; -+ ixp->ixp_ctx.authCtx.authAlgo = IX_CRYPTO_ACC_AUTH_SHA1; -+ ixp->ixp_ctx.authCtx.authDigestLen = AUTH_LEN(cri, SHA1_HASH_LEN); -+ ixp->ixp_ctx.authCtx.aadLen = 0; -+ /* Only SHA1_HMAC needs a key */ -+ if (cri->cri_alg == CRYPTO_SHA1_HMAC) { -+ ixp->ixp_ctx.authCtx.authKeyLen = (cri->cri_klen + 7) / 8; -+ if (ixp->ixp_ctx.authCtx.authKeyLen > -+ sizeof(ixp->ixp_ctx.authCtx.key.authKey)) { -+ printk( -+ "ixp4xx: Invalid key length for SHA1_HMAC - %d bits\n", -+ cri->cri_klen); -+ ixp_freesession(NULL, i); -+ return EINVAL; -+ } -+ memcpy(ixp->ixp_ctx.authCtx.key.authKey, -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ } -+ break; -+ -+ default: -+ printk("ixp: unknown algo 0x%x\n", cri->cri_alg); -+ ixp_freesession(NULL, i); -+ return EINVAL; -+ } -+ cri = cri->cri_next; -+ } -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ INIT_WORK(&ixp->ixp_pending_work, ixp_process_pending_wq); -+ INIT_WORK(&ixp->ixp_registration_work, ixp_registration_wq); -+#else -+ INIT_WORK(&ixp->ixp_pending_work, ixp_process_pending, ixp); -+ INIT_WORK(&ixp->ixp_registration_work, ixp_registration, ixp); -+#endif -+ -+ return 0; -+} -+ -+ -+/* -+ * Free a session. -+ */ -+static int -+ixp_freesession(device_t dev, u_int64_t tid) -+{ -+ u_int32_t sid = CRYPTO_SESID2LID(tid); -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid > ixp_sesnum || ixp_sessions == NULL || -+ ixp_sessions[sid] == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ /* Silently accept and return */ -+ if (sid == 0) -+ return 0; -+ -+ if (ixp_sessions[sid]) { -+ if (ixp_sessions[sid]->ixp_ctx_id != -1) { -+ ixCryptoAccCtxUnregister(ixp_sessions[sid]->ixp_ctx_id); -+ ixp_sessions[sid]->ixp_ctx_id = -1; -+ } -+ kfree(ixp_sessions[sid]); -+ } -+ ixp_sessions[sid] = NULL; -+ if (ixp_blocked) { -+ ixp_blocked = 0; -+ crypto_unblock(ixp_id, CRYPTO_SYMQ); -+ } -+ return 0; -+} -+ -+ -+/* -+ * callback for when hash processing is complete -+ */ -+ -+static void -+ixp_hash_perform_cb( -+ UINT32 hash_key_id, -+ IX_MBUF *bufp, -+ IxCryptoAccStatus status) -+{ -+ struct ixp_q *q; -+ -+ dprintk("%s(%u, %p, 0x%x)\n", __FUNCTION__, hash_key_id, bufp, status); -+ -+ if (bufp == NULL) { -+ printk("ixp: NULL buf in %s\n", __FUNCTION__); -+ return; -+ } -+ -+ q = IX_MBUF_PRIV(bufp); -+ if (q == NULL) { -+ printk("ixp: NULL priv in %s\n", __FUNCTION__); -+ return; -+ } -+ -+ if (status == IX_CRYPTO_ACC_STATUS_SUCCESS) { -+ /* On success, need to copy hash back into original client buffer */ -+ memcpy(q->ixp_hash_dest, q->ixp_hash_src, -+ (q->ixp_q_data->ixp_auth_alg == CRYPTO_SHA1) ? -+ SHA1_HASH_LEN : MD5_HASH_LEN); -+ } -+ else { -+ printk("ixp: hash perform failed status=%d\n", status); -+ q->ixp_q_crp->crp_etype = EINVAL; -+ } -+ -+ /* Free internal buffer used for hashing */ -+ kfree(IX_MBUF_MDATA(&q->ixp_q_mbuf)); -+ -+ crypto_done(q->ixp_q_crp); -+ kmem_cache_free(qcache, q); -+} -+ -+/* -+ * setup a request and perform it -+ */ -+static void -+ixp_q_process(struct ixp_q *q) -+{ -+ IxCryptoAccStatus status; -+ struct ixp_data *ixp = q->ixp_q_data; -+ int auth_off = 0; -+ int auth_len = 0; -+ int crypt_off = 0; -+ int crypt_len = 0; -+ int icv_off = 0; -+ char *crypt_func; -+ -+ dprintk("%s(%p)\n", __FUNCTION__, q); -+ -+ if (q->ixp_q_ccrd) { -+ if (q->ixp_q_ccrd->crd_flags & CRD_F_IV_EXPLICIT) { -+ q->ixp_q_iv = q->ixp_q_ccrd->crd_iv; -+ } else { -+ q->ixp_q_iv = q->ixp_q_iv_data; -+ crypto_copydata(q->ixp_q_crp->crp_flags, q->ixp_q_crp->crp_buf, -+ q->ixp_q_ccrd->crd_inject, -+ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen, -+ (caddr_t) q->ixp_q_iv); -+ } -+ -+ if (q->ixp_q_acrd) { -+ auth_off = q->ixp_q_acrd->crd_skip; -+ auth_len = q->ixp_q_acrd->crd_len; -+ icv_off = q->ixp_q_acrd->crd_inject; -+ } -+ -+ crypt_off = q->ixp_q_ccrd->crd_skip; -+ crypt_len = q->ixp_q_ccrd->crd_len; -+ } else { /* if (q->ixp_q_acrd) */ -+ auth_off = q->ixp_q_acrd->crd_skip; -+ auth_len = q->ixp_q_acrd->crd_len; -+ icv_off = q->ixp_q_acrd->crd_inject; -+ } -+ -+ if (q->ixp_q_crp->crp_flags & CRYPTO_F_SKBUF) { -+ struct sk_buff *skb = (struct sk_buff *) q->ixp_q_crp->crp_buf; -+ if (skb_shinfo(skb)->nr_frags) { -+ /* -+ * DAVIDM fix this limitation one day by using -+ * a buffer pool and chaining, it is not currently -+ * needed for current user/kernel space acceleration -+ */ -+ printk("ixp: Cannot handle fragmented skb's yet !\n"); -+ q->ixp_q_crp->crp_etype = ENOENT; -+ goto done; -+ } -+ IX_MBUF_MLEN(&q->ixp_q_mbuf) = -+ IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = skb->len; -+ IX_MBUF_MDATA(&q->ixp_q_mbuf) = skb->data; -+ } else if (q->ixp_q_crp->crp_flags & CRYPTO_F_IOV) { -+ struct uio *uiop = (struct uio *) q->ixp_q_crp->crp_buf; -+ if (uiop->uio_iovcnt != 1) { -+ /* -+ * DAVIDM fix this limitation one day by using -+ * a buffer pool and chaining, it is not currently -+ * needed for current user/kernel space acceleration -+ */ -+ printk("ixp: Cannot handle more than 1 iovec yet !\n"); -+ q->ixp_q_crp->crp_etype = ENOENT; -+ goto done; -+ } -+ IX_MBUF_MLEN(&q->ixp_q_mbuf) = -+ IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = uiop->uio_iov[0].iov_len; -+ IX_MBUF_MDATA(&q->ixp_q_mbuf) = uiop->uio_iov[0].iov_base; -+ } else /* contig buffer */ { -+ IX_MBUF_MLEN(&q->ixp_q_mbuf) = -+ IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = q->ixp_q_crp->crp_ilen; -+ IX_MBUF_MDATA(&q->ixp_q_mbuf) = q->ixp_q_crp->crp_buf; -+ } -+ -+ IX_MBUF_PRIV(&q->ixp_q_mbuf) = q; -+ -+ if (ixp->ixp_auth_alg == CRYPTO_SHA1 || ixp->ixp_auth_alg == CRYPTO_MD5) { -+ /* -+ * For SHA1 and MD5 hash, need to create an internal buffer that is big -+ * enough to hold the original data + the appropriate padding for the -+ * hash algorithm. -+ */ -+ UINT8 *tbuf = NULL; -+ -+ IX_MBUF_MLEN(&q->ixp_q_mbuf) = IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = -+ ((IX_MBUF_MLEN(&q->ixp_q_mbuf) * 8) + 72 + 511) / 8; -+ tbuf = kmalloc(IX_MBUF_MLEN(&q->ixp_q_mbuf), SLAB_ATOMIC); -+ -+ if (IX_MBUF_MDATA(&q->ixp_q_mbuf) == NULL) { -+ printk("ixp: kmalloc(%u, SLAB_ATOMIC) failed\n", -+ IX_MBUF_MLEN(&q->ixp_q_mbuf)); -+ q->ixp_q_crp->crp_etype = ENOMEM; -+ goto done; -+ } -+ memcpy(tbuf, &(IX_MBUF_MDATA(&q->ixp_q_mbuf))[auth_off], auth_len); -+ -+ /* Set location in client buffer to copy hash into */ -+ q->ixp_hash_dest = -+ &(IX_MBUF_MDATA(&q->ixp_q_mbuf))[auth_off + auth_len]; -+ -+ IX_MBUF_MDATA(&q->ixp_q_mbuf) = tbuf; -+ -+ /* Set location in internal buffer for where hash starts */ -+ q->ixp_hash_src = &(IX_MBUF_MDATA(&q->ixp_q_mbuf))[auth_len]; -+ -+ crypt_func = "ixCryptoAccHashPerform"; -+ status = ixCryptoAccHashPerform(ixp->ixp_ctx.authCtx.authAlgo, -+ &q->ixp_q_mbuf, ixp_hash_perform_cb, 0, auth_len, auth_len, -+ &ixp->ixp_hash_key_id); -+ } -+ else { -+ crypt_func = "ixCryptoAccAuthCryptPerform"; -+ status = ixCryptoAccAuthCryptPerform(ixp->ixp_ctx_id, &q->ixp_q_mbuf, -+ NULL, auth_off, auth_len, crypt_off, crypt_len, icv_off, -+ q->ixp_q_iv); -+ } -+ -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) -+ return; -+ -+ if (IX_CRYPTO_ACC_STATUS_QUEUE_FULL == status) { -+ q->ixp_q_crp->crp_etype = ENOMEM; -+ goto done; -+ } -+ -+ printk("ixp: %s failed %u\n", crypt_func, status); -+ q->ixp_q_crp->crp_etype = EINVAL; -+ -+done: -+ crypto_done(q->ixp_q_crp); -+ kmem_cache_free(qcache, q); -+} -+ -+ -+/* -+ * because we cannot process the Q from the Register callback -+ * we do it here on a task Q. -+ */ -+ -+static void -+ixp_process_pending(void *arg) -+{ -+ struct ixp_data *ixp = arg; -+ struct ixp_q *q = NULL; -+ -+ dprintk("%s(%p)\n", __FUNCTION__, arg); -+ -+ if (!ixp) -+ return; -+ -+ while (!list_empty(&ixp->ixp_q)) { -+ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); -+ list_del(&q->ixp_q_list); -+ ixp_q_process(q); -+ } -+} -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void -+ixp_process_pending_wq(struct work_struct *work) -+{ -+ struct ixp_data *ixp = container_of(work, struct ixp_data, ixp_pending_work); -+ ixp_process_pending(ixp); -+} -+#endif -+ -+/* -+ * callback for when context registration is complete -+ */ -+ -+static void -+ixp_register_cb(UINT32 ctx_id, IX_MBUF *bufp, IxCryptoAccStatus status) -+{ -+ int i; -+ struct ixp_data *ixp; -+ struct ixp_q *q; -+ -+ dprintk("%s(%d, %p, %d)\n", __FUNCTION__, ctx_id, bufp, status); -+ -+ /* -+ * free any buffer passed in to this routine -+ */ -+ if (bufp) { -+ IX_MBUF_MLEN(bufp) = IX_MBUF_PKT_LEN(bufp) = 0; -+ kfree(IX_MBUF_MDATA(bufp)); -+ IX_MBUF_MDATA(bufp) = NULL; -+ } -+ -+ for (i = 0; i < ixp_sesnum; i++) { -+ ixp = ixp_sessions[i]; -+ if (ixp && ixp->ixp_ctx_id == ctx_id) -+ break; -+ } -+ if (i >= ixp_sesnum) { -+ printk("ixp: invalid context id %d\n", ctx_id); -+ return; -+ } -+ -+ if (IX_CRYPTO_ACC_STATUS_WAIT == status) { -+ /* this is normal to free the first of two buffers */ -+ dprintk("ixp: register not finished yet.\n"); -+ return; -+ } -+ -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS != status) { -+ printk("ixp: register failed 0x%x\n", status); -+ while (!list_empty(&ixp->ixp_q)) { -+ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); -+ list_del(&q->ixp_q_list); -+ q->ixp_q_crp->crp_etype = EINVAL; -+ crypto_done(q->ixp_q_crp); -+ kmem_cache_free(qcache, q); -+ } -+ return; -+ } -+ -+ /* -+ * we are now registered, we cannot start processing the Q here -+ * or we get strange errors with AES (DES/3DES seem to be ok). -+ */ -+ ixp->ixp_registered = 1; -+ schedule_work(&ixp->ixp_pending_work); -+} -+ -+ -+/* -+ * callback for when data processing is complete -+ */ -+ -+static void -+ixp_perform_cb( -+ UINT32 ctx_id, -+ IX_MBUF *sbufp, -+ IX_MBUF *dbufp, -+ IxCryptoAccStatus status) -+{ -+ struct ixp_q *q; -+ -+ dprintk("%s(%d, %p, %p, 0x%x)\n", __FUNCTION__, ctx_id, sbufp, -+ dbufp, status); -+ -+ if (sbufp == NULL) { -+ printk("ixp: NULL sbuf in ixp_perform_cb\n"); -+ return; -+ } -+ -+ q = IX_MBUF_PRIV(sbufp); -+ if (q == NULL) { -+ printk("ixp: NULL priv in ixp_perform_cb\n"); -+ return; -+ } -+ -+ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { -+ printk("ixp: perform failed status=%d\n", status); -+ q->ixp_q_crp->crp_etype = EINVAL; -+ } -+ -+ crypto_done(q->ixp_q_crp); -+ kmem_cache_free(qcache, q); -+} -+ -+ -+/* -+ * registration is not callable at IRQ time, so we defer -+ * to a task queue, this routines completes the registration for us -+ * when the task queue runs -+ * -+ * Unfortunately this means we cannot tell OCF that the driver is blocked, -+ * we do that on the next request. -+ */ -+ -+static void -+ixp_registration(void *arg) -+{ -+ struct ixp_data *ixp = arg; -+ struct ixp_q *q = NULL; -+ IX_MBUF *pri = NULL, *sec = NULL; -+ int status = IX_CRYPTO_ACC_STATUS_SUCCESS; -+ -+ if (!ixp) { -+ printk("ixp: ixp_registration with no arg\n"); -+ return; -+ } -+ -+ if (ixp->ixp_ctx_id != -1) { -+ ixCryptoAccCtxUnregister(ixp->ixp_ctx_id); -+ ixp->ixp_ctx_id = -1; -+ } -+ -+ if (list_empty(&ixp->ixp_q)) { -+ printk("ixp: ixp_registration with no Q\n"); -+ return; -+ } -+ -+ /* -+ * setup the primary and secondary buffers -+ */ -+ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); -+ if (q->ixp_q_acrd) { -+ pri = &ixp->ixp_pri_mbuf; -+ sec = &ixp->ixp_sec_mbuf; -+ IX_MBUF_MLEN(pri) = IX_MBUF_PKT_LEN(pri) = 128; -+ IX_MBUF_MDATA(pri) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); -+ IX_MBUF_MLEN(sec) = IX_MBUF_PKT_LEN(sec) = 128; -+ IX_MBUF_MDATA(sec) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); -+ } -+ -+ /* Only need to register if a crypt op or HMAC op */ -+ if (!(ixp->ixp_auth_alg == CRYPTO_SHA1 || -+ ixp->ixp_auth_alg == CRYPTO_MD5)) { -+ status = ixCryptoAccCtxRegister( -+ &ixp->ixp_ctx, -+ pri, sec, -+ ixp_register_cb, -+ ixp_perform_cb, -+ &ixp->ixp_ctx_id); -+ } -+ else { -+ /* Otherwise we start processing pending q */ -+ schedule_work(&ixp->ixp_pending_work); -+ } -+ -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) -+ return; -+ -+ if (IX_CRYPTO_ACC_STATUS_EXCEED_MAX_TUNNELS == status) { -+ printk("ixp: ixCryptoAccCtxRegister failed (out of tunnels)\n"); -+ ixp_blocked = 1; -+ /* perhaps we should return EGAIN on queued ops ? */ -+ return; -+ } -+ -+ printk("ixp: ixCryptoAccCtxRegister failed %d\n", status); -+ ixp->ixp_ctx_id = -1; -+ -+ /* -+ * everything waiting is toasted -+ */ -+ while (!list_empty(&ixp->ixp_q)) { -+ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); -+ list_del(&q->ixp_q_list); -+ q->ixp_q_crp->crp_etype = ENOENT; -+ crypto_done(q->ixp_q_crp); -+ kmem_cache_free(qcache, q); -+ } -+} -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void -+ixp_registration_wq(struct work_struct *work) -+{ -+ struct ixp_data *ixp = container_of(work, struct ixp_data, -+ ixp_registration_work); -+ ixp_registration(ixp); -+} -+#endif -+ -+/* -+ * Process a request. -+ */ -+static int -+ixp_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ struct ixp_data *ixp; -+ unsigned int lid; -+ struct ixp_q *q = NULL; -+ int status; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ /* Sanity check */ -+ if (crp == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ crp->crp_etype = 0; -+ -+ if (ixp_blocked) -+ return ERESTART; -+ -+ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ /* -+ * find the session we are using -+ */ -+ -+ lid = crp->crp_sid & 0xffffffff; -+ if (lid >= ixp_sesnum || lid == 0 || ixp_sessions == NULL || -+ ixp_sessions[lid] == NULL) { -+ crp->crp_etype = ENOENT; -+ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); -+ goto done; -+ } -+ ixp = ixp_sessions[lid]; -+ -+ /* -+ * setup a new request ready for queuing -+ */ -+ q = kmem_cache_alloc(qcache, SLAB_ATOMIC); -+ if (q == NULL) { -+ dprintk("%s,%d: ENOMEM\n", __FILE__, __LINE__); -+ crp->crp_etype = ENOMEM; -+ goto done; -+ } -+ /* -+ * save some cycles by only zeroing the important bits -+ */ -+ memset(&q->ixp_q_mbuf, 0, sizeof(q->ixp_q_mbuf)); -+ q->ixp_q_ccrd = NULL; -+ q->ixp_q_acrd = NULL; -+ q->ixp_q_crp = crp; -+ q->ixp_q_data = ixp; -+ -+ /* -+ * point the cipher and auth descriptors appropriately -+ * check that we have something to do -+ */ -+ if (crp->crp_desc->crd_alg == ixp->ixp_cipher_alg) -+ q->ixp_q_ccrd = crp->crp_desc; -+ else if (crp->crp_desc->crd_alg == ixp->ixp_auth_alg) -+ q->ixp_q_acrd = crp->crp_desc; -+ else { -+ crp->crp_etype = ENOENT; -+ dprintk("%s,%d: bad desc match: ENOENT\n", __FILE__, __LINE__); -+ goto done; -+ } -+ if (crp->crp_desc->crd_next) { -+ if (crp->crp_desc->crd_next->crd_alg == ixp->ixp_cipher_alg) -+ q->ixp_q_ccrd = crp->crp_desc->crd_next; -+ else if (crp->crp_desc->crd_next->crd_alg == ixp->ixp_auth_alg) -+ q->ixp_q_acrd = crp->crp_desc->crd_next; -+ else { -+ crp->crp_etype = ENOENT; -+ dprintk("%s,%d: bad desc match: ENOENT\n", __FILE__, __LINE__); -+ goto done; -+ } -+ } -+ -+ /* -+ * If there is a direction change for this context then we mark it as -+ * unregistered and re-register is for the new direction. This is not -+ * a very expensive operation and currently only tends to happen when -+ * user-space application are doing benchmarks -+ * -+ * DM - we should be checking for pending requests before unregistering. -+ */ -+ if (q->ixp_q_ccrd && ixp->ixp_registered && -+ ixp->ixp_crd_flags != (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT)) { -+ dprintk("%s - detected direction change on session\n", __FUNCTION__); -+ ixp->ixp_registered = 0; -+ } -+ -+ /* -+ * if we are registered, call straight into the perform code -+ */ -+ if (ixp->ixp_registered) { -+ ixp_q_process(q); -+ return 0; -+ } -+ -+ /* -+ * the only part of the context not set in newsession is the direction -+ * dependent parts -+ */ -+ if (q->ixp_q_ccrd) { -+ ixp->ixp_crd_flags = (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT); -+ if (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT) { -+ ixp->ixp_ctx.operation = q->ixp_q_acrd ? -+ IX_CRYPTO_ACC_OP_ENCRYPT_AUTH : IX_CRYPTO_ACC_OP_ENCRYPT; -+ } else { -+ ixp->ixp_ctx.operation = q->ixp_q_acrd ? -+ IX_CRYPTO_ACC_OP_AUTH_DECRYPT : IX_CRYPTO_ACC_OP_DECRYPT; -+ } -+ } else { -+ /* q->ixp_q_acrd must be set if we are here */ -+ ixp->ixp_ctx.operation = IX_CRYPTO_ACC_OP_AUTH_CALC; -+ } -+ -+ status = list_empty(&ixp->ixp_q); -+ list_add_tail(&q->ixp_q_list, &ixp->ixp_q); -+ if (status) -+ schedule_work(&ixp->ixp_registration_work); -+ return 0; -+ -+done: -+ if (q) -+ kmem_cache_free(qcache, q); -+ crypto_done(crp); -+ return 0; -+} -+ -+ -+#ifdef __ixp46X -+/* -+ * key processing support for the ixp465 -+ */ -+ -+ -+/* -+ * copy a BN (LE) into a buffer (BE) an fill out the op appropriately -+ * assume zeroed and only copy bits that are significant -+ */ -+ -+static int -+ixp_copy_ibuf(struct crparam *p, IxCryptoAccPkeEauOperand *op, UINT32 *buf) -+{ -+ unsigned char *src = (unsigned char *) p->crp_p; -+ unsigned char *dst; -+ int len, bits = p->crp_nbits; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (bits > MAX_IOP_SIZE * sizeof(UINT32) * 8) { -+ dprintk("%s - ibuf too big (%d > %d)\n", __FUNCTION__, -+ bits, MAX_IOP_SIZE * sizeof(UINT32) * 8); -+ return -1; -+ } -+ -+ len = (bits + 31) / 32; /* the number UINT32's needed */ -+ -+ dst = (unsigned char *) &buf[len]; -+ dst--; -+ -+ while (bits > 0) { -+ *dst-- = *src++; -+ bits -= 8; -+ } -+ -+#if 0 /* no need to zero remaining bits as it is done during request alloc */ -+ while (dst > (unsigned char *) buf) -+ *dst-- = '\0'; -+#endif -+ -+ op->pData = buf; -+ op->dataLen = len; -+ return 0; -+} -+ -+/* -+ * copy out the result, be as forgiving as we can about small output buffers -+ */ -+ -+static int -+ixp_copy_obuf(struct crparam *p, IxCryptoAccPkeEauOpResult *op, UINT32 *buf) -+{ -+ unsigned char *dst = (unsigned char *) p->crp_p; -+ unsigned char *src = (unsigned char *) buf; -+ int len, z, bits = p->crp_nbits; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ len = op->dataLen * sizeof(UINT32); -+ -+ /* skip leading zeroes to be small buffer friendly */ -+ z = 0; -+ while (z < len && src[z] == '\0') -+ z++; -+ -+ src += len; -+ src--; -+ len -= z; -+ -+ while (len > 0 && bits > 0) { -+ *dst++ = *src--; -+ len--; -+ bits -= 8; -+ } -+ -+ while (bits > 0) { -+ *dst++ = '\0'; -+ bits -= 8; -+ } -+ -+ if (len > 0) { -+ dprintk("%s - obuf is %d (z=%d, ob=%d) bytes too small\n", -+ __FUNCTION__, len, z, p->crp_nbits / 8); -+ return -1; -+ } -+ -+ return 0; -+} -+ -+ -+/* -+ * the parameter offsets for exp_mod -+ */ -+ -+#define IXP_PARAM_BASE 0 -+#define IXP_PARAM_EXP 1 -+#define IXP_PARAM_MOD 2 -+#define IXP_PARAM_RES 3 -+ -+/* -+ * key processing complete callback, is also used to start processing -+ * by passing a NULL for pResult -+ */ -+ -+static void -+ixp_kperform_cb( -+ IxCryptoAccPkeEauOperation operation, -+ IxCryptoAccPkeEauOpResult *pResult, -+ BOOL carryOrBorrow, -+ IxCryptoAccStatus status) -+{ -+ struct ixp_pkq *q, *tmp; -+ unsigned long flags; -+ -+ dprintk("%s(0x%x, %p, %d, 0x%x)\n", __FUNCTION__, operation, pResult, -+ carryOrBorrow, status); -+ -+ /* handle a completed request */ -+ if (pResult) { -+ if (ixp_pk_cur && &ixp_pk_cur->pkq_result == pResult) { -+ q = ixp_pk_cur; -+ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { -+ dprintk("%s() - op failed 0x%x\n", __FUNCTION__, status); -+ q->pkq_krp->krp_status = ERANGE; /* could do better */ -+ } else { -+ /* copy out the result */ -+ if (ixp_copy_obuf(&q->pkq_krp->krp_param[IXP_PARAM_RES], -+ &q->pkq_result, q->pkq_obuf)) -+ q->pkq_krp->krp_status = ERANGE; -+ } -+ crypto_kdone(q->pkq_krp); -+ kfree(q); -+ ixp_pk_cur = NULL; -+ } else -+ printk("%s - callback with invalid result pointer\n", __FUNCTION__); -+ } -+ -+ spin_lock_irqsave(&ixp_pkq_lock, flags); -+ if (ixp_pk_cur || list_empty(&ixp_pkq)) { -+ spin_unlock_irqrestore(&ixp_pkq_lock, flags); -+ return; -+ } -+ -+ list_for_each_entry_safe(q, tmp, &ixp_pkq, pkq_list) { -+ -+ list_del(&q->pkq_list); -+ ixp_pk_cur = q; -+ -+ spin_unlock_irqrestore(&ixp_pkq_lock, flags); -+ -+ status = ixCryptoAccPkeEauPerform( -+ IX_CRYPTO_ACC_OP_EAU_MOD_EXP, -+ &q->pkq_op, -+ ixp_kperform_cb, -+ &q->pkq_result); -+ -+ if (status == IX_CRYPTO_ACC_STATUS_SUCCESS) { -+ dprintk("%s() - ixCryptoAccPkeEauPerform SUCCESS\n", __FUNCTION__); -+ return; /* callback will return here for callback */ -+ } else if (status == IX_CRYPTO_ACC_STATUS_RETRY) { -+ printk("%s() - ixCryptoAccPkeEauPerform RETRY\n", __FUNCTION__); -+ } else { -+ printk("%s() - ixCryptoAccPkeEauPerform failed %d\n", -+ __FUNCTION__, status); -+ } -+ q->pkq_krp->krp_status = ERANGE; /* could do better */ -+ crypto_kdone(q->pkq_krp); -+ kfree(q); -+ spin_lock_irqsave(&ixp_pkq_lock, flags); -+ } -+ spin_unlock_irqrestore(&ixp_pkq_lock, flags); -+} -+ -+ -+static int -+ixp_kprocess(device_t dev, struct cryptkop *krp, int hint) -+{ -+ struct ixp_pkq *q; -+ int rc = 0; -+ unsigned long flags; -+ -+ dprintk("%s l1=%d l2=%d l3=%d l4=%d\n", __FUNCTION__, -+ krp->krp_param[IXP_PARAM_BASE].crp_nbits, -+ krp->krp_param[IXP_PARAM_EXP].crp_nbits, -+ krp->krp_param[IXP_PARAM_MOD].crp_nbits, -+ krp->krp_param[IXP_PARAM_RES].crp_nbits); -+ -+ -+ if (krp->krp_op != CRK_MOD_EXP) { -+ krp->krp_status = EOPNOTSUPP; -+ goto err; -+ } -+ -+ q = (struct ixp_pkq *) kmalloc(sizeof(*q), GFP_KERNEL); -+ if (q == NULL) { -+ krp->krp_status = ENOMEM; -+ goto err; -+ } -+ -+ /* -+ * The PKE engine does not appear to zero the output buffer -+ * appropriately, so we need to do it all here. -+ */ -+ memset(q, 0, sizeof(*q)); -+ -+ q->pkq_krp = krp; -+ INIT_LIST_HEAD(&q->pkq_list); -+ -+ if (ixp_copy_ibuf(&krp->krp_param[IXP_PARAM_BASE], &q->pkq_op.modExpOpr.M, -+ q->pkq_ibuf0)) -+ rc = 1; -+ if (!rc && ixp_copy_ibuf(&krp->krp_param[IXP_PARAM_EXP], -+ &q->pkq_op.modExpOpr.e, q->pkq_ibuf1)) -+ rc = 2; -+ if (!rc && ixp_copy_ibuf(&krp->krp_param[IXP_PARAM_MOD], -+ &q->pkq_op.modExpOpr.N, q->pkq_ibuf2)) -+ rc = 3; -+ -+ if (rc) { -+ kfree(q); -+ krp->krp_status = ERANGE; -+ goto err; -+ } -+ -+ q->pkq_result.pData = q->pkq_obuf; -+ q->pkq_result.dataLen = -+ (krp->krp_param[IXP_PARAM_RES].crp_nbits + 31) / 32; -+ -+ spin_lock_irqsave(&ixp_pkq_lock, flags); -+ list_add_tail(&q->pkq_list, &ixp_pkq); -+ spin_unlock_irqrestore(&ixp_pkq_lock, flags); -+ -+ if (!ixp_pk_cur) -+ ixp_kperform_cb(0, NULL, 0, 0); -+ return (0); -+ -+err: -+ crypto_kdone(krp); -+ return (0); -+} -+ -+ -+ -+#ifdef CONFIG_OCF_RANDOMHARVEST -+/* -+ * We run the random number generator output through SHA so that it -+ * is FIPS compliant. -+ */ -+ -+static volatile int sha_done = 0; -+static unsigned char sha_digest[20]; -+ -+static void -+ixp_hash_cb(UINT8 *digest, IxCryptoAccStatus status) -+{ -+ dprintk("%s(%p, %d)\n", __FUNCTION__, digest, status); -+ if (sha_digest != digest) -+ printk("digest error\n"); -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) -+ sha_done = 1; -+ else -+ sha_done = -status; -+} -+ -+static int -+ixp_read_random(void *arg, u_int32_t *buf, int maxwords) -+{ -+ IxCryptoAccStatus status; -+ int i, n, rc; -+ -+ dprintk("%s(%p, %d)\n", __FUNCTION__, buf, maxwords); -+ memset(buf, 0, maxwords * sizeof(*buf)); -+ status = ixCryptoAccPkePseudoRandomNumberGet(maxwords, buf); -+ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { -+ dprintk("%s: ixCryptoAccPkePseudoRandomNumberGet failed %d\n", -+ __FUNCTION__, status); -+ return 0; -+ } -+ -+ /* -+ * run the random data through SHA to make it look more random -+ */ -+ -+ n = sizeof(sha_digest); /* process digest bytes at a time */ -+ -+ rc = 0; -+ for (i = 0; i < maxwords; i += n / sizeof(*buf)) { -+ if ((maxwords - i) * sizeof(*buf) < n) -+ n = (maxwords - i) * sizeof(*buf); -+ sha_done = 0; -+ status = ixCryptoAccPkeHashPerform(IX_CRYPTO_ACC_AUTH_SHA1, -+ (UINT8 *) &buf[i], n, ixp_hash_cb, sha_digest); -+ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { -+ dprintk("ixCryptoAccPkeHashPerform failed %d\n", status); -+ return -EIO; -+ } -+ while (!sha_done) -+ schedule(); -+ if (sha_done < 0) { -+ dprintk("ixCryptoAccPkeHashPerform failed CB %d\n", -sha_done); -+ return 0; -+ } -+ memcpy(&buf[i], sha_digest, n); -+ rc += n / sizeof(*buf);; -+ } -+ -+ return rc; -+} -+#endif /* CONFIG_OCF_RANDOMHARVEST */ -+ -+#endif /* __ixp46X */ -+ -+ -+ -+/* -+ * our driver startup and shutdown routines -+ */ -+ -+static int -+ixp_init(void) -+{ -+ dprintk("%s(%p)\n", __FUNCTION__, ixp_init); -+ -+ if (ixp_init_crypto && ixCryptoAccInit() != IX_CRYPTO_ACC_STATUS_SUCCESS) -+ printk("ixCryptoAccInit failed, assuming already initialised!\n"); -+ -+ qcache = kmem_cache_create("ixp4xx_q", sizeof(struct ixp_q), 0, -+ SLAB_HWCACHE_ALIGN, NULL -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) -+ , NULL -+#endif -+ ); -+ if (!qcache) { -+ printk("failed to create Qcache\n"); -+ return -ENOENT; -+ } -+ -+ memset(&ixpdev, 0, sizeof(ixpdev)); -+ softc_device_init(&ixpdev, "ixp4xx", 0, ixp_methods); -+ -+ ixp_id = crypto_get_driverid(softc_get_device(&ixpdev), -+ CRYPTOCAP_F_HARDWARE); -+ if (ixp_id < 0) -+ panic("IXP/OCF crypto device cannot initialize!"); -+ -+#define REGISTER(alg) \ -+ crypto_register(ixp_id,alg,0,0) -+ -+ REGISTER(CRYPTO_DES_CBC); -+ REGISTER(CRYPTO_3DES_CBC); -+ REGISTER(CRYPTO_RIJNDAEL128_CBC); -+#ifdef CONFIG_OCF_IXP4XX_SHA1_MD5 -+ REGISTER(CRYPTO_MD5); -+ REGISTER(CRYPTO_SHA1); -+#endif -+ REGISTER(CRYPTO_MD5_HMAC); -+ REGISTER(CRYPTO_SHA1_HMAC); -+#undef REGISTER -+ -+#ifdef __ixp46X -+ spin_lock_init(&ixp_pkq_lock); -+ /* -+ * we do not enable the go fast options here as they can potentially -+ * allow timing based attacks -+ * -+ * http://www.openssl.org/news/secadv_20030219.txt -+ */ -+ ixCryptoAccPkeEauExpConfig(0, 0); -+ crypto_kregister(ixp_id, CRK_MOD_EXP, 0); -+#ifdef CONFIG_OCF_RANDOMHARVEST -+ crypto_rregister(ixp_id, ixp_read_random, NULL); -+#endif -+#endif -+ -+ return 0; -+} -+ -+static void -+ixp_exit(void) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ crypto_unregister_all(ixp_id); -+ ixp_id = -1; -+ kmem_cache_destroy(qcache); -+ qcache = NULL; -+} -+ -+module_init(ixp_init); -+module_exit(ixp_exit); -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("ixp (OCF module for IXP4xx crypto)"); -diff -Nur linux-2.6.36.orig/crypto/ocf/ixp4xx/Makefile linux-2.6.36/crypto/ocf/ixp4xx/Makefile ---- linux-2.6.36.orig/crypto/ocf/ixp4xx/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/ixp4xx/Makefile 2010-11-09 20:28:05.113478850 +0100 -@@ -0,0 +1,104 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+# -+# You will need to point this at your Intel ixp425 includes, this portion -+# of the Makefile only really works under SGLinux with the appropriate libs -+# installed. They can be downloaded from http://www.snapgear.org/ -+# -+ifeq ($(CONFIG_CPU_IXP46X),y) -+IXPLATFORM = ixp46X -+else -+ifeq ($(CONFIG_CPU_IXP43X),y) -+IXPLATFORM = ixp43X -+else -+IXPLATFORM = ixp42X -+endif -+endif -+ -+ifdef CONFIG_IXP400_LIB_2_4 -+IX_XSCALE_SW = $(ROOTDIR)/modules/ixp425/ixp400-2.4/ixp400_xscale_sw -+OSAL_DIR = $(ROOTDIR)/modules/ixp425/ixp400-2.4/ixp_osal -+endif -+ifdef CONFIG_IXP400_LIB_2_1 -+IX_XSCALE_SW = $(ROOTDIR)/modules/ixp425/ixp400-2.1/ixp400_xscale_sw -+OSAL_DIR = $(ROOTDIR)/modules/ixp425/ixp400-2.1/ixp_osal -+endif -+ifdef CONFIG_IXP400_LIB_2_0 -+IX_XSCALE_SW = $(ROOTDIR)/modules/ixp425/ixp400-2.0/ixp400_xscale_sw -+OSAL_DIR = $(ROOTDIR)/modules/ixp425/ixp400-2.0/ixp_osal -+endif -+ifdef IX_XSCALE_SW -+ifdef CONFIG_IXP400_LIB_2_4 -+IXP_CFLAGS = \ -+ -I$(ROOTDIR)/. \ -+ -I$(IX_XSCALE_SW)/src/include \ -+ -I$(OSAL_DIR)/common/include/ \ -+ -I$(OSAL_DIR)/common/include/modules/ \ -+ -I$(OSAL_DIR)/common/include/modules/ddk/ \ -+ -I$(OSAL_DIR)/common/include/modules/bufferMgt/ \ -+ -I$(OSAL_DIR)/common/include/modules/ioMem/ \ -+ -I$(OSAL_DIR)/common/os/linux/include/ \ -+ -I$(OSAL_DIR)/common/os/linux/include/core/ \ -+ -I$(OSAL_DIR)/common/os/linux/include/modules/ \ -+ -I$(OSAL_DIR)/common/os/linux/include/modules/ddk/ \ -+ -I$(OSAL_DIR)/common/os/linux/include/modules/bufferMgt/ \ -+ -I$(OSAL_DIR)/common/os/linux/include/modules/ioMem/ \ -+ -I$(OSAL_DIR)/platforms/$(IXPLATFORM)/include/ \ -+ -I$(OSAL_DIR)/platforms/$(IXPLATFORM)/os/linux/include/ \ -+ -DENABLE_IOMEM -DENABLE_BUFFERMGT -DENABLE_DDK \ -+ -DUSE_IXP4XX_CRYPTO -+else -+IXP_CFLAGS = \ -+ -I$(ROOTDIR)/. \ -+ -I$(IX_XSCALE_SW)/src/include \ -+ -I$(OSAL_DIR)/ \ -+ -I$(OSAL_DIR)/os/linux/include/ \ -+ -I$(OSAL_DIR)/os/linux/include/modules/ \ -+ -I$(OSAL_DIR)/os/linux/include/modules/ioMem/ \ -+ -I$(OSAL_DIR)/os/linux/include/modules/bufferMgt/ \ -+ -I$(OSAL_DIR)/os/linux/include/core/ \ -+ -I$(OSAL_DIR)/os/linux/include/platforms/ \ -+ -I$(OSAL_DIR)/os/linux/include/platforms/ixp400/ \ -+ -I$(OSAL_DIR)/os/linux/include/platforms/ixp400/ixp425 \ -+ -I$(OSAL_DIR)/os/linux/include/platforms/ixp400/ixp465 \ -+ -I$(OSAL_DIR)/os/linux/include/core/ \ -+ -I$(OSAL_DIR)/include/ \ -+ -I$(OSAL_DIR)/include/modules/ \ -+ -I$(OSAL_DIR)/include/modules/bufferMgt/ \ -+ -I$(OSAL_DIR)/include/modules/ioMem/ \ -+ -I$(OSAL_DIR)/include/platforms/ \ -+ -I$(OSAL_DIR)/include/platforms/ixp400/ \ -+ -DUSE_IXP4XX_CRYPTO -+endif -+endif -+ifdef CONFIG_IXP400_LIB_1_4 -+IXP_CFLAGS = \ -+ -I$(ROOTDIR)/. \ -+ -I$(ROOTDIR)/modules/ixp425/ixp400-1.4/ixp400_xscale_sw/src/include \ -+ -I$(ROOTDIR)/modules/ixp425/ixp400-1.4/ixp400_xscale_sw/src/linux \ -+ -DUSE_IXP4XX_CRYPTO -+endif -+ifndef IXPDIR -+IXPDIR = ixp-version-is-not-supported -+endif -+ -+ifeq ($(CONFIG_CPU_IXP46X),y) -+IXP_CFLAGS += -D__ixp46X -+else -+ifeq ($(CONFIG_CPU_IXP43X),y) -+IXP_CFLAGS += -D__ixp43X -+else -+IXP_CFLAGS += -D__ixp42X -+endif -+endif -+ -+obj-$(CONFIG_OCF_IXP4XX) += ixp4xx.o -+ -+obj ?= . -+EXTRA_CFLAGS += $(IXP_CFLAGS) -I$(obj)/.. -I$(obj)/. -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/Kconfig linux-2.6.36/crypto/ocf/Kconfig ---- linux-2.6.36.orig/crypto/ocf/Kconfig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/Kconfig 2010-11-09 20:28:05.141255099 +0100 -@@ -0,0 +1,119 @@ -+menu "OCF Configuration" -+ -+config OCF_OCF -+ tristate "OCF (Open Cryptograhic Framework)" -+ help -+ A linux port of the OpenBSD/FreeBSD crypto framework. -+ -+config OCF_RANDOMHARVEST -+ bool "crypto random --- harvest entropy for /dev/random" -+ depends on OCF_OCF -+ help -+ Includes code to harvest random numbers from devices that support it. -+ -+config OCF_FIPS -+ bool "enable fips RNG checks" -+ depends on OCF_OCF && OCF_RANDOMHARVEST -+ help -+ Run all RNG provided data through a fips check before -+ adding it /dev/random's entropy pool. -+ -+config OCF_CRYPTODEV -+ tristate "cryptodev (user space support)" -+ depends on OCF_OCF -+ help -+ The user space API to access crypto hardware. -+ -+config OCF_CRYPTOSOFT -+ tristate "cryptosoft (software crypto engine)" -+ depends on OCF_OCF -+ help -+ A software driver for the OCF framework that uses -+ the kernel CryptoAPI. -+ -+config OCF_SAFE -+ tristate "safenet (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ A driver for a number of the safenet Excel crypto accelerators. -+ Currently tested and working on the 1141 and 1741. -+ -+config OCF_IXP4XX -+ tristate "IXP4xx (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ XScale IXP4xx crypto accelerator driver. Requires the -+ Intel Access library. -+ -+config OCF_IXP4XX_SHA1_MD5 -+ bool "IXP4xx SHA1 and MD5 Hashing" -+ depends on OCF_IXP4XX -+ help -+ Allows the IXP4xx crypto accelerator to perform SHA1 and MD5 hashing. -+ Note: this is MUCH slower than using cryptosoft (software crypto engine). -+ -+config OCF_HIFN -+ tristate "hifn (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for various HIFN based crypto accelerators. -+ (7951, 7955, 7956, 7751, 7811) -+ -+config OCF_HIFNHIPP -+ tristate "Hifn HIPP (HW packet crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for various HIFN (HIPP) based crypto accelerators -+ (7855) -+ -+config OCF_TALITOS -+ tristate "talitos (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for Freescale's security engine (SEC/talitos). -+ -+config OCF_PASEMI -+ tristate "pasemi (HW crypto engine)" -+ depends on OCF_OCF && PPC_PASEMI -+ help -+ OCF driver for the PA Semi PWRficient DMA Engine -+ -+config OCF_EP80579 -+ tristate "ep80579 (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for the Intel EP80579 Integrated Processor Product Line. -+ -+config OCF_CRYPTOCTEON -+ tristate "cryptocteon (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for the Cavium OCTEON Processors. -+ -+config OCF_KIRKWOOD -+ tristate "kirkwood (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for the Marvell Kirkwood (88F6xxx) Processors. -+ -+config OCF_C7108 -+ tristate "Micronas 7108 (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for the Microna 7108 Cipher processors. -+ -+config OCF_OCFNULL -+ tristate "ocfnull (fake crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for measuring ipsec overheads (does no crypto) -+ -+config OCF_BENCH -+ tristate "ocf-bench (HW crypto in-kernel benchmark)" -+ depends on OCF_OCF -+ help -+ A very simple encryption test for the in-kernel interface -+ of OCF. Also includes code to benchmark the IXP Access library -+ for comparison. -+ -+endmenu -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.c linux-2.6.36/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.c 2010-11-09 20:28:05.189557501 +0100 -@@ -0,0 +1,317 @@ -+/* rijndael-alg-ref.c v2.0 August '99 -+ * Reference ANSI C code -+ * authors: Paulo Barreto -+ * Vincent Rijmen, K.U.Leuven -+ * -+ * This code is placed in the public domain. -+ */ -+ -+#include "mvOs.h" -+ -+#include "mvAesAlg.h" -+ -+#include "mvAesBoxes.dat" -+ -+ -+MV_U8 mul1(MV_U8 aa, MV_U8 bb); -+void KeyAddition(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC], MV_U8 BC); -+void ShiftRow128Enc(MV_U8 a[4][MAXBC]); -+void ShiftRow128Dec(MV_U8 a[4][MAXBC]); -+void Substitution(MV_U8 a[4][MAXBC], MV_U8 box[256]); -+void MixColumn(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC]); -+void InvMixColumn(MV_U8 a[4][MAXBC]); -+ -+ -+#define mul(aa, bb) (mask[bb] & Alogtable[aa + Logtable[bb]]) -+ -+MV_U8 mul1(MV_U8 aa, MV_U8 bb) -+{ -+ return mask[bb] & Alogtable[aa + Logtable[bb]]; -+} -+ -+ -+void KeyAddition(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC], MV_U8 BC) -+{ -+ /* Exor corresponding text input and round key input bytes -+ */ -+ ((MV_U32*)(&(a[0][0])))[0] ^= ((MV_U32*)(&(rk[0][0])))[0]; -+ ((MV_U32*)(&(a[1][0])))[0] ^= ((MV_U32*)(&(rk[1][0])))[0]; -+ ((MV_U32*)(&(a[2][0])))[0] ^= ((MV_U32*)(&(rk[2][0])))[0]; -+ ((MV_U32*)(&(a[3][0])))[0] ^= ((MV_U32*)(&(rk[3][0])))[0]; -+ -+} -+ -+void ShiftRow128Enc(MV_U8 a[4][MAXBC]) { -+ /* Row 0 remains unchanged -+ * The other three rows are shifted a variable amount -+ */ -+ MV_U8 tmp[MAXBC]; -+ -+ tmp[0] = a[1][1]; -+ tmp[1] = a[1][2]; -+ tmp[2] = a[1][3]; -+ tmp[3] = a[1][0]; -+ -+ ((MV_U32*)(&(a[1][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; -+ /* -+ a[1][0] = tmp[0]; -+ a[1][1] = tmp[1]; -+ a[1][2] = tmp[2]; -+ a[1][3] = tmp[3]; -+ */ -+ tmp[0] = a[2][2]; -+ tmp[1] = a[2][3]; -+ tmp[2] = a[2][0]; -+ tmp[3] = a[2][1]; -+ -+ ((MV_U32*)(&(a[2][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; -+ /* -+ a[2][0] = tmp[0]; -+ a[2][1] = tmp[1]; -+ a[2][2] = tmp[2]; -+ a[2][3] = tmp[3]; -+ */ -+ tmp[0] = a[3][3]; -+ tmp[1] = a[3][0]; -+ tmp[2] = a[3][1]; -+ tmp[3] = a[3][2]; -+ -+ ((MV_U32*)(&(a[3][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; -+ /* -+ a[3][0] = tmp[0]; -+ a[3][1] = tmp[1]; -+ a[3][2] = tmp[2]; -+ a[3][3] = tmp[3]; -+ */ -+} -+ -+void ShiftRow128Dec(MV_U8 a[4][MAXBC]) { -+ /* Row 0 remains unchanged -+ * The other three rows are shifted a variable amount -+ */ -+ MV_U8 tmp[MAXBC]; -+ -+ tmp[0] = a[1][3]; -+ tmp[1] = a[1][0]; -+ tmp[2] = a[1][1]; -+ tmp[3] = a[1][2]; -+ -+ ((MV_U32*)(&(a[1][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; -+ /* -+ a[1][0] = tmp[0]; -+ a[1][1] = tmp[1]; -+ a[1][2] = tmp[2]; -+ a[1][3] = tmp[3]; -+ */ -+ -+ tmp[0] = a[2][2]; -+ tmp[1] = a[2][3]; -+ tmp[2] = a[2][0]; -+ tmp[3] = a[2][1]; -+ -+ ((MV_U32*)(&(a[2][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; -+ /* -+ a[2][0] = tmp[0]; -+ a[2][1] = tmp[1]; -+ a[2][2] = tmp[2]; -+ a[2][3] = tmp[3]; -+ */ -+ -+ tmp[0] = a[3][1]; -+ tmp[1] = a[3][2]; -+ tmp[2] = a[3][3]; -+ tmp[3] = a[3][0]; -+ -+ ((MV_U32*)(&(a[3][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; -+ /* -+ a[3][0] = tmp[0]; -+ a[3][1] = tmp[1]; -+ a[3][2] = tmp[2]; -+ a[3][3] = tmp[3]; -+ */ -+} -+ -+void Substitution(MV_U8 a[4][MAXBC], MV_U8 box[256]) { -+ /* Replace every byte of the input by the byte at that place -+ * in the nonlinear S-box -+ */ -+ int i, j; -+ -+ for(i = 0; i < 4; i++) -+ for(j = 0; j < 4; j++) a[i][j] = box[a[i][j]] ; -+} -+ -+void MixColumn(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC]) { -+ /* Mix the four bytes of every column in a linear way -+ */ -+ MV_U8 b[4][MAXBC]; -+ int i, j; -+ -+ for(j = 0; j < 4; j++){ -+ b[0][j] = mul(25,a[0][j]) ^ mul(1,a[1][j]) ^ a[2][j] ^ a[3][j]; -+ b[1][j] = mul(25,a[1][j]) ^ mul(1,a[2][j]) ^ a[3][j] ^ a[0][j]; -+ b[2][j] = mul(25,a[2][j]) ^ mul(1,a[3][j]) ^ a[0][j] ^ a[1][j]; -+ b[3][j] = mul(25,a[3][j]) ^ mul(1,a[0][j]) ^ a[1][j] ^ a[2][j]; -+ } -+ for(i = 0; i < 4; i++) -+ /*for(j = 0; j < BC; j++) a[i][j] = b[i][j];*/ -+ ((MV_U32*)(&(a[i][0])))[0] = ((MV_U32*)(&(b[i][0])))[0] ^ ((MV_U32*)(&(rk[i][0])))[0];; -+} -+ -+void InvMixColumn(MV_U8 a[4][MAXBC]) { -+ /* Mix the four bytes of every column in a linear way -+ * This is the opposite operation of Mixcolumn -+ */ -+ MV_U8 b[4][MAXBC]; -+ int i, j; -+ -+ for(j = 0; j < 4; j++){ -+ b[0][j] = mul(223,a[0][j]) ^ mul(104,a[1][j]) ^ mul(238,a[2][j]) ^ mul(199,a[3][j]); -+ b[1][j] = mul(223,a[1][j]) ^ mul(104,a[2][j]) ^ mul(238,a[3][j]) ^ mul(199,a[0][j]); -+ b[2][j] = mul(223,a[2][j]) ^ mul(104,a[3][j]) ^ mul(238,a[0][j]) ^ mul(199,a[1][j]); -+ b[3][j] = mul(223,a[3][j]) ^ mul(104,a[0][j]) ^ mul(238,a[1][j]) ^ mul(199,a[2][j]); -+ } -+ for(i = 0; i < 4; i++) -+ /*for(j = 0; j < BC; j++) a[i][j] = b[i][j];*/ -+ ((MV_U32*)(&(a[i][0])))[0] = ((MV_U32*)(&(b[i][0])))[0]; -+} -+ -+int rijndaelKeySched (MV_U8 k[4][MAXKC], int keyBits, int blockBits, MV_U8 W[MAXROUNDS+1][4][MAXBC]) -+{ -+ /* Calculate the necessary round keys -+ * The number of calculations depends on keyBits and blockBits -+ */ -+ int KC, BC, ROUNDS; -+ int i, j, t, rconpointer = 0; -+ MV_U8 tk[4][MAXKC]; -+ -+ switch (keyBits) { -+ case 128: KC = 4; break; -+ case 192: KC = 6; break; -+ case 256: KC = 8; break; -+ default : return (-1); -+ } -+ -+ switch (blockBits) { -+ case 128: BC = 4; break; -+ case 192: BC = 6; break; -+ case 256: BC = 8; break; -+ default : return (-2); -+ } -+ -+ switch (keyBits >= blockBits ? keyBits : blockBits) { -+ case 128: ROUNDS = 10; break; -+ case 192: ROUNDS = 12; break; -+ case 256: ROUNDS = 14; break; -+ default : return (-3); /* this cannot happen */ -+ } -+ -+ -+ for(j = 0; j < KC; j++) -+ for(i = 0; i < 4; i++) -+ tk[i][j] = k[i][j]; -+ t = 0; -+ /* copy values into round key array */ -+ for(j = 0; (j < KC) && (t < (ROUNDS+1)*BC); j++, t++) -+ for(i = 0; i < 4; i++) W[t / BC][i][t % BC] = tk[i][j]; -+ -+ while (t < (ROUNDS+1)*BC) { /* while not enough round key material calculated */ -+ /* calculate new values */ -+ for(i = 0; i < 4; i++) -+ tk[i][0] ^= S[tk[(i+1)%4][KC-1]]; -+ tk[0][0] ^= rcon[rconpointer++]; -+ -+ if (KC != 8) -+ for(j = 1; j < KC; j++) -+ for(i = 0; i < 4; i++) tk[i][j] ^= tk[i][j-1]; -+ else { -+ for(j = 1; j < KC/2; j++) -+ for(i = 0; i < 4; i++) tk[i][j] ^= tk[i][j-1]; -+ for(i = 0; i < 4; i++) tk[i][KC/2] ^= S[tk[i][KC/2 - 1]]; -+ for(j = KC/2 + 1; j < KC; j++) -+ for(i = 0; i < 4; i++) tk[i][j] ^= tk[i][j-1]; -+ } -+ /* copy values into round key array */ -+ for(j = 0; (j < KC) && (t < (ROUNDS+1)*BC); j++, t++) -+ for(i = 0; i < 4; i++) W[t / BC][i][t % BC] = tk[i][j]; -+ } -+ -+ return 0; -+} -+ -+ -+ -+int rijndaelEncrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds) -+{ -+ /* Encryption of one block. -+ */ -+ int r, BC, ROUNDS; -+ -+ BC = 4; -+ ROUNDS = rounds; -+ -+ /* begin with a key addition -+ */ -+ -+ KeyAddition(a,rk[0],BC); -+ -+ /* ROUNDS-1 ordinary rounds -+ */ -+ for(r = 1; r < ROUNDS; r++) { -+ Substitution(a,S); -+ ShiftRow128Enc(a); -+ MixColumn(a, rk[r]); -+ /*KeyAddition(a,rk[r],BC);*/ -+ } -+ -+ /* Last round is special: there is no MixColumn -+ */ -+ Substitution(a,S); -+ ShiftRow128Enc(a); -+ KeyAddition(a,rk[ROUNDS],BC); -+ -+ return 0; -+} -+ -+ -+int rijndaelDecrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds) -+{ -+ int r, BC, ROUNDS; -+ -+ BC = 4; -+ ROUNDS = rounds; -+ -+ /* To decrypt: apply the inverse operations of the encrypt routine, -+ * in opposite order -+ * -+ * (KeyAddition is an involution: it 's equal to its inverse) -+ * (the inverse of Substitution with table S is Substitution with the inverse table of S) -+ * (the inverse of Shiftrow is Shiftrow over a suitable distance) -+ */ -+ -+ /* First the special round: -+ * without InvMixColumn -+ * with extra KeyAddition -+ */ -+ KeyAddition(a,rk[ROUNDS],BC); -+ ShiftRow128Dec(a); -+ Substitution(a,Si); -+ -+ /* ROUNDS-1 ordinary rounds -+ */ -+ for(r = ROUNDS-1; r > 0; r--) { -+ KeyAddition(a,rk[r],BC); -+ InvMixColumn(a); -+ ShiftRow128Dec(a); -+ Substitution(a,Si); -+ -+ } -+ -+ /* End with the extra key addition -+ */ -+ -+ KeyAddition(a,rk[0],BC); -+ -+ return 0; -+} -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.h linux-2.6.36/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.h 2010-11-09 20:28:05.222495460 +0100 -@@ -0,0 +1,19 @@ -+/* rijndael-alg-ref.h v2.0 August '99 -+ * Reference ANSI C code -+ * authors: Paulo Barreto -+ * Vincent Rijmen, K.U.Leuven -+ */ -+#ifndef __RIJNDAEL_ALG_H -+#define __RIJNDAEL_ALG_H -+ -+#define MAXBC (128/32) -+#define MAXKC (256/32) -+#define MAXROUNDS 14 -+ -+ -+int rijndaelKeySched (MV_U8 k[4][MAXKC], int keyBits, int blockBits, MV_U8 rk[MAXROUNDS+1][4][MAXBC]); -+ -+int rijndaelEncrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds); -+int rijndaelDecrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds); -+ -+#endif /* __RIJNDAEL_ALG_H */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/cesa/AES/mvAesApi.c linux-2.6.36/crypto/ocf/kirkwood/cesa/AES/mvAesApi.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/cesa/AES/mvAesApi.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/cesa/AES/mvAesApi.c 2010-11-09 20:28:05.264499847 +0100 -@@ -0,0 +1,312 @@ -+/* rijndael-api-ref.c v2.1 April 2000 -+ * Reference ANSI C code -+ * authors: v2.0 Paulo Barreto -+ * Vincent Rijmen, K.U.Leuven -+ * v2.1 Vincent Rijmen, K.U.Leuven -+ * -+ * This code is placed in the public domain. -+ */ -+#include "mvOs.h" -+ -+#include "mvAes.h" -+#include "mvAesAlg.h" -+ -+ -+/* Defines: -+ Add any additional defines you need -+*/ -+ -+#define MODE_ECB 1 /* Are we ciphering in ECB mode? */ -+#define MODE_CBC 2 /* Are we ciphering in CBC mode? */ -+#define MODE_CFB1 3 /* Are we ciphering in 1-bit CFB mode? */ -+ -+ -+int aesMakeKey(MV_U8 *expandedKey, MV_U8 *keyMaterial, int keyLen, int blockLen) -+{ -+ MV_U8 W[MAXROUNDS+1][4][MAXBC]; -+ MV_U8 k[4][MAXKC]; -+ MV_U8 j; -+ int i, rounds, KC; -+ -+ if (expandedKey == NULL) -+ { -+ return AES_BAD_KEY_INSTANCE; -+ } -+ -+ if (!((keyLen == 128) || (keyLen == 192) || (keyLen == 256))) -+ { -+ return AES_BAD_KEY_MAT; -+ } -+ -+ if (keyMaterial == NULL) -+ { -+ return AES_BAD_KEY_MAT; -+ } -+ -+ /* initialize key schedule: */ -+ for(i=0; i= 3) -+MV_U32 cesaChainLength = 0; -+int chainReqNum = 0; -+MV_U32 chainIndex = 0; -+MV_CESA_REQ* pNextActiveChain = 0; -+MV_CESA_REQ* pEndCurrChain = 0; -+MV_BOOL isFirstReq = MV_TRUE; -+#endif -+ -+static INLINE MV_U8* mvCesaSramAddrGet(void) -+{ -+#ifdef MV_CESA_NO_SRAM -+ return (MV_U8*)cesaSramVirtPtr; -+#else -+ return (MV_U8*)cesaCryptEngBase; -+#endif /* MV_CESA_NO_SRAM */ -+} -+ -+static INLINE MV_ULONG mvCesaSramVirtToPhys(void* pDev, MV_U8* pSramVirt) -+{ -+#ifdef MV_CESA_NO_SRAM -+ return (MV_ULONG)mvOsIoVirtToPhy(NULL, pSramVirt); -+#else -+ return (MV_ULONG)pSramVirt; -+#endif /* MV_CESA_NO_SRAM */ -+} -+ -+/* Internal Function prototypes */ -+ -+static INLINE void mvCesaSramDescrBuild(MV_U32 config, int frag, -+ int cryptoOffset, int ivOffset, int cryptoLength, -+ int macOffset, int digestOffset, int macLength, int macTotalLen, -+ MV_CESA_REQ *pCesaReq, MV_DMA_DESC* pDmaDesc); -+ -+static INLINE void mvCesaSramSaUpdate(short sid, MV_DMA_DESC *pDmaDesc); -+ -+static INLINE int mvCesaDmaCopyPrepare(MV_CESA_MBUF* pMbuf, MV_U8* pSramBuf, -+ MV_DMA_DESC* pDmaDesc, MV_BOOL isToMbuf, -+ int offset, int copySize, MV_BOOL skipFlush); -+ -+static void mvCesaHmacIvGet(MV_CESA_MAC_MODE macMode, unsigned char key[], int keyLength, -+ unsigned char innerIV[], unsigned char outerIV[]); -+ -+static MV_STATUS mvCesaFragAuthComplete(MV_CESA_REQ* pReq, MV_CESA_SA* pSA, -+ int macDataSize); -+ -+static MV_CESA_COMMAND* mvCesaCtrModeInit(void); -+ -+static MV_STATUS mvCesaCtrModePrepare(MV_CESA_COMMAND *pCtrModeCmd, MV_CESA_COMMAND *pCmd); -+static MV_STATUS mvCesaCtrModeComplete(MV_CESA_COMMAND *pOrgCmd, MV_CESA_COMMAND *pCmd); -+static void mvCesaCtrModeFinish(MV_CESA_COMMAND *pCmd); -+ -+static INLINE MV_STATUS mvCesaReqProcess(MV_CESA_REQ* pReq); -+static MV_STATUS mvCesaFragReqProcess(MV_CESA_REQ* pReq, MV_U8 frag); -+ -+static INLINE MV_STATUS mvCesaParamCheck(MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, MV_U8* pFixOffset); -+static INLINE MV_STATUS mvCesaFragParamCheck(MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd); -+ -+static INLINE void mvCesaFragSizeFind(MV_CESA_SA* pSA, MV_CESA_REQ* pReq, -+ int cryptoOffset, int macOffset, -+ int* pCopySize, int* pCryptoDataSize, int* pMacDataSize); -+static MV_STATUS mvCesaMbufCacheUnmap(MV_CESA_MBUF* pMbuf, int offset, int size); -+ -+ -+/* Go to the next request in the request queue */ -+static INLINE MV_CESA_REQ* MV_CESA_REQ_NEXT_PTR(MV_CESA_REQ* pReq) -+{ -+ if(pReq == pCesaReqLast) -+ return pCesaReqFirst; -+ -+ return pReq+1; -+} -+ -+#if (MV_CESA_VERSION >= 3) -+/* Go to the previous request in the request queue */ -+static INLINE MV_CESA_REQ* MV_CESA_REQ_PREV_PTR(MV_CESA_REQ* pReq) -+{ -+ if(pReq == pCesaReqFirst) -+ return pCesaReqLast; -+ -+ return pReq-1; -+} -+ -+#endif -+ -+ -+static INLINE void mvCesaReqProcessStart(MV_CESA_REQ* pReq) -+{ -+ int frag; -+ -+#if (MV_CESA_VERSION >= 3) -+ pReq->state = MV_CESA_CHAIN; -+#else -+ pReq->state = MV_CESA_PROCESS; -+#endif -+ cesaStats.startCount++; -+ -+ if(pReq->fragMode == MV_CESA_FRAG_NONE) -+ { -+ frag = 0; -+ } -+ else -+ { -+ frag = pReq->frags.nextFrag; -+ pReq->frags.nextFrag++; -+ } -+#if (MV_CESA_VERSION >= 2) -+ /* Enable TDMA engine */ -+ MV_REG_WRITE(MV_CESA_TDMA_CURR_DESC_PTR_REG, 0); -+ MV_REG_WRITE(MV_CESA_TDMA_NEXT_DESC_PTR_REG, -+ (MV_U32)mvCesaVirtToPhys(&pReq->dmaDescBuf, pReq->dma[frag].pDmaFirst)); -+#else -+ /* Enable IDMA engine */ -+ MV_REG_WRITE(IDMA_CURR_DESC_PTR_REG(0), 0); -+ MV_REG_WRITE(IDMA_NEXT_DESC_PTR_REG(0), -+ (MV_U32)mvCesaVirtToPhys(&pReq->dmaDescBuf, pReq->dma[frag].pDmaFirst)); -+#endif /* MV_CESA_VERSION >= 2 */ -+ -+#if defined(MV_BRIDGE_SYNC_REORDER) -+ mvOsBridgeReorderWA(); -+#endif -+ -+ /* Start Accelerator */ -+ MV_REG_WRITE(MV_CESA_CMD_REG, MV_CESA_CMD_CHAN_ENABLE_MASK); -+} -+ -+ -+/******************************************************************************* -+* mvCesaHalInit - Initialize the CESA driver -+* -+* DESCRIPTION: -+* This function initialize the CESA driver. -+* 1) Session database -+* 2) Request queue -+* 4) DMA descriptor lists - one list per request. Each list -+* has MV_CESA_MAX_DMA_DESC descriptors. -+* -+* INPUT: -+* numOfSession - maximum number of supported sessions -+* queueDepth - number of elements in the request queue. -+* pSramBase - virtual address of Sram -+* osHandle - A handle used by the OS to allocate memory for the -+* module (Passed to the OS Services layer) -+* -+* RETURN: -+* MV_OK - Success -+* MV_NO_RESOURCE - Fail, can't allocate resources: -+* Session database, request queue, -+* DMA descriptors list, LRU cache database. -+* MV_NOT_ALIGNED - Sram base address is not 8 byte aligned. -+* -+*******************************************************************************/ -+MV_STATUS mvCesaHalInit (int numOfSession, int queueDepth, char* pSramBase, MV_U32 cryptEngBase, -+ void *osHandle) -+{ -+ int i, req; -+ MV_U32 descOffsetReg, configReg; -+ MV_CESA_SRAM_SA *pSramSA; -+ -+ -+ mvOsPrintf("mvCesaInit: sessions=%d, queue=%d, pSram=%p\n", -+ numOfSession, queueDepth, pSramBase); -+ -+ cesaOsHandle = osHandle; -+ /* Create Session database */ -+ pCesaSAD = mvOsMalloc(sizeof(MV_CESA_SA)*numOfSession); -+ if(pCesaSAD == NULL) -+ { -+ mvOsPrintf("mvCesaInit: Can't allocate %u bytes for %d SAs\n", -+ sizeof(MV_CESA_SA)*numOfSession, numOfSession); -+ mvCesaFinish(); -+ return MV_NO_RESOURCE; -+ } -+ memset(pCesaSAD, 0, sizeof(MV_CESA_SA)*numOfSession); -+ cesaMaxSA = numOfSession; -+ -+ /* Allocate imag of sramSA in the DRAM */ -+ cesaSramSaBuf.bufSize = sizeof(MV_CESA_SRAM_SA)*numOfSession + -+ CPU_D_CACHE_LINE_SIZE; -+ -+ cesaSramSaBuf.bufVirtPtr = mvOsIoCachedMalloc(osHandle,cesaSramSaBuf.bufSize, -+ &cesaSramSaBuf.bufPhysAddr, -+ &cesaSramSaBuf.memHandle); -+ -+ if(cesaSramSaBuf.bufVirtPtr == NULL) -+ { -+ mvOsPrintf("mvCesaInit: Can't allocate %d bytes for sramSA structures\n", -+ cesaSramSaBuf.bufSize); -+ mvCesaFinish(); -+ return MV_NO_RESOURCE; -+ } -+ memset(cesaSramSaBuf.bufVirtPtr, 0, cesaSramSaBuf.bufSize); -+ pSramSA = (MV_CESA_SRAM_SA*)MV_ALIGN_UP((MV_ULONG)cesaSramSaBuf.bufVirtPtr, -+ CPU_D_CACHE_LINE_SIZE); -+ for(i=0; i= 3) -+ cesaChainLength = MAX_CESA_CHAIN_LENGTH; -+#endif -+ /* pSramBase must be 8 byte aligned */ -+ if( MV_IS_NOT_ALIGN((MV_ULONG)pSramBase, 8) ) -+ { -+ mvOsPrintf("mvCesaInit: pSramBase (%p) must be 8 byte aligned\n", -+ pSramBase); -+ mvCesaFinish(); -+ return MV_NOT_ALIGNED; -+ } -+ cesaSramVirtPtr = (MV_CESA_SRAM_MAP*)pSramBase; -+ -+ cesaCryptEngBase = cryptEngBase; -+ -+ /*memset(cesaSramVirtPtr, 0, sizeof(MV_CESA_SRAM_MAP));*/ -+ -+ /* Clear registers */ -+ MV_REG_WRITE( MV_CESA_CFG_REG, 0); -+ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); -+ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, 0); -+ -+ /* Initialize DMA descriptor lists for all requests in Request queue */ -+ descOffsetReg = configReg = 0; -+ for(req=0; reqcesaDescBuf.bufSize = sizeof(MV_CESA_DESC)*MV_CESA_MAX_REQ_FRAGS + -+ CPU_D_CACHE_LINE_SIZE; -+ -+ pReq->cesaDescBuf.bufVirtPtr = -+ mvOsIoCachedMalloc(osHandle,pReq->cesaDescBuf.bufSize, -+ &pReq->cesaDescBuf.bufPhysAddr, -+ &pReq->cesaDescBuf.memHandle); -+ -+ if(pReq->cesaDescBuf.bufVirtPtr == NULL) -+ { -+ mvOsPrintf("mvCesaInit: req=%d, Can't allocate %d bytes for CESA descriptors\n", -+ req, pReq->cesaDescBuf.bufSize); -+ mvCesaFinish(); -+ return MV_NO_RESOURCE; -+ } -+ memset(pReq->cesaDescBuf.bufVirtPtr, 0, pReq->cesaDescBuf.bufSize); -+ pReq->pCesaDesc = (MV_CESA_DESC*)MV_ALIGN_UP((MV_ULONG)pReq->cesaDescBuf.bufVirtPtr, -+ CPU_D_CACHE_LINE_SIZE); -+ -+ pReq->dmaDescBuf.bufSize = sizeof(MV_DMA_DESC)*MV_CESA_MAX_DMA_DESC*MV_CESA_MAX_REQ_FRAGS + -+ CPU_D_CACHE_LINE_SIZE; -+ -+ pReq->dmaDescBuf.bufVirtPtr = -+ mvOsIoCachedMalloc(osHandle,pReq->dmaDescBuf.bufSize, -+ &pReq->dmaDescBuf.bufPhysAddr, -+ &pReq->dmaDescBuf.memHandle); -+ -+ if(pReq->dmaDescBuf.bufVirtPtr == NULL) -+ { -+ mvOsPrintf("mvCesaInit: req=%d, Can't allocate %d bytes for DMA descriptor list\n", -+ req, pReq->dmaDescBuf.bufSize); -+ mvCesaFinish(); -+ return MV_NO_RESOURCE; -+ } -+ memset(pReq->dmaDescBuf.bufVirtPtr, 0, pReq->dmaDescBuf.bufSize); -+ pDmaDesc = (MV_DMA_DESC*)MV_ALIGN_UP((MV_ULONG)pReq->dmaDescBuf.bufVirtPtr, -+ CPU_D_CACHE_LINE_SIZE); -+ -+ for(frag=0; fragdma[frag]; -+ -+ pDma->pDmaFirst = pDmaDesc; -+ pDma->pDmaLast = NULL; -+ -+ for(i=0; ipDmaFirst[i].phyNextDescPtr = -+ MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, &pDmaDesc[i+1])); -+ } -+ pDma->pDmaFirst[i].phyNextDescPtr = 0; -+ mvOsCacheFlush(NULL, &pDma->pDmaFirst[0], MV_CESA_MAX_DMA_DESC*sizeof(MV_DMA_DESC)); -+ -+ pDmaDesc += MV_CESA_MAX_DMA_DESC; -+ } -+ } -+ /*mvCesaCryptoIvSet(NULL, MV_CESA_MAX_IV_LENGTH);*/ -+ descOffsetReg = (MV_U16)((MV_U8*)&cesaSramVirtPtr->desc - mvCesaSramAddrGet()); -+ MV_REG_WRITE(MV_CESA_CHAN_DESC_OFFSET_REG, descOffsetReg); -+ -+ configReg |= (MV_CESA_CFG_WAIT_DMA_MASK | MV_CESA_CFG_ACT_DMA_MASK); -+#if (MV_CESA_VERSION >= 3) -+ configReg |= MV_CESA_CFG_CHAIN_MODE_MASK; -+#endif -+ -+#if (MV_CESA_VERSION >= 2) -+ /* Initialize TDMA engine */ -+ MV_REG_WRITE(MV_CESA_TDMA_CTRL_REG, MV_CESA_TDMA_CTRL_VALUE); -+ MV_REG_WRITE(MV_CESA_TDMA_BYTE_COUNT_REG, 0); -+ MV_REG_WRITE(MV_CESA_TDMA_CURR_DESC_PTR_REG, 0); -+#else -+ /* Initialize IDMA #0 engine */ -+ MV_REG_WRITE(IDMA_CTRL_LOW_REG(0), 0); -+ MV_REG_WRITE(IDMA_BYTE_COUNT_REG(0), 0); -+ MV_REG_WRITE(IDMA_CURR_DESC_PTR_REG(0), 0); -+ MV_REG_WRITE(IDMA_CTRL_HIGH_REG(0), ICCHR_ENDIAN_LITTLE -+#ifdef MV_CPU_LE -+ | ICCHR_DESC_BYTE_SWAP_EN -+#endif -+ ); -+ /* Clear Cause Byte of IDMA channel to be used */ -+ MV_REG_WRITE( IDMA_CAUSE_REG, ~ICICR_CAUSE_MASK_ALL(0)); -+ MV_REG_WRITE(IDMA_CTRL_LOW_REG(0), MV_CESA_IDMA_CTRL_LOW_VALUE); -+#endif /* (MV_CESA_VERSION >= 2) */ -+ -+ /* Set CESA configuration registers */ -+ MV_REG_WRITE( MV_CESA_CFG_REG, configReg); -+ mvCesaDebugStatsClear(); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaFinish - Shutdown the CESA driver -+* -+* DESCRIPTION: -+* This function shutdown the CESA driver and free all allocted resources. -+* -+* INPUT: None -+* -+* RETURN: -+* MV_OK - Success -+* Other - Fail -+* -+*******************************************************************************/ -+MV_STATUS mvCesaFinish (void) -+{ -+ int req; -+ MV_CESA_REQ* pReq; -+ -+ mvOsPrintf("mvCesaFinish: \n"); -+ -+ cesaSramVirtPtr = NULL; -+ -+ /* Free all resources: DMA list, etc. */ -+ for(req=0; reqdmaDescBuf.bufVirtPtr != NULL) -+ { -+ mvOsIoCachedFree(cesaOsHandle,pReq->dmaDescBuf.bufSize, -+ pReq->dmaDescBuf.bufPhysAddr, -+ pReq->dmaDescBuf.bufVirtPtr, -+ pReq->dmaDescBuf.memHandle); -+ } -+ if(pReq->cesaDescBuf.bufVirtPtr != NULL) -+ { -+ mvOsIoCachedFree(cesaOsHandle,pReq->cesaDescBuf.bufSize, -+ pReq->cesaDescBuf.bufPhysAddr, -+ pReq->cesaDescBuf.bufVirtPtr, -+ pReq->cesaDescBuf.memHandle); -+ } -+ } -+#if (MV_CESA_VERSION < 2) -+ MV_REG_WRITE(IDMA_CTRL_LOW_REG(0), 0); -+#endif /* (MV_CESA_VERSION < 2) */ -+ -+ /* Free request queue */ -+ if(pCesaReqFirst != NULL) -+ { -+ mvOsFree(pCesaReqFirst); -+ pCesaReqFirst = pCesaReqLast = NULL; -+ pCesaReqEmpty = pCesaReqProcess = NULL; -+ cesaQueueDepth = cesaReqResources = 0; -+ } -+ /* Free SA database */ -+ if(pCesaSAD != NULL) -+ { -+ mvOsFree(pCesaSAD); -+ pCesaSAD = NULL; -+ cesaMaxSA = 0; -+ } -+ MV_REG_WRITE( MV_CESA_CFG_REG, 0); -+ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); -+ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, 0); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaCryptoIvSet - Set IV value for Crypto algorithm working in CBC mode -+* -+* DESCRIPTION: -+* This function set IV value using by Crypto algorithms in CBC mode. -+* Each channel has its own IV value. -+* This function gets IV value from the caller. If no IV value passed from -+* the caller or only part of IV passed, the function will init the rest part -+* of IV value (or the whole IV) by random value. -+* -+* INPUT: -+* MV_U8* pIV - Pointer to IV value supplied by user. If pIV==NULL -+* the function will generate random IV value. -+* int ivSize - size (in bytes) of IV provided by user. If ivSize is -+* smaller than maximum IV size, the function will complete -+* IV by random value. -+* -+* RETURN: -+* MV_OK - Success -+* Other - Fail -+* -+*******************************************************************************/ -+MV_STATUS mvCesaCryptoIvSet(MV_U8* pIV, int ivSize) -+{ -+ MV_U8* pSramIV; -+#if defined(MV646xx) -+ mvOsPrintf("mvCesaCryptoIvSet: ERR. shouldn't use this call on MV64660\n"); -+#endif -+ pSramIV = cesaSramVirtPtr->cryptoIV; -+ if(ivSize > MV_CESA_MAX_IV_LENGTH) -+ { -+ mvOsPrintf("mvCesaCryptoIvSet: ivSize (%d) is too large\n", ivSize); -+ ivSize = MV_CESA_MAX_IV_LENGTH; -+ } -+ if(pIV != NULL) -+ { -+ memcpy(pSramIV, pIV, ivSize); -+ ivSize = MV_CESA_MAX_IV_LENGTH - ivSize; -+ pSramIV += ivSize; -+ } -+ -+ while(ivSize > 0) -+ { -+ int size, mv_random = mvOsRand(); -+ -+ size = MV_MIN(ivSize, sizeof(mv_random)); -+ memcpy(pSramIV, (void*)&mv_random, size); -+ -+ pSramIV += size; -+ ivSize -= size; -+ } -+/* -+ mvOsCacheFlush(NULL, cesaSramVirtPtr->cryptoIV, -+ MV_CESA_MAX_IV_LENGTH); -+ mvOsCacheInvalidate(NULL, cesaSramVirtPtr->cryptoIV, -+ MV_CESA_MAX_IV_LENGTH); -+*/ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaSessionOpen - Open new uni-directional crypto session -+* -+* DESCRIPTION: -+* This function open new session. -+* -+* INPUT: -+* MV_CESA_OPEN_SESSION *pSession - pointer to new session input parameters -+* -+* OUTPUT: -+* short *pSid - session ID, should be used for all future -+* requests over this session. -+* -+* RETURN: -+* MV_OK - Session opend successfully. -+* MV_FULL - All sessions are in use, no free place in -+* SA database. -+* MV_BAD_PARAM - One of session input parameters is invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvCesaSessionOpen(MV_CESA_OPEN_SESSION *pSession, short* pSid) -+{ -+ short sid; -+ MV_U32 config = 0; -+ int digestSize; -+ -+ cesaStats.openedCount++; -+ -+ /* Find free entry in SAD */ -+ for(sid=0; sidoperation >= MV_CESA_MAX_OPERATION) -+ { -+ mvOsPrintf("mvCesaSessionOpen: Unexpected operation %d\n", -+ pSession->operation); -+ return MV_BAD_PARAM; -+ } -+ config |= (pSession->operation << MV_CESA_OPERATION_OFFSET); -+ -+ if( (pSession->direction != MV_CESA_DIR_ENCODE) && -+ (pSession->direction != MV_CESA_DIR_DECODE) ) -+ { -+ mvOsPrintf("mvCesaSessionOpen: Unexpected direction %d\n", -+ pSession->direction); -+ return MV_BAD_PARAM; -+ } -+ config |= (pSession->direction << MV_CESA_DIRECTION_BIT); -+ /* Clear SA entry */ -+ /* memset(&pCesaSAD[sid], 0, sizeof(pCesaSAD[sid])); */ -+ -+ /* Check AUTH parameters and update SA entry */ -+ if(pSession->operation != MV_CESA_CRYPTO_ONLY) -+ { -+ /* For HMAC (MD5 and SHA1) - Maximum Key size is 64 bytes */ -+ if( (pSession->macMode == MV_CESA_MAC_HMAC_MD5) || -+ (pSession->macMode == MV_CESA_MAC_HMAC_SHA1) ) -+ { -+ if(pSession->macKeyLength > MV_CESA_MAX_MAC_KEY_LENGTH) -+ { -+ mvOsPrintf("mvCesaSessionOpen: macKeyLength %d is too large\n", -+ pSession->macKeyLength); -+ return MV_BAD_PARAM; -+ } -+ mvCesaHmacIvGet(pSession->macMode, pSession->macKey, pSession->macKeyLength, -+ pCesaSAD[sid].pSramSA->macInnerIV, -+ pCesaSAD[sid].pSramSA->macOuterIV); -+ pCesaSAD[sid].macKeyLength = pSession->macKeyLength; -+ } -+ switch(pSession->macMode) -+ { -+ case MV_CESA_MAC_MD5: -+ case MV_CESA_MAC_HMAC_MD5: -+ digestSize = MV_CESA_MD5_DIGEST_SIZE; -+ break; -+ -+ case MV_CESA_MAC_SHA1: -+ case MV_CESA_MAC_HMAC_SHA1: -+ digestSize = MV_CESA_SHA1_DIGEST_SIZE; -+ break; -+ -+ default: -+ mvOsPrintf("mvCesaSessionOpen: Unexpected macMode %d\n", -+ pSession->macMode); -+ return MV_BAD_PARAM; -+ } -+ config |= (pSession->macMode << MV_CESA_MAC_MODE_OFFSET); -+ -+ /* Supported digest sizes: MD5 - 16 bytes (128 bits), */ -+ /* SHA1 - 20 bytes (160 bits) or 12 bytes (96 bits) for both */ -+ if( (pSession->digestSize != digestSize) && (pSession->digestSize != 12)) -+ { -+ mvOsPrintf("mvCesaSessionOpen: Unexpected digest size %d\n", -+ pSession->digestSize); -+ mvOsPrintf("\t Valid values [bytes]: MD5-16, SHA1-20, Both-12\n"); -+ return MV_BAD_PARAM; -+ } -+ pCesaSAD[sid].digestSize = pSession->digestSize; -+ -+ if(pCesaSAD[sid].digestSize == 12) -+ { -+ /* Set MV_CESA_MAC_DIGEST_SIZE_BIT if digest size is 96 bits */ -+ config |= (MV_CESA_MAC_DIGEST_96B << MV_CESA_MAC_DIGEST_SIZE_BIT); -+ } -+ } -+ -+ /* Check CRYPTO parameters and update SA entry */ -+ if(pSession->operation != MV_CESA_MAC_ONLY) -+ { -+ switch(pSession->cryptoAlgorithm) -+ { -+ case MV_CESA_CRYPTO_DES: -+ pCesaSAD[sid].cryptoKeyLength = MV_CESA_DES_KEY_LENGTH; -+ pCesaSAD[sid].cryptoBlockSize = MV_CESA_DES_BLOCK_SIZE; -+ break; -+ -+ case MV_CESA_CRYPTO_3DES: -+ pCesaSAD[sid].cryptoKeyLength = MV_CESA_3DES_KEY_LENGTH; -+ pCesaSAD[sid].cryptoBlockSize = MV_CESA_DES_BLOCK_SIZE; -+ /* Only EDE mode is supported */ -+ config |= (MV_CESA_CRYPTO_3DES_EDE << -+ MV_CESA_CRYPTO_3DES_MODE_BIT); -+ break; -+ -+ case MV_CESA_CRYPTO_AES: -+ switch(pSession->cryptoKeyLength) -+ { -+ case 16: -+ pCesaSAD[sid].cryptoKeyLength = MV_CESA_AES_128_KEY_LENGTH; -+ config |= (MV_CESA_CRYPTO_AES_KEY_128 << -+ MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET); -+ break; -+ -+ case 24: -+ pCesaSAD[sid].cryptoKeyLength = MV_CESA_AES_192_KEY_LENGTH; -+ config |= (MV_CESA_CRYPTO_AES_KEY_192 << -+ MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET); -+ break; -+ -+ case 32: -+ default: -+ pCesaSAD[sid].cryptoKeyLength = MV_CESA_AES_256_KEY_LENGTH; -+ config |= (MV_CESA_CRYPTO_AES_KEY_256 << -+ MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET); -+ break; -+ } -+ pCesaSAD[sid].cryptoBlockSize = MV_CESA_AES_BLOCK_SIZE; -+ break; -+ -+ default: -+ mvOsPrintf("mvCesaSessionOpen: Unexpected cryptoAlgorithm %d\n", -+ pSession->cryptoAlgorithm); -+ return MV_BAD_PARAM; -+ } -+ config |= (pSession->cryptoAlgorithm << MV_CESA_CRYPTO_ALG_OFFSET); -+ -+ if(pSession->cryptoKeyLength != pCesaSAD[sid].cryptoKeyLength) -+ { -+ mvOsPrintf("cesaSessionOpen: Wrong CryptoKeySize %d != %d\n", -+ pSession->cryptoKeyLength, pCesaSAD[sid].cryptoKeyLength); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Copy Crypto key */ -+ if( (pSession->cryptoAlgorithm == MV_CESA_CRYPTO_AES) && -+ (pSession->direction == MV_CESA_DIR_DECODE)) -+ { -+ /* Crypto Key for AES decode is computed from original key material */ -+ /* and depend on cryptoKeyLength (128/192/256 bits) */ -+ aesMakeKey(pCesaSAD[sid].pSramSA->cryptoKey, pSession->cryptoKey, -+ pSession->cryptoKeyLength*8, MV_CESA_AES_BLOCK_SIZE*8); -+ } -+ else -+ { -+ /*panic("mvCesaSessionOpen2");*/ -+ memcpy(pCesaSAD[sid].pSramSA->cryptoKey, pSession->cryptoKey, -+ pCesaSAD[sid].cryptoKeyLength); -+ -+ } -+ -+ switch(pSession->cryptoMode) -+ { -+ case MV_CESA_CRYPTO_ECB: -+ pCesaSAD[sid].cryptoIvSize = 0; -+ break; -+ -+ case MV_CESA_CRYPTO_CBC: -+ pCesaSAD[sid].cryptoIvSize = pCesaSAD[sid].cryptoBlockSize; -+ break; -+ -+ case MV_CESA_CRYPTO_CTR: -+ /* Supported only for AES algorithm */ -+ if(pSession->cryptoAlgorithm != MV_CESA_CRYPTO_AES) -+ { -+ mvOsPrintf("mvCesaSessionOpen: CRYPTO CTR mode supported for AES only\n"); -+ return MV_BAD_PARAM; -+ } -+ pCesaSAD[sid].cryptoIvSize = 0; -+ pCesaSAD[sid].ctrMode = 1; -+ /* Replace to ECB mode for HW */ -+ pSession->cryptoMode = MV_CESA_CRYPTO_ECB; -+ break; -+ -+ default: -+ mvOsPrintf("mvCesaSessionOpen: Unexpected cryptoMode %d\n", -+ pSession->cryptoMode); -+ return MV_BAD_PARAM; -+ } -+ -+ config |= (pSession->cryptoMode << MV_CESA_CRYPTO_MODE_BIT); -+ } -+ pCesaSAD[sid].config = config; -+ -+ mvOsCacheFlush(NULL, pCesaSAD[sid].pSramSA, sizeof(MV_CESA_SRAM_SA)); -+ if(pSid != NULL) -+ *pSid = sid; -+ -+ pCesaSAD[sid].valid = 1; -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaSessionClose - Close active crypto session -+* -+* DESCRIPTION: -+* This function closes existing session -+* -+* INPUT: -+* short sid - Unique identifier of the session to be closed -+* -+* RETURN: -+* MV_OK - Session closed successfully. -+* MV_BAD_PARAM - Session identifier is out of valid range. -+* MV_NOT_FOUND - There is no active session with such ID. -+* -+*******************************************************************************/ -+MV_STATUS mvCesaSessionClose(short sid) -+{ -+ cesaStats.closedCount++; -+ -+ if(sid >= cesaMaxSA) -+ { -+ mvOsPrintf("CESA Error: sid (%d) is too big\n", sid); -+ return MV_BAD_PARAM; -+ } -+ if(pCesaSAD[sid].valid == 0) -+ { -+ mvOsPrintf("CESA Warning: Session (sid=%d) is invalid\n", sid); -+ return MV_NOT_FOUND; -+ } -+ if(cesaLastSid == sid) -+ cesaLastSid = -1; -+ -+ pCesaSAD[sid].valid = 0; -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaAction - Perform crypto operation -+* -+* DESCRIPTION: -+* This function set new CESA request FIFO queue for further HW processing. -+* The function checks request parameters before set new request to the queue. -+* If one of the CESA channels is ready for processing the request will be -+* passed to HW. When request processing is finished the CESA interrupt will -+* be generated by HW. The caller should call mvCesaReadyGet() function to -+* complete request processing and get result. -+* -+* INPUT: -+* MV_CESA_COMMAND *pCmd - pointer to new CESA request. -+* It includes pointers to Source and Destination -+* buffers, session identifier get from -+* mvCesaSessionOpen() function, pointer to caller -+* private data and all needed crypto parameters. -+* -+* RETURN: -+* MV_OK - request successfully added to request queue -+* and will be processed. -+* MV_NO_MORE - request successfully added to request queue and will -+* be processed, but request queue became Full and next -+* request will not be accepted. -+* MV_NO_RESOURCE - request queue is FULL and the request can not -+* be processed. -+* MV_OUT_OF_CPU_MEM - memory allocation needed for request processing is -+* failed. Request can not be processed. -+* MV_NOT_ALLOWED - This mixed request (CRYPTO+MAC) can not be processed -+* as one request and should be splitted for two requests: -+* CRYPTO_ONLY and MAC_ONLY. -+* MV_BAD_PARAM - One of the request parameters is out of valid range. -+* The request can not be processed. -+* -+*******************************************************************************/ -+MV_STATUS mvCesaAction (MV_CESA_COMMAND *pCmd) -+{ -+ MV_STATUS status; -+ MV_CESA_REQ* pReq = pCesaReqEmpty; -+ int sid = pCmd->sessionId; -+ MV_CESA_SA* pSA = &pCesaSAD[sid]; -+#if (MV_CESA_VERSION >= 3) -+ MV_CESA_REQ* pFromReq; -+ MV_CESA_REQ* pToReq; -+#endif -+ cesaStats.reqCount++; -+ -+ /* Check that the request queue is not FULL */ -+ if(cesaReqResources == 0) -+ return MV_NO_RESOURCE; -+ -+ if( (sid >= cesaMaxSA) || (!pSA->valid) ) -+ { -+ mvOsPrintf("CESA Action Error: Session sid=%d is INVALID\n", sid); -+ return MV_BAD_PARAM; -+ } -+ pSA->count++; -+ -+ if(pSA->ctrMode) -+ { -+ /* AES in CTR mode can't be mixed with Authentication */ -+ if( (pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ mvOsPrintf("mvCesaAction : CRYPTO CTR mode can't be mixed with AUTH\n"); -+ return MV_NOT_ALLOWED; -+ } -+ /* All other request parameters should not be checked because key stream */ -+ /* (not user data) processed by AES HW engine */ -+ pReq->pOrgCmd = pCmd; -+ /* Allocate temporary pCmd structure for Key stream */ -+ pCmd = mvCesaCtrModeInit(); -+ if(pCmd == NULL) -+ return MV_OUT_OF_CPU_MEM; -+ -+ /* Prepare Key stream */ -+ mvCesaCtrModePrepare(pCmd, pReq->pOrgCmd); -+ pReq->fixOffset = 0; -+ } -+ else -+ { -+ /* Check request parameters and calculae fixOffset */ -+ status = mvCesaParamCheck(pSA, pCmd, &pReq->fixOffset); -+ if(status != MV_OK) -+ { -+ return status; -+ } -+ } -+ pReq->pCmd = pCmd; -+ -+ /* Check if the packet need fragmentation */ -+ if(pCmd->pSrc->mbufSize <= sizeof(cesaSramVirtPtr->buf) ) -+ { -+ /* request size is smaller than single buffer size */ -+ pReq->fragMode = MV_CESA_FRAG_NONE; -+ -+ /* Prepare NOT fragmented packets */ -+ status = mvCesaReqProcess(pReq); -+ if(status != MV_OK) -+ { -+ mvOsPrintf("CesaReady: ReqProcess error: pReq=%p, status=0x%x\n", -+ pReq, status); -+ } -+#if (MV_CESA_VERSION >= 3) -+ pReq->frags.numFrag = 1; -+#endif -+ } -+ else -+ { -+ MV_U8 frag = 0; -+ -+ /* request size is larger than buffer size - needs fragmentation */ -+ -+ /* Check restrictions for processing fragmented packets */ -+ status = mvCesaFragParamCheck(pSA, pCmd); -+ if(status != MV_OK) -+ return status; -+ -+ pReq->fragMode = MV_CESA_FRAG_FIRST; -+ pReq->frags.nextFrag = 0; -+ -+ /* Prepare Process Fragmented packets */ -+ while(pReq->fragMode != MV_CESA_FRAG_LAST) -+ { -+ if(frag >= MV_CESA_MAX_REQ_FRAGS) -+ { -+ mvOsPrintf("mvCesaAction Error: Too large request frag=%d\n", frag); -+ return MV_OUT_OF_CPU_MEM; -+ } -+ status = mvCesaFragReqProcess(pReq, frag); -+ if(status == MV_OK) { -+#if (MV_CESA_VERSION >= 3) -+ if(frag) { -+ pReq->dma[frag-1].pDmaLast->phyNextDescPtr = -+ MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, pReq->dma[frag].pDmaFirst)); -+ mvOsCacheFlush(NULL, pReq->dma[frag-1].pDmaLast, sizeof(MV_DMA_DESC)); -+ } -+#endif -+ frag++; -+ } -+ } -+ pReq->frags.numFrag = frag; -+#if (MV_CESA_VERSION >= 3) -+ if(chainReqNum) { -+ chainReqNum += pReq->frags.numFrag; -+ if(chainReqNum >= MAX_CESA_CHAIN_LENGTH) -+ chainReqNum = MAX_CESA_CHAIN_LENGTH; -+ } -+#endif -+ } -+ -+ pReq->state = MV_CESA_PENDING; -+ -+ pCesaReqEmpty = MV_CESA_REQ_NEXT_PTR(pReq); -+ cesaReqResources -= 1; -+ -+/* #ifdef CESA_DEBUG */ -+ if( (cesaQueueDepth - cesaReqResources) > cesaStats.maxReqCount) -+ cesaStats.maxReqCount = (cesaQueueDepth - cesaReqResources); -+/* #endif CESA_DEBUG */ -+ -+ cesaLastSid = sid; -+ -+#if (MV_CESA_VERSION >= 3) -+ /* Are we within chain bounderies and follows the first request ? */ -+ if((chainReqNum > 0) && (chainReqNum < MAX_CESA_CHAIN_LENGTH)) { -+ if(chainIndex) { -+ pFromReq = MV_CESA_REQ_PREV_PTR(pReq); -+ pToReq = pReq; -+ pReq->state = MV_CESA_CHAIN; -+ /* assume concatenating is possible */ -+ pFromReq->dma[pFromReq->frags.numFrag-1].pDmaLast->phyNextDescPtr = -+ MV_32BIT_LE(mvCesaVirtToPhys(&pToReq->dmaDescBuf, pToReq->dma[0].pDmaFirst)); -+ mvOsCacheFlush(NULL, pFromReq->dma[pFromReq->frags.numFrag-1].pDmaLast, sizeof(MV_DMA_DESC)); -+ -+ /* align active & next pointers */ -+ if(pNextActiveChain->state != MV_CESA_PENDING) -+ pEndCurrChain = pNextActiveChain = MV_CESA_REQ_NEXT_PTR(pReq); -+ } -+ else { /* we have only one chain, start new one */ -+ chainReqNum = 0; -+ chainIndex++; -+ /* align active & next pointers */ -+ if(pNextActiveChain->state != MV_CESA_PENDING) -+ pEndCurrChain = pNextActiveChain = pReq; -+ } -+ } -+ else { -+ /* In case we concatenate full chain */ -+ if(chainReqNum == MAX_CESA_CHAIN_LENGTH) { -+ chainIndex++; -+ if(pNextActiveChain->state != MV_CESA_PENDING) -+ pEndCurrChain = pNextActiveChain = pReq; -+ chainReqNum = 0; -+ } -+ -+ pReq = pCesaReqProcess; -+ if(pReq->state == MV_CESA_PENDING) { -+ pNextActiveChain = pReq; -+ pEndCurrChain = MV_CESA_REQ_NEXT_PTR(pReq); -+ /* Start Process new request */ -+ mvCesaReqProcessStart(pReq); -+ } -+ } -+ -+ chainReqNum++; -+ -+ if((chainIndex < MAX_CESA_CHAIN_LENGTH) && (chainReqNum > cesaStats.maxChainUsage)) -+ cesaStats.maxChainUsage = chainReqNum; -+ -+#else -+ -+ /* Check status of CESA channels and process requests if possible */ -+ pReq = pCesaReqProcess; -+ if(pReq->state == MV_CESA_PENDING) -+ { -+ /* Start Process new request */ -+ mvCesaReqProcessStart(pReq); -+ } -+#endif -+ /* If request queue became FULL - return MV_NO_MORE */ -+ if(cesaReqResources == 0) -+ return MV_NO_MORE; -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvCesaReadyGet - Get crypto request that processing is finished -+* -+* DESCRIPTION: -+* This function complete request processing and return ready request to -+* caller. To don't miss interrupts the caller must call this function -+* while MV_OK or MV_TERMINATE values returned. -+* -+* INPUT: -+* MV_U32 chanMap - map of CESA channels finished thier job -+* accordingly with CESA Cause register. -+* MV_CESA_RESULT* pResult - pointer to structure contains information -+* about ready request. It includes pointer to -+* user private structure "pReqPrv", session identifier -+* for this request "sessionId" and return code. -+* Return code set to MV_FAIL if calculated digest value -+* on decode direction is different than digest value -+* in the packet. -+* -+* RETURN: -+* MV_OK - Success, ready request is returned. -+* MV_NOT_READY - Next request is not ready yet. New interrupt will -+* be generated for futher request processing. -+* MV_EMPTY - There is no more request for processing. -+* MV_BUSY - Fragmented request is not ready yet. -+* MV_TERMINATE - Call this function once more to complete processing -+* of fragmented request. -+* -+*******************************************************************************/ -+MV_STATUS mvCesaReadyGet(MV_CESA_RESULT* pResult) -+{ -+ MV_STATUS status, readyStatus = MV_NOT_READY; -+ MV_U32 statusReg; -+ MV_CESA_REQ* pReq; -+ MV_CESA_SA* pSA; -+ -+#if (MV_CESA_VERSION >= 3) -+ if(isFirstReq == MV_TRUE) { -+ if(chainIndex == 0) -+ chainReqNum = 0; -+ -+ isFirstReq = MV_FALSE; -+ -+ if(pNextActiveChain->state == MV_CESA_PENDING) { -+ /* Start request Process */ -+ mvCesaReqProcessStart(pNextActiveChain); -+ pEndCurrChain = pNextActiveChain; -+ if(chainIndex > 0) -+ chainIndex--; -+ /* Update pNextActiveChain to next chain head */ -+ while(pNextActiveChain->state == MV_CESA_CHAIN) -+ pNextActiveChain = MV_CESA_REQ_NEXT_PTR(pNextActiveChain); -+ } -+ } -+ -+ /* Check if there are more processed requests - can we remove pEndCurrChain ??? */ -+ if(pCesaReqProcess == pEndCurrChain) { -+ isFirstReq = MV_TRUE; -+ pEndCurrChain = pNextActiveChain; -+#else -+ if(pCesaReqProcess->state != MV_CESA_PROCESS) { -+#endif -+ return MV_EMPTY; -+ } -+ -+#ifdef CESA_DEBUG -+ statusReg = MV_REG_READ(MV_CESA_STATUS_REG); -+ if( statusReg & MV_CESA_STATUS_ACTIVE_MASK ) -+ { -+ mvOsPrintf("mvCesaReadyGet: Not Ready, Status = 0x%x\n", statusReg); -+ cesaStats.notReadyCount++; -+ return MV_NOT_READY; -+ } -+#endif /* CESA_DEBUG */ -+ -+ cesaStats.readyCount++; -+ -+ pReq = pCesaReqProcess; -+ pSA = &pCesaSAD[pReq->pCmd->sessionId]; -+ -+ pResult->retCode = MV_OK; -+ if(pReq->fragMode != MV_CESA_FRAG_NONE) -+ { -+ MV_U8* pNewDigest; -+ int frag; -+#if (MV_CESA_VERSION >= 3) -+ pReq->frags.nextFrag = 1; -+ while(pReq->frags.nextFrag <= pReq->frags.numFrag) { -+#endif -+ frag = (pReq->frags.nextFrag - 1); -+ -+ /* Restore DMA descriptor list */ -+ pReq->dma[frag].pDmaLast->phyNextDescPtr = -+ MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, &pReq->dma[frag].pDmaLast[1])); -+ pReq->dma[frag].pDmaLast = NULL; -+ -+ /* Special processing for finished fragmented request */ -+ if(pReq->frags.nextFrag >= pReq->frags.numFrag) -+ { -+ mvCesaMbufCacheUnmap(pReq->pCmd->pDst, 0, pReq->pCmd->pDst->mbufSize); -+ -+ /* Fragmented packet is ready */ -+ if( (pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ int macDataSize = pReq->pCmd->macLength - pReq->frags.macSize; -+ -+ if(macDataSize != 0) -+ { -+ /* Calculate all other blocks by SW */ -+ mvCesaFragAuthComplete(pReq, pSA, macDataSize); -+ } -+ -+ /* Copy new digest from SRAM to the Destination buffer */ -+ pNewDigest = cesaSramVirtPtr->buf + pReq->frags.newDigestOffset; -+ status = mvCesaCopyToMbuf(pNewDigest, pReq->pCmd->pDst, -+ pReq->pCmd->digestOffset, pSA->digestSize); -+ -+ /* For decryption: Compare new digest value with original one */ -+ if((pSA->config & MV_CESA_DIRECTION_MASK) == -+ (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) -+ { -+ if( memcmp(pNewDigest, pReq->frags.orgDigest, pSA->digestSize) != 0) -+ { -+/* -+ mvOsPrintf("Digest error: chan=%d, newDigest=%p, orgDigest=%p, status = 0x%x\n", -+ chan, pNewDigest, pReq->frags.orgDigest, MV_REG_READ(MV_CESA_STATUS_REG)); -+*/ -+ /* Signiture verification is failed */ -+ pResult->retCode = MV_FAIL; -+ } -+ } -+ } -+ readyStatus = MV_OK; -+ } -+#if (MV_CESA_VERSION >= 3) -+ pReq->frags.nextFrag++; -+ } -+#endif -+ } -+ else -+ { -+ mvCesaMbufCacheUnmap(pReq->pCmd->pDst, 0, pReq->pCmd->pDst->mbufSize); -+ -+ /* Restore DMA descriptor list */ -+ pReq->dma[0].pDmaLast->phyNextDescPtr = -+ MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, &pReq->dma[0].pDmaLast[1])); -+ pReq->dma[0].pDmaLast = NULL; -+ if( ((pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) && -+ ((pSA->config & MV_CESA_DIRECTION_MASK) == -+ (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) ) -+ { -+ /* For AUTH on decode : Check Digest result in Status register */ -+ statusReg = MV_REG_READ(MV_CESA_STATUS_REG); -+ if(statusReg & MV_CESA_STATUS_DIGEST_ERR_MASK) -+ { -+/* -+ mvOsPrintf("Digest error: chan=%d, status = 0x%x\n", -+ chan, statusReg); -+*/ -+ /* Signiture verification is failed */ -+ pResult->retCode = MV_FAIL; -+ } -+ } -+ readyStatus = MV_OK; -+ } -+ -+ if(readyStatus == MV_OK) -+ { -+ /* If Request is ready - Prepare pResult structure */ -+ pResult->pReqPrv = pReq->pCmd->pReqPrv; -+ pResult->sessionId = pReq->pCmd->sessionId; -+ -+ pReq->state = MV_CESA_IDLE; -+ pCesaReqProcess = MV_CESA_REQ_NEXT_PTR(pReq); -+ cesaReqResources++; -+ -+ if(pSA->ctrMode) -+ { -+ /* For AES CTR mode - complete processing and free allocated resources */ -+ mvCesaCtrModeComplete(pReq->pOrgCmd, pReq->pCmd); -+ mvCesaCtrModeFinish(pReq->pCmd); -+ pReq->pOrgCmd = NULL; -+ } -+ } -+ -+#if (MV_CESA_VERSION < 3) -+ if(pCesaReqProcess->state == MV_CESA_PROCESS) -+ { -+ /* Start request Process */ -+ mvCesaReqProcessStart(pCesaReqProcess); -+ if(readyStatus == MV_NOT_READY) -+ readyStatus = MV_BUSY; -+ } -+ else if(pCesaReqProcess != pCesaReqEmpty) -+ { -+ /* Start process new request from the queue */ -+ mvCesaReqProcessStart(pCesaReqProcess); -+ } -+#endif -+ return readyStatus; -+} -+ -+/***************** Functions to work with CESA_MBUF structure ******************/ -+ -+/******************************************************************************* -+* mvCesaMbufOffset - Locate offset in the Mbuf structure -+* -+* DESCRIPTION: -+* This function locates offset inside Multi-Bufeer structure. -+* It get fragment number and place in the fragment where the offset -+* is located. -+* -+* -+* INPUT: -+* MV_CESA_MBUF* pMbuf - Pointer to multi-buffer structure -+* int offset - Offset from the beginning of the data presented by -+* the Mbuf structure. -+* -+* OUTPUT: -+* int* pBufOffset - Offset from the beginning of the fragment where -+* the offset is located. -+* -+* RETURN: -+* int - Number of fragment, where the offset is located\ -+* -+*******************************************************************************/ -+int mvCesaMbufOffset(MV_CESA_MBUF* pMbuf, int offset, int* pBufOffset) -+{ -+ int frag = 0; -+ -+ while(offset > 0) -+ { -+ if(frag >= pMbuf->numFrags) -+ { -+ mvOsPrintf("mvCesaMbufOffset: Error: frag (%d) > numFrags (%d)\n", -+ frag, pMbuf->numFrags); -+ return MV_INVALID; -+ } -+ if(offset < pMbuf->pFrags[frag].bufSize) -+ { -+ break; -+ } -+ offset -= pMbuf->pFrags[frag].bufSize; -+ frag++; -+ } -+ if(pBufOffset != NULL) -+ *pBufOffset = offset; -+ -+ return frag; -+} -+ -+/******************************************************************************* -+* mvCesaCopyFromMbuf - Copy data from the Mbuf structure to continuous buffer -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_U8* pDstBuf - Pointer to continuous buffer, where data is -+* copied to. -+* MV_CESA_MBUF* pSrcMbuf - Pointer to multi-buffer structure where data is -+* copied from. -+* int offset - Offset in the Mbuf structure where located first -+* byte of data should be copied. -+* int size - Size of data should be copied -+* -+* RETURN: -+* MV_OK - Success, all data is copied successfully. -+* MV_OUT_OF_RANGE - Failed, offset is out of Multi-buffer data range. -+* No data is copied. -+* MV_EMPTY - Multi-buffer structure has not enough data to copy -+* Data from the offset to end of Mbuf data is copied. -+* -+*******************************************************************************/ -+MV_STATUS mvCesaCopyFromMbuf(MV_U8* pDstBuf, MV_CESA_MBUF* pSrcMbuf, -+ int offset, int size) -+{ -+ int frag, fragOffset, bufSize; -+ MV_U8* pBuf; -+ -+ if(size == 0) -+ return MV_OK; -+ -+ frag = mvCesaMbufOffset(pSrcMbuf, offset, &fragOffset); -+ if(frag == MV_INVALID) -+ { -+ mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); -+ return MV_OUT_OF_RANGE; -+ } -+ -+ bufSize = pSrcMbuf->pFrags[frag].bufSize - fragOffset; -+ pBuf = pSrcMbuf->pFrags[frag].bufVirtPtr + fragOffset; -+ while(MV_TRUE) -+ { -+ if(size <= bufSize) -+ { -+ memcpy(pDstBuf, pBuf, size); -+ return MV_OK; -+ } -+ memcpy(pDstBuf, pBuf, bufSize); -+ size -= bufSize; -+ frag++; -+ pDstBuf += bufSize; -+ if(frag >= pSrcMbuf->numFrags) -+ break; -+ -+ bufSize = pSrcMbuf->pFrags[frag].bufSize; -+ pBuf = pSrcMbuf->pFrags[frag].bufVirtPtr; -+ } -+ mvOsPrintf("mvCesaCopyFromMbuf: Mbuf is EMPTY - %d bytes isn't copied\n", -+ size); -+ return MV_EMPTY; -+} -+ -+/******************************************************************************* -+* mvCesaCopyToMbuf - Copy data from continuous buffer to the Mbuf structure -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_U8* pSrcBuf - Pointer to continuous buffer, where data is -+* copied from. -+* MV_CESA_MBUF* pDstMbuf - Pointer to multi-buffer structure where data is -+* copied to. -+* int offset - Offset in the Mbuf structure where located first -+* byte of data should be copied. -+* int size - Size of data should be copied -+* -+* RETURN: -+* MV_OK - Success, all data is copied successfully. -+* MV_OUT_OF_RANGE - Failed, offset is out of Multi-buffer data range. -+* No data is copied. -+* MV_FULL - Multi-buffer structure has not enough place to copy -+* all data. Data from the offset to end of Mbuf data -+* is copied. -+* -+*******************************************************************************/ -+MV_STATUS mvCesaCopyToMbuf(MV_U8* pSrcBuf, MV_CESA_MBUF* pDstMbuf, -+ int offset, int size) -+{ -+ int frag, fragOffset, bufSize; -+ MV_U8* pBuf; -+ -+ if(size == 0) -+ return MV_OK; -+ -+ frag = mvCesaMbufOffset(pDstMbuf, offset, &fragOffset); -+ if(frag == MV_INVALID) -+ { -+ mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); -+ return MV_OUT_OF_RANGE; -+ } -+ -+ bufSize = pDstMbuf->pFrags[frag].bufSize - fragOffset; -+ pBuf = pDstMbuf->pFrags[frag].bufVirtPtr + fragOffset; -+ while(MV_TRUE) -+ { -+ if(size <= bufSize) -+ { -+ memcpy(pBuf, pSrcBuf, size); -+ return MV_OK; -+ } -+ memcpy(pBuf, pSrcBuf, bufSize); -+ size -= bufSize; -+ frag++; -+ pSrcBuf += bufSize; -+ if(frag >= pDstMbuf->numFrags) -+ break; -+ -+ bufSize = pDstMbuf->pFrags[frag].bufSize; -+ pBuf = pDstMbuf->pFrags[frag].bufVirtPtr; -+ } -+ mvOsPrintf("mvCesaCopyToMbuf: Mbuf is FULL - %d bytes isn't copied\n", -+ size); -+ return MV_FULL; -+} -+ -+/******************************************************************************* -+* mvCesaMbufCopy - Copy data from one Mbuf structure to the other Mbuf structure -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* -+* MV_CESA_MBUF* pDstMbuf - Pointer to multi-buffer structure where data is -+* copied to. -+* int dstMbufOffset - Offset in the dstMbuf structure where first byte -+* of data should be copied to. -+* MV_CESA_MBUF* pSrcMbuf - Pointer to multi-buffer structure where data is -+* copied from. -+* int srcMbufOffset - Offset in the srcMbuf structure where first byte -+* of data should be copied from. -+* int size - Size of data should be copied -+* -+* RETURN: -+* MV_OK - Success, all data is copied successfully. -+* MV_OUT_OF_RANGE - Failed, srcMbufOffset or dstMbufOffset is out of -+* srcMbuf or dstMbuf structure correspondently. -+* No data is copied. -+* MV_BAD_SIZE - srcMbuf or dstMbuf structure is too small to copy -+* all data. Partial data is copied -+* -+*******************************************************************************/ -+MV_STATUS mvCesaMbufCopy(MV_CESA_MBUF* pMbufDst, int dstMbufOffset, -+ MV_CESA_MBUF* pMbufSrc, int srcMbufOffset, int size) -+{ -+ int srcFrag, dstFrag, srcSize, dstSize, srcOffset, dstOffset; -+ int copySize; -+ MV_U8 *pSrc, *pDst; -+ -+ if(size == 0) -+ return MV_OK; -+ -+ srcFrag = mvCesaMbufOffset(pMbufSrc, srcMbufOffset, &srcOffset); -+ if(srcFrag == MV_INVALID) -+ { -+ mvOsPrintf("CESA srcMbuf Error: offset (%d) out of range\n", srcMbufOffset); -+ return MV_OUT_OF_RANGE; -+ } -+ pSrc = pMbufSrc->pFrags[srcFrag].bufVirtPtr + srcOffset; -+ srcSize = pMbufSrc->pFrags[srcFrag].bufSize - srcOffset; -+ -+ dstFrag = mvCesaMbufOffset(pMbufDst, dstMbufOffset, &dstOffset); -+ if(dstFrag == MV_INVALID) -+ { -+ mvOsPrintf("CESA dstMbuf Error: offset (%d) out of range\n", dstMbufOffset); -+ return MV_OUT_OF_RANGE; -+ } -+ pDst = pMbufDst->pFrags[dstFrag].bufVirtPtr + dstOffset; -+ dstSize = pMbufDst->pFrags[dstFrag].bufSize - dstOffset; -+ -+ while(size > 0) -+ { -+ copySize = MV_MIN(srcSize, dstSize); -+ if(size <= copySize) -+ { -+ memcpy(pDst, pSrc, size); -+ return MV_OK; -+ } -+ memcpy(pDst, pSrc, copySize); -+ size -= copySize; -+ srcSize -= copySize; -+ dstSize -= copySize; -+ -+ if(srcSize == 0) -+ { -+ srcFrag++; -+ if(srcFrag >= pMbufSrc->numFrags) -+ break; -+ -+ pSrc = pMbufSrc->pFrags[srcFrag].bufVirtPtr; -+ srcSize = pMbufSrc->pFrags[srcFrag].bufSize; -+ } -+ -+ if(dstSize == 0) -+ { -+ dstFrag++; -+ if(dstFrag >= pMbufDst->numFrags) -+ break; -+ -+ pDst = pMbufDst->pFrags[dstFrag].bufVirtPtr; -+ dstSize = pMbufDst->pFrags[dstFrag].bufSize; -+ } -+ } -+ mvOsPrintf("mvCesaMbufCopy: BAD size - %d bytes isn't copied\n", -+ size); -+ -+ return MV_BAD_SIZE; -+} -+ -+static MV_STATUS mvCesaMbufCacheUnmap(MV_CESA_MBUF* pMbuf, int offset, int size) -+{ -+ int frag, fragOffset, bufSize; -+ MV_U8* pBuf; -+ -+ if(size == 0) -+ return MV_OK; -+ -+ frag = mvCesaMbufOffset(pMbuf, offset, &fragOffset); -+ if(frag == MV_INVALID) -+ { -+ mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); -+ return MV_OUT_OF_RANGE; -+ } -+ -+ bufSize = pMbuf->pFrags[frag].bufSize - fragOffset; -+ pBuf = pMbuf->pFrags[frag].bufVirtPtr + fragOffset; -+ while(MV_TRUE) -+ { -+ if(size <= bufSize) -+ { -+ mvOsCacheUnmap(NULL, mvOsIoVirtToPhy(NULL, pBuf), size); -+ return MV_OK; -+ } -+ -+ mvOsCacheUnmap(NULL, mvOsIoVirtToPhy(NULL, pBuf), bufSize); -+ size -= bufSize; -+ frag++; -+ if(frag >= pMbuf->numFrags) -+ break; -+ -+ bufSize = pMbuf->pFrags[frag].bufSize; -+ pBuf = pMbuf->pFrags[frag].bufVirtPtr; -+ } -+ mvOsPrintf("%s: Mbuf is FULL - %d bytes isn't Unmapped\n", -+ __FUNCTION__, size); -+ return MV_FULL; -+} -+ -+ -+/*************************************** Local Functions ******************************/ -+ -+/******************************************************************************* -+* mvCesaFragReqProcess - Process fragmented request -+* -+* DESCRIPTION: -+* This function processes a fragment of fragmented request (First, Middle or Last) -+* -+* -+* INPUT: -+* MV_CESA_REQ* pReq - Pointer to the request in the request queue. -+* -+* RETURN: -+* MV_OK - The fragment is successfully passed to HW for processing. -+* MV_TERMINATE - Means, that HW finished its work on this packet and no more -+* interrupts will be generated for this request. -+* Function mvCesaReadyGet() must be called to complete request -+* processing and get request result. -+* -+*******************************************************************************/ -+static MV_STATUS mvCesaFragReqProcess(MV_CESA_REQ* pReq, MV_U8 frag) -+{ -+ int i, copySize, cryptoDataSize, macDataSize, sid; -+ int cryptoIvOffset, digestOffset; -+ MV_U32 config; -+ MV_CESA_COMMAND* pCmd = pReq->pCmd; -+ MV_CESA_SA* pSA; -+ MV_CESA_MBUF* pMbuf; -+ MV_DMA_DESC* pDmaDesc = pReq->dma[frag].pDmaFirst; -+ MV_U8* pSramBuf = cesaSramVirtPtr->buf; -+ int macTotalLen = 0; -+ int fixOffset, cryptoOffset, macOffset; -+ -+ cesaStats.fragCount++; -+ -+ sid = pReq->pCmd->sessionId; -+ -+ pSA = &pCesaSAD[sid]; -+ -+ cryptoIvOffset = digestOffset = 0; -+ i = macDataSize = 0; -+ cryptoDataSize = 0; -+ -+ /* First fragment processing */ -+ if(pReq->fragMode == MV_CESA_FRAG_FIRST) -+ { -+ /* pReq->frags monitors processing of fragmented request between fragments */ -+ pReq->frags.bufOffset = 0; -+ pReq->frags.cryptoSize = 0; -+ pReq->frags.macSize = 0; -+ -+ config = pSA->config | (MV_CESA_FRAG_FIRST << MV_CESA_FRAG_MODE_OFFSET); -+ -+ /* fixOffset can be not equal to zero only for FIRST fragment */ -+ fixOffset = pReq->fixOffset; -+ /* For FIRST fragment crypto and mac offsets are taken from pCmd */ -+ cryptoOffset = pCmd->cryptoOffset; -+ macOffset = pCmd->macOffset; -+ -+ copySize = sizeof(cesaSramVirtPtr->buf) - pReq->fixOffset; -+ -+ /* Find fragment size: Must meet all requirements for CRYPTO and MAC -+ * cryptoDataSize - size of data will be encrypted/decrypted in this fragment -+ * macDataSize - size of data will be signed/verified in this fragment -+ * copySize - size of data will be copied from srcMbuf to SRAM and -+ * back to dstMbuf for this fragment -+ */ -+ mvCesaFragSizeFind(pSA, pReq, cryptoOffset, macOffset, -+ ©Size, &cryptoDataSize, &macDataSize); -+ -+ if( (pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) -+ { -+ /* CryptoIV special processing */ -+ if( (pSA->config & MV_CESA_CRYPTO_MODE_MASK) == -+ (MV_CESA_CRYPTO_CBC << MV_CESA_CRYPTO_MODE_BIT) ) -+ { -+ /* In CBC mode for encode direction when IV from user */ -+ if( (pCmd->ivFromUser) && -+ ((pSA->config & MV_CESA_DIRECTION_MASK) == -+ (MV_CESA_DIR_ENCODE << MV_CESA_DIRECTION_BIT)) ) -+ { -+ -+ /* For Crypto Encode in CBC mode HW always takes IV from SRAM IVPointer, -+ * (not from IVBufPointer). So when ivFromUser==1, we should copy IV from user place -+ * in the buffer to SRAM IVPointer -+ */ -+ i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->cryptoIV, &pDmaDesc[i], -+ MV_FALSE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); -+ } -+ -+ /* Special processing when IV is not located in the first fragment */ -+ if(pCmd->ivOffset > (copySize - pSA->cryptoIvSize)) -+ { -+ /* Prepare dummy place for cryptoIV in SRAM */ -+ cryptoIvOffset = cesaSramVirtPtr->tempCryptoIV - mvCesaSramAddrGet(); -+ -+ /* For Decryption: Copy IV value from pCmd->ivOffset to Special SRAM place */ -+ if((pSA->config & MV_CESA_DIRECTION_MASK) == -+ (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) -+ { -+ i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->tempCryptoIV, &pDmaDesc[i], -+ MV_FALSE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); -+ } -+ else -+ { -+ /* For Encryption when IV is NOT from User: */ -+ /* Copy IV from SRAM to buffer (pCmd->ivOffset) */ -+ if(pCmd->ivFromUser == 0) -+ { -+ /* copy IV value from cryptoIV to Buffer (pCmd->ivOffset) */ -+ i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->cryptoIV, &pDmaDesc[i], -+ MV_TRUE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); -+ } -+ } -+ } -+ else -+ { -+ cryptoIvOffset = pCmd->ivOffset; -+ } -+ } -+ } -+ -+ if( (pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ /* MAC digest special processing on Decode direction */ -+ if((pSA->config & MV_CESA_DIRECTION_MASK) == -+ (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) -+ { -+ /* Save digest from pCmd->digestOffset */ -+ mvCesaCopyFromMbuf(pReq->frags.orgDigest, -+ pCmd->pSrc, pCmd->digestOffset, pSA->digestSize); -+ -+ /* If pCmd->digestOffset is not located on the first */ -+ if(pCmd->digestOffset > (copySize - pSA->digestSize)) -+ { -+ MV_U8 digestZero[MV_CESA_MAX_DIGEST_SIZE]; -+ -+ /* Set zeros to pCmd->digestOffset (DRAM) */ -+ memset(digestZero, 0, MV_CESA_MAX_DIGEST_SIZE); -+ mvCesaCopyToMbuf(digestZero, pCmd->pSrc, pCmd->digestOffset, pSA->digestSize); -+ -+ /* Prepare dummy place for digest in SRAM */ -+ digestOffset = cesaSramVirtPtr->tempDigest - mvCesaSramAddrGet(); -+ } -+ else -+ { -+ digestOffset = pCmd->digestOffset; -+ } -+ } -+ } -+ /* Update SA in SRAM */ -+ if(cesaLastSid != sid) -+ { -+ mvCesaSramSaUpdate(sid, &pDmaDesc[i]); -+ i++; -+ } -+ -+ pReq->fragMode = MV_CESA_FRAG_MIDDLE; -+ } -+ else -+ { -+ /* Continue fragment */ -+ fixOffset = 0; -+ cryptoOffset = 0; -+ macOffset = 0; -+ if( (pCmd->pSrc->mbufSize - pReq->frags.bufOffset) <= sizeof(cesaSramVirtPtr->buf)) -+ { -+ /* Last fragment */ -+ config = pSA->config | (MV_CESA_FRAG_LAST << MV_CESA_FRAG_MODE_OFFSET); -+ pReq->fragMode = MV_CESA_FRAG_LAST; -+ copySize = pCmd->pSrc->mbufSize - pReq->frags.bufOffset; -+ -+ if( (pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ macDataSize = pCmd->macLength - pReq->frags.macSize; -+ -+ /* If pCmd->digestOffset is not located on last fragment */ -+ if(pCmd->digestOffset < pReq->frags.bufOffset) -+ { -+ /* Prepare dummy place for digest in SRAM */ -+ digestOffset = cesaSramVirtPtr->tempDigest - mvCesaSramAddrGet(); -+ } -+ else -+ { -+ digestOffset = pCmd->digestOffset - pReq->frags.bufOffset; -+ } -+ pReq->frags.newDigestOffset = digestOffset; -+ macTotalLen = pCmd->macLength; -+ -+ /* HW can't calculate the Digest correctly for fragmented packets -+ * in the following cases: -+ * - MV88F5182 || -+ * - MV88F5181L when total macLength more that 16 Kbytes || -+ * - total macLength more that 64 Kbytes -+ */ -+ if( (mvCtrlModelGet() == MV_5182_DEV_ID) || -+ ( (mvCtrlModelGet() == MV_5181_DEV_ID) && -+ (mvCtrlRevGet() >= MV_5181L_A0_REV) && -+ (pCmd->macLength >= (1 << 14)) ) ) -+ { -+ return MV_TERMINATE; -+ } -+ } -+ if( (pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ cryptoDataSize = pCmd->cryptoLength - pReq->frags.cryptoSize; -+ } -+ -+ /* cryptoIvOffset - don't care */ -+ } -+ else -+ { -+ /* WA for MV88F5182 SHA1 and MD5 fragmentation mode */ -+ if( (mvCtrlModelGet() == MV_5182_DEV_ID) && -+ (((pSA->config & MV_CESA_MAC_MODE_MASK) == -+ (MV_CESA_MAC_MD5 << MV_CESA_MAC_MODE_OFFSET)) || -+ ((pSA->config & MV_CESA_MAC_MODE_MASK) == -+ (MV_CESA_MAC_SHA1 << MV_CESA_MAC_MODE_OFFSET))) ) -+ { -+ pReq->frags.newDigestOffset = cesaSramVirtPtr->tempDigest - mvCesaSramAddrGet(); -+ pReq->fragMode = MV_CESA_FRAG_LAST; -+ -+ return MV_TERMINATE; -+ } -+ /* Middle fragment */ -+ config = pSA->config | (MV_CESA_FRAG_MIDDLE << MV_CESA_FRAG_MODE_OFFSET); -+ copySize = sizeof(cesaSramVirtPtr->buf); -+ /* digestOffset and cryptoIvOffset - don't care */ -+ -+ /* Find fragment size */ -+ mvCesaFragSizeFind(pSA, pReq, cryptoOffset, macOffset, -+ ©Size, &cryptoDataSize, &macDataSize); -+ } -+ } -+ /********* Prepare DMA descriptors to copy from pSrc to SRAM *********/ -+ pMbuf = pCmd->pSrc; -+ i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], -+ MV_FALSE, pReq->frags.bufOffset, copySize, pCmd->skipFlush); -+ -+ /* Prepare CESA descriptor to copy from DRAM to SRAM by DMA */ -+ mvCesaSramDescrBuild(config, frag, -+ cryptoOffset + fixOffset, cryptoIvOffset + fixOffset, -+ cryptoDataSize, macOffset + fixOffset, -+ digestOffset + fixOffset, macDataSize, macTotalLen, -+ pReq, &pDmaDesc[i]); -+ i++; -+ -+ /* Add special descriptor Ownership for CPU */ -+ pDmaDesc[i].byteCnt = 0; -+ pDmaDesc[i].phySrcAdd = 0; -+ pDmaDesc[i].phyDestAdd = 0; -+ i++; -+ -+ /********* Prepare DMA descriptors to copy from SRAM to pDst *********/ -+ pMbuf = pCmd->pDst; -+ i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], -+ MV_TRUE, pReq->frags.bufOffset, copySize, pCmd->skipFlush); -+ -+ /* Next field of Last DMA descriptor must be NULL */ -+ pDmaDesc[i-1].phyNextDescPtr = 0; -+ pReq->dma[frag].pDmaLast = &pDmaDesc[i-1]; -+ mvOsCacheFlush(NULL, pReq->dma[frag].pDmaFirst, -+ i*sizeof(MV_DMA_DESC)); -+ -+ /*mvCesaDebugDescriptor(&cesaSramVirtPtr->desc[frag]);*/ -+ -+ pReq->frags.bufOffset += copySize; -+ pReq->frags.cryptoSize += cryptoDataSize; -+ pReq->frags.macSize += macDataSize; -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvCesaReqProcess - Process regular (Non-fragmented) request -+* -+* DESCRIPTION: -+* This function processes the whole (not fragmented) request -+* -+* INPUT: -+* MV_CESA_REQ* pReq - Pointer to the request in the request queue. -+* -+* RETURN: -+* MV_OK - The request is successfully passed to HW for processing. -+* Other - Failure. The request will not be processed -+* -+*******************************************************************************/ -+static MV_STATUS mvCesaReqProcess(MV_CESA_REQ* pReq) -+{ -+ MV_CESA_MBUF *pMbuf; -+ MV_DMA_DESC *pDmaDesc; -+ MV_U8 *pSramBuf; -+ int sid, i, fixOffset; -+ MV_CESA_SA *pSA; -+ MV_CESA_COMMAND *pCmd = pReq->pCmd; -+ -+ cesaStats.procCount++; -+ -+ sid = pCmd->sessionId; -+ pSA = &pCesaSAD[sid]; -+ pDmaDesc = pReq->dma[0].pDmaFirst; -+ pSramBuf = cesaSramVirtPtr->buf; -+ fixOffset = pReq->fixOffset; -+ -+/* -+ mvOsPrintf("mvCesaReqProcess: sid=%d, pSA=%p, pDmaDesc=%p, pSramBuf=%p\n", -+ sid, pSA, pDmaDesc, pSramBuf); -+*/ -+ i = 0; -+ -+ /* Crypto IV Special processing in CBC mode for Encryption direction */ -+ if( ((pSA->config & MV_CESA_OPERATION_MASK) != (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) && -+ ((pSA->config & MV_CESA_CRYPTO_MODE_MASK) == (MV_CESA_CRYPTO_CBC << MV_CESA_CRYPTO_MODE_BIT)) && -+ ((pSA->config & MV_CESA_DIRECTION_MASK) == (MV_CESA_DIR_ENCODE << MV_CESA_DIRECTION_BIT)) && -+ (pCmd->ivFromUser) ) -+ { -+ /* For Crypto Encode in CBC mode HW always takes IV from SRAM IVPointer, -+ * (not from IVBufPointer). So when ivFromUser==1, we should copy IV from user place -+ * in the buffer to SRAM IVPointer -+ */ -+ i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->cryptoIV, &pDmaDesc[i], -+ MV_FALSE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); -+ } -+ -+ /* Update SA in SRAM */ -+ if(cesaLastSid != sid) -+ { -+ mvCesaSramSaUpdate(sid, &pDmaDesc[i]); -+ i++; -+ } -+ -+ /********* Prepare DMA descriptors to copy from pSrc to SRAM *********/ -+ pMbuf = pCmd->pSrc; -+ i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], -+ MV_FALSE, 0, pMbuf->mbufSize, pCmd->skipFlush); -+ -+ /* Prepare Security Accelerator descriptor to SRAM words 0 - 7 */ -+ mvCesaSramDescrBuild(pSA->config, 0, pCmd->cryptoOffset + fixOffset, -+ pCmd->ivOffset + fixOffset, pCmd->cryptoLength, -+ pCmd->macOffset + fixOffset, pCmd->digestOffset + fixOffset, -+ pCmd->macLength, pCmd->macLength, pReq, &pDmaDesc[i]); -+ i++; -+ -+ /* Add special descriptor Ownership for CPU */ -+ pDmaDesc[i].byteCnt = 0; -+ pDmaDesc[i].phySrcAdd = 0; -+ pDmaDesc[i].phyDestAdd = 0; -+ i++; -+ -+ /********* Prepare DMA descriptors to copy from SRAM to pDst *********/ -+ pMbuf = pCmd->pDst; -+ i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], -+ MV_TRUE, 0, pMbuf->mbufSize, pCmd->skipFlush); -+ -+ /* Next field of Last DMA descriptor must be NULL */ -+ pDmaDesc[i-1].phyNextDescPtr = 0; -+ pReq->dma[0].pDmaLast = &pDmaDesc[i-1]; -+ mvOsCacheFlush(NULL, pReq->dma[0].pDmaFirst, i*sizeof(MV_DMA_DESC)); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvCesaSramDescrBuild - Set CESA descriptor in SRAM -+* -+* DESCRIPTION: -+* This function builds CESA descriptor in SRAM from all Command parameters -+* -+* -+* INPUT: -+* int chan - CESA channel uses the descriptor -+* MV_U32 config - 32 bits of WORD_0 in CESA descriptor structure -+* int cryptoOffset - Offset from the beginning of SRAM buffer where -+* data for encryption/decription is started. -+* int ivOffset - Offset of crypto IV from the SRAM base. Valid only -+* for first fragment. -+* int cryptoLength - Size (in bytes) of data for encryption/descryption -+* operation on this fragment. -+* int macOffset - Offset from the beginning of SRAM buffer where -+* data for Authentication is started -+* int digestOffset - Offset from the beginning of SRAM buffer where -+* digest is located. Valid for first and last fragments. -+* int macLength - Size (in bytes) of data for Authentication -+* operation on this fragment. -+* int macTotalLen - Toatl size (in bytes) of data for Authentication -+* operation on the whole request (packet). Valid for -+* last fragment only. -+* -+* RETURN: None -+* -+*******************************************************************************/ -+static void mvCesaSramDescrBuild(MV_U32 config, int frag, -+ int cryptoOffset, int ivOffset, int cryptoLength, -+ int macOffset, int digestOffset, int macLength, -+ int macTotalLen, MV_CESA_REQ* pReq, MV_DMA_DESC* pDmaDesc) -+{ -+ MV_CESA_DESC* pCesaDesc = &pReq->pCesaDesc[frag]; -+ MV_CESA_DESC* pSramDesc = pSramDesc = &cesaSramVirtPtr->desc; -+ MV_U16 sramBufOffset = (MV_U16)((MV_U8*)cesaSramVirtPtr->buf - mvCesaSramAddrGet()); -+ -+ pCesaDesc->config = MV_32BIT_LE(config); -+ -+ if( (config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ /* word 1 */ -+ pCesaDesc->cryptoSrcOffset = MV_16BIT_LE(sramBufOffset + cryptoOffset); -+ pCesaDesc->cryptoDstOffset = MV_16BIT_LE(sramBufOffset + cryptoOffset); -+ /* word 2 */ -+ pCesaDesc->cryptoDataLen = MV_16BIT_LE(cryptoLength); -+ /* word 3 */ -+ pCesaDesc->cryptoKeyOffset = MV_16BIT_LE((MV_U16)(cesaSramVirtPtr->sramSA.cryptoKey - -+ mvCesaSramAddrGet())); -+ /* word 4 */ -+ pCesaDesc->cryptoIvOffset = MV_16BIT_LE((MV_U16)(cesaSramVirtPtr->cryptoIV - -+ mvCesaSramAddrGet())); -+ pCesaDesc->cryptoIvBufOffset = MV_16BIT_LE(sramBufOffset + ivOffset); -+ } -+ -+ if( (config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ /* word 5 */ -+ pCesaDesc->macSrcOffset = MV_16BIT_LE(sramBufOffset + macOffset); -+ pCesaDesc->macTotalLen = MV_16BIT_LE(macTotalLen); -+ -+ /* word 6 */ -+ pCesaDesc->macDigestOffset = MV_16BIT_LE(sramBufOffset + digestOffset); -+ pCesaDesc->macDataLen = MV_16BIT_LE(macLength); -+ -+ /* word 7 */ -+ pCesaDesc->macInnerIvOffset = MV_16BIT_LE((MV_U16)(cesaSramVirtPtr->sramSA.macInnerIV - -+ mvCesaSramAddrGet())); -+ pCesaDesc->macOuterIvOffset = MV_16BIT_LE((MV_U16)(cesaSramVirtPtr->sramSA.macOuterIV - -+ mvCesaSramAddrGet())); -+ } -+ /* Prepare DMA descriptor to CESA descriptor from DRAM to SRAM */ -+ pDmaDesc->phySrcAdd = MV_32BIT_LE(mvCesaVirtToPhys(&pReq->cesaDescBuf, pCesaDesc)); -+ pDmaDesc->phyDestAdd = MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (MV_U8*)pSramDesc)); -+ pDmaDesc->byteCnt = MV_32BIT_LE(sizeof(MV_CESA_DESC) | BIT31); -+ -+ /* flush Source buffer */ -+ mvOsCacheFlush(NULL, pCesaDesc, sizeof(MV_CESA_DESC)); -+} -+ -+/******************************************************************************* -+* mvCesaSramSaUpdate - Move required SA information to SRAM if needed. -+* -+* DESCRIPTION: -+* Copy to SRAM values of the required SA. -+* -+* -+* INPUT: -+* short sid - Session ID needs SRAM Cache update -+* MV_DMA_DESC *pDmaDesc - Pointer to DMA descriptor used to -+* copy SA values from DRAM to SRAM. -+* -+* RETURN: -+* MV_OK - Cache entry for this SA copied to SRAM. -+* MV_NO_CHANGE - Cache entry for this SA already exist in SRAM -+* -+*******************************************************************************/ -+static INLINE void mvCesaSramSaUpdate(short sid, MV_DMA_DESC *pDmaDesc) -+{ -+ MV_CESA_SA *pSA = &pCesaSAD[sid]; -+ -+ /* Prepare DMA descriptor to Copy CACHE_SA from SA database in DRAM to SRAM */ -+ pDmaDesc->byteCnt = MV_32BIT_LE(sizeof(MV_CESA_SRAM_SA) | BIT31); -+ pDmaDesc->phySrcAdd = MV_32BIT_LE(mvCesaVirtToPhys(&cesaSramSaBuf, pSA->pSramSA)); -+ pDmaDesc->phyDestAdd = -+ MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (MV_U8*)&cesaSramVirtPtr->sramSA)); -+ -+ /* Source buffer is already flushed during OpenSession*/ -+ /*mvOsCacheFlush(NULL, &pSA->sramSA, sizeof(MV_CESA_SRAM_SA));*/ -+} -+ -+/******************************************************************************* -+* mvCesaDmaCopyPrepare - prepare DMA descriptor list to copy data presented by -+* Mbuf structure from DRAM to SRAM -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_CESA_MBUF* pMbuf - pointer to Mbuf structure contains request -+* data in DRAM -+* MV_U8* pSramBuf - pointer to buffer in SRAM where data should -+* be copied to. -+* MV_DMA_DESC* pDmaDesc - pointer to first DMA descriptor for this copy. -+* The function set number of DMA descriptors needed -+* to copy the copySize bytes from Mbuf. -+* MV_BOOL isToMbuf - Copy direction. -+* MV_TRUE means copy from SRAM buffer to Mbuf in DRAM. -+* MV_FALSE means copy from Mbuf in DRAM to SRAM buffer. -+* int offset - Offset in the Mbuf structure that copy should be -+* started from. -+* int copySize - Size of data should be copied. -+* -+* RETURN: -+* int - number of DMA descriptors used for the copy. -+* -+*******************************************************************************/ -+#ifndef MV_NETBSD -+static INLINE int mvCesaDmaCopyPrepare(MV_CESA_MBUF* pMbuf, MV_U8* pSramBuf, -+ MV_DMA_DESC* pDmaDesc, MV_BOOL isToMbuf, -+ int offset, int copySize, MV_BOOL skipFlush) -+{ -+ int bufOffset, bufSize, size, frag, i; -+ MV_U8* pBuf; -+ -+ i = 0; -+ -+ /* Calculate start place for copy: fragment number and offset in the fragment */ -+ frag = mvCesaMbufOffset(pMbuf, offset, &bufOffset); -+ bufSize = pMbuf->pFrags[frag].bufSize - bufOffset; -+ pBuf = pMbuf->pFrags[frag].bufVirtPtr + bufOffset; -+ -+ /* Size accumulate total copy size */ -+ size = 0; -+ -+ /* Create DMA lists to copy mBuf from pSrc to SRAM */ -+ while(size < copySize) -+ { -+ /* Find copy size for each DMA descriptor */ -+ bufSize = MV_MIN(bufSize, (copySize - size)); -+ pDmaDesc[i].byteCnt = MV_32BIT_LE(bufSize | BIT31); -+ if(isToMbuf) -+ { -+ pDmaDesc[i].phyDestAdd = MV_32BIT_LE(mvOsIoVirtToPhy(NULL, pBuf)); -+ pDmaDesc[i].phySrcAdd = -+ MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (pSramBuf + size))); -+ /* invalidate the buffer */ -+ if(skipFlush == MV_FALSE) -+ mvOsCacheInvalidate(NULL, pBuf, bufSize); -+ } -+ else -+ { -+ pDmaDesc[i].phySrcAdd = MV_32BIT_LE(mvOsIoVirtToPhy(NULL, pBuf)); -+ pDmaDesc[i].phyDestAdd = -+ MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (pSramBuf + size))); -+ /* flush the buffer */ -+ if(skipFlush == MV_FALSE) -+ mvOsCacheFlush(NULL, pBuf, bufSize); -+ } -+ -+ /* Count number of used DMA descriptors */ -+ i++; -+ size += bufSize; -+ -+ /* go to next fragment in the Mbuf */ -+ frag++; -+ pBuf = pMbuf->pFrags[frag].bufVirtPtr; -+ bufSize = pMbuf->pFrags[frag].bufSize; -+ } -+ return i; -+} -+#else /* MV_NETBSD */ -+static int mvCesaDmaCopyPrepare(MV_CESA_MBUF* pMbuf, MV_U8* pSramBuf, -+ MV_DMA_DESC* pDmaDesc, MV_BOOL isToMbuf, -+ int offset, int copySize, MV_BOOL skipFlush) -+{ -+ int bufOffset, bufSize, thisSize, size, frag, i; -+ MV_ULONG bufPhys, sramPhys; -+ MV_U8* pBuf; -+ -+ /* -+ * Calculate start place for copy: fragment number and offset in -+ * the fragment -+ */ -+ frag = mvCesaMbufOffset(pMbuf, offset, &bufOffset); -+ -+ /* -+ * Get SRAM physical address only once. We can update it in-place -+ * as we build the descriptor chain. -+ */ -+ sramPhys = mvCesaSramVirtToPhys(NULL, pSramBuf); -+ -+ /* -+ * 'size' accumulates total copy size, 'i' counts desccriptors. -+ */ -+ size = i = 0; -+ -+ /* Create DMA lists to copy mBuf from pSrc to SRAM */ -+ while (size < copySize) { -+ /* -+ * Calculate # of bytes to copy from the current fragment, -+ * and the pointer to the start of data -+ */ -+ bufSize = pMbuf->pFrags[frag].bufSize - bufOffset; -+ pBuf = pMbuf->pFrags[frag].bufVirtPtr + bufOffset; -+ bufOffset = 0; /* First frag may be non-zero */ -+ frag++; -+ -+ /* -+ * As long as there is data in the current fragment... -+ */ -+ while (bufSize > 0) { -+ /* -+ * Ensure we don't cross an MMU page boundary. -+ * XXX: This is NetBSD-specific, but it is a -+ * quick and dirty way to fix the problem. -+ * A true HAL would rely on the OS-specific -+ * driver to do this... -+ */ -+ thisSize = PAGE_SIZE - -+ (((MV_ULONG)pBuf) & (PAGE_SIZE - 1)); -+ thisSize = MV_MIN(bufSize, thisSize); -+ /* -+ * Make sure we don't copy more than requested -+ */ -+ if (thisSize > (copySize - size)) { -+ thisSize = copySize - size; -+ bufSize = 0; -+ } -+ -+ /* -+ * Physicall address of this fragment -+ */ -+ bufPhys = MV_32BIT_LE(mvOsIoVirtToPhy(NULL, pBuf)); -+ -+ /* -+ * Set up the descriptor -+ */ -+ pDmaDesc[i].byteCnt = MV_32BIT_LE(thisSize | BIT31); -+ if(isToMbuf) { -+ pDmaDesc[i].phyDestAdd = bufPhys; -+ pDmaDesc[i].phySrcAdd = MV_32BIT_LE(sramPhys); -+ /* invalidate the buffer */ -+ if(skipFlush == MV_FALSE) -+ mvOsCacheInvalidate(NULL, pBuf, thisSize); -+ } else { -+ pDmaDesc[i].phySrcAdd = bufPhys; -+ pDmaDesc[i].phyDestAdd = MV_32BIT_LE(sramPhys); -+ /* flush the buffer */ -+ if(skipFlush == MV_FALSE) -+ mvOsCacheFlush(NULL, pBuf, thisSize); -+ } -+ -+ pDmaDesc[i].phyNextDescPtr = -+ MV_32BIT_LE(mvOsIoVirtToPhy(NULL,(&pDmaDesc[i+1]))); -+ -+ /* flush the DMA desc */ -+ mvOsCacheFlush(NULL, &pDmaDesc[i], sizeof(MV_DMA_DESC)); -+ -+ /* Update state */ -+ bufSize -= thisSize; -+ sramPhys += thisSize; -+ pBuf += thisSize; -+ size += thisSize; -+ i++; -+ } -+ } -+ -+ return i; -+} -+#endif /* MV_NETBSD */ -+/******************************************************************************* -+* mvCesaHmacIvGet - Calculate Inner and Outter values from HMAC key -+* -+* DESCRIPTION: -+* This function calculate Inner and Outer values used for HMAC algorithm. -+* This operation allows improve performance fro the whole HMAC processing. -+* -+* INPUT: -+* MV_CESA_MAC_MODE macMode - Authentication mode: HMAC_MD5 or HMAC_SHA1. -+* unsigned char key[] - Pointer to HMAC key. -+* int keyLength - Size of HMAC key (maximum 64 bytes) -+* -+* OUTPUT: -+* unsigned char innerIV[] - HASH(key^inner) -+* unsigned char outerIV[] - HASH(key^outter) -+* -+* RETURN: None -+* -+*******************************************************************************/ -+static void mvCesaHmacIvGet(MV_CESA_MAC_MODE macMode, unsigned char key[], int keyLength, -+ unsigned char innerIV[], unsigned char outerIV[]) -+{ -+ unsigned char inner[MV_CESA_MAX_MAC_KEY_LENGTH]; -+ unsigned char outer[MV_CESA_MAX_MAC_KEY_LENGTH]; -+ int i, digestSize = 0; -+#if defined(MV_CPU_LE) || defined(MV_PPC) -+ MV_U32 swapped32, val32, *pVal32; -+#endif -+ for(i=0; ipFrags[frag].bufVirtPtr + fragOffset; -+ size = pMbuf->pFrags[frag].bufSize - fragOffset; -+ -+ /* Complete Inner part */ -+ while(macLeftSize > 0) -+ { -+ if(macLeftSize <= size) -+ { -+ mvSHA1Update(&ctx, pData, macLeftSize); -+ break; -+ } -+ mvSHA1Update(&ctx, pData, size); -+ macLeftSize -= size; -+ frag++; -+ pData = pMbuf->pFrags[frag].bufVirtPtr; -+ size = pMbuf->pFrags[frag].bufSize; -+ } -+ mvSHA1Final(pDigest, &ctx); -+/* -+ mvOsPrintf("mvCesaFragSha1Complete: pOuterIV=%p, macLeftSize=%d, macTotalSize=%d\n", -+ pOuterIV, macLeftSize, macTotalSize); -+ mvDebugMemDump(pDigest, MV_CESA_SHA1_DIGEST_SIZE, 1); -+*/ -+ -+ if(pOuterIV != NULL) -+ { -+ /* If HMAC - Complete Outer part */ -+ for(i=0; ipFrags[frag].bufVirtPtr + fragOffset; -+ size = pMbuf->pFrags[frag].bufSize - fragOffset; -+ -+ /* Complete Inner part */ -+ while(macLeftSize > 0) -+ { -+ if(macLeftSize <= size) -+ { -+ mvMD5Update(&ctx, pData, macLeftSize); -+ break; -+ } -+ mvMD5Update(&ctx, pData, size); -+ macLeftSize -= size; -+ frag++; -+ pData = pMbuf->pFrags[frag].bufVirtPtr; -+ size = pMbuf->pFrags[frag].bufSize; -+ } -+ mvMD5Final(pDigest, &ctx); -+ -+/* -+ mvOsPrintf("mvCesaFragMd5Complete: pOuterIV=%p, macLeftSize=%d, macTotalSize=%d\n", -+ pOuterIV, macLeftSize, macTotalSize); -+ mvDebugMemDump(pDigest, MV_CESA_MD5_DIGEST_SIZE, 1); -+*/ -+ if(pOuterIV != NULL) -+ { -+ /* Complete Outer part */ -+ for(i=0; ipCmd; -+ MV_U8* pDigest; -+ MV_CESA_MAC_MODE macMode; -+ MV_U8* pOuterIV = NULL; -+ -+ /* Copy data from Source fragment to Destination */ -+ if(pCmd->pSrc != pCmd->pDst) -+ { -+ mvCesaMbufCopy(pCmd->pDst, pReq->frags.bufOffset, -+ pCmd->pSrc, pReq->frags.bufOffset, macDataSize); -+ } -+ -+/* -+ mvCesaCopyFromMbuf(cesaSramVirtPtr->buf[0], pCmd->pSrc, pReq->frags.bufOffset, macDataSize); -+ mvCesaCopyToMbuf(cesaSramVirtPtr->buf[0], pCmd->pDst, pReq->frags.bufOffset, macDataSize); -+*/ -+ pDigest = (mvCesaSramAddrGet() + pReq->frags.newDigestOffset); -+ -+ macMode = (pSA->config & MV_CESA_MAC_MODE_MASK) >> MV_CESA_MAC_MODE_OFFSET; -+/* -+ mvOsPrintf("macDataSize=%d, macLength=%d, digestOffset=%d, macMode=%d\n", -+ macDataSize, pCmd->macLength, pCmd->digestOffset, macMode); -+*/ -+ switch(macMode) -+ { -+ case MV_CESA_MAC_HMAC_MD5: -+ pOuterIV = pSA->pSramSA->macOuterIV; -+ -+ case MV_CESA_MAC_MD5: -+ mvCesaFragMd5Complete(pCmd->pDst, pReq->frags.bufOffset, pOuterIV, -+ macDataSize, pCmd->macLength, pDigest); -+ break; -+ -+ case MV_CESA_MAC_HMAC_SHA1: -+ pOuterIV = pSA->pSramSA->macOuterIV; -+ -+ case MV_CESA_MAC_SHA1: -+ mvCesaFragSha1Complete(pCmd->pDst, pReq->frags.bufOffset, pOuterIV, -+ macDataSize, pCmd->macLength, pDigest); -+ break; -+ -+ default: -+ mvOsPrintf("mvCesaFragAuthComplete: Unexpected macMode %d\n", macMode); -+ return MV_BAD_PARAM; -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaCtrModeInit - -+* -+* DESCRIPTION: -+* -+* -+* INPUT: NONE -+* -+* -+* RETURN: -+* MV_CESA_COMMAND* -+* -+*******************************************************************************/ -+static MV_CESA_COMMAND* mvCesaCtrModeInit(void) -+{ -+ MV_CESA_MBUF *pMbuf; -+ MV_U8 *pBuf; -+ MV_CESA_COMMAND *pCmd; -+ -+ pBuf = mvOsMalloc(sizeof(MV_CESA_COMMAND) + -+ sizeof(MV_CESA_MBUF) + sizeof(MV_BUF_INFO) + 100); -+ if(pBuf == NULL) -+ { -+ mvOsPrintf("mvCesaSessionOpen: Can't allocate %u bytes for CTR Mode\n", -+ sizeof(MV_CESA_COMMAND) + sizeof(MV_CESA_MBUF) + sizeof(MV_BUF_INFO) ); -+ return NULL; -+ } -+ pCmd = (MV_CESA_COMMAND*)pBuf; -+ pBuf += sizeof(MV_CESA_COMMAND); -+ -+ pMbuf = (MV_CESA_MBUF*)pBuf; -+ pBuf += sizeof(MV_CESA_MBUF); -+ -+ pMbuf->pFrags = (MV_BUF_INFO*)pBuf; -+ -+ pMbuf->numFrags = 1; -+ pCmd->pSrc = pMbuf; -+ pCmd->pDst = pMbuf; -+/* -+ mvOsPrintf("CtrModeInit: pCmd=%p, pSrc=%p, pDst=%p, pFrags=%p\n", -+ pCmd, pCmd->pSrc, pCmd->pDst, -+ pMbuf->pFrags); -+*/ -+ return pCmd; -+} -+ -+/******************************************************************************* -+* mvCesaCtrModePrepare - -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_CESA_COMMAND *pCtrModeCmd, MV_CESA_COMMAND *pCmd -+* -+* RETURN: -+* MV_STATUS -+* -+*******************************************************************************/ -+static MV_STATUS mvCesaCtrModePrepare(MV_CESA_COMMAND *pCtrModeCmd, MV_CESA_COMMAND *pCmd) -+{ -+ MV_CESA_MBUF *pMbuf; -+ MV_U8 *pBuf, *pIV; -+ MV_U32 counter, *pCounter; -+ int cryptoSize = MV_ALIGN_UP(pCmd->cryptoLength, MV_CESA_AES_BLOCK_SIZE); -+/* -+ mvOsPrintf("CtrModePrepare: pCmd=%p, pCtrSrc=%p, pCtrDst=%p, pOrgCmd=%p, pOrgSrc=%p, pOrgDst=%p\n", -+ pCmd, pCmd->pSrc, pCmd->pDst, -+ pCtrModeCmd, pCtrModeCmd->pSrc, pCtrModeCmd->pDst); -+*/ -+ pMbuf = pCtrModeCmd->pSrc; -+ -+ /* Allocate buffer for Key stream */ -+ pBuf = mvOsIoCachedMalloc(cesaOsHandle,cryptoSize, -+ &pMbuf->pFrags[0].bufPhysAddr, -+ &pMbuf->pFrags[0].memHandle); -+ if(pBuf == NULL) -+ { -+ mvOsPrintf("mvCesaCtrModePrepare: Can't allocate %d bytes\n", cryptoSize); -+ return MV_OUT_OF_CPU_MEM; -+ } -+ memset(pBuf, 0, cryptoSize); -+ mvOsCacheFlush(NULL, pBuf, cryptoSize); -+ -+ pMbuf->pFrags[0].bufVirtPtr = pBuf; -+ pMbuf->mbufSize = cryptoSize; -+ pMbuf->pFrags[0].bufSize = cryptoSize; -+ -+ pCtrModeCmd->pReqPrv = pCmd->pReqPrv; -+ pCtrModeCmd->sessionId = pCmd->sessionId; -+ -+ /* ivFromUser and ivOffset are don't care */ -+ pCtrModeCmd->cryptoOffset = 0; -+ pCtrModeCmd->cryptoLength = cryptoSize; -+ -+ /* digestOffset, macOffset and macLength are don't care */ -+ -+ mvCesaCopyFromMbuf(pBuf, pCmd->pSrc, pCmd->ivOffset, MV_CESA_AES_BLOCK_SIZE); -+ pCounter = (MV_U32*)(pBuf + (MV_CESA_AES_BLOCK_SIZE - sizeof(counter))); -+ counter = *pCounter; -+ counter = MV_32BIT_BE(counter); -+ pIV = pBuf; -+ cryptoSize -= MV_CESA_AES_BLOCK_SIZE; -+ -+ /* fill key stream */ -+ while(cryptoSize > 0) -+ { -+ pBuf += MV_CESA_AES_BLOCK_SIZE; -+ memcpy(pBuf, pIV, MV_CESA_AES_BLOCK_SIZE - sizeof(counter)); -+ pCounter = (MV_U32*)(pBuf + (MV_CESA_AES_BLOCK_SIZE - sizeof(counter))); -+ counter++; -+ *pCounter = MV_32BIT_BE(counter); -+ cryptoSize -= MV_CESA_AES_BLOCK_SIZE; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaCtrModeComplete - -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_CESA_COMMAND *pOrgCmd, MV_CESA_COMMAND *pCmd -+* -+* RETURN: -+* MV_STATUS -+* -+*******************************************************************************/ -+static MV_STATUS mvCesaCtrModeComplete(MV_CESA_COMMAND *pOrgCmd, MV_CESA_COMMAND *pCmd) -+{ -+ int srcFrag, dstFrag, srcOffset, dstOffset, keyOffset, srcSize, dstSize; -+ int cryptoSize = pCmd->cryptoLength; -+ MV_U8 *pSrc, *pDst, *pKey; -+ MV_STATUS status = MV_OK; -+/* -+ mvOsPrintf("CtrModeComplete: pCmd=%p, pCtrSrc=%p, pCtrDst=%p, pOrgCmd=%p, pOrgSrc=%p, pOrgDst=%p\n", -+ pCmd, pCmd->pSrc, pCmd->pDst, -+ pOrgCmd, pOrgCmd->pSrc, pOrgCmd->pDst); -+*/ -+ /* XOR source data with key stream to destination data */ -+ pKey = pCmd->pDst->pFrags[0].bufVirtPtr; -+ keyOffset = 0; -+ -+ if( (pOrgCmd->pSrc != pOrgCmd->pDst) && -+ (pOrgCmd->cryptoOffset > 0) ) -+ { -+ /* Copy Prefix from source buffer to destination buffer */ -+ -+ status = mvCesaMbufCopy(pOrgCmd->pDst, 0, -+ pOrgCmd->pSrc, 0, pOrgCmd->cryptoOffset); -+/* -+ status = mvCesaCopyFromMbuf(tempBuf, pOrgCmd->pSrc, -+ 0, pOrgCmd->cryptoOffset); -+ status = mvCesaCopyToMbuf(tempBuf, pOrgCmd->pDst, -+ 0, pOrgCmd->cryptoOffset); -+*/ -+ } -+ -+ srcFrag = mvCesaMbufOffset(pOrgCmd->pSrc, pOrgCmd->cryptoOffset, &srcOffset); -+ pSrc = pOrgCmd->pSrc->pFrags[srcFrag].bufVirtPtr; -+ srcSize = pOrgCmd->pSrc->pFrags[srcFrag].bufSize; -+ -+ dstFrag = mvCesaMbufOffset(pOrgCmd->pDst, pOrgCmd->cryptoOffset, &dstOffset); -+ pDst = pOrgCmd->pDst->pFrags[dstFrag].bufVirtPtr; -+ dstSize = pOrgCmd->pDst->pFrags[dstFrag].bufSize; -+ -+ while(cryptoSize > 0) -+ { -+ pDst[dstOffset] = (pSrc[srcOffset] ^ pKey[keyOffset]); -+ -+ cryptoSize--; -+ dstOffset++; -+ srcOffset++; -+ keyOffset++; -+ -+ if(srcOffset >= srcSize) -+ { -+ srcFrag++; -+ srcOffset = 0; -+ pSrc = pOrgCmd->pSrc->pFrags[srcFrag].bufVirtPtr; -+ srcSize = pOrgCmd->pSrc->pFrags[srcFrag].bufSize; -+ } -+ -+ if(dstOffset >= dstSize) -+ { -+ dstFrag++; -+ dstOffset = 0; -+ pDst = pOrgCmd->pDst->pFrags[dstFrag].bufVirtPtr; -+ dstSize = pOrgCmd->pDst->pFrags[dstFrag].bufSize; -+ } -+ } -+ -+ if(pOrgCmd->pSrc != pOrgCmd->pDst) -+ { -+ /* Copy Suffix from source buffer to destination buffer */ -+ srcOffset = pOrgCmd->cryptoOffset + pOrgCmd->cryptoLength; -+ -+ if( (pOrgCmd->pDst->mbufSize - srcOffset) > 0) -+ { -+ status = mvCesaMbufCopy(pOrgCmd->pDst, srcOffset, -+ pOrgCmd->pSrc, srcOffset, -+ pOrgCmd->pDst->mbufSize - srcOffset); -+ } -+ -+/* -+ status = mvCesaCopyFromMbuf(tempBuf, pOrgCmd->pSrc, -+ srcOffset, pOrgCmd->pSrc->mbufSize - srcOffset); -+ status = mvCesaCopyToMbuf(tempBuf, pOrgCmd->pDst, -+ srcOffset, pOrgCmd->pDst->mbufSize - srcOffset); -+*/ -+ } -+ -+ /* Free buffer used for Key stream */ -+ mvOsIoCachedFree(cesaOsHandle,pCmd->pDst->pFrags[0].bufSize, -+ pCmd->pDst->pFrags[0].bufPhysAddr, -+ pCmd->pDst->pFrags[0].bufVirtPtr, -+ pCmd->pDst->pFrags[0].memHandle); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaCtrModeFinish - -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_CESA_COMMAND* pCmd -+* -+* RETURN: -+* MV_STATUS -+* -+*******************************************************************************/ -+static void mvCesaCtrModeFinish(MV_CESA_COMMAND* pCmd) -+{ -+ mvOsFree(pCmd); -+} -+ -+/******************************************************************************* -+* mvCesaParamCheck - -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, MV_U8* pFixOffset -+* -+* RETURN: -+* MV_STATUS -+* -+*******************************************************************************/ -+static MV_STATUS mvCesaParamCheck(MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, -+ MV_U8* pFixOffset) -+{ -+ MV_U8 fixOffset = 0xFF; -+ -+ /* Check AUTH operation parameters */ -+ if( ((pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET)) ) -+ { -+ /* MAC offset should be at least 4 byte aligned */ -+ if( MV_IS_NOT_ALIGN(pCmd->macOffset, 4) ) -+ { -+ mvOsPrintf("mvCesaAction: macOffset %d must be 4 byte aligned\n", -+ pCmd->macOffset); -+ return MV_BAD_PARAM; -+ } -+ /* Digest offset must be 4 byte aligned */ -+ if( MV_IS_NOT_ALIGN(pCmd->digestOffset, 4) ) -+ { -+ mvOsPrintf("mvCesaAction: digestOffset %d must be 4 byte aligned\n", -+ pCmd->digestOffset); -+ return MV_BAD_PARAM; -+ } -+ /* In addition all offsets should be the same alignment: 8 or 4 */ -+ if(fixOffset == 0xFF) -+ { -+ fixOffset = (pCmd->macOffset % 8); -+ } -+ else -+ { -+ if( (pCmd->macOffset % 8) != fixOffset) -+ { -+ mvOsPrintf("mvCesaAction: macOffset %d mod 8 must be equal %d\n", -+ pCmd->macOffset, fixOffset); -+ return MV_BAD_PARAM; -+ } -+ } -+ if( (pCmd->digestOffset % 8) != fixOffset) -+ { -+ mvOsPrintf("mvCesaAction: digestOffset %d mod 8 must be equal %d\n", -+ pCmd->digestOffset, fixOffset); -+ return MV_BAD_PARAM; -+ } -+ } -+ /* Check CRYPTO operation parameters */ -+ if( ((pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) ) -+ { -+ /* CryptoOffset should be at least 4 byte aligned */ -+ if( MV_IS_NOT_ALIGN(pCmd->cryptoOffset, 4) ) -+ { -+ mvOsPrintf("CesaAction: cryptoOffset=%d must be 4 byte aligned\n", -+ pCmd->cryptoOffset); -+ return MV_BAD_PARAM; -+ } -+ /* cryptoLength should be the whole number of blocks */ -+ if( MV_IS_NOT_ALIGN(pCmd->cryptoLength, pSA->cryptoBlockSize) ) -+ { -+ mvOsPrintf("mvCesaAction: cryptoLength=%d must be %d byte aligned\n", -+ pCmd->cryptoLength, pSA->cryptoBlockSize); -+ return MV_BAD_PARAM; -+ } -+ if(fixOffset == 0xFF) -+ { -+ fixOffset = (pCmd->cryptoOffset % 8); -+ } -+ else -+ { -+ /* In addition all offsets should be the same alignment: 8 or 4 */ -+ if( (pCmd->cryptoOffset % 8) != fixOffset) -+ { -+ mvOsPrintf("mvCesaAction: cryptoOffset %d mod 8 must be equal %d \n", -+ pCmd->cryptoOffset, fixOffset); -+ return MV_BAD_PARAM; -+ } -+ } -+ -+ /* check for CBC mode */ -+ if(pSA->cryptoIvSize > 0) -+ { -+ /* cryptoIV must not be part of CryptoLength */ -+ if( ((pCmd->ivOffset + pSA->cryptoIvSize) > pCmd->cryptoOffset) && -+ (pCmd->ivOffset < (pCmd->cryptoOffset + pCmd->cryptoLength)) ) -+ { -+ mvOsPrintf("mvCesaFragParamCheck: cryptoIvOffset (%d) is part of cryptoLength (%d+%d)\n", -+ pCmd->ivOffset, pCmd->macOffset, pCmd->macLength); -+ return MV_BAD_PARAM; -+ } -+ -+ /* ivOffset must be 4 byte aligned */ -+ if( MV_IS_NOT_ALIGN(pCmd->ivOffset, 4) ) -+ { -+ mvOsPrintf("CesaAction: ivOffset=%d must be 4 byte aligned\n", -+ pCmd->ivOffset); -+ return MV_BAD_PARAM; -+ } -+ /* In addition all offsets should be the same alignment: 8 or 4 */ -+ if( (pCmd->ivOffset % 8) != fixOffset) -+ { -+ mvOsPrintf("mvCesaAction: ivOffset %d mod 8 must be %d\n", -+ pCmd->ivOffset, fixOffset); -+ return MV_BAD_PARAM; -+ } -+ } -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaFragParamCheck - -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd -+* -+* RETURN: -+* MV_STATUS -+* -+*******************************************************************************/ -+static MV_STATUS mvCesaFragParamCheck(MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd) -+{ -+ int offset; -+ -+ if( ((pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET)) ) -+ { -+ /* macOffset must be less that SRAM buffer size */ -+ if(pCmd->macOffset > (sizeof(cesaSramVirtPtr->buf) - MV_CESA_AUTH_BLOCK_SIZE)) -+ { -+ mvOsPrintf("mvCesaFragParamCheck: macOffset is too large (%d)\n", -+ pCmd->macOffset); -+ return MV_BAD_PARAM; -+ } -+ /* macOffset+macSize must be more than mbufSize - SRAM buffer size */ -+ if( ((pCmd->macOffset + pCmd->macLength) > pCmd->pSrc->mbufSize) || -+ ((pCmd->pSrc->mbufSize - (pCmd->macOffset + pCmd->macLength)) >= -+ sizeof(cesaSramVirtPtr->buf)) ) -+ { -+ mvOsPrintf("mvCesaFragParamCheck: macLength is too large (%d), mbufSize=%d\n", -+ pCmd->macLength, pCmd->pSrc->mbufSize); -+ return MV_BAD_PARAM; -+ } -+ } -+ -+ if( ((pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) ) -+ { -+ /* cryptoOffset must be less that SRAM buffer size */ -+ /* 4 for possible fixOffset */ -+ if( (pCmd->cryptoOffset + 4) > (sizeof(cesaSramVirtPtr->buf) - pSA->cryptoBlockSize)) -+ { -+ mvOsPrintf("mvCesaFragParamCheck: cryptoOffset is too large (%d)\n", -+ pCmd->cryptoOffset); -+ return MV_BAD_PARAM; -+ } -+ -+ /* cryptoOffset+cryptoSize must be more than mbufSize - SRAM buffer size */ -+ if( ((pCmd->cryptoOffset + pCmd->cryptoLength) > pCmd->pSrc->mbufSize) || -+ ((pCmd->pSrc->mbufSize - (pCmd->cryptoOffset + pCmd->cryptoLength)) >= -+ (sizeof(cesaSramVirtPtr->buf) - pSA->cryptoBlockSize)) ) -+ { -+ mvOsPrintf("mvCesaFragParamCheck: cryptoLength is too large (%d), mbufSize=%d\n", -+ pCmd->cryptoLength, pCmd->pSrc->mbufSize); -+ return MV_BAD_PARAM; -+ } -+ } -+ -+ /* When MAC_THEN_CRYPTO or CRYPTO_THEN_MAC */ -+ if( ((pSA->config & MV_CESA_OPERATION_MASK) == -+ (MV_CESA_MAC_THEN_CRYPTO << MV_CESA_OPERATION_OFFSET)) || -+ ((pSA->config & MV_CESA_OPERATION_MASK) == -+ (MV_CESA_CRYPTO_THEN_MAC << MV_CESA_OPERATION_OFFSET)) ) -+ { -+ if( (mvCtrlModelGet() == MV_5182_DEV_ID) || -+ ( (mvCtrlModelGet() == MV_5181_DEV_ID) && -+ (mvCtrlRevGet() >= MV_5181L_A0_REV) && -+ (pCmd->macLength >= (1 << 14)) ) ) -+ { -+ return MV_NOT_ALLOWED; -+ } -+ -+ /* abs(cryptoOffset-macOffset) must be aligned cryptoBlockSize */ -+ if(pCmd->cryptoOffset > pCmd->macOffset) -+ { -+ offset = pCmd->cryptoOffset - pCmd->macOffset; -+ } -+ else -+ { -+ offset = pCmd->macOffset - pCmd->cryptoOffset; -+ } -+ -+ if( MV_IS_NOT_ALIGN(offset, pSA->cryptoBlockSize) ) -+ { -+/* -+ mvOsPrintf("mvCesaFragParamCheck: (cryptoOffset - macOffset) must be %d byte aligned\n", -+ pSA->cryptoBlockSize); -+*/ -+ return MV_NOT_ALLOWED; -+ } -+ /* Digest must not be part of CryptoLength */ -+ if( ((pCmd->digestOffset + pSA->digestSize) > pCmd->cryptoOffset) && -+ (pCmd->digestOffset < (pCmd->cryptoOffset + pCmd->cryptoLength)) ) -+ { -+/* -+ mvOsPrintf("mvCesaFragParamCheck: digestOffset (%d) is part of cryptoLength (%d+%d)\n", -+ pCmd->digestOffset, pCmd->cryptoOffset, pCmd->cryptoLength); -+*/ -+ return MV_NOT_ALLOWED; -+ } -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaFragSizeFind - -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, -+* int cryptoOffset, int macOffset, -+* -+* OUTPUT: -+* int* pCopySize, int* pCryptoDataSize, int* pMacDataSize -+* -+* RETURN: -+* MV_STATUS -+* -+*******************************************************************************/ -+static void mvCesaFragSizeFind(MV_CESA_SA* pSA, MV_CESA_REQ* pReq, -+ int cryptoOffset, int macOffset, -+ int* pCopySize, int* pCryptoDataSize, int* pMacDataSize) -+{ -+ MV_CESA_COMMAND *pCmd = pReq->pCmd; -+ int cryptoDataSize, macDataSize, copySize; -+ -+ cryptoDataSize = macDataSize = 0; -+ copySize = *pCopySize; -+ -+ if( (pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ cryptoDataSize = MV_MIN( (copySize - cryptoOffset), -+ (pCmd->cryptoLength - (pReq->frags.cryptoSize + 1)) ); -+ -+ /* cryptoSize for each fragment must be the whole number of blocksSize */ -+ if( MV_IS_NOT_ALIGN(cryptoDataSize, pSA->cryptoBlockSize) ) -+ { -+ cryptoDataSize = MV_ALIGN_DOWN(cryptoDataSize, pSA->cryptoBlockSize); -+ copySize = cryptoOffset + cryptoDataSize; -+ } -+ } -+ if( (pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ macDataSize = MV_MIN( (copySize - macOffset), -+ (pCmd->macLength - (pReq->frags.macSize + 1))); -+ -+ /* macSize for each fragment (except last) must be the whole number of blocksSize */ -+ if( MV_IS_NOT_ALIGN(macDataSize, MV_CESA_AUTH_BLOCK_SIZE) ) -+ { -+ macDataSize = MV_ALIGN_DOWN(macDataSize, MV_CESA_AUTH_BLOCK_SIZE); -+ copySize = macOffset + macDataSize; -+ } -+ cryptoDataSize = copySize - cryptoOffset; -+ } -+ *pCopySize = copySize; -+ -+ if(pCryptoDataSize != NULL) -+ *pCryptoDataSize = cryptoDataSize; -+ -+ if(pMacDataSize != NULL) -+ *pMacDataSize = macDataSize; -+} -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/cesa/mvCesaDebug.c linux-2.6.36/crypto/ocf/kirkwood/cesa/mvCesaDebug.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/cesa/mvCesaDebug.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/cesa/mvCesaDebug.c 2010-11-09 20:28:05.342495385 +0100 -@@ -0,0 +1,484 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "mvOs.h" -+#include "mvDebug.h" -+ -+#include "cesa/mvMD5.h" -+#include "cesa/mvSHA1.h" -+ -+#include "cesa/mvCesa.h" -+#include "cesa/mvCesaRegs.h" -+#include "cesa/AES/mvAes.h" -+ -+static const char* mvCesaDebugStateStr(MV_CESA_STATE state) -+{ -+ switch(state) -+ { -+ case MV_CESA_IDLE: -+ return "Idle"; -+ -+ case MV_CESA_PENDING: -+ return "Pend"; -+ -+ case MV_CESA_PROCESS: -+ return "Proc"; -+ -+ case MV_CESA_READY: -+ return "Ready"; -+ -+ default: -+ break; -+ } -+ return "Unknown"; -+} -+ -+static const char* mvCesaDebugOperStr(MV_CESA_OPERATION oper) -+{ -+ switch(oper) -+ { -+ case MV_CESA_MAC_ONLY: -+ return "MacOnly"; -+ -+ case MV_CESA_CRYPTO_ONLY: -+ return "CryptoOnly"; -+ -+ case MV_CESA_MAC_THEN_CRYPTO: -+ return "MacCrypto"; -+ -+ case MV_CESA_CRYPTO_THEN_MAC: -+ return "CryptoMac"; -+ -+ default: -+ break; -+ } -+ return "Null"; -+} -+ -+static const char* mvCesaDebugCryptoAlgStr(MV_CESA_CRYPTO_ALG cryptoAlg) -+{ -+ switch(cryptoAlg) -+ { -+ case MV_CESA_CRYPTO_DES: -+ return "DES"; -+ -+ case MV_CESA_CRYPTO_3DES: -+ return "3DES"; -+ -+ case MV_CESA_CRYPTO_AES: -+ return "AES"; -+ -+ default: -+ break; -+ } -+ return "Null"; -+} -+ -+static const char* mvCesaDebugMacModeStr(MV_CESA_MAC_MODE macMode) -+{ -+ switch(macMode) -+ { -+ case MV_CESA_MAC_MD5: -+ return "MD5"; -+ -+ case MV_CESA_MAC_SHA1: -+ return "SHA1"; -+ -+ case MV_CESA_MAC_HMAC_MD5: -+ return "HMAC-MD5"; -+ -+ case MV_CESA_MAC_HMAC_SHA1: -+ return "HMAC_SHA1"; -+ -+ default: -+ break; -+ } -+ return "Null"; -+} -+ -+void mvCesaDebugCmd(MV_CESA_COMMAND* pCmd, int mode) -+{ -+ mvOsPrintf("pCmd=%p, pReqPrv=%p, pSrc=%p, pDst=%p, pCB=%p, sid=%d\n", -+ pCmd, pCmd->pReqPrv, pCmd->pSrc, pCmd->pDst, -+ pCmd->pFuncCB, pCmd->sessionId); -+ mvOsPrintf("isUser=%d, ivOffs=%d, crOffs=%d, crLen=%d, digest=%d, macOffs=%d, macLen=%d\n", -+ pCmd->ivFromUser, pCmd->ivOffset, pCmd->cryptoOffset, pCmd->cryptoLength, -+ pCmd->digestOffset, pCmd->macOffset, pCmd->macLength); -+} -+ -+/* no need to use in tool */ -+void mvCesaDebugMbuf(const char* str, MV_CESA_MBUF *pMbuf, int offset, int size) -+{ -+ int frag, len, fragOffset; -+ -+ if(str != NULL) -+ mvOsPrintf("%s: pMbuf=%p, numFrags=%d, mbufSize=%d\n", -+ str, pMbuf, pMbuf->numFrags, pMbuf->mbufSize); -+ -+ frag = mvCesaMbufOffset(pMbuf, offset, &fragOffset); -+ if(frag == MV_INVALID) -+ { -+ mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); -+ return; -+ } -+ -+ for(; fragnumFrags; frag++) -+ { -+ mvOsPrintf("#%2d. bufVirt=%p, bufSize=%d\n", -+ frag, pMbuf->pFrags[frag].bufVirtPtr, -+ pMbuf->pFrags[frag].bufSize); -+ if(size > 0) -+ { -+ len = MV_MIN(pMbuf->pFrags[frag].bufSize, size); -+ mvDebugMemDump(pMbuf->pFrags[frag].bufVirtPtr+fragOffset, len, 1); -+ size -= len; -+ fragOffset = 0; -+ } -+ } -+} -+ -+void mvCesaDebugRegs(void) -+{ -+ mvOsPrintf("\t CESA Registers:\n"); -+ -+ mvOsPrintf("MV_CESA_CMD_REG : 0x%X = 0x%08x\n", -+ MV_CESA_CMD_REG, -+ MV_REG_READ( MV_CESA_CMD_REG ) ); -+ -+ mvOsPrintf("MV_CESA_CHAN_DESC_OFFSET_REG : 0x%X = 0x%08x\n", -+ MV_CESA_CHAN_DESC_OFFSET_REG, -+ MV_REG_READ(MV_CESA_CHAN_DESC_OFFSET_REG) ); -+ -+ mvOsPrintf("MV_CESA_CFG_REG : 0x%X = 0x%08x\n", -+ MV_CESA_CFG_REG, -+ MV_REG_READ( MV_CESA_CFG_REG ) ); -+ -+ mvOsPrintf("MV_CESA_STATUS_REG : 0x%X = 0x%08x\n", -+ MV_CESA_STATUS_REG, -+ MV_REG_READ( MV_CESA_STATUS_REG ) ); -+ -+ mvOsPrintf("MV_CESA_ISR_CAUSE_REG : 0x%X = 0x%08x\n", -+ MV_CESA_ISR_CAUSE_REG, -+ MV_REG_READ( MV_CESA_ISR_CAUSE_REG ) ); -+ -+ mvOsPrintf("MV_CESA_ISR_MASK_REG : 0x%X = 0x%08x\n", -+ MV_CESA_ISR_MASK_REG, -+ MV_REG_READ( MV_CESA_ISR_MASK_REG ) ); -+#if (MV_CESA_VERSION >= 2) -+ mvOsPrintf("MV_CESA_TDMA_CTRL_REG : 0x%X = 0x%08x\n", -+ MV_CESA_TDMA_CTRL_REG, -+ MV_REG_READ( MV_CESA_TDMA_CTRL_REG ) ); -+ -+ mvOsPrintf("MV_CESA_TDMA_BYTE_COUNT_REG : 0x%X = 0x%08x\n", -+ MV_CESA_TDMA_BYTE_COUNT_REG, -+ MV_REG_READ( MV_CESA_TDMA_BYTE_COUNT_REG ) ); -+ -+ mvOsPrintf("MV_CESA_TDMA_SRC_ADDR_REG : 0x%X = 0x%08x\n", -+ MV_CESA_TDMA_SRC_ADDR_REG, -+ MV_REG_READ( MV_CESA_TDMA_SRC_ADDR_REG ) ); -+ -+ mvOsPrintf("MV_CESA_TDMA_DST_ADDR_REG : 0x%X = 0x%08x\n", -+ MV_CESA_TDMA_DST_ADDR_REG, -+ MV_REG_READ( MV_CESA_TDMA_DST_ADDR_REG ) ); -+ -+ mvOsPrintf("MV_CESA_TDMA_NEXT_DESC_PTR_REG : 0x%X = 0x%08x\n", -+ MV_CESA_TDMA_NEXT_DESC_PTR_REG, -+ MV_REG_READ( MV_CESA_TDMA_NEXT_DESC_PTR_REG ) ); -+ -+ mvOsPrintf("MV_CESA_TDMA_CURR_DESC_PTR_REG : 0x%X = 0x%08x\n", -+ MV_CESA_TDMA_CURR_DESC_PTR_REG, -+ MV_REG_READ( MV_CESA_TDMA_CURR_DESC_PTR_REG ) ); -+ -+ mvOsPrintf("MV_CESA_TDMA_ERROR_CAUSE_REG : 0x%X = 0x%08x\n", -+ MV_CESA_TDMA_ERROR_CAUSE_REG, -+ MV_REG_READ( MV_CESA_TDMA_ERROR_CAUSE_REG ) ); -+ -+ mvOsPrintf("MV_CESA_TDMA_ERROR_MASK_REG : 0x%X = 0x%08x\n", -+ MV_CESA_TDMA_ERROR_MASK_REG, -+ MV_REG_READ( MV_CESA_TDMA_ERROR_CAUSE_REG ) ); -+ -+#endif -+} -+ -+void mvCesaDebugStatus(void) -+{ -+ mvOsPrintf("\n\t CESA Status\n\n"); -+ -+ mvOsPrintf("pReqQ=%p, qDepth=%d, reqSize=%ld bytes, qRes=%d, ", -+ pCesaReqFirst, cesaQueueDepth, sizeof(MV_CESA_REQ), -+ cesaReqResources); -+#if (MV_CESA_VERSION >= 3) -+ mvOsPrintf("chainLength=%u\n",cesaChainLength); -+#else -+ mvOsPrintf("\n"); -+#endif -+ -+ mvOsPrintf("pSAD=%p, maxSA=%d, sizeSA=%ld bytes\n", -+ pCesaSAD, cesaMaxSA, sizeof(MV_CESA_SA)); -+ -+ mvOsPrintf("\n"); -+ -+ mvCesaDebugRegs(); -+ mvCesaDebugStats(); -+ mvCesaDebugStatsClear(); -+} -+ -+void mvCesaDebugDescriptor(MV_CESA_DESC* pDesc) -+{ -+ mvOsPrintf("config=0x%08x, crSrcOffs=0x%04x, crDstOffs=0x%04x\n", -+ pDesc->config, pDesc->cryptoSrcOffset, pDesc->cryptoDstOffset); -+ -+ mvOsPrintf("crLen=0x%04x, crKeyOffs=0x%04x, ivOffs=0x%04x, ivBufOffs=0x%04x\n", -+ pDesc->cryptoDataLen, pDesc->cryptoKeyOffset, -+ pDesc->cryptoIvOffset, pDesc->cryptoIvBufOffset); -+ -+ mvOsPrintf("macSrc=0x%04x, digest=0x%04x, macLen=0x%04x, inIv=0x%04x, outIv=0x%04x\n", -+ pDesc->macSrcOffset, pDesc->macDigestOffset, pDesc->macDataLen, -+ pDesc->macInnerIvOffset, pDesc->macOuterIvOffset); -+} -+ -+void mvCesaDebugQueue(int mode) -+{ -+ mvOsPrintf("\n\t CESA Request Queue:\n\n"); -+ -+ mvOsPrintf("pFirstReq=%p, pLastReq=%p, qDepth=%d, reqSize=%ld bytes\n", -+ pCesaReqFirst, pCesaReqLast, cesaQueueDepth, sizeof(MV_CESA_REQ)); -+ -+ mvOsPrintf("pEmpty=%p, pProcess=%p, qResources=%d\n", -+ pCesaReqEmpty, pCesaReqProcess, -+ cesaReqResources); -+ -+ if(mode != 0) -+ { -+ int count = 0; -+ MV_CESA_REQ* pReq = pCesaReqFirst; -+ -+ for(count=0; countstate), -+ pReq->fragMode, pReq->pCmd, pReq->dma[0].pDmaFirst, &pReq->pCesaDesc[0]); -+ if(pReq->fragMode != MV_CESA_FRAG_NONE) -+ { -+ int frag; -+ -+ mvOsPrintf("pFrags=%p, num=%d, next=%d, bufOffset=%d, cryptoSize=%d, macSize=%d\n", -+ &pReq->frags, pReq->frags.numFrag, pReq->frags.nextFrag, -+ pReq->frags.bufOffset, pReq->frags.cryptoSize, pReq->frags.macSize); -+ for(frag=0; fragfrags.numFrag; frag++) -+ { -+ mvOsPrintf("#%d: pDmaFirst=%p, pDesc=%p\n", frag, -+ pReq->dma[frag].pDmaFirst, &pReq->pCesaDesc[frag]); -+ } -+ } -+ if(mode > 1) -+ { -+ /* Print out Command */ -+ mvCesaDebugCmd(pReq->pCmd, mode); -+ -+ /* Print out Descriptor */ -+ mvCesaDebugDescriptor(&pReq->pCesaDesc[0]); -+ } -+ pReq++; -+ } -+ } -+} -+ -+ -+void mvCesaDebugSramSA(MV_CESA_SRAM_SA* pSramSA, int mode) -+{ -+ if(pSramSA == NULL) -+ { -+ mvOsPrintf("cesaSramSA: Unexpected pSramSA=%p\n", pSramSA); -+ return; -+ } -+ mvOsPrintf("pSramSA=%p, sizeSramSA=%ld bytes\n", -+ pSramSA, sizeof(MV_CESA_SRAM_SA)); -+ -+ if(mode != 0) -+ { -+ mvOsPrintf("cryptoKey=%p, maxCryptoKey=%d bytes\n", -+ pSramSA->cryptoKey, MV_CESA_MAX_CRYPTO_KEY_LENGTH); -+ mvDebugMemDump(pSramSA->cryptoKey, MV_CESA_MAX_CRYPTO_KEY_LENGTH, 1); -+ -+ mvOsPrintf("macInnerIV=%p, maxInnerIV=%d bytes\n", -+ pSramSA->macInnerIV, MV_CESA_MAX_DIGEST_SIZE); -+ mvDebugMemDump(pSramSA->macInnerIV, MV_CESA_MAX_DIGEST_SIZE, 1); -+ -+ mvOsPrintf("macOuterIV=%p, maxOuterIV=%d bytes\n", -+ pSramSA->macOuterIV, MV_CESA_MAX_DIGEST_SIZE); -+ mvDebugMemDump(pSramSA->macOuterIV, MV_CESA_MAX_DIGEST_SIZE, 1); -+ } -+} -+ -+void mvCesaDebugSA(short sid, int mode) -+{ -+ MV_CESA_OPERATION oper; -+ MV_CESA_DIRECTION dir; -+ MV_CESA_CRYPTO_ALG cryptoAlg; -+ MV_CESA_CRYPTO_MODE cryptoMode; -+ MV_CESA_MAC_MODE macMode; -+ MV_CESA_SA* pSA = &pCesaSAD[sid]; -+ -+ if( (pSA->valid) || ((pSA->count != 0) && (mode > 0)) || (mode >= 2) ) -+ { -+ mvOsPrintf("\n\nCESA SA Entry #%d (%p) - %s (count=%d)\n", -+ sid, pSA, -+ pSA->valid ? "Valid" : "Invalid", pSA->count); -+ -+ oper = (pSA->config & MV_CESA_OPERATION_MASK) >> MV_CESA_OPERATION_OFFSET; -+ dir = (pSA->config & MV_CESA_DIRECTION_MASK) >> MV_CESA_DIRECTION_BIT; -+ mvOsPrintf("%s - %s ", mvCesaDebugOperStr(oper), -+ (dir == MV_CESA_DIR_ENCODE) ? "Encode" : "Decode"); -+ if(oper != MV_CESA_MAC_ONLY) -+ { -+ cryptoAlg = (pSA->config & MV_CESA_CRYPTO_ALG_MASK) >> MV_CESA_CRYPTO_ALG_OFFSET; -+ cryptoMode = (pSA->config & MV_CESA_CRYPTO_MODE_MASK) >> MV_CESA_CRYPTO_MODE_BIT; -+ mvOsPrintf("- %s - %s ", mvCesaDebugCryptoAlgStr(cryptoAlg), -+ (cryptoMode == MV_CESA_CRYPTO_ECB) ? "ECB" : "CBC"); -+ } -+ if(oper != MV_CESA_CRYPTO_ONLY) -+ { -+ macMode = (pSA->config & MV_CESA_MAC_MODE_MASK) >> MV_CESA_MAC_MODE_OFFSET; -+ mvOsPrintf("- %s ", mvCesaDebugMacModeStr(macMode)); -+ } -+ mvOsPrintf("\n"); -+ -+ if(mode > 0) -+ { -+ mvOsPrintf("config=0x%08x, cryptoKeySize=%d, digestSize=%d\n", -+ pCesaSAD[sid].config, pCesaSAD[sid].cryptoKeyLength, -+ pCesaSAD[sid].digestSize); -+ -+ mvCesaDebugSramSA(pCesaSAD[sid].pSramSA, mode); -+ } -+ } -+} -+ -+ -+/**/ -+void mvCesaDebugSram(int mode) -+{ -+ mvOsPrintf("\n\t SRAM contents: size=%ld, pVirt=%p\n\n", -+ sizeof(MV_CESA_SRAM_MAP), cesaSramVirtPtr); -+ -+ mvOsPrintf("\n\t Sram buffer: size=%d, pVirt=%p\n", -+ MV_CESA_MAX_BUF_SIZE, cesaSramVirtPtr->buf); -+ if(mode != 0) -+ mvDebugMemDump(cesaSramVirtPtr->buf, 64, 1); -+ -+ mvOsPrintf("\n"); -+ mvOsPrintf("\n\t Sram descriptor: size=%ld, pVirt=%p\n", -+ sizeof(MV_CESA_DESC), &cesaSramVirtPtr->desc); -+ if(mode != 0) -+ { -+ mvOsPrintf("\n"); -+ mvCesaDebugDescriptor(&cesaSramVirtPtr->desc); -+ } -+ mvOsPrintf("\n\t Sram IV: size=%d, pVirt=%p\n", -+ MV_CESA_MAX_IV_LENGTH, &cesaSramVirtPtr->cryptoIV); -+ if(mode != 0) -+ { -+ mvOsPrintf("\n"); -+ mvDebugMemDump(cesaSramVirtPtr->cryptoIV, MV_CESA_MAX_IV_LENGTH, 1); -+ } -+ mvOsPrintf("\n"); -+ mvCesaDebugSramSA(&cesaSramVirtPtr->sramSA, 0); -+} -+ -+void mvCesaDebugSAD(int mode) -+{ -+ int sid; -+ -+ mvOsPrintf("\n\t Cesa SAD status: pSAD=%p, maxSA=%d\n", -+ pCesaSAD, cesaMaxSA); -+ -+ for(sid=0; sid= 3) -+ mvOsPrintf("maxChainUsage=%u\n",cesaStats.maxChainUsage); -+#endif -+ mvOsPrintf("\n"); -+ mvOsPrintf("proc=%u, ready=%u, notReady=%u\n", -+ cesaStats.procCount, cesaStats.readyCount, cesaStats.notReadyCount); -+} -+ -+void mvCesaDebugStatsClear(void) -+{ -+ memset(&cesaStats, 0, sizeof(cesaStats)); -+} -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/cesa/mvCesa.h linux-2.6.36/crypto/ocf/kirkwood/cesa/mvCesa.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/cesa/mvCesa.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/cesa/mvCesa.h 2010-11-09 20:28:05.737859537 +0100 -@@ -0,0 +1,412 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+/******************************************************************************* -+* mvCesa.h - Header File for Cryptographic Engines and Security Accelerator -+* -+* DESCRIPTION: -+* This header file contains macros typedefs and function declaration for -+* the Marvell Cryptographic Engines and Security Accelerator. -+* -+*******************************************************************************/ -+ -+#ifndef __mvCesa_h__ -+#define __mvCesa_h__ -+ -+#include "mvOs.h" -+#include "mvCommon.h" -+#include "mvDebug.h" -+ -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+ -+#include "cesa/mvMD5.h" -+#include "cesa/mvSHA1.h" -+ -+#include "cesa/mvCesa.h" -+#include "cesa/AES/mvAes.h" -+#include "mvSysHwConfig.h" -+ -+#ifdef MV_INCLUDE_IDMA -+#include "idma/mvIdma.h" -+#include "idma/mvIdmaRegs.h" -+#else -+/* Redefine MV_DMA_DESC structure */ -+typedef struct _mvDmaDesc -+{ -+ MV_U32 byteCnt; /* The total number of bytes to transfer */ -+ MV_U32 phySrcAdd; /* The physical source address */ -+ MV_U32 phyDestAdd; /* The physical destination address */ -+ MV_U32 phyNextDescPtr; /* If we are using chain mode DMA transfer, */ -+ /* then this pointer should point to the */ -+ /* physical address of the next descriptor, */ -+ /* otherwise it should be NULL. */ -+}MV_DMA_DESC; -+#endif /* MV_INCLUDE_IDMA */ -+ -+#include "cesa/mvCesaRegs.h" -+ -+#define MV_CESA_AUTH_BLOCK_SIZE 64 /* bytes */ -+ -+#define MV_CESA_MD5_DIGEST_SIZE 16 /* bytes */ -+#define MV_CESA_SHA1_DIGEST_SIZE 20 /* bytes */ -+ -+#define MV_CESA_MAX_DIGEST_SIZE MV_CESA_SHA1_DIGEST_SIZE -+ -+#define MV_CESA_DES_KEY_LENGTH 8 /* bytes = 64 bits */ -+#define MV_CESA_3DES_KEY_LENGTH 24 /* bytes = 192 bits */ -+#define MV_CESA_AES_128_KEY_LENGTH 16 /* bytes = 128 bits */ -+#define MV_CESA_AES_192_KEY_LENGTH 24 /* bytes = 192 bits */ -+#define MV_CESA_AES_256_KEY_LENGTH 32 /* bytes = 256 bits */ -+ -+#define MV_CESA_MAX_CRYPTO_KEY_LENGTH MV_CESA_AES_256_KEY_LENGTH -+ -+#define MV_CESA_DES_BLOCK_SIZE 8 /* bytes = 64 bits */ -+#define MV_CESA_3DES_BLOCK_SIZE 8 /* bytes = 64 bits */ -+ -+#define MV_CESA_AES_BLOCK_SIZE 16 /* bytes = 128 bits */ -+ -+#define MV_CESA_MAX_IV_LENGTH MV_CESA_AES_BLOCK_SIZE -+ -+#define MV_CESA_MAX_MAC_KEY_LENGTH 64 /* bytes */ -+ -+typedef struct -+{ -+ MV_U8 cryptoKey[MV_CESA_MAX_CRYPTO_KEY_LENGTH]; -+ MV_U8 macKey[MV_CESA_MAX_MAC_KEY_LENGTH]; -+ MV_CESA_OPERATION operation; -+ MV_CESA_DIRECTION direction; -+ MV_CESA_CRYPTO_ALG cryptoAlgorithm; -+ MV_CESA_CRYPTO_MODE cryptoMode; -+ MV_U8 cryptoKeyLength; -+ MV_CESA_MAC_MODE macMode; -+ MV_U8 macKeyLength; -+ MV_U8 digestSize; -+ -+} MV_CESA_OPEN_SESSION; -+ -+typedef struct -+{ -+ MV_BUF_INFO *pFrags; -+ MV_U16 numFrags; -+ MV_U16 mbufSize; -+ -+} MV_CESA_MBUF; -+ -+typedef struct -+{ -+ void* pReqPrv; /* instead of reqId */ -+ MV_U32 retCode; -+ MV_16 sessionId; -+ -+} MV_CESA_RESULT; -+ -+typedef void (*MV_CESA_CALLBACK) (MV_CESA_RESULT* pResult); -+ -+ -+typedef struct -+{ -+ void* pReqPrv; /* instead of reqId */ -+ MV_CESA_MBUF* pSrc; -+ MV_CESA_MBUF* pDst; -+ MV_CESA_CALLBACK* pFuncCB; -+ MV_16 sessionId; -+ MV_U16 ivFromUser; -+ MV_U16 ivOffset; -+ MV_U16 cryptoOffset; -+ MV_U16 cryptoLength; -+ MV_U16 digestOffset; -+ MV_U16 macOffset; -+ MV_U16 macLength; -+ MV_BOOL skipFlush; -+} MV_CESA_COMMAND; -+ -+ -+ -+MV_STATUS mvCesaHalInit (int numOfSession, int queueDepth, char* pSramBase, MV_U32 cryptEngBase, void *osHandle); -+MV_STATUS mvCesaFinish (void); -+MV_STATUS mvCesaSessionOpen(MV_CESA_OPEN_SESSION *pSession, short* pSid); -+MV_STATUS mvCesaSessionClose(short sid); -+MV_STATUS mvCesaCryptoIvSet(MV_U8* pIV, int ivSize); -+ -+MV_STATUS mvCesaAction (MV_CESA_COMMAND* pCmd); -+ -+MV_U32 mvCesaInProcessGet(void); -+MV_STATUS mvCesaReadyDispatch(void); -+MV_STATUS mvCesaReadyGet(MV_CESA_RESULT* pResult); -+MV_BOOL mvCesaIsReady(void); -+ -+int mvCesaMbufOffset(MV_CESA_MBUF* pMbuf, int offset, int* pBufOffset); -+MV_STATUS mvCesaCopyFromMbuf(MV_U8* pDst, MV_CESA_MBUF* pSrcMbuf, -+ int offset, int size); -+MV_STATUS mvCesaCopyToMbuf(MV_U8* pSrc, MV_CESA_MBUF* pDstMbuf, -+ int offset, int size); -+MV_STATUS mvCesaMbufCopy(MV_CESA_MBUF* pMbufDst, int dstMbufOffset, -+ MV_CESA_MBUF* pMbufSrc, int srcMbufOffset, int size); -+ -+/********** Debug functions ********/ -+ -+void mvCesaDebugMbuf(const char* str, MV_CESA_MBUF *pMbuf, int offset, int size); -+void mvCesaDebugSA(short sid, int mode); -+void mvCesaDebugStats(void); -+void mvCesaDebugStatsClear(void); -+void mvCesaDebugRegs(void); -+void mvCesaDebugStatus(void); -+void mvCesaDebugQueue(int mode); -+void mvCesaDebugSram(int mode); -+void mvCesaDebugSAD(int mode); -+ -+ -+/******** CESA Private definitions ********/ -+#if (MV_CESA_VERSION >= 2) -+#if (MV_CACHE_COHERENCY == MV_CACHE_COHER_SW) -+#define MV_CESA_TDMA_CTRL_VALUE MV_CESA_TDMA_DST_BURST_MASK(MV_CESA_TDMA_BURST_128B) \ -+ | MV_CESA_TDMA_SRC_BURST_MASK(MV_CESA_TDMA_BURST_128B) \ -+ | MV_CESA_TDMA_OUTSTAND_READ_EN_MASK \ -+ | MV_CESA_TDMA_NO_BYTE_SWAP_MASK \ -+ | MV_CESA_TDMA_ENABLE_MASK -+#else -+#define MV_CESA_TDMA_CTRL_VALUE MV_CESA_TDMA_DST_BURST_MASK(MV_CESA_TDMA_BURST_32B) \ -+ | MV_CESA_TDMA_SRC_BURST_MASK(MV_CESA_TDMA_BURST_128B) \ -+ /*| MV_CESA_TDMA_OUTSTAND_READ_EN_MASK */\ -+ | MV_CESA_TDMA_ENABLE_MASK -+ -+#endif -+#else -+#define MV_CESA_IDMA_CTRL_LOW_VALUE ICCLR_DST_BURST_LIM_128BYTE \ -+ | ICCLR_SRC_BURST_LIM_128BYTE \ -+ | ICCLR_INT_MODE_MASK \ -+ | ICCLR_BLOCK_MODE \ -+ | ICCLR_CHAN_ENABLE \ -+ | ICCLR_DESC_MODE_16M -+#endif /* MV_CESA_VERSION >= 2 */ -+ -+#define MV_CESA_MAX_PKT_SIZE (64 * 1024) -+#define MV_CESA_MAX_MBUF_FRAGS 20 -+ -+#define MV_CESA_MAX_REQ_FRAGS ( (MV_CESA_MAX_PKT_SIZE / MV_CESA_MAX_BUF_SIZE) + 1) -+ -+#define MV_CESA_MAX_DMA_DESC (MV_CESA_MAX_MBUF_FRAGS*2 + 5) -+ -+#define MAX_CESA_CHAIN_LENGTH 20 -+ -+typedef enum -+{ -+ MV_CESA_IDLE = 0, -+ MV_CESA_PENDING, -+ MV_CESA_PROCESS, -+ MV_CESA_READY, -+#if (MV_CESA_VERSION >= 3) -+ MV_CESA_CHAIN, -+#endif -+} MV_CESA_STATE; -+ -+ -+/* Session database */ -+ -+/* Map of Key materials of the session in SRAM. -+ * Each field must be 8 byte aligned -+ * Total size: 32 + 24 + 24 = 80 bytes -+ */ -+typedef struct -+{ -+ MV_U8 cryptoKey[MV_CESA_MAX_CRYPTO_KEY_LENGTH]; -+ MV_U8 macInnerIV[MV_CESA_MAX_DIGEST_SIZE]; -+ MV_U8 reservedInner[4]; -+ MV_U8 macOuterIV[MV_CESA_MAX_DIGEST_SIZE]; -+ MV_U8 reservedOuter[4]; -+ -+} MV_CESA_SRAM_SA; -+ -+typedef struct -+{ -+ MV_CESA_SRAM_SA* pSramSA; -+ MV_U32 config; -+ MV_U8 cryptoKeyLength; -+ MV_U8 cryptoIvSize; -+ MV_U8 cryptoBlockSize; -+ MV_U8 digestSize; -+ MV_U8 macKeyLength; -+ MV_U8 valid; -+ MV_U8 ctrMode; -+ MV_U32 count; -+ -+} MV_CESA_SA; -+ -+/* DMA list management */ -+typedef struct -+{ -+ MV_DMA_DESC* pDmaFirst; -+ MV_DMA_DESC* pDmaLast; -+ -+} MV_CESA_DMA; -+ -+ -+typedef struct -+{ -+ MV_U8 numFrag; -+ MV_U8 nextFrag; -+ int bufOffset; -+ int cryptoSize; -+ int macSize; -+ int newDigestOffset; -+ MV_U8 orgDigest[MV_CESA_MAX_DIGEST_SIZE]; -+ -+} MV_CESA_FRAGS; -+ -+/* Request queue */ -+typedef struct -+{ -+ MV_U8 state; -+ MV_U8 fragMode; -+ MV_U8 fixOffset; -+ MV_CESA_COMMAND* pCmd; -+ MV_CESA_COMMAND* pOrgCmd; -+ MV_BUF_INFO dmaDescBuf; -+ MV_CESA_DMA dma[MV_CESA_MAX_REQ_FRAGS]; -+ MV_BUF_INFO cesaDescBuf; -+ MV_CESA_DESC* pCesaDesc; -+ MV_CESA_FRAGS frags; -+ -+ -+} MV_CESA_REQ; -+ -+ -+/* SRAM map */ -+/* Total SRAM size calculation */ -+/* SRAM size = -+ * MV_CESA_MAX_BUF_SIZE + -+ * sizeof(MV_CESA_DESC) + -+ * MV_CESA_MAX_IV_LENGTH + -+ * MV_CESA_MAX_IV_LENGTH + -+ * MV_CESA_MAX_DIGEST_SIZE + -+ * sizeof(MV_CESA_SRAM_SA) -+ * = 1600 + 32 + 16 + 16 + 24 + 80 + 280 (reserved) = 2048 bytes -+ * = 3200 + 32 + 16 + 16 + 24 + 80 + 728 (reserved) = 4096 bytes -+ */ -+typedef struct -+{ -+ MV_U8 buf[MV_CESA_MAX_BUF_SIZE]; -+ MV_CESA_DESC desc; -+ MV_U8 cryptoIV[MV_CESA_MAX_IV_LENGTH]; -+ MV_U8 tempCryptoIV[MV_CESA_MAX_IV_LENGTH]; -+ MV_U8 tempDigest[MV_CESA_MAX_DIGEST_SIZE+4]; -+ MV_CESA_SRAM_SA sramSA; -+ -+} MV_CESA_SRAM_MAP; -+ -+ -+typedef struct -+{ -+ MV_U32 openedCount; -+ MV_U32 closedCount; -+ MV_U32 fragCount; -+ MV_U32 reqCount; -+ MV_U32 maxReqCount; -+ MV_U32 procCount; -+ MV_U32 readyCount; -+ MV_U32 notReadyCount; -+ MV_U32 startCount; -+#if (MV_CESA_VERSION >= 3) -+ MV_U32 maxChainUsage; -+#endif -+ -+} MV_CESA_STATS; -+ -+ -+/* External variables */ -+ -+extern MV_CESA_STATS cesaStats; -+extern MV_CESA_FRAGS cesaFrags; -+ -+extern MV_BUF_INFO cesaSramSaBuf; -+ -+extern MV_CESA_SA* pCesaSAD; -+extern MV_U16 cesaMaxSA; -+ -+extern MV_CESA_REQ* pCesaReqFirst; -+extern MV_CESA_REQ* pCesaReqLast; -+extern MV_CESA_REQ* pCesaReqEmpty; -+extern MV_CESA_REQ* pCesaReqProcess; -+extern int cesaQueueDepth; -+extern int cesaReqResources; -+#if (MV_CESA_VERSION>= 3) -+extern MV_U32 cesaChainLength; -+#endif -+ -+extern MV_CESA_SRAM_MAP* cesaSramVirtPtr; -+extern MV_U32 cesaSramPhysAddr; -+ -+static INLINE MV_ULONG mvCesaVirtToPhys(MV_BUF_INFO* pBufInfo, void* pVirt) -+{ -+ return (pBufInfo->bufPhysAddr + ((MV_U8*)pVirt - pBufInfo->bufVirtPtr)); -+} -+ -+/* Additional DEBUG functions */ -+void mvCesaDebugSramSA(MV_CESA_SRAM_SA* pSramSA, int mode); -+void mvCesaDebugCmd(MV_CESA_COMMAND* pCmd, int mode); -+void mvCesaDebugDescriptor(MV_CESA_DESC* pDesc); -+ -+ -+ -+#endif /* __mvCesa_h__ */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/cesa/mvCesaRegs.h linux-2.6.36/crypto/ocf/kirkwood/cesa/mvCesaRegs.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/cesa/mvCesaRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/cesa/mvCesaRegs.h 2010-11-09 20:28:05.772495441 +0100 -@@ -0,0 +1,357 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __mvCesaRegs_h__ -+#define __mvCesaRegs_h__ -+ -+#include "mvTypes.h" -+ -+typedef struct -+{ -+ /* word 0 */ -+ MV_U32 config; -+ /* word 1 */ -+ MV_U16 cryptoSrcOffset; -+ MV_U16 cryptoDstOffset; -+ /* word 2 */ -+ MV_U16 cryptoDataLen; -+ MV_U16 reserved1; -+ /* word 3 */ -+ MV_U16 cryptoKeyOffset; -+ MV_U16 reserved2; -+ /* word 4 */ -+ MV_U16 cryptoIvOffset; -+ MV_U16 cryptoIvBufOffset; -+ /* word 5 */ -+ MV_U16 macSrcOffset; -+ MV_U16 macTotalLen; -+ /* word 6 */ -+ MV_U16 macDigestOffset; -+ MV_U16 macDataLen; -+ /* word 7 */ -+ MV_U16 macInnerIvOffset; -+ MV_U16 macOuterIvOffset; -+ -+} MV_CESA_DESC; -+ -+/* operation */ -+typedef enum -+{ -+ MV_CESA_MAC_ONLY = 0, -+ MV_CESA_CRYPTO_ONLY = 1, -+ MV_CESA_MAC_THEN_CRYPTO = 2, -+ MV_CESA_CRYPTO_THEN_MAC = 3, -+ -+ MV_CESA_MAX_OPERATION -+ -+} MV_CESA_OPERATION; -+ -+#define MV_CESA_OPERATION_OFFSET 0 -+#define MV_CESA_OPERATION_MASK (0x3 << MV_CESA_OPERATION_OFFSET) -+ -+/* mac algorithm */ -+typedef enum -+{ -+ MV_CESA_MAC_NULL = 0, -+ MV_CESA_MAC_MD5 = 4, -+ MV_CESA_MAC_SHA1 = 5, -+ MV_CESA_MAC_HMAC_MD5 = 6, -+ MV_CESA_MAC_HMAC_SHA1 = 7, -+ -+} MV_CESA_MAC_MODE; -+ -+#define MV_CESA_MAC_MODE_OFFSET 4 -+#define MV_CESA_MAC_MODE_MASK (0x7 << MV_CESA_MAC_MODE_OFFSET) -+ -+typedef enum -+{ -+ MV_CESA_MAC_DIGEST_FULL = 0, -+ MV_CESA_MAC_DIGEST_96B = 1, -+ -+} MV_CESA_MAC_DIGEST_SIZE; -+ -+#define MV_CESA_MAC_DIGEST_SIZE_BIT 7 -+#define MV_CESA_MAC_DIGEST_SIZE_MASK (1 << MV_CESA_MAC_DIGEST_SIZE_BIT) -+ -+ -+typedef enum -+{ -+ MV_CESA_CRYPTO_NULL = 0, -+ MV_CESA_CRYPTO_DES = 1, -+ MV_CESA_CRYPTO_3DES = 2, -+ MV_CESA_CRYPTO_AES = 3, -+ -+} MV_CESA_CRYPTO_ALG; -+ -+#define MV_CESA_CRYPTO_ALG_OFFSET 8 -+#define MV_CESA_CRYPTO_ALG_MASK (0x3 << MV_CESA_CRYPTO_ALG_OFFSET) -+ -+ -+/* direction */ -+typedef enum -+{ -+ MV_CESA_DIR_ENCODE = 0, -+ MV_CESA_DIR_DECODE = 1, -+ -+} MV_CESA_DIRECTION; -+ -+#define MV_CESA_DIRECTION_BIT 12 -+#define MV_CESA_DIRECTION_MASK (1 << MV_CESA_DIRECTION_BIT) -+ -+/* crypto IV mode */ -+typedef enum -+{ -+ MV_CESA_CRYPTO_ECB = 0, -+ MV_CESA_CRYPTO_CBC = 1, -+ -+ /* NO HW Support */ -+ MV_CESA_CRYPTO_CTR = 10, -+ -+} MV_CESA_CRYPTO_MODE; -+ -+#define MV_CESA_CRYPTO_MODE_BIT 16 -+#define MV_CESA_CRYPTO_MODE_MASK (1 << MV_CESA_CRYPTO_MODE_BIT) -+ -+/* 3DES mode */ -+typedef enum -+{ -+ MV_CESA_CRYPTO_3DES_EEE = 0, -+ MV_CESA_CRYPTO_3DES_EDE = 1, -+ -+} MV_CESA_CRYPTO_3DES_MODE; -+ -+#define MV_CESA_CRYPTO_3DES_MODE_BIT 20 -+#define MV_CESA_CRYPTO_3DES_MODE_MASK (1 << MV_CESA_CRYPTO_3DES_MODE_BIT) -+ -+ -+/* AES Key Length */ -+typedef enum -+{ -+ MV_CESA_CRYPTO_AES_KEY_128 = 0, -+ MV_CESA_CRYPTO_AES_KEY_192 = 1, -+ MV_CESA_CRYPTO_AES_KEY_256 = 2, -+ -+} MV_CESA_CRYPTO_AES_KEY_LEN; -+ -+#define MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET 24 -+#define MV_CESA_CRYPTO_AES_KEY_LEN_MASK (0x3 << MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET) -+ -+/* Fragmentation mode */ -+typedef enum -+{ -+ MV_CESA_FRAG_NONE = 0, -+ MV_CESA_FRAG_FIRST = 1, -+ MV_CESA_FRAG_LAST = 2, -+ MV_CESA_FRAG_MIDDLE = 3, -+ -+} MV_CESA_FRAG_MODE; -+ -+#define MV_CESA_FRAG_MODE_OFFSET 30 -+#define MV_CESA_FRAG_MODE_MASK (0x3 << MV_CESA_FRAG_MODE_OFFSET) -+/*---------------------------------------------------------------------------*/ -+ -+/********** Security Accelerator Command Register **************/ -+#define MV_CESA_CMD_REG (MV_CESA_REG_BASE + 0xE00) -+ -+#define MV_CESA_CMD_CHAN_ENABLE_BIT 0 -+#define MV_CESA_CMD_CHAN_ENABLE_MASK (1 << MV_CESA_CMD_CHAN_ENABLE_BIT) -+ -+#define MV_CESA_CMD_CHAN_DISABLE_BIT 2 -+#define MV_CESA_CMD_CHAN_DISABLE_MASK (1 << MV_CESA_CMD_CHAN_DISABLE_BIT) -+ -+/********** Security Accelerator Descriptor Pointers Register **********/ -+#define MV_CESA_CHAN_DESC_OFFSET_REG (MV_CESA_REG_BASE + 0xE04) -+ -+/********** Security Accelerator Configuration Register **********/ -+#define MV_CESA_CFG_REG (MV_CESA_REG_BASE + 0xE08) -+ -+#define MV_CESA_CFG_STOP_DIGEST_ERR_BIT 0 -+#define MV_CESA_CFG_STOP_DIGEST_ERR_MASK (1 << MV_CESA_CFG_STOP_DIGEST_ERR_BIT) -+ -+#define MV_CESA_CFG_WAIT_DMA_BIT 7 -+#define MV_CESA_CFG_WAIT_DMA_MASK (1 << MV_CESA_CFG_WAIT_DMA_BIT) -+ -+#define MV_CESA_CFG_ACT_DMA_BIT 9 -+#define MV_CESA_CFG_ACT_DMA_MASK (1 << MV_CESA_CFG_ACT_DMA_BIT) -+ -+#define MV_CESA_CFG_CHAIN_MODE_BIT 11 -+#define MV_CESA_CFG_CHAIN_MODE_MASK (1 << MV_CESA_CFG_CHAIN_MODE_BIT) -+ -+/********** Security Accelerator Status Register ***********/ -+#define MV_CESA_STATUS_REG (MV_CESA_REG_BASE + 0xE0C) -+ -+#define MV_CESA_STATUS_ACTIVE_BIT 0 -+#define MV_CESA_STATUS_ACTIVE_MASK (1 << MV_CESA_STATUS_ACTIVE_BIT) -+ -+#define MV_CESA_STATUS_DIGEST_ERR_BIT 8 -+#define MV_CESA_STATUS_DIGEST_ERR_MASK (1 << MV_CESA_STATUS_DIGEST_ERR_BIT) -+ -+ -+/* Cryptographic Engines and Security Accelerator Interrupt Cause Register */ -+#define MV_CESA_ISR_CAUSE_REG (MV_CESA_REG_BASE + 0xE20) -+ -+/* Cryptographic Engines and Security Accelerator Interrupt Mask Register */ -+#define MV_CESA_ISR_MASK_REG (MV_CESA_REG_BASE + 0xE24) -+ -+#define MV_CESA_CAUSE_AUTH_MASK (1 << 0) -+#define MV_CESA_CAUSE_DES_MASK (1 << 1) -+#define MV_CESA_CAUSE_AES_ENCR_MASK (1 << 2) -+#define MV_CESA_CAUSE_AES_DECR_MASK (1 << 3) -+#define MV_CESA_CAUSE_DES_ALL_MASK (1 << 4) -+ -+#define MV_CESA_CAUSE_ACC_BIT 5 -+#define MV_CESA_CAUSE_ACC_MASK (1 << MV_CESA_CAUSE_ACC_BIT) -+ -+#define MV_CESA_CAUSE_ACC_DMA_BIT 7 -+#define MV_CESA_CAUSE_ACC_DMA_MASK (1 << MV_CESA_CAUSE_ACC_DMA_BIT) -+#define MV_CESA_CAUSE_ACC_DMA_ALL_MASK (3 << MV_CESA_CAUSE_ACC_DMA_BIT) -+ -+#define MV_CESA_CAUSE_DMA_COMPL_BIT 9 -+#define MV_CESA_CAUSE_DMA_COMPL_MASK (1 << MV_CESA_CAUSE_DMA_COMPL_BIT) -+ -+#define MV_CESA_CAUSE_DMA_OWN_ERR_BIT 10 -+#define MV_CESA_CAUSE_DMA_OWN_ERR_MASK (1 < MV_CESA_CAUSE_DMA_OWN_ERR_BIT) -+ -+#define MV_CESA_CAUSE_DMA_CHAIN_PKT_BIT 11 -+#define MV_CESA_CAUSE_DMA_CHAIN_PKT_MASK (1 < MV_CESA_CAUSE_DMA_CHAIN_PKT_BIT) -+ -+ -+#define MV_CESA_AUTH_DATA_IN_REG (MV_CESA_REG_BASE + 0xd38) -+#define MV_CESA_AUTH_BIT_COUNT_LOW_REG (MV_CESA_REG_BASE + 0xd20) -+#define MV_CESA_AUTH_BIT_COUNT_HIGH_REG (MV_CESA_REG_BASE + 0xd24) -+ -+#define MV_CESA_AUTH_INIT_VAL_DIGEST_REG(i) (MV_CESA_REG_BASE + 0xd00 + (i<<2)) -+ -+#define MV_CESA_AUTH_INIT_VAL_DIGEST_A_REG (MV_CESA_REG_BASE + 0xd00) -+#define MV_CESA_AUTH_INIT_VAL_DIGEST_B_REG (MV_CESA_REG_BASE + 0xd04) -+#define MV_CESA_AUTH_INIT_VAL_DIGEST_C_REG (MV_CESA_REG_BASE + 0xd08) -+#define MV_CESA_AUTH_INIT_VAL_DIGEST_D_REG (MV_CESA_REG_BASE + 0xd0c) -+#define MV_CESA_AUTH_INIT_VAL_DIGEST_E_REG (MV_CESA_REG_BASE + 0xd10) -+#define MV_CESA_AUTH_COMMAND_REG (MV_CESA_REG_BASE + 0xd18) -+ -+#define MV_CESA_AUTH_ALGORITHM_BIT 0 -+#define MV_CESA_AUTH_ALGORITHM_MD5 (0< -+wait_queue_head_t cesaTest_waitq; -+spinlock_t cesaLock; -+ -+#define CESA_TEST_LOCK(flags) spin_lock_irqsave( &cesaLock, flags) -+#define CESA_TEST_UNLOCK(flags) spin_unlock_irqrestore( &cesaLock, flags); -+ -+#define CESA_TEST_WAIT_INIT() init_waitqueue_head(&cesaTest_waitq) -+#define CESA_TEST_WAKE_UP() wake_up(&cesaTest_waitq) -+#define CESA_TEST_WAIT(cond, ms) wait_event_timeout(cesaTest_waitq, (cond), msecs_to_jiffies(ms)) -+ -+#define CESA_TEST_TICK_GET() jiffies -+#define CESA_TEST_TICK_TO_MS(tick) jiffies_to_msecs(tick) -+ -+#elif defined(MV_NETBSD) -+ -+#include -+#include -+static int cesaLock; -+ -+#define CESA_TEST_LOCK(flags) flags = splnet() -+#define CESA_TEST_UNLOCK(flags) splx(flags) -+ -+#define CESA_TEST_WAIT_INIT() /* nothing */ -+#define CESA_TEST_WAKE_UP() wakeup(&cesaLock) -+#define CESA_TEST_WAIT(cond, ms) \ -+do { \ -+ while (!(cond)) \ -+ tsleep(&cesaLock, PWAIT, "cesatest",mstohz(ms)); \ -+} while (/*CONSTCOND*/0) -+ -+#define CESA_TEST_TICK_GET() hardclock_ticks -+#define CESA_TEST_TICK_TO_MS(tick) ((1000/hz)*(tick)) -+ -+#define request_irq(i,h,t,n,a) \ -+ !mv_intr_establish((i),IPL_NET,(int(*)(void *))(h),(a)) -+ -+#else -+#error "Only Linux, VxWorks, or NetBSD OS are supported" -+#endif -+ -+#include "mvDebug.h" -+ -+#include "mvSysHwConfig.h" -+#include "boardEnv/mvBoardEnvLib.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+#include "cntmr/mvCntmr.h" -+#include "cesa/mvCesa.h" -+#include "cesa/mvCesaRegs.h" -+#include "cesa/mvMD5.h" -+#include "cesa/mvSHA1.h" -+ -+#if defined(CONFIG_MV646xx) -+#include "marvell_pic.h" -+#endif -+ -+#define MV_CESA_USE_TIMER_ID 0 -+#define CESA_DEF_BUF_SIZE 1500 -+#define CESA_DEF_BUF_NUM 1 -+#define CESA_DEF_SESSION_NUM 32 -+ -+#define CESA_DEF_ITER_NUM 100 -+ -+#define CESA_DEF_REQ_SIZE 256 -+ -+ -+/* CESA Tests Debug */ -+#undef CESA_TEST_DEBUG -+ -+#ifdef CESA_TEST_DEBUG -+ -+# define CESA_TEST_DEBUG_PRINT(msg) mvOsPrintf msg -+# define CESA_TEST_DEBUG_CODE(code) code -+ -+typedef struct -+{ -+ int type; /* 0 - isrEmpty, 1 - cesaReadyGet, 2 - cesaAction */ -+ MV_U32 timeStamp; -+ MV_U32 cause; -+ MV_U32 realCause; -+ MV_U32 dmaCause; -+ int resources; -+ MV_CESA_REQ* pReqReady; -+ MV_CESA_REQ* pReqEmpty; -+ MV_CESA_REQ* pReqProcess; -+} MV_CESA_TEST_TRACE; -+ -+#define MV_CESA_TEST_TRACE_SIZE 25 -+ -+static int cesaTestTraceIdx = 0; -+static MV_CESA_TEST_TRACE cesaTestTrace[MV_CESA_TEST_TRACE_SIZE]; -+ -+static void cesaTestTraceAdd(int type, MV_U32 cause) -+{ -+ cesaTestTrace[cesaTestTraceIdx].type = type; -+ cesaTestTrace[cesaTestTraceIdx].cause = cause; -+ cesaTestTrace[cesaTestTraceIdx].realCause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); -+ cesaTestTrace[cesaTestTraceIdx].dmaCause = MV_REG_READ(IDMA_CAUSE_REG); -+ cesaTestTrace[cesaTestTraceIdx].resources = cesaReqResources; -+ cesaTestTrace[cesaTestTraceIdx].pReqReady = pCesaReqReady; -+ cesaTestTrace[cesaTestTraceIdx].pReqEmpty = pCesaReqEmpty; -+ cesaTestTrace[cesaTestTraceIdx].pReqProcess = pCesaReqProcess; -+ cesaTestTrace[cesaTestTraceIdx].timeStamp = mvCntmrRead(MV_CESA_USE_TIMER_ID); -+ cesaTestTraceIdx++; -+ if(cesaTestTraceIdx == MV_CESA_TEST_TRACE_SIZE) -+ cesaTestTraceIdx = 0; -+} -+ -+#else -+ -+# define CESA_TEST_DEBUG_PRINT(msg) -+# define CESA_TEST_DEBUG_CODE(code) -+ -+#endif /* CESA_TEST_DEBUG */ -+ -+int cesaExpReqId=0; -+int cesaCbIter=0; -+ -+int cesaIdx; -+int cesaIteration; -+int cesaRateSize; -+int cesaReqSize; -+unsigned long cesaTaskId; -+int cesaBufNum; -+int cesaBufSize; -+int cesaCheckOffset; -+int cesaCheckSize; -+int cesaCheckMode; -+int cesaTestIdx; -+int cesaCaseIdx; -+ -+ -+MV_U32 cesaTestIsrCount = 0; -+MV_U32 cesaTestIsrMissCount = 0; -+ -+MV_U32 cesaCryptoError = 0; -+MV_U32 cesaReqIdError = 0; -+MV_U32 cesaError = 0; -+ -+char* cesaHexBuffer = NULL; -+ -+char* cesaBinBuffer = NULL; -+char* cesaExpBinBuffer = NULL; -+ -+char* cesaInputHexStr = NULL; -+char* cesaOutputHexStr = NULL; -+ -+MV_BUF_INFO cesaReqBufs[CESA_DEF_REQ_SIZE]; -+ -+MV_CESA_COMMAND* cesaCmdRing; -+MV_CESA_RESULT cesaResult; -+ -+int cesaTestFull = 0; -+ -+MV_BOOL cesaIsReady = MV_FALSE; -+MV_U32 cesaCycles = 0; -+MV_U32 cesaBeginTicks = 0; -+MV_U32 cesaEndTicks = 0; -+MV_U32 cesaRate = 0; -+MV_U32 cesaRateAfterDot = 0; -+ -+void *cesaTestOSHandle = NULL; -+ -+enum -+{ -+ CESA_FAST_CHECK_MODE = 0, -+ CESA_FULL_CHECK_MODE, -+ CESA_NULL_CHECK_MODE, -+ CESA_SHOW_CHECK_MODE, -+ CESA_SW_SHOW_CHECK_MODE, -+ CESA_SW_NULL_CHECK_MODE, -+ -+ CESA_MAX_CHECK_MODE -+}; -+ -+enum -+{ -+ DES_TEST_TYPE = 0, -+ TRIPLE_DES_TEST_TYPE = 1, -+ AES_TEST_TYPE = 2, -+ MD5_TEST_TYPE = 3, -+ SHA_TEST_TYPE = 4, -+ COMBINED_TEST_TYPE = 5, -+ -+ MAX_TEST_TYPE -+}; -+ -+/* Tests data base */ -+typedef struct -+{ -+ short sid; -+ char cryptoAlgorithm; /* DES/3DES/AES */ -+ char cryptoMode; /* ECB or CBC */ -+ char macAlgorithm; /* MD5 / SHA1 */ -+ char operation; /* CRYPTO/HMAC/CRYPTO+HMAC/HMAC+CRYPTO */ -+ char direction; /* ENCODE(SIGN)/DECODE(VERIFY) */ -+ unsigned char* pCryptoKey; -+ int cryptoKeySize; -+ unsigned char* pMacKey; -+ int macKeySize; -+ const char* name; -+ -+} MV_CESA_TEST_SESSION; -+ -+typedef struct -+{ -+ MV_CESA_TEST_SESSION* pSessions; -+ int numSessions; -+ -+} MV_CESA_TEST_DB_ENTRY; -+ -+typedef struct -+{ -+ char* plainHexStr; -+ char* cipherHexStr; -+ unsigned char* pCryptoIV; -+ int cryptoLength; -+ int macLength; -+ int digestOffset; -+ -+} MV_CESA_TEST_CASE; -+ -+typedef struct -+{ -+ int size; -+ const char* outputHexStr; -+ -+} MV_CESA_SIZE_TEST; -+ -+static unsigned char cryptoKey1[] = {0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, -+ 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, -+ 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef}; -+ -+static unsigned char cryptoKey7[] = {0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef}; -+static unsigned char iv1[] = {0x12, 0x34, 0x56, 0x78, 0x90, 0xab, 0xcd, 0xef}; -+ -+ -+static unsigned char cryptoKey2[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, -+ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F}; -+ -+static unsigned char cryptoKey3[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, -+ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, -+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17}; -+ -+static unsigned char cryptoKey4[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, -+ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, -+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, -+ 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f}; -+ -+static unsigned char cryptoKey5[] = {0x56, 0xe4, 0x7a, 0x38, 0xc5, 0x59, 0x89, 0x74, -+ 0xbc, 0x46, 0x90, 0x3d, 0xba, 0x29, 0x03, 0x49}; -+ -+ -+static unsigned char key3des1[] = {0x01, 0x23, 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF, -+ 0x23, 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF, 0x01, -+ 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF, 0x01, 0x23}; -+ -+/* Input ASCII string: The quick brown fox jump */ -+static char plain3des1[] = "54686520717566636B2062726F776E20666F78206A756D70"; -+static char cipher3des1[] = "A826FD8CE53B855FCCE21C8112256FE668D5C05DD9B6B900"; -+ -+static unsigned char key3des2[] = {0x62, 0x7f, 0x46, 0x0e, 0x08, 0x10, 0x4a, 0x10, -+ 0x43, 0xcd, 0x26, 0x5d, 0x58, 0x40, 0xea, 0xf1, -+ 0x31, 0x3e, 0xdf, 0x97, 0xdf, 0x2a, 0x8a, 0x8c}; -+ -+static unsigned char iv3des2[] = {0x8e, 0x29, 0xf7, 0x5e, 0xa7, 0x7e, 0x54, 0x75}; -+ -+static char plain3des2[] = "326a494cd33fe756"; -+ -+static char cipher3desCbc2[] = "8e29f75ea77e5475" -+ "b22b8d66de970692"; -+ -+static unsigned char key3des3[] = {0x37, 0xae, 0x5e, 0xbf, 0x46, 0xdf, 0xf2, 0xdc, -+ 0x07, 0x54, 0xb9, 0x4f, 0x31, 0xcb, 0xb3, 0x85, -+ 0x5e, 0x7f, 0xd3, 0x6d, 0xc8, 0x70, 0xbf, 0xae}; -+ -+static unsigned char iv3des3[] = {0x3d, 0x1d, 0xe3, 0xcc, 0x13, 0x2e, 0x3b, 0x65}; -+ -+static char plain3des3[] = "84401f78fe6c10876d8ea23094ea5309"; -+ -+static char cipher3desCbc3[] = "3d1de3cc132e3b65" -+ "7b1f7c7e3b1c948ebd04a75ffba7d2f5"; -+ -+static unsigned char iv5[] = {0x8c, 0xe8, 0x2e, 0xef, 0xbe, 0xa0, 0xda, 0x3c, -+ 0x44, 0x69, 0x9e, 0xd7, 0xdb, 0x51, 0xb7, 0xd9}; -+ -+static unsigned char aesCtrKey[] = {0x76, 0x91, 0xBE, 0x03, 0x5E, 0x50, 0x20, 0xA8, -+ 0xAC, 0x6E, 0x61, 0x85, 0x29, 0xF9, 0xA0, 0xDC}; -+ -+static unsigned char mdKey1[] = {0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, -+ 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b}; -+ -+static unsigned char mdKey2[] = {0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -+ 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa}; -+ -+static unsigned char shaKey1[] = {0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, -+ 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, -+ 0x0b, 0x0b, 0x0b, 0x0b}; -+ -+static unsigned char shaKey2[] = {0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -+ 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -+ 0xaa, 0xaa, 0xaa, 0xaa}; -+ -+static unsigned char mdKey4[] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10}; -+ -+static unsigned char shaKey4[] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10, -+ 0x11, 0x12, 0x13, 0x14}; -+ -+ -+static MV_CESA_TEST_SESSION desTestSessions[] = -+{ -+/*000*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey7, sizeof(cryptoKey7)/sizeof(cryptoKey7[0]), -+ NULL, 0, -+ "DES ECB encode", -+ }, -+/*001*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_DECODE, -+ cryptoKey7, sizeof(cryptoKey7)/sizeof(cryptoKey7[0]), -+ NULL, 0, -+ "DES ECB decode", -+ }, -+/*002*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey7, sizeof(cryptoKey7)/sizeof(cryptoKey7[0]), -+ NULL, 0, -+ "DES CBC encode" -+ }, -+/*003*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_DECODE, -+ cryptoKey7, sizeof(cryptoKey7)/sizeof(cryptoKey7[0]), -+ NULL, 0, -+ "DES CBC decode" -+ }, -+/*004*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, NULL, 0, -+ "NULL Crypto Algorithm encode" -+ }, -+}; -+ -+ -+static MV_CESA_TEST_SESSION tripleDesTestSessions[] = -+{ -+/*100*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ NULL, 0, -+ "3DES ECB encode", -+ }, -+/*101*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_DECODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ NULL, 0, -+ "3DES ECB decode", -+ }, -+/*102*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ NULL, 0, -+ "3DES CBC encode" -+ }, -+/*103*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_DECODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ NULL, 0, -+ "3DES CBC decode" -+ }, -+/*104*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ key3des1, sizeof(key3des1), -+ NULL, 0, -+ "3DES ECB encode" -+ }, -+/*105*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ key3des2, sizeof(key3des2), -+ NULL, 0, -+ "3DES ECB encode" -+ }, -+/*106*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ key3des3, sizeof(key3des3), -+ NULL, 0, -+ "3DES ECB encode" -+ }, -+}; -+ -+ -+static MV_CESA_TEST_SESSION aesTestSessions[] = -+{ -+/*200*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey2, sizeof(cryptoKey2)/sizeof(cryptoKey2[0]), -+ NULL, 0, -+ "AES-128 ECB encode" -+ }, -+/*201*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_DECODE, -+ cryptoKey2, sizeof(cryptoKey2)/sizeof(cryptoKey2[0]), -+ NULL, 0, -+ "AES-128 ECB decode" -+ }, -+/*202*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey5, sizeof(cryptoKey5)/sizeof(cryptoKey5[0]), -+ NULL, 0, -+ "AES-128 CBC encode" -+ }, -+/*203*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_DECODE, -+ cryptoKey5, sizeof(cryptoKey5)/sizeof(cryptoKey5[0]), -+ NULL, 0, -+ "AES-128 CBC decode" -+ }, -+/*204*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey3, sizeof(cryptoKey3)/sizeof(cryptoKey3[0]), -+ NULL, 0, -+ "AES-192 ECB encode" -+ }, -+/*205*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_DECODE, -+ cryptoKey3, sizeof(cryptoKey3)/sizeof(cryptoKey3[0]), -+ NULL, 0, -+ "AES-192 ECB decode" -+ }, -+/*206*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey4, sizeof(cryptoKey4)/sizeof(cryptoKey4[0]), -+ NULL, 0, -+ "AES-256 ECB encode" -+ }, -+/*207*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_DECODE, -+ cryptoKey4, sizeof(cryptoKey4)/sizeof(cryptoKey4[0]), -+ NULL, 0, -+ "AES-256 ECB decode" -+ }, -+/*208*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CTR, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ aesCtrKey, sizeof(aesCtrKey)/sizeof(aesCtrKey[0]), -+ NULL, 0, -+ "AES-128 CTR encode" -+ }, -+}; -+ -+ -+static MV_CESA_TEST_SESSION md5TestSessions[] = -+{ -+/*300*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, -+ mdKey1, sizeof(mdKey1), -+ "HMAC-MD5 Generate Signature" -+ }, -+/*301*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_DECODE, -+ NULL, 0, -+ mdKey1, sizeof(mdKey1), -+ "HMAC-MD5 Verify Signature" -+ }, -+/*302*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, -+ mdKey2, sizeof(mdKey2), -+ "HMAC-MD5 Generate Signature" -+ }, -+/*303*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_DECODE, -+ NULL, 0, -+ mdKey2, sizeof(mdKey2), -+ "HMAC-MD5 Verify Signature" -+ }, -+/*304*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, -+ mdKey4, sizeof(mdKey4), -+ "HMAC-MD5 Generate Signature" -+ }, -+/*305*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_MD5, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, -+ NULL, 0, -+ "HASH-MD5 Generate Signature" -+ }, -+}; -+ -+ -+static MV_CESA_TEST_SESSION shaTestSessions[] = -+{ -+/*400*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, -+ shaKey1, sizeof(shaKey1), -+ "HMAC-SHA1 Generate Signature" -+ }, -+/*401*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_DECODE, -+ NULL, 0, -+ shaKey1, sizeof(shaKey1), -+ "HMAC-SHA1 Verify Signature" -+ }, -+/*402*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, -+ shaKey2, sizeof(shaKey2), -+ "HMAC-SHA1 Generate Signature" -+ }, -+/*403*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_DECODE, -+ NULL, 0, -+ shaKey2, sizeof(shaKey2), -+ "HMAC-SHA1 Verify Signature" -+ }, -+/*404*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, -+ shaKey4, sizeof(shaKey4), -+ "HMAC-SHA1 Generate Signature" -+ }, -+/*405*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_SHA1, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, -+ NULL, 0, -+ "HASH-SHA1 Generate Signature" -+ }, -+}; -+ -+static MV_CESA_TEST_SESSION combinedTestSessions[] = -+{ -+/*500*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey1, MV_CESA_DES_KEY_LENGTH, -+ mdKey4, sizeof(mdKey4), -+ "DES + MD5 encode" -+ }, -+/*501*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey1, MV_CESA_DES_KEY_LENGTH, -+ shaKey4, sizeof(shaKey4), -+ "DES + SHA1 encode" -+ }, -+/*502*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ mdKey4, sizeof(mdKey4), -+ "3DES + MD5 encode" -+ }, -+/*503*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ shaKey4, sizeof(shaKey4), -+ "3DES + SHA1 encode" -+ }, -+/*504*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ mdKey4, sizeof(mdKey4), -+ "3DES CBC + MD5 encode" -+ }, -+/*505*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ shaKey4, sizeof(shaKey4), -+ "3DES CBC + SHA1 encode" -+ }, -+/*506*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey5, sizeof(cryptoKey5)/sizeof(cryptoKey5[0]), -+ mdKey4, sizeof(mdKey4), -+ "AES-128 CBC + MD5 encode" -+ }, -+/*507*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey5, sizeof(cryptoKey5)/sizeof(cryptoKey5[0]), -+ shaKey4, sizeof(shaKey4), -+ "AES-128 CBC + SHA1 encode" -+ }, -+/*508*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_THEN_CRYPTO, -+ MV_CESA_DIR_DECODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ mdKey4, sizeof(mdKey4), -+ "HMAC-MD5 + 3DES decode" -+ }, -+}; -+ -+ -+static MV_CESA_TEST_DB_ENTRY cesaTestsDB[MAX_TEST_TYPE+1] = -+{ -+ { desTestSessions, sizeof(desTestSessions)/sizeof(desTestSessions[0]) }, -+ { tripleDesTestSessions, sizeof(tripleDesTestSessions)/sizeof(tripleDesTestSessions[0]) }, -+ { aesTestSessions, sizeof(aesTestSessions)/sizeof(aesTestSessions[0]) }, -+ { md5TestSessions, sizeof(md5TestSessions)/sizeof(md5TestSessions[0]) }, -+ { shaTestSessions, sizeof(shaTestSessions)/sizeof(shaTestSessions[0]) }, -+ { combinedTestSessions, sizeof(combinedTestSessions)/sizeof(combinedTestSessions[0]) }, -+ { NULL, 0 } -+}; -+ -+ -+char cesaNullPlainHexText[] = "000000000000000000000000000000000000000000000000"; -+ -+char cesaPlainAsciiText[] = "Now is the time for all "; -+char cesaPlainHexEbc[] = "4e6f77206973207468652074696d6520666f7220616c6c20"; -+char cesaCipherHexEcb[] = "3fa40e8a984d48156a271787ab8883f9893d51ec4b563b53"; -+char cesaPlainHexCbc[] = "1234567890abcdef4e6f77206973207468652074696d6520666f7220616c6c20"; -+char cesaCipherHexCbc[] = "1234567890abcdefe5c7cdde872bf27c43e934008c389c0f683788499a7c05f6"; -+ -+char cesaAesPlainHexEcb[] = "000102030405060708090a0b0c0d0e0f"; -+char cesaAes128cipherHexEcb[] = "0a940bb5416ef045f1c39458c653ea5a"; -+char cesaAes192cipherHexEcb[] = "0060bffe46834bb8da5cf9a61ff220ae"; -+char cesaAes256cipherHexEcb[] = "5a6e045708fb7196f02e553d02c3a692"; -+ -+char cesaAsciiStr1[] = "Hi There"; -+char cesaDataHexStr1[] = "4869205468657265"; -+char cesaHmacMd5digestHex1[] = "9294727a3638bb1c13f48ef8158bfc9d"; -+char cesaHmacSha1digestHex1[] = "b617318655057264e28bc0b6fb378c8ef146be00"; -+char cesaDataAndMd5digest1[] = "48692054686572659294727a3638bb1c13f48ef8158bfc9d"; -+char cesaDataAndSha1digest1[] = "4869205468657265b617318655057264e28bc0b6fb378c8ef146be00"; -+ -+char cesaAesPlainText[] = "a0a1a2a3a4a5a6a7a8a9aaabacadaeaf" -+ "b0b1b2b3b4b5b6b7b8b9babbbcbdbebf" -+ "c0c1c2c3c4c5c6c7c8c9cacbcccdcecf" -+ "d0d1d2d3d4d5d6d7d8d9dadbdcdddedf"; -+ -+char cesaAes128CipherCbc[] = "c30e32ffedc0774e6aff6af0869f71aa" -+ "0f3af07a9a31a9c684db207eb0ef8e4e" -+ "35907aa632c3ffdf868bb7b29d3d46ad" -+ "83ce9f9a102ee99d49a53e87f4c3da55"; -+ -+char cesaAesIvPlainText[] = "8ce82eefbea0da3c44699ed7db51b7d9" -+ "a0a1a2a3a4a5a6a7a8a9aaabacadaeaf" -+ "b0b1b2b3b4b5b6b7b8b9babbbcbdbebf" -+ "c0c1c2c3c4c5c6c7c8c9cacbcccdcecf" -+ "d0d1d2d3d4d5d6d7d8d9dadbdcdddedf"; -+ -+char cesaAes128IvCipherCbc[] = "8ce82eefbea0da3c44699ed7db51b7d9" -+ "c30e32ffedc0774e6aff6af0869f71aa" -+ "0f3af07a9a31a9c684db207eb0ef8e4e" -+ "35907aa632c3ffdf868bb7b29d3d46ad" -+ "83ce9f9a102ee99d49a53e87f4c3da55"; -+ -+char cesaAesCtrPlain[] = "00E0017B27777F3F4A1786F000000001" -+ "000102030405060708090A0B0C0D0E0F" -+ "101112131415161718191A1B1C1D1E1F" -+ "20212223"; -+ -+char cesaAesCtrCipher[] = "00E0017B27777F3F4A1786F000000001" -+ "C1CF48A89F2FFDD9CF4652E9EFDB72D7" -+ "4540A42BDE6D7836D59A5CEAAEF31053" -+ "25B2072F"; -+ -+ -+ -+/* Input cesaHmacHex3 is '0xdd' repeated 50 times */ -+char cesaHmacMd5digestHex3[] = "56be34521d144c88dbb8c733f0e8b3f6"; -+char cesaHmacSha1digestHex3[] = "125d7342b9ac11cd91a39af48aa17b4f63f175d3"; -+char cesaDataHexStr3[50*2+1] = ""; -+char cesaDataAndMd5digest3[sizeof(cesaDataHexStr3)+sizeof(cesaHmacMd5digestHex3)+8*2+1] = ""; -+char cesaDataAndSha1digest3[sizeof(cesaDataHexStr3)+sizeof(cesaHmacSha1digestHex3)+8*2+1] = ""; -+ -+/* Ascii string is "abc" */ -+char hashHexStr3[] = "616263"; -+char hashMd5digest3[] = "900150983cd24fb0d6963f7d28e17f72"; -+char hashSha1digest3[] = "a9993e364706816aba3e25717850c26c9cd0d89d"; -+ -+char hashHexStr80[] = "31323334353637383930" -+ "31323334353637383930" -+ "31323334353637383930" -+ "31323334353637383930" -+ "31323334353637383930" -+ "31323334353637383930" -+ "31323334353637383930" -+ "31323334353637383930"; -+ -+char hashMd5digest80[] = "57edf4a22be3c955ac49da2e2107b67a"; -+ -+char tripleDesThenMd5digest80[] = "b7726a03aad490bd6c5a452a89a1b271"; -+char tripleDesThenSha1digest80[] = "b2ddeaca91030eab5b95a234ef2c0f6e738ff883"; -+ -+char cbc3desThenMd5digest80[] = "6f463057e1a90e0e91ae505b527bcec0"; -+char cbc3desThenSha1digest80[] = "1b002ed050be743aa98860cf35659646bb8efcc0"; -+ -+char cbcAes128ThenMd5digest80[] = "6b6e863ac5a71d15e3e9b1c86c9ba05f"; -+char cbcAes128ThenSha1digest80[] = "13558472d1fc1c90dffec6e5136c7203452d509b"; -+ -+ -+static MV_CESA_TEST_CASE cesaTestCases[] = -+{ -+ /* plainHexStr cipherHexStr IV crypto mac digest */ -+ /* Length Length Offset */ -+ /*0*/ { NULL, NULL, NULL, 0, 0, -1 }, -+ /*1*/ { cesaPlainHexEbc, cesaCipherHexEcb, NULL, 24, 0, -1 }, -+ /*2*/ { cesaPlainHexCbc, cesaCipherHexCbc, NULL, 24, 0, -1 }, -+ /*3*/ { cesaAesPlainHexEcb, cesaAes128cipherHexEcb, NULL, 16, 0, -1 }, -+ /*4*/ { cesaAesPlainHexEcb, cesaAes192cipherHexEcb, NULL, 16, 0, -1 }, -+ /*5*/ { cesaAesPlainHexEcb, cesaAes256cipherHexEcb, NULL, 16, 0, -1 }, -+ /*6*/ { cesaDataHexStr1, cesaHmacMd5digestHex1, NULL, 0, 8, -1 }, -+ /*7*/ { NULL, cesaDataAndMd5digest1, NULL, 0, 8, -1 }, -+ /*8*/ { cesaDataHexStr3, cesaHmacMd5digestHex3, NULL, 0, 50, -1 }, -+ /*9*/ { NULL, cesaDataAndMd5digest3, NULL, 0, 50, -1 }, -+/*10*/ { cesaAesPlainText, cesaAes128IvCipherCbc, iv5, 64, 0, -1 }, -+/*11*/ { cesaDataHexStr1, cesaHmacSha1digestHex1, NULL, 0, 8, -1 }, -+/*12*/ { NULL, cesaDataAndSha1digest1, NULL, 0, 8, -1 }, -+/*13*/ { cesaDataHexStr3, cesaHmacSha1digestHex3, NULL, 0, 50, -1 }, -+/*14*/ { NULL, cesaDataAndSha1digest3, NULL, 0, 50, -1 }, -+/*15*/ { hashHexStr3, hashMd5digest3, NULL, 0, 3, -1 }, -+/*16*/ { hashHexStr3, hashSha1digest3, NULL, 0, 3, -1 }, -+/*17*/ { hashHexStr80, tripleDesThenMd5digest80, NULL, 80, 80, -1 }, -+/*18*/ { hashHexStr80, tripleDesThenSha1digest80, NULL, 80, 80, -1 }, -+/*19*/ { hashHexStr80, cbc3desThenMd5digest80, iv1, 80, 80, -1 }, -+/*20*/ { hashHexStr80, cbc3desThenSha1digest80, iv1, 80, 80, -1 }, -+/*21*/ { hashHexStr80, cbcAes128ThenMd5digest80, iv5, 80, 80, -1 }, -+/*22*/ { hashHexStr80, cbcAes128ThenSha1digest80, iv5, 80, 80, -1 }, -+/*23*/ { cesaAesCtrPlain, cesaAesCtrCipher, NULL, 36, 0, -1 }, -+/*24*/ { cesaAesIvPlainText, cesaAes128IvCipherCbc, NULL, 64, 0, -1 }, -+/*25*/ { plain3des1, cipher3des1, NULL, 0, 0, -1 }, -+/*26*/ { plain3des2, cipher3desCbc2, iv3des2,0, 0, -1 }, -+/*27*/ { plain3des3, cipher3desCbc3, iv3des3,0, 0, -1 }, -+}; -+ -+ -+/* Key = 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -+ * 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa -+ * Input 0xdd repeated "size" times -+ */ -+static MV_CESA_SIZE_TEST mdMultiSizeTest302[] = -+{ -+ { 80, "7a031a640c14a4872814930b1ef3a5b2" }, -+ { 512, "5488e6c5a14dc72a79f28312ca5b939b" }, -+ { 1000, "d00814f586a8b78a05724239d2531821" }, -+ { 1001, "bf07df7b7f49d3f5b5ecacd4e9e63281" }, -+ { 1002, "1ed4a1a802e87817a819d4e37bb4d0f7" }, -+ { 1003, "5972ab64a4f265ee371dac2f2f137f90" }, -+ { 1004, "71f95e7ec3aa7df2548e90898abdb28e" }, -+ { 1005, "e082790b4857fcfc266e92e59e608814" }, -+ { 1006, "9500f02fd8ac7fde8b10e4fece9a920d" }, -+ { 1336, "e42edcce57d0b75b01aa09d71427948b" }, -+ { 1344, "bb5454ada0deb49ba0a97ffd60f57071" }, -+ { 1399, "0f44d793e744b24d53f44f295082ee8c" }, -+ { 1400, "359de8a03a9b707928c6c60e0e8d79f1" }, -+ { 1401, "e913858b484cbe2b384099ea88d8855b" }, -+ { 1402, "d9848a164af53620e0540c1d7d87629e" }, -+ { 1403, "0c9ee1c2c9ef45e9b625c26cbaf3e822" }, -+ { 1404, "12edd4f609416e3c936170360561b064" }, -+ { 1405, "7fc912718a05446395345009132bf562" }, -+ { 1406, "882f17425e579ff0d85a91a59f308aa0" }, -+ { 1407, "005cae408630a2fb5db82ad9db7e59da" }, -+ { 1408, "64655f8b404b3fea7a3e3e609bc5088f" }, -+ { 1409, "4a145284a7f74e01b6bb1a0ec6a0dd80" }, -+ { 2048, "67caf64475650732def374ebb8bde3fd" }, -+ { 2049, "6c84f11f472825f7e6cd125c2981884b" }, -+ { 2050, "8999586754a73a99efbe4dbad2816d41" }, -+ { 2051, "ba6946b610e098d286bc81091659dfff" }, -+ { 2052, "d0afa01c92d4d13def2b024f36faed83" }, -+ { 3072, "61d8beac61806afa2585d74a9a0e6974" }, -+ { 3074, "f6501a28dcc24d1e4770505c51a87ed3" }, -+ { 3075, "ea4a6929be67e33e61ff475369248b73" }, -+ { 4048, "aa8c4d68f282a07e7385acdfa69f4bed" }, -+ { 4052, "afb5ed2c0e1d430ea59e59ed5ed6b18a" }, -+ { 4058, "9e8553f9bdd43aebe0bd729f0e600c99" }, -+ { 6144, "f628f3e5d183fe5cdd3a5abee39cf872" }, -+ { 6150, "89a3efcea9a2f25f919168ad4a1fd292" }, -+ { 6400, "cdd176b7fb747873efa4da5e32bdf88f" }, -+ { 6528, "b1d707b027354aca152c45ee559ccd3f" }, -+ { 8192, "c600ea4429ac47f9941f09182166e51a" }, -+ {16384, "16e8754bfbeb4c649218422792267a37" }, -+ {18432, "0fd0607521b0aa8b52219cfbe215f63e" }, -+ { 0, NULL }, -+}; -+ -+/* Key = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ */ -+static MV_CESA_SIZE_TEST mdMultiSizeTest304[] = -+{ -+ { 80, "a456c4723fee6068530af5a2afa71627" }, -+ { 512, "f85c2a2344f5de68b432208ad13e5794" }, -+ { 1000, "35464d6821fd4a293a41eb84e274c8c5" }, -+ { 1001, "c08eedbdce60cceb54bc2d732bb32c8b" }, -+ { 1002, "5664f71800c011cc311cb6943339c1b8" }, -+ { 1003, "779c723b044c585dc7802b13e8501bdc" }, -+ { 1004, "55e500766a2c307bc5c5fdd15e4cacd4" }, -+ { 1005, "d5f978954f5c38529d1679d2b714f068" }, -+ { 1006, "cd3efc827ce628b7281b72172693abf9" }, -+ { 1336, "6f04479910785878ae6335b8d1e87edf" }, -+ { 1344, "b6d27b50c2bce1ba2a8e1b5cc4324368" }, -+ { 1399, "65f70a1d4c86e5eaeb0704c8a7816795" }, -+ { 1400, "3394b5adc4cb3ff98843ca260a44a88a" }, -+ { 1401, "3a06f3582033a66a4e57e0603ce94e74" }, -+ { 1402, "e4d97f5ed51edc48abfa46eeb5c31752" }, -+ { 1403, "3d05e40b080ee3bedf293cb87b7140e7" }, -+ { 1404, "8cf294fc3cd153ab18dccb2a52cbf244" }, -+ { 1405, "d1487bd42f6edd9b4dab316631159221" }, -+ { 1406, "0527123b6bf6936cf5d369dc18c6c70f" }, -+ { 1407, "3224a06639db70212a0cd1ae1fcc570a" }, -+ { 1408, "a9e13335612c0356f5e2c27086e86c43" }, -+ { 1409, "a86d1f37d1ed8a3552e9a4f04dceea98" }, -+ { 2048, "396905c9b961cd0f6152abfb69c4449c" }, -+ { 2049, "49f39bff85d9dcf059fadb89efc4a70f" }, -+ { 2050, "3a2b4823bc4d0415656550226a63e34a" }, -+ { 2051, "dec60580d406c782540f398ad0bcc7e0" }, -+ { 2052, "32f76610a14310309eb748fe025081bf" }, -+ { 3072, "45edc1a42bf9d708a621076b63b774da" }, -+ { 3074, "9be1b333fe7c0c9f835fb369dc45f778" }, -+ { 3075, "8c06fcac7bd0e7b7a17fd6508c09a549" }, -+ { 4048, "0ddaef848184bf0ad98507a10f1e90e4" }, -+ { 4052, "81976bcaeb274223983996c137875cb8" }, -+ { 4058, "0b0a7a1c82bc7cbc64d8b7cd2dc2bb22" }, -+ { 6144, "1c24056f52725ede2dff0d7f9fc9855f" }, -+ { 6150, "b7f4b65681c4e43ee68ca466ca9ca4ec" }, -+ { 6400, "443bbaab9f7331ddd4bf11b659cd43c8" }, -+ { 6528, "216f44f23047cfee03a7a64f88f9a995" }, -+ { 8192, "ac7a993b2cad54879dba1bde63e39097" }, -+ { 8320, "55ed7be9682d6c0025b3221a62088d08" }, -+ {16384, "c6c722087653b62007aea668277175e5" }, -+ {18432, "f1faca8e907872c809e14ffbd85792d6" }, -+ { 0, NULL }, -+}; -+ -+/* HASH-MD5 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ * repeated "size" times -+ */ -+static MV_CESA_SIZE_TEST mdMultiSizeTest305[] = -+{ -+ { 80, "57edf4a22be3c955ac49da2e2107b67a" }, -+ { 512, "c729ae8f0736cc377a9767a660eaa04e" }, -+ { 1000, "f1257a8659eb92d36fe14c6bf3852a6a" }, -+ { 1001, "f8a46fe8ea04fdc8c7de0e84042d3878" }, -+ { 1002, "da188dd67bff87d58aa3c02af2d0cc0f" }, -+ { 1003, "961753017feee04c9b93a8e51658a829" }, -+ { 1004, "dd68c4338608dcc87807a711636bf2af" }, -+ { 1005, "e338d567d3ce66bf69ada29658a8759b" }, -+ { 1006, "443c9811e8b92599b0b149e8d7ec700a" }, -+ { 1336, "89a98511706008ba4cbd0b4a24fa5646" }, -+ { 1344, "335a919805f370b9e402a62c6fe01739" }, -+ { 1399, "5d18d0eddcd84212fe28d812b5e80e3b" }, -+ { 1400, "6b695c240d2dffd0dffc99459ca76db6" }, -+ { 1401, "49590f61298a76719bc93a57a30136f5" }, -+ { 1402, "94c2999fa3ef1910a683d69b2b8476f2" }, -+ { 1403, "37073a02ab00ecba2645c57c228860db" }, -+ { 1404, "1bcd06994fce28b624f0c5fdc2dcdd2b" }, -+ { 1405, "11b93671a64c95079e8cf9e7cddc8b3d" }, -+ { 1406, "4b6695772a4c66313fa4871017d05f36" }, -+ { 1407, "d1539b97fbfda1c075624e958de19c5b" }, -+ { 1408, "b801b9b69920907cd018e8063092ede9" }, -+ { 1409, "b765f1406cfe78e238273ed01bbcaf7e" }, -+ { 2048, "1d7e2c64ac29e2b3fb4c272844ed31f5" }, -+ { 2049, "71d38fac49c6b1f4478d8d88447bcdd0" }, -+ { 2050, "141c34a5592b1bebfa731e0b23d0cdba" }, -+ { 2051, "c5e1853f21c59f5d6039bd13d4b380d8" }, -+ { 2052, "dd44a0d128b63d4b5cccd967906472d7" }, -+ { 3072, "37d158e33b21390822739d13db7b87fe" }, -+ { 3074, "aef3b209d01d39d0597fe03634bbf441" }, -+ { 3075, "335ffb428eabf210bada96d74d5a4012" }, -+ { 4048, "2434c2b43d798d2819487a886261fc64" }, -+ { 4052, "ac2fa84a8a33065b2e92e36432e861f8" }, -+ { 4058, "856781f85616c341c3533d090c1e1e84" }, -+ { 6144, "e5d134c652c18bf19833e115f7a82e9b" }, -+ { 6150, "a09a353be7795fac2401dac5601872e6" }, -+ { 6400, "08b9033ac6a1821398f50af75a2dbc83" }, -+ { 6528, "3d47aa193a8540c091e7e02f779e6751" }, -+ { 8192, "d3164e710c0626f6f395b38f20141cb7" }, -+ { 8320, "b727589d9183ff4e8491dd24466974a3" }, -+ {16384, "3f54d970793d2274d5b20d10a69938ac" }, -+ {18432, "f558511dcf81985b7a1bb57fad970531" }, -+ { 0, NULL }, -+}; -+ -+ -+/* Key = 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -+ * 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa -+ * 0xaa, 0xaa, 0xaa, 0xaa -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ */ -+static MV_CESA_SIZE_TEST shaMultiSizeTest402[] = -+{ -+ { 80, "e812f370e659705a1649940d1f78cd7af18affd3" }, -+ { 512, "e547f886b2c15d995ed76a8a924cb408c8080f66" }, -+ { 1000, "239443194409f1a5342ecde1a092c8f3a3ed790a" }, -+ { 1001, "f278ab9a102850a9f48dc4e9e6822afe2d0c52b5" }, -+ { 1002, "8bcc667df5ab6ece988b3af361d09747c77f4e72" }, -+ { 1003, "0fae6046c7dc1d3e356b25af836f6077a363f338" }, -+ { 1004, "0ea48401cc92ae6bc92ae76685269cb0167fbe1a" }, -+ { 1005, "ecbcd7c879b295bafcd8766cbeac58cc371e31d1" }, -+ { 1006, "eb4a4a3d07d1e9a15e6f1ab8a9c47f243e27324c" }, -+ { 1336, "f5950ee1d77c10e9011d2149699c9366fe52529c" }, -+ { 1344, "b04263604a63c351b0b3b9cf1785b4bdba6c8838" }, -+ { 1399, "8cb1cff61d5b784045974a2fc69386e3b8d24218" }, -+ { 1400, "9bb2f3fcbeddb2b90f0be797cd647334a2816d51" }, -+ { 1401, "23ae462a7a0cb440f7445791079a5d75a535dd33" }, -+ { 1402, "832974b524a4d3f9cc2f45a3cabf5ccef65cd2aa" }, -+ { 1403, "d1c683742fe404c3c20d5704a5430e7832a7ec95" }, -+ { 1404, "867c79042e64f310628e219d8b85594cd0c7adc3" }, -+ { 1405, "c9d81d49d13d94358f56ccfd61af02b36c69f7c3" }, -+ { 1406, "0df43daab2786172f9b8d07d61f14a070cf1287a" }, -+ { 1407, "0fd8f3ad7f169534b274d4c66bbddd89f759e391" }, -+ { 1408, "3987511182b18473a564436003139b808fa46343" }, -+ { 1409, "ef667e063c9e9f539a8987a8d0bd3066ee85d901" }, -+ { 2048, "921109c99f3fedaca21727156d5f2b4460175327" }, -+ { 2049, "47188600dd165eb45f27c27196d3c46f4f042c1b" }, -+ { 2050, "8831939904009338de10e7fa670847041387807d" }, -+ { 2051, "2f8ebb5db2997d614e767be1050366f3641e7520" }, -+ { 2052, "669e51cd730dae158d3bef8adba075bd95a0d011" }, -+ { 3072, "cfee66cfd83abc8451af3c96c6b35a41cc6c55f5" }, -+ { 3074, "216ea26f02976a261b7d21a4dd3085157bedfabd" }, -+ { 3075, "bd612ebba021fd8e012b14c3bd60c8c5161fabc0" }, -+ { 4048, "c2564c1fdf2d5e9d7dde7aace2643428e90662e8" }, -+ { 4052, "91ce61fe924b445dfe7b5a1dcd10a27caec16df6" }, -+ { 4058, "db2a9be5ee8124f091c7ebd699266c5de223c164" }, -+ { 6144, "855109903feae2ba3a7a05a326b8a171116eb368" }, -+ { 6150, "37520bb3a668294d9c7b073e7e3daf8fee248a78" }, -+ { 6400, "60a353c841b6d2b1a05890349dad2fa33c7536b7" }, -+ { 6528, "9e53a43a69bb42d7c8522ca8bd632e421d5edb36" }, -+ { 8192, "a918cb0da862eaea0a33ee0efea50243e6b4927c" }, -+ { 8320, "29a5dcf55d1db29cd113fcf0572ae414f1c71329" }, -+ {16384, "6fb27966138e0c8d5a0d65ace817ebd53633cee1" }, -+ {18432, "ca09900d891c7c9ae2a559b10f63a217003341c1" }, -+ { 0, NULL }, -+}; -+ -+/* Key = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 -+ * 0x11, 0x12, 0x13, 0x14 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ */ -+static MV_CESA_SIZE_TEST shaMultiSizeTest404[] = -+{ -+ { 80, "beaf20a34b06a87558d156c0949bc3957d40222e" }, -+ { 512, "3353955358d886bc2940a3c7f337ff7dafb59c7b" }, -+ { 1000, "8737a542c5e9b2b6244b757ebb69d5bd602a829f" }, -+ { 1001, "fd9e7582d8a5d3c9fe3b923e4e6a41b07a1eb4d4" }, -+ { 1002, "a146d14a6fc3c274ff600568f4d75b977989e00d" }, -+ { 1003, "be22601bbc027ddef2dec97d30b3dc424fd803c5" }, -+ { 1004, "3e71fe99b2fe2b7bfdf4dbf0c7f3da25d7ea35e7" }, -+ { 1005, "2c422735d7295408fddd76f5e8a83a2a8da13df3" }, -+ { 1006, "6d875319049314b61855101a647b9ba3313428e6" }, -+ { 1336, "c1631ea80bad9dc43a180712461b65a0598c711c" }, -+ { 1344, "816069bf91d34581005746e2e0283d0f9c7b7605" }, -+ { 1399, "4e139866dc61cfcb8b67ca2ebd637b3a538593af" }, -+ { 1400, "ff2a0f8dd2b02c5417910f6f55d33a78e081a723" }, -+ { 1401, "ab00c12be62336964cbce31ae97fe2a0002984d5" }, -+ { 1402, "61349e7f999f3a1acc56c3e9a5060a9c4a7b05b6" }, -+ { 1403, "3edbc0f61e435bc1317fa27d840076093fb79353" }, -+ { 1404, "d052c6dfdbe63d45dab23ef9893e2aa4636aca1e" }, -+ { 1405, "0cc16b7388d67bf0add15a31e6e6c753cfae4987" }, -+ { 1406, "c96ba7eaad74253c38c22101b558d2850b1d1b90" }, -+ { 1407, "3445428a40d2c6556e7c55797ad8d323b61a48d9" }, -+ { 1408, "8d6444f937a09317c89834187b8ea9b8d3a8c56b" }, -+ { 1409, "c700acd3ecd19014ea2bdb4d42510c467e088475" }, -+ { 2048, "ee27d2a0cb77470c2f496212dfd68b5bb7b04e4b" }, -+ { 2049, "683762d7a02983b26a6d046e6451d9cd82c25932" }, -+ { 2050, "0fd20f1d55a9ee18363c2a6fd54aa13aee69992f" }, -+ { 2051, "86c267d8cc4bc8d59090e4f8b303da960fd228b7" }, -+ { 2052, "452395ae05b3ec503eea34f86fc0832485ad97c1" }, -+ { 3072, "75198e3cfd0b9bcff2dabdf8e38e6fdaa33ca49a" }, -+ { 3074, "4e24785ef080141ce4aab4675986d9acea624d7c" }, -+ { 3075, "3a20c5978dd637ec0e809bf84f0d9ccf30bc65bf" }, -+ { 4048, "3c32da256be7a7554922bf5fed51b0d2d09e59ad" }, -+ { 4052, "fff898426ea16e54325ae391a32c6c9bce4c23c0" }, -+ { 4058, "c800b9e562e1c91e1310116341a3c91d37f848ec" }, -+ { 6144, "d91d509d0cc4376c2d05bf9a5097717a373530e6" }, -+ { 6150, "d957030e0f13c5df07d9eec298542d8f94a07f12" }, -+ { 6400, "bb745313c3d7dc17b3f955e5534ad500a1082613" }, -+ { 6528, "77905f80d9ca82080bbb3e5654896dabfcfd1bdb" }, -+ { 8192, "5237fd9a81830c974396f99f32047586612ff3c0" }, -+ { 8320, "57668e28d5f2dba0839518a11db0f6af3d7e08bf" }, -+ {16384, "62e093fde467f0748087beea32e9af97d5c61241" }, -+ {18432, "845fb33130c7d6ea554fd5aacb9c50cf7ccb5929" }, -+ { 0, NULL }, -+}; -+ -+/* HASH-SHA1 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ * repeated "size" times -+ */ -+static MV_CESA_SIZE_TEST shaMultiSizeTest405[] = -+{ -+ { 80, "50abf5706a150990a08b2c5ea40fa0e585554732" }, -+ { 512, "f14516a08948fa27917a974d219741a697ba0087" }, -+ { 1000, "0bd18c378d5788817eb4f1e5dc07d867efa5cbf4" }, -+ { 1001, "ca29b85c35db1b8aef83c977893a11159d1b7aa2" }, -+ { 1002, "d83bc973eaaedb8a31437994dabbb3304b0be086" }, -+ { 1003, "2cf7bbef0acd6c00536b5c58ca470df9a3a90b6c" }, -+ { 1004, "e4375d09b1223385a8a393066f8209acfd936a80" }, -+ { 1005, "1029b38043e027745d019ce1d2d68e3d8b9d8f99" }, -+ { 1006, "deea16dcebbd8ac137e2b984deb639b9fb5e9680" }, -+ { 1336, "ea031b065fff63dcfb6a41956e4777520cdbc55d" }, -+ { 1344, "b52096c6445e6c0a8355995c70dc36ae186c863c" }, -+ { 1399, "cde2f6f8379870db4b32cf17471dc828a8dbff2b" }, -+ { 1400, "e53ff664064bc09fe5054c650806bd42d8179518" }, -+ { 1401, "d1156db5ddafcace64cdb510ff0d4af9b9a8ad64" }, -+ { 1402, "34ede0e9a909dd84a2ae291539105c0507b958e1" }, -+ { 1403, "a772ca3536da77e6ad3251e4f9e1234a4d7b87c0" }, -+ { 1404, "29740fd2b04e7a8bfd32242db6233156ad699948" }, -+ { 1405, "65b17397495b70ce4865dad93bf991b74c97cce1" }, -+ { 1406, "a7ee89cd0754061fdb91af7ea6abad2c69d542e3" }, -+ { 1407, "3eebf82f7420188e23d328b7ce93580b279a5715" }, -+ { 1408, "e08d3363a8b9a490dfb3a4c453452b8f114deeec" }, -+ { 1409, "95d74df739181a4ff30b8c39e28793a36598e924" }, -+ { 2048, "aa40262509c2abf84aab0197f83187fc90056d91" }, -+ { 2049, "7dec28ef105bc313bade8d9a7cdeac58b99de5ea" }, -+ { 2050, "d2e30f77ec81197de20f56588a156094ecb88450" }, -+ { 2051, "6b22ccc874833e96551a39da0c0edcaa0d969d92" }, -+ { 2052, "f843141e57875cd669af58744bc60aa9ea59549c" }, -+ { 3072, "09c5fedeaa62c132e673cc3c608a00142273d086" }, -+ { 3074, "b09e95eea9c7b1b007a58accec488301901a7f3d" }, -+ { 3075, "e6226b77b4ada287a8c9bbcf4ed71eec5ce632dc" }, -+ { 4048, "e99394894f855821951ddddf5bfc628547435f5c" }, -+ { 4052, "32d2f1af38be9cfba6cd03d55a254d0b3e1eb382" }, -+ { 4058, "d906552a4f2aca3a22e1fecccbcd183d7289d0ef" }, -+ { 6144, "2e7f62d35a860988e1224dc0543204af19316041" }, -+ { 6150, "d6b89698ee133df46fec9d552fadc328aa5a1b51" }, -+ { 6400, "dff50e90c46853988fa3a4b4ce5dda6945aae976" }, -+ { 6528, "9e63ec0430b96db02d38bc78357a2f63de2ab7f8" }, -+ { 8192, "971eb71ed60394d5ab5abb12e88420bdd41b5992" }, -+ { 8320, "91606a31b46afeaac965cecf87297e791b211013" }, -+ {16384, "547f830a5ec1f5f170ce818f156b1002cabc7569" }, -+ {18432, "f16f272787f3b8d539652e4dc315af6ab4fda0ef" }, -+ { 0, NULL }, -+}; -+ -+/* CryptoKey = 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef; -+ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ * Note: only sizes aligned to 3DES block size (8 bytes) allowed -+ */ -+static MV_CESA_SIZE_TEST tripleDesMdMultiSizeTest502[] = -+{ -+ { 64, "9586962a2aaaef28803dec2e17807a7f" }, -+ { 80, "b7726a03aad490bd6c5a452a89a1b271" }, -+ { 352, "f1ed9563aecc3c0d2766eb2bed3b4e4c" }, -+ { 512, "0f9decb11ab40fe86f4d4d9397bc020e" }, -+ { 1000, "3ba69deac12cab8ff9dff7dbd9669927" }, -+ { 1336, "6cf47bf1e80e03e2c1d0945bc50d37d2" }, -+ { 1344, "4be388dab21ceb3fa1b8d302e9b821f7" }, -+ { 1400, "a58b79fb21dd9bfc6ec93e3b99fb0ef1" }, -+ { 1408, "8bc97379fc2ac3237effcdd4f7a86528" }, -+ { 2048, "1339f03ab3076f25a20bc4cba16eb5bf" }, -+ { 3072, "731204d2d90c4b36ae41f5e1fb874288" }, -+ { 4048, "c028d998cfda5642547b7e1ed5ea16e4" }, -+ { 6144, "b1b19cd910cc51bd22992f1e59f1e068" }, -+ { 6400, "44e4613496ba622deb0e7cb768135a2f" }, -+ { 6528, "3b06b0a86f8db9cd67f9448dfcf10549" }, -+ { 8192, "d581780b7163138a0f412be681457d82" }, -+ {16384, "03b8ac05527faaf1bed03df149c65ccf" }, -+ {18432, "677c8a86a41dab6c5d81b85b8fb10ff6" }, -+ { 0, NULL }, -+}; -+ -+ -+/* CryptoKey = 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef; -+ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 -+ * 0x11, 0x12, 0x13, 0x14 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ * Note: only sizes aligned to 3DES block size (8 bytes) allowed -+ */ -+static MV_CESA_SIZE_TEST tripleDesShaMultiSizeTest503[] = -+{ -+ { 64, "44a1e9bcbfc1429630d9ea68b7a48b0427a684f2" }, -+ { 80, "b2ddeaca91030eab5b95a234ef2c0f6e738ff883" }, -+ { 352, "4b91864c7ff629bdff75d9726421f76705452aaf" }, -+ { 512, "6dd37faceeb2aa98ba74f4242ed6734a4d546af5" }, -+ { 1000, "463661c30300be512a9df40904f0757cde5f1141" }, -+ { 1336, "b931f831d9034fe59c65176400b039fe9c1f44a5" }, -+ { 1344, "af8866b1cd4a4887d6185bfe72470ffdfb3648e1" }, -+ { 1400, "49c6caf07296d5e31d2504d088bc5b20c3ee7cdb" }, -+ { 1408, "fcae8deedbc6ebf0763575dc7e9de075b448a0f4" }, -+ { 2048, "edece5012146c1faa0dd10f50b183ba5d2af58ac" }, -+ { 3072, "5b83625adb43a488b8d64fecf39bb766818547b7" }, -+ { 4048, "d2c533678d26c970293af60f14c8279dc708bfc9" }, -+ { 6144, "b8f67af4f991b08b725f969b049ebf813bfacc5c" }, -+ { 6400, "d9a6c7f746ac7a60ef2edbed2841cf851c25cfb0" }, -+ { 6528, "376792b8c8d18161d15579fb7829e6e3a27e9946" }, -+ { 8192, "d890eabdca195b34ef8724b28360cffa92ae5655" }, -+ {16384, "a167ee52639ec7bf19aee9c6e8f76667c14134b9" }, -+ {18432, "e4396ab56f67296b220985a12078f4a0e365d2cc" }, -+ { 0, NULL }, -+}; -+ -+/* CryptoKey = 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef -+ * IV = 0x12345678, 0x90abcdef -+ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ * Note: only sizes aligned to 3DES block size (8 bytes) allowed -+ */ -+static MV_CESA_SIZE_TEST cbc3desMdMultiSizeTest504[] = -+{ -+ { 64, "8d10e00802460ede0058c139ba48bd2d" }, -+ { 80, "6f463057e1a90e0e91ae505b527bcec0" }, -+ { 352, "4938d48bdf86aece2c6851e7c6079788" }, -+ { 512, "516705d59f3cf810ebf2a13a23a7d42e" }, -+ { 1000, "a5a000ee5c830e67ddc6a2d2e5644b31" }, -+ { 1336, "44af60087b74ed07950088efbe3b126a" }, -+ { 1344, "1f5b39e0577920af731dabbfcf6dfc2a" }, -+ { 1400, "6804ea640e29b9cd39e08bc37dbce734" }, -+ { 1408, "4fb436624b02516fc9d1535466574bf9" }, -+ { 2048, "c909b0985c423d8d86719f701e9e83db" }, -+ { 3072, "cfe0bc34ef97213ee3d3f8b10122db21" }, -+ { 4048, "03ea10b5ae4ddeb20aed6af373082ed1" }, -+ { 6144, "b9a0ff4f87fc14b3c2dc6f0ed0998fdf" }, -+ { 6400, "6995f85d9d4985dd99e974ec7dda9dd6" }, -+ { 6528, "bbbb548ce2fa3d58467f6a6a5168a0e6" }, -+ { 8192, "afe101fbe745bb449ae4f50d10801456" }, -+ {16384, "9741706d0b1c923340c4660ff97cacdf" }, -+ {18432, "b0217becb73cb8f61fd79c7ce9d023fb" }, -+ { 0, NULL }, -+}; -+ -+ -+/* CryptoKey = 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef; -+ * IV = 0x12345678, 0x90abcdef -+ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 -+ * 0x11, 0x12, 0x13, 0x14 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ * Note: only sizes aligned to 3DES block size (8 bytes) allowed -+ */ -+static MV_CESA_SIZE_TEST cbc3desShaMultiSizeTest505[] = -+{ -+ { 64, "409187e5bdb0be4a7754ca3747f7433dc4f01b98" }, -+ { 80, "1b002ed050be743aa98860cf35659646bb8efcc0" }, -+ { 352, "6cbf7ebe50fa4fa6eecc19eca23f9eae553ccfff" }, -+ { 512, "cfb5253fb4bf72b743320c30c7e48c54965853b0" }, -+ { 1000, "95e04e1ca2937e7c5a9aba9e42d2bcdb8a7af21f" }, -+ { 1336, "3b5c1f5eee5837ebf67b83ae01405542d77a6627" }, -+ { 1344, "2b3d42ab25615437f98a1ee310b81d07a02badc2" }, -+ { 1400, "7f8687df7c1af44e4baf3c934b6cca5ab6bc993e" }, -+ { 1408, "473a581c5f04f7527d50793c845471ac87e86430" }, -+ { 2048, "e41d20cae7ebe34e6e828ed62b1e5734019037bb" }, -+ { 3072, "275664afd7a561d804e6b0d204e53939cde653ae" }, -+ { 4048, "0d220cc5b34aeeb46bbbd637dde6290b5a8285a3" }, -+ { 6144, "cb393ddcc8b1c206060625b7d822ef9839e67bc5" }, -+ { 6400, "dd3317e2a627fc04800f74a4b05bfda00fab0347" }, -+ { 6528, "8a74c3b2441ab3f5a7e08895cc432566219a7c41" }, -+ { 8192, "b8e6ef3a549ed0e005bd5b8b1a5fe6689e9711a7" }, -+ {16384, "55f59404008276cdac0e2ba0d193af2d40eac5ce" }, -+ {18432, "86ae6c4fc72369a54cce39938e2d0296cd9c6ec5" }, -+ { 0, NULL }, -+}; -+ -+ -+/* CryptoKey = 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef -+ * IV = 0x12345678, 0x90abcdef -+ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ * Note: only sizes aligned to AES block size (16 bytes) allowed -+ */ -+static MV_CESA_SIZE_TEST cbcAes128md5multiSizeTest506[] = -+{ -+ { 16, "7ca4c2ba866751598720c5c4aa0d6786" }, -+ { 64, "7dba7fb988e80da609b1fea7254bced8" }, -+ { 80, "6b6e863ac5a71d15e3e9b1c86c9ba05f" }, -+ { 352, "a1ceb9c2e3021002400d525187a9f38c" }, -+ { 512, "596c055c1c55db748379223164075641" }, -+ { 1008, "f920989c02f3b3603f53c99d89492377" }, -+ { 1344, "2e496b73759d77ed32ea222dbd2e7b41" }, -+ { 1408, "7178c046b3a8d772efdb6a71c4991ea4" }, -+ { 2048, "a917f0099c69eb94079a8421714b6aad" }, -+ { 3072, "693cd5033d7f5391d3c958519fa9e934" }, -+ { 4048, "139dca91bcff65b3c40771749052906b" }, -+ { 6144, "428d9cef6df4fb70a6e9b6bbe4819e55" }, -+ { 6400, "9c0b909e76daa811e12b1fc17000a0c4" }, -+ { 6528, "ad876f6297186a7be1f1b907ed860eda" }, -+ { 8192, "479cbbaca37dd3191ea1f3e8134a0ef4" }, -+ {16384, "60fda559c74f91df538100c9842f2f15" }, -+ {18432, "4a3eb1cba1fa45f3981270953f720c42" }, -+ { 0, NULL }, -+}; -+ -+ -+/* CryptoKey = 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef; -+ * IV = 0x12345678, 0x90abcdef -+ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 -+ * 0x11, 0x12, 0x13, 0x14 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ * Note: only sizes aligned to AES block size (16 bytes) allowed -+ */ -+static MV_CESA_SIZE_TEST cbcAes128sha1multiSizeTest507[] = -+{ -+ { 16, "9aa8dc1c45f0946daf78057fa978759c625c1fee" }, -+ { 64, "9f588fc1ede851e5f8b20256abc9979465ae2189" }, -+ { 80, "13558472d1fc1c90dffec6e5136c7203452d509b" }, -+ { 352, "6b93518e006cfaa1f7adb24615e7291fb0a27e06" }, -+ { 512, "096874951a77fbbf333e49d80c096ee2016e09bd" }, -+ { 1008, "696fc203c2e4b5ae0ec5d1db3f623c490bc6dbac" }, -+ { 1344, "79bf77509935ccd3528caaac6a5eb6481f74029b" }, -+ { 1408, "627f9462b95fc188e8cfa7eec15119bdc5d4fcf1" }, -+ { 2048, "3d50d0c005feba92fe41502d609fced9c882b4d1" }, -+ { 3072, "758807e5b983e3a91c06fb218fe0f73f77111e94" }, -+ { 4048, "ca90e85242e33f005da3504416a52098d0d31fb2" }, -+ { 6144, "8044c1d4fd06642dfc46990b4f18b61ef1e972cf" }, -+ { 6400, "166f1f4ea57409f04feba9fb1e39af0e00bd6f43" }, -+ { 6528, "0389016a39485d6e330f8b4215ddf718b404f7e9" }, -+ { 8192, "6df7ee2a8b61d6f7f860ce8dbf778f0c2a5b508b" }, -+ {16384, "a70a6d8dfa1f91ded621c3dbaed34162bc48783f" }, -+ {18432, "8dfad627922ce15df1eed10bdbed49244efa57db" }, -+ { 0, NULL }, -+}; -+ -+ -+void cesaTestPrintStatus(void); -+ -+ -+/*------------------------- LOCAL FUNCTIONs ---------------------------------*/ -+MV_STATUS testCmd(int sid, int iter, MV_CESA_COMMAND* pCmd, -+ MV_CESA_TEST_SESSION* pTestSession, MV_U8* pIV, int ivSize); -+MV_STATUS testClose(int idx); -+MV_STATUS testOpen(int idx); -+void close_session(int sid); -+void cesaTestCheckReady(const MV_CESA_RESULT *r); -+void cesaCheckReady(MV_CESA_RESULT* r); -+void printTestResults(int idx, MV_STATUS status, int checkMode); -+void cesaLastResult(void); -+void cesaTestPrintReq(int req, int offset, int size); -+ -+void cesaTestPrintStatus(void); -+void cesaTestPrintSession(int idx); -+void sizeTest(int testIdx, int iter, int checkMode); -+void multiTest(int iter, int reqSize, int checkMode); -+void oneTest(int testIdx, int caseIdx,int iter, int reqSize, int checkMode); -+void multiSizeTest(int idx, int iter, int checkMode, char* inputData); -+void cesaTest(int iter, int reqSize, int checkMode); -+void cesaOneTest(int testIdx, int caseIdx,int iter, int reqSize, int checkMode); -+void combiTest(int iter, int reqSize, int checkMode); -+void shaTest(int iter, int reqSize, int checkMode); -+void mdTest(int iter, int reqSize, int checkMode); -+void aesTest(int iter, int reqSize, int checkMode); -+void tripleDesTest(int iter, int reqSize, int checkMode); -+void desTest(int iter, int reqSize, int checkMode); -+void cesaTestStop(void); -+MV_STATUS testRun(int idx, int caseIdx, int iter,int reqSize, int checkMode); -+void cesaTestStart(int bufNum, int bufSize); -+ -+ -+static MV_U32 getRate(MV_U32* remainder) -+{ -+ MV_U32 kBits, milliSec, rate; -+ -+ milliSec = 0; -+ if( (cesaEndTicks - cesaBeginTicks) > 0) -+ { -+ milliSec = CESA_TEST_TICK_TO_MS(cesaEndTicks - cesaBeginTicks); -+ } -+ if(milliSec == 0) -+ { -+ if(remainder != NULL) -+ *remainder = 0; -+ return 0; -+ } -+ -+ kBits = (cesaIteration*cesaRateSize*8)/1000; -+ rate = kBits/milliSec; -+ if(remainder != NULL) -+ *remainder = ((kBits % milliSec)*10)/milliSec; -+ -+ return rate; -+} -+ -+static char* extractMbuf(MV_CESA_MBUF *pMbuf, -+ int offset, int size, char* hexStr) -+{ -+ mvCesaCopyFromMbuf((MV_U8*)cesaBinBuffer, pMbuf, offset, size); -+ mvBinToHex((const MV_U8*)cesaBinBuffer, hexStr, size); -+ -+ return hexStr; -+} -+ -+static MV_BOOL cesaCheckMbuf(MV_CESA_MBUF *pMbuf, -+ const char* hexString, int offset, -+ int checkSize) -+{ -+ MV_BOOL isFailed = MV_FALSE; -+ MV_STATUS status; -+ int size = strlen(hexString)/2; -+ int checkedSize = 0; -+/* -+ mvOsPrintf("cesaCheckMbuf: pMbuf=%p, offset=%d, checkSize=%d, mBufSize=%d\n", -+ pMbuf, offset, checkSize, pMbuf->mbufSize); -+*/ -+ if(pMbuf->mbufSize < (checkSize + offset)) -+ { -+ mvOsPrintf("checkSize (%d) is too large: offset=%d, mbufSize=%d\n", -+ checkSize, offset, pMbuf->mbufSize); -+ return MV_TRUE; -+ } -+ status = mvCesaCopyFromMbuf((MV_U8*)cesaBinBuffer, pMbuf, offset, checkSize); -+ if(status != MV_OK) -+ { -+ mvOsPrintf("CesaTest: Can't copy %d bytes from Mbuf=%p to checkBuf=%p\n", -+ checkSize, pMbuf, cesaBinBuffer); -+ return MV_TRUE; -+ } -+/* -+ mvDebugMemDump(cesaBinBuffer, size, 1); -+*/ -+ mvHexToBin(hexString, (MV_U8*)cesaExpBinBuffer, size); -+ -+ /* Compare buffers */ -+ while(checkSize > checkedSize) -+ { -+ size = MV_MIN(size, (checkSize - checkedSize)); -+ if(memcmp(cesaExpBinBuffer, &cesaBinBuffer[checkedSize], size) != 0) -+ { -+ mvOsPrintf("CheckMbuf failed: checkSize=%d, size=%d, checkedSize=%d\n", -+ checkSize, size, checkedSize); -+ mvDebugMemDump(&cesaBinBuffer[checkedSize], size, 1); -+ mvDebugMemDump(cesaExpBinBuffer, size, 1); -+ -+ isFailed = MV_TRUE; -+ break; -+ } -+ checkedSize += size; -+ } -+ -+ return isFailed; -+} -+ -+static MV_STATUS cesaSetMbuf(MV_CESA_MBUF *pMbuf, -+ const char* hexString, -+ int offset, int reqSize) -+{ -+ MV_STATUS status = MV_OK; -+ int copySize, size = strlen(hexString)/2; -+ -+ mvHexToBin(hexString, (MV_U8*)cesaBinBuffer, size); -+ -+ copySize = 0; -+ while(reqSize > copySize) -+ { -+ size = MV_MIN(size, (reqSize - copySize)); -+ -+ status = mvCesaCopyToMbuf((MV_U8*)cesaBinBuffer, pMbuf, offset+copySize, size); -+ if(status != MV_OK) -+ { -+ mvOsPrintf("cesaSetMbuf Error: Copy %d of %d bytes to MBuf\n", -+ copySize, reqSize); -+ break; -+ } -+ copySize += size; -+ } -+ pMbuf->mbufSize = offset+copySize; -+ return status; -+} -+ -+static MV_CESA_TEST_SESSION* getTestSessionDb(int idx, int* pTestIdx) -+{ -+ int testIdx, dbIdx = idx/100; -+ -+ if(dbIdx > MAX_TEST_TYPE) -+ { -+ mvOsPrintf("Wrong index %d - No such test type\n", idx); -+ return NULL; -+ } -+ testIdx = idx % 100; -+ -+ if(testIdx >= cesaTestsDB[dbIdx].numSessions) -+ { -+ mvOsPrintf("Wrong index %d - No such test\n", idx); -+ return NULL; -+ } -+ if(pTestIdx != NULL) -+ *pTestIdx = testIdx; -+ -+ return cesaTestsDB[dbIdx].pSessions; -+} -+ -+/* Debug */ -+void cesaTestPrintReq(int req, int offset, int size) -+{ -+ MV_CESA_MBUF* pMbuf; -+ -+ mvOsPrintf("cesaTestPrintReq: req=%d, offset=%d, size=%d\n", -+ req, offset, size); -+ mvDebugMemDump(cesaCmdRing, 128, 4); -+ -+ pMbuf = cesaCmdRing[req].pSrc; -+ mvCesaDebugMbuf("src", pMbuf, offset,size); -+ pMbuf = cesaCmdRing[req].pDst; -+ mvCesaDebugMbuf("dst", pMbuf, offset, size); -+ -+ cesaTestPrintStatus(); -+} -+ -+void cesaLastResult(void) -+{ -+ mvOsPrintf("Last Result: ReqId = %d, SessionId = %d, rc = (%d)\n", -+ (MV_U32)cesaResult.pReqPrv, cesaResult.sessionId, -+ cesaResult.retCode); -+} -+ -+void printTestResults(int idx, MV_STATUS status, int checkMode) -+{ -+ int testIdx; -+ MV_CESA_TEST_SESSION* pTestSessions = getTestSessionDb(idx, &testIdx); -+ -+ if(pTestSessions == NULL) -+ return; -+ -+ mvOsPrintf("%-35s %4dx%-4d : ", pTestSessions[testIdx].name, -+ cesaIteration, cesaReqSize); -+ if( (status == MV_OK) && -+ (cesaCryptoError == 0) && -+ (cesaError == 0) && -+ (cesaReqIdError == 0) ) -+ { -+ mvOsPrintf("Passed, Rate=%3u.%u Mbps (%5u cpp)\n", -+ cesaRate, cesaRateAfterDot, cesaEndTicks - cesaBeginTicks); -+ } -+ else -+ { -+ mvOsPrintf("Failed, Status = 0x%x\n", status); -+ if(cesaCryptoError > 0) -+ mvOsPrintf("cryptoError : %d\n", cesaCryptoError); -+ if(cesaReqIdError > 0) -+ mvOsPrintf("reqIdError : %d\n", cesaReqIdError); -+ if(cesaError > 0) -+ mvOsPrintf("cesaError : %d\n", cesaError); -+ } -+ if(cesaTestIsrMissCount > 0) -+ mvOsPrintf("cesaIsrMissed : %d\n", cesaTestIsrMissCount); -+} -+ -+void cesaCheckReady(MV_CESA_RESULT* r) -+{ -+ int reqId; -+ MV_CESA_MBUF *pMbuf; -+ MV_BOOL isFailed; -+ -+ cesaResult = *r; -+ reqId = (int)cesaResult.pReqPrv; -+ pMbuf = cesaCmdRing[reqId].pDst; -+ -+/* -+ mvOsPrintf("cesaCheckReady: reqId=%d, checkOffset=%d, checkSize=%d\n", -+ reqId, cesaCheckOffset, cesaCheckSize); -+*/ -+ /* Check expected reqId */ -+ if(reqId != cesaExpReqId) -+ { -+ cesaReqIdError++; -+/* -+ mvOsPrintf("CESA reqId Error: cbIter=%d (%d), reqId=%d, expReqId=%d\n", -+ cesaCbIter, cesaIteration, reqId, cesaExpReqId); -+*/ -+ } -+ else -+ { -+ if( (cesaCheckMode == CESA_FULL_CHECK_MODE) || -+ (cesaCheckMode == CESA_FAST_CHECK_MODE) ) -+ { -+ if(cesaResult.retCode != MV_OK) -+ { -+ cesaError++; -+ -+ mvOsPrintf("CESA Error: cbIter=%d (%d), reqId=%d, rc=%d\n", -+ cesaCbIter, cesaIteration, reqId, cesaResult.retCode); -+ } -+ else -+ { -+ if( (cesaCheckSize > 0) && (cesaOutputHexStr != NULL) ) -+ { -+ /* Check expected output */ -+ -+ isFailed = cesaCheckMbuf(pMbuf, cesaOutputHexStr, cesaCheckOffset, cesaCheckSize); -+ if(isFailed) -+ { -+ mvOsPrintf("CESA Crypto Error: cbIter=%d (%d), reqId=%d\n", -+ cesaCbIter, cesaIteration, reqId); -+ -+ CESA_TEST_DEBUG_PRINT(("Error: reqId=%d, reqSize=%d, checkOffset=%d, checkSize=%d\n", -+ reqId, cesaReqSize, cesaCheckOffset, cesaCheckSize)); -+ -+ CESA_TEST_DEBUG_PRINT(("Output str: %s\n", cesaOutputHexStr)); -+ -+ CESA_TEST_DEBUG_CODE( mvCesaDebugMbuf("error", pMbuf, 0, cesaCheckOffset+cesaCheckSize) ); -+ -+ cesaCryptoError++; -+ } -+ } -+ } -+ } -+ } -+ if(cesaCheckMode == CESA_SHOW_CHECK_MODE) -+ { -+ extractMbuf(pMbuf, cesaCheckOffset, cesaCheckSize, cesaHexBuffer); -+ mvOsPrintf("%4d, %s\n", cesaCheckOffset, cesaHexBuffer); -+ } -+ -+ cesaCbIter++; -+ if(cesaCbIter >= cesaIteration) -+ { -+ cesaCbIter = 0; -+ cesaExpReqId = 0; -+ cesaIsReady = MV_TRUE; -+ -+ cesaEndTicks = CESA_TEST_TICK_GET(); -+ cesaRate = getRate(&cesaRateAfterDot); -+ } -+ else -+ { -+ cesaExpReqId = reqId + 1; -+ if(cesaExpReqId == CESA_DEF_REQ_SIZE) -+ cesaExpReqId = 0; -+ } -+} -+ -+ -+#ifdef MV_NETBSD -+static int cesaTestReadyIsr(void *arg) -+#else -+#ifdef __KERNEL__ -+static irqreturn_t cesaTestReadyIsr( int irq , void *dev_id) -+#endif -+#ifdef MV_VXWORKS -+void cesaTestReadyIsr(void) -+#endif -+#endif -+{ -+ MV_U32 cause; -+ MV_STATUS status; -+ MV_CESA_RESULT result; -+ -+ cesaTestIsrCount++; -+ /* Clear cause register */ -+ cause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); -+ if( (cause & MV_CESA_CAUSE_ACC_DMA_ALL_MASK) == 0) -+ { -+ mvOsPrintf("cesaTestReadyIsr: cause=0x%x\n", cause); -+#ifdef MV_NETBSD -+ return 0; -+#else -+#ifdef __KERNEL__ -+ return 1; -+#else -+ return; -+#endif -+#endif -+ } -+ -+ MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); -+ -+ while(MV_TRUE) -+ { -+ /* Get Ready requests */ -+ status = mvCesaReadyGet(&result); -+ if(status == MV_OK) -+ cesaCheckReady(&result); -+ -+ break; -+ } -+ if( (cesaTestFull == 1) && (status != MV_BUSY) ) -+ { -+ cesaTestFull = 0; -+ CESA_TEST_WAKE_UP(); -+ } -+ -+#ifdef __KERNEL__ -+ return 1; -+#endif -+} -+ -+void -+cesaTestCheckReady(const MV_CESA_RESULT *r) -+{ -+ MV_CESA_RESULT result = *r; -+ -+ cesaCheckReady(&result); -+ -+ if (cesaTestFull == 1) { -+ cesaTestFull = 0; -+ CESA_TEST_WAKE_UP(); -+ } -+} -+ -+static INLINE int open_session(MV_CESA_OPEN_SESSION* pOs) -+{ -+ MV_U16 sid; -+ MV_STATUS status; -+ -+ status = mvCesaSessionOpen(pOs, (short*)&sid); -+ if(status != MV_OK) -+ { -+ mvOsPrintf("CesaTest: Can't open new session - status = 0x%x\n", -+ status); -+ return -1; -+ } -+ -+ return (int)sid; -+} -+ -+void close_session(int sid) -+{ -+ MV_STATUS status; -+ -+ status = mvCesaSessionClose(sid); -+ if(status != MV_OK) -+ { -+ mvOsPrintf("CesaTest: Can't close session %d - status = 0x%x\n", -+ sid, status); -+ } -+} -+ -+MV_STATUS testOpen(int idx) -+{ -+ MV_CESA_OPEN_SESSION os; -+ int sid, i, testIdx; -+ MV_CESA_TEST_SESSION* pTestSession; -+ MV_U16 digestSize = 0; -+ -+ pTestSession = getTestSessionDb(idx, &testIdx); -+ if(pTestSession == NULL) -+ { -+ mvOsPrintf("Test %d is not exist\n", idx); -+ return MV_BAD_PARAM; -+ } -+ pTestSession = &pTestSession[testIdx]; -+ -+ if(pTestSession->sid != -1) -+ { -+ mvOsPrintf("Session for test %d already created: sid=%d\n", -+ idx, pTestSession->sid); -+ return MV_OK; -+ } -+ -+ os.cryptoAlgorithm = pTestSession->cryptoAlgorithm; -+ os.macMode = pTestSession->macAlgorithm; -+ switch(os.macMode) -+ { -+ case MV_CESA_MAC_MD5: -+ case MV_CESA_MAC_HMAC_MD5: -+ digestSize = MV_CESA_MD5_DIGEST_SIZE; -+ break; -+ -+ case MV_CESA_MAC_SHA1: -+ case MV_CESA_MAC_HMAC_SHA1: -+ digestSize = MV_CESA_SHA1_DIGEST_SIZE; -+ break; -+ -+ case MV_CESA_MAC_NULL: -+ digestSize = 0; -+ } -+ os.cryptoMode = pTestSession->cryptoMode; -+ os.direction = pTestSession->direction; -+ os.operation = pTestSession->operation; -+ -+ for(i=0; icryptoKeySize; i++) -+ os.cryptoKey[i] = pTestSession->pCryptoKey[i]; -+ -+ os.cryptoKeyLength = pTestSession->cryptoKeySize; -+ -+ for(i=0; imacKeySize; i++) -+ os.macKey[i] = pTestSession->pMacKey[i]; -+ -+ os.macKeyLength = pTestSession->macKeySize; -+ os.digestSize = digestSize; -+ -+ sid = open_session(&os); -+ if(sid == -1) -+ { -+ mvOsPrintf("Can't open session for test %d: rc=0x%x\n", -+ idx, cesaResult.retCode); -+ return cesaResult.retCode; -+ } -+ CESA_TEST_DEBUG_PRINT(("Opened session: sid = %d\n", sid)); -+ pTestSession->sid = sid; -+ return MV_OK; -+} -+ -+MV_STATUS testClose(int idx) -+{ -+ int testIdx; -+ MV_CESA_TEST_SESSION* pTestSession; -+ -+ pTestSession = getTestSessionDb(idx, &testIdx); -+ if(pTestSession == NULL) -+ { -+ mvOsPrintf("Test %d is not exist\n", idx); -+ return MV_BAD_PARAM; -+ } -+ pTestSession = &pTestSession[testIdx]; -+ -+ if(pTestSession->sid == -1) -+ { -+ mvOsPrintf("Test session %d is not opened\n", idx); -+ return MV_NO_SUCH; -+ } -+ -+ close_session(pTestSession->sid); -+ pTestSession->sid = -1; -+ -+ return MV_OK; -+} -+ -+MV_STATUS testCmd(int sid, int iter, MV_CESA_COMMAND* pCmd, -+ MV_CESA_TEST_SESSION* pTestSession, MV_U8* pIV, int ivSize) -+{ -+ int cmdReqId = 0; -+ int i; -+ MV_STATUS rc = MV_OK; -+ char ivZeroHex[] = "0000"; -+ -+ if(iter == 0) -+ iter = CESA_DEF_ITER_NUM; -+ -+ if(pCmd == NULL) -+ { -+ mvOsPrintf("testCmd failed: pCmd=NULL\n"); -+ return MV_BAD_PARAM; -+ } -+ pCmd->sessionId = sid; -+ -+ cesaCryptoError = 0; -+ cesaReqIdError = 0; -+ cesaError = 0; -+ cesaTestIsrMissCount = 0; -+ cesaIsReady = MV_FALSE; -+ cesaIteration = iter; -+ -+ if(cesaInputHexStr == NULL) -+ cesaInputHexStr = cesaPlainHexEbc; -+ -+ for(i=0; ipSrc = (MV_CESA_MBUF*)(cesaCmdRing[i].pSrc); -+ if(pIV != NULL) -+ { -+ /* If IV from SA - set IV in Source buffer to zeros */ -+ cesaSetMbuf(pCmd->pSrc, ivZeroHex, 0, pCmd->cryptoOffset); -+ cesaSetMbuf(pCmd->pSrc, cesaInputHexStr, pCmd->cryptoOffset, -+ (cesaReqSize - pCmd->cryptoOffset)); -+ } -+ else -+ { -+ cesaSetMbuf(pCmd->pSrc, cesaInputHexStr, 0, cesaReqSize); -+ } -+ pCmd->pDst = (MV_CESA_MBUF*)(cesaCmdRing[i].pDst); -+ cesaSetMbuf(pCmd->pDst, cesaNullPlainHexText, 0, cesaReqSize); -+ -+ memcpy(&cesaCmdRing[i], pCmd, sizeof(*pCmd)); -+ } -+ -+ if(cesaCheckMode == CESA_SW_SHOW_CHECK_MODE) -+ { -+ MV_U8 pDigest[MV_CESA_MAX_DIGEST_SIZE]; -+ -+ if(pTestSession->macAlgorithm == MV_CESA_MAC_MD5) -+ { -+ mvMD5(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, pDigest); -+ mvOsPrintf("SW HASH_MD5: reqSize=%d, macLength=%d\n", -+ cesaReqSize, pCmd->macLength); -+ mvDebugMemDump(pDigest, MV_CESA_MD5_DIGEST_SIZE, 1); -+ return MV_OK; -+ } -+ if(pTestSession->macAlgorithm == MV_CESA_MAC_SHA1) -+ { -+ mvSHA1(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, pDigest); -+ mvOsPrintf("SW HASH_SHA1: reqSize=%d, macLength=%d\n", -+ cesaReqSize, pCmd->macLength); -+ mvDebugMemDump(pDigest, MV_CESA_SHA1_DIGEST_SIZE, 1); -+ return MV_OK; -+ } -+ } -+ -+ cesaBeginTicks = CESA_TEST_TICK_GET(); -+ CESA_TEST_DEBUG_CODE( memset(cesaTestTrace, 0, sizeof(cesaTestTrace)); -+ cesaTestTraceIdx = 0; -+ ); -+ -+ if(cesaCheckMode == CESA_SW_NULL_CHECK_MODE) -+ { -+ volatile MV_U8 pDigest[MV_CESA_MAX_DIGEST_SIZE]; -+ -+ for(i=0; imacAlgorithm == MV_CESA_MAC_MD5) -+ { -+ mvMD5(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, (unsigned char*)pDigest); -+ } -+ if(pTestSession->macAlgorithm == MV_CESA_MAC_SHA1) -+ { -+ mvSHA1(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, (MV_U8 *)pDigest); -+ } -+ } -+ cesaEndTicks = CESA_TEST_TICK_GET(); -+ cesaRate = getRate(&cesaRateAfterDot); -+ cesaIsReady = MV_TRUE; -+ -+ return MV_OK; -+ } -+ -+ /*cesaTestIsrCount = 0;*/ -+ /*mvCesaDebugStatsClear();*/ -+ -+#ifndef MV_NETBSD -+ MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); -+#endif -+ -+ for(i=0; ipReqPrv = (void*)cmdReqId; -+ -+ CESA_TEST_LOCK(flags); -+ -+ rc = mvCesaAction(pCmd); -+ if(rc == MV_NO_RESOURCE) -+ cesaTestFull = 1; -+ -+ CESA_TEST_UNLOCK(flags); -+ -+ if(rc == MV_NO_RESOURCE) -+ { -+ CESA_TEST_LOCK(flags); -+ CESA_TEST_WAIT( (cesaTestFull == 0), 100); -+ CESA_TEST_UNLOCK(flags); -+ if(cesaTestFull == 1) -+ { -+ mvOsPrintf("CESA Test timeout: i=%d, iter=%d, cesaTestFull=%d\n", -+ i, iter, cesaTestFull); -+ cesaTestFull = 0; -+ return MV_TIMEOUT; -+ } -+ -+ CESA_TEST_LOCK(flags); -+ -+ rc = mvCesaAction(pCmd); -+ -+ CESA_TEST_UNLOCK(flags); -+ } -+ if( (rc != MV_OK) && (rc != MV_NO_MORE) ) -+ { -+ mvOsPrintf("mvCesaAction failed: rc=%d\n", rc); -+ return rc; -+ } -+ -+ cmdReqId++; -+ if(cmdReqId >= CESA_DEF_REQ_SIZE) -+ cmdReqId = 0; -+ -+#ifdef MV_LINUX -+ /* Reschedule each 16 requests */ -+ if( (i & 0xF) == 0) -+ schedule(); -+#endif -+ } -+ return MV_OK; -+} -+ -+void cesaTestStart(int bufNum, int bufSize) -+{ -+ int i, j, idx; -+ MV_CESA_MBUF *pMbufSrc, *pMbufDst; -+ MV_BUF_INFO *pFragsSrc, *pFragsDst; -+ char *pBuf; -+#ifndef MV_NETBSD -+ int numOfSessions, queueDepth; -+ char *pSram; -+ MV_STATUS status; -+ MV_CPU_DEC_WIN addrDecWin; -+#endif -+ -+ cesaCmdRing = mvOsMalloc(sizeof(MV_CESA_COMMAND) * CESA_DEF_REQ_SIZE); -+ if(cesaCmdRing == NULL) -+ { -+ mvOsPrintf("testStart: Can't allocate %ld bytes of memory\n", -+ sizeof(MV_CESA_COMMAND) * CESA_DEF_REQ_SIZE); -+ return; -+ } -+ memset(cesaCmdRing, 0, sizeof(MV_CESA_COMMAND) * CESA_DEF_REQ_SIZE); -+ -+ if(bufNum == 0) -+ bufNum = CESA_DEF_BUF_NUM; -+ -+ if(bufSize == 0) -+ bufSize = CESA_DEF_BUF_SIZE; -+ -+ cesaBufNum = bufNum; -+ cesaBufSize = bufSize; -+ mvOsPrintf("CESA test started: bufNum = %d, bufSize = %d\n", -+ bufNum, bufSize); -+ -+ cesaHexBuffer = mvOsMalloc(2*bufNum*bufSize); -+ if(cesaHexBuffer == NULL) -+ { -+ mvOsPrintf("testStart: Can't malloc %d bytes for cesaHexBuffer.\n", -+ 2*bufNum*bufSize); -+ return; -+ } -+ memset(cesaHexBuffer, 0, (2*bufNum*bufSize)); -+ -+ cesaBinBuffer = mvOsMalloc(bufNum*bufSize); -+ if(cesaBinBuffer == NULL) -+ { -+ mvOsPrintf("testStart: Can't malloc %d bytes for cesaBinBuffer\n", -+ bufNum*bufSize); -+ return; -+ } -+ memset(cesaBinBuffer, 0, (bufNum*bufSize)); -+ -+ cesaExpBinBuffer = mvOsMalloc(bufNum*bufSize); -+ if(cesaExpBinBuffer == NULL) -+ { -+ mvOsPrintf("testStart: Can't malloc %d bytes for cesaExpBinBuffer\n", -+ bufNum*bufSize); -+ return; -+ } -+ memset(cesaExpBinBuffer, 0, (bufNum*bufSize)); -+ -+ CESA_TEST_WAIT_INIT(); -+ -+ pMbufSrc = mvOsMalloc(sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); -+ pFragsSrc = mvOsMalloc(sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); -+ -+ pMbufDst = mvOsMalloc(sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); -+ pFragsDst = mvOsMalloc(sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); -+ -+ if( (pMbufSrc == NULL) || (pFragsSrc == NULL) || -+ (pMbufDst == NULL) || (pFragsDst == NULL) ) -+ { -+ mvOsPrintf("testStart: Can't malloc Src and Dst pMbuf and pFrags structures.\n"); -+ /* !!!! Dima cesaTestCleanup();*/ -+ return; -+ } -+ -+ memset(pMbufSrc, 0, sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); -+ memset(pFragsSrc, 0, sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); -+ -+ memset(pMbufDst, 0, sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); -+ memset(pFragsDst, 0, sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); -+ -+ mvOsPrintf("Cesa Test Start: pMbufSrc=%p, pFragsSrc=%p, pMbufDst=%p, pFragsDst=%p\n", -+ pMbufSrc, pFragsSrc, pMbufDst, pFragsDst); -+ -+ idx = 0; -+ for(i=0; ipFrags = &pFragsSrc[idx]; -+ cesaCmdRing[i].pSrc->numFrags = bufNum; -+ cesaCmdRing[i].pSrc->mbufSize = 0; -+ -+ cesaCmdRing[i].pDst = &pMbufDst[i]; -+ cesaCmdRing[i].pDst->pFrags = &pFragsDst[idx]; -+ cesaCmdRing[i].pDst->numFrags = bufNum; -+ cesaCmdRing[i].pDst->mbufSize = 0; -+ -+ for(j=0; jpFrags[j].bufVirtPtr = (MV_U8*)pBuf; -+ cesaCmdRing[i].pSrc->pFrags[j].bufSize = bufSize; -+ pBuf += bufSize; -+ cesaCmdRing[i].pDst->pFrags[j].bufVirtPtr = (MV_U8*)pBuf; -+ cesaCmdRing[i].pDst->pFrags[j].bufSize = bufSize; -+ pBuf += bufSize; -+ } -+ idx += bufNum; -+ } -+ -+#ifndef MV_NETBSD -+ if (mvCpuIfTargetWinGet(CRYPT_ENG, &addrDecWin) == MV_OK) -+ pSram = (char*)addrDecWin.addrWin.baseLow; -+ else -+ { -+ mvOsPrintf("mvCesaInit: ERR. mvCpuIfTargetWinGet failed\n"); -+ return; -+ } -+ -+#ifdef MV_CESA_NO_SRAM -+ pSram = mvOsMalloc(4*1024+8); -+ if(pSram == NULL) -+ { -+ mvOsPrintf("CesaTest: can't allocate %d bytes for SRAM simulation\n", -+ 4*1024+8); -+ /* !!!! Dima cesaTestCleanup();*/ -+ return; -+ } -+ pSram = (MV_U8*)MV_ALIGN_UP((MV_U32)pSram, 8); -+#endif /* MV_CESA_NO_SRAM */ -+ -+ numOfSessions = CESA_DEF_SESSION_NUM; -+ queueDepth = CESA_DEF_REQ_SIZE - MV_CESA_MAX_CHAN; -+ -+ status = mvCesaInit(numOfSessions, queueDepth, pSram, NULL); -+ if(status != MV_OK) -+ { -+ mvOsPrintf("mvCesaInit is Failed: status = 0x%x\n", status); -+ /* !!!! Dima cesaTestCleanup();*/ -+ return; -+ } -+#endif /* !MV_NETBSD */ -+ -+ /* Prepare data for tests */ -+ for(i=0; i<50; i++) -+ strcat((char*)cesaDataHexStr3, "dd"); -+ -+ strcpy((char*)cesaDataAndMd5digest3, cesaDataHexStr3); -+ strcpy((char*)cesaDataAndSha1digest3, cesaDataHexStr3); -+ -+ /* Digest must be 8 byte aligned */ -+ for(; i<56; i++) -+ { -+ strcat((char*)cesaDataAndMd5digest3, "00"); -+ strcat((char*)cesaDataAndSha1digest3, "00"); -+ } -+ strcat((char*)cesaDataAndMd5digest3, cesaHmacMd5digestHex3); -+ strcat((char*)cesaDataAndSha1digest3, cesaHmacSha1digestHex3); -+ -+#ifndef MV_NETBSD -+ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); -+ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, MV_CESA_CAUSE_ACC_DMA_MASK); -+#endif -+ -+#ifdef MV_VXWORKS -+ { -+ MV_STATUS status; -+ -+ status = intConnect((VOIDFUNCPTR *)INT_LVL_CESA, cesaTestReadyIsr, (int)NULL); -+ if (status != OK) -+ { -+ mvOsPrintf("CESA: Can't connect CESA (%d) interrupt, status=0x%x \n", -+ INT_LVL_CESA, status); -+ /* !!!! Dima cesaTestCleanup();*/ -+ return; -+ } -+ cesaSemId = semMCreate(SEM_Q_PRIORITY | SEM_INVERSION_SAFE | SEM_DELETE_SAFE); -+ if(cesaSemId == NULL) -+ { -+ mvOsPrintf("cesaTestStart: Can't create semaphore\n"); -+ return; -+ } -+ intEnable(INT_LVL_CESA); -+ } -+#endif /* MV_VXWORKS */ -+ -+#if !defined(MV_NETBSD) && defined(__KERNEL__) -+ if( request_irq(CESA_IRQ, cesaTestReadyIsr, (SA_INTERRUPT) , "cesa_test", NULL ) ) -+ { -+ mvOsPrintf( "cannot assign irq\n" ); -+ /* !!!! Dima cesaTestCleanup();*/ -+ return; -+ } -+ spin_lock_init( &cesaLock ); -+#endif -+} -+ -+MV_STATUS testRun(int idx, int caseIdx, int iter, -+ int reqSize, int checkMode) -+{ -+ int testIdx, count, sid, digestSize; -+ int blockSize; -+ MV_CESA_TEST_SESSION* pTestSession; -+ MV_CESA_COMMAND cmd; -+ MV_STATUS status; -+ -+ memset(&cmd, 0, sizeof(cmd)); -+ -+ pTestSession = getTestSessionDb(idx, &testIdx); -+ if(pTestSession == NULL) -+ { -+ mvOsPrintf("Test %d is not exist\n", idx); -+ return MV_BAD_PARAM; -+ } -+ pTestSession = &pTestSession[testIdx]; -+ -+ sid = pTestSession->sid; -+ if(sid == -1) -+ { -+ mvOsPrintf("Test %d is not opened\n", idx); -+ return MV_BAD_STATE; -+ } -+ switch(pTestSession->cryptoAlgorithm) -+ { -+ case MV_CESA_CRYPTO_DES: -+ case MV_CESA_CRYPTO_3DES: -+ blockSize = MV_CESA_DES_BLOCK_SIZE; -+ break; -+ -+ case MV_CESA_CRYPTO_AES: -+ blockSize = MV_CESA_AES_BLOCK_SIZE; -+ break; -+ -+ case MV_CESA_CRYPTO_NULL: -+ blockSize = 0; -+ break; -+ -+ default: -+ mvOsPrintf("cesaTestRun: Bad CryptoAlgorithm=%d\n", -+ pTestSession->cryptoAlgorithm); -+ return MV_BAD_PARAM; -+ } -+ switch(pTestSession->macAlgorithm) -+ { -+ case MV_CESA_MAC_MD5: -+ case MV_CESA_MAC_HMAC_MD5: -+ digestSize = MV_CESA_MD5_DIGEST_SIZE; -+ break; -+ -+ case MV_CESA_MAC_SHA1: -+ case MV_CESA_MAC_HMAC_SHA1: -+ digestSize = MV_CESA_SHA1_DIGEST_SIZE; -+ break; -+ default: -+ digestSize = 0; -+ } -+ -+ if(iter == 0) -+ iter = CESA_DEF_ITER_NUM; -+ -+ if(pTestSession->direction == MV_CESA_DIR_ENCODE) -+ { -+ cesaOutputHexStr = cesaTestCases[caseIdx].cipherHexStr; -+ cesaInputHexStr = cesaTestCases[caseIdx].plainHexStr; -+ } -+ else -+ { -+ cesaOutputHexStr = cesaTestCases[caseIdx].plainHexStr; -+ cesaInputHexStr = cesaTestCases[caseIdx].cipherHexStr; -+ } -+ -+ cmd.sessionId = sid; -+ if(checkMode == CESA_FAST_CHECK_MODE) -+ { -+ cmd.cryptoLength = cesaTestCases[caseIdx].cryptoLength; -+ cmd.macLength = cesaTestCases[caseIdx].macLength; -+ } -+ else -+ { -+ cmd.cryptoLength = reqSize; -+ cmd.macLength = reqSize; -+ } -+ cesaRateSize = cmd.cryptoLength; -+ cesaReqSize = cmd.cryptoLength; -+ cmd.cryptoOffset = 0; -+ if(pTestSession->operation != MV_CESA_MAC_ONLY) -+ { -+ if( (pTestSession->cryptoMode == MV_CESA_CRYPTO_CBC) || -+ (pTestSession->cryptoMode == MV_CESA_CRYPTO_CTR) ) -+ { -+ cmd.ivOffset = 0; -+ cmd.cryptoOffset = blockSize; -+ if(cesaTestCases[caseIdx].pCryptoIV == NULL) -+ { -+ cmd.ivFromUser = 1; -+ } -+ else -+ { -+ cmd.ivFromUser = 0; -+ mvCesaCryptoIvSet(cesaTestCases[caseIdx].pCryptoIV, blockSize); -+ } -+ cesaReqSize = cmd.cryptoOffset + cmd.cryptoLength; -+ } -+ } -+ -+/* -+ mvOsPrintf("ivFromUser=%d, cryptoLength=%d, cesaReqSize=%d, cryptoOffset=%d\n", -+ cmd.ivFromUser, cmd.cryptoLength, cesaReqSize, cmd.cryptoOffset); -+*/ -+ if(pTestSession->operation != MV_CESA_CRYPTO_ONLY) -+ { -+ cmd.macOffset = cmd.cryptoOffset; -+ -+ if(cesaTestCases[caseIdx].digestOffset == -1) -+ { -+ cmd.digestOffset = cmd.macOffset + cmd.macLength; -+ cmd.digestOffset = MV_ALIGN_UP(cmd.digestOffset, 8); -+ } -+ else -+ { -+ cmd.digestOffset = cesaTestCases[caseIdx].digestOffset; -+ } -+ if( (cmd.digestOffset + digestSize) > cesaReqSize) -+ cesaReqSize = cmd.digestOffset + digestSize; -+ } -+ -+ cesaCheckMode = checkMode; -+ -+ if(checkMode == CESA_NULL_CHECK_MODE) -+ { -+ cesaCheckSize = 0; -+ cesaCheckOffset = 0; -+ } -+ else -+ { -+ if(pTestSession->operation == MV_CESA_CRYPTO_ONLY) -+ { -+ cesaCheckOffset = 0; -+ cesaCheckSize = cmd.cryptoLength; -+ } -+ else -+ { -+ cesaCheckSize = digestSize; -+ cesaCheckOffset = cmd.digestOffset; -+ } -+ } -+/* -+ mvOsPrintf("reqSize=%d, checkSize=%d, checkOffset=%d, checkMode=%d\n", -+ cesaReqSize, cesaCheckSize, cesaCheckOffset, cesaCheckMode); -+ -+ mvOsPrintf("blockSize=%d, ivOffset=%d, ivFromUser=%d, crOffset=%d, crLength=%d\n", -+ blockSize, cmd.ivOffset, cmd.ivFromUser, -+ cmd.cryptoOffset, cmd.cryptoLength); -+ -+ mvOsPrintf("macOffset=%d, digestOffset=%d, macLength=%d\n", -+ cmd.macOffset, cmd.digestOffset, cmd.macLength); -+*/ -+ status = testCmd(sid, iter, &cmd, pTestSession, -+ cesaTestCases[caseIdx].pCryptoIV, blockSize); -+ -+ if(status != MV_OK) -+ return status; -+ -+ /* Wait when all callbacks is received */ -+ count = 0; -+ while(cesaIsReady == MV_FALSE) -+ { -+ mvOsSleep(10); -+ count++; -+ if(count > 100) -+ { -+ mvOsPrintf("testRun: Timeout occured\n"); -+ return MV_TIMEOUT; -+ } -+ } -+ -+ return MV_OK; -+} -+ -+ -+void cesaTestStop(void) -+{ -+ MV_CESA_MBUF *pMbufSrc, *pMbufDst; -+ MV_BUF_INFO *pFragsSrc, *pFragsDst; -+ int i; -+ -+ /* Release all allocated memories */ -+ pMbufSrc = (MV_CESA_MBUF*)(cesaCmdRing[0].pSrc); -+ pFragsSrc = cesaCmdRing[0].pSrc->pFrags; -+ -+ pMbufDst = (MV_CESA_MBUF*)(cesaCmdRing[0].pDst); -+ pFragsDst = cesaCmdRing[0].pDst->pFrags; -+ -+ mvOsFree(pMbufSrc); -+ mvOsFree(pMbufDst); -+ mvOsFree(pFragsSrc); -+ mvOsFree(pFragsDst); -+ -+ for(i=0; i 0) -+ cryptoError++; -+ if(cesaReqIdError > 0) -+ reqIdError++; -+ -+ testClose(idx); -+ } -+ } -+ if(cryptoError > 0) -+ mvOsPrintf("cryptoError : %d\n", cryptoError); -+ if(reqIdError > 0) -+ mvOsPrintf("reqIdError : %d\n", reqIdError); -+ -+ if(openErrors > 0) -+ { -+ mvOsPrintf("Open Errors = %d\n", openErrors); -+ for(i=0; i<100; i++) -+ { -+ if(openErrDisp[i] != 0) -+ mvOsPrintf("Error %d - occurs %d times\n", i, openErrDisp[i]); -+ } -+ } -+} -+ -+ -+void loopback_test(int idx, int iter, int size, char* pPlainData) -+{ -+} -+ -+ -+#if defined(MV_VXWORKS) -+int testMode = 0; -+unsigned __TASKCONV cesaTask(void* args) -+{ -+ int reqSize = cesaReqSize; -+ -+ if(testMode == 0) -+ { -+ cesaOneTest(cesaTestIdx, cesaCaseIdx, cesaIteration, -+ reqSize, cesaCheckMode); -+ } -+ else -+ { -+ if(testMode == 1) -+ { -+ cesaTest(cesaIteration, reqSize, cesaCheckMode); -+ combiTest(cesaIteration, reqSize, cesaCheckMode); -+ } -+ else -+ { -+ multiSizeTest(cesaIdx, cesaIteration, cesaCheckMode, NULL); -+ } -+ } -+ return 0; -+} -+ -+void oneTest(int testIdx, int caseIdx, -+ int iter, int reqSize, int checkMode) -+{ -+ long rc; -+ -+ cesaIteration = iter; -+ cesaReqSize = cesaRateSize = reqSize; -+ cesaCheckMode = checkMode; -+ testMode = 0; -+ cesaTestIdx = testIdx; -+ cesaCaseIdx = caseIdx; -+ rc = mvOsTaskCreate("CESA_T", 100, 4*1024, cesaTask, NULL, &cesaTaskId); -+ if (rc != MV_OK) -+ { -+ mvOsPrintf("hMW: Can't create CESA multiCmd test task, rc = %ld\n", rc); -+ } -+} -+ -+void multiTest(int iter, int reqSize, int checkMode) -+{ -+ long rc; -+ -+ cesaIteration = iter; -+ cesaCheckMode = checkMode; -+ cesaReqSize = reqSize; -+ testMode = 1; -+ rc = mvOsTaskCreate("CESA_T", 100, 4*1024, cesaTask, NULL, &cesaTaskId); -+ if (rc != MV_OK) -+ { -+ mvOsPrintf("hMW: Can't create CESA multiCmd test task, rc = %ld\n", rc); -+ } -+} -+ -+void sizeTest(int testIdx, int iter, int checkMode) -+{ -+ long rc; -+ -+ cesaIteration = iter; -+ cesaCheckMode = checkMode; -+ testMode = 2; -+ cesaIdx = testIdx; -+ rc = mvOsTaskCreate("CESA_T", 100, 4*1024, cesaTask, NULL, &cesaTaskId); -+ if (rc != MV_OK) -+ { -+ mvOsPrintf("hMW: Can't create CESA test task, rc = %ld\n", rc); -+ } -+} -+ -+#endif /* MV_VXWORKS */ -+ -+extern void mvCesaDebugSA(short sid, int mode); -+void cesaTestPrintSession(int idx) -+{ -+ int testIdx; -+ MV_CESA_TEST_SESSION* pTestSession; -+ -+ pTestSession = getTestSessionDb(idx, &testIdx); -+ if(pTestSession == NULL) -+ { -+ mvOsPrintf("Test %d is not exist\n", idx); -+ return; -+ } -+ pTestSession = &pTestSession[testIdx]; -+ -+ if(pTestSession->sid == -1) -+ { -+ mvOsPrintf("Test session %d is not opened\n", idx); -+ return; -+ } -+ -+ mvCesaDebugSA(pTestSession->sid, 1); -+} -+ -+void cesaTestPrintStatus(void) -+{ -+ mvOsPrintf("\n\t Cesa Test Status\n\n"); -+ -+ mvOsPrintf("isrCount=%d\n", -+ cesaTestIsrCount); -+ -+#ifdef CESA_TEST_DEBUG -+ { -+ int i, j; -+ j = cesaTestTraceIdx; -+ mvOsPrintf("No Type Cause rCause iCause Res Time pReady pProc pEmpty\n"); -+ for(i=0; itable = mvOsMalloc(numOfEntries*sizeof(MV_LRU_ENTRY)); -+ if(pLruCache->table == NULL) -+ { -+ mvOsFree(pLruCache); -+ return NULL; -+ } -+ memset(pLruCache->table, 0, numOfEntries*sizeof(MV_LRU_ENTRY)); -+ pLruCache->tableSize = numOfEntries; -+ -+ for(i=0; itable[i].next = i+1; -+ pLruCache->table[i].prev = i-1; -+ } -+ pLruCache->least = 0; -+ pLruCache->most = numOfEntries-1; -+ -+ return pLruCache; -+} -+ -+void mvLruCacheFinish(MV_LRU_CACHE* pLruCache) -+{ -+ mvOsFree(pLruCache->table); -+ mvOsFree(pLruCache); -+} -+ -+/* Update LRU cache database after using cache Index */ -+void mvLruCacheIdxUpdate(MV_LRU_CACHE* pLruHndl, int cacheIdx) -+{ -+ int prev, next; -+ -+ if(cacheIdx == pLruHndl->most) -+ return; -+ -+ next = pLruHndl->table[cacheIdx].next; -+ if(cacheIdx == pLruHndl->least) -+ { -+ pLruHndl->least = next; -+ } -+ else -+ { -+ prev = pLruHndl->table[cacheIdx].prev; -+ -+ pLruHndl->table[next].prev = prev; -+ pLruHndl->table[prev].next = next; -+ } -+ -+ pLruHndl->table[pLruHndl->most].next = cacheIdx; -+ pLruHndl->table[cacheIdx].prev = pLruHndl->most; -+ pLruHndl->most = cacheIdx; -+} -+ -+/* Delete LRU cache entry */ -+void mvLruCacheIdxDelete(MV_LRU_CACHE* pLruHndl, int cacheIdx) -+{ -+ int prev, next; -+ -+ if(cacheIdx == pLruHndl->least) -+ return; -+ -+ prev = pLruHndl->table[cacheIdx].prev; -+ if(cacheIdx == pLruHndl->most) -+ { -+ pLruHndl->most = prev; -+ } -+ else -+ { -+ next = pLruHndl->table[cacheIdx].next; -+ -+ pLruHndl->table[next].prev = prev; -+ pLruHndl->table[prev].next = next; -+ } -+ pLruHndl->table[pLruHndl->least].prev = cacheIdx; -+ pLruHndl->table[cacheIdx].next = pLruHndl->least; -+ pLruHndl->least = cacheIdx; -+} -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/cesa/mvLru.h linux-2.6.36/crypto/ocf/kirkwood/cesa/mvLru.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/cesa/mvLru.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/cesa/mvLru.h 2010-11-09 20:28:05.861235773 +0100 -@@ -0,0 +1,112 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+/******************************************************************************* -+* mvLru.h - Header File for Least Recently Used Cache algorithm -+* -+* DESCRIPTION: -+* This header file contains macros typedefs and function declaration for -+* the Least Recently Used Cache algorithm. -+* -+*******************************************************************************/ -+ -+#ifndef __mvLru_h__ -+#define __mvLru_h__ -+ -+ -+typedef struct -+{ -+ int next; -+ int prev; -+} MV_LRU_ENTRY; -+ -+typedef struct -+{ -+ int least; -+ int most; -+ MV_LRU_ENTRY* table; -+ int tableSize; -+ -+}MV_LRU_CACHE; -+ -+ -+/* Find Cache index for replacement LRU */ -+static INLINE int mvLruCacheIdxFind(MV_LRU_CACHE* pLruHndl) -+{ -+ return pLruHndl->least; -+} -+ -+/* Init LRU cache module */ -+MV_LRU_CACHE* mvLruCacheInit(int numOfEntries); -+ -+/* Finish LRU cache module */ -+void mvLruCacheFinish(MV_LRU_CACHE* pLruHndl); -+ -+/* Update LRU cache database after using cache Index */ -+void mvLruCacheIdxUpdate(MV_LRU_CACHE* pLruHndl, int cacheIdx); -+ -+/* Delete LRU cache entry */ -+void mvLruCacheIdxDelete(MV_LRU_CACHE* pLruHndl, int cacheIdx); -+ -+ -+#endif /* __mvLru_h__ */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/cesa/mvMD5.c linux-2.6.36/crypto/ocf/kirkwood/cesa/mvMD5.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/cesa/mvMD5.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/cesa/mvMD5.c 2010-11-09 20:28:05.902495799 +0100 -@@ -0,0 +1,349 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "mvOs.h" -+#include "mvMD5.h" -+ -+static void mvMD5Transform(MV_U32 buf[4], MV_U32 const in[MV_MD5_MAC_LEN]); -+ -+#ifdef MV_CPU_LE -+#define mvByteReverse(buf, len) /* Nothing */ -+#else -+static void mvByteReverse(unsigned char *buf, unsigned longs); -+ -+/* -+ * Note: this code is harmless on little-endian machines. -+ */ -+static void mvByteReverse(unsigned char *buf, unsigned longs) -+{ -+ MV_U32 t; -+ -+ do -+ { -+ t = (MV_U32) ((unsigned) buf[3] << 8 | buf[2]) << 16 | -+ ((unsigned) buf[1] << 8 | buf[0]); -+ *(MV_U32 *) buf = t; -+ buf += 4; -+ } while (--longs); -+} -+#endif -+ -+/* -+ * Start MD5 accumulation. Set bit count to 0 and buffer to mysterious -+ * initialization constants. -+ */ -+void mvMD5Init(MV_MD5_CONTEXT *ctx) -+{ -+ ctx->buf[0] = 0x67452301; -+ ctx->buf[1] = 0xefcdab89; -+ ctx->buf[2] = 0x98badcfe; -+ ctx->buf[3] = 0x10325476; -+ -+ ctx->bits[0] = 0; -+ ctx->bits[1] = 0; -+} -+ -+/* -+ * Update context to reflect the concatenation of another buffer full -+ * of bytes. -+ */ -+void mvMD5Update(MV_MD5_CONTEXT *ctx, unsigned char const *buf, unsigned len) -+{ -+ MV_U32 t; -+ -+ /* Update bitcount */ -+ -+ t = ctx->bits[0]; -+ if ((ctx->bits[0] = t + ((MV_U32) len << 3)) < t) -+ ctx->bits[1]++; /* Carry from low to high */ -+ ctx->bits[1] += len >> 29; -+ -+ t = (t >> 3) & 0x3f; /* Bytes already in shsInfo->data */ -+ -+ /* Handle any leading odd-sized chunks */ -+ -+ if (t) -+ { -+ unsigned char *p = (unsigned char *) ctx->in + t; -+ -+ t = 64 - t; -+ if (len < t) -+ { -+ memcpy(p, buf, len); -+ return; -+ } -+ memcpy(p, buf, t); -+ mvByteReverse(ctx->in, MV_MD5_MAC_LEN); -+ mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in); -+ buf += t; -+ len -= t; -+ } -+ /* Process data in 64-byte chunks */ -+ -+ while (len >= 64) -+ { -+ memcpy(ctx->in, buf, 64); -+ mvByteReverse(ctx->in, MV_MD5_MAC_LEN); -+ mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in); -+ buf += 64; -+ len -= 64; -+ } -+ -+ /* Handle any remaining bytes of data. */ -+ -+ memcpy(ctx->in, buf, len); -+} -+ -+/* -+ * Final wrapup - pad to 64-byte boundary with the bit pattern -+ * 1 0* (64-bit count of bits processed, MSB-first) -+ */ -+void mvMD5Final(unsigned char digest[MV_MD5_MAC_LEN], MV_MD5_CONTEXT *ctx) -+{ -+ unsigned count; -+ unsigned char *p; -+ -+ /* Compute number of bytes mod 64 */ -+ count = (ctx->bits[0] >> 3) & 0x3F; -+ -+ /* Set the first char of padding to 0x80. This is safe since there is -+ always at least one byte free */ -+ p = ctx->in + count; -+ *p++ = 0x80; -+ -+ /* Bytes of padding needed to make 64 bytes */ -+ count = 64 - 1 - count; -+ -+ /* Pad out to 56 mod 64 */ -+ if (count < 8) -+ { -+ /* Two lots of padding: Pad the first block to 64 bytes */ -+ memset(p, 0, count); -+ mvByteReverse(ctx->in, MV_MD5_MAC_LEN); -+ mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in); -+ -+ /* Now fill the next block with 56 bytes */ -+ memset(ctx->in, 0, 56); -+ } -+ else -+ { -+ /* Pad block to 56 bytes */ -+ memset(p, 0, count - 8); -+ } -+ mvByteReverse(ctx->in, 14); -+ -+ /* Append length in bits and transform */ -+ ((MV_U32 *) ctx->in)[14] = ctx->bits[0]; -+ ((MV_U32 *) ctx->in)[15] = ctx->bits[1]; -+ -+ mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in); -+ mvByteReverse((unsigned char *) ctx->buf, 4); -+ memcpy(digest, ctx->buf, MV_MD5_MAC_LEN); -+ memset(ctx, 0, sizeof(ctx)); /* In case it's sensitive */ -+} -+ -+/* The four core functions - F1 is optimized somewhat */ -+ -+/* #define F1(x, y, z) (x & y | ~x & z) */ -+#define F1(x, y, z) (z ^ (x & (y ^ z))) -+#define F2(x, y, z) F1(z, x, y) -+#define F3(x, y, z) (x ^ y ^ z) -+#define F4(x, y, z) (y ^ (x | ~z)) -+ -+/* This is the central step in the MD5 algorithm. */ -+#define MD5STEP(f, w, x, y, z, data, s) \ -+ ( w += f(x, y, z) + data, w = w<>(32-s), w += x ) -+ -+/* -+ * The core of the MD5 algorithm, this alters an existing MD5 hash to -+ * reflect the addition of 16 longwords of new data. MD5Update blocks -+ * the data and converts bytes into longwords for this routine. -+ */ -+static void mvMD5Transform(MV_U32 buf[4], MV_U32 const in[MV_MD5_MAC_LEN]) -+{ -+ register MV_U32 a, b, c, d; -+ -+ a = buf[0]; -+ b = buf[1]; -+ c = buf[2]; -+ d = buf[3]; -+ -+ MD5STEP(F1, a, b, c, d, in[0] + 0xd76aa478, 7); -+ MD5STEP(F1, d, a, b, c, in[1] + 0xe8c7b756, 12); -+ MD5STEP(F1, c, d, a, b, in[2] + 0x242070db, 17); -+ MD5STEP(F1, b, c, d, a, in[3] + 0xc1bdceee, 22); -+ MD5STEP(F1, a, b, c, d, in[4] + 0xf57c0faf, 7); -+ MD5STEP(F1, d, a, b, c, in[5] + 0x4787c62a, 12); -+ MD5STEP(F1, c, d, a, b, in[6] + 0xa8304613, 17); -+ MD5STEP(F1, b, c, d, a, in[7] + 0xfd469501, 22); -+ MD5STEP(F1, a, b, c, d, in[8] + 0x698098d8, 7); -+ MD5STEP(F1, d, a, b, c, in[9] + 0x8b44f7af, 12); -+ MD5STEP(F1, c, d, a, b, in[10] + 0xffff5bb1, 17); -+ MD5STEP(F1, b, c, d, a, in[11] + 0x895cd7be, 22); -+ MD5STEP(F1, a, b, c, d, in[12] + 0x6b901122, 7); -+ MD5STEP(F1, d, a, b, c, in[13] + 0xfd987193, 12); -+ MD5STEP(F1, c, d, a, b, in[14] + 0xa679438e, 17); -+ MD5STEP(F1, b, c, d, a, in[15] + 0x49b40821, 22); -+ -+ MD5STEP(F2, a, b, c, d, in[1] + 0xf61e2562, 5); -+ MD5STEP(F2, d, a, b, c, in[6] + 0xc040b340, 9); -+ MD5STEP(F2, c, d, a, b, in[11] + 0x265e5a51, 14); -+ MD5STEP(F2, b, c, d, a, in[0] + 0xe9b6c7aa, 20); -+ MD5STEP(F2, a, b, c, d, in[5] + 0xd62f105d, 5); -+ MD5STEP(F2, d, a, b, c, in[10] + 0x02441453, 9); -+ MD5STEP(F2, c, d, a, b, in[15] + 0xd8a1e681, 14); -+ MD5STEP(F2, b, c, d, a, in[4] + 0xe7d3fbc8, 20); -+ MD5STEP(F2, a, b, c, d, in[9] + 0x21e1cde6, 5); -+ MD5STEP(F2, d, a, b, c, in[14] + 0xc33707d6, 9); -+ MD5STEP(F2, c, d, a, b, in[3] + 0xf4d50d87, 14); -+ MD5STEP(F2, b, c, d, a, in[8] + 0x455a14ed, 20); -+ MD5STEP(F2, a, b, c, d, in[13] + 0xa9e3e905, 5); -+ MD5STEP(F2, d, a, b, c, in[2] + 0xfcefa3f8, 9); -+ MD5STEP(F2, c, d, a, b, in[7] + 0x676f02d9, 14); -+ MD5STEP(F2, b, c, d, a, in[12] + 0x8d2a4c8a, 20); -+ -+ MD5STEP(F3, a, b, c, d, in[5] + 0xfffa3942, 4); -+ MD5STEP(F3, d, a, b, c, in[8] + 0x8771f681, 11); -+ MD5STEP(F3, c, d, a, b, in[11] + 0x6d9d6122, 16); -+ MD5STEP(F3, b, c, d, a, in[14] + 0xfde5380c, 23); -+ MD5STEP(F3, a, b, c, d, in[1] + 0xa4beea44, 4); -+ MD5STEP(F3, d, a, b, c, in[4] + 0x4bdecfa9, 11); -+ MD5STEP(F3, c, d, a, b, in[7] + 0xf6bb4b60, 16); -+ MD5STEP(F3, b, c, d, a, in[10] + 0xbebfbc70, 23); -+ MD5STEP(F3, a, b, c, d, in[13] + 0x289b7ec6, 4); -+ MD5STEP(F3, d, a, b, c, in[0] + 0xeaa127fa, 11); -+ MD5STEP(F3, c, d, a, b, in[3] + 0xd4ef3085, 16); -+ MD5STEP(F3, b, c, d, a, in[6] + 0x04881d05, 23); -+ MD5STEP(F3, a, b, c, d, in[9] + 0xd9d4d039, 4); -+ MD5STEP(F3, d, a, b, c, in[12] + 0xe6db99e5, 11); -+ MD5STEP(F3, c, d, a, b, in[15] + 0x1fa27cf8, 16); -+ MD5STEP(F3, b, c, d, a, in[2] + 0xc4ac5665, 23); -+ -+ MD5STEP(F4, a, b, c, d, in[0] + 0xf4292244, 6); -+ MD5STEP(F4, d, a, b, c, in[7] + 0x432aff97, 10); -+ MD5STEP(F4, c, d, a, b, in[14] + 0xab9423a7, 15); -+ MD5STEP(F4, b, c, d, a, in[5] + 0xfc93a039, 21); -+ MD5STEP(F4, a, b, c, d, in[12] + 0x655b59c3, 6); -+ MD5STEP(F4, d, a, b, c, in[3] + 0x8f0ccc92, 10); -+ MD5STEP(F4, c, d, a, b, in[10] + 0xffeff47d, 15); -+ MD5STEP(F4, b, c, d, a, in[1] + 0x85845dd1, 21); -+ MD5STEP(F4, a, b, c, d, in[8] + 0x6fa87e4f, 6); -+ MD5STEP(F4, d, a, b, c, in[15] + 0xfe2ce6e0, 10); -+ MD5STEP(F4, c, d, a, b, in[6] + 0xa3014314, 15); -+ MD5STEP(F4, b, c, d, a, in[13] + 0x4e0811a1, 21); -+ MD5STEP(F4, a, b, c, d, in[4] + 0xf7537e82, 6); -+ MD5STEP(F4, d, a, b, c, in[11] + 0xbd3af235, 10); -+ MD5STEP(F4, c, d, a, b, in[2] + 0x2ad7d2bb, 15); -+ MD5STEP(F4, b, c, d, a, in[9] + 0xeb86d391, 21); -+ -+ buf[0] += a; -+ buf[1] += b; -+ buf[2] += c; -+ buf[3] += d; -+} -+ -+void mvMD5(unsigned char const *buf, unsigned len, unsigned char* digest) -+{ -+ MV_MD5_CONTEXT ctx; -+ -+ mvMD5Init(&ctx); -+ mvMD5Update(&ctx, buf, len); -+ mvMD5Final(digest, &ctx); -+} -+ -+ -+void mvHmacMd5(unsigned char const* text, int text_len, -+ unsigned char const* key, int key_len, -+ unsigned char* digest) -+{ -+ int i; -+ MV_MD5_CONTEXT ctx; -+ unsigned char k_ipad[64+1]; /* inner padding - key XORd with ipad */ -+ unsigned char k_opad[64+1]; /* outer padding - key XORd with opad */ -+ -+ /* start out by storing key in pads */ -+ memset(k_ipad, 0, 64); -+ memcpy(k_ipad, key, key_len); -+ memset(k_opad, 0, 64); -+ memcpy(k_opad, key, key_len); -+ -+ /* XOR key with ipad and opad values */ -+ for (i=0; i<64; i++) -+ { -+ k_ipad[i] ^= 0x36; -+ k_opad[i] ^= 0x5c; -+ } -+ -+ /* perform inner MD5 */ -+ mvMD5Init(&ctx); /* init ctx for 1st pass */ -+ mvMD5Update(&ctx, k_ipad, 64); /* start with inner pad */ -+ mvMD5Update(&ctx, text, text_len); /* then text of datagram */ -+ mvMD5Final(digest, &ctx); /* finish up 1st pass */ -+ -+ /* perform outer MD5 */ -+ mvMD5Init(&ctx); /* init ctx for 2nd pass */ -+ mvMD5Update(&ctx, k_opad, 64); /* start with outer pad */ -+ mvMD5Update(&ctx, digest, 16); /* then results of 1st hash */ -+ mvMD5Final(digest, &ctx); /* finish up 2nd pass */ -+} -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/cesa/mvMD5.h linux-2.6.36/crypto/ocf/kirkwood/cesa/mvMD5.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/cesa/mvMD5.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/cesa/mvMD5.h 2010-11-09 20:28:05.942495390 +0100 -@@ -0,0 +1,93 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __mvMD5_h__ -+#define __mvMD5_h__ -+ -+#include "mvMD5.h" -+ -+#define MV_MD5_MAC_LEN 16 -+ -+ -+typedef struct -+{ -+ MV_U32 buf[4]; -+ MV_U32 bits[2]; -+ MV_U8 in[64]; -+ -+} MV_MD5_CONTEXT; -+ -+void mvMD5Init(MV_MD5_CONTEXT *context); -+void mvMD5Update(MV_MD5_CONTEXT *context, unsigned char const *buf, -+ unsigned len); -+void mvMD5Final(unsigned char digest[16], MV_MD5_CONTEXT *context); -+ -+void mvMD5(unsigned char const *buf, unsigned len, unsigned char* digest); -+ -+void mvHmacMd5(unsigned char const* text, int text_len, -+ unsigned char const* key, int key_len, -+ unsigned char* digest); -+ -+ -+#endif /* __mvMD5_h__ */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/cesa/mvSHA1.c linux-2.6.36/crypto/ocf/kirkwood/cesa/mvSHA1.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/cesa/mvSHA1.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/cesa/mvSHA1.c 2010-11-09 20:28:05.972495400 +0100 -@@ -0,0 +1,239 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "mvOs.h" -+#include "mvSHA1.h" -+ -+#define SHA1HANDSOFF -+ -+typedef union -+{ -+ MV_U8 c[64]; -+ MV_U32 l[16]; -+ -+} CHAR64LONG16; -+ -+static void mvSHA1Transform(MV_U32 state[5], const MV_U8 *buffer); -+ -+#define rol(value, bits) (((value) << (bits)) | ((value) >> (32 - (bits)))) -+ -+ -+#ifdef MV_CPU_LE -+#define blk0(i) (block->l[i] = (rol(block->l[i], 24) & 0xFF00FF00) | \ -+ (rol(block->l[i], 8) & 0x00FF00FF)) -+#else -+#define blk0(i) block->l[i] -+#endif -+#define blk(i) (block->l[i & 15] = rol(block->l[(i + 13) & 15] ^ \ -+ block->l[(i + 8) & 15] ^ block->l[(i + 2) & 15] ^ block->l[i & 15], 1)) -+ -+/* (R0+R1), R2, R3, R4 are the different operations used in SHA1 */ -+#define R0(v,w,x,y,z,i) \ -+ z += ((w & (x ^ y)) ^ y) + blk0(i) + 0x5A827999 + rol(v, 5); \ -+ w = rol(w, 30); -+#define R1(v,w,x,y,z,i) \ -+ z += ((w & (x ^ y)) ^ y) + blk(i) + 0x5A827999 + rol(v, 5); \ -+ w = rol(w, 30); -+#define R2(v,w,x,y,z,i) \ -+ z += (w ^ x ^ y) + blk(i) + 0x6ED9EBA1 + rol(v, 5); w = rol(w, 30); -+#define R3(v,w,x,y,z,i) \ -+ z += (((w | x) & y) | (w & x)) + blk(i) + 0x8F1BBCDC + rol(v, 5); \ -+ w = rol(w, 30); -+#define R4(v,w,x,y,z,i) \ -+ z += (w ^ x ^ y) + blk(i) + 0xCA62C1D6 + rol(v, 5); \ -+ w=rol(w, 30); -+ -+/* Hash a single 512-bit block. This is the core of the algorithm. */ -+static void mvSHA1Transform(MV_U32 state[5], const MV_U8 *buffer) -+{ -+ MV_U32 a, b, c, d, e; -+ CHAR64LONG16* block; -+ -+#ifdef SHA1HANDSOFF -+ static MV_U32 workspace[16]; -+ -+ block = (CHAR64LONG16 *) workspace; -+ memcpy(block, buffer, 64); -+#else -+ block = (CHAR64LONG16 *) buffer; -+#endif -+ /* Copy context->state[] to working vars */ -+ a = state[0]; -+ b = state[1]; -+ c = state[2]; -+ d = state[3]; -+ e = state[4]; -+ /* 4 rounds of 20 operations each. Loop unrolled. */ -+ R0(a,b,c,d,e, 0); R0(e,a,b,c,d, 1); R0(d,e,a,b,c, 2); R0(c,d,e,a,b, 3); -+ R0(b,c,d,e,a, 4); R0(a,b,c,d,e, 5); R0(e,a,b,c,d, 6); R0(d,e,a,b,c, 7); -+ R0(c,d,e,a,b, 8); R0(b,c,d,e,a, 9); R0(a,b,c,d,e,10); R0(e,a,b,c,d,11); -+ R0(d,e,a,b,c,12); R0(c,d,e,a,b,13); R0(b,c,d,e,a,14); R0(a,b,c,d,e,15); -+ R1(e,a,b,c,d,16); R1(d,e,a,b,c,17); R1(c,d,e,a,b,18); R1(b,c,d,e,a,19); -+ R2(a,b,c,d,e,20); R2(e,a,b,c,d,21); R2(d,e,a,b,c,22); R2(c,d,e,a,b,23); -+ R2(b,c,d,e,a,24); R2(a,b,c,d,e,25); R2(e,a,b,c,d,26); R2(d,e,a,b,c,27); -+ R2(c,d,e,a,b,28); R2(b,c,d,e,a,29); R2(a,b,c,d,e,30); R2(e,a,b,c,d,31); -+ R2(d,e,a,b,c,32); R2(c,d,e,a,b,33); R2(b,c,d,e,a,34); R2(a,b,c,d,e,35); -+ R2(e,a,b,c,d,36); R2(d,e,a,b,c,37); R2(c,d,e,a,b,38); R2(b,c,d,e,a,39); -+ R3(a,b,c,d,e,40); R3(e,a,b,c,d,41); R3(d,e,a,b,c,42); R3(c,d,e,a,b,43); -+ R3(b,c,d,e,a,44); R3(a,b,c,d,e,45); R3(e,a,b,c,d,46); R3(d,e,a,b,c,47); -+ R3(c,d,e,a,b,48); R3(b,c,d,e,a,49); R3(a,b,c,d,e,50); R3(e,a,b,c,d,51); -+ R3(d,e,a,b,c,52); R3(c,d,e,a,b,53); R3(b,c,d,e,a,54); R3(a,b,c,d,e,55); -+ R3(e,a,b,c,d,56); R3(d,e,a,b,c,57); R3(c,d,e,a,b,58); R3(b,c,d,e,a,59); -+ R4(a,b,c,d,e,60); R4(e,a,b,c,d,61); R4(d,e,a,b,c,62); R4(c,d,e,a,b,63); -+ R4(b,c,d,e,a,64); R4(a,b,c,d,e,65); R4(e,a,b,c,d,66); R4(d,e,a,b,c,67); -+ R4(c,d,e,a,b,68); R4(b,c,d,e,a,69); R4(a,b,c,d,e,70); R4(e,a,b,c,d,71); -+ R4(d,e,a,b,c,72); R4(c,d,e,a,b,73); R4(b,c,d,e,a,74); R4(a,b,c,d,e,75); -+ R4(e,a,b,c,d,76); R4(d,e,a,b,c,77); R4(c,d,e,a,b,78); R4(b,c,d,e,a,79); -+ /* Add the working vars back into context.state[] */ -+ state[0] += a; -+ state[1] += b; -+ state[2] += c; -+ state[3] += d; -+ state[4] += e; -+ /* Wipe variables */ -+ a = b = c = d = e = 0; -+} -+ -+void mvSHA1Init(MV_SHA1_CTX* context) -+{ -+ /* SHA1 initialization constants */ -+ context->state[0] = 0x67452301; -+ context->state[1] = 0xEFCDAB89; -+ context->state[2] = 0x98BADCFE; -+ context->state[3] = 0x10325476; -+ context->state[4] = 0xC3D2E1F0; -+ context->count[0] = context->count[1] = 0; -+} -+ -+ -+/* Run your data through this. */ -+void mvSHA1Update(MV_SHA1_CTX *context, MV_U8 const *data, -+ unsigned int len) -+{ -+ MV_U32 i, j; -+ -+ j = (context->count[0] >> 3) & 63; -+ if ((context->count[0] += len << 3) < (len << 3)) -+ context->count[1]++; -+ context->count[1] += (len >> 29); -+ if ((j + len) > 63) -+ { -+ memcpy(&context->buffer[j], data, (i = 64-j)); -+ mvSHA1Transform(context->state, context->buffer); -+ for ( ; i + 63 < len; i += 64) -+ { -+ mvSHA1Transform(context->state, &data[i]); -+ } -+ j = 0; -+ } -+ else -+ { -+ i = 0; -+ } -+ memcpy(&context->buffer[j], &data[i], len - i); -+} -+ -+void mvSHA1Final(MV_U8* digest, MV_SHA1_CTX* context) -+{ -+ MV_U32 i; -+ MV_U8 finalcount[8]; -+ -+ for (i = 0; i < 8; i++) -+ { -+ finalcount[i] = (unsigned char)((context->count[(i >= 4 ? 0 : 1)] >> -+ ((3-(i & 3)) * 8) ) & 255); /* Endian independent */ -+ } -+ mvSHA1Update(context, (const unsigned char *) "\200", 1); -+ while ((context->count[0] & 504) != 448) -+ { -+ mvSHA1Update(context, (const unsigned char *) "\0", 1); -+ } -+ mvSHA1Update(context, finalcount, 8); /* Should cause a mvSHA1Transform() -+ */ -+ for (i = 0; i < 20; i++) -+ { -+ digest[i] = (unsigned char) -+ ((context->state[i >> 2] >> ((3 - (i & 3)) * 8)) & 255); -+ } -+ /* Wipe variables */ -+ i = 0; -+ memset(context->buffer, 0, 64); -+ memset(context->state, 0, 20); -+ memset(context->count, 0, 8); -+ memset(finalcount, 0, 8); -+ -+#ifdef SHA1HANDSOFF /* make SHA1Transform overwrite it's own static vars */ -+ mvSHA1Transform(context->state, context->buffer); -+#endif -+} -+ -+ -+void mvSHA1(MV_U8 const *buf, unsigned int len, MV_U8* digest) -+{ -+ MV_SHA1_CTX ctx; -+ -+ mvSHA1Init(&ctx); -+ mvSHA1Update(&ctx, buf, len); -+ mvSHA1Final(digest, &ctx); -+} -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/cesa/mvSHA1.h linux-2.6.36/crypto/ocf/kirkwood/cesa/mvSHA1.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/cesa/mvSHA1.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/cesa/mvSHA1.h 2010-11-09 20:28:06.012495345 +0100 -@@ -0,0 +1,88 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __mvSHA1_h__ -+#define __mvSHA1_h__ -+ -+#include "mvSHA1.h" -+ -+#define MV_SHA1_MAC_LEN 20 -+ -+ -+typedef struct -+{ -+ MV_U32 state[5]; -+ MV_U32 count[2]; -+ MV_U8 buffer[64]; -+ -+} MV_SHA1_CTX; -+ -+void mvSHA1Init(MV_SHA1_CTX *context); -+void mvSHA1Update(MV_SHA1_CTX *context, MV_U8 const *buf, unsigned int len); -+void mvSHA1Final(MV_U8* digest, MV_SHA1_CTX *context); -+ -+void mvSHA1(MV_U8 const *buf, unsigned int len, MV_U8* digest); -+ -+ -+#endif /* __mvSHA1_h__ */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/cesa_ocf_drv.c linux-2.6.36/crypto/ocf/kirkwood/cesa_ocf_drv.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/cesa_ocf_drv.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/cesa_ocf_drv.c 2010-11-09 20:28:06.052495403 +0100 -@@ -0,0 +1,1296 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+*******************************************************************************/ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "ctrlEnv/sys/mvSysCesa.h" -+#include "cesa/mvCesa.h" /* moved here before cryptodev.h due to include dependencies */ -+#include -+#include -+#include -+#include -+#include "mvDebug.h" -+ -+#include "cesa/mvMD5.h" -+#include "cesa/mvSHA1.h" -+ -+#include "cesa/mvCesaRegs.h" -+#include "cesa/AES/mvAes.h" -+#include "cesa/mvLru.h" -+ -+#undef RT_DEBUG -+#ifdef RT_DEBUG -+static int debug = 1; -+module_param(debug, int, 1); -+MODULE_PARM_DESC(debug, "Enable debug"); -+#undef dprintk -+#define dprintk(a...) if (debug) { printk(a); } else -+#else -+static int debug = 0; -+#undef dprintk -+#define dprintk(a...) -+#endif -+ -+ -+/* TDMA Regs */ -+#define WINDOW_BASE(i) 0xA00 + (i << 3) -+#define WINDOW_CTRL(i) 0xA04 + (i << 3) -+ -+/* interrupt handling */ -+#undef CESA_OCF_POLLING -+#undef CESA_OCF_TASKLET -+ -+#if defined(CESA_OCF_POLLING) && defined(CESA_OCF_TASKLET) -+#error "don't use both tasklet and polling mode" -+#endif -+ -+extern int cesaReqResources; -+/* support for spliting action into 2 actions */ -+#define CESA_OCF_SPLIT -+ -+/* general defines */ -+#define CESA_OCF_MAX_SES 128 -+#define CESA_Q_SIZE 64 -+ -+ -+/* data structures */ -+struct cesa_ocf_data { -+ int cipher_alg; -+ int auth_alg; -+ int encrypt_tn_auth; -+#define auth_tn_decrypt encrypt_tn_auth -+ int ivlen; -+ int digestlen; -+ short sid_encrypt; -+ short sid_decrypt; -+ /* fragment workaround sessions */ -+ short frag_wa_encrypt; -+ short frag_wa_decrypt; -+ short frag_wa_auth; -+}; -+ -+/* CESA device data */ -+struct cesa_dev { -+ void __iomem *sram; -+ void __iomem *reg; -+ struct mv_cesa_platform_data *plat_data; -+ int irq; -+}; -+ -+#define DIGEST_BUF_SIZE 32 -+struct cesa_ocf_process { -+ MV_CESA_COMMAND cesa_cmd; -+ MV_CESA_MBUF cesa_mbuf; -+ MV_BUF_INFO cesa_bufs[MV_CESA_MAX_MBUF_FRAGS]; -+ char digest[DIGEST_BUF_SIZE]; -+ int digest_len; -+ struct cryptop *crp; -+ int need_cb; -+}; -+ -+/* global variables */ -+static int32_t cesa_ocf_id = -1; -+static struct cesa_ocf_data *cesa_ocf_sessions[CESA_OCF_MAX_SES]; -+static spinlock_t cesa_lock; -+static struct cesa_dev cesa_device; -+ -+/* static APIs */ -+static int cesa_ocf_process (device_t, struct cryptop *, int); -+static int cesa_ocf_newsession (device_t, u_int32_t *, struct cryptoini *); -+static int cesa_ocf_freesession (device_t, u_int64_t); -+static void cesa_callback (unsigned long); -+static irqreturn_t cesa_interrupt_handler (int, void *); -+#ifdef CESA_OCF_POLLING -+static void cesa_interrupt_polling(void); -+#endif -+#ifdef CESA_OCF_TASKLET -+static struct tasklet_struct cesa_ocf_tasklet; -+#endif -+ -+static struct timeval tt_start; -+static struct timeval tt_end; -+ -+/* -+ * dummy device structure -+ */ -+ -+static struct { -+ softc_device_decl sc_dev; -+} mv_cesa_dev; -+ -+static device_method_t mv_cesa_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, cesa_ocf_newsession), -+ DEVMETHOD(cryptodev_freesession,cesa_ocf_freesession), -+ DEVMETHOD(cryptodev_process, cesa_ocf_process), -+ DEVMETHOD(cryptodev_kprocess, NULL), -+}; -+ -+ -+ -+/* Add debug Trace */ -+#undef CESA_OCF_TRACE_DEBUG -+#ifdef CESA_OCF_TRACE_DEBUG -+ -+#define MV_CESA_USE_TIMER_ID 0 -+ -+typedef struct -+{ -+ int type; /* 0 - isrEmpty, 1 - cesaReadyGet, 2 - cesaAction */ -+ MV_U32 timeStamp; -+ MV_U32 cause; -+ MV_U32 realCause; -+ MV_U32 dmaCause; -+ int resources; -+ MV_CESA_REQ* pReqReady; -+ MV_CESA_REQ* pReqEmpty; -+ MV_CESA_REQ* pReqProcess; -+} MV_CESA_TEST_TRACE; -+ -+#define MV_CESA_TEST_TRACE_SIZE 50 -+ -+static int cesaTestTraceIdx = 0; -+static MV_CESA_TEST_TRACE cesaTestTrace[MV_CESA_TEST_TRACE_SIZE]; -+ -+static void cesaTestTraceAdd(int type) -+{ -+ cesaTestTrace[cesaTestTraceIdx].type = type; -+ cesaTestTrace[cesaTestTraceIdx].realCause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); -+ //cesaTestTrace[cesaTestTraceIdx].idmaCause = MV_REG_READ(IDMA_CAUSE_REG); -+ cesaTestTrace[cesaTestTraceIdx].resources = cesaReqResources; -+ cesaTestTrace[cesaTestTraceIdx].pReqReady = pCesaReqReady; -+ cesaTestTrace[cesaTestTraceIdx].pReqEmpty = pCesaReqEmpty; -+ cesaTestTrace[cesaTestTraceIdx].pReqProcess = pCesaReqProcess; -+ cesaTestTrace[cesaTestTraceIdx].timeStamp = mvCntmrRead(MV_CESA_USE_TIMER_ID); -+ cesaTestTraceIdx++; -+ if(cesaTestTraceIdx == MV_CESA_TEST_TRACE_SIZE) -+ cesaTestTraceIdx = 0; -+} -+ -+#else /* CESA_OCF_TRACE_DEBUG */ -+ -+#define cesaTestTraceAdd(x) -+ -+#endif /* CESA_OCF_TRACE_DEBUG */ -+ -+unsigned int -+get_usec(unsigned int start) -+{ -+ if(start) { -+ do_gettimeofday (&tt_start); -+ return 0; -+ } -+ else { -+ do_gettimeofday (&tt_end); -+ tt_end.tv_sec -= tt_start.tv_sec; -+ tt_end.tv_usec -= tt_start.tv_usec; -+ if (tt_end.tv_usec < 0) { -+ tt_end.tv_usec += 1000 * 1000; -+ tt_end.tv_sec -= 1; -+ } -+ } -+ printk("time taken is %d\n", (unsigned int)(tt_end.tv_usec + tt_end.tv_sec * 1000000)); -+ return (tt_end.tv_usec + tt_end.tv_sec * 1000000); -+} -+ -+#ifdef RT_DEBUG -+/* -+ * check that the crp action match the current session -+ */ -+static int -+ocf_check_action(struct cryptop *crp, struct cesa_ocf_data *cesa_ocf_cur_ses) { -+ int count = 0; -+ int encrypt = 0, decrypt = 0, auth = 0; -+ struct cryptodesc *crd; -+ -+ /* Go through crypto descriptors, processing as we go */ -+ for (crd = crp->crp_desc; crd; crd = crd->crd_next, count++) { -+ if(count > 2) { -+ printk("%s,%d: session mode is not supported.\n", __FILE__, __LINE__); -+ return 1; -+ } -+ -+ /* Encryption /Decryption */ -+ if(crd->crd_alg == cesa_ocf_cur_ses->cipher_alg) { -+ /* check that the action is compatible with session */ -+ if(encrypt || decrypt) { -+ printk("%s,%d: session mode is not supported.\n", __FILE__, __LINE__); -+ return 1; -+ } -+ -+ if(crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ -+ if( (count == 2) && (cesa_ocf_cur_ses->encrypt_tn_auth) ) { -+ printk("%s,%d: sequence isn't supported by this session.\n", __FILE__, __LINE__); -+ return 1; -+ } -+ encrypt++; -+ } -+ else { /* decrypt */ -+ if( (count == 2) && !(cesa_ocf_cur_ses->auth_tn_decrypt) ) { -+ printk("%s,%d: sequence isn't supported by this session.\n", __FILE__, __LINE__); -+ return 1; -+ } -+ decrypt++; -+ } -+ -+ } -+ /* Authentication */ -+ else if(crd->crd_alg == cesa_ocf_cur_ses->auth_alg) { -+ /* check that the action is compatible with session */ -+ if(auth) { -+ printk("%s,%d: session mode is not supported.\n", __FILE__, __LINE__); -+ return 1; -+ } -+ if( (count == 2) && (decrypt) && (cesa_ocf_cur_ses->auth_tn_decrypt)) { -+ printk("%s,%d: sequence isn't supported by this session.\n", __FILE__, __LINE__); -+ return 1; -+ } -+ if( (count == 2) && (encrypt) && !(cesa_ocf_cur_ses->encrypt_tn_auth)) { -+ printk("%s,%d: sequence isn't supported by this session.\n", __FILE__, __LINE__); -+ return 1; -+ } -+ auth++; -+ } -+ else { -+ printk("%s,%d: Alg isn't supported by this session.\n", __FILE__, __LINE__); -+ return 1; -+ } -+ } -+ return 0; -+ -+} -+#endif -+ -+/* -+ * Process a request. -+ */ -+static int -+cesa_ocf_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ struct cesa_ocf_process *cesa_ocf_cmd = NULL; -+ struct cesa_ocf_process *cesa_ocf_cmd_wa = NULL; -+ MV_CESA_COMMAND *cesa_cmd; -+ struct cryptodesc *crd; -+ struct cesa_ocf_data *cesa_ocf_cur_ses; -+ int sid = 0, temp_len = 0, i; -+ int encrypt = 0, decrypt = 0, auth = 0; -+ int status; -+ struct sk_buff *skb = NULL; -+ struct uio *uiop = NULL; -+ unsigned char *ivp; -+ MV_BUF_INFO *p_buf_info; -+ MV_CESA_MBUF *p_mbuf_info; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if( cesaReqResources <= 1 ) { -+ dprintk("%s,%d: ERESTART\n", __FILE__, __LINE__); -+ return ERESTART; -+ } -+ -+#ifdef RT_DEBUG -+ /* Sanity check */ -+ if (crp == NULL) { -+ printk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ if (crp->crp_desc == NULL || crp->crp_buf == NULL ) { -+ printk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ return EINVAL; -+ } -+ -+ sid = crp->crp_sid & 0xffffffff; -+ if ((sid >= CESA_OCF_MAX_SES) || (cesa_ocf_sessions[sid] == NULL)) { -+ crp->crp_etype = ENOENT; -+ printk("%s,%d: ENOENT session %d \n", __FILE__, __LINE__, sid); -+ return EINVAL; -+ } -+#endif -+ -+ sid = crp->crp_sid & 0xffffffff; -+ crp->crp_etype = 0; -+ cesa_ocf_cur_ses = cesa_ocf_sessions[sid]; -+ -+#ifdef RT_DEBUG -+ if(ocf_check_action(crp, cesa_ocf_cur_ses)){ -+ goto p_error; -+ } -+#endif -+ -+ /* malloc a new cesa process */ -+ cesa_ocf_cmd = kmalloc(sizeof(struct cesa_ocf_process), GFP_ATOMIC); -+ -+ if (cesa_ocf_cmd == NULL) { -+ printk("%s,%d: ENOBUFS \n", __FILE__, __LINE__); -+ goto p_error; -+ } -+ memset(cesa_ocf_cmd, 0, sizeof(struct cesa_ocf_process)); -+ -+ /* init cesa_process */ -+ cesa_ocf_cmd->crp = crp; -+ /* always call callback */ -+ cesa_ocf_cmd->need_cb = 1; -+ -+ /* init cesa_cmd for usage of the HALs */ -+ cesa_cmd = &cesa_ocf_cmd->cesa_cmd; -+ cesa_cmd->pReqPrv = (void *)cesa_ocf_cmd; -+ cesa_cmd->sessionId = cesa_ocf_cur_ses->sid_encrypt; /* defualt use encrypt */ -+ -+ /* prepare src buffer */ -+ /* we send the entire buffer to the HAL, even if only part of it should be encrypt/auth. */ -+ /* if not using seesions for both encrypt and auth, then it will be wiser to to copy only */ -+ /* from skip to crd_len. */ -+ p_buf_info = cesa_ocf_cmd->cesa_bufs; -+ p_mbuf_info = &cesa_ocf_cmd->cesa_mbuf; -+ -+ p_buf_info += 2; /* save 2 first buffers for IV and digest - -+ we won't append them to the end since, they -+ might be places in an unaligned addresses. */ -+ -+ p_mbuf_info->pFrags = p_buf_info; -+ temp_len = 0; -+ -+ /* handle SKB */ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ -+ dprintk("%s,%d: handle SKB.\n", __FILE__, __LINE__); -+ skb = (struct sk_buff *) crp->crp_buf; -+ -+ if (skb_shinfo(skb)->nr_frags >= (MV_CESA_MAX_MBUF_FRAGS - 1)) { -+ printk("%s,%d: %d nr_frags > MV_CESA_MAX_MBUF_FRAGS", __FILE__, __LINE__, skb_shinfo(skb)->nr_frags); -+ goto p_error; -+ } -+ -+ p_mbuf_info->mbufSize = skb->len; -+ temp_len = skb->len; -+ /* first skb fragment */ -+ p_buf_info->bufSize = skb_headlen(skb); -+ p_buf_info->bufVirtPtr = skb->data; -+ p_buf_info++; -+ -+ /* now handle all other skb fragments */ -+ for ( i = 0; i < skb_shinfo(skb)->nr_frags; i++ ) { -+ skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; -+ p_buf_info->bufSize = frag->size; -+ p_buf_info->bufVirtPtr = page_address(frag->page) + frag->page_offset; -+ p_buf_info++; -+ } -+ p_mbuf_info->numFrags = skb_shinfo(skb)->nr_frags + 1; -+ } -+ /* handle UIO */ -+ else if(crp->crp_flags & CRYPTO_F_IOV) { -+ -+ dprintk("%s,%d: handle UIO.\n", __FILE__, __LINE__); -+ uiop = (struct uio *) crp->crp_buf; -+ -+ if (uiop->uio_iovcnt > (MV_CESA_MAX_MBUF_FRAGS - 1)) { -+ printk("%s,%d: %d uio_iovcnt > MV_CESA_MAX_MBUF_FRAGS \n", __FILE__, __LINE__, uiop->uio_iovcnt); -+ goto p_error; -+ } -+ -+ p_mbuf_info->mbufSize = crp->crp_ilen; -+ p_mbuf_info->numFrags = uiop->uio_iovcnt; -+ for(i = 0; i < uiop->uio_iovcnt; i++) { -+ p_buf_info->bufVirtPtr = uiop->uio_iov[i].iov_base; -+ p_buf_info->bufSize = uiop->uio_iov[i].iov_len; -+ temp_len += p_buf_info->bufSize; -+ dprintk("%s,%d: buf %x-> addr %x, size %x \n" -+ , __FILE__, __LINE__, i, (unsigned int)p_buf_info->bufVirtPtr, p_buf_info->bufSize); -+ p_buf_info++; -+ } -+ -+ } -+ /* handle CONTIG */ -+ else { -+ dprintk("%s,%d: handle CONTIG.\n", __FILE__, __LINE__); -+ p_mbuf_info->numFrags = 1; -+ p_mbuf_info->mbufSize = crp->crp_ilen; -+ p_buf_info->bufVirtPtr = crp->crp_buf; -+ p_buf_info->bufSize = crp->crp_ilen; -+ temp_len = crp->crp_ilen; -+ p_buf_info++; -+ } -+ -+ /* Support up to 64K why? cause! */ -+ if(crp->crp_ilen > 64*1024) { -+ printk("%s,%d: buf too big %x \n", __FILE__, __LINE__, crp->crp_ilen); -+ goto p_error; -+ } -+ -+ if( temp_len != crp->crp_ilen ) { -+ printk("%s,%d: warning size don't match.(%x %x) \n", __FILE__, __LINE__, temp_len, crp->crp_ilen); -+ } -+ -+ cesa_cmd->pSrc = p_mbuf_info; -+ cesa_cmd->pDst = p_mbuf_info; -+ -+ /* restore p_buf_info to point to first available buf */ -+ p_buf_info = cesa_ocf_cmd->cesa_bufs; -+ p_buf_info += 1; -+ -+ -+ /* Go through crypto descriptors, processing as we go */ -+ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { -+ -+ /* Encryption /Decryption */ -+ if(crd->crd_alg == cesa_ocf_cur_ses->cipher_alg) { -+ -+ dprintk("%s,%d: cipher", __FILE__, __LINE__); -+ -+ cesa_cmd->cryptoOffset = crd->crd_skip; -+ cesa_cmd->cryptoLength = crd->crd_len; -+ -+ if(crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ -+ dprintk(" encrypt \n"); -+ encrypt++; -+ -+ /* handle IV */ -+ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { /* IV from USER */ -+ dprintk("%s,%d: IV from USER (offset %x) \n", __FILE__, __LINE__, crd->crd_inject); -+ cesa_cmd->ivFromUser = 1; -+ ivp = crd->crd_iv; -+ -+ /* -+ * do we have to copy the IV back to the buffer ? -+ */ -+ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { -+ dprintk("%s,%d: copy the IV back to the buffer\n", __FILE__, __LINE__); -+ cesa_cmd->ivOffset = crd->crd_inject; -+ crypto_copy_bits_back(crp->crp_buf, crd->crd_inject, ivp, cesa_ocf_cur_ses->ivlen); -+ } -+ else { -+ dprintk("%s,%d: don't copy the IV back to the buffer \n", __FILE__, __LINE__); -+ p_mbuf_info->numFrags++; -+ p_mbuf_info->mbufSize += cesa_ocf_cur_ses->ivlen; -+ p_mbuf_info->pFrags = p_buf_info; -+ -+ p_buf_info->bufVirtPtr = ivp; -+ p_buf_info->bufSize = cesa_ocf_cur_ses->ivlen; -+ p_buf_info--; -+ -+ /* offsets */ -+ cesa_cmd->ivOffset = 0; -+ cesa_cmd->cryptoOffset += cesa_ocf_cur_ses->ivlen; -+ if(auth) { -+ cesa_cmd->macOffset += cesa_ocf_cur_ses->ivlen; -+ cesa_cmd->digestOffset += cesa_ocf_cur_ses->ivlen; -+ } -+ } -+ } -+ else { /* random IV */ -+ dprintk("%s,%d: random IV \n", __FILE__, __LINE__); -+ cesa_cmd->ivFromUser = 0; -+ -+ /* -+ * do we have to copy the IV back to the buffer ? -+ */ -+ /* in this mode the HAL will always copy the IV */ -+ /* given by the session to the ivOffset */ -+ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { -+ cesa_cmd->ivOffset = crd->crd_inject; -+ } -+ else { -+ /* if IV isn't copy, then how will the user know which IV did we use??? */ -+ printk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ goto p_error; -+ } -+ } -+ } -+ else { /* decrypt */ -+ dprintk(" decrypt \n"); -+ decrypt++; -+ cesa_cmd->sessionId = cesa_ocf_cur_ses->sid_decrypt; -+ -+ /* handle IV */ -+ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { -+ dprintk("%s,%d: IV from USER \n", __FILE__, __LINE__); -+ /* append the IV buf to the mbuf */ -+ cesa_cmd->ivFromUser = 1; -+ p_mbuf_info->numFrags++; -+ p_mbuf_info->mbufSize += cesa_ocf_cur_ses->ivlen; -+ p_mbuf_info->pFrags = p_buf_info; -+ -+ p_buf_info->bufVirtPtr = crd->crd_iv; -+ p_buf_info->bufSize = cesa_ocf_cur_ses->ivlen; -+ p_buf_info--; -+ -+ /* offsets */ -+ cesa_cmd->ivOffset = 0; -+ cesa_cmd->cryptoOffset += cesa_ocf_cur_ses->ivlen; -+ if(auth) { -+ cesa_cmd->macOffset += cesa_ocf_cur_ses->ivlen; -+ cesa_cmd->digestOffset += cesa_ocf_cur_ses->ivlen; -+ } -+ } -+ else { -+ dprintk("%s,%d: IV inside the buffer \n", __FILE__, __LINE__); -+ cesa_cmd->ivFromUser = 0; -+ cesa_cmd->ivOffset = crd->crd_inject; -+ } -+ } -+ -+ } -+ /* Authentication */ -+ else if(crd->crd_alg == cesa_ocf_cur_ses->auth_alg) { -+ dprintk("%s,%d: Authentication \n", __FILE__, __LINE__); -+ auth++; -+ cesa_cmd->macOffset = crd->crd_skip; -+ cesa_cmd->macLength = crd->crd_len; -+ -+ /* digest + mac */ -+ cesa_cmd->digestOffset = crd->crd_inject; -+ } -+ else { -+ printk("%s,%d: Alg isn't supported by this session.\n", __FILE__, __LINE__); -+ goto p_error; -+ } -+ } -+ -+ dprintk("\n"); -+ dprintk("%s,%d: Sending Action: \n", __FILE__, __LINE__); -+ dprintk("%s,%d: IV from user: %d. IV offset %x \n", __FILE__, __LINE__, cesa_cmd->ivFromUser, cesa_cmd->ivOffset); -+ dprintk("%s,%d: crypt offset %x len %x \n", __FILE__, __LINE__, cesa_cmd->cryptoOffset, cesa_cmd->cryptoLength); -+ dprintk("%s,%d: Auth offset %x len %x \n", __FILE__, __LINE__, cesa_cmd->macOffset, cesa_cmd->macLength); -+ dprintk("%s,%d: set digest in offset %x . \n", __FILE__, __LINE__, cesa_cmd->digestOffset); -+ if(debug) { -+ mvCesaDebugMbuf("SRC BUFFER", cesa_cmd->pSrc, 0, cesa_cmd->pSrc->mbufSize); -+ } -+ -+ -+ /* send action to HAL */ -+ spin_lock_irqsave(&cesa_lock, flags); -+ status = mvCesaAction(cesa_cmd); -+ spin_unlock_irqrestore(&cesa_lock, flags); -+ -+ /* action not allowed */ -+ if(status == MV_NOT_ALLOWED) { -+#ifdef CESA_OCF_SPLIT -+ /* if both encrypt and auth try to split */ -+ if(auth && (encrypt || decrypt)) { -+ MV_CESA_COMMAND *cesa_cmd_wa; -+ -+ /* malloc a new cesa process and init it */ -+ cesa_ocf_cmd_wa = kmalloc(sizeof(struct cesa_ocf_process), GFP_ATOMIC); -+ -+ if (cesa_ocf_cmd_wa == NULL) { -+ printk("%s,%d: ENOBUFS \n", __FILE__, __LINE__); -+ goto p_error; -+ } -+ memcpy(cesa_ocf_cmd_wa, cesa_ocf_cmd, sizeof(struct cesa_ocf_process)); -+ cesa_cmd_wa = &cesa_ocf_cmd_wa->cesa_cmd; -+ cesa_cmd_wa->pReqPrv = (void *)cesa_ocf_cmd_wa; -+ cesa_ocf_cmd_wa->need_cb = 0; -+ -+ /* break requests to two operation, first operation completion won't call callback */ -+ if((decrypt) && (cesa_ocf_cur_ses->auth_tn_decrypt)) { -+ cesa_cmd_wa->sessionId = cesa_ocf_cur_ses->frag_wa_auth; -+ cesa_cmd->sessionId = cesa_ocf_cur_ses->frag_wa_decrypt; -+ } -+ else if((decrypt) && !(cesa_ocf_cur_ses->auth_tn_decrypt)) { -+ cesa_cmd_wa->sessionId = cesa_ocf_cur_ses->frag_wa_decrypt; -+ cesa_cmd->sessionId = cesa_ocf_cur_ses->frag_wa_auth; -+ } -+ else if((encrypt) && (cesa_ocf_cur_ses->encrypt_tn_auth)) { -+ cesa_cmd_wa->sessionId = cesa_ocf_cur_ses->frag_wa_encrypt; -+ cesa_cmd->sessionId = cesa_ocf_cur_ses->frag_wa_auth; -+ } -+ else if((encrypt) && !(cesa_ocf_cur_ses->encrypt_tn_auth)){ -+ cesa_cmd_wa->sessionId = cesa_ocf_cur_ses->frag_wa_auth; -+ cesa_cmd->sessionId = cesa_ocf_cur_ses->frag_wa_encrypt; -+ } -+ else { -+ printk("%s,%d: Unsupporterd fragment wa mode \n", __FILE__, __LINE__); -+ goto p_error; -+ } -+ -+ /* send the 2 actions to the HAL */ -+ spin_lock_irqsave(&cesa_lock, flags); -+ status = mvCesaAction(cesa_cmd_wa); -+ spin_unlock_irqrestore(&cesa_lock, flags); -+ -+ if((status != MV_NO_MORE) && (status != MV_OK)) { -+ printk("%s,%d: cesa action failed, status = 0x%x\n", __FILE__, __LINE__, status); -+ goto p_error; -+ } -+ spin_lock_irqsave(&cesa_lock, flags); -+ status = mvCesaAction(cesa_cmd); -+ spin_unlock_irqrestore(&cesa_lock, flags); -+ -+ } -+ /* action not allowed and can't split */ -+ else -+#endif -+ { -+ goto p_error; -+ } -+ } -+ -+ /* Hal Q is full, send again. This should never happen */ -+ if(status == MV_NO_RESOURCE) { -+ printk("%s,%d: cesa no more resources \n", __FILE__, __LINE__); -+ if(cesa_ocf_cmd) -+ kfree(cesa_ocf_cmd); -+ if(cesa_ocf_cmd_wa) -+ kfree(cesa_ocf_cmd_wa); -+ return ERESTART; -+ } -+ else if((status != MV_NO_MORE) && (status != MV_OK)) { -+ printk("%s,%d: cesa action failed, status = 0x%x\n", __FILE__, __LINE__, status); -+ goto p_error; -+ } -+ -+ -+#ifdef CESA_OCF_POLLING -+ cesa_interrupt_polling(); -+#endif -+ cesaTestTraceAdd(5); -+ -+ return 0; -+p_error: -+ crp->crp_etype = EINVAL; -+ if(cesa_ocf_cmd) -+ kfree(cesa_ocf_cmd); -+ if(cesa_ocf_cmd_wa) -+ kfree(cesa_ocf_cmd_wa); -+ return EINVAL; -+} -+ -+/* -+ * cesa callback. -+ */ -+static void -+cesa_callback(unsigned long dummy) -+{ -+ struct cesa_ocf_process *cesa_ocf_cmd = NULL; -+ struct cryptop *crp = NULL; -+ MV_CESA_RESULT result[MV_CESA_MAX_CHAN]; -+ int res_idx = 0,i; -+ MV_STATUS status; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+#ifdef CESA_OCF_TASKLET -+ disable_irq(cesa_device.irq); -+#endif -+ while(MV_TRUE) { -+ -+ /* Get Ready requests */ -+ spin_lock(&cesa_lock); -+ status = mvCesaReadyGet(&result[res_idx]); -+ spin_unlock(&cesa_lock); -+ -+ cesaTestTraceAdd(2); -+ -+ if(status != MV_OK) { -+#ifdef CESA_OCF_POLLING -+ if(status == MV_BUSY) { /* Fragment */ -+ cesa_interrupt_polling(); -+ return; -+ } -+#endif -+ break; -+ } -+ res_idx++; -+ break; -+ } -+ -+ for(i = 0; i < res_idx; i++) { -+ -+ if(!result[i].pReqPrv) { -+ printk("%s,%d: warning private is NULL\n", __FILE__, __LINE__); -+ break; -+ } -+ -+ cesa_ocf_cmd = result[i].pReqPrv; -+ crp = cesa_ocf_cmd->crp; -+ -+ // ignore HMAC error. -+ //if(result->retCode) -+ // crp->crp_etype = EIO; -+ -+#if defined(CESA_OCF_POLLING) -+ if(!cesa_ocf_cmd->need_cb){ -+ cesa_interrupt_polling(); -+ } -+#endif -+ if(cesa_ocf_cmd->need_cb) { -+ if(debug) { -+ mvCesaDebugMbuf("DST BUFFER", cesa_ocf_cmd->cesa_cmd.pDst, 0, cesa_ocf_cmd->cesa_cmd.pDst->mbufSize); -+ } -+ crypto_done(crp); -+ } -+ kfree(cesa_ocf_cmd); -+ } -+#ifdef CESA_OCF_TASKLET -+ enable_irq(cesa_device.irq); -+#endif -+ -+ cesaTestTraceAdd(3); -+ -+ return; -+} -+ -+#ifdef CESA_OCF_POLLING -+static void -+cesa_interrupt_polling(void) -+{ -+ u32 cause; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ /* Read cause register */ -+ do { -+ cause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); -+ cause &= MV_CESA_CAUSE_ACC_DMA_ALL_MASK; -+ -+ } while (cause == 0); -+ -+ /* clear interrupts */ -+ MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); -+ -+ cesa_callback(0); -+ -+ return; -+} -+ -+#endif -+ -+/* -+ * cesa Interrupt polling routine. -+ */ -+static irqreturn_t -+cesa_interrupt_handler(int irq, void *arg) -+{ -+ u32 cause; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ cesaTestTraceAdd(0); -+ -+ /* Read cause register */ -+ cause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); -+ -+ if( (cause & MV_CESA_CAUSE_ACC_DMA_ALL_MASK) == 0) -+ { -+ /* Empty interrupt */ -+ dprintk("%s,%d: cesaTestReadyIsr: cause=0x%x\n", __FILE__, __LINE__, cause); -+ return IRQ_HANDLED; -+ } -+ -+ /* clear interrupts */ -+ MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); -+ -+ cesaTestTraceAdd(1); -+#ifdef CESA_OCF_TASKLET -+ tasklet_hi_schedule(&cesa_ocf_tasklet); -+#else -+ cesa_callback(0); -+#endif -+ return IRQ_HANDLED; -+} -+ -+/* -+ * Open a session. -+ */ -+static int -+/*cesa_ocf_newsession(void *arg, u_int32_t *sid, struct cryptoini *cri)*/ -+cesa_ocf_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) -+{ -+ u32 status = 0, i; -+ u32 count = 0, auth = 0, encrypt =0; -+ struct cesa_ocf_data *cesa_ocf_cur_ses; -+ MV_CESA_OPEN_SESSION cesa_session; -+ MV_CESA_OPEN_SESSION *cesa_ses = &cesa_session; -+ -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid == NULL || cri == NULL) { -+ printk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ /* leave first empty like in other implementations */ -+ for (i = 1; i < CESA_OCF_MAX_SES; i++) { -+ if (cesa_ocf_sessions[i] == NULL) -+ break; -+ } -+ -+ if(i >= CESA_OCF_MAX_SES) { -+ printk("%s,%d: no more sessions \n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ cesa_ocf_sessions[i] = (struct cesa_ocf_data *) kmalloc(sizeof(struct cesa_ocf_data), GFP_ATOMIC); -+ if (cesa_ocf_sessions[i] == NULL) { -+ cesa_ocf_freesession(NULL, i); -+ printk("%s,%d: ENOBUFS \n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ dprintk("%s,%d: new session %d \n", __FILE__, __LINE__, i); -+ -+ *sid = i; -+ cesa_ocf_cur_ses = cesa_ocf_sessions[i]; -+ memset(cesa_ocf_cur_ses, 0, sizeof(struct cesa_ocf_data)); -+ cesa_ocf_cur_ses->sid_encrypt = -1; -+ cesa_ocf_cur_ses->sid_decrypt = -1; -+ cesa_ocf_cur_ses->frag_wa_encrypt = -1; -+ cesa_ocf_cur_ses->frag_wa_decrypt = -1; -+ cesa_ocf_cur_ses->frag_wa_auth = -1; -+ -+ /* init the session */ -+ memset(cesa_ses, 0, sizeof(MV_CESA_OPEN_SESSION)); -+ count = 1; -+ while (cri) { -+ if(count > 2) { -+ printk("%s,%d: don't support more then 2 operations\n", __FILE__, __LINE__); -+ goto error; -+ } -+ switch (cri->cri_alg) { -+ case CRYPTO_AES_CBC: -+ dprintk("%s,%d: (%d) AES CBC \n", __FILE__, __LINE__, count); -+ cesa_ocf_cur_ses->cipher_alg = cri->cri_alg; -+ cesa_ocf_cur_ses->ivlen = MV_CESA_AES_BLOCK_SIZE; -+ cesa_ses->cryptoAlgorithm = MV_CESA_CRYPTO_AES; -+ cesa_ses->cryptoMode = MV_CESA_CRYPTO_CBC; -+ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { -+ printk("%s,%d: CRYPTO key too long.\n", __FILE__, __LINE__); -+ goto error; -+ } -+ memcpy(cesa_ses->cryptoKey, cri->cri_key, cri->cri_klen/8); -+ dprintk("%s,%d: key length %d \n", __FILE__, __LINE__, cri->cri_klen/8); -+ cesa_ses->cryptoKeyLength = cri->cri_klen/8; -+ encrypt += count; -+ break; -+ case CRYPTO_3DES_CBC: -+ dprintk("%s,%d: (%d) 3DES CBC \n", __FILE__, __LINE__, count); -+ cesa_ocf_cur_ses->cipher_alg = cri->cri_alg; -+ cesa_ocf_cur_ses->ivlen = MV_CESA_3DES_BLOCK_SIZE; -+ cesa_ses->cryptoAlgorithm = MV_CESA_CRYPTO_3DES; -+ cesa_ses->cryptoMode = MV_CESA_CRYPTO_CBC; -+ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { -+ printk("%s,%d: CRYPTO key too long.\n", __FILE__, __LINE__); -+ goto error; -+ } -+ memcpy(cesa_ses->cryptoKey, cri->cri_key, cri->cri_klen/8); -+ cesa_ses->cryptoKeyLength = cri->cri_klen/8; -+ encrypt += count; -+ break; -+ case CRYPTO_DES_CBC: -+ dprintk("%s,%d: (%d) DES CBC \n", __FILE__, __LINE__, count); -+ cesa_ocf_cur_ses->cipher_alg = cri->cri_alg; -+ cesa_ocf_cur_ses->ivlen = MV_CESA_DES_BLOCK_SIZE; -+ cesa_ses->cryptoAlgorithm = MV_CESA_CRYPTO_DES; -+ cesa_ses->cryptoMode = MV_CESA_CRYPTO_CBC; -+ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { -+ printk("%s,%d: CRYPTO key too long.\n", __FILE__, __LINE__); -+ goto error; -+ } -+ memcpy(cesa_ses->cryptoKey, cri->cri_key, cri->cri_klen/8); -+ cesa_ses->cryptoKeyLength = cri->cri_klen/8; -+ encrypt += count; -+ break; -+ case CRYPTO_MD5: -+ case CRYPTO_MD5_HMAC: -+ dprintk("%s,%d: (%d) %sMD5 CBC \n", __FILE__, __LINE__, count, (cri->cri_alg != CRYPTO_MD5)? "H-":" "); -+ cesa_ocf_cur_ses->auth_alg = cri->cri_alg; -+ cesa_ocf_cur_ses->digestlen = (cri->cri_alg == CRYPTO_MD5)? MV_CESA_MD5_DIGEST_SIZE : 12; -+ cesa_ses->macMode = (cri->cri_alg == CRYPTO_MD5)? MV_CESA_MAC_MD5 : MV_CESA_MAC_HMAC_MD5; -+ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { -+ printk("%s,%d: MAC key too long. \n", __FILE__, __LINE__); -+ goto error; -+ } -+ cesa_ses->macKeyLength = cri->cri_klen/8; -+ memcpy(cesa_ses->macKey, cri->cri_key, cri->cri_klen/8); -+ cesa_ses->digestSize = cesa_ocf_cur_ses->digestlen; -+ auth += count; -+ break; -+ case CRYPTO_SHA1: -+ case CRYPTO_SHA1_HMAC: -+ dprintk("%s,%d: (%d) %sSHA1 CBC \n", __FILE__, __LINE__, count, (cri->cri_alg != CRYPTO_SHA1)? "H-":" "); -+ cesa_ocf_cur_ses->auth_alg = cri->cri_alg; -+ cesa_ocf_cur_ses->digestlen = (cri->cri_alg == CRYPTO_SHA1)? MV_CESA_SHA1_DIGEST_SIZE : 12; -+ cesa_ses->macMode = (cri->cri_alg == CRYPTO_SHA1)? MV_CESA_MAC_SHA1 : MV_CESA_MAC_HMAC_SHA1; -+ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { -+ printk("%s,%d: MAC key too long. \n", __FILE__, __LINE__); -+ goto error; -+ } -+ cesa_ses->macKeyLength = cri->cri_klen/8; -+ memcpy(cesa_ses->macKey, cri->cri_key, cri->cri_klen/8); -+ cesa_ses->digestSize = cesa_ocf_cur_ses->digestlen; -+ auth += count; -+ break; -+ default: -+ printk("%s,%d: unknown algo 0x%x\n", __FILE__, __LINE__, cri->cri_alg); -+ goto error; -+ } -+ cri = cri->cri_next; -+ count++; -+ } -+ -+ if((encrypt > 2) || (auth > 2)) { -+ printk("%s,%d: session mode is not supported.\n", __FILE__, __LINE__); -+ goto error; -+ } -+ /* create new sessions in HAL */ -+ if(encrypt) { -+ cesa_ses->operation = MV_CESA_CRYPTO_ONLY; -+ /* encrypt session */ -+ if(auth == 1) { -+ cesa_ses->operation = MV_CESA_MAC_THEN_CRYPTO; -+ } -+ else if(auth == 2) { -+ cesa_ses->operation = MV_CESA_CRYPTO_THEN_MAC; -+ cesa_ocf_cur_ses->encrypt_tn_auth = 1; -+ } -+ else { -+ cesa_ses->operation = MV_CESA_CRYPTO_ONLY; -+ } -+ cesa_ses->direction = MV_CESA_DIR_ENCODE; -+ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->sid_encrypt); -+ if(status != MV_OK) { -+ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); -+ goto error; -+ } -+ /* decrypt session */ -+ if( cesa_ses->operation == MV_CESA_MAC_THEN_CRYPTO ) { -+ cesa_ses->operation = MV_CESA_CRYPTO_THEN_MAC; -+ } -+ else if( cesa_ses->operation == MV_CESA_CRYPTO_THEN_MAC ) { -+ cesa_ses->operation = MV_CESA_MAC_THEN_CRYPTO; -+ } -+ cesa_ses->direction = MV_CESA_DIR_DECODE; -+ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->sid_decrypt); -+ if(status != MV_OK) { -+ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); -+ goto error; -+ } -+ -+ /* preapre one action sessions for case we will need to split an action */ -+#ifdef CESA_OCF_SPLIT -+ if(( cesa_ses->operation == MV_CESA_MAC_THEN_CRYPTO ) || -+ ( cesa_ses->operation == MV_CESA_CRYPTO_THEN_MAC )) { -+ /* open one session for encode and one for decode */ -+ cesa_ses->operation = MV_CESA_CRYPTO_ONLY; -+ cesa_ses->direction = MV_CESA_DIR_ENCODE; -+ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->frag_wa_encrypt); -+ if(status != MV_OK) { -+ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); -+ goto error; -+ } -+ -+ cesa_ses->direction = MV_CESA_DIR_DECODE; -+ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->frag_wa_decrypt); -+ if(status != MV_OK) { -+ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); -+ goto error; -+ } -+ /* open one session for auth */ -+ cesa_ses->operation = MV_CESA_MAC_ONLY; -+ cesa_ses->direction = MV_CESA_DIR_ENCODE; -+ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->frag_wa_auth); -+ if(status != MV_OK) { -+ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); -+ goto error; -+ } -+ } -+#endif -+ } -+ else { /* only auth */ -+ cesa_ses->operation = MV_CESA_MAC_ONLY; -+ cesa_ses->direction = MV_CESA_DIR_ENCODE; -+ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->sid_encrypt); -+ if(status != MV_OK) { -+ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); -+ goto error; -+ } -+ } -+ -+ return 0; -+error: -+ cesa_ocf_freesession(NULL, *sid); -+ return EINVAL; -+ -+} -+ -+ -+/* -+ * Free a session. -+ */ -+static int -+cesa_ocf_freesession(device_t dev, u_int64_t tid) -+{ -+ struct cesa_ocf_data *cesa_ocf_cur_ses; -+ u_int32_t sid = CRYPTO_SESID2LID(tid); -+ //unsigned long flags; -+ -+ dprintk("%s() %d \n", __FUNCTION__, sid); -+ if ( (sid >= CESA_OCF_MAX_SES) || (cesa_ocf_sessions[sid] == NULL) ) { -+ printk("%s,%d: EINVAL can't free session %d \n", __FILE__, __LINE__, sid); -+ return(EINVAL); -+ } -+ -+ /* Silently accept and return */ -+ if (sid == 0) -+ return(0); -+ -+ /* release session from HAL */ -+ cesa_ocf_cur_ses = cesa_ocf_sessions[sid]; -+ if (cesa_ocf_cur_ses->sid_encrypt != -1) { -+ mvCesaSessionClose(cesa_ocf_cur_ses->sid_encrypt); -+ } -+ if (cesa_ocf_cur_ses->sid_decrypt != -1) { -+ mvCesaSessionClose(cesa_ocf_cur_ses->sid_decrypt); -+ } -+ if (cesa_ocf_cur_ses->frag_wa_encrypt != -1) { -+ mvCesaSessionClose(cesa_ocf_cur_ses->frag_wa_encrypt); -+ } -+ if (cesa_ocf_cur_ses->frag_wa_decrypt != -1) { -+ mvCesaSessionClose(cesa_ocf_cur_ses->frag_wa_decrypt); -+ } -+ if (cesa_ocf_cur_ses->frag_wa_auth != -1) { -+ mvCesaSessionClose(cesa_ocf_cur_ses->frag_wa_auth); -+ } -+ -+ kfree(cesa_ocf_cur_ses); -+ cesa_ocf_sessions[sid] = NULL; -+ -+ return 0; -+} -+ -+ -+/* TDMA Window setup */ -+ -+static void __init -+setup_tdma_mbus_windows(struct cesa_dev *dev) -+{ -+ int i; -+ -+ for (i = 0; i < 4; i++) { -+ writel(0, dev->reg + WINDOW_BASE(i)); -+ writel(0, dev->reg + WINDOW_CTRL(i)); -+ } -+ -+ for (i = 0; i < dev->plat_data->dram->num_cs; i++) { -+ struct mbus_dram_window *cs = dev->plat_data->dram->cs + i; -+ writel( -+ ((cs->size - 1) & 0xffff0000) | -+ (cs->mbus_attr << 8) | -+ (dev->plat_data->dram->mbus_dram_target_id << 4) | 1, -+ dev->reg + WINDOW_CTRL(i) -+ ); -+ writel(cs->base, dev->reg + WINDOW_BASE(i)); -+ } -+} -+ -+/* -+ * our driver startup and shutdown routines -+ */ -+static int -+mv_cesa_ocf_init(struct platform_device *pdev) -+{ -+#if defined(CONFIG_MV78200) || defined(CONFIG_MV632X) -+ if (MV_FALSE == mvSocUnitIsMappedToThisCpu(CESA)) -+ { -+ dprintk("CESA is not mapped to this CPU\n"); -+ return -ENODEV; -+ } -+#endif -+ -+ dprintk("%s\n", __FUNCTION__); -+ memset(&mv_cesa_dev, 0, sizeof(mv_cesa_dev)); -+ softc_device_init(&mv_cesa_dev, "MV CESA", 0, mv_cesa_methods); -+ cesa_ocf_id = crypto_get_driverid(softc_get_device(&mv_cesa_dev),CRYPTOCAP_F_HARDWARE); -+ -+ if (cesa_ocf_id < 0) -+ panic("MV CESA crypto device cannot initialize!"); -+ -+ dprintk("%s,%d: cesa ocf device id is %d \n", __FILE__, __LINE__, cesa_ocf_id); -+ -+ /* CESA unit is auto power on off */ -+#if 0 -+ if (MV_FALSE == mvCtrlPwrClckGet(CESA_UNIT_ID,0)) -+ { -+ printk("\nWarning CESA %d is Powered Off\n",0); -+ return EINVAL; -+ } -+#endif -+ -+ memset(&cesa_device, 0, sizeof(struct cesa_dev)); -+ /* Get the IRQ, and crypto memory regions */ -+ { -+ struct resource *res; -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram"); -+ -+ if (!res) -+ return -ENXIO; -+ -+ cesa_device.sram = ioremap(res->start, res->end - res->start + 1); -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); -+ -+ if (!res) { -+ iounmap(cesa_device.sram); -+ return -ENXIO; -+ } -+ cesa_device.reg = ioremap(res->start, res->end - res->start + 1); -+ cesa_device.irq = platform_get_irq(pdev, 0); -+ cesa_device.plat_data = pdev->dev.platform_data; -+ setup_tdma_mbus_windows(&cesa_device); -+ -+ } -+ -+ -+ if( MV_OK != mvCesaInit(CESA_OCF_MAX_SES*5, CESA_Q_SIZE, cesa_device.reg, -+ NULL) ) { -+ printk("%s,%d: mvCesaInit Failed. \n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ /* clear and unmask Int */ -+ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); -+#ifndef CESA_OCF_POLLING -+ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, MV_CESA_CAUSE_ACC_DMA_MASK); -+#endif -+#ifdef CESA_OCF_TASKLET -+ tasklet_init(&cesa_ocf_tasklet, cesa_callback, (unsigned int) 0); -+#endif -+ /* register interrupt */ -+ if( request_irq( cesa_device.irq, cesa_interrupt_handler, -+ (IRQF_DISABLED) , "cesa", &cesa_ocf_id) < 0) { -+ printk("%s,%d: cannot assign irq %x\n", __FILE__, __LINE__, cesa_device.reg); -+ return EINVAL; -+ } -+ -+ -+ memset(cesa_ocf_sessions, 0, sizeof(struct cesa_ocf_data *) * CESA_OCF_MAX_SES); -+ -+#define REGISTER(alg) \ -+ crypto_register(cesa_ocf_id, alg, 0,0) -+ REGISTER(CRYPTO_AES_CBC); -+ REGISTER(CRYPTO_DES_CBC); -+ REGISTER(CRYPTO_3DES_CBC); -+ REGISTER(CRYPTO_MD5); -+ REGISTER(CRYPTO_MD5_HMAC); -+ REGISTER(CRYPTO_SHA1); -+ REGISTER(CRYPTO_SHA1_HMAC); -+#undef REGISTER -+ -+ return 0; -+} -+ -+static void -+mv_cesa_ocf_exit(struct platform_device *pdev) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ crypto_unregister_all(cesa_ocf_id); -+ cesa_ocf_id = -1; -+ iounmap(cesa_device.reg); -+ iounmap(cesa_device.sram); -+ free_irq(cesa_device.irq, NULL); -+ -+ /* mask and clear Int */ -+ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, 0); -+ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); -+ -+ -+ if( MV_OK != mvCesaFinish() ) { -+ printk("%s,%d: mvCesaFinish Failed. \n", __FILE__, __LINE__); -+ return; -+ } -+} -+ -+ -+void cesa_ocf_debug(void) -+{ -+ -+#ifdef CESA_OCF_TRACE_DEBUG -+ { -+ int i, j; -+ j = cesaTestTraceIdx; -+ mvOsPrintf("No Type rCause iCause Proc Isr Res Time pReady pProc pEmpty\n"); -+ for(i=0; i= _1G) -+ { -+ mvOsOutput("%3dGB ", size / _1G); -+ size %= _1G; -+ if(size) -+ mvOsOutput("+"); -+ } -+ if(size >= _1M ) -+ { -+ mvOsOutput("%3dMB ", size / _1M); -+ size %= _1M; -+ if(size) -+ mvOsOutput("+"); -+ } -+ if(size >= _1K) -+ { -+ mvOsOutput("%3dKB ", size / _1K); -+ size %= _1K; -+ if(size) -+ mvOsOutput("+"); -+ } -+ if(size > 0) -+ { -+ mvOsOutput("%3dB ", size); -+ } -+} -+ -+/******************************************************************************* -+* mvHexToBin - Convert hex to binary -+* -+* DESCRIPTION: -+* This function Convert hex to binary. -+* -+* INPUT: -+* pHexStr - hex buffer pointer. -+* size - Size to convert. -+* -+* OUTPUT: -+* pBin - Binary buffer pointer. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvHexToBin(const char* pHexStr, MV_U8* pBin, int size) -+{ -+ int j, i; -+ char tmp[3]; -+ MV_U8 byte; -+ -+ for(j=0, i=0; j> 1; -+ result++; -+ } -+ return result; -+} -+ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/common/mvCommon.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/common/mvCommon.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/common/mvCommon.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/common/mvCommon.h 2010-11-09 20:28:06.212495496 +0100 -@@ -0,0 +1,308 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+ -+#ifndef __INCmvCommonh -+#define __INCmvCommonh -+ -+#include "mvTypes.h" -+ -+/* Swap tool */ -+ -+/* 16bit nibble swap. For example 0x1234 -> 0x2143 */ -+#define MV_NIBBLE_SWAP_16BIT(X) (((X&0xf) << 4) | \ -+ ((X&0xf0) >> 4) | \ -+ ((X&0xf00) << 4) | \ -+ ((X&0xf000) >> 4)) -+ -+/* 32bit nibble swap. For example 0x12345678 -> 0x21436587 */ -+#define MV_NIBBLE_SWAP_32BIT(X) (((X&0xf) << 4) | \ -+ ((X&0xf0) >> 4) | \ -+ ((X&0xf00) << 4) | \ -+ ((X&0xf000) >> 4) | \ -+ ((X&0xf0000) << 4) | \ -+ ((X&0xf00000) >> 4) | \ -+ ((X&0xf000000) << 4) | \ -+ ((X&0xf0000000) >> 4)) -+ -+/* 16bit byte swap. For example 0x1122 -> 0x2211 */ -+#define MV_BYTE_SWAP_16BIT(X) ((((X)&0xff)<<8) | (((X)&0xff00)>>8)) -+ -+/* 32bit byte swap. For example 0x11223344 -> 0x44332211 */ -+#define MV_BYTE_SWAP_32BIT(X) ((((X)&0xff)<<24) | \ -+ (((X)&0xff00)<<8) | \ -+ (((X)&0xff0000)>>8) | \ -+ (((X)&0xff000000)>>24)) -+ -+/* 64bit byte swap. For example 0x11223344.55667788 -> 0x88776655.44332211 */ -+#define MV_BYTE_SWAP_64BIT(X) ((l64) ((((X)&0xffULL)<<56) | \ -+ (((X)&0xff00ULL)<<40) | \ -+ (((X)&0xff0000ULL)<<24) | \ -+ (((X)&0xff000000ULL)<<8) | \ -+ (((X)&0xff00000000ULL)>>8) | \ -+ (((X)&0xff0000000000ULL)>>24) | \ -+ (((X)&0xff000000000000ULL)>>40) | \ -+ (((X)&0xff00000000000000ULL)>>56))) -+ -+/* Endianess macros. */ -+#if defined(MV_CPU_LE) -+ #define MV_16BIT_LE(X) (X) -+ #define MV_32BIT_LE(X) (X) -+ #define MV_64BIT_LE(X) (X) -+ #define MV_16BIT_BE(X) MV_BYTE_SWAP_16BIT(X) -+ #define MV_32BIT_BE(X) MV_BYTE_SWAP_32BIT(X) -+ #define MV_64BIT_BE(X) MV_BYTE_SWAP_64BIT(X) -+#elif defined(MV_CPU_BE) -+ #define MV_16BIT_LE(X) MV_BYTE_SWAP_16BIT(X) -+ #define MV_32BIT_LE(X) MV_BYTE_SWAP_32BIT(X) -+ #define MV_64BIT_LE(X) MV_BYTE_SWAP_64BIT(X) -+ #define MV_16BIT_BE(X) (X) -+ #define MV_32BIT_BE(X) (X) -+ #define MV_64BIT_BE(X) (X) -+#else -+ #error "CPU endianess isn't defined!\n" -+#endif -+ -+ -+/* Bit field definitions */ -+#define NO_BIT 0x00000000 -+#define BIT0 0x00000001 -+#define BIT1 0x00000002 -+#define BIT2 0x00000004 -+#define BIT3 0x00000008 -+#define BIT4 0x00000010 -+#define BIT5 0x00000020 -+#define BIT6 0x00000040 -+#define BIT7 0x00000080 -+#define BIT8 0x00000100 -+#define BIT9 0x00000200 -+#define BIT10 0x00000400 -+#define BIT11 0x00000800 -+#define BIT12 0x00001000 -+#define BIT13 0x00002000 -+#define BIT14 0x00004000 -+#define BIT15 0x00008000 -+#define BIT16 0x00010000 -+#define BIT17 0x00020000 -+#define BIT18 0x00040000 -+#define BIT19 0x00080000 -+#define BIT20 0x00100000 -+#define BIT21 0x00200000 -+#define BIT22 0x00400000 -+#define BIT23 0x00800000 -+#define BIT24 0x01000000 -+#define BIT25 0x02000000 -+#define BIT26 0x04000000 -+#define BIT27 0x08000000 -+#define BIT28 0x10000000 -+#define BIT29 0x20000000 -+#define BIT30 0x40000000 -+#define BIT31 0x80000000 -+ -+/* Handy sizes */ -+#define _1K 0x00000400 -+#define _2K 0x00000800 -+#define _4K 0x00001000 -+#define _8K 0x00002000 -+#define _16K 0x00004000 -+#define _32K 0x00008000 -+#define _64K 0x00010000 -+#define _128K 0x00020000 -+#define _256K 0x00040000 -+#define _512K 0x00080000 -+ -+#define _1M 0x00100000 -+#define _2M 0x00200000 -+#define _4M 0x00400000 -+#define _8M 0x00800000 -+#define _16M 0x01000000 -+#define _32M 0x02000000 -+#define _64M 0x04000000 -+#define _128M 0x08000000 -+#define _256M 0x10000000 -+#define _512M 0x20000000 -+ -+#define _1G 0x40000000 -+#define _2G 0x80000000 -+ -+/* Tclock and Sys clock define */ -+#define _100MHz 100000000 -+#define _125MHz 125000000 -+#define _133MHz 133333334 -+#define _150MHz 150000000 -+#define _160MHz 160000000 -+#define _166MHz 166666667 -+#define _175MHz 175000000 -+#define _178MHz 178000000 -+#define _183MHz 183333334 -+#define _187MHz 187000000 -+#define _192MHz 192000000 -+#define _194MHz 194000000 -+#define _200MHz 200000000 -+#define _233MHz 233333334 -+#define _250MHz 250000000 -+#define _266MHz 266666667 -+#define _300MHz 300000000 -+ -+/* For better address window table readability */ -+#define EN MV_TRUE -+#define DIS MV_FALSE -+#define N_A -1 /* Not applicable */ -+ -+/* Cache configuration options for memory (DRAM, SRAM, ... ) */ -+ -+/* Memory uncached, HW or SW cache coherency is not needed */ -+#define MV_UNCACHED 0 -+/* Memory cached, HW cache coherency supported in WriteThrough mode */ -+#define MV_CACHE_COHER_HW_WT 1 -+/* Memory cached, HW cache coherency supported in WriteBack mode */ -+#define MV_CACHE_COHER_HW_WB 2 -+/* Memory cached, No HW cache coherency, Cache coherency must be in SW */ -+#define MV_CACHE_COHER_SW 3 -+ -+ -+/* Macro for testing aligment. Positive if number is NOT aligned */ -+#define MV_IS_NOT_ALIGN(number, align) ((number) & ((align) - 1)) -+ -+/* Macro for alignment up. For example, MV_ALIGN_UP(0x0330, 0x20) = 0x0340 */ -+#define MV_ALIGN_UP(number, align) \ -+(((number) & ((align) - 1)) ? (((number) + (align)) & ~((align)-1)) : (number)) -+ -+/* Macro for alignment down. For example, MV_ALIGN_UP(0x0330, 0x20) = 0x0320 */ -+#define MV_ALIGN_DOWN(number, align) ((number) & ~((align)-1)) -+ -+/* This macro returns absolute value */ -+#define MV_ABS(number) (((int)(number) < 0) ? -(int)(number) : (int)(number)) -+ -+ -+/* Bit fields manipulation macros */ -+ -+/* An integer word which its 'x' bit is set */ -+#define MV_BIT_MASK(bitNum) (1 << (bitNum) ) -+ -+/* Checks wheter bit 'x' in integer word is set */ -+#define MV_BIT_CHECK(word, bitNum) ( (word) & MV_BIT_MASK(bitNum) ) -+ -+/* Clear (reset) bit 'x' in integer word (RMW - Read-Modify-Write) */ -+#define MV_BIT_CLEAR(word, bitNum) ( (word) &= ~(MV_BIT_MASK(bitNum)) ) -+ -+/* Set bit 'x' in integer word (RMW) */ -+#define MV_BIT_SET(word, bitNum) ( (word) |= MV_BIT_MASK(bitNum) ) -+ -+/* Invert bit 'x' in integer word (RMW) */ -+#define MV_BIT_INV(word, bitNum) ( (word) ^= MV_BIT_MASK(bitNum) ) -+ -+/* Get the min between 'a' or 'b' */ -+#define MV_MIN(a,b) (((a) < (b)) ? (a) : (b)) -+ -+/* Get the max between 'a' or 'b' */ -+#define MV_MAX(a,b) (((a) < (b)) ? (b) : (a)) -+ -+/* Temporary */ -+#define mvOsDivide(num, div) \ -+({ \ -+ int i=0, rem=(num); \ -+ \ -+ while(rem >= (div)) \ -+ { \ -+ rem -= (div); \ -+ i++; \ -+ } \ -+ (i); \ -+}) -+ -+/* Temporary */ -+#define mvOsReminder(num, div) \ -+({ \ -+ int rem = (num); \ -+ \ -+ while(rem >= (div)) \ -+ rem -= (div); \ -+ (rem); \ -+}) -+ -+#define MV_IP_QUAD(ipAddr) ((ipAddr >> 24) & 0xFF), ((ipAddr >> 16) & 0xFF), \ -+ ((ipAddr >> 8) & 0xFF), ((ipAddr >> 0) & 0xFF) -+ -+#define MV_IS_POWER_OF_2(num) ((num != 0) && ((num & (num - 1)) == 0)) -+ -+#ifndef MV_ASMLANGUAGE -+/* mvCommon API list */ -+ -+MV_VOID mvHexToBin(const char* pHexStr, MV_U8* pBin, int size); -+void mvAsciiToHex(const char* asciiStr, char* hexStr); -+void mvBinToHex(const MV_U8* bin, char* hexStr, int size); -+void mvBinToAscii(const MV_U8* bin, char* asciiStr, int size); -+ -+MV_STATUS mvMacStrToHex(const char* macStr, MV_U8* macHex); -+MV_STATUS mvMacHexToStr(MV_U8* macHex, char* macStr); -+void mvSizePrint(MV_U32); -+ -+MV_U32 mvLog2(MV_U32 num); -+ -+#endif /* MV_ASMLANGUAGE */ -+ -+ -+#endif /* __INCmvCommonh */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/common/mvDebug.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/common/mvDebug.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/common/mvDebug.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/common/mvDebug.c 2010-11-09 20:28:06.252495437 +0100 -@@ -0,0 +1,326 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+ -+/* includes */ -+#include "mvOs.h" -+#include "mv802_3.h" -+#include "mvCommon.h" -+#include "mvDebug.h" -+ -+/* Global variables effect on behave MV_DEBUG_PRINT and MV_DEBUG_CODE macros -+ * mvDebug - map of bits (one for each module) bit=1 means enable -+ * debug code and messages for this module -+ * mvModuleDebug - array of 32 bits varables one for each module -+ */ -+MV_U32 mvDebug = 0; -+MV_U32 mvDebugModules[MV_MODULE_MAX]; -+ -+/* Init mvModuleDebug array to default values */ -+void mvDebugInit(void) -+{ -+ int bit; -+ -+ mvDebug = 0; -+ for(bit=0; bit 0) -+ { -+ mvOsPrintf("%08x: ", memAddr); -+ i = 0; -+ /* 32 bytes in the line */ -+ while(i < 32) -+ { -+ if(memAddr >= (MV_U32)addr) -+ { -+ switch(access) -+ { -+ case 1: -+ if( memAddr == CPU_PHY_MEM(memAddr) ) -+ { -+ mvOsPrintf("%02x ", MV_MEMIO8_READ(memAddr)); -+ } -+ else -+ { -+ mvOsPrintf("%02x ", *((MV_U8*)memAddr)); -+ } -+ break; -+ -+ case 2: -+ if( memAddr == CPU_PHY_MEM(memAddr) ) -+ { -+ mvOsPrintf("%04x ", MV_MEMIO16_READ(memAddr)); -+ } -+ else -+ { -+ mvOsPrintf("%04x ", *((MV_U16*)memAddr)); -+ } -+ break; -+ -+ case 4: -+ if( memAddr == CPU_PHY_MEM(memAddr) ) -+ { -+ mvOsPrintf("%08x ", MV_MEMIO32_READ(memAddr)); -+ } -+ else -+ { -+ mvOsPrintf("%08x ", *((MV_U32*)memAddr)); -+ } -+ break; -+ } -+ } -+ else -+ { -+ for(j=0; j<(access*2+1); j++) -+ mvOsPrintf(" "); -+ } -+ i += access; -+ memAddr += access; -+ size -= access; -+ if(size <= 0) -+ break; -+ } -+ mvOsPrintf("\n"); -+ } -+} -+ -+void mvDebugPrintBufInfo(BUF_INFO* pBufInfo, int size, int access) -+{ -+ if(pBufInfo == NULL) -+ { -+ mvOsPrintf("\n!!! pBufInfo = NULL\n"); -+ return; -+ } -+ mvOsPrintf("\n*** pBufInfo=0x%x, cmdSts=0x%08x, pBuf=0x%x, bufSize=%d\n", -+ (unsigned int)pBufInfo, -+ (unsigned int)pBufInfo->cmdSts, -+ (unsigned int)pBufInfo->pBuff, -+ (unsigned int)pBufInfo->bufSize); -+ mvOsPrintf("pData=0x%x, byteCnt=%d, pNext=0x%x, uInfo1=0x%x, uInfo2=0x%x\n", -+ (unsigned int)pBufInfo->pData, -+ (unsigned int)pBufInfo->byteCnt, -+ (unsigned int)pBufInfo->pNextBufInfo, -+ (unsigned int)pBufInfo->userInfo1, -+ (unsigned int)pBufInfo->userInfo2); -+ if(pBufInfo->pData != NULL) -+ { -+ if(size > pBufInfo->byteCnt) -+ size = pBufInfo->byteCnt; -+ mvDebugMemDump(pBufInfo->pData, size, access); -+ } -+} -+ -+void mvDebugPrintPktInfo(MV_PKT_INFO* pPktInfo, int size, int access) -+{ -+ int frag, len; -+ -+ if(pPktInfo == NULL) -+ { -+ mvOsPrintf("\n!!! pPktInfo = NULL\n"); -+ return; -+ } -+ mvOsPrintf("\npPkt=%p, stat=0x%08x, numFr=%d, size=%d, pFr=%p, osInfo=0x%lx\n", -+ pPktInfo, pPktInfo->status, pPktInfo->numFrags, pPktInfo->pktSize, -+ pPktInfo->pFrags, pPktInfo->osInfo); -+ -+ for(frag=0; fragnumFrags; frag++) -+ { -+ mvOsPrintf("#%2d. bufVirt=%p, bufSize=%d\n", -+ frag, pPktInfo->pFrags[frag].bufVirtPtr, -+ pPktInfo->pFrags[frag].bufSize); -+ if(size > 0) -+ { -+ len = MV_MIN((int)pPktInfo->pFrags[frag].bufSize, size); -+ mvDebugMemDump(pPktInfo->pFrags[frag].bufVirtPtr, len, access); -+ size -= len; -+ } -+ } -+ -+} -+ -+void mvDebugPrintIpAddr(MV_U32 ipAddr) -+{ -+ mvOsPrintf("%d.%d.%d.%d", ((ipAddr >> 24) & 0xFF), ((ipAddr >> 16) & 0xFF), -+ ((ipAddr >> 8) & 0xFF), ((ipAddr >> 0) & 0xFF)); -+} -+ -+void mvDebugPrintMacAddr(const MV_U8* pMacAddr) -+{ -+ int i; -+ -+ mvOsPrintf("%02x", (unsigned int)pMacAddr[0]); -+ for(i=1; ibegin = 0; -+ pTimeEntry->count = count; -+ pTimeEntry->end = 0; -+ pTimeEntry->left = pTimeEntry->count; -+ pTimeEntry->total = 0; -+ pTimeEntry->min = 0xFFFFFFFF; -+ pTimeEntry->max = 0x0; -+ strncpy(pTimeEntry->name, pName, sizeof(pTimeEntry->name)-1); -+ pTimeEntry->name[sizeof(pTimeEntry->name)-1] = '\0'; -+} -+ -+/* Print out MV_DEBUG_TIMES entry */ -+void mvDebugPrintTimeEntry(MV_DEBUG_TIMES* pTimeEntry, MV_BOOL isTitle) -+{ -+ int num; -+ -+ if(isTitle == MV_TRUE) -+ mvOsPrintf("Event NumOfEvents TotalTime Average Min Max\n"); -+ -+ num = pTimeEntry->count-pTimeEntry->left; -+ if(num > 0) -+ { -+ mvOsPrintf("%-11s %6u 0x%08lx %6lu %6lu %6lu\n", -+ pTimeEntry->name, num, pTimeEntry->total, pTimeEntry->total/num, -+ pTimeEntry->min, pTimeEntry->max); -+ } -+} -+ -+/* Update MV_DEBUG_TIMES entry */ -+void mvDebugUpdateTimeEntry(MV_DEBUG_TIMES* pTimeEntry) -+{ -+ MV_U32 delta; -+ -+ if(pTimeEntry->left > 0) -+ { -+ if(pTimeEntry->end <= pTimeEntry->begin) -+ { -+ delta = pTimeEntry->begin - pTimeEntry->end; -+ } -+ else -+ { -+ delta = ((MV_U32)0x10000 - pTimeEntry->end) + pTimeEntry->begin; -+ } -+ pTimeEntry->total += delta; -+ -+ if(delta < pTimeEntry->min) -+ pTimeEntry->min = delta; -+ -+ if(delta > pTimeEntry->max) -+ pTimeEntry->max = delta; -+ -+ pTimeEntry->left--; -+ } -+} -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/common/mvDebug.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/common/mvDebug.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/common/mvDebug.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/common/mvDebug.h 2010-11-09 20:28:06.292495404 +0100 -@@ -0,0 +1,178 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+ -+#ifndef __INCmvDebugh -+#define __INCmvDebugh -+ -+/* includes */ -+#include "mvTypes.h" -+ -+typedef enum -+{ -+ MV_MODULE_INVALID = -1, -+ MV_MODULE_ETH = 0, -+ MV_MODULE_IDMA, -+ MV_MODULE_XOR, -+ MV_MODULE_TWASI, -+ MV_MODULE_MGI, -+ MV_MODULE_USB, -+ MV_MODULE_CESA, -+ -+ MV_MODULE_MAX -+}MV_MODULE_ID; -+ -+/* Define generic flags useful for most of modules */ -+#define MV_DEBUG_FLAG_ALL (0) -+#define MV_DEBUG_FLAG_INIT (1 << 0) -+#define MV_DEBUG_FLAG_RX (1 << 1) -+#define MV_DEBUG_FLAG_TX (1 << 2) -+#define MV_DEBUG_FLAG_ERR (1 << 3) -+#define MV_DEBUG_FLAG_TRACE (1 << 4) -+#define MV_DEBUG_FLAG_DUMP (1 << 5) -+#define MV_DEBUG_FLAG_CACHE (1 << 6) -+#define MV_DEBUG_FLAG_IOCTL (1 << 7) -+#define MV_DEBUG_FLAG_STATS (1 << 8) -+ -+extern MV_U32 mvDebug; -+extern MV_U32 mvDebugModules[MV_MODULE_MAX]; -+ -+#ifdef MV_DEBUG -+# define MV_DEBUG_PRINT(module, flags, msg) mvOsPrintf msg -+# define MV_DEBUG_CODE(module, flags, code) code -+#elif defined(MV_RT_DEBUG) -+# define MV_DEBUG_PRINT(module, flags, msg) \ -+ if( (mvDebug & (1<<(module))) && \ -+ ((mvDebugModules[(module)] & (flags)) == (flags)) ) \ -+ mvOsPrintf msg -+# define MV_DEBUG_CODE(module, flags, code) \ -+ if( (mvDebug & (1<<(module))) && \ -+ ((mvDebugModules[(module)] & (flags)) == (flags)) ) \ -+ code -+#else -+# define MV_DEBUG_PRINT(module, flags, msg) -+# define MV_DEBUG_CODE(module, flags, code) -+#endif -+ -+ -+ -+/* typedefs */ -+ -+/* time measurement structure used to check how much time pass between -+ * two points -+ */ -+typedef struct { -+ char name[20]; /* name of the entry */ -+ unsigned long begin; /* time measured on begin point */ -+ unsigned long end; /* time measured on end point */ -+ unsigned long total; /* Accumulated time */ -+ unsigned long left; /* The rest measurement actions */ -+ unsigned long count; /* Maximum measurement actions */ -+ unsigned long min; /* Minimum time from begin to end */ -+ unsigned long max; /* Maximum time from begin to end */ -+} MV_DEBUG_TIMES; -+ -+ -+/* mvDebug.h API list */ -+ -+/****** Error Recording ******/ -+ -+/* Dump memory in specific format: -+ * address: X1X1X1X1 X2X2X2X2 ... X8X8X8X8 -+ */ -+void mvDebugMemDump(void* addr, int size, int access); -+ -+void mvDebugPrintBufInfo(BUF_INFO* pBufInfo, int size, int access); -+ -+void mvDebugPrintPktInfo(MV_PKT_INFO* pPktInfo, int size, int access); -+ -+void mvDebugPrintIpAddr(MV_U32 ipAddr); -+ -+void mvDebugPrintMacAddr(const MV_U8* pMacAddr); -+ -+/**** There are three functions deals with MV_DEBUG_TIMES structure ****/ -+ -+/* Reset MV_DEBUG_TIMES entry */ -+void mvDebugResetTimeEntry(MV_DEBUG_TIMES* pTimeEntry, int count, char* name); -+ -+/* Update MV_DEBUG_TIMES entry */ -+void mvDebugUpdateTimeEntry(MV_DEBUG_TIMES* pTimeEntry); -+ -+/* Print out MV_DEBUG_TIMES entry */ -+void mvDebugPrintTimeEntry(MV_DEBUG_TIMES* pTimeEntry, MV_BOOL isTitle); -+ -+ -+/******** General ***********/ -+ -+/* Change value of mvDebugPrint global variable */ -+ -+void mvDebugInit(void); -+void mvDebugModuleEnable(MV_MODULE_ID module, MV_BOOL isEnable); -+void mvDebugModuleSetFlags(MV_MODULE_ID module, MV_U32 flags); -+void mvDebugModuleClearFlags(MV_MODULE_ID module, MV_U32 flags); -+ -+ -+#endif /* __INCmvDebug.h */ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h 2010-11-09 20:28:06.332495486 +0100 -@@ -0,0 +1,225 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvDeviceIdh -+#define __INCmvDeviceIdh -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* defines */ -+#define MARVELL_VEN_ID 0x11ab -+ -+/* Disco-3 */ -+#define MV64460_DEV_ID 0x6480 -+#define MV64460B_DEV_ID 0x6485 -+#define MV64430_DEV_ID 0x6420 -+ -+/* Disco-5 */ -+#define MV64560_DEV_ID 0x6450 -+ -+/* Disco-6 */ -+#define MV64660_DEV_ID 0x6460 -+ -+/* Orion */ -+#define MV_1181_DEV_ID 0x1181 -+#define MV_5181_DEV_ID 0x5181 -+#define MV_5281_DEV_ID 0x5281 -+#define MV_5182_DEV_ID 0x5182 -+#define MV_8660_DEV_ID 0x8660 -+#define MV_5180_DEV_ID 0x5180 -+#define MV_5082_DEV_ID 0x5082 -+#define MV_1281_DEV_ID 0x1281 -+#define MV_6082_DEV_ID 0x6082 -+#define MV_6183_DEV_ID 0x6183 -+#define MV_6183L_DEV_ID 0x6083 -+ -+#define MV_5281_D0_REV 0x4 -+#define MV_5281_D0_ID ((MV_5281_DEV_ID << 16) | MV_5281_D0_REV) -+#define MV_5281_D0_NAME "88F5281 D0" -+ -+#define MV_5281_D1_REV 0x5 -+#define MV_5281_D1_ID ((MV_5281_DEV_ID << 16) | MV_5281_D1_REV) -+#define MV_5281_D1_NAME "88F5281 D1" -+ -+#define MV_5281_D2_REV 0x6 -+#define MV_5281_D2_ID ((MV_5281_DEV_ID << 16) | MV_5281_D2_REV) -+#define MV_5281_D2_NAME "88F5281 D2" -+ -+ -+#define MV_5181L_A0_REV 0x8 /* need for PCIE Er */ -+#define MV_5181_A1_REV 0x1 /* for USB Er ..*/ -+#define MV_5181_B0_REV 0x2 -+#define MV_5181_B1_REV 0x3 -+#define MV_5182_A1_REV 0x1 -+#define MV_5180N_B1_REV 0x3 -+#define MV_5181L_A0_ID ((MV_5181_DEV_ID << 16) | MV_5181L_A0_REV) -+ -+ -+ -+/* kw */ -+#define MV_6281_DEV_ID 0x6281 -+#define MV_6192_DEV_ID 0x6192 -+#define MV_6190_DEV_ID 0x6190 -+#define MV_6180_DEV_ID 0x6180 -+ -+#define MV_6281_A0_REV 0x2 -+#define MV_6281_A0_ID ((MV_6281_DEV_ID << 16) | MV_6281_A0_REV) -+#define MV_6281_A0_NAME "88F6281 A0" -+ -+#define MV_6192_A0_REV 0x2 -+#define MV_6192_A0_ID ((MV_6192_DEV_ID << 16) | MV_6192_A0_REV) -+#define MV_6192_A0_NAME "88F6192 A0" -+ -+#define MV_6190_A0_REV 0x2 -+#define MV_6190_A0_ID ((MV_6190_DEV_ID << 16) | MV_6190_A0_REV) -+#define MV_6190_A0_NAME "88F6190 A0" -+ -+#define MV_6180_A0_REV 0x2 -+#define MV_6180_A0_ID ((MV_6180_DEV_ID << 16) | MV_6180_A0_REV) -+#define MV_6180_A0_NAME "88F6180 A0" -+ -+#define MV_6281_A1_REV 0x3 -+#define MV_6281_A1_ID ((MV_6281_DEV_ID << 16) | MV_6281_A1_REV) -+#define MV_6281_A1_NAME "88F6281 A1" -+ -+#define MV_6192_A1_REV 0x3 -+#define MV_6192_A1_ID ((MV_6192_DEV_ID << 16) | MV_6192_A1_REV) -+#define MV_6192_A1_NAME "88F6192 A1" -+ -+#define MV_6190_A1_REV 0x3 -+#define MV_6190_A1_ID ((MV_6190_DEV_ID << 16) | MV_6190_A1_REV) -+#define MV_6190_A1_NAME "88F6190 A1" -+ -+#define MV_6180_A1_REV 0x3 -+#define MV_6180_A1_ID ((MV_6180_DEV_ID << 16) | MV_6180_A1_REV) -+#define MV_6180_A1_NAME "88F6180 A1" -+ -+#define MV_88F6XXX_A0_REV 0x2 -+#define MV_88F6XXX_A1_REV 0x3 -+/* Disco-Duo */ -+#define MV_78XX0_ZY_DEV_ID 0x6381 -+#define MV_78XX0_ZY_NAME "MV78X00" -+ -+#define MV_78XX0_Z0_REV 0x1 -+#define MV_78XX0_Z0_ID ((MV_78XX0_ZY_DEV_ID << 16) | MV_78XX0_Z0_REV) -+#define MV_78XX0_Z0_NAME "78X00 Z0" -+ -+#define MV_78XX0_Y0_REV 0x2 -+#define MV_78XX0_Y0_ID ((MV_78XX0_ZY_DEV_ID << 16) | MV_78XX0_Y0_REV) -+#define MV_78XX0_Y0_NAME "78X00 Y0" -+ -+#define MV_78XX0_DEV_ID 0x7800 -+#define MV_78XX0_NAME "MV78X00" -+ -+#define MV_76100_DEV_ID 0x7610 -+#define MV_78200_DEV_ID 0x7820 -+#define MV_78100_DEV_ID 0x7810 -+#define MV_78XX0_A0_REV 0x1 -+#define MV_78XX0_A1_REV 0x2 -+ -+#define MV_76100_NAME "MV76100" -+#define MV_78100_NAME "MV78100" -+#define MV_78200_NAME "MV78200" -+ -+#define MV_76100_A0_ID ((MV_76100_DEV_ID << 16) | MV_78XX0_A0_REV) -+#define MV_78100_A0_ID ((MV_78100_DEV_ID << 16) | MV_78XX0_A0_REV) -+#define MV_78200_A0_ID ((MV_78200_DEV_ID << 16) | MV_78XX0_A0_REV) -+ -+#define MV_76100_A1_ID ((MV_76100_DEV_ID << 16) | MV_78XX0_A1_REV) -+#define MV_78100_A1_ID ((MV_78100_DEV_ID << 16) | MV_78XX0_A1_REV) -+#define MV_78200_A1_ID ((MV_78200_DEV_ID << 16) | MV_78XX0_A1_REV) -+ -+#define MV_76100_A0_NAME "MV76100 A0" -+#define MV_78100_A0_NAME "MV78100 A0" -+#define MV_78200_A0_NAME "MV78200 A0" -+#define MV_78XX0_A0_NAME "MV78XX0 A0" -+ -+#define MV_76100_A1_NAME "MV76100 A1" -+#define MV_78100_A1_NAME "MV78100 A1" -+#define MV_78200_A1_NAME "MV78200 A1" -+#define MV_78XX0_A1_NAME "MV78XX0 A1" -+ -+/*MV88F632X family*/ -+#define MV_6321_DEV_ID 0x6321 -+#define MV_6322_DEV_ID 0x6322 -+#define MV_6323_DEV_ID 0x6323 -+ -+#define MV_6321_NAME "88F6321" -+#define MV_6322_NAME "88F6322" -+#define MV_6323_NAME "88F6323" -+ -+#define MV_632X_A1_REV 0x2 -+ -+#define MV_6321_A1_ID ((MV_6321_DEV_ID << 16) | MV_632X_A1_REV) -+#define MV_6322_A1_ID ((MV_6322_DEV_ID << 16) | MV_632X_A1_REV) -+#define MV_6323_A1_ID ((MV_6323_DEV_ID << 16) | MV_632X_A1_REV) -+ -+#define MV_6321_A1_NAME "88F6321 A1" -+#define MV_6322_A1_NAME "88F6322 A1" -+#define MV_6323_A1_NAME "88F6323 A1" -+ -+ -+#endif /* __INCmvDeviceIdh */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/common/mvHalVer.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/common/mvHalVer.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/common/mvHalVer.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/common/mvHalVer.h 2010-11-09 20:28:07.069296580 +0100 -@@ -0,0 +1,73 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvHalVerh -+#define __INCmvHalVerh -+ -+/* Defines */ -+#define MV_HAL_VERSION "FEROCEON_HAL_3_1_7" -+#define MV_RELEASE_BASELINE "SoCandControllers_FEROCEON_RELEASE_7_9_2009_KW_4_3_4_DD_2_1_4_6183_1_1_4" -+ -+#endif /* __INCmvHalVerh */ -\ No newline at end of file -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/common/mvStack.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/common/mvStack.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/common/mvStack.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/common/mvStack.c 2010-11-09 20:28:07.102606889 +0100 -@@ -0,0 +1,100 @@ -+/******************************************************************************* -+* Copyright 2003, Marvell Semiconductor Israel LTD. * -+* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL. * -+* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT * -+* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE * -+* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL. * -+* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED, * -+* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE. * -+* * -+* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, * -+* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL * -+* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K. * -+* (MJKK), MARVELL SEMICONDUCTOR ISRAEL LTD (MSIL). * -+******************************************************************************** -+* mvQueue.c -+* -+* FILENAME: $Workfile: mvStack.c $ -+* REVISION: $Revision: 1.1 $ -+* LAST UPDATE: $Modtime: $ -+* -+* DESCRIPTION: -+* This file implements simple Stack LIFO functionality. -+*******************************************************************************/ -+ -+/* includes */ -+#include "mvOs.h" -+#include "mvTypes.h" -+#include "mvDebug.h" -+#include "mvStack.h" -+ -+/* defines */ -+ -+ -+/* Public functions */ -+ -+ -+/* Purpose: Create new stack -+ * Inputs: -+ * - MV_U32 noOfElements - maximum number of elements in the stack. -+ * Each element 4 bytes size -+ * Return: void* - pointer to created stack. -+ */ -+void* mvStackCreate(int numOfElements) -+{ -+ MV_STACK* pStack; -+ MV_U32* pStackElements; -+ -+ pStack = (MV_STACK*)mvOsMalloc(sizeof(MV_STACK)); -+ pStackElements = (MV_U32*)mvOsMalloc(numOfElements*sizeof(MV_U32)); -+ if( (pStack == NULL) || (pStackElements == NULL) ) -+ { -+ mvOsPrintf("mvStack: Can't create new stack\n"); -+ return NULL; -+ } -+ memset(pStackElements, 0, numOfElements*sizeof(MV_U32)); -+ pStack->numOfElements = numOfElements; -+ pStack->stackIdx = 0; -+ pStack->stackElements = pStackElements; -+ -+ return pStack; -+} -+ -+/* Purpose: Delete existing stack -+ * Inputs: -+ * - void* stackHndl - Stack handle as returned by "mvStackCreate()" function -+ * -+ * Return: MV_STATUS MV_NOT_FOUND - Failure. StackHandle is not valid. -+ * MV_OK - Success. -+ */ -+MV_STATUS mvStackDelete(void* stackHndl) -+{ -+ MV_STACK* pStack = (MV_STACK*)stackHndl; -+ -+ if( (pStack == NULL) || (pStack->stackElements == NULL) ) -+ return MV_NOT_FOUND; -+ -+ mvOsFree(pStack->stackElements); -+ mvOsFree(pStack); -+ -+ return MV_OK; -+} -+ -+ -+/* PrintOut status of the stack */ -+void mvStackStatus(void* stackHndl, MV_BOOL isPrintElements) -+{ -+ int i; -+ MV_STACK* pStack = (MV_STACK*)stackHndl; -+ -+ mvOsPrintf("StackHandle=%p, pElements=%p, numElements=%d, stackIdx=%d\n", -+ stackHndl, pStack->stackElements, pStack->numOfElements, -+ pStack->stackIdx); -+ if(isPrintElements == MV_TRUE) -+ { -+ for(i=0; istackIdx; i++) -+ { -+ mvOsPrintf("%3d. Value=0x%x\n", i, pStack->stackElements[i]); -+ } -+ } -+} -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/common/mvStack.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/common/mvStack.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/common/mvStack.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/common/mvStack.h 2010-11-09 20:28:07.160842220 +0100 -@@ -0,0 +1,140 @@ -+/******************************************************************************* -+* Copyright 2003, Marvell Semiconductor Israel LTD. * -+* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL. * -+* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT * -+* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE * -+* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL. * -+* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED, * -+* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE. * -+* * -+* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, * -+* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL * -+* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K. * -+* (MJKK), MARVELL SEMICONDUCTOR ISRAEL LTD (MSIL). * -+******************************************************************************** -+* mvStack.h - Header File for : -+* -+* FILENAME: $Workfile: mvStack.h $ -+* REVISION: $Revision: 1.1 $ -+* LAST UPDATE: $Modtime: $ -+* -+* DESCRIPTION: -+* This file defines simple Stack (LIFO) functionality. -+* -+*******************************************************************************/ -+ -+#ifndef __mvStack_h__ -+#define __mvStack_h__ -+ -+ -+/* includes */ -+#include "mvTypes.h" -+ -+ -+/* defines */ -+ -+ -+/* typedefs */ -+/* Data structure describes general purpose Stack */ -+typedef struct -+{ -+ int stackIdx; -+ int numOfElements; -+ MV_U32* stackElements; -+} MV_STACK; -+ -+static INLINE MV_BOOL mvStackIsFull(void* stackHndl) -+{ -+ MV_STACK* pStack = (MV_STACK*)stackHndl; -+ -+ if(pStack->stackIdx == pStack->numOfElements) -+ return MV_TRUE; -+ -+ return MV_FALSE; -+} -+ -+static INLINE MV_BOOL mvStackIsEmpty(void* stackHndl) -+{ -+ MV_STACK* pStack = (MV_STACK*)stackHndl; -+ -+ if(pStack->stackIdx == 0) -+ return MV_TRUE; -+ -+ return MV_FALSE; -+} -+/* Purpose: Push new element to stack -+ * Inputs: -+ * - void* stackHndl - Stack handle as returned by "mvStackCreate()" function. -+ * - MV_U32 value - New element. -+ * -+ * Return: MV_STATUS MV_FULL - Failure. Stack is full. -+ * MV_OK - Success. Element is put to stack. -+ */ -+static INLINE void mvStackPush(void* stackHndl, MV_U32 value) -+{ -+ MV_STACK* pStack = (MV_STACK*)stackHndl; -+ -+#ifdef MV_RT_DEBUG -+ if(pStack->stackIdx == pStack->numOfElements) -+ { -+ mvOsPrintf("mvStackPush: Stack is FULL\n"); -+ return; -+ } -+#endif /* MV_RT_DEBUG */ -+ -+ pStack->stackElements[pStack->stackIdx] = value; -+ pStack->stackIdx++; -+} -+ -+/* Purpose: Pop element from the top of stack and copy it to "pValue" -+ * Inputs: -+ * - void* stackHndl - Stack handle as returned by "mvStackCreate()" function. -+ * - MV_U32 value - Element in the top of stack. -+ * -+ * Return: MV_STATUS MV_EMPTY - Failure. Stack is empty. -+ * MV_OK - Success. Element is removed from the stack and -+ * copied to pValue argument -+ */ -+static INLINE MV_U32 mvStackPop(void* stackHndl) -+{ -+ MV_STACK* pStack = (MV_STACK*)stackHndl; -+ -+#ifdef MV_RT_DEBUG -+ if(pStack->stackIdx == 0) -+ { -+ mvOsPrintf("mvStackPop: Stack is EMPTY\n"); -+ return 0; -+ } -+#endif /* MV_RT_DEBUG */ -+ -+ pStack->stackIdx--; -+ return pStack->stackElements[pStack->stackIdx]; -+} -+ -+static INLINE int mvStackIndex(void* stackHndl) -+{ -+ MV_STACK* pStack = (MV_STACK*)stackHndl; -+ -+ return pStack->stackIdx; -+} -+ -+static INLINE int mvStackFreeElements(void* stackHndl) -+{ -+ MV_STACK* pStack = (MV_STACK*)stackHndl; -+ -+ return (pStack->numOfElements - pStack->stackIdx); -+} -+ -+/* mvStack.h API list */ -+ -+/* Create new Stack */ -+void* mvStackCreate(int numOfElements); -+ -+/* Delete existing stack */ -+MV_STATUS mvStackDelete(void* stackHndl); -+ -+/* Print status of the stack */ -+void mvStackStatus(void* stackHndl, MV_BOOL isPrintElements); -+ -+#endif /* __mvStack_h__ */ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/common/mvTypes.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/common/mvTypes.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/common/mvTypes.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/common/mvTypes.h 2010-11-09 20:28:07.191385803 +0100 -@@ -0,0 +1,245 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvTypesh -+#define __INCmvTypesh -+ -+/* Defines */ -+ -+/* The following is a list of Marvell status */ -+#define MV_ERROR (-1) -+#define MV_OK (0x00) /* Operation succeeded */ -+#define MV_FAIL (0x01) /* Operation failed */ -+#define MV_BAD_VALUE (0x02) /* Illegal value (general) */ -+#define MV_OUT_OF_RANGE (0x03) /* The value is out of range */ -+#define MV_BAD_PARAM (0x04) /* Illegal parameter in function called */ -+#define MV_BAD_PTR (0x05) /* Illegal pointer value */ -+#define MV_BAD_SIZE (0x06) /* Illegal size */ -+#define MV_BAD_STATE (0x07) /* Illegal state of state machine */ -+#define MV_SET_ERROR (0x08) /* Set operation failed */ -+#define MV_GET_ERROR (0x09) /* Get operation failed */ -+#define MV_CREATE_ERROR (0x0A) /* Fail while creating an item */ -+#define MV_NOT_FOUND (0x0B) /* Item not found */ -+#define MV_NO_MORE (0x0C) /* No more items found */ -+#define MV_NO_SUCH (0x0D) /* No such item */ -+#define MV_TIMEOUT (0x0E) /* Time Out */ -+#define MV_NO_CHANGE (0x0F) /* Parameter(s) is already in this value */ -+#define MV_NOT_SUPPORTED (0x10) /* This request is not support */ -+#define MV_NOT_IMPLEMENTED (0x11) /* Request supported but not implemented */ -+#define MV_NOT_INITIALIZED (0x12) /* The item is not initialized */ -+#define MV_NO_RESOURCE (0x13) /* Resource not available (memory ...) */ -+#define MV_FULL (0x14) /* Item is full (Queue or table etc...) */ -+#define MV_EMPTY (0x15) /* Item is empty (Queue or table etc...) */ -+#define MV_INIT_ERROR (0x16) /* Error occured while INIT process */ -+#define MV_HW_ERROR (0x17) /* Hardware error */ -+#define MV_TX_ERROR (0x18) /* Transmit operation not succeeded */ -+#define MV_RX_ERROR (0x19) /* Recieve operation not succeeded */ -+#define MV_NOT_READY (0x1A) /* The other side is not ready yet */ -+#define MV_ALREADY_EXIST (0x1B) /* Tried to create existing item */ -+#define MV_OUT_OF_CPU_MEM (0x1C) /* Cpu memory allocation failed. */ -+#define MV_NOT_STARTED (0x1D) /* Not started yet */ -+#define MV_BUSY (0x1E) /* Item is busy. */ -+#define MV_TERMINATE (0x1F) /* Item terminates it's work. */ -+#define MV_NOT_ALIGNED (0x20) /* Wrong alignment */ -+#define MV_NOT_ALLOWED (0x21) /* Operation NOT allowed */ -+#define MV_WRITE_PROTECT (0x22) /* Write protected */ -+ -+ -+#define MV_INVALID (int)(-1) -+ -+#define MV_FALSE 0 -+#define MV_TRUE (!(MV_FALSE)) -+ -+ -+#ifndef NULL -+#define NULL ((void*)0) -+#endif -+ -+ -+#ifndef MV_ASMLANGUAGE -+/* typedefs */ -+ -+typedef char MV_8; -+typedef unsigned char MV_U8; -+ -+typedef int MV_32; -+typedef unsigned int MV_U32; -+ -+typedef short MV_16; -+typedef unsigned short MV_U16; -+ -+#ifdef MV_PPC64 -+typedef long MV_64; -+typedef unsigned long MV_U64; -+#else -+typedef long long MV_64; -+typedef unsigned long long MV_U64; -+#endif -+ -+typedef long MV_LONG; /* 32/64 */ -+typedef unsigned long MV_ULONG; /* 32/64 */ -+ -+typedef int MV_STATUS; -+typedef int MV_BOOL; -+typedef void MV_VOID; -+typedef float MV_FLOAT; -+ -+typedef int (*MV_FUNCPTR) (void); /* ptr to function returning int */ -+typedef void (*MV_VOIDFUNCPTR) (void); /* ptr to function returning void */ -+typedef double (*MV_DBLFUNCPTR) (void); /* ptr to function returning double*/ -+typedef float (*MV_FLTFUNCPTR) (void); /* ptr to function returning float */ -+ -+typedef MV_U32 MV_KHZ; -+typedef MV_U32 MV_MHZ; -+typedef MV_U32 MV_HZ; -+ -+ -+/* This enumerator describes the set of commands that can be applied on */ -+/* an engine (e.g. IDMA, XOR). Appling a comman depends on the current */ -+/* status (see MV_STATE enumerator) */ -+/* Start can be applied only when status is IDLE */ -+/* Stop can be applied only when status is IDLE, ACTIVE or PAUSED */ -+/* Pause can be applied only when status is ACTIVE */ -+/* Restart can be applied only when status is PAUSED */ -+typedef enum _mvCommand -+{ -+ MV_START, /* Start */ -+ MV_STOP, /* Stop */ -+ MV_PAUSE, /* Pause */ -+ MV_RESTART /* Restart */ -+} MV_COMMAND; -+ -+/* This enumerator describes the set of state conditions. */ -+/* Moving from one state to other is stricted. */ -+typedef enum _mvState -+{ -+ MV_IDLE, -+ MV_ACTIVE, -+ MV_PAUSED, -+ MV_UNDEFINED_STATE -+} MV_STATE; -+ -+ -+/* This structure describes address space window. Window base can be */ -+/* 64 bit, window size up to 4GB */ -+typedef struct _mvAddrWin -+{ -+ MV_U32 baseLow; /* 32bit base low */ -+ MV_U32 baseHigh; /* 32bit base high */ -+ MV_U32 size; /* 32bit size */ -+}MV_ADDR_WIN; -+ -+/* This binary enumerator describes protection attribute status */ -+typedef enum _mvProtRight -+{ -+ ALLOWED, /* Protection attribute allowed */ -+ FORBIDDEN /* Protection attribute forbidden */ -+}MV_PROT_RIGHT; -+ -+/* Unified struct for Rx and Tx packet operations. The user is required to */ -+/* be familier only with Tx/Rx descriptor command status. */ -+typedef struct _bufInfo -+{ -+ MV_U32 cmdSts; /* Tx/Rx command status */ -+ MV_U16 byteCnt; /* Size of valid data in the buffer */ -+ MV_U16 bufSize; /* Total size of the buffer */ -+ MV_U8 *pBuff; /* Pointer to Buffer */ -+ MV_U8 *pData; /* Pointer to data in the Buffer */ -+ MV_U32 userInfo1; /* Tx/Rx attached user information 1 */ -+ MV_U32 userInfo2; /* Tx/Rx attached user information 2 */ -+ struct _bufInfo *pNextBufInfo; /* Next buffer in packet */ -+} BUF_INFO; -+ -+/* This structure contains information describing one of buffers -+ * (fragments) they are built Ethernet packet. -+ */ -+typedef struct -+{ -+ MV_U8* bufVirtPtr; -+ MV_ULONG bufPhysAddr; -+ MV_U32 bufSize; -+ MV_U32 dataSize; -+ MV_U32 memHandle; -+ MV_32 bufAddrShift; -+} MV_BUF_INFO; -+ -+/* This structure contains information describing Ethernet packet. -+ * The packet can be divided for few buffers (fragments) -+ */ -+typedef struct -+{ -+ MV_ULONG osInfo; -+ MV_BUF_INFO *pFrags; -+ MV_U32 status; -+ MV_U16 pktSize; -+ MV_U16 numFrags; -+ MV_U32 ownerId; -+ MV_U32 fragIP; -+} MV_PKT_INFO; -+ -+#endif /* MV_ASMLANGUAGE */ -+ -+#endif /* __INCmvTypesh */ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/dbg-trace.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/dbg-trace.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/dbg-trace.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/dbg-trace.c 2010-11-09 20:28:07.232495685 +0100 -@@ -0,0 +1,110 @@ -+#include -+#include -+#include -+#include "dbg-trace.h" -+ -+#define TRACE_ARR_LEN 800 -+#define STR_LEN 128 -+struct trace { -+ struct timeval tv; -+ char str[STR_LEN]; -+ unsigned int callback_val1; -+ unsigned int callback_val2; -+ char valid; -+}; -+static unsigned int (*trc_callback1) (unsigned char) = NULL; -+static unsigned int (*trc_callback2) (unsigned char) = NULL; -+static unsigned char trc_param1 = 0; -+static unsigned char trc_param2 = 0; -+struct trace *trc_arr; -+static int trc_index; -+static int trc_active = 0; -+ -+void TRC_START() -+{ -+ trc_active = 1; -+} -+ -+void TRC_STOP() -+{ -+ trc_active = 0; -+} -+ -+void TRC_INIT(void *callback1, void *callback2, unsigned char callback1_param, unsigned char callback2_param) -+{ -+ printk("Marvell debug tracing is on\n"); -+ trc_arr = (struct trace *)kmalloc(TRACE_ARR_LEN*sizeof(struct trace),GFP_KERNEL); -+ if(trc_arr == NULL) -+ { -+ printk("Can't allocate Debug Trace buffer\n"); -+ return; -+ } -+ memset(trc_arr,0,TRACE_ARR_LEN*sizeof(struct trace)); -+ trc_index = 0; -+ trc_callback1 = callback1; -+ trc_callback2 = callback2; -+ trc_param1 = callback1_param; -+ trc_param2 = callback2_param; -+} -+void TRC_REC(char *fmt,...) -+{ -+ va_list args; -+ struct trace *trc = &trc_arr[trc_index]; -+ -+ if(trc_active == 0) -+ return; -+ -+ do_gettimeofday(&trc->tv); -+ if(trc_callback1) -+ trc->callback_val1 = trc_callback1(trc_param1); -+ if(trc_callback2) -+ trc->callback_val2 = trc_callback2(trc_param2); -+ va_start(args, fmt); -+ vsprintf(trc->str,fmt,args); -+ va_end(args); -+ trc->valid = 1; -+ if((++trc_index) == TRACE_ARR_LEN) { -+ trc_index = 0; -+ } -+} -+void TRC_OUTPUT(void) -+{ -+ int i,j; -+ struct trace *p; -+ printk("\n\nTrace %d items\n",TRACE_ARR_LEN); -+ for(i=0,j=trc_index; ivalid) { -+ unsigned long uoffs; -+ struct trace *plast; -+ if(p == &trc_arr[0]) -+ plast = &trc_arr[TRACE_ARR_LEN-1]; -+ else -+ plast = p-1; -+ if(p->tv.tv_sec == ((plast)->tv.tv_sec)) -+ uoffs = (p->tv.tv_usec - ((plast)->tv.tv_usec)); -+ else -+ uoffs = (1000000 - ((plast)->tv.tv_usec)) + -+ ((p->tv.tv_sec - ((plast)->tv.tv_sec) - 1) * 1000000) + -+ p->tv.tv_usec; -+ printk("%03d: [+%ld usec]", j, (unsigned long)uoffs); -+ if(trc_callback1) -+ printk("[%u]",p->callback_val1); -+ if(trc_callback2) -+ printk("[%u]",p->callback_val2); -+ printk(": %s",p->str); -+ } -+ p->valid = 0; -+ } -+ memset(trc_arr,0,TRACE_ARR_LEN*sizeof(struct trace)); -+ trc_index = 0; -+} -+void TRC_RELEASE(void) -+{ -+ kfree(trc_arr); -+ trc_index = 0; -+} -+ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/dbg-trace.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/dbg-trace.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/dbg-trace.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/dbg-trace.h 2010-11-09 20:28:07.276291416 +0100 -@@ -0,0 +1,24 @@ -+ -+#ifndef _MV_DBG_TRCE_H_ -+#define _MV_DBG_TRCE_H_ -+ -+#ifdef CONFIG_MV_DBG_TRACE -+void TRC_INIT(void *callback1, void *callback2, -+ unsigned char callback1_param, unsigned char callback2_param); -+void TRC_REC(char *fmt,...); -+void TRC_OUTPUT(void); -+void TRC_RELEASE(void); -+void TRC_START(void); -+void TRC_STOP(void); -+ -+#else -+#define TRC_INIT(x1,x2,x3,x4) -+#define TRC_REC(X...) -+#define TRC_OUTPUT() -+#define TRC_RELEASE() -+#define TRC_START() -+#define TRC_STOP() -+#endif -+ -+ -+#endif -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c 2010-11-09 20:28:07.327371127 +0100 -@@ -0,0 +1,2513 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "boardEnv/mvBoardEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+#include "cpu/mvCpu.h" -+#include "cntmr/mvCntmr.h" -+#include "gpp/mvGpp.h" -+#include "twsi/mvTwsi.h" -+#include "pex/mvPex.h" -+#include "device/mvDevice.h" -+#include "eth/gbe/mvEthRegs.h" -+ -+/* defines */ -+/* #define MV_DEBUG */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+extern MV_CPU_ARM_CLK _cpuARMDDRCLK[]; -+ -+#define CODE_IN_ROM MV_FALSE -+#define CODE_IN_RAM MV_TRUE -+ -+extern MV_BOARD_INFO* boardInfoTbl[]; -+#define BOARD_INFO(boardId) boardInfoTbl[boardId - BOARD_ID_BASE] -+ -+/* Locals */ -+static MV_DEV_CS_INFO* boardGetDevEntry(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); -+ -+MV_U32 tClkRate = -1; -+ -+ -+/******************************************************************************* -+* mvBoardEnvInit - Init board -+* -+* DESCRIPTION: -+* In this function the board environment take care of device bank -+* initialization. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvBoardEnvInit(MV_VOID) -+{ -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardEnvInit:Board unknown.\n"); -+ return; -+ -+ } -+ -+ /* Set GPP Out value */ -+ MV_REG_WRITE(GPP_DATA_OUT_REG(0), BOARD_INFO(boardId)->gppOutValLow); -+ MV_REG_WRITE(GPP_DATA_OUT_REG(1), BOARD_INFO(boardId)->gppOutValHigh); -+ -+ /* set GPP polarity */ -+ mvGppPolaritySet(0, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValLow); -+ mvGppPolaritySet(1, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValHigh); -+ -+ /* Workaround for Erratum FE-MISC-70*/ -+ if(mvCtrlRevGet()==MV_88F6XXX_A0_REV) -+ { -+ BOARD_INFO(boardId)->gppOutEnValLow &= 0xfffffffd; -+ BOARD_INFO(boardId)->gppOutEnValLow |= (BOARD_INFO(boardId)->gppOutEnValHigh) & 0x00000002; -+ } /*End of WA*/ -+ -+ /* Set GPP Out Enable*/ -+ mvGppTypeSet(0, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValLow); -+ mvGppTypeSet(1, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValHigh); -+ -+ /* Nand CE */ -+ MV_REG_BIT_SET(NAND_CTRL_REG, NAND_ACTCEBOOT_BIT); -+} -+ -+/******************************************************************************* -+* mvBoardModelGet - Get Board model -+* -+* DESCRIPTION: -+* This function returns 16bit describing board model. -+* Board model is constructed of one byte major and minor numbers in the -+* following manner: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* String describing board model. -+* -+*******************************************************************************/ -+MV_U16 mvBoardModelGet(MV_VOID) -+{ -+ return (mvBoardIdGet() >> 16); -+} -+ -+/******************************************************************************* -+* mbBoardRevlGet - Get Board revision -+* -+* DESCRIPTION: -+* This function returns a 32bit describing the board revision. -+* Board revision is constructed of 4bytes. 2bytes describes major number -+* and the other 2bytes describes minor munber. -+* For example for board revision 3.4 the function will return -+* 0x00030004. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* String describing board model. -+* -+*******************************************************************************/ -+MV_U16 mvBoardRevGet(MV_VOID) -+{ -+ return (mvBoardIdGet() & 0xFFFF); -+} -+ -+/******************************************************************************* -+* mvBoardNameGet - Get Board name -+* -+* DESCRIPTION: -+* This function returns a string describing the board model and revision. -+* String is extracted from board I2C EEPROM. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* pNameBuff - Buffer to contain board name string. Minimum size 32 chars. -+* -+* RETURN: -+* -+* MV_ERROR if informantion can not be read. -+*******************************************************************************/ -+MV_STATUS mvBoardNameGet(char *pNameBuff) -+{ -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsSPrintf (pNameBuff, "Board unknown.\n"); -+ return MV_ERROR; -+ -+ } -+ -+ mvOsSPrintf (pNameBuff, "%s",BOARD_INFO(boardId)->boardName); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvBoardIsPortInSgmii - -+* -+* DESCRIPTION: -+* This routine returns MV_TRUE for port number works in SGMII or MV_FALSE -+* For all other options. -+* -+* INPUT: -+* ethPortNum - Ethernet port number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE - port in SGMII. -+* MV_FALSE - other. -+* -+*******************************************************************************/ -+MV_BOOL mvBoardIsPortInSgmii(MV_U32 ethPortNum) -+{ -+ MV_BOOL ethPortSgmiiSupport[BOARD_ETH_PORT_NUM] = MV_ETH_PORT_SGMII; -+ -+ if(ethPortNum >= BOARD_ETH_PORT_NUM) -+ { -+ mvOsPrintf ("Invalid portNo=%d\n", ethPortNum); -+ return MV_FALSE; -+ } -+ return ethPortSgmiiSupport[ethPortNum]; -+} -+ -+/******************************************************************************* -+* mvBoardIsPortInGmii - -+* -+* DESCRIPTION: -+* This routine returns MV_TRUE for port number works in GMII or MV_FALSE -+* For all other options. -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE - port in GMII. -+* MV_FALSE - other. -+* -+*******************************************************************************/ -+MV_BOOL mvBoardIsPortInGmii(MV_VOID) -+{ -+ MV_U32 devClassId, devClass = 0; -+ if (mvBoardMppGroupTypeGet(devClass) == MV_BOARD_AUTO) -+ { -+ /* Get MPP module ID */ -+ devClassId = mvBoarModuleTypeGet(devClass); -+ if (MV_BOARD_MODULE_GMII_ID == devClassId) -+ return MV_TRUE; -+ } -+ else if (mvBoardMppGroupTypeGet(devClass) == MV_BOARD_GMII) -+ return MV_TRUE; -+ -+ return MV_FALSE; -+} -+/******************************************************************************* -+* mvBoardPhyAddrGet - Get the phy address -+* -+* DESCRIPTION: -+* This routine returns the Phy address of a given ethernet port. -+* -+* INPUT: -+* ethPortNum - Ethernet port number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit describing Phy address, -1 if the port number is wrong. -+* -+*******************************************************************************/ -+MV_32 mvBoardPhyAddrGet(MV_U32 ethPortNum) -+{ -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardPhyAddrGet: Board unknown.\n"); -+ return MV_ERROR; -+ } -+ -+ return BOARD_INFO(boardId)->pBoardMacInfo[ethPortNum].boardEthSmiAddr; -+} -+ -+/******************************************************************************* -+* mvBoardMacSpeedGet - Get the Mac speed -+* -+* DESCRIPTION: -+* This routine returns the Mac speed if pre define of a given ethernet port. -+* -+* INPUT: -+* ethPortNum - Ethernet port number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BOARD_MAC_SPEED, -1 if the port number is wrong. -+* -+*******************************************************************************/ -+MV_BOARD_MAC_SPEED mvBoardMacSpeedGet(MV_U32 ethPortNum) -+{ -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardMacSpeedGet: Board unknown.\n"); -+ return MV_ERROR; -+ } -+ -+ return BOARD_INFO(boardId)->pBoardMacInfo[ethPortNum].boardMacSpeed; -+} -+ -+/******************************************************************************* -+* mvBoardLinkStatusIrqGet - Get the IRQ number for the link status indication -+* -+* DESCRIPTION: -+* This routine returns the IRQ number for the link status indication. -+* -+* INPUT: -+* ethPortNum - Ethernet port number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* the number of the IRQ for the link status indication, -1 if the port -+* number is wrong or if not relevant. -+* -+*******************************************************************************/ -+MV_32 mvBoardLinkStatusIrqGet(MV_U32 ethPortNum) -+{ -+ MV_U32 boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardLinkStatusIrqGet: Board unknown.\n"); -+ return MV_ERROR; -+ } -+ -+ return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].linkStatusIrq; -+} -+ -+/******************************************************************************* -+* mvBoardSwitchPortGet - Get the mapping between the board connector and the -+* Ethernet Switch port -+* -+* DESCRIPTION: -+* This routine returns the matching Switch port. -+* -+* INPUT: -+* ethPortNum - Ethernet port number. -+* boardPortNum - logical number of the connector on the board -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* the matching Switch port, -1 if the port number is wrong or if not relevant. -+* -+*******************************************************************************/ -+MV_32 mvBoardSwitchPortGet(MV_U32 ethPortNum, MV_U8 boardPortNum) -+{ -+ MV_U32 boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardSwitchPortGet: Board unknown.\n"); -+ return MV_ERROR; -+ } -+ if (boardPortNum >= BOARD_ETH_SWITCH_PORT_NUM) -+ { -+ mvOsPrintf("mvBoardSwitchPortGet: Illegal board port number.\n"); -+ return MV_ERROR; -+ } -+ -+ return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].qdPort[boardPortNum]; -+} -+ -+/******************************************************************************* -+* mvBoardSwitchCpuPortGet - Get the the Ethernet Switch CPU port -+* -+* DESCRIPTION: -+* This routine returns the Switch CPU port. -+* -+* INPUT: -+* ethPortNum - Ethernet port number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* the Switch CPU port, -1 if the port number is wrong or if not relevant. -+* -+*******************************************************************************/ -+MV_32 mvBoardSwitchCpuPortGet(MV_U32 ethPortNum) -+{ -+ MV_U32 boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardSwitchCpuPortGet: Board unknown.\n"); -+ return MV_ERROR; -+ } -+ -+ return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].qdCpuPort; -+} -+ -+/******************************************************************************* -+* mvBoardIsSwitchConnected - Get switch connection status -+* DESCRIPTION: -+* This routine returns port's connection status -+* -+* INPUT: -+* ethPortNum - Ethernet port number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 1 - if ethPortNum is connected to switch, 0 otherwise -+* -+*******************************************************************************/ -+MV_32 mvBoardIsSwitchConnected(MV_U32 ethPortNum) -+{ -+ MV_U32 boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardIsSwitchConnected: Board unknown.\n"); -+ return MV_ERROR; -+ } -+ -+ if(ethPortNum >= BOARD_INFO(boardId)->numBoardMacInfo) -+ { -+ mvOsPrintf("mvBoardIsSwitchConnected: Illegal port number(%u)\n", ethPortNum); -+ return MV_ERROR; -+ } -+ -+ if((MV_32)(BOARD_INFO(boardId)->pSwitchInfo)) -+ return (MV_32)(BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].switchOnPort == ethPortNum); -+ else -+ return 0; -+} -+/******************************************************************************* -+* mvBoardSmiScanModeGet - Get Switch SMI scan mode -+* -+* DESCRIPTION: -+* This routine returns Switch SMI scan mode. -+* -+* INPUT: -+* ethPortNum - Ethernet port number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 1 for SMI_MANUAL_MODE, -1 if the port number is wrong or if not relevant. -+* -+*******************************************************************************/ -+MV_32 mvBoardSmiScanModeGet(MV_U32 ethPortNum) -+{ -+ MV_U32 boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardSmiScanModeGet: Board unknown.\n"); -+ return MV_ERROR; -+ } -+ -+ return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].smiScanMode; -+} -+/******************************************************************************* -+* mvBoardSpecInitGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: Return MV_TRUE and parameters in case board need spesific phy init, -+* otherwise return MV_FALSE. -+* -+* -+*******************************************************************************/ -+ -+MV_BOOL mvBoardSpecInitGet(MV_U32* regOff, MV_U32* data) -+{ -+ return MV_FALSE; -+} -+ -+/******************************************************************************* -+* mvBoardTclkGet - Get the board Tclk (Controller clock) -+* -+* DESCRIPTION: -+* This routine extract the controller core clock. -+* This function uses the controller counters to make identification. -+* Note: In order to avoid interference, make sure task context switch -+* and interrupts will not occure during this function operation -+* -+* INPUT: -+* countNum - Counter number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit clock cycles in Hertz. -+* -+*******************************************************************************/ -+MV_U32 mvBoardTclkGet(MV_VOID) -+{ -+ if(mvCtrlModelGet()==MV_6281_DEV_ID) -+ { -+#if defined(TCLK_AUTO_DETECT) -+ MV_U32 tmpTClkRate = MV_BOARD_TCLK_166MHZ; -+ -+ tmpTClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ tmpTClkRate &= MSAR_TCLCK_MASK; -+ -+ switch (tmpTClkRate) -+ { -+ case MSAR_TCLCK_166: -+ return MV_BOARD_TCLK_166MHZ; -+ break; -+ case MSAR_TCLCK_200: -+ return MV_BOARD_TCLK_200MHZ; -+ break; -+ } -+#else -+ return MV_BOARD_TCLK_200MHZ; -+#endif -+ } -+ -+ return MV_BOARD_TCLK_166MHZ; -+ -+} -+/******************************************************************************* -+* mvBoardSysClkGet - Get the board SysClk (CPU bus clock) -+* -+* DESCRIPTION: -+* This routine extract the CPU bus clock. -+* -+* INPUT: -+* countNum - Counter number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit clock cycles in Hertz. -+* -+*******************************************************************************/ -+static MV_U32 mvBoard6180SysClkGet(MV_VOID) -+{ -+ MV_U32 sysClkRate=0; -+ MV_CPU_ARM_CLK _cpu6180_ddr_l2_CLK[] = MV_CPU6180_DDR_L2_CLCK_TBL; -+ -+ sysClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ sysClkRate = sysClkRate & MSAR_CPUCLCK_MASK_6180; -+ sysClkRate = sysClkRate >> MSAR_CPUCLCK_OFFS_6180; -+ -+ sysClkRate = _cpu6180_ddr_l2_CLK[sysClkRate].ddrClk; -+ -+ return sysClkRate; -+ -+} -+ -+MV_U32 mvBoardSysClkGet(MV_VOID) -+{ -+#ifdef SYSCLK_AUTO_DETECT -+ MV_U32 sysClkRate, tmp, pClkRate, indexDdrRtio; -+ MV_U32 cpuCLK[] = MV_CPU_CLCK_TBL; -+ MV_U32 ddrRtio[][2] = MV_DDR_CLCK_RTIO_TBL; -+ -+ if(mvCtrlModelGet() == MV_6180_DEV_ID) -+ return mvBoard6180SysClkGet(); -+ -+ tmp = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ pClkRate = MSAR_CPUCLCK_EXTRACT(tmp); -+ pClkRate = cpuCLK[pClkRate]; -+ -+ indexDdrRtio = tmp & MSAR_DDRCLCK_RTIO_MASK; -+ indexDdrRtio = indexDdrRtio >> MSAR_DDRCLCK_RTIO_OFFS; -+ if(ddrRtio[indexDdrRtio][0] != 0) -+ sysClkRate = ((pClkRate * ddrRtio[indexDdrRtio][1]) / ddrRtio[indexDdrRtio][0]); -+ else -+ sysClkRate = 0; -+ return sysClkRate; -+#else -+ return MV_BOARD_DEFAULT_SYSCLK; -+#endif -+} -+ -+ -+/******************************************************************************* -+* mvBoardPexBridgeIntPinGet - Get PEX to PCI bridge interrupt pin number -+* -+* DESCRIPTION: -+* Multi-ported PCI Express bridges that is implemented on the board -+* collapse interrupts across multiple conventional PCI/PCI-X buses. -+* A dual-headed PCI Express bridge would map (or "swizzle") the -+* interrupts per the following table (in accordance with the respective -+* logical PCI/PCI-X bridge's Device Number), collapse the INTA#-INTD# -+* signals from its two logical PCI/PCI-X bridges, collapse the -+* INTA#-INTD# signals from any internal sources, and convert the -+* signals to in-band PCI Express messages. 10 -+* This function returns the upstream interrupt as it was converted by -+* the bridge, according to board configuration and the following table: -+* PCI dev num -+* Interrupt pin 7, 8, 9 -+* A -> A D C -+* B -> B A D -+* C -> C B A -+* D -> D C B -+* -+* -+* INPUT: -+* devNum - PCI/PCIX device number. -+* intPin - PCI Int pin -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Int pin connected to the Interrupt controller -+* -+*******************************************************************************/ -+MV_U32 mvBoardPexBridgeIntPinGet(MV_U32 devNum, MV_U32 intPin) -+{ -+ MV_U32 realIntPin = ((intPin + (3 - (devNum % 4))) %4 ); -+ -+ if (realIntPin == 0) return 4; -+ else return realIntPin; -+ -+} -+ -+/******************************************************************************* -+* mvBoardDebugLedNumGet - Get number of debug Leds -+* -+* DESCRIPTION: -+* INPUT: -+* boardId -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_U32 mvBoardDebugLedNumGet(MV_U32 boardId) -+{ -+ return BOARD_INFO(boardId)->activeLedsNumber; -+} -+ -+/******************************************************************************* -+* mvBoardDebugLeg - Set the board debug Leds -+* -+* DESCRIPTION: turn on/off status leds. -+* Note: assume MPP leds are part of group 0 only. -+* -+* INPUT: -+* hexNum - Number to be displied in hex by Leds. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvBoardDebugLed(MV_U32 hexNum) -+{ -+ MV_U32 val = 0,totalMask, currentBitMask = 1,i; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (BOARD_INFO(boardId)->pLedGppPin == NULL) -+ return; -+ -+ totalMask = (1 << BOARD_INFO(boardId)->activeLedsNumber) -1; -+ hexNum &= totalMask; -+ totalMask = 0; -+ -+ for (i = 0 ; i < BOARD_INFO(boardId)->activeLedsNumber ; i++) -+ { -+ if (hexNum & currentBitMask) -+ { -+ val |= (1 << BOARD_INFO(boardId)->pLedGppPin[i]); -+ } -+ -+ totalMask |= (1 << BOARD_INFO(boardId)->pLedGppPin[i]); -+ -+ currentBitMask = (currentBitMask << 1); -+ } -+ -+ if (BOARD_INFO(boardId)->ledsPolarity) -+ { -+ mvGppValueSet(0, totalMask, val); -+ } -+ else -+ { -+ mvGppValueSet(0, totalMask, ~val); -+ } -+} -+ -+ -+/******************************************************************************* -+* mvBoarGpioPinGet - mvBoarGpioPinGet -+* -+* DESCRIPTION: -+* -+* INPUT: -+* class - MV_BOARD_GPP_CLASS enum. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* GPIO pin number. The function return -1 for bad parameters. -+* -+*******************************************************************************/ -+MV_32 mvBoarGpioPinNumGet(MV_BOARD_GPP_CLASS class, MV_U32 index) -+{ -+ MV_U32 boardId, i; -+ MV_U32 indexFound = 0; -+ -+ boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardRTCGpioPinGet:Board unknown.\n"); -+ return MV_ERROR; -+ -+ } -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardGppInfo; i++) -+ if (BOARD_INFO(boardId)->pBoardGppInfo[i].devClass == class) { -+ if (indexFound == index) -+ return (MV_U32)BOARD_INFO(boardId)->pBoardGppInfo[i].gppPinNum; -+ else -+ indexFound++; -+ -+ } -+ -+ return MV_ERROR; -+} -+ -+ -+/******************************************************************************* -+* mvBoardRTCGpioPinGet - mvBoardRTCGpioPinGet -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* GPIO pin number. The function return -1 for bad parameters. -+* -+*******************************************************************************/ -+MV_32 mvBoardRTCGpioPinGet(MV_VOID) -+{ -+ return mvBoarGpioPinNumGet(BOARD_GPP_RTC, 0); -+} -+ -+ -+/******************************************************************************* -+* mvBoardReset - mvBoardReset -+* -+* DESCRIPTION: -+* Reset the board -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None -+* -+*******************************************************************************/ -+MV_VOID mvBoardReset(MV_VOID) -+{ -+ MV_32 resetPin; -+ -+ /* Get gpp reset pin if define */ -+ resetPin = mvBoardResetGpioPinGet(); -+ if (resetPin != MV_ERROR) -+ { -+ MV_REG_BIT_RESET( GPP_DATA_OUT_REG(0) ,(1 << resetPin)); -+ MV_REG_BIT_RESET( GPP_DATA_OUT_EN_REG(0) ,(1 << resetPin)); -+ -+ } -+ else -+ { -+ /* No gpp reset pin was found, try to reset ussing -+ system reset out */ -+ MV_REG_BIT_SET( CPU_RSTOUTN_MASK_REG , BIT2); -+ MV_REG_BIT_SET( CPU_SYS_SOFT_RST_REG , BIT0); -+ } -+} -+ -+/******************************************************************************* -+* mvBoardResetGpioPinGet - mvBoardResetGpioPinGet -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* GPIO pin number. The function return -1 for bad parameters. -+* -+*******************************************************************************/ -+MV_32 mvBoardResetGpioPinGet(MV_VOID) -+{ -+ return mvBoarGpioPinNumGet(BOARD_GPP_RESET, 0); -+} -+/******************************************************************************* -+* mvBoardSDIOGpioPinGet - mvBoardSDIOGpioPinGet -+* -+* DESCRIPTION: -+* used for hotswap detection -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* GPIO pin number. The function return -1 for bad parameters. -+* -+*******************************************************************************/ -+MV_32 mvBoardSDIOGpioPinGet(MV_VOID) -+{ -+ return mvBoarGpioPinNumGet(BOARD_GPP_SDIO_DETECT, 0); -+} -+ -+/******************************************************************************* -+* mvBoardUSBVbusGpioPinGet - return Vbus input GPP -+* -+* DESCRIPTION: -+* -+* INPUT: -+* int devNo. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* GPIO pin number. The function return -1 for bad parameters. -+* -+*******************************************************************************/ -+MV_32 mvBoardUSBVbusGpioPinGet(MV_32 devId) -+{ -+ return mvBoarGpioPinNumGet(BOARD_GPP_USB_VBUS, devId); -+} -+ -+/******************************************************************************* -+* mvBoardUSBVbusEnGpioPinGet - return Vbus Enable output GPP -+* -+* DESCRIPTION: -+* -+* INPUT: -+* int devNo. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* GPIO pin number. The function return -1 for bad parameters. -+* -+*******************************************************************************/ -+MV_32 mvBoardUSBVbusEnGpioPinGet(MV_32 devId) -+{ -+ return mvBoarGpioPinNumGet(BOARD_GPP_USB_VBUS_EN, devId); -+} -+ -+ -+/******************************************************************************* -+* mvBoardGpioIntMaskGet - Get GPIO mask for interrupt pins -+* -+* DESCRIPTION: -+* This function returns a 32-bit mask of GPP pins that connected to -+* interrupt generating sources on board. -+* For example if UART channel A is hardwired to GPP pin 8 and -+* UART channel B is hardwired to GPP pin 4 the fuinction will return -+* the value 0x000000110 -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* See description. The function return -1 if board is not identified. -+* -+*******************************************************************************/ -+MV_32 mvBoardGpioIntMaskLowGet(MV_VOID) -+{ -+ MV_U32 boardId; -+ -+ boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardGpioIntMaskGet:Board unknown.\n"); -+ return MV_ERROR; -+ -+ } -+ -+ return BOARD_INFO(boardId)->intsGppMaskLow; -+} -+MV_32 mvBoardGpioIntMaskHighGet(MV_VOID) -+{ -+ MV_U32 boardId; -+ -+ boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardGpioIntMaskGet:Board unknown.\n"); -+ return MV_ERROR; -+ -+ } -+ -+ return BOARD_INFO(boardId)->intsGppMaskHigh; -+} -+ -+ -+/******************************************************************************* -+* mvBoardMppGet - Get board dependent MPP register value -+* -+* DESCRIPTION: -+* MPP settings are derived from board design. -+* MPP group consist of 8 MPPs. An MPP group represent MPP -+* control register. -+* This function retrieves board dependend MPP register value. -+* -+* INPUT: -+* mppGroupNum - MPP group number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit value describing MPP control register value. -+* -+*******************************************************************************/ -+MV_32 mvBoardMppGet(MV_U32 mppGroupNum) -+{ -+ MV_U32 boardId; -+ -+ boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardMppGet:Board unknown.\n"); -+ return MV_ERROR; -+ -+ } -+ -+ return BOARD_INFO(boardId)->pBoardMppConfigValue[0].mppGroup[mppGroupNum]; -+} -+ -+ -+/******************************************************************************* -+* mvBoardMppGroupId - If MPP group type is AUTO then identify it using twsi -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_VOID mvBoardMppGroupIdUpdate(MV_VOID) -+{ -+ -+ MV_BOARD_MPP_GROUP_CLASS devClass; -+ MV_BOARD_MODULE_ID_CLASS devClassId; -+ MV_BOARD_MPP_TYPE_CLASS mppGroupType; -+ MV_U32 devId; -+ MV_U32 maxMppGrp = 1; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ maxMppGrp = MV_6281_MPP_MAX_MODULE; -+ break; -+ case MV_6192_DEV_ID: -+ maxMppGrp = MV_6192_MPP_MAX_MODULE; -+ break; -+ case MV_6190_DEV_ID: -+ maxMppGrp = MV_6190_MPP_MAX_MODULE; -+ break; -+ case MV_6180_DEV_ID: -+ maxMppGrp = MV_6180_MPP_MAX_MODULE; -+ break; -+ } -+ -+ for (devClass = 0; devClass < maxMppGrp; devClass++) -+ { -+ /* If MPP group can be defined by the module connected to it */ -+ if (mvBoardMppGroupTypeGet(devClass) == MV_BOARD_AUTO) -+ { -+ /* Get MPP module ID */ -+ devClassId = mvBoarModuleTypeGet(devClass); -+ if (MV_ERROR != devClassId) -+ { -+ switch(devClassId) -+ { -+ case MV_BOARD_MODULE_TDM_ID: -+ case MV_BOARD_MODULE_TDM_5CHAN_ID: -+ mppGroupType = MV_BOARD_TDM; -+ break; -+ case MV_BOARD_MODULE_AUDIO_ID: -+ mppGroupType = MV_BOARD_AUDIO; -+ break; -+ case MV_BOARD_MODULE_RGMII_ID: -+ mppGroupType = MV_BOARD_RGMII; -+ break; -+ case MV_BOARD_MODULE_GMII_ID: -+ mppGroupType = MV_BOARD_GMII; -+ break; -+ case MV_BOARD_MODULE_TS_ID: -+ mppGroupType = MV_BOARD_TS; -+ break; -+ case MV_BOARD_MODULE_MII_ID: -+ mppGroupType = MV_BOARD_MII; -+ break; -+ default: -+ mppGroupType = MV_BOARD_OTHER; -+ break; -+ } -+ } -+ else -+ /* The module bay is empty */ -+ mppGroupType = MV_BOARD_OTHER; -+ -+ /* Update MPP group type */ -+ mvBoardMppGroupTypeSet(devClass, mppGroupType); -+ } -+ -+ /* Update MPP output voltage for RGMII 1.8V. Set port to GMII for GMII module */ -+ if ((mvBoardMppGroupTypeGet(devClass) == MV_BOARD_RGMII)) -+ MV_REG_BIT_SET(MPP_OUTPUT_DRIVE_REG,MPP_1_8_RGMII1_OUTPUT_DRIVE | MPP_1_8_RGMII0_OUTPUT_DRIVE); -+ else -+ { -+ if ((mvBoardMppGroupTypeGet(devClass) == MV_BOARD_GMII)) -+ { -+ MV_REG_BIT_RESET(MPP_OUTPUT_DRIVE_REG, BIT7 | BIT15); -+ MV_REG_BIT_RESET(ETH_PORT_SERIAL_CTRL_1_REG(0),BIT3); -+ MV_REG_BIT_RESET(ETH_PORT_SERIAL_CTRL_1_REG(1),BIT3); -+ } -+ else if ((mvBoardMppGroupTypeGet(devClass) == MV_BOARD_MII)) -+ { -+ /* Assumption that the MDC & MDIO should be 3.3V */ -+ MV_REG_BIT_RESET(MPP_OUTPUT_DRIVE_REG, BIT7 | BIT15); -+ /* Assumption that only ETH1 can be MII when using modules on DB */ -+ MV_REG_BIT_RESET(ETH_PORT_SERIAL_CTRL_1_REG(1),BIT3); -+ } -+ } -+ } -+} -+ -+/******************************************************************************* -+* mvBoardMppGroupTypeGet -+* -+* DESCRIPTION: -+* -+* INPUT: -+* mppGroupClass - MPP group number 0 for MPP[35:20] or 1 for MPP[49:36]. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_BOARD_MPP_TYPE_CLASS mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass) -+{ -+ MV_U32 boardId; -+ -+ boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardMppGet:Board unknown.\n"); -+ return MV_ERROR; -+ -+ } -+ -+ if (mppGroupClass == MV_BOARD_MPP_GROUP_1) -+ return BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup1; -+ else -+ return BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup2; -+} -+ -+/******************************************************************************* -+* mvBoardMppGroupTypeSet -+* -+* DESCRIPTION: -+* -+* INPUT: -+* mppGroupClass - MPP group number 0 for MPP[35:20] or 1 for MPP[49:36]. -+* mppGroupType - MPP group type for MPP[35:20] or for MPP[49:36]. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_VOID mvBoardMppGroupTypeSet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass, -+ MV_BOARD_MPP_TYPE_CLASS mppGroupType) -+{ -+ MV_U32 boardId; -+ -+ boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardMppGet:Board unknown.\n"); -+ } -+ -+ if (mppGroupClass == MV_BOARD_MPP_GROUP_1) -+ BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup1 = mppGroupType; -+ else -+ BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup2 = mppGroupType; -+ -+} -+ -+/******************************************************************************* -+* mvBoardMppMuxSet - Update MPP mux -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_VOID mvBoardMppMuxSet(MV_VOID) -+{ -+ -+ MV_BOARD_MPP_GROUP_CLASS devClass; -+ MV_BOARD_MPP_TYPE_CLASS mppGroupType; -+ MV_U32 devId; -+ MV_U8 muxVal = 0xf; -+ MV_U32 maxMppGrp = 1; -+ MV_TWSI_SLAVE twsiSlave; -+ MV_TWSI_ADDR slave; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ maxMppGrp = MV_6281_MPP_MAX_MODULE; -+ break; -+ case MV_6192_DEV_ID: -+ maxMppGrp = MV_6192_MPP_MAX_MODULE; -+ break; -+ case MV_6190_DEV_ID: -+ maxMppGrp = MV_6190_MPP_MAX_MODULE; -+ break; -+ case MV_6180_DEV_ID: -+ maxMppGrp = MV_6180_MPP_MAX_MODULE; -+ break; -+ } -+ -+ for (devClass = 0; devClass < maxMppGrp; devClass++) -+ { -+ mppGroupType = mvBoardMppGroupTypeGet(devClass); -+ -+ switch(mppGroupType) -+ { -+ case MV_BOARD_TDM: -+ muxVal &= ~(devClass ? (0x2 << (devClass * 2)):0x0); -+ break; -+ case MV_BOARD_AUDIO: -+ muxVal &= ~(devClass ? 0x7 : 0x0); /*old Z0 value 0xd:0x0*/ -+ break; -+ case MV_BOARD_TS: -+ muxVal &= ~(devClass ? (0x2 << (devClass * 2)):0x0); -+ break; -+ default: -+ muxVal |= (devClass ? 0xf : 0); -+ break; -+ } -+ } -+ -+ /* TWSI init */ -+ slave.type = ADDR7_BIT; -+ slave.address = 0; -+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); -+ -+ /* Read MPP module ID */ -+ DB(mvOsPrintf("Board: twsi exp set\n")); -+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(MV_BOARD_MUX_I2C_ADDR_ENTRY); -+ twsiSlave.slaveAddr.type = mvBoardTwsiExpAddrTypeGet(MV_BOARD_MUX_I2C_ADDR_ENTRY); -+ twsiSlave.validOffset = MV_TRUE; -+ /* Offset is the first command after the address which indicate the register number to be read -+ in next operation */ -+ twsiSlave.offset = 2; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ -+ -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) -+ { -+ DB(mvOsPrintf("Board: twsi exp out val fail\n")); -+ return; -+ } -+ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); -+ -+ /* Change twsi exp to output */ -+ twsiSlave.offset = 6; -+ muxVal = 0; -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) -+ { -+ DB(mvOsPrintf("Board: twsi exp change to out fail\n")); -+ return; -+ } -+ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); -+ -+} -+ -+/******************************************************************************* -+* mvBoardTdmMppSet - set MPPs in TDM module -+* -+* DESCRIPTION: -+* -+* INPUT: type of second telephony device -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_VOID mvBoardTdmMppSet(MV_32 chType) -+{ -+ -+ MV_BOARD_MPP_GROUP_CLASS devClass; -+ MV_BOARD_MPP_TYPE_CLASS mppGroupType; -+ MV_U32 devId; -+ MV_U8 muxVal = 1; -+ MV_U8 muxValMask = 1; -+ MV_U8 twsiVal; -+ MV_U32 maxMppGrp = 1; -+ MV_TWSI_SLAVE twsiSlave; -+ MV_TWSI_ADDR slave; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ maxMppGrp = MV_6281_MPP_MAX_MODULE; -+ break; -+ case MV_6192_DEV_ID: -+ maxMppGrp = MV_6192_MPP_MAX_MODULE; -+ break; -+ case MV_6190_DEV_ID: -+ maxMppGrp = MV_6190_MPP_MAX_MODULE; -+ break; -+ case MV_6180_DEV_ID: -+ maxMppGrp = MV_6180_MPP_MAX_MODULE; -+ break; -+ } -+ -+ for (devClass = 0; devClass < maxMppGrp; devClass++) -+ { -+ mppGroupType = mvBoardMppGroupTypeGet(devClass); -+ if(mppGroupType == MV_BOARD_TDM) -+ break; -+ } -+ -+ if(devClass == maxMppGrp) -+ return; /* TDM module not found */ -+ -+ /* TWSI init */ -+ slave.type = ADDR7_BIT; -+ slave.address = 0; -+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); -+ -+ /* Read MPP module ID */ -+ DB(mvOsPrintf("Board: twsi exp set\n")); -+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(devClass); -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ /* Offset is the first command after the address which indicate the register number to be read -+ in next operation */ -+ twsiSlave.offset = 3; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ if(mvBoardIdGet() == RD_88F6281A_ID) -+ { -+ muxVal = 0xc; -+ muxValMask = 0xf3; -+ } -+ -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ muxVal = (twsiVal & muxValMask) | muxVal; -+ -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) -+ { -+ mvOsPrintf("Board: twsi exp out val fail\n"); -+ return; -+ } -+ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); -+ -+ /* Change twsi exp to output */ -+ twsiSlave.offset = 7; -+ muxVal = 0xfe; -+ if(mvBoardIdGet() == RD_88F6281A_ID) -+ muxVal = 0xf3; -+ -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ muxVal = (twsiVal & muxVal); -+ -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) -+ { -+ mvOsPrintf("Board: twsi exp change to out fail\n"); -+ return; -+ } -+ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); -+ /* reset the line to 0 */ -+ twsiSlave.offset = 3; -+ muxVal = 0; -+ muxValMask = 1; -+ -+ if(mvBoardIdGet() == RD_88F6281A_ID) { -+ muxVal = 0x0; -+ muxValMask = 0xf3; -+ } -+ -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ muxVal = (twsiVal & muxValMask) | muxVal; -+ -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) -+ { -+ mvOsPrintf("Board: twsi exp out val fail\n"); -+ return; -+ } -+ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); -+ -+ mvOsDelay(20); -+ -+ /* set the line to 1 */ -+ twsiSlave.offset = 3; -+ muxVal = 1; -+ muxValMask = 1; -+ -+ if(mvBoardIdGet() == RD_88F6281A_ID) -+ { -+ muxVal = 0xc; -+ muxValMask = 0xf3; -+ if(chType) /* FXS - issue reset properly */ -+ { -+ MV_REG_BIT_SET(GPP_DATA_OUT_REG(1), MV_GPP12); -+ mvOsDelay(50); -+ MV_REG_BIT_RESET(GPP_DATA_OUT_REG(1), MV_GPP12); -+ } -+ else /* FXO - issue reset via TDM_CODEC_RST*/ -+ { -+ /* change MPP44 type to TDM_CODEC_RST(0x2) */ -+ MV_REG_WRITE(MPP_CONTROL_REG5, ((MV_REG_READ(MPP_CONTROL_REG5) & 0xFFF0FFFF) | BIT17)); -+ } -+ } -+ -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ muxVal = (twsiVal & muxValMask) | muxVal; -+ -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) -+ { -+ mvOsPrintf("Board: twsi exp out val fail\n"); -+ return; -+ } -+ -+ /* TBD - 5 channels */ -+#if defined(MV_TDM_5CHANNELS) -+ /* change MPP38 type to GPIO(0x0) & polarity for TDM_STROBE */ -+ MV_REG_WRITE(MPP_CONTROL_REG4, (MV_REG_READ(MPP_CONTROL_REG4) & 0xF0FFFFFF)); -+ mvGppPolaritySet(1, MV_GPP6, 0); -+ -+ twsiSlave.offset = 6; -+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(2); -+ -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ muxVal = (twsiVal & ~BIT2); -+ -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) -+ { -+ mvOsPrintf("Board: twsi exp change to out fail\n"); -+ return; -+ } -+ -+ -+ twsiSlave.offset = 2; -+ -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ muxVal = (twsiVal & ~BIT2); -+ -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) -+ { -+ mvOsPrintf("Board: twsi exp change to out fail\n"); -+ return; -+ } -+#endif -+ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); -+ -+ -+} -+/******************************************************************************* -+* mvBoardVoiceConnModeGet - return SLIC/DAA connection & interrupt modes -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+ -+MV_VOID mvBoardVoiceConnModeGet(MV_32* connMode, MV_32* irqMode) -+{ -+ switch(mvBoardIdGet()) -+ { -+ case RD_88F6281A_ID: -+ *connMode = DAISY_CHAIN_MODE; -+ *irqMode = INTERRUPT_TO_TDM; -+ break; -+ case DB_88F6281A_BP_ID: -+ *connMode = DUAL_CHIP_SELECT_MODE; -+ *irqMode = INTERRUPT_TO_TDM; -+ break; -+ case RD_88F6192A_ID: -+ *connMode = DUAL_CHIP_SELECT_MODE; -+ *irqMode = INTERRUPT_TO_TDM; -+ break; -+ case DB_88F6192A_BP_ID: -+ *connMode = DUAL_CHIP_SELECT_MODE; -+ *irqMode = INTERRUPT_TO_TDM; -+ break; -+ default: -+ *connMode = *irqMode = -1; -+ mvOsPrintf("mvBoardVoiceAssembleModeGet: TDM not supported(boardId=0x%x)\n",mvBoardIdGet()); -+ } -+ return; -+ -+} -+ -+/******************************************************************************* -+* mvBoardMppModuleTypePrint - print module detect -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_VOID mvBoardMppModuleTypePrint(MV_VOID) -+{ -+ -+ MV_BOARD_MPP_GROUP_CLASS devClass; -+ MV_BOARD_MPP_TYPE_CLASS mppGroupType; -+ MV_U32 devId; -+ MV_U32 maxMppGrp = 1; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ maxMppGrp = MV_6281_MPP_MAX_MODULE; -+ break; -+ case MV_6192_DEV_ID: -+ maxMppGrp = MV_6192_MPP_MAX_MODULE; -+ break; -+ case MV_6190_DEV_ID: -+ maxMppGrp = MV_6190_MPP_MAX_MODULE; -+ break; -+ case MV_6180_DEV_ID: -+ maxMppGrp = MV_6180_MPP_MAX_MODULE; -+ break; -+ } -+ -+ for (devClass = 0; devClass < maxMppGrp; devClass++) -+ { -+ mppGroupType = mvBoardMppGroupTypeGet(devClass); -+ -+ switch(mppGroupType) -+ { -+ case MV_BOARD_TDM: -+ if(devId != MV_6190_DEV_ID) -+ mvOsPrintf("Module %d is TDM\n", devClass); -+ break; -+ case MV_BOARD_AUDIO: -+ if(devId != MV_6190_DEV_ID) -+ mvOsPrintf("Module %d is AUDIO\n", devClass); -+ break; -+ case MV_BOARD_RGMII: -+ if(devId != MV_6190_DEV_ID) -+ mvOsPrintf("Module %d is RGMII\n", devClass); -+ break; -+ case MV_BOARD_GMII: -+ if(devId != MV_6190_DEV_ID) -+ mvOsPrintf("Module %d is GMII\n", devClass); -+ break; -+ case MV_BOARD_TS: -+ if(devId != MV_6190_DEV_ID) -+ mvOsPrintf("Module %d is TS\n", devClass); -+ break; -+ default: -+ break; -+ } -+ } -+} -+ -+/* Board devices API managments */ -+ -+/******************************************************************************* -+* mvBoardGetDeviceNumber - Get number of device of some type on the board -+* -+* DESCRIPTION: -+* -+* INPUT: -+* devType - The device type ( Flash,RTC , etc .. ) -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* If the device is found on the board the then the functions returns the -+* number of those devices else the function returns 0 -+* -+* -+*******************************************************************************/ -+MV_32 mvBoardGetDevicesNumber(MV_BOARD_DEV_CLASS devClass) -+{ -+ MV_U32 foundIndex=0,devNum; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardGetDeviceNumber:Board unknown.\n"); -+ return 0xFFFFFFFF; -+ -+ } -+ -+ for (devNum = START_DEV_CS; devNum < BOARD_INFO(boardId)->numBoardDeviceIf; devNum++) -+ { -+ if (BOARD_INFO(boardId)->pDevCsInfo[devNum].devClass == devClass) -+ { -+ foundIndex++; -+ } -+ } -+ -+ return foundIndex; -+ -+} -+ -+/******************************************************************************* -+* mvBoardGetDeviceBaseAddr - Get base address of a device existing on the board -+* -+* DESCRIPTION: -+* -+* INPUT: -+* devIndex - The device sequential number on the board -+* devType - The device type ( Flash,RTC , etc .. ) -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* If the device is found on the board the then the functions returns the -+* Base address else the function returns 0xffffffff -+* -+* -+*******************************************************************************/ -+MV_32 mvBoardGetDeviceBaseAddr(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) -+{ -+ MV_DEV_CS_INFO* devEntry; -+ devEntry = boardGetDevEntry(devNum,devClass); -+ if (devEntry != NULL) -+ { -+ return mvCpuIfTargetWinBaseLowGet(DEV_TO_TARGET(devEntry->deviceCS)); -+ -+ } -+ -+ return 0xFFFFFFFF; -+} -+ -+/******************************************************************************* -+* mvBoardGetDeviceBusWidth - Get Bus width of a device existing on the board -+* -+* DESCRIPTION: -+* -+* INPUT: -+* devIndex - The device sequential number on the board -+* devType - The device type ( Flash,RTC , etc .. ) -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* If the device is found on the board the then the functions returns the -+* Bus width else the function returns 0xffffffff -+* -+* -+*******************************************************************************/ -+MV_32 mvBoardGetDeviceBusWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) -+{ -+ MV_DEV_CS_INFO* devEntry; -+ -+ devEntry = boardGetDevEntry(devNum,devClass); -+ if (devEntry != NULL) -+ { -+ return 8; -+ } -+ -+ return 0xFFFFFFFF; -+ -+} -+ -+/******************************************************************************* -+* mvBoardGetDeviceWidth - Get dev width of a device existing on the board -+* -+* DESCRIPTION: -+* -+* INPUT: -+* devIndex - The device sequential number on the board -+* devType - The device type ( Flash,RTC , etc .. ) -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* If the device is found on the board the then the functions returns the -+* dev width else the function returns 0xffffffff -+* -+* -+*******************************************************************************/ -+MV_32 mvBoardGetDeviceWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) -+{ -+ MV_DEV_CS_INFO* devEntry; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("Board unknown.\n"); -+ return 0xFFFFFFFF; -+ } -+ -+ devEntry = boardGetDevEntry(devNum,devClass); -+ if (devEntry != NULL) -+ return devEntry->devWidth; -+ -+ return MV_ERROR; -+ -+} -+ -+/******************************************************************************* -+* mvBoardGetDeviceWinSize - Get the window size of a device existing on the board -+* -+* DESCRIPTION: -+* -+* INPUT: -+* devIndex - The device sequential number on the board -+* devType - The device type ( Flash,RTC , etc .. ) -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* If the device is found on the board the then the functions returns the -+* window size else the function returns 0xffffffff -+* -+* -+*******************************************************************************/ -+MV_32 mvBoardGetDeviceWinSize(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) -+{ -+ MV_DEV_CS_INFO* devEntry; -+ MV_U32 boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("Board unknown.\n"); -+ return 0xFFFFFFFF; -+ } -+ -+ devEntry = boardGetDevEntry(devNum,devClass); -+ if (devEntry != NULL) -+ { -+ return mvCpuIfTargetWinSizeGet(DEV_TO_TARGET(devEntry->deviceCS)); -+ } -+ -+ return 0xFFFFFFFF; -+} -+ -+ -+/******************************************************************************* -+* boardGetDevEntry - returns the entry pointer of a device on the board -+* -+* DESCRIPTION: -+* -+* INPUT: -+* devIndex - The device sequential number on the board -+* devType - The device type ( Flash,RTC , etc .. ) -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* If the device is found on the board the then the functions returns the -+* dev number else the function returns 0x0 -+* -+* -+*******************************************************************************/ -+static MV_DEV_CS_INFO* boardGetDevEntry(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) -+{ -+ MV_U32 foundIndex=0,devIndex; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("boardGetDevEntry: Board unknown.\n"); -+ return NULL; -+ -+ } -+ -+ for (devIndex = START_DEV_CS; devIndex < BOARD_INFO(boardId)->numBoardDeviceIf; devIndex++) -+ { -+ /* TBR */ -+ /*if (BOARD_INFO(boardId)->pDevCsInfo[devIndex].deviceCS == MV_BOOTDEVICE_INDEX) -+ continue;*/ -+ -+ if (BOARD_INFO(boardId)->pDevCsInfo[devIndex].devClass == devClass) -+ { -+ if (foundIndex == devNum) -+ { -+ return &(BOARD_INFO(boardId)->pDevCsInfo[devIndex]); -+ } -+ foundIndex++; -+ } -+ } -+ -+ /* device not found */ -+ return NULL; -+} -+ -+/* Get device CS number */ -+ -+MV_U32 boardGetDevCSNum(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) -+{ -+ MV_DEV_CS_INFO* devEntry; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("Board unknown.\n"); -+ return 0xFFFFFFFF; -+ -+ } -+ -+ -+ devEntry = boardGetDevEntry(devNum,devClass); -+ if (devEntry != NULL) -+ return devEntry->deviceCS; -+ -+ return 0xFFFFFFFF; -+ -+} -+ -+/******************************************************************************* -+* mvBoardRtcTwsiAddrTypeGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_U8 mvBoardRtcTwsiAddrTypeGet() -+{ -+ int i; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) -+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_RTC) -+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; -+ return (MV_ERROR); -+} -+ -+/******************************************************************************* -+* mvBoardRtcTwsiAddrGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_U8 mvBoardRtcTwsiAddrGet() -+{ -+ int i; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) -+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_RTC) -+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; -+ return (0xFF); -+} -+ -+/******************************************************************************* -+* mvBoardA2DTwsiAddrTypeGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_U8 mvBoardA2DTwsiAddrTypeGet() -+{ -+ int i; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) -+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_AUDIO_DEC) -+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; -+ return (MV_ERROR); -+} -+ -+/******************************************************************************* -+* mvBoardA2DTwsiAddrGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_U8 mvBoardA2DTwsiAddrGet() -+{ -+ int i; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) -+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_AUDIO_DEC) -+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; -+ return (0xFF); -+} -+ -+/******************************************************************************* -+* mvBoardTwsiExpAddrTypeGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_U8 mvBoardTwsiExpAddrTypeGet(MV_U32 index) -+{ -+ int i; -+ MV_U32 indexFound = 0; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) -+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_EXP) -+ { -+ if (indexFound == index) -+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; -+ else -+ indexFound++; -+ } -+ -+ return (MV_ERROR); -+} -+ -+/******************************************************************************* -+* mvBoardTwsiExpAddrGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_U8 mvBoardTwsiExpAddrGet(MV_U32 index) -+{ -+ int i; -+ MV_U32 indexFound = 0; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) -+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_EXP) -+ { -+ if (indexFound == index) -+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; -+ else -+ indexFound++; -+ } -+ -+ return (0xFF); -+} -+ -+ -+/******************************************************************************* -+* mvBoardTwsiSatRAddrTypeGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_U8 mvBoardTwsiSatRAddrTypeGet(MV_U32 index) -+{ -+ int i; -+ MV_U32 indexFound = 0; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) -+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_SATR) -+ { -+ if (indexFound == index) -+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; -+ else -+ indexFound++; -+ } -+ -+ return (MV_ERROR); -+} -+ -+/******************************************************************************* -+* mvBoardTwsiSatRAddrGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_U8 mvBoardTwsiSatRAddrGet(MV_U32 index) -+{ -+ int i; -+ MV_U32 indexFound = 0; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) -+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_SATR) -+ { -+ if (indexFound == index) -+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; -+ else -+ indexFound++; -+ } -+ -+ return (0xFF); -+} -+ -+/******************************************************************************* -+* mvBoardNandWidthGet - -+* -+* DESCRIPTION: Get the width of the first NAND device in byte. -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: 1, 2, 4 or MV_ERROR -+* -+* -+*******************************************************************************/ -+/* */ -+MV_32 mvBoardNandWidthGet(void) -+{ -+ MV_U32 devNum; -+ MV_U32 devWidth; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (devNum = START_DEV_CS; devNum < BOARD_INFO(boardId)->numBoardDeviceIf; devNum++) -+ { -+ devWidth = mvBoardGetDeviceWidth(devNum, BOARD_DEV_NAND_FLASH); -+ if (devWidth != MV_ERROR) -+ return (devWidth / 8); -+ } -+ -+ /* NAND wasn't found */ -+ return MV_ERROR; -+} -+ -+MV_U32 gBoardId = -1; -+ -+/******************************************************************************* -+* mvBoardIdGet - Get Board model -+* -+* DESCRIPTION: -+* This function returns board ID. -+* Board ID is 32bit word constructed of board model (16bit) and -+* board revision (16bit) in the following way: 0xMMMMRRRR. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit board ID number, '-1' if board is undefined. -+* -+*******************************************************************************/ -+MV_U32 mvBoardIdGet(MV_VOID) -+{ -+ MV_U32 tmpBoardId = -1; -+ -+ if(gBoardId == -1) -+ { -+ #if defined(DB_88F6281A) -+ tmpBoardId = DB_88F6281A_BP_ID; -+ #elif defined(RD_88F6281A) -+ tmpBoardId = RD_88F6281A_ID; -+ #elif defined(DB_88F6192A) -+ tmpBoardId = DB_88F6192A_BP_ID; -+ #elif defined(DB_88F6190A) -+ tmpBoardId = DB_88F6190A_BP_ID; -+ #elif defined(RD_88F6192A) -+ tmpBoardId = RD_88F6192A_ID; -+ #elif defined(RD_88F6190A) -+ tmpBoardId = RD_88F6190A_ID; -+ #elif defined(DB_88F6180A) -+ tmpBoardId = DB_88F6180A_BP_ID; -+ #elif defined(RD_88F6281A_PCAC) -+ tmpBoardId = RD_88F6281A_PCAC_ID; -+ #elif defined(RD_88F6281A_SHEEVA_PLUG) -+ tmpBoardId = SHEEVA_PLUG_ID; -+ #elif defined(DB_CUSTOMER) -+ tmpBoardId = DB_CUSTOMER_ID; -+ #endif -+ gBoardId = tmpBoardId; -+ } -+ -+ return gBoardId; -+} -+ -+ -+/******************************************************************************* -+* mvBoarModuleTypeGet - mvBoarModuleTypeGet -+* -+* DESCRIPTION: -+* -+* INPUT: -+* group num - MV_BOARD_MPP_GROUP_CLASS enum -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* module num - MV_BOARD_MODULE_CLASS enum -+* -+*******************************************************************************/ -+MV_BOARD_MODULE_ID_CLASS mvBoarModuleTypeGet(MV_BOARD_MPP_GROUP_CLASS devClass) -+{ -+ MV_TWSI_SLAVE twsiSlave; -+ MV_TWSI_ADDR slave; -+ MV_U8 data; -+ -+ /* TWSI init */ -+ slave.type = ADDR7_BIT; -+ slave.address = 0; -+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); -+ -+ /* Read MPP module ID */ -+ DB(mvOsPrintf("Board: Read MPP module ID\n")); -+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(devClass); -+ twsiSlave.slaveAddr.type = mvBoardTwsiExpAddrTypeGet(devClass); -+ twsiSlave.validOffset = MV_TRUE; -+ /* Offset is the first command after the address which indicate the register number to be read -+ in next operation */ -+ twsiSlave.offset = 0; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ -+ -+ if( MV_OK != mvTwsiRead (0, &twsiSlave, &data, 1) ) -+ { -+ DB(mvOsPrintf("Board: Read MPP module ID fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: Read MPP module ID succeded\n")); -+ -+ return data; -+} -+ -+/******************************************************************************* -+* mvBoarTwsiSatRGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* device num - one of three devices -+* reg num - 0 or 1 -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* reg value -+* -+*******************************************************************************/ -+MV_U8 mvBoarTwsiSatRGet(MV_U8 devNum, MV_U8 regNum) -+{ -+ MV_TWSI_SLAVE twsiSlave; -+ MV_TWSI_ADDR slave; -+ MV_U8 data; -+ -+ /* TWSI init */ -+ slave.type = ADDR7_BIT; -+ slave.address = 0; -+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); -+ -+ /* Read MPP module ID */ -+ DB(mvOsPrintf("Board: Read S@R device read\n")); -+ twsiSlave.slaveAddr.address = mvBoardTwsiSatRAddrGet(devNum); -+ twsiSlave.slaveAddr.type = mvBoardTwsiSatRAddrTypeGet(devNum); -+ twsiSlave.validOffset = MV_TRUE; -+ /* Use offset as command */ -+ twsiSlave.offset = regNum; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ if( MV_OK != mvTwsiRead (0, &twsiSlave, &data, 1) ) -+ { -+ DB(mvOsPrintf("Board: Read S@R fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: Read S@R succeded\n")); -+ -+ return data; -+} -+ -+/******************************************************************************* -+* mvBoarTwsiSatRSet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* devNum - one of three devices -+* regNum - 0 or 1 -+* regVal - value -+* -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* reg value -+* -+*******************************************************************************/ -+MV_STATUS mvBoarTwsiSatRSet(MV_U8 devNum, MV_U8 regNum, MV_U8 regVal) -+{ -+ MV_TWSI_SLAVE twsiSlave; -+ MV_TWSI_ADDR slave; -+ -+ /* TWSI init */ -+ slave.type = ADDR7_BIT; -+ slave.address = 0; -+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); -+ -+ /* Read MPP module ID */ -+ twsiSlave.slaveAddr.address = mvBoardTwsiSatRAddrGet(devNum); -+ twsiSlave.slaveAddr.type = mvBoardTwsiSatRAddrTypeGet(devNum); -+ twsiSlave.validOffset = MV_TRUE; -+ DB(mvOsPrintf("Board: Write S@R device addr %x, type %x, data %x\n", twsiSlave.slaveAddr.address,\ -+ twsiSlave.slaveAddr.type, regVal)); -+ /* Use offset as command */ -+ twsiSlave.offset = regNum; -+ twsiSlave.moreThen256 = MV_FALSE; -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, ®Val, 1) ) -+ { -+ DB(mvOsPrintf("Board: Write S@R fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: Write S@R succeded\n")); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvBoardSlicGpioPinGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_32 mvBoardSlicGpioPinGet(MV_U32 slicNum) -+{ -+ MV_U32 boardId; -+ boardId = mvBoardIdGet(); -+ -+ switch (boardId) -+ { -+ case DB_88F6281A_BP_ID: -+ case RD_88F6281A_ID: -+ default: -+ return MV_ERROR; -+ break; -+ -+ } -+} -+ -+/******************************************************************************* -+* mvBoardFanPowerControl - Turn on/off the fan power control on the RD-6281A -+* -+* DESCRIPTION: -+* -+* INPUT: -+* mode - MV_TRUE = on ; MV_FALSE = off -+* -+* OUTPUT: -+* MV_STATUS - MV_OK , MV_ERROR. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_STATUS mvBoardFanPowerControl(MV_BOOL mode) -+{ -+ -+ MV_U8 val = 1, twsiVal; -+ MV_TWSI_SLAVE twsiSlave; -+ MV_TWSI_ADDR slave; -+ -+ if(mvBoardIdGet() != RD_88F6281A_ID) -+ return MV_ERROR; -+ -+ /* TWSI init */ -+ slave.type = ADDR7_BIT; -+ slave.address = 0; -+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); -+ -+ /* Read MPP module ID */ -+ DB(mvOsPrintf("Board: twsi exp set\n")); -+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(1); -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ /* Offset is the first command after the address which indicate the register number to be read -+ in next operation */ -+ twsiSlave.offset = 3; -+ twsiSlave.moreThen256 = MV_FALSE; -+ if(mode == MV_TRUE) -+ val = 0x1; -+ else -+ val = 0; -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ val = (twsiVal & 0xfe) | val; -+ -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) -+ { -+ DB(mvOsPrintf("Board: twsi exp out val fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); -+ -+ /* Change twsi exp to output */ -+ twsiSlave.offset = 7; -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ val = (twsiVal & 0xfe); -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) -+ { -+ DB(mvOsPrintf("Board: twsi exp change to out fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvBoardHDDPowerControl - Turn on/off the HDD power control on the RD-6281A -+* -+* DESCRIPTION: -+* -+* INPUT: -+* mode - MV_TRUE = on ; MV_FALSE = off -+* -+* OUTPUT: -+* MV_STATUS - MV_OK , MV_ERROR. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_STATUS mvBoardHDDPowerControl(MV_BOOL mode) -+{ -+ -+ MV_U8 val = 1, twsiVal; -+ MV_TWSI_SLAVE twsiSlave; -+ MV_TWSI_ADDR slave; -+ -+ if(mvBoardIdGet() != RD_88F6281A_ID) -+ return MV_ERROR; -+ -+ /* TWSI init */ -+ slave.type = ADDR7_BIT; -+ slave.address = 0; -+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); -+ -+ /* Read MPP module ID */ -+ DB(mvOsPrintf("Board: twsi exp set\n")); -+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(1); -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ /* Offset is the first command after the address which indicate the register number to be read -+ in next operation */ -+ twsiSlave.offset = 3; -+ twsiSlave.moreThen256 = MV_FALSE; -+ if(mode == MV_TRUE) -+ val = 0x2; -+ else -+ val = 0; -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ val = (twsiVal & 0xfd) | val; -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) -+ { -+ DB(mvOsPrintf("Board: twsi exp out val fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); -+ -+ /* Change twsi exp to output */ -+ twsiSlave.offset = 7; -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ val = (twsiVal & 0xfd); -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) -+ { -+ DB(mvOsPrintf("Board: twsi exp change to out fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvBoardSDioWPControl - Turn on/off the SDIO WP on the RD-6281A -+* -+* DESCRIPTION: -+* -+* INPUT: -+* mode - MV_TRUE = on ; MV_FALSE = off -+* -+* OUTPUT: -+* MV_STATUS - MV_OK , MV_ERROR. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_STATUS mvBoardSDioWPControl(MV_BOOL mode) -+{ -+ -+ MV_U8 val = 1, twsiVal; -+ MV_TWSI_SLAVE twsiSlave; -+ MV_TWSI_ADDR slave; -+ -+ if(mvBoardIdGet() != RD_88F6281A_ID) -+ return MV_ERROR; -+ -+ /* TWSI init */ -+ slave.type = ADDR7_BIT; -+ slave.address = 0; -+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); -+ -+ /* Read MPP module ID */ -+ DB(mvOsPrintf("Board: twsi exp set\n")); -+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(0); -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ /* Offset is the first command after the address which indicate the register number to be read -+ in next operation */ -+ twsiSlave.offset = 3; -+ twsiSlave.moreThen256 = MV_FALSE; -+ if(mode == MV_TRUE) -+ val = 0x10; -+ else -+ val = 0; -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ val = (twsiVal & 0xef) | val; -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) -+ { -+ DB(mvOsPrintf("Board: twsi exp out val fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); -+ -+ /* Change twsi exp to output */ -+ twsiSlave.offset = 7; -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ val = (twsiVal & 0xef); -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) -+ { -+ DB(mvOsPrintf("Board: twsi exp change to out fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); -+ return MV_OK; -+} -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h 2010-11-09 20:28:07.362495449 +0100 -@@ -0,0 +1,376 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#ifndef __INCmvBoardEnvLibh -+#define __INCmvBoardEnvLibh -+ -+/* defines */ -+/* The below constant macros defines the board I2C EEPROM data offsets */ -+ -+ -+ -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "mvSysHwConfig.h" -+#include "boardEnv/mvBoardEnvSpec.h" -+ -+ -+/* DUART stuff for Tclk detection only */ -+#define DUART_BAUD_RATE 115200 -+#define MAX_CLOCK_MARGINE 5000000 /* Maximum detected clock margine */ -+ -+/* Voice devices assembly modes */ -+#define DAISY_CHAIN_MODE 1 -+#define DUAL_CHIP_SELECT_MODE 0 -+#define INTERRUPT_TO_MPP 1 -+#define INTERRUPT_TO_TDM 0 -+ -+ -+#define BOARD_ETH_PORT_NUM MV_ETH_MAX_PORTS -+#define BOARD_ETH_SWITCH_PORT_NUM 5 -+ -+#define MV_BOARD_MAX_USB_IF 1 -+#define MV_BOARD_MAX_MPP 7 -+#define MV_BOARD_NAME_LEN 0x20 -+ -+typedef struct _boardData -+{ -+ MV_U32 magic; -+ MV_U16 boardId; -+ MV_U8 boardVer; -+ MV_U8 boardRev; -+ MV_U32 reserved1; -+ MV_U32 reserved2; -+ -+}BOARD_DATA; -+ -+typedef enum _devBoardMppGroupClass -+{ -+ MV_BOARD_MPP_GROUP_1, -+ MV_BOARD_MPP_GROUP_2, -+ MV_BOARD_MAX_MPP_GROUP -+}MV_BOARD_MPP_GROUP_CLASS; -+ -+typedef enum _devBoardMppTypeClass -+{ -+ MV_BOARD_AUTO, -+ MV_BOARD_TDM, -+ MV_BOARD_AUDIO, -+ MV_BOARD_RGMII, -+ MV_BOARD_GMII, -+ MV_BOARD_TS, -+ MV_BOARD_MII, -+ MV_BOARD_OTHER -+}MV_BOARD_MPP_TYPE_CLASS; -+ -+typedef enum _devBoardModuleIdClass -+{ -+ MV_BOARD_MODULE_TDM_ID = 1, -+ MV_BOARD_MODULE_AUDIO_ID, -+ MV_BOARD_MODULE_RGMII_ID, -+ MV_BOARD_MODULE_GMII_ID, -+ MV_BOARD_MODULE_TS_ID, -+ MV_BOARD_MODULE_MII_ID, -+ MV_BOARD_MODULE_TDM_5CHAN_ID, -+ MV_BOARD_MODULE_OTHER_ID -+}MV_BOARD_MODULE_ID_CLASS; -+ -+typedef struct _boardMppTypeInfo -+{ -+ MV_BOARD_MPP_TYPE_CLASS boardMppGroup1; -+ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2; -+ -+}MV_BOARD_MPP_TYPE_INFO; -+ -+ -+typedef enum _devBoardClass -+{ -+ BOARD_DEV_NOR_FLASH, -+ BOARD_DEV_NAND_FLASH, -+ BOARD_DEV_SEVEN_SEG, -+ BOARD_DEV_FPGA, -+ BOARD_DEV_SRAM, -+ BOARD_DEV_SPI_FLASH, -+ BOARD_DEV_OTHER, -+}MV_BOARD_DEV_CLASS; -+ -+typedef enum _devTwsiBoardClass -+{ -+ BOARD_TWSI_RTC, -+ BOARD_DEV_TWSI_EXP, -+ BOARD_DEV_TWSI_SATR, -+ BOARD_TWSI_AUDIO_DEC, -+ BOARD_TWSI_OTHER -+}MV_BOARD_TWSI_CLASS; -+ -+typedef enum _devGppBoardClass -+{ -+ BOARD_GPP_RTC, -+ BOARD_GPP_MV_SWITCH, -+ BOARD_GPP_USB_VBUS, -+ BOARD_GPP_USB_VBUS_EN, -+ BOARD_GPP_USB_OC, -+ BOARD_GPP_USB_HOST_DEVICE, -+ BOARD_GPP_REF_CLCK, -+ BOARD_GPP_VOIP_SLIC, -+ BOARD_GPP_LIFELINE, -+ BOARD_GPP_BUTTON, -+ BOARD_GPP_TS_BUTTON_C, -+ BOARD_GPP_TS_BUTTON_U, -+ BOARD_GPP_TS_BUTTON_D, -+ BOARD_GPP_TS_BUTTON_L, -+ BOARD_GPP_TS_BUTTON_R, -+ BOARD_GPP_POWER_BUTTON, -+ BOARD_GPP_RESTOR_BUTTON, -+ BOARD_GPP_WPS_BUTTON, -+ BOARD_GPP_HDD0_POWER, -+ BOARD_GPP_HDD1_POWER, -+ BOARD_GPP_FAN_POWER, -+ BOARD_GPP_RESET, -+ BOARD_GPP_POWER_ON_LED, -+ BOARD_GPP_HDD_POWER, -+ BOARD_GPP_SDIO_POWER, -+ BOARD_GPP_SDIO_DETECT, -+ BOARD_GPP_SDIO_WP, -+ BOARD_GPP_SWITCH_PHY_INT, -+ BOARD_GPP_TSU_DIRCTION, -+ BOARD_GPP_OTHER -+}MV_BOARD_GPP_CLASS; -+ -+ -+typedef struct _devCsInfo -+{ -+ MV_U8 deviceCS; -+ MV_U32 params; -+ MV_U32 devClass; /* MV_BOARD_DEV_CLASS */ -+ MV_U8 devWidth; -+ -+}MV_DEV_CS_INFO; -+ -+ -+#define MV_BOARD_PHY_FORCE_10MB 0x0 -+#define MV_BOARD_PHY_FORCE_100MB 0x1 -+#define MV_BOARD_PHY_FORCE_1000MB 0x2 -+#define MV_BOARD_PHY_SPEED_AUTO 0x3 -+ -+typedef struct _boardSwitchInfo -+{ -+ MV_32 linkStatusIrq; -+ MV_32 qdPort[BOARD_ETH_SWITCH_PORT_NUM]; -+ MV_32 qdCpuPort; -+ MV_32 smiScanMode; /* 1 for SMI_MANUAL_MODE, 0 otherwise */ -+ MV_32 switchOnPort; -+ -+}MV_BOARD_SWITCH_INFO; -+ -+typedef struct _boardLedInfo -+{ -+ MV_U8 activeLedsNumber; -+ MV_U8 ledsPolarity; /* '0' or '1' to turn on led */ -+ MV_U8* gppPinNum; /* Pointer to GPP values */ -+ -+}MV_BOARD_LED_INFO; -+ -+typedef struct _boardGppInfo -+{ -+ MV_BOARD_GPP_CLASS devClass; -+ MV_U8 gppPinNum; -+ -+}MV_BOARD_GPP_INFO; -+ -+ -+typedef struct _boardTwsiInfo -+{ -+ MV_BOARD_TWSI_CLASS devClass; -+ MV_U8 twsiDevAddr; -+ MV_U8 twsiDevAddrType; -+ -+}MV_BOARD_TWSI_INFO; -+ -+ -+typedef enum _boardMacSpeed -+{ -+ BOARD_MAC_SPEED_10M, -+ BOARD_MAC_SPEED_100M, -+ BOARD_MAC_SPEED_1000M, -+ BOARD_MAC_SPEED_AUTO, -+ -+}MV_BOARD_MAC_SPEED; -+ -+typedef struct _boardMacInfo -+{ -+ MV_BOARD_MAC_SPEED boardMacSpeed; -+ MV_U8 boardEthSmiAddr; -+ -+}MV_BOARD_MAC_INFO; -+ -+typedef struct _boardMppInfo -+{ -+ MV_U32 mppGroup[MV_BOARD_MAX_MPP]; -+ -+}MV_BOARD_MPP_INFO; -+ -+typedef struct _boardInfo -+{ -+ char boardName[MV_BOARD_NAME_LEN]; -+ MV_U8 numBoardMppTypeValue; -+ MV_BOARD_MPP_TYPE_INFO* pBoardMppTypeValue; -+ MV_U8 numBoardMppConfigValue; -+ MV_BOARD_MPP_INFO* pBoardMppConfigValue; -+ MV_U32 intsGppMaskLow; -+ MV_U32 intsGppMaskHigh; -+ MV_U8 numBoardDeviceIf; -+ MV_DEV_CS_INFO* pDevCsInfo; -+ MV_U8 numBoardTwsiDev; -+ MV_BOARD_TWSI_INFO* pBoardTwsiDev; -+ MV_U8 numBoardMacInfo; -+ MV_BOARD_MAC_INFO* pBoardMacInfo; -+ MV_U8 numBoardGppInfo; -+ MV_BOARD_GPP_INFO* pBoardGppInfo; -+ MV_U8 activeLedsNumber; -+ MV_U8* pLedGppPin; -+ MV_U8 ledsPolarity; /* '0' or '1' to turn on led */ -+ /* GPP values */ -+ MV_U32 gppOutEnValLow; -+ MV_U32 gppOutEnValHigh; -+ MV_U32 gppOutValLow; -+ MV_U32 gppOutValHigh; -+ MV_U32 gppPolarityValLow; -+ MV_U32 gppPolarityValHigh; -+ -+ /* Switch Configuration */ -+ MV_BOARD_SWITCH_INFO* pSwitchInfo; -+}MV_BOARD_INFO; -+ -+ -+ -+MV_VOID mvBoardEnvInit(MV_VOID); -+MV_U32 mvBoardIdGet(MV_VOID); -+MV_U16 mvBoardModelGet(MV_VOID); -+MV_U16 mvBoardRevGet(MV_VOID); -+MV_STATUS mvBoardNameGet(char *pNameBuff); -+MV_32 mvBoardPhyAddrGet(MV_U32 ethPortNum); -+MV_BOARD_MAC_SPEED mvBoardMacSpeedGet(MV_U32 ethPortNum); -+MV_32 mvBoardLinkStatusIrqGet(MV_U32 ethPortNum); -+MV_32 mvBoardSwitchPortGet(MV_U32 ethPortNum, MV_U8 boardPortNum); -+MV_32 mvBoardSwitchCpuPortGet(MV_U32 ethPortNum); -+MV_32 mvBoardIsSwitchConnected(MV_U32 ethPortNum); -+MV_32 mvBoardSmiScanModeGet(MV_U32 ethPortNum); -+MV_BOOL mvBoardIsPortInSgmii(MV_U32 ethPortNum); -+MV_BOOL mvBoardIsPortInGmii(MV_VOID); -+MV_U32 mvBoardTclkGet(MV_VOID); -+MV_U32 mvBoardSysClkGet(MV_VOID); -+MV_U32 mvBoardDebugLedNumGet(MV_U32 boardId); -+MV_VOID mvBoardDebugLed(MV_U32 hexNum); -+MV_32 mvBoardMppGet(MV_U32 mppGroupNum); -+ -+MV_U8 mvBoardRtcTwsiAddrTypeGet(MV_VOID); -+MV_U8 mvBoardRtcTwsiAddrGet(MV_VOID); -+ -+MV_U8 mvBoardA2DTwsiAddrTypeGet(MV_VOID); -+MV_U8 mvBoardA2DTwsiAddrGet(MV_VOID); -+ -+MV_U8 mvBoardTwsiExpAddrGet(MV_U32 index); -+MV_U8 mvBoardTwsiSatRAddrTypeGet(MV_U32 index); -+MV_U8 mvBoardTwsiSatRAddrGet(MV_U32 index); -+MV_U8 mvBoardTwsiExpAddrTypeGet(MV_U32 index); -+MV_BOARD_MODULE_ID_CLASS mvBoarModuleTypeGet(MV_BOARD_MPP_GROUP_CLASS devClass); -+MV_BOARD_MPP_TYPE_CLASS mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass); -+MV_VOID mvBoardMppGroupTypeSet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass, -+ MV_BOARD_MPP_TYPE_CLASS mppGroupType); -+MV_VOID mvBoardMppGroupIdUpdate(MV_VOID); -+MV_VOID mvBoardMppMuxSet(MV_VOID); -+MV_VOID mvBoardTdmMppSet(MV_32 chType); -+MV_VOID mvBoardVoiceConnModeGet(MV_32* connMode, MV_32* irqMode); -+ -+MV_VOID mvBoardMppModuleTypePrint(MV_VOID); -+MV_VOID mvBoardReset(MV_VOID); -+MV_U8 mvBoarTwsiSatRGet(MV_U8 devNum, MV_U8 regNum); -+MV_STATUS mvBoarTwsiSatRSet(MV_U8 devNum, MV_U8 regNum, MV_U8 regVal); -+MV_BOOL mvBoardSpecInitGet(MV_U32* regOff, MV_U32* data); -+/* Board devices API managments */ -+MV_32 mvBoardGetDevicesNumber(MV_BOARD_DEV_CLASS devClass); -+MV_32 mvBoardGetDeviceBaseAddr(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); -+MV_32 mvBoardGetDeviceBusWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); -+MV_32 mvBoardGetDeviceWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); -+MV_32 mvBoardGetDeviceWinSize(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); -+MV_U32 boardGetDevCSNum(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); -+ -+/* Gpio Pin Connections API */ -+MV_32 mvBoardUSBVbusGpioPinGet(int devId); -+MV_32 mvBoardUSBVbusEnGpioPinGet(int devId); -+MV_U32 mvBoardPexBridgeIntPinGet(MV_U32 devNum, MV_U32 intPin); -+ -+MV_32 mvBoardResetGpioPinGet(MV_VOID); -+MV_32 mvBoardRTCGpioPinGet(MV_VOID); -+MV_32 mvBoardGpioIntMaskLowGet(MV_VOID); -+MV_32 mvBoardGpioIntMaskHighGet(MV_VOID); -+MV_32 mvBoardSlicGpioPinGet(MV_U32 slicNum); -+ -+MV_32 mvBoardSDIOGpioPinGet(MV_VOID); -+MV_STATUS mvBoardSDioWPControl(MV_BOOL mode); -+MV_32 mvBoarGpioPinNumGet(MV_BOARD_GPP_CLASS class, MV_U32 index); -+ -+MV_32 mvBoardNandWidthGet(void); -+MV_STATUS mvBoardFanPowerControl(MV_BOOL mode); -+MV_STATUS mvBoardHDDPowerControl(MV_BOOL mode); -+#endif /* __INCmvBoardEnvLibh */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c 2010-11-09 20:28:07.443751783 +0100 -@@ -0,0 +1,848 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#include "mvCommon.h" -+#include "mvBoardEnvLib.h" -+#include "mvBoardEnvSpec.h" -+#include "twsi/mvTwsi.h" -+ -+#define DB_88F6281A_BOARD_PCI_IF_NUM 0x0 -+#define DB_88F6281A_BOARD_TWSI_DEF_NUM 0x7 -+#define DB_88F6281A_BOARD_MAC_INFO_NUM 0x2 -+#define DB_88F6281A_BOARD_GPP_INFO_NUM 0x3 -+#define DB_88F6281A_BOARD_MPP_CONFIG_NUM 0x1 -+#define DB_88F6281A_BOARD_MPP_GROUP_TYPE_NUM 0x1 -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ #define DB_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1 -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ #define DB_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x2 -+#else -+ #define DB_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1 -+#endif -+#define DB_88F6281A_BOARD_DEBUG_LED_NUM 0x0 -+ -+ -+MV_BOARD_TWSI_INFO db88f6281AInfoBoardTwsiDev[] = -+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ -+ { -+ {BOARD_DEV_TWSI_EXP, 0x20, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_EXP, 0x21, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_SATR, 0x4D, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_SATR, 0x4E, ADDR7_BIT}, -+ {BOARD_TWSI_AUDIO_DEC, 0x4A, ADDR7_BIT} -+ }; -+ -+MV_BOARD_MAC_INFO db88f6281AInfoBoardMacInfo[] = -+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ -+ { -+ {BOARD_MAC_SPEED_AUTO, 0x8}, -+ {BOARD_MAC_SPEED_AUTO, 0x9} -+ }; -+ -+MV_BOARD_MPP_TYPE_INFO db88f6281AInfoBoardMppTypeInfo[] = -+ /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, -+ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ -+ {{MV_BOARD_AUTO, MV_BOARD_AUTO} -+ }; -+ -+MV_BOARD_GPP_INFO db88f6281AInfoBoardGppInfo[] = -+ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ -+ { -+ {BOARD_GPP_TSU_DIRCTION, 33} -+ /*muxed with TDM/Audio module via IOexpender -+ {BOARD_GPP_SDIO_DETECT, 38}, -+ {BOARD_GPP_USB_VBUS, 49}*/ -+ }; -+ -+MV_DEV_CS_INFO db88f6281AInfoBoardDeCsInfo[] = -+ /*{deviceCS, params, devType, devWidth}*/ -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ { -+ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ -+ {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ -+ }; -+#else -+ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ -+#endif -+ -+MV_BOARD_MPP_INFO db88f6281AInfoBoardMppConfigValue[] = -+ {{{ -+ DB_88F6281A_MPP0_7, -+ DB_88F6281A_MPP8_15, -+ DB_88F6281A_MPP16_23, -+ DB_88F6281A_MPP24_31, -+ DB_88F6281A_MPP32_39, -+ DB_88F6281A_MPP40_47, -+ DB_88F6281A_MPP48_55 -+ }}}; -+ -+ -+MV_BOARD_INFO db88f6281AInfo = { -+ "DB-88F6281A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ -+ DB_88F6281A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ -+ db88f6281AInfoBoardMppTypeInfo, -+ DB_88F6281A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ db88f6281AInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ 0, /* intsGppMaskHigh */ -+ DB_88F6281A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ db88f6281AInfoBoardDeCsInfo, -+ DB_88F6281A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ db88f6281AInfoBoardTwsiDev, -+ DB_88F6281A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ db88f6281AInfoBoardMacInfo, -+ DB_88F6281A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ db88f6281AInfoBoardGppInfo, -+ DB_88F6281A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ NULL, -+ 0, /* ledsPolarity */ -+ DB_88F6281A_OE_LOW, /* gppOutEnLow */ -+ DB_88F6281A_OE_HIGH, /* gppOutEnHigh */ -+ DB_88F6281A_OE_VAL_LOW, /* gppOutValLow */ -+ DB_88F6281A_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ BIT6, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+ -+#define RD_88F6281A_BOARD_PCI_IF_NUM 0x0 -+#define RD_88F6281A_BOARD_TWSI_DEF_NUM 0x2 -+#define RD_88F6281A_BOARD_MAC_INFO_NUM 0x2 -+#define RD_88F6281A_BOARD_GPP_INFO_NUM 0x5 -+#define RD_88F6281A_BOARD_MPP_GROUP_TYPE_NUM 0x1 -+#define RD_88F6281A_BOARD_MPP_CONFIG_NUM 0x1 -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ #define RD_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1 -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ #define RD_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x2 -+#else -+ #define RD_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1 -+#endif -+#define RD_88F6281A_BOARD_DEBUG_LED_NUM 0x0 -+ -+MV_BOARD_MAC_INFO rd88f6281AInfoBoardMacInfo[] = -+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ -+ {{BOARD_MAC_SPEED_1000M, 0xa}, -+ {BOARD_MAC_SPEED_AUTO, 0xb} -+ }; -+ -+MV_BOARD_SWITCH_INFO rd88f6281AInfoBoardSwitchInfo[] = -+ /* MV_32 linkStatusIrq, {MV_32 qdPort0, MV_32 qdPort1, MV_32 qdPort2, MV_32 qdPort3, MV_32 qdPort4}, -+ MV_32 qdCpuPort, MV_32 smiScanMode, MV_32 switchOnPort} */ -+ {{38, {0, 1, 2, 3, -1}, 5, 2, 0}, -+ {-1, {-1}, -1, -1, -1}}; -+ -+MV_BOARD_TWSI_INFO rd88f6281AInfoBoardTwsiDev[] = -+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ -+ { -+ {BOARD_DEV_TWSI_EXP, 0xFF, ADDR7_BIT}, /* dummy entry to align with modules indexes */ -+ {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT} -+ }; -+ -+MV_BOARD_MPP_TYPE_INFO rd88f6281AInfoBoardMppTypeInfo[] = -+ {{MV_BOARD_RGMII, MV_BOARD_TDM} -+ }; -+ -+MV_DEV_CS_INFO rd88f6281AInfoBoardDeCsInfo[] = -+ /*{deviceCS, params, devType, devWidth}*/ -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ { -+ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ -+ {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ -+ }; -+#else -+ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ -+#endif -+ -+MV_BOARD_GPP_INFO rd88f6281AInfoBoardGppInfo[] = -+ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ -+ {{BOARD_GPP_SDIO_DETECT, 28}, -+ {BOARD_GPP_USB_OC, 29}, -+ {BOARD_GPP_WPS_BUTTON, 35}, -+ {BOARD_GPP_MV_SWITCH, 38}, -+ {BOARD_GPP_USB_VBUS, 49} -+ }; -+ -+MV_BOARD_MPP_INFO rd88f6281AInfoBoardMppConfigValue[] = -+ {{{ -+ RD_88F6281A_MPP0_7, -+ RD_88F6281A_MPP8_15, -+ RD_88F6281A_MPP16_23, -+ RD_88F6281A_MPP24_31, -+ RD_88F6281A_MPP32_39, -+ RD_88F6281A_MPP40_47, -+ RD_88F6281A_MPP48_55 -+ }}}; -+ -+MV_BOARD_INFO rd88f6281AInfo = { -+ "RD-88F6281A", /* boardName[MAX_BOARD_NAME_LEN] */ -+ RD_88F6281A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ -+ rd88f6281AInfoBoardMppTypeInfo, -+ RD_88F6281A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ rd88f6281AInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ (1 << 3), /* intsGppMaskHigh */ -+ RD_88F6281A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ rd88f6281AInfoBoardDeCsInfo, -+ RD_88F6281A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ rd88f6281AInfoBoardTwsiDev, -+ RD_88F6281A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ rd88f6281AInfoBoardMacInfo, -+ RD_88F6281A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ rd88f6281AInfoBoardGppInfo, -+ RD_88F6281A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ NULL, -+ 0, /* ledsPolarity */ -+ RD_88F6281A_OE_LOW, /* gppOutEnLow */ -+ RD_88F6281A_OE_HIGH, /* gppOutEnHigh */ -+ RD_88F6281A_OE_VAL_LOW, /* gppOutValLow */ -+ RD_88F6281A_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ BIT6, /* gppPolarityValHigh */ -+ rd88f6281AInfoBoardSwitchInfo /* pSwitchInfo */ -+}; -+ -+ -+#define DB_88F6192A_BOARD_PCI_IF_NUM 0x0 -+#define DB_88F6192A_BOARD_TWSI_DEF_NUM 0x7 -+#define DB_88F6192A_BOARD_MAC_INFO_NUM 0x2 -+#define DB_88F6192A_BOARD_GPP_INFO_NUM 0x3 -+#define DB_88F6192A_BOARD_MPP_GROUP_TYPE_NUM 0x1 -+#define DB_88F6192A_BOARD_MPP_CONFIG_NUM 0x1 -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ #define DB_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x1 -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ #define DB_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x2 -+#else -+ #define DB_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x1 -+#endif -+#define DB_88F6192A_BOARD_DEBUG_LED_NUM 0x0 -+ -+MV_BOARD_TWSI_INFO db88f6192AInfoBoardTwsiDev[] = -+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ -+ { -+ {BOARD_DEV_TWSI_EXP, 0x20, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_EXP, 0x21, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_SATR, 0x4D, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_SATR, 0x4E, ADDR7_BIT}, -+ {BOARD_TWSI_AUDIO_DEC, 0x4A, ADDR7_BIT} -+ }; -+ -+MV_BOARD_MAC_INFO db88f6192AInfoBoardMacInfo[] = -+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ -+ { -+ {BOARD_MAC_SPEED_AUTO, 0x8}, -+ {BOARD_MAC_SPEED_AUTO, 0x9} -+ }; -+ -+MV_BOARD_MPP_TYPE_INFO db88f6192AInfoBoardMppTypeInfo[] = -+ /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, -+ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ -+ {{MV_BOARD_AUTO, MV_BOARD_OTHER} -+ }; -+ -+MV_DEV_CS_INFO db88f6192AInfoBoardDeCsInfo[] = -+ /*{deviceCS, params, devType, devWidth}*/ -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ { -+ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ -+ {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ -+ }; -+#else -+ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ -+#endif -+ -+MV_BOARD_GPP_INFO db88f6192AInfoBoardGppInfo[] = -+ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ -+ { -+ {BOARD_GPP_SDIO_WP, 20}, -+ {BOARD_GPP_USB_VBUS, 22}, -+ {BOARD_GPP_SDIO_DETECT, 23}, -+ }; -+ -+MV_BOARD_MPP_INFO db88f6192AInfoBoardMppConfigValue[] = -+ {{{ -+ DB_88F6192A_MPP0_7, -+ DB_88F6192A_MPP8_15, -+ DB_88F6192A_MPP16_23, -+ DB_88F6192A_MPP24_31, -+ DB_88F6192A_MPP32_35 -+ }}}; -+ -+MV_BOARD_INFO db88f6192AInfo = { -+ "DB-88F6192A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ -+ DB_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ -+ db88f6192AInfoBoardMppTypeInfo, -+ DB_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ db88f6192AInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ (1 << 3), /* intsGppMaskHigh */ -+ DB_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ db88f6192AInfoBoardDeCsInfo, -+ DB_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ db88f6192AInfoBoardTwsiDev, -+ DB_88F6192A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ db88f6192AInfoBoardMacInfo, -+ DB_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ db88f6192AInfoBoardGppInfo, -+ DB_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ NULL, -+ 0, /* ledsPolarity */ -+ DB_88F6192A_OE_LOW, /* gppOutEnLow */ -+ DB_88F6192A_OE_HIGH, /* gppOutEnHigh */ -+ DB_88F6192A_OE_VAL_LOW, /* gppOutValLow */ -+ DB_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ 0, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+#define DB_88F6190A_BOARD_MAC_INFO_NUM 0x1 -+ -+MV_BOARD_INFO db88f6190AInfo = { -+ "DB-88F6190A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ -+ DB_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ -+ db88f6192AInfoBoardMppTypeInfo, -+ DB_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ db88f6192AInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ (1 << 3), /* intsGppMaskHigh */ -+ DB_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ db88f6192AInfoBoardDeCsInfo, -+ DB_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ db88f6192AInfoBoardTwsiDev, -+ DB_88F6190A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ db88f6192AInfoBoardMacInfo, -+ DB_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ db88f6192AInfoBoardGppInfo, -+ DB_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ NULL, -+ 0, /* ledsPolarity */ -+ DB_88F6192A_OE_LOW, /* gppOutEnLow */ -+ DB_88F6192A_OE_HIGH, /* gppOutEnHigh */ -+ DB_88F6192A_OE_VAL_LOW, /* gppOutValLow */ -+ DB_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ 0, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+#define RD_88F6192A_BOARD_PCI_IF_NUM 0x0 -+#define RD_88F6192A_BOARD_TWSI_DEF_NUM 0x0 -+#define RD_88F6192A_BOARD_MAC_INFO_NUM 0x1 -+#define RD_88F6192A_BOARD_GPP_INFO_NUM 0xE -+#define RD_88F6192A_BOARD_MPP_GROUP_TYPE_NUM 0x1 -+#define RD_88F6192A_BOARD_MPP_CONFIG_NUM 0x1 -+#define RD_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x1 -+#define RD_88F6192A_BOARD_DEBUG_LED_NUM 0x3 -+ -+MV_U8 rd88f6192AInfoBoardDebugLedIf[] = -+ {17, 28, 29}; -+ -+MV_BOARD_MAC_INFO rd88f6192AInfoBoardMacInfo[] = -+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ -+ {{BOARD_MAC_SPEED_AUTO, 0x8} -+ }; -+ -+MV_BOARD_MPP_TYPE_INFO rd88f6192AInfoBoardMppTypeInfo[] = -+ /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, -+ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ -+ {{MV_BOARD_OTHER, MV_BOARD_OTHER} -+ }; -+ -+MV_DEV_CS_INFO rd88f6192AInfoBoardDeCsInfo[] = -+ /*{deviceCS, params, devType, devWidth}*/ -+ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ -+ -+MV_BOARD_GPP_INFO rd88f6192AInfoBoardGppInfo[] = -+ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ -+ { -+ {BOARD_GPP_USB_VBUS_EN, 10}, -+ {BOARD_GPP_USB_HOST_DEVICE, 11}, -+ {BOARD_GPP_RESET, 14}, -+ {BOARD_GPP_POWER_ON_LED, 15}, -+ {BOARD_GPP_HDD_POWER, 16}, -+ {BOARD_GPP_WPS_BUTTON, 24}, -+ {BOARD_GPP_TS_BUTTON_C, 25}, -+ {BOARD_GPP_USB_VBUS, 26}, -+ {BOARD_GPP_USB_OC, 27}, -+ {BOARD_GPP_TS_BUTTON_U, 30}, -+ {BOARD_GPP_TS_BUTTON_R, 31}, -+ {BOARD_GPP_TS_BUTTON_L, 32}, -+ {BOARD_GPP_TS_BUTTON_D, 34}, -+ {BOARD_GPP_FAN_POWER, 35} -+ }; -+ -+MV_BOARD_MPP_INFO rd88f6192AInfoBoardMppConfigValue[] = -+ {{{ -+ RD_88F6192A_MPP0_7, -+ RD_88F6192A_MPP8_15, -+ RD_88F6192A_MPP16_23, -+ RD_88F6192A_MPP24_31, -+ RD_88F6192A_MPP32_35 -+ }}}; -+ -+MV_BOARD_INFO rd88f6192AInfo = { -+ "RD-88F6192A-NAS", /* boardName[MAX_BOARD_NAME_LEN] */ -+ RD_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ -+ rd88f6192AInfoBoardMppTypeInfo, -+ RD_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ rd88f6192AInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ (1 << 3), /* intsGppMaskHigh */ -+ RD_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ rd88f6192AInfoBoardDeCsInfo, -+ RD_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ NULL, -+ RD_88F6192A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ rd88f6192AInfoBoardMacInfo, -+ RD_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ rd88f6192AInfoBoardGppInfo, -+ RD_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ rd88f6192AInfoBoardDebugLedIf, -+ 0, /* ledsPolarity */ -+ RD_88F6192A_OE_LOW, /* gppOutEnLow */ -+ RD_88F6192A_OE_HIGH, /* gppOutEnHigh */ -+ RD_88F6192A_OE_VAL_LOW, /* gppOutValLow */ -+ RD_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ 0, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+MV_BOARD_INFO rd88f6190AInfo = { -+ "RD-88F6190A-NAS", /* boardName[MAX_BOARD_NAME_LEN] */ -+ RD_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ -+ rd88f6192AInfoBoardMppTypeInfo, -+ RD_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ rd88f6192AInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ (1 << 3), /* intsGppMaskHigh */ -+ RD_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ rd88f6192AInfoBoardDeCsInfo, -+ RD_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ NULL, -+ RD_88F6192A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ rd88f6192AInfoBoardMacInfo, -+ RD_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ rd88f6192AInfoBoardGppInfo, -+ RD_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ rd88f6192AInfoBoardDebugLedIf, -+ 0, /* ledsPolarity */ -+ RD_88F6192A_OE_LOW, /* gppOutEnLow */ -+ RD_88F6192A_OE_HIGH, /* gppOutEnHigh */ -+ RD_88F6192A_OE_VAL_LOW, /* gppOutValLow */ -+ RD_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ 0, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+#define DB_88F6180A_BOARD_PCI_IF_NUM 0x0 -+#define DB_88F6180A_BOARD_TWSI_DEF_NUM 0x5 -+#define DB_88F6180A_BOARD_MAC_INFO_NUM 0x1 -+#define DB_88F6180A_BOARD_GPP_INFO_NUM 0x0 -+#define DB_88F6180A_BOARD_MPP_GROUP_TYPE_NUM 0x2 -+#define DB_88F6180A_BOARD_MPP_CONFIG_NUM 0x1 -+#define DB_88F6180A_BOARD_DEVICE_CONFIG_NUM 0x1 -+#define DB_88F6180A_BOARD_DEBUG_LED_NUM 0x0 -+ -+MV_BOARD_TWSI_INFO db88f6180AInfoBoardTwsiDev[] = -+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ -+ { -+ {BOARD_DEV_TWSI_EXP, 0x20, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_EXP, 0x21, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, -+ {BOARD_TWSI_AUDIO_DEC, 0x4A, ADDR7_BIT} -+ }; -+ -+MV_BOARD_MAC_INFO db88f6180AInfoBoardMacInfo[] = -+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ -+ {{BOARD_MAC_SPEED_AUTO, 0x8} -+ }; -+ -+MV_BOARD_GPP_INFO db88f6180AInfoBoardGppInfo[] = -+ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ -+ { -+ /* Muxed with TDM/Audio module via IOexpender -+ {BOARD_GPP_USB_VBUS, 6} */ -+ }; -+ -+MV_BOARD_MPP_TYPE_INFO db88f6180AInfoBoardMppTypeInfo[] = -+ /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, -+ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ -+ {{MV_BOARD_OTHER, MV_BOARD_AUTO} -+ }; -+ -+MV_DEV_CS_INFO db88f6180AInfoBoardDeCsInfo[] = -+ /*{deviceCS, params, devType, devWidth}*/ -+#if defined(MV_NAND_BOOT) -+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ -+#else -+ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ -+#endif -+ -+MV_BOARD_MPP_INFO db88f6180AInfoBoardMppConfigValue[] = -+ {{{ -+ DB_88F6180A_MPP0_7, -+ DB_88F6180A_MPP8_15, -+ DB_88F6180A_MPP16_23, -+ DB_88F6180A_MPP24_31, -+ DB_88F6180A_MPP32_39, -+ DB_88F6180A_MPP40_44 -+ }}}; -+ -+MV_BOARD_INFO db88f6180AInfo = { -+ "DB-88F6180A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ -+ DB_88F6180A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ -+ db88f6180AInfoBoardMppTypeInfo, -+ DB_88F6180A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ db88f6180AInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ 0, /* intsGppMaskHigh */ -+ DB_88F6180A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ db88f6180AInfoBoardDeCsInfo, -+ DB_88F6180A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ db88f6180AInfoBoardTwsiDev, -+ DB_88F6180A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ db88f6180AInfoBoardMacInfo, -+ DB_88F6180A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ NULL, -+ DB_88F6180A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ NULL, -+ 0, /* ledsPolarity */ -+ DB_88F6180A_OE_LOW, /* gppOutEnLow */ -+ DB_88F6180A_OE_HIGH, /* gppOutEnHigh */ -+ DB_88F6180A_OE_VAL_LOW, /* gppOutValLow */ -+ DB_88F6180A_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ 0, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+ -+#define RD_88F6281A_PCAC_BOARD_PCI_IF_NUM 0x0 -+#define RD_88F6281A_PCAC_BOARD_TWSI_DEF_NUM 0x1 -+#define RD_88F6281A_PCAC_BOARD_MAC_INFO_NUM 0x1 -+#define RD_88F6281A_PCAC_BOARD_GPP_INFO_NUM 0x0 -+#define RD_88F6281A_PCAC_BOARD_MPP_GROUP_TYPE_NUM 0x1 -+#define RD_88F6281A_PCAC_BOARD_MPP_CONFIG_NUM 0x1 -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ #define RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM 0x1 -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ #define RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM 0x2 -+#else -+ #define RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM 0x1 -+#endif -+#define RD_88F6281A_PCAC_BOARD_DEBUG_LED_NUM 0x4 -+ -+MV_U8 rd88f6281APcacInfoBoardDebugLedIf[] = -+ {38, 39, 40, 41}; -+ -+MV_BOARD_MAC_INFO rd88f6281APcacInfoBoardMacInfo[] = -+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ -+ {{BOARD_MAC_SPEED_AUTO, 0x8} -+ }; -+ -+MV_BOARD_TWSI_INFO rd88f6281APcacInfoBoardTwsiDev[] = -+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ -+ { -+ {BOARD_TWSI_OTHER, 0xa7, ADDR7_BIT} -+ }; -+ -+MV_BOARD_MPP_TYPE_INFO rd88f6281APcacInfoBoardMppTypeInfo[] = -+ {{MV_BOARD_OTHER, MV_BOARD_OTHER} -+ }; -+ -+MV_DEV_CS_INFO rd88f6281APcacInfoBoardDeCsInfo[] = -+ /*{deviceCS, params, devType, devWidth}*/ -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ { -+ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ -+ {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ -+ }; -+#else -+ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ -+#endif -+ -+MV_BOARD_MPP_INFO rd88f6281APcacInfoBoardMppConfigValue[] = -+ {{{ -+ RD_88F6281A_PCAC_MPP0_7, -+ RD_88F6281A_PCAC_MPP8_15, -+ RD_88F6281A_PCAC_MPP16_23, -+ RD_88F6281A_PCAC_MPP24_31, -+ RD_88F6281A_PCAC_MPP32_39, -+ RD_88F6281A_PCAC_MPP40_47, -+ RD_88F6281A_PCAC_MPP48_55 -+ }}}; -+ -+MV_BOARD_INFO rd88f6281APcacInfo = { -+ "RD-88F6281A-PCAC", /* boardName[MAX_BOARD_NAME_LEN] */ -+ RD_88F6281A_PCAC_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ -+ rd88f6281APcacInfoBoardMppTypeInfo, -+ RD_88F6281A_PCAC_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ rd88f6281APcacInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ (1 << 3), /* intsGppMaskHigh */ -+ RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ rd88f6281APcacInfoBoardDeCsInfo, -+ RD_88F6281A_PCAC_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ rd88f6281APcacInfoBoardTwsiDev, -+ RD_88F6281A_PCAC_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ rd88f6281APcacInfoBoardMacInfo, -+ RD_88F6281A_PCAC_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ 0, -+ RD_88F6281A_PCAC_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ NULL, -+ 0, /* ledsPolarity */ -+ RD_88F6281A_PCAC_OE_LOW, /* gppOutEnLow */ -+ RD_88F6281A_PCAC_OE_HIGH, /* gppOutEnHigh */ -+ RD_88F6281A_PCAC_OE_VAL_LOW, /* gppOutValLow */ -+ RD_88F6281A_PCAC_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ 0, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+ -+/* 6281 Sheeva Plug*/ -+ -+#define SHEEVA_PLUG_BOARD_PCI_IF_NUM 0x0 -+#define SHEEVA_PLUG_BOARD_TWSI_DEF_NUM 0x0 -+#define SHEEVA_PLUG_BOARD_MAC_INFO_NUM 0x1 -+#define SHEEVA_PLUG_BOARD_GPP_INFO_NUM 0x0 -+#define SHEEVA_PLUG_BOARD_MPP_GROUP_TYPE_NUN 0x1 -+#define SHEEVA_PLUG_BOARD_MPP_CONFIG_NUM 0x1 -+#define SHEEVA_PLUG_BOARD_DEVICE_CONFIG_NUM 0x1 -+#define SHEEVA_PLUG_BOARD_DEBUG_LED_NUM 0x1 -+ -+MV_U8 sheevaPlugInfoBoardDebugLedIf[] = -+ {49}; -+ -+MV_BOARD_MAC_INFO sheevaPlugInfoBoardMacInfo[] = -+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ -+ {{BOARD_MAC_SPEED_AUTO, 0x0}}; -+ -+MV_BOARD_TWSI_INFO sheevaPlugInfoBoardTwsiDev[] = -+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ -+ {{BOARD_TWSI_OTHER, 0x0, ADDR7_BIT}}; -+ -+MV_BOARD_MPP_TYPE_INFO sheevaPlugInfoBoardMppTypeInfo[] = -+ {{MV_BOARD_OTHER, MV_BOARD_OTHER} -+ }; -+ -+MV_DEV_CS_INFO sheevaPlugInfoBoardDeCsInfo[] = -+ /*{deviceCS, params, devType, devWidth}*/ -+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ -+ -+MV_BOARD_MPP_INFO sheevaPlugInfoBoardMppConfigValue[] = -+ {{{ -+ RD_SHEEVA_PLUG_MPP0_7, -+ RD_SHEEVA_PLUG_MPP8_15, -+ RD_SHEEVA_PLUG_MPP16_23, -+ RD_SHEEVA_PLUG_MPP24_31, -+ RD_SHEEVA_PLUG_MPP32_39, -+ RD_SHEEVA_PLUG_MPP40_47, -+ RD_SHEEVA_PLUG_MPP48_55 -+ }}}; -+ -+MV_BOARD_INFO sheevaPlugInfo = { -+ "SHEEVA PLUG", /* boardName[MAX_BOARD_NAME_LEN] */ -+ SHEEVA_PLUG_BOARD_MPP_GROUP_TYPE_NUN, /* numBoardMppGroupType */ -+ sheevaPlugInfoBoardMppTypeInfo, -+ SHEEVA_PLUG_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ sheevaPlugInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ 0, /* intsGppMaskHigh */ -+ SHEEVA_PLUG_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ sheevaPlugInfoBoardDeCsInfo, -+ SHEEVA_PLUG_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ sheevaPlugInfoBoardTwsiDev, -+ SHEEVA_PLUG_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ sheevaPlugInfoBoardMacInfo, -+ SHEEVA_PLUG_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ 0, -+ SHEEVA_PLUG_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ sheevaPlugInfoBoardDebugLedIf, -+ 0, /* ledsPolarity */ -+ RD_SHEEVA_PLUG_OE_LOW, /* gppOutEnLow */ -+ RD_SHEEVA_PLUG_OE_HIGH, /* gppOutEnHigh */ -+ RD_SHEEVA_PLUG_OE_VAL_LOW, /* gppOutValLow */ -+ RD_SHEEVA_PLUG_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ 0, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+/* Customer specific board place holder*/ -+ -+#define DB_CUSTOMER_BOARD_PCI_IF_NUM 0x0 -+#define DB_CUSTOMER_BOARD_TWSI_DEF_NUM 0x0 -+#define DB_CUSTOMER_BOARD_MAC_INFO_NUM 0x0 -+#define DB_CUSTOMER_BOARD_GPP_INFO_NUM 0x0 -+#define DB_CUSTOMER_BOARD_MPP_GROUP_TYPE_NUN 0x0 -+#define DB_CUSTOMER_BOARD_MPP_CONFIG_NUM 0x0 -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ #define DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM 0x0 -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ #define DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM 0x0 -+#else -+ #define DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM 0x0 -+#endif -+#define DB_CUSTOMER_BOARD_DEBUG_LED_NUM 0x0 -+ -+MV_U8 dbCustomerInfoBoardDebugLedIf[] = -+ {0}; -+ -+MV_BOARD_MAC_INFO dbCustomerInfoBoardMacInfo[] = -+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ -+ {{BOARD_MAC_SPEED_AUTO, 0x0}}; -+ -+MV_BOARD_TWSI_INFO dbCustomerInfoBoardTwsiDev[] = -+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ -+ {{BOARD_TWSI_OTHER, 0x0, ADDR7_BIT}}; -+ -+MV_BOARD_MPP_TYPE_INFO dbCustomerInfoBoardMppTypeInfo[] = -+ {{MV_BOARD_OTHER, MV_BOARD_OTHER} -+ }; -+ -+MV_DEV_CS_INFO dbCustomerInfoBoardDeCsInfo[] = -+ /*{deviceCS, params, devType, devWidth}*/ -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ { -+ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ -+ {2, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ -+ }; -+#else -+ {{2, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ -+#endif -+ -+MV_BOARD_MPP_INFO dbCustomerInfoBoardMppConfigValue[] = -+ {{{ -+ DB_CUSTOMER_MPP0_7, -+ DB_CUSTOMER_MPP8_15, -+ DB_CUSTOMER_MPP16_23, -+ DB_CUSTOMER_MPP24_31, -+ DB_CUSTOMER_MPP32_39, -+ DB_CUSTOMER_MPP40_47, -+ DB_CUSTOMER_MPP48_55 -+ }}}; -+ -+MV_BOARD_INFO dbCustomerInfo = { -+ "DB-CUSTOMER", /* boardName[MAX_BOARD_NAME_LEN] */ -+ DB_CUSTOMER_BOARD_MPP_GROUP_TYPE_NUN, /* numBoardMppGroupType */ -+ dbCustomerInfoBoardMppTypeInfo, -+ DB_CUSTOMER_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ dbCustomerInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ 0, /* intsGppMaskHigh */ -+ DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ dbCustomerInfoBoardDeCsInfo, -+ DB_CUSTOMER_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ dbCustomerInfoBoardTwsiDev, -+ DB_CUSTOMER_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ dbCustomerInfoBoardMacInfo, -+ DB_CUSTOMER_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ 0, -+ DB_CUSTOMER_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ NULL, -+ 0, /* ledsPolarity */ -+ DB_CUSTOMER_OE_LOW, /* gppOutEnLow */ -+ DB_CUSTOMER_OE_HIGH, /* gppOutEnHigh */ -+ DB_CUSTOMER_OE_VAL_LOW, /* gppOutValLow */ -+ DB_CUSTOMER_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ 0, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+MV_BOARD_INFO* boardInfoTbl[] = { -+ &db88f6281AInfo, -+ &rd88f6281AInfo, -+ &db88f6192AInfo, -+ &rd88f6192AInfo, -+ &db88f6180AInfo, -+ &db88f6190AInfo, -+ &rd88f6190AInfo, -+ &rd88f6281APcacInfo, -+ &dbCustomerInfo, -+ &sheevaPlugInfo -+ }; -+ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.h 2010-11-09 20:28:07.482495476 +0100 -@@ -0,0 +1,262 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvBoardEnvSpech -+#define __INCmvBoardEnvSpech -+ -+#include "mvSysHwConfig.h" -+ -+ -+/* For future use */ -+#define BD_ID_DATA_START_OFFS 0x0 -+#define BD_DETECT_SEQ_OFFS 0x0 -+#define BD_SYS_NUM_OFFS 0x4 -+#define BD_NAME_OFFS 0x8 -+ -+/* I2C bus addresses */ -+#define MV_BOARD_CTRL_I2C_ADDR 0x0 /* Controller slave addr */ -+#define MV_BOARD_CTRL_I2C_ADDR_TYPE ADDR7_BIT -+#define MV_BOARD_DIMM0_I2C_ADDR 0x56 -+#define MV_BOARD_DIMM0_I2C_ADDR_TYPE ADDR7_BIT -+#define MV_BOARD_DIMM1_I2C_ADDR 0x54 -+#define MV_BOARD_DIMM1_I2C_ADDR_TYPE ADDR7_BIT -+#define MV_BOARD_EEPROM_I2C_ADDR 0x51 -+#define MV_BOARD_EEPROM_I2C_ADDR_TYPE ADDR7_BIT -+#define MV_BOARD_MAIN_EEPROM_I2C_ADDR 0x50 -+#define MV_BOARD_MAIN_EEPROM_I2C_ADDR_TYPE ADDR7_BIT -+#define MV_BOARD_MUX_I2C_ADDR_ENTRY 0x2 -+#define MV_BOARD_DIMM_I2C_CHANNEL 0x0 -+ -+#define BOOT_FLASH_INDEX 0 -+#define MAIN_FLASH_INDEX 1 -+ -+#define BOARD_ETH_START_PORT_NUM 0 -+ -+/* Supported clocks */ -+#define MV_BOARD_TCLK_100MHZ 100000000 -+#define MV_BOARD_TCLK_125MHZ 125000000 -+#define MV_BOARD_TCLK_133MHZ 133333333 -+#define MV_BOARD_TCLK_150MHZ 150000000 -+#define MV_BOARD_TCLK_166MHZ 166666667 -+#define MV_BOARD_TCLK_200MHZ 200000000 -+ -+#define MV_BOARD_SYSCLK_100MHZ 100000000 -+#define MV_BOARD_SYSCLK_125MHZ 125000000 -+#define MV_BOARD_SYSCLK_133MHZ 133333333 -+#define MV_BOARD_SYSCLK_150MHZ 150000000 -+#define MV_BOARD_SYSCLK_166MHZ 166666667 -+#define MV_BOARD_SYSCLK_200MHZ 200000000 -+#define MV_BOARD_SYSCLK_233MHZ 233333333 -+#define MV_BOARD_SYSCLK_250MHZ 250000000 -+#define MV_BOARD_SYSCLK_267MHZ 266666667 -+#define MV_BOARD_SYSCLK_300MHZ 300000000 -+#define MV_BOARD_SYSCLK_333MHZ 333333334 -+#define MV_BOARD_SYSCLK_400MHZ 400000000 -+ -+#define MV_BOARD_REFCLK_25MHZ 25000000 -+ -+/* Board specific */ -+/* =============================== */ -+ -+/* boards ID numbers */ -+ -+#define BOARD_ID_BASE 0x0 -+ -+/* New board ID numbers */ -+#define DB_88F6281A_BP_ID (BOARD_ID_BASE) -+#define DB_88F6281_BP_MLL_ID 1680 -+#define RD_88F6281A_ID (BOARD_ID_BASE+0x1) -+#define RD_88F6281_MLL_ID 1682 -+#define DB_88F6192A_BP_ID (BOARD_ID_BASE+0x2) -+#define RD_88F6192A_ID (BOARD_ID_BASE+0x3) -+#define RD_88F6192_MLL_ID 1681 -+#define DB_88F6180A_BP_ID (BOARD_ID_BASE+0x4) -+#define DB_88F6190A_BP_ID (BOARD_ID_BASE+0x5) -+#define RD_88F6190A_ID (BOARD_ID_BASE+0x6) -+#define RD_88F6281A_PCAC_ID (BOARD_ID_BASE+0x7) -+#define DB_CUSTOMER_ID (BOARD_ID_BASE+0x8) -+#define SHEEVA_PLUG_ID (BOARD_ID_BASE+0x9) -+#define MV_MAX_BOARD_ID (SHEEVA_PLUG_ID + 1) -+ -+/* DB-88F6281A-BP */ -+#if defined(MV_NAND) -+ #define DB_88F6281A_MPP0_7 0x21111111 -+#else -+ #define DB_88F6281A_MPP0_7 0x21112220 -+#endif -+#define DB_88F6281A_MPP8_15 0x11113311 -+#define DB_88F6281A_MPP16_23 0x00551111 -+#define DB_88F6281A_MPP24_31 0x00000000 -+#define DB_88F6281A_MPP32_39 0x00000000 -+#define DB_88F6281A_MPP40_47 0x00000000 -+#define DB_88F6281A_MPP48_55 0x00000000 -+#define DB_88F6281A_OE_LOW 0x0 -+#if defined(MV_TDM_5CHANNELS) -+ #define DB_88F6281A_OE_HIGH (BIT6) -+#else -+#define DB_88F6281A_OE_HIGH 0x0 -+#endif -+#define DB_88F6281A_OE_VAL_LOW 0x0 -+#define DB_88F6281A_OE_VAL_HIGH 0x0 -+ -+/* RD-88F6281A */ -+#if defined(MV_NAND) -+ #define RD_88F6281A_MPP0_7 0x21111111 -+#else -+ #define RD_88F6281A_MPP0_7 0x21112220 -+#endif -+#define RD_88F6281A_MPP8_15 0x11113311 -+#define RD_88F6281A_MPP16_23 0x33331111 -+#define RD_88F6281A_MPP24_31 0x33003333 -+#define RD_88F6281A_MPP32_39 0x20440533 -+#define RD_88F6281A_MPP40_47 0x22202222 -+#define RD_88F6281A_MPP48_55 0x00000002 -+#define RD_88F6281A_OE_LOW (BIT28 | BIT29) -+#define RD_88F6281A_OE_HIGH (BIT3 | BIT6 | BIT17) -+#define RD_88F6281A_OE_VAL_LOW 0x0 -+#define RD_88F6281A_OE_VAL_HIGH 0x0 -+ -+/* DB-88F6192A-BP */ -+#if defined(MV_NAND) -+ #define DB_88F6192A_MPP0_7 0x21111111 -+#else -+ #define DB_88F6192A_MPP0_7 0x21112220 -+#endif -+#define DB_88F6192A_MPP8_15 0x11113311 -+#define DB_88F6192A_MPP16_23 0x00501111 -+#define DB_88F6192A_MPP24_31 0x00000000 -+#define DB_88F6192A_MPP32_35 0x00000000 -+#define DB_88F6192A_OE_LOW (BIT22 | BIT23) -+#define DB_88F6192A_OE_HIGH 0x0 -+#define DB_88F6192A_OE_VAL_LOW 0x0 -+#define DB_88F6192A_OE_VAL_HIGH 0x0 -+ -+/* RD-88F6192A */ -+#define RD_88F6192A_MPP0_7 0x01222222 -+#define RD_88F6192A_MPP8_15 0x00000011 -+#define RD_88F6192A_MPP16_23 0x05550000 -+#define RD_88F6192A_MPP24_31 0x0 -+#define RD_88F6192A_MPP32_35 0x0 -+#define RD_88F6192A_OE_LOW (BIT11 | BIT14 | BIT24 | BIT25 | BIT26 | BIT27 | BIT30 | BIT31) -+#define RD_88F6192A_OE_HIGH (BIT0 | BIT2) -+#define RD_88F6192A_OE_VAL_LOW 0x18400 -+#define RD_88F6192A_OE_VAL_HIGH 0x8 -+ -+/* DB-88F6180A-BP */ -+#if defined(MV_NAND) -+ #define DB_88F6180A_MPP0_7 0x21111111 -+#else -+ #define DB_88F6180A_MPP0_7 0x01112222 -+#endif -+#define DB_88F6180A_MPP8_15 0x11113311 -+#define DB_88F6180A_MPP16_23 0x00001111 -+#define DB_88F6180A_MPP24_31 0x0 -+#define DB_88F6180A_MPP32_39 0x4444c000 -+#define DB_88F6180A_MPP40_44 0x00044444 -+#define DB_88F6180A_OE_LOW 0x0 -+#define DB_88F6180A_OE_HIGH 0x0 -+#define DB_88F6180A_OE_VAL_LOW 0x0 -+#define DB_88F6180A_OE_VAL_HIGH 0x0 -+ -+/* RD-88F6281A_PCAC */ -+#define RD_88F6281A_PCAC_MPP0_7 0x21111111 -+#define RD_88F6281A_PCAC_MPP8_15 0x00003311 -+#define RD_88F6281A_PCAC_MPP16_23 0x00001100 -+#define RD_88F6281A_PCAC_MPP24_31 0x00000000 -+#define RD_88F6281A_PCAC_MPP32_39 0x00000000 -+#define RD_88F6281A_PCAC_MPP40_47 0x00000000 -+#define RD_88F6281A_PCAC_MPP48_55 0x00000000 -+#define RD_88F6281A_PCAC_OE_LOW 0x0 -+#define RD_88F6281A_PCAC_OE_HIGH 0x0 -+#define RD_88F6281A_PCAC_OE_VAL_LOW 0x0 -+#define RD_88F6281A_PCAC_OE_VAL_HIGH 0x0 -+ -+/* SHEEVA PLUG */ -+#define RD_SHEEVA_PLUG_MPP0_7 0x01111111 -+#define RD_SHEEVA_PLUG_MPP8_15 0x11113322 -+#define RD_SHEEVA_PLUG_MPP16_23 0x00001111 -+#define RD_SHEEVA_PLUG_MPP24_31 0x00100000 -+#define RD_SHEEVA_PLUG_MPP32_39 0x00000000 -+#define RD_SHEEVA_PLUG_MPP40_47 0x00000000 -+#define RD_SHEEVA_PLUG_MPP48_55 0x00000000 -+#define RD_SHEEVA_PLUG_OE_LOW 0x0 -+#define RD_SHEEVA_PLUG_OE_HIGH 0x0 -+#define RD_SHEEVA_PLUG_OE_VAL_LOW (BIT29) -+#define RD_SHEEVA_PLUG_OE_VAL_HIGH ((~(BIT17 | BIT16 | BIT15)) | BIT14) -+ -+/* DB-CUSTOMER */ -+#define DB_CUSTOMER_MPP0_7 0x21111111 -+#define DB_CUSTOMER_MPP8_15 0x00003311 -+#define DB_CUSTOMER_MPP16_23 0x00001100 -+#define DB_CUSTOMER_MPP24_31 0x00000000 -+#define DB_CUSTOMER_MPP32_39 0x00000000 -+#define DB_CUSTOMER_MPP40_47 0x00000000 -+#define DB_CUSTOMER_MPP48_55 0x00000000 -+#define DB_CUSTOMER_OE_LOW 0x0 -+#define DB_CUSTOMER_OE_HIGH (~((BIT6) | (BIT7) | (BIT8) | (BIT9))) -+#define DB_CUSTOMER_OE_VAL_LOW 0x0 -+#define DB_CUSTOMER_OE_VAL_HIGH 0x0 -+ -+#endif /* __INCmvBoardEnvSpech */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c 2010-11-09 20:28:07.522495500 +0100 -@@ -0,0 +1,320 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#include "cpu/mvCpu.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvRegs.h" -+#include "ctrlEnv/sys/mvCpuIfRegs.h" -+ -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+/* locals */ -+ -+/******************************************************************************* -+* mvCpuPclkGet - Get the CPU pClk (pipe clock) -+* -+* DESCRIPTION: -+* This routine extract the CPU core clock. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit clock cycles in MHertz. -+* -+*******************************************************************************/ -+/* 6180 have different clk reset sampling */ -+ -+static MV_U32 mvCpu6180PclkGet(MV_VOID) -+{ -+ MV_U32 tmpPClkRate=0; -+ MV_CPU_ARM_CLK cpu6180_ddr_l2_CLK[] = MV_CPU6180_DDR_L2_CLCK_TBL; -+ -+ tmpPClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ tmpPClkRate = tmpPClkRate & MSAR_CPUCLCK_MASK_6180; -+ tmpPClkRate = tmpPClkRate >> MSAR_CPUCLCK_OFFS_6180; -+ -+ tmpPClkRate = cpu6180_ddr_l2_CLK[tmpPClkRate].cpuClk; -+ -+ return tmpPClkRate; -+} -+ -+ -+MV_U32 mvCpuPclkGet(MV_VOID) -+{ -+#if defined(PCLCK_AUTO_DETECT) -+ MV_U32 tmpPClkRate=0; -+ MV_U32 cpuCLK[] = MV_CPU_CLCK_TBL; -+ -+ if(mvCtrlModelGet() == MV_6180_DEV_ID) -+ return mvCpu6180PclkGet(); -+ -+ tmpPClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ tmpPClkRate = MSAR_CPUCLCK_EXTRACT(tmpPClkRate); -+ tmpPClkRate = cpuCLK[tmpPClkRate]; -+ -+ return tmpPClkRate; -+#else -+ return MV_DEFAULT_PCLK -+#endif -+} -+ -+/******************************************************************************* -+* mvCpuL2ClkGet - Get the CPU L2 (CPU bus clock) -+* -+* DESCRIPTION: -+* This routine extract the CPU L2 clock. -+* -+* RETURN: -+* 32bit clock cycles in Hertz. -+* -+*******************************************************************************/ -+static MV_U32 mvCpu6180L2ClkGet(MV_VOID) -+{ -+ MV_U32 L2ClkRate=0; -+ MV_CPU_ARM_CLK _cpu6180_ddr_l2_CLK[] = MV_CPU6180_DDR_L2_CLCK_TBL; -+ -+ L2ClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ L2ClkRate = L2ClkRate & MSAR_CPUCLCK_MASK_6180; -+ L2ClkRate = L2ClkRate >> MSAR_CPUCLCK_OFFS_6180; -+ -+ L2ClkRate = _cpu6180_ddr_l2_CLK[L2ClkRate].l2Clk; -+ -+ return L2ClkRate; -+ -+} -+ -+MV_U32 mvCpuL2ClkGet(MV_VOID) -+{ -+#ifdef L2CLK_AUTO_DETECT -+ MV_U32 L2ClkRate, tmp, pClkRate, indexL2Rtio; -+ MV_U32 L2Rtio[][2] = MV_L2_CLCK_RTIO_TBL; -+ -+ if(mvCtrlModelGet() == MV_6180_DEV_ID) -+ return mvCpu6180L2ClkGet(); -+ -+ pClkRate = mvCpuPclkGet(); -+ -+ tmp = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ indexL2Rtio = MSAR_L2CLCK_EXTRACT(tmp); -+ -+ L2ClkRate = ((pClkRate * L2Rtio[indexL2Rtio][1]) / L2Rtio[indexL2Rtio][0]); -+ -+ return L2ClkRate; -+#else -+ return MV_BOARD_DEFAULT_L2CLK; -+#endif -+} -+ -+ -+/******************************************************************************* -+* mvCpuNameGet - Get CPU name -+* -+* DESCRIPTION: -+* This function returns a string describing the CPU model and revision. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* pNameBuff - Buffer to contain board name string. Minimum size 32 chars. -+* -+* RETURN: -+* None. -+*******************************************************************************/ -+MV_VOID mvCpuNameGet(char *pNameBuff) -+{ -+ MV_U32 cpuModel; -+ -+ cpuModel = mvOsCpuPartGet(); -+ -+ /* The CPU module is indicated in the Processor Version Register (PVR) */ -+ switch(cpuModel) -+ { -+ case CPU_PART_MRVL131: -+ mvOsSPrintf(pNameBuff, "%s (Rev %d)", "Marvell Feroceon",mvOsCpuRevGet()); -+ break; -+ case CPU_PART_ARM926: -+ mvOsSPrintf(pNameBuff, "%s (Rev %d)", "ARM926",mvOsCpuRevGet()); -+ break; -+ case CPU_PART_ARM946: -+ mvOsSPrintf(pNameBuff, "%s (Rev %d)", "ARM946",mvOsCpuRevGet()); -+ break; -+ default: -+ mvOsSPrintf(pNameBuff,"??? (0x%04x) (Rev %d)",cpuModel,mvOsCpuRevGet()); -+ break; -+ } /* switch */ -+ -+ return; -+} -+ -+ -+#define MV_PROC_STR_SIZE 50 -+ -+static void mvCpuIfGetL2EccMode(MV_8 *buf) -+{ -+ MV_U32 regVal = MV_REG_READ(CPU_L2_CONFIG_REG); -+ if (regVal & BIT2) -+ mvOsSPrintf(buf, "L2 ECC Enabled"); -+ else -+ mvOsSPrintf(buf, "L2 ECC Disabled"); -+} -+ -+static void mvCpuIfGetL2Mode(MV_8 *buf) -+{ -+ MV_U32 regVal = 0; -+ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ -+ if (regVal & BIT22) -+ mvOsSPrintf(buf, "L2 Enabled"); -+ else -+ mvOsSPrintf(buf, "L2 Disabled"); -+} -+ -+static void mvCpuIfGetL2PrefetchMode(MV_8 *buf) -+{ -+ MV_U32 regVal = 0; -+ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ -+ if (regVal & BIT24) -+ mvOsSPrintf(buf, "L2 Prefetch Disabled"); -+ else -+ mvOsSPrintf(buf, "L2 Prefetch Enabled"); -+} -+ -+static void mvCpuIfGetWriteAllocMode(MV_8 *buf) -+{ -+ MV_U32 regVal = 0; -+ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ -+ if (regVal & BIT28) -+ mvOsSPrintf(buf, "Write Allocate Enabled"); -+ else -+ mvOsSPrintf(buf, "Write Allocate Disabled"); -+} -+ -+static void mvCpuIfGetCpuStreamMode(MV_8 *buf) -+{ -+ MV_U32 regVal = 0; -+ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ -+ if (regVal & BIT29) -+ mvOsSPrintf(buf, "CPU Streaming Enabled"); -+ else -+ mvOsSPrintf(buf, "CPU Streaming Disabled"); -+} -+ -+static void mvCpuIfPrintCpuRegs(void) -+{ -+ MV_U32 regVal = 0; -+ -+ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ -+ mvOsPrintf("Extra Feature Reg = 0x%x\n",regVal); -+ -+ __asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (regVal)); /* Read Control register */ -+ mvOsPrintf("Control Reg = 0x%x\n",regVal); -+ -+ __asm volatile ("mrc p15, 0, %0, c0, c0, 0" : "=r" (regVal)); /* Read ID Code register */ -+ mvOsPrintf("ID Code Reg = 0x%x\n",regVal); -+ -+ __asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=r" (regVal)); /* Read Cache Type register */ -+ mvOsPrintf("Cache Type Reg = 0x%x\n",regVal); -+ -+} -+ -+MV_U32 mvCpuIfPrintSystemConfig(MV_8 *buffer, MV_U32 index) -+{ -+ MV_U32 count = 0; -+ -+ MV_8 L2_ECC_str[MV_PROC_STR_SIZE]; -+ MV_8 L2_En_str[MV_PROC_STR_SIZE]; -+ MV_8 L2_Prefetch_str[MV_PROC_STR_SIZE]; -+ MV_8 Write_Alloc_str[MV_PROC_STR_SIZE]; -+ MV_8 Cpu_Stream_str[MV_PROC_STR_SIZE]; -+ -+ mvCpuIfGetL2Mode(L2_En_str); -+ mvCpuIfGetL2EccMode(L2_ECC_str); -+ mvCpuIfGetL2PrefetchMode(L2_Prefetch_str); -+ mvCpuIfGetWriteAllocMode(Write_Alloc_str); -+ mvCpuIfGetCpuStreamMode(Cpu_Stream_str); -+ mvCpuIfPrintCpuRegs(); -+ -+ count += mvOsSPrintf(buffer + count + index, "%s\n", L2_En_str); -+ count += mvOsSPrintf(buffer + count + index, "%s\n", L2_ECC_str); -+ count += mvOsSPrintf(buffer + count + index, "%s\n", L2_Prefetch_str); -+ count += mvOsSPrintf(buffer + count + index, "%s\n", Write_Alloc_str); -+ count += mvOsSPrintf(buffer + count + index, "%s\n", Cpu_Stream_str); -+ return count; -+} -+ -+MV_U32 whoAmI(MV_VOID) -+{ -+ return 0; -+} -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h 2010-11-09 20:28:07.562495452 +0100 -@@ -0,0 +1,99 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvCpuh -+#define __INCmvCpuh -+ -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+ -+/* defines */ -+#define CPU_PART_MRVL131 0x131 -+#define CPU_PART_ARM926 0x926 -+#define CPU_PART_ARM946 0x946 -+#define MV_CPU_ARM_CLK_ELM_SIZE 12 -+#define MV_CPU_ARM_CLK_RATIO_OFF 8 -+#define MV_CPU_ARM_CLK_DDR_OFF 4 -+ -+#ifndef MV_ASMLANGUAGE -+typedef struct _mvCpuArmClk -+{ -+ MV_U32 cpuClk; /* CPU clock in MHz */ -+ MV_U32 ddrClk; /* DDR clock in MHz */ -+ MV_U32 l2Clk; /* CPU DDR clock ratio */ -+ -+}MV_CPU_ARM_CLK; -+ -+MV_U32 mvCpuPclkGet(MV_VOID); -+MV_VOID mvCpuNameGet(char *pNameBuff); -+MV_U32 mvCpuL2ClkGet(MV_VOID); -+MV_U32 mvCpuIfPrintSystemConfig(MV_8 *buffer, MV_U32 index); -+MV_U32 whoAmI(MV_VOID); -+ -+#endif /* MV_ASMLANGUAGE */ -+ -+ -+#endif /* __INCmvCpuh */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c 2010-11-09 20:28:07.602495466 +0100 -@@ -0,0 +1,296 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+/******************************************************************************* -+* mvCtrlEnvAddrDec.h - Marvell controller address decode library -+* -+* DESCRIPTION: -+* -+* DEPENDENCIES: -+* None. -+* -+*******************************************************************************/ -+ -+/* includes */ -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+#include "ctrlEnv/sys/mvAhbToMbusRegs.h" -+#include "ddr2/mvDramIfRegs.h" -+#include "pex/mvPexRegs.h" -+ -+#define MV_DEBUG -+ -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+/* Default Attributes array */ -+MV_TARGET_ATTRIB mvTargetDefaultsArray[] = TARGETS_DEF_ARRAY; -+extern MV_TARGET *sampleAtResetTargetArray; -+/* Dram\AHBToMbus\PEX share regsiter */ -+ -+#define CTRL_DEC_BASE_OFFS 16 -+#define CTRL_DEC_BASE_MASK (0xffff << CTRL_DEC_BASE_OFFS) -+#define CTRL_DEC_BASE_ALIGNMENT 0x10000 -+ -+#define CTRL_DEC_SIZE_OFFS 16 -+#define CTRL_DEC_SIZE_MASK (0xffff << CTRL_DEC_SIZE_OFFS) -+#define CTRL_DEC_SIZE_ALIGNMENT 0x10000 -+ -+#define CTRL_DEC_WIN_EN BIT0 -+ -+ -+ -+/******************************************************************************* -+* mvCtrlAddrDecToReg - Get address decode register format values -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_STATUS mvCtrlAddrDecToReg(MV_ADDR_WIN *pAddrDecWin, MV_DEC_REGS *pAddrDecRegs) -+{ -+ -+ MV_U32 baseToReg=0 , sizeToReg=0; -+ -+ /* BaseLow[31:16] => base register [31:16] */ -+ baseToReg = pAddrDecWin->baseLow & CTRL_DEC_BASE_MASK; -+ -+ /* Write to address decode Base Address Register */ -+ pAddrDecRegs->baseReg &= ~CTRL_DEC_BASE_MASK; -+ pAddrDecRegs->baseReg |= baseToReg; -+ -+ /* Get size register value according to window size */ -+ sizeToReg = ctrlSizeToReg(pAddrDecWin->size, CTRL_DEC_SIZE_ALIGNMENT); -+ -+ /* Size parameter validity check. */ -+ if (-1 == sizeToReg) -+ { -+ return MV_BAD_PARAM; -+ } -+ -+ /* set size */ -+ pAddrDecRegs->sizeReg &= ~CTRL_DEC_SIZE_MASK; -+ pAddrDecRegs->sizeReg |= (sizeToReg << CTRL_DEC_SIZE_OFFS); -+ -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvCtrlRegToAddrDec - Extract address decode struct from registers. -+* -+* DESCRIPTION: -+* This function extract address decode struct from address decode -+* registers given as parameters. -+* -+* INPUT: -+* pAddrDecRegs - Address decode register struct. -+* -+* OUTPUT: -+* pAddrDecWin - Target window data structure. -+* -+* RETURN: -+* MV_BAD_PARAM if address decode registers data is invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvCtrlRegToAddrDec(MV_DEC_REGS *pAddrDecRegs, MV_ADDR_WIN *pAddrDecWin) -+{ -+ MV_U32 sizeRegVal; -+ -+ sizeRegVal = (pAddrDecRegs->sizeReg & CTRL_DEC_SIZE_MASK) >> -+ CTRL_DEC_SIZE_OFFS; -+ -+ pAddrDecWin->size = ctrlRegToSize(sizeRegVal, CTRL_DEC_SIZE_ALIGNMENT); -+ -+ -+ /* Extract base address */ -+ /* Base register [31:16] ==> baseLow[31:16] */ -+ pAddrDecWin->baseLow = pAddrDecRegs->baseReg & CTRL_DEC_BASE_MASK; -+ -+ pAddrDecWin->baseHigh = 0; -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvCtrlAttribGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+* -+*******************************************************************************/ -+ -+MV_STATUS mvCtrlAttribGet(MV_TARGET target, -+ MV_TARGET_ATTRIB *targetAttrib) -+{ -+ -+ targetAttrib->attrib = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].attrib; -+ targetAttrib->targetId = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId; -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvCtrlGetAttrib - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_TARGET mvCtrlTargetGet(MV_TARGET_ATTRIB *targetAttrib) -+{ -+ MV_TARGET target; -+ MV_TARGET x; -+ for (target = SDRAM_CS0; target < MAX_TARGETS ; target ++) -+ { -+ x = MV_CHANGE_BOOT_CS(target); -+ if ((mvTargetDefaultsArray[x].attrib == targetAttrib->attrib) && -+ (mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId == targetAttrib->targetId)) -+ { -+ /* found it */ -+ break; -+ } -+ } -+ -+ return target; -+} -+ -+MV_STATUS mvCtrlAddrDecToParams(MV_DEC_WIN *pAddrDecWin, -+ MV_DEC_WIN_PARAMS *pWinParam) -+{ -+ MV_U32 baseToReg=0, sizeToReg=0; -+ -+ /* BaseLow[31:16] => base register [31:16] */ -+ baseToReg = pAddrDecWin->addrWin.baseLow & CTRL_DEC_BASE_MASK; -+ -+ /* Write to address decode Base Address Register */ -+ pWinParam->baseAddr &= ~CTRL_DEC_BASE_MASK; -+ pWinParam->baseAddr |= baseToReg; -+ -+ /* Get size register value according to window size */ -+ sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, CTRL_DEC_SIZE_ALIGNMENT); -+ -+ /* Size parameter validity check. */ -+ if (-1 == sizeToReg) -+ { -+ mvOsPrintf("mvCtrlAddrDecToParams: ERR. ctrlSizeToReg failed.\n"); -+ return MV_BAD_PARAM; -+ } -+ pWinParam->size = sizeToReg; -+ -+ pWinParam->attrib = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(pAddrDecWin->target)].attrib; -+ pWinParam->targetId = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(pAddrDecWin->target)].targetId; -+ -+ return MV_OK; -+} -+ -+MV_STATUS mvCtrlParamsToAddrDec(MV_DEC_WIN_PARAMS *pWinParam, -+ MV_DEC_WIN *pAddrDecWin) -+{ -+ MV_TARGET_ATTRIB targetAttrib; -+ -+ pAddrDecWin->addrWin.baseLow = pWinParam->baseAddr; -+ -+ /* Upper 32bit address base is supported under PCI High Address remap */ -+ pAddrDecWin->addrWin.baseHigh = 0; -+ -+ /* Prepare sizeReg to ctrlRegToSize function */ -+ pAddrDecWin->addrWin.size = ctrlRegToSize(pWinParam->size, CTRL_DEC_SIZE_ALIGNMENT); -+ -+ if (-1 == pAddrDecWin->addrWin.size) -+ { -+ DB(mvOsPrintf("mvCtrlParamsToAddrDec: ERR. ctrlRegToSize failed.\n")); -+ return MV_BAD_PARAM; -+ } -+ targetAttrib.targetId = pWinParam->targetId; -+ targetAttrib.attrib = pWinParam->attrib; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ return MV_OK; -+} -+ -+ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h 2010-11-09 20:28:07.642495620 +0100 -@@ -0,0 +1,203 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvCtrlEnvAddrDech -+#define __INCmvCtrlEnvAddrDech -+ -+/* includes */ -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvRegs.h" -+ -+ -+/* defines */ -+/* DUnit attributes */ -+#define ATMWCR_WIN_DUNIT_CS0_OFFS 0 -+#define ATMWCR_WIN_DUNIT_CS0_MASK BIT0 -+#define ATMWCR_WIN_DUNIT_CS0_REQ (0 << ATMWCR_WIN_DUNIT_CS0_OFFS) -+ -+#define ATMWCR_WIN_DUNIT_CS1_OFFS 1 -+#define ATMWCR_WIN_DUNIT_CS1_MASK BIT1 -+#define ATMWCR_WIN_DUNIT_CS1_REQ (0 << ATMWCR_WIN_DUNIT_CS1_OFFS) -+ -+#define ATMWCR_WIN_DUNIT_CS2_OFFS 2 -+#define ATMWCR_WIN_DUNIT_CS2_MASK BIT2 -+#define ATMWCR_WIN_DUNIT_CS2_REQ (0 << ATMWCR_WIN_DUNIT_CS2_OFFS) -+ -+#define ATMWCR_WIN_DUNIT_CS3_OFFS 3 -+#define ATMWCR_WIN_DUNIT_CS3_MASK BIT3 -+#define ATMWCR_WIN_DUNIT_CS3_REQ (0 << ATMWCR_WIN_DUNIT_CS3_OFFS) -+ -+/* RUnit (Device) attributes */ -+#define ATMWCR_WIN_RUNIT_DEVCS0_OFFS 0 -+#define ATMWCR_WIN_RUNIT_DEVCS0_MASK BIT0 -+#define ATMWCR_WIN_RUNIT_DEVCS0_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS0_OFFS) -+ -+#define ATMWCR_WIN_RUNIT_DEVCS1_OFFS 1 -+#define ATMWCR_WIN_RUNIT_DEVCS1_MASK BIT1 -+#define ATMWCR_WIN_RUNIT_DEVCS1_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS1_OFFS) -+ -+#define ATMWCR_WIN_RUNIT_DEVCS2_OFFS 2 -+#define ATMWCR_WIN_RUNIT_DEVCS2_MASK BIT2 -+#define ATMWCR_WIN_RUNIT_DEVCS2_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS2_OFFS) -+ -+#define ATMWCR_WIN_RUNIT_BOOTCS_OFFS 4 -+#define ATMWCR_WIN_RUNIT_BOOTCS_MASK BIT4 -+#define ATMWCR_WIN_RUNIT_BOOTCS_REQ (0 << ATMWCR_WIN_RUNIT_BOOTCS_OFFS) -+ -+/* LMaster (PCI) attributes */ -+#define ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS 0 -+#define ATMWCR_WIN_LUNIT_BYTE_SWP_MASK BIT0 -+#define ATMWCR_WIN_LUNIT_BYTE_SWP (0 << ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS) -+#define ATMWCR_WIN_LUNIT_BYTE_NO_SWP (1 << ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS) -+ -+ -+#define ATMWCR_WIN_LUNIT_WORD_SWP_OFFS 1 -+#define ATMWCR_WIN_LUNIT_WORD_SWP_MASK BIT1 -+#define ATMWCR_WIN_LUNIT_WORD_SWP (0 << ATMWCR_WIN_LUNIT_WORD_SWP_OFFS) -+#define ATMWCR_WIN_LUNIT_WORD_NO_SWP (1 << ATMWCR_WIN_LUNIT_WORD_SWP_OFFS) -+ -+#define ATMWCR_WIN_LUNIT_NO_SNOOP BIT2 -+ -+#define ATMWCR_WIN_LUNIT_TYPE_OFFS 3 -+#define ATMWCR_WIN_LUNIT_TYPE_MASK BIT3 -+#define ATMWCR_WIN_LUNIT_TYPE_IO (0 << ATMWCR_WIN_LUNIT_TYPE_OFFS) -+#define ATMWCR_WIN_LUNIT_TYPE_MEM (1 << ATMWCR_WIN_LUNIT_TYPE_OFFS) -+ -+#define ATMWCR_WIN_LUNIT_FORCE64_OFFS 4 -+#define ATMWCR_WIN_LUNIT_FORCE64_MASK BIT4 -+#define ATMWCR_WIN_LUNIT_FORCE64 (0 << ATMWCR_WIN_LUNIT_FORCE64_OFFS) -+ -+#define ATMWCR_WIN_LUNIT_ORDERING_OFFS 6 -+#define ATMWCR_WIN_LUNIT_ORDERING_MASK BIT6 -+#define ATMWCR_WIN_LUNIT_ORDERING (1 << ATMWCR_WIN_LUNIT_FORCE64_OFFS) -+ -+/* PEX Attributes */ -+#define ATMWCR_WIN_PEX_TYPE_OFFS 3 -+#define ATMWCR_WIN_PEX_TYPE_MASK BIT3 -+#define ATMWCR_WIN_PEX_TYPE_IO (0 << ATMWCR_WIN_PEX_TYPE_OFFS) -+#define ATMWCR_WIN_PEX_TYPE_MEM (1 << ATMWCR_WIN_PEX_TYPE_OFFS) -+ -+/* typedefs */ -+ -+/* Unsupported attributes for address decode: */ -+/* 2) PCI0/1_REQ64n control */ -+ -+typedef struct _mvDecRegs -+{ -+ MV_U32 baseReg; -+ MV_U32 baseRegHigh; -+ MV_U32 sizeReg; -+ -+}MV_DEC_REGS; -+ -+typedef struct _mvTargetAttrib -+{ -+ MV_U8 attrib; /* chip select attributes */ -+ MV_TARGET_ID targetId; /* Target Id of this MV_TARGET */ -+ -+}MV_TARGET_ATTRIB; -+ -+ -+/* This structure describes address decode window */ -+typedef struct _mvDecWin -+{ -+ MV_TARGET target; /* Target for addr decode window */ -+ MV_ADDR_WIN addrWin; /* Address window of target */ -+ MV_BOOL enable; /* Window enable/disable */ -+}MV_DEC_WIN; -+ -+typedef struct _mvDecWinParams -+{ -+ MV_TARGET_ID targetId; /* Target ID field */ -+ MV_U8 attrib; /* Attribute field */ -+ MV_U32 baseAddr; /* Base address in register format */ -+ MV_U32 size; /* Size in register format */ -+}MV_DEC_WIN_PARAMS; -+ -+ -+/* mvCtrlEnvAddrDec API list */ -+ -+MV_STATUS mvCtrlAddrDecToReg(MV_ADDR_WIN *pAddrDecWin, -+ MV_DEC_REGS *pAddrDecRegs); -+ -+MV_STATUS mvCtrlRegToAddrDec(MV_DEC_REGS *pAddrDecRegs, -+ MV_ADDR_WIN *pAddrDecWin); -+ -+MV_STATUS mvCtrlAttribGet(MV_TARGET target, -+ MV_TARGET_ATTRIB *targetAttrib); -+ -+MV_TARGET mvCtrlTargetGet(MV_TARGET_ATTRIB *targetAttrib); -+ -+ -+MV_STATUS mvCtrlAddrDecToParams(MV_DEC_WIN *pAddrDecWin, -+ MV_DEC_WIN_PARAMS *pWinParam); -+ -+MV_STATUS mvCtrlParamsToAddrDec(MV_DEC_WIN_PARAMS *pWinParam, -+ MV_DEC_WIN *pAddrDecWin); -+ -+ -+ -+ -+#endif /* __INCmvCtrlEnvAddrDech */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h 2010-11-09 20:28:07.682495401 +0100 -@@ -0,0 +1,98 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvCtrlEnvAsmh -+#define __INCmvCtrlEnvAsmh -+#include "pex/mvPexRegs.h" -+ -+#define CHIP_BOND_REG 0x10034 -+#define PCKG_OPT_MASK_AS #3 -+#define PXCCARI_REVID_MASK_AS #PXCCARI_REVID_MASK -+ -+/* Read device ID into toReg bits 15:0 from 0xd0000000 */ -+/* defines */ -+#define MV_DV_CTRL_MODEL_GET_ASM(toReg, tmpReg) \ -+ MV_DV_REG_READ_ASM(toReg, tmpReg, CHIP_BOND_REG);\ -+ and toReg, toReg, PCKG_OPT_MASK_AS /* Mask for package ID */ -+ -+/* Read device ID into toReg bits 15:0 from 0xf1000000*/ -+#define MV_CTRL_MODEL_GET_ASM(toReg, tmpReg) \ -+ MV_REG_READ_ASM(toReg, tmpReg, CHIP_BOND_REG);\ -+ and toReg, toReg, PCKG_OPT_MASK_AS /* Mask for package ID */ -+ -+/* Read Revision into toReg bits 7:0 0xd0000000*/ -+#define MV_DV_CTRL_REV_GET_ASM(toReg, tmpReg) \ -+ /* Read device revision */ \ -+ MV_DV_REG_READ_ASM(toReg, tmpReg, PEX_CFG_DIRECT_ACCESS(0,PEX_CLASS_CODE_AND_REVISION_ID));\ -+ and toReg, toReg, PXCCARI_REVID_MASK_AS /* Mask for calss ID */ -+ -+/* Read Revision into toReg bits 7:0 0xf1000000*/ -+#define MV_CTRL_REV_GET_ASM(toReg, tmpReg) \ -+ /* Read device revision */ \ -+ MV_REG_READ_ASM(toReg, tmpReg, PEX_CFG_DIRECT_ACCESS(0,PEX_CLASS_CODE_AND_REVISION_ID));\ -+ and toReg, toReg, PXCCARI_REVID_MASK_AS /* Mask for calss ID */ -+ -+ -+#endif /* __INCmvCtrlEnvAsmh */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c 2010-11-09 20:28:07.712495488 +0100 -@@ -0,0 +1,1825 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+/* includes */ -+#include "mvCommon.h" -+#include "mvCtrlEnvLib.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+ -+#if defined(MV_INCLUDE_PEX) -+#include "pex/mvPex.h" -+#include "ctrlEnv/sys/mvSysPex.h" -+#endif -+ -+#if defined(MV_INCLUDE_GIG_ETH) -+#include "ctrlEnv/sys/mvSysGbe.h" -+#endif -+ -+#if defined(MV_INCLUDE_XOR) -+#include "ctrlEnv/sys/mvSysXor.h" -+#endif -+ -+#if defined(MV_INCLUDE_SATA) -+#include "ctrlEnv/sys/mvSysSata.h" -+#endif -+ -+#if defined(MV_INCLUDE_USB) -+#include "ctrlEnv/sys/mvSysUsb.h" -+#endif -+ -+#if defined(MV_INCLUDE_AUDIO) -+#include "ctrlEnv/sys/mvSysAudio.h" -+#endif -+ -+#if defined(MV_INCLUDE_CESA) -+#include "ctrlEnv/sys/mvSysCesa.h" -+#endif -+ -+#if defined(MV_INCLUDE_TS) -+#include "ctrlEnv/sys/mvSysTs.h" -+#endif -+ -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+/******************************************************************************* -+* mvCtrlEnvInit - Initialize Marvell controller environment. -+* -+* DESCRIPTION: -+* This function get environment information and initialize controller -+* internal/external environment. For example -+* 1) MPP settings according to board MPP macros. -+* NOTE: It is the user responsibility to shut down all DMA channels -+* in device and disable controller sub units interrupts during -+* boot process. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvCtrlEnvInit(MV_VOID) -+{ -+ MV_U32 mppGroup; -+ MV_U32 devId; -+ MV_U32 boardId; -+ MV_U32 i; -+ MV_U32 maxMppGrp = 1; -+ MV_U32 mppVal = 0; -+ MV_U32 bootVal = 0; -+ MV_U32 mppGroupType = 0; -+ MV_U32 mppGroup1[][3] = MPP_GROUP_1_TYPE; -+ MV_U32 mppGroup2[][3] = MPP_GROUP_2_TYPE; -+ -+ devId = mvCtrlModelGet(); -+ boardId= mvBoardIdGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ maxMppGrp = MV_6281_MPP_MAX_GROUP; -+ break; -+ case MV_6192_DEV_ID: -+ maxMppGrp = MV_6192_MPP_MAX_GROUP; -+ break; -+ case MV_6190_DEV_ID: -+ maxMppGrp = MV_6190_MPP_MAX_GROUP; -+ break; -+ case MV_6180_DEV_ID: -+ maxMppGrp = MV_6180_MPP_MAX_GROUP; -+ break; -+ } -+ -+ /* MPP Init */ -+ /* We split mpp init to 3 phases: -+ * 1. We init mpp[19:0] from the board info. mpp[23:20] will be over write -+ * in phase 2. -+ * 2. We detect the mpp group type and according the mpp values [35:20]. -+ * 3. We detect the mpp group type and according the mpp values [49:36]. -+ */ -+ /* Mpp phase 1 mpp[19:0] */ -+ /* Read MPP group from board level and assign to MPP register */ -+ for (mppGroup = 0; mppGroup < 3; mppGroup++) -+ { -+ mppVal = mvBoardMppGet(mppGroup); -+ if (mppGroup == 0) -+ { -+ bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); -+ if (mvCtrlIsBootFromSPI()) -+ { -+ mppVal &= ~0xffff; -+ bootVal &= 0xffff; -+ mppVal |= bootVal; -+ } -+ else if (mvCtrlIsBootFromSPIUseNAND()) -+ { -+ mppVal &= ~0xf0000000; -+ bootVal &= 0xf0000000; -+ mppVal |= bootVal; -+ } -+ else if (mvCtrlIsBootFromNAND()) -+ { -+ mppVal &= ~0xffffff; -+ bootVal &= 0xffffff; -+ mppVal |= bootVal; -+ } -+ } -+ -+ if (mppGroup == 2) -+ { -+ bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); -+ if (mvCtrlIsBootFromNAND()) -+ { -+ mppVal &= ~0xff00; -+ bootVal &= 0xff00; -+ mppVal |= bootVal; -+ } -+ } -+ -+ MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal); -+ } -+ -+ /* Identify MPPs group */ -+ mvBoardMppGroupIdUpdate(); -+ -+ /* Update MPPs mux relevent only on Marvell DB */ -+ if ((boardId == DB_88F6281A_BP_ID) || -+ (boardId == DB_88F6180A_BP_ID)) -+ mvBoardMppMuxSet(); -+ -+ mppGroupType = mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_1); -+ -+ /* Mpp phase 2 */ -+ /* Read MPP group from board level and assign to MPP register */ -+ if (devId != MV_6180_DEV_ID) -+ { -+ i = 0; -+ for (mppGroup = 2; mppGroup < 5; mppGroup++) -+ { -+ if ((mppGroupType == MV_BOARD_OTHER) || -+ (boardId == RD_88F6281A_ID) || -+ (boardId == RD_88F6192A_ID) || -+ (boardId == RD_88F6190A_ID) || -+ (boardId == RD_88F6281A_PCAC_ID) || -+ (boardId == SHEEVA_PLUG_ID)) -+ mppVal = mvBoardMppGet(mppGroup); -+ else -+ { -+ mppVal = mppGroup1[mppGroupType][i]; -+ i++; -+ } -+ -+ /* Group 2 is shared mpp[23:16] */ -+ if (mppGroup == 2) -+ { -+ bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); -+ mppVal &= ~0xffff; -+ bootVal &= 0xffff; -+ mppVal |= bootVal; -+ } -+ -+ MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal); -+ } -+ } -+ -+ if ((devId == MV_6192_DEV_ID) || (devId == MV_6190_DEV_ID)) -+ return MV_OK; -+ -+ /* Mpp phase 3 */ -+ mppGroupType = mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_2); -+ /* Read MPP group from board level and assign to MPP register */ -+ i = 0; -+ for (mppGroup = 4; mppGroup < 7; mppGroup++) -+ { -+ if ((mppGroupType == MV_BOARD_OTHER) || -+ (boardId == RD_88F6281A_ID) || -+ (boardId == RD_88F6281A_PCAC_ID) || -+ (boardId == SHEEVA_PLUG_ID)) -+ mppVal = mvBoardMppGet(mppGroup); -+ else -+ { -+ mppVal = mppGroup2[mppGroupType][i]; -+ i++; -+ } -+ -+ /* Group 4 is shared mpp[35:32] */ -+ if (mppGroup == 4) -+ { -+ bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); -+ mppVal &= ~0xffff; -+ bootVal &= 0xffff; -+ mppVal |= bootVal; -+ } -+ -+ MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal); -+ } -+ /* Update SSCG configuration register*/ -+ if(mvBoardIdGet() == DB_88F6281A_BP_ID || mvBoardIdGet() == DB_88F6192A_BP_ID || -+ mvBoardIdGet() == DB_88F6190A_BP_ID || mvBoardIdGet() == DB_88F6180A_BP_ID) -+ MV_REG_WRITE(0x100d8, 0x53); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCtrlMppRegGet - return reg address of mpp group -+* -+* DESCRIPTION: -+* -+* INPUT: -+* mppGroup - MPP group. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_U32 - Register address. -+* -+*******************************************************************************/ -+MV_U32 mvCtrlMppRegGet(MV_U32 mppGroup) -+{ -+ MV_U32 ret; -+ -+ switch(mppGroup){ -+ case (0): ret = MPP_CONTROL_REG0; -+ break; -+ case (1): ret = MPP_CONTROL_REG1; -+ break; -+ case (2): ret = MPP_CONTROL_REG2; -+ break; -+ case (3): ret = MPP_CONTROL_REG3; -+ break; -+ case (4): ret = MPP_CONTROL_REG4; -+ break; -+ case (5): ret = MPP_CONTROL_REG5; -+ break; -+ case (6): ret = MPP_CONTROL_REG6; -+ break; -+ default: ret = MPP_CONTROL_REG0; -+ break; -+ } -+ return ret; -+} -+#if defined(MV_INCLUDE_PEX) -+/******************************************************************************* -+* mvCtrlPexMaxIfGet - Get Marvell controller number of PEX interfaces. -+* -+* DESCRIPTION: -+* This function returns Marvell controller number of PEX interfaces. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Marvell controller number of PEX interfaces. If controller -+* ID is undefined the function returns '0'. -+* -+*******************************************************************************/ -+MV_U32 mvCtrlPexMaxIfGet(MV_VOID) -+{ -+ -+ return MV_PEX_MAX_IF; -+} -+#endif -+ -+#if defined(MV_INCLUDE_GIG_ETH) -+/******************************************************************************* -+* mvCtrlEthMaxPortGet - Get Marvell controller number of etherent ports. -+* -+* DESCRIPTION: -+* This function returns Marvell controller number of etherent port. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Marvell controller number of etherent port. -+* -+*******************************************************************************/ -+MV_U32 mvCtrlEthMaxPortGet(MV_VOID) -+{ -+ MV_U32 devId; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ return MV_6281_ETH_MAX_PORTS; -+ break; -+ case MV_6192_DEV_ID: -+ return MV_6192_ETH_MAX_PORTS; -+ break; -+ case MV_6190_DEV_ID: -+ return MV_6190_ETH_MAX_PORTS; -+ break; -+ case MV_6180_DEV_ID: -+ return MV_6180_ETH_MAX_PORTS; -+ break; -+ } -+ return 0; -+ -+} -+#endif -+ -+#if defined(MV_INCLUDE_XOR) -+/******************************************************************************* -+* mvCtrlXorMaxChanGet - Get Marvell controller number of XOR channels. -+* -+* DESCRIPTION: -+* This function returns Marvell controller number of XOR channels. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Marvell controller number of XOR channels. -+* -+*******************************************************************************/ -+MV_U32 mvCtrlXorMaxChanGet(MV_VOID) -+{ -+ return MV_XOR_MAX_CHAN; -+} -+#endif -+ -+#if defined(MV_INCLUDE_USB) -+/******************************************************************************* -+* mvCtrlUsbHostMaxGet - Get number of Marvell Usb controllers -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* returns number of Marvell USB controllers. -+* -+*******************************************************************************/ -+MV_U32 mvCtrlUsbMaxGet(void) -+{ -+ return MV_USB_MAX_PORTS; -+} -+#endif -+ -+ -+#if defined(MV_INCLUDE_NAND) -+/******************************************************************************* -+* mvCtrlNandSupport - Return if this controller has integrated NAND flash support -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if NAND is supported and MV_FALSE otherwise -+* -+*******************************************************************************/ -+MV_U32 mvCtrlNandSupport(MV_VOID) -+{ -+ MV_U32 devId; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ return MV_6281_NAND; -+ break; -+ case MV_6192_DEV_ID: -+ return MV_6192_NAND; -+ break; -+ case MV_6190_DEV_ID: -+ return MV_6190_NAND; -+ break; -+ case MV_6180_DEV_ID: -+ return MV_6180_NAND; -+ break; -+ } -+ return 0; -+ -+} -+#endif -+ -+#if defined(MV_INCLUDE_SDIO) -+/******************************************************************************* -+* mvCtrlSdioSupport - Return if this controller has integrated SDIO flash support -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if SDIO is supported and MV_FALSE otherwise -+* -+*******************************************************************************/ -+MV_U32 mvCtrlSdioSupport(MV_VOID) -+{ -+ MV_U32 devId; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ return MV_6281_SDIO; -+ break; -+ case MV_6192_DEV_ID: -+ return MV_6192_SDIO; -+ break; -+ case MV_6190_DEV_ID: -+ return MV_6190_SDIO; -+ break; -+ case MV_6180_DEV_ID: -+ return MV_6180_SDIO; -+ break; -+ } -+ return 0; -+ -+} -+#endif -+ -+#if defined(MV_INCLUDE_TS) -+/******************************************************************************* -+* mvCtrlTsSupport - Return if this controller has integrated TS flash support -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if TS is supported and MV_FALSE otherwise -+* -+*******************************************************************************/ -+MV_U32 mvCtrlTsSupport(MV_VOID) -+{ -+ MV_U32 devId; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ return MV_6281_TS; -+ break; -+ case MV_6192_DEV_ID: -+ return MV_6192_TS; -+ break; -+ case MV_6190_DEV_ID: -+ return MV_6190_TS; -+ break; -+ case MV_6180_DEV_ID: -+ return MV_6180_TS; -+ break; -+ } -+ return 0; -+} -+#endif -+ -+#if defined(MV_INCLUDE_AUDIO) -+/******************************************************************************* -+* mvCtrlAudioSupport - Return if this controller has integrated AUDIO flash support -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if AUDIO is supported and MV_FALSE otherwise -+* -+*******************************************************************************/ -+MV_U32 mvCtrlAudioSupport(MV_VOID) -+{ -+ MV_U32 devId; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ return MV_6281_AUDIO; -+ break; -+ case MV_6192_DEV_ID: -+ return MV_6192_AUDIO; -+ break; -+ case MV_6190_DEV_ID: -+ return MV_6190_AUDIO; -+ break; -+ case MV_6180_DEV_ID: -+ return MV_6180_AUDIO; -+ break; -+ } -+ return 0; -+ -+} -+#endif -+ -+#if defined(MV_INCLUDE_TDM) -+/******************************************************************************* -+* mvCtrlTdmSupport - Return if this controller has integrated TDM flash support -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if TDM is supported and MV_FALSE otherwise -+* -+*******************************************************************************/ -+MV_U32 mvCtrlTdmSupport(MV_VOID) -+{ -+ MV_U32 devId; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ return MV_6281_TDM; -+ break; -+ case MV_6192_DEV_ID: -+ return MV_6192_TDM; -+ break; -+ case MV_6190_DEV_ID: -+ return MV_6190_TDM; -+ break; -+ case MV_6180_DEV_ID: -+ return MV_6180_TDM; -+ break; -+ } -+ return 0; -+ -+} -+#endif -+ -+/******************************************************************************* -+* mvCtrlModelGet - Get Marvell controller device model (Id) -+* -+* DESCRIPTION: -+* This function returns 16bit describing the device model (ID) as defined -+* in PCI Device and Vendor ID configuration register offset 0x0. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 16bit desscribing Marvell controller ID -+* -+*******************************************************************************/ -+MV_U16 mvCtrlModelGet(MV_VOID) -+{ -+ MV_U32 devId; -+ -+ devId = MV_REG_READ(CHIP_BOND_REG); -+ devId &= PCKG_OPT_MASK; -+ -+ switch(devId){ -+ case 2: -+ return MV_6281_DEV_ID; -+ break; -+ case 1: -+ if (((MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0,PEX_DEVICE_AND_VENDOR_ID))& 0xffff0000) >> 16) -+ == MV_6190_DEV_ID) -+ return MV_6190_DEV_ID; -+ else -+ return MV_6192_DEV_ID; -+ break; -+ case 0: -+ return MV_6180_DEV_ID; -+ break; -+ } -+ -+ return 0; -+} -+/******************************************************************************* -+* mvCtrlRevGet - Get Marvell controller device revision number -+* -+* DESCRIPTION: -+* This function returns 8bit describing the device revision as defined -+* in PCI Express Class Code and Revision ID Register. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 8bit desscribing Marvell controller revision number -+* -+*******************************************************************************/ -+MV_U8 mvCtrlRevGet(MV_VOID) -+{ -+ MV_U8 revNum; -+#if defined(MV_INCLUDE_CLK_PWR_CNTRL) -+ /* Check pex power state */ -+ MV_U32 pexPower; -+ pexPower = mvCtrlPwrClckGet(PEX_UNIT_ID,0); -+ if (pexPower == MV_FALSE) -+ mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_TRUE); -+#endif -+ revNum = (MV_U8)MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0,PCI_CLASS_CODE_AND_REVISION_ID)); -+#if defined(MV_INCLUDE_CLK_PWR_CNTRL) -+ /* Return to power off state */ -+ if (pexPower == MV_FALSE) -+ mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_FALSE); -+#endif -+ return ((revNum & PCCRIR_REVID_MASK) >> PCCRIR_REVID_OFFS); -+} -+ -+/******************************************************************************* -+* mvCtrlNameGet - Get Marvell controller name -+* -+* DESCRIPTION: -+* This function returns a string describing the device model and revision. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* pNameBuff - Buffer to contain device name string. Minimum size 30 chars. -+* -+* RETURN: -+* -+* MV_ERROR if informantion can not be read. -+*******************************************************************************/ -+MV_STATUS mvCtrlNameGet(char *pNameBuff) -+{ -+ mvOsSPrintf (pNameBuff, "%s%x Rev %d", SOC_NAME_PREFIX, -+ mvCtrlModelGet(), mvCtrlRevGet()); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCtrlModelRevGet - Get Controller Model (Device ID) and Revision -+* -+* DESCRIPTION: -+* This function returns 32bit value describing both Device ID and Revision -+* as defined in PCI Express Device and Vendor ID Register and device revision -+* as defined in PCI Express Class Code and Revision ID Register. -+ -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit describing both controller device ID and revision number -+* -+*******************************************************************************/ -+MV_U32 mvCtrlModelRevGet(MV_VOID) -+{ -+ return ((mvCtrlModelGet() << 16) | mvCtrlRevGet()); -+} -+ -+/******************************************************************************* -+* mvCtrlModelRevNameGet - Get Marvell controller name -+* -+* DESCRIPTION: -+* This function returns a string describing the device model and revision. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* pNameBuff - Buffer to contain device name string. Minimum size 30 chars. -+* -+* RETURN: -+* -+* MV_ERROR if informantion can not be read. -+*******************************************************************************/ -+ -+MV_STATUS mvCtrlModelRevNameGet(char *pNameBuff) -+{ -+ -+ switch (mvCtrlModelRevGet()) -+ { -+ case MV_6281_A0_ID: -+ mvOsSPrintf (pNameBuff, "%s",MV_6281_A0_NAME); -+ break; -+ case MV_6192_A0_ID: -+ mvOsSPrintf (pNameBuff, "%s",MV_6192_A0_NAME); -+ break; -+ case MV_6180_A0_ID: -+ mvOsSPrintf (pNameBuff, "%s",MV_6180_A0_NAME); -+ break; -+ case MV_6190_A0_ID: -+ mvOsSPrintf (pNameBuff, "%s",MV_6190_A0_NAME); -+ break; -+ case MV_6281_A1_ID: -+ mvOsSPrintf (pNameBuff, "%s",MV_6281_A1_NAME); -+ break; -+ case MV_6192_A1_ID: -+ mvOsSPrintf (pNameBuff, "%s",MV_6192_A1_NAME); -+ break; -+ case MV_6180_A1_ID: -+ mvOsSPrintf (pNameBuff, "%s",MV_6180_A1_NAME); -+ break; -+ case MV_6190_A1_ID: -+ mvOsSPrintf (pNameBuff, "%s",MV_6190_A1_NAME); -+ break; -+ default: -+ mvCtrlNameGet(pNameBuff); -+ break; -+ } -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* ctrlWinOverlapTest - Test address windows for overlaping. -+* -+* DESCRIPTION: -+* This function checks the given two address windows for overlaping. -+* -+* INPUT: -+* pAddrWin1 - Address window 1. -+* pAddrWin2 - Address window 2. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* MV_TRUE if address window overlaps, MV_FALSE otherwise. -+*******************************************************************************/ -+MV_STATUS ctrlWinOverlapTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2) -+{ -+ MV_U32 winBase1, winBase2; -+ MV_U32 winTop1, winTop2; -+ -+ /* check if we have overflow than 4G*/ -+ if (((0xffffffff - pAddrWin1->baseLow) < pAddrWin1->size-1)|| -+ ((0xffffffff - pAddrWin2->baseLow) < pAddrWin2->size-1)) -+ { -+ return MV_TRUE; -+ } -+ -+ winBase1 = pAddrWin1->baseLow; -+ winBase2 = pAddrWin2->baseLow; -+ winTop1 = winBase1 + pAddrWin1->size-1; -+ winTop2 = winBase2 + pAddrWin2->size-1; -+ -+ -+ if (((winBase1 <= winTop2 ) && ( winTop2 <= winTop1)) || -+ ((winBase1 <= winBase2) && (winBase2 <= winTop1))) -+ { -+ return MV_TRUE; -+ } -+ else -+ { -+ return MV_FALSE; -+ } -+} -+ -+/******************************************************************************* -+* ctrlWinWithinWinTest - Test address windows for overlaping. -+* -+* DESCRIPTION: -+* This function checks the given win1 boundries is within -+* win2 boundries. -+* -+* INPUT: -+* pAddrWin1 - Address window 1. -+* pAddrWin2 - Address window 2. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* MV_TRUE if found win1 inside win2, MV_FALSE otherwise. -+*******************************************************************************/ -+MV_STATUS ctrlWinWithinWinTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2) -+{ -+ MV_U32 winBase1, winBase2; -+ MV_U32 winTop1, winTop2; -+ -+ winBase1 = pAddrWin1->baseLow; -+ winBase2 = pAddrWin2->baseLow; -+ winTop1 = winBase1 + pAddrWin1->size -1; -+ winTop2 = winBase2 + pAddrWin2->size -1; -+ -+ if (((winBase1 >= winBase2 ) && ( winBase1 <= winTop2)) || -+ ((winTop1 >= winBase2) && (winTop1 <= winTop2))) -+ { -+ return MV_TRUE; -+ } -+ else -+ { -+ return MV_FALSE; -+ } -+} -+ -+static const char* cntrlName[] = TARGETS_NAME_ARRAY; -+ -+/******************************************************************************* -+* mvCtrlTargetNameGet - Get Marvell controller target name -+* -+* DESCRIPTION: -+* This function convert the trget enumeration to string. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Target name (const MV_8 *) -+*******************************************************************************/ -+const MV_8* mvCtrlTargetNameGet( MV_TARGET target ) -+{ -+ -+ if (target >= MAX_TARGETS) -+ { -+ return "target unknown"; -+ } -+ -+ return cntrlName[target]; -+} -+ -+/******************************************************************************* -+* mvCtrlAddrDecShow - Print the Controller units address decode map. -+* -+* DESCRIPTION: -+* This function the Controller units address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvCtrlAddrDecShow(MV_VOID) -+{ -+ mvCpuIfAddDecShow(); -+ mvAhbToMbusAddDecShow(); -+#if defined(MV_INCLUDE_PEX) -+ mvPexAddrDecShow(); -+#endif -+#if defined(MV_INCLUDE_USB) -+ mvUsbAddrDecShow(); -+#endif -+#if defined(MV_INCLUDE_GIG_ETH) -+ mvEthAddrDecShow(); -+#endif -+#if defined(MV_INCLUDE_XOR) -+ mvXorAddrDecShow(); -+#endif -+#if defined(MV_INCLUDE_SATA) -+ mvSataAddrDecShow(); -+#endif -+#if defined(MV_INCLUDE_AUDIO) -+ mvAudioAddrDecShow(); -+#endif -+#if defined(MV_INCLUDE_TS) -+ mvTsuAddrDecShow(); -+#endif -+} -+ -+/******************************************************************************* -+* ctrlSizeToReg - Extract size value for register assignment. -+* -+* DESCRIPTION: -+* Address decode size parameter must be programed from LSB to MSB as -+* sequence of 1's followed by sequence of 0's. The number of 1's -+* specifies the size of the window in 64 KB granularity (e.g. a -+* value of 0x00ff specifies 256x64k = 16 MB). -+* This function extract the size value from the size parameter according -+* to given aligment paramter. For example for size 0x1000000 (16MB) and -+* aligment 0x10000 (64KB) the function will return 0x00FF. -+* -+* INPUT: -+* size - Size. -+* alignment - Size alignment. Note that alignment must be power of 2! -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit describing size register value correspond to size parameter. -+* If value is '-1' size parameter or aligment are invalid. -+*******************************************************************************/ -+MV_U32 ctrlSizeToReg(MV_U32 size, MV_U32 alignment) -+{ -+ MV_U32 retVal; -+ -+ /* Check size parameter alignment */ -+ if ((0 == size) || (MV_IS_NOT_ALIGN(size, alignment))) -+ { -+ DB(mvOsPrintf("ctrlSizeToReg: ERR. Size is zero or not aligned.\n")); -+ return -1; -+ } -+ -+ /* Take out the "alignment" portion out of the size parameter */ -+ alignment--; /* Now the alignmet is a sequance of '1' (e.g. 0xffff) */ -+ /* and size is 0x1000000 (16MB) for example */ -+ while(alignment & 1) /* Check that alignmet LSB is set */ -+ { -+ size = (size >> 1); /* If LSB is set, move 'size' one bit to right */ -+ alignment = (alignment >> 1); -+ } -+ -+ /* If after the alignment first '0' was met we still have '1' in */ -+ /* it then aligment is invalid (not power of 2) */ -+ if (alignment) -+ { -+ DB(mvOsPrintf("ctrlSizeToReg: ERR. Alignment parameter 0x%x invalid.\n", -+ (MV_U32)alignment)); -+ return -1; -+ } -+ -+ /* Now the size is shifted right according to aligment: 0x0100 */ -+ size--; /* Now the size is a sequance of '1': 0x00ff */ -+ -+ retVal = size ; -+ -+ /* Check that LSB to MSB is sequence of 1's followed by sequence of 0's */ -+ while(size & 1) /* Check that LSB is set */ -+ { -+ size = (size >> 1); /* If LSB is set, move one bit to the right */ -+ } -+ -+ if (size) /* Sequance of 1's is over. Check that we have no other 1's */ -+ { -+ DB(mvOsPrintf("ctrlSizeToReg: ERR. Size parameter 0x%x invalid.\n", -+ size)); -+ return -1; -+ } -+ -+ return retVal; -+ -+} -+ -+/******************************************************************************* -+* ctrlRegToSize - Extract size value from register value. -+* -+* DESCRIPTION: -+* This function extract a size value from the register size parameter -+* according to given aligment paramter. For example for register size -+* value 0xff and aligment 0x10000 the function will return 0x01000000. -+* -+* INPUT: -+* regSize - Size as in register format. See ctrlSizeToReg. -+* alignment - Size alignment. Note that alignment must be power of 2! -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit describing size. -+* If value is '-1' size parameter or aligment are invalid. -+*******************************************************************************/ -+MV_U32 ctrlRegToSize(MV_U32 regSize, MV_U32 alignment) -+{ -+ MV_U32 temp; -+ -+ /* Check that LSB to MSB is sequence of 1's followed by sequence of 0's */ -+ temp = regSize; /* Now the size is a sequance of '1': 0x00ff */ -+ -+ while(temp & 1) /* Check that LSB is set */ -+ { -+ temp = (temp >> 1); /* If LSB is set, move one bit to the right */ -+ } -+ -+ if (temp) /* Sequance of 1's is over. Check that we have no other 1's */ -+ { -+ DB(mvOsPrintf("ctrlRegToSize: ERR. Size parameter 0x%x invalid.\n", -+ regSize)); -+ return -1; -+ } -+ -+ -+ /* Check that aligment is a power of two */ -+ temp = alignment - 1;/* Now the alignmet is a sequance of '1' (0xffff) */ -+ -+ while(temp & 1) /* Check that alignmet LSB is set */ -+ { -+ temp = (temp >> 1); /* If LSB is set, move 'size' one bit to right */ -+ } -+ -+ /* If after the 'temp' first '0' was met we still have '1' in 'temp' */ -+ /* then 'temp' is invalid (not power of 2) */ -+ if (temp) -+ { -+ DB(mvOsPrintf("ctrlSizeToReg: ERR. Alignment parameter 0x%x invalid.\n", -+ alignment)); -+ return -1; -+ } -+ -+ regSize++; /* Now the size is 0x0100 */ -+ -+ /* Add in the "alignment" portion to the register size parameter */ -+ alignment--; /* Now the alignmet is a sequance of '1' (e.g. 0xffff) */ -+ -+ while(alignment & 1) /* Check that alignmet LSB is set */ -+ { -+ regSize = (regSize << 1); /* LSB is set, move 'size' one bit left */ -+ alignment = (alignment >> 1); -+ } -+ -+ return regSize; -+} -+ -+ -+/******************************************************************************* -+* ctrlSizeRegRoundUp - Round up given size -+* -+* DESCRIPTION: -+* This function round up a given size to a size that fits the -+* restrictions of size format given an aligment parameter. -+* to given aligment paramter. For example for size parameter 0xa1000 and -+* aligment 0x1000 the function will return 0xFF000. -+* -+* INPUT: -+* size - Size. -+* alignment - Size alignment. Note that alignment must be power of 2! -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit describing size value correspond to size in register. -+*******************************************************************************/ -+MV_U32 ctrlSizeRegRoundUp(MV_U32 size, MV_U32 alignment) -+{ -+ MV_U32 msbBit = 0; -+ MV_U32 retSize; -+ -+ /* Check if size parameter is already comply with restriction */ -+ if (!(-1 == ctrlSizeToReg(size, alignment))) -+ { -+ return size; -+ } -+ -+ while(size) -+ { -+ size = (size >> 1); -+ msbBit++; -+ } -+ -+ retSize = (1 << msbBit); -+ -+ if (retSize < alignment) -+ { -+ return alignment; -+ } -+ else -+ { -+ return retSize; -+ } -+} -+/******************************************************************************* -+* mvCtrlSysRstLengthCounterGet - Return number of milliseconds the reset button -+* was pressed and clear counter -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: number of milliseconds the reset button was pressed -+*******************************************************************************/ -+MV_U32 mvCtrlSysRstLengthCounterGet(MV_VOID) -+{ -+ static volatile MV_U32 Count = 0; -+ -+ if(!Count) { -+ Count = (MV_REG_READ(SYSRST_LENGTH_COUNTER_REG) & SLCR_COUNT_MASK); -+ Count = (Count / (MV_BOARD_REFCLK_25MHZ / 1000)); -+ /* clear counter for next boot */ -+ MV_REG_BIT_SET(SYSRST_LENGTH_COUNTER_REG, SLCR_CLR_MASK); -+ } -+ -+ DB(mvOsPrintf("mvCtrlSysRstLengthCounterGet: Reset button was pressed for %u milliseconds\n", Count)); -+ -+ return Count; -+} -+ -+MV_BOOL mvCtrlIsBootFromSPI(MV_VOID) -+{ -+ MV_U32 satr = 0; -+ satr = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ if(mvCtrlModelGet() == MV_6180_DEV_ID) -+ { -+ if (MSAR_BOOT_MODE_6180(satr) == MSAR_BOOT_SPI_WITH_BOOTROM_6180) -+ return MV_TRUE; -+ else -+ return MV_FALSE; -+ } -+ satr = satr & MSAR_BOOT_MODE_MASK; -+ if (satr == MSAR_BOOT_SPI_WITH_BOOTROM) -+ return MV_TRUE; -+ else -+ return MV_FALSE; -+} -+ -+MV_BOOL mvCtrlIsBootFromSPIUseNAND(MV_VOID) -+{ -+ MV_U32 satr = 0; -+ if(mvCtrlModelGet() == MV_6180_DEV_ID) -+ return MV_FALSE; -+ satr = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ satr = satr & MSAR_BOOT_MODE_MASK; -+ -+ if (satr == MSAR_BOOT_SPI_USE_NAND_WITH_BOOTROM) -+ return MV_TRUE; -+ else -+ return MV_FALSE; -+} -+ -+MV_BOOL mvCtrlIsBootFromNAND(MV_VOID) -+{ -+ MV_U32 satr = 0; -+ satr = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ if(mvCtrlModelGet() == MV_6180_DEV_ID) -+ { -+ if (MSAR_BOOT_MODE_6180(satr) == MSAR_BOOT_NAND_WITH_BOOTROM_6180) -+ return MV_TRUE; -+ else -+ return MV_FALSE; -+ } -+ satr = satr & MSAR_BOOT_MODE_MASK; -+ if ((satr == MSAR_BOOT_NAND_WITH_BOOTROM)) -+ return MV_TRUE; -+ else -+ return MV_FALSE; -+} -+ -+#if defined(MV_INCLUDE_CLK_PWR_CNTRL) -+/******************************************************************************* -+* mvCtrlPwrSaveOn - Set Power save mode -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+*******************************************************************************/ -+MV_VOID mvCtrlPwrSaveOn(MV_VOID) -+{ -+ unsigned long old,temp; -+ /* Disable int */ -+ __asm__ __volatile__("mrs %0, cpsr\n" -+ "orr %1, %0, #0xc0\n" -+ "msr cpsr_c, %1" -+ : "=r" (old), "=r" (temp) -+ : -+ : "memory"); -+ -+ /* Set SoC in power save */ -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, BIT11); -+ /* Wait for int */ -+ __asm__ __volatile__("mcr p15, 0, r0, c7, c0, 4"); -+ -+ /* Enabled int */ -+ __asm__ __volatile__("msr cpsr_c, %0" -+ : -+ : "r" (old) -+ : "memory"); -+} -+ -+ -+ -+/******************************************************************************* -+* mvCtrlPwrSaveOff - Go out of power save mode -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+*******************************************************************************/ -+MV_VOID mvCtrlPwrSaveOff(MV_VOID) -+{ -+ unsigned long old,temp; -+ /* Disable int */ -+ __asm__ __volatile__("mrs %0, cpsr\n" -+ "orr %1, %0, #0xc0\n" -+ "msr cpsr_c, %1" -+ : "=r" (old), "=r" (temp) -+ : -+ : "memory"); -+ -+ /* Set SoC in power save */ -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, BIT11); -+ /* Wait for int */ -+ __asm__ __volatile__("mcr p15, 0, r0, c7, c0, 4"); -+ -+ /* Enabled int */ -+ __asm__ __volatile__("msr cpsr_c, %0" -+ : -+ : "r" (old) -+ : "memory"); -+} -+ -+/******************************************************************************* -+* mvCtrlPwrClckSet - Set Power State for specific Unit -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+*******************************************************************************/ -+MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) -+{ -+ switch (unitId) -+ { -+#if defined(MV_INCLUDE_PEX) -+ case PEX_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_PEXSTOPCLOCK_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_PEXSTOPCLOCK_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_GIG_ETH) -+ case ETH_GIG_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_GESTOPCLOCK_MASK(index)); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_GESTOPCLOCK_MASK(index)); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_INTEG_SATA) -+ case SATA_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SATASTOPCLOCK_MASK(index)); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SATASTOPCLOCK_MASK(index)); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_CESA) -+ case CESA_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SESTOPCLOCK_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SESTOPCLOCK_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_USB) -+ case USB_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_USBSTOPCLOCK_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_USBSTOPCLOCK_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_AUDIO) -+ case AUDIO_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_AUDIOSTOPCLOCK_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_AUDIOSTOPCLOCK_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_TS) -+ case TS_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_TSSTOPCLOCK_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_TSSTOPCLOCK_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_SDIO) -+ case SDIO_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SDIOSTOPCLOCK_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SDIOSTOPCLOCK_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_TDM) -+ case TDM_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_TDMSTOPCLOCK_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_TDMSTOPCLOCK_MASK); -+ } -+ break; -+#endif -+ -+ default: -+ -+ break; -+ -+ } -+} -+ -+/******************************************************************************* -+* mvCtrlPwrClckGet - Get Power State of specific Unit -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+******************************************************************************/ -+MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index) -+{ -+ MV_U32 reg = MV_REG_READ(POWER_MNG_CTRL_REG); -+ MV_BOOL state = MV_TRUE; -+ -+ switch (unitId) -+ { -+#if defined(MV_INCLUDE_PEX) -+ case PEX_UNIT_ID: -+ if ((reg & PMC_PEXSTOPCLOCK_MASK) == PMC_PEXSTOPCLOCK_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ -+ break; -+#endif -+#if defined(MV_INCLUDE_GIG_ETH) -+ case ETH_GIG_UNIT_ID: -+ if ((reg & PMC_GESTOPCLOCK_MASK(index)) == PMC_GESTOPCLOCK_STOP(index)) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_SATA) -+ case SATA_UNIT_ID: -+ if ((reg & PMC_SATASTOPCLOCK_MASK(index)) == PMC_SATASTOPCLOCK_STOP(index)) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_CESA) -+ case CESA_UNIT_ID: -+ if ((reg & PMC_SESTOPCLOCK_MASK) == PMC_SESTOPCLOCK_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_USB) -+ case USB_UNIT_ID: -+ if ((reg & PMC_USBSTOPCLOCK_MASK) == PMC_USBSTOPCLOCK_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_AUDIO) -+ case AUDIO_UNIT_ID: -+ if ((reg & PMC_AUDIOSTOPCLOCK_MASK) == PMC_AUDIOSTOPCLOCK_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_TS) -+ case TS_UNIT_ID: -+ if ((reg & PMC_TSSTOPCLOCK_MASK) == PMC_TSSTOPCLOCK_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_SDIO) -+ case SDIO_UNIT_ID: -+ if ((reg & PMC_SDIOSTOPCLOCK_MASK)== PMC_SDIOSTOPCLOCK_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_TDM) -+ case TDM_UNIT_ID: -+ if ((reg & PMC_TDMSTOPCLOCK_MASK) == PMC_TDMSTOPCLOCK_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+ -+ default: -+ state = MV_TRUE; -+ break; -+ } -+ -+ -+ return state; -+} -+/******************************************************************************* -+* mvCtrlPwrMemSet - Set Power State for memory on specific Unit -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+*******************************************************************************/ -+MV_VOID mvCtrlPwrMemSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) -+{ -+ switch (unitId) -+ { -+#if defined(MV_INCLUDE_PEX) -+ case PEX_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_PEXSTOPMEM_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_PEXSTOPMEM_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_GIG_ETH) -+ case ETH_GIG_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_GESTOPMEM_MASK(index)); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_GESTOPMEM_MASK(index)); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_INTEG_SATA) -+ case SATA_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_SATASTOPMEM_MASK(index)); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_SATASTOPMEM_MASK(index)); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_CESA) -+ case CESA_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_SESTOPMEM_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_SESTOPMEM_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_USB) -+ case USB_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_USBSTOPMEM_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_USBSTOPMEM_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_AUDIO) -+ case AUDIO_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_AUDIOSTOPMEM_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_AUDIOSTOPMEM_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_XOR) -+ case XOR_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_XORSTOPMEM_MASK(index)); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_XORSTOPMEM_MASK(index)); -+ } -+ break; -+#endif -+ default: -+ -+ break; -+ -+ } -+} -+ -+/******************************************************************************* -+* mvCtrlPwrMemGet - Get Power State of memory on specific Unit -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+******************************************************************************/ -+MV_BOOL mvCtrlPwrMemGet(MV_UNIT_ID unitId, MV_U32 index) -+{ -+ MV_U32 reg = MV_REG_READ(POWER_MNG_MEM_CTRL_REG); -+ MV_BOOL state = MV_TRUE; -+ -+ switch (unitId) -+ { -+#if defined(MV_INCLUDE_PEX) -+ case PEX_UNIT_ID: -+ if ((reg & PMC_PEXSTOPMEM_MASK) == PMC_PEXSTOPMEM_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ -+ break; -+#endif -+#if defined(MV_INCLUDE_GIG_ETH) -+ case ETH_GIG_UNIT_ID: -+ if ((reg & PMC_GESTOPMEM_MASK(index)) == PMC_GESTOPMEM_STOP(index)) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_SATA) -+ case SATA_UNIT_ID: -+ if ((reg & PMC_SATASTOPMEM_MASK(index)) == PMC_SATASTOPMEM_STOP(index)) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_CESA) -+ case CESA_UNIT_ID: -+ if ((reg & PMC_SESTOPMEM_MASK) == PMC_SESTOPMEM_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_USB) -+ case USB_UNIT_ID: -+ if ((reg & PMC_USBSTOPMEM_MASK) == PMC_USBSTOPMEM_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_AUDIO) -+ case AUDIO_UNIT_ID: -+ if ((reg & PMC_AUDIOSTOPMEM_MASK) == PMC_AUDIOSTOPMEM_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_XOR) -+ case XOR_UNIT_ID: -+ if ((reg & PMC_XORSTOPMEM_MASK(index)) == PMC_XORSTOPMEM_STOP(index)) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+ -+ default: -+ state = MV_TRUE; -+ break; -+ } -+ -+ -+ return state; -+} -+#else -+MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) {return;} -+MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index) {return MV_TRUE;} -+#endif /* #if defined(MV_INCLUDE_CLK_PWR_CNTRL) */ -+ -+ -+/******************************************************************************* -+* mvMPPConfigToSPI - Change MPP[3:0] configuration to SPI mode -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+******************************************************************************/ -+MV_VOID mvMPPConfigToSPI(MV_VOID) -+{ -+ MV_U32 mppVal = 0; -+ MV_U32 bootVal = 0; -+ -+ if(!mvCtrlIsBootFromSPIUseNAND()) -+ return; -+ mppVal = 0x00002220; /* Set MPP [3:1] to SPI mode */ -+ bootVal = MV_REG_READ(mvCtrlMppRegGet(0)); -+ bootVal &= 0xffff000f; -+ mppVal |= bootVal; -+ -+ MV_REG_WRITE(mvCtrlMppRegGet(0), mppVal); -+} -+ -+ -+/******************************************************************************* -+* mvMPPConfigToDefault - Change MPP[7:0] configuration to default configuration -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+******************************************************************************/ -+MV_VOID mvMPPConfigToDefault(MV_VOID) -+{ -+ MV_U32 mppVal = 0; -+ MV_U32 bootVal = 0; -+ -+ if(!mvCtrlIsBootFromSPIUseNAND()) -+ return; -+ mppVal = mvBoardMppGet(0); -+ bootVal = MV_REG_READ(mvCtrlMppRegGet(0)); -+ mppVal &= ~0xffff000f; -+ bootVal &= 0xffff000f; -+ mppVal |= bootVal; -+ -+ MV_REG_WRITE(mvCtrlMppRegGet(0), mppVal); -+} -+ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h 2010-11-09 20:28:07.742495476 +0100 -@@ -0,0 +1,185 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvCtrlEnvLibh -+#define __INCmvCtrlEnvLibh -+ -+/* includes */ -+#include "mvSysHwConfig.h" -+#include "mvCommon.h" -+#include "mvTypes.h" -+#include "mvOs.h" -+#include "boardEnv/mvBoardEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+#include "ctrlEnv/mvCtrlEnvRegs.h" -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+ -+ -+/* typedefs */ -+ -+/* This enumerator describes the possible HW cache coherency policies the */ -+/* controllers supports. */ -+typedef enum _mvCachePolicy -+{ -+ NO_COHERENCY, /* No HW cache coherency support */ -+ WT_COHERENCY, /* HW cache coherency supported in Write Through policy */ -+ WB_COHERENCY /* HW cache coherency supported in Write Back policy */ -+}MV_CACHE_POLICY; -+ -+ -+/* The swapping is referred to a 64-bit words (as this is the controller */ -+/* internal data path width). This enumerator describes the possible */ -+/* data swap types. Below is an example of the data 0x0011223344556677 */ -+typedef enum _mvSwapType -+{ -+ MV_BYTE_SWAP, /* Byte Swap 77 66 55 44 33 22 11 00 */ -+ MV_NO_SWAP, /* No swapping 00 11 22 33 44 55 66 77 */ -+ MV_BYTE_WORD_SWAP, /* Both byte and word swap 33 22 11 00 77 66 55 44 */ -+ MV_WORD_SWAP, /* Word swap 44 55 66 77 00 11 22 33 */ -+ SWAP_TYPE_MAX /* Delimiter for this enumerator */ -+}MV_SWAP_TYPE; -+ -+/* This structure describes access rights for Access protection windows */ -+/* that can be found in IDMA, XOR, Ethernet and MPSC units. */ -+/* Note that the permission enumerator coresponds to its register format. */ -+/* For example, Read only premission is presented as "1" in register field. */ -+typedef enum _mvAccessRights -+{ -+ NO_ACCESS_ALLOWED = 0, /* No access allowed */ -+ READ_ONLY = 1, /* Read only permission */ -+ ACC_RESERVED = 2, /* Reserved access right */ -+ FULL_ACCESS = 3, /* Read and Write permission */ -+ MAX_ACC_RIGHTS -+}MV_ACCESS_RIGHTS; -+ -+ -+/* mcspLib.h API list */ -+ -+MV_STATUS mvCtrlEnvInit(MV_VOID); -+MV_U32 mvCtrlMppRegGet(MV_U32 mppGroup); -+ -+#if defined(MV_INCLUDE_PEX) -+MV_U32 mvCtrlPexMaxIfGet(MV_VOID); -+#else -+#define mvCtrlPexMaxIfGet() (0) -+#endif -+ -+#define mvCtrlPciIfMaxIfGet() (0) -+ -+#if defined(MV_INCLUDE_GIG_ETH) -+MV_U32 mvCtrlEthMaxPortGet(MV_VOID); -+#endif -+#if defined(MV_INCLUDE_XOR) -+MV_U32 mvCtrlXorMaxChanGet(MV_VOID); -+#endif -+#if defined(MV_INCLUDE_USB) -+MV_U32 mvCtrlUsbMaxGet(MV_VOID); -+#endif -+#if defined(MV_INCLUDE_NAND) -+MV_U32 mvCtrlNandSupport(MV_VOID); -+#endif -+#if defined(MV_INCLUDE_SDIO) -+MV_U32 mvCtrlSdioSupport(MV_VOID); -+#endif -+#if defined(MV_INCLUDE_TS) -+MV_U32 mvCtrlTsSupport(MV_VOID); -+#endif -+#if defined(MV_INCLUDE_AUDIO) -+MV_U32 mvCtrlAudioSupport(MV_VOID); -+#endif -+#if defined(MV_INCLUDE_TDM) -+MV_U32 mvCtrlTdmSupport(MV_VOID); -+#endif -+ -+MV_U16 mvCtrlModelGet(MV_VOID); -+MV_U8 mvCtrlRevGet(MV_VOID); -+MV_STATUS mvCtrlNameGet(char *pNameBuff); -+MV_U32 mvCtrlModelRevGet(MV_VOID); -+MV_STATUS mvCtrlModelRevNameGet(char *pNameBuff); -+MV_VOID mvCtrlAddrDecShow(MV_VOID); -+const MV_8* mvCtrlTargetNameGet(MV_TARGET target); -+MV_U32 ctrlSizeToReg(MV_U32 size, MV_U32 alignment); -+MV_U32 ctrlRegToSize(MV_U32 regSize, MV_U32 alignment); -+MV_U32 ctrlSizeRegRoundUp(MV_U32 size, MV_U32 alignment); -+MV_U32 mvCtrlSysRstLengthCounterGet(MV_VOID); -+MV_STATUS ctrlWinOverlapTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2); -+MV_STATUS ctrlWinWithinWinTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2); -+ -+MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable); -+MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index); -+MV_VOID mvCtrlPwrMemSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable); -+MV_BOOL mvCtrlIsBootFromSPI(MV_VOID); -+MV_BOOL mvCtrlIsBootFromSPIUseNAND(MV_VOID); -+MV_BOOL mvCtrlIsBootFromNAND(MV_VOID); -+#if defined(MV_INCLUDE_CLK_PWR_CNTRL) -+MV_VOID mvCtrlPwrSaveOn(MV_VOID); -+MV_VOID mvCtrlPwrSaveOff(MV_VOID); -+#endif -+MV_BOOL mvCtrlPwrMemGet(MV_UNIT_ID unitId, MV_U32 index); -+MV_VOID mvMPPConfigToSPI(MV_VOID); -+MV_VOID mvMPPConfigToDefault(MV_VOID); -+ -+ -+#endif /* __INCmvCtrlEnvLibh */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h 2010-11-09 20:28:07.772495664 +0100 -@@ -0,0 +1,419 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvCtrlEnvRegsh -+#define __INCmvCtrlEnvRegsh -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* CV Support */ -+#define PEX0_MEM0 PEX0_MEM -+#define PCI0_MEM0 PEX0_MEM -+ -+/* Controller revision info */ -+#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 -+#define PCCRIR_REVID_OFFS 0 /* Revision ID */ -+#define PCCRIR_REVID_MASK (0xff << PCCRIR_REVID_OFFS) -+ -+/* Controler environment registers offsets */ -+ -+/* Power Managment Control */ -+#define POWER_MNG_MEM_CTRL_REG 0x20118 -+ -+#define PMC_GESTOPMEM_OFFS(port) ((port)? 13 : 0) -+#define PMC_GESTOPMEM_MASK(port) (1 << PMC_GESTOPMEM_OFFS(port)) -+#define PMC_GESTOPMEM_EN(port) (0 << PMC_GESTOPMEM_OFFS(port)) -+#define PMC_GESTOPMEM_STOP(port) (1 << PMC_GESTOPMEM_OFFS(port)) -+ -+#define PMC_PEXSTOPMEM_OFFS 1 -+#define PMC_PEXSTOPMEM_MASK (1 << PMC_PEXSTOPMEM_OFFS) -+#define PMC_PEXSTOPMEM_EN (0 << PMC_PEXSTOPMEM_OFFS) -+#define PMC_PEXSTOPMEM_STOP (1 << PMC_PEXSTOPMEM_OFFS) -+ -+#define PMC_USBSTOPMEM_OFFS 2 -+#define PMC_USBSTOPMEM_MASK (1 << PMC_USBSTOPMEM_OFFS) -+#define PMC_USBSTOPMEM_EN (0 << PMC_USBSTOPMEM_OFFS) -+#define PMC_USBSTOPMEM_STOP (1 << PMC_USBSTOPMEM_OFFS) -+ -+#define PMC_DUNITSTOPMEM_OFFS 3 -+#define PMC_DUNITSTOPMEM_MASK (1 << PMC_DUNITSTOPMEM_OFFS) -+#define PMC_DUNITSTOPMEM_EN (0 << PMC_DUNITSTOPMEM_OFFS) -+#define PMC_DUNITSTOPMEM_STOP (1 << PMC_DUNITSTOPMEM_OFFS) -+ -+#define PMC_RUNITSTOPMEM_OFFS 4 -+#define PMC_RUNITSTOPMEM_MASK (1 << PMC_RUNITSTOPMEM_OFFS) -+#define PMC_RUNITSTOPMEM_EN (0 << PMC_RUNITSTOPMEM_OFFS) -+#define PMC_RUNITSTOPMEM_STOP (1 << PMC_RUNITSTOPMEM_OFFS) -+ -+#define PMC_XORSTOPMEM_OFFS(port) (5+(port*2)) -+#define PMC_XORSTOPMEM_MASK(port) (1 << PMC_XORSTOPMEM_OFFS(port)) -+#define PMC_XORSTOPMEM_EN(port) (0 << PMC_XORSTOPMEM_OFFS(port)) -+#define PMC_XORSTOPMEM_STOP(port) (1 << PMC_XORSTOPMEM_OFFS(port)) -+ -+#define PMC_SATASTOPMEM_OFFS(port) (6+(port*5)) -+#define PMC_SATASTOPMEM_MASK(port) (1 << PMC_SATASTOPMEM_OFFS(port)) -+#define PMC_SATASTOPMEM_EN(port) (0 << PMC_SATASTOPMEM_OFFS(port)) -+#define PMC_SATASTOPMEM_STOP(port) (1 << PMC_SATASTOPMEM_OFFS(port)) -+ -+#define PMC_SESTOPMEM_OFFS 8 -+#define PMC_SESTOPMEM_MASK (1 << PMC_SESTOPMEM_OFFS) -+#define PMC_SESTOPMEM_EN (0 << PMC_SESTOPMEM_OFFS) -+#define PMC_SESTOPMEM_STOP (1 << PMC_SESTOPMEM_OFFS) -+ -+#define PMC_AUDIOSTOPMEM_OFFS 9 -+#define PMC_AUDIOSTOPMEM_MASK (1 << PMC_AUDIOSTOPMEM_OFFS) -+#define PMC_AUDIOSTOPMEM_EN (0 << PMC_AUDIOSTOPMEM_OFFS) -+#define PMC_AUDIOSTOPMEM_STOP (1 << PMC_AUDIOSTOPMEM_OFFS) -+ -+#define POWER_MNG_CTRL_REG 0x2011C -+ -+#define PMC_GESTOPCLOCK_OFFS(port) ((port)? 19 : 0) -+#define PMC_GESTOPCLOCK_MASK(port) (1 << PMC_GESTOPCLOCK_OFFS(port)) -+#define PMC_GESTOPCLOCK_EN(port) (1 << PMC_GESTOPCLOCK_OFFS(port)) -+#define PMC_GESTOPCLOCK_STOP(port) (0 << PMC_GESTOPCLOCK_OFFS(port)) -+ -+#define PMC_PEXPHYSTOPCLOCK_OFFS 1 -+#define PMC_PEXPHYSTOPCLOCK_MASK (1 << PMC_PEXPHYSTOPCLOCK_OFFS) -+#define PMC_PEXPHYSTOPCLOCK_EN (1 << PMC_PEXPHYSTOPCLOCK_OFFS) -+#define PMC_PEXPHYSTOPCLOCK_STOP (0 << PMC_PEXPHYSTOPCLOCK_OFFS) -+ -+#define PMC_PEXSTOPCLOCK_OFFS 2 -+#define PMC_PEXSTOPCLOCK_MASK (1 << PMC_PEXSTOPCLOCK_OFFS) -+#define PMC_PEXSTOPCLOCK_EN (1 << PMC_PEXSTOPCLOCK_OFFS) -+#define PMC_PEXSTOPCLOCK_STOP (0 << PMC_PEXSTOPCLOCK_OFFS) -+ -+#define PMC_USBSTOPCLOCK_OFFS 3 -+#define PMC_USBSTOPCLOCK_MASK (1 << PMC_USBSTOPCLOCK_OFFS) -+#define PMC_USBSTOPCLOCK_EN (1 << PMC_USBSTOPCLOCK_OFFS) -+#define PMC_USBSTOPCLOCK_STOP (0 << PMC_USBSTOPCLOCK_OFFS) -+ -+#define PMC_SDIOSTOPCLOCK_OFFS 4 -+#define PMC_SDIOSTOPCLOCK_MASK (1 << PMC_SDIOSTOPCLOCK_OFFS) -+#define PMC_SDIOSTOPCLOCK_EN (1 << PMC_SDIOSTOPCLOCK_OFFS) -+#define PMC_SDIOSTOPCLOCK_STOP (0 << PMC_SDIOSTOPCLOCK_OFFS) -+ -+#define PMC_TSSTOPCLOCK_OFFS 5 -+#define PMC_TSSTOPCLOCK_MASK (1 << PMC_TSSTOPCLOCK_OFFS) -+#define PMC_TSSTOPCLOCK_EN (1 << PMC_TSSTOPCLOCK_OFFS) -+#define PMC_TSSTOPCLOCK_STOP (0 << PMC_TSSTOPCLOCK_OFFS) -+ -+#define PMC_AUDIOSTOPCLOCK_OFFS 9 -+#define PMC_AUDIOSTOPCLOCK_MASK (1 << PMC_AUDIOSTOPCLOCK_OFFS) -+#define PMC_AUDIOSTOPCLOCK_EN (1 << PMC_AUDIOSTOPCLOCK_OFFS) -+#define PMC_AUDIOSTOPCLOCK_STOP (0 << PMC_AUDIOSTOPCLOCK_OFFS) -+ -+#define PMC_POWERSAVE_OFFS 11 -+#define PMC_POWERSAVE_MASK (1 << PMC_POWERSAVE_OFFS) -+#define PMC_POWERSAVE_EN (1 << PMC_POWERSAVE_OFFS) -+#define PMC_POWERSAVE_STOP (0 << PMC_POWERSAVE_OFFS) -+ -+ -+ -+ -+#define PMC_SATASTOPCLOCK_OFFS(port) (14+(port)) -+#define PMC_SATASTOPCLOCK_MASK(port) (1 << PMC_SATASTOPCLOCK_OFFS(port)) -+#define PMC_SATASTOPCLOCK_EN(port) (1 << PMC_SATASTOPCLOCK_OFFS(port)) -+#define PMC_SATASTOPCLOCK_STOP(port) (0 << PMC_SATASTOPCLOCK_OFFS(port)) -+ -+#define PMC_SESTOPCLOCK_OFFS 17 -+#define PMC_SESTOPCLOCK_MASK (1 << PMC_SESTOPCLOCK_OFFS) -+#define PMC_SESTOPCLOCK_EN (1 << PMC_SESTOPCLOCK_OFFS) -+#define PMC_SESTOPCLOCK_STOP (0 << PMC_SESTOPCLOCK_OFFS) -+ -+#define PMC_TDMSTOPCLOCK_OFFS 20 -+#define PMC_TDMSTOPCLOCK_MASK (1 << PMC_TDMSTOPCLOCK_OFFS) -+#define PMC_TDMSTOPCLOCK_EN (1 << PMC_TDMSTOPCLOCK_OFFS) -+#define PMC_TDMSTOPCLOCK_STOP (0 << PMC_TDMSTOPCLOCK_OFFS) -+ -+ -+/* Controler environment registers offsets */ -+#define MPP_CONTROL_REG0 0x10000 -+#define MPP_CONTROL_REG1 0x10004 -+#define MPP_CONTROL_REG2 0x10008 -+#define MPP_CONTROL_REG3 0x1000C -+#define MPP_CONTROL_REG4 0x10010 -+#define MPP_CONTROL_REG5 0x10014 -+#define MPP_CONTROL_REG6 0x10018 -+#define MPP_SAMPLE_AT_RESET 0x10030 -+#define CHIP_BOND_REG 0x10034 -+#define SYSRST_LENGTH_COUNTER_REG 0x10050 -+#define SLCR_COUNT_OFFS 0 -+#define SLCR_COUNT_MASK (0x1FFFFFFF << SLCR_COUNT_OFFS) -+#define SLCR_CLR_OFFS 31 -+#define SLCR_CLR_MASK (1 << SLCR_CLR_OFFS) -+#define PCKG_OPT_MASK 0x3 -+#define MPP_OUTPUT_DRIVE_REG 0x100E0 -+#define MPP_RGMII0_OUTPUT_DRIVE_OFFS 7 -+#define MPP_3_3_RGMII0_OUTPUT_DRIVE (0x0 << MPP_RGMII0_OUTPUT_DRIVE_OFFS) -+#define MPP_1_8_RGMII0_OUTPUT_DRIVE (0x1 << MPP_RGMII0_OUTPUT_DRIVE_OFFS) -+#define MPP_RGMII1_OUTPUT_DRIVE_OFFS 15 -+#define MPP_3_3_RGMII1_OUTPUT_DRIVE (0x0 << MPP_RGMII1_OUTPUT_DRIVE_OFFS) -+#define MPP_1_8_RGMII1_OUTPUT_DRIVE (0x1 << MPP_RGMII1_OUTPUT_DRIVE_OFFS) -+ -+#define MSAR_BOOT_MODE_OFFS 12 -+#define MSAR_BOOT_MODE_MASK (0x7 << MSAR_BOOT_MODE_OFFS) -+#define MSAR_BOOT_NAND_WITH_BOOTROM (0x5 << MSAR_BOOT_MODE_OFFS) -+#define MSAR_BOOT_SPI_WITH_BOOTROM (0x4 << MSAR_BOOT_MODE_OFFS) -+#define MSAR_BOOT_SPI_USE_NAND_WITH_BOOTROM (0x2 << MSAR_BOOT_MODE_OFFS) -+ -+#define MSAR_BOOT_MODE_6180(X) (((X & 0x3000) >> 12) | \ -+ ((X & 0x2) << 1)) -+#define MSAR_BOOT_SPI_WITH_BOOTROM_6180 0x1 -+#define MSAR_BOOT_NAND_WITH_BOOTROM_6180 0x5 -+ -+#define MSAR_TCLCK_OFFS 21 -+#define MSAR_TCLCK_MASK (0x1 << MSAR_TCLCK_OFFS) -+#define MSAR_TCLCK_166 (0x1 << MSAR_TCLCK_OFFS) -+#define MSAR_TCLCK_200 (0x0 << MSAR_TCLCK_OFFS) -+ -+ -+#define MSAR_CPUCLCK_EXTRACT(X) (((X & 0x2) >> 1) | ((X & 0x400000) >> 21) | \ -+ ((X & 0x18) >> 1)) -+ -+#define MSAR_CPUCLCK_OFFS_6180 2 -+#define MSAR_CPUCLCK_MASK_6180 (0x7 << MSAR_CPUCLCK_OFFS_6180) -+ -+#define MSAR_DDRCLCK_RTIO_OFFS 5 -+#define MSAR_DDRCLCK_RTIO_MASK (0xF << MSAR_DDRCLCK_RTIO_OFFS) -+ -+#define MSAR_L2CLCK_EXTRACT(X) (((X & 0x600) >> 9) | ((X & 0x80000) >> 17)) -+ -+#ifndef MV_ASMLANGUAGE -+/* CPU clock for 6281,6192 0->Resereved */ -+#define MV_CPU_CLCK_TBL { 0, 0, 0, 0, \ -+ 600000000, 0, 800000000, 1000000000, \ -+ 0, 1200000000, 0, 0, \ -+ 1500000000, 0, 0, 0} -+ -+/* DDR clock RATIO for 6281,6192 {0,0}->Reserved */ -+#define MV_DDR_CLCK_RTIO_TBL {\ -+ {0, 0}, {0, 0}, {2, 1}, {0, 0}, \ -+ {3, 1}, {0, 0}, {4, 1}, {9, 2}, \ -+ {5, 1}, {6, 1}, {0, 0}, {0, 0}, \ -+ {0, 0}, {0, 0}, {0, 0}, {0, 0} \ -+} -+ -+/* L2 clock RATIO for 6281,6192 {1,1}->Reserved */ -+#define MV_L2_CLCK_RTIO_TBL {\ -+ {0, 0}, {2, 1}, {0, 0}, {3, 1}, \ -+ {0, 0}, {0, 0}, {0, 0}, {0, 0} \ -+} -+ -+/* 6180 have different clk reset sampling */ -+/* ARM CPU, DDR, L2 clock for 6180 {0,0,0}->Reserved */ -+#define MV_CPU6180_DDR_L2_CLCK_TBL { \ -+ {0, 0, 0 },\ -+ {0, 0, 0 },\ -+ {0, 0, 0 },\ -+ {0, 0, 0 },\ -+ {0, 0, 0 },\ -+ {600000000, 200000000, 300000000 },\ -+ {800000000, 200000000, 400000000 },\ -+ {0, 0, 0 }\ -+} -+ -+ -+ -+/* These macros help units to identify a target Mbus Arbiter group */ -+#define MV_TARGET_IS_DRAM(target) \ -+ ((target >= SDRAM_CS0) && (target <= SDRAM_CS3)) -+ -+#define MV_TARGET_IS_PEX0(target) \ -+ ((target >= PEX0_MEM) && (target <= PEX0_IO)) -+ -+#define MV_TARGET_IS_PEX1(target) 0 -+ -+#define MV_TARGET_IS_PEX(target) (MV_TARGET_IS_PEX0(target) || MV_TARGET_IS_PEX1(target)) -+ -+#define MV_TARGET_IS_DEVICE(target) \ -+ ((target >= DEVICE_CS0) && (target <= DEVICE_CS3)) -+ -+#define MV_PCI_DRAM_BAR_TO_DRAM_TARGET(bar) 0 -+ -+#define MV_TARGET_IS_AS_BOOT(target) ((target) == (sampleAtResetTargetArray[ \ -+ (mvCtrlModelGet() == MV_6180_DEV_ID)? MSAR_BOOT_MODE_6180 \ -+ (MV_REG_READ(MPP_SAMPLE_AT_RESET)):((MV_REG_READ(MPP_SAMPLE_AT_RESET)\ -+ & MSAR_BOOT_MODE_MASK) >> MSAR_BOOT_MODE_OFFS)])) -+ -+ -+#define MV_CHANGE_BOOT_CS(target) (((target) == DEV_BOOCS)?\ -+ sampleAtResetTargetArray[(mvCtrlModelGet() == MV_6180_DEV_ID)? \ -+ MSAR_BOOT_MODE_6180(MV_REG_READ(MPP_SAMPLE_AT_RESET)): \ -+ ((MV_REG_READ(MPP_SAMPLE_AT_RESET) & MSAR_BOOT_MODE_MASK)\ -+ >> MSAR_BOOT_MODE_OFFS)]:(target)) -+ -+#define TCLK_TO_COUNTER_RATIO 1 /* counters running in Tclk */ -+ -+#define BOOT_TARGETS_NAME_ARRAY { \ -+ TBL_TERM, \ -+ TBL_TERM, \ -+ BOOT_ROM_CS, \ -+ TBL_TERM, \ -+ BOOT_ROM_CS, \ -+ BOOT_ROM_CS, \ -+ TBL_TERM, \ -+ TBL_TERM \ -+} -+ -+#define BOOT_TARGETS_NAME_ARRAY_6180 { \ -+ TBL_TERM, \ -+ BOOT_ROM_CS, \ -+ TBL_TERM, \ -+ TBL_TERM, \ -+ TBL_TERM, \ -+ BOOT_ROM_CS, \ -+ TBL_TERM, \ -+ TBL_TERM \ -+} -+ -+ -+/* For old competability */ -+#define DEVICE_CS0 NFLASH_CS -+#define DEVICE_CS1 SPI_CS -+#define DEVICE_CS2 BOOT_ROM_CS -+#define DEVICE_CS3 DEV_BOOCS -+#define MV_BOOTDEVICE_INDEX 0 -+ -+#define START_DEV_CS DEV_CS0 -+#define DEV_TO_TARGET(dev) ((dev) + DEVICE_CS0) -+ -+#define PCI_IF0_MEM0 PEX0_MEM -+#define PCI_IF0_IO PEX0_IO -+ -+ -+/* This enumerator defines the Marvell controller target ID */ -+typedef enum _mvTargetId -+{ -+ DRAM_TARGET_ID = 0 , /* Port 0 -> DRAM interface */ -+ DEV_TARGET_ID = 1, /* Port 1 -> Nand/SPI */ -+ PEX0_TARGET_ID = 4 , /* Port 4 -> PCI Express0 */ -+ CRYPT_TARGET_ID = 3 , /* Port 3 --> Crypto Engine */ -+ SAGE_TARGET_ID = 12 , /* Port 12 -> SAGE Unit */ -+ MAX_TARGETS_ID -+}MV_TARGET_ID; -+ -+ -+/* This enumerator described the possible Controller paripheral targets. */ -+/* Controller peripherals are designated memory/IO address spaces that the */ -+/* controller can access. They are also refered as "targets" */ -+typedef enum _mvTarget -+{ -+ TBL_TERM = -1, /* none valid target, used as targets list terminator*/ -+ SDRAM_CS0, /* SDRAM chip select 0 */ -+ SDRAM_CS1, /* SDRAM chip select 1 */ -+ SDRAM_CS2, /* SDRAM chip select 2 */ -+ SDRAM_CS3, /* SDRAM chip select 3 */ -+ PEX0_MEM, /* PCI Express 0 Memory */ -+ PEX0_IO, /* PCI Express 0 IO */ -+ INTER_REGS, /* Internal registers */ -+ NFLASH_CS, /* NFLASH_CS */ -+ SPI_CS, /* SPI_CS */ -+ BOOT_ROM_CS, /* BOOT_ROM_CS */ -+ DEV_BOOCS, /* DEV_BOOCS */ -+ CRYPT_ENG, /* Crypto Engine */ -+#ifdef MV_INCLUDE_SAGE -+ SAGE_UNIT, /* SAGE Unit */ -+#endif -+ MAX_TARGETS -+ -+}MV_TARGET; -+ -+#define TARGETS_DEF_ARRAY { \ -+ {0x0E, DRAM_TARGET_ID }, /* SDRAM_CS0 */ \ -+ {0x0D, DRAM_TARGET_ID }, /* SDRAM_CS1 */ \ -+ {0x0B, DRAM_TARGET_ID }, /* SDRAM_CS0 */ \ -+ {0x07, DRAM_TARGET_ID }, /* SDRAM_CS1 */ \ -+ {0xE8, PEX0_TARGET_ID }, /* PEX0_MEM */ \ -+ {0xE0, PEX0_TARGET_ID }, /* PEX0_IO */ \ -+ {0xFF, 0xFF }, /* INTER_REGS */ \ -+ {0x2F, DEV_TARGET_ID }, /* NFLASH_CS */ \ -+ {0x1E, DEV_TARGET_ID }, /* SPI_CS */ \ -+ {0x1D, DEV_TARGET_ID }, /* BOOT_ROM_CS */ \ -+ {0x1E, DEV_TARGET_ID }, /* DEV_BOOCS */ \ -+ {0x01, CRYPT_TARGET_ID}, /* CRYPT_ENG */ \ -+ {0x00, SAGE_TARGET_ID } \ -+} -+ -+ -+#define TARGETS_NAME_ARRAY { \ -+ "SDRAM_CS0", /* SDRAM_CS0 */ \ -+ "SDRAM_CS1", /* SDRAM_CS1 */ \ -+ "SDRAM_CS2", /* SDRAM_CS2 */ \ -+ "SDRAM_CS3", /* SDRAM_CS3 */ \ -+ "PEX0_MEM", /* PEX0_MEM */ \ -+ "PEX0_IO", /* PEX0_IO */ \ -+ "INTER_REGS", /* INTER_REGS */ \ -+ "NFLASH_CS", /* NFLASH_CS */ \ -+ "SPI_CS", /* SPI_CS */ \ -+ "BOOT_ROM_CS", /* BOOT_ROM_CS */ \ -+ "DEV_BOOTCS", /* DEV_BOOCS */ \ -+ "CRYPT_ENG", /* CRYPT_ENG */ \ -+ "SAGE_UNIT" /* SAGE_UNIT */ \ -+} -+#endif /* MV_ASMLANGUAGE */ -+ -+ -+#endif -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h 2010-11-09 20:28:07.802495420 +0100 -@@ -0,0 +1,257 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvCtrlEnvSpech -+#define __INCmvCtrlEnvSpech -+ -+#include "mvDeviceId.h" -+#include "mvSysHwConfig.h" -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+#define MV_ARM_SOC -+#define SOC_NAME_PREFIX "MV88F" -+ -+ -+/* units base and port numbers */ -+#ifdef MV_ASMLANGUAGE -+#define XOR_UNIT_BASE(unit) 0x60800 -+#else -+#define MV_XOR_REG_BASE 0x60000 -+#define XOR_UNIT_BASE(unit) ((unit)? 0x60900:0x60800) -+#endif -+ -+#define TDM_REG_BASE 0xD0000 -+#define USB_REG_BASE(dev) 0x50000 -+#define AUDIO_REG_BASE 0xA0000 -+#define SATA_REG_BASE 0x80000 -+#define MV_CESA_REG_BASE 0x3D000 -+#define MV_CESA_TDMA_REG_BASE 0x30000 -+#define MV_SDIO_REG_BASE 0x90000 -+#define MV_ETH_REG_BASE(port) (((port) == 0) ? 0x72000 : 0x76000) -+#define MV_UART_CHAN_BASE(chanNum) (0x12000 + (chanNum * 0x100)) -+#define DRAM_BASE 0x0 -+#define CNTMR_BASE 0x20300 -+#define TWSI_SLAVE_BASE(chanNum) 0x11000 -+#define PEX_IF_BASE(pexIf) 0x40000 -+#define MPP_REG_BASE 0x10000 -+#define TSU_GLOBAL_REG_BASE 0xB4000 -+#define MAX_AHB_TO_MBUS_REG_BASE 0x20000 -+ -+#define INTER_REGS_SIZE _1M -+/* This define describes the TWSI interrupt bit and location */ -+#define TWSI_CPU_MAIN_INT_CAUSE_REG 0x20200 -+#define TWSI0_CPU_MAIN_INT_BIT (1<<29) -+#define TWSI_SPEED 100000 -+ -+#define MV_GPP_MAX_GROUP 2 -+#define MV_CNTMR_MAX_COUNTER 2 -+#define MV_UART_MAX_CHAN 2 -+#define MV_XOR_MAX_UNIT 2 -+#define MV_XOR_MAX_CHAN 4 /* total channels for all units together*/ -+#define MV_XOR_MAX_CHAN_PER_UNIT 2 /* channels for units */ -+#define MV_SATA_MAX_CHAN 2 -+ -+#define MV_6281_MPP_MAX_MODULE 2 -+#define MV_6192_MPP_MAX_MODULE 1 -+#define MV_6190_MPP_MAX_MODULE 1 -+#define MV_6180_MPP_MAX_MODULE 2 -+#define MV_6281_MPP_MAX_GROUP 7 -+#define MV_6192_MPP_MAX_GROUP 4 -+#define MV_6190_MPP_MAX_GROUP 4 -+#define MV_6180_MPP_MAX_GROUP 3 -+ -+#define MV_DRAM_MAX_CS 4 -+ -+/* This define describes the maximum number of supported PCI\PCIX Interfaces*/ -+#define MV_PCI_MAX_IF 0 -+#define MV_PCI_START_IF 0 -+ -+/* This define describes the maximum number of supported PEX Interfaces */ -+#define MV_INCLUDE_PEX0 -+#define MV_DISABLE_PEX_DEVICE_BAR -+#define MV_PEX_MAX_IF 1 -+#define MV_PEX_START_IF MV_PCI_MAX_IF -+ -+/* This define describes the maximum number of supported PCI Interfaces */ -+#define MV_PCI_IF_MAX_IF (MV_PEX_MAX_IF+MV_PCI_MAX_IF) -+ -+#define MV_ETH_MAX_PORTS 2 -+#define MV_6281_ETH_MAX_PORTS 2 -+#define MV_6192_ETH_MAX_PORTS 2 -+#define MV_6190_ETH_MAX_PORTS 1 -+#define MV_6180_ETH_MAX_PORTS 1 -+ -+#define MV_IDMA_MAX_CHAN 0 -+ -+#define MV_USB_MAX_PORTS 1 -+ -+#define MV_USB_VERSION 1 -+ -+ -+#define MV_6281_NAND 1 -+#define MV_6192_NAND 1 -+#define MV_6190_NAND 1 -+#define MV_6180_NAND 0 -+ -+#define MV_6281_SDIO 1 -+#define MV_6192_SDIO 1 -+#define MV_6190_SDIO 1 -+#define MV_6180_SDIO 1 -+ -+#define MV_6281_TS 1 -+#define MV_6192_TS 1 -+#define MV_6190_TS 0 -+#define MV_6180_TS 0 -+ -+#define MV_6281_AUDIO 1 -+#define MV_6192_AUDIO 1 -+#define MV_6190_AUDIO 0 -+#define MV_6180_AUDIO 1 -+ -+#define MV_6281_TDM 1 -+#define MV_6192_TDM 1 -+#define MV_6190_TDM 0 -+#define MV_6180_TDM 0 -+ -+#define MV_DEVICE_MAX_CS 4 -+ -+/* Others */ -+#define PEX_HOST_BUS_NUM(pciIf) (pciIf) -+#define PEX_HOST_DEV_NUM(pciIf) 0 -+ -+#define PCI_IO(pciIf) (PEX0_IO) -+#define PCI_MEM(pciIf, memNum) (PEX0_MEM0) -+/* CESA version #2: One channel, 2KB SRAM, TDMA */ -+#if defined(MV_CESA_CHAIN_MODE_SUPPORT) -+ #define MV_CESA_VERSION 3 -+#else -+#define MV_CESA_VERSION 2 -+#endif -+#define MV_CESA_SRAM_SIZE 2*1024 -+/* This define describes the maximum number of supported Ethernet ports */ -+#define MV_ETH_VERSION 4 -+#define MV_ETH_MAX_RXQ 8 -+#define MV_ETH_MAX_TXQ 8 -+#define MV_ETH_PORT_SGMII { MV_FALSE, MV_FALSE } -+/* This define describes the the support of USB */ -+#define MV_USB_VERSION 1 -+ -+#define MV_INCLUDE_SDRAM_CS0 -+#define MV_INCLUDE_SDRAM_CS1 -+#define MV_INCLUDE_SDRAM_CS2 -+#define MV_INCLUDE_SDRAM_CS3 -+ -+#define MV_INCLUDE_DEVICE_CS0 -+#define MV_INCLUDE_DEVICE_CS1 -+#define MV_INCLUDE_DEVICE_CS2 -+#define MV_INCLUDE_DEVICE_CS3 -+ -+#define MPP_GROUP_1_TYPE {\ -+ {0, 0, 0}, /* Reserved for AUTO */ \ -+ {0x22220000, 0x22222222, 0x2222}, /* TDM */ \ -+ {0x44440000, 0x00044444, 0x0000}, /* AUDIO */ \ -+ {0x33330000, 0x33003333, 0x0033}, /* RGMII */ \ -+ {0x33330000, 0x03333333, 0x0033}, /* GMII */ \ -+ {0x11110000, 0x11111111, 0x0001}, /* TS */ \ -+ {0x33330000, 0x33333333, 0x3333} /* MII */ \ -+} -+ -+#define MPP_GROUP_2_TYPE {\ -+ {0, 0, 0}, /* Reserved for AUTO */ \ -+ {0x22220000, 0x22222222, 0x22}, /* TDM */ \ -+ {0x44440000, 0x00044444, 0x0}, /* AUDIO */ \ -+ {0, 0, 0}, /* N_A */ \ -+ {0, 0, 0}, /* N_A */ \ -+ {0x11110000, 0x11111111, 0x01} /* TS */ \ -+} -+ -+#ifndef MV_ASMLANGUAGE -+ -+/* This enumerator defines the Marvell Units ID */ -+typedef enum _mvUnitId -+{ -+ DRAM_UNIT_ID, -+ PEX_UNIT_ID, -+ ETH_GIG_UNIT_ID, -+ USB_UNIT_ID, -+ IDMA_UNIT_ID, -+ XOR_UNIT_ID, -+ SATA_UNIT_ID, -+ TDM_UNIT_ID, -+ UART_UNIT_ID, -+ CESA_UNIT_ID, -+ SPI_UNIT_ID, -+ AUDIO_UNIT_ID, -+ SDIO_UNIT_ID, -+ TS_UNIT_ID, -+ MAX_UNITS_ID -+ -+}MV_UNIT_ID; -+ -+#endif -+ -+#endif /* __INCmvCtrlEnvSpech */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c 2010-11-09 20:28:07.842495395 +0100 -@@ -0,0 +1,1048 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+/* includes */ -+#include "ctrlEnv/sys/mvAhbToMbus.h" -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+ -+#undef MV_DEBUG -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+/* typedefs */ -+ -+ -+/* CPU address remap registers offsets are inconsecutive. This struct */ -+/* describes address remap register offsets */ -+typedef struct _ahbToMbusRemapRegOffs -+{ -+ MV_U32 lowRegOffs; /* Low 32-bit remap register offset */ -+ MV_U32 highRegOffs; /* High 32 bit remap register offset */ -+}AHB_TO_MBUS_REMAP_REG_OFFS; -+ -+/* locals */ -+static MV_STATUS ahbToMbusRemapRegOffsGet (MV_U32 winNum, -+ AHB_TO_MBUS_REMAP_REG_OFFS *pRemapRegs); -+ -+/******************************************************************************* -+* mvAhbToMbusInit - Initialize Ahb To Mbus Address Map ! -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK laways. -+* -+*******************************************************************************/ -+MV_STATUS mvAhbToMbusInit(void) -+{ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvAhbToMbusWinSet - Set CPU-to-peripheral winNum address window -+* -+* DESCRIPTION: -+* This function sets -+* address window, also known as address decode window. -+* A new address decode window is set for specified winNum address window. -+* If address decode window parameter structure enables the window, -+* the routine will also enable the winNum window, allowing CPU to access -+* the winNum window. -+* -+* INPUT: -+* winNum - Windows number. -+* pAddrDecWin - CPU winNum window data structure. -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_OK if CPU winNum window was set correctly, MV_ERROR in case of -+* address window overlapps with other active CPU winNum window or -+* trying to assign 36bit base address while CPU does not support that. -+* The function returns MV_NOT_SUPPORTED, if the winNum is unsupported. -+* -+*******************************************************************************/ -+MV_STATUS mvAhbToMbusWinSet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin) -+{ -+ MV_TARGET_ATTRIB targetAttribs; -+ MV_DEC_REGS decRegs; -+ -+ /* Parameter checking */ -+ if (winNum >= MAX_AHB_TO_MBUS_WINS) -+ { -+ mvOsPrintf("mvAhbToMbusWinSet: ERR. Invalid winNum %d\n", winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ -+ /* read base register*/ -+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum)); -+ } -+ else -+ { -+ decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_INTEREG_REG); -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvAhbToMbusWinSet:Error setting AHB to MBUS window %d to "\ -+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, -+ mvCtrlTargetNameGet(pAddrDecWin->target), -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ /* read control register*/ -+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ decRegs.sizeReg = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum)); -+ } -+ -+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) -+ { -+ mvOsPrintf("mvAhbToMbusWinSet:mvCtrlAddrDecToReg Failed\n"); -+ return MV_ERROR; -+ } -+ -+ /* enable\Disable */ -+ if (MV_TRUE == pAddrDecWin->enable) -+ { -+ decRegs.sizeReg |= ATMWCR_WIN_ENABLE; -+ } -+ else -+ { -+ decRegs.sizeReg &= ~ATMWCR_WIN_ENABLE; -+ } -+ -+ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); -+ -+ /* set attributes */ -+ decRegs.sizeReg &= ~ATMWCR_WIN_ATTR_MASK; -+ decRegs.sizeReg |= targetAttribs.attrib << ATMWCR_WIN_ATTR_OFFS; -+ /* set target ID */ -+ decRegs.sizeReg &= ~ATMWCR_WIN_TARGET_MASK; -+ decRegs.sizeReg |= targetAttribs.targetId << ATMWCR_WIN_TARGET_OFFS; -+ -+#if !defined(MV_RUN_FROM_FLASH) -+ /* To be on the safe side we disable the window before writing the */ -+ /* new values. */ -+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ mvAhbToMbusWinEnable(winNum,MV_FALSE); -+ } -+#endif -+ -+ /* 3) Write to address decode Base Address Register */ -+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum), decRegs.baseReg); -+ } -+ else -+ { -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_INTEREG_REG, decRegs.baseReg); -+ } -+ -+ -+ /* Internal register space have no size */ -+ /* register. Do not perform size register assigment for those targets */ -+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ /* Write to address decode Size Register */ -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), decRegs.sizeReg); -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvAhbToMbusWinGet - Get CPU-to-peripheral winNum address window -+* -+* DESCRIPTION: -+* Get the CPU peripheral winNum address window. -+* -+* INPUT: -+* winNum - Peripheral winNum enumerator -+* -+* OUTPUT: -+* pAddrDecWin - CPU winNum window information data structure. -+* -+* RETURN: -+* MV_OK if winNum exist, MV_ERROR otherwise. -+* -+*******************************************************************************/ -+MV_STATUS mvAhbToMbusWinGet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin) -+{ -+ MV_DEC_REGS decRegs; -+ MV_TARGET_ATTRIB targetAttrib; -+ -+ -+ /* Parameter checking */ -+ if (winNum >= MAX_AHB_TO_MBUS_WINS) -+ { -+ mvOsPrintf("mvAhbToMbusWinGet: ERR. Invalid winNum %d\n", winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ -+ /* Internal register space size have no size register*/ -+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ decRegs.sizeReg = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum)); -+ } -+ else -+ { -+ decRegs.sizeReg = 0; -+ } -+ -+ -+ /* Read base and size */ -+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum)); -+ } -+ else -+ { -+ decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_INTEREG_REG); -+ } -+ -+ -+ -+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) -+ { -+ mvOsPrintf("mvAhbToMbusWinGet: mvCtrlRegToAddrDec Failed \n"); -+ return MV_ERROR; -+ } -+ -+ if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ pAddrDecWin->addrWin.size = INTER_REGS_SIZE; -+ pAddrDecWin->target = INTER_REGS; -+ pAddrDecWin->enable = MV_TRUE; -+ -+ return MV_OK; -+ } -+ -+ -+ if (decRegs.sizeReg & ATMWCR_WIN_ENABLE) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ -+ } -+ -+ -+ -+ if (-1 == pAddrDecWin->addrWin.size) -+ { -+ return MV_ERROR; -+ } -+ -+ /* attrib and targetId */ -+ targetAttrib.attrib = (decRegs.sizeReg & ATMWCR_WIN_ATTR_MASK) >> -+ ATMWCR_WIN_ATTR_OFFS; -+ targetAttrib.targetId = (decRegs.sizeReg & ATMWCR_WIN_TARGET_MASK) >> -+ ATMWCR_WIN_TARGET_OFFS; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvAhbToMbusWinTargetGet - Get Window number associated with target -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_U32 mvAhbToMbusWinTargetGet(MV_TARGET target) -+{ -+ MV_AHB_TO_MBUS_DEC_WIN decWin; -+ MV_U32 winNum; -+ -+ /* Check parameters */ -+ if (target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetGet: target %d is Illigal\n", target); -+ return 0xffffffff; -+ } -+ -+ if (INTER_REGS == target) -+ { -+ return MV_AHB_TO_MBUS_INTREG_WIN; -+ } -+ -+ for (winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS ; winNum++) -+ { -+ if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) -+ continue; -+ -+ if (mvAhbToMbusWinGet(winNum,&decWin) != MV_OK) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetGet: mvAhbToMbusWinGet fail\n"); -+ return 0xffffffff; -+ -+ } -+ -+ if (decWin.enable == MV_TRUE) -+ { -+ if (decWin.target == target) -+ { -+ return winNum; -+ } -+ -+ } -+ -+ } -+ -+ return 0xFFFFFFFF; -+ -+ -+} -+ -+/******************************************************************************* -+* mvAhbToMbusWinAvailGet - Get First Available window number. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_U32 mvAhbToMbusWinAvailGet(MV_VOID) -+{ -+ MV_AHB_TO_MBUS_DEC_WIN decWin; -+ MV_U32 winNum; -+ -+ for (winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS ; winNum++) -+ { -+ if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) -+ continue; -+ -+ if (mvAhbToMbusWinGet(winNum,&decWin) != MV_OK) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetGet: mvAhbToMbusWinGet fail\n"); -+ return 0xffffffff; -+ -+ } -+ -+ if (decWin.enable == MV_FALSE) -+ { -+ return winNum; -+ } -+ -+ } -+ -+ return 0xFFFFFFFF; -+} -+ -+ -+/******************************************************************************* -+* mvAhbToMbusWinEnable - Enable/disable a CPU address decode window -+* -+* DESCRIPTION: -+* This function enable/disable a CPU address decode window. -+* if parameter 'enable' == MV_TRUE the routine will enable the -+* window, thus enabling CPU accesses (before enabling the window it is -+* tested for overlapping). Otherwise, the window will be disabled. -+* -+* INPUT: -+* winNum - Peripheral winNum enumerator. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_ERROR if protection window number was wrong, or the window -+* overlapps other winNum window. -+* -+*******************************************************************************/ -+MV_STATUS mvAhbToMbusWinEnable(MV_U32 winNum, MV_BOOL enable) -+{ -+ -+ /* Parameter checking */ -+ if (winNum >= MAX_AHB_TO_MBUS_WINS) -+ { -+ mvOsPrintf("mvAhbToMbusWinEnable: ERR. Invalid winNum %d\n", winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ /* Internal registers bar can't be disable or enabled */ -+ if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ return (enable ? MV_OK : MV_ERROR); -+ } -+ -+ if (enable == MV_TRUE) -+ { -+ /* enable the window */ -+ MV_REG_BIT_SET(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ATMWCR_WIN_ENABLE); -+ } -+ else -+ { /* Disable address decode winNum window */ -+ MV_REG_BIT_RESET(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ATMWCR_WIN_ENABLE); -+ } -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvAhbToMbusWinRemap - Set CPU remap register for address windows. -+* -+* DESCRIPTION: -+* After a CPU address hits one of PCI address decode windows there is an -+* option to remap the address to a different one. For example, CPU -+* executes a read from PCI winNum window address 0x1200.0000. This -+* can be modified so the address on the PCI bus would be 0x1400.0000 -+* Using the PCI address remap mechanism. -+* -+* INPUT: -+* winNum - Peripheral winNum enumerator. Must be a PCI winNum. -+* pAddrDecWin - CPU winNum window information data structure. -+* Note that caller has to fill in the base field only. The -+* size field is ignored. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR if winNum is not a PCI one, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_U32 mvAhbToMbusWinRemap(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 baseAddr; -+ AHB_TO_MBUS_REMAP_REG_OFFS remapRegOffs; -+ -+ MV_U32 effectiveBaseAddress=0, -+ baseAddrValue=0,windowSizeValue=0; -+ -+ -+ /* Get registers offsets of given winNum */ -+ if (MV_NO_SUCH == ahbToMbusRemapRegOffsGet(winNum, &remapRegOffs)) -+ { -+ return 0xffffffff; -+ } -+ -+ /* 1) Set address remap low */ -+ baseAddr = pAddrWin->baseLow; -+ -+ /* Check base address aligment */ -+ /* -+ if (MV_IS_NOT_ALIGN(baseAddr, ATMWRLR_REMAP_LOW_ALIGNMENT)) -+ { -+ mvOsPrintf("mvAhbToMbusPciRemap: Warning. Target base 0x%x unaligned\n", -+ baseAddr); -+ return MV_ERROR; -+ } -+ */ -+ -+ /* BaseLow[31:16] => base register [31:16] */ -+ baseAddr = baseAddr & ATMWRLR_REMAP_LOW_MASK; -+ -+ MV_REG_WRITE(remapRegOffs.lowRegOffs, baseAddr); -+ -+ MV_REG_WRITE(remapRegOffs.highRegOffs, pAddrWin->baseHigh); -+ -+ -+ baseAddrValue = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum)); -+ windowSizeValue = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum)); -+ -+ baseAddrValue &= ATMWBR_BASE_MASK; -+ windowSizeValue &=ATMWCR_WIN_SIZE_MASK; -+ -+ /* Start calculating the effective Base Address */ -+ effectiveBaseAddress = baseAddrValue ; -+ -+ /* The effective base address will be combined from the chopped (if any) -+ remap value (according to the size value and remap mechanism) and the -+ window's base address */ -+ effectiveBaseAddress |= (((windowSizeValue) | 0xffff) & pAddrWin->baseLow); -+ /* If the effectiveBaseAddress exceed the window boundaries return an -+ invalid value. */ -+ -+ if (effectiveBaseAddress > (baseAddrValue + (windowSizeValue | 0xffff))) -+ { -+ mvOsPrintf("mvAhbToMbusPciRemap: Error\n"); -+ return 0xffffffff; -+ } -+ -+ return effectiveBaseAddress; -+ -+ -+} -+/******************************************************************************* -+* mvAhbToMbusWinTargetSwap - Swap AhbToMbus windows between targets -+* -+* DESCRIPTION: -+* -+* INPUT: -+* target1 - CPU Interface target 1 -+* target2 - CPU Interface target 2 -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR if targets are illigal, or if one of the targets is not -+* associated to a valid window . -+* MV_OK otherwise. -+* -+*******************************************************************************/ -+ -+ -+MV_STATUS mvAhbToMbusWinTargetSwap(MV_TARGET target1,MV_TARGET target2) -+{ -+ MV_U32 winNum1,winNum2; -+ MV_AHB_TO_MBUS_DEC_WIN winDec1,winDec2,winDecTemp; -+ AHB_TO_MBUS_REMAP_REG_OFFS remapRegs1,remapRegs2; -+ MV_U32 remapBaseLow1=0,remapBaseLow2=0; -+ MV_U32 remapBaseHigh1=0,remapBaseHigh2=0; -+ -+ -+ /* Check parameters */ -+ if (target1 >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d is Illigal\n", target1); -+ return MV_ERROR; -+ } -+ -+ if (target2 >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d is Illigal\n", target1); -+ return MV_ERROR; -+ } -+ -+ -+ /* get window associated with this target */ -+ winNum1 = mvAhbToMbusWinTargetGet(target1); -+ -+ if (winNum1 == 0xffffffff) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d has illigal win %d\n", -+ target1,winNum1); -+ return MV_ERROR; -+ -+ } -+ -+ /* get window associated with this target */ -+ winNum2 = mvAhbToMbusWinTargetGet(target2); -+ -+ if (winNum2 == 0xffffffff) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d has illigal win %d\n", -+ target2,winNum2); -+ return MV_ERROR; -+ -+ } -+ -+ /* now Get original values of both Windows */ -+ if (MV_OK != mvAhbToMbusWinGet(winNum1,&winDec1)) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetSwap: mvAhbToMbusWinGet failed win %d\n", -+ winNum1); -+ return MV_ERROR; -+ -+ } -+ if (MV_OK != mvAhbToMbusWinGet(winNum2,&winDec2)) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetSwap: mvAhbToMbusWinGet failed win %d\n", -+ winNum2); -+ return MV_ERROR; -+ -+ } -+ -+ -+ /* disable both windows */ -+ if (MV_OK != mvAhbToMbusWinEnable(winNum1,MV_FALSE)) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetSwap: failed to enable window %d\n", -+ winNum1); -+ return MV_ERROR; -+ -+ } -+ if (MV_OK != mvAhbToMbusWinEnable(winNum2,MV_FALSE)) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetSwap: failed to enable windo %d\n", -+ winNum2); -+ return MV_ERROR; -+ -+ } -+ -+ -+ /* now swap targets */ -+ -+ /* first save winDec2 values */ -+ winDecTemp.addrWin.baseHigh = winDec2.addrWin.baseHigh; -+ winDecTemp.addrWin.baseLow = winDec2.addrWin.baseLow; -+ winDecTemp.addrWin.size = winDec2.addrWin.size; -+ winDecTemp.enable = winDec2.enable; -+ winDecTemp.target = winDec2.target; -+ -+ /* winDec2 = winDec1 */ -+ winDec2.addrWin.baseHigh = winDec1.addrWin.baseHigh; -+ winDec2.addrWin.baseLow = winDec1.addrWin.baseLow; -+ winDec2.addrWin.size = winDec1.addrWin.size; -+ winDec2.enable = winDec1.enable; -+ winDec2.target = winDec1.target; -+ -+ -+ /* winDec1 = winDecTemp */ -+ winDec1.addrWin.baseHigh = winDecTemp.addrWin.baseHigh; -+ winDec1.addrWin.baseLow = winDecTemp.addrWin.baseLow; -+ winDec1.addrWin.size = winDecTemp.addrWin.size; -+ winDec1.enable = winDecTemp.enable; -+ winDec1.target = winDecTemp.target; -+ -+ -+ /* now set the new values */ -+ -+ -+ mvAhbToMbusWinSet(winNum1,&winDec1); -+ mvAhbToMbusWinSet(winNum2,&winDec2); -+ -+ -+ -+ -+ -+ /* now we will treat the remap windows if exist */ -+ -+ -+ /* now check if one or both windows has a remap window -+ as well after the swap ! */ -+ -+ /* if a window had a remap value differnt than the base value -+ before the swap , then after the swap the remap value will be -+ equal to the base value unless both windows has a remap windows*/ -+ -+ /* first get old values */ -+ if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum1,&remapRegs1)) -+ { -+ remapBaseLow1 = MV_REG_READ(remapRegs1.lowRegOffs); -+ remapBaseHigh1 = MV_REG_READ(remapRegs1.highRegOffs); -+ -+ } -+ if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2,&remapRegs2)) -+ { -+ remapBaseLow2 = MV_REG_READ(remapRegs2.lowRegOffs); -+ remapBaseHigh2 = MV_REG_READ(remapRegs2.highRegOffs); -+ -+ -+ } -+ -+ /* now do the swap */ -+ if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum1,&remapRegs1)) -+ { -+ if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2,&remapRegs2)) -+ { -+ /* Two windows has a remap !!! so swap */ -+ -+ MV_REG_WRITE(remapRegs2.highRegOffs,remapBaseHigh1); -+ MV_REG_WRITE(remapRegs2.lowRegOffs,remapBaseLow1); -+ -+ MV_REG_WRITE(remapRegs1.highRegOffs,remapBaseHigh2); -+ MV_REG_WRITE(remapRegs1.lowRegOffs,remapBaseLow2); -+ -+ -+ -+ } -+ else -+ { -+ /* remap == base */ -+ MV_REG_WRITE(remapRegs1.highRegOffs,winDec1.addrWin.baseHigh); -+ MV_REG_WRITE(remapRegs1.lowRegOffs,winDec1.addrWin.baseLow); -+ -+ } -+ -+ } -+ else if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2,&remapRegs2)) -+ { -+ /* remap == base */ -+ MV_REG_WRITE(remapRegs2.highRegOffs,winDec2.addrWin.baseHigh); -+ MV_REG_WRITE(remapRegs2.lowRegOffs,winDec2.addrWin.baseLow); -+ -+ } -+ -+ -+ -+ return MV_OK; -+ -+ -+} -+ -+ -+ -+#if defined(MV_88F1181) -+ -+/******************************************************************************* -+* mvAhbToMbusXbarCtrlSet - Set The CPU master Xbar arbitration. -+* -+* DESCRIPTION: -+* This function sets CPU Mbus Arbiter -+* -+* INPUT: -+* pPizzaArbArray - A priority Structure describing 16 "pizza slices". At -+* each clock cycle, the crossbar arbiter samples all -+* requests and gives the bus to the next agent according -+* to the "pizza". -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_ERROR if paramers to function invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvMbusArbSet(MV_MBUS_ARB_TARGET *pPizzaArbArray) -+{ -+ MV_U32 sliceNum; -+ MV_U32 xbarCtrl = 0; -+ MV_MBUS_ARB_TARGET xbarTarget; -+ -+ /* 1) Set crossbar control low register */ -+ for (sliceNum = 0; sliceNum < MRLR_SLICE_NUM; sliceNum++) -+ { -+ xbarTarget = pPizzaArbArray[sliceNum]; -+ -+ /* sliceNum parameter check */ -+ if (xbarTarget > MAX_MBUS_ARB_TARGETS) -+ { -+ mvOsPrintf("mvAhbToMbusXbarCtrlSet: ERR. Can't set Target %d\n", -+ xbarTarget); -+ return MV_ERROR; -+ } -+ xbarCtrl |= (xbarTarget << MRLR_LOW_ARB_OFFS(sliceNum)); -+ } -+ /* Write to crossbar control low register */ -+ MV_REG_WRITE(MBUS_ARBITER_LOW_REG, xbarCtrl); -+ -+ xbarCtrl = 0; -+ -+ /* 2) Set crossbar control high register */ -+ for (sliceNum = MRLR_SLICE_NUM; -+ sliceNum < MRLR_SLICE_NUM+MRHR_SLICE_NUM; -+ sliceNum++) -+ { -+ -+ xbarTarget = pPizzaArbArray[sliceNum]; -+ -+ /* sliceNum parameter check */ -+ if (xbarTarget > MAX_MBUS_ARB_TARGETS) -+ { -+ mvOsPrintf("mvAhbToMbusXbarCtrlSet: ERR. Can't set Target %d\n", -+ xbarTarget); -+ return MV_ERROR; -+ } -+ xbarCtrl |= (xbarTarget << MRHR_HIGH_ARB_OFFS(sliceNum)); -+ } -+ /* Write to crossbar control high register */ -+ MV_REG_WRITE(MBUS_ARBITER_HIGH_REG, xbarCtrl); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvMbusArbCtrlSet - Set MBus Arbiter control register -+* -+* DESCRIPTION: -+* -+* INPUT: -+* ctrl - pointer to MV_MBUS_ARB_CTRL register -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_ERROR if paramers to function invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvMbusArbCtrlSet(MV_MBUS_ARB_CTRL *ctrl) -+{ -+ -+ if (ctrl->highPrio == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(MBUS_ARBITER_CTRL_REG, MACR_ARB_ARM_TOP); -+ } -+ else -+ { -+ MV_REG_BIT_SET(MBUS_ARBITER_CTRL_REG, MACR_ARB_ARM_TOP); -+ } -+ -+ if (ctrl->fixedRoundRobin == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(MBUS_ARBITER_CTRL_REG, MACR_ARB_TARGET_FIXED); -+ } -+ else -+ { -+ MV_REG_BIT_SET(MBUS_ARBITER_CTRL_REG, MACR_ARB_TARGET_FIXED); -+ } -+ -+ if (ctrl->starvEn == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(MBUS_ARBITER_CTRL_REG, MACR_ARB_REQ_CTRL_EN); -+ } -+ else -+ { -+ MV_REG_BIT_SET(MBUS_ARBITER_CTRL_REG, MACR_ARB_REQ_CTRL_EN); -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvMbusArbCtrlGet - Get MBus Arbiter control register -+* -+* DESCRIPTION: -+* -+* INPUT: -+* ctrl - pointer to MV_MBUS_ARB_CTRL register -+* -+* OUTPUT: -+* ctrl - pointer to MV_MBUS_ARB_CTRL register -+* -+* RETURN: -+* MV_ERROR if paramers to function invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvMbusArbCtrlGet(MV_MBUS_ARB_CTRL *ctrl) -+{ -+ -+ MV_U32 ctrlReg = MV_REG_READ(MBUS_ARBITER_CTRL_REG); -+ -+ if (ctrlReg & MACR_ARB_ARM_TOP) -+ { -+ ctrl->highPrio = MV_TRUE; -+ } -+ else -+ { -+ ctrl->highPrio = MV_FALSE; -+ } -+ -+ if (ctrlReg & MACR_ARB_TARGET_FIXED) -+ { -+ ctrl->fixedRoundRobin = MV_TRUE; -+ } -+ else -+ { -+ ctrl->fixedRoundRobin = MV_FALSE; -+ } -+ -+ if (ctrlReg & MACR_ARB_REQ_CTRL_EN) -+ { -+ ctrl->starvEn = MV_TRUE; -+ } -+ else -+ { -+ ctrl->starvEn = MV_FALSE; -+ } -+ -+ -+ return MV_OK; -+} -+ -+#endif /* #if defined(MV_88F1181) */ -+ -+ -+ -+/******************************************************************************* -+* ahbToMbusRemapRegOffsGet - Get CPU address remap register offsets -+* -+* DESCRIPTION: -+* CPU to PCI address remap registers offsets are inconsecutive. -+* This function returns PCI address remap registers offsets. -+* -+* INPUT: -+* winNum - Address decode window number. See MV_U32 enumerator. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR if winNum is not a PCI one. -+* -+*******************************************************************************/ -+static MV_STATUS ahbToMbusRemapRegOffsGet(MV_U32 winNum, -+ AHB_TO_MBUS_REMAP_REG_OFFS *pRemapRegs) -+{ -+ switch (winNum) -+ { -+ case 0: -+ case 1: -+ pRemapRegs->lowRegOffs = AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum); -+ pRemapRegs->highRegOffs = AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum); -+ break; -+ case 2: -+ case 3: -+ if((mvCtrlModelGet() == MV_5281_DEV_ID) || -+ (mvCtrlModelGet() == MV_1281_DEV_ID) || -+ (mvCtrlModelGet() == MV_6183_DEV_ID) || -+ (mvCtrlModelGet() == MV_6183L_DEV_ID)) -+ { -+ pRemapRegs->lowRegOffs = AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum); -+ pRemapRegs->highRegOffs = AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum); -+ break; -+ } -+ else -+ { -+ pRemapRegs->lowRegOffs = 0; -+ pRemapRegs->highRegOffs = 0; -+ -+ DB(mvOsPrintf("ahbToMbusRemapRegOffsGet: ERR. Invalid winNum %d\n", -+ winNum)); -+ return MV_NO_SUCH; -+ } -+ default: -+ { -+ pRemapRegs->lowRegOffs = 0; -+ pRemapRegs->highRegOffs = 0; -+ -+ DB(mvOsPrintf("ahbToMbusRemapRegOffsGet: ERR. Invalid winNum %d\n", -+ winNum)); -+ return MV_NO_SUCH; -+ } -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvAhbToMbusAddDecShow - Print the AHB to MBus bridge address decode map. -+* -+* DESCRIPTION: -+* This function print the CPU address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvAhbToMbusAddDecShow(MV_VOID) -+{ -+ MV_AHB_TO_MBUS_DEC_WIN win; -+ MV_U32 winNum; -+ mvOsOutput( "\n" ); -+ mvOsOutput( "AHB To MBUS Bridge:\n" ); -+ mvOsOutput( "-------------------\n" ); -+ -+ for( winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS; winNum++ ) -+ { -+ memset( &win, 0, sizeof(MV_AHB_TO_MBUS_DEC_WIN) ); -+ -+ mvOsOutput( "win%d - ", winNum ); -+ -+ if( mvAhbToMbusWinGet( winNum, &win ) == MV_OK ) -+ { -+ if( win.enable ) -+ { -+ mvOsOutput( "%s base %08x, ", -+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); -+ mvOsOutput( "...." ); -+ mvSizePrint( win.addrWin.size ); -+ -+ mvOsOutput( "\n" ); -+ -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ } -+ } -+ -+} -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h 2010-11-09 20:28:07.872495394 +0100 -@@ -0,0 +1,130 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvAhbToMbush -+#define __INCmvAhbToMbush -+ -+/* includes */ -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/sys/mvAhbToMbusRegs.h" -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+ -+/* defines */ -+ -+#if defined(MV_88F1181) -+/* This enumerator defines the Marvell controller possible MBUS arbiter */ -+/* target ports. It is used to define crossbar priority scheame (pizza) */ -+typedef enum _mvMBusArbTargetId -+{ -+ DRAM_MBUS_ARB_TARGET = 0, /* Port 0 -> DRAM interface */ -+ TWSI_MBUS_ARB_TARGET = 1, /* Port 1 -> TWSI */ -+ ARM_MBUS_ARB_TARGET = 2, /* Port 2 -> ARM */ -+ PEX1_MBUS_ARB_TARGET = 3, /* Port 3 -> PCI Express 1 */ -+ PEX0_MBUS_ARB_TARGET = 4, /* Port 4 -> PCI Express0 */ -+ MAX_MBUS_ARB_TARGETS -+}MV_MBUS_ARB_TARGET; -+ -+typedef struct _mvMBusArbCtrl -+{ -+ MV_BOOL starvEn; -+ MV_BOOL highPrio; -+ MV_BOOL fixedRoundRobin; -+ -+}MV_MBUS_ARB_CTRL; -+ -+#endif /* #if defined(MV_88F1181) */ -+ -+typedef struct _mvAhbtoMbusDecWin -+{ -+ MV_TARGET target; -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+}MV_AHB_TO_MBUS_DEC_WIN; -+ -+/* mvAhbToMbus.h API list */ -+ -+MV_STATUS mvAhbToMbusInit(MV_VOID); -+MV_STATUS mvAhbToMbusWinSet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin); -+MV_STATUS mvAhbToMbusWinGet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin); -+MV_STATUS mvAhbToMbusWinEnable(MV_U32 winNum,MV_BOOL enable); -+MV_U32 mvAhbToMbusWinRemap(MV_U32 winNum, MV_ADDR_WIN *pAddrDecWin); -+MV_U32 mvAhbToMbusWinTargetGet(MV_TARGET target); -+MV_U32 mvAhbToMbusWinAvailGet(MV_VOID); -+MV_STATUS mvAhbToMbusWinTargetSwap(MV_TARGET target1,MV_TARGET target2); -+ -+#if defined(MV_88F1181) -+ -+MV_STATUS mvMbusArbSet(MV_MBUS_ARB_TARGET *pPizzaArbArray); -+MV_STATUS mvMbusArbCtrlSet(MV_MBUS_ARB_CTRL *ctrl); -+MV_STATUS mvMbusArbCtrlGet(MV_MBUS_ARB_CTRL *ctrl); -+ -+#endif /* #if defined(MV_88F1181) */ -+ -+ -+MV_VOID mvAhbToMbusAddDecShow(MV_VOID); -+ -+ -+#endif /* __INCmvAhbToMbush */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h 2010-11-09 20:28:07.902495495 +0100 -@@ -0,0 +1,143 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvAhbToMbusRegsh -+#define __INCmvAhbToMbusRegsh -+ -+/******************************/ -+/* ARM Address Map Registers */ -+/******************************/ -+ -+#define MAX_AHB_TO_MBUS_WINS 9 -+#define MV_AHB_TO_MBUS_INTREG_WIN 8 -+ -+ -+#define AHB_TO_MBUS_WIN_CTRL_REG(winNum) (0x20000 + (winNum)*0x10) -+#define AHB_TO_MBUS_WIN_BASE_REG(winNum) (0x20004 + (winNum)*0x10) -+#define AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum) (0x20008 + (winNum)*0x10) -+#define AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum) (0x2000C + (winNum)*0x10) -+#define AHB_TO_MBUS_WIN_INTEREG_REG 0x20080 -+ -+/* Window Control Register */ -+/* AHB_TO_MBUS_WIN_CTRL_REG (ATMWCR)*/ -+#define ATMWCR_WIN_ENABLE BIT0 /* Window Enable */ -+ -+#define ATMWCR_WIN_TARGET_OFFS 4 /* The target interface associated -+ with this window*/ -+#define ATMWCR_WIN_TARGET_MASK (0xf << ATMWCR_WIN_TARGET_OFFS) -+ -+#define ATMWCR_WIN_ATTR_OFFS 8 /* The target interface attributes -+ Associated with this window */ -+#define ATMWCR_WIN_ATTR_MASK (0xff << ATMWCR_WIN_ATTR_OFFS) -+ -+ -+/* -+Used with the Base register to set the address window size and location -+Must be programed from LSB to MSB as sequence of 1’s followed -+by sequence of 0’s. The number of 1’s specifies the size of the window -+in 64 KB granularity (e.g. a value of 0x00FF specifies 256 = 16 MB). -+ -+NOTE: A value of 0x0 specifies 64KB size. -+*/ -+#define ATMWCR_WIN_SIZE_OFFS 16 /* Window Size */ -+#define ATMWCR_WIN_SIZE_MASK (0xffff << ATMWCR_WIN_SIZE_OFFS) -+#define ATMWCR_WIN_SIZE_ALIGNMENT 0x10000 -+ -+/* Window Base Register */ -+/* AHB_TO_MBUS_WIN_BASE_REG (ATMWBR) */ -+ -+/* -+Used with the size field to set the address window size and location. -+Corresponds to transaction address[31:16] -+*/ -+#define ATMWBR_BASE_OFFS 16 /* Base Address */ -+#define ATMWBR_BASE_MASK (0xffff << ATMWBR_BASE_OFFS) -+#define ATMWBR_BASE_ALIGNMENT 0x10000 -+ -+/* Window Remap Low Register */ -+/* AHB_TO_MBUS_WIN_REMAP_LOW_REG (ATMWRLR) */ -+ -+/* -+Used with the size field to specifies address bits[31:0] to be driven to -+the target interface.: -+target_addr[31:16] = (addr[31:16] & size[15:0]) | (remap[31:16] & ~size[15:0]) -+*/ -+#define ATMWRLR_REMAP_LOW_OFFS 16 /* Remap Address */ -+#define ATMWRLR_REMAP_LOW_MASK (0xffff << ATMWRLR_REMAP_LOW_OFFS) -+#define ATMWRLR_REMAP_LOW_ALIGNMENT 0x10000 -+ -+/* Window Remap High Register */ -+/* AHB_TO_MBUS_WIN_REMAP_HIGH_REG (ATMWRHR) */ -+ -+/* -+Specifies address bits[63:32] to be driven to the target interface. -+target_addr[63:32] = (RemapHigh[31:0] -+*/ -+#define ATMWRHR_REMAP_HIGH_OFFS 0 /* Remap Address */ -+#define ATMWRHR_REMAP_HIGH_MASK (0xffffffff << ATMWRHR_REMAP_HIGH_OFFS) -+ -+ -+#endif /* __INCmvAhbToMbusRegsh */ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c 2010-11-09 20:28:07.942495425 +0100 -@@ -0,0 +1,1036 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+/* includes */ -+#include "ctrlEnv/sys/mvCpuIf.h" -+#include "ctrlEnv/sys/mvAhbToMbusRegs.h" -+#include "cpu/mvCpu.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "mvSysHwConfig.h" -+#include "mvSysDram.h" -+ -+/*#define MV_DEBUG*/ -+/* defines */ -+ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+/* locals */ -+/* static functions */ -+static MV_BOOL cpuTargetWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin); -+ -+MV_TARGET * sampleAtResetTargetArray; -+MV_TARGET sampleAtResetTargetArrayP[] = BOOT_TARGETS_NAME_ARRAY; -+MV_TARGET sampleAtResetTargetArray6180P[] = BOOT_TARGETS_NAME_ARRAY_6180; -+/******************************************************************************* -+* mvCpuIfInit - Initialize Controller CPU interface -+* -+* DESCRIPTION: -+* This function initialize Controller CPU interface: -+* 1. Set CPU interface configuration registers. -+* 2. Set CPU master Pizza arbiter control according to static -+* configuration described in configuration file. -+* 3. Opens CPU address decode windows. DRAM windows are assumed to be -+* already set (auto detection). -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvCpuIfInit(MV_CPU_DEC_WIN *cpuAddrWinMap) -+{ -+ MV_U32 regVal; -+ MV_TARGET target; -+ MV_ADDR_WIN addrWin; -+ -+ if (cpuAddrWinMap == NULL) -+ { -+ DB(mvOsPrintf("mvCpuIfInit:ERR. cpuAddrWinMap == NULL\n")); -+ return MV_ERROR; -+ } -+ -+ /*Initialize the boot target array according to device type*/ -+ if(mvCtrlModelGet() == MV_6180_DEV_ID) -+ sampleAtResetTargetArray = sampleAtResetTargetArray6180P; -+ else -+ sampleAtResetTargetArray = sampleAtResetTargetArrayP; -+ -+ /* Set ARM Configuration register */ -+ regVal = MV_REG_READ(CPU_CONFIG_REG); -+ regVal &= ~CPU_CONFIG_DEFAULT_MASK; -+ regVal |= CPU_CONFIG_DEFAULT; -+ MV_REG_WRITE(CPU_CONFIG_REG,regVal); -+ -+ /* First disable all CPU target windows */ -+ for (target = 0; cpuAddrWinMap[target].enable != TBL_TERM; target++) -+ { -+ if ((MV_TARGET_IS_DRAM(target))||(target == INTER_REGS)) -+ { -+ continue; -+ } -+ -+#if defined(MV_MEM_OVER_PCI_WA) || defined(MV_UART_OVER_PCI_WA) -+ /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ -+ if (MV_TARGET_IS_PCI(target)) -+ { -+ continue; -+ } -+#endif -+ -+#if defined(MV_MEM_OVER_PEX_WA) || defined(MV_UART_OVER_PEX_WA) -+ /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ -+ if (MV_TARGET_IS_PEX(target)) -+ { -+ continue; -+ } -+#endif -+#if defined(MV_RUN_FROM_FLASH) -+ /* Don't disable the boot device. */ -+ if (target == DEV_BOOCS) -+ { -+ continue; -+ } -+#endif /* MV_RUN_FROM_FLASH */ -+ mvCpuIfTargetWinEnable(MV_CHANGE_BOOT_CS(target),MV_FALSE); -+ } -+ -+#if defined(MV_RUN_FROM_FLASH) -+ /* Resize the bootcs windows before other windows, because this */ -+ /* window is enabled and will cause an overlap if not resized. */ -+ target = DEV_BOOCS; -+ -+ if (MV_OK != mvCpuIfTargetWinSet(target, &cpuAddrWinMap[target])) -+ { -+ DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinSet fail\n")); -+ return MV_ERROR; -+ } -+ -+ addrWin.baseLow = cpuAddrWinMap[target].addrWin.baseLow; -+ addrWin.baseHigh = cpuAddrWinMap[target].addrWin.baseHigh; -+ if (0xffffffff == mvAhbToMbusWinRemap(cpuAddrWinMap[target].winNum ,&addrWin)) -+ { -+ DB(mvOsPrintf("mvCpuIfInit:WARN. mvAhbToMbusWinRemap can't remap winNum=%d\n", -+ cpuAddrWinMap[target].winNum)); -+ } -+ -+#endif /* MV_RUN_FROM_FLASH */ -+ -+ /* Go through all targets in user table until table terminator */ -+ for (target = 0; cpuAddrWinMap[target].enable != TBL_TERM; target++) -+ { -+ -+#if defined(MV_RUN_FROM_FLASH) -+ if (target == DEV_BOOCS) -+ { -+ continue; -+ } -+#endif /* MV_RUN_FROM_FLASH */ -+ -+ /* if DRAM auto sizing is used do not initialized DRAM target windows, */ -+ /* assuming this already has been done earlier. */ -+#ifdef MV_DRAM_AUTO_SIZE -+ if (MV_TARGET_IS_DRAM(target)) -+ { -+ continue; -+ } -+#endif -+ -+#if defined(MV_MEM_OVER_PCI_WA) || defined(MV_UART_OVER_PCI_WA) -+ /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ -+ if (MV_TARGET_IS_PCI(target)) -+ { -+ continue; -+ } -+#endif -+ -+#if defined(MV_MEM_OVER_PEX_WA) || defined(MV_UART_OVER_PEX_WA) -+ /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ -+ if (MV_TARGET_IS_PEX(target)) -+ { -+ continue; -+ } -+#endif -+ /* If the target attribute is the same as the boot device attribute */ -+ /* then it's stays disable */ -+ if (MV_TARGET_IS_AS_BOOT(target)) -+ { -+ continue; -+ } -+ -+ if((0 == cpuAddrWinMap[target].addrWin.size) || -+ (DIS == cpuAddrWinMap[target].enable)) -+ -+ { -+ if (MV_OK != mvCpuIfTargetWinEnable(target, MV_FALSE)) -+ { -+ DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinEnable fail\n")); -+ return MV_ERROR; -+ } -+ -+ } -+ else -+ { -+ if (MV_OK != mvCpuIfTargetWinSet(target, &cpuAddrWinMap[target])) -+ { -+ DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinSet fail\n")); -+ return MV_ERROR; -+ } -+ -+ addrWin.baseLow = cpuAddrWinMap[target].addrWin.baseLow; -+ addrWin.baseHigh = cpuAddrWinMap[target].addrWin.baseHigh; -+ if (0xffffffff == mvAhbToMbusWinRemap(cpuAddrWinMap[target].winNum ,&addrWin)) -+ { -+ DB(mvOsPrintf("mvCpuIfInit:WARN. mvAhbToMbusWinRemap can't remap winNum=%d\n", -+ cpuAddrWinMap[target].winNum)); -+ } -+ -+ -+ } -+ } -+ -+ return MV_OK; -+ -+ -+} -+ -+ -+/******************************************************************************* -+* mvCpuIfTargetWinSet - Set CPU-to-peripheral target address window -+* -+* DESCRIPTION: -+* This function sets a peripheral target (e.g. SDRAM bank0, PCI0_MEM0) -+* address window, also known as address decode window. -+* A new address decode window is set for specified target address window. -+* If address decode window parameter structure enables the window, -+* the routine will also enable the target window, allowing CPU to access -+* the target window. -+* -+* INPUT: -+* target - Peripheral target enumerator. -+* pAddrDecWin - CPU target window data structure. -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_OK if CPU target window was set correctly, MV_ERROR in case of -+* address window overlapps with other active CPU target window or -+* trying to assign 36bit base address while CPU does not support that. -+* The function returns MV_NOT_SUPPORTED, if the target is unsupported. -+* -+*******************************************************************************/ -+MV_STATUS mvCpuIfTargetWinSet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin) -+{ -+ MV_AHB_TO_MBUS_DEC_WIN decWin; -+ MV_U32 existingWinNum; -+ MV_DRAM_DEC_WIN addrDecWin; -+ -+ target = MV_CHANGE_BOOT_CS(target); -+ -+ /* Check parameters */ -+ if (target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvCpuIfTargetWinSet: target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ /* 2) Check if the requested window overlaps with current windows */ -+ if (MV_TRUE == cpuTargetWinOverlap(target, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("mvCpuIfTargetWinSet: ERR. Target %d overlap\n", target); -+ return MV_BAD_PARAM; -+ } -+ -+ if (MV_TARGET_IS_DRAM(target)) -+ { -+ /* copy relevant data to MV_DRAM_DEC_WIN structure */ -+ addrDecWin.addrWin.baseHigh = pAddrDecWin->addrWin.baseHigh; -+ addrDecWin.addrWin.baseLow = pAddrDecWin->addrWin.baseLow; -+ addrDecWin.addrWin.size = pAddrDecWin->addrWin.size; -+ addrDecWin.enable = pAddrDecWin->enable; -+ -+ -+ if (mvDramIfWinSet(target,&addrDecWin) != MV_OK); -+ { -+ mvOsPrintf("mvCpuIfTargetWinSet: mvDramIfWinSet Failed\n"); -+ return MV_ERROR; -+ } -+ -+ } -+ else -+ { -+ /* copy relevant data to MV_AHB_TO_MBUS_DEC_WIN structure */ -+ decWin.addrWin.baseLow = pAddrDecWin->addrWin.baseLow; -+ decWin.addrWin.baseHigh = pAddrDecWin->addrWin.baseHigh; -+ decWin.addrWin.size = pAddrDecWin->addrWin.size; -+ decWin.enable = pAddrDecWin->enable; -+ decWin.target = target; -+ -+ existingWinNum = mvAhbToMbusWinTargetGet(target); -+ -+ /* check if there is already another Window configured -+ for this target */ -+ if ((existingWinNum < MAX_AHB_TO_MBUS_WINS )&& -+ (existingWinNum != pAddrDecWin->winNum)) -+ { -+ /* if we want to enable the new winow number -+ passed by the user , then the old one should -+ be disabled */ -+ if (MV_TRUE == pAddrDecWin->enable) -+ { -+ /* be sure it is disabled */ -+ mvAhbToMbusWinEnable(existingWinNum , MV_FALSE); -+ } -+ } -+ -+ if (mvAhbToMbusWinSet(pAddrDecWin->winNum,&decWin) != MV_OK) -+ { -+ mvOsPrintf("mvCpuIfTargetWinSet: mvAhbToMbusWinSet Failed\n"); -+ return MV_ERROR; -+ } -+ -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCpuIfTargetWinGet - Get CPU-to-peripheral target address window -+* -+* DESCRIPTION: -+* Get the CPU peripheral target address window. -+* -+* INPUT: -+* target - Peripheral target enumerator -+* -+* OUTPUT: -+* pAddrDecWin - CPU target window information data structure. -+* -+* RETURN: -+* MV_OK if target exist, MV_ERROR otherwise. -+* -+*******************************************************************************/ -+MV_STATUS mvCpuIfTargetWinGet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin) -+{ -+ -+ MV_U32 winNum=0xffffffff; -+ MV_AHB_TO_MBUS_DEC_WIN decWin; -+ MV_DRAM_DEC_WIN addrDecWin; -+ -+ target = MV_CHANGE_BOOT_CS(target); -+ -+ /* Check parameters */ -+ if (target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvCpuIfTargetWinGet: target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ if (MV_TARGET_IS_DRAM(target)) -+ { -+ if (mvDramIfWinGet(target,&addrDecWin) != MV_OK) -+ { -+ mvOsPrintf("mvCpuIfTargetWinGet: Failed to get window target %d\n", -+ target); -+ return MV_ERROR; -+ } -+ -+ /* copy relevant data to MV_CPU_DEC_WIN structure */ -+ pAddrDecWin->addrWin.baseLow = addrDecWin.addrWin.baseLow; -+ pAddrDecWin->addrWin.baseHigh = addrDecWin.addrWin.baseHigh; -+ pAddrDecWin->addrWin.size = addrDecWin.addrWin.size; -+ pAddrDecWin->enable = addrDecWin.enable; -+ pAddrDecWin->winNum = 0xffffffff; -+ -+ } -+ else -+ { -+ /* get the Window number associated with this target */ -+ -+ winNum = mvAhbToMbusWinTargetGet(target); -+ if (winNum >= MAX_AHB_TO_MBUS_WINS) -+ { -+ return MV_NO_SUCH; -+ -+ } -+ -+ if (mvAhbToMbusWinGet(winNum , &decWin) != MV_OK) -+ { -+ mvOsPrintf("%s: mvAhbToMbusWinGet Failed at winNum = %d\n", -+ __FUNCTION__, winNum); -+ return MV_ERROR; -+ -+ } -+ -+ /* copy relevant data to MV_CPU_DEC_WIN structure */ -+ pAddrDecWin->addrWin.baseLow = decWin.addrWin.baseLow; -+ pAddrDecWin->addrWin.baseHigh = decWin.addrWin.baseHigh; -+ pAddrDecWin->addrWin.size = decWin.addrWin.size; -+ pAddrDecWin->enable = decWin.enable; -+ pAddrDecWin->winNum = winNum; -+ -+ } -+ -+ -+ -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvCpuIfTargetWinEnable - Enable/disable a CPU address decode window -+* -+* DESCRIPTION: -+* This function enable/disable a CPU address decode window. -+* if parameter 'enable' == MV_TRUE the routine will enable the -+* window, thus enabling CPU accesses (before enabling the window it is -+* tested for overlapping). Otherwise, the window will be disabled. -+* -+* INPUT: -+* target - Peripheral target enumerator. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_ERROR if protection window number was wrong, or the window -+* overlapps other target window. -+* -+*******************************************************************************/ -+MV_STATUS mvCpuIfTargetWinEnable(MV_TARGET target,MV_BOOL enable) -+{ -+ MV_U32 winNum, temp; -+ MV_CPU_DEC_WIN addrDecWin; -+ -+ target = MV_CHANGE_BOOT_CS(target); -+ -+ /* Check parameters */ -+ if (target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvCpuIfTargetWinEnable: target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ /* get the window and check if it exist */ -+ temp = mvCpuIfTargetWinGet(target, &addrDecWin); -+ if (MV_NO_SUCH == temp) -+ { -+ return (enable? MV_ERROR: MV_OK); -+ } -+ else if( MV_OK != temp) -+ { -+ mvOsPrintf("%s: ERR. Getting target %d failed.\n",__FUNCTION__, target); -+ return MV_ERROR; -+ } -+ -+ -+ /* check overlap */ -+ -+ if (MV_TRUE == enable) -+ { -+ if (MV_TRUE == cpuTargetWinOverlap(target, &addrDecWin.addrWin)) -+ { -+ DB(mvOsPrintf("%s: ERR. Target %d overlap\n",__FUNCTION__, target)); -+ return MV_ERROR; -+ } -+ -+ } -+ -+ -+ if (MV_TARGET_IS_DRAM(target)) -+ { -+ if (mvDramIfWinEnable(target , enable) != MV_OK) -+ { -+ mvOsPrintf("mvCpuIfTargetWinGet: mvDramIfWinEnable Failed at \n"); -+ return MV_ERROR; -+ -+ } -+ -+ } -+ else -+ { -+ /* get the Window number associated with this target */ -+ -+ winNum = mvAhbToMbusWinTargetGet(target); -+ -+ if (winNum >= MAX_AHB_TO_MBUS_WINS) -+ { -+ return (enable? MV_ERROR: MV_OK); -+ } -+ -+ if (mvAhbToMbusWinEnable(winNum , enable) != MV_OK) -+ { -+ mvOsPrintf("mvCpuIfTargetWinGet: Failed to enable window = %d\n", -+ winNum); -+ return MV_ERROR; -+ -+ } -+ -+ } -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvCpuIfTargetWinSizeGet - Get CPU target address window size -+* -+* DESCRIPTION: -+* Get the size of CPU-to-peripheral target window. -+* -+* INPUT: -+* target - Peripheral target enumerator -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit size. Function also returns '0' if window is closed. -+* Function returns 0xFFFFFFFF in case of an error. -+* -+*******************************************************************************/ -+MV_U32 mvCpuIfTargetWinSizeGet(MV_TARGET target) -+{ -+ MV_CPU_DEC_WIN addrDecWin; -+ -+ target = MV_CHANGE_BOOT_CS(target); -+ -+ /* Check parameters */ -+ if (target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvCpuIfTargetWinSizeGet: target %d is Illigal\n", target); -+ return 0; -+ } -+ -+ /* Get the winNum window */ -+ if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) -+ { -+ mvOsPrintf("mvCpuIfTargetWinSizeGet:ERR. Getting target %d failed.\n", -+ target); -+ return 0; -+ } -+ -+ /* Check if window is enabled */ -+ if (addrDecWin.enable == MV_TRUE) -+ { -+ return (addrDecWin.addrWin.size); -+ } -+ else -+ { -+ return 0; /* Window disabled. return 0 */ -+ } -+} -+ -+/******************************************************************************* -+* mvCpuIfTargetWinBaseLowGet - Get CPU target address window base low -+* -+* DESCRIPTION: -+* CPU-to-peripheral target address window base is constructed of -+* two parts: Low and high. -+* This function gets the CPU peripheral target low base address. -+* -+* INPUT: -+* target - Peripheral target enumerator -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit low base address. -+* -+*******************************************************************************/ -+MV_U32 mvCpuIfTargetWinBaseLowGet(MV_TARGET target) -+{ -+ MV_CPU_DEC_WIN addrDecWin; -+ -+ target = MV_CHANGE_BOOT_CS(target); -+ -+ /* Check parameters */ -+ if (target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvCpuIfTargetWinBaseLowGet: target %d is Illigal\n", target); -+ return 0xffffffff; -+ } -+ -+ /* Get the target window */ -+ if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) -+ { -+ mvOsPrintf("mvCpuIfTargetWinBaseLowGet:ERR. Getting target %d failed.\n", -+ target); -+ return 0xffffffff; -+ } -+ -+ if (MV_FALSE == addrDecWin.enable) -+ { -+ return 0xffffffff; -+ } -+ return (addrDecWin.addrWin.baseLow); -+} -+ -+/******************************************************************************* -+* mvCpuIfTargetWinBaseHighGet - Get CPU target address window base high -+* -+* DESCRIPTION: -+* CPU-to-peripheral target address window base is constructed of -+* two parts: Low and high. -+* This function gets the CPU peripheral target high base address. -+* -+* INPUT: -+* target - Peripheral target enumerator -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit high base address. -+* -+*******************************************************************************/ -+MV_U32 mvCpuIfTargetWinBaseHighGet(MV_TARGET target) -+{ -+ MV_CPU_DEC_WIN addrDecWin; -+ -+ target = MV_CHANGE_BOOT_CS(target); -+ -+ /* Check parameters */ -+ if (target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvCpuIfTargetWinBaseLowGet: target %d is Illigal\n", target); -+ return 0xffffffff; -+ } -+ -+ /* Get the target window */ -+ if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) -+ { -+ mvOsPrintf("mvCpuIfTargetWinBaseHighGet:ERR. Getting target %d failed.\n", -+ target); -+ return 0xffffffff; -+ } -+ -+ if (MV_FALSE == addrDecWin.enable) -+ { -+ return 0; -+ } -+ -+ return (addrDecWin.addrWin.baseHigh); -+} -+ -+#if defined(MV_INCLUDE_PEX) -+/******************************************************************************* -+* mvCpuIfPexRemap - Set CPU remap register for address windows. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* pexTarget - Peripheral target enumerator. Must be a PEX target. -+* pAddrDecWin - CPU target window information data structure. -+* Note that caller has to fill in the base field only. The -+* size field is ignored. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR if target is not a PEX one, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_U32 mvCpuIfPexRemap(MV_TARGET pexTarget, MV_ADDR_WIN *pAddrDecWin) -+{ -+ MV_U32 winNum; -+ -+ /* Check parameters */ -+ -+ if (mvCtrlPexMaxIfGet() > 1) -+ { -+ if ((!MV_TARGET_IS_PEX1(pexTarget))&&(!MV_TARGET_IS_PEX0(pexTarget))) -+ { -+ mvOsPrintf("mvCpuIfPexRemap: target %d is Illigal\n",pexTarget); -+ return 0xffffffff; -+ } -+ -+ } -+ else -+ { -+ if (!MV_TARGET_IS_PEX0(pexTarget)) -+ { -+ mvOsPrintf("mvCpuIfPexRemap: target %d is Illigal\n",pexTarget); -+ return 0xffffffff; -+ } -+ -+ } -+ -+ /* get the Window number associated with this target */ -+ winNum = mvAhbToMbusWinTargetGet(pexTarget); -+ -+ if (winNum >= MAX_AHB_TO_MBUS_WINS) -+ { -+ mvOsPrintf("mvCpuIfPexRemap: mvAhbToMbusWinTargetGet Failed\n"); -+ return 0xffffffff; -+ -+ } -+ -+ return mvAhbToMbusWinRemap(winNum , pAddrDecWin); -+} -+ -+#endif -+ -+#if defined(MV_INCLUDE_PCI) -+/******************************************************************************* -+* mvCpuIfPciRemap - Set CPU remap register for address windows. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* pciTarget - Peripheral target enumerator. Must be a PCI target. -+* pAddrDecWin - CPU target window information data structure. -+* Note that caller has to fill in the base field only. The -+* size field is ignored. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR if target is not a PCI one, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_U32 mvCpuIfPciRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin) -+{ -+ MV_U32 winNum; -+ -+ /* Check parameters */ -+ if (!MV_TARGET_IS_PCI(pciTarget)) -+ { -+ mvOsPrintf("mvCpuIfPciRemap: target %d is Illigal\n",pciTarget); -+ return 0xffffffff; -+ } -+ -+ /* get the Window number associated with this target */ -+ winNum = mvAhbToMbusWinTargetGet(pciTarget); -+ -+ if (winNum >= MAX_AHB_TO_MBUS_WINS) -+ { -+ mvOsPrintf("mvCpuIfPciRemap: mvAhbToMbusWinTargetGet Failed\n"); -+ return 0xffffffff; -+ -+ } -+ -+ return mvAhbToMbusWinRemap(winNum , pAddrDecWin); -+} -+#endif /* MV_INCLUDE_PCI */ -+ -+ -+/******************************************************************************* -+* mvCpuIfPciIfRemap - Set CPU remap register for address windows. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* pciTarget - Peripheral target enumerator. Must be a PCI target. -+* pAddrDecWin - CPU target window information data structure. -+* Note that caller has to fill in the base field only. The -+* size field is ignored. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR if target is not a PCI one, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_U32 mvCpuIfPciIfRemap(MV_TARGET pciIfTarget, MV_ADDR_WIN *pAddrDecWin) -+{ -+#if defined(MV_INCLUDE_PEX) -+ if (MV_TARGET_IS_PEX(pciIfTarget)) -+ { -+ return mvCpuIfPexRemap(pciIfTarget,pAddrDecWin); -+ } -+#endif -+#if defined(MV_INCLUDE_PCI) -+ -+ if (MV_TARGET_IS_PCI(pciIfTarget)) -+ { -+ return mvCpuIfPciRemap(pciIfTarget,pAddrDecWin); -+ } -+#endif -+ return 0; -+} -+ -+ -+ -+/******************************************************************************* -+* mvCpuIfTargetOfBaseAddressGet - Get the target according to base address -+* -+* DESCRIPTION: -+* -+* INPUT: -+* baseAddress - base address to be checked -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* the target number that baseAddress belongs to or MAX_TARGETS is not -+* found -+* -+*******************************************************************************/ -+ -+MV_TARGET mvCpuIfTargetOfBaseAddressGet(MV_U32 baseAddress) -+{ -+ MV_CPU_DEC_WIN win; -+ MV_U32 target; -+ -+ for( target = 0; target < MAX_TARGETS; target++ ) -+ { -+ if( mvCpuIfTargetWinGet( target, &win ) == MV_OK ) -+ { -+ if( win.enable ) -+ { -+ if ((baseAddress >= win.addrWin.baseLow) && -+ (baseAddress < win.addrWin.baseLow + win.addrWin.size)) break; -+ } -+ } -+ else return MAX_TARGETS; -+ -+ } -+ -+ return target; -+} -+/******************************************************************************* -+* cpuTargetWinOverlap - Detect CPU address decode windows overlapping -+* -+* DESCRIPTION: -+* An unpredicted behaviur is expected in case CPU address decode -+* windows overlapps. -+* This function detects CPU address decode windows overlapping of a -+* specified target. The function does not check the target itself for -+* overlapping. The function also skipps disabled address decode windows. -+* -+* INPUT: -+* target - Peripheral target enumerator. -+* pAddrDecWin - An address decode window struct. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlaps current address -+* decode map, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+static MV_BOOL cpuTargetWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 targetNum; -+ MV_CPU_DEC_WIN addrDecWin; -+ MV_STATUS status; -+ -+ -+ for(targetNum = 0; targetNum < MAX_TARGETS; targetNum++) -+ { -+#if defined(MV_RUN_FROM_FLASH) -+ if(MV_TARGET_IS_AS_BOOT(target)) -+ { -+ if (MV_CHANGE_BOOT_CS(targetNum) == target) -+ continue; -+ } -+#endif /* MV_RUN_FROM_FLASH */ -+ -+ /* don't check our target or illegal targets */ -+ if (targetNum == target) -+ { -+ continue; -+ } -+ -+ /* Get window parameters */ -+ status = mvCpuIfTargetWinGet(targetNum, &addrDecWin); -+ if(MV_NO_SUCH == status) -+ { -+ continue; -+ } -+ if(MV_OK != status) -+ { -+ DB(mvOsPrintf("cpuTargetWinOverlap: ERR. TargetWinGet failed\n")); -+ return MV_TRUE; -+ } -+ -+ /* Do not check disabled windows */ -+ if (MV_FALSE == addrDecWin.enable) -+ { -+ continue; -+ } -+ -+ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) -+ { -+ DB(mvOsPrintf( -+ "cpuTargetWinOverlap: Required target %d overlap current %d\n", -+ target, targetNum)); -+ return MV_TRUE; -+ } -+ } -+ -+ return MV_FALSE; -+ -+} -+ -+/******************************************************************************* -+* mvCpuIfAddDecShow - Print the CPU address decode map. -+* -+* DESCRIPTION: -+* This function print the CPU address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvCpuIfAddDecShow(MV_VOID) -+{ -+ MV_CPU_DEC_WIN win; -+ MV_U32 target; -+ mvOsOutput( "\n" ); -+ mvOsOutput( "CPU Interface\n" ); -+ mvOsOutput( "-------------\n" ); -+ -+ for( target = 0; target < MAX_TARGETS; target++ ) -+ { -+ -+ memset( &win, 0, sizeof(MV_CPU_DEC_WIN) ); -+ -+ mvOsOutput( "%s ",mvCtrlTargetNameGet(target)); -+ mvOsOutput( "...." ); -+ -+ if( mvCpuIfTargetWinGet( target, &win ) == MV_OK ) -+ { -+ if( win.enable ) -+ { -+ mvOsOutput( "base %08x, ", win.addrWin.baseLow ); -+ mvSizePrint( win.addrWin.size ); -+ mvOsOutput( "\n" ); -+ -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ } -+ else if( mvCpuIfTargetWinGet( target, &win ) == MV_NO_SUCH ) -+ { -+ mvOsOutput( "no such\n" ); -+ } -+ } -+} -+ -+/******************************************************************************* -+* mvCpuIfEnablePex - Enable PCI Express. -+* -+* DESCRIPTION: -+* This function Enable PCI Express. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* pexType - MV_PEX_ROOT_COMPLEX - root complex device -+* MV_PEX_END_POINT - end point device -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+#if defined(MV_INCLUDE_PEX) -+MV_VOID mvCpuIfEnablePex(MV_U32 pexIf, MV_PEX_TYPE pexType) -+{ -+ /* Set pex mode incase S@R not exist */ -+ if( pexType == MV_PEX_END_POINT) -+ { -+ MV_REG_BIT_RESET(PEX_CTRL_REG(pexIf),PXCR_DEV_TYPE_CTRL_MASK); -+ /* Change pex mode in capability reg */ -+ MV_REG_BIT_RESET(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_CAPABILITY_REG), BIT22); -+ MV_REG_BIT_SET(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_CAPABILITY_REG), BIT20); -+ -+ } -+ else -+ { -+ MV_REG_BIT_SET(PEX_CTRL_REG(pexIf),PXCR_DEV_TYPE_CTRL_MASK); -+ } -+ -+ /* CPU config register Pex enable */ -+ MV_REG_BIT_SET(CPU_CTRL_STAT_REG,CCSR_PCI_ACCESS_MASK); -+} -+#endif -+ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h 2010-11-09 20:28:07.982495689 +0100 -@@ -0,0 +1,120 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvCpuIfh -+#define __INCmvCpuIfh -+ -+/* includes */ -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/sys/mvCpuIfRegs.h" -+#include "ctrlEnv/sys/mvAhbToMbus.h" -+#include "ddr2/mvDramIf.h" -+#include "ctrlEnv/sys/mvSysDram.h" -+#if defined(MV_INCLUDE_PEX) -+#include "pex/mvPex.h" -+#endif -+ -+/* defines */ -+ -+/* typedefs */ -+/* This structure describes CPU interface address decode window */ -+typedef struct _mvCpuIfDecWin -+{ -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_U32 winNum; /* Window Number in the AHB To Mbus bridge */ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+}MV_CPU_DEC_WIN; -+ -+ -+ -+/* mvCpuIfLib.h API list */ -+ -+/* mvCpuIfLib.h API list */ -+ -+MV_STATUS mvCpuIfInit(MV_CPU_DEC_WIN *cpuAddrWinMap); -+MV_STATUS mvCpuIfTargetWinSet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin); -+MV_STATUS mvCpuIfTargetWinGet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin); -+MV_STATUS mvCpuIfTargetWinEnable(MV_TARGET target,MV_BOOL enable); -+MV_U32 mvCpuIfTargetWinSizeGet(MV_TARGET target); -+MV_U32 mvCpuIfTargetWinBaseLowGet(MV_TARGET target); -+MV_U32 mvCpuIfTargetWinBaseHighGet(MV_TARGET target); -+MV_TARGET mvCpuIfTargetOfBaseAddressGet(MV_U32 baseAddress); -+#if defined(MV_INCLUDE_PEX) -+MV_U32 mvCpuIfPexRemap(MV_TARGET pexTarget, MV_ADDR_WIN *pAddrDecWin); -+MV_VOID mvCpuIfEnablePex(MV_U32 pexIf, MV_PEX_TYPE pexType); -+#endif -+#if defined(MV_INCLUDE_PCI) -+MV_U32 mvCpuIfPciRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin); -+#endif -+MV_U32 mvCpuIfPciIfRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin); -+ -+MV_VOID mvCpuIfAddDecShow(MV_VOID); -+ -+#if defined(MV88F6281) -+MV_STATUS mvCpuIfBridgeReorderWAInit(void); -+#endif -+ -+#endif /* __INCmvCpuIfh */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h 2010-11-09 20:28:08.012495399 +0100 -@@ -0,0 +1,304 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvCpuIfRegsh -+#define __INCmvCpuIfRegsh -+ -+/****************************************/ -+/* ARM Control and Status Registers Map */ -+/****************************************/ -+ -+#define CPU_CONFIG_REG 0x20100 -+#define CPU_CTRL_STAT_REG 0x20104 -+#define CPU_RSTOUTN_MASK_REG 0x20108 -+#define CPU_SYS_SOFT_RST_REG 0x2010C -+#define CPU_AHB_MBUS_CAUSE_INT_REG 0x20110 -+#define CPU_AHB_MBUS_MASK_INT_REG 0x20114 -+#define CPU_FTDLL_CONFIG_REG 0x20120 -+#define CPU_L2_CONFIG_REG 0x20128 -+ -+ -+ -+/* ARM Configuration register */ -+/* CPU_CONFIG_REG (CCR) */ -+ -+ -+/* Reset vector location */ -+#define CCR_VEC_INIT_LOC_OFFS 1 -+#define CCR_VEC_INIT_LOC_MASK BIT1 -+/* reset at 0x00000000 */ -+#define CCR_VEC_INIT_LOC_0000 (0 << CCR_VEC_INIT_LOC_OFFS) -+/* reset at 0xFFFF0000 */ -+#define CCR_VEC_INIT_LOC_FF00 (1 << CCR_VEC_INIT_LOC_OFFS) -+ -+ -+#define CCR_AHB_ERROR_PROP_OFFS 2 -+#define CCR_AHB_ERROR_PROP_MASK BIT2 -+/* Erros are not propogated to AHB */ -+#define CCR_AHB_ERROR_PROP_NO_INDICATE (0 << CCR_AHB_ERROR_PROP_OFFS) -+/* Erros are propogated to AHB */ -+#define CCR_AHB_ERROR_PROP_INDICATE (1 << CCR_AHB_ERROR_PROP_OFFS) -+ -+ -+#define CCR_ENDIAN_INIT_OFFS 3 -+#define CCR_ENDIAN_INIT_MASK BIT3 -+#define CCR_ENDIAN_INIT_LITTLE (0 << CCR_ENDIAN_INIT_OFFS) -+#define CCR_ENDIAN_INIT_BIG (1 << CCR_ENDIAN_INIT_OFFS) -+ -+ -+#define CCR_INCR_EN_OFFS 4 -+#define CCR_INCR_EN_MASK BIT4 -+#define CCR_INCR_EN BIT4 -+ -+ -+#define CCR_NCB_BLOCKING_OFFS 5 -+#define CCR_NCB_BLOCKING_MASK (1 << CCR_NCB_BLOCKING_OFFS) -+#define CCR_NCB_BLOCKING_NON (0 << CCR_NCB_BLOCKING_OFFS) -+#define CCR_NCB_BLOCKING_EN (1 << CCR_NCB_BLOCKING_OFFS) -+ -+#define CCR_CPU_2_MBUSL_TICK_DRV_OFFS 8 -+#define CCR_CPU_2_MBUSL_TICK_DRV_MASK (0xF << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) -+#define CCR_CPU_2_MBUSL_TICK_SMPL_OFFS 12 -+#define CCR_CPU_2_MBUSL_TICK_SMPL_MASK (0xF << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS) -+#define CCR_ICACH_PREF_BUF_ENABLE BIT16 -+#define CCR_DCACH_PREF_BUF_ENABLE BIT17 -+ -+/* Ratio options for CPU to DDR for 6281/6192/6190 */ -+#define CPU_2_DDR_CLK_1x3 4 -+#define CPU_2_DDR_CLK_1x4 6 -+ -+/* Ratio options for CPU to DDR for 6281 only */ -+#define CPU_2_DDR_CLK_2x9 7 -+#define CPU_2_DDR_CLK_1x5 8 -+#define CPU_2_DDR_CLK_1x6 9 -+ -+/* Ratio options for CPU to DDR for 6180 only */ -+#define CPU_2_DDR_CLK_1x3_1 0x5 -+#define CPU_2_DDR_CLK_1x4_1 0x6 -+ -+/* Default values for CPU to Mbus-L DDR Interface Tick Driver and */ -+/* CPU to Mbus-L Tick Sample fields in CPU config register */ -+ -+#define TICK_DRV_1x1 0 -+#define TICK_DRV_1x2 0 -+#define TICK_DRV_1x3 1 -+#define TICK_DRV_1x4 2 -+#define TICK_SMPL_1x1 0 -+#define TICK_SMPL_1x2 1 -+#define TICK_SMPL_1x3 0 -+#define TICK_SMPL_1x4 0 -+ -+#define CPU_2_MBUSL_DDR_CLK_1x2 \ -+ ((TICK_DRV_1x2 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \ -+ (TICK_SMPL_1x2 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS)) -+#define CPU_2_MBUSL_DDR_CLK_1x3 \ -+ ((TICK_DRV_1x3 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \ -+ (TICK_SMPL_1x3 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS)) -+#define CPU_2_MBUSL_DDR_CLK_1x4 \ -+ ((TICK_DRV_1x4 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \ -+ (TICK_SMPL_1x4 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS)) -+ -+/* ARM Control and Status register */ -+/* CPU_CTRL_STAT_REG (CCSR) */ -+ -+ -+/* -+This is used to block PCI express\PCI from access Socrates/Feroceon GP -+while ARM boot is still in progress -+*/ -+ -+#define CCSR_PCI_ACCESS_OFFS 0 -+#define CCSR_PCI_ACCESS_MASK BIT0 -+#define CCSR_PCI_ACCESS_ENABLE (0 << CCSR_PCI_ACCESS_OFFS) -+#define CCSR_PCI_ACCESS_DISBALE (1 << CCSR_PCI_ACCESS_OFFS) -+ -+#define CCSR_ARM_RESET BIT1 -+#define CCSR_SELF_INT BIT2 -+#define CCSR_BIG_ENDIAN BIT15 -+ -+ -+/* RSTOUTn Mask Register */ -+/* CPU_RSTOUTN_MASK_REG (CRMR) */ -+ -+#define CRMR_PEX_RST_OUT_OFFS 0 -+#define CRMR_PEX_RST_OUT_MASK BIT0 -+#define CRMR_PEX_RST_OUT_ENABLE (1 << CRMR_PEX_RST_OUT_OFFS) -+#define CRMR_PEX_RST_OUT_DISABLE (0 << CRMR_PEX_RST_OUT_OFFS) -+ -+#define CRMR_WD_RST_OUT_OFFS 1 -+#define CRMR_WD_RST_OUT_MASK BIT1 -+#define CRMR_WD_RST_OUT_ENABLE (1 << CRMR_WD_RST_OUT_OFFS) -+#define CRMR_WD_RST_OUT_DISBALE (0 << CRMR_WD_RST_OUT_OFFS) -+ -+#define CRMR_SOFT_RST_OUT_OFFS 2 -+#define CRMR_SOFT_RST_OUT_MASK BIT2 -+#define CRMR_SOFT_RST_OUT_ENABLE (1 << CRMR_SOFT_RST_OUT_OFFS) -+#define CRMR_SOFT_RST_OUT_DISBALE (0 << CRMR_SOFT_RST_OUT_OFFS) -+ -+/* System Software Reset Register */ -+/* CPU_SYS_SOFT_RST_REG (CSSRR) */ -+ -+#define CSSRR_SYSTEM_SOFT_RST BIT0 -+ -+/* AHB to Mbus Bridge Interrupt Cause Register*/ -+/* CPU_AHB_MBUS_CAUSE_INT_REG (CAMCIR) */ -+ -+#define CAMCIR_ARM_SELF_INT BIT0 -+#define CAMCIR_ARM_TIMER0_INT_REQ BIT1 -+#define CAMCIR_ARM_TIMER1_INT_REQ BIT2 -+#define CAMCIR_ARM_WD_TIMER_INT_REQ BIT3 -+ -+ -+/* AHB to Mbus Bridge Interrupt Mask Register*/ -+/* CPU_AHB_MBUS_MASK_INT_REG (CAMMIR) */ -+ -+#define CAMCIR_ARM_SELF_INT_OFFS 0 -+#define CAMCIR_ARM_SELF_INT_MASK BIT0 -+#define CAMCIR_ARM_SELF_INT_EN (1 << CAMCIR_ARM_SELF_INT_OFFS) -+#define CAMCIR_ARM_SELF_INT_DIS (0 << CAMCIR_ARM_SELF_INT_OFFS) -+ -+ -+#define CAMCIR_ARM_TIMER0_INT_REQ_OFFS 1 -+#define CAMCIR_ARM_TIMER0_INT_REQ_MASK BIT1 -+#define CAMCIR_ARM_TIMER0_INT_REQ_EN (1 << CAMCIR_ARM_TIMER0_INT_REQ_OFFS) -+#define CAMCIR_ARM_TIMER0_INT_REQ_DIS (0 << CAMCIR_ARM_TIMER0_INT_REQ_OFFS) -+ -+#define CAMCIR_ARM_TIMER1_INT_REQ_OFFS 2 -+#define CAMCIR_ARM_TIMER1_INT_REQ_MASK BIT2 -+#define CAMCIR_ARM_TIMER1_INT_REQ_EN (1 << CAMCIR_ARM_TIMER1_INT_REQ_OFFS) -+#define CAMCIR_ARM_TIMER1_INT_REQ_DIS (0 << CAMCIR_ARM_TIMER1_INT_REQ_OFFS) -+ -+#define CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS 3 -+#define CAMCIR_ARM_WD_TIMER_INT_REQ_MASK BIT3 -+#define CAMCIR_ARM_WD_TIMER_INT_REQ_EN (1 << CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS) -+#define CAMCIR_ARM_WD_TIMER_INT_REQ_DIS (0 << CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS) -+ -+/* CPU FTDLL Config register (CFCR) fields */ -+#define CFCR_FTDLL_ICACHE_TAG_OFFS 0 -+#define CFCR_FTDLL_ICACHE_TAG_MASK (0x7F << CFCR_FTDLL_ICACHE_TAG_OFFS) -+#define CFCR_FTDLL_DCACHE_TAG_OFFS 8 -+#define CFCR_FTDLL_DCACHE_TAG_MASK (0x7F << CFCR_FTDLL_DCACHE_TAG_OFFS) -+#define CFCR_FTDLL_OVERWRITE_ENABLE (1 << 15) -+/* For Orion 2 D2 only */ -+#define CFCR_MRVL_CPU_ID_OFFS 16 -+#define CFCR_MRVL_CPU_ID_MASK (0x1 << CFCR_MRVL_CPU_ID_OFFS) -+#define CFCR_ARM_CPU_ID (0x0 << CFCR_MRVL_CPU_ID_OFFS) -+#define CFCR_MRVL_CPU_ID (0x1 << CFCR_MRVL_CPU_ID_OFFS) -+#define CFCR_VFP_SUB_ARC_NUM_OFFS 7 -+#define CFCR_VFP_SUB_ARC_NUM_MASK (0x1 << CFCR_VFP_SUB_ARC_NUM_OFFS) -+#define CFCR_VFP_SUB_ARC_NUM_1 (0x0 << CFCR_VFP_SUB_ARC_NUM_OFFS) -+#define CFCR_VFP_SUB_ARC_NUM_2 (0x1 << CFCR_VFP_SUB_ARC_NUM_OFFS) -+ -+/* CPU_L2_CONFIG_REG fields */ -+#ifdef MV_CPU_LE -+#define CL2CR_L2_ECC_EN_OFFS 2 -+#define CL2CR_L2_WT_MODE_OFFS 4 -+#else -+#define CL2CR_L2_ECC_EN_OFFS 26 -+#define CL2CR_L2_WT_MODE_OFFS 28 -+#endif -+ -+#define CL2CR_L2_ECC_EN_MASK (1 << CL2CR_L2_ECC_EN_OFFS) -+#define CL2CR_L2_WT_MODE_MASK (1 << CL2CR_L2_WT_MODE_OFFS) -+ -+/*******************************************/ -+/* Main Interrupt Controller Registers Map */ -+/*******************************************/ -+ -+#define CPU_MAIN_INT_CAUSE_REG 0x20200 -+#define CPU_MAIN_IRQ_MASK_REG 0x20204 -+#define CPU_MAIN_FIQ_MASK_REG 0x20208 -+#define CPU_ENPOINT_MASK_REG 0x2020C -+#define CPU_MAIN_INT_CAUSE_HIGH_REG 0x20210 -+#define CPU_MAIN_IRQ_MASK_HIGH_REG 0x20214 -+#define CPU_MAIN_FIQ_MASK_HIGH_REG 0x20218 -+#define CPU_ENPOINT_MASK_HIGH_REG 0x2021C -+ -+ -+/*******************************************/ -+/* ARM Doorbell Registers Map */ -+/*******************************************/ -+ -+#define CPU_HOST_TO_ARM_DRBL_REG 0x20400 -+#define CPU_HOST_TO_ARM_MASK_REG 0x20404 -+#define CPU_ARM_TO_HOST_DRBL_REG 0x20408 -+#define CPU_ARM_TO_HOST_MASK_REG 0x2040C -+ -+ -+ -+/* CPU control register map */ -+/* Set bits means value is about to change according to new value */ -+#define CPU_CONFIG_DEFAULT_MASK (CCR_VEC_INIT_LOC_MASK | CCR_AHB_ERROR_PROP_MASK) -+ -+#define CPU_CONFIG_DEFAULT (CCR_VEC_INIT_LOC_FF00) -+ -+/* CPU Control and status defaults */ -+#define CPU_CTRL_STAT_DEFAULT_MASK (CCSR_PCI_ACCESS_MASK) -+ -+ -+#define CPU_CTRL_STAT_DEFAULT (CCSR_PCI_ACCESS_ENABLE) -+ -+#endif /* __INCmvCpuIfRegsh */ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c 2010-11-09 20:28:08.042495347 +0100 -@@ -0,0 +1,324 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#include "mvSysAudio.h" -+ -+/******************************************************************************* -+* mvAudioWinSet - Set AUDIO target address window -+* -+* DESCRIPTION: -+* This function sets a peripheral target (e.g. SDRAM bank0, PCI_MEM0) -+* address window, also known as address decode window. -+* After setting this target window, the AUDIO will be able to access the -+* target within the address window. -+* -+* INPUT: -+* winNum - AUDIO target address decode window number. -+* pAddrDecWin - AUDIO target window data structure. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR if address window overlapps with other address decode windows. -+* MV_BAD_PARAM if base address is invalid parameter or target is -+* unknown. -+* -+*******************************************************************************/ -+MV_STATUS mvAudioWinSet(MV_U32 winNum, MV_AUDIO_DEC_WIN *pAddrDecWin) -+{ -+ MV_TARGET_ATTRIB targetAttribs; -+ MV_DEC_REGS decRegs; -+ -+ /* Parameter checking */ -+ if (winNum >= MV_AUDIO_MAX_ADDR_DECODE_WIN) -+ { -+ mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvAudioWinSet:Error setting AUDIO window %d to "\ -+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, -+ mvCtrlTargetNameGet(pAddrDecWin->target), -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ decRegs.baseReg = 0; -+ decRegs.sizeReg = 0; -+ -+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) -+ { -+ mvOsPrintf("%s: mvCtrlAddrDecToReg Failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); -+ -+ /* set attributes */ -+ decRegs.sizeReg &= ~MV_AUDIO_WIN_ATTR_MASK; -+ decRegs.sizeReg |= (targetAttribs.attrib << MV_AUDIO_WIN_ATTR_OFFSET); -+ -+ /* set target ID */ -+ decRegs.sizeReg &= ~MV_AUDIO_WIN_TARGET_MASK; -+ decRegs.sizeReg |= (targetAttribs.targetId << MV_AUDIO_WIN_TARGET_OFFSET); -+ -+ if (pAddrDecWin->enable == MV_TRUE) -+ { -+ decRegs.sizeReg |= MV_AUDIO_WIN_ENABLE_MASK; -+ } -+ else -+ { -+ decRegs.sizeReg &= ~MV_AUDIO_WIN_ENABLE_MASK; -+ } -+ -+ MV_REG_WRITE( MV_AUDIO_WIN_CTRL_REG(winNum), decRegs.sizeReg); -+ MV_REG_WRITE( MV_AUDIO_WIN_BASE_REG(winNum), decRegs.baseReg); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvAudioWinGet - Get AUDIO peripheral target address window. -+* -+* DESCRIPTION: -+* Get AUDIO peripheral target address window. -+* -+* INPUT: -+* winNum - AUDIO target address decode window number. -+* -+* OUTPUT: -+* pAddrDecWin - AUDIO target window data structure. -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvAudioWinGet(MV_U32 winNum, MV_AUDIO_DEC_WIN *pAddrDecWin) -+{ -+ MV_DEC_REGS decRegs; -+ MV_TARGET_ATTRIB targetAttrib; -+ -+ /* Parameter checking */ -+ if (winNum >= MV_AUDIO_MAX_ADDR_DECODE_WIN) -+ { -+ mvOsPrintf("%s : ERR. Invalid winNum %d\n", -+ __FUNCTION__, winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ decRegs.baseReg = MV_REG_READ( MV_AUDIO_WIN_BASE_REG(winNum) ); -+ decRegs.sizeReg = MV_REG_READ( MV_AUDIO_WIN_CTRL_REG(winNum) ); -+ -+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs, &pAddrDecWin->addrWin) ) -+ { -+ mvOsPrintf("%s: mvCtrlRegToAddrDec Failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ /* attrib and targetId */ -+ targetAttrib.attrib = (decRegs.sizeReg & MV_AUDIO_WIN_ATTR_MASK) >> -+ MV_AUDIO_WIN_ATTR_OFFSET; -+ targetAttrib.targetId = (decRegs.sizeReg & MV_AUDIO_WIN_TARGET_MASK) >> -+ MV_AUDIO_WIN_TARGET_OFFSET; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ /* Check if window is enabled */ -+ if(decRegs.sizeReg & MV_AUDIO_WIN_ENABLE_MASK) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ } -+ return MV_OK; -+} -+/******************************************************************************* -+* mvAudioAddrDecShow - Print the AUDIO address decode map. -+* -+* DESCRIPTION: -+* This function print the AUDIO address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvAudioAddrDecShow(MV_VOID) -+{ -+ -+ MV_AUDIO_DEC_WIN win; -+ int i; -+ -+ if (MV_FALSE == mvCtrlPwrClckGet(AUDIO_UNIT_ID, 0)) -+ return; -+ -+ -+ mvOsOutput( "\n" ); -+ mvOsOutput( "AUDIO:\n" ); -+ mvOsOutput( "----\n" ); -+ -+ for( i = 0; i < MV_AUDIO_MAX_ADDR_DECODE_WIN; i++ ) -+ { -+ memset( &win, 0, sizeof(MV_AUDIO_DEC_WIN) ); -+ -+ mvOsOutput( "win%d - ", i ); -+ -+ if( mvAudioWinGet( i, &win ) == MV_OK ) -+ { -+ if( win.enable ) -+ { -+ mvOsOutput( "%s base %08x, ", -+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); -+ mvOsOutput( "...." ); -+ -+ mvSizePrint( win.addrWin.size ); -+ -+ mvOsOutput( "\n" ); -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ } -+ } -+} -+ -+ -+/******************************************************************************* -+* mvAudioWinInit - Initialize the integrated AUDIO target address window. -+* -+* DESCRIPTION: -+* Initialize the AUDIO peripheral target address window. -+* -+* INPUT: -+* -+* -+* OUTPUT: -+* -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvAudioInit(MV_VOID) -+{ -+ int winNum; -+ MV_AUDIO_DEC_WIN audioWin; -+ MV_CPU_DEC_WIN cpuAddrDecWin; -+ MV_U32 status; -+ -+ mvAudioHalInit(); -+ -+ /* Initiate Audio address decode */ -+ -+ /* First disable all address decode windows */ -+ for(winNum = 0; winNum < MV_AUDIO_MAX_ADDR_DECODE_WIN; winNum++) -+ { -+ MV_U32 regVal = MV_REG_READ(MV_AUDIO_WIN_CTRL_REG(winNum)); -+ regVal &= ~MV_AUDIO_WIN_ENABLE_MASK; -+ MV_REG_WRITE(MV_AUDIO_WIN_CTRL_REG(winNum), regVal); -+ } -+ -+ for(winNum = 0; winNum < MV_AUDIO_MAX_ADDR_DECODE_WIN; winNum++) -+ { -+ -+ /* We will set the Window to DRAM_CS0 in default */ -+ /* first get attributes from CPU If */ -+ status = mvCpuIfTargetWinGet(SDRAM_CS0, -+ &cpuAddrDecWin); -+ -+ if (MV_OK != status) -+ { -+ mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ if (cpuAddrDecWin.enable == MV_TRUE) -+ { -+ audioWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; -+ audioWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; -+ audioWin.addrWin.size = cpuAddrDecWin.addrWin.size; -+ audioWin.enable = MV_TRUE; -+ audioWin.target = SDRAM_CS0; -+ -+ if(MV_OK != mvAudioWinSet(winNum, &audioWin)) -+ { -+ return MV_ERROR; -+ } -+ } -+ } -+ -+ return MV_OK; -+} -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h 2010-11-09 20:28:08.082495466 +0100 -@@ -0,0 +1,123 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#ifndef __INCMVSysAudioH -+#define __INCMVSysAudioH -+ -+#include "mvCommon.h" -+#include "audio/mvAudio.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+ -+/***********************************/ -+/* Audio Address Decoding registers*/ -+/***********************************/ -+ -+#define MV_AUDIO_MAX_ADDR_DECODE_WIN 2 -+#define MV_AUDIO_RECORD_WIN_NUM 0 -+#define MV_AUDIO_PLAYBACK_WIN_NUM 1 -+ -+#define MV_AUDIO_WIN_CTRL_REG(win) (AUDIO_REG_BASE + 0xA04 + ((win)<<3)) -+#define MV_AUDIO_WIN_BASE_REG(win) (AUDIO_REG_BASE + 0xA00 + ((win)<<3)) -+ -+#define MV_AUDIO_RECORD_WIN_CTRL_REG MV_AUDIO_WIN_CTRL_REG(MV_AUDIO_RECORD_WIN_NUM) -+#define MV_AUDIO_RECORD_WIN_BASE_REG MV_AUDIO_WIN_BASE_REG(MV_AUDIO_RECORD_WIN_NUM) -+#define MV_AUDIO_PLAYBACK_WIN_CTRL_REG MV_AUDIO_WIN_CTRL_REG(MV_AUDIO_PLAYBACK_WIN_NUM) -+#define MV_AUDIO_PLAYBACK_WIN_BASE_REG MV_AUDIO_WIN_BASE_REG(MV_AUDIO_PLAYBACK_WIN_NUM) -+ -+ -+/* BITs in Windows 0-3 Control and Base Registers */ -+#define MV_AUDIO_WIN_ENABLE_BIT 0 -+#define MV_AUDIO_WIN_ENABLE_MASK (1<= 2) -+MV_TARGET tdmaAddrDecPrioTable[] = -+{ -+#if defined(MV_INCLUDE_SDRAM_CS0) -+ SDRAM_CS0, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS1) -+ SDRAM_CS1, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS2) -+ SDRAM_CS2, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS3) -+ SDRAM_CS3, -+#endif -+#if defined(MV_INCLUDE_PEX) -+ PEX0_MEM, -+#endif -+ -+ TBL_TERM -+}; -+ -+/******************************************************************************* -+* mvCesaWinGet - Get TDMA target address window. -+* -+* DESCRIPTION: -+* Get TDMA target address window. -+* -+* INPUT: -+* winNum - TDMA target address decode window number. -+* -+* OUTPUT: -+* pDecWin - TDMA target window data structure. -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+static MV_STATUS mvCesaWinGet(MV_U32 winNum, MV_DEC_WIN *pDecWin) -+{ -+ MV_DEC_WIN_PARAMS winParam; -+ MV_U32 sizeReg, baseReg; -+ -+ /* Parameter checking */ -+ if (winNum >= MV_CESA_TDMA_ADDR_DEC_WIN) -+ { -+ mvOsPrintf("%s : ERR. Invalid winNum %d\n", -+ __FUNCTION__, winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ baseReg = MV_REG_READ( MV_CESA_TDMA_BASE_ADDR_REG(winNum) ); -+ sizeReg = MV_REG_READ( MV_CESA_TDMA_WIN_CTRL_REG(winNum) ); -+ -+ /* Check if window is enabled */ -+ if(sizeReg & MV_CESA_TDMA_WIN_ENABLE_MASK) -+ { -+ pDecWin->enable = MV_TRUE; -+ -+ /* Extract window parameters from registers */ -+ winParam.targetId = (sizeReg & MV_CESA_TDMA_WIN_TARGET_MASK) >> MV_CESA_TDMA_WIN_TARGET_OFFSET; -+ winParam.attrib = (sizeReg & MV_CESA_TDMA_WIN_ATTR_MASK) >> MV_CESA_TDMA_WIN_ATTR_OFFSET; -+ winParam.size = (sizeReg & MV_CESA_TDMA_WIN_SIZE_MASK) >> MV_CESA_TDMA_WIN_SIZE_OFFSET; -+ winParam.baseAddr = (baseReg & MV_CESA_TDMA_WIN_BASE_MASK); -+ -+ /* Translate the decode window parameters to address decode struct */ -+ if (MV_OK != mvCtrlParamsToAddrDec(&winParam, pDecWin)) -+ { -+ mvOsPrintf("Failed to translate register parameters to CESA address" \ -+ " decode window structure\n"); -+ return MV_ERROR; -+ } -+ } -+ else -+ { -+ pDecWin->enable = MV_FALSE; -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* cesaWinOverlapDetect - Detect CESA TDMA address windows overlapping -+* -+* DESCRIPTION: -+* An unpredicted behaviur is expected in case TDMA address decode -+* windows overlapps. -+* This function detects TDMA address decode windows overlapping of a -+* specified window. The function does not check the window itself for -+* overlapping. The function also skipps disabled address decode windows. -+* -+* INPUT: -+* winNum - address decode window number. -+* pAddrDecWin - An address decode window struct. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE - if the given address window overlap current address -+* decode map, -+* MV_FALSE - otherwise, MV_ERROR if reading invalid data -+* from registers. -+* -+*******************************************************************************/ -+static MV_STATUS cesaWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 winNumIndex; -+ MV_DEC_WIN addrDecWin; -+ -+ for(winNumIndex=0; winNumIndex= MV_CESA_TDMA_ADDR_DEC_WIN) -+ { -+ mvOsPrintf("mvCesaTdmaWinSet: ERR. Invalid win num %d\n",winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlapps with current windows */ -+ if (MV_TRUE == cesaWinOverlapDetect(winNum, &pDecWin->addrWin)) -+ { -+ mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); -+ return MV_ERROR; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pDecWin->addrWin.baseLow, pDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvCesaTdmaWinSet: Error setting CESA TDMA window %d to "\ -+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, -+ mvCtrlTargetNameGet(pDecWin->target), -+ pDecWin->addrWin.baseLow, -+ pDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ if(MV_OK != mvCtrlAddrDecToParams(pDecWin, &winParams)) -+ { -+ mvOsPrintf("%s: mvCtrlAddrDecToParams Failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ /* set Size, Attributes and TargetID */ -+ sizeReg = (((winParams.targetId << MV_CESA_TDMA_WIN_TARGET_OFFSET) & MV_CESA_TDMA_WIN_TARGET_MASK) | -+ ((winParams.attrib << MV_CESA_TDMA_WIN_ATTR_OFFSET) & MV_CESA_TDMA_WIN_ATTR_MASK) | -+ ((winParams.size << MV_CESA_TDMA_WIN_SIZE_OFFSET) & MV_CESA_TDMA_WIN_SIZE_MASK)); -+ -+ if (pDecWin->enable == MV_TRUE) -+ { -+ sizeReg |= MV_CESA_TDMA_WIN_ENABLE_MASK; -+ } -+ else -+ { -+ sizeReg &= ~MV_CESA_TDMA_WIN_ENABLE_MASK; -+ } -+ -+ /* Update Base value */ -+ baseReg = (winParams.baseAddr & MV_CESA_TDMA_WIN_BASE_MASK); -+ -+ MV_REG_WRITE( MV_CESA_TDMA_WIN_CTRL_REG(winNum), sizeReg); -+ MV_REG_WRITE( MV_CESA_TDMA_BASE_ADDR_REG(winNum), baseReg); -+ -+ return MV_OK; -+} -+ -+ -+static MV_STATUS mvCesaTdmaAddrDecInit (void) -+{ -+ MV_U32 winNum; -+ MV_STATUS status; -+ MV_CPU_DEC_WIN cpuAddrDecWin; -+ MV_DEC_WIN cesaWin; -+ MV_U32 winPrioIndex = 0; -+ -+ /* First disable all address decode windows */ -+ for(winNum=0; winNum= 2 */ -+ -+ -+ -+ -+MV_STATUS mvCesaInit (int numOfSession, int queueDepth, char* pSramBase, void *osHandle) -+{ -+ MV_U32 cesaCryptEngBase; -+ MV_CPU_DEC_WIN addrDecWin; -+ -+ if(sizeof(MV_CESA_SRAM_MAP) > MV_CESA_SRAM_SIZE) -+ { -+ mvOsPrintf("mvCesaInit: Wrong SRAM map - %ld > %d\n", -+ sizeof(MV_CESA_SRAM_MAP), MV_CESA_SRAM_SIZE); -+ return MV_FAIL; -+ } -+#if 0 -+ if (mvCpuIfTargetWinGet(CRYPT_ENG, &addrDecWin) == MV_OK) -+ cesaCryptEngBase = addrDecWin.addrWin.baseLow; -+ else -+ { -+ mvOsPrintf("mvCesaInit: ERR. mvCpuIfTargetWinGet failed\n"); -+ return MV_ERROR; -+ } -+#else -+ cesaCryptEngBase = (MV_U32)pSramBase; -+#endif -+ -+#if 0 /* Already done in the platform init */ -+#if (MV_CESA_VERSION >= 2) -+ mvCesaTdmaAddrDecInit(); -+#endif /* MV_CESA_VERSION >= 2 */ -+#endif -+ return mvCesaHalInit(numOfSession, queueDepth, pSramBase, cesaCryptEngBase, -+ osHandle); -+ -+} -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h 2010-11-09 20:28:08.152495441 +0100 -@@ -0,0 +1,100 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __mvSysCesa_h__ -+#define __mvSysCesa_h__ -+ -+ -+#include "mvCommon.h" -+#include "cesa/mvCesa.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+ -+/***************************** TDMA Registers *************************************/ -+ -+#define MV_CESA_TDMA_ADDR_DEC_WIN 4 -+ -+#define MV_CESA_TDMA_BASE_ADDR_REG(win) (MV_CESA_TDMA_REG_BASE + 0xa00 + (win<<3)) -+ -+#define MV_CESA_TDMA_WIN_CTRL_REG(win) (MV_CESA_TDMA_REG_BASE + 0xa04 + (win<<3)) -+ -+#define MV_CESA_TDMA_WIN_ENABLE_BIT 0 -+#define MV_CESA_TDMA_WIN_ENABLE_MASK (1 << MV_CESA_TDMA_WIN_ENABLE_BIT) -+ -+#define MV_CESA_TDMA_WIN_TARGET_OFFSET 4 -+#define MV_CESA_TDMA_WIN_TARGET_MASK (0xf << MV_CESA_TDMA_WIN_TARGET_OFFSET) -+ -+#define MV_CESA_TDMA_WIN_ATTR_OFFSET 8 -+#define MV_CESA_TDMA_WIN_ATTR_MASK (0xff << MV_CESA_TDMA_WIN_ATTR_OFFSET) -+ -+#define MV_CESA_TDMA_WIN_SIZE_OFFSET 16 -+#define MV_CESA_TDMA_WIN_SIZE_MASK (0xFFFF << MV_CESA_TDMA_WIN_SIZE_OFFSET) -+ -+#define MV_CESA_TDMA_WIN_BASE_OFFSET 16 -+#define MV_CESA_TDMA_WIN_BASE_MASK (0xFFFF << MV_CESA_TDMA_WIN_BASE_OFFSET) -+ -+ -+MV_STATUS mvCesaInit (int numOfSession, int queueDepth, char* pSramBase, void *osHandle); -+ -+#endif -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.c 2010-11-09 20:28:08.192500699 +0100 -@@ -0,0 +1,348 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+/* includes */ -+ -+#include "ddr2/mvDramIf.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+#include "ctrlEnv/sys/mvSysDram.h" -+ -+/* #define MV_DEBUG */ -+#ifdef MV_DEBUG -+#define DB(x) x -+#else -+#define DB(x) -+#endif -+ -+static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin); -+ -+/******************************************************************************* -+* mvDramIfWinSet - Set DRAM interface address decode window -+* -+* DESCRIPTION: -+* This function sets DRAM interface address decode window. -+* -+* INPUT: -+* target - System target. Use only SDRAM targets. -+* pAddrDecWin - SDRAM address window structure. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK -+* otherwise. -+*******************************************************************************/ -+MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) -+{ -+ MV_U32 baseReg=0,sizeReg=0; -+ MV_U32 baseToReg=0 , sizeToReg=0; -+ -+ /* Check parameters */ -+ if (!MV_TARGET_IS_DRAM(target)) -+ { -+ mvOsPrintf("mvDramIfWinSet: target %d is not SDRAM\n", target); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlaps with current enabled windows */ -+ if (MV_TRUE == sdramIfWinOverlap(target, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("mvDramIfWinSet: ERR. Target %d overlaps\n", target); -+ return MV_BAD_PARAM; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvDramIfWinSet:Error setting DRAM interface window %d."\ -+ "\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ target, -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ /* read base register*/ -+ baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(0,target)); -+ -+ /* read size register */ -+ sizeReg = MV_REG_READ(SDRAM_SIZE_REG(0,target)); -+ -+ /* BaseLow[31:16] => base register [31:16] */ -+ baseToReg = pAddrDecWin->addrWin.baseLow & SCBAR_BASE_MASK; -+ -+ /* Write to address decode Base Address Register */ -+ baseReg &= ~SCBAR_BASE_MASK; -+ baseReg |= baseToReg; -+ -+ /* Translate the given window size to register format */ -+ sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, SCSR_SIZE_ALIGNMENT); -+ -+ /* Size parameter validity check. */ -+ if (-1 == sizeToReg) -+ { -+ mvOsPrintf("mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n",target); -+ return MV_BAD_PARAM; -+ } -+ -+ /* set size */ -+ sizeReg &= ~SCSR_SIZE_MASK; -+ /* Size is located at upper 16 bits */ -+ sizeReg |= (sizeToReg << SCSR_SIZE_OFFS); -+ -+ /* enable/Disable */ -+ if (MV_TRUE == pAddrDecWin->enable) -+ { -+ sizeReg |= SCSR_WIN_EN; -+ } -+ else -+ { -+ sizeReg &= ~SCSR_WIN_EN; -+ } -+ -+ /* 3) Write to address decode Base Address Register */ -+ MV_REG_WRITE(SDRAM_BASE_ADDR_REG(0,target), baseReg); -+ -+ /* Write to address decode Size Register */ -+ MV_REG_WRITE(SDRAM_SIZE_REG(0,target), sizeReg); -+ -+ return MV_OK; -+} -+/******************************************************************************* -+* mvDramIfWinGet - Get DRAM interface address decode window -+* -+* DESCRIPTION: -+* This function gets DRAM interface address decode window. -+* -+* INPUT: -+* target - System target. Use only SDRAM targets. -+* -+* OUTPUT: -+* pAddrDecWin - SDRAM address window structure. -+* -+* RETURN: -+* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK -+* otherwise. -+*******************************************************************************/ -+MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) -+{ -+ MV_U32 baseReg,sizeReg; -+ MV_U32 sizeRegVal; -+ /* Check parameters */ -+ if (!MV_TARGET_IS_DRAM(target)) -+ { -+ mvOsPrintf("mvDramIfWinGet: target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ /* Read base and size registers */ -+ sizeReg = MV_REG_READ(SDRAM_SIZE_REG(0,target)); -+ baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(0,target)); -+ -+ sizeRegVal = (sizeReg & SCSR_SIZE_MASK) >> SCSR_SIZE_OFFS; -+ -+ pAddrDecWin->addrWin.size = ctrlRegToSize(sizeRegVal, -+ SCSR_SIZE_ALIGNMENT); -+ -+ /* Check if ctrlRegToSize returned OK */ -+ if (-1 == pAddrDecWin->addrWin.size) -+ { -+ mvOsPrintf("mvDramIfWinGet: size of target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ /* Extract base address */ -+ /* Base register [31:16] ==> baseLow[31:16] */ -+ pAddrDecWin->addrWin.baseLow = baseReg & SCBAR_BASE_MASK; -+ -+ pAddrDecWin->addrWin.baseHigh = 0; -+ -+ -+ if (sizeReg & SCSR_WIN_EN) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ } -+ -+ return MV_OK; -+} -+/******************************************************************************* -+* mvDramIfWinEnable - Enable/Disable SDRAM address decode window -+* -+* DESCRIPTION: -+* This function enable/Disable SDRAM address decode window. -+* -+* INPUT: -+* target - System target. Use only SDRAM targets. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR in case function parameter are invalid, MV_OK otherewise. -+* -+*******************************************************************************/ -+MV_STATUS mvDramIfWinEnable(MV_TARGET target, MV_BOOL enable) -+{ -+ MV_DRAM_DEC_WIN addrDecWin; -+ -+ /* Check parameters */ -+ if (!MV_TARGET_IS_DRAM(target)) -+ { -+ mvOsPrintf("mvDramIfWinEnable: target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ if (enable == MV_TRUE) -+ { /* First check for overlap with other enabled windows */ -+ if (MV_OK != mvDramIfWinGet(target, &addrDecWin)) -+ { -+ mvOsPrintf("mvDramIfWinEnable:ERR. Getting target %d failed.\n", -+ target); -+ return MV_ERROR; -+ } -+ /* Check for overlapping */ -+ if (MV_FALSE == sdramIfWinOverlap(target, &(addrDecWin.addrWin))) -+ { -+ /* No Overlap. Enable address decode winNum window */ -+ MV_REG_BIT_SET(SDRAM_SIZE_REG(0,target), SCSR_WIN_EN); -+ } -+ else -+ { /* Overlap detected */ -+ mvOsPrintf("mvDramIfWinEnable: ERR. Target %d overlap detect\n", -+ target); -+ return MV_ERROR; -+ } -+ } -+ else -+ { /* Disable address decode winNum window */ -+ MV_REG_BIT_RESET(SDRAM_SIZE_REG(0, target), SCSR_WIN_EN); -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* sdramIfWinOverlap - Check if an address window overlap an SDRAM address window -+* -+* DESCRIPTION: -+* This function scan each SDRAM address decode window to test if it -+* overlapps the given address windoow -+* -+* INPUT: -+* target - SDRAM target where the function skips checking. -+* pAddrDecWin - The tested address window for overlapping with -+* SDRAM windows. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlaps any enabled address -+* decode map, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_TARGET targetNum; -+ MV_DRAM_DEC_WIN addrDecWin; -+ -+ for(targetNum = SDRAM_CS0; targetNum < MV_DRAM_MAX_CS ; targetNum++) -+ { -+ /* don't check our winNum or illegal targets */ -+ if (targetNum == target) -+ { -+ continue; -+ } -+ -+ /* Get window parameters */ -+ if (MV_OK != mvDramIfWinGet(targetNum, &addrDecWin)) -+ { -+ mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); -+ return MV_ERROR; -+ } -+ -+ /* Do not check disabled windows */ -+ if (MV_FALSE == addrDecWin.enable) -+ { -+ continue; -+ } -+ -+ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) -+ { -+ mvOsPrintf( -+ "sdramIfWinOverlap: Required target %d overlap winNum %d\n", -+ target, targetNum); -+ return MV_TRUE; -+ } -+ } -+ -+ return MV_FALSE; -+} -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h 2010-11-09 20:28:08.232495451 +0100 -@@ -0,0 +1,80 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __sysDram -+#define __sysDram -+ -+/* This structure describes CPU interface address decode window */ -+typedef struct _mvDramIfDecWin -+{ -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+}MV_DRAM_DEC_WIN; -+ -+MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); -+MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); -+MV_STATUS mvDramIfWinEnable(MV_TARGET target, MV_BOOL enable); -+ -+#endif -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c 2010-11-09 20:28:08.262495451 +0100 -@@ -0,0 +1,658 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#include "ctrlEnv/sys/mvSysGbe.h" -+ -+ -+ -+typedef struct _mvEthDecWin -+{ -+ MV_TARGET target; -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+}MV_ETH_DEC_WIN; -+ -+MV_TARGET ethAddrDecPrioTap[] = -+{ -+#if defined(MV_INCLUDE_SDRAM_CS0) -+ SDRAM_CS0, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS1) -+ SDRAM_CS1, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS2) -+ SDRAM_CS2, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS3) -+ SDRAM_CS3, -+#endif -+#if defined(MV_INCLUDE_DEVICE_CS0) -+ DEVICE_CS0, -+#endif -+#if defined(MV_INCLUDE_DEVICE_CS1) -+ DEVICE_CS1, -+#endif -+#if defined(MV_INCLUDE_DEVICE_CS2) -+ DEVICE_CS2, -+#endif -+#if defined(MV_INCLUDE_DEVICE_CS3) -+ DEVICE_CS3, -+#endif -+#if defined(MV_INCLUDE_PEX) -+ PEX0_IO, -+#endif -+ TBL_TERM -+}; -+ -+static MV_STATUS ethWinOverlapDetect(int port, MV_U32 winNum, MV_ADDR_WIN *pAddrWin); -+static MV_STATUS mvEthWinSet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin); -+static MV_STATUS mvEthWinGet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin); -+ -+ -+/******************************************************************************* -+* mvEthWinInit - Initialize ETH address decode windows -+* -+* DESCRIPTION: -+* This function initialize ETH window decode unit. It set the -+* default address decode windows of the unit. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR if setting fail. -+*******************************************************************************/ -+/* Configure EthDrv memory map registes. */ -+MV_STATUS mvEthWinInit (int port) -+{ -+ MV_U32 winNum, status, winPrioIndex=0, i, regVal=0; -+ MV_ETH_DEC_WIN ethWin; -+ MV_CPU_DEC_WIN cpuAddrDecWin; -+ static MV_U32 accessProtReg = 0; -+ -+#if (MV_ETH_VERSION <= 1) -+ static MV_BOOL isFirst = MV_TRUE; -+ -+ if(isFirst == MV_FALSE) -+ { -+ MV_REG_WRITE(ETH_ACCESS_PROTECT_REG(port), accessProtReg); -+ return MV_OK; -+ } -+ isFirst = MV_FALSE; -+#endif /* MV_GIGA_ETH_VERSION */ -+ -+ /* Initiate Ethernet address decode */ -+ -+ /* First disable all address decode windows */ -+ for(winNum=0; winNum= ETH_MAX_DECODE_WIN) -+ { -+ mvOsPrintf("mvEthWinSet: ERR. Invalid win num %d\n",winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlapps with current windows */ -+ if (MV_TRUE == ethWinOverlapDetect(port, winNum, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("mvEthWinSet: ERR. Window %d overlap\n", winNum); -+ return MV_ERROR; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvEthWinSet: Error setting Ethernet window %d to "\ -+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, -+ mvCtrlTargetNameGet(pAddrDecWin->target), -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ -+ decRegs.baseReg = MV_REG_READ(ETH_WIN_BASE_REG(port, winNum)); -+ decRegs.sizeReg = MV_REG_READ(ETH_WIN_SIZE_REG(port, winNum)); -+ -+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) -+ { -+ mvOsPrintf("mvEthWinSet:mvCtrlAddrDecToReg Failed\n"); -+ return MV_ERROR; -+ } -+ -+ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); -+ -+ /* set attributes */ -+ decRegs.baseReg &= ~ETH_WIN_ATTR_MASK; -+ decRegs.baseReg |= targetAttribs.attrib << ETH_WIN_ATTR_OFFS; -+ /* set target ID */ -+ decRegs.baseReg &= ~ETH_WIN_TARGET_MASK; -+ decRegs.baseReg |= targetAttribs.targetId << ETH_WIN_TARGET_OFFS; -+ -+ /* for the safe side we disable the window before writing the new -+ values */ -+ mvEthWinEnable(port, winNum, MV_FALSE); -+ MV_REG_WRITE(ETH_WIN_BASE_REG(port, winNum), decRegs.baseReg); -+ -+ /* Write to address decode Size Register */ -+ MV_REG_WRITE(ETH_WIN_SIZE_REG(port, winNum), decRegs.sizeReg); -+ -+ /* Enable address decode target window */ -+ if (pAddrDecWin->enable == MV_TRUE) -+ { -+ mvEthWinEnable(port, winNum, MV_TRUE); -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvETHWinGet - Get dma peripheral target address window. -+* -+* DESCRIPTION: -+* Get ETH peripheral target address window. -+* -+* INPUT: -+* winNum - ETH to target address decode window number. -+* -+* OUTPUT: -+* pAddrDecWin - ETH target window data structure. -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvEthWinGet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin) -+{ -+ MV_DEC_REGS decRegs; -+ MV_TARGET_ATTRIB targetAttrib; -+ -+ /* Parameter checking */ -+ if (winNum >= ETH_MAX_DECODE_WIN) -+ { -+ mvOsPrintf("mvEthWinGet: ERR. Invalid winNum %d\n", winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ decRegs.baseReg = MV_REG_READ(ETH_WIN_BASE_REG(port, winNum)); -+ decRegs.sizeReg = MV_REG_READ(ETH_WIN_SIZE_REG(port, winNum)); -+ -+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) -+ { -+ mvOsPrintf("mvAhbToMbusWinGet: mvCtrlRegToAddrDec Failed \n"); -+ return MV_ERROR; -+ } -+ -+ /* attrib and targetId */ -+ targetAttrib.attrib = -+ (decRegs.baseReg & ETH_WIN_ATTR_MASK) >> ETH_WIN_ATTR_OFFS; -+ targetAttrib.targetId = -+ (decRegs.baseReg & ETH_WIN_TARGET_MASK) >> ETH_WIN_TARGET_OFFS; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ /* Check if window is enabled */ -+ if (~(MV_REG_READ(ETH_BASE_ADDR_ENABLE_REG(port))) & (1 << winNum) ) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthWinEnable - Enable/disable a ETH to target address window -+* -+* DESCRIPTION: -+* This function enable/disable a ETH to target address window. -+* According to parameter 'enable' the routine will enable the -+* window, thus enabling ETH accesses (before enabling the window it is -+* tested for overlapping). Otherwise, the window will be disabled. -+* -+* INPUT: -+* winNum - ETH to target address decode window number. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_ERROR if decode window number was wrong or enabled window overlapps. -+* -+*******************************************************************************/ -+MV_STATUS mvEthWinEnable(int port, MV_U32 winNum,MV_BOOL enable) -+{ -+ MV_ETH_DEC_WIN addrDecWin; -+ -+ /* Parameter checking */ -+ if (winNum >= ETH_MAX_DECODE_WIN) -+ { -+ mvOsPrintf("mvEthTargetWinEnable:ERR. Invalid winNum%d\n",winNum); -+ return MV_ERROR; -+ } -+ -+ if (enable == MV_TRUE) -+ { /* First check for overlap with other enabled windows */ -+ /* Get current window */ -+ if (MV_OK != mvEthWinGet(port, winNum, &addrDecWin)) -+ { -+ mvOsPrintf("mvEthTargetWinEnable:ERR. targetWinGet fail\n"); -+ return MV_ERROR; -+ } -+ /* Check for overlapping */ -+ if (MV_FALSE == ethWinOverlapDetect(port, winNum, &(addrDecWin.addrWin))) -+ { -+ /* No Overlap. Enable address decode target window */ -+ MV_REG_BIT_RESET(ETH_BASE_ADDR_ENABLE_REG(port), (1 << winNum)); -+ } -+ else -+ { /* Overlap detected */ -+ mvOsPrintf("mvEthTargetWinEnable:ERR. Overlap detected\n"); -+ return MV_ERROR; -+ } -+ } -+ else -+ { /* Disable address decode target window */ -+ MV_REG_BIT_SET(ETH_BASE_ADDR_ENABLE_REG(port), (1 << winNum)); -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthWinTargetGet - Get Window number associated with target -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+* window number -+* -+*******************************************************************************/ -+MV_U32 mvEthWinTargetGet(int port, MV_TARGET target) -+{ -+ MV_ETH_DEC_WIN decWin; -+ MV_U32 winNum; -+ -+ /* Check parameters */ -+ if (target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetGet: target %d is Illigal\n", target); -+ return 0xffffffff; -+ } -+ -+ for (winNum=0; winNum= mvCtrlEthMaxPortGet()) -+ { -+ mvOsPrintf("mvEthProtWinSet:ERR. Invalid port number %d\n", portNo); -+ return MV_ERROR; -+ } -+ -+ if (winNum >= ETH_MAX_DECODE_WIN) -+ { -+ mvOsPrintf("mvEthProtWinSet:ERR. Invalid winNum%d\n",winNum); -+ return MV_ERROR; -+ } -+ -+ if((access == ACC_RESERVED) || (access >= MAX_ACC_RIGHTS)) -+ { -+ mvOsPrintf("mvEthProtWinSet:ERR. Inv access param %d\n", access); -+ return MV_ERROR; -+ } -+ /* Read current protection register */ -+ protReg = MV_REG_READ(ETH_ACCESS_PROTECT_REG(portNo)); -+ -+ /* Clear protection window field */ -+ protReg &= ~(ETH_PROT_WIN_MASK(winNum)); -+ -+ /* Set new protection field value */ -+ protReg |= (access << (ETH_PROT_WIN_OFFS(winNum))); -+ -+ /* Write protection register back */ -+ MV_REG_WRITE(ETH_ACCESS_PROTECT_REG(portNo), protReg); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* ethWinOverlapDetect - Detect ETH address windows overlapping -+* -+* DESCRIPTION: -+* An unpredicted behaviur is expected in case ETH address decode -+* windows overlapps. -+* This function detects ETH address decode windows overlapping of a -+* specified window. The function does not check the window itself for -+* overlapping. The function also skipps disabled address decode windows. -+* -+* INPUT: -+* winNum - address decode window number. -+* pAddrDecWin - An address decode window struct. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data -+* from registers. -+* -+*******************************************************************************/ -+static MV_STATUS ethWinOverlapDetect(int port, MV_U32 winNum, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 baseAddrEnableReg; -+ MV_U32 winNumIndex; -+ MV_ETH_DEC_WIN addrDecWin; -+ -+ /* Read base address enable register. Do not check disabled windows */ -+ baseAddrEnableReg = MV_REG_READ(ETH_BASE_ADDR_ENABLE_REG(port)); -+ -+ for (winNumIndex=0; winNumIndex= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexInit: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Enabled CPU access to PCI-Express */ -+ mvCpuIfEnablePex(pexIf, pexType); -+ -+ /* Start with bars */ -+ /* First disable all PEX bars*/ -+ for (bar = 0; bar < PEX_MAX_BARS; bar++) -+ { -+ if (PEX_INTER_REGS_BAR != bar) -+ { -+ if (MV_OK != mvPexBarEnable(pexIf, bar, MV_FALSE)) -+ { -+ mvOsPrintf("mvPexInit:mvPexBarEnable bar =%d failed \n",bar); -+ return MV_ERROR; -+ } -+ -+ } -+ -+ } -+ -+ /* and disable all PEX target windows */ -+ for (winNum = 0; winNum < PEX_MAX_TARGET_WIN - 2; winNum++) -+ { -+ if (MV_OK != mvPexTargetWinEnable(pexIf, winNum, MV_FALSE)) -+ { -+ mvOsPrintf("mvPexInit:mvPexTargetWinEnable winNum =%d failed \n", -+ winNum); -+ return MV_ERROR; -+ -+ } -+ } -+ -+ /* Now, go through all bars*/ -+ -+ -+ -+/******************************************************************************/ -+/* Internal registers bar */ -+/******************************************************************************/ -+ bar = PEX_INTER_REGS_BAR; -+ -+ /* we only open the bar , no need to open windows for this bar */ -+ -+ /* first get the CS attribute from the CPU Interface */ -+ if (MV_OK !=mvCpuIfTargetWinGet(INTER_REGS,&addrDecWin)) -+ { -+ mvOsPrintf("mvPexInit: ERR. mvCpuIfTargetWinGet failed target =%d\n",INTER_REGS); -+ return MV_ERROR; -+ } -+ -+ pexBar.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; -+ pexBar.addrWin.baseLow = addrDecWin.addrWin.baseLow; -+ pexBar.addrWin.size = addrDecWin.addrWin.size; -+ pexBar.enable = MV_TRUE; -+ -+ if (MV_OK != mvPexBarSet(pexIf, bar, &pexBar)) -+ { -+ mvOsPrintf("mvPexInit: ERR. mvPexBarSet %d failed\n", bar); -+ return MV_ERROR; -+ } -+ -+/******************************************************************************/ -+/* DRAM bar */ -+/******************************************************************************/ -+ -+ bar = PEX_DRAM_BAR; -+ -+ pexBar.addrWin.size = 0; -+ -+ for (target = SDRAM_CS0;target < MV_DRAM_MAX_CS; target++ ) -+ { -+ -+ status = mvCpuIfTargetWinGet(target,&addrDecWin); -+ -+ if((MV_NO_SUCH == status)&&(target != SDRAM_CS0)) -+ { -+ continue; -+ } -+ -+ /* first get attributes from CPU If */ -+ if (MV_OK != status) -+ { -+ mvOsPrintf("mvPexInit: ERR. mvCpuIfTargetWinGet failed target =%d\n",target); -+ return MV_ERROR; -+ } -+ if (addrDecWin.enable == MV_TRUE) -+ { -+ /* the base is the base of DRAM CS0 always */ -+ if (SDRAM_CS0 == target ) -+ { -+ pexBar.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; -+ pexBar.addrWin.baseLow = addrDecWin.addrWin.baseLow; -+ -+ } -+ -+ /* increment the bar size to be the sum of the size of all -+ DRAM chips selecs */ -+ pexBar.addrWin.size += addrDecWin.addrWin.size; -+ -+ /* set a Pex window for this target ! -+ DRAM CS always will have a Pex Window , and is not a -+ part of the priority table */ -+ pexWin.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; -+ pexWin.addrWin.baseLow = addrDecWin.addrWin.baseLow; -+ pexWin.addrWin.size = addrDecWin.addrWin.size; -+ -+ /* we disable the windows at first because we are not -+ sure that it is witihin bar boundries */ -+ pexWin.enable =MV_FALSE; -+ pexWin.target = target; -+ pexWin.targetBar = bar; -+ -+ if (MV_OK != mvPexTargetWinSet(pexIf,pexCurrWin++,&pexWin)) -+ { -+ mvOsPrintf("mvPexInit: ERR. mvPexTargetWinSet failed\n"); -+ return MV_ERROR; -+ } -+ } -+ } -+ -+ /* check if the size of the bar is illeggal */ -+ if (-1 == ctrlSizeToReg(pexBar.addrWin.size, PXBCR_BAR_SIZE_ALIGNMENT)) -+ { -+ /* try to get a good size */ -+ pexBar.addrWin.size = ctrlSizeRegRoundUp(pexBar.addrWin.size, -+ PXBCR_BAR_SIZE_ALIGNMENT); -+ } -+ -+ /* check if the size and base are valid */ -+ if (MV_TRUE == pexBarOverlapDetect(pexIf,bar,&pexBar.addrWin)) -+ { -+ mvOsPrintf("mvPexInit:Warning :Bar %d size is illigal\n",bar); -+ mvOsPrintf("it will be disabled\n"); -+ mvOsPrintf("please check Pex and CPU windows configuration\n"); -+ } -+ else -+ { -+ pexBar.enable = MV_TRUE; -+ -+ /* configure the bar */ -+ if (MV_OK != mvPexBarSet(pexIf, bar, &pexBar)) -+ { -+ mvOsPrintf("mvPexInit: ERR. mvPexBarSet %d failed\n", bar); -+ return MV_ERROR; -+ } -+ -+ /* after the bar was configured then we enable the Pex windows*/ -+ for (winNum = 0;winNum < pexCurrWin ;winNum++) -+ { -+ if (MV_OK != mvPexTargetWinEnable(pexIf, winNum, MV_TRUE)) -+ { -+ mvOsPrintf("mvPexInit: Can't enable window =%d\n",winNum); -+ return MV_ERROR; -+ } -+ -+ } -+ } -+ -+/******************************************************************************/ -+/* DEVICE bar */ -+/******************************************************************************/ -+ -+/* Open the Device BAR for non linux only */ -+#ifndef MV_DISABLE_PEX_DEVICE_BAR -+ -+ /* then device bar*/ -+ bar = PEX_DEVICE_BAR; -+ -+ /* save the starting window */ -+ pexStartWindow = pexCurrWin; -+ pexBar.addrWin.size = 0; -+ pexBar.addrWin.baseLow = 0xffffffff; -+ pexBar.addrWin.baseHigh = 0; -+ maxBase = 0; -+ -+ for (target = DEV_TO_TARGET(START_DEV_CS);target < DEV_TO_TARGET(MV_DEV_MAX_CS); target++ ) -+ { -+ status = mvCpuIfTargetWinGet(target,&addrDecWin); -+ -+ if (MV_NO_SUCH == status) -+ { -+ continue; -+ } -+ -+ if (MV_OK != status) -+ { -+ mvOsPrintf("mvPexInit: ERR. mvCpuIfTargetWinGet failed target =%d\n",target); -+ return MV_ERROR; -+ } -+ -+ if (addrDecWin.enable == MV_TRUE) -+ { -+ /* get the minimum base */ -+ if (addrDecWin.addrWin.baseLow < pexBar.addrWin.baseLow) -+ { -+ pexBar.addrWin.baseLow = addrDecWin.addrWin.baseLow; -+ } -+ -+ /* get the maximum base */ -+ if (addrDecWin.addrWin.baseLow > maxBase) -+ { -+ maxBase = addrDecWin.addrWin.baseLow; -+ sizeOfMaxBase = addrDecWin.addrWin.size; -+ } -+ -+ /* search in the priority table for this target */ -+ for (winIndex = 0; pexDevBarPrioTable[winIndex] != TBL_TERM; -+ winIndex++) -+ { -+ if (pexDevBarPrioTable[winIndex] != target) -+ { -+ continue; -+ } -+ else if (pexDevBarPrioTable[winIndex] == target) -+ { -+ /*found it */ -+ -+ /* if the index of this target in the prio table is valid -+ then we set the Pex window for this target, a valid index is -+ an index that is lower than the number of the windows that -+ was not configured yet */ -+ -+ /* we subtract 2 always because the default and expantion -+ rom windows are always configured */ -+ if ( pexCurrWin < PEX_MAX_TARGET_WIN - 2) -+ { -+ /* set a Pex window for this target ! */ -+ pexWin.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; -+ pexWin.addrWin.baseLow = addrDecWin.addrWin.baseLow; -+ pexWin.addrWin.size = addrDecWin.addrWin.size; -+ -+ /* we disable the windows at first because we are not -+ sure that it is witihin bar boundries */ -+ pexWin.enable = MV_FALSE; -+ pexWin.target = target; -+ pexWin.targetBar = bar; -+ -+ if (MV_OK != mvPexTargetWinSet(pexIf,pexCurrWin++, -+ &pexWin)) -+ { -+ mvOsPrintf("mvPexInit: ERR. Window Set failed\n"); -+ return MV_ERROR; -+ } -+ } -+ } -+ } -+ } -+ } -+ -+ pexBar.addrWin.size = maxBase - pexBar.addrWin.baseLow + sizeOfMaxBase; -+ pexBar.enable = MV_TRUE; -+ -+ /* check if the size of the bar is illegal */ -+ if (-1 == ctrlSizeToReg(pexBar.addrWin.size, PXBCR_BAR_SIZE_ALIGNMENT)) -+ { -+ /* try to get a good size */ -+ pexBar.addrWin.size = ctrlSizeRegRoundUp(pexBar.addrWin.size, -+ PXBCR_BAR_SIZE_ALIGNMENT); -+ } -+ -+ /* check if the size and base are valid */ -+ if (MV_TRUE == pexBarOverlapDetect(pexIf,bar,&pexBar.addrWin)) -+ { -+ mvOsPrintf("mvPexInit:Warning :Bar %d size is illigal\n",bar); -+ mvOsPrintf("it will be disabled\n"); -+ mvOsPrintf("please check Pex and CPU windows configuration\n"); -+ } -+ else -+ { -+ if (MV_OK != mvPexBarSet(pexIf, bar, &pexBar)) -+ { -+ mvOsPrintf("mvPexInit: ERR. mvPexBarSet %d failed\n", bar); -+ return MV_ERROR; -+ } -+ -+ /* now enable the windows */ -+ for (winNum = pexStartWindow; winNum < pexCurrWin ; winNum++) -+ { -+ if (MV_OK != mvPexTargetWinEnable(pexIf, winNum, MV_TRUE)) -+ { -+ mvOsPrintf("mvPexInit:mvPexTargetWinEnable winNum =%d failed \n", -+ winNum); -+ return MV_ERROR; -+ } -+ } -+ } -+ -+#endif -+ -+ return mvPexHalInit(pexIf, pexType); -+ -+} -+ -+/******************************************************************************* -+* mvPexTargetWinSet - Set PEX to peripheral target address window BAR -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_OK if PEX BAR target window was set correctly, -+* MV_BAD_PARAM on bad params -+* MV_ERROR otherwise -+* (e.g. address window overlapps with other active PEX target window). -+* -+*******************************************************************************/ -+MV_STATUS mvPexTargetWinSet(MV_U32 pexIf, MV_U32 winNum, -+ MV_PEX_DEC_WIN *pAddrDecWin) -+{ -+ -+ MV_DEC_REGS decRegs; -+ PEX_WIN_REG_INFO winRegInfo; -+ MV_TARGET_ATTRIB targetAttribs; -+ -+ /* Parameter checking */ -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexTargetWinSet: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ -+ if (winNum >= PEX_MAX_TARGET_WIN) -+ { -+ mvOsPrintf("mvPexTargetWinSet: ERR. Invalid PEX winNum %d\n", winNum); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ /* get the pex Window registers offsets */ -+ pexWinRegInfoGet(pexIf,winNum,&winRegInfo); -+ -+ -+ if (MV_TRUE == pAddrDecWin->enable) -+ { -+ -+ /* 2) Check if the requested window overlaps with current windows */ -+ if (MV_TRUE == pexWinOverlapDetect(pexIf,winNum, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("mvPexTargetWinSet: ERR. Target %d overlap\n", winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* 2) Check if the requested window overlaps with current windows */ -+ if (MV_FALSE == pexIsWinWithinBar(pexIf,&pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("mvPexTargetWinSet: Win %d should be in bar boundries\n", -+ winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ } -+ -+ -+ -+ /* read base register*/ -+ -+ if (winRegInfo.baseLowRegOffs) -+ { -+ decRegs.baseReg = MV_REG_READ(winRegInfo.baseLowRegOffs); -+ } -+ else -+ { -+ decRegs.baseReg = 0; -+ } -+ -+ if (winRegInfo.sizeRegOffs) -+ { -+ decRegs.sizeReg = MV_REG_READ(winRegInfo.sizeRegOffs); -+ } -+ else -+ { -+ decRegs.sizeReg =0; -+ } -+ -+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) -+ { -+ mvOsPrintf("mvPexTargetWinSet:mvCtrlAddrDecToReg Failed\n"); -+ return MV_ERROR; -+ } -+ -+ /* enable\Disable */ -+ if (MV_TRUE == pAddrDecWin->enable) -+ { -+ decRegs.sizeReg |= PXWCR_WIN_EN; -+ } -+ else -+ { -+ decRegs.sizeReg &= ~PXWCR_WIN_EN; -+ } -+ -+ -+ /* clear bit location */ -+ decRegs.sizeReg &= ~PXWCR_WIN_BAR_MAP_MASK; -+ -+ /* set bar Mapping */ -+ if (pAddrDecWin->targetBar == 1) -+ { -+ decRegs.sizeReg |= PXWCR_WIN_BAR_MAP_BAR1; -+ } -+ else if (pAddrDecWin->targetBar == 2) -+ { -+ decRegs.sizeReg |= PXWCR_WIN_BAR_MAP_BAR2; -+ } -+ -+ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); -+ -+ /* set attributes */ -+ decRegs.sizeReg &= ~PXWCR_ATTRIB_MASK; -+ decRegs.sizeReg |= targetAttribs.attrib << PXWCR_ATTRIB_OFFS; -+ /* set target ID */ -+ decRegs.sizeReg &= ~PXWCR_TARGET_MASK; -+ decRegs.sizeReg |= targetAttribs.targetId << PXWCR_TARGET_OFFS; -+ -+ -+ /* 3) Write to address decode Base Address Register */ -+ -+ if (winRegInfo.baseLowRegOffs) -+ { -+ MV_REG_WRITE(winRegInfo.baseLowRegOffs, decRegs.baseReg); -+ } -+ -+ /* write size reg */ -+ if (winRegInfo.sizeRegOffs) -+ { -+ if ((MV_PEX_WIN_DEFAULT == winNum)|| -+ (MV_PEX_WIN_EXP_ROM == winNum)) -+ { -+ /* clear size because there is no size field*/ -+ decRegs.sizeReg &= ~PXWCR_SIZE_MASK; -+ -+ /* clear enable because there is no enable field*/ -+ decRegs.sizeReg &= ~PXWCR_WIN_EN; -+ -+ } -+ -+ MV_REG_WRITE(winRegInfo.sizeRegOffs, decRegs.sizeReg); -+ } -+ -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvPexTargetWinGet - Get PEX to peripheral target address window -+* -+* DESCRIPTION: -+* Get the PEX to peripheral target address window BAR. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* bar - BAR to be accessed by slave. -+* -+* OUTPUT: -+* pAddrBarWin - PEX target window information data structure. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexTargetWinGet(MV_U32 pexIf, MV_U32 winNum, -+ MV_PEX_DEC_WIN *pAddrDecWin) -+{ -+ MV_TARGET_ATTRIB targetAttrib; -+ MV_DEC_REGS decRegs; -+ -+ PEX_WIN_REG_INFO winRegInfo; -+ -+ /* Parameter checking */ -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexTargetWinGet: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ -+ if (winNum >= PEX_MAX_TARGET_WIN) -+ { -+ mvOsPrintf("mvPexTargetWinGet: ERR. Invalid PEX winNum %d\n", winNum); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ /* get the pex Window registers offsets */ -+ pexWinRegInfoGet(pexIf,winNum,&winRegInfo); -+ -+ /* read base register*/ -+ if (winRegInfo.baseLowRegOffs) -+ { -+ decRegs.baseReg = MV_REG_READ(winRegInfo.baseLowRegOffs); -+ } -+ else -+ { -+ decRegs.baseReg = 0; -+ } -+ -+ /* read size reg */ -+ if (winRegInfo.sizeRegOffs) -+ { -+ decRegs.sizeReg = MV_REG_READ(winRegInfo.sizeRegOffs); -+ } -+ else -+ { -+ decRegs.sizeReg =0; -+ } -+ -+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) -+ { -+ mvOsPrintf("mvPexTargetWinGet: mvCtrlRegToAddrDec Failed \n"); -+ return MV_ERROR; -+ -+ } -+ -+ if (decRegs.sizeReg & PXWCR_WIN_EN) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ -+ } -+ -+ -+ #if 0 -+ if (-1 == pAddrDecWin->addrWin.size) -+ { -+ return MV_ERROR; -+ } -+ #endif -+ -+ -+ /* get target bar */ -+ if ((decRegs.sizeReg & PXWCR_WIN_BAR_MAP_MASK) == PXWCR_WIN_BAR_MAP_BAR1 ) -+ { -+ pAddrDecWin->targetBar = 1; -+ } -+ else if ((decRegs.sizeReg & PXWCR_WIN_BAR_MAP_MASK) == -+ PXWCR_WIN_BAR_MAP_BAR2 ) -+ { -+ pAddrDecWin->targetBar = 2; -+ } -+ -+ /* attrib and targetId */ -+ pAddrDecWin->attrib = (decRegs.sizeReg & PXWCR_ATTRIB_MASK) >> -+ PXWCR_ATTRIB_OFFS; -+ pAddrDecWin->targetId = (decRegs.sizeReg & PXWCR_TARGET_MASK) >> -+ PXWCR_TARGET_OFFS; -+ -+ targetAttrib.attrib = pAddrDecWin->attrib; -+ targetAttrib.targetId = pAddrDecWin->targetId; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ return MV_OK; -+ -+} -+ -+ -+/******************************************************************************* -+* mvPexTargetWinEnable - Enable/disable a PEX BAR window -+* -+* DESCRIPTION: -+* This function enable/disable a PEX BAR window. -+* if parameter 'enable' == MV_TRUE the routine will enable the -+* window, thus enabling PEX accesses for that BAR (before enabling the -+* window it is tested for overlapping). Otherwise, the window will -+* be disabled. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* bar - BAR to be accessed by slave. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexTargetWinEnable(MV_U32 pexIf,MV_U32 winNum, MV_BOOL enable) -+{ -+ PEX_WIN_REG_INFO winRegInfo; -+ MV_PEX_DEC_WIN addrDecWin; -+ -+ /* Parameter checking */ -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexTargetWinEnable: ERR. Invalid PEX If %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ -+ if (winNum >= PEX_MAX_TARGET_WIN) -+ { -+ mvOsPrintf("mvPexTargetWinEnable ERR. Invalid PEX winNum %d\n", winNum); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ -+ /* get the pex Window registers offsets */ -+ pexWinRegInfoGet(pexIf,winNum,&winRegInfo); -+ -+ -+ /* if the address windows is disabled , we only disable the appropriare -+ pex window and ignore other settings */ -+ -+ if (MV_FALSE == enable) -+ { -+ -+ /* this is not relevant to default and expantion rom -+ windows */ -+ if (winRegInfo.sizeRegOffs) -+ { -+ if ((MV_PEX_WIN_DEFAULT != winNum)&& -+ (MV_PEX_WIN_EXP_ROM != winNum)) -+ { -+ MV_REG_BIT_RESET(winRegInfo.sizeRegOffs, PXWCR_WIN_EN); -+ } -+ } -+ -+ } -+ else -+ { -+ if (MV_OK != mvPexTargetWinGet(pexIf,winNum, &addrDecWin)) -+ { -+ mvOsPrintf("mvPexTargetWinEnable: mvPexTargetWinGet Failed\n"); -+ return MV_ERROR; -+ } -+ -+ /* Check if the requested window overlaps with current windows */ -+ if (MV_TRUE == pexWinOverlapDetect(pexIf,winNum, &addrDecWin.addrWin)) -+ { -+ mvOsPrintf("mvPexTargetWinEnable: ERR. Target %d overlap\n", winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ if (MV_FALSE == pexIsWinWithinBar(pexIf,&addrDecWin.addrWin)) -+ { -+ mvOsPrintf("mvPexTargetWinEnable: Win %d should be in bar boundries\n", -+ winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ -+ /* this is not relevant to default and expantion rom -+ windows */ -+ if (winRegInfo.sizeRegOffs) -+ { -+ if ((MV_PEX_WIN_DEFAULT != winNum)&& -+ (MV_PEX_WIN_EXP_ROM != winNum)) -+ { -+ MV_REG_BIT_SET(winRegInfo.sizeRegOffs, PXWCR_WIN_EN); -+ } -+ } -+ -+ -+ } -+ -+ return MV_OK; -+ -+} -+ -+ -+ -+/******************************************************************************* -+* mvPexTargetWinRemap - Set PEX to target address window remap. -+* -+* DESCRIPTION: -+* The PEX interface supports remap of the BAR original address window. -+* For each BAR it is possible to define a remap address. For example -+* an address 0x12345678 that hits BAR 0x10 (SDRAM CS[0]) will be modified -+* according to remap register but will also be targeted to the -+* SDRAM CS[0]. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* bar - Peripheral target enumerator accessed by slave. -+* pAddrWin - Address window to be checked. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexTargetWinRemap(MV_U32 pexIf, MV_U32 winNum, -+ MV_PEX_REMAP_WIN *pAddrWin) -+{ -+ -+ PEX_WIN_REG_INFO winRegInfo; -+ -+ /* Parameter checking */ -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX interface num %d\n", -+ pexIf); -+ return MV_BAD_PARAM; -+ } -+ if (MV_PEX_WIN_DEFAULT == winNum) -+ { -+ mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX win num %d\n", -+ winNum); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ if (MV_IS_NOT_ALIGN(pAddrWin->addrWin.baseLow, PXWRR_REMAP_ALIGNMENT)) -+ { -+ mvOsPrintf("mvPexTargetWinRemap: Error remap PEX interface %d win %d."\ -+ "\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ pexIf, -+ winNum, -+ pAddrWin->addrWin.baseLow, -+ pAddrWin->addrWin.size); -+ -+ return MV_ERROR; -+ } -+ -+ pexWinRegInfoGet(pexIf, winNum, &winRegInfo); -+ -+ /* Set remap low register value */ -+ MV_REG_WRITE(winRegInfo.remapLowRegOffs, pAddrWin->addrWin.baseLow); -+ -+ /* Skip base high settings if the BAR has only base low (32-bit) */ -+ if (0 != winRegInfo.remapHighRegOffs) -+ { -+ MV_REG_WRITE(winRegInfo.remapHighRegOffs, pAddrWin->addrWin.baseHigh); -+ } -+ -+ -+ if (pAddrWin->enable == MV_TRUE) -+ { -+ MV_REG_BIT_SET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvPexTargetWinRemapEnable - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+ -+MV_STATUS mvPexTargetWinRemapEnable(MV_U32 pexIf, MV_U32 winNum, -+ MV_BOOL enable) -+{ -+ PEX_WIN_REG_INFO winRegInfo; -+ -+ /* Parameter checking */ -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX interface num %d\n", -+ pexIf); -+ return MV_BAD_PARAM; -+ } -+ if (MV_PEX_WIN_DEFAULT == winNum) -+ { -+ mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX win num %d\n", -+ winNum); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ -+ pexWinRegInfoGet(pexIf, winNum, &winRegInfo); -+ -+ if (enable == MV_TRUE) -+ { -+ MV_REG_BIT_SET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); -+ } -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvPexBarSet - Set PEX bar address and size -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexBarSet(MV_U32 pexIf, -+ MV_U32 barNum, -+ MV_PEX_BAR *pAddrWin) -+{ -+ MV_U32 regBaseLow; -+ MV_U32 regSize,sizeToReg; -+ -+ -+ /* check parameters */ -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexBarSet: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ -+ if(barNum >= PEX_MAX_BARS) -+ { -+ mvOsPrintf("mvPexBarSet: ERR. Invalid bar number %d\n", barNum); -+ return MV_BAD_PARAM; -+ } -+ -+ -+ if (pAddrWin->addrWin.size == 0) -+ { -+ mvOsPrintf("mvPexBarSet: Size zero is Illigal\n" ); -+ return MV_BAD_PARAM; -+ } -+ -+ -+ /* Check if the window complies with PEX spec */ -+ if (MV_TRUE != pexBarIsValid(pAddrWin->addrWin.baseLow, -+ pAddrWin->addrWin.size)) -+ { -+ mvOsPrintf("mvPexBarSet: ERR. Target %d window invalid\n", barNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* 2) Check if the requested bar overlaps with current bars */ -+ if (MV_TRUE == pexBarOverlapDetect(pexIf,barNum, &pAddrWin->addrWin)) -+ { -+ mvOsPrintf("mvPexBarSet: ERR. Target %d overlap\n", barNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Get size register value according to window size */ -+ sizeToReg = ctrlSizeToReg(pAddrWin->addrWin.size, PXBCR_BAR_SIZE_ALIGNMENT); -+ -+ /* Read bar size */ -+ if (PEX_INTER_REGS_BAR != barNum) /* internal registers have no size */ -+ { -+ regSize = MV_REG_READ(PEX_BAR_CTRL_REG(pexIf,barNum)); -+ -+ /* Size parameter validity check. */ -+ if (-1 == sizeToReg) -+ { -+ mvOsPrintf("mvPexBarSet: ERR. Target BAR %d size invalid.\n",barNum); -+ return MV_BAD_PARAM; -+ } -+ -+ regSize &= ~PXBCR_BAR_SIZE_MASK; -+ regSize |= (sizeToReg << PXBCR_BAR_SIZE_OFFS) ; -+ -+ MV_REG_WRITE(PEX_BAR_CTRL_REG(pexIf,barNum),regSize); -+ -+ } -+ -+ /* set size */ -+ -+ -+ -+ /* Read base address low */ -+ regBaseLow = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, -+ PEX_MV_BAR_BASE(barNum))); -+ -+ /* clear current base */ -+ if (PEX_INTER_REGS_BAR == barNum) -+ { -+ regBaseLow &= ~PXBIR_BASE_MASK; -+ regBaseLow |= (pAddrWin->addrWin.baseLow & PXBIR_BASE_MASK); -+ } -+ else -+ { -+ regBaseLow &= ~PXBR_BASE_MASK; -+ regBaseLow |= (pAddrWin->addrWin.baseLow & PXBR_BASE_MASK); -+ } -+ -+ /* if we had a previous value that contain the bar type (MeM\IO), we want to -+ restore it */ -+ regBaseLow |= PEX_BAR_DEFAULT_ATTRIB; -+ -+ -+ -+ /* write base low */ -+ MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE(barNum)), -+ regBaseLow); -+ -+ if (pAddrWin->addrWin.baseHigh != 0) -+ { -+ /* Read base address high */ -+ MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE_HIGH(barNum)), -+ pAddrWin->addrWin.baseHigh); -+ -+ } -+ -+ /* lastly enable the Bar */ -+ if (pAddrWin->enable == MV_TRUE) -+ { -+ if (PEX_INTER_REGS_BAR != barNum) /* internal registers -+ are enabled always */ -+ { -+ MV_REG_BIT_SET(PEX_BAR_CTRL_REG(pexIf,barNum),PXBCR_BAR_EN); -+ } -+ } -+ else if (MV_FALSE == pAddrWin->enable) -+ { -+ if (PEX_INTER_REGS_BAR != barNum) /* internal registers -+ are enabled always */ -+ { -+ MV_REG_BIT_RESET(PEX_BAR_CTRL_REG(pexIf,barNum),PXBCR_BAR_EN); -+ } -+ -+ } -+ -+ -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPexBarGet - Get PEX bar address and size -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+ -+MV_STATUS mvPexBarGet(MV_U32 pexIf, -+ MV_U32 barNum, -+ MV_PEX_BAR *pAddrWin) -+{ -+ /* check parameters */ -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexBarGet: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ -+ if(barNum >= PEX_MAX_BARS) -+ { -+ mvOsPrintf("mvPexBarGet: ERR. Invalid bar number %d\n", barNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* read base low */ -+ pAddrWin->addrWin.baseLow = -+ MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE(barNum))); -+ -+ -+ if (PEX_INTER_REGS_BAR == barNum) -+ { -+ pAddrWin->addrWin.baseLow &= PXBIR_BASE_MASK; -+ } -+ else -+ { -+ pAddrWin->addrWin.baseLow &= PXBR_BASE_MASK; -+ } -+ -+ -+ /* read base high */ -+ pAddrWin->addrWin.baseHigh = -+ MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE_HIGH(barNum))); -+ -+ -+ /* Read bar size */ -+ if (PEX_INTER_REGS_BAR != barNum) /* internal registers have no size */ -+ { -+ pAddrWin->addrWin.size = MV_REG_READ(PEX_BAR_CTRL_REG(pexIf,barNum)); -+ -+ /* check if enable or not */ -+ if (pAddrWin->addrWin.size & PXBCR_BAR_EN) -+ { -+ pAddrWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrWin->enable = MV_FALSE; -+ } -+ -+ /* now get the size */ -+ pAddrWin->addrWin.size &= PXBCR_BAR_SIZE_MASK; -+ pAddrWin->addrWin.size >>= PXBCR_BAR_SIZE_OFFS; -+ -+ pAddrWin->addrWin.size = ctrlRegToSize(pAddrWin->addrWin.size, -+ PXBCR_BAR_SIZE_ALIGNMENT); -+ -+ } -+ else /* PEX_INTER_REGS_BAR */ -+ { -+ pAddrWin->addrWin.size = INTER_REGS_SIZE; -+ pAddrWin->enable = MV_TRUE; -+ } -+ -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvPexBarEnable - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+ -+ -+MV_STATUS mvPexBarEnable(MV_U32 pexIf, MV_U32 barNum, MV_BOOL enable) -+{ -+ -+ MV_PEX_BAR pexBar; -+ -+ /* check parameters */ -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexBarEnable: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ -+ -+ if(barNum >= PEX_MAX_BARS) -+ { -+ mvOsPrintf("mvPexBarEnable: ERR. Invalid bar number %d\n", barNum); -+ return MV_BAD_PARAM; -+ } -+ -+ if (PEX_INTER_REGS_BAR == barNum) -+ { -+ if (MV_TRUE == enable) -+ { -+ return MV_OK; -+ } -+ else -+ { -+ return MV_ERROR; -+ } -+ } -+ -+ -+ if (MV_FALSE == enable) -+ { -+ /* disable bar and quit */ -+ MV_REG_BIT_RESET(PEX_BAR_CTRL_REG(pexIf,barNum),PXBCR_BAR_EN); -+ return MV_OK; -+ } -+ -+ /* else */ -+ -+ if (mvPexBarGet(pexIf,barNum,&pexBar) != MV_OK) -+ { -+ mvOsPrintf("mvPexBarEnable: mvPexBarGet Failed\n"); -+ return MV_ERROR; -+ -+ } -+ -+ if (MV_TRUE == pexBar.enable) -+ { -+ /* it is already enabled !!! */ -+ return MV_OK; -+ } -+ -+ /* else enable the bar*/ -+ -+ pexBar.enable = MV_TRUE; -+ -+ if (mvPexBarSet(pexIf,barNum,&pexBar) != MV_OK) -+ { -+ mvOsPrintf("mvPexBarEnable: mvPexBarSet Failed\n"); -+ return MV_ERROR; -+ -+ } -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* pexWinOverlapDetect - Detect address windows overlapping -+* -+* DESCRIPTION: -+* This function detects address window overlapping of a given address -+* window in PEX BARs. -+* -+* INPUT: -+* pAddrWin - Address window to be checked. -+* bar - BAR to be accessed by slave. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+static MV_BOOL pexWinOverlapDetect(MV_U32 pexIf, -+ MV_U32 winNum, -+ MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 win; -+ MV_PEX_DEC_WIN addrDecWin; -+ -+ -+ for(win = 0; win < PEX_MAX_TARGET_WIN -2 ; win++) -+ { -+ /* don't check our target or illegal targets */ -+ if (winNum == win) -+ { -+ continue; -+ } -+ -+ /* Get window parameters */ -+ if (MV_OK != mvPexTargetWinGet(pexIf, win, &addrDecWin)) -+ { -+ mvOsPrintf("pexWinOverlapDetect: ERR. TargetWinGet failed win=%x\n", -+ win); -+ return MV_ERROR; -+ } -+ -+ /* Do not check disabled windows */ -+ if (MV_FALSE == addrDecWin.enable) -+ { -+ continue; -+ } -+ -+ -+ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) -+ { -+ mvOsPrintf("pexWinOverlapDetect: winNum %d overlap current %d\n", -+ winNum, win); -+ return MV_TRUE; -+ } -+ } -+ -+ return MV_FALSE; -+} -+ -+/******************************************************************************* -+* pexIsWinWithinBar - Detect if address is within PEX bar boundries -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+static MV_BOOL pexIsWinWithinBar(MV_U32 pexIf, -+ MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 bar; -+ MV_PEX_BAR addrDecWin; -+ -+ for(bar = 0; bar < PEX_MAX_BARS; bar++) -+ { -+ -+ /* Get window parameters */ -+ if (MV_OK != mvPexBarGet(pexIf, bar, &addrDecWin)) -+ { -+ mvOsPrintf("pexIsWinWithinBar: ERR. mvPexBarGet failed\n"); -+ return MV_ERROR; -+ } -+ -+ /* Do not check disabled bars */ -+ if (MV_FALSE == addrDecWin.enable) -+ { -+ continue; -+ } -+ -+ -+ if(MV_TRUE == ctrlWinWithinWinTest(pAddrWin, &addrDecWin.addrWin)) -+ { -+ return MV_TRUE; -+ } -+ } -+ -+ return MV_FALSE; -+ -+} -+ -+/******************************************************************************* -+* pexBarOverlapDetect - Detect address windows overlapping -+* -+* DESCRIPTION: -+* This function detects address window overlapping of a given address -+* window in PEX BARs. -+* -+* INPUT: -+* pAddrWin - Address window to be checked. -+* bar - BAR to be accessed by slave. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+static MV_BOOL pexBarOverlapDetect(MV_U32 pexIf, -+ MV_U32 barNum, -+ MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 bar; -+ MV_PEX_BAR barDecWin; -+ -+ -+ for(bar = 0; bar < PEX_MAX_BARS; bar++) -+ { -+ /* don't check our target or illegal targets */ -+ if (barNum == bar) -+ { -+ continue; -+ } -+ -+ /* Get window parameters */ -+ if (MV_OK != mvPexBarGet(pexIf, bar, &barDecWin)) -+ { -+ mvOsPrintf("pexBarOverlapDetect: ERR. TargetWinGet failed\n"); -+ return MV_ERROR; -+ } -+ -+ /* don'nt check disabled bars */ -+ if (barDecWin.enable == MV_FALSE) -+ { -+ continue; -+ } -+ -+ -+ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &barDecWin.addrWin)) -+ { -+ mvOsPrintf("pexBarOverlapDetect: winNum %d overlap current %d\n", -+ barNum, bar); -+ return MV_TRUE; -+ } -+ } -+ -+ return MV_FALSE; -+} -+ -+/******************************************************************************* -+* pexBarIsValid - Check if the given address window is valid -+* -+* DESCRIPTION: -+* PEX spec restrict BAR base to be aligned to BAR size. -+* This function checks if the given address window is valid. -+* -+* INPUT: -+* baseLow - 32bit low base address. -+* size - Window size. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the address window is valid, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+static MV_STATUS pexBarIsValid(MV_U32 baseLow, MV_U32 size) -+{ -+ -+ /* PCI spec restrict BAR base to be aligned to BAR size */ -+ if(MV_IS_NOT_ALIGN(baseLow, size)) -+ { -+ return MV_ERROR; -+ } -+ else -+ { -+ return MV_TRUE; -+ } -+ -+ return MV_TRUE; -+} -+ -+/******************************************************************************* -+* pexBarRegInfoGet - Get BAR register information -+* -+* DESCRIPTION: -+* PEX BARs registers offsets are inconsecutive. -+* This function gets a PEX BAR register information like register offsets -+* and function location of the BAR. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* bar - The PEX BAR in question. -+* -+* OUTPUT: -+* pBarRegInfo - BAR register info struct. -+* -+* RETURN: -+* MV_BAD_PARAM when bad parameters ,MV_ERROR on error ,othewise MV_OK -+* -+*******************************************************************************/ -+static MV_STATUS pexWinRegInfoGet(MV_U32 pexIf, -+ MV_U32 winNum, -+ PEX_WIN_REG_INFO *pWinRegInfo) -+{ -+ -+ if ((winNum >= 0)&&(winNum <=3)) -+ { -+ pWinRegInfo->baseLowRegOffs = PEX_WIN0_3_BASE_REG(pexIf,winNum); -+ pWinRegInfo->baseHighRegOffs = 0; -+ pWinRegInfo->sizeRegOffs = PEX_WIN0_3_CTRL_REG(pexIf,winNum); -+ pWinRegInfo->remapLowRegOffs = PEX_WIN0_3_REMAP_REG(pexIf,winNum); -+ pWinRegInfo->remapHighRegOffs = 0; -+ } -+ else if ((winNum >= 4)&&(winNum <=5)) -+ { -+ pWinRegInfo->baseLowRegOffs = PEX_WIN4_5_BASE_REG(pexIf,winNum); -+ pWinRegInfo->baseHighRegOffs = 0; -+ pWinRegInfo->sizeRegOffs = PEX_WIN4_5_CTRL_REG(pexIf,winNum); -+ pWinRegInfo->remapLowRegOffs = PEX_WIN4_5_REMAP_REG(pexIf,winNum); -+ pWinRegInfo->remapHighRegOffs = PEX_WIN4_5_REMAP_HIGH_REG(pexIf,winNum); -+ -+ } -+ else if (MV_PEX_WIN_DEFAULT == winNum) -+ { -+ pWinRegInfo->baseLowRegOffs = 0; -+ pWinRegInfo->baseHighRegOffs = 0; -+ pWinRegInfo->sizeRegOffs = PEX_WIN_DEFAULT_CTRL_REG(pexIf); -+ pWinRegInfo->remapLowRegOffs = 0; -+ pWinRegInfo->remapHighRegOffs = 0; -+ } -+ else if (MV_PEX_WIN_EXP_ROM == winNum) -+ { -+ pWinRegInfo->baseLowRegOffs = 0; -+ pWinRegInfo->baseHighRegOffs = 0; -+ pWinRegInfo->sizeRegOffs = PEX_WIN_EXP_ROM_CTRL_REG(pexIf); -+ pWinRegInfo->remapLowRegOffs = PEX_WIN_EXP_ROM_REMAP_REG(pexIf); -+ pWinRegInfo->remapHighRegOffs = 0; -+ -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* pexBarNameGet - Get the string name of PEX BAR. -+* -+* DESCRIPTION: -+* This function get the string name of PEX BAR. -+* -+* INPUT: -+* bar - PEX bar number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* pointer to the string name of PEX BAR. -+* -+*******************************************************************************/ -+const MV_8* pexBarNameGet( MV_U32 bar ) -+{ -+ switch( bar ) -+ { -+ case PEX_INTER_REGS_BAR: -+ return "Internal Regs Bar0...."; -+ case PEX_DRAM_BAR: -+ return "DRAM Bar1............."; -+ case PEX_DEVICE_BAR: -+ return "Devices Bar2.........."; -+ default: -+ return "Bar unknown"; -+ } -+} -+/******************************************************************************* -+* mvPexAddrDecShow - Print the PEX address decode map (BARs and windows). -+* -+* DESCRIPTION: -+* This function print the PEX address decode map (BARs and windows). -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvPexAddrDecShow(MV_VOID) -+{ -+ MV_PEX_BAR pexBar; -+ MV_PEX_DEC_WIN win; -+ MV_U32 pexIf; -+ MV_U32 bar,winNum; -+ -+ for( pexIf = 0; pexIf < mvCtrlPexMaxIfGet(); pexIf++ ) -+ { -+ if (MV_FALSE == mvCtrlPwrClckGet(PEX_UNIT_ID, pexIf)) continue; -+ mvOsOutput( "\n" ); -+ mvOsOutput( "PEX%d:\n", pexIf ); -+ mvOsOutput( "-----\n" ); -+ -+ mvOsOutput( "\nPex Bars \n\n"); -+ -+ for( bar = 0; bar < PEX_MAX_BARS; bar++ ) -+ { -+ memset( &pexBar, 0, sizeof(MV_PEX_BAR) ); -+ -+ mvOsOutput( "%s ", pexBarNameGet(bar) ); -+ -+ if( mvPexBarGet( pexIf, bar, &pexBar ) == MV_OK ) -+ { -+ if( pexBar.enable ) -+ { -+ mvOsOutput( "base %08x, ", pexBar.addrWin.baseLow ); -+ mvSizePrint( pexBar.addrWin.size ); -+ mvOsOutput( "\n" ); -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ } -+ } -+ mvOsOutput( "\nPex Decode Windows\n\n"); -+ -+ for( winNum = 0; winNum < PEX_MAX_TARGET_WIN - 2; winNum++) -+ { -+ memset( &win, 0,sizeof(MV_PEX_DEC_WIN) ); -+ -+ mvOsOutput( "win%d - ", winNum ); -+ -+ if ( mvPexTargetWinGet(pexIf,winNum,&win) == MV_OK) -+ { -+ if (win.enable) -+ { -+ mvOsOutput( "%s base %08x, ", -+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); -+ mvOsOutput( "...." ); -+ mvSizePrint( win.addrWin.size ); -+ -+ mvOsOutput( "\n" ); -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ -+ -+ } -+ } -+ -+ memset( &win, 0,sizeof(MV_PEX_DEC_WIN) ); -+ -+ mvOsOutput( "default win - " ); -+ -+ if ( mvPexTargetWinGet(pexIf, MV_PEX_WIN_DEFAULT, &win) == MV_OK) -+ { -+ mvOsOutput( "%s ", -+ mvCtrlTargetNameGet(win.target) ); -+ mvOsOutput( "\n" ); -+ } -+ memset( &win, 0,sizeof(MV_PEX_DEC_WIN) ); -+ -+ mvOsOutput( "Expansion ROM - " ); -+ -+ if ( mvPexTargetWinGet(pexIf, MV_PEX_WIN_EXP_ROM, &win) == MV_OK) -+ { -+ mvOsOutput( "%s ", -+ mvCtrlTargetNameGet(win.target) ); -+ mvOsOutput( "\n" ); -+ } -+ -+ } -+} -+ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.h 2010-11-09 20:28:08.372495456 +0100 -@@ -0,0 +1,348 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCSysPEXH -+#define __INCSysPEXH -+ -+#include "mvCommon.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+ -+/* 4KB granularity */ -+#define MINIMUM_WINDOW_SIZE 0x1000 -+#define MINIMUM_BAR_SIZE 0x1000 -+#define MINIMUM_BAR_SIZE_MASK 0xFFFFF000 -+#define BAR_SIZE_OFFS 12 -+#define BAR_SIZE_MASK (0xFFFFF << BAR_SIZE_OFFS) -+ -+ -+ -+#define MV_PEX_WIN_DEFAULT 6 -+#define MV_PEX_WIN_EXP_ROM 7 -+#define PEX_MAX_TARGET_WIN 8 -+ -+ -+#define PEX_MAX_BARS 3 -+#define PEX_INTER_REGS_BAR 0 -+#define PEX_DRAM_BAR 1 -+#define PEX_DEVICE_BAR 2 -+ -+/*************************************/ -+/* PCI Express BAR Control Registers */ -+/*************************************/ -+#define PEX_BAR_CTRL_REG(pexIf,bar) (0x41804 + (bar-1)*4- (pexIf)*0x10000) -+#define PEX_EXP_ROM_BAR_CTRL_REG(pexIf) (0x4180C - (pexIf)*0x10000) -+ -+ -+/* PCI Express BAR Control Register */ -+/* PEX_BAR_CTRL_REG (PXBCR) */ -+ -+#define PXBCR_BAR_EN BIT0 -+#define PXBCR_BAR_SIZE_OFFS 16 -+#define PXBCR_BAR_SIZE_MASK (0xffff << PXBCR_BAR_SIZE_OFFS) -+#define PXBCR_BAR_SIZE_ALIGNMENT 0x10000 -+ -+ -+ -+/* PCI Express Expansion ROM BAR Control Register */ -+/* PEX_EXP_ROM_BAR_CTRL_REG (PXERBCR) */ -+ -+#define PXERBCR_EXPROM_EN BIT0 -+#define PXERBCR_EXPROMSZ_OFFS 19 -+#define PXERBCR_EXPROMSZ_MASK (0xf << PXERBCR_EXPROMSZ_OFFS) -+#define PXERBCR_EXPROMSZ_512KB (0x0 << PXERBCR_EXPROMSZ_OFFS) -+#define PXERBCR_EXPROMSZ_1024KB (0x1 << PXERBCR_EXPROMSZ_OFFS) -+#define PXERBCR_EXPROMSZ_2048KB (0x3 << PXERBCR_EXPROMSZ_OFFS) -+#define PXERBCR_EXPROMSZ_4096KB (0x7 << PXERBCR_EXPROMSZ_OFFS) -+ -+/************************************************/ -+/* PCI Express Address Window Control Registers */ -+/************************************************/ -+#define PEX_WIN0_3_CTRL_REG(pexIf,winNum) \ -+ (0x41820 + (winNum) * 0x10 - (pexIf) * 0x10000) -+#define PEX_WIN0_3_BASE_REG(pexIf,winNum) \ -+ (0x41824 + (winNum) * 0x10 - (pexIf) * 0x10000) -+#define PEX_WIN0_3_REMAP_REG(pexIf,winNum) \ -+ (0x4182C + (winNum) * 0x10 - (pexIf) * 0x10000) -+#define PEX_WIN4_5_CTRL_REG(pexIf,winNum) \ -+ (0x41860 + (winNum - 4) * 0x20 - (pexIf) * 0x10000) -+#define PEX_WIN4_5_BASE_REG(pexIf,winNum) \ -+ (0x41864 + (winNum - 4) * 0x20 - (pexIf) * 0x10000) -+#define PEX_WIN4_5_REMAP_REG(pexIf,winNum) \ -+ (0x4186C + (winNum - 4) * 0x20 - (pexIf) * 0x10000) -+#define PEX_WIN4_5_REMAP_HIGH_REG(pexIf,winNum) \ -+ (0x41870 + (winNum - 4) * 0x20 - (pexIf) * 0x10000) -+ -+#define PEX_WIN_DEFAULT_CTRL_REG(pexIf) (0x418B0 - (pexIf) * 0x10000) -+#define PEX_WIN_EXP_ROM_CTRL_REG(pexIf) (0x418C0 - (pexIf) * 0x10000) -+#define PEX_WIN_EXP_ROM_REMAP_REG(pexIf) (0x418C4 - (pexIf) * 0x10000) -+ -+/* PCI Express Window Control Register */ -+/* PEX_WIN_CTRL_REG (PXWCR) */ -+ -+#define PXWCR_WIN_EN BIT0 /* Window Enable.*/ -+ -+#define PXWCR_WIN_BAR_MAP_OFFS 1 /* Mapping to BAR.*/ -+#define PXWCR_WIN_BAR_MAP_MASK BIT1 -+#define PXWCR_WIN_BAR_MAP_BAR1 (0 << PXWCR_WIN_BAR_MAP_OFFS) -+#define PXWCR_WIN_BAR_MAP_BAR2 (1 << PXWCR_WIN_BAR_MAP_OFFS) -+ -+#define PXWCR_TARGET_OFFS 4 /*Unit ID */ -+#define PXWCR_TARGET_MASK (0xf << PXWCR_TARGET_OFFS) -+ -+#define PXWCR_ATTRIB_OFFS 8 /* target attributes */ -+#define PXWCR_ATTRIB_MASK (0xff << PXWCR_ATTRIB_OFFS) -+ -+#define PXWCR_SIZE_OFFS 16 /* size */ -+#define PXWCR_SIZE_MASK (0xffff << PXWCR_SIZE_OFFS) -+#define PXWCR_SIZE_ALIGNMENT 0x10000 -+ -+/* PCI Express Window Base Register */ -+/* PEX_WIN_BASE_REG (PXWBR)*/ -+ -+#define PXWBR_BASE_OFFS 16 /* address[31:16] */ -+#define PXWBR_BASE_MASK (0xffff << PXWBR_BASE_OFFS) -+#define PXWBR_BASE_ALIGNMENT 0x10000 -+ -+/* PCI Express Window Remap Register */ -+/* PEX_WIN_REMAP_REG (PXWRR)*/ -+ -+#define PXWRR_REMAP_EN BIT0 -+#define PXWRR_REMAP_OFFS 16 -+#define PXWRR_REMAP_MASK (0xffff << PXWRR_REMAP_OFFS) -+#define PXWRR_REMAP_ALIGNMENT 0x10000 -+ -+/* PCI Express Window Remap (High) Register */ -+/* PEX_WIN_REMAP_HIGH_REG (PXWRHR)*/ -+ -+#define PXWRHR_REMAP_HIGH_OFFS 0 -+#define PXWRHR_REMAP_HIGH_MASK (0xffffffff << PXWRHR_REMAP_HIGH_OFFS) -+ -+/* PCI Express Default Window Control Register */ -+/* PEX_WIN_DEFAULT_CTRL_REG (PXWDCR) */ -+ -+#define PXWDCR_TARGET_OFFS 4 /*Unit ID */ -+#define PXWDCR_TARGET_MASK (0xf << PXWDCR_TARGET_OFFS) -+#define PXWDCR_ATTRIB_OFFS 8 /* target attributes */ -+#define PXWDCR_ATTRIB_MASK (0xff << PXWDCR_ATTRIB_OFFS) -+ -+/* PCI Express Expansion ROM Window Control Register */ -+/* PEX_WIN_EXP_ROM_CTRL_REG (PXWERCR)*/ -+ -+#define PXWERCR_TARGET_OFFS 4 /*Unit ID */ -+#define PXWERCR_TARGET_MASK (0xf << PXWERCR_TARGET_OFFS) -+#define PXWERCR_ATTRIB_OFFS 8 /* target attributes */ -+#define PXWERCR_ATTRIB_MASK (0xff << PXWERCR_ATTRIB_OFFS) -+ -+/* PCI Express Expansion ROM Window Remap Register */ -+/* PEX_WIN_EXP_ROM_REMAP_REG (PXWERRR)*/ -+ -+#define PXWERRR_REMAP_EN BIT0 -+#define PXWERRR_REMAP_OFFS 16 -+#define PXWERRR_REMAP_MASK (0xffff << PXWERRR_REMAP_OFFS) -+#define PXWERRR_REMAP_ALIGNMENT 0x10000 -+ -+ -+ -+/*PEX_MEMORY_BAR_BASE_ADDR(barNum) (PXMBBA)*/ -+/* PCI Express BAR0 Internal Register*/ -+/*PEX BAR0_INTER_REG (PXBIR)*/ -+ -+#define PXBIR_IOSPACE BIT0 /* Memory Space Indicator */ -+ -+#define PXBIR_TYPE_OFFS 1 /* BAR Type/Init Val. */ -+#define PXBIR_TYPE_MASK (0x3 << PXBIR_TYPE_OFFS) -+#define PXBIR_TYPE_32BIT_ADDR (0x0 << PXBIR_TYPE_OFFS) -+#define PXBIR_TYPE_64BIT_ADDR (0x2 << PXBIR_TYPE_OFFS) -+ -+#define PXBIR_PREFETCH_EN BIT3 /* Prefetch Enable */ -+ -+#define PXBIR_BASE_OFFS 20 /* Base address. Address bits [31:20] */ -+#define PXBIR_BASE_MASK (0xfff << PXBIR_BASE_OFFS) -+#define PXBIR_BASE_ALIGNMET (1 << PXBIR_BASE_OFFS) -+ -+ -+/* PCI Express BAR0 Internal (High) Register*/ -+/*PEX BAR0_INTER_REG_HIGH (PXBIRH)*/ -+ -+#define PXBIRH_BASE_OFFS 0 /* Base address. Bits [63:32] */ -+#define PXBIRH_BASE_MASK (0xffffffff << PBBHR_BASE_OFFS) -+ -+ -+#define PEX_BAR_DEFAULT_ATTRIB 0xc /* Memory - Prefetch - 64 bit address */ -+#define PEX_BAR0_DEFAULT_ATTRIB PEX_BAR_DEFAULT_ATTRIB -+#define PEX_BAR1_DEFAULT_ATTRIB PEX_BAR_DEFAULT_ATTRIB -+#define PEX_BAR2_DEFAULT_ATTRIB PEX_BAR_DEFAULT_ATTRIB -+ -+ -+/* PCI Express BAR1 Register */ -+/* PCI Express BAR2 Register*/ -+/*PEX BAR1_REG (PXBR)*/ -+/*PEX BAR2_REG (PXBR)*/ -+ -+#define PXBR_IOSPACE BIT0 /* Memory Space Indicator */ -+ -+#define PXBR_TYPE_OFFS 1 /* BAR Type/Init Val. */ -+#define PXBR_TYPE_MASK (0x3 << PXBR_TYPE_OFFS) -+#define PXBR_TYPE_32BIT_ADDR (0x0 << PXBR_TYPE_OFFS) -+#define PXBR_TYPE_64BIT_ADDR (0x2 << PXBR_TYPE_OFFS) -+ -+#define PXBR_PREFETCH_EN BIT3 /* Prefetch Enable */ -+ -+#define PXBR_BASE_OFFS 16 /* Base address. Address bits [31:16] */ -+#define PXBR_BASE_MASK (0xffff << PXBR_BASE_OFFS) -+#define PXBR_BASE_ALIGNMET (1 << PXBR_BASE_OFFS) -+ -+ -+/* PCI Express BAR1 (High) Register*/ -+/* PCI Express BAR2 (High) Register*/ -+/*PEX BAR1_REG_HIGH (PXBRH)*/ -+/*PEX BAR2_REG_HIGH (PXBRH)*/ -+ -+#define PXBRH_BASE_OFFS 0 /* Base address. Address bits [63:32] */ -+#define PXBRH_BASE_MASK (0xffffffff << PXBRH_BASE_OFFS) -+ -+/* PCI Express Expansion ROM BAR Register*/ -+/*PEX_EXPANSION_ROM_BASE_ADDR_REG (PXERBAR)*/ -+ -+#define PXERBAR_EXPROMEN BIT0 /* Expansion ROM Enable */ -+ -+#define PXERBAR_BASE_512K_OFFS 19 /* Expansion ROM Base Address */ -+#define PXERBAR_BASE_512K_MASK (0x1fff << PXERBAR_BASE_512K_OFFS) -+ -+#define PXERBAR_BASE_1MB_OFFS 20 /* Expansion ROM Base Address */ -+#define PXERBAR_BASE_1MB_MASK (0xfff << PXERBAR_BASE_1MB_OFFS) -+ -+#define PXERBAR_BASE_2MB_OFFS 21 /* Expansion ROM Base Address */ -+#define PXERBAR_BASE_2MB_MASK (0x7ff << PXERBAR_BASE_2MB_OFFS) -+ -+#define PXERBAR_BASE_4MB_OFFS 22 /* Expansion ROM Base Address */ -+#define PXERBAR_BASE_4MB_MASK (0x3ff << PXERBAR_BASE_4MB_OFFS) -+ -+/* PEX Bar attributes */ -+typedef struct _mvPexBar -+{ -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+}MV_PEX_BAR; -+ -+/* PEX Remap Window attributes */ -+typedef struct _mvPexRemapWin -+{ -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+}MV_PEX_REMAP_WIN; -+ -+/* PEX Remap Window attributes */ -+typedef struct _mvPexDecWin -+{ -+ MV_TARGET target; -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_U32 targetBar; -+ MV_U8 attrib; /* chip select attributes */ -+ MV_TARGET_ID targetId; /* Target Id of this MV_TARGET */ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+}MV_PEX_DEC_WIN; -+ -+/* Global Functions prototypes */ -+/* mvPexHalInit - Initialize PEX interfaces*/ -+MV_STATUS mvPexInit(MV_U32 pexIf, MV_PEX_TYPE pexType); -+ -+ -+/* mvPexTargetWinSet - Set PEX to peripheral target address window BAR*/ -+MV_STATUS mvPexTargetWinSet(MV_U32 pexIf, MV_U32 winNum, -+ MV_PEX_DEC_WIN *pAddrDecWin); -+ -+/* mvPexTargetWinGet - Get PEX to peripheral target address window*/ -+MV_STATUS mvPexTargetWinGet(MV_U32 pexIf, MV_U32 winNum, -+ MV_PEX_DEC_WIN *pAddrDecWin); -+ -+/* mvPexTargetWinEnable - Enable/disable a PEX BAR window*/ -+MV_STATUS mvPexTargetWinEnable(MV_U32 pexIf,MV_U32 winNum, MV_BOOL enable); -+ -+/* mvPexTargetWinRemap - Set PEX to target address window remap.*/ -+MV_STATUS mvPexTargetWinRemap(MV_U32 pexIf, MV_U32 winNum, -+ MV_PEX_REMAP_WIN *pAddrWin); -+ -+/* mvPexTargetWinRemapEnable -enable\disable a PEX Window remap.*/ -+MV_STATUS mvPexTargetWinRemapEnable(MV_U32 pexIf, MV_U32 winNum, -+ MV_BOOL enable); -+ -+/* mvPexBarSet - Set PEX bar address and size */ -+MV_STATUS mvPexBarSet(MV_U32 pexIf, MV_U32 barNum, MV_PEX_BAR *addrWin); -+ -+/* mvPexBarGet - Get PEX bar address and size */ -+MV_STATUS mvPexBarGet(MV_U32 pexIf, MV_U32 barNum, MV_PEX_BAR *addrWin); -+ -+/* mvPexBarEnable - enable\disable a PEX bar*/ -+MV_STATUS mvPexBarEnable(MV_U32 pexIf, MV_U32 barNum, MV_BOOL enable); -+ -+/* mvPexAddrDecShow - Display address decode windows attributes */ -+MV_VOID mvPexAddrDecShow(MV_VOID); -+ -+#endif -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.c 2010-11-09 20:28:08.402495399 +0100 -@@ -0,0 +1,430 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#include "mvTypes.h" -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "cpu/mvCpu.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+#include "sata/CoreDriver/mvRegs.h" -+#include "ctrlEnv/sys/mvSysSata.h" -+ -+MV_TARGET sataAddrDecPrioTab[] = -+{ -+#if defined(MV_INCLUDE_SDRAM_CS0) -+ SDRAM_CS0, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS1) -+ SDRAM_CS1, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS2) -+ SDRAM_CS2, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS3) -+ SDRAM_CS3, -+#endif -+#if defined(MV_INCLUDE_PEX) -+ PEX0_MEM, -+#endif -+ TBL_TERM -+}; -+ -+ -+/******************************************************************************* -+* sataWinOverlapDetect - Detect SATA address windows overlapping -+* -+* DESCRIPTION: -+* An unpredicted behaviur is expected in case SATA address decode -+* windows overlapps. -+* This function detects SATA address decode windows overlapping of a -+* specified window. The function does not check the window itself for -+* overlapping. The function also skipps disabled address decode windows. -+* -+* INPUT: -+* winNum - address decode window number. -+* pAddrDecWin - An address decode window struct. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data -+* from registers. -+* -+*******************************************************************************/ -+static MV_STATUS sataWinOverlapDetect(int dev, MV_U32 winNum, -+ MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 winNumIndex; -+ MV_SATA_DEC_WIN addrDecWin; -+ -+ for(winNumIndex=0; winNumIndex= MV_SATA_MAX_ADDR_DECODE_WIN) -+ { -+ mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlapps with current windows */ -+ if (MV_TRUE == sataWinOverlapDetect(dev, winNum, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); -+ return MV_ERROR; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvSataWinSet:Error setting SATA window %d to "\ -+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, -+ mvCtrlTargetNameGet(pAddrDecWin->target), -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ decRegs.baseReg = 0; -+ decRegs.sizeReg = 0; -+ -+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) -+ { -+ mvOsPrintf("%s: mvCtrlAddrDecToReg Failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); -+ -+ /* set attributes */ -+ decRegs.sizeReg &= ~MV_SATA_WIN_ATTR_MASK; -+ decRegs.sizeReg |= (targetAttribs.attrib << MV_SATA_WIN_ATTR_OFFSET); -+ -+ /* set target ID */ -+ decRegs.sizeReg &= ~MV_SATA_WIN_TARGET_MASK; -+ decRegs.sizeReg |= (targetAttribs.targetId << MV_SATA_WIN_TARGET_OFFSET); -+ -+ if (pAddrDecWin->enable == MV_TRUE) -+ { -+ decRegs.sizeReg |= MV_SATA_WIN_ENABLE_MASK; -+ } -+ else -+ { -+ decRegs.sizeReg &= ~MV_SATA_WIN_ENABLE_MASK; -+ } -+ -+ MV_REG_WRITE( MV_SATA_WIN_CTRL_REG(dev, winNum), decRegs.sizeReg); -+ MV_REG_WRITE( MV_SATA_WIN_BASE_REG(dev, winNum), decRegs.baseReg); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSataWinGet - Get SATA peripheral target address window. -+* -+* DESCRIPTION: -+* Get SATA peripheral target address window. -+* -+* INPUT: -+* winNum - SATA target address decode window number. -+* -+* OUTPUT: -+* pAddrDecWin - SATA target window data structure. -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvSataWinGet(int dev, MV_U32 winNum, MV_SATA_DEC_WIN *pAddrDecWin) -+{ -+ MV_DEC_REGS decRegs; -+ MV_TARGET_ATTRIB targetAttrib; -+ -+ /* Parameter checking */ -+ if (winNum >= MV_SATA_MAX_ADDR_DECODE_WIN) -+ { -+ mvOsPrintf("%s (dev=%d): ERR. Invalid winNum %d\n", -+ __FUNCTION__, dev, winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ decRegs.baseReg = MV_REG_READ( MV_SATA_WIN_BASE_REG(dev, winNum) ); -+ decRegs.sizeReg = MV_REG_READ( MV_SATA_WIN_CTRL_REG(dev, winNum) ); -+ -+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs, &pAddrDecWin->addrWin) ) -+ { -+ mvOsPrintf("%s: mvCtrlRegToAddrDec Failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ /* attrib and targetId */ -+ targetAttrib.attrib = (decRegs.sizeReg & MV_SATA_WIN_ATTR_MASK) >> -+ MV_SATA_WIN_ATTR_OFFSET; -+ targetAttrib.targetId = (decRegs.sizeReg & MV_SATA_WIN_TARGET_MASK) >> -+ MV_SATA_WIN_TARGET_OFFSET; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ /* Check if window is enabled */ -+ if(decRegs.sizeReg & MV_SATA_WIN_ENABLE_MASK) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ } -+ return MV_OK; -+} -+/******************************************************************************* -+* mvSataAddrDecShow - Print the SATA address decode map. -+* -+* DESCRIPTION: -+* This function print the SATA address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvSataAddrDecShow(MV_VOID) -+{ -+ -+ MV_SATA_DEC_WIN win; -+ int i,j; -+ -+ -+ -+ for( j = 0; j < MV_SATA_MAX_CHAN; j++ ) -+ { -+ if (MV_FALSE == mvCtrlPwrClckGet(SATA_UNIT_ID, j)) -+ return; -+ -+ mvOsOutput( "\n" ); -+ mvOsOutput( "SATA %d:\n", j ); -+ mvOsOutput( "----\n" ); -+ -+ for( i = 0; i < MV_SATA_MAX_ADDR_DECODE_WIN; i++ ) -+ { -+ memset( &win, 0, sizeof(MV_SATA_DEC_WIN) ); -+ -+ mvOsOutput( "win%d - ", i ); -+ -+ if( mvSataWinGet(j, i, &win ) == MV_OK ) -+ { -+ if( win.enable ) -+ { -+ mvOsOutput( "%s base %08x, ", -+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); -+ mvOsOutput( "...." ); -+ -+ mvSizePrint( win.addrWin.size ); -+ -+ mvOsOutput( "\n" ); -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ } -+ } -+ } -+} -+ -+ -+/******************************************************************************* -+* mvSataWinInit - Initialize the integrated SATA target address window. -+* -+* DESCRIPTION: -+* Initialize the SATA peripheral target address window. -+* -+* INPUT: -+* -+* -+* OUTPUT: -+* -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvSataWinInit(MV_VOID) -+{ -+ int winNum; -+ MV_SATA_DEC_WIN sataWin; -+ MV_CPU_DEC_WIN cpuAddrDecWin; -+ MV_U32 status, winPrioIndex = 0; -+ -+ /* Initiate Sata address decode */ -+ -+ /* First disable all address decode windows */ -+ for(winNum = 0; winNum < MV_SATA_MAX_ADDR_DECODE_WIN; winNum++) -+ { -+ MV_U32 regVal = MV_REG_READ(MV_SATA_WIN_CTRL_REG(0, winNum)); -+ regVal &= ~MV_SATA_WIN_ENABLE_MASK; -+ MV_REG_WRITE(MV_SATA_WIN_CTRL_REG(0, winNum), regVal); -+ } -+ -+ winNum = 0; -+ while( (sataAddrDecPrioTab[winPrioIndex] != TBL_TERM) && -+ (winNum < MV_SATA_MAX_ADDR_DECODE_WIN) ) -+ { -+ /* first get attributes from CPU If */ -+ status = mvCpuIfTargetWinGet(sataAddrDecPrioTab[winPrioIndex], -+ &cpuAddrDecWin); -+ -+ if(MV_NO_SUCH == status) -+ { -+ winPrioIndex++; -+ continue; -+ } -+ if (MV_OK != status) -+ { -+ mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ if (cpuAddrDecWin.enable == MV_TRUE) -+ { -+ sataWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; -+ sataWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; -+ sataWin.addrWin.size = cpuAddrDecWin.addrWin.size; -+ sataWin.enable = MV_TRUE; -+ sataWin.target = sataAddrDecPrioTab[winPrioIndex]; -+ -+ if(MV_OK != mvSataWinSet(0/*dev*/, winNum, &sataWin)) -+ { -+ return MV_ERROR; -+ } -+ winNum++; -+ } -+ winPrioIndex++; -+ } -+ return MV_OK; -+} -+ -+ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.h 2010-11-09 20:28:08.526524216 +0100 -@@ -0,0 +1,128 @@ -+ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#ifndef __INCMVSysSataAddrDech -+#define __INCMVSysSataAddrDech -+ -+#include "mvCommon.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+ -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+typedef struct _mvSataDecWin -+{ -+ MV_TARGET target; -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+} MV_SATA_DEC_WIN; -+ -+ -+#define MV_SATA_MAX_ADDR_DECODE_WIN 4 -+ -+#define MV_SATA_WIN_CTRL_REG(dev, win) (SATA_REG_BASE + 0x30 + ((win)<<4)) -+#define MV_SATA_WIN_BASE_REG(dev, win) (SATA_REG_BASE + 0x34 + ((win)<<4)) -+ -+/* BITs in Bridge Interrupt Cause and Mask registers */ -+#define MV_SATA_ADDR_DECODE_ERROR_BIT 0 -+#define MV_SATA_ADDR_DECODE_ERROR_MASK (1<= MV_SDMMC_MAX_ADDR_DECODE_WIN) -+ { -+ mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlapps with current windows */ -+ if (MV_TRUE == sdmmcWinOverlapDetect(dev, winNum, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); -+ return MV_ERROR; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvSdmmcWinSet:Error setting SDMMC window %d to "\ -+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, -+ mvCtrlTargetNameGet(pAddrDecWin->target), -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ decRegs.baseReg = 0; -+ decRegs.sizeReg = 0; -+ -+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) -+ { -+ mvOsPrintf("%s: mvCtrlAddrDecToReg Failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); -+ -+ /* set attributes */ -+ decRegs.sizeReg &= ~MV_SDMMC_WIN_ATTR_MASK; -+ decRegs.sizeReg |= (targetAttribs.attrib << MV_SDMMC_WIN_ATTR_OFFSET); -+ -+ /* set target ID */ -+ decRegs.sizeReg &= ~MV_SDMMC_WIN_TARGET_MASK; -+ decRegs.sizeReg |= (targetAttribs.targetId << MV_SDMMC_WIN_TARGET_OFFSET); -+ -+ if (pAddrDecWin->enable == MV_TRUE) -+ { -+ decRegs.sizeReg |= MV_SDMMC_WIN_ENABLE_MASK; -+ } -+ else -+ { -+ decRegs.sizeReg &= ~MV_SDMMC_WIN_ENABLE_MASK; -+ } -+ -+ MV_REG_WRITE( MV_SDMMC_WIN_CTRL_REG(dev, winNum), decRegs.sizeReg); -+ MV_REG_WRITE( MV_SDMMC_WIN_BASE_REG(dev, winNum), decRegs.baseReg); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSdmmcWinGet - Get SDMMC peripheral target address window. -+* -+* DESCRIPTION: -+* Get SDMMC peripheral target address window. -+* -+* INPUT: -+* winNum - SDMMC target address decode window number. -+*d -+* OUTPUT: -+* pAddrDecWin - SDMMC target window data structure. -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvSdmmcWinGet(int dev, MV_U32 winNum, MV_SDMMC_DEC_WIN *pAddrDecWin) -+{ -+ MV_DEC_REGS decRegs; -+ MV_TARGET_ATTRIB targetAttrib; -+ -+ /* Parameter checking */ -+ if (winNum >= MV_SDMMC_MAX_ADDR_DECODE_WIN) -+ { -+ mvOsPrintf("%s (dev=%d): ERR. Invalid winNum %d\n", -+ __FUNCTION__, dev, winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ decRegs.baseReg = MV_REG_READ( MV_SDMMC_WIN_BASE_REG(dev, winNum) ); -+ decRegs.sizeReg = MV_REG_READ( MV_SDMMC_WIN_CTRL_REG(dev, winNum) ); -+ -+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs, &pAddrDecWin->addrWin) ) -+ { -+ mvOsPrintf("%s: mvCtrlRegToAddrDec Failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ /* attrib and targetId */ -+ targetAttrib.attrib = (decRegs.sizeReg & MV_SDMMC_WIN_ATTR_MASK) >> -+ MV_SDMMC_WIN_ATTR_OFFSET; -+ targetAttrib.targetId = (decRegs.sizeReg & MV_SDMMC_WIN_TARGET_MASK) >> -+ MV_SDMMC_WIN_TARGET_OFFSET; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ /* Check if window is enabled */ -+ if(decRegs.sizeReg & MV_SDMMC_WIN_ENABLE_MASK) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ } -+ return MV_OK; -+} -+/******************************************************************************* -+* mvSdmmcAddrDecShow - Print the SDMMC address decode map. -+* -+* DESCRIPTION: -+* This function print the SDMMC address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvSdmmcAddrDecShow(MV_VOID) -+{ -+ -+ MV_SDMMC_DEC_WIN win; -+ int i,j=0; -+ -+ -+ -+ if (MV_FALSE == mvCtrlPwrClckGet(SDIO_UNIT_ID, 0)) -+ return; -+ -+ mvOsOutput( "\n" ); -+ mvOsOutput( "SDMMC %d:\n", j ); -+ mvOsOutput( "----\n" ); -+ -+ for( i = 0; i < MV_SDMMC_MAX_ADDR_DECODE_WIN; i++ ) -+ { -+ memset( &win, 0, sizeof(MV_SDMMC_DEC_WIN) ); -+ -+ mvOsOutput( "win%d - ", i ); -+ -+ if( mvSdmmcWinGet(j, i, &win ) == MV_OK ) -+ { -+ if( win.enable ) -+ { -+ mvOsOutput( "%s base %08x, ", -+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); -+ mvOsOutput( "...." ); -+ -+ mvSizePrint( win.addrWin.size ); -+ -+ mvOsOutput( "\n" ); -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ } -+ } -+} -+ -+ -+/******************************************************************************* -+* mvSdmmcWinInit - Initialize the integrated SDMMC target address window. -+* -+* DESCRIPTION: -+* Initialize the SDMMC peripheral target address window. -+* -+* INPUT: -+* -+* -+* OUTPUT: -+* -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvSdmmcWinInit(MV_VOID) -+{ -+ int winNum; -+ MV_SDMMC_DEC_WIN sdmmcWin; -+ MV_CPU_DEC_WIN cpuAddrDecWin; -+ MV_U32 status, winPrioIndex = 0; -+ -+ /* Initiate Sdmmc address decode */ -+ -+ /* First disable all address decode windows */ -+ for(winNum = 0; winNum < MV_SDMMC_MAX_ADDR_DECODE_WIN; winNum++) -+ { -+ MV_U32 regVal = MV_REG_READ(MV_SDMMC_WIN_CTRL_REG(0, winNum)); -+ regVal &= ~MV_SDMMC_WIN_ENABLE_MASK; -+ MV_REG_WRITE(MV_SDMMC_WIN_CTRL_REG(0, winNum), regVal); -+ } -+ -+ winNum = 0; -+ while( (sdmmcAddrDecPrioTab[winPrioIndex] != TBL_TERM) && -+ (winNum < MV_SDMMC_MAX_ADDR_DECODE_WIN) ) -+ { -+ /* first get attributes from CPU If */ -+ status = mvCpuIfTargetWinGet(sdmmcAddrDecPrioTab[winPrioIndex], -+ &cpuAddrDecWin); -+ -+ if(MV_NO_SUCH == status) -+ { -+ winPrioIndex++; -+ continue; -+ } -+ if (MV_OK != status) -+ { -+ mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ if (cpuAddrDecWin.enable == MV_TRUE) -+ { -+ sdmmcWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; -+ sdmmcWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; -+ sdmmcWin.addrWin.size = cpuAddrDecWin.addrWin.size; -+ sdmmcWin.enable = MV_TRUE; -+ sdmmcWin.target = sdmmcAddrDecPrioTab[winPrioIndex]; -+ -+ if(MV_OK != mvSdmmcWinSet(0/*dev*/, winNum, &sdmmcWin)) -+ { -+ return MV_ERROR; -+ } -+ winNum++; -+ } -+ winPrioIndex++; -+ } -+ return MV_OK; -+} -+ -+ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h 2010-11-09 20:28:08.891243103 +0100 -@@ -0,0 +1,125 @@ -+ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#ifndef __INCMVSysSdmmcAddrDech -+#define __INCMVSysSdmmcAddrDech -+ -+#include "mvCommon.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+ -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+typedef struct _mvSdmmcDecWin -+{ -+ MV_TARGET target; -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+} MV_SDMMC_DEC_WIN; -+ -+ -+#define MV_SDMMC_MAX_ADDR_DECODE_WIN 4 -+ -+#define MV_SDMMC_WIN_CTRL_REG(dev, win) (MV_SDIO_REG_BASE + 0x108 + ((win)<<3)) -+#define MV_SDMMC_WIN_BASE_REG(dev, win) (MV_SDIO_REG_BASE + 0x10c + ((win)<<3)) -+ -+ -+/* BITs in Windows 0-3 Control and Base Registers */ -+#define MV_SDMMC_WIN_ENABLE_BIT 0 -+#define MV_SDMMC_WIN_ENABLE_MASK (1<= TDM_MBUS_MAX_WIN) -+ { -+ mvOsPrintf("mvTdmWinSet: ERR. Invalid win num %d\n",winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlapps with current windows */ -+ if (MV_TRUE == tdmWinOverlapDetect(winNum, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("mvTdmWinSet: ERR. Window %d overlap\n", winNum); -+ return MV_ERROR; -+ } -+ -+ /* check if address is aligned to the size */ -+ if (MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvTdmWinSet: Error setting TDM window %d to "\ -+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, -+ mvCtrlTargetNameGet(pAddrDecWin->target), -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ decRegs.baseReg = MV_REG_READ(TDM_WIN_BASE_REG(winNum)); -+ decRegs.sizeReg = (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_SIZE_MASK) >> TDM_WIN_SIZE_OFFS; -+ -+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) -+ { -+ mvOsPrintf("mvTdmWinSet: mvCtrlAddrDecToReg Failed\n"); -+ return MV_ERROR; -+ } -+ -+ mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); -+ -+ /* for the safe side we disable the window before writing the new -+ values */ -+ mvTdmWinEnable(winNum, MV_FALSE); -+ -+ ctrlReg |= (targetAttribs.attrib << TDM_WIN_ATTRIB_OFFS); -+ ctrlReg |= (targetAttribs.targetId << TDM_WIN_TARGET_OFFS); -+ ctrlReg |= (decRegs.sizeReg & TDM_WIN_SIZE_MASK); -+ -+ /* Write to address base and control registers */ -+ MV_REG_WRITE(TDM_WIN_BASE_REG(winNum), decRegs.baseReg); -+ MV_REG_WRITE(TDM_WIN_CTRL_REG(winNum), ctrlReg); -+ /* Enable address decode target window */ -+ if (pAddrDecWin->enable == MV_TRUE) -+ { -+ mvTdmWinEnable(winNum, MV_TRUE); -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvTdmWinGet - Get peripheral target address window. -+* -+* DESCRIPTION: -+* Get TDM peripheral target address window. -+* -+* INPUT: -+* winNum - TDM to target address decode window number. -+* -+* OUTPUT: -+* pAddrDecWin - TDM target window data structure. -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+ -+MV_STATUS mvTdmWinGet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin) -+{ -+ -+ MV_DEC_REGS decRegs; -+ MV_TARGET_ATTRIB targetAttrib; -+ -+ /* Parameter checking */ -+ if (winNum >= TDM_MBUS_MAX_WIN) -+ { -+ mvOsPrintf("mvTdmWinGet: ERR. Invalid winNum %d\n", winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ decRegs.baseReg = MV_REG_READ(TDM_WIN_BASE_REG(winNum)); -+ decRegs.sizeReg = (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_SIZE_MASK) >> TDM_WIN_SIZE_OFFS; -+ -+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) -+ { -+ mvOsPrintf("mvTdmWinGet: mvCtrlRegToAddrDec Failed \n"); -+ return MV_ERROR; -+ } -+ -+ /* attrib and targetId */ -+ targetAttrib.attrib = -+ (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ATTRIB_MASK) >> TDM_WIN_ATTRIB_OFFS; -+ targetAttrib.targetId = -+ (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_TARGET_MASK) >> TDM_WIN_TARGET_OFFS; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ /* Check if window is enabled */ -+ if (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ENABLE_MASK) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvTdmWinEnable - Enable/disable a TDM to target address window -+* -+* DESCRIPTION: -+* This function enable/disable a TDM to target address window. -+* According to parameter 'enable' the routine will enable the -+* window, thus enabling TDM accesses (before enabling the window it is -+* tested for overlapping). Otherwise, the window will be disabled. -+* -+* INPUT: -+* winNum - TDM to target address decode window number. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_ERROR if decode window number was wrong or enabled window overlapps. -+* -+*******************************************************************************/ -+MV_STATUS mvTdmWinEnable(int winNum, MV_BOOL enable) -+{ -+ MV_TDM_DEC_WIN addrDecWin; -+ -+ if (MV_TRUE == enable) -+ { -+ if (winNum >= TDM_MBUS_MAX_WIN) -+ { -+ mvOsPrintf("mvTdmWinEnable:ERR. Invalid winNum%d\n",winNum); -+ return MV_ERROR; -+ } -+ -+ /* First check for overlap with other enabled windows */ -+ /* Get current window */ -+ if (MV_OK != mvTdmWinGet(winNum, &addrDecWin)) -+ { -+ mvOsPrintf("mvTdmWinEnable:ERR. targetWinGet fail\n"); -+ return MV_ERROR; -+ } -+ /* Check for overlapping */ -+ if (MV_FALSE == tdmWinOverlapDetect(winNum, &(addrDecWin.addrWin))) -+ { -+ /* No Overlap. Enable address decode target window */ -+ MV_REG_BIT_SET(TDM_WIN_CTRL_REG(winNum), TDM_WIN_ENABLE_MASK); -+ } -+ else -+ { /* Overlap detected */ -+ mvOsPrintf("mvTdmWinEnable:ERR. Overlap detected\n"); -+ return MV_ERROR; -+ } -+ } -+ else -+ { -+ MV_REG_BIT_RESET(TDM_WIN_CTRL_REG(winNum), TDM_WIN_ENABLE_MASK); -+ } -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* tdmWinOverlapDetect - Detect TDM address windows overlapping -+* -+* DESCRIPTION: -+* An unpredicted behaviour is expected in case TDM address decode -+* windows overlapps. -+* This function detects TDM address decode windows overlapping of a -+* specified window. The function does not check the window itself for -+* overlapping. The function also skipps disabled address decode windows. -+* -+* INPUT: -+* winNum - address decode window number. -+* pAddrDecWin - An address decode window struct. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data -+* from registers. -+* -+*******************************************************************************/ -+static MV_STATUS tdmWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 winNumIndex; -+ MV_TDM_DEC_WIN addrDecWin; -+ -+ for (winNumIndex = 0; winNumIndex < TDM_MBUS_MAX_WIN; winNumIndex++) -+ { -+ /* Do not check window itself */ -+ if (winNumIndex == winNum) -+ { -+ continue; -+ } -+ /* Do not check disabled windows */ -+ if (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ENABLE_MASK) -+ { -+ /* Get window parameters */ -+ if (MV_OK != mvTdmWinGet(winNumIndex, &addrDecWin)) -+ { -+ DB(mvOsPrintf("dmaWinOverlapDetect: ERR. TargetWinGet failed\n")); -+ return MV_ERROR; -+ } -+ -+ if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin))) -+ { -+ return MV_TRUE; -+ } -+ } -+ } -+ return MV_FALSE; -+} -+ -+/******************************************************************************* -+* mvTdmAddrDecShow - Print the TDM address decode map. -+* -+* DESCRIPTION: -+* This function print the TDM address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvTdmAddrDecShow(MV_VOID) -+{ -+ MV_TDM_DEC_WIN win; -+ int i; -+ -+ mvOsOutput( "\n" ); -+ mvOsOutput( "TDM:\n" ); -+ mvOsOutput( "----\n" ); -+ -+ for( i = 0; i < TDM_MBUS_MAX_WIN; i++ ) -+ { -+ memset( &win, 0, sizeof(MV_TDM_DEC_WIN) ); -+ -+ mvOsOutput( "win%d - ", i ); -+ -+ if (mvTdmWinGet(i, &win ) == MV_OK ) -+ { -+ if( win.enable ) -+ { -+ mvOsOutput( "%s base %08x, ", -+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow); -+ mvOsOutput( "...." ); -+ mvSizePrint( win.addrWin.size ); -+ mvOsOutput( "\n" ); -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ } -+ } -+} -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.h 2010-11-09 20:28:09.471497270 +0100 -@@ -0,0 +1,106 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvSysTdmh -+#define __INCmvSysTdmh -+ -+#include "ctrlEnv/sys/mvCpuIf.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+ -+typedef struct _mvTdmDecWin -+{ -+ MV_TARGET target; -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+} MV_TDM_DEC_WIN; -+ -+MV_STATUS mvTdmWinInit(MV_VOID); -+MV_STATUS mvTdmWinSet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin); -+MV_STATUS mvTdmWinGet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin); -+MV_STATUS mvTdmWinEnable(int winNum, MV_BOOL enable); -+MV_VOID mvTdmAddrDecShow(MV_VOID); -+ -+ -+#define TDM_MBUS_MAX_WIN 4 -+#define TDM_WIN_CTRL_REG(win) ((TDM_REG_BASE + 0x4030) + (win<<4)) -+#define TDM_WIN_BASE_REG(win) ((TDM_REG_BASE +0x4034) + (win<<4)) -+ -+/* TDM_WIN_CTRL_REG bits */ -+#define TDM_WIN_ENABLE_OFFS 0 -+#define TDM_WIN_ENABLE_MASK (1<= TSU_MAX_DECODE_WIN) -+ { -+ mvOsPrintf("mvTsuWinSet: ERR. Invalid win num %d\n",winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlapps with current windows */ -+ if(MV_TRUE == tsuWinOverlapDetect(winNum, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("mvTsuWinSet: ERR. Window %d overlap\n", winNum); -+ return MV_ERROR; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow,pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvTsuWinSet: Error setting TSU window %d to target " -+ "%s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, mvCtrlTargetNameGet(pAddrDecWin->target), -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ decRegs.baseReg = MV_REG_READ(MV_TSU_WIN_BASE_REG(winNum)); -+ decRegs.sizeReg = MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNum)); -+ -+ if(MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) -+ { -+ mvOsPrintf("mvTsuWinSet: mvCtrlAddrDecToReg Failed\n"); -+ return MV_ERROR; -+ } -+ -+ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); -+ -+ /* set attributes */ -+ decRegs.sizeReg &= ~TSU_WIN_CTRL_ATTR_MASK; -+ decRegs.sizeReg |= targetAttribs.attrib << TSU_WIN_CTRL_ATTR_OFFS; -+ /* set target ID */ -+ decRegs.sizeReg &= ~TSU_WIN_CTRL_TARGET_MASK; -+ decRegs.sizeReg |= targetAttribs.targetId << TSU_WIN_CTRL_TARGET_OFFS; -+ -+ /* for the safe side we disable the window before writing the new */ -+ /* values */ -+ mvTsuWinEnable(winNum, MV_FALSE); -+ MV_REG_WRITE(MV_TSU_WIN_CTRL_REG(winNum),decRegs.sizeReg); -+ -+ /* Write to address decode Size Register */ -+ MV_REG_WRITE(MV_TSU_WIN_BASE_REG(winNum), decRegs.baseReg); -+ -+ /* Enable address decode target window */ -+ if(pAddrDecWin->enable == MV_TRUE) -+ { -+ mvTsuWinEnable(winNum,MV_TRUE); -+ } -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvTsuWinGet -+* -+* DESCRIPTION: -+* Get TSU peripheral target address window. -+* -+* INPUT: -+* winNum - TSU to target address decode window number. -+* -+* OUTPUT: -+* pAddrDecWin - TSU target window data structure. -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvTsuWinGet(MV_U32 winNum, MV_TSU_DEC_WIN *pAddrDecWin) -+{ -+ MV_DEC_REGS decRegs; -+ MV_TARGET_ATTRIB targetAttrib; -+ -+ /* Parameter checking */ -+ if(winNum >= TSU_MAX_DECODE_WIN) -+ { -+ mvOsPrintf("mvTsuWinGet: ERR. Invalid winNum %d\n", winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ decRegs.baseReg = MV_REG_READ(MV_TSU_WIN_BASE_REG(winNum)); -+ decRegs.sizeReg = MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNum)); -+ -+ if(MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) -+ { -+ mvOsPrintf("mvTsuWinGet: mvCtrlRegToAddrDec Failed \n"); -+ return MV_ERROR; -+ } -+ -+ /* attrib and targetId */ -+ targetAttrib.attrib = -+ (decRegs.sizeReg & TSU_WIN_CTRL_ATTR_MASK) >> TSU_WIN_CTRL_ATTR_OFFS; -+ targetAttrib.targetId = -+ (decRegs.sizeReg & TSU_WIN_CTRL_TARGET_MASK) >> TSU_WIN_CTRL_TARGET_OFFS; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ /* Check if window is enabled */ -+ if((MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNum)) & TSU_WIN_CTRL_EN_MASK)) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ } -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvTsuWinEnable -+* -+* DESCRIPTION: -+* This function enable/disable a TSU to target address window. -+* According to parameter 'enable' the routine will enable the -+* window, thus enabling TSU accesses (before enabling the window it is -+* tested for overlapping). Otherwise, the window will be disabled. -+* -+* INPUT: -+* winNum - TSU to target address decode window number. -+* enable - Enable / disable parameter. -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_ERROR if decode window number was wrong or enabled window overlapps. -+* -+*******************************************************************************/ -+MV_STATUS mvTsuWinEnable(MV_U32 winNum,MV_BOOL enable) -+{ -+ MV_TSU_DEC_WIN addrDecWin; -+ -+ /* Parameter checking */ -+ if(winNum >= TSU_MAX_DECODE_WIN) -+ { -+ mvOsPrintf("mvTsuWinEnable: ERR. Invalid winNum%d\n",winNum); -+ return MV_ERROR; -+ } -+ -+ if(enable == MV_TRUE) -+ { -+ /* First check for overlap with other enabled windows */ -+ /* Get current window. */ -+ if(MV_OK != mvTsuWinGet(winNum,&addrDecWin)) -+ { -+ mvOsPrintf("mvTsuWinEnable: ERR. targetWinGet fail\n"); -+ return MV_ERROR; -+ } -+ /* Check for overlapping. */ -+ if(MV_FALSE == tsuWinOverlapDetect(winNum,&(addrDecWin.addrWin))) -+ { -+ /* No Overlap. Enable address decode target window */ -+ MV_REG_BIT_SET(MV_TSU_WIN_CTRL_REG(winNum), -+ TSU_WIN_CTRL_EN_MASK); -+ } -+ else -+ { -+ /* Overlap detected */ -+ mvOsPrintf("mvTsuWinEnable: ERR. Overlap detected\n"); -+ return MV_ERROR; -+ } -+ } -+ else -+ { -+ /* Disable address decode target window */ -+ MV_REG_BIT_RESET(MV_TSU_WIN_CTRL_REG(winNum), -+ TSU_WIN_CTRL_EN_MASK); -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvTsuWinTargetGet -+* -+* DESCRIPTION: -+* Get Window number associated with target -+* -+* INPUT: -+* target - Target ID to get the window number for. -+* OUTPUT: -+* -+* RETURN: -+* window number or 0xFFFFFFFF on error. -+* -+*******************************************************************************/ -+MV_U32 mvTsuWinTargetGet(MV_TARGET target) -+{ -+ MV_TSU_DEC_WIN decWin; -+ MV_U32 winNum; -+ -+ /* Check parameters */ -+ if(target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvTsuWinTargetGet: target %d is Illigal\n", target); -+ return 0xffffffff; -+ } -+ -+ for(winNum = 0; winNum < TSU_MAX_DECODE_WIN; winNum++) -+ { -+ if(mvTsuWinGet(winNum,&decWin) != MV_OK) -+ { -+ mvOsPrintf("mvTsuWinGet: window returned error\n"); -+ return 0xffffffff; -+ } -+ -+ if (decWin.enable == MV_TRUE) -+ { -+ if(decWin.target == target) -+ { -+ return winNum; -+ } -+ } -+ } -+ return 0xFFFFFFFF; -+} -+ -+ -+/******************************************************************************* -+* tsuWinOverlapDetect -+* -+* DESCRIPTION: -+* Detect TSU address windows overlapping -+* An unpredicted behaviur is expected in case TSU address decode -+* windows overlapps. -+* This function detects TSU address decode windows overlapping of a -+* specified window. The function does not check the window itself for -+* overlapping. The function also skipps disabled address decode windows. -+* -+* INPUT: -+* winNum - address decode window number. -+* pAddrDecWin - An address decode window struct. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data -+* from registers. -+* -+*******************************************************************************/ -+static MV_STATUS tsuWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 ctrlReg; -+ MV_U32 winNumIndex; -+ MV_TSU_DEC_WIN addrDecWin; -+ -+ for(winNumIndex = 0; winNumIndex < TSU_MAX_DECODE_WIN; winNumIndex++) -+ { -+ /* Do not check window itself */ -+ if(winNumIndex == winNum) -+ { -+ continue; -+ } -+ -+ /* Do not check disabled windows */ -+ ctrlReg = MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNumIndex)); -+ if((ctrlReg & TSU_WIN_CTRL_EN_MASK) == 0) -+ { -+ continue; -+ } -+ -+ /* Get window parameters */ -+ if (MV_OK != mvTsuWinGet(winNumIndex, &addrDecWin)) -+ { -+ mvOsPrintf("tsuWinOverlapDetect: ERR. mvTsuWinGet failed\n"); -+ return MV_ERROR; -+ } -+ -+ if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin))) -+ { -+ return MV_TRUE; -+ } -+ } -+ return MV_FALSE; -+} -+ -+ -+/******************************************************************************* -+* mvTsuAddrDecShow -+* -+* DESCRIPTION: -+* Print the TSU address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+void mvTsuAddrDecShow(void) -+{ -+ MV_TSU_DEC_WIN win; -+ int i; -+ -+ if (MV_FALSE == mvCtrlPwrClckGet(TS_UNIT_ID, 0)) -+ return; -+ -+ mvOsOutput( "\n" ); -+ mvOsOutput( "TSU:\n"); -+ mvOsOutput( "----\n" ); -+ -+ for(i = 0; i < TSU_MAX_DECODE_WIN; i++) -+ { -+ memset(&win, 0, sizeof(TSU_MAX_DECODE_WIN)); -+ mvOsOutput( "win%d - ", i ); -+ -+ if(mvTsuWinGet(i, &win ) == MV_OK ) -+ { -+ if(win.enable == MV_TRUE) -+ { -+ mvOsOutput("%s base %08x, ", -+ mvCtrlTargetNameGet(win.target), -+ win.addrWin.baseLow); -+ mvOsOutput( "...." ); -+ mvSizePrint(win.addrWin.size ); -+ mvOsOutput( "\n" ); -+ } -+ else -+ { -+ mvOsOutput( "disable\n" ); -+ } -+ } -+ } -+ return; -+} -+ -+ -+/******************************************************************************* -+* mvTsuInit -+* -+* DESCRIPTION: -+* Initialize the TSU unit, and get unit out of reset. -+* -+* INPUT: -+* coreClock - The core clock at which the TSU should operate. -+* mode - The mode on configure the unit into (serial/parallel). -+* memHandle - Memory handle used for memory allocations. -+* OUTPUT: -+* None. -+* RETURN: -+* MV_OK - on success, -+* -+*******************************************************************************/ -+MV_STATUS mvTsuInit(MV_TSU_CORE_CLOCK coreClock, MV_TSU_PORTS_MODE mode, -+ void *osHandle) -+{ -+ MV_STATUS status; -+ -+ status = mvTsuWinInit(); -+ if(status == MV_OK) -+ status = mvTsuHalInit(coreClock,mode,osHandle); -+ -+ return status; -+} -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h 2010-11-09 20:28:09.894776606 +0100 -@@ -0,0 +1,110 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvSysTsh -+#define __INCmvSysTsh -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* includes */ -+#include "ts/mvTsu.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+ -+#define TSU_MAX_DECODE_WIN 4 -+ -+ -+/*******************************************/ -+/* TSU Windows Registers */ -+/*******************************************/ -+#define MV_TSU_WIN_CTRL_REG(win) (TSU_GLOBAL_REG_BASE +0x30 + 0x10 * win) -+#define MV_TSU_WIN_BASE_REG(win) (TSU_GLOBAL_REG_BASE +0x34 + 0x10 * win) -+ -+/* TSU windows control register. */ -+#define TSU_WIN_CTRL_EN_MASK (0x1 << 0) -+#define TSU_WIN_CTRL_TARGET_OFFS 4 -+#define TSU_WIN_CTRL_TARGET_MASK (0xF << TSU_WIN_CTRL_TARGET_OFFS) -+#define TSU_WIN_CTRL_ATTR_OFFS 8 -+#define TSU_WIN_CTRL_ATTR_MASK (0xFF << TSU_WIN_CTRL_ATTR_OFFS) -+#define TSU_WIN_CTRL_SIZE_OFFS 16 -+#define TSU_WIN_CTRL_SIZE_MASK (0xFFFF << TSU_WIN_CTRL_SIZE_OFFS) -+ -+/* TSU windows base register. */ -+#define TSU_WIN_BASE_OFFS 16 -+#define TSU_WIN_BASE_MASK (0xFFFF << TSU_WIN_BASE_OFFS) -+ -+MV_STATUS mvTsuWinInit(void); -+ -+void mvTsuAddrDecShow(void); -+MV_STATUS mvTsuInit(MV_TSU_CORE_CLOCK coreClock, MV_TSU_PORTS_MODE mode, -+ void *osHandle); -+ -+#ifdef __cplusplus -+} -+#endif /* __cplusplus */ -+ -+#endif /* __INCmvTsh */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.c 2010-11-09 20:28:09.932495382 +0100 -@@ -0,0 +1,497 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "ctrlEnv/sys/mvSysUsb.h" -+ -+MV_TARGET usbAddrDecPrioTab[] = -+{ -+#if defined(MV_INCLUDE_SDRAM_CS0) -+ SDRAM_CS0, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS1) -+ SDRAM_CS1, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS2) -+ SDRAM_CS2, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS3) -+ SDRAM_CS3, -+#endif -+#if defined(MV_INCLUDE_CESA) && defined(USB_UNDERRUN_WA) -+ CRYPT_ENG, -+#endif -+#if defined(MV_INCLUDE_PEX) -+ PEX0_MEM, -+#endif -+ TBL_TERM -+}; -+ -+ -+ -+MV_STATUS mvUsbInit(int dev, MV_BOOL isHost) -+{ -+ MV_STATUS status; -+ -+ status = mvUsbWinInit(dev); -+ if(status != MV_OK) -+ return status; -+ -+ return mvUsbHalInit(dev, isHost); -+} -+ -+ -+/******************************************************************************* -+* usbWinOverlapDetect - Detect USB address windows overlapping -+* -+* DESCRIPTION: -+* An unpredicted behaviur is expected in case USB address decode -+* windows overlapps. -+* This function detects USB address decode windows overlapping of a -+* specified window. The function does not check the window itself for -+* overlapping. The function also skipps disabled address decode windows. -+* -+* INPUT: -+* winNum - address decode window number. -+* pAddrDecWin - An address decode window struct. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data -+* from registers. -+* -+*******************************************************************************/ -+static MV_STATUS usbWinOverlapDetect(int dev, MV_U32 winNum, -+ MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 winNumIndex; -+ MV_DEC_WIN addrDecWin; -+ -+ for(winNumIndex=0; winNumIndex= MV_USB_MAX_ADDR_DECODE_WIN) -+ { -+ mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlapps with current windows */ -+ if (MV_TRUE == usbWinOverlapDetect(dev, winNum, &pDecWin->addrWin)) -+ { -+ mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); -+ return MV_ERROR; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pDecWin->addrWin.baseLow, pDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvUsbWinSet:Error setting USB window %d to "\ -+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, -+ mvCtrlTargetNameGet(pDecWin->target), -+ pDecWin->addrWin.baseLow, -+ pDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ if(MV_OK != mvCtrlAddrDecToParams(pDecWin, &winParams)) -+ { -+ mvOsPrintf("%s: mvCtrlAddrDecToParams Failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ /* set Size, Attributes and TargetID */ -+ sizeReg = (((winParams.targetId << MV_USB_WIN_TARGET_OFFSET) & MV_USB_WIN_TARGET_MASK) | -+ ((winParams.attrib << MV_USB_WIN_ATTR_OFFSET) & MV_USB_WIN_ATTR_MASK) | -+ ((winParams.size << MV_USB_WIN_SIZE_OFFSET) & MV_USB_WIN_SIZE_MASK)); -+ -+#if defined(MV645xx) || defined(MV646xx) -+ /* If window is DRAM with HW cache coherency, make sure bit2 is set */ -+ sizeReg &= ~MV_USB_WIN_BURST_WR_LIMIT_MASK; -+ -+ if((MV_TARGET_IS_DRAM(pDecWin->target)) && -+ (pDecWin->addrWinAttr.cachePolicy != NO_COHERENCY)) -+ { -+ sizeReg |= MV_USB_WIN_BURST_WR_32BIT_LIMIT; -+ } -+ else -+ { -+ sizeReg |= MV_USB_WIN_BURST_WR_NO_LIMIT; -+ } -+#endif /* MV645xx || MV646xx */ -+ -+ if (pDecWin->enable == MV_TRUE) -+ { -+ sizeReg |= MV_USB_WIN_ENABLE_MASK; -+ } -+ else -+ { -+ sizeReg &= ~MV_USB_WIN_ENABLE_MASK; -+ } -+ -+ /* Update Base value */ -+ baseReg = (winParams.baseAddr & MV_USB_WIN_BASE_MASK); -+ -+ MV_REG_WRITE( MV_USB_WIN_CTRL_REG(dev, winNum), sizeReg); -+ MV_REG_WRITE( MV_USB_WIN_BASE_REG(dev, winNum), baseReg); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvUsbWinGet - Get USB peripheral target address window. -+* -+* DESCRIPTION: -+* Get USB peripheral target address window. -+* -+* INPUT: -+* winNum - USB target address decode window number. -+* -+* OUTPUT: -+* pDecWin - USB target window data structure. -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvUsbWinGet(int dev, MV_U32 winNum, MV_DEC_WIN *pDecWin) -+{ -+ MV_DEC_WIN_PARAMS winParam; -+ MV_U32 sizeReg, baseReg; -+ -+ /* Parameter checking */ -+ if (winNum >= MV_USB_MAX_ADDR_DECODE_WIN) -+ { -+ mvOsPrintf("%s (dev=%d): ERR. Invalid winNum %d\n", -+ __FUNCTION__, dev, winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ baseReg = MV_REG_READ( MV_USB_WIN_BASE_REG(dev, winNum) ); -+ sizeReg = MV_REG_READ( MV_USB_WIN_CTRL_REG(dev, winNum) ); -+ -+ /* Check if window is enabled */ -+ if(sizeReg & MV_USB_WIN_ENABLE_MASK) -+ { -+ pDecWin->enable = MV_TRUE; -+ -+ /* Extract window parameters from registers */ -+ winParam.targetId = (sizeReg & MV_USB_WIN_TARGET_MASK) >> MV_USB_WIN_TARGET_OFFSET; -+ winParam.attrib = (sizeReg & MV_USB_WIN_ATTR_MASK) >> MV_USB_WIN_ATTR_OFFSET; -+ winParam.size = (sizeReg & MV_USB_WIN_SIZE_MASK) >> MV_USB_WIN_SIZE_OFFSET; -+ winParam.baseAddr = (baseReg & MV_USB_WIN_BASE_MASK); -+ -+ /* Translate the decode window parameters to address decode struct */ -+ if (MV_OK != mvCtrlParamsToAddrDec(&winParam, pDecWin)) -+ { -+ mvOsPrintf("Failed to translate register parameters to USB address" \ -+ " decode window structure\n"); -+ return MV_ERROR; -+ } -+ } -+ else -+ { -+ pDecWin->enable = MV_FALSE; -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvUsbWinInit - -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvUsbWinInit(int dev) -+{ -+ MV_STATUS status; -+ MV_DEC_WIN usbWin; -+ MV_CPU_DEC_WIN cpuAddrDecWin; -+ int winNum; -+ MV_U32 winPrioIndex = 0; -+ -+ /* First disable all address decode windows */ -+ for(winNum = 0; winNum < MV_USB_MAX_ADDR_DECODE_WIN; winNum++) -+ { -+ MV_REG_BIT_RESET(MV_USB_WIN_CTRL_REG(dev, winNum), MV_USB_WIN_ENABLE_MASK); -+ } -+ -+ /* Go through all windows in user table until table terminator */ -+ winNum = 0; -+ while( (usbAddrDecPrioTab[winPrioIndex] != TBL_TERM) && -+ (winNum < MV_USB_MAX_ADDR_DECODE_WIN) ) -+ { -+ /* first get attributes from CPU If */ -+ status = mvCpuIfTargetWinGet(usbAddrDecPrioTab[winPrioIndex], -+ &cpuAddrDecWin); -+ -+ if(MV_NO_SUCH == status) -+ { -+ winPrioIndex++; -+ continue; -+ } -+ if (MV_OK != status) -+ { -+ mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ if (cpuAddrDecWin.enable == MV_TRUE) -+ { -+ usbWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; -+ usbWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; -+ usbWin.addrWin.size = cpuAddrDecWin.addrWin.size; -+ usbWin.enable = MV_TRUE; -+ usbWin.target = usbAddrDecPrioTab[winPrioIndex]; -+ -+#if defined(MV645xx) || defined(MV646xx) -+ /* Get the default attributes for that target window */ -+ mvCtrlDefAttribGet(usbWin.target, &usbWin.addrWinAttr); -+#endif /* MV645xx || MV646xx */ -+ -+ if(MV_OK != mvUsbWinSet(dev, winNum, &usbWin)) -+ { -+ return MV_ERROR; -+ } -+ winNum++; -+ } -+ winPrioIndex++; -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvUsbAddrDecShow - Print the USB address decode map. -+* -+* DESCRIPTION: -+* This function print the USB address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvUsbAddrDecShow(MV_VOID) -+{ -+ MV_DEC_WIN addrDecWin; -+ int i, winNum; -+ -+ mvOsOutput( "\n" ); -+ mvOsOutput( "USB:\n" ); -+ mvOsOutput( "----\n" ); -+ -+ for(i=0; i= XOR_MAX_ADDR_DEC_WIN) -+ { -+ DB(mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum)); -+ return MV_BAD_PARAM; -+ } -+ if (pAddrDecWin == NULL) -+ { -+ DB(mvOsPrintf("%s: ERR. pAddrDecWin is NULL pointer\n", __FUNCTION__ )); -+ return MV_BAD_PTR; -+ } -+ /* Check if the requested window overlaps with current windows */ -+ if (MV_TRUE == xorWinOverlapDetect(unit, winNum, &pAddrDecWin->addrWin)) -+ { -+ DB(mvOsPrintf("%s: ERR. Window %d overlap\n",__FUNCTION__,winNum)); -+ return MV_ERROR; -+ } -+ -+ xorDecRegs.baseReg = MV_REG_READ(XOR_BASE_ADDR_REG(unit,winNum)); -+ xorDecRegs.sizeReg = MV_REG_READ(XOR_SIZE_MASK_REG(unit,winNum)); -+ -+ /* Get Base Address and size registers values */ -+ if(MV_OK != mvCtrlAddrDecToReg(&pAddrDecWin->addrWin, &xorDecRegs)) -+ { -+ DB(mvOsPrintf("%s: ERR. Invalid addr dec window\n",__FUNCTION__)); -+ return MV_BAD_PARAM; -+ } -+ -+ -+ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); -+ -+ /* set attributes */ -+ xorDecRegs.baseReg &= ~XEBARX_ATTR_MASK; -+ xorDecRegs.baseReg |= targetAttribs.attrib << XEBARX_ATTR_OFFS; -+ /* set target ID */ -+ xorDecRegs.baseReg &= ~XEBARX_TARGET_MASK; -+ xorDecRegs.baseReg |= targetAttribs.targetId << XEBARX_TARGET_OFFS; -+ -+ -+ /* Write to address decode Base Address Register */ -+ MV_REG_WRITE(XOR_BASE_ADDR_REG(unit,winNum), xorDecRegs.baseReg); -+ -+ /* Write to Size Register */ -+ MV_REG_WRITE(XOR_SIZE_MASK_REG(unit,winNum), xorDecRegs.sizeReg); -+ -+ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) -+ { -+ if (pAddrDecWin->enable) -+ { -+ MV_REG_BIT_SET(XOR_WINDOW_CTRL_REG(unit,chan), -+ XEXWCR_WIN_EN_MASK(winNum)); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(XOR_WINDOW_CTRL_REG(unit,chan), -+ XEXWCR_WIN_EN_MASK(winNum)); -+ } -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvXorTargetWinGet - Get xor peripheral target address window. -+* -+* DESCRIPTION: -+* Get xor peripheral target address window. -+* -+* INPUT: -+* winNum - One of the possible XOR memory decode windows. -+* -+* OUTPUT: -+* base - Window base address. -+* size - Window size. -+* enable - window enable/disable. -+* -+* RETURN: -+* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_STATUS mvXorTargetWinGet(MV_U32 unit,MV_U32 winNum, MV_XOR_DEC_WIN *pAddrDecWin) -+{ -+ MV_DEC_REGS xorDecRegs; -+ MV_TARGET_ATTRIB targetAttrib; -+ MV_U32 chan=0,chanWinEn; -+ -+ /* Parameter checking */ -+ if (winNum >= XOR_MAX_ADDR_DEC_WIN) -+ { -+ DB(mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__ , winNum)); -+ return MV_ERROR; -+ } -+ -+ if (NULL == pAddrDecWin) -+ { -+ DB(mvOsPrintf("%s: ERR. pAddrDecWin is NULL pointer\n", __FUNCTION__ )); -+ return MV_BAD_PTR; -+ } -+ -+ chanWinEn = MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,0)) & XEXWCR_WIN_EN_MASK(winNum); -+ -+ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) /* we should scan here all channels per unit */ -+ { -+ /* Check if enable bit is equal for all channels */ -+ if ((MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,chan)) & -+ XEXWCR_WIN_EN_MASK(winNum)) != chanWinEn) -+ { -+ mvOsPrintf("%s: ERR. Window enable field must be equal in " -+ "all channels(chan=%d)\n",__FUNCTION__, chan); -+ return MV_ERROR; -+ } -+ } -+ -+ -+ -+ xorDecRegs.baseReg = MV_REG_READ(XOR_BASE_ADDR_REG(unit,winNum)); -+ xorDecRegs.sizeReg = MV_REG_READ(XOR_SIZE_MASK_REG(unit,winNum)); -+ -+ if (MV_OK != mvCtrlRegToAddrDec(&xorDecRegs, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("%s: ERR. mvCtrlRegToAddrDec failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ /* attrib and targetId */ -+ targetAttrib.attrib = -+ (xorDecRegs.baseReg & XEBARX_ATTR_MASK) >> XEBARX_ATTR_OFFS; -+ targetAttrib.targetId = -+ (xorDecRegs.baseReg & XEBARX_TARGET_MASK) >> XEBARX_TARGET_OFFS; -+ -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ if(chanWinEn) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else pAddrDecWin->enable = MV_FALSE; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvXorTargetWinEnable - Enable/disable a Xor address decode window -+* -+* DESCRIPTION: -+* This function enable/disable a XOR address decode window. -+* if parameter 'enable' == MV_TRUE the routine will enable the -+* window, thus enabling XOR accesses (before enabling the window it is -+* tested for overlapping). Otherwise, the window will be disabled. -+* -+* INPUT: -+* winNum - Decode window number. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_STATUS mvXorTargetWinEnable(MV_U32 unit,MV_U32 winNum, MV_BOOL enable) -+{ -+ MV_XOR_DEC_WIN addrDecWin; -+ MV_U32 chan; -+ -+ /* Parameter checking */ -+ if (winNum >= XOR_MAX_ADDR_DEC_WIN) -+ { -+ DB(mvOsPrintf("%s: ERR. Invalid winNum%d\n", __FUNCTION__, winNum)); -+ return MV_ERROR; -+ } -+ -+ if (enable == MV_TRUE) -+ { -+ /* Get current window */ -+ if (MV_OK != mvXorTargetWinGet(unit,winNum, &addrDecWin)) -+ { -+ DB(mvOsPrintf("%s: ERR. targetWinGet fail\n", __FUNCTION__)); -+ return MV_ERROR; -+ } -+ -+ /* Check for overlapping */ -+ if (MV_TRUE == xorWinOverlapDetect(unit,winNum, &(addrDecWin.addrWin))) -+ { -+ /* Overlap detected */ -+ DB(mvOsPrintf("%s: ERR. Overlap detected\n", __FUNCTION__)); -+ return MV_ERROR; -+ } -+ -+ /* No Overlap. Enable address decode target window */ -+ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) -+ { -+ MV_REG_BIT_SET(XOR_WINDOW_CTRL_REG(unit,chan), -+ XEXWCR_WIN_EN_MASK(winNum)); -+ } -+ -+ } -+ else -+ { -+ /* Disable address decode target window */ -+ -+ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) -+ { -+ MV_REG_BIT_RESET(XOR_WINDOW_CTRL_REG(unit,chan), -+ XEXWCR_WIN_EN_MASK(winNum)); -+ } -+ -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvXorSetProtWinSet - Configure access attributes of a XOR engine -+* to one of the XOR memory windows. -+* -+* DESCRIPTION: -+* Each engine can be configured with access attributes for each of the -+* memory spaces. This function sets access attributes -+* to a given window for the given engine -+* -+* INPUTS: -+* chan - One of the possible engines. -+* winNum - One of the possible XOR memory spaces. -+* access - Protection access rights. -+* write - Write rights. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_STATUS mvXorProtWinSet (MV_U32 unit,MV_U32 chan, MV_U32 winNum, MV_BOOL access, -+ MV_BOOL write) -+{ -+ MV_U32 temp; -+ -+ /* Parameter checking */ -+ if (chan >= MV_XOR_MAX_CHAN_PER_UNIT) -+ { -+ DB(mvOsPrintf("%s: ERR. Invalid chan num %d\n", __FUNCTION__ , chan)); -+ return MV_BAD_PARAM; -+ } -+ if (winNum >= XOR_MAX_ADDR_DEC_WIN) -+ { -+ DB(mvOsPrintf("%s: ERR. Invalid win num %d\n", __FUNCTION__, winNum)); -+ return MV_BAD_PARAM; -+ } -+ -+ temp = MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,chan)) & -+ (~XEXWCR_WIN_ACC_MASK(winNum)); -+ -+ /* if access is disable */ -+ if (!access) -+ { -+ /* disable access */ -+ temp |= XEXWCR_WIN_ACC_NO_ACC(winNum); -+ } -+ /* if access is enable */ -+ else -+ { -+ /* if write is enable */ -+ if (write) -+ { -+ /* enable write */ -+ temp |= XEXWCR_WIN_ACC_RW(winNum); -+ } -+ /* if write is disable */ -+ else -+ { -+ /* disable write */ -+ temp |= XEXWCR_WIN_ACC_RO(winNum); -+ } -+ } -+ MV_REG_WRITE(XOR_WINDOW_CTRL_REG(unit,chan),temp); -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvXorPciRemap - Set XOR remap register for PCI address windows. -+* -+* DESCRIPTION: -+* only Windows 0-3 can be remapped. -+* -+* INPUT: -+* winNum - window number -+* pAddrDecWin - pointer to address space window structure -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_STATUS mvXorPciRemap(MV_U32 unit,MV_U32 winNum, MV_U32 addrHigh) -+{ -+ /* Parameter checking */ -+ if (winNum >= XOR_MAX_REMAP_WIN) -+ { -+ DB(mvOsPrintf("%s: ERR. Invalid win num %d\n", __FUNCTION__, winNum)); -+ return MV_BAD_PARAM; -+ } -+ -+ MV_REG_WRITE(XOR_HIGH_ADDR_REMAP_REG(unit,winNum), addrHigh); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* xorWinOverlapDetect - Detect XOR address windows overlaping -+* -+* DESCRIPTION: -+* An unpredicted behaviour is expected in case XOR address decode -+* windows overlaps. -+* This function detects XOR address decode windows overlaping of a -+* specified window. The function does not check the window itself for -+* overlaping. The function also skipps disabled address decode windows. -+* -+* INPUT: -+* winNum - address decode window number. -+* pAddrDecWin - An address decode window struct. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data -+* from registers. -+* -+*******************************************************************************/ -+static MV_STATUS xorWinOverlapDetect(MV_U32 unit,MV_U32 winNum, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 baseAddrEnableReg; -+ MV_U32 winNumIndex,chan; -+ MV_XOR_DEC_WIN addrDecWin; -+ -+ if (pAddrWin == NULL) -+ { -+ DB(mvOsPrintf("%s: ERR. pAddrWin is NULL pointer\n", __FUNCTION__ )); -+ return MV_BAD_PTR; -+ } -+ -+ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) -+ { -+ /* Read base address enable register. Do not check disabled windows */ -+ baseAddrEnableReg = MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,chan)); -+ -+ for (winNumIndex = 0; winNumIndex < XOR_MAX_ADDR_DEC_WIN; winNumIndex++) -+ { -+ /* Do not check window itself */ -+ if (winNumIndex == winNum) -+ { -+ continue; -+ } -+ -+ /* Do not check disabled windows */ -+ if ((baseAddrEnableReg & XEXWCR_WIN_EN_MASK(winNumIndex)) == 0) -+ { -+ continue; -+ } -+ -+ /* Get window parameters */ -+ if (MV_OK != mvXorTargetWinGet(unit,winNumIndex, &addrDecWin)) -+ { -+ DB(mvOsPrintf("%s: ERR. TargetWinGet failed\n", __FUNCTION__ )); -+ return MV_ERROR; -+ } -+ -+ if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin))) -+ { -+ return MV_TRUE; -+ } -+ } -+ } -+ -+ return MV_FALSE; -+} -+ -+static MV_VOID mvXorAddrDecShowUnit(MV_U32 unit) -+{ -+ MV_XOR_DEC_WIN win; -+ int i; -+ -+ mvOsOutput( "\n" ); -+ mvOsOutput( "XOR %d:\n", unit ); -+ mvOsOutput( "----\n" ); -+ -+ for( i = 0; i < XOR_MAX_ADDR_DEC_WIN; i++ ) -+ { -+ memset( &win, 0, sizeof(MV_XOR_DEC_WIN) ); -+ -+ mvOsOutput( "win%d - ", i ); -+ -+ if( mvXorTargetWinGet(unit, i, &win ) == MV_OK ) -+ { -+ if( win.enable ) -+ { -+ mvOsOutput( "%s base %x, ", -+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); -+ -+ mvSizePrint( win.addrWin.size ); -+ -+ mvOsOutput( "\n" ); -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ } -+ } -+} -+ -+/******************************************************************************* -+* mvXorAddrDecShow - Print the XOR address decode map. -+* -+* DESCRIPTION: -+* This function print the XOR address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvXorAddrDecShow(MV_VOID) -+{ -+ int i; -+ -+ for( i = 0; i < MV_XOR_MAX_UNIT; i++ ) -+ mvXorAddrDecShowUnit(i); -+ -+} -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.h 2010-11-09 20:28:10.062495382 +0100 -@@ -0,0 +1,140 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCMVSysXorh -+#define __INCMVSysXorh -+ -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+#include "ctrlEnv/sys/mvCpuIf.h" -+ -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+ -+#define XOR_MAX_ADDR_DEC_WIN 8 /* Maximum address decode windows */ -+#define XOR_MAX_REMAP_WIN 4 /* Maximum address arbiter windows */ -+ -+/* XOR Engine Address Decoding Register Map */ -+#define XOR_WINDOW_CTRL_REG(unit,chan) (XOR_UNIT_BASE(unit)+(0x240 + ((chan) * 4))) -+#define XOR_BASE_ADDR_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x250 + ((winNum) * 4))) -+#define XOR_SIZE_MASK_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x270 + ((winNum) * 4))) -+#define XOR_HIGH_ADDR_REMAP_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x290 + ((winNum) * 4))) -+ -+/* XOR Engine [0..1] Window Control Registers (XExWCR) */ -+#define XEXWCR_WIN_EN_OFFS(winNum) (winNum) -+#define XEXWCR_WIN_EN_MASK(winNum) (1 << (XEXWCR_WIN_EN_OFFS(winNum))) -+#define XEXWCR_WIN_EN_ENABLE(winNum) (1 << (XEXWCR_WIN_EN_OFFS(winNum))) -+#define XEXWCR_WIN_EN_DISABLE(winNum) (0 << (XEXWCR_WIN_EN_OFFS(winNum))) -+ -+#define XEXWCR_WIN_ACC_OFFS(winNum) ((2 * winNum) + 16) -+#define XEXWCR_WIN_ACC_MASK(winNum) (3 << (XEXWCR_WIN_ACC_OFFS(winNum))) -+#define XEXWCR_WIN_ACC_NO_ACC(winNum) (0 << (XEXWCR_WIN_ACC_OFFS(winNum))) -+#define XEXWCR_WIN_ACC_RO(winNum) (1 << (XEXWCR_WIN_ACC_OFFS(winNum))) -+#define XEXWCR_WIN_ACC_RW(winNum) (3 << (XEXWCR_WIN_ACC_OFFS(winNum))) -+ -+/* XOR Engine Base Address Registers (XEBARx) */ -+#define XEBARX_TARGET_OFFS (0) -+#define XEBARX_TARGET_MASK (0xF << XEBARX_TARGET_OFFS) -+#define XEBARX_ATTR_OFFS (8) -+#define XEBARX_ATTR_MASK (0xFF << XEBARX_ATTR_OFFS) -+#define XEBARX_BASE_OFFS (16) -+#define XEBARX_BASE_MASK (0xFFFF << XEBARX_BASE_OFFS) -+ -+/* XOR Engine Size Mask Registers (XESMRx) */ -+#define XESMRX_SIZE_MASK_OFFS (16) -+#define XESMRX_SIZE_MASK_MASK (0xFFFF << XESMRX_SIZE_MASK_OFFS) -+ -+/* XOR Engine High Address Remap Register (XEHARRx1) */ -+#define XEHARRX_REMAP_OFFS (0) -+#define XEHARRX_REMAP_MASK (0xFFFFFFFF << XEHARRX_REMAP_OFFS) -+ -+typedef struct _mvXorDecWin -+{ -+ MV_TARGET target; -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+}MV_XOR_DEC_WIN; -+ -+MV_STATUS mvXorInit (MV_VOID); -+MV_STATUS mvXorTargetWinSet(MV_U32 unit, MV_U32 winNum, -+ MV_XOR_DEC_WIN *pAddrDecWin); -+MV_STATUS mvXorTargetWinGet(MV_U32 unit, MV_U32 winNum, -+ MV_XOR_DEC_WIN *pAddrDecWin); -+MV_STATUS mvXorTargetWinEnable(MV_U32 unit, -+ MV_U32 winNum, MV_BOOL enable); -+MV_STATUS mvXorProtWinSet (MV_U32 unit,MV_U32 chan, MV_U32 winNum, MV_BOOL access, -+ MV_BOOL write); -+MV_STATUS mvXorPciRemap(MV_U32 unit, MV_U32 winNum, MV_U32 addrHigh); -+ -+MV_VOID mvXorAddrDecShow(MV_VOID); -+ -+#ifdef __cplusplus -+} -+#endif -+ -+#endif -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.c 2010-11-09 20:28:10.101392611 +0100 -@@ -0,0 +1,75 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "device/mvDevice.h" -+ -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.h 2010-11-09 20:28:10.141918633 +0100 -@@ -0,0 +1,74 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvDeviceH -+#define __INCmvDeviceH -+ -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+#include "device/mvDeviceRegs.h" -+ -+ -+#endif /* #ifndef __INCmvDeviceH */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDeviceRegs.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDeviceRegs.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDeviceRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDeviceRegs.h 2010-11-09 20:28:10.181250318 +0100 -@@ -0,0 +1,101 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvDeviceRegsH -+#define __INCmvDeviceRegsH -+ -+#ifndef MV_ASMLANGUAGE -+#include "ctrlEnv/mvCtrlEnvLib.h" -+/* This enumerator describes the Marvell controller possible devices that */ -+/* can be connected to its device interface. */ -+typedef enum _mvDevice -+{ -+#if defined(MV_INCLUDE_DEVICE_CS0) -+ DEV_CS0 = 0, /* Device connected to dev CS[0] */ -+#endif -+#if defined(MV_INCLUDE_DEVICE_CS1) -+ DEV_CS1 = 1, /* Device connected to dev CS[1] */ -+#endif -+#if defined(MV_INCLUDE_DEVICE_CS2) -+ DEV_CS2 = 2, /* Device connected to dev CS[2] */ -+#endif -+#if defined(MV_INCLUDE_DEVICE_CS3) -+ DEV_CS3 = 3, /* Device connected to dev CS[2] */ -+#endif -+#if defined(MV_INCLUDE_DEVICE_CS4) -+ DEV_CS4 = 4, /* Device connected to BOOT dev */ -+#endif -+ MV_DEV_MAX_CS = MV_DEVICE_MAX_CS -+}MV_DEVICE; -+ -+ -+#endif /* MV_ASMLANGUAGE */ -+ -+ -+#define NAND_CTRL_REG 0x10470 -+ -+#define NAND_ACTCEBOOT_BIT BIT1 -+ -+ -+#endif /* #ifndef __INCmvDeviceRegsH */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.c 2010-11-09 20:28:10.222495542 +0100 -@@ -0,0 +1,211 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+*******************************************************************************/ -+/******************************************************************************* -+* mvOsCpuArchLib.c - Marvell CPU architecture library -+* -+* DESCRIPTION: -+* This library introduce Marvell API for OS dependent CPU architecture -+* APIs. This library introduce single CPU architecture services APKI -+* cross OS. -+* -+* DEPENDENCIES: -+* None. -+* -+*******************************************************************************/ -+ -+/* includes */ -+#include -+#include "mvOs.h" -+ -+static MV_U32 read_p15_c0 (void); -+ -+/* defines */ -+#define ARM_ID_REVISION_OFFS 0 -+#define ARM_ID_REVISION_MASK (0xf << ARM_ID_REVISION_OFFS) -+ -+#define ARM_ID_PART_NUM_OFFS 4 -+#define ARM_ID_PART_NUM_MASK (0xfff << ARM_ID_PART_NUM_OFFS) -+ -+#define ARM_ID_ARCH_OFFS 16 -+#define ARM_ID_ARCH_MASK (0xf << ARM_ID_ARCH_OFFS) -+ -+#define ARM_ID_VAR_OFFS 20 -+#define ARM_ID_VAR_MASK (0xf << ARM_ID_VAR_OFFS) -+ -+#define ARM_ID_ASCII_OFFS 24 -+#define ARM_ID_ASCII_MASK (0xff << ARM_ID_ASCII_OFFS) -+ -+ -+ -+void* mvOsIoCachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, -+ MV_U32 *memHandle) -+{ -+ void *p = kmalloc( size, GFP_KERNEL ); -+ *pPhyAddr = pci_map_single( osHandle, p, 0, PCI_DMA_BIDIRECTIONAL ); -+ return p; -+} -+void* mvOsIoUncachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, -+ MV_U32 *memHandle) -+{ -+ return pci_alloc_consistent( osHandle, size, (dma_addr_t *)pPhyAddr ); -+} -+ -+void mvOsIoUncachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, -+ MV_U32 memHandle) -+{ -+ return pci_free_consistent( osHandle, size, pVirtAddr, (dma_addr_t)phyAddr ); -+} -+ -+void mvOsIoCachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, -+ MV_U32 memHandle ) -+{ -+ return kfree( pVirtAddr ); -+} -+ -+int mvOsRand(void) -+{ -+ int rand; -+ get_random_bytes(&rand, sizeof(rand) ); -+ return rand; -+} -+ -+/******************************************************************************* -+* mvOsCpuVerGet() - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit CPU Revision -+* -+*******************************************************************************/ -+MV_U32 mvOsCpuRevGet( MV_VOID ) -+{ -+ return ((read_p15_c0() & ARM_ID_REVISION_MASK ) >> ARM_ID_REVISION_OFFS); -+} -+/******************************************************************************* -+* mvOsCpuPartGet() - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit CPU Part number -+* -+*******************************************************************************/ -+MV_U32 mvOsCpuPartGet( MV_VOID ) -+{ -+ return ((read_p15_c0() & ARM_ID_PART_NUM_MASK ) >> ARM_ID_PART_NUM_OFFS); -+} -+/******************************************************************************* -+* mvOsCpuArchGet() - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit CPU Architicture number -+* -+*******************************************************************************/ -+MV_U32 mvOsCpuArchGet( MV_VOID ) -+{ -+ return ((read_p15_c0() & ARM_ID_ARCH_MASK ) >> ARM_ID_ARCH_OFFS); -+} -+/******************************************************************************* -+* mvOsCpuVarGet() - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit CPU Variant number -+* -+*******************************************************************************/ -+MV_U32 mvOsCpuVarGet( MV_VOID ) -+{ -+ return ((read_p15_c0() & ARM_ID_VAR_MASK ) >> ARM_ID_VAR_OFFS); -+} -+/******************************************************************************* -+* mvOsCpuAsciiGet() - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit CPU Variant number -+* -+*******************************************************************************/ -+MV_U32 mvOsCpuAsciiGet( MV_VOID ) -+{ -+ return ((read_p15_c0() & ARM_ID_ASCII_MASK ) >> ARM_ID_ASCII_OFFS); -+} -+ -+ -+ -+/* -+static unsigned long read_p15_c0 (void) -+*/ -+/* read co-processor 15, register #0 (ID register) */ -+static MV_U32 read_p15_c0 (void) -+{ -+ MV_U32 value; -+ -+ __asm__ __volatile__( -+ "mrc p15, 0, %0, c0, c0, 0 @ read control reg\n" -+ : "=r" (value) -+ : -+ : "memory"); -+ -+ return value; -+} -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h 2010-11-09 20:28:10.262495482 +0100 -@@ -0,0 +1,423 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+*******************************************************************************/ -+#ifndef _MV_OS_LNX_H_ -+#define _MV_OS_LNX_H_ -+ -+ -+#ifdef __KERNEL__ -+/* for kernel space */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "dbg-trace.h" -+ -+extern void mv_early_printk(char *fmt,...); -+ -+#define MV_ASM __asm__ __volatile__ -+#define INLINE inline -+#define MV_TRC_REC TRC_REC -+#define mvOsPrintf printk -+#define mvOsEarlyPrintf mv_early_printk -+#define mvOsOutput printk -+#define mvOsSPrintf sprintf -+#define mvOsMalloc(_size_) kmalloc(_size_,GFP_ATOMIC) -+#define mvOsFree kfree -+#define mvOsMemcpy memcpy -+#define mvOsSleep(_mils_) mdelay(_mils_) -+#define mvOsTaskLock() -+#define mvOsTaskUnlock() -+#define strtol simple_strtoul -+#define mvOsDelay(x) mdelay(x) -+#define mvOsUDelay(x) udelay(x) -+#define mvCopyFromOs copy_from_user -+#define mvCopyToOs copy_to_user -+ -+ -+#include "mvTypes.h" -+#include "mvCommon.h" -+ -+#ifdef MV_NDEBUG -+#define mvOsAssert(cond) -+#else -+#define mvOsAssert(cond) { do { if(!(cond)) { BUG(); } }while(0); } -+#endif /* MV_NDEBUG */ -+ -+#else /* __KERNEL__ */ -+ -+/* for user space applications */ -+#include -+#include -+#include -+#include -+ -+#define INLINE inline -+#define mvOsPrintf printf -+#define mvOsOutput printf -+#define mvOsMalloc(_size_) malloc(_size_) -+#define mvOsFree free -+#define mvOsAssert(cond) assert(cond) -+ -+#endif /* __KERNEL__ */ -+#define mvOsIoVirtToPhy(pDev, pVirtAddr) \ -+ pci_map_single( (pDev), (pVirtAddr), 0, PCI_DMA_BIDIRECTIONAL ) -+ -+#define mvOsCacheClear(pDev, p, size ) \ -+ pci_map_single( (pDev), (p), (size), PCI_DMA_BIDIRECTIONAL) -+ -+#define mvOsCacheFlush(pDev, p, size ) \ -+ pci_map_single( (pDev), (p), (size), PCI_DMA_TODEVICE) -+ -+#define mvOsCacheInvalidate(pDev, p, size) \ -+ pci_map_single( (pDev), (p), (size), PCI_DMA_FROMDEVICE ) -+ -+#define mvOsCacheUnmap(pDev, phys, size) \ -+ pci_unmap_single( (pDev), (dma_addr_t)(phys), (size), PCI_DMA_FROMDEVICE ) -+ -+ -+#define CPU_PHY_MEM(x) (MV_U32)x -+#define CPU_MEMIO_CACHED_ADDR(x) (void*)x -+#define CPU_MEMIO_UNCACHED_ADDR(x) (void*)x -+ -+ -+/* CPU architecture dependent 32, 16, 8 bit read/write IO addresses */ -+#define MV_MEMIO32_WRITE(addr, data) \ -+ ((*((volatile unsigned int*)(addr))) = ((unsigned int)(data))) -+ -+#define MV_MEMIO32_READ(addr) \ -+ ((*((volatile unsigned int*)(addr)))) -+ -+#define MV_MEMIO16_WRITE(addr, data) \ -+ ((*((volatile unsigned short*)(addr))) = ((unsigned short)(data))) -+ -+#define MV_MEMIO16_READ(addr) \ -+ ((*((volatile unsigned short*)(addr)))) -+ -+#define MV_MEMIO8_WRITE(addr, data) \ -+ ((*((volatile unsigned char*)(addr))) = ((unsigned char)(data))) -+ -+#define MV_MEMIO8_READ(addr) \ -+ ((*((volatile unsigned char*)(addr)))) -+ -+ -+/* No Fast Swap implementation (in assembler) for ARM */ -+#define MV_32BIT_LE_FAST(val) MV_32BIT_LE(val) -+#define MV_16BIT_LE_FAST(val) MV_16BIT_LE(val) -+#define MV_32BIT_BE_FAST(val) MV_32BIT_BE(val) -+#define MV_16BIT_BE_FAST(val) MV_16BIT_BE(val) -+ -+/* 32 and 16 bit read/write in big/little endian mode */ -+ -+/* 16bit write in little endian mode */ -+#define MV_MEMIO_LE16_WRITE(addr, data) \ -+ MV_MEMIO16_WRITE(addr, MV_16BIT_LE_FAST(data)) -+ -+/* 16bit read in little endian mode */ -+static __inline MV_U16 MV_MEMIO_LE16_READ(MV_U32 addr) -+{ -+ MV_U16 data; -+ -+ data= (MV_U16)MV_MEMIO16_READ(addr); -+ -+ return (MV_U16)MV_16BIT_LE_FAST(data); -+} -+ -+/* 32bit write in little endian mode */ -+#define MV_MEMIO_LE32_WRITE(addr, data) \ -+ MV_MEMIO32_WRITE(addr, MV_32BIT_LE_FAST(data)) -+ -+/* 32bit read in little endian mode */ -+static __inline MV_U32 MV_MEMIO_LE32_READ(MV_U32 addr) -+{ -+ MV_U32 data; -+ -+ data= (MV_U32)MV_MEMIO32_READ(addr); -+ -+ return (MV_U32)MV_32BIT_LE_FAST(data); -+} -+ -+static __inline void mvOsBCopy(char* srcAddr, char* dstAddr, int byteCount) -+{ -+ while(byteCount != 0) -+ { -+ *dstAddr = *srcAddr; -+ dstAddr++; -+ srcAddr++; -+ byteCount--; -+ } -+} -+ -+static INLINE MV_U64 mvOsDivMod64(MV_U64 divided, MV_U64 divisor, MV_U64* modulu) -+{ -+ MV_U64 division = 0; -+ -+ if(divisor == 1) -+ return divided; -+ -+ while(divided >= divisor) -+ { -+ division++; -+ divided -= divisor; -+ } -+ if (modulu != NULL) -+ *modulu = divided; -+ -+ return division; -+} -+ -+#if defined(MV_BRIDGE_SYNC_REORDER) -+extern MV_U32 *mvUncachedParam; -+ -+static __inline void mvOsBridgeReorderWA(void) -+{ -+ volatile MV_U32 val = 0; -+ -+ val = mvUncachedParam[0]; -+} -+#endif -+ -+ -+/* Flash APIs */ -+#define MV_FL_8_READ MV_MEMIO8_READ -+#define MV_FL_16_READ MV_MEMIO_LE16_READ -+#define MV_FL_32_READ MV_MEMIO_LE32_READ -+#define MV_FL_8_DATA_READ MV_MEMIO8_READ -+#define MV_FL_16_DATA_READ MV_MEMIO16_READ -+#define MV_FL_32_DATA_READ MV_MEMIO32_READ -+#define MV_FL_8_WRITE MV_MEMIO8_WRITE -+#define MV_FL_16_WRITE MV_MEMIO_LE16_WRITE -+#define MV_FL_32_WRITE MV_MEMIO_LE32_WRITE -+#define MV_FL_8_DATA_WRITE MV_MEMIO8_WRITE -+#define MV_FL_16_DATA_WRITE MV_MEMIO16_WRITE -+#define MV_FL_32_DATA_WRITE MV_MEMIO32_WRITE -+ -+ -+/* CPU cache information */ -+#define CPU_I_CACHE_LINE_SIZE 32 /* 2do: replace 32 with linux core macro */ -+#define CPU_D_CACHE_LINE_SIZE 32 /* 2do: replace 32 with linux core macro */ -+ -+#ifdef CONFIG_L2_CACHE_ENABLE -+/* Data cache flush one line */ -+#define mvOsCacheLineFlushInv(handle, addr) \ -+{ \ -+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c14, 1" : : "r" (addr));\ -+ __asm__ __volatile__ ("mcr p15, 1, %0, c15, c10, 1" : : "r" (addr));\ -+ __asm__ __volatile__ ("mcr p15, 0, r0, c7, c10, 4"); \ -+} -+ -+#else -+ -+/* Data cache flush one line */ -+#define mvOsCacheLineFlushInv(handle, addr) \ -+{ \ -+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c14, 1" : : "r" (addr));\ -+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" : : "r" (addr)); \ -+} -+#endif -+ -+#ifdef CONFIG_L2_CACHE_ENABLE -+#define mvOsCacheLineInv(handle,addr) \ -+{ \ -+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c6, 1" : : "r" (addr)); \ -+ __asm__ __volatile__ ("mcr p15, 1, %0, c15, c11, 1" : : "r" (addr)); \ -+} -+#else -+#define mvOsCacheLineInv(handle,addr) \ -+{ \ -+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c6, 1" : : "r" (addr)); \ -+} -+#endif -+ -+#ifdef CONFIG_L2_CACHE_ENABLE -+/* Data cache flush one line */ -+#define mvOsCacheLineFlush(handle, addr) \ -+{ \ -+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 1" : : "r" (addr));\ -+ __asm__ __volatile__ ("mcr p15, 1, %0, c15, c9, 1" : : "r" (addr));\ -+ __asm__ __volatile__ ("mcr p15, 0, r0, c7, c10, 4"); \ -+} -+ -+#else -+/* Data cache flush one line */ -+#define mvOsCacheLineFlush(handle, addr) \ -+{ \ -+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 1" : : "r" (addr));\ -+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" : : "r" (addr)); \ -+} -+#endif -+ -+static __inline void mvOsPrefetch(const void *ptr) -+{ -+#ifdef CONFIG_USE_DSP -+ __asm__ __volatile__( -+ "pld\t%0" -+ : -+ : "o" (*(char *)ptr) -+ : "cc"); -+#else -+ return; -+#endif -+} -+ -+ -+/* Flush CPU pipe */ -+#define CPU_PIPE_FLUSH -+ -+ -+ -+ -+ -+/* register manipulations */ -+ -+/****************************************************************************** -+* This debug function enable the write of each register that u-boot access to -+* to an array in the DRAM, the function record only MV_REG_WRITE access. -+* The function could not be operate when booting from flash. -+* In order to print the array we use the printreg command. -+******************************************************************************/ -+/* #define REG_DEBUG */ -+#if defined(REG_DEBUG) -+extern int reg_arry[2048][2]; -+extern int reg_arry_index; -+#endif -+ -+/* Marvell controller register read/write macros */ -+#define MV_REG_VALUE(offset) \ -+ (MV_MEMIO32_READ((INTER_REGS_BASE | (offset)))) -+ -+#define MV_REG_READ(offset) \ -+ (MV_MEMIO_LE32_READ(INTER_REGS_BASE | (offset))) -+ -+#if defined(REG_DEBUG) -+#define MV_REG_WRITE(offset, val) \ -+ MV_MEMIO_LE32_WRITE((INTER_REGS_BASE | (offset)), (val)); \ -+ { \ -+ reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\ -+ reg_arry[reg_arry_index][1] = (val);\ -+ reg_arry_index++;\ -+ } -+#else -+#define MV_REG_WRITE(offset, val) \ -+ MV_MEMIO_LE32_WRITE((INTER_REGS_BASE | (offset)), (val)); -+#endif -+ -+#define MV_REG_BYTE_READ(offset) \ -+ (MV_MEMIO8_READ((INTER_REGS_BASE | (offset)))) -+ -+#if defined(REG_DEBUG) -+#define MV_REG_BYTE_WRITE(offset, val) \ -+ MV_MEMIO8_WRITE((INTER_REGS_BASE | (offset)), (val)); \ -+ { \ -+ reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\ -+ reg_arry[reg_arry_index][1] = (val);\ -+ reg_arry_index++;\ -+ } -+#else -+#define MV_REG_BYTE_WRITE(offset, val) \ -+ MV_MEMIO8_WRITE((INTER_REGS_BASE | (offset)), (val)) -+#endif -+ -+#if defined(REG_DEBUG) -+#define MV_REG_BIT_SET(offset, bitMask) \ -+ (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ -+ (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) | \ -+ MV_32BIT_LE_FAST(bitMask)))); \ -+ { \ -+ reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\ -+ reg_arry[reg_arry_index][1] = (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)));\ -+ reg_arry_index++;\ -+ } -+#else -+#define MV_REG_BIT_SET(offset, bitMask) \ -+ (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ -+ (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) | \ -+ MV_32BIT_LE_FAST(bitMask)))) -+#endif -+ -+#if defined(REG_DEBUG) -+#define MV_REG_BIT_RESET(offset,bitMask) \ -+ (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ -+ (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) & \ -+ MV_32BIT_LE_FAST(~bitMask)))); \ -+ { \ -+ reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\ -+ reg_arry[reg_arry_index][1] = (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)));\ -+ reg_arry_index++;\ -+ } -+#else -+#define MV_REG_BIT_RESET(offset,bitMask) \ -+ (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ -+ (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) & \ -+ MV_32BIT_LE_FAST(~bitMask)))) -+#endif -+ -+ -+ -+/* ARM architecture APIs */ -+MV_U32 mvOsCpuRevGet (MV_VOID); -+MV_U32 mvOsCpuPartGet (MV_VOID); -+MV_U32 mvOsCpuArchGet (MV_VOID); -+MV_U32 mvOsCpuVarGet (MV_VOID); -+MV_U32 mvOsCpuAsciiGet (MV_VOID); -+ -+/* Other APIs */ -+void* mvOsIoCachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, MV_U32 *memHandle); -+void* mvOsIoUncachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, MV_U32 *memHandle ); -+void mvOsIoUncachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, MV_U32 memHandle ); -+void mvOsIoCachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, MV_U32 memHandle ); -+int mvOsRand(void); -+ -+#endif /* _MV_OS_LNX_H_ */ -+ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOsSata.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/linux_oss/mvOsSata.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOsSata.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/linux_oss/mvOsSata.h 2010-11-09 20:28:10.302495426 +0100 -@@ -0,0 +1,158 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+*******************************************************************************/ -+/******************************************************************************* -+* mvOsLinux.h - O.S. interface header file for Linux -+* -+* DESCRIPTION: -+* This header file contains OS dependent definition under Linux -+* -+* DEPENDENCIES: -+* Linux kernel header files. -+* -+* FILE REVISION NUMBER: -+* $Revision: 1.1 $ -+*******************************************************************************/ -+ -+#ifndef __INCmvOsLinuxh -+#define __INCmvOsLinuxh -+ -+/* Includes */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include "mvOs.h" -+ -+ -+/* Definitions */ -+#define MV_DEFAULT_QUEUE_DEPTH 2 -+#define MV_SATA_SUPPORT_EDMA_SINGLE_DATA_REGION -+#define MV_SATA_SUPPORT_GEN2E_128_QUEUE_LEN -+ -+#ifdef CONFIG_MV88F6082 -+ #define MV_SATA_OVERRIDE_SW_QUEUE_SIZE -+ #define MV_SATA_REQUESTED_SW_QUEUE_SIZE 2 -+ #undef MV_SATA_SUPPORT_GEN2E_128_QUEUE_LEN -+#endif -+ -+/* System dependent macro for flushing CPU write cache */ -+#if defined (MV_BRIDGE_SYNC_REORDER) -+#define MV_CPU_WRITE_BUFFER_FLUSH() do { \ -+ wmb(); \ -+ mvOsBridgeReorderWA(); \ -+ } while (0) -+#else -+#define MV_CPU_WRITE_BUFFER_FLUSH() wmb() -+#endif /* CONFIG_MV78XX0 */ -+ -+/* System dependent little endian from / to CPU conversions */ -+#define MV_CPU_TO_LE16(x) cpu_to_le16(x) -+#define MV_CPU_TO_LE32(x) cpu_to_le32(x) -+ -+#define MV_LE16_TO_CPU(x) le16_to_cpu(x) -+#define MV_LE32_TO_CPU(x) le32_to_cpu(x) -+ -+#ifdef __BIG_ENDIAN_BITFIELD -+#define MV_BIG_ENDIAN_BITFIELD -+#endif -+ -+/* System dependent register read / write in byte/word/dword variants */ -+#define MV_REG_WRITE_BYTE(base, offset, val) writeb(val, base + offset) -+#define MV_REG_WRITE_WORD(base, offset, val) writew(val, base + offset) -+#define MV_REG_WRITE_DWORD(base, offset, val) writel(val, base + offset) -+#define MV_REG_READ_BYTE(base, offset) readb(base + offset) -+#define MV_REG_READ_WORD(base, offset) readw(base + offset) -+#define MV_REG_READ_DWORD(base, offset) readl(base + offset) -+ -+ -+/* Typedefs */ -+ -+/* System dependant typedefs */ -+typedef void *MV_VOID_PTR; -+typedef u32 *MV_U32_PTR; -+typedef u16 *MV_U16_PTR; -+typedef u8 *MV_U8_PTR; -+typedef char *MV_CHAR_PTR; -+typedef void *MV_BUS_ADDR_T; -+typedef unsigned long MV_CPU_FLAGS; -+ -+ -+/* Structures */ -+/* System dependent structure */ -+typedef struct mvOsSemaphore -+{ -+ int notUsed; -+} MV_OS_SEMAPHORE; -+ -+ -+/* Functions (User implemented)*/ -+ -+/* Semaphore init, take and release */ -+#define mvOsSemInit(x) MV_TRUE -+#define mvOsSemTake(x) -+#define mvOsSemRelease(x) -+ -+/* Interrupt masking and unmasking functions */ -+MV_CPU_FLAGS mvOsSaveFlagsAndMaskCPUInterrupts(MV_VOID); -+MV_VOID mvOsRestoreFlags(MV_CPU_FLAGS); -+ -+/* Delay function in micro seconds resolution */ -+void mvMicroSecondsDelay(MV_VOID_PTR, MV_U32); -+ -+/* Typedefs */ -+typedef enum mvBoolean -+{ -+ MV_SFALSE, MV_STRUE -+} MV_BOOLEAN; -+ -+/* System logging function */ -+#include "mvLog.h" -+/* Enable READ/WRITE Long SCSI command only when driver is compiled for debugging */ -+#ifdef MV_LOGGER -+#define MV_SATA_SUPPORT_READ_WRITE_LONG -+#endif -+ -+#define MV_IAL_LOG_ID 3 -+ -+#endif /* __INCmvOsLinuxh */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.c 2010-11-09 20:28:10.342495568 +0100 -@@ -0,0 +1,376 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "mvCntmr.h" -+#include "cpu/mvCpu.h" -+ -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+extern unsigned int whoAmI(void); -+ -+/******************************************************************************* -+* mvCntmrLoad - -+* -+* DESCRIPTION: -+* Load an init Value to a given counter/timer -+* -+* INPUT: -+* countNum - counter number -+* value - value to be loaded -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess -+*******************************************************************************/ -+MV_STATUS mvCntmrLoad(MV_U32 countNum, MV_U32 value) -+{ -+ if (countNum >= MV_CNTMR_MAX_COUNTER ) -+ { -+ -+ mvOsPrintf(("mvCntmrLoad: Err. Illigal counter number \n")); -+ return MV_BAD_PARAM;; -+ -+ } -+ -+ MV_REG_WRITE(CNTMR_RELOAD_REG(countNum),value); -+ MV_REG_WRITE(CNTMR_VAL_REG(countNum),value); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCntmrRead - -+* -+* DESCRIPTION: -+* Returns the value of the given Counter/Timer -+* -+* INPUT: -+* countNum - counter number -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_U32 counter value -+*******************************************************************************/ -+MV_U32 mvCntmrRead(MV_U32 countNum) -+{ -+ return MV_REG_READ(CNTMR_VAL_REG(countNum)); -+} -+ -+/******************************************************************************* -+* mvCntmrWrite - -+* -+* DESCRIPTION: -+* Returns the value of the given Counter/Timer -+* -+* INPUT: -+* countNum - counter number -+* countVal - value to write -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None -+*******************************************************************************/ -+void mvCntmrWrite(MV_U32 countNum,MV_U32 countVal) -+{ -+ MV_REG_WRITE(CNTMR_VAL_REG(countNum),countVal); -+} -+ -+/******************************************************************************* -+* mvCntmrCtrlSet - -+* -+* DESCRIPTION: -+* Set the Control to a given counter/timer -+* -+* INPUT: -+* countNum - counter number -+* pCtrl - pointer to MV_CNTMR_CTRL structure -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess -+*******************************************************************************/ -+MV_STATUS mvCntmrCtrlSet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl) -+{ -+ MV_U32 cntmrCtrl; -+ -+ if (countNum >= MV_CNTMR_MAX_COUNTER ) -+ { -+ -+ DB(mvOsPrintf(("mvCntmrCtrlSet: Err. Illigal counter number \n"))); -+ return MV_BAD_PARAM;; -+ -+ } -+ -+ /* read control register */ -+ cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG); -+ -+ -+ if (pCtrl->enable) /* enable counter\timer */ -+ { -+ cntmrCtrl |= CTCR_ARM_TIMER_EN(countNum); -+ } -+ else /* disable counter\timer */ -+ { -+ cntmrCtrl &= ~CTCR_ARM_TIMER_EN(countNum); -+ } -+ -+ if ( pCtrl->autoEnable ) /* Auto mode */ -+ { -+ cntmrCtrl |= CTCR_ARM_TIMER_AUTO_EN(countNum); -+ -+ } -+ else /* no auto mode */ -+ { -+ cntmrCtrl &= ~CTCR_ARM_TIMER_AUTO_EN(countNum); -+ } -+ -+ MV_REG_WRITE(CNTMR_CTRL_REG,cntmrCtrl); -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvCntmrCtrlGet - -+* -+* DESCRIPTION: -+* Get the Control value of a given counter/timer -+* -+* INPUT: -+* countNum - counter number -+* pCtrl - pointer to MV_CNTMR_CTRL structure -+* -+* OUTPUT: -+* Counter\Timer control value -+* -+* RETURN: -+* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess -+*******************************************************************************/ -+MV_STATUS mvCntmrCtrlGet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl) -+{ -+ MV_U32 cntmrCtrl; -+ -+ if (countNum >= MV_CNTMR_MAX_COUNTER ) -+ { -+ DB(mvOsPrintf(("mvCntmrCtrlGet: Err. Illigal counter number \n"))); -+ return MV_BAD_PARAM;; -+ } -+ -+ /* read control register */ -+ cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG); -+ -+ /* enable counter\timer */ -+ if (cntmrCtrl & CTCR_ARM_TIMER_EN(countNum)) -+ { -+ pCtrl->enable = MV_TRUE; -+ } -+ else -+ { -+ pCtrl->enable = MV_FALSE; -+ } -+ -+ /* counter mode */ -+ if (cntmrCtrl & CTCR_ARM_TIMER_AUTO_EN(countNum)) -+ { -+ pCtrl->autoEnable = MV_TRUE; -+ } -+ else -+ { -+ pCtrl->autoEnable = MV_FALSE; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCntmrEnable - -+* -+* DESCRIPTION: -+* Set the Enable-Bit to logic '1' ==> starting the counter -+* -+* INPUT: -+* countNum - counter number -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess -+*******************************************************************************/ -+MV_STATUS mvCntmrEnable(MV_U32 countNum) -+{ -+ MV_U32 cntmrCtrl; -+ -+ if (countNum >= MV_CNTMR_MAX_COUNTER ) -+ { -+ -+ DB(mvOsPrintf(("mvCntmrEnable: Err. Illigal counter number \n"))); -+ return MV_BAD_PARAM;; -+ -+ } -+ -+ /* read control register */ -+ cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG); -+ -+ /* enable counter\timer */ -+ cntmrCtrl |= CTCR_ARM_TIMER_EN(countNum); -+ -+ -+ MV_REG_WRITE(CNTMR_CTRL_REG,cntmrCtrl); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCntmrDisable - -+* -+* DESCRIPTION: -+* Stop the counter/timer running, and returns its Value -+* -+* INPUT: -+* countNum - counter number -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_U32 counter\timer value -+*******************************************************************************/ -+MV_STATUS mvCntmrDisable(MV_U32 countNum) -+{ -+ MV_U32 cntmrCtrl; -+ -+ if (countNum >= MV_CNTMR_MAX_COUNTER ) -+ { -+ -+ DB(mvOsPrintf(("mvCntmrDisable: Err. Illigal counter number \n"))); -+ return MV_BAD_PARAM;; -+ -+ } -+ -+ /* read control register */ -+ cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG); -+ -+ /* disable counter\timer */ -+ cntmrCtrl &= ~CTCR_ARM_TIMER_EN(countNum); -+ -+ MV_REG_WRITE(CNTMR_CTRL_REG,cntmrCtrl); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCntmrStart - -+* -+* DESCRIPTION: -+* Combined all the sub-operations above to one function: Load,setMode,Enable -+* -+* INPUT: -+* countNum - counter number -+* value - value of the counter\timer to be set -+* pCtrl - pointer to MV_CNTMR_CTRL structure -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess -+*******************************************************************************/ -+MV_STATUS mvCntmrStart(MV_U32 countNum, MV_U32 value, -+ MV_CNTMR_CTRL *pCtrl) -+{ -+ -+ if (countNum >= MV_CNTMR_MAX_COUNTER ) -+ { -+ -+ mvOsPrintf(("mvCntmrDisable: Err. Illigal counter number \n")); -+ return MV_BAD_PARAM;; -+ -+ } -+ -+ /* load value onto counter\timer */ -+ mvCntmrLoad(countNum,value); -+ -+ /* set the counter to load in the first time */ -+ mvCntmrWrite(countNum,value); -+ -+ /* set control for timer \ cunter and enable */ -+ mvCntmrCtrlSet(countNum,pCtrl); -+ -+ return MV_OK; -+} -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.h 2010-11-09 20:28:10.381238003 +0100 -@@ -0,0 +1,121 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvTmrWtdgh -+#define __INCmvTmrWtdgh -+ -+/* includes */ -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "cntmr/mvCntmrRegs.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+ -+ -+/* This enumerator describe counters\watchdog numbers */ -+typedef enum _mvCntmrID -+{ -+ TIMER0 = 0, -+ TIMER1, -+ WATCHDOG, -+ TIMER2, -+ TIMER3, -+}MV_CNTMR_ID; -+ -+ -+/* Counter / Timer control structure */ -+typedef struct _mvCntmrCtrl -+{ -+ MV_BOOL enable; /* enable */ -+ MV_BOOL autoEnable; /* counter/Timer */ -+}MV_CNTMR_CTRL; -+ -+ -+/* Functions */ -+ -+/* Load an init Value to a given counter/timer */ -+MV_STATUS mvCntmrLoad(MV_U32 countNum, MV_U32 value); -+ -+/* Returns the value of the given Counter/Timer */ -+MV_U32 mvCntmrRead(MV_U32 countNum); -+ -+/* Write a value of the given Counter/Timer */ -+void mvCntmrWrite(MV_U32 countNum,MV_U32 countVal); -+ -+/* Set the Control to a given counter/timer */ -+MV_STATUS mvCntmrCtrlSet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl); -+ -+/* Get the value of a given counter/timer */ -+MV_STATUS mvCntmrCtrlGet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl); -+ -+/* Set the Enable-Bit to logic '1' ==> starting the counter. */ -+MV_STATUS mvCntmrEnable(MV_U32 countNum); -+ -+/* Stop the counter/timer running, and returns its Value. */ -+MV_STATUS mvCntmrDisable(MV_U32 countNum); -+ -+/* Combined all the sub-operations above to one function: Load,setMode,Enable */ -+MV_STATUS mvCntmrStart(MV_U32 countNum, MV_U32 value, -+ MV_CNTMR_CTRL *pCtrl); -+ -+#endif /* __INCmvTmrWtdgh */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmrRegs.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmrRegs.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmrRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmrRegs.h 2010-11-09 20:28:10.422495568 +0100 -@@ -0,0 +1,121 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvTmrwtdgRegsh -+#define __INCmvTmrwtdgRegsh -+ -+/*******************************************/ -+/* ARM Timers Registers Map */ -+/*******************************************/ -+ -+#define CNTMR_RELOAD_REG(tmrNum) (CNTMR_BASE + 0x10 + (tmrNum)*8 + \ -+ (((tmrNum) <= 3)?0:8)) -+#define CNTMR_VAL_REG(tmrNum) (CNTMR_BASE + 0x14 + (tmrNum)*8 + \ -+ (((tmrNum) <= 3)?0:8)) -+#define CNTMR_CTRL_REG (CNTMR_BASE) -+ -+/*For MV78XX0*/ -+#define CNTMR_CAUSE_REG (CPU_AHB_MBUS_CAUSE_INT_REG(whoAmI())) -+#define CNTMR_MASK_REG (CPU_AHB_MBUS_MASK_INT_REG(whoAmI())) -+ -+/* ARM Timers Registers Map */ -+/*******************************************/ -+ -+ -+/* ARM Timers Control Register */ -+/* CPU_TIMERS_CTRL_REG (CTCR) */ -+ -+#define TIMER0_NUM 0 -+#define TIMER1_NUM 1 -+#define WATCHDOG_NUM 2 -+#define TIMER2_NUM 3 -+#define TIMER3_NUM 4 -+ -+#define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2) -+#define CTCR_ARM_TIMER_EN_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS) -+#define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr)) -+#define CTCR_ARM_TIMER_DIS(cntr) (0 << CTCR_ARM_TIMER_EN_OFFS(cntr)) -+ -+#define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1) -+#define CTCR_ARM_TIMER_AUTO_MASK(cntr) BIT1 -+#define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) -+#define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) -+ -+ -+/* ARM Timer\Watchdog Reload Register */ -+/* CNTMR_RELOAD_REG (TRR) */ -+ -+#define TRG_ARM_TIMER_REL_OFFS 0 -+#define TRG_ARM_TIMER_REL_MASK 0xffffffff -+ -+/* ARM Timer\Watchdog Register */ -+/* CNTMR_VAL_REG (TVRG) */ -+ -+#define TVR_ARM_TIMER_OFFS 0 -+#define TVR_ARM_TIMER_MASK 0xffffffff -+#define TVR_ARM_TIMER_MAX 0xffffffff -+ -+ -+ -+#endif /* __INCmvTmrwtdgRegsh */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c 2010-11-09 20:28:10.462495409 +0100 -@@ -0,0 +1,207 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include "mvOs.h" -+#include "mvCpuCntrs.h" -+ -+ -+const static MV_CPU_CNTRS_OPS mvCpuCntrsOpsTbl[MV_CPU_CNTRS_NUM][MV_CPU_CNTRS_OPS_NUM] = -+{ -+ /*0*/ -+ { -+ MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_DCACHE_READ_HIT, MV_CPU_CNTRS_DCACHE_READ_MISS, -+ MV_CPU_CNTRS_DCACHE_WRITE_HIT, MV_CPU_CNTRS_DCACHE_WRITE_MISS, MV_CPU_CNTRS_INSTRUCTIONS, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, -+ MV_CPU_CNTRS_MMU_READ_LATENCY, MV_CPU_CNTRS_ICACHE_READ_LATENCY, MV_CPU_CNTRS_WB_WRITE_LATENCY, -+ MV_CPU_CNTRS_LDM_STM_HOLD, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, -+ MV_CPU_CNTRS_DATA_WRITE_ACCESS, MV_CPU_CNTRS_DATA_READ_ACCESS, MV_CPU_CNTRS_INVALID, -+ MV_CPU_CNTRS_BRANCH_PREDICT_COUNT, -+ }, -+ /*1*/ -+ { -+ MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_ICACHE_READ_MISS, MV_CPU_CNTRS_DCACHE_READ_MISS, -+ MV_CPU_CNTRS_DCACHE_WRITE_MISS, MV_CPU_CNTRS_ITLB_MISS, MV_CPU_CNTRS_SINGLE_ISSUE, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BRANCH_RETIRED, MV_CPU_CNTRS_INVALID, -+ MV_CPU_CNTRS_MMU_READ_BEAT, MV_CPU_CNTRS_ICACHE_READ_LATENCY, MV_CPU_CNTRS_WB_WRITE_BEAT, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_IS_HOLD, MV_CPU_CNTRS_DATA_READ_ACCESS, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, -+ MV_CPU_CNTRS_INVALID, -+ }, -+ /*2*/ -+ { -+ MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DCACHE_ACCESS, -+ MV_CPU_CNTRS_DTLB_MISS, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BRANCH_PREDICT_MISS, MV_CPU_CNTRS_WB_WRITE_BEAT, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DCACHE_READ_LATENCY, MV_CPU_CNTRS_DCACHE_WRITE_LATENCY, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BIU_SIMULT_ACCESS, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, -+ MV_CPU_CNTRS_INVALID, -+ }, -+ /*3*/ -+ { -+ MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_DCACHE_READ_MISS, MV_CPU_CNTRS_DCACHE_WRITE_MISS, -+ MV_CPU_CNTRS_TLB_MISS, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BRANCH_TAKEN, MV_CPU_CNTRS_WB_FULL_CYCLES, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DCACHE_READ_BEAT, MV_CPU_CNTRS_DCACHE_WRITE_BEAT, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BIU_ANY_ACCESS, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DATA_WRITE_ACCESS, -+ MV_CPU_CNTRS_INVALID, -+ } -+}; -+ -+MV_CPU_CNTRS_ENTRY mvCpuCntrsTbl[MV_CPU_CNTRS_NUM]; -+ -+MV_CPU_CNTRS_EVENT* mvCpuCntrsEventTbl[128]; -+ -+void mvCpuCntrsReset(void) -+{ -+ MV_U32 reg = 0; -+ -+ MV_ASM ("mcr p15, 0, %0, c15, c13, 0" : : "r" (reg)); -+ MV_ASM ("mcr p15, 0, %0, c15, c13, 1" : : "r" (reg)); -+ MV_ASM ("mcr p15, 0, %0, c15, c13, 2" : : "r" (reg)); -+ MV_ASM ("mcr p15, 0, %0, c15, c13, 3" : : "r" (reg)); -+ MV_ASM ("mcr p15, 0, %0, c15, c13, 4" : : "r" (reg)); -+ MV_ASM ("mcr p15, 0, %0, c15, c13, 5" : : "r" (reg)); -+ MV_ASM ("mcr p15, 0, %0, c15, c13, 6" : : "r" (reg)); -+ MV_ASM ("mcr p15, 0, %0, c15, c13, 7" : : "r" (reg)); -+} -+ -+void program_counter(int counter, int op) -+{ -+ MV_U32 reg = (1 << op) | 0x1; /*enable*/ -+ -+ switch(counter) -+ { -+ case 0: -+ __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 0" : : "r" (reg)); -+ return; -+ -+ case 1: -+ __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 1" : : "r" (reg)); -+ return; -+ -+ case 2: -+ __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 2" : : "r" (reg)); -+ return; -+ -+ case 3: -+ __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 3" : : "r" (reg)); -+ return; -+ -+ default: -+ mvOsPrintf("error in program_counter: bad counter number (%d)\n", counter); -+ } -+ return; -+} -+ -+void mvCpuCntrsEventClear(MV_CPU_CNTRS_EVENT* pEvent) -+{ -+ int i; -+ -+ for(i=0; icounters_sum[i] = 0; -+ } -+ pEvent->num_of_measurements = 0; -+} -+ -+ -+MV_CPU_CNTRS_EVENT* mvCpuCntrsEventCreate(char* name, MV_U32 print_threshold) -+{ -+ int i; -+ MV_CPU_CNTRS_EVENT* event = mvOsMalloc(sizeof(MV_CPU_CNTRS_EVENT)); -+ -+ if(event) -+ { -+ strncpy(event->name, name, sizeof(event->name)); -+ event->num_of_measurements = 0; -+ event->avg_sample_count = print_threshold; -+ for(i=0; icounters_before[i] = 0; -+ event->counters_after[i] = 0; -+ event->counters_sum[i] = 0; -+ } -+ } -+ return event; -+} -+ -+void mvCpuCntrsEventDelete(MV_CPU_CNTRS_EVENT* event) -+{ -+ if(event != NULL) -+ mvOsFree(event); -+} -+ -+ -+MV_STATUS mvCpuCntrsProgram(int counter, MV_CPU_CNTRS_OPS op, -+ char* name, MV_U32 overhead) -+{ -+ int i; -+ -+ /* Find required operations */ -+ for(i=0; inum_of_measurements < pEvent->avg_sample_count) -+ return; -+ -+ mvOsPrintf("%16s: ", pEvent->name); -+ for(i=0; icounters_sum[i], -+ pEvent->num_of_measurements, NULL); -+ if(counters_avg >= mvCpuCntrsTbl[i].overhead) -+ counters_avg -= mvCpuCntrsTbl[i].overhead; -+ else -+ counters_avg = 0; -+ -+ mvOsPrintf("%s=%5llu, ", mvCpuCntrsTbl[i].name, counters_avg); -+ } -+ mvOsPrintf("\n"); -+ mvCpuCntrsEventClear(pEvent); -+ mvCpuCntrsReset(); -+} -+ -+void mvCpuCntrsStatus(void) -+{ -+ int i; -+ -+ for(i=0; icounters_before[i] = mvCpuCntrsRead(i); -+#else -+ pEvent->counters_before[1] = mvCpuCntrsRead(1); -+ pEvent->counters_before[3] = mvCpuCntrsRead(3); -+ pEvent->counters_before[0] = mvCpuCntrsRead(0); -+ pEvent->counters_before[2] = mvCpuCntrsRead(2); -+#endif -+} -+ -+static INLINE void mvCpuCntrsReadAfter(MV_CPU_CNTRS_EVENT* pEvent) -+{ -+ int i; -+ -+#if 0 -+ /* order is important - we want to measure the cycle count first here! */ -+ for(i=0; icounters_after[i] = mvCpuCntrsRead(i); -+#else -+ pEvent->counters_after[2] = mvCpuCntrsRead(2); -+ pEvent->counters_after[0] = mvCpuCntrsRead(0); -+ pEvent->counters_after[3] = mvCpuCntrsRead(3); -+ pEvent->counters_after[1] = mvCpuCntrsRead(1); -+#endif -+ -+ for(i=0; icounters_sum[i] += (pEvent->counters_after[i] - pEvent->counters_before[i]); -+ } -+ pEvent->num_of_measurements++; -+} -+ -+ -+#ifdef CONFIG_MV_CPU_PERF_CNTRS -+ -+#define MV_CPU_CNTRS_READ(counter) mvCpuCntrsRead(counter) -+ -+#define MV_CPU_CNTRS_START(event) mvCpuCntrsReadBefore(event) -+ -+#define MV_CPU_CNTRS_STOP(event) mvCpuCntrsReadAfter(event) -+ -+#define MV_CPU_CNTRS_SHOW(event) mvCpuCntrsShow(event) -+ -+#else -+ -+#define MV_CPU_CNTRS_READ(counter) -+#define MV_CPU_CNTRS_START(event) -+#define MV_CPU_CNTRS_STOP(event) -+#define MV_CPU_CNTRS_SHOW(event) -+ -+#endif /* CONFIG_MV_CPU_PERF_CNTRS */ -+ -+ -+#endif /* __mvCpuCntrs_h__ */ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c 2010-11-09 20:28:10.522495411 +0100 -@@ -0,0 +1,143 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include "mvOs.h" -+#include "mvCpuL2Cntrs.h" -+ -+ -+ -+MV_CPU_L2_CNTRS_ENTRY mvCpuL2CntrsTbl[MV_CPU_L2_CNTRS_NUM]; -+ -+MV_CPU_L2_CNTRS_EVENT* mvCpuL2CntrsEventTbl[128]; -+ -+void mvCpuL2CntrsReset(void) -+{ -+ MV_U32 reg = 0; -+ -+ MV_ASM ("mcr p15, 6, %0, c15, c13, 0" : : "r" (reg)); -+ MV_ASM ("mcr p15, 6, %0, c15, c13, 1" : : "r" (reg)); -+ MV_ASM ("mcr p15, 6, %0, c15, c13, 2" : : "r" (reg)); -+ MV_ASM ("mcr p15, 6, %0, c15, c13, 3" : : "r" (reg)); -+} -+ -+static void mvCpuL2CntrConfig(int counter, int op) -+{ -+ MV_U32 reg = (1 << op) | 0x1; /*enable*/ -+ -+ switch(counter) -+ { -+ case 0: -+ MV_ASM ("mcr p15, 6, %0, c15, c12, 0" : : "r" (reg)); -+ return; -+ -+ case 1: -+ MV_ASM ("mcr p15, 6, %0, c15, c12, 1" : : "r" (reg)); -+ return; -+ -+ default: -+ mvOsPrintf("mvCpuL2CntrConfig: bad counter number (%d)\n", counter); -+ } -+ return; -+} -+ -+void mvCpuL2CntrsEventClear(MV_CPU_L2_CNTRS_EVENT* pEvent) -+{ -+ int i; -+ -+ for(i=0; icounters_sum[i] = 0; -+ } -+ pEvent->num_of_measurements = 0; -+} -+ -+ -+MV_CPU_L2_CNTRS_EVENT* mvCpuL2CntrsEventCreate(char* name, MV_U32 print_threshold) -+{ -+ int i; -+ MV_CPU_L2_CNTRS_EVENT* event = mvOsMalloc(sizeof(MV_CPU_L2_CNTRS_EVENT)); -+ -+ if(event) -+ { -+ strncpy(event->name, name, sizeof(event->name)); -+ event->num_of_measurements = 0; -+ event->avg_sample_count = print_threshold; -+ for(i=0; icounters_before[i] = 0; -+ event->counters_after[i] = 0; -+ event->counters_sum[i] = 0; -+ } -+ } -+ return event; -+} -+ -+void mvCpuL2CntrsEventDelete(MV_CPU_L2_CNTRS_EVENT* event) -+{ -+ if(event != NULL) -+ mvOsFree(event); -+} -+ -+ -+MV_STATUS mvCpuL2CntrsProgram(int counter, MV_CPU_L2_CNTRS_OPS op, -+ char* name, MV_U32 overhead) -+{ -+ strncpy(mvCpuL2CntrsTbl[counter].name, name, sizeof(mvCpuL2CntrsTbl[counter].name)); -+ mvCpuL2CntrsTbl[counter].operation = op; -+ mvCpuL2CntrsTbl[counter].opIdx = op; -+ mvCpuL2CntrsTbl[counter].overhead = overhead; -+ mvCpuL2CntrConfig(counter, op); -+ mvOsPrintf("CPU L2 Counter %d: operation=%d, overhead=%d\n", -+ counter, op, overhead); -+ return MV_OK; -+} -+ -+void mvCpuL2CntrsShow(MV_CPU_L2_CNTRS_EVENT* pEvent) -+{ -+ int i; -+ MV_U64 counters_avg; -+ -+ if(pEvent->num_of_measurements < pEvent->avg_sample_count) -+ return; -+ -+ mvOsPrintf("%16s: ", pEvent->name); -+ for(i=0; icounters_sum[i], -+ pEvent->num_of_measurements, NULL); -+ -+ if(counters_avg >= mvCpuL2CntrsTbl[i].overhead) -+ counters_avg -= mvCpuL2CntrsTbl[i].overhead; -+ else -+ counters_avg = 0; -+ -+ mvOsPrintf("%s=%5llu, ", mvCpuL2CntrsTbl[i].name, counters_avg); -+ } -+ mvOsPrintf("\n"); -+ mvCpuL2CntrsEventClear(pEvent); -+ mvCpuL2CntrsReset(); -+} -+ -+void mvCpuL2CntrsStatus(void) -+{ -+ int i; -+ -+ for(i=0; icounters_before[i] = mvCpuL2CntrsRead(i); -+} -+ -+static INLINE void mvCpuL2CntrsReadAfter(MV_CPU_L2_CNTRS_EVENT* pEvent) -+{ -+ int i; -+ -+ for(i=0; icounters_after[i] = mvCpuL2CntrsRead(i); -+ pEvent->counters_sum[i] += (pEvent->counters_after[i] - pEvent->counters_before[i]); -+ } -+ pEvent->num_of_measurements++; -+} -+ -+ -+#ifdef CONFIG_MV_CPU_L2_PERF_CNTRS -+ -+#define MV_CPU_L2_CNTRS_READ(counter) mvCpuL2CntrsRead(counter) -+ -+#define MV_CPU_L2_CNTRS_START(event) mvCpuL2CntrsReadBefore(event) -+ -+#define MV_CPU_L2_CNTRS_STOP(event) mvCpuL2CntrsReadAfter(event) -+ -+#define MV_CPU_L2_CNTRS_SHOW(event) mvCpuL2CntrsShow(event) -+ -+#else -+ -+#define MV_CPU_L2_CNTRS_READ(counter) -+#define MV_CPU_L2_CNTRS_START(event) -+#define MV_CPU_L2_CNTRS_STOP(event) -+#define MV_CPU_L2_CNTRS_SHOW(event) -+ -+#endif /* CONFIG_MV_CPU_L2_PERF_CNTRS */ -+ -+ -+#endif /* __mvCpuL2Cntrs_h__ */ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c 2010-11-09 20:28:10.592495381 +0100 -@@ -0,0 +1,1479 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "ddr1_2/mvDram.h" -+#include "boardEnv/mvBoardEnvLib.h" -+ -+#undef MV_DEBUG -+#ifdef MV_DEBUG -+#define DB(x) x -+#else -+#define DB(x) -+#endif -+ -+static MV_VOID cpyDimm2BankInfo(MV_DIMM_INFO *pDimmInfo, -+ MV_DRAM_BANK_INFO *pBankInfo); -+static MV_U32 cas2ps(MV_U8 spd_byte); -+/******************************************************************************* -+* mvDramBankGet - Get the DRAM bank paramters. -+* -+* DESCRIPTION: -+* This function retrieves DRAM bank parameters as described in -+* DRAM_BANK_INFO struct to the controller DRAM unit. In case the board -+* has its DRAM on DIMMs it will use its EEPROM to extract SPD data -+* from it. Otherwise, if the DRAM is soldered on board, the function -+* should insert its bank information into MV_DRAM_BANK_INFO struct. -+* -+* INPUT: -+* bankNum - Board DRAM bank number. -+* -+* OUTPUT: -+* pBankInfo - DRAM bank information struct. -+* -+* RETURN: -+* MV_FAIL - Bank parameters could not be read. -+* -+*******************************************************************************/ -+MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo) -+{ -+ MV_DIMM_INFO dimmInfo; -+ -+ DB(mvOsPrintf("Dram: mvDramBankInfoGet bank %d\n", bankNum)); -+ /* zero pBankInfo structure */ -+ memset(pBankInfo, 0, sizeof(*pBankInfo)); -+ -+ if((NULL == pBankInfo) || (bankNum >= MV_DRAM_MAX_CS )) -+ { -+ DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); -+ return MV_BAD_PARAM; -+ } -+ if( MV_OK != dimmSpdGet((MV_U32)(bankNum/2), &dimmInfo)) -+ { -+ DB(mvOsPrintf("Dram: ERR dimmSpdGet failed to get dimm info \n")); -+ return MV_FAIL; -+ } -+ if((dimmInfo.numOfModuleBanks == 1) && ((bankNum % 2) == 1)) -+ { -+ DB(mvOsPrintf("Dram: ERR dimmSpdGet. Can't find DIMM bank 2 \n")); -+ return MV_FAIL; -+ } -+ -+ /* convert Dimm info to Bank info */ -+ cpyDimm2BankInfo(&dimmInfo, pBankInfo); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* cpyDimm2BankInfo - Convert a Dimm info struct into a bank info struct. -+* -+* DESCRIPTION: -+* Convert a Dimm info struct into a bank info struct. -+* -+* INPUT: -+* pDimmInfo - DIMM information structure. -+* -+* OUTPUT: -+* pBankInfo - DRAM bank information struct. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+static MV_VOID cpyDimm2BankInfo(MV_DIMM_INFO *pDimmInfo, -+ MV_DRAM_BANK_INFO *pBankInfo) -+{ -+ pBankInfo->memoryType = pDimmInfo->memoryType; -+ -+ /* DIMM dimensions */ -+ pBankInfo->numOfRowAddr = pDimmInfo->numOfRowAddr; -+ pBankInfo->numOfColAddr = pDimmInfo->numOfColAddr; -+ pBankInfo->dataWidth = pDimmInfo->dataWidth; -+ pBankInfo->errorCheckType = pDimmInfo->errorCheckType; -+ pBankInfo->sdramWidth = pDimmInfo->sdramWidth; -+ pBankInfo->errorCheckDataWidth = pDimmInfo->errorCheckDataWidth; -+ pBankInfo->numOfBanksOnEachDevice = pDimmInfo->numOfBanksOnEachDevice; -+ pBankInfo->suportedCasLatencies = pDimmInfo->suportedCasLatencies; -+ pBankInfo->refreshInterval = pDimmInfo->refreshInterval; -+ -+ /* DIMM timing parameters */ -+ pBankInfo->minCycleTimeAtMaxCasLatPs = pDimmInfo->minCycleTimeAtMaxCasLatPs; -+ pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps = -+ pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps; -+ pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps = -+ pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps; -+ -+ pBankInfo->minRowPrechargeTime = pDimmInfo->minRowPrechargeTime; -+ pBankInfo->minRowActiveToRowActive = pDimmInfo->minRowActiveToRowActive; -+ pBankInfo->minRasToCasDelay = pDimmInfo->minRasToCasDelay; -+ pBankInfo->minRasPulseWidth = pDimmInfo->minRasPulseWidth; -+ pBankInfo->minWriteRecoveryTime = pDimmInfo->minWriteRecoveryTime; -+ pBankInfo->minWriteToReadCmdDelay = pDimmInfo->minWriteToReadCmdDelay; -+ pBankInfo->minReadToPrechCmdDelay = pDimmInfo->minReadToPrechCmdDelay; -+ pBankInfo->minRefreshToActiveCmd = pDimmInfo->minRefreshToActiveCmd; -+ -+ /* Parameters calculated from the extracted DIMM information */ -+ pBankInfo->size = pDimmInfo->size/pDimmInfo->numOfModuleBanks; -+ pBankInfo->deviceDensity = pDimmInfo->deviceDensity; -+ pBankInfo->numberOfDevices = pDimmInfo->numberOfDevices / -+ pDimmInfo->numOfModuleBanks; -+ -+ /* DIMM attributes (MV_TRUE for yes) */ -+ -+ if ((pDimmInfo->memoryType == MEM_TYPE_SDRAM) || -+ (pDimmInfo->memoryType == MEM_TYPE_DDR1) ) -+ { -+ if (pDimmInfo->dimmAttributes & BIT1) -+ pBankInfo->registeredAddrAndControlInputs = MV_TRUE; -+ else -+ pBankInfo->registeredAddrAndControlInputs = MV_FALSE; -+ } -+ else /* pDimmInfo->memoryType == MEM_TYPE_DDR2 */ -+ { -+ if (pDimmInfo->dimmTypeInfo & (BIT0 | BIT4)) -+ pBankInfo->registeredAddrAndControlInputs = MV_TRUE; -+ else -+ pBankInfo->registeredAddrAndControlInputs = MV_FALSE; -+ } -+ -+ return; -+} -+ -+/******************************************************************************* -+* dimmSpdCpy - Cpy SPD parameters from dimm 0 to dimm 1. -+* -+* DESCRIPTION: -+* Read the DIMM SPD parameters from dimm 0 into dimm 1 SPD. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+MV_STATUS dimmSpdCpy(MV_VOID) -+{ -+ MV_U32 i; -+ MV_U32 spdChecksum; -+ -+ MV_TWSI_SLAVE twsiSlave; -+ MV_U8 data[SPD_SIZE]; -+ -+ /* zero dimmInfo structure */ -+ memset(data, 0, SPD_SIZE); -+ -+ /* read the dimm eeprom */ -+ DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); -+ twsiSlave.slaveAddr.address = MV_BOARD_DIMM0_I2C_ADDR; -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ twsiSlave.offset = 0; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, -+ &twsiSlave, data, SPD_SIZE) ) -+ { -+ DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 0\n")); -+ return MV_FAIL; -+ } -+ DB(puts("DRAM: Reading dimm info succeded.\n")); -+ -+ /* calculate SPD checksum */ -+ spdChecksum = 0; -+ -+ for(i = 0 ; i <= 62 ; i++) -+ { -+ spdChecksum += data[i]; -+ } -+ -+ if ((spdChecksum & 0xff) != data[63]) -+ { -+ DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", -+ (MV_U32)(spdChecksum & 0xff), data[63])); -+ } -+ else -+ { -+ DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); -+ } -+ -+ /* copy the SPD content 1:1 into the DIMM 1 SPD */ -+ twsiSlave.slaveAddr.address = MV_BOARD_DIMM1_I2C_ADDR; -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ twsiSlave.offset = 0; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ for(i = 0 ; i < SPD_SIZE ; i++) -+ { -+ twsiSlave.offset = i; -+ if( MV_OK != mvTwsiWrite (MV_BOARD_DIMM_I2C_CHANNEL, -+ &twsiSlave, &data[i], 1) ) -+ { -+ mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 1 byte %d \n",i); -+ return MV_FAIL; -+ } -+ mvOsDelay(5); -+ } -+ -+ DB(puts("DRAM: Reading dimm info succeded.\n")); -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* dimmSpdGet - Get the SPD parameters. -+* -+* DESCRIPTION: -+* Read the DIMM SPD parameters into given struct parameter. -+* -+* INPUT: -+* dimmNum - DIMM number. See MV_BOARD_DIMM_NUM enumerator. -+* -+* OUTPUT: -+* pDimmInfo - DIMM information structure. -+* -+* RETURN: -+* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo) -+{ -+ MV_U32 i; -+ MV_U32 density = 1; -+ MV_U32 spdChecksum; -+ -+ MV_TWSI_SLAVE twsiSlave; -+ MV_U8 data[SPD_SIZE]; -+ -+ if((NULL == pDimmInfo)|| (dimmNum >= MAX_DIMM_NUM)) -+ { -+ DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); -+ return MV_BAD_PARAM; -+ } -+ -+ /* zero dimmInfo structure */ -+ memset(data, 0, SPD_SIZE); -+ -+ /* read the dimm eeprom */ -+ DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); -+ twsiSlave.slaveAddr.address = (dimmNum == 0) ? -+ MV_BOARD_DIMM0_I2C_ADDR : MV_BOARD_DIMM1_I2C_ADDR; -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ twsiSlave.offset = 0; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, -+ &twsiSlave, data, SPD_SIZE) ) -+ { -+ DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum %d \n", dimmNum)); -+ return MV_FAIL; -+ } -+ DB(puts("DRAM: Reading dimm info succeded.\n")); -+ -+ /* calculate SPD checksum */ -+ spdChecksum = 0; -+ -+ for(i = 0 ; i <= 62 ; i++) -+ { -+ spdChecksum += data[i]; -+ } -+ -+ if ((spdChecksum & 0xff) != data[63]) -+ { -+ DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", -+ (MV_U32)(spdChecksum & 0xff), data[63])); -+ } -+ else -+ { -+ DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); -+ } -+ -+ /* copy the SPD content 1:1 into the dimmInfo structure*/ -+ for(i = 0 ; i < SPD_SIZE ; i++) -+ { -+ pDimmInfo->spdRawData[i] = data[i]; -+ DB(mvOsPrintf("SPD-EEPROM Byte %3d = %3x (%3d)\n",i, data[i], data[i])); -+ } -+ -+ DB(mvOsPrintf("DRAM SPD Information:\n")); -+ -+ /* Memory type (DDR / SDRAM) */ -+ switch (data[DIMM_MEM_TYPE]) -+ { -+ case (DIMM_MEM_TYPE_SDRAM): -+ pDimmInfo->memoryType = MEM_TYPE_SDRAM; -+ DB(mvOsPrintf("DRAM Memeory type SDRAM\n")); -+ break; -+ case (DIMM_MEM_TYPE_DDR1): -+ pDimmInfo->memoryType = MEM_TYPE_DDR1; -+ DB(mvOsPrintf("DRAM Memeory type DDR1\n")); -+ break; -+ case (DIMM_MEM_TYPE_DDR2): -+ pDimmInfo->memoryType = MEM_TYPE_DDR2; -+ DB(mvOsPrintf("DRAM Memeory type DDR2\n")); -+ break; -+ default: -+ mvOsPrintf("ERROR: Undefined memory type!\n"); -+ return MV_ERROR; -+ } -+ -+ -+ /* Number Of Row Addresses */ -+ pDimmInfo->numOfRowAddr = data[DIMM_ROW_NUM]; -+ DB(mvOsPrintf("DRAM numOfRowAddr[3] %d\n",pDimmInfo->numOfRowAddr)); -+ -+ /* Number Of Column Addresses */ -+ pDimmInfo->numOfColAddr = data[DIMM_COL_NUM]; -+ DB(mvOsPrintf("DRAM numOfColAddr[4] %d\n",pDimmInfo->numOfColAddr)); -+ -+ /* Number Of Module Banks */ -+ pDimmInfo->numOfModuleBanks = data[DIMM_MODULE_BANK_NUM]; -+ DB(mvOsPrintf("DRAM numOfModuleBanks[5] 0x%x\n", -+ pDimmInfo->numOfModuleBanks)); -+ -+ /* Number of module banks encoded differently for DDR2 */ -+ if (pDimmInfo->memoryType == MEM_TYPE_DDR2) -+ pDimmInfo->numOfModuleBanks = (pDimmInfo->numOfModuleBanks & 0x7)+1; -+ -+ /* Data Width */ -+ pDimmInfo->dataWidth = data[DIMM_DATA_WIDTH]; -+ DB(mvOsPrintf("DRAM dataWidth[6] 0x%x\n", pDimmInfo->dataWidth)); -+ -+ /* Minimum Cycle Time At Max CasLatancy */ -+ pDimmInfo->minCycleTimeAtMaxCasLatPs = cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS]); -+ -+ /* Error Check Type */ -+ pDimmInfo->errorCheckType = data[DIMM_ERR_CHECK_TYPE]; -+ DB(mvOsPrintf("DRAM errorCheckType[11] 0x%x\n", -+ pDimmInfo->errorCheckType)); -+ -+ /* Refresh Interval */ -+ pDimmInfo->refreshInterval = data[DIMM_REFRESH_INTERVAL]; -+ DB(mvOsPrintf("DRAM refreshInterval[12] 0x%x\n", -+ pDimmInfo->refreshInterval)); -+ -+ /* Sdram Width */ -+ pDimmInfo->sdramWidth = data[DIMM_SDRAM_WIDTH]; -+ DB(mvOsPrintf("DRAM sdramWidth[13] 0x%x\n",pDimmInfo->sdramWidth)); -+ -+ /* Error Check Data Width */ -+ pDimmInfo->errorCheckDataWidth = data[DIMM_ERR_CHECK_DATA_WIDTH]; -+ DB(mvOsPrintf("DRAM errorCheckDataWidth[14] 0x%x\n", -+ pDimmInfo->errorCheckDataWidth)); -+ -+ /* Burst Length Supported */ -+ /* SDRAM/DDR1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * -+ *********************************************************/ -+ /* DDR2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * -+ *********************************************************/ -+ -+ pDimmInfo->burstLengthSupported = data[DIMM_BURST_LEN_SUP]; -+ DB(mvOsPrintf("DRAM burstLengthSupported[16] 0x%x\n", -+ pDimmInfo->burstLengthSupported)); -+ -+ /* Number Of Banks On Each Device */ -+ pDimmInfo->numOfBanksOnEachDevice = data[DIMM_DEV_BANK_NUM]; -+ DB(mvOsPrintf("DRAM numOfBanksOnEachDevice[17] 0x%x\n", -+ pDimmInfo->numOfBanksOnEachDevice)); -+ -+ /* Suported Cas Latencies */ -+ -+ /* SDRAM: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * -+ ********************************************************/ -+ -+ /* DDR 1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * -+ *********************************************************/ -+ -+ /* DDR 2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * -+ *********************************************************/ -+ -+ pDimmInfo->suportedCasLatencies = data[DIMM_SUP_CAL]; -+ DB(mvOsPrintf("DRAM suportedCasLatencies[18] 0x%x\n", -+ pDimmInfo->suportedCasLatencies)); -+ -+ /* For DDR2 only, get the DIMM type information */ -+ if (pDimmInfo->memoryType == MEM_TYPE_DDR2) -+ { -+ pDimmInfo->dimmTypeInfo = data[DIMM_DDR2_TYPE_INFORMATION]; -+ DB(mvOsPrintf("DRAM dimmTypeInfo[20] (DDR2) 0x%x\n", -+ pDimmInfo->dimmTypeInfo)); -+ } -+ -+ /* SDRAM Modules Attributes */ -+ pDimmInfo->dimmAttributes = data[DIMM_BUF_ADDR_CONT_IN]; -+ DB(mvOsPrintf("DRAM dimmAttributes[21] 0x%x\n", -+ pDimmInfo->dimmAttributes)); -+ -+ /* Minimum Cycle Time At Max CasLatancy Minus 1*/ -+ pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps = -+ cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS1]); -+ -+ /* Minimum Cycle Time At Max CasLatancy Minus 2*/ -+ pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps = -+ cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS2]); -+ -+ pDimmInfo->minRowPrechargeTime = data[DIMM_MIN_ROW_PRECHARGE_TIME]; -+ DB(mvOsPrintf("DRAM minRowPrechargeTime[27] 0x%x\n", -+ pDimmInfo->minRowPrechargeTime)); -+ pDimmInfo->minRowActiveToRowActive = data[DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE]; -+ DB(mvOsPrintf("DRAM minRowActiveToRowActive[28] 0x%x\n", -+ pDimmInfo->minRowActiveToRowActive)); -+ pDimmInfo->minRasToCasDelay = data[DIMM_MIN_RAS_TO_CAS_DELAY]; -+ DB(mvOsPrintf("DRAM minRasToCasDelay[29] 0x%x\n", -+ pDimmInfo->minRasToCasDelay)); -+ pDimmInfo->minRasPulseWidth = data[DIMM_MIN_RAS_PULSE_WIDTH]; -+ DB(mvOsPrintf("DRAM minRasPulseWidth[30] 0x%x\n", -+ pDimmInfo->minRasPulseWidth)); -+ -+ /* DIMM Bank Density */ -+ pDimmInfo->dimmBankDensity = data[DIMM_BANK_DENSITY]; -+ DB(mvOsPrintf("DRAM dimmBankDensity[31] 0x%x\n", -+ pDimmInfo->dimmBankDensity)); -+ -+ /* Only DDR2 includes Write Recovery Time field. Other SDRAM ignore */ -+ pDimmInfo->minWriteRecoveryTime = data[DIMM_MIN_WRITE_RECOVERY_TIME]; -+ DB(mvOsPrintf("DRAM minWriteRecoveryTime[36] 0x%x\n", -+ pDimmInfo->minWriteRecoveryTime)); -+ -+ /* Only DDR2 includes Internal Write To Read Command Delay field. */ -+ pDimmInfo->minWriteToReadCmdDelay = data[DIMM_MIN_WRITE_TO_READ_CMD_DELAY]; -+ DB(mvOsPrintf("DRAM minWriteToReadCmdDelay[37] 0x%x\n", -+ pDimmInfo->minWriteToReadCmdDelay)); -+ -+ /* Only DDR2 includes Internal Read To Precharge Command Delay field. */ -+ pDimmInfo->minReadToPrechCmdDelay = data[DIMM_MIN_READ_TO_PRECH_CMD_DELAY]; -+ DB(mvOsPrintf("DRAM minReadToPrechCmdDelay[38] 0x%x\n", -+ pDimmInfo->minReadToPrechCmdDelay)); -+ -+ /* Only DDR2 includes Minimum Refresh to Activate/Refresh Command field */ -+ pDimmInfo->minRefreshToActiveCmd = data[DIMM_MIN_REFRESH_TO_ACTIVATE_CMD]; -+ DB(mvOsPrintf("DRAM minRefreshToActiveCmd[42] 0x%x\n", -+ pDimmInfo->minRefreshToActiveCmd)); -+ -+ /* calculating the sdram density. Representing device density from */ -+ /* bit 20 to allow representation of 4GB and above. */ -+ /* For example, if density is 512Mbit 0x20000000, will be represent in */ -+ /* deviceDensity by 0x20000000 >> 16 --> 0x00000200. Another example */ -+ /* is density 8GB 0x200000000 >> 16 --> 0x00002000. */ -+ density = (1 << ((pDimmInfo->numOfRowAddr + pDimmInfo->numOfColAddr) - 20)); -+ pDimmInfo->deviceDensity = density * -+ pDimmInfo->numOfBanksOnEachDevice * -+ pDimmInfo->sdramWidth; -+ DB(mvOsPrintf("DRAM deviceDensity %d\n",pDimmInfo->deviceDensity)); -+ -+ /* Number of devices includeing Error correction */ -+ pDimmInfo->numberOfDevices = (pDimmInfo->dataWidth/pDimmInfo->sdramWidth) * -+ pDimmInfo->numOfModuleBanks; -+ DB(mvOsPrintf("DRAM numberOfDevices %d\n", -+ pDimmInfo->numberOfDevices)); -+ -+ pDimmInfo->size = 0; -+ -+ /* Note that pDimmInfo->size is in MB units */ -+ if (pDimmInfo->memoryType == MEM_TYPE_SDRAM) -+ { -+ if (pDimmInfo->dimmBankDensity & BIT0) -+ pDimmInfo->size += 1024; /* Equal to 1GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT1) -+ pDimmInfo->size += 8; /* Equal to 8MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT2) -+ pDimmInfo->size += 16; /* Equal to 16MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT3) -+ pDimmInfo->size += 32; /* Equal to 32MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT4) -+ pDimmInfo->size += 64; /* Equal to 64MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT5) -+ pDimmInfo->size += 128; /* Equal to 128MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT6) -+ pDimmInfo->size += 256; /* Equal to 256MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT7) -+ pDimmInfo->size += 512; /* Equal to 512MB */ -+ } -+ else if (pDimmInfo->memoryType == MEM_TYPE_DDR1) -+ { -+ if (pDimmInfo->dimmBankDensity & BIT0) -+ pDimmInfo->size += 1024; /* Equal to 1GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT1) -+ pDimmInfo->size += 2048; /* Equal to 2GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT2) -+ pDimmInfo->size += 16; /* Equal to 16MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT3) -+ pDimmInfo->size += 32; /* Equal to 32MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT4) -+ pDimmInfo->size += 64; /* Equal to 64MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT5) -+ pDimmInfo->size += 128; /* Equal to 128MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT6) -+ pDimmInfo->size += 256; /* Equal to 256MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT7) -+ pDimmInfo->size += 512; /* Equal to 512MB */ -+ } -+ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ -+ { -+ if (pDimmInfo->dimmBankDensity & BIT0) -+ pDimmInfo->size += 1024; /* Equal to 1GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT1) -+ pDimmInfo->size += 2048; /* Equal to 2GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT2) -+ pDimmInfo->size += 4096; /* Equal to 4GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT3) -+ pDimmInfo->size += 8192; /* Equal to 8GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT4) -+ pDimmInfo->size += 16384; /* Equal to 16GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT5) -+ pDimmInfo->size += 128; /* Equal to 128MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT6) -+ pDimmInfo->size += 256; /* Equal to 256MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT7) -+ pDimmInfo->size += 512; /* Equal to 512MB */ -+ } -+ -+ pDimmInfo->size *= pDimmInfo->numOfModuleBanks; -+ -+ DB(mvOsPrintf("Dram: dimm size %dMB \n",pDimmInfo->size)); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* dimmSpdPrint - Print the SPD parameters. -+* -+* DESCRIPTION: -+* Print the Dimm SPD parameters. -+* -+* INPUT: -+* pDimmInfo - DIMM information structure. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID dimmSpdPrint(MV_U32 dimmNum) -+{ -+ MV_DIMM_INFO dimmInfo; -+ MV_U32 i, temp = 0; -+ MV_U32 k, maskLeftOfPoint = 0, maskRightOfPoint = 0; -+ MV_U32 rightOfPoint = 0,leftOfPoint = 0, div, time_tmp, shift; -+ MV_U32 busClkPs; -+ MV_U8 trp_clocks=0, trcd_clocks, tras_clocks, trrd_clocks, -+ temp_buf[40], *spdRawData; -+ -+ busClkPs = 1000000000 / (mvBoardSysClkGet() / 100); /* in 10 ps units */ -+ -+ spdRawData = dimmInfo.spdRawData; -+ -+ if(MV_OK != dimmSpdGet(dimmNum, &dimmInfo)) -+ { -+ mvOsOutput("ERROR: Could not read SPD information!\n"); -+ return; -+ } -+ -+ /* find Manufactura of Dimm Module */ -+ mvOsOutput("\nManufacturer's JEDEC ID Code: "); -+ for(i = 0 ; i < DIMM_MODULE_MANU_SIZE ; i++) -+ { -+ mvOsOutput("%x",spdRawData[DIMM_MODULE_MANU_OFFS + i]); -+ } -+ mvOsOutput("\n"); -+ -+ /* Manufacturer's Specific Data */ -+ for(i = 0 ; i < DIMM_MODULE_ID_SIZE ; i++) -+ { -+ temp_buf[i] = spdRawData[DIMM_MODULE_ID_OFFS + i]; -+ } -+ mvOsOutput("Manufacturer's Specific Data: %s\n", temp_buf); -+ -+ /* Module Part Number */ -+ for(i = 0 ; i < DIMM_MODULE_VEN_SIZE ; i++) -+ { -+ temp_buf[i] = spdRawData[DIMM_MODULE_VEN_OFFS + i]; -+ } -+ mvOsOutput("Module Part Number: %s\n", temp_buf); -+ -+ /* Module Serial Number */ -+ for(i = 0; i < sizeof(MV_U32); i++) -+ { -+ temp |= spdRawData[95+i] << 8*i; -+ } -+ mvOsOutput("DIMM Serial No. %ld (%lx)\n", (long)temp, -+ (long)temp); -+ -+ /* find Manufac-Data of Dimm Module */ -+ mvOsOutput("Manufactoring Date: Year 20%d%d/ ww %d%d\n", -+ ((spdRawData[93] & 0xf0) >> 4), (spdRawData[93] & 0xf), -+ ((spdRawData[94] & 0xf0) >> 4), (spdRawData[94] & 0xf)); -+ /* find modul_revision of Dimm Module */ -+ mvOsOutput("Module Revision: %d.%d\n", -+ spdRawData[91], spdRawData[92]); -+ -+ /* find manufac_place of Dimm Module */ -+ mvOsOutput("manufac_place: %d\n", spdRawData[72]); -+ -+ /* go over the first 35 I2C data bytes */ -+ for(i = 2 ; i <= 35 ; i++) -+ switch(i) -+ { -+ case 2: /* Memory type (DDR1/2 / SDRAM) */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ mvOsOutput("Dram Type is: SDRAM\n"); -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ mvOsOutput("Dram Type is: SDRAM DDR1\n"); -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) -+ mvOsOutput("Dram Type is: SDRAM DDR2\n"); -+ else -+ mvOsOutput("Dram Type unknown\n"); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 3: /* Number Of Row Addresses */ -+ mvOsOutput("Module Number of row addresses: %d\n", -+ dimmInfo.numOfRowAddr); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 4: /* Number Of Column Addresses */ -+ mvOsOutput("Module Number of col addresses: %d\n", -+ dimmInfo.numOfColAddr); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 5: /* Number Of Module Banks */ -+ mvOsOutput("Number of Banks on Mod.: %d\n", -+ dimmInfo.numOfModuleBanks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 6: /* Data Width */ -+ mvOsOutput("Module Data Width: %d bit\n", -+ dimmInfo.dataWidth); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 8: /* Voltage Interface */ -+ switch(spdRawData[i]) -+ { -+ case 0x0: -+ mvOsOutput("Module is TTL_5V_TOLERANT\n"); -+ break; -+ case 0x1: -+ mvOsOutput("Module is LVTTL\n"); -+ break; -+ case 0x2: -+ mvOsOutput("Module is HSTL_1_5V\n"); -+ break; -+ case 0x3: -+ mvOsOutput("Module is SSTL_3_3V\n"); -+ break; -+ case 0x4: -+ mvOsOutput("Module is SSTL_2_5V\n"); -+ break; -+ case 0x5: -+ if (dimmInfo.memoryType != MEM_TYPE_SDRAM) -+ { -+ mvOsOutput("Module is SSTL_1_8V\n"); -+ break; -+ } -+ default: -+ mvOsOutput("Module is VOLTAGE_UNKNOWN\n"); -+ break; -+ } -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 9: /* Minimum Cycle Time At Max CasLatancy */ -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ rightOfPoint = (spdRawData[i] & 0x0f) * 10; -+ -+ /* DDR2 addition of right of point */ -+ if ((spdRawData[i] & 0x0f) == 0xA) -+ { -+ rightOfPoint = 25; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xB) -+ { -+ rightOfPoint = 33; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xC) -+ { -+ rightOfPoint = 66; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xD) -+ { -+ rightOfPoint = 75; -+ } -+ mvOsOutput("Minimum Cycle Time At Max CL: %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 10: /* Clock To Data Out */ -+ div = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 10:100; -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / div; -+ rightOfPoint = time_tmp % div; -+ mvOsOutput("Clock To Data Out: %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 11: /* Error Check Type */ -+ mvOsOutput("Error Check Type (0=NONE): %d\n", -+ dimmInfo.errorCheckType); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 12: /* Refresh Interval */ -+ mvOsOutput("Refresh Rate: %x\n", -+ dimmInfo.refreshInterval); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 13: /* Sdram Width */ -+ mvOsOutput("Sdram Width: %d bits\n", -+ dimmInfo.sdramWidth); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 14: /* Error Check Data Width */ -+ mvOsOutput("Error Check Data Width: %d bits\n", -+ dimmInfo.errorCheckDataWidth); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 15: /* Minimum Clock Delay is unsupported */ -+ if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || -+ (dimmInfo.memoryType == MEM_TYPE_DDR1)) -+ { -+ mvOsOutput("Minimum Clk Delay back to back: %d\n", -+ spdRawData[i]); -+ } -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 16: /* Burst Length Supported */ -+ /* SDRAM/DDR1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * -+ *********************************************************/ -+ /* DDR2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * -+ *********************************************************/ -+ mvOsOutput("Burst Length Supported: "); -+ if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || -+ (dimmInfo.memoryType == MEM_TYPE_DDR1)) -+ { -+ if (dimmInfo.burstLengthSupported & BIT0) -+ mvOsOutput("1, "); -+ if (dimmInfo.burstLengthSupported & BIT1) -+ mvOsOutput("2, "); -+ } -+ if (dimmInfo.burstLengthSupported & BIT2) -+ mvOsOutput("4, "); -+ if (dimmInfo.burstLengthSupported & BIT3) -+ mvOsOutput("8, "); -+ -+ mvOsOutput(" Bit \n"); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 17: /* Number Of Banks On Each Device */ -+ mvOsOutput("Number Of Banks On Each Chip: %d\n", -+ dimmInfo.numOfBanksOnEachDevice); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 18: /* Suported Cas Latencies */ -+ -+ /* SDRAM: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * -+ ********************************************************/ -+ -+ /* DDR 1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * -+ *********************************************************/ -+ -+ /* DDR 2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * -+ *********************************************************/ -+ -+ mvOsOutput("Suported Cas Latencies: (CL) "); -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ for (k = 0; k <=7; k++) -+ { -+ if (dimmInfo.suportedCasLatencies & (1 << k)) -+ mvOsOutput("%d, ", k+1); -+ } -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ { -+ if (dimmInfo.suportedCasLatencies & BIT0) -+ mvOsOutput("1, "); -+ if (dimmInfo.suportedCasLatencies & BIT1) -+ mvOsOutput("1.5, "); -+ if (dimmInfo.suportedCasLatencies & BIT2) -+ mvOsOutput("2, "); -+ if (dimmInfo.suportedCasLatencies & BIT3) -+ mvOsOutput("2.5, "); -+ if (dimmInfo.suportedCasLatencies & BIT4) -+ mvOsOutput("3, "); -+ if (dimmInfo.suportedCasLatencies & BIT5) -+ mvOsOutput("3.5, "); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) -+ { -+ if (dimmInfo.suportedCasLatencies & BIT2) -+ mvOsOutput("2, "); -+ if (dimmInfo.suportedCasLatencies & BIT3) -+ mvOsOutput("3, "); -+ if (dimmInfo.suportedCasLatencies & BIT4) -+ mvOsOutput("4, "); -+ if (dimmInfo.suportedCasLatencies & BIT5) -+ mvOsOutput("5, "); -+ } -+ else -+ mvOsOutput("?.?, "); -+ mvOsOutput("\n"); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 20: /* DDR2 DIMM type info */ -+ if (dimmInfo.memoryType == MEM_TYPE_DDR2) -+ { -+ if (dimmInfo.dimmTypeInfo & (BIT0 | BIT4)) -+ mvOsOutput("Registered DIMM (RDIMM)\n"); -+ else if (dimmInfo.dimmTypeInfo & (BIT1 | BIT5)) -+ mvOsOutput("Unbuffered DIMM (UDIMM)\n"); -+ else -+ mvOsOutput("Unknown DIMM type.\n"); -+ } -+ -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 21: /* SDRAM Modules Attributes */ -+ mvOsOutput("\nModule Attributes (SPD Byte 21): \n"); -+ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ if (dimmInfo.dimmAttributes & BIT0) -+ mvOsOutput(" Buffered Addr/Control Input: Yes\n"); -+ else -+ mvOsOutput(" Buffered Addr/Control Input: No\n"); -+ -+ if (dimmInfo.dimmAttributes & BIT1) -+ mvOsOutput(" Registered Addr/Control Input: Yes\n"); -+ else -+ mvOsOutput(" Registered Addr/Control Input: No\n"); -+ -+ if (dimmInfo.dimmAttributes & BIT2) -+ mvOsOutput(" On-Card PLL (clock): Yes \n"); -+ else -+ mvOsOutput(" On-Card PLL (clock): No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT3) -+ mvOsOutput(" Bufferd DQMB Input: Yes \n"); -+ else -+ mvOsOutput(" Bufferd DQMB Inputs: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT4) -+ mvOsOutput(" Registered DQMB Inputs: Yes \n"); -+ else -+ mvOsOutput(" Registered DQMB Inputs: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT5) -+ mvOsOutput(" Differential Clock Input: Yes \n"); -+ else -+ mvOsOutput(" Differential Clock Input: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT6) -+ mvOsOutput(" redundant Row Addressing: Yes \n"); -+ else -+ mvOsOutput(" redundant Row Addressing: No \n"); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ { -+ if (dimmInfo.dimmAttributes & BIT0) -+ mvOsOutput(" Buffered Addr/Control Input: Yes\n"); -+ else -+ mvOsOutput(" Buffered Addr/Control Input: No\n"); -+ -+ if (dimmInfo.dimmAttributes & BIT1) -+ mvOsOutput(" Registered Addr/Control Input: Yes\n"); -+ else -+ mvOsOutput(" Registered Addr/Control Input: No\n"); -+ -+ if (dimmInfo.dimmAttributes & BIT2) -+ mvOsOutput(" On-Card PLL (clock): Yes \n"); -+ else -+ mvOsOutput(" On-Card PLL (clock): No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT3) -+ mvOsOutput(" FET Switch On-Card Enabled: Yes \n"); -+ else -+ mvOsOutput(" FET Switch On-Card Enabled: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT4) -+ mvOsOutput(" FET Switch External Enabled: Yes \n"); -+ else -+ mvOsOutput(" FET Switch External Enabled: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT5) -+ mvOsOutput(" Differential Clock Input: Yes \n"); -+ else -+ mvOsOutput(" Differential Clock Input: No \n"); -+ } -+ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ -+ { -+ mvOsOutput(" Number of Active Registers on the DIMM: %d\n", -+ (dimmInfo.dimmAttributes & 0x3) + 1); -+ -+ mvOsOutput(" Number of PLLs on the DIMM: %d\n", -+ ((dimmInfo.dimmAttributes) >> 2) & 0x3); -+ -+ if (dimmInfo.dimmAttributes & BIT4) -+ mvOsOutput(" FET Switch External Enabled: Yes \n"); -+ else -+ mvOsOutput(" FET Switch External Enabled: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT6) -+ mvOsOutput(" Analysis probe installed: Yes \n"); -+ else -+ mvOsOutput(" Analysis probe installed: No \n"); -+ } -+ -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 22: /* Suported AutoPreCharge */ -+ mvOsOutput("\nModul Attributes (SPD Byte 22): \n"); -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ if ( spdRawData[i] & BIT0 ) -+ mvOsOutput(" Early Ras Precharge: Yes \n"); -+ else -+ mvOsOutput(" Early Ras Precharge: No \n"); -+ -+ if ( spdRawData[i] & BIT1 ) -+ mvOsOutput(" AutoPreCharge: Yes \n"); -+ else -+ mvOsOutput(" AutoPreCharge: No \n"); -+ -+ if ( spdRawData[i] & BIT2 ) -+ mvOsOutput(" Precharge All: Yes \n"); -+ else -+ mvOsOutput(" Precharge All: No \n"); -+ -+ if ( spdRawData[i] & BIT3 ) -+ mvOsOutput(" Write 1/ReadBurst: Yes \n"); -+ else -+ mvOsOutput(" Write 1/ReadBurst: No \n"); -+ -+ if ( spdRawData[i] & BIT4 ) -+ mvOsOutput(" lower VCC tolerance: 5%%\n"); -+ else -+ mvOsOutput(" lower VCC tolerance: 10%%\n"); -+ -+ if ( spdRawData[i] & BIT5 ) -+ mvOsOutput(" upper VCC tolerance: 5%%\n"); -+ else -+ mvOsOutput(" upper VCC tolerance: 10%%\n"); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ { -+ if ( spdRawData[i] & BIT0 ) -+ mvOsOutput(" Supports Weak Driver: Yes \n"); -+ else -+ mvOsOutput(" Supports Weak Driver: No \n"); -+ -+ if ( !(spdRawData[i] & BIT4) ) -+ mvOsOutput(" lower VCC tolerance: 0.2V\n"); -+ -+ if ( !(spdRawData[i] & BIT5) ) -+ mvOsOutput(" upper VCC tolerance: 0.2V\n"); -+ -+ if ( spdRawData[i] & BIT6 ) -+ mvOsOutput(" Concurrent Auto Preharge: Yes \n"); -+ else -+ mvOsOutput(" Concurrent Auto Preharge: No \n"); -+ -+ if ( spdRawData[i] & BIT7 ) -+ mvOsOutput(" Supports Fast AP: Yes \n"); -+ else -+ mvOsOutput(" Supports Fast AP: No \n"); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) -+ { -+ if ( spdRawData[i] & BIT0 ) -+ mvOsOutput(" Supports Weak Driver: Yes \n"); -+ else -+ mvOsOutput(" Supports Weak Driver: No \n"); -+ } -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 23: -+ /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */ -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ rightOfPoint = (spdRawData[i] & 0x0f) * 10; -+ -+ /* DDR2 addition of right of point */ -+ if ((spdRawData[i] & 0x0f) == 0xA) -+ { -+ rightOfPoint = 25; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xB) -+ { -+ rightOfPoint = 33; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xC) -+ { -+ rightOfPoint = 66; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xD) -+ { -+ rightOfPoint = 75; -+ } -+ -+ mvOsOutput("Minimum Cycle Time At 2nd highest CasLatancy" -+ "(0 = Not supported): %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint ); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 24: /* Clock To Data Out 2nd highest Cas Latency Value*/ -+ div = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? 10:100; -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / div; -+ rightOfPoint = time_tmp % div; -+ mvOsOutput("Clock To Data Out (2nd CL value): %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 25: -+ /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ leftOfPoint = (spdRawData[i] & 0xfc) >> 2; -+ rightOfPoint = (spdRawData[i] & 0x3) * 25; -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ rightOfPoint = (spdRawData[i] & 0x0f) * 10; -+ -+ /* DDR2 addition of right of point */ -+ if ((spdRawData[i] & 0x0f) == 0xA) -+ { -+ rightOfPoint = 25; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xB) -+ { -+ rightOfPoint = 33; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xC) -+ { -+ rightOfPoint = 66; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xD) -+ { -+ rightOfPoint = 75; -+ } -+ } -+ mvOsOutput("Minimum Cycle Time At 3rd highest CasLatancy" -+ "(0 = Not supported): %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint ); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 26: /* Clock To Data Out 3rd highest Cas Latency Value*/ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ leftOfPoint = (spdRawData[i] & 0xfc) >> 2; -+ rightOfPoint = (spdRawData[i] & 0x3) * 25; -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = 0; -+ rightOfPoint = time_tmp; -+ } -+ mvOsOutput("Clock To Data Out (3rd CL value): %d.%2d[ns]\n", -+ leftOfPoint, rightOfPoint ); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 27: /* Minimum Row Precharge Time */ -+ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; -+ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0xff : 0xfc; -+ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0x00 : 0x03; -+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); -+ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; -+ temp = ((leftOfPoint*100) + rightOfPoint);/* in 10ps Intervals*/ -+ trp_clocks = (temp + (busClkPs-1)) / busClkPs; -+ mvOsOutput("Minimum Row Precharge Time [ns]: %d.%d = " -+ "in Clk cycles %d\n", -+ leftOfPoint, rightOfPoint, trp_clocks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 28: /* Minimum Row Active to Row Active Time */ -+ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; -+ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0xff : 0xfc; -+ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0x00 : 0x03; -+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); -+ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; -+ temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ -+ trrd_clocks = (temp + (busClkPs-1)) / busClkPs; -+ mvOsOutput("Minimum Row Active -To- Row Active Delay [ns]: " -+ "%d.%d = in Clk cycles %d\n", -+ leftOfPoint, rightOfPoint, trp_clocks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 29: /* Minimum Ras-To-Cas Delay */ -+ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; -+ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0xff : 0xfc; -+ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0x00 : 0x03; -+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); -+ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; -+ temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ -+ trcd_clocks = (temp + (busClkPs-1) )/ busClkPs; -+ mvOsOutput("Minimum Ras-To-Cas Delay [ns]: %d.%d = " -+ "in Clk cycles %d\n", -+ leftOfPoint, rightOfPoint, trp_clocks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 30: /* Minimum Ras Pulse Width */ -+ tras_clocks = (cas2ps(spdRawData[i])+(busClkPs-1)) / busClkPs; -+ mvOsOutput("Minimum Ras Pulse Width [ns]: %d = " -+ "in Clk cycles %d\n", spdRawData[i], tras_clocks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 31: /* Module Bank Density */ -+ mvOsOutput("Module Bank Density (more than 1= Multisize-Module):"); -+ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ if (dimmInfo.dimmBankDensity & BIT0) -+ mvOsOutput("1GB, "); -+ if (dimmInfo.dimmBankDensity & BIT1) -+ mvOsOutput("8MB, "); -+ if (dimmInfo.dimmBankDensity & BIT2) -+ mvOsOutput("16MB, "); -+ if (dimmInfo.dimmBankDensity & BIT3) -+ mvOsOutput("32MB, "); -+ if (dimmInfo.dimmBankDensity & BIT4) -+ mvOsOutput("64MB, "); -+ if (dimmInfo.dimmBankDensity & BIT5) -+ mvOsOutput("128MB, "); -+ if (dimmInfo.dimmBankDensity & BIT6) -+ mvOsOutput("256MB, "); -+ if (dimmInfo.dimmBankDensity & BIT7) -+ mvOsOutput("512MB, "); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ { -+ if (dimmInfo.dimmBankDensity & BIT0) -+ mvOsOutput("1GB, "); -+ if (dimmInfo.dimmBankDensity & BIT1) -+ mvOsOutput("2GB, "); -+ if (dimmInfo.dimmBankDensity & BIT2) -+ mvOsOutput("16MB, "); -+ if (dimmInfo.dimmBankDensity & BIT3) -+ mvOsOutput("32MB, "); -+ if (dimmInfo.dimmBankDensity & BIT4) -+ mvOsOutput("64MB, "); -+ if (dimmInfo.dimmBankDensity & BIT5) -+ mvOsOutput("128MB, "); -+ if (dimmInfo.dimmBankDensity & BIT6) -+ mvOsOutput("256MB, "); -+ if (dimmInfo.dimmBankDensity & BIT7) -+ mvOsOutput("512MB, "); -+ } -+ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ -+ { -+ if (dimmInfo.dimmBankDensity & BIT0) -+ mvOsOutput("1GB, "); -+ if (dimmInfo.dimmBankDensity & BIT1) -+ mvOsOutput("2GB, "); -+ if (dimmInfo.dimmBankDensity & BIT2) -+ mvOsOutput("4GB, "); -+ if (dimmInfo.dimmBankDensity & BIT3) -+ mvOsOutput("8GB, "); -+ if (dimmInfo.dimmBankDensity & BIT4) -+ mvOsOutput("16GB, "); -+ if (dimmInfo.dimmBankDensity & BIT5) -+ mvOsOutput("128MB, "); -+ if (dimmInfo.dimmBankDensity & BIT6) -+ mvOsOutput("256MB, "); -+ if (dimmInfo.dimmBankDensity & BIT7) -+ mvOsOutput("512MB, "); -+ } -+ mvOsOutput("\n"); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 32: /* Address And Command Setup Time (measured in ns/1000) */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ rightOfPoint = (spdRawData[i] & 0x0f); -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ if(leftOfPoint > 7) -+ { -+ leftOfPoint *= -1; -+ } -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / 100; -+ rightOfPoint = time_tmp % 100; -+ } -+ mvOsOutput("Address And Command Setup Time [ns]: %d.%d\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 33: /* Address And Command Hold Time */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ rightOfPoint = (spdRawData[i] & 0x0f); -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ if(leftOfPoint > 7) -+ { -+ leftOfPoint *= -1; -+ } -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / 100; -+ rightOfPoint = time_tmp % 100; -+ } -+ mvOsOutput("Address And Command Hold Time [ns]: %d.%d\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 34: /* Data Input Setup Time */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ rightOfPoint = (spdRawData[i] & 0x0f); -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ if(leftOfPoint > 7) -+ { -+ leftOfPoint *= -1; -+ } -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / 100; -+ rightOfPoint = time_tmp % 100; -+ } -+ mvOsOutput("Data Input Setup Time [ns]: %d.%d\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 35: /* Data Input Hold Time */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ rightOfPoint = (spdRawData[i] & 0x0f); -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ if(leftOfPoint > 7) -+ { -+ leftOfPoint *= -1; -+ } -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / 100; -+ rightOfPoint = time_tmp % 100; -+ } -+ mvOsOutput("Data Input Hold Time [ns]: %d.%d\n\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 36: /* Relevant for DDR2 only: Write Recovery Time */ -+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> 2); -+ rightOfPoint = (spdRawData[i] & maskRightOfPoint) * 25; -+ mvOsOutput("Write Recovery Time [ns]: %d.%d\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ } -+ -+} -+ -+ -+/* -+ * translate ns.ns/10 coding of SPD timing values -+ * into ps unit values -+ */ -+/******************************************************************************* -+* cas2ps - Translate x.y ns parameter to pico-seconds values -+* -+* DESCRIPTION: -+* This function translates x.y nano seconds to its value in pico seconds. -+* For example 3.75ns will return 3750. -+* -+* INPUT: -+* spd_byte - DIMM SPD byte. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* value in pico seconds. -+* -+*******************************************************************************/ -+static MV_U32 cas2ps(MV_U8 spd_byte) -+{ -+ MV_U32 ns, ns10; -+ -+ /* isolate upper nibble */ -+ ns = (spd_byte >> 4) & 0x0F; -+ /* isolate lower nibble */ -+ ns10 = (spd_byte & 0x0F); -+ -+ if( ns10 < 10 ) { -+ ns10 *= 10; -+ } -+ else if( ns10 == 10 ) -+ ns10 = 25; -+ else if( ns10 == 11 ) -+ ns10 = 33; -+ else if( ns10 == 12 ) -+ ns10 = 66; -+ else if( ns10 == 13 ) -+ ns10 = 75; -+ else -+ { -+ mvOsOutput("cas2ps Err. unsupported cycle time.\n"); -+ } -+ -+ return (ns*1000 + ns10*10); -+} -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h 2010-11-09 20:28:10.622495522 +0100 -@@ -0,0 +1,191 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvDram -+#define __INCmvDram -+ -+#include "ddr1_2/mvDramIf.h" -+#include "twsi/mvTwsi.h" -+ -+#define MAX_DIMM_NUM 2 -+#define SPD_SIZE 128 -+ -+/* Dimm spd offsets */ -+#define DIMM_MEM_TYPE 2 -+#define DIMM_ROW_NUM 3 -+#define DIMM_COL_NUM 4 -+#define DIMM_MODULE_BANK_NUM 5 -+#define DIMM_DATA_WIDTH 6 -+#define DIMM_VOLT_IF 8 -+#define DIMM_MIN_CC_AT_MAX_CAS 9 -+#define DIMM_ERR_CHECK_TYPE 11 -+#define DIMM_REFRESH_INTERVAL 12 -+#define DIMM_SDRAM_WIDTH 13 -+#define DIMM_ERR_CHECK_DATA_WIDTH 14 -+#define DIMM_MIN_CLK_DEL 15 -+#define DIMM_BURST_LEN_SUP 16 -+#define DIMM_DEV_BANK_NUM 17 -+#define DIMM_SUP_CAL 18 -+#define DIMM_DDR2_TYPE_INFORMATION 20 /* DDR2 only */ -+#define DIMM_BUF_ADDR_CONT_IN 21 -+#define DIMM_MIN_CC_AT_MAX_CAS_MINUS1 23 -+#define DIMM_MIN_CC_AT_MAX_CAS_MINUS2 25 -+#define DIMM_MIN_ROW_PRECHARGE_TIME 27 -+#define DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE 28 -+#define DIMM_MIN_RAS_TO_CAS_DELAY 29 -+#define DIMM_MIN_RAS_PULSE_WIDTH 30 -+#define DIMM_BANK_DENSITY 31 -+#define DIMM_MIN_WRITE_RECOVERY_TIME 36 -+#define DIMM_MIN_WRITE_TO_READ_CMD_DELAY 37 -+#define DIMM_MIN_READ_TO_PRECH_CMD_DELAY 38 -+#define DIMM_MIN_REFRESH_TO_ACTIVATE_CMD 42 -+ -+/* Dimm Memory Type values */ -+#define DIMM_MEM_TYPE_SDRAM 0x4 -+#define DIMM_MEM_TYPE_DDR1 0x7 -+#define DIMM_MEM_TYPE_DDR2 0x8 -+ -+#define DIMM_MODULE_MANU_OFFS 64 -+#define DIMM_MODULE_MANU_SIZE 8 -+#define DIMM_MODULE_VEN_OFFS 73 -+#define DIMM_MODULE_VEN_SIZE 25 -+#define DIMM_MODULE_ID_OFFS 99 -+#define DIMM_MODULE_ID_SIZE 18 -+ -+/* enumeration for voltage levels. */ -+typedef enum _mvDimmVoltageIf -+{ -+ TTL_5V_TOLERANT, -+ LVTTL, -+ HSTL_1_5V, -+ SSTL_3_3V, -+ SSTL_2_5V, -+ VOLTAGE_UNKNOWN, -+} MV_DIMM_VOLTAGE_IF; -+ -+ -+/* enumaration for SDRAM CAS Latencies. */ -+typedef enum _mvDimmSdramCas -+{ -+ SD_CL_1 =1, -+ SD_CL_2, -+ SD_CL_3, -+ SD_CL_4, -+ SD_CL_5, -+ SD_CL_6, -+ SD_CL_7, -+ SD_FAULT -+}MV_DIMM_SDRAM_CAS; -+ -+ -+/* DIMM information structure */ -+typedef struct _mvDimmInfo -+{ -+ MV_MEMORY_TYPE memoryType; /* DDR or SDRAM */ -+ -+ MV_U8 spdRawData[SPD_SIZE]; /* Content of SPD-EEPROM copied 1:1 */ -+ -+ /* DIMM dimensions */ -+ MV_U32 numOfRowAddr; -+ MV_U32 numOfColAddr; -+ MV_U32 numOfModuleBanks; -+ MV_U32 dataWidth; -+ MV_U32 errorCheckType; /* ECC , PARITY..*/ -+ MV_U32 sdramWidth; /* 4,8,16 or 32 */ -+ MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ -+ MV_U32 burstLengthSupported; -+ MV_U32 numOfBanksOnEachDevice; -+ MV_U32 suportedCasLatencies; -+ MV_U32 refreshInterval; -+ MV_U32 dimmBankDensity; -+ MV_U32 dimmTypeInfo; /* DDR2 only */ -+ MV_U32 dimmAttributes; -+ -+ /* DIMM timing parameters */ -+ MV_U32 minCycleTimeAtMaxCasLatPs; -+ MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; -+ MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; -+ MV_U32 minRowPrechargeTime; -+ MV_U32 minRowActiveToRowActive; -+ MV_U32 minRasToCasDelay; -+ MV_U32 minRasPulseWidth; -+ MV_U32 minWriteRecoveryTime; /* DDR2 only */ -+ MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ -+ MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ -+ MV_U32 minRefreshToActiveCmd; /* DDR2 only */ -+ -+ /* Parameters calculated from the extracted DIMM information */ -+ MV_U32 size; /* 16,64,128,256 or 512 MByte in MB units */ -+ MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit in MB units */ -+ MV_U32 numberOfDevices; -+ -+} MV_DIMM_INFO; -+ -+ -+MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo); -+MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo); -+MV_VOID dimmSpdPrint(MV_U32 dimmNum); -+MV_STATUS dimmSpdCpy(MV_VOID); -+ -+#endif /* __INCmvDram */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c 2010-11-09 20:28:10.662495471 +0100 -@@ -0,0 +1,1599 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+/* includes */ -+#include "ddr1_2/mvDramIf.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+ -+ -+ -+#ifdef MV_DEBUG -+#define DB(x) x -+#else -+#define DB(x) -+#endif -+ -+/* DRAM bank presence encoding */ -+#define BANK_PRESENT_CS0 0x1 -+#define BANK_PRESENT_CS0_CS1 0x3 -+#define BANK_PRESENT_CS0_CS2 0x5 -+#define BANK_PRESENT_CS0_CS1_CS2 0x7 -+#define BANK_PRESENT_CS0_CS2_CS3 0xd -+#define BANK_PRESENT_CS0_CS2_CS3_CS4 0xf -+ -+/* locals */ -+static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin); -+#if defined(MV_INC_BOARD_DDIM) -+static void sdramDDr2OdtConfig(MV_DRAM_BANK_INFO *pBankInfo); -+static MV_U32 dunitCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas); -+static MV_U32 sdramModeRegCalc(MV_U32 minCas); -+static MV_U32 sdramExtModeRegCalc(MV_DRAM_BANK_INFO *pBankInfo); -+static MV_U32 sdramAddrCtrlRegCalc(MV_DRAM_BANK_INFO *pBankInfo); -+static MV_U32 sdramConfigRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk); -+static MV_U32 minCasCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk, -+ MV_U32 forcedCl); -+static MV_U32 sdramTimeCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, -+ MV_U32 minCas, MV_U32 busClk); -+static MV_U32 sdramTimeCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, -+ MV_U32 busClk); -+ -+/******************************************************************************* -+* mvDramIfDetect - Prepare DRAM interface configuration values. -+* -+* DESCRIPTION: -+* This function implements the full DRAM detection and timing -+* configuration for best system performance. -+* Since this routine runs from a ROM device (Boot Flash), its stack -+* resides on RAM, that might be the system DRAM. Changing DRAM -+* configuration values while keeping vital data in DRAM is risky. That -+* is why the function does not preform the configuration setting but -+* prepare those in predefined 32bit registers (in this case IDMA -+* registers are used) for other routine to perform the settings. -+* The function will call for board DRAM SPD information for each DRAM -+* chip select. The function will then analyze those SPD parameters of -+* all DRAM banks in order to decide on DRAM configuration compatible -+* for all DRAM banks. -+* The function will set the CPU DRAM address decode registers. -+* Note: This routine prepares values that will overide configuration of -+* mvDramBasicAsmInit(). -+* -+* INPUT: -+* forcedCl - Forced CAL Latency. If equal to zero, do not force. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvDramIfDetect(MV_U32 forcedCl) -+{ -+ MV_U32 retVal = MV_OK; /* return value */ -+ MV_DRAM_BANK_INFO bankInfo[MV_DRAM_MAX_CS]; -+ MV_U32 busClk, size, base = 0, i, temp, deviceW, dimmW; -+ MV_U8 minCas; -+ MV_DRAM_DEC_WIN dramDecWin; -+ -+ dramDecWin.addrWin.baseHigh = 0; -+ -+ busClk = mvBoardSysClkGet(); -+ -+ if (0 == busClk) -+ { -+ mvOsPrintf("Dram: ERR. Can't detect system clock! \n"); -+ return MV_ERROR; -+ } -+ -+ /* Close DRAM banks except bank 0 (in case code is excecuting from it...) */ -+#if defined(MV_INCLUDE_SDRAM_CS1) -+ for(i= SDRAM_CS1; i < MV_DRAM_MAX_CS; i++) -+ mvCpuIfTargetWinEnable(i, MV_FALSE); -+#endif -+ -+ /* we will use bank 0 as the representative of the all the DRAM banks, */ -+ /* since bank 0 must exist. */ -+ for(i = 0; i < MV_DRAM_MAX_CS; i++) -+ { -+ /* if Bank exist */ -+ if(MV_OK == mvDramBankInfoGet(i, &bankInfo[i])) -+ { -+ /* check it isn't SDRAM */ -+ if(bankInfo[i].memoryType == MEM_TYPE_SDRAM) -+ { -+ mvOsPrintf("Dram: ERR. SDRAM type not supported !!!\n"); -+ return MV_ERROR; -+ } -+ /* All banks must support registry in order to activate it */ -+ if(bankInfo[i].registeredAddrAndControlInputs != -+ bankInfo[0].registeredAddrAndControlInputs) -+ { -+ mvOsPrintf("Dram: ERR. different Registered settings !!!\n"); -+ return MV_ERROR; -+ } -+ -+ /* Init the CPU window decode */ -+ /* Note that the size in Bank info is in MB units */ -+ /* Note that the Dimm width might be different then the device DRAM width */ -+ temp = MV_REG_READ(SDRAM_CONFIG_REG); -+ -+ deviceW = ((temp & SDRAM_DWIDTH_MASK) == SDRAM_DWIDTH_16BIT )? 16 : 32; -+ dimmW = bankInfo[0].dataWidth - (bankInfo[0].dataWidth % 16); -+ size = ((bankInfo[i].size << 20) / (dimmW/deviceW)); -+ -+ /* We can not change DRAM window settings while excecuting */ -+ /* code from it. That is why we skip the DRAM CS[0], saving */ -+ /* it to the ROM configuration routine */ -+ if(i == SDRAM_CS0) -+ { -+ MV_U32 sizeToReg; -+ -+ /* Translate the given window size to register format */ -+ sizeToReg = ctrlSizeToReg(size, SCSR_SIZE_ALIGNMENT); -+ -+ /* Size parameter validity check. */ -+ if (-1 == sizeToReg) -+ { -+ mvOsPrintf("mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n" -+ ,i); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Size is located at upper 16 bits */ -+ sizeToReg <<= SCSR_SIZE_OFFS; -+ -+ /* enable it */ -+ sizeToReg |= SCSR_WIN_EN; -+ -+ MV_REG_WRITE(DRAM_BUF_REG0, sizeToReg); -+ } -+ else -+ { -+ dramDecWin.addrWin.baseLow = base; -+ dramDecWin.addrWin.size = size; -+ dramDecWin.enable = MV_TRUE; -+ -+ if (MV_OK != mvDramIfWinSet(SDRAM_CS0 + i, &dramDecWin)) -+ { -+ mvOsPrintf("Dram: ERR. Fail to set bank %d!!!\n", -+ SDRAM_CS0 + i); -+ return MV_ERROR; -+ } -+ } -+ -+ base += size; -+ -+ /* update the suportedCasLatencies mask */ -+ bankInfo[0].suportedCasLatencies &= bankInfo[i].suportedCasLatencies; -+ -+ } -+ else -+ { -+ if( i == 0 ) /* bank 0 doesn't exist */ -+ { -+ mvOsPrintf("Dram: ERR. Fail to detect bank 0 !!!\n"); -+ return MV_ERROR; -+ } -+ else -+ { -+ DB(mvOsPrintf("Dram: Could not find bank %d\n", i)); -+ bankInfo[i].size = 0; /* Mark this bank as non exist */ -+ } -+ } -+ } -+ -+ /* calculate minimum CAS */ -+ minCas = minCasCalc(&bankInfo[0], busClk, forcedCl); -+ if (0 == minCas) -+ { -+ mvOsOutput("Dram: Warn: Could not find CAS compatible to SysClk %dMhz\n", -+ (busClk / 1000000)); -+ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ minCas = DDR2_CL_4; /* Continue with this CAS */ -+ mvOsPrintf("Set default CAS latency 4\n"); -+ } -+ else -+ { -+ minCas = DDR1_CL_3; /* Continue with this CAS */ -+ mvOsPrintf("Set default CAS latency 3\n"); -+ } -+ } -+ -+ /* calc SDRAM_CONFIG_REG and save it to temp register */ -+ temp = sdramConfigRegCalc(&bankInfo[0], busClk); -+ if(-1 == temp) -+ { -+ mvOsPrintf("Dram: ERR. sdramConfigRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG1, temp); -+ -+ /* calc SDRAM_MODE_REG and save it to temp register */ -+ temp = sdramModeRegCalc(minCas); -+ if(-1 == temp) -+ { -+ mvOsPrintf("Dram: ERR. sdramModeRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG2, temp); -+ -+ /* calc SDRAM_EXTENDED_MODE_REG and save it to temp register */ -+ temp = sdramExtModeRegCalc(&bankInfo[0]); -+ if(-1 == temp) -+ { -+ mvOsPrintf("Dram: ERR. sdramModeRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG10, temp); -+ -+ /* calc D_UNIT_CONTROL_LOW and save it to temp register */ -+ temp = dunitCtrlLowRegCalc(&bankInfo[0], minCas); -+ if(-1 == temp) -+ { -+ mvOsPrintf("Dram: ERR. dunitCtrlLowRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG3, temp); -+ -+ /* calc SDRAM_ADDR_CTRL_REG and save it to temp register */ -+ temp = sdramAddrCtrlRegCalc(&bankInfo[0]); -+ if(-1 == temp) -+ { -+ mvOsPrintf("Dram: ERR. sdramAddrCtrlRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG4, temp); -+ -+ /* calc SDRAM_TIMING_CTRL_LOW_REG and save it to temp register */ -+ temp = sdramTimeCtrlLowRegCalc(&bankInfo[0], minCas, busClk); -+ if(-1 == temp) -+ { -+ mvOsPrintf("Dram: ERR. sdramTimeCtrlLowRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG5, temp); -+ -+ /* calc SDRAM_TIMING_CTRL_HIGH_REG and save it to temp register */ -+ temp = sdramTimeCtrlHighRegCalc(&bankInfo[0], busClk); -+ if(-1 == temp) -+ { -+ mvOsPrintf("Dram: ERR. sdramTimeCtrlHighRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG6, temp); -+ -+ /* Config DDR2 On Die Termination (ODT) registers */ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ sdramDDr2OdtConfig(bankInfo); -+ } -+ -+ /* Note that DDR SDRAM Address/Control and Data pad calibration */ -+ /* settings is done in mvSdramIfConfig.s */ -+ -+ return retVal; -+} -+ -+/******************************************************************************* -+* minCasCalc - Calculate the Minimum CAS latency which can be used. -+* -+* DESCRIPTION: -+* Calculate the minimum CAS latency that can be used, base on the DRAM -+* parameters and the SDRAM bus Clock freq. -+* -+* INPUT: -+* busClk - the DRAM bus Clock. -+* pBankInfo - bank info parameters. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* The minimum CAS Latency. The function returns 0 if max CAS latency -+* supported by banks is incompatible with system bus clock frequancy. -+* -+*******************************************************************************/ -+static MV_U32 minCasCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk, -+ MV_U32 forcedCl) -+{ -+ MV_U32 count = 1, j; -+ MV_U32 busClkPs = 1000000000 / (busClk / 1000); /* in ps units */ -+ MV_U32 startBit, stopBit; -+ -+ /* DDR 1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * -+ *********************************************************/ -+ -+ /* DDR 2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * -+ *********************************************************/ -+ -+ -+ /* If we are asked to use the forced CAL */ -+ if (forcedCl) -+ { -+ mvOsPrintf("DRAM: Using forced CL %d.%d\n", (forcedCl / 10), -+ (forcedCl % 10)); -+ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ if (forcedCl == 30) -+ pBankInfo->suportedCasLatencies = 0x08; -+ else if (forcedCl == 40) -+ pBankInfo->suportedCasLatencies = 0x10; -+ else -+ { -+ mvOsPrintf("Forced CL %d.%d not supported. Set default CL 4\n", -+ (forcedCl / 10), (forcedCl % 10)); -+ pBankInfo->suportedCasLatencies = 0x10; -+ } -+ } -+ else -+ { -+ if (forcedCl == 15) -+ pBankInfo->suportedCasLatencies = 0x02; -+ else if (forcedCl == 20) -+ pBankInfo->suportedCasLatencies = 0x04; -+ else if (forcedCl == 25) -+ pBankInfo->suportedCasLatencies = 0x08; -+ else if (forcedCl == 30) -+ pBankInfo->suportedCasLatencies = 0x10; -+ else if (forcedCl == 40) -+ pBankInfo->suportedCasLatencies = 0x40; -+ else -+ { -+ mvOsPrintf("Forced CL %d.%d not supported. Set default CL 3\n", -+ (forcedCl / 10), (forcedCl % 10)); -+ pBankInfo->suportedCasLatencies = 0x10; -+ } -+ } -+ -+ return pBankInfo->suportedCasLatencies; -+ } -+ -+ /* go over the supported cas mask from Max Cas down and check if the */ -+ /* SysClk stands in its time requirments. */ -+ -+ -+ DB(mvOsPrintf("Dram: minCasCalc supported mask = %x busClkPs = %x \n", -+ pBankInfo->suportedCasLatencies,busClkPs )); -+ for(j = 7; j > 0; j--) -+ { -+ if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) -+ { -+ /* Reset the bits for CL incompatible for the sysClk */ -+ switch (count) -+ { -+ case 1: -+ if (pBankInfo->minCycleTimeAtMaxCasLatPs > busClkPs) -+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ case 2: -+ if (pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps > busClkPs) -+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ case 3: -+ if (pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps > busClkPs) -+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ default: -+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); -+ break; -+ } -+ } -+ } -+ -+ DB(mvOsPrintf("Dram: minCasCalc support = %x (after SysCC calc)\n", -+ pBankInfo->suportedCasLatencies )); -+ -+ /* SDRAM DDR1 controller supports CL 1.5 to 3.5 */ -+ /* SDRAM DDR2 controller supports CL 3 to 5 */ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ startBit = 3; /* DDR2 support CL start with CL3 (bit 3) */ -+ stopBit = 5; /* DDR2 support CL stops with CL5 (bit 5) */ -+ } -+ else -+ { -+ startBit = 1; /* DDR1 support CL start with CL1.5 (bit 3) */ -+ stopBit = 4; /* DDR1 support CL stops with CL3 (bit 4) */ -+ } -+ -+ for(j = startBit; j <= stopBit ; j++) -+ { -+ if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) -+ { -+ DB(mvOsPrintf("Dram: minCasCalc choose CAS %x \n",(BIT0 << j))); -+ return (BIT0 << j); -+ } -+ } -+ -+ return 0; -+} -+ -+/******************************************************************************* -+* sdramConfigRegCalc - Calculate sdram config register -+* -+* DESCRIPTION: Calculate sdram config register optimized value based -+* on the bank info parameters. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram config reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramConfigRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) -+{ -+ MV_U32 sdramConfig = 0; -+ MV_U32 refreshPeriod; -+ -+ busClk /= 1000000; /* we work with busClk in MHz */ -+ -+ sdramConfig = MV_REG_READ(SDRAM_CONFIG_REG); -+ -+ /* figure out the memory refresh internal */ -+ switch (pBankInfo->refreshInterval & 0xf) -+ { -+ case 0x0: /* refresh period is 15.625 usec */ -+ refreshPeriod = 15625; -+ break; -+ case 0x1: /* refresh period is 3.9 usec */ -+ refreshPeriod = 3900; -+ break; -+ case 0x2: /* refresh period is 7.8 usec */ -+ refreshPeriod = 7800; -+ break; -+ case 0x3: /* refresh period is 31.3 usec */ -+ refreshPeriod = 31300; -+ break; -+ case 0x4: /* refresh period is 62.5 usec */ -+ refreshPeriod = 62500; -+ break; -+ case 0x5: /* refresh period is 125 usec */ -+ refreshPeriod = 125000; -+ break; -+ default: /* refresh period undefined */ -+ mvOsPrintf("Dram: ERR. DRAM refresh period is unknown!\n"); -+ return -1; -+ } -+ -+ /* Now the refreshPeriod is in register format value */ -+ refreshPeriod = (busClk * refreshPeriod) / 1000; -+ -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc calculated refresh interval %0x\n", -+ refreshPeriod)); -+ -+ /* make sure the refresh value is only 14 bits */ -+ if(refreshPeriod > SDRAM_REFRESH_MAX) -+ { -+ refreshPeriod = SDRAM_REFRESH_MAX; -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc adjusted refresh interval %0x\n", -+ refreshPeriod)); -+ } -+ -+ /* Clear the refresh field */ -+ sdramConfig &= ~SDRAM_REFRESH_MASK; -+ -+ /* Set new value to refresh field */ -+ sdramConfig |= (refreshPeriod & SDRAM_REFRESH_MASK); -+ -+ /* registered DRAM ? */ -+ if ( pBankInfo->registeredAddrAndControlInputs ) -+ { -+ /* it's registered DRAM, so set the reg. DRAM bit */ -+ sdramConfig |= SDRAM_REGISTERED; -+ mvOsPrintf("DRAM Attribute: Registered address and control inputs.\n"); -+ } -+ -+ /* set DDR SDRAM devices configuration */ -+ sdramConfig &= ~SDRAM_DCFG_MASK; /* Clear Dcfg field */ -+ -+ switch (pBankInfo->sdramWidth) -+ { -+ case 8: /* memory is x8 */ -+ sdramConfig |= SDRAM_DCFG_X8_DEV; -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc SDRAM device width x8\n")); -+ break; -+ case 16: -+ sdramConfig |= SDRAM_DCFG_X16_DEV; -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc SDRAM device width x16\n")); -+ break; -+ default: /* memory width unsupported */ -+ mvOsPrintf("Dram: ERR. DRAM chip width is unknown!\n"); -+ return -1; -+ } -+ -+ /* Set static default settings */ -+ sdramConfig |= SDRAM_CONFIG_DV; -+ -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc set sdramConfig to 0x%x\n", -+ sdramConfig)); -+ -+ return sdramConfig; -+} -+ -+/******************************************************************************* -+* sdramModeRegCalc - Calculate sdram mode register -+* -+* DESCRIPTION: Calculate sdram mode register optimized value based -+* on the bank info parameters and the minCas. -+* -+* INPUT: -+* minCas - minimum CAS supported. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram mode reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramModeRegCalc(MV_U32 minCas) -+{ -+ MV_U32 sdramMode; -+ -+ sdramMode = MV_REG_READ(SDRAM_MODE_REG); -+ -+ /* Clear CAS Latency field */ -+ sdramMode &= ~SDRAM_CL_MASK; -+ -+ mvOsPrintf("DRAM CAS Latency "); -+ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ switch (minCas) -+ { -+ case DDR2_CL_3: -+ sdramMode |= SDRAM_DDR2_CL_3; -+ mvOsPrintf("3.\n"); -+ break; -+ case DDR2_CL_4: -+ sdramMode |= SDRAM_DDR2_CL_4; -+ mvOsPrintf("4.\n"); -+ break; -+ case DDR2_CL_5: -+ sdramMode |= SDRAM_DDR2_CL_5; -+ mvOsPrintf("5.\n"); -+ break; -+ default: -+ mvOsPrintf("\nsdramModeRegCalc ERROR: Max. CL out of range\n"); -+ return -1; -+ } -+ sdramMode |= DDR2_MODE_REG_DV; -+ } -+ else /* DDR1 */ -+ { -+ switch (minCas) -+ { -+ case DDR1_CL_1_5: -+ sdramMode |= SDRAM_DDR1_CL_1_5; -+ mvOsPrintf("1.5\n"); -+ break; -+ case DDR1_CL_2: -+ sdramMode |= SDRAM_DDR1_CL_2; -+ mvOsPrintf("2\n"); -+ break; -+ case DDR1_CL_2_5: -+ sdramMode |= SDRAM_DDR1_CL_2_5; -+ mvOsPrintf("2.5\n"); -+ break; -+ case DDR1_CL_3: -+ sdramMode |= SDRAM_DDR1_CL_3; -+ mvOsPrintf("3\n"); -+ break; -+ case DDR1_CL_4: -+ sdramMode |= SDRAM_DDR1_CL_4; -+ mvOsPrintf("4\n"); -+ break; -+ default: -+ mvOsPrintf("\nsdramModeRegCalc ERROR: Max. CL out of range\n"); -+ return -1; -+ } -+ sdramMode |= DDR1_MODE_REG_DV; -+ } -+ -+ DB(mvOsPrintf("nsdramModeRegCalc register 0x%x\n", sdramMode )); -+ -+ return sdramMode; -+} -+ -+/******************************************************************************* -+* sdramExtModeRegCalc - Calculate sdram Extended mode register -+* -+* DESCRIPTION: -+* Return sdram Extended mode register value based -+* on the bank info parameters and bank presence. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram Extended mode reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramExtModeRegCalc(MV_DRAM_BANK_INFO *pBankInfo) -+{ -+ MV_U32 populateBanks = 0; -+ int bankNum; -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ /* Represent the populate banks in binary form */ -+ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ if (0 != pBankInfo[bankNum].size) -+ { -+ populateBanks |= (1 << bankNum); -+ } -+ } -+ -+ switch(populateBanks) -+ { -+ case(BANK_PRESENT_CS0): -+ return DDR_SDRAM_EXT_MODE_CS0_DV; -+ -+ case(BANK_PRESENT_CS0_CS1): -+ return DDR_SDRAM_EXT_MODE_CS0_DV; -+ -+ case(BANK_PRESENT_CS0_CS2): -+ return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; -+ -+ case(BANK_PRESENT_CS0_CS1_CS2): -+ return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; -+ -+ case(BANK_PRESENT_CS0_CS2_CS3): -+ return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; -+ -+ case(BANK_PRESENT_CS0_CS2_CS3_CS4): -+ return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; -+ -+ default: -+ mvOsPrintf("sdramExtModeRegCalc: Invalid DRAM bank presence\n"); -+ return -1; -+ } -+ } -+ return 0; -+} -+ -+/******************************************************************************* -+* dunitCtrlLowRegCalc - Calculate sdram dunit control low register -+* -+* DESCRIPTION: Calculate sdram dunit control low register optimized value based -+* on the bank info parameters and the minCas. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* minCas - minimum CAS supported. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram dunit control low reg value. -+* -+*******************************************************************************/ -+static MV_U32 dunitCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas) -+{ -+ MV_U32 dunitCtrlLow; -+ -+ dunitCtrlLow = MV_REG_READ(SDRAM_DUNIT_CTRL_REG); -+ -+ /* Clear StBurstDel field */ -+ dunitCtrlLow &= ~SDRAM_ST_BURST_DEL_MASK; -+ -+#ifdef MV_88W8660 -+ /* Clear address/control output timing field */ -+ dunitCtrlLow &= ~SDRAM_CTRL_POS_RISE; -+#endif /* MV_88W8660 */ -+ -+ DB(mvOsPrintf("Dram: dunitCtrlLowRegCalc\n")); -+ -+ /* For proper sample of read data set the Dunit Control register's */ -+ /* stBurstDel bits [27:24] */ -+ /********-********-********-********-********-********* -+ * CL=1.5 | CL=2 | CL=2.5 | CL=3 | CL=4 | CL=5 * -+ *********-********-********-********-********-********* -+Not Reg. * 0011 | 0011 | 0100 | 0100 | 0101 | TBD * -+ *********-********-********-********-********-********* -+Registered * 0100 | 0100 | 0101 | 0101 | 0110 | TBD * -+ *********-********-********-********-********-*********/ -+ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ switch (minCas) -+ { -+ case DDR2_CL_3: -+ /* registerd DDR SDRAM? */ -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; -+ else -+ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; -+ break; -+ case DDR2_CL_4: -+ /* registerd DDR SDRAM? */ -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ dunitCtrlLow |= 0x6 << SDRAM_ST_BURST_DEL_OFFS; -+ else -+ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; -+ break; -+ default: -+ mvOsPrintf("Dram: dunitCtrlLowRegCalc Max. CL out of range %d\n", -+ minCas); -+ return -1; -+ } -+ } -+ else /* DDR1 */ -+ { -+ switch (minCas) -+ { -+ case DDR1_CL_1_5: -+ /* registerd DDR SDRAM? */ -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; -+ else -+ dunitCtrlLow |= 0x3 << SDRAM_ST_BURST_DEL_OFFS; -+ break; -+ case DDR1_CL_2: -+ /* registerd DDR SDRAM? */ -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; -+ else -+ dunitCtrlLow |= 0x3 << SDRAM_ST_BURST_DEL_OFFS; -+ break; -+ case DDR1_CL_2_5: -+ /* registerd DDR SDRAM? */ -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; -+ else -+ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; -+ break; -+ case DDR1_CL_3: -+ /* registerd DDR SDRAM? */ -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; -+ else -+ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; -+ break; -+ case DDR1_CL_4: -+ /* registerd DDR SDRAM? */ -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ dunitCtrlLow |= 0x6 << SDRAM_ST_BURST_DEL_OFFS; -+ else -+ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; -+ break; -+ default: -+ mvOsPrintf("Dram: dunitCtrlLowRegCalc Max. CL out of range %d\n", -+ minCas); -+ return -1; -+ } -+ -+ } -+ DB(mvOsPrintf("Dram: Reg dunit control low = %x\n", dunitCtrlLow )); -+ -+ return dunitCtrlLow; -+} -+ -+/******************************************************************************* -+* sdramAddrCtrlRegCalc - Calculate sdram address control register -+* -+* DESCRIPTION: Calculate sdram address control register optimized value based -+* on the bank info parameters and the minCas. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram address control reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramAddrCtrlRegCalc(MV_DRAM_BANK_INFO *pBankInfo) -+{ -+ MV_U32 addrCtrl = 0; -+ -+ /* Set Address Control register static configuration bits */ -+ addrCtrl = MV_REG_READ(SDRAM_ADDR_CTRL_REG); -+ -+ /* Set address control default value */ -+ addrCtrl |= SDRAM_ADDR_CTRL_DV; -+ -+ /* Clear DSize field */ -+ addrCtrl &= ~SDRAM_DSIZE_MASK; -+ -+ /* Note that density is in MB units */ -+ switch (pBankInfo->deviceDensity) -+ { -+ case 128: /* 128 Mbit */ -+ DB(mvOsPrintf("DRAM Device Density 128Mbit\n")); -+ addrCtrl |= SDRAM_DSIZE_128Mb; -+ break; -+ case 256: /* 256 Mbit */ -+ DB(mvOsPrintf("DRAM Device Density 256Mbit\n")); -+ addrCtrl |= SDRAM_DSIZE_256Mb; -+ break; -+ case 512: /* 512 Mbit */ -+ DB(mvOsPrintf("DRAM Device Density 512Mbit\n")); -+ addrCtrl |= SDRAM_DSIZE_512Mb; -+ break; -+ default: -+ mvOsPrintf("Dram: sdramAddrCtrl unsupported RAM-Device size %d\n", -+ pBankInfo->deviceDensity); -+ return -1; -+ } -+ -+ /* SDRAM address control */ -+ DB(mvOsPrintf("Dram: setting sdram address control with: %x \n", addrCtrl)); -+ -+ return addrCtrl; -+} -+ -+/******************************************************************************* -+* sdramTimeCtrlLowRegCalc - Calculate sdram timing control low register -+* -+* DESCRIPTION: -+* This function calculates sdram timing control low register -+* optimized value based on the bank info parameters and the minCas. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* busClk - Bus clock -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram timinf control low reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramTimeCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, -+ MV_U32 minCas, MV_U32 busClk) -+{ -+ MV_U32 tRp = 0; -+ MV_U32 tRrd = 0; -+ MV_U32 tRcd = 0; -+ MV_U32 tRas = 0; -+ MV_U32 tWr = 0; -+ MV_U32 tWtr = 0; -+ MV_U32 tRtp = 0; -+ -+ MV_U32 bankNum; -+ -+ busClk = busClk / 1000000; /* In MHz */ -+ -+ /* Scan all DRAM banks to find maximum timing values */ -+ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ tRp = MV_MAX(tRp, pBankInfo[bankNum].minRowPrechargeTime); -+ tRrd = MV_MAX(tRrd, pBankInfo[bankNum].minRowActiveToRowActive); -+ tRcd = MV_MAX(tRcd, pBankInfo[bankNum].minRasToCasDelay); -+ tRas = MV_MAX(tRas, pBankInfo[bankNum].minRasPulseWidth); -+ } -+ -+ /* Extract timing (in ns) from SPD value. We ignore the tenth ns part. */ -+ /* by shifting the data two bits right. */ -+ tRp = tRp >> 2; /* For example 0x50 -> 20ns */ -+ tRrd = tRrd >> 2; -+ tRcd = tRcd >> 2; -+ -+ /* Extract clock cycles from time parameter. We need to round up */ -+ tRp = ((busClk * tRp) / 1000) + (((busClk * tRp) % 1000) ? 1 : 0); -+ /* Micron work around for 133MHz */ -+ if (busClk == 133) -+ tRp += 1; -+ DB(mvOsPrintf("Dram Timing Low: tRp = %d ", tRp)); -+ tRrd = ((busClk * tRrd) / 1000) + (((busClk * tRrd) % 1000) ? 1 : 0); -+ /* JEDEC min reqeirments tRrd = 2 */ -+ if (tRrd < 2) -+ tRrd = 2; -+ DB(mvOsPrintf("tRrd = %d ", tRrd)); -+ tRcd = ((busClk * tRcd) / 1000) + (((busClk * tRcd) % 1000) ? 1 : 0); -+ DB(mvOsPrintf("tRcd = %d ", tRcd)); -+ tRas = ((busClk * tRas) / 1000) + (((busClk * tRas) % 1000) ? 1 : 0); -+ DB(mvOsPrintf("tRas = %d ", tRas)); -+ -+ /* tWr and tWtr is different for DDR1 and DDR2. tRtp is only for DDR2 */ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ /* Scan all DRAM banks to find maximum timing values */ -+ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ tWr = MV_MAX(tWr, pBankInfo[bankNum].minWriteRecoveryTime); -+ tWtr = MV_MAX(tWtr, pBankInfo[bankNum].minWriteToReadCmdDelay); -+ tRtp = MV_MAX(tRtp, pBankInfo[bankNum].minReadToPrechCmdDelay); -+ } -+ -+ /* Extract timing (in ns) from SPD value. We ignore the tenth ns */ -+ /* part by shifting the data two bits right. */ -+ tWr = tWr >> 2; /* For example 0x50 -> 20ns */ -+ tWtr = tWtr >> 2; -+ tRtp = tRtp >> 2; -+ -+ /* Extract clock cycles from time parameter. We need to round up */ -+ tWr = ((busClk * tWr) / 1000) + (((busClk * tWr) % 1000) ? 1 : 0); -+ DB(mvOsPrintf("tWr = %d ", tWr)); -+ tWtr = ((busClk * tWtr) / 1000) + (((busClk * tWtr) % 1000) ? 1 : 0); -+ /* JEDEC min reqeirments tWtr = 2 */ -+ if (tWtr < 2) -+ tWtr = 2; -+ DB(mvOsPrintf("tWtr = %d ", tWtr)); -+ tRtp = ((busClk * tRtp) / 1000) + (((busClk * tRtp) % 1000) ? 1 : 0); -+ /* JEDEC min reqeirments tRtp = 2 */ -+ if (tRtp < 2) -+ tRtp = 2; -+ DB(mvOsPrintf("tRtp = %d ", tRtp)); -+ } -+ else -+ { -+ tWr = ((busClk*SDRAM_TWR) / 1000) + (((busClk*SDRAM_TWR) % 1000)?1:0); -+ -+ if ((200 == busClk) || ((100 == busClk) && (DDR1_CL_1_5 == minCas))) -+ { -+ tWtr = 2; -+ } -+ else -+ { -+ tWtr = 1; -+ } -+ -+ tRtp = 2; /* Must be set to 0x1 (two cycles) when using DDR1 */ -+ } -+ -+ DB(mvOsPrintf("tWtr = %d\n", tWtr)); -+ -+ /* Note: value of 0 in register means one cycle, 1 means two and so on */ -+ return (((tRp - 1) << SDRAM_TRP_OFFS) | -+ ((tRrd - 1) << SDRAM_TRRD_OFFS) | -+ ((tRcd - 1) << SDRAM_TRCD_OFFS) | -+ ((tRas - 1) << SDRAM_TRAS_OFFS) | -+ ((tWr - 1) << SDRAM_TWR_OFFS) | -+ ((tWtr - 1) << SDRAM_TWTR_OFFS) | -+ ((tRtp - 1) << SDRAM_TRTP_OFFS)); -+} -+ -+/******************************************************************************* -+* sdramTimeCtrlHighRegCalc - Calculate sdram timing control high register -+* -+* DESCRIPTION: -+* This function calculates sdram timing control high register -+* optimized value based on the bank info parameters and the bus clock. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* busClk - Bus clock -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram timinf control high reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramTimeCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, -+ MV_U32 busClk) -+{ -+ MV_U32 tRfc; -+ MV_U32 timeNs = 0; -+ int bankNum; -+ MV_U32 sdramTw2wCyc = 0; -+ -+ busClk = busClk / 1000000; /* In MHz */ -+ -+ /* tRfc is different for DDR1 and DDR2. */ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ MV_U32 bankNum; -+ -+ /* Scan all DRAM banks to find maximum timing values */ -+ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ timeNs = MV_MAX(timeNs, pBankInfo[bankNum].minRefreshToActiveCmd); -+ } -+ else -+ { -+ if (pBankInfo[0].deviceDensity == _1G) -+ { -+ timeNs = SDRAM_TRFC_1G; -+ } -+ else -+ { -+ if (200 == busClk) -+ { -+ timeNs = SDRAM_TRFC_64_512M_AT_200MHZ; -+ } -+ else -+ { -+ timeNs = SDRAM_TRFC_64_512M; -+ } -+ } -+ } -+ -+ tRfc = ((busClk * timeNs) / 1000) + (((busClk * timeNs) % 1000) ? 1 : 0); -+ -+ DB(mvOsPrintf("Dram Timing High: tRfc = %d\n", tRfc)); -+ -+ -+ /* Represent the populate banks in binary form */ -+ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ if (0 != pBankInfo[bankNum].size) -+ sdramTw2wCyc++; -+ } -+ -+ /* If we have more the 1 bank then we need the TW2W in 1 for ODT switch */ -+ if (sdramTw2wCyc > 1) -+ sdramTw2wCyc = 1; -+ else -+ sdramTw2wCyc = 0; -+ -+ /* Note: value of 0 in register means one cycle, 1 means two and so on */ -+ return ((((tRfc - 1) & SDRAM_TRFC_MASK) << SDRAM_TRFC_OFFS) | -+ ((SDRAM_TR2R_CYC - 1) << SDRAM_TR2R_OFFS) | -+ ((SDRAM_TR2WW2R_CYC - 1) << SDRAM_TR2W_W2R_OFFS) | -+ (((tRfc - 1) >> 4) << SDRAM_TRFC_EXT_OFFS) | -+ (sdramTw2wCyc << SDRAM_TW2W_OFFS)); -+ -+} -+ -+/******************************************************************************* -+* sdramDDr2OdtConfig - Set DRAM DDR2 On Die Termination registers. -+* -+* DESCRIPTION: -+* This function config DDR2 On Die Termination (ODT) registers. -+* ODT configuration is done according to DIMM presence: -+* -+* Presence Ctrl Low Ctrl High Dunit Ctrl Ext Mode -+* CS0 0x84210000 0x00000000 0x0000780F 0x00000440 -+* CS0+CS1 0x84210000 0x00000000 0x0000780F 0x00000440 -+* CS0+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 -+* CS0+CS1+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 -+* CS0+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 -+* CS0+CS1+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 -+* -+* INPUT: -+* pBankInfo - bank info parameters. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* None -+*******************************************************************************/ -+static void sdramDDr2OdtConfig(MV_DRAM_BANK_INFO *pBankInfo) -+{ -+ MV_U32 populateBanks = 0; -+ MV_U32 odtCtrlLow, odtCtrlHigh, dunitOdtCtrl; -+ int bankNum; -+ -+ /* Represent the populate banks in binary form */ -+ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ if (0 != pBankInfo[bankNum].size) -+ { -+ populateBanks |= (1 << bankNum); -+ } -+ } -+ -+ switch(populateBanks) -+ { -+ case(BANK_PRESENT_CS0): -+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_DV; -+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_DV; -+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_DV; -+ break; -+ case(BANK_PRESENT_CS0_CS1): -+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_DV; -+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_DV; -+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_DV; -+ break; -+ case(BANK_PRESENT_CS0_CS2): -+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; -+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; -+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; -+ break; -+ case(BANK_PRESENT_CS0_CS1_CS2): -+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; -+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; -+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; -+ break; -+ case(BANK_PRESENT_CS0_CS2_CS3): -+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; -+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; -+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; -+ break; -+ case(BANK_PRESENT_CS0_CS2_CS3_CS4): -+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; -+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; -+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; -+ break; -+ default: -+ mvOsPrintf("sdramDDr2OdtConfig: Invalid DRAM bank presence\n"); -+ return; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG7, odtCtrlLow); -+ MV_REG_WRITE(DRAM_BUF_REG8, odtCtrlHigh); -+ MV_REG_WRITE(DRAM_BUF_REG9, dunitOdtCtrl); -+ return; -+} -+#endif /* defined(MV_INC_BOARD_DDIM) */ -+ -+/******************************************************************************* -+* mvDramIfWinSet - Set DRAM interface address decode window -+* -+* DESCRIPTION: -+* This function sets DRAM interface address decode window. -+* -+* INPUT: -+* target - System target. Use only SDRAM targets. -+* pAddrDecWin - SDRAM address window structure. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK -+* otherwise. -+*******************************************************************************/ -+MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) -+{ -+ MV_U32 baseReg=0,sizeReg=0; -+ MV_U32 baseToReg=0 , sizeToReg=0; -+ -+ /* Check parameters */ -+ if (!MV_TARGET_IS_DRAM(target)) -+ { -+ mvOsPrintf("mvDramIfWinSet: target %d is not SDRAM\n", target); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlaps with current enabled windows */ -+ if (MV_TRUE == sdramIfWinOverlap(target, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("mvDramIfWinSet: ERR. Target %d overlaps\n", target); -+ return MV_BAD_PARAM; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvDramIfWinSet:Error setting DRAM interface window %d."\ -+ "\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ target, -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ /* read base register*/ -+ baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(target)); -+ -+ /* read size register */ -+ sizeReg = MV_REG_READ(SDRAM_SIZE_REG(target)); -+ -+ /* BaseLow[31:16] => base register [31:16] */ -+ baseToReg = pAddrDecWin->addrWin.baseLow & SCBAR_BASE_MASK; -+ -+ /* Write to address decode Base Address Register */ -+ baseReg &= ~SCBAR_BASE_MASK; -+ baseReg |= baseToReg; -+ -+ /* Translate the given window size to register format */ -+ sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, SCSR_SIZE_ALIGNMENT); -+ -+ /* Size parameter validity check. */ -+ if (-1 == sizeToReg) -+ { -+ mvOsPrintf("mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n",target); -+ return MV_BAD_PARAM; -+ } -+ -+ /* set size */ -+ sizeReg &= ~SCSR_SIZE_MASK; -+ /* Size is located at upper 16 bits */ -+ sizeReg |= (sizeToReg << SCSR_SIZE_OFFS); -+ -+ /* enable/Disable */ -+ if (MV_TRUE == pAddrDecWin->enable) -+ { -+ sizeReg |= SCSR_WIN_EN; -+ } -+ else -+ { -+ sizeReg &= ~SCSR_WIN_EN; -+ } -+ -+ /* 3) Write to address decode Base Address Register */ -+ MV_REG_WRITE(SDRAM_BASE_ADDR_REG(target), baseReg); -+ -+ /* Write to address decode Size Register */ -+ MV_REG_WRITE(SDRAM_SIZE_REG(target), sizeReg); -+ -+ return MV_OK; -+} -+/******************************************************************************* -+* mvDramIfWinGet - Get DRAM interface address decode window -+* -+* DESCRIPTION: -+* This function gets DRAM interface address decode window. -+* -+* INPUT: -+* target - System target. Use only SDRAM targets. -+* -+* OUTPUT: -+* pAddrDecWin - SDRAM address window structure. -+* -+* RETURN: -+* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK -+* otherwise. -+*******************************************************************************/ -+MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) -+{ -+ MV_U32 baseReg,sizeReg; -+ MV_U32 sizeRegVal; -+ -+ /* Check parameters */ -+ if (!MV_TARGET_IS_DRAM(target)) -+ { -+ mvOsPrintf("mvDramIfWinGet: target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ /* Read base and size registers */ -+ sizeReg = MV_REG_READ(SDRAM_SIZE_REG(target)); -+ baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(target)); -+ -+ sizeRegVal = (sizeReg & SCSR_SIZE_MASK) >> SCSR_SIZE_OFFS; -+ -+ pAddrDecWin->addrWin.size = ctrlRegToSize(sizeRegVal, -+ SCSR_SIZE_ALIGNMENT); -+ -+ /* Check if ctrlRegToSize returned OK */ -+ if (-1 == pAddrDecWin->addrWin.size) -+ { -+ mvOsPrintf("mvDramIfWinGet: size of target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ /* Extract base address */ -+ /* Base register [31:16] ==> baseLow[31:16] */ -+ pAddrDecWin->addrWin.baseLow = baseReg & SCBAR_BASE_MASK; -+ -+ pAddrDecWin->addrWin.baseHigh = 0; -+ -+ -+ if (sizeReg & SCSR_WIN_EN) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ } -+ -+ return MV_OK; -+} -+/******************************************************************************* -+* mvDramIfWinEnable - Enable/Disable SDRAM address decode window -+* -+* DESCRIPTION: -+* This function enable/Disable SDRAM address decode window. -+* -+* INPUT: -+* target - System target. Use only SDRAM targets. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR in case function parameter are invalid, MV_OK otherewise. -+* -+*******************************************************************************/ -+MV_STATUS mvDramIfWinEnable(MV_TARGET target,MV_BOOL enable) -+{ -+ MV_DRAM_DEC_WIN addrDecWin; -+ -+ /* Check parameters */ -+ if (!MV_TARGET_IS_DRAM(target)) -+ { -+ mvOsPrintf("mvDramIfWinEnable: target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ if (enable == MV_TRUE) -+ { /* First check for overlap with other enabled windows */ -+ if (MV_OK != mvDramIfWinGet(target, &addrDecWin)) -+ { -+ mvOsPrintf("mvDramIfWinEnable:ERR. Getting target %d failed.\n", -+ target); -+ return MV_ERROR; -+ } -+ /* Check for overlapping */ -+ if (MV_FALSE == sdramIfWinOverlap(target, &(addrDecWin.addrWin))) -+ { -+ /* No Overlap. Enable address decode winNum window */ -+ MV_REG_BIT_SET(SDRAM_SIZE_REG(target), SCSR_WIN_EN); -+ } -+ else -+ { /* Overlap detected */ -+ mvOsPrintf("mvDramIfWinEnable: ERR. Target %d overlap detect\n", -+ target); -+ return MV_ERROR; -+ } -+ } -+ else -+ { /* Disable address decode winNum window */ -+ MV_REG_BIT_RESET(SDRAM_SIZE_REG(target), SCSR_WIN_EN); -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* sdramIfWinOverlap - Check if an address window overlap an SDRAM address window -+* -+* DESCRIPTION: -+* This function scan each SDRAM address decode window to test if it -+* overlapps the given address windoow -+* -+* INPUT: -+* target - SDRAM target where the function skips checking. -+* pAddrDecWin - The tested address window for overlapping with -+* SDRAM windows. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlaps any enabled address -+* decode map, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_TARGET targetNum; -+ MV_DRAM_DEC_WIN addrDecWin; -+ -+ for(targetNum = SDRAM_CS0; targetNum < MV_DRAM_MAX_CS ; targetNum++) -+ { -+ /* don't check our winNum or illegal targets */ -+ if (targetNum == target) -+ { -+ continue; -+ } -+ -+ /* Get window parameters */ -+ if (MV_OK != mvDramIfWinGet(targetNum, &addrDecWin)) -+ { -+ mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); -+ return MV_ERROR; -+ } -+ -+ /* Do not check disabled windows */ -+ if (MV_FALSE == addrDecWin.enable) -+ { -+ continue; -+ } -+ -+ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) -+ { -+ mvOsPrintf( -+ "sdramIfWinOverlap: Required target %d overlap winNum %d\n", -+ target, targetNum); -+ return MV_TRUE; -+ } -+ } -+ -+ return MV_FALSE; -+} -+ -+/******************************************************************************* -+* mvDramIfBankSizeGet - Get DRAM interface bank size. -+* -+* DESCRIPTION: -+* This function returns the size of a given DRAM bank. -+* -+* INPUT: -+* bankNum - Bank number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* DRAM bank size. If bank is disabled the function return '0'. In case -+* or paramter is invalid, the function returns -1. -+* -+*******************************************************************************/ -+MV_32 mvDramIfBankSizeGet(MV_U32 bankNum) -+{ -+ MV_DRAM_DEC_WIN addrDecWin; -+ -+ /* Check parameters */ -+ if (!MV_TARGET_IS_DRAM(bankNum)) -+ { -+ mvOsPrintf("mvDramIfBankBaseGet: bankNum %d is invalid\n", bankNum); -+ return -1; -+ } -+ /* Get window parameters */ -+ if (MV_OK != mvDramIfWinGet(bankNum, &addrDecWin)) -+ { -+ mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); -+ return -1; -+ } -+ -+ if (MV_TRUE == addrDecWin.enable) -+ { -+ return addrDecWin.addrWin.size; -+ } -+ else -+ { -+ return 0; -+ } -+} -+ -+ -+/******************************************************************************* -+* mvDramIfSizeGet - Get DRAM interface total size. -+* -+* DESCRIPTION: -+* This function get the DRAM total size. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* DRAM total size. In case or paramter is invalid, the function -+* returns -1. -+* -+*******************************************************************************/ -+MV_32 mvDramIfSizeGet(MV_VOID) -+{ -+ MV_U32 totalSize = 0, bankSize = 0, bankNum; -+ -+ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ bankSize = mvDramIfBankSizeGet(bankNum); -+ -+ if (-1 == bankSize) -+ { -+ mvOsPrintf("Dram: mvDramIfSizeGet error with bank %d \n",bankNum); -+ return -1; -+ } -+ else -+ { -+ totalSize += bankSize; -+ } -+ } -+ -+ DB(mvOsPrintf("Dram: Total DRAM size is 0x%x \n",totalSize)); -+ -+ return totalSize; -+} -+ -+/******************************************************************************* -+* mvDramIfBankBaseGet - Get DRAM interface bank base. -+* -+* DESCRIPTION: -+* This function returns the 32 bit base address of a given DRAM bank. -+* -+* INPUT: -+* bankNum - Bank number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* DRAM bank size. If bank is disabled or paramter is invalid, the -+* function returns -1. -+* -+*******************************************************************************/ -+MV_32 mvDramIfBankBaseGet(MV_U32 bankNum) -+{ -+ MV_DRAM_DEC_WIN addrDecWin; -+ -+ /* Check parameters */ -+ if (!MV_TARGET_IS_DRAM(bankNum)) -+ { -+ mvOsPrintf("mvDramIfBankBaseGet: bankNum %d is invalid\n", bankNum); -+ return -1; -+ } -+ /* Get window parameters */ -+ if (MV_OK != mvDramIfWinGet(bankNum, &addrDecWin)) -+ { -+ mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); -+ return -1; -+ } -+ -+ if (MV_TRUE == addrDecWin.enable) -+ { -+ return addrDecWin.addrWin.baseLow; -+ } -+ else -+ { -+ return -1; -+ } -+} -+ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h 2010-11-09 20:28:10.692495407 +0100 -@@ -0,0 +1,192 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvDramIfConfigh -+#define __INCmvDramIfConfigh -+ -+/* includes */ -+ -+/* defines */ -+ -+/* registers defaults values */ -+ -+#define SDRAM_CONFIG_DV \ -+ (SDRAM_PERR_WRITE | \ -+ SDRAM_SRMODE | \ -+ SDRAM_SRCLK_GATED) -+ -+#define SDRAM_DUNIT_CTRL_LOW_DV \ -+ (SDRAM_CTRL_POS_RISE | \ -+ SDRAM_CLK1DRV_NORMAL | \ -+ SDRAM_LOCKEN_ENABLE) -+ -+#define SDRAM_ADDR_CTRL_DV 0 -+ -+#define SDRAM_TIMING_CTRL_LOW_REG_DV \ -+ ((0x2 << SDRAM_TRCD_OFFS) | \ -+ (0x2 << SDRAM_TRP_OFFS) | \ -+ (0x1 << SDRAM_TWR_OFFS) | \ -+ (0x0 << SDRAM_TWTR_OFFS) | \ -+ (0x5 << SDRAM_TRAS_OFFS) | \ -+ (0x1 << SDRAM_TRRD_OFFS)) -+/* TRFC 0x27, TW2W 0x1 */ -+#define SDRAM_TIMING_CTRL_HIGH_REG_DV (( 0x7 << SDRAM_TRFC_OFFS ) |\ -+ ( 0x2 << SDRAM_TRFC_EXT_OFFS) |\ -+ ( 0x1 << SDRAM_TW2W_OFFS)) -+ -+#define SDRAM_OPEN_PAGES_CTRL_REG_DV SDRAM_OPEN_PAGE_EN -+ -+/* DDR2 ODT default register values */ -+ -+/* Presence Ctrl Low Ctrl High Dunit Ctrl Ext Mode */ -+/* CS0 0x84210000 0x00000000 0x0000780F 0x00000440 */ -+/* CS0+CS1 0x84210000 0x00000000 0x0000780F 0x00000440 */ -+/* CS0+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -+/* CS0+CS1+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -+/* CS0+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -+/* CS0+CS1+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -+ -+#define DDR2_ODT_CTRL_LOW_CS0_DV 0x84210000 -+#define DDR2_ODT_CTRL_HIGH_CS0_DV 0x00000000 -+#define DDR2_DUNIT_ODT_CTRL_CS0_DV 0x0000780F -+#define DDR_SDRAM_EXT_MODE_CS0_DV 0x00000440 -+ -+#define DDR2_ODT_CTRL_LOW_CS0_CS2_DV 0x030C030C -+#define DDR2_ODT_CTRL_HIGH_CS0_CS2_DV 0x00000000 -+#define DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV 0x0000740F -+#define DDR_SDRAM_EXT_MODE_CS0_CS2_DV 0x00000404 -+ -+ -+/* DDR SDRAM Adderss/Control and Data Pads Calibration default values */ -+#define DDR1_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \ -+ (1 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) -+#define DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \ -+ (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) -+ -+ -+#define DDR1_DATA_PAD_STRENGTH_TYPICAL_DV \ -+ (1 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) -+#define DDR2_DATA_PAD_STRENGTH_TYPICAL_DV \ -+ (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) -+ -+/* DDR SDRAM Mode Register default value */ -+#define DDR1_MODE_REG_DV 0x00000000 -+#define DDR2_MODE_REG_DV 0x00000400 -+ -+/* DDR SDRAM Timing parameter default values */ -+#define DDR1_TIMING_LOW_DV 0x11602220 -+#define DDR1_TIMING_HIGH_DV 0x0000000d -+ -+#define DDR2_TIMING_LOW_DV 0x11812220 -+#define DDR2_TIMING_HIGH_DV 0x0000030f -+ -+/* For Guideline (GL# MEM-4) DQS Reference Delay Tuning */ -+#define FTDLL_DDR1_166MHZ ((0x1 << 0) | \ -+ (0x7F<< 12) | \ -+ (0x1 << 22)) -+ -+#define FTDLL_DDR1_133MHZ FTDLL_DDR1_166MHZ -+ -+#define FTDLL_DDR1_200MHZ ((0x1 << 0) | \ -+ (0x1 << 12) | \ -+ (0x3 << 14) | \ -+ (0x1 << 18) | \ -+ (0x1 << 22)) -+ -+ -+#define FTDLL_DDR2_166MHZ ((0x1 << 0) | \ -+ (0x1 << 12) | \ -+ (0x1 << 14) | \ -+ (0x1 << 16) | \ -+ (0x1 << 19) | \ -+ (0xF << 20)) -+ -+#define FTDLL_DDR2_133MHZ FTDLL_DDR2_166MHZ -+ -+#define FTDLL_DDR2_200MHZ ((0x1 << 0) | \ -+ (0x1 << 12) | \ -+ (0x1 << 14) | \ -+ (0x1 << 16) | \ -+ (0x1 << 19) | \ -+ (0xF << 20)) -+ -+#define FTDLL_DDR2_250MHZ 0x445001 -+ -+/* Orion 1 B1 and above */ -+#define FTDLL_DDR1_166MHZ_5181_B1 0x45D001 -+ -+/* Orion nas */ -+#define FTDLL_DDR2_166MHZ_5182 0x597001 -+ -+/* Orion 2 D0 and above */ -+#define FTDLL_DDR1_166MHZ_5281_D0 0x8D0001 -+#define FTDLL_DDR1_200MHZ_5281_D0 0x8D0001 -+#define FTDLL_DDR2_166MHZ_5281_D0 0x485001 -+#define FTDLL_DDR2_200MHZ_5281_D0 0x485001 -+#define FTDLL_DDR2_250MHZ_5281_D0 0x445001 -+#define FTDLL_DDR2_200MHZ_5281_D1 0x995001 -+#define FTDLL_DDR2_250MHZ_5281_D1 0x984801 -+ -+#endif /* __INCmvDramIfh */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h 2010-11-09 20:28:10.747105889 +0100 -@@ -0,0 +1,179 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvDramIfh -+#define __INCmvDramIfh -+ -+/* includes */ -+#include "ddr1_2/mvDramIfRegs.h" -+#include "ddr1_2/mvDramIfConfig.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+ -+/* defines */ -+/* DRAM Timing parameters */ -+#define SDRAM_TWR 15 /* ns tWr */ -+#define SDRAM_TRFC_64_512M_AT_200MHZ 70 /* ns tRfc for dens 64-512 @ 200MHz */ -+#define SDRAM_TRFC_64_512M 75 /* ns tRfc for dens 64-512 */ -+#define SDRAM_TRFC_1G 120 /* ns tRfc for dens 1GB */ -+#define SDRAM_TR2R_CYC 1 /* cycle for tR2r */ -+#define SDRAM_TR2WW2R_CYC 1 /* cycle for tR2wW2r */ -+ -+/* typedefs */ -+ -+/* enumeration for memory types */ -+typedef enum _mvMemoryType -+{ -+ MEM_TYPE_SDRAM, -+ MEM_TYPE_DDR1, -+ MEM_TYPE_DDR2 -+}MV_MEMORY_TYPE; -+ -+/* enumeration for DDR1 supported CAS Latencies */ -+typedef enum _mvDimmDdr1Cas -+{ -+ DDR1_CL_1_5 = 0x02, -+ DDR1_CL_2 = 0x04, -+ DDR1_CL_2_5 = 0x08, -+ DDR1_CL_3 = 0x10, -+ DDR1_CL_4 = 0x40, -+ DDR1_CL_FAULT -+} MV_DIMM_DDR1_CAS; -+ -+/* enumeration for DDR2 supported CAS Latencies */ -+typedef enum _mvDimmDdr2Cas -+{ -+ DDR2_CL_3 = 0x08, -+ DDR2_CL_4 = 0x10, -+ DDR2_CL_5 = 0x20, -+ DDR2_CL_FAULT -+} MV_DIMM_DDR2_CAS; -+ -+ -+typedef struct _mvDramBankInfo -+{ -+ MV_MEMORY_TYPE memoryType; /* DDR1, DDR2 or SDRAM */ -+ -+ /* DIMM dimensions */ -+ MV_U32 numOfRowAddr; -+ MV_U32 numOfColAddr; -+ MV_U32 dataWidth; -+ MV_U32 errorCheckType; /* ECC , PARITY..*/ -+ MV_U32 sdramWidth; /* 4,8,16 or 32 */ -+ MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ -+ MV_U32 burstLengthSupported; -+ MV_U32 numOfBanksOnEachDevice; -+ MV_U32 suportedCasLatencies; -+ MV_U32 refreshInterval; -+ -+ /* DIMM timing parameters */ -+ MV_U32 minCycleTimeAtMaxCasLatPs; -+ MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; -+ MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; -+ MV_U32 minRowPrechargeTime; -+ MV_U32 minRowActiveToRowActive; -+ MV_U32 minRasToCasDelay; -+ MV_U32 minRasPulseWidth; -+ MV_U32 minWriteRecoveryTime; /* DDR2 only */ -+ MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ -+ MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ -+ MV_U32 minRefreshToActiveCmd; /* DDR2 only */ -+ -+ /* Parameters calculated from the extracted DIMM information */ -+ MV_U32 size; -+ MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit */ -+ MV_U32 numberOfDevices; -+ -+ /* DIMM attributes (MV_TRUE for yes) */ -+ MV_BOOL registeredAddrAndControlInputs; -+ -+}MV_DRAM_BANK_INFO; -+ -+/* This structure describes CPU interface address decode window */ -+typedef struct _mvDramIfDecWin -+{ -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+}MV_DRAM_DEC_WIN; -+ -+#include "ddr1_2/mvDram.h" -+ -+/* mvDramIf.h API list */ -+MV_VOID mvDramIfBasicAsmInit(MV_VOID); -+MV_STATUS mvDramIfDetect(MV_U32 forcedCl); -+MV_VOID _mvDramIfConfig(MV_VOID); -+ -+MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); -+MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); -+MV_STATUS mvDramIfWinEnable(MV_TARGET target,MV_BOOL enable); -+MV_32 mvDramIfBankSizeGet(MV_U32 bankNum); -+MV_32 mvDramIfBankBaseGet(MV_U32 bankNum); -+MV_32 mvDramIfSizeGet(MV_VOID); -+ -+#if 0 -+MV_STATUS mvDramIfMbusCtrlSet(MV_XBAR_TARGET *pPizzaArbArray); -+MV_STATUS mvDramIfMbusToutSet(MV_U32 timeout, MV_BOOL enable); -+#endif -+ -+#endif /* __INCmvDramIfh */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h 2010-11-09 20:28:10.772495655 +0100 -@@ -0,0 +1,306 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvDramIfRegsh -+#define __INCmvDramIfRegsh -+ -+ -+/* DDR SDRAM Controller Address Decode Registers */ -+/* SDRAM CSn Base Address Register (SCBAR) */ -+#define SDRAM_BASE_ADDR_REG(csNum) (0x1500 + (csNum * 8)) -+#define SCBAR_BASE_OFFS 16 -+#define SCBAR_BASE_MASK (0xffff << SCBAR_BASE_OFFS) -+#define SCBAR_BASE_ALIGNMENT 0x10000 -+ -+/* SDRAM CSn Size Register (SCSR) */ -+#define SDRAM_SIZE_REG(csNum) (0x1504 + (csNum * 8)) -+#define SCSR_WIN_EN BIT0 -+#define SCSR_SIZE_OFFS 16 -+#define SCSR_SIZE_MASK (0xffff << SCSR_SIZE_OFFS) -+#define SCSR_SIZE_ALIGNMENT 0x10000 -+ -+/* configuration register */ -+#define SDRAM_CONFIG_REG 0x1400 -+#define SDRAM_REFRESH_OFFS 0 -+#define SDRAM_REFRESH_MAX 0x3000 -+#define SDRAM_REFRESH_MASK (SDRAM_REFRESH_MAX << SDRAM_REFRESH_OFFS) -+#define SDRAM_DWIDTH_OFFS 14 -+#define SDRAM_DWIDTH_MASK (3 << SDRAM_DWIDTH_OFFS) -+#define SDRAM_DWIDTH_16BIT (1 << SDRAM_DWIDTH_OFFS) -+#define SDRAM_DWIDTH_32BIT (2 << SDRAM_DWIDTH_OFFS) -+#define SDRAM_DTYPE_OFFS 16 -+#define SDRAM_DTYPE_MASK (1 << SDRAM_DTYPE_OFFS) -+#define SDRAM_DTYPE_DDR1 (0 << SDRAM_DTYPE_OFFS) -+#define SDRAM_DTYPE_DDR2 (1 << SDRAM_DTYPE_OFFS) -+#define SDRAM_REGISTERED (1 << 17) -+#define SDRAM_PERR_OFFS 18 -+#define SDRAM_PERR_MASK (1 << SDRAM_PERR_OFFS) -+#define SDRAM_PERR_NO_WRITE (0 << SDRAM_PERR_OFFS) -+#define SDRAM_PERR_WRITE (1 << SDRAM_PERR_OFFS) -+#define SDRAM_DCFG_OFFS 20 -+#define SDRAM_DCFG_MASK (0x3 << SDRAM_DCFG_OFFS) -+#define SDRAM_DCFG_X16_DEV (1 << SDRAM_DCFG_OFFS) -+#define SDRAM_DCFG_X8_DEV (2 << SDRAM_DCFG_OFFS) -+#define SDRAM_SRMODE (1 << 24) -+#define SDRAM_SRCLK_OFFS 25 -+#define SDRAM_SRCLK_MASK (1 << SDRAM_SRCLK_OFFS) -+#define SDRAM_SRCLK_KEPT (0 << SDRAM_SRCLK_OFFS) -+#define SDRAM_SRCLK_GATED (1 << SDRAM_SRCLK_OFFS) -+#define SDRAM_CATTH_OFFS 26 -+#define SDRAM_CATTHR_EN (1 << SDRAM_CATTH_OFFS) -+ -+ -+/* dunit control register */ -+#define SDRAM_DUNIT_CTRL_REG 0x1404 -+#define SDRAM_CTRL_POS_OFFS 6 -+#define SDRAM_CTRL_POS_FALL (0 << SDRAM_CTRL_POS_OFFS) -+#define SDRAM_CTRL_POS_RISE (1 << SDRAM_CTRL_POS_OFFS) -+#define SDRAM_CLK1DRV_OFFS 12 -+#define SDRAM_CLK1DRV_MASK (1 << SDRAM_CLK1DRV_OFFS) -+#define SDRAM_CLK1DRV_HIGH_Z (0 << SDRAM_CLK1DRV_OFFS) -+#define SDRAM_CLK1DRV_NORMAL (1 << SDRAM_CLK1DRV_OFFS) -+#define SDRAM_LOCKEN_OFFS 18 -+#define SDRAM_LOCKEN_MASK (1 << SDRAM_LOCKEN_OFFS) -+#define SDRAM_LOCKEN_DISABLE (0 << SDRAM_LOCKEN_OFFS) -+#define SDRAM_LOCKEN_ENABLE (1 << SDRAM_LOCKEN_OFFS) -+#define SDRAM_ST_BURST_DEL_OFFS 24 -+#define SDRAM_ST_BURST_DEL_MAX 0xf -+#define SDRAM_ST_BURST_DEL_MASK (SDRAM_ST_BURST_DEL_MAX< busClkPs) -+ { -+ mvOsOutput("Dram: ERR. Bank %d doesn't support memory clock!!!\n", i); -+ return MV_ERROR; -+ } -+ -+ /* All banks must support registry in order to activate it */ -+ if(bankInfo[i].registeredAddrAndControlInputs != -+ bankInfo[0].registeredAddrAndControlInputs) -+ { -+ mvOsOutput("Dram: ERR. different Registered settings !!!\n"); -+ return MV_ERROR; -+ } -+ -+ /* All banks must support same ECC mode */ -+ if(bankInfo[i].errorCheckType != -+ bankInfo[0].errorCheckType) -+ { -+ mvOsOutput("Dram: ERR. different ECC settings !!!\n"); -+ return MV_ERROR; -+ } -+ -+ } -+ else -+ { -+ if( i == 0 ) /* bank 0 doesn't exist */ -+ { -+ mvOsOutput("Dram: ERR. Fail to detect bank 0 !!!\n"); -+ return MV_ERROR; -+ } -+ else -+ { -+ DB(mvOsPrintf("Dram: Could not find bank %d\n", i)); -+ bankInfo[i].size = 0; /* Mark this bank as non exist */ -+ } -+ } -+ } -+ -+#ifdef MV_INCLUDE_SDRAM_CS2 -+ if (bankInfo[SDRAM_CS0].size < bankInfo[SDRAM_CS2].size) -+ { -+ MV_DRAM_CS_order[0] = SDRAM_CS2; -+ MV_DRAM_CS_order[1] = SDRAM_CS3; -+ MV_DRAM_CS_order[2] = SDRAM_CS0; -+ MV_DRAM_CS_order[3] = SDRAM_CS1; -+ DRAM_CS_Order[0] = SDRAM_CS2; -+ DRAM_CS_Order[1] = SDRAM_CS3; -+ DRAM_CS_Order[2] = SDRAM_CS0; -+ DRAM_CS_Order[3] = SDRAM_CS1; -+ -+ } -+ else -+#endif -+ { -+ MV_DRAM_CS_order[0] = SDRAM_CS0; -+ MV_DRAM_CS_order[1] = SDRAM_CS1; -+ DRAM_CS_Order[0] = SDRAM_CS0; -+ DRAM_CS_Order[1] = SDRAM_CS1; -+#ifdef MV_INCLUDE_SDRAM_CS2 -+ MV_DRAM_CS_order[2] = SDRAM_CS2; -+ MV_DRAM_CS_order[3] = SDRAM_CS3; -+ DRAM_CS_Order[2] = SDRAM_CS2; -+ DRAM_CS_Order[3] = SDRAM_CS3; -+#endif -+ } -+ -+ for(j = 0; j < MV_DRAM_MAX_CS; j++) -+ { -+ i = MV_DRAM_CS_order[j]; -+ -+ if (0 == bankInfo[i].size) -+ continue; -+ -+ /* Init the CPU window decode */ -+ /* Note that the Dimm width might be different then the device DRAM width */ -+#ifdef MV78XX0 -+ temp = MV_REG_READ(SDRAM_CONFIG_REG); -+ deviceW = ((temp & SDRAM_DWIDTH_MASK) == SDRAM_DWIDTH_32BIT )? 32 : 64; -+#else -+ deviceW = 16 /* KW family */; -+#endif -+ dimmW = bankInfo[0].dataWidth - (bankInfo[0].dataWidth % 16); -+ size = ((bankInfo[i].size << 20) / (dimmW/deviceW)); -+ -+ /* We can not change DRAM window settings while excecuting */ -+ /* code from it. That is why we skip the DRAM CS[0], saving */ -+ /* it to the ROM configuration routine */ -+ -+ numOfAllDevices += bankInfo[i].numberOfDevices; -+ if (i == MV_DRAM_CS_order[0]) -+ { -+ MV_U32 sizeToReg; -+ /* Translate the given window size to register format */ -+ sizeToReg = ctrlSizeToReg(size, SCSR_SIZE_ALIGNMENT); -+ /* Size parameter validity check. */ -+ if (-1 == sizeToReg) -+ { -+ mvOsOutput("DRAM: mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n" -+ ,i); -+ return MV_BAD_PARAM; -+ } -+ -+ DB(mvOsPrintf("Dram: Bank 0 Size - %x\n",sizeToReg);) -+ sizeToReg = (sizeToReg << SCSR_SIZE_OFFS); -+ sizeToReg |= SCSR_WIN_EN; -+ MV_REG_WRITE(DRAM_BUF_REG0, sizeToReg); -+ } -+ else -+ { -+ dramDecWin.addrWin.baseLow = base; -+ dramDecWin.addrWin.size = size; -+ dramDecWin.enable = MV_TRUE; -+ DB(mvOsPrintf("Dram: Enable window %d base 0x%x, size=0x%x\n",i, base, size)); -+ -+ /* Check if the DRAM size is more then 3GByte */ -+ if (base < 0xC0000000) -+ { -+ DB(mvOsPrintf("Dram: Enable window %d base 0x%x, size=0x%x\n",i, base, size)); -+ if (MV_OK != mvCpuIfTargetWinSet(i, &dramDecWin)) -+ { -+ mvOsPrintf("Dram: ERR. Fail to set bank %d!!!\n", SDRAM_CS0 + i); -+ return MV_ERROR; -+ } -+ } -+ } -+ -+ base += size; -+ -+ /* update the suportedCasLatencies mask */ -+ bankInfo[0].suportedCasLatencies &= bankInfo[i].suportedCasLatencies; -+ } -+ -+ /* calculate minimum CAS */ -+ minCas = minCasCalc(&bankInfo[0], &bankInfo[2], busClk, forcedCl); -+ if (0 == minCas) -+ { -+ mvOsOutput("Dram: Warn: Could not find CAS compatible to SysClk %dMhz\n", -+ (busClk / 1000000)); -+ -+ minCas = DDR2_CL_4; /* Continue with this CAS */ -+ mvOsOutput("Set default CAS latency 4\n"); -+ } -+ -+ /* calc SDRAM_CONFIG_REG and save it to temp register */ -+ temp = sdramConfigRegCalc(&bankInfo[0],&bankInfo[2], busClk); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. sdramConfigRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ -+ /* check if ECC is enabled by the user */ -+ if(eccDisable) -+ { -+ /* turn off ECC*/ -+ temp &= ~BIT18; -+ } -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG1, temp); -+ -+ /* calc SDRAM_MODE_REG and save it to temp register */ -+ temp = sdramModeRegCalc(minCas); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. sdramModeRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: sdramModeRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG2, temp); -+ -+ /* calc SDRAM_EXTENDED_MODE_REG and save it to temp register */ -+ temp = sdramExtModeRegCalc(&bankInfo[0], busClk); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. sdramExtModeRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: sdramExtModeRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG10, temp); -+ -+ /* calc D_UNIT_CONTROL_LOW and save it to temp register */ -+ TTMode = MV_FALSE; -+ DB(mvOsPrintf("Dram: numOfAllDevices = %x\n",numOfAllDevices);) -+ if( (numOfAllDevices > 9) && (bankInfo[0].registeredAddrAndControlInputs == MV_FALSE) ) -+ { -+ if ( ( (numOfAllDevices > 9) && (busClk > MV_BOARD_SYSCLK_200MHZ) ) || -+ (numOfAllDevices > 18) ) -+ { -+ mvOsOutput("Enable 2T "); -+ TTMode = MV_TRUE; -+ } -+ } -+ -+ temp = dunitCtrlLowRegCalc(&bankInfo[0], minCas, busClk, TTMode ); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. dunitCtrlLowRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: dunitCtrlLowRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG3, temp); -+ -+ /* calc D_UNIT_CONTROL_HIGH and save it to temp register */ -+ temp = dunitCtrlHighRegCalc(&bankInfo[0], busClk); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. dunitCtrlHighRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: dunitCtrlHighRegCalc - %x\n",temp);) -+ /* check if ECC is enabled by the user */ -+ if(eccDisable) -+ { -+ /* turn off sample stage if no ecc */ -+ temp &= ~SDRAM__D2P_EN;; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG13, temp); -+ -+ /* calc SDRAM_ADDR_CTRL_REG and save it to temp register */ -+ temp = sdramAddrCtrlRegCalc(&bankInfo[0],&bankInfo[2]); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. sdramAddrCtrlRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: sdramAddrCtrlRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG4, temp); -+ -+ /* calc SDRAM_TIMING_CTRL_LOW_REG and save it to temp register */ -+ temp = sdramTimeCtrlLowRegCalc(&bankInfo[0], minCas, busClk); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. sdramTimeCtrlLowRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: sdramTimeCtrlLowRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG5, temp); -+ -+ /* calc SDRAM_TIMING_CTRL_HIGH_REG and save it to temp register */ -+ temp = sdramTimeCtrlHighRegCalc(&bankInfo[0], busClk); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. sdramTimeCtrlHighRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: sdramTimeCtrlHighRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG6, temp); -+ -+ sdramDDr2OdtConfig(bankInfo); -+ -+ /* calc DDR2_SDRAM_TIMING_LOW_REG and save it to temp register */ -+ temp = sdramDdr2TimeLoRegCalc(minCas); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. sdramDdr2TimeLoRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: sdramDdr2TimeLoRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG11, temp); -+ -+ /* calc DDR2_SDRAM_TIMING_HIGH_REG and save it to temp register */ -+ temp = sdramDdr2TimeHiRegCalc(minCas); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. sdramDdr2TimeHiRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: sdramDdr2TimeHiRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG12, temp); -+#endif -+ -+ /* Note that DDR SDRAM Address/Control and Data pad calibration */ -+ /* settings is done in mvSdramIfConfig.s */ -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvDramIfBankBaseGet - Get DRAM interface bank base. -+* -+* DESCRIPTION: -+* This function returns the 32 bit base address of a given DRAM bank. -+* -+* INPUT: -+* bankNum - Bank number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* DRAM bank size. If bank is disabled or paramter is invalid, the -+* function returns -1. -+* -+*******************************************************************************/ -+MV_U32 mvDramIfBankBaseGet(MV_U32 bankNum) -+{ -+ DB(mvOsPrintf("Dram: mvDramIfBankBaseGet Bank %d base addr is %x \n", -+ bankNum, mvCpuIfTargetWinBaseLowGet(SDRAM_CS0 + bankNum))); -+ return mvCpuIfTargetWinBaseLowGet(SDRAM_CS0 + bankNum); -+} -+ -+/******************************************************************************* -+* mvDramIfBankSizeGet - Get DRAM interface bank size. -+* -+* DESCRIPTION: -+* This function returns the size of a given DRAM bank. -+* -+* INPUT: -+* bankNum - Bank number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* DRAM bank size. If bank is disabled the function return '0'. In case -+* or paramter is invalid, the function returns -1. -+* -+*******************************************************************************/ -+MV_U32 mvDramIfBankSizeGet(MV_U32 bankNum) -+{ -+ DB(mvOsPrintf("Dram: mvDramIfBankSizeGet Bank %d size is %x \n", -+ bankNum, mvCpuIfTargetWinSizeGet(SDRAM_CS0 + bankNum))); -+ return mvCpuIfTargetWinSizeGet(SDRAM_CS0 + bankNum); -+} -+ -+ -+/******************************************************************************* -+* mvDramIfSizeGet - Get DRAM interface total size. -+* -+* DESCRIPTION: -+* This function get the DRAM total size. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* DRAM total size. In case or paramter is invalid, the function -+* returns -1. -+* -+*******************************************************************************/ -+MV_U32 mvDramIfSizeGet(MV_VOID) -+{ -+ MV_U32 size = 0, i; -+ -+ for(i = 0; i < MV_DRAM_MAX_CS; i++) -+ size += mvDramIfBankSizeGet(i); -+ -+ DB(mvOsPrintf("Dram: mvDramIfSizeGet size is %x \n",size)); -+ return size; -+} -+ -+/******************************************************************************* -+* mvDramIfSingleBitErrThresholdSet - Set single bit ECC threshold. -+* -+* DESCRIPTION: -+* The ECC single bit error threshold is the number of single bit -+* errors to happen before the Dunit generates an interrupt. -+* This function set single bit ECC threshold. -+* -+* INPUT: -+* threshold - threshold. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM if threshold is to big, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_STATUS mvDramIfSingleBitErrThresholdSet(MV_U32 threshold) -+{ -+ MV_U32 regVal; -+ -+ if (threshold > SECR_THRECC_MAX) -+ { -+ return MV_BAD_PARAM; -+ } -+ -+ regVal = MV_REG_READ(SDRAM_ECC_CONTROL_REG); -+ regVal &= ~SECR_THRECC_MASK; -+ regVal |= ((SECR_THRECC(threshold) & SECR_THRECC_MASK)); -+ MV_REG_WRITE(SDRAM_ECC_CONTROL_REG, regVal); -+ -+ return MV_OK; -+} -+ -+#ifndef MV_STATIC_DRAM_ON_BOARD -+/******************************************************************************* -+* minCasCalc - Calculate the Minimum CAS latency which can be used. -+* -+* DESCRIPTION: -+* Calculate the minimum CAS latency that can be used, base on the DRAM -+* parameters and the SDRAM bus Clock freq. -+* -+* INPUT: -+* busClk - the DRAM bus Clock. -+* pBankInfo - bank info parameters. -+* forcedCl - Forced CAS Latency multiplied by 10. If equal to zero, do not force. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* The minimum CAS Latency. The function returns 0 if max CAS latency -+* supported by banks is incompatible with system bus clock frequancy. -+* -+*******************************************************************************/ -+ -+static MV_U32 minCasCalc(MV_DRAM_BANK_INFO *pBankInfo,MV_DRAM_BANK_INFO *pBankInfo2, MV_U32 busClk, MV_U32 forcedCl) -+{ -+ MV_U32 count = 1, j; -+ MV_U32 busClkPs = 1000000000 / (busClk / 1000); /* in ps units */ -+ MV_U32 startBit, stopBit; -+ MV_U32 minCas0 = 0, minCas2 = 0; -+ -+ -+ /* DDR 2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * -+ Disco VI= * TBD | TBD | 5 | 4 | 3 | TBD | TBD | TBD * -+ Disco Duo= * TBD | 6 | 5 | 4 | 3 | TBD | TBD | TBD * -+ *********************************************************/ -+ -+ -+ /* If we are asked to use the forced CAL we change the suported CAL to be forcedCl only */ -+ if (forcedCl) -+ { -+ mvOsOutput("DRAM: Using forced CL %d.%d\n", (forcedCl / 10), (forcedCl % 10)); -+ -+ if (forcedCl == 30) -+ pBankInfo->suportedCasLatencies = 0x08; -+ else if (forcedCl == 40) -+ pBankInfo->suportedCasLatencies = 0x10; -+ else if (forcedCl == 50) -+ pBankInfo->suportedCasLatencies = 0x20; -+ else if (forcedCl == 60) -+ pBankInfo->suportedCasLatencies = 0x40; -+ else -+ { -+ mvOsPrintf("Forced CL %d.%d not supported. Set default CL 4\n", -+ (forcedCl / 10), (forcedCl % 10)); -+ pBankInfo->suportedCasLatencies = 0x10; -+ } -+ -+ return pBankInfo->suportedCasLatencies; -+ } -+ -+ /* go over the supported cas mask from Max Cas down and check if the */ -+ /* SysClk stands in its time requirments. */ -+ -+ DB(mvOsPrintf("Dram: minCasCalc supported mask = %x busClkPs = %x \n", -+ pBankInfo->suportedCasLatencies,busClkPs )); -+ count = 1; -+ for(j = 7; j > 0; j--) -+ { -+ if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) -+ { -+ /* Reset the bits for CL incompatible for the sysClk */ -+ switch (count) -+ { -+ case 1: -+ if (pBankInfo->minCycleTimeAtMaxCasLatPs > busClkPs) -+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ case 2: -+ if (pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps > busClkPs) -+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ case 3: -+ if (pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps > busClkPs) -+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ default: -+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); -+ break; -+ } -+ } -+ } -+ -+ DB(mvOsPrintf("Dram: minCasCalc support = %x (after SysCC calc)\n", -+ pBankInfo->suportedCasLatencies )); -+ -+ count = 1; -+ DB(mvOsPrintf("Dram2: minCasCalc supported mask = %x busClkPs = %x \n", -+ pBankInfo2->suportedCasLatencies,busClkPs )); -+ for(j = 7; j > 0; j--) -+ { -+ if((pBankInfo2->suportedCasLatencies >> j) & BIT0 ) -+ { -+ /* Reset the bits for CL incompatible for the sysClk */ -+ switch (count) -+ { -+ case 1: -+ if (pBankInfo2->minCycleTimeAtMaxCasLatPs > busClkPs) -+ pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ case 2: -+ if (pBankInfo2->minCycleTimeAtMaxCasLatMinus1Ps > busClkPs) -+ pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ case 3: -+ if (pBankInfo2->minCycleTimeAtMaxCasLatMinus2Ps > busClkPs) -+ pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ default: -+ pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); -+ break; -+ } -+ } -+ } -+ -+ DB(mvOsPrintf("Dram2: minCasCalc support = %x (after SysCC calc)\n", -+ pBankInfo2->suportedCasLatencies )); -+ -+ startBit = 3; /* DDR2 support CL start with CL3 (bit 3) */ -+ stopBit = 6; /* DDR2 support CL stops with CL6 (bit 6) */ -+ -+ for(j = startBit; j <= stopBit ; j++) -+ { -+ if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) -+ { -+ DB(mvOsPrintf("Dram: minCasCalc choose CAS %x \n",(BIT0 << j))); -+ minCas0 = (BIT0 << j); -+ break; -+ } -+ } -+ -+ for(j = startBit; j <= stopBit ; j++) -+ { -+ if((pBankInfo2->suportedCasLatencies >> j) & BIT0 ) -+ { -+ DB(mvOsPrintf("Dram: minCasCalc choose CAS %x \n",(BIT0 << j))); -+ minCas2 = (BIT0 << j); -+ break; -+ } -+ } -+ -+ if (minCas2 > minCas0) -+ return minCas2; -+ else -+ return minCas0; -+ -+ return 0; -+} -+ -+/******************************************************************************* -+* sdramConfigRegCalc - Calculate sdram config register -+* -+* DESCRIPTION: Calculate sdram config register optimized value based -+* on the bank info parameters. -+* -+* INPUT: -+* busClk - the DRAM bus Clock. -+* pBankInfo - sdram bank parameters -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram config reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramConfigRegCalc(MV_DRAM_BANK_INFO *pBankInfo,MV_DRAM_BANK_INFO *pBankInfo2, MV_U32 busClk) -+{ -+ MV_U32 sdramConfig = 0; -+ MV_U32 refreshPeriod; -+ -+ busClk /= 1000000; /* we work with busClk in MHz */ -+ -+ sdramConfig = MV_REG_READ(SDRAM_CONFIG_REG); -+ -+ /* figure out the memory refresh internal */ -+ switch (pBankInfo->refreshInterval & 0xf) -+ { -+ case 0x0: /* refresh period is 15.625 usec */ -+ refreshPeriod = 15625; -+ break; -+ case 0x1: /* refresh period is 3.9 usec */ -+ refreshPeriod = 3900; -+ break; -+ case 0x2: /* refresh period is 7.8 usec */ -+ refreshPeriod = 7800; -+ break; -+ case 0x3: /* refresh period is 31.3 usec */ -+ refreshPeriod = 31300; -+ break; -+ case 0x4: /* refresh period is 62.5 usec */ -+ refreshPeriod = 62500; -+ break; -+ case 0x5: /* refresh period is 125 usec */ -+ refreshPeriod = 125000; -+ break; -+ default: /* refresh period undefined */ -+ mvOsPrintf("Dram: ERR. DRAM refresh period is unknown!\n"); -+ return -1; -+ } -+ -+ /* Now the refreshPeriod is in register format value */ -+ refreshPeriod = (busClk * refreshPeriod) / 1000; -+ -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc calculated refresh interval %0x\n", -+ refreshPeriod)); -+ -+ /* make sure the refresh value is only 14 bits */ -+ if(refreshPeriod > SDRAM_REFRESH_MAX) -+ { -+ refreshPeriod = SDRAM_REFRESH_MAX; -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc adjusted refresh interval %0x\n", -+ refreshPeriod)); -+ } -+ -+ /* Clear the refresh field */ -+ sdramConfig &= ~SDRAM_REFRESH_MASK; -+ -+ /* Set new value to refresh field */ -+ sdramConfig |= (refreshPeriod & SDRAM_REFRESH_MASK); -+ -+ /* registered DRAM ? */ -+ if ( pBankInfo->registeredAddrAndControlInputs ) -+ { -+ /* it's registered DRAM, so set the reg. DRAM bit */ -+ sdramConfig |= SDRAM_REGISTERED; -+ DB(mvOsPrintf("DRAM Attribute: Registered address and control inputs.\n");) -+ } -+ -+ /* ECC and IERR support */ -+ sdramConfig &= ~SDRAM_ECC_MASK; /* Clear ECC field */ -+ sdramConfig &= ~SDRAM_IERR_MASK; /* Clear IErr field */ -+ -+ if ( pBankInfo->errorCheckType ) -+ { -+ sdramConfig |= SDRAM_ECC_EN; -+ sdramConfig |= SDRAM_IERR_REPORTE; -+ DB(mvOsPrintf("Dram: mvDramIfDetect Enabling ECC\n")); -+ } -+ else -+ { -+ sdramConfig |= SDRAM_ECC_DIS; -+ sdramConfig |= SDRAM_IERR_IGNORE; -+ DB(mvOsPrintf("Dram: mvDramIfDetect Disabling ECC!\n")); -+ } -+ /* Set static default settings */ -+ sdramConfig |= SDRAM_CONFIG_DV; -+ -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc set sdramConfig to 0x%x\n", -+ sdramConfig)); -+ -+ return sdramConfig; -+} -+ -+/******************************************************************************* -+* sdramModeRegCalc - Calculate sdram mode register -+* -+* DESCRIPTION: Calculate sdram mode register optimized value based -+* on the bank info parameters and the minCas. -+* -+* INPUT: -+* minCas - minimum CAS supported. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram mode reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramModeRegCalc(MV_U32 minCas) -+{ -+ MV_U32 sdramMode; -+ -+ sdramMode = MV_REG_READ(SDRAM_MODE_REG); -+ -+ /* Clear CAS Latency field */ -+ sdramMode &= ~SDRAM_CL_MASK; -+ -+ DB(mvOsPrintf("DRAM CAS Latency ");) -+ -+ switch (minCas) -+ { -+ case DDR2_CL_3: -+ sdramMode |= SDRAM_DDR2_CL_3; -+ DB(mvOsPrintf("3.\n");) -+ break; -+ case DDR2_CL_4: -+ sdramMode |= SDRAM_DDR2_CL_4; -+ DB(mvOsPrintf("4.\n");) -+ break; -+ case DDR2_CL_5: -+ sdramMode |= SDRAM_DDR2_CL_5; -+ DB(mvOsPrintf("5.\n");) -+ break; -+ case DDR2_CL_6: -+ sdramMode |= SDRAM_DDR2_CL_6; -+ DB(mvOsPrintf("6.\n");) -+ break; -+ default: -+ mvOsOutput("\nsdramModeRegCalc ERROR: Max. CL out of range\n"); -+ return -1; -+ } -+ -+ DB(mvOsPrintf("\nsdramModeRegCalc register 0x%x\n", sdramMode )); -+ -+ return sdramMode; -+} -+/******************************************************************************* -+* sdramExtModeRegCalc - Calculate sdram Extended mode register -+* -+* DESCRIPTION: -+* Return sdram Extended mode register value based -+* on the bank info parameters and bank presence. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* busClk - DRAM frequency -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram Extended mode reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramExtModeRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) -+{ -+ MV_U32 populateBanks = 0; -+ int bankNum; -+ -+ /* Represent the populate banks in binary form */ -+ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ if (0 != pBankInfo[bankNum].size) -+ { -+ populateBanks |= (1 << bankNum); -+ } -+ } -+ -+ switch(populateBanks) -+ { -+ case(BANK_PRESENT_CS0): -+ case(BANK_PRESENT_CS0_CS1): -+ return DDR_SDRAM_EXT_MODE_CS0_CS1_DV; -+ -+ case(BANK_PRESENT_CS0_CS2): -+ case(BANK_PRESENT_CS0_CS1_CS2): -+ case(BANK_PRESENT_CS0_CS2_CS3): -+ case(BANK_PRESENT_CS0_CS2_CS3_CS4): -+ if (busClk >= MV_BOARD_SYSCLK_267MHZ) -+ return DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV; -+ else -+ return DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV; -+ -+ default: -+ mvOsOutput("sdramExtModeRegCalc: Invalid DRAM bank presence\n"); -+ return -1; -+ } -+ return 0; -+} -+ -+/******************************************************************************* -+* dunitCtrlLowRegCalc - Calculate sdram dunit control low register -+* -+* DESCRIPTION: Calculate sdram dunit control low register optimized value based -+* on the bank info parameters and the minCas. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* minCas - minimum CAS supported. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram dunit control low reg value. -+* -+*******************************************************************************/ -+static MV_U32 dunitCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas, MV_U32 busClk, MV_STATUS TTMode) -+{ -+ MV_U32 dunitCtrlLow, cl; -+ MV_U32 sbOutR[4]={3,5,7,9} ; -+ MV_U32 sbOutU[4]={1,3,5,7} ; -+ -+ dunitCtrlLow = MV_REG_READ(SDRAM_DUNIT_CTRL_REG); -+ -+ DB(mvOsPrintf("Dram: dunitCtrlLowRegCalc\n")); -+ -+ /* Clear StBurstOutDel field */ -+ dunitCtrlLow &= ~SDRAM_SB_OUT_MASK; -+ -+ /* Clear StBurstInDel field */ -+ dunitCtrlLow &= ~SDRAM_SB_IN_MASK; -+ -+ /* Clear CtrlPos field */ -+ dunitCtrlLow &= ~SDRAM_CTRL_POS_MASK; -+ -+ /* Clear 2T field */ -+ dunitCtrlLow &= ~SDRAM_2T_MASK; -+ if (TTMode == MV_TRUE) -+ { -+ dunitCtrlLow |= SDRAM_2T_MODE; -+ } -+ -+ /* For proper sample of read data set the Dunit Control register's */ -+ /* stBurstInDel bits [27:24] */ -+ /* 200MHz - 267MHz None reg = CL + 1 */ -+ /* 200MHz - 267MHz reg = CL + 2 */ -+ /* > 267MHz None reg = CL + 2 */ -+ /* > 267MHz reg = CL + 3 */ -+ -+ /* For proper sample of read data set the Dunit Control register's */ -+ /* stBurstOutDel bits [23:20] */ -+ /********-********-********-********- -+ * CL=3 | CL=4 | CL=5 | CL=6 | -+ *********-********-********-********- -+ Not Reg. * 0001 | 0011 | 0101 | 0111 | -+ *********-********-********-********- -+ Registered * 0011 | 0101 | 0111 | 1001 | -+ *********-********-********-********/ -+ -+ /* Set Dunit Control low default value */ -+ dunitCtrlLow |= SDRAM_DUNIT_CTRL_LOW_DDR2_DV; -+ -+ switch (minCas) -+ { -+ case DDR2_CL_3: cl = 3; break; -+ case DDR2_CL_4: cl = 4; break; -+ case DDR2_CL_5: cl = 5; break; -+ case DDR2_CL_6: cl = 6; break; -+ default: -+ mvOsOutput("Dram: dunitCtrlLowRegCalc Max. CL out of range %d\n", minCas); -+ return -1; -+ } -+ -+ /* registerd DDR SDRAM? */ -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ { -+ dunitCtrlLow |= (sbOutR[cl-3]) << SDRAM_SB_OUT_DEL_OFFS; -+ } -+ else -+ { -+ dunitCtrlLow |= (sbOutU[cl-3]) << SDRAM_SB_OUT_DEL_OFFS; -+ } -+ -+ DB(mvOsPrintf("\n\ndunitCtrlLowRegCalc: CL = %d, frequencies=%d\n", cl, busClk)); -+ -+ if (busClk <= MV_BOARD_SYSCLK_267MHZ) -+ { -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ cl = cl + 2; -+ else -+ cl = cl + 1; -+ } -+ else -+ { -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ cl = cl + 3; -+ else -+ cl = cl + 2; -+ } -+ -+ DB(mvOsPrintf("dunitCtrlLowRegCalc: SDRAM_SB_IN_DEL_OFFS = %d \n", cl)); -+ dunitCtrlLow |= cl << SDRAM_SB_IN_DEL_OFFS; -+ -+ DB(mvOsPrintf("Dram: Reg dunit control low = %x\n", dunitCtrlLow )); -+ -+ return dunitCtrlLow; -+} -+ -+/******************************************************************************* -+* dunitCtrlHighRegCalc - Calculate sdram dunit control high register -+* -+* DESCRIPTION: Calculate sdram dunit control high register optimized value based -+* on the bus clock. -+* -+* INPUT: -+* busClk - DRAM frequency. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram dunit control high reg value. -+* -+*******************************************************************************/ -+static MV_U32 dunitCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) -+{ -+ MV_U32 dunitCtrlHigh; -+ dunitCtrlHigh = MV_REG_READ(SDRAM_DUNIT_CTRL_HI_REG); -+ if(busClk > MV_BOARD_SYSCLK_300MHZ) -+ dunitCtrlHigh |= SDRAM__P2D_EN; -+ else -+ dunitCtrlHigh &= ~SDRAM__P2D_EN; -+ -+ if(busClk > MV_BOARD_SYSCLK_267MHZ) -+ dunitCtrlHigh |= (SDRAM__WR_MESH_DELAY_EN | SDRAM__PUP_ZERO_SKEW_EN | SDRAM__ADD_HALF_FCC_EN); -+ -+ /* If ECC support we turn on D2P sample */ -+ dunitCtrlHigh &= ~SDRAM__D2P_EN; /* Clear D2P bit */ -+ if (( pBankInfo->errorCheckType ) && (busClk > MV_BOARD_SYSCLK_267MHZ)) -+ dunitCtrlHigh |= SDRAM__D2P_EN; -+ -+ return dunitCtrlHigh; -+} -+ -+/******************************************************************************* -+* sdramAddrCtrlRegCalc - Calculate sdram address control register -+* -+* DESCRIPTION: Calculate sdram address control register optimized value based -+* on the bank info parameters and the minCas. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram address control reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramAddrCtrlRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_DRAM_BANK_INFO *pBankInfoDIMM1) -+{ -+ MV_U32 addrCtrl = 0; -+ -+ if (pBankInfoDIMM1->size) -+ { -+ switch (pBankInfoDIMM1->sdramWidth) -+ { -+ case 4: /* memory is x4 */ -+ mvOsOutput("sdramAddrCtrlRegCalc: Error - x4 not supported!\n"); -+ return -1; -+ break; -+ case 8: /* memory is x8 */ -+ addrCtrl |= SDRAM_ADDRSEL_X8(2) | SDRAM_ADDRSEL_X8(3); -+ DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device DIMM2 width x8\n")); -+ break; -+ case 16: -+ addrCtrl |= SDRAM_ADDRSEL_X16(2) | SDRAM_ADDRSEL_X16(3); -+ DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device DIMM2 width x16\n")); -+ break; -+ default: /* memory width unsupported */ -+ mvOsOutput("sdramAddrCtrlRegCalc: ERR. DRAM chip width is unknown!\n"); -+ return -1; -+ } -+ } -+ -+ switch (pBankInfo->sdramWidth) -+ { -+ case 4: /* memory is x4 */ -+ mvOsOutput("sdramAddrCtrlRegCalc: Error - x4 not supported!\n"); -+ return -1; -+ break; -+ case 8: /* memory is x8 */ -+ addrCtrl |= SDRAM_ADDRSEL_X8(0) | SDRAM_ADDRSEL_X8(1); -+ DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device width x8\n")); -+ break; -+ case 16: -+ addrCtrl |= SDRAM_ADDRSEL_X16(0) | SDRAM_ADDRSEL_X16(1); -+ DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device width x16\n")); -+ break; -+ default: /* memory width unsupported */ -+ mvOsOutput("sdramAddrCtrlRegCalc: ERR. DRAM chip width is unknown!\n"); -+ return -1; -+ } -+ -+ /* Note that density is in MB units */ -+ switch (pBankInfo->deviceDensity) -+ { -+ case 256: /* 256 Mbit */ -+ DB(mvOsPrintf("DRAM Device Density 256Mbit\n")); -+ addrCtrl |= SDRAM_DSIZE_256Mb(0) | SDRAM_DSIZE_256Mb(1); -+ break; -+ case 512: /* 512 Mbit */ -+ DB(mvOsPrintf("DRAM Device Density 512Mbit\n")); -+ addrCtrl |= SDRAM_DSIZE_512Mb(0) | SDRAM_DSIZE_512Mb(1); -+ break; -+ case 1024: /* 1 Gbit */ -+ DB(mvOsPrintf("DRAM Device Density 1Gbit\n")); -+ addrCtrl |= SDRAM_DSIZE_1Gb(0) | SDRAM_DSIZE_1Gb(1); -+ break; -+ case 2048: /* 2 Gbit */ -+ DB(mvOsPrintf("DRAM Device Density 2Gbit\n")); -+ addrCtrl |= SDRAM_DSIZE_2Gb(0) | SDRAM_DSIZE_2Gb(1); -+ break; -+ default: -+ mvOsOutput("Dram: sdramAddrCtrl unsupported RAM-Device size %d\n", -+ pBankInfo->deviceDensity); -+ return -1; -+ } -+ -+ if (pBankInfoDIMM1->size) -+ { -+ switch (pBankInfoDIMM1->deviceDensity) -+ { -+ case 256: /* 256 Mbit */ -+ DB(mvOsPrintf("DIMM2: DRAM Device Density 256Mbit\n")); -+ addrCtrl |= SDRAM_DSIZE_256Mb(2) | SDRAM_DSIZE_256Mb(3); -+ break; -+ case 512: /* 512 Mbit */ -+ DB(mvOsPrintf("DIMM2: DRAM Device Density 512Mbit\n")); -+ addrCtrl |= SDRAM_DSIZE_512Mb(2) | SDRAM_DSIZE_512Mb(3); -+ break; -+ case 1024: /* 1 Gbit */ -+ DB(mvOsPrintf("DIMM2: DRAM Device Density 1Gbit\n")); -+ addrCtrl |= SDRAM_DSIZE_1Gb(2) | SDRAM_DSIZE_1Gb(3); -+ break; -+ case 2048: /* 2 Gbit */ -+ DB(mvOsPrintf("DIMM2: DRAM Device Density 2Gbit\n")); -+ addrCtrl |= SDRAM_DSIZE_2Gb(2) | SDRAM_DSIZE_2Gb(3); -+ break; -+ default: -+ mvOsOutput("DIMM2: Dram: sdramAddrCtrl unsupported RAM-Device size %d\n", -+ pBankInfoDIMM1->deviceDensity); -+ return -1; -+ } -+ } -+ /* SDRAM address control */ -+ DB(mvOsPrintf("Dram: setting sdram address control with: %x \n", addrCtrl)); -+ -+ return addrCtrl; -+} -+ -+/******************************************************************************* -+* sdramTimeCtrlLowRegCalc - Calculate sdram timing control low register -+* -+* DESCRIPTION: -+* This function calculates sdram timing control low register -+* optimized value based on the bank info parameters and the minCas. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* minCas - minimum CAS supported. -+* busClk - Bus clock -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram timing control low reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramTimeCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas, MV_U32 busClk) -+{ -+ MV_U32 tRp = 0; -+ MV_U32 tRrd = 0; -+ MV_U32 tRcd = 0; -+ MV_U32 tRas = 0; -+ MV_U32 tWr = 0; -+ MV_U32 tWtr = 0; -+ MV_U32 tRtp = 0; -+ MV_U32 timeCtrlLow = 0; -+ -+ MV_U32 bankNum; -+ -+ busClk = busClk / 1000000; /* In MHz */ -+ -+ /* Scan all DRAM banks to find maximum timing values */ -+ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ tRp = MV_MAX(tRp, pBankInfo[bankNum].minRowPrechargeTime); -+ tRrd = MV_MAX(tRrd, pBankInfo[bankNum].minRowActiveToRowActive); -+ tRcd = MV_MAX(tRcd, pBankInfo[bankNum].minRasToCasDelay); -+ tRas = MV_MAX(tRas, pBankInfo[bankNum].minRasPulseWidth); -+ } -+ -+ /* Extract timing (in ns) from SPD value. We ignore the tenth ns part. */ -+ /* by shifting the data two bits right. */ -+ tRp = tRp >> 2; /* For example 0x50 -> 20ns */ -+ tRrd = tRrd >> 2; -+ tRcd = tRcd >> 2; -+ -+ /* Extract clock cycles from time parameter. We need to round up */ -+ tRp = ((busClk * tRp) / 1000) + (((busClk * tRp) % 1000) ? 1 : 0); -+ DB(mvOsPrintf("Dram Timing Low: tRp = %d ", tRp)); -+ tRrd = ((busClk * tRrd) / 1000) + (((busClk * tRrd) % 1000) ? 1 : 0); -+ /* JEDEC min reqeirments tRrd = 2 */ -+ if (tRrd < 2) -+ tRrd = 2; -+ DB(mvOsPrintf("tRrd = %d ", tRrd)); -+ tRcd = ((busClk * tRcd) / 1000) + (((busClk * tRcd) % 1000) ? 1 : 0); -+ DB(mvOsPrintf("tRcd = %d ", tRcd)); -+ tRas = ((busClk * tRas) / 1000) + (((busClk * tRas) % 1000) ? 1 : 0); -+ DB(mvOsPrintf("tRas = %d ", tRas)); -+ -+ /* tWr and tWtr is different for DDR1 and DDR2. tRtp is only for DDR2 */ -+ /* Scan all DRAM banks to find maximum timing values */ -+ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ tWr = MV_MAX(tWr, pBankInfo[bankNum].minWriteRecoveryTime); -+ tWtr = MV_MAX(tWtr, pBankInfo[bankNum].minWriteToReadCmdDelay); -+ tRtp = MV_MAX(tRtp, pBankInfo[bankNum].minReadToPrechCmdDelay); -+ } -+ -+ /* Extract timing (in ns) from SPD value. We ignore the tenth ns */ -+ /* part by shifting the data two bits right. */ -+ tWr = tWr >> 2; /* For example 0x50 -> 20ns */ -+ tWtr = tWtr >> 2; -+ tRtp = tRtp >> 2; -+ /* Extract clock cycles from time parameter. We need to round up */ -+ tWr = ((busClk * tWr) / 1000) + (((busClk * tWr) % 1000) ? 1 : 0); -+ DB(mvOsPrintf("tWr = %d ", tWr)); -+ tWtr = ((busClk * tWtr) / 1000) + (((busClk * tWtr) % 1000) ? 1 : 0); -+ /* JEDEC min reqeirments tWtr = 2 */ -+ if (tWtr < 2) -+ tWtr = 2; -+ DB(mvOsPrintf("tWtr = %d ", tWtr)); -+ tRtp = ((busClk * tRtp) / 1000) + (((busClk * tRtp) % 1000) ? 1 : 0); -+ /* JEDEC min reqeirments tRtp = 2 */ -+ if (tRtp < 2) -+ tRtp = 2; -+ DB(mvOsPrintf("tRtp = %d ", tRtp)); -+ -+ /* Note: value of 0 in register means one cycle, 1 means two and so on */ -+ timeCtrlLow = (((tRp - 1) << SDRAM_TRP_OFFS) | -+ ((tRrd - 1) << SDRAM_TRRD_OFFS) | -+ ((tRcd - 1) << SDRAM_TRCD_OFFS) | -+ (((tRas - 1) << SDRAM_TRAS_OFFS) & SDRAM_TRAS_MASK)| -+ ((tWr - 1) << SDRAM_TWR_OFFS) | -+ ((tWtr - 1) << SDRAM_TWTR_OFFS) | -+ ((tRtp - 1) << SDRAM_TRTP_OFFS)); -+ -+ /* Check extended tRas bit */ -+ if ((tRas - 1) & BIT4) -+ timeCtrlLow |= (1 << SDRAM_EXT_TRAS_OFFS); -+ -+ return timeCtrlLow; -+} -+ -+/******************************************************************************* -+* sdramTimeCtrlHighRegCalc - Calculate sdram timing control high register -+* -+* DESCRIPTION: -+* This function calculates sdram timing control high register -+* optimized value based on the bank info parameters and the bus clock. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* busClk - Bus clock -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram timing control high reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramTimeCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) -+{ -+ MV_U32 tRfc; -+ MV_U32 timingHigh; -+ MV_U32 timeNs = 0; -+ MV_U32 bankNum; -+ -+ busClk = busClk / 1000000; /* In MHz */ -+ -+ /* Set DDR timing high register static configuration bits */ -+ timingHigh = MV_REG_READ(SDRAM_TIMING_CTRL_HIGH_REG); -+ -+ /* Set DDR timing high register default value */ -+ timingHigh |= SDRAM_TIMING_CTRL_HIGH_REG_DV; -+ -+ /* Clear tRfc field */ -+ timingHigh &= ~SDRAM_TRFC_MASK; -+ -+ /* Scan all DRAM banks to find maximum timing values */ -+ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ timeNs = MV_MAX(timeNs, pBankInfo[bankNum].minRefreshToActiveCmd); -+ DB(mvOsPrintf("Dram: Timing High: minRefreshToActiveCmd = %d\n", -+ pBankInfo[bankNum].minRefreshToActiveCmd)); -+ } -+ if(busClk >= 333 && mvCtrlModelGet() == MV_78XX0_A1_REV) -+ { -+ timingHigh |= 0x1 << SDRAM_TR2W_W2R_OFFS; -+ } -+ -+ tRfc = ((busClk * timeNs) / 1000) + (((busClk * timeNs) % 1000) ? 1 : 0); -+ /* Note: value of 0 in register means one cycle, 1 means two and so on */ -+ DB(mvOsPrintf("Dram: Timing High: tRfc = %d\n", tRfc)); -+ timingHigh |= (((tRfc - 1) & SDRAM_TRFC_MASK) << SDRAM_TRFC_OFFS); -+ DB(mvOsPrintf("Dram: Timing High: tRfc = %d\n", tRfc)); -+ -+ /* SDRAM timing high */ -+ DB(mvOsPrintf("Dram: setting timing high with: %x \n", timingHigh)); -+ -+ return timingHigh; -+} -+/******************************************************************************* -+* sdramDDr2OdtConfig - Set DRAM DDR2 On Die Termination registers. -+* -+* DESCRIPTION: -+* This function config DDR2 On Die Termination (ODT) registers. -+* -+* INPUT: -+* pBankInfo - bank info parameters. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* None -+*******************************************************************************/ -+static void sdramDDr2OdtConfig(MV_DRAM_BANK_INFO *pBankInfo) -+{ -+ MV_U32 populateBanks = 0; -+ MV_U32 odtCtrlLow, odtCtrlHigh, dunitOdtCtrl; -+ int bankNum; -+ -+ /* Represent the populate banks in binary form */ -+ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ if (0 != pBankInfo[bankNum].size) -+ { -+ populateBanks |= (1 << bankNum); -+ } -+ } -+ -+ switch(populateBanks) -+ { -+ case(BANK_PRESENT_CS0): -+ case(BANK_PRESENT_CS0_CS1): -+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS1_DV; -+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS1_DV; -+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV; -+ break; -+ case(BANK_PRESENT_CS0_CS2): -+ case(BANK_PRESENT_CS0_CS1_CS2): -+ case(BANK_PRESENT_CS0_CS2_CS3): -+ case(BANK_PRESENT_CS0_CS2_CS3_CS4): -+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV; -+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS1_CS2_CS3_DV; -+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV; -+ break; -+ default: -+ DB(mvOsPrintf("sdramDDr2OdtConfig: Invalid DRAM bank presence\n")); -+ return; -+ } -+ /* DDR2 SDRAM ODT ctrl low */ -+ DB(mvOsPrintf("Dram: DDR2 setting ODT ctrl low with: %x \n", odtCtrlLow)); -+ MV_REG_WRITE(DRAM_BUF_REG7, odtCtrlLow); -+ -+ /* DDR2 SDRAM ODT ctrl high */ -+ DB(mvOsPrintf("Dram: DDR2 setting ODT ctrl high with: %x \n", odtCtrlHigh)); -+ MV_REG_WRITE(DRAM_BUF_REG8, odtCtrlHigh); -+ -+ /* DDR2 DUNIT ODT ctrl */ -+ if ( ((mvCtrlModelGet() == MV_78XX0_DEV_ID) && (mvCtrlRevGet() == MV_78XX0_Y0_REV)) || -+ (mvCtrlModelGet() == MV_76100_DEV_ID) || -+ (mvCtrlModelGet() == MV_78100_DEV_ID) || -+ (mvCtrlModelGet() == MV_78200_DEV_ID) ) -+ dunitOdtCtrl &= ~(BIT9|BIT8); /* Clear ODT always on */ -+ -+ DB(mvOsPrintf("DUNIT: DDR2 setting ODT ctrl with: %x \n", dunitOdtCtrl)); -+ MV_REG_WRITE(DRAM_BUF_REG9, dunitOdtCtrl); -+ return; -+} -+/******************************************************************************* -+* sdramDdr2TimeLoRegCalc - Set DDR2 DRAM Timing Low registers. -+* -+* DESCRIPTION: -+* This function config DDR2 DRAM Timing low registers. -+* -+* INPUT: -+* minCas - minimum CAS supported. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* DDR2 sdram timing low reg value. -+*******************************************************************************/ -+static MV_U32 sdramDdr2TimeLoRegCalc(MV_U32 minCas) -+{ -+ MV_U8 cl = -1; -+ MV_U32 ddr2TimeLoReg; -+ -+ /* read and clear the feilds we are going to set */ -+ ddr2TimeLoReg = MV_REG_READ(SDRAM_DDR2_TIMING_LO_REG); -+ ddr2TimeLoReg &= ~(SD2TLR_TODT_ON_RD_MASK | -+ SD2TLR_TODT_OFF_RD_MASK | -+ SD2TLR_TODT_ON_CTRL_RD_MASK | -+ SD2TLR_TODT_OFF_CTRL_RD_MASK); -+ -+ if( minCas == DDR2_CL_3 ) -+ { -+ cl = 3; -+ } -+ else if( minCas == DDR2_CL_4 ) -+ { -+ cl = 4; -+ } -+ else if( minCas == DDR2_CL_5 ) -+ { -+ cl = 5; -+ } -+ else if( minCas == DDR2_CL_6 ) -+ { -+ cl = 6; -+ } -+ else -+ { -+ DB(mvOsPrintf("sdramDdr2TimeLoRegCalc: CAS latency %d unsupported. using CAS latency 4\n", -+ minCas)); -+ cl = 4; -+ } -+ -+ ddr2TimeLoReg |= ((cl-3) << SD2TLR_TODT_ON_RD_OFFS); -+ ddr2TimeLoReg |= ( cl << SD2TLR_TODT_OFF_RD_OFFS); -+ ddr2TimeLoReg |= ( cl << SD2TLR_TODT_ON_CTRL_RD_OFFS); -+ ddr2TimeLoReg |= ((cl+3) << SD2TLR_TODT_OFF_CTRL_RD_OFFS); -+ -+ /* DDR2 SDRAM timing low */ -+ DB(mvOsPrintf("Dram: DDR2 setting timing low with: %x \n", ddr2TimeLoReg)); -+ -+ return ddr2TimeLoReg; -+} -+ -+/******************************************************************************* -+* sdramDdr2TimeHiRegCalc - Set DDR2 DRAM Timing High registers. -+* -+* DESCRIPTION: -+* This function config DDR2 DRAM Timing high registers. -+* -+* INPUT: -+* minCas - minimum CAS supported. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* DDR2 sdram timing high reg value. -+*******************************************************************************/ -+static MV_U32 sdramDdr2TimeHiRegCalc(MV_U32 minCas) -+{ -+ MV_U8 cl = -1; -+ MV_U32 ddr2TimeHiReg; -+ -+ /* read and clear the feilds we are going to set */ -+ ddr2TimeHiReg = MV_REG_READ(SDRAM_DDR2_TIMING_HI_REG); -+ ddr2TimeHiReg &= ~(SD2THR_TODT_ON_WR_MASK | -+ SD2THR_TODT_OFF_WR_MASK | -+ SD2THR_TODT_ON_CTRL_WR_MASK | -+ SD2THR_TODT_OFF_CTRL_WR_MASK); -+ -+ if( minCas == DDR2_CL_3 ) -+ { -+ cl = 3; -+ } -+ else if( minCas == DDR2_CL_4 ) -+ { -+ cl = 4; -+ } -+ else if( minCas == DDR2_CL_5 ) -+ { -+ cl = 5; -+ } -+ else if( minCas == DDR2_CL_6 ) -+ { -+ cl = 6; -+ } -+ else -+ { -+ mvOsOutput("sdramDdr2TimeHiRegCalc: CAS latency %d unsupported. using CAS latency 4\n", -+ minCas); -+ cl = 4; -+ } -+ -+ ddr2TimeHiReg |= ((cl-3) << SD2THR_TODT_ON_WR_OFFS); -+ ddr2TimeHiReg |= ( cl << SD2THR_TODT_OFF_WR_OFFS); -+ ddr2TimeHiReg |= ( cl << SD2THR_TODT_ON_CTRL_WR_OFFS); -+ ddr2TimeHiReg |= ((cl+3) << SD2THR_TODT_OFF_CTRL_WR_OFFS); -+ -+ /* DDR2 SDRAM timin high */ -+ DB(mvOsPrintf("Dram: DDR2 setting timing high with: %x \n", ddr2TimeHiReg)); -+ -+ return ddr2TimeHiReg; -+} -+#endif -+ -+/******************************************************************************* -+* mvDramIfCalGet - Get CAS Latency -+* -+* DESCRIPTION: -+* This function get the CAS Latency. -+* -+* INPUT: -+* None -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* CAS latency times 10 (to avoid using floating point). -+* -+*******************************************************************************/ -+MV_U32 mvDramIfCalGet(void) -+{ -+ MV_U32 sdramCasLat, casLatMask; -+ -+ casLatMask = (MV_REG_READ(SDRAM_MODE_REG) & SDRAM_CL_MASK); -+ -+ switch (casLatMask) -+ { -+ case SDRAM_DDR2_CL_3: -+ sdramCasLat = 30; -+ break; -+ case SDRAM_DDR2_CL_4: -+ sdramCasLat = 40; -+ break; -+ case SDRAM_DDR2_CL_5: -+ sdramCasLat = 50; -+ break; -+ case SDRAM_DDR2_CL_6: -+ sdramCasLat = 60; -+ break; -+ default: -+ mvOsOutput("mvDramIfCalGet: Err, unknown DDR2 CAL\n"); -+ return -1; -+ } -+ -+ return sdramCasLat; -+} -+ -+ -+/******************************************************************************* -+* mvDramIfSelfRefreshSet - Put the dram in self refresh mode - -+* -+* DESCRIPTION: -+* add support in power management. -+* -+* -+* INPUT: -+* None -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* None -+* -+*******************************************************************************/ -+ -+MV_VOID mvDramIfSelfRefreshSet() -+{ -+ MV_U32 operReg; -+ -+ operReg = MV_REG_READ(SDRAM_OPERATION_REG); -+ MV_REG_WRITE(SDRAM_OPERATION_REG ,operReg |SDRAM_CMD_SLF_RFRSH); -+ /* Read until register is reset to 0 */ -+ while(MV_REG_READ(SDRAM_OPERATION_REG)); -+} -+/******************************************************************************* -+* mvDramIfDimGetSPDversion - return DIMM SPD version. -+* -+* DESCRIPTION: -+* This function prints the DRAM controller information. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+static void mvDramIfDimGetSPDversion(MV_U32 *pMajor, MV_U32 *pMinor, MV_U32 bankNum) -+{ -+ MV_DIMM_INFO dimmInfo; -+ if (bankNum >= MV_DRAM_MAX_CS ) -+ { -+ DB(mvOsPrintf("Dram: mvDramIfDimGetSPDversion bad params \n")); -+ return ; -+ } -+ memset(&dimmInfo,0,sizeof(dimmInfo)); -+ if ( MV_OK != dimmSpdGet((MV_U32)(bankNum/2), &dimmInfo)) -+ { -+ DB(mvOsPrintf("Dram: ERR dimmSpdGet failed to get dimm info \n")); -+ return ; -+ } -+ *pMajor = dimmInfo.spdRawData[DIMM_SPD_VERSION]/10; -+ *pMinor = dimmInfo.spdRawData[DIMM_SPD_VERSION]%10; -+} -+/******************************************************************************* -+* mvDramIfShow - Show DRAM controller information. -+* -+* DESCRIPTION: -+* This function prints the DRAM controller information. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+void mvDramIfShow(void) -+{ -+ int i, sdramCasLat, sdramCsSize; -+ MV_U32 Major=0, Minor=0; -+ -+ mvOsOutput("DRAM Controller info:\n"); -+ -+ mvOsOutput("Total DRAM "); -+ mvSizePrint(mvDramIfSizeGet()); -+ mvOsOutput("\n"); -+ -+ for(i = 0; i < MV_DRAM_MAX_CS; i++) -+ { -+ sdramCsSize = mvDramIfBankSizeGet(i); -+ if (sdramCsSize) -+ { -+ if (0 == (i & 1)) -+ { -+ mvDramIfDimGetSPDversion(&Major, &Minor,i); -+ mvOsOutput("DIMM %d version %d.%d\n", i/2, Major, Minor); -+ } -+ mvOsOutput("\tDRAM CS[%d] ", i); -+ mvSizePrint(sdramCsSize); -+ mvOsOutput("\n"); -+ } -+ } -+ sdramCasLat = mvDramIfCalGet(); -+ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_ECC_EN) -+ { -+ mvOsOutput("ECC enabled, "); -+ } -+ else -+ { -+ mvOsOutput("ECC Disabled, "); -+ } -+ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_REGISTERED) -+ { -+ mvOsOutput("Registered DIMM\n"); -+ } -+ else -+ { -+ mvOsOutput("Non registered DIMM\n"); -+ } -+ -+ mvOsOutput("Configured CAS Latency %d.%d\n", sdramCasLat/10, sdramCasLat%10); -+} -+/******************************************************************************* -+* mvDramIfGetFirstCS - find the DRAM bank on the lower address -+* -+* -+* DESCRIPTION: -+* This function return the fisrt CS on address 0 -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* SDRAM_CS0 or SDRAM_CS2 -+* -+*******************************************************************************/ -+MV_U32 mvDramIfGetFirstCS(void) -+{ -+ MV_DRAM_BANK_INFO bankInfo[MV_DRAM_MAX_CS]; -+ -+ if (DRAM_CS_Order[0] == N_A) -+ { -+ mvDramBankInfoGet(SDRAM_CS0, &bankInfo[SDRAM_CS0]); -+#ifdef MV_INCLUDE_SDRAM_CS2 -+ mvDramBankInfoGet(SDRAM_CS2, &bankInfo[SDRAM_CS2]); -+#endif -+ -+#ifdef MV_INCLUDE_SDRAM_CS2 -+ if (bankInfo[SDRAM_CS0].size < bankInfo[SDRAM_CS2].size) -+ { -+ DRAM_CS_Order[0] = SDRAM_CS2; -+ DRAM_CS_Order[1] = SDRAM_CS3; -+ DRAM_CS_Order[2] = SDRAM_CS0; -+ DRAM_CS_Order[3] = SDRAM_CS1; -+ -+ return SDRAM_CS2; -+ } -+#endif -+ DRAM_CS_Order[0] = SDRAM_CS0; -+ DRAM_CS_Order[1] = SDRAM_CS1; -+#ifdef MV_INCLUDE_SDRAM_CS2 -+ DRAM_CS_Order[2] = SDRAM_CS2; -+ DRAM_CS_Order[3] = SDRAM_CS3; -+#endif -+ return SDRAM_CS0; -+ } -+ return DRAM_CS_Order[0]; -+} -+/******************************************************************************* -+* mvDramIfGetCSorder - -+* -+* -+* DESCRIPTION: -+* This function return the fisrt CS on address 0 -+* -+* INPUT: -+* CS number. -+* -+* OUTPUT: -+* CS order. -+* -+* RETURN: -+* SDRAM_CS0 or SDRAM_CS2 -+* -+* NOTE: mvDramIfGetFirstCS must be caled before this subroutine -+*******************************************************************************/ -+MV_U32 mvDramIfGetCSorder(MV_U32 csOrder ) -+{ -+ return DRAM_CS_Order[csOrder]; -+} -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h 2010-11-09 20:28:10.852495382 +0100 -@@ -0,0 +1,157 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvDramIfConfigh -+#define __INCmvDramIfConfigh -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* includes */ -+ -+/* defines */ -+ -+/* registers defaults values */ -+ -+#define SDRAM_CONFIG_DV (SDRAM_SRMODE_DRAM | BIT25 | BIT30) -+ -+#define SDRAM_DUNIT_CTRL_LOW_DDR2_DV \ -+ (SDRAM_SRCLK_KEPT | \ -+ SDRAM_CLK1DRV_NORMAL | \ -+ (BIT28 | BIT29)) -+ -+#define SDRAM_ADDR_CTRL_DV 2 -+ -+#define SDRAM_TIMING_CTRL_LOW_REG_DV \ -+ ((0x2 << SDRAM_TRCD_OFFS) | \ -+ (0x2 << SDRAM_TRP_OFFS) | \ -+ (0x1 << SDRAM_TWR_OFFS) | \ -+ (0x0 << SDRAM_TWTR_OFFS) | \ -+ (0x5 << SDRAM_TRAS_OFFS) | \ -+ (0x1 << SDRAM_TRRD_OFFS)) -+ -+/* Note: value of 0 in register means one cycle, 1 means two and so on */ -+#define SDRAM_TIMING_CTRL_HIGH_REG_DV \ -+ ((0x0 << SDRAM_TR2R_OFFS) | \ -+ (0x0 << SDRAM_TR2W_W2R_OFFS) | \ -+ (0x1 << SDRAM_TW2W_OFFS)) -+ -+#define SDRAM_OPEN_PAGES_CTRL_REG_DV SDRAM_OPEN_PAGE_EN -+ -+/* Presence Ctrl Low Ctrl High Dunit Ctrl Ext Mode */ -+/* CS0 0x84210000 0x00000000 0x0000780F 0x00000440 */ -+/* CS0+CS1 0x84210000 0x00000000 0x0000780F 0x00000440 */ -+/* CS0+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -+/* CS0+CS1+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -+/* CS0+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -+/* CS0+CS1+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -+ -+#define DDR2_ODT_CTRL_LOW_CS0_CS1_DV 0x84210000 -+#define DDR2_ODT_CTRL_HIGH_CS0_CS1_DV 0x00000000 -+#define DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV 0x0000E80F -+#ifdef MV78XX0 -+#define DDR_SDRAM_EXT_MODE_CS0_CS1_DV 0x00000040 -+#else -+#define DDR_SDRAM_EXT_MODE_CS0_CS1_DV 0x00000440 -+#endif -+ -+#define DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV 0x030C030C -+#define DDR2_ODT_CTRL_HIGH_CS0_CS1_CS2_CS3_DV 0x00000000 -+#define DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV 0x0000F40F -+#ifdef MV78XX0 -+#define DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV 0x00000004 -+#define DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV 0x00000044 -+#else -+#define DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV 0x00000404 -+#define DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV 0x00000444 -+#endif -+ -+/* DDR SDRAM Adderss/Control and Data Pads Calibration default values */ -+#define DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \ -+ (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) -+ -+#define DDR2_DATA_PAD_STRENGTH_TYPICAL_DV \ -+ (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) -+ -+/* DDR SDRAM Mode Register default value */ -+#define DDR2_MODE_REG_DV (SDRAM_BURST_LEN_4 | SDRAM_WR_3_CYC) -+/* DDR SDRAM Timing parameter default values */ -+#define SDRAM_TIMING_CTRL_LOW_REG_DEFAULT 0x33136552 -+#define SDRAM_TRFC_DEFAULT_VALUE 0x34 -+#define SDRAM_TRFC_DEFAULT SDRAM_TRFC_DEFAULT_VALUE -+#define SDRAM_TW2W_DEFALT (0x1 << SDRAM_TW2W_OFFS) -+ -+#define SDRAM_TIMING_CTRL_HIGH_REG_DEFAULT (SDRAM_TRFC_DEFAULT | SDRAM_TW2W_DEFALT) -+ -+#define SDRAM_FTDLL_REG_DEFAULT_LEFT 0x88C800 -+#define SDRAM_FTDLL_REG_DEFAULT_RIGHT 0x88C800 -+#define SDRAM_FTDLL_REG_DEFAULT_UP 0x88C800 -+ -+#ifdef __cplusplus -+} -+#endif /* __cplusplus */ -+ -+#endif /* __INCmvDramIfh */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h 2010-11-09 20:28:10.882495421 +0100 -@@ -0,0 +1,172 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvDramIfh -+#define __INCmvDramIfh -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* includes */ -+#include "ddr2/mvDramIfRegs.h" -+#include "ddr2/mvDramIfConfig.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+ -+/* defines */ -+/* DRAM Timing parameters */ -+#define SDRAM_TWR 15 /* ns tWr */ -+#define SDRAM_TRFC_64_512M_AT_200MHZ 70 /* ns tRfc for dens 64-512 @ 200MHz */ -+#define SDRAM_TRFC_64_512M 75 /* ns tRfc for dens 64-512 */ -+#define SDRAM_TRFC_1G 120 /* ns tRfc for dens 1GB */ -+#define SDRAM_TR2R_CYC 1 /* cycle for tR2r */ -+ -+#define CAL_AUTO_DETECT 0 /* Do not force CAS latancy (mvDramIfDetect) */ -+#define ECC_DISABLE 1 /* Force ECC to Disable */ -+#define ECC_ENABLE 0 /* Force ECC to ENABLE */ -+/* typedefs */ -+ -+/* enumeration for memory types */ -+typedef enum _mvMemoryType -+{ -+ MEM_TYPE_SDRAM, -+ MEM_TYPE_DDR1, -+ MEM_TYPE_DDR2 -+}MV_MEMORY_TYPE; -+ -+/* enumeration for DDR2 supported CAS Latencies */ -+typedef enum _mvDimmDdr2Cas -+{ -+ DDR2_CL_3 = 0x08, -+ DDR2_CL_4 = 0x10, -+ DDR2_CL_5 = 0x20, -+ DDR2_CL_6 = 0x40, -+ DDR2_CL_FAULT -+} MV_DIMM_DDR2_CAS; -+ -+ -+typedef struct _mvDramBankInfo -+{ -+ MV_MEMORY_TYPE memoryType; /* DDR1, DDR2 or SDRAM */ -+ -+ /* DIMM dimensions */ -+ MV_U32 numOfRowAddr; -+ MV_U32 numOfColAddr; -+ MV_U32 dataWidth; -+ MV_U32 errorCheckType; /* ECC , PARITY..*/ -+ MV_U32 sdramWidth; /* 4,8,16 or 32 */ -+ MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ -+ MV_U32 burstLengthSupported; -+ MV_U32 numOfBanksOnEachDevice; -+ MV_U32 suportedCasLatencies; -+ MV_U32 refreshInterval; -+ -+ /* DIMM timing parameters */ -+ MV_U32 minCycleTimeAtMaxCasLatPs; -+ MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; -+ MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; -+ MV_U32 minRowPrechargeTime; -+ MV_U32 minRowActiveToRowActive; -+ MV_U32 minRasToCasDelay; -+ MV_U32 minRasPulseWidth; -+ MV_U32 minWriteRecoveryTime; /* DDR2 only */ -+ MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ -+ MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ -+ MV_U32 minRefreshToActiveCmd; /* DDR2 only */ -+ -+ /* Parameters calculated from the extracted DIMM information */ -+ MV_U32 size; -+ MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit */ -+ MV_U32 numberOfDevices; -+ -+ /* DIMM attributes (MV_TRUE for yes) */ -+ MV_BOOL registeredAddrAndControlInputs; -+ MV_BOOL registeredDQMBinputs; -+ -+}MV_DRAM_BANK_INFO; -+ -+#include "ddr2/spd/mvSpd.h" -+ -+/* mvDramIf.h API list */ -+MV_VOID mvDramIfBasicAsmInit(MV_VOID); -+MV_STATUS mvDramIfDetect(MV_U32 forcedCl, MV_BOOL eccDisable); -+MV_VOID _mvDramIfConfig(int entryNum); -+ -+MV_U32 mvDramIfBankSizeGet(MV_U32 bankNum); -+MV_U32 mvDramIfBankBaseGet(MV_U32 bankNum); -+MV_U32 mvDramIfSizeGet(MV_VOID); -+MV_U32 mvDramIfCalGet(void); -+MV_STATUS mvDramIfSingleBitErrThresholdSet(MV_U32 threshold); -+MV_VOID mvDramIfSelfRefreshSet(void); -+void mvDramIfShow(void); -+MV_U32 mvDramIfGetFirstCS(void); -+MV_U32 mvDramIfGetCSorder(MV_U32 csOrder ); -+MV_U32 mvDramCsSizeGet(MV_U32 csNum); -+ -+#ifdef __cplusplus -+} -+#endif /* __cplusplus */ -+ -+#endif /* __INCmvDramIfh */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h 2010-11-09 20:28:10.921244571 +0100 -@@ -0,0 +1,423 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvDramIfRegsh -+#define __INCmvDramIfRegsh -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* DDR SDRAM Controller Address Decode Registers */ -+ /* SDRAM CSn Base Address Register (SCBAR) */ -+#define SDRAM_BASE_ADDR_REG(cpu,csNum) (0x1500 + ((csNum) * 8) + ((cpu) * 0x70)) -+#define SCBAR_BASE_OFFS 16 -+#define SCBAR_BASE_MASK (0xffff << SCBAR_BASE_OFFS) -+#define SCBAR_BASE_ALIGNMENT 0x10000 -+ -+/* SDRAM CSn Size Register (SCSR) */ -+#define SDRAM_SIZE_REG(cpu,csNum) (0x1504 + ((csNum) * 8) + ((cpu) * 0x70)) -+#define SCSR_SIZE_OFFS 24 -+#define SCSR_SIZE_MASK (0xff << SCSR_SIZE_OFFS) -+#define SCSR_SIZE_ALIGNMENT 0x1000000 -+#define SCSR_WIN_EN BIT0 -+ -+/* configuration register */ -+#define SDRAM_CONFIG_REG (DRAM_BASE + 0x1400) -+#define SDRAM_REFRESH_OFFS 0 -+#define SDRAM_REFRESH_MAX 0x3FFF -+#define SDRAM_REFRESH_MASK (SDRAM_REFRESH_MAX << SDRAM_REFRESH_OFFS) -+#define SDRAM_DWIDTH_OFFS 15 -+#define SDRAM_DWIDTH_MASK (1 << SDRAM_DWIDTH_OFFS) -+#define SDRAM_DWIDTH_32BIT (0 << SDRAM_DWIDTH_OFFS) -+#define SDRAM_DWIDTH_64BIT (1 << SDRAM_DWIDTH_OFFS) -+#define SDRAM_REGISTERED (1 << 17) -+#define SDRAM_ECC_OFFS 18 -+#define SDRAM_ECC_MASK (1 << SDRAM_ECC_OFFS) -+#define SDRAM_ECC_DIS (0 << SDRAM_ECC_OFFS) -+#define SDRAM_ECC_EN (1 << SDRAM_ECC_OFFS) -+#define SDRAM_IERR_OFFS 19 -+#define SDRAM_IERR_MASK (1 << SDRAM_IERR_OFFS) -+#define SDRAM_IERR_REPORTE (0 << SDRAM_IERR_OFFS) -+#define SDRAM_IERR_IGNORE (1 << SDRAM_IERR_OFFS) -+#define SDRAM_SRMODE_OFFS 24 -+#define SDRAM_SRMODE_MASK (1 << SDRAM_SRMODE_OFFS) -+#define SDRAM_SRMODE_POWER (0 << SDRAM_SRMODE_OFFS) -+#define SDRAM_SRMODE_DRAM (1 << SDRAM_SRMODE_OFFS) -+ -+/* dunit control low register */ -+#define SDRAM_DUNIT_CTRL_REG (DRAM_BASE + 0x1404) -+#define SDRAM_2T_OFFS 4 -+#define SDRAM_2T_MASK (1 << SDRAM_2T_OFFS) -+#define SDRAM_2T_MODE (1 << SDRAM_2T_OFFS) -+ -+#define SDRAM_SRCLK_OFFS 5 -+#define SDRAM_SRCLK_MASK (1 << SDRAM_SRCLK_OFFS) -+#define SDRAM_SRCLK_KEPT (0 << SDRAM_SRCLK_OFFS) -+#define SDRAM_SRCLK_GATED (1 << SDRAM_SRCLK_OFFS) -+#define SDRAM_CTRL_POS_OFFS 6 -+#define SDRAM_CTRL_POS_MASK (1 << SDRAM_CTRL_POS_OFFS) -+#define SDRAM_CTRL_POS_FALL (0 << SDRAM_CTRL_POS_OFFS) -+#define SDRAM_CTRL_POS_RISE (1 << SDRAM_CTRL_POS_OFFS) -+#define SDRAM_CLK1DRV_OFFS 12 -+#define SDRAM_CLK1DRV_MASK (1 << SDRAM_CLK1DRV_OFFS) -+#define SDRAM_CLK1DRV_HIGH_Z (0 << SDRAM_CLK1DRV_OFFS) -+#define SDRAM_CLK1DRV_NORMAL (1 << SDRAM_CLK1DRV_OFFS) -+#define SDRAM_CLK2DRV_OFFS 13 -+#define SDRAM_CLK2DRV_MASK (1 << SDRAM_CLK2DRV_OFFS) -+#define SDRAM_CLK2DRV_HIGH_Z (0 << SDRAM_CLK2DRV_OFFS) -+#define SDRAM_CLK2DRV_NORMAL (1 << SDRAM_CLK2DRV_OFFS) -+#define SDRAM_SB_OUT_DEL_OFFS 20 -+#define SDRAM_SB_OUT_DEL_MAX 0xf -+#define SDRAM_SB_OUT_MASK (SDRAM_SB_OUT_DEL_MAX<= MV_DRAM_MAX_CS )) -+ { -+ DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); -+ return MV_BAD_PARAM; -+ } -+ memset(pBankInfo, 0, sizeof(*pBankInfo)); -+ -+ if ( MV_OK != dimmSpdGet((MV_U32)(bankNum/2), &dimmInfo)) -+ { -+ DB(mvOsPrintf("Dram: ERR dimmSpdGet failed to get dimm info \n")); -+ return MV_FAIL; -+ } -+ if ((dimmInfo.numOfModuleBanks == 1) && ((bankNum % 2) == 1)) -+ { -+ DB(mvOsPrintf("Dram: ERR dimmSpdGet. Can't find DIMM bank 2 \n")); -+ return MV_FAIL; -+ } -+ /* convert Dimm info to Bank info */ -+ cpyDimm2BankInfo(&dimmInfo, pBankInfo); -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* cpyDimm2BankInfo - Convert a Dimm info struct into a bank info struct. -+* -+* DESCRIPTION: -+* Convert a Dimm info struct into a bank info struct. -+* -+* INPUT: -+* pDimmInfo - DIMM information structure. -+* -+* OUTPUT: -+* pBankInfo - DRAM bank information struct. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+static MV_VOID cpyDimm2BankInfo(MV_DIMM_INFO *pDimmInfo, -+ MV_DRAM_BANK_INFO *pBankInfo) -+{ -+ pBankInfo->memoryType = pDimmInfo->memoryType; -+ -+ /* DIMM dimensions */ -+ pBankInfo->numOfRowAddr = pDimmInfo->numOfRowAddr; -+ pBankInfo->numOfColAddr = pDimmInfo->numOfColAddr; -+ pBankInfo->dataWidth = pDimmInfo->dataWidth; -+ pBankInfo->errorCheckType = pDimmInfo->errorCheckType; -+ pBankInfo->sdramWidth = pDimmInfo->sdramWidth; -+ pBankInfo->errorCheckDataWidth = pDimmInfo->errorCheckDataWidth; -+ pBankInfo->numOfBanksOnEachDevice = pDimmInfo->numOfBanksOnEachDevice; -+ pBankInfo->suportedCasLatencies = pDimmInfo->suportedCasLatencies; -+ pBankInfo->refreshInterval = pDimmInfo->refreshInterval; -+ -+ /* DIMM timing parameters */ -+ pBankInfo->minCycleTimeAtMaxCasLatPs = pDimmInfo->minCycleTimeAtMaxCasLatPs; -+ pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps = -+ pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps; -+ pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps = -+ pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps; -+ -+ pBankInfo->minRowPrechargeTime = pDimmInfo->minRowPrechargeTime; -+ pBankInfo->minRowActiveToRowActive = pDimmInfo->minRowActiveToRowActive; -+ pBankInfo->minRasToCasDelay = pDimmInfo->minRasToCasDelay; -+ pBankInfo->minRasPulseWidth = pDimmInfo->minRasPulseWidth; -+ pBankInfo->minWriteRecoveryTime = pDimmInfo->minWriteRecoveryTime; -+ pBankInfo->minWriteToReadCmdDelay = pDimmInfo->minWriteToReadCmdDelay; -+ pBankInfo->minReadToPrechCmdDelay = pDimmInfo->minReadToPrechCmdDelay; -+ pBankInfo->minRefreshToActiveCmd = pDimmInfo->minRefreshToActiveCmd; -+ -+ /* Parameters calculated from the extracted DIMM information */ -+ pBankInfo->size = pDimmInfo->size/pDimmInfo->numOfModuleBanks; -+ pBankInfo->deviceDensity = pDimmInfo->deviceDensity; -+ pBankInfo->numberOfDevices = pDimmInfo->numberOfDevices / -+ pDimmInfo->numOfModuleBanks; -+ -+ /* DIMM attributes (MV_TRUE for yes) */ -+ -+ if ((pDimmInfo->memoryType == MEM_TYPE_SDRAM) || -+ (pDimmInfo->memoryType == MEM_TYPE_DDR1) ) -+ { -+ if (pDimmInfo->dimmAttributes & BIT1) -+ pBankInfo->registeredAddrAndControlInputs = MV_TRUE; -+ else -+ pBankInfo->registeredAddrAndControlInputs = MV_FALSE; -+ } -+ else /* pDimmInfo->memoryType == MEM_TYPE_DDR2 */ -+ { -+ if (pDimmInfo->dimmTypeInfo & (BIT0 | BIT4)) -+ pBankInfo->registeredAddrAndControlInputs = MV_TRUE; -+ else -+ pBankInfo->registeredAddrAndControlInputs = MV_FALSE; -+ } -+ -+ return; -+} -+/******************************************************************************* -+* dimmSpdCpy - Cpy SPD parameters from dimm 0 to dimm 1. -+* -+* DESCRIPTION: -+* Read the DIMM SPD parameters from dimm 0 into dimm 1 SPD. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+MV_STATUS dimmSpdCpy(MV_VOID) -+{ -+ MV_U32 i; -+ MV_U32 spdChecksum; -+ -+ MV_TWSI_SLAVE twsiSlave; -+ MV_U8 data[SPD_SIZE]; -+ -+ /* zero dimmInfo structure */ -+ memset(data, 0, SPD_SIZE); -+ -+ /* read the dimm eeprom */ -+ DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); -+ twsiSlave.slaveAddr.address = MV_BOARD_DIMM0_I2C_ADDR; -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ twsiSlave.offset = 0; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, &twsiSlave, data, SPD_SIZE) ) -+ { -+ DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 0\n")); -+ return MV_FAIL; -+ } -+ DB(puts("DRAM: Reading dimm info succeded.\n")); -+ -+ /* calculate SPD checksum */ -+ spdChecksum = 0; -+ -+ for(i = 0 ; i <= 62 ; i++) -+ { -+ spdChecksum += data[i]; -+ } -+ -+ if ((spdChecksum & 0xff) != data[63]) -+ { -+ DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", -+ (MV_U32)(spdChecksum & 0xff), data[63])); -+ } -+ else -+ { -+ DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); -+ } -+ -+ /* copy the SPD content 1:1 into the DIMM 1 SPD */ -+ twsiSlave.slaveAddr.address = MV_BOARD_DIMM1_I2C_ADDR; -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ twsiSlave.offset = 0; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ for(i = 0 ; i < SPD_SIZE ; i++) -+ { -+ twsiSlave.offset = i; -+ if( MV_OK != mvTwsiWrite (MV_BOARD_DIMM_I2C_CHANNEL, &twsiSlave, &data[i], 1) ) -+ { -+ mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 1 byte %d \n",i); -+ return MV_FAIL; -+ } -+ mvOsDelay(5); -+ } -+ -+ DB(puts("DRAM: Reading dimm info succeded.\n")); -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* dimmSpdGet - Get the SPD parameters. -+* -+* DESCRIPTION: -+* Read the DIMM SPD parameters into given struct parameter. -+* -+* INPUT: -+* dimmNum - DIMM number. See MV_BOARD_DIMM_NUM enumerator. -+* -+* OUTPUT: -+* pDimmInfo - DIMM information structure. -+* -+* RETURN: -+* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo) -+{ -+ MV_U32 i; -+ MV_U32 density = 1; -+ MV_U32 spdChecksum; -+ -+ MV_TWSI_SLAVE twsiSlave; -+ MV_U8 data[SPD_SIZE]; -+ -+ if((NULL == pDimmInfo)|| (dimmNum >= MAX_DIMM_NUM)) -+ { -+ DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); -+ return MV_BAD_PARAM; -+ } -+ -+ /* zero dimmInfo structure */ -+ memset(data, 0, SPD_SIZE); -+ -+ /* read the dimm eeprom */ -+ DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); -+ twsiSlave.slaveAddr.address = (dimmNum == 0) ? -+ MV_BOARD_DIMM0_I2C_ADDR : MV_BOARD_DIMM1_I2C_ADDR; -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ twsiSlave.offset = 0; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, &twsiSlave, data, SPD_SIZE) ) -+ { -+ DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum %d \n", dimmNum)); -+ return MV_FAIL; -+ } -+ DB(puts("DRAM: Reading dimm info succeded.\n")); -+ -+ /* calculate SPD checksum */ -+ spdChecksum = 0; -+ -+ for(i = 0 ; i <= 62 ; i++) -+ { -+ spdChecksum += data[i]; -+ } -+ -+ if ((spdChecksum & 0xff) != data[63]) -+ { -+ DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", -+ (MV_U32)(spdChecksum & 0xff), data[63])); -+ } -+ else -+ { -+ DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); -+ } -+ -+ /* copy the SPD content 1:1 into the dimmInfo structure*/ -+ for(i = 0 ; i < SPD_SIZE ; i++) -+ { -+ pDimmInfo->spdRawData[i] = data[i]; -+ DB(mvOsPrintf("SPD-EEPROM Byte %3d = %3x (%3d)\n",i, data[i], data[i])); -+ } -+ -+ DB(mvOsPrintf("DRAM SPD Information:\n")); -+ -+ /* Memory type (DDR / SDRAM) */ -+ switch (data[DIMM_MEM_TYPE]) -+ { -+ case (DIMM_MEM_TYPE_SDRAM): -+ pDimmInfo->memoryType = MEM_TYPE_SDRAM; -+ DB(mvOsPrintf("DRAM Memeory type SDRAM\n")); -+ break; -+ case (DIMM_MEM_TYPE_DDR1): -+ pDimmInfo->memoryType = MEM_TYPE_DDR1; -+ DB(mvOsPrintf("DRAM Memeory type DDR1\n")); -+ break; -+ case (DIMM_MEM_TYPE_DDR2): -+ pDimmInfo->memoryType = MEM_TYPE_DDR2; -+ DB(mvOsPrintf("DRAM Memeory type DDR2\n")); -+ break; -+ default: -+ mvOsPrintf("ERROR: Undefined memory type!\n"); -+ return MV_ERROR; -+ } -+ -+ -+ /* Number Of Row Addresses */ -+ pDimmInfo->numOfRowAddr = data[DIMM_ROW_NUM]; -+ DB(mvOsPrintf("DRAM numOfRowAddr[3] %d\n",pDimmInfo->numOfRowAddr)); -+ -+ /* Number Of Column Addresses */ -+ pDimmInfo->numOfColAddr = data[DIMM_COL_NUM]; -+ DB(mvOsPrintf("DRAM numOfColAddr[4] %d\n",pDimmInfo->numOfColAddr)); -+ -+ /* Number Of Module Banks */ -+ pDimmInfo->numOfModuleBanks = data[DIMM_MODULE_BANK_NUM]; -+ DB(mvOsPrintf("DRAM numOfModuleBanks[5] 0x%x\n", -+ pDimmInfo->numOfModuleBanks)); -+ -+ /* Number of module banks encoded differently for DDR2 */ -+ if (pDimmInfo->memoryType == MEM_TYPE_DDR2) -+ pDimmInfo->numOfModuleBanks = (pDimmInfo->numOfModuleBanks & 0x7)+1; -+ -+ /* Data Width */ -+ pDimmInfo->dataWidth = data[DIMM_DATA_WIDTH]; -+ DB(mvOsPrintf("DRAM dataWidth[6] 0x%x\n", pDimmInfo->dataWidth)); -+ -+ /* Minimum Cycle Time At Max CasLatancy */ -+ pDimmInfo->minCycleTimeAtMaxCasLatPs = cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS]); -+ -+ /* Error Check Type */ -+ pDimmInfo->errorCheckType = data[DIMM_ERR_CHECK_TYPE]; -+ DB(mvOsPrintf("DRAM errorCheckType[11] 0x%x\n", -+ pDimmInfo->errorCheckType)); -+ -+ /* Refresh Interval */ -+ pDimmInfo->refreshInterval = data[DIMM_REFRESH_INTERVAL]; -+ DB(mvOsPrintf("DRAM refreshInterval[12] 0x%x\n", -+ pDimmInfo->refreshInterval)); -+ -+ /* Sdram Width */ -+ pDimmInfo->sdramWidth = data[DIMM_SDRAM_WIDTH]; -+ DB(mvOsPrintf("DRAM sdramWidth[13] 0x%x\n",pDimmInfo->sdramWidth)); -+ -+ /* Error Check Data Width */ -+ pDimmInfo->errorCheckDataWidth = data[DIMM_ERR_CHECK_DATA_WIDTH]; -+ DB(mvOsPrintf("DRAM errorCheckDataWidth[14] 0x%x\n", -+ pDimmInfo->errorCheckDataWidth)); -+ -+ /* Burst Length Supported */ -+ /* SDRAM/DDR1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * -+ *********************************************************/ -+ /* DDR2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * -+ *********************************************************/ -+ -+ pDimmInfo->burstLengthSupported = data[DIMM_BURST_LEN_SUP]; -+ DB(mvOsPrintf("DRAM burstLengthSupported[16] 0x%x\n", -+ pDimmInfo->burstLengthSupported)); -+ -+ /* Number Of Banks On Each Device */ -+ pDimmInfo->numOfBanksOnEachDevice = data[DIMM_DEV_BANK_NUM]; -+ DB(mvOsPrintf("DRAM numOfBanksOnEachDevice[17] 0x%x\n", -+ pDimmInfo->numOfBanksOnEachDevice)); -+ -+ /* Suported Cas Latencies */ -+ -+ /* SDRAM: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * -+ ********************************************************/ -+ -+ /* DDR 1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * -+ *********************************************************/ -+ -+ /* DDR 2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * -+ *********************************************************/ -+ -+ pDimmInfo->suportedCasLatencies = data[DIMM_SUP_CAL]; -+ DB(mvOsPrintf("DRAM suportedCasLatencies[18] 0x%x\n", -+ pDimmInfo->suportedCasLatencies)); -+ -+ /* For DDR2 only, get the DIMM type information */ -+ if (pDimmInfo->memoryType == MEM_TYPE_DDR2) -+ { -+ pDimmInfo->dimmTypeInfo = data[DIMM_DDR2_TYPE_INFORMATION]; -+ DB(mvOsPrintf("DRAM dimmTypeInfo[20] (DDR2) 0x%x\n", -+ pDimmInfo->dimmTypeInfo)); -+ } -+ -+ /* SDRAM Modules Attributes */ -+ pDimmInfo->dimmAttributes = data[DIMM_BUF_ADDR_CONT_IN]; -+ DB(mvOsPrintf("DRAM dimmAttributes[21] 0x%x\n", -+ pDimmInfo->dimmAttributes)); -+ -+ /* Minimum Cycle Time At Max CasLatancy Minus 1*/ -+ pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps = -+ cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS1]); -+ -+ /* Minimum Cycle Time At Max CasLatancy Minus 2*/ -+ pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps = -+ cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS2]); -+ -+ pDimmInfo->minRowPrechargeTime = data[DIMM_MIN_ROW_PRECHARGE_TIME]; -+ DB(mvOsPrintf("DRAM minRowPrechargeTime[27] 0x%x\n", -+ pDimmInfo->minRowPrechargeTime)); -+ pDimmInfo->minRowActiveToRowActive = data[DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE]; -+ DB(mvOsPrintf("DRAM minRowActiveToRowActive[28] 0x%x\n", -+ pDimmInfo->minRowActiveToRowActive)); -+ pDimmInfo->minRasToCasDelay = data[DIMM_MIN_RAS_TO_CAS_DELAY]; -+ DB(mvOsPrintf("DRAM minRasToCasDelay[29] 0x%x\n", -+ pDimmInfo->minRasToCasDelay)); -+ pDimmInfo->minRasPulseWidth = data[DIMM_MIN_RAS_PULSE_WIDTH]; -+ DB(mvOsPrintf("DRAM minRasPulseWidth[30] 0x%x\n", -+ pDimmInfo->minRasPulseWidth)); -+ -+ /* DIMM Bank Density */ -+ pDimmInfo->dimmBankDensity = data[DIMM_BANK_DENSITY]; -+ DB(mvOsPrintf("DRAM dimmBankDensity[31] 0x%x\n", -+ pDimmInfo->dimmBankDensity)); -+ -+ /* Only DDR2 includes Write Recovery Time field. Other SDRAM ignore */ -+ pDimmInfo->minWriteRecoveryTime = data[DIMM_MIN_WRITE_RECOVERY_TIME]; -+ DB(mvOsPrintf("DRAM minWriteRecoveryTime[36] 0x%x\n", -+ pDimmInfo->minWriteRecoveryTime)); -+ -+ /* Only DDR2 includes Internal Write To Read Command Delay field. */ -+ pDimmInfo->minWriteToReadCmdDelay = data[DIMM_MIN_WRITE_TO_READ_CMD_DELAY]; -+ DB(mvOsPrintf("DRAM minWriteToReadCmdDelay[37] 0x%x\n", -+ pDimmInfo->minWriteToReadCmdDelay)); -+ -+ /* Only DDR2 includes Internal Read To Precharge Command Delay field. */ -+ pDimmInfo->minReadToPrechCmdDelay = data[DIMM_MIN_READ_TO_PRECH_CMD_DELAY]; -+ DB(mvOsPrintf("DRAM minReadToPrechCmdDelay[38] 0x%x\n", -+ pDimmInfo->minReadToPrechCmdDelay)); -+ -+ /* Only DDR2 includes Minimum Refresh to Activate/Refresh Command field */ -+ pDimmInfo->minRefreshToActiveCmd = data[DIMM_MIN_REFRESH_TO_ACTIVATE_CMD]; -+ DB(mvOsPrintf("DRAM minRefreshToActiveCmd[42] 0x%x\n", -+ pDimmInfo->minRefreshToActiveCmd)); -+ -+ /* calculating the sdram density. Representing device density from */ -+ /* bit 20 to allow representation of 4GB and above. */ -+ /* For example, if density is 512Mbit 0x20000000, will be represent in */ -+ /* deviceDensity by 0x20000000 >> 16 --> 0x00000200. Another example */ -+ /* is density 8GB 0x200000000 >> 16 --> 0x00002000. */ -+ density = (1 << ((pDimmInfo->numOfRowAddr + pDimmInfo->numOfColAddr) - 20)); -+ pDimmInfo->deviceDensity = density * -+ pDimmInfo->numOfBanksOnEachDevice * -+ pDimmInfo->sdramWidth; -+ DB(mvOsPrintf("DRAM deviceDensity %d\n",pDimmInfo->deviceDensity)); -+ -+ /* Number of devices includeing Error correction */ -+ pDimmInfo->numberOfDevices = (pDimmInfo->dataWidth/pDimmInfo->sdramWidth) * -+ pDimmInfo->numOfModuleBanks; -+ DB(mvOsPrintf("DRAM numberOfDevices %d\n", -+ pDimmInfo->numberOfDevices)); -+ -+ pDimmInfo->size = 0; -+ -+ /* Note that pDimmInfo->size is in MB units */ -+ if (pDimmInfo->memoryType == MEM_TYPE_SDRAM) -+ { -+ if (pDimmInfo->dimmBankDensity & BIT0) -+ pDimmInfo->size += 1024; /* Equal to 1GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT1) -+ pDimmInfo->size += 8; /* Equal to 8MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT2) -+ pDimmInfo->size += 16; /* Equal to 16MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT3) -+ pDimmInfo->size += 32; /* Equal to 32MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT4) -+ pDimmInfo->size += 64; /* Equal to 64MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT5) -+ pDimmInfo->size += 128; /* Equal to 128MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT6) -+ pDimmInfo->size += 256; /* Equal to 256MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT7) -+ pDimmInfo->size += 512; /* Equal to 512MB */ -+ } -+ else if (pDimmInfo->memoryType == MEM_TYPE_DDR1) -+ { -+ if (pDimmInfo->dimmBankDensity & BIT0) -+ pDimmInfo->size += 1024; /* Equal to 1GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT1) -+ pDimmInfo->size += 2048; /* Equal to 2GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT2) -+ pDimmInfo->size += 16; /* Equal to 16MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT3) -+ pDimmInfo->size += 32; /* Equal to 32MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT4) -+ pDimmInfo->size += 64; /* Equal to 64MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT5) -+ pDimmInfo->size += 128; /* Equal to 128MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT6) -+ pDimmInfo->size += 256; /* Equal to 256MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT7) -+ pDimmInfo->size += 512; /* Equal to 512MB */ -+ } -+ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ -+ { -+ if (pDimmInfo->dimmBankDensity & BIT0) -+ pDimmInfo->size += 1024; /* Equal to 1GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT1) -+ pDimmInfo->size += 2048; /* Equal to 2GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT2) -+ pDimmInfo->size += 4096; /* Equal to 4GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT3) -+ pDimmInfo->size += 8192; /* Equal to 8GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT4) -+ pDimmInfo->size += 16384; /* Equal to 16GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT5) -+ pDimmInfo->size += 128; /* Equal to 128MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT6) -+ pDimmInfo->size += 256; /* Equal to 256MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT7) -+ pDimmInfo->size += 512; /* Equal to 512MB */ -+ } -+ -+ pDimmInfo->size *= pDimmInfo->numOfModuleBanks; -+ -+ DB(mvOsPrintf("Dram: dimm size %dMB \n",pDimmInfo->size)); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* dimmSpdPrint - Print the SPD parameters. -+* -+* DESCRIPTION: -+* Print the Dimm SPD parameters. -+* -+* INPUT: -+* pDimmInfo - DIMM information structure. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID dimmSpdPrint(MV_U32 dimmNum) -+{ -+ MV_DIMM_INFO dimmInfo; -+ MV_U32 i, temp = 0; -+ MV_U32 k, maskLeftOfPoint = 0, maskRightOfPoint = 0; -+ MV_U32 rightOfPoint = 0,leftOfPoint = 0, div, time_tmp, shift; -+ MV_U32 busClkPs; -+ MV_U8 trp_clocks=0, trcd_clocks, tras_clocks, trrd_clocks, -+ temp_buf[40], *spdRawData; -+ -+ busClkPs = 1000000000 / (mvBoardSysClkGet() / 100); /* in 10 ps units */ -+ -+ spdRawData = dimmInfo.spdRawData; -+ -+ if(MV_OK != dimmSpdGet(dimmNum, &dimmInfo)) -+ { -+ mvOsOutput("ERROR: Could not read SPD information!\n"); -+ return; -+ } -+ -+ /* find Manufactura of Dimm Module */ -+ mvOsOutput("\nManufacturer's JEDEC ID Code: "); -+ for(i = 0 ; i < DIMM_MODULE_MANU_SIZE ; i++) -+ { -+ mvOsOutput("%x",spdRawData[DIMM_MODULE_MANU_OFFS + i]); -+ } -+ mvOsOutput("\n"); -+ -+ /* Manufacturer's Specific Data */ -+ for(i = 0 ; i < DIMM_MODULE_ID_SIZE ; i++) -+ { -+ temp_buf[i] = spdRawData[DIMM_MODULE_ID_OFFS + i]; -+ } -+ mvOsOutput("Manufacturer's Specific Data: %s\n", temp_buf); -+ -+ /* Module Part Number */ -+ for(i = 0 ; i < DIMM_MODULE_VEN_SIZE ; i++) -+ { -+ temp_buf[i] = spdRawData[DIMM_MODULE_VEN_OFFS + i]; -+ } -+ mvOsOutput("Module Part Number: %s\n", temp_buf); -+ -+ /* Module Serial Number */ -+ for(i = 0; i < sizeof(MV_U32); i++) -+ { -+ temp |= spdRawData[95+i] << 8*i; -+ } -+ mvOsOutput("DIMM Serial No. %ld (%lx)\n", (long)temp, -+ (long)temp); -+ -+ /* find Manufac-Data of Dimm Module */ -+ mvOsOutput("Manufactoring Date: Year 20%d%d/ ww %d%d\n", -+ ((spdRawData[93] & 0xf0) >> 4), (spdRawData[93] & 0xf), -+ ((spdRawData[94] & 0xf0) >> 4), (spdRawData[94] & 0xf)); -+ /* find modul_revision of Dimm Module */ -+ mvOsOutput("Module Revision: %d.%d\n", -+ spdRawData[62]/10, spdRawData[62]%10); -+ -+ /* find manufac_place of Dimm Module */ -+ mvOsOutput("manufac_place: %d\n", spdRawData[72]); -+ -+ /* go over the first 35 I2C data bytes */ -+ for(i = 2 ; i <= 35 ; i++) -+ switch(i) -+ { -+ case 2: /* Memory type (DDR1/2 / SDRAM) */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ mvOsOutput("Dram Type is: SDRAM\n"); -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ mvOsOutput("Dram Type is: SDRAM DDR1\n"); -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) -+ mvOsOutput("Dram Type is: SDRAM DDR2\n"); -+ else -+ mvOsOutput("Dram Type unknown\n"); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 3: /* Number Of Row Addresses */ -+ mvOsOutput("Module Number of row addresses: %d\n", -+ dimmInfo.numOfRowAddr); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 4: /* Number Of Column Addresses */ -+ mvOsOutput("Module Number of col addresses: %d\n", -+ dimmInfo.numOfColAddr); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 5: /* Number Of Module Banks */ -+ mvOsOutput("Number of Banks on Mod.: %d\n", -+ dimmInfo.numOfModuleBanks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 6: /* Data Width */ -+ mvOsOutput("Module Data Width: %d bit\n", -+ dimmInfo.dataWidth); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 8: /* Voltage Interface */ -+ switch(spdRawData[i]) -+ { -+ case 0x0: -+ mvOsOutput("Module is TTL_5V_TOLERANT\n"); -+ break; -+ case 0x1: -+ mvOsOutput("Module is LVTTL\n"); -+ break; -+ case 0x2: -+ mvOsOutput("Module is HSTL_1_5V\n"); -+ break; -+ case 0x3: -+ mvOsOutput("Module is SSTL_3_3V\n"); -+ break; -+ case 0x4: -+ mvOsOutput("Module is SSTL_2_5V\n"); -+ break; -+ case 0x5: -+ if (dimmInfo.memoryType != MEM_TYPE_SDRAM) -+ { -+ mvOsOutput("Module is SSTL_1_8V\n"); -+ break; -+ } -+ default: -+ mvOsOutput("Module is VOLTAGE_UNKNOWN\n"); -+ break; -+ } -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 9: /* Minimum Cycle Time At Max CasLatancy */ -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ rightOfPoint = (spdRawData[i] & 0x0f) * 10; -+ -+ /* DDR2 addition of right of point */ -+ if ((spdRawData[i] & 0x0f) == 0xA) -+ { -+ rightOfPoint = 25; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xB) -+ { -+ rightOfPoint = 33; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xC) -+ { -+ rightOfPoint = 66; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xD) -+ { -+ rightOfPoint = 75; -+ } -+ mvOsOutput("Minimum Cycle Time At Max CL: %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 10: /* Clock To Data Out */ -+ div = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 10:100; -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / div; -+ rightOfPoint = time_tmp % div; -+ mvOsOutput("Clock To Data Out: %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 11: /* Error Check Type */ -+ mvOsOutput("Error Check Type (0=NONE): %d\n", -+ dimmInfo.errorCheckType); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 12: /* Refresh Interval */ -+ mvOsOutput("Refresh Rate: %x\n", -+ dimmInfo.refreshInterval); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 13: /* Sdram Width */ -+ mvOsOutput("Sdram Width: %d bits\n", -+ dimmInfo.sdramWidth); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 14: /* Error Check Data Width */ -+ mvOsOutput("Error Check Data Width: %d bits\n", -+ dimmInfo.errorCheckDataWidth); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 15: /* Minimum Clock Delay is unsupported */ -+ if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || -+ (dimmInfo.memoryType == MEM_TYPE_DDR1)) -+ { -+ mvOsOutput("Minimum Clk Delay back to back: %d\n", -+ spdRawData[i]); -+ } -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 16: /* Burst Length Supported */ -+ /* SDRAM/DDR1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * -+ *********************************************************/ -+ /* DDR2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * -+ *********************************************************/ -+ mvOsOutput("Burst Length Supported: "); -+ if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || -+ (dimmInfo.memoryType == MEM_TYPE_DDR1)) -+ { -+ if (dimmInfo.burstLengthSupported & BIT0) -+ mvOsOutput("1, "); -+ if (dimmInfo.burstLengthSupported & BIT1) -+ mvOsOutput("2, "); -+ } -+ if (dimmInfo.burstLengthSupported & BIT2) -+ mvOsOutput("4, "); -+ if (dimmInfo.burstLengthSupported & BIT3) -+ mvOsOutput("8, "); -+ -+ mvOsOutput(" Bit \n"); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 17: /* Number Of Banks On Each Device */ -+ mvOsOutput("Number Of Banks On Each Chip: %d\n", -+ dimmInfo.numOfBanksOnEachDevice); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 18: /* Suported Cas Latencies */ -+ -+ /* SDRAM: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * -+ ********************************************************/ -+ -+ /* DDR 1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * -+ *********************************************************/ -+ -+ /* DDR 2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * -+ *********************************************************/ -+ -+ mvOsOutput("Suported Cas Latencies: (CL) "); -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ for (k = 0; k <=7; k++) -+ { -+ if (dimmInfo.suportedCasLatencies & (1 << k)) -+ mvOsOutput("%d, ", k+1); -+ } -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ { -+ if (dimmInfo.suportedCasLatencies & BIT0) -+ mvOsOutput("1, "); -+ if (dimmInfo.suportedCasLatencies & BIT1) -+ mvOsOutput("1.5, "); -+ if (dimmInfo.suportedCasLatencies & BIT2) -+ mvOsOutput("2, "); -+ if (dimmInfo.suportedCasLatencies & BIT3) -+ mvOsOutput("2.5, "); -+ if (dimmInfo.suportedCasLatencies & BIT4) -+ mvOsOutput("3, "); -+ if (dimmInfo.suportedCasLatencies & BIT5) -+ mvOsOutput("3.5, "); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) -+ { -+ if (dimmInfo.suportedCasLatencies & BIT2) -+ mvOsOutput("2, "); -+ if (dimmInfo.suportedCasLatencies & BIT3) -+ mvOsOutput("3, "); -+ if (dimmInfo.suportedCasLatencies & BIT4) -+ mvOsOutput("4, "); -+ if (dimmInfo.suportedCasLatencies & BIT5) -+ mvOsOutput("5, "); -+ } -+ else -+ mvOsOutput("?.?, "); -+ mvOsOutput("\n"); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 20: /* DDR2 DIMM type info */ -+ if (dimmInfo.memoryType == MEM_TYPE_DDR2) -+ { -+ if (dimmInfo.dimmTypeInfo & (BIT0 | BIT4)) -+ mvOsOutput("Registered DIMM (RDIMM)\n"); -+ else if (dimmInfo.dimmTypeInfo & (BIT1 | BIT5)) -+ mvOsOutput("Unbuffered DIMM (UDIMM)\n"); -+ else -+ mvOsOutput("Unknown DIMM type.\n"); -+ } -+ -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 21: /* SDRAM Modules Attributes */ -+ mvOsOutput("\nModule Attributes (SPD Byte 21): \n"); -+ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ if (dimmInfo.dimmAttributes & BIT0) -+ mvOsOutput(" Buffered Addr/Control Input: Yes\n"); -+ else -+ mvOsOutput(" Buffered Addr/Control Input: No\n"); -+ -+ if (dimmInfo.dimmAttributes & BIT1) -+ mvOsOutput(" Registered Addr/Control Input: Yes\n"); -+ else -+ mvOsOutput(" Registered Addr/Control Input: No\n"); -+ -+ if (dimmInfo.dimmAttributes & BIT2) -+ mvOsOutput(" On-Card PLL (clock): Yes \n"); -+ else -+ mvOsOutput(" On-Card PLL (clock): No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT3) -+ mvOsOutput(" Bufferd DQMB Input: Yes \n"); -+ else -+ mvOsOutput(" Bufferd DQMB Inputs: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT4) -+ mvOsOutput(" Registered DQMB Inputs: Yes \n"); -+ else -+ mvOsOutput(" Registered DQMB Inputs: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT5) -+ mvOsOutput(" Differential Clock Input: Yes \n"); -+ else -+ mvOsOutput(" Differential Clock Input: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT6) -+ mvOsOutput(" redundant Row Addressing: Yes \n"); -+ else -+ mvOsOutput(" redundant Row Addressing: No \n"); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ { -+ if (dimmInfo.dimmAttributes & BIT0) -+ mvOsOutput(" Buffered Addr/Control Input: Yes\n"); -+ else -+ mvOsOutput(" Buffered Addr/Control Input: No\n"); -+ -+ if (dimmInfo.dimmAttributes & BIT1) -+ mvOsOutput(" Registered Addr/Control Input: Yes\n"); -+ else -+ mvOsOutput(" Registered Addr/Control Input: No\n"); -+ -+ if (dimmInfo.dimmAttributes & BIT2) -+ mvOsOutput(" On-Card PLL (clock): Yes \n"); -+ else -+ mvOsOutput(" On-Card PLL (clock): No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT3) -+ mvOsOutput(" FET Switch On-Card Enabled: Yes \n"); -+ else -+ mvOsOutput(" FET Switch On-Card Enabled: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT4) -+ mvOsOutput(" FET Switch External Enabled: Yes \n"); -+ else -+ mvOsOutput(" FET Switch External Enabled: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT5) -+ mvOsOutput(" Differential Clock Input: Yes \n"); -+ else -+ mvOsOutput(" Differential Clock Input: No \n"); -+ } -+ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ -+ { -+ mvOsOutput(" Number of Active Registers on the DIMM: %d\n", -+ (dimmInfo.dimmAttributes & 0x3) + 1); -+ -+ mvOsOutput(" Number of PLLs on the DIMM: %d\n", -+ ((dimmInfo.dimmAttributes) >> 2) & 0x3); -+ -+ if (dimmInfo.dimmAttributes & BIT4) -+ mvOsOutput(" FET Switch External Enabled: Yes \n"); -+ else -+ mvOsOutput(" FET Switch External Enabled: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT6) -+ mvOsOutput(" Analysis probe installed: Yes \n"); -+ else -+ mvOsOutput(" Analysis probe installed: No \n"); -+ } -+ -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 22: /* Suported AutoPreCharge */ -+ mvOsOutput("\nModul Attributes (SPD Byte 22): \n"); -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ if ( spdRawData[i] & BIT0 ) -+ mvOsOutput(" Early Ras Precharge: Yes \n"); -+ else -+ mvOsOutput(" Early Ras Precharge: No \n"); -+ -+ if ( spdRawData[i] & BIT1 ) -+ mvOsOutput(" AutoPreCharge: Yes \n"); -+ else -+ mvOsOutput(" AutoPreCharge: No \n"); -+ -+ if ( spdRawData[i] & BIT2 ) -+ mvOsOutput(" Precharge All: Yes \n"); -+ else -+ mvOsOutput(" Precharge All: No \n"); -+ -+ if ( spdRawData[i] & BIT3 ) -+ mvOsOutput(" Write 1/ReadBurst: Yes \n"); -+ else -+ mvOsOutput(" Write 1/ReadBurst: No \n"); -+ -+ if ( spdRawData[i] & BIT4 ) -+ mvOsOutput(" lower VCC tolerance: 5%%\n"); -+ else -+ mvOsOutput(" lower VCC tolerance: 10%%\n"); -+ -+ if ( spdRawData[i] & BIT5 ) -+ mvOsOutput(" upper VCC tolerance: 5%%\n"); -+ else -+ mvOsOutput(" upper VCC tolerance: 10%%\n"); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ { -+ if ( spdRawData[i] & BIT0 ) -+ mvOsOutput(" Supports Weak Driver: Yes \n"); -+ else -+ mvOsOutput(" Supports Weak Driver: No \n"); -+ -+ if ( !(spdRawData[i] & BIT4) ) -+ mvOsOutput(" lower VCC tolerance: 0.2V\n"); -+ -+ if ( !(spdRawData[i] & BIT5) ) -+ mvOsOutput(" upper VCC tolerance: 0.2V\n"); -+ -+ if ( spdRawData[i] & BIT6 ) -+ mvOsOutput(" Concurrent Auto Preharge: Yes \n"); -+ else -+ mvOsOutput(" Concurrent Auto Preharge: No \n"); -+ -+ if ( spdRawData[i] & BIT7 ) -+ mvOsOutput(" Supports Fast AP: Yes \n"); -+ else -+ mvOsOutput(" Supports Fast AP: No \n"); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) -+ { -+ if ( spdRawData[i] & BIT0 ) -+ mvOsOutput(" Supports Weak Driver: Yes \n"); -+ else -+ mvOsOutput(" Supports Weak Driver: No \n"); -+ } -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 23: -+ /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */ -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ rightOfPoint = (spdRawData[i] & 0x0f) * 10; -+ -+ /* DDR2 addition of right of point */ -+ if ((spdRawData[i] & 0x0f) == 0xA) -+ { -+ rightOfPoint = 25; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xB) -+ { -+ rightOfPoint = 33; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xC) -+ { -+ rightOfPoint = 66; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xD) -+ { -+ rightOfPoint = 75; -+ } -+ -+ mvOsOutput("Minimum Cycle Time At 2nd highest CasLatancy" -+ "(0 = Not supported): %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint ); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 24: /* Clock To Data Out 2nd highest Cas Latency Value*/ -+ div = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? 10:100; -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / div; -+ rightOfPoint = time_tmp % div; -+ mvOsOutput("Clock To Data Out (2nd CL value): %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 25: -+ /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ leftOfPoint = (spdRawData[i] & 0xfc) >> 2; -+ rightOfPoint = (spdRawData[i] & 0x3) * 25; -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ rightOfPoint = (spdRawData[i] & 0x0f) * 10; -+ -+ /* DDR2 addition of right of point */ -+ if ((spdRawData[i] & 0x0f) == 0xA) -+ { -+ rightOfPoint = 25; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xB) -+ { -+ rightOfPoint = 33; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xC) -+ { -+ rightOfPoint = 66; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xD) -+ { -+ rightOfPoint = 75; -+ } -+ } -+ mvOsOutput("Minimum Cycle Time At 3rd highest CasLatancy" -+ "(0 = Not supported): %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint ); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 26: /* Clock To Data Out 3rd highest Cas Latency Value*/ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ leftOfPoint = (spdRawData[i] & 0xfc) >> 2; -+ rightOfPoint = (spdRawData[i] & 0x3) * 25; -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = 0; -+ rightOfPoint = time_tmp; -+ } -+ mvOsOutput("Clock To Data Out (3rd CL value): %d.%2d[ns]\n", -+ leftOfPoint, rightOfPoint ); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 27: /* Minimum Row Precharge Time */ -+ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; -+ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0xff : 0xfc; -+ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0x00 : 0x03; -+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); -+ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; -+ temp = ((leftOfPoint*100) + rightOfPoint);/* in 10ps Intervals*/ -+ trp_clocks = (temp + (busClkPs-1)) / busClkPs; -+ mvOsOutput("Minimum Row Precharge Time [ns]: %d.%d = " -+ "in Clk cycles %d\n", -+ leftOfPoint, rightOfPoint, trp_clocks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 28: /* Minimum Row Active to Row Active Time */ -+ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; -+ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0xff : 0xfc; -+ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0x00 : 0x03; -+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); -+ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; -+ temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ -+ trrd_clocks = (temp + (busClkPs-1)) / busClkPs; -+ mvOsOutput("Minimum Row Active -To- Row Active Delay [ns]: " -+ "%d.%d = in Clk cycles %d\n", -+ leftOfPoint, rightOfPoint, trp_clocks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 29: /* Minimum Ras-To-Cas Delay */ -+ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; -+ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0xff : 0xfc; -+ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0x00 : 0x03; -+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); -+ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; -+ temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ -+ trcd_clocks = (temp + (busClkPs-1) )/ busClkPs; -+ mvOsOutput("Minimum Ras-To-Cas Delay [ns]: %d.%d = " -+ "in Clk cycles %d\n", -+ leftOfPoint, rightOfPoint, trp_clocks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 30: /* Minimum Ras Pulse Width */ -+ tras_clocks = (cas2ps(spdRawData[i])+(busClkPs-1)) / busClkPs; -+ mvOsOutput("Minimum Ras Pulse Width [ns]: %d = " -+ "in Clk cycles %d\n", spdRawData[i], tras_clocks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 31: /* Module Bank Density */ -+ mvOsOutput("Module Bank Density (more than 1= Multisize-Module):"); -+ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ if (dimmInfo.dimmBankDensity & BIT0) -+ mvOsOutput("1GB, "); -+ if (dimmInfo.dimmBankDensity & BIT1) -+ mvOsOutput("8MB, "); -+ if (dimmInfo.dimmBankDensity & BIT2) -+ mvOsOutput("16MB, "); -+ if (dimmInfo.dimmBankDensity & BIT3) -+ mvOsOutput("32MB, "); -+ if (dimmInfo.dimmBankDensity & BIT4) -+ mvOsOutput("64MB, "); -+ if (dimmInfo.dimmBankDensity & BIT5) -+ mvOsOutput("128MB, "); -+ if (dimmInfo.dimmBankDensity & BIT6) -+ mvOsOutput("256MB, "); -+ if (dimmInfo.dimmBankDensity & BIT7) -+ mvOsOutput("512MB, "); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ { -+ if (dimmInfo.dimmBankDensity & BIT0) -+ mvOsOutput("1GB, "); -+ if (dimmInfo.dimmBankDensity & BIT1) -+ mvOsOutput("2GB, "); -+ if (dimmInfo.dimmBankDensity & BIT2) -+ mvOsOutput("16MB, "); -+ if (dimmInfo.dimmBankDensity & BIT3) -+ mvOsOutput("32MB, "); -+ if (dimmInfo.dimmBankDensity & BIT4) -+ mvOsOutput("64MB, "); -+ if (dimmInfo.dimmBankDensity & BIT5) -+ mvOsOutput("128MB, "); -+ if (dimmInfo.dimmBankDensity & BIT6) -+ mvOsOutput("256MB, "); -+ if (dimmInfo.dimmBankDensity & BIT7) -+ mvOsOutput("512MB, "); -+ } -+ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ -+ { -+ if (dimmInfo.dimmBankDensity & BIT0) -+ mvOsOutput("1GB, "); -+ if (dimmInfo.dimmBankDensity & BIT1) -+ mvOsOutput("2GB, "); -+ if (dimmInfo.dimmBankDensity & BIT2) -+ mvOsOutput("4GB, "); -+ if (dimmInfo.dimmBankDensity & BIT3) -+ mvOsOutput("8GB, "); -+ if (dimmInfo.dimmBankDensity & BIT4) -+ mvOsOutput("16GB, "); -+ if (dimmInfo.dimmBankDensity & BIT5) -+ mvOsOutput("128MB, "); -+ if (dimmInfo.dimmBankDensity & BIT6) -+ mvOsOutput("256MB, "); -+ if (dimmInfo.dimmBankDensity & BIT7) -+ mvOsOutput("512MB, "); -+ } -+ mvOsOutput("\n"); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 32: /* Address And Command Setup Time (measured in ns/1000) */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ rightOfPoint = (spdRawData[i] & 0x0f); -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ if(leftOfPoint > 7) -+ { -+ leftOfPoint *= -1; -+ } -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / 100; -+ rightOfPoint = time_tmp % 100; -+ } -+ mvOsOutput("Address And Command Setup Time [ns]: %d.%d\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 33: /* Address And Command Hold Time */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ rightOfPoint = (spdRawData[i] & 0x0f); -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ if(leftOfPoint > 7) -+ { -+ leftOfPoint *= -1; -+ } -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / 100; -+ rightOfPoint = time_tmp % 100; -+ } -+ mvOsOutput("Address And Command Hold Time [ns]: %d.%d\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 34: /* Data Input Setup Time */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ rightOfPoint = (spdRawData[i] & 0x0f); -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ if(leftOfPoint > 7) -+ { -+ leftOfPoint *= -1; -+ } -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / 100; -+ rightOfPoint = time_tmp % 100; -+ } -+ mvOsOutput("Data Input Setup Time [ns]: %d.%d\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 35: /* Data Input Hold Time */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ rightOfPoint = (spdRawData[i] & 0x0f); -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ if(leftOfPoint > 7) -+ { -+ leftOfPoint *= -1; -+ } -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / 100; -+ rightOfPoint = time_tmp % 100; -+ } -+ mvOsOutput("Data Input Hold Time [ns]: %d.%d\n\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 36: /* Relevant for DDR2 only: Write Recovery Time */ -+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> 2); -+ rightOfPoint = (spdRawData[i] & maskRightOfPoint) * 25; -+ mvOsOutput("Write Recovery Time [ns]: %d.%d\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ } -+ -+} -+ -+ -+/* -+ * translate ns.ns/10 coding of SPD timing values -+ * into ps unit values -+ */ -+/******************************************************************************* -+* cas2ps - Translate x.y ns parameter to pico-seconds values -+* -+* DESCRIPTION: -+* This function translates x.y nano seconds to its value in pico seconds. -+* For example 3.75ns will return 3750. -+* -+* INPUT: -+* spd_byte - DIMM SPD byte. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* value in pico seconds. -+* -+*******************************************************************************/ -+static MV_U32 cas2ps(MV_U8 spd_byte) -+{ -+ MV_U32 ns, ns10; -+ -+ /* isolate upper nibble */ -+ ns = (spd_byte >> 4) & 0x0F; -+ /* isolate lower nibble */ -+ ns10 = (spd_byte & 0x0F); -+ -+ if( ns10 < 10 ) { -+ ns10 *= 10; -+ } -+ else if( ns10 == 10 ) -+ ns10 = 25; -+ else if( ns10 == 11 ) -+ ns10 = 33; -+ else if( ns10 == 12 ) -+ ns10 = 66; -+ else if( ns10 == 13 ) -+ ns10 = 75; -+ else -+ { -+ mvOsOutput("cas2ps Err. unsupported cycle time.\n"); -+ } -+ -+ return (ns*1000 + ns10*10); -+} -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h 2010-11-09 20:28:11.032495447 +0100 -@@ -0,0 +1,192 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvDram -+#define __INCmvDram -+ -+#include "ddr2/mvDramIf.h" -+#include "twsi/mvTwsi.h" -+ -+#define MAX_DIMM_NUM 2 -+#define SPD_SIZE 128 -+ -+/* Dimm spd offsets */ -+#define DIMM_MEM_TYPE 2 -+#define DIMM_ROW_NUM 3 -+#define DIMM_COL_NUM 4 -+#define DIMM_MODULE_BANK_NUM 5 -+#define DIMM_DATA_WIDTH 6 -+#define DIMM_VOLT_IF 8 -+#define DIMM_MIN_CC_AT_MAX_CAS 9 -+#define DIMM_ERR_CHECK_TYPE 11 -+#define DIMM_REFRESH_INTERVAL 12 -+#define DIMM_SDRAM_WIDTH 13 -+#define DIMM_ERR_CHECK_DATA_WIDTH 14 -+#define DIMM_MIN_CLK_DEL 15 -+#define DIMM_BURST_LEN_SUP 16 -+#define DIMM_DEV_BANK_NUM 17 -+#define DIMM_SUP_CAL 18 -+#define DIMM_DDR2_TYPE_INFORMATION 20 /* DDR2 only */ -+#define DIMM_BUF_ADDR_CONT_IN 21 -+#define DIMM_MIN_CC_AT_MAX_CAS_MINUS1 23 -+#define DIMM_MIN_CC_AT_MAX_CAS_MINUS2 25 -+#define DIMM_MIN_ROW_PRECHARGE_TIME 27 -+#define DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE 28 -+#define DIMM_MIN_RAS_TO_CAS_DELAY 29 -+#define DIMM_MIN_RAS_PULSE_WIDTH 30 -+#define DIMM_BANK_DENSITY 31 -+#define DIMM_MIN_WRITE_RECOVERY_TIME 36 -+#define DIMM_MIN_WRITE_TO_READ_CMD_DELAY 37 -+#define DIMM_MIN_READ_TO_PRECH_CMD_DELAY 38 -+#define DIMM_MIN_REFRESH_TO_ACTIVATE_CMD 42 -+#define DIMM_SPD_VERSION 62 -+ -+/* Dimm Memory Type values */ -+#define DIMM_MEM_TYPE_SDRAM 0x4 -+#define DIMM_MEM_TYPE_DDR1 0x7 -+#define DIMM_MEM_TYPE_DDR2 0x8 -+ -+#define DIMM_MODULE_MANU_OFFS 64 -+#define DIMM_MODULE_MANU_SIZE 8 -+#define DIMM_MODULE_VEN_OFFS 73 -+#define DIMM_MODULE_VEN_SIZE 25 -+#define DIMM_MODULE_ID_OFFS 99 -+#define DIMM_MODULE_ID_SIZE 18 -+ -+/* enumeration for voltage levels. */ -+typedef enum _mvDimmVoltageIf -+{ -+ TTL_5V_TOLERANT, -+ LVTTL, -+ HSTL_1_5V, -+ SSTL_3_3V, -+ SSTL_2_5V, -+ VOLTAGE_UNKNOWN, -+} MV_DIMM_VOLTAGE_IF; -+ -+ -+/* enumaration for SDRAM CAS Latencies. */ -+typedef enum _mvDimmSdramCas -+{ -+ SD_CL_1 =1, -+ SD_CL_2, -+ SD_CL_3, -+ SD_CL_4, -+ SD_CL_5, -+ SD_CL_6, -+ SD_CL_7, -+ SD_FAULT -+}MV_DIMM_SDRAM_CAS; -+ -+ -+/* DIMM information structure */ -+typedef struct _mvDimmInfo -+{ -+ MV_MEMORY_TYPE memoryType; /* DDR or SDRAM */ -+ -+ MV_U8 spdRawData[SPD_SIZE]; /* Content of SPD-EEPROM copied 1:1 */ -+ -+ /* DIMM dimensions */ -+ MV_U32 numOfRowAddr; -+ MV_U32 numOfColAddr; -+ MV_U32 numOfModuleBanks; -+ MV_U32 dataWidth; -+ MV_U32 errorCheckType; /* ECC , PARITY..*/ -+ MV_U32 sdramWidth; /* 4,8,16 or 32 */ -+ MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ -+ MV_U32 burstLengthSupported; -+ MV_U32 numOfBanksOnEachDevice; -+ MV_U32 suportedCasLatencies; -+ MV_U32 refreshInterval; -+ MV_U32 dimmBankDensity; -+ MV_U32 dimmTypeInfo; /* DDR2 only */ -+ MV_U32 dimmAttributes; -+ -+ /* DIMM timing parameters */ -+ MV_U32 minCycleTimeAtMaxCasLatPs; -+ MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; -+ MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; -+ MV_U32 minRowPrechargeTime; -+ MV_U32 minRowActiveToRowActive; -+ MV_U32 minRasToCasDelay; -+ MV_U32 minRasPulseWidth; -+ MV_U32 minWriteRecoveryTime; /* DDR2 only */ -+ MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ -+ MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ -+ MV_U32 minRefreshToActiveCmd; /* DDR2 only */ -+ -+ /* Parameters calculated from the extracted DIMM information */ -+ MV_U32 size; /* 16,64,128,256 or 512 MByte in MB units */ -+ MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit in MB units */ -+ MV_U32 numberOfDevices; -+ -+} MV_DIMM_INFO; -+ -+ -+MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo); -+MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo); -+MV_VOID dimmSpdPrint(MV_U32 dimmNum); -+MV_STATUS dimmSpdCpy(MV_VOID); -+ -+#endif /* __INCmvDram */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEth.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEth.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEth.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEth.c 2010-11-09 20:28:11.042495489 +0100 -@@ -0,0 +1,2952 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+/******************************************************************************* -+* mvEth.c - Marvell's Gigabit Ethernet controller low level driver -+* -+* DESCRIPTION: -+* This file introduce OS independent APIs to Marvell's Gigabit Ethernet -+* controller. This Gigabit Ethernet Controller driver API controls -+* 1) Operations (i.e. port Init, Finish, Up, Down, PhyReset etc'). -+* 2) Data flow (i.e. port Send, Receive etc'). -+* 3) MAC Filtering functions (ethSetMcastAddr, ethSetRxFilterMode, etc.) -+* 4) MIB counters support (ethReadMibCounter) -+* 5) Debug functions (ethPortRegs, ethPortCounters, ethPortQueues, etc.) -+* Each Gigabit Ethernet port is controlled via ETH_PORT_CTRL struct. -+* This struct includes configuration information as well as driver -+* internal data needed for its operations. -+* -+* Supported Features: -+* - OS independent. All required OS services are implemented via external -+* OS dependent components (like osLayer or ethOsg) -+* - The user is free from Rx/Tx queue managing. -+* - Simple Gigabit Ethernet port operation API. -+* - Simple Gigabit Ethernet port data flow API. -+* - Data flow and operation API support per queue functionality. -+* - Support cached descriptors for better performance. -+* - PHY access and control API. -+* - Port Configuration API. -+* - Full control over Special and Other Multicast MAC tables. -+* -+*******************************************************************************/ -+/* includes */ -+#include "mvTypes.h" -+#include "mv802_3.h" -+#include "mvDebug.h" -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "eth-phy/mvEthPhy.h" -+#include "eth/mvEth.h" -+#include "eth/gbe/mvEthGbe.h" -+#include "cpu/mvCpu.h" -+ -+#ifdef INCLUDE_SYNC_BARR -+#include "sys/mvCpuIf.h" -+#endif -+ -+#ifdef MV_RT_DEBUG -+# define ETH_DEBUG -+#endif -+ -+ -+/* locals */ -+MV_BOOL ethDescInSram; -+MV_BOOL ethDescSwCoher; -+ -+/* This array holds the control structure of each port */ -+ETH_PORT_CTRL* ethPortCtrl[MV_ETH_MAX_PORTS]; -+ -+/* Ethernet Port Local routines */ -+ -+static void ethInitRxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue); -+ -+static void ethInitTxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue); -+ -+static void ethSetUcastTable(int portNo, int queue); -+ -+static MV_BOOL ethSetUcastAddr (int ethPortNum, MV_U8 lastNibble, int queue); -+static MV_BOOL ethSetSpecialMcastAddr(int ethPortNum, MV_U8 lastByte, int queue); -+static MV_BOOL ethSetOtherMcastAddr(int ethPortNum, MV_U8 crc8, int queue); -+ -+static void ethFreeDescrMemory(ETH_PORT_CTRL* pEthPortCtrl, MV_BUF_INFO* pDescBuf); -+static MV_U8* ethAllocDescrMemory(ETH_PORT_CTRL* pEthPortCtrl, int size, -+ MV_ULONG* pPhysAddr, MV_U32 *memHandle); -+ -+static MV_U32 mvEthMruGet(MV_U32 maxRxPktSize); -+ -+static void mvEthPortSgmiiConfig(int port); -+ -+ -+ -+/******************************************************************************/ -+/* EthDrv Initialization functions */ -+/******************************************************************************/ -+ -+/******************************************************************************* -+* mvEthHalInit - Initialize the Giga Ethernet unit -+* -+* DESCRIPTION: -+* This function initialize the Giga Ethernet unit. -+* 1) Configure Address decode windows of the unit -+* 2) Set registers to HW default values. -+* 3) Clear and Disable interrupts -+* -+* INPUT: NONE -+* -+* RETURN: NONE -+* -+* NOTE: this function is called once in the boot process. -+*******************************************************************************/ -+void mvEthHalInit(void) -+{ -+ int port; -+ -+ /* Init static data structures */ -+ for (port=0; port 0) -+ { -+ isSram = MV_TRUE; -+ #if (INTEG_SRAM_COHER == MV_CACHE_COHER_SW) -+ isSwCoher = MV_TRUE; -+ #else -+ isSwCoher = MV_FALSE; -+ #endif -+ } -+#endif /* ETH_DESCR_IN_SRAM */ -+ -+ if(pIsSram != NULL) -+ *pIsSram = isSram; -+ -+ if(pIsSwCoher != NULL) -+ *pIsSwCoher = isSwCoher; -+} -+ -+ -+ -+/******************************************************************************/ -+/* Port Initialization functions */ -+/******************************************************************************/ -+ -+/******************************************************************************* -+* mvEthPortInit - Initialize the Ethernet port driver -+* -+* DESCRIPTION: -+* This function initialize the ethernet port. -+* 1) Allocate and initialize internal port Control structure. -+* 2) Create RX and TX descriptor rings for default RX and TX queues -+* 3) Disable RX and TX operations, clear cause registers and -+* mask all interrupts. -+* 4) Set all registers to default values and clean all MAC tables. -+* -+* INPUT: -+* int portNo - Ethernet port number -+* ETH_PORT_INIT *pEthPortInit - Ethernet port init structure -+* -+* RETURN: -+* void* - ethernet port handler, that should be passed to the most other -+* functions dealing with this port. -+* -+* NOTE: This function is called once per port when loading the eth module. -+*******************************************************************************/ -+void* mvEthPortInit(int portNo, MV_ETH_PORT_INIT *pEthPortInit) -+{ -+ int queue, descSize; -+ ETH_PORT_CTRL* pPortCtrl; -+ -+ /* Check validity of parameters */ -+ if( (portNo >= (int)mvCtrlEthMaxPortGet()) || -+ (pEthPortInit->rxDefQ >= MV_ETH_RX_Q_NUM) || -+ (pEthPortInit->maxRxPktSize < 1518) ) -+ { -+ mvOsPrintf("EthPort #%d: Bad initialization parameters\n", portNo); -+ return NULL; -+ } -+ if( (pEthPortInit->rxDescrNum[pEthPortInit->rxDefQ]) == 0) -+ { -+ mvOsPrintf("EthPort #%d: rxDefQ (%d) must be created\n", -+ portNo, pEthPortInit->rxDefQ); -+ return NULL; -+ } -+ -+ pPortCtrl = (ETH_PORT_CTRL*)mvOsMalloc( sizeof(ETH_PORT_CTRL) ); -+ if(pPortCtrl == NULL) -+ { -+ mvOsPrintf("EthDrv: Can't allocate %dB for port #%d control structure!\n", -+ (int)sizeof(ETH_PORT_CTRL), portNo); -+ return NULL; -+ } -+ -+ memset(pPortCtrl, 0, sizeof(ETH_PORT_CTRL) ); -+ ethPortCtrl[portNo] = pPortCtrl; -+ -+ pPortCtrl->portState = MV_UNDEFINED_STATE; -+ -+ pPortCtrl->portNo = portNo; -+ -+ pPortCtrl->osHandle = pEthPortInit->osHandle; -+ -+ /* Copy Configuration parameters */ -+ pPortCtrl->portConfig.maxRxPktSize = pEthPortInit->maxRxPktSize; -+ pPortCtrl->portConfig.rxDefQ = pEthPortInit->rxDefQ; -+ pPortCtrl->portConfig.ejpMode = 0; -+ -+ for( queue=0; queuerxQueueConfig[queue].descrNum = pEthPortInit->rxDescrNum[queue]; -+ } -+ for( queue=0; queuetxQueueConfig[queue].descrNum = pEthPortInit->txDescrNum[queue]; -+ } -+ -+ mvEthPortDisable(pPortCtrl); -+ -+ /* Set the board information regarding PHY address */ -+ mvEthPhyAddrSet(pPortCtrl, mvBoardPhyAddrGet(portNo) ); -+ -+ /* Create all requested RX queues */ -+ for(queue=0; queuerxQueueConfig[queue].descrNum == 0) -+ continue; -+ -+ /* Allocate memory for RX descriptors */ -+ descSize = ((pPortCtrl->rxQueueConfig[queue].descrNum * ETH_RX_DESC_ALIGNED_SIZE) + -+ CPU_D_CACHE_LINE_SIZE); -+ -+ pPortCtrl->rxQueue[queue].descBuf.bufVirtPtr = -+ ethAllocDescrMemory(pPortCtrl, descSize, -+ &pPortCtrl->rxQueue[queue].descBuf.bufPhysAddr, -+ &pPortCtrl->rxQueue[queue].descBuf.memHandle); -+ pPortCtrl->rxQueue[queue].descBuf.bufSize = descSize; -+ if(pPortCtrl->rxQueue[queue].descBuf.bufVirtPtr == NULL) -+ { -+ mvOsPrintf("EthPort #%d, rxQ=%d: Can't allocate %d bytes in %s for %d RX descr\n", -+ pPortCtrl->portNo, queue, descSize, -+ ethDescInSram ? "SRAM" : "DRAM", -+ pPortCtrl->rxQueueConfig[queue].descrNum); -+ return NULL; -+ } -+ -+ ethInitRxDescRing(pPortCtrl, queue); -+ } -+ /* Create TX queues */ -+ for(queue=0; queuetxQueueConfig[queue].descrNum == 0) -+ continue; -+ -+ /* Allocate memory for TX descriptors */ -+ descSize = ((pPortCtrl->txQueueConfig[queue].descrNum * ETH_TX_DESC_ALIGNED_SIZE) + -+ CPU_D_CACHE_LINE_SIZE); -+ -+ pPortCtrl->txQueue[queue].descBuf.bufVirtPtr = -+ ethAllocDescrMemory(pPortCtrl, descSize, -+ &pPortCtrl->txQueue[queue].descBuf.bufPhysAddr, -+ &pPortCtrl->txQueue[queue].descBuf.memHandle); -+ pPortCtrl->txQueue[queue].descBuf.bufSize = descSize; -+ if(pPortCtrl->txQueue[queue].descBuf.bufVirtPtr == NULL) -+ { -+ mvOsPrintf("EthPort #%d, txQ=%d: Can't allocate %d bytes in %s for %d TX descr\n", -+ pPortCtrl->portNo, queue, descSize, ethDescInSram ? "SRAM" : "DRAM", -+ pPortCtrl->txQueueConfig[queue].descrNum); -+ return NULL; -+ } -+ -+ ethInitTxDescRing(pPortCtrl, queue); -+ } -+ mvEthDefaultsSet(pPortCtrl); -+ -+ pPortCtrl->portState = MV_IDLE; -+ return pPortCtrl; -+} -+ -+/******************************************************************************* -+* ethPortFinish - Finish the Ethernet port driver -+* -+* DESCRIPTION: -+* This function finish the ethernet port. -+* 1) Down ethernet port if needed. -+* 2) Delete RX and TX descriptor rings for all created RX and TX queues -+* 3) Free internal port Control structure. -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet port handler -+* -+* RETURN: NONE. -+* -+*******************************************************************************/ -+void mvEthPortFinish(void* pPortHndl) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ int queue, portNo = pPortCtrl->portNo; -+ -+ if(pPortCtrl->portState == MV_ACTIVE) -+ { -+ mvOsPrintf("ethPort #%d: Warning !!! Finish port in Active state\n", -+ portNo); -+ mvEthPortDisable(pPortHndl); -+ } -+ -+ /* Free all allocated RX queues */ -+ for(queue=0; queuerxQueue[queue].descBuf); -+ } -+ -+ /* Free all allocated TX queues */ -+ for(queue=0; queuetxQueue[queue].descBuf); -+ } -+ -+ /* Free port control structure */ -+ mvOsFree(pPortCtrl); -+ -+ ethPortCtrl[portNo] = NULL; -+} -+ -+/******************************************************************************* -+* mvEthDefaultsSet - Set defaults to the ethernet port -+* -+* DESCRIPTION: -+* This function set default values to the ethernet port. -+* 1) Clear Cause registers and Mask all interrupts -+* 2) Clear all MAC tables -+* 3) Set defaults to all registers -+* 4) Reset all created RX and TX descriptors ring -+* 5) Reset PHY -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet port handler -+* -+* RETURN: MV_STATUS -+* MV_OK - Success, Others - Failure -+* NOTE: -+* This function update all the port configuration except those set -+* Initialy by the OsGlue by MV_ETH_PORT_INIT. -+* This function can be called after portDown to return the port setting -+* to defaults. -+*******************************************************************************/ -+MV_STATUS mvEthDefaultsSet(void* pPortHndl) -+{ -+ int ethPortNo, queue; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ MV_U32 txPrio; -+ MV_U32 portCfgReg, portCfgExtReg, portSerialCtrlReg, portSerialCtrl1Reg, portSdmaCfgReg; -+ MV_BOARD_MAC_SPEED boardMacCfg; -+ -+ ethPortNo = pPortCtrl->portNo; -+ -+ /* Clear Cause registers */ -+ MV_REG_WRITE(ETH_INTR_CAUSE_REG(ethPortNo),0); -+ MV_REG_WRITE(ETH_INTR_CAUSE_EXT_REG(ethPortNo),0); -+ -+ /* Mask all interrupts */ -+ MV_REG_WRITE(ETH_INTR_MASK_REG(ethPortNo),0); -+ MV_REG_WRITE(ETH_INTR_MASK_EXT_REG(ethPortNo),0); -+ -+ portCfgReg = PORT_CONFIG_VALUE; -+ portCfgExtReg = PORT_CONFIG_EXTEND_VALUE; -+ -+ boardMacCfg = mvBoardMacSpeedGet(ethPortNo); -+ -+ if(boardMacCfg == BOARD_MAC_SPEED_100M) -+ { -+ portSerialCtrlReg = PORT_SERIAL_CONTROL_100MB_FORCE_VALUE; -+ } -+ else if(boardMacCfg == BOARD_MAC_SPEED_1000M) -+ { -+ portSerialCtrlReg = PORT_SERIAL_CONTROL_1000MB_FORCE_VALUE; -+ } -+ else -+ { -+ portSerialCtrlReg = PORT_SERIAL_CONTROL_VALUE; -+ } -+ -+ /* build PORT_SDMA_CONFIG_REG */ -+ portSdmaCfgReg = ETH_TX_INTR_COAL_MASK(0); -+ portSdmaCfgReg |= ETH_TX_BURST_SIZE_MASK(ETH_BURST_SIZE_16_64BIT_VALUE); -+ -+#if ( (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WB) || \ -+ (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WT) ) -+ /* some devices have restricted RX burst size when using HW coherency */ -+ portSdmaCfgReg |= ETH_RX_BURST_SIZE_MASK(ETH_BURST_SIZE_4_64BIT_VALUE); -+#else -+ portSdmaCfgReg |= ETH_RX_BURST_SIZE_MASK(ETH_BURST_SIZE_16_64BIT_VALUE); -+#endif -+ -+#if defined(MV_CPU_BE) -+ /* big endian */ -+# if defined(MV_ARM) -+ portSdmaCfgReg |= (ETH_RX_NO_DATA_SWAP_MASK | -+ ETH_TX_NO_DATA_SWAP_MASK | -+ ETH_DESC_SWAP_MASK); -+# elif defined(MV_PPC) -+ portSdmaCfgReg |= (ETH_RX_DATA_SWAP_MASK | -+ ETH_TX_DATA_SWAP_MASK | -+ ETH_NO_DESC_SWAP_MASK); -+# else -+# error "Giga Ethernet Swap policy is not defined for the CPU_ARCH" -+# endif /* MV_ARM / MV_PPC */ -+ -+#else /* MV_CPU_LE */ -+ /* little endian */ -+ portSdmaCfgReg |= (ETH_RX_NO_DATA_SWAP_MASK | -+ ETH_TX_NO_DATA_SWAP_MASK | -+ ETH_NO_DESC_SWAP_MASK); -+#endif /* MV_CPU_BE / MV_CPU_LE */ -+ -+ pPortCtrl->portRxQueueCmdReg = 0; -+ pPortCtrl->portTxQueueCmdReg = 0; -+ -+#if (MV_ETH_VERSION >= 4) -+ if(pPortCtrl->portConfig.ejpMode == MV_TRUE) -+ { -+ MV_REG_WRITE(ETH_TXQ_CMD_1_REG(ethPortNo), ETH_TX_EJP_ENABLE_MASK); -+ } -+ else -+ { -+ MV_REG_WRITE(ETH_TXQ_CMD_1_REG(ethPortNo), 0) -+ } -+#endif /* (MV_ETH_VERSION >= 4) */ -+ -+ ethSetUcastTable(ethPortNo, -1); -+ mvEthSetSpecialMcastTable(ethPortNo, -1); -+ mvEthSetOtherMcastTable(ethPortNo, -1); -+ -+ portSerialCtrlReg &= ~ETH_MAX_RX_PACKET_SIZE_MASK; -+ -+ portSerialCtrlReg |= mvEthMruGet(pPortCtrl->portConfig.maxRxPktSize); -+ -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNo), portSerialCtrlReg); -+ -+ /* Update value of PortConfig register accordingly with all RxQueue types */ -+ pPortCtrl->portConfig.rxArpQ = pPortCtrl->portConfig.rxDefQ; -+ pPortCtrl->portConfig.rxBpduQ = pPortCtrl->portConfig.rxDefQ; -+ pPortCtrl->portConfig.rxTcpQ = pPortCtrl->portConfig.rxDefQ; -+ pPortCtrl->portConfig.rxUdpQ = pPortCtrl->portConfig.rxDefQ; -+ -+ portCfgReg &= ~ETH_DEF_RX_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_QUEUE_MASK(pPortCtrl->portConfig.rxDefQ); -+ -+ portCfgReg &= ~ETH_DEF_RX_ARP_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_ARP_QUEUE_MASK(pPortCtrl->portConfig.rxArpQ); -+ -+ portCfgReg &= ~ETH_DEF_RX_BPDU_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_BPDU_QUEUE_MASK(pPortCtrl->portConfig.rxBpduQ); -+ -+ portCfgReg &= ~ETH_DEF_RX_TCP_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_TCP_QUEUE_MASK(pPortCtrl->portConfig.rxTcpQ); -+ -+ portCfgReg &= ~ETH_DEF_RX_UDP_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_UDP_QUEUE_MASK(pPortCtrl->portConfig.rxUdpQ); -+ -+ /* Assignment of Tx CTRP of given queue */ -+ txPrio = 0; -+ -+ for(queue=0; queuetxQueue[queue]; -+ -+ if(pQueueCtrl->pFirstDescr != NULL) -+ { -+ ethResetTxDescRing(pPortCtrl, queue); -+ -+ MV_REG_WRITE(ETH_TXQ_TOKEN_COUNT_REG(ethPortNo, queue), -+ 0x3fffffff); -+ MV_REG_WRITE(ETH_TXQ_TOKEN_CFG_REG(ethPortNo, queue), -+ 0x03ffffff); -+ } -+ else -+ { -+ MV_REG_WRITE(ETH_TXQ_TOKEN_COUNT_REG(ethPortNo, queue), 0x0); -+ MV_REG_WRITE(ETH_TXQ_TOKEN_CFG_REG(ethPortNo, queue), 0x0); -+ } -+ } -+ -+ /* Assignment of Rx CRDP of given queue */ -+ for(queue=0; queueportNo; -+ -+ if( (pPortCtrl->portState != MV_ACTIVE) && -+ (pPortCtrl->portState != MV_PAUSED) ) -+ { -+ mvOsPrintf("ethDrv port%d: Unexpected port state %d\n", -+ ethPortNo, pPortCtrl->portState); -+ return MV_BAD_STATE; -+ } -+ -+ ethPortNo = pPortCtrl->portNo; -+ -+ /* Enable port RX. */ -+ MV_REG_WRITE(ETH_RX_QUEUE_COMMAND_REG(ethPortNo), pPortCtrl->portRxQueueCmdReg); -+ -+ /* Enable port TX. */ -+ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(ethPortNo)) = pPortCtrl->portTxQueueCmdReg; -+ -+ pPortCtrl->portState = MV_ACTIVE; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* ethPortDown - Stop the Ethernet port activity. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet port handler -+* -+* RETURN: MV_STATUS -+* MV_OK - Success, Others - Failure. -+* -+* NOTE : used for port link down. -+*******************************************************************************/ -+MV_STATUS mvEthPortDown(void* pEthPortHndl) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ int ethPortNum = pPortCtrl->portNo; -+ unsigned int regData; -+ volatile int uDelay, mDelay; -+ -+ /* Stop Rx port activity. Check port Rx activity. */ -+ regData = (MV_REG_READ(ETH_RX_QUEUE_COMMAND_REG(ethPortNum))) & ETH_RXQ_ENABLE_MASK; -+ if(regData != 0) -+ { -+ /* Issue stop command for active channels only */ -+ MV_REG_WRITE(ETH_RX_QUEUE_COMMAND_REG(ethPortNum), (regData << ETH_RXQ_DISABLE_OFFSET)); -+ } -+ -+ /* Stop Tx port activity. Check port Tx activity. */ -+ regData = (MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(ethPortNum))) & ETH_TXQ_ENABLE_MASK; -+ if(regData != 0) -+ { -+ /* Issue stop command for active channels only */ -+ MV_REG_WRITE(ETH_TX_QUEUE_COMMAND_REG(ethPortNum), -+ (regData << ETH_TXQ_DISABLE_OFFSET) ); -+ } -+ -+ /* Force link down */ -+/* -+ regData = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNum)); -+ regData &= ~(ETH_DO_NOT_FORCE_LINK_FAIL_MASK); -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNum), regData); -+*/ -+ /* Wait for all Rx activity to terminate. */ -+ mDelay = 0; -+ do -+ { -+ if(mDelay >= RX_DISABLE_TIMEOUT_MSEC) -+ { -+ mvOsPrintf("ethPort_%d: TIMEOUT for RX stopped !!! rxQueueCmd - 0x08%x\n", -+ ethPortNum, regData); -+ break; -+ } -+ mvOsDelay(1); -+ mDelay++; -+ -+ /* Check port RX Command register that all Rx queues are stopped */ -+ regData = MV_REG_READ(ETH_RX_QUEUE_COMMAND_REG(ethPortNum)); -+ } -+ while(regData & 0xFF); -+ -+ /* Wait for all Tx activity to terminate. */ -+ mDelay = 0; -+ do -+ { -+ if(mDelay >= TX_DISABLE_TIMEOUT_MSEC) -+ { -+ mvOsPrintf("ethPort_%d: TIMEOUT for TX stoped !!! txQueueCmd - 0x08%x\n", -+ ethPortNum, regData); -+ break; -+ } -+ mvOsDelay(1); -+ mDelay++; -+ -+ /* Check port TX Command register that all Tx queues are stopped */ -+ regData = MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(ethPortNum)); -+ } -+ while(regData & 0xFF); -+ -+ /* Double check to Verify that TX FIFO is Empty */ -+ mDelay = 0; -+ while(MV_TRUE) -+ { -+ do -+ { -+ if(mDelay >= TX_FIFO_EMPTY_TIMEOUT_MSEC) -+ { -+ mvOsPrintf("\n ethPort_%d: TIMEOUT for TX FIFO empty !!! portStatus - 0x08%x\n", -+ ethPortNum, regData); -+ break; -+ } -+ mvOsDelay(1); -+ mDelay++; -+ -+ regData = MV_REG_READ(ETH_PORT_STATUS_REG(ethPortNum)); -+ } -+ while( ((regData & ETH_TX_FIFO_EMPTY_MASK) == 0) || -+ ((regData & ETH_TX_IN_PROGRESS_MASK) != 0) ); -+ -+ if(mDelay >= TX_FIFO_EMPTY_TIMEOUT_MSEC) -+ break; -+ -+ /* Double check */ -+ regData = MV_REG_READ(ETH_PORT_STATUS_REG(ethPortNum)); -+ if( ((regData & ETH_TX_FIFO_EMPTY_MASK) != 0) && -+ ((regData & ETH_TX_IN_PROGRESS_MASK) == 0) ) -+ { -+ break; -+ } -+ else -+ mvOsPrintf("ethPort_%d: TX FIFO Empty double check failed. %d msec, portStatus=0x%x\n", -+ ethPortNum, mDelay, regData); -+ } -+ -+ /* Do NOT force link down */ -+/* -+ regData = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNum)); -+ regData |= (ETH_DO_NOT_FORCE_LINK_FAIL_MASK); -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNum), regData); -+*/ -+ /* Wait about 2500 tclk cycles */ -+ uDelay = (PORT_DISABLE_WAIT_TCLOCKS/(mvBoardTclkGet()/1000000)); -+ mvOsUDelay(uDelay); -+ -+ pPortCtrl->portState = MV_PAUSED; -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* ethPortEnable - Enable the Ethernet port and Start RX and TX. -+* -+* DESCRIPTION: -+* This routine enable the Ethernet port and Rx and Tx activity: -+* -+* Note: Each Rx and Tx queue descriptor's list must be initialized prior -+* to calling this function (use etherInitTxDescRing for Tx queues and -+* etherInitRxDescRing for Rx queues). -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet port handler -+* -+* RETURN: MV_STATUS -+* MV_OK - Success, Others - Failure. -+* -+* NOTE: main usage is to enable the port after ifconfig up. -+*******************************************************************************/ -+MV_STATUS mvEthPortEnable(void* pEthPortHndl) -+{ -+ int ethPortNo; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ MV_U32 portSerialCtrlReg; -+ -+ ethPortNo = pPortCtrl->portNo; -+ -+ /* Enable port */ -+ portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNo)); -+ portSerialCtrlReg |= (ETH_DO_NOT_FORCE_LINK_FAIL_MASK | ETH_PORT_ENABLE_MASK); -+ -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNo), portSerialCtrlReg); -+ -+ mvEthMibCountersClear(pEthPortHndl); -+ -+ pPortCtrl->portState = MV_PAUSED; -+ -+ /* If Link is UP, Start RX and TX traffic */ -+ if( MV_REG_READ( ETH_PORT_STATUS_REG(ethPortNo) ) & ETH_LINK_UP_MASK) -+ return( mvEthPortUp(pEthPortHndl) ); -+ -+ return MV_NOT_READY; -+} -+ -+ -+/******************************************************************************* -+* mvEthPortDisable - Stop RX and TX activities and Disable the Ethernet port. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet port handler -+* -+* RETURN: MV_STATUS -+* MV_OK - Success, Others - Failure. -+* -+* NOTE: main usage is to disable the port after ifconfig down. -+*******************************************************************************/ -+MV_STATUS mvEthPortDisable(void* pEthPortHndl) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ int ethPortNum = pPortCtrl->portNo; -+ unsigned int regData; -+ volatile int mvDelay; -+ -+ if(pPortCtrl->portState == MV_ACTIVE) -+ { -+ /* Stop RX and TX activities */ -+ mvEthPortDown(pEthPortHndl); -+ } -+ -+ /* Reset the Enable bit in the Serial Control Register */ -+ regData = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNum)); -+ regData &= ~(ETH_PORT_ENABLE_MASK); -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNum), regData); -+ -+ /* Wait about 2500 tclk cycles */ -+ mvDelay = (PORT_DISABLE_WAIT_TCLOCKS*(mvCpuPclkGet()/mvBoardTclkGet())); -+ for(mvDelay; mvDelay>0; mvDelay--); -+ -+ pPortCtrl->portState = MV_IDLE; -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthPortForceTxDone - Get next buffer from TX queue in spite of buffer ownership. -+* -+* DESCRIPTION: -+* This routine used to free buffers attached to the Tx ring and should -+* be called only when Giga Ethernet port is Down -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet Port handler. -+* int txQueue - Number of TX queue. -+* -+* OUTPUT: -+* MV_PKT_INFO *pPktInfo - Pointer to packet was sent. -+* -+* RETURN: -+* MV_EMPTY - There is no more buffers in this queue. -+* MV_OK - Buffer detached from the queue and pPktInfo structure -+* filled with relevant information. -+* -+*******************************************************************************/ -+MV_PKT_INFO* mvEthPortForceTxDone(void* pEthPortHndl, int txQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ MV_PKT_INFO* pPktInfo; -+ ETH_TX_DESC* pTxDesc; -+ int port = pPortCtrl->portNo; -+ -+ pQueueCtrl = &pPortCtrl->txQueue[txQueue]; -+ -+ while( (pQueueCtrl->pUsedDescr != pQueueCtrl->pCurrentDescr) || -+ (pQueueCtrl->resource == 0) ) -+ { -+ /* Free next descriptor */ -+ pQueueCtrl->resource++; -+ pTxDesc = (ETH_TX_DESC*)pQueueCtrl->pUsedDescr; -+ -+ /* pPktInfo is available only in descriptors which are last descriptors */ -+ pPktInfo = (MV_PKT_INFO*)pTxDesc->returnInfo; -+ if (pPktInfo) -+ pPktInfo->status = pTxDesc->cmdSts; -+ -+ pTxDesc->cmdSts = 0x0; -+ pTxDesc->returnInfo = 0x0; -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxDesc); -+ -+ pQueueCtrl->pUsedDescr = TX_NEXT_DESC_PTR(pTxDesc, pQueueCtrl); -+ -+ if (pPktInfo) -+ if (pPktInfo->status & ETH_TX_LAST_DESC_MASK) -+ return pPktInfo; -+ } -+ MV_REG_WRITE( ETH_TX_CUR_DESC_PTR_REG(port, txQueue), -+ (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); -+ return NULL; -+} -+ -+ -+ -+/******************************************************************************* -+* mvEthPortForceRx - Get next buffer from RX queue in spite of buffer ownership. -+* -+* DESCRIPTION: -+* This routine used to free buffers attached to the Rx ring and should -+* be called only when Giga Ethernet port is Down -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet Port handler. -+* int rxQueue - Number of Rx queue. -+* -+* OUTPUT: -+* MV_PKT_INFO *pPktInfo - Pointer to received packet. -+* -+* RETURN: -+* MV_EMPTY - There is no more buffers in this queue. -+* MV_OK - Buffer detached from the queue and pBufInfo structure -+* filled with relevant information. -+* -+*******************************************************************************/ -+MV_PKT_INFO* mvEthPortForceRx(void* pEthPortHndl, int rxQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ ETH_RX_DESC* pRxDesc; -+ MV_PKT_INFO* pPktInfo; -+ int port = pPortCtrl->portNo; -+ -+ pQueueCtrl = &pPortCtrl->rxQueue[rxQueue]; -+ -+ if(pQueueCtrl->resource == 0) -+ { -+ MV_REG_WRITE( ETH_RX_CUR_DESC_PTR_REG(port, rxQueue), -+ (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); -+ -+ return NULL; -+ } -+ /* Free next descriptor */ -+ pQueueCtrl->resource--; -+ pRxDesc = (ETH_RX_DESC*)pQueueCtrl->pCurrentDescr; -+ pPktInfo = (MV_PKT_INFO*)pRxDesc->returnInfo; -+ -+ pPktInfo->status = pRxDesc->cmdSts; -+ pRxDesc->cmdSts = 0x0; -+ pRxDesc->returnInfo = 0x0; -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxDesc); -+ -+ pQueueCtrl->pCurrentDescr = RX_NEXT_DESC_PTR(pRxDesc, pQueueCtrl); -+ return pPktInfo; -+} -+ -+ -+/******************************************************************************/ -+/* Port Configuration functions */ -+/******************************************************************************/ -+/******************************************************************************* -+* mvEthMruGet - Get MRU configuration for Max Rx packet size. -+* -+* INPUT: -+* MV_U32 maxRxPktSize - max packet size. -+* -+* RETURN: MV_U32 - MRU configuration. -+* -+*******************************************************************************/ -+static MV_U32 mvEthMruGet(MV_U32 maxRxPktSize) -+{ -+ MV_U32 portSerialCtrlReg = 0; -+ -+ if(maxRxPktSize > 9192) -+ portSerialCtrlReg |= ETH_MAX_RX_PACKET_9700BYTE; -+ else if(maxRxPktSize > 9022) -+ portSerialCtrlReg |= ETH_MAX_RX_PACKET_9192BYTE; -+ else if(maxRxPktSize > 1552) -+ portSerialCtrlReg |= ETH_MAX_RX_PACKET_9022BYTE; -+ else if(maxRxPktSize > 1522) -+ portSerialCtrlReg |= ETH_MAX_RX_PACKET_1552BYTE; -+ else if(maxRxPktSize > 1518) -+ portSerialCtrlReg |= ETH_MAX_RX_PACKET_1522BYTE; -+ else -+ portSerialCtrlReg |= ETH_MAX_RX_PACKET_1518BYTE; -+ -+ return portSerialCtrlReg; -+} -+ -+/******************************************************************************* -+* mvEthRxCoalSet - Sets coalescing interrupt mechanism on RX path -+* -+* DESCRIPTION: -+* This routine sets the RX coalescing interrupt mechanism parameter. -+* This parameter is a timeout counter, that counts in 64 tClk -+* chunks, that when timeout event occurs a maskable interrupt occurs. -+* The parameter is calculated using the tCLK frequency of the -+* MV-64xxx chip, and the required number is in micro seconds. -+* -+* INPUT: -+* void* pPortHndl - Ethernet Port handler. -+* MV_U32 uSec - Number of micro seconds between -+* RX interrupts -+* -+* RETURN: -+* None. -+* -+* COMMENT: -+* 1 sec - TCLK_RATE clocks -+* 1 uSec - TCLK_RATE / 1,000,000 clocks -+* -+* Register Value for N micro seconds - ((N * ( (TCLK_RATE / 1,000,000)) / 64) -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_U32 mvEthRxCoalSet (void* pPortHndl, MV_U32 uSec) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ MV_U32 coal = ((uSec * (mvBoardTclkGet() / 1000000)) / 64); -+ MV_U32 portSdmaCfgReg; -+ -+ portSdmaCfgReg = MV_REG_READ(ETH_SDMA_CONFIG_REG(pPortCtrl->portNo)); -+ portSdmaCfgReg &= ~ETH_RX_INTR_COAL_ALL_MASK; -+ -+ portSdmaCfgReg |= ETH_RX_INTR_COAL_MASK(coal); -+ -+#if (MV_ETH_VERSION >= 2) -+ /* Set additional bit if needed ETH_RX_INTR_COAL_MSB_BIT (25) */ -+ if(ETH_RX_INTR_COAL_MASK(coal) > ETH_RX_INTR_COAL_ALL_MASK) -+ portSdmaCfgReg |= ETH_RX_INTR_COAL_MSB_MASK; -+#endif /* MV_ETH_VERSION >= 2 */ -+ -+ MV_REG_WRITE (ETH_SDMA_CONFIG_REG(pPortCtrl->portNo), portSdmaCfgReg); -+ return coal; -+} -+ -+/******************************************************************************* -+* mvEthTxCoalSet - Sets coalescing interrupt mechanism on TX path -+* -+* DESCRIPTION: -+* This routine sets the TX coalescing interrupt mechanism parameter. -+* This parameter is a timeout counter, that counts in 64 tClk -+* chunks, that when timeout event occurs a maskable interrupt -+* occurs. -+* The parameter is calculated using the tCLK frequency of the -+* MV-64xxx chip, and the required number is in micro seconds. -+* -+* INPUT: -+* void* pPortHndl - Ethernet Port handler. -+* MV_U32 uSec - Number of micro seconds between -+* RX interrupts -+* -+* RETURN: -+* None. -+* -+* COMMENT: -+* 1 sec - TCLK_RATE clocks -+* 1 uSec - TCLK_RATE / 1,000,000 clocks -+* -+* Register Value for N micro seconds - ((N * ( (TCLK_RATE / 1,000,000)) / 64) -+* -+*******************************************************************************/ -+MV_U32 mvEthTxCoalSet(void* pPortHndl, MV_U32 uSec) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ MV_U32 coal = ((uSec * (mvBoardTclkGet() / 1000000)) / 64); -+ MV_U32 regVal; -+ -+ regVal = MV_REG_READ(ETH_TX_FIFO_URGENT_THRESH_REG(pPortCtrl->portNo)); -+ regVal &= ~ETH_TX_INTR_COAL_ALL_MASK; -+ regVal |= ETH_TX_INTR_COAL_MASK(coal); -+ -+ /* Set TX Coalescing mechanism */ -+ MV_REG_WRITE (ETH_TX_FIFO_URGENT_THRESH_REG(pPortCtrl->portNo), regVal); -+ return coal; -+} -+ -+/******************************************************************************* -+* mvEthCoalGet - Gets RX and TX coalescing values in micro seconds -+* -+* DESCRIPTION: -+* This routine gets the RX and TX coalescing interrupt values. -+* The parameter is calculated using the tCLK frequency of the -+* MV-64xxx chip, and the returned numbers are in micro seconds. -+* -+* INPUTs: -+* void* pPortHndl - Ethernet Port handler. -+* -+* OUTPUTs: -+* MV_U32* pRxCoal - Number of micro seconds between RX interrupts -+* MV_U32* pTxCoal - Number of micro seconds between TX interrupts -+* -+* RETURN: -+* MV_STATUS MV_OK - success -+* Others - failure. -+* -+* COMMENT: -+* 1 sec - TCLK_RATE clocks -+* 1 uSec - TCLK_RATE / 1,000,000 clocks -+* -+* Register Value for N micro seconds - ((N * ( (TCLK_RATE / 1,000,000)) / 64) -+* -+*******************************************************************************/ -+MV_STATUS mvEthCoalGet(void* pPortHndl, MV_U32* pRxCoal, MV_U32* pTxCoal) -+{ -+ MV_U32 regVal, coal, usec; -+ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ -+ /* get TX Coalescing */ -+ regVal = MV_REG_READ (ETH_TX_FIFO_URGENT_THRESH_REG(pPortCtrl->portNo)); -+ coal = ((regVal & ETH_TX_INTR_COAL_ALL_MASK) >> ETH_TX_INTR_COAL_OFFSET); -+ -+ usec = (coal * 64) / (mvBoardTclkGet() / 1000000); -+ if(pTxCoal != NULL) -+ *pTxCoal = usec; -+ -+ /* Get RX Coalescing */ -+ regVal = MV_REG_READ(ETH_SDMA_CONFIG_REG(pPortCtrl->portNo)); -+ coal = ((regVal & ETH_RX_INTR_COAL_ALL_MASK) >> ETH_RX_INTR_COAL_OFFSET); -+ -+#if (MV_ETH_VERSION >= 2) -+ if(regVal & ETH_RX_INTR_COAL_MSB_MASK) -+ { -+ /* Add MSB */ -+ coal |= (ETH_RX_INTR_COAL_ALL_MASK + 1); -+ } -+#endif /* MV_ETH_VERSION >= 2 */ -+ -+ usec = (coal * 64) / (mvBoardTclkGet() / 1000000); -+ if(pRxCoal != NULL) -+ *pRxCoal = usec; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthMaxRxSizeSet - -+* -+* DESCRIPTION: -+* Change maximum receive size of the port. This configuration will take place -+* after next call of ethPortSetDefaults() function. -+* -+* INPUT: -+* -+* RETURN: -+*******************************************************************************/ -+MV_STATUS mvEthMaxRxSizeSet(void* pPortHndl, int maxRxSize) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ MV_U32 portSerialCtrlReg; -+ -+ if((maxRxSize < 1518) || (maxRxSize & ~ETH_RX_BUFFER_MASK)) -+ return MV_BAD_PARAM; -+ -+ pPortCtrl->portConfig.maxRxPktSize = maxRxSize; -+ -+ portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(pPortCtrl->portNo)); -+ portSerialCtrlReg &= ~ETH_MAX_RX_PACKET_SIZE_MASK; -+ portSerialCtrlReg |= mvEthMruGet(pPortCtrl->portConfig.maxRxPktSize); -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(pPortCtrl->portNo), portSerialCtrlReg); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************/ -+/* MAC Filtering functions */ -+/******************************************************************************/ -+ -+/******************************************************************************* -+* mvEthRxFilterModeSet - Configure Fitering mode of Ethernet port -+* -+* DESCRIPTION: -+* This routine used to free buffers attached to the Rx ring and should -+* be called only when Giga Ethernet port is Down -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet Port handler. -+* MV_BOOL isPromisc - Promiscous mode -+* MV_TRUE - accept all Broadcast, Multicast -+* and Unicast packets -+* MV_FALSE - accept all Broadcast, -+* specially added Multicast and -+* single Unicast packets -+* -+* RETURN: MV_STATUS MV_OK - Success, Other - Failure -+* -+*******************************************************************************/ -+MV_STATUS mvEthRxFilterModeSet(void* pEthPortHndl, MV_BOOL isPromisc) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ int queue; -+ MV_U32 portCfgReg; -+ -+ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); -+ /* Set / Clear UPM bit in port configuration register */ -+ if(isPromisc) -+ { -+ /* Accept all multicast packets to RX default queue */ -+ queue = pPortCtrl->portConfig.rxDefQ; -+ portCfgReg |= ETH_UNICAST_PROMISCUOUS_MODE_MASK; -+ memset(pPortCtrl->mcastCount, 1, sizeof(pPortCtrl->mcastCount)); -+ MV_REG_WRITE(ETH_MAC_ADDR_LOW_REG(pPortCtrl->portNo),0xFFFF); -+ MV_REG_WRITE(ETH_MAC_ADDR_HIGH_REG(pPortCtrl->portNo),0xFFFFFFFF); -+ } -+ else -+ { -+ /* Reject all Multicast addresses */ -+ queue = -1; -+ portCfgReg &= ~ETH_UNICAST_PROMISCUOUS_MODE_MASK; -+ /* Clear all mcastCount */ -+ memset(pPortCtrl->mcastCount, 0, sizeof(pPortCtrl->mcastCount)); -+ } -+ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); -+ -+ /* Set Special Multicast and Other Multicast tables */ -+ mvEthSetSpecialMcastTable(pPortCtrl->portNo, queue); -+ mvEthSetOtherMcastTable(pPortCtrl->portNo, queue); -+ ethSetUcastTable(pPortCtrl->portNo, queue); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthMacAddrSet - This function Set the port Unicast address. -+* -+* DESCRIPTION: -+* This function Set the port Ethernet MAC address. This address -+* will be used to send Pause frames if enabled. Packets with this -+* address will be accepted and dispatched to default RX queue -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet port handler. -+* char* pAddr - Address to be set -+* -+* RETURN: MV_STATUS -+* MV_OK - Success, Other - Faulure -+* -+*******************************************************************************/ -+MV_STATUS mvEthMacAddrSet(void* pPortHndl, unsigned char *pAddr, int queue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ unsigned int macH; -+ unsigned int macL; -+ -+ if(queue >= MV_ETH_RX_Q_NUM) -+ { -+ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", queue); -+ return MV_BAD_PARAM; -+ } -+ -+ if(queue != -1) -+ { -+ macL = (pAddr[4] << 8) | (pAddr[5]); -+ macH = (pAddr[0] << 24)| (pAddr[1] << 16) | -+ (pAddr[2] << 8) | (pAddr[3] << 0); -+ -+ MV_REG_WRITE(ETH_MAC_ADDR_LOW_REG(pPortCtrl->portNo), macL); -+ MV_REG_WRITE(ETH_MAC_ADDR_HIGH_REG(pPortCtrl->portNo), macH); -+ } -+ -+ /* Accept frames of this address */ -+ ethSetUcastAddr(pPortCtrl->portNo, pAddr[5], queue); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthMacAddrGet - This function returns the port Unicast address. -+* -+* DESCRIPTION: -+* This function returns the port Ethernet MAC address. -+* -+* INPUT: -+* int portNo - Ethernet port number. -+* char* pAddr - Pointer where address will be written to -+* -+* RETURN: MV_STATUS -+* MV_OK - Success, Other - Faulure -+* -+*******************************************************************************/ -+MV_STATUS mvEthMacAddrGet(int portNo, unsigned char *pAddr) -+{ -+ unsigned int macH; -+ unsigned int macL; -+ -+ if(pAddr == NULL) -+ { -+ mvOsPrintf("mvEthMacAddrGet: NULL pointer.\n"); -+ return MV_BAD_PARAM; -+ } -+ -+ macH = MV_REG_READ(ETH_MAC_ADDR_HIGH_REG(portNo)); -+ macL = MV_REG_READ(ETH_MAC_ADDR_LOW_REG(portNo)); -+ pAddr[0] = (macH >> 24) & 0xff; -+ pAddr[1] = (macH >> 16) & 0xff; -+ pAddr[2] = (macH >> 8) & 0xff; -+ pAddr[3] = macH & 0xff; -+ pAddr[4] = (macL >> 8) & 0xff; -+ pAddr[5] = macL & 0xff; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthMcastCrc8Get - Calculate CRC8 of MAC address. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* MV_U8* pAddr - Address to calculate CRC-8 -+* -+* RETURN: MV_U8 - CRC-8 of this MAC address -+* -+*******************************************************************************/ -+MV_U8 mvEthMcastCrc8Get(MV_U8* pAddr) -+{ -+ unsigned int macH; -+ unsigned int macL; -+ int macArray[48]; -+ int crc[8]; -+ int i; -+ unsigned char crcResult = 0; -+ -+ /* Calculate CRC-8 out of the given address */ -+ macH = (pAddr[0] << 8) | (pAddr[1]); -+ macL = (pAddr[2] << 24)| (pAddr[3] << 16) | -+ (pAddr[4] << 8) | (pAddr[5] << 0); -+ -+ for(i=0; i<32; i++) -+ macArray[i] = (macL >> i) & 0x1; -+ -+ for(i=32; i<48; i++) -+ macArray[i] = (macH >> (i - 32)) & 0x1; -+ -+ crc[0] = macArray[45] ^ macArray[43] ^ macArray[40] ^ macArray[39] ^ -+ macArray[35] ^ macArray[34] ^ macArray[31] ^ macArray[30] ^ -+ macArray[28] ^ macArray[23] ^ macArray[21] ^ macArray[19] ^ -+ macArray[18] ^ macArray[16] ^ macArray[14] ^ macArray[12] ^ -+ macArray[8] ^ macArray[7] ^ macArray[6] ^ macArray[0]; -+ -+ crc[1] = macArray[46] ^ macArray[45] ^ macArray[44] ^ macArray[43] ^ -+ macArray[41] ^ macArray[39] ^ macArray[36] ^ macArray[34] ^ -+ macArray[32] ^ macArray[30] ^ macArray[29] ^ macArray[28] ^ -+ macArray[24] ^ macArray[23] ^ macArray[22] ^ macArray[21] ^ -+ macArray[20] ^ macArray[18] ^ macArray[17] ^ macArray[16] ^ -+ macArray[15] ^ macArray[14] ^ macArray[13] ^ macArray[12] ^ -+ macArray[9] ^ macArray[6] ^ macArray[1] ^ macArray[0]; -+ -+ crc[2] = macArray[47] ^ macArray[46] ^ macArray[44] ^ macArray[43] ^ -+ macArray[42] ^ macArray[39] ^ macArray[37] ^ macArray[34] ^ -+ macArray[33] ^ macArray[29] ^ macArray[28] ^ macArray[25] ^ -+ macArray[24] ^ macArray[22] ^ macArray[17] ^ macArray[15] ^ -+ macArray[13] ^ macArray[12] ^ macArray[10] ^ macArray[8] ^ -+ macArray[6] ^ macArray[2] ^ macArray[1] ^ macArray[0]; -+ -+ crc[3] = macArray[47] ^ macArray[45] ^ macArray[44] ^ macArray[43] ^ -+ macArray[40] ^ macArray[38] ^ macArray[35] ^ macArray[34] ^ -+ macArray[30] ^ macArray[29] ^ macArray[26] ^ macArray[25] ^ -+ macArray[23] ^ macArray[18] ^ macArray[16] ^ macArray[14] ^ -+ macArray[13] ^ macArray[11] ^ macArray[9] ^ macArray[7] ^ -+ macArray[3] ^ macArray[2] ^ macArray[1]; -+ -+ crc[4] = macArray[46] ^ macArray[45] ^ macArray[44] ^ macArray[41] ^ -+ macArray[39] ^ macArray[36] ^ macArray[35] ^ macArray[31] ^ -+ macArray[30] ^ macArray[27] ^ macArray[26] ^ macArray[24] ^ -+ macArray[19] ^ macArray[17] ^ macArray[15] ^ macArray[14] ^ -+ macArray[12] ^ macArray[10] ^ macArray[8] ^ macArray[4] ^ -+ macArray[3] ^ macArray[2]; -+ -+ crc[5] = macArray[47] ^ macArray[46] ^ macArray[45] ^ macArray[42] ^ -+ macArray[40] ^ macArray[37] ^ macArray[36] ^ macArray[32] ^ -+ macArray[31] ^ macArray[28] ^ macArray[27] ^ macArray[25] ^ -+ macArray[20] ^ macArray[18] ^ macArray[16] ^ macArray[15] ^ -+ macArray[13] ^ macArray[11] ^ macArray[9] ^ macArray[5] ^ -+ macArray[4] ^ macArray[3]; -+ -+ crc[6] = macArray[47] ^ macArray[46] ^ macArray[43] ^ macArray[41] ^ -+ macArray[38] ^ macArray[37] ^ macArray[33] ^ macArray[32] ^ -+ macArray[29] ^ macArray[28] ^ macArray[26] ^ macArray[21] ^ -+ macArray[19] ^ macArray[17] ^ macArray[16] ^ macArray[14] ^ -+ macArray[12] ^ macArray[10] ^ macArray[6] ^ macArray[5] ^ -+ macArray[4]; -+ -+ crc[7] = macArray[47] ^ macArray[44] ^ macArray[42] ^ macArray[39] ^ -+ macArray[38] ^ macArray[34] ^ macArray[33] ^ macArray[30] ^ -+ macArray[29] ^ macArray[27] ^ macArray[22] ^ macArray[20] ^ -+ macArray[18] ^ macArray[17] ^ macArray[15] ^ macArray[13] ^ -+ macArray[11] ^ macArray[7] ^ macArray[6] ^ macArray[5]; -+ -+ for(i=0; i<8; i++) -+ crcResult = crcResult | (crc[i] << i); -+ -+ return crcResult; -+} -+/******************************************************************************* -+* mvEthMcastAddrSet - Multicast address settings. -+* -+* DESCRIPTION: -+* This API controls the MV device MAC multicast support. -+* The MV device supports multicast using two tables: -+* 1) Special Multicast Table for MAC addresses of the form -+* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). -+* The MAC DA[7:0] bits are used as a pointer to the Special Multicast -+* Table entries in the DA-Filter table. -+* In this case, the function calls ethPortSmcAddr() routine to set the -+* Special Multicast Table. -+* 2) Other Multicast Table for multicast of another type. A CRC-8bit -+* is used as an index to the Other Multicast Table entries in the -+* DA-Filter table. -+* In this case, the function calculates the CRC-8bit value and calls -+* ethPortOmcAddr() routine to set the Other Multicast Table. -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet port handler. -+* MV_U8* pAddr - Address to be set -+* int queue - RX queue to capture all packets with this -+* Multicast MAC address. -+* -1 means delete this Multicast address. -+* -+* RETURN: MV_STATUS -+* MV_TRUE - Success, Other - Failure -+* -+*******************************************************************************/ -+MV_STATUS mvEthMcastAddrSet(void* pPortHndl, MV_U8 *pAddr, int queue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ unsigned char crcResult = 0; -+ -+ if(queue >= MV_ETH_RX_Q_NUM) -+ { -+ mvOsPrintf("ethPort %d: RX queue #%d is out of range\n", -+ pPortCtrl->portNo, queue); -+ return MV_BAD_PARAM; -+ } -+ -+ if((pAddr[0] == 0x01) && -+ (pAddr[1] == 0x00) && -+ (pAddr[2] == 0x5E) && -+ (pAddr[3] == 0x00) && -+ (pAddr[4] == 0x00)) -+ { -+ ethSetSpecialMcastAddr(pPortCtrl->portNo, pAddr[5], queue); -+ } -+ else -+ { -+ crcResult = mvEthMcastCrc8Get(pAddr); -+ -+ /* Check Add counter for this CRC value */ -+ if(queue == -1) -+ { -+ if(pPortCtrl->mcastCount[crcResult] == 0) -+ { -+ mvOsPrintf("ethPort #%d: No valid Mcast for crc8=0x%02x\n", -+ pPortCtrl->portNo, (unsigned)crcResult); -+ return MV_NO_SUCH; -+ } -+ -+ pPortCtrl->mcastCount[crcResult]--; -+ if(pPortCtrl->mcastCount[crcResult] != 0) -+ { -+ mvOsPrintf("ethPort #%d: After delete there are %d valid Mcast for crc8=0x%02x\n", -+ pPortCtrl->portNo, pPortCtrl->mcastCount[crcResult], -+ (unsigned)crcResult); -+ return MV_NO_CHANGE; -+ } -+ } -+ else -+ { -+ pPortCtrl->mcastCount[crcResult]++; -+ if(pPortCtrl->mcastCount[crcResult] > 1) -+ { -+ mvOsPrintf("ethPort #%d: Valid Mcast for crc8=0x%02x already exists\n", -+ pPortCtrl->portNo, (unsigned)crcResult); -+ return MV_NO_CHANGE; -+ } -+ } -+ ethSetOtherMcastAddr(pPortCtrl->portNo, crcResult, queue); -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* ethSetUcastTable - Unicast address settings. -+* -+* DESCRIPTION: -+* Set all entries in the Unicast MAC Table queue==-1 means reject all -+* INPUT: -+* -+* RETURN: -+* -+*******************************************************************************/ -+static void ethSetUcastTable(int portNo, int queue) -+{ -+ int offset; -+ MV_U32 regValue; -+ -+ if(queue == -1) -+ { -+ regValue = 0; -+ } -+ else -+ { -+ regValue = (((0x01 | (queue<<1)) << 0) | -+ ((0x01 | (queue<<1)) << 8) | -+ ((0x01 | (queue<<1)) << 16) | -+ ((0x01 | (queue<<1)) << 24)); -+ } -+ -+ for (offset=0; offset<=0xC; offset+=4) -+ MV_REG_WRITE((ETH_DA_FILTER_UCAST_BASE(portNo) + offset), regValue); -+} -+ -+/******************************************************************************* -+* mvEthSetSpecialMcastTable - Special Multicast address settings. -+* -+* DESCRIPTION: -+* Set all entries to the Special Multicast MAC Table. queue==-1 means reject all -+* INPUT: -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_VOID mvEthSetSpecialMcastTable(int portNo, int queue) -+{ -+ int offset; -+ MV_U32 regValue; -+ -+ if(queue == -1) -+ { -+ regValue = 0; -+ } -+ else -+ { -+ regValue = (((0x01 | (queue<<1)) << 0) | -+ ((0x01 | (queue<<1)) << 8) | -+ ((0x01 | (queue<<1)) << 16) | -+ ((0x01 | (queue<<1)) << 24)); -+ } -+ -+ for (offset=0; offset<=0xFC; offset+=4) -+ { -+ MV_REG_WRITE((ETH_DA_FILTER_SPEC_MCAST_BASE(portNo) + -+ offset), regValue); -+ } -+} -+ -+/******************************************************************************* -+* mvEthSetOtherMcastTable - Other Multicast address settings. -+* -+* DESCRIPTION: -+* Set all entries to the Other Multicast MAC Table. queue==-1 means reject all -+* INPUT: -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_VOID mvEthSetOtherMcastTable(int portNo, int queue) -+{ -+ int offset; -+ MV_U32 regValue; -+ -+ if(queue == -1) -+ { -+ regValue = 0; -+ } -+ else -+ { -+ regValue = (((0x01 | (queue<<1)) << 0) | -+ ((0x01 | (queue<<1)) << 8) | -+ ((0x01 | (queue<<1)) << 16) | -+ ((0x01 | (queue<<1)) << 24)); -+ } -+ -+ for (offset=0; offset<=0xFC; offset+=4) -+ { -+ MV_REG_WRITE((ETH_DA_FILTER_OTH_MCAST_BASE(portNo) + -+ offset), regValue); -+ } -+} -+ -+/******************************************************************************* -+* ethSetUcastAddr - This function Set the port unicast address table -+* -+* DESCRIPTION: -+* This function locates the proper entry in the Unicast table for the -+* specified MAC nibble and sets its properties according to function -+* parameters. -+* -+* INPUT: -+* int ethPortNum - Port number. -+* MV_U8 lastNibble - Unicast MAC Address last nibble. -+* int queue - Rx queue number for this MAC address. -+* value "-1" means remove address -+* -+* OUTPUT: -+* This function add/removes MAC addresses from the port unicast address -+* table. -+* -+* RETURN: -+* MV_TRUE is output succeeded. -+* MV_FALSE if option parameter is invalid. -+* -+*******************************************************************************/ -+static MV_BOOL ethSetUcastAddr(int portNo, MV_U8 lastNibble, int queue) -+{ -+ unsigned int unicastReg; -+ unsigned int tblOffset; -+ unsigned int regOffset; -+ -+ /* Locate the Unicast table entry */ -+ lastNibble = (0xf & lastNibble); -+ tblOffset = (lastNibble / 4) * 4; /* Register offset from unicast table base*/ -+ regOffset = lastNibble % 4; /* Entry offset within the above register */ -+ -+ -+ unicastReg = MV_REG_READ( (ETH_DA_FILTER_UCAST_BASE(portNo) + -+ tblOffset)); -+ -+ -+ if(queue == -1) -+ { -+ /* Clear accepts frame bit at specified unicast DA table entry */ -+ unicastReg &= ~(0xFF << (8*regOffset)); -+ } -+ else -+ { -+ unicastReg &= ~(0xFF << (8*regOffset)); -+ unicastReg |= ((0x01 | (queue<<1)) << (8*regOffset)); -+ } -+ MV_REG_WRITE( (ETH_DA_FILTER_UCAST_BASE(portNo) + tblOffset), -+ unicastReg); -+ -+ return MV_TRUE; -+} -+ -+/******************************************************************************* -+* ethSetSpecialMcastAddr - Special Multicast address settings. -+* -+* DESCRIPTION: -+* This routine controls the MV device special MAC multicast support. -+* The Special Multicast Table for MAC addresses supports MAC of the form -+* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). -+* The MAC DA[7:0] bits are used as a pointer to the Special Multicast -+* Table entries in the DA-Filter table. -+* This function set the Special Multicast Table appropriate entry -+* according to the argument given. -+* -+* INPUT: -+* int ethPortNum Port number. -+* unsigned char mcByte Multicast addr last byte (MAC DA[7:0] bits). -+* int queue Rx queue number for this MAC address. -+* int option 0 = Add, 1 = remove address. -+* -+* OUTPUT: -+* See description. -+* -+* RETURN: -+* MV_TRUE is output succeeded. -+* MV_FALSE if option parameter is invalid. -+* -+*******************************************************************************/ -+static MV_BOOL ethSetSpecialMcastAddr(int ethPortNum, MV_U8 lastByte, int queue) -+{ -+ unsigned int smcTableReg; -+ unsigned int tblOffset; -+ unsigned int regOffset; -+ -+ /* Locate the SMC table entry */ -+ tblOffset = (lastByte / 4); /* Register offset from SMC table base */ -+ regOffset = lastByte % 4; /* Entry offset within the above register */ -+ -+ smcTableReg = MV_REG_READ((ETH_DA_FILTER_SPEC_MCAST_BASE(ethPortNum) + tblOffset*4)); -+ -+ if(queue == -1) -+ { -+ /* Clear accepts frame bit at specified Special DA table entry */ -+ smcTableReg &= ~(0xFF << (8 * regOffset)); -+ } -+ else -+ { -+ smcTableReg &= ~(0xFF << (8 * regOffset)); -+ smcTableReg |= ((0x01 | (queue<<1)) << (8 * regOffset)); -+ } -+ MV_REG_WRITE((ETH_DA_FILTER_SPEC_MCAST_BASE(ethPortNum) + -+ tblOffset*4), smcTableReg); -+ -+ return MV_TRUE; -+} -+ -+/******************************************************************************* -+* ethSetOtherMcastAddr - Multicast address settings. -+* -+* DESCRIPTION: -+* This routine controls the MV device Other MAC multicast support. -+* The Other Multicast Table is used for multicast of another type. -+* A CRC-8bit is used as an index to the Other Multicast Table entries -+* in the DA-Filter table. -+* The function gets the CRC-8bit value from the calling routine and -+* set the Other Multicast Table appropriate entry according to the -+* CRC-8 argument given. -+* -+* INPUT: -+* int ethPortNum Port number. -+* MV_U8 crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1). -+* int queue Rx queue number for this MAC address. -+* -+* OUTPUT: -+* See description. -+* -+* RETURN: -+* MV_TRUE is output succeeded. -+* MV_FALSE if option parameter is invalid. -+* -+*******************************************************************************/ -+static MV_BOOL ethSetOtherMcastAddr(int ethPortNum, MV_U8 crc8, int queue) -+{ -+ unsigned int omcTableReg; -+ unsigned int tblOffset; -+ unsigned int regOffset; -+ -+ /* Locate the OMC table entry */ -+ tblOffset = (crc8 / 4) * 4; /* Register offset from OMC table base */ -+ regOffset = crc8 % 4; /* Entry offset within the above register */ -+ -+ omcTableReg = MV_REG_READ( -+ (ETH_DA_FILTER_OTH_MCAST_BASE(ethPortNum) + tblOffset)); -+ -+ if(queue == -1) -+ { -+ /* Clear accepts frame bit at specified Other DA table entry */ -+ omcTableReg &= ~(0xFF << (8 * regOffset)); -+ } -+ else -+ { -+ omcTableReg &= ~(0xFF << (8 * regOffset)); -+ omcTableReg |= ((0x01 | (queue<<1)) << (8 * regOffset)); -+ } -+ -+ MV_REG_WRITE((ETH_DA_FILTER_OTH_MCAST_BASE(ethPortNum) + tblOffset), -+ omcTableReg); -+ -+ return MV_TRUE; -+} -+ -+ -+/******************************************************************************/ -+/* MIB Counters functions */ -+/******************************************************************************/ -+ -+ -+/******************************************************************************* -+* mvEthMibCounterRead - Read a MIB counter -+* -+* DESCRIPTION: -+* This function reads a MIB counter of a specific ethernet port. -+* NOTE - Read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW or -+* ETH_MIB_GOOD_OCTETS_SENT_LOW counters will return 64 bits value, -+* so pHigh32 pointer should not be NULL in this case. -+* -+* INPUT: -+* int ethPortNum - Ethernet Port number. -+* unsigned int mibOffset - MIB counter offset. -+* -+* OUTPUT: -+* MV_U32* pHigh32 - pointer to place where 32 most significant bits -+* of the counter will be stored. -+* -+* RETURN: -+* 32 low sgnificant bits of MIB counter value. -+* -+*******************************************************************************/ -+MV_U32 mvEthMibCounterRead(void* pPortHandle, unsigned int mibOffset, -+ MV_U32* pHigh32) -+{ -+ int portNo; -+ MV_U32 valLow32, valHigh32; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ -+ portNo = pPortCtrl->portNo; -+ -+ valLow32 = MV_REG_READ(ETH_MIB_COUNTERS_BASE(portNo) + mibOffset); -+ -+ /* Implement FEr ETH. Erroneous Value when Reading the Upper 32-bits */ -+ /* of a 64-bit MIB Counter. */ -+ if( (mibOffset == ETH_MIB_GOOD_OCTETS_RECEIVED_LOW) || -+ (mibOffset == ETH_MIB_GOOD_OCTETS_SENT_LOW) ) -+ { -+ valHigh32 = MV_REG_READ(ETH_MIB_COUNTERS_BASE(portNo) + mibOffset + 4); -+ if(pHigh32 != NULL) -+ *pHigh32 = valHigh32; -+ } -+ return valLow32; -+} -+ -+/******************************************************************************* -+* mvEthMibCountersClear - Clear all MIB counters -+* -+* DESCRIPTION: -+* This function clears all MIB counters -+* -+* INPUT: -+* int ethPortNum - Ethernet Port number. -+* -+* -+* RETURN: void -+* -+*******************************************************************************/ -+void mvEthMibCountersClear(void* pPortHandle) -+{ -+ int i, portNo; -+ unsigned int dummy; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ -+ portNo = pPortCtrl->portNo; -+ -+ /* Perform dummy reads from MIB counters */ -+ for(i=ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i 0xFF) -+ { -+ mvOsPrintf("eth_%d: tos=0x%x is out of range\n", pPortCtrl->portNo, tos); -+ return -1; -+ } -+ regIdx = mvOsDivide(tos>>2, 10); -+ regOffs = mvOsReminder(tos>>2, 10); -+ -+ regValue = MV_REG_READ(ETH_DIFF_SERV_PRIO_REG(pPortCtrl->portNo, regIdx) ); -+ rxq = (regValue >> (regOffs*3)); -+ rxq &= 0x7; -+ -+ return rxq; -+} -+ -+/******************************************************************************* -+* mvEthTosToRxqSet - Map packets with special TOS value to special RX queue -+* -+* DESCRIPTION: -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* int tos - TOS value in the IP header of the packet -+* int rxq - RX Queue for packets with the configured TOS value -+* Negative value (-1) means no special processing for these packets, -+* so they will be processed as regular packets. -+* -+* RETURN: MV_STATUS -+*******************************************************************************/ -+MV_STATUS mvEthTosToRxqSet(void* pPortHandle, int tos, int rxq) -+{ -+ MV_U32 regValue; -+ int regIdx, regOffs; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ -+ if( (rxq < 0) || (rxq >= MV_ETH_RX_Q_NUM) ) -+ { -+ mvOsPrintf("eth_%d: RX queue #%d is out of range\n", pPortCtrl->portNo, rxq); -+ return MV_BAD_PARAM; -+ } -+ if(tos > 0xFF) -+ { -+ mvOsPrintf("eth_%d: tos=0x%x is out of range\n", pPortCtrl->portNo, tos); -+ return MV_BAD_PARAM; -+ } -+ regIdx = mvOsDivide(tos>>2, 10); -+ regOffs = mvOsReminder(tos>>2, 10); -+ -+ regValue = MV_REG_READ(ETH_DIFF_SERV_PRIO_REG(pPortCtrl->portNo, regIdx) ); -+ regValue &= ~(0x7 << (regOffs*3)); -+ regValue |= (rxq << (regOffs*3)); -+ -+ MV_REG_WRITE(ETH_DIFF_SERV_PRIO_REG(pPortCtrl->portNo, regIdx), regValue); -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthVlanPrioRxQueue - Configure RX queue to capture VLAN tagged packets with -+* special priority bits [0-2] -+* -+* DESCRIPTION: -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* int bpduQueue - Special queue to capture VLAN tagged packets with special -+* priority. -+* Negative value (-1) means no special processing for these packets, -+* so they will be processed as regular packets. -+* -+* RETURN: MV_STATUS -+* MV_OK - Success -+* MV_FAIL - Failed. -+* -+*******************************************************************************/ -+MV_STATUS mvEthVlanPrioRxQueue(void* pPortHandle, int vlanPrio, int vlanPrioQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ MV_U32 vlanPrioReg; -+ -+ if(vlanPrioQueue >= MV_ETH_RX_Q_NUM) -+ { -+ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", vlanPrioQueue); -+ return MV_BAD_PARAM; -+ } -+ if(vlanPrio >= 8) -+ { -+ mvOsPrintf("ethDrv: vlanPrio=%d is out of range\n", vlanPrio); -+ return MV_BAD_PARAM; -+ } -+ -+ vlanPrioReg = MV_REG_READ(ETH_VLAN_TAG_TO_PRIO_REG(pPortCtrl->portNo)); -+ vlanPrioReg &= ~(0x7 << (vlanPrio*3)); -+ vlanPrioReg |= (vlanPrioQueue << (vlanPrio*3)); -+ MV_REG_WRITE(ETH_VLAN_TAG_TO_PRIO_REG(pPortCtrl->portNo), vlanPrioReg); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvEthBpduRxQueue - Configure RX queue to capture BPDU packets. -+* -+* DESCRIPTION: -+* This function defines processing of BPDU packets. -+* BPDU packets can be accepted and captured to one of RX queues -+* or can be processing as regular Multicast packets. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* int bpduQueue - Special queue to capture BPDU packets (DA is equal to -+* 01-80-C2-00-00-00 through 01-80-C2-00-00-FF, -+* except for the Flow-Control Pause packets). -+* Negative value (-1) means no special processing for BPDU, -+* packets so they will be processed as regular Multicast packets. -+* -+* RETURN: MV_STATUS -+* MV_OK - Success -+* MV_FAIL - Failed. -+* -+*******************************************************************************/ -+MV_STATUS mvEthBpduRxQueue(void* pPortHandle, int bpduQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ MV_U32 portCfgReg; -+ MV_U32 portCfgExtReg; -+ -+ if(bpduQueue >= MV_ETH_RX_Q_NUM) -+ { -+ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", bpduQueue); -+ return MV_BAD_PARAM; -+ } -+ -+ portCfgExtReg = MV_REG_READ(ETH_PORT_CONFIG_EXTEND_REG(pPortCtrl->portNo)); -+ -+ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); -+ if(bpduQueue >= 0) -+ { -+ pPortCtrl->portConfig.rxBpduQ = bpduQueue; -+ -+ portCfgReg &= ~ETH_DEF_RX_BPDU_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_BPDU_QUEUE_MASK(pPortCtrl->portConfig.rxBpduQ); -+ -+ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); -+ -+ portCfgExtReg |= ETH_CAPTURE_SPAN_BPDU_ENABLE_MASK; -+ } -+ else -+ { -+ pPortCtrl->portConfig.rxBpduQ = -1; -+ /* no special processing for BPDU packets */ -+ portCfgExtReg &= (~ETH_CAPTURE_SPAN_BPDU_ENABLE_MASK); -+ } -+ -+ MV_REG_WRITE(ETH_PORT_CONFIG_EXTEND_REG(pPortCtrl->portNo), portCfgExtReg); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvEthArpRxQueue - Configure RX queue to capture ARP packets. -+* -+* DESCRIPTION: -+* This function defines processing of ARP (type=0x0806) packets. -+* ARP packets can be accepted and captured to one of RX queues -+* or can be processed as other Broadcast packets. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* int arpQueue - Special queue to capture ARP packets (type=0x806). -+* Negative value (-1) means discard ARP packets -+* -+* RETURN: MV_STATUS -+* MV_OK - Success -+* MV_FAIL - Failed. -+* -+*******************************************************************************/ -+MV_STATUS mvEthArpRxQueue(void* pPortHandle, int arpQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ MV_U32 portCfgReg; -+ -+ if(arpQueue >= MV_ETH_RX_Q_NUM) -+ { -+ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", arpQueue); -+ return MV_BAD_PARAM; -+ } -+ -+ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); -+ -+ if(arpQueue >= 0) -+ { -+ pPortCtrl->portConfig.rxArpQ = arpQueue; -+ portCfgReg &= ~ETH_DEF_RX_ARP_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_ARP_QUEUE_MASK(pPortCtrl->portConfig.rxArpQ); -+ -+ portCfgReg &= (~ETH_REJECT_ARP_BCAST_MASK); -+ } -+ else -+ { -+ pPortCtrl->portConfig.rxArpQ = -1; -+ portCfgReg |= ETH_REJECT_ARP_BCAST_MASK; -+ } -+ -+ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvEthTcpRxQueue - Configure RX queue to capture TCP packets. -+* -+* DESCRIPTION: -+* This function defines processing of TCP packets. -+* TCP packets can be accepted and captured to one of RX queues -+* or can be processed as regular Unicast packets. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* int tcpQueue - Special queue to capture TCP packets. Value "-1" -+* means no special processing for TCP packets, -+* so they will be processed as regular -+* -+* RETURN: MV_STATUS -+* MV_OK - Success -+* MV_FAIL - Failed. -+* -+*******************************************************************************/ -+MV_STATUS mvEthTcpRxQueue(void* pPortHandle, int tcpQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ MV_U32 portCfgReg; -+ -+ if(tcpQueue >= MV_ETH_RX_Q_NUM) -+ { -+ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", tcpQueue); -+ return MV_BAD_PARAM; -+ } -+ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); -+ -+ if(tcpQueue >= 0) -+ { -+ pPortCtrl->portConfig.rxTcpQ = tcpQueue; -+ portCfgReg &= ~ETH_DEF_RX_TCP_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_TCP_QUEUE_MASK(pPortCtrl->portConfig.rxTcpQ); -+ -+ portCfgReg |= ETH_CAPTURE_TCP_FRAMES_ENABLE_MASK; -+ } -+ else -+ { -+ pPortCtrl->portConfig.rxTcpQ = -1; -+ portCfgReg &= (~ETH_CAPTURE_TCP_FRAMES_ENABLE_MASK); -+ } -+ -+ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvEthUdpRxQueue - Configure RX queue to capture UDP packets. -+* -+* DESCRIPTION: -+* This function defines processing of UDP packets. -+* TCP packets can be accepted and captured to one of RX queues -+* or can be processed as regular Unicast packets. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* int udpQueue - Special queue to capture UDP packets. Value "-1" -+* means no special processing for UDP packets, -+* so they will be processed as regular -+* -+* RETURN: MV_STATUS -+* MV_OK - Success -+* MV_FAIL - Failed. -+* -+*******************************************************************************/ -+MV_STATUS mvEthUdpRxQueue(void* pPortHandle, int udpQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ MV_U32 portCfgReg; -+ -+ if(udpQueue >= MV_ETH_RX_Q_NUM) -+ { -+ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", udpQueue); -+ return MV_BAD_PARAM; -+ } -+ -+ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); -+ -+ if(udpQueue >= 0) -+ { -+ pPortCtrl->portConfig.rxUdpQ = udpQueue; -+ portCfgReg &= ~ETH_DEF_RX_UDP_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_UDP_QUEUE_MASK(pPortCtrl->portConfig.rxUdpQ); -+ -+ portCfgReg |= ETH_CAPTURE_UDP_FRAMES_ENABLE_MASK; -+ } -+ else -+ { -+ pPortCtrl->portConfig.rxUdpQ = -1; -+ portCfgReg &= ~ETH_CAPTURE_UDP_FRAMES_ENABLE_MASK; -+ } -+ -+ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************/ -+/* Speed, Duplex, FlowControl routines */ -+/******************************************************************************/ -+ -+/******************************************************************************* -+* mvEthSpeedDuplexSet - Set Speed and Duplex of the port. -+* -+* DESCRIPTION: -+* This function configure the port to work with desirable Duplex and Speed. -+* Changing of these parameters are allowed only when port is disabled. -+* This function disable the port if was enabled, change duplex and speed -+* and, enable the port back if needed. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* ETH_PORT_SPEED speed - Speed of the port. -+* ETH_PORT_SPEED duplex - Duplex of the port. -+* -+* RETURN: MV_STATUS -+* MV_OK - Success -+* MV_OUT_OF_RANGE - Failed. Port is out of valid range -+* MV_NOT_FOUND - Failed. Port is not initialized. -+* MV_BAD_PARAM - Input parameters (speed/duplex) in conflict. -+* MV_BAD_VALUE - Value of one of input parameters (speed, duplex) -+* is not valid -+* -+*******************************************************************************/ -+MV_STATUS mvEthSpeedDuplexSet(void* pPortHandle, MV_ETH_PORT_SPEED speed, -+ MV_ETH_PORT_DUPLEX duplex) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ int port = pPortCtrl->portNo; -+ MV_U32 portSerialCtrlReg; -+ -+ if( (port < 0) || (port >= (int)mvCtrlEthMaxPortGet()) ) -+ return MV_OUT_OF_RANGE; -+ -+ pPortCtrl = ethPortCtrl[port]; -+ if(pPortCtrl == NULL) -+ return MV_NOT_FOUND; -+ -+ /* Check validity */ -+ if( (speed == MV_ETH_SPEED_1000) && (duplex == MV_ETH_DUPLEX_HALF) ) -+ return MV_BAD_PARAM; -+ -+ portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port)); -+ /* Set Speed */ -+ switch(speed) -+ { -+ case MV_ETH_SPEED_AN: -+ portSerialCtrlReg &= ~ETH_DISABLE_SPEED_AUTO_NEG_MASK; -+ break; -+ -+ case MV_ETH_SPEED_10: -+ portSerialCtrlReg |= ETH_DISABLE_SPEED_AUTO_NEG_MASK; -+ portSerialCtrlReg &= ~ETH_SET_GMII_SPEED_1000_MASK; -+ portSerialCtrlReg &= ~ETH_SET_MII_SPEED_100_MASK; -+ break; -+ -+ case MV_ETH_SPEED_100: -+ portSerialCtrlReg |= ETH_DISABLE_SPEED_AUTO_NEG_MASK; -+ portSerialCtrlReg &= ~ETH_SET_GMII_SPEED_1000_MASK; -+ portSerialCtrlReg |= ETH_SET_MII_SPEED_100_MASK; -+ break; -+ -+ case MV_ETH_SPEED_1000: -+ portSerialCtrlReg |= ETH_DISABLE_SPEED_AUTO_NEG_MASK; -+ portSerialCtrlReg |= ETH_SET_GMII_SPEED_1000_MASK; -+ break; -+ -+ default: -+ mvOsPrintf("ethDrv: Unexpected Speed value %d\n", speed); -+ return MV_BAD_VALUE; -+ } -+ /* Set duplex */ -+ switch(duplex) -+ { -+ case MV_ETH_DUPLEX_AN: -+ portSerialCtrlReg &= ~ETH_DISABLE_DUPLEX_AUTO_NEG_MASK; -+ break; -+ -+ case MV_ETH_DUPLEX_HALF: -+ portSerialCtrlReg |= ETH_DISABLE_DUPLEX_AUTO_NEG_MASK; -+ portSerialCtrlReg &= ~ETH_SET_FULL_DUPLEX_MASK; -+ break; -+ -+ case MV_ETH_DUPLEX_FULL: -+ portSerialCtrlReg |= ETH_DISABLE_DUPLEX_AUTO_NEG_MASK; -+ portSerialCtrlReg |= ETH_SET_FULL_DUPLEX_MASK; -+ break; -+ -+ default: -+ mvOsPrintf("ethDrv: Unexpected Duplex value %d\n", duplex); -+ return MV_BAD_VALUE; -+ } -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(port), portSerialCtrlReg); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthFlowCtrlSet - Set Flow Control of the port. -+* -+* DESCRIPTION: -+* This function configure the port to work with desirable Duplex and -+* Speed. Changing of these parameters are allowed only when port is -+* disabled. This function disable the port if was enabled, change -+* duplex and speed and, enable the port back if needed. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* MV_ETH_PORT_FC flowControl - Flow control of the port. -+* -+* RETURN: MV_STATUS -+* MV_OK - Success -+* MV_OUT_OF_RANGE - Failed. Port is out of valid range -+* MV_NOT_FOUND - Failed. Port is not initialized. -+* MV_BAD_VALUE - Value flowControl parameters is not valid -+* -+*******************************************************************************/ -+MV_STATUS mvEthFlowCtrlSet(void* pPortHandle, MV_ETH_PORT_FC flowControl) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ int port = pPortCtrl->portNo; -+ MV_U32 portSerialCtrlReg; -+ -+ if( (port < 0) || (port >= (int)mvCtrlEthMaxPortGet() ) ) -+ return MV_OUT_OF_RANGE; -+ -+ pPortCtrl = ethPortCtrl[port]; -+ if(pPortCtrl == NULL) -+ return MV_NOT_FOUND; -+ -+ portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port)); -+ switch(flowControl) -+ { -+ case MV_ETH_FC_AN_ADV_DIS: -+ portSerialCtrlReg &= ~ETH_DISABLE_FC_AUTO_NEG_MASK; -+ portSerialCtrlReg &= ~ETH_ADVERTISE_SYM_FC_MASK; -+ break; -+ -+ case MV_ETH_FC_AN_ADV_SYM: -+ portSerialCtrlReg &= ~ETH_DISABLE_FC_AUTO_NEG_MASK; -+ portSerialCtrlReg |= ETH_ADVERTISE_SYM_FC_MASK; -+ break; -+ -+ case MV_ETH_FC_DISABLE: -+ portSerialCtrlReg |= ETH_DISABLE_FC_AUTO_NEG_MASK; -+ portSerialCtrlReg &= ~ETH_SET_FLOW_CTRL_MASK; -+ break; -+ -+ case MV_ETH_FC_ENABLE: -+ portSerialCtrlReg |= ETH_DISABLE_FC_AUTO_NEG_MASK; -+ portSerialCtrlReg |= ETH_SET_FLOW_CTRL_MASK; -+ break; -+ -+ default: -+ mvOsPrintf("ethDrv: Unexpected FlowControl value %d\n", flowControl); -+ return MV_BAD_VALUE; -+ } -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(port), portSerialCtrlReg); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthHeaderModeSet - Set port header mode. -+* -+* DESCRIPTION: -+* This function configures the port to work in Marvell-Header mode. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* MV_ETH_HEADER_MODE headerMode - The header mode to set the port in. -+* -+* RETURN: MV_STATUS -+* MV_OK - Success -+* MV_NOT_SUPPORTED- Feature not supported. -+* MV_OUT_OF_RANGE - Failed. Port is out of valid range -+* MV_NOT_FOUND - Failed. Port is not initialized. -+* MV_BAD_VALUE - Value of headerMode or numRxQueue parameter is not valid. -+* -+*******************************************************************************/ -+MV_STATUS mvEthHeaderModeSet(void* pPortHandle, MV_ETH_HEADER_MODE headerMode) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ int port = pPortCtrl->portNo; -+ MV_U32 mvHeaderReg; -+ MV_U32 numRxQ = MV_ETH_RX_Q_NUM; -+ -+ if((port < 0) || (port >= mvCtrlEthMaxPortGet())) -+ return MV_OUT_OF_RANGE; -+ -+ pPortCtrl = ethPortCtrl[port]; -+ if(pPortCtrl == NULL) -+ return MV_NOT_FOUND; -+ -+ mvHeaderReg = MV_REG_READ(ETH_PORT_MARVELL_HEADER_REG(port)); -+ /* Disable header mode. */ -+ mvHeaderReg &= ~ETH_MVHDR_EN_MASK; -+ -+ if(headerMode != MV_ETH_DISABLE_HEADER_MODE) -+ { -+ /* Enable Header mode. */ -+ mvHeaderReg |= ETH_MVHDR_EN_MASK; -+ -+ /* Clear DA-Prefix & MHMask fields.*/ -+ mvHeaderReg &= ~(ETH_MVHDR_DAPREFIX_MASK | ETH_MVHDR_MHMASK_MASK); -+ -+ if(numRxQ > 1) -+ { -+ switch (headerMode) -+ { -+ case(MV_ETH_ENABLE_HEADER_MODE_PRI_2_1): -+ mvHeaderReg |= ETH_MVHDR_DAPREFIX_PRI_1_2; -+ break; -+ case(MV_ETH_ENABLE_HEADER_MODE_PRI_DBNUM): -+ mvHeaderReg |= ETH_MVHDR_DAPREFIX_DBNUM_PRI; -+ break; -+ case(MV_ETH_ENABLE_HEADER_MODE_PRI_SPID): -+ mvHeaderReg |= ETH_MVHDR_DAPREFIX_SPID_PRI; -+ break; -+ default: -+ break; -+ } -+ -+ switch (numRxQ) -+ { -+ case (4): -+ mvHeaderReg |= ETH_MVHDR_MHMASK_4_QUEUE; -+ break; -+ case (8): -+ mvHeaderReg |= ETH_MVHDR_MHMASK_8_QUEUE; -+ break; -+ default: -+ break; -+ } -+ } -+ } -+ -+ MV_REG_WRITE(ETH_PORT_MARVELL_HEADER_REG(port), mvHeaderReg); -+ -+ return MV_OK; -+} -+ -+#if (MV_ETH_VERSION >= 4) -+/******************************************************************************* -+* mvEthEjpModeSet - Enable / Disable EJP policy for TX. -+* -+* DESCRIPTION: -+* This function -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* MV_BOOL TRUE - enable EJP mode -+* FALSE - disable EJP mode -+* -+* OUTPUT: MV_STATUS -+* MV_OK - Success -+* Other - Failure -+* -+* RETURN: None. -+* -+*******************************************************************************/ -+MV_STATUS mvEthEjpModeSet(void* pPortHandle, int mode) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ int port = pPortCtrl->portNo; -+ -+ if((port < 0) || (port >= mvCtrlEthMaxPortGet())) -+ return MV_OUT_OF_RANGE; -+ -+ pPortCtrl = ethPortCtrl[port]; -+ if(pPortCtrl == NULL) -+ return MV_NOT_FOUND; -+ -+ pPortCtrl->portConfig.ejpMode = mode; -+ if(mode) -+ { -+ /* EJP enabled */ -+ MV_REG_WRITE(ETH_TXQ_CMD_1_REG(port), ETH_TX_EJP_ENABLE_MASK); -+ } -+ else -+ { -+ /* EJP disabled */ -+ MV_REG_WRITE(ETH_TXQ_CMD_1_REG(port), 0); -+ } -+ mvOsPrintf("eth_%d: EJP %s - ETH_TXQ_CMD_1_REG: 0x%x = 0x%08x\n", -+ port, mode ? "Enabled" : "Disabled", ETH_TXQ_CMD_1_REG(port), -+ MV_REG_READ(ETH_TXQ_CMD_1_REG(port))); -+ -+ return MV_OK; -+} -+#endif /* MV_ETH_VERSION >= 4 */ -+ -+/******************************************************************************* -+* mvEthStatusGet - Get major properties of the port . -+* -+* DESCRIPTION: -+* This function get major properties of the port (link, speed, duplex, -+* flowControl, etc) and return them using the single structure. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* -+* OUTPUT: -+* MV_ETH_PORT_STATUS* pStatus - Pointer to structure, were port status -+* will be placed. -+* -+* RETURN: None. -+* -+*******************************************************************************/ -+void mvEthStatusGet(void* pPortHandle, MV_ETH_PORT_STATUS* pStatus) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ int port = pPortCtrl->portNo; -+ -+ MV_U32 regValue; -+ -+ regValue = MV_REG_READ( ETH_PORT_STATUS_REG(port) ); -+ -+ if(regValue & ETH_GMII_SPEED_1000_MASK) -+ pStatus->speed = MV_ETH_SPEED_1000; -+ else if(regValue & ETH_MII_SPEED_100_MASK) -+ pStatus->speed = MV_ETH_SPEED_100; -+ else -+ pStatus->speed = MV_ETH_SPEED_10; -+ -+ if(regValue & ETH_LINK_UP_MASK) -+ pStatus->isLinkUp = MV_TRUE; -+ else -+ pStatus->isLinkUp = MV_FALSE; -+ -+ if(regValue & ETH_FULL_DUPLEX_MASK) -+ pStatus->duplex = MV_ETH_DUPLEX_FULL; -+ else -+ pStatus->duplex = MV_ETH_DUPLEX_HALF; -+ -+ -+ if(regValue & ETH_ENABLE_RCV_FLOW_CTRL_MASK) -+ pStatus->flowControl = MV_ETH_FC_ENABLE; -+ else -+ pStatus->flowControl = MV_ETH_FC_DISABLE; -+} -+ -+ -+/******************************************************************************/ -+/* PHY Control Functions */ -+/******************************************************************************/ -+ -+ -+/******************************************************************************* -+* mvEthPhyAddrSet - Set the ethernet port PHY address. -+* -+* DESCRIPTION: -+* This routine set the ethernet port PHY address according to given -+* parameter. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* int phyAddr - PHY address -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+void mvEthPhyAddrSet(void* pPortHandle, int phyAddr) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ int port = pPortCtrl->portNo; -+ unsigned int regData; -+ -+ regData = MV_REG_READ(ETH_PHY_ADDR_REG(port)); -+ -+ regData &= ~ETH_PHY_ADDR_MASK; -+ regData |= phyAddr; -+ -+ MV_REG_WRITE(ETH_PHY_ADDR_REG(port), regData); -+ -+ return; -+} -+ -+/******************************************************************************* -+* mvEthPhyAddrGet - Get the ethernet port PHY address. -+* -+* DESCRIPTION: -+* This routine returns the given ethernet port PHY address. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* -+* -+* RETURN: int - PHY address. -+* -+*******************************************************************************/ -+int mvEthPhyAddrGet(void* pPortHandle) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ int port = pPortCtrl->portNo; -+ unsigned int regData; -+ -+ regData = MV_REG_READ(ETH_PHY_ADDR_REG(port)); -+ -+ return ((regData >> (5 * port)) & 0x1f); -+} -+ -+/******************************************************************************/ -+/* Descriptor handling Functions */ -+/******************************************************************************/ -+ -+/******************************************************************************* -+* etherInitRxDescRing - Curve a Rx chain desc list and buffer in memory. -+* -+* DESCRIPTION: -+* This function prepares a Rx chained list of descriptors and packet -+* buffers in a form of a ring. The routine must be called after port -+* initialization routine and before port start routine. -+* The Ethernet SDMA engine uses CPU bus addresses to access the various -+* devices in the system (i.e. DRAM). This function uses the ethernet -+* struct 'virtual to physical' routine (set by the user) to set the ring -+* with physical addresses. -+* -+* INPUT: -+* ETH_QUEUE_CTRL *pEthPortCtrl Ethernet Port Control srtuct. -+* int rxQueue Number of Rx queue. -+* int rxDescNum Number of Rx descriptors -+* MV_U8* rxDescBaseAddr Rx descriptors memory area base addr. -+* -+* OUTPUT: -+* The routine updates the Ethernet port control struct with information -+* regarding the Rx descriptors and buffers. -+* -+* RETURN: None -+* -+*******************************************************************************/ -+static void ethInitRxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue) -+{ -+ ETH_RX_DESC *pRxDescBase, *pRxDesc, *pRxPrevDesc; -+ int ix, rxDescNum = pPortCtrl->rxQueueConfig[queue].descrNum; -+ ETH_QUEUE_CTRL *pQueueCtrl = &pPortCtrl->rxQueue[queue]; -+ -+ /* Make sure descriptor address is cache line size aligned */ -+ pRxDescBase = (ETH_RX_DESC*)MV_ALIGN_UP((MV_ULONG)pQueueCtrl->descBuf.bufVirtPtr, -+ CPU_D_CACHE_LINE_SIZE); -+ -+ pRxDesc = (ETH_RX_DESC*)pRxDescBase; -+ pRxPrevDesc = pRxDesc; -+ -+ /* initialize the Rx descriptors ring */ -+ for (ix=0; ixbufSize = 0x0; -+ pRxDesc->byteCnt = 0x0; -+ pRxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; -+ pRxDesc->bufPtr = 0x0; -+ pRxDesc->returnInfo = 0x0; -+ pRxPrevDesc = pRxDesc; -+ if(ix == (rxDescNum-1)) -+ { -+ /* Closing Rx descriptors ring */ -+ pRxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pRxDescBase); -+ } -+ else -+ { -+ pRxDesc = (ETH_RX_DESC*)((MV_ULONG)pRxDesc + ETH_RX_DESC_ALIGNED_SIZE); -+ pRxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pRxDesc); -+ } -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxPrevDesc); -+ } -+ -+ pQueueCtrl->pCurrentDescr = pRxDescBase; -+ pQueueCtrl->pUsedDescr = pRxDescBase; -+ -+ pQueueCtrl->pFirstDescr = pRxDescBase; -+ pQueueCtrl->pLastDescr = pRxDesc; -+ pQueueCtrl->resource = 0; -+} -+ -+void ethResetRxDescRing(void* pPortHndl, int queue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->rxQueue[queue]; -+ ETH_RX_DESC* pRxDesc = (ETH_RX_DESC*)pQueueCtrl->pFirstDescr; -+ -+ pQueueCtrl->resource = 0; -+ if(pQueueCtrl->pFirstDescr != NULL) -+ { -+ while(MV_TRUE) -+ { -+ pRxDesc->bufSize = 0x0; -+ pRxDesc->byteCnt = 0x0; -+ pRxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; -+ pRxDesc->bufPtr = 0x0; -+ pRxDesc->returnInfo = 0x0; -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxDesc); -+ if( (void*)pRxDesc == pQueueCtrl->pLastDescr) -+ break; -+ pRxDesc = RX_NEXT_DESC_PTR(pRxDesc, pQueueCtrl); -+ } -+ pQueueCtrl->pCurrentDescr = pQueueCtrl->pFirstDescr; -+ pQueueCtrl->pUsedDescr = pQueueCtrl->pFirstDescr; -+ -+ /* Update RX Command register */ -+ pPortCtrl->portRxQueueCmdReg |= (1 << queue); -+ -+ /* update HW */ -+ MV_REG_WRITE( ETH_RX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), -+ (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); -+ } -+ else -+ { -+ /* Update RX Command register */ -+ pPortCtrl->portRxQueueCmdReg &= ~(1 << queue); -+ -+ /* update HW */ -+ MV_REG_WRITE( ETH_RX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), 0); -+ } -+} -+ -+/******************************************************************************* -+* etherInitTxDescRing - Curve a Tx chain desc list and buffer in memory. -+* -+* DESCRIPTION: -+* This function prepares a Tx chained list of descriptors and packet -+* buffers in a form of a ring. The routine must be called after port -+* initialization routine and before port start routine. -+* The Ethernet SDMA engine uses CPU bus addresses to access the various -+* devices in the system (i.e. DRAM). This function uses the ethernet -+* struct 'virtual to physical' routine (set by the user) to set the ring -+* with physical addresses. -+* -+* INPUT: -+* ETH_PORT_CTRL *pEthPortCtrl Ethernet Port Control srtuct. -+* int txQueue Number of Tx queue. -+* int txDescNum Number of Tx descriptors -+* int txBuffSize Size of Tx buffer -+* MV_U8* pTxDescBase Tx descriptors memory area base addr. -+* -+* OUTPUT: -+* The routine updates the Ethernet port control struct with information -+* regarding the Tx descriptors and buffers. -+* -+* RETURN: None. -+* -+*******************************************************************************/ -+static void ethInitTxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue) -+{ -+ ETH_TX_DESC *pTxDescBase, *pTxDesc, *pTxPrevDesc; -+ int ix, txDescNum = pPortCtrl->txQueueConfig[queue].descrNum; -+ ETH_QUEUE_CTRL *pQueueCtrl = &pPortCtrl->txQueue[queue]; -+ -+ /* Make sure descriptor address is cache line size aligned */ -+ pTxDescBase = (ETH_TX_DESC*)MV_ALIGN_UP((MV_ULONG)pQueueCtrl->descBuf.bufVirtPtr, -+ CPU_D_CACHE_LINE_SIZE); -+ -+ pTxDesc = (ETH_TX_DESC*)pTxDescBase; -+ pTxPrevDesc = pTxDesc; -+ -+ /* initialize the Tx descriptors ring */ -+ for (ix=0; ixbyteCnt = 0x0000; -+ pTxDesc->L4iChk = 0x0000; -+ pTxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; -+ pTxDesc->bufPtr = 0x0; -+ pTxDesc->returnInfo = 0x0; -+ -+ pTxPrevDesc = pTxDesc; -+ -+ if(ix == (txDescNum-1)) -+ { -+ /* Closing Tx descriptors ring */ -+ pTxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pTxDescBase); -+ } -+ else -+ { -+ pTxDesc = (ETH_TX_DESC*)((MV_ULONG)pTxDesc + ETH_TX_DESC_ALIGNED_SIZE); -+ pTxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pTxDesc); -+ } -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxPrevDesc); -+ } -+ -+ pQueueCtrl->pCurrentDescr = pTxDescBase; -+ pQueueCtrl->pUsedDescr = pTxDescBase; -+ -+ pQueueCtrl->pFirstDescr = pTxDescBase; -+ pQueueCtrl->pLastDescr = pTxDesc; -+ /* Leave one TX descriptor out of use */ -+ pQueueCtrl->resource = txDescNum - 1; -+} -+ -+void ethResetTxDescRing(void* pPortHndl, int queue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->txQueue[queue]; -+ ETH_TX_DESC* pTxDesc = (ETH_TX_DESC*)pQueueCtrl->pFirstDescr; -+ -+ pQueueCtrl->resource = 0; -+ if(pQueueCtrl->pFirstDescr != NULL) -+ { -+ while(MV_TRUE) -+ { -+ pTxDesc->byteCnt = 0x0000; -+ pTxDesc->L4iChk = 0x0000; -+ pTxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; -+ pTxDesc->bufPtr = 0x0; -+ pTxDesc->returnInfo = 0x0; -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxDesc); -+ pQueueCtrl->resource++; -+ if( (void*)pTxDesc == pQueueCtrl->pLastDescr) -+ break; -+ pTxDesc = TX_NEXT_DESC_PTR(pTxDesc, pQueueCtrl); -+ } -+ /* Leave one TX descriptor out of use */ -+ pQueueCtrl->resource--; -+ pQueueCtrl->pCurrentDescr = pQueueCtrl->pFirstDescr; -+ pQueueCtrl->pUsedDescr = pQueueCtrl->pFirstDescr; -+ -+ /* Update TX Command register */ -+ pPortCtrl->portTxQueueCmdReg |= MV_32BIT_LE_FAST(1 << queue); -+ /* update HW */ -+ MV_REG_WRITE( ETH_TX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), -+ (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); -+ } -+ else -+ { -+ /* Update TX Command register */ -+ pPortCtrl->portTxQueueCmdReg &= MV_32BIT_LE_FAST(~(1 << queue)); -+ /* update HW */ -+ MV_REG_WRITE( ETH_TX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), 0 ); -+ } -+} -+ -+/******************************************************************************* -+* ethAllocDescrMemory - Free memory allocated for RX and TX descriptors. -+* -+* DESCRIPTION: -+* This function allocates memory for RX and TX descriptors. -+* - If ETH_DESCR_IN_SRAM defined, allocate memory from SRAM. -+* - If ETH_DESCR_IN_SDRAM defined, allocate memory in SDRAM. -+* -+* INPUT: -+* int size - size of memory should be allocated. -+* -+* RETURN: None -+* -+*******************************************************************************/ -+static MV_U8* ethAllocDescrMemory(ETH_PORT_CTRL* pPortCtrl, int descSize, -+ MV_ULONG* pPhysAddr, MV_U32 *memHandle) -+{ -+ MV_U8* pVirt; -+ -+#if defined(ETH_DESCR_IN_SRAM) -+ if(ethDescInSram == MV_TRUE) -+ pVirt = (char*)mvSramMalloc(descSize, pPhysAddr); -+ else -+#endif /* ETH_DESCR_IN_SRAM */ -+ { -+#ifdef ETH_DESCR_UNCACHED -+ pVirt = (MV_U8*)mvOsIoUncachedMalloc(pPortCtrl->osHandle, descSize, -+ pPhysAddr,memHandle); -+#else -+ pVirt = (MV_U8*)mvOsIoCachedMalloc(pPortCtrl->osHandle, descSize, -+ pPhysAddr, memHandle); -+#endif /* ETH_DESCR_UNCACHED */ -+ } -+ memset(pVirt, 0, descSize); -+ -+ return pVirt; -+} -+ -+/******************************************************************************* -+* ethFreeDescrMemory - Free memory allocated for RX and TX descriptors. -+* -+* DESCRIPTION: -+* This function frees memory allocated for RX and TX descriptors. -+* - If ETH_DESCR_IN_SRAM defined, free memory using gtSramFree() function. -+* - If ETH_DESCR_IN_SDRAM defined, free memory using mvOsFree() function. -+* -+* INPUT: -+* void* pVirtAddr - virtual pointer to memory allocated for RX and TX -+* desriptors. -+* -+* RETURN: None -+* -+*******************************************************************************/ -+void ethFreeDescrMemory(ETH_PORT_CTRL* pPortCtrl, MV_BUF_INFO* pDescBuf) -+{ -+ if( (pDescBuf == NULL) || (pDescBuf->bufVirtPtr == NULL) ) -+ return; -+ -+#if defined(ETH_DESCR_IN_SRAM) -+ if( ethDescInSram ) -+ { -+ mvSramFree(pDescBuf->bufSize, pDescBuf->bufPhysAddr, pDescBuf->bufVirtPtr); -+ return; -+ } -+#endif /* ETH_DESCR_IN_SRAM */ -+ -+#ifdef ETH_DESCR_UNCACHED -+ mvOsIoUncachedFree(pPortCtrl->osHandle, pDescBuf->bufSize, pDescBuf->bufPhysAddr, -+ pDescBuf->bufVirtPtr,pDescBuf->memHandle); -+#else -+ mvOsIoCachedFree(pPortCtrl->osHandle, pDescBuf->bufSize, pDescBuf->bufPhysAddr, -+ pDescBuf->bufVirtPtr,pDescBuf->memHandle); -+#endif /* ETH_DESCR_UNCACHED */ -+} -+ -+/******************************************************************************/ -+/* Other Functions */ -+/******************************************************************************/ -+ -+void mvEthPortPowerUp(int port) -+{ -+ MV_U32 regVal; -+ -+ /* MAC Cause register should be cleared */ -+ MV_REG_WRITE(ETH_UNIT_INTR_CAUSE_REG(port), 0); -+ -+ if (mvBoardIsPortInSgmii(port)) -+ mvEthPortSgmiiConfig(port); -+ -+ /* Cancel Port Reset */ -+ regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)); -+ regVal &= (~ETH_PORT_RESET_MASK); -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal); -+ while( (MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)) & ETH_PORT_RESET_MASK) != 0); -+} -+ -+void mvEthPortPowerDown(int port) -+{ -+ MV_U32 regVal; -+ -+ /* Port must be DISABLED */ -+ regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port)); -+ if( (regVal & ETH_PORT_ENABLE_MASK) != 0) -+ { -+ mvOsPrintf("ethPort #%d: PowerDown - port must be Disabled (PSC=0x%x)\n", -+ port, regVal); -+ return; -+ } -+ -+ /* Port Reset (Read after write the register as a precaution) */ -+ regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)); -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal | ETH_PORT_RESET_MASK); -+ while((MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)) & ETH_PORT_RESET_MASK) == 0); -+} -+ -+static void mvEthPortSgmiiConfig(int port) -+{ -+ MV_U32 regVal; -+ -+ regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)); -+ -+ regVal |= (ETH_SGMII_MODE_MASK /*| ETH_INBAND_AUTO_NEG_ENABLE_MASK */); -+ regVal &= (~ETH_INBAND_AUTO_NEG_BYPASS_MASK); -+ -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal); -+} -+ -+ -+ -+ -+ -+ -+ -+ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c 2010-11-09 20:28:11.072495491 +0100 -@@ -0,0 +1,748 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+/******************************************************************************* -+* mvEthDebug.c - Source file for user friendly debug functions -+* -+* DESCRIPTION: -+* -+* DEPENDENCIES: -+* None. -+* -+*******************************************************************************/ -+ -+#include "mvOs.h" -+#include "mvCommon.h" -+#include "mvTypes.h" -+#include "mv802_3.h" -+#include "mvDebug.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "eth-phy/mvEthPhy.h" -+#include "eth/mvEth.h" -+#include "eth/gbe/mvEthDebug.h" -+ -+/* #define mvOsPrintf printf */ -+ -+void mvEthPortShow(void* pHndl); -+void mvEthQueuesShow(void* pHndl, int rxQueue, int txQueue, int mode); -+ -+/******************************************************************************/ -+/* Debug functions */ -+/******************************************************************************/ -+void ethRxCoal(int port, int usec) -+{ -+ void* pHndl; -+ -+ pHndl = mvEthPortHndlGet(port); -+ if(pHndl != NULL) -+ { -+ mvEthRxCoalSet(pHndl, usec); -+ } -+} -+ -+void ethTxCoal(int port, int usec) -+{ -+ void* pHndl; -+ -+ pHndl = mvEthPortHndlGet(port); -+ if(pHndl != NULL) -+ { -+ mvEthTxCoalSet(pHndl, usec); -+ } -+} -+ -+#if (MV_ETH_VERSION >= 4) -+void ethEjpModeSet(int port, int mode) -+{ -+ void* pHndl; -+ -+ pHndl = mvEthPortHndlGet(port); -+ if(pHndl != NULL) -+ { -+ mvEthEjpModeSet(pHndl, mode); -+ } -+} -+#endif /* (MV_ETH_VERSION >= 4) */ -+ -+void ethBpduRxQ(int port, int bpduQueue) -+{ -+ void* pHndl; -+ -+ pHndl = mvEthPortHndlGet(port); -+ if(pHndl != NULL) -+ { -+ mvEthBpduRxQueue(pHndl, bpduQueue); -+ } -+} -+ -+void ethArpRxQ(int port, int arpQueue) -+{ -+ void* pHndl; -+ -+ pHndl = mvEthPortHndlGet(port); -+ if(pHndl != NULL) -+ { -+ mvEthArpRxQueue(pHndl, arpQueue); -+ } -+} -+ -+void ethTcpRxQ(int port, int tcpQueue) -+{ -+ void* pHndl; -+ -+ pHndl = mvEthPortHndlGet(port); -+ if(pHndl != NULL) -+ { -+ mvEthTcpRxQueue(pHndl, tcpQueue); -+ } -+} -+ -+void ethUdpRxQ(int port, int udpQueue) -+{ -+ void* pHndl; -+ -+ pHndl = mvEthPortHndlGet(port); -+ if(pHndl != NULL) -+ { -+ mvEthUdpRxQueue(pHndl, udpQueue); -+ } -+} -+ -+void ethTxPolicyRegs(int port) -+{ -+ int queue; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)mvEthPortHndlGet(port); -+ -+ if(pPortCtrl == NULL) -+ { -+ return; -+ } -+ mvOsPrintf("Port #%d TX Policy: EJP=%d, TXQs: ", -+ port, pPortCtrl->portConfig.ejpMode); -+ for(queue=0; queuetxQueueConfig[queue].descrNum > 0) -+ mvOsPrintf("%d, ", queue); -+ } -+ mvOsPrintf("\n"); -+ -+ mvOsPrintf("\n\t TX policy Port #%d configuration registers\n", port); -+ -+ mvOsPrintf("ETH_TX_QUEUE_COMMAND_REG : 0x%X = 0x%08x\n", -+ ETH_TX_QUEUE_COMMAND_REG(port), -+ MV_REG_READ( ETH_TX_QUEUE_COMMAND_REG(port) ) ); -+ -+ mvOsPrintf("ETH_TX_FIXED_PRIO_CFG_REG : 0x%X = 0x%08x\n", -+ ETH_TX_FIXED_PRIO_CFG_REG(port), -+ MV_REG_READ( ETH_TX_FIXED_PRIO_CFG_REG(port) ) ); -+ -+ mvOsPrintf("ETH_TX_TOKEN_RATE_CFG_REG : 0x%X = 0x%08x\n", -+ ETH_TX_TOKEN_RATE_CFG_REG(port), -+ MV_REG_READ( ETH_TX_TOKEN_RATE_CFG_REG(port) ) ); -+ -+ mvOsPrintf("ETH_MAX_TRANSMIT_UNIT_REG : 0x%X = 0x%08x\n", -+ ETH_MAX_TRANSMIT_UNIT_REG(port), -+ MV_REG_READ( ETH_MAX_TRANSMIT_UNIT_REG(port) ) ); -+ -+ mvOsPrintf("ETH_TX_TOKEN_BUCKET_SIZE_REG : 0x%X = 0x%08x\n", -+ ETH_TX_TOKEN_BUCKET_SIZE_REG(port), -+ MV_REG_READ( ETH_TX_TOKEN_BUCKET_SIZE_REG(port) ) ); -+ -+ mvOsPrintf("ETH_TX_TOKEN_BUCKET_COUNT_REG : 0x%X = 0x%08x\n", -+ ETH_TX_TOKEN_BUCKET_COUNT_REG(port), -+ MV_REG_READ( ETH_TX_TOKEN_BUCKET_COUNT_REG(port) ) ); -+ -+ for(queue=0; queue> 24) & 0xff), ((macH >> 16) & 0xff), -+ ((macH >> 8) & 0xff), (macH & 0xff), -+ ((macL >> 8) & 0xff), (macL & 0xff) ); -+ -+ for (i=0; i<4; i++) -+ { -+ unicastReg = MV_REG_READ( (ETH_DA_FILTER_UCAST_BASE(port) + i*4)); -+ for(j=0; j<4; j++) -+ { -+ MV_U8 macEntry = (unicastReg >> (8*j)) & 0xFF; -+ -+ mvOsPrintf("%X: %8s, Q = %d\n", i*4+j, -+ (macEntry & BIT0) ? "Accept" : "Reject", (macEntry >> 1) & 0x7); -+ } -+ } -+} -+ -+void ethMcastAdd(int port, char* macStr, int queue) -+{ -+ void* pHndl; -+ MV_U8 macAddr[MV_MAC_ADDR_SIZE]; -+ -+ pHndl = mvEthPortHndlGet(port); -+ if(pHndl != NULL) -+ { -+ mvMacStrToHex(macStr, macAddr); -+ mvEthMcastAddrSet(pHndl, macAddr, queue); -+ } -+} -+ -+void ethPortMcast(int port) -+{ -+ int tblIdx, regIdx; -+ MV_U32 regVal; -+ -+ mvOsPrintf("\n\t Port #%d Special (IP) Multicast table: 01:00:5E:00:00:XX\n\n", -+ port); -+ -+ for(tblIdx=0; tblIdx<(256/4); tblIdx++) -+ { -+ regVal = MV_REG_READ((ETH_DA_FILTER_SPEC_MCAST_BASE(port) + tblIdx*4)); -+ for(regIdx=0; regIdx<4; regIdx++) -+ { -+ if((regVal & (0x01 << (regIdx*8))) != 0) -+ { -+ mvOsPrintf("0x%02X: Accepted, rxQ = %d\n", -+ tblIdx*4+regIdx, ((regVal >> (regIdx*8+1)) & 0x07)); -+ } -+ } -+ } -+ mvOsPrintf("\n\t Port #%d Other Multicast table\n\n", port); -+ for(tblIdx=0; tblIdx<(256/4); tblIdx++) -+ { -+ regVal = MV_REG_READ((ETH_DA_FILTER_OTH_MCAST_BASE(port) + tblIdx*4)); -+ for(regIdx=0; regIdx<4; regIdx++) -+ { -+ if((regVal & (0x01 << (regIdx*8))) != 0) -+ { -+ mvOsPrintf("Crc8=0x%02X: Accepted, rxQ = %d\n", -+ tblIdx*4+regIdx, ((regVal >> (regIdx*8+1)) & 0x07)); -+ } -+ } -+ } -+} -+ -+ -+/* Print status of Ethernet port */ -+void mvEthPortShow(void* pHndl) -+{ -+ MV_U32 regValue, rxCoal, txCoal; -+ int speed, queue, port; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pHndl; -+ -+ port = pPortCtrl->portNo; -+ -+ regValue = MV_REG_READ( ETH_PORT_STATUS_REG(port) ); -+ -+ mvOsPrintf("\n\t ethGiga #%d port Status: 0x%04x = 0x%08x\n\n", -+ port, ETH_PORT_STATUS_REG(port), regValue); -+ -+ mvOsPrintf("descInSram=%d, descSwCoher=%d\n", -+ ethDescInSram, ethDescSwCoher); -+ -+ if(regValue & ETH_GMII_SPEED_1000_MASK) -+ speed = 1000; -+ else if(regValue & ETH_MII_SPEED_100_MASK) -+ speed = 100; -+ else -+ speed = 10; -+ -+ mvEthCoalGet(pPortCtrl, &rxCoal, &txCoal); -+ -+ /* Link, Speed, Duplex, FlowControl */ -+ mvOsPrintf("Link=%s, Speed=%d, Duplex=%s, RxFlowControl=%s", -+ (regValue & ETH_LINK_UP_MASK) ? "UP" : "DOWN", -+ speed, -+ (regValue & ETH_FULL_DUPLEX_MASK) ? "FULL" : "HALF", -+ (regValue & ETH_ENABLE_RCV_FLOW_CTRL_MASK) ? "ENABLE" : "DISABLE"); -+ -+ mvOsPrintf("\n"); -+ -+ mvOsPrintf("RxCoal = %d usec, TxCoal = %d usec\n", -+ rxCoal, txCoal); -+ -+ mvOsPrintf("rxDefQ=%d, arpQ=%d, bpduQ=%d, tcpQ=%d, udpQ=%d\n\n", -+ pPortCtrl->portConfig.rxDefQ, pPortCtrl->portConfig.rxArpQ, -+ pPortCtrl->portConfig.rxBpduQ, -+ pPortCtrl->portConfig.rxTcpQ, pPortCtrl->portConfig.rxUdpQ); -+ -+ /* Print all RX and TX queues */ -+ for(queue=0; queuerxQueue[queue].pFirstDescr, -+ mvEthRxResourceGet(pPortCtrl, queue) ); -+ } -+ mvOsPrintf("\n"); -+ for(queue=0; queuetxQueue[queue].pFirstDescr, -+ mvEthTxResourceGet(pPortCtrl, queue) ); -+ } -+} -+ -+/* Print RX and TX queue of the Ethernet port */ -+void mvEthQueuesShow(void* pHndl, int rxQueue, int txQueue, int mode) -+{ -+ ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL*)pHndl; -+ ETH_QUEUE_CTRL *pQueueCtrl; -+ MV_U32 regValue; -+ ETH_RX_DESC *pRxDescr; -+ ETH_TX_DESC *pTxDescr; -+ int i, port = pPortCtrl->portNo; -+ -+ if( (rxQueue >=0) && (rxQueue < MV_ETH_RX_Q_NUM) ) -+ { -+ pQueueCtrl = &(pPortCtrl->rxQueue[rxQueue]); -+ mvOsPrintf("Port #%d, RX Queue #%d\n\n", port, rxQueue); -+ -+ mvOsPrintf("CURR_RX_DESC_PTR : 0x%X = 0x%08x\n", -+ ETH_RX_CUR_DESC_PTR_REG(port, rxQueue), -+ MV_REG_READ( ETH_RX_CUR_DESC_PTR_REG(port, rxQueue))); -+ -+ -+ if(pQueueCtrl->pFirstDescr != NULL) -+ { -+ mvOsPrintf("pFirstDescr=0x%lx, pLastDescr=0x%lx, numOfResources=%d\n", -+ (MV_ULONG)pQueueCtrl->pFirstDescr, (MV_ULONG)pQueueCtrl->pLastDescr, -+ pQueueCtrl->resource); -+ mvOsPrintf("pCurrDescr: 0x%lx, pUsedDescr: 0x%lx\n", -+ (MV_ULONG)pQueueCtrl->pCurrentDescr, -+ (MV_ULONG)pQueueCtrl->pUsedDescr); -+ -+ if(mode == 1) -+ { -+ pRxDescr = (ETH_RX_DESC*)pQueueCtrl->pFirstDescr; -+ i = 0; -+ do -+ { -+ mvOsPrintf("%3d. desc=%08x (%08x), cmd=%08x, data=%4d, buf=%4d, buf=%08x, pkt=%lx, os=%lx\n", -+ i, (MV_U32)pRxDescr, (MV_U32)ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pRxDescr), -+ pRxDescr->cmdSts, pRxDescr->byteCnt, (MV_U32)pRxDescr->bufSize, -+ (unsigned int)pRxDescr->bufPtr, (MV_ULONG)pRxDescr->returnInfo, -+ ((MV_PKT_INFO*)pRxDescr->returnInfo)->osInfo); -+ -+ ETH_DESCR_INV(pPortCtrl, pRxDescr); -+ pRxDescr = RX_NEXT_DESC_PTR(pRxDescr, pQueueCtrl); -+ i++; -+ } while (pRxDescr != pQueueCtrl->pFirstDescr); -+ } -+ } -+ else -+ mvOsPrintf("RX Queue #%d is NOT CREATED\n", rxQueue); -+ } -+ -+ if( (txQueue >=0) && (txQueue < MV_ETH_TX_Q_NUM) ) -+ { -+ pQueueCtrl = &(pPortCtrl->txQueue[txQueue]); -+ mvOsPrintf("Port #%d, TX Queue #%d\n\n", port, txQueue); -+ -+ regValue = MV_REG_READ( ETH_TX_CUR_DESC_PTR_REG(port, txQueue)); -+ mvOsPrintf("CURR_TX_DESC_PTR : 0x%X = 0x%08x\n", -+ ETH_TX_CUR_DESC_PTR_REG(port, txQueue), regValue); -+ -+ if(pQueueCtrl->pFirstDescr != NULL) -+ { -+ mvOsPrintf("pFirstDescr=0x%lx, pLastDescr=0x%lx, numOfResources=%d\n", -+ (MV_ULONG)pQueueCtrl->pFirstDescr, -+ (MV_ULONG)pQueueCtrl->pLastDescr, -+ pQueueCtrl->resource); -+ mvOsPrintf("pCurrDescr: 0x%lx, pUsedDescr: 0x%lx\n", -+ (MV_ULONG)pQueueCtrl->pCurrentDescr, -+ (MV_ULONG)pQueueCtrl->pUsedDescr); -+ -+ if(mode == 1) -+ { -+ pTxDescr = (ETH_TX_DESC*)pQueueCtrl->pFirstDescr; -+ i = 0; -+ do -+ { -+ mvOsPrintf("%3d. desc=%08x (%08x), cmd=%08x, data=%4d, buf=%08x, pkt=%lx, os=%lx\n", -+ i, (MV_U32)pTxDescr, (MV_U32)ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pTxDescr), -+ pTxDescr->cmdSts, pTxDescr->byteCnt, -+ (MV_U32)pTxDescr->bufPtr, (MV_ULONG)pTxDescr->returnInfo, -+ pTxDescr->returnInfo ? (((MV_PKT_INFO*)pTxDescr->returnInfo)->osInfo) : 0x0); -+ -+ ETH_DESCR_INV(pPortCtrl, pTxDescr); -+ pTxDescr = TX_NEXT_DESC_PTR(pTxDescr, pQueueCtrl); -+ i++; -+ } while (pTxDescr != pQueueCtrl->pFirstDescr); -+ } -+ } -+ else -+ mvOsPrintf("TX Queue #%d is NOT CREATED\n", txQueue); -+ } -+} -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.h 2010-11-09 20:28:11.112495471 +0100 -@@ -0,0 +1,146 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#ifndef __MV_ETH_DEBUG_H__ -+#define __MV_ETH_DEBUG_H__ -+ -+#if 0 -+/* -+ ** Externs -+ */ -+void ethBpduRxQ(int port, int bpduQueue); -+void ethArpRxQ(int port, int bpduQueue); -+void ethTcpRxQ(int port, int bpduQueue); -+void ethUdpRxQ(int port, int bpduQueue); -+void ethMcastAdd(int port, char* macStr, int queue); -+ -+#ifdef INCLUDE_MULTI_QUEUE -+void ethRxPolicy( int port); -+void ethTxPolicy( int port); -+void ethTxPolDA(int port, char* macStr, int txQ, char* headerHexStr); -+void ethRxPolMode(int port, MV_ETH_PRIO_MODE prioMode); -+void ethRxPolQ(int port, int rxQueue, int rxQuota); -+#endif /* INCLUDE_MULTI_QUEUE */ -+ -+void print_egiga_stat(void *sc, unsigned int port); -+void ethPortStatus (int port); -+void ethPortQueues( int port, int rxQueue, int txQueue, int mode); -+void ethPortMcast(int port); -+void ethPortRegs(int port); -+void ethPortCounters(int port); -+void ethPortRmonCounters(int port); -+void ethRxCoal(int port, int usec); -+void ethTxCoal(int port, int usec); -+ -+void ethRegs(int port); -+void ethClearCounters(int port); -+void ethUcastSet(int port, char* macStr, int queue); -+void ethPortUcastShow(int port); -+ -+#ifdef CONFIG_MV_ETH_HEADER -+void run_com_header(const char *buffer); -+#endif -+ -+#ifdef INCLUDE_MULTI_QUEUE -+void ethRxPolMode(int port, MV_ETH_PRIO_MODE prioMode); -+void ethRxPolQ(int port, int queue, int quota); -+void ethRxPolicy(int port); -+void ethTxPolDef(int port, int txQ, char* headerHexStr); -+void ethTxPolDA(int port, char* macStr, int txQ, char* headerHexStr); -+void ethTxPolicy(int port); -+#endif /* INCLUDE_MULTI_QUEUE */ -+ -+#if (MV_ETH_VERSION >= 4) -+void ethEjpModeSet(int port, int mode) -+#endif -+#endif /* 0 */ -+ -+ -+ -+ -+void ethRxCoal(int port, int usec); -+void ethTxCoal(int port, int usec); -+#if (MV_ETH_VERSION >= 4) -+void ethEjpModeSet(int port, int mode); -+#endif /* (MV_ETH_VERSION >= 4) */ -+ -+void ethBpduRxQ(int port, int bpduQueue); -+void ethArpRxQ(int port, int arpQueue); -+void ethTcpRxQ(int port, int tcpQueue); -+void ethUdpRxQ(int port, int udpQueue); -+void ethTxPolicyRegs(int port); -+void ethPortRegs(int port); -+void ethRegs(int port); -+void ethClearCounters(int port); -+void ethPortCounters(int port); -+void ethPortRmonCounters(int port); -+void ethPortStatus(int port); -+void ethPortQueues(int port, int rxQueue, int txQueue, int mode); -+void ethUcastSet(int port, char* macStr, int queue); -+void ethPortUcastShow(int port); -+void ethMcastAdd(int port, char* macStr, int queue); -+void ethPortMcast(int port); -+void mvEthPortShow(void* pHndl); -+void mvEthQueuesShow(void* pHndl, int rxQueue, int txQueue, int mode); -+ -+#endif -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthGbe.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthGbe.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthGbe.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthGbe.h 2010-11-09 20:28:11.152495442 +0100 -@@ -0,0 +1,751 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+/******************************************************************************* -+* mvEth.h - Header File for : Marvell Gigabit Ethernet Controller -+* -+* DESCRIPTION: -+* This header file contains macros typedefs and function declaration specific to -+* the Marvell Gigabit Ethernet Controller. -+* -+* DEPENDENCIES: -+* None. -+* -+*******************************************************************************/ -+ -+#ifndef __mvEthGbe_h__ -+#define __mvEthGbe_h__ -+ -+extern MV_BOOL ethDescInSram; -+extern MV_BOOL ethDescSwCoher; -+extern ETH_PORT_CTRL* ethPortCtrl[]; -+ -+static INLINE MV_ULONG ethDescVirtToPhy(ETH_QUEUE_CTRL* pQueueCtrl, MV_U8* pDesc) -+{ -+#if defined (ETH_DESCR_IN_SRAM) -+ if( ethDescInSram ) -+ return mvSramVirtToPhy(pDesc); -+ else -+#endif /* ETH_DESCR_IN_SRAM */ -+ return (pQueueCtrl->descBuf.bufPhysAddr + (pDesc - pQueueCtrl->descBuf.bufVirtPtr)); -+} -+/* Return port handler */ -+#define mvEthPortHndlGet(port) ethPortCtrl[port] -+ -+/* Used as WA for HW/SW race on TX */ -+static INLINE int mvEthPortTxEnable(void* pPortHndl, int queue, int max_deep) -+{ -+ int deep = 0; -+ MV_U32 txCurrReg, txEnReg; -+ ETH_TX_DESC* pTxLastDesc; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ -+ txEnReg = MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)); -+ if( (txEnReg & MV_32BIT_LE_FAST(ETH_TXQ_ENABLE_MASK)) == 0) -+ { -+ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) = pPortCtrl->portTxQueueCmdReg; -+ return 0; -+ } -+ -+ pQueueCtrl = &pPortCtrl->txQueue[queue]; -+ pTxLastDesc = pQueueCtrl->pCurrentDescr; -+ txCurrReg = MV_REG_READ(ETH_TX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue)); -+ if(ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pTxLastDesc) == txCurrReg) -+ { -+ /* All descriptors are processed, no chance for race */ -+ return 0; -+ } -+ -+ /* Check distance betwee HW and SW location: */ -+ /* If distance between HW and SW pointers is less than max_deep descriptors */ -+ /* Race condition is possible, so wait end of TX and restart TXQ */ -+ while(deep < max_deep) -+ { -+ pTxLastDesc = TX_PREV_DESC_PTR(pTxLastDesc, pQueueCtrl); -+ if(ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pTxLastDesc) == txCurrReg) -+ { -+ int count = 0; -+ -+ while( (txEnReg & MV_32BIT_LE_FAST(ETH_TXQ_ENABLE_MASK)) != 0) -+ { -+ count++; -+ if(count > 10000) -+ { -+ mvOsPrintf("mvEthPortTxEnable: timeout - TXQ_CMD=0x%08x\n", -+ MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) ); -+ break; -+ } -+ txEnReg = MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)); -+ } -+ -+ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) = pPortCtrl->portTxQueueCmdReg; -+ return count; -+ } -+ deep++; -+ } -+ /* Distance between HW and SW pointers is more than max_deep descriptors, */ -+ /* So NO race condition - do nothing */ -+ return -1; -+} -+ -+ -+/* defines */ -+#define ETH_CSUM_MIN_BYTE_COUNT 72 -+ -+/* Tailgate and Kirwood have only 2K TX FIFO */ -+#if (MV_ETH_VERSION == 2) || (MV_ETH_VERSION == 4) -+#define ETH_CSUM_MAX_BYTE_COUNT 1600 -+#else -+#define ETH_CSUM_MAX_BYTE_COUNT 9*1024 -+#endif /* MV_ETH_VERSION */ -+ -+#define ETH_MV_HEADER_SIZE 2 -+#define ETH_MV_TX_EN -+ -+/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */ -+#define MIN_TX_BUFF_LOAD 8 -+#define TX_BUF_OFFSET_IN_DESC (ETH_TX_DESC_ALIGNED_SIZE - MIN_TX_BUFF_LOAD) -+ -+/* Default port configuration value */ -+#define PORT_CONFIG_VALUE \ -+ ETH_DEF_RX_QUEUE_MASK(0) | \ -+ ETH_DEF_RX_ARP_QUEUE_MASK(0) | \ -+ ETH_DEF_RX_TCP_QUEUE_MASK(0) | \ -+ ETH_DEF_RX_UDP_QUEUE_MASK(0) | \ -+ ETH_DEF_RX_BPDU_QUEUE_MASK(0) | \ -+ ETH_RX_CHECKSUM_WITH_PSEUDO_HDR -+ -+/* Default port extend configuration value */ -+#define PORT_CONFIG_EXTEND_VALUE 0 -+ -+#define PORT_SERIAL_CONTROL_VALUE \ -+ ETH_DISABLE_FC_AUTO_NEG_MASK | \ -+ BIT9 | \ -+ ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ -+ ETH_MAX_RX_PACKET_1552BYTE | \ -+ ETH_SET_FULL_DUPLEX_MASK -+ -+#define PORT_SERIAL_CONTROL_100MB_FORCE_VALUE \ -+ ETH_FORCE_LINK_PASS_MASK | \ -+ ETH_DISABLE_DUPLEX_AUTO_NEG_MASK | \ -+ ETH_DISABLE_FC_AUTO_NEG_MASK | \ -+ BIT9 | \ -+ ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ -+ ETH_DISABLE_SPEED_AUTO_NEG_MASK | \ -+ ETH_SET_FULL_DUPLEX_MASK | \ -+ ETH_SET_MII_SPEED_100_MASK | \ -+ ETH_MAX_RX_PACKET_1552BYTE -+ -+ -+#define PORT_SERIAL_CONTROL_1000MB_FORCE_VALUE \ -+ ETH_FORCE_LINK_PASS_MASK | \ -+ ETH_DISABLE_DUPLEX_AUTO_NEG_MASK | \ -+ ETH_DISABLE_FC_AUTO_NEG_MASK | \ -+ BIT9 | \ -+ ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ -+ ETH_DISABLE_SPEED_AUTO_NEG_MASK | \ -+ ETH_SET_FULL_DUPLEX_MASK | \ -+ ETH_SET_GMII_SPEED_1000_MASK | \ -+ ETH_MAX_RX_PACKET_1552BYTE -+ -+#define PORT_SERIAL_CONTROL_SGMII_IBAN_VALUE \ -+ ETH_DISABLE_FC_AUTO_NEG_MASK | \ -+ BIT9 | \ -+ ETH_IN_BAND_AN_EN_MASK | \ -+ ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ -+ ETH_MAX_RX_PACKET_1552BYTE -+ -+/* Function headers: */ -+MV_VOID mvEthSetSpecialMcastTable(int portNo, int queue); -+MV_STATUS mvEthArpRxQueue(void* pPortHandle, int arpQueue); -+MV_STATUS mvEthUdpRxQueue(void* pPortHandle, int udpQueue); -+MV_STATUS mvEthTcpRxQueue(void* pPortHandle, int tcpQueue); -+MV_STATUS mvEthMacAddrGet(int portNo, unsigned char *pAddr); -+MV_VOID mvEthSetOtherMcastTable(int portNo, int queue); -+MV_STATUS mvEthHeaderModeSet(void* pPortHandle, MV_ETH_HEADER_MODE headerMode); -+/* Interrupt Coalesting functions */ -+MV_U32 mvEthRxCoalSet(void* pPortHndl, MV_U32 uSec); -+MV_U32 mvEthTxCoalSet(void* pPortHndl, MV_U32 uSec); -+MV_STATUS mvEthCoalGet(void* pPortHndl, MV_U32* pRxCoal, MV_U32* pTxCoal); -+ -+/******************************************************************************/ -+/* Data Flow functions */ -+/******************************************************************************/ -+static INLINE void mvEthPortTxRestart(void* pPortHndl) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ -+ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) = pPortCtrl->portTxQueueCmdReg; -+} -+ -+/* Get number of Free resources in specific TX queue */ -+static INLINE int mvEthTxResourceGet(void* pPortHndl, int txQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ -+ return (pPortCtrl->txQueue[txQueue].resource); -+} -+ -+/* Get number of Free resources in specific RX queue */ -+static INLINE int mvEthRxResourceGet(void* pPortHndl, int rxQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ -+ return (pPortCtrl->rxQueue[rxQueue].resource); -+} -+ -+static INLINE int mvEthTxQueueIsFull(void* pPortHndl, int txQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ -+ if(pPortCtrl->txQueue[txQueue].resource == 0) -+ return MV_TRUE; -+ -+ return MV_FALSE; -+} -+ -+/* Get number of Free resources in specific RX queue */ -+static INLINE int mvEthRxQueueIsFull(void* pPortHndl, int rxQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->rxQueue[rxQueue]; -+ -+ if( (pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) && -+ (pQueueCtrl->resource != 0) ) -+ return MV_TRUE; -+ -+ return MV_FALSE; -+} -+ -+static INLINE int mvEthTxQueueIsEmpty(void* pPortHndl, int txQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->txQueue[txQueue]; -+ -+ if( (pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) && -+ (pQueueCtrl->resource != 0) ) -+ { -+ return MV_TRUE; -+ } -+ return MV_FALSE; -+} -+ -+/* Get number of Free resources in specific RX queue */ -+static INLINE int mvEthRxQueueIsEmpty(void* pPortHndl, int rxQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ -+ if(pPortCtrl->rxQueue[rxQueue].resource == 0) -+ return MV_TRUE; -+ -+ return MV_FALSE; -+} -+ -+/******************************************************************************* -+* mvEthPortTx - Send an Ethernet packet -+* -+* DESCRIPTION: -+* This routine send a given packet described by pPktInfo parameter. -+* Single buffer only. -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet Port handler. -+* int txQueue - Number of Tx queue. -+* MV_PKT_INFO *pPktInfo - User packet to send. -+* -+* RETURN: -+* MV_NO_RESOURCE - No enough resources to send this packet. -+* MV_ERROR - Unexpected Fatal error. -+* MV_OK - Packet send successfully. -+* -+*******************************************************************************/ -+static INLINE MV_STATUS mvEthPortTx(void* pEthPortHndl, int txQueue, MV_PKT_INFO* pPktInfo) -+{ -+ ETH_TX_DESC* pTxCurrDesc; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ int portNo; -+ MV_BUF_INFO* pBufInfo = pPktInfo->pFrags; -+ -+#ifdef ETH_DEBUG -+ if(pPortCtrl->portState != MV_ACTIVE) -+ return MV_BAD_STATE; -+#endif /* ETH_DEBUG */ -+ -+ portNo = pPortCtrl->portNo; -+ pQueueCtrl = &pPortCtrl->txQueue[txQueue]; -+ -+ /* Get the Tx Desc ring indexes */ -+ pTxCurrDesc = pQueueCtrl->pCurrentDescr; -+ -+ /* Check if there is enough resources to send the packet */ -+ if(pQueueCtrl->resource == 0) -+ return MV_NO_RESOURCE; -+ -+ pTxCurrDesc->byteCnt = pBufInfo->dataSize; -+ -+ /* Flash Buffer */ -+ if(pPktInfo->pktSize != 0) -+ { -+#ifdef MV_NETBSD -+ pTxCurrDesc->bufPtr = pBufInfo->bufPhysAddr; -+ ETH_PACKET_CACHE_FLUSH(pBufInfo->bufVirtPtr, pPktInfo->pktSize); -+#else -+ pTxCurrDesc->bufPtr = ETH_PACKET_CACHE_FLUSH(pBufInfo->bufVirtPtr, pPktInfo->pktSize); -+#endif -+ pPktInfo->pktSize = 0; -+ } -+ else -+ pTxCurrDesc->bufPtr = pBufInfo->bufPhysAddr; -+ -+ pTxCurrDesc->returnInfo = (MV_ULONG)pPktInfo; -+ -+ /* There is only one buffer in the packet */ -+ /* The OSG might set some bits for checksum offload, so add them to first descriptor */ -+ pTxCurrDesc->cmdSts = pPktInfo->status | -+ ETH_BUFFER_OWNED_BY_DMA | -+ ETH_TX_GENERATE_CRC_MASK | -+ ETH_TX_ENABLE_INTERRUPT_MASK | -+ ETH_TX_ZERO_PADDING_MASK | -+ ETH_TX_FIRST_DESC_MASK | -+ ETH_TX_LAST_DESC_MASK; -+ -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); -+ -+ pQueueCtrl->resource--; -+ pQueueCtrl->pCurrentDescr = TX_NEXT_DESC_PTR(pTxCurrDesc, pQueueCtrl); -+ -+ /* Apply send command */ -+ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(portNo)) = pPortCtrl->portTxQueueCmdReg; -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvEthPortSgTx - Send an Ethernet packet -+* -+* DESCRIPTION: -+* This routine send a given packet described by pBufInfo parameter. It -+* supports transmitting of a packet spaned over multiple buffers. -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet Port handler. -+* int txQueue - Number of Tx queue. -+* MV_PKT_INFO *pPktInfo - User packet to send. -+* -+* RETURN: -+* MV_NO_RESOURCE - No enough resources to send this packet. -+* MV_ERROR - Unexpected Fatal error. -+* MV_OK - Packet send successfully. -+* -+*******************************************************************************/ -+static INLINE MV_STATUS mvEthPortSgTx(void* pEthPortHndl, int txQueue, MV_PKT_INFO* pPktInfo) -+{ -+ ETH_TX_DESC* pTxFirstDesc; -+ ETH_TX_DESC* pTxCurrDesc; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ int portNo, bufCount; -+ MV_BUF_INFO* pBufInfo = pPktInfo->pFrags; -+ MV_U8* pTxBuf; -+ -+#ifdef ETH_DEBUG -+ if(pPortCtrl->portState != MV_ACTIVE) -+ return MV_BAD_STATE; -+#endif /* ETH_DEBUG */ -+ -+ portNo = pPortCtrl->portNo; -+ pQueueCtrl = &pPortCtrl->txQueue[txQueue]; -+ -+ /* Get the Tx Desc ring indexes */ -+ pTxCurrDesc = pQueueCtrl->pCurrentDescr; -+ -+ /* Check if there is enough resources to send the packet */ -+ if(pQueueCtrl->resource < pPktInfo->numFrags) -+ return MV_NO_RESOURCE; -+ -+ /* Remember first desc */ -+ pTxFirstDesc = pTxCurrDesc; -+ -+ bufCount = 0; -+ while(MV_TRUE) -+ { -+ if(pBufInfo[bufCount].dataSize <= MIN_TX_BUFF_LOAD) -+ { -+ /* Buffers with a payload smaller than MIN_TX_BUFF_LOAD (8 bytes) must be aligned */ -+ /* to 64-bit boundary. Two options here: */ -+ /* 1) Usually, copy the payload to the reserved 8 bytes inside descriptor. */ -+ /* 2) In the Half duplex workaround, the reserved 8 bytes inside descriptor are used */ -+ /* as a pointer to the aligned buffer, copy the small payload to this buffer. */ -+ pTxBuf = ((MV_U8*)pTxCurrDesc)+TX_BUF_OFFSET_IN_DESC; -+ mvOsBCopy(pBufInfo[bufCount].bufVirtPtr, pTxBuf, pBufInfo[bufCount].dataSize); -+ pTxCurrDesc->bufPtr = ethDescVirtToPhy(pQueueCtrl, pTxBuf); -+ } -+ else -+ { -+ /* Flash Buffer */ -+#ifdef MV_NETBSD -+ pTxCurrDesc->bufPtr = pBufInfo[bufCount].bufPhysAddr; -+ ETH_PACKET_CACHE_FLUSH(pBufInfo[bufCount].bufVirtPtr, pBufInfo[bufCount].dataSize); -+#else -+ pTxCurrDesc->bufPtr = ETH_PACKET_CACHE_FLUSH(pBufInfo[bufCount].bufVirtPtr, pBufInfo[bufCount].dataSize); -+#endif -+ } -+ -+ pTxCurrDesc->byteCnt = pBufInfo[bufCount].dataSize; -+ bufCount++; -+ -+ if(bufCount >= pPktInfo->numFrags) -+ break; -+ -+ if(bufCount > 1) -+ { -+ /* There is middle buffer of the packet Not First and Not Last */ -+ pTxCurrDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA; -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); -+ } -+ /* Go to next descriptor and next buffer */ -+ pTxCurrDesc = TX_NEXT_DESC_PTR(pTxCurrDesc, pQueueCtrl); -+ } -+ /* Set last desc with DMA ownership and interrupt enable. */ -+ pTxCurrDesc->returnInfo = (MV_ULONG)pPktInfo; -+ if(bufCount == 1) -+ { -+ /* There is only one buffer in the packet */ -+ /* The OSG might set some bits for checksum offload, so add them to first descriptor */ -+ pTxCurrDesc->cmdSts = pPktInfo->status | -+ ETH_BUFFER_OWNED_BY_DMA | -+ ETH_TX_GENERATE_CRC_MASK | -+ ETH_TX_ENABLE_INTERRUPT_MASK | -+ ETH_TX_ZERO_PADDING_MASK | -+ ETH_TX_FIRST_DESC_MASK | -+ ETH_TX_LAST_DESC_MASK; -+ -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); -+ } -+ else -+ { -+ /* Last but not First */ -+ pTxCurrDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA | -+ ETH_TX_ENABLE_INTERRUPT_MASK | -+ ETH_TX_ZERO_PADDING_MASK | -+ ETH_TX_LAST_DESC_MASK; -+ -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); -+ -+ /* Update First when more than one buffer in the packet */ -+ /* The OSG might set some bits for checksum offload, so add them to first descriptor */ -+ pTxFirstDesc->cmdSts = pPktInfo->status | -+ ETH_BUFFER_OWNED_BY_DMA | -+ ETH_TX_GENERATE_CRC_MASK | -+ ETH_TX_FIRST_DESC_MASK; -+ -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxFirstDesc); -+ } -+ /* Update txQueue state */ -+ pQueueCtrl->resource -= bufCount; -+ pQueueCtrl->pCurrentDescr = TX_NEXT_DESC_PTR(pTxCurrDesc, pQueueCtrl); -+ -+ /* Apply send command */ -+ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(portNo)) = pPortCtrl->portTxQueueCmdReg; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthPortTxDone - Free all used Tx descriptors and mBlks. -+* -+* DESCRIPTION: -+* This routine returns the transmitted packet information to the caller. -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet Port handler. -+* int txQueue - Number of Tx queue. -+* -+* OUTPUT: -+* MV_PKT_INFO *pPktInfo - Pointer to packet was sent. -+* -+* RETURN: -+* MV_NOT_FOUND - No transmitted packets to return. Transmit in progress. -+* MV_EMPTY - No transmitted packets to return. TX Queue is empty. -+* MV_ERROR - Unexpected Fatal error. -+* MV_OK - There is transmitted packet in the queue, -+* 'pPktInfo' filled with relevant information. -+* -+*******************************************************************************/ -+static INLINE MV_PKT_INFO* mvEthPortTxDone(void* pEthPortHndl, int txQueue) -+{ -+ ETH_TX_DESC* pTxCurrDesc; -+ ETH_TX_DESC* pTxUsedDesc; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ MV_PKT_INFO* pPktInfo; -+ MV_U32 commandStatus; -+ -+ pQueueCtrl = &pPortCtrl->txQueue[txQueue]; -+ -+ pTxUsedDesc = pQueueCtrl->pUsedDescr; -+ pTxCurrDesc = pQueueCtrl->pCurrentDescr; -+ -+ while(MV_TRUE) -+ { -+ /* No more used descriptors */ -+ commandStatus = pTxUsedDesc->cmdSts; -+ if (commandStatus & (ETH_BUFFER_OWNED_BY_DMA)) -+ { -+ ETH_DESCR_INV(pPortCtrl, pTxUsedDesc); -+ return NULL; -+ } -+ if( (pTxUsedDesc == pTxCurrDesc) && -+ (pQueueCtrl->resource != 0) ) -+ { -+ return NULL; -+ } -+ pQueueCtrl->resource++; -+ pQueueCtrl->pUsedDescr = TX_NEXT_DESC_PTR(pTxUsedDesc, pQueueCtrl); -+ if(commandStatus & (ETH_TX_LAST_DESC_MASK)) -+ { -+ pPktInfo = (MV_PKT_INFO*)pTxUsedDesc->returnInfo; -+ pPktInfo->status = commandStatus; -+ return pPktInfo; -+ } -+ pTxUsedDesc = pQueueCtrl->pUsedDescr; -+ } -+} -+ -+/******************************************************************************* -+* mvEthPortRx - Get new received packets from Rx queue. -+* -+* DESCRIPTION: -+* This routine returns the received data to the caller. There is no -+* data copying during routine operation. All information is returned -+* using pointer to packet information struct passed from the caller. -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet Port handler. -+* int rxQueue - Number of Rx queue. -+* -+* OUTPUT: -+* MV_PKT_INFO *pPktInfo - Pointer to received packet. -+* -+* RETURN: -+* MV_NO_RESOURCE - No free resources in RX queue. -+* MV_ERROR - Unexpected Fatal error. -+* MV_OK - New packet received and 'pBufInfo' structure filled -+* with relevant information. -+* -+*******************************************************************************/ -+static INLINE MV_PKT_INFO* mvEthPortRx(void* pEthPortHndl, int rxQueue) -+{ -+ ETH_RX_DESC *pRxCurrDesc; -+ MV_U32 commandStatus; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ MV_PKT_INFO* pPktInfo; -+ -+ pQueueCtrl = &(pPortCtrl->rxQueue[rxQueue]); -+ -+ /* Check resources */ -+ if(pQueueCtrl->resource == 0) -+ { -+ mvOsPrintf("ethPortRx: no more resources\n"); -+ return NULL; -+ } -+ while(MV_TRUE) -+ { -+ /* Get the Rx Desc ring 'curr and 'used' indexes */ -+ pRxCurrDesc = pQueueCtrl->pCurrentDescr; -+ -+ commandStatus = pRxCurrDesc->cmdSts; -+ if (commandStatus & (ETH_BUFFER_OWNED_BY_DMA)) -+ { -+ /* Nothing to receive... */ -+ ETH_DESCR_INV(pPortCtrl, pRxCurrDesc); -+ return NULL; -+ } -+ -+ /* Valid RX only if FIRST and LAST bits are set */ -+ if( (commandStatus & (ETH_RX_LAST_DESC_MASK | ETH_RX_FIRST_DESC_MASK)) == -+ (ETH_RX_LAST_DESC_MASK | ETH_RX_FIRST_DESC_MASK) ) -+ { -+ pPktInfo = (MV_PKT_INFO*)pRxCurrDesc->returnInfo; -+ pPktInfo->pFrags->dataSize = pRxCurrDesc->byteCnt - 4; -+ pPktInfo->status = commandStatus; -+ pPktInfo->fragIP = pRxCurrDesc->bufSize & ETH_RX_IP_FRAGMENTED_FRAME_MASK; -+ -+ pQueueCtrl->resource--; -+ /* Update 'curr' in data structure */ -+ pQueueCtrl->pCurrentDescr = RX_NEXT_DESC_PTR(pRxCurrDesc, pQueueCtrl); -+ -+#ifdef INCLUDE_SYNC_BARR -+ mvCpuIfSyncBarr(DRAM_TARGET); -+#endif -+ return pPktInfo; -+ } -+ else -+ { -+ ETH_RX_DESC* pRxUsedDesc = pQueueCtrl->pUsedDescr; -+ -+#ifdef ETH_DEBUG -+ mvOsPrintf("ethDrv: Unexpected Jumbo frame: " -+ "status=0x%08x, byteCnt=%d, pData=0x%x\n", -+ commandStatus, pRxCurrDesc->byteCnt, pRxCurrDesc->bufPtr); -+#endif /* ETH_DEBUG */ -+ -+ /* move buffer from pCurrentDescr position to pUsedDescr position */ -+ pRxUsedDesc->bufPtr = pRxCurrDesc->bufPtr; -+ pRxUsedDesc->returnInfo = pRxCurrDesc->returnInfo; -+ pRxUsedDesc->bufSize = pRxCurrDesc->bufSize & ETH_RX_BUFFER_MASK; -+ -+ /* Return the descriptor to DMA ownership */ -+ pRxUsedDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA | -+ ETH_RX_ENABLE_INTERRUPT_MASK; -+ -+ /* Flush descriptor and CPU pipe */ -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxUsedDesc); -+ -+ /* Move the used descriptor pointer to the next descriptor */ -+ pQueueCtrl->pUsedDescr = RX_NEXT_DESC_PTR(pRxUsedDesc, pQueueCtrl); -+ pQueueCtrl->pCurrentDescr = RX_NEXT_DESC_PTR(pRxCurrDesc, pQueueCtrl); -+ } -+ } -+} -+ -+/******************************************************************************* -+* mvEthPortRxDone - Returns a Rx buffer back to the Rx ring. -+* -+* DESCRIPTION: -+* This routine returns a Rx buffer back to the Rx ring. -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet Port handler. -+* int rxQueue - Number of Rx queue. -+* MV_PKT_INFO *pPktInfo - Pointer to received packet. -+* -+* RETURN: -+* MV_ERROR - Unexpected Fatal error. -+* MV_OUT_OF_RANGE - RX queue is already FULL, so this buffer can't be -+* returned to this queue. -+* MV_FULL - Buffer returned successfully and RX queue became full. -+* More buffers should not be returned at the time. -+* MV_OK - Buffer returned successfully and there are more free -+* places in the queue. -+* -+*******************************************************************************/ -+static INLINE MV_STATUS mvEthPortRxDone(void* pEthPortHndl, int rxQueue, MV_PKT_INFO *pPktInfo) -+{ -+ ETH_RX_DESC* pRxUsedDesc; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ -+ pQueueCtrl = &pPortCtrl->rxQueue[rxQueue]; -+ -+ /* Get 'used' Rx descriptor */ -+ pRxUsedDesc = pQueueCtrl->pUsedDescr; -+ -+ /* Check that ring is not FULL */ -+ if( (pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) && -+ (pQueueCtrl->resource != 0) ) -+ { -+ mvOsPrintf("%s %d: out of range Error resource=%d, curr=%p, used=%p\n", -+ __FUNCTION__, pPortCtrl->portNo, pQueueCtrl->resource, -+ pQueueCtrl->pCurrentDescr, pQueueCtrl->pUsedDescr); -+ return MV_OUT_OF_RANGE; -+ } -+ -+ pRxUsedDesc->bufPtr = pPktInfo->pFrags->bufPhysAddr; -+ pRxUsedDesc->returnInfo = (MV_ULONG)pPktInfo; -+ pRxUsedDesc->bufSize = pPktInfo->pFrags->bufSize & ETH_RX_BUFFER_MASK; -+ -+ /* Invalidate data buffer accordingly with pktSize */ -+ if(pPktInfo->pktSize != 0) -+ { -+ ETH_PACKET_CACHE_INVALIDATE(pPktInfo->pFrags->bufVirtPtr, pPktInfo->pktSize); -+ pPktInfo->pktSize = 0; -+ } -+ -+ /* Return the descriptor to DMA ownership */ -+ pRxUsedDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT_MASK; -+ -+ /* Flush descriptor and CPU pipe */ -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxUsedDesc); -+ -+ pQueueCtrl->resource++; -+ -+ /* Move the used descriptor pointer to the next descriptor */ -+ pQueueCtrl->pUsedDescr = RX_NEXT_DESC_PTR(pRxUsedDesc, pQueueCtrl); -+ -+ /* If ring became Full return MV_FULL */ -+ if(pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) -+ return MV_FULL; -+ -+ return MV_OK; -+} -+ -+ -+#endif /* __mvEthGbe_h__ */ -+ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h 2010-11-09 20:28:11.192495435 +0100 -@@ -0,0 +1,700 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvEthRegsh -+#define __INCmvEthRegsh -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+ -+/****************************************/ -+/* Ethernet Unit Registers */ -+/****************************************/ -+#define ETH_REG_BASE MV_ETH_REG_BASE -+ -+#define ETH_PHY_ADDR_REG(port) (ETH_REG_BASE(port) + 0x000) -+#define ETH_SMI_REG(port) (ETH_REG_BASE(port) + 0x004) -+#define ETH_UNIT_DEF_ADDR_REG(port) (ETH_REG_BASE(port) + 0x008) -+#define ETH_UNIT_DEF_ID_REG(port) (ETH_REG_BASE(port) + 0x00c) -+#define ETH_UNIT_RESERVED(port) (ETH_REG_BASE(port) + 0x014) -+#define ETH_UNIT_INTR_CAUSE_REG(port) (ETH_REG_BASE(port) + 0x080) -+#define ETH_UNIT_INTR_MASK_REG(port) (ETH_REG_BASE(port) + 0x084) -+ -+ -+#define ETH_UNIT_ERROR_ADDR_REG(port) (ETH_REG_BASE(port) + 0x094) -+#define ETH_UNIT_INT_ADDR_ERROR_REG(port) (ETH_REG_BASE(port) + 0x098) -+#define ETH_UNIT_CONTROL_REG(port) (ETH_REG_BASE(port) + 0x0B0) -+ -+#define ETH_PORT_CONFIG_REG(port) (ETH_REG_BASE(port) + 0x400) -+#define ETH_PORT_CONFIG_EXTEND_REG(port) (ETH_REG_BASE(port) + 0x404) -+#define ETH_MII_SERIAL_PARAM_REG(port) (ETH_REG_BASE(port) + 0x408) -+#define ETH_GMII_SERIAL_PARAM_REG(port) (ETH_REG_BASE(port) + 0x40c) -+#define ETH_VLAN_ETHER_TYPE_REG(port) (ETH_REG_BASE(port) + 0x410) -+#define ETH_MAC_ADDR_LOW_REG(port) (ETH_REG_BASE(port) + 0x414) -+#define ETH_MAC_ADDR_HIGH_REG(port) (ETH_REG_BASE(port) + 0x418) -+#define ETH_SDMA_CONFIG_REG(port) (ETH_REG_BASE(port) + 0x41c) -+#define ETH_DIFF_SERV_PRIO_REG(port, code) (ETH_REG_BASE(port) + 0x420 + ((code)<<2)) -+#define ETH_PORT_SERIAL_CTRL_REG(port) (ETH_REG_BASE(port) + 0x43c) -+#define ETH_VLAN_TAG_TO_PRIO_REG(port) (ETH_REG_BASE(port) + 0x440) -+#define ETH_PORT_STATUS_REG(port) (ETH_REG_BASE(port) + 0x444) -+ -+#define ETH_RX_QUEUE_COMMAND_REG(port) (ETH_REG_BASE(port) + 0x680) -+#define ETH_TX_QUEUE_COMMAND_REG(port) (ETH_REG_BASE(port) + 0x448) -+ -+#define ETH_PORT_SERIAL_CTRL_1_REG(port) (ETH_REG_BASE(port) + 0x44c) -+#define ETH_PORT_STATUS_1_REG(port) (ETH_REG_BASE(port) + 0x450) -+#define ETH_PORT_MARVELL_HEADER_REG(port) (ETH_REG_BASE(port) + 0x454) -+#define ETH_PORT_FIFO_PARAMS_REG(port) (ETH_REG_BASE(port) + 0x458) -+#define ETH_MAX_TOKEN_BUCKET_SIZE_REG(port) (ETH_REG_BASE(port) + 0x45c) -+#define ETH_INTR_CAUSE_REG(port) (ETH_REG_BASE(port) + 0x460) -+#define ETH_INTR_CAUSE_EXT_REG(port) (ETH_REG_BASE(port) + 0x464) -+#define ETH_INTR_MASK_REG(port) (ETH_REG_BASE(port) + 0x468) -+#define ETH_INTR_MASK_EXT_REG(port) (ETH_REG_BASE(port) + 0x46c) -+#define ETH_TX_FIFO_URGENT_THRESH_REG(port) (ETH_REG_BASE(port) + 0x474) -+#define ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (ETH_REG_BASE(port) + 0x47c) -+#define ETH_RX_DISCARD_PKTS_CNTR_REG(port) (ETH_REG_BASE(port) + 0x484) -+#define ETH_RX_OVERRUN_PKTS_CNTR_REG(port) (ETH_REG_BASE(port) + 0x488) -+#define ETH_INTERNAL_ADDR_ERROR_REG(port) (ETH_REG_BASE(port) + 0x494) -+#define ETH_TX_FIXED_PRIO_CFG_REG(port) (ETH_REG_BASE(port) + 0x4dc) -+#define ETH_TX_TOKEN_RATE_CFG_REG(port) (ETH_REG_BASE(port) + 0x4e0) -+#define ETH_TX_QUEUE_COMMAND1_REG(port) (ETH_REG_BASE(port) + 0x4e4) -+#define ETH_MAX_TRANSMIT_UNIT_REG(port) (ETH_REG_BASE(port) + 0x4e8) -+#define ETH_TX_TOKEN_BUCKET_SIZE_REG(port) (ETH_REG_BASE(port) + 0x4ec) -+#define ETH_TX_TOKEN_BUCKET_COUNT_REG(port) (ETH_REG_BASE(port) + 0x780) -+#define ETH_RX_DESCR_STAT_CMD_REG(port, q) (ETH_REG_BASE(port) + 0x600 + ((q)<<4)) -+#define ETH_RX_BYTE_COUNT_REG(port, q) (ETH_REG_BASE(port) + 0x604 + ((q)<<4)) -+#define ETH_RX_BUF_PTR_REG(port, q) (ETH_REG_BASE(port) + 0x608 + ((q)<<4)) -+#define ETH_RX_CUR_DESC_PTR_REG(port, q) (ETH_REG_BASE(port) + 0x60c + ((q)<<4)) -+#define ETH_TX_CUR_DESC_PTR_REG(port, q) (ETH_REG_BASE(port) + 0x6c0 + ((q)<<2)) -+ -+#define ETH_TXQ_TOKEN_COUNT_REG(port, q) (ETH_REG_BASE(port) + 0x700 + ((q)<<4)) -+#define ETH_TXQ_TOKEN_CFG_REG(port, q) (ETH_REG_BASE(port) + 0x704 + ((q)<<4)) -+#define ETH_TXQ_ARBITER_CFG_REG(port, q) (ETH_REG_BASE(port) + 0x708 + ((q)<<4)) -+ -+#if (MV_ETH_VERSION >= 4) -+#define ETH_TXQ_CMD_1_REG(port) (ETH_REG_BASE(port) + 0x4E4) -+#define ETH_EJP_TX_HI_IPG_REG(port) (ETH_REG_BASE(port) + 0x7A8) -+#define ETH_EJP_TX_LO_IPG_REG(port) (ETH_REG_BASE(port) + 0x7B8) -+#define ETH_EJP_HI_TKN_LO_PKT_REG(port) (ETH_REG_BASE(port) + 0x7C0) -+#define ETH_EJP_HI_TKN_ASYNC_PKT_REG(port) (ETH_REG_BASE(port) + 0x7C4) -+#define ETH_EJP_LO_TKN_ASYNC_PKT_REG(port) (ETH_REG_BASE(port) + 0x7C8) -+#define ETH_EJP_TX_SPEED_REG(port) (ETH_REG_BASE(port) + 0x7D0) -+#endif /* MV_ETH_VERSION >= 4 */ -+ -+#define ETH_MIB_COUNTERS_BASE(port) (ETH_REG_BASE(port) + 0x1000) -+#define ETH_DA_FILTER_SPEC_MCAST_BASE(port) (ETH_REG_BASE(port) + 0x1400) -+#define ETH_DA_FILTER_OTH_MCAST_BASE(port) (ETH_REG_BASE(port) + 0x1500) -+#define ETH_DA_FILTER_UCAST_BASE(port) (ETH_REG_BASE(port) + 0x1600) -+ -+/* Phy address register definitions */ -+#define ETH_PHY_ADDR_OFFS 0 -+#define ETH_PHY_ADDR_MASK (0x1f <= 4) -+#define ETH_TX_EJP_RESET_BIT 0 -+#define ETH_TX_EJP_RESET_MASK (1 << ETH_TX_EJP_RESET_BIT) -+ -+#define ETH_TX_EJP_ENABLE_BIT 2 -+#define ETH_TX_EJP_ENABLE_MASK (1 << ETH_TX_EJP_ENABLE_BIT) -+ -+#define ETH_TX_LEGACY_WRR_BIT 3 -+#define ETH_TX_LEGACY_WRR_MASK (1 << ETH_TX_LEGACY_WRR_BIT) -+#endif /* (MV_ETH_VERSION >= 4) */ -+ -+/***** BITs of Ethernet Port Status reg (PSR) *****/ -+#define ETH_LINK_UP_BIT 1 -+#define ETH_LINK_UP_MASK (1<= 4) -+MV_STATUS mvEthEjpModeSet(void* pPortHandle, int mode); -+#endif /* (MV_ETH_VERSION >= 4) */ -+ -+void mvEthStatusGet(void* pPortHandle, MV_ETH_PORT_STATUS* pStatus); -+ -+/* Marvell Header control */ -+MV_STATUS mvEthHeaderModeSet(void* pPortHandle, MV_ETH_HEADER_MODE headerMode); -+ -+/* PHY routines */ -+void mvEthPhyAddrSet(void* pPortHandle, int phyAddr); -+int mvEthPhyAddrGet(void* pPortHandle); -+ -+/* Power management routines */ -+void mvEthPortPowerDown(int port); -+void mvEthPortPowerUp(int port); -+ -+/******************** ETH PRIVATE ************************/ -+ -+/*#define UNCACHED_TX_BUFFERS*/ -+/*#define UNCACHED_RX_BUFFERS*/ -+ -+ -+/* Port attributes */ -+/* Size of a Tx/Rx descriptor used in chain list data structure */ -+#define ETH_RX_DESC_ALIGNED_SIZE 32 -+#define ETH_TX_DESC_ALIGNED_SIZE 32 -+ -+#define TX_DISABLE_TIMEOUT_MSEC 1000 -+#define RX_DISABLE_TIMEOUT_MSEC 1000 -+#define TX_FIFO_EMPTY_TIMEOUT_MSEC 10000 -+#define PORT_DISABLE_WAIT_TCLOCKS 5000 -+ -+/* Macros that save access to desc in order to find next desc pointer */ -+#define RX_NEXT_DESC_PTR(pRxDescr, pQueueCtrl) \ -+ ((pRxDescr) == (pQueueCtrl)->pLastDescr) ? \ -+ (ETH_RX_DESC*)((pQueueCtrl)->pFirstDescr) : \ -+ (ETH_RX_DESC*)(((MV_ULONG)(pRxDescr)) + ETH_RX_DESC_ALIGNED_SIZE) -+ -+#define TX_NEXT_DESC_PTR(pTxDescr, pQueueCtrl) \ -+ ((pTxDescr) == (pQueueCtrl)->pLastDescr) ? \ -+ (ETH_TX_DESC*)((pQueueCtrl)->pFirstDescr) : \ -+ (ETH_TX_DESC*)(((MV_ULONG)(pTxDescr)) + ETH_TX_DESC_ALIGNED_SIZE) -+ -+#define RX_PREV_DESC_PTR(pRxDescr, pQueueCtrl) \ -+ ((pRxDescr) == (pQueueCtrl)->pFirstDescr) ? \ -+ (ETH_RX_DESC*)((pQueueCtrl)->pLastDescr) : \ -+ (ETH_RX_DESC*)(((MV_ULONG)(pRxDescr)) - ETH_RX_DESC_ALIGNED_SIZE) -+ -+#define TX_PREV_DESC_PTR(pTxDescr, pQueueCtrl) \ -+ ((pTxDescr) == (pQueueCtrl)->pFirstDescr) ? \ -+ (ETH_TX_DESC*)((pQueueCtrl)->pLastDescr) : \ -+ (ETH_TX_DESC*)(((MV_ULONG)(pTxDescr)) - ETH_TX_DESC_ALIGNED_SIZE) -+ -+ -+/* Queue specific information */ -+typedef struct -+{ -+ void* pFirstDescr; -+ void* pLastDescr; -+ void* pCurrentDescr; -+ void* pUsedDescr; -+ int resource; -+ MV_BUF_INFO descBuf; -+} ETH_QUEUE_CTRL; -+ -+ -+/* Ethernet port specific infomation */ -+typedef struct _ethPortCtrl -+{ -+ int portNo; -+ ETH_QUEUE_CTRL rxQueue[MV_ETH_RX_Q_NUM]; /* Rx ring resource */ -+ ETH_QUEUE_CTRL txQueue[MV_ETH_TX_Q_NUM]; /* Tx ring resource */ -+ -+ MV_ETH_PORT_CFG portConfig; -+ MV_ETH_RX_Q_CFG rxQueueConfig[MV_ETH_RX_Q_NUM]; -+ MV_ETH_TX_Q_CFG txQueueConfig[MV_ETH_TX_Q_NUM]; -+ -+ /* Register images - For DP */ -+ MV_U32 portTxQueueCmdReg; /* Port active Tx queues summary */ -+ MV_U32 portRxQueueCmdReg; /* Port active Rx queues summary */ -+ -+ MV_STATE portState; -+ -+ MV_U8 mcastCount[256]; -+ MV_U32* hashPtr; -+ void *osHandle; -+} ETH_PORT_CTRL; -+ -+/************** MACROs ****************/ -+ -+/* MACROs to Flush / Invalidate TX / RX Buffers */ -+#if (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) && !defined(UNCACHED_TX_BUFFERS) -+# define ETH_PACKET_CACHE_FLUSH(pAddr, size) \ -+ mvOsCacheClear(NULL, (pAddr), (size)); \ -+ /*CPU_PIPE_FLUSH;*/ -+#else -+# define ETH_PACKET_CACHE_FLUSH(pAddr, size) \ -+ mvOsIoVirtToPhy(NULL, (pAddr)); -+#endif /* ETHER_DRAM_COHER == MV_CACHE_COHER_SW */ -+ -+#if ( (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) && !defined(UNCACHED_RX_BUFFERS) ) -+# define ETH_PACKET_CACHE_INVALIDATE(pAddr, size) \ -+ mvOsCacheInvalidate (NULL, (pAddr), (size)); \ -+ /*CPU_PIPE_FLUSH;*/ -+#else -+# define ETH_PACKET_CACHE_INVALIDATE(pAddr, size) -+#endif /* ETHER_DRAM_COHER == MV_CACHE_COHER_SW && !UNCACHED_RX_BUFFERS */ -+ -+#ifdef ETH_DESCR_UNCACHED -+ -+#define ETH_DESCR_FLUSH_INV(pPortCtrl, pDescr) -+#define ETH_DESCR_INV(pPortCtrl, pDescr) -+ -+#else -+ -+#define ETH_DESCR_FLUSH_INV(pPortCtrl, pDescr) \ -+ mvOsCacheLineFlushInv(pPortCtrl->osHandle, (MV_ULONG)(pDescr)) -+ -+#define ETH_DESCR_INV(pPortCtrl, pDescr) \ -+ mvOsCacheLineInv(pPortCtrl->osHandle, (MV_ULONG)(pDescr)) -+ -+#endif /* ETH_DESCR_UNCACHED */ -+ -+#include "eth/gbe/mvEthGbe.h" -+ -+#endif /* __mvEth_h__ */ -+ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.c 2010-11-09 20:28:11.262495582 +0100 -@@ -0,0 +1,362 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "gpp/mvGpp.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+static MV_VOID gppRegSet(MV_U32 group, MV_U32 regOffs,MV_U32 mask,MV_U32 value); -+ -+/******************************************************************************* -+* mvGppTypeSet - Enable a GPP (OUT) pin -+* -+* DESCRIPTION: -+* -+* INPUT: -+* group - GPP group number -+* mask - 32bit mask value. Each set bit in the mask means that the type -+* of corresponding GPP will be set. Other GPPs are ignored. -+* value - 32bit value that describes GPP type per pin. -+* -+* OUTPUT: -+* None. -+* -+* EXAMPLE: -+* Set GPP8 to input and GPP15 to output. -+* mvGppTypeSet(0, (GPP8 | GPP15), -+* ((MV_GPP_IN & GPP8) | (MV_GPP_OUT & GPP15)) ); -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvGppTypeSet(MV_U32 group, MV_U32 mask, MV_U32 value) -+{ -+ if (group >= MV_GPP_MAX_GROUP) -+ { -+ DB(mvOsPrintf("mvGppTypeSet: ERR. invalid group number \n")); -+ return MV_BAD_PARAM; -+ } -+ -+ gppRegSet(group, GPP_DATA_OUT_EN_REG(group), mask, value); -+ -+ /* Workaround for Erratum FE-MISC-70*/ -+ if(mvCtrlRevGet()==MV_88F6XXX_A0_REV && (group == 1)) -+ { -+ mask &= 0x2; -+ gppRegSet(0, GPP_DATA_OUT_EN_REG(0), mask, value); -+ } /*End of WA*/ -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvGppBlinkEn - Set a GPP (IN) Pin list to blink every ~100ms -+* -+* DESCRIPTION: -+* -+* INPUT: -+* group - GPP group number -+* mask - 32bit mask value. Each set bit in the mask means that the type -+* of corresponding GPP will be set. Other GPPs are ignored. -+* value - 32bit value that describes GPP blink per pin. -+* -+* OUTPUT: -+* None. -+* -+* EXAMPLE: -+* Set GPP8 to be static and GPP15 to be blinking. -+* mvGppBlinkEn(0, (GPP8 | GPP15), -+* ((MV_GPP_OUT_STATIC & GPP8) | (MV_GPP_OUT_BLINK & GPP15)) ); -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvGppBlinkEn(MV_U32 group, MV_U32 mask, MV_U32 value) -+{ -+ if (group >= MV_GPP_MAX_GROUP) -+ { -+ DB(mvOsPrintf("mvGppBlinkEn: ERR. invalid group number \n")); -+ return MV_BAD_PARAM; -+ } -+ -+ gppRegSet(group, GPP_BLINK_EN_REG(group), mask, value); -+ -+ return MV_OK; -+ -+} -+/******************************************************************************* -+* mvGppPolaritySet - Set a GPP (IN) Pin list Polarity mode -+* -+* DESCRIPTION: -+* -+* INPUT: -+* group - GPP group number -+* mask - 32bit mask value. Each set bit in the mask means that the type -+* of corresponding GPP will be set. Other GPPs are ignored. -+* value - 32bit value that describes GPP polarity per pin. -+* -+* OUTPUT: -+* None. -+* -+* EXAMPLE: -+* Set GPP8 to the actual pin value and GPP15 to be inverted. -+* mvGppPolaritySet(0, (GPP8 | GPP15), -+* ((MV_GPP_IN_ORIGIN & GPP8) | (MV_GPP_IN_INVERT & GPP15)) ); -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvGppPolaritySet(MV_U32 group, MV_U32 mask, MV_U32 value) -+{ -+ if (group >= MV_GPP_MAX_GROUP) -+ { -+ DB(mvOsPrintf("mvGppPolaritySet: ERR. invalid group number \n")); -+ return MV_BAD_PARAM; -+ } -+ -+ gppRegSet(group, GPP_DATA_IN_POL_REG(group), mask, value); -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvGppPolarityGet - Get a value of relevant bits from GPP Polarity register. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* group - GPP group number -+* mask - 32bit mask value. Each set bit in the mask means that the -+* returned value is valid for it. -+* -+* OUTPUT: -+* None. -+* -+* EXAMPLE: -+* Get GPP8 and GPP15 value. -+* mvGppPolarityGet(0, (GPP8 | GPP15)); -+* -+* RETURN: -+* 32bit value that describes GPP polatity mode per pin. -+* -+*******************************************************************************/ -+MV_U32 mvGppPolarityGet(MV_U32 group, MV_U32 mask) -+{ -+ MV_U32 regVal; -+ -+ if (group >= MV_GPP_MAX_GROUP) -+ { -+ DB(mvOsPrintf("mvGppActiveSet: Error invalid group number \n")); -+ return MV_ERROR; -+ } -+ regVal = MV_REG_READ(GPP_DATA_IN_POL_REG(group)); -+ -+ return (regVal & mask); -+} -+ -+/******************************************************************************* -+* mvGppValueGet - Get a GPP Pin list value. -+* -+* DESCRIPTION: -+* This function get GPP value. -+* -+* INPUT: -+* group - GPP group number -+* mask - 32bit mask value. Each set bit in the mask means that the -+* returned value is valid for it. -+* -+* OUTPUT: -+* None. -+* -+* EXAMPLE: -+* Get GPP8 and GPP15 value. -+* mvGppValueGet(0, (GPP8 | GPP15)); -+* -+* RETURN: -+* 32bit value that describes GPP activity mode per pin. -+* -+*******************************************************************************/ -+MV_U32 mvGppValueGet(MV_U32 group, MV_U32 mask) -+{ -+ MV_U32 gppData; -+ -+ gppData = MV_REG_READ(GPP_DATA_IN_REG(group)); -+ -+ gppData &= mask; -+ -+ return gppData; -+ -+} -+ -+/******************************************************************************* -+* mvGppValueSet - Set a GPP Pin list value. -+* -+* DESCRIPTION: -+* This function set value for given GPP pin list. -+* -+* INPUT: -+* group - GPP group number -+* mask - 32bit mask value. Each set bit in the mask means that the -+* value of corresponding GPP will be set accordingly. Other GPP -+* are not affected. -+* value - 32bit value that describes GPP value per pin. -+* -+* OUTPUT: -+* None. -+* -+* EXAMPLE: -+* Set GPP8 value of '0' and GPP15 value of '1'. -+* mvGppActiveSet(0, (GPP8 | GPP15), ((0 & GPP8) | (GPP15)) ); -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvGppValueSet (MV_U32 group, MV_U32 mask, MV_U32 value) -+{ -+ MV_U32 outEnable, tmp; -+ MV_U32 i; -+ -+ if (group >= MV_GPP_MAX_GROUP) -+ { -+ DB(mvOsPrintf("mvGppValueSet: Error invalid group number \n")); -+ return MV_BAD_PARAM; -+ } -+ -+ /* verify that the gpp pin is configured as output */ -+ /* Note that in the register out enabled -> bit = '0'. */ -+ outEnable = ~MV_REG_READ(GPP_DATA_OUT_EN_REG(group)); -+ -+ /* Workaround for Erratum FE-MISC-70*/ -+ if(mvCtrlRevGet()==MV_88F6XXX_A0_REV && (group == 1)) -+ { -+ tmp = ~MV_REG_READ(GPP_DATA_OUT_EN_REG(0)); -+ outEnable &= 0xfffffffd; -+ outEnable |= (tmp & 0x2); -+ } /*End of WA*/ -+ -+ for (i = 0 ; i < 32 ;i++) -+ { -+ if (((mask & (1 << i)) & (outEnable & (1 << i))) != (mask & (1 << i))) -+ { -+ mvOsPrintf("mvGppValueSet: Err. An attempt to set output "\ -+ "value to GPP %d in input mode.\n", i); -+ return MV_ERROR; -+ } -+ } -+ -+ gppRegSet(group, GPP_DATA_OUT_REG(group), mask, value); -+ -+ return MV_OK; -+ -+} -+/******************************************************************************* -+* gppRegSet - Set a specific GPP pin on a specific GPP register -+* -+* DESCRIPTION: -+* This function set a specific GPP pin on a specific GPP register -+* -+* INPUT: -+* regOffs - GPP Register offset -+* group - GPP group number -+* mask - 32bit mask value. Each set bit in the mask means that the -+* value of corresponding GPP will be set accordingly. Other GPP -+* are not affected. -+* value - 32bit value that describes GPP value per pin. -+* -+* OUTPUT: -+* None. -+* -+* EXAMPLE: -+* Set GPP8 value of '0' and GPP15 value of '1'. -+* mvGppActiveSet(0, (GPP8 | GPP15), ((0 & GPP8) | (1 & GPP15)) ); -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+static MV_VOID gppRegSet (MV_U32 group, MV_U32 regOffs,MV_U32 mask,MV_U32 value) -+{ -+ MV_U32 gppData; -+ -+ gppData = MV_REG_READ(regOffs); -+ -+ gppData &= ~mask; -+ -+ gppData |= (value & mask); -+ -+ MV_REG_WRITE(regOffs, gppData); -+} -+ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.h 2010-11-09 20:28:11.302495429 +0100 -@@ -0,0 +1,118 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvGppH -+#define __INCmvGppH -+ -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+#include "gpp/mvGppRegs.h" -+ -+/* These macros describes the GPP type. Each of the GPPs pins can */ -+/* be assigned to act as a general purpose input or output pin. */ -+#define MV_GPP_IN 0xFFFFFFFF /* GPP input */ -+#define MV_GPP_OUT 0 /* GPP output */ -+ -+ -+/* These macros describes the GPP Out Enable. */ -+#define MV_GPP_OUT_DIS 0xFFFFFFFF /* Out pin disabled*/ -+#define MV_GPP_OUT_EN 0 /* Out pin enabled*/ -+ -+/* These macros describes the GPP Out Blinking. */ -+/* When set and the corresponding bit in GPIO Data Out Enable Control */ -+/* Register is enabled, the GPIO pin blinks every ~100 ms (a period of */ -+/* 2^24 TCLK clocks). */ -+#define MV_GPP_OUT_BLINK 0xFFFFFFFF /* Out pin blinking*/ -+#define MV_GPP_OUT_STATIC 0 /* Out pin static*/ -+ -+ -+/* These macros describes the GPP Polarity. */ -+/* When set to 1 GPIO Data In Register reflects the inverted value of the */ -+/* corresponding pin. */ -+ -+#define MV_GPP_IN_INVERT 0xFFFFFFFF /* Inverted value is got*/ -+#define MV_GPP_IN_ORIGIN 0 /* original value is got*/ -+ -+/* mvGppTypeSet - Set PP pin mode (IN or OUT) */ -+MV_STATUS mvGppTypeSet(MV_U32 group, MV_U32 mask, MV_U32 value); -+ -+/* mvGppBlinkEn - Set a GPP (IN) Pin list to blink every ~100ms */ -+MV_STATUS mvGppBlinkEn(MV_U32 group, MV_U32 mask, MV_U32 value); -+ -+/* mvGppPolaritySet - Set a GPP (IN) Pin list Polarity mode. */ -+MV_STATUS mvGppPolaritySet(MV_U32 group, MV_U32 mask, MV_U32 value); -+ -+/* mvGppPolarityGet - Get the Polarity of a GPP Pin */ -+MV_U32 mvGppPolarityGet(MV_U32 group, MV_U32 mask); -+ -+/* mvGppValueGet - Get a GPP Pin list value.*/ -+MV_U32 mvGppValueGet(MV_U32 group, MV_U32 mask); -+ -+ -+/* mvGppValueSet - Set a GPP Pin list value. */ -+MV_STATUS mvGppValueSet (MV_U32 group, MV_U32 mask, MV_U32 value); -+ -+#endif /* #ifndef __INCmvGppH */ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGppRegs.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGppRegs.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGppRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGppRegs.h 2010-11-09 20:28:11.342495467 +0100 -@@ -0,0 +1,116 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvGppRegsH -+#define __INCmvGppRegsH -+ -+#define MV_GPP0 BIT0 -+#define MV_GPP1 BIT1 -+#define MV_GPP2 BIT2 -+#define MV_GPP3 BIT3 -+#define MV_GPP4 BIT4 -+#define MV_GPP5 BIT5 -+#define MV_GPP6 BIT6 -+#define MV_GPP7 BIT7 -+#define MV_GPP8 BIT8 -+#define MV_GPP9 BIT9 -+#define MV_GPP10 BIT10 -+#define MV_GPP11 BIT11 -+#define MV_GPP12 BIT12 -+#define MV_GPP13 BIT13 -+#define MV_GPP14 BIT14 -+#define MV_GPP15 BIT15 -+#define MV_GPP16 BIT16 -+#define MV_GPP17 BIT17 -+#define MV_GPP18 BIT18 -+#define MV_GPP19 BIT19 -+#define MV_GPP20 BIT20 -+#define MV_GPP21 BIT21 -+#define MV_GPP22 BIT22 -+#define MV_GPP23 BIT23 -+#define MV_GPP24 BIT24 -+#define MV_GPP25 BIT25 -+#define MV_GPP26 BIT26 -+#define MV_GPP27 BIT27 -+#define MV_GPP28 BIT28 -+#define MV_GPP29 BIT29 -+#define MV_GPP30 BIT30 -+#define MV_GPP31 BIT31 -+ -+ -+/* registers offsets */ -+ -+#define GPP_DATA_OUT_REG(grp) ((grp == 0) ? 0x10100 : 0x10140) -+#define GPP_DATA_OUT_EN_REG(grp) ((grp == 0) ? 0x10104 : 0x10144) -+#define GPP_BLINK_EN_REG(grp) ((grp == 0) ? 0x10108 : 0x10148) -+#define GPP_DATA_IN_POL_REG(grp) ((grp == 0) ? 0x1010C : 0x1014c) -+#define GPP_DATA_IN_REG(grp) ((grp == 0) ? 0x10110 : 0x10150) -+#define GPP_INT_CAUSE_REG(grp) ((grp == 0) ? 0x10114 : 0x10154) -+#define GPP_INT_MASK_REG(grp) ((grp == 0) ? 0x10118 : 0x10158) -+#define GPP_INT_LVL_REG(grp) ((grp == 0) ? 0x1011c : 0x1015c) -+ -+#define GPP_DATA_OUT_SET_REG 0x10120 -+#define GPP_DATA_OUT_CLEAR_REG 0x10124 -+ -+#endif /* #ifndef __INCmvGppRegsH */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.c 2010-11-09 20:28:11.372495482 +0100 -@@ -0,0 +1,1047 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#include "pci/mvPci.h" -+ -+#include "ctrlEnv/mvCtrlEnvLib.h" -+ -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+ -+ -+MV_VOID mvPciHalInit(MV_U32 pciIf, MV_PCI_MOD pciIfmod) -+{ -+ if (MV_PCI_MOD_HOST == pciIfmod) -+ { -+ -+ mvPciLocalBusNumSet(pciIf, PCI_HOST_BUS_NUM(pciIf)); -+ mvPciLocalDevNumSet(pciIf, PCI_HOST_DEV_NUM(pciIf)); -+ -+ /* Local device master Enable */ -+ mvPciMasterEnable(pciIf, MV_TRUE); -+ -+ /* Local device slave Enable */ -+ mvPciSlaveEnable(pciIf, mvPciLocalBusNumGet(pciIf), -+ mvPciLocalDevNumGet(pciIf), MV_TRUE); -+ } -+ /* enable CPU-2-PCI ordering */ -+ MV_REG_BIT_SET(PCI_CMD_REG(0), PCR_CPU_TO_PCI_ORDER_EN); -+} -+ -+/******************************************************************************* -+* mvPciCommandSet - Set PCI comman register value. -+* -+* DESCRIPTION: -+* This function sets a given PCI interface with its command register -+* value. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* command - 32bit value to be written to comamnd register. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM if pciIf is not in range otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciCommandSet(MV_U32 pciIf, MV_U32 command) -+{ -+ MV_U32 locBusNum, locDevNum, regVal; -+ -+ locBusNum = mvPciLocalBusNumGet(pciIf); -+ locDevNum = mvPciLocalDevNumGet(pciIf); -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciCommandSet: ERR. Invalid PCI IF num %d\n", pciIf); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Set command register */ -+ MV_REG_WRITE(PCI_CMD_REG(pciIf), command); -+ -+ /* Upodate device max outstanding split tarnsaction */ -+ if ((command & PCR_CPU_TO_PCI_ORDER_EN) && -+ (command & PCR_PCI_TO_CPU_ORDER_EN)) -+ { -+ /* Read PCI-X command register */ -+ regVal = mvPciConfigRead (pciIf, locBusNum, locDevNum, 0, PCIX_COMMAND); -+ -+ /* clear bits 22:20 */ -+ regVal &= 0xff8fffff; -+ -+ /* set reset value */ -+ regVal |= (0x3 << 20); -+ -+ /* Write back the value */ -+ mvPciConfigWrite (pciIf, locBusNum, locDevNum, 0, PCIX_COMMAND, regVal); -+ } -+ -+ return MV_OK; -+ -+ -+} -+ -+ -+/******************************************************************************* -+* mvPciModeGet - Get PCI interface mode. -+* -+* DESCRIPTION: -+* This function returns the given PCI interface mode. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* -+* OUTPUT: -+* pPciMode - Pointer to PCI mode structure. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciModeGet(MV_U32 pciIf, MV_PCI_MODE *pPciMode) -+{ -+ MV_U32 pciMode; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciModeGet: ERR. Invalid PCI interface %d\n", pciIf); -+ return MV_BAD_PARAM; -+ } -+ if (NULL == pPciMode) -+ { -+ mvOsPrintf("mvPciModeGet: ERR. pPciMode = NULL \n"); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Read pci mode register */ -+ pciMode = MV_REG_READ(PCI_MODE_REG(pciIf)); -+ -+ switch (pciMode & PMR_PCI_MODE_MASK) -+ { -+ case PMR_PCI_MODE_CONV: -+ pPciMode->pciType = MV_PCI_CONV; -+ -+ if (MV_REG_READ(PCI_DLL_CTRL_REG(pciIf)) & PDC_DLL_EN) -+ { -+ pPciMode->pciSpeed = 66000000; /* 66MHZ */ -+ } -+ else -+ { -+ pPciMode->pciSpeed = 33000000; /* 33MHZ */ -+ } -+ -+ break; -+ -+ case PMR_PCI_MODE_PCIX_66MHZ: -+ pPciMode->pciType = MV_PCIX; -+ pPciMode->pciSpeed = 66000000; /* 66MHZ */ -+ break; -+ -+ case PMR_PCI_MODE_PCIX_100MHZ: -+ pPciMode->pciType = MV_PCIX; -+ pPciMode->pciSpeed = 100000000; /* 100MHZ */ -+ break; -+ -+ case PMR_PCI_MODE_PCIX_133MHZ: -+ pPciMode->pciType = MV_PCIX; -+ pPciMode->pciSpeed = 133000000; /* 133MHZ */ -+ break; -+ -+ default: -+ { -+ mvOsPrintf("mvPciModeGet: ERR. Non existing mode !!\n"); -+ return MV_ERROR; -+ } -+ } -+ -+ switch (pciMode & PMR_PCI_64_MASK) -+ { -+ case PMR_PCI_64_64BIT: -+ pPciMode->pciWidth = MV_PCI_64; -+ break; -+ -+ case PMR_PCI_64_32BIT: -+ pPciMode->pciWidth = MV_PCI_32; -+ break; -+ -+ default: -+ { -+ mvOsPrintf("mvPciModeGet: ERR. Non existing mode !!\n"); -+ return MV_ERROR; -+ } -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvPciRetrySet - Set PCI retry counters -+* -+* DESCRIPTION: -+* This function specifies the number of times the PCI controller -+* retries a transaction before it quits. -+* Applies to the PCI Master when acting as a requester. -+* Applies to the PCI slave when acting as a completer (PCI-X mode). -+* A 0x00 value means a "retry forever". -+* -+* INPUT: -+* pciIf - PCI interface number. -+* counter - Number of times PCI controller retry. Use counter value -+* up to PRR_RETRY_CNTR_MAX. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciRetrySet(MV_U32 pciIf, MV_U32 counter) -+{ -+ MV_U32 pciRetry; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciRetrySet: ERR. Invalid PCI interface %d\n", pciIf); -+ return MV_BAD_PARAM; -+ } -+ -+ if (counter >= PRR_RETRY_CNTR_MAX) -+ { -+ mvOsPrintf("mvPciRetrySet: ERR. Invalid counter: %d\n", counter); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ /* Reading PCI retry register */ -+ pciRetry = MV_REG_READ(PCI_RETRY_REG(pciIf)); -+ -+ pciRetry &= ~PRR_RETRY_CNTR_MASK; -+ -+ pciRetry |= (counter << PRR_RETRY_CNTR_OFFS); -+ -+ /* write new value */ -+ MV_REG_WRITE(PCI_RETRY_REG(pciIf), pciRetry); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPciDiscardTimerSet - Set PCI discard timer -+* -+* DESCRIPTION: -+* This function set PCI discard timer. -+* In conventional PCI mode: -+* Specifies the number of PCLK cycles the PCI slave keeps a non-accessed -+* read buffers (non-completed delayed read) before invalidate the buffer. -+* Set to '0' to disable the timer. The PCI slave waits for delayed -+* read completion forever. -+* In PCI-X mode: -+* Specifies the number of PCLK cycles the PCI master waits for split -+* completion transaction, before it invalidates the pre-allocated read -+* buffer. -+* Set to '0' to disable the timer. The PCI master waits for split -+* completion forever. -+* NOTE: Must be set to a number greater than MV_PCI_MAX_DISCARD_CLK, -+* unless using the "wait for ever" setting 0x0. -+* NOTE: Must not be updated while there are pending read requests. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* pClkCycles - Number of PCI clock cycles. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciDiscardTimerSet(MV_U32 pciIf, MV_U32 pClkCycles) -+{ -+ MV_U32 pciDiscardTimer; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciDiscardTimerSet: ERR. Invalid PCI interface %d\n", -+ pciIf); -+ return MV_BAD_PARAM; -+ } -+ -+ if (pClkCycles >= PDTR_TIMER_MIN) -+ { -+ mvOsPrintf("mvPciDiscardTimerSet: ERR. Invalid Clk value: %d\n", -+ pClkCycles); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ /* Read PCI Discard Timer */ -+ pciDiscardTimer = MV_REG_READ(PCI_DISCARD_TIMER_REG(pciIf)); -+ -+ pciDiscardTimer &= ~PDTR_TIMER_MASK; -+ -+ pciDiscardTimer |= (pClkCycles << PDTR_TIMER_OFFS); -+ -+ /* Write new value */ -+ MV_REG_WRITE(PCI_DISCARD_TIMER_REG(pciIf), pciDiscardTimer); -+ -+ return MV_OK; -+ -+} -+ -+/* PCI Arbiter routines */ -+ -+/******************************************************************************* -+* mvPciArbEnable - PCI arbiter enable/disable -+* -+* DESCRIPTION: -+* This fuction enable/disables a given PCI interface arbiter. -+* NOTE: Arbiter setting can not be changed while in work. It should only -+* be set once. -+* INPUT: -+* pciIf - PCI interface number. -+* enable - Enable/disable parameter. If enable = MV_TRUE then enable. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvPciArbEnable(MV_U32 pciIf, MV_BOOL enable) -+{ -+ MV_U32 regVal; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciArbEnable: ERR. Invalid PCI interface %d\n", pciIf); -+ return MV_ERROR; -+ } -+ -+ /* Set PCI Arbiter Control register according to default configuration */ -+ regVal = MV_REG_READ(PCI_ARBITER_CTRL_REG(pciIf)); -+ -+ /* Make sure arbiter disabled before changing its values */ -+ MV_REG_BIT_RESET(PCI_ARBITER_CTRL_REG(pciIf), PACR_ARB_ENABLE); -+ -+ regVal &= ~PCI_ARBITER_CTRL_DEFAULT_MASK; -+ -+ regVal |= PCI_ARBITER_CTRL_DEFAULT; /* Set default configuration */ -+ -+ if (MV_TRUE == enable) -+ { -+ regVal |= PACR_ARB_ENABLE; -+ } -+ else -+ { -+ regVal &= ~PACR_ARB_ENABLE; -+ } -+ -+ /* Write to register */ -+ MV_REG_WRITE(PCI_ARBITER_CTRL_REG(pciIf), regVal); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPciArbParkDis - Disable arbiter parking on agent -+* -+* DESCRIPTION: -+* This function disables the PCI arbiter from parking on the given agent -+* list. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* pciAgentMask - When a bit in the mask is set to '1', parking on -+* the associated PCI master is disabled. Mask bit -+* refers to bit 0 - 6. For example disable parking on PCI -+* agent 3 set pciAgentMask 0x4 (bit 3 is set). -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvPciArbParkDis(MV_U32 pciIf, MV_U32 pciAgentMask) -+{ -+ MV_U32 pciArbiterCtrl; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciArbParkDis: ERR. Invalid PCI interface %d\n", pciIf); -+ return MV_ERROR; -+ } -+ -+ /* Reading Arbiter Control register */ -+ pciArbiterCtrl = MV_REG_READ(PCI_ARBITER_CTRL_REG(pciIf)); -+ -+ /* Arbiter must be disabled before changing parking */ -+ MV_REG_BIT_RESET(PCI_ARBITER_CTRL_REG(pciIf), PACR_ARB_ENABLE); -+ -+ /* do the change */ -+ pciArbiterCtrl &= ~PACR_PARK_DIS_MASK; -+ pciArbiterCtrl |= (pciAgentMask << PACR_PARK_DIS_OFFS); -+ -+ /* writing new value ( if th earbiter was enabled before the change */ -+ /* here it will be reenabled */ -+ MV_REG_WRITE(PCI_ARBITER_CTRL_REG(pciIf), pciArbiterCtrl); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPciArbBrokDetectSet - Set PCI arbiter broken detection -+* -+* DESCRIPTION: -+* This function sets the maximum number of cycles that the arbiter -+* waits for a PCI master to respond to its grant assertion. If a -+* PCI agent fails to respond within this time, the PCI arbiter aborts -+* the transaction and performs a new arbitration cycle. -+* NOTE: Value must be greater than '1' for conventional PCI and -+* greater than '5' for PCI-X. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* pClkCycles - Number of PCI clock cycles. If equal to '0' the broken -+* master detection is disabled. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciArbBrokDetectSet(MV_U32 pciIf, MV_U32 pClkCycles) -+{ -+ MV_U32 pciArbiterCtrl; -+ MV_U32 pciMode; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciArbBrokDetectSet: ERR. Invalid PCI interface %d\n", -+ pciIf); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Checking PCI mode and if pClkCycles is legal value */ -+ pciMode = MV_REG_READ(PCI_MODE_REG(pciIf)); -+ pciMode &= PMR_PCI_MODE_MASK; -+ -+ if (PMR_PCI_MODE_CONV == pciMode) -+ { -+ if (pClkCycles < PACR_BROKEN_VAL_CONV_MIN) -+ return MV_ERROR; -+ } -+ else -+ { -+ if (pClkCycles < PACR_BROKEN_VAL_PCIX_MIN) -+ return MV_ERROR; -+ } -+ -+ pClkCycles <<= PACR_BROKEN_VAL_OFFS; -+ -+ /* Reading Arbiter Control register */ -+ pciArbiterCtrl = MV_REG_READ(PCI_ARBITER_CTRL_REG(pciIf)); -+ pciArbiterCtrl &= ~PACR_BROKEN_VAL_MASK; -+ pciArbiterCtrl |= pClkCycles; -+ -+ /* Arbiter must be disabled before changing broken detection */ -+ MV_REG_BIT_RESET(PCI_ARBITER_CTRL_REG(pciIf), PACR_ARB_ENABLE); -+ -+ /* writing new value ( if th earbiter was enabled before the change */ -+ /* here it will be reenabled */ -+ -+ MV_REG_WRITE(PCI_ARBITER_CTRL_REG(pciIf), pciArbiterCtrl); -+ -+ return MV_OK; -+} -+ -+/* PCI configuration space read write */ -+ -+/******************************************************************************* -+* mvPciConfigRead - Read from configuration space -+* -+* DESCRIPTION: -+* This function performs a 32 bit read from PCI configuration space. -+* It supports both type 0 and type 1 of Configuration Transactions -+* (local and over bridge). In order to read from local bus segment, use -+* bus number retrieved from mvPciLocalBusNumGet(). Other bus numbers -+* will result configuration transaction of type 1 (over bridge). -+* -+* INPUT: -+* pciIf - PCI interface number. -+* bus - PCI segment bus number. -+* dev - PCI device number. -+* func - Function number. -+* regOffs - Register offset. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit register data, 0xffffffff on error -+* -+*******************************************************************************/ -+MV_U32 mvPciConfigRead (MV_U32 pciIf, MV_U32 bus, MV_U32 dev, MV_U32 func, -+ MV_U32 regOff) -+{ -+ MV_U32 pciData = 0; -+ -+ /* Parameter checking */ -+ if (PCI_DEFAULT_IF != pciIf) -+ { -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciConfigRead: ERR. Invalid PCI interface %d\n",pciIf); -+ return 0xFFFFFFFF; -+ } -+ } -+ -+ if (dev >= MAX_PCI_DEVICES) -+ { -+ DB(mvOsPrintf("mvPciConfigRead: ERR. device number illigal %d\n", dev)); -+ return 0xFFFFFFFF; -+ } -+ -+ if (func >= MAX_PCI_FUNCS) -+ { -+ DB(mvOsPrintf("mvPciConfigRead: ERR. function number illigal %d\n", func)); -+ return 0xFFFFFFFF; -+ } -+ -+ if (bus >= MAX_PCI_BUSSES) -+ { -+ DB(mvOsPrintf("mvPciConfigRead: ERR. bus number illigal %d\n", bus)); -+ return MV_ERROR; -+ } -+ -+ -+ /* Creating PCI address to be passed */ -+ pciData |= (bus << PCAR_BUS_NUM_OFFS); -+ pciData |= (dev << PCAR_DEVICE_NUM_OFFS); -+ pciData |= (func << PCAR_FUNC_NUM_OFFS); -+ pciData |= (regOff & PCAR_REG_NUM_MASK); -+ -+ pciData |= PCAR_CONFIG_EN; -+ -+ /* Write the address to the PCI configuration address register */ -+ MV_REG_WRITE(PCI_CONFIG_ADDR_REG(pciIf), pciData); -+ -+ /* In order to let the PCI controller absorbed the address of the read */ -+ /* transaction we perform a validity check that the address was written */ -+ if(pciData != MV_REG_READ(PCI_CONFIG_ADDR_REG(pciIf))) -+ { -+ return MV_ERROR; -+ } -+ /* Read the Data returned in the PCI Data register */ -+ pciData = MV_REG_READ(PCI_CONFIG_DATA_REG(pciIf)); -+ -+ return pciData; -+} -+ -+/******************************************************************************* -+* mvPciConfigWrite - Write to configuration space -+* -+* DESCRIPTION: -+* This function performs a 32 bit write to PCI configuration space. -+* It supports both type 0 and type 1 of Configuration Transactions -+* (local and over bridge). In order to write to local bus segment, use -+* bus number retrieved from mvPciLocalBusNumGet(). Other bus numbers -+* will result configuration transaction of type 1 (over bridge). -+* -+* INPUT: -+* pciIf - PCI interface number. -+* bus - PCI segment bus number. -+* dev - PCI device number. -+* func - Function number. -+* regOffs - Register offset. -+* data - 32bit data. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciConfigWrite(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data) -+{ -+ MV_U32 pciData = 0; -+ -+ /* Parameter checking */ -+ if (PCI_DEFAULT_IF != pciIf) -+ { -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciConfigWrite: ERR. Invalid PCI interface %d\n", -+ pciIf); -+ return 0xFFFFFFFF; -+ } -+ } -+ -+ if (dev >= MAX_PCI_DEVICES) -+ { -+ mvOsPrintf("mvPciConfigWrite: ERR. device number illigal %d\n",dev); -+ return MV_BAD_PARAM; -+ } -+ -+ if (func >= MAX_PCI_FUNCS) -+ { -+ mvOsPrintf("mvPciConfigWrite: ERR. function number illigal %d\n", func); -+ return MV_ERROR; -+ } -+ -+ if (bus >= MAX_PCI_BUSSES) -+ { -+ mvOsPrintf("mvPciConfigWrite: ERR. bus number illigal %d\n", bus); -+ return MV_ERROR; -+ } -+ -+ /* Creating PCI address to be passed */ -+ pciData |= (bus << PCAR_BUS_NUM_OFFS); -+ pciData |= (dev << PCAR_DEVICE_NUM_OFFS); -+ pciData |= (func << PCAR_FUNC_NUM_OFFS); -+ pciData |= (regOff & PCAR_REG_NUM_MASK); -+ -+ pciData |= PCAR_CONFIG_EN; -+ -+ /* Write the address to the PCI configuration address register */ -+ MV_REG_WRITE(PCI_CONFIG_ADDR_REG(pciIf), pciData); -+ -+ /* In order to let the PCI controller absorbed the address of the read */ -+ /* transaction we perform a validity check that the address was written */ -+ if(pciData != MV_REG_READ(PCI_CONFIG_ADDR_REG(pciIf))) -+ { -+ return MV_ERROR; -+ } -+ -+ /* Write the Data passed to the PCI Data register */ -+ MV_REG_WRITE(PCI_CONFIG_DATA_REG(pciIf), data); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvPciMasterEnable - Enable/disale PCI interface master transactions. -+* -+* DESCRIPTION: -+* This function performs read modified write to PCI command status -+* (offset 0x4) to set/reset bit 2. After this bit is set, the PCI -+* master is allowed to gain ownership on the bus, otherwise it is -+* incapable to do so. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciMasterEnable(MV_U32 pciIf, MV_BOOL enable) -+{ -+ MV_U32 pciCommandStatus; -+ MV_U32 RegOffs; -+ MV_U32 localBus; -+ MV_U32 localDev; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciMasterEnable: ERR. Invalid PCI interface %d\n", pciIf); -+ return MV_ERROR; -+ } -+ -+ localBus = mvPciLocalBusNumGet(pciIf); -+ localDev = mvPciLocalDevNumGet(pciIf); -+ -+ RegOffs = PCI_STATUS_AND_COMMAND; -+ -+ pciCommandStatus = mvPciConfigRead(pciIf, localBus, localDev, 0, RegOffs); -+ -+ if (MV_TRUE == enable) -+ { -+ pciCommandStatus |= PSCR_MASTER_EN; -+ } -+ else -+ { -+ pciCommandStatus &= ~PSCR_MASTER_EN; -+ } -+ -+ mvPciConfigWrite(pciIf, localBus, localDev, 0, RegOffs, pciCommandStatus); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPciSlaveEnable - Enable/disale PCI interface slave transactions. -+* -+* DESCRIPTION: -+* This function performs read modified write to PCI command status -+* (offset 0x4) to set/reset bit 0 and 1. After those bits are set, -+* the PCI slave is allowed to respond to PCI IO space access (bit 0) -+* and PCI memory space access (bit 1). -+* -+* INPUT: -+* pciIf - PCI interface number. -+* dev - PCI device number. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciSlaveEnable(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, MV_BOOL enable) -+{ -+ MV_U32 pciCommandStatus; -+ MV_U32 RegOffs; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciSlaveEnable: ERR. Invalid PCI interface %d\n", pciIf); -+ return MV_BAD_PARAM; -+ } -+ if (dev >= MAX_PCI_DEVICES) -+ { -+ mvOsPrintf("mvPciLocalDevNumSet: ERR. device number illigal %d\n", dev); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ RegOffs = PCI_STATUS_AND_COMMAND; -+ -+ pciCommandStatus=mvPciConfigRead(pciIf, bus, dev, 0, RegOffs); -+ -+ if (MV_TRUE == enable) -+ { -+ pciCommandStatus |= (PSCR_IO_EN | PSCR_MEM_EN); -+ } -+ else -+ { -+ pciCommandStatus &= ~(PSCR_IO_EN | PSCR_MEM_EN); -+ } -+ -+ mvPciConfigWrite(pciIf, bus, dev, 0, RegOffs, pciCommandStatus); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvPciLocalBusNumSet - Set PCI interface local bus number. -+* -+* DESCRIPTION: -+* This function sets given PCI interface its local bus number. -+* Note: In case the PCI interface is PCI-X, the information is read-only. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* busNum - Bus number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_NOT_ALLOWED in case PCI interface is PCI-X. -+* MV_BAD_PARAM on bad parameters , -+* otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciLocalBusNumSet(MV_U32 pciIf, MV_U32 busNum) -+{ -+ MV_U32 pciP2PConfig; -+ MV_PCI_MODE pciMode; -+ MV_U32 localBus; -+ MV_U32 localDev; -+ -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciLocalBusNumSet: ERR. Invalid PCI interface %d\n",pciIf); -+ return MV_BAD_PARAM; -+ } -+ if (busNum >= MAX_PCI_BUSSES) -+ { -+ mvOsPrintf("mvPciLocalBusNumSet: ERR. bus number illigal %d\n", busNum); -+ return MV_ERROR; -+ -+ } -+ -+ localBus = mvPciLocalBusNumGet(pciIf); -+ localDev = mvPciLocalDevNumGet(pciIf); -+ -+ -+ /* PCI interface mode */ -+ mvPciModeGet(pciIf, &pciMode); -+ -+ /* if PCI type is PCI-X then it is not allowed to change the dev number */ -+ if (MV_PCIX == pciMode.pciType) -+ { -+ pciP2PConfig = mvPciConfigRead(pciIf, localBus, localDev, 0, PCIX_STATUS ); -+ -+ pciP2PConfig &= ~PXS_BN_MASK; -+ -+ pciP2PConfig |= (busNum << PXS_BN_OFFS) & PXS_BN_MASK; -+ -+ mvPciConfigWrite(pciIf, localBus, localDev, 0, PCIX_STATUS,pciP2PConfig ); -+ -+ } -+ else -+ { -+ pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); -+ -+ pciP2PConfig &= ~PPCR_BUS_NUM_MASK; -+ -+ pciP2PConfig |= (busNum << PPCR_BUS_NUM_OFFS) & PPCR_BUS_NUM_MASK; -+ -+ MV_REG_WRITE(PCI_P2P_CONFIG_REG(pciIf), pciP2PConfig); -+ -+ } -+ -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPciLocalBusNumGet - Get PCI interface local bus number. -+* -+* DESCRIPTION: -+* This function gets the local bus number of a given PCI interface. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Local bus number.0xffffffff on Error -+* -+*******************************************************************************/ -+MV_U32 mvPciLocalBusNumGet(MV_U32 pciIf) -+{ -+ MV_U32 pciP2PConfig; -+ -+ /* Parameter checking */ -+ if (PCI_DEFAULT_IF != pciIf) -+ { -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciLocalBusNumGet: ERR. Invalid PCI interface %d\n", -+ pciIf); -+ return 0xFFFFFFFF; -+ } -+ } -+ -+ pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); -+ pciP2PConfig &= PPCR_BUS_NUM_MASK; -+ return (pciP2PConfig >> PPCR_BUS_NUM_OFFS); -+} -+ -+ -+/******************************************************************************* -+* mvPciLocalDevNumSet - Set PCI interface local device number. -+* -+* DESCRIPTION: -+* This function sets given PCI interface its local device number. -+* Note: In case the PCI interface is PCI-X, the information is read-only. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* devNum - Device number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_NOT_ALLOWED in case PCI interface is PCI-X. MV_BAD_PARAM on bad parameters , -+* otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciLocalDevNumSet(MV_U32 pciIf, MV_U32 devNum) -+{ -+ MV_U32 pciP2PConfig; -+ MV_PCI_MODE pciMode; -+ MV_U32 localBus; -+ MV_U32 localDev; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciLocalDevNumSet: ERR. Invalid PCI interface %d\n",pciIf); -+ return MV_BAD_PARAM; -+ } -+ if (devNum >= MAX_PCI_DEVICES) -+ { -+ mvOsPrintf("mvPciLocalDevNumSet: ERR. device number illigal %d\n", -+ devNum); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ localBus = mvPciLocalBusNumGet(pciIf); -+ localDev = mvPciLocalDevNumGet(pciIf); -+ -+ /* PCI interface mode */ -+ mvPciModeGet(pciIf, &pciMode); -+ -+ /* if PCI type is PCIX then it is not allowed to change the dev number */ -+ if (MV_PCIX == pciMode.pciType) -+ { -+ pciP2PConfig = mvPciConfigRead(pciIf, localBus, localDev, 0, PCIX_STATUS ); -+ -+ pciP2PConfig &= ~PXS_DN_MASK; -+ -+ pciP2PConfig |= (devNum << PXS_DN_OFFS) & PXS_DN_MASK; -+ -+ mvPciConfigWrite(pciIf,localBus, localDev, 0, PCIX_STATUS,pciP2PConfig ); -+ } -+ else -+ { -+ pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); -+ -+ pciP2PConfig &= ~PPCR_DEV_NUM_MASK; -+ -+ pciP2PConfig |= (devNum << PPCR_DEV_NUM_OFFS) & PPCR_DEV_NUM_MASK; -+ -+ MV_REG_WRITE(PCI_P2P_CONFIG_REG(pciIf), pciP2PConfig); -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvPciLocalDevNumGet - Get PCI interface local device number. -+* -+* DESCRIPTION: -+* This function gets the local device number of a given PCI interface. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Local device number. 0xffffffff on Error -+* -+*******************************************************************************/ -+MV_U32 mvPciLocalDevNumGet(MV_U32 pciIf) -+{ -+ MV_U32 pciP2PConfig; -+ -+ /* Parameter checking */ -+ -+ if (PCI_DEFAULT_IF != pciIf) -+ { -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciLocalDevNumGet: ERR. Invalid PCI interface %d\n", -+ pciIf); -+ return 0xFFFFFFFF; -+ } -+ } -+ -+ pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); -+ -+ pciP2PConfig &= PPCR_DEV_NUM_MASK; -+ -+ return (pciP2PConfig >> PPCR_DEV_NUM_OFFS); -+} -+ -+ -+ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h 2010-11-09 20:28:11.412495457 +0100 -@@ -0,0 +1,185 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCPCIH -+#define __INCPCIH -+ -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+#include "pci/mvPciRegs.h" -+ -+ -+/* NOTE not supported in this driver: -+ -+ Built In Self Test (BIST) -+ Vital Product Data (VPD) -+ Message Signaled Interrupt (MSI) -+ Power Management -+ Compact PCI Hot Swap -+ Header retarget -+ -+Registers not supported: -+1) PCI DLL Status and Control (PCI0 0x1D20, PCI1 0x1DA0) -+2) PCI/MPP Pads Calibration (CI0/MPP[31:16] 0x1D1C, PCI1/MPP[15:0] 0X1D9C) -+*/ -+ -+/* defines */ -+/* The number of supported PCI interfaces depend on Marvell controller */ -+/* device number. This device number ID is located on the PCI unit */ -+/* configuration header. This creates a loop where calling PCI */ -+/* configuration read/write routine results a call to get PCI configuration */ -+/* information etc. This macro defines a default PCI interface. This PCI */ -+/* interface is sure to exist. */ -+#define PCI_DEFAULT_IF 0 -+ -+ -+/* typedefs */ -+/* The Marvell controller supports both conventional PCI and PCI-X. */ -+/* This enumeration describes the PCI type. */ -+typedef enum _mvPciType -+{ -+ MV_PCI_CONV, /* Conventional PCI */ -+ MV_PCIX /* PCI-X */ -+}MV_PCI_TYPE; -+ -+typedef enum _mvPciMod -+{ -+ MV_PCI_MOD_HOST, -+ MV_PCI_MOD_DEVICE -+}MV_PCI_MOD; -+ -+ -+/* The Marvell controller supports both PCI width of 32 and 64 bit. */ -+/* This enumerator describes PCI width */ -+typedef enum _mvPciWidth -+{ -+ MV_PCI_32, /* PCI width 32bit */ -+ MV_PCI_64 /* PCI width 64bit */ -+}MV_PCI_WIDTH; -+ -+/* This structure describes the PCI unit configured type, speed and width. */ -+typedef struct _mvPciMode -+{ -+ MV_PCI_TYPE pciType; /* PCI type */ -+ MV_U32 pciSpeed; /* Assuming PCI base clock on board is 33MHz */ -+ MV_PCI_WIDTH pciWidth; /* PCI bus width */ -+}MV_PCI_MODE; -+ -+/* mvPciInit - Initialize PCI interfaces*/ -+MV_VOID mvPciHalInit(MV_U32 pciIf, MV_PCI_MOD pciIfmod); -+ -+/* mvPciCommandSet - Set PCI comman register value.*/ -+MV_STATUS mvPciCommandSet(MV_U32 pciIf, MV_U32 command); -+ -+/* mvPciModeGet - Get PCI interface mode.*/ -+MV_STATUS mvPciModeGet(MV_U32 pciIf, MV_PCI_MODE *pPciMode); -+ -+/* mvPciRetrySet - Set PCI retry counters*/ -+MV_STATUS mvPciRetrySet(MV_U32 pciIf, MV_U32 counter); -+ -+/* mvPciDiscardTimerSet - Set PCI discard timer*/ -+MV_STATUS mvPciDiscardTimerSet(MV_U32 pciIf, MV_U32 pClkCycles); -+ -+/* mvPciArbEnable - PCI arbiter enable/disable*/ -+MV_STATUS mvPciArbEnable(MV_U32 pciIf, MV_BOOL enable); -+ -+/* mvPciArbParkDis - Disable arbiter parking on agent */ -+MV_STATUS mvPciArbParkDis(MV_U32 pciIf, MV_U32 pciAgentMask); -+ -+/* mvPciArbBrokDetectSet - Set PCI arbiter broken detection */ -+MV_STATUS mvPciArbBrokDetectSet(MV_U32 pciIf, MV_U32 pClkCycles); -+ -+/* mvPciConfigRead - Read from configuration space */ -+MV_U32 mvPciConfigRead (MV_U32 pciIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func,MV_U32 regOff); -+ -+/* mvPciConfigWrite - Write to configuration space */ -+MV_STATUS mvPciConfigWrite(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data); -+ -+/* mvPciMasterEnable - Enable/disale PCI interface master transactions.*/ -+MV_STATUS mvPciMasterEnable(MV_U32 pciIf, MV_BOOL enable); -+ -+/* mvPciSlaveEnable - Enable/disale PCI interface slave transactions.*/ -+MV_STATUS mvPciSlaveEnable(MV_U32 pciIf, MV_U32 bus, MV_U32 dev,MV_BOOL enable); -+ -+/* mvPciLocalBusNumSet - Set PCI interface local bus number.*/ -+MV_STATUS mvPciLocalBusNumSet(MV_U32 pciIf, MV_U32 busNum); -+ -+/* mvPciLocalBusNumGet - Get PCI interface local bus number.*/ -+MV_U32 mvPciLocalBusNumGet(MV_U32 pciIf); -+ -+/* mvPciLocalDevNumSet - Set PCI interface local device number.*/ -+MV_STATUS mvPciLocalDevNumSet(MV_U32 pciIf, MV_U32 devNum); -+ -+/* mvPciLocalDevNumGet - Get PCI interface local device number.*/ -+MV_U32 mvPciLocalDevNumGet(MV_U32 pciIf); -+ -+ -+#endif /* #ifndef __INCPCIH */ -+ -+ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h 2010-11-09 20:28:11.452495500 +0100 -@@ -0,0 +1,411 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCPCIREGSH -+#define __INCPCIREGSH -+ -+ -+#include "pci-if/mvPciIfRegs.h" -+/* defines */ -+#define MAX_PCI_DEVICES 32 -+#define MAX_PCI_FUNCS 8 -+#define MAX_PCI_BUSSES 128 -+ -+/* enumerators */ -+ -+/* This enumerator described the possible PCI slave targets. */ -+/* PCI slave targets are designated memory/IO address spaces that the */ -+/* PCI slave targets can access. They are also refered as "targets" */ -+/* this enumeratoe order is determined by the content of : -+ PCI_BASE_ADDR_ENABLE_REG */ -+ -+ -+/* registers offsetes defines */ -+ -+ -+ -+/*************************/ -+/* PCI control registers */ -+/*************************/ -+/* maen : should add new registers */ -+#define PCI_CMD_REG(pciIf) (0x30c00 + ((pciIf) * 0x80)) -+#define PCI_MODE_REG(pciIf) (0x30d00 + ((pciIf) * 0x80)) -+#define PCI_RETRY_REG(pciIf) (0x30c04 + ((pciIf) * 0x80)) -+#define PCI_DISCARD_TIMER_REG(pciIf) (0x30d04 + ((pciIf) * 0x80)) -+#define PCI_ARBITER_CTRL_REG(pciIf) (0x31d00 + ((pciIf) * 0x80)) -+#define PCI_P2P_CONFIG_REG(pciIf) (0x31d14 + ((pciIf) * 0x80)) -+#define PCI_ACCESS_CTRL_BASEL_REG(pciIf, targetWin) \ -+ (0x31e00 + ((pciIf) * 0x80) + ((targetWin) * 0x10)) -+#define PCI_ACCESS_CTRL_BASEH_REG(pciIf, targetWin) \ -+ (0x31e04 + ((pciIf) * 0x80) + ((targetWin) * 0x10)) -+#define PCI_ACCESS_CTRL_SIZE_REG(pciIf, targetWin) \ -+ (0x31e08 + ((pciIf) * 0x80) + ((targetWin) * 0x10)) -+ -+#define PCI_DLL_CTRL_REG(pciIf) (0x31d20 + ((pciIf) * 0x80)) -+ -+/* PCI Dll Control (PDC)*/ -+#define PDC_DLL_EN BIT0 -+ -+ -+/* PCI Command Register (PCR) */ -+#define PCR_MASTER_BYTE_SWAP_EN BIT0 -+#define PCR_MASTER_WR_COMBINE_EN BIT4 -+#define PCR_MASTER_RD_COMBINE_EN BIT5 -+#define PCR_MASTER_WR_TRIG_WHOLE BIT6 -+#define PCR_MASTER_RD_TRIG_WHOLE BIT7 -+#define PCR_MASTER_MEM_RD_LINE_EN BIT8 -+#define PCR_MASTER_MEM_RD_MULT_EN BIT9 -+#define PCR_MASTER_WORD_SWAP_EN BIT10 -+#define PCR_SLAVE_WORD_SWAP_EN BIT11 -+#define PCR_NS_ACCORDING_RCV_TRANS BIT14 -+#define PCR_MASTER_PCIX_REQ64N_EN BIT15 -+#define PCR_SLAVE_BYTE_SWAP_EN BIT16 -+#define PCR_MASTER_DAC_EN BIT17 -+#define PCR_MASTER_M64_ALLIGN BIT18 -+#define PCR_ERRORS_PROPAGATION_EN BIT19 -+#define PCR_SLAVE_SWAP_ENABLE BIT20 -+#define PCR_MASTER_SWAP_ENABLE BIT21 -+#define PCR_MASTER_INT_SWAP_EN BIT22 -+#define PCR_LOOP_BACK_ENABLE BIT23 -+#define PCR_SLAVE_INTREG_SWAP_OFFS 24 -+#define PCR_SLAVE_INTREG_SWAP_MASK 0x3 -+#define PCR_SLAVE_INTREG_BYTE_SWAP \ -+ (MV_BYTE_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) -+#define PCR_SLAVE_INTREG_NO_SWAP \ -+ (MV_NO_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) -+#define PCR_SLAVE_INTREG_BYTE_WORD \ -+ (MV_BYTE_WORD_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) -+#define PCR_SLAVE_INTREG_WORD_SWAP \ -+ (MV_WORD_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) -+#define PCR_RESET_REASSERTION_EN BIT26 -+#define PCR_PCI_TO_CPU_REG_ORDER_EN BIT28 -+#define PCR_CPU_TO_PCI_ORDER_EN BIT29 -+#define PCR_PCI_TO_CPU_ORDER_EN BIT30 -+ -+/* PCI Mode Register (PMR) */ -+#define PMR_PCI_ID_OFFS 0 /* PCI Interface ID */ -+#define PMR_PCI_ID_MASK (0x1 << PMR_PCI_ID_OFFS) -+#define PMR_PCI_ID_PCI(pciNum) ((pciNum) << PCI_MODE_PCIID_OFFS) -+ -+#define PMR_PCI_64_OFFS 2 /* 64-bit PCI Interface */ -+#define PMR_PCI_64_MASK (0x1 << PMR_PCI_64_OFFS) -+#define PMR_PCI_64_64BIT (0x1 << PMR_PCI_64_OFFS) -+#define PMR_PCI_64_32BIT (0x0 << PMR_PCI_64_OFFS) -+ -+#define PMR_PCI_MODE_OFFS 4 /* PCI interface mode of operation */ -+#define PMR_PCI_MODE_MASK (0x3 << PMR_PCI_MODE_OFFS) -+#define PMR_PCI_MODE_CONV (0x0 << PMR_PCI_MODE_OFFS) -+#define PMR_PCI_MODE_PCIX_66MHZ (0x1 << PMR_PCI_MODE_OFFS) -+#define PMR_PCI_MODE_PCIX_100MHZ (0x2 << PMR_PCI_MODE_OFFS) -+#define PMR_PCI_MODE_PCIX_133MHZ (0x3 << PMR_PCI_MODE_OFFS) -+ -+#define PMR_EXP_ROM_SUPPORT BIT8 /* Expansion ROM Active */ -+ -+#define PMR_PCI_RESET_OFFS 31 /* PCI Interface Reset Indication */ -+#define PMR_PCI_RESET_MASK (0x1 << PMR_PCI_RESET_OFFS) -+#define PMR_PCI_RESET_PCIXRST (0x0 << PMR_PCI_RESET_OFFS) -+ -+ -+/* PCI Retry Register (PRR) */ -+#define PRR_RETRY_CNTR_OFFS 16 /* Retry Counter */ -+#define PRR_RETRY_CNTR_MAX 0xff -+#define PRR_RETRY_CNTR_MASK (PRR_RETRY_CNTR_MAX << PRR_RETRY_CNTR_OFFS) -+ -+ -+/* PCI Discard Timer Register (PDTR) */ -+#define PDTR_TIMER_OFFS 0 /* Timer */ -+#define PDTR_TIMER_MAX 0xffff -+#define PDTR_TIMER_MIN 0x7F -+#define PDTR_TIMER_MASK (PDTR_TIMER_MAX << PDTR_TIMER_OFFS) -+ -+ -+/* PCI Arbiter Control Register (PACR) */ -+#define PACR_BROKEN_DETECT_EN BIT1 /* Broken Detection Enable */ -+ -+#define PACR_BROKEN_VAL_OFFS 3 /* Broken Value */ -+#define PACR_BROKEN_VAL_MASK (0xf << PACR_BROKEN_VAL_OFFS) -+#define PACR_BROKEN_VAL_CONV_MIN 0x2 -+#define PACR_BROKEN_VAL_PCIX_MIN 0x6 -+ -+#define PACR_PARK_DIS_OFFS 14 /* Parking Disable */ -+#define PACR_PARK_DIS_MAX_AGENT 0x3f -+#define PACR_PARK_DIS_MASK (PACR_PARK_DIS_MAX_AGENT<= MV_PCI_START_IF)&&(pciIf < MV_PCI_MAX_IF + MV_PCI_START_IF)) -+ { -+ return PCI_IF_TYPE_CONVEN_PCIX; -+ } -+ else if ((pciIf >= MV_PEX_START_IF) && -+ (pciIf < MV_PEX_MAX_IF + MV_PEX_START_IF)) -+ { -+ return PCI_IF_TYPE_PEX; -+ -+ } -+ else -+ { -+ mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf); -+ } -+ -+ return 0xffffffff; -+ -+} -+ -+/******************************************************************************* -+* mvPciIfTypeGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+ -+MV_U32 mvPciRealIfNumGet(MV_U32 pciIf) -+{ -+ -+ PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf); -+ -+ if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType) -+ { -+ return (pciIf - MV_PCI_START_IF); -+ } -+ else if (PCI_IF_TYPE_PEX == pciIfType) -+ { -+ return (pciIf - MV_PEX_START_IF); -+ -+ } -+ else -+ { -+ mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf); -+ } -+ -+ return 0xffffffff; -+ -+} -+ -+ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.h 2010-11-09 20:28:11.552495455 +0100 -@@ -0,0 +1,134 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCPCIIFH -+#define __INCPCIIFH -+ -+#include "mvSysHwConfig.h" -+#include "pci-if/mvPciIfRegs.h" -+#if defined(MV_INCLUDE_PEX) -+#include "pex/mvPex.h" -+#endif -+#if defined(MV_INCLUDE_PCI) -+#include "pci/mvPci.h" -+#endif -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+ -+typedef enum _mvPCIIfType -+{ -+ PCI_IF_TYPE_CONVEN_PCIX, -+ PCI_IF_TYPE_PEX -+ -+}PCI_IF_TYPE; -+ -+typedef enum _mvPCIIfMode -+{ -+ PCI_IF_MODE_HOST, -+ PCI_IF_MODE_DEVICE -+}PCI_IF_MODE; -+ -+ -+/* Global Functions prototypes */ -+ -+/* mvPciIfInit - Initialize PCI interfaces*/ -+MV_STATUS mvPciIfInit(MV_U32 pciIf, PCI_IF_MODE pciIfmode); -+ -+/* mvPciIfConfigRead - Read from configuration space */ -+MV_U32 mvPciIfConfigRead (MV_U32 pciIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func,MV_U32 regOff); -+ -+/* mvPciIfConfigWrite - Write to configuration space */ -+MV_STATUS mvPciIfConfigWrite(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data); -+ -+/* mvPciIfMasterEnable - Enable/disale PCI interface master transactions.*/ -+MV_STATUS mvPciIfMasterEnable(MV_U32 pciIf, MV_BOOL enable); -+ -+/* mvPciIfSlaveEnable - Enable/disale PCI interface slave transactions.*/ -+MV_STATUS mvPciIfSlaveEnable(MV_U32 pciIf,MV_U32 bus, MV_U32 dev, -+ MV_BOOL enable); -+ -+/* mvPciIfLocalBusNumSet - Set PCI interface local bus number.*/ -+MV_STATUS mvPciIfLocalBusNumSet(MV_U32 pciIf, MV_U32 busNum); -+ -+/* mvPciIfLocalBusNumGet - Get PCI interface local bus number.*/ -+MV_U32 mvPciIfLocalBusNumGet(MV_U32 pciIf); -+ -+/* mvPciIfLocalDevNumSet - Set PCI interface local device number.*/ -+MV_STATUS mvPciIfLocalDevNumSet(MV_U32 pciIf, MV_U32 devNum); -+ -+/* mvPciIfLocalDevNumGet - Get PCI interface local device number.*/ -+MV_U32 mvPciIfLocalDevNumGet(MV_U32 pciIf); -+ -+/* mvPciIfTypeGet - Get PCI If type*/ -+PCI_IF_TYPE mvPciIfTypeGet(MV_U32 pciIf); -+ -+MV_U32 mvPciRealIfNumGet(MV_U32 pciIf); -+ -+/* mvPciIfAddrDecShow - Display address decode windows attributes */ -+MV_VOID mvPciIfAddrDecShow(MV_VOID); -+ -+#endif /* #ifndef __INCPCIIFH */ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h 2010-11-09 20:28:11.592495403 +0100 -@@ -0,0 +1,245 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCPCIIFREGSH -+#define __INCPCIIFREGSH -+ -+ -+/* defines */ -+#define MAX_PCI_DEVICES 32 -+#define MAX_PCI_FUNCS 8 -+#define MAX_PCI_BUSSES 128 -+ -+/***************************************/ -+/* PCI Configuration registers */ -+/***************************************/ -+ -+/*********************************************/ -+/* PCI Configuration, Function 0, Registers */ -+/*********************************************/ -+ -+ -+/* Standard registers */ -+#define PCI_DEVICE_AND_VENDOR_ID 0x000 -+#define PCI_STATUS_AND_COMMAND 0x004 -+#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 -+#define PCI_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE 0x00C -+#define PCI_MEMORY_BAR_BASE_ADDR(barNum) (0x010 + ((barNum) << 2)) -+#define PCI_SUBSYS_ID_AND_SUBSYS_VENDOR_ID 0x02C -+#define PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030 -+#define PCI_CAPABILTY_LIST_POINTER 0x034 -+#define PCI_INTERRUPT_PIN_AND_LINE 0x03C -+ -+ -+/* PCI Device and Vendor ID Register (PDVIR) */ -+#define PDVIR_VEN_ID_OFFS 0 /* Vendor ID */ -+#define PDVIR_VEN_ID_MASK (0xffff << PDVIR_VEN_ID_OFFS) -+ -+#define PDVIR_DEV_ID_OFFS 16 /* Device ID */ -+#define PDVIR_DEV_ID_MASK (0xffff << PDVIR_DEV_ID_OFFS) -+ -+/* PCI Status and Command Register (PSCR) */ -+#define PSCR_IO_EN BIT0 /* IO Enable */ -+#define PSCR_MEM_EN BIT1 /* Memory Enable */ -+#define PSCR_MASTER_EN BIT2 /* Master Enable */ -+#define PSCR_SPECIAL_EN BIT3 /* Special Cycle Enable */ -+#define PSCR_MEM_WRI_INV BIT4 /* Memory Write and Invalidate Enable */ -+#define PSCR_VGA BIT5 /* VGA Palette Snoops */ -+#define PSCR_PERR_EN BIT6 /* Parity Errors Respond Enable */ -+#define PSCR_ADDR_STEP BIT7 /* Address Stepping Enable (Wait Cycle En)*/ -+#define PSCR_SERR_EN BIT8 /* Ability to assert SERR# line */ -+#define PSCR_FAST_BTB_EN BIT9 /* generate fast back-to-back transactions*/ -+#define PSCR_CAP_LIST BIT20 /* Capability List Support */ -+#define PSCR_66MHZ_EN BIT21 /* 66 MHz Capable */ -+#define PSCR_UDF_EN BIT22 /* User definable features */ -+#define PSCR_TAR_FAST_BB BIT23 /* fast back-to-back transactions capable */ -+#define PSCR_DATA_PERR BIT24 /* Data Parity reported */ -+ -+#define PSCR_DEVSEL_TIM_OFFS 25 /* DEVSEL timing */ -+#define PSCR_DEVSEL_TIM_MASK (0x3 << PSCR_DEVSEL_TIM_OFFS) -+#define PSCR_DEVSEL_TIM_FAST (0x0 << PSCR_DEVSEL_TIM_OFFS) -+#define PSCR_DEVSEL_TIM_MED (0x1 << PSCR_DEVSEL_TIM_OFFS) -+#define PSCR_DEVSEL_TIM_SLOW (0x2 << PSCR_DEVSEL_TIM_OFFS) -+ -+#define PSCR_SLAVE_TABORT BIT27 /* Signalled Target Abort */ -+#define PSCR_MASTER_TABORT BIT28 /* Recieved Target Abort */ -+#define PSCR_MABORT BIT29 /* Recieved Master Abort */ -+#define PSCR_SYSERR BIT30 /* Signalled system error */ -+#define PSCR_DET_PARERR BIT31 /* Detect Parity Error */ -+ -+/* PCI configuration register offset=0x08 fields -+ (PCI_CLASS_CODE_AND_REVISION_ID)(PCCRI) */ -+ -+#define PCCRIR_REVID_OFFS 0 /* Revision ID */ -+#define PCCRIR_REVID_MASK (0xff << PCCRIR_REVID_OFFS) -+ -+#define PCCRIR_FULL_CLASS_OFFS 8 /* Full Class Code */ -+#define PCCRIR_FULL_CLASS_MASK (0xffffff << PCCRIR_FULL_CLASS_OFFS) -+ -+#define PCCRIR_PROGIF_OFFS 8 /* Prog .I/F*/ -+#define PCCRIR_PROGIF_MASK (0xff << PCCRIR_PROGIF_OFFS) -+ -+#define PCCRIR_SUB_CLASS_OFFS 16 /* Sub Class*/ -+#define PCCRIR_SUB_CLASS_MASK (0xff << PCCRIR_SUB_CLASS_OFFS) -+ -+#define PCCRIR_BASE_CLASS_OFFS 24 /* Base Class*/ -+#define PCCRIR_BASE_CLASS_MASK (0xff << PCCRIR_BASE_CLASS_OFFS) -+ -+/* PCI configuration register offset=0x0C fields -+ (PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE)(PBHTLTCL) */ -+ -+#define PBHTLTCLR_CACHELINE_OFFS 0 /* Specifies the cache line size */ -+#define PBHTLTCLR_CACHELINE_MASK (0xff << PBHTLTCLR_CACHELINE_OFFS) -+ -+#define PBHTLTCLR_LATTIMER_OFFS 8 /* latency timer */ -+#define PBHTLTCLR_LATTIMER_MASK (0xff << PBHTLTCLR_LATTIMER_OFFS) -+ -+#define PBHTLTCLR_HEADTYPE_FULL_OFFS 16 /* Full Header Type */ -+#define PBHTLTCLR_HEADTYPE_FULL_MASK (0xff << PBHTLTCLR_HEADTYPE_FULL_OFFS) -+ -+#define PBHTLTCLR_MULTI_FUNC BIT23 /* Multi/Single function */ -+ -+#define PBHTLTCLR_HEADER_OFFS 16 /* Header type */ -+#define PBHTLTCLR_HEADER_MASK (0x7f << PBHTLTCLR_HEADER_OFFS) -+#define PBHTLTCLR_HEADER_STANDARD (0x0 << PBHTLTCLR_HEADER_OFFS) -+#define PBHTLTCLR_HEADER_PCI2PCI_BRIDGE (0x1 << PBHTLTCLR_HEADER_OFFS) -+ -+ -+#define PBHTLTCLR_BISTCOMP_OFFS 24 /* BIST Completion Code */ -+#define PBHTLTCLR_BISTCOMP_MASK (0xf << PBHTLTCLR_BISTCOMP_OFFS) -+ -+#define PBHTLTCLR_BISTACT BIT30 /* BIST Activate bit */ -+#define PBHTLTCLR_BISTCAP BIT31 /* BIST Capable Bit */ -+ -+ -+/* PCI Bar Base Low Register (PBBLR) */ -+#define PBBLR_IOSPACE BIT0 /* Memory Space Indicator */ -+ -+#define PBBLR_TYPE_OFFS 1 /* BAR Type/Init Val. */ -+#define PBBLR_TYPE_MASK (0x3 << PBBLR_TYPE_OFFS) -+#define PBBLR_TYPE_32BIT_ADDR (0x0 << PBBLR_TYPE_OFFS) -+#define PBBLR_TYPE_64BIT_ADDR (0x2 << PBBLR_TYPE_OFFS) -+ -+#define PBBLR_PREFETCH_EN BIT3 /* Prefetch Enable */ -+ -+ -+#define PBBLR_MEM_BASE_OFFS 4 /* Memory Bar Base address. Corresponds to -+ address bits [31:4] */ -+#define PBBLR_MEM_BASE_MASK (0xfffffff << PBBLR_MEM_BASE_OFFS) -+ -+#define PBBLR_IO_BASE_OFFS 2 /* IO Bar Base address. Corresponds to -+ address bits [31:2] */ -+#define PBBLR_IO_BASE_MASK (0x3fffffff << PBBLR_IO_BASE_OFFS) -+ -+ -+#define PBBLR_BASE_OFFS 12 /* Base address. Address bits [31:12] */ -+#define PBBLR_BASE_MASK (0xfffff << PBBLR_BASE_OFFS) -+#define PBBLR_BASE_ALIGNMET (1 << PBBLR_BASE_OFFS) -+ -+ -+/* PCI Bar Base High Fegister (PBBHR) */ -+#define PBBHR_BASE_OFFS 0 /* Base address. Address bits [31:12] */ -+#define PBBHR_BASE_MASK (0xffffffff << PBBHR_BASE_OFFS) -+ -+ -+/* PCI configuration register offset=0x2C fields -+ (PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID)(PSISVI) */ -+ -+#define PSISVIR_VENID_OFFS 0 /* Subsystem Manufacturer Vendor ID Number */ -+#define PSISVIR_VENID_MASK (0xffff << PSISVIR_VENID_OFFS) -+ -+#define PSISVIR_DEVID_OFFS 16 /* Subsystem Device ID Number */ -+#define PSISVIR_DEVID_MASK (0xffff << PSISVIR_DEVID_OFFS) -+ -+/* PCI configuration register offset=0x30 fields -+ (PCI_EXPANSION_ROM_BASE_ADDR_REG)(PERBA) */ -+ -+#define PERBAR_EXPROMEN BIT0 /* Expansion ROM Enable */ -+ -+#define PERBAR_BASE_OFFS 12 /* Expansion ROM Base Address */ -+#define PERBAR_BASE_MASK (0xfffff << PERBAR_BASE_OFFS) -+ -+/* PCI configuration register offset=0x34 fields -+ (PCI_CAPABILTY_LIST_POINTER)(PCLP) */ -+ -+#define PCLPR_CAPPTR_OFFS 0 /* Capability List Pointer */ -+#define PCLPR_CAPPTR_MASK (0xff << PCLPR_CAPPTR_OFFS) -+ -+/* PCI configuration register offset=0x3C fields -+ (PCI_INTERRUPT_PIN_AND_LINE)(PIPL) */ -+ -+#define PIPLR_INTLINE_OFFS 0 /* Interrupt line (IRQ) */ -+#define PIPLR_INTLINE_MASK (0xff << PIPLR_INTLINE_OFFS) -+ -+#define PIPLR_INTPIN_OFFS 8 /* interrupt pin (A,B,C,D) */ -+#define PIPLR_INTPIN_MASK (0xff << PIPLR_INTPIN_OFFS) -+ -+#define PIPLR_MINGRANT_OFFS 16 /* Minimum Grant on 250 nano seconds units */ -+#define PIPLR_MINGRANT_MASK (0xff << PIPLR_MINGRANT_OFFS) -+ -+#define PIPLR_MAXLATEN_OFFS 24 /* Maximum latency on 250 nano seconds units */ -+#define PIPLR_MAXLATEN_MASK (0xff << PIPLR_MAXLATEN_OFFS) -+ -+#endif /* #ifndef __INCPCIIFREGSH */ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.c 2010-11-09 20:28:11.632495445 +0100 -@@ -0,0 +1,1006 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+/* includes */ -+#include "mvPciUtils.h" -+ -+#include "ctrlEnv/mvCtrlEnvLib.h" -+ -+/* #define MV_DEBUG */ -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+ #define mvOsPrintf printf -+#else -+ #define DB(x) -+#endif -+ -+/* -+This module only support scanning of Header type 00h of pci devices -+There is no suppotr for Header type 01h of pci devices ( PCI bridges ) -+*/ -+ -+ -+static MV_STATUS pciDetectDevice(MV_U32 pciIf, -+ MV_U32 bus, -+ MV_U32 dev, -+ MV_U32 func, -+ MV_PCI_DEVICE *pPciAgent); -+ -+static MV_U32 pciDetectDeviceBars(MV_U32 pciIf, -+ MV_U32 bus, -+ MV_U32 dev, -+ MV_U32 func, -+ MV_PCI_DEVICE *pPciAgent); -+ -+ -+ -+ -+ -+ -+/******************************************************************************* -+* mvPciScan - Scan a PCI interface bus -+* -+* DESCRIPTION: -+* Performs a full scan on a PCI interface and returns all possible details -+* on the agents found on the bus. -+* -+* INPUT: -+* pciIf - PCI Interface -+* pPciAgents - Pointer to an Array of the pci agents to be detected -+* pPciAgentsNum - pPciAgents array maximum number of elements -+* -+* OUTPUT: -+* pPciAgents - Array of the pci agents detected on the bus -+* pPciAgentsNum - Number of pci agents detected on the bus -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+ -+MV_STATUS mvPciScan(MV_U32 pciIf, -+ MV_PCI_DEVICE *pPciAgents, -+ MV_U32 *pPciAgentsNum) -+{ -+ -+ MV_U32 devIndex,funcIndex=0,busIndex=0,detectedDevNum=0; -+ MV_U32 localBus=mvPciIfLocalBusNumGet(pciIf); -+ MV_PCI_DEVICE *pPciDevice; -+ MV_PCI_DEVICE *pMainDevice; -+ -+ DB(mvOsPrintf("mvPciScan: PCI interface num %d\n", pciIf)); -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPexMaxIfGet()) -+ { -+ DB(mvOsPrintf("mvPciScan: ERR. Invalid PCI interface num %d\n", pciIf)); -+ return MV_BAD_PARAM; -+ } -+ if (NULL == pPciAgents) -+ { -+ DB(mvOsPrintf("mvPciScan: ERR. pPciAgents=NULL \n")); -+ return MV_BAD_PARAM; -+ } -+ if (NULL == pPciAgentsNum) -+ { -+ DB(mvOsPrintf("mvPciScan: ERR. pPciAgentsNum=NULL \n")); -+ return MV_BAD_PARAM; -+ } -+ -+ -+ DB(mvOsPrintf("mvPciScan: PCI interface num %d mvPciMasterEnable\n", pciIf)); -+ /* Master enable the MV PCI master */ -+ if (MV_OK != mvPciIfMasterEnable(pciIf,MV_TRUE)) -+ { -+ DB(mvOsPrintf("mvPciScan: ERR. mvPciMasterEnable failed \n")); -+ return MV_ERROR; -+ -+ } -+ -+ DB(mvOsPrintf("mvPciScan: PCI interface num scan%d\n", pciIf)); -+ -+ /* go through all busses */ -+ for (busIndex=localBus ; busIndex < MAX_PCI_BUSSES ; busIndex++) -+ { -+ /* go through all possible devices on the local bus */ -+ for (devIndex=0 ; devIndex < MAX_PCI_DEVICES ; devIndex++) -+ { -+ /* always start with function equal to zero */ -+ funcIndex=0; -+ -+ pPciDevice=&pPciAgents[detectedDevNum]; -+ DB(mvOsPrintf("mvPciScan: PCI interface num scan%d:%d\n", busIndex, devIndex)); -+ -+ if (MV_ERROR == pciDetectDevice(pciIf, -+ busIndex, -+ devIndex, -+ funcIndex, -+ pPciDevice)) -+ { -+ /* no device detected , try the next address */ -+ continue; -+ } -+ -+ /* We are here ! means we have detected a device*/ -+ /* always we start with only one function per device */ -+ pMainDevice = pPciDevice; -+ pPciDevice->funtionsNum = 1; -+ -+ -+ /* move on */ -+ detectedDevNum++; -+ -+ -+ /* check if we have no more room for a new device */ -+ if (detectedDevNum == *pPciAgentsNum) -+ { -+ DB(mvOsPrintf("mvPciScan: ERR. array passed too small \n")); -+ return MV_ERROR; -+ } -+ -+ /* check the detected device if it is a multi functional device then -+ scan all device functions*/ -+ if (pPciDevice->isMultiFunction == MV_TRUE) -+ { -+ /* start with function number 1 because we have already detected -+ function 0 */ -+ for (funcIndex=1; funcIndexfuntionsNum++; -+ detectedDevNum++; -+ -+ /* check if we have no more room for a new device */ -+ if (detectedDevNum == *pPciAgentsNum) -+ { -+ DB(mvOsPrintf("mvPciScan: ERR. Array too small\n")); -+ return MV_ERROR; -+ } -+ -+ -+ } -+ } -+ -+ } -+ -+ } -+ -+ /* return the number of devices actually detected on the bus ! */ -+ *pPciAgentsNum = detectedDevNum; -+ -+ return MV_OK; -+ -+} -+ -+ -+/******************************************************************************* -+* pciDetectDevice - Detect a pci device parameters -+* -+* DESCRIPTION: -+* This function detect if a pci agent exist on certain address ! -+* and if exists then it fills all possible information on the -+* agent -+* -+* INPUT: -+* pciIf - PCI Interface -+* bus - Bus number -+* dev - Device number -+* func - Function number -+* -+* -+* -+* OUTPUT: -+* pPciAgent - pointer to the pci agent filled with its information -+* -+* RETURN: -+* MV_ERROR if no device , MV_OK otherwise -+* -+*******************************************************************************/ -+ -+static MV_STATUS pciDetectDevice(MV_U32 pciIf, -+ MV_U32 bus, -+ MV_U32 dev, -+ MV_U32 func, -+ MV_PCI_DEVICE *pPciAgent) -+{ -+ MV_U32 pciData; -+ -+ /* no Parameters checking ! because it is static function and it is assumed -+ that all parameters were checked in the calling function */ -+ -+ -+ /* Try read the PCI Vendor ID and Device ID */ -+ -+ /* We will scan only ourselves and the PCI slots that exist on the -+ board, because we may have a case that we have one slot that has -+ a Cardbus connector, and because CardBus answers all IDsels we want -+ to scan only this slot and ourseleves. -+ -+ */ -+ #if defined(MV_INCLUDE_PCI) -+ if ((PCI_IF_TYPE_CONVEN_PCIX == mvPciIfTypeGet(pciIf)) && -+ (DB_88F5181_DDR1_PRPMC != mvBoardIdGet()) && -+ (DB_88F5181_DDR1_PEXPCI != mvBoardIdGet()) && -+ (DB_88F5181_DDR1_MNG != mvBoardIdGet())) -+ { -+ -+ if (mvBoardIsOurPciSlot(bus, dev) == MV_FALSE) -+ { -+ return MV_ERROR; -+ } -+ } -+ #endif /* defined(MV_INCLUDE_PCI) */ -+ -+ pciData = mvPciIfConfigRead(pciIf, bus,dev,func, PCI_DEVICE_AND_VENDOR_ID); -+ -+ if (PCI_ERROR_CODE == pciData) -+ { -+ /* no device exist */ -+ return MV_ERROR; -+ } -+ -+ /* we are here ! means a device is detected */ -+ -+ /* fill basic information */ -+ pPciAgent->busNumber=bus; -+ pPciAgent->deviceNum=dev; -+ pPciAgent->function=func; -+ -+ /* Fill the PCI Vendor ID and Device ID */ -+ -+ pPciAgent->venID = (pciData & PDVIR_VEN_ID_MASK) >> PDVIR_VEN_ID_OFFS; -+ pPciAgent->deviceID = (pciData & PDVIR_DEV_ID_MASK) >> PDVIR_DEV_ID_OFFS; -+ -+ /* Read Status and command */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_STATUS_AND_COMMAND); -+ -+ -+ /* Fill related Status and Command information*/ -+ -+ if (pciData & PSCR_TAR_FAST_BB) -+ { -+ pPciAgent->isFastB2BCapable = MV_TRUE; -+ } -+ else -+ { -+ pPciAgent->isFastB2BCapable = MV_FALSE; -+ } -+ -+ if (pciData & PSCR_CAP_LIST) -+ { -+ pPciAgent->isCapListSupport=MV_TRUE; -+ } -+ else -+ { -+ pPciAgent->isCapListSupport=MV_FALSE; -+ } -+ -+ if (pciData & PSCR_66MHZ_EN) -+ { -+ pPciAgent->is66MHZCapable=MV_TRUE; -+ } -+ else -+ { -+ pPciAgent->is66MHZCapable=MV_FALSE; -+ } -+ -+ /* Read Class Code and Revision */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_CLASS_CODE_AND_REVISION_ID); -+ -+ -+ pPciAgent->baseClassCode = -+ (pciData & PCCRIR_BASE_CLASS_MASK) >> PCCRIR_BASE_CLASS_OFFS; -+ -+ pPciAgent->subClassCode = -+ (pciData & PCCRIR_SUB_CLASS_MASK) >> PCCRIR_SUB_CLASS_OFFS; -+ -+ pPciAgent->progIf = -+ (pciData & PCCRIR_PROGIF_MASK) >> PCCRIR_PROGIF_OFFS; -+ -+ pPciAgent->revisionID = -+ (pciData & PCCRIR_REVID_MASK) >> PCCRIR_REVID_OFFS; -+ -+ /* Read PCI_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE); -+ -+ -+ -+ pPciAgent->pciCacheLine= -+ (pciData & PBHTLTCLR_CACHELINE_MASK ) >> PBHTLTCLR_CACHELINE_OFFS; -+ pPciAgent->pciLatencyTimer= -+ (pciData & PBHTLTCLR_LATTIMER_MASK) >> PBHTLTCLR_LATTIMER_OFFS; -+ -+ switch (pciData & PBHTLTCLR_HEADER_MASK) -+ { -+ case PBHTLTCLR_HEADER_STANDARD: -+ -+ pPciAgent->pciHeader=MV_PCI_STANDARD; -+ break; -+ case PBHTLTCLR_HEADER_PCI2PCI_BRIDGE: -+ -+ pPciAgent->pciHeader=MV_PCI_PCI2PCI_BRIDGE; -+ break; -+ -+ } -+ -+ if (pciData & PBHTLTCLR_MULTI_FUNC) -+ { -+ pPciAgent->isMultiFunction=MV_TRUE; -+ } -+ else -+ { -+ pPciAgent->isMultiFunction=MV_FALSE; -+ } -+ -+ if (pciData & PBHTLTCLR_BISTCAP) -+ { -+ pPciAgent->isBISTCapable=MV_TRUE; -+ } -+ else -+ { -+ pPciAgent->isBISTCapable=MV_FALSE; -+ } -+ -+ -+ /* read this device pci bars */ -+ -+ pciDetectDeviceBars(pciIf, -+ bus,dev,func, -+ pPciAgent); -+ -+ -+ /* check if we are bridge*/ -+ if ((pPciAgent->baseClassCode == PCI_BRIDGE_CLASS)&& -+ (pPciAgent->subClassCode == P2P_BRIDGE_SUB_CLASS_CODE)) -+ { -+ -+ /* Read P2P_BUSSES_NUM */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ P2P_BUSSES_NUM); -+ -+ pPciAgent->p2pPrimBusNum = -+ (pciData & PBM_PRIME_BUS_NUM_MASK) >> PBM_PRIME_BUS_NUM_OFFS; -+ -+ pPciAgent->p2pSecBusNum = -+ (pciData & PBM_SEC_BUS_NUM_MASK) >> PBM_SEC_BUS_NUM_OFFS; -+ -+ pPciAgent->p2pSubBusNum = -+ (pciData & PBM_SUB_BUS_NUM_MASK) >> PBM_SUB_BUS_NUM_OFFS; -+ -+ pPciAgent->p2pSecLatencyTimer = -+ (pciData & PBM_SEC_LAT_TMR_MASK) >> PBM_SEC_LAT_TMR_OFFS; -+ -+ /* Read P2P_IO_BASE_LIMIT_SEC_STATUS */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ P2P_IO_BASE_LIMIT_SEC_STATUS); -+ -+ pPciAgent->p2pSecStatus = -+ (pciData & PIBLSS_SEC_STATUS_MASK) >> PIBLSS_SEC_STATUS_OFFS; -+ -+ -+ pPciAgent->p2pIObase = -+ (pciData & PIBLSS_IO_BASE_MASK) << PIBLSS_IO_LIMIT_OFFS; -+ -+ /* clear low address (should be zero)*/ -+ pPciAgent->p2pIObase &= PIBLSS_HIGH_ADDR_MASK; -+ -+ pPciAgent->p2pIOLimit = -+ (pciData & PIBLSS_IO_LIMIT_MASK); -+ -+ /* fill low address with 0xfff */ -+ pPciAgent->p2pIOLimit |= PIBLSS_LOW_ADDR_MASK; -+ -+ -+ switch ((pciData & PIBLSS_ADD_CAP_MASK) >> PIBLSS_ADD_CAP_OFFS) -+ { -+ case PIBLSS_ADD_CAP_16BIT: -+ -+ pPciAgent->bIO32 = MV_FALSE; -+ -+ break; -+ case PIBLSS_ADD_CAP_32BIT: -+ -+ pPciAgent->bIO32 = MV_TRUE; -+ -+ /* Read P2P_IO_BASE_LIMIT_UPPER_16 */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ P2P_IO_BASE_LIMIT_UPPER_16); -+ -+ pPciAgent->p2pIObase |= -+ (pciData & PRBU_IO_UPP_BASE_MASK) << PRBU_IO_UPP_LIMIT_OFFS; -+ -+ -+ pPciAgent->p2pIOLimit |= -+ (pciData & PRBU_IO_UPP_LIMIT_MASK); -+ -+ break; -+ -+ } -+ -+ -+ /* Read P2P_MEM_BASE_LIMIT */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ P2P_MEM_BASE_LIMIT); -+ -+ pPciAgent->p2pMemBase = -+ (pciData & PMBL_MEM_BASE_MASK) << PMBL_MEM_LIMIT_OFFS; -+ -+ /* clear low address */ -+ pPciAgent->p2pMemBase &= PMBL_HIGH_ADDR_MASK; -+ -+ pPciAgent->p2pMemLimit = -+ (pciData & PMBL_MEM_LIMIT_MASK); -+ -+ /* add 0xfffff */ -+ pPciAgent->p2pMemLimit |= PMBL_LOW_ADDR_MASK; -+ -+ -+ /* Read P2P_PREF_MEM_BASE_LIMIT */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ P2P_PREF_MEM_BASE_LIMIT); -+ -+ -+ pPciAgent->p2pPrefMemBase = -+ (pciData & PRMBL_PREF_MEM_BASE_MASK) << PRMBL_PREF_MEM_LIMIT_OFFS; -+ -+ /* get high address only */ -+ pPciAgent->p2pPrefMemBase &= PRMBL_HIGH_ADDR_MASK; -+ -+ -+ -+ pPciAgent->p2pPrefMemLimit = -+ (pciData & PRMBL_PREF_MEM_LIMIT_MASK); -+ -+ /* add 0xfffff */ -+ pPciAgent->p2pPrefMemLimit |= PRMBL_LOW_ADDR_MASK; -+ -+ switch (pciData & PRMBL_ADD_CAP_MASK) -+ { -+ case PRMBL_ADD_CAP_32BIT: -+ -+ pPciAgent->bPrefMem64 = MV_FALSE; -+ -+ /* Read P2P_PREF_BASE_UPPER_32 */ -+ pPciAgent->p2pPrefBaseUpper32Bits = 0; -+ -+ /* Read P2P_PREF_LIMIT_UPPER_32 */ -+ pPciAgent->p2pPrefLimitUpper32Bits = 0; -+ -+ break; -+ case PRMBL_ADD_CAP_64BIT: -+ -+ pPciAgent->bPrefMem64 = MV_TRUE; -+ -+ /* Read P2P_PREF_BASE_UPPER_32 */ -+ pPciAgent->p2pPrefBaseUpper32Bits = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ P2P_PREF_BASE_UPPER_32); -+ -+ /* Read P2P_PREF_LIMIT_UPPER_32 */ -+ pPciAgent->p2pPrefLimitUpper32Bits = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ P2P_PREF_LIMIT_UPPER_32); -+ -+ break; -+ -+ } -+ -+ } -+ else /* no bridge */ -+ { -+ /* Read PCI_SUBSYS_ID_AND_SUBSYS_VENDOR_ID */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_SUBSYS_ID_AND_SUBSYS_VENDOR_ID); -+ -+ -+ pPciAgent->subSysVenID = -+ (pciData & PSISVIR_VENID_MASK) >> PSISVIR_VENID_OFFS; -+ pPciAgent->subSysID = -+ (pciData & PSISVIR_DEVID_MASK) >> PSISVIR_DEVID_OFFS; -+ -+ -+ /* Read PCI_EXPANSION_ROM_BASE_ADDR_REG */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_EXPANSION_ROM_BASE_ADDR_REG); -+ -+ -+ if (pciData & PERBAR_EXPROMEN) -+ { -+ pPciAgent->isExpRom = MV_TRUE; -+ } -+ else -+ { -+ pPciAgent->isExpRom = MV_FALSE; -+ } -+ -+ pPciAgent->expRomAddr = -+ (pciData & PERBAR_BASE_MASK) >> PERBAR_BASE_OFFS; -+ -+ } -+ -+ -+ if (MV_TRUE == pPciAgent->isCapListSupport) -+ { -+ /* Read PCI_CAPABILTY_LIST_POINTER */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_CAPABILTY_LIST_POINTER); -+ -+ pPciAgent->capListPointer = -+ (pciData & PCLPR_CAPPTR_MASK) >> PCLPR_CAPPTR_OFFS; -+ -+ } -+ -+ /* Read PCI_INTERRUPT_PIN_AND_LINE */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_INTERRUPT_PIN_AND_LINE); -+ -+ -+ pPciAgent->irqLine= -+ (pciData & PIPLR_INTLINE_MASK) >> PIPLR_INTLINE_OFFS; -+ -+ pPciAgent->intPin= -+ (MV_PCI_INT_PIN)(pciData & PIPLR_INTPIN_MASK) >> PIPLR_INTPIN_OFFS; -+ -+ pPciAgent->minGrant= -+ (pciData & PIPLR_MINGRANT_MASK) >> PIPLR_MINGRANT_OFFS; -+ pPciAgent->maxLatency= -+ (pciData & PIPLR_MAXLATEN_MASK) >> PIPLR_MAXLATEN_OFFS; -+ -+ mvPciClassNameGet(pPciAgent->baseClassCode, -+ (MV_8 *)pPciAgent->type); -+ -+ return MV_OK; -+ -+ -+} -+ -+/******************************************************************************* -+* pciDetectDeviceBars - Detect a pci device bars -+* -+* DESCRIPTION: -+* This function detects all pci agent bars -+* -+* INPUT: -+* pciIf - PCI Interface -+* bus - Bus number -+* dev - Device number -+* func - Function number -+* -+* -+* -+* OUTPUT: -+* pPciAgent - pointer to the pci agent filled with its information -+* -+* RETURN: -+* detected bars number -+* -+*******************************************************************************/ -+static MV_U32 pciDetectDeviceBars(MV_U32 pciIf, -+ MV_U32 bus, -+ MV_U32 dev, -+ MV_U32 func, -+ MV_PCI_DEVICE *pPciAgent) -+{ -+ MV_U32 pciData,barIndex,detectedBar=0; -+ MV_U32 tmpBaseHigh=0,tmpBaseLow=0; -+ MV_U32 pciMaxBars=0; -+ -+ pPciAgent->barsNum=0; -+ -+ /* check if we are bridge*/ -+ if ((pPciAgent->baseClassCode == PCI_BRIDGE_CLASS)&& -+ (pPciAgent->subClassCode == P2P_BRIDGE_SUB_CLASS_CODE)) -+ { -+ pciMaxBars = 2; -+ } -+ else /* no bridge */ -+ { -+ pciMaxBars = 6; -+ } -+ -+ /* read this device pci bars */ -+ for (barIndex = 0 ; barIndex < pciMaxBars ; barIndex++ ) -+ { -+ /* Read PCI_MEMORY_BAR_BASE_ADDR */ -+ tmpBaseLow = pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex)); -+ -+ pPciAgent->pciBar[detectedBar].barOffset = -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex); -+ -+ /* check if the bar is 32bit or 64bit bar */ -+ switch (pciData & PBBLR_TYPE_MASK) -+ { -+ case PBBLR_TYPE_32BIT_ADDR: -+ pPciAgent->pciBar[detectedBar].barType = PCI_32BIT_BAR; -+ break; -+ case PBBLR_TYPE_64BIT_ADDR: -+ pPciAgent->pciBar[detectedBar].barType = PCI_64BIT_BAR; -+ break; -+ -+ } -+ -+ /* check if it is memory or IO bar */ -+ if (pciData & PBBLR_IOSPACE) -+ { -+ pPciAgent->pciBar[detectedBar].barMapping=PCI_IO_BAR; -+ } -+ else -+ { -+ pPciAgent->pciBar[detectedBar].barMapping=PCI_MEMORY_BAR; -+ } -+ -+ /* if it is memory bar then check if it is prefetchable */ -+ if (PCI_MEMORY_BAR == pPciAgent->pciBar[detectedBar].barMapping) -+ { -+ if (pciData & PBBLR_PREFETCH_EN) -+ { -+ pPciAgent->pciBar[detectedBar].isPrefetchable = MV_TRUE; -+ } -+ else -+ { -+ pPciAgent->pciBar[detectedBar].isPrefetchable = MV_FALSE; -+ } -+ -+ pPciAgent->pciBar[detectedBar].barBaseLow = -+ pciData & PBBLR_MEM_BASE_MASK; -+ -+ -+ } -+ else /* IO Bar */ -+ { -+ pPciAgent->pciBar[detectedBar].barBaseLow = -+ pciData & PBBLR_IO_BASE_MASK; -+ -+ } -+ -+ pPciAgent->pciBar[detectedBar].barBaseHigh=0; -+ -+ if (PCI_64BIT_BAR == pPciAgent->pciBar[detectedBar].barType) -+ { -+ barIndex++; -+ -+ tmpBaseHigh = pPciAgent->pciBar[detectedBar].barBaseHigh = -+ mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex)); -+ -+ -+ } -+ -+ /* calculating full base address (64bit) */ -+ pPciAgent->pciBar[detectedBar].barBaseAddr = -+ (MV_U64)pPciAgent->pciBar[detectedBar].barBaseHigh; -+ -+ pPciAgent->pciBar[detectedBar].barBaseAddr <<= 32; -+ -+ pPciAgent->pciBar[detectedBar].barBaseAddr |= -+ (MV_U64)pPciAgent->pciBar[detectedBar].barBaseLow; -+ -+ -+ -+ /* get the sizes of the the bar */ -+ -+ pPciAgent->pciBar[detectedBar].barSizeHigh=0; -+ -+ if ((PCI_64BIT_BAR == pPciAgent->pciBar[detectedBar].barType) && -+ (PCI_MEMORY_BAR == pPciAgent->pciBar[detectedBar].barMapping)) -+ -+ { -+ /* write oxffffffff to the bar to get the size */ -+ /* start with sizelow ( original value was saved in tmpBaseLow ) */ -+ mvPciIfConfigWrite(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex-1), -+ 0xffffffff); -+ -+ /* read size */ -+ pPciAgent->pciBar[detectedBar].barSizeLow = -+ mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex-1)); -+ -+ -+ -+ /* restore original value */ -+ mvPciIfConfigWrite(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex-1), -+ tmpBaseLow); -+ -+ -+ /* now do the same for BaseHigh */ -+ -+ /* write oxffffffff to the bar to get the size */ -+ mvPciIfConfigWrite(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex), -+ 0xffffffff); -+ -+ /* read size */ -+ pPciAgent->pciBar[detectedBar].barSizeHigh = -+ mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex)); -+ -+ /* restore original value */ -+ mvPciIfConfigWrite(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex), -+ tmpBaseHigh); -+ -+ if ((0 == pPciAgent->pciBar[detectedBar].barSizeLow)&& -+ (0 == pPciAgent->pciBar[detectedBar].barSizeHigh)) -+ { -+ /* this bar is not applicable for this device, -+ ignore all previous settings and check the next bar*/ -+ -+ /* we though this was a 64bit bar , and it seems this -+ was wrong ! so decrement barIndex */ -+ barIndex--; -+ continue; -+ } -+ -+ /* calculate the full 64 bit size */ -+ -+ if (0 != pPciAgent->pciBar[detectedBar].barSizeHigh) -+ { -+ pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_MEM_BASE_MASK; -+ -+ pPciAgent->pciBar[detectedBar].barSizeLow = -+ ~pPciAgent->pciBar[detectedBar].barSizeLow + 1; -+ -+ pPciAgent->pciBar[detectedBar].barSizeHigh = 0; -+ -+ } -+ else -+ { -+ -+ pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_MEM_BASE_MASK; -+ -+ pPciAgent->pciBar[detectedBar].barSizeLow = -+ ~pPciAgent->pciBar[detectedBar].barSizeLow + 1; -+ -+ pPciAgent->pciBar[detectedBar].barSizeHigh = 0; -+ -+ } -+ -+ -+ -+ } -+ else /* 32bit bar */ -+ { -+ /* write oxffffffff to the bar to get the size */ -+ mvPciIfConfigWrite(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex), -+ 0xffffffff); -+ -+ /* read size */ -+ pPciAgent->pciBar[detectedBar].barSizeLow = -+ mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex)); -+ -+ if (0 == pPciAgent->pciBar[detectedBar].barSizeLow) -+ { -+ /* this bar is not applicable for this device, -+ ignore all previous settings and check the next bar*/ -+ continue; -+ } -+ -+ -+ /* restore original value */ -+ mvPciIfConfigWrite(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex), -+ tmpBaseLow); -+ -+ /* calculate size low */ -+ -+ if (PCI_MEMORY_BAR == pPciAgent->pciBar[detectedBar].barMapping) -+ { -+ pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_MEM_BASE_MASK; -+ } -+ else -+ { -+ pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_IO_BASE_MASK; -+ } -+ -+ pPciAgent->pciBar[detectedBar].barSizeLow = -+ ~pPciAgent->pciBar[detectedBar].barSizeLow + 1; -+ -+ pPciAgent->pciBar[detectedBar].barSizeHigh = 0; -+ pPciAgent->pciBar[detectedBar].barSize = -+ (MV_U64)pPciAgent->pciBar[detectedBar].barSizeLow; -+ -+ -+ } -+ -+ /* we are here ! this means we have already detected a bar for -+ this device , now move on */ -+ -+ detectedBar++; -+ pPciAgent->barsNum++; -+ } -+ -+ return detectedBar; -+} -+ -+ -+/******************************************************************************* -+* mvPciClassNameGet - get PCI class name -+* -+* DESCRIPTION: -+* This function returns the PCI class name -+* -+* INPUT: -+* baseClassCode - Base Class Code. -+* -+* OUTPUT: -+* pType - the class name -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciClassNameGet(MV_U32 baseClassCode, MV_8 *pType) -+{ -+ -+ switch(baseClassCode) -+ { -+ case 0x0: -+ strcpy(pType,"Old generation device"); -+ break; -+ case 0x1: -+ strcpy(pType,"Mass storage controller"); -+ break; -+ case 0x2: -+ strcpy(pType,"Network controller"); -+ break; -+ case 0x3: -+ strcpy(pType,"Display controller"); -+ break; -+ case 0x4: -+ strcpy(pType,"Multimedia device"); -+ break; -+ case 0x5: -+ strcpy(pType,"Memory controller"); -+ break; -+ case 0x6: -+ strcpy(pType,"Bridge Device"); -+ break; -+ case 0x7: -+ strcpy(pType,"Simple Communication controllers"); -+ break; -+ case 0x8: -+ strcpy(pType,"Base system peripherals"); -+ break; -+ case 0x9: -+ strcpy(pType,"Input Devices"); -+ break; -+ case 0xa: -+ strcpy(pType,"Docking stations"); -+ break; -+ case 0xb: -+ strcpy(pType,"Processors"); -+ break; -+ case 0xc: -+ strcpy(pType,"Serial bus controllers"); -+ break; -+ case 0xd: -+ strcpy(pType,"Wireless controllers"); -+ break; -+ case 0xe: -+ strcpy(pType,"Intelligent I/O controllers"); -+ break; -+ case 0xf: -+ strcpy(pType,"Satellite communication controllers"); -+ break; -+ case 0x10: -+ strcpy(pType,"Encryption/Decryption controllers"); -+ break; -+ case 0x11: -+ strcpy(pType,"Data acquisition and signal processing controllers"); -+ break; -+ default: -+ strcpy(pType,"Unknown device"); -+ break; -+ } -+ -+ return MV_OK; -+ -+} -+ -+ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.h 2010-11-09 20:28:11.662495451 +0100 -@@ -0,0 +1,323 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvPciUtilsh -+#define __INCmvPciUtilsh -+ -+/* -+This module only support scanning of Header type 00h of pci devices -+There is no suppotr for Header type 01h of pci devices ( PCI bridges ) -+*/ -+ -+/* includes */ -+#include "mvSysHwConfig.h" -+#include "pci-if/mvPciIf.h" -+#include "pci/mvPciRegs.h" -+ -+ -+ -+/* PCI base address low bar mask */ -+#define PCI_ERROR_CODE 0xffffffff -+ -+#define PCI_BRIDGE_CLASS 0x6 -+#define P2P_BRIDGE_SUB_CLASS_CODE 0x4 -+ -+ -+#define P2P_BUSSES_NUM 0x18 -+#define P2P_IO_BASE_LIMIT_SEC_STATUS 0x1C -+#define P2P_MEM_BASE_LIMIT 0x20 -+#define P2P_PREF_MEM_BASE_LIMIT 0x24 -+#define P2P_PREF_BASE_UPPER_32 0x28 -+#define P2P_PREF_LIMIT_UPPER_32 0x2C -+#define P2P_IO_BASE_LIMIT_UPPER_16 0x30 -+#define P2P_EXP_ROM 0x38 -+ -+/* P2P_BUSSES_NUM (PBM) */ -+ -+#define PBM_PRIME_BUS_NUM_OFFS 0 -+#define PBM_PRIME_BUS_NUM_MASK (0xff << PBM_PRIME_BUS_NUM_OFFS) -+ -+#define PBM_SEC_BUS_NUM_OFFS 8 -+#define PBM_SEC_BUS_NUM_MASK (0xff << PBM_SEC_BUS_NUM_OFFS) -+ -+#define PBM_SUB_BUS_NUM_OFFS 16 -+#define PBM_SUB_BUS_NUM_MASK (0xff << PBM_SUB_BUS_NUM_OFFS) -+ -+#define PBM_SEC_LAT_TMR_OFFS 24 -+#define PBM_SEC_LAT_TMR_MASK (0xff << PBM_SEC_LAT_TMR_OFFS) -+ -+/* P2P_IO_BASE_LIMIT_SEC_STATUS (PIBLSS) */ -+ -+#define PIBLSS_IO_BASE_OFFS 0 -+#define PIBLSS_IO_BASE_MASK (0xff << PIBLSS_IO_BASE_OFFS) -+ -+#define PIBLSS_ADD_CAP_OFFS 0 -+#define PIBLSS_ADD_CAP_MASK (0x3 << PIBLSS_ADD_CAP_OFFS) -+#define PIBLSS_ADD_CAP_16BIT (0x0 << PIBLSS_ADD_CAP_OFFS) -+#define PIBLSS_ADD_CAP_32BIT (0x1 << PIBLSS_ADD_CAP_OFFS) -+ -+#define PIBLSS_LOW_ADDR_OFFS 0 -+#define PIBLSS_LOW_ADDR_MASK (0xFFF << PIBLSS_LOW_ADDR_OFFS) -+ -+#define PIBLSS_HIGH_ADDR_OFFS 12 -+#define PIBLSS_HIGH_ADDR_MASK (0xF << PIBLSS_HIGH_ADDR_OFFS) -+ -+#define PIBLSS_IO_LIMIT_OFFS 8 -+#define PIBLSS_IO_LIMIT_MASK (0xff << PIBLSS_IO_LIMIT_OFFS) -+ -+#define PIBLSS_SEC_STATUS_OFFS 16 -+#define PIBLSS_SEC_STATUS_MASK (0xffff << PIBLSS_SEC_STATUS_OFFS) -+ -+ -+/* P2P_MEM_BASE_LIMIT (PMBL)*/ -+ -+#define PMBL_MEM_BASE_OFFS 0 -+#define PMBL_MEM_BASE_MASK (0xffff << PMBL_MEM_BASE_OFFS) -+ -+#define PMBL_MEM_LIMIT_OFFS 16 -+#define PMBL_MEM_LIMIT_MASK (0xffff << PMBL_MEM_LIMIT_OFFS) -+ -+ -+#define PMBL_LOW_ADDR_OFFS 0 -+#define PMBL_LOW_ADDR_MASK (0xFFFFF << PMBL_LOW_ADDR_OFFS) -+ -+#define PMBL_HIGH_ADDR_OFFS 20 -+#define PMBL_HIGH_ADDR_MASK (0xFFF << PMBL_HIGH_ADDR_OFFS) -+ -+ -+/* P2P_PREF_MEM_BASE_LIMIT (PRMBL) */ -+ -+#define PRMBL_PREF_MEM_BASE_OFFS 0 -+#define PRMBL_PREF_MEM_BASE_MASK (0xffff << PRMBL_PREF_MEM_BASE_OFFS) -+ -+#define PRMBL_PREF_MEM_LIMIT_OFFS 16 -+#define PRMBL_PREF_MEM_LIMIT_MASK (0xffff<= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexModeGet: ERR. Invalid PEX interface %d\n",pexIf); -+ return MV_ERROR; -+ } -+ } -+ -+ pexData = MV_REG_READ(PEX_CTRL_REG(pexIf)); -+ -+ switch (pexData & PXCR_DEV_TYPE_CTRL_MASK) -+ { -+ case PXCR_DEV_TYPE_CTRL_CMPLX: -+ pexMode->pexType = MV_PEX_ROOT_COMPLEX; -+ break; -+ case PXCR_DEV_TYPE_CTRL_POINT: -+ pexMode->pexType = MV_PEX_END_POINT; -+ break; -+ -+ } -+ -+ /* Check if we have link */ -+ if (MV_REG_READ(PEX_STATUS_REG(pexIf)) & PXSR_DL_DOWN) -+ { -+ pexMode->pexLinkUp = MV_FALSE; -+ -+ /* If there is no link, the auto negotiation data is worthless */ -+ pexMode->pexWidth = MV_PEX_WITDH_INVALID; -+ } -+ else -+ { -+ pexMode->pexLinkUp = MV_TRUE; -+ -+ /* We have link. The link width is now valid */ -+ pexData = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG)); -+ pexMode->pexWidth = ((pexData & PXLCSR_NEG_LNK_WDTH_MASK) >> -+ PXLCSR_NEG_LNK_WDTH_OFFS); -+ } -+ -+ return MV_OK; -+} -+ -+ -+/* PEX configuration space read write */ -+ -+/******************************************************************************* -+* mvPexConfigRead - Read from configuration space -+* -+* DESCRIPTION: -+* This function performs a 32 bit read from PEX configuration space. -+* It supports both type 0 and type 1 of Configuration Transactions -+* (local and over bridge). In order to read from local bus segment, use -+* bus number retrieved from mvPexLocalBusNumGet(). Other bus numbers -+* will result configuration transaction of type 1 (over bridge). -+* -+* INPUT: -+* pexIf - PEX interface number. -+* bus - PEX segment bus number. -+* dev - PEX device number. -+* func - Function number. -+* regOffs - Register offset. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit register data, 0xffffffff on error -+* -+*******************************************************************************/ -+MV_U32 mvPexConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, -+ MV_U32 regOff) -+{ -+#if defined(PCIE_VIRTUAL_BRIDGE_SUPPORT) -+ return mvPexVrtBrgConfigRead (pexIf, bus, dev, func, regOff); -+} -+ -+MV_U32 mvPexHwConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, -+ MV_U32 regOff) -+{ -+#endif -+ MV_U32 pexData = 0; -+ MV_U32 localDev,localBus; -+ -+ /* Parameter checking */ -+ if (PEX_DEFAULT_IF != pexIf) -+ { -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexConfigRead: ERR. Invalid PEX interface %d\n",pexIf); -+ return 0xFFFFFFFF; -+ } -+ } -+ -+ if (dev >= MAX_PEX_DEVICES) -+ { -+ DB(mvOsPrintf("mvPexConfigRead: ERR. device number illigal %d\n", dev)); -+ return 0xFFFFFFFF; -+ } -+ -+ if (func >= MAX_PEX_FUNCS) -+ { -+ DB(mvOsPrintf("mvPexConfigRead: ERR. function num illigal %d\n", func)); -+ return 0xFFFFFFFF; -+ } -+ -+ if (bus >= MAX_PEX_BUSSES) -+ { -+ DB(mvOsPrintf("mvPexConfigRead: ERR. bus number illigal %d\n", bus)); -+ return MV_ERROR; -+ } -+ -+ DB(mvOsPrintf("mvPexConfigRead: pexIf %d, bus %d, dev %d, func %d, regOff 0x%x\n", -+ pexIf, bus, dev, func, regOff)); -+ -+ localDev = mvPexLocalDevNumGet(pexIf); -+ localBus = mvPexLocalBusNumGet(pexIf); -+ -+ /* Speed up the process. In case on no link, return MV_ERROR */ -+ if ((dev != localDev) || (bus != localBus)) -+ { -+ pexData = MV_REG_READ(PEX_STATUS_REG(pexIf)); -+ -+ if ((pexData & PXSR_DL_DOWN)) -+ { -+ return MV_ERROR; -+ } -+ } -+ -+ /* in PCI Express we have only one device number */ -+ /* and this number is the first number we encounter -+ else that the localDev*/ -+ /* spec pex define return on config read/write on any device */ -+ if (bus == localBus) -+ { -+ if (localDev == 0) -+ { -+ /* if local dev is 0 then the first number we encounter -+ after 0 is 1 */ -+ if ((dev != 1)&&(dev != localDev)) -+ { -+ return MV_ERROR; -+ } -+ } -+ else -+ { -+ /* if local dev is not 0 then the first number we encounter -+ is 0 */ -+ -+ if ((dev != 0)&&(dev != localDev)) -+ { -+ return MV_ERROR; -+ } -+ } -+ if(func != 0 ) /* i.e bridge */ -+ { -+ return MV_ERROR; -+ } -+ } -+ -+ -+ /* Creating PEX address to be passed */ -+ pexData = (bus << PXCAR_BUS_NUM_OFFS); -+ pexData |= (dev << PXCAR_DEVICE_NUM_OFFS); -+ pexData |= (func << PXCAR_FUNC_NUM_OFFS); -+ pexData |= (regOff & PXCAR_REG_NUM_MASK); /* lgacy register space */ -+ /* extended register space */ -+ pexData |=(((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >> -+ PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS); -+ -+ pexData |= PXCAR_CONFIG_EN; -+ -+ /* Write the address to the PEX configuration address register */ -+ MV_REG_WRITE(PEX_CFG_ADDR_REG(pexIf), pexData); -+ -+ DB(mvOsPrintf("mvPexConfigRead:address pexData=%x ",pexData)); -+ -+ -+ /* In order to let the PEX controller absorbed the address of the read */ -+ /* transaction we perform a validity check that the address was written */ -+ if(pexData != MV_REG_READ(PEX_CFG_ADDR_REG(pexIf))) -+ { -+ return MV_ERROR; -+ } -+ -+ /* cleaning Master Abort */ -+ MV_REG_BIT_SET(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_STATUS_AND_COMMAND), -+ PXSAC_MABORT); -+#if 0 -+ /* Guideline (GL# PCI Express-1) Erroneous Read Data on Configuration */ -+ /* This guideline is relevant for all devices except of the following devices: -+ 88F5281-BO and above, 88F5181L-A0 and above, 88F1281 A0 and above -+ 88F6183 A0 and above, 88F6183L */ -+ if ( ( (dev != localDev) || (bus != localBus) ) && -+ ( -+ !(MV_5281_DEV_ID == mvCtrlModelGet())&& -+ !((MV_5181_DEV_ID == mvCtrlModelGet())&& (mvCtrlRevGet() >= MV_5181L_A0_REV))&& -+ !(MV_1281_DEV_ID == mvCtrlModelGet())&& -+ !(MV_6183_DEV_ID == mvCtrlModelGet())&& -+ !(MV_6183L_DEV_ID == mvCtrlModelGet())&& -+ !(MV_6281_DEV_ID == mvCtrlModelGet())&& -+ !(MV_6192_DEV_ID == mvCtrlModelGet())&& -+ !(MV_6190_DEV_ID == mvCtrlModelGet())&& -+ !(MV_6180_DEV_ID == mvCtrlModelGet())&& -+ !(MV_78XX0_DEV_ID == mvCtrlModelGet()) -+ )) -+ { -+ -+ /* PCI-Express configuration read work-around */ -+ -+ /* we will use one of the Punit (AHBToMbus) windows to access the xbar -+ and read the data from there */ -+ /* -+ Need to configure the 2 free Punit (AHB to MBus bridge) -+ address decoding windows: -+ Configure the flash Window to handle Configuration space requests -+ for PEX0/1: -+ 1. write 0x7931/0x7941 to the flash window and the size, -+ 79-xbar attr (pci cfg), 3/4-xbar target (pex0/1), 1-WinEn -+ 2. write base to flash window -+ -+ Configuration transactions from the CPU should write/read the data -+ to/from address of the form: -+ addr[31:28] = 0x5 (for PEX0) or 0x6 (for PEX1) -+ addr[27:24] = extended register number -+ addr[23:16] = bus number -+ addr[15:11] = device number -+ addr[10:8] = function number -+ addr[7:0] = register number -+ */ -+ -+ #include "ctrlEnv/sys/mvAhbToMbus.h" -+ { -+ MV_U32 winNum; -+ MV_AHB_TO_MBUS_DEC_WIN originWin; -+ MV_U32 pciAddr=0; -+ MV_U32 remapLow=0,remapHigh=0; -+ -+ /* -+ We will use DEV_CS2\Flash window for this workarround -+ */ -+ -+ winNum = mvAhbToMbusWinTargetGet(PEX_CONFIG_RW_WA_TARGET); -+ -+ /* save remap values if exist */ -+ if ((1 == winNum)||(0 == winNum)) -+ { -+ remapLow = MV_REG_READ(AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum)); -+ remapHigh = MV_REG_READ(AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum)); -+ -+ } -+ -+ -+ /* save the original window values */ -+ mvAhbToMbusWinGet(winNum,&originWin); -+ -+ if (PEX_CONFIG_RW_WA_USE_ORIGINAL_WIN_VALUES) -+ { -+ /* set the window as xbar window */ -+ if (pexIf) -+ { -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), -+ (0x7931 | (((originWin.addrWin.size >> 16)-1) ) << 16)); -+ } -+ else -+ { -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), -+ (0x7941 | (((originWin.addrWin.size >> 16)-1) ) << 16)); -+ } -+ -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum), -+ originWin.addrWin.baseLow); -+ -+ /*pciAddr = originWin.addrWin.baseLow;*/ -+ pciAddr = (MV_U32)CPU_MEMIO_UNCACHED_ADDR( -+ (MV_U32)originWin.addrWin.baseLow); -+ -+ } -+ else -+ { -+ /* set the window as xbar window */ -+ if (pexIf) -+ { -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), -+ (0x7931 | (((PEX_CONFIG_RW_WA_SIZE >> 16)-1) ) << 16)); -+ } -+ else -+ { -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), -+ (0x7941 | (((PEX_CONFIG_RW_WA_SIZE >> 16)-1) ) << 16)); -+ } -+ -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum), -+ PEX_CONFIG_RW_WA_BASE); -+ -+ pciAddr = (MV_U32)CPU_MEMIO_UNCACHED_ADDR(PEX_CONFIG_RW_WA_BASE); -+ } -+ -+ -+ /* remap should be as base */ -+ if ((1 == winNum)||(0 == winNum)) -+ { -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum),pciAddr); -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum),0); -+ -+ } -+ -+ /* extended register space */ -+ pciAddr |= (bus << 16); -+ pciAddr |= (dev << 11); -+ pciAddr |= (func << 8); -+ pciAddr |= (regOff & PXCAR_REG_NUM_MASK); /* lgacy register space */ -+ -+ pexData = *(MV_U32*)pciAddr; -+ pexData = MV_32BIT_LE(pexData); /* Data always in LE */ -+ -+ /* restore the original window values */ -+ mvAhbToMbusWinSet(winNum,&originWin); -+ -+ /* restore original remap values*/ -+ if ((1 == winNum)||(0 == winNum)) -+ { -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum),remapLow); -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum),remapHigh); -+ -+ } -+ } -+ } -+ else -+#endif -+ { -+ /* Read the Data returned in the PEX Data register */ -+ pexData = MV_REG_READ(PEX_CFG_DATA_REG(pexIf)); -+ -+ } -+ -+ DB(mvOsPrintf("mvPexConfigRead: got : %x \n",pexData)); -+ -+ return pexData; -+ -+} -+ -+/******************************************************************************* -+* mvPexConfigWrite - Write to configuration space -+* -+* DESCRIPTION: -+* This function performs a 32 bit write to PEX configuration space. -+* It supports both type 0 and type 1 of Configuration Transactions -+* (local and over bridge). In order to write to local bus segment, use -+* bus number retrieved from mvPexLocalBusNumGet(). Other bus numbers -+* will result configuration transaction of type 1 (over bridge). -+* -+* INPUT: -+* pexIf - PEX interface number. -+* bus - PEX segment bus number. -+* dev - PEX device number. -+* func - Function number. -+* regOffs - Register offset. -+* data - 32bit data. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data) -+{ -+#if defined(PCIE_VIRTUAL_BRIDGE_SUPPORT) -+ return mvPexVrtBrgConfigWrite (pexIf, bus, dev, func, regOff, data); -+} -+ -+MV_STATUS mvPexHwConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data) -+{ -+#endif -+ MV_U32 pexData = 0; -+ MV_U32 localDev,localBus; -+ -+ /* Parameter checking */ -+ if (PEX_DEFAULT_IF != pexIf) -+ { -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexConfigWrite: ERR. Invalid PEX interface %d\n", -+ pexIf); -+ return MV_ERROR; -+ } -+ } -+ -+ if (dev >= MAX_PEX_DEVICES) -+ { -+ mvOsPrintf("mvPexConfigWrite: ERR. device number illigal %d\n",dev); -+ return MV_BAD_PARAM; -+ } -+ -+ if (func >= MAX_PEX_FUNCS) -+ { -+ mvOsPrintf("mvPexConfigWrite: ERR. function number illigal %d\n", func); -+ return MV_ERROR; -+ } -+ -+ if (bus >= MAX_PEX_BUSSES) -+ { -+ mvOsPrintf("mvPexConfigWrite: ERR. bus number illigal %d\n", bus); -+ return MV_ERROR; -+ } -+ -+ -+ -+ localDev = mvPexLocalDevNumGet(pexIf); -+ localBus = mvPexLocalBusNumGet(pexIf); -+ -+ -+ /* in PCI Express we have only one device number other than ourselves*/ -+ /* and this number is the first number we encounter -+ else than the localDev that can be any valid dev number*/ -+ /* pex spec define return on config read/write on any device */ -+ if (bus == localBus) -+ { -+ -+ if (localDev == 0) -+ { -+ /* if local dev is 0 then the first number we encounter -+ after 0 is 1 */ -+ if ((dev != 1)&&(dev != localDev)) -+ { -+ return MV_ERROR; -+ } -+ -+ } -+ else -+ { -+ /* if local dev is not 0 then the first number we encounter -+ is 0 */ -+ -+ if ((dev != 0)&&(dev != localDev)) -+ { -+ return MV_ERROR; -+ } -+ } -+ -+ -+ } -+ -+ /* if we are not accessing ourselves , then check the link */ -+ if ((dev != localDev) || (bus != localBus) ) -+ { -+ /* workarround */ -+ /* when no link return MV_ERROR */ -+ -+ pexData = MV_REG_READ(PEX_STATUS_REG(pexIf)); -+ -+ if ((pexData & PXSR_DL_DOWN)) -+ { -+ return MV_ERROR; -+ } -+ -+ } -+ -+ pexData =0; -+ -+ /* Creating PEX address to be passed */ -+ pexData |= (bus << PXCAR_BUS_NUM_OFFS); -+ pexData |= (dev << PXCAR_DEVICE_NUM_OFFS); -+ pexData |= (func << PXCAR_FUNC_NUM_OFFS); -+ pexData |= (regOff & PXCAR_REG_NUM_MASK); /* lgacy register space */ -+ /* extended register space */ -+ pexData |=(((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >> -+ PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS); -+ pexData |= PXCAR_CONFIG_EN; -+ -+ DB(mvOsPrintf("mvPexConfigWrite: If=%x bus=%x func=%x dev=%x regOff=%x data=%x \n", -+ pexIf,bus,func,dev,regOff,data,pexData) ); -+ -+ /* Write the address to the PEX configuration address register */ -+ MV_REG_WRITE(PEX_CFG_ADDR_REG(pexIf), pexData); -+ -+ /* Clear CPU pipe. Important where CPU can perform OOO execution */ -+ CPU_PIPE_FLUSH; -+ -+ /* In order to let the PEX controller absorbed the address of the read */ -+ /* transaction we perform a validity check that the address was written */ -+ if(pexData != MV_REG_READ(PEX_CFG_ADDR_REG(pexIf))) -+ { -+ return MV_ERROR; -+ } -+ -+ /* Write the Data passed to the PEX Data register */ -+ MV_REG_WRITE(PEX_CFG_DATA_REG(pexIf), data); -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvPexMasterEnable - Enable/disale PEX interface master transactions. -+* -+* DESCRIPTION: -+* This function performs read modified write to PEX command status -+* (offset 0x4) to set/reset bit 2. After this bit is set, the PEX -+* master is allowed to gain ownership on the bus, otherwise it is -+* incapable to do so. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexMasterEnable(MV_U32 pexIf, MV_BOOL enable) -+{ -+ MV_U32 pexCommandStatus; -+ MV_U32 localBus; -+ MV_U32 localDev; -+ -+ /* Parameter checking */ -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexMasterEnable: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_ERROR; -+ } -+ -+ localBus = mvPexLocalBusNumGet(pexIf); -+ localDev = mvPexLocalDevNumGet(pexIf); -+ -+ pexCommandStatus = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, -+ PEX_STATUS_AND_COMMAND)); -+ -+ -+ if (MV_TRUE == enable) -+ { -+ pexCommandStatus |= PXSAC_MASTER_EN; -+ } -+ else -+ { -+ pexCommandStatus &= ~PXSAC_MASTER_EN; -+ } -+ -+ -+ MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_STATUS_AND_COMMAND), -+ pexCommandStatus); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPexSlaveEnable - Enable/disale PEX interface slave transactions. -+* -+* DESCRIPTION: -+* This function performs read modified write to PEX command status -+* (offset 0x4) to set/reset bit 0 and 1. After those bits are set, -+* the PEX slave is allowed to respond to PEX IO space access (bit 0) -+* and PEX memory space access (bit 1). -+* -+* INPUT: -+* pexIf - PEX interface number. -+* dev - PEX device number. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexSlaveEnable(MV_U32 pexIf, MV_U32 bus,MV_U32 dev, MV_BOOL enable) -+{ -+ MV_U32 pexCommandStatus; -+ MV_U32 RegOffs; -+ -+ /* Parameter checking */ -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexSlaveEnable: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ if (dev >= MAX_PEX_DEVICES) -+ { -+ mvOsPrintf("mvPexLocalDevNumSet: ERR. device number illigal %d\n", dev); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ -+ RegOffs = PEX_STATUS_AND_COMMAND; -+ -+ pexCommandStatus = mvPexConfigRead(pexIf, bus, dev, 0, RegOffs); -+ -+ if (MV_TRUE == enable) -+ { -+ pexCommandStatus |= (PXSAC_IO_EN | PXSAC_MEM_EN); -+ } -+ else -+ { -+ pexCommandStatus &= ~(PXSAC_IO_EN | PXSAC_MEM_EN); -+ } -+ -+ mvPexConfigWrite(pexIf, bus, dev, 0, RegOffs, pexCommandStatus); -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvPexLocalBusNumSet - Set PEX interface local bus number. -+* -+* DESCRIPTION: -+* This function sets given PEX interface its local bus number. -+* Note: In case the PEX interface is PEX-X, the information is read-only. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* busNum - Bus number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_NOT_ALLOWED in case PEX interface is PEX-X. -+* MV_BAD_PARAM on bad parameters , -+* otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexLocalBusNumSet(MV_U32 pexIf, MV_U32 busNum) -+{ -+ MV_U32 pexStatus; -+ MV_U32 localBus; -+ MV_U32 localDev; -+ -+ -+ /* Parameter checking */ -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexLocalBusNumSet: ERR. Invalid PEX interface %d\n",pexIf); -+ return MV_BAD_PARAM; -+ } -+ if (busNum >= MAX_PEX_BUSSES) -+ { -+ mvOsPrintf("mvPexLocalBusNumSet: ERR. bus number illigal %d\n", busNum); -+ return MV_ERROR; -+ -+ } -+ -+ localBus = mvPexLocalBusNumGet(pexIf); -+ localDev = mvPexLocalDevNumGet(pexIf); -+ -+ -+ -+ pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); -+ -+ pexStatus &= ~PXSR_PEX_BUS_NUM_MASK; -+ -+ pexStatus |= (busNum << PXSR_PEX_BUS_NUM_OFFS) & PXSR_PEX_BUS_NUM_MASK; -+ -+ MV_REG_WRITE(PEX_STATUS_REG(pexIf), pexStatus); -+ -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPexLocalBusNumGet - Get PEX interface local bus number. -+* -+* DESCRIPTION: -+* This function gets the local bus number of a given PEX interface. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Local bus number.0xffffffff on Error -+* -+*******************************************************************************/ -+MV_U32 mvPexLocalBusNumGet(MV_U32 pexIf) -+{ -+ MV_U32 pexStatus; -+ -+ /* Parameter checking */ -+ if (PEX_DEFAULT_IF != pexIf) -+ { -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexLocalBusNumGet: ERR. Invalid PEX interface %d\n",pexIf); -+ return 0xFFFFFFFF; -+ } -+ } -+ -+ -+ pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); -+ -+ pexStatus &= PXSR_PEX_BUS_NUM_MASK; -+ -+ return (pexStatus >> PXSR_PEX_BUS_NUM_OFFS); -+ -+} -+ -+ -+/******************************************************************************* -+* mvPexLocalDevNumSet - Set PEX interface local device number. -+* -+* DESCRIPTION: -+* This function sets given PEX interface its local device number. -+* Note: In case the PEX interface is PEX-X, the information is read-only. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* devNum - Device number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_NOT_ALLOWED in case PEX interface is PEX-X. -+* MV_BAD_PARAM on bad parameters , -+* otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexLocalDevNumSet(MV_U32 pexIf, MV_U32 devNum) -+{ -+ MV_U32 pexStatus; -+ MV_U32 localBus; -+ MV_U32 localDev; -+ -+ /* Parameter checking */ -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexLocalDevNumSet: ERR. Invalid PEX interface %d\n",pexIf); -+ return MV_BAD_PARAM; -+ } -+ if (devNum >= MAX_PEX_DEVICES) -+ { -+ mvOsPrintf("mvPexLocalDevNumSet: ERR. device number illigal %d\n", -+ devNum); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ localBus = mvPexLocalBusNumGet(pexIf); -+ localDev = mvPexLocalDevNumGet(pexIf); -+ -+ -+ pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); -+ -+ pexStatus &= ~PXSR_PEX_DEV_NUM_MASK; -+ -+ pexStatus |= (devNum << PXSR_PEX_DEV_NUM_OFFS) & PXSR_PEX_DEV_NUM_MASK; -+ -+ MV_REG_WRITE(PEX_STATUS_REG(pexIf), pexStatus); -+ -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvPexLocalDevNumGet - Get PEX interface local device number. -+* -+* DESCRIPTION: -+* This function gets the local device number of a given PEX interface. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Local device number. 0xffffffff on Error -+* -+*******************************************************************************/ -+MV_U32 mvPexLocalDevNumGet(MV_U32 pexIf) -+{ -+ MV_U32 pexStatus; -+ -+ /* Parameter checking */ -+ -+ if (PEX_DEFAULT_IF != pexIf) -+ { -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexLocalDevNumGet: ERR. Invalid PEX interface %d\n", -+ pexIf); -+ return 0xFFFFFFFF; -+ } -+ } -+ -+ pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); -+ -+ pexStatus &= PXSR_PEX_DEV_NUM_MASK; -+ -+ return (pexStatus >> PXSR_PEX_DEV_NUM_OFFS); -+} -+ -+MV_VOID mvPexPhyRegRead(MV_U32 pexIf, MV_U32 regOffset, MV_U16 *value) -+{ -+ -+ MV_U32 regAddr; -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexPhyRegRead: ERR. Invalid PEX interface %d\n", pexIf); -+ return; -+ } -+ regAddr = (BIT31 | ((regOffset & 0x3fff) << 16)); -+ MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexIf), regAddr); -+ *value = MV_REG_READ(PEX_PHY_ACCESS_REG(pexIf)); -+} -+ -+ -+MV_VOID mvPexPhyRegWrite(MV_U32 pexIf, MV_U32 regOffset, MV_U16 value) -+{ -+ -+ MV_U32 regAddr; -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexPhyRegWrite: ERR. Invalid PEX interface %d\n", pexIf); -+ return; -+ } -+ regAddr = (((regOffset & 0x3fff) << 16) | value); -+ MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexIf), regAddr); -+} -+ -+/******************************************************************************* -+* mvPexActiveStateLinkPMEnable -+* -+* DESCRIPTION: -+* Enable Active Link State Power Management -+* -+* INPUT: -+* pexIf - PEX interface number. -+* enable - MV_TRUE to enable ASPM, MV_FALSE to disable. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* MV_OK on success , MV_ERROR otherwise -+* -+*******************************************************************************/ -+MV_STATUS mvPexActiveStateLinkPMEnable(MV_U32 pexIf, MV_BOOL enable) -+{ -+ MV_U32 reg; -+ -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexActiveStateLinkPMEnable: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_ERROR; -+ } -+ -+ reg = MV_REG_READ(PEX_PWR_MNG_EXT_REG(pexIf)) & ~PXPMER_L1_ASPM_EN_MASK; -+ if(enable == MV_TRUE) -+ reg |= PXPMER_L1_ASPM_EN_MASK; -+ MV_REG_WRITE(PEX_PWR_MNG_EXT_REG(pexIf), reg); -+ -+ /* Enable / Disable L0/1 entry */ -+ reg = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG)) -+ & ~PXLCSR_ASPM_CNT_MASK; -+ if(enable == MV_TRUE) -+ reg |= PXLCSR_ASPM_CNT_L0S_L1S_ENT_SUPP; -+ MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG), reg); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPexForceX1 -+* -+* DESCRIPTION: -+* shut down lanes 1-3 if recognize that attached to an x1 end-point -+* INPUT: -+* pexIf - PEX interface number. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* MV_OK on success , MV_ERROR otherwise -+* -+*******************************************************************************/ -+MV_U32 mvPexForceX1(MV_U32 pexIf) -+{ -+ MV_U32 regData = 0; -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexForceX1: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ -+ regData = MV_REG_READ(PEX_CTRL_REG(pexIf)) & ~(PXCR_CONF_LINK_MASK) ; -+ regData |= PXCR_CONF_LINK_X1; -+ -+ MV_REG_WRITE(PEX_CTRL_REG(pexIf), regData); -+ return MV_OK; -+} -+ -+MV_BOOL mvPexIsPowerUp(MV_U32 pexIf) -+{ -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexIsPowerUp: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_FALSE; -+ } -+ return mvCtrlPwrClckGet(PEX_UNIT_ID, pexIf); -+} -+ -+ -+MV_VOID mvPexPowerDown(MV_U32 pexIf) -+{ -+ if ( (mvCtrlModelGet() == MV_78XX0_DEV_ID) || -+ (mvCtrlModelGet() == MV_76100_DEV_ID) || -+ (mvCtrlModelGet() == MV_78100_DEV_ID) || -+ (mvCtrlModelGet() == MV_78200_DEV_ID) ) -+ { -+ mvCtrlPwrClckSet(PEX_UNIT_ID, pexIf, MV_FALSE); -+ } -+ else -+ { -+ MV_REG_WRITE((0x41B00 -(pexIf)*0x10000), 0x20800087); -+ } -+} -+ -+ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h 2010-11-09 20:28:11.742495415 +0100 -@@ -0,0 +1,168 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCPEXH -+#define __INCPEXH -+ -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "pex/mvPexRegs.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+ -+ -+ -+/* NOTE not supported in this driver:*/ -+ -+ -+/* defines */ -+/* The number of supported PEX interfaces depend on Marvell controller */ -+/* device number. This device number ID is located on the PEX unit */ -+/* configuration header. This creates a loop where calling PEX */ -+/* configuration read/write routine results a call to get PEX configuration */ -+/* information etc. This macro defines a default PEX interface. This PEX */ -+/* interface is sure to exist. */ -+#define PEX_DEFAULT_IF 0 -+ -+ -+/* typedefs */ -+/* The Marvell controller supports both root complex and end point devices */ -+/* This enumeration describes the PEX type. */ -+typedef enum _mvPexType -+{ -+ MV_PEX_ROOT_COMPLEX, /* root complex device */ -+ MV_PEX_END_POINT /* end point device */ -+}MV_PEX_TYPE; -+ -+typedef enum _mvPexWidth -+{ -+ MV_PEX_WITDH_X1 = 1, -+ MV_PEX_WITDH_X2, -+ MV_PEX_WITDH_X3, -+ MV_PEX_WITDH_X4, -+ MV_PEX_WITDH_INVALID -+}MV_PEX_WIDTH; -+ -+/* PEX Bar attributes */ -+typedef struct _mvPexMode -+{ -+ MV_PEX_TYPE pexType; -+ MV_PEX_WIDTH pexWidth; -+ MV_BOOL pexLinkUp; -+}MV_PEX_MODE; -+ -+ -+ -+/* Global Functions prototypes */ -+/* mvPexInit - Initialize PEX interfaces*/ -+MV_STATUS mvPexHalInit(MV_U32 pexIf, MV_PEX_TYPE pexType); -+ -+/* mvPexModeGet - Get Pex If mode */ -+MV_U32 mvPexModeGet(MV_U32 pexIf,MV_PEX_MODE *pexMode); -+ -+/* mvPexConfigRead - Read from configuration space */ -+MV_U32 mvPexConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func,MV_U32 regOff); -+ -+/* mvPexConfigWrite - Write to configuration space */ -+MV_STATUS mvPexConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data); -+ -+/* mvPexMasterEnable - Enable/disale PEX interface master transactions.*/ -+MV_STATUS mvPexMasterEnable(MV_U32 pexIf, MV_BOOL enable); -+ -+/* mvPexSlaveEnable - Enable/disale PEX interface slave transactions.*/ -+MV_STATUS mvPexSlaveEnable(MV_U32 pexIf, MV_U32 bus,MV_U32 dev, MV_BOOL enable); -+ -+/* mvPexLocalBusNumSet - Set PEX interface local bus number.*/ -+MV_STATUS mvPexLocalBusNumSet(MV_U32 pexIf, MV_U32 busNum); -+ -+/* mvPexLocalBusNumGet - Get PEX interface local bus number.*/ -+MV_U32 mvPexLocalBusNumGet(MV_U32 pexIf); -+ -+/* mvPexLocalDevNumSet - Set PEX interface local device number.*/ -+MV_STATUS mvPexLocalDevNumSet(MV_U32 pexIf, MV_U32 devNum); -+ -+/* mvPexLocalDevNumGet - Get PEX interface local device number.*/ -+MV_U32 mvPexLocalDevNumGet(MV_U32 pexIf); -+/* mvPexForceX1 - Force PEX interface to X1 mode. */ -+MV_U32 mvPexForceX1(MV_U32 pexIf); -+ -+/* mvPexIsPowerUp - Is PEX interface Power up? */ -+MV_BOOL mvPexIsPowerUp(MV_U32 pexIf); -+ -+/* mvPexPowerDown - Power Down */ -+MV_VOID mvPexPowerDown(MV_U32 pexIf); -+ -+/* mvPexPowerUp - Power Up */ -+MV_VOID mvPexPowerUp(MV_U32 pexIf); -+ -+/* mvPexPhyRegRead - Pex phy read */ -+MV_VOID mvPexPhyRegRead(MV_U32 pexIf, MV_U32 regOffset, MV_U16 *value); -+ -+/* mvPexPhyRegWrite - Pex phy write */ -+MV_VOID mvPexPhyRegWrite(MV_U32 pexIf, MV_U32 regOffset, MV_U16 value); -+ -+MV_STATUS mvPexActiveStateLinkPMEnable(MV_U32 pexIf, MV_BOOL enable); -+ -+#endif /* #ifndef __INCPEXH */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h 2010-11-09 20:28:11.782495900 +0100 -@@ -0,0 +1,751 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCPEXREGSH -+#define __INCPEXREGSH -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* defines */ -+#define MAX_PEX_DEVICES 32 -+#define MAX_PEX_FUNCS 8 -+#define MAX_PEX_BUSSES 256 -+ -+ -+ -+/*********************************************************/ -+/* PCI Express Configuration Cycles Generation Registers */ -+/*********************************************************/ -+ -+#define PEX_CFG_ADDR_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x18F8) -+#define PEX_CFG_DATA_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x18FC) -+#define PEX_PHY_ACCESS_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1B00) -+/* PCI Express Configuration Address Register */ -+/* PEX_CFG_ADDR_REG (PXCAR)*/ -+ -+#define PXCAR_REG_NUM_OFFS 2 -+#define PXCAR_REG_NUM_MAX 0x3F -+#define PXCAR_REG_NUM_MASK (PXCAR_REG_NUM_MAX << PXCAR_REG_NUM_OFFS) -+#define PXCAR_FUNC_NUM_OFFS 8 -+#define PXCAR_FUNC_NUM_MAX 0x7 -+#define PXCAR_FUNC_NUM_MASK (PXCAR_FUNC_NUM_MAX << PXCAR_FUNC_NUM_OFFS) -+#define PXCAR_DEVICE_NUM_OFFS 11 -+#define PXCAR_DEVICE_NUM_MAX 0x1F -+#define PXCAR_DEVICE_NUM_MASK (PXCAR_DEVICE_NUM_MAX << PXCAR_DEVICE_NUM_OFFS) -+#define PXCAR_BUS_NUM_OFFS 16 -+#define PXCAR_BUS_NUM_MAX 0xFF -+#define PXCAR_BUS_NUM_MASK (PXCAR_BUS_NUM_MAX << PXCAR_BUS_NUM_OFFS) -+#define PXCAR_EXT_REG_NUM_OFFS 24 -+#define PXCAR_EXT_REG_NUM_MAX 0xF -+ -+/* in pci express register address is now the legacy register address (8 bits) -+with the new extended register address (more 4 bits) , below is the mask of -+the upper 4 bits of the full register address */ -+ -+#define PXCAR_REAL_EXT_REG_NUM_OFFS 8 -+#define PXCAR_EXT_REG_NUM_MASK (PXCAR_EXT_REG_NUM_MAX << PXCAR_EXT_REG_NUM_OFFS) -+#define PXCAR_CONFIG_EN BIT31 -+ -+#define PXCAR_REAL_EXT_REG_NUM_OFFS 8 -+#define PXCAR_REAL_EXT_REG_NUM_MASK (0xF << PXCAR_REAL_EXT_REG_NUM_OFFS) -+ -+/* The traditional PCI spec defined 6-bit field to describe register offset.*/ -+/* The new PCI Express extend the register offset by an extra 4-bits. */ -+/* The below macro assign 10-bit register offset into the apprpreate */ -+/* fields in the CFG_ADDR_REG */ -+#define PXCAR_REG_OFFS_SET(regOffs) \ -+ ( (regOff & PXCAR_REG_NUM_MASK) | \ -+ ( ((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >> PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS) ) -+ -+/***********************************/ -+/* PCI Express Interrupt registers */ -+/***********************************/ -+#define PEX_CAUSE_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1900) -+#define PEX_MASK_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1910) -+ -+#define PXICR_TX_REQ_IN_DLDOWN_ERR BIT0 /* Transmit request while field */ -+ /* of the PCI Express */ -+/* PCI Express Interrupt Cause */ -+/* PEX_INT_CAUSE_REG (PXICR)*/ -+/* PEX_INT_MASK_REG*/ -+/* -+NOTE:All bits except bits[27:24] are Read/Write Clear only. A cause bit sets -+upon an error event occurrence. A write of 0 clears the bit. A write of 1 has -+no affect. Bits[24:27} are set and cleared upon reception of interrupt -+emulation messages. -+ -+Mask bit per cause bit. If a bit is set to 1, the corresponding event is -+enabled. Mask does not affect setting of the Interrupt Cause register bits; -+it only affects the assertion of the interrupt .*/ -+ -+ -+#define PXICR_MDIS_CAUSE BIT1 /* Attempt to generate PCI transaction -+ while master is disabled */ -+#define PXICR_ERR_WRTO_REG_CAUSE BIT3 /* Erroneous write attempt to -+ PCI Express internal register*/ -+#define PXICR_HIT_DFLT_WIN_ERR BIT4 /* Hit Default Window Error */ -+#define PXICR_RX_RAM_PAR_ERR BIT6 /* Rx RAM Parity Error */ -+#define PXICR_TX_RAM_PAR_ERR BIT7 /* Tx RAM Parity Error */ -+#define PXICR_COR_ERR_DET BIT8 /* Correctable Error Detected*/ -+#define PXICR_NF_ERR_DET BIT9 /* Non-Fatal Error Detected*/ -+#define PXICR_FERR_DET BIT10 /* Fatal Error Detected*/ -+#define PXICR_DSTATE_CHANGE BIT11 /* Dstate Change Indication*/ -+#define PXICR_BIST BIT12 /* PCI-Express BIST activated*/ -+#define PXICR_FLW_CTRL_PROT BIT14 /* Flow Control Protocol Error */ -+ -+#define PXICR_RCV_UR_CA_ERR BIT15 /* Received UR or CA status. */ -+#define PXICR_RCV_ERR_FATAL BIT16 /* Received ERR_FATAL message.*/ -+#define PXICR_RCV_ERR_NON_FATAL BIT17 /* Received ERR_NONFATAL message*/ -+#define PXICR_RCV_ERR_COR BIT18 /* Received ERR_COR message.*/ -+#define PXICR_RCV_CRS BIT19 /* Received CRS completion status*/ -+#define PXICR_SLV_HOT_RESET BIT20 /* Received Hot Reset Indication*/ -+#define PXICR_SLV_DIS_LINK BIT21 /* Slave Disable Link Indication*/ -+#define PXICR_SLV_LB BIT22 /* Slave Loopback Indication*/ -+#define PXICR_LINK_FAIL BIT23 /* Link Failure indication.*/ -+#define PXICR_RCV_INTA BIT24 /* IntA status.*/ -+#define PXICR_RCV_INTB BIT25 /* IntB status.*/ -+#define PXICR_RCV_INTC BIT26 /* IntC status.*/ -+#define PXICR_RCV_INTD BIT27 /* IntD status.*/ -+#define PXICR_RCV_PM_PME BIT28 /* Received PM_PME message. */ -+ -+ -+/********************************************/ -+/* PCI Express Control and Status Registers */ -+/********************************************/ -+#define PEX_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A00) -+#define PEX_STATUS_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A04) -+#define PEX_COMPLT_TMEOUT_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A10) -+#define PEX_PWR_MNG_EXT_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A18) -+#define PEX_FLOW_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A20) -+#define PEX_ACK_TMR_4X_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A30) -+#define PEX_ACK_TMR_1X_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A40) -+#define PEX_TL_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1AB0) -+ -+ -+#define PEX_RAM_PARITY_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A50) -+/* PCI Express Control Register */ -+/* PEX_CTRL_REG (PXCR) */ -+ -+#define PXCR_CONF_LINK_OFFS 0 -+#define PXCR_CONF_LINK_MASK (1 << PXCR_CONF_LINK_OFFS) -+#define PXCR_CONF_LINK_X4 (0 << PXCR_CONF_LINK_OFFS) -+#define PXCR_CONF_LINK_X1 (1 << PXCR_CONF_LINK_OFFS) -+#define PXCR_DEV_TYPE_CTRL_OFFS 1 /*PCI ExpressDevice Type Control*/ -+#define PXCR_DEV_TYPE_CTRL_MASK BIT1 -+#define PXCR_DEV_TYPE_CTRL_CMPLX (1 << PXCR_DEV_TYPE_CTRL_OFFS) -+#define PXCR_DEV_TYPE_CTRL_POINT (0 << PXCR_DEV_TYPE_CTRL_OFFS) -+#define PXCR_CFG_MAP_TO_MEM_EN BIT2 /* Configuration Header Mapping -+ to Memory Space Enable */ -+ -+#define PXCR_CFG_MAP_TO_MEM_EN BIT2 /* Configuration Header Mapping -+ to Memory Space Enable*/ -+ -+#define PXCR_RSRV1_OFFS 5 -+#define PXCR_RSRV1_MASK (0x7 << PXCR_RSRV1_OFFS) -+#define PXCR_RSRV1_VAL (0x0 << PXCR_RSRV1_OFFS) -+ -+#define PXCR_CONF_MAX_OUTSTND_OFFS 8 /*Maximum outstanding NP requests as a master*/ -+#define PXCR_CONF_MAX_OUTSTND_MASK (0x3 << PXCR_CONF_MAX_OUTSTND_OFFS) -+ -+ -+#define PXCR_CONF_NFTS_OFFS 16 /*number of FTS Ordered-Sets*/ -+#define PXCR_CONF_NFTS_MASK (0xff << PXCR_CONF_NFTS_OFFS) -+ -+#define PXCR_CONF_MSTR_HOT_RESET BIT24 /*Master Hot-Reset.*/ -+#define PXCR_CONF_MSTR_LB BIT26 /* Master Loopback */ -+#define PXCR_CONF_MSTR_DIS_SCRMB BIT27 /* Master Disable Scrambling*/ -+#define PXCR_CONF_DIRECT_DIS_SCRMB BIT28 /* Direct Disable Scrambling*/ -+ -+/* PCI Express Status Register */ -+/* PEX_STATUS_REG (PXSR) */ -+ -+#define PXSR_DL_DOWN BIT0 /* DL_Down indication.*/ -+ -+#define PXSR_PEX_BUS_NUM_OFFS 8 /* Bus Number Indication */ -+#define PXSR_PEX_BUS_NUM_MASK (0xff << PXSR_PEX_BUS_NUM_OFFS) -+ -+#define PXSR_PEX_DEV_NUM_OFFS 16 /* Device Number Indication */ -+#define PXSR_PEX_DEV_NUM_MASK (0x1f << PXSR_PEX_DEV_NUM_OFFS) -+ -+#define PXSR_PEX_SLV_HOT_RESET BIT24 /* Slave Hot Reset Indication*/ -+#define PXSR_PEX_SLV_DIS_LINK BIT25 /* Slave Disable Link Indication*/ -+#define PXSR_PEX_SLV_LB BIT26 /* Slave Loopback Indication*/ -+#define PXSR_PEX_SLV_DIS_SCRMB BIT27 /* Slave Disable Scrambling Indication*/ -+ -+ -+/* PCI Express Completion Timeout Register */ -+/* PEX_COMPLT_TMEOUT_REG (PXCTR)*/ -+ -+#define PXCTR_CMP_TO_THRSHLD_OFFS 0 /* Completion Timeout Threshold */ -+#define PXCTR_CMP_TO_THRSHLD_MASK (0xffff << PXCTR_CMP_TO_THRSHLD_OFFS) -+ -+/* PCI Express Power Management Extended Register */ -+/* PEX_PWR_MNG_EXT_REG (PXPMER) */ -+ -+#define PXPMER_L1_ASPM_EN_OFFS 1 -+#define PXPMER_L1_ASPM_EN_MASK (0x1 << PXPMER_L1_ASPM_EN_OFFS) -+ -+/* PCI Express Flow Control Register */ -+/* PEX_FLOW_CTRL_REG (PXFCR)*/ -+ -+#define PXFCR_PH_INIT_FC_OFFS 0 /*Posted Headers Flow Control Credit -+ Initial Value.*/ -+#define PXFCR_PH_INIT_FC_MASK (0xff << PXFCR_PH_INIT_FC_OFFS) -+ -+ -+#define PXFCR_NPH_INIT_FC_OFFS 8 /* Classified Non-Posted Headers -+ Flow Control Credit Initial Value*/ -+#define PXFCR_NPH_INIT_FC_MASK (0xff << PXFCR_NPH_INIT_FC_OFFS) -+ -+#define PXFCR_CH_INIT_FC_OFFS 16 /* Completion Headers Flow Control -+ Credit Initial Value Infinite*/ -+ -+#define PXFCR_CH_INIT_FC_MASK (0xff << PXFCR_CH_INIT_FC_OFFS) -+ -+#define PXFCR_FC_UPDATE_TO_OFFS 24 /* Flow Control Update Timeout */ -+#define PXFCR_FC_UPDATE_TO_MASK (0xff << PXFCR_FC_UPDATE_TO_OFFS) -+ -+/* PCI Express Acknowledge Timers (4X) Register */ -+/* PEX_ACK_TMR_4X_REG (PXAT4R) */ -+#define PXAT1R_ACK_LAT_TOX4_OFFS 0 /* Ack Latency Timer Timeout Value */ -+#define PXAT1R_ACK_LAT_TOX4_MASK (0xffff << PXAT4R_ACK_LAT_TOX1_OFFS) -+#define PXAT1R_ACK_RPLY_TOX4_OFFS 16 /* Ack Replay Timer Timeout Value */ -+#define PXAT1R_ACK_RPLY_TOX4_MASK (0xffff << PXAT1R_ACK_RPLY_TOX1_OFFS) -+ -+/* PCI Express Acknowledge Timers (1X) Register */ -+/* PEX_ACK_TMR_1X_REG (PXAT1R) */ -+ -+#define PXAT1R_ACK_LAT_TOX1_OFFS 0 /* Acknowledge Latency Timer Timeout -+ Value for 1X Link*/ -+#define PXAT1R_ACK_LAT_TOX1_MASK (0xffff << PXAT1R_ACK_LAT_TOX1_OFFS) -+ -+#define PXAT1R_ACK_RPLY_TOX1_OFFS 16 /* Acknowledge Replay Timer Timeout -+ Value for 1X*/ -+#define PXAT1R_ACK_RPLY_TOX1_MASK (0xffff << PXAT1R_ACK_RPLY_TOX1_OFFS) -+ -+ -+/* PCI Express TL Control Register */ -+/* PEX_TL_CTRL_REG (PXTCR) */ -+ -+#define PXTCR_TX_CMP_BUFF_NO_OFFS 8 /*Number of completion buffers in Tx*/ -+#define PXTCR_TX_CMP_BUFF_NO_MASK (0xf << PXTCR_TX_CMP_BUFF_NO_OFFS) -+ -+/* PCI Express Debug MAC Control Register */ -+/* PEX_DEBUG_MAC_CTRL_REG (PXDMCR) */ -+ -+#define PXDMCR_LINKUP BIT4 -+ -+ -+ -+/**********************************************/ -+/* PCI Express Configuration Header Registers */ -+/**********************************************/ -+#define PEX_CFG_DIRECT_ACCESS(pexIf,cfgReg) ((PEX_IF_BASE(pexIf)) + (cfgReg)) -+ -+#define PEX_DEVICE_AND_VENDOR_ID 0x000 -+#define PEX_STATUS_AND_COMMAND 0x004 -+#define PEX_CLASS_CODE_AND_REVISION_ID 0x008 -+#define PEX_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE 0x00C -+#define PEX_MEMORY_BAR_BASE_ADDR(barNum) (0x010 + ((barNum) << 2)) -+#define PEX_MV_BAR_BASE(barNum) (0x010 + (barNum) * 8) -+#define PEX_MV_BAR_BASE_HIGH(barNum) (0x014 + (barNum) * 8) -+#define PEX_BAR0_INTER_REG 0x010 -+#define PEX_BAR0_INTER_REG_HIGH 0x014 -+#define PEX_BAR1_REG 0x018 -+#define PEX_BAR1_REG_HIGH 0x01C -+#define PEX_BAR2_REG 0x020 -+#define PEX_BAR2_REG_HIGH 0x024 -+ -+#define PEX_SUBSYS_ID_AND_SUBSYS_VENDOR_ID 0x02C -+#define PEX_EXPANSION_ROM_BASE_ADDR_REG 0x030 -+#define PEX_CAPABILTY_LIST_POINTER 0x034 -+#define PEX_INTERRUPT_PIN_AND_LINE 0x03C -+ -+/* capability list */ -+#define PEX_POWER_MNG_CAPABILITY 0x040 -+#define PEX_POWER_MNG_STATUS_CONTROL 0x044 -+ -+#define PEX_MSI_MESSAGE_CONTROL 0x050 -+#define PEX_MSI_MESSAGE_ADDR 0x054 -+#define PEX_MSI_MESSAGE_HIGH_ADDR 0x058 -+#define PEX_MSI_MESSAGE_DATA 0x05C -+ -+#define PEX_CAPABILITY_REG 0x60 -+#define PEX_DEV_CAPABILITY_REG 0x64 -+#define PEX_DEV_CTRL_STAT_REG 0x68 -+#define PEX_LINK_CAPABILITY_REG 0x6C -+#define PEX_LINK_CTRL_STAT_REG 0x70 -+ -+#define PEX_ADV_ERR_RPRT_HDR_TRGT_REG 0x100 -+#define PEX_UNCORRECT_ERR_STAT_REG 0x104 -+#define PEX_UNCORRECT_ERR_MASK_REG 0x108 -+#define PEX_UNCORRECT_ERR_SERVITY_REG 0x10C -+#define PEX_CORRECT_ERR_STAT_REG 0x110 -+#define PEX_CORRECT_ERR_MASK_REG 0x114 -+#define PEX_ADV_ERR_CAPABILITY_CTRL_REG 0x118 -+#define PEX_HDR_LOG_FIRST_DWORD_REG 0x11C -+#define PEX_HDR_LOG_SECOND_DWORD_REG 0x120 -+#define PEX_HDR_LOG_THIRD_DWORD_REG 0x124 -+#define PEX_HDR_LOG_FOURTH_DWORD_REG 0x128 -+ -+ -+ -+/* PCI Express Device and Vendor ID Register*/ -+/*PEX_DEVICE_AND_VENDOR_ID (PXDAVI)*/ -+ -+#define PXDAVI_VEN_ID_OFFS 0 /* Vendor ID */ -+#define PXDAVI_VEN_ID_MASK (0xffff << PXDAVI_VEN_ID_OFFS) -+ -+#define PXDAVI_DEV_ID_OFFS 16 /* Device ID */ -+#define PXDAVI_DEV_ID_MASK (0xffff << PXDAVI_DEV_ID_OFFS) -+ -+ -+/* PCI Express Command and Status Register*/ -+/*PEX_STATUS_AND_COMMAND (PXSAC)*/ -+ -+#define PXSAC_IO_EN BIT0 /* IO Enable */ -+#define PXSAC_MEM_EN BIT1 /* Memory Enable */ -+#define PXSAC_MASTER_EN BIT2 /* Master Enable */ -+#define PXSAC_PERR_EN BIT6 /* Parity Errors Respond Enable */ -+#define PXSAC_SERR_EN BIT8 /* Ability to assert SERR# line */ -+#define PXSAC_INT_DIS BIT10 /* Interrupt Disable */ -+#define PXSAC_INT_STAT BIT19 /* Interrupt Status */ -+#define PXSAC_CAP_LIST BIT20 /* Capability List Support */ -+#define PXSAC_MAS_DATA_PERR BIT24 /* Master Data Parity Error */ -+#define PXSAC_SLAVE_TABORT BIT27 /* Signalled Target Abort */ -+#define PXSAC_RT_ABORT BIT28 /* Recieved Target Abort */ -+#define PXSAC_MABORT BIT29 /* Recieved Master Abort */ -+#define PXSAC_SYSERR BIT30 /* Signalled system error */ -+#define PXSAC_DET_PARERR BIT31 /* Detect Parity Error */ -+ -+ -+/* PCI Express Class Code and Revision ID Register*/ -+/*PEX_CLASS_CODE_AND_REVISION_ID (PXCCARI)*/ -+ -+#define PXCCARI_REVID_OFFS 0 /* Revision ID */ -+#define PXCCARI_REVID_MASK (0xff << PXCCARI_REVID_OFFS) -+ -+#define PXCCARI_FULL_CLASS_OFFS 8 /* Full Class Code */ -+#define PXCCARI_FULL_CLASS_MASK (0xffffff << PXCCARI_FULL_CLASS_OFFS) -+ -+#define PXCCARI_PROGIF_OFFS 8 /* Prog .I/F*/ -+#define PXCCARI_PROGIF_MASK (0xff << PXCCARI_PROGIF_OFFS) -+ -+#define PXCCARI_SUB_CLASS_OFFS 16 /* Sub Class*/ -+#define PXCCARI_SUB_CLASS_MASK (0xff << PXCCARI_SUB_CLASS_OFFS) -+ -+#define PXCCARI_BASE_CLASS_OFFS 24 /* Base Class*/ -+#define PXCCARI_BASE_CLASS_MASK (0xff << PXCCARI_BASE_CLASS_OFFS) -+ -+ -+/* PCI Express BIST, Header Type and Cache Line Size Register*/ -+/*PEX_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE (PXBHTLTCL)*/ -+ -+#define PXBHTLTCL_CACHELINE_OFFS 0 /* Specifies the cache line size */ -+#define PXBHTLTCL_CACHELINE_MASK (0xff << PXBHTLTCL_CACHELINE_OFFS) -+ -+#define PXBHTLTCL_HEADTYPE_FULL_OFFS 16 /* Full Header Type */ -+#define PXBHTLTCL_HEADTYPE_FULL_MASK (0xff << PXBHTLTCL_HEADTYPE_FULL_OFFS) -+ -+#define PXBHTLTCL_MULTI_FUNC BIT23 /* Multi/Single function */ -+ -+#define PXBHTLTCL_HEADER_OFFS 16 /* Header type */ -+#define PXBHTLTCL_HEADER_MASK (0x7f << PXBHTLTCL_HEADER_OFFS) -+#define PXBHTLTCL_HEADER_STANDARD (0x0 << PXBHTLTCL_HEADER_OFFS) -+#define PXBHTLTCL_HEADER_PCI2PCI_BRIDGE (0x1 << PXBHTLTCL_HEADER_OFFS) -+ -+ -+#define PXBHTLTCL_BISTCOMP_OFFS 24 /* BIST Completion Code */ -+#define PXBHTLTCL_BISTCOMP_MASK (0xf << PXBHTLTCL_BISTCOMP_OFFS) -+ -+#define PXBHTLTCL_BISTACT BIT30 /* BIST Activate bit */ -+#define PXBHTLTCL_BISTCAP BIT31 /* BIST Capable Bit */ -+#define PXBHTLTCL_BISTCAP_OFFS 31 -+#define PXBHTLTCL_BISTCAP_MASK BIT31 -+#define PXBHTLTCL_BISTCAP_VAL 0 -+ -+ -+/* PCI Express Subsystem Device and Vendor ID */ -+/*PEX_SUBSYS_ID_AND_SUBSYS_VENDOR_ID (PXSIASVI)*/ -+ -+#define PXSIASVI_VENID_OFFS 0 /* Subsystem Manufacturer Vendor ID Number */ -+#define PXSIASVI_VENID_MASK (0xffff << PXSIASVI_VENID_OFFS) -+ -+#define PXSIASVI_DEVID_OFFS 16 /* Subsystem Device ID Number */ -+#define PXSIASVI_DEVID_MASK (0xffff << PXSIASVI_DEVID_OFFS) -+ -+ -+/* PCI Express Capability List Pointer Register*/ -+/*PEX_CAPABILTY_LIST_POINTER (PXCLP)*/ -+ -+#define PXCLP_CAPPTR_OFFS 0 /* Capability List Pointer */ -+#define PXCLP_CAPPTR_MASK (0xff << PXCLP_CAPPTR_OFFS) -+ -+/* PCI Express Interrupt Pin and Line Register */ -+/*PEX_INTERRUPT_PIN_AND_LINE (PXIPAL)*/ -+ -+#define PXIPAL_INTLINE_OFFS 0 /* Interrupt line (IRQ) */ -+#define PXIPAL_INTLINE_MASK (0xff << PXIPAL_INTLINE_OFFS) -+ -+#define PXIPAL_INTPIN_OFFS 8 /* interrupt pin (A,B,C,D) */ -+#define PXIPAL_INTPIN_MASK (0xff << PXIPAL_INTPIN_OFFS) -+ -+ -+/* PCI Express Power Management Capability Header Register*/ -+/*PEX_POWER_MNG_CAPABILITY (PXPMC)*/ -+ -+#define PXPMC_CAP_ID_OFFS 0 /* Capability ID */ -+#define PXPMC_CAP_ID_MASK (0xff << PXPMC_CAP_ID_OFFS) -+ -+#define PXPMC_NEXT_PTR_OFFS 8 /* Next Item Pointer */ -+#define PXPMC_NEXT_PTR_MASK (0xff << PXPMC_NEXT_PTR_OFFS) -+ -+#define PXPMC_PMC_VER_OFFS 16 /* PCI Power Management Capability Version*/ -+#define PXPMC_PMC_VER_MASK (0x7 << PXPMC_PMC_VER_OFFS) -+ -+#define PXPMC_DSI BIT21/* Device Specific Initialization */ -+ -+#define PXPMC_AUX_CUR_OFFS 22 /* Auxiliary Current Requirements */ -+#define PXPMC_AUX_CUR_MASK (0x7 << PXPMC_AUX_CUR_OFFS) -+ -+#define PXPMC_D1_SUP BIT25 /* D1 Power Management support*/ -+ -+#define PXPMC_D2_SUP BIT26 /* D2 Power Management support*/ -+ -+#define PXPMC_PME_SUP_OFFS 27 /* PM Event generation support*/ -+#define PXPMC_PME_SUP_MASK (0x1f << PXPMC_PME_SUP_OFFS) -+ -+/* PCI Express Power Management Control and Status Register*/ -+/*PEX_POWER_MNG_STATUS_CONTROL (PXPMSC)*/ -+ -+#define PXPMSC_PM_STATE_OFFS 0 /* Power State */ -+#define PXPMSC_PM_STATE_MASK (0x3 << PXPMSC_PM_STATE_OFFS) -+#define PXPMSC_PM_STATE_D0 (0x0 << PXPMSC_PM_STATE_OFFS) -+#define PXPMSC_PM_STATE_D1 (0x1 << PXPMSC_PM_STATE_OFFS) -+#define PXPMSC_PM_STATE_D2 (0x2 << PXPMSC_PM_STATE_OFFS) -+#define PXPMSC_PM_STATE_D3 (0x3 << PXPMSC_PM_STATE_OFFS) -+ -+#define PXPMSC_PME_EN BIT8/* PM_PME Message Generation Enable */ -+ -+#define PXPMSC_PM_DATA_SEL_OFFS 9 /* Data Select*/ -+#define PXPMSC_PM_DATA_SEL_MASK (0xf << PXPMSC_PM_DATA_SEL_OFFS) -+ -+#define PXPMSC_PM_DATA_SCALE_OFFS 13 /* Data Scale */ -+#define PXPMSC_PM_DATA_SCALE_MASK (0x3 << PXPMSC_PM_DATA_SCALE_OFFS) -+ -+#define PXPMSC_PME_STAT BIT15/* PME Status */ -+ -+#define PXPMSC_PM_DATA_OFFS 24 /* State Data */ -+#define PXPMSC_PM_DATA_MASK (0xff << PXPMSC_PM_DATA_OFFS) -+ -+ -+/* PCI Express MSI Message Control Register*/ -+/*PEX_MSI_MESSAGE_CONTROL (PXMMC)*/ -+ -+#define PXMMC_CAP_ID_OFFS 0 /* Capability ID */ -+#define PXMMC_CAP_ID_MASK (0xff << PXMMC_CAP_ID_OFFS) -+ -+#define PXMMC_NEXT_PTR_OFFS 8 /* Next Item Pointer */ -+#define PXMMC_NEXT_PTR_MASK (0xff << PXMMC_NEXT_PTR_OFFS) -+ -+#define PXMMC_MSI_EN BIT18 /* MSI Enable */ -+ -+#define PXMMC_MULTI_CAP_OFFS 17 /* Multiple Message Capable */ -+#define PXMMC_MULTI_CAP_MASK (0x7 << PXMMC_MULTI_CAP_OFFS) -+ -+#define PXMMC_MULTI_EN_OFFS 20 /* Multiple Messages Enable */ -+#define PXMMC_MULTI_EN_MASK (0x7 << PXMMC_MULTI_EN_OFFS) -+ -+#define PXMMC_ADDR64 BIT23 /* 64-bit Addressing Capable */ -+ -+ -+/* PCI Express MSI Message Address Register*/ -+/*PEX_MSI_MESSAGE_ADDR (PXMMA)*/ -+ -+#define PXMMA_MSI_ADDR_OFFS 2 /* Message Address corresponds to -+ Address[31:2] of the MSI MWr TLP*/ -+#define PXMMA_MSI_ADDR_MASK (0x3fffffff << PXMMA_MSI_ADDR_OFFS) -+ -+ -+/* PCI Express MSI Message Address (High) Register */ -+/*PEX_MSI_MESSAGE_HIGH_ADDR (PXMMHA)*/ -+ -+#define PXMMA_MSI_ADDR_H_OFFS 0 /* Message Upper Address corresponds to -+ Address[63:32] of the MSI MWr TLP*/ -+#define PXMMA_MSI_ADDR_H_MASK (0xffffffff << PXMMA_MSI_ADDR_H_OFFS ) -+ -+ -+/* PCI Express MSI Message Data Register*/ -+/*PEX_MSI_MESSAGE_DATA (PXMMD)*/ -+ -+#define PXMMD_MSI_DATA_OFFS 0 /* Message Data */ -+#define PXMMD_MSI_DATA_MASK (0xffff << PXMMD_MSI_DATA_OFFS ) -+ -+ -+/* PCI Express Capability Register*/ -+/*PEX_CAPABILITY_REG (PXCR)*/ -+ -+#define PXCR_CAP_ID_OFFS 0 /* Capability ID*/ -+#define PXCR_CAP_ID_MASK (0xff << PXCR_CAP_ID_OFFS) -+ -+#define PXCR_NEXT_PTR_OFFS 8 /* Next Item Pointer*/ -+#define PXCR_NEXT_PTR_MASK (0xff << PXCR_NEXT_PTR_OFFS) -+ -+#define PXCR_CAP_VER_OFFS 16 /* Capability Version*/ -+#define PXCR_CAP_VER_MASK (0xf << PXCR_CAP_VER_OFFS) -+ -+#define PXCR_DEV_TYPE_OFFS 20 /* Device/Port Type*/ -+#define PXCR_DEV_TYPE_MASK (0xf << PXCR_DEV_TYPE_OFFS) -+ -+#define PXCR_SLOT_IMP BIT24 /* Slot Implemented*/ -+ -+#define PXCR_INT_MSG_NUM_OFFS 25 /* Interrupt Message Number*/ -+#define PXCR_INT_MSG_NUM_MASK (0x1f << PXCR_INT_MSG_NUM_OFFS) -+ -+ -+/* PCI Express Device Capabilities Register */ -+/*PEX_DEV_CAPABILITY_REG (PXDCR)*/ -+ -+#define PXDCR_MAX_PLD_SIZE_SUP_OFFS 0 /* Maximum Payload Size Supported*/ -+#define PXDCR_MAX_PLD_SIZE_SUP_MASK (0x7 << PXDCR_MAX_PLD_SIZE_SUP_OFFS) -+ -+#define PXDCR_EP_L0S_ACC_LAT_OFFS 6/* Endpoint L0s Acceptable Latency*/ -+#define PXDCR_EP_L0S_ACC_LAT_MASK (0x7 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+#define PXDCR_EP_L0S_ACC_LAT_64NS_LESS (0x0 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+#define PXDCR_EP_L0S_ACC_LAT_64NS_128NS (0x1 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+#define PXDCR_EP_L0S_ACC_LAT_128NS_256NS (0x2 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+#define PXDCR_EP_L0S_ACC_LAT_256NS_512NS (0x3 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+#define PXDCR_EP_L0S_ACC_LAT_512NS_1US (0x4 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+#define PXDCR_EP_L0S_ACC_LAT_1US_2US (0x5 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+#define PXDCR_EP_L0S_ACC_LAT_2US_4US (0x6 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+#define PXDCR_EP_L0S_ACC_LAT_4US_MORE (0x7 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+ -+#define PXDCR_EP_L1_ACC_LAT_OFFS 9 /* Endpoint L1 Acceptable Latency*/ -+#define PXDCR_EP_L1_ACC_LAT_MASK (0x7 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXDCR_EP_L1_ACC_LAT_64NS_LESS (0x0 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXDCR_EP_L1_ACC_LAT_64NS_128NS (0x1 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXDCR_EP_L1_ACC_LAT_128NS_256NS (0x2 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXDCR_EP_L1_ACC_LAT_256NS_512NS (0x3 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXDCR_EP_L1_ACC_LAT_512NS_1US (0x4 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXDCR_EP_L1_ACC_LAT_1US_2US (0x5 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXDCR_EP_L1_ACC_LAT_2US_4US (0x6 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXDCR_EP_L1_ACC_LAT_4US_MORE (0x7 << PXDCR_EP_L1_ACC_LAT_OFFS) -+ -+ -+#define PXDCR_ATT_BUT_PRS_OFFS 12 /* Attention Button Present*/ -+#define PXDCR_ATT_BUT_PRS_MASK BIT12 -+#define PXDCR_ATT_BUT_PRS_IMPLEMENTED BIT12 -+ -+#define PXDCR_ATT_IND_PRS_OFFS 13 /* Attention Indicator Present*/ -+#define PXDCR_ATT_IND_PRS_MASK BIT13 -+#define PXDCR_ATT_IND_PRS_IMPLEMENTED BIT13 -+ -+#define PXDCR_PWR_IND_PRS_OFFS 14/* Power Indicator Present*/ -+#define PXDCR_PWR_IND_PRS_MASK BIT14 -+#define PXDCR_PWR_IND_PRS_IMPLEMENTED BIT14 -+ -+#define PXDCR_CAP_SPL_VAL_OFFS 18 /*Captured Slot Power Limit -+ Value*/ -+#define PXDCR_CAP_SPL_VAL_MASK (0xff << PXDCR_CAP_SPL_VAL_OFFS) -+ -+#define PXDCR_CAP_SP_LSCL_OFFS 26 /* Captured Slot Power Limit -+ Scale */ -+#define PXDCR_CAP_SP_LSCL_MASK (0x3 << PXDCR_CAP_SP_LSCL_OFFS) -+ -+/* PCI Express Device Control Status Register */ -+/*PEX_DEV_CTRL_STAT_REG (PXDCSR)*/ -+ -+#define PXDCSR_COR_ERR_REP_EN BIT0 /* Correctable Error Reporting Enable*/ -+#define PXDCSR_NF_ERR_REP_EN BIT1 /* Non-Fatal Error Reporting Enable*/ -+#define PXDCSR_F_ERR_REP_EN BIT2 /* Fatal Error Reporting Enable*/ -+#define PXDCSR_UR_REP_EN BIT3 /* Unsupported Request (UR) -+ Reporting Enable*/ -+#define PXDCSR_EN_RO BIT4 /* Enable Relaxed Ordering*/ -+ -+#define PXDCSR_MAX_PLD_SZ_OFFS 5 /* Maximum Payload Size*/ -+#define PXDCSR_MAX_PLD_SZ_MASK (0x7 << PXDCSR_MAX_PLD_SZ_OFFS) -+#define PXDCSR_MAX_PLD_SZ_128B (0x0 << PXDCSR_MAX_PLD_SZ_OFFS) -+#define PXDCSR_EN_NS BIT11 /* Enable No Snoop*/ -+ -+#define PXDCSR_MAX_RD_RQ_SZ_OFFS 12 /* Maximum Read Request Size*/ -+#define PXDCSR_MAX_RD_RQ_SZ_MASK (0x7 << PXDCSR_MAX_RD_RQ_SZ_OFFS) -+#define PXDCSR_MAX_RD_RQ_SZ_128B (0x0 << PXDCSR_MAX_RD_RQ_SZ_OFFS) -+#define PXDCSR_MAX_RD_RQ_SZ_256B (0x1 << PXDCSR_MAX_RD_RQ_SZ_OFFS) -+#define PXDCSR_MAX_RD_RQ_SZ_512B (0x2 << PXDCSR_MAX_RD_RQ_SZ_OFFS) -+#define PXDCSR_MAX_RD_RQ_SZ_1KB (0x3 << PXDCSR_MAX_RD_RQ_SZ_OFFS) -+#define PXDCSR_MAX_RD_RQ_SZ_2KB (0x4 << PXDCSR_MAX_RD_RQ_SZ_OFFS) -+#define PXDCSR_MAX_RD_RQ_SZ_4KB (0x5 << PXDCSR_MAX_RD_RQ_SZ_OFFS) -+ -+#define PXDCSR_COR_ERR_DET BIT16 /* Correctable Error Detected*/ -+#define PXDCSR_NF_ERR_DET BIT17 /* Non-Fatal Error Detected.*/ -+#define PXDCSR_F_ERR_DET BIT18 /* Fatal Error Detected.*/ -+#define PXDCSR_UR_DET BIT19 /* Unsupported Request Detected */ -+#define PXDCSR_AUX_PWR_DET BIT20 /* Reserved*/ -+ -+#define PXDCSR_TRANS_PEND_OFFS 21 /* Transactions Pending*/ -+#define PXDCSR_TRANS_PEND_MASK BIT21 -+#define PXDCSR_TRANS_PEND_NOT_COMPLETED (0x1 << PXDCSR_TRANS_PEND_OFFS) -+ -+ -+/* PCI Express Link Capabilities Register*/ -+/*PEX_LINK_CAPABILITY_REG (PXLCR)*/ -+ -+#define PXLCR_MAX_LINK_SPD_OFFS 0 /* Maximum Link Speed*/ -+#define PXLCR_MAX_LINK_SPD_MASK (0xf << PXLCR_MAX_LINK_SPD_OFFS) -+ -+#define PXLCR_MAX_LNK_WDTH_OFFS 3 /* Maximum Link Width*/ -+#define PXLCR_MAX_LNK_WDTH_MASK (0x3f << PXLCR_MAX_LNK_WDTH_OFFS) -+ -+#define PXLCR_ASPM_SUP_OFFS 10 /* Active State Link PM Support*/ -+#define PXLCR_ASPM_SUP_MASK (0x3 << PXLCR_ASPM_SUP_OFFS) -+ -+#define PXLCR_L0S_EXT_LAT_OFFS 12 /* L0s Exit Latency*/ -+#define PXLCR_L0S_EXT_LAT_MASK (0x7 << PXLCR_L0S_EXT_LAT_OFFS) -+#define PXLCR_L0S_EXT_LAT_64NS_LESS (0x0 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXLCR_L0S_EXT_LAT_64NS_128NS (0x1 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXLCR_L0S_EXT_LAT_128NS_256NS (0x2 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXLCR_L0S_EXT_LAT_256NS_512NS (0x3 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXLCR_L0S_EXT_LAT_512NS_1US (0x4 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXLCR_L0S_EXT_LAT_1US_2US (0x5 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXLCR_L0S_EXT_LAT_2US_4US (0x6 << PXDCR_EP_L1_ACC_LAT_OFFS) -+ -+#define PXLCR_POR_TNUM_OFFS 24 /* Port Number */ -+#define PXLCR_POR_TNUM_MASK (0xff << PXLCR_POR_TNUM_OFFS) -+ -+/* PCI Express Link Control Status Register */ -+/*PEX_LINK_CTRL_STAT_REG (PXLCSR)*/ -+ -+#define PXLCSR_ASPM_CNT_OFFS 0 /* Active State Link PM Control */ -+#define PXLCSR_ASPM_CNT_MASK (0x3 << PXLCSR_ASPM_CNT_OFFS) -+#define PXLCSR_ASPM_CNT_DISABLED (0x0 << PXLCSR_ASPM_CNT_OFFS) -+#define PXLCSR_ASPM_CNT_L0S_ENT_SUPP (0x1 << PXLCSR_ASPM_CNT_OFFS) -+#define PXLCSR_ASPM_CNT_L1S_ENT_SUPP (0x2 << PXLCSR_ASPM_CNT_OFFS) -+#define PXLCSR_ASPM_CNT_L0S_L1S_ENT_SUPP (0x3 << PXLCSR_ASPM_CNT_OFFS) -+ -+#define PXLCSR_RCB_OFFS 3 /* Read Completion Boundary */ -+#define PXLCSR_RCB_MASK BIT3 -+#define PXLCSR_RCB_64B (0 << PXLCSR_RCB_OFFS) -+#define PXLCSR_RCB_128B (1 << PXLCSR_RCB_OFFS) -+ -+#define PXLCSR_LNK_DIS BIT4 /* Link Disable */ -+#define PXLCSR_RETRN_LNK BIT5 /* Retrain Link */ -+#define PXLCSR_CMN_CLK_CFG BIT6 /* Common Clock Configuration */ -+#define PXLCSR_EXTD_SNC BIT7 /* Extended Sync */ -+ -+#define PXLCSR_LNK_SPD_OFFS 16 /* Link Speed */ -+#define PXLCSR_LNK_SPD_MASK (0xf << PXLCSR_LNK_SPD_OFFS) -+ -+#define PXLCSR_NEG_LNK_WDTH_OFFS 20 /* Negotiated Link Width */ -+#define PXLCSR_NEG_LNK_WDTH_MASK (0x3f << PXLCSR_NEG_LNK_WDTH_OFFS) -+#define PXLCSR_NEG_LNK_WDTH_X1 (0x1 << PXLCSR_NEG_LNK_WDTH_OFFS) -+ -+#define PXLCSR_LNK_TRN BIT27 /* Link Training */ -+ -+#define PXLCSR_SLT_CLK_CFG_OFFS 28 /* Slot Clock Configuration */ -+#define PXLCSR_SLT_CLK_CFG_MASK BIT28 -+#define PXLCSR_SLT_CLK_CFG_INDPNT (0x0 << PXLCSR_SLT_CLK_CFG_OFFS) -+#define PXLCSR_SLT_CLK_CFG_REF (0x1 << PXLCSR_SLT_CLK_CFG_OFFS) -+ -+/* PCI Express Advanced Error Report Header Register */ -+/*PEX_ADV_ERR_RPRT_HDR_TRGT_REG (PXAERHTR)*/ -+ -+/* PCI Express Uncorrectable Error Status Register*/ -+/*PEX_UNCORRECT_ERR_STAT_REG (PXUESR)*/ -+ -+/* PCI Express Uncorrectable Error Mask Register */ -+/*PEX_UNCORRECT_ERR_MASK_REG (PXUEMR)*/ -+ -+/* PCI Express Uncorrectable Error Severity Register */ -+/*PEX_UNCORRECT_ERR_SERVITY_REG (PXUESR)*/ -+ -+/* PCI Express Correctable Error Status Register */ -+/*PEX_CORRECT_ERR_STAT_REG (PXCESR)*/ -+ -+/* PCI Express Correctable Error Mask Register */ -+/*PEX_CORRECT_ERR_MASK_REG (PXCEMR)*/ -+ -+/* PCI Express Advanced Error Capability and Control Register*/ -+/*PEX_ADV_ERR_CAPABILITY_CTRL_REG (PXAECCR)*/ -+ -+/* PCI Express Header Log First DWORD Register*/ -+/*PEX_HDR_LOG_FIRST_DWORD_REG (PXHLFDR)*/ -+ -+/* PCI Express Header Log Second DWORD Register*/ -+/*PEX_HDR_LOG_SECOND_DWORD_REG (PXHLSDR)*/ -+ -+/* PCI Express Header Log Third DWORD Register*/ -+/*PEX_HDR_LOG_THIRD_DWORD_REG (PXHLTDR)*/ -+ -+/* PCI Express Header Log Fourth DWORD Register*/ -+/*PEX_HDR_LOG_FOURTH_DWORD_REG (PXHLFDR)*/ -+ -+#ifdef __cplusplus -+} -+#endif /* __cplusplus */ -+ -+#endif /* #ifndef __INCPEXREGSH */ -+ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c 2010-11-09 20:28:11.822495468 +0100 -@@ -0,0 +1,313 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "mvPex.h" -+ -+//#define MV_DEBUG -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+/* locals */ -+typedef struct -+{ -+ MV_U32 data; -+ MV_U32 mask; -+}PEX_HEADER_DATA; -+ -+/* local function forwad decleration */ -+MV_U32 mvPexHwConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, -+ MV_U32 regOff); -+MV_STATUS mvPexHwConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data); -+void resetPexConfig(MV_U32 pexIf, MV_U32 bus, MV_U32 dev); -+ -+ -+PEX_HEADER_DATA configHdr[16] = -+{ -+{0x888811ab, 0x00000000}, /*[device ID, vendor ID] */ -+{0x00100007, 0x0000ffff}, /*[status register, command register] */ -+{0x0604000e, 0x00000000}, /*[programming interface, sub class code, class code, revision ID] */ -+{0x00010008, 0x00000000}, /*[BIST, header type, latency time, cache line] */ -+{0x00000000, 0x00000000}, /*[base address 0] */ -+{0x00000000, 0x00000000}, /*[base address 1] */ -+{0x00000000, 0x00ffffff}, /*[secondary latency timersubordinate bus number, secondary bus number, primary bus number] */ -+{0x0000f101, 0x00000000}, /*[secondary status ,IO limit, IO base] */ -+{0x9ff0a000, 0x00000000}, /*[memory limit, memory base] */ -+{0x0001fff1, 0x00000000}, /*[prefetch memory limit, prefetch memory base] */ -+{0xffffffff, 0x00000000}, /*[prefetch memory base upper] */ -+{0x00000000, 0x00000000}, /*[prefetch memory limit upper] */ -+{0xeffff000, 0x00000000}, /*[IO limit upper 16 bits, IO base upper 16 bits] */ -+{0x00000000, 0x00000000}, /*[reserved, capability pointer] */ -+{0x00000000, 0x00000000}, /*[expansion ROM base address] */ -+{0x00000000, 0x000000FF}, /*[bridge control, interrupt pin, interrupt line] */ -+}; -+ -+ -+#define HEADER_WRITE(data, offset) configHdr[offset/4].data = ((configHdr[offset/4].data & ~configHdr[offset/4].mask) | \ -+ (data & configHdr[offset/4].mask)) -+#define HEADER_READ(offset) configHdr[offset/4].data -+ -+/******************************************************************************* -+* mvVrtBrgPexInit - Initialize PEX interfaces -+* -+* DESCRIPTION: -+* -+* This function is responsible of intialization of the Pex Interface , It -+* configure the Pex Bars and Windows in the following manner: -+* -+* Assumptions : -+* Bar0 is always internal registers bar -+* Bar1 is always the DRAM bar -+* Bar2 is always the Device bar -+* -+* 1) Sets the Internal registers bar base by obtaining the base from -+* the CPU Interface -+* 2) Sets the DRAM bar base and size by getting the base and size from -+* the CPU Interface when the size is the sum of all enabled DRAM -+* chip selects and the base is the base of CS0 . -+* 3) Sets the Device bar base and size by getting these values from the -+* CPU Interface when the base is the base of the lowest base of the -+* Device chip selects, and the -+* -+* -+* INPUT: -+* -+* pexIf - PEX interface number. -+* -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK if function success otherwise MV_ERROR or MV_BAD_PARAM -+* -+*******************************************************************************/ -+MV_STATUS mvPexVrtBrgInit(MV_U32 pexIf) -+{ -+ /* reset PEX tree to recover previous U-boot/Boot configurations */ -+ MV_U32 localBus = mvPexLocalBusNumGet(pexIf); -+ -+ -+ resetPexConfig(pexIf, localBus, 1); -+ return MV_OK; -+} -+ -+ -+MV_U32 mvPexVrtBrgConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, -+ MV_U32 regOff) -+{ -+ -+ MV_U32 localBus = mvPexLocalBusNumGet(pexIf); -+ MV_U32 localDev = mvPexLocalDevNumGet(pexIf); -+ MV_U32 val; -+ if(bus == localBus) -+ { -+ if(dev > 1) -+ { -+/* on the local device allow only device #0 & #1 */ -+ return 0xffffffff; -+ } -+ else -+ if (dev == localDev) -+ { -+ /* read the memory controller registers */ -+ return mvPexHwConfigRead (pexIf, bus, dev, func, regOff); -+ } -+ else -+ { -+ /* access the virtual brg header */ -+ return HEADER_READ(regOff); -+ } -+ } -+ else -+ if(bus == (localBus + 1)) -+ { -+ /* access the device behind the virtual bridge */ -+ if((dev == localDev) || (dev > 1)) -+ { -+ return 0xffffffff; -+ } -+ else -+ { -+ /* access the device behind the virtual bridge, in this case -+ * change the bus number to the local bus number in order to -+ * generate type 0 config cycle -+ */ -+ mvPexLocalBusNumSet(pexIf, bus); -+ mvPexLocalDevNumSet(pexIf, 1); -+ val = mvPexHwConfigRead (pexIf, bus, 0, func, regOff); -+ mvPexLocalBusNumSet(pexIf, localBus); -+ mvPexLocalDevNumSet(pexIf, localDev); -+ return val; -+ } -+ } -+ /* for all other devices use the HW function to get the -+ * requested registers -+ */ -+ mvPexLocalDevNumSet(pexIf, 1); -+ val = mvPexHwConfigRead (pexIf, bus, dev, func, regOff); -+ mvPexLocalDevNumSet(pexIf, localDev); -+ return val; -+} -+ -+ -+MV_STATUS mvPexVrtBrgConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data) -+{ -+ MV_U32 localBus = mvPexLocalBusNumGet(pexIf); -+ MV_U32 localDev = mvPexLocalDevNumGet(pexIf); -+ MV_STATUS status; -+ -+ if(bus == localBus) -+ { -+ if(dev > 1) -+ { -+ /* on the local device allow only device #0 & #1 */ -+ return MV_ERROR; -+ } -+ else -+ if (dev == localDev) -+ { -+ /* read the memory controller registers */ -+ return mvPexHwConfigWrite (pexIf, bus, dev, func, regOff, data); -+ } -+ else -+ { -+ /* access the virtual brg header */ -+ HEADER_WRITE(data, regOff); -+ return MV_OK; -+ } -+ } -+ else -+ if(bus == (localBus + 1)) -+ { -+ /* access the device behind the virtual bridge */ -+ if((dev == localDev) || (dev > 1)) -+ { -+ return MV_ERROR; -+ } -+ else -+ { -+ /* access the device behind the virtual bridge, in this case -+ * change the bus number to the local bus number in order to -+ * generate type 0 config cycle -+ */ -+ //return mvPexHwConfigWrite (pexIf, localBus, dev, func, regOff, data); -+ mvPexLocalBusNumSet(pexIf, bus); -+ mvPexLocalDevNumSet(pexIf, 1); -+ status = mvPexHwConfigWrite (pexIf, bus, 0, func, regOff, data); -+ mvPexLocalBusNumSet(pexIf, localBus); -+ mvPexLocalDevNumSet(pexIf, localDev); -+ return status; -+ -+ } -+ } -+ /* for all other devices use the HW function to get the -+ * requested registers -+ */ -+ mvPexLocalDevNumSet(pexIf, 1); -+ status = mvPexHwConfigWrite (pexIf, bus, dev, func, regOff, data); -+ mvPexLocalDevNumSet(pexIf, localDev); -+ return status; -+} -+ -+ -+ -+ -+void resetPexConfig(MV_U32 pexIf, MV_U32 bus, MV_U32 dev) -+{ -+ MV_U32 tData; -+ MV_U32 i; -+ -+ /* restore the PEX configuration to initialization state */ -+ /* in case PEX P2P call recursive and reset config */ -+ tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x0); -+ if(tData != 0xffffffff) -+ { -+ /* agent had been found - check whether P2P */ -+ tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x8); -+ if((tData & 0xffff0000) == 0x06040000) -+ {/* P2P */ -+ /* get the sec bus and the subordinate */ -+ MV_U32 secBus; -+ tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x18); -+ secBus = ((tData >> 8) & 0xff); -+ /* now scan on sec bus */ -+ for(i = 0;i < 0xff;i++) -+ { -+ resetPexConfig(pexIf, secBus, i); -+ } -+ /* now reset this device */ -+ DB(mvOsPrintf("Reset bus %d dev %d\n", bus, dev)); -+ mvPexHwConfigWrite(pexIf, bus, dev, 0x0, 0x18, 0x0); -+ DB(mvOsPrintf("Reset bus %d dev %d\n", bus, dev)); -+ } -+ } -+} -+ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h 2010-11-09 20:28:11.861239834 +0100 -@@ -0,0 +1,82 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCVRTBRGPEXH -+#define __INCVRTBRGPEXH -+ -+ -+/* Global Functions prototypes */ -+/* mvPexInit - Initialize PEX interfaces*/ -+MV_STATUS mvPexVrtBrgInit(MV_U32 pexIf); -+ -+/* mvPexConfigRead - Read from configuration space */ -+MV_U32 mvPexVrtBrgConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func,MV_U32 regOff); -+ -+/* mvPexConfigWrite - Write to configuration space */ -+MV_STATUS mvPexVrtBrgConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data); -+ -+ -+#endif /* #ifndef __INCPEXH */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.c 2010-11-09 20:28:11.901246212 +0100 -@@ -0,0 +1,1522 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#include "mvOs.h" -+#include "sflash/mvSFlash.h" -+#include "sflash/mvSFlashSpec.h" -+#include "spi/mvSpi.h" -+#include "spi/mvSpiCmnd.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+ -+/*#define MV_DEBUG*/ -+#ifdef MV_DEBUG -+#define DB(x) x -+#else -+#define DB(x) -+#endif -+ -+/* Globals */ -+static MV_SFLASH_DEVICE_PARAMS sflash[] = { -+ /* ST M25P32 SPI flash, 4MB, 64 sectors of 64K each */ -+ { -+ MV_M25P_WREN_CMND_OPCD, -+ MV_M25P_WRDI_CMND_OPCD, -+ MV_M25P_RDID_CMND_OPCD, -+ MV_M25P_RDSR_CMND_OPCD, -+ MV_M25P_WRSR_CMND_OPCD, -+ MV_M25P_READ_CMND_OPCD, -+ MV_M25P_FAST_RD_CMND_OPCD, -+ MV_M25P_PP_CMND_OPCD, -+ MV_M25P_SE_CMND_OPCD, -+ MV_M25P_BE_CMND_OPCD, -+ MV_M25P_RES_CMND_OPCD, -+ MV_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */ -+ MV_M25P32_SECTOR_SIZE, -+ MV_M25P32_SECTOR_NUMBER, -+ MV_M25P_PAGE_SIZE, -+ "ST M25P32", -+ MV_M25PXXX_ST_MANF_ID, -+ MV_M25P32_DEVICE_ID, -+ MV_M25P32_MAX_SPI_FREQ, -+ MV_M25P32_MAX_FAST_SPI_FREQ, -+ MV_M25P32_FAST_READ_DUMMY_BYTES -+ }, -+ /* ST M25P64 SPI flash, 8MB, 128 sectors of 64K each */ -+ { -+ MV_M25P_WREN_CMND_OPCD, -+ MV_M25P_WRDI_CMND_OPCD, -+ MV_M25P_RDID_CMND_OPCD, -+ MV_M25P_RDSR_CMND_OPCD, -+ MV_M25P_WRSR_CMND_OPCD, -+ MV_M25P_READ_CMND_OPCD, -+ MV_M25P_FAST_RD_CMND_OPCD, -+ MV_M25P_PP_CMND_OPCD, -+ MV_M25P_SE_CMND_OPCD, -+ MV_M25P_BE_CMND_OPCD, -+ MV_M25P_RES_CMND_OPCD, -+ MV_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */ -+ MV_M25P64_SECTOR_SIZE, -+ MV_M25P64_SECTOR_NUMBER, -+ MV_M25P_PAGE_SIZE, -+ "ST M25P64", -+ MV_M25PXXX_ST_MANF_ID, -+ MV_M25P64_DEVICE_ID, -+ MV_M25P64_MAX_SPI_FREQ, -+ MV_M25P64_MAX_FAST_SPI_FREQ, -+ MV_M25P64_FAST_READ_DUMMY_BYTES -+ }, -+ /* ST M25P128 SPI flash, 16MB, 64 sectors of 256K each */ -+ { -+ MV_M25P_WREN_CMND_OPCD, -+ MV_M25P_WRDI_CMND_OPCD, -+ MV_M25P_RDID_CMND_OPCD, -+ MV_M25P_RDSR_CMND_OPCD, -+ MV_M25P_WRSR_CMND_OPCD, -+ MV_M25P_READ_CMND_OPCD, -+ MV_M25P_FAST_RD_CMND_OPCD, -+ MV_M25P_PP_CMND_OPCD, -+ MV_M25P_SE_CMND_OPCD, -+ MV_M25P_BE_CMND_OPCD, -+ MV_M25P_RES_CMND_OPCD, -+ MV_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */ -+ MV_M25P128_SECTOR_SIZE, -+ MV_M25P128_SECTOR_NUMBER, -+ MV_M25P_PAGE_SIZE, -+ "ST M25P128", -+ MV_M25PXXX_ST_MANF_ID, -+ MV_M25P128_DEVICE_ID, -+ MV_M25P128_MAX_SPI_FREQ, -+ MV_M25P128_MAX_FAST_SPI_FREQ, -+ MV_M25P128_FAST_READ_DUMMY_BYTES -+ }, -+ /* Macronix MXIC MX25L6405 SPI flash, 8MB, 128 sectors of 64K each */ -+ { -+ MV_MX25L_WREN_CMND_OPCD, -+ MV_MX25L_WRDI_CMND_OPCD, -+ MV_MX25L_RDID_CMND_OPCD, -+ MV_MX25L_RDSR_CMND_OPCD, -+ MV_MX25L_WRSR_CMND_OPCD, -+ MV_MX25L_READ_CMND_OPCD, -+ MV_MX25L_FAST_RD_CMND_OPCD, -+ MV_MX25L_PP_CMND_OPCD, -+ MV_MX25L_SE_CMND_OPCD, -+ MV_MX25L_BE_CMND_OPCD, -+ MV_MX25L_RES_CMND_OPCD, -+ MV_MX25L_DP_CMND_OPCD, -+ MV_MX25L6405_SECTOR_SIZE, -+ MV_MX25L6405_SECTOR_NUMBER, -+ MV_MXIC_PAGE_SIZE, -+ "MXIC MX25L6405", -+ MV_MXIC_MANF_ID, -+ MV_MX25L6405_DEVICE_ID, -+ MV_MX25L6405_MAX_SPI_FREQ, -+ MV_MX25L6405_MAX_FAST_SPI_FREQ, -+ MV_MX25L6405_FAST_READ_DUMMY_BYTES -+ }, -+ /* SPANSION S25FL128P SPI flash, 16MB, 64 sectors of 256K each */ -+ { -+ MV_S25FL_WREN_CMND_OPCD, -+ MV_S25FL_WRDI_CMND_OPCD, -+ MV_S25FL_RDID_CMND_OPCD, -+ MV_S25FL_RDSR_CMND_OPCD, -+ MV_S25FL_WRSR_CMND_OPCD, -+ MV_S25FL_READ_CMND_OPCD, -+ MV_S25FL_FAST_RD_CMND_OPCD, -+ MV_S25FL_PP_CMND_OPCD, -+ MV_S25FL_SE_CMND_OPCD, -+ MV_S25FL_BE_CMND_OPCD, -+ MV_S25FL_RES_CMND_OPCD, -+ MV_S25FL_DP_CMND_OPCD, -+ MV_S25FL128_SECTOR_SIZE, -+ MV_S25FL128_SECTOR_NUMBER, -+ MV_S25FL_PAGE_SIZE, -+ "SPANSION S25FL128", -+ MV_SPANSION_MANF_ID, -+ MV_S25FL128_DEVICE_ID, -+ MV_S25FL128_MAX_SPI_FREQ, -+ MV_M25P128_MAX_FAST_SPI_FREQ, -+ MV_M25P128_FAST_READ_DUMMY_BYTES -+ } -+}; -+ -+/* Static Functions */ -+static MV_STATUS mvWriteEnable (MV_SFLASH_INFO * pFlinfo); -+static MV_STATUS mvStatusRegGet (MV_SFLASH_INFO * pFlinfo, MV_U8 * pStatReg); -+static MV_STATUS mvStatusRegSet (MV_SFLASH_INFO * pFlinfo, MV_U8 sr); -+static MV_STATUS mvWaitOnWipClear(MV_SFLASH_INFO * pFlinfo); -+static MV_STATUS mvSFlashPageWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, \ -+ MV_U8* pPageBuff, MV_U32 buffSize); -+static MV_STATUS mvSFlashWithDefaultsIdGet (MV_SFLASH_INFO * pFlinfo, \ -+ MV_U8* manId, MV_U16* devId); -+ -+/******************************************************************************* -+* mvWriteEnable - serialize the write enable sequence -+* -+* DESCRIPTION: -+* transmit the sequence for write enable -+* -+********************************************************************************/ -+static MV_STATUS mvWriteEnable(MV_SFLASH_INFO * pFlinfo) -+{ -+ MV_U8 cmd[MV_SFLASH_WREN_CMND_LENGTH]; -+ -+ -+ cmd[0] = sflash[pFlinfo->index].opcdWREN; -+ -+ return mvSpiWriteThenRead(cmd, MV_SFLASH_WREN_CMND_LENGTH, NULL, 0, 0); -+} -+ -+/******************************************************************************* -+* mvStatusRegGet - Retrieve the value of the status register -+* -+* DESCRIPTION: -+* perform the RDSR sequence to get the 8bit status register -+* -+********************************************************************************/ -+static MV_STATUS mvStatusRegGet(MV_SFLASH_INFO * pFlinfo, MV_U8 * pStatReg) -+{ -+ MV_STATUS ret; -+ MV_U8 cmd[MV_SFLASH_RDSR_CMND_LENGTH]; -+ MV_U8 sr[MV_SFLASH_RDSR_REPLY_LENGTH]; -+ -+ -+ -+ -+ cmd[0] = sflash[pFlinfo->index].opcdRDSR; -+ -+ if ((ret = mvSpiWriteThenRead(cmd, MV_SFLASH_RDSR_CMND_LENGTH, sr, -+ MV_SFLASH_RDSR_REPLY_LENGTH,0)) != MV_OK) -+ return ret; -+ -+ *pStatReg = sr[0]; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvWaitOnWipClear - Block waiting for the WIP (write in progress) to be cleared -+* -+* DESCRIPTION: -+* Block waiting for the WIP (write in progress) to be cleared -+* -+********************************************************************************/ -+static MV_STATUS mvWaitOnWipClear(MV_SFLASH_INFO * pFlinfo) -+{ -+ MV_STATUS ret; -+ MV_U32 i; -+ MV_U8 stat; -+ -+ for (i=0; iindex].opcdWRSR; -+ cmd[1] = sr; -+ -+ if ((ret = mvSpiWriteThenRead(cmd, MV_SFLASH_WRSR_CMND_LENGTH, NULL, 0, 0)) != MV_OK) -+ return ret; -+ -+ if ((ret = mvWaitOnWipClear(pFlinfo)) != MV_OK) -+ return ret; -+ -+ mvOsDelay(1); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSFlashPageWr - Write up to 256 Bytes in the same page -+* -+* DESCRIPTION: -+* Write a buffer up to the page size in length provided that the whole address -+* range is within the same page (alligned to page bounderies) -+* -+*******************************************************************************/ -+static MV_STATUS mvSFlashPageWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, -+ MV_U8* pPageBuff, MV_U32 buffSize) -+{ -+ MV_STATUS ret; -+ MV_U8 cmd[MV_SFLASH_PP_CMND_LENGTH]; -+ -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invalid parameter device index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* check that we do not cross the page bounderies */ -+ if (((offset & (sflash[pFlinfo->index].pageSize - 1)) + buffSize) > -+ sflash[pFlinfo->index].pageSize) -+ { -+ DB(mvOsPrintf("%s WARNING: Page allignment problem!\n", __FUNCTION__);) -+ return MV_OUT_OF_RANGE; -+ } -+ -+ /* Issue the Write enable command prior the page program command */ -+ if ((ret = mvWriteEnable(pFlinfo)) != MV_OK) -+ return ret; -+ -+ cmd[0] = sflash[pFlinfo->index].opcdPP; -+ cmd[1] = ((offset >> 16) & 0xFF); -+ cmd[2] = ((offset >> 8) & 0xFF); -+ cmd[3] = (offset & 0xFF); -+ -+ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_PP_CMND_LENGTH, pPageBuff, buffSize)) != MV_OK) -+ return ret; -+ -+ if ((ret = mvWaitOnWipClear(pFlinfo)) != MV_OK) -+ return ret; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSFlashWithDefaultsIdGet - Try to read the manufacturer and Device IDs from -+* the device using the default RDID opcode and the default WREN opcode. -+* -+* DESCRIPTION: -+* This is used to detect a generic device that uses the default opcodes -+* for the WREN and RDID. -+* -+********************************************************************************/ -+static MV_STATUS mvSFlashWithDefaultsIdGet (MV_SFLASH_INFO * pFlinfo, MV_U8* manId, MV_U16* devId) -+{ -+ MV_STATUS ret; -+ MV_U8 cmdRDID[MV_SFLASH_RDID_CMND_LENGTH]; -+ MV_U8 id[MV_SFLASH_RDID_REPLY_LENGTH]; -+ -+ -+ -+ /* Use the default RDID opcode to read the IDs */ -+ cmdRDID[0] = MV_SFLASH_DEFAULT_RDID_OPCD; /* unknown model try default */ -+ if ((ret = mvSpiWriteThenRead(cmdRDID, MV_SFLASH_RDID_CMND_LENGTH, id, MV_SFLASH_RDID_REPLY_LENGTH, 0)) != MV_OK) -+ return ret; -+ -+ *manId = id[0]; -+ *devId = 0; -+ *devId |= (id[1] << 8); -+ *devId |= id[2]; -+ -+ return MV_OK; -+} -+ -+/* -+##################################################################################### -+##################################################################################### -+*/ -+ -+/******************************************************************************* -+* mvSFlashInit - Initialize the serial flash device -+* -+* DESCRIPTION: -+* Perform the neccessary initialization and configuration -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* pFlinfo->baseAddr: base address in fast mode. -+* pFlinfo->index: Index of the flash in the sflash tabel. If the SPI -+* flash device does not support read Id command with -+* the standard opcode, then the user should supply this -+* as an input to skip the autodetection process!!!! -+* -+* OUTPUT: -+* pFlinfo: pointer to the Flash information structure after detection -+* pFlinfo->manufacturerId: Manufacturer ID -+* pFlinfo->deviceId: Device ID -+* pFlinfo->sectorSize: size of the sector (all sectors are the same). -+* pFlinfo->sectorNumber: number of sectors. -+* pFlinfo->pageSize: size of the page. -+* pFlinfo->index: Index of the detected flash in the sflash tabel -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashInit (MV_SFLASH_INFO * pFlinfo) -+{ -+ MV_STATUS ret; -+ MV_U8 manf; -+ MV_U16 dev; -+ MV_U32 indx; -+ MV_BOOL detectFlag = MV_FALSE; -+ -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Initialize the SPI interface with low frequency to make sure that the read ID succeeds */ -+ if ((ret = mvSpiInit(MV_SFLASH_BASIC_SPI_FREQ)) != MV_OK) -+ { -+ mvOsPrintf("%s ERROR: Failed to initialize the SPI interface!\n", __FUNCTION__); -+ return ret; -+ } -+ -+ /* First try to read the Manufacturer and Device IDs */ -+ if ((ret = mvSFlashIdGet(pFlinfo, &manf, &dev)) != MV_OK) -+ { -+ mvOsPrintf("%s ERROR: Failed to get the SFlash ID!\n", __FUNCTION__); -+ return ret; -+ } -+ -+ /* loop over the whole table and look for the appropriate SFLASH */ -+ for (indx=0; indxmanufacturerId = manf; -+ pFlinfo->deviceId = dev; -+ pFlinfo->index = indx; -+ detectFlag = MV_TRUE; -+ } -+ } -+ -+ if(!detectFlag) -+ { -+ mvOsPrintf("%s ERROR: Unknown SPI flash device!\n", __FUNCTION__); -+ return MV_FAIL; -+ } -+ -+ /* fill the info based on the model detected */ -+ pFlinfo->sectorSize = sflash[pFlinfo->index].sectorSize; -+ pFlinfo->sectorNumber = sflash[pFlinfo->index].sectorNumber; -+ pFlinfo->pageSize = sflash[pFlinfo->index].pageSize; -+ -+ /* Set the SPI frequency to the MAX allowed for the device for best performance */ -+ if ((ret = mvSpiBaudRateSet(sflash[pFlinfo->index].spiMaxFreq)) != MV_OK) -+ { -+ mvOsPrintf("%s ERROR: Failed to set the SPI frequency!\n", __FUNCTION__); -+ return ret; -+ } -+ -+ /* As default lock the SR */ -+ if ((ret = mvSFlashStatRegLock(pFlinfo, MV_TRUE)) != MV_OK) -+ return ret; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSFlashSectorErase - Erasse a single sector of the serial flash -+* -+* DESCRIPTION: -+* Issue the erase sector command and address -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* secNumber: sector Number to erase (0 -> (sectorNumber-1)) -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashSectorErase (MV_SFLASH_INFO * pFlinfo, MV_U32 secNumber) -+{ -+ MV_STATUS ret; -+ MV_U8 cmd[MV_SFLASH_SE_CMND_LENGTH]; -+ -+ MV_U32 secAddr = (secNumber * pFlinfo->sectorSize); -+#if 0 -+ MV_U32 i; -+ MV_U32 * pW = (MV_U32*) (secAddr + pFlinfo->baseAddr); -+ MV_U32 erasedWord = 0xFFFFFFFF; -+ MV_U32 wordsPerSector = (pFlinfo->sectorSize / sizeof(MV_U32)); -+ MV_BOOL eraseNeeded = MV_FALSE; -+#endif -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* check that the sector number is valid */ -+ if (secNumber >= pFlinfo->sectorNumber) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter sector number!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* we don't want to access SPI in direct mode from in-direct API, -+ becasue of timing issue between CS asserts. */ -+#if 0 -+ /* First compare to FF and check if erase is needed */ -+ for (i=0; iindex].opcdSE; -+ cmd[1] = ((secAddr >> 16) & 0xFF); -+ cmd[2] = ((secAddr >> 8) & 0xFF); -+ cmd[3] = (secAddr & 0xFF); -+ -+ /* Issue the Write enable command prior the sector erase command */ -+ if ((ret = mvWriteEnable(pFlinfo)) != MV_OK) -+ return ret; -+ -+ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_SE_CMND_LENGTH, NULL, 0)) != MV_OK) -+ return ret; -+ -+ if ((ret = mvWaitOnWipClear(pFlinfo)) != MV_OK) -+ return ret; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSFlashChipErase - Erasse the whole serial flash -+* -+* DESCRIPTION: -+* Issue the bulk (chip) erase command -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashChipErase (MV_SFLASH_INFO * pFlinfo) -+{ -+ MV_STATUS ret; -+ MV_U8 cmd[MV_SFLASH_BE_CMND_LENGTH]; -+ -+ -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ cmd[0] = sflash[pFlinfo->index].opcdBE; -+ -+ /* Issue the Write enable command prior the Bulk erase command */ -+ if ((ret = mvWriteEnable(pFlinfo)) != MV_OK) -+ return ret; -+ -+ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_BE_CMND_LENGTH, NULL, 0)) != MV_OK) -+ return ret; -+ -+ if ((ret = mvWaitOnChipEraseDone(pFlinfo)) != MV_OK) -+ return ret; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSFlashBlockRd - Read from the serial flash -+* -+* DESCRIPTION: -+* Issue the read command and address then perfom the needed read -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* offset: byte offset with the flash to start reading from -+* pReadBuff: pointer to the buffer to read the data in -+* buffSize: size of the buffer to read. -+* -+* OUTPUT: -+* pReadBuff: pointer to the buffer containing the read data -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, -+ MV_U8* pReadBuff, MV_U32 buffSize) -+{ -+ MV_U8 cmd[MV_SFLASH_READ_CMND_LENGTH]; -+ -+ -+ /* check for NULL pointer */ -+ if ((pFlinfo == NULL) || (pReadBuff == NULL)) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ cmd[0] = sflash[pFlinfo->index].opcdREAD; -+ cmd[1] = ((offset >> 16) & 0xFF); -+ cmd[2] = ((offset >> 8) & 0xFF); -+ cmd[3] = (offset & 0xFF); -+ -+ return mvSpiWriteThenRead(cmd, MV_SFLASH_READ_CMND_LENGTH, pReadBuff, buffSize, 0); -+} -+ -+/******************************************************************************* -+* mvSFlashFastBlockRd - Fast read from the serial flash -+* -+* DESCRIPTION: -+* Issue the fast read command and address then perfom the needed read -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* offset: byte offset with the flash to start reading from -+* pReadBuff: pointer to the buffer to read the data in -+* buffSize: size of the buffer to read. -+* -+* OUTPUT: -+* pReadBuff: pointer to the buffer containing the read data -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashFastBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, -+ MV_U8* pReadBuff, MV_U32 buffSize) -+{ -+ MV_U8 cmd[MV_SFLASH_READ_CMND_LENGTH]; -+ MV_STATUS ret; -+ -+ /* check for NULL pointer */ -+ if ((pFlinfo == NULL) || (pReadBuff == NULL)) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* Set the SPI frequency to the MAX allowed for fast-read operations */ -+ mvOsPrintf("Setting freq to %d.\n",sflash[pFlinfo->index].spiMaxFastFreq); -+ if ((ret = mvSpiBaudRateSet(sflash[pFlinfo->index].spiMaxFastFreq)) != MV_OK) -+ { -+ mvOsPrintf("%s ERROR: Failed to set the SPI fast frequency!\n", __FUNCTION__); -+ return ret; -+ } -+ -+ cmd[0] = sflash[pFlinfo->index].opcdFSTRD; -+ cmd[1] = ((offset >> 16) & 0xFF); -+ cmd[2] = ((offset >> 8) & 0xFF); -+ cmd[3] = (offset & 0xFF); -+ -+ -+ ret = mvSpiWriteThenRead(cmd, MV_SFLASH_READ_CMND_LENGTH, pReadBuff, buffSize, -+ sflash[pFlinfo->index].spiFastRdDummyBytes); -+ -+ /* Reset the SPI frequency to the MAX allowed for the device for best performance */ -+ if ((ret = mvSpiBaudRateSet(sflash[pFlinfo->index].spiMaxFreq)) != MV_OK) -+ { -+ mvOsPrintf("%s ERROR: Failed to set the SPI frequency!\n", __FUNCTION__); -+ return ret; -+ } -+ -+ return ret; -+} -+ -+ -+/******************************************************************************* -+* mvSFlashBlockWr - Write a buffer with any size -+* -+* DESCRIPTION: -+* write regardless of the page boundaries and size limit per Page -+* program command -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* offset: byte offset within the flash region -+* pWriteBuff: pointer to the buffer holding the data to program -+* buffSize: size of the buffer to write -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashBlockWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, -+ MV_U8* pWriteBuff, MV_U32 buffSize) -+{ -+ MV_STATUS ret; -+ MV_U32 data2write = buffSize; -+ MV_U32 preAllOffset = (offset & MV_SFLASH_PAGE_ALLIGN_MASK(MV_M25P_PAGE_SIZE)); -+ MV_U32 preAllSz = (preAllOffset ? (MV_M25P_PAGE_SIZE - preAllOffset) : 0); -+ MV_U32 writeOffset = offset; -+ -+ /* check for NULL pointer */ -+#ifndef CONFIG_MARVELL -+ if(NULL == pWriteBuff) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+#endif -+ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* check that the buffer size does not exceed the flash size */ -+ if ((offset + buffSize) > mvSFlashSizeGet(pFlinfo)) -+ { -+ DB(mvOsPrintf("%s WARNING: Write exceeds flash size!\n", __FUNCTION__);) -+ return MV_OUT_OF_RANGE; -+ } -+ -+ /* check if the total block size is less than the first chunk remainder */ -+ if (data2write < preAllSz) -+ preAllSz = data2write; -+ -+ /* check if programing does not start at a 64byte alligned offset */ -+ if (preAllSz) -+ { -+ if ((ret = mvSFlashPageWr(pFlinfo, writeOffset, pWriteBuff, preAllSz)) != MV_OK) -+ return ret; -+ -+ /* increment pointers and counters */ -+ writeOffset += preAllSz; -+ data2write -= preAllSz; -+ pWriteBuff += preAllSz; -+ } -+ -+ /* program the data that fits in complete page chunks */ -+ while (data2write >= sflash[pFlinfo->index].pageSize) -+ { -+ if ((ret = mvSFlashPageWr(pFlinfo, writeOffset, pWriteBuff, sflash[pFlinfo->index].pageSize)) != MV_OK) -+ return ret; -+ -+ /* increment pointers and counters */ -+ writeOffset += sflash[pFlinfo->index].pageSize; -+ data2write -= sflash[pFlinfo->index].pageSize; -+ pWriteBuff += sflash[pFlinfo->index].pageSize; -+ } -+ -+ /* program the last partial chunk */ -+ if (data2write) -+ { -+ if ((ret = mvSFlashPageWr(pFlinfo, writeOffset, pWriteBuff, data2write)) != MV_OK) -+ return ret; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSFlashIdGet - Get the manufacturer and device IDs. -+* -+* DESCRIPTION: -+* Get the Manufacturer and device IDs from the serial flash through -+* writing the RDID command then reading 3 bytes of data. In case that -+* this command was called for the first time in order to detect the -+* manufacturer and device IDs, then the default RDID opcode will be used -+* unless the device index is indicated by the user (in case the SPI flash -+* does not use the default RDID opcode). -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* pManId: pointer to the 8bit variable to hold the manufacturing ID -+* pDevId: pointer to the 16bit variable to hold the device ID -+* -+* OUTPUT: -+* pManId: pointer to the 8bit variable holding the manufacturing ID -+* pDevId: pointer to the 16bit variable holding the device ID -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashIdGet (MV_SFLASH_INFO * pFlinfo, MV_U8* pManId, MV_U16* pDevId) -+{ -+ MV_STATUS ret; -+ MV_U8 cmd[MV_SFLASH_RDID_CMND_LENGTH]; -+ MV_U8 id[MV_SFLASH_RDID_REPLY_LENGTH]; -+ -+ -+ -+ /* check for NULL pointer */ -+ if ((pFlinfo == NULL) || (pManId == NULL) || (pDevId == NULL)) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ return mvSFlashWithDefaultsIdGet(pFlinfo, pManId, pDevId); -+ else -+ cmd[0] = sflash[pFlinfo->index].opcdRDID; -+ -+ if ((ret = mvSpiWriteThenRead(cmd, MV_SFLASH_RDID_CMND_LENGTH, id, MV_SFLASH_RDID_REPLY_LENGTH, 0)) != MV_OK) -+ return ret; -+ -+ *pManId = id[0]; -+ *pDevId = 0; -+ *pDevId |= (id[1] << 8); -+ *pDevId |= id[2]; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSFlashWpRegionSet - Set the Write-Protected region -+* -+* DESCRIPTION: -+* Set the Write-Protected region -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* wpRegion: which region will be protected -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashWpRegionSet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION wpRegion) -+{ -+ MV_U8 wpMask; -+ -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the chip is an ST flash; then WP supports only 3 bits */ -+ if (pFlinfo->manufacturerId == MV_M25PXXX_ST_MANF_ID) -+ { -+ switch (wpRegion) -+ { -+ case MV_WP_NONE: -+ wpMask = MV_M25P_STATUS_BP_NONE; -+ break; -+ -+ case MV_WP_UPR_1OF128: -+ DB(mvOsPrintf("%s WARNING: Invaild option for this flash chip!\n", __FUNCTION__);) -+ return MV_NOT_SUPPORTED; -+ -+ case MV_WP_UPR_1OF64: -+ wpMask = MV_M25P_STATUS_BP_1_OF_64; -+ break; -+ -+ case MV_WP_UPR_1OF32: -+ wpMask = MV_M25P_STATUS_BP_1_OF_32; -+ break; -+ -+ case MV_WP_UPR_1OF16: -+ wpMask = MV_M25P_STATUS_BP_1_OF_16; -+ break; -+ -+ case MV_WP_UPR_1OF8: -+ wpMask = MV_M25P_STATUS_BP_1_OF_8; -+ break; -+ -+ case MV_WP_UPR_1OF4: -+ wpMask = MV_M25P_STATUS_BP_1_OF_4; -+ break; -+ -+ case MV_WP_UPR_1OF2: -+ wpMask = MV_M25P_STATUS_BP_1_OF_2; -+ break; -+ -+ case MV_WP_ALL: -+ wpMask = MV_M25P_STATUS_BP_ALL; -+ break; -+ -+ default: -+ DB(mvOsPrintf("%s WARNING: Invaild parameter WP region!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ } -+ /* check if the manufacturer is MXIC then the WP is 4bits */ -+ else if (pFlinfo->manufacturerId == MV_MXIC_MANF_ID) -+ { -+ switch (wpRegion) -+ { -+ case MV_WP_NONE: -+ wpMask = MV_MX25L_STATUS_BP_NONE; -+ break; -+ -+ case MV_WP_UPR_1OF128: -+ wpMask = MV_MX25L_STATUS_BP_1_OF_128; -+ break; -+ -+ case MV_WP_UPR_1OF64: -+ wpMask = MV_MX25L_STATUS_BP_1_OF_64; -+ break; -+ -+ case MV_WP_UPR_1OF32: -+ wpMask = MV_MX25L_STATUS_BP_1_OF_32; -+ break; -+ -+ case MV_WP_UPR_1OF16: -+ wpMask = MV_MX25L_STATUS_BP_1_OF_16; -+ break; -+ -+ case MV_WP_UPR_1OF8: -+ wpMask = MV_MX25L_STATUS_BP_1_OF_8; -+ break; -+ -+ case MV_WP_UPR_1OF4: -+ wpMask = MV_MX25L_STATUS_BP_1_OF_4; -+ break; -+ -+ case MV_WP_UPR_1OF2: -+ wpMask = MV_MX25L_STATUS_BP_1_OF_2; -+ break; -+ -+ case MV_WP_ALL: -+ wpMask = MV_MX25L_STATUS_BP_ALL; -+ break; -+ -+ default: -+ DB(mvOsPrintf("%s WARNING: Invaild parameter WP region!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ } -+ /* check if the manufacturer is SPANSION then the WP is 4bits */ -+ else if (pFlinfo->manufacturerId == MV_SPANSION_MANF_ID) -+ { -+ switch (wpRegion) -+ { -+ case MV_WP_NONE: -+ wpMask = MV_S25FL_STATUS_BP_NONE; -+ break; -+ -+ case MV_WP_UPR_1OF128: -+ DB(mvOsPrintf("%s WARNING: Invaild option for this flash chip!\n", __FUNCTION__);) -+ return MV_NOT_SUPPORTED; -+ -+ case MV_WP_UPR_1OF64: -+ wpMask = MV_S25FL_STATUS_BP_1_OF_64; -+ break; -+ -+ case MV_WP_UPR_1OF32: -+ wpMask = MV_S25FL_STATUS_BP_1_OF_32; -+ break; -+ -+ case MV_WP_UPR_1OF16: -+ wpMask = MV_S25FL_STATUS_BP_1_OF_16; -+ break; -+ -+ case MV_WP_UPR_1OF8: -+ wpMask = MV_S25FL_STATUS_BP_1_OF_8; -+ break; -+ -+ case MV_WP_UPR_1OF4: -+ wpMask = MV_S25FL_STATUS_BP_1_OF_4; -+ break; -+ -+ case MV_WP_UPR_1OF2: -+ wpMask = MV_S25FL_STATUS_BP_1_OF_2; -+ break; -+ -+ case MV_WP_ALL: -+ wpMask = MV_S25FL_STATUS_BP_ALL; -+ break; -+ -+ -+ default: -+ DB(mvOsPrintf("%s WARNING: Invaild parameter WP region!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ } -+ else -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter Manufacturer ID!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* Verify that the SRWD bit is always set - register is s/w locked */ -+ wpMask |= MV_SFLASH_STATUS_REG_SRWD_MASK; -+ -+ return mvStatusRegSet(pFlinfo, wpMask); -+} -+ -+/******************************************************************************* -+* mvSFlashWpRegionGet - Get the Write-Protected region configured -+* -+* DESCRIPTION: -+* Get from the chip the Write-Protected region configured -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* pWpRegion: pointer to the variable to return the WP region in -+* -+* OUTPUT: -+* wpRegion: pointer to the variable holding the WP region configured -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashWpRegionGet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION * pWpRegion) -+{ -+ MV_STATUS ret; -+ MV_U8 reg; -+ -+ /* check for NULL pointer */ -+ if ((pFlinfo == NULL) || (pWpRegion == NULL)) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ if ((ret = mvStatusRegGet(pFlinfo, ®)) != MV_OK) -+ return ret; -+ -+ /* Check if the chip is an ST flash; then WP supports only 3 bits */ -+ if (pFlinfo->manufacturerId == MV_M25PXXX_ST_MANF_ID) -+ { -+ switch ((reg & MV_M25P_STATUS_REG_WP_MASK)) -+ { -+ case MV_M25P_STATUS_BP_NONE: -+ *pWpRegion = MV_WP_NONE; -+ break; -+ -+ case MV_M25P_STATUS_BP_1_OF_64: -+ *pWpRegion = MV_WP_UPR_1OF64; -+ break; -+ -+ case MV_M25P_STATUS_BP_1_OF_32: -+ *pWpRegion = MV_WP_UPR_1OF32; -+ break; -+ -+ case MV_M25P_STATUS_BP_1_OF_16: -+ *pWpRegion = MV_WP_UPR_1OF16; -+ break; -+ -+ case MV_M25P_STATUS_BP_1_OF_8: -+ *pWpRegion = MV_WP_UPR_1OF8; -+ break; -+ -+ case MV_M25P_STATUS_BP_1_OF_4: -+ *pWpRegion = MV_WP_UPR_1OF4; -+ break; -+ -+ case MV_M25P_STATUS_BP_1_OF_2: -+ *pWpRegion = MV_WP_UPR_1OF2; -+ break; -+ -+ case MV_M25P_STATUS_BP_ALL: -+ *pWpRegion = MV_WP_ALL; -+ break; -+ -+ default: -+ DB(mvOsPrintf("%s WARNING: Unidentified WP region in h/w!\n", __FUNCTION__);) -+ return MV_BAD_VALUE; -+ } -+ } -+ /* check if the manufacturer is MXIC then the WP is 4bits */ -+ else if (pFlinfo->manufacturerId == MV_MXIC_MANF_ID) -+ { -+ switch ((reg & MV_MX25L_STATUS_REG_WP_MASK)) -+ { -+ case MV_MX25L_STATUS_BP_NONE: -+ *pWpRegion = MV_WP_NONE; -+ break; -+ -+ case MV_MX25L_STATUS_BP_1_OF_128: -+ *pWpRegion = MV_WP_UPR_1OF128; -+ break; -+ -+ case MV_MX25L_STATUS_BP_1_OF_64: -+ *pWpRegion = MV_WP_UPR_1OF64; -+ break; -+ -+ case MV_MX25L_STATUS_BP_1_OF_32: -+ *pWpRegion = MV_WP_UPR_1OF32; -+ break; -+ -+ case MV_MX25L_STATUS_BP_1_OF_16: -+ *pWpRegion = MV_WP_UPR_1OF16; -+ break; -+ -+ case MV_MX25L_STATUS_BP_1_OF_8: -+ *pWpRegion = MV_WP_UPR_1OF8; -+ break; -+ -+ case MV_MX25L_STATUS_BP_1_OF_4: -+ *pWpRegion = MV_WP_UPR_1OF4; -+ break; -+ -+ case MV_MX25L_STATUS_BP_1_OF_2: -+ *pWpRegion = MV_WP_UPR_1OF2; -+ break; -+ -+ case MV_MX25L_STATUS_BP_ALL: -+ *pWpRegion = MV_WP_ALL; -+ break; -+ -+ default: -+ DB(mvOsPrintf("%s WARNING: Unidentified WP region in h/w!\n", __FUNCTION__);) -+ return MV_BAD_VALUE; -+ } -+ } -+ /* Check if the chip is an SPANSION flash; then WP supports only 3 bits */ -+ else if (pFlinfo->manufacturerId == MV_SPANSION_MANF_ID) -+ { -+ switch ((reg & MV_S25FL_STATUS_REG_WP_MASK)) -+ { -+ case MV_S25FL_STATUS_BP_NONE: -+ *pWpRegion = MV_WP_NONE; -+ break; -+ -+ case MV_S25FL_STATUS_BP_1_OF_64: -+ *pWpRegion = MV_WP_UPR_1OF64; -+ break; -+ -+ case MV_S25FL_STATUS_BP_1_OF_32: -+ *pWpRegion = MV_WP_UPR_1OF32; -+ break; -+ -+ case MV_S25FL_STATUS_BP_1_OF_16: -+ *pWpRegion = MV_WP_UPR_1OF16; -+ break; -+ -+ case MV_S25FL_STATUS_BP_1_OF_8: -+ *pWpRegion = MV_WP_UPR_1OF8; -+ break; -+ -+ case MV_S25FL_STATUS_BP_1_OF_4: -+ *pWpRegion = MV_WP_UPR_1OF4; -+ break; -+ -+ case MV_S25FL_STATUS_BP_1_OF_2: -+ *pWpRegion = MV_WP_UPR_1OF2; -+ break; -+ -+ case MV_S25FL_STATUS_BP_ALL: -+ *pWpRegion = MV_WP_ALL; -+ break; -+ -+ default: -+ DB(mvOsPrintf("%s WARNING: Unidentified WP region in h/w!\n", __FUNCTION__);) -+ return MV_BAD_VALUE; -+ } -+ } -+ else -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter Manufacturer ID!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSFlashStatRegLock - Lock the status register for writing - W/Vpp -+* pin should be low to take effect -+* -+* DESCRIPTION: -+* Lock the access to the Status Register for writing. This will -+* cause the flash to enter the hardware protection mode if the W/Vpp -+* is low. If the W/Vpp is hi, the chip will be in soft protection mode, but -+* the register will continue to be writable if WREN sequence was used. -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* srLock: enable/disable (MV_TRUE/MV_FALSE) status registor lock mechanism -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashStatRegLock (MV_SFLASH_INFO * pFlinfo, MV_BOOL srLock) -+{ -+ MV_STATUS ret; -+ MV_U8 reg; -+ -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ if ((ret = mvStatusRegGet(pFlinfo, ®)) != MV_OK) -+ return ret; -+ -+ if (srLock) -+ reg |= MV_SFLASH_STATUS_REG_SRWD_MASK; -+ else -+ reg &= ~MV_SFLASH_STATUS_REG_SRWD_MASK; -+ -+ return mvStatusRegSet(pFlinfo, reg); -+} -+ -+/******************************************************************************* -+* mvSFlashSizeGet - Get the size of the SPI flash -+* -+* DESCRIPTION: -+* based on the sector number and size of each sector calculate the total -+* size of the flash memory. -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Size of the flash in bytes. -+* -+* -+*******************************************************************************/ -+MV_U32 mvSFlashSizeGet (MV_SFLASH_INFO * pFlinfo) -+{ -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return 0; -+ } -+ -+ return (pFlinfo->sectorSize * pFlinfo->sectorNumber); -+} -+ -+/******************************************************************************* -+* mvSFlashPowerSaveEnter - Cause the falsh device to go into power save mode -+* -+* DESCRIPTION: -+* Enter a special power save mode. -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Size of the flash in bytes. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashPowerSaveEnter(MV_SFLASH_INFO * pFlinfo) -+{ -+ MV_STATUS ret; -+ MV_U8 cmd[MV_SFLASH_DP_CMND_LENGTH]; -+ -+ -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return 0; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* check that power save mode is supported in the specific device */ -+ if (sflash[pFlinfo->index].opcdPwrSave == MV_SFLASH_NO_SPECIFIC_OPCD) -+ { -+ DB(mvOsPrintf("%s WARNING: Power save not supported for this device!\n", __FUNCTION__);) -+ return MV_NOT_SUPPORTED; -+ } -+ -+ cmd[0] = sflash[pFlinfo->index].opcdPwrSave; -+ -+ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_DP_CMND_LENGTH, NULL, 0)) != MV_OK) -+ return ret; -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvSFlashPowerSaveExit - Cause the falsh device to exit the power save mode -+* -+* DESCRIPTION: -+* Exit the deep power save mode. -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Size of the flash in bytes. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashPowerSaveExit (MV_SFLASH_INFO * pFlinfo) -+{ -+ MV_STATUS ret; -+ MV_U8 cmd[MV_SFLASH_RES_CMND_LENGTH]; -+ -+ -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return 0; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* check that power save mode is supported in the specific device */ -+ if (sflash[pFlinfo->index].opcdRES == MV_SFLASH_NO_SPECIFIC_OPCD) -+ { -+ DB(mvOsPrintf("%s WARNING: Read Electronic Signature not supported for this device!\n", __FUNCTION__);) -+ return MV_NOT_SUPPORTED; -+ } -+ -+ cmd[0] = sflash[pFlinfo->index].opcdRES; -+ -+ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_RES_CMND_LENGTH, NULL, 0)) != MV_OK) -+ return ret; -+ -+ /* add the delay needed for the device to wake up */ -+ mvOsDelay(MV_MXIC_DP_EXIT_DELAY); /* 30 ms */ -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvSFlashModelGet - Retreive the string with the device manufacturer and model -+* -+* DESCRIPTION: -+* Retreive the string with the device manufacturer and model -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* pointer to the string indicating the device manufacturer and model -+* -+* -+*******************************************************************************/ -+const MV_8 * mvSFlashModelGet (MV_SFLASH_INFO * pFlinfo) -+{ -+ static const MV_8 * unknModel = (const MV_8 *)"Unknown"; -+ -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return 0; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return unknModel; -+ } -+ -+ return sflash[pFlinfo->index].deviceModel; -+} -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.h 2010-11-09 20:28:11.941246441 +0100 -@@ -0,0 +1,166 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvSFlashH -+#define __INCmvSFlashH -+ -+#include "mvTypes.h" -+ -+/* MCAROS */ -+#define MV_SFLASH_PAGE_ALLIGN_MASK(pgSz) (pgSz-1) -+#define MV_ARRAY_SIZE(a) ((sizeof(a)) / (sizeof(a[0]))) -+ -+/* Constants */ -+#define MV_INVALID_DEVICE_NUMBER 0xFFFFFFFF -+/* 10 MHz is the minimum possible SPI frequency when tclk is set 200MHz*/ -+#define MV_SFLASH_BASIC_SPI_FREQ 10000000 -+/* enumerations */ -+typedef enum -+{ -+ MV_WP_NONE, /* Unprotect the whole chip */ -+ MV_WP_UPR_1OF128, /* Write protect the upper 1/128 part */ -+ MV_WP_UPR_1OF64, /* Write protect the upper 1/64 part */ -+ MV_WP_UPR_1OF32, /* Write protect the upper 1/32 part */ -+ MV_WP_UPR_1OF16, /* Write protect the upper 1/16 part */ -+ MV_WP_UPR_1OF8, /* Write protect the upper 1/8 part */ -+ MV_WP_UPR_1OF4, /* Write protect the upper 1/4 part */ -+ MV_WP_UPR_1OF2, /* Write protect the upper 1/2 part */ -+ MV_WP_ALL /* Write protect the whole chip */ -+} MV_SFLASH_WP_REGION; -+ -+/* Type Definitions */ -+typedef struct -+{ -+ MV_U8 opcdWREN; /* Write enable opcode */ -+ MV_U8 opcdWRDI; /* Write disable opcode */ -+ MV_U8 opcdRDID; /* Read ID opcode */ -+ MV_U8 opcdRDSR; /* Read Status Register opcode */ -+ MV_U8 opcdWRSR; /* Write Status register opcode */ -+ MV_U8 opcdREAD; /* Read opcode */ -+ MV_U8 opcdFSTRD; /* Fast Read opcode */ -+ MV_U8 opcdPP; /* Page program opcode */ -+ MV_U8 opcdSE; /* Sector erase opcode */ -+ MV_U8 opcdBE; /* Bulk erase opcode */ -+ MV_U8 opcdRES; /* Read electronic signature */ -+ MV_U8 opcdPwrSave; /* Go into power save mode */ -+ MV_U32 sectorSize; /* Size of each sector */ -+ MV_U32 sectorNumber; /* Number of sectors */ -+ MV_U32 pageSize; /* size of each page */ -+ const char * deviceModel; /* string with the device model */ -+ MV_U32 manufacturerId; /* The manufacturer ID */ -+ MV_U32 deviceId; /* Device ID */ -+ MV_U32 spiMaxFreq; /* The MAX frequency that can be used with the device */ -+ MV_U32 spiMaxFastFreq; /* The MAX frequency that can be used with the device for fast reads */ -+ MV_U32 spiFastRdDummyBytes; /* Number of dumy bytes to read before real data when working in fast read mode. */ -+} MV_SFLASH_DEVICE_PARAMS; -+ -+typedef struct -+{ -+ MV_U32 baseAddr; /* Flash Base Address used in fast mode */ -+ MV_U8 manufacturerId; /* Manufacturer ID */ -+ MV_U16 deviceId; /* Device ID */ -+ MV_U32 sectorSize; /* Size of each sector - all the same */ -+ MV_U32 sectorNumber; /* Number of sectors */ -+ MV_U32 pageSize; /* Page size - affect allignment */ -+ MV_U32 index; /* index of the device in the sflash table (internal parameter) */ -+} MV_SFLASH_INFO; -+ -+/* Function Prototypes */ -+/* Init */ -+MV_STATUS mvSFlashInit (MV_SFLASH_INFO * pFlinfo); -+ -+/* erase */ -+MV_STATUS mvSFlashSectorErase (MV_SFLASH_INFO * pFlinfo, MV_U32 secNumber); -+MV_STATUS mvSFlashChipErase (MV_SFLASH_INFO * pFlinfo); -+ -+/* Read */ -+MV_STATUS mvSFlashBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, -+ MV_U8* pReadBuff, MV_U32 buffSize); -+MV_STATUS mvSFlashFastBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, -+ MV_U8* pReadBuff, MV_U32 buffSize); -+ -+/* write regardless of the page boundaries and size limit per Page program command */ -+MV_STATUS mvSFlashBlockWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, -+ MV_U8* pWriteBuff, MV_U32 buffSize); -+/* Get IDs */ -+MV_STATUS mvSFlashIdGet (MV_SFLASH_INFO * pFlinfo, MV_U8* pManId, MV_U16* pDevId); -+ -+/* Set and Get the Write Protection region - if the Status register is not locked */ -+MV_STATUS mvSFlashWpRegionSet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION wpRegion); -+MV_STATUS mvSFlashWpRegionGet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION * pWpRegion); -+ -+/* Lock the status register for writing - W/Vpp pin should be low to take effect */ -+MV_STATUS mvSFlashStatRegLock (MV_SFLASH_INFO * pFlinfo, MV_BOOL srLock); -+ -+/* Get the regions sizes */ -+MV_U32 mvSFlashSizeGet (MV_SFLASH_INFO * pFlinfo); -+ -+/* Cause the falsh device to go into power save mode */ -+MV_STATUS mvSFlashPowerSaveEnter(MV_SFLASH_INFO * pFlinfo); -+MV_STATUS mvSFlashPowerSaveExit (MV_SFLASH_INFO * pFlinfo); -+ -+/* Retreive the string with the device manufacturer and model */ -+const MV_8 * mvSFlashModelGet (MV_SFLASH_INFO * pFlinfo); -+ -+#endif /* __INCmvSFlashH */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlashSpec.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlashSpec.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlashSpec.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlashSpec.h 2010-11-09 20:28:11.981246772 +0100 -@@ -0,0 +1,233 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvSFlashSpecH -+#define __INCmvSFlashSpecH -+ -+/* Constants */ -+#define MV_SFLASH_READ_CMND_LENGTH 4 /* 1B opcode + 3B address */ -+#define MV_SFLASH_SE_CMND_LENGTH 4 /* 1B opcode + 3B address */ -+#define MV_SFLASH_BE_CMND_LENGTH 1 /* 1B opcode */ -+#define MV_SFLASH_PP_CMND_LENGTH 4 /* 1B opcode + 3B address */ -+#define MV_SFLASH_WREN_CMND_LENGTH 1 /* 1B opcode */ -+#define MV_SFLASH_WRDI_CMND_LENGTH 1 /* 1B opcode */ -+#define MV_SFLASH_RDID_CMND_LENGTH 1 /* 1B opcode */ -+#define MV_SFLASH_RDID_REPLY_LENGTH 3 /* 1B manf ID and 2B device ID */ -+#define MV_SFLASH_RDSR_CMND_LENGTH 1 /* 1B opcode */ -+#define MV_SFLASH_RDSR_REPLY_LENGTH 1 /* 1B status */ -+#define MV_SFLASH_WRSR_CMND_LENGTH 2 /* 1B opcode + 1B status value */ -+#define MV_SFLASH_DP_CMND_LENGTH 1 /* 1B opcode */ -+#define MV_SFLASH_RES_CMND_LENGTH 1 /* 1B opcode */ -+ -+/* Status Register Bit Masks */ -+#define MV_SFLASH_STATUS_REG_WIP_OFFSET 0 /* bit 0; write in progress */ -+#define MV_SFLASH_STATUS_REG_WP_OFFSET 2 /* bit 2-4; write protect option */ -+#define MV_SFLASH_STATUS_REG_SRWD_OFFSET 7 /* bit 7; lock status register write */ -+#define MV_SFLASH_STATUS_REG_WIP_MASK (0x1 << MV_SFLASH_STATUS_REG_WIP_OFFSET) -+#define MV_SFLASH_STATUS_REG_SRWD_MASK (0x1 << MV_SFLASH_STATUS_REG_SRWD_OFFSET) -+ -+#define MV_SFLASH_MAX_WAIT_LOOP 1000000 -+#define MV_SFLASH_CHIP_ERASE_MAX_WAIT_LOOP 0x50000000 -+ -+#define MV_SFLASH_DEFAULT_RDID_OPCD 0x9F /* Default Read ID */ -+#define MV_SFLASH_DEFAULT_WREN_OPCD 0x06 /* Default Write Enable */ -+#define MV_SFLASH_NO_SPECIFIC_OPCD 0x00 -+ -+/********************************/ -+/* ST M25Pxxx Device Specific */ -+/********************************/ -+ -+/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ -+#define MV_M25PXXX_ST_MANF_ID 0x20 -+#define MV_M25P32_DEVICE_ID 0x2016 -+#define MV_M25P32_MAX_SPI_FREQ 20000000 /* 20MHz */ -+#define MV_M25P32_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ -+#define MV_M25P32_FAST_READ_DUMMY_BYTES 1 -+#define MV_M25P64_DEVICE_ID 0x2017 -+#define MV_M25P64_MAX_SPI_FREQ 20000000 /* 20MHz */ -+#define MV_M25P64_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ -+#define MV_M25P64_FAST_READ_DUMMY_BYTES 1 -+#define MV_M25P128_DEVICE_ID 0x2018 -+#define MV_M25P128_MAX_SPI_FREQ 20000000 /* 20MHz */ -+#define MV_M25P128_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ -+#define MV_M25P128_FAST_READ_DUMMY_BYTES 1 -+ -+ -+/* Sector Sizes and population per device model*/ -+#define MV_M25P32_SECTOR_SIZE 0x10000 /* 64K */ -+#define MV_M25P64_SECTOR_SIZE 0x10000 /* 64K */ -+#define MV_M25P128_SECTOR_SIZE 0x40000 /* 256K */ -+#define MV_M25P32_SECTOR_NUMBER 64 -+#define MV_M25P64_SECTOR_NUMBER 128 -+#define MV_M25P128_SECTOR_NUMBER 64 -+#define MV_M25P_PAGE_SIZE 0x100 /* 256 byte */ -+ -+#define MV_M25P_WREN_CMND_OPCD 0x06 /* Write Enable */ -+#define MV_M25P_WRDI_CMND_OPCD 0x04 /* Write Disable */ -+#define MV_M25P_RDID_CMND_OPCD 0x9F /* Read ID */ -+#define MV_M25P_RDSR_CMND_OPCD 0x05 /* Read Status Register */ -+#define MV_M25P_WRSR_CMND_OPCD 0x01 /* Write Status Register */ -+#define MV_M25P_READ_CMND_OPCD 0x03 /* Sequential Read */ -+#define MV_M25P_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ -+#define MV_M25P_PP_CMND_OPCD 0x02 /* Page Program */ -+#define MV_M25P_SE_CMND_OPCD 0xD8 /* Sector Erase */ -+#define MV_M25P_BE_CMND_OPCD 0xC7 /* Bulk Erase */ -+#define MV_M25P_RES_CMND_OPCD 0xAB /* Read Electronic Signature */ -+ -+/* Status Register Write Protect Bit Masks - 3bits */ -+#define MV_M25P_STATUS_REG_WP_MASK (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_M25P_STATUS_BP_NONE (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_M25P_STATUS_BP_1_OF_64 (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_M25P_STATUS_BP_1_OF_32 (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_M25P_STATUS_BP_1_OF_16 (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_M25P_STATUS_BP_1_OF_8 (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_M25P_STATUS_BP_1_OF_4 (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_M25P_STATUS_BP_1_OF_2 (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_M25P_STATUS_BP_ALL (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+ -+/************************************/ -+/* MXIC MX25L6405 Device Specific */ -+/************************************/ -+ -+/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ -+#define MV_MXIC_MANF_ID 0xC2 -+#define MV_MX25L6405_DEVICE_ID 0x2017 -+#define MV_MX25L6405_MAX_SPI_FREQ 20000000 /* 20MHz */ -+#define MV_MX25L6405_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ -+#define MV_MX25L6405_FAST_READ_DUMMY_BYTES 1 -+#define MV_MXIC_DP_EXIT_DELAY 30 /* 30 ms */ -+ -+/* Sector Sizes and population per device model*/ -+#define MV_MX25L6405_SECTOR_SIZE 0x10000 /* 64K */ -+#define MV_MX25L6405_SECTOR_NUMBER 128 -+#define MV_MXIC_PAGE_SIZE 0x100 /* 256 byte */ -+ -+#define MV_MX25L_WREN_CMND_OPCD 0x06 /* Write Enable */ -+#define MV_MX25L_WRDI_CMND_OPCD 0x04 /* Write Disable */ -+#define MV_MX25L_RDID_CMND_OPCD 0x9F /* Read ID */ -+#define MV_MX25L_RDSR_CMND_OPCD 0x05 /* Read Status Register */ -+#define MV_MX25L_WRSR_CMND_OPCD 0x01 /* Write Status Register */ -+#define MV_MX25L_READ_CMND_OPCD 0x03 /* Sequential Read */ -+#define MV_MX25L_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ -+#define MV_MX25L_PP_CMND_OPCD 0x02 /* Page Program */ -+#define MV_MX25L_SE_CMND_OPCD 0xD8 /* Sector Erase */ -+#define MV_MX25L_BE_CMND_OPCD 0xC7 /* Bulk Erase */ -+#define MV_MX25L_DP_CMND_OPCD 0xB9 /* Deep Power Down */ -+#define MV_MX25L_RES_CMND_OPCD 0xAB /* Read Electronic Signature */ -+ -+/* Status Register Write Protect Bit Masks - 4bits */ -+#define MV_MX25L_STATUS_REG_WP_MASK (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_NONE (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_1_OF_128 (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_1_OF_64 (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_1_OF_32 (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_1_OF_16 (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_1_OF_8 (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_1_OF_4 (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_1_OF_2 (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_ALL (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) -+ -+/************************************/ -+/* SPANSION S25FL128P Device Specific */ -+/************************************/ -+ -+/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ -+#define MV_SPANSION_MANF_ID 0x01 -+#define MV_S25FL128_DEVICE_ID 0x2018 -+#define MV_S25FL128_MAX_SPI_FREQ 33000000 /* 33MHz */ -+#define MV_S25FL128_MAX_FAST_SPI_FREQ 104000000 /* 104MHz */ -+#define MV_S25FL128_FAST_READ_DUMMY_BYTES 1 -+ -+/* Sector Sizes and population per device model*/ -+#define MV_S25FL128_SECTOR_SIZE 0x40000 /* 256K */ -+#define MV_S25FL128_SECTOR_NUMBER 64 -+#define MV_S25FL_PAGE_SIZE 0x100 /* 256 byte */ -+ -+#define MV_S25FL_WREN_CMND_OPCD 0x06 /* Write Enable */ -+#define MV_S25FL_WRDI_CMND_OPCD 0x04 /* Write Disable */ -+#define MV_S25FL_RDID_CMND_OPCD 0x9F /* Read ID */ -+#define MV_S25FL_RDSR_CMND_OPCD 0x05 /* Read Status Register */ -+#define MV_S25FL_WRSR_CMND_OPCD 0x01 /* Write Status Register */ -+#define MV_S25FL_READ_CMND_OPCD 0x03 /* Sequential Read */ -+#define MV_S25FL_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ -+#define MV_S25FL_PP_CMND_OPCD 0x02 /* Page Program */ -+#define MV_S25FL_SE_CMND_OPCD 0xD8 /* Sector Erase */ -+#define MV_S25FL_BE_CMND_OPCD 0xC7 /* Bulk Erase */ -+#define MV_S25FL_DP_CMND_OPCD 0xB9 /* Deep Power Down */ -+#define MV_S25FL_RES_CMND_OPCD 0xAB /* Read Electronic Signature */ -+ -+/* Status Register Write Protect Bit Masks - 4bits */ -+#define MV_S25FL_STATUS_REG_WP_MASK (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_NONE (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_1_OF_128 (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_1_OF_64 (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_1_OF_32 (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_1_OF_16 (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_1_OF_8 (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_1_OF_4 (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_1_OF_2 (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_ALL (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) -+ -+#endif /* __INCmvSFlashSpecH */ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.c 2010-11-09 20:28:12.022495595 +0100 -@@ -0,0 +1,576 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "spi/mvSpi.h" -+#include "spi/mvSpiSpec.h" -+ -+#include "ctrlEnv/mvCtrlEnvLib.h" -+ -+/* #define MV_DEBUG */ -+#ifdef MV_DEBUG -+#define DB(x) x -+#define mvOsPrintf printf -+#else -+#define DB(x) -+#endif -+ -+ -+/******************************************************************************* -+* mvSpi16bitDataTxRx - Transmt and receive data -+* -+* DESCRIPTION: -+* Tx data and block waiting for data to be transmitted -+* -+********************************************************************************/ -+static MV_STATUS mvSpi16bitDataTxRx (MV_U16 txData, MV_U16 * pRxData) -+{ -+ MV_U32 i; -+ MV_BOOL ready = MV_FALSE; -+ -+ /* First clear the bit in the interrupt cause register */ -+ MV_REG_WRITE(MV_SPI_INT_CAUSE_REG, 0x0); -+ -+ /* Transmit data */ -+ MV_REG_WRITE(MV_SPI_DATA_OUT_REG, MV_16BIT_LE(txData)); -+ -+ /* wait with timeout for memory ready */ -+ for (i=0; i> 8) & 0xFF); -+ -+#elif defined(MV_CPU_BE) -+ -+ /* perform the data write to the buffer in two stages with 8bit each */ -+ MV_U8 * bptr = (MV_U8 *)pRxData; -+ MV_U16 data = MV_16BIT_LE(MV_REG_READ(MV_SPI_DATA_IN_REG)); -+ *bptr = ((data >> 8) & 0xFF); -+ ++bptr; -+ *bptr = (data & 0xFF); -+ -+#else -+ #error "CPU endianess isn't defined!\n" -+#endif -+ -+ } -+ else -+ *pRxData = MV_16BIT_LE(MV_REG_READ(MV_SPI_DATA_IN_REG)); -+ } -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvSpi8bitDataTxRx - Transmt and receive data (8bits) -+* -+* DESCRIPTION: -+* Tx data and block waiting for data to be transmitted -+* -+********************************************************************************/ -+static MV_STATUS mvSpi8bitDataTxRx (MV_U8 txData, MV_U8 * pRxData) -+{ -+ MV_U32 i; -+ MV_BOOL ready = MV_FALSE; -+ -+ /* First clear the bit in the interrupt cause register */ -+ MV_REG_WRITE(MV_SPI_INT_CAUSE_REG, 0x0); -+ -+ /* Transmit data */ -+ MV_REG_WRITE(MV_SPI_DATA_OUT_REG, txData); -+ -+ /* wait with timeout for memory ready */ -+ for (i=0; i serialBaudRate) -+ continue; -+ -+ /* check for exact fit */ -+ if ((cpuClk / preScale[i]) == serialBaudRate) -+ { -+ bestPrescaleIndx = i; -+ break; -+ } -+ -+ /* check if this is better than the previous one */ -+ if ((serialBaudRate - (cpuClk / preScale[i])) < minBaudOffset) -+ { -+ minBaudOffset = (serialBaudRate - (cpuClk / preScale[i])); -+ bestPrescaleIndx = i; -+ } -+ } -+ -+ if (bestPrescaleIndx > 14) -+ { -+ mvOsPrintf("%s ERROR: SPI baud rate prescale error!\n", __FUNCTION__); -+ return MV_OUT_OF_RANGE; -+ } -+ -+ /* configure the Prescale */ -+ tempReg = MV_REG_READ(MV_SPI_IF_CONFIG_REG); -+ tempReg = ((tempReg & ~MV_SPI_CLK_PRESCALE_MASK) | (bestPrescaleIndx + 0x12)); -+ MV_REG_WRITE(MV_SPI_IF_CONFIG_REG, tempReg); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSpiCsAssert - Assert the Chip Select pin indicating a new transfer -+* -+* DESCRIPTION: -+* Assert The chip select - used to select an external SPI device -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Success or Error code. -+* -+********************************************************************************/ -+MV_VOID mvSpiCsAssert(MV_VOID) -+{ -+ /* For devices in which the SPI is muxed on the MPP with other interfaces*/ -+ mvMPPConfigToSPI(); -+ mvOsUDelay(1); -+ MV_REG_BIT_SET(MV_SPI_IF_CTRL_REG, MV_SPI_CS_ENABLE_MASK); -+} -+ -+/******************************************************************************* -+* mvSpiCsDeassert - DeAssert the Chip Select pin indicating the end of a -+* SPI transfer sequence -+* -+* DESCRIPTION: -+* DeAssert the chip select pin -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Success or Error code. -+* -+********************************************************************************/ -+MV_VOID mvSpiCsDeassert(MV_VOID) -+{ -+ MV_REG_BIT_RESET(MV_SPI_IF_CTRL_REG, MV_SPI_CS_ENABLE_MASK); -+ -+ /* For devices in which the SPI is muxed on the MPP with other interfaces*/ -+ mvMPPConfigToDefault(); -+} -+ -+/******************************************************************************* -+* mvSpiRead - Read a buffer over the SPI interface -+* -+* DESCRIPTION: -+* Receive (read) a buffer over the SPI interface in 16bit chunks. If the -+* buffer size is odd, then the last chunk will be 8bits. Chip select is not -+* handled at this level. -+* -+* INPUT: -+* pRxBuff: Pointer to the buffer to hold the received data -+* buffSize: length of the pRxBuff -+* -+* OUTPUT: -+* pRxBuff: Pointer to the buffer with the received data -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSpiRead (MV_U8* pRxBuff, MV_U32 buffSize) -+{ -+ MV_STATUS ret; -+ MV_U32 bytesLeft = buffSize; -+ MV_U16* rxPtr = (MV_U16*)pRxBuff; -+ -+ /* check for null parameters */ -+ if (pRxBuff == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check that the buffer pointer and the buffer size are 16bit aligned */ -+ if ((((MV_U32)buffSize & 1) == 0) && (((MV_U32)pRxBuff & 1) == 0)) -+ { -+ /* Verify that the SPI mode is in 16bit mode */ -+ MV_REG_BIT_SET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); -+ -+ /* TX/RX as long we have complete 16bit chunks */ -+ while (bytesLeft >= MV_SPI_16_BIT_CHUNK_SIZE) -+ { -+ /* Transmitted and wait for the transfer to be completed */ -+ if ((ret = mvSpi16bitDataTxRx(MV_SPI_DUMMY_WRITE_16BITS, rxPtr)) != MV_OK) -+ return ret; -+ -+ /* increment the pointers */ -+ rxPtr++; -+ bytesLeft -= MV_SPI_16_BIT_CHUNK_SIZE; -+ } -+ -+ } -+ else -+ { -+ /* Verify that the SPI mode is in 8bit mode */ -+ MV_REG_BIT_RESET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); -+ -+ /* TX/RX in 8bit chanks */ -+ while (bytesLeft > 0) -+ { -+ /* Transmitted and wait for the transfer to be completed */ -+ if ((ret = mvSpi8bitDataTxRx(MV_SPI_DUMMY_WRITE_8BITS, pRxBuff)) != MV_OK) -+ return ret; -+ /* increment the pointers */ -+ pRxBuff++; -+ bytesLeft--; -+ } -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSpiWrite - Transmit a buffer over the SPI interface -+* -+* DESCRIPTION: -+* Transmit a buffer over the SPI interface in 16bit chunks. If the -+* buffer size is odd, then the last chunk will be 8bits. No chip select -+* action is taken. -+* -+* INPUT: -+* pTxBuff: Pointer to the buffer holding the TX data -+* buffSize: length of the pTxBuff -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSpiWrite(MV_U8* pTxBuff, MV_U32 buffSize) -+{ -+ MV_STATUS ret; -+ MV_U32 bytesLeft = buffSize; -+ MV_U16* txPtr = (MV_U16*)pTxBuff; -+ -+ /* check for null parameters */ -+ if (pTxBuff == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check that the buffer pointer and the buffer size are 16bit aligned */ -+ if ((((MV_U32)buffSize & 1) == 0) && (((MV_U32)pTxBuff & 1) == 0)) -+ { -+ /* Verify that the SPI mode is in 16bit mode */ -+ MV_REG_BIT_SET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); -+ -+ /* TX/RX as long we have complete 16bit chunks */ -+ while (bytesLeft >= MV_SPI_16_BIT_CHUNK_SIZE) -+ { -+ /* Transmitted and wait for the transfer to be completed */ -+ if ((ret = mvSpi16bitDataTxRx(*txPtr, NULL)) != MV_OK) -+ return ret; -+ -+ /* increment the pointers */ -+ txPtr++; -+ bytesLeft -= MV_SPI_16_BIT_CHUNK_SIZE; -+ } -+ } -+ else -+ { -+ -+ /* Verify that the SPI mode is in 8bit mode */ -+ MV_REG_BIT_RESET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); -+ -+ /* TX/RX in 8bit chanks */ -+ while (bytesLeft > 0) -+ { -+ /* Transmitted and wait for the transfer to be completed */ -+ if ((ret = mvSpi8bitDataTxRx(*pTxBuff, NULL)) != MV_OK) -+ return ret; -+ -+ /* increment the pointers */ -+ pTxBuff++; -+ bytesLeft--; -+ } -+ } -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvSpiReadWrite - Read and Write a buffer simultanuosely -+* -+* DESCRIPTION: -+* Transmit and receive a buffer over the SPI in 16bit chunks. If the -+* buffer size is odd, then the last chunk will be 8bits. The SPI chip -+* select is not handled implicitely. -+* -+* INPUT: -+* pRxBuff: Pointer to the buffer to write the RX info in -+* pTxBuff: Pointer to the buffer holding the TX info -+* buffSize: length of both the pTxBuff and pRxBuff -+* -+* OUTPUT: -+* pRxBuff: Pointer of the buffer holding the RX data -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSpiReadWrite(MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize) -+{ -+ MV_STATUS ret; -+ MV_U32 bytesLeft = buffSize; -+ MV_U16* txPtr = (MV_U16*)pTxBuff; -+ MV_U16* rxPtr = (MV_U16*)pRxBuff; -+ -+ /* check for null parameters */ -+ if ((pRxBuff == NULL) || (pTxBuff == NULL)) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check that the buffer pointer and the buffer size are 16bit aligned */ -+ if ((((MV_U32)buffSize & 1) == 0) && (((MV_U32)pTxBuff & 1) == 0) && (((MV_U32)pRxBuff & 1) == 0)) -+ { -+ /* Verify that the SPI mode is in 16bit mode */ -+ MV_REG_BIT_SET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); -+ -+ /* TX/RX as long we have complete 16bit chunks */ -+ while (bytesLeft >= MV_SPI_16_BIT_CHUNK_SIZE) -+ { -+ /* Transmitted and wait for the transfer to be completed */ -+ if ((ret = mvSpi16bitDataTxRx(*txPtr, rxPtr)) != MV_OK) -+ return ret; -+ -+ /* increment the pointers */ -+ txPtr++; -+ rxPtr++; -+ bytesLeft -= MV_SPI_16_BIT_CHUNK_SIZE; -+ } -+ } -+ else -+ { -+ /* Verify that the SPI mode is in 8bit mode */ -+ MV_REG_BIT_RESET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); -+ -+ /* TX/RX in 8bit chanks */ -+ while (bytesLeft > 0) -+ { -+ /* Transmitted and wait for the transfer to be completed */ -+ if ( (ret = mvSpi8bitDataTxRx(*pTxBuff, pRxBuff) ) != MV_OK) -+ return ret; -+ pRxBuff++; -+ pTxBuff++; -+ bytesLeft--; -+ } -+ } -+ -+ return MV_OK; -+} -+ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.c 2010-11-09 20:28:12.052495353 +0100 -@@ -0,0 +1,249 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "spi/mvSpi.h" -+#include "spi/mvSpiSpec.h" -+ -+/*#define MV_DEBUG*/ -+#ifdef MV_DEBUG -+#define DB(x) x -+#else -+#define DB(x) -+#endif -+ -+ -+/******************************************************************************* -+* mvSpiReadAndWrite - Read and Write a buffer simultanuousely -+* -+* DESCRIPTION: -+* Transmit and receive a buffer over the SPI in 16bit chunks. If the -+* buffer size is odd, then the last chunk will be 8bits. -+* -+* INPUT: -+* pRxBuff: Pointer to the buffer to write the RX info in -+* pTxBuff: Pointer to the buffer holding the TX info -+* buffSize: length of both the pTxBuff and pRxBuff -+* -+* OUTPUT: -+* pRxBuff: Pointer of the buffer holding the RX data -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSpiReadAndWrite(MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize) -+{ -+ MV_STATUS ret; -+ -+ /* check for null parameters */ -+ if ((pRxBuff == NULL) || (pTxBuff == NULL) || (buffSize == 0)) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* First assert the chip select */ -+ mvSpiCsAssert(); -+ -+ ret = mvSpiReadWrite(pRxBuff, pTxBuff, buffSize); -+ -+ /* Finally deassert the chip select */ -+ mvSpiCsDeassert(); -+ -+ return ret; -+} -+ -+/******************************************************************************* -+* mvSpiWriteThenWrite - Serialize a command followed by the data over the TX line -+* -+* DESCRIPTION: -+* Assert the chip select line. Transmit the command buffer followed by -+* the data buffer. Then deassert the CS line. -+* -+* INPUT: -+* pCmndBuff: Pointer to the command buffer to transmit -+* cmndSize: length of the command size -+* pTxDataBuff: Pointer to the data buffer to transmit -+* txDataSize: length of the data buffer -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSpiWriteThenWrite (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pTxDataBuff, -+ MV_U32 txDataSize) -+{ -+ MV_STATUS ret = MV_OK, tempRet; -+ -+ /* check for null parameters */ -+#ifndef CONFIG_MARVELL -+ if(NULL == pTxDataBuff) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+#endif -+ -+ if (pCmndBuff == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* First assert the chip select */ -+ mvSpiCsAssert(); -+ -+ /* first write the command */ -+ if ((cmndSize) && (pCmndBuff != NULL)) -+ { -+ if ((tempRet = mvSpiWrite(pCmndBuff, cmndSize)) != MV_OK) -+ ret = tempRet; -+ } -+ -+ /* Then write the data buffer */ -+#ifndef CONFIG_MARVELL -+ if (txDataSize) -+#else -+ if ((txDataSize) && (pTxDataBuff != NULL)) -+#endif -+ { -+ if ((tempRet = mvSpiWrite(pTxDataBuff, txDataSize)) != MV_OK) -+ ret = tempRet; -+ } -+ -+ /* Finally deassert the chip select */ -+ mvSpiCsDeassert(); -+ -+ return ret; -+} -+ -+/******************************************************************************* -+* mvSpiWriteThenRead - Serialize a command then read a data buffer -+* -+* DESCRIPTION: -+* Assert the chip select line. Transmit the command buffer then read -+* the data buffer. Then deassert the CS line. -+* -+* INPUT: -+* pCmndBuff: Pointer to the command buffer to transmit -+* cmndSize: length of the command size -+* pRxDataBuff: Pointer to the buffer to read the data in -+* txDataSize: length of the data buffer -+* -+* OUTPUT: -+* pRxDataBuff: Pointer to the buffer holding the data -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSpiWriteThenRead (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pRxDataBuff, -+ MV_U32 rxDataSize,MV_U32 dummyBytesToRead) -+{ -+ MV_STATUS ret = MV_OK, tempRet; -+ MV_U8 dummyByte; -+ -+ /* check for null parameters */ -+ if ((pCmndBuff == NULL) && (pRxDataBuff == NULL)) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* First assert the chip select */ -+ mvSpiCsAssert(); -+ -+ /* first write the command */ -+ if ((cmndSize) && (pCmndBuff != NULL)) -+ { -+ if ((tempRet = mvSpiWrite(pCmndBuff, cmndSize)) != MV_OK) -+ ret = tempRet; -+ } -+ -+ /* Read dummy bytes before real data. */ -+ while(dummyBytesToRead) -+ { -+ mvSpiRead(&dummyByte,1); -+ dummyBytesToRead--; -+ } -+ -+ /* Then write the data buffer */ -+ if ((rxDataSize) && (pRxDataBuff != NULL)) -+ { -+ if ((tempRet = mvSpiRead(pRxDataBuff, rxDataSize)) != MV_OK) -+ ret = tempRet; -+ } -+ -+ /* Finally deassert the chip select */ -+ mvSpiCsDeassert(); -+ -+ return ret; -+} -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.h 2010-11-09 20:28:12.082495364 +0100 -@@ -0,0 +1,82 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvSpiCmndhH -+#define __INCmvSpiCmndhH -+ -+#include "mvTypes.h" -+ -+/* Function Prototypes */ -+ -+/* Simultanuous Read and write */ -+MV_STATUS mvSpiReadAndWrite (MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize); -+ -+/* write command - write a command and then write data */ -+MV_STATUS mvSpiWriteThenWrite (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pTxDataBuff, MV_U32 txDataSize); -+ -+/* read command - write a command and then read data by writing dummy data */ -+MV_STATUS mvSpiWriteThenRead (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pRxDataBuff, -+ MV_U32 rxDataSize,MV_U32 dummyBytesToRead); -+ -+#endif /* __INCmvSpiCmndhH */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.h 2010-11-09 20:28:12.121243940 +0100 -@@ -0,0 +1,94 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvSpihH -+#define __INCmvSpihH -+ -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+ -+/* Function Prototypes */ -+/* Init */ -+MV_STATUS mvSpiInit (MV_U32 serialBaudRate); -+ -+/* Set the Frequency of the Spi clock */ -+MV_STATUS mvSpiBaudRateSet(MV_U32 serialBaudRate); -+ -+/* Assert the SPI chip select */ -+MV_VOID mvSpiCsAssert (MV_VOID); -+ -+/* De-assert the SPI chip select */ -+MV_VOID mvSpiCsDeassert (MV_VOID); -+ -+/* Simultanuous Read and write */ -+MV_STATUS mvSpiReadWrite (MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize); -+ -+/* serialize a buffer on the TX line - Rx is ignored */ -+MV_STATUS mvSpiWrite (MV_U8* pTxBuff, MV_U32 buffSize); -+ -+/* read from the RX line by writing dummy values to the TX line */ -+MV_STATUS mvSpiRead (MV_U8* pRxBuff, MV_U32 buffSize); -+ -+#endif /* __INCmvSpihH */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiSpec.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiSpec.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiSpec.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiSpec.h 2010-11-09 20:28:12.162495430 +0100 -@@ -0,0 +1,98 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvSpiSpecH -+#define __INCmvSpiSpecH -+ -+/* Constants */ -+#define MV_SPI_WAIT_RDY_MAX_LOOP 100000 -+#define MV_SPI_16_BIT_CHUNK_SIZE 2 -+#define MV_SPI_DUMMY_WRITE_16BITS 0xFFFF -+#define MV_SPI_DUMMY_WRITE_8BITS 0xFF -+ -+/* Marvell Flash Device Controller Registers */ -+#define MV_SPI_CTRLR_OFST 0x10600 -+#define MV_SPI_IF_CTRL_REG (MV_SPI_CTRLR_OFST + 0x00) -+#define MV_SPI_IF_CONFIG_REG (MV_SPI_CTRLR_OFST + 0x04) -+#define MV_SPI_DATA_OUT_REG (MV_SPI_CTRLR_OFST + 0x08) -+#define MV_SPI_DATA_IN_REG (MV_SPI_CTRLR_OFST + 0x0c) -+#define MV_SPI_INT_CAUSE_REG (MV_SPI_CTRLR_OFST + 0x10) -+#define MV_SPI_INT_CAUSE_MASK_REG (MV_SPI_CTRLR_OFST + 0x14) -+ -+/* Serial Memory Interface Control Register Masks */ -+#define MV_SPI_CS_ENABLE_OFFSET 0 /* bit 0 */ -+#define MV_SPI_MEMORY_READY_OFFSET 1 /* bit 1 */ -+#define MV_SPI_CS_ENABLE_MASK (0x1 << MV_SPI_CS_ENABLE_OFFSET) -+#define MV_SPI_MEMORY_READY_MASK (0x1 << MV_SPI_MEMORY_READY_OFFSET) -+ -+/* Serial Memory Interface Configuration Register Masks */ -+#define MV_SPI_CLK_PRESCALE_OFFSET 0 /* bit 0-4 */ -+#define MV_SPI_BYTE_LENGTH_OFFSET 5 /* bit 5 */ -+#define MV_SPI_ADDRESS_BURST_LENGTH_OFFSET 8 /* bit 8-9 */ -+#define MV_SPI_CLK_PRESCALE_MASK (0x1F << MV_SPI_CLK_PRESCALE_OFFSET) -+#define MV_SPI_BYTE_LENGTH_MASK (0x1 << MV_SPI_BYTE_LENGTH_OFFSET) -+#define MV_SPI_ADDRESS_BURST_LENGTH_MASK (0x3 << MV_SPI_ADDRESS_BURST_LENGTH_OFFSET) -+ -+#endif /* __INCmvSpiSpecH */ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.c 2010-11-09 20:28:12.192495512 +0100 -@@ -0,0 +1,1023 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#include "mvTwsi.h" -+#include "mvTwsiSpec.h" -+#include "cpu/mvCpu.h" -+ -+ -+/*#define MV_DEBUG*/ -+#ifdef MV_DEBUG -+#define DB(x) x -+#else -+#define DB(x) -+#endif -+ -+static MV_VOID twsiIntFlgClr(MV_U8 chanNum); -+static MV_BOOL twsiMainIntGet(MV_U8 chanNum); -+static MV_VOID twsiAckBitSet(MV_U8 chanNum); -+static MV_U32 twsiStsGet(MV_U8 chanNum); -+static MV_VOID twsiReset(MV_U8 chanNum); -+static MV_STATUS twsiAddr7BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command); -+static MV_STATUS twsiAddr10BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command); -+static MV_STATUS twsiDataTransmit(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize); -+static MV_STATUS twsiDataReceive(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize); -+static MV_STATUS twsiTargetOffsSet(MV_U8 chanNum, MV_U32 offset,MV_BOOL moreThen256); -+ -+ -+static MV_BOOL twsiTimeoutChk(MV_U32 timeout, const MV_8 *pString) -+{ -+ if(timeout >= TWSI_TIMEOUT_VALUE) -+ { -+ DB(mvOsPrintf("%s",pString)); -+ return MV_TRUE; -+ } -+ return MV_FALSE; -+ -+} -+/******************************************************************************* -+* mvTwsiStartBitSet - Set start bit on the bus -+* -+* DESCRIPTION: -+* This routine sets the start bit on the TWSI bus. -+* The routine first checks for interrupt flag condition, then it sets -+* the start bit in the TWSI Control register. -+* If the interrupt flag condition check previously was set, the function -+* will clear it. -+* The function then wait for the start bit to be cleared by the HW. -+* Then it waits for the interrupt flag to be set and eventually, the -+* TWSI status is checked to be 0x8 or 0x10(repeated start bit). -+* -+* INPUT: -+* chanNum - TWSI channel. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK is start bit was set successfuly on the bus. -+* MV_FAIL if interrupt flag was set before setting start bit. -+* -+*******************************************************************************/ -+MV_STATUS mvTwsiStartBitSet(MV_U8 chanNum) -+{ -+ MV_BOOL isIntFlag = MV_FALSE; -+ MV_U32 timeout, temp; -+ -+ DB(mvOsPrintf("TWSI: mvTwsiStartBitSet \n")); -+ /* check Int flag */ -+ if(twsiMainIntGet(chanNum)) -+ isIntFlag = MV_TRUE; -+ /* set start Bit */ -+ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); -+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp | TWSI_CONTROL_START_BIT); -+ -+ /* in case that the int flag was set before i.e. repeated start bit */ -+ if(isIntFlag){ -+ DB(mvOsPrintf("TWSI: mvTwsiStartBitSet repeated start Bit\n")); -+ twsiIntFlgClr(chanNum); -+ } -+ -+ /* wait for interrupt */ -+ timeout = 0; -+ while(!twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: mvTwsiStartBitSet ERROR - Start Clear bit TimeOut .\n")) -+ return MV_TIMEOUT; -+ -+ -+ /* check that start bit went down */ -+ if((MV_REG_READ(TWSI_CONTROL_REG(chanNum)) & TWSI_CONTROL_START_BIT) != 0) -+ { -+ mvOsPrintf("TWSI: mvTwsiStartBitSet ERROR - start bit didn't went down\n"); -+ return MV_FAIL; -+ } -+ -+ /* check the status */ -+ temp = twsiStsGet(chanNum); -+ if(( temp != TWSI_START_CON_TRA ) && ( temp != TWSI_REPEATED_START_CON_TRA )) -+ { -+ mvOsPrintf("TWSI: mvTwsiStartBitSet ERROR - status %x after Set Start Bit. \n",temp); -+ return MV_FAIL; -+ } -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvTwsiStopBitSet - Set stop bit on the bus -+* -+* DESCRIPTION: -+* This routine set the stop bit on the TWSI bus. -+* The function then wait for the stop bit to be cleared by the HW. -+* Finally the function checks for status of 0xF8. -+* -+* INPUT: -+* chanNum - TWSI channel -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE is stop bit was set successfuly on the bus. -+* -+*******************************************************************************/ -+MV_STATUS mvTwsiStopBitSet(MV_U8 chanNum) -+{ -+ MV_U32 timeout, temp; -+ -+ /* Generate stop bit */ -+ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); -+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp | TWSI_CONTROL_STOP_BIT); -+ -+ twsiIntFlgClr(chanNum); -+ -+ /* wait for stop bit to come down */ -+ timeout = 0; -+ while( ((MV_REG_READ(TWSI_CONTROL_REG(chanNum)) & TWSI_CONTROL_STOP_BIT) != 0) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: mvTwsiStopBitSet ERROR - Stop bit TimeOut .\n")) -+ return MV_TIMEOUT; -+ -+ /* check that the stop bit went down */ -+ if((MV_REG_READ(TWSI_CONTROL_REG(chanNum)) & TWSI_CONTROL_STOP_BIT) != 0) -+ { -+ mvOsPrintf("TWSI: mvTwsiStopBitSet ERROR - stop bit didn't went down. \n"); -+ return MV_FAIL; -+ } -+ -+ /* check the status */ -+ temp = twsiStsGet(chanNum); -+ if( temp != TWSI_NO_REL_STS_INT_FLAG_IS_KEPT_0){ -+ mvOsPrintf("TWSI: mvTwsiStopBitSet ERROR - status %x after Stop Bit. \n", temp); -+ return MV_FAIL; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* twsiMainIntGet - Get twsi bit from main Interrupt cause. -+* -+* DESCRIPTION: -+* This routine returns the twsi interrupt flag value. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE is interrupt flag is set, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+static MV_BOOL twsiMainIntGet(MV_U8 chanNum) -+{ -+ MV_U32 temp; -+ -+ /* get the int flag bit */ -+ -+ temp = MV_REG_READ(TWSI_CPU_MAIN_INT_CAUSE_REG); -+ if (temp & (TWSI0_CPU_MAIN_INT_BIT << chanNum)) -+ return MV_TRUE; -+ -+ return MV_FALSE; -+} -+/******************************************************************************* -+* twsiIntFlgClr - Clear Interrupt flag. -+* -+* DESCRIPTION: -+* This routine clears the interrupt flag. It does NOT poll the interrupt -+* to make sure the clear. After clearing the interrupt, it waits for at -+* least 1 miliseconds. -+* -+* INPUT: -+* chanNum - TWSI channel -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+static MV_VOID twsiIntFlgClr(MV_U8 chanNum) -+{ -+ MV_U32 temp; -+ -+ /* wait for 1 mili to prevent TWSI register write after write problems */ -+ mvOsDelay(1); -+ /* clear the int flag bit */ -+ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); -+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum),temp & ~(TWSI_CONTROL_INT_FLAG_SET)); -+ -+ /* wait for 1 mili sec for the clear to take effect */ -+ mvOsDelay(1); -+ -+ return; -+} -+ -+ -+/******************************************************************************* -+* twsiAckBitSet - Set acknowledge bit on the bus -+* -+* DESCRIPTION: -+* This routine set the acknowledge bit on the TWSI bus. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+static MV_VOID twsiAckBitSet(MV_U8 chanNum) -+{ -+ MV_U32 temp; -+ -+ /*Set the Ack bit */ -+ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); -+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp | TWSI_CONTROL_ACK); -+ -+ /* Add delay of 1ms */ -+ mvOsDelay(1); -+ return; -+} -+ -+ -+/******************************************************************************* -+* twsiInit - Initialize TWSI interface -+* -+* DESCRIPTION: -+* This routine: -+* -Reset the TWSI. -+* -Initialize the TWSI clock baud rate according to given frequancy -+* parameter based on Tclk frequancy and enables TWSI slave. -+* -Set the ack bit. -+* -Assign the TWSI slave address according to the TWSI address Type. -+* -+* -+* INPUT: -+* chanNum - TWSI channel -+* frequancy - TWSI frequancy in KHz. (up to 100KHZ) -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Actual frequancy. -+* -+*******************************************************************************/ -+MV_U32 mvTwsiInit(MV_U8 chanNum, MV_HZ frequancy, MV_U32 Tclk, MV_TWSI_ADDR *pTwsiAddr, MV_BOOL generalCallEnable) -+{ -+ MV_U32 n,m,freq,margin,minMargin = 0xffffffff; -+ MV_U32 power; -+ MV_U32 actualFreq = 0,actualN = 0,actualM = 0,val; -+ -+ if(frequancy > 100000) -+ { -+ mvOsPrintf("Warning TWSI frequancy is too high, please use up tp 100Khz. \n"); -+ } -+ -+ DB(mvOsPrintf("TWSI: mvTwsiInit - Tclk = %d freq = %d\n",Tclk,frequancy)); -+ /* Calucalte N and M for the TWSI clock baud rate */ -+ for(n = 0 ; n < 8 ; n++) -+ { -+ for(m = 0 ; m < 16 ; m++) -+ { -+ power = 2 << n; /* power = 2^(n+1) */ -+ freq = Tclk/(10*(m+1)*power); -+ margin = MV_ABS(frequancy - freq); -+ if(margin < minMargin) -+ { -+ minMargin = margin; -+ actualFreq = freq; -+ actualN = n; -+ actualM = m; -+ } -+ } -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiInit - actN %d actM %d actFreq %d\n",actualN , actualM, actualFreq)); -+ /* Reset the TWSI logic */ -+ twsiReset(chanNum); -+ -+ /* Set the baud rate */ -+ val = ((actualM<< TWSI_BAUD_RATE_M_OFFS) | actualN << TWSI_BAUD_RATE_N_OFFS); -+ MV_REG_WRITE(TWSI_STATUS_BAUDE_RATE_REG(chanNum),val); -+ -+ /* Enable the TWSI and slave */ -+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), TWSI_CONTROL_ENA | TWSI_CONTROL_ACK); -+ -+ /* set the TWSI slave address */ -+ if( pTwsiAddr->type == ADDR10_BIT )/* 10 Bit deviceAddress */ -+ { -+ /* writing the 2 most significant bits of the 10 bit address*/ -+ val = ((pTwsiAddr->address & TWSI_SLAVE_ADDR_10BIT_MASK) >> TWSI_SLAVE_ADDR_10BIT_OFFS ); -+ /* bits 7:3 must be 0x11110 */ -+ val |= TWSI_SLAVE_ADDR_10BIT_CONST; -+ /* set GCE bit */ -+ if(generalCallEnable) -+ val |= TWSI_SLAVE_ADDR_GCE_ENA; -+ /* write slave address */ -+ MV_REG_WRITE(TWSI_SLAVE_ADDR_REG(chanNum),val); -+ -+ /* writing the 8 least significant bits of the 10 bit address*/ -+ val = (pTwsiAddr->address << TWSI_EXTENDED_SLAVE_OFFS) & TWSI_EXTENDED_SLAVE_MASK; -+ MV_REG_WRITE(TWSI_EXTENDED_SLAVE_ADDR_REG(chanNum), val); -+ } -+ else /*7 bit address*/ -+ { -+ /* set the 7 Bits address */ -+ MV_REG_WRITE(TWSI_EXTENDED_SLAVE_ADDR_REG(chanNum),0x0); -+ val = (pTwsiAddr->address << TWSI_SLAVE_ADDR_7BIT_OFFS) & TWSI_SLAVE_ADDR_7BIT_MASK; -+ MV_REG_WRITE(TWSI_SLAVE_ADDR_REG(chanNum), val); -+ } -+ -+ /* unmask twsi int */ -+ val = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); -+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), val | TWSI_CONTROL_INT_ENA); -+ /* Add delay of 1ms */ -+ mvOsDelay(1); -+ -+ return actualFreq; -+} -+ -+ -+/******************************************************************************* -+* twsiStsGet - Get the TWSI status value. -+* -+* DESCRIPTION: -+* This routine returns the TWSI status value. -+* -+* INPUT: -+* chanNum - TWSI channel -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_U32 - the TWSI status. -+* -+*******************************************************************************/ -+static MV_U32 twsiStsGet(MV_U8 chanNum) -+{ -+ return MV_REG_READ(TWSI_STATUS_BAUDE_RATE_REG(chanNum)); -+ -+} -+ -+/******************************************************************************* -+* twsiReset - Reset the TWSI. -+* -+* DESCRIPTION: -+* Resets the TWSI logic and sets all TWSI registers to their reset values. -+* -+* INPUT: -+* chanNum - TWSI channel -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None -+* -+*******************************************************************************/ -+static MV_VOID twsiReset(MV_U8 chanNum) -+{ -+ /* Reset the TWSI logic */ -+ MV_REG_WRITE(TWSI_SOFT_RESET_REG(chanNum),0); -+ -+ /* wait for 2 mili sec */ -+ mvOsDelay(2); -+ -+ return; -+} -+ -+ -+ -+ -+/******************************* POLICY ****************************************/ -+ -+ -+ -+/******************************************************************************* -+* mvTwsiAddrSet - Set address on TWSI bus. -+* -+* DESCRIPTION: -+* This function Set address (7 or 10 Bit address) on the Twsi Bus. -+* -+* INPUT: -+* chanNum - TWSI channel -+* pTwsiAddr - twsi address. -+* command - read / write . -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK - if setting the address completed succesfully. -+* MV_FAIL otherwmise. -+* -+*******************************************************************************/ -+MV_STATUS mvTwsiAddrSet(MV_U8 chanNum, MV_TWSI_ADDR *pTwsiAddr, MV_TWSI_CMD command) -+{ -+ DB(mvOsPrintf("TWSI: mvTwsiAddr7BitSet addr %x , type %d, cmd is %s\n",pTwsiAddr->address,\ -+ pTwsiAddr->type, ((command==MV_TWSI_WRITE)?"Write":"Read") )); -+ /* 10 Bit address */ -+ if(pTwsiAddr->type == ADDR10_BIT) -+ { -+ return twsiAddr10BitSet(chanNum, pTwsiAddr->address,command); -+ } -+ /* 7 Bit address */ -+ else -+ { -+ return twsiAddr7BitSet(chanNum, pTwsiAddr->address,command); -+ } -+ -+} -+ -+/******************************************************************************* -+* twsiAddr10BitSet - Set 10 Bit address on TWSI bus. -+* -+* DESCRIPTION: -+* There are two address phases: -+* 1) Write '11110' to data register bits [7:3] and 10-bit address MSB -+* (bits [9:8]) to data register bits [2:1] plus a write(0) or read(1) bit -+* to the Data register. Then it clears interrupt flag which drive -+* the address on the TWSI bus. The function then waits for interrupt -+* flag to be active and status 0x18 (write) or 0x40 (read) to be set. -+* 2) write the rest of 10-bit address to data register and clears -+* interrupt flag which drive the address on the TWSI bus. The -+* function then waits for interrupt flag to be active and status -+* 0xD0 (write) or 0xE0 (read) to be set. -+* -+* INPUT: -+* chanNum - TWSI channel -+* deviceAddress - twsi address. -+* command - read / write . -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK - if setting the address completed succesfully. -+* MV_FAIL otherwmise. -+* -+*******************************************************************************/ -+static MV_STATUS twsiAddr10BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command) -+{ -+ MV_U32 val,timeout; -+ -+ /* writing the 2 most significant bits of the 10 bit address*/ -+ val = ((deviceAddress & TWSI_DATA_ADDR_10BIT_MASK) >> TWSI_DATA_ADDR_10BIT_OFFS ); -+ /* bits 7:3 must be 0x11110 */ -+ val |= TWSI_DATA_ADDR_10BIT_CONST; -+ /* set command */ -+ val |= command; -+ MV_REG_WRITE(TWSI_DATA_REG(chanNum), val); -+ /* WA add a delay */ -+ mvOsDelay(1); -+ -+ /* clear Int flag */ -+ twsiIntFlgClr(chanNum); -+ -+ /* wait for Int to be Set */ -+ timeout = 0; -+ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiAddr10BitSet ERROR - 1st addr (10Bit) Int TimeOut.\n")) -+ return MV_TIMEOUT; -+ -+ /* check the status */ -+ val = twsiStsGet(chanNum); -+ if(( (val != TWSI_AD_PLS_RD_BIT_TRA_ACK_REC) && (command == MV_TWSI_READ ) ) || -+ ( (val != TWSI_AD_PLS_WR_BIT_TRA_ACK_REC) && (command == MV_TWSI_WRITE) )) -+ { -+ mvOsPrintf("TWSI: twsiAddr10BitSet ERROR - status %x 1st addr (10 Bit) in %s mode.\n"\ -+ ,val, ((command==MV_TWSI_WRITE)?"Write":"Read") ); -+ return MV_FAIL; -+ } -+ -+ /* set 8 LSB of the address */ -+ val = (deviceAddress << TWSI_DATA_ADDR_7BIT_OFFS) & TWSI_DATA_ADDR_7BIT_MASK; -+ MV_REG_WRITE(TWSI_DATA_REG(chanNum), val); -+ -+ /* clear Int flag */ -+ twsiIntFlgClr(chanNum); -+ -+ /* wait for Int to be Set */ -+ timeout = 0; -+ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiAddr10BitSet ERROR - 2nd (10 Bit) Int TimOut.\n")) -+ return MV_TIMEOUT; -+ -+ /* check the status */ -+ val = twsiStsGet(chanNum); -+ if(( (val != TWSI_SEC_AD_PLS_RD_BIT_TRA_ACK_REC) && (command == MV_TWSI_READ ) ) || -+ ( (val != TWSI_SEC_AD_PLS_WR_BIT_TRA_ACK_REC) && (command == MV_TWSI_WRITE) )) -+ { -+ mvOsPrintf("TWSI: twsiAddr10BitSet ERROR - status %x 2nd addr(10 Bit) in %s mode.\n"\ -+ ,val, ((command==MV_TWSI_WRITE)?"Write":"Read") ); -+ return MV_FAIL; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* twsiAddr7BitSet - Set 7 Bit address on TWSI bus. -+* -+* DESCRIPTION: -+* This function writes 7 bit address plus a write or read bit to the -+* Data register. Then it clears interrupt flag which drive the address on -+* the TWSI bus. The function then waits for interrupt flag to be active -+* and status 0x18 (write) or 0x40 (read) to be set. -+* -+* INPUT: -+* chanNum - TWSI channel -+* deviceAddress - twsi address. -+* command - read / write . -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK - if setting the address completed succesfully. -+* MV_FAIL otherwmise. -+* -+*******************************************************************************/ -+static MV_STATUS twsiAddr7BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command) -+{ -+ MV_U32 val,timeout; -+ -+ /* set the address */ -+ val = (deviceAddress << TWSI_DATA_ADDR_7BIT_OFFS) & TWSI_DATA_ADDR_7BIT_MASK; -+ /* set command */ -+ val |= command; -+ MV_REG_WRITE(TWSI_DATA_REG(chanNum), val); -+ /* WA add a delay */ -+ mvOsDelay(1); -+ -+ /* clear Int flag */ -+ twsiIntFlgClr(chanNum); -+ -+ /* wait for Int to be Set */ -+ timeout = 0; -+ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiAddr7BitSet ERROR - Addr (7 Bit) int TimeOut.\n")) -+ return MV_TIMEOUT; -+ -+ /* check the status */ -+ val = twsiStsGet(chanNum); -+ if(( (val != TWSI_AD_PLS_RD_BIT_TRA_ACK_REC) && (command == MV_TWSI_READ ) ) || -+ ( (val != TWSI_AD_PLS_WR_BIT_TRA_ACK_REC) && (command == MV_TWSI_WRITE) )) -+ { -+ /* only in debug, since in boot we try to read the SPD of both DRAM, and we don't -+ want error messeges in case DIMM doesn't exist. */ -+ DB(mvOsPrintf("TWSI: twsiAddr7BitSet ERROR - status %x addr (7 Bit) in %s mode.\n"\ -+ ,val,((command==MV_TWSI_WRITE)?"Write":"Read") )); -+ return MV_FAIL; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* twsiDataWrite - Trnasmit a data block over TWSI bus. -+* -+* DESCRIPTION: -+* This function writes a given data block to TWSI bus in 8 bit granularity. -+* first The function waits for interrupt flag to be active then -+* For each 8-bit data: -+* The function writes data to data register. It then clears -+* interrupt flag which drives the data on the TWSI bus. -+* The function then waits for interrupt flag to be active and status -+* 0x28 to be set. -+* -+* -+* INPUT: -+* chanNum - TWSI channel -+* pBlock - Data block. -+* blockSize - number of chars in pBlock. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK - if transmiting the block completed succesfully, -+* MV_BAD_PARAM - if pBlock is NULL, -+* MV_FAIL otherwmise. -+* -+*******************************************************************************/ -+static MV_STATUS twsiDataTransmit(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize) -+{ -+ MV_U32 timeout, temp, blockSizeWr = blockSize; -+ -+ if(NULL == pBlock) -+ return MV_BAD_PARAM; -+ -+ /* wait for Int to be Set */ -+ timeout = 0; -+ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataTransmit ERROR - Read Data Int TimeOut.\n")) -+ return MV_TIMEOUT; -+ -+ while(blockSizeWr) -+ { -+ /* write the data*/ -+ MV_REG_WRITE(TWSI_DATA_REG(chanNum),(MV_U32)*pBlock); -+ DB(mvOsPrintf("TWSI: twsiDataTransmit place = %d write %x \n",\ -+ blockSize - blockSizeWr, *pBlock)); -+ pBlock++; -+ blockSizeWr--; -+ -+ twsiIntFlgClr(chanNum); -+ -+ /* wait for Int to be Set */ -+ timeout = 0; -+ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataTransmit ERROR - Read Data Int TimeOut.\n")) -+ return MV_TIMEOUT; -+ -+ /* check the status */ -+ temp = twsiStsGet(chanNum); -+ if(temp != TWSI_M_TRAN_DATA_BYTE_ACK_REC) -+ { -+ mvOsPrintf("TWSI: twsiDataTransmit ERROR - status %x in write trans\n",temp); -+ return MV_FAIL; -+ } -+ -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* twsiDataReceive - Receive data block from TWSI bus. -+* -+* DESCRIPTION: -+* This function receive data block from TWSI bus in 8bit granularity -+* into pBlock buffer. -+* first The function waits for interrupt flag to be active then -+* For each 8-bit data: -+* It clears the interrupt flag which allows the next data to be -+* received from TWSI bus. -+* The function waits for interrupt flag to be active, -+* and status reg is 0x50. -+* Then the function reads data from data register, and copies it to -+* the given buffer. -+* -+* INPUT: -+* chanNum - TWSI channel -+* blockSize - number of bytes to read. -+* -+* OUTPUT: -+* pBlock - Data block. -+* -+* RETURN: -+* MV_OK - if receive transaction completed succesfully, -+* MV_BAD_PARAM - if pBlock is NULL, -+* MV_FAIL otherwmise. -+* -+*******************************************************************************/ -+static MV_STATUS twsiDataReceive(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize) -+{ -+ MV_U32 timeout, temp, blockSizeRd = blockSize; -+ if(NULL == pBlock) -+ return MV_BAD_PARAM; -+ -+ /* wait for Int to be Set */ -+ timeout = 0; -+ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataReceive ERROR - Read Data int Time out .\n")) -+ return MV_TIMEOUT; -+ -+ while(blockSizeRd) -+ { -+ if(blockSizeRd == 1) -+ { -+ /* clear ack and Int flag */ -+ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); -+ temp &= ~(TWSI_CONTROL_ACK); -+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp); -+ } -+ twsiIntFlgClr(chanNum); -+ /* wait for Int to be Set */ -+ timeout = 0; -+ while( (!twsiMainIntGet(chanNum)) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataReceive ERROR - Read Data Int Time out .\n")) -+ return MV_TIMEOUT; -+ -+ /* check the status */ -+ temp = twsiStsGet(chanNum); -+ if((temp != TWSI_M_REC_RD_DATA_ACK_TRA) && (blockSizeRd !=1)) -+ { -+ mvOsPrintf("TWSI: twsiDataReceive ERROR - status %x in read trans \n",temp); -+ return MV_FAIL; -+ } -+ else if((temp != TWSI_M_REC_RD_DATA_ACK_NOT_TRA) && (blockSizeRd ==1)) -+ { -+ mvOsPrintf("TWSI: twsiDataReceive ERROR - status %x in Rd Terminate\n",temp); -+ return MV_FAIL; -+ } -+ -+ /* read the data*/ -+ *pBlock = (MV_U8)MV_REG_READ(TWSI_DATA_REG(chanNum)); -+ DB(mvOsPrintf("TWSI: twsiDataReceive place %d read %x \n",\ -+ blockSize - blockSizeRd,*pBlock)); -+ pBlock++; -+ blockSizeRd--; -+ } -+ -+ return MV_OK; -+} -+ -+ -+ -+/******************************************************************************* -+* twsiTargetOffsSet - Set TWST target offset on TWSI bus. -+* -+* DESCRIPTION: -+* The function support TWSI targets that have inside address space (for -+* example EEPROMs). The function: -+* 1) Convert the given offset into pBlock and size. -+* in case the offset should be set to a TWSI slave which support -+* more then 256 bytes offset, the offset setting will be done -+* in 2 transactions. -+* 2) Use twsiDataTransmit to place those on the bus. -+* -+* INPUT: -+* chanNum - TWSI channel -+* offset - offset to be set on the EEPROM device. -+* moreThen256 - whether the EEPROM device support more then 256 byte offset. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK - if setting the offset completed succesfully. -+* MV_FAIL otherwmise. -+* -+*******************************************************************************/ -+static MV_STATUS twsiTargetOffsSet(MV_U8 chanNum, MV_U32 offset, MV_BOOL moreThen256) -+{ -+ MV_U8 offBlock[2]; -+ MV_U32 offSize; -+ -+ if(moreThen256 == MV_TRUE) -+ { -+ offBlock[0] = (offset >> 8) & 0xff; -+ offBlock[1] = offset & 0xff; -+ offSize = 2; -+ } -+ else -+ { -+ offBlock[0] = offset & 0xff; -+ offSize = 1; -+ } -+ DB(mvOsPrintf("TWSI: twsiTargetOffsSet offSize = %x addr1 = %x addr2 = %x\n",\ -+ offSize,offBlock[0],offBlock[1])); -+ return twsiDataTransmit(chanNum, offBlock, offSize); -+ -+} -+ -+/******************************************************************************* -+* mvTwsiRead - Read data block from a TWSI Slave. -+* -+* DESCRIPTION: -+* The function calls the following functions: -+* -) mvTwsiStartBitSet(); -+* if(EEPROM device) -+* -) mvTwsiAddrSet(w); -+* -) twsiTargetOffsSet(); -+* -) mvTwsiStartBitSet(); -+* -) mvTwsiAddrSet(r); -+* -) twsiDataReceive(); -+* -) mvTwsiStopBitSet(); -+* -+* INPUT: -+* chanNum - TWSI channel -+* pTwsiSlave - Twsi Slave structure. -+* blockSize - number of bytes to read. -+* -+* OUTPUT: -+* pBlock - Data block. -+* -+* RETURN: -+* MV_OK - if EEPROM read transaction completed succesfully, -+* MV_BAD_PARAM - if pBlock is NULL, -+* MV_FAIL otherwmise. -+* -+*******************************************************************************/ -+MV_STATUS mvTwsiRead(MV_U8 chanNum, MV_TWSI_SLAVE *pTwsiSlave, MV_U8 *pBlock, MV_U32 blockSize) -+{ -+ if((NULL == pBlock) || (NULL == pTwsiSlave)) -+ return MV_BAD_PARAM; -+ if(MV_OK != mvTwsiStartBitSet(chanNum)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ -+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiStartBitSet\n")); -+ -+ /* in case offset exsist (i.e. eeprom ) */ -+ if(MV_TRUE == pTwsiSlave->validOffset) -+ { -+ if(MV_OK != mvTwsiAddrSet(chanNum, &(pTwsiSlave->slaveAddr), MV_TWSI_WRITE)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiAddrSet\n")); -+ if(MV_OK != twsiTargetOffsSet(chanNum, pTwsiSlave->offset, pTwsiSlave->moreThen256)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after twsiTargetOffsSet\n")); -+ if(MV_OK != mvTwsiStartBitSet(chanNum)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiStartBitSet\n")); -+ } -+ if(MV_OK != mvTwsiAddrSet(chanNum, &(pTwsiSlave->slaveAddr), MV_TWSI_READ)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiAddrSet\n")); -+ if(MV_OK != twsiDataReceive(chanNum, pBlock, blockSize)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after twsiDataReceive\n")); -+ -+ if(MV_OK != mvTwsiStopBitSet(chanNum)) -+ { -+ return MV_FAIL; -+ } -+ -+ twsiAckBitSet(chanNum); -+ -+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiStopBitSet\n")); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvTwsiWrite - Write data block to a TWSI Slave. -+* -+* DESCRIPTION: -+* The function calls the following functions: -+* -) mvTwsiStartBitSet(); -+* -) mvTwsiAddrSet(); -+* -)if(EEPROM device) -+* -) twsiTargetOffsSet(); -+* -) twsiDataTransmit(); -+* -) mvTwsiStopBitSet(); -+* -+* INPUT: -+* chanNum - TWSI channel -+* eepromAddress - eeprom address. -+* blockSize - number of bytes to write. -+* pBlock - Data block. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* MV_OK - if EEPROM read transaction completed succesfully. -+* MV_BAD_PARAM - if pBlock is NULL, -+* MV_FAIL otherwmise. -+* -+* NOTE: Part of the EEPROM, required that the offset will be aligned to the -+* max write burst supported. -+*******************************************************************************/ -+MV_STATUS mvTwsiWrite(MV_U8 chanNum, MV_TWSI_SLAVE *pTwsiSlave, MV_U8 *pBlock, MV_U32 blockSize) -+{ -+ if((NULL == pBlock) || (NULL == pTwsiSlave)) -+ return MV_BAD_PARAM; -+ -+ if(MV_OK != mvTwsiStartBitSet(chanNum)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ -+ DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after mvTwsiStartBitSet\n")); -+ if(MV_OK != mvTwsiAddrSet(chanNum, &(pTwsiSlave->slaveAddr), MV_TWSI_WRITE)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI :mvTwsiEepromWrite after mvTwsiAddrSet\n")); -+ -+ /* in case offset exsist (i.e. eeprom ) */ -+ if(MV_TRUE == pTwsiSlave->validOffset) -+ { -+ if(MV_OK != twsiTargetOffsSet(chanNum, pTwsiSlave->offset, pTwsiSlave->moreThen256)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after twsiTargetOffsSet\n")); -+ } -+ if(MV_OK != twsiDataTransmit(chanNum, pBlock, blockSize)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after twsiDataTransmit\n")); -+ if(MV_OK != mvTwsiStopBitSet(chanNum)) -+ { -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after mvTwsiStopBitSet\n")); -+ -+ return MV_OK; -+} -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.h 2010-11-09 20:28:12.231824496 +0100 -@@ -0,0 +1,121 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#ifndef __INCmvTwsiH -+#define __INCmvTwsiH -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* need to update this includes */ -+#include "twsi/mvTwsiSpec.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+ -+ -+/* The TWSI interface supports both 7-bit and 10-bit addressing. */ -+/* This enumerator describes addressing type. */ -+typedef enum _mvTwsiAddrType -+{ -+ ADDR7_BIT, /* 7 bit address */ -+ ADDR10_BIT /* 10 bit address */ -+}MV_TWSI_ADDR_TYPE; -+ -+/* This structure describes TWSI address. */ -+typedef struct _mvTwsiAddr -+{ -+ MV_U32 address; /* address */ -+ MV_TWSI_ADDR_TYPE type; /* Address type */ -+}MV_TWSI_ADDR; -+ -+/* This structure describes a TWSI slave. */ -+typedef struct _mvTwsiSlave -+{ -+ MV_TWSI_ADDR slaveAddr; -+ MV_BOOL validOffset; /* whether the slave has offset (i.e. Eeprom etc.) */ -+ MV_U32 offset; /* offset in the slave. */ -+ MV_BOOL moreThen256; /* whether the ofset is bigger then 256 */ -+}MV_TWSI_SLAVE; -+ -+/* This enumerator describes TWSI protocol commands. */ -+typedef enum _mvTwsiCmd -+{ -+ MV_TWSI_WRITE, /* TWSI write command - 0 according to spec */ -+ MV_TWSI_READ /* TWSI read command - 1 according to spec */ -+}MV_TWSI_CMD; -+ -+MV_STATUS mvTwsiStartBitSet(MV_U8 chanNum); -+MV_STATUS mvTwsiStopBitSet(MV_U8 chanNum); -+MV_STATUS mvTwsiAddrSet(MV_U8 chanNum, MV_TWSI_ADDR *twsiAddr, MV_TWSI_CMD command); -+ -+MV_U32 mvTwsiInit(MV_U8 chanNum, MV_KHZ frequancy, MV_U32 Tclk, MV_TWSI_ADDR *twsiAddr, MV_BOOL generalCallEnable); -+MV_STATUS mvTwsiRead (MV_U8 chanNum, MV_TWSI_SLAVE *twsiSlave, MV_U8 *pBlock, MV_U32 blockSize); -+MV_STATUS mvTwsiWrite(MV_U8 chanNum, MV_TWSI_SLAVE *twsiSlave, MV_U8 *pBlock, MV_U32 blockSize); -+ -+ -+#ifdef __cplusplus -+} -+#endif /* __cplusplus */ -+ -+#endif /* __INCmvTwsiH */ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiSpec.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiSpec.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiSpec.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiSpec.h 2010-11-09 20:28:12.272374071 +0100 -@@ -0,0 +1,160 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+/****************************************/ -+/* TWSI Registers */ -+/****************************************/ -+#ifndef __INCmvTwsiSpech -+#define __INCmvTwsiSpech -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* defines */ -+#define TWSI_SLAVE_ADDR_REG(chanNum) (TWSI_SLAVE_BASE(chanNum)+ 0x00) -+ -+#define TWSI_SLAVE_ADDR_GCE_ENA BIT0 -+#define TWSI_SLAVE_ADDR_7BIT_OFFS 0x1 -+#define TWSI_SLAVE_ADDR_7BIT_MASK (0xFF << TWSI_SLAVE_ADDR_7BIT_OFFS) -+#define TWSI_SLAVE_ADDR_10BIT_OFFS 0x7 -+#define TWSI_SLAVE_ADDR_10BIT_MASK 0x300 -+#define TWSI_SLAVE_ADDR_10BIT_CONST 0xF0 -+ -+ -+#define TWSI_EXTENDED_SLAVE_ADDR_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x10) -+#define TWSI_EXTENDED_SLAVE_OFFS 0 -+#define TWSI_EXTENDED_SLAVE_MASK (0xFF << TWSI_EXTENDED_SLAVE_OFFS) -+ -+ -+#define TWSI_DATA_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x04) -+#define TWSI_DATA_COMMAND_OFFS 0x0 -+#define TWSI_DATA_COMMAND_MASK (0x1 << TWSI_DATA_COMMAND_OFFS) -+#define TWSI_DATA_COMMAND_WR (0x1 << TWSI_DATA_COMMAND_OFFS) -+#define TWSI_DATA_COMMAND_RD (0x0 << TWSI_DATA_COMMAND_OFFS) -+#define TWSI_DATA_ADDR_7BIT_OFFS 0x1 -+#define TWSI_DATA_ADDR_7BIT_MASK (0xFF << TWSI_DATA_ADDR_7BIT_OFFS) -+#define TWSI_DATA_ADDR_10BIT_OFFS 0x7 -+#define TWSI_DATA_ADDR_10BIT_MASK 0x300 -+#define TWSI_DATA_ADDR_10BIT_CONST 0xF0 -+ -+ -+#define TWSI_CONTROL_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x08) -+#define TWSI_CONTROL_ACK BIT2 -+#define TWSI_CONTROL_INT_FLAG_SET BIT3 -+#define TWSI_CONTROL_STOP_BIT BIT4 -+#define TWSI_CONTROL_START_BIT BIT5 -+#define TWSI_CONTROL_ENA BIT6 -+#define TWSI_CONTROL_INT_ENA BIT7 -+ -+ -+#define TWSI_STATUS_BAUDE_RATE_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x0c) -+#define TWSI_BAUD_RATE_N_OFFS 0 -+#define TWSI_BAUD_RATE_N_MASK (0x7 << TWSI_BAUD_RATE_N_OFFS) -+#define TWSI_BAUD_RATE_M_OFFS 3 -+#define TWSI_BAUD_RATE_M_MASK (0xF << TWSI_BAUD_RATE_M_OFFS) -+ -+#define TWSI_SOFT_RESET_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x1c) -+ -+/* defines */ -+#define TWSI_TIMEOUT_VALUE 0x500 -+ -+/* TWSI status codes */ -+#define TWSI_BUS_ERROR 0x00 -+#define TWSI_START_CON_TRA 0x08 -+#define TWSI_REPEATED_START_CON_TRA 0x10 -+#define TWSI_AD_PLS_WR_BIT_TRA_ACK_REC 0x18 -+#define TWSI_AD_PLS_WR_BIT_TRA_ACK_NOT_REC 0x20 -+#define TWSI_M_TRAN_DATA_BYTE_ACK_REC 0x28 -+#define TWSI_M_TRAN_DATA_BYTE_ACK_NOT_REC 0x30 -+#define TWSI_M_LOST_ARB_DUR_AD_OR_DATA_TRA 0x38 -+#define TWSI_AD_PLS_RD_BIT_TRA_ACK_REC 0x40 -+#define TWSI_AD_PLS_RD_BIT_TRA_ACK_NOT_REC 0x48 -+#define TWSI_M_REC_RD_DATA_ACK_TRA 0x50 -+#define TWSI_M_REC_RD_DATA_ACK_NOT_TRA 0x58 -+#define TWSI_SLA_REC_AD_PLS_WR_BIT_ACK_TRA 0x60 -+#define TWSI_M_LOST_ARB_DUR_AD_TRA_AD_IS_TRGT_TO_SLA_ACK_TRA_W 0x68 -+#define TWSI_GNL_CALL_REC_ACK_TRA 0x70 -+#define TWSI_M_LOST_ARB_DUR_AD_TRA_GNL_CALL_AD_REC_ACK_TRA 0x78 -+#define TWSI_SLA_REC_WR_DATA_AF_REC_SLA_AD_ACK_TRAN 0x80 -+#define TWSI_SLA_REC_WR_DATA_AF_REC_SLA_AD_ACK_NOT_TRAN 0x88 -+#define TWSI_SLA_REC_WR_DATA_AF_REC_GNL_CALL_ACK_TRAN 0x90 -+#define TWSI_SLA_REC_WR_DATA_AF_REC_GNL_CALL_ACK_NOT_TRAN 0x98 -+#define TWSI_SLA_REC_STOP_OR_REPEATED_STRT_CON 0xA0 -+#define TWSI_SLA_REC_AD_PLS_RD_BIT_ACK_TRA 0xA8 -+#define TWSI_M_LOST_ARB_DUR_AD_TRA_AD_IS_TRGT_TO_SLA_ACK_TRA_R 0xB0 -+#define TWSI_SLA_TRA_RD_DATA_ACK_REC 0xB8 -+#define TWSI_SLA_TRA_RD_DATA_ACK_NOT_REC 0xC0 -+#define TWSI_SLA_TRA_LAST_RD_DATA_ACK_REC 0xC8 -+#define TWSI_SEC_AD_PLS_WR_BIT_TRA_ACK_REC 0xD0 -+#define TWSI_SEC_AD_PLS_WR_BIT_TRA_ACK_NOT_REC 0xD8 -+#define TWSI_SEC_AD_PLS_RD_BIT_TRA_ACK_REC 0xE0 -+#define TWSI_SEC_AD_PLS_RD_BIT_TRA_ACK_NOT_REC 0xE8 -+#define TWSI_NO_REL_STS_INT_FLAG_IS_KEPT_0 0xF8 -+ -+ -+#ifdef __cplusplus -+} -+#endif /* __cplusplus */ -+ -+#endif /* __INCmvTwsiSpech */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mvSysHwConfig.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mvSysHwConfig.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mvSysHwConfig.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mvSysHwConfig.h 2010-11-09 20:28:12.322486315 +0100 -@@ -0,0 +1,375 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+ -+*******************************************************************************/ -+/******************************************************************************* -+* mvSysHwCfg.h - Marvell system HW configuration file -+* -+* DESCRIPTION: -+* None. -+* -+* DEPENDENCIES: -+* None. -+* -+*******************************************************************************/ -+ -+#ifndef __INCmvSysHwConfigh -+#define __INCmvSysHwConfigh -+ -+#include "../../../../include/linux/autoconf.h" -+ -+#define CONFIG_MARVELL 1 -+ -+/* includes */ -+#define _1K 0x00000400 -+#define _4K 0x00001000 -+#define _8K 0x00002000 -+#define _16K 0x00004000 -+#define _32K 0x00008000 -+#define _64K 0x00010000 -+#define _128K 0x00020000 -+#define _256K 0x00040000 -+#define _512K 0x00080000 -+ -+#define _1M 0x00100000 -+#define _2M 0x00200000 -+#define _4M 0x00400000 -+#define _8M 0x00800000 -+#define _16M 0x01000000 -+#define _32M 0x02000000 -+#define _64M 0x04000000 -+#define _128M 0x08000000 -+#define _256M 0x10000000 -+#define _512M 0x20000000 -+ -+#define _1G 0x40000000 -+#define _2G 0x80000000 -+ -+/****************************************/ -+/* Soc supporeted Units definitions */ -+/****************************************/ -+ -+#ifdef CONFIG_MV_INCLUDE_PEX -+#define MV_INCLUDE_PEX -+#endif -+#ifdef CONFIG_MV_INCLUDE_TWSI -+#define MV_INCLUDE_TWSI -+#endif -+#ifdef CONFIG_MV_INCLUDE_CESA -+#define MV_INCLUDE_CESA -+#endif -+#ifdef CONFIG_MV_INCLUDE_GIG_ETH -+#define MV_INCLUDE_GIG_ETH -+#endif -+#ifdef CONFIG_MV_INCLUDE_INTEG_SATA -+#define MV_INCLUDE_INTEG_SATA -+#define MV_INCLUDE_SATA -+#endif -+#ifdef CONFIG_MV_INCLUDE_USB -+#define MV_INCLUDE_USB -+#define MV_USB_VOLTAGE_FIX -+#endif -+#ifdef CONFIG_MV_INCLUDE_NAND -+#define MV_INCLUDE_NAND -+#endif -+#ifdef CONFIG_MV_INCLUDE_TDM -+#define MV_INCLUDE_TDM -+#endif -+#ifdef CONFIG_MV_INCLUDE_XOR -+#define MV_INCLUDE_XOR -+#endif -+#ifdef CONFIG_MV_INCLUDE_TWSI -+#define MV_INCLUDE_TWSI -+#endif -+#ifdef CONFIG_MV_INCLUDE_UART -+#define MV_INCLUDE_UART -+#endif -+#ifdef CONFIG_MV_INCLUDE_SPI -+#define MV_INCLUDE_SPI -+#endif -+#ifdef CONFIG_MV_INCLUDE_SFLASH_MTD -+#define MV_INCLUDE_SFLASH_MTD -+#endif -+#ifdef CONFIG_MV_INCLUDE_AUDIO -+#define MV_INCLUDE_AUDIO -+#endif -+#ifdef CONFIG_MV_INCLUDE_TS -+#define MV_INCLUDE_TS -+#endif -+#ifdef CONFIG_MV_INCLUDE_SDIO -+#define MV_INCLUDE_SDIO -+#endif -+ -+ -+/* NAND flash stuff */ -+#ifdef CONFIG_MV_NAND_BOOT -+#define MV_NAND_BOOT -+#endif -+#ifdef CONFIG_MV_NAND -+#define MV_NAND -+#endif -+ -+/* SPI flash stuff */ -+#ifdef CONFIG_MV_SPI_BOOT -+#define MV_SPI_BOOT -+#endif -+ -+ -+/****************************************************************/ -+/************* General configuration ********************/ -+/****************************************************************/ -+ -+/* Enable Clock Power Control */ -+#define MV_INCLUDE_CLK_PWR_CNTRL -+ -+/* Disable the DEVICE BAR in the PEX */ -+#define MV_DISABLE_PEX_DEVICE_BAR -+ -+/* Allow the usage of early printings during initialization */ -+#define MV_INCLUDE_EARLY_PRINTK -+ -+/****************************************************************/ -+/************* NFP configuration ********************************/ -+/****************************************************************/ -+#define MV_NFP_SEC_Q_SIZE 64 -+#define MV_NFP_SEC_REQ_Q_SIZE 1000 -+ -+ -+ -+/****************************************************************/ -+/************* CESA configuration ********************/ -+/****************************************************************/ -+ -+#ifdef MV_INCLUDE_CESA -+ -+#define MV_CESA_MAX_CHAN 4 -+ -+/* Use 2K of SRAM */ -+#define MV_CESA_MAX_BUF_SIZE 1600 -+ -+#endif /* MV_INCLUDE_CESA */ -+ -+#if defined(CONFIG_MV_INCLUDE_GIG_ETH) -+ -+#ifdef CONFIG_MV_NFP_STATS -+#define MV_FP_STATISTICS -+#else -+#undef MV_FP_STATISTICS -+#endif -+/* Default configuration for SKB_REUSE: 0 - Disabled, 1 - Enabled */ -+#define MV_ETH_SKB_REUSE_DEFAULT 1 -+/* Default configuration for TX_EN workaround: 0 - Disabled, 1 - Enabled */ -+#define MV_ETH_TX_EN_DEFAULT 0 -+ -+/* un-comment if you want to perform tx_done from within the poll function */ -+/* #define ETH_TX_DONE_ISR */ -+ -+/* put descriptors in uncached memory */ -+/* #define ETH_DESCR_UNCACHED */ -+ -+/* Descriptors location: DRAM/internal-SRAM */ -+#define ETH_DESCR_IN_SDRAM -+#undef ETH_DESCR_IN_SRAM /* No integrated SRAM in 88Fxx81 devices */ -+ -+#if defined(ETH_DESCR_IN_SRAM) -+#if defined(ETH_DESCR_UNCACHED) -+ #define ETH_DESCR_CONFIG_STR "Uncached descriptors in integrated SRAM" -+#else -+ #define ETH_DESCR_CONFIG_STR "Cached descriptors in integrated SRAM" -+#endif -+#elif defined(ETH_DESCR_IN_SDRAM) -+#if defined(ETH_DESCR_UNCACHED) -+ #define ETH_DESCR_CONFIG_STR "Uncached descriptors in DRAM" -+#else -+ #define ETH_DESCR_CONFIG_STR "Cached descriptors in DRAM" -+#endif -+#else -+ #error "Ethernet descriptors location undefined" -+#endif /* ETH_DESCR_IN_SRAM or ETH_DESCR_IN_SDRAM*/ -+ -+/* SW Sync-Barrier: not relevant for 88fxx81*/ -+/* Reasnable to define this macro when descriptors in SRAM and buffers in DRAM */ -+/* In RX the CPU theoretically might see himself as the descriptor owner, */ -+/* although the buffer hadn't been written to DRAM yet. Performance cost. */ -+/* #define INCLUDE_SYNC_BARR */ -+ -+/* Buffers cache coherency method (buffers in DRAM) */ -+#ifndef MV_CACHE_COHER_SW -+/* Taken from mvCommon.h */ -+/* Memory uncached, HW or SW cache coherency is not needed */ -+#define MV_UNCACHED 0 -+/* Memory cached, HW cache coherency supported in WriteThrough mode */ -+#define MV_CACHE_COHER_HW_WT 1 -+/* Memory cached, HW cache coherency supported in WriteBack mode */ -+#define MV_CACHE_COHER_HW_WB 2 -+/* Memory cached, No HW cache coherency, Cache coherency must be in SW */ -+#define MV_CACHE_COHER_SW 3 -+ -+#endif -+ -+/* DRAM cache coherency configuration */ -+#define MV_CACHE_COHERENCY MV_CACHE_COHER_SW -+ -+ -+#define ETHER_DRAM_COHER MV_CACHE_COHER_SW /* No HW coherency in 88Fxx81 devices */ -+ -+#if (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WB) -+ #define ETH_SDRAM_CONFIG_STR "DRAM HW cache coherency (write-back)" -+#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WT) -+ #define ETH_SDRAM_CONFIG_STR "DRAM HW cache coherency (write-through)" -+#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) -+ #define ETH_SDRAM_CONFIG_STR "DRAM SW cache-coherency" -+#elif (ETHER_DRAM_COHER == MV_UNCACHED) -+# define ETH_SDRAM_CONFIG_STR "DRAM uncached" -+#else -+ #error "Ethernet-DRAM undefined" -+#endif /* ETHER_DRAM_COHER */ -+ -+ -+/****************************************************************/ -+/************* Ethernet driver configuration ********************/ -+/****************************************************************/ -+ -+/* port's default queueus */ -+#define ETH_DEF_TXQ 0 -+#define ETH_DEF_RXQ 0 -+ -+#define MV_ETH_RX_Q_NUM CONFIG_MV_ETH_RX_Q_NUM -+#define MV_ETH_TX_Q_NUM CONFIG_MV_ETH_TX_Q_NUM -+ -+/* interrupt coalescing setting */ -+#define ETH_TX_COAL 200 -+#define ETH_RX_COAL 200 -+ -+/* Checksum offloading */ -+#define TX_CSUM_OFFLOAD -+#define RX_CSUM_OFFLOAD -+ -+#endif /* CONFIG_MV_INCLUDE_GIG_ETH */ -+ -+/****************************************************************/ -+/*************** Telephony configuration ************************/ -+/****************************************************************/ -+#if defined(CONFIG_MV_TDM_LINEAR_MODE) -+ #define MV_TDM_LINEAR_MODE -+#elif defined(CONFIG_MV_TDM_ULAW_MODE) -+ #define MV_TDM_ULAW_MODE -+#endif -+ -+#if defined(CONFIG_MV_TDM_5CHANNELS) -+ #define MV_TDM_5CHANNELS -+#endif -+ -+#if defined(CONFIG_MV_TDM_USE_EXTERNAL_PCLK_SOURCE) -+ #define MV_TDM_USE_EXTERNAL_PCLK_SOURCE -+#endif -+ -+/* We use the following registers to store DRAM interface pre configuration */ -+/* auto-detection results */ -+/* IMPORTANT: We are using mask register for that purpose. Before writing */ -+/* to units mask register, make sure main maks register is set to disable */ -+/* all interrupts. */ -+#define DRAM_BUF_REG0 0x30810 /* sdram bank 0 size */ -+#define DRAM_BUF_REG1 0x30820 /* sdram config */ -+#define DRAM_BUF_REG2 0x30830 /* sdram mode */ -+#define DRAM_BUF_REG3 0x308c4 /* dunit control low */ -+#define DRAM_BUF_REG4 0x60a90 /* sdram address control */ -+#define DRAM_BUF_REG5 0x60a94 /* sdram timing control low */ -+#define DRAM_BUF_REG6 0x60a98 /* sdram timing control high */ -+#define DRAM_BUF_REG7 0x60a9c /* sdram ODT control low */ -+#define DRAM_BUF_REG8 0x60b90 /* sdram ODT control high */ -+#define DRAM_BUF_REG9 0x60b94 /* sdram Dunit ODT control */ -+#define DRAM_BUF_REG10 0x60b98 /* sdram Extended Mode */ -+#define DRAM_BUF_REG11 0x60b9c /* sdram Ddr2 Time Low Reg */ -+#define DRAM_BUF_REG12 0x60a00 /* sdram Ddr2 Time High Reg */ -+#define DRAM_BUF_REG13 0x60a04 /* dunit Ctrl High */ -+#define DRAM_BUF_REG14 0x60b00 /* sdram second DIMM exist */ -+ -+/* Following the pre-configuration registers default values restored after */ -+/* auto-detection is done */ -+#define DRAM_BUF_REG_DV 0 -+ -+/* System Mapping */ -+#define SDRAM_CS0_BASE 0x00000000 -+#define SDRAM_CS0_SIZE _256M -+ -+#define SDRAM_CS1_BASE 0x10000000 -+#define SDRAM_CS1_SIZE _256M -+ -+#define SDRAM_CS2_BASE 0x20000000 -+#define SDRAM_CS2_SIZE _256M -+ -+#define SDRAM_CS3_BASE 0x30000000 -+#define SDRAM_CS3_SIZE _256M -+ -+/* PEX */ -+#define PEX0_MEM_BASE 0xe8000000 -+#define PEX0_MEM_SIZE _128M -+ -+#define PEX0_IO_BASE 0xf2000000 -+#define PEX0_IO_SIZE _1M -+ -+/* Device Chip Selects */ -+#define NFLASH_CS_BASE 0xfa000000 -+#define NFLASH_CS_SIZE _2M -+ -+#define SPI_CS_BASE 0xf4000000 -+#define SPI_CS_SIZE _16M -+ -+#define CRYPT_ENG_BASE 0xf0000000 -+#define CRYPT_ENG_SIZE _2M -+ -+#define BOOTDEV_CS_BASE 0xff800000 -+#define BOOTDEV_CS_SIZE _8M -+ -+/* CS2 - BOOTROM */ -+#define DEVICE_CS2_BASE 0xff900000 -+#define DEVICE_CS2_SIZE _1M -+ -+/* PEX Work arround */ -+/* the target we will use for the workarround */ -+#define PEX_CONFIG_RW_WA_TARGET PEX0_MEM -+/*a flag that indicates if we are going to use the -+size and base of the target we using for the workarround -+window */ -+#define PEX_CONFIG_RW_WA_USE_ORIGINAL_WIN_VALUES 1 -+/* if the above flag is 0 then the following values -+will be used for the workarround window base and size, -+otherwise the following defines will be ignored */ -+#define PEX_CONFIG_RW_WA_BASE 0xF3000000 -+#define PEX_CONFIG_RW_WA_SIZE _16M -+ -+/* Internal registers: size is defined in Controllerenvironment */ -+#define INTER_REGS_BASE 0xFEE00000 -+ -+/* DRAM detection stuff */ -+#define MV_DRAM_AUTO_SIZE -+ -+/* Board clock detection */ -+#define TCLK_AUTO_DETECT /* Use Tclk auto detection */ -+#define SYSCLK_AUTO_DETECT /* Use SysClk auto detection */ -+#define PCLCK_AUTO_DETECT /* Use PClk auto detection */ -+#define L2CLK_AUTO_DETECT /* Use L2Clk auto detection */ -+ -+/* PEX-PCI\PCI-PCI Bridge*/ -+#define PCI0_IF_PTP 0 /* Bridge exist on pciIf0*/ -+ -+ -+ -+#endif /* __INCmvSysHwConfigh */ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/Makefile linux-2.6.36/crypto/ocf/Makefile ---- linux-2.6.36.orig/crypto/ocf/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/Makefile 2010-11-09 20:28:12.342495369 +0100 -@@ -0,0 +1,124 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+OCF_OBJS = crypto.o criov.o -+ -+ifdef CONFIG_OCF_RANDOMHARVEST -+ OCF_OBJS += random.o -+endif -+ -+ifdef CONFIG_OCF_FIPS -+ OCF_OBJS += rndtest.o -+endif -+ -+# Add in autoconf.h to get #defines for CONFIG_xxx -+AUTOCONF_H=$(ROOTDIR)/modules/autoconf.h -+ifeq ($(AUTOCONF_H), $(wildcard $(AUTOCONF_H))) -+ EXTRA_CFLAGS += -include $(AUTOCONF_H) -+ export EXTRA_CFLAGS -+endif -+ -+ifndef obj -+ obj ?= . -+ _obj = subdir -+ mod-subdirs := safe hifn ixp4xx talitos ocfnull -+ export-objs += crypto.o criov.o random.o -+ list-multi += ocf.o -+ _slash := -+else -+ _obj = obj -+ _slash := / -+endif -+ -+EXTRA_CFLAGS += -I$(obj)/. -+ -+obj-$(CONFIG_OCF_OCF) += ocf.o -+obj-$(CONFIG_OCF_CRYPTODEV) += cryptodev.o -+obj-$(CONFIG_OCF_CRYPTOSOFT) += cryptosoft.o -+obj-$(CONFIG_OCF_BENCH) += ocf-bench.o -+ -+$(_obj)-$(CONFIG_OCF_SAFE) += safe$(_slash) -+$(_obj)-$(CONFIG_OCF_HIFN) += hifn$(_slash) -+$(_obj)-$(CONFIG_OCF_IXP4XX) += ixp4xx$(_slash) -+$(_obj)-$(CONFIG_OCF_TALITOS) += talitos$(_slash) -+$(_obj)-$(CONFIG_OCF_PASEMI) += pasemi$(_slash) -+$(_obj)-$(CONFIG_OCF_EP80579) += ep80579$(_slash) -+$(_obj)-$(CONFIG_OCF_CRYPTOCTEON) += cryptocteon$(_slash) -+$(_obj)-$(CONFIG_OCF_KIRKWOOD) += kirkwood$(_slash) -+$(_obj)-$(CONFIG_OCF_OCFNULL) += ocfnull$(_slash) -+$(_obj)-$(CONFIG_OCF_C7108) += c7108$(_slash) -+ -+ocf-objs := $(OCF_OBJS) -+ -+$(list-multi) dummy1: $(ocf-objs) -+ $(LD) -r -o $@ $(ocf-objs) -+ -+.PHONY: -+clean: -+ rm -f *.o *.ko .*.o.flags .*.ko.cmd .*.o.cmd .*.mod.o.cmd *.mod.c -+ rm -f */*.o */*.ko */.*.o.cmd */.*.ko.cmd */.*.mod.o.cmd */*.mod.c */.*.o.flags -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -+# -+# release gen targets -+# -+ -+.PHONY: patch -+patch: -+ REL=`date +%Y%m%d`; \ -+ patch=ocf-linux-$$REL.patch; \ -+ patch24=ocf-linux-24-$$REL.patch; \ -+ patch26=ocf-linux-26-$$REL.patch; \ -+ ( \ -+ find . -name Makefile; \ -+ find . -name Config.in; \ -+ find . -name Kconfig; \ -+ find . -name README; \ -+ find . -name '*.[ch]' | grep -v '.mod.c'; \ -+ ) | while read t; do \ -+ diff -Nau /dev/null $$t | sed 's?^+++ \./?+++ linux/crypto/ocf/?'; \ -+ done > $$patch; \ -+ cat patches/linux-2.4.35-ocf.patch $$patch > $$patch24; \ -+ cat patches/linux-2.6.33-ocf.patch $$patch > $$patch26 -+ -+.PHONY: tarball -+tarball: -+ REL=`date +%Y%m%d`; RELDIR=/tmp/ocf-linux-$$REL; \ -+ CURDIR=`pwd`; \ -+ rm -rf /tmp/ocf-linux-$$REL*; \ -+ mkdir -p $$RELDIR/tools; \ -+ cp README* $$RELDIR; \ -+ cp patches/openss*.patch $$RELDIR; \ -+ cp patches/crypto-tools.patch $$RELDIR; \ -+ cp tools/[!C]* $$RELDIR/tools; \ -+ cd ..; \ -+ tar cvf $$RELDIR/ocf-linux.tar \ -+ --exclude=CVS \ -+ --exclude=.* \ -+ --exclude=*.o \ -+ --exclude=*.ko \ -+ --exclude=*.mod.* \ -+ --exclude=README* \ -+ --exclude=ocf-*.patch \ -+ --exclude=ocf/patches/openss*.patch \ -+ --exclude=ocf/patches/crypto-tools.patch \ -+ --exclude=ocf/tools \ -+ ocf; \ -+ gzip -9 $$RELDIR/ocf-linux.tar; \ -+ cd /tmp; \ -+ tar cvf ocf-linux-$$REL.tar ocf-linux-$$REL; \ -+ gzip -9 ocf-linux-$$REL.tar; \ -+ cd $$CURDIR/../../user; \ -+ rm -rf /tmp/crypto-tools-$$REL*; \ -+ tar cvf /tmp/crypto-tools-$$REL.tar \ -+ --exclude=CVS \ -+ --exclude=.* \ -+ --exclude=*.o \ -+ --exclude=cryptotest \ -+ --exclude=cryptokeytest \ -+ crypto-tools; \ -+ gzip -9 /tmp/crypto-tools-$$REL.tar -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/ocf-bench.c linux-2.6.36/crypto/ocf/ocf-bench.c ---- linux-2.6.36.orig/crypto/ocf/ocf-bench.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/ocf-bench.c 2010-11-09 20:28:12.381251524 +0100 -@@ -0,0 +1,436 @@ -+/* -+ * A loadable module that benchmarks the OCF crypto speed from kernel space. -+ * -+ * Copyright (C) 2004-2010 David McCullough -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * ALTERNATIVELY, provided that this notice is retained in full, this product -+ * may be distributed under the terms of the GNU General Public License (GPL), -+ * in which case the provisions of the GPL apply INSTEAD OF those given above. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ */ -+ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#ifdef I_HAVE_AN_XSCALE_WITH_INTEL_SDK -+#define BENCH_IXP_ACCESS_LIB 1 -+#endif -+#ifdef BENCH_IXP_ACCESS_LIB -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#endif -+ -+/* -+ * support for access lib version 1.4 -+ */ -+#ifndef IX_MBUF_PRIV -+#define IX_MBUF_PRIV(x) ((x)->priv) -+#endif -+ -+/* -+ * the number of simultaneously active requests -+ */ -+static int request_q_len = 20; -+module_param(request_q_len, int, 0); -+MODULE_PARM_DESC(request_q_len, "Number of outstanding requests"); -+/* -+ * how many requests we want to have processed -+ */ -+static int request_num = 1024; -+module_param(request_num, int, 0); -+MODULE_PARM_DESC(request_num, "run for at least this many requests"); -+/* -+ * the size of each request -+ */ -+static int request_size = 1500; -+module_param(request_size, int, 0); -+MODULE_PARM_DESC(request_size, "size of each request"); -+ -+/* -+ * a structure for each request -+ */ -+typedef struct { -+ struct work_struct work; -+#ifdef BENCH_IXP_ACCESS_LIB -+ IX_MBUF mbuf; -+#endif -+ unsigned char *buffer; -+} request_t; -+ -+static request_t *requests; -+ -+static int outstanding; -+static int total; -+ -+/*************************************************************************/ -+/* -+ * OCF benchmark routines -+ */ -+ -+static uint64_t ocf_cryptoid; -+static int ocf_init(void); -+static int ocf_cb(struct cryptop *crp); -+static void ocf_request(void *arg); -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void ocf_request_wq(struct work_struct *work); -+#endif -+ -+static int -+ocf_init(void) -+{ -+ int error; -+ struct cryptoini crie, cria; -+ struct cryptodesc crda, crde; -+ -+ memset(&crie, 0, sizeof(crie)); -+ memset(&cria, 0, sizeof(cria)); -+ memset(&crde, 0, sizeof(crde)); -+ memset(&crda, 0, sizeof(crda)); -+ -+ cria.cri_alg = CRYPTO_SHA1_HMAC; -+ cria.cri_klen = 20 * 8; -+ cria.cri_key = "0123456789abcdefghij"; -+ -+ crie.cri_alg = CRYPTO_3DES_CBC; -+ crie.cri_klen = 24 * 8; -+ crie.cri_key = "0123456789abcdefghijklmn"; -+ -+ crie.cri_next = &cria; -+ -+ error = crypto_newsession(&ocf_cryptoid, &crie, 0); -+ if (error) { -+ printk("crypto_newsession failed %d\n", error); -+ return -1; -+ } -+ return 0; -+} -+ -+static int -+ocf_cb(struct cryptop *crp) -+{ -+ request_t *r = (request_t *) crp->crp_opaque; -+ -+ if (crp->crp_etype) -+ printk("Error in OCF processing: %d\n", crp->crp_etype); -+ total++; -+ crypto_freereq(crp); -+ crp = NULL; -+ -+ if (total > request_num) { -+ outstanding--; -+ return 0; -+ } -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ INIT_WORK(&r->work, ocf_request_wq); -+#else -+ INIT_WORK(&r->work, ocf_request, r); -+#endif -+ schedule_work(&r->work); -+ return 0; -+} -+ -+ -+static void -+ocf_request(void *arg) -+{ -+ request_t *r = arg; -+ struct cryptop *crp = crypto_getreq(2); -+ struct cryptodesc *crde, *crda; -+ -+ if (!crp) { -+ outstanding--; -+ return; -+ } -+ -+ crde = crp->crp_desc; -+ crda = crde->crd_next; -+ -+ crda->crd_skip = 0; -+ crda->crd_flags = 0; -+ crda->crd_len = request_size; -+ crda->crd_inject = request_size; -+ crda->crd_alg = CRYPTO_SHA1_HMAC; -+ crda->crd_key = "0123456789abcdefghij"; -+ crda->crd_klen = 20 * 8; -+ -+ crde->crd_skip = 0; -+ crde->crd_flags = CRD_F_IV_EXPLICIT | CRD_F_ENCRYPT; -+ crde->crd_len = request_size; -+ crde->crd_inject = request_size; -+ crde->crd_alg = CRYPTO_3DES_CBC; -+ crde->crd_key = "0123456789abcdefghijklmn"; -+ crde->crd_klen = 24 * 8; -+ -+ crp->crp_ilen = request_size + 64; -+ crp->crp_flags = CRYPTO_F_CBIMM; -+ crp->crp_buf = (caddr_t) r->buffer; -+ crp->crp_callback = ocf_cb; -+ crp->crp_sid = ocf_cryptoid; -+ crp->crp_opaque = (caddr_t) r; -+ crypto_dispatch(crp); -+} -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void -+ocf_request_wq(struct work_struct *work) -+{ -+ request_t *r = container_of(work, request_t, work); -+ ocf_request(r); -+} -+#endif -+ -+/*************************************************************************/ -+#ifdef BENCH_IXP_ACCESS_LIB -+/*************************************************************************/ -+/* -+ * CryptoAcc benchmark routines -+ */ -+ -+static IxCryptoAccCtx ixp_ctx; -+static UINT32 ixp_ctx_id; -+static IX_MBUF ixp_pri; -+static IX_MBUF ixp_sec; -+static int ixp_registered = 0; -+ -+static void ixp_register_cb(UINT32 ctx_id, IX_MBUF *bufp, -+ IxCryptoAccStatus status); -+static void ixp_perform_cb(UINT32 ctx_id, IX_MBUF *sbufp, IX_MBUF *dbufp, -+ IxCryptoAccStatus status); -+static void ixp_request(void *arg); -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void ixp_request_wq(struct work_struct *work); -+#endif -+ -+static int -+ixp_init(void) -+{ -+ IxCryptoAccStatus status; -+ -+ ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_3DES; -+ ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; -+ ixp_ctx.cipherCtx.cipherKeyLen = 24; -+ ixp_ctx.cipherCtx.cipherBlockLen = IX_CRYPTO_ACC_DES_BLOCK_64; -+ ixp_ctx.cipherCtx.cipherInitialVectorLen = IX_CRYPTO_ACC_DES_IV_64; -+ memcpy(ixp_ctx.cipherCtx.key.cipherKey, "0123456789abcdefghijklmn", 24); -+ -+ ixp_ctx.authCtx.authAlgo = IX_CRYPTO_ACC_AUTH_SHA1; -+ ixp_ctx.authCtx.authDigestLen = 12; -+ ixp_ctx.authCtx.aadLen = 0; -+ ixp_ctx.authCtx.authKeyLen = 20; -+ memcpy(ixp_ctx.authCtx.key.authKey, "0123456789abcdefghij", 20); -+ -+ ixp_ctx.useDifferentSrcAndDestMbufs = 0; -+ ixp_ctx.operation = IX_CRYPTO_ACC_OP_ENCRYPT_AUTH ; -+ -+ IX_MBUF_MLEN(&ixp_pri) = IX_MBUF_PKT_LEN(&ixp_pri) = 128; -+ IX_MBUF_MDATA(&ixp_pri) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); -+ IX_MBUF_MLEN(&ixp_sec) = IX_MBUF_PKT_LEN(&ixp_sec) = 128; -+ IX_MBUF_MDATA(&ixp_sec) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); -+ -+ status = ixCryptoAccCtxRegister(&ixp_ctx, &ixp_pri, &ixp_sec, -+ ixp_register_cb, ixp_perform_cb, &ixp_ctx_id); -+ -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) { -+ while (!ixp_registered) -+ schedule(); -+ return ixp_registered < 0 ? -1 : 0; -+ } -+ -+ printk("ixp: ixCryptoAccCtxRegister failed %d\n", status); -+ return -1; -+} -+ -+static void -+ixp_register_cb(UINT32 ctx_id, IX_MBUF *bufp, IxCryptoAccStatus status) -+{ -+ if (bufp) { -+ IX_MBUF_MLEN(bufp) = IX_MBUF_PKT_LEN(bufp) = 0; -+ kfree(IX_MBUF_MDATA(bufp)); -+ IX_MBUF_MDATA(bufp) = NULL; -+ } -+ -+ if (IX_CRYPTO_ACC_STATUS_WAIT == status) -+ return; -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) -+ ixp_registered = 1; -+ else -+ ixp_registered = -1; -+} -+ -+static void -+ixp_perform_cb( -+ UINT32 ctx_id, -+ IX_MBUF *sbufp, -+ IX_MBUF *dbufp, -+ IxCryptoAccStatus status) -+{ -+ request_t *r = NULL; -+ -+ total++; -+ if (total > request_num) { -+ outstanding--; -+ return; -+ } -+ -+ if (!sbufp || !(r = IX_MBUF_PRIV(sbufp))) { -+ printk("crappo %p %p\n", sbufp, r); -+ outstanding--; -+ return; -+ } -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ INIT_WORK(&r->work, ixp_request_wq); -+#else -+ INIT_WORK(&r->work, ixp_request, r); -+#endif -+ schedule_work(&r->work); -+} -+ -+static void -+ixp_request(void *arg) -+{ -+ request_t *r = arg; -+ IxCryptoAccStatus status; -+ -+ memset(&r->mbuf, 0, sizeof(r->mbuf)); -+ IX_MBUF_MLEN(&r->mbuf) = IX_MBUF_PKT_LEN(&r->mbuf) = request_size + 64; -+ IX_MBUF_MDATA(&r->mbuf) = r->buffer; -+ IX_MBUF_PRIV(&r->mbuf) = r; -+ status = ixCryptoAccAuthCryptPerform(ixp_ctx_id, &r->mbuf, NULL, -+ 0, request_size, 0, request_size, request_size, r->buffer); -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS != status) { -+ printk("status1 = %d\n", status); -+ outstanding--; -+ return; -+ } -+ return; -+} -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void -+ixp_request_wq(struct work_struct *work) -+{ -+ request_t *r = container_of(work, request_t, work); -+ ixp_request(r); -+} -+#endif -+ -+/*************************************************************************/ -+#endif /* BENCH_IXP_ACCESS_LIB */ -+/*************************************************************************/ -+ -+int -+ocfbench_init(void) -+{ -+ int i, jstart, jstop; -+ -+ printk("Crypto Speed tests\n"); -+ -+ requests = kmalloc(sizeof(request_t) * request_q_len, GFP_KERNEL); -+ if (!requests) { -+ printk("malloc failed\n"); -+ return -EINVAL; -+ } -+ -+ for (i = 0; i < request_q_len; i++) { -+ /* +64 for return data */ -+ requests[i].buffer = kmalloc(request_size + 128, GFP_DMA); -+ if (!requests[i].buffer) { -+ printk("malloc failed\n"); -+ return -EINVAL; -+ } -+ memset(requests[i].buffer, '0' + i, request_size + 128); -+ } -+ -+ /* -+ * OCF benchmark -+ */ -+ printk("OCF: testing ...\n"); -+ ocf_init(); -+ total = outstanding = 0; -+ jstart = jiffies; -+ for (i = 0; i < request_q_len; i++) { -+ outstanding++; -+ ocf_request(&requests[i]); -+ } -+ while (outstanding > 0) -+ schedule(); -+ jstop = jiffies; -+ -+ printk("OCF: %d requests of %d bytes in %d jiffies\n", total, request_size, -+ jstop - jstart); -+ -+#ifdef BENCH_IXP_ACCESS_LIB -+ /* -+ * IXP benchmark -+ */ -+ printk("IXP: testing ...\n"); -+ ixp_init(); -+ total = outstanding = 0; -+ jstart = jiffies; -+ for (i = 0; i < request_q_len; i++) { -+ outstanding++; -+ ixp_request(&requests[i]); -+ } -+ while (outstanding > 0) -+ schedule(); -+ jstop = jiffies; -+ -+ printk("IXP: %d requests of %d bytes in %d jiffies\n", total, request_size, -+ jstop - jstart); -+#endif /* BENCH_IXP_ACCESS_LIB */ -+ -+ for (i = 0; i < request_q_len; i++) -+ kfree(requests[i].buffer); -+ kfree(requests); -+ return -EINVAL; /* always fail to load so it can be re-run quickly ;-) */ -+} -+ -+static void __exit ocfbench_exit(void) -+{ -+} -+ -+module_init(ocfbench_init); -+module_exit(ocfbench_exit); -+ -+MODULE_LICENSE("BSD"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("Benchmark various in-kernel crypto speeds"); -diff -Nur linux-2.6.36.orig/crypto/ocf/ocf-compat.h linux-2.6.36/crypto/ocf/ocf-compat.h ---- linux-2.6.36.orig/crypto/ocf/ocf-compat.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/ocf-compat.h 2010-11-09 20:28:12.422358492 +0100 -@@ -0,0 +1,294 @@ -+#ifndef _BSD_COMPAT_H_ -+#define _BSD_COMPAT_H_ 1 -+/****************************************************************************/ -+/* -+ * Provide compat routines for older linux kernels and BSD kernels -+ * -+ * Written by David McCullough -+ * Copyright (C) 2010 David McCullough -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * ALTERNATIVELY, provided that this notice is retained in full, this file -+ * may be distributed under the terms of the GNU General Public License (GPL), -+ * in which case the provisions of the GPL apply INSTEAD OF those given above. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ */ -+/****************************************************************************/ -+#ifdef __KERNEL__ -+/* -+ * fake some BSD driver interface stuff specifically for OCF use -+ */ -+ -+typedef struct ocf_device *device_t; -+ -+typedef struct { -+ int (*cryptodev_newsession)(device_t dev, u_int32_t *sidp, struct cryptoini *cri); -+ int (*cryptodev_freesession)(device_t dev, u_int64_t tid); -+ int (*cryptodev_process)(device_t dev, struct cryptop *crp, int hint); -+ int (*cryptodev_kprocess)(device_t dev, struct cryptkop *krp, int hint); -+} device_method_t; -+#define DEVMETHOD(id, func) id: func -+ -+struct ocf_device { -+ char name[32]; /* the driver name */ -+ char nameunit[32]; /* the driver name + HW instance */ -+ int unit; -+ device_method_t methods; -+ void *softc; -+}; -+ -+#define CRYPTODEV_NEWSESSION(dev, sid, cri) \ -+ ((*(dev)->methods.cryptodev_newsession)(dev,sid,cri)) -+#define CRYPTODEV_FREESESSION(dev, sid) \ -+ ((*(dev)->methods.cryptodev_freesession)(dev, sid)) -+#define CRYPTODEV_PROCESS(dev, crp, hint) \ -+ ((*(dev)->methods.cryptodev_process)(dev, crp, hint)) -+#define CRYPTODEV_KPROCESS(dev, krp, hint) \ -+ ((*(dev)->methods.cryptodev_kprocess)(dev, krp, hint)) -+ -+#define device_get_name(dev) ((dev)->name) -+#define device_get_nameunit(dev) ((dev)->nameunit) -+#define device_get_unit(dev) ((dev)->unit) -+#define device_get_softc(dev) ((dev)->softc) -+ -+#define softc_device_decl \ -+ struct ocf_device _device; \ -+ device_t -+ -+#define softc_device_init(_sc, _name, _unit, _methods) \ -+ if (1) {\ -+ strncpy((_sc)->_device.name, _name, sizeof((_sc)->_device.name) - 1); \ -+ snprintf((_sc)->_device.nameunit, sizeof((_sc)->_device.name), "%s%d", _name, _unit); \ -+ (_sc)->_device.unit = _unit; \ -+ (_sc)->_device.methods = _methods; \ -+ (_sc)->_device.softc = (void *) _sc; \ -+ *(device_t *)((softc_get_device(_sc))+1) = &(_sc)->_device; \ -+ } else -+ -+#define softc_get_device(_sc) (&(_sc)->_device) -+ -+/* -+ * iomem support for 2.4 and 2.6 kernels -+ */ -+#include -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+#define ocf_iomem_t unsigned long -+ -+/* -+ * implement simple workqueue like support for older kernels -+ */ -+ -+#include -+ -+#define work_struct tq_struct -+ -+#define INIT_WORK(wp, fp, ap) \ -+ do { \ -+ (wp)->sync = 0; \ -+ (wp)->routine = (fp); \ -+ (wp)->data = (ap); \ -+ } while (0) -+ -+#define schedule_work(wp) \ -+ do { \ -+ queue_task((wp), &tq_immediate); \ -+ mark_bh(IMMEDIATE_BH); \ -+ } while (0) -+ -+#define flush_scheduled_work() run_task_queue(&tq_immediate) -+ -+#else -+#define ocf_iomem_t void __iomem * -+ -+#include -+ -+#endif -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26) -+#include -+#elif LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) -+#define files_fdtable(files) (files) -+#endif -+ -+#ifdef MODULE_PARM -+#undef module_param /* just in case */ -+#define module_param(a,b,c) MODULE_PARM(a,"i") -+#endif -+ -+#define bzero(s,l) memset(s,0,l) -+#define bcopy(s,d,l) memcpy(d,s,l) -+#define bcmp(x, y, l) memcmp(x,y,l) -+ -+#define MIN(x,y) ((x) < (y) ? (x) : (y)) -+ -+#define device_printf(dev, a...) ({ \ -+ printk("%s: ", device_get_nameunit(dev)); printk(a); \ -+ }) -+ -+#undef printf -+#define printf(fmt...) printk(fmt) -+ -+#define KASSERT(c,p) if (!(c)) { printk p ; } else -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+#define ocf_daemonize(str) \ -+ daemonize(); \ -+ spin_lock_irq(¤t->sigmask_lock); \ -+ sigemptyset(¤t->blocked); \ -+ recalc_sigpending(current); \ -+ spin_unlock_irq(¤t->sigmask_lock); \ -+ sprintf(current->comm, str); -+#else -+#define ocf_daemonize(str) daemonize(str); -+#endif -+ -+#define TAILQ_INSERT_TAIL(q,d,m) list_add_tail(&(d)->m, (q)) -+#define TAILQ_EMPTY(q) list_empty(q) -+#define TAILQ_FOREACH(v, q, m) list_for_each_entry(v, q, m) -+ -+#define read_random(p,l) get_random_bytes(p,l) -+ -+#define DELAY(x) ((x) > 2000 ? mdelay((x)/1000) : udelay(x)) -+#define strtoul simple_strtoul -+ -+#define pci_get_vendor(dev) ((dev)->vendor) -+#define pci_get_device(dev) ((dev)->device) -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+#define pci_set_consistent_dma_mask(dev, mask) (0) -+#endif -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10) -+#define pci_dma_sync_single_for_cpu pci_dma_sync_single -+#endif -+ -+#ifndef DMA_32BIT_MASK -+#define DMA_32BIT_MASK 0x00000000ffffffffULL -+#endif -+ -+#ifndef htole32 -+#define htole32(x) cpu_to_le32(x) -+#endif -+#ifndef htobe32 -+#define htobe32(x) cpu_to_be32(x) -+#endif -+#ifndef htole16 -+#define htole16(x) cpu_to_le16(x) -+#endif -+#ifndef htobe16 -+#define htobe16(x) cpu_to_be16(x) -+#endif -+ -+/* older kernels don't have these */ -+ -+#include -+#if !defined(IRQ_NONE) && !defined(IRQ_RETVAL) -+#define IRQ_NONE -+#define IRQ_HANDLED -+#define IRQ_WAKE_THREAD -+#define IRQ_RETVAL -+#define irqreturn_t void -+typedef irqreturn_t (*irq_handler_t)(int irq, void *arg, struct pt_regs *regs); -+#endif -+#ifndef IRQF_SHARED -+#define IRQF_SHARED SA_SHIRQ -+#endif -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) -+# define strlcpy(dest,src,len) \ -+ ({strncpy(dest,src,(len)-1); ((char *)dest)[(len)-1] = '\0'; }) -+#endif -+ -+#ifndef MAX_ERRNO -+#define MAX_ERRNO 4095 -+#endif -+#ifndef IS_ERR_VALUE -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,5) -+#include -+#endif -+#ifndef IS_ERR_VALUE -+#define IS_ERR_VALUE(x) ((unsigned long)(x) >= (unsigned long)-MAX_ERRNO) -+#endif -+#endif -+ -+/* -+ * common debug for all -+ */ -+#if 1 -+#define dprintk(a...) do { if (debug) printk(a); } while(0) -+#else -+#define dprintk(a...) -+#endif -+ -+#ifndef SLAB_ATOMIC -+/* Changed in 2.6.20, must use GFP_ATOMIC now */ -+#define SLAB_ATOMIC GFP_ATOMIC -+#endif -+ -+/* -+ * need some additional support for older kernels */ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,2) -+#define pci_register_driver_compat(driver, rc) \ -+ do { \ -+ if ((rc) > 0) { \ -+ (rc) = 0; \ -+ } else if (rc == 0) { \ -+ (rc) = -ENODEV; \ -+ } else { \ -+ pci_unregister_driver(driver); \ -+ } \ -+ } while (0) -+#elif LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10) -+#define pci_register_driver_compat(driver,rc) ((rc) = (rc) < 0 ? (rc) : 0) -+#else -+#define pci_register_driver_compat(driver,rc) -+#endif -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) -+ -+#include -+#include -+ -+static inline void sg_set_page(struct scatterlist *sg, struct page *page, -+ unsigned int len, unsigned int offset) -+{ -+ sg->page = page; -+ sg->offset = offset; -+ sg->length = len; -+} -+ -+static inline void *sg_virt(struct scatterlist *sg) -+{ -+ return page_address(sg->page) + sg->offset; -+} -+ -+#define sg_init_table(sg, n) -+ -+#endif -+ -+#ifndef late_initcall -+#define late_initcall(init) module_init(init) -+#endif -+ -+#endif /* __KERNEL__ */ -+ -+/****************************************************************************/ -+#endif /* _BSD_COMPAT_H_ */ -diff -Nur linux-2.6.36.orig/crypto/ocf/ocfnull/Makefile linux-2.6.36/crypto/ocf/ocfnull/Makefile ---- linux-2.6.36.orig/crypto/ocf/ocfnull/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/ocfnull/Makefile 2010-11-09 20:28:12.462495574 +0100 -@@ -0,0 +1,12 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+obj-$(CONFIG_OCF_OCFNULL) += ocfnull.o -+ -+obj ?= . -+EXTRA_CFLAGS += -I$(obj)/.. -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/ocfnull/ocfnull.c linux-2.6.36/crypto/ocf/ocfnull/ocfnull.c ---- linux-2.6.36.orig/crypto/ocf/ocfnull/ocfnull.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/ocfnull/ocfnull.c 2010-11-09 20:28:12.501251038 +0100 -@@ -0,0 +1,203 @@ -+/* -+ * An OCF module for determining the cost of crypto versus the cost of -+ * IPSec processing outside of OCF. This modules gives us the effect of -+ * zero cost encryption, of course you will need to run it at both ends -+ * since it does no crypto at all. -+ * -+ * Written by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * ALTERNATIVELY, provided that this notice is retained in full, this product -+ * may be distributed under the terms of the GNU General Public License (GPL), -+ * in which case the provisions of the GPL apply INSTEAD OF those given above. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ */ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+static int32_t null_id = -1; -+static u_int32_t null_sesnum = 0; -+ -+static int null_process(device_t, struct cryptop *, int); -+static int null_newsession(device_t, u_int32_t *, struct cryptoini *); -+static int null_freesession(device_t, u_int64_t); -+ -+#define debug ocfnull_debug -+int ocfnull_debug = 0; -+module_param(ocfnull_debug, int, 0644); -+MODULE_PARM_DESC(ocfnull_debug, "Enable debug"); -+ -+/* -+ * dummy device structure -+ */ -+ -+static struct { -+ softc_device_decl sc_dev; -+} nulldev; -+ -+static device_method_t null_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, null_newsession), -+ DEVMETHOD(cryptodev_freesession,null_freesession), -+ DEVMETHOD(cryptodev_process, null_process), -+}; -+ -+/* -+ * Generate a new software session. -+ */ -+static int -+null_newsession(device_t arg, u_int32_t *sid, struct cryptoini *cri) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid == NULL || cri == NULL) { -+ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ if (null_sesnum == 0) -+ null_sesnum++; -+ *sid = null_sesnum++; -+ return 0; -+} -+ -+ -+/* -+ * Free a session. -+ */ -+static int -+null_freesession(device_t arg, u_int64_t tid) -+{ -+ u_int32_t sid = CRYPTO_SESID2LID(tid); -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid > null_sesnum) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ /* Silently accept and return */ -+ if (sid == 0) -+ return 0; -+ return 0; -+} -+ -+ -+/* -+ * Process a request. -+ */ -+static int -+null_process(device_t arg, struct cryptop *crp, int hint) -+{ -+ unsigned int lid; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ /* Sanity check */ -+ if (crp == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ crp->crp_etype = 0; -+ -+ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ /* -+ * find the session we are using -+ */ -+ -+ lid = crp->crp_sid & 0xffffffff; -+ if (lid >= null_sesnum || lid == 0) { -+ crp->crp_etype = ENOENT; -+ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); -+ goto done; -+ } -+ -+done: -+ crypto_done(crp); -+ return 0; -+} -+ -+ -+/* -+ * our driver startup and shutdown routines -+ */ -+ -+static int -+null_init(void) -+{ -+ dprintk("%s(%p)\n", __FUNCTION__, null_init); -+ -+ memset(&nulldev, 0, sizeof(nulldev)); -+ softc_device_init(&nulldev, "ocfnull", 0, null_methods); -+ -+ null_id = crypto_get_driverid(softc_get_device(&nulldev), -+ CRYPTOCAP_F_HARDWARE); -+ if (null_id < 0) -+ panic("ocfnull: crypto device cannot initialize!"); -+ -+#define REGISTER(alg) \ -+ crypto_register(null_id,alg,0,0) -+ REGISTER(CRYPTO_DES_CBC); -+ REGISTER(CRYPTO_3DES_CBC); -+ REGISTER(CRYPTO_RIJNDAEL128_CBC); -+ REGISTER(CRYPTO_MD5); -+ REGISTER(CRYPTO_SHA1); -+ REGISTER(CRYPTO_MD5_HMAC); -+ REGISTER(CRYPTO_SHA1_HMAC); -+#undef REGISTER -+ -+ return 0; -+} -+ -+static void -+null_exit(void) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ crypto_unregister_all(null_id); -+ null_id = -1; -+} -+ -+module_init(null_init); -+module_exit(null_exit); -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("ocfnull - claims a lot but does nothing"); -diff -Nur linux-2.6.36.orig/crypto/ocf/pasemi/Makefile linux-2.6.36/crypto/ocf/pasemi/Makefile ---- linux-2.6.36.orig/crypto/ocf/pasemi/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/pasemi/Makefile 2010-11-09 20:28:12.532495480 +0100 -@@ -0,0 +1,12 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+obj-$(CONFIG_OCF_PASEMI) += pasemi.o -+ -+obj ?= . -+EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/pasemi/pasemi.c linux-2.6.36/crypto/ocf/pasemi/pasemi.c ---- linux-2.6.36.orig/crypto/ocf/pasemi/pasemi.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/pasemi/pasemi.c 2010-11-09 20:28:12.572495531 +0100 -@@ -0,0 +1,1009 @@ -+/* -+ * Copyright (C) 2007 PA Semi, Inc -+ * -+ * Driver for the PA Semi PWRficient DMA Crypto Engine -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "pasemi_fnu.h" -+ -+#define DRV_NAME "pasemi" -+ -+#define TIMER_INTERVAL 1000 -+ -+static void __devexit pasemi_dma_remove(struct pci_dev *pdev); -+static struct pasdma_status volatile * dma_status; -+ -+static int debug; -+module_param(debug, int, 0644); -+MODULE_PARM_DESC(debug, "Enable debug"); -+ -+static void pasemi_desc_start(struct pasemi_desc *desc, u64 hdr) -+{ -+ desc->postop = 0; -+ desc->quad[0] = hdr; -+ desc->quad_cnt = 1; -+ desc->size = 1; -+} -+ -+static void pasemi_desc_build(struct pasemi_desc *desc, u64 val) -+{ -+ desc->quad[desc->quad_cnt++] = val; -+ desc->size = (desc->quad_cnt + 1) / 2; -+} -+ -+static void pasemi_desc_hdr(struct pasemi_desc *desc, u64 hdr) -+{ -+ desc->quad[0] |= hdr; -+} -+ -+static int pasemi_desc_size(struct pasemi_desc *desc) -+{ -+ return desc->size; -+} -+ -+static void pasemi_ring_add_desc( -+ struct pasemi_fnu_txring *ring, -+ struct pasemi_desc *desc, -+ struct cryptop *crp) { -+ int i; -+ int ring_index = 2 * (ring->next_to_fill & (TX_RING_SIZE-1)); -+ -+ TX_DESC_INFO(ring, ring->next_to_fill).desc_size = desc->size; -+ TX_DESC_INFO(ring, ring->next_to_fill).desc_postop = desc->postop; -+ TX_DESC_INFO(ring, ring->next_to_fill).cf_crp = crp; -+ -+ for (i = 0; i < desc->quad_cnt; i += 2) { -+ ring_index = 2 * (ring->next_to_fill & (TX_RING_SIZE-1)); -+ ring->desc[ring_index] = desc->quad[i]; -+ ring->desc[ring_index + 1] = desc->quad[i + 1]; -+ ring->next_to_fill++; -+ } -+ -+ if (desc->quad_cnt & 1) -+ ring->desc[ring_index + 1] = 0; -+} -+ -+static void pasemi_ring_incr(struct pasemi_softc *sc, int chan_index, int incr) -+{ -+ out_le32(sc->dma_regs + PAS_DMA_TXCHAN_INCR(sc->base_chan + chan_index), -+ incr); -+} -+ -+/* -+ * Generate a new software session. -+ */ -+static int -+pasemi_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) -+{ -+ struct cryptoini *c, *encini = NULL, *macini = NULL; -+ struct pasemi_softc *sc = device_get_softc(dev); -+ struct pasemi_session *ses = NULL, **sespp; -+ int sesn, blksz = 0; -+ u64 ccmd = 0; -+ unsigned long flags; -+ struct pasemi_desc init_desc; -+ struct pasemi_fnu_txring *txring; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ if (sidp == NULL || cri == NULL || sc == NULL) { -+ DPRINTF("%s,%d - EINVAL\n", __FILE__, __LINE__); -+ return -EINVAL; -+ } -+ for (c = cri; c != NULL; c = c->cri_next) { -+ if (ALG_IS_SIG(c->cri_alg)) { -+ if (macini) -+ return -EINVAL; -+ macini = c; -+ } else if (ALG_IS_CIPHER(c->cri_alg)) { -+ if (encini) -+ return -EINVAL; -+ encini = c; -+ } else { -+ DPRINTF("UNKNOWN c->cri_alg %d\n", c->cri_alg); -+ return -EINVAL; -+ } -+ } -+ if (encini == NULL && macini == NULL) -+ return -EINVAL; -+ if (encini) { -+ /* validate key length */ -+ switch (encini->cri_alg) { -+ case CRYPTO_DES_CBC: -+ if (encini->cri_klen != 64) -+ return -EINVAL; -+ ccmd = DMA_CALGO_DES; -+ break; -+ case CRYPTO_3DES_CBC: -+ if (encini->cri_klen != 192) -+ return -EINVAL; -+ ccmd = DMA_CALGO_3DES; -+ break; -+ case CRYPTO_AES_CBC: -+ if (encini->cri_klen != 128 && -+ encini->cri_klen != 192 && -+ encini->cri_klen != 256) -+ return -EINVAL; -+ ccmd = DMA_CALGO_AES; -+ break; -+ case CRYPTO_ARC4: -+ if (encini->cri_klen != 128) -+ return -EINVAL; -+ ccmd = DMA_CALGO_ARC; -+ break; -+ default: -+ DPRINTF("UNKNOWN encini->cri_alg %d\n", -+ encini->cri_alg); -+ return -EINVAL; -+ } -+ } -+ -+ if (macini) { -+ switch (macini->cri_alg) { -+ case CRYPTO_MD5: -+ case CRYPTO_MD5_HMAC: -+ blksz = 16; -+ break; -+ case CRYPTO_SHA1: -+ case CRYPTO_SHA1_HMAC: -+ blksz = 20; -+ break; -+ default: -+ DPRINTF("UNKNOWN macini->cri_alg %d\n", -+ macini->cri_alg); -+ return -EINVAL; -+ } -+ if (((macini->cri_klen + 7) / 8) > blksz) { -+ DPRINTF("key length %d bigger than blksize %d not supported\n", -+ ((macini->cri_klen + 7) / 8), blksz); -+ return -EINVAL; -+ } -+ } -+ -+ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { -+ if (sc->sc_sessions[sesn] == NULL) { -+ sc->sc_sessions[sesn] = (struct pasemi_session *) -+ kzalloc(sizeof(struct pasemi_session), GFP_ATOMIC); -+ ses = sc->sc_sessions[sesn]; -+ break; -+ } else if (sc->sc_sessions[sesn]->used == 0) { -+ ses = sc->sc_sessions[sesn]; -+ break; -+ } -+ } -+ -+ if (ses == NULL) { -+ sespp = (struct pasemi_session **) -+ kzalloc(sc->sc_nsessions * 2 * -+ sizeof(struct pasemi_session *), GFP_ATOMIC); -+ if (sespp == NULL) -+ return -ENOMEM; -+ memcpy(sespp, sc->sc_sessions, -+ sc->sc_nsessions * sizeof(struct pasemi_session *)); -+ kfree(sc->sc_sessions); -+ sc->sc_sessions = sespp; -+ sesn = sc->sc_nsessions; -+ ses = sc->sc_sessions[sesn] = (struct pasemi_session *) -+ kzalloc(sizeof(struct pasemi_session), GFP_ATOMIC); -+ if (ses == NULL) -+ return -ENOMEM; -+ sc->sc_nsessions *= 2; -+ } -+ -+ ses->used = 1; -+ -+ ses->dma_addr = pci_map_single(sc->dma_pdev, (void *) ses->civ, -+ sizeof(struct pasemi_session), DMA_TO_DEVICE); -+ -+ /* enter the channel scheduler */ -+ spin_lock_irqsave(&sc->sc_chnlock, flags); -+ -+ /* ARC4 has to be processed by the even channel */ -+ if (encini && (encini->cri_alg == CRYPTO_ARC4)) -+ ses->chan = sc->sc_lastchn & ~1; -+ else -+ ses->chan = sc->sc_lastchn; -+ sc->sc_lastchn = (sc->sc_lastchn + 1) % sc->sc_num_channels; -+ -+ spin_unlock_irqrestore(&sc->sc_chnlock, flags); -+ -+ txring = &sc->tx[ses->chan]; -+ -+ if (encini) { -+ ses->ccmd = ccmd; -+ -+ /* get an IV */ -+ /* XXX may read fewer than requested */ -+ get_random_bytes(ses->civ, sizeof(ses->civ)); -+ -+ ses->keysz = (encini->cri_klen - 63) / 64; -+ memcpy(ses->key, encini->cri_key, (ses->keysz + 1) * 8); -+ -+ pasemi_desc_start(&init_desc, -+ XCT_CTRL_HDR(ses->chan, (encini && macini) ? 0x68 : 0x40, DMA_FN_CIV0)); -+ pasemi_desc_build(&init_desc, -+ XCT_FUN_SRC_PTR((encini && macini) ? 0x68 : 0x40, ses->dma_addr)); -+ } -+ if (macini) { -+ if (macini->cri_alg == CRYPTO_MD5_HMAC || -+ macini->cri_alg == CRYPTO_SHA1_HMAC) -+ memcpy(ses->hkey, macini->cri_key, blksz); -+ else { -+ /* Load initialization constants(RFC 1321, 3174) */ -+ ses->hiv[0] = 0x67452301efcdab89ULL; -+ ses->hiv[1] = 0x98badcfe10325476ULL; -+ ses->hiv[2] = 0xc3d2e1f000000000ULL; -+ } -+ ses->hseq = 0ULL; -+ } -+ -+ spin_lock_irqsave(&txring->fill_lock, flags); -+ -+ if (((txring->next_to_fill + pasemi_desc_size(&init_desc)) - -+ txring->next_to_clean) > TX_RING_SIZE) { -+ spin_unlock_irqrestore(&txring->fill_lock, flags); -+ return ERESTART; -+ } -+ -+ if (encini) { -+ pasemi_ring_add_desc(txring, &init_desc, NULL); -+ pasemi_ring_incr(sc, ses->chan, -+ pasemi_desc_size(&init_desc)); -+ } -+ -+ txring->sesn = sesn; -+ spin_unlock_irqrestore(&txring->fill_lock, flags); -+ -+ *sidp = PASEMI_SID(sesn); -+ return 0; -+} -+ -+/* -+ * Deallocate a session. -+ */ -+static int -+pasemi_freesession(device_t dev, u_int64_t tid) -+{ -+ struct pasemi_softc *sc = device_get_softc(dev); -+ int session; -+ u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (sc == NULL) -+ return -EINVAL; -+ session = PASEMI_SESSION(sid); -+ if (session >= sc->sc_nsessions || !sc->sc_sessions[session]) -+ return -EINVAL; -+ -+ pci_unmap_single(sc->dma_pdev, -+ sc->sc_sessions[session]->dma_addr, -+ sizeof(struct pasemi_session), DMA_TO_DEVICE); -+ memset(sc->sc_sessions[session], 0, -+ sizeof(struct pasemi_session)); -+ -+ return 0; -+} -+ -+static int -+pasemi_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ -+ int err = 0, ivsize, srclen = 0, reinit = 0, reinit_size = 0, chsel; -+ struct pasemi_softc *sc = device_get_softc(dev); -+ struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; -+ caddr_t ivp; -+ struct pasemi_desc init_desc, work_desc; -+ struct pasemi_session *ses; -+ struct sk_buff *skb; -+ struct uio *uiop; -+ unsigned long flags; -+ struct pasemi_fnu_txring *txring; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (crp == NULL || crp->crp_callback == NULL || sc == NULL) -+ return -EINVAL; -+ -+ crp->crp_etype = 0; -+ if (PASEMI_SESSION(crp->crp_sid) >= sc->sc_nsessions) -+ return -EINVAL; -+ -+ ses = sc->sc_sessions[PASEMI_SESSION(crp->crp_sid)]; -+ -+ crd1 = crp->crp_desc; -+ if (crd1 == NULL) { -+ err = -EINVAL; -+ goto errout; -+ } -+ crd2 = crd1->crd_next; -+ -+ if (ALG_IS_SIG(crd1->crd_alg)) { -+ maccrd = crd1; -+ if (crd2 == NULL) -+ enccrd = NULL; -+ else if (ALG_IS_CIPHER(crd2->crd_alg) && -+ (crd2->crd_flags & CRD_F_ENCRYPT) == 0) -+ enccrd = crd2; -+ else -+ goto erralg; -+ } else if (ALG_IS_CIPHER(crd1->crd_alg)) { -+ enccrd = crd1; -+ if (crd2 == NULL) -+ maccrd = NULL; -+ else if (ALG_IS_SIG(crd2->crd_alg) && -+ (crd1->crd_flags & CRD_F_ENCRYPT)) -+ maccrd = crd2; -+ else -+ goto erralg; -+ } else -+ goto erralg; -+ -+ chsel = ses->chan; -+ -+ txring = &sc->tx[chsel]; -+ -+ if (enccrd && !maccrd) { -+ if (enccrd->crd_alg == CRYPTO_ARC4) -+ reinit = 1; -+ reinit_size = 0x40; -+ srclen = crp->crp_ilen; -+ -+ pasemi_desc_start(&work_desc, XCT_FUN_O | XCT_FUN_I -+ | XCT_FUN_FUN(chsel)); -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) -+ pasemi_desc_hdr(&work_desc, XCT_FUN_CRM_ENC); -+ else -+ pasemi_desc_hdr(&work_desc, XCT_FUN_CRM_DEC); -+ } else if (enccrd && maccrd) { -+ if (enccrd->crd_alg == CRYPTO_ARC4) -+ reinit = 1; -+ reinit_size = 0x68; -+ -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) { -+ /* Encrypt -> Authenticate */ -+ pasemi_desc_start(&work_desc, XCT_FUN_O | XCT_FUN_I | XCT_FUN_CRM_ENC_SIG -+ | XCT_FUN_A | XCT_FUN_FUN(chsel)); -+ srclen = maccrd->crd_skip + maccrd->crd_len; -+ } else { -+ /* Authenticate -> Decrypt */ -+ pasemi_desc_start(&work_desc, XCT_FUN_O | XCT_FUN_I | XCT_FUN_CRM_SIG_DEC -+ | XCT_FUN_24BRES | XCT_FUN_FUN(chsel)); -+ pasemi_desc_build(&work_desc, 0); -+ pasemi_desc_build(&work_desc, 0); -+ pasemi_desc_build(&work_desc, 0); -+ work_desc.postop = PASEMI_CHECK_SIG; -+ srclen = crp->crp_ilen; -+ } -+ -+ pasemi_desc_hdr(&work_desc, XCT_FUN_SHL(maccrd->crd_skip / 4)); -+ pasemi_desc_hdr(&work_desc, XCT_FUN_CHL(enccrd->crd_skip - maccrd->crd_skip)); -+ } else if (!enccrd && maccrd) { -+ srclen = maccrd->crd_len; -+ -+ pasemi_desc_start(&init_desc, -+ XCT_CTRL_HDR(chsel, 0x58, DMA_FN_HKEY0)); -+ pasemi_desc_build(&init_desc, -+ XCT_FUN_SRC_PTR(0x58, ((struct pasemi_session *)ses->dma_addr)->hkey)); -+ -+ pasemi_desc_start(&work_desc, XCT_FUN_O | XCT_FUN_I | XCT_FUN_CRM_SIG -+ | XCT_FUN_A | XCT_FUN_FUN(chsel)); -+ } -+ -+ if (enccrd) { -+ switch (enccrd->crd_alg) { -+ case CRYPTO_3DES_CBC: -+ pasemi_desc_hdr(&work_desc, XCT_FUN_ALG_3DES | -+ XCT_FUN_BCM_CBC); -+ ivsize = sizeof(u64); -+ break; -+ case CRYPTO_DES_CBC: -+ pasemi_desc_hdr(&work_desc, XCT_FUN_ALG_DES | -+ XCT_FUN_BCM_CBC); -+ ivsize = sizeof(u64); -+ break; -+ case CRYPTO_AES_CBC: -+ pasemi_desc_hdr(&work_desc, XCT_FUN_ALG_AES | -+ XCT_FUN_BCM_CBC); -+ ivsize = 2 * sizeof(u64); -+ break; -+ case CRYPTO_ARC4: -+ pasemi_desc_hdr(&work_desc, XCT_FUN_ALG_ARC); -+ ivsize = 0; -+ break; -+ default: -+ printk(DRV_NAME ": unimplemented enccrd->crd_alg %d\n", -+ enccrd->crd_alg); -+ err = -EINVAL; -+ goto errout; -+ } -+ -+ ivp = (ivsize == sizeof(u64)) ? (caddr_t) &ses->civ[1] : (caddr_t) &ses->civ[0]; -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) { -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) -+ memcpy(ivp, enccrd->crd_iv, ivsize); -+ /* If IV is not present in the buffer already, it has to be copied there */ -+ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ enccrd->crd_inject, ivsize, ivp); -+ } else { -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) -+ /* IV is provided expicitly in descriptor */ -+ memcpy(ivp, enccrd->crd_iv, ivsize); -+ else -+ /* IV is provided in the packet */ -+ crypto_copydata(crp->crp_flags, crp->crp_buf, -+ enccrd->crd_inject, ivsize, -+ ivp); -+ } -+ } -+ -+ if (maccrd) { -+ switch (maccrd->crd_alg) { -+ case CRYPTO_MD5: -+ pasemi_desc_hdr(&work_desc, XCT_FUN_SIG_MD5 | -+ XCT_FUN_HSZ((crp->crp_ilen - maccrd->crd_inject) / 4)); -+ break; -+ case CRYPTO_SHA1: -+ pasemi_desc_hdr(&work_desc, XCT_FUN_SIG_SHA1 | -+ XCT_FUN_HSZ((crp->crp_ilen - maccrd->crd_inject) / 4)); -+ break; -+ case CRYPTO_MD5_HMAC: -+ pasemi_desc_hdr(&work_desc, XCT_FUN_SIG_HMAC_MD5 | -+ XCT_FUN_HSZ((crp->crp_ilen - maccrd->crd_inject) / 4)); -+ break; -+ case CRYPTO_SHA1_HMAC: -+ pasemi_desc_hdr(&work_desc, XCT_FUN_SIG_HMAC_SHA1 | -+ XCT_FUN_HSZ((crp->crp_ilen - maccrd->crd_inject) / 4)); -+ break; -+ default: -+ printk(DRV_NAME ": unimplemented maccrd->crd_alg %d\n", -+ maccrd->crd_alg); -+ err = -EINVAL; -+ goto errout; -+ } -+ } -+ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ /* using SKB buffers */ -+ skb = (struct sk_buff *)crp->crp_buf; -+ if (skb_shinfo(skb)->nr_frags) { -+ printk(DRV_NAME ": skb frags unimplemented\n"); -+ err = -EINVAL; -+ goto errout; -+ } -+ pasemi_desc_build( -+ &work_desc, -+ XCT_FUN_DST_PTR(skb->len, pci_map_single( -+ sc->dma_pdev, skb->data, -+ skb->len, DMA_TO_DEVICE))); -+ pasemi_desc_build( -+ &work_desc, -+ XCT_FUN_SRC_PTR( -+ srclen, pci_map_single( -+ sc->dma_pdev, skb->data, -+ srclen, DMA_TO_DEVICE))); -+ pasemi_desc_hdr(&work_desc, XCT_FUN_LLEN(srclen)); -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ /* using IOV buffers */ -+ uiop = (struct uio *)crp->crp_buf; -+ if (uiop->uio_iovcnt > 1) { -+ printk(DRV_NAME ": iov frags unimplemented\n"); -+ err = -EINVAL; -+ goto errout; -+ } -+ -+ /* crp_olen is never set; always use crp_ilen */ -+ pasemi_desc_build( -+ &work_desc, -+ XCT_FUN_DST_PTR(crp->crp_ilen, pci_map_single( -+ sc->dma_pdev, -+ uiop->uio_iov->iov_base, -+ crp->crp_ilen, DMA_TO_DEVICE))); -+ pasemi_desc_hdr(&work_desc, XCT_FUN_LLEN(srclen)); -+ -+ pasemi_desc_build( -+ &work_desc, -+ XCT_FUN_SRC_PTR(srclen, pci_map_single( -+ sc->dma_pdev, -+ uiop->uio_iov->iov_base, -+ srclen, DMA_TO_DEVICE))); -+ } else { -+ /* using contig buffers */ -+ pasemi_desc_build( -+ &work_desc, -+ XCT_FUN_DST_PTR(crp->crp_ilen, pci_map_single( -+ sc->dma_pdev, -+ crp->crp_buf, -+ crp->crp_ilen, DMA_TO_DEVICE))); -+ pasemi_desc_build( -+ &work_desc, -+ XCT_FUN_SRC_PTR(srclen, pci_map_single( -+ sc->dma_pdev, -+ crp->crp_buf, srclen, -+ DMA_TO_DEVICE))); -+ pasemi_desc_hdr(&work_desc, XCT_FUN_LLEN(srclen)); -+ } -+ -+ spin_lock_irqsave(&txring->fill_lock, flags); -+ -+ if (txring->sesn != PASEMI_SESSION(crp->crp_sid)) { -+ txring->sesn = PASEMI_SESSION(crp->crp_sid); -+ reinit = 1; -+ } -+ -+ if (enccrd) { -+ pasemi_desc_start(&init_desc, -+ XCT_CTRL_HDR(chsel, reinit ? reinit_size : 0x10, DMA_FN_CIV0)); -+ pasemi_desc_build(&init_desc, -+ XCT_FUN_SRC_PTR(reinit ? reinit_size : 0x10, ses->dma_addr)); -+ } -+ -+ if (((txring->next_to_fill + pasemi_desc_size(&init_desc) + -+ pasemi_desc_size(&work_desc)) - -+ txring->next_to_clean) > TX_RING_SIZE) { -+ spin_unlock_irqrestore(&txring->fill_lock, flags); -+ err = ERESTART; -+ goto errout; -+ } -+ -+ pasemi_ring_add_desc(txring, &init_desc, NULL); -+ pasemi_ring_add_desc(txring, &work_desc, crp); -+ -+ pasemi_ring_incr(sc, chsel, -+ pasemi_desc_size(&init_desc) + -+ pasemi_desc_size(&work_desc)); -+ -+ spin_unlock_irqrestore(&txring->fill_lock, flags); -+ -+ mod_timer(&txring->crypto_timer, jiffies + TIMER_INTERVAL); -+ -+ return 0; -+ -+erralg: -+ printk(DRV_NAME ": unsupported algorithm or algorithm order alg1 %d alg2 %d\n", -+ crd1->crd_alg, crd2->crd_alg); -+ err = -EINVAL; -+ -+errout: -+ if (err != ERESTART) { -+ crp->crp_etype = err; -+ crypto_done(crp); -+ } -+ return err; -+} -+ -+static int pasemi_clean_tx(struct pasemi_softc *sc, int chan) -+{ -+ int i, j, ring_idx; -+ struct pasemi_fnu_txring *ring = &sc->tx[chan]; -+ u16 delta_cnt; -+ int flags, loops = 10; -+ int desc_size; -+ struct cryptop *crp; -+ -+ spin_lock_irqsave(&ring->clean_lock, flags); -+ -+ while ((delta_cnt = (dma_status->tx_sta[sc->base_chan + chan] -+ & PAS_STATUS_PCNT_M) - ring->total_pktcnt) -+ && loops--) { -+ -+ for (i = 0; i < delta_cnt; i++) { -+ desc_size = TX_DESC_INFO(ring, ring->next_to_clean).desc_size; -+ crp = TX_DESC_INFO(ring, ring->next_to_clean).cf_crp; -+ if (crp) { -+ ring_idx = 2 * (ring->next_to_clean & (TX_RING_SIZE-1)); -+ if (TX_DESC_INFO(ring, ring->next_to_clean).desc_postop & PASEMI_CHECK_SIG) { -+ /* Need to make sure signature matched, -+ * if not - return error */ -+ if (!(ring->desc[ring_idx + 1] & (1ULL << 63))) -+ crp->crp_etype = -EINVAL; -+ } -+ crypto_done(TX_DESC_INFO(ring, -+ ring->next_to_clean).cf_crp); -+ TX_DESC_INFO(ring, ring->next_to_clean).cf_crp = NULL; -+ pci_unmap_single( -+ sc->dma_pdev, -+ XCT_PTR_ADDR_LEN(ring->desc[ring_idx + 1]), -+ PCI_DMA_TODEVICE); -+ -+ ring->desc[ring_idx] = ring->desc[ring_idx + 1] = 0; -+ -+ ring->next_to_clean++; -+ for (j = 1; j < desc_size; j++) { -+ ring_idx = 2 * -+ (ring->next_to_clean & -+ (TX_RING_SIZE-1)); -+ pci_unmap_single( -+ sc->dma_pdev, -+ XCT_PTR_ADDR_LEN(ring->desc[ring_idx]), -+ PCI_DMA_TODEVICE); -+ if (ring->desc[ring_idx + 1]) -+ pci_unmap_single( -+ sc->dma_pdev, -+ XCT_PTR_ADDR_LEN( -+ ring->desc[ -+ ring_idx + 1]), -+ PCI_DMA_TODEVICE); -+ ring->desc[ring_idx] = -+ ring->desc[ring_idx + 1] = 0; -+ ring->next_to_clean++; -+ } -+ } else { -+ for (j = 0; j < desc_size; j++) { -+ ring_idx = 2 * (ring->next_to_clean & (TX_RING_SIZE-1)); -+ ring->desc[ring_idx] = -+ ring->desc[ring_idx + 1] = 0; -+ ring->next_to_clean++; -+ } -+ } -+ } -+ -+ ring->total_pktcnt += delta_cnt; -+ } -+ spin_unlock_irqrestore(&ring->clean_lock, flags); -+ -+ return 0; -+} -+ -+static void sweepup_tx(struct pasemi_softc *sc) -+{ -+ int i; -+ -+ for (i = 0; i < sc->sc_num_channels; i++) -+ pasemi_clean_tx(sc, i); -+} -+ -+static irqreturn_t pasemi_intr(int irq, void *arg, struct pt_regs *regs) -+{ -+ struct pasemi_softc *sc = arg; -+ unsigned int reg; -+ int chan = irq - sc->base_irq; -+ int chan_index = sc->base_chan + chan; -+ u64 stat = dma_status->tx_sta[chan_index]; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (!(stat & PAS_STATUS_CAUSE_M)) -+ return IRQ_NONE; -+ -+ pasemi_clean_tx(sc, chan); -+ -+ stat = dma_status->tx_sta[chan_index]; -+ -+ reg = PAS_IOB_DMA_TXCH_RESET_PINTC | -+ PAS_IOB_DMA_TXCH_RESET_PCNT(sc->tx[chan].total_pktcnt); -+ -+ if (stat & PAS_STATUS_SOFT) -+ reg |= PAS_IOB_DMA_RXCH_RESET_SINTC; -+ -+ out_le32(sc->iob_regs + PAS_IOB_DMA_TXCH_RESET(chan_index), reg); -+ -+ -+ return IRQ_HANDLED; -+} -+ -+static int pasemi_dma_setup_tx_resources(struct pasemi_softc *sc, int chan) -+{ -+ u32 val; -+ int chan_index = chan + sc->base_chan; -+ int ret; -+ struct pasemi_fnu_txring *ring; -+ -+ ring = &sc->tx[chan]; -+ -+ spin_lock_init(&ring->fill_lock); -+ spin_lock_init(&ring->clean_lock); -+ -+ ring->desc_info = kzalloc(sizeof(struct pasemi_desc_info) * -+ TX_RING_SIZE, GFP_KERNEL); -+ if (!ring->desc_info) -+ return -ENOMEM; -+ -+ /* Allocate descriptors */ -+ ring->desc = dma_alloc_coherent(&sc->dma_pdev->dev, -+ TX_RING_SIZE * -+ 2 * sizeof(u64), -+ &ring->dma, GFP_KERNEL); -+ if (!ring->desc) -+ return -ENOMEM; -+ -+ memset((void *) ring->desc, 0, TX_RING_SIZE * 2 * sizeof(u64)); -+ -+ out_le32(sc->iob_regs + PAS_IOB_DMA_TXCH_RESET(chan_index), 0x30); -+ -+ ring->total_pktcnt = 0; -+ -+ out_le32(sc->dma_regs + PAS_DMA_TXCHAN_BASEL(chan_index), -+ PAS_DMA_TXCHAN_BASEL_BRBL(ring->dma)); -+ -+ val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->dma >> 32); -+ val |= PAS_DMA_TXCHAN_BASEU_SIZ(TX_RING_SIZE >> 2); -+ -+ out_le32(sc->dma_regs + PAS_DMA_TXCHAN_BASEU(chan_index), val); -+ -+ out_le32(sc->dma_regs + PAS_DMA_TXCHAN_CFG(chan_index), -+ PAS_DMA_TXCHAN_CFG_TY_FUNC | -+ PAS_DMA_TXCHAN_CFG_TATTR(chan) | -+ PAS_DMA_TXCHAN_CFG_WT(2)); -+ -+ /* enable tx channel */ -+ out_le32(sc->dma_regs + -+ PAS_DMA_TXCHAN_TCMDSTA(chan_index), -+ PAS_DMA_TXCHAN_TCMDSTA_EN); -+ -+ out_le32(sc->iob_regs + PAS_IOB_DMA_TXCH_CFG(chan_index), -+ PAS_IOB_DMA_TXCH_CFG_CNTTH(1000)); -+ -+ ring->next_to_fill = 0; -+ ring->next_to_clean = 0; -+ -+ snprintf(ring->irq_name, sizeof(ring->irq_name), -+ "%s%d", "crypto", chan); -+ -+ ring->irq = irq_create_mapping(NULL, sc->base_irq + chan); -+ ret = request_irq(ring->irq, (irq_handler_t) -+ pasemi_intr, IRQF_DISABLED, ring->irq_name, sc); -+ if (ret) { -+ printk(KERN_ERR DRV_NAME ": failed to hook irq %d ret %d\n", -+ ring->irq, ret); -+ ring->irq = -1; -+ return ret; -+ } -+ -+ setup_timer(&ring->crypto_timer, (void *) sweepup_tx, (unsigned long) sc); -+ -+ return 0; -+} -+ -+static device_method_t pasemi_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, pasemi_newsession), -+ DEVMETHOD(cryptodev_freesession, pasemi_freesession), -+ DEVMETHOD(cryptodev_process, pasemi_process), -+}; -+ -+/* Set up the crypto device structure, private data, -+ * and anything else we need before we start */ -+ -+static int __devinit -+pasemi_dma_probe(struct pci_dev *pdev, const struct pci_device_id *ent) -+{ -+ struct pasemi_softc *sc; -+ int ret, i; -+ -+ DPRINTF(KERN_ERR "%s()\n", __FUNCTION__); -+ -+ sc = kzalloc(sizeof(*sc), GFP_KERNEL); -+ if (!sc) -+ return -ENOMEM; -+ -+ softc_device_init(sc, DRV_NAME, 1, pasemi_methods); -+ -+ pci_set_drvdata(pdev, sc); -+ -+ spin_lock_init(&sc->sc_chnlock); -+ -+ sc->sc_sessions = (struct pasemi_session **) -+ kzalloc(PASEMI_INITIAL_SESSIONS * -+ sizeof(struct pasemi_session *), GFP_ATOMIC); -+ if (sc->sc_sessions == NULL) { -+ ret = -ENOMEM; -+ goto out; -+ } -+ -+ sc->sc_nsessions = PASEMI_INITIAL_SESSIONS; -+ sc->sc_lastchn = 0; -+ sc->base_irq = pdev->irq + 6; -+ sc->base_chan = 6; -+ sc->sc_cid = -1; -+ sc->dma_pdev = pdev; -+ -+ sc->iob_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL); -+ if (!sc->iob_pdev) { -+ dev_err(&pdev->dev, "Can't find I/O Bridge\n"); -+ ret = -ENODEV; -+ goto out; -+ } -+ -+ /* This is hardcoded and ugly, but we have some firmware versions -+ * who don't provide the register space in the device tree. Luckily -+ * they are at well-known locations so we can just do the math here. -+ */ -+ sc->dma_regs = -+ ioremap(0xe0000000 + (sc->dma_pdev->devfn << 12), 0x2000); -+ sc->iob_regs = -+ ioremap(0xe0000000 + (sc->iob_pdev->devfn << 12), 0x2000); -+ if (!sc->dma_regs || !sc->iob_regs) { -+ dev_err(&pdev->dev, "Can't map registers\n"); -+ ret = -ENODEV; -+ goto out; -+ } -+ -+ dma_status = __ioremap(0xfd800000, 0x1000, 0); -+ if (!dma_status) { -+ ret = -ENODEV; -+ dev_err(&pdev->dev, "Can't map dmastatus space\n"); -+ goto out; -+ } -+ -+ sc->tx = (struct pasemi_fnu_txring *) -+ kzalloc(sizeof(struct pasemi_fnu_txring) -+ * 8, GFP_KERNEL); -+ if (!sc->tx) { -+ ret = -ENOMEM; -+ goto out; -+ } -+ -+ /* Initialize the h/w */ -+ out_le32(sc->dma_regs + PAS_DMA_COM_CFG, -+ (in_le32(sc->dma_regs + PAS_DMA_COM_CFG) | -+ PAS_DMA_COM_CFG_FWF)); -+ out_le32(sc->dma_regs + PAS_DMA_COM_TXCMD, PAS_DMA_COM_TXCMD_EN); -+ -+ for (i = 0; i < PASEMI_FNU_CHANNELS; i++) { -+ sc->sc_num_channels++; -+ ret = pasemi_dma_setup_tx_resources(sc, i); -+ if (ret) -+ goto out; -+ } -+ -+ sc->sc_cid = crypto_get_driverid(softc_get_device(sc), -+ CRYPTOCAP_F_HARDWARE); -+ if (sc->sc_cid < 0) { -+ printk(KERN_ERR DRV_NAME ": could not get crypto driver id\n"); -+ ret = -ENXIO; -+ goto out; -+ } -+ -+ /* register algorithms with the framework */ -+ printk(DRV_NAME ":"); -+ -+ crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); -+ -+ return 0; -+ -+out: -+ pasemi_dma_remove(pdev); -+ return ret; -+} -+ -+#define MAX_RETRIES 5000 -+ -+static void pasemi_free_tx_resources(struct pasemi_softc *sc, int chan) -+{ -+ struct pasemi_fnu_txring *ring = &sc->tx[chan]; -+ int chan_index = chan + sc->base_chan; -+ int retries; -+ u32 stat; -+ -+ /* Stop the channel */ -+ out_le32(sc->dma_regs + -+ PAS_DMA_TXCHAN_TCMDSTA(chan_index), -+ PAS_DMA_TXCHAN_TCMDSTA_ST); -+ -+ for (retries = 0; retries < MAX_RETRIES; retries++) { -+ stat = in_le32(sc->dma_regs + -+ PAS_DMA_TXCHAN_TCMDSTA(chan_index)); -+ if (!(stat & PAS_DMA_TXCHAN_TCMDSTA_ACT)) -+ break; -+ cond_resched(); -+ } -+ -+ if (stat & PAS_DMA_TXCHAN_TCMDSTA_ACT) -+ dev_err(&sc->dma_pdev->dev, "Failed to stop tx channel %d\n", -+ chan_index); -+ -+ /* Disable the channel */ -+ out_le32(sc->dma_regs + -+ PAS_DMA_TXCHAN_TCMDSTA(chan_index), -+ 0); -+ -+ if (ring->desc_info) -+ kfree((void *) ring->desc_info); -+ if (ring->desc) -+ dma_free_coherent(&sc->dma_pdev->dev, -+ TX_RING_SIZE * -+ 2 * sizeof(u64), -+ (void *) ring->desc, ring->dma); -+ if (ring->irq != -1) -+ free_irq(ring->irq, sc); -+ -+ del_timer(&ring->crypto_timer); -+} -+ -+static void __devexit pasemi_dma_remove(struct pci_dev *pdev) -+{ -+ struct pasemi_softc *sc = pci_get_drvdata(pdev); -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (sc->sc_cid >= 0) { -+ crypto_unregister_all(sc->sc_cid); -+ } -+ -+ if (sc->tx) { -+ for (i = 0; i < sc->sc_num_channels; i++) -+ pasemi_free_tx_resources(sc, i); -+ -+ kfree(sc->tx); -+ } -+ if (sc->sc_sessions) { -+ for (i = 0; i < sc->sc_nsessions; i++) -+ kfree(sc->sc_sessions[i]); -+ kfree(sc->sc_sessions); -+ } -+ if (sc->iob_pdev) -+ pci_dev_put(sc->iob_pdev); -+ if (sc->dma_regs) -+ iounmap(sc->dma_regs); -+ if (sc->iob_regs) -+ iounmap(sc->iob_regs); -+ kfree(sc); -+} -+ -+static struct pci_device_id pasemi_dma_pci_tbl[] = { -+ { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa007) }, -+}; -+ -+MODULE_DEVICE_TABLE(pci, pasemi_dma_pci_tbl); -+ -+static struct pci_driver pasemi_dma_driver = { -+ .name = "pasemi_dma", -+ .id_table = pasemi_dma_pci_tbl, -+ .probe = pasemi_dma_probe, -+ .remove = __devexit_p(pasemi_dma_remove), -+}; -+ -+static void __exit pasemi_dma_cleanup_module(void) -+{ -+ pci_unregister_driver(&pasemi_dma_driver); -+ __iounmap(dma_status); -+ dma_status = NULL; -+} -+ -+int pasemi_dma_init_module(void) -+{ -+ return pci_register_driver(&pasemi_dma_driver); -+} -+ -+module_init(pasemi_dma_init_module); -+module_exit(pasemi_dma_cleanup_module); -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_AUTHOR("Egor Martovetsky egor@pasemi.com"); -+MODULE_DESCRIPTION("OCF driver for PA Semi PWRficient DMA Crypto Engine"); -diff -Nur linux-2.6.36.orig/crypto/ocf/pasemi/pasemi_fnu.h linux-2.6.36/crypto/ocf/pasemi/pasemi_fnu.h ---- linux-2.6.36.orig/crypto/ocf/pasemi/pasemi_fnu.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/pasemi/pasemi_fnu.h 2010-11-09 20:28:12.612495424 +0100 -@@ -0,0 +1,410 @@ -+/* -+ * Copyright (C) 2007 PA Semi, Inc -+ * -+ * Driver for the PA Semi PWRficient DMA Crypto Engine, soft state and -+ * hardware register layouts. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef PASEMI_FNU_H -+#define PASEMI_FNU_H -+ -+#include -+ -+#define PASEMI_SESSION(sid) ((sid) & 0xffffffff) -+#define PASEMI_SID(sesn) ((sesn) & 0xffffffff) -+#define DPRINTF(a...) if (debug) { printk(DRV_NAME ": " a); } -+ -+/* Must be a power of two */ -+#define RX_RING_SIZE 512 -+#define TX_RING_SIZE 512 -+#define TX_DESC(ring, num) ((ring)->desc[2 * (num & (TX_RING_SIZE-1))]) -+#define TX_DESC_INFO(ring, num) ((ring)->desc_info[(num) & (TX_RING_SIZE-1)]) -+#define MAX_DESC_SIZE 8 -+#define PASEMI_INITIAL_SESSIONS 10 -+#define PASEMI_FNU_CHANNELS 8 -+ -+/* DMA descriptor */ -+struct pasemi_desc { -+ u64 quad[2*MAX_DESC_SIZE]; -+ int quad_cnt; -+ int size; -+ int postop; -+}; -+ -+/* -+ * Holds per descriptor data -+ */ -+struct pasemi_desc_info { -+ int desc_size; -+ int desc_postop; -+#define PASEMI_CHECK_SIG 0x1 -+ -+ struct cryptop *cf_crp; -+}; -+ -+/* -+ * Holds per channel data -+ */ -+struct pasemi_fnu_txring { -+ volatile u64 *desc; -+ volatile struct -+ pasemi_desc_info *desc_info; -+ dma_addr_t dma; -+ struct timer_list crypto_timer; -+ spinlock_t fill_lock; -+ spinlock_t clean_lock; -+ unsigned int next_to_fill; -+ unsigned int next_to_clean; -+ u16 total_pktcnt; -+ int irq; -+ int sesn; -+ char irq_name[10]; -+}; -+ -+/* -+ * Holds data specific to a single pasemi device. -+ */ -+struct pasemi_softc { -+ softc_device_decl sc_cdev; -+ struct pci_dev *dma_pdev; /* device backpointer */ -+ struct pci_dev *iob_pdev; /* device backpointer */ -+ void __iomem *dma_regs; -+ void __iomem *iob_regs; -+ int base_irq; -+ int base_chan; -+ int32_t sc_cid; /* crypto tag */ -+ int sc_nsessions; -+ struct pasemi_session **sc_sessions; -+ int sc_num_channels;/* number of crypto channels */ -+ -+ /* pointer to the array of txring datastructures, one txring per channel */ -+ struct pasemi_fnu_txring *tx; -+ -+ /* -+ * mutual exclusion for the channel scheduler -+ */ -+ spinlock_t sc_chnlock; -+ /* last channel used, for now use round-robin to allocate channels */ -+ int sc_lastchn; -+}; -+ -+struct pasemi_session { -+ u64 civ[2]; -+ u64 keysz; -+ u64 key[4]; -+ u64 ccmd; -+ u64 hkey[4]; -+ u64 hseq; -+ u64 giv[2]; -+ u64 hiv[4]; -+ -+ int used; -+ dma_addr_t dma_addr; -+ int chan; -+}; -+ -+/* status register layout in IOB region, at 0xfd800000 */ -+struct pasdma_status { -+ u64 rx_sta[64]; -+ u64 tx_sta[20]; -+}; -+ -+#define ALG_IS_CIPHER(alg) ((alg == CRYPTO_DES_CBC) || \ -+ (alg == CRYPTO_3DES_CBC) || \ -+ (alg == CRYPTO_AES_CBC) || \ -+ (alg == CRYPTO_ARC4) || \ -+ (alg == CRYPTO_NULL_CBC)) -+ -+#define ALG_IS_SIG(alg) ((alg == CRYPTO_MD5) || \ -+ (alg == CRYPTO_MD5_HMAC) || \ -+ (alg == CRYPTO_SHA1) || \ -+ (alg == CRYPTO_SHA1_HMAC) || \ -+ (alg == CRYPTO_NULL_HMAC)) -+ -+enum { -+ PAS_DMA_COM_TXCMD = 0x100, /* Transmit Command Register */ -+ PAS_DMA_COM_TXSTA = 0x104, /* Transmit Status Register */ -+ PAS_DMA_COM_RXCMD = 0x108, /* Receive Command Register */ -+ PAS_DMA_COM_RXSTA = 0x10c, /* Receive Status Register */ -+ PAS_DMA_COM_CFG = 0x114, /* DMA Configuration Register */ -+}; -+ -+/* All these registers live in the PCI configuration space for the DMA PCI -+ * device. Use the normal PCI config access functions for them. -+ */ -+ -+#define PAS_DMA_COM_CFG_FWF 0x18000000 -+ -+#define PAS_DMA_COM_TXCMD_EN 0x00000001 /* enable */ -+#define PAS_DMA_COM_TXSTA_ACT 0x00000001 /* active */ -+#define PAS_DMA_COM_RXCMD_EN 0x00000001 /* enable */ -+#define PAS_DMA_COM_RXSTA_ACT 0x00000001 /* active */ -+ -+#define _PAS_DMA_TXCHAN_STRIDE 0x20 /* Size per channel */ -+#define _PAS_DMA_TXCHAN_TCMDSTA 0x300 /* Command / Status */ -+#define _PAS_DMA_TXCHAN_CFG 0x304 /* Configuration */ -+#define _PAS_DMA_TXCHAN_DSCRBU 0x308 /* Descriptor BU Allocation */ -+#define _PAS_DMA_TXCHAN_INCR 0x310 /* Descriptor increment */ -+#define _PAS_DMA_TXCHAN_CNT 0x314 /* Descriptor count/offset */ -+#define _PAS_DMA_TXCHAN_BASEL 0x318 /* Descriptor ring base (low) */ -+#define _PAS_DMA_TXCHAN_BASEU 0x31c /* (high) */ -+#define PAS_DMA_TXCHAN_TCMDSTA(c) (0x300+(c)*_PAS_DMA_TXCHAN_STRIDE) -+#define PAS_DMA_TXCHAN_TCMDSTA_EN 0x00000001 /* Enabled */ -+#define PAS_DMA_TXCHAN_TCMDSTA_ST 0x00000002 /* Stop interface */ -+#define PAS_DMA_TXCHAN_TCMDSTA_ACT 0x00010000 /* Active */ -+#define PAS_DMA_TXCHAN_CFG(c) (0x304+(c)*_PAS_DMA_TXCHAN_STRIDE) -+#define PAS_DMA_TXCHAN_CFG_TY_FUNC 0x00000002 /* Type = interface */ -+#define PAS_DMA_TXCHAN_CFG_TY_IFACE 0x00000000 /* Type = interface */ -+#define PAS_DMA_TXCHAN_CFG_TATTR_M 0x0000003c -+#define PAS_DMA_TXCHAN_CFG_TATTR_S 2 -+#define PAS_DMA_TXCHAN_CFG_TATTR(x) (((x) << PAS_DMA_TXCHAN_CFG_TATTR_S) & \ -+ PAS_DMA_TXCHAN_CFG_TATTR_M) -+#define PAS_DMA_TXCHAN_CFG_WT_M 0x000001c0 -+#define PAS_DMA_TXCHAN_CFG_WT_S 6 -+#define PAS_DMA_TXCHAN_CFG_WT(x) (((x) << PAS_DMA_TXCHAN_CFG_WT_S) & \ -+ PAS_DMA_TXCHAN_CFG_WT_M) -+#define PAS_DMA_TXCHAN_CFG_LPSQ_FAST 0x00000400 -+#define PAS_DMA_TXCHAN_CFG_LPDQ_FAST 0x00000800 -+#define PAS_DMA_TXCHAN_CFG_CF 0x00001000 /* Clean first line */ -+#define PAS_DMA_TXCHAN_CFG_CL 0x00002000 /* Clean last line */ -+#define PAS_DMA_TXCHAN_CFG_UP 0x00004000 /* update tx descr when sent */ -+#define PAS_DMA_TXCHAN_INCR(c) (0x310+(c)*_PAS_DMA_TXCHAN_STRIDE) -+#define PAS_DMA_TXCHAN_BASEL(c) (0x318+(c)*_PAS_DMA_TXCHAN_STRIDE) -+#define PAS_DMA_TXCHAN_BASEL_BRBL_M 0xffffffc0 -+#define PAS_DMA_TXCHAN_BASEL_BRBL_S 0 -+#define PAS_DMA_TXCHAN_BASEL_BRBL(x) (((x) << PAS_DMA_TXCHAN_BASEL_BRBL_S) & \ -+ PAS_DMA_TXCHAN_BASEL_BRBL_M) -+#define PAS_DMA_TXCHAN_BASEU(c) (0x31c+(c)*_PAS_DMA_TXCHAN_STRIDE) -+#define PAS_DMA_TXCHAN_BASEU_BRBH_M 0x00000fff -+#define PAS_DMA_TXCHAN_BASEU_BRBH_S 0 -+#define PAS_DMA_TXCHAN_BASEU_BRBH(x) (((x) << PAS_DMA_TXCHAN_BASEU_BRBH_S) & \ -+ PAS_DMA_TXCHAN_BASEU_BRBH_M) -+/* # of cache lines worth of buffer ring */ -+#define PAS_DMA_TXCHAN_BASEU_SIZ_M 0x3fff0000 -+#define PAS_DMA_TXCHAN_BASEU_SIZ_S 16 /* 0 = 16K */ -+#define PAS_DMA_TXCHAN_BASEU_SIZ(x) (((x) << PAS_DMA_TXCHAN_BASEU_SIZ_S) & \ -+ PAS_DMA_TXCHAN_BASEU_SIZ_M) -+ -+#define PAS_STATUS_PCNT_M 0x000000000000ffffull -+#define PAS_STATUS_PCNT_S 0 -+#define PAS_STATUS_DCNT_M 0x00000000ffff0000ull -+#define PAS_STATUS_DCNT_S 16 -+#define PAS_STATUS_BPCNT_M 0x0000ffff00000000ull -+#define PAS_STATUS_BPCNT_S 32 -+#define PAS_STATUS_CAUSE_M 0xf000000000000000ull -+#define PAS_STATUS_TIMER 0x1000000000000000ull -+#define PAS_STATUS_ERROR 0x2000000000000000ull -+#define PAS_STATUS_SOFT 0x4000000000000000ull -+#define PAS_STATUS_INT 0x8000000000000000ull -+ -+#define PAS_IOB_DMA_RXCH_CFG(i) (0x1100 + (i)*4) -+#define PAS_IOB_DMA_RXCH_CFG_CNTTH_M 0x00000fff -+#define PAS_IOB_DMA_RXCH_CFG_CNTTH_S 0 -+#define PAS_IOB_DMA_RXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_RXCH_CFG_CNTTH_S) & \ -+ PAS_IOB_DMA_RXCH_CFG_CNTTH_M) -+#define PAS_IOB_DMA_TXCH_CFG(i) (0x1200 + (i)*4) -+#define PAS_IOB_DMA_TXCH_CFG_CNTTH_M 0x00000fff -+#define PAS_IOB_DMA_TXCH_CFG_CNTTH_S 0 -+#define PAS_IOB_DMA_TXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_TXCH_CFG_CNTTH_S) & \ -+ PAS_IOB_DMA_TXCH_CFG_CNTTH_M) -+#define PAS_IOB_DMA_RXCH_STAT(i) (0x1300 + (i)*4) -+#define PAS_IOB_DMA_RXCH_STAT_INTGEN 0x00001000 -+#define PAS_IOB_DMA_RXCH_STAT_CNTDEL_M 0x00000fff -+#define PAS_IOB_DMA_RXCH_STAT_CNTDEL_S 0 -+#define PAS_IOB_DMA_RXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_RXCH_STAT_CNTDEL_S) &\ -+ PAS_IOB_DMA_RXCH_STAT_CNTDEL_M) -+#define PAS_IOB_DMA_TXCH_STAT(i) (0x1400 + (i)*4) -+#define PAS_IOB_DMA_TXCH_STAT_INTGEN 0x00001000 -+#define PAS_IOB_DMA_TXCH_STAT_CNTDEL_M 0x00000fff -+#define PAS_IOB_DMA_TXCH_STAT_CNTDEL_S 0 -+#define PAS_IOB_DMA_TXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_TXCH_STAT_CNTDEL_S) &\ -+ PAS_IOB_DMA_TXCH_STAT_CNTDEL_M) -+#define PAS_IOB_DMA_RXCH_RESET(i) (0x1500 + (i)*4) -+#define PAS_IOB_DMA_RXCH_RESET_PCNT_M 0xffff0000 -+#define PAS_IOB_DMA_RXCH_RESET_PCNT_S 16 -+#define PAS_IOB_DMA_RXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_RXCH_RESET_PCNT_S) & \ -+ PAS_IOB_DMA_RXCH_RESET_PCNT_M) -+#define PAS_IOB_DMA_RXCH_RESET_PCNTRST 0x00000020 -+#define PAS_IOB_DMA_RXCH_RESET_DCNTRST 0x00000010 -+#define PAS_IOB_DMA_RXCH_RESET_TINTC 0x00000008 -+#define PAS_IOB_DMA_RXCH_RESET_DINTC 0x00000004 -+#define PAS_IOB_DMA_RXCH_RESET_SINTC 0x00000002 -+#define PAS_IOB_DMA_RXCH_RESET_PINTC 0x00000001 -+#define PAS_IOB_DMA_TXCH_RESET(i) (0x1600 + (i)*4) -+#define PAS_IOB_DMA_TXCH_RESET_PCNT_M 0xffff0000 -+#define PAS_IOB_DMA_TXCH_RESET_PCNT_S 16 -+#define PAS_IOB_DMA_TXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_TXCH_RESET_PCNT_S) & \ -+ PAS_IOB_DMA_TXCH_RESET_PCNT_M) -+#define PAS_IOB_DMA_TXCH_RESET_PCNTRST 0x00000020 -+#define PAS_IOB_DMA_TXCH_RESET_DCNTRST 0x00000010 -+#define PAS_IOB_DMA_TXCH_RESET_TINTC 0x00000008 -+#define PAS_IOB_DMA_TXCH_RESET_DINTC 0x00000004 -+#define PAS_IOB_DMA_TXCH_RESET_SINTC 0x00000002 -+#define PAS_IOB_DMA_TXCH_RESET_PINTC 0x00000001 -+ -+#define PAS_IOB_DMA_COM_TIMEOUTCFG 0x1700 -+#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M 0x00ffffff -+#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S 0 -+#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(x) (((x) << PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S) & \ -+ PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M) -+ -+/* Transmit descriptor fields */ -+#define XCT_MACTX_T 0x8000000000000000ull -+#define XCT_MACTX_ST 0x4000000000000000ull -+#define XCT_MACTX_NORES 0x0000000000000000ull -+#define XCT_MACTX_8BRES 0x1000000000000000ull -+#define XCT_MACTX_24BRES 0x2000000000000000ull -+#define XCT_MACTX_40BRES 0x3000000000000000ull -+#define XCT_MACTX_I 0x0800000000000000ull -+#define XCT_MACTX_O 0x0400000000000000ull -+#define XCT_MACTX_E 0x0200000000000000ull -+#define XCT_MACTX_VLAN_M 0x0180000000000000ull -+#define XCT_MACTX_VLAN_NOP 0x0000000000000000ull -+#define XCT_MACTX_VLAN_REMOVE 0x0080000000000000ull -+#define XCT_MACTX_VLAN_INSERT 0x0100000000000000ull -+#define XCT_MACTX_VLAN_REPLACE 0x0180000000000000ull -+#define XCT_MACTX_CRC_M 0x0060000000000000ull -+#define XCT_MACTX_CRC_NOP 0x0000000000000000ull -+#define XCT_MACTX_CRC_INSERT 0x0020000000000000ull -+#define XCT_MACTX_CRC_PAD 0x0040000000000000ull -+#define XCT_MACTX_CRC_REPLACE 0x0060000000000000ull -+#define XCT_MACTX_SS 0x0010000000000000ull -+#define XCT_MACTX_LLEN_M 0x00007fff00000000ull -+#define XCT_MACTX_LLEN_S 32ull -+#define XCT_MACTX_LLEN(x) ((((long)(x)) << XCT_MACTX_LLEN_S) & \ -+ XCT_MACTX_LLEN_M) -+#define XCT_MACTX_IPH_M 0x00000000f8000000ull -+#define XCT_MACTX_IPH_S 27ull -+#define XCT_MACTX_IPH(x) ((((long)(x)) << XCT_MACTX_IPH_S) & \ -+ XCT_MACTX_IPH_M) -+#define XCT_MACTX_IPO_M 0x0000000007c00000ull -+#define XCT_MACTX_IPO_S 22ull -+#define XCT_MACTX_IPO(x) ((((long)(x)) << XCT_MACTX_IPO_S) & \ -+ XCT_MACTX_IPO_M) -+#define XCT_MACTX_CSUM_M 0x0000000000000060ull -+#define XCT_MACTX_CSUM_NOP 0x0000000000000000ull -+#define XCT_MACTX_CSUM_TCP 0x0000000000000040ull -+#define XCT_MACTX_CSUM_UDP 0x0000000000000060ull -+#define XCT_MACTX_V6 0x0000000000000010ull -+#define XCT_MACTX_C 0x0000000000000004ull -+#define XCT_MACTX_AL2 0x0000000000000002ull -+ -+#define XCT_PTR_T 0x8000000000000000ull -+#define XCT_PTR_LEN_M 0x7ffff00000000000ull -+#define XCT_PTR_LEN_S 44 -+#define XCT_PTR_LEN(x) ((((long)(x)) << XCT_PTR_LEN_S) & \ -+ XCT_PTR_LEN_M) -+#define XCT_PTR_ADDR_M 0x00000fffffffffffull -+#define XCT_PTR_ADDR_S 0 -+#define XCT_PTR_ADDR(x) ((((long)(x)) << XCT_PTR_ADDR_S) & \ -+ XCT_PTR_ADDR_M) -+ -+/* Function descriptor fields */ -+#define XCT_FUN_T 0x8000000000000000ull -+#define XCT_FUN_ST 0x4000000000000000ull -+#define XCT_FUN_NORES 0x0000000000000000ull -+#define XCT_FUN_8BRES 0x1000000000000000ull -+#define XCT_FUN_24BRES 0x2000000000000000ull -+#define XCT_FUN_40BRES 0x3000000000000000ull -+#define XCT_FUN_I 0x0800000000000000ull -+#define XCT_FUN_O 0x0400000000000000ull -+#define XCT_FUN_E 0x0200000000000000ull -+#define XCT_FUN_FUN_S 54 -+#define XCT_FUN_FUN_M 0x01c0000000000000ull -+#define XCT_FUN_FUN(num) ((((long)(num)) << XCT_FUN_FUN_S) & \ -+ XCT_FUN_FUN_M) -+#define XCT_FUN_CRM_NOP 0x0000000000000000ull -+#define XCT_FUN_CRM_SIG 0x0008000000000000ull -+#define XCT_FUN_CRM_ENC 0x0010000000000000ull -+#define XCT_FUN_CRM_DEC 0x0018000000000000ull -+#define XCT_FUN_CRM_SIG_ENC 0x0020000000000000ull -+#define XCT_FUN_CRM_ENC_SIG 0x0028000000000000ull -+#define XCT_FUN_CRM_SIG_DEC 0x0030000000000000ull -+#define XCT_FUN_CRM_DEC_SIG 0x0038000000000000ull -+#define XCT_FUN_LLEN_M 0x0007ffff00000000ull -+#define XCT_FUN_LLEN_S 32ULL -+#define XCT_FUN_LLEN(x) ((((long)(x)) << XCT_FUN_LLEN_S) & \ -+ XCT_FUN_LLEN_M) -+#define XCT_FUN_SHL_M 0x00000000f8000000ull -+#define XCT_FUN_SHL_S 27ull -+#define XCT_FUN_SHL(x) ((((long)(x)) << XCT_FUN_SHL_S) & \ -+ XCT_FUN_SHL_M) -+#define XCT_FUN_CHL_M 0x0000000007c00000ull -+#define XCT_FUN_CHL_S 22ull -+#define XCT_FUN_CHL(x) ((((long)(x)) << XCT_FUN_CHL_S) & \ -+ XCT_FUN_CHL_M) -+#define XCT_FUN_HSZ_M 0x00000000003c0000ull -+#define XCT_FUN_HSZ_S 18ull -+#define XCT_FUN_HSZ(x) ((((long)(x)) << XCT_FUN_HSZ_S) & \ -+ XCT_FUN_HSZ_M) -+#define XCT_FUN_ALG_DES 0x0000000000000000ull -+#define XCT_FUN_ALG_3DES 0x0000000000008000ull -+#define XCT_FUN_ALG_AES 0x0000000000010000ull -+#define XCT_FUN_ALG_ARC 0x0000000000018000ull -+#define XCT_FUN_ALG_KASUMI 0x0000000000020000ull -+#define XCT_FUN_BCM_ECB 0x0000000000000000ull -+#define XCT_FUN_BCM_CBC 0x0000000000001000ull -+#define XCT_FUN_BCM_CFB 0x0000000000002000ull -+#define XCT_FUN_BCM_OFB 0x0000000000003000ull -+#define XCT_FUN_BCM_CNT 0x0000000000003800ull -+#define XCT_FUN_BCM_KAS_F8 0x0000000000002800ull -+#define XCT_FUN_BCM_KAS_F9 0x0000000000001800ull -+#define XCT_FUN_BCP_NO_PAD 0x0000000000000000ull -+#define XCT_FUN_BCP_ZRO 0x0000000000000200ull -+#define XCT_FUN_BCP_PL 0x0000000000000400ull -+#define XCT_FUN_BCP_INCR 0x0000000000000600ull -+#define XCT_FUN_SIG_MD5 (0ull << 4) -+#define XCT_FUN_SIG_SHA1 (2ull << 4) -+#define XCT_FUN_SIG_HMAC_MD5 (8ull << 4) -+#define XCT_FUN_SIG_HMAC_SHA1 (10ull << 4) -+#define XCT_FUN_A 0x0000000000000008ull -+#define XCT_FUN_C 0x0000000000000004ull -+#define XCT_FUN_AL2 0x0000000000000002ull -+#define XCT_FUN_SE 0x0000000000000001ull -+ -+#define XCT_FUN_SRC_PTR(len, addr) (XCT_PTR_LEN(len) | XCT_PTR_ADDR(addr)) -+#define XCT_FUN_DST_PTR(len, addr) (XCT_FUN_SRC_PTR(len, addr) | \ -+ 0x8000000000000000ull) -+ -+#define XCT_CTRL_HDR_FUN_NUM_M 0x01c0000000000000ull -+#define XCT_CTRL_HDR_FUN_NUM_S 54 -+#define XCT_CTRL_HDR_LEN_M 0x0007ffff00000000ull -+#define XCT_CTRL_HDR_LEN_S 32 -+#define XCT_CTRL_HDR_REG_M 0x00000000000000ffull -+#define XCT_CTRL_HDR_REG_S 0 -+ -+#define XCT_CTRL_HDR(funcN,len,reg) (0x9400000000000000ull | \ -+ ((((long)(funcN)) << XCT_CTRL_HDR_FUN_NUM_S) \ -+ & XCT_CTRL_HDR_FUN_NUM_M) | \ -+ ((((long)(len)) << \ -+ XCT_CTRL_HDR_LEN_S) & XCT_CTRL_HDR_LEN_M) | \ -+ ((((long)(reg)) << \ -+ XCT_CTRL_HDR_REG_S) & XCT_CTRL_HDR_REG_M)) -+ -+/* Function config command options */ -+#define DMA_CALGO_DES 0x00 -+#define DMA_CALGO_3DES 0x01 -+#define DMA_CALGO_AES 0x02 -+#define DMA_CALGO_ARC 0x03 -+ -+#define DMA_FN_CIV0 0x02 -+#define DMA_FN_CIV1 0x03 -+#define DMA_FN_HKEY0 0x0a -+ -+#define XCT_PTR_ADDR_LEN(ptr) ((ptr) & XCT_PTR_ADDR_M), \ -+ (((ptr) & XCT_PTR_LEN_M) >> XCT_PTR_LEN_S) -+ -+#endif /* PASEMI_FNU_H */ -diff -Nur linux-2.6.36.orig/crypto/ocf/random.c linux-2.6.36/crypto/ocf/random.c ---- linux-2.6.36.orig/crypto/ocf/random.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/random.c 2010-11-09 20:28:12.652495434 +0100 -@@ -0,0 +1,322 @@ -+/* -+ * A system independant way of adding entropy to the kernels pool -+ * this way the drivers can focus on the real work and we can take -+ * care of pushing it to the appropriate place in the kernel. -+ * -+ * This should be fast and callable from timers/interrupts -+ * -+ * Written by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * ALTERNATIVELY, provided that this notice is retained in full, this product -+ * may be distributed under the terms of the GNU General Public License (GPL), -+ * in which case the provisions of the GPL apply INSTEAD OF those given above. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ */ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#ifdef CONFIG_OCF_FIPS -+#include "rndtest.h" -+#endif -+ -+#ifndef HAS_RANDOM_INPUT_WAIT -+#error "Please do not enable OCF_RANDOMHARVEST unless you have applied patches" -+#endif -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) -+#include -+#define kill_proc(p,s,v) send_sig(s,find_task_by_vpid(p),0) -+#endif -+ -+/* -+ * a hack to access the debug levels from the crypto driver -+ */ -+extern int crypto_debug; -+#define debug crypto_debug -+ -+/* -+ * a list of all registered random providers -+ */ -+static LIST_HEAD(random_ops); -+static int started = 0; -+static int initted = 0; -+ -+struct random_op { -+ struct list_head random_list; -+ u_int32_t driverid; -+ int (*read_random)(void *arg, u_int32_t *buf, int len); -+ void *arg; -+}; -+ -+static int random_proc(void *arg); -+ -+static pid_t randomproc = (pid_t) -1; -+static spinlock_t random_lock; -+ -+/* -+ * just init the spin locks -+ */ -+static int -+crypto_random_init(void) -+{ -+ spin_lock_init(&random_lock); -+ initted = 1; -+ return(0); -+} -+ -+/* -+ * Add the given random reader to our list (if not present) -+ * and start the thread (if not already started) -+ * -+ * we have to assume that driver id is ok for now -+ */ -+int -+crypto_rregister( -+ u_int32_t driverid, -+ int (*read_random)(void *arg, u_int32_t *buf, int len), -+ void *arg) -+{ -+ unsigned long flags; -+ int ret = 0; -+ struct random_op *rops, *tmp; -+ -+ dprintk("%s,%d: %s(0x%x, %p, %p)\n", __FILE__, __LINE__, -+ __FUNCTION__, driverid, read_random, arg); -+ -+ if (!initted) -+ crypto_random_init(); -+ -+#if 0 -+ struct cryptocap *cap; -+ -+ cap = crypto_checkdriver(driverid); -+ if (!cap) -+ return EINVAL; -+#endif -+ -+ list_for_each_entry_safe(rops, tmp, &random_ops, random_list) { -+ if (rops->driverid == driverid && rops->read_random == read_random) -+ return EEXIST; -+ } -+ -+ rops = (struct random_op *) kmalloc(sizeof(*rops), GFP_KERNEL); -+ if (!rops) -+ return ENOMEM; -+ -+ rops->driverid = driverid; -+ rops->read_random = read_random; -+ rops->arg = arg; -+ -+ spin_lock_irqsave(&random_lock, flags); -+ list_add_tail(&rops->random_list, &random_ops); -+ if (!started) { -+ randomproc = kernel_thread(random_proc, NULL, CLONE_FS|CLONE_FILES); -+ if (randomproc < 0) { -+ ret = randomproc; -+ printk("crypto: crypto_rregister cannot start random thread; " -+ "error %d", ret); -+ } else -+ started = 1; -+ } -+ spin_unlock_irqrestore(&random_lock, flags); -+ -+ return ret; -+} -+EXPORT_SYMBOL(crypto_rregister); -+ -+int -+crypto_runregister_all(u_int32_t driverid) -+{ -+ struct random_op *rops, *tmp; -+ unsigned long flags; -+ -+ dprintk("%s,%d: %s(0x%x)\n", __FILE__, __LINE__, __FUNCTION__, driverid); -+ -+ list_for_each_entry_safe(rops, tmp, &random_ops, random_list) { -+ if (rops->driverid == driverid) { -+ list_del(&rops->random_list); -+ kfree(rops); -+ } -+ } -+ -+ spin_lock_irqsave(&random_lock, flags); -+ if (list_empty(&random_ops) && started) -+ kill_proc(randomproc, SIGKILL, 1); -+ spin_unlock_irqrestore(&random_lock, flags); -+ return(0); -+} -+EXPORT_SYMBOL(crypto_runregister_all); -+ -+/* -+ * while we can add entropy to random.c continue to read random data from -+ * the drivers and push it to random. -+ */ -+static int -+random_proc(void *arg) -+{ -+ int n; -+ int wantcnt; -+ int bufcnt = 0; -+ int retval = 0; -+ int *buf = NULL; -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ daemonize(); -+ spin_lock_irq(¤t->sigmask_lock); -+ sigemptyset(¤t->blocked); -+ recalc_sigpending(current); -+ spin_unlock_irq(¤t->sigmask_lock); -+ sprintf(current->comm, "ocf-random"); -+#else -+ daemonize("ocf-random"); -+ allow_signal(SIGKILL); -+#endif -+ -+ (void) get_fs(); -+ set_fs(get_ds()); -+ -+#ifdef CONFIG_OCF_FIPS -+#define NUM_INT (RNDTEST_NBYTES/sizeof(int)) -+#else -+#define NUM_INT 32 -+#endif -+ -+ /* -+ * some devices can transferr their RNG data direct into memory, -+ * so make sure it is device friendly -+ */ -+ buf = kmalloc(NUM_INT * sizeof(int), GFP_DMA); -+ if (NULL == buf) { -+ printk("crypto: RNG could not allocate memory\n"); -+ retval = -ENOMEM; -+ goto bad_alloc; -+ } -+ -+ wantcnt = NUM_INT; /* start by adding some entropy */ -+ -+ /* -+ * its possible due to errors or driver removal that we no longer -+ * have anything to do, if so exit or we will consume all the CPU -+ * doing nothing -+ */ -+ while (!list_empty(&random_ops)) { -+ struct random_op *rops, *tmp; -+ -+#ifdef CONFIG_OCF_FIPS -+ if (wantcnt) -+ wantcnt = NUM_INT; /* FIPs mode can do 20000 bits or none */ -+#endif -+ -+ /* see if we can get enough entropy to make the world -+ * a better place. -+ */ -+ while (bufcnt < wantcnt && bufcnt < NUM_INT) { -+ list_for_each_entry_safe(rops, tmp, &random_ops, random_list) { -+ -+ n = (*rops->read_random)(rops->arg, &buf[bufcnt], -+ NUM_INT - bufcnt); -+ -+ /* on failure remove the random number generator */ -+ if (n == -1) { -+ list_del(&rops->random_list); -+ printk("crypto: RNG (driverid=0x%x) failed, disabling\n", -+ rops->driverid); -+ kfree(rops); -+ } else if (n > 0) -+ bufcnt += n; -+ } -+ /* give up CPU for a bit, just in case as this is a loop */ -+ schedule(); -+ } -+ -+ -+#ifdef CONFIG_OCF_FIPS -+ if (bufcnt > 0 && rndtest_buf((unsigned char *) &buf[0])) { -+ dprintk("crypto: buffer had fips errors, discarding\n"); -+ bufcnt = 0; -+ } -+#endif -+ -+ /* -+ * if we have a certified buffer, we can send some data -+ * to /dev/random and move along -+ */ -+ if (bufcnt > 0) { -+ /* add what we have */ -+ random_input_words(buf, bufcnt, bufcnt*sizeof(int)*8); -+ bufcnt = 0; -+ } -+ -+ /* give up CPU for a bit so we don't hog while filling */ -+ schedule(); -+ -+ /* wait for needing more */ -+ wantcnt = random_input_wait(); -+ -+ if (wantcnt <= 0) -+ wantcnt = 0; /* try to get some info again */ -+ else -+ /* round up to one word or we can loop forever */ -+ wantcnt = (wantcnt + (sizeof(int)*8)) / (sizeof(int)*8); -+ if (wantcnt > NUM_INT) { -+ wantcnt = NUM_INT; -+ } -+ -+ if (signal_pending(current)) { -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ spin_lock_irq(¤t->sigmask_lock); -+#endif -+ flush_signals(current); -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ spin_unlock_irq(¤t->sigmask_lock); -+#endif -+ } -+ } -+ -+ kfree(buf); -+ -+bad_alloc: -+ spin_lock_irq(&random_lock); -+ randomproc = (pid_t) -1; -+ started = 0; -+ spin_unlock_irq(&random_lock); -+ -+ return retval; -+} -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/README linux-2.6.36/crypto/ocf/README ---- linux-2.6.36.orig/crypto/ocf/README 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/README 2010-11-09 20:28:12.681240186 +0100 -@@ -0,0 +1,167 @@ -+README - ocf-linux-20100325 -+--------------------------- -+ -+This README provides instructions for getting ocf-linux compiled and -+operating in a generic linux environment. For other information you -+might like to visit the home page for this project: -+ -+ http://ocf-linux.sourceforge.net/ -+ -+Adding OCF to linux -+------------------- -+ -+ Not much in this file for now, just some notes. I usually build -+ the ocf support as modules but it can be built into the kernel as -+ well. To use it: -+ -+ * mknod /dev/crypto c 10 70 -+ -+ * to add OCF to your kernel source, you have two options. Apply -+ the kernel specific patch: -+ -+ cd linux-2.4*; gunzip < ocf-linux-24-XXXXXXXX.patch.gz | patch -p1 -+ cd linux-2.6*; gunzip < ocf-linux-26-XXXXXXXX.patch.gz | patch -p1 -+ -+ if you do one of the above, then you can proceed to the next step, -+ or you can do the above process by hand with using the patches against -+ linux-2.4.35 and 2.6.33 to include the ocf code under crypto/ocf. -+ Here's how to add it: -+ -+ for 2.4.35 (and later) -+ -+ cd linux-2.4.35/crypto -+ tar xvzf ocf-linux.tar.gz -+ cd .. -+ patch -p1 < crypto/ocf/patches/linux-2.4.35-ocf.patch -+ -+ for 2.6.23 (and later), find the kernel patch specific (or nearest) -+ to your kernel versions and then: -+ -+ cd linux-2.6.NN/crypto -+ tar xvzf ocf-linux.tar.gz -+ cd .. -+ patch -p1 < crypto/ocf/patches/linux-2.6.NN-ocf.patch -+ -+ It should be easy to take this patch and apply it to other more -+ recent versions of the kernels. The same patches should also work -+ relatively easily on kernels as old as 2.6.11 and 2.4.18. -+ -+ * under 2.4 if you are on a non-x86 platform, you may need to: -+ -+ cp linux-2.X.x/include/asm-i386/kmap_types.h linux-2.X.x/include/asm-YYY -+ -+ so that you can build the kernel crypto support needed for the cryptosoft -+ driver. -+ -+ * For simplicity you should enable all the crypto support in your kernel -+ except for the test driver. Likewise for the OCF options. Do not -+ enable OCF crypto drivers for HW that you do not have (for example -+ ixp4xx will not compile on non-Xscale systems). -+ -+ * make sure that cryptodev.h (from ocf-linux.tar.gz) is installed as -+ crypto/cryptodev.h in an include directory that is used for building -+ applications for your platform. For example on a host system that -+ might be: -+ -+ /usr/include/crypto/cryptodev.h -+ -+ * patch your openssl-0.9.8n code with the openssl-0.9.8n.patch. -+ (NOTE: there is no longer a need to patch ssh). The patch is against: -+ openssl-0_9_8e -+ -+ If you need a patch for an older version of openssl, you should look -+ to older OCF releases. This patch is unlikely to work on older -+ openssl versions. -+ -+ openssl-0.9.8n.patch -+ - enables --with-cryptodev for non BSD systems -+ - adds -cpu option to openssl speed for calculating CPU load -+ under linux -+ - fixes null pointer in openssl speed multi thread output. -+ - fixes test keys to work with linux crypto's more stringent -+ key checking. -+ - adds MD5/SHA acceleration (Ronen Shitrit), only enabled -+ with the --with-cryptodev-digests option -+ - fixes bug in engine code caching. -+ -+ * build crypto-tools-XXXXXXXX.tar.gz if you want to try some of the BSD -+ tools for testing OCF (ie., cryptotest). -+ -+How to load the OCF drivers -+--------------------------- -+ -+ First insert the base modules: -+ -+ insmod ocf -+ insmod cryptodev -+ -+ You can then install the software OCF driver with: -+ -+ insmod cryptosoft -+ -+ and one or more of the OCF HW drivers with: -+ -+ insmod safe -+ insmod hifn7751 -+ insmod ixp4xx -+ ... -+ -+ all the drivers take a debug option to enable verbose debug so that -+ you can see what is going on. For debug you load them as: -+ -+ insmod ocf crypto_debug=1 -+ insmod cryptodev cryptodev_debug=1 -+ insmod cryptosoft swcr_debug=1 -+ -+ You may load more than one OCF crypto driver but then there is no guarantee -+ as to which will be used. -+ -+ You can also enable debug at run time on 2.6 systems with the following: -+ -+ echo 1 > /sys/module/ocf/parameters/crypto_debug -+ echo 1 > /sys/module/cryptodev/parameters/cryptodev_debug -+ echo 1 > /sys/module/cryptosoft/parameters/swcr_debug -+ echo 1 > /sys/module/hifn7751/parameters/hifn_debug -+ echo 1 > /sys/module/safe/parameters/safe_debug -+ echo 1 > /sys/module/ixp4xx/parameters/ixp_debug -+ ... -+ -+Testing the OCF support -+----------------------- -+ -+ run "cryptotest", it should do a short test for a couple of -+ des packets. If it does everything is working. -+ -+ If this works, then ssh will use the driver when invoked as: -+ -+ ssh -c 3des username@host -+ -+ to see for sure that it is operating, enable debug as defined above. -+ -+ To get a better idea of performance run: -+ -+ cryptotest 100 4096 -+ -+ There are more options to cryptotest, see the help. -+ -+ It is also possible to use openssl to test the speed of the crypto -+ drivers. -+ -+ openssl speed -evp des -engine cryptodev -elapsed -+ openssl speed -evp des3 -engine cryptodev -elapsed -+ openssl speed -evp aes128 -engine cryptodev -elapsed -+ -+ and multiple threads (10) with: -+ -+ openssl speed -evp des -engine cryptodev -elapsed -multi 10 -+ openssl speed -evp des3 -engine cryptodev -elapsed -multi 10 -+ openssl speed -evp aes128 -engine cryptodev -elapsed -multi 10 -+ -+ for public key testing you can try: -+ -+ cryptokeytest -+ openssl speed -engine cryptodev rsa -elapsed -+ openssl speed -engine cryptodev dsa -elapsed -+ -+David McCullough -+david_mccullough@mcafee.com -diff -Nur linux-2.6.36.orig/crypto/ocf/rndtest.c linux-2.6.36/crypto/ocf/rndtest.c ---- linux-2.6.36.orig/crypto/ocf/rndtest.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/rndtest.c 2010-11-09 20:28:12.722495563 +0100 -@@ -0,0 +1,300 @@ -+/* $OpenBSD$ */ -+ -+/* -+ * OCF/Linux port done by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * The license and original author are listed below. -+ * -+ * Copyright (c) 2002 Jason L. Wright (jason@thought.net) -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. All advertising materials mentioning features or use of this software -+ * must display the following acknowledgement: -+ * This product includes software developed by Jason L. Wright -+ * 4. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "rndtest.h" -+ -+static struct rndtest_stats rndstats; -+ -+static void rndtest_test(struct rndtest_state *); -+ -+/* The tests themselves */ -+static int rndtest_monobit(struct rndtest_state *); -+static int rndtest_runs(struct rndtest_state *); -+static int rndtest_longruns(struct rndtest_state *); -+static int rndtest_chi_4(struct rndtest_state *); -+ -+static int rndtest_runs_check(struct rndtest_state *, int, int *); -+static void rndtest_runs_record(struct rndtest_state *, int, int *); -+ -+static const struct rndtest_testfunc { -+ int (*test)(struct rndtest_state *); -+} rndtest_funcs[] = { -+ { rndtest_monobit }, -+ { rndtest_runs }, -+ { rndtest_chi_4 }, -+ { rndtest_longruns }, -+}; -+ -+#define RNDTEST_NTESTS (sizeof(rndtest_funcs)/sizeof(rndtest_funcs[0])) -+ -+static void -+rndtest_test(struct rndtest_state *rsp) -+{ -+ int i, rv = 0; -+ -+ rndstats.rst_tests++; -+ for (i = 0; i < RNDTEST_NTESTS; i++) -+ rv |= (*rndtest_funcs[i].test)(rsp); -+ rsp->rs_discard = (rv != 0); -+} -+ -+ -+extern int crypto_debug; -+#define rndtest_verbose 2 -+#define rndtest_report(rsp, failure, fmt, a...) \ -+ { if (failure || crypto_debug) { printk("rng_test: " fmt "\n", a); } else; } -+ -+#define RNDTEST_MONOBIT_MINONES 9725 -+#define RNDTEST_MONOBIT_MAXONES 10275 -+ -+static int -+rndtest_monobit(struct rndtest_state *rsp) -+{ -+ int i, ones = 0, j; -+ u_int8_t r; -+ -+ for (i = 0; i < RNDTEST_NBYTES; i++) { -+ r = rsp->rs_buf[i]; -+ for (j = 0; j < 8; j++, r <<= 1) -+ if (r & 0x80) -+ ones++; -+ } -+ if (ones > RNDTEST_MONOBIT_MINONES && -+ ones < RNDTEST_MONOBIT_MAXONES) { -+ if (rndtest_verbose > 1) -+ rndtest_report(rsp, 0, "monobit pass (%d < %d < %d)", -+ RNDTEST_MONOBIT_MINONES, ones, -+ RNDTEST_MONOBIT_MAXONES); -+ return (0); -+ } else { -+ if (rndtest_verbose) -+ rndtest_report(rsp, 1, -+ "monobit failed (%d ones)", ones); -+ rndstats.rst_monobit++; -+ return (-1); -+ } -+} -+ -+#define RNDTEST_RUNS_NINTERVAL 6 -+ -+static const struct rndtest_runs_tabs { -+ u_int16_t min, max; -+} rndtest_runs_tab[] = { -+ { 2343, 2657 }, -+ { 1135, 1365 }, -+ { 542, 708 }, -+ { 251, 373 }, -+ { 111, 201 }, -+ { 111, 201 }, -+}; -+ -+static int -+rndtest_runs(struct rndtest_state *rsp) -+{ -+ int i, j, ones, zeros, rv = 0; -+ int onei[RNDTEST_RUNS_NINTERVAL], zeroi[RNDTEST_RUNS_NINTERVAL]; -+ u_int8_t c; -+ -+ bzero(onei, sizeof(onei)); -+ bzero(zeroi, sizeof(zeroi)); -+ ones = zeros = 0; -+ for (i = 0; i < RNDTEST_NBYTES; i++) { -+ c = rsp->rs_buf[i]; -+ for (j = 0; j < 8; j++, c <<= 1) { -+ if (c & 0x80) { -+ ones++; -+ rndtest_runs_record(rsp, zeros, zeroi); -+ zeros = 0; -+ } else { -+ zeros++; -+ rndtest_runs_record(rsp, ones, onei); -+ ones = 0; -+ } -+ } -+ } -+ rndtest_runs_record(rsp, ones, onei); -+ rndtest_runs_record(rsp, zeros, zeroi); -+ -+ rv |= rndtest_runs_check(rsp, 0, zeroi); -+ rv |= rndtest_runs_check(rsp, 1, onei); -+ -+ if (rv) -+ rndstats.rst_runs++; -+ -+ return (rv); -+} -+ -+static void -+rndtest_runs_record(struct rndtest_state *rsp, int len, int *intrv) -+{ -+ if (len == 0) -+ return; -+ if (len > RNDTEST_RUNS_NINTERVAL) -+ len = RNDTEST_RUNS_NINTERVAL; -+ len -= 1; -+ intrv[len]++; -+} -+ -+static int -+rndtest_runs_check(struct rndtest_state *rsp, int val, int *src) -+{ -+ int i, rv = 0; -+ -+ for (i = 0; i < RNDTEST_RUNS_NINTERVAL; i++) { -+ if (src[i] < rndtest_runs_tab[i].min || -+ src[i] > rndtest_runs_tab[i].max) { -+ rndtest_report(rsp, 1, -+ "%s interval %d failed (%d, %d-%d)", -+ val ? "ones" : "zeros", -+ i + 1, src[i], rndtest_runs_tab[i].min, -+ rndtest_runs_tab[i].max); -+ rv = -1; -+ } else { -+ rndtest_report(rsp, 0, -+ "runs pass %s interval %d (%d < %d < %d)", -+ val ? "ones" : "zeros", -+ i + 1, rndtest_runs_tab[i].min, src[i], -+ rndtest_runs_tab[i].max); -+ } -+ } -+ return (rv); -+} -+ -+static int -+rndtest_longruns(struct rndtest_state *rsp) -+{ -+ int i, j, ones = 0, zeros = 0, maxones = 0, maxzeros = 0; -+ u_int8_t c; -+ -+ for (i = 0; i < RNDTEST_NBYTES; i++) { -+ c = rsp->rs_buf[i]; -+ for (j = 0; j < 8; j++, c <<= 1) { -+ if (c & 0x80) { -+ zeros = 0; -+ ones++; -+ if (ones > maxones) -+ maxones = ones; -+ } else { -+ ones = 0; -+ zeros++; -+ if (zeros > maxzeros) -+ maxzeros = zeros; -+ } -+ } -+ } -+ -+ if (maxones < 26 && maxzeros < 26) { -+ rndtest_report(rsp, 0, "longruns pass (%d ones, %d zeros)", -+ maxones, maxzeros); -+ return (0); -+ } else { -+ rndtest_report(rsp, 1, "longruns fail (%d ones, %d zeros)", -+ maxones, maxzeros); -+ rndstats.rst_longruns++; -+ return (-1); -+ } -+} -+ -+/* -+ * chi^2 test over 4 bits: (this is called the poker test in FIPS 140-2, -+ * but it is really the chi^2 test over 4 bits (the poker test as described -+ * by Knuth vol 2 is something different, and I take him as authoritative -+ * on nomenclature over NIST). -+ */ -+#define RNDTEST_CHI4_K 16 -+#define RNDTEST_CHI4_K_MASK (RNDTEST_CHI4_K - 1) -+ -+/* -+ * The unnormalized values are used so that we don't have to worry about -+ * fractional precision. The "real" value is found by: -+ * (V - 1562500) * (16 / 5000) = Vn (where V is the unnormalized value) -+ */ -+#define RNDTEST_CHI4_VMIN 1563181 /* 2.1792 */ -+#define RNDTEST_CHI4_VMAX 1576929 /* 46.1728 */ -+ -+static int -+rndtest_chi_4(struct rndtest_state *rsp) -+{ -+ unsigned int freq[RNDTEST_CHI4_K], i, sum; -+ -+ for (i = 0; i < RNDTEST_CHI4_K; i++) -+ freq[i] = 0; -+ -+ /* Get number of occurances of each 4 bit pattern */ -+ for (i = 0; i < RNDTEST_NBYTES; i++) { -+ freq[(rsp->rs_buf[i] >> 4) & RNDTEST_CHI4_K_MASK]++; -+ freq[(rsp->rs_buf[i] >> 0) & RNDTEST_CHI4_K_MASK]++; -+ } -+ -+ for (i = 0, sum = 0; i < RNDTEST_CHI4_K; i++) -+ sum += freq[i] * freq[i]; -+ -+ if (sum >= 1563181 && sum <= 1576929) { -+ rndtest_report(rsp, 0, "chi^2(4): pass (sum %u)", sum); -+ return (0); -+ } else { -+ rndtest_report(rsp, 1, "chi^2(4): failed (sum %u)", sum); -+ rndstats.rst_chi++; -+ return (-1); -+ } -+} -+ -+int -+rndtest_buf(unsigned char *buf) -+{ -+ struct rndtest_state rsp; -+ -+ memset(&rsp, 0, sizeof(rsp)); -+ rsp.rs_buf = buf; -+ rndtest_test(&rsp); -+ return(rsp.rs_discard); -+} -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/rndtest.h linux-2.6.36/crypto/ocf/rndtest.h ---- linux-2.6.36.orig/crypto/ocf/rndtest.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/rndtest.h 2010-11-09 20:28:12.762495556 +0100 -@@ -0,0 +1,54 @@ -+/* $FreeBSD: src/sys/dev/rndtest/rndtest.h,v 1.1 2003/03/11 22:54:44 sam Exp $ */ -+/* $OpenBSD$ */ -+ -+/* -+ * Copyright (c) 2002 Jason L. Wright (jason@thought.net) -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. All advertising materials mentioning features or use of this software -+ * must display the following acknowledgement: -+ * This product includes software developed by Jason L. Wright -+ * 4. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/* Some of the tests depend on these values */ -+#define RNDTEST_NBYTES 2500 -+#define RNDTEST_NBITS (8 * RNDTEST_NBYTES) -+ -+struct rndtest_state { -+ int rs_discard; /* discard/accept random data */ -+ u_int8_t *rs_buf; -+}; -+ -+struct rndtest_stats { -+ u_int32_t rst_discard; /* number of bytes discarded */ -+ u_int32_t rst_tests; /* number of test runs */ -+ u_int32_t rst_monobit; /* monobit test failures */ -+ u_int32_t rst_runs; /* 0/1 runs failures */ -+ u_int32_t rst_longruns; /* longruns failures */ -+ u_int32_t rst_chi; /* chi^2 failures */ -+}; -+ -+extern int rndtest_buf(unsigned char *buf); -diff -Nur linux-2.6.36.orig/crypto/ocf/safe/Makefile linux-2.6.36/crypto/ocf/safe/Makefile ---- linux-2.6.36.orig/crypto/ocf/safe/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/safe/Makefile 2010-11-09 20:28:12.805576889 +0100 -@@ -0,0 +1,12 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+obj-$(CONFIG_OCF_SAFE) += safe.o -+ -+obj ?= . -+EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/safe/md5.c linux-2.6.36/crypto/ocf/safe/md5.c ---- linux-2.6.36.orig/crypto/ocf/safe/md5.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/safe/md5.c 2010-11-09 20:28:12.842495449 +0100 -@@ -0,0 +1,308 @@ -+/* $KAME: md5.c,v 1.5 2000/11/08 06:13:08 itojun Exp $ */ -+/* -+ * Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. Neither the name of the project nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ */ -+ -+#if 0 -+#include -+__FBSDID("$FreeBSD: src/sys/crypto/md5.c,v 1.9 2004/01/27 19:49:19 des Exp $"); -+ -+#include -+#include -+#include -+#include -+#include -+#endif -+ -+#define SHIFT(X, s) (((X) << (s)) | ((X) >> (32 - (s)))) -+ -+#define F(X, Y, Z) (((X) & (Y)) | ((~X) & (Z))) -+#define G(X, Y, Z) (((X) & (Z)) | ((Y) & (~Z))) -+#define H(X, Y, Z) ((X) ^ (Y) ^ (Z)) -+#define I(X, Y, Z) ((Y) ^ ((X) | (~Z))) -+ -+#define ROUND1(a, b, c, d, k, s, i) { \ -+ (a) = (a) + F((b), (c), (d)) + X[(k)] + T[(i)]; \ -+ (a) = SHIFT((a), (s)); \ -+ (a) = (b) + (a); \ -+} -+ -+#define ROUND2(a, b, c, d, k, s, i) { \ -+ (a) = (a) + G((b), (c), (d)) + X[(k)] + T[(i)]; \ -+ (a) = SHIFT((a), (s)); \ -+ (a) = (b) + (a); \ -+} -+ -+#define ROUND3(a, b, c, d, k, s, i) { \ -+ (a) = (a) + H((b), (c), (d)) + X[(k)] + T[(i)]; \ -+ (a) = SHIFT((a), (s)); \ -+ (a) = (b) + (a); \ -+} -+ -+#define ROUND4(a, b, c, d, k, s, i) { \ -+ (a) = (a) + I((b), (c), (d)) + X[(k)] + T[(i)]; \ -+ (a) = SHIFT((a), (s)); \ -+ (a) = (b) + (a); \ -+} -+ -+#define Sa 7 -+#define Sb 12 -+#define Sc 17 -+#define Sd 22 -+ -+#define Se 5 -+#define Sf 9 -+#define Sg 14 -+#define Sh 20 -+ -+#define Si 4 -+#define Sj 11 -+#define Sk 16 -+#define Sl 23 -+ -+#define Sm 6 -+#define Sn 10 -+#define So 15 -+#define Sp 21 -+ -+#define MD5_A0 0x67452301 -+#define MD5_B0 0xefcdab89 -+#define MD5_C0 0x98badcfe -+#define MD5_D0 0x10325476 -+ -+/* Integer part of 4294967296 times abs(sin(i)), where i is in radians. */ -+static const u_int32_t T[65] = { -+ 0, -+ 0xd76aa478, 0xe8c7b756, 0x242070db, 0xc1bdceee, -+ 0xf57c0faf, 0x4787c62a, 0xa8304613, 0xfd469501, -+ 0x698098d8, 0x8b44f7af, 0xffff5bb1, 0x895cd7be, -+ 0x6b901122, 0xfd987193, 0xa679438e, 0x49b40821, -+ -+ 0xf61e2562, 0xc040b340, 0x265e5a51, 0xe9b6c7aa, -+ 0xd62f105d, 0x2441453, 0xd8a1e681, 0xe7d3fbc8, -+ 0x21e1cde6, 0xc33707d6, 0xf4d50d87, 0x455a14ed, -+ 0xa9e3e905, 0xfcefa3f8, 0x676f02d9, 0x8d2a4c8a, -+ -+ 0xfffa3942, 0x8771f681, 0x6d9d6122, 0xfde5380c, -+ 0xa4beea44, 0x4bdecfa9, 0xf6bb4b60, 0xbebfbc70, -+ 0x289b7ec6, 0xeaa127fa, 0xd4ef3085, 0x4881d05, -+ 0xd9d4d039, 0xe6db99e5, 0x1fa27cf8, 0xc4ac5665, -+ -+ 0xf4292244, 0x432aff97, 0xab9423a7, 0xfc93a039, -+ 0x655b59c3, 0x8f0ccc92, 0xffeff47d, 0x85845dd1, -+ 0x6fa87e4f, 0xfe2ce6e0, 0xa3014314, 0x4e0811a1, -+ 0xf7537e82, 0xbd3af235, 0x2ad7d2bb, 0xeb86d391, -+}; -+ -+static const u_int8_t md5_paddat[MD5_BUFLEN] = { -+ 0x80, 0, 0, 0, 0, 0, 0, 0, -+ 0, 0, 0, 0, 0, 0, 0, 0, -+ 0, 0, 0, 0, 0, 0, 0, 0, -+ 0, 0, 0, 0, 0, 0, 0, 0, -+ 0, 0, 0, 0, 0, 0, 0, 0, -+ 0, 0, 0, 0, 0, 0, 0, 0, -+ 0, 0, 0, 0, 0, 0, 0, 0, -+ 0, 0, 0, 0, 0, 0, 0, 0, -+}; -+ -+static void md5_calc(u_int8_t *, md5_ctxt *); -+ -+void md5_init(ctxt) -+ md5_ctxt *ctxt; -+{ -+ ctxt->md5_n = 0; -+ ctxt->md5_i = 0; -+ ctxt->md5_sta = MD5_A0; -+ ctxt->md5_stb = MD5_B0; -+ ctxt->md5_stc = MD5_C0; -+ ctxt->md5_std = MD5_D0; -+ bzero(ctxt->md5_buf, sizeof(ctxt->md5_buf)); -+} -+ -+void md5_loop(ctxt, input, len) -+ md5_ctxt *ctxt; -+ u_int8_t *input; -+ u_int len; /* number of bytes */ -+{ -+ u_int gap, i; -+ -+ ctxt->md5_n += len * 8; /* byte to bit */ -+ gap = MD5_BUFLEN - ctxt->md5_i; -+ -+ if (len >= gap) { -+ bcopy((void *)input, (void *)(ctxt->md5_buf + ctxt->md5_i), -+ gap); -+ md5_calc(ctxt->md5_buf, ctxt); -+ -+ for (i = gap; i + MD5_BUFLEN <= len; i += MD5_BUFLEN) { -+ md5_calc((u_int8_t *)(input + i), ctxt); -+ } -+ -+ ctxt->md5_i = len - i; -+ bcopy((void *)(input + i), (void *)ctxt->md5_buf, ctxt->md5_i); -+ } else { -+ bcopy((void *)input, (void *)(ctxt->md5_buf + ctxt->md5_i), -+ len); -+ ctxt->md5_i += len; -+ } -+} -+ -+void md5_pad(ctxt) -+ md5_ctxt *ctxt; -+{ -+ u_int gap; -+ -+ /* Don't count up padding. Keep md5_n. */ -+ gap = MD5_BUFLEN - ctxt->md5_i; -+ if (gap > 8) { -+ bcopy(md5_paddat, -+ (void *)(ctxt->md5_buf + ctxt->md5_i), -+ gap - sizeof(ctxt->md5_n)); -+ } else { -+ /* including gap == 8 */ -+ bcopy(md5_paddat, (void *)(ctxt->md5_buf + ctxt->md5_i), -+ gap); -+ md5_calc(ctxt->md5_buf, ctxt); -+ bcopy((md5_paddat + gap), -+ (void *)ctxt->md5_buf, -+ MD5_BUFLEN - sizeof(ctxt->md5_n)); -+ } -+ -+ /* 8 byte word */ -+#if BYTE_ORDER == LITTLE_ENDIAN -+ bcopy(&ctxt->md5_n8[0], &ctxt->md5_buf[56], 8); -+#endif -+#if BYTE_ORDER == BIG_ENDIAN -+ ctxt->md5_buf[56] = ctxt->md5_n8[7]; -+ ctxt->md5_buf[57] = ctxt->md5_n8[6]; -+ ctxt->md5_buf[58] = ctxt->md5_n8[5]; -+ ctxt->md5_buf[59] = ctxt->md5_n8[4]; -+ ctxt->md5_buf[60] = ctxt->md5_n8[3]; -+ ctxt->md5_buf[61] = ctxt->md5_n8[2]; -+ ctxt->md5_buf[62] = ctxt->md5_n8[1]; -+ ctxt->md5_buf[63] = ctxt->md5_n8[0]; -+#endif -+ -+ md5_calc(ctxt->md5_buf, ctxt); -+} -+ -+void md5_result(digest, ctxt) -+ u_int8_t *digest; -+ md5_ctxt *ctxt; -+{ -+ /* 4 byte words */ -+#if BYTE_ORDER == LITTLE_ENDIAN -+ bcopy(&ctxt->md5_st8[0], digest, 16); -+#endif -+#if BYTE_ORDER == BIG_ENDIAN -+ digest[ 0] = ctxt->md5_st8[ 3]; digest[ 1] = ctxt->md5_st8[ 2]; -+ digest[ 2] = ctxt->md5_st8[ 1]; digest[ 3] = ctxt->md5_st8[ 0]; -+ digest[ 4] = ctxt->md5_st8[ 7]; digest[ 5] = ctxt->md5_st8[ 6]; -+ digest[ 6] = ctxt->md5_st8[ 5]; digest[ 7] = ctxt->md5_st8[ 4]; -+ digest[ 8] = ctxt->md5_st8[11]; digest[ 9] = ctxt->md5_st8[10]; -+ digest[10] = ctxt->md5_st8[ 9]; digest[11] = ctxt->md5_st8[ 8]; -+ digest[12] = ctxt->md5_st8[15]; digest[13] = ctxt->md5_st8[14]; -+ digest[14] = ctxt->md5_st8[13]; digest[15] = ctxt->md5_st8[12]; -+#endif -+} -+ -+static void md5_calc(b64, ctxt) -+ u_int8_t *b64; -+ md5_ctxt *ctxt; -+{ -+ u_int32_t A = ctxt->md5_sta; -+ u_int32_t B = ctxt->md5_stb; -+ u_int32_t C = ctxt->md5_stc; -+ u_int32_t D = ctxt->md5_std; -+#if BYTE_ORDER == LITTLE_ENDIAN -+ u_int32_t *X = (u_int32_t *)b64; -+#endif -+#if BYTE_ORDER == BIG_ENDIAN -+ /* 4 byte words */ -+ /* what a brute force but fast! */ -+ u_int32_t X[16]; -+ u_int8_t *y = (u_int8_t *)X; -+ y[ 0] = b64[ 3]; y[ 1] = b64[ 2]; y[ 2] = b64[ 1]; y[ 3] = b64[ 0]; -+ y[ 4] = b64[ 7]; y[ 5] = b64[ 6]; y[ 6] = b64[ 5]; y[ 7] = b64[ 4]; -+ y[ 8] = b64[11]; y[ 9] = b64[10]; y[10] = b64[ 9]; y[11] = b64[ 8]; -+ y[12] = b64[15]; y[13] = b64[14]; y[14] = b64[13]; y[15] = b64[12]; -+ y[16] = b64[19]; y[17] = b64[18]; y[18] = b64[17]; y[19] = b64[16]; -+ y[20] = b64[23]; y[21] = b64[22]; y[22] = b64[21]; y[23] = b64[20]; -+ y[24] = b64[27]; y[25] = b64[26]; y[26] = b64[25]; y[27] = b64[24]; -+ y[28] = b64[31]; y[29] = b64[30]; y[30] = b64[29]; y[31] = b64[28]; -+ y[32] = b64[35]; y[33] = b64[34]; y[34] = b64[33]; y[35] = b64[32]; -+ y[36] = b64[39]; y[37] = b64[38]; y[38] = b64[37]; y[39] = b64[36]; -+ y[40] = b64[43]; y[41] = b64[42]; y[42] = b64[41]; y[43] = b64[40]; -+ y[44] = b64[47]; y[45] = b64[46]; y[46] = b64[45]; y[47] = b64[44]; -+ y[48] = b64[51]; y[49] = b64[50]; y[50] = b64[49]; y[51] = b64[48]; -+ y[52] = b64[55]; y[53] = b64[54]; y[54] = b64[53]; y[55] = b64[52]; -+ y[56] = b64[59]; y[57] = b64[58]; y[58] = b64[57]; y[59] = b64[56]; -+ y[60] = b64[63]; y[61] = b64[62]; y[62] = b64[61]; y[63] = b64[60]; -+#endif -+ -+ ROUND1(A, B, C, D, 0, Sa, 1); ROUND1(D, A, B, C, 1, Sb, 2); -+ ROUND1(C, D, A, B, 2, Sc, 3); ROUND1(B, C, D, A, 3, Sd, 4); -+ ROUND1(A, B, C, D, 4, Sa, 5); ROUND1(D, A, B, C, 5, Sb, 6); -+ ROUND1(C, D, A, B, 6, Sc, 7); ROUND1(B, C, D, A, 7, Sd, 8); -+ ROUND1(A, B, C, D, 8, Sa, 9); ROUND1(D, A, B, C, 9, Sb, 10); -+ ROUND1(C, D, A, B, 10, Sc, 11); ROUND1(B, C, D, A, 11, Sd, 12); -+ ROUND1(A, B, C, D, 12, Sa, 13); ROUND1(D, A, B, C, 13, Sb, 14); -+ ROUND1(C, D, A, B, 14, Sc, 15); ROUND1(B, C, D, A, 15, Sd, 16); -+ -+ ROUND2(A, B, C, D, 1, Se, 17); ROUND2(D, A, B, C, 6, Sf, 18); -+ ROUND2(C, D, A, B, 11, Sg, 19); ROUND2(B, C, D, A, 0, Sh, 20); -+ ROUND2(A, B, C, D, 5, Se, 21); ROUND2(D, A, B, C, 10, Sf, 22); -+ ROUND2(C, D, A, B, 15, Sg, 23); ROUND2(B, C, D, A, 4, Sh, 24); -+ ROUND2(A, B, C, D, 9, Se, 25); ROUND2(D, A, B, C, 14, Sf, 26); -+ ROUND2(C, D, A, B, 3, Sg, 27); ROUND2(B, C, D, A, 8, Sh, 28); -+ ROUND2(A, B, C, D, 13, Se, 29); ROUND2(D, A, B, C, 2, Sf, 30); -+ ROUND2(C, D, A, B, 7, Sg, 31); ROUND2(B, C, D, A, 12, Sh, 32); -+ -+ ROUND3(A, B, C, D, 5, Si, 33); ROUND3(D, A, B, C, 8, Sj, 34); -+ ROUND3(C, D, A, B, 11, Sk, 35); ROUND3(B, C, D, A, 14, Sl, 36); -+ ROUND3(A, B, C, D, 1, Si, 37); ROUND3(D, A, B, C, 4, Sj, 38); -+ ROUND3(C, D, A, B, 7, Sk, 39); ROUND3(B, C, D, A, 10, Sl, 40); -+ ROUND3(A, B, C, D, 13, Si, 41); ROUND3(D, A, B, C, 0, Sj, 42); -+ ROUND3(C, D, A, B, 3, Sk, 43); ROUND3(B, C, D, A, 6, Sl, 44); -+ ROUND3(A, B, C, D, 9, Si, 45); ROUND3(D, A, B, C, 12, Sj, 46); -+ ROUND3(C, D, A, B, 15, Sk, 47); ROUND3(B, C, D, A, 2, Sl, 48); -+ -+ ROUND4(A, B, C, D, 0, Sm, 49); ROUND4(D, A, B, C, 7, Sn, 50); -+ ROUND4(C, D, A, B, 14, So, 51); ROUND4(B, C, D, A, 5, Sp, 52); -+ ROUND4(A, B, C, D, 12, Sm, 53); ROUND4(D, A, B, C, 3, Sn, 54); -+ ROUND4(C, D, A, B, 10, So, 55); ROUND4(B, C, D, A, 1, Sp, 56); -+ ROUND4(A, B, C, D, 8, Sm, 57); ROUND4(D, A, B, C, 15, Sn, 58); -+ ROUND4(C, D, A, B, 6, So, 59); ROUND4(B, C, D, A, 13, Sp, 60); -+ ROUND4(A, B, C, D, 4, Sm, 61); ROUND4(D, A, B, C, 11, Sn, 62); -+ ROUND4(C, D, A, B, 2, So, 63); ROUND4(B, C, D, A, 9, Sp, 64); -+ -+ ctxt->md5_sta += A; -+ ctxt->md5_stb += B; -+ ctxt->md5_stc += C; -+ ctxt->md5_std += D; -+} -diff -Nur linux-2.6.36.orig/crypto/ocf/safe/md5.h linux-2.6.36/crypto/ocf/safe/md5.h ---- linux-2.6.36.orig/crypto/ocf/safe/md5.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/safe/md5.h 2010-11-09 20:28:12.881683669 +0100 -@@ -0,0 +1,76 @@ -+/* $FreeBSD: src/sys/crypto/md5.h,v 1.4 2002/03/20 05:13:50 alfred Exp $ */ -+/* $KAME: md5.h,v 1.4 2000/03/27 04:36:22 sumikawa Exp $ */ -+ -+/* -+ * Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. Neither the name of the project nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ */ -+ -+#ifndef _NETINET6_MD5_H_ -+#define _NETINET6_MD5_H_ -+ -+#define MD5_BUFLEN 64 -+ -+typedef struct { -+ union { -+ u_int32_t md5_state32[4]; -+ u_int8_t md5_state8[16]; -+ } md5_st; -+ -+#define md5_sta md5_st.md5_state32[0] -+#define md5_stb md5_st.md5_state32[1] -+#define md5_stc md5_st.md5_state32[2] -+#define md5_std md5_st.md5_state32[3] -+#define md5_st8 md5_st.md5_state8 -+ -+ union { -+ u_int64_t md5_count64; -+ u_int8_t md5_count8[8]; -+ } md5_count; -+#define md5_n md5_count.md5_count64 -+#define md5_n8 md5_count.md5_count8 -+ -+ u_int md5_i; -+ u_int8_t md5_buf[MD5_BUFLEN]; -+} md5_ctxt; -+ -+extern void md5_init(md5_ctxt *); -+extern void md5_loop(md5_ctxt *, u_int8_t *, u_int); -+extern void md5_pad(md5_ctxt *); -+extern void md5_result(u_int8_t *, md5_ctxt *); -+ -+/* compatibility */ -+#define MD5_CTX md5_ctxt -+#define MD5Init(x) md5_init((x)) -+#define MD5Update(x, y, z) md5_loop((x), (y), (z)) -+#define MD5Final(x, y) \ -+do { \ -+ md5_pad((y)); \ -+ md5_result((x), (y)); \ -+} while (0) -+ -+#endif /* ! _NETINET6_MD5_H_*/ -diff -Nur linux-2.6.36.orig/crypto/ocf/safe/safe.c linux-2.6.36/crypto/ocf/safe/safe.c ---- linux-2.6.36.orig/crypto/ocf/safe/safe.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/safe/safe.c 2010-11-09 20:28:12.922204086 +0100 -@@ -0,0 +1,2288 @@ -+/*- -+ * Linux port done by David McCullough -+ * Copyright (C) 2004-2010 David McCullough -+ * The license and original author are listed below. -+ * -+ * Copyright (c) 2003 Sam Leffler, Errno Consulting -+ * Copyright (c) 2003 Global Technology Associates, Inc. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ * -+__FBSDID("$FreeBSD: src/sys/dev/safe/safe.c,v 1.18 2007/03/21 03:42:50 sam Exp $"); -+ */ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* -+ * SafeNet SafeXcel-1141 hardware crypto accelerator -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#if 1 -+#define DPRINTF(a) do { \ -+ if (debug) { \ -+ printk("%s: ", sc ? \ -+ device_get_nameunit(sc->sc_dev) : "safe"); \ -+ printk a; \ -+ } \ -+ } while (0) -+#else -+#define DPRINTF(a) -+#endif -+ -+/* -+ * until we find a cleaner way, include the BSD md5/sha1 code -+ * here -+ */ -+#define HMAC_HACK 1 -+#ifdef HMAC_HACK -+#define LITTLE_ENDIAN 1234 -+#define BIG_ENDIAN 4321 -+#ifdef __LITTLE_ENDIAN -+#define BYTE_ORDER LITTLE_ENDIAN -+#endif -+#ifdef __BIG_ENDIAN -+#define BYTE_ORDER BIG_ENDIAN -+#endif -+#include -+#include -+#include -+#include -+ -+u_int8_t hmac_ipad_buffer[64] = { -+ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, -+ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, -+ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, -+ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, -+ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, -+ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, -+ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, -+ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36 -+}; -+ -+u_int8_t hmac_opad_buffer[64] = { -+ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, -+ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, -+ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, -+ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, -+ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, -+ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, -+ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, -+ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C -+}; -+#endif /* HMAC_HACK */ -+ -+/* add proc entry for this */ -+struct safe_stats safestats; -+ -+#define debug safe_debug -+int safe_debug = 0; -+module_param(safe_debug, int, 0644); -+MODULE_PARM_DESC(safe_debug, "Enable debug"); -+ -+static void safe_callback(struct safe_softc *, struct safe_ringentry *); -+static void safe_feed(struct safe_softc *, struct safe_ringentry *); -+#if defined(CONFIG_OCF_RANDOMHARVEST) && !defined(SAFE_NO_RNG) -+static void safe_rng_init(struct safe_softc *); -+int safe_rngbufsize = 8; /* 32 bytes each read */ -+module_param(safe_rngbufsize, int, 0644); -+MODULE_PARM_DESC(safe_rngbufsize, "RNG polling buffer size (32-bit words)"); -+int safe_rngmaxalarm = 8; /* max alarms before reset */ -+module_param(safe_rngmaxalarm, int, 0644); -+MODULE_PARM_DESC(safe_rngmaxalarm, "RNG max alarms before reset"); -+#endif /* SAFE_NO_RNG */ -+ -+static void safe_totalreset(struct safe_softc *sc); -+static int safe_dmamap_aligned(struct safe_softc *sc, const struct safe_operand *op); -+static int safe_dmamap_uniform(struct safe_softc *sc, const struct safe_operand *op); -+static int safe_free_entry(struct safe_softc *sc, struct safe_ringentry *re); -+static int safe_kprocess(device_t dev, struct cryptkop *krp, int hint); -+static int safe_kstart(struct safe_softc *sc); -+static int safe_ksigbits(struct safe_softc *sc, struct crparam *cr); -+static void safe_kfeed(struct safe_softc *sc); -+static void safe_kpoll(unsigned long arg); -+static void safe_kload_reg(struct safe_softc *sc, u_int32_t off, -+ u_int32_t len, struct crparam *n); -+ -+static int safe_newsession(device_t, u_int32_t *, struct cryptoini *); -+static int safe_freesession(device_t, u_int64_t); -+static int safe_process(device_t, struct cryptop *, int); -+ -+static device_method_t safe_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, safe_newsession), -+ DEVMETHOD(cryptodev_freesession,safe_freesession), -+ DEVMETHOD(cryptodev_process, safe_process), -+ DEVMETHOD(cryptodev_kprocess, safe_kprocess), -+}; -+ -+#define READ_REG(sc,r) readl((sc)->sc_base_addr + (r)) -+#define WRITE_REG(sc,r,val) writel((val), (sc)->sc_base_addr + (r)) -+ -+#define SAFE_MAX_CHIPS 8 -+static struct safe_softc *safe_chip_idx[SAFE_MAX_CHIPS]; -+ -+/* -+ * split our buffers up into safe DMAable byte fragments to avoid lockup -+ * bug in 1141 HW on rev 1.0. -+ */ -+ -+static int -+pci_map_linear( -+ struct safe_softc *sc, -+ struct safe_operand *buf, -+ void *addr, -+ int len) -+{ -+ dma_addr_t tmp; -+ int chunk, tlen = len; -+ -+ tmp = pci_map_single(sc->sc_pcidev, addr, len, PCI_DMA_BIDIRECTIONAL); -+ -+ buf->mapsize += len; -+ while (len > 0) { -+ chunk = (len > sc->sc_max_dsize) ? sc->sc_max_dsize : len; -+ buf->segs[buf->nsegs].ds_addr = tmp; -+ buf->segs[buf->nsegs].ds_len = chunk; -+ buf->segs[buf->nsegs].ds_tlen = tlen; -+ buf->nsegs++; -+ tmp += chunk; -+ len -= chunk; -+ tlen = 0; -+ } -+ return 0; -+} -+ -+/* -+ * map in a given uio buffer (great on some arches :-) -+ */ -+ -+static int -+pci_map_uio(struct safe_softc *sc, struct safe_operand *buf, struct uio *uio) -+{ -+ struct iovec *iov = uio->uio_iov; -+ int n; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ buf->mapsize = 0; -+ buf->nsegs = 0; -+ -+ for (n = 0; n < uio->uio_iovcnt; n++) { -+ pci_map_linear(sc, buf, iov->iov_base, iov->iov_len); -+ iov++; -+ } -+ -+ /* identify this buffer by the first segment */ -+ buf->map = (void *) buf->segs[0].ds_addr; -+ return(0); -+} -+ -+/* -+ * map in a given sk_buff -+ */ -+ -+static int -+pci_map_skb(struct safe_softc *sc,struct safe_operand *buf,struct sk_buff *skb) -+{ -+ int i; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ buf->mapsize = 0; -+ buf->nsegs = 0; -+ -+ pci_map_linear(sc, buf, skb->data, skb_headlen(skb)); -+ -+ for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { -+ pci_map_linear(sc, buf, -+ page_address(skb_shinfo(skb)->frags[i].page) + -+ skb_shinfo(skb)->frags[i].page_offset, -+ skb_shinfo(skb)->frags[i].size); -+ } -+ -+ /* identify this buffer by the first segment */ -+ buf->map = (void *) buf->segs[0].ds_addr; -+ return(0); -+} -+ -+ -+#if 0 /* not needed at this time */ -+static void -+pci_sync_operand(struct safe_softc *sc, struct safe_operand *buf) -+{ -+ int i; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ for (i = 0; i < buf->nsegs; i++) -+ pci_dma_sync_single_for_cpu(sc->sc_pcidev, buf->segs[i].ds_addr, -+ buf->segs[i].ds_len, PCI_DMA_BIDIRECTIONAL); -+} -+#endif -+ -+static void -+pci_unmap_operand(struct safe_softc *sc, struct safe_operand *buf) -+{ -+ int i; -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ for (i = 0; i < buf->nsegs; i++) { -+ if (buf->segs[i].ds_tlen) { -+ DPRINTF(("%s - unmap %d 0x%x %d\n", __FUNCTION__, i, buf->segs[i].ds_addr, buf->segs[i].ds_tlen)); -+ pci_unmap_single(sc->sc_pcidev, buf->segs[i].ds_addr, -+ buf->segs[i].ds_tlen, PCI_DMA_BIDIRECTIONAL); -+ DPRINTF(("%s - unmap %d 0x%x %d done\n", __FUNCTION__, i, buf->segs[i].ds_addr, buf->segs[i].ds_tlen)); -+ } -+ buf->segs[i].ds_addr = 0; -+ buf->segs[i].ds_len = 0; -+ buf->segs[i].ds_tlen = 0; -+ } -+ buf->nsegs = 0; -+ buf->mapsize = 0; -+ buf->map = 0; -+} -+ -+ -+/* -+ * SafeXcel Interrupt routine -+ */ -+static irqreturn_t -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) -+safe_intr(int irq, void *arg) -+#else -+safe_intr(int irq, void *arg, struct pt_regs *regs) -+#endif -+{ -+ struct safe_softc *sc = arg; -+ int stat; -+ unsigned long flags; -+ -+ stat = READ_REG(sc, SAFE_HM_STAT); -+ -+ DPRINTF(("%s(stat=0x%x)\n", __FUNCTION__, stat)); -+ -+ if (stat == 0) /* shared irq, not for us */ -+ return IRQ_NONE; -+ -+ WRITE_REG(sc, SAFE_HI_CLR, stat); /* IACK */ -+ -+ if ((stat & SAFE_INT_PE_DDONE)) { -+ /* -+ * Descriptor(s) done; scan the ring and -+ * process completed operations. -+ */ -+ spin_lock_irqsave(&sc->sc_ringmtx, flags); -+ while (sc->sc_back != sc->sc_front) { -+ struct safe_ringentry *re = sc->sc_back; -+ -+#ifdef SAFE_DEBUG -+ if (debug) { -+ safe_dump_ringstate(sc, __func__); -+ safe_dump_request(sc, __func__, re); -+ } -+#endif -+ /* -+ * safe_process marks ring entries that were allocated -+ * but not used with a csr of zero. This insures the -+ * ring front pointer never needs to be set backwards -+ * in the event that an entry is allocated but not used -+ * because of a setup error. -+ */ -+ DPRINTF(("%s re->re_desc.d_csr=0x%x\n", __FUNCTION__, re->re_desc.d_csr)); -+ if (re->re_desc.d_csr != 0) { -+ if (!SAFE_PE_CSR_IS_DONE(re->re_desc.d_csr)) { -+ DPRINTF(("%s !CSR_IS_DONE\n", __FUNCTION__)); -+ break; -+ } -+ if (!SAFE_PE_LEN_IS_DONE(re->re_desc.d_len)) { -+ DPRINTF(("%s !LEN_IS_DONE\n", __FUNCTION__)); -+ break; -+ } -+ sc->sc_nqchip--; -+ safe_callback(sc, re); -+ } -+ if (++(sc->sc_back) == sc->sc_ringtop) -+ sc->sc_back = sc->sc_ring; -+ } -+ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); -+ } -+ -+ /* -+ * Check to see if we got any DMA Error -+ */ -+ if (stat & SAFE_INT_PE_ERROR) { -+ printk("%s: dmaerr dmastat %08x\n", device_get_nameunit(sc->sc_dev), -+ (int)READ_REG(sc, SAFE_PE_DMASTAT)); -+ safestats.st_dmaerr++; -+ safe_totalreset(sc); -+#if 0 -+ safe_feed(sc); -+#endif -+ } -+ -+ if (sc->sc_needwakeup) { /* XXX check high watermark */ -+ int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); -+ DPRINTF(("%s: wakeup crypto %x\n", __func__, -+ sc->sc_needwakeup)); -+ sc->sc_needwakeup &= ~wakeup; -+ crypto_unblock(sc->sc_cid, wakeup); -+ } -+ -+ return IRQ_HANDLED; -+} -+ -+/* -+ * safe_feed() - post a request to chip -+ */ -+static void -+safe_feed(struct safe_softc *sc, struct safe_ringentry *re) -+{ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+#ifdef SAFE_DEBUG -+ if (debug) { -+ safe_dump_ringstate(sc, __func__); -+ safe_dump_request(sc, __func__, re); -+ } -+#endif -+ sc->sc_nqchip++; -+ if (sc->sc_nqchip > safestats.st_maxqchip) -+ safestats.st_maxqchip = sc->sc_nqchip; -+ /* poke h/w to check descriptor ring, any value can be written */ -+ WRITE_REG(sc, SAFE_HI_RD_DESCR, 0); -+} -+ -+#define N(a) (sizeof(a) / sizeof (a[0])) -+static void -+safe_setup_enckey(struct safe_session *ses, caddr_t key) -+{ -+ int i; -+ -+ bcopy(key, ses->ses_key, ses->ses_klen / 8); -+ -+ /* PE is little-endian, insure proper byte order */ -+ for (i = 0; i < N(ses->ses_key); i++) -+ ses->ses_key[i] = htole32(ses->ses_key[i]); -+} -+ -+static void -+safe_setup_mackey(struct safe_session *ses, int algo, caddr_t key, int klen) -+{ -+#ifdef HMAC_HACK -+ MD5_CTX md5ctx; -+ SHA1_CTX sha1ctx; -+ int i; -+ -+ -+ for (i = 0; i < klen; i++) -+ key[i] ^= HMAC_IPAD_VAL; -+ -+ if (algo == CRYPTO_MD5_HMAC) { -+ MD5Init(&md5ctx); -+ MD5Update(&md5ctx, key, klen); -+ MD5Update(&md5ctx, hmac_ipad_buffer, MD5_HMAC_BLOCK_LEN - klen); -+ bcopy(md5ctx.md5_st8, ses->ses_hminner, sizeof(md5ctx.md5_st8)); -+ } else { -+ SHA1Init(&sha1ctx); -+ SHA1Update(&sha1ctx, key, klen); -+ SHA1Update(&sha1ctx, hmac_ipad_buffer, -+ SHA1_HMAC_BLOCK_LEN - klen); -+ bcopy(sha1ctx.h.b32, ses->ses_hminner, sizeof(sha1ctx.h.b32)); -+ } -+ -+ for (i = 0; i < klen; i++) -+ key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); -+ -+ if (algo == CRYPTO_MD5_HMAC) { -+ MD5Init(&md5ctx); -+ MD5Update(&md5ctx, key, klen); -+ MD5Update(&md5ctx, hmac_opad_buffer, MD5_HMAC_BLOCK_LEN - klen); -+ bcopy(md5ctx.md5_st8, ses->ses_hmouter, sizeof(md5ctx.md5_st8)); -+ } else { -+ SHA1Init(&sha1ctx); -+ SHA1Update(&sha1ctx, key, klen); -+ SHA1Update(&sha1ctx, hmac_opad_buffer, -+ SHA1_HMAC_BLOCK_LEN - klen); -+ bcopy(sha1ctx.h.b32, ses->ses_hmouter, sizeof(sha1ctx.h.b32)); -+ } -+ -+ for (i = 0; i < klen; i++) -+ key[i] ^= HMAC_OPAD_VAL; -+ -+#if 0 -+ /* -+ * this code prevents SHA working on a BE host, -+ * so it is obviously wrong. I think the byte -+ * swap setup we do with the chip fixes this for us -+ */ -+ -+ /* PE is little-endian, insure proper byte order */ -+ for (i = 0; i < N(ses->ses_hminner); i++) { -+ ses->ses_hminner[i] = htole32(ses->ses_hminner[i]); -+ ses->ses_hmouter[i] = htole32(ses->ses_hmouter[i]); -+ } -+#endif -+#else /* HMAC_HACK */ -+ printk("safe: md5/sha not implemented\n"); -+#endif /* HMAC_HACK */ -+} -+#undef N -+ -+/* -+ * Allocate a new 'session' and return an encoded session id. 'sidp' -+ * contains our registration id, and should contain an encoded session -+ * id on successful allocation. -+ */ -+static int -+safe_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) -+{ -+ struct safe_softc *sc = device_get_softc(dev); -+ struct cryptoini *c, *encini = NULL, *macini = NULL; -+ struct safe_session *ses = NULL; -+ int sesn; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (sidp == NULL || cri == NULL || sc == NULL) -+ return (EINVAL); -+ -+ for (c = cri; c != NULL; c = c->cri_next) { -+ if (c->cri_alg == CRYPTO_MD5_HMAC || -+ c->cri_alg == CRYPTO_SHA1_HMAC || -+ c->cri_alg == CRYPTO_NULL_HMAC) { -+ if (macini) -+ return (EINVAL); -+ macini = c; -+ } else if (c->cri_alg == CRYPTO_DES_CBC || -+ c->cri_alg == CRYPTO_3DES_CBC || -+ c->cri_alg == CRYPTO_AES_CBC || -+ c->cri_alg == CRYPTO_NULL_CBC) { -+ if (encini) -+ return (EINVAL); -+ encini = c; -+ } else -+ return (EINVAL); -+ } -+ if (encini == NULL && macini == NULL) -+ return (EINVAL); -+ if (encini) { /* validate key length */ -+ switch (encini->cri_alg) { -+ case CRYPTO_DES_CBC: -+ if (encini->cri_klen != 64) -+ return (EINVAL); -+ break; -+ case CRYPTO_3DES_CBC: -+ if (encini->cri_klen != 192) -+ return (EINVAL); -+ break; -+ case CRYPTO_AES_CBC: -+ if (encini->cri_klen != 128 && -+ encini->cri_klen != 192 && -+ encini->cri_klen != 256) -+ return (EINVAL); -+ break; -+ } -+ } -+ -+ if (sc->sc_sessions == NULL) { -+ ses = sc->sc_sessions = (struct safe_session *) -+ kmalloc(sizeof(struct safe_session), SLAB_ATOMIC); -+ if (ses == NULL) -+ return (ENOMEM); -+ memset(ses, 0, sizeof(struct safe_session)); -+ sesn = 0; -+ sc->sc_nsessions = 1; -+ } else { -+ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { -+ if (sc->sc_sessions[sesn].ses_used == 0) { -+ ses = &sc->sc_sessions[sesn]; -+ break; -+ } -+ } -+ -+ if (ses == NULL) { -+ sesn = sc->sc_nsessions; -+ ses = (struct safe_session *) -+ kmalloc((sesn + 1) * sizeof(struct safe_session), SLAB_ATOMIC); -+ if (ses == NULL) -+ return (ENOMEM); -+ memset(ses, 0, (sesn + 1) * sizeof(struct safe_session)); -+ bcopy(sc->sc_sessions, ses, sesn * -+ sizeof(struct safe_session)); -+ bzero(sc->sc_sessions, sesn * -+ sizeof(struct safe_session)); -+ kfree(sc->sc_sessions); -+ sc->sc_sessions = ses; -+ ses = &sc->sc_sessions[sesn]; -+ sc->sc_nsessions++; -+ } -+ } -+ -+ bzero(ses, sizeof(struct safe_session)); -+ ses->ses_used = 1; -+ -+ if (encini) { -+ /* get an IV */ -+ /* XXX may read fewer than requested */ -+ read_random(ses->ses_iv, sizeof(ses->ses_iv)); -+ -+ ses->ses_klen = encini->cri_klen; -+ if (encini->cri_key != NULL) -+ safe_setup_enckey(ses, encini->cri_key); -+ } -+ -+ if (macini) { -+ ses->ses_mlen = macini->cri_mlen; -+ if (ses->ses_mlen == 0) { -+ if (macini->cri_alg == CRYPTO_MD5_HMAC) -+ ses->ses_mlen = MD5_HASH_LEN; -+ else -+ ses->ses_mlen = SHA1_HASH_LEN; -+ } -+ -+ if (macini->cri_key != NULL) { -+ safe_setup_mackey(ses, macini->cri_alg, macini->cri_key, -+ macini->cri_klen / 8); -+ } -+ } -+ -+ *sidp = SAFE_SID(device_get_unit(sc->sc_dev), sesn); -+ return (0); -+} -+ -+/* -+ * Deallocate a session. -+ */ -+static int -+safe_freesession(device_t dev, u_int64_t tid) -+{ -+ struct safe_softc *sc = device_get_softc(dev); -+ int session, ret; -+ u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (sc == NULL) -+ return (EINVAL); -+ -+ session = SAFE_SESSION(sid); -+ if (session < sc->sc_nsessions) { -+ bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session])); -+ ret = 0; -+ } else -+ ret = EINVAL; -+ return (ret); -+} -+ -+ -+static int -+safe_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ struct safe_softc *sc = device_get_softc(dev); -+ int err = 0, i, nicealign, uniform; -+ struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; -+ int bypass, oplen, ivsize; -+ caddr_t iv; -+ int16_t coffset; -+ struct safe_session *ses; -+ struct safe_ringentry *re; -+ struct safe_sarec *sa; -+ struct safe_pdesc *pd; -+ u_int32_t cmd0, cmd1, staterec; -+ unsigned long flags; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { -+ safestats.st_invalid++; -+ return (EINVAL); -+ } -+ if (SAFE_SESSION(crp->crp_sid) >= sc->sc_nsessions) { -+ safestats.st_badsession++; -+ return (EINVAL); -+ } -+ -+ spin_lock_irqsave(&sc->sc_ringmtx, flags); -+ if (sc->sc_front == sc->sc_back && sc->sc_nqchip != 0) { -+ safestats.st_ringfull++; -+ sc->sc_needwakeup |= CRYPTO_SYMQ; -+ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); -+ return (ERESTART); -+ } -+ re = sc->sc_front; -+ -+ staterec = re->re_sa.sa_staterec; /* save */ -+ /* NB: zero everything but the PE descriptor */ -+ bzero(&re->re_sa, sizeof(struct safe_ringentry) - sizeof(re->re_desc)); -+ re->re_sa.sa_staterec = staterec; /* restore */ -+ -+ re->re_crp = crp; -+ re->re_sesn = SAFE_SESSION(crp->crp_sid); -+ -+ re->re_src.nsegs = 0; -+ re->re_dst.nsegs = 0; -+ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ re->re_src_skb = (struct sk_buff *)crp->crp_buf; -+ re->re_dst_skb = (struct sk_buff *)crp->crp_buf; -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ re->re_src_io = (struct uio *)crp->crp_buf; -+ re->re_dst_io = (struct uio *)crp->crp_buf; -+ } else { -+ safestats.st_badflags++; -+ err = EINVAL; -+ goto errout; /* XXX we don't handle contiguous blocks! */ -+ } -+ -+ sa = &re->re_sa; -+ ses = &sc->sc_sessions[re->re_sesn]; -+ -+ crd1 = crp->crp_desc; -+ if (crd1 == NULL) { -+ safestats.st_nodesc++; -+ err = EINVAL; -+ goto errout; -+ } -+ crd2 = crd1->crd_next; -+ -+ cmd0 = SAFE_SA_CMD0_BASIC; /* basic group operation */ -+ cmd1 = 0; -+ if (crd2 == NULL) { -+ if (crd1->crd_alg == CRYPTO_MD5_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1_HMAC || -+ crd1->crd_alg == CRYPTO_NULL_HMAC) { -+ maccrd = crd1; -+ enccrd = NULL; -+ cmd0 |= SAFE_SA_CMD0_OP_HASH; -+ } else if (crd1->crd_alg == CRYPTO_DES_CBC || -+ crd1->crd_alg == CRYPTO_3DES_CBC || -+ crd1->crd_alg == CRYPTO_AES_CBC || -+ crd1->crd_alg == CRYPTO_NULL_CBC) { -+ maccrd = NULL; -+ enccrd = crd1; -+ cmd0 |= SAFE_SA_CMD0_OP_CRYPT; -+ } else { -+ safestats.st_badalg++; -+ err = EINVAL; -+ goto errout; -+ } -+ } else { -+ if ((crd1->crd_alg == CRYPTO_MD5_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1_HMAC || -+ crd1->crd_alg == CRYPTO_NULL_HMAC) && -+ (crd2->crd_alg == CRYPTO_DES_CBC || -+ crd2->crd_alg == CRYPTO_3DES_CBC || -+ crd2->crd_alg == CRYPTO_AES_CBC || -+ crd2->crd_alg == CRYPTO_NULL_CBC) && -+ ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { -+ maccrd = crd1; -+ enccrd = crd2; -+ } else if ((crd1->crd_alg == CRYPTO_DES_CBC || -+ crd1->crd_alg == CRYPTO_3DES_CBC || -+ crd1->crd_alg == CRYPTO_AES_CBC || -+ crd1->crd_alg == CRYPTO_NULL_CBC) && -+ (crd2->crd_alg == CRYPTO_MD5_HMAC || -+ crd2->crd_alg == CRYPTO_SHA1_HMAC || -+ crd2->crd_alg == CRYPTO_NULL_HMAC) && -+ (crd1->crd_flags & CRD_F_ENCRYPT)) { -+ enccrd = crd1; -+ maccrd = crd2; -+ } else { -+ safestats.st_badalg++; -+ err = EINVAL; -+ goto errout; -+ } -+ cmd0 |= SAFE_SA_CMD0_OP_BOTH; -+ } -+ -+ if (enccrd) { -+ if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) -+ safe_setup_enckey(ses, enccrd->crd_key); -+ -+ if (enccrd->crd_alg == CRYPTO_DES_CBC) { -+ cmd0 |= SAFE_SA_CMD0_DES; -+ cmd1 |= SAFE_SA_CMD1_CBC; -+ ivsize = 2*sizeof(u_int32_t); -+ } else if (enccrd->crd_alg == CRYPTO_3DES_CBC) { -+ cmd0 |= SAFE_SA_CMD0_3DES; -+ cmd1 |= SAFE_SA_CMD1_CBC; -+ ivsize = 2*sizeof(u_int32_t); -+ } else if (enccrd->crd_alg == CRYPTO_AES_CBC) { -+ cmd0 |= SAFE_SA_CMD0_AES; -+ cmd1 |= SAFE_SA_CMD1_CBC; -+ if (ses->ses_klen == 128) -+ cmd1 |= SAFE_SA_CMD1_AES128; -+ else if (ses->ses_klen == 192) -+ cmd1 |= SAFE_SA_CMD1_AES192; -+ else -+ cmd1 |= SAFE_SA_CMD1_AES256; -+ ivsize = 4*sizeof(u_int32_t); -+ } else { -+ cmd0 |= SAFE_SA_CMD0_CRYPT_NULL; -+ ivsize = 0; -+ } -+ -+ /* -+ * Setup encrypt/decrypt state. When using basic ops -+ * we can't use an inline IV because hash/crypt offset -+ * must be from the end of the IV to the start of the -+ * crypt data and this leaves out the preceding header -+ * from the hash calculation. Instead we place the IV -+ * in the state record and set the hash/crypt offset to -+ * copy both the header+IV. -+ */ -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) { -+ cmd0 |= SAFE_SA_CMD0_OUTBOUND; -+ -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) -+ iv = enccrd->crd_iv; -+ else -+ iv = (caddr_t) ses->ses_iv; -+ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ enccrd->crd_inject, ivsize, iv); -+ } -+ bcopy(iv, re->re_sastate.sa_saved_iv, ivsize); -+ /* make iv LE */ -+ for (i = 0; i < ivsize/sizeof(re->re_sastate.sa_saved_iv[0]); i++) -+ re->re_sastate.sa_saved_iv[i] = -+ cpu_to_le32(re->re_sastate.sa_saved_iv[i]); -+ cmd0 |= SAFE_SA_CMD0_IVLD_STATE | SAFE_SA_CMD0_SAVEIV; -+ re->re_flags |= SAFE_QFLAGS_COPYOUTIV; -+ } else { -+ cmd0 |= SAFE_SA_CMD0_INBOUND; -+ -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) { -+ bcopy(enccrd->crd_iv, -+ re->re_sastate.sa_saved_iv, ivsize); -+ } else { -+ crypto_copydata(crp->crp_flags, crp->crp_buf, -+ enccrd->crd_inject, ivsize, -+ (caddr_t)re->re_sastate.sa_saved_iv); -+ } -+ /* make iv LE */ -+ for (i = 0; i < ivsize/sizeof(re->re_sastate.sa_saved_iv[0]); i++) -+ re->re_sastate.sa_saved_iv[i] = -+ cpu_to_le32(re->re_sastate.sa_saved_iv[i]); -+ cmd0 |= SAFE_SA_CMD0_IVLD_STATE; -+ } -+ /* -+ * For basic encryption use the zero pad algorithm. -+ * This pads results to an 8-byte boundary and -+ * suppresses padding verification for inbound (i.e. -+ * decrypt) operations. -+ * -+ * NB: Not sure if the 8-byte pad boundary is a problem. -+ */ -+ cmd0 |= SAFE_SA_CMD0_PAD_ZERO; -+ -+ /* XXX assert key bufs have the same size */ -+ bcopy(ses->ses_key, sa->sa_key, sizeof(sa->sa_key)); -+ } -+ -+ if (maccrd) { -+ if (maccrd->crd_flags & CRD_F_KEY_EXPLICIT) { -+ safe_setup_mackey(ses, maccrd->crd_alg, -+ maccrd->crd_key, maccrd->crd_klen / 8); -+ } -+ -+ if (maccrd->crd_alg == CRYPTO_MD5_HMAC) { -+ cmd0 |= SAFE_SA_CMD0_MD5; -+ cmd1 |= SAFE_SA_CMD1_HMAC; /* NB: enable HMAC */ -+ } else if (maccrd->crd_alg == CRYPTO_SHA1_HMAC) { -+ cmd0 |= SAFE_SA_CMD0_SHA1; -+ cmd1 |= SAFE_SA_CMD1_HMAC; /* NB: enable HMAC */ -+ } else { -+ cmd0 |= SAFE_SA_CMD0_HASH_NULL; -+ } -+ /* -+ * Digest data is loaded from the SA and the hash -+ * result is saved to the state block where we -+ * retrieve it for return to the caller. -+ */ -+ /* XXX assert digest bufs have the same size */ -+ bcopy(ses->ses_hminner, sa->sa_indigest, -+ sizeof(sa->sa_indigest)); -+ bcopy(ses->ses_hmouter, sa->sa_outdigest, -+ sizeof(sa->sa_outdigest)); -+ -+ cmd0 |= SAFE_SA_CMD0_HSLD_SA | SAFE_SA_CMD0_SAVEHASH; -+ re->re_flags |= SAFE_QFLAGS_COPYOUTICV; -+ } -+ -+ if (enccrd && maccrd) { -+ /* -+ * The offset from hash data to the start of -+ * crypt data is the difference in the skips. -+ */ -+ bypass = maccrd->crd_skip; -+ coffset = enccrd->crd_skip - maccrd->crd_skip; -+ if (coffset < 0) { -+ DPRINTF(("%s: hash does not precede crypt; " -+ "mac skip %u enc skip %u\n", -+ __func__, maccrd->crd_skip, enccrd->crd_skip)); -+ safestats.st_skipmismatch++; -+ err = EINVAL; -+ goto errout; -+ } -+ oplen = enccrd->crd_skip + enccrd->crd_len; -+ if (maccrd->crd_skip + maccrd->crd_len != oplen) { -+ DPRINTF(("%s: hash amount %u != crypt amount %u\n", -+ __func__, maccrd->crd_skip + maccrd->crd_len, -+ oplen)); -+ safestats.st_lenmismatch++; -+ err = EINVAL; -+ goto errout; -+ } -+#ifdef SAFE_DEBUG -+ if (debug) { -+ printf("mac: skip %d, len %d, inject %d\n", -+ maccrd->crd_skip, maccrd->crd_len, -+ maccrd->crd_inject); -+ printf("enc: skip %d, len %d, inject %d\n", -+ enccrd->crd_skip, enccrd->crd_len, -+ enccrd->crd_inject); -+ printf("bypass %d coffset %d oplen %d\n", -+ bypass, coffset, oplen); -+ } -+#endif -+ if (coffset & 3) { /* offset must be 32-bit aligned */ -+ DPRINTF(("%s: coffset %u misaligned\n", -+ __func__, coffset)); -+ safestats.st_coffmisaligned++; -+ err = EINVAL; -+ goto errout; -+ } -+ coffset >>= 2; -+ if (coffset > 255) { /* offset must be <256 dwords */ -+ DPRINTF(("%s: coffset %u too big\n", -+ __func__, coffset)); -+ safestats.st_cofftoobig++; -+ err = EINVAL; -+ goto errout; -+ } -+ /* -+ * Tell the hardware to copy the header to the output. -+ * The header is defined as the data from the end of -+ * the bypass to the start of data to be encrypted. -+ * Typically this is the inline IV. Note that you need -+ * to do this even if src+dst are the same; it appears -+ * that w/o this bit the crypted data is written -+ * immediately after the bypass data. -+ */ -+ cmd1 |= SAFE_SA_CMD1_HDRCOPY; -+ /* -+ * Disable IP header mutable bit handling. This is -+ * needed to get correct HMAC calculations. -+ */ -+ cmd1 |= SAFE_SA_CMD1_MUTABLE; -+ } else { -+ if (enccrd) { -+ bypass = enccrd->crd_skip; -+ oplen = bypass + enccrd->crd_len; -+ } else { -+ bypass = maccrd->crd_skip; -+ oplen = bypass + maccrd->crd_len; -+ } -+ coffset = 0; -+ } -+ /* XXX verify multiple of 4 when using s/g */ -+ if (bypass > 96) { /* bypass offset must be <= 96 bytes */ -+ DPRINTF(("%s: bypass %u too big\n", __func__, bypass)); -+ safestats.st_bypasstoobig++; -+ err = EINVAL; -+ goto errout; -+ } -+ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ if (pci_map_skb(sc, &re->re_src, re->re_src_skb)) { -+ safestats.st_noload++; -+ err = ENOMEM; -+ goto errout; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ if (pci_map_uio(sc, &re->re_src, re->re_src_io)) { -+ safestats.st_noload++; -+ err = ENOMEM; -+ goto errout; -+ } -+ } -+ nicealign = safe_dmamap_aligned(sc, &re->re_src); -+ uniform = safe_dmamap_uniform(sc, &re->re_src); -+ -+ DPRINTF(("src nicealign %u uniform %u nsegs %u\n", -+ nicealign, uniform, re->re_src.nsegs)); -+ if (re->re_src.nsegs > 1) { -+ re->re_desc.d_src = sc->sc_spalloc.dma_paddr + -+ ((caddr_t) sc->sc_spfree - (caddr_t) sc->sc_spring); -+ for (i = 0; i < re->re_src_nsegs; i++) { -+ /* NB: no need to check if there's space */ -+ pd = sc->sc_spfree; -+ if (++(sc->sc_spfree) == sc->sc_springtop) -+ sc->sc_spfree = sc->sc_spring; -+ -+ KASSERT((pd->pd_flags&3) == 0 || -+ (pd->pd_flags&3) == SAFE_PD_DONE, -+ ("bogus source particle descriptor; flags %x", -+ pd->pd_flags)); -+ pd->pd_addr = re->re_src_segs[i].ds_addr; -+ pd->pd_size = re->re_src_segs[i].ds_len; -+ pd->pd_flags = SAFE_PD_READY; -+ } -+ cmd0 |= SAFE_SA_CMD0_IGATHER; -+ } else { -+ /* -+ * No need for gather, reference the operand directly. -+ */ -+ re->re_desc.d_src = re->re_src_segs[0].ds_addr; -+ } -+ -+ if (enccrd == NULL && maccrd != NULL) { -+ /* -+ * Hash op; no destination needed. -+ */ -+ } else { -+ if (crp->crp_flags & (CRYPTO_F_IOV|CRYPTO_F_SKBUF)) { -+ if (!nicealign) { -+ safestats.st_iovmisaligned++; -+ err = EINVAL; -+ goto errout; -+ } -+ if (uniform != 1) { -+ device_printf(sc->sc_dev, "!uniform source\n"); -+ if (!uniform) { -+ /* -+ * There's no way to handle the DMA -+ * requirements with this uio. We -+ * could create a separate DMA area for -+ * the result and then copy it back, -+ * but for now we just bail and return -+ * an error. Note that uio requests -+ * > SAFE_MAX_DSIZE are handled because -+ * the DMA map and segment list for the -+ * destination wil result in a -+ * destination particle list that does -+ * the necessary scatter DMA. -+ */ -+ safestats.st_iovnotuniform++; -+ err = EINVAL; -+ goto errout; -+ } -+ } else -+ re->re_dst = re->re_src; -+ } else { -+ safestats.st_badflags++; -+ err = EINVAL; -+ goto errout; -+ } -+ -+ if (re->re_dst.nsegs > 1) { -+ re->re_desc.d_dst = sc->sc_dpalloc.dma_paddr + -+ ((caddr_t) sc->sc_dpfree - (caddr_t) sc->sc_dpring); -+ for (i = 0; i < re->re_dst_nsegs; i++) { -+ pd = sc->sc_dpfree; -+ KASSERT((pd->pd_flags&3) == 0 || -+ (pd->pd_flags&3) == SAFE_PD_DONE, -+ ("bogus dest particle descriptor; flags %x", -+ pd->pd_flags)); -+ if (++(sc->sc_dpfree) == sc->sc_dpringtop) -+ sc->sc_dpfree = sc->sc_dpring; -+ pd->pd_addr = re->re_dst_segs[i].ds_addr; -+ pd->pd_flags = SAFE_PD_READY; -+ } -+ cmd0 |= SAFE_SA_CMD0_OSCATTER; -+ } else { -+ /* -+ * No need for scatter, reference the operand directly. -+ */ -+ re->re_desc.d_dst = re->re_dst_segs[0].ds_addr; -+ } -+ } -+ -+ /* -+ * All done with setup; fillin the SA command words -+ * and the packet engine descriptor. The operation -+ * is now ready for submission to the hardware. -+ */ -+ sa->sa_cmd0 = cmd0 | SAFE_SA_CMD0_IPCI | SAFE_SA_CMD0_OPCI; -+ sa->sa_cmd1 = cmd1 -+ | (coffset << SAFE_SA_CMD1_OFFSET_S) -+ | SAFE_SA_CMD1_SAREV1 /* Rev 1 SA data structure */ -+ | SAFE_SA_CMD1_SRPCI -+ ; -+ /* -+ * NB: the order of writes is important here. In case the -+ * chip is scanning the ring because of an outstanding request -+ * it might nab this one too. In that case we need to make -+ * sure the setup is complete before we write the length -+ * field of the descriptor as it signals the descriptor is -+ * ready for processing. -+ */ -+ re->re_desc.d_csr = SAFE_PE_CSR_READY | SAFE_PE_CSR_SAPCI; -+ if (maccrd) -+ re->re_desc.d_csr |= SAFE_PE_CSR_LOADSA | SAFE_PE_CSR_HASHFINAL; -+ wmb(); -+ re->re_desc.d_len = oplen -+ | SAFE_PE_LEN_READY -+ | (bypass << SAFE_PE_LEN_BYPASS_S) -+ ; -+ -+ safestats.st_ipackets++; -+ safestats.st_ibytes += oplen; -+ -+ if (++(sc->sc_front) == sc->sc_ringtop) -+ sc->sc_front = sc->sc_ring; -+ -+ /* XXX honor batching */ -+ safe_feed(sc, re); -+ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); -+ return (0); -+ -+errout: -+ if (re->re_src.map != re->re_dst.map) -+ pci_unmap_operand(sc, &re->re_dst); -+ if (re->re_src.map) -+ pci_unmap_operand(sc, &re->re_src); -+ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); -+ if (err != ERESTART) { -+ crp->crp_etype = err; -+ crypto_done(crp); -+ } else { -+ sc->sc_needwakeup |= CRYPTO_SYMQ; -+ } -+ return (err); -+} -+ -+static void -+safe_callback(struct safe_softc *sc, struct safe_ringentry *re) -+{ -+ struct cryptop *crp = (struct cryptop *)re->re_crp; -+ struct cryptodesc *crd; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ safestats.st_opackets++; -+ safestats.st_obytes += re->re_dst.mapsize; -+ -+ if (re->re_desc.d_csr & SAFE_PE_CSR_STATUS) { -+ device_printf(sc->sc_dev, "csr 0x%x cmd0 0x%x cmd1 0x%x\n", -+ re->re_desc.d_csr, -+ re->re_sa.sa_cmd0, re->re_sa.sa_cmd1); -+ safestats.st_peoperr++; -+ crp->crp_etype = EIO; /* something more meaningful? */ -+ } -+ -+ if (re->re_dst.map != NULL && re->re_dst.map != re->re_src.map) -+ pci_unmap_operand(sc, &re->re_dst); -+ pci_unmap_operand(sc, &re->re_src); -+ -+ /* -+ * If result was written to a differet mbuf chain, swap -+ * it in as the return value and reclaim the original. -+ */ -+ if ((crp->crp_flags & CRYPTO_F_SKBUF) && re->re_src_skb != re->re_dst_skb) { -+ device_printf(sc->sc_dev, "no CRYPTO_F_SKBUF swapping support\n"); -+ /* kfree_skb(skb) */ -+ /* crp->crp_buf = (caddr_t)re->re_dst_skb */ -+ return; -+ } -+ -+ if (re->re_flags & SAFE_QFLAGS_COPYOUTIV) { -+ /* copy out IV for future use */ -+ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { -+ int i; -+ int ivsize; -+ -+ if (crd->crd_alg == CRYPTO_DES_CBC || -+ crd->crd_alg == CRYPTO_3DES_CBC) { -+ ivsize = 2*sizeof(u_int32_t); -+ } else if (crd->crd_alg == CRYPTO_AES_CBC) { -+ ivsize = 4*sizeof(u_int32_t); -+ } else -+ continue; -+ crypto_copydata(crp->crp_flags, crp->crp_buf, -+ crd->crd_skip + crd->crd_len - ivsize, ivsize, -+ (caddr_t)sc->sc_sessions[re->re_sesn].ses_iv); -+ for (i = 0; -+ i < ivsize/sizeof(sc->sc_sessions[re->re_sesn].ses_iv[0]); -+ i++) -+ sc->sc_sessions[re->re_sesn].ses_iv[i] = -+ cpu_to_le32(sc->sc_sessions[re->re_sesn].ses_iv[i]); -+ break; -+ } -+ } -+ -+ if (re->re_flags & SAFE_QFLAGS_COPYOUTICV) { -+ /* copy out ICV result */ -+ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { -+ if (!(crd->crd_alg == CRYPTO_MD5_HMAC || -+ crd->crd_alg == CRYPTO_SHA1_HMAC || -+ crd->crd_alg == CRYPTO_NULL_HMAC)) -+ continue; -+ if (crd->crd_alg == CRYPTO_SHA1_HMAC) { -+ /* -+ * SHA-1 ICV's are byte-swapped; fix 'em up -+ * before copy them to their destination. -+ */ -+ re->re_sastate.sa_saved_indigest[0] = -+ cpu_to_be32(re->re_sastate.sa_saved_indigest[0]); -+ re->re_sastate.sa_saved_indigest[1] = -+ cpu_to_be32(re->re_sastate.sa_saved_indigest[1]); -+ re->re_sastate.sa_saved_indigest[2] = -+ cpu_to_be32(re->re_sastate.sa_saved_indigest[2]); -+ } else { -+ re->re_sastate.sa_saved_indigest[0] = -+ cpu_to_le32(re->re_sastate.sa_saved_indigest[0]); -+ re->re_sastate.sa_saved_indigest[1] = -+ cpu_to_le32(re->re_sastate.sa_saved_indigest[1]); -+ re->re_sastate.sa_saved_indigest[2] = -+ cpu_to_le32(re->re_sastate.sa_saved_indigest[2]); -+ } -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, -+ sc->sc_sessions[re->re_sesn].ses_mlen, -+ (caddr_t)re->re_sastate.sa_saved_indigest); -+ break; -+ } -+ } -+ crypto_done(crp); -+} -+ -+ -+#if defined(CONFIG_OCF_RANDOMHARVEST) && !defined(SAFE_NO_RNG) -+#define SAFE_RNG_MAXWAIT 1000 -+ -+static void -+safe_rng_init(struct safe_softc *sc) -+{ -+ u_int32_t w, v; -+ int i; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ WRITE_REG(sc, SAFE_RNG_CTRL, 0); -+ /* use default value according to the manual */ -+ WRITE_REG(sc, SAFE_RNG_CNFG, 0x834); /* magic from SafeNet */ -+ WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); -+ -+ /* -+ * There is a bug in rev 1.0 of the 1140 that when the RNG -+ * is brought out of reset the ready status flag does not -+ * work until the RNG has finished its internal initialization. -+ * -+ * So in order to determine the device is through its -+ * initialization we must read the data register, using the -+ * status reg in the read in case it is initialized. Then read -+ * the data register until it changes from the first read. -+ * Once it changes read the data register until it changes -+ * again. At this time the RNG is considered initialized. -+ * This could take between 750ms - 1000ms in time. -+ */ -+ i = 0; -+ w = READ_REG(sc, SAFE_RNG_OUT); -+ do { -+ v = READ_REG(sc, SAFE_RNG_OUT); -+ if (v != w) { -+ w = v; -+ break; -+ } -+ DELAY(10); -+ } while (++i < SAFE_RNG_MAXWAIT); -+ -+ /* Wait Until data changes again */ -+ i = 0; -+ do { -+ v = READ_REG(sc, SAFE_RNG_OUT); -+ if (v != w) -+ break; -+ DELAY(10); -+ } while (++i < SAFE_RNG_MAXWAIT); -+} -+ -+static __inline void -+safe_rng_disable_short_cycle(struct safe_softc *sc) -+{ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ WRITE_REG(sc, SAFE_RNG_CTRL, -+ READ_REG(sc, SAFE_RNG_CTRL) &~ SAFE_RNG_CTRL_SHORTEN); -+} -+ -+static __inline void -+safe_rng_enable_short_cycle(struct safe_softc *sc) -+{ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ WRITE_REG(sc, SAFE_RNG_CTRL, -+ READ_REG(sc, SAFE_RNG_CTRL) | SAFE_RNG_CTRL_SHORTEN); -+} -+ -+static __inline u_int32_t -+safe_rng_read(struct safe_softc *sc) -+{ -+ int i; -+ -+ i = 0; -+ while (READ_REG(sc, SAFE_RNG_STAT) != 0 && ++i < SAFE_RNG_MAXWAIT) -+ ; -+ return READ_REG(sc, SAFE_RNG_OUT); -+} -+ -+static int -+safe_read_random(void *arg, u_int32_t *buf, int maxwords) -+{ -+ struct safe_softc *sc = (struct safe_softc *) arg; -+ int i, rc; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ safestats.st_rng++; -+ /* -+ * Fetch the next block of data. -+ */ -+ if (maxwords > safe_rngbufsize) -+ maxwords = safe_rngbufsize; -+ if (maxwords > SAFE_RNG_MAXBUFSIZ) -+ maxwords = SAFE_RNG_MAXBUFSIZ; -+retry: -+ /* read as much as we can */ -+ for (rc = 0; rc < maxwords; rc++) { -+ if (READ_REG(sc, SAFE_RNG_STAT) != 0) -+ break; -+ buf[rc] = READ_REG(sc, SAFE_RNG_OUT); -+ } -+ if (rc == 0) -+ return 0; -+ /* -+ * Check the comparator alarm count and reset the h/w if -+ * it exceeds our threshold. This guards against the -+ * hardware oscillators resonating with external signals. -+ */ -+ if (READ_REG(sc, SAFE_RNG_ALM_CNT) > safe_rngmaxalarm) { -+ u_int32_t freq_inc, w; -+ -+ DPRINTF(("%s: alarm count %u exceeds threshold %u\n", __func__, -+ (unsigned)READ_REG(sc, SAFE_RNG_ALM_CNT), safe_rngmaxalarm)); -+ safestats.st_rngalarm++; -+ safe_rng_enable_short_cycle(sc); -+ freq_inc = 18; -+ for (i = 0; i < 64; i++) { -+ w = READ_REG(sc, SAFE_RNG_CNFG); -+ freq_inc = ((w + freq_inc) & 0x3fL); -+ w = ((w & ~0x3fL) | freq_inc); -+ WRITE_REG(sc, SAFE_RNG_CNFG, w); -+ -+ WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); -+ -+ (void) safe_rng_read(sc); -+ DELAY(25); -+ -+ if (READ_REG(sc, SAFE_RNG_ALM_CNT) == 0) { -+ safe_rng_disable_short_cycle(sc); -+ goto retry; -+ } -+ freq_inc = 1; -+ } -+ safe_rng_disable_short_cycle(sc); -+ } else -+ WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); -+ -+ return(rc); -+} -+#endif /* defined(CONFIG_OCF_RANDOMHARVEST) && !defined(SAFE_NO_RNG) */ -+ -+ -+/* -+ * Resets the board. Values in the regesters are left as is -+ * from the reset (i.e. initial values are assigned elsewhere). -+ */ -+static void -+safe_reset_board(struct safe_softc *sc) -+{ -+ u_int32_t v; -+ /* -+ * Reset the device. The manual says no delay -+ * is needed between marking and clearing reset. -+ */ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ v = READ_REG(sc, SAFE_PE_DMACFG) &~ -+ (SAFE_PE_DMACFG_PERESET | SAFE_PE_DMACFG_PDRRESET | -+ SAFE_PE_DMACFG_SGRESET); -+ WRITE_REG(sc, SAFE_PE_DMACFG, v -+ | SAFE_PE_DMACFG_PERESET -+ | SAFE_PE_DMACFG_PDRRESET -+ | SAFE_PE_DMACFG_SGRESET); -+ WRITE_REG(sc, SAFE_PE_DMACFG, v); -+} -+ -+/* -+ * Initialize registers we need to touch only once. -+ */ -+static void -+safe_init_board(struct safe_softc *sc) -+{ -+ u_int32_t v, dwords; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ v = READ_REG(sc, SAFE_PE_DMACFG); -+ v &=~ ( SAFE_PE_DMACFG_PEMODE -+ | SAFE_PE_DMACFG_FSENA /* failsafe enable */ -+ | SAFE_PE_DMACFG_GPRPCI /* gather ring on PCI */ -+ | SAFE_PE_DMACFG_SPRPCI /* scatter ring on PCI */ -+ | SAFE_PE_DMACFG_ESDESC /* endian-swap descriptors */ -+ | SAFE_PE_DMACFG_ESPDESC /* endian-swap part. desc's */ -+ | SAFE_PE_DMACFG_ESSA /* endian-swap SA's */ -+ | SAFE_PE_DMACFG_ESPACKET /* swap the packet data */ -+ ); -+ v |= SAFE_PE_DMACFG_FSENA /* failsafe enable */ -+ | SAFE_PE_DMACFG_GPRPCI /* gather ring on PCI */ -+ | SAFE_PE_DMACFG_SPRPCI /* scatter ring on PCI */ -+ | SAFE_PE_DMACFG_ESDESC /* endian-swap descriptors */ -+ | SAFE_PE_DMACFG_ESPDESC /* endian-swap part. desc's */ -+ | SAFE_PE_DMACFG_ESSA /* endian-swap SA's */ -+#if 0 -+ | SAFE_PE_DMACFG_ESPACKET /* swap the packet data */ -+#endif -+ ; -+ WRITE_REG(sc, SAFE_PE_DMACFG, v); -+ -+#ifdef __BIG_ENDIAN -+ /* tell the safenet that we are 4321 and not 1234 */ -+ WRITE_REG(sc, SAFE_ENDIAN, 0xe4e41b1b); -+#endif -+ -+ if (sc->sc_chiprev == SAFE_REV(1,0)) { -+ /* -+ * Avoid large PCI DMA transfers. Rev 1.0 has a bug where -+ * "target mode transfers" done while the chip is DMA'ing -+ * >1020 bytes cause the hardware to lockup. To avoid this -+ * we reduce the max PCI transfer size and use small source -+ * particle descriptors (<= 256 bytes). -+ */ -+ WRITE_REG(sc, SAFE_DMA_CFG, 256); -+ device_printf(sc->sc_dev, -+ "Reduce max DMA size to %u words for rev %u.%u WAR\n", -+ (unsigned) ((READ_REG(sc, SAFE_DMA_CFG)>>2) & 0xff), -+ (unsigned) SAFE_REV_MAJ(sc->sc_chiprev), -+ (unsigned) SAFE_REV_MIN(sc->sc_chiprev)); -+ sc->sc_max_dsize = 256; -+ } else { -+ sc->sc_max_dsize = SAFE_MAX_DSIZE; -+ } -+ -+ /* NB: operands+results are overlaid */ -+ WRITE_REG(sc, SAFE_PE_PDRBASE, sc->sc_ringalloc.dma_paddr); -+ WRITE_REG(sc, SAFE_PE_RDRBASE, sc->sc_ringalloc.dma_paddr); -+ /* -+ * Configure ring entry size and number of items in the ring. -+ */ -+ KASSERT((sizeof(struct safe_ringentry) % sizeof(u_int32_t)) == 0, -+ ("PE ring entry not 32-bit aligned!")); -+ dwords = sizeof(struct safe_ringentry) / sizeof(u_int32_t); -+ WRITE_REG(sc, SAFE_PE_RINGCFG, -+ (dwords << SAFE_PE_RINGCFG_OFFSET_S) | SAFE_MAX_NQUEUE); -+ WRITE_REG(sc, SAFE_PE_RINGPOLL, 0); /* disable polling */ -+ -+ WRITE_REG(sc, SAFE_PE_GRNGBASE, sc->sc_spalloc.dma_paddr); -+ WRITE_REG(sc, SAFE_PE_SRNGBASE, sc->sc_dpalloc.dma_paddr); -+ WRITE_REG(sc, SAFE_PE_PARTSIZE, -+ (SAFE_TOTAL_DPART<<16) | SAFE_TOTAL_SPART); -+ /* -+ * NB: destination particles are fixed size. We use -+ * an mbuf cluster and require all results go to -+ * clusters or smaller. -+ */ -+ WRITE_REG(sc, SAFE_PE_PARTCFG, sc->sc_max_dsize); -+ -+ /* it's now safe to enable PE mode, do it */ -+ WRITE_REG(sc, SAFE_PE_DMACFG, v | SAFE_PE_DMACFG_PEMODE); -+ -+ /* -+ * Configure hardware to use level-triggered interrupts and -+ * to interrupt after each descriptor is processed. -+ */ -+ WRITE_REG(sc, SAFE_HI_CFG, SAFE_HI_CFG_LEVEL); -+ WRITE_REG(sc, SAFE_HI_CLR, 0xffffffff); -+ WRITE_REG(sc, SAFE_HI_DESC_CNT, 1); -+ WRITE_REG(sc, SAFE_HI_MASK, SAFE_INT_PE_DDONE | SAFE_INT_PE_ERROR); -+} -+ -+ -+/* -+ * Clean up after a chip crash. -+ * It is assumed that the caller in splimp() -+ */ -+static void -+safe_cleanchip(struct safe_softc *sc) -+{ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (sc->sc_nqchip != 0) { -+ struct safe_ringentry *re = sc->sc_back; -+ -+ while (re != sc->sc_front) { -+ if (re->re_desc.d_csr != 0) -+ safe_free_entry(sc, re); -+ if (++re == sc->sc_ringtop) -+ re = sc->sc_ring; -+ } -+ sc->sc_back = re; -+ sc->sc_nqchip = 0; -+ } -+} -+ -+/* -+ * free a safe_q -+ * It is assumed that the caller is within splimp(). -+ */ -+static int -+safe_free_entry(struct safe_softc *sc, struct safe_ringentry *re) -+{ -+ struct cryptop *crp; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ /* -+ * Free header MCR -+ */ -+ if ((re->re_dst_skb != NULL) && (re->re_src_skb != re->re_dst_skb)) -+#ifdef NOTYET -+ m_freem(re->re_dst_m); -+#else -+ printk("%s,%d: SKB not supported\n", __FILE__, __LINE__); -+#endif -+ -+ crp = (struct cryptop *)re->re_crp; -+ -+ re->re_desc.d_csr = 0; -+ -+ crp->crp_etype = EFAULT; -+ crypto_done(crp); -+ return(0); -+} -+ -+/* -+ * Routine to reset the chip and clean up. -+ * It is assumed that the caller is in splimp() -+ */ -+static void -+safe_totalreset(struct safe_softc *sc) -+{ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ safe_reset_board(sc); -+ safe_init_board(sc); -+ safe_cleanchip(sc); -+} -+ -+/* -+ * Is the operand suitable aligned for direct DMA. Each -+ * segment must be aligned on a 32-bit boundary and all -+ * but the last segment must be a multiple of 4 bytes. -+ */ -+static int -+safe_dmamap_aligned(struct safe_softc *sc, const struct safe_operand *op) -+{ -+ int i; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ for (i = 0; i < op->nsegs; i++) { -+ if (op->segs[i].ds_addr & 3) -+ return (0); -+ if (i != (op->nsegs - 1) && (op->segs[i].ds_len & 3)) -+ return (0); -+ } -+ return (1); -+} -+ -+/* -+ * Is the operand suitable for direct DMA as the destination -+ * of an operation. The hardware requires that each ``particle'' -+ * but the last in an operation result have the same size. We -+ * fix that size at SAFE_MAX_DSIZE bytes. This routine returns -+ * 0 if some segment is not a multiple of of this size, 1 if all -+ * segments are exactly this size, or 2 if segments are at worst -+ * a multple of this size. -+ */ -+static int -+safe_dmamap_uniform(struct safe_softc *sc, const struct safe_operand *op) -+{ -+ int result = 1; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (op->nsegs > 0) { -+ int i; -+ -+ for (i = 0; i < op->nsegs-1; i++) { -+ if (op->segs[i].ds_len % sc->sc_max_dsize) -+ return (0); -+ if (op->segs[i].ds_len != sc->sc_max_dsize) -+ result = 2; -+ } -+ } -+ return (result); -+} -+ -+static int -+safe_kprocess(device_t dev, struct cryptkop *krp, int hint) -+{ -+ struct safe_softc *sc = device_get_softc(dev); -+ struct safe_pkq *q; -+ unsigned long flags; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (sc == NULL) { -+ krp->krp_status = EINVAL; -+ goto err; -+ } -+ -+ if (krp->krp_op != CRK_MOD_EXP) { -+ krp->krp_status = EOPNOTSUPP; -+ goto err; -+ } -+ -+ q = (struct safe_pkq *) kmalloc(sizeof(*q), GFP_KERNEL); -+ if (q == NULL) { -+ krp->krp_status = ENOMEM; -+ goto err; -+ } -+ memset(q, 0, sizeof(*q)); -+ q->pkq_krp = krp; -+ INIT_LIST_HEAD(&q->pkq_list); -+ -+ spin_lock_irqsave(&sc->sc_pkmtx, flags); -+ list_add_tail(&q->pkq_list, &sc->sc_pkq); -+ safe_kfeed(sc); -+ spin_unlock_irqrestore(&sc->sc_pkmtx, flags); -+ return (0); -+ -+err: -+ crypto_kdone(krp); -+ return (0); -+} -+ -+#define SAFE_CRK_PARAM_BASE 0 -+#define SAFE_CRK_PARAM_EXP 1 -+#define SAFE_CRK_PARAM_MOD 2 -+ -+static int -+safe_kstart(struct safe_softc *sc) -+{ -+ struct cryptkop *krp = sc->sc_pkq_cur->pkq_krp; -+ int exp_bits, mod_bits, base_bits; -+ u_int32_t op, a_off, b_off, c_off, d_off; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (krp->krp_iparams < 3 || krp->krp_oparams != 1) { -+ krp->krp_status = EINVAL; -+ return (1); -+ } -+ -+ base_bits = safe_ksigbits(sc, &krp->krp_param[SAFE_CRK_PARAM_BASE]); -+ if (base_bits > 2048) -+ goto too_big; -+ if (base_bits <= 0) /* 5. base not zero */ -+ goto too_small; -+ -+ exp_bits = safe_ksigbits(sc, &krp->krp_param[SAFE_CRK_PARAM_EXP]); -+ if (exp_bits > 2048) -+ goto too_big; -+ if (exp_bits <= 0) /* 1. exponent word length > 0 */ -+ goto too_small; /* 4. exponent not zero */ -+ -+ mod_bits = safe_ksigbits(sc, &krp->krp_param[SAFE_CRK_PARAM_MOD]); -+ if (mod_bits > 2048) -+ goto too_big; -+ if (mod_bits <= 32) /* 2. modulus word length > 1 */ -+ goto too_small; /* 8. MSW of modulus != zero */ -+ if (mod_bits < exp_bits) /* 3 modulus len >= exponent len */ -+ goto too_small; -+ if ((krp->krp_param[SAFE_CRK_PARAM_MOD].crp_p[0] & 1) == 0) -+ goto bad_domain; /* 6. modulus is odd */ -+ if (mod_bits > krp->krp_param[krp->krp_iparams].crp_nbits) -+ goto too_small; /* make sure result will fit */ -+ -+ /* 7. modulus > base */ -+ if (mod_bits < base_bits) -+ goto too_small; -+ if (mod_bits == base_bits) { -+ u_int8_t *basep, *modp; -+ int i; -+ -+ basep = krp->krp_param[SAFE_CRK_PARAM_BASE].crp_p + -+ ((base_bits + 7) / 8) - 1; -+ modp = krp->krp_param[SAFE_CRK_PARAM_MOD].crp_p + -+ ((mod_bits + 7) / 8) - 1; -+ -+ for (i = 0; i < (mod_bits + 7) / 8; i++, basep--, modp--) { -+ if (*modp < *basep) -+ goto too_small; -+ if (*modp > *basep) -+ break; -+ } -+ } -+ -+ /* And on the 9th step, he rested. */ -+ -+ WRITE_REG(sc, SAFE_PK_A_LEN, (exp_bits + 31) / 32); -+ WRITE_REG(sc, SAFE_PK_B_LEN, (mod_bits + 31) / 32); -+ if (mod_bits > 1024) { -+ op = SAFE_PK_FUNC_EXP4; -+ a_off = 0x000; -+ b_off = 0x100; -+ c_off = 0x200; -+ d_off = 0x300; -+ } else { -+ op = SAFE_PK_FUNC_EXP16; -+ a_off = 0x000; -+ b_off = 0x080; -+ c_off = 0x100; -+ d_off = 0x180; -+ } -+ sc->sc_pk_reslen = b_off - a_off; -+ sc->sc_pk_resoff = d_off; -+ -+ /* A is exponent, B is modulus, C is base, D is result */ -+ safe_kload_reg(sc, a_off, b_off - a_off, -+ &krp->krp_param[SAFE_CRK_PARAM_EXP]); -+ WRITE_REG(sc, SAFE_PK_A_ADDR, a_off >> 2); -+ safe_kload_reg(sc, b_off, b_off - a_off, -+ &krp->krp_param[SAFE_CRK_PARAM_MOD]); -+ WRITE_REG(sc, SAFE_PK_B_ADDR, b_off >> 2); -+ safe_kload_reg(sc, c_off, b_off - a_off, -+ &krp->krp_param[SAFE_CRK_PARAM_BASE]); -+ WRITE_REG(sc, SAFE_PK_C_ADDR, c_off >> 2); -+ WRITE_REG(sc, SAFE_PK_D_ADDR, d_off >> 2); -+ -+ WRITE_REG(sc, SAFE_PK_FUNC, op | SAFE_PK_FUNC_RUN); -+ -+ return (0); -+ -+too_big: -+ krp->krp_status = E2BIG; -+ return (1); -+too_small: -+ krp->krp_status = ERANGE; -+ return (1); -+bad_domain: -+ krp->krp_status = EDOM; -+ return (1); -+} -+ -+static int -+safe_ksigbits(struct safe_softc *sc, struct crparam *cr) -+{ -+ u_int plen = (cr->crp_nbits + 7) / 8; -+ int i, sig = plen * 8; -+ u_int8_t c, *p = cr->crp_p; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ for (i = plen - 1; i >= 0; i--) { -+ c = p[i]; -+ if (c != 0) { -+ while ((c & 0x80) == 0) { -+ sig--; -+ c <<= 1; -+ } -+ break; -+ } -+ sig -= 8; -+ } -+ return (sig); -+} -+ -+static void -+safe_kfeed(struct safe_softc *sc) -+{ -+ struct safe_pkq *q, *tmp; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (list_empty(&sc->sc_pkq) && sc->sc_pkq_cur == NULL) -+ return; -+ if (sc->sc_pkq_cur != NULL) -+ return; -+ list_for_each_entry_safe(q, tmp, &sc->sc_pkq, pkq_list) { -+ sc->sc_pkq_cur = q; -+ list_del(&q->pkq_list); -+ if (safe_kstart(sc) != 0) { -+ crypto_kdone(q->pkq_krp); -+ kfree(q); -+ sc->sc_pkq_cur = NULL; -+ } else { -+ /* op started, start polling */ -+ mod_timer(&sc->sc_pkto, jiffies + 1); -+ break; -+ } -+ } -+} -+ -+static void -+safe_kpoll(unsigned long arg) -+{ -+ struct safe_softc *sc = NULL; -+ struct safe_pkq *q; -+ struct crparam *res; -+ int i; -+ u_int32_t buf[64]; -+ unsigned long flags; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (arg >= SAFE_MAX_CHIPS) -+ return; -+ sc = safe_chip_idx[arg]; -+ if (!sc) { -+ DPRINTF(("%s() - bad callback\n", __FUNCTION__)); -+ return; -+ } -+ -+ spin_lock_irqsave(&sc->sc_pkmtx, flags); -+ if (sc->sc_pkq_cur == NULL) -+ goto out; -+ if (READ_REG(sc, SAFE_PK_FUNC) & SAFE_PK_FUNC_RUN) { -+ /* still running, check back later */ -+ mod_timer(&sc->sc_pkto, jiffies + 1); -+ goto out; -+ } -+ -+ q = sc->sc_pkq_cur; -+ res = &q->pkq_krp->krp_param[q->pkq_krp->krp_iparams]; -+ bzero(buf, sizeof(buf)); -+ bzero(res->crp_p, (res->crp_nbits + 7) / 8); -+ for (i = 0; i < sc->sc_pk_reslen >> 2; i++) -+ buf[i] = le32_to_cpu(READ_REG(sc, SAFE_PK_RAM_START + -+ sc->sc_pk_resoff + (i << 2))); -+ bcopy(buf, res->crp_p, (res->crp_nbits + 7) / 8); -+ /* -+ * reduce the bits that need copying if possible -+ */ -+ res->crp_nbits = min(res->crp_nbits,sc->sc_pk_reslen * 8); -+ res->crp_nbits = safe_ksigbits(sc, res); -+ -+ for (i = SAFE_PK_RAM_START; i < SAFE_PK_RAM_END; i += 4) -+ WRITE_REG(sc, i, 0); -+ -+ crypto_kdone(q->pkq_krp); -+ kfree(q); -+ sc->sc_pkq_cur = NULL; -+ -+ safe_kfeed(sc); -+out: -+ spin_unlock_irqrestore(&sc->sc_pkmtx, flags); -+} -+ -+static void -+safe_kload_reg(struct safe_softc *sc, u_int32_t off, u_int32_t len, -+ struct crparam *n) -+{ -+ u_int32_t buf[64], i; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ bzero(buf, sizeof(buf)); -+ bcopy(n->crp_p, buf, (n->crp_nbits + 7) / 8); -+ -+ for (i = 0; i < len >> 2; i++) -+ WRITE_REG(sc, SAFE_PK_RAM_START + off + (i << 2), -+ cpu_to_le32(buf[i])); -+} -+ -+#ifdef SAFE_DEBUG -+static void -+safe_dump_dmastatus(struct safe_softc *sc, const char *tag) -+{ -+ printf("%s: ENDIAN 0x%x SRC 0x%x DST 0x%x STAT 0x%x\n" -+ , tag -+ , READ_REG(sc, SAFE_DMA_ENDIAN) -+ , READ_REG(sc, SAFE_DMA_SRCADDR) -+ , READ_REG(sc, SAFE_DMA_DSTADDR) -+ , READ_REG(sc, SAFE_DMA_STAT) -+ ); -+} -+ -+static void -+safe_dump_intrstate(struct safe_softc *sc, const char *tag) -+{ -+ printf("%s: HI_CFG 0x%x HI_MASK 0x%x HI_DESC_CNT 0x%x HU_STAT 0x%x HM_STAT 0x%x\n" -+ , tag -+ , READ_REG(sc, SAFE_HI_CFG) -+ , READ_REG(sc, SAFE_HI_MASK) -+ , READ_REG(sc, SAFE_HI_DESC_CNT) -+ , READ_REG(sc, SAFE_HU_STAT) -+ , READ_REG(sc, SAFE_HM_STAT) -+ ); -+} -+ -+static void -+safe_dump_ringstate(struct safe_softc *sc, const char *tag) -+{ -+ u_int32_t estat = READ_REG(sc, SAFE_PE_ERNGSTAT); -+ -+ /* NB: assume caller has lock on ring */ -+ printf("%s: ERNGSTAT %x (next %u) back %lu front %lu\n", -+ tag, -+ estat, (estat >> SAFE_PE_ERNGSTAT_NEXT_S), -+ (unsigned long)(sc->sc_back - sc->sc_ring), -+ (unsigned long)(sc->sc_front - sc->sc_ring)); -+} -+ -+static void -+safe_dump_request(struct safe_softc *sc, const char* tag, struct safe_ringentry *re) -+{ -+ int ix, nsegs; -+ -+ ix = re - sc->sc_ring; -+ printf("%s: %p (%u): csr %x src %x dst %x sa %x len %x\n" -+ , tag -+ , re, ix -+ , re->re_desc.d_csr -+ , re->re_desc.d_src -+ , re->re_desc.d_dst -+ , re->re_desc.d_sa -+ , re->re_desc.d_len -+ ); -+ if (re->re_src.nsegs > 1) { -+ ix = (re->re_desc.d_src - sc->sc_spalloc.dma_paddr) / -+ sizeof(struct safe_pdesc); -+ for (nsegs = re->re_src.nsegs; nsegs; nsegs--) { -+ printf(" spd[%u] %p: %p size %u flags %x" -+ , ix, &sc->sc_spring[ix] -+ , (caddr_t)(uintptr_t) sc->sc_spring[ix].pd_addr -+ , sc->sc_spring[ix].pd_size -+ , sc->sc_spring[ix].pd_flags -+ ); -+ if (sc->sc_spring[ix].pd_size == 0) -+ printf(" (zero!)"); -+ printf("\n"); -+ if (++ix == SAFE_TOTAL_SPART) -+ ix = 0; -+ } -+ } -+ if (re->re_dst.nsegs > 1) { -+ ix = (re->re_desc.d_dst - sc->sc_dpalloc.dma_paddr) / -+ sizeof(struct safe_pdesc); -+ for (nsegs = re->re_dst.nsegs; nsegs; nsegs--) { -+ printf(" dpd[%u] %p: %p flags %x\n" -+ , ix, &sc->sc_dpring[ix] -+ , (caddr_t)(uintptr_t) sc->sc_dpring[ix].pd_addr -+ , sc->sc_dpring[ix].pd_flags -+ ); -+ if (++ix == SAFE_TOTAL_DPART) -+ ix = 0; -+ } -+ } -+ printf("sa: cmd0 %08x cmd1 %08x staterec %x\n", -+ re->re_sa.sa_cmd0, re->re_sa.sa_cmd1, re->re_sa.sa_staterec); -+ printf("sa: key %x %x %x %x %x %x %x %x\n" -+ , re->re_sa.sa_key[0] -+ , re->re_sa.sa_key[1] -+ , re->re_sa.sa_key[2] -+ , re->re_sa.sa_key[3] -+ , re->re_sa.sa_key[4] -+ , re->re_sa.sa_key[5] -+ , re->re_sa.sa_key[6] -+ , re->re_sa.sa_key[7] -+ ); -+ printf("sa: indigest %x %x %x %x %x\n" -+ , re->re_sa.sa_indigest[0] -+ , re->re_sa.sa_indigest[1] -+ , re->re_sa.sa_indigest[2] -+ , re->re_sa.sa_indigest[3] -+ , re->re_sa.sa_indigest[4] -+ ); -+ printf("sa: outdigest %x %x %x %x %x\n" -+ , re->re_sa.sa_outdigest[0] -+ , re->re_sa.sa_outdigest[1] -+ , re->re_sa.sa_outdigest[2] -+ , re->re_sa.sa_outdigest[3] -+ , re->re_sa.sa_outdigest[4] -+ ); -+ printf("sr: iv %x %x %x %x\n" -+ , re->re_sastate.sa_saved_iv[0] -+ , re->re_sastate.sa_saved_iv[1] -+ , re->re_sastate.sa_saved_iv[2] -+ , re->re_sastate.sa_saved_iv[3] -+ ); -+ printf("sr: hashbc %u indigest %x %x %x %x %x\n" -+ , re->re_sastate.sa_saved_hashbc -+ , re->re_sastate.sa_saved_indigest[0] -+ , re->re_sastate.sa_saved_indigest[1] -+ , re->re_sastate.sa_saved_indigest[2] -+ , re->re_sastate.sa_saved_indigest[3] -+ , re->re_sastate.sa_saved_indigest[4] -+ ); -+} -+ -+static void -+safe_dump_ring(struct safe_softc *sc, const char *tag) -+{ -+ unsigned long flags; -+ -+ spin_lock_irqsave(&sc->sc_ringmtx, flags); -+ printf("\nSafeNet Ring State:\n"); -+ safe_dump_intrstate(sc, tag); -+ safe_dump_dmastatus(sc, tag); -+ safe_dump_ringstate(sc, tag); -+ if (sc->sc_nqchip) { -+ struct safe_ringentry *re = sc->sc_back; -+ do { -+ safe_dump_request(sc, tag, re); -+ if (++re == sc->sc_ringtop) -+ re = sc->sc_ring; -+ } while (re != sc->sc_front); -+ } -+ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); -+} -+#endif /* SAFE_DEBUG */ -+ -+ -+static int safe_probe(struct pci_dev *dev, const struct pci_device_id *ent) -+{ -+ struct safe_softc *sc = NULL; -+ u32 mem_start, mem_len, cmd; -+ int i, rc, devinfo; -+ dma_addr_t raddr; -+ static int num_chips = 0; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (pci_enable_device(dev) < 0) -+ return(-ENODEV); -+ -+ if (!dev->irq) { -+ printk("safe: found device with no IRQ assigned. check BIOS settings!"); -+ pci_disable_device(dev); -+ return(-ENODEV); -+ } -+ -+ if (pci_set_mwi(dev)) { -+ printk("safe: pci_set_mwi failed!"); -+ return(-ENODEV); -+ } -+ -+ sc = (struct safe_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); -+ if (!sc) -+ return(-ENOMEM); -+ memset(sc, 0, sizeof(*sc)); -+ -+ softc_device_init(sc, "safe", num_chips, safe_methods); -+ -+ sc->sc_irq = -1; -+ sc->sc_cid = -1; -+ sc->sc_pcidev = dev; -+ if (num_chips < SAFE_MAX_CHIPS) { -+ safe_chip_idx[device_get_unit(sc->sc_dev)] = sc; -+ num_chips++; -+ } -+ -+ INIT_LIST_HEAD(&sc->sc_pkq); -+ spin_lock_init(&sc->sc_pkmtx); -+ -+ pci_set_drvdata(sc->sc_pcidev, sc); -+ -+ /* we read its hardware registers as memory */ -+ mem_start = pci_resource_start(sc->sc_pcidev, 0); -+ mem_len = pci_resource_len(sc->sc_pcidev, 0); -+ -+ sc->sc_base_addr = (ocf_iomem_t) ioremap(mem_start, mem_len); -+ if (!sc->sc_base_addr) { -+ device_printf(sc->sc_dev, "failed to ioremap 0x%x-0x%x\n", -+ mem_start, mem_start + mem_len - 1); -+ goto out; -+ } -+ -+ /* fix up the bus size */ -+ if (pci_set_dma_mask(sc->sc_pcidev, DMA_32BIT_MASK)) { -+ device_printf(sc->sc_dev, "No usable DMA configuration, aborting.\n"); -+ goto out; -+ } -+ if (pci_set_consistent_dma_mask(sc->sc_pcidev, DMA_32BIT_MASK)) { -+ device_printf(sc->sc_dev, "No usable consistent DMA configuration, aborting.\n"); -+ goto out; -+ } -+ -+ pci_set_master(sc->sc_pcidev); -+ -+ pci_read_config_dword(sc->sc_pcidev, PCI_COMMAND, &cmd); -+ -+ if (!(cmd & PCI_COMMAND_MEMORY)) { -+ device_printf(sc->sc_dev, "failed to enable memory mapping\n"); -+ goto out; -+ } -+ -+ if (!(cmd & PCI_COMMAND_MASTER)) { -+ device_printf(sc->sc_dev, "failed to enable bus mastering\n"); -+ goto out; -+ } -+ -+ rc = request_irq(dev->irq, safe_intr, IRQF_SHARED, "safe", sc); -+ if (rc) { -+ device_printf(sc->sc_dev, "failed to hook irq %d\n", sc->sc_irq); -+ goto out; -+ } -+ sc->sc_irq = dev->irq; -+ -+ sc->sc_chiprev = READ_REG(sc, SAFE_DEVINFO) & -+ (SAFE_DEVINFO_REV_MAJ | SAFE_DEVINFO_REV_MIN); -+ -+ /* -+ * Allocate packet engine descriptors. -+ */ -+ sc->sc_ringalloc.dma_vaddr = pci_alloc_consistent(sc->sc_pcidev, -+ SAFE_MAX_NQUEUE * sizeof (struct safe_ringentry), -+ &sc->sc_ringalloc.dma_paddr); -+ if (!sc->sc_ringalloc.dma_vaddr) { -+ device_printf(sc->sc_dev, "cannot allocate PE descriptor ring\n"); -+ goto out; -+ } -+ -+ /* -+ * Hookup the static portion of all our data structures. -+ */ -+ sc->sc_ring = (struct safe_ringentry *) sc->sc_ringalloc.dma_vaddr; -+ sc->sc_ringtop = sc->sc_ring + SAFE_MAX_NQUEUE; -+ sc->sc_front = sc->sc_ring; -+ sc->sc_back = sc->sc_ring; -+ raddr = sc->sc_ringalloc.dma_paddr; -+ bzero(sc->sc_ring, SAFE_MAX_NQUEUE * sizeof(struct safe_ringentry)); -+ for (i = 0; i < SAFE_MAX_NQUEUE; i++) { -+ struct safe_ringentry *re = &sc->sc_ring[i]; -+ -+ re->re_desc.d_sa = raddr + -+ offsetof(struct safe_ringentry, re_sa); -+ re->re_sa.sa_staterec = raddr + -+ offsetof(struct safe_ringentry, re_sastate); -+ -+ raddr += sizeof (struct safe_ringentry); -+ } -+ spin_lock_init(&sc->sc_ringmtx); -+ -+ /* -+ * Allocate scatter and gather particle descriptors. -+ */ -+ sc->sc_spalloc.dma_vaddr = pci_alloc_consistent(sc->sc_pcidev, -+ SAFE_TOTAL_SPART * sizeof (struct safe_pdesc), -+ &sc->sc_spalloc.dma_paddr); -+ if (!sc->sc_spalloc.dma_vaddr) { -+ device_printf(sc->sc_dev, "cannot allocate source particle descriptor ring\n"); -+ goto out; -+ } -+ sc->sc_spring = (struct safe_pdesc *) sc->sc_spalloc.dma_vaddr; -+ sc->sc_springtop = sc->sc_spring + SAFE_TOTAL_SPART; -+ sc->sc_spfree = sc->sc_spring; -+ bzero(sc->sc_spring, SAFE_TOTAL_SPART * sizeof(struct safe_pdesc)); -+ -+ sc->sc_dpalloc.dma_vaddr = pci_alloc_consistent(sc->sc_pcidev, -+ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), -+ &sc->sc_dpalloc.dma_paddr); -+ if (!sc->sc_dpalloc.dma_vaddr) { -+ device_printf(sc->sc_dev, "cannot allocate destination particle descriptor ring\n"); -+ goto out; -+ } -+ sc->sc_dpring = (struct safe_pdesc *) sc->sc_dpalloc.dma_vaddr; -+ sc->sc_dpringtop = sc->sc_dpring + SAFE_TOTAL_DPART; -+ sc->sc_dpfree = sc->sc_dpring; -+ bzero(sc->sc_dpring, SAFE_TOTAL_DPART * sizeof(struct safe_pdesc)); -+ -+ sc->sc_cid = crypto_get_driverid(softc_get_device(sc), CRYPTOCAP_F_HARDWARE); -+ if (sc->sc_cid < 0) { -+ device_printf(sc->sc_dev, "could not get crypto driver id\n"); -+ goto out; -+ } -+ -+ printf("%s:", device_get_nameunit(sc->sc_dev)); -+ -+ devinfo = READ_REG(sc, SAFE_DEVINFO); -+ if (devinfo & SAFE_DEVINFO_RNG) { -+ sc->sc_flags |= SAFE_FLAGS_RNG; -+ printf(" rng"); -+ } -+ if (devinfo & SAFE_DEVINFO_PKEY) { -+ printf(" key"); -+ sc->sc_flags |= SAFE_FLAGS_KEY; -+ crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0); -+#if 0 -+ crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0); -+#endif -+ init_timer(&sc->sc_pkto); -+ sc->sc_pkto.function = safe_kpoll; -+ sc->sc_pkto.data = (unsigned long) device_get_unit(sc->sc_dev); -+ } -+ if (devinfo & SAFE_DEVINFO_DES) { -+ printf(" des/3des"); -+ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); -+ } -+ if (devinfo & SAFE_DEVINFO_AES) { -+ printf(" aes"); -+ crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); -+ } -+ if (devinfo & SAFE_DEVINFO_MD5) { -+ printf(" md5"); -+ crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); -+ } -+ if (devinfo & SAFE_DEVINFO_SHA1) { -+ printf(" sha1"); -+ crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); -+ } -+ printf(" null"); -+ crypto_register(sc->sc_cid, CRYPTO_NULL_CBC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_NULL_HMAC, 0, 0); -+ /* XXX other supported algorithms */ -+ printf("\n"); -+ -+ safe_reset_board(sc); /* reset h/w */ -+ safe_init_board(sc); /* init h/w */ -+ -+#if defined(CONFIG_OCF_RANDOMHARVEST) && !defined(SAFE_NO_RNG) -+ if (sc->sc_flags & SAFE_FLAGS_RNG) { -+ safe_rng_init(sc); -+ crypto_rregister(sc->sc_cid, safe_read_random, sc); -+ } -+#endif /* SAFE_NO_RNG */ -+ -+ return (0); -+ -+out: -+ if (sc->sc_cid >= 0) -+ crypto_unregister_all(sc->sc_cid); -+ if (sc->sc_irq != -1) -+ free_irq(sc->sc_irq, sc); -+ if (sc->sc_ringalloc.dma_vaddr) -+ pci_free_consistent(sc->sc_pcidev, -+ SAFE_MAX_NQUEUE * sizeof (struct safe_ringentry), -+ sc->sc_ringalloc.dma_vaddr, sc->sc_ringalloc.dma_paddr); -+ if (sc->sc_spalloc.dma_vaddr) -+ pci_free_consistent(sc->sc_pcidev, -+ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), -+ sc->sc_spalloc.dma_vaddr, sc->sc_spalloc.dma_paddr); -+ if (sc->sc_dpalloc.dma_vaddr) -+ pci_free_consistent(sc->sc_pcidev, -+ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), -+ sc->sc_dpalloc.dma_vaddr, sc->sc_dpalloc.dma_paddr); -+ kfree(sc); -+ return(-ENODEV); -+} -+ -+static void safe_remove(struct pci_dev *dev) -+{ -+ struct safe_softc *sc = pci_get_drvdata(dev); -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ /* XXX wait/abort active ops */ -+ -+ WRITE_REG(sc, SAFE_HI_MASK, 0); /* disable interrupts */ -+ -+ del_timer_sync(&sc->sc_pkto); -+ -+ crypto_unregister_all(sc->sc_cid); -+ -+ safe_cleanchip(sc); -+ -+ if (sc->sc_irq != -1) -+ free_irq(sc->sc_irq, sc); -+ if (sc->sc_ringalloc.dma_vaddr) -+ pci_free_consistent(sc->sc_pcidev, -+ SAFE_MAX_NQUEUE * sizeof (struct safe_ringentry), -+ sc->sc_ringalloc.dma_vaddr, sc->sc_ringalloc.dma_paddr); -+ if (sc->sc_spalloc.dma_vaddr) -+ pci_free_consistent(sc->sc_pcidev, -+ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), -+ sc->sc_spalloc.dma_vaddr, sc->sc_spalloc.dma_paddr); -+ if (sc->sc_dpalloc.dma_vaddr) -+ pci_free_consistent(sc->sc_pcidev, -+ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), -+ sc->sc_dpalloc.dma_vaddr, sc->sc_dpalloc.dma_paddr); -+ sc->sc_irq = -1; -+ sc->sc_ringalloc.dma_vaddr = NULL; -+ sc->sc_spalloc.dma_vaddr = NULL; -+ sc->sc_dpalloc.dma_vaddr = NULL; -+} -+ -+static struct pci_device_id safe_pci_tbl[] = { -+ { PCI_VENDOR_SAFENET, PCI_PRODUCT_SAFEXCEL, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ { }, -+}; -+MODULE_DEVICE_TABLE(pci, safe_pci_tbl); -+ -+static struct pci_driver safe_driver = { -+ .name = "safe", -+ .id_table = safe_pci_tbl, -+ .probe = safe_probe, -+ .remove = safe_remove, -+ /* add PM stuff here one day */ -+}; -+ -+static int __init safe_init (void) -+{ -+ struct safe_softc *sc = NULL; -+ int rc; -+ -+ DPRINTF(("%s(%p)\n", __FUNCTION__, safe_init)); -+ -+ rc = pci_register_driver(&safe_driver); -+ pci_register_driver_compat(&safe_driver, rc); -+ -+ return rc; -+} -+ -+static void __exit safe_exit (void) -+{ -+ pci_unregister_driver(&safe_driver); -+} -+ -+module_init(safe_init); -+module_exit(safe_exit); -+ -+MODULE_LICENSE("BSD"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("OCF driver for safenet PCI crypto devices"); -diff -Nur linux-2.6.36.orig/crypto/ocf/safe/safereg.h linux-2.6.36/crypto/ocf/safe/safereg.h ---- linux-2.6.36.orig/crypto/ocf/safe/safereg.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/safe/safereg.h 2010-11-09 20:28:12.962495464 +0100 -@@ -0,0 +1,421 @@ -+/*- -+ * Copyright (c) 2003 Sam Leffler, Errno Consulting -+ * Copyright (c) 2003 Global Technology Associates, Inc. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ * -+ * $FreeBSD: src/sys/dev/safe/safereg.h,v 1.1 2003/07/21 21:46:07 sam Exp $ -+ */ -+#ifndef _SAFE_SAFEREG_H_ -+#define _SAFE_SAFEREG_H_ -+ -+/* -+ * Register definitions for SafeNet SafeXcel-1141 crypto device. -+ * Definitions from revision 1.3 (Nov 6 2002) of the User's Manual. -+ */ -+ -+#define BS_BAR 0x10 /* DMA base address register */ -+#define BS_TRDY_TIMEOUT 0x40 /* TRDY timeout */ -+#define BS_RETRY_TIMEOUT 0x41 /* DMA retry timeout */ -+ -+#define PCI_VENDOR_SAFENET 0x16ae /* SafeNet, Inc. */ -+ -+/* SafeNet */ -+#define PCI_PRODUCT_SAFEXCEL 0x1141 /* 1141 */ -+ -+#define SAFE_PE_CSR 0x0000 /* Packet Enginge Ctrl/Status */ -+#define SAFE_PE_SRC 0x0004 /* Packet Engine Source */ -+#define SAFE_PE_DST 0x0008 /* Packet Engine Destination */ -+#define SAFE_PE_SA 0x000c /* Packet Engine SA */ -+#define SAFE_PE_LEN 0x0010 /* Packet Engine Length */ -+#define SAFE_PE_DMACFG 0x0040 /* Packet Engine DMA Configuration */ -+#define SAFE_PE_DMASTAT 0x0044 /* Packet Engine DMA Status */ -+#define SAFE_PE_PDRBASE 0x0048 /* Packet Engine Descriptor Ring Base */ -+#define SAFE_PE_RDRBASE 0x004c /* Packet Engine Result Ring Base */ -+#define SAFE_PE_RINGCFG 0x0050 /* Packet Engine Ring Configuration */ -+#define SAFE_PE_RINGPOLL 0x0054 /* Packet Engine Ring Poll */ -+#define SAFE_PE_IRNGSTAT 0x0058 /* Packet Engine Internal Ring Status */ -+#define SAFE_PE_ERNGSTAT 0x005c /* Packet Engine External Ring Status */ -+#define SAFE_PE_IOTHRESH 0x0060 /* Packet Engine I/O Threshold */ -+#define SAFE_PE_GRNGBASE 0x0064 /* Packet Engine Gather Ring Base */ -+#define SAFE_PE_SRNGBASE 0x0068 /* Packet Engine Scatter Ring Base */ -+#define SAFE_PE_PARTSIZE 0x006c /* Packet Engine Particlar Ring Size */ -+#define SAFE_PE_PARTCFG 0x0070 /* Packet Engine Particle Ring Config */ -+#define SAFE_CRYPTO_CTRL 0x0080 /* Crypto Control */ -+#define SAFE_DEVID 0x0084 /* Device ID */ -+#define SAFE_DEVINFO 0x0088 /* Device Info */ -+#define SAFE_HU_STAT 0x00a0 /* Host Unmasked Status */ -+#define SAFE_HM_STAT 0x00a4 /* Host Masked Status (read-only) */ -+#define SAFE_HI_CLR 0x00a4 /* Host Clear Interrupt (write-only) */ -+#define SAFE_HI_MASK 0x00a8 /* Host Mask Control */ -+#define SAFE_HI_CFG 0x00ac /* Interrupt Configuration */ -+#define SAFE_HI_RD_DESCR 0x00b4 /* Force Descriptor Read */ -+#define SAFE_HI_DESC_CNT 0x00b8 /* Host Descriptor Done Count */ -+#define SAFE_DMA_ENDIAN 0x00c0 /* Master Endian Status */ -+#define SAFE_DMA_SRCADDR 0x00c4 /* DMA Source Address Status */ -+#define SAFE_DMA_DSTADDR 0x00c8 /* DMA Destination Address Status */ -+#define SAFE_DMA_STAT 0x00cc /* DMA Current Status */ -+#define SAFE_DMA_CFG 0x00d4 /* DMA Configuration/Status */ -+#define SAFE_ENDIAN 0x00e0 /* Endian Configuration */ -+#define SAFE_PK_A_ADDR 0x0800 /* Public Key A Address */ -+#define SAFE_PK_B_ADDR 0x0804 /* Public Key B Address */ -+#define SAFE_PK_C_ADDR 0x0808 /* Public Key C Address */ -+#define SAFE_PK_D_ADDR 0x080c /* Public Key D Address */ -+#define SAFE_PK_A_LEN 0x0810 /* Public Key A Length */ -+#define SAFE_PK_B_LEN 0x0814 /* Public Key B Length */ -+#define SAFE_PK_SHIFT 0x0818 /* Public Key Shift */ -+#define SAFE_PK_FUNC 0x081c /* Public Key Function */ -+#define SAFE_PK_RAM_START 0x1000 /* Public Key RAM start address */ -+#define SAFE_PK_RAM_END 0x1fff /* Public Key RAM end address */ -+ -+#define SAFE_RNG_OUT 0x0100 /* RNG Output */ -+#define SAFE_RNG_STAT 0x0104 /* RNG Status */ -+#define SAFE_RNG_CTRL 0x0108 /* RNG Control */ -+#define SAFE_RNG_A 0x010c /* RNG A */ -+#define SAFE_RNG_B 0x0110 /* RNG B */ -+#define SAFE_RNG_X_LO 0x0114 /* RNG X [31:0] */ -+#define SAFE_RNG_X_MID 0x0118 /* RNG X [63:32] */ -+#define SAFE_RNG_X_HI 0x011c /* RNG X [80:64] */ -+#define SAFE_RNG_X_CNTR 0x0120 /* RNG Counter */ -+#define SAFE_RNG_ALM_CNT 0x0124 /* RNG Alarm Count */ -+#define SAFE_RNG_CNFG 0x0128 /* RNG Configuration */ -+#define SAFE_RNG_LFSR1_LO 0x012c /* RNG LFSR1 [31:0] */ -+#define SAFE_RNG_LFSR1_HI 0x0130 /* RNG LFSR1 [47:32] */ -+#define SAFE_RNG_LFSR2_LO 0x0134 /* RNG LFSR1 [31:0] */ -+#define SAFE_RNG_LFSR2_HI 0x0138 /* RNG LFSR1 [47:32] */ -+ -+#define SAFE_PE_CSR_READY 0x00000001 /* ready for processing */ -+#define SAFE_PE_CSR_DONE 0x00000002 /* h/w completed processing */ -+#define SAFE_PE_CSR_LOADSA 0x00000004 /* load SA digests */ -+#define SAFE_PE_CSR_HASHFINAL 0x00000010 /* do hash pad & write result */ -+#define SAFE_PE_CSR_SABUSID 0x000000c0 /* bus id for SA */ -+#define SAFE_PE_CSR_SAPCI 0x00000040 /* PCI bus id for SA */ -+#define SAFE_PE_CSR_NXTHDR 0x0000ff00 /* next hdr value for IPsec */ -+#define SAFE_PE_CSR_FPAD 0x0000ff00 /* fixed pad for basic ops */ -+#define SAFE_PE_CSR_STATUS 0x00ff0000 /* operation result status */ -+#define SAFE_PE_CSR_AUTH_FAIL 0x00010000 /* ICV mismatch (inbound) */ -+#define SAFE_PE_CSR_PAD_FAIL 0x00020000 /* pad verify fail (inbound) */ -+#define SAFE_PE_CSR_SEQ_FAIL 0x00040000 /* sequence number (inbound) */ -+#define SAFE_PE_CSR_XERROR 0x00080000 /* extended error follows */ -+#define SAFE_PE_CSR_XECODE 0x00f00000 /* extended error code */ -+#define SAFE_PE_CSR_XECODE_S 20 -+#define SAFE_PE_CSR_XECODE_BADCMD 0 /* invalid command */ -+#define SAFE_PE_CSR_XECODE_BADALG 1 /* invalid algorithm */ -+#define SAFE_PE_CSR_XECODE_ALGDIS 2 /* algorithm disabled */ -+#define SAFE_PE_CSR_XECODE_ZEROLEN 3 /* zero packet length */ -+#define SAFE_PE_CSR_XECODE_DMAERR 4 /* bus DMA error */ -+#define SAFE_PE_CSR_XECODE_PIPEABORT 5 /* secondary bus DMA error */ -+#define SAFE_PE_CSR_XECODE_BADSPI 6 /* IPsec SPI mismatch */ -+#define SAFE_PE_CSR_XECODE_TIMEOUT 10 /* failsafe timeout */ -+#define SAFE_PE_CSR_PAD 0xff000000 /* ESP padding control/status */ -+#define SAFE_PE_CSR_PAD_MIN 0x00000000 /* minimum IPsec padding */ -+#define SAFE_PE_CSR_PAD_16 0x08000000 /* pad to 16-byte boundary */ -+#define SAFE_PE_CSR_PAD_32 0x10000000 /* pad to 32-byte boundary */ -+#define SAFE_PE_CSR_PAD_64 0x20000000 /* pad to 64-byte boundary */ -+#define SAFE_PE_CSR_PAD_128 0x40000000 /* pad to 128-byte boundary */ -+#define SAFE_PE_CSR_PAD_256 0x80000000 /* pad to 256-byte boundary */ -+ -+/* -+ * Check the CSR to see if the PE has returned ownership to -+ * the host. Note that before processing a descriptor this -+ * must be done followed by a check of the SAFE_PE_LEN register -+ * status bits to avoid premature processing of a descriptor -+ * on its way back to the host. -+ */ -+#define SAFE_PE_CSR_IS_DONE(_csr) \ -+ (((_csr) & (SAFE_PE_CSR_READY | SAFE_PE_CSR_DONE)) == SAFE_PE_CSR_DONE) -+ -+#define SAFE_PE_LEN_LENGTH 0x000fffff /* total length (bytes) */ -+#define SAFE_PE_LEN_READY 0x00400000 /* ready for processing */ -+#define SAFE_PE_LEN_DONE 0x00800000 /* h/w completed processing */ -+#define SAFE_PE_LEN_BYPASS 0xff000000 /* bypass offset (bytes) */ -+#define SAFE_PE_LEN_BYPASS_S 24 -+ -+#define SAFE_PE_LEN_IS_DONE(_len) \ -+ (((_len) & (SAFE_PE_LEN_READY | SAFE_PE_LEN_DONE)) == SAFE_PE_LEN_DONE) -+ -+/* NB: these apply to HU_STAT, HM_STAT, HI_CLR, and HI_MASK */ -+#define SAFE_INT_PE_CDONE 0x00000002 /* PE context done */ -+#define SAFE_INT_PE_DDONE 0x00000008 /* PE descriptor done */ -+#define SAFE_INT_PE_ERROR 0x00000010 /* PE error */ -+#define SAFE_INT_PE_ODONE 0x00000020 /* PE operation done */ -+ -+#define SAFE_HI_CFG_PULSE 0x00000001 /* use pulse interrupt */ -+#define SAFE_HI_CFG_LEVEL 0x00000000 /* use level interrupt */ -+#define SAFE_HI_CFG_AUTOCLR 0x00000002 /* auto-clear pulse interrupt */ -+ -+#define SAFE_ENDIAN_PASS 0x000000e4 /* straight pass-thru */ -+#define SAFE_ENDIAN_SWAB 0x0000001b /* swap bytes in 32-bit word */ -+ -+#define SAFE_PE_DMACFG_PERESET 0x00000001 /* reset packet engine */ -+#define SAFE_PE_DMACFG_PDRRESET 0x00000002 /* reset PDR counters/ptrs */ -+#define SAFE_PE_DMACFG_SGRESET 0x00000004 /* reset scatter/gather cache */ -+#define SAFE_PE_DMACFG_FSENA 0x00000008 /* enable failsafe reset */ -+#define SAFE_PE_DMACFG_PEMODE 0x00000100 /* packet engine mode */ -+#define SAFE_PE_DMACFG_SAPREC 0x00000200 /* SA precedes packet */ -+#define SAFE_PE_DMACFG_PKFOLL 0x00000400 /* packet follows descriptor */ -+#define SAFE_PE_DMACFG_GPRBID 0x00003000 /* gather particle ring busid */ -+#define SAFE_PE_DMACFG_GPRPCI 0x00001000 /* PCI gather particle ring */ -+#define SAFE_PE_DMACFG_SPRBID 0x0000c000 /* scatter part. ring busid */ -+#define SAFE_PE_DMACFG_SPRPCI 0x00004000 /* PCI scatter part. ring */ -+#define SAFE_PE_DMACFG_ESDESC 0x00010000 /* endian swap descriptors */ -+#define SAFE_PE_DMACFG_ESSA 0x00020000 /* endian swap SA data */ -+#define SAFE_PE_DMACFG_ESPACKET 0x00040000 /* endian swap packet data */ -+#define SAFE_PE_DMACFG_ESPDESC 0x00080000 /* endian swap particle desc. */ -+#define SAFE_PE_DMACFG_NOPDRUP 0x00100000 /* supp. PDR ownership update */ -+#define SAFE_PD_EDMACFG_PCIMODE 0x01000000 /* PCI target mode */ -+ -+#define SAFE_PE_DMASTAT_PEIDONE 0x00000001 /* PE core input done */ -+#define SAFE_PE_DMASTAT_PEODONE 0x00000002 /* PE core output done */ -+#define SAFE_PE_DMASTAT_ENCDONE 0x00000004 /* encryption done */ -+#define SAFE_PE_DMASTAT_IHDONE 0x00000008 /* inner hash done */ -+#define SAFE_PE_DMASTAT_OHDONE 0x00000010 /* outer hash (HMAC) done */ -+#define SAFE_PE_DMASTAT_PADFLT 0x00000020 /* crypto pad fault */ -+#define SAFE_PE_DMASTAT_ICVFLT 0x00000040 /* ICV fault */ -+#define SAFE_PE_DMASTAT_SPIMIS 0x00000080 /* SPI mismatch */ -+#define SAFE_PE_DMASTAT_CRYPTO 0x00000100 /* crypto engine timeout */ -+#define SAFE_PE_DMASTAT_CQACT 0x00000200 /* command queue active */ -+#define SAFE_PE_DMASTAT_IRACT 0x00000400 /* input request active */ -+#define SAFE_PE_DMASTAT_ORACT 0x00000800 /* output request active */ -+#define SAFE_PE_DMASTAT_PEISIZE 0x003ff000 /* PE input size:32-bit words */ -+#define SAFE_PE_DMASTAT_PEOSIZE 0xffc00000 /* PE out. size:32-bit words */ -+ -+#define SAFE_PE_RINGCFG_SIZE 0x000003ff /* ring size (descriptors) */ -+#define SAFE_PE_RINGCFG_OFFSET 0xffff0000 /* offset btw desc's (dwords) */ -+#define SAFE_PE_RINGCFG_OFFSET_S 16 -+ -+#define SAFE_PE_RINGPOLL_POLL 0x00000fff /* polling frequency/divisor */ -+#define SAFE_PE_RINGPOLL_RETRY 0x03ff0000 /* polling frequency/divisor */ -+#define SAFE_PE_RINGPOLL_CONT 0x80000000 /* continuously poll */ -+ -+#define SAFE_PE_IRNGSTAT_CQAVAIL 0x00000001 /* command queue available */ -+ -+#define SAFE_PE_ERNGSTAT_NEXT 0x03ff0000 /* index of next packet desc. */ -+#define SAFE_PE_ERNGSTAT_NEXT_S 16 -+ -+#define SAFE_PE_IOTHRESH_INPUT 0x000003ff /* input threshold (dwords) */ -+#define SAFE_PE_IOTHRESH_OUTPUT 0x03ff0000 /* output threshold (dwords) */ -+ -+#define SAFE_PE_PARTCFG_SIZE 0x0000ffff /* scatter particle size */ -+#define SAFE_PE_PARTCFG_GBURST 0x00030000 /* gather particle burst */ -+#define SAFE_PE_PARTCFG_GBURST_2 0x00000000 -+#define SAFE_PE_PARTCFG_GBURST_4 0x00010000 -+#define SAFE_PE_PARTCFG_GBURST_8 0x00020000 -+#define SAFE_PE_PARTCFG_GBURST_16 0x00030000 -+#define SAFE_PE_PARTCFG_SBURST 0x000c0000 /* scatter particle burst */ -+#define SAFE_PE_PARTCFG_SBURST_2 0x00000000 -+#define SAFE_PE_PARTCFG_SBURST_4 0x00040000 -+#define SAFE_PE_PARTCFG_SBURST_8 0x00080000 -+#define SAFE_PE_PARTCFG_SBURST_16 0x000c0000 -+ -+#define SAFE_PE_PARTSIZE_SCAT 0xffff0000 /* scatter particle ring size */ -+#define SAFE_PE_PARTSIZE_GATH 0x0000ffff /* gather particle ring size */ -+ -+#define SAFE_CRYPTO_CTRL_3DES 0x00000001 /* enable 3DES support */ -+#define SAFE_CRYPTO_CTRL_PKEY 0x00010000 /* enable public key support */ -+#define SAFE_CRYPTO_CTRL_RNG 0x00020000 /* enable RNG support */ -+ -+#define SAFE_DEVINFO_REV_MIN 0x0000000f /* minor rev for chip */ -+#define SAFE_DEVINFO_REV_MAJ 0x000000f0 /* major rev for chip */ -+#define SAFE_DEVINFO_REV_MAJ_S 4 -+#define SAFE_DEVINFO_DES 0x00000100 /* DES/3DES support present */ -+#define SAFE_DEVINFO_ARC4 0x00000200 /* ARC4 support present */ -+#define SAFE_DEVINFO_AES 0x00000400 /* AES support present */ -+#define SAFE_DEVINFO_MD5 0x00001000 /* MD5 support present */ -+#define SAFE_DEVINFO_SHA1 0x00002000 /* SHA-1 support present */ -+#define SAFE_DEVINFO_RIPEMD 0x00004000 /* RIPEMD support present */ -+#define SAFE_DEVINFO_DEFLATE 0x00010000 /* Deflate support present */ -+#define SAFE_DEVINFO_SARAM 0x00100000 /* on-chip SA RAM present */ -+#define SAFE_DEVINFO_EMIBUS 0x00200000 /* EMI bus present */ -+#define SAFE_DEVINFO_PKEY 0x00400000 /* public key support present */ -+#define SAFE_DEVINFO_RNG 0x00800000 /* RNG present */ -+ -+#define SAFE_REV(_maj, _min) (((_maj) << SAFE_DEVINFO_REV_MAJ_S) | (_min)) -+#define SAFE_REV_MAJ(_chiprev) \ -+ (((_chiprev) & SAFE_DEVINFO_REV_MAJ) >> SAFE_DEVINFO_REV_MAJ_S) -+#define SAFE_REV_MIN(_chiprev) ((_chiprev) & SAFE_DEVINFO_REV_MIN) -+ -+#define SAFE_PK_FUNC_MULT 0x00000001 /* Multiply function */ -+#define SAFE_PK_FUNC_SQUARE 0x00000004 /* Square function */ -+#define SAFE_PK_FUNC_ADD 0x00000010 /* Add function */ -+#define SAFE_PK_FUNC_SUB 0x00000020 /* Subtract function */ -+#define SAFE_PK_FUNC_LSHIFT 0x00000040 /* Left-shift function */ -+#define SAFE_PK_FUNC_RSHIFT 0x00000080 /* Right-shift function */ -+#define SAFE_PK_FUNC_DIV 0x00000100 /* Divide function */ -+#define SAFE_PK_FUNC_CMP 0x00000400 /* Compare function */ -+#define SAFE_PK_FUNC_COPY 0x00000800 /* Copy function */ -+#define SAFE_PK_FUNC_EXP16 0x00002000 /* Exponentiate (4-bit ACT) */ -+#define SAFE_PK_FUNC_EXP4 0x00004000 /* Exponentiate (2-bit ACT) */ -+#define SAFE_PK_FUNC_RUN 0x00008000 /* start/status */ -+ -+#define SAFE_RNG_STAT_BUSY 0x00000001 /* busy, data not valid */ -+ -+#define SAFE_RNG_CTRL_PRE_LFSR 0x00000001 /* enable output pre-LFSR */ -+#define SAFE_RNG_CTRL_TST_MODE 0x00000002 /* enable test mode */ -+#define SAFE_RNG_CTRL_TST_RUN 0x00000004 /* start test state machine */ -+#define SAFE_RNG_CTRL_ENA_RING1 0x00000008 /* test entropy oscillator #1 */ -+#define SAFE_RNG_CTRL_ENA_RING2 0x00000010 /* test entropy oscillator #2 */ -+#define SAFE_RNG_CTRL_DIS_ALARM 0x00000020 /* disable RNG alarm reports */ -+#define SAFE_RNG_CTRL_TST_CLOCK 0x00000040 /* enable test clock */ -+#define SAFE_RNG_CTRL_SHORTEN 0x00000080 /* shorten state timers */ -+#define SAFE_RNG_CTRL_TST_ALARM 0x00000100 /* simulate alarm state */ -+#define SAFE_RNG_CTRL_RST_LFSR 0x00000200 /* reset LFSR */ -+ -+/* -+ * Packet engine descriptor. Note that d_csr is a copy of the -+ * SAFE_PE_CSR register and all definitions apply, and d_len -+ * is a copy of the SAFE_PE_LEN register and all definitions apply. -+ * d_src and d_len may point directly to contiguous data or to a -+ * list of ``particle descriptors'' when using scatter/gather i/o. -+ */ -+struct safe_desc { -+ u_int32_t d_csr; /* per-packet control/status */ -+ u_int32_t d_src; /* source address */ -+ u_int32_t d_dst; /* destination address */ -+ u_int32_t d_sa; /* SA address */ -+ u_int32_t d_len; /* length, bypass, status */ -+}; -+ -+/* -+ * Scatter/Gather particle descriptor. -+ * -+ * NB: scatter descriptors do not specify a size; this is fixed -+ * by the setting of the SAFE_PE_PARTCFG register. -+ */ -+struct safe_pdesc { -+ u_int32_t pd_addr; /* particle address */ -+#ifdef __BIG_ENDIAN -+ u_int16_t pd_flags; /* control word */ -+ u_int16_t pd_size; /* particle size (bytes) */ -+#else -+ u_int16_t pd_flags; /* control word */ -+ u_int16_t pd_size; /* particle size (bytes) */ -+#endif -+}; -+ -+#define SAFE_PD_READY 0x0001 /* ready for processing */ -+#define SAFE_PD_DONE 0x0002 /* h/w completed processing */ -+ -+/* -+ * Security Association (SA) Record (Rev 1). One of these is -+ * required for each operation processed by the packet engine. -+ */ -+struct safe_sarec { -+ u_int32_t sa_cmd0; -+ u_int32_t sa_cmd1; -+ u_int32_t sa_resv0; -+ u_int32_t sa_resv1; -+ u_int32_t sa_key[8]; /* DES/3DES/AES key */ -+ u_int32_t sa_indigest[5]; /* inner digest */ -+ u_int32_t sa_outdigest[5]; /* outer digest */ -+ u_int32_t sa_spi; /* SPI */ -+ u_int32_t sa_seqnum; /* sequence number */ -+ u_int32_t sa_seqmask[2]; /* sequence number mask */ -+ u_int32_t sa_resv2; -+ u_int32_t sa_staterec; /* address of state record */ -+ u_int32_t sa_resv3[2]; -+ u_int32_t sa_samgmt0; /* SA management field 0 */ -+ u_int32_t sa_samgmt1; /* SA management field 0 */ -+}; -+ -+#define SAFE_SA_CMD0_OP 0x00000007 /* operation code */ -+#define SAFE_SA_CMD0_OP_CRYPT 0x00000000 /* encrypt/decrypt (basic) */ -+#define SAFE_SA_CMD0_OP_BOTH 0x00000001 /* encrypt-hash/hash-decrypto */ -+#define SAFE_SA_CMD0_OP_HASH 0x00000003 /* hash (outbound-only) */ -+#define SAFE_SA_CMD0_OP_ESP 0x00000000 /* ESP in/out (proto) */ -+#define SAFE_SA_CMD0_OP_AH 0x00000001 /* AH in/out (proto) */ -+#define SAFE_SA_CMD0_INBOUND 0x00000008 /* inbound operation */ -+#define SAFE_SA_CMD0_OUTBOUND 0x00000000 /* outbound operation */ -+#define SAFE_SA_CMD0_GROUP 0x00000030 /* operation group */ -+#define SAFE_SA_CMD0_BASIC 0x00000000 /* basic operation */ -+#define SAFE_SA_CMD0_PROTO 0x00000010 /* protocol/packet operation */ -+#define SAFE_SA_CMD0_BUNDLE 0x00000020 /* bundled operation (resvd) */ -+#define SAFE_SA_CMD0_PAD 0x000000c0 /* crypto pad method */ -+#define SAFE_SA_CMD0_PAD_IPSEC 0x00000000 /* IPsec padding */ -+#define SAFE_SA_CMD0_PAD_PKCS7 0x00000040 /* PKCS#7 padding */ -+#define SAFE_SA_CMD0_PAD_CONS 0x00000080 /* constant padding */ -+#define SAFE_SA_CMD0_PAD_ZERO 0x000000c0 /* zero padding */ -+#define SAFE_SA_CMD0_CRYPT_ALG 0x00000f00 /* symmetric crypto algorithm */ -+#define SAFE_SA_CMD0_DES 0x00000000 /* DES crypto algorithm */ -+#define SAFE_SA_CMD0_3DES 0x00000100 /* 3DES crypto algorithm */ -+#define SAFE_SA_CMD0_AES 0x00000300 /* AES crypto algorithm */ -+#define SAFE_SA_CMD0_CRYPT_NULL 0x00000f00 /* null crypto algorithm */ -+#define SAFE_SA_CMD0_HASH_ALG 0x0000f000 /* hash algorithm */ -+#define SAFE_SA_CMD0_MD5 0x00000000 /* MD5 hash algorithm */ -+#define SAFE_SA_CMD0_SHA1 0x00001000 /* SHA-1 hash algorithm */ -+#define SAFE_SA_CMD0_HASH_NULL 0x0000f000 /* null hash algorithm */ -+#define SAFE_SA_CMD0_HDR_PROC 0x00080000 /* header processing */ -+#define SAFE_SA_CMD0_IBUSID 0x00300000 /* input bus id */ -+#define SAFE_SA_CMD0_IPCI 0x00100000 /* PCI input bus id */ -+#define SAFE_SA_CMD0_OBUSID 0x00c00000 /* output bus id */ -+#define SAFE_SA_CMD0_OPCI 0x00400000 /* PCI output bus id */ -+#define SAFE_SA_CMD0_IVLD 0x03000000 /* IV loading */ -+#define SAFE_SA_CMD0_IVLD_NONE 0x00000000 /* IV no load (reuse) */ -+#define SAFE_SA_CMD0_IVLD_IBUF 0x01000000 /* IV load from input buffer */ -+#define SAFE_SA_CMD0_IVLD_STATE 0x02000000 /* IV load from state */ -+#define SAFE_SA_CMD0_HSLD 0x0c000000 /* hash state loading */ -+#define SAFE_SA_CMD0_HSLD_SA 0x00000000 /* hash state load from SA */ -+#define SAFE_SA_CMD0_HSLD_STATE 0x08000000 /* hash state load from state */ -+#define SAFE_SA_CMD0_HSLD_NONE 0x0c000000 /* hash state no load */ -+#define SAFE_SA_CMD0_SAVEIV 0x10000000 /* save IV */ -+#define SAFE_SA_CMD0_SAVEHASH 0x20000000 /* save hash state */ -+#define SAFE_SA_CMD0_IGATHER 0x40000000 /* input gather */ -+#define SAFE_SA_CMD0_OSCATTER 0x80000000 /* output scatter */ -+ -+#define SAFE_SA_CMD1_HDRCOPY 0x00000002 /* copy header to output */ -+#define SAFE_SA_CMD1_PAYCOPY 0x00000004 /* copy payload to output */ -+#define SAFE_SA_CMD1_PADCOPY 0x00000008 /* copy pad to output */ -+#define SAFE_SA_CMD1_IPV4 0x00000000 /* IPv4 protocol */ -+#define SAFE_SA_CMD1_IPV6 0x00000010 /* IPv6 protocol */ -+#define SAFE_SA_CMD1_MUTABLE 0x00000020 /* mutable bit processing */ -+#define SAFE_SA_CMD1_SRBUSID 0x000000c0 /* state record bus id */ -+#define SAFE_SA_CMD1_SRPCI 0x00000040 /* state record from PCI */ -+#define SAFE_SA_CMD1_CRMODE 0x00000300 /* crypto mode */ -+#define SAFE_SA_CMD1_ECB 0x00000000 /* ECB crypto mode */ -+#define SAFE_SA_CMD1_CBC 0x00000100 /* CBC crypto mode */ -+#define SAFE_SA_CMD1_OFB 0x00000200 /* OFB crypto mode */ -+#define SAFE_SA_CMD1_CFB 0x00000300 /* CFB crypto mode */ -+#define SAFE_SA_CMD1_CRFEEDBACK 0x00000c00 /* crypto feedback mode */ -+#define SAFE_SA_CMD1_64BIT 0x00000000 /* 64-bit crypto feedback */ -+#define SAFE_SA_CMD1_8BIT 0x00000400 /* 8-bit crypto feedback */ -+#define SAFE_SA_CMD1_1BIT 0x00000800 /* 1-bit crypto feedback */ -+#define SAFE_SA_CMD1_128BIT 0x00000c00 /* 128-bit crypto feedback */ -+#define SAFE_SA_CMD1_OPTIONS 0x00001000 /* HMAC/options mutable bit */ -+#define SAFE_SA_CMD1_HMAC SAFE_SA_CMD1_OPTIONS -+#define SAFE_SA_CMD1_SAREV1 0x00008000 /* SA Revision 1 */ -+#define SAFE_SA_CMD1_OFFSET 0x00ff0000 /* hash/crypto offset(dwords) */ -+#define SAFE_SA_CMD1_OFFSET_S 16 -+#define SAFE_SA_CMD1_AESKEYLEN 0x0f000000 /* AES key length */ -+#define SAFE_SA_CMD1_AES128 0x02000000 /* 128-bit AES key */ -+#define SAFE_SA_CMD1_AES192 0x03000000 /* 192-bit AES key */ -+#define SAFE_SA_CMD1_AES256 0x04000000 /* 256-bit AES key */ -+ -+/* -+ * Security Associate State Record (Rev 1). -+ */ -+struct safe_sastate { -+ u_int32_t sa_saved_iv[4]; /* saved IV (DES/3DES/AES) */ -+ u_int32_t sa_saved_hashbc; /* saved hash byte count */ -+ u_int32_t sa_saved_indigest[5]; /* saved inner digest */ -+}; -+#endif /* _SAFE_SAFEREG_H_ */ -diff -Nur linux-2.6.36.orig/crypto/ocf/safe/safevar.h linux-2.6.36/crypto/ocf/safe/safevar.h ---- linux-2.6.36.orig/crypto/ocf/safe/safevar.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/safe/safevar.h 2010-11-09 20:28:13.022495375 +0100 -@@ -0,0 +1,230 @@ -+/*- -+ * The linux port of this code done by David McCullough -+ * Copyright (C) 2004-2010 David McCullough -+ * The license and original author are listed below. -+ * -+ * Copyright (c) 2003 Sam Leffler, Errno Consulting -+ * Copyright (c) 2003 Global Technology Associates, Inc. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ * -+ * $FreeBSD: src/sys/dev/safe/safevar.h,v 1.2 2006/05/17 18:34:26 pjd Exp $ -+ */ -+#ifndef _SAFE_SAFEVAR_H_ -+#define _SAFE_SAFEVAR_H_ -+ -+/* Maximum queue length */ -+#ifndef SAFE_MAX_NQUEUE -+#define SAFE_MAX_NQUEUE 60 -+#endif -+ -+#define SAFE_MAX_PART 64 /* Maximum scatter/gather depth */ -+#define SAFE_DMA_BOUNDARY 0 /* No boundary for source DMA ops */ -+#define SAFE_MAX_DSIZE 2048 /* MCLBYTES Fixed scatter particle size */ -+#define SAFE_MAX_SSIZE 0x0ffff /* Maximum gather particle size */ -+#define SAFE_MAX_DMA 0xfffff /* Maximum PE operand size (20 bits) */ -+/* total src+dst particle descriptors */ -+#define SAFE_TOTAL_DPART (SAFE_MAX_NQUEUE * SAFE_MAX_PART) -+#define SAFE_TOTAL_SPART (SAFE_MAX_NQUEUE * SAFE_MAX_PART) -+ -+#define SAFE_RNG_MAXBUFSIZ 128 /* 32-bit words */ -+ -+#define SAFE_CARD(sid) (((sid) & 0xf0000000) >> 28) -+#define SAFE_SESSION(sid) ( (sid) & 0x0fffffff) -+#define SAFE_SID(crd, sesn) (((crd) << 28) | ((sesn) & 0x0fffffff)) -+ -+#define SAFE_DEF_RTY 0xff /* PCI Retry Timeout */ -+#define SAFE_DEF_TOUT 0xff /* PCI TRDY Timeout */ -+#define SAFE_DEF_CACHELINE 0x01 /* Cache Line setting */ -+ -+#ifdef __KERNEL__ -+/* -+ * State associated with the allocation of each chunk -+ * of memory setup for DMA. -+ */ -+struct safe_dma_alloc { -+ dma_addr_t dma_paddr; -+ void *dma_vaddr; -+}; -+ -+/* -+ * Cryptographic operand state. One of these exists for each -+ * source and destination operand passed in from the crypto -+ * subsystem. When possible source and destination operands -+ * refer to the same memory. More often they are distinct. -+ * We track the virtual address of each operand as well as -+ * where each is mapped for DMA. -+ */ -+struct safe_operand { -+ union { -+ struct sk_buff *skb; -+ struct uio *io; -+ } u; -+ void *map; -+ int mapsize; /* total number of bytes in segs */ -+ struct { -+ dma_addr_t ds_addr; -+ int ds_len; -+ int ds_tlen; -+ } segs[SAFE_MAX_PART]; -+ int nsegs; -+}; -+ -+/* -+ * Packet engine ring entry and cryptographic operation state. -+ * The packet engine requires a ring of descriptors that contain -+ * pointers to various cryptographic state. However the ring -+ * configuration register allows you to specify an arbitrary size -+ * for ring entries. We use this feature to collect most of the -+ * state for each cryptographic request into one spot. Other than -+ * ring entries only the ``particle descriptors'' (scatter/gather -+ * lists) and the actual operand data are kept separate. The -+ * particle descriptors must also be organized in rings. The -+ * operand data can be located aribtrarily (modulo alignment constraints). -+ * -+ * Note that the descriptor ring is mapped onto the PCI bus so -+ * the hardware can DMA data. This means the entire ring must be -+ * contiguous. -+ */ -+struct safe_ringentry { -+ struct safe_desc re_desc; /* command descriptor */ -+ struct safe_sarec re_sa; /* SA record */ -+ struct safe_sastate re_sastate; /* SA state record */ -+ -+ struct cryptop *re_crp; /* crypto operation */ -+ -+ struct safe_operand re_src; /* source operand */ -+ struct safe_operand re_dst; /* destination operand */ -+ -+ int re_sesn; /* crypto session ID */ -+ int re_flags; -+#define SAFE_QFLAGS_COPYOUTIV 0x1 /* copy back on completion */ -+#define SAFE_QFLAGS_COPYOUTICV 0x2 /* copy back on completion */ -+}; -+ -+#define re_src_skb re_src.u.skb -+#define re_src_io re_src.u.io -+#define re_src_map re_src.map -+#define re_src_nsegs re_src.nsegs -+#define re_src_segs re_src.segs -+#define re_src_mapsize re_src.mapsize -+ -+#define re_dst_skb re_dst.u.skb -+#define re_dst_io re_dst.u.io -+#define re_dst_map re_dst.map -+#define re_dst_nsegs re_dst.nsegs -+#define re_dst_segs re_dst.segs -+#define re_dst_mapsize re_dst.mapsize -+ -+struct rndstate_test; -+ -+struct safe_session { -+ u_int32_t ses_used; -+ u_int32_t ses_klen; /* key length in bits */ -+ u_int32_t ses_key[8]; /* DES/3DES/AES key */ -+ u_int32_t ses_mlen; /* hmac length in bytes */ -+ u_int32_t ses_hminner[5]; /* hmac inner state */ -+ u_int32_t ses_hmouter[5]; /* hmac outer state */ -+ u_int32_t ses_iv[4]; /* DES/3DES/AES iv */ -+}; -+ -+struct safe_pkq { -+ struct list_head pkq_list; -+ struct cryptkop *pkq_krp; -+}; -+ -+struct safe_softc { -+ softc_device_decl sc_dev; -+ u32 sc_irq; -+ -+ struct pci_dev *sc_pcidev; -+ ocf_iomem_t sc_base_addr; -+ -+ u_int sc_chiprev; /* major/minor chip revision */ -+ int sc_flags; /* device specific flags */ -+#define SAFE_FLAGS_KEY 0x01 /* has key accelerator */ -+#define SAFE_FLAGS_RNG 0x02 /* hardware rng */ -+ int sc_suspended; -+ int sc_needwakeup; /* notify crypto layer */ -+ int32_t sc_cid; /* crypto tag */ -+ -+ struct safe_dma_alloc sc_ringalloc; /* PE ring allocation state */ -+ struct safe_ringentry *sc_ring; /* PE ring */ -+ struct safe_ringentry *sc_ringtop; /* PE ring top */ -+ struct safe_ringentry *sc_front; /* next free entry */ -+ struct safe_ringentry *sc_back; /* next pending entry */ -+ int sc_nqchip; /* # passed to chip */ -+ spinlock_t sc_ringmtx; /* PE ring lock */ -+ struct safe_pdesc *sc_spring; /* src particle ring */ -+ struct safe_pdesc *sc_springtop; /* src particle ring top */ -+ struct safe_pdesc *sc_spfree; /* next free src particle */ -+ struct safe_dma_alloc sc_spalloc; /* src particle ring state */ -+ struct safe_pdesc *sc_dpring; /* dest particle ring */ -+ struct safe_pdesc *sc_dpringtop; /* dest particle ring top */ -+ struct safe_pdesc *sc_dpfree; /* next free dest particle */ -+ struct safe_dma_alloc sc_dpalloc; /* dst particle ring state */ -+ int sc_nsessions; /* # of sessions */ -+ struct safe_session *sc_sessions; /* sessions */ -+ -+ struct timer_list sc_pkto; /* PK polling */ -+ spinlock_t sc_pkmtx; /* PK lock */ -+ struct list_head sc_pkq; /* queue of PK requests */ -+ struct safe_pkq *sc_pkq_cur; /* current processing request */ -+ u_int32_t sc_pk_reslen, sc_pk_resoff; -+ -+ int sc_max_dsize; /* maximum safe DMA size */ -+}; -+#endif /* __KERNEL__ */ -+ -+struct safe_stats { -+ u_int64_t st_ibytes; -+ u_int64_t st_obytes; -+ u_int32_t st_ipackets; -+ u_int32_t st_opackets; -+ u_int32_t st_invalid; /* invalid argument */ -+ u_int32_t st_badsession; /* invalid session id */ -+ u_int32_t st_badflags; /* flags indicate !(mbuf | uio) */ -+ u_int32_t st_nodesc; /* op submitted w/o descriptors */ -+ u_int32_t st_badalg; /* unsupported algorithm */ -+ u_int32_t st_ringfull; /* PE descriptor ring full */ -+ u_int32_t st_peoperr; /* PE marked error */ -+ u_int32_t st_dmaerr; /* PE DMA error */ -+ u_int32_t st_bypasstoobig; /* bypass > 96 bytes */ -+ u_int32_t st_skipmismatch; /* enc part begins before auth part */ -+ u_int32_t st_lenmismatch; /* enc length different auth length */ -+ u_int32_t st_coffmisaligned; /* crypto offset not 32-bit aligned */ -+ u_int32_t st_cofftoobig; /* crypto offset > 255 words */ -+ u_int32_t st_iovmisaligned; /* iov op not aligned */ -+ u_int32_t st_iovnotuniform; /* iov op not suitable */ -+ u_int32_t st_unaligned; /* unaligned src caused copy */ -+ u_int32_t st_notuniform; /* non-uniform src caused copy */ -+ u_int32_t st_nomap; /* bus_dmamap_create failed */ -+ u_int32_t st_noload; /* bus_dmamap_load_* failed */ -+ u_int32_t st_nombuf; /* MGET* failed */ -+ u_int32_t st_nomcl; /* MCLGET* failed */ -+ u_int32_t st_maxqchip; /* max mcr1 ops out for processing */ -+ u_int32_t st_rng; /* RNG requests */ -+ u_int32_t st_rngalarm; /* RNG alarm requests */ -+ u_int32_t st_noicvcopy; /* ICV data copies suppressed */ -+}; -+#endif /* _SAFE_SAFEVAR_H_ */ -diff -Nur linux-2.6.36.orig/crypto/ocf/safe/sha1.c linux-2.6.36/crypto/ocf/safe/sha1.c ---- linux-2.6.36.orig/crypto/ocf/safe/sha1.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/safe/sha1.c 2010-11-09 20:28:13.072495484 +0100 -@@ -0,0 +1,279 @@ -+/* $KAME: sha1.c,v 1.5 2000/11/08 06:13:08 itojun Exp $ */ -+/* -+ * Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. Neither the name of the project nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ */ -+ -+/* -+ * FIPS pub 180-1: Secure Hash Algorithm (SHA-1) -+ * based on: http://csrc.nist.gov/fips/fip180-1.txt -+ * implemented by Jun-ichiro itojun Itoh -+ */ -+ -+#if 0 -+#include -+__FBSDID("$FreeBSD: src/sys/crypto/sha1.c,v 1.9 2003/06/10 21:36:57 obrien Exp $"); -+ -+#include -+#include -+#include -+#include -+ -+#include -+#endif -+ -+/* sanity check */ -+#if BYTE_ORDER != BIG_ENDIAN -+# if BYTE_ORDER != LITTLE_ENDIAN -+# define unsupported 1 -+# endif -+#endif -+ -+#ifndef unsupported -+ -+/* constant table */ -+static u_int32_t _K[] = { 0x5a827999, 0x6ed9eba1, 0x8f1bbcdc, 0xca62c1d6 }; -+#define K(t) _K[(t) / 20] -+ -+#define F0(b, c, d) (((b) & (c)) | ((~(b)) & (d))) -+#define F1(b, c, d) (((b) ^ (c)) ^ (d)) -+#define F2(b, c, d) (((b) & (c)) | ((b) & (d)) | ((c) & (d))) -+#define F3(b, c, d) (((b) ^ (c)) ^ (d)) -+ -+#define S(n, x) (((x) << (n)) | ((x) >> (32 - n))) -+ -+#undef H -+#define H(n) (ctxt->h.b32[(n)]) -+#define COUNT (ctxt->count) -+#define BCOUNT (ctxt->c.b64[0] / 8) -+#define W(n) (ctxt->m.b32[(n)]) -+ -+#define PUTBYTE(x) { \ -+ ctxt->m.b8[(COUNT % 64)] = (x); \ -+ COUNT++; \ -+ COUNT %= 64; \ -+ ctxt->c.b64[0] += 8; \ -+ if (COUNT % 64 == 0) \ -+ sha1_step(ctxt); \ -+ } -+ -+#define PUTPAD(x) { \ -+ ctxt->m.b8[(COUNT % 64)] = (x); \ -+ COUNT++; \ -+ COUNT %= 64; \ -+ if (COUNT % 64 == 0) \ -+ sha1_step(ctxt); \ -+ } -+ -+static void sha1_step(struct sha1_ctxt *); -+ -+static void -+sha1_step(ctxt) -+ struct sha1_ctxt *ctxt; -+{ -+ u_int32_t a, b, c, d, e; -+ size_t t, s; -+ u_int32_t tmp; -+ -+#if BYTE_ORDER == LITTLE_ENDIAN -+ struct sha1_ctxt tctxt; -+ bcopy(&ctxt->m.b8[0], &tctxt.m.b8[0], 64); -+ ctxt->m.b8[0] = tctxt.m.b8[3]; ctxt->m.b8[1] = tctxt.m.b8[2]; -+ ctxt->m.b8[2] = tctxt.m.b8[1]; ctxt->m.b8[3] = tctxt.m.b8[0]; -+ ctxt->m.b8[4] = tctxt.m.b8[7]; ctxt->m.b8[5] = tctxt.m.b8[6]; -+ ctxt->m.b8[6] = tctxt.m.b8[5]; ctxt->m.b8[7] = tctxt.m.b8[4]; -+ ctxt->m.b8[8] = tctxt.m.b8[11]; ctxt->m.b8[9] = tctxt.m.b8[10]; -+ ctxt->m.b8[10] = tctxt.m.b8[9]; ctxt->m.b8[11] = tctxt.m.b8[8]; -+ ctxt->m.b8[12] = tctxt.m.b8[15]; ctxt->m.b8[13] = tctxt.m.b8[14]; -+ ctxt->m.b8[14] = tctxt.m.b8[13]; ctxt->m.b8[15] = tctxt.m.b8[12]; -+ ctxt->m.b8[16] = tctxt.m.b8[19]; ctxt->m.b8[17] = tctxt.m.b8[18]; -+ ctxt->m.b8[18] = tctxt.m.b8[17]; ctxt->m.b8[19] = tctxt.m.b8[16]; -+ ctxt->m.b8[20] = tctxt.m.b8[23]; ctxt->m.b8[21] = tctxt.m.b8[22]; -+ ctxt->m.b8[22] = tctxt.m.b8[21]; ctxt->m.b8[23] = tctxt.m.b8[20]; -+ ctxt->m.b8[24] = tctxt.m.b8[27]; ctxt->m.b8[25] = tctxt.m.b8[26]; -+ ctxt->m.b8[26] = tctxt.m.b8[25]; ctxt->m.b8[27] = tctxt.m.b8[24]; -+ ctxt->m.b8[28] = tctxt.m.b8[31]; ctxt->m.b8[29] = tctxt.m.b8[30]; -+ ctxt->m.b8[30] = tctxt.m.b8[29]; ctxt->m.b8[31] = tctxt.m.b8[28]; -+ ctxt->m.b8[32] = tctxt.m.b8[35]; ctxt->m.b8[33] = tctxt.m.b8[34]; -+ ctxt->m.b8[34] = tctxt.m.b8[33]; ctxt->m.b8[35] = tctxt.m.b8[32]; -+ ctxt->m.b8[36] = tctxt.m.b8[39]; ctxt->m.b8[37] = tctxt.m.b8[38]; -+ ctxt->m.b8[38] = tctxt.m.b8[37]; ctxt->m.b8[39] = tctxt.m.b8[36]; -+ ctxt->m.b8[40] = tctxt.m.b8[43]; ctxt->m.b8[41] = tctxt.m.b8[42]; -+ ctxt->m.b8[42] = tctxt.m.b8[41]; ctxt->m.b8[43] = tctxt.m.b8[40]; -+ ctxt->m.b8[44] = tctxt.m.b8[47]; ctxt->m.b8[45] = tctxt.m.b8[46]; -+ ctxt->m.b8[46] = tctxt.m.b8[45]; ctxt->m.b8[47] = tctxt.m.b8[44]; -+ ctxt->m.b8[48] = tctxt.m.b8[51]; ctxt->m.b8[49] = tctxt.m.b8[50]; -+ ctxt->m.b8[50] = tctxt.m.b8[49]; ctxt->m.b8[51] = tctxt.m.b8[48]; -+ ctxt->m.b8[52] = tctxt.m.b8[55]; ctxt->m.b8[53] = tctxt.m.b8[54]; -+ ctxt->m.b8[54] = tctxt.m.b8[53]; ctxt->m.b8[55] = tctxt.m.b8[52]; -+ ctxt->m.b8[56] = tctxt.m.b8[59]; ctxt->m.b8[57] = tctxt.m.b8[58]; -+ ctxt->m.b8[58] = tctxt.m.b8[57]; ctxt->m.b8[59] = tctxt.m.b8[56]; -+ ctxt->m.b8[60] = tctxt.m.b8[63]; ctxt->m.b8[61] = tctxt.m.b8[62]; -+ ctxt->m.b8[62] = tctxt.m.b8[61]; ctxt->m.b8[63] = tctxt.m.b8[60]; -+#endif -+ -+ a = H(0); b = H(1); c = H(2); d = H(3); e = H(4); -+ -+ for (t = 0; t < 20; t++) { -+ s = t & 0x0f; -+ if (t >= 16) { -+ W(s) = S(1, W((s+13) & 0x0f) ^ W((s+8) & 0x0f) ^ W((s+2) & 0x0f) ^ W(s)); -+ } -+ tmp = S(5, a) + F0(b, c, d) + e + W(s) + K(t); -+ e = d; d = c; c = S(30, b); b = a; a = tmp; -+ } -+ for (t = 20; t < 40; t++) { -+ s = t & 0x0f; -+ W(s) = S(1, W((s+13) & 0x0f) ^ W((s+8) & 0x0f) ^ W((s+2) & 0x0f) ^ W(s)); -+ tmp = S(5, a) + F1(b, c, d) + e + W(s) + K(t); -+ e = d; d = c; c = S(30, b); b = a; a = tmp; -+ } -+ for (t = 40; t < 60; t++) { -+ s = t & 0x0f; -+ W(s) = S(1, W((s+13) & 0x0f) ^ W((s+8) & 0x0f) ^ W((s+2) & 0x0f) ^ W(s)); -+ tmp = S(5, a) + F2(b, c, d) + e + W(s) + K(t); -+ e = d; d = c; c = S(30, b); b = a; a = tmp; -+ } -+ for (t = 60; t < 80; t++) { -+ s = t & 0x0f; -+ W(s) = S(1, W((s+13) & 0x0f) ^ W((s+8) & 0x0f) ^ W((s+2) & 0x0f) ^ W(s)); -+ tmp = S(5, a) + F3(b, c, d) + e + W(s) + K(t); -+ e = d; d = c; c = S(30, b); b = a; a = tmp; -+ } -+ -+ H(0) = H(0) + a; -+ H(1) = H(1) + b; -+ H(2) = H(2) + c; -+ H(3) = H(3) + d; -+ H(4) = H(4) + e; -+ -+ bzero(&ctxt->m.b8[0], 64); -+} -+ -+/*------------------------------------------------------------*/ -+ -+void -+sha1_init(ctxt) -+ struct sha1_ctxt *ctxt; -+{ -+ bzero(ctxt, sizeof(struct sha1_ctxt)); -+ H(0) = 0x67452301; -+ H(1) = 0xefcdab89; -+ H(2) = 0x98badcfe; -+ H(3) = 0x10325476; -+ H(4) = 0xc3d2e1f0; -+} -+ -+void -+sha1_pad(ctxt) -+ struct sha1_ctxt *ctxt; -+{ -+ size_t padlen; /*pad length in bytes*/ -+ size_t padstart; -+ -+ PUTPAD(0x80); -+ -+ padstart = COUNT % 64; -+ padlen = 64 - padstart; -+ if (padlen < 8) { -+ bzero(&ctxt->m.b8[padstart], padlen); -+ COUNT += padlen; -+ COUNT %= 64; -+ sha1_step(ctxt); -+ padstart = COUNT % 64; /* should be 0 */ -+ padlen = 64 - padstart; /* should be 64 */ -+ } -+ bzero(&ctxt->m.b8[padstart], padlen - 8); -+ COUNT += (padlen - 8); -+ COUNT %= 64; -+#if BYTE_ORDER == BIG_ENDIAN -+ PUTPAD(ctxt->c.b8[0]); PUTPAD(ctxt->c.b8[1]); -+ PUTPAD(ctxt->c.b8[2]); PUTPAD(ctxt->c.b8[3]); -+ PUTPAD(ctxt->c.b8[4]); PUTPAD(ctxt->c.b8[5]); -+ PUTPAD(ctxt->c.b8[6]); PUTPAD(ctxt->c.b8[7]); -+#else -+ PUTPAD(ctxt->c.b8[7]); PUTPAD(ctxt->c.b8[6]); -+ PUTPAD(ctxt->c.b8[5]); PUTPAD(ctxt->c.b8[4]); -+ PUTPAD(ctxt->c.b8[3]); PUTPAD(ctxt->c.b8[2]); -+ PUTPAD(ctxt->c.b8[1]); PUTPAD(ctxt->c.b8[0]); -+#endif -+} -+ -+void -+sha1_loop(ctxt, input, len) -+ struct sha1_ctxt *ctxt; -+ const u_int8_t *input; -+ size_t len; -+{ -+ size_t gaplen; -+ size_t gapstart; -+ size_t off; -+ size_t copysiz; -+ -+ off = 0; -+ -+ while (off < len) { -+ gapstart = COUNT % 64; -+ gaplen = 64 - gapstart; -+ -+ copysiz = (gaplen < len - off) ? gaplen : len - off; -+ bcopy(&input[off], &ctxt->m.b8[gapstart], copysiz); -+ COUNT += copysiz; -+ COUNT %= 64; -+ ctxt->c.b64[0] += copysiz * 8; -+ if (COUNT % 64 == 0) -+ sha1_step(ctxt); -+ off += copysiz; -+ } -+} -+ -+void -+sha1_result(ctxt, digest0) -+ struct sha1_ctxt *ctxt; -+ caddr_t digest0; -+{ -+ u_int8_t *digest; -+ -+ digest = (u_int8_t *)digest0; -+ sha1_pad(ctxt); -+#if BYTE_ORDER == BIG_ENDIAN -+ bcopy(&ctxt->h.b8[0], digest, 20); -+#else -+ digest[0] = ctxt->h.b8[3]; digest[1] = ctxt->h.b8[2]; -+ digest[2] = ctxt->h.b8[1]; digest[3] = ctxt->h.b8[0]; -+ digest[4] = ctxt->h.b8[7]; digest[5] = ctxt->h.b8[6]; -+ digest[6] = ctxt->h.b8[5]; digest[7] = ctxt->h.b8[4]; -+ digest[8] = ctxt->h.b8[11]; digest[9] = ctxt->h.b8[10]; -+ digest[10] = ctxt->h.b8[9]; digest[11] = ctxt->h.b8[8]; -+ digest[12] = ctxt->h.b8[15]; digest[13] = ctxt->h.b8[14]; -+ digest[14] = ctxt->h.b8[13]; digest[15] = ctxt->h.b8[12]; -+ digest[16] = ctxt->h.b8[19]; digest[17] = ctxt->h.b8[18]; -+ digest[18] = ctxt->h.b8[17]; digest[19] = ctxt->h.b8[16]; -+#endif -+} -+ -+#endif /*unsupported*/ -diff -Nur linux-2.6.36.orig/crypto/ocf/safe/sha1.h linux-2.6.36/crypto/ocf/safe/sha1.h ---- linux-2.6.36.orig/crypto/ocf/safe/sha1.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/safe/sha1.h 2010-11-09 20:28:13.112495423 +0100 -@@ -0,0 +1,72 @@ -+/* $FreeBSD: src/sys/crypto/sha1.h,v 1.8 2002/03/20 05:13:50 alfred Exp $ */ -+/* $KAME: sha1.h,v 1.5 2000/03/27 04:36:23 sumikawa Exp $ */ -+ -+/* -+ * Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. Neither the name of the project nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ */ -+/* -+ * FIPS pub 180-1: Secure Hash Algorithm (SHA-1) -+ * based on: http://csrc.nist.gov/fips/fip180-1.txt -+ * implemented by Jun-ichiro itojun Itoh -+ */ -+ -+#ifndef _NETINET6_SHA1_H_ -+#define _NETINET6_SHA1_H_ -+ -+struct sha1_ctxt { -+ union { -+ u_int8_t b8[20]; -+ u_int32_t b32[5]; -+ } h; -+ union { -+ u_int8_t b8[8]; -+ u_int64_t b64[1]; -+ } c; -+ union { -+ u_int8_t b8[64]; -+ u_int32_t b32[16]; -+ } m; -+ u_int8_t count; -+}; -+ -+#ifdef __KERNEL__ -+extern void sha1_init(struct sha1_ctxt *); -+extern void sha1_pad(struct sha1_ctxt *); -+extern void sha1_loop(struct sha1_ctxt *, const u_int8_t *, size_t); -+extern void sha1_result(struct sha1_ctxt *, caddr_t); -+ -+/* compatibilty with other SHA1 source codes */ -+typedef struct sha1_ctxt SHA1_CTX; -+#define SHA1Init(x) sha1_init((x)) -+#define SHA1Update(x, y, z) sha1_loop((x), (y), (z)) -+#define SHA1Final(x, y) sha1_result((y), (x)) -+#endif /* __KERNEL__ */ -+ -+#define SHA1_RESULTLEN (160/8) -+ -+#endif /*_NETINET6_SHA1_H_*/ -diff -Nur linux-2.6.36.orig/crypto/ocf/talitos/Makefile linux-2.6.36/crypto/ocf/talitos/Makefile ---- linux-2.6.36.orig/crypto/ocf/talitos/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/talitos/Makefile 2010-11-09 20:28:13.155214387 +0100 -@@ -0,0 +1,12 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+obj-$(CONFIG_OCF_TALITOS) += talitos.o -+ -+obj ?= . -+EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/talitos/talitos.c linux-2.6.36/crypto/ocf/talitos/talitos.c ---- linux-2.6.36.orig/crypto/ocf/talitos/talitos.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/talitos/talitos.c 2010-11-09 20:28:13.192104548 +0100 -@@ -0,0 +1,1359 @@ -+/* -+ * crypto/ocf/talitos/talitos.c -+ * -+ * An OCF-Linux module that uses Freescale's SEC to do the crypto. -+ * Based on crypto/ocf/hifn and crypto/ocf/safe OCF drivers -+ * -+ * Copyright (c) 2006 Freescale Semiconductor, Inc. -+ * -+ * This code written by Kim A. B. Phillips -+ * some code copied from files with the following: -+ * Copyright (C) 2004-2007 David McCullough -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * --------------------------------------------------------------------------- -+ * -+ * NOTES: -+ * -+ * The Freescale SEC (also known as 'talitos') resides on the -+ * internal bus, and runs asynchronous to the processor core. It has -+ * a wide gamut of cryptographic acceleration features, including single- -+ * pass IPsec (also known as algorithm chaining). To properly utilize -+ * all of the SEC's performance enhancing features, further reworking -+ * of higher level code (framework, applications) will be necessary. -+ * -+ * The following table shows which SEC version is present in which devices: -+ * -+ * Devices SEC version -+ * -+ * 8272, 8248 SEC 1.0 -+ * 885, 875 SEC 1.2 -+ * 8555E, 8541E SEC 2.0 -+ * 8349E SEC 2.01 -+ * 8548E SEC 2.1 -+ * -+ * The following table shows the features offered by each SEC version: -+ * -+ * Max. chan- -+ * version Bus I/F Clock nels DEU AESU AFEU MDEU PKEU RNG KEU -+ * -+ * SEC 1.0 internal 64b 100MHz 4 1 1 1 1 1 1 0 -+ * SEC 1.2 internal 32b 66MHz 1 1 1 0 1 0 0 0 -+ * SEC 2.0 internal 64b 166MHz 4 1 1 1 1 1 1 0 -+ * SEC 2.01 internal 64b 166MHz 4 1 1 1 1 1 1 0 -+ * SEC 2.1 internal 64b 333MHz 4 1 1 1 1 1 1 1 -+ * -+ * Each execution unit in the SEC has two modes of execution; channel and -+ * slave/debug. This driver employs the channel infrastructure in the -+ * device for convenience. Only the RNG is directly accessed due to the -+ * convenience of its random fifo pool. The relationship between the -+ * channels and execution units is depicted in the following diagram: -+ * -+ * ------- ------------ -+ * ---| ch0 |---| | -+ * ------- | | -+ * | |------+-------+-------+-------+------------ -+ * ------- | | | | | | | -+ * ---| ch1 |---| | | | | | | -+ * ------- | | ------ ------ ------ ------ ------ -+ * |controller| |DEU | |AESU| |MDEU| |PKEU| ... |RNG | -+ * ------- | | ------ ------ ------ ------ ------ -+ * ---| ch2 |---| | | | | | | -+ * ------- | | | | | | | -+ * | |------+-------+-------+-------+------------ -+ * ------- | | -+ * ---| ch3 |---| | -+ * ------- ------------ -+ * -+ * Channel ch0 may drive an aes operation to the aes unit (AESU), -+ * and, at the same time, ch1 may drive a message digest operation -+ * to the mdeu. Each channel has an input descriptor FIFO, and the -+ * FIFO can contain, e.g. on the 8541E, up to 24 entries, before a -+ * a buffer overrun error is triggered. The controller is responsible -+ * for fetching the data from descriptor pointers, and passing the -+ * data to the appropriate EUs. The controller also writes the -+ * cryptographic operation's result to memory. The SEC notifies -+ * completion by triggering an interrupt and/or setting the 1st byte -+ * of the hdr field to 0xff. -+ * -+ * TODO: -+ * o support more algorithms -+ * o support more versions of the SEC -+ * o add support for linux 2.4 -+ * o scatter-gather (sg) support -+ * o add support for public key ops (PKEU) -+ * o add statistics -+ */ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include /* dma_map_single() */ -+#include -+ -+#include -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,15) -+#include -+#endif -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) -+#include -+#endif -+ -+#include -+#include -+ -+#define DRV_NAME "talitos" -+ -+#include "talitos_dev.h" -+#include "talitos_soft.h" -+ -+#define read_random(p,l) get_random_bytes(p,l) -+ -+const char talitos_driver_name[] = "Talitos OCF"; -+const char talitos_driver_version[] = "0.2"; -+ -+static int talitos_newsession(device_t dev, u_int32_t *sidp, -+ struct cryptoini *cri); -+static int talitos_freesession(device_t dev, u_int64_t tid); -+static int talitos_process(device_t dev, struct cryptop *crp, int hint); -+static void dump_talitos_status(struct talitos_softc *sc); -+static int talitos_submit(struct talitos_softc *sc, struct talitos_desc *td, -+ int chsel); -+static void talitos_doneprocessing(struct talitos_softc *sc); -+static void talitos_init_device(struct talitos_softc *sc); -+static void talitos_reset_device_master(struct talitos_softc *sc); -+static void talitos_reset_device(struct talitos_softc *sc); -+static void talitos_errorprocessing(struct talitos_softc *sc); -+#ifdef CONFIG_PPC_MERGE -+static int talitos_probe(struct of_device *ofdev, const struct of_device_id *match); -+static int talitos_remove(struct of_device *ofdev); -+#else -+static int talitos_probe(struct platform_device *pdev); -+static int talitos_remove(struct platform_device *pdev); -+#endif -+#ifdef CONFIG_OCF_RANDOMHARVEST -+static int talitos_read_random(void *arg, u_int32_t *buf, int maxwords); -+static void talitos_rng_init(struct talitos_softc *sc); -+#endif -+ -+static device_method_t talitos_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, talitos_newsession), -+ DEVMETHOD(cryptodev_freesession,talitos_freesession), -+ DEVMETHOD(cryptodev_process, talitos_process), -+}; -+ -+#define debug talitos_debug -+int talitos_debug = 0; -+module_param(talitos_debug, int, 0644); -+MODULE_PARM_DESC(talitos_debug, "Enable debug"); -+ -+static inline void talitos_write(volatile unsigned *addr, u32 val) -+{ -+ out_be32(addr, val); -+} -+ -+static inline u32 talitos_read(volatile unsigned *addr) -+{ -+ u32 val; -+ val = in_be32(addr); -+ return val; -+} -+ -+static void dump_talitos_status(struct talitos_softc *sc) -+{ -+ unsigned int v, v_hi, i, *ptr; -+ v = talitos_read(sc->sc_base_addr + TALITOS_MCR); -+ v_hi = talitos_read(sc->sc_base_addr + TALITOS_MCR_HI); -+ printk(KERN_INFO "%s: MCR 0x%08x_%08x\n", -+ device_get_nameunit(sc->sc_cdev), v, v_hi); -+ v = talitos_read(sc->sc_base_addr + TALITOS_IMR); -+ v_hi = talitos_read(sc->sc_base_addr + TALITOS_IMR_HI); -+ printk(KERN_INFO "%s: IMR 0x%08x_%08x\n", -+ device_get_nameunit(sc->sc_cdev), v, v_hi); -+ v = talitos_read(sc->sc_base_addr + TALITOS_ISR); -+ v_hi = talitos_read(sc->sc_base_addr + TALITOS_ISR_HI); -+ printk(KERN_INFO "%s: ISR 0x%08x_%08x\n", -+ device_get_nameunit(sc->sc_cdev), v, v_hi); -+ for (i = 0; i < sc->sc_num_channels; i++) { -+ v = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + -+ TALITOS_CH_CDPR); -+ v_hi = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + -+ TALITOS_CH_CDPR_HI); -+ printk(KERN_INFO "%s: CDPR ch%d 0x%08x_%08x\n", -+ device_get_nameunit(sc->sc_cdev), i, v, v_hi); -+ } -+ for (i = 0; i < sc->sc_num_channels; i++) { -+ v = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + -+ TALITOS_CH_CCPSR); -+ v_hi = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + -+ TALITOS_CH_CCPSR_HI); -+ printk(KERN_INFO "%s: CCPSR ch%d 0x%08x_%08x\n", -+ device_get_nameunit(sc->sc_cdev), i, v, v_hi); -+ } -+ ptr = sc->sc_base_addr + TALITOS_CH_DESCBUF; -+ for (i = 0; i < 16; i++) { -+ v = talitos_read(ptr++); v_hi = talitos_read(ptr++); -+ printk(KERN_INFO "%s: DESCBUF ch0 0x%08x_%08x (tdp%02d)\n", -+ device_get_nameunit(sc->sc_cdev), v, v_hi, i); -+ } -+ return; -+} -+ -+ -+#ifdef CONFIG_OCF_RANDOMHARVEST -+/* -+ * pull random numbers off the RNG FIFO, not exceeding amount available -+ */ -+static int -+talitos_read_random(void *arg, u_int32_t *buf, int maxwords) -+{ -+ struct talitos_softc *sc = (struct talitos_softc *) arg; -+ int rc; -+ u_int32_t v; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ /* check for things like FIFO underflow */ -+ v = talitos_read(sc->sc_base_addr + TALITOS_RNGISR_HI); -+ if (unlikely(v)) { -+ printk(KERN_ERR "%s: RNGISR_HI error %08x\n", -+ device_get_nameunit(sc->sc_cdev), v); -+ return 0; -+ } -+ /* -+ * OFL is number of available 64-bit words, -+ * shift and convert to a 32-bit word count -+ */ -+ v = talitos_read(sc->sc_base_addr + TALITOS_RNGSR_HI); -+ v = (v & TALITOS_RNGSR_HI_OFL) >> (16 - 1); -+ if (maxwords > v) -+ maxwords = v; -+ for (rc = 0; rc < maxwords; rc++) { -+ buf[rc] = talitos_read(sc->sc_base_addr + -+ TALITOS_RNG_FIFO + rc*sizeof(u_int32_t)); -+ } -+ if (maxwords & 1) { -+ /* -+ * RNG will complain with an AE in the RNGISR -+ * if we don't complete the pairs of 32-bit reads -+ * to its 64-bit register based FIFO -+ */ -+ v = talitos_read(sc->sc_base_addr + -+ TALITOS_RNG_FIFO + rc*sizeof(u_int32_t)); -+ } -+ -+ return rc; -+} -+ -+static void -+talitos_rng_init(struct talitos_softc *sc) -+{ -+ u_int32_t v; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ /* reset RNG EU */ -+ v = talitos_read(sc->sc_base_addr + TALITOS_RNGRCR_HI); -+ v |= TALITOS_RNGRCR_HI_SR; -+ talitos_write(sc->sc_base_addr + TALITOS_RNGRCR_HI, v); -+ while ((talitos_read(sc->sc_base_addr + TALITOS_RNGSR_HI) -+ & TALITOS_RNGSR_HI_RD) == 0) -+ cpu_relax(); -+ /* -+ * we tell the RNG to start filling the RNG FIFO -+ * by writing the RNGDSR -+ */ -+ v = talitos_read(sc->sc_base_addr + TALITOS_RNGDSR_HI); -+ talitos_write(sc->sc_base_addr + TALITOS_RNGDSR_HI, v); -+ /* -+ * 64 bits of data will be pushed onto the FIFO every -+ * 256 SEC cycles until the FIFO is full. The RNG then -+ * attempts to keep the FIFO full. -+ */ -+ v = talitos_read(sc->sc_base_addr + TALITOS_RNGISR_HI); -+ if (v) { -+ printk(KERN_ERR "%s: RNGISR_HI error %08x\n", -+ device_get_nameunit(sc->sc_cdev), v); -+ return; -+ } -+ /* -+ * n.b. we need to add a FIPS test here - if the RNG is going -+ * to fail, it's going to fail at reset time -+ */ -+ return; -+} -+#endif /* CONFIG_OCF_RANDOMHARVEST */ -+ -+/* -+ * Generate a new software session. -+ */ -+static int -+talitos_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) -+{ -+ struct cryptoini *c, *encini = NULL, *macini = NULL; -+ struct talitos_softc *sc = device_get_softc(dev); -+ struct talitos_session *ses = NULL; -+ int sesn; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ if (sidp == NULL || cri == NULL || sc == NULL) { -+ DPRINTF("%s,%d - EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ for (c = cri; c != NULL; c = c->cri_next) { -+ if (c->cri_alg == CRYPTO_MD5 || -+ c->cri_alg == CRYPTO_MD5_HMAC || -+ c->cri_alg == CRYPTO_SHA1 || -+ c->cri_alg == CRYPTO_SHA1_HMAC || -+ c->cri_alg == CRYPTO_NULL_HMAC) { -+ if (macini) -+ return EINVAL; -+ macini = c; -+ } else if (c->cri_alg == CRYPTO_DES_CBC || -+ c->cri_alg == CRYPTO_3DES_CBC || -+ c->cri_alg == CRYPTO_AES_CBC || -+ c->cri_alg == CRYPTO_NULL_CBC) { -+ if (encini) -+ return EINVAL; -+ encini = c; -+ } else { -+ DPRINTF("UNKNOWN c->cri_alg %d\n", encini->cri_alg); -+ return EINVAL; -+ } -+ } -+ if (encini == NULL && macini == NULL) -+ return EINVAL; -+ if (encini) { -+ /* validate key length */ -+ switch (encini->cri_alg) { -+ case CRYPTO_DES_CBC: -+ if (encini->cri_klen != 64) -+ return EINVAL; -+ break; -+ case CRYPTO_3DES_CBC: -+ if (encini->cri_klen != 192) { -+ return EINVAL; -+ } -+ break; -+ case CRYPTO_AES_CBC: -+ if (encini->cri_klen != 128 && -+ encini->cri_klen != 192 && -+ encini->cri_klen != 256) -+ return EINVAL; -+ break; -+ default: -+ DPRINTF("UNKNOWN encini->cri_alg %d\n", -+ encini->cri_alg); -+ return EINVAL; -+ } -+ } -+ -+ if (sc->sc_sessions == NULL) { -+ ses = sc->sc_sessions = (struct talitos_session *) -+ kmalloc(sizeof(struct talitos_session), SLAB_ATOMIC); -+ if (ses == NULL) -+ return ENOMEM; -+ memset(ses, 0, sizeof(struct talitos_session)); -+ sesn = 0; -+ sc->sc_nsessions = 1; -+ } else { -+ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { -+ if (sc->sc_sessions[sesn].ses_used == 0) { -+ ses = &sc->sc_sessions[sesn]; -+ break; -+ } -+ } -+ -+ if (ses == NULL) { -+ /* allocating session */ -+ sesn = sc->sc_nsessions; -+ ses = (struct talitos_session *) kmalloc( -+ (sesn + 1) * sizeof(struct talitos_session), -+ SLAB_ATOMIC); -+ if (ses == NULL) -+ return ENOMEM; -+ memset(ses, 0, -+ (sesn + 1) * sizeof(struct talitos_session)); -+ memcpy(ses, sc->sc_sessions, -+ sesn * sizeof(struct talitos_session)); -+ memset(sc->sc_sessions, 0, -+ sesn * sizeof(struct talitos_session)); -+ kfree(sc->sc_sessions); -+ sc->sc_sessions = ses; -+ ses = &sc->sc_sessions[sesn]; -+ sc->sc_nsessions++; -+ } -+ } -+ -+ ses->ses_used = 1; -+ -+ if (encini) { -+ /* get an IV */ -+ /* XXX may read fewer than requested */ -+ read_random(ses->ses_iv, sizeof(ses->ses_iv)); -+ -+ ses->ses_klen = (encini->cri_klen + 7) / 8; -+ memcpy(ses->ses_key, encini->cri_key, ses->ses_klen); -+ if (macini) { -+ /* doing hash on top of cipher */ -+ ses->ses_hmac_len = (macini->cri_klen + 7) / 8; -+ memcpy(ses->ses_hmac, macini->cri_key, -+ ses->ses_hmac_len); -+ } -+ } else if (macini) { -+ /* doing hash */ -+ ses->ses_klen = (macini->cri_klen + 7) / 8; -+ memcpy(ses->ses_key, macini->cri_key, ses->ses_klen); -+ } -+ -+ /* back compat way of determining MSC result len */ -+ if (macini) { -+ ses->ses_mlen = macini->cri_mlen; -+ if (ses->ses_mlen == 0) { -+ if (macini->cri_alg == CRYPTO_MD5_HMAC) -+ ses->ses_mlen = MD5_HASH_LEN; -+ else -+ ses->ses_mlen = SHA1_HASH_LEN; -+ } -+ } -+ -+ /* really should make up a template td here, -+ * and only fill things like i/o and direction in process() */ -+ -+ /* assign session ID */ -+ *sidp = TALITOS_SID(sc->sc_num, sesn); -+ return 0; -+} -+ -+/* -+ * Deallocate a session. -+ */ -+static int -+talitos_freesession(device_t dev, u_int64_t tid) -+{ -+ struct talitos_softc *sc = device_get_softc(dev); -+ int session, ret; -+ u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; -+ -+ if (sc == NULL) -+ return EINVAL; -+ session = TALITOS_SESSION(sid); -+ if (session < sc->sc_nsessions) { -+ memset(&sc->sc_sessions[session], 0, -+ sizeof(sc->sc_sessions[session])); -+ ret = 0; -+ } else -+ ret = EINVAL; -+ return ret; -+} -+ -+/* -+ * launch device processing - it will come back with done notification -+ * in the form of an interrupt and/or HDR_DONE_BITS in header -+ */ -+static int -+talitos_submit( -+ struct talitos_softc *sc, -+ struct talitos_desc *td, -+ int chsel) -+{ -+ u_int32_t v; -+ -+ v = dma_map_single(NULL, td, sizeof(*td), DMA_TO_DEVICE); -+ talitos_write(sc->sc_base_addr + -+ chsel*TALITOS_CH_OFFSET + TALITOS_CH_FF, 0); -+ talitos_write(sc->sc_base_addr + -+ chsel*TALITOS_CH_OFFSET + TALITOS_CH_FF_HI, v); -+ return 0; -+} -+ -+static int -+talitos_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ int i, err = 0, ivsize; -+ struct talitos_softc *sc = device_get_softc(dev); -+ struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; -+ caddr_t iv; -+ struct talitos_session *ses; -+ struct talitos_desc *td; -+ unsigned long flags; -+ /* descriptor mappings */ -+ int hmac_key, hmac_data, cipher_iv, cipher_key, -+ in_fifo, out_fifo, cipher_iv_out; -+ static int chsel = -1; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { -+ return EINVAL; -+ } -+ crp->crp_etype = 0; -+ if (TALITOS_SESSION(crp->crp_sid) >= sc->sc_nsessions) { -+ return EINVAL; -+ } -+ -+ ses = &sc->sc_sessions[TALITOS_SESSION(crp->crp_sid)]; -+ -+ /* enter the channel scheduler */ -+ spin_lock_irqsave(&sc->sc_chnfifolock[sc->sc_num_channels], flags); -+ -+ /* reuse channel that already had/has requests for the required EU */ -+ for (i = 0; i < sc->sc_num_channels; i++) { -+ if (sc->sc_chnlastalg[i] == crp->crp_desc->crd_alg) -+ break; -+ } -+ if (i == sc->sc_num_channels) { -+ /* -+ * haven't seen this algo the last sc_num_channels or more -+ * use round robin in this case -+ * nb: sc->sc_num_channels must be power of 2 -+ */ -+ chsel = (chsel + 1) & (sc->sc_num_channels - 1); -+ } else { -+ /* -+ * matches channel with same target execution unit; -+ * use same channel in this case -+ */ -+ chsel = i; -+ } -+ sc->sc_chnlastalg[chsel] = crp->crp_desc->crd_alg; -+ -+ /* release the channel scheduler lock */ -+ spin_unlock_irqrestore(&sc->sc_chnfifolock[sc->sc_num_channels], flags); -+ -+ /* acquire the selected channel fifo lock */ -+ spin_lock_irqsave(&sc->sc_chnfifolock[chsel], flags); -+ -+ /* find and reserve next available descriptor-cryptop pair */ -+ for (i = 0; i < sc->sc_chfifo_len; i++) { -+ if (sc->sc_chnfifo[chsel][i].cf_desc.hdr == 0) { -+ /* -+ * ensure correct descriptor formation by -+ * avoiding inadvertently setting "optional" entries -+ * e.g. not using "optional" dptr2 for MD/HMAC descs -+ */ -+ memset(&sc->sc_chnfifo[chsel][i].cf_desc, -+ 0, sizeof(*td)); -+ /* reserve it with done notification request bit */ -+ sc->sc_chnfifo[chsel][i].cf_desc.hdr |= -+ TALITOS_DONE_NOTIFY; -+ break; -+ } -+ } -+ spin_unlock_irqrestore(&sc->sc_chnfifolock[chsel], flags); -+ -+ if (i == sc->sc_chfifo_len) { -+ /* fifo full */ -+ err = ERESTART; -+ goto errout; -+ } -+ -+ td = &sc->sc_chnfifo[chsel][i].cf_desc; -+ sc->sc_chnfifo[chsel][i].cf_crp = crp; -+ -+ crd1 = crp->crp_desc; -+ if (crd1 == NULL) { -+ err = EINVAL; -+ goto errout; -+ } -+ crd2 = crd1->crd_next; -+ /* prevent compiler warning */ -+ hmac_key = 0; -+ hmac_data = 0; -+ if (crd2 == NULL) { -+ td->hdr |= TD_TYPE_COMMON_NONSNOOP_NO_AFEU; -+ /* assign descriptor dword ptr mappings for this desc. type */ -+ cipher_iv = 1; -+ cipher_key = 2; -+ in_fifo = 3; -+ cipher_iv_out = 5; -+ if (crd1->crd_alg == CRYPTO_MD5_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1 || -+ crd1->crd_alg == CRYPTO_MD5) { -+ out_fifo = 5; -+ maccrd = crd1; -+ enccrd = NULL; -+ } else if (crd1->crd_alg == CRYPTO_DES_CBC || -+ crd1->crd_alg == CRYPTO_3DES_CBC || -+ crd1->crd_alg == CRYPTO_AES_CBC || -+ crd1->crd_alg == CRYPTO_ARC4) { -+ out_fifo = 4; -+ maccrd = NULL; -+ enccrd = crd1; -+ } else { -+ DPRINTF("UNKNOWN crd1->crd_alg %d\n", crd1->crd_alg); -+ err = EINVAL; -+ goto errout; -+ } -+ } else { -+ if (sc->sc_desc_types & TALITOS_HAS_DT_IPSEC_ESP) { -+ td->hdr |= TD_TYPE_IPSEC_ESP; -+ } else { -+ DPRINTF("unimplemented: multiple descriptor ipsec\n"); -+ err = EINVAL; -+ goto errout; -+ } -+ /* assign descriptor dword ptr mappings for this desc. type */ -+ hmac_key = 0; -+ hmac_data = 1; -+ cipher_iv = 2; -+ cipher_key = 3; -+ in_fifo = 4; -+ out_fifo = 5; -+ cipher_iv_out = 6; -+ if ((crd1->crd_alg == CRYPTO_MD5_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1_HMAC || -+ crd1->crd_alg == CRYPTO_MD5 || -+ crd1->crd_alg == CRYPTO_SHA1) && -+ (crd2->crd_alg == CRYPTO_DES_CBC || -+ crd2->crd_alg == CRYPTO_3DES_CBC || -+ crd2->crd_alg == CRYPTO_AES_CBC || -+ crd2->crd_alg == CRYPTO_ARC4) && -+ ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { -+ maccrd = crd1; -+ enccrd = crd2; -+ } else if ((crd1->crd_alg == CRYPTO_DES_CBC || -+ crd1->crd_alg == CRYPTO_ARC4 || -+ crd1->crd_alg == CRYPTO_3DES_CBC || -+ crd1->crd_alg == CRYPTO_AES_CBC) && -+ (crd2->crd_alg == CRYPTO_MD5_HMAC || -+ crd2->crd_alg == CRYPTO_SHA1_HMAC || -+ crd2->crd_alg == CRYPTO_MD5 || -+ crd2->crd_alg == CRYPTO_SHA1) && -+ (crd1->crd_flags & CRD_F_ENCRYPT)) { -+ enccrd = crd1; -+ maccrd = crd2; -+ } else { -+ /* We cannot order the SEC as requested */ -+ printk("%s: cannot do the order\n", -+ device_get_nameunit(sc->sc_cdev)); -+ err = EINVAL; -+ goto errout; -+ } -+ } -+ /* assign in_fifo and out_fifo based on input/output struct type */ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ /* using SKB buffers */ -+ struct sk_buff *skb = (struct sk_buff *)crp->crp_buf; -+ if (skb_shinfo(skb)->nr_frags) { -+ printk("%s: skb frags unimplemented\n", -+ device_get_nameunit(sc->sc_cdev)); -+ err = EINVAL; -+ goto errout; -+ } -+ td->ptr[in_fifo].ptr = dma_map_single(NULL, skb->data, -+ skb->len, DMA_TO_DEVICE); -+ td->ptr[in_fifo].len = skb->len; -+ td->ptr[out_fifo].ptr = dma_map_single(NULL, skb->data, -+ skb->len, DMA_TO_DEVICE); -+ td->ptr[out_fifo].len = skb->len; -+ td->ptr[hmac_data].ptr = dma_map_single(NULL, skb->data, -+ skb->len, DMA_TO_DEVICE); -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ /* using IOV buffers */ -+ struct uio *uiop = (struct uio *)crp->crp_buf; -+ if (uiop->uio_iovcnt > 1) { -+ printk("%s: iov frags unimplemented\n", -+ device_get_nameunit(sc->sc_cdev)); -+ err = EINVAL; -+ goto errout; -+ } -+ td->ptr[in_fifo].ptr = dma_map_single(NULL, -+ uiop->uio_iov->iov_base, crp->crp_ilen, DMA_TO_DEVICE); -+ td->ptr[in_fifo].len = crp->crp_ilen; -+ /* crp_olen is never set; always use crp_ilen */ -+ td->ptr[out_fifo].ptr = dma_map_single(NULL, -+ uiop->uio_iov->iov_base, -+ crp->crp_ilen, DMA_TO_DEVICE); -+ td->ptr[out_fifo].len = crp->crp_ilen; -+ } else { -+ /* using contig buffers */ -+ td->ptr[in_fifo].ptr = dma_map_single(NULL, -+ crp->crp_buf, crp->crp_ilen, DMA_TO_DEVICE); -+ td->ptr[in_fifo].len = crp->crp_ilen; -+ td->ptr[out_fifo].ptr = dma_map_single(NULL, -+ crp->crp_buf, crp->crp_ilen, DMA_TO_DEVICE); -+ td->ptr[out_fifo].len = crp->crp_ilen; -+ } -+ if (enccrd) { -+ switch (enccrd->crd_alg) { -+ case CRYPTO_3DES_CBC: -+ td->hdr |= TALITOS_MODE0_DEU_3DES; -+ /* FALLTHROUGH */ -+ case CRYPTO_DES_CBC: -+ td->hdr |= TALITOS_SEL0_DEU -+ | TALITOS_MODE0_DEU_CBC; -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) -+ td->hdr |= TALITOS_MODE0_DEU_ENC; -+ ivsize = 2*sizeof(u_int32_t); -+ DPRINTF("%cDES ses %d ch %d len %d\n", -+ (td->hdr & TALITOS_MODE0_DEU_3DES)?'3':'1', -+ (u32)TALITOS_SESSION(crp->crp_sid), -+ chsel, td->ptr[in_fifo].len); -+ break; -+ case CRYPTO_AES_CBC: -+ td->hdr |= TALITOS_SEL0_AESU -+ | TALITOS_MODE0_AESU_CBC; -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) -+ td->hdr |= TALITOS_MODE0_AESU_ENC; -+ ivsize = 4*sizeof(u_int32_t); -+ DPRINTF("AES ses %d ch %d len %d\n", -+ (u32)TALITOS_SESSION(crp->crp_sid), -+ chsel, td->ptr[in_fifo].len); -+ break; -+ default: -+ printk("%s: unimplemented enccrd->crd_alg %d\n", -+ device_get_nameunit(sc->sc_cdev), enccrd->crd_alg); -+ err = EINVAL; -+ goto errout; -+ } -+ /* -+ * Setup encrypt/decrypt state. When using basic ops -+ * we can't use an inline IV because hash/crypt offset -+ * must be from the end of the IV to the start of the -+ * crypt data and this leaves out the preceding header -+ * from the hash calculation. Instead we place the IV -+ * in the state record and set the hash/crypt offset to -+ * copy both the header+IV. -+ */ -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) { -+ td->hdr |= TALITOS_DIR_OUTBOUND; -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) -+ iv = enccrd->crd_iv; -+ else -+ iv = (caddr_t) ses->ses_iv; -+ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ enccrd->crd_inject, ivsize, iv); -+ } -+ } else { -+ td->hdr |= TALITOS_DIR_INBOUND; -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) { -+ iv = enccrd->crd_iv; -+ bcopy(enccrd->crd_iv, iv, ivsize); -+ } else { -+ iv = (caddr_t) ses->ses_iv; -+ crypto_copydata(crp->crp_flags, crp->crp_buf, -+ enccrd->crd_inject, ivsize, iv); -+ } -+ } -+ td->ptr[cipher_iv].ptr = dma_map_single(NULL, iv, ivsize, -+ DMA_TO_DEVICE); -+ td->ptr[cipher_iv].len = ivsize; -+ /* -+ * we don't need the cipher iv out length/pointer -+ * field to do ESP IPsec. Therefore we set the len field as 0, -+ * which tells the SEC not to do anything with this len/ptr -+ * field. Previously, when length/pointer as pointing to iv, -+ * it gave us corruption of packets. -+ */ -+ td->ptr[cipher_iv_out].len = 0; -+ } -+ if (enccrd && maccrd) { -+ /* this is ipsec only for now */ -+ td->hdr |= TALITOS_SEL1_MDEU -+ | TALITOS_MODE1_MDEU_INIT -+ | TALITOS_MODE1_MDEU_PAD; -+ switch (maccrd->crd_alg) { -+ case CRYPTO_MD5: -+ td->hdr |= TALITOS_MODE1_MDEU_MD5; -+ break; -+ case CRYPTO_MD5_HMAC: -+ td->hdr |= TALITOS_MODE1_MDEU_MD5_HMAC; -+ break; -+ case CRYPTO_SHA1: -+ td->hdr |= TALITOS_MODE1_MDEU_SHA1; -+ break; -+ case CRYPTO_SHA1_HMAC: -+ td->hdr |= TALITOS_MODE1_MDEU_SHA1_HMAC; -+ break; -+ default: -+ /* We cannot order the SEC as requested */ -+ printk("%s: cannot do the order\n", -+ device_get_nameunit(sc->sc_cdev)); -+ err = EINVAL; -+ goto errout; -+ } -+ if ((maccrd->crd_alg == CRYPTO_MD5_HMAC) || -+ (maccrd->crd_alg == CRYPTO_SHA1_HMAC)) { -+ /* -+ * The offset from hash data to the start of -+ * crypt data is the difference in the skips. -+ */ -+ /* ipsec only for now */ -+ td->ptr[hmac_key].ptr = dma_map_single(NULL, -+ ses->ses_hmac, ses->ses_hmac_len, DMA_TO_DEVICE); -+ td->ptr[hmac_key].len = ses->ses_hmac_len; -+ td->ptr[in_fifo].ptr += enccrd->crd_skip; -+ td->ptr[in_fifo].len = enccrd->crd_len; -+ td->ptr[out_fifo].ptr += enccrd->crd_skip; -+ td->ptr[out_fifo].len = enccrd->crd_len; -+ /* bytes of HMAC to postpend to ciphertext */ -+ td->ptr[out_fifo].extent = ses->ses_mlen; -+ td->ptr[hmac_data].ptr += maccrd->crd_skip; -+ td->ptr[hmac_data].len = enccrd->crd_skip - maccrd->crd_skip; -+ } -+ if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) { -+ printk("%s: CRD_F_KEY_EXPLICIT unimplemented\n", -+ device_get_nameunit(sc->sc_cdev)); -+ } -+ } -+ if (!enccrd && maccrd) { -+ /* single MD5 or SHA */ -+ td->hdr |= TALITOS_SEL0_MDEU -+ | TALITOS_MODE0_MDEU_INIT -+ | TALITOS_MODE0_MDEU_PAD; -+ switch (maccrd->crd_alg) { -+ case CRYPTO_MD5: -+ td->hdr |= TALITOS_MODE0_MDEU_MD5; -+ DPRINTF("MD5 ses %d ch %d len %d\n", -+ (u32)TALITOS_SESSION(crp->crp_sid), -+ chsel, td->ptr[in_fifo].len); -+ break; -+ case CRYPTO_MD5_HMAC: -+ td->hdr |= TALITOS_MODE0_MDEU_MD5_HMAC; -+ break; -+ case CRYPTO_SHA1: -+ td->hdr |= TALITOS_MODE0_MDEU_SHA1; -+ DPRINTF("SHA1 ses %d ch %d len %d\n", -+ (u32)TALITOS_SESSION(crp->crp_sid), -+ chsel, td->ptr[in_fifo].len); -+ break; -+ case CRYPTO_SHA1_HMAC: -+ td->hdr |= TALITOS_MODE0_MDEU_SHA1_HMAC; -+ break; -+ default: -+ /* We cannot order the SEC as requested */ -+ DPRINTF("cannot do the order\n"); -+ err = EINVAL; -+ goto errout; -+ } -+ -+ if (crp->crp_flags & CRYPTO_F_IOV) -+ td->ptr[out_fifo].ptr += maccrd->crd_inject; -+ -+ if ((maccrd->crd_alg == CRYPTO_MD5_HMAC) || -+ (maccrd->crd_alg == CRYPTO_SHA1_HMAC)) { -+ td->ptr[hmac_key].ptr = dma_map_single(NULL, -+ ses->ses_hmac, ses->ses_hmac_len, -+ DMA_TO_DEVICE); -+ td->ptr[hmac_key].len = ses->ses_hmac_len; -+ } -+ } -+ else { -+ /* using process key (session data has duplicate) */ -+ td->ptr[cipher_key].ptr = dma_map_single(NULL, -+ enccrd->crd_key, (enccrd->crd_klen + 7) / 8, -+ DMA_TO_DEVICE); -+ td->ptr[cipher_key].len = (enccrd->crd_klen + 7) / 8; -+ } -+ /* descriptor complete - GO! */ -+ return talitos_submit(sc, td, chsel); -+ -+errout: -+ if (err != ERESTART) { -+ crp->crp_etype = err; -+ crypto_done(crp); -+ } -+ return err; -+} -+ -+/* go through all channels descriptors, notifying OCF what has -+ * _and_hasn't_ successfully completed and reset the device -+ * (otherwise it's up to decoding desc hdrs!) -+ */ -+static void talitos_errorprocessing(struct talitos_softc *sc) -+{ -+ unsigned long flags; -+ int i, j; -+ -+ /* disable further scheduling until under control */ -+ spin_lock_irqsave(&sc->sc_chnfifolock[sc->sc_num_channels], flags); -+ -+ if (debug) dump_talitos_status(sc); -+ /* go through descriptors, try and salvage those successfully done, -+ * and EIO those that weren't -+ */ -+ for (i = 0; i < sc->sc_num_channels; i++) { -+ spin_lock_irqsave(&sc->sc_chnfifolock[i], flags); -+ for (j = 0; j < sc->sc_chfifo_len; j++) { -+ if (sc->sc_chnfifo[i][j].cf_desc.hdr) { -+ if ((sc->sc_chnfifo[i][j].cf_desc.hdr -+ & TALITOS_HDR_DONE_BITS) -+ != TALITOS_HDR_DONE_BITS) { -+ /* this one didn't finish */ -+ /* signify in crp->etype */ -+ sc->sc_chnfifo[i][j].cf_crp->crp_etype -+ = EIO; -+ } -+ } else -+ continue; /* free entry */ -+ /* either way, notify ocf */ -+ crypto_done(sc->sc_chnfifo[i][j].cf_crp); -+ /* and tag it available again -+ * -+ * memset to ensure correct descriptor formation by -+ * avoiding inadvertently setting "optional" entries -+ * e.g. not using "optional" dptr2 MD/HMAC processing -+ */ -+ memset(&sc->sc_chnfifo[i][j].cf_desc, -+ 0, sizeof(struct talitos_desc)); -+ } -+ spin_unlock_irqrestore(&sc->sc_chnfifolock[i], flags); -+ } -+ /* reset and initialize the SEC h/w device */ -+ talitos_reset_device(sc); -+ talitos_init_device(sc); -+#ifdef CONFIG_OCF_RANDOMHARVEST -+ if (sc->sc_exec_units & TALITOS_HAS_EU_RNG) -+ talitos_rng_init(sc); -+#endif -+ -+ /* Okay. Stand by. */ -+ spin_unlock_irqrestore(&sc->sc_chnfifolock[sc->sc_num_channels], flags); -+ -+ return; -+} -+ -+/* go through all channels descriptors, notifying OCF what's been done */ -+static void talitos_doneprocessing(struct talitos_softc *sc) -+{ -+ unsigned long flags; -+ int i, j; -+ -+ /* go through descriptors looking for done bits */ -+ for (i = 0; i < sc->sc_num_channels; i++) { -+ spin_lock_irqsave(&sc->sc_chnfifolock[i], flags); -+ for (j = 0; j < sc->sc_chfifo_len; j++) { -+ /* descriptor has done bits set? */ -+ if ((sc->sc_chnfifo[i][j].cf_desc.hdr -+ & TALITOS_HDR_DONE_BITS) -+ == TALITOS_HDR_DONE_BITS) { -+ /* notify ocf */ -+ crypto_done(sc->sc_chnfifo[i][j].cf_crp); -+ /* and tag it available again -+ * -+ * memset to ensure correct descriptor formation by -+ * avoiding inadvertently setting "optional" entries -+ * e.g. not using "optional" dptr2 MD/HMAC processing -+ */ -+ memset(&sc->sc_chnfifo[i][j].cf_desc, -+ 0, sizeof(struct talitos_desc)); -+ } -+ } -+ spin_unlock_irqrestore(&sc->sc_chnfifolock[i], flags); -+ } -+ return; -+} -+ -+static irqreturn_t -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) -+talitos_intr(int irq, void *arg) -+#else -+talitos_intr(int irq, void *arg, struct pt_regs *regs) -+#endif -+{ -+ struct talitos_softc *sc = arg; -+ u_int32_t v, v_hi; -+ -+ /* ack */ -+ v = talitos_read(sc->sc_base_addr + TALITOS_ISR); -+ v_hi = talitos_read(sc->sc_base_addr + TALITOS_ISR_HI); -+ talitos_write(sc->sc_base_addr + TALITOS_ICR, v); -+ talitos_write(sc->sc_base_addr + TALITOS_ICR_HI, v_hi); -+ -+ if (unlikely(v & TALITOS_ISR_ERROR)) { -+ /* Okay, Houston, we've had a problem here. */ -+ printk(KERN_DEBUG "%s: got error interrupt - ISR 0x%08x_%08x\n", -+ device_get_nameunit(sc->sc_cdev), v, v_hi); -+ talitos_errorprocessing(sc); -+ } else -+ if (likely(v & TALITOS_ISR_DONE)) { -+ talitos_doneprocessing(sc); -+ } -+ return IRQ_HANDLED; -+} -+ -+/* -+ * Initialize registers we need to touch only once. -+ */ -+static void -+talitos_init_device(struct talitos_softc *sc) -+{ -+ u_int32_t v; -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ /* init all channels */ -+ for (i = 0; i < sc->sc_num_channels; i++) { -+ v = talitos_read(sc->sc_base_addr + -+ i*TALITOS_CH_OFFSET + TALITOS_CH_CCCR_HI); -+ v |= TALITOS_CH_CCCR_HI_CDWE -+ | TALITOS_CH_CCCR_HI_CDIE; /* invoke interrupt if done */ -+ talitos_write(sc->sc_base_addr + -+ i*TALITOS_CH_OFFSET + TALITOS_CH_CCCR_HI, v); -+ } -+ /* enable all interrupts */ -+ v = talitos_read(sc->sc_base_addr + TALITOS_IMR); -+ v |= TALITOS_IMR_ALL; -+ talitos_write(sc->sc_base_addr + TALITOS_IMR, v); -+ v = talitos_read(sc->sc_base_addr + TALITOS_IMR_HI); -+ v |= TALITOS_IMR_HI_ERRONLY; -+ talitos_write(sc->sc_base_addr + TALITOS_IMR_HI, v); -+ return; -+} -+ -+/* -+ * set the master reset bit on the device. -+ */ -+static void -+talitos_reset_device_master(struct talitos_softc *sc) -+{ -+ u_int32_t v; -+ -+ /* Reset the device by writing 1 to MCR:SWR and waiting 'til cleared */ -+ v = talitos_read(sc->sc_base_addr + TALITOS_MCR); -+ talitos_write(sc->sc_base_addr + TALITOS_MCR, v | TALITOS_MCR_SWR); -+ -+ while (talitos_read(sc->sc_base_addr + TALITOS_MCR) & TALITOS_MCR_SWR) -+ cpu_relax(); -+ -+ return; -+} -+ -+/* -+ * Resets the device. Values in the registers are left as is -+ * from the reset (i.e. initial values are assigned elsewhere). -+ */ -+static void -+talitos_reset_device(struct talitos_softc *sc) -+{ -+ u_int32_t v; -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ /* -+ * Master reset -+ * errata documentation: warning: certain SEC interrupts -+ * are not fully cleared by writing the MCR:SWR bit, -+ * set bit twice to completely reset -+ */ -+ talitos_reset_device_master(sc); /* once */ -+ talitos_reset_device_master(sc); /* and once again */ -+ -+ /* reset all channels */ -+ for (i = 0; i < sc->sc_num_channels; i++) { -+ v = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + -+ TALITOS_CH_CCCR); -+ talitos_write(sc->sc_base_addr + i*TALITOS_CH_OFFSET + -+ TALITOS_CH_CCCR, v | TALITOS_CH_CCCR_RESET); -+ } -+} -+ -+/* Set up the crypto device structure, private data, -+ * and anything else we need before we start */ -+#ifdef CONFIG_PPC_MERGE -+static int talitos_probe(struct of_device *ofdev, const struct of_device_id *match) -+#else -+static int talitos_probe(struct platform_device *pdev) -+#endif -+{ -+ struct talitos_softc *sc = NULL; -+ struct resource *r; -+#ifdef CONFIG_PPC_MERGE -+ struct device *device = &ofdev->dev; -+ struct device_node *np = ofdev->node; -+ const unsigned int *prop; -+ int err; -+ struct resource res; -+#endif -+ static int num_chips = 0; -+ int rc; -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ sc = (struct talitos_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); -+ if (!sc) -+ return -ENOMEM; -+ memset(sc, 0, sizeof(*sc)); -+ -+ softc_device_init(sc, DRV_NAME, num_chips, talitos_methods); -+ -+ sc->sc_irq = -1; -+ sc->sc_cid = -1; -+#ifndef CONFIG_PPC_MERGE -+ sc->sc_dev = pdev; -+#endif -+ sc->sc_num = num_chips++; -+ -+#ifdef CONFIG_PPC_MERGE -+ dev_set_drvdata(device, sc); -+#else -+ platform_set_drvdata(sc->sc_dev, sc); -+#endif -+ -+ /* get the irq line */ -+#ifdef CONFIG_PPC_MERGE -+ err = of_address_to_resource(np, 0, &res); -+ if (err) -+ return -EINVAL; -+ r = &res; -+ -+ sc->sc_irq = irq_of_parse_and_map(np, 0); -+#else -+ /* get a pointer to the register memory */ -+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ -+ sc->sc_irq = platform_get_irq(pdev, 0); -+#endif -+ rc = request_irq(sc->sc_irq, talitos_intr, 0, -+ device_get_nameunit(sc->sc_cdev), sc); -+ if (rc) { -+ printk(KERN_ERR "%s: failed to hook irq %d\n", -+ device_get_nameunit(sc->sc_cdev), sc->sc_irq); -+ sc->sc_irq = -1; -+ goto out; -+ } -+ -+ sc->sc_base_addr = (ocf_iomem_t) ioremap(r->start, (r->end - r->start)); -+ if (!sc->sc_base_addr) { -+ printk(KERN_ERR "%s: failed to ioremap\n", -+ device_get_nameunit(sc->sc_cdev)); -+ goto out; -+ } -+ -+ /* figure out our SEC's properties and capabilities */ -+ sc->sc_chiprev = (u64)talitos_read(sc->sc_base_addr + TALITOS_ID) << 32 -+ | talitos_read(sc->sc_base_addr + TALITOS_ID_HI); -+ DPRINTF("sec id 0x%llx\n", sc->sc_chiprev); -+ -+#ifdef CONFIG_PPC_MERGE -+ /* get SEC properties from device tree, defaulting to SEC 2.0 */ -+ -+ prop = of_get_property(np, "num-channels", NULL); -+ sc->sc_num_channels = prop ? *prop : TALITOS_NCHANNELS_SEC_2_0; -+ -+ prop = of_get_property(np, "channel-fifo-len", NULL); -+ sc->sc_chfifo_len = prop ? *prop : TALITOS_CHFIFOLEN_SEC_2_0; -+ -+ prop = of_get_property(np, "exec-units-mask", NULL); -+ sc->sc_exec_units = prop ? *prop : TALITOS_HAS_EUS_SEC_2_0; -+ -+ prop = of_get_property(np, "descriptor-types-mask", NULL); -+ sc->sc_desc_types = prop ? *prop : TALITOS_HAS_DESCTYPES_SEC_2_0; -+#else -+ /* bulk should go away with openfirmware flat device tree support */ -+ if (sc->sc_chiprev & TALITOS_ID_SEC_2_0) { -+ sc->sc_num_channels = TALITOS_NCHANNELS_SEC_2_0; -+ sc->sc_chfifo_len = TALITOS_CHFIFOLEN_SEC_2_0; -+ sc->sc_exec_units = TALITOS_HAS_EUS_SEC_2_0; -+ sc->sc_desc_types = TALITOS_HAS_DESCTYPES_SEC_2_0; -+ } else { -+ printk(KERN_ERR "%s: failed to id device\n", -+ device_get_nameunit(sc->sc_cdev)); -+ goto out; -+ } -+#endif -+ -+ /* + 1 is for the meta-channel lock used by the channel scheduler */ -+ sc->sc_chnfifolock = (spinlock_t *) kmalloc( -+ (sc->sc_num_channels + 1) * sizeof(spinlock_t), GFP_KERNEL); -+ if (!sc->sc_chnfifolock) -+ goto out; -+ for (i = 0; i < sc->sc_num_channels + 1; i++) { -+ spin_lock_init(&sc->sc_chnfifolock[i]); -+ } -+ -+ sc->sc_chnlastalg = (int *) kmalloc( -+ sc->sc_num_channels * sizeof(int), GFP_KERNEL); -+ if (!sc->sc_chnlastalg) -+ goto out; -+ memset(sc->sc_chnlastalg, 0, sc->sc_num_channels * sizeof(int)); -+ -+ sc->sc_chnfifo = (struct desc_cryptop_pair **) kmalloc( -+ sc->sc_num_channels * sizeof(struct desc_cryptop_pair *), -+ GFP_KERNEL); -+ if (!sc->sc_chnfifo) -+ goto out; -+ for (i = 0; i < sc->sc_num_channels; i++) { -+ sc->sc_chnfifo[i] = (struct desc_cryptop_pair *) kmalloc( -+ sc->sc_chfifo_len * sizeof(struct desc_cryptop_pair), -+ GFP_KERNEL); -+ if (!sc->sc_chnfifo[i]) -+ goto out; -+ memset(sc->sc_chnfifo[i], 0, -+ sc->sc_chfifo_len * sizeof(struct desc_cryptop_pair)); -+ } -+ -+ /* reset and initialize the SEC h/w device */ -+ talitos_reset_device(sc); -+ talitos_init_device(sc); -+ -+ sc->sc_cid = crypto_get_driverid(softc_get_device(sc),CRYPTOCAP_F_HARDWARE); -+ if (sc->sc_cid < 0) { -+ printk(KERN_ERR "%s: could not get crypto driver id\n", -+ device_get_nameunit(sc->sc_cdev)); -+ goto out; -+ } -+ -+ /* register algorithms with the framework */ -+ printk("%s:", device_get_nameunit(sc->sc_cdev)); -+ -+ if (sc->sc_exec_units & TALITOS_HAS_EU_RNG) { -+ printk(" rng"); -+#ifdef CONFIG_OCF_RANDOMHARVEST -+ talitos_rng_init(sc); -+ crypto_rregister(sc->sc_cid, talitos_read_random, sc); -+#endif -+ } -+ if (sc->sc_exec_units & TALITOS_HAS_EU_DEU) { -+ printk(" des/3des"); -+ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); -+ } -+ if (sc->sc_exec_units & TALITOS_HAS_EU_AESU) { -+ printk(" aes"); -+ crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); -+ } -+ if (sc->sc_exec_units & TALITOS_HAS_EU_MDEU) { -+ printk(" md5"); -+ crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0); -+ /* HMAC support only with IPsec for now */ -+ crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); -+ printk(" sha1"); -+ crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0); -+ /* HMAC support only with IPsec for now */ -+ crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); -+ } -+ printk("\n"); -+ return 0; -+ -+out: -+#ifndef CONFIG_PPC_MERGE -+ talitos_remove(pdev); -+#endif -+ return -ENOMEM; -+} -+ -+#ifdef CONFIG_PPC_MERGE -+static int talitos_remove(struct of_device *ofdev) -+#else -+static int talitos_remove(struct platform_device *pdev) -+#endif -+{ -+#ifdef CONFIG_PPC_MERGE -+ struct talitos_softc *sc = dev_get_drvdata(&ofdev->dev); -+#else -+ struct talitos_softc *sc = platform_get_drvdata(pdev); -+#endif -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ if (sc->sc_cid >= 0) -+ crypto_unregister_all(sc->sc_cid); -+ if (sc->sc_chnfifo) { -+ for (i = 0; i < sc->sc_num_channels; i++) -+ if (sc->sc_chnfifo[i]) -+ kfree(sc->sc_chnfifo[i]); -+ kfree(sc->sc_chnfifo); -+ } -+ if (sc->sc_chnlastalg) -+ kfree(sc->sc_chnlastalg); -+ if (sc->sc_chnfifolock) -+ kfree(sc->sc_chnfifolock); -+ if (sc->sc_irq != -1) -+ free_irq(sc->sc_irq, sc); -+ if (sc->sc_base_addr) -+ iounmap((void *) sc->sc_base_addr); -+ kfree(sc); -+ return 0; -+} -+ -+#ifdef CONFIG_PPC_MERGE -+static struct of_device_id talitos_match[] = { -+ { -+ .type = "crypto", -+ .compatible = "talitos", -+ }, -+ {}, -+}; -+ -+MODULE_DEVICE_TABLE(of, talitos_match); -+ -+static struct of_platform_driver talitos_driver = { -+ .name = DRV_NAME, -+ .match_table = talitos_match, -+ .probe = talitos_probe, -+ .remove = talitos_remove, -+}; -+ -+static int __init talitos_init(void) -+{ -+ return of_register_platform_driver(&talitos_driver); -+} -+ -+static void __exit talitos_exit(void) -+{ -+ of_unregister_platform_driver(&talitos_driver); -+} -+#else -+/* Structure for a platform device driver */ -+static struct platform_driver talitos_driver = { -+ .probe = talitos_probe, -+ .remove = talitos_remove, -+ .driver = { -+ .name = "fsl-sec2", -+ } -+}; -+ -+static int __init talitos_init(void) -+{ -+ return platform_driver_register(&talitos_driver); -+} -+ -+static void __exit talitos_exit(void) -+{ -+ platform_driver_unregister(&talitos_driver); -+} -+#endif -+ -+module_init(talitos_init); -+module_exit(talitos_exit); -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_AUTHOR("kim.phillips@freescale.com"); -+MODULE_DESCRIPTION("OCF driver for Freescale SEC (talitos)"); -diff -Nur linux-2.6.36.orig/crypto/ocf/talitos/talitos_dev.h linux-2.6.36/crypto/ocf/talitos/talitos_dev.h ---- linux-2.6.36.orig/crypto/ocf/talitos/talitos_dev.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/talitos/talitos_dev.h 2010-11-09 20:28:13.232495491 +0100 -@@ -0,0 +1,277 @@ -+/* -+ * Freescale SEC (talitos) device dependent data structures -+ * -+ * Copyright (c) 2006 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ */ -+ -+/* device ID register values */ -+#define TALITOS_ID_SEC_2_0 0x40 -+#define TALITOS_ID_SEC_2_1 0x40 /* cross ref with IP block revision reg */ -+ -+/* -+ * following num_channels, channel-fifo-depth, exec-unit-mask, and -+ * descriptor-types-mask are for forward-compatibility with openfirmware -+ * flat device trees -+ */ -+ -+/* -+ * num_channels : the number of channels available in each SEC version. -+ */ -+ -+/* n.b. this driver requires these values be a power of 2 */ -+#define TALITOS_NCHANNELS_SEC_1_0 4 -+#define TALITOS_NCHANNELS_SEC_1_2 1 -+#define TALITOS_NCHANNELS_SEC_2_0 4 -+#define TALITOS_NCHANNELS_SEC_2_01 4 -+#define TALITOS_NCHANNELS_SEC_2_1 4 -+#define TALITOS_NCHANNELS_SEC_2_4 4 -+ -+/* -+ * channel-fifo-depth : The number of descriptor -+ * pointers a channel fetch fifo can hold. -+ */ -+#define TALITOS_CHFIFOLEN_SEC_1_0 1 -+#define TALITOS_CHFIFOLEN_SEC_1_2 1 -+#define TALITOS_CHFIFOLEN_SEC_2_0 24 -+#define TALITOS_CHFIFOLEN_SEC_2_01 24 -+#define TALITOS_CHFIFOLEN_SEC_2_1 24 -+#define TALITOS_CHFIFOLEN_SEC_2_4 24 -+ -+/* -+ * exec-unit-mask : The bitmask representing what Execution Units (EUs) -+ * are available. EU information should be encoded following the SEC's -+ * EU_SEL0 bitfield documentation, i.e. as follows: -+ * -+ * bit 31 = set if SEC permits no-EU selection (should be always set) -+ * bit 30 = set if SEC has the ARC4 EU (AFEU) -+ * bit 29 = set if SEC has the des/3des EU (DEU) -+ * bit 28 = set if SEC has the message digest EU (MDEU) -+ * bit 27 = set if SEC has the random number generator EU (RNG) -+ * bit 26 = set if SEC has the public key EU (PKEU) -+ * bit 25 = set if SEC has the aes EU (AESU) -+ * bit 24 = set if SEC has the Kasumi EU (KEU) -+ * -+ */ -+#define TALITOS_HAS_EU_NONE (1<<0) -+#define TALITOS_HAS_EU_AFEU (1<<1) -+#define TALITOS_HAS_EU_DEU (1<<2) -+#define TALITOS_HAS_EU_MDEU (1<<3) -+#define TALITOS_HAS_EU_RNG (1<<4) -+#define TALITOS_HAS_EU_PKEU (1<<5) -+#define TALITOS_HAS_EU_AESU (1<<6) -+#define TALITOS_HAS_EU_KEU (1<<7) -+ -+/* the corresponding masks for each SEC version */ -+#define TALITOS_HAS_EUS_SEC_1_0 0x7f -+#define TALITOS_HAS_EUS_SEC_1_2 0x4d -+#define TALITOS_HAS_EUS_SEC_2_0 0x7f -+#define TALITOS_HAS_EUS_SEC_2_01 0x7f -+#define TALITOS_HAS_EUS_SEC_2_1 0xff -+#define TALITOS_HAS_EUS_SEC_2_4 0x7f -+ -+/* -+ * descriptor-types-mask : The bitmask representing what descriptors -+ * are available. Descriptor type information should be encoded -+ * following the SEC's Descriptor Header Dword DESC_TYPE field -+ * documentation, i.e. as follows: -+ * -+ * bit 0 = set if SEC supports the aesu_ctr_nonsnoop desc. type -+ * bit 1 = set if SEC supports the ipsec_esp descriptor type -+ * bit 2 = set if SEC supports the common_nonsnoop desc. type -+ * bit 3 = set if SEC supports the 802.11i AES ccmp desc. type -+ * bit 4 = set if SEC supports the hmac_snoop_no_afeu desc. type -+ * bit 5 = set if SEC supports the srtp descriptor type -+ * bit 6 = set if SEC supports the non_hmac_snoop_no_afeu desc.type -+ * bit 7 = set if SEC supports the pkeu_assemble descriptor type -+ * bit 8 = set if SEC supports the aesu_key_expand_output desc.type -+ * bit 9 = set if SEC supports the pkeu_ptmul descriptor type -+ * bit 10 = set if SEC supports the common_nonsnoop_afeu desc. type -+ * bit 11 = set if SEC supports the pkeu_ptadd_dbl descriptor type -+ * -+ * ..and so on and so forth. -+ */ -+#define TALITOS_HAS_DT_AESU_CTR_NONSNOOP (1<<0) -+#define TALITOS_HAS_DT_IPSEC_ESP (1<<1) -+#define TALITOS_HAS_DT_COMMON_NONSNOOP (1<<2) -+ -+/* the corresponding masks for each SEC version */ -+#define TALITOS_HAS_DESCTYPES_SEC_2_0 0x01010ebf -+#define TALITOS_HAS_DESCTYPES_SEC_2_1 0x012b0ebf -+ -+/* -+ * a TALITOS_xxx_HI address points to the low data bits (32-63) of the register -+ */ -+ -+/* global register offset addresses */ -+#define TALITOS_ID 0x1020 -+#define TALITOS_ID_HI 0x1024 -+#define TALITOS_MCR 0x1030 /* master control register */ -+#define TALITOS_MCR_HI 0x1038 /* master control register */ -+#define TALITOS_MCR_SWR 0x1 -+#define TALITOS_IMR 0x1008 /* interrupt mask register */ -+#define TALITOS_IMR_ALL 0x00010fff /* enable all interrupts mask */ -+#define TALITOS_IMR_ERRONLY 0x00010aaa /* enable error interrupts */ -+#define TALITOS_IMR_HI 0x100C /* interrupt mask register */ -+#define TALITOS_IMR_HI_ALL 0x00323333 /* enable all interrupts mask */ -+#define TALITOS_IMR_HI_ERRONLY 0x00222222 /* enable error interrupts */ -+#define TALITOS_ISR 0x1010 /* interrupt status register */ -+#define TALITOS_ISR_ERROR 0x00010faa /* errors mask */ -+#define TALITOS_ISR_DONE 0x00000055 /* channel(s) done mask */ -+#define TALITOS_ISR_HI 0x1014 /* interrupt status register */ -+#define TALITOS_ICR 0x1018 /* interrupt clear register */ -+#define TALITOS_ICR_HI 0x101C /* interrupt clear register */ -+ -+/* channel register address stride */ -+#define TALITOS_CH_OFFSET 0x100 -+ -+/* channel register offset addresses and bits */ -+#define TALITOS_CH_CCCR 0x1108 /* Crypto-Channel Config Register */ -+#define TALITOS_CH_CCCR_RESET 0x1 /* Channel Reset bit */ -+#define TALITOS_CH_CCCR_HI 0x110c /* Crypto-Channel Config Register */ -+#define TALITOS_CH_CCCR_HI_CDWE 0x10 /* Channel done writeback enable bit */ -+#define TALITOS_CH_CCCR_HI_NT 0x4 /* Notification type bit */ -+#define TALITOS_CH_CCCR_HI_CDIE 0x2 /* Channel Done Interrupt Enable bit */ -+#define TALITOS_CH_CCPSR 0x1110 /* Crypto-Channel Pointer Status Reg */ -+#define TALITOS_CH_CCPSR_HI 0x1114 /* Crypto-Channel Pointer Status Reg */ -+#define TALITOS_CH_FF 0x1148 /* Fetch FIFO */ -+#define TALITOS_CH_FF_HI 0x114c /* Fetch FIFO's FETCH_ADRS */ -+#define TALITOS_CH_CDPR 0x1140 /* Crypto-Channel Pointer Status Reg */ -+#define TALITOS_CH_CDPR_HI 0x1144 /* Crypto-Channel Pointer Status Reg */ -+#define TALITOS_CH_DESCBUF 0x1180 /* (thru 11bf) Crypto-Channel -+ * Descriptor Buffer (debug) */ -+ -+/* execution unit register offset addresses and bits */ -+#define TALITOS_DEUSR 0x2028 /* DEU status register */ -+#define TALITOS_DEUSR_HI 0x202c /* DEU status register */ -+#define TALITOS_DEUISR 0x2030 /* DEU interrupt status register */ -+#define TALITOS_DEUISR_HI 0x2034 /* DEU interrupt status register */ -+#define TALITOS_DEUICR 0x2038 /* DEU interrupt control register */ -+#define TALITOS_DEUICR_HI 0x203c /* DEU interrupt control register */ -+#define TALITOS_AESUISR 0x4030 /* AESU interrupt status register */ -+#define TALITOS_AESUISR_HI 0x4034 /* AESU interrupt status register */ -+#define TALITOS_AESUICR 0x4038 /* AESU interrupt control register */ -+#define TALITOS_AESUICR_HI 0x403c /* AESU interrupt control register */ -+#define TALITOS_MDEUISR 0x6030 /* MDEU interrupt status register */ -+#define TALITOS_MDEUISR_HI 0x6034 /* MDEU interrupt status register */ -+#define TALITOS_RNGSR 0xa028 /* RNG status register */ -+#define TALITOS_RNGSR_HI 0xa02c /* RNG status register */ -+#define TALITOS_RNGSR_HI_RD 0x1 /* RNG Reset done */ -+#define TALITOS_RNGSR_HI_OFL 0xff0000/* number of dwords in RNG output FIFO*/ -+#define TALITOS_RNGDSR 0xa010 /* RNG data size register */ -+#define TALITOS_RNGDSR_HI 0xa014 /* RNG data size register */ -+#define TALITOS_RNG_FIFO 0xa800 /* RNG FIFO - pool of random numbers */ -+#define TALITOS_RNGISR 0xa030 /* RNG Interrupt status register */ -+#define TALITOS_RNGISR_HI 0xa034 /* RNG Interrupt status register */ -+#define TALITOS_RNGRCR 0xa018 /* RNG Reset control register */ -+#define TALITOS_RNGRCR_HI 0xa01c /* RNG Reset control register */ -+#define TALITOS_RNGRCR_HI_SR 0x1 /* RNG RNGRCR:Software Reset */ -+ -+/* descriptor pointer entry */ -+struct talitos_desc_ptr { -+ u16 len; /* length */ -+ u8 extent; /* jump (to s/g link table) and extent */ -+ u8 res; /* reserved */ -+ u32 ptr; /* pointer */ -+}; -+ -+/* descriptor */ -+struct talitos_desc { -+ u32 hdr; /* header */ -+ u32 res; /* reserved */ -+ struct talitos_desc_ptr ptr[7]; /* ptr/len pair array */ -+}; -+ -+/* talitos descriptor header (hdr) bits */ -+ -+/* primary execution unit select */ -+#define TALITOS_SEL0_AFEU 0x10000000 -+#define TALITOS_SEL0_DEU 0x20000000 -+#define TALITOS_SEL0_MDEU 0x30000000 -+#define TALITOS_SEL0_RNG 0x40000000 -+#define TALITOS_SEL0_PKEU 0x50000000 -+#define TALITOS_SEL0_AESU 0x60000000 -+ -+/* primary execution unit mode (MODE0) and derivatives */ -+#define TALITOS_MODE0_AESU_CBC 0x00200000 -+#define TALITOS_MODE0_AESU_ENC 0x00100000 -+#define TALITOS_MODE0_DEU_CBC 0x00400000 -+#define TALITOS_MODE0_DEU_3DES 0x00200000 -+#define TALITOS_MODE0_DEU_ENC 0x00100000 -+#define TALITOS_MODE0_MDEU_INIT 0x01000000 /* init starting regs */ -+#define TALITOS_MODE0_MDEU_HMAC 0x00800000 -+#define TALITOS_MODE0_MDEU_PAD 0x00400000 /* PD */ -+#define TALITOS_MODE0_MDEU_MD5 0x00200000 -+#define TALITOS_MODE0_MDEU_SHA256 0x00100000 -+#define TALITOS_MODE0_MDEU_SHA1 0x00000000 /* SHA-160 */ -+#define TALITOS_MODE0_MDEU_MD5_HMAC \ -+ (TALITOS_MODE0_MDEU_MD5 | TALITOS_MODE0_MDEU_HMAC) -+#define TALITOS_MODE0_MDEU_SHA256_HMAC \ -+ (TALITOS_MODE0_MDEU_SHA256 | TALITOS_MODE0_MDEU_HMAC) -+#define TALITOS_MODE0_MDEU_SHA1_HMAC \ -+ (TALITOS_MODE0_MDEU_SHA1 | TALITOS_MODE0_MDEU_HMAC) -+ -+/* secondary execution unit select (SEL1) */ -+/* it's MDEU or nothing */ -+#define TALITOS_SEL1_MDEU 0x00030000 -+ -+/* secondary execution unit mode (MODE1) and derivatives */ -+#define TALITOS_MODE1_MDEU_INIT 0x00001000 /* init starting regs */ -+#define TALITOS_MODE1_MDEU_HMAC 0x00000800 -+#define TALITOS_MODE1_MDEU_PAD 0x00000400 /* PD */ -+#define TALITOS_MODE1_MDEU_MD5 0x00000200 -+#define TALITOS_MODE1_MDEU_SHA256 0x00000100 -+#define TALITOS_MODE1_MDEU_SHA1 0x00000000 /* SHA-160 */ -+#define TALITOS_MODE1_MDEU_MD5_HMAC \ -+ (TALITOS_MODE1_MDEU_MD5 | TALITOS_MODE1_MDEU_HMAC) -+#define TALITOS_MODE1_MDEU_SHA256_HMAC \ -+ (TALITOS_MODE1_MDEU_SHA256 | TALITOS_MODE1_MDEU_HMAC) -+#define TALITOS_MODE1_MDEU_SHA1_HMAC \ -+ (TALITOS_MODE1_MDEU_SHA1 | TALITOS_MODE1_MDEU_HMAC) -+ -+/* direction of overall data flow (DIR) */ -+#define TALITOS_DIR_OUTBOUND 0x00000000 -+#define TALITOS_DIR_INBOUND 0x00000002 -+ -+/* done notification (DN) */ -+#define TALITOS_DONE_NOTIFY 0x00000001 -+ -+/* descriptor types */ -+/* odd numbers here are valid on SEC2 and greater only (e.g. ipsec_esp) */ -+#define TD_TYPE_AESU_CTR_NONSNOOP (0 << 3) -+#define TD_TYPE_IPSEC_ESP (1 << 3) -+#define TD_TYPE_COMMON_NONSNOOP_NO_AFEU (2 << 3) -+#define TD_TYPE_HMAC_SNOOP_NO_AFEU (4 << 3) -+ -+#define TALITOS_HDR_DONE_BITS 0xff000000 -+ -+#define DPRINTF(a...) do { \ -+ if (debug) { \ -+ printk("%s: ", sc ? \ -+ device_get_nameunit(sc->sc_cdev) : "talitos"); \ -+ printk(a); \ -+ } \ -+ } while (0) -diff -Nur linux-2.6.36.orig/crypto/ocf/talitos/talitos_soft.h linux-2.6.36/crypto/ocf/talitos/talitos_soft.h ---- linux-2.6.36.orig/crypto/ocf/talitos/talitos_soft.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/talitos/talitos_soft.h 2010-11-09 20:28:13.272495451 +0100 -@@ -0,0 +1,77 @@ -+/* -+ * Freescale SEC data structures for integration with ocf-linux -+ * -+ * Copyright (c) 2006 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/* -+ * paired descriptor and associated crypto operation -+ */ -+struct desc_cryptop_pair { -+ struct talitos_desc cf_desc; /* descriptor ptr */ -+ struct cryptop *cf_crp; /* cryptop ptr */ -+}; -+ -+/* -+ * Holds data specific to a single talitos device. -+ */ -+struct talitos_softc { -+ softc_device_decl sc_cdev; -+ struct platform_device *sc_dev; /* device backpointer */ -+ ocf_iomem_t sc_base_addr; -+ int sc_irq; -+ int sc_num; /* if we have multiple chips */ -+ int32_t sc_cid; /* crypto tag */ -+ u64 sc_chiprev; /* major/minor chip revision */ -+ int sc_nsessions; -+ struct talitos_session *sc_sessions; -+ int sc_num_channels;/* number of crypto channels */ -+ int sc_chfifo_len; /* channel fetch fifo len */ -+ int sc_exec_units; /* execution units mask */ -+ int sc_desc_types; /* descriptor types mask */ -+ /* -+ * mutual exclusion for intra-channel resources, e.g. fetch fifos -+ * the last entry is a meta-channel lock used by the channel scheduler -+ */ -+ spinlock_t *sc_chnfifolock; -+ /* sc_chnlastalgo contains last algorithm for that channel */ -+ int *sc_chnlastalg; -+ /* sc_chnfifo holds pending descriptor--crypto operation pairs */ -+ struct desc_cryptop_pair **sc_chnfifo; -+}; -+ -+struct talitos_session { -+ u_int32_t ses_used; -+ u_int32_t ses_klen; /* key length in bits */ -+ u_int32_t ses_key[8]; /* DES/3DES/AES key */ -+ u_int32_t ses_hmac[5]; /* hmac inner state */ -+ u_int32_t ses_hmac_len; /* hmac length */ -+ u_int32_t ses_iv[4]; /* DES/3DES/AES iv */ -+ u_int32_t ses_mlen; /* desired hash result len (12=ipsec or 16) */ -+}; -+ -+#define TALITOS_SESSION(sid) ((sid) & 0x0fffffff) -+#define TALITOS_SID(crd, sesn) (((crd) << 28) | ((sesn) & 0x0fffffff)) -diff -Nur linux-2.6.36.orig/crypto/ocf/uio.h linux-2.6.36/crypto/ocf/uio.h ---- linux-2.6.36.orig/crypto/ocf/uio.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/uio.h 2010-11-09 20:28:13.313482727 +0100 -@@ -0,0 +1,54 @@ -+#ifndef _OCF_UIO_H_ -+#define _OCF_UIO_H_ -+ -+#include -+ -+/* -+ * The linux uio.h doesn't have all we need. To be fully api compatible -+ * with the BSD cryptodev, we need to keep this around. Perhaps this can -+ * be moved back into the linux/uio.h -+ * -+ * Linux port done by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * ALTERNATIVELY, provided that this notice is retained in full, this product -+ * may be distributed under the terms of the GNU General Public License (GPL), -+ * in which case the provisions of the GPL apply INSTEAD OF those given above. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ * --------------------------------------------------------------------------- -+ */ -+ -+struct uio { -+ struct iovec *uio_iov; -+ int uio_iovcnt; -+ off_t uio_offset; -+ int uio_resid; -+#if 0 -+ enum uio_seg uio_segflg; -+ enum uio_rw uio_rw; -+ struct thread *uio_td; -+#endif -+}; -+ -+#endif -diff -Nur linux-2.6.36.orig/drivers/char/random.c linux-2.6.36/drivers/char/random.c ---- linux-2.6.36.orig/drivers/char/random.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/drivers/char/random.c 2010-11-09 20:28:13.352495461 +0100 -@@ -129,6 +129,9 @@ - * unsigned int value); - * void add_interrupt_randomness(int irq); - * -+ * void random_input_words(__u32 *buf, size_t wordcount, int ent_count) -+ * int random_input_wait(void); -+ * - * add_input_randomness() uses the input layer interrupt timing, as well as - * the event type information from the hardware. - * -@@ -140,6 +143,13 @@ - * a better measure, since the timing of the disk interrupts are more - * unpredictable. - * -+ * random_input_words() just provides a raw block of entropy to the input -+ * pool, such as from a hardware entropy generator. -+ * -+ * random_input_wait() suspends the caller until such time as the -+ * entropy pool falls below the write threshold, and returns a count of how -+ * much entropy (in bits) is needed to sustain the pool. -+ * - * All of these routines try to estimate how many bits of randomness a - * particular randomness source. They do this by keeping track of the - * first and second order deltas of the event timings. -@@ -259,6 +269,7 @@ - #define SEC_XFER_SIZE 512 - #define EXTRACT_SIZE 10 - -+ - /* - * The minimum number of bits of entropy before we wake up a read on - * /dev/random. Should be enough to do a significant reseed. -@@ -552,6 +563,60 @@ - spin_unlock_irqrestore(&r->lock, flags); - } - -+/* -+ * random_input_words - add bulk entropy to pool -+ * -+ * @buf: buffer to add -+ * @wordcount: number of __u32 words to add -+ * @ent_count: total amount of entropy (in bits) to credit -+ * -+ * this provides bulk input of entropy to the input pool -+ * -+ */ -+void random_input_words(__u32 *buf, size_t wordcount, int ent_count) -+{ -+ mix_pool_bytes(&input_pool, buf, wordcount*4); -+ -+ credit_entropy_bits(&input_pool, ent_count); -+ -+ DEBUG_ENT("crediting %d bits => %d\n", -+ ent_count, input_pool.entropy_count); -+ /* -+ * Wake up waiting processes if we have enough -+ * entropy. -+ */ -+ if (input_pool.entropy_count >= random_read_wakeup_thresh) -+ wake_up_interruptible(&random_read_wait); -+} -+EXPORT_SYMBOL(random_input_words); -+ -+/* -+ * random_input_wait - wait until random needs entropy -+ * -+ * this function sleeps until the /dev/random subsystem actually -+ * needs more entropy, and then return the amount of entropy -+ * that it would be nice to have added to the system. -+ */ -+int random_input_wait(void) -+{ -+ int count; -+ -+ wait_event_interruptible(random_write_wait, -+ input_pool.entropy_count < random_write_wakeup_thresh); -+ -+ count = random_write_wakeup_thresh - input_pool.entropy_count; -+ -+ /* likely we got woken up due to a signal */ -+ if (count <= 0) count = random_read_wakeup_thresh; -+ -+ DEBUG_ENT("requesting %d bits from input_wait()er %d<%d\n", -+ count, -+ input_pool.entropy_count, random_write_wakeup_thresh); -+ -+ return count; -+} -+EXPORT_SYMBOL(random_input_wait); -+ - /********************************************************************* - * - * Entropy input management -diff -Nur linux-2.6.36.orig/fs/fcntl.c linux-2.6.36/fs/fcntl.c ---- linux-2.6.36.orig/fs/fcntl.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/fs/fcntl.c 2010-11-09 20:28:13.392495458 +0100 -@@ -142,6 +142,7 @@ - } - return ret; - } -+EXPORT_SYMBOL(sys_dup); - - #define SETFL_MASK (O_APPEND | O_NONBLOCK | O_NDELAY | O_DIRECT | O_NOATIME) - -diff -Nur linux-2.6.36.orig/include/linux/miscdevice.h linux-2.6.36/include/linux/miscdevice.h ---- linux-2.6.36.orig/include/linux/miscdevice.h 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/include/linux/miscdevice.h 2010-11-09 20:28:13.432495492 +0100 -@@ -18,6 +18,7 @@ - #define APOLLO_MOUSE_MINOR 7 - #define PC110PAD_MINOR 9 - /*#define ADB_MOUSE_MINOR 10 FIXME OBSOLETE */ -+#define CRYPTODEV_MINOR 70 /* /dev/crypto */ - #define WATCHDOG_MINOR 130 /* Watchdog timer */ - #define TEMP_MINOR 131 /* Temperature Sensor */ - #define RTC_MINOR 135 -diff -Nur linux-2.6.36.orig/include/linux/random.h linux-2.6.36/include/linux/random.h ---- linux-2.6.36.orig/include/linux/random.h 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/include/linux/random.h 2010-11-09 20:28:13.597270121 +0100 -@@ -9,6 +9,7 @@ - - #include - #include -+#include /* for __u32 in user space */ - #include - - /* ioctl()'s for the random number generator */ -@@ -34,6 +35,30 @@ - /* Clear the entropy pool and associated counters. (Superuser only.) */ - #define RNDCLEARPOOL _IO( 'R', 0x06 ) - -+#ifdef CONFIG_FIPS_RNG -+ -+/* Size of seed value - equal to AES blocksize */ -+#define AES_BLOCK_SIZE_BYTES 16 -+#define SEED_SIZE_BYTES AES_BLOCK_SIZE_BYTES -+/* Size of AES key */ -+#define KEY_SIZE_BYTES 16 -+ -+/* ioctl() structure used by FIPS 140-2 Tests */ -+struct rand_fips_test { -+ unsigned char key[KEY_SIZE_BYTES]; /* Input */ -+ unsigned char datetime[SEED_SIZE_BYTES]; /* Input */ -+ unsigned char seed[SEED_SIZE_BYTES]; /* Input */ -+ unsigned char result[SEED_SIZE_BYTES]; /* Output */ -+}; -+ -+/* FIPS 140-2 RNG Variable Seed Test. (Superuser only.) */ -+#define RNDFIPSVST _IOWR('R', 0x10, struct rand_fips_test) -+ -+/* FIPS 140-2 RNG Monte Carlo Test. (Superuser only.) */ -+#define RNDFIPSMCT _IOWR('R', 0x11, struct rand_fips_test) -+ -+#endif /* #ifdef CONFIG_FIPS_RNG */ -+ - struct rand_pool_info { - int entropy_count; - int buf_size; -@@ -54,6 +79,10 @@ - unsigned int value); - extern void add_interrupt_randomness(int irq); - -+extern void random_input_words(__u32 *buf, size_t wordcount, int ent_count); -+extern int random_input_wait(void); -+#define HAS_RANDOM_INPUT_WAIT 1 -+ - extern void get_random_bytes(void *buf, int nbytes); - void generate_random_uuid(unsigned char uuid_out[16]); - diff --git a/target/linux/patches/2.6.36/rb532.patch b/target/linux/patches/2.6.36/rb532.patch deleted file mode 100644 index be68c65f0..000000000 --- a/target/linux/patches/2.6.36/rb532.patch +++ /dev/null @@ -1,18 +0,0 @@ -diff -Nur linux-2.6.36.orig/arch/mips/rb532/devices.c linux-2.6.36/arch/mips/rb532/devices.c ---- linux-2.6.36.orig/arch/mips/rb532/devices.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/arch/mips/rb532/devices.c 2010-12-21 20:26:05.000000000 +0100 -@@ -190,8 +190,12 @@ - }, { - .name = "rootfs", - .offset = MTDPART_OFS_NXTBLK, -- .size = MTDPART_SIZ_FULL, -- } -+ .size = 0x8000000 - 0x400000 - 0x400000, -+ }, { -+ .name = "cfgfs", -+ .offset = 0x8000000 - 0x400000, -+ .size = 0x400000, -+ }, - }; - - static struct platform_device rb532_led = { diff --git a/target/linux/patches/2.6.36/startup.patch b/target/linux/patches/2.6.36/startup.patch deleted file mode 100644 index 68e8987b0..000000000 --- a/target/linux/patches/2.6.36/startup.patch +++ /dev/null @@ -1,20 +0,0 @@ -diff -Nur linux-2.6.34.orig/init/main.c linux-2.6.34/init/main.c ---- linux-2.6.34.orig/init/main.c 2010-05-16 23:17:36.000000000 +0200 -+++ linux-2.6.34/init/main.c 2010-05-20 20:13:26.321613615 +0200 -@@ -842,6 +842,7 @@ - printk(KERN_WARNING "Failed to execute %s. Attempting " - "defaults...\n", execute_command); - } -+ run_init_process("/init"); - run_init_process("/sbin/init"); - run_init_process("/etc/init"); - run_init_process("/bin/init"); -@@ -889,6 +890,8 @@ - if (sys_open((const char __user *) "/dev/console", O_RDWR, 0) < 0) - printk(KERN_WARNING "Warning: unable to open an initial console.\n"); - -+ printk(KERN_WARNING "Starting Linux (built with OpenADK).\n"); -+ - (void) sys_dup(0); - (void) sys_dup(0); - /* diff --git a/target/linux/patches/2.6.36/uuid.patch b/target/linux/patches/2.6.36/uuid.patch deleted file mode 100644 index cf2869ed2..000000000 --- a/target/linux/patches/2.6.36/uuid.patch +++ /dev/null @@ -1,261 +0,0 @@ -# DP: Add support for specifying the root device using UUIDs on the -# DP: kernel command line like this without the need for an initrd: -# DP: linux ... root=UUID=ce40d6b2-18eb-4a75-aefe-7ddb0995ce63 -# DP: Note: debugging code is kept in, commented out “//†style. -# DP: -# DP: Written © 2010 by Thorsten Glaser -# DP: Idea from 1999 by David Balazic - ---- linux-2.6.36/block/genhd.c~ Wed Oct 20 22:30:22 2010 -+++ linux-2.6.36/block/genhd.c Sat Nov 20 23:14:03 2010 -@@ -35,7 +35,7 @@ struct kobject *block_depr; - static DEFINE_MUTEX(ext_devt_mutex); - static DEFINE_IDR(ext_devt_idr); - --static struct device_type disk_type; -+struct device_type disk_type; - - /** - * disk_get_part - get partition -@@ -1019,7 +1019,7 @@ static char *block_devnode(struct device *dev, mode_t - return NULL; - } - --static struct device_type disk_type = { -+struct device_type disk_type = { - .name = "disk", - .groups = disk_attr_groups, - .release = disk_release, ---- linux-2.6.36/init/do_mounts.c~ Wed Oct 20 20:29:58 2010 -+++ linux-2.6.36/init/do_mounts.c Sun Nov 21 18:37:36 2010 -@@ -32,6 +32,132 @@ static int __initdata root_wait; - - dev_t ROOT_DEV; - -+#ifdef CONFIG_EXT2_FS -+/* support for root=UUID=ce40d6b2-18eb-4a75-aefe-7ddb0995ce63 bootargs */ -+ -+#include -+ -+__u8 root_dev_uuid[16]; -+int root_dev_type; /* 0 = normal (/dev/hda1, 0301); 1 = UUID; 3 = bad */ -+ -+/* imported from block/genhd.c after removing its static qualifier */ -+extern struct device_type disk_type; -+ -+/* helper function */ -+static __u8 __init fromhex(char c) -+{ -+ if (c >= '0' && c <= '9') -+ return (c - '0'); -+ c &= ~32; -+ if (c >= 'A' && c <= 'F') -+ return (c - 'A' + 10); -+ return (0xFF); -+} -+ -+static void __init parse_uuid(const char *s) -+{ -+ int i; -+ __u8 j, k; -+ -+ if (strlen(s) != 36 || s[8] != '-' || s[13] != '-' || -+ s[18] != '-' || s[23] != '-') -+ goto bad_uuid; -+ for (i = 0; i < 16; i++) { -+ if (*s == '-') -+ ++s; -+ j = fromhex(*s++); -+ k = fromhex(*s++); -+ if (j == 0xFF || k == 0xFF) -+ goto bad_uuid; -+ root_dev_uuid[i] = (j << 4) | k; -+ } -+ return; -+ bad_uuid: -+ /* we cannot panic here, defer */ -+ root_dev_type = 3; -+} -+ -+/* from drivers/md/md.c */ -+static void __init initcode_bi_complete(struct bio *bio, int error) -+{ -+ complete((struct completion*)bio->bi_private); -+} -+ -+static int __init initcode_sync_page_read(struct block_device *bdev, -+ sector_t sector, int size, struct page *page) -+{ -+ struct bio *bio = bio_alloc(GFP_NOIO, 1); -+ struct completion event; -+ int ret, rw = READ; -+ -+ rw |= REQ_SYNC | REQ_UNPLUG; -+ -+ bio->bi_bdev = bdev; -+ bio->bi_sector = sector; -+ bio_add_page(bio, page, size, 0); -+ init_completion(&event); -+ bio->bi_private = &event; -+ bio->bi_end_io = initcode_bi_complete; -+ submit_bio(rw, bio); -+ wait_for_completion(&event); -+ -+ ret = test_bit(BIO_UPTODATE, &bio->bi_flags); -+ bio_put(bio); -+ /* 0 = failure */ -+ return ret; -+} -+ -+/* most of this taken from fs/ext2/super.c */ -+static int __init check_dev(struct gendisk *thedisk, dev_t devt, -+ int blocksize, struct page *page) -+{ -+ struct ext2_super_block * es; -+ struct block_device *bdev; -+ unsigned long sb_block = 1; -+ unsigned long logic_sb_block; -+ unsigned long offset = 0; -+ int rv = /* not found */ 0; -+ char bff[22]; -+ -+ bdev = bdget(devt); -+ if (blkdev_get(bdev, FMODE_READ)) { -+ printk(KERN_ERR "VFS: opening block device %s failed!\n", -+ format_dev_t(bff, devt)); -+ return (0); -+ } -+ -+ if (blocksize != BLOCK_SIZE) { -+ logic_sb_block = (sb_block*BLOCK_SIZE) / blocksize; -+ offset = (sb_block*BLOCK_SIZE) % blocksize; -+ } else { -+ logic_sb_block = sb_block; -+ } -+ -+// printk(KERN_ERR "D: attempting to read %d @%lu from " -+// "bdev %p devt %08X %s\n", blocksize, logic_sb_block, -+// bdev, devt, format_dev_t(bff, devt)); -+ if (!initcode_sync_page_read(bdev, logic_sb_block, blocksize, page)) { -+// printk(KERN_ERR "D: failed!\n"); -+ goto out; -+ } -+ es = (struct ext2_super_block *)(((char *)page_address(page)) + offset); -+ if (le16_to_cpu(es->s_magic) == EXT2_SUPER_MAGIC) { -+// printk(KERN_ERR "D: has uuid " -+// "%02X%02X%02X%02X-%02X%02X-%02X%02X-%02X%02X-%02X%02X%02X%02X%02X%02X\n", -+// es->s_uuid[0], es->s_uuid[1], es->s_uuid[2], es->s_uuid[3], -+// es->s_uuid[4], es->s_uuid[5], es->s_uuid[6], es->s_uuid[7], -+// es->s_uuid[8], es->s_uuid[9], es->s_uuid[10], es->s_uuid[11], -+// es->s_uuid[12], es->s_uuid[13], es->s_uuid[14], es->s_uuid[15]); -+ if (!memcmp(es->s_uuid, root_dev_uuid, 16)) -+ rv = /* found */ 1; -+ } -+// else printk(KERN_ERR "D: bad ext2fs magic\n"); -+ out: -+ blkdev_put(bdev, FMODE_READ); -+ return (rv); -+} -+#endif /* CONFIG_EXT2_FS for UUID support */ -+ - static int __init load_ramdisk(char *str) - { - rd_doload = simple_strtol(str,NULL,0) & 3; -@@ -148,6 +274,13 @@ done: - static int __init root_dev_setup(char *line) - { - strlcpy(saved_root_name, line, sizeof(saved_root_name)); -+#ifdef CONFIG_EXT2_FS -+ root_dev_type = 0; -+ if (!strncmp(line, "UUID=", 5)) { -+ root_dev_type = 1; -+ parse_uuid(line + 5); -+ } -+#endif /* CONFIG_EXT2_FS for UUID support */ - return 1; - } - -@@ -333,6 +466,83 @@ void __init change_floppy(char *fmt, ... - - void __init mount_root(void) - { -+#ifdef CONFIG_EXT2_FS -+ /* UUID support */ -+// printk_all_partitions(); -+ if (root_dev_type == 1) { -+ int blocksize; -+ -+ /* from block/genhd.c printk_all_partitions */ -+ struct class_dev_iter iter; -+ struct device *dev; -+ -+ /* from drivers/md/md.c */ -+ struct page *sb_page; -+ -+ if (!(sb_page = alloc_page(GFP_KERNEL))) { -+ printk(KERN_ERR "VFS: no memory for bio page\n"); -+ goto nomemforbio; -+ } -+ -+// printk(KERN_ERR "D: root is: " -+// "%02X%02X%02X%02X-%02X%02X-%02X%02X-%02X%02X-%02X%02X%02X%02X%02X%02X\n", -+// root_dev_uuid[0], root_dev_uuid[1], root_dev_uuid[2], root_dev_uuid[3], -+// root_dev_uuid[4], root_dev_uuid[5], root_dev_uuid[6], root_dev_uuid[7], -+// root_dev_uuid[8], root_dev_uuid[9], root_dev_uuid[10], root_dev_uuid[11], -+// root_dev_uuid[12], root_dev_uuid[13], root_dev_uuid[14], root_dev_uuid[15]); -+ /* from block/genhd.c printk_all_partitions */ -+// printk(KERN_ERR "D: begin iter\n"); -+ class_dev_iter_init(&iter, &block_class, NULL, &disk_type); -+ while (root_dev_type && (dev = class_dev_iter_next(&iter))) { -+// char bff[22]; -+ struct gendisk *disk = dev_to_disk(dev); -+ struct disk_part_iter piter; -+ struct hd_struct *part; -+ if (get_capacity(disk) == 0 || -+ (disk->flags & GENHD_FL_SUPPRESS_PARTITION_INFO)) { -+// printk(KERN_ERR "D: ignoring\n"); -+ continue; -+ } -+ blocksize = queue_logical_block_size(disk->queue); -+// printk(KERN_ERR "D: gendisk, blocksize %d " -+// "name '%s' devt %08X %s #part %d\n", blocksize, -+// disk->disk_name, dev->devt, -+// format_dev_t(bff, dev->devt), -+// disk_max_parts(disk)); -+ disk_part_iter_init(&piter, disk, DISK_PITER_INCL_PART0); -+ while (root_dev_type && (part = disk_part_iter_next(&piter))) { -+ /* avoid empty or too small partitions */ -+// printk(KERN_ERR "D: part #%d start %llu " -+// "nr %llu\n", part->partno, -+// (__u64)part->start_sect, -+// (__u64)part->nr_sects); -+ if (part->nr_sects < 8) -+ continue; -+ if (check_dev(disk, MKDEV(MAJOR(dev->devt), -+ MINOR(dev->devt) + part->partno), -+ blocksize, sb_page)) { -+ ROOT_DEV = part_devt(part); -+// printk(KERN_ERR "D: got match!\n"); -+ // comment out below for debugging -+ root_dev_type = 0; -+ } -+ } -+ disk_part_iter_exit(&piter); -+ } -+// printk(KERN_ERR "D: end iter\n"); -+ class_dev_iter_exit(&iter); -+ put_page(sb_page); -+ } -+ nomemforbio: -+ if (root_dev_type == 1) -+ printk(KERN_ERR "VFS: Unable to find root by UUID %s.\n", -+ saved_root_name + 5); -+ else if (root_dev_type == 3) -+ /* execute deferred panic from parse_uuid */ -+ panic("Badly formatted UUID %s was supplied as kernel " -+ "parameter root", saved_root_name + 5); -+#endif /* CONFIG_EXT2_FS for UUID support */ -+ - #ifdef CONFIG_ROOT_NFS - if (MAJOR(ROOT_DEV) == UNNAMED_MAJOR) { - if (mount_nfs_root()) diff --git a/target/linux/patches/2.6.36/yaffs2.patch b/target/linux/patches/2.6.36/yaffs2.patch deleted file mode 100644 index 4a52d3f10..000000000 --- a/target/linux/patches/2.6.36/yaffs2.patch +++ /dev/null @@ -1,16912 +0,0 @@ -diff -Nur linux-2.6.36.orig/fs/Kconfig linux-2.6.36/fs/Kconfig ---- linux-2.6.36.orig/fs/Kconfig 2011-01-10 19:28:45.000000000 +0100 -+++ linux-2.6.36/fs/Kconfig 2011-01-10 19:29:29.000000000 +0100 -@@ -174,6 +174,7 @@ - source "fs/befs/Kconfig" - source "fs/bfs/Kconfig" - source "fs/efs/Kconfig" -+source "fs/yaffs2/Kconfig" - source "fs/jffs2/Kconfig" - # UBIFS File system configuration - source "fs/ubifs/Kconfig" -diff -Nur linux-2.6.36.orig/fs/Makefile linux-2.6.36/fs/Makefile ---- linux-2.6.36.orig/fs/Makefile 2011-01-10 19:28:45.000000000 +0100 -+++ linux-2.6.36/fs/Makefile 2011-01-10 19:30:04.000000000 +0100 -@@ -124,6 +124,7 @@ - obj-$(CONFIG_OCFS2_FS) += ocfs2/ - obj-$(CONFIG_BTRFS_FS) += btrfs/ - obj-$(CONFIG_GFS2_FS) += gfs2/ -+obj-$(CONFIG_YAFFS_FS) += yaffs2/ - obj-$(CONFIG_EXOFS_FS) += exofs/ - obj-$(CONFIG_CEPH_FS) += ceph/ - obj-$(CONFIG_AUFS_FS) += aufs/ -diff -Nur linux-2.6.36.orig/fs/yaffs2/Kconfig linux-2.6.36/fs/yaffs2/Kconfig ---- linux-2.6.36.orig/fs/yaffs2/Kconfig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/Kconfig 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,161 @@ -+# -+# YAFFS file system configurations -+# -+ -+config YAFFS_FS -+ tristate "YAFFS2 file system support" -+ default n -+ depends on MTD_BLOCK -+ select YAFFS_YAFFS1 -+ select YAFFS_YAFFS2 -+ help -+ YAFFS2, or Yet Another Flash Filing System, is a filing system -+ optimised for NAND Flash chips. -+ -+ To compile the YAFFS2 file system support as a module, choose M -+ here: the module will be called yaffs2. -+ -+ If unsure, say N. -+ -+ Further information on YAFFS2 is available at -+ . -+ -+config YAFFS_YAFFS1 -+ bool "512 byte / page devices" -+ depends on YAFFS_FS -+ default y -+ help -+ Enable YAFFS1 support -- yaffs for 512 byte / page devices -+ -+ Not needed for 2K-page devices. -+ -+ If unsure, say Y. -+ -+config YAFFS_9BYTE_TAGS -+ bool "Use older-style on-NAND data format with pageStatus byte" -+ depends on YAFFS_YAFFS1 -+ default n -+ help -+ -+ Older-style on-NAND data format has a "pageStatus" byte to record -+ chunk/page state. This byte is zero when the page is discarded. -+ Choose this option if you have existing on-NAND data using this -+ format that you need to continue to support. New data written -+ also uses the older-style format. Note: Use of this option -+ generally requires that MTD's oob layout be adjusted to use the -+ older-style format. See notes on tags formats and MTD versions -+ in yaffs_mtdif1.c. -+ -+ If unsure, say N. -+ -+config YAFFS_DOES_ECC -+ bool "Lets Yaffs do its own ECC" -+ depends on YAFFS_FS && YAFFS_YAFFS1 && !YAFFS_9BYTE_TAGS -+ default n -+ help -+ This enables Yaffs to use its own ECC functions instead of using -+ the ones from the generic MTD-NAND driver. -+ -+ If unsure, say N. -+ -+config YAFFS_ECC_WRONG_ORDER -+ bool "Use the same ecc byte order as Steven Hill's nand_ecc.c" -+ depends on YAFFS_FS && YAFFS_DOES_ECC && !YAFFS_9BYTE_TAGS -+ default n -+ help -+ This makes yaffs_ecc.c use the same ecc byte order as Steven -+ Hill's nand_ecc.c. If not set, then you get the same ecc byte -+ order as SmartMedia. -+ -+ If unsure, say N. -+ -+config YAFFS_YAFFS2 -+ bool "2048 byte (or larger) / page devices" -+ depends on YAFFS_FS -+ default y -+ help -+ Enable YAFFS2 support -- yaffs for >= 2K bytes per page devices -+ -+ If unsure, say Y. -+ -+config YAFFS_AUTO_YAFFS2 -+ bool "Autoselect yaffs2 format" -+ depends on YAFFS_YAFFS2 -+ default y -+ help -+ Without this, you need to explicitely use yaffs2 as the file -+ system type. With this, you can say "yaffs" and yaffs or yaffs2 -+ will be used depending on the device page size (yaffs on -+ 512-byte page devices, yaffs2 on 2K page devices). -+ -+ If unsure, say Y. -+ -+config YAFFS_DISABLE_TAGS_ECC -+ bool "Disable YAFFS from doing ECC on tags by default" -+ depends on YAFFS_FS && YAFFS_YAFFS2 -+ default n -+ help -+ This defaults Yaffs to using its own ECC calculations on tags instead of -+ just relying on the MTD. -+ This behavior can also be overridden with tags_ecc_on and -+ tags_ecc_off mount options. -+ -+ If unsure, say N. -+ -+config YAFFS_ALWAYS_CHECK_CHUNK_ERASED -+ bool "Force chunk erase check" -+ depends on YAFFS_FS -+ default n -+ help -+ Normally YAFFS only checks chunks before writing until an erased -+ chunk is found. This helps to detect any partially written -+ chunks that might have happened due to power loss. -+ -+ Enabling this forces on the test that chunks are erased in flash -+ before writing to them. This takes more time but is potentially -+ a bit more secure. -+ -+ Suggest setting Y during development and ironing out driver -+ issues etc. Suggest setting to N if you want faster writing. -+ -+ If unsure, say Y. -+ -+config YAFFS_EMPTY_LOST_AND_FOUND -+ bool "Empty lost and found on boot" -+ depends on YAFFS_FS -+ default n -+ help -+ If this is enabled then the contents of lost and found is -+ automatically dumped at mount. -+ -+ If unsure, say N. -+ -+config YAFFS_DISABLE_BLOCK_REFRESHING -+ bool "Disable yaffs2 block refreshing" -+ depends on YAFFS_FS -+ default n -+ help -+ If this is set, then block refreshing is disabled. -+ Block refreshing infrequently refreshes the oldest block in -+ a yaffs2 file system. This mechanism helps to refresh flash to -+ mitigate against data loss. This is particularly useful for MLC. -+ -+ If unsure, say N. -+ -+config YAFFS_DISABLE_BACKGROUND -+ bool "Disable yaffs2 background processing" -+ depends on YAFFS_FS -+ default n -+ help -+ If this is set, then background processing is disabled. -+ Background processing makes many foreground activities faster. -+ -+ If unsure, say N. -+ -+config YAFFS_XATTR -+ bool "Enable yaffs2 xattr support" -+ depends on YAFFS_FS -+ default y -+ help -+ If this is set then yaffs2 will provide xattr support. -+ If unsure, say Y. -diff -Nur linux-2.6.36.orig/fs/yaffs2/Makefile linux-2.6.36/fs/yaffs2/Makefile ---- linux-2.6.36.orig/fs/yaffs2/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/Makefile 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,17 @@ -+# -+# Makefile for the linux YAFFS filesystem routines. -+# -+ -+obj-$(CONFIG_YAFFS_FS) += yaffs.o -+ -+yaffs-y := yaffs_ecc.o yaffs_vfs.o yaffs_guts.o yaffs_checkptrw.o -+yaffs-y += yaffs_packedtags1.o yaffs_packedtags2.o yaffs_nand.o -+yaffs-y += yaffs_tagscompat.o yaffs_tagsvalidity.o -+yaffs-y += yaffs_mtdif.o yaffs_mtdif1.o yaffs_mtdif2.o -+yaffs-y += yaffs_nameval.o yaffs_attribs.o -+yaffs-y += yaffs_allocator.o -+yaffs-y += yaffs_yaffs1.o -+yaffs-y += yaffs_yaffs2.o -+yaffs-y += yaffs_bitmap.o -+yaffs-y += yaffs_verify.o -+ -diff -Nur linux-2.6.36.orig/fs/yaffs2/moduleconfig.h linux-2.6.36/fs/yaffs2/moduleconfig.h ---- linux-2.6.36.orig/fs/yaffs2/moduleconfig.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/moduleconfig.h 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,81 @@ -+/* -+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Martin Fouts -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU Lesser General Public License version 2.1 as -+ * published by the Free Software Foundation. -+ * -+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. -+ */ -+ -+#ifndef __YAFFS_CONFIG_H__ -+#define __YAFFS_CONFIG_H__ -+ -+#ifdef YAFFS_OUT_OF_TREE -+ -+/* DO NOT UNSET THESE THREE. YAFFS2 will not compile if you do. */ -+#define CONFIG_YAFFS_FS -+#define CONFIG_YAFFS_YAFFS1 -+#define CONFIG_YAFFS_YAFFS2 -+ -+/* These options are independent of each other. Select those that matter. */ -+ -+/* Default: Not selected */ -+/* Meaning: Yaffs does its own ECC, rather than using MTD ECC */ -+/* #define CONFIG_YAFFS_DOES_ECC */ -+ -+/* Default: Selected */ -+/* Meaning: Yaffs does its own ECC on tags for packed tags rather than use mtd */ -+#define CONFIG_YAFFS_DOES_TAGS_ECC -+ -+/* Default: Not selected */ -+/* Meaning: ECC byte order is 'wrong'. Only meaningful if */ -+/* CONFIG_YAFFS_DOES_ECC is set */ -+/* #define CONFIG_YAFFS_ECC_WRONG_ORDER */ -+ -+/* Default: Not selected */ -+/* Meaning: Always test whether chunks are erased before writing to them. -+ Use during mtd debugging and init. */ -+/* #define CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED */ -+ -+/* Default: Not Selected */ -+/* Meaning: At mount automatically empty all files from lost and found. */ -+/* This is done to fix an old problem where rmdir was not checking for an */ -+/* empty directory. This can also be achieved with a mount option. */ -+#define CONFIG_YAFFS_EMPTY_LOST_AND_FOUND -+ -+/* Default: Unselected */ -+/* Meaning: Select to disable block refreshing. */ -+/* Block Refreshing periodically rewrites the oldest block. */ -+/* #define CONFIG_DISABLE_BLOCK_REFRESHING */ -+ -+/* Default: Unselected */ -+/* Meaning: Select to disable background processing */ -+/* #define CONFIG_DISABLE_BACKGROUND */ -+ -+/* Default: Selected */ -+/* Meaning: Enable XATTR support */ -+#define CONFIG_YAFFS_XATTR -+ -+/* -+Older-style on-NAND data format has a "page_status" byte to record -+chunk/page state. This byte is zeroed when the page is discarded. -+Choose this option if you have existing on-NAND data in this format -+that you need to continue to support. New data written also uses the -+older-style format. -+Note: Use of this option generally requires that MTD's oob layout be -+adjusted to use the older-style format. See notes on tags formats and -+MTD versions in yaffs_mtdif1.c. -+*/ -+/* Default: Not selected */ -+/* Meaning: Use older-style on-NAND data format with page_status byte */ -+/* #define CONFIG_YAFFS_9BYTE_TAGS */ -+ -+#endif /* YAFFS_OUT_OF_TREE */ -+ -+#endif /* __YAFFS_CONFIG_H__ */ -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_allocator.c linux-2.6.36/fs/yaffs2/yaffs_allocator.c ---- linux-2.6.36.orig/fs/yaffs2/yaffs_allocator.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_allocator.c 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,397 @@ -+/* -+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include "yaffs_allocator.h" -+#include "yaffs_guts.h" -+#include "yaffs_trace.h" -+#include "yportenv.h" -+ -+#ifdef CONFIG_YAFFS_YMALLOC_ALLOCATOR -+ -+void yaffs_deinit_raw_tnodes_and_objs(struct yaffs_dev *dev) -+{ -+ dev = dev; -+} -+ -+void yaffs_init_raw_tnodes_and_objs(struct yaffs_dev *dev) -+{ -+ dev = dev; -+} -+ -+struct yaffs_tnode *yaffs_alloc_raw_tnode(struct yaffs_dev *dev) -+{ -+ return (struct yaffs_tnode *)YMALLOC(dev->tnode_size); -+} -+ -+void yaffs_free_raw_tnode(struct yaffs_dev *dev, struct yaffs_tnode *tn) -+{ -+ dev = dev; -+ YFREE(tn); -+} -+ -+void yaffs_init_raw_objs(struct yaffs_dev *dev) -+{ -+ dev = dev; -+} -+ -+void yaffs_deinit_raw_objs(struct yaffs_dev *dev) -+{ -+ dev = dev; -+} -+ -+struct yaffs_obj *yaffs_alloc_raw_obj(struct yaffs_dev *dev) -+{ -+ dev = dev; -+ return (struct yaffs_obj *)YMALLOC(sizeof(struct yaffs_obj)); -+} -+ -+void yaffs_free_raw_obj(struct yaffs_dev *dev, struct yaffs_obj *obj) -+{ -+ -+ dev = dev; -+ YFREE(obj); -+} -+ -+#else -+ -+struct yaffs_tnode_list { -+ struct yaffs_tnode_list *next; -+ struct yaffs_tnode *tnodes; -+}; -+ -+struct yaffs_obj_list { -+ struct yaffs_obj_list *next; -+ struct yaffs_obj *objects; -+}; -+ -+struct yaffs_allocator { -+ int n_tnodes_created; -+ struct yaffs_tnode *free_tnodes; -+ int n_free_tnodes; -+ struct yaffs_tnode_list *alloc_tnode_list; -+ -+ int n_obj_created; -+ struct yaffs_obj *free_objs; -+ int n_free_objects; -+ -+ struct yaffs_obj_list *allocated_obj_list; -+}; -+ -+static void yaffs_deinit_raw_tnodes(struct yaffs_dev *dev) -+{ -+ -+ struct yaffs_allocator *allocator = -+ (struct yaffs_allocator *)dev->allocator; -+ -+ struct yaffs_tnode_list *tmp; -+ -+ if (!allocator) { -+ YBUG(); -+ return; -+ } -+ -+ while (allocator->alloc_tnode_list) { -+ tmp = allocator->alloc_tnode_list->next; -+ -+ YFREE(allocator->alloc_tnode_list->tnodes); -+ YFREE(allocator->alloc_tnode_list); -+ allocator->alloc_tnode_list = tmp; -+ -+ } -+ -+ allocator->free_tnodes = NULL; -+ allocator->n_free_tnodes = 0; -+ allocator->n_tnodes_created = 0; -+} -+ -+static void yaffs_init_raw_tnodes(struct yaffs_dev *dev) -+{ -+ struct yaffs_allocator *allocator = dev->allocator; -+ -+ if (allocator) { -+ allocator->alloc_tnode_list = NULL; -+ allocator->free_tnodes = NULL; -+ allocator->n_free_tnodes = 0; -+ allocator->n_tnodes_created = 0; -+ } else { -+ YBUG(); -+ } -+} -+ -+static int yaffs_create_tnodes(struct yaffs_dev *dev, int n_tnodes) -+{ -+ struct yaffs_allocator *allocator = -+ (struct yaffs_allocator *)dev->allocator; -+ int i; -+ struct yaffs_tnode *new_tnodes; -+ u8 *mem; -+ struct yaffs_tnode *curr; -+ struct yaffs_tnode *next; -+ struct yaffs_tnode_list *tnl; -+ -+ if (!allocator) { -+ YBUG(); -+ return YAFFS_FAIL; -+ } -+ -+ if (n_tnodes < 1) -+ return YAFFS_OK; -+ -+ /* make these things */ -+ -+ new_tnodes = YMALLOC(n_tnodes * dev->tnode_size); -+ mem = (u8 *) new_tnodes; -+ -+ if (!new_tnodes) { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR("yaffs: Could not allocate Tnodes" TENDSTR))); -+ return YAFFS_FAIL; -+ } -+ -+ /* New hookup for wide tnodes */ -+ for (i = 0; i < n_tnodes - 1; i++) { -+ curr = (struct yaffs_tnode *)&mem[i * dev->tnode_size]; -+ next = (struct yaffs_tnode *)&mem[(i + 1) * dev->tnode_size]; -+ curr->internal[0] = next; -+ } -+ -+ curr = (struct yaffs_tnode *)&mem[(n_tnodes - 1) * dev->tnode_size]; -+ curr->internal[0] = allocator->free_tnodes; -+ allocator->free_tnodes = (struct yaffs_tnode *)mem; -+ -+ allocator->n_free_tnodes += n_tnodes; -+ allocator->n_tnodes_created += n_tnodes; -+ -+ /* Now add this bunch of tnodes to a list for freeing up. -+ * NB If we can't add this to the management list it isn't fatal -+ * but it just means we can't free this bunch of tnodes later. -+ */ -+ -+ tnl = YMALLOC(sizeof(struct yaffs_tnode_list)); -+ if (!tnl) { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR -+ ("yaffs: Could not add tnodes to management list" TENDSTR))); -+ return YAFFS_FAIL; -+ } else { -+ tnl->tnodes = new_tnodes; -+ tnl->next = allocator->alloc_tnode_list; -+ allocator->alloc_tnode_list = tnl; -+ } -+ -+ T(YAFFS_TRACE_ALLOCATE, (TSTR("yaffs: Tnodes added" TENDSTR))); -+ -+ return YAFFS_OK; -+} -+ -+struct yaffs_tnode *yaffs_alloc_raw_tnode(struct yaffs_dev *dev) -+{ -+ struct yaffs_allocator *allocator = -+ (struct yaffs_allocator *)dev->allocator; -+ struct yaffs_tnode *tn = NULL; -+ -+ if (!allocator) { -+ YBUG(); -+ return NULL; -+ } -+ -+ /* If there are none left make more */ -+ if (!allocator->free_tnodes) -+ yaffs_create_tnodes(dev, YAFFS_ALLOCATION_NTNODES); -+ -+ if (allocator->free_tnodes) { -+ tn = allocator->free_tnodes; -+ allocator->free_tnodes = allocator->free_tnodes->internal[0]; -+ allocator->n_free_tnodes--; -+ } -+ -+ return tn; -+} -+ -+/* FreeTnode frees up a tnode and puts it back on the free list */ -+void yaffs_free_raw_tnode(struct yaffs_dev *dev, struct yaffs_tnode *tn) -+{ -+ struct yaffs_allocator *allocator = dev->allocator; -+ -+ if (!allocator) { -+ YBUG(); -+ return; -+ } -+ -+ if (tn) { -+ tn->internal[0] = allocator->free_tnodes; -+ allocator->free_tnodes = tn; -+ allocator->n_free_tnodes++; -+ } -+ dev->checkpoint_blocks_required = 0; /* force recalculation */ -+} -+ -+static void yaffs_init_raw_objs(struct yaffs_dev *dev) -+{ -+ struct yaffs_allocator *allocator = dev->allocator; -+ -+ if (allocator) { -+ allocator->allocated_obj_list = NULL; -+ allocator->free_objs = NULL; -+ allocator->n_free_objects = 0; -+ } else { -+ YBUG(); -+ } -+} -+ -+static void yaffs_deinit_raw_objs(struct yaffs_dev *dev) -+{ -+ struct yaffs_allocator *allocator = dev->allocator; -+ struct yaffs_obj_list *tmp; -+ -+ if (!allocator) { -+ YBUG(); -+ return; -+ } -+ -+ while (allocator->allocated_obj_list) { -+ tmp = allocator->allocated_obj_list->next; -+ YFREE(allocator->allocated_obj_list->objects); -+ YFREE(allocator->allocated_obj_list); -+ -+ allocator->allocated_obj_list = tmp; -+ } -+ -+ allocator->free_objs = NULL; -+ allocator->n_free_objects = 0; -+ allocator->n_obj_created = 0; -+} -+ -+static int yaffs_create_free_objs(struct yaffs_dev *dev, int n_obj) -+{ -+ struct yaffs_allocator *allocator = dev->allocator; -+ -+ int i; -+ struct yaffs_obj *new_objs; -+ struct yaffs_obj_list *list; -+ -+ if (!allocator) { -+ YBUG(); -+ return YAFFS_FAIL; -+ } -+ -+ if (n_obj < 1) -+ return YAFFS_OK; -+ -+ /* make these things */ -+ new_objs = YMALLOC(n_obj * sizeof(struct yaffs_obj)); -+ list = YMALLOC(sizeof(struct yaffs_obj_list)); -+ -+ if (!new_objs || !list) { -+ if (new_objs) { -+ YFREE(new_objs); -+ new_objs = NULL; -+ } -+ if (list) { -+ YFREE(list); -+ list = NULL; -+ } -+ T(YAFFS_TRACE_ALLOCATE, -+ (TSTR("yaffs: Could not allocate more objects" TENDSTR))); -+ return YAFFS_FAIL; -+ } -+ -+ /* Hook them into the free list */ -+ for (i = 0; i < n_obj - 1; i++) { -+ new_objs[i].siblings.next = -+ (struct list_head *)(&new_objs[i + 1]); -+ } -+ -+ new_objs[n_obj - 1].siblings.next = (void *)allocator->free_objs; -+ allocator->free_objs = new_objs; -+ allocator->n_free_objects += n_obj; -+ allocator->n_obj_created += n_obj; -+ -+ /* Now add this bunch of Objects to a list for freeing up. */ -+ -+ list->objects = new_objs; -+ list->next = allocator->allocated_obj_list; -+ allocator->allocated_obj_list = list; -+ -+ return YAFFS_OK; -+} -+ -+struct yaffs_obj *yaffs_alloc_raw_obj(struct yaffs_dev *dev) -+{ -+ struct yaffs_obj *obj = NULL; -+ struct yaffs_allocator *allocator = dev->allocator; -+ -+ if (!allocator) { -+ YBUG(); -+ return obj; -+ } -+ -+ /* If there are none left make more */ -+ if (!allocator->free_objs) -+ yaffs_create_free_objs(dev, YAFFS_ALLOCATION_NOBJECTS); -+ -+ if (allocator->free_objs) { -+ obj = allocator->free_objs; -+ allocator->free_objs = -+ (struct yaffs_obj *)(allocator->free_objs->siblings.next); -+ allocator->n_free_objects--; -+ } -+ -+ return obj; -+} -+ -+void yaffs_free_raw_obj(struct yaffs_dev *dev, struct yaffs_obj *obj) -+{ -+ -+ struct yaffs_allocator *allocator = dev->allocator; -+ -+ if (!allocator) -+ YBUG(); -+ else { -+ /* Link into the free list. */ -+ obj->siblings.next = (struct list_head *)(allocator->free_objs); -+ allocator->free_objs = obj; -+ allocator->n_free_objects++; -+ } -+} -+ -+void yaffs_deinit_raw_tnodes_and_objs(struct yaffs_dev *dev) -+{ -+ if (dev->allocator) { -+ yaffs_deinit_raw_tnodes(dev); -+ yaffs_deinit_raw_objs(dev); -+ -+ YFREE(dev->allocator); -+ dev->allocator = NULL; -+ } else { -+ YBUG(); -+ } -+} -+ -+void yaffs_init_raw_tnodes_and_objs(struct yaffs_dev *dev) -+{ -+ struct yaffs_allocator *allocator; -+ -+ if (!dev->allocator) { -+ allocator = YMALLOC(sizeof(struct yaffs_allocator)); -+ if (allocator) { -+ dev->allocator = allocator; -+ yaffs_init_raw_tnodes(dev); -+ yaffs_init_raw_objs(dev); -+ } -+ } else { -+ YBUG(); -+ } -+} -+ -+#endif -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_allocator.h linux-2.6.36/fs/yaffs2/yaffs_allocator.h ---- linux-2.6.36.orig/fs/yaffs2/yaffs_allocator.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_allocator.h 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,30 @@ -+/* -+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU Lesser General Public License version 2.1 as -+ * published by the Free Software Foundation. -+ * -+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. -+ */ -+ -+#ifndef __YAFFS_ALLOCATOR_H__ -+#define __YAFFS_ALLOCATOR_H__ -+ -+#include "yaffs_guts.h" -+ -+void yaffs_init_raw_tnodes_and_objs(struct yaffs_dev *dev); -+void yaffs_deinit_raw_tnodes_and_objs(struct yaffs_dev *dev); -+ -+struct yaffs_tnode *yaffs_alloc_raw_tnode(struct yaffs_dev *dev); -+void yaffs_free_raw_tnode(struct yaffs_dev *dev, struct yaffs_tnode *tn); -+ -+struct yaffs_obj *yaffs_alloc_raw_obj(struct yaffs_dev *dev); -+void yaffs_free_raw_obj(struct yaffs_dev *dev, struct yaffs_obj *obj); -+ -+#endif -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_attribs.c linux-2.6.36/fs/yaffs2/yaffs_attribs.c ---- linux-2.6.36.orig/fs/yaffs2/yaffs_attribs.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_attribs.c 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,124 @@ -+/* -+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include "yaffs_guts.h" -+#include "yaffs_attribs.h" -+ -+void yaffs_load_attribs(struct yaffs_obj *obj, struct yaffs_obj_hdr *oh) -+{ -+ obj->yst_uid = oh->yst_uid; -+ obj->yst_gid = oh->yst_gid; -+ obj->yst_atime = oh->yst_atime; -+ obj->yst_mtime = oh->yst_mtime; -+ obj->yst_ctime = oh->yst_ctime; -+ obj->yst_rdev = oh->yst_rdev; -+} -+ -+void yaffs_load_attribs_oh(struct yaffs_obj_hdr *oh, struct yaffs_obj *obj) -+{ -+ oh->yst_uid = obj->yst_uid; -+ oh->yst_gid = obj->yst_gid; -+ oh->yst_atime = obj->yst_atime; -+ oh->yst_mtime = obj->yst_mtime; -+ oh->yst_ctime = obj->yst_ctime; -+ oh->yst_rdev = obj->yst_rdev; -+ -+} -+ -+void yaffs_load_current_time(struct yaffs_obj *obj, int do_a, int do_c) -+{ -+ obj->yst_mtime = Y_CURRENT_TIME; -+ if (do_a) -+ obj->yst_atime = obj->yst_atime; -+ if (do_c) -+ obj->yst_ctime = obj->yst_atime; -+} -+ -+void yaffs_attribs_init(struct yaffs_obj *obj, u32 gid, u32 uid, u32 rdev) -+{ -+ yaffs_load_current_time(obj, 1, 1); -+ obj->yst_rdev = rdev; -+ obj->yst_uid = uid; -+ obj->yst_gid = gid; -+} -+ -+loff_t yaffs_get_file_size(struct yaffs_obj *obj) -+{ -+ YCHAR *alias = NULL; -+ obj = yaffs_get_equivalent_obj(obj); -+ -+ switch (obj->variant_type) { -+ case YAFFS_OBJECT_TYPE_FILE: -+ return obj->variant.file_variant.file_size; -+ case YAFFS_OBJECT_TYPE_SYMLINK: -+ alias = obj->variant.symlink_variant.alias; -+ if (!alias) -+ return 0; -+ return yaffs_strnlen(alias, YAFFS_MAX_ALIAS_LENGTH); -+ default: -+ return 0; -+ } -+} -+ -+int yaffs_set_attribs(struct yaffs_obj *obj, struct iattr *attr) -+{ -+ unsigned int valid = attr->ia_valid; -+ -+ if (valid & ATTR_MODE) -+ obj->yst_mode = attr->ia_mode; -+ if (valid & ATTR_UID) -+ obj->yst_uid = attr->ia_uid; -+ if (valid & ATTR_GID) -+ obj->yst_gid = attr->ia_gid; -+ -+ if (valid & ATTR_ATIME) -+ obj->yst_atime = Y_TIME_CONVERT(attr->ia_atime); -+ if (valid & ATTR_CTIME) -+ obj->yst_ctime = Y_TIME_CONVERT(attr->ia_ctime); -+ if (valid & ATTR_MTIME) -+ obj->yst_mtime = Y_TIME_CONVERT(attr->ia_mtime); -+ -+ if (valid & ATTR_SIZE) -+ yaffs_resize_file(obj, attr->ia_size); -+ -+ yaffs_update_oh(obj, NULL, 1, 0, 0, NULL); -+ -+ return YAFFS_OK; -+ -+} -+ -+int yaffs_get_attribs(struct yaffs_obj *obj, struct iattr *attr) -+{ -+ unsigned int valid = 0; -+ -+ attr->ia_mode = obj->yst_mode; -+ valid |= ATTR_MODE; -+ attr->ia_uid = obj->yst_uid; -+ valid |= ATTR_UID; -+ attr->ia_gid = obj->yst_gid; -+ valid |= ATTR_GID; -+ -+ Y_TIME_CONVERT(attr->ia_atime) = obj->yst_atime; -+ valid |= ATTR_ATIME; -+ Y_TIME_CONVERT(attr->ia_ctime) = obj->yst_ctime; -+ valid |= ATTR_CTIME; -+ Y_TIME_CONVERT(attr->ia_mtime) = obj->yst_mtime; -+ valid |= ATTR_MTIME; -+ -+ attr->ia_size = yaffs_get_file_size(obj); -+ valid |= ATTR_SIZE; -+ -+ attr->ia_valid = valid; -+ -+ return YAFFS_OK; -+} -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_attribs.h linux-2.6.36/fs/yaffs2/yaffs_attribs.h ---- linux-2.6.36.orig/fs/yaffs2/yaffs_attribs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_attribs.h 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,28 @@ -+/* -+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU Lesser General Public License version 2.1 as -+ * published by the Free Software Foundation. -+ * -+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. -+ */ -+ -+#ifndef __YAFFS_ATTRIBS_H__ -+#define __YAFFS_ATTRIBS_H__ -+ -+#include "yaffs_guts.h" -+ -+void yaffs_load_attribs(struct yaffs_obj *obj, struct yaffs_obj_hdr *oh); -+void yaffs_load_attribs_oh(struct yaffs_obj_hdr *oh, struct yaffs_obj *obj); -+void yaffs_attribs_init(struct yaffs_obj *obj, u32 gid, u32 uid, u32 rdev); -+void yaffs_load_current_time(struct yaffs_obj *obj, int do_a, int do_c); -+int yaffs_set_attribs(struct yaffs_obj *obj, struct iattr *attr); -+int yaffs_get_attribs(struct yaffs_obj *obj, struct iattr *attr); -+ -+#endif -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_bitmap.c linux-2.6.36/fs/yaffs2/yaffs_bitmap.c ---- linux-2.6.36.orig/fs/yaffs2/yaffs_bitmap.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_bitmap.c 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,104 @@ -+/* -+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include "yaffs_bitmap.h" -+#include "yaffs_trace.h" -+/* -+ * Chunk bitmap manipulations -+ */ -+ -+static Y_INLINE u8 *yaffs_block_bits(struct yaffs_dev *dev, int blk) -+{ -+ if (blk < dev->internal_start_block || blk > dev->internal_end_block) { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR("**>> yaffs: BlockBits block %d is not valid" TENDSTR), -+ blk)); -+ YBUG(); -+ } -+ return dev->chunk_bits + -+ (dev->chunk_bit_stride * (blk - dev->internal_start_block)); -+} -+ -+void yaffs_verify_chunk_bit_id(struct yaffs_dev *dev, int blk, int chunk) -+{ -+ if (blk < dev->internal_start_block || blk > dev->internal_end_block || -+ chunk < 0 || chunk >= dev->param.chunks_per_block) { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR("**>> yaffs: Chunk Id (%d:%d) invalid" TENDSTR), -+ blk, chunk)); -+ YBUG(); -+ } -+} -+ -+void yaffs_clear_chunk_bits(struct yaffs_dev *dev, int blk) -+{ -+ u8 *blk_bits = yaffs_block_bits(dev, blk); -+ -+ memset(blk_bits, 0, dev->chunk_bit_stride); -+} -+ -+void yaffs_clear_chunk_bit(struct yaffs_dev *dev, int blk, int chunk) -+{ -+ u8 *blk_bits = yaffs_block_bits(dev, blk); -+ -+ yaffs_verify_chunk_bit_id(dev, blk, chunk); -+ -+ blk_bits[chunk / 8] &= ~(1 << (chunk & 7)); -+} -+ -+void yaffs_set_chunk_bit(struct yaffs_dev *dev, int blk, int chunk) -+{ -+ u8 *blk_bits = yaffs_block_bits(dev, blk); -+ -+ yaffs_verify_chunk_bit_id(dev, blk, chunk); -+ -+ blk_bits[chunk / 8] |= (1 << (chunk & 7)); -+} -+ -+int yaffs_check_chunk_bit(struct yaffs_dev *dev, int blk, int chunk) -+{ -+ u8 *blk_bits = yaffs_block_bits(dev, blk); -+ yaffs_verify_chunk_bit_id(dev, blk, chunk); -+ -+ return (blk_bits[chunk / 8] & (1 << (chunk & 7))) ? 1 : 0; -+} -+ -+int yaffs_still_some_chunks(struct yaffs_dev *dev, int blk) -+{ -+ u8 *blk_bits = yaffs_block_bits(dev, blk); -+ int i; -+ for (i = 0; i < dev->chunk_bit_stride; i++) { -+ if (*blk_bits) -+ return 1; -+ blk_bits++; -+ } -+ return 0; -+} -+ -+int yaffs_count_chunk_bits(struct yaffs_dev *dev, int blk) -+{ -+ u8 *blk_bits = yaffs_block_bits(dev, blk); -+ int i; -+ int n = 0; -+ for (i = 0; i < dev->chunk_bit_stride; i++) { -+ u8 x = *blk_bits; -+ while (x) { -+ if (x & 1) -+ n++; -+ x >>= 1; -+ } -+ -+ blk_bits++; -+ } -+ return n; -+} -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_bitmap.h linux-2.6.36/fs/yaffs2/yaffs_bitmap.h ---- linux-2.6.36.orig/fs/yaffs2/yaffs_bitmap.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_bitmap.h 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,33 @@ -+/* -+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU Lesser General Public License version 2.1 as -+ * published by the Free Software Foundation. -+ * -+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. -+ */ -+ -+/* -+ * Chunk bitmap manipulations -+ */ -+ -+#ifndef __YAFFS_BITMAP_H__ -+#define __YAFFS_BITMAP_H__ -+ -+#include "yaffs_guts.h" -+ -+void yaffs_verify_chunk_bit_id(struct yaffs_dev *dev, int blk, int chunk); -+void yaffs_clear_chunk_bits(struct yaffs_dev *dev, int blk); -+void yaffs_clear_chunk_bit(struct yaffs_dev *dev, int blk, int chunk); -+void yaffs_set_chunk_bit(struct yaffs_dev *dev, int blk, int chunk); -+int yaffs_check_chunk_bit(struct yaffs_dev *dev, int blk, int chunk); -+int yaffs_still_some_chunks(struct yaffs_dev *dev, int blk); -+int yaffs_count_chunk_bits(struct yaffs_dev *dev, int blk); -+ -+#endif -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_checkptrw.c linux-2.6.36/fs/yaffs2/yaffs_checkptrw.c ---- linux-2.6.36.orig/fs/yaffs2/yaffs_checkptrw.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_checkptrw.c 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,420 @@ -+/* -+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include "yaffs_checkptrw.h" -+#include "yaffs_getblockinfo.h" -+ -+static int yaffs2_checkpt_space_ok(struct yaffs_dev *dev) -+{ -+ int blocks_avail = dev->n_erased_blocks - dev->param.n_reserved_blocks; -+ -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR("checkpt blocks available = %d" TENDSTR), blocks_avail)); -+ -+ return (blocks_avail <= 0) ? 0 : 1; -+} -+ -+static int yaffs_checkpt_erase(struct yaffs_dev *dev) -+{ -+ int i; -+ -+ if (!dev->param.erase_fn) -+ return 0; -+ T(YAFFS_TRACE_CHECKPOINT, (TSTR("checking blocks %d to %d" TENDSTR), -+ dev->internal_start_block, -+ dev->internal_end_block)); -+ -+ for (i = dev->internal_start_block; i <= dev->internal_end_block; i++) { -+ struct yaffs_block_info *bi = yaffs_get_block_info(dev, i); -+ if (bi->block_state == YAFFS_BLOCK_STATE_CHECKPOINT) { -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR("erasing checkpt block %d" TENDSTR), i)); -+ -+ dev->n_erasures++; -+ -+ if (dev->param. -+ erase_fn(dev, -+ i - dev->block_offset /* realign */ )) { -+ bi->block_state = YAFFS_BLOCK_STATE_EMPTY; -+ dev->n_erased_blocks++; -+ dev->n_free_chunks += -+ dev->param.chunks_per_block; -+ } else { -+ dev->param.bad_block_fn(dev, i); -+ bi->block_state = YAFFS_BLOCK_STATE_DEAD; -+ } -+ } -+ } -+ -+ dev->blocks_in_checkpt = 0; -+ -+ return 1; -+} -+ -+static void yaffs2_checkpt_find_erased_block(struct yaffs_dev *dev) -+{ -+ int i; -+ int blocks_avail = dev->n_erased_blocks - dev->param.n_reserved_blocks; -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR -+ ("allocating checkpt block: erased %d reserved %d avail %d next %d " -+ TENDSTR), dev->n_erased_blocks, dev->param.n_reserved_blocks, -+ blocks_avail, dev->checkpt_next_block)); -+ -+ if (dev->checkpt_next_block >= 0 && -+ dev->checkpt_next_block <= dev->internal_end_block && -+ blocks_avail > 0) { -+ -+ for (i = dev->checkpt_next_block; i <= dev->internal_end_block; -+ i++) { -+ struct yaffs_block_info *bi = -+ yaffs_get_block_info(dev, i); -+ if (bi->block_state == YAFFS_BLOCK_STATE_EMPTY) { -+ dev->checkpt_next_block = i + 1; -+ dev->checkpt_cur_block = i; -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR("allocating checkpt block %d" TENDSTR), -+ i)); -+ return; -+ } -+ } -+ } -+ T(YAFFS_TRACE_CHECKPOINT, (TSTR("out of checkpt blocks" TENDSTR))); -+ -+ dev->checkpt_next_block = -1; -+ dev->checkpt_cur_block = -1; -+} -+ -+static void yaffs2_checkpt_find_block(struct yaffs_dev *dev) -+{ -+ int i; -+ struct yaffs_ext_tags tags; -+ -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR("find next checkpt block: start: blocks %d next %d" TENDSTR), -+ dev->blocks_in_checkpt, dev->checkpt_next_block)); -+ -+ if (dev->blocks_in_checkpt < dev->checkpt_max_blocks) -+ for (i = dev->checkpt_next_block; i <= dev->internal_end_block; -+ i++) { -+ int chunk = i * dev->param.chunks_per_block; -+ int realigned_chunk = chunk - dev->chunk_offset; -+ -+ dev->param.read_chunk_tags_fn(dev, realigned_chunk, -+ NULL, &tags); -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR -+ ("find next checkpt block: search: block %d oid %d seq %d eccr %d" -+ TENDSTR), i, tags.obj_id, tags.seq_number, -+ tags.ecc_result)); -+ -+ if (tags.seq_number == YAFFS_SEQUENCE_CHECKPOINT_DATA) { -+ /* Right kind of block */ -+ dev->checkpt_next_block = tags.obj_id; -+ dev->checkpt_cur_block = i; -+ dev->checkpt_block_list[dev-> -+ blocks_in_checkpt] = i; -+ dev->blocks_in_checkpt++; -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR("found checkpt block %d" TENDSTR), i)); -+ return; -+ } -+ } -+ -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR("found no more checkpt blocks" TENDSTR))); -+ -+ dev->checkpt_next_block = -1; -+ dev->checkpt_cur_block = -1; -+} -+ -+int yaffs2_checkpt_open(struct yaffs_dev *dev, int writing) -+{ -+ -+ dev->checkpt_open_write = writing; -+ -+ /* Got the functions we need? */ -+ if (!dev->param.write_chunk_tags_fn || -+ !dev->param.read_chunk_tags_fn || -+ !dev->param.erase_fn || !dev->param.bad_block_fn) -+ return 0; -+ -+ if (writing && !yaffs2_checkpt_space_ok(dev)) -+ return 0; -+ -+ if (!dev->checkpt_buffer) -+ dev->checkpt_buffer = -+ YMALLOC_DMA(dev->param.total_bytes_per_chunk); -+ if (!dev->checkpt_buffer) -+ return 0; -+ -+ dev->checkpt_page_seq = 0; -+ dev->checkpt_byte_count = 0; -+ dev->checkpt_sum = 0; -+ dev->checkpt_xor = 0; -+ dev->checkpt_cur_block = -1; -+ dev->checkpt_cur_chunk = -1; -+ dev->checkpt_next_block = dev->internal_start_block; -+ -+ /* Erase all the blocks in the checkpoint area */ -+ if (writing) { -+ memset(dev->checkpt_buffer, 0, dev->data_bytes_per_chunk); -+ dev->checkpt_byte_offs = 0; -+ return yaffs_checkpt_erase(dev); -+ } else { -+ int i; -+ /* Set to a value that will kick off a read */ -+ dev->checkpt_byte_offs = dev->data_bytes_per_chunk; -+ /* A checkpoint block list of 1 checkpoint block per 16 block is (hopefully) -+ * going to be way more than we need */ -+ dev->blocks_in_checkpt = 0; -+ dev->checkpt_max_blocks = -+ (dev->internal_end_block - dev->internal_start_block) / 16 + -+ 2; -+ dev->checkpt_block_list = -+ YMALLOC(sizeof(int) * dev->checkpt_max_blocks); -+ if (!dev->checkpt_block_list) -+ return 0; -+ -+ for (i = 0; i < dev->checkpt_max_blocks; i++) -+ dev->checkpt_block_list[i] = -1; -+ } -+ -+ return 1; -+} -+ -+int yaffs2_get_checkpt_sum(struct yaffs_dev *dev, u32 * sum) -+{ -+ u32 composite_sum; -+ composite_sum = (dev->checkpt_sum << 8) | (dev->checkpt_xor & 0xFF); -+ *sum = composite_sum; -+ return 1; -+} -+ -+static int yaffs2_checkpt_flush_buffer(struct yaffs_dev *dev) -+{ -+ int chunk; -+ int realigned_chunk; -+ -+ struct yaffs_ext_tags tags; -+ -+ if (dev->checkpt_cur_block < 0) { -+ yaffs2_checkpt_find_erased_block(dev); -+ dev->checkpt_cur_chunk = 0; -+ } -+ -+ if (dev->checkpt_cur_block < 0) -+ return 0; -+ -+ tags.is_deleted = 0; -+ tags.obj_id = dev->checkpt_next_block; /* Hint to next place to look */ -+ tags.chunk_id = dev->checkpt_page_seq + 1; -+ tags.seq_number = YAFFS_SEQUENCE_CHECKPOINT_DATA; -+ tags.n_bytes = dev->data_bytes_per_chunk; -+ if (dev->checkpt_cur_chunk == 0) { -+ /* First chunk we write for the block? Set block state to -+ checkpoint */ -+ struct yaffs_block_info *bi = -+ yaffs_get_block_info(dev, dev->checkpt_cur_block); -+ bi->block_state = YAFFS_BLOCK_STATE_CHECKPOINT; -+ dev->blocks_in_checkpt++; -+ } -+ -+ chunk = -+ dev->checkpt_cur_block * dev->param.chunks_per_block + -+ dev->checkpt_cur_chunk; -+ -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR -+ ("checkpoint wite buffer nand %d(%d:%d) objid %d chId %d" TENDSTR), -+ chunk, dev->checkpt_cur_block, dev->checkpt_cur_chunk, tags.obj_id, -+ tags.chunk_id)); -+ -+ realigned_chunk = chunk - dev->chunk_offset; -+ -+ dev->n_page_writes++; -+ -+ dev->param.write_chunk_tags_fn(dev, realigned_chunk, -+ dev->checkpt_buffer, &tags); -+ dev->checkpt_byte_offs = 0; -+ dev->checkpt_page_seq++; -+ dev->checkpt_cur_chunk++; -+ if (dev->checkpt_cur_chunk >= dev->param.chunks_per_block) { -+ dev->checkpt_cur_chunk = 0; -+ dev->checkpt_cur_block = -1; -+ } -+ memset(dev->checkpt_buffer, 0, dev->data_bytes_per_chunk); -+ -+ return 1; -+} -+ -+int yaffs2_checkpt_wr(struct yaffs_dev *dev, const void *data, int n_bytes) -+{ -+ int i = 0; -+ int ok = 1; -+ -+ u8 *data_bytes = (u8 *) data; -+ -+ if (!dev->checkpt_buffer) -+ return 0; -+ -+ if (!dev->checkpt_open_write) -+ return -1; -+ -+ while (i < n_bytes && ok) { -+ dev->checkpt_buffer[dev->checkpt_byte_offs] = *data_bytes; -+ dev->checkpt_sum += *data_bytes; -+ dev->checkpt_xor ^= *data_bytes; -+ -+ dev->checkpt_byte_offs++; -+ i++; -+ data_bytes++; -+ dev->checkpt_byte_count++; -+ -+ if (dev->checkpt_byte_offs < 0 || -+ dev->checkpt_byte_offs >= dev->data_bytes_per_chunk) -+ ok = yaffs2_checkpt_flush_buffer(dev); -+ } -+ -+ return i; -+} -+ -+int yaffs2_checkpt_rd(struct yaffs_dev *dev, void *data, int n_bytes) -+{ -+ int i = 0; -+ int ok = 1; -+ struct yaffs_ext_tags tags; -+ -+ int chunk; -+ int realigned_chunk; -+ -+ u8 *data_bytes = (u8 *) data; -+ -+ if (!dev->checkpt_buffer) -+ return 0; -+ -+ if (dev->checkpt_open_write) -+ return -1; -+ -+ while (i < n_bytes && ok) { -+ -+ if (dev->checkpt_byte_offs < 0 || -+ dev->checkpt_byte_offs >= dev->data_bytes_per_chunk) { -+ -+ if (dev->checkpt_cur_block < 0) { -+ yaffs2_checkpt_find_block(dev); -+ dev->checkpt_cur_chunk = 0; -+ } -+ -+ if (dev->checkpt_cur_block < 0) -+ ok = 0; -+ else { -+ chunk = dev->checkpt_cur_block * -+ dev->param.chunks_per_block + -+ dev->checkpt_cur_chunk; -+ -+ realigned_chunk = chunk - dev->chunk_offset; -+ -+ dev->n_page_reads++; -+ -+ /* read in the next chunk */ -+ dev->param.read_chunk_tags_fn(dev, -+ realigned_chunk, -+ dev-> -+ checkpt_buffer, -+ &tags); -+ -+ if (tags.chunk_id != (dev->checkpt_page_seq + 1) -+ || tags.ecc_result > YAFFS_ECC_RESULT_FIXED -+ || tags.seq_number != -+ YAFFS_SEQUENCE_CHECKPOINT_DATA) -+ ok = 0; -+ -+ dev->checkpt_byte_offs = 0; -+ dev->checkpt_page_seq++; -+ dev->checkpt_cur_chunk++; -+ -+ if (dev->checkpt_cur_chunk >= -+ dev->param.chunks_per_block) -+ dev->checkpt_cur_block = -1; -+ } -+ } -+ -+ if (ok) { -+ *data_bytes = -+ dev->checkpt_buffer[dev->checkpt_byte_offs]; -+ dev->checkpt_sum += *data_bytes; -+ dev->checkpt_xor ^= *data_bytes; -+ dev->checkpt_byte_offs++; -+ i++; -+ data_bytes++; -+ dev->checkpt_byte_count++; -+ } -+ } -+ -+ return i; -+} -+ -+int yaffs_checkpt_close(struct yaffs_dev *dev) -+{ -+ -+ if (dev->checkpt_open_write) { -+ if (dev->checkpt_byte_offs != 0) -+ yaffs2_checkpt_flush_buffer(dev); -+ } else if (dev->checkpt_block_list) { -+ int i; -+ for (i = 0; -+ i < dev->blocks_in_checkpt -+ && dev->checkpt_block_list[i] >= 0; i++) { -+ int blk = dev->checkpt_block_list[i]; -+ struct yaffs_block_info *bi = NULL; -+ if (dev->internal_start_block <= blk -+ && blk <= dev->internal_end_block) -+ bi = yaffs_get_block_info(dev, blk); -+ if (bi && bi->block_state == YAFFS_BLOCK_STATE_EMPTY) -+ bi->block_state = YAFFS_BLOCK_STATE_CHECKPOINT; -+ else { -+ /* Todo this looks odd... */ -+ } -+ } -+ YFREE(dev->checkpt_block_list); -+ dev->checkpt_block_list = NULL; -+ } -+ -+ dev->n_free_chunks -= -+ dev->blocks_in_checkpt * dev->param.chunks_per_block; -+ dev->n_erased_blocks -= dev->blocks_in_checkpt; -+ -+ T(YAFFS_TRACE_CHECKPOINT, (TSTR("checkpoint byte count %d" TENDSTR), -+ dev->checkpt_byte_count)); -+ -+ if (dev->checkpt_buffer) { -+ /* free the buffer */ -+ YFREE(dev->checkpt_buffer); -+ dev->checkpt_buffer = NULL; -+ return 1; -+ } else { -+ return 0; -+ } -+} -+ -+int yaffs2_checkpt_invalidate_stream(struct yaffs_dev *dev) -+{ -+ /* Erase the checkpoint data */ -+ -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR("checkpoint invalidate of %d blocks" TENDSTR), -+ dev->blocks_in_checkpt)); -+ -+ return yaffs_checkpt_erase(dev); -+} -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_checkptrw.h linux-2.6.36/fs/yaffs2/yaffs_checkptrw.h ---- linux-2.6.36.orig/fs/yaffs2/yaffs_checkptrw.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_checkptrw.h 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,33 @@ -+/* -+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU Lesser General Public License version 2.1 as -+ * published by the Free Software Foundation. -+ * -+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. -+ */ -+ -+#ifndef __YAFFS_CHECKPTRW_H__ -+#define __YAFFS_CHECKPTRW_H__ -+ -+#include "yaffs_guts.h" -+ -+int yaffs2_checkpt_open(struct yaffs_dev *dev, int writing); -+ -+int yaffs2_checkpt_wr(struct yaffs_dev *dev, const void *data, int n_bytes); -+ -+int yaffs2_checkpt_rd(struct yaffs_dev *dev, void *data, int n_bytes); -+ -+int yaffs2_get_checkpt_sum(struct yaffs_dev *dev, u32 * sum); -+ -+int yaffs_checkpt_close(struct yaffs_dev *dev); -+ -+int yaffs2_checkpt_invalidate_stream(struct yaffs_dev *dev); -+ -+#endif -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_ecc.c linux-2.6.36/fs/yaffs2/yaffs_ecc.c ---- linux-2.6.36.orig/fs/yaffs2/yaffs_ecc.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_ecc.c 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,322 @@ -+/* -+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+/* -+ * This code implements the ECC algorithm used in SmartMedia. -+ * -+ * The ECC comprises 22 bits of parity information and is stuffed into 3 bytes. -+ * The two unused bit are set to 1. -+ * The ECC can correct single bit errors in a 256-byte page of data. Thus, two such ECC -+ * blocks are used on a 512-byte NAND page. -+ * -+ */ -+ -+/* Table generated by gen-ecc.c -+ * Using a table means we do not have to calculate p1..p4 and p1'..p4' -+ * for each byte of data. These are instead provided in a table in bits7..2. -+ * Bit 0 of each entry indicates whether the entry has an odd or even parity, and therefore -+ * this bytes influence on the line parity. -+ */ -+ -+#include "yportenv.h" -+ -+#include "yaffs_ecc.h" -+ -+static const unsigned char column_parity_table[] = { -+ 0x00, 0x55, 0x59, 0x0c, 0x65, 0x30, 0x3c, 0x69, -+ 0x69, 0x3c, 0x30, 0x65, 0x0c, 0x59, 0x55, 0x00, -+ 0x95, 0xc0, 0xcc, 0x99, 0xf0, 0xa5, 0xa9, 0xfc, -+ 0xfc, 0xa9, 0xa5, 0xf0, 0x99, 0xcc, 0xc0, 0x95, -+ 0x99, 0xcc, 0xc0, 0x95, 0xfc, 0xa9, 0xa5, 0xf0, -+ 0xf0, 0xa5, 0xa9, 0xfc, 0x95, 0xc0, 0xcc, 0x99, -+ 0x0c, 0x59, 0x55, 0x00, 0x69, 0x3c, 0x30, 0x65, -+ 0x65, 0x30, 0x3c, 0x69, 0x00, 0x55, 0x59, 0x0c, -+ 0xa5, 0xf0, 0xfc, 0xa9, 0xc0, 0x95, 0x99, 0xcc, -+ 0xcc, 0x99, 0x95, 0xc0, 0xa9, 0xfc, 0xf0, 0xa5, -+ 0x30, 0x65, 0x69, 0x3c, 0x55, 0x00, 0x0c, 0x59, -+ 0x59, 0x0c, 0x00, 0x55, 0x3c, 0x69, 0x65, 0x30, -+ 0x3c, 0x69, 0x65, 0x30, 0x59, 0x0c, 0x00, 0x55, -+ 0x55, 0x00, 0x0c, 0x59, 0x30, 0x65, 0x69, 0x3c, -+ 0xa9, 0xfc, 0xf0, 0xa5, 0xcc, 0x99, 0x95, 0xc0, -+ 0xc0, 0x95, 0x99, 0xcc, 0xa5, 0xf0, 0xfc, 0xa9, -+ 0xa9, 0xfc, 0xf0, 0xa5, 0xcc, 0x99, 0x95, 0xc0, -+ 0xc0, 0x95, 0x99, 0xcc, 0xa5, 0xf0, 0xfc, 0xa9, -+ 0x3c, 0x69, 0x65, 0x30, 0x59, 0x0c, 0x00, 0x55, -+ 0x55, 0x00, 0x0c, 0x59, 0x30, 0x65, 0x69, 0x3c, -+ 0x30, 0x65, 0x69, 0x3c, 0x55, 0x00, 0x0c, 0x59, -+ 0x59, 0x0c, 0x00, 0x55, 0x3c, 0x69, 0x65, 0x30, -+ 0xa5, 0xf0, 0xfc, 0xa9, 0xc0, 0x95, 0x99, 0xcc, -+ 0xcc, 0x99, 0x95, 0xc0, 0xa9, 0xfc, 0xf0, 0xa5, -+ 0x0c, 0x59, 0x55, 0x00, 0x69, 0x3c, 0x30, 0x65, -+ 0x65, 0x30, 0x3c, 0x69, 0x00, 0x55, 0x59, 0x0c, -+ 0x99, 0xcc, 0xc0, 0x95, 0xfc, 0xa9, 0xa5, 0xf0, -+ 0xf0, 0xa5, 0xa9, 0xfc, 0x95, 0xc0, 0xcc, 0x99, -+ 0x95, 0xc0, 0xcc, 0x99, 0xf0, 0xa5, 0xa9, 0xfc, -+ 0xfc, 0xa9, 0xa5, 0xf0, 0x99, 0xcc, 0xc0, 0x95, -+ 0x00, 0x55, 0x59, 0x0c, 0x65, 0x30, 0x3c, 0x69, -+ 0x69, 0x3c, 0x30, 0x65, 0x0c, 0x59, 0x55, 0x00, -+}; -+ -+/* Count the bits in an unsigned char or a U32 */ -+ -+static int yaffs_count_bits(unsigned char x) -+{ -+ int r = 0; -+ while (x) { -+ if (x & 1) -+ r++; -+ x >>= 1; -+ } -+ return r; -+} -+ -+static int yaffs_count_bits32(unsigned x) -+{ -+ int r = 0; -+ while (x) { -+ if (x & 1) -+ r++; -+ x >>= 1; -+ } -+ return r; -+} -+ -+/* Calculate the ECC for a 256-byte block of data */ -+void yaffs_ecc_cacl(const unsigned char *data, unsigned char *ecc) -+{ -+ unsigned int i; -+ -+ unsigned char col_parity = 0; -+ unsigned char line_parity = 0; -+ unsigned char line_parity_prime = 0; -+ unsigned char t; -+ unsigned char b; -+ -+ for (i = 0; i < 256; i++) { -+ b = column_parity_table[*data++]; -+ col_parity ^= b; -+ -+ if (b & 0x01) { /* odd number of bits in the byte */ -+ line_parity ^= i; -+ line_parity_prime ^= ~i; -+ } -+ } -+ -+ ecc[2] = (~col_parity) | 0x03; -+ -+ t = 0; -+ if (line_parity & 0x80) -+ t |= 0x80; -+ if (line_parity_prime & 0x80) -+ t |= 0x40; -+ if (line_parity & 0x40) -+ t |= 0x20; -+ if (line_parity_prime & 0x40) -+ t |= 0x10; -+ if (line_parity & 0x20) -+ t |= 0x08; -+ if (line_parity_prime & 0x20) -+ t |= 0x04; -+ if (line_parity & 0x10) -+ t |= 0x02; -+ if (line_parity_prime & 0x10) -+ t |= 0x01; -+ ecc[1] = ~t; -+ -+ t = 0; -+ if (line_parity & 0x08) -+ t |= 0x80; -+ if (line_parity_prime & 0x08) -+ t |= 0x40; -+ if (line_parity & 0x04) -+ t |= 0x20; -+ if (line_parity_prime & 0x04) -+ t |= 0x10; -+ if (line_parity & 0x02) -+ t |= 0x08; -+ if (line_parity_prime & 0x02) -+ t |= 0x04; -+ if (line_parity & 0x01) -+ t |= 0x02; -+ if (line_parity_prime & 0x01) -+ t |= 0x01; -+ ecc[0] = ~t; -+ -+#ifdef CONFIG_YAFFS_ECC_WRONG_ORDER -+ /* Swap the bytes into the wrong order */ -+ t = ecc[0]; -+ ecc[0] = ecc[1]; -+ ecc[1] = t; -+#endif -+} -+ -+/* Correct the ECC on a 256 byte block of data */ -+ -+int yaffs_ecc_correct(unsigned char *data, unsigned char *read_ecc, -+ const unsigned char *test_ecc) -+{ -+ unsigned char d0, d1, d2; /* deltas */ -+ -+ d0 = read_ecc[0] ^ test_ecc[0]; -+ d1 = read_ecc[1] ^ test_ecc[1]; -+ d2 = read_ecc[2] ^ test_ecc[2]; -+ -+ if ((d0 | d1 | d2) == 0) -+ return 0; /* no error */ -+ -+ if (((d0 ^ (d0 >> 1)) & 0x55) == 0x55 && -+ ((d1 ^ (d1 >> 1)) & 0x55) == 0x55 && -+ ((d2 ^ (d2 >> 1)) & 0x54) == 0x54) { -+ /* Single bit (recoverable) error in data */ -+ -+ unsigned byte; -+ unsigned bit; -+ -+#ifdef CONFIG_YAFFS_ECC_WRONG_ORDER -+ /* swap the bytes to correct for the wrong order */ -+ unsigned char t; -+ -+ t = d0; -+ d0 = d1; -+ d1 = t; -+#endif -+ -+ bit = byte = 0; -+ -+ if (d1 & 0x80) -+ byte |= 0x80; -+ if (d1 & 0x20) -+ byte |= 0x40; -+ if (d1 & 0x08) -+ byte |= 0x20; -+ if (d1 & 0x02) -+ byte |= 0x10; -+ if (d0 & 0x80) -+ byte |= 0x08; -+ if (d0 & 0x20) -+ byte |= 0x04; -+ if (d0 & 0x08) -+ byte |= 0x02; -+ if (d0 & 0x02) -+ byte |= 0x01; -+ -+ if (d2 & 0x80) -+ bit |= 0x04; -+ if (d2 & 0x20) -+ bit |= 0x02; -+ if (d2 & 0x08) -+ bit |= 0x01; -+ -+ data[byte] ^= (1 << bit); -+ -+ return 1; /* Corrected the error */ -+ } -+ -+ if ((yaffs_count_bits(d0) + -+ yaffs_count_bits(d1) + yaffs_count_bits(d2)) == 1) { -+ /* Reccoverable error in ecc */ -+ -+ read_ecc[0] = test_ecc[0]; -+ read_ecc[1] = test_ecc[1]; -+ read_ecc[2] = test_ecc[2]; -+ -+ return 1; /* Corrected the error */ -+ } -+ -+ /* Unrecoverable error */ -+ -+ return -1; -+ -+} -+ -+/* -+ * ECCxxxOther does ECC calcs on arbitrary n bytes of data -+ */ -+void yaffs_ecc_calc_other(const unsigned char *data, unsigned n_bytes, -+ struct yaffs_ecc_other *ecc_other) -+{ -+ unsigned int i; -+ -+ unsigned char col_parity = 0; -+ unsigned line_parity = 0; -+ unsigned line_parity_prime = 0; -+ unsigned char b; -+ -+ for (i = 0; i < n_bytes; i++) { -+ b = column_parity_table[*data++]; -+ col_parity ^= b; -+ -+ if (b & 0x01) { -+ /* odd number of bits in the byte */ -+ line_parity ^= i; -+ line_parity_prime ^= ~i; -+ } -+ -+ } -+ -+ ecc_other->col_parity = (col_parity >> 2) & 0x3f; -+ ecc_other->line_parity = line_parity; -+ ecc_other->line_parity_prime = line_parity_prime; -+} -+ -+int yaffs_ecc_correct_other(unsigned char *data, unsigned n_bytes, -+ struct yaffs_ecc_other *read_ecc, -+ const struct yaffs_ecc_other *test_ecc) -+{ -+ unsigned char delta_col; /* column parity delta */ -+ unsigned delta_line; /* line parity delta */ -+ unsigned delta_line_prime; /* line parity delta */ -+ unsigned bit; -+ -+ delta_col = read_ecc->col_parity ^ test_ecc->col_parity; -+ delta_line = read_ecc->line_parity ^ test_ecc->line_parity; -+ delta_line_prime = -+ read_ecc->line_parity_prime ^ test_ecc->line_parity_prime; -+ -+ if ((delta_col | delta_line | delta_line_prime) == 0) -+ return 0; /* no error */ -+ -+ if (delta_line == ~delta_line_prime && -+ (((delta_col ^ (delta_col >> 1)) & 0x15) == 0x15)) { -+ /* Single bit (recoverable) error in data */ -+ -+ bit = 0; -+ -+ if (delta_col & 0x20) -+ bit |= 0x04; -+ if (delta_col & 0x08) -+ bit |= 0x02; -+ if (delta_col & 0x02) -+ bit |= 0x01; -+ -+ if (delta_line >= n_bytes) -+ return -1; -+ -+ data[delta_line] ^= (1 << bit); -+ -+ return 1; /* corrected */ -+ } -+ -+ if ((yaffs_count_bits32(delta_line) + -+ yaffs_count_bits32(delta_line_prime) + -+ yaffs_count_bits(delta_col)) == 1) { -+ /* Reccoverable error in ecc */ -+ -+ *read_ecc = *test_ecc; -+ return 1; /* corrected */ -+ } -+ -+ /* Unrecoverable error */ -+ -+ return -1; -+} -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_ecc.h linux-2.6.36/fs/yaffs2/yaffs_ecc.h ---- linux-2.6.36.orig/fs/yaffs2/yaffs_ecc.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_ecc.h 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,44 @@ -+/* -+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU Lesser General Public License version 2.1 as -+ * published by the Free Software Foundation. -+ * -+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. -+ */ -+ -+/* -+ * This code implements the ECC algorithm used in SmartMedia. -+ * -+ * The ECC comprises 22 bits of parity information and is stuffed into 3 bytes. -+ * The two unused bit are set to 1. -+ * The ECC can correct single bit errors in a 256-byte page of data. Thus, two such ECC -+ * blocks are used on a 512-byte NAND page. -+ * -+ */ -+ -+#ifndef __YAFFS_ECC_H__ -+#define __YAFFS_ECC_H__ -+ -+struct yaffs_ecc_other { -+ unsigned char col_parity; -+ unsigned line_parity; -+ unsigned line_parity_prime; -+}; -+ -+void yaffs_ecc_cacl(const unsigned char *data, unsigned char *ecc); -+int yaffs_ecc_correct(unsigned char *data, unsigned char *read_ecc, -+ const unsigned char *test_ecc); -+ -+void yaffs_ecc_calc_other(const unsigned char *data, unsigned n_bytes, -+ struct yaffs_ecc_other *ecc); -+int yaffs_ecc_correct_other(unsigned char *data, unsigned n_bytes, -+ struct yaffs_ecc_other *read_ecc, -+ const struct yaffs_ecc_other *test_ecc); -+#endif -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_getblockinfo.h linux-2.6.36/fs/yaffs2/yaffs_getblockinfo.h ---- linux-2.6.36.orig/fs/yaffs2/yaffs_getblockinfo.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_getblockinfo.h 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,36 @@ -+/* -+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU Lesser General Public License version 2.1 as -+ * published by the Free Software Foundation. -+ * -+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. -+ */ -+ -+#ifndef __YAFFS_GETBLOCKINFO_H__ -+#define __YAFFS_GETBLOCKINFO_H__ -+ -+#include "yaffs_guts.h" -+#include "yaffs_trace.h" -+ -+/* Function to manipulate block info */ -+static Y_INLINE struct yaffs_block_info *yaffs_get_block_info(struct yaffs_dev -+ *dev, int blk) -+{ -+ if (blk < dev->internal_start_block || blk > dev->internal_end_block) { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR -+ ("**>> yaffs: get_block_info block %d is not valid" TENDSTR), -+ blk)); -+ YBUG(); -+ } -+ return &dev->block_info[blk - dev->internal_start_block]; -+} -+ -+#endif -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_guts.c linux-2.6.36/fs/yaffs2/yaffs_guts.c ---- linux-2.6.36.orig/fs/yaffs2/yaffs_guts.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_guts.c 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,5227 @@ -+/* -+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include "yportenv.h" -+#include "yaffs_trace.h" -+ -+#include "yaffs_guts.h" -+#include "yaffs_tagsvalidity.h" -+#include "yaffs_getblockinfo.h" -+ -+#include "yaffs_tagscompat.h" -+ -+#include "yaffs_nand.h" -+ -+#include "yaffs_yaffs1.h" -+#include "yaffs_yaffs2.h" -+#include "yaffs_bitmap.h" -+#include "yaffs_verify.h" -+ -+#include "yaffs_nand.h" -+#include "yaffs_packedtags2.h" -+ -+#include "yaffs_nameval.h" -+#include "yaffs_allocator.h" -+ -+#include "yaffs_attribs.h" -+ -+/* Note YAFFS_GC_GOOD_ENOUGH must be <= YAFFS_GC_PASSIVE_THRESHOLD */ -+#define YAFFS_GC_GOOD_ENOUGH 2 -+#define YAFFS_GC_PASSIVE_THRESHOLD 4 -+ -+#include "yaffs_ecc.h" -+ -+/* Robustification (if it ever comes about...) */ -+static void yaffs_retire_block(struct yaffs_dev *dev, int flash_block); -+static void yaffs_handle_chunk_wr_error(struct yaffs_dev *dev, int nand_chunk, -+ int erased_ok); -+static void yaffs_handle_chunk_wr_ok(struct yaffs_dev *dev, int nand_chunk, -+ const u8 * data, -+ const struct yaffs_ext_tags *tags); -+static void yaffs_handle_chunk_update(struct yaffs_dev *dev, int nand_chunk, -+ const struct yaffs_ext_tags *tags); -+ -+/* Other local prototypes */ -+static void yaffs_update_parent(struct yaffs_obj *obj); -+static int yaffs_unlink_obj(struct yaffs_obj *obj); -+static int yaffs_obj_cache_dirty(struct yaffs_obj *obj); -+ -+static int yaffs_write_new_chunk(struct yaffs_dev *dev, -+ const u8 * buffer, -+ struct yaffs_ext_tags *tags, int use_reserver); -+ -+static struct yaffs_obj *yaffs_new_obj(struct yaffs_dev *dev, int number, -+ enum yaffs_obj_type type); -+ -+static int yaffs_apply_xattrib_mod(struct yaffs_obj *obj, char *buffer, -+ struct yaffs_xattr_mod *xmod); -+ -+static void yaffs_remove_obj_from_dir(struct yaffs_obj *obj); -+static int yaffs_generic_obj_del(struct yaffs_obj *in); -+ -+static int yaffs_check_chunk_erased(struct yaffs_dev *dev, int nand_chunk); -+ -+static int yaffs_unlink_worker(struct yaffs_obj *obj); -+ -+static int yaffs_tags_match(const struct yaffs_ext_tags *tags, int obj_id, -+ int chunk_obj); -+ -+static int yaffs_alloc_chunk(struct yaffs_dev *dev, int use_reserver, -+ struct yaffs_block_info **block_ptr); -+ -+static void yaffs_check_obj_details_loaded(struct yaffs_obj *in); -+ -+static void yaffs_invalidate_whole_cache(struct yaffs_obj *in); -+static void yaffs_invalidate_chunk_cache(struct yaffs_obj *object, -+ int chunk_id); -+ -+static int yaffs_find_chunk_in_file(struct yaffs_obj *in, int inode_chunk, -+ struct yaffs_ext_tags *tags); -+ -+static int yaffs_verify_chunk_written(struct yaffs_dev *dev, -+ int nand_chunk, -+ const u8 * data, -+ struct yaffs_ext_tags *tags); -+ -+static void yaffs_load_name_from_oh(struct yaffs_dev *dev, YCHAR * name, -+ const YCHAR * oh_name, int buff_size); -+static void yaffs_load_oh_from_name(struct yaffs_dev *dev, YCHAR * oh_name, -+ const YCHAR * name); -+ -+/* Function to calculate chunk and offset */ -+ -+static void yaffs_addr_to_chunk(struct yaffs_dev *dev, loff_t addr, -+ int *chunk_out, u32 * offset_out) -+{ -+ int chunk; -+ u32 offset; -+ -+ chunk = (u32) (addr >> dev->chunk_shift); -+ -+ if (dev->chunk_div == 1) { -+ /* easy power of 2 case */ -+ offset = (u32) (addr & dev->chunk_mask); -+ } else { -+ /* Non power-of-2 case */ -+ -+ loff_t chunk_base; -+ -+ chunk /= dev->chunk_div; -+ -+ chunk_base = ((loff_t) chunk) * dev->data_bytes_per_chunk; -+ offset = (u32) (addr - chunk_base); -+ } -+ -+ *chunk_out = chunk; -+ *offset_out = offset; -+} -+ -+/* Function to return the number of shifts for a power of 2 greater than or -+ * equal to the given number -+ * Note we don't try to cater for all possible numbers and this does not have to -+ * be hellishly efficient. -+ */ -+ -+static u32 calc_shifts_ceiling(u32 x) -+{ -+ int extra_bits; -+ int shifts; -+ -+ shifts = extra_bits = 0; -+ -+ while (x > 1) { -+ if (x & 1) -+ extra_bits++; -+ x >>= 1; -+ shifts++; -+ } -+ -+ if (extra_bits) -+ shifts++; -+ -+ return shifts; -+} -+ -+/* Function to return the number of shifts to get a 1 in bit 0 -+ */ -+ -+static u32 calc_shifts(u32 x) -+{ -+ u32 shifts; -+ -+ shifts = 0; -+ -+ if (!x) -+ return 0; -+ -+ while (!(x & 1)) { -+ x >>= 1; -+ shifts++; -+ } -+ -+ return shifts; -+} -+ -+/* -+ * Temporary buffer manipulations. -+ */ -+ -+static int yaffs_init_tmp_buffers(struct yaffs_dev *dev) -+{ -+ int i; -+ u8 *buf = (u8 *) 1; -+ -+ memset(dev->temp_buffer, 0, sizeof(dev->temp_buffer)); -+ -+ for (i = 0; buf && i < YAFFS_N_TEMP_BUFFERS; i++) { -+ dev->temp_buffer[i].line = 0; /* not in use */ -+ dev->temp_buffer[i].buffer = buf = -+ YMALLOC_DMA(dev->param.total_bytes_per_chunk); -+ } -+ -+ return buf ? YAFFS_OK : YAFFS_FAIL; -+} -+ -+u8 *yaffs_get_temp_buffer(struct yaffs_dev * dev, int line_no) -+{ -+ int i, j; -+ -+ dev->temp_in_use++; -+ if (dev->temp_in_use > dev->max_temp) -+ dev->max_temp = dev->temp_in_use; -+ -+ for (i = 0; i < YAFFS_N_TEMP_BUFFERS; i++) { -+ if (dev->temp_buffer[i].line == 0) { -+ dev->temp_buffer[i].line = line_no; -+ if ((i + 1) > dev->max_temp) { -+ dev->max_temp = i + 1; -+ for (j = 0; j <= i; j++) -+ dev->temp_buffer[j].max_line = -+ dev->temp_buffer[j].line; -+ } -+ -+ return dev->temp_buffer[i].buffer; -+ } -+ } -+ -+ T(YAFFS_TRACE_BUFFERS, -+ (TSTR("Out of temp buffers at line %d, other held by lines:"), -+ line_no)); -+ for (i = 0; i < YAFFS_N_TEMP_BUFFERS; i++) -+ T(YAFFS_TRACE_BUFFERS, -+ (TSTR(" %d "), dev->temp_buffer[i].line)); -+ -+ T(YAFFS_TRACE_BUFFERS, (TSTR(" " TENDSTR))); -+ -+ /* -+ * If we got here then we have to allocate an unmanaged one -+ * This is not good. -+ */ -+ -+ dev->unmanaged_buffer_allocs++; -+ return YMALLOC(dev->data_bytes_per_chunk); -+ -+} -+ -+void yaffs_release_temp_buffer(struct yaffs_dev *dev, u8 * buffer, int line_no) -+{ -+ int i; -+ -+ dev->temp_in_use--; -+ -+ for (i = 0; i < YAFFS_N_TEMP_BUFFERS; i++) { -+ if (dev->temp_buffer[i].buffer == buffer) { -+ dev->temp_buffer[i].line = 0; -+ return; -+ } -+ } -+ -+ if (buffer) { -+ /* assume it is an unmanaged one. */ -+ T(YAFFS_TRACE_BUFFERS, -+ (TSTR("Releasing unmanaged temp buffer in line %d" TENDSTR), -+ line_no)); -+ YFREE(buffer); -+ dev->unmanaged_buffer_deallocs++; -+ } -+ -+} -+ -+/* -+ * Determine if we have a managed buffer. -+ */ -+int yaffs_is_managed_tmp_buffer(struct yaffs_dev *dev, const u8 * buffer) -+{ -+ int i; -+ -+ for (i = 0; i < YAFFS_N_TEMP_BUFFERS; i++) { -+ if (dev->temp_buffer[i].buffer == buffer) -+ return 1; -+ } -+ -+ for (i = 0; i < dev->param.n_caches; i++) { -+ if (dev->cache[i].data == buffer) -+ return 1; -+ } -+ -+ if (buffer == dev->checkpt_buffer) -+ return 1; -+ -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR("yaffs: unmaged buffer detected.\n" TENDSTR))); -+ return 0; -+} -+ -+/* -+ * Verification code -+ */ -+ -+/* -+ * Simple hash function. Needs to have a reasonable spread -+ */ -+ -+static Y_INLINE int yaffs_hash_fn(int n) -+{ -+ n = abs(n); -+ return n % YAFFS_NOBJECT_BUCKETS; -+} -+ -+/* -+ * Access functions to useful fake objects. -+ * Note that root might have a presence in NAND if permissions are set. -+ */ -+ -+struct yaffs_obj *yaffs_root(struct yaffs_dev *dev) -+{ -+ return dev->root_dir; -+} -+ -+struct yaffs_obj *yaffs_lost_n_found(struct yaffs_dev *dev) -+{ -+ return dev->lost_n_found; -+} -+ -+/* -+ * Erased NAND checking functions -+ */ -+ -+int yaffs_check_ff(u8 * buffer, int n_bytes) -+{ -+ /* Horrible, slow implementation */ -+ while (n_bytes--) { -+ if (*buffer != 0xFF) -+ return 0; -+ buffer++; -+ } -+ return 1; -+} -+ -+static int yaffs_check_chunk_erased(struct yaffs_dev *dev, int nand_chunk) -+{ -+ int retval = YAFFS_OK; -+ u8 *data = yaffs_get_temp_buffer(dev, __LINE__); -+ struct yaffs_ext_tags tags; -+ int result; -+ -+ result = yaffs_rd_chunk_tags_nand(dev, nand_chunk, data, &tags); -+ -+ if (tags.ecc_result > YAFFS_ECC_RESULT_NO_ERROR) -+ retval = YAFFS_FAIL; -+ -+ if (!yaffs_check_ff(data, dev->data_bytes_per_chunk) || tags.chunk_used) { -+ T(YAFFS_TRACE_NANDACCESS, -+ (TSTR("Chunk %d not erased" TENDSTR), nand_chunk)); -+ retval = YAFFS_FAIL; -+ } -+ -+ yaffs_release_temp_buffer(dev, data, __LINE__); -+ -+ return retval; -+ -+} -+ -+static int yaffs_verify_chunk_written(struct yaffs_dev *dev, -+ int nand_chunk, -+ const u8 * data, -+ struct yaffs_ext_tags *tags) -+{ -+ int retval = YAFFS_OK; -+ struct yaffs_ext_tags temp_tags; -+ u8 *buffer = yaffs_get_temp_buffer(dev, __LINE__); -+ int result; -+ -+ result = yaffs_rd_chunk_tags_nand(dev, nand_chunk, buffer, &temp_tags); -+ if (memcmp(buffer, data, dev->data_bytes_per_chunk) || -+ temp_tags.obj_id != tags->obj_id || -+ temp_tags.chunk_id != tags->chunk_id || -+ temp_tags.n_bytes != tags->n_bytes) -+ retval = YAFFS_FAIL; -+ -+ yaffs_release_temp_buffer(dev, buffer, __LINE__); -+ -+ return retval; -+} -+ -+static int yaffs_write_new_chunk(struct yaffs_dev *dev, -+ const u8 * data, -+ struct yaffs_ext_tags *tags, int use_reserver) -+{ -+ int attempts = 0; -+ int write_ok = 0; -+ int chunk; -+ -+ yaffs2_checkpt_invalidate(dev); -+ -+ do { -+ struct yaffs_block_info *bi = 0; -+ int erased_ok = 0; -+ -+ chunk = yaffs_alloc_chunk(dev, use_reserver, &bi); -+ if (chunk < 0) { -+ /* no space */ -+ break; -+ } -+ -+ /* First check this chunk is erased, if it needs -+ * checking. The checking policy (unless forced -+ * always on) is as follows: -+ * -+ * Check the first page we try to write in a block. -+ * If the check passes then we don't need to check any -+ * more. If the check fails, we check again... -+ * If the block has been erased, we don't need to check. -+ * -+ * However, if the block has been prioritised for gc, -+ * then we think there might be something odd about -+ * this block and stop using it. -+ * -+ * Rationale: We should only ever see chunks that have -+ * not been erased if there was a partially written -+ * chunk due to power loss. This checking policy should -+ * catch that case with very few checks and thus save a -+ * lot of checks that are most likely not needed. -+ * -+ * Mods to the above -+ * If an erase check fails or the write fails we skip the -+ * rest of the block. -+ */ -+ -+ /* let's give it a try */ -+ attempts++; -+ -+ if (dev->param.always_check_erased) -+ bi->skip_erased_check = 0; -+ -+ if (!bi->skip_erased_check) { -+ erased_ok = yaffs_check_chunk_erased(dev, chunk); -+ if (erased_ok != YAFFS_OK) { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR("**>> yaffs chunk %d was not erased" -+ TENDSTR), chunk)); -+ -+ /* If not erased, delete this one, -+ * skip rest of block and -+ * try another chunk */ -+ yaffs_chunk_del(dev, chunk, 1, __LINE__); -+ yaffs_skip_rest_of_block(dev); -+ continue; -+ } -+ } -+ -+ write_ok = yaffs_wr_chunk_tags_nand(dev, chunk, data, tags); -+ -+ if (!bi->skip_erased_check) -+ write_ok = -+ yaffs_verify_chunk_written(dev, chunk, data, tags); -+ -+ if (write_ok != YAFFS_OK) { -+ /* Clean up aborted write, skip to next block and -+ * try another chunk */ -+ yaffs_handle_chunk_wr_error(dev, chunk, erased_ok); -+ continue; -+ } -+ -+ bi->skip_erased_check = 1; -+ -+ /* Copy the data into the robustification buffer */ -+ yaffs_handle_chunk_wr_ok(dev, chunk, data, tags); -+ -+ } while (write_ok != YAFFS_OK && -+ (yaffs_wr_attempts <= 0 || attempts <= yaffs_wr_attempts)); -+ -+ if (!write_ok) -+ chunk = -1; -+ -+ if (attempts > 1) { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR("**>> yaffs write required %d attempts" TENDSTR), -+ attempts)); -+ -+ dev->n_retired_writes += (attempts - 1); -+ } -+ -+ return chunk; -+} -+ -+/* -+ * Block retiring for handling a broken block. -+ */ -+ -+static void yaffs_retire_block(struct yaffs_dev *dev, int flash_block) -+{ -+ struct yaffs_block_info *bi = yaffs_get_block_info(dev, flash_block); -+ -+ yaffs2_checkpt_invalidate(dev); -+ -+ yaffs2_clear_oldest_dirty_seq(dev, bi); -+ -+ if (yaffs_mark_bad(dev, flash_block) != YAFFS_OK) { -+ if (yaffs_erase_block(dev, flash_block) != YAFFS_OK) { -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR -+ ("yaffs: Failed to mark bad and erase block %d" -+ TENDSTR), flash_block)); -+ } else { -+ struct yaffs_ext_tags tags; -+ int chunk_id = -+ flash_block * dev->param.chunks_per_block; -+ -+ u8 *buffer = yaffs_get_temp_buffer(dev, __LINE__); -+ -+ memset(buffer, 0xff, dev->data_bytes_per_chunk); -+ yaffs_init_tags(&tags); -+ tags.seq_number = YAFFS_SEQUENCE_BAD_BLOCK; -+ if (dev->param.write_chunk_tags_fn(dev, chunk_id - -+ dev->chunk_offset, -+ buffer, -+ &tags) != YAFFS_OK) -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR -+ ("yaffs: Failed to " -+ TCONT("write bad block marker to block %d") -+ TENDSTR), flash_block)); -+ -+ yaffs_release_temp_buffer(dev, buffer, __LINE__); -+ } -+ } -+ -+ bi->block_state = YAFFS_BLOCK_STATE_DEAD; -+ bi->gc_prioritise = 0; -+ bi->needs_retiring = 0; -+ -+ dev->n_retired_blocks++; -+} -+ -+/* -+ * Functions for robustisizing TODO -+ * -+ */ -+ -+static void yaffs_handle_chunk_wr_ok(struct yaffs_dev *dev, int nand_chunk, -+ const u8 * data, -+ const struct yaffs_ext_tags *tags) -+{ -+ dev = dev; -+ nand_chunk = nand_chunk; -+ data = data; -+ tags = tags; -+} -+ -+static void yaffs_handle_chunk_update(struct yaffs_dev *dev, int nand_chunk, -+ const struct yaffs_ext_tags *tags) -+{ -+ dev = dev; -+ nand_chunk = nand_chunk; -+ tags = tags; -+} -+ -+void yaffs_handle_chunk_error(struct yaffs_dev *dev, -+ struct yaffs_block_info *bi) -+{ -+ if (!bi->gc_prioritise) { -+ bi->gc_prioritise = 1; -+ dev->has_pending_prioritised_gc = 1; -+ bi->chunk_error_strikes++; -+ -+ if (bi->chunk_error_strikes > 3) { -+ bi->needs_retiring = 1; /* Too many stikes, so retire this */ -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR("yaffs: Block struck out" TENDSTR))); -+ -+ } -+ } -+} -+ -+static void yaffs_handle_chunk_wr_error(struct yaffs_dev *dev, int nand_chunk, -+ int erased_ok) -+{ -+ int flash_block = nand_chunk / dev->param.chunks_per_block; -+ struct yaffs_block_info *bi = yaffs_get_block_info(dev, flash_block); -+ -+ yaffs_handle_chunk_error(dev, bi); -+ -+ if (erased_ok) { -+ /* Was an actual write failure, so mark the block for retirement */ -+ bi->needs_retiring = 1; -+ T(YAFFS_TRACE_ERROR | YAFFS_TRACE_BAD_BLOCKS, -+ (TSTR("**>> Block %d needs retiring" TENDSTR), flash_block)); -+ } -+ -+ /* Delete the chunk */ -+ yaffs_chunk_del(dev, nand_chunk, 1, __LINE__); -+ yaffs_skip_rest_of_block(dev); -+} -+ -+/*---------------- Name handling functions ------------*/ -+ -+static u16 yaffs_calc_name_sum(const YCHAR * name) -+{ -+ u16 sum = 0; -+ u16 i = 1; -+ -+ const YUCHAR *bname = (const YUCHAR *)name; -+ if (bname) { -+ while ((*bname) && (i < (YAFFS_MAX_NAME_LENGTH / 2))) { -+ -+ /* 0x1f mask is case insensitive */ -+ sum += ((*bname) & 0x1f) * i; -+ i++; -+ bname++; -+ } -+ } -+ return sum; -+} -+ -+void yaffs_set_obj_name(struct yaffs_obj *obj, const YCHAR * name) -+{ -+#ifndef CONFIG_YAFFS_NO_SHORT_NAMES -+ memset(obj->short_name, 0, sizeof(obj->short_name)); -+ if (name && -+ yaffs_strnlen(name, YAFFS_SHORT_NAME_LENGTH + 1) <= -+ YAFFS_SHORT_NAME_LENGTH) -+ yaffs_strcpy(obj->short_name, name); -+ else -+ obj->short_name[0] = _Y('\0'); -+#endif -+ obj->sum = yaffs_calc_name_sum(name); -+} -+ -+void yaffs_set_obj_name_from_oh(struct yaffs_obj *obj, -+ const struct yaffs_obj_hdr *oh) -+{ -+#ifdef CONFIG_YAFFS_AUTO_UNICODE -+ YCHAR tmp_name[YAFFS_MAX_NAME_LENGTH + 1]; -+ memset(tmp_name, 0, sizeof(tmp_name)); -+ yaffs_load_name_from_oh(obj->my_dev, tmp_name, oh->name, -+ YAFFS_MAX_NAME_LENGTH + 1); -+ yaffs_set_obj_name(obj, tmp_name); -+#else -+ yaffs_set_obj_name(obj, oh->name); -+#endif -+} -+ -+/*-------------------- TNODES ------------------- -+ -+ * List of spare tnodes -+ * The list is hooked together using the first pointer -+ * in the tnode. -+ */ -+ -+struct yaffs_tnode *yaffs_get_tnode(struct yaffs_dev *dev) -+{ -+ struct yaffs_tnode *tn = yaffs_alloc_raw_tnode(dev); -+ if (tn) { -+ memset(tn, 0, dev->tnode_size); -+ dev->n_tnodes++; -+ } -+ -+ dev->checkpoint_blocks_required = 0; /* force recalculation */ -+ -+ return tn; -+} -+ -+/* FreeTnode frees up a tnode and puts it back on the free list */ -+static void yaffs_free_tnode(struct yaffs_dev *dev, struct yaffs_tnode *tn) -+{ -+ yaffs_free_raw_tnode(dev, tn); -+ dev->n_tnodes--; -+ dev->checkpoint_blocks_required = 0; /* force recalculation */ -+} -+ -+static void yaffs_deinit_tnodes_and_objs(struct yaffs_dev *dev) -+{ -+ yaffs_deinit_raw_tnodes_and_objs(dev); -+ dev->n_obj = 0; -+ dev->n_tnodes = 0; -+} -+ -+void yaffs_load_tnode_0(struct yaffs_dev *dev, struct yaffs_tnode *tn, -+ unsigned pos, unsigned val) -+{ -+ u32 *map = (u32 *) tn; -+ u32 bit_in_map; -+ u32 bit_in_word; -+ u32 word_in_map; -+ u32 mask; -+ -+ pos &= YAFFS_TNODES_LEVEL0_MASK; -+ val >>= dev->chunk_grp_bits; -+ -+ bit_in_map = pos * dev->tnode_width; -+ word_in_map = bit_in_map / 32; -+ bit_in_word = bit_in_map & (32 - 1); -+ -+ mask = dev->tnode_mask << bit_in_word; -+ -+ map[word_in_map] &= ~mask; -+ map[word_in_map] |= (mask & (val << bit_in_word)); -+ -+ if (dev->tnode_width > (32 - bit_in_word)) { -+ bit_in_word = (32 - bit_in_word); -+ word_in_map++;; -+ mask = -+ dev->tnode_mask >> ( /*dev->tnode_width - */ bit_in_word); -+ map[word_in_map] &= ~mask; -+ map[word_in_map] |= (mask & (val >> bit_in_word)); -+ } -+} -+ -+u32 yaffs_get_group_base(struct yaffs_dev *dev, struct yaffs_tnode *tn, -+ unsigned pos) -+{ -+ u32 *map = (u32 *) tn; -+ u32 bit_in_map; -+ u32 bit_in_word; -+ u32 word_in_map; -+ u32 val; -+ -+ pos &= YAFFS_TNODES_LEVEL0_MASK; -+ -+ bit_in_map = pos * dev->tnode_width; -+ word_in_map = bit_in_map / 32; -+ bit_in_word = bit_in_map & (32 - 1); -+ -+ val = map[word_in_map] >> bit_in_word; -+ -+ if (dev->tnode_width > (32 - bit_in_word)) { -+ bit_in_word = (32 - bit_in_word); -+ word_in_map++;; -+ val |= (map[word_in_map] << bit_in_word); -+ } -+ -+ val &= dev->tnode_mask; -+ val <<= dev->chunk_grp_bits; -+ -+ return val; -+} -+ -+/* ------------------- End of individual tnode manipulation -----------------*/ -+ -+/* ---------Functions to manipulate the look-up tree (made up of tnodes) ------ -+ * The look up tree is represented by the top tnode and the number of top_level -+ * in the tree. 0 means only the level 0 tnode is in the tree. -+ */ -+ -+/* FindLevel0Tnode finds the level 0 tnode, if one exists. */ -+struct yaffs_tnode *yaffs_find_tnode_0(struct yaffs_dev *dev, -+ struct yaffs_file_var *file_struct, -+ u32 chunk_id) -+{ -+ struct yaffs_tnode *tn = file_struct->top; -+ u32 i; -+ int required_depth; -+ int level = file_struct->top_level; -+ -+ dev = dev; -+ -+ /* Check sane level and chunk Id */ -+ if (level < 0 || level > YAFFS_TNODES_MAX_LEVEL) -+ return NULL; -+ -+ if (chunk_id > YAFFS_MAX_CHUNK_ID) -+ return NULL; -+ -+ /* First check we're tall enough (ie enough top_level) */ -+ -+ i = chunk_id >> YAFFS_TNODES_LEVEL0_BITS; -+ required_depth = 0; -+ while (i) { -+ i >>= YAFFS_TNODES_INTERNAL_BITS; -+ required_depth++; -+ } -+ -+ if (required_depth > file_struct->top_level) -+ return NULL; /* Not tall enough, so we can't find it */ -+ -+ /* Traverse down to level 0 */ -+ while (level > 0 && tn) { -+ tn = tn->internal[(chunk_id >> -+ (YAFFS_TNODES_LEVEL0_BITS + -+ (level - 1) * -+ YAFFS_TNODES_INTERNAL_BITS)) & -+ YAFFS_TNODES_INTERNAL_MASK]; -+ level--; -+ } -+ -+ return tn; -+} -+ -+/* AddOrFindLevel0Tnode finds the level 0 tnode if it exists, otherwise first expands the tree. -+ * This happens in two steps: -+ * 1. If the tree isn't tall enough, then make it taller. -+ * 2. Scan down the tree towards the level 0 tnode adding tnodes if required. -+ * -+ * Used when modifying the tree. -+ * -+ * If the tn argument is NULL, then a fresh tnode will be added otherwise the specified tn will -+ * be plugged into the ttree. -+ */ -+ -+struct yaffs_tnode *yaffs_add_find_tnode_0(struct yaffs_dev *dev, -+ struct yaffs_file_var *file_struct, -+ u32 chunk_id, -+ struct yaffs_tnode *passed_tn) -+{ -+ int required_depth; -+ int i; -+ int l; -+ struct yaffs_tnode *tn; -+ -+ u32 x; -+ -+ /* Check sane level and page Id */ -+ if (file_struct->top_level < 0 -+ || file_struct->top_level > YAFFS_TNODES_MAX_LEVEL) -+ return NULL; -+ -+ if (chunk_id > YAFFS_MAX_CHUNK_ID) -+ return NULL; -+ -+ /* First check we're tall enough (ie enough top_level) */ -+ -+ x = chunk_id >> YAFFS_TNODES_LEVEL0_BITS; -+ required_depth = 0; -+ while (x) { -+ x >>= YAFFS_TNODES_INTERNAL_BITS; -+ required_depth++; -+ } -+ -+ if (required_depth > file_struct->top_level) { -+ /* Not tall enough, gotta make the tree taller */ -+ for (i = file_struct->top_level; i < required_depth; i++) { -+ -+ tn = yaffs_get_tnode(dev); -+ -+ if (tn) { -+ tn->internal[0] = file_struct->top; -+ file_struct->top = tn; -+ file_struct->top_level++; -+ } else { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR("yaffs: no more tnodes" TENDSTR))); -+ return NULL; -+ } -+ } -+ } -+ -+ /* Traverse down to level 0, adding anything we need */ -+ -+ l = file_struct->top_level; -+ tn = file_struct->top; -+ -+ if (l > 0) { -+ while (l > 0 && tn) { -+ x = (chunk_id >> -+ (YAFFS_TNODES_LEVEL0_BITS + -+ (l - 1) * YAFFS_TNODES_INTERNAL_BITS)) & -+ YAFFS_TNODES_INTERNAL_MASK; -+ -+ if ((l > 1) && !tn->internal[x]) { -+ /* Add missing non-level-zero tnode */ -+ tn->internal[x] = yaffs_get_tnode(dev); -+ if (!tn->internal[x]) -+ return NULL; -+ } else if (l == 1) { -+ /* Looking from level 1 at level 0 */ -+ if (passed_tn) { -+ /* If we already have one, then release it. */ -+ if (tn->internal[x]) -+ yaffs_free_tnode(dev, -+ tn-> -+ internal[x]); -+ tn->internal[x] = passed_tn; -+ -+ } else if (!tn->internal[x]) { -+ /* Don't have one, none passed in */ -+ tn->internal[x] = yaffs_get_tnode(dev); -+ if (!tn->internal[x]) -+ return NULL; -+ } -+ } -+ -+ tn = tn->internal[x]; -+ l--; -+ } -+ } else { -+ /* top is level 0 */ -+ if (passed_tn) { -+ memcpy(tn, passed_tn, -+ (dev->tnode_width * YAFFS_NTNODES_LEVEL0) / 8); -+ yaffs_free_tnode(dev, passed_tn); -+ } -+ } -+ -+ return tn; -+} -+ -+static int yaffs_find_chunk_in_group(struct yaffs_dev *dev, int the_chunk, -+ struct yaffs_ext_tags *tags, int obj_id, -+ int inode_chunk) -+{ -+ int j; -+ -+ for (j = 0; the_chunk && j < dev->chunk_grp_size; j++) { -+ if (yaffs_check_chunk_bit -+ (dev, the_chunk / dev->param.chunks_per_block, -+ the_chunk % dev->param.chunks_per_block)) { -+ -+ if (dev->chunk_grp_size == 1) -+ return the_chunk; -+ else { -+ yaffs_rd_chunk_tags_nand(dev, the_chunk, NULL, -+ tags); -+ if (yaffs_tags_match(tags, obj_id, inode_chunk)) { -+ /* found it; */ -+ return the_chunk; -+ } -+ } -+ } -+ the_chunk++; -+ } -+ return -1; -+} -+ -+static void yaffs_soft_del_chunk(struct yaffs_dev *dev, int chunk) -+{ -+ struct yaffs_block_info *the_block; -+ unsigned block_no; -+ -+ T(YAFFS_TRACE_DELETION, (TSTR("soft delete chunk %d" TENDSTR), chunk)); -+ -+ block_no = chunk / dev->param.chunks_per_block; -+ the_block = yaffs_get_block_info(dev, block_no); -+ if (the_block) { -+ the_block->soft_del_pages++; -+ dev->n_free_chunks++; -+ yaffs2_update_oldest_dirty_seq(dev, block_no, the_block); -+ } -+} -+ -+/* SoftDeleteWorker scans backwards through the tnode tree and soft deletes all the chunks in the file. -+ * All soft deleting does is increment the block's softdelete count and pulls the chunk out -+ * of the tnode. -+ * Thus, essentially this is the same as DeleteWorker except that the chunks are soft deleted. -+ */ -+ -+static int yaffs_soft_del_worker(struct yaffs_obj *in, struct yaffs_tnode *tn, -+ u32 level, int chunk_offset) -+{ -+ int i; -+ int the_chunk; -+ int all_done = 1; -+ struct yaffs_dev *dev = in->my_dev; -+ -+ if (tn) { -+ if (level > 0) { -+ -+ for (i = YAFFS_NTNODES_INTERNAL - 1; all_done && i >= 0; -+ i--) { -+ if (tn->internal[i]) { -+ all_done = -+ yaffs_soft_del_worker(in, -+ tn->internal -+ [i], -+ level - 1, -+ (chunk_offset -+ << -+ YAFFS_TNODES_INTERNAL_BITS) -+ + i); -+ if (all_done) { -+ yaffs_free_tnode(dev, -+ tn->internal -+ [i]); -+ tn->internal[i] = NULL; -+ } else { -+ /* Hoosterman... how could this happen? */ -+ } -+ } -+ } -+ return (all_done) ? 1 : 0; -+ } else if (level == 0) { -+ -+ for (i = YAFFS_NTNODES_LEVEL0 - 1; i >= 0; i--) { -+ the_chunk = yaffs_get_group_base(dev, tn, i); -+ if (the_chunk) { -+ /* Note this does not find the real chunk, only the chunk group. -+ * We make an assumption that a chunk group is not larger than -+ * a block. -+ */ -+ yaffs_soft_del_chunk(dev, the_chunk); -+ yaffs_load_tnode_0(dev, tn, i, 0); -+ } -+ -+ } -+ return 1; -+ -+ } -+ -+ } -+ -+ return 1; -+ -+} -+ -+static void yaffs_soft_del_file(struct yaffs_obj *obj) -+{ -+ if (obj->deleted && -+ obj->variant_type == YAFFS_OBJECT_TYPE_FILE && !obj->soft_del) { -+ if (obj->n_data_chunks <= 0) { -+ /* Empty file with no duplicate object headers, just delete it immediately */ -+ yaffs_free_tnode(obj->my_dev, -+ obj->variant.file_variant.top); -+ obj->variant.file_variant.top = NULL; -+ T(YAFFS_TRACE_TRACING, -+ (TSTR("yaffs: Deleting empty file %d" TENDSTR), -+ obj->obj_id)); -+ yaffs_generic_obj_del(obj); -+ } else { -+ yaffs_soft_del_worker(obj, -+ obj->variant.file_variant.top, -+ obj->variant. -+ file_variant.top_level, 0); -+ obj->soft_del = 1; -+ } -+ } -+} -+ -+/* Pruning removes any part of the file structure tree that is beyond the -+ * bounds of the file (ie that does not point to chunks). -+ * -+ * A file should only get pruned when its size is reduced. -+ * -+ * Before pruning, the chunks must be pulled from the tree and the -+ * level 0 tnode entries must be zeroed out. -+ * Could also use this for file deletion, but that's probably better handled -+ * by a special case. -+ * -+ * This function is recursive. For levels > 0 the function is called again on -+ * any sub-tree. For level == 0 we just check if the sub-tree has data. -+ * If there is no data in a subtree then it is pruned. -+ */ -+ -+static struct yaffs_tnode *yaffs_prune_worker(struct yaffs_dev *dev, -+ struct yaffs_tnode *tn, u32 level, -+ int del0) -+{ -+ int i; -+ int has_data; -+ -+ if (tn) { -+ has_data = 0; -+ -+ if (level > 0) { -+ for (i = 0; i < YAFFS_NTNODES_INTERNAL; i++) { -+ if (tn->internal[i]) { -+ tn->internal[i] = -+ yaffs_prune_worker(dev, -+ tn->internal[i], -+ level - 1, -+ (i == -+ 0) ? del0 : 1); -+ } -+ -+ if (tn->internal[i]) -+ has_data++; -+ } -+ } else { -+ int tnode_size_u32 = dev->tnode_size / sizeof(u32); -+ u32 *map = (u32 *) tn; -+ -+ for (i = 0; !has_data && i < tnode_size_u32; i++) { -+ if (map[i]) -+ has_data++; -+ } -+ } -+ -+ if (has_data == 0 && del0) { -+ /* Free and return NULL */ -+ -+ yaffs_free_tnode(dev, tn); -+ tn = NULL; -+ } -+ -+ } -+ -+ return tn; -+ -+} -+ -+static int yaffs_prune_tree(struct yaffs_dev *dev, -+ struct yaffs_file_var *file_struct) -+{ -+ int i; -+ int has_data; -+ int done = 0; -+ struct yaffs_tnode *tn; -+ -+ if (file_struct->top_level > 0) { -+ file_struct->top = -+ yaffs_prune_worker(dev, file_struct->top, -+ file_struct->top_level, 0); -+ -+ /* Now we have a tree with all the non-zero branches NULL but the height -+ * is the same as it was. -+ * Let's see if we can trim internal tnodes to shorten the tree. -+ * We can do this if only the 0th element in the tnode is in use -+ * (ie all the non-zero are NULL) -+ */ -+ -+ while (file_struct->top_level && !done) { -+ tn = file_struct->top; -+ -+ has_data = 0; -+ for (i = 1; i < YAFFS_NTNODES_INTERNAL; i++) { -+ if (tn->internal[i]) -+ has_data++; -+ } -+ -+ if (!has_data) { -+ file_struct->top = tn->internal[0]; -+ file_struct->top_level--; -+ yaffs_free_tnode(dev, tn); -+ } else { -+ done = 1; -+ } -+ } -+ } -+ -+ return YAFFS_OK; -+} -+ -+/*-------------------- End of File Structure functions.-------------------*/ -+ -+/* AllocateEmptyObject gets us a clean Object. Tries to make allocate more if we run out */ -+static struct yaffs_obj *yaffs_alloc_empty_obj(struct yaffs_dev *dev) -+{ -+ struct yaffs_obj *obj = yaffs_alloc_raw_obj(dev); -+ -+ if (obj) { -+ dev->n_obj++; -+ -+ /* Now sweeten it up... */ -+ -+ memset(obj, 0, sizeof(struct yaffs_obj)); -+ obj->being_created = 1; -+ -+ obj->my_dev = dev; -+ obj->hdr_chunk = 0; -+ obj->variant_type = YAFFS_OBJECT_TYPE_UNKNOWN; -+ INIT_LIST_HEAD(&(obj->hard_links)); -+ INIT_LIST_HEAD(&(obj->hash_link)); -+ INIT_LIST_HEAD(&obj->siblings); -+ -+ /* Now make the directory sane */ -+ if (dev->root_dir) { -+ obj->parent = dev->root_dir; -+ list_add(&(obj->siblings), -+ &dev->root_dir->variant.dir_variant.children); -+ } -+ -+ /* Add it to the lost and found directory. -+ * NB Can't put root or lost-n-found in lost-n-found so -+ * check if lost-n-found exists first -+ */ -+ if (dev->lost_n_found) -+ yaffs_add_obj_to_dir(dev->lost_n_found, obj); -+ -+ obj->being_created = 0; -+ } -+ -+ dev->checkpoint_blocks_required = 0; /* force recalculation */ -+ -+ return obj; -+} -+ -+static struct yaffs_obj *yaffs_create_fake_dir(struct yaffs_dev *dev, -+ int number, u32 mode) -+{ -+ -+ struct yaffs_obj *obj = -+ yaffs_new_obj(dev, number, YAFFS_OBJECT_TYPE_DIRECTORY); -+ if (obj) { -+ obj->fake = 1; /* it is fake so it might have no NAND presence... */ -+ obj->rename_allowed = 0; /* ... and we're not allowed to rename it... */ -+ obj->unlink_allowed = 0; /* ... or unlink it */ -+ obj->deleted = 0; -+ obj->unlinked = 0; -+ obj->yst_mode = mode; -+ obj->my_dev = dev; -+ obj->hdr_chunk = 0; /* Not a valid chunk. */ -+ } -+ -+ return obj; -+ -+} -+ -+static void yaffs_unhash_obj(struct yaffs_obj *obj) -+{ -+ int bucket; -+ struct yaffs_dev *dev = obj->my_dev; -+ -+ /* If it is still linked into the bucket list, free from the list */ -+ if (!list_empty(&obj->hash_link)) { -+ list_del_init(&obj->hash_link); -+ bucket = yaffs_hash_fn(obj->obj_id); -+ dev->obj_bucket[bucket].count--; -+ } -+} -+ -+/* FreeObject frees up a Object and puts it back on the free list */ -+static void yaffs_free_obj(struct yaffs_obj *obj) -+{ -+ struct yaffs_dev *dev = obj->my_dev; -+ -+ T(YAFFS_TRACE_OS, -+ (TSTR("FreeObject %p inode %p" TENDSTR), obj, obj->my_inode)); -+ -+ if (!obj) -+ YBUG(); -+ if (obj->parent) -+ YBUG(); -+ if (!list_empty(&obj->siblings)) -+ YBUG(); -+ -+ if (obj->my_inode) { -+ /* We're still hooked up to a cached inode. -+ * Don't delete now, but mark for later deletion -+ */ -+ obj->defered_free = 1; -+ return; -+ } -+ -+ yaffs_unhash_obj(obj); -+ -+ yaffs_free_raw_obj(dev, obj); -+ dev->n_obj--; -+ dev->checkpoint_blocks_required = 0; /* force recalculation */ -+} -+ -+void yaffs_handle_defered_free(struct yaffs_obj *obj) -+{ -+ if (obj->defered_free) -+ yaffs_free_obj(obj); -+} -+ -+static void yaffs_init_tnodes_and_objs(struct yaffs_dev *dev) -+{ -+ int i; -+ -+ dev->n_obj = 0; -+ dev->n_tnodes = 0; -+ -+ yaffs_init_raw_tnodes_and_objs(dev); -+ -+ for (i = 0; i < YAFFS_NOBJECT_BUCKETS; i++) { -+ INIT_LIST_HEAD(&dev->obj_bucket[i].list); -+ dev->obj_bucket[i].count = 0; -+ } -+} -+ -+static int yaffs_find_nice_bucket(struct yaffs_dev *dev) -+{ -+ int i; -+ int l = 999; -+ int lowest = 999999; -+ -+ /* Search for the shortest list or one that -+ * isn't too long. -+ */ -+ -+ for (i = 0; i < 10 && lowest > 4; i++) { -+ dev->bucket_finder++; -+ dev->bucket_finder %= YAFFS_NOBJECT_BUCKETS; -+ if (dev->obj_bucket[dev->bucket_finder].count < lowest) { -+ lowest = dev->obj_bucket[dev->bucket_finder].count; -+ l = dev->bucket_finder; -+ } -+ -+ } -+ -+ return l; -+} -+ -+static int yaffs_new_obj_id(struct yaffs_dev *dev) -+{ -+ int bucket = yaffs_find_nice_bucket(dev); -+ -+ /* Now find an object value that has not already been taken -+ * by scanning the list. -+ */ -+ -+ int found = 0; -+ struct list_head *i; -+ -+ u32 n = (u32) bucket; -+ -+ /* yaffs_check_obj_hash_sane(); */ -+ -+ while (!found) { -+ found = 1; -+ n += YAFFS_NOBJECT_BUCKETS; -+ if (1 || dev->obj_bucket[bucket].count > 0) { -+ list_for_each(i, &dev->obj_bucket[bucket].list) { -+ /* If there is already one in the list */ -+ if (i && list_entry(i, struct yaffs_obj, -+ hash_link)->obj_id == n) { -+ found = 0; -+ } -+ } -+ } -+ } -+ -+ return n; -+} -+ -+static void yaffs_hash_obj(struct yaffs_obj *in) -+{ -+ int bucket = yaffs_hash_fn(in->obj_id); -+ struct yaffs_dev *dev = in->my_dev; -+ -+ list_add(&in->hash_link, &dev->obj_bucket[bucket].list); -+ dev->obj_bucket[bucket].count++; -+} -+ -+struct yaffs_obj *yaffs_find_by_number(struct yaffs_dev *dev, u32 number) -+{ -+ int bucket = yaffs_hash_fn(number); -+ struct list_head *i; -+ struct yaffs_obj *in; -+ -+ list_for_each(i, &dev->obj_bucket[bucket].list) { -+ /* Look if it is in the list */ -+ if (i) { -+ in = list_entry(i, struct yaffs_obj, hash_link); -+ if (in->obj_id == number) { -+ -+ /* Don't tell the VFS about this one if it is defered free */ -+ if (in->defered_free) -+ return NULL; -+ -+ return in; -+ } -+ } -+ } -+ -+ return NULL; -+} -+ -+struct yaffs_obj *yaffs_new_obj(struct yaffs_dev *dev, int number, -+ enum yaffs_obj_type type) -+{ -+ struct yaffs_obj *the_obj = NULL; -+ struct yaffs_tnode *tn = NULL; -+ -+ if (number < 0) -+ number = yaffs_new_obj_id(dev); -+ -+ if (type == YAFFS_OBJECT_TYPE_FILE) { -+ tn = yaffs_get_tnode(dev); -+ if (!tn) -+ return NULL; -+ } -+ -+ the_obj = yaffs_alloc_empty_obj(dev); -+ if (!the_obj) { -+ if (tn) -+ yaffs_free_tnode(dev, tn); -+ return NULL; -+ } -+ -+ if (the_obj) { -+ the_obj->fake = 0; -+ the_obj->rename_allowed = 1; -+ the_obj->unlink_allowed = 1; -+ the_obj->obj_id = number; -+ yaffs_hash_obj(the_obj); -+ the_obj->variant_type = type; -+ yaffs_load_current_time(the_obj, 1, 1); -+ -+ switch (type) { -+ case YAFFS_OBJECT_TYPE_FILE: -+ the_obj->variant.file_variant.file_size = 0; -+ the_obj->variant.file_variant.scanned_size = 0; -+ the_obj->variant.file_variant.shrink_size = ~0; /* max */ -+ the_obj->variant.file_variant.top_level = 0; -+ the_obj->variant.file_variant.top = tn; -+ break; -+ case YAFFS_OBJECT_TYPE_DIRECTORY: -+ INIT_LIST_HEAD(&the_obj->variant.dir_variant.children); -+ INIT_LIST_HEAD(&the_obj->variant.dir_variant.dirty); -+ break; -+ case YAFFS_OBJECT_TYPE_SYMLINK: -+ case YAFFS_OBJECT_TYPE_HARDLINK: -+ case YAFFS_OBJECT_TYPE_SPECIAL: -+ /* No action required */ -+ break; -+ case YAFFS_OBJECT_TYPE_UNKNOWN: -+ /* todo this should not happen */ -+ break; -+ } -+ } -+ -+ return the_obj; -+} -+ -+struct yaffs_obj *yaffs_find_or_create_by_number(struct yaffs_dev *dev, -+ int number, -+ enum yaffs_obj_type type) -+{ -+ struct yaffs_obj *the_obj = NULL; -+ -+ if (number > 0) -+ the_obj = yaffs_find_by_number(dev, number); -+ -+ if (!the_obj) -+ the_obj = yaffs_new_obj(dev, number, type); -+ -+ return the_obj; -+ -+} -+ -+YCHAR *yaffs_clone_str(const YCHAR * str) -+{ -+ YCHAR *new_str = NULL; -+ int len; -+ -+ if (!str) -+ str = _Y(""); -+ -+ len = yaffs_strnlen(str, YAFFS_MAX_ALIAS_LENGTH); -+ new_str = YMALLOC((len + 1) * sizeof(YCHAR)); -+ if (new_str) { -+ yaffs_strncpy(new_str, str, len); -+ new_str[len] = 0; -+ } -+ return new_str; -+ -+} -+ -+/* -+ * Mknod (create) a new object. -+ * equiv_obj only has meaning for a hard link; -+ * alias_str only has meaning for a symlink. -+ * rdev only has meaning for devices (a subset of special objects) -+ */ -+ -+static struct yaffs_obj *yaffs_create_obj(enum yaffs_obj_type type, -+ struct yaffs_obj *parent, -+ const YCHAR * name, -+ u32 mode, -+ u32 uid, -+ u32 gid, -+ struct yaffs_obj *equiv_obj, -+ const YCHAR * alias_str, u32 rdev) -+{ -+ struct yaffs_obj *in; -+ YCHAR *str = NULL; -+ -+ struct yaffs_dev *dev = parent->my_dev; -+ -+ /* Check if the entry exists. If it does then fail the call since we don't want a dup. */ -+ if (yaffs_find_by_name(parent, name)) -+ return NULL; -+ -+ if (type == YAFFS_OBJECT_TYPE_SYMLINK) { -+ str = yaffs_clone_str(alias_str); -+ if (!str) -+ return NULL; -+ } -+ -+ in = yaffs_new_obj(dev, -1, type); -+ -+ if (!in) { -+ if (str) -+ YFREE(str); -+ return NULL; -+ } -+ -+ if (in) { -+ in->hdr_chunk = 0; -+ in->valid = 1; -+ in->variant_type = type; -+ -+ in->yst_mode = mode; -+ -+ yaffs_attribs_init(in, gid, uid, rdev); -+ -+ in->n_data_chunks = 0; -+ -+ yaffs_set_obj_name(in, name); -+ in->dirty = 1; -+ -+ yaffs_add_obj_to_dir(parent, in); -+ -+ in->my_dev = parent->my_dev; -+ -+ switch (type) { -+ case YAFFS_OBJECT_TYPE_SYMLINK: -+ in->variant.symlink_variant.alias = str; -+ break; -+ case YAFFS_OBJECT_TYPE_HARDLINK: -+ in->variant.hardlink_variant.equiv_obj = equiv_obj; -+ in->variant.hardlink_variant.equiv_id = -+ equiv_obj->obj_id; -+ list_add(&in->hard_links, &equiv_obj->hard_links); -+ break; -+ case YAFFS_OBJECT_TYPE_FILE: -+ case YAFFS_OBJECT_TYPE_DIRECTORY: -+ case YAFFS_OBJECT_TYPE_SPECIAL: -+ case YAFFS_OBJECT_TYPE_UNKNOWN: -+ /* do nothing */ -+ break; -+ } -+ -+ if (yaffs_update_oh(in, name, 0, 0, 0, NULL) < 0) { -+ /* Could not create the object header, fail the creation */ -+ yaffs_del_obj(in); -+ in = NULL; -+ } -+ -+ yaffs_update_parent(parent); -+ } -+ -+ return in; -+} -+ -+struct yaffs_obj *yaffs_create_file(struct yaffs_obj *parent, -+ const YCHAR * name, u32 mode, u32 uid, -+ u32 gid) -+{ -+ return yaffs_create_obj(YAFFS_OBJECT_TYPE_FILE, parent, name, mode, -+ uid, gid, NULL, NULL, 0); -+} -+ -+struct yaffs_obj *yaffs_create_dir(struct yaffs_obj *parent, const YCHAR * name, -+ u32 mode, u32 uid, u32 gid) -+{ -+ return yaffs_create_obj(YAFFS_OBJECT_TYPE_DIRECTORY, parent, name, -+ mode, uid, gid, NULL, NULL, 0); -+} -+ -+struct yaffs_obj *yaffs_create_special(struct yaffs_obj *parent, -+ const YCHAR * name, u32 mode, u32 uid, -+ u32 gid, u32 rdev) -+{ -+ return yaffs_create_obj(YAFFS_OBJECT_TYPE_SPECIAL, parent, name, mode, -+ uid, gid, NULL, NULL, rdev); -+} -+ -+struct yaffs_obj *yaffs_create_symlink(struct yaffs_obj *parent, -+ const YCHAR * name, u32 mode, u32 uid, -+ u32 gid, const YCHAR * alias) -+{ -+ return yaffs_create_obj(YAFFS_OBJECT_TYPE_SYMLINK, parent, name, mode, -+ uid, gid, NULL, alias, 0); -+} -+ -+/* yaffs_link_obj returns the object id of the equivalent object.*/ -+struct yaffs_obj *yaffs_link_obj(struct yaffs_obj *parent, const YCHAR * name, -+ struct yaffs_obj *equiv_obj) -+{ -+ /* Get the real object in case we were fed a hard link as an equivalent object */ -+ equiv_obj = yaffs_get_equivalent_obj(equiv_obj); -+ -+ if (yaffs_create_obj -+ (YAFFS_OBJECT_TYPE_HARDLINK, parent, name, 0, 0, 0, -+ equiv_obj, NULL, 0)) { -+ return equiv_obj; -+ } else { -+ return NULL; -+ } -+ -+} -+ -+static int yaffs_change_obj_name(struct yaffs_obj *obj, -+ struct yaffs_obj *new_dir, -+ const YCHAR * new_name, int force, int shadows) -+{ -+ int unlink_op; -+ int del_op; -+ -+ struct yaffs_obj *existing_target; -+ -+ if (new_dir == NULL) -+ new_dir = obj->parent; /* use the old directory */ -+ -+ if (new_dir->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) { -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR -+ ("tragedy: yaffs_change_obj_name: new_dir is not a directory" -+ TENDSTR))); -+ YBUG(); -+ } -+ -+ /* TODO: Do we need this different handling for YAFFS2 and YAFFS1?? */ -+ if (obj->my_dev->param.is_yaffs2) -+ unlink_op = (new_dir == obj->my_dev->unlinked_dir); -+ else -+ unlink_op = (new_dir == obj->my_dev->unlinked_dir -+ && obj->variant_type == YAFFS_OBJECT_TYPE_FILE); -+ -+ del_op = (new_dir == obj->my_dev->del_dir); -+ -+ existing_target = yaffs_find_by_name(new_dir, new_name); -+ -+ /* If the object is a file going into the unlinked directory, -+ * then it is OK to just stuff it in since duplicate names are allowed. -+ * else only proceed if the new name does not exist and if we're putting -+ * it into a directory. -+ */ -+ if ((unlink_op || -+ del_op || -+ force || -+ (shadows > 0) || -+ !existing_target) && -+ new_dir->variant_type == YAFFS_OBJECT_TYPE_DIRECTORY) { -+ yaffs_set_obj_name(obj, new_name); -+ obj->dirty = 1; -+ -+ yaffs_add_obj_to_dir(new_dir, obj); -+ -+ if (unlink_op) -+ obj->unlinked = 1; -+ -+ /* If it is a deletion then we mark it as a shrink for gc purposes. */ -+ if (yaffs_update_oh(obj, new_name, 0, del_op, shadows, NULL) >= -+ 0) -+ return YAFFS_OK; -+ } -+ -+ return YAFFS_FAIL; -+} -+ -+int yaffs_rename_obj(struct yaffs_obj *old_dir, const YCHAR * old_name, -+ struct yaffs_obj *new_dir, const YCHAR * new_name) -+{ -+ struct yaffs_obj *obj = NULL; -+ struct yaffs_obj *existing_target = NULL; -+ int force = 0; -+ int result; -+ struct yaffs_dev *dev; -+ -+ if (!old_dir || old_dir->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) -+ YBUG(); -+ if (!new_dir || new_dir->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) -+ YBUG(); -+ -+ dev = old_dir->my_dev; -+ -+#ifdef CONFIG_YAFFS_CASE_INSENSITIVE -+ /* Special case for case insemsitive systems. -+ * While look-up is case insensitive, the name isn't. -+ * Therefore we might want to change x.txt to X.txt -+ */ -+ if (old_dir == new_dir && yaffs_strcmp(old_name, new_name) == 0) -+ force = 1; -+#endif -+ -+ if (yaffs_strnlen(new_name, YAFFS_MAX_NAME_LENGTH + 1) > -+ YAFFS_MAX_NAME_LENGTH) -+ /* ENAMETOOLONG */ -+ return YAFFS_FAIL; -+ -+ obj = yaffs_find_by_name(old_dir, old_name); -+ -+ if (obj && obj->rename_allowed) { -+ -+ /* Now do the handling for an existing target, if there is one */ -+ -+ existing_target = yaffs_find_by_name(new_dir, new_name); -+ if (existing_target && -+ existing_target->variant_type == YAFFS_OBJECT_TYPE_DIRECTORY -+ && !list_empty(&existing_target->variant.dir_variant. -+ children)) { -+ /* There is a target that is a non-empty directory, so we fail */ -+ return YAFFS_FAIL; /* EEXIST or ENOTEMPTY */ -+ } else if (existing_target && existing_target != obj) { -+ /* Nuke the target first, using shadowing, -+ * but only if it isn't the same object. -+ * -+ * Note we must disable gc otherwise it can mess up the shadowing. -+ * -+ */ -+ dev->gc_disable = 1; -+ yaffs_change_obj_name(obj, new_dir, new_name, force, -+ existing_target->obj_id); -+ existing_target->is_shadowed = 1; -+ yaffs_unlink_obj(existing_target); -+ dev->gc_disable = 0; -+ } -+ -+ result = yaffs_change_obj_name(obj, new_dir, new_name, 1, 0); -+ -+ yaffs_update_parent(old_dir); -+ if (new_dir != old_dir) -+ yaffs_update_parent(new_dir); -+ -+ return result; -+ } -+ return YAFFS_FAIL; -+} -+ -+/*------------------------- Block Management and Page Allocation ----------------*/ -+ -+static int yaffs_init_blocks(struct yaffs_dev *dev) -+{ -+ int n_blocks = dev->internal_end_block - dev->internal_start_block + 1; -+ -+ dev->block_info = NULL; -+ dev->chunk_bits = NULL; -+ -+ dev->alloc_block = -1; /* force it to get a new one */ -+ -+ /* If the first allocation strategy fails, thry the alternate one */ -+ dev->block_info = YMALLOC(n_blocks * sizeof(struct yaffs_block_info)); -+ if (!dev->block_info) { -+ dev->block_info = -+ YMALLOC_ALT(n_blocks * sizeof(struct yaffs_block_info)); -+ dev->block_info_alt = 1; -+ } else { -+ dev->block_info_alt = 0; -+ } -+ -+ if (dev->block_info) { -+ /* Set up dynamic blockinfo stuff. */ -+ dev->chunk_bit_stride = (dev->param.chunks_per_block + 7) / 8; /* round up bytes */ -+ dev->chunk_bits = YMALLOC(dev->chunk_bit_stride * n_blocks); -+ if (!dev->chunk_bits) { -+ dev->chunk_bits = -+ YMALLOC_ALT(dev->chunk_bit_stride * n_blocks); -+ dev->chunk_bits_alt = 1; -+ } else { -+ dev->chunk_bits_alt = 0; -+ } -+ } -+ -+ if (dev->block_info && dev->chunk_bits) { -+ memset(dev->block_info, 0, -+ n_blocks * sizeof(struct yaffs_block_info)); -+ memset(dev->chunk_bits, 0, dev->chunk_bit_stride * n_blocks); -+ return YAFFS_OK; -+ } -+ -+ return YAFFS_FAIL; -+} -+ -+static void yaffs_deinit_blocks(struct yaffs_dev *dev) -+{ -+ if (dev->block_info_alt && dev->block_info) -+ YFREE_ALT(dev->block_info); -+ else if (dev->block_info) -+ YFREE(dev->block_info); -+ -+ dev->block_info_alt = 0; -+ -+ dev->block_info = NULL; -+ -+ if (dev->chunk_bits_alt && dev->chunk_bits) -+ YFREE_ALT(dev->chunk_bits); -+ else if (dev->chunk_bits) -+ YFREE(dev->chunk_bits); -+ dev->chunk_bits_alt = 0; -+ dev->chunk_bits = NULL; -+} -+ -+void yaffs_block_became_dirty(struct yaffs_dev *dev, int block_no) -+{ -+ struct yaffs_block_info *bi = yaffs_get_block_info(dev, block_no); -+ -+ int erased_ok = 0; -+ -+ /* If the block is still healthy erase it and mark as clean. -+ * If the block has had a data failure, then retire it. -+ */ -+ -+ T(YAFFS_TRACE_GC | YAFFS_TRACE_ERASE, -+ (TSTR("yaffs_block_became_dirty block %d state %d %s" TENDSTR), -+ block_no, bi->block_state, -+ (bi->needs_retiring) ? "needs retiring" : "")); -+ -+ yaffs2_clear_oldest_dirty_seq(dev, bi); -+ -+ bi->block_state = YAFFS_BLOCK_STATE_DIRTY; -+ -+ /* If this is the block being garbage collected then stop gc'ing this block */ -+ if (block_no == dev->gc_block) -+ dev->gc_block = 0; -+ -+ /* If this block is currently the best candidate for gc then drop as a candidate */ -+ if (block_no == dev->gc_dirtiest) { -+ dev->gc_dirtiest = 0; -+ dev->gc_pages_in_use = 0; -+ } -+ -+ if (!bi->needs_retiring) { -+ yaffs2_checkpt_invalidate(dev); -+ erased_ok = yaffs_erase_block(dev, block_no); -+ if (!erased_ok) { -+ dev->n_erase_failures++; -+ T(YAFFS_TRACE_ERROR | YAFFS_TRACE_BAD_BLOCKS, -+ (TSTR("**>> Erasure failed %d" TENDSTR), block_no)); -+ } -+ } -+ -+ if (erased_ok && -+ ((yaffs_trace_mask & YAFFS_TRACE_ERASE) -+ || !yaffs_skip_verification(dev))) { -+ int i; -+ for (i = 0; i < dev->param.chunks_per_block; i++) { -+ if (!yaffs_check_chunk_erased -+ (dev, block_no * dev->param.chunks_per_block + i)) { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR -+ (">>Block %d erasure supposedly OK, but chunk %d not erased" -+ TENDSTR), block_no, i)); -+ } -+ } -+ } -+ -+ if (erased_ok) { -+ /* Clean it up... */ -+ bi->block_state = YAFFS_BLOCK_STATE_EMPTY; -+ bi->seq_number = 0; -+ dev->n_erased_blocks++; -+ bi->pages_in_use = 0; -+ bi->soft_del_pages = 0; -+ bi->has_shrink_hdr = 0; -+ bi->skip_erased_check = 1; /* This is clean, so no need to check */ -+ bi->gc_prioritise = 0; -+ yaffs_clear_chunk_bits(dev, block_no); -+ -+ T(YAFFS_TRACE_ERASE, -+ (TSTR("Erased block %d" TENDSTR), block_no)); -+ } else { -+ dev->n_free_chunks -= dev->param.chunks_per_block; /* We lost a block of free space */ -+ -+ yaffs_retire_block(dev, block_no); -+ T(YAFFS_TRACE_ERROR | YAFFS_TRACE_BAD_BLOCKS, -+ (TSTR("**>> Block %d retired" TENDSTR), block_no)); -+ } -+} -+ -+static int yaffs_find_alloc_block(struct yaffs_dev *dev) -+{ -+ int i; -+ -+ struct yaffs_block_info *bi; -+ -+ if (dev->n_erased_blocks < 1) { -+ /* Hoosterman we've got a problem. -+ * Can't get space to gc -+ */ -+ T(YAFFS_TRACE_ERROR, -+ (TSTR("yaffs tragedy: no more erased blocks" TENDSTR))); -+ -+ return -1; -+ } -+ -+ /* Find an empty block. */ -+ -+ for (i = dev->internal_start_block; i <= dev->internal_end_block; i++) { -+ dev->alloc_block_finder++; -+ if (dev->alloc_block_finder < dev->internal_start_block -+ || dev->alloc_block_finder > dev->internal_end_block) { -+ dev->alloc_block_finder = dev->internal_start_block; -+ } -+ -+ bi = yaffs_get_block_info(dev, dev->alloc_block_finder); -+ -+ if (bi->block_state == YAFFS_BLOCK_STATE_EMPTY) { -+ bi->block_state = YAFFS_BLOCK_STATE_ALLOCATING; -+ dev->seq_number++; -+ bi->seq_number = dev->seq_number; -+ dev->n_erased_blocks--; -+ T(YAFFS_TRACE_ALLOCATE, -+ (TSTR("Allocated block %d, seq %d, %d left" TENDSTR), -+ dev->alloc_block_finder, dev->seq_number, -+ dev->n_erased_blocks)); -+ return dev->alloc_block_finder; -+ } -+ } -+ -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR -+ ("yaffs tragedy: no more erased blocks, but there should have been %d" -+ TENDSTR), dev->n_erased_blocks)); -+ -+ return -1; -+} -+ -+/* -+ * Check if there's space to allocate... -+ * Thinks.... do we need top make this ths same as yaffs_get_free_chunks()? -+ */ -+int yaffs_check_alloc_available(struct yaffs_dev *dev, int n_chunks) -+{ -+ int reserved_chunks; -+ int reserved_blocks = dev->param.n_reserved_blocks; -+ int checkpt_blocks; -+ -+ checkpt_blocks = yaffs_calc_checkpt_blocks_required(dev); -+ -+ reserved_chunks = -+ ((reserved_blocks + checkpt_blocks) * dev->param.chunks_per_block); -+ -+ return (dev->n_free_chunks > (reserved_chunks + n_chunks)); -+} -+ -+static int yaffs_alloc_chunk(struct yaffs_dev *dev, int use_reserver, -+ struct yaffs_block_info **block_ptr) -+{ -+ int ret_val; -+ struct yaffs_block_info *bi; -+ -+ if (dev->alloc_block < 0) { -+ /* Get next block to allocate off */ -+ dev->alloc_block = yaffs_find_alloc_block(dev); -+ dev->alloc_page = 0; -+ } -+ -+ if (!use_reserver && !yaffs_check_alloc_available(dev, 1)) { -+ /* Not enough space to allocate unless we're allowed to use the reserve. */ -+ return -1; -+ } -+ -+ if (dev->n_erased_blocks < dev->param.n_reserved_blocks -+ && dev->alloc_page == 0) { -+ T(YAFFS_TRACE_ALLOCATE, (TSTR("Allocating reserve" TENDSTR))); -+ } -+ -+ /* Next page please.... */ -+ if (dev->alloc_block >= 0) { -+ bi = yaffs_get_block_info(dev, dev->alloc_block); -+ -+ ret_val = (dev->alloc_block * dev->param.chunks_per_block) + -+ dev->alloc_page; -+ bi->pages_in_use++; -+ yaffs_set_chunk_bit(dev, dev->alloc_block, dev->alloc_page); -+ -+ dev->alloc_page++; -+ -+ dev->n_free_chunks--; -+ -+ /* If the block is full set the state to full */ -+ if (dev->alloc_page >= dev->param.chunks_per_block) { -+ bi->block_state = YAFFS_BLOCK_STATE_FULL; -+ dev->alloc_block = -1; -+ } -+ -+ if (block_ptr) -+ *block_ptr = bi; -+ -+ return ret_val; -+ } -+ -+ T(YAFFS_TRACE_ERROR, -+ (TSTR("!!!!!!!!! Allocator out !!!!!!!!!!!!!!!!!" TENDSTR))); -+ -+ return -1; -+} -+ -+static int yaffs_get_erased_chunks(struct yaffs_dev *dev) -+{ -+ int n; -+ -+ n = dev->n_erased_blocks * dev->param.chunks_per_block; -+ -+ if (dev->alloc_block > 0) -+ n += (dev->param.chunks_per_block - dev->alloc_page); -+ -+ return n; -+ -+} -+ -+/* -+ * yaffs_skip_rest_of_block() skips over the rest of the allocation block -+ * if we don't want to write to it. -+ */ -+void yaffs_skip_rest_of_block(struct yaffs_dev *dev) -+{ -+ if (dev->alloc_block > 0) { -+ struct yaffs_block_info *bi = -+ yaffs_get_block_info(dev, dev->alloc_block); -+ if (bi->block_state == YAFFS_BLOCK_STATE_ALLOCATING) { -+ bi->block_state = YAFFS_BLOCK_STATE_FULL; -+ dev->alloc_block = -1; -+ } -+ } -+} -+ -+static int yaffs_gc_block(struct yaffs_dev *dev, int block, int whole_block) -+{ -+ int old_chunk; -+ int new_chunk; -+ int mark_flash; -+ int ret_val = YAFFS_OK; -+ int i; -+ int is_checkpt_block; -+ int matching_chunk; -+ int max_copies; -+ -+ int chunks_before = yaffs_get_erased_chunks(dev); -+ int chunks_after; -+ -+ struct yaffs_ext_tags tags; -+ -+ struct yaffs_block_info *bi = yaffs_get_block_info(dev, block); -+ -+ struct yaffs_obj *object; -+ -+ is_checkpt_block = (bi->block_state == YAFFS_BLOCK_STATE_CHECKPOINT); -+ -+ T(YAFFS_TRACE_TRACING, -+ (TSTR -+ ("Collecting block %d, in use %d, shrink %d, whole_block %d" -+ TENDSTR), block, bi->pages_in_use, bi->has_shrink_hdr, -+ whole_block)); -+ -+ /*yaffs_verify_free_chunks(dev); */ -+ -+ if (bi->block_state == YAFFS_BLOCK_STATE_FULL) -+ bi->block_state = YAFFS_BLOCK_STATE_COLLECTING; -+ -+ bi->has_shrink_hdr = 0; /* clear the flag so that the block can erase */ -+ -+ dev->gc_disable = 1; -+ -+ if (is_checkpt_block || !yaffs_still_some_chunks(dev, block)) { -+ T(YAFFS_TRACE_TRACING, -+ (TSTR -+ ("Collecting block %d that has no chunks in use" TENDSTR), -+ block)); -+ yaffs_block_became_dirty(dev, block); -+ } else { -+ -+ u8 *buffer = yaffs_get_temp_buffer(dev, __LINE__); -+ -+ yaffs_verify_blk(dev, bi, block); -+ -+ max_copies = (whole_block) ? dev->param.chunks_per_block : 5; -+ old_chunk = block * dev->param.chunks_per_block + dev->gc_chunk; -+ -+ for ( /* init already done */ ; -+ ret_val == YAFFS_OK && -+ dev->gc_chunk < dev->param.chunks_per_block && -+ (bi->block_state == YAFFS_BLOCK_STATE_COLLECTING) && -+ max_copies > 0; dev->gc_chunk++, old_chunk++) { -+ if (yaffs_check_chunk_bit(dev, block, dev->gc_chunk)) { -+ -+ /* This page is in use and might need to be copied off */ -+ -+ max_copies--; -+ -+ mark_flash = 1; -+ -+ yaffs_init_tags(&tags); -+ -+ yaffs_rd_chunk_tags_nand(dev, old_chunk, -+ buffer, &tags); -+ -+ object = yaffs_find_by_number(dev, tags.obj_id); -+ -+ T(YAFFS_TRACE_GC_DETAIL, -+ (TSTR -+ ("Collecting chunk in block %d, %d %d %d " -+ TENDSTR), dev->gc_chunk, tags.obj_id, -+ tags.chunk_id, tags.n_bytes)); -+ -+ if (object && !yaffs_skip_verification(dev)) { -+ if (tags.chunk_id == 0) -+ matching_chunk = -+ object->hdr_chunk; -+ else if (object->soft_del) -+ matching_chunk = old_chunk; /* Defeat the test */ -+ else -+ matching_chunk = -+ yaffs_find_chunk_in_file -+ (object, tags.chunk_id, -+ NULL); -+ -+ if (old_chunk != matching_chunk) -+ T(YAFFS_TRACE_ERROR, -+ (TSTR -+ ("gc: page in gc mismatch: %d %d %d %d" -+ TENDSTR), old_chunk, -+ matching_chunk, tags.obj_id, -+ tags.chunk_id)); -+ -+ } -+ -+ if (!object) { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR -+ ("page %d in gc has no object: %d %d %d " -+ TENDSTR), old_chunk, -+ tags.obj_id, tags.chunk_id, -+ tags.n_bytes)); -+ } -+ -+ if (object && -+ object->deleted && -+ object->soft_del && tags.chunk_id != 0) { -+ /* Data chunk in a soft deleted file, throw it away -+ * It's a soft deleted data chunk, -+ * No need to copy this, just forget about it and -+ * fix up the object. -+ */ -+ -+ /* Free chunks already includes softdeleted chunks. -+ * How ever this chunk is going to soon be really deleted -+ * which will increment free chunks. -+ * We have to decrement free chunks so this works out properly. -+ */ -+ dev->n_free_chunks--; -+ bi->soft_del_pages--; -+ -+ object->n_data_chunks--; -+ -+ if (object->n_data_chunks <= 0) { -+ /* remeber to clean up the object */ -+ dev->gc_cleanup_list[dev-> -+ n_clean_ups] -+ = tags.obj_id; -+ dev->n_clean_ups++; -+ } -+ mark_flash = 0; -+ } else if (0) { -+ /* Todo object && object->deleted && object->n_data_chunks == 0 */ -+ /* Deleted object header with no data chunks. -+ * Can be discarded and the file deleted. -+ */ -+ object->hdr_chunk = 0; -+ yaffs_free_tnode(object->my_dev, -+ object-> -+ variant.file_variant. -+ top); -+ object->variant.file_variant.top = NULL; -+ yaffs_generic_obj_del(object); -+ -+ } else if (object) { -+ /* It's either a data chunk in a live file or -+ * an ObjectHeader, so we're interested in it. -+ * NB Need to keep the ObjectHeaders of deleted files -+ * until the whole file has been deleted off -+ */ -+ tags.serial_number++; -+ -+ dev->n_gc_copies++; -+ -+ if (tags.chunk_id == 0) { -+ /* It is an object Id, -+ * We need to nuke the shrinkheader flags first -+ * Also need to clean up shadowing. -+ * We no longer want the shrink_header flag since its work is done -+ * and if it is left in place it will mess up scanning. -+ */ -+ -+ struct yaffs_obj_hdr *oh; -+ oh = (struct yaffs_obj_hdr *) -+ buffer; -+ -+ oh->is_shrink = 0; -+ tags.extra_is_shrink = 0; -+ -+ oh->shadows_obj = 0; -+ oh->inband_shadowed_obj_id = 0; -+ tags.extra_shadows = 0; -+ -+ /* Update file size */ -+ if (object->variant_type == -+ YAFFS_OBJECT_TYPE_FILE) { -+ oh->file_size = -+ object->variant. -+ file_variant. -+ file_size; -+ tags.extra_length = -+ oh->file_size; -+ } -+ -+ yaffs_verify_oh(object, oh, -+ &tags, 1); -+ new_chunk = -+ yaffs_write_new_chunk(dev, -+ (u8 *) -+ oh, -+ &tags, -+ 1); -+ } else { -+ new_chunk = -+ yaffs_write_new_chunk(dev, -+ buffer, -+ &tags, -+ 1); -+ } -+ -+ if (new_chunk < 0) { -+ ret_val = YAFFS_FAIL; -+ } else { -+ -+ /* Ok, now fix up the Tnodes etc. */ -+ -+ if (tags.chunk_id == 0) { -+ /* It's a header */ -+ object->hdr_chunk = -+ new_chunk; -+ object->serial = -+ tags.serial_number; -+ } else { -+ /* It's a data chunk */ -+ int ok; -+ ok = yaffs_put_chunk_in_file(object, tags.chunk_id, new_chunk, 0); -+ } -+ } -+ } -+ -+ if (ret_val == YAFFS_OK) -+ yaffs_chunk_del(dev, old_chunk, -+ mark_flash, __LINE__); -+ -+ } -+ } -+ -+ yaffs_release_temp_buffer(dev, buffer, __LINE__); -+ -+ } -+ -+ yaffs_verify_collected_blk(dev, bi, block); -+ -+ if (bi->block_state == YAFFS_BLOCK_STATE_COLLECTING) { -+ /* -+ * The gc did not complete. Set block state back to FULL -+ * because checkpointing does not restore gc. -+ */ -+ bi->block_state = YAFFS_BLOCK_STATE_FULL; -+ } else { -+ /* The gc completed. */ -+ /* Do any required cleanups */ -+ for (i = 0; i < dev->n_clean_ups; i++) { -+ /* Time to delete the file too */ -+ object = -+ yaffs_find_by_number(dev, dev->gc_cleanup_list[i]); -+ if (object) { -+ yaffs_free_tnode(dev, -+ object->variant. -+ file_variant.top); -+ object->variant.file_variant.top = NULL; -+ T(YAFFS_TRACE_GC, -+ (TSTR -+ ("yaffs: About to finally delete object %d" -+ TENDSTR), object->obj_id)); -+ yaffs_generic_obj_del(object); -+ object->my_dev->n_deleted_files--; -+ } -+ -+ } -+ -+ chunks_after = yaffs_get_erased_chunks(dev); -+ if (chunks_before >= chunks_after) { -+ T(YAFFS_TRACE_GC, -+ (TSTR -+ ("gc did not increase free chunks before %d after %d" -+ TENDSTR), chunks_before, chunks_after)); -+ } -+ dev->gc_block = 0; -+ dev->gc_chunk = 0; -+ dev->n_clean_ups = 0; -+ } -+ -+ dev->gc_disable = 0; -+ -+ return ret_val; -+} -+ -+/* -+ * FindBlockForgarbageCollection is used to select the dirtiest block (or close enough) -+ * for garbage collection. -+ */ -+ -+static unsigned yaffs_find_gc_block(struct yaffs_dev *dev, -+ int aggressive, int background) -+{ -+ int i; -+ int iterations; -+ unsigned selected = 0; -+ int prioritised = 0; -+ int prioritised_exist = 0; -+ struct yaffs_block_info *bi; -+ int threshold; -+ -+ /* First let's see if we need to grab a prioritised block */ -+ if (dev->has_pending_prioritised_gc && !aggressive) { -+ dev->gc_dirtiest = 0; -+ bi = dev->block_info; -+ for (i = dev->internal_start_block; -+ i <= dev->internal_end_block && !selected; i++) { -+ -+ if (bi->gc_prioritise) { -+ prioritised_exist = 1; -+ if (bi->block_state == YAFFS_BLOCK_STATE_FULL && -+ yaffs_block_ok_for_gc(dev, bi)) { -+ selected = i; -+ prioritised = 1; -+ } -+ } -+ bi++; -+ } -+ -+ /* -+ * If there is a prioritised block and none was selected then -+ * this happened because there is at least one old dirty block gumming -+ * up the works. Let's gc the oldest dirty block. -+ */ -+ -+ if (prioritised_exist && -+ !selected && dev->oldest_dirty_block > 0) -+ selected = dev->oldest_dirty_block; -+ -+ if (!prioritised_exist) /* None found, so we can clear this */ -+ dev->has_pending_prioritised_gc = 0; -+ } -+ -+ /* If we're doing aggressive GC then we are happy to take a less-dirty block, and -+ * search harder. -+ * else (we're doing a leasurely gc), then we only bother to do this if the -+ * block has only a few pages in use. -+ */ -+ -+ if (!selected) { -+ int pages_used; -+ int n_blocks = -+ dev->internal_end_block - dev->internal_start_block + 1; -+ if (aggressive) { -+ threshold = dev->param.chunks_per_block; -+ iterations = n_blocks; -+ } else { -+ int max_threshold; -+ -+ if (background) -+ max_threshold = dev->param.chunks_per_block / 2; -+ else -+ max_threshold = dev->param.chunks_per_block / 8; -+ -+ if (max_threshold < YAFFS_GC_PASSIVE_THRESHOLD) -+ max_threshold = YAFFS_GC_PASSIVE_THRESHOLD; -+ -+ threshold = background ? (dev->gc_not_done + 2) * 2 : 0; -+ if (threshold < YAFFS_GC_PASSIVE_THRESHOLD) -+ threshold = YAFFS_GC_PASSIVE_THRESHOLD; -+ if (threshold > max_threshold) -+ threshold = max_threshold; -+ -+ iterations = n_blocks / 16 + 1; -+ if (iterations > 100) -+ iterations = 100; -+ } -+ -+ for (i = 0; -+ i < iterations && -+ (dev->gc_dirtiest < 1 || -+ dev->gc_pages_in_use > YAFFS_GC_GOOD_ENOUGH); i++) { -+ dev->gc_block_finder++; -+ if (dev->gc_block_finder < dev->internal_start_block || -+ dev->gc_block_finder > dev->internal_end_block) -+ dev->gc_block_finder = -+ dev->internal_start_block; -+ -+ bi = yaffs_get_block_info(dev, dev->gc_block_finder); -+ -+ pages_used = bi->pages_in_use - bi->soft_del_pages; -+ -+ if (bi->block_state == YAFFS_BLOCK_STATE_FULL && -+ pages_used < dev->param.chunks_per_block && -+ (dev->gc_dirtiest < 1 -+ || pages_used < dev->gc_pages_in_use) -+ && yaffs_block_ok_for_gc(dev, bi)) { -+ dev->gc_dirtiest = dev->gc_block_finder; -+ dev->gc_pages_in_use = pages_used; -+ } -+ } -+ -+ if (dev->gc_dirtiest > 0 && dev->gc_pages_in_use <= threshold) -+ selected = dev->gc_dirtiest; -+ } -+ -+ /* -+ * If nothing has been selected for a while, try selecting the oldest dirty -+ * because that's gumming up the works. -+ */ -+ -+ if (!selected && dev->param.is_yaffs2 && -+ dev->gc_not_done >= (background ? 10 : 20)) { -+ yaffs2_find_oldest_dirty_seq(dev); -+ if (dev->oldest_dirty_block > 0) { -+ selected = dev->oldest_dirty_block; -+ dev->gc_dirtiest = selected; -+ dev->oldest_dirty_gc_count++; -+ bi = yaffs_get_block_info(dev, selected); -+ dev->gc_pages_in_use = -+ bi->pages_in_use - bi->soft_del_pages; -+ } else { -+ dev->gc_not_done = 0; -+ } -+ } -+ -+ if (selected) { -+ T(YAFFS_TRACE_GC, -+ (TSTR -+ ("GC Selected block %d with %d free, prioritised:%d" -+ TENDSTR), selected, -+ dev->param.chunks_per_block - dev->gc_pages_in_use, -+ prioritised)); -+ -+ dev->n_gc_blocks++; -+ if (background) -+ dev->bg_gcs++; -+ -+ dev->gc_dirtiest = 0; -+ dev->gc_pages_in_use = 0; -+ dev->gc_not_done = 0; -+ if (dev->refresh_skip > 0) -+ dev->refresh_skip--; -+ } else { -+ dev->gc_not_done++; -+ T(YAFFS_TRACE_GC, -+ (TSTR -+ ("GC none: finder %d skip %d threshold %d dirtiest %d using %d oldest %d%s" -+ TENDSTR), dev->gc_block_finder, dev->gc_not_done, threshold, -+ dev->gc_dirtiest, dev->gc_pages_in_use, -+ dev->oldest_dirty_block, background ? " bg" : "")); -+ } -+ -+ return selected; -+} -+ -+/* New garbage collector -+ * If we're very low on erased blocks then we do aggressive garbage collection -+ * otherwise we do "leasurely" garbage collection. -+ * Aggressive gc looks further (whole array) and will accept less dirty blocks. -+ * Passive gc only inspects smaller areas and will only accept more dirty blocks. -+ * -+ * The idea is to help clear out space in a more spread-out manner. -+ * Dunno if it really does anything useful. -+ */ -+static int yaffs_check_gc(struct yaffs_dev *dev, int background) -+{ -+ int aggressive = 0; -+ int gc_ok = YAFFS_OK; -+ int max_tries = 0; -+ int min_erased; -+ int erased_chunks; -+ int checkpt_block_adjust; -+ -+ if (dev->param.gc_control && (dev->param.gc_control(dev) & 1) == 0) -+ return YAFFS_OK; -+ -+ if (dev->gc_disable) { -+ /* Bail out so we don't get recursive gc */ -+ return YAFFS_OK; -+ } -+ -+ /* This loop should pass the first time. -+ * We'll only see looping here if the collection does not increase space. -+ */ -+ -+ do { -+ max_tries++; -+ -+ checkpt_block_adjust = yaffs_calc_checkpt_blocks_required(dev); -+ -+ min_erased = -+ dev->param.n_reserved_blocks + checkpt_block_adjust + 1; -+ erased_chunks = -+ dev->n_erased_blocks * dev->param.chunks_per_block; -+ -+ /* If we need a block soon then do aggressive gc. */ -+ if (dev->n_erased_blocks < min_erased) -+ aggressive = 1; -+ else { -+ if (!background -+ && erased_chunks > (dev->n_free_chunks / 4)) -+ break; -+ -+ if (dev->gc_skip > 20) -+ dev->gc_skip = 20; -+ if (erased_chunks < dev->n_free_chunks / 2 || -+ dev->gc_skip < 1 || background) -+ aggressive = 0; -+ else { -+ dev->gc_skip--; -+ break; -+ } -+ } -+ -+ dev->gc_skip = 5; -+ -+ /* If we don't already have a block being gc'd then see if we should start another */ -+ -+ if (dev->gc_block < 1 && !aggressive) { -+ dev->gc_block = yaffs2_find_refresh_block(dev); -+ dev->gc_chunk = 0; -+ dev->n_clean_ups = 0; -+ } -+ if (dev->gc_block < 1) { -+ dev->gc_block = -+ yaffs_find_gc_block(dev, aggressive, background); -+ dev->gc_chunk = 0; -+ dev->n_clean_ups = 0; -+ } -+ -+ if (dev->gc_block > 0) { -+ dev->all_gcs++; -+ if (!aggressive) -+ dev->passive_gc_count++; -+ -+ T(YAFFS_TRACE_GC, -+ (TSTR -+ ("yaffs: GC n_erased_blocks %d aggressive %d" -+ TENDSTR), dev->n_erased_blocks, aggressive)); -+ -+ gc_ok = yaffs_gc_block(dev, dev->gc_block, aggressive); -+ } -+ -+ if (dev->n_erased_blocks < (dev->param.n_reserved_blocks) -+ && dev->gc_block > 0) { -+ T(YAFFS_TRACE_GC, -+ (TSTR -+ ("yaffs: GC !!!no reclaim!!! n_erased_blocks %d after try %d block %d" -+ TENDSTR), dev->n_erased_blocks, max_tries, -+ dev->gc_block)); -+ } -+ } while ((dev->n_erased_blocks < dev->param.n_reserved_blocks) && -+ (dev->gc_block > 0) && (max_tries < 2)); -+ -+ return aggressive ? gc_ok : YAFFS_OK; -+} -+ -+/* -+ * yaffs_bg_gc() -+ * Garbage collects. Intended to be called from a background thread. -+ * Returns non-zero if at least half the free chunks are erased. -+ */ -+int yaffs_bg_gc(struct yaffs_dev *dev, unsigned urgency) -+{ -+ int erased_chunks = dev->n_erased_blocks * dev->param.chunks_per_block; -+ -+ T(YAFFS_TRACE_BACKGROUND, (TSTR("Background gc %u" TENDSTR), urgency)); -+ -+ yaffs_check_gc(dev, 1); -+ return erased_chunks > dev->n_free_chunks / 2; -+} -+ -+/*------------------------- TAGS --------------------------------*/ -+ -+static int yaffs_tags_match(const struct yaffs_ext_tags *tags, int obj_id, -+ int chunk_obj) -+{ -+ return (tags->chunk_id == chunk_obj && -+ tags->obj_id == obj_id && !tags->is_deleted) ? 1 : 0; -+ -+} -+ -+/*-------------------- Data file manipulation -----------------*/ -+ -+static int yaffs_find_chunk_in_file(struct yaffs_obj *in, int inode_chunk, -+ struct yaffs_ext_tags *tags) -+{ -+ /*Get the Tnode, then get the level 0 offset chunk offset */ -+ struct yaffs_tnode *tn; -+ int the_chunk = -1; -+ struct yaffs_ext_tags local_tags; -+ int ret_val = -1; -+ -+ struct yaffs_dev *dev = in->my_dev; -+ -+ if (!tags) { -+ /* Passed a NULL, so use our own tags space */ -+ tags = &local_tags; -+ } -+ -+ tn = yaffs_find_tnode_0(dev, &in->variant.file_variant, inode_chunk); -+ -+ if (tn) { -+ the_chunk = yaffs_get_group_base(dev, tn, inode_chunk); -+ -+ ret_val = -+ yaffs_find_chunk_in_group(dev, the_chunk, tags, in->obj_id, -+ inode_chunk); -+ } -+ return ret_val; -+} -+ -+static int yaffs_find_del_file_chunk(struct yaffs_obj *in, int inode_chunk, -+ struct yaffs_ext_tags *tags) -+{ -+ /* Get the Tnode, then get the level 0 offset chunk offset */ -+ struct yaffs_tnode *tn; -+ int the_chunk = -1; -+ struct yaffs_ext_tags local_tags; -+ -+ struct yaffs_dev *dev = in->my_dev; -+ int ret_val = -1; -+ -+ if (!tags) { -+ /* Passed a NULL, so use our own tags space */ -+ tags = &local_tags; -+ } -+ -+ tn = yaffs_find_tnode_0(dev, &in->variant.file_variant, inode_chunk); -+ -+ if (tn) { -+ -+ the_chunk = yaffs_get_group_base(dev, tn, inode_chunk); -+ -+ ret_val = -+ yaffs_find_chunk_in_group(dev, the_chunk, tags, in->obj_id, -+ inode_chunk); -+ -+ /* Delete the entry in the filestructure (if found) */ -+ if (ret_val != -1) -+ yaffs_load_tnode_0(dev, tn, inode_chunk, 0); -+ } -+ -+ return ret_val; -+} -+ -+int yaffs_put_chunk_in_file(struct yaffs_obj *in, int inode_chunk, -+ int nand_chunk, int in_scan) -+{ -+ /* NB in_scan is zero unless scanning. -+ * For forward scanning, in_scan is > 0; -+ * for backward scanning in_scan is < 0 -+ * -+ * nand_chunk = 0 is a dummy insert to make sure the tnodes are there. -+ */ -+ -+ struct yaffs_tnode *tn; -+ struct yaffs_dev *dev = in->my_dev; -+ int existing_cunk; -+ struct yaffs_ext_tags existing_tags; -+ struct yaffs_ext_tags new_tags; -+ unsigned existing_serial, new_serial; -+ -+ if (in->variant_type != YAFFS_OBJECT_TYPE_FILE) { -+ /* Just ignore an attempt at putting a chunk into a non-file during scanning -+ * If it is not during Scanning then something went wrong! -+ */ -+ if (!in_scan) { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR -+ ("yaffs tragedy:attempt to put data chunk into a non-file" -+ TENDSTR))); -+ YBUG(); -+ } -+ -+ yaffs_chunk_del(dev, nand_chunk, 1, __LINE__); -+ return YAFFS_OK; -+ } -+ -+ tn = yaffs_add_find_tnode_0(dev, -+ &in->variant.file_variant, -+ inode_chunk, NULL); -+ if (!tn) -+ return YAFFS_FAIL; -+ -+ if (!nand_chunk) -+ /* Dummy insert, bail now */ -+ return YAFFS_OK; -+ -+ existing_cunk = yaffs_get_group_base(dev, tn, inode_chunk); -+ -+ if (in_scan != 0) { -+ /* If we're scanning then we need to test for duplicates -+ * NB This does not need to be efficient since it should only ever -+ * happen when the power fails during a write, then only one -+ * chunk should ever be affected. -+ * -+ * Correction for YAFFS2: This could happen quite a lot and we need to think about efficiency! TODO -+ * Update: For backward scanning we don't need to re-read tags so this is quite cheap. -+ */ -+ -+ if (existing_cunk > 0) { -+ /* NB Right now existing chunk will not be real chunk_id if the chunk group size > 1 -+ * thus we have to do a FindChunkInFile to get the real chunk id. -+ * -+ * We have a duplicate now we need to decide which one to use: -+ * -+ * Backwards scanning YAFFS2: The old one is what we use, dump the new one. -+ * Forward scanning YAFFS2: The new one is what we use, dump the old one. -+ * YAFFS1: Get both sets of tags and compare serial numbers. -+ */ -+ -+ if (in_scan > 0) { -+ /* Only do this for forward scanning */ -+ yaffs_rd_chunk_tags_nand(dev, -+ nand_chunk, -+ NULL, &new_tags); -+ -+ /* Do a proper find */ -+ existing_cunk = -+ yaffs_find_chunk_in_file(in, inode_chunk, -+ &existing_tags); -+ } -+ -+ if (existing_cunk <= 0) { -+ /*Hoosterman - how did this happen? */ -+ -+ T(YAFFS_TRACE_ERROR, -+ (TSTR -+ ("yaffs tragedy: existing chunk < 0 in scan" -+ TENDSTR))); -+ -+ } -+ -+ /* NB The deleted flags should be false, otherwise the chunks will -+ * not be loaded during a scan -+ */ -+ -+ if (in_scan > 0) { -+ new_serial = new_tags.serial_number; -+ existing_serial = existing_tags.serial_number; -+ } -+ -+ if ((in_scan > 0) && -+ (existing_cunk <= 0 || -+ ((existing_serial + 1) & 3) == new_serial)) { -+ /* Forward scanning. -+ * Use new -+ * Delete the old one and drop through to update the tnode -+ */ -+ yaffs_chunk_del(dev, existing_cunk, 1, -+ __LINE__); -+ } else { -+ /* Backward scanning or we want to use the existing one -+ * Use existing. -+ * Delete the new one and return early so that the tnode isn't changed -+ */ -+ yaffs_chunk_del(dev, nand_chunk, 1, __LINE__); -+ return YAFFS_OK; -+ } -+ } -+ -+ } -+ -+ if (existing_cunk == 0) -+ in->n_data_chunks++; -+ -+ yaffs_load_tnode_0(dev, tn, inode_chunk, nand_chunk); -+ -+ return YAFFS_OK; -+} -+ -+static int yaffs_rd_data_obj(struct yaffs_obj *in, int inode_chunk, u8 * buffer) -+{ -+ int nand_chunk = yaffs_find_chunk_in_file(in, inode_chunk, NULL); -+ -+ if (nand_chunk >= 0) -+ return yaffs_rd_chunk_tags_nand(in->my_dev, nand_chunk, -+ buffer, NULL); -+ else { -+ T(YAFFS_TRACE_NANDACCESS, -+ (TSTR("Chunk %d not found zero instead" TENDSTR), -+ nand_chunk)); -+ /* get sane (zero) data if you read a hole */ -+ memset(buffer, 0, in->my_dev->data_bytes_per_chunk); -+ return 0; -+ } -+ -+} -+ -+void yaffs_chunk_del(struct yaffs_dev *dev, int chunk_id, int mark_flash, -+ int lyn) -+{ -+ int block; -+ int page; -+ struct yaffs_ext_tags tags; -+ struct yaffs_block_info *bi; -+ -+ if (chunk_id <= 0) -+ return; -+ -+ dev->n_deletions++; -+ block = chunk_id / dev->param.chunks_per_block; -+ page = chunk_id % dev->param.chunks_per_block; -+ -+ if (!yaffs_check_chunk_bit(dev, block, page)) -+ T(YAFFS_TRACE_VERIFY, -+ (TSTR("Deleting invalid chunk %d" TENDSTR), chunk_id)); -+ -+ bi = yaffs_get_block_info(dev, block); -+ -+ yaffs2_update_oldest_dirty_seq(dev, block, bi); -+ -+ T(YAFFS_TRACE_DELETION, -+ (TSTR("line %d delete of chunk %d" TENDSTR), lyn, chunk_id)); -+ -+ if (!dev->param.is_yaffs2 && mark_flash && -+ bi->block_state != YAFFS_BLOCK_STATE_COLLECTING) { -+ -+ yaffs_init_tags(&tags); -+ -+ tags.is_deleted = 1; -+ -+ yaffs_wr_chunk_tags_nand(dev, chunk_id, NULL, &tags); -+ yaffs_handle_chunk_update(dev, chunk_id, &tags); -+ } else { -+ dev->n_unmarked_deletions++; -+ } -+ -+ /* Pull out of the management area. -+ * If the whole block became dirty, this will kick off an erasure. -+ */ -+ if (bi->block_state == YAFFS_BLOCK_STATE_ALLOCATING || -+ bi->block_state == YAFFS_BLOCK_STATE_FULL || -+ bi->block_state == YAFFS_BLOCK_STATE_NEEDS_SCANNING || -+ bi->block_state == YAFFS_BLOCK_STATE_COLLECTING) { -+ dev->n_free_chunks++; -+ -+ yaffs_clear_chunk_bit(dev, block, page); -+ -+ bi->pages_in_use--; -+ -+ if (bi->pages_in_use == 0 && -+ !bi->has_shrink_hdr && -+ bi->block_state != YAFFS_BLOCK_STATE_ALLOCATING && -+ bi->block_state != YAFFS_BLOCK_STATE_NEEDS_SCANNING) { -+ yaffs_block_became_dirty(dev, block); -+ } -+ -+ } -+ -+} -+ -+static int yaffs_wr_data_obj(struct yaffs_obj *in, int inode_chunk, -+ const u8 * buffer, int n_bytes, int use_reserve) -+{ -+ /* Find old chunk Need to do this to get serial number -+ * Write new one and patch into tree. -+ * Invalidate old tags. -+ */ -+ -+ int prev_chunk_id; -+ struct yaffs_ext_tags prev_tags; -+ -+ int new_chunk_id; -+ struct yaffs_ext_tags new_tags; -+ -+ struct yaffs_dev *dev = in->my_dev; -+ -+ yaffs_check_gc(dev, 0); -+ -+ /* Get the previous chunk at this location in the file if it exists. -+ * If it does not exist then put a zero into the tree. This creates -+ * the tnode now, rather than later when it is harder to clean up. -+ */ -+ prev_chunk_id = yaffs_find_chunk_in_file(in, inode_chunk, &prev_tags); -+ if (prev_chunk_id < 1 && -+ !yaffs_put_chunk_in_file(in, inode_chunk, 0, 0)) -+ return 0; -+ -+ /* Set up new tags */ -+ yaffs_init_tags(&new_tags); -+ -+ new_tags.chunk_id = inode_chunk; -+ new_tags.obj_id = in->obj_id; -+ new_tags.serial_number = -+ (prev_chunk_id > 0) ? prev_tags.serial_number + 1 : 1; -+ new_tags.n_bytes = n_bytes; -+ -+ if (n_bytes < 1 || n_bytes > dev->param.total_bytes_per_chunk) { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR("Writing %d bytes to chunk!!!!!!!!!" TENDSTR), -+ n_bytes)); -+ YBUG(); -+ } -+ -+ new_chunk_id = -+ yaffs_write_new_chunk(dev, buffer, &new_tags, use_reserve); -+ -+ if (new_chunk_id > 0) { -+ yaffs_put_chunk_in_file(in, inode_chunk, new_chunk_id, 0); -+ -+ if (prev_chunk_id > 0) -+ yaffs_chunk_del(dev, prev_chunk_id, 1, __LINE__); -+ -+ yaffs_verify_file_sane(in); -+ } -+ return new_chunk_id; -+ -+} -+ -+/* UpdateObjectHeader updates the header on NAND for an object. -+ * If name is not NULL, then that new name is used. -+ */ -+int yaffs_update_oh(struct yaffs_obj *in, const YCHAR * name, int force, -+ int is_shrink, int shadows, struct yaffs_xattr_mod *xmod) -+{ -+ -+ struct yaffs_block_info *bi; -+ -+ struct yaffs_dev *dev = in->my_dev; -+ -+ int prev_chunk_id; -+ int ret_val = 0; -+ int result = 0; -+ -+ int new_chunk_id; -+ struct yaffs_ext_tags new_tags; -+ struct yaffs_ext_tags old_tags; -+ const YCHAR *alias = NULL; -+ -+ u8 *buffer = NULL; -+ YCHAR old_name[YAFFS_MAX_NAME_LENGTH + 1]; -+ -+ struct yaffs_obj_hdr *oh = NULL; -+ -+ yaffs_strcpy(old_name, _Y("silly old name")); -+ -+ if (!in->fake || in == dev->root_dir || /* The root_dir should also be saved */ -+ force || xmod) { -+ -+ yaffs_check_gc(dev, 0); -+ yaffs_check_obj_details_loaded(in); -+ -+ buffer = yaffs_get_temp_buffer(in->my_dev, __LINE__); -+ oh = (struct yaffs_obj_hdr *)buffer; -+ -+ prev_chunk_id = in->hdr_chunk; -+ -+ if (prev_chunk_id > 0) { -+ result = yaffs_rd_chunk_tags_nand(dev, prev_chunk_id, -+ buffer, &old_tags); -+ -+ yaffs_verify_oh(in, oh, &old_tags, 0); -+ -+ memcpy(old_name, oh->name, sizeof(oh->name)); -+ memset(buffer, 0xFF, sizeof(struct yaffs_obj_hdr)); -+ } else { -+ memset(buffer, 0xFF, dev->data_bytes_per_chunk); -+ } -+ -+ oh->type = in->variant_type; -+ oh->yst_mode = in->yst_mode; -+ oh->shadows_obj = oh->inband_shadowed_obj_id = shadows; -+ -+ yaffs_load_attribs_oh(oh, in); -+ -+ if (in->parent) -+ oh->parent_obj_id = in->parent->obj_id; -+ else -+ oh->parent_obj_id = 0; -+ -+ if (name && *name) { -+ memset(oh->name, 0, sizeof(oh->name)); -+ yaffs_load_oh_from_name(dev, oh->name, name); -+ } else if (prev_chunk_id > 0) { -+ memcpy(oh->name, old_name, sizeof(oh->name)); -+ } else { -+ memset(oh->name, 0, sizeof(oh->name)); -+ } -+ -+ oh->is_shrink = is_shrink; -+ -+ switch (in->variant_type) { -+ case YAFFS_OBJECT_TYPE_UNKNOWN: -+ /* Should not happen */ -+ break; -+ case YAFFS_OBJECT_TYPE_FILE: -+ oh->file_size = -+ (oh->parent_obj_id == YAFFS_OBJECTID_DELETED -+ || oh->parent_obj_id == -+ YAFFS_OBJECTID_UNLINKED) ? 0 : in-> -+ variant.file_variant.file_size; -+ break; -+ case YAFFS_OBJECT_TYPE_HARDLINK: -+ oh->equiv_id = in->variant.hardlink_variant.equiv_id; -+ break; -+ case YAFFS_OBJECT_TYPE_SPECIAL: -+ /* Do nothing */ -+ break; -+ case YAFFS_OBJECT_TYPE_DIRECTORY: -+ /* Do nothing */ -+ break; -+ case YAFFS_OBJECT_TYPE_SYMLINK: -+ alias = in->variant.symlink_variant.alias; -+ if (!alias) -+ alias = _Y("no alias"); -+ yaffs_strncpy(oh->alias, alias, YAFFS_MAX_ALIAS_LENGTH); -+ oh->alias[YAFFS_MAX_ALIAS_LENGTH] = 0; -+ break; -+ } -+ -+ /* process any xattrib modifications */ -+ if (xmod) -+ yaffs_apply_xattrib_mod(in, (char *)buffer, xmod); -+ -+ /* Tags */ -+ yaffs_init_tags(&new_tags); -+ in->serial++; -+ new_tags.chunk_id = 0; -+ new_tags.obj_id = in->obj_id; -+ new_tags.serial_number = in->serial; -+ -+ /* Add extra info for file header */ -+ -+ new_tags.extra_available = 1; -+ new_tags.extra_parent_id = oh->parent_obj_id; -+ new_tags.extra_length = oh->file_size; -+ new_tags.extra_is_shrink = oh->is_shrink; -+ new_tags.extra_equiv_id = oh->equiv_id; -+ new_tags.extra_shadows = (oh->shadows_obj > 0) ? 1 : 0; -+ new_tags.extra_obj_type = in->variant_type; -+ -+ yaffs_verify_oh(in, oh, &new_tags, 1); -+ -+ /* Create new chunk in NAND */ -+ new_chunk_id = -+ yaffs_write_new_chunk(dev, buffer, &new_tags, -+ (prev_chunk_id > 0) ? 1 : 0); -+ -+ if (new_chunk_id >= 0) { -+ -+ in->hdr_chunk = new_chunk_id; -+ -+ if (prev_chunk_id > 0) { -+ yaffs_chunk_del(dev, prev_chunk_id, 1, -+ __LINE__); -+ } -+ -+ if (!yaffs_obj_cache_dirty(in)) -+ in->dirty = 0; -+ -+ /* If this was a shrink, then mark the block that the chunk lives on */ -+ if (is_shrink) { -+ bi = yaffs_get_block_info(in->my_dev, -+ new_chunk_id / -+ in->my_dev->param. -+ chunks_per_block); -+ bi->has_shrink_hdr = 1; -+ } -+ -+ } -+ -+ ret_val = new_chunk_id; -+ -+ } -+ -+ if (buffer) -+ yaffs_release_temp_buffer(dev, buffer, __LINE__); -+ -+ return ret_val; -+} -+ -+/*------------------------ Short Operations Cache ---------------------------------------- -+ * In many situations where there is no high level buffering a lot of -+ * reads might be short sequential reads, and a lot of writes may be short -+ * sequential writes. eg. scanning/writing a jpeg file. -+ * In these cases, a short read/write cache can provide a huge perfomance -+ * benefit with dumb-as-a-rock code. -+ * In Linux, the page cache provides read buffering and the short op cache -+ * provides write buffering. -+ * -+ * There are a limited number (~10) of cache chunks per device so that we don't -+ * need a very intelligent search. -+ */ -+ -+static int yaffs_obj_cache_dirty(struct yaffs_obj *obj) -+{ -+ struct yaffs_dev *dev = obj->my_dev; -+ int i; -+ struct yaffs_cache *cache; -+ int n_caches = obj->my_dev->param.n_caches; -+ -+ for (i = 0; i < n_caches; i++) { -+ cache = &dev->cache[i]; -+ if (cache->object == obj && cache->dirty) -+ return 1; -+ } -+ -+ return 0; -+} -+ -+static void yaffs_flush_file_cache(struct yaffs_obj *obj) -+{ -+ struct yaffs_dev *dev = obj->my_dev; -+ int lowest = -99; /* Stop compiler whining. */ -+ int i; -+ struct yaffs_cache *cache; -+ int chunk_written = 0; -+ int n_caches = obj->my_dev->param.n_caches; -+ -+ if (n_caches > 0) { -+ do { -+ cache = NULL; -+ -+ /* Find the dirty cache for this object with the lowest chunk id. */ -+ for (i = 0; i < n_caches; i++) { -+ if (dev->cache[i].object == obj && -+ dev->cache[i].dirty) { -+ if (!cache -+ || dev->cache[i].chunk_id < -+ lowest) { -+ cache = &dev->cache[i]; -+ lowest = cache->chunk_id; -+ } -+ } -+ } -+ -+ if (cache && !cache->locked) { -+ /* Write it out and free it up */ -+ -+ chunk_written = -+ yaffs_wr_data_obj(cache->object, -+ cache->chunk_id, -+ cache->data, -+ cache->n_bytes, 1); -+ cache->dirty = 0; -+ cache->object = NULL; -+ } -+ -+ } while (cache && chunk_written > 0); -+ -+ if (cache) { -+ /* Hoosterman, disk full while writing cache out. */ -+ T(YAFFS_TRACE_ERROR, -+ (TSTR -+ ("yaffs tragedy: no space during cache write" -+ TENDSTR))); -+ -+ } -+ } -+ -+} -+ -+/*yaffs_flush_whole_cache(dev) -+ * -+ * -+ */ -+ -+void yaffs_flush_whole_cache(struct yaffs_dev *dev) -+{ -+ struct yaffs_obj *obj; -+ int n_caches = dev->param.n_caches; -+ int i; -+ -+ /* Find a dirty object in the cache and flush it... -+ * until there are no further dirty objects. -+ */ -+ do { -+ obj = NULL; -+ for (i = 0; i < n_caches && !obj; i++) { -+ if (dev->cache[i].object && dev->cache[i].dirty) -+ obj = dev->cache[i].object; -+ -+ } -+ if (obj) -+ yaffs_flush_file_cache(obj); -+ -+ } while (obj); -+ -+} -+ -+/* Grab us a cache chunk for use. -+ * First look for an empty one. -+ * Then look for the least recently used non-dirty one. -+ * Then look for the least recently used dirty one...., flush and look again. -+ */ -+static struct yaffs_cache *yaffs_grab_chunk_worker(struct yaffs_dev *dev) -+{ -+ int i; -+ -+ if (dev->param.n_caches > 0) { -+ for (i = 0; i < dev->param.n_caches; i++) { -+ if (!dev->cache[i].object) -+ return &dev->cache[i]; -+ } -+ } -+ -+ return NULL; -+} -+ -+static struct yaffs_cache *yaffs_grab_chunk_cache(struct yaffs_dev *dev) -+{ -+ struct yaffs_cache *cache; -+ struct yaffs_obj *the_obj; -+ int usage; -+ int i; -+ int pushout; -+ -+ if (dev->param.n_caches > 0) { -+ /* Try find a non-dirty one... */ -+ -+ cache = yaffs_grab_chunk_worker(dev); -+ -+ if (!cache) { -+ /* They were all dirty, find the last recently used object and flush -+ * its cache, then find again. -+ * NB what's here is not very accurate, we actually flush the object -+ * the last recently used page. -+ */ -+ -+ /* With locking we can't assume we can use entry zero */ -+ -+ the_obj = NULL; -+ usage = -1; -+ cache = NULL; -+ pushout = -1; -+ -+ for (i = 0; i < dev->param.n_caches; i++) { -+ if (dev->cache[i].object && -+ !dev->cache[i].locked && -+ (dev->cache[i].last_use < usage -+ || !cache)) { -+ usage = dev->cache[i].last_use; -+ the_obj = dev->cache[i].object; -+ cache = &dev->cache[i]; -+ pushout = i; -+ } -+ } -+ -+ if (!cache || cache->dirty) { -+ /* Flush and try again */ -+ yaffs_flush_file_cache(the_obj); -+ cache = yaffs_grab_chunk_worker(dev); -+ } -+ -+ } -+ return cache; -+ } else { -+ return NULL; -+ } -+} -+ -+/* Find a cached chunk */ -+static struct yaffs_cache *yaffs_find_chunk_cache(const struct yaffs_obj *obj, -+ int chunk_id) -+{ -+ struct yaffs_dev *dev = obj->my_dev; -+ int i; -+ if (dev->param.n_caches > 0) { -+ for (i = 0; i < dev->param.n_caches; i++) { -+ if (dev->cache[i].object == obj && -+ dev->cache[i].chunk_id == chunk_id) { -+ dev->cache_hits++; -+ -+ return &dev->cache[i]; -+ } -+ } -+ } -+ return NULL; -+} -+ -+/* Mark the chunk for the least recently used algorithym */ -+static void yaffs_use_cache(struct yaffs_dev *dev, struct yaffs_cache *cache, -+ int is_write) -+{ -+ -+ if (dev->param.n_caches > 0) { -+ if (dev->cache_last_use < 0 || dev->cache_last_use > 100000000) { -+ /* Reset the cache usages */ -+ int i; -+ for (i = 1; i < dev->param.n_caches; i++) -+ dev->cache[i].last_use = 0; -+ -+ dev->cache_last_use = 0; -+ } -+ -+ dev->cache_last_use++; -+ -+ cache->last_use = dev->cache_last_use; -+ -+ if (is_write) -+ cache->dirty = 1; -+ } -+} -+ -+/* Invalidate a single cache page. -+ * Do this when a whole page gets written, -+ * ie the short cache for this page is no longer valid. -+ */ -+static void yaffs_invalidate_chunk_cache(struct yaffs_obj *object, int chunk_id) -+{ -+ if (object->my_dev->param.n_caches > 0) { -+ struct yaffs_cache *cache = -+ yaffs_find_chunk_cache(object, chunk_id); -+ -+ if (cache) -+ cache->object = NULL; -+ } -+} -+ -+/* Invalidate all the cache pages associated with this object -+ * Do this whenever ther file is deleted or resized. -+ */ -+static void yaffs_invalidate_whole_cache(struct yaffs_obj *in) -+{ -+ int i; -+ struct yaffs_dev *dev = in->my_dev; -+ -+ if (dev->param.n_caches > 0) { -+ /* Invalidate it. */ -+ for (i = 0; i < dev->param.n_caches; i++) { -+ if (dev->cache[i].object == in) -+ dev->cache[i].object = NULL; -+ } -+ } -+} -+ -+/*--------------------- File read/write ------------------------ -+ * Read and write have very similar structures. -+ * In general the read/write has three parts to it -+ * An incomplete chunk to start with (if the read/write is not chunk-aligned) -+ * Some complete chunks -+ * An incomplete chunk to end off with -+ * -+ * Curve-balls: the first chunk might also be the last chunk. -+ */ -+ -+int yaffs_file_rd(struct yaffs_obj *in, u8 * buffer, loff_t offset, int n_bytes) -+{ -+ -+ int chunk; -+ u32 start; -+ int n_copy; -+ int n = n_bytes; -+ int n_done = 0; -+ struct yaffs_cache *cache; -+ -+ struct yaffs_dev *dev; -+ -+ dev = in->my_dev; -+ -+ while (n > 0) { -+ /* chunk = offset / dev->data_bytes_per_chunk + 1; */ -+ /* start = offset % dev->data_bytes_per_chunk; */ -+ yaffs_addr_to_chunk(dev, offset, &chunk, &start); -+ chunk++; -+ -+ /* OK now check for the curveball where the start and end are in -+ * the same chunk. -+ */ -+ if ((start + n) < dev->data_bytes_per_chunk) -+ n_copy = n; -+ else -+ n_copy = dev->data_bytes_per_chunk - start; -+ -+ cache = yaffs_find_chunk_cache(in, chunk); -+ -+ /* If the chunk is already in the cache or it is less than a whole chunk -+ * or we're using inband tags then use the cache (if there is caching) -+ * else bypass the cache. -+ */ -+ if (cache || n_copy != dev->data_bytes_per_chunk -+ || dev->param.inband_tags) { -+ if (dev->param.n_caches > 0) { -+ -+ /* If we can't find the data in the cache, then load it up. */ -+ -+ if (!cache) { -+ cache = -+ yaffs_grab_chunk_cache(in->my_dev); -+ cache->object = in; -+ cache->chunk_id = chunk; -+ cache->dirty = 0; -+ cache->locked = 0; -+ yaffs_rd_data_obj(in, chunk, -+ cache->data); -+ cache->n_bytes = 0; -+ } -+ -+ yaffs_use_cache(dev, cache, 0); -+ -+ cache->locked = 1; -+ -+ memcpy(buffer, &cache->data[start], n_copy); -+ -+ cache->locked = 0; -+ } else { -+ /* Read into the local buffer then copy.. */ -+ -+ u8 *local_buffer = -+ yaffs_get_temp_buffer(dev, __LINE__); -+ yaffs_rd_data_obj(in, chunk, local_buffer); -+ -+ memcpy(buffer, &local_buffer[start], n_copy); -+ -+ yaffs_release_temp_buffer(dev, local_buffer, -+ __LINE__); -+ } -+ -+ } else { -+ -+ /* A full chunk. Read directly into the supplied buffer. */ -+ yaffs_rd_data_obj(in, chunk, buffer); -+ -+ } -+ -+ n -= n_copy; -+ offset += n_copy; -+ buffer += n_copy; -+ n_done += n_copy; -+ -+ } -+ -+ return n_done; -+} -+ -+int yaffs_do_file_wr(struct yaffs_obj *in, const u8 * buffer, loff_t offset, -+ int n_bytes, int write_trhrough) -+{ -+ -+ int chunk; -+ u32 start; -+ int n_copy; -+ int n = n_bytes; -+ int n_done = 0; -+ int n_writeback; -+ int start_write = offset; -+ int chunk_written = 0; -+ u32 n_bytes_read; -+ u32 chunk_start; -+ -+ struct yaffs_dev *dev; -+ -+ dev = in->my_dev; -+ -+ while (n > 0 && chunk_written >= 0) { -+ yaffs_addr_to_chunk(dev, offset, &chunk, &start); -+ -+ if (chunk * dev->data_bytes_per_chunk + start != offset || -+ start >= dev->data_bytes_per_chunk) { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR -+ ("AddrToChunk of offset %d gives chunk %d start %d" -+ TENDSTR), (int)offset, chunk, start)); -+ } -+ chunk++; /* File pos to chunk in file offset */ -+ -+ /* OK now check for the curveball where the start and end are in -+ * the same chunk. -+ */ -+ -+ if ((start + n) < dev->data_bytes_per_chunk) { -+ n_copy = n; -+ -+ /* Now folks, to calculate how many bytes to write back.... -+ * If we're overwriting and not writing to then end of file then -+ * we need to write back as much as was there before. -+ */ -+ -+ chunk_start = ((chunk - 1) * dev->data_bytes_per_chunk); -+ -+ if (chunk_start > in->variant.file_variant.file_size) -+ n_bytes_read = 0; /* Past end of file */ -+ else -+ n_bytes_read = -+ in->variant.file_variant.file_size - -+ chunk_start; -+ -+ if (n_bytes_read > dev->data_bytes_per_chunk) -+ n_bytes_read = dev->data_bytes_per_chunk; -+ -+ n_writeback = -+ (n_bytes_read > -+ (start + n)) ? n_bytes_read : (start + n); -+ -+ if (n_writeback < 0 -+ || n_writeback > dev->data_bytes_per_chunk) -+ YBUG(); -+ -+ } else { -+ n_copy = dev->data_bytes_per_chunk - start; -+ n_writeback = dev->data_bytes_per_chunk; -+ } -+ -+ if (n_copy != dev->data_bytes_per_chunk -+ || dev->param.inband_tags) { -+ /* An incomplete start or end chunk (or maybe both start and end chunk), -+ * or we're using inband tags, so we want to use the cache buffers. -+ */ -+ if (dev->param.n_caches > 0) { -+ struct yaffs_cache *cache; -+ /* If we can't find the data in the cache, then load the cache */ -+ cache = yaffs_find_chunk_cache(in, chunk); -+ -+ if (!cache -+ && yaffs_check_alloc_available(dev, 1)) { -+ cache = yaffs_grab_chunk_cache(dev); -+ cache->object = in; -+ cache->chunk_id = chunk; -+ cache->dirty = 0; -+ cache->locked = 0; -+ yaffs_rd_data_obj(in, chunk, -+ cache->data); -+ } else if (cache && -+ !cache->dirty && -+ !yaffs_check_alloc_available(dev, -+ 1)) { -+ /* Drop the cache if it was a read cache item and -+ * no space check has been made for it. -+ */ -+ cache = NULL; -+ } -+ -+ if (cache) { -+ yaffs_use_cache(dev, cache, 1); -+ cache->locked = 1; -+ -+ memcpy(&cache->data[start], buffer, -+ n_copy); -+ -+ cache->locked = 0; -+ cache->n_bytes = n_writeback; -+ -+ if (write_trhrough) { -+ chunk_written = -+ yaffs_wr_data_obj -+ (cache->object, -+ cache->chunk_id, -+ cache->data, -+ cache->n_bytes, 1); -+ cache->dirty = 0; -+ } -+ -+ } else { -+ chunk_written = -1; /* fail the write */ -+ } -+ } else { -+ /* An incomplete start or end chunk (or maybe both start and end chunk) -+ * Read into the local buffer then copy, then copy over and write back. -+ */ -+ -+ u8 *local_buffer = -+ yaffs_get_temp_buffer(dev, __LINE__); -+ -+ yaffs_rd_data_obj(in, chunk, local_buffer); -+ -+ memcpy(&local_buffer[start], buffer, n_copy); -+ -+ chunk_written = -+ yaffs_wr_data_obj(in, chunk, -+ local_buffer, -+ n_writeback, 0); -+ -+ yaffs_release_temp_buffer(dev, local_buffer, -+ __LINE__); -+ -+ } -+ -+ } else { -+ /* A full chunk. Write directly from the supplied buffer. */ -+ -+ chunk_written = -+ yaffs_wr_data_obj(in, chunk, buffer, -+ dev->data_bytes_per_chunk, 0); -+ -+ /* Since we've overwritten the cached data, we better invalidate it. */ -+ yaffs_invalidate_chunk_cache(in, chunk); -+ } -+ -+ if (chunk_written >= 0) { -+ n -= n_copy; -+ offset += n_copy; -+ buffer += n_copy; -+ n_done += n_copy; -+ } -+ -+ } -+ -+ /* Update file object */ -+ -+ if ((start_write + n_done) > in->variant.file_variant.file_size) -+ in->variant.file_variant.file_size = (start_write + n_done); -+ -+ in->dirty = 1; -+ -+ return n_done; -+} -+ -+int yaffs_wr_file(struct yaffs_obj *in, const u8 * buffer, loff_t offset, -+ int n_bytes, int write_trhrough) -+{ -+ yaffs2_handle_hole(in, offset); -+ return yaffs_do_file_wr(in, buffer, offset, n_bytes, write_trhrough); -+} -+ -+/* ---------------------- File resizing stuff ------------------ */ -+ -+static void yaffs_prune_chunks(struct yaffs_obj *in, int new_size) -+{ -+ -+ struct yaffs_dev *dev = in->my_dev; -+ int old_size = in->variant.file_variant.file_size; -+ -+ int last_del = 1 + (old_size - 1) / dev->data_bytes_per_chunk; -+ -+ int start_del = 1 + (new_size + dev->data_bytes_per_chunk - 1) / -+ dev->data_bytes_per_chunk; -+ int i; -+ int chunk_id; -+ -+ /* Delete backwards so that we don't end up with holes if -+ * power is lost part-way through the operation. -+ */ -+ for (i = last_del; i >= start_del; i--) { -+ /* NB this could be optimised somewhat, -+ * eg. could retrieve the tags and write them without -+ * using yaffs_chunk_del -+ */ -+ -+ chunk_id = yaffs_find_del_file_chunk(in, i, NULL); -+ if (chunk_id > 0) { -+ if (chunk_id < -+ (dev->internal_start_block * -+ dev->param.chunks_per_block) -+ || chunk_id >= -+ ((dev->internal_end_block + -+ 1) * dev->param.chunks_per_block)) { -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR -+ ("Found daft chunk_id %d for %d" TENDSTR), -+ chunk_id, i)); -+ } else { -+ in->n_data_chunks--; -+ yaffs_chunk_del(dev, chunk_id, 1, __LINE__); -+ } -+ } -+ } -+ -+} -+ -+void yaffs_resize_file_down(struct yaffs_obj *obj, loff_t new_size) -+{ -+ int new_full; -+ u32 new_partial; -+ struct yaffs_dev *dev = obj->my_dev; -+ -+ yaffs_addr_to_chunk(dev, new_size, &new_full, &new_partial); -+ -+ yaffs_prune_chunks(obj, new_size); -+ -+ if (new_partial != 0) { -+ int last_chunk = 1 + new_full; -+ u8 *local_buffer = yaffs_get_temp_buffer(dev, __LINE__); -+ -+ /* Got to read and rewrite the last chunk with its new size and zero pad */ -+ yaffs_rd_data_obj(obj, last_chunk, local_buffer); -+ memset(local_buffer + new_partial, 0, -+ dev->data_bytes_per_chunk - new_partial); -+ -+ yaffs_wr_data_obj(obj, last_chunk, local_buffer, -+ new_partial, 1); -+ -+ yaffs_release_temp_buffer(dev, local_buffer, __LINE__); -+ } -+ -+ obj->variant.file_variant.file_size = new_size; -+ -+ yaffs_prune_tree(dev, &obj->variant.file_variant); -+} -+ -+int yaffs_resize_file(struct yaffs_obj *in, loff_t new_size) -+{ -+ struct yaffs_dev *dev = in->my_dev; -+ int old_size = in->variant.file_variant.file_size; -+ -+ yaffs_flush_file_cache(in); -+ yaffs_invalidate_whole_cache(in); -+ -+ yaffs_check_gc(dev, 0); -+ -+ if (in->variant_type != YAFFS_OBJECT_TYPE_FILE) -+ return YAFFS_FAIL; -+ -+ if (new_size == old_size) -+ return YAFFS_OK; -+ -+ if (new_size > old_size) { -+ yaffs2_handle_hole(in, new_size); -+ in->variant.file_variant.file_size = new_size; -+ } else { -+ /* new_size < old_size */ -+ yaffs_resize_file_down(in, new_size); -+ } -+ -+ /* Write a new object header to reflect the resize. -+ * show we've shrunk the file, if need be -+ * Do this only if the file is not in the deleted directories -+ * and is not shadowed. -+ */ -+ if (in->parent && -+ !in->is_shadowed && -+ in->parent->obj_id != YAFFS_OBJECTID_UNLINKED && -+ in->parent->obj_id != YAFFS_OBJECTID_DELETED) -+ yaffs_update_oh(in, NULL, 0, 0, 0, NULL); -+ -+ return YAFFS_OK; -+} -+ -+int yaffs_flush_file(struct yaffs_obj *in, int update_time, int data_sync) -+{ -+ int ret_val; -+ if (in->dirty) { -+ yaffs_flush_file_cache(in); -+ if (data_sync) /* Only sync data */ -+ ret_val = YAFFS_OK; -+ else { -+ if (update_time) -+ yaffs_load_current_time(in, 0, 0); -+ -+ ret_val = (yaffs_update_oh(in, NULL, 0, 0, 0, NULL) >= -+ 0) ? YAFFS_OK : YAFFS_FAIL; -+ } -+ } else { -+ ret_val = YAFFS_OK; -+ } -+ -+ return ret_val; -+ -+} -+ -+static int yaffs_generic_obj_del(struct yaffs_obj *in) -+{ -+ -+ /* First off, invalidate the file's data in the cache, without flushing. */ -+ yaffs_invalidate_whole_cache(in); -+ -+ if (in->my_dev->param.is_yaffs2 && (in->parent != in->my_dev->del_dir)) { -+ /* Move to the unlinked directory so we have a record that it was deleted. */ -+ yaffs_change_obj_name(in, in->my_dev->del_dir, _Y("deleted"), 0, -+ 0); -+ -+ } -+ -+ yaffs_remove_obj_from_dir(in); -+ yaffs_chunk_del(in->my_dev, in->hdr_chunk, 1, __LINE__); -+ in->hdr_chunk = 0; -+ -+ yaffs_free_obj(in); -+ return YAFFS_OK; -+ -+} -+ -+/* yaffs_del_file deletes the whole file data -+ * and the inode associated with the file. -+ * It does not delete the links associated with the file. -+ */ -+static int yaffs_unlink_file_if_needed(struct yaffs_obj *in) -+{ -+ -+ int ret_val; -+ int del_now = 0; -+ struct yaffs_dev *dev = in->my_dev; -+ -+ if (!in->my_inode) -+ del_now = 1; -+ -+ if (del_now) { -+ ret_val = -+ yaffs_change_obj_name(in, in->my_dev->del_dir, -+ _Y("deleted"), 0, 0); -+ T(YAFFS_TRACE_TRACING, -+ (TSTR("yaffs: immediate deletion of file %d" TENDSTR), -+ in->obj_id)); -+ in->deleted = 1; -+ in->my_dev->n_deleted_files++; -+ if (dev->param.disable_soft_del || dev->param.is_yaffs2) -+ yaffs_resize_file(in, 0); -+ yaffs_soft_del_file(in); -+ } else { -+ ret_val = -+ yaffs_change_obj_name(in, in->my_dev->unlinked_dir, -+ _Y("unlinked"), 0, 0); -+ } -+ -+ return ret_val; -+} -+ -+int yaffs_del_file(struct yaffs_obj *in) -+{ -+ int ret_val = YAFFS_OK; -+ int deleted; /* Need to cache value on stack if in is freed */ -+ struct yaffs_dev *dev = in->my_dev; -+ -+ if (dev->param.disable_soft_del || dev->param.is_yaffs2) -+ yaffs_resize_file(in, 0); -+ -+ if (in->n_data_chunks > 0) { -+ /* Use soft deletion if there is data in the file. -+ * That won't be the case if it has been resized to zero. -+ */ -+ if (!in->unlinked) -+ ret_val = yaffs_unlink_file_if_needed(in); -+ -+ deleted = in->deleted; -+ -+ if (ret_val == YAFFS_OK && in->unlinked && !in->deleted) { -+ in->deleted = 1; -+ deleted = 1; -+ in->my_dev->n_deleted_files++; -+ yaffs_soft_del_file(in); -+ } -+ return deleted ? YAFFS_OK : YAFFS_FAIL; -+ } else { -+ /* The file has no data chunks so we toss it immediately */ -+ yaffs_free_tnode(in->my_dev, in->variant.file_variant.top); -+ in->variant.file_variant.top = NULL; -+ yaffs_generic_obj_del(in); -+ -+ return YAFFS_OK; -+ } -+} -+ -+static int yaffs_is_non_empty_dir(struct yaffs_obj *obj) -+{ -+ return (obj->variant_type == YAFFS_OBJECT_TYPE_DIRECTORY) && -+ !(list_empty(&obj->variant.dir_variant.children)); -+} -+ -+static int yaffs_del_dir(struct yaffs_obj *obj) -+{ -+ /* First check that the directory is empty. */ -+ if (yaffs_is_non_empty_dir(obj)) -+ return YAFFS_FAIL; -+ -+ return yaffs_generic_obj_del(obj); -+} -+ -+static int yaffs_del_symlink(struct yaffs_obj *in) -+{ -+ if (in->variant.symlink_variant.alias) -+ YFREE(in->variant.symlink_variant.alias); -+ in->variant.symlink_variant.alias = NULL; -+ -+ return yaffs_generic_obj_del(in); -+} -+ -+static int yaffs_del_link(struct yaffs_obj *in) -+{ -+ /* remove this hardlink from the list assocaited with the equivalent -+ * object -+ */ -+ list_del_init(&in->hard_links); -+ return yaffs_generic_obj_del(in); -+} -+ -+int yaffs_del_obj(struct yaffs_obj *obj) -+{ -+ int ret_val = -1; -+ switch (obj->variant_type) { -+ case YAFFS_OBJECT_TYPE_FILE: -+ ret_val = yaffs_del_file(obj); -+ break; -+ case YAFFS_OBJECT_TYPE_DIRECTORY: -+ if (!list_empty(&obj->variant.dir_variant.dirty)) { -+ T(YAFFS_TRACE_BACKGROUND, -+ (TSTR -+ ("Remove object %d from dirty directories" TENDSTR), -+ obj->obj_id)); -+ list_del_init(&obj->variant.dir_variant.dirty); -+ } -+ return yaffs_del_dir(obj); -+ break; -+ case YAFFS_OBJECT_TYPE_SYMLINK: -+ ret_val = yaffs_del_symlink(obj); -+ break; -+ case YAFFS_OBJECT_TYPE_HARDLINK: -+ ret_val = yaffs_del_link(obj); -+ break; -+ case YAFFS_OBJECT_TYPE_SPECIAL: -+ ret_val = yaffs_generic_obj_del(obj); -+ break; -+ case YAFFS_OBJECT_TYPE_UNKNOWN: -+ ret_val = 0; -+ break; /* should not happen. */ -+ } -+ -+ return ret_val; -+} -+ -+static int yaffs_unlink_worker(struct yaffs_obj *obj) -+{ -+ -+ int del_now = 0; -+ -+ if (!obj->my_inode) -+ del_now = 1; -+ -+ if (obj) -+ yaffs_update_parent(obj->parent); -+ -+ if (obj->variant_type == YAFFS_OBJECT_TYPE_HARDLINK) { -+ return yaffs_del_link(obj); -+ } else if (!list_empty(&obj->hard_links)) { -+ /* Curve ball: We're unlinking an object that has a hardlink. -+ * -+ * This problem arises because we are not strictly following -+ * The Linux link/inode model. -+ * -+ * We can't really delete the object. -+ * Instead, we do the following: -+ * - Select a hardlink. -+ * - Unhook it from the hard links -+ * - Move it from its parent directory (so that the rename can work) -+ * - Rename the object to the hardlink's name. -+ * - Delete the hardlink -+ */ -+ -+ struct yaffs_obj *hl; -+ struct yaffs_obj *parent; -+ int ret_val; -+ YCHAR name[YAFFS_MAX_NAME_LENGTH + 1]; -+ -+ hl = list_entry(obj->hard_links.next, struct yaffs_obj, -+ hard_links); -+ -+ yaffs_get_obj_name(hl, name, YAFFS_MAX_NAME_LENGTH + 1); -+ parent = hl->parent; -+ -+ list_del_init(&hl->hard_links); -+ -+ yaffs_add_obj_to_dir(obj->my_dev->unlinked_dir, hl); -+ -+ ret_val = yaffs_change_obj_name(obj, parent, name, 0, 0); -+ -+ if (ret_val == YAFFS_OK) -+ ret_val = yaffs_generic_obj_del(hl); -+ -+ return ret_val; -+ -+ } else if (del_now) { -+ switch (obj->variant_type) { -+ case YAFFS_OBJECT_TYPE_FILE: -+ return yaffs_del_file(obj); -+ break; -+ case YAFFS_OBJECT_TYPE_DIRECTORY: -+ list_del_init(&obj->variant.dir_variant.dirty); -+ return yaffs_del_dir(obj); -+ break; -+ case YAFFS_OBJECT_TYPE_SYMLINK: -+ return yaffs_del_symlink(obj); -+ break; -+ case YAFFS_OBJECT_TYPE_SPECIAL: -+ return yaffs_generic_obj_del(obj); -+ break; -+ case YAFFS_OBJECT_TYPE_HARDLINK: -+ case YAFFS_OBJECT_TYPE_UNKNOWN: -+ default: -+ return YAFFS_FAIL; -+ } -+ } else if (yaffs_is_non_empty_dir(obj)) { -+ return YAFFS_FAIL; -+ } else { -+ return yaffs_change_obj_name(obj, obj->my_dev->unlinked_dir, -+ _Y("unlinked"), 0, 0); -+ } -+} -+ -+static int yaffs_unlink_obj(struct yaffs_obj *obj) -+{ -+ -+ if (obj && obj->unlink_allowed) -+ return yaffs_unlink_worker(obj); -+ -+ return YAFFS_FAIL; -+ -+} -+ -+int yaffs_unlinker(struct yaffs_obj *dir, const YCHAR * name) -+{ -+ struct yaffs_obj *obj; -+ -+ obj = yaffs_find_by_name(dir, name); -+ return yaffs_unlink_obj(obj); -+} -+ -+/*----------------------- Initialisation Scanning ---------------------- */ -+ -+void yaffs_handle_shadowed_obj(struct yaffs_dev *dev, int obj_id, -+ int backward_scanning) -+{ -+ struct yaffs_obj *obj; -+ -+ if (!backward_scanning) { -+ /* Handle YAFFS1 forward scanning case -+ * For YAFFS1 we always do the deletion -+ */ -+ -+ } else { -+ /* Handle YAFFS2 case (backward scanning) -+ * If the shadowed object exists then ignore. -+ */ -+ obj = yaffs_find_by_number(dev, obj_id); -+ if (obj) -+ return; -+ } -+ -+ /* Let's create it (if it does not exist) assuming it is a file so that it can do shrinking etc. -+ * We put it in unlinked dir to be cleaned up after the scanning -+ */ -+ obj = -+ yaffs_find_or_create_by_number(dev, obj_id, YAFFS_OBJECT_TYPE_FILE); -+ if (!obj) -+ return; -+ obj->is_shadowed = 1; -+ yaffs_add_obj_to_dir(dev->unlinked_dir, obj); -+ obj->variant.file_variant.shrink_size = 0; -+ obj->valid = 1; /* So that we don't read any other info for this file */ -+ -+} -+ -+void yaffs_link_fixup(struct yaffs_dev *dev, struct yaffs_obj *hard_list) -+{ -+ struct yaffs_obj *hl; -+ struct yaffs_obj *in; -+ -+ while (hard_list) { -+ hl = hard_list; -+ hard_list = (struct yaffs_obj *)(hard_list->hard_links.next); -+ -+ in = yaffs_find_by_number(dev, -+ hl->variant. -+ hardlink_variant.equiv_id); -+ -+ if (in) { -+ /* Add the hardlink pointers */ -+ hl->variant.hardlink_variant.equiv_obj = in; -+ list_add(&hl->hard_links, &in->hard_links); -+ } else { -+ /* Todo Need to report/handle this better. -+ * Got a problem... hardlink to a non-existant object -+ */ -+ hl->variant.hardlink_variant.equiv_obj = NULL; -+ INIT_LIST_HEAD(&hl->hard_links); -+ -+ } -+ } -+} -+ -+static void yaffs_strip_deleted_objs(struct yaffs_dev *dev) -+{ -+ /* -+ * Sort out state of unlinked and deleted objects after scanning. -+ */ -+ struct list_head *i; -+ struct list_head *n; -+ struct yaffs_obj *l; -+ -+ if (dev->read_only) -+ return; -+ -+ /* Soft delete all the unlinked files */ -+ list_for_each_safe(i, n, -+ &dev->unlinked_dir->variant.dir_variant.children) { -+ if (i) { -+ l = list_entry(i, struct yaffs_obj, siblings); -+ yaffs_del_obj(l); -+ } -+ } -+ -+ list_for_each_safe(i, n, &dev->del_dir->variant.dir_variant.children) { -+ if (i) { -+ l = list_entry(i, struct yaffs_obj, siblings); -+ yaffs_del_obj(l); -+ } -+ } -+ -+} -+ -+/* -+ * This code iterates through all the objects making sure that they are rooted. -+ * Any unrooted objects are re-rooted in lost+found. -+ * An object needs to be in one of: -+ * - Directly under deleted, unlinked -+ * - Directly or indirectly under root. -+ * -+ * Note: -+ * This code assumes that we don't ever change the current relationships between -+ * directories: -+ * root_dir->parent == unlinked_dir->parent == del_dir->parent == NULL -+ * lost-n-found->parent == root_dir -+ * -+ * This fixes the problem where directories might have inadvertently been deleted -+ * leaving the object "hanging" without being rooted in the directory tree. -+ */ -+ -+static int yaffs_has_null_parent(struct yaffs_dev *dev, struct yaffs_obj *obj) -+{ -+ return (obj == dev->del_dir || -+ obj == dev->unlinked_dir || obj == dev->root_dir); -+} -+ -+static void yaffs_fix_hanging_objs(struct yaffs_dev *dev) -+{ -+ struct yaffs_obj *obj; -+ struct yaffs_obj *parent; -+ int i; -+ struct list_head *lh; -+ struct list_head *n; -+ int depth_limit; -+ int hanging; -+ -+ if (dev->read_only) -+ return; -+ -+ /* Iterate through the objects in each hash entry, -+ * looking at each object. -+ * Make sure it is rooted. -+ */ -+ -+ for (i = 0; i < YAFFS_NOBJECT_BUCKETS; i++) { -+ list_for_each_safe(lh, n, &dev->obj_bucket[i].list) { -+ if (lh) { -+ obj = -+ list_entry(lh, struct yaffs_obj, hash_link); -+ parent = obj->parent; -+ -+ if (yaffs_has_null_parent(dev, obj)) { -+ /* These directories are not hanging */ -+ hanging = 0; -+ } else if (!parent -+ || parent->variant_type != -+ YAFFS_OBJECT_TYPE_DIRECTORY) { -+ hanging = 1; -+ } else if (yaffs_has_null_parent(dev, parent)) { -+ hanging = 0; -+ } else { -+ /* -+ * Need to follow the parent chain to see if it is hanging. -+ */ -+ hanging = 0; -+ depth_limit = 100; -+ -+ while (parent != dev->root_dir && -+ parent->parent && -+ parent->parent->variant_type == -+ YAFFS_OBJECT_TYPE_DIRECTORY -+ && depth_limit > 0) { -+ parent = parent->parent; -+ depth_limit--; -+ } -+ if (parent != dev->root_dir) -+ hanging = 1; -+ } -+ if (hanging) { -+ T(YAFFS_TRACE_SCAN, -+ (TSTR -+ ("Hanging object %d moved to lost and found" -+ TENDSTR), obj->obj_id)); -+ yaffs_add_obj_to_dir(dev->lost_n_found, -+ obj); -+ } -+ } -+ } -+ } -+} -+ -+/* -+ * Delete directory contents for cleaning up lost and found. -+ */ -+static void yaffs_del_dir_contents(struct yaffs_obj *dir) -+{ -+ struct yaffs_obj *obj; -+ struct list_head *lh; -+ struct list_head *n; -+ -+ if (dir->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) -+ YBUG(); -+ -+ list_for_each_safe(lh, n, &dir->variant.dir_variant.children) { -+ if (lh) { -+ obj = list_entry(lh, struct yaffs_obj, siblings); -+ if (obj->variant_type == YAFFS_OBJECT_TYPE_DIRECTORY) -+ yaffs_del_dir_contents(obj); -+ -+ T(YAFFS_TRACE_SCAN, -+ (TSTR("Deleting lost_found object %d" TENDSTR), -+ obj->obj_id)); -+ -+ /* Need to use UnlinkObject since Delete would not handle -+ * hardlinked objects correctly. -+ */ -+ yaffs_unlink_obj(obj); -+ } -+ } -+ -+} -+ -+static void yaffs_empty_l_n_f(struct yaffs_dev *dev) -+{ -+ yaffs_del_dir_contents(dev->lost_n_found); -+} -+ -+static void yaffs_check_obj_details_loaded(struct yaffs_obj *in) -+{ -+ u8 *chunk_data; -+ struct yaffs_obj_hdr *oh; -+ struct yaffs_dev *dev; -+ struct yaffs_ext_tags tags; -+ int result; -+ int alloc_failed = 0; -+ -+ if (!in) -+ return; -+ -+ dev = in->my_dev; -+ -+ if (in->lazy_loaded && in->hdr_chunk > 0) { -+ in->lazy_loaded = 0; -+ chunk_data = yaffs_get_temp_buffer(dev, __LINE__); -+ -+ result = -+ yaffs_rd_chunk_tags_nand(dev, in->hdr_chunk, chunk_data, -+ &tags); -+ oh = (struct yaffs_obj_hdr *)chunk_data; -+ -+ in->yst_mode = oh->yst_mode; -+ yaffs_load_attribs(in, oh); -+ yaffs_set_obj_name_from_oh(in, oh); -+ -+ if (in->variant_type == YAFFS_OBJECT_TYPE_SYMLINK) { -+ in->variant.symlink_variant.alias = -+ yaffs_clone_str(oh->alias); -+ if (!in->variant.symlink_variant.alias) -+ alloc_failed = 1; /* Not returned to caller */ -+ } -+ -+ yaffs_release_temp_buffer(dev, chunk_data, __LINE__); -+ } -+} -+ -+/*------------------------------ Directory Functions ----------------------------- */ -+ -+/* -+ *yaffs_update_parent() handles fixing a directories mtime and ctime when a new -+ * link (ie. name) is created or deleted in the directory. -+ * -+ * ie. -+ * create dir/a : update dir's mtime/ctime -+ * rm dir/a: update dir's mtime/ctime -+ * modify dir/a: don't update dir's mtimme/ctime -+ * -+ * This can be handled immediately or defered. Defering helps reduce the number -+ * of updates when many files in a directory are changed within a brief period. -+ * -+ * If the directory updating is defered then yaffs_update_dirty_dirs must be -+ * called periodically. -+ */ -+ -+static void yaffs_update_parent(struct yaffs_obj *obj) -+{ -+ struct yaffs_dev *dev; -+ if (!obj) -+ return; -+ dev = obj->my_dev; -+ obj->dirty = 1; -+ yaffs_load_current_time(obj, 0, 1); -+ if (dev->param.defered_dir_update) { -+ struct list_head *link = &obj->variant.dir_variant.dirty; -+ -+ if (list_empty(link)) { -+ list_add(link, &dev->dirty_dirs); -+ T(YAFFS_TRACE_BACKGROUND, -+ (TSTR("Added object %d to dirty directories" TENDSTR), -+ obj->obj_id)); -+ } -+ -+ } else { -+ yaffs_update_oh(obj, NULL, 0, 0, 0, NULL); -+ } -+} -+ -+void yaffs_update_dirty_dirs(struct yaffs_dev *dev) -+{ -+ struct list_head *link; -+ struct yaffs_obj *obj; -+ struct yaffs_dir_var *d_s; -+ union yaffs_obj_var *o_v; -+ -+ T(YAFFS_TRACE_BACKGROUND, (TSTR("Update dirty directories" TENDSTR))); -+ -+ while (!list_empty(&dev->dirty_dirs)) { -+ link = dev->dirty_dirs.next; -+ list_del_init(link); -+ -+ d_s = list_entry(link, struct yaffs_dir_var, dirty); -+ o_v = list_entry(d_s, union yaffs_obj_var, dir_variant); -+ obj = list_entry(o_v, struct yaffs_obj, variant); -+ -+ T(YAFFS_TRACE_BACKGROUND, -+ (TSTR("Update directory %d" TENDSTR), obj->obj_id)); -+ -+ if (obj->dirty) -+ yaffs_update_oh(obj, NULL, 0, 0, 0, NULL); -+ } -+} -+ -+static void yaffs_remove_obj_from_dir(struct yaffs_obj *obj) -+{ -+ struct yaffs_dev *dev = obj->my_dev; -+ struct yaffs_obj *parent; -+ -+ yaffs_verify_obj_in_dir(obj); -+ parent = obj->parent; -+ -+ yaffs_verify_dir(parent); -+ -+ if (dev && dev->param.remove_obj_fn) -+ dev->param.remove_obj_fn(obj); -+ -+ list_del_init(&obj->siblings); -+ obj->parent = NULL; -+ -+ yaffs_verify_dir(parent); -+} -+ -+void yaffs_add_obj_to_dir(struct yaffs_obj *directory, struct yaffs_obj *obj) -+{ -+ if (!directory) { -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR -+ ("tragedy: Trying to add an object to a null pointer directory" -+ TENDSTR))); -+ YBUG(); -+ return; -+ } -+ if (directory->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) { -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR -+ ("tragedy: Trying to add an object to a non-directory" -+ TENDSTR))); -+ YBUG(); -+ } -+ -+ if (obj->siblings.prev == NULL) { -+ /* Not initialised */ -+ YBUG(); -+ } -+ -+ yaffs_verify_dir(directory); -+ -+ yaffs_remove_obj_from_dir(obj); -+ -+ /* Now add it */ -+ list_add(&obj->siblings, &directory->variant.dir_variant.children); -+ obj->parent = directory; -+ -+ if (directory == obj->my_dev->unlinked_dir -+ || directory == obj->my_dev->del_dir) { -+ obj->unlinked = 1; -+ obj->my_dev->n_unlinked_files++; -+ obj->rename_allowed = 0; -+ } -+ -+ yaffs_verify_dir(directory); -+ yaffs_verify_obj_in_dir(obj); -+} -+ -+struct yaffs_obj *yaffs_find_by_name(struct yaffs_obj *directory, -+ const YCHAR * name) -+{ -+ int sum; -+ -+ struct list_head *i; -+ YCHAR buffer[YAFFS_MAX_NAME_LENGTH + 1]; -+ -+ struct yaffs_obj *l; -+ -+ if (!name) -+ return NULL; -+ -+ if (!directory) { -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR -+ ("tragedy: yaffs_find_by_name: null pointer directory" -+ TENDSTR))); -+ YBUG(); -+ return NULL; -+ } -+ if (directory->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) { -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR("tragedy: yaffs_find_by_name: non-directory" TENDSTR))); -+ YBUG(); -+ } -+ -+ sum = yaffs_calc_name_sum(name); -+ -+ list_for_each(i, &directory->variant.dir_variant.children) { -+ if (i) { -+ l = list_entry(i, struct yaffs_obj, siblings); -+ -+ if (l->parent != directory) -+ YBUG(); -+ -+ yaffs_check_obj_details_loaded(l); -+ -+ /* Special case for lost-n-found */ -+ if (l->obj_id == YAFFS_OBJECTID_LOSTNFOUND) { -+ if (!yaffs_strcmp(name, YAFFS_LOSTNFOUND_NAME)) -+ return l; -+ } else if (yaffs_sum_cmp(l->sum, sum) -+ || l->hdr_chunk <= 0) { -+ /* LostnFound chunk called Objxxx -+ * Do a real check -+ */ -+ yaffs_get_obj_name(l, buffer, -+ YAFFS_MAX_NAME_LENGTH + 1); -+ if (yaffs_strncmp -+ (name, buffer, YAFFS_MAX_NAME_LENGTH) == 0) -+ return l; -+ } -+ } -+ } -+ -+ return NULL; -+} -+ -+/* GetEquivalentObject dereferences any hard links to get to the -+ * actual object. -+ */ -+ -+struct yaffs_obj *yaffs_get_equivalent_obj(struct yaffs_obj *obj) -+{ -+ if (obj && obj->variant_type == YAFFS_OBJECT_TYPE_HARDLINK) { -+ /* We want the object id of the equivalent object, not this one */ -+ obj = obj->variant.hardlink_variant.equiv_obj; -+ yaffs_check_obj_details_loaded(obj); -+ } -+ return obj; -+} -+ -+/* -+ * A note or two on object names. -+ * * If the object name is missing, we then make one up in the form objnnn -+ * -+ * * ASCII names are stored in the object header's name field from byte zero -+ * * Unicode names are historically stored starting from byte zero. -+ * -+ * Then there are automatic Unicode names... -+ * The purpose of these is to save names in a way that can be read as -+ * ASCII or Unicode names as appropriate, thus allowing a Unicode and ASCII -+ * system to share files. -+ * -+ * These automatic unicode are stored slightly differently... -+ * - If the name can fit in the ASCII character space then they are saved as -+ * ascii names as per above. -+ * - If the name needs Unicode then the name is saved in Unicode -+ * starting at oh->name[1]. -+ -+ */ -+static void yaffs_fix_null_name(struct yaffs_obj *obj, YCHAR * name, -+ int buffer_size) -+{ -+ /* Create an object name if we could not find one. */ -+ if (yaffs_strnlen(name, YAFFS_MAX_NAME_LENGTH) == 0) { -+ YCHAR local_name[20]; -+ YCHAR num_string[20]; -+ YCHAR *x = &num_string[19]; -+ unsigned v = obj->obj_id; -+ num_string[19] = 0; -+ while (v > 0) { -+ x--; -+ *x = '0' + (v % 10); -+ v /= 10; -+ } -+ /* make up a name */ -+ yaffs_strcpy(local_name, YAFFS_LOSTNFOUND_PREFIX); -+ yaffs_strcat(local_name, x); -+ yaffs_strncpy(name, local_name, buffer_size - 1); -+ } -+} -+ -+static void yaffs_load_name_from_oh(struct yaffs_dev *dev, YCHAR * name, -+ const YCHAR * oh_name, int buff_size) -+{ -+#ifdef CONFIG_YAFFS_AUTO_UNICODE -+ if (dev->param.auto_unicode) { -+ if (*oh_name) { -+ /* It is an ASCII name, so do an ASCII to unicode conversion */ -+ const char *ascii_oh_name = (const char *)oh_name; -+ int n = buff_size - 1; -+ while (n > 0 && *ascii_oh_name) { -+ *name = *ascii_oh_name; -+ name++; -+ ascii_oh_name++; -+ n--; -+ } -+ } else { -+ yaffs_strncpy(name, oh_name + 1, buff_size - 1); -+ } -+ } else { -+#else -+ { -+#endif -+ yaffs_strncpy(name, oh_name, buff_size - 1); -+ } -+} -+ -+static void yaffs_load_oh_from_name(struct yaffs_dev *dev, YCHAR * oh_name, -+ const YCHAR * name) -+{ -+#ifdef CONFIG_YAFFS_AUTO_UNICODE -+ -+ int is_ascii; -+ YCHAR *w; -+ -+ if (dev->param.auto_unicode) { -+ -+ is_ascii = 1; -+ w = name; -+ -+ /* Figure out if the name will fit in ascii character set */ -+ while (is_ascii && *w) { -+ if ((*w) & 0xff00) -+ is_ascii = 0; -+ w++; -+ } -+ -+ if (is_ascii) { -+ /* It is an ASCII name, so do a unicode to ascii conversion */ -+ char *ascii_oh_name = (char *)oh_name; -+ int n = YAFFS_MAX_NAME_LENGTH - 1; -+ while (n > 0 && *name) { -+ *ascii_oh_name = *name; -+ name++; -+ ascii_oh_name++; -+ n--; -+ } -+ } else { -+ /* It is a unicode name, so save starting at the second YCHAR */ -+ *oh_name = 0; -+ yaffs_strncpy(oh_name + 1, name, -+ YAFFS_MAX_NAME_LENGTH - 2); -+ } -+ } else { -+#else -+ { -+#endif -+ yaffs_strncpy(oh_name, name, YAFFS_MAX_NAME_LENGTH - 1); -+ } -+ -+} -+ -+int yaffs_get_obj_name(struct yaffs_obj *obj, YCHAR * name, int buffer_size) -+{ -+ memset(name, 0, buffer_size * sizeof(YCHAR)); -+ -+ yaffs_check_obj_details_loaded(obj); -+ -+ if (obj->obj_id == YAFFS_OBJECTID_LOSTNFOUND) { -+ yaffs_strncpy(name, YAFFS_LOSTNFOUND_NAME, buffer_size - 1); -+ } -+#ifndef CONFIG_YAFFS_NO_SHORT_NAMES -+ else if (obj->short_name[0]) { -+ yaffs_strcpy(name, obj->short_name); -+ } -+#endif -+ else if (obj->hdr_chunk > 0) { -+ int result; -+ u8 *buffer = yaffs_get_temp_buffer(obj->my_dev, __LINE__); -+ -+ struct yaffs_obj_hdr *oh = (struct yaffs_obj_hdr *)buffer; -+ -+ memset(buffer, 0, obj->my_dev->data_bytes_per_chunk); -+ -+ if (obj->hdr_chunk > 0) { -+ result = yaffs_rd_chunk_tags_nand(obj->my_dev, -+ obj->hdr_chunk, -+ buffer, NULL); -+ } -+ yaffs_load_name_from_oh(obj->my_dev, name, oh->name, -+ buffer_size); -+ -+ yaffs_release_temp_buffer(obj->my_dev, buffer, __LINE__); -+ } -+ -+ yaffs_fix_null_name(obj, name, buffer_size); -+ -+ return yaffs_strnlen(name, YAFFS_MAX_NAME_LENGTH); -+} -+ -+int yaffs_get_obj_length(struct yaffs_obj *obj) -+{ -+ /* Dereference any hard linking */ -+ obj = yaffs_get_equivalent_obj(obj); -+ -+ if (obj->variant_type == YAFFS_OBJECT_TYPE_FILE) -+ return obj->variant.file_variant.file_size; -+ if (obj->variant_type == YAFFS_OBJECT_TYPE_SYMLINK) { -+ if (!obj->variant.symlink_variant.alias) -+ return 0; -+ return yaffs_strnlen(obj->variant.symlink_variant.alias, -+ YAFFS_MAX_ALIAS_LENGTH); -+ } else { -+ /* Only a directory should drop through to here */ -+ return obj->my_dev->data_bytes_per_chunk; -+ } -+} -+ -+int yaffs_get_obj_link_count(struct yaffs_obj *obj) -+{ -+ int count = 0; -+ struct list_head *i; -+ -+ if (!obj->unlinked) -+ count++; /* the object itself */ -+ -+ list_for_each(i, &obj->hard_links) -+ count++; /* add the hard links; */ -+ -+ return count; -+} -+ -+int yaffs_get_obj_inode(struct yaffs_obj *obj) -+{ -+ obj = yaffs_get_equivalent_obj(obj); -+ -+ return obj->obj_id; -+} -+ -+unsigned yaffs_get_obj_type(struct yaffs_obj *obj) -+{ -+ obj = yaffs_get_equivalent_obj(obj); -+ -+ switch (obj->variant_type) { -+ case YAFFS_OBJECT_TYPE_FILE: -+ return DT_REG; -+ break; -+ case YAFFS_OBJECT_TYPE_DIRECTORY: -+ return DT_DIR; -+ break; -+ case YAFFS_OBJECT_TYPE_SYMLINK: -+ return DT_LNK; -+ break; -+ case YAFFS_OBJECT_TYPE_HARDLINK: -+ return DT_REG; -+ break; -+ case YAFFS_OBJECT_TYPE_SPECIAL: -+ if (S_ISFIFO(obj->yst_mode)) -+ return DT_FIFO; -+ if (S_ISCHR(obj->yst_mode)) -+ return DT_CHR; -+ if (S_ISBLK(obj->yst_mode)) -+ return DT_BLK; -+ if (S_ISSOCK(obj->yst_mode)) -+ return DT_SOCK; -+ default: -+ return DT_REG; -+ break; -+ } -+} -+ -+YCHAR *yaffs_get_symlink_alias(struct yaffs_obj *obj) -+{ -+ obj = yaffs_get_equivalent_obj(obj); -+ if (obj->variant_type == YAFFS_OBJECT_TYPE_SYMLINK) -+ return yaffs_clone_str(obj->variant.symlink_variant.alias); -+ else -+ return yaffs_clone_str(_Y("")); -+} -+ -+static int yaffs_do_xattrib_mod(struct yaffs_obj *obj, int set, -+ const YCHAR * name, const void *value, int size, -+ int flags) -+{ -+ struct yaffs_xattr_mod xmod; -+ -+ int result; -+ -+ xmod.set = set; -+ xmod.name = name; -+ xmod.data = value; -+ xmod.size = size; -+ xmod.flags = flags; -+ xmod.result = -ENOSPC; -+ -+ result = yaffs_update_oh(obj, NULL, 0, 0, 0, &xmod); -+ -+ if (result > 0) -+ return xmod.result; -+ else -+ return -ENOSPC; -+} -+ -+static int yaffs_apply_xattrib_mod(struct yaffs_obj *obj, char *buffer, -+ struct yaffs_xattr_mod *xmod) -+{ -+ int retval = 0; -+ int x_offs = sizeof(struct yaffs_obj_hdr); -+ struct yaffs_dev *dev = obj->my_dev; -+ int x_size = dev->data_bytes_per_chunk - sizeof(struct yaffs_obj_hdr); -+ -+ char *x_buffer = buffer + x_offs; -+ -+ if (xmod->set) -+ retval = -+ nval_set(x_buffer, x_size, xmod->name, xmod->data, -+ xmod->size, xmod->flags); -+ else -+ retval = nval_del(x_buffer, x_size, xmod->name); -+ -+ obj->has_xattr = nval_hasvalues(x_buffer, x_size); -+ obj->xattr_known = 1; -+ -+ xmod->result = retval; -+ -+ return retval; -+} -+ -+static int yaffs_do_xattrib_fetch(struct yaffs_obj *obj, const YCHAR * name, -+ void *value, int size) -+{ -+ char *buffer = NULL; -+ int result; -+ struct yaffs_ext_tags tags; -+ struct yaffs_dev *dev = obj->my_dev; -+ int x_offs = sizeof(struct yaffs_obj_hdr); -+ int x_size = dev->data_bytes_per_chunk - sizeof(struct yaffs_obj_hdr); -+ -+ char *x_buffer; -+ -+ int retval = 0; -+ -+ if (obj->hdr_chunk < 1) -+ return -ENODATA; -+ -+ /* If we know that the object has no xattribs then don't do all the -+ * reading and parsing. -+ */ -+ if (obj->xattr_known && !obj->has_xattr) { -+ if (name) -+ return -ENODATA; -+ else -+ return 0; -+ } -+ -+ buffer = (char *)yaffs_get_temp_buffer(dev, __LINE__); -+ if (!buffer) -+ return -ENOMEM; -+ -+ result = -+ yaffs_rd_chunk_tags_nand(dev, obj->hdr_chunk, (u8 *) buffer, &tags); -+ -+ if (result != YAFFS_OK) -+ retval = -ENOENT; -+ else { -+ x_buffer = buffer + x_offs; -+ -+ if (!obj->xattr_known) { -+ obj->has_xattr = nval_hasvalues(x_buffer, x_size); -+ obj->xattr_known = 1; -+ } -+ -+ if (name) -+ retval = nval_get(x_buffer, x_size, name, value, size); -+ else -+ retval = nval_list(x_buffer, x_size, value, size); -+ } -+ yaffs_release_temp_buffer(dev, (u8 *) buffer, __LINE__); -+ return retval; -+} -+ -+int yaffs_set_xattrib(struct yaffs_obj *obj, const YCHAR * name, -+ const void *value, int size, int flags) -+{ -+ return yaffs_do_xattrib_mod(obj, 1, name, value, size, flags); -+} -+ -+int yaffs_remove_xattrib(struct yaffs_obj *obj, const YCHAR * name) -+{ -+ return yaffs_do_xattrib_mod(obj, 0, name, NULL, 0, 0); -+} -+ -+int yaffs_get_xattrib(struct yaffs_obj *obj, const YCHAR * name, void *value, -+ int size) -+{ -+ return yaffs_do_xattrib_fetch(obj, name, value, size); -+} -+ -+int yaffs_list_xattrib(struct yaffs_obj *obj, char *buffer, int size) -+{ -+ return yaffs_do_xattrib_fetch(obj, NULL, buffer, size); -+} -+ -+/*---------------------------- Initialisation code -------------------------------------- */ -+ -+static int yaffs_check_dev_fns(const struct yaffs_dev *dev) -+{ -+ -+ /* Common functions, gotta have */ -+ if (!dev->param.erase_fn || !dev->param.initialise_flash_fn) -+ return 0; -+ -+#ifdef CONFIG_YAFFS_YAFFS2 -+ -+ /* Can use the "with tags" style interface for yaffs1 or yaffs2 */ -+ if (dev->param.write_chunk_tags_fn && -+ dev->param.read_chunk_tags_fn && -+ !dev->param.write_chunk_fn && -+ !dev->param.read_chunk_fn && -+ dev->param.bad_block_fn && dev->param.query_block_fn) -+ return 1; -+#endif -+ -+ /* Can use the "spare" style interface for yaffs1 */ -+ if (!dev->param.is_yaffs2 && -+ !dev->param.write_chunk_tags_fn && -+ !dev->param.read_chunk_tags_fn && -+ dev->param.write_chunk_fn && -+ dev->param.read_chunk_fn && -+ !dev->param.bad_block_fn && !dev->param.query_block_fn) -+ return 1; -+ -+ return 0; /* bad */ -+} -+ -+static int yaffs_create_initial_dir(struct yaffs_dev *dev) -+{ -+ /* Initialise the unlinked, deleted, root and lost and found directories */ -+ -+ dev->lost_n_found = dev->root_dir = NULL; -+ dev->unlinked_dir = dev->del_dir = NULL; -+ -+ dev->unlinked_dir = -+ yaffs_create_fake_dir(dev, YAFFS_OBJECTID_UNLINKED, S_IFDIR); -+ -+ dev->del_dir = -+ yaffs_create_fake_dir(dev, YAFFS_OBJECTID_DELETED, S_IFDIR); -+ -+ dev->root_dir = -+ yaffs_create_fake_dir(dev, YAFFS_OBJECTID_ROOT, -+ YAFFS_ROOT_MODE | S_IFDIR); -+ dev->lost_n_found = -+ yaffs_create_fake_dir(dev, YAFFS_OBJECTID_LOSTNFOUND, -+ YAFFS_LOSTNFOUND_MODE | S_IFDIR); -+ -+ if (dev->lost_n_found && dev->root_dir && dev->unlinked_dir -+ && dev->del_dir) { -+ yaffs_add_obj_to_dir(dev->root_dir, dev->lost_n_found); -+ return YAFFS_OK; -+ } -+ -+ return YAFFS_FAIL; -+} -+ -+int yaffs_guts_initialise(struct yaffs_dev *dev) -+{ -+ int init_failed = 0; -+ unsigned x; -+ int bits; -+ -+ T(YAFFS_TRACE_TRACING, -+ (TSTR("yaffs: yaffs_guts_initialise()" TENDSTR))); -+ -+ /* Check stuff that must be set */ -+ -+ if (!dev) { -+ T(YAFFS_TRACE_ALWAYS, (TSTR("yaffs: Need a device" TENDSTR))); -+ return YAFFS_FAIL; -+ } -+ -+ dev->internal_start_block = dev->param.start_block; -+ dev->internal_end_block = dev->param.end_block; -+ dev->block_offset = 0; -+ dev->chunk_offset = 0; -+ dev->n_free_chunks = 0; -+ -+ dev->gc_block = 0; -+ -+ if (dev->param.start_block == 0) { -+ dev->internal_start_block = dev->param.start_block + 1; -+ dev->internal_end_block = dev->param.end_block + 1; -+ dev->block_offset = 1; -+ dev->chunk_offset = dev->param.chunks_per_block; -+ } -+ -+ /* Check geometry parameters. */ -+ -+ if ((!dev->param.inband_tags && dev->param.is_yaffs2 && dev->param.total_bytes_per_chunk < 1024) || (!dev->param.is_yaffs2 && dev->param.total_bytes_per_chunk < 512) || (dev->param.inband_tags && !dev->param.is_yaffs2) || dev->param.chunks_per_block < 2 || dev->param.n_reserved_blocks < 2 || dev->internal_start_block <= 0 || dev->internal_end_block <= 0 || dev->internal_end_block <= (dev->internal_start_block + dev->param.n_reserved_blocks + 2)) { /* otherwise it is too small */ -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR -+ ("yaffs: NAND geometry problems: chunk size %d, type is yaffs%s, inband_tags %d " -+ TENDSTR), dev->param.total_bytes_per_chunk, -+ dev->param.is_yaffs2 ? "2" : "", dev->param.inband_tags)); -+ return YAFFS_FAIL; -+ } -+ -+ if (yaffs_init_nand(dev) != YAFFS_OK) { -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR("yaffs: InitialiseNAND failed" TENDSTR))); -+ return YAFFS_FAIL; -+ } -+ -+ /* Sort out space for inband tags, if required */ -+ if (dev->param.inband_tags) -+ dev->data_bytes_per_chunk = -+ dev->param.total_bytes_per_chunk - -+ sizeof(struct yaffs_packed_tags2_tags_only); -+ else -+ dev->data_bytes_per_chunk = dev->param.total_bytes_per_chunk; -+ -+ /* Got the right mix of functions? */ -+ if (!yaffs_check_dev_fns(dev)) { -+ /* Function missing */ -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR -+ ("yaffs: device function(s) missing or wrong\n" TENDSTR))); -+ -+ return YAFFS_FAIL; -+ } -+ -+ if (dev->is_mounted) { -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR("yaffs: device already mounted\n" TENDSTR))); -+ return YAFFS_FAIL; -+ } -+ -+ /* Finished with most checks. One or two more checks happen later on too. */ -+ -+ dev->is_mounted = 1; -+ -+ /* OK now calculate a few things for the device */ -+ -+ /* -+ * Calculate all the chunk size manipulation numbers: -+ */ -+ x = dev->data_bytes_per_chunk; -+ /* We always use dev->chunk_shift and dev->chunk_div */ -+ dev->chunk_shift = calc_shifts(x); -+ x >>= dev->chunk_shift; -+ dev->chunk_div = x; -+ /* We only use chunk mask if chunk_div is 1 */ -+ dev->chunk_mask = (1 << dev->chunk_shift) - 1; -+ -+ /* -+ * Calculate chunk_grp_bits. -+ * We need to find the next power of 2 > than internal_end_block -+ */ -+ -+ x = dev->param.chunks_per_block * (dev->internal_end_block + 1); -+ -+ bits = calc_shifts_ceiling(x); -+ -+ /* Set up tnode width if wide tnodes are enabled. */ -+ if (!dev->param.wide_tnodes_disabled) { -+ /* bits must be even so that we end up with 32-bit words */ -+ if (bits & 1) -+ bits++; -+ if (bits < 16) -+ dev->tnode_width = 16; -+ else -+ dev->tnode_width = bits; -+ } else { -+ dev->tnode_width = 16; -+ } -+ -+ dev->tnode_mask = (1 << dev->tnode_width) - 1; -+ -+ /* Level0 Tnodes are 16 bits or wider (if wide tnodes are enabled), -+ * so if the bitwidth of the -+ * chunk range we're using is greater than 16 we need -+ * to figure out chunk shift and chunk_grp_size -+ */ -+ -+ if (bits <= dev->tnode_width) -+ dev->chunk_grp_bits = 0; -+ else -+ dev->chunk_grp_bits = bits - dev->tnode_width; -+ -+ dev->tnode_size = (dev->tnode_width * YAFFS_NTNODES_LEVEL0) / 8; -+ if (dev->tnode_size < sizeof(struct yaffs_tnode)) -+ dev->tnode_size = sizeof(struct yaffs_tnode); -+ -+ dev->chunk_grp_size = 1 << dev->chunk_grp_bits; -+ -+ if (dev->param.chunks_per_block < dev->chunk_grp_size) { -+ /* We have a problem because the soft delete won't work if -+ * the chunk group size > chunks per block. -+ * This can be remedied by using larger "virtual blocks". -+ */ -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR("yaffs: chunk group too large\n" TENDSTR))); -+ -+ return YAFFS_FAIL; -+ } -+ -+ /* OK, we've finished verifying the device, lets continue with initialisation */ -+ -+ /* More device initialisation */ -+ dev->all_gcs = 0; -+ dev->passive_gc_count = 0; -+ dev->oldest_dirty_gc_count = 0; -+ dev->bg_gcs = 0; -+ dev->gc_block_finder = 0; -+ dev->buffered_block = -1; -+ dev->doing_buffered_block_rewrite = 0; -+ dev->n_deleted_files = 0; -+ dev->n_bg_deletions = 0; -+ dev->n_unlinked_files = 0; -+ dev->n_ecc_fixed = 0; -+ dev->n_ecc_unfixed = 0; -+ dev->n_tags_ecc_fixed = 0; -+ dev->n_tags_ecc_unfixed = 0; -+ dev->n_erase_failures = 0; -+ dev->n_erased_blocks = 0; -+ dev->gc_disable = 0; -+ dev->has_pending_prioritised_gc = 1; /* Assume the worst for now, will get fixed on first GC */ -+ INIT_LIST_HEAD(&dev->dirty_dirs); -+ dev->oldest_dirty_seq = 0; -+ dev->oldest_dirty_block = 0; -+ -+ /* Initialise temporary buffers and caches. */ -+ if (!yaffs_init_tmp_buffers(dev)) -+ init_failed = 1; -+ -+ dev->cache = NULL; -+ dev->gc_cleanup_list = NULL; -+ -+ if (!init_failed && dev->param.n_caches > 0) { -+ int i; -+ void *buf; -+ int cache_bytes = -+ dev->param.n_caches * sizeof(struct yaffs_cache); -+ -+ if (dev->param.n_caches > YAFFS_MAX_SHORT_OP_CACHES) -+ dev->param.n_caches = YAFFS_MAX_SHORT_OP_CACHES; -+ -+ dev->cache = YMALLOC(cache_bytes); -+ -+ buf = (u8 *) dev->cache; -+ -+ if (dev->cache) -+ memset(dev->cache, 0, cache_bytes); -+ -+ for (i = 0; i < dev->param.n_caches && buf; i++) { -+ dev->cache[i].object = NULL; -+ dev->cache[i].last_use = 0; -+ dev->cache[i].dirty = 0; -+ dev->cache[i].data = buf = -+ YMALLOC_DMA(dev->param.total_bytes_per_chunk); -+ } -+ if (!buf) -+ init_failed = 1; -+ -+ dev->cache_last_use = 0; -+ } -+ -+ dev->cache_hits = 0; -+ -+ if (!init_failed) { -+ dev->gc_cleanup_list = -+ YMALLOC(dev->param.chunks_per_block * sizeof(u32)); -+ if (!dev->gc_cleanup_list) -+ init_failed = 1; -+ } -+ -+ if (dev->param.is_yaffs2) -+ dev->param.use_header_file_size = 1; -+ -+ if (!init_failed && !yaffs_init_blocks(dev)) -+ init_failed = 1; -+ -+ yaffs_init_tnodes_and_objs(dev); -+ -+ if (!init_failed && !yaffs_create_initial_dir(dev)) -+ init_failed = 1; -+ -+ if (!init_failed) { -+ /* Now scan the flash. */ -+ if (dev->param.is_yaffs2) { -+ if (yaffs2_checkpt_restore(dev)) { -+ yaffs_check_obj_details_loaded(dev->root_dir); -+ T(YAFFS_TRACE_CHECKPOINT | YAFFS_TRACE_MOUNT, -+ (TSTR -+ ("yaffs: restored from checkpoint" -+ TENDSTR))); -+ } else { -+ -+ /* Clean up the mess caused by an aborted checkpoint load -+ * and scan backwards. -+ */ -+ yaffs_deinit_blocks(dev); -+ -+ yaffs_deinit_tnodes_and_objs(dev); -+ -+ dev->n_erased_blocks = 0; -+ dev->n_free_chunks = 0; -+ dev->alloc_block = -1; -+ dev->alloc_page = -1; -+ dev->n_deleted_files = 0; -+ dev->n_unlinked_files = 0; -+ dev->n_bg_deletions = 0; -+ -+ if (!init_failed && !yaffs_init_blocks(dev)) -+ init_failed = 1; -+ -+ yaffs_init_tnodes_and_objs(dev); -+ -+ if (!init_failed -+ && !yaffs_create_initial_dir(dev)) -+ init_failed = 1; -+ -+ if (!init_failed && !yaffs2_scan_backwards(dev)) -+ init_failed = 1; -+ } -+ } else if (!yaffs1_scan(dev)) { -+ init_failed = 1; -+ } -+ -+ yaffs_strip_deleted_objs(dev); -+ yaffs_fix_hanging_objs(dev); -+ if (dev->param.empty_lost_n_found) -+ yaffs_empty_l_n_f(dev); -+ } -+ -+ if (init_failed) { -+ /* Clean up the mess */ -+ T(YAFFS_TRACE_TRACING, -+ (TSTR("yaffs: yaffs_guts_initialise() aborted.\n" TENDSTR))); -+ -+ yaffs_deinitialise(dev); -+ return YAFFS_FAIL; -+ } -+ -+ /* Zero out stats */ -+ dev->n_page_reads = 0; -+ dev->n_page_writes = 0; -+ dev->n_erasures = 0; -+ dev->n_gc_copies = 0; -+ dev->n_retired_writes = 0; -+ -+ dev->n_retired_blocks = 0; -+ -+ yaffs_verify_free_chunks(dev); -+ yaffs_verify_blocks(dev); -+ -+ /* Clean up any aborted checkpoint data */ -+ if (!dev->is_checkpointed && dev->blocks_in_checkpt > 0) -+ yaffs2_checkpt_invalidate(dev); -+ -+ T(YAFFS_TRACE_TRACING, -+ (TSTR("yaffs: yaffs_guts_initialise() done.\n" TENDSTR))); -+ return YAFFS_OK; -+ -+} -+ -+void yaffs_deinitialise(struct yaffs_dev *dev) -+{ -+ if (dev->is_mounted) { -+ int i; -+ -+ yaffs_deinit_blocks(dev); -+ yaffs_deinit_tnodes_and_objs(dev); -+ if (dev->param.n_caches > 0 && dev->cache) { -+ -+ for (i = 0; i < dev->param.n_caches; i++) { -+ if (dev->cache[i].data) -+ YFREE(dev->cache[i].data); -+ dev->cache[i].data = NULL; -+ } -+ -+ YFREE(dev->cache); -+ dev->cache = NULL; -+ } -+ -+ YFREE(dev->gc_cleanup_list); -+ -+ for (i = 0; i < YAFFS_N_TEMP_BUFFERS; i++) -+ YFREE(dev->temp_buffer[i].buffer); -+ -+ dev->is_mounted = 0; -+ -+ if (dev->param.deinitialise_flash_fn) -+ dev->param.deinitialise_flash_fn(dev); -+ } -+} -+ -+int yaffs_count_free_chunks(struct yaffs_dev *dev) -+{ -+ int n_free = 0; -+ int b; -+ -+ struct yaffs_block_info *blk; -+ -+ blk = dev->block_info; -+ for (b = dev->internal_start_block; b <= dev->internal_end_block; b++) { -+ switch (blk->block_state) { -+ case YAFFS_BLOCK_STATE_EMPTY: -+ case YAFFS_BLOCK_STATE_ALLOCATING: -+ case YAFFS_BLOCK_STATE_COLLECTING: -+ case YAFFS_BLOCK_STATE_FULL: -+ n_free += -+ (dev->param.chunks_per_block - blk->pages_in_use + -+ blk->soft_del_pages); -+ break; -+ default: -+ break; -+ } -+ blk++; -+ } -+ -+ return n_free; -+} -+ -+int yaffs_get_n_free_chunks(struct yaffs_dev *dev) -+{ -+ /* This is what we report to the outside world */ -+ -+ int n_free; -+ int n_dirty_caches; -+ int blocks_for_checkpt; -+ int i; -+ -+ n_free = dev->n_free_chunks; -+ n_free += dev->n_deleted_files; -+ -+ /* Now count the number of dirty chunks in the cache and subtract those */ -+ -+ for (n_dirty_caches = 0, i = 0; i < dev->param.n_caches; i++) { -+ if (dev->cache[i].dirty) -+ n_dirty_caches++; -+ } -+ -+ n_free -= n_dirty_caches; -+ -+ n_free -= -+ ((dev->param.n_reserved_blocks + 1) * dev->param.chunks_per_block); -+ -+ /* Now we figure out how much to reserve for the checkpoint and report that... */ -+ blocks_for_checkpt = yaffs_calc_checkpt_blocks_required(dev); -+ -+ n_free -= (blocks_for_checkpt * dev->param.chunks_per_block); -+ -+ if (n_free < 0) -+ n_free = 0; -+ -+ return n_free; -+ -+} -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_guts.h linux-2.6.36/fs/yaffs2/yaffs_guts.h ---- linux-2.6.36.orig/fs/yaffs2/yaffs_guts.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_guts.h 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,914 @@ -+/* -+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU Lesser General Public License version 2.1 as -+ * published by the Free Software Foundation. -+ * -+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. -+ */ -+ -+#ifndef __YAFFS_GUTS_H__ -+#define __YAFFS_GUTS_H__ -+ -+#include "yportenv.h" -+ -+#define YAFFS_OK 1 -+#define YAFFS_FAIL 0 -+ -+/* Give us a Y=0x59, -+ * Give us an A=0x41, -+ * Give us an FF=0xFF -+ * Give us an S=0x53 -+ * And what have we got... -+ */ -+#define YAFFS_MAGIC 0x5941FF53 -+ -+#define YAFFS_NTNODES_LEVEL0 16 -+#define YAFFS_TNODES_LEVEL0_BITS 4 -+#define YAFFS_TNODES_LEVEL0_MASK 0xf -+ -+#define YAFFS_NTNODES_INTERNAL (YAFFS_NTNODES_LEVEL0 / 2) -+#define YAFFS_TNODES_INTERNAL_BITS (YAFFS_TNODES_LEVEL0_BITS - 1) -+#define YAFFS_TNODES_INTERNAL_MASK 0x7 -+#define YAFFS_TNODES_MAX_LEVEL 6 -+ -+#ifndef CONFIG_YAFFS_NO_YAFFS1 -+#define YAFFS_BYTES_PER_SPARE 16 -+#define YAFFS_BYTES_PER_CHUNK 512 -+#define YAFFS_CHUNK_SIZE_SHIFT 9 -+#define YAFFS_CHUNKS_PER_BLOCK 32 -+#define YAFFS_BYTES_PER_BLOCK (YAFFS_CHUNKS_PER_BLOCK*YAFFS_BYTES_PER_CHUNK) -+#endif -+ -+#define YAFFS_MIN_YAFFS2_CHUNK_SIZE 1024 -+#define YAFFS_MIN_YAFFS2_SPARE_SIZE 32 -+ -+#define YAFFS_MAX_CHUNK_ID 0x000FFFFF -+ -+#define YAFFS_ALLOCATION_NOBJECTS 100 -+#define YAFFS_ALLOCATION_NTNODES 100 -+#define YAFFS_ALLOCATION_NLINKS 100 -+ -+#define YAFFS_NOBJECT_BUCKETS 256 -+ -+#define YAFFS_OBJECT_SPACE 0x40000 -+#define YAFFS_MAX_OBJECT_ID (YAFFS_OBJECT_SPACE -1) -+ -+#define YAFFS_CHECKPOINT_VERSION 4 -+ -+#ifdef CONFIG_YAFFS_UNICODE -+#define YAFFS_MAX_NAME_LENGTH 127 -+#define YAFFS_MAX_ALIAS_LENGTH 79 -+#else -+#define YAFFS_MAX_NAME_LENGTH 255 -+#define YAFFS_MAX_ALIAS_LENGTH 159 -+#endif -+ -+#define YAFFS_SHORT_NAME_LENGTH 15 -+ -+/* Some special object ids for pseudo objects */ -+#define YAFFS_OBJECTID_ROOT 1 -+#define YAFFS_OBJECTID_LOSTNFOUND 2 -+#define YAFFS_OBJECTID_UNLINKED 3 -+#define YAFFS_OBJECTID_DELETED 4 -+ -+/* Pseudo object ids for checkpointing */ -+#define YAFFS_OBJECTID_SB_HEADER 0x10 -+#define YAFFS_OBJECTID_CHECKPOINT_DATA 0x20 -+#define YAFFS_SEQUENCE_CHECKPOINT_DATA 0x21 -+ -+#define YAFFS_MAX_SHORT_OP_CACHES 20 -+ -+#define YAFFS_N_TEMP_BUFFERS 6 -+ -+/* We limit the number attempts at sucessfully saving a chunk of data. -+ * Small-page devices have 32 pages per block; large-page devices have 64. -+ * Default to something in the order of 5 to 10 blocks worth of chunks. -+ */ -+#define YAFFS_WR_ATTEMPTS (5*64) -+ -+/* Sequence numbers are used in YAFFS2 to determine block allocation order. -+ * The range is limited slightly to help distinguish bad numbers from good. -+ * This also allows us to perhaps in the future use special numbers for -+ * special purposes. -+ * EFFFFF00 allows the allocation of 8 blocks per second (~1Mbytes) for 15 years, -+ * and is a larger number than the lifetime of a 2GB device. -+ */ -+#define YAFFS_LOWEST_SEQUENCE_NUMBER 0x00001000 -+#define YAFFS_HIGHEST_SEQUENCE_NUMBER 0xEFFFFF00 -+ -+/* Special sequence number for bad block that failed to be marked bad */ -+#define YAFFS_SEQUENCE_BAD_BLOCK 0xFFFF0000 -+ -+/* ChunkCache is used for short read/write operations.*/ -+struct yaffs_cache { -+ struct yaffs_obj *object; -+ int chunk_id; -+ int last_use; -+ int dirty; -+ int n_bytes; /* Only valid if the cache is dirty */ -+ int locked; /* Can't push out or flush while locked. */ -+ u8 *data; -+}; -+ -+/* Tags structures in RAM -+ * NB This uses bitfield. Bitfields should not straddle a u32 boundary otherwise -+ * the structure size will get blown out. -+ */ -+ -+#ifndef CONFIG_YAFFS_NO_YAFFS1 -+struct yaffs_tags { -+ unsigned chunk_id:20; -+ unsigned serial_number:2; -+ unsigned n_bytes_lsb:10; -+ unsigned obj_id:18; -+ unsigned ecc:12; -+ unsigned n_bytes_msb:2; -+}; -+ -+union yaffs_tags_union { -+ struct yaffs_tags as_tags; -+ u8 as_bytes[8]; -+}; -+ -+#endif -+ -+/* Stuff used for extended tags in YAFFS2 */ -+ -+enum yaffs_ecc_result { -+ YAFFS_ECC_RESULT_UNKNOWN, -+ YAFFS_ECC_RESULT_NO_ERROR, -+ YAFFS_ECC_RESULT_FIXED, -+ YAFFS_ECC_RESULT_UNFIXED -+}; -+ -+enum yaffs_obj_type { -+ YAFFS_OBJECT_TYPE_UNKNOWN, -+ YAFFS_OBJECT_TYPE_FILE, -+ YAFFS_OBJECT_TYPE_SYMLINK, -+ YAFFS_OBJECT_TYPE_DIRECTORY, -+ YAFFS_OBJECT_TYPE_HARDLINK, -+ YAFFS_OBJECT_TYPE_SPECIAL -+}; -+ -+#define YAFFS_OBJECT_TYPE_MAX YAFFS_OBJECT_TYPE_SPECIAL -+ -+struct yaffs_ext_tags { -+ -+ unsigned validity0; -+ unsigned chunk_used; /* Status of the chunk: used or unused */ -+ unsigned obj_id; /* If 0 then this is not part of an object (unused) */ -+ unsigned chunk_id; /* If 0 then this is a header, else a data chunk */ -+ unsigned n_bytes; /* Only valid for data chunks */ -+ -+ /* The following stuff only has meaning when we read */ -+ enum yaffs_ecc_result ecc_result; -+ unsigned block_bad; -+ -+ /* YAFFS 1 stuff */ -+ unsigned is_deleted; /* The chunk is marked deleted */ -+ unsigned serial_number; /* Yaffs1 2-bit serial number */ -+ -+ /* YAFFS2 stuff */ -+ unsigned seq_number; /* The sequence number of this block */ -+ -+ /* Extra info if this is an object header (YAFFS2 only) */ -+ -+ unsigned extra_available; /* There is extra info available if this is not zero */ -+ unsigned extra_parent_id; /* The parent object */ -+ unsigned extra_is_shrink; /* Is it a shrink header? */ -+ unsigned extra_shadows; /* Does this shadow another object? */ -+ -+ enum yaffs_obj_type extra_obj_type; /* What object type? */ -+ -+ unsigned extra_length; /* Length if it is a file */ -+ unsigned extra_equiv_id; /* Equivalent object Id if it is a hard link */ -+ -+ unsigned validity1; -+ -+}; -+ -+/* Spare structure for YAFFS1 */ -+struct yaffs_spare { -+ u8 tb0; -+ u8 tb1; -+ u8 tb2; -+ u8 tb3; -+ u8 page_status; /* set to 0 to delete the chunk */ -+ u8 block_status; -+ u8 tb4; -+ u8 tb5; -+ u8 ecc1[3]; -+ u8 tb6; -+ u8 tb7; -+ u8 ecc2[3]; -+}; -+ -+/*Special structure for passing through to mtd */ -+struct yaffs_nand_spare { -+ struct yaffs_spare spare; -+ int eccres1; -+ int eccres2; -+}; -+ -+/* Block data in RAM */ -+ -+enum yaffs_block_state { -+ YAFFS_BLOCK_STATE_UNKNOWN = 0, -+ -+ YAFFS_BLOCK_STATE_SCANNING, -+ /* Being scanned */ -+ -+ YAFFS_BLOCK_STATE_NEEDS_SCANNING, -+ /* The block might have something on it (ie it is allocating or full, perhaps empty) -+ * but it needs to be scanned to determine its true state. -+ * This state is only valid during scanning. -+ * NB We tolerate empty because the pre-scanner might be incapable of deciding -+ * However, if this state is returned on a YAFFS2 device, then we expect a sequence number -+ */ -+ -+ YAFFS_BLOCK_STATE_EMPTY, -+ /* This block is empty */ -+ -+ YAFFS_BLOCK_STATE_ALLOCATING, -+ /* This block is partially allocated. -+ * At least one page holds valid data. -+ * This is the one currently being used for page -+ * allocation. Should never be more than one of these. -+ * If a block is only partially allocated at mount it is treated as full. -+ */ -+ -+ YAFFS_BLOCK_STATE_FULL, -+ /* All the pages in this block have been allocated. -+ * If a block was only partially allocated when mounted we treat -+ * it as fully allocated. -+ */ -+ -+ YAFFS_BLOCK_STATE_DIRTY, -+ /* The block was full and now all chunks have been deleted. -+ * Erase me, reuse me. -+ */ -+ -+ YAFFS_BLOCK_STATE_CHECKPOINT, -+ /* This block is assigned to holding checkpoint data. */ -+ -+ YAFFS_BLOCK_STATE_COLLECTING, -+ /* This block is being garbage collected */ -+ -+ YAFFS_BLOCK_STATE_DEAD -+ /* This block has failed and is not in use */ -+}; -+ -+#define YAFFS_NUMBER_OF_BLOCK_STATES (YAFFS_BLOCK_STATE_DEAD + 1) -+ -+struct yaffs_block_info { -+ -+ int soft_del_pages:10; /* number of soft deleted pages */ -+ int pages_in_use:10; /* number of pages in use */ -+ unsigned block_state:4; /* One of the above block states. NB use unsigned because enum is sometimes an int */ -+ u32 needs_retiring:1; /* Data has failed on this block, need to get valid data off */ -+ /* and retire the block. */ -+ u32 skip_erased_check:1; /* If this is set we can skip the erased check on this block */ -+ u32 gc_prioritise:1; /* An ECC check or blank check has failed on this block. -+ It should be prioritised for GC */ -+ u32 chunk_error_strikes:3; /* How many times we've had ecc etc failures on this block and tried to reuse it */ -+ -+#ifdef CONFIG_YAFFS_YAFFS2 -+ u32 has_shrink_hdr:1; /* This block has at least one shrink object header */ -+ u32 seq_number; /* block sequence number for yaffs2 */ -+#endif -+ -+}; -+ -+/* -------------------------- Object structure -------------------------------*/ -+/* This is the object structure as stored on NAND */ -+ -+struct yaffs_obj_hdr { -+ enum yaffs_obj_type type; -+ -+ /* Apply to everything */ -+ int parent_obj_id; -+ u16 sum_no_longer_used; /* checksum of name. No longer used */ -+ YCHAR name[YAFFS_MAX_NAME_LENGTH + 1]; -+ -+ /* The following apply to directories, files, symlinks - not hard links */ -+ u32 yst_mode; /* protection */ -+ -+ u32 yst_uid; -+ u32 yst_gid; -+ u32 yst_atime; -+ u32 yst_mtime; -+ u32 yst_ctime; -+ -+ /* File size applies to files only */ -+ int file_size; -+ -+ /* Equivalent object id applies to hard links only. */ -+ int equiv_id; -+ -+ /* Alias is for symlinks only. */ -+ YCHAR alias[YAFFS_MAX_ALIAS_LENGTH + 1]; -+ -+ u32 yst_rdev; /* device stuff for block and char devices (major/min) */ -+ -+ u32 win_ctime[2]; -+ u32 win_atime[2]; -+ u32 win_mtime[2]; -+ -+ u32 inband_shadowed_obj_id; -+ u32 inband_is_shrink; -+ -+ u32 reserved[2]; -+ int shadows_obj; /* This object header shadows the specified object if > 0 */ -+ -+ /* is_shrink applies to object headers written when we shrink the file (ie resize) */ -+ u32 is_shrink; -+ -+}; -+ -+/*--------------------------- Tnode -------------------------- */ -+ -+struct yaffs_tnode { -+ struct yaffs_tnode *internal[YAFFS_NTNODES_INTERNAL]; -+}; -+ -+/*------------------------ Object -----------------------------*/ -+/* An object can be one of: -+ * - a directory (no data, has children links -+ * - a regular file (data.... not prunes :->). -+ * - a symlink [symbolic link] (the alias). -+ * - a hard link -+ */ -+ -+struct yaffs_file_var { -+ u32 file_size; -+ u32 scanned_size; -+ u32 shrink_size; -+ int top_level; -+ struct yaffs_tnode *top; -+}; -+ -+struct yaffs_dir_var { -+ struct list_head children; /* list of child links */ -+ struct list_head dirty; /* Entry for list of dirty directories */ -+}; -+ -+struct yaffs_symlink_var { -+ YCHAR *alias; -+}; -+ -+struct yaffs_hardlink_var { -+ struct yaffs_obj *equiv_obj; -+ u32 equiv_id; -+}; -+ -+union yaffs_obj_var { -+ struct yaffs_file_var file_variant; -+ struct yaffs_dir_var dir_variant; -+ struct yaffs_symlink_var symlink_variant; -+ struct yaffs_hardlink_var hardlink_variant; -+}; -+ -+struct yaffs_obj { -+ u8 deleted:1; /* This should only apply to unlinked files. */ -+ u8 soft_del:1; /* it has also been soft deleted */ -+ u8 unlinked:1; /* An unlinked file. The file should be in the unlinked directory. */ -+ u8 fake:1; /* A fake object has no presence on NAND. */ -+ u8 rename_allowed:1; /* Some objects are not allowed to be renamed. */ -+ u8 unlink_allowed:1; -+ u8 dirty:1; /* the object needs to be written to flash */ -+ u8 valid:1; /* When the file system is being loaded up, this -+ * object might be created before the data -+ * is available (ie. file data records appear before the header). -+ */ -+ u8 lazy_loaded:1; /* This object has been lazy loaded and is missing some detail */ -+ -+ u8 defered_free:1; /* For Linux kernel. Object is removed from NAND, but is -+ * still in the inode cache. Free of object is defered. -+ * until the inode is released. -+ */ -+ u8 being_created:1; /* This object is still being created so skip some checks. */ -+ u8 is_shadowed:1; /* This object is shadowed on the way to being renamed. */ -+ -+ u8 xattr_known:1; /* We know if this has object has xattribs or not. */ -+ u8 has_xattr:1; /* This object has xattribs. Valid if xattr_known. */ -+ -+ u8 serial; /* serial number of chunk in NAND. Cached here */ -+ u16 sum; /* sum of the name to speed searching */ -+ -+ struct yaffs_dev *my_dev; /* The device I'm on */ -+ -+ struct list_head hash_link; /* list of objects in this hash bucket */ -+ -+ struct list_head hard_links; /* all the equivalent hard linked objects */ -+ -+ /* directory structure stuff */ -+ /* also used for linking up the free list */ -+ struct yaffs_obj *parent; -+ struct list_head siblings; -+ -+ /* Where's my object header in NAND? */ -+ int hdr_chunk; -+ -+ int n_data_chunks; /* Number of data chunks attached to the file. */ -+ -+ u32 obj_id; /* the object id value */ -+ -+ u32 yst_mode; -+ -+#ifndef CONFIG_YAFFS_NO_SHORT_NAMES -+ YCHAR short_name[YAFFS_SHORT_NAME_LENGTH + 1]; -+#endif -+ -+#ifdef CONFIG_YAFFS_WINCE -+ u32 win_ctime[2]; -+ u32 win_mtime[2]; -+ u32 win_atime[2]; -+#else -+ u32 yst_uid; -+ u32 yst_gid; -+ u32 yst_atime; -+ u32 yst_mtime; -+ u32 yst_ctime; -+#endif -+ -+ u32 yst_rdev; -+ -+ void *my_inode; -+ -+ enum yaffs_obj_type variant_type; -+ -+ union yaffs_obj_var variant; -+ -+}; -+ -+struct yaffs_obj_bucket { -+ struct list_head list; -+ int count; -+}; -+ -+/* yaffs_checkpt_obj holds the definition of an object as dumped -+ * by checkpointing. -+ */ -+ -+struct yaffs_checkpt_obj { -+ int struct_type; -+ u32 obj_id; -+ u32 parent_id; -+ int hdr_chunk; -+ enum yaffs_obj_type variant_type:3; -+ u8 deleted:1; -+ u8 soft_del:1; -+ u8 unlinked:1; -+ u8 fake:1; -+ u8 rename_allowed:1; -+ u8 unlink_allowed:1; -+ u8 serial; -+ int n_data_chunks; -+ u32 size_or_equiv_obj; -+}; -+ -+/*--------------------- Temporary buffers ---------------- -+ * -+ * These are chunk-sized working buffers. Each device has a few -+ */ -+ -+struct yaffs_buffer { -+ u8 *buffer; -+ int line; /* track from whence this buffer was allocated */ -+ int max_line; -+}; -+ -+/*----------------- Device ---------------------------------*/ -+ -+struct yaffs_param { -+ const YCHAR *name; -+ -+ /* -+ * Entry parameters set up way early. Yaffs sets up the rest. -+ * The structure should be zeroed out before use so that unused -+ * and defualt values are zero. -+ */ -+ -+ int inband_tags; /* Use unband tags */ -+ u32 total_bytes_per_chunk; /* Should be >= 512, does not need to be a power of 2 */ -+ int chunks_per_block; /* does not need to be a power of 2 */ -+ int spare_bytes_per_chunk; /* spare area size */ -+ int start_block; /* Start block we're allowed to use */ -+ int end_block; /* End block we're allowed to use */ -+ int n_reserved_blocks; /* We want this tuneable so that we can reduce */ -+ /* reserved blocks on NOR and RAM. */ -+ -+ int n_caches; /* If <= 0, then short op caching is disabled, else -+ * the number of short op caches (don't use too many). -+ * 10 to 20 is a good bet. -+ */ -+ int use_nand_ecc; /* Flag to decide whether or not to use NANDECC on data (yaffs1) */ -+ int no_tags_ecc; /* Flag to decide whether or not to do ECC on packed tags (yaffs2) */ -+ -+ int is_yaffs2; /* Use yaffs2 mode on this device */ -+ -+ int empty_lost_n_found; /* Auto-empty lost+found directory on mount */ -+ -+ int refresh_period; /* How often we should check to do a block refresh */ -+ -+ /* Checkpoint control. Can be set before or after initialisation */ -+ u8 skip_checkpt_rd; -+ u8 skip_checkpt_wr; -+ -+ int enable_xattr; /* Enable xattribs */ -+ -+ /* NAND access functions (Must be set before calling YAFFS) */ -+ -+ int (*write_chunk_fn) (struct yaffs_dev * dev, -+ int nand_chunk, const u8 * data, -+ const struct yaffs_spare * spare); -+ int (*read_chunk_fn) (struct yaffs_dev * dev, -+ int nand_chunk, u8 * data, -+ struct yaffs_spare * spare); -+ int (*erase_fn) (struct yaffs_dev * dev, int flash_block); -+ int (*initialise_flash_fn) (struct yaffs_dev * dev); -+ int (*deinitialise_flash_fn) (struct yaffs_dev * dev); -+ -+#ifdef CONFIG_YAFFS_YAFFS2 -+ int (*write_chunk_tags_fn) (struct yaffs_dev * dev, -+ int nand_chunk, const u8 * data, -+ const struct yaffs_ext_tags * tags); -+ int (*read_chunk_tags_fn) (struct yaffs_dev * dev, -+ int nand_chunk, u8 * data, -+ struct yaffs_ext_tags * tags); -+ int (*bad_block_fn) (struct yaffs_dev * dev, int block_no); -+ int (*query_block_fn) (struct yaffs_dev * dev, int block_no, -+ enum yaffs_block_state * state, -+ u32 * seq_number); -+#endif -+ -+ /* The remove_obj_fn function must be supplied by OS flavours that -+ * need it. -+ * yaffs direct uses it to implement the faster readdir. -+ * Linux uses it to protect the directory during unlocking. -+ */ -+ void (*remove_obj_fn) (struct yaffs_obj * obj); -+ -+ /* Callback to mark the superblock dirty */ -+ void (*sb_dirty_fn) (struct yaffs_dev * dev); -+ -+ /* Callback to control garbage collection. */ -+ unsigned (*gc_control) (struct yaffs_dev * dev); -+ -+ /* Debug control flags. Don't use unless you know what you're doing */ -+ int use_header_file_size; /* Flag to determine if we should use file sizes from the header */ -+ int disable_lazy_load; /* Disable lazy loading on this device */ -+ int wide_tnodes_disabled; /* Set to disable wide tnodes */ -+ int disable_soft_del; /* yaffs 1 only: Set to disable the use of softdeletion. */ -+ -+ int defered_dir_update; /* Set to defer directory updates */ -+ -+#ifdef CONFIG_YAFFS_AUTO_UNICODE -+ int auto_unicode; -+#endif -+ int always_check_erased; /* Force chunk erased check always on */ -+}; -+ -+struct yaffs_dev { -+ struct yaffs_param param; -+ -+ /* Context storage. Holds extra OS specific data for this device */ -+ -+ void *os_context; -+ void *driver_context; -+ -+ struct list_head dev_list; -+ -+ /* Runtime parameters. Set up by YAFFS. */ -+ int data_bytes_per_chunk; -+ -+ /* Non-wide tnode stuff */ -+ u16 chunk_grp_bits; /* Number of bits that need to be resolved if -+ * the tnodes are not wide enough. -+ */ -+ u16 chunk_grp_size; /* == 2^^chunk_grp_bits */ -+ -+ /* Stuff to support wide tnodes */ -+ u32 tnode_width; -+ u32 tnode_mask; -+ u32 tnode_size; -+ -+ /* Stuff for figuring out file offset to chunk conversions */ -+ u32 chunk_shift; /* Shift value */ -+ u32 chunk_div; /* Divisor after shifting: 1 for power-of-2 sizes */ -+ u32 chunk_mask; /* Mask to use for power-of-2 case */ -+ -+ int is_mounted; -+ int read_only; -+ int is_checkpointed; -+ -+ /* Stuff to support block offsetting to support start block zero */ -+ int internal_start_block; -+ int internal_end_block; -+ int block_offset; -+ int chunk_offset; -+ -+ /* Runtime checkpointing stuff */ -+ int checkpt_page_seq; /* running sequence number of checkpoint pages */ -+ int checkpt_byte_count; -+ int checkpt_byte_offs; -+ u8 *checkpt_buffer; -+ int checkpt_open_write; -+ int blocks_in_checkpt; -+ int checkpt_cur_chunk; -+ int checkpt_cur_block; -+ int checkpt_next_block; -+ int *checkpt_block_list; -+ int checkpt_max_blocks; -+ u32 checkpt_sum; -+ u32 checkpt_xor; -+ -+ int checkpoint_blocks_required; /* Number of blocks needed to store current checkpoint set */ -+ -+ /* Block Info */ -+ struct yaffs_block_info *block_info; -+ u8 *chunk_bits; /* bitmap of chunks in use */ -+ unsigned block_info_alt:1; /* was allocated using alternative strategy */ -+ unsigned chunk_bits_alt:1; /* was allocated using alternative strategy */ -+ int chunk_bit_stride; /* Number of bytes of chunk_bits per block. -+ * Must be consistent with chunks_per_block. -+ */ -+ -+ int n_erased_blocks; -+ int alloc_block; /* Current block being allocated off */ -+ u32 alloc_page; -+ int alloc_block_finder; /* Used to search for next allocation block */ -+ -+ /* Object and Tnode memory management */ -+ void *allocator; -+ int n_obj; -+ int n_tnodes; -+ -+ int n_hardlinks; -+ -+ struct yaffs_obj_bucket obj_bucket[YAFFS_NOBJECT_BUCKETS]; -+ u32 bucket_finder; -+ -+ int n_free_chunks; -+ -+ /* Garbage collection control */ -+ u32 *gc_cleanup_list; /* objects to delete at the end of a GC. */ -+ u32 n_clean_ups; -+ -+ unsigned has_pending_prioritised_gc; /* We think this device might have pending prioritised gcs */ -+ unsigned gc_disable; -+ unsigned gc_block_finder; -+ unsigned gc_dirtiest; -+ unsigned gc_pages_in_use; -+ unsigned gc_not_done; -+ unsigned gc_block; -+ unsigned gc_chunk; -+ unsigned gc_skip; -+ -+ /* Special directories */ -+ struct yaffs_obj *root_dir; -+ struct yaffs_obj *lost_n_found; -+ -+ /* Buffer areas for storing data to recover from write failures TODO -+ * u8 buffered_data[YAFFS_CHUNKS_PER_BLOCK][YAFFS_BYTES_PER_CHUNK]; -+ * struct yaffs_spare buffered_spare[YAFFS_CHUNKS_PER_BLOCK]; -+ */ -+ -+ int buffered_block; /* Which block is buffered here? */ -+ int doing_buffered_block_rewrite; -+ -+ struct yaffs_cache *cache; -+ int cache_last_use; -+ -+ /* Stuff for background deletion and unlinked files. */ -+ struct yaffs_obj *unlinked_dir; /* Directory where unlinked and deleted files live. */ -+ struct yaffs_obj *del_dir; /* Directory where deleted objects are sent to disappear. */ -+ struct yaffs_obj *unlinked_deletion; /* Current file being background deleted. */ -+ int n_deleted_files; /* Count of files awaiting deletion; */ -+ int n_unlinked_files; /* Count of unlinked files. */ -+ int n_bg_deletions; /* Count of background deletions. */ -+ -+ /* Temporary buffer management */ -+ struct yaffs_buffer temp_buffer[YAFFS_N_TEMP_BUFFERS]; -+ int max_temp; -+ int temp_in_use; -+ int unmanaged_buffer_allocs; -+ int unmanaged_buffer_deallocs; -+ -+ /* yaffs2 runtime stuff */ -+ unsigned seq_number; /* Sequence number of currently allocating block */ -+ unsigned oldest_dirty_seq; -+ unsigned oldest_dirty_block; -+ -+ /* Block refreshing */ -+ int refresh_skip; /* A skip down counter. Refresh happens when this gets to zero. */ -+ -+ /* Dirty directory handling */ -+ struct list_head dirty_dirs; /* List of dirty directories */ -+ -+ /* Statistcs */ -+ u32 n_page_writes; -+ u32 n_page_reads; -+ u32 n_erasures; -+ u32 n_erase_failures; -+ u32 n_gc_copies; -+ u32 all_gcs; -+ u32 passive_gc_count; -+ u32 oldest_dirty_gc_count; -+ u32 n_gc_blocks; -+ u32 bg_gcs; -+ u32 n_retired_writes; -+ u32 n_retired_blocks; -+ u32 n_ecc_fixed; -+ u32 n_ecc_unfixed; -+ u32 n_tags_ecc_fixed; -+ u32 n_tags_ecc_unfixed; -+ u32 n_deletions; -+ u32 n_unmarked_deletions; -+ u32 refresh_count; -+ u32 cache_hits; -+ -+}; -+ -+/* The CheckpointDevice structure holds the device information that changes at runtime and -+ * must be preserved over unmount/mount cycles. -+ */ -+struct yaffs_checkpt_dev { -+ int struct_type; -+ int n_erased_blocks; -+ int alloc_block; /* Current block being allocated off */ -+ u32 alloc_page; -+ int n_free_chunks; -+ -+ int n_deleted_files; /* Count of files awaiting deletion; */ -+ int n_unlinked_files; /* Count of unlinked files. */ -+ int n_bg_deletions; /* Count of background deletions. */ -+ -+ /* yaffs2 runtime stuff */ -+ unsigned seq_number; /* Sequence number of currently allocating block */ -+ -+}; -+ -+struct yaffs_checkpt_validity { -+ int struct_type; -+ u32 magic; -+ u32 version; -+ u32 head; -+}; -+ -+struct yaffs_shadow_fixer { -+ int obj_id; -+ int shadowed_id; -+ struct yaffs_shadow_fixer *next; -+}; -+ -+/* Structure for doing xattr modifications */ -+struct yaffs_xattr_mod { -+ int set; /* If 0 then this is a deletion */ -+ const YCHAR *name; -+ const void *data; -+ int size; -+ int flags; -+ int result; -+}; -+ -+/*----------------------- YAFFS Functions -----------------------*/ -+ -+int yaffs_guts_initialise(struct yaffs_dev *dev); -+void yaffs_deinitialise(struct yaffs_dev *dev); -+ -+int yaffs_get_n_free_chunks(struct yaffs_dev *dev); -+ -+int yaffs_rename_obj(struct yaffs_obj *old_dir, const YCHAR * old_name, -+ struct yaffs_obj *new_dir, const YCHAR * new_name); -+ -+int yaffs_unlinker(struct yaffs_obj *dir, const YCHAR * name); -+int yaffs_del_obj(struct yaffs_obj *obj); -+ -+int yaffs_get_obj_name(struct yaffs_obj *obj, YCHAR * name, int buffer_size); -+int yaffs_get_obj_length(struct yaffs_obj *obj); -+int yaffs_get_obj_inode(struct yaffs_obj *obj); -+unsigned yaffs_get_obj_type(struct yaffs_obj *obj); -+int yaffs_get_obj_link_count(struct yaffs_obj *obj); -+ -+/* File operations */ -+int yaffs_file_rd(struct yaffs_obj *obj, u8 * buffer, loff_t offset, -+ int n_bytes); -+int yaffs_wr_file(struct yaffs_obj *obj, const u8 * buffer, loff_t offset, -+ int n_bytes, int write_trhrough); -+int yaffs_resize_file(struct yaffs_obj *obj, loff_t new_size); -+ -+struct yaffs_obj *yaffs_create_file(struct yaffs_obj *parent, -+ const YCHAR * name, u32 mode, u32 uid, -+ u32 gid); -+ -+int yaffs_flush_file(struct yaffs_obj *obj, int update_time, int data_sync); -+ -+/* Flushing and checkpointing */ -+void yaffs_flush_whole_cache(struct yaffs_dev *dev); -+ -+int yaffs_checkpoint_save(struct yaffs_dev *dev); -+int yaffs_checkpoint_restore(struct yaffs_dev *dev); -+ -+/* Directory operations */ -+struct yaffs_obj *yaffs_create_dir(struct yaffs_obj *parent, const YCHAR * name, -+ u32 mode, u32 uid, u32 gid); -+struct yaffs_obj *yaffs_find_by_name(struct yaffs_obj *the_dir, -+ const YCHAR * name); -+struct yaffs_obj *yaffs_find_by_number(struct yaffs_dev *dev, u32 number); -+ -+/* Link operations */ -+struct yaffs_obj *yaffs_link_obj(struct yaffs_obj *parent, const YCHAR * name, -+ struct yaffs_obj *equiv_obj); -+ -+struct yaffs_obj *yaffs_get_equivalent_obj(struct yaffs_obj *obj); -+ -+/* Symlink operations */ -+struct yaffs_obj *yaffs_create_symlink(struct yaffs_obj *parent, -+ const YCHAR * name, u32 mode, u32 uid, -+ u32 gid, const YCHAR * alias); -+YCHAR *yaffs_get_symlink_alias(struct yaffs_obj *obj); -+ -+/* Special inodes (fifos, sockets and devices) */ -+struct yaffs_obj *yaffs_create_special(struct yaffs_obj *parent, -+ const YCHAR * name, u32 mode, u32 uid, -+ u32 gid, u32 rdev); -+ -+int yaffs_set_xattrib(struct yaffs_obj *obj, const YCHAR * name, -+ const void *value, int size, int flags); -+int yaffs_get_xattrib(struct yaffs_obj *obj, const YCHAR * name, void *value, -+ int size); -+int yaffs_list_xattrib(struct yaffs_obj *obj, char *buffer, int size); -+int yaffs_remove_xattrib(struct yaffs_obj *obj, const YCHAR * name); -+ -+/* Special directories */ -+struct yaffs_obj *yaffs_root(struct yaffs_dev *dev); -+struct yaffs_obj *yaffs_lost_n_found(struct yaffs_dev *dev); -+ -+void yaffs_handle_defered_free(struct yaffs_obj *obj); -+ -+void yaffs_update_dirty_dirs(struct yaffs_dev *dev); -+ -+int yaffs_bg_gc(struct yaffs_dev *dev, unsigned urgency); -+ -+/* Debug dump */ -+int yaffs_dump_obj(struct yaffs_obj *obj); -+ -+void yaffs_guts_test(struct yaffs_dev *dev); -+ -+/* A few useful functions to be used within the core files*/ -+void yaffs_chunk_del(struct yaffs_dev *dev, int chunk_id, int mark_flash, -+ int lyn); -+int yaffs_check_ff(u8 * buffer, int n_bytes); -+void yaffs_handle_chunk_error(struct yaffs_dev *dev, -+ struct yaffs_block_info *bi); -+ -+u8 *yaffs_get_temp_buffer(struct yaffs_dev *dev, int line_no); -+void yaffs_release_temp_buffer(struct yaffs_dev *dev, u8 * buffer, int line_no); -+ -+struct yaffs_obj *yaffs_find_or_create_by_number(struct yaffs_dev *dev, -+ int number, -+ enum yaffs_obj_type type); -+int yaffs_put_chunk_in_file(struct yaffs_obj *in, int inode_chunk, -+ int nand_chunk, int in_scan); -+void yaffs_set_obj_name(struct yaffs_obj *obj, const YCHAR * name); -+void yaffs_set_obj_name_from_oh(struct yaffs_obj *obj, -+ const struct yaffs_obj_hdr *oh); -+void yaffs_add_obj_to_dir(struct yaffs_obj *directory, struct yaffs_obj *obj); -+YCHAR *yaffs_clone_str(const YCHAR * str); -+void yaffs_link_fixup(struct yaffs_dev *dev, struct yaffs_obj *hard_list); -+void yaffs_block_became_dirty(struct yaffs_dev *dev, int block_no); -+int yaffs_update_oh(struct yaffs_obj *in, const YCHAR * name, -+ int force, int is_shrink, int shadows, -+ struct yaffs_xattr_mod *xop); -+void yaffs_handle_shadowed_obj(struct yaffs_dev *dev, int obj_id, -+ int backward_scanning); -+int yaffs_check_alloc_available(struct yaffs_dev *dev, int n_chunks); -+struct yaffs_tnode *yaffs_get_tnode(struct yaffs_dev *dev); -+struct yaffs_tnode *yaffs_add_find_tnode_0(struct yaffs_dev *dev, -+ struct yaffs_file_var *file_struct, -+ u32 chunk_id, -+ struct yaffs_tnode *passed_tn); -+ -+int yaffs_do_file_wr(struct yaffs_obj *in, const u8 * buffer, loff_t offset, -+ int n_bytes, int write_trhrough); -+void yaffs_resize_file_down(struct yaffs_obj *obj, loff_t new_size); -+void yaffs_skip_rest_of_block(struct yaffs_dev *dev); -+ -+int yaffs_count_free_chunks(struct yaffs_dev *dev); -+ -+struct yaffs_tnode *yaffs_find_tnode_0(struct yaffs_dev *dev, -+ struct yaffs_file_var *file_struct, -+ u32 chunk_id); -+ -+u32 yaffs_get_group_base(struct yaffs_dev *dev, struct yaffs_tnode *tn, -+ unsigned pos); -+ -+#endif -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_linux.h linux-2.6.36/fs/yaffs2/yaffs_linux.h ---- linux-2.6.36.orig/fs/yaffs2/yaffs_linux.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_linux.h 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,41 @@ -+/* -+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU Lesser General Public License version 2.1 as -+ * published by the Free Software Foundation. -+ * -+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. -+ */ -+ -+#ifndef __YAFFS_LINUX_H__ -+#define __YAFFS_LINUX_H__ -+ -+#include "yportenv.h" -+ -+struct yaffs_linux_context { -+ struct list_head context_list; /* List of these we have mounted */ -+ struct yaffs_dev *dev; -+ struct super_block *super; -+ struct task_struct *bg_thread; /* Background thread for this device */ -+ int bg_running; -+ struct mutex gross_lock; /* Gross locking mutex*/ -+ u8 *spare_buffer; /* For mtdif2 use. Don't know the size of the buffer -+ * at compile time so we have to allocate it. -+ */ -+ struct list_head search_contexts; -+ void (*put_super_fn) (struct super_block * sb); -+ -+ struct task_struct *readdir_process; -+ unsigned mount_id; -+}; -+ -+#define yaffs_dev_to_lc(dev) ((struct yaffs_linux_context *)((dev)->os_context)) -+#define yaffs_dev_to_mtd(dev) ((struct mtd_info *)((dev)->driver_context)) -+ -+#endif -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_mtdif.c linux-2.6.36/fs/yaffs2/yaffs_mtdif.c ---- linux-2.6.36.orig/fs/yaffs2/yaffs_mtdif.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_mtdif.c 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,54 @@ -+/* -+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include "yportenv.h" -+ -+#include "yaffs_mtdif.h" -+ -+#include "linux/mtd/mtd.h" -+#include "linux/types.h" -+#include "linux/time.h" -+#include "linux/mtd/nand.h" -+ -+#include "yaffs_linux.h" -+ -+int nandmtd_erase_block(struct yaffs_dev *dev, int block_no) -+{ -+ struct mtd_info *mtd = yaffs_dev_to_mtd(dev); -+ u32 addr = -+ ((loff_t) block_no) * dev->param.total_bytes_per_chunk -+ * dev->param.chunks_per_block; -+ struct erase_info ei; -+ -+ int retval = 0; -+ -+ ei.mtd = mtd; -+ ei.addr = addr; -+ ei.len = dev->param.total_bytes_per_chunk * dev->param.chunks_per_block; -+ ei.time = 1000; -+ ei.retries = 2; -+ ei.callback = NULL; -+ ei.priv = (u_long) dev; -+ -+ retval = mtd->erase(mtd, &ei); -+ -+ if (retval == 0) -+ return YAFFS_OK; -+ else -+ return YAFFS_FAIL; -+} -+ -+int nandmtd_initialise(struct yaffs_dev *dev) -+{ -+ return YAFFS_OK; -+} -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_mtdif.h linux-2.6.36/fs/yaffs2/yaffs_mtdif.h ---- linux-2.6.36.orig/fs/yaffs2/yaffs_mtdif.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_mtdif.h 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,23 @@ -+/* -+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU Lesser General Public License version 2.1 as -+ * published by the Free Software Foundation. -+ * -+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. -+ */ -+ -+#ifndef __YAFFS_MTDIF_H__ -+#define __YAFFS_MTDIF_H__ -+ -+#include "yaffs_guts.h" -+ -+int nandmtd_erase_block(struct yaffs_dev *dev, int block_no); -+int nandmtd_initialise(struct yaffs_dev *dev); -+#endif -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_mtdif1.c linux-2.6.36/fs/yaffs2/yaffs_mtdif1.c ---- linux-2.6.36.orig/fs/yaffs2/yaffs_mtdif1.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_mtdif1.c 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,365 @@ -+/* -+ * YAFFS: Yet another FFS. A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+/* -+ * This module provides the interface between yaffs_nand.c and the -+ * MTD API. This version is used when the MTD interface supports the -+ * 'mtd_oob_ops' style calls to read_oob and write_oob, circa 2.6.17, -+ * and we have small-page NAND device. -+ * -+ * These functions are invoked via function pointers in yaffs_nand.c. -+ * This replaces functionality provided by functions in yaffs_mtdif.c -+ * and the yaffs_tags compatability functions in yaffs_tagscompat.c that are -+ * called in yaffs_mtdif.c when the function pointers are NULL. -+ * We assume the MTD layer is performing ECC (use_nand_ecc is true). -+ */ -+ -+#include "yportenv.h" -+#include "yaffs_trace.h" -+#include "yaffs_guts.h" -+#include "yaffs_packedtags1.h" -+#include "yaffs_tagscompat.h" /* for yaffs_calc_tags_ecc */ -+#include "yaffs_linux.h" -+ -+#include "linux/kernel.h" -+#include "linux/version.h" -+#include "linux/types.h" -+#include "linux/mtd/mtd.h" -+ -+/* Don't compile this module if we don't have MTD's mtd_oob_ops interface */ -+#if (MTD_VERSION_CODE > MTD_VERSION(2, 6, 17)) -+ -+#ifndef CONFIG_YAFFS_9BYTE_TAGS -+# define YTAG1_SIZE 8 -+#else -+# define YTAG1_SIZE 9 -+#endif -+ -+#if 0 -+/* Use the following nand_ecclayout with MTD when using -+ * CONFIG_YAFFS_9BYTE_TAGS and the older on-NAND tags layout. -+ * If you have existing Yaffs images and the byte order differs from this, -+ * adjust 'oobfree' to match your existing Yaffs data. -+ * -+ * This nand_ecclayout scatters/gathers to/from the old-yaffs layout with the -+ * page_status byte (at NAND spare offset 4) scattered/gathered from/to -+ * the 9th byte. -+ * -+ * Old-style on-NAND format: T0,T1,T2,T3,P,B,T4,T5,E0,E1,E2,T6,T7,E3,E4,E5 -+ * We have/need packed_tags1 plus page_status: T0,T1,T2,T3,T4,T5,T6,T7,P -+ * where Tn are the tag bytes, En are MTD's ECC bytes, P is the page_status -+ * byte and B is the small-page bad-block indicator byte. -+ */ -+static struct nand_ecclayout nand_oob_16 = { -+ .eccbytes = 6, -+ .eccpos = {8, 9, 10, 13, 14, 15}, -+ .oobavail = 9, -+ .oobfree = {{0, 4}, {6, 2}, {11, 2}, {4, 1}} -+}; -+#endif -+ -+/* Write a chunk (page) of data to NAND. -+ * -+ * Caller always provides ExtendedTags data which are converted to a more -+ * compact (packed) form for storage in NAND. A mini-ECC runs over the -+ * contents of the tags meta-data; used to valid the tags when read. -+ * -+ * - Pack ExtendedTags to packed_tags1 form -+ * - Compute mini-ECC for packed_tags1 -+ * - Write data and packed tags to NAND. -+ * -+ * Note: Due to the use of the packed_tags1 meta-data which does not include -+ * a full sequence number (as found in the larger packed_tags2 form) it is -+ * necessary for Yaffs to re-write a chunk/page (just once) to mark it as -+ * discarded and dirty. This is not ideal: newer NAND parts are supposed -+ * to be written just once. When Yaffs performs this operation, this -+ * function is called with a NULL data pointer -- calling MTD write_oob -+ * without data is valid usage (2.6.17). -+ * -+ * Any underlying MTD error results in YAFFS_FAIL. -+ * Returns YAFFS_OK or YAFFS_FAIL. -+ */ -+int nandmtd1_write_chunk_tags(struct yaffs_dev *dev, -+ int nand_chunk, const u8 * data, -+ const struct yaffs_ext_tags *etags) -+{ -+ struct mtd_info *mtd = yaffs_dev_to_mtd(dev); -+ int chunk_bytes = dev->data_bytes_per_chunk; -+ loff_t addr = ((loff_t) nand_chunk) * chunk_bytes; -+ struct mtd_oob_ops ops; -+ struct yaffs_packed_tags1 pt1; -+ int retval; -+ -+ /* we assume that packed_tags1 and struct yaffs_tags are compatible */ -+ compile_time_assertion(sizeof(struct yaffs_packed_tags1) == 12); -+ compile_time_assertion(sizeof(struct yaffs_tags) == 8); -+ -+ yaffs_pack_tags1(&pt1, etags); -+ yaffs_calc_tags_ecc((struct yaffs_tags *)&pt1); -+ -+ /* When deleting a chunk, the upper layer provides only skeletal -+ * etags, one with is_deleted set. However, we need to update the -+ * tags, not erase them completely. So we use the NAND write property -+ * that only zeroed-bits stick and set tag bytes to all-ones and -+ * zero just the (not) deleted bit. -+ */ -+#ifndef CONFIG_YAFFS_9BYTE_TAGS -+ if (etags->is_deleted) { -+ memset(&pt1, 0xff, 8); -+ /* clear delete status bit to indicate deleted */ -+ pt1.deleted = 0; -+ } -+#else -+ ((u8 *) & pt1)[8] = 0xff; -+ if (etags->is_deleted) { -+ memset(&pt1, 0xff, 8); -+ /* zero page_status byte to indicate deleted */ -+ ((u8 *) & pt1)[8] = 0; -+ } -+#endif -+ -+ memset(&ops, 0, sizeof(ops)); -+ ops.mode = MTD_OOB_AUTO; -+ ops.len = (data) ? chunk_bytes : 0; -+ ops.ooblen = YTAG1_SIZE; -+ ops.datbuf = (u8 *) data; -+ ops.oobbuf = (u8 *) & pt1; -+ -+ retval = mtd->write_oob(mtd, addr, &ops); -+ if (retval) { -+ T(YAFFS_TRACE_MTD, -+ (TSTR("write_oob failed, chunk %d, mtd error %d" TENDSTR), -+ nand_chunk, retval)); -+ } -+ return retval ? YAFFS_FAIL : YAFFS_OK; -+} -+ -+/* Return with empty ExtendedTags but add ecc_result. -+ */ -+static int rettags(struct yaffs_ext_tags *etags, int ecc_result, int retval) -+{ -+ if (etags) { -+ memset(etags, 0, sizeof(*etags)); -+ etags->ecc_result = ecc_result; -+ } -+ return retval; -+} -+ -+/* Read a chunk (page) from NAND. -+ * -+ * Caller expects ExtendedTags data to be usable even on error; that is, -+ * all members except ecc_result and block_bad are zeroed. -+ * -+ * - Check ECC results for data (if applicable) -+ * - Check for blank/erased block (return empty ExtendedTags if blank) -+ * - Check the packed_tags1 mini-ECC (correct if necessary/possible) -+ * - Convert packed_tags1 to ExtendedTags -+ * - Update ecc_result and block_bad members to refect state. -+ * -+ * Returns YAFFS_OK or YAFFS_FAIL. -+ */ -+int nandmtd1_read_chunk_tags(struct yaffs_dev *dev, -+ int nand_chunk, u8 * data, -+ struct yaffs_ext_tags *etags) -+{ -+ struct mtd_info *mtd = yaffs_dev_to_mtd(dev); -+ int chunk_bytes = dev->data_bytes_per_chunk; -+ loff_t addr = ((loff_t) nand_chunk) * chunk_bytes; -+ int eccres = YAFFS_ECC_RESULT_NO_ERROR; -+ struct mtd_oob_ops ops; -+ struct yaffs_packed_tags1 pt1; -+ int retval; -+ int deleted; -+ -+ memset(&ops, 0, sizeof(ops)); -+ ops.mode = MTD_OOB_AUTO; -+ ops.len = (data) ? chunk_bytes : 0; -+ ops.ooblen = YTAG1_SIZE; -+ ops.datbuf = data; -+ ops.oobbuf = (u8 *) & pt1; -+ -+#if (MTD_VERSION_CODE < MTD_VERSION(2, 6, 20)) -+ /* In MTD 2.6.18 to 2.6.19 nand_base.c:nand_do_read_oob() has a bug; -+ * help it out with ops.len = ops.ooblen when ops.datbuf == NULL. -+ */ -+ ops.len = (ops.datbuf) ? ops.len : ops.ooblen; -+#endif -+ /* Read page and oob using MTD. -+ * Check status and determine ECC result. -+ */ -+ retval = mtd->read_oob(mtd, addr, &ops); -+ if (retval) { -+ T(YAFFS_TRACE_MTD, -+ (TSTR("read_oob failed, chunk %d, mtd error %d" TENDSTR), -+ nand_chunk, retval)); -+ } -+ -+ switch (retval) { -+ case 0: -+ /* no error */ -+ break; -+ -+ case -EUCLEAN: -+ /* MTD's ECC fixed the data */ -+ eccres = YAFFS_ECC_RESULT_FIXED; -+ dev->n_ecc_fixed++; -+ break; -+ -+ case -EBADMSG: -+ /* MTD's ECC could not fix the data */ -+ dev->n_ecc_unfixed++; -+ /* fall into... */ -+ default: -+ rettags(etags, YAFFS_ECC_RESULT_UNFIXED, 0); -+ etags->block_bad = (mtd->block_isbad) (mtd, addr); -+ return YAFFS_FAIL; -+ } -+ -+ /* Check for a blank/erased chunk. -+ */ -+ if (yaffs_check_ff((u8 *) & pt1, 8)) { -+ /* when blank, upper layers want ecc_result to be <= NO_ERROR */ -+ return rettags(etags, YAFFS_ECC_RESULT_NO_ERROR, YAFFS_OK); -+ } -+#ifndef CONFIG_YAFFS_9BYTE_TAGS -+ /* Read deleted status (bit) then return it to it's non-deleted -+ * state before performing tags mini-ECC check. pt1.deleted is -+ * inverted. -+ */ -+ deleted = !pt1.deleted; -+ pt1.deleted = 1; -+#else -+ deleted = (yaffs_count_bits(((u8 *) & pt1)[8]) < 7); -+#endif -+ -+ /* Check the packed tags mini-ECC and correct if necessary/possible. -+ */ -+ retval = yaffs_check_tags_ecc((struct yaffs_tags *)&pt1); -+ switch (retval) { -+ case 0: -+ /* no tags error, use MTD result */ -+ break; -+ case 1: -+ /* recovered tags-ECC error */ -+ dev->n_tags_ecc_fixed++; -+ if (eccres == YAFFS_ECC_RESULT_NO_ERROR) -+ eccres = YAFFS_ECC_RESULT_FIXED; -+ break; -+ default: -+ /* unrecovered tags-ECC error */ -+ dev->n_tags_ecc_unfixed++; -+ return rettags(etags, YAFFS_ECC_RESULT_UNFIXED, YAFFS_FAIL); -+ } -+ -+ /* Unpack the tags to extended form and set ECC result. -+ * [set should_be_ff just to keep yaffs_unpack_tags1 happy] -+ */ -+ pt1.should_be_ff = 0xFFFFFFFF; -+ yaffs_unpack_tags1(etags, &pt1); -+ etags->ecc_result = eccres; -+ -+ /* Set deleted state */ -+ etags->is_deleted = deleted; -+ return YAFFS_OK; -+} -+ -+/* Mark a block bad. -+ * -+ * This is a persistant state. -+ * Use of this function should be rare. -+ * -+ * Returns YAFFS_OK or YAFFS_FAIL. -+ */ -+int nandmtd1_mark_block_bad(struct yaffs_dev *dev, int block_no) -+{ -+ struct mtd_info *mtd = yaffs_dev_to_mtd(dev); -+ int blocksize = dev->param.chunks_per_block * dev->data_bytes_per_chunk; -+ int retval; -+ -+ T(YAFFS_TRACE_BAD_BLOCKS, -+ (TSTR("marking block %d bad" TENDSTR), block_no)); -+ -+ retval = mtd->block_markbad(mtd, (loff_t) blocksize * block_no); -+ return (retval) ? YAFFS_FAIL : YAFFS_OK; -+} -+ -+/* Check any MTD prerequists. -+ * -+ * Returns YAFFS_OK or YAFFS_FAIL. -+ */ -+static int nandmtd1_test_prerequists(struct mtd_info *mtd) -+{ -+ /* 2.6.18 has mtd->ecclayout->oobavail */ -+ /* 2.6.21 has mtd->ecclayout->oobavail and mtd->oobavail */ -+ int oobavail = mtd->ecclayout->oobavail; -+ -+ if (oobavail < YTAG1_SIZE) { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR -+ ("mtd device has only %d bytes for tags, need %d" TENDSTR), -+ oobavail, YTAG1_SIZE)); -+ return YAFFS_FAIL; -+ } -+ return YAFFS_OK; -+} -+ -+/* Query for the current state of a specific block. -+ * -+ * Examine the tags of the first chunk of the block and return the state: -+ * - YAFFS_BLOCK_STATE_DEAD, the block is marked bad -+ * - YAFFS_BLOCK_STATE_NEEDS_SCANNING, the block is in use -+ * - YAFFS_BLOCK_STATE_EMPTY, the block is clean -+ * -+ * Always returns YAFFS_OK. -+ */ -+int nandmtd1_query_block(struct yaffs_dev *dev, int block_no, -+ enum yaffs_block_state *state_ptr, u32 * seq_ptr) -+{ -+ struct mtd_info *mtd = yaffs_dev_to_mtd(dev); -+ int chunk_num = block_no * dev->param.chunks_per_block; -+ loff_t addr = (loff_t) chunk_num * dev->data_bytes_per_chunk; -+ struct yaffs_ext_tags etags; -+ int state = YAFFS_BLOCK_STATE_DEAD; -+ int seqnum = 0; -+ int retval; -+ -+ /* We don't yet have a good place to test for MTD config prerequists. -+ * Do it here as we are called during the initial scan. -+ */ -+ if (nandmtd1_test_prerequists(mtd) != YAFFS_OK) -+ return YAFFS_FAIL; -+ -+ retval = nandmtd1_read_chunk_tags(dev, chunk_num, NULL, &etags); -+ etags.block_bad = (mtd->block_isbad) (mtd, addr); -+ if (etags.block_bad) { -+ T(YAFFS_TRACE_BAD_BLOCKS, -+ (TSTR("block %d is marked bad" TENDSTR), block_no)); -+ state = YAFFS_BLOCK_STATE_DEAD; -+ } else if (etags.ecc_result != YAFFS_ECC_RESULT_NO_ERROR) { -+ /* bad tags, need to look more closely */ -+ state = YAFFS_BLOCK_STATE_NEEDS_SCANNING; -+ } else if (etags.chunk_used) { -+ state = YAFFS_BLOCK_STATE_NEEDS_SCANNING; -+ seqnum = etags.seq_number; -+ } else { -+ state = YAFFS_BLOCK_STATE_EMPTY; -+ } -+ -+ *state_ptr = state; -+ *seq_ptr = seqnum; -+ -+ /* query always succeeds */ -+ return YAFFS_OK; -+} -+ -+#endif /*MTD_VERSION */ -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_mtdif1.h linux-2.6.36/fs/yaffs2/yaffs_mtdif1.h ---- linux-2.6.36.orig/fs/yaffs2/yaffs_mtdif1.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_mtdif1.h 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,29 @@ -+/* -+ * YAFFS: Yet another Flash File System. A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU Lesser General Public License version 2.1 as -+ * published by the Free Software Foundation. -+ * -+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. -+ */ -+ -+#ifndef __YAFFS_MTDIF1_H__ -+#define __YAFFS_MTDIF1_H__ -+ -+int nandmtd1_write_chunk_tags(struct yaffs_dev *dev, int nand_chunk, -+ const u8 * data, -+ const struct yaffs_ext_tags *tags); -+ -+int nandmtd1_read_chunk_tags(struct yaffs_dev *dev, int nand_chunk, -+ u8 * data, struct yaffs_ext_tags *tags); -+ -+int nandmtd1_mark_block_bad(struct yaffs_dev *dev, int block_no); -+ -+int nandmtd1_query_block(struct yaffs_dev *dev, int block_no, -+ enum yaffs_block_state *state, u32 * seq_number); -+ -+#endif -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_mtdif2.c linux-2.6.36/fs/yaffs2/yaffs_mtdif2.c ---- linux-2.6.36.orig/fs/yaffs2/yaffs_mtdif2.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_mtdif2.c 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,261 @@ -+/* -+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+/* mtd interface for YAFFS2 */ -+ -+#include "yportenv.h" -+#include "yaffs_trace.h" -+ -+#include "yaffs_mtdif2.h" -+ -+#include "linux/mtd/mtd.h" -+#include "linux/types.h" -+#include "linux/time.h" -+ -+#include "yaffs_packedtags2.h" -+ -+#include "yaffs_linux.h" -+ -+/* NB For use with inband tags.... -+ * We assume that the data buffer is of size total_bytes_per_chunk so that we can also -+ * use it to load the tags. -+ */ -+int nandmtd2_write_chunk_tags(struct yaffs_dev *dev, int nand_chunk, -+ const u8 * data, -+ const struct yaffs_ext_tags *tags) -+{ -+ struct mtd_info *mtd = yaffs_dev_to_mtd(dev); -+#if (MTD_VERSION_CODE > MTD_VERSION(2, 6, 17)) -+ struct mtd_oob_ops ops; -+#else -+ size_t dummy; -+#endif -+ int retval = 0; -+ -+ loff_t addr; -+ -+ struct yaffs_packed_tags2 pt; -+ -+ int packed_tags_size = -+ dev->param.no_tags_ecc ? sizeof(pt.t) : sizeof(pt); -+ void *packed_tags_ptr = -+ dev->param.no_tags_ecc ? (void *)&pt.t : (void *)&pt; -+ -+ T(YAFFS_TRACE_MTD, -+ (TSTR -+ ("nandmtd2_write_chunk_tags chunk %d data %p tags %p" -+ TENDSTR), nand_chunk, data, tags)); -+ -+ addr = ((loff_t) nand_chunk) * dev->param.total_bytes_per_chunk; -+ -+ /* For yaffs2 writing there must be both data and tags. -+ * If we're using inband tags, then the tags are stuffed into -+ * the end of the data buffer. -+ */ -+ if (!data || !tags) -+ BUG(); -+ else if (dev->param.inband_tags) { -+ struct yaffs_packed_tags2_tags_only *pt2tp; -+ pt2tp = -+ (struct yaffs_packed_tags2_tags_only *)(data + -+ dev-> -+ data_bytes_per_chunk); -+ yaffs_pack_tags2_tags_only(pt2tp, tags); -+ } else { -+ yaffs_pack_tags2(&pt, tags, !dev->param.no_tags_ecc); -+ } -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17)) -+ ops.mode = MTD_OOB_AUTO; -+ ops.ooblen = (dev->param.inband_tags) ? 0 : packed_tags_size; -+ ops.len = dev->param.total_bytes_per_chunk; -+ ops.ooboffs = 0; -+ ops.datbuf = (u8 *) data; -+ ops.oobbuf = (dev->param.inband_tags) ? NULL : packed_tags_ptr; -+ retval = mtd->write_oob(mtd, addr, &ops); -+ -+#else -+ if (!dev->param.inband_tags) { -+ retval = -+ mtd->write_ecc(mtd, addr, dev->data_bytes_per_chunk, -+ &dummy, data, (u8 *) packed_tags_ptr, NULL); -+ } else { -+ retval = -+ mtd->write(mtd, addr, dev->param.total_bytes_per_chunk, -+ &dummy, data); -+ } -+#endif -+ -+ if (retval == 0) -+ return YAFFS_OK; -+ else -+ return YAFFS_FAIL; -+} -+ -+int nandmtd2_read_chunk_tags(struct yaffs_dev *dev, int nand_chunk, -+ u8 * data, struct yaffs_ext_tags *tags) -+{ -+ struct mtd_info *mtd = yaffs_dev_to_mtd(dev); -+#if (MTD_VERSION_CODE > MTD_VERSION(2, 6, 17)) -+ struct mtd_oob_ops ops; -+#endif -+ size_t dummy; -+ int retval = 0; -+ int local_data = 0; -+ -+ loff_t addr = ((loff_t) nand_chunk) * dev->param.total_bytes_per_chunk; -+ -+ struct yaffs_packed_tags2 pt; -+ -+ int packed_tags_size = -+ dev->param.no_tags_ecc ? sizeof(pt.t) : sizeof(pt); -+ void *packed_tags_ptr = -+ dev->param.no_tags_ecc ? (void *)&pt.t : (void *)&pt; -+ -+ T(YAFFS_TRACE_MTD, -+ (TSTR -+ ("nandmtd2_read_chunk_tags chunk %d data %p tags %p" -+ TENDSTR), nand_chunk, data, tags)); -+ -+ if (dev->param.inband_tags) { -+ -+ if (!data) { -+ local_data = 1; -+ data = yaffs_get_temp_buffer(dev, __LINE__); -+ } -+ -+ } -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17)) -+ if (dev->param.inband_tags || (data && !tags)) -+ retval = mtd->read(mtd, addr, dev->param.total_bytes_per_chunk, -+ &dummy, data); -+ else if (tags) { -+ ops.mode = MTD_OOB_AUTO; -+ ops.ooblen = packed_tags_size; -+ ops.len = data ? dev->data_bytes_per_chunk : packed_tags_size; -+ ops.ooboffs = 0; -+ ops.datbuf = data; -+ ops.oobbuf = yaffs_dev_to_lc(dev)->spare_buffer; -+ retval = mtd->read_oob(mtd, addr, &ops); -+ } -+#else -+ if (!dev->param.inband_tags && data && tags) { -+ -+ retval = mtd->read_ecc(mtd, addr, dev->data_bytes_per_chunk, -+ &dummy, data, dev->spare_buffer, NULL); -+ } else { -+ if (data) -+ retval = -+ mtd->read(mtd, addr, dev->data_bytes_per_chunk, -+ &dummy, data); -+ if (!dev->param.inband_tags && tags) -+ retval = -+ mtd->read_oob(mtd, addr, mtd->oobsize, &dummy, -+ dev->spare_buffer); -+ } -+#endif -+ -+ if (dev->param.inband_tags) { -+ if (tags) { -+ struct yaffs_packed_tags2_tags_only *pt2tp; -+ pt2tp = -+ (struct yaffs_packed_tags2_tags_only *)&data[dev-> -+ data_bytes_per_chunk]; -+ yaffs_unpack_tags2_tags_only(tags, pt2tp); -+ } -+ } else { -+ if (tags) { -+ memcpy(packed_tags_ptr, -+ yaffs_dev_to_lc(dev)->spare_buffer, -+ packed_tags_size); -+ yaffs_unpack_tags2(tags, &pt, !dev->param.no_tags_ecc); -+ } -+ } -+ -+ if (local_data) -+ yaffs_release_temp_buffer(dev, data, __LINE__); -+ -+ if (tags && retval == -EBADMSG -+ && tags->ecc_result == YAFFS_ECC_RESULT_NO_ERROR) { -+ tags->ecc_result = YAFFS_ECC_RESULT_UNFIXED; -+ dev->n_ecc_unfixed++; -+ } -+ if (tags && retval == -EUCLEAN -+ && tags->ecc_result == YAFFS_ECC_RESULT_NO_ERROR) { -+ tags->ecc_result = YAFFS_ECC_RESULT_FIXED; -+ dev->n_ecc_fixed++; -+ } -+ if (retval == 0) -+ return YAFFS_OK; -+ else -+ return YAFFS_FAIL; -+} -+ -+int nandmtd2_mark_block_bad(struct yaffs_dev *dev, int block_no) -+{ -+ struct mtd_info *mtd = yaffs_dev_to_mtd(dev); -+ int retval; -+ T(YAFFS_TRACE_MTD, -+ (TSTR("nandmtd2_mark_block_bad %d" TENDSTR), block_no)); -+ -+ retval = -+ mtd->block_markbad(mtd, -+ block_no * dev->param.chunks_per_block * -+ dev->param.total_bytes_per_chunk); -+ -+ if (retval == 0) -+ return YAFFS_OK; -+ else -+ return YAFFS_FAIL; -+ -+} -+ -+int nandmtd2_query_block(struct yaffs_dev *dev, int block_no, -+ enum yaffs_block_state *state, u32 * seq_number) -+{ -+ struct mtd_info *mtd = yaffs_dev_to_mtd(dev); -+ int retval; -+ -+ T(YAFFS_TRACE_MTD, (TSTR("nandmtd2_query_block %d" TENDSTR), block_no)); -+ retval = -+ mtd->block_isbad(mtd, -+ block_no * dev->param.chunks_per_block * -+ dev->param.total_bytes_per_chunk); -+ -+ if (retval) { -+ T(YAFFS_TRACE_MTD, (TSTR("block is bad" TENDSTR))); -+ -+ *state = YAFFS_BLOCK_STATE_DEAD; -+ *seq_number = 0; -+ } else { -+ struct yaffs_ext_tags t; -+ nandmtd2_read_chunk_tags(dev, block_no * -+ dev->param.chunks_per_block, NULL, &t); -+ -+ if (t.chunk_used) { -+ *seq_number = t.seq_number; -+ *state = YAFFS_BLOCK_STATE_NEEDS_SCANNING; -+ } else { -+ *seq_number = 0; -+ *state = YAFFS_BLOCK_STATE_EMPTY; -+ } -+ } -+ T(YAFFS_TRACE_MTD, -+ (TSTR("block is bad seq %d state %d" TENDSTR), *seq_number, *state)); -+ -+ if (retval == 0) -+ return YAFFS_OK; -+ else -+ return YAFFS_FAIL; -+} -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_mtdif2.h linux-2.6.36/fs/yaffs2/yaffs_mtdif2.h ---- linux-2.6.36.orig/fs/yaffs2/yaffs_mtdif2.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_mtdif2.h 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,29 @@ -+/* -+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU Lesser General Public License version 2.1 as -+ * published by the Free Software Foundation. -+ * -+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. -+ */ -+ -+#ifndef __YAFFS_MTDIF2_H__ -+#define __YAFFS_MTDIF2_H__ -+ -+#include "yaffs_guts.h" -+int nandmtd2_write_chunk_tags(struct yaffs_dev *dev, int nand_chunk, -+ const u8 * data, -+ const struct yaffs_ext_tags *tags); -+int nandmtd2_read_chunk_tags(struct yaffs_dev *dev, int nand_chunk, -+ u8 * data, struct yaffs_ext_tags *tags); -+int nandmtd2_mark_block_bad(struct yaffs_dev *dev, int block_no); -+int nandmtd2_query_block(struct yaffs_dev *dev, int block_no, -+ enum yaffs_block_state *state, u32 * seq_number); -+ -+#endif -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_nameval.c linux-2.6.36/fs/yaffs2/yaffs_nameval.c ---- linux-2.6.36.orig/fs/yaffs2/yaffs_nameval.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_nameval.c 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,201 @@ -+/* -+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+/* -+ * This simple implementation of a name-value store assumes a small number of values and fits -+ * into a small finite buffer. -+ * -+ * Each attribute is stored as a record: -+ * sizeof(int) bytes record size. -+ * strnlen+1 bytes name null terminated. -+ * nbytes value. -+ * ---------- -+ * total size stored in record size -+ * -+ * This code has not been tested with unicode yet. -+ */ -+ -+#include "yaffs_nameval.h" -+ -+#include "yportenv.h" -+ -+static int nval_find(const char *xb, int xb_size, const YCHAR * name, -+ int *exist_size) -+{ -+ int pos = 0; -+ int size; -+ -+ memcpy(&size, xb, sizeof(int)); -+ while (size > 0 && (size < xb_size) && (pos + size < xb_size)) { -+ if (yaffs_strncmp -+ ((YCHAR *) (xb + pos + sizeof(int)), name, size) == 0) { -+ if (exist_size) -+ *exist_size = size; -+ return pos; -+ } -+ pos += size; -+ if (pos < xb_size - sizeof(int)) -+ memcpy(&size, xb + pos, sizeof(int)); -+ else -+ size = 0; -+ } -+ if (exist_size) -+ *exist_size = 0; -+ return -1; -+} -+ -+static int nval_used(const char *xb, int xb_size) -+{ -+ int pos = 0; -+ int size; -+ -+ memcpy(&size, xb + pos, sizeof(int)); -+ while (size > 0 && (size < xb_size) && (pos + size < xb_size)) { -+ pos += size; -+ if (pos < xb_size - sizeof(int)) -+ memcpy(&size, xb + pos, sizeof(int)); -+ else -+ size = 0; -+ } -+ return pos; -+} -+ -+int nval_del(char *xb, int xb_size, const YCHAR * name) -+{ -+ int pos = nval_find(xb, xb_size, name, NULL); -+ int size; -+ -+ if (pos >= 0 && pos < xb_size) { -+ /* Find size, shift rest over this record, then zero out the rest of buffer */ -+ memcpy(&size, xb + pos, sizeof(int)); -+ memcpy(xb + pos, xb + pos + size, xb_size - (pos + size)); -+ memset(xb + (xb_size - size), 0, size); -+ return 0; -+ } else { -+ return -ENODATA; -+ } -+} -+ -+int nval_set(char *xb, int xb_size, const YCHAR * name, const char *buf, -+ int bsize, int flags) -+{ -+ int pos; -+ int namelen = yaffs_strnlen(name, xb_size); -+ int reclen; -+ int size_exist = 0; -+ int space; -+ int start; -+ -+ pos = nval_find(xb, xb_size, name, &size_exist); -+ -+ if (flags & XATTR_CREATE && pos >= 0) -+ return -EEXIST; -+ if (flags & XATTR_REPLACE && pos < 0) -+ return -ENODATA; -+ -+ start = nval_used(xb, xb_size); -+ space = xb_size - start + size_exist; -+ -+ reclen = (sizeof(int) + namelen + 1 + bsize); -+ -+ if (reclen > space) -+ return -ENOSPC; -+ -+ if (pos >= 0) { -+ nval_del(xb, xb_size, name); -+ start = nval_used(xb, xb_size); -+ } -+ -+ pos = start; -+ -+ memcpy(xb + pos, &reclen, sizeof(int)); -+ pos += sizeof(int); -+ yaffs_strncpy((YCHAR *) (xb + pos), name, reclen); -+ pos += (namelen + 1); -+ memcpy(xb + pos, buf, bsize); -+ return 0; -+} -+ -+int nval_get(const char *xb, int xb_size, const YCHAR * name, char *buf, -+ int bsize) -+{ -+ int pos = nval_find(xb, xb_size, name, NULL); -+ int size; -+ -+ if (pos >= 0 && pos < xb_size) { -+ -+ memcpy(&size, xb + pos, sizeof(int)); -+ pos += sizeof(int); /* advance past record length */ -+ size -= sizeof(int); -+ -+ /* Advance over name string */ -+ while (xb[pos] && size > 0 && pos < xb_size) { -+ pos++; -+ size--; -+ } -+ /*Advance over NUL */ -+ pos++; -+ size--; -+ -+ if (size <= bsize) { -+ memcpy(buf, xb + pos, size); -+ return size; -+ } -+ -+ } -+ if (pos >= 0) -+ return -ERANGE; -+ else -+ return -ENODATA; -+} -+ -+int nval_list(const char *xb, int xb_size, char *buf, int bsize) -+{ -+ int pos = 0; -+ int size; -+ int name_len; -+ int ncopied = 0; -+ int filled = 0; -+ -+ memcpy(&size, xb + pos, sizeof(int)); -+ while (size > sizeof(int) && size <= xb_size && (pos + size) < xb_size -+ && !filled) { -+ pos += sizeof(int); -+ size -= sizeof(int); -+ name_len = yaffs_strnlen((YCHAR *) (xb + pos), size); -+ if (ncopied + name_len + 1 < bsize) { -+ memcpy(buf, xb + pos, name_len * sizeof(YCHAR)); -+ buf += name_len; -+ *buf = '\0'; -+ buf++; -+ if (sizeof(YCHAR) > 1) { -+ *buf = '\0'; -+ buf++; -+ } -+ ncopied += (name_len + 1); -+ } else { -+ filled = 1; -+ } -+ pos += size; -+ if (pos < xb_size - sizeof(int)) -+ memcpy(&size, xb + pos, sizeof(int)); -+ else -+ size = 0; -+ } -+ return ncopied; -+} -+ -+int nval_hasvalues(const char *xb, int xb_size) -+{ -+ return nval_used(xb, xb_size) > 0; -+} -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_nameval.h linux-2.6.36/fs/yaffs2/yaffs_nameval.h ---- linux-2.6.36.orig/fs/yaffs2/yaffs_nameval.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_nameval.h 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,28 @@ -+/* -+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU Lesser General Public License version 2.1 as -+ * published by the Free Software Foundation. -+ * -+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. -+ */ -+ -+#ifndef __NAMEVAL_H__ -+#define __NAMEVAL_H__ -+ -+#include "yportenv.h" -+ -+int nval_del(char *xb, int xb_size, const YCHAR * name); -+int nval_set(char *xb, int xb_size, const YCHAR * name, const char *buf, -+ int bsize, int flags); -+int nval_get(const char *xb, int xb_size, const YCHAR * name, char *buf, -+ int bsize); -+int nval_list(const char *xb, int xb_size, char *buf, int bsize); -+int nval_hasvalues(const char *xb, int xb_size); -+#endif -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_nand.c linux-2.6.36/fs/yaffs2/yaffs_nand.c ---- linux-2.6.36.orig/fs/yaffs2/yaffs_nand.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_nand.c 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,128 @@ -+/* -+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include "yaffs_nand.h" -+#include "yaffs_tagscompat.h" -+#include "yaffs_tagsvalidity.h" -+ -+#include "yaffs_getblockinfo.h" -+ -+int yaffs_rd_chunk_tags_nand(struct yaffs_dev *dev, int nand_chunk, -+ u8 * buffer, struct yaffs_ext_tags *tags) -+{ -+ int result; -+ struct yaffs_ext_tags local_tags; -+ -+ int realigned_chunk = nand_chunk - dev->chunk_offset; -+ -+ dev->n_page_reads++; -+ -+ /* If there are no tags provided, use local tags to get prioritised gc working */ -+ if (!tags) -+ tags = &local_tags; -+ -+ if (dev->param.read_chunk_tags_fn) -+ result = -+ dev->param.read_chunk_tags_fn(dev, realigned_chunk, buffer, -+ tags); -+ else -+ result = yaffs_tags_compat_rd(dev, -+ realigned_chunk, buffer, tags); -+ if (tags && tags->ecc_result > YAFFS_ECC_RESULT_NO_ERROR) { -+ -+ struct yaffs_block_info *bi; -+ bi = yaffs_get_block_info(dev, -+ nand_chunk / -+ dev->param.chunks_per_block); -+ yaffs_handle_chunk_error(dev, bi); -+ } -+ -+ return result; -+} -+ -+int yaffs_wr_chunk_tags_nand(struct yaffs_dev *dev, -+ int nand_chunk, -+ const u8 * buffer, struct yaffs_ext_tags *tags) -+{ -+ -+ dev->n_page_writes++; -+ -+ nand_chunk -= dev->chunk_offset; -+ -+ if (tags) { -+ tags->seq_number = dev->seq_number; -+ tags->chunk_used = 1; -+ if (!yaffs_validate_tags(tags)) { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR("Writing uninitialised tags" TENDSTR))); -+ YBUG(); -+ } -+ T(YAFFS_TRACE_WRITE, -+ (TSTR("Writing chunk %d tags %d %d" TENDSTR), nand_chunk, -+ tags->obj_id, tags->chunk_id)); -+ } else { -+ T(YAFFS_TRACE_ERROR, (TSTR("Writing with no tags" TENDSTR))); -+ YBUG(); -+ } -+ -+ if (dev->param.write_chunk_tags_fn) -+ return dev->param.write_chunk_tags_fn(dev, nand_chunk, buffer, -+ tags); -+ else -+ return yaffs_tags_compat_wr(dev, nand_chunk, buffer, tags); -+} -+ -+int yaffs_mark_bad(struct yaffs_dev *dev, int block_no) -+{ -+ block_no -= dev->block_offset; -+ -+ if (dev->param.bad_block_fn) -+ return dev->param.bad_block_fn(dev, block_no); -+ else -+ return yaffs_tags_compat_mark_bad(dev, block_no); -+} -+ -+int yaffs_query_init_block_state(struct yaffs_dev *dev, -+ int block_no, -+ enum yaffs_block_state *state, -+ u32 * seq_number) -+{ -+ block_no -= dev->block_offset; -+ -+ if (dev->param.query_block_fn) -+ return dev->param.query_block_fn(dev, block_no, state, -+ seq_number); -+ else -+ return yaffs_tags_compat_query_block(dev, block_no, -+ state, seq_number); -+} -+ -+int yaffs_erase_block(struct yaffs_dev *dev, int flash_block) -+{ -+ int result; -+ -+ flash_block -= dev->block_offset; -+ -+ dev->n_erasures++; -+ -+ result = dev->param.erase_fn(dev, flash_block); -+ -+ return result; -+} -+ -+int yaffs_init_nand(struct yaffs_dev *dev) -+{ -+ if (dev->param.initialise_flash_fn) -+ return dev->param.initialise_flash_fn(dev); -+ return YAFFS_OK; -+} -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_nand.h linux-2.6.36/fs/yaffs2/yaffs_nand.h ---- linux-2.6.36.orig/fs/yaffs2/yaffs_nand.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_nand.h 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,38 @@ -+/* -+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU Lesser General Public License version 2.1 as -+ * published by the Free Software Foundation. -+ * -+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. -+ */ -+ -+#ifndef __YAFFS_NAND_H__ -+#define __YAFFS_NAND_H__ -+#include "yaffs_guts.h" -+ -+int yaffs_rd_chunk_tags_nand(struct yaffs_dev *dev, int nand_chunk, -+ u8 * buffer, struct yaffs_ext_tags *tags); -+ -+int yaffs_wr_chunk_tags_nand(struct yaffs_dev *dev, -+ int nand_chunk, -+ const u8 * buffer, struct yaffs_ext_tags *tags); -+ -+int yaffs_mark_bad(struct yaffs_dev *dev, int block_no); -+ -+int yaffs_query_init_block_state(struct yaffs_dev *dev, -+ int block_no, -+ enum yaffs_block_state *state, -+ unsigned *seq_number); -+ -+int yaffs_erase_block(struct yaffs_dev *dev, int flash_block); -+ -+int yaffs_init_nand(struct yaffs_dev *dev); -+ -+#endif -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_packedtags1.c linux-2.6.36/fs/yaffs2/yaffs_packedtags1.c ---- linux-2.6.36.orig/fs/yaffs2/yaffs_packedtags1.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_packedtags1.c 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,53 @@ -+/* -+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include "yaffs_packedtags1.h" -+#include "yportenv.h" -+ -+void yaffs_pack_tags1(struct yaffs_packed_tags1 *pt, -+ const struct yaffs_ext_tags *t) -+{ -+ pt->chunk_id = t->chunk_id; -+ pt->serial_number = t->serial_number; -+ pt->n_bytes = t->n_bytes; -+ pt->obj_id = t->obj_id; -+ pt->ecc = 0; -+ pt->deleted = (t->is_deleted) ? 0 : 1; -+ pt->unused_stuff = 0; -+ pt->should_be_ff = 0xFFFFFFFF; -+ -+} -+ -+void yaffs_unpack_tags1(struct yaffs_ext_tags *t, -+ const struct yaffs_packed_tags1 *pt) -+{ -+ static const u8 all_ff[] = -+ { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -+ 0xff -+ }; -+ -+ if (memcmp(all_ff, pt, sizeof(struct yaffs_packed_tags1))) { -+ t->block_bad = 0; -+ if (pt->should_be_ff != 0xFFFFFFFF) -+ t->block_bad = 1; -+ t->chunk_used = 1; -+ t->obj_id = pt->obj_id; -+ t->chunk_id = pt->chunk_id; -+ t->n_bytes = pt->n_bytes; -+ t->ecc_result = YAFFS_ECC_RESULT_NO_ERROR; -+ t->is_deleted = (pt->deleted) ? 0 : 1; -+ t->serial_number = pt->serial_number; -+ } else { -+ memset(t, 0, sizeof(struct yaffs_ext_tags)); -+ } -+} -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_packedtags1.h linux-2.6.36/fs/yaffs2/yaffs_packedtags1.h ---- linux-2.6.36.orig/fs/yaffs2/yaffs_packedtags1.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_packedtags1.h 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,39 @@ -+/* -+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU Lesser General Public License version 2.1 as -+ * published by the Free Software Foundation. -+ * -+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. -+ */ -+ -+/* This is used to pack YAFFS1 tags, not YAFFS2 tags. */ -+ -+#ifndef __YAFFS_PACKEDTAGS1_H__ -+#define __YAFFS_PACKEDTAGS1_H__ -+ -+#include "yaffs_guts.h" -+ -+struct yaffs_packed_tags1 { -+ unsigned chunk_id:20; -+ unsigned serial_number:2; -+ unsigned n_bytes:10; -+ unsigned obj_id:18; -+ unsigned ecc:12; -+ unsigned deleted:1; -+ unsigned unused_stuff:1; -+ unsigned should_be_ff; -+ -+}; -+ -+void yaffs_pack_tags1(struct yaffs_packed_tags1 *pt, -+ const struct yaffs_ext_tags *t); -+void yaffs_unpack_tags1(struct yaffs_ext_tags *t, -+ const struct yaffs_packed_tags1 *pt); -+#endif -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_packedtags2.c linux-2.6.36/fs/yaffs2/yaffs_packedtags2.c ---- linux-2.6.36.orig/fs/yaffs2/yaffs_packedtags2.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_packedtags2.c 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,197 @@ -+/* -+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include "yaffs_packedtags2.h" -+#include "yportenv.h" -+#include "yaffs_trace.h" -+#include "yaffs_tagsvalidity.h" -+ -+/* This code packs a set of extended tags into a binary structure for -+ * NAND storage -+ */ -+ -+/* Some of the information is "extra" struff which can be packed in to -+ * speed scanning -+ * This is defined by having the EXTRA_HEADER_INFO_FLAG set. -+ */ -+ -+/* Extra flags applied to chunk_id */ -+ -+#define EXTRA_HEADER_INFO_FLAG 0x80000000 -+#define EXTRA_SHRINK_FLAG 0x40000000 -+#define EXTRA_SHADOWS_FLAG 0x20000000 -+#define EXTRA_SPARE_FLAGS 0x10000000 -+ -+#define ALL_EXTRA_FLAGS 0xF0000000 -+ -+/* Also, the top 4 bits of the object Id are set to the object type. */ -+#define EXTRA_OBJECT_TYPE_SHIFT (28) -+#define EXTRA_OBJECT_TYPE_MASK ((0x0F) << EXTRA_OBJECT_TYPE_SHIFT) -+ -+static void yaffs_dump_packed_tags2_tags_only(const struct -+ yaffs_packed_tags2_tags_only *ptt) -+{ -+ T(YAFFS_TRACE_MTD, -+ (TSTR("packed tags obj %d chunk %d byte %d seq %d" TENDSTR), -+ ptt->obj_id, ptt->chunk_id, ptt->n_bytes, ptt->seq_number)); -+} -+ -+static void yaffs_dump_packed_tags2(const struct yaffs_packed_tags2 *pt) -+{ -+ yaffs_dump_packed_tags2_tags_only(&pt->t); -+} -+ -+static void yaffs_dump_tags2(const struct yaffs_ext_tags *t) -+{ -+ T(YAFFS_TRACE_MTD, -+ (TSTR -+ ("ext.tags eccres %d blkbad %d chused %d obj %d chunk%d byte %d del %d ser %d seq %d" -+ TENDSTR), t->ecc_result, t->block_bad, t->chunk_used, t->obj_id, -+ t->chunk_id, t->n_bytes, t->is_deleted, t->serial_number, -+ t->seq_number)); -+ -+} -+ -+void yaffs_pack_tags2_tags_only(struct yaffs_packed_tags2_tags_only *ptt, -+ const struct yaffs_ext_tags *t) -+{ -+ ptt->chunk_id = t->chunk_id; -+ ptt->seq_number = t->seq_number; -+ ptt->n_bytes = t->n_bytes; -+ ptt->obj_id = t->obj_id; -+ -+ if (t->chunk_id == 0 && t->extra_available) { -+ /* Store the extra header info instead */ -+ /* We save the parent object in the chunk_id */ -+ ptt->chunk_id = EXTRA_HEADER_INFO_FLAG | t->extra_parent_id; -+ if (t->extra_is_shrink) -+ ptt->chunk_id |= EXTRA_SHRINK_FLAG; -+ if (t->extra_shadows) -+ ptt->chunk_id |= EXTRA_SHADOWS_FLAG; -+ -+ ptt->obj_id &= ~EXTRA_OBJECT_TYPE_MASK; -+ ptt->obj_id |= (t->extra_obj_type << EXTRA_OBJECT_TYPE_SHIFT); -+ -+ if (t->extra_obj_type == YAFFS_OBJECT_TYPE_HARDLINK) -+ ptt->n_bytes = t->extra_equiv_id; -+ else if (t->extra_obj_type == YAFFS_OBJECT_TYPE_FILE) -+ ptt->n_bytes = t->extra_length; -+ else -+ ptt->n_bytes = 0; -+ } -+ -+ yaffs_dump_packed_tags2_tags_only(ptt); -+ yaffs_dump_tags2(t); -+} -+ -+void yaffs_pack_tags2(struct yaffs_packed_tags2 *pt, -+ const struct yaffs_ext_tags *t, int tags_ecc) -+{ -+ yaffs_pack_tags2_tags_only(&pt->t, t); -+ -+ if (tags_ecc) -+ yaffs_ecc_calc_other((unsigned char *)&pt->t, -+ sizeof(struct -+ yaffs_packed_tags2_tags_only), -+ &pt->ecc); -+} -+ -+void yaffs_unpack_tags2_tags_only(struct yaffs_ext_tags *t, -+ struct yaffs_packed_tags2_tags_only *ptt) -+{ -+ -+ memset(t, 0, sizeof(struct yaffs_ext_tags)); -+ -+ yaffs_init_tags(t); -+ -+ if (ptt->seq_number != 0xFFFFFFFF) { -+ t->block_bad = 0; -+ t->chunk_used = 1; -+ t->obj_id = ptt->obj_id; -+ t->chunk_id = ptt->chunk_id; -+ t->n_bytes = ptt->n_bytes; -+ t->is_deleted = 0; -+ t->serial_number = 0; -+ t->seq_number = ptt->seq_number; -+ -+ /* Do extra header info stuff */ -+ -+ if (ptt->chunk_id & EXTRA_HEADER_INFO_FLAG) { -+ t->chunk_id = 0; -+ t->n_bytes = 0; -+ -+ t->extra_available = 1; -+ t->extra_parent_id = -+ ptt->chunk_id & (~(ALL_EXTRA_FLAGS)); -+ t->extra_is_shrink = -+ (ptt->chunk_id & EXTRA_SHRINK_FLAG) ? 1 : 0; -+ t->extra_shadows = -+ (ptt->chunk_id & EXTRA_SHADOWS_FLAG) ? 1 : 0; -+ t->extra_obj_type = -+ ptt->obj_id >> EXTRA_OBJECT_TYPE_SHIFT; -+ t->obj_id &= ~EXTRA_OBJECT_TYPE_MASK; -+ -+ if (t->extra_obj_type == YAFFS_OBJECT_TYPE_HARDLINK) -+ t->extra_equiv_id = ptt->n_bytes; -+ else -+ t->extra_length = ptt->n_bytes; -+ } -+ } -+ -+ yaffs_dump_packed_tags2_tags_only(ptt); -+ yaffs_dump_tags2(t); -+ -+} -+ -+void yaffs_unpack_tags2(struct yaffs_ext_tags *t, struct yaffs_packed_tags2 *pt, -+ int tags_ecc) -+{ -+ -+ enum yaffs_ecc_result ecc_result = YAFFS_ECC_RESULT_NO_ERROR; -+ -+ if (pt->t.seq_number != 0xFFFFFFFF && tags_ecc) { -+ /* Chunk is in use and we need to do ECC */ -+ -+ struct yaffs_ecc_other ecc; -+ int result; -+ yaffs_ecc_calc_other((unsigned char *)&pt->t, -+ sizeof(struct -+ yaffs_packed_tags2_tags_only), -+ &ecc); -+ result = -+ yaffs_ecc_correct_other((unsigned char *)&pt->t, -+ sizeof(struct -+ yaffs_packed_tags2_tags_only), -+ &pt->ecc, &ecc); -+ switch (result) { -+ case 0: -+ ecc_result = YAFFS_ECC_RESULT_NO_ERROR; -+ break; -+ case 1: -+ ecc_result = YAFFS_ECC_RESULT_FIXED; -+ break; -+ case -1: -+ ecc_result = YAFFS_ECC_RESULT_UNFIXED; -+ break; -+ default: -+ ecc_result = YAFFS_ECC_RESULT_UNKNOWN; -+ } -+ } -+ -+ yaffs_unpack_tags2_tags_only(t, &pt->t); -+ -+ t->ecc_result = ecc_result; -+ -+ yaffs_dump_packed_tags2(pt); -+ yaffs_dump_tags2(t); -+} -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_packedtags2.h linux-2.6.36/fs/yaffs2/yaffs_packedtags2.h ---- linux-2.6.36.orig/fs/yaffs2/yaffs_packedtags2.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_packedtags2.h 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,47 @@ -+/* -+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU Lesser General Public License version 2.1 as -+ * published by the Free Software Foundation. -+ * -+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. -+ */ -+ -+/* This is used to pack YAFFS2 tags, not YAFFS1tags. */ -+ -+#ifndef __YAFFS_PACKEDTAGS2_H__ -+#define __YAFFS_PACKEDTAGS2_H__ -+ -+#include "yaffs_guts.h" -+#include "yaffs_ecc.h" -+ -+struct yaffs_packed_tags2_tags_only { -+ unsigned seq_number; -+ unsigned obj_id; -+ unsigned chunk_id; -+ unsigned n_bytes; -+}; -+ -+struct yaffs_packed_tags2 { -+ struct yaffs_packed_tags2_tags_only t; -+ struct yaffs_ecc_other ecc; -+}; -+ -+/* Full packed tags with ECC, used for oob tags */ -+void yaffs_pack_tags2(struct yaffs_packed_tags2 *pt, -+ const struct yaffs_ext_tags *t, int tags_ecc); -+void yaffs_unpack_tags2(struct yaffs_ext_tags *t, struct yaffs_packed_tags2 *pt, -+ int tags_ecc); -+ -+/* Only the tags part (no ECC for use with inband tags */ -+void yaffs_pack_tags2_tags_only(struct yaffs_packed_tags2_tags_only *pt, -+ const struct yaffs_ext_tags *t); -+void yaffs_unpack_tags2_tags_only(struct yaffs_ext_tags *t, -+ struct yaffs_packed_tags2_tags_only *pt); -+#endif -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_tagscompat.c linux-2.6.36/fs/yaffs2/yaffs_tagscompat.c ---- linux-2.6.36.orig/fs/yaffs2/yaffs_tagscompat.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_tagscompat.c 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,454 @@ -+/* -+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include "yaffs_guts.h" -+#include "yaffs_tagscompat.h" -+#include "yaffs_ecc.h" -+#include "yaffs_getblockinfo.h" -+#include "yaffs_trace.h" -+ -+static void yaffs_handle_rd_data_error(struct yaffs_dev *dev, int nand_chunk); -+ -+static const char yaffs_count_bits_table[256] = { -+ 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4, -+ 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, -+ 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, -+ 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, -+ 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, -+ 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, -+ 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, -+ 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, -+ 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, -+ 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, -+ 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, -+ 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, -+ 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, -+ 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, -+ 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, -+ 4, 5, 5, 6, 5, 6, 6, 7, 5, 6, 6, 7, 6, 7, 7, 8 -+}; -+ -+int yaffs_count_bits(u8 x) -+{ -+ int ret_val; -+ ret_val = yaffs_count_bits_table[x]; -+ return ret_val; -+} -+ -+/********** Tags ECC calculations *********/ -+ -+void yaffs_calc_ecc(const u8 * data, struct yaffs_spare *spare) -+{ -+ yaffs_ecc_cacl(data, spare->ecc1); -+ yaffs_ecc_cacl(&data[256], spare->ecc2); -+} -+ -+void yaffs_calc_tags_ecc(struct yaffs_tags *tags) -+{ -+ /* Calculate an ecc */ -+ -+ unsigned char *b = ((union yaffs_tags_union *)tags)->as_bytes; -+ unsigned i, j; -+ unsigned ecc = 0; -+ unsigned bit = 0; -+ -+ tags->ecc = 0; -+ -+ for (i = 0; i < 8; i++) { -+ for (j = 1; j & 0xff; j <<= 1) { -+ bit++; -+ if (b[i] & j) -+ ecc ^= bit; -+ } -+ } -+ -+ tags->ecc = ecc; -+ -+} -+ -+int yaffs_check_tags_ecc(struct yaffs_tags *tags) -+{ -+ unsigned ecc = tags->ecc; -+ -+ yaffs_calc_tags_ecc(tags); -+ -+ ecc ^= tags->ecc; -+ -+ if (ecc && ecc <= 64) { -+ /* TODO: Handle the failure better. Retire? */ -+ unsigned char *b = ((union yaffs_tags_union *)tags)->as_bytes; -+ -+ ecc--; -+ -+ b[ecc / 8] ^= (1 << (ecc & 7)); -+ -+ /* Now recvalc the ecc */ -+ yaffs_calc_tags_ecc(tags); -+ -+ return 1; /* recovered error */ -+ } else if (ecc) { -+ /* Wierd ecc failure value */ -+ /* TODO Need to do somethiong here */ -+ return -1; /* unrecovered error */ -+ } -+ -+ return 0; -+} -+ -+/********** Tags **********/ -+ -+static void yaffs_load_tags_to_spare(struct yaffs_spare *spare_ptr, -+ struct yaffs_tags *tags_ptr) -+{ -+ union yaffs_tags_union *tu = (union yaffs_tags_union *)tags_ptr; -+ -+ yaffs_calc_tags_ecc(tags_ptr); -+ -+ spare_ptr->tb0 = tu->as_bytes[0]; -+ spare_ptr->tb1 = tu->as_bytes[1]; -+ spare_ptr->tb2 = tu->as_bytes[2]; -+ spare_ptr->tb3 = tu->as_bytes[3]; -+ spare_ptr->tb4 = tu->as_bytes[4]; -+ spare_ptr->tb5 = tu->as_bytes[5]; -+ spare_ptr->tb6 = tu->as_bytes[6]; -+ spare_ptr->tb7 = tu->as_bytes[7]; -+} -+ -+static void yaffs_get_tags_from_spare(struct yaffs_dev *dev, -+ struct yaffs_spare *spare_ptr, -+ struct yaffs_tags *tags_ptr) -+{ -+ union yaffs_tags_union *tu = (union yaffs_tags_union *)tags_ptr; -+ int result; -+ -+ tu->as_bytes[0] = spare_ptr->tb0; -+ tu->as_bytes[1] = spare_ptr->tb1; -+ tu->as_bytes[2] = spare_ptr->tb2; -+ tu->as_bytes[3] = spare_ptr->tb3; -+ tu->as_bytes[4] = spare_ptr->tb4; -+ tu->as_bytes[5] = spare_ptr->tb5; -+ tu->as_bytes[6] = spare_ptr->tb6; -+ tu->as_bytes[7] = spare_ptr->tb7; -+ -+ result = yaffs_check_tags_ecc(tags_ptr); -+ if (result > 0) -+ dev->n_tags_ecc_fixed++; -+ else if (result < 0) -+ dev->n_tags_ecc_unfixed++; -+} -+ -+static void yaffs_spare_init(struct yaffs_spare *spare) -+{ -+ memset(spare, 0xFF, sizeof(struct yaffs_spare)); -+} -+ -+static int yaffs_wr_nand(struct yaffs_dev *dev, -+ int nand_chunk, const u8 * data, -+ struct yaffs_spare *spare) -+{ -+ if (nand_chunk < dev->param.start_block * dev->param.chunks_per_block) { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR("**>> yaffs chunk %d is not valid" TENDSTR), -+ nand_chunk)); -+ return YAFFS_FAIL; -+ } -+ -+ return dev->param.write_chunk_fn(dev, nand_chunk, data, spare); -+} -+ -+static int yaffs_rd_chunk_nand(struct yaffs_dev *dev, -+ int nand_chunk, -+ u8 * data, -+ struct yaffs_spare *spare, -+ enum yaffs_ecc_result *ecc_result, -+ int correct_errors) -+{ -+ int ret_val; -+ struct yaffs_spare local_spare; -+ -+ if (!spare && data) { -+ /* If we don't have a real spare, then we use a local one. */ -+ /* Need this for the calculation of the ecc */ -+ spare = &local_spare; -+ } -+ -+ if (!dev->param.use_nand_ecc) { -+ ret_val = -+ dev->param.read_chunk_fn(dev, nand_chunk, data, spare); -+ if (data && correct_errors) { -+ /* Do ECC correction */ -+ /* Todo handle any errors */ -+ int ecc_result1, ecc_result2; -+ u8 calc_ecc[3]; -+ -+ yaffs_ecc_cacl(data, calc_ecc); -+ ecc_result1 = -+ yaffs_ecc_correct(data, spare->ecc1, calc_ecc); -+ yaffs_ecc_cacl(&data[256], calc_ecc); -+ ecc_result2 = -+ yaffs_ecc_correct(&data[256], spare->ecc2, -+ calc_ecc); -+ -+ if (ecc_result1 > 0) { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR -+ ("**>>yaffs ecc error fix performed on chunk %d:0" -+ TENDSTR), nand_chunk)); -+ dev->n_ecc_fixed++; -+ } else if (ecc_result1 < 0) { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR -+ ("**>>yaffs ecc error unfixed on chunk %d:0" -+ TENDSTR), nand_chunk)); -+ dev->n_ecc_unfixed++; -+ } -+ -+ if (ecc_result2 > 0) { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR -+ ("**>>yaffs ecc error fix performed on chunk %d:1" -+ TENDSTR), nand_chunk)); -+ dev->n_ecc_fixed++; -+ } else if (ecc_result2 < 0) { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR -+ ("**>>yaffs ecc error unfixed on chunk %d:1" -+ TENDSTR), nand_chunk)); -+ dev->n_ecc_unfixed++; -+ } -+ -+ if (ecc_result1 || ecc_result2) { -+ /* We had a data problem on this page */ -+ yaffs_handle_rd_data_error(dev, nand_chunk); -+ } -+ -+ if (ecc_result1 < 0 || ecc_result2 < 0) -+ *ecc_result = YAFFS_ECC_RESULT_UNFIXED; -+ else if (ecc_result1 > 0 || ecc_result2 > 0) -+ *ecc_result = YAFFS_ECC_RESULT_FIXED; -+ else -+ *ecc_result = YAFFS_ECC_RESULT_NO_ERROR; -+ } -+ } else { -+ /* Must allocate enough memory for spare+2*sizeof(int) */ -+ /* for ecc results from device. */ -+ struct yaffs_nand_spare nspare; -+ -+ memset(&nspare, 0, sizeof(nspare)); -+ -+ ret_val = dev->param.read_chunk_fn(dev, nand_chunk, data, -+ (struct yaffs_spare *) -+ &nspare); -+ memcpy(spare, &nspare, sizeof(struct yaffs_spare)); -+ if (data && correct_errors) { -+ if (nspare.eccres1 > 0) { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR -+ ("**>>mtd ecc error fix performed on chunk %d:0" -+ TENDSTR), nand_chunk)); -+ } else if (nspare.eccres1 < 0) { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR -+ ("**>>mtd ecc error unfixed on chunk %d:0" -+ TENDSTR), nand_chunk)); -+ } -+ -+ if (nspare.eccres2 > 0) { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR -+ ("**>>mtd ecc error fix performed on chunk %d:1" -+ TENDSTR), nand_chunk)); -+ } else if (nspare.eccres2 < 0) { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR -+ ("**>>mtd ecc error unfixed on chunk %d:1" -+ TENDSTR), nand_chunk)); -+ } -+ -+ if (nspare.eccres1 || nspare.eccres2) { -+ /* We had a data problem on this page */ -+ yaffs_handle_rd_data_error(dev, nand_chunk); -+ } -+ -+ if (nspare.eccres1 < 0 || nspare.eccres2 < 0) -+ *ecc_result = YAFFS_ECC_RESULT_UNFIXED; -+ else if (nspare.eccres1 > 0 || nspare.eccres2 > 0) -+ *ecc_result = YAFFS_ECC_RESULT_FIXED; -+ else -+ *ecc_result = YAFFS_ECC_RESULT_NO_ERROR; -+ -+ } -+ } -+ return ret_val; -+} -+ -+/* -+ * Functions for robustisizing -+ */ -+ -+static void yaffs_handle_rd_data_error(struct yaffs_dev *dev, int nand_chunk) -+{ -+ int flash_block = nand_chunk / dev->param.chunks_per_block; -+ -+ /* Mark the block for retirement */ -+ yaffs_get_block_info(dev, -+ flash_block + dev->block_offset)->needs_retiring = -+ 1; -+ T(YAFFS_TRACE_ERROR | YAFFS_TRACE_BAD_BLOCKS, -+ (TSTR("**>>Block %d marked for retirement" TENDSTR), flash_block)); -+ -+ /* TODO: -+ * Just do a garbage collection on the affected block -+ * then retire the block -+ * NB recursion -+ */ -+} -+ -+int yaffs_tags_compat_wr(struct yaffs_dev *dev, -+ int nand_chunk, -+ const u8 * data, const struct yaffs_ext_tags *ext_tags) -+{ -+ struct yaffs_spare spare; -+ struct yaffs_tags tags; -+ -+ yaffs_spare_init(&spare); -+ -+ if (ext_tags->is_deleted) -+ spare.page_status = 0; -+ else { -+ tags.obj_id = ext_tags->obj_id; -+ tags.chunk_id = ext_tags->chunk_id; -+ -+ tags.n_bytes_lsb = ext_tags->n_bytes & 0x3ff; -+ -+ if (dev->data_bytes_per_chunk >= 1024) -+ tags.n_bytes_msb = (ext_tags->n_bytes >> 10) & 3; -+ else -+ tags.n_bytes_msb = 3; -+ -+ tags.serial_number = ext_tags->serial_number; -+ -+ if (!dev->param.use_nand_ecc && data) -+ yaffs_calc_ecc(data, &spare); -+ -+ yaffs_load_tags_to_spare(&spare, &tags); -+ -+ } -+ -+ return yaffs_wr_nand(dev, nand_chunk, data, &spare); -+} -+ -+int yaffs_tags_compat_rd(struct yaffs_dev *dev, -+ int nand_chunk, -+ u8 * data, struct yaffs_ext_tags *ext_tags) -+{ -+ -+ struct yaffs_spare spare; -+ struct yaffs_tags tags; -+ enum yaffs_ecc_result ecc_result = YAFFS_ECC_RESULT_UNKNOWN; -+ -+ static struct yaffs_spare spare_ff; -+ static int init; -+ -+ if (!init) { -+ memset(&spare_ff, 0xFF, sizeof(spare_ff)); -+ init = 1; -+ } -+ -+ if (yaffs_rd_chunk_nand(dev, nand_chunk, data, &spare, &ecc_result, 1)) { -+ /* ext_tags may be NULL */ -+ if (ext_tags) { -+ -+ int deleted = -+ (yaffs_count_bits(spare.page_status) < 7) ? 1 : 0; -+ -+ ext_tags->is_deleted = deleted; -+ ext_tags->ecc_result = ecc_result; -+ ext_tags->block_bad = 0; /* We're reading it */ -+ /* therefore it is not a bad block */ -+ ext_tags->chunk_used = -+ (memcmp(&spare_ff, &spare, sizeof(spare_ff)) != -+ 0) ? 1 : 0; -+ -+ if (ext_tags->chunk_used) { -+ yaffs_get_tags_from_spare(dev, &spare, &tags); -+ -+ ext_tags->obj_id = tags.obj_id; -+ ext_tags->chunk_id = tags.chunk_id; -+ ext_tags->n_bytes = tags.n_bytes_lsb; -+ -+ if (dev->data_bytes_per_chunk >= 1024) -+ ext_tags->n_bytes |= -+ (((unsigned)tags. -+ n_bytes_msb) << 10); -+ -+ ext_tags->serial_number = tags.serial_number; -+ } -+ } -+ -+ return YAFFS_OK; -+ } else { -+ return YAFFS_FAIL; -+ } -+} -+ -+int yaffs_tags_compat_mark_bad(struct yaffs_dev *dev, int flash_block) -+{ -+ -+ struct yaffs_spare spare; -+ -+ memset(&spare, 0xff, sizeof(struct yaffs_spare)); -+ -+ spare.block_status = 'Y'; -+ -+ yaffs_wr_nand(dev, flash_block * dev->param.chunks_per_block, NULL, -+ &spare); -+ yaffs_wr_nand(dev, flash_block * dev->param.chunks_per_block + 1, -+ NULL, &spare); -+ -+ return YAFFS_OK; -+ -+} -+ -+int yaffs_tags_compat_query_block(struct yaffs_dev *dev, -+ int block_no, -+ enum yaffs_block_state *state, -+ u32 * seq_number) -+{ -+ -+ struct yaffs_spare spare0, spare1; -+ static struct yaffs_spare spare_ff; -+ static int init; -+ enum yaffs_ecc_result dummy; -+ -+ if (!init) { -+ memset(&spare_ff, 0xFF, sizeof(spare_ff)); -+ init = 1; -+ } -+ -+ *seq_number = 0; -+ -+ yaffs_rd_chunk_nand(dev, block_no * dev->param.chunks_per_block, NULL, -+ &spare0, &dummy, 1); -+ yaffs_rd_chunk_nand(dev, block_no * dev->param.chunks_per_block + 1, -+ NULL, &spare1, &dummy, 1); -+ -+ if (yaffs_count_bits(spare0.block_status & spare1.block_status) < 7) -+ *state = YAFFS_BLOCK_STATE_DEAD; -+ else if (memcmp(&spare_ff, &spare0, sizeof(spare_ff)) == 0) -+ *state = YAFFS_BLOCK_STATE_EMPTY; -+ else -+ *state = YAFFS_BLOCK_STATE_NEEDS_SCANNING; -+ -+ return YAFFS_OK; -+} -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_tagscompat.h linux-2.6.36/fs/yaffs2/yaffs_tagscompat.h ---- linux-2.6.36.orig/fs/yaffs2/yaffs_tagscompat.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_tagscompat.h 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,36 @@ -+/* -+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU Lesser General Public License version 2.1 as -+ * published by the Free Software Foundation. -+ * -+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. -+ */ -+ -+#ifndef __YAFFS_TAGSCOMPAT_H__ -+#define __YAFFS_TAGSCOMPAT_H__ -+ -+#include "yaffs_guts.h" -+int yaffs_tags_compat_wr(struct yaffs_dev *dev, -+ int nand_chunk, -+ const u8 * data, const struct yaffs_ext_tags *tags); -+int yaffs_tags_compat_rd(struct yaffs_dev *dev, -+ int nand_chunk, -+ u8 * data, struct yaffs_ext_tags *tags); -+int yaffs_tags_compat_mark_bad(struct yaffs_dev *dev, int block_no); -+int yaffs_tags_compat_query_block(struct yaffs_dev *dev, -+ int block_no, -+ enum yaffs_block_state *state, -+ u32 * seq_number); -+ -+void yaffs_calc_tags_ecc(struct yaffs_tags *tags); -+int yaffs_check_tags_ecc(struct yaffs_tags *tags); -+int yaffs_count_bits(u8 byte); -+ -+#endif -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_tagsvalidity.c linux-2.6.36/fs/yaffs2/yaffs_tagsvalidity.c ---- linux-2.6.36.orig/fs/yaffs2/yaffs_tagsvalidity.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_tagsvalidity.c 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,27 @@ -+/* -+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include "yaffs_tagsvalidity.h" -+ -+void yaffs_init_tags(struct yaffs_ext_tags *tags) -+{ -+ memset(tags, 0, sizeof(struct yaffs_ext_tags)); -+ tags->validity0 = 0xAAAAAAAA; -+ tags->validity1 = 0x55555555; -+} -+ -+int yaffs_validate_tags(struct yaffs_ext_tags *tags) -+{ -+ return (tags->validity0 == 0xAAAAAAAA && tags->validity1 == 0x55555555); -+ -+} -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_tagsvalidity.h linux-2.6.36/fs/yaffs2/yaffs_tagsvalidity.h ---- linux-2.6.36.orig/fs/yaffs2/yaffs_tagsvalidity.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_tagsvalidity.h 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,23 @@ -+/* -+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU Lesser General Public License version 2.1 as -+ * published by the Free Software Foundation. -+ * -+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. -+ */ -+ -+#ifndef __YAFFS_TAGS_VALIDITY_H__ -+#define __YAFFS_TAGS_VALIDITY_H__ -+ -+#include "yaffs_guts.h" -+ -+void yaffs_init_tags(struct yaffs_ext_tags *tags); -+int yaffs_validate_tags(struct yaffs_ext_tags *tags); -+#endif -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_trace.h linux-2.6.36/fs/yaffs2/yaffs_trace.h ---- linux-2.6.36.orig/fs/yaffs2/yaffs_trace.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_trace.h 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,59 @@ -+/* -+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU Lesser General Public License version 2.1 as -+ * published by the Free Software Foundation. -+ * -+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. -+ */ -+ -+#ifndef __YTRACE_H__ -+#define __YTRACE_H__ -+ -+extern unsigned int yaffs_trace_mask; -+extern unsigned int yaffs_wr_attempts; -+ -+/* -+ * Tracing flags. -+ * The flags masked in YAFFS_TRACE_ALWAYS are always traced. -+ */ -+ -+#define YAFFS_TRACE_OS 0x00000002 -+#define YAFFS_TRACE_ALLOCATE 0x00000004 -+#define YAFFS_TRACE_SCAN 0x00000008 -+#define YAFFS_TRACE_BAD_BLOCKS 0x00000010 -+#define YAFFS_TRACE_ERASE 0x00000020 -+#define YAFFS_TRACE_GC 0x00000040 -+#define YAFFS_TRACE_WRITE 0x00000080 -+#define YAFFS_TRACE_TRACING 0x00000100 -+#define YAFFS_TRACE_DELETION 0x00000200 -+#define YAFFS_TRACE_BUFFERS 0x00000400 -+#define YAFFS_TRACE_NANDACCESS 0x00000800 -+#define YAFFS_TRACE_GC_DETAIL 0x00001000 -+#define YAFFS_TRACE_SCAN_DEBUG 0x00002000 -+#define YAFFS_TRACE_MTD 0x00004000 -+#define YAFFS_TRACE_CHECKPOINT 0x00008000 -+ -+#define YAFFS_TRACE_VERIFY 0x00010000 -+#define YAFFS_TRACE_VERIFY_NAND 0x00020000 -+#define YAFFS_TRACE_VERIFY_FULL 0x00040000 -+#define YAFFS_TRACE_VERIFY_ALL 0x000F0000 -+ -+#define YAFFS_TRACE_SYNC 0x00100000 -+#define YAFFS_TRACE_BACKGROUND 0x00200000 -+#define YAFFS_TRACE_LOCK 0x00400000 -+#define YAFFS_TRACE_MOUNT 0x00800000 -+ -+#define YAFFS_TRACE_ERROR 0x40000000 -+#define YAFFS_TRACE_BUG 0x80000000 -+#define YAFFS_TRACE_ALWAYS 0xF0000000 -+ -+#define T(mask, p) do { if ((mask) & (yaffs_trace_mask | YAFFS_TRACE_ALWAYS)) TOUT(p); } while (0) -+ -+#endif -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_verify.c linux-2.6.36/fs/yaffs2/yaffs_verify.c ---- linux-2.6.36.orig/fs/yaffs2/yaffs_verify.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_verify.c 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,546 @@ -+/* -+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include "yaffs_verify.h" -+#include "yaffs_trace.h" -+#include "yaffs_bitmap.h" -+#include "yaffs_getblockinfo.h" -+#include "yaffs_nand.h" -+ -+int yaffs_skip_verification(struct yaffs_dev *dev) -+{ -+ dev = dev; -+ return !(yaffs_trace_mask & -+ (YAFFS_TRACE_VERIFY | YAFFS_TRACE_VERIFY_FULL)); -+} -+ -+static int yaffs_skip_full_verification(struct yaffs_dev *dev) -+{ -+ dev = dev; -+ return !(yaffs_trace_mask & (YAFFS_TRACE_VERIFY_FULL)); -+} -+ -+static int yaffs_skip_nand_verification(struct yaffs_dev *dev) -+{ -+ dev = dev; -+ return !(yaffs_trace_mask & (YAFFS_TRACE_VERIFY_NAND)); -+} -+ -+static const char *block_state_name[] = { -+ "Unknown", -+ "Needs scanning", -+ "Scanning", -+ "Empty", -+ "Allocating", -+ "Full", -+ "Dirty", -+ "Checkpoint", -+ "Collecting", -+ "Dead" -+}; -+ -+void yaffs_verify_blk(struct yaffs_dev *dev, struct yaffs_block_info *bi, int n) -+{ -+ int actually_used; -+ int in_use; -+ -+ if (yaffs_skip_verification(dev)) -+ return; -+ -+ /* Report illegal runtime states */ -+ if (bi->block_state >= YAFFS_NUMBER_OF_BLOCK_STATES) -+ T(YAFFS_TRACE_VERIFY, -+ (TSTR("Block %d has undefined state %d" TENDSTR), n, -+ bi->block_state)); -+ -+ switch (bi->block_state) { -+ case YAFFS_BLOCK_STATE_UNKNOWN: -+ case YAFFS_BLOCK_STATE_SCANNING: -+ case YAFFS_BLOCK_STATE_NEEDS_SCANNING: -+ T(YAFFS_TRACE_VERIFY, -+ (TSTR("Block %d has bad run-state %s" TENDSTR), n, -+ block_state_name[bi->block_state])); -+ } -+ -+ /* Check pages in use and soft deletions are legal */ -+ -+ actually_used = bi->pages_in_use - bi->soft_del_pages; -+ -+ if (bi->pages_in_use < 0 -+ || bi->pages_in_use > dev->param.chunks_per_block -+ || bi->soft_del_pages < 0 -+ || bi->soft_del_pages > dev->param.chunks_per_block -+ || actually_used < 0 || actually_used > dev->param.chunks_per_block) -+ T(YAFFS_TRACE_VERIFY, -+ (TSTR -+ ("Block %d has illegal values pages_in_used %d soft_del_pages %d" -+ TENDSTR), n, bi->pages_in_use, bi->soft_del_pages)); -+ -+ /* Check chunk bitmap legal */ -+ in_use = yaffs_count_chunk_bits(dev, n); -+ if (in_use != bi->pages_in_use) -+ T(YAFFS_TRACE_VERIFY, -+ (TSTR -+ ("Block %d has inconsistent values pages_in_use %d counted chunk bits %d" -+ TENDSTR), n, bi->pages_in_use, in_use)); -+ -+} -+ -+void yaffs_verify_collected_blk(struct yaffs_dev *dev, -+ struct yaffs_block_info *bi, int n) -+{ -+ yaffs_verify_blk(dev, bi, n); -+ -+ /* After collection the block should be in the erased state */ -+ -+ if (bi->block_state != YAFFS_BLOCK_STATE_COLLECTING && -+ bi->block_state != YAFFS_BLOCK_STATE_EMPTY) { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR -+ ("Block %d is in state %d after gc, should be erased" -+ TENDSTR), n, bi->block_state)); -+ } -+} -+ -+void yaffs_verify_blocks(struct yaffs_dev *dev) -+{ -+ int i; -+ int state_count[YAFFS_NUMBER_OF_BLOCK_STATES]; -+ int illegal_states = 0; -+ -+ if (yaffs_skip_verification(dev)) -+ return; -+ -+ memset(state_count, 0, sizeof(state_count)); -+ -+ for (i = dev->internal_start_block; i <= dev->internal_end_block; i++) { -+ struct yaffs_block_info *bi = yaffs_get_block_info(dev, i); -+ yaffs_verify_blk(dev, bi, i); -+ -+ if (bi->block_state < YAFFS_NUMBER_OF_BLOCK_STATES) -+ state_count[bi->block_state]++; -+ else -+ illegal_states++; -+ } -+ -+ T(YAFFS_TRACE_VERIFY, (TSTR("" TENDSTR))); -+ T(YAFFS_TRACE_VERIFY, (TSTR("Block summary" TENDSTR))); -+ -+ T(YAFFS_TRACE_VERIFY, -+ (TSTR("%d blocks have illegal states" TENDSTR), illegal_states)); -+ if (state_count[YAFFS_BLOCK_STATE_ALLOCATING] > 1) -+ T(YAFFS_TRACE_VERIFY, -+ (TSTR("Too many allocating blocks" TENDSTR))); -+ -+ for (i = 0; i < YAFFS_NUMBER_OF_BLOCK_STATES; i++) -+ T(YAFFS_TRACE_VERIFY, -+ (TSTR("%s %d blocks" TENDSTR), -+ block_state_name[i], state_count[i])); -+ -+ if (dev->blocks_in_checkpt != state_count[YAFFS_BLOCK_STATE_CHECKPOINT]) -+ T(YAFFS_TRACE_VERIFY, -+ (TSTR("Checkpoint block count wrong dev %d count %d" TENDSTR), -+ dev->blocks_in_checkpt, -+ state_count[YAFFS_BLOCK_STATE_CHECKPOINT])); -+ -+ if (dev->n_erased_blocks != state_count[YAFFS_BLOCK_STATE_EMPTY]) -+ T(YAFFS_TRACE_VERIFY, -+ (TSTR("Erased block count wrong dev %d count %d" TENDSTR), -+ dev->n_erased_blocks, state_count[YAFFS_BLOCK_STATE_EMPTY])); -+ -+ if (state_count[YAFFS_BLOCK_STATE_COLLECTING] > 1) -+ T(YAFFS_TRACE_VERIFY, -+ (TSTR("Too many collecting blocks %d (max is 1)" TENDSTR), -+ state_count[YAFFS_BLOCK_STATE_COLLECTING])); -+ -+ T(YAFFS_TRACE_VERIFY, (TSTR("" TENDSTR))); -+ -+} -+ -+/* -+ * Verify the object header. oh must be valid, but obj and tags may be NULL in which -+ * case those tests will not be performed. -+ */ -+void yaffs_verify_oh(struct yaffs_obj *obj, struct yaffs_obj_hdr *oh, -+ struct yaffs_ext_tags *tags, int parent_check) -+{ -+ if (obj && yaffs_skip_verification(obj->my_dev)) -+ return; -+ -+ if (!(tags && obj && oh)) { -+ T(YAFFS_TRACE_VERIFY, -+ (TSTR("Verifying object header tags %p obj %p oh %p" TENDSTR), -+ tags, obj, oh)); -+ return; -+ } -+ -+ if (oh->type <= YAFFS_OBJECT_TYPE_UNKNOWN || -+ oh->type > YAFFS_OBJECT_TYPE_MAX) -+ T(YAFFS_TRACE_VERIFY, -+ (TSTR("Obj %d header type is illegal value 0x%x" TENDSTR), -+ tags->obj_id, oh->type)); -+ -+ if (tags->obj_id != obj->obj_id) -+ T(YAFFS_TRACE_VERIFY, -+ (TSTR("Obj %d header mismatch obj_id %d" TENDSTR), -+ tags->obj_id, obj->obj_id)); -+ -+ /* -+ * Check that the object's parent ids match if parent_check requested. -+ * -+ * Tests do not apply to the root object. -+ */ -+ -+ if (parent_check && tags->obj_id > 1 && !obj->parent) -+ T(YAFFS_TRACE_VERIFY, -+ (TSTR -+ ("Obj %d header mismatch parent_id %d obj->parent is NULL" -+ TENDSTR), tags->obj_id, oh->parent_obj_id)); -+ -+ if (parent_check && obj->parent && -+ oh->parent_obj_id != obj->parent->obj_id && -+ (oh->parent_obj_id != YAFFS_OBJECTID_UNLINKED || -+ obj->parent->obj_id != YAFFS_OBJECTID_DELETED)) -+ T(YAFFS_TRACE_VERIFY, -+ (TSTR -+ ("Obj %d header mismatch parent_id %d parent_obj_id %d" -+ TENDSTR), tags->obj_id, oh->parent_obj_id, -+ obj->parent->obj_id)); -+ -+ if (tags->obj_id > 1 && oh->name[0] == 0) /* Null name */ -+ T(YAFFS_TRACE_VERIFY, -+ (TSTR("Obj %d header name is NULL" TENDSTR), obj->obj_id)); -+ -+ if (tags->obj_id > 1 && ((u8) (oh->name[0])) == 0xff) /* Trashed name */ -+ T(YAFFS_TRACE_VERIFY, -+ (TSTR("Obj %d header name is 0xFF" TENDSTR), obj->obj_id)); -+} -+ -+void yaffs_verify_file(struct yaffs_obj *obj) -+{ -+ int required_depth; -+ int actual_depth; -+ u32 last_chunk; -+ u32 x; -+ u32 i; -+ struct yaffs_dev *dev; -+ struct yaffs_ext_tags tags; -+ struct yaffs_tnode *tn; -+ u32 obj_id; -+ -+ if (!obj) -+ return; -+ -+ if (yaffs_skip_verification(obj->my_dev)) -+ return; -+ -+ dev = obj->my_dev; -+ obj_id = obj->obj_id; -+ -+ /* Check file size is consistent with tnode depth */ -+ last_chunk = -+ obj->variant.file_variant.file_size / dev->data_bytes_per_chunk + 1; -+ x = last_chunk >> YAFFS_TNODES_LEVEL0_BITS; -+ required_depth = 0; -+ while (x > 0) { -+ x >>= YAFFS_TNODES_INTERNAL_BITS; -+ required_depth++; -+ } -+ -+ actual_depth = obj->variant.file_variant.top_level; -+ -+ /* Check that the chunks in the tnode tree are all correct. -+ * We do this by scanning through the tnode tree and -+ * checking the tags for every chunk match. -+ */ -+ -+ if (yaffs_skip_nand_verification(dev)) -+ return; -+ -+ for (i = 1; i <= last_chunk; i++) { -+ tn = yaffs_find_tnode_0(dev, &obj->variant.file_variant, i); -+ -+ if (tn) { -+ u32 the_chunk = yaffs_get_group_base(dev, tn, i); -+ if (the_chunk > 0) { -+ /* T(~0,(TSTR("verifying (%d:%d) %d"TENDSTR),obj_id,i,the_chunk)); */ -+ yaffs_rd_chunk_tags_nand(dev, the_chunk, NULL, -+ &tags); -+ if (tags.obj_id != obj_id || tags.chunk_id != i) { -+ T(~0, -+ (TSTR -+ ("Object %d chunk_id %d NAND mismatch chunk %d tags (%d:%d)" -+ TENDSTR), obj_id, i, the_chunk, -+ tags.obj_id, tags.chunk_id)); -+ } -+ } -+ } -+ } -+} -+ -+void yaffs_verify_link(struct yaffs_obj *obj) -+{ -+ if (obj && yaffs_skip_verification(obj->my_dev)) -+ return; -+ -+ /* Verify sane equivalent object */ -+} -+ -+void yaffs_verify_symlink(struct yaffs_obj *obj) -+{ -+ if (obj && yaffs_skip_verification(obj->my_dev)) -+ return; -+ -+ /* Verify symlink string */ -+} -+ -+void yaffs_verify_special(struct yaffs_obj *obj) -+{ -+ if (obj && yaffs_skip_verification(obj->my_dev)) -+ return; -+} -+ -+void yaffs_verify_obj(struct yaffs_obj *obj) -+{ -+ struct yaffs_dev *dev; -+ -+ u32 chunk_min; -+ u32 chunk_max; -+ -+ u32 chunk_id_ok; -+ u32 chunk_in_range; -+ u32 chunk_wrongly_deleted; -+ u32 chunk_valid; -+ -+ if (!obj) -+ return; -+ -+ if (obj->being_created) -+ return; -+ -+ dev = obj->my_dev; -+ -+ if (yaffs_skip_verification(dev)) -+ return; -+ -+ /* Check sane object header chunk */ -+ -+ chunk_min = dev->internal_start_block * dev->param.chunks_per_block; -+ chunk_max = -+ (dev->internal_end_block + 1) * dev->param.chunks_per_block - 1; -+ -+ chunk_in_range = (((unsigned)(obj->hdr_chunk)) >= chunk_min && -+ ((unsigned)(obj->hdr_chunk)) <= chunk_max); -+ chunk_id_ok = chunk_in_range || (obj->hdr_chunk == 0); -+ chunk_valid = chunk_in_range && -+ yaffs_check_chunk_bit(dev, -+ obj->hdr_chunk / dev->param.chunks_per_block, -+ obj->hdr_chunk % dev->param.chunks_per_block); -+ chunk_wrongly_deleted = chunk_in_range && !chunk_valid; -+ -+ if (!obj->fake && (!chunk_id_ok || chunk_wrongly_deleted)) { -+ T(YAFFS_TRACE_VERIFY, -+ (TSTR("Obj %d has chunk_id %d %s %s" TENDSTR), -+ obj->obj_id, obj->hdr_chunk, -+ chunk_id_ok ? "" : ",out of range", -+ chunk_wrongly_deleted ? ",marked as deleted" : "")); -+ } -+ -+ if (chunk_valid && !yaffs_skip_nand_verification(dev)) { -+ struct yaffs_ext_tags tags; -+ struct yaffs_obj_hdr *oh; -+ u8 *buffer = yaffs_get_temp_buffer(dev, __LINE__); -+ -+ oh = (struct yaffs_obj_hdr *)buffer; -+ -+ yaffs_rd_chunk_tags_nand(dev, obj->hdr_chunk, buffer, &tags); -+ -+ yaffs_verify_oh(obj, oh, &tags, 1); -+ -+ yaffs_release_temp_buffer(dev, buffer, __LINE__); -+ } -+ -+ /* Verify it has a parent */ -+ if (obj && !obj->fake && (!obj->parent || obj->parent->my_dev != dev)) { -+ T(YAFFS_TRACE_VERIFY, -+ (TSTR -+ ("Obj %d has parent pointer %p which does not look like an object" -+ TENDSTR), obj->obj_id, obj->parent)); -+ } -+ -+ /* Verify parent is a directory */ -+ if (obj->parent -+ && obj->parent->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) { -+ T(YAFFS_TRACE_VERIFY, -+ (TSTR("Obj %d's parent is not a directory (type %d)" TENDSTR), -+ obj->obj_id, obj->parent->variant_type)); -+ } -+ -+ switch (obj->variant_type) { -+ case YAFFS_OBJECT_TYPE_FILE: -+ yaffs_verify_file(obj); -+ break; -+ case YAFFS_OBJECT_TYPE_SYMLINK: -+ yaffs_verify_symlink(obj); -+ break; -+ case YAFFS_OBJECT_TYPE_DIRECTORY: -+ yaffs_verify_dir(obj); -+ break; -+ case YAFFS_OBJECT_TYPE_HARDLINK: -+ yaffs_verify_link(obj); -+ break; -+ case YAFFS_OBJECT_TYPE_SPECIAL: -+ yaffs_verify_special(obj); -+ break; -+ case YAFFS_OBJECT_TYPE_UNKNOWN: -+ default: -+ T(YAFFS_TRACE_VERIFY, -+ (TSTR("Obj %d has illegaltype %d" TENDSTR), -+ obj->obj_id, obj->variant_type)); -+ break; -+ } -+} -+ -+void yaffs_verify_objects(struct yaffs_dev *dev) -+{ -+ struct yaffs_obj *obj; -+ int i; -+ struct list_head *lh; -+ -+ if (yaffs_skip_verification(dev)) -+ return; -+ -+ /* Iterate through the objects in each hash entry */ -+ -+ for (i = 0; i < YAFFS_NOBJECT_BUCKETS; i++) { -+ list_for_each(lh, &dev->obj_bucket[i].list) { -+ if (lh) { -+ obj = -+ list_entry(lh, struct yaffs_obj, hash_link); -+ yaffs_verify_obj(obj); -+ } -+ } -+ } -+} -+ -+void yaffs_verify_obj_in_dir(struct yaffs_obj *obj) -+{ -+ struct list_head *lh; -+ struct yaffs_obj *list_obj; -+ -+ int count = 0; -+ -+ if (!obj) { -+ T(YAFFS_TRACE_ALWAYS, (TSTR("No object to verify" TENDSTR))); -+ YBUG(); -+ return; -+ } -+ -+ if (yaffs_skip_verification(obj->my_dev)) -+ return; -+ -+ if (!obj->parent) { -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR("Object does not have parent" TENDSTR))); -+ YBUG(); -+ return; -+ } -+ -+ if (obj->parent->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) { -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR("Parent is not directory" TENDSTR))); -+ YBUG(); -+ } -+ -+ /* Iterate through the objects in each hash entry */ -+ -+ list_for_each(lh, &obj->parent->variant.dir_variant.children) { -+ if (lh) { -+ list_obj = list_entry(lh, struct yaffs_obj, siblings); -+ yaffs_verify_obj(list_obj); -+ if (obj == list_obj) -+ count++; -+ } -+ } -+ -+ if (count != 1) { -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR("Object in directory %d times" TENDSTR), count)); -+ YBUG(); -+ } -+} -+ -+void yaffs_verify_dir(struct yaffs_obj *directory) -+{ -+ struct list_head *lh; -+ struct yaffs_obj *list_obj; -+ -+ if (!directory) { -+ YBUG(); -+ return; -+ } -+ -+ if (yaffs_skip_full_verification(directory->my_dev)) -+ return; -+ -+ if (directory->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) { -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR("Directory has wrong type: %d" TENDSTR), -+ directory->variant_type)); -+ YBUG(); -+ } -+ -+ /* Iterate through the objects in each hash entry */ -+ -+ list_for_each(lh, &directory->variant.dir_variant.children) { -+ if (lh) { -+ list_obj = list_entry(lh, struct yaffs_obj, siblings); -+ if (list_obj->parent != directory) { -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR -+ ("Object in directory list has wrong parent %p" -+ TENDSTR), list_obj->parent)); -+ YBUG(); -+ } -+ yaffs_verify_obj_in_dir(list_obj); -+ } -+ } -+} -+ -+static int yaffs_free_verification_failures; -+ -+void yaffs_verify_free_chunks(struct yaffs_dev *dev) -+{ -+ int counted; -+ int difference; -+ -+ if (yaffs_skip_verification(dev)) -+ return; -+ -+ counted = yaffs_count_free_chunks(dev); -+ -+ difference = dev->n_free_chunks - counted; -+ -+ if (difference) { -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR("Freechunks verification failure %d %d %d" TENDSTR), -+ dev->n_free_chunks, counted, difference)); -+ yaffs_free_verification_failures++; -+ } -+} -+ -+int yaffs_verify_file_sane(struct yaffs_obj *in) -+{ -+ in = in; -+ return YAFFS_OK; -+} -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_verify.h linux-2.6.36/fs/yaffs2/yaffs_verify.h ---- linux-2.6.36.orig/fs/yaffs2/yaffs_verify.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_verify.h 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,43 @@ -+/* -+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU Lesser General Public License version 2.1 as -+ * published by the Free Software Foundation. -+ * -+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. -+ */ -+ -+#ifndef __YAFFS_VERIFY_H__ -+#define __YAFFS_VERIFY_H__ -+ -+#include "yaffs_guts.h" -+ -+void yaffs_verify_blk(struct yaffs_dev *dev, struct yaffs_block_info *bi, -+ int n); -+void yaffs_verify_collected_blk(struct yaffs_dev *dev, -+ struct yaffs_block_info *bi, int n); -+void yaffs_verify_blocks(struct yaffs_dev *dev); -+ -+void yaffs_verify_oh(struct yaffs_obj *obj, struct yaffs_obj_hdr *oh, -+ struct yaffs_ext_tags *tags, int parent_check); -+void yaffs_verify_file(struct yaffs_obj *obj); -+void yaffs_verify_link(struct yaffs_obj *obj); -+void yaffs_verify_symlink(struct yaffs_obj *obj); -+void yaffs_verify_special(struct yaffs_obj *obj); -+void yaffs_verify_obj(struct yaffs_obj *obj); -+void yaffs_verify_objects(struct yaffs_dev *dev); -+void yaffs_verify_obj_in_dir(struct yaffs_obj *obj); -+void yaffs_verify_dir(struct yaffs_obj *directory); -+void yaffs_verify_free_chunks(struct yaffs_dev *dev); -+ -+int yaffs_verify_file_sane(struct yaffs_obj *obj); -+ -+int yaffs_skip_verification(struct yaffs_dev *dev); -+ -+#endif -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_vfs.c linux-2.6.36/fs/yaffs2/yaffs_vfs.c ---- linux-2.6.36.orig/fs/yaffs2/yaffs_vfs.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_vfs.c 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,3565 @@ -+/* -+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * Acknowledgements: -+ * Luc van OostenRyck for numerous patches. -+ * Nick Bane for numerous patches. -+ * Nick Bane for 2.5/2.6 integration. -+ * Andras Toth for mknod rdev issue. -+ * Michael Fischer for finding the problem with inode inconsistency. -+ * Some code bodily lifted from JFFS -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+/* -+ * -+ * This is the file system front-end to YAFFS that hooks it up to -+ * the VFS. -+ * -+ * Special notes: -+ * >> 2.4: sb->u.generic_sbp points to the struct yaffs_dev associated with -+ * this superblock -+ * >> 2.6: sb->s_fs_info points to the struct yaffs_dev associated with this -+ * superblock -+ * >> inode->u.generic_ip points to the associated struct yaffs_obj. -+ */ -+ -+/* -+ * There are two variants of the VFS glue code. This variant should compile -+ * for any version of Linux. -+ */ -+#include -+ -+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 10)) -+#define YAFFS_COMPILE_BACKGROUND -+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6, 23)) -+#define YAFFS_COMPILE_FREEZER -+#endif -+#endif -+ -+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)) -+#define YAFFS_COMPILE_EXPORTFS -+#endif -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)) -+#define YAFFS_USE_SETATTR_COPY -+#define YAFFS_USE_TRUNCATE_SETSIZE -+#endif -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)) -+#define YAFFS_HAS_EVICT_INODE -+#endif -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,13)) -+#define YAFFS_NEW_FOLLOW_LINK 1 -+#else -+#define YAFFS_NEW_FOLLOW_LINK 0 -+#endif -+ -+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19)) -+#include -+#endif -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#if (YAFFS_NEW_FOLLOW_LINK == 1) -+#include -+#endif -+ -+#ifdef YAFFS_COMPILE_EXPORTFS -+#include -+#endif -+ -+#ifdef YAFFS_COMPILE_BACKGROUND -+#include -+#include -+#endif -+#ifdef YAFFS_COMPILE_FREEZER -+#include -+#endif -+ -+#include -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) -+ -+#include -+ -+#define UnlockPage(p) unlock_page(p) -+#define Page_Uptodate(page) test_bit(PG_uptodate, &(page)->flags) -+ -+/* FIXME: use sb->s_id instead ? */ -+#define yaffs_devname(sb, buf) bdevname(sb->s_bdev, buf) -+ -+#else -+ -+#include -+#define BDEVNAME_SIZE 0 -+#define yaffs_devname(sb, buf) kdevname(sb->s_dev) -+ -+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 0)) -+/* added NCB 26/5/2006 for 2.4.25-vrs2-tcl1 kernel */ -+#define __user -+#endif -+ -+#endif -+ -+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 26)) -+#define YPROC_ROOT (&proc_root) -+#else -+#define YPROC_ROOT NULL -+#endif -+ -+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) -+#define Y_INIT_TIMER(a) init_timer(a) -+#else -+#define Y_INIT_TIMER(a) init_timer_on_stack(a) -+#endif -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17)) -+#define WRITE_SIZE_STR "writesize" -+#define WRITE_SIZE(mtd) ((mtd)->writesize) -+#else -+#define WRITE_SIZE_STR "oobblock" -+#define WRITE_SIZE(mtd) ((mtd)->oobblock) -+#endif -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 27)) -+#define YAFFS_USE_WRITE_BEGIN_END 1 -+#else -+#define YAFFS_USE_WRITE_BEGIN_END 0 -+#endif -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 28)) -+static uint32_t YCALCBLOCKS(uint64_t partition_size, uint32_t block_size) -+{ -+ uint64_t result = partition_size; -+ do_div(result, block_size); -+ return (uint32_t) result; -+} -+#else -+#define YCALCBLOCKS(s, b) ((s)/(b)) -+#endif -+ -+#include -+#include -+ -+#include "yportenv.h" -+#include "yaffs_trace.h" -+#include "yaffs_guts.h" -+#include "yaffs_attribs.h" -+ -+#include "yaffs_linux.h" -+ -+#include "yaffs_mtdif.h" -+#include "yaffs_mtdif1.h" -+#include "yaffs_mtdif2.h" -+ -+unsigned int yaffs_trace_mask = YAFFS_TRACE_BAD_BLOCKS | YAFFS_TRACE_ALWAYS; -+unsigned int yaffs_wr_attempts = YAFFS_WR_ATTEMPTS; -+unsigned int yaffs_auto_checkpoint = 1; -+unsigned int yaffs_gc_control = 1; -+unsigned int yaffs_bg_enable = 1; -+ -+/* Module Parameters */ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) -+module_param(yaffs_trace_mask, uint, 0644); -+module_param(yaffs_wr_attempts, uint, 0644); -+module_param(yaffs_auto_checkpoint, uint, 0644); -+module_param(yaffs_gc_control, uint, 0644); -+module_param(yaffs_bg_enable, uint, 0644); -+#else -+MODULE_PARM(yaffs_trace_mask, "i"); -+MODULE_PARM(yaffs_wr_attempts, "i"); -+MODULE_PARM(yaffs_auto_checkpoint, "i"); -+MODULE_PARM(yaffs_gc_control, "i"); -+#endif -+ -+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 25)) -+/* use iget and read_inode */ -+#define Y_IGET(sb, inum) iget((sb), (inum)) -+static void yaffs_read_inode(struct inode *inode); -+ -+#else -+/* Call local equivalent */ -+#define YAFFS_USE_OWN_IGET -+#define Y_IGET(sb, inum) yaffs_iget((sb), (inum)) -+ -+static struct inode *yaffs_iget(struct super_block *sb, unsigned long ino); -+#endif -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 18)) -+#define yaffs_inode_to_obj_lv(iptr) ((iptr)->i_private) -+#else -+#define yaffs_inode_to_obj_lv(iptr) ((iptr)->u.generic_ip) -+#endif -+ -+#define yaffs_inode_to_obj(iptr) ((struct yaffs_obj *)(yaffs_inode_to_obj_lv(iptr))) -+#define yaffs_dentry_to_obj(dptr) yaffs_inode_to_obj((dptr)->d_inode) -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) -+#define yaffs_super_to_dev(sb) ((struct yaffs_dev *)sb->s_fs_info) -+#else -+#define yaffs_super_to_dev(sb) ((struct yaffs_dev *)sb->u.generic_sbp) -+#endif -+ -+#define update_dir_time(dir) do {\ -+ (dir)->i_ctime = (dir)->i_mtime = CURRENT_TIME; \ -+ } while(0) -+ -+static void yaffs_put_super(struct super_block *sb); -+ -+static ssize_t yaffs_file_write(struct file *f, const char *buf, size_t n, -+ loff_t * pos); -+static ssize_t yaffs_hold_space(struct file *f); -+static void yaffs_release_space(struct file *f); -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17)) -+static int yaffs_file_flush(struct file *file, fl_owner_t id); -+#else -+static int yaffs_file_flush(struct file *file); -+#endif -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 34)) -+static int yaffs_sync_object(struct file *file, int datasync); -+#else -+static int yaffs_sync_object(struct file *file, struct dentry *dentry, -+ int datasync); -+#endif -+ -+static int yaffs_readdir(struct file *f, void *dirent, filldir_t filldir); -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) -+static int yaffs_create(struct inode *dir, struct dentry *dentry, int mode, -+ struct nameidata *n); -+static struct dentry *yaffs_lookup(struct inode *dir, struct dentry *dentry, -+ struct nameidata *n); -+#else -+static int yaffs_create(struct inode *dir, struct dentry *dentry, int mode); -+static struct dentry *yaffs_lookup(struct inode *dir, struct dentry *dentry); -+#endif -+static int yaffs_link(struct dentry *old_dentry, struct inode *dir, -+ struct dentry *dentry); -+static int yaffs_unlink(struct inode *dir, struct dentry *dentry); -+static int yaffs_symlink(struct inode *dir, struct dentry *dentry, -+ const char *symname); -+static int yaffs_mkdir(struct inode *dir, struct dentry *dentry, int mode); -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) -+static int yaffs_mknod(struct inode *dir, struct dentry *dentry, int mode, -+ dev_t dev); -+#else -+static int yaffs_mknod(struct inode *dir, struct dentry *dentry, int mode, -+ int dev); -+#endif -+static int yaffs_rename(struct inode *old_dir, struct dentry *old_dentry, -+ struct inode *new_dir, struct dentry *new_dentry); -+static int yaffs_setattr(struct dentry *dentry, struct iattr *attr); -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17)) -+static int yaffs_sync_fs(struct super_block *sb, int wait); -+static void yaffs_write_super(struct super_block *sb); -+#else -+static int yaffs_sync_fs(struct super_block *sb); -+static int yaffs_write_super(struct super_block *sb); -+#endif -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17)) -+static int yaffs_statfs(struct dentry *dentry, struct kstatfs *buf); -+#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) -+static int yaffs_statfs(struct super_block *sb, struct kstatfs *buf); -+#else -+static int yaffs_statfs(struct super_block *sb, struct statfs *buf); -+#endif -+ -+#ifdef YAFFS_HAS_PUT_INODE -+static void yaffs_put_inode(struct inode *inode); -+#endif -+ -+#ifdef YAFFS_HAS_EVICT_INODE -+static void yaffs_evict_inode(struct inode *); -+#else -+static void yaffs_delete_inode(struct inode *); -+static void yaffs_clear_inode(struct inode *); -+#endif -+ -+static int yaffs_readpage(struct file *file, struct page *page); -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) -+static int yaffs_writepage(struct page *page, struct writeback_control *wbc); -+#else -+static int yaffs_writepage(struct page *page); -+#endif -+ -+#ifdef CONFIG_YAFFS_XATTR -+int yaffs_setxattr(struct dentry *dentry, const char *name, -+ const void *value, size_t size, int flags); -+ssize_t yaffs_getxattr(struct dentry *dentry, const char *name, void *buff, -+ size_t size); -+int yaffs_removexattr(struct dentry *dentry, const char *name); -+ssize_t yaffs_listxattr(struct dentry *dentry, char *buff, size_t size); -+#endif -+ -+#if (YAFFS_USE_WRITE_BEGIN_END != 0) -+static int yaffs_write_begin(struct file *filp, struct address_space *mapping, -+ loff_t pos, unsigned len, unsigned flags, -+ struct page **pagep, void **fsdata); -+static int yaffs_write_end(struct file *filp, struct address_space *mapping, -+ loff_t pos, unsigned len, unsigned copied, -+ struct page *pg, void *fsdadata); -+#else -+static int yaffs_prepare_write(struct file *f, struct page *pg, -+ unsigned offset, unsigned to); -+static int yaffs_commit_write(struct file *f, struct page *pg, unsigned offset, -+ unsigned to); -+ -+#endif -+ -+static int yaffs_readlink(struct dentry *dentry, char __user * buffer, -+ int buflen); -+#if (YAFFS_NEW_FOLLOW_LINK == 1) -+void yaffs_put_link(struct dentry *dentry, struct nameidata *nd, void *alias); -+static void *yaffs_follow_link(struct dentry *dentry, struct nameidata *nd); -+#else -+static int yaffs_follow_link(struct dentry *dentry, struct nameidata *nd); -+#endif -+ -+static void yaffs_touch_super(struct yaffs_dev *dev); -+ -+static loff_t yaffs_dir_llseek(struct file *file, loff_t offset, int origin); -+ -+static int yaffs_vfs_setattr(struct inode *, struct iattr *); -+ -+static struct address_space_operations yaffs_file_address_operations = { -+ .readpage = yaffs_readpage, -+ .writepage = yaffs_writepage, -+#if (YAFFS_USE_WRITE_BEGIN_END > 0) -+ .write_begin = yaffs_write_begin, -+ .write_end = yaffs_write_end, -+#else -+ .prepare_write = yaffs_prepare_write, -+ .commit_write = yaffs_commit_write, -+#endif -+}; -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 22)) -+static const struct file_operations yaffs_file_operations = { -+ .read = do_sync_read, -+ .write = do_sync_write, -+ .aio_read = generic_file_aio_read, -+ .aio_write = generic_file_aio_write, -+ .mmap = generic_file_mmap, -+ .flush = yaffs_file_flush, -+ .fsync = yaffs_sync_object, -+ .splice_read = generic_file_splice_read, -+ .splice_write = generic_file_splice_write, -+ .llseek = generic_file_llseek, -+}; -+ -+#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 18)) -+ -+static const struct file_operations yaffs_file_operations = { -+ .read = do_sync_read, -+ .write = do_sync_write, -+ .aio_read = generic_file_aio_read, -+ .aio_write = generic_file_aio_write, -+ .mmap = generic_file_mmap, -+ .flush = yaffs_file_flush, -+ .fsync = yaffs_sync_object, -+ .sendfile = generic_file_sendfile, -+}; -+ -+#else -+ -+static const struct file_operations yaffs_file_operations = { -+ .read = generic_file_read, -+ .write = generic_file_write, -+ .mmap = generic_file_mmap, -+ .flush = yaffs_file_flush, -+ .fsync = yaffs_sync_object, -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) -+ .sendfile = generic_file_sendfile, -+#endif -+}; -+#endif -+ -+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)) -+static void zero_user_segment(struct page *page, unsigned start, unsigned end) -+{ -+ void *kaddr = kmap_atomic(page, KM_USER0); -+ memset(kaddr + start, 0, end - start); -+ kunmap_atomic(kaddr, KM_USER0); -+ flush_dcache_page(page); -+} -+#endif -+ -+static const struct inode_operations yaffs_file_inode_operations = { -+ .setattr = yaffs_setattr, -+#ifdef CONFIG_YAFFS_XATTR -+ .setxattr = yaffs_setxattr, -+ .getxattr = yaffs_getxattr, -+ .listxattr = yaffs_listxattr, -+ .removexattr = yaffs_removexattr, -+#endif -+}; -+ -+static const struct inode_operations yaffs_symlink_inode_operations = { -+ .readlink = yaffs_readlink, -+ .follow_link = yaffs_follow_link, -+#if (YAFFS_NEW_FOLLOW_LINK == 1) -+ .put_link = yaffs_put_link, -+#endif -+ .setattr = yaffs_setattr, -+#ifdef CONFIG_YAFFS_XATTR -+ .setxattr = yaffs_setxattr, -+ .getxattr = yaffs_getxattr, -+ .listxattr = yaffs_listxattr, -+ .removexattr = yaffs_removexattr, -+#endif -+}; -+ -+static const struct inode_operations yaffs_dir_inode_operations = { -+ .create = yaffs_create, -+ .lookup = yaffs_lookup, -+ .link = yaffs_link, -+ .unlink = yaffs_unlink, -+ .symlink = yaffs_symlink, -+ .mkdir = yaffs_mkdir, -+ .rmdir = yaffs_unlink, -+ .mknod = yaffs_mknod, -+ .rename = yaffs_rename, -+ .setattr = yaffs_setattr, -+#ifdef CONFIG_YAFFS_XATTR -+ .setxattr = yaffs_setxattr, -+ .getxattr = yaffs_getxattr, -+ .listxattr = yaffs_listxattr, -+ .removexattr = yaffs_removexattr, -+#endif -+}; -+ -+static const struct file_operations yaffs_dir_operations = { -+ .read = generic_read_dir, -+ .readdir = yaffs_readdir, -+ .fsync = yaffs_sync_object, -+ .llseek = yaffs_dir_llseek, -+}; -+ -+static const struct super_operations yaffs_super_ops = { -+ .statfs = yaffs_statfs, -+ -+#ifndef YAFFS_USE_OWN_IGET -+ .read_inode = yaffs_read_inode, -+#endif -+#ifdef YAFFS_HAS_PUT_INODE -+ .put_inode = yaffs_put_inode, -+#endif -+ .put_super = yaffs_put_super, -+#ifdef YAFFS_HAS_EVICT_INODE -+ .evict_inode = yaffs_evict_inode, -+#else -+ .delete_inode = yaffs_delete_inode, -+ .clear_inode = yaffs_clear_inode, -+#endif -+ .sync_fs = yaffs_sync_fs, -+ .write_super = yaffs_write_super, -+}; -+ -+static int yaffs_vfs_setattr(struct inode *inode, struct iattr *attr) -+{ -+#ifdef YAFFS_USE_SETATTR_COPY -+ setattr_copy(inode, attr); -+ return 0; -+#else -+ return inode_setattr(inode, attr); -+#endif -+ -+} -+ -+static int yaffs_vfs_setsize(struct inode *inode, loff_t newsize) -+{ -+#ifdef YAFFS_USE_TRUNCATE_SETSIZE -+ truncate_setsize(inode, newsize); -+ return 0; -+#else -+ truncate_inode_pages(&inode->i_data, newsize); -+ return 0; -+#endif -+ -+} -+ -+static unsigned yaffs_gc_control_callback(struct yaffs_dev *dev) -+{ -+ return yaffs_gc_control; -+} -+ -+static void yaffs_gross_lock(struct yaffs_dev *dev) -+{ -+ T(YAFFS_TRACE_LOCK, (TSTR("yaffs locking %p\n"), current)); -+ mutex_lock(&(yaffs_dev_to_lc(dev)->gross_lock)); -+ T(YAFFS_TRACE_LOCK, (TSTR("yaffs locked %p\n"), current)); -+} -+ -+static void yaffs_gross_unlock(struct yaffs_dev *dev) -+{ -+ T(YAFFS_TRACE_LOCK, (TSTR("yaffs unlocking %p\n"), current)); -+ mutex_unlock(&(yaffs_dev_to_lc(dev)->gross_lock)); -+} -+ -+#ifdef YAFFS_COMPILE_EXPORTFS -+ -+static struct inode *yaffs2_nfs_get_inode(struct super_block *sb, uint64_t ino, -+ uint32_t generation) -+{ -+ return Y_IGET(sb, ino); -+} -+ -+static struct dentry *yaffs2_fh_to_dentry(struct super_block *sb, -+ struct fid *fid, int fh_len, -+ int fh_type) -+{ -+ return generic_fh_to_dentry(sb, fid, fh_len, fh_type, -+ yaffs2_nfs_get_inode); -+} -+ -+static struct dentry *yaffs2_fh_to_parent(struct super_block *sb, -+ struct fid *fid, int fh_len, -+ int fh_type) -+{ -+ return generic_fh_to_parent(sb, fid, fh_len, fh_type, -+ yaffs2_nfs_get_inode); -+} -+ -+struct dentry *yaffs2_get_parent(struct dentry *dentry) -+{ -+ -+ struct super_block *sb = dentry->d_inode->i_sb; -+ struct dentry *parent = ERR_PTR(-ENOENT); -+ struct inode *inode; -+ unsigned long parent_ino; -+ struct yaffs_obj *d_obj; -+ struct yaffs_obj *parent_obj; -+ -+ d_obj = yaffs_inode_to_obj(dentry->d_inode); -+ -+ if (d_obj) { -+ parent_obj = d_obj->parent; -+ if (parent_obj) { -+ parent_ino = yaffs_get_obj_inode(parent_obj); -+ inode = Y_IGET(sb, parent_ino); -+ -+ if (IS_ERR(inode)) { -+ parent = ERR_CAST(inode); -+ } else { -+ parent = d_obtain_alias(inode); -+ if (!IS_ERR(parent)) { -+ parent = ERR_PTR(-ENOMEM); -+ iput(inode); -+ } -+ } -+ } -+ } -+ -+ return parent; -+} -+ -+/* Just declare a zero structure as a NULL value implies -+ * using the default functions of exportfs. -+ */ -+ -+static struct export_operations yaffs_export_ops = { -+ .fh_to_dentry = yaffs2_fh_to_dentry, -+ .fh_to_parent = yaffs2_fh_to_parent, -+ .get_parent = yaffs2_get_parent, -+}; -+ -+#endif -+ -+/*-----------------------------------------------------------------*/ -+/* Directory search context allows us to unlock access to yaffs during -+ * filldir without causing problems with the directory being modified. -+ * This is similar to the tried and tested mechanism used in yaffs direct. -+ * -+ * A search context iterates along a doubly linked list of siblings in the -+ * directory. If the iterating object is deleted then this would corrupt -+ * the list iteration, likely causing a crash. The search context avoids -+ * this by using the remove_obj_fn to move the search context to the -+ * next object before the object is deleted. -+ * -+ * Many readdirs (and thus seach conexts) may be alive simulateously so -+ * each struct yaffs_dev has a list of these. -+ * -+ * A seach context lives for the duration of a readdir. -+ * -+ * All these functions must be called while yaffs is locked. -+ */ -+ -+struct yaffs_search_context { -+ struct yaffs_dev *dev; -+ struct yaffs_obj *dir_obj; -+ struct yaffs_obj *next_return; -+ struct list_head others; -+}; -+ -+/* -+ * yaffs_new_search() creates a new search context, initialises it and -+ * adds it to the device's search context list. -+ * -+ * Called at start of readdir. -+ */ -+static struct yaffs_search_context *yaffs_new_search(struct yaffs_obj *dir) -+{ -+ struct yaffs_dev *dev = dir->my_dev; -+ struct yaffs_search_context *sc = -+ YMALLOC(sizeof(struct yaffs_search_context)); -+ if (sc) { -+ sc->dir_obj = dir; -+ sc->dev = dev; -+ if (list_empty(&sc->dir_obj->variant.dir_variant.children)) -+ sc->next_return = NULL; -+ else -+ sc->next_return = -+ list_entry(dir->variant.dir_variant.children.next, -+ struct yaffs_obj, siblings); -+ INIT_LIST_HEAD(&sc->others); -+ list_add(&sc->others, &(yaffs_dev_to_lc(dev)->search_contexts)); -+ } -+ return sc; -+} -+ -+/* -+ * yaffs_search_end() disposes of a search context and cleans up. -+ */ -+static void yaffs_search_end(struct yaffs_search_context *sc) -+{ -+ if (sc) { -+ list_del(&sc->others); -+ YFREE(sc); -+ } -+} -+ -+/* -+ * yaffs_search_advance() moves a search context to the next object. -+ * Called when the search iterates or when an object removal causes -+ * the search context to be moved to the next object. -+ */ -+static void yaffs_search_advance(struct yaffs_search_context *sc) -+{ -+ if (!sc) -+ return; -+ -+ if (sc->next_return == NULL || -+ list_empty(&sc->dir_obj->variant.dir_variant.children)) -+ sc->next_return = NULL; -+ else { -+ struct list_head *next = sc->next_return->siblings.next; -+ -+ if (next == &sc->dir_obj->variant.dir_variant.children) -+ sc->next_return = NULL; /* end of list */ -+ else -+ sc->next_return = -+ list_entry(next, struct yaffs_obj, siblings); -+ } -+} -+ -+/* -+ * yaffs_remove_obj_callback() is called when an object is unlinked. -+ * We check open search contexts and advance any which are currently -+ * on the object being iterated. -+ */ -+static void yaffs_remove_obj_callback(struct yaffs_obj *obj) -+{ -+ -+ struct list_head *i; -+ struct yaffs_search_context *sc; -+ struct list_head *search_contexts = -+ &(yaffs_dev_to_lc(obj->my_dev)->search_contexts); -+ -+ /* Iterate through the directory search contexts. -+ * If any are currently on the object being removed, then advance -+ * the search context to the next object to prevent a hanging pointer. -+ */ -+ list_for_each(i, search_contexts) { -+ if (i) { -+ sc = list_entry(i, struct yaffs_search_context, others); -+ if (sc->next_return == obj) -+ yaffs_search_advance(sc); -+ } -+ } -+ -+} -+ -+/*-----------------------------------------------------------------*/ -+ -+static int yaffs_readlink(struct dentry *dentry, char __user * buffer, -+ int buflen) -+{ -+ unsigned char *alias; -+ int ret; -+ -+ struct yaffs_dev *dev = yaffs_dentry_to_obj(dentry)->my_dev; -+ -+ yaffs_gross_lock(dev); -+ -+ alias = yaffs_get_symlink_alias(yaffs_dentry_to_obj(dentry)); -+ -+ yaffs_gross_unlock(dev); -+ -+ if (!alias) -+ return -ENOMEM; -+ -+ ret = vfs_readlink(dentry, buffer, buflen, alias); -+ kfree(alias); -+ return ret; -+} -+ -+#if (YAFFS_NEW_FOLLOW_LINK == 1) -+static void *yaffs_follow_link(struct dentry *dentry, struct nameidata *nd) -+{ -+ void *ret; -+#else -+static int yaffs_follow_link(struct dentry *dentry, struct nameidata *nd) -+{ -+ int ret -+#endif -+ unsigned char *alias; -+ int ret_int = 0; -+ struct yaffs_dev *dev = yaffs_dentry_to_obj(dentry)->my_dev; -+ -+ yaffs_gross_lock(dev); -+ -+ alias = yaffs_get_symlink_alias(yaffs_dentry_to_obj(dentry)); -+ yaffs_gross_unlock(dev); -+ -+ if (!alias) { -+ ret_int = -ENOMEM; -+ goto out; -+ } -+#if (YAFFS_NEW_FOLLOW_LINK == 1) -+ nd_set_link(nd, alias); -+ ret = alias; -+out: -+ if (ret_int) -+ ret = ERR_PTR(ret_int); -+ return ret; -+#else -+ ret = vfs_follow_link(nd, alias); -+ kfree(alias); -+out: -+ if (ret_int) -+ ret = ret_int; -+ return ret; -+#endif -+} -+ -+#if (YAFFS_NEW_FOLLOW_LINK == 1) -+void yaffs_put_link(struct dentry *dentry, struct nameidata *nd, void *alias) -+{ -+ kfree(alias); -+} -+#endif -+ -+struct inode *yaffs_get_inode(struct super_block *sb, int mode, int dev, -+ struct yaffs_obj *obj); -+ -+/* -+ * Lookup is used to find objects in the fs -+ */ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) -+ -+static struct dentry *yaffs_lookup(struct inode *dir, struct dentry *dentry, -+ struct nameidata *n) -+#else -+static struct dentry *yaffs_lookup(struct inode *dir, struct dentry *dentry) -+#endif -+{ -+ struct yaffs_obj *obj; -+ struct inode *inode = NULL; /* NCB 2.5/2.6 needs NULL here */ -+ -+ struct yaffs_dev *dev = yaffs_inode_to_obj(dir)->my_dev; -+ -+ if (current != yaffs_dev_to_lc(dev)->readdir_process) -+ yaffs_gross_lock(dev); -+ -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_lookup for %d:%s\n"), -+ yaffs_inode_to_obj(dir)->obj_id, dentry->d_name.name)); -+ -+ obj = yaffs_find_by_name(yaffs_inode_to_obj(dir), dentry->d_name.name); -+ -+ obj = yaffs_get_equivalent_obj(obj); /* in case it was a hardlink */ -+ -+ /* Can't hold gross lock when calling yaffs_get_inode() */ -+ if (current != yaffs_dev_to_lc(dev)->readdir_process) -+ yaffs_gross_unlock(dev); -+ -+ if (obj) { -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_lookup found %d\n"), obj->obj_id)); -+ -+ inode = yaffs_get_inode(dir->i_sb, obj->yst_mode, 0, obj); -+ -+ if (inode) { -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_loookup dentry \n"))); -+/* #if 0 asserted by NCB for 2.5/6 compatability - falls through to -+ * d_add even if NULL inode */ -+#if 0 -+ /*dget(dentry); // try to solve directory bug */ -+ d_add(dentry, inode); -+ -+ /* return dentry; */ -+ return NULL; -+#endif -+ } -+ -+ } else { -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_lookup not found\n"))); -+ -+ } -+ -+/* added NCB for 2.5/6 compatability - forces add even if inode is -+ * NULL which creates dentry hash */ -+ d_add(dentry, inode); -+ -+ return NULL; -+} -+ -+#ifdef YAFFS_HAS_PUT_INODE -+ -+/* For now put inode is just for debugging -+ * Put inode is called when the inode **structure** is put. -+ */ -+static void yaffs_put_inode(struct inode *inode) -+{ -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_put_inode: ino %d, count %d\n"), (int)inode->i_ino, -+ atomic_read(&inode->i_count))); -+ -+} -+#endif -+ -+static void yaffs_unstitch_obj(struct inode *inode, struct yaffs_obj *obj) -+{ -+ /* Clear the association between the inode and -+ * the struct yaffs_obj. -+ */ -+ obj->my_inode = NULL; -+ yaffs_inode_to_obj_lv(inode) = NULL; -+ -+ /* If the object freeing was deferred, then the real -+ * free happens now. -+ * This should fix the inode inconsistency problem. -+ */ -+ yaffs_handle_defered_free(obj); -+} -+ -+#ifdef YAFFS_HAS_EVICT_INODE -+/* yaffs_evict_inode combines into one operation what was previously done in -+ * yaffs_clear_inode() and yaffs_delete_inode() -+ * -+ */ -+static void yaffs_evict_inode(struct inode *inode) -+{ -+ struct yaffs_obj *obj; -+ struct yaffs_dev *dev; -+ int deleteme = 0; -+ -+ obj = yaffs_inode_to_obj(inode); -+ -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_evict_inode: ino %d, count %d %s\n"), (int)inode->i_ino, -+ atomic_read(&inode->i_count), -+ obj ? "object exists" : "null object")); -+ -+ if (!inode->i_nlink && !is_bad_inode(inode)) -+ deleteme = 1; -+ truncate_inode_pages(&inode->i_data, 0); -+ end_writeback(inode); -+ -+ if (deleteme && obj) { -+ dev = obj->my_dev; -+ yaffs_gross_lock(dev); -+ yaffs_del_obj(obj); -+ yaffs_gross_unlock(dev); -+ } -+ if (obj) { -+ dev = obj->my_dev; -+ yaffs_gross_lock(dev); -+ yaffs_unstitch_obj(inode, obj); -+ yaffs_gross_unlock(dev); -+ } -+ -+} -+#else -+ -+/* clear is called to tell the fs to release any per-inode data it holds. -+ * The object might still exist on disk and is just being thrown out of the cache -+ * or else the object has actually been deleted and we're being called via -+ * the chain -+ * yaffs_delete_inode() -> clear_inode()->yaffs_clear_inode() -+ */ -+ -+static void yaffs_clear_inode(struct inode *inode) -+{ -+ struct yaffs_obj *obj; -+ struct yaffs_dev *dev; -+ -+ obj = yaffs_inode_to_obj(inode); -+ -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_clear_inode: ino %d, count %d %s\n"), (int)inode->i_ino, -+ atomic_read(&inode->i_count), -+ obj ? "object exists" : "null object")); -+ -+ if (obj) { -+ dev = obj->my_dev; -+ yaffs_gross_lock(dev); -+ yaffs_unstitch_obj(inode, obj); -+ yaffs_gross_unlock(dev); -+ } -+ -+} -+ -+/* delete is called when the link count is zero and the inode -+ * is put (ie. nobody wants to know about it anymore, time to -+ * delete the file). -+ * NB Must call clear_inode() -+ */ -+static void yaffs_delete_inode(struct inode *inode) -+{ -+ struct yaffs_obj *obj = yaffs_inode_to_obj(inode); -+ struct yaffs_dev *dev; -+ -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_delete_inode: ino %d, count %d %s\n"), (int)inode->i_ino, -+ atomic_read(&inode->i_count), -+ obj ? "object exists" : "null object")); -+ -+ if (obj) { -+ dev = obj->my_dev; -+ yaffs_gross_lock(dev); -+ yaffs_del_obj(obj); -+ yaffs_gross_unlock(dev); -+ } -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 13)) -+ truncate_inode_pages(&inode->i_data, 0); -+#endif -+ clear_inode(inode); -+} -+#endif -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17)) -+static int yaffs_file_flush(struct file *file, fl_owner_t id) -+#else -+static int yaffs_file_flush(struct file *file) -+#endif -+{ -+ struct yaffs_obj *obj = yaffs_dentry_to_obj(file->f_dentry); -+ -+ struct yaffs_dev *dev = obj->my_dev; -+ -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_file_flush object %d (%s)\n"), obj->obj_id, -+ obj->dirty ? "dirty" : "clean")); -+ -+ yaffs_gross_lock(dev); -+ -+ yaffs_flush_file(obj, 1, 0); -+ -+ yaffs_gross_unlock(dev); -+ -+ return 0; -+} -+ -+static int yaffs_readpage_nolock(struct file *f, struct page *pg) -+{ -+ /* Lifted from jffs2 */ -+ -+ struct yaffs_obj *obj; -+ unsigned char *pg_buf; -+ int ret; -+ -+ struct yaffs_dev *dev; -+ -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_readpage_nolock at %08x, size %08x\n"), -+ (unsigned)(pg->index << PAGE_CACHE_SHIFT), -+ (unsigned)PAGE_CACHE_SIZE)); -+ -+ obj = yaffs_dentry_to_obj(f->f_dentry); -+ -+ dev = obj->my_dev; -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) -+ BUG_ON(!PageLocked(pg)); -+#else -+ if (!PageLocked(pg)) -+ PAGE_BUG(pg); -+#endif -+ -+ pg_buf = kmap(pg); -+ /* FIXME: Can kmap fail? */ -+ -+ yaffs_gross_lock(dev); -+ -+ ret = yaffs_file_rd(obj, pg_buf, -+ pg->index << PAGE_CACHE_SHIFT, PAGE_CACHE_SIZE); -+ -+ yaffs_gross_unlock(dev); -+ -+ if (ret >= 0) -+ ret = 0; -+ -+ if (ret) { -+ ClearPageUptodate(pg); -+ SetPageError(pg); -+ } else { -+ SetPageUptodate(pg); -+ ClearPageError(pg); -+ } -+ -+ flush_dcache_page(pg); -+ kunmap(pg); -+ -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_readpage_nolock done\n"))); -+ return ret; -+} -+ -+static int yaffs_readpage_unlock(struct file *f, struct page *pg) -+{ -+ int ret = yaffs_readpage_nolock(f, pg); -+ UnlockPage(pg); -+ return ret; -+} -+ -+static int yaffs_readpage(struct file *f, struct page *pg) -+{ -+ int ret; -+ -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_readpage\n"))); -+ ret = yaffs_readpage_unlock(f, pg); -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_readpage done\n"))); -+ return ret; -+} -+ -+/* writepage inspired by/stolen from smbfs */ -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) -+static int yaffs_writepage(struct page *page, struct writeback_control *wbc) -+#else -+static int yaffs_writepage(struct page *page) -+#endif -+{ -+ struct yaffs_dev *dev; -+ struct address_space *mapping = page->mapping; -+ struct inode *inode; -+ unsigned long end_index; -+ char *buffer; -+ struct yaffs_obj *obj; -+ int n_written = 0; -+ unsigned n_bytes; -+ loff_t i_size; -+ -+ if (!mapping) -+ BUG(); -+ inode = mapping->host; -+ if (!inode) -+ BUG(); -+ i_size = i_size_read(inode); -+ -+ end_index = i_size >> PAGE_CACHE_SHIFT; -+ -+ if (page->index < end_index) -+ n_bytes = PAGE_CACHE_SIZE; -+ else { -+ n_bytes = i_size & (PAGE_CACHE_SIZE - 1); -+ -+ if (page->index > end_index || !n_bytes) { -+ T(YAFFS_TRACE_OS, -+ (TSTR -+ ("yaffs_writepage at %08x, inode size = %08x!!!\n"), -+ (unsigned)(page->index << PAGE_CACHE_SHIFT), -+ (unsigned)inode->i_size)); -+ T(YAFFS_TRACE_OS, -+ (TSTR(" -> don't care!!\n"))); -+ -+ zero_user_segment(page, 0, PAGE_CACHE_SIZE); -+ set_page_writeback(page); -+ unlock_page(page); -+ end_page_writeback(page); -+ return 0; -+ } -+ } -+ -+ if (n_bytes != PAGE_CACHE_SIZE) -+ zero_user_segment(page, n_bytes, PAGE_CACHE_SIZE); -+ -+ get_page(page); -+ -+ buffer = kmap(page); -+ -+ obj = yaffs_inode_to_obj(inode); -+ dev = obj->my_dev; -+ yaffs_gross_lock(dev); -+ -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_writepage at %08x, size %08x\n"), -+ (unsigned)(page->index << PAGE_CACHE_SHIFT), n_bytes)); -+ T(YAFFS_TRACE_OS, -+ (TSTR("writepag0: obj = %05x, ino = %05x\n"), -+ (int)obj->variant.file_variant.file_size, (int)inode->i_size)); -+ -+ n_written = yaffs_wr_file(obj, buffer, -+ page->index << PAGE_CACHE_SHIFT, n_bytes, 0); -+ -+ yaffs_touch_super(dev); -+ -+ T(YAFFS_TRACE_OS, -+ (TSTR("writepag1: obj = %05x, ino = %05x\n"), -+ (int)obj->variant.file_variant.file_size, (int)inode->i_size)); -+ -+ yaffs_gross_unlock(dev); -+ -+ kunmap(page); -+ set_page_writeback(page); -+ unlock_page(page); -+ end_page_writeback(page); -+ put_page(page); -+ -+ return (n_written == n_bytes) ? 0 : -ENOSPC; -+} -+ -+#if (YAFFS_USE_WRITE_BEGIN_END > 0) -+static int yaffs_write_begin(struct file *filp, struct address_space *mapping, -+ loff_t pos, unsigned len, unsigned flags, -+ struct page **pagep, void **fsdata) -+{ -+ struct page *pg = NULL; -+ pgoff_t index = pos >> PAGE_CACHE_SHIFT; -+ -+ int ret = 0; -+ int space_held = 0; -+ -+ /* Get a page */ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 28) -+ pg = grab_cache_page_write_begin(mapping, index, flags); -+#else -+ pg = __grab_cache_page(mapping, index); -+#endif -+ -+ *pagep = pg; -+ if (!pg) { -+ ret = -ENOMEM; -+ goto out; -+ } -+ T(YAFFS_TRACE_OS, -+ (TSTR("start yaffs_write_begin index %d(%x) uptodate %d\n"), -+ (int)index, (int)index, Page_Uptodate(pg) ? 1 : 0)); -+ -+ /* Get fs space */ -+ space_held = yaffs_hold_space(filp); -+ -+ if (!space_held) { -+ ret = -ENOSPC; -+ goto out; -+ } -+ -+ /* Update page if required */ -+ -+ if (!Page_Uptodate(pg)) -+ ret = yaffs_readpage_nolock(filp, pg); -+ -+ if (ret) -+ goto out; -+ -+ /* Happy path return */ -+ T(YAFFS_TRACE_OS, (TSTR("end yaffs_write_begin - ok\n"))); -+ -+ return 0; -+ -+out: -+ T(YAFFS_TRACE_OS, -+ (TSTR("end yaffs_write_begin fail returning %d\n"), ret)); -+ if (space_held) -+ yaffs_release_space(filp); -+ if (pg) { -+ unlock_page(pg); -+ page_cache_release(pg); -+ } -+ return ret; -+} -+ -+#else -+ -+static int yaffs_prepare_write(struct file *f, struct page *pg, -+ unsigned offset, unsigned to) -+{ -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_prepair_write\n"))); -+ -+ if (!Page_Uptodate(pg)) -+ return yaffs_readpage_nolock(f, pg); -+ return 0; -+} -+#endif -+ -+#if (YAFFS_USE_WRITE_BEGIN_END > 0) -+static int yaffs_write_end(struct file *filp, struct address_space *mapping, -+ loff_t pos, unsigned len, unsigned copied, -+ struct page *pg, void *fsdadata) -+{ -+ int ret = 0; -+ void *addr, *kva; -+ uint32_t offset_into_page = pos & (PAGE_CACHE_SIZE - 1); -+ -+ kva = kmap(pg); -+ addr = kva + offset_into_page; -+ -+ T(YAFFS_TRACE_OS, -+ ("yaffs_write_end addr %p pos %x n_bytes %d\n", -+ addr, (unsigned)pos, copied)); -+ -+ ret = yaffs_file_write(filp, addr, copied, &pos); -+ -+ if (ret != copied) { -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_write_end not same size ret %d copied %d\n"), -+ ret, copied)); -+ SetPageError(pg); -+ } else { -+ /* Nothing */ -+ } -+ -+ kunmap(pg); -+ -+ yaffs_release_space(filp); -+ unlock_page(pg); -+ page_cache_release(pg); -+ return ret; -+} -+#else -+ -+static int yaffs_commit_write(struct file *f, struct page *pg, unsigned offset, -+ unsigned to) -+{ -+ void *addr, *kva; -+ -+ loff_t pos = (((loff_t) pg->index) << PAGE_CACHE_SHIFT) + offset; -+ int n_bytes = to - offset; -+ int n_written; -+ -+ unsigned spos = pos; -+ unsigned saddr; -+ -+ kva = kmap(pg); -+ addr = kva + offset; -+ -+ saddr = (unsigned)addr; -+ -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_commit_write addr %x pos %x n_bytes %d\n"), -+ saddr, spos, n_bytes)); -+ -+ n_written = yaffs_file_write(f, addr, n_bytes, &pos); -+ -+ if (n_written != n_bytes) { -+ T(YAFFS_TRACE_OS, -+ (TSTR -+ ("yaffs_commit_write not same size n_written %d n_bytes %d\n"), -+ n_written, n_bytes)); -+ SetPageError(pg); -+ } else { -+ /* Nothing */ -+ } -+ -+ kunmap(pg); -+ -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_commit_write returning %d\n"), -+ n_written == n_bytes ? 0 : n_written)); -+ -+ return n_written == n_bytes ? 0 : n_written; -+} -+#endif -+ -+static void yaffs_fill_inode_from_obj(struct inode *inode, -+ struct yaffs_obj *obj) -+{ -+ if (inode && obj) { -+ -+ /* Check mode against the variant type and attempt to repair if broken. */ -+ u32 mode = obj->yst_mode; -+ switch (obj->variant_type) { -+ case YAFFS_OBJECT_TYPE_FILE: -+ if (!S_ISREG(mode)) { -+ obj->yst_mode &= ~S_IFMT; -+ obj->yst_mode |= S_IFREG; -+ } -+ -+ break; -+ case YAFFS_OBJECT_TYPE_SYMLINK: -+ if (!S_ISLNK(mode)) { -+ obj->yst_mode &= ~S_IFMT; -+ obj->yst_mode |= S_IFLNK; -+ } -+ -+ break; -+ case YAFFS_OBJECT_TYPE_DIRECTORY: -+ if (!S_ISDIR(mode)) { -+ obj->yst_mode &= ~S_IFMT; -+ obj->yst_mode |= S_IFDIR; -+ } -+ -+ break; -+ case YAFFS_OBJECT_TYPE_UNKNOWN: -+ case YAFFS_OBJECT_TYPE_HARDLINK: -+ case YAFFS_OBJECT_TYPE_SPECIAL: -+ default: -+ /* TODO? */ -+ break; -+ } -+ -+ inode->i_flags |= S_NOATIME; -+ -+ inode->i_ino = obj->obj_id; -+ inode->i_mode = obj->yst_mode; -+ inode->i_uid = obj->yst_uid; -+ inode->i_gid = obj->yst_gid; -+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19)) -+ inode->i_blksize = inode->i_sb->s_blocksize; -+#endif -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) -+ -+ inode->i_rdev = old_decode_dev(obj->yst_rdev); -+ inode->i_atime.tv_sec = (time_t) (obj->yst_atime); -+ inode->i_atime.tv_nsec = 0; -+ inode->i_mtime.tv_sec = (time_t) obj->yst_mtime; -+ inode->i_mtime.tv_nsec = 0; -+ inode->i_ctime.tv_sec = (time_t) obj->yst_ctime; -+ inode->i_ctime.tv_nsec = 0; -+#else -+ inode->i_rdev = obj->yst_rdev; -+ inode->i_atime = obj->yst_atime; -+ inode->i_mtime = obj->yst_mtime; -+ inode->i_ctime = obj->yst_ctime; -+#endif -+ inode->i_size = yaffs_get_obj_length(obj); -+ inode->i_blocks = (inode->i_size + 511) >> 9; -+ -+ inode->i_nlink = yaffs_get_obj_link_count(obj); -+ -+ T(YAFFS_TRACE_OS, -+ (TSTR -+ ("yaffs_fill_inode mode %x uid %d gid %d size %d count %d\n"), -+ inode->i_mode, inode->i_uid, inode->i_gid, -+ (int)inode->i_size, atomic_read(&inode->i_count))); -+ -+ switch (obj->yst_mode & S_IFMT) { -+ default: /* fifo, device or socket */ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) -+ init_special_inode(inode, obj->yst_mode, -+ old_decode_dev(obj->yst_rdev)); -+#else -+ init_special_inode(inode, obj->yst_mode, -+ (dev_t) (obj->yst_rdev)); -+#endif -+ break; -+ case S_IFREG: /* file */ -+ inode->i_op = &yaffs_file_inode_operations; -+ inode->i_fop = &yaffs_file_operations; -+ inode->i_mapping->a_ops = -+ &yaffs_file_address_operations; -+ break; -+ case S_IFDIR: /* directory */ -+ inode->i_op = &yaffs_dir_inode_operations; -+ inode->i_fop = &yaffs_dir_operations; -+ break; -+ case S_IFLNK: /* symlink */ -+ inode->i_op = &yaffs_symlink_inode_operations; -+ break; -+ } -+ -+ yaffs_inode_to_obj_lv(inode) = obj; -+ -+ obj->my_inode = inode; -+ -+ } else { -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_fill_inode invalid parameters\n"))); -+ } -+ -+} -+ -+struct inode *yaffs_get_inode(struct super_block *sb, int mode, int dev, -+ struct yaffs_obj *obj) -+{ -+ struct inode *inode; -+ -+ if (!sb) { -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_get_inode for NULL super_block!!\n"))); -+ return NULL; -+ -+ } -+ -+ if (!obj) { -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_get_inode for NULL object!!\n"))); -+ return NULL; -+ -+ } -+ -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_get_inode for object %d\n"), obj->obj_id)); -+ -+ inode = Y_IGET(sb, obj->obj_id); -+ if (IS_ERR(inode)) -+ return NULL; -+ -+ /* NB Side effect: iget calls back to yaffs_read_inode(). */ -+ /* iget also increments the inode's i_count */ -+ /* NB You can't be holding gross_lock or deadlock will happen! */ -+ -+ return inode; -+} -+ -+static ssize_t yaffs_file_write(struct file *f, const char *buf, size_t n, -+ loff_t * pos) -+{ -+ struct yaffs_obj *obj; -+ int n_written, ipos; -+ struct inode *inode; -+ struct yaffs_dev *dev; -+ -+ obj = yaffs_dentry_to_obj(f->f_dentry); -+ -+ dev = obj->my_dev; -+ -+ yaffs_gross_lock(dev); -+ -+ inode = f->f_dentry->d_inode; -+ -+ if (!S_ISBLK(inode->i_mode) && f->f_flags & O_APPEND) -+ ipos = inode->i_size; -+ else -+ ipos = *pos; -+ -+ if (!obj) -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_file_write: hey obj is null!\n"))); -+ else -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_file_write about to write writing %u(%x) bytes" -+ "to object %d at %d(%x)\n"), -+ (unsigned)n, (unsigned)n, obj->obj_id, ipos, ipos)); -+ -+ n_written = yaffs_wr_file(obj, buf, ipos, n, 0); -+ -+ yaffs_touch_super(dev); -+ -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_file_write: %d(%x) bytes written\n"), -+ (unsigned)n, (unsigned)n)); -+ -+ if (n_written > 0) { -+ ipos += n_written; -+ *pos = ipos; -+ if (ipos > inode->i_size) { -+ inode->i_size = ipos; -+ inode->i_blocks = (ipos + 511) >> 9; -+ -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_file_write size updated to %d bytes, " -+ "%d blocks\n"), ipos, (int)(inode->i_blocks))); -+ } -+ -+ } -+ yaffs_gross_unlock(dev); -+ return (n_written == 0) && (n > 0) ? -ENOSPC : n_written; -+} -+ -+/* Space holding and freeing is done to ensure we have space available for write_begin/end */ -+/* For now we just assume few parallel writes and check against a small number. */ -+/* Todo: need to do this with a counter to handle parallel reads better */ -+ -+static ssize_t yaffs_hold_space(struct file *f) -+{ -+ struct yaffs_obj *obj; -+ struct yaffs_dev *dev; -+ -+ int n_free_chunks; -+ -+ obj = yaffs_dentry_to_obj(f->f_dentry); -+ -+ dev = obj->my_dev; -+ -+ yaffs_gross_lock(dev); -+ -+ n_free_chunks = yaffs_get_n_free_chunks(dev); -+ -+ yaffs_gross_unlock(dev); -+ -+ return (n_free_chunks > 20) ? 1 : 0; -+} -+ -+static void yaffs_release_space(struct file *f) -+{ -+ struct yaffs_obj *obj; -+ struct yaffs_dev *dev; -+ -+ obj = yaffs_dentry_to_obj(f->f_dentry); -+ -+ dev = obj->my_dev; -+ -+ yaffs_gross_lock(dev); -+ -+ yaffs_gross_unlock(dev); -+} -+ -+static loff_t yaffs_dir_llseek(struct file *file, loff_t offset, int origin) -+{ -+ long long retval; -+ -+ lock_kernel(); -+ -+ switch (origin) { -+ case 2: -+ offset += i_size_read(file->f_path.dentry->d_inode); -+ break; -+ case 1: -+ offset += file->f_pos; -+ } -+ retval = -EINVAL; -+ -+ if (offset >= 0) { -+ if (offset != file->f_pos) -+ file->f_pos = offset; -+ -+ retval = offset; -+ } -+ unlock_kernel(); -+ return retval; -+} -+ -+static int yaffs_readdir(struct file *f, void *dirent, filldir_t filldir) -+{ -+ struct yaffs_obj *obj; -+ struct yaffs_dev *dev; -+ struct yaffs_search_context *sc; -+ struct inode *inode = f->f_dentry->d_inode; -+ unsigned long offset, curoffs; -+ struct yaffs_obj *l; -+ int ret_val = 0; -+ -+ char name[YAFFS_MAX_NAME_LENGTH + 1]; -+ -+ obj = yaffs_dentry_to_obj(f->f_dentry); -+ dev = obj->my_dev; -+ -+ yaffs_gross_lock(dev); -+ -+ yaffs_dev_to_lc(dev)->readdir_process = current; -+ -+ offset = f->f_pos; -+ -+ sc = yaffs_new_search(obj); -+ if (!sc) { -+ ret_val = -ENOMEM; -+ goto out; -+ } -+ -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_readdir: starting at %d\n"), (int)offset)); -+ -+ if (offset == 0) { -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_readdir: entry . ino %d \n"), -+ (int)inode->i_ino)); -+ yaffs_gross_unlock(dev); -+ if (filldir(dirent, ".", 1, offset, inode->i_ino, DT_DIR) < 0) { -+ yaffs_gross_lock(dev); -+ goto out; -+ } -+ yaffs_gross_lock(dev); -+ offset++; -+ f->f_pos++; -+ } -+ if (offset == 1) { -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_readdir: entry .. ino %d \n"), -+ (int)f->f_dentry->d_parent->d_inode->i_ino)); -+ yaffs_gross_unlock(dev); -+ if (filldir(dirent, "..", 2, offset, -+ f->f_dentry->d_parent->d_inode->i_ino, -+ DT_DIR) < 0) { -+ yaffs_gross_lock(dev); -+ goto out; -+ } -+ yaffs_gross_lock(dev); -+ offset++; -+ f->f_pos++; -+ } -+ -+ curoffs = 1; -+ -+ /* If the directory has changed since the open or last call to -+ readdir, rewind to after the 2 canned entries. */ -+ if (f->f_version != inode->i_version) { -+ offset = 2; -+ f->f_pos = offset; -+ f->f_version = inode->i_version; -+ } -+ -+ while (sc->next_return) { -+ curoffs++; -+ l = sc->next_return; -+ if (curoffs >= offset) { -+ int this_inode = yaffs_get_obj_inode(l); -+ int this_type = yaffs_get_obj_type(l); -+ -+ yaffs_get_obj_name(l, name, YAFFS_MAX_NAME_LENGTH + 1); -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_readdir: %s inode %d\n"), -+ name, yaffs_get_obj_inode(l))); -+ -+ yaffs_gross_unlock(dev); -+ -+ if (filldir(dirent, -+ name, -+ strlen(name), -+ offset, this_inode, this_type) < 0) { -+ yaffs_gross_lock(dev); -+ goto out; -+ } -+ -+ yaffs_gross_lock(dev); -+ -+ offset++; -+ f->f_pos++; -+ } -+ yaffs_search_advance(sc); -+ } -+ -+out: -+ yaffs_search_end(sc); -+ yaffs_dev_to_lc(dev)->readdir_process = NULL; -+ yaffs_gross_unlock(dev); -+ -+ return ret_val; -+} -+ -+/* -+ * File creation. Allocate an inode, and we're done.. -+ */ -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 29) -+#define YCRED(x) x -+#else -+#define YCRED(x) (x->cred) -+#endif -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) -+static int yaffs_mknod(struct inode *dir, struct dentry *dentry, int mode, -+ dev_t rdev) -+#else -+static int yaffs_mknod(struct inode *dir, struct dentry *dentry, int mode, -+ int rdev) -+#endif -+{ -+ struct inode *inode; -+ -+ struct yaffs_obj *obj = NULL; -+ struct yaffs_dev *dev; -+ -+ struct yaffs_obj *parent = yaffs_inode_to_obj(dir); -+ -+ int error = -ENOSPC; -+ uid_t uid = YCRED(current)->fsuid; -+ gid_t gid = -+ (dir->i_mode & S_ISGID) ? dir->i_gid : YCRED(current)->fsgid; -+ -+ if ((dir->i_mode & S_ISGID) && S_ISDIR(mode)) -+ mode |= S_ISGID; -+ -+ if (parent) { -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_mknod: parent object %d type %d\n"), -+ parent->obj_id, parent->variant_type)); -+ } else { -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_mknod: could not get parent object\n"))); -+ return -EPERM; -+ } -+ -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_mknod: making oject for %s, " -+ "mode %x dev %x\n"), -+ dentry->d_name.name, mode, rdev)); -+ -+ dev = parent->my_dev; -+ -+ yaffs_gross_lock(dev); -+ -+ switch (mode & S_IFMT) { -+ default: -+ /* Special (socket, fifo, device...) */ -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_mknod: making special\n"))); -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) -+ obj = -+ yaffs_create_special(parent, dentry->d_name.name, mode, uid, -+ gid, old_encode_dev(rdev)); -+#else -+ obj = -+ yaffs_create_special(parent, dentry->d_name.name, mode, uid, -+ gid, rdev); -+#endif -+ break; -+ case S_IFREG: /* file */ -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_mknod: making file\n"))); -+ obj = yaffs_create_file(parent, dentry->d_name.name, mode, uid, -+ gid); -+ break; -+ case S_IFDIR: /* directory */ -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_mknod: making directory\n"))); -+ obj = yaffs_create_dir(parent, dentry->d_name.name, mode, -+ uid, gid); -+ break; -+ case S_IFLNK: /* symlink */ -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_mknod: making symlink\n"))); -+ obj = NULL; /* Do we ever get here? */ -+ break; -+ } -+ -+ /* Can not call yaffs_get_inode() with gross lock held */ -+ yaffs_gross_unlock(dev); -+ -+ if (obj) { -+ inode = yaffs_get_inode(dir->i_sb, mode, rdev, obj); -+ d_instantiate(dentry, inode); -+ update_dir_time(dir); -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_mknod created object %d count = %d\n"), -+ obj->obj_id, atomic_read(&inode->i_count))); -+ error = 0; -+ yaffs_fill_inode_from_obj(dir, parent); -+ } else { -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_mknod failed making object\n"))); -+ error = -ENOMEM; -+ } -+ -+ return error; -+} -+ -+static int yaffs_mkdir(struct inode *dir, struct dentry *dentry, int mode) -+{ -+ int ret_val; -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_mkdir\n"))); -+ ret_val = yaffs_mknod(dir, dentry, mode | S_IFDIR, 0); -+ return ret_val; -+} -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) -+static int yaffs_create(struct inode *dir, struct dentry *dentry, int mode, -+ struct nameidata *n) -+#else -+static int yaffs_create(struct inode *dir, struct dentry *dentry, int mode) -+#endif -+{ -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_create\n"))); -+ return yaffs_mknod(dir, dentry, mode | S_IFREG, 0); -+} -+ -+static int yaffs_unlink(struct inode *dir, struct dentry *dentry) -+{ -+ int ret_val; -+ -+ struct yaffs_dev *dev; -+ struct yaffs_obj *obj; -+ -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_unlink %d:%s\n"), -+ (int)(dir->i_ino), dentry->d_name.name)); -+ obj = yaffs_inode_to_obj(dir); -+ dev = obj->my_dev; -+ -+ yaffs_gross_lock(dev); -+ -+ ret_val = yaffs_unlinker(obj, dentry->d_name.name); -+ -+ if (ret_val == YAFFS_OK) { -+ dentry->d_inode->i_nlink--; -+ dir->i_version++; -+ yaffs_gross_unlock(dev); -+ mark_inode_dirty(dentry->d_inode); -+ update_dir_time(dir); -+ return 0; -+ } -+ yaffs_gross_unlock(dev); -+ return -ENOTEMPTY; -+} -+ -+/* -+ * Create a link... -+ */ -+static int yaffs_link(struct dentry *old_dentry, struct inode *dir, -+ struct dentry *dentry) -+{ -+ struct inode *inode = old_dentry->d_inode; -+ struct yaffs_obj *obj = NULL; -+ struct yaffs_obj *link = NULL; -+ struct yaffs_dev *dev; -+ -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_link\n"))); -+ -+ obj = yaffs_inode_to_obj(inode); -+ dev = obj->my_dev; -+ -+ yaffs_gross_lock(dev); -+ -+ if (!S_ISDIR(inode->i_mode)) /* Don't link directories */ -+ link = -+ yaffs_link_obj(yaffs_inode_to_obj(dir), dentry->d_name.name, -+ obj); -+ -+ if (link) { -+ old_dentry->d_inode->i_nlink = yaffs_get_obj_link_count(obj); -+ d_instantiate(dentry, old_dentry->d_inode); -+ atomic_inc(&old_dentry->d_inode->i_count); -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_link link count %d i_count %d\n"), -+ old_dentry->d_inode->i_nlink, -+ atomic_read(&old_dentry->d_inode->i_count))); -+ } -+ -+ yaffs_gross_unlock(dev); -+ -+ if (link) { -+ update_dir_time(dir); -+ return 0; -+ } -+ -+ return -EPERM; -+} -+ -+static int yaffs_symlink(struct inode *dir, struct dentry *dentry, -+ const char *symname) -+{ -+ struct yaffs_obj *obj; -+ struct yaffs_dev *dev; -+ uid_t uid = YCRED(current)->fsuid; -+ gid_t gid = -+ (dir->i_mode & S_ISGID) ? dir->i_gid : YCRED(current)->fsgid; -+ -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_symlink\n"))); -+ -+ dev = yaffs_inode_to_obj(dir)->my_dev; -+ yaffs_gross_lock(dev); -+ obj = yaffs_create_symlink(yaffs_inode_to_obj(dir), dentry->d_name.name, -+ S_IFLNK | S_IRWXUGO, uid, gid, symname); -+ yaffs_gross_unlock(dev); -+ -+ if (obj) { -+ struct inode *inode; -+ -+ inode = yaffs_get_inode(dir->i_sb, obj->yst_mode, 0, obj); -+ d_instantiate(dentry, inode); -+ update_dir_time(dir); -+ T(YAFFS_TRACE_OS, (TSTR("symlink created OK\n"))); -+ return 0; -+ } else { -+ T(YAFFS_TRACE_OS, (TSTR("symlink not created\n"))); -+ } -+ -+ return -ENOMEM; -+} -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 34)) -+static int yaffs_sync_object(struct file *file, int datasync) -+#else -+static int yaffs_sync_object(struct file *file, struct dentry *dentry, -+ int datasync) -+#endif -+{ -+ -+ struct yaffs_obj *obj; -+ struct yaffs_dev *dev; -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 34)) -+ struct dentry *dentry = file->f_path.dentry; -+#endif -+ -+ obj = yaffs_dentry_to_obj(dentry); -+ -+ dev = obj->my_dev; -+ -+ T(YAFFS_TRACE_OS | YAFFS_TRACE_SYNC, (TSTR("yaffs_sync_object\n"))); -+ yaffs_gross_lock(dev); -+ yaffs_flush_file(obj, 1, datasync); -+ yaffs_gross_unlock(dev); -+ return 0; -+} -+ -+/* -+ * The VFS layer already does all the dentry stuff for rename. -+ * -+ * NB: POSIX says you can rename an object over an old object of the same name -+ */ -+static int yaffs_rename(struct inode *old_dir, struct dentry *old_dentry, -+ struct inode *new_dir, struct dentry *new_dentry) -+{ -+ struct yaffs_dev *dev; -+ int ret_val = YAFFS_FAIL; -+ struct yaffs_obj *target; -+ -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_rename\n"))); -+ dev = yaffs_inode_to_obj(old_dir)->my_dev; -+ -+ yaffs_gross_lock(dev); -+ -+ /* Check if the target is an existing directory that is not empty. */ -+ target = yaffs_find_by_name(yaffs_inode_to_obj(new_dir), -+ new_dentry->d_name.name); -+ -+ if (target && target->variant_type == YAFFS_OBJECT_TYPE_DIRECTORY && -+ !list_empty(&target->variant.dir_variant.children)) { -+ -+ T(YAFFS_TRACE_OS, (TSTR("target is non-empty dir\n"))); -+ -+ ret_val = YAFFS_FAIL; -+ } else { -+ /* Now does unlinking internally using shadowing mechanism */ -+ T(YAFFS_TRACE_OS, (TSTR("calling yaffs_rename_obj\n"))); -+ -+ ret_val = yaffs_rename_obj(yaffs_inode_to_obj(old_dir), -+ old_dentry->d_name.name, -+ yaffs_inode_to_obj(new_dir), -+ new_dentry->d_name.name); -+ } -+ yaffs_gross_unlock(dev); -+ -+ if (ret_val == YAFFS_OK) { -+ if (target) { -+ new_dentry->d_inode->i_nlink--; -+ mark_inode_dirty(new_dentry->d_inode); -+ } -+ -+ update_dir_time(old_dir); -+ if (old_dir != new_dir) -+ update_dir_time(new_dir); -+ return 0; -+ } else { -+ return -ENOTEMPTY; -+ } -+} -+ -+static int yaffs_setattr(struct dentry *dentry, struct iattr *attr) -+{ -+ struct inode *inode = dentry->d_inode; -+ int error = 0; -+ struct yaffs_dev *dev; -+ -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_setattr of object %d\n"), -+ yaffs_inode_to_obj(inode)->obj_id)); -+ -+ /* Fail if a requested resize >= 2GB */ -+ if (attr->ia_valid & ATTR_SIZE && (attr->ia_size >> 31)) -+ error = -EINVAL; -+ -+ if (error == 0) -+ error = inode_change_ok(inode, attr); -+ if (error == 0) { -+ int result; -+ if (!error) { -+ error = yaffs_vfs_setattr(inode, attr); -+ T(YAFFS_TRACE_OS, (TSTR("inode_setattr called\n"))); -+ if (attr->ia_valid & ATTR_SIZE) { -+ yaffs_vfs_setsize(inode, attr->ia_size); -+ inode->i_blocks = (inode->i_size + 511) >> 9; -+ } -+ } -+ dev = yaffs_inode_to_obj(inode)->my_dev; -+ if (attr->ia_valid & ATTR_SIZE) { -+ T(YAFFS_TRACE_OS, (TSTR("resize to %d(%x)\n"), -+ (int)(attr->ia_size), -+ (int)(attr->ia_size))); -+ } -+ yaffs_gross_lock(dev); -+ result = yaffs_set_attribs(yaffs_inode_to_obj(inode), attr); -+ if (result == YAFFS_OK) { -+ error = 0; -+ } else { -+ error = -EPERM; -+ } -+ yaffs_gross_unlock(dev); -+ -+ } -+ -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_setattr done returning %d\n"), error)); -+ -+ return error; -+} -+ -+#ifdef CONFIG_YAFFS_XATTR -+int yaffs_setxattr(struct dentry *dentry, const char *name, -+ const void *value, size_t size, int flags) -+{ -+ struct inode *inode = dentry->d_inode; -+ int error = 0; -+ struct yaffs_dev *dev; -+ struct yaffs_obj *obj = yaffs_inode_to_obj(inode); -+ -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_setxattr of object %d\n"), obj->obj_id)); -+ -+ if (error == 0) { -+ int result; -+ dev = obj->my_dev; -+ yaffs_gross_lock(dev); -+ result = yaffs_set_xattrib(obj, name, value, size, flags); -+ if (result == YAFFS_OK) -+ error = 0; -+ else if (result < 0) -+ error = result; -+ yaffs_gross_unlock(dev); -+ -+ } -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_setxattr done returning %d\n"), error)); -+ -+ return error; -+} -+ -+ssize_t yaffs_getxattr(struct dentry * dentry, const char *name, void *buff, -+ size_t size) -+{ -+ struct inode *inode = dentry->d_inode; -+ int error = 0; -+ struct yaffs_dev *dev; -+ struct yaffs_obj *obj = yaffs_inode_to_obj(inode); -+ -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_getxattr \"%s\" from object %d\n"), name, obj->obj_id)); -+ -+ if (error == 0) { -+ dev = obj->my_dev; -+ yaffs_gross_lock(dev); -+ error = yaffs_get_xattrib(obj, name, buff, size); -+ yaffs_gross_unlock(dev); -+ -+ } -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_getxattr done returning %d\n"), error)); -+ -+ return error; -+} -+ -+int yaffs_removexattr(struct dentry *dentry, const char *name) -+{ -+ struct inode *inode = dentry->d_inode; -+ int error = 0; -+ struct yaffs_dev *dev; -+ struct yaffs_obj *obj = yaffs_inode_to_obj(inode); -+ -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_removexattr of object %d\n"), obj->obj_id)); -+ -+ if (error == 0) { -+ int result; -+ dev = obj->my_dev; -+ yaffs_gross_lock(dev); -+ result = yaffs_remove_xattrib(obj, name); -+ if (result == YAFFS_OK) -+ error = 0; -+ else if (result < 0) -+ error = result; -+ yaffs_gross_unlock(dev); -+ -+ } -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_removexattr done returning %d\n"), error)); -+ -+ return error; -+} -+ -+ssize_t yaffs_listxattr(struct dentry * dentry, char *buff, size_t size) -+{ -+ struct inode *inode = dentry->d_inode; -+ int error = 0; -+ struct yaffs_dev *dev; -+ struct yaffs_obj *obj = yaffs_inode_to_obj(inode); -+ -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_listxattr of object %d\n"), obj->obj_id)); -+ -+ if (error == 0) { -+ dev = obj->my_dev; -+ yaffs_gross_lock(dev); -+ error = yaffs_list_xattrib(obj, buff, size); -+ yaffs_gross_unlock(dev); -+ -+ } -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_listxattr done returning %d\n"), error)); -+ -+ return error; -+} -+ -+#endif -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17)) -+static int yaffs_statfs(struct dentry *dentry, struct kstatfs *buf) -+{ -+ struct yaffs_dev *dev = yaffs_dentry_to_obj(dentry)->my_dev; -+ struct super_block *sb = dentry->d_sb; -+#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) -+static int yaffs_statfs(struct super_block *sb, struct kstatfs *buf) -+{ -+ struct yaffs_dev *dev = yaffs_super_to_dev(sb); -+#else -+static int yaffs_statfs(struct super_block *sb, struct statfs *buf) -+{ -+ struct yaffs_dev *dev = yaffs_super_to_dev(sb); -+#endif -+ -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_statfs\n"))); -+ -+ yaffs_gross_lock(dev); -+ -+ buf->f_type = YAFFS_MAGIC; -+ buf->f_bsize = sb->s_blocksize; -+ buf->f_namelen = 255; -+ -+ if (dev->data_bytes_per_chunk & (dev->data_bytes_per_chunk - 1)) { -+ /* Do this if chunk size is not a power of 2 */ -+ -+ uint64_t bytes_in_dev; -+ uint64_t bytes_free; -+ -+ bytes_in_dev = -+ ((uint64_t) -+ ((dev->param.end_block - dev->param.start_block + -+ 1))) * ((uint64_t) (dev->param.chunks_per_block * -+ dev->data_bytes_per_chunk)); -+ -+ do_div(bytes_in_dev, sb->s_blocksize); /* bytes_in_dev becomes the number of blocks */ -+ buf->f_blocks = bytes_in_dev; -+ -+ bytes_free = ((uint64_t) (yaffs_get_n_free_chunks(dev))) * -+ ((uint64_t) (dev->data_bytes_per_chunk)); -+ -+ do_div(bytes_free, sb->s_blocksize); -+ -+ buf->f_bfree = bytes_free; -+ -+ } else if (sb->s_blocksize > dev->data_bytes_per_chunk) { -+ -+ buf->f_blocks = -+ (dev->param.end_block - dev->param.start_block + 1) * -+ dev->param.chunks_per_block / -+ (sb->s_blocksize / dev->data_bytes_per_chunk); -+ buf->f_bfree = -+ yaffs_get_n_free_chunks(dev) / -+ (sb->s_blocksize / dev->data_bytes_per_chunk); -+ } else { -+ buf->f_blocks = -+ (dev->param.end_block - dev->param.start_block + 1) * -+ dev->param.chunks_per_block * -+ (dev->data_bytes_per_chunk / sb->s_blocksize); -+ -+ buf->f_bfree = -+ yaffs_get_n_free_chunks(dev) * -+ (dev->data_bytes_per_chunk / sb->s_blocksize); -+ } -+ -+ buf->f_files = 0; -+ buf->f_ffree = 0; -+ buf->f_bavail = buf->f_bfree; -+ -+ yaffs_gross_unlock(dev); -+ return 0; -+} -+ -+static void yaffs_flush_inodes(struct super_block *sb) -+{ -+ struct inode *iptr; -+ struct yaffs_obj *obj; -+ -+ list_for_each_entry(iptr, &sb->s_inodes, i_sb_list) { -+ obj = yaffs_inode_to_obj(iptr); -+ if (obj) { -+ T(YAFFS_TRACE_OS, (TSTR("flushing obj %d\n"), -+ obj->obj_id)); -+ yaffs_flush_file(obj, 1, 0); -+ } -+ } -+} -+ -+static void yaffs_flush_super(struct super_block *sb, int do_checkpoint) -+{ -+ struct yaffs_dev *dev = yaffs_super_to_dev(sb); -+ if (!dev) -+ return; -+ -+ yaffs_flush_inodes(sb); -+ yaffs_update_dirty_dirs(dev); -+ yaffs_flush_whole_cache(dev); -+ if (do_checkpoint) -+ yaffs_checkpoint_save(dev); -+} -+ -+static unsigned yaffs_bg_gc_urgency(struct yaffs_dev *dev) -+{ -+ unsigned erased_chunks = -+ dev->n_erased_blocks * dev->param.chunks_per_block; -+ struct yaffs_linux_context *context = yaffs_dev_to_lc(dev); -+ unsigned scattered = 0; /* Free chunks not in an erased block */ -+ -+ if (erased_chunks < dev->n_free_chunks) -+ scattered = (dev->n_free_chunks - erased_chunks); -+ -+ if (!context->bg_running) -+ return 0; -+ else if (scattered < (dev->param.chunks_per_block * 2)) -+ return 0; -+ else if (erased_chunks > dev->n_free_chunks / 2) -+ return 0; -+ else if (erased_chunks > dev->n_free_chunks / 4) -+ return 1; -+ else -+ return 2; -+} -+ -+static int yaffs_do_sync_fs(struct super_block *sb, int request_checkpoint) -+{ -+ -+ struct yaffs_dev *dev = yaffs_super_to_dev(sb); -+ unsigned int oneshot_checkpoint = (yaffs_auto_checkpoint & 4); -+ unsigned gc_urgent = yaffs_bg_gc_urgency(dev); -+ int do_checkpoint; -+ -+ T(YAFFS_TRACE_OS | YAFFS_TRACE_SYNC | YAFFS_TRACE_BACKGROUND, -+ (TSTR("yaffs_do_sync_fs: gc-urgency %d %s %s%s\n"), -+ gc_urgent, -+ sb->s_dirt ? "dirty" : "clean", -+ request_checkpoint ? "checkpoint requested" : "no checkpoint", -+ oneshot_checkpoint ? " one-shot" : "")); -+ -+ yaffs_gross_lock(dev); -+ do_checkpoint = ((request_checkpoint && !gc_urgent) || -+ oneshot_checkpoint) && !dev->is_checkpointed; -+ -+ if (sb->s_dirt || do_checkpoint) { -+ yaffs_flush_super(sb, !dev->is_checkpointed && do_checkpoint); -+ sb->s_dirt = 0; -+ if (oneshot_checkpoint) -+ yaffs_auto_checkpoint &= ~4; -+ } -+ yaffs_gross_unlock(dev); -+ -+ return 0; -+} -+ -+/* -+ * yaffs background thread functions . -+ * yaffs_bg_thread_fn() the thread function -+ * yaffs_bg_start() launches the background thread. -+ * yaffs_bg_stop() cleans up the background thread. -+ * -+ * NB: -+ * The thread should only run after the yaffs is initialised -+ * The thread should be stopped before yaffs is unmounted. -+ * The thread should not do any writing while the fs is in read only. -+ */ -+ -+#ifdef YAFFS_COMPILE_BACKGROUND -+ -+void yaffs_background_waker(unsigned long data) -+{ -+ wake_up_process((struct task_struct *)data); -+} -+ -+static int yaffs_bg_thread_fn(void *data) -+{ -+ struct yaffs_dev *dev = (struct yaffs_dev *)data; -+ struct yaffs_linux_context *context = yaffs_dev_to_lc(dev); -+ unsigned long now = jiffies; -+ unsigned long next_dir_update = now; -+ unsigned long next_gc = now; -+ unsigned long expires; -+ unsigned int urgency; -+ -+ int gc_result; -+ struct timer_list timer; -+ -+ T(YAFFS_TRACE_BACKGROUND, -+ (TSTR("yaffs_background starting for dev %p\n"), (void *)dev)); -+ -+#ifdef YAFFS_COMPILE_FREEZER -+ set_freezable(); -+#endif -+ while (context->bg_running) { -+ T(YAFFS_TRACE_BACKGROUND, (TSTR("yaffs_background\n"))); -+ -+ if (kthread_should_stop()) -+ break; -+ -+#ifdef YAFFS_COMPILE_FREEZER -+ if (try_to_freeze()) -+ continue; -+#endif -+ yaffs_gross_lock(dev); -+ -+ now = jiffies; -+ -+ if (time_after(now, next_dir_update) && yaffs_bg_enable) { -+ yaffs_update_dirty_dirs(dev); -+ next_dir_update = now + HZ; -+ } -+ -+ if (time_after(now, next_gc) && yaffs_bg_enable) { -+ if (!dev->is_checkpointed) { -+ urgency = yaffs_bg_gc_urgency(dev); -+ gc_result = yaffs_bg_gc(dev, urgency); -+ if (urgency > 1) -+ next_gc = now + HZ / 20 + 1; -+ else if (urgency > 0) -+ next_gc = now + HZ / 10 + 1; -+ else -+ next_gc = now + HZ * 2; -+ } else { -+ /* -+ * gc not running so set to next_dir_update -+ * to cut down on wake ups -+ */ -+ next_gc = next_dir_update; -+ } -+ } -+ yaffs_gross_unlock(dev); -+#if 1 -+ expires = next_dir_update; -+ if (time_before(next_gc, expires)) -+ expires = next_gc; -+ if (time_before(expires, now)) -+ expires = now + HZ; -+ -+ Y_INIT_TIMER(&timer); -+ timer.expires = expires + 1; -+ timer.data = (unsigned long)current; -+ timer.function = yaffs_background_waker; -+ -+ set_current_state(TASK_INTERRUPTIBLE); -+ add_timer(&timer); -+ schedule(); -+ del_timer_sync(&timer); -+#else -+ msleep(10); -+#endif -+ } -+ -+ return 0; -+} -+ -+static int yaffs_bg_start(struct yaffs_dev *dev) -+{ -+ int retval = 0; -+ struct yaffs_linux_context *context = yaffs_dev_to_lc(dev); -+ -+ if (dev->read_only) -+ return -1; -+ -+ context->bg_running = 1; -+ -+ context->bg_thread = kthread_run(yaffs_bg_thread_fn, -+ (void *)dev, "yaffs-bg-%d", -+ context->mount_id); -+ -+ if (IS_ERR(context->bg_thread)) { -+ retval = PTR_ERR(context->bg_thread); -+ context->bg_thread = NULL; -+ context->bg_running = 0; -+ } -+ return retval; -+} -+ -+static void yaffs_bg_stop(struct yaffs_dev *dev) -+{ -+ struct yaffs_linux_context *ctxt = yaffs_dev_to_lc(dev); -+ -+ ctxt->bg_running = 0; -+ -+ if (ctxt->bg_thread) { -+ kthread_stop(ctxt->bg_thread); -+ ctxt->bg_thread = NULL; -+ } -+} -+#else -+static int yaffs_bg_thread_fn(void *data) -+{ -+ return 0; -+} -+ -+static int yaffs_bg_start(struct yaffs_dev *dev) -+{ -+ return 0; -+} -+ -+static void yaffs_bg_stop(struct yaffs_dev *dev) -+{ -+} -+#endif -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17)) -+static void yaffs_write_super(struct super_block *sb) -+#else -+static int yaffs_write_super(struct super_block *sb) -+#endif -+{ -+ unsigned request_checkpoint = (yaffs_auto_checkpoint >= 2); -+ -+ T(YAFFS_TRACE_OS | YAFFS_TRACE_SYNC | YAFFS_TRACE_BACKGROUND, -+ (TSTR("yaffs_write_super%s\n"), -+ request_checkpoint ? " checkpt" : "")); -+ -+ yaffs_do_sync_fs(sb, request_checkpoint); -+ -+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)) -+ return 0; -+#endif -+} -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17)) -+static int yaffs_sync_fs(struct super_block *sb, int wait) -+#else -+static int yaffs_sync_fs(struct super_block *sb) -+#endif -+{ -+ unsigned request_checkpoint = (yaffs_auto_checkpoint >= 1); -+ -+ T(YAFFS_TRACE_OS | YAFFS_TRACE_SYNC, -+ (TSTR("yaffs_sync_fs%s\n"), request_checkpoint ? " checkpt" : "")); -+ -+ yaffs_do_sync_fs(sb, request_checkpoint); -+ -+ return 0; -+} -+ -+#ifdef YAFFS_USE_OWN_IGET -+ -+static struct inode *yaffs_iget(struct super_block *sb, unsigned long ino) -+{ -+ struct inode *inode; -+ struct yaffs_obj *obj; -+ struct yaffs_dev *dev = yaffs_super_to_dev(sb); -+ -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_iget for %lu\n"), ino)); -+ -+ inode = iget_locked(sb, ino); -+ if (!inode) -+ return ERR_PTR(-ENOMEM); -+ if (!(inode->i_state & I_NEW)) -+ return inode; -+ -+ /* NB This is called as a side effect of other functions, but -+ * we had to release the lock to prevent deadlocks, so -+ * need to lock again. -+ */ -+ -+ yaffs_gross_lock(dev); -+ -+ obj = yaffs_find_by_number(dev, inode->i_ino); -+ -+ yaffs_fill_inode_from_obj(inode, obj); -+ -+ yaffs_gross_unlock(dev); -+ -+ unlock_new_inode(inode); -+ return inode; -+} -+ -+#else -+ -+static void yaffs_read_inode(struct inode *inode) -+{ -+ /* NB This is called as a side effect of other functions, but -+ * we had to release the lock to prevent deadlocks, so -+ * need to lock again. -+ */ -+ -+ struct yaffs_obj *obj; -+ struct yaffs_dev *dev = yaffs_super_to_dev(inode->i_sb); -+ -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_read_inode for %d\n"), (int)inode->i_ino)); -+ -+ if (current != yaffs_dev_to_lc(dev)->readdir_process) -+ yaffs_gross_lock(dev); -+ -+ obj = yaffs_find_by_number(dev, inode->i_ino); -+ -+ yaffs_fill_inode_from_obj(inode, obj); -+ -+ if (current != yaffs_dev_to_lc(dev)->readdir_process) -+ yaffs_gross_unlock(dev); -+} -+ -+#endif -+ -+static LIST_HEAD(yaffs_context_list); -+struct mutex yaffs_context_lock; -+ -+static void yaffs_put_super(struct super_block *sb) -+{ -+ struct yaffs_dev *dev = yaffs_super_to_dev(sb); -+ -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_put_super\n"))); -+ -+ T(YAFFS_TRACE_OS | YAFFS_TRACE_BACKGROUND, -+ (TSTR("Shutting down yaffs background thread\n"))); -+ yaffs_bg_stop(dev); -+ T(YAFFS_TRACE_OS | YAFFS_TRACE_BACKGROUND, -+ (TSTR("yaffs background thread shut down\n"))); -+ -+ yaffs_gross_lock(dev); -+ -+ yaffs_flush_super(sb, 1); -+ -+ if (yaffs_dev_to_lc(dev)->put_super_fn) -+ yaffs_dev_to_lc(dev)->put_super_fn(sb); -+ -+ yaffs_deinitialise(dev); -+ -+ yaffs_gross_unlock(dev); -+ -+ mutex_lock(&yaffs_context_lock); -+ list_del_init(&(yaffs_dev_to_lc(dev)->context_list)); -+ mutex_unlock(&yaffs_context_lock); -+ -+ if (yaffs_dev_to_lc(dev)->spare_buffer) { -+ YFREE(yaffs_dev_to_lc(dev)->spare_buffer); -+ yaffs_dev_to_lc(dev)->spare_buffer = NULL; -+ } -+ -+ kfree(dev); -+} -+ -+static void yaffs_mtd_put_super(struct super_block *sb) -+{ -+ struct mtd_info *mtd = yaffs_dev_to_mtd(yaffs_super_to_dev(sb)); -+ -+ if (mtd->sync) -+ mtd->sync(mtd); -+ -+ put_mtd_device(mtd); -+} -+ -+static void yaffs_touch_super(struct yaffs_dev *dev) -+{ -+ struct super_block *sb = yaffs_dev_to_lc(dev)->super; -+ -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_touch_super() sb = %p\n"), sb)); -+ if (sb) -+ sb->s_dirt = 1; -+} -+ -+struct yaffs_options { -+ int inband_tags; -+ int skip_checkpoint_read; -+ int skip_checkpoint_write; -+ int no_cache; -+ int tags_ecc_on; -+ int tags_ecc_overridden; -+ int lazy_loading_enabled; -+ int lazy_loading_overridden; -+ int empty_lost_and_found; -+ int empty_lost_and_found_overridden; -+}; -+ -+#define MAX_OPT_LEN 30 -+static int yaffs_parse_options(struct yaffs_options *options, -+ const char *options_str) -+{ -+ char cur_opt[MAX_OPT_LEN + 1]; -+ int p; -+ int error = 0; -+ -+ /* Parse through the options which is a comma seperated list */ -+ -+ while (options_str && *options_str && !error) { -+ memset(cur_opt, 0, MAX_OPT_LEN + 1); -+ p = 0; -+ -+ while (*options_str == ',') -+ options_str++; -+ -+ while (*options_str && *options_str != ',') { -+ if (p < MAX_OPT_LEN) { -+ cur_opt[p] = *options_str; -+ p++; -+ } -+ options_str++; -+ } -+ -+ if (!strcmp(cur_opt, "inband-tags")) { -+ options->inband_tags = 1; -+ } else if (!strcmp(cur_opt, "tags-ecc-off")) { -+ options->tags_ecc_on = 0; -+ options->tags_ecc_overridden = 1; -+ } else if (!strcmp(cur_opt, "tags-ecc-on")) { -+ options->tags_ecc_on = 1; -+ options->tags_ecc_overridden = 1; -+ } else if (!strcmp(cur_opt, "lazy-loading-off")) { -+ options->lazy_loading_enabled = 0; -+ options->lazy_loading_overridden = 1; -+ } else if (!strcmp(cur_opt, "lazy-loading-on")) { -+ options->lazy_loading_enabled = 1; -+ options->lazy_loading_overridden = 1; -+ } else if (!strcmp(cur_opt, "empty-lost-and-found-off")) { -+ options->empty_lost_and_found = 0; -+ options->empty_lost_and_found_overridden = 1; -+ } else if (!strcmp(cur_opt, "empty-lost-and-found-on")) { -+ options->empty_lost_and_found = 1; -+ options->empty_lost_and_found_overridden = 1; -+ } else if (!strcmp(cur_opt, "no-cache")) { -+ options->no_cache = 1; -+ } else if (!strcmp(cur_opt, "no-checkpoint-read")) { -+ options->skip_checkpoint_read = 1; -+ } else if (!strcmp(cur_opt, "no-checkpoint-write")) { -+ options->skip_checkpoint_write = 1; -+ } else if (!strcmp(cur_opt, "no-checkpoint")) { -+ options->skip_checkpoint_read = 1; -+ options->skip_checkpoint_write = 1; -+ } else { -+ printk(KERN_INFO "yaffs: Bad mount option \"%s\"\n", -+ cur_opt); -+ error = 1; -+ } -+ } -+ -+ return error; -+} -+ -+static struct super_block *yaffs_internal_read_super(int yaffs_version, -+ struct super_block *sb, -+ void *data, int silent) -+{ -+ int n_blocks; -+ struct inode *inode = NULL; -+ struct dentry *root; -+ struct yaffs_dev *dev = 0; -+ char devname_buf[BDEVNAME_SIZE + 1]; -+ struct mtd_info *mtd; -+ int err; -+ char *data_str = (char *)data; -+ struct yaffs_linux_context *context = NULL; -+ struct yaffs_param *param; -+ -+ int read_only = 0; -+ -+ struct yaffs_options options; -+ -+ unsigned mount_id; -+ int found; -+ struct yaffs_linux_context *context_iterator; -+ struct list_head *l; -+ -+ sb->s_magic = YAFFS_MAGIC; -+ sb->s_op = &yaffs_super_ops; -+ sb->s_flags |= MS_NOATIME; -+ -+ read_only = ((sb->s_flags & MS_RDONLY) != 0); -+ -+#ifdef YAFFS_COMPILE_EXPORTFS -+ sb->s_export_op = &yaffs_export_ops; -+#endif -+ -+ if (!sb) -+ printk(KERN_INFO "yaffs: sb is NULL\n"); -+ else if (!sb->s_dev) -+ printk(KERN_INFO "yaffs: sb->s_dev is NULL\n"); -+ else if (!yaffs_devname(sb, devname_buf)) -+ printk(KERN_INFO "yaffs: devname is NULL\n"); -+ else -+ printk(KERN_INFO "yaffs: dev is %d name is \"%s\" %s\n", -+ sb->s_dev, -+ yaffs_devname(sb, devname_buf), read_only ? "ro" : "rw"); -+ -+ if (!data_str) -+ data_str = ""; -+ -+ printk(KERN_INFO "yaffs: passed flags \"%s\"\n", data_str); -+ -+ memset(&options, 0, sizeof(options)); -+ -+ if (yaffs_parse_options(&options, data_str)) { -+ /* Option parsing failed */ -+ return NULL; -+ } -+ -+ sb->s_blocksize = PAGE_CACHE_SIZE; -+ sb->s_blocksize_bits = PAGE_CACHE_SHIFT; -+ -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_read_super: Using yaffs%d\n"), yaffs_version)); -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_read_super: block size %d\n"), (int)(sb->s_blocksize))); -+ -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR("yaffs: Attempting MTD mount of %u.%u,\"%s\"\n"), -+ MAJOR(sb->s_dev), MINOR(sb->s_dev), yaffs_devname(sb, devname_buf))); -+ -+ /* Check it's an mtd device..... */ -+ if (MAJOR(sb->s_dev) != MTD_BLOCK_MAJOR) -+ return NULL; /* This isn't an mtd device */ -+ -+ /* Get the device */ -+ mtd = get_mtd_device(NULL, MINOR(sb->s_dev)); -+ if (!mtd) { -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR("yaffs: MTD device #%u doesn't appear to exist\n"), -+ MINOR(sb->s_dev))); -+ return NULL; -+ } -+ /* Check it's NAND */ -+ if (mtd->type != MTD_NANDFLASH) { -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR("yaffs: MTD device is not NAND it's type %d\n"), -+ mtd->type)); -+ return NULL; -+ } -+ -+ T(YAFFS_TRACE_OS, (TSTR(" erase %p\n"), mtd->erase)); -+ T(YAFFS_TRACE_OS, (TSTR(" read %p\n"), mtd->read)); -+ T(YAFFS_TRACE_OS, (TSTR(" write %p\n"), mtd->write)); -+ T(YAFFS_TRACE_OS, (TSTR(" readoob %p\n"), mtd->read_oob)); -+ T(YAFFS_TRACE_OS, (TSTR(" writeoob %p\n"), mtd->write_oob)); -+ T(YAFFS_TRACE_OS, (TSTR(" block_isbad %p\n"), mtd->block_isbad)); -+ T(YAFFS_TRACE_OS, (TSTR(" block_markbad %p\n"), mtd->block_markbad)); -+ T(YAFFS_TRACE_OS, (TSTR(" %s %d\n"), WRITE_SIZE_STR, WRITE_SIZE(mtd))); -+ T(YAFFS_TRACE_OS, (TSTR(" oobsize %d\n"), mtd->oobsize)); -+ T(YAFFS_TRACE_OS, (TSTR(" erasesize %d\n"), mtd->erasesize)); -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 29) -+ T(YAFFS_TRACE_OS, (TSTR(" size %u\n"), mtd->size)); -+#else -+ T(YAFFS_TRACE_OS, (TSTR(" size %lld\n"), mtd->size)); -+#endif -+ -+#ifdef CONFIG_YAFFS_AUTO_YAFFS2 -+ -+ if (yaffs_version == 1 && WRITE_SIZE(mtd) >= 2048) { -+ T(YAFFS_TRACE_ALWAYS, (TSTR("yaffs: auto selecting yaffs2\n"))); -+ yaffs_version = 2; -+ } -+ -+ /* Added NCB 26/5/2006 for completeness */ -+ if (yaffs_version == 2 && !options.inband_tags -+ && WRITE_SIZE(mtd) == 512) { -+ T(YAFFS_TRACE_ALWAYS, (TSTR("yaffs: auto selecting yaffs1\n"))); -+ yaffs_version = 1; -+ } -+#endif -+ -+ if (yaffs_version == 2) { -+ /* Check for version 2 style functions */ -+ if (!mtd->erase || -+ !mtd->block_isbad || -+ !mtd->block_markbad || !mtd->read || !mtd->write || -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17)) -+ !mtd->read_oob || !mtd->write_oob) { -+#else -+ !mtd->write_ecc || -+ !mtd->read_ecc || !mtd->read_oob || !mtd->write_oob) { -+#endif -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR("yaffs: MTD device does not support required " -+ "functions\n"))); -+ return NULL; -+ } -+ -+ if ((WRITE_SIZE(mtd) < YAFFS_MIN_YAFFS2_CHUNK_SIZE || -+ mtd->oobsize < YAFFS_MIN_YAFFS2_SPARE_SIZE) && -+ !options.inband_tags) { -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR("yaffs: MTD device does not have the " -+ "right page sizes\n"))); -+ return NULL; -+ } -+ } else { -+ /* Check for V1 style functions */ -+ if (!mtd->erase || !mtd->read || !mtd->write || -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17)) -+ !mtd->read_oob || !mtd->write_oob) { -+#else -+ !mtd->write_ecc || -+ !mtd->read_ecc || !mtd->read_oob || !mtd->write_oob) { -+#endif -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR("yaffs: MTD device does not support required " -+ "functions\n"))); -+ return NULL; -+ } -+ -+ if (WRITE_SIZE(mtd) < YAFFS_BYTES_PER_CHUNK || -+ mtd->oobsize != YAFFS_BYTES_PER_SPARE) { -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR("yaffs: MTD device does not support have the " -+ "right page sizes\n"))); -+ return NULL; -+ } -+ } -+ -+ /* OK, so if we got here, we have an MTD that's NAND and looks -+ * like it has the right capabilities -+ * Set the struct yaffs_dev up for mtd -+ */ -+ -+ if (!read_only && !(mtd->flags & MTD_WRITEABLE)) { -+ read_only = 1; -+ printk(KERN_INFO -+ "yaffs: mtd is read only, setting superblock read only"); -+ sb->s_flags |= MS_RDONLY; -+ } -+ -+ dev = kmalloc(sizeof(struct yaffs_dev), GFP_KERNEL); -+ context = kmalloc(sizeof(struct yaffs_linux_context), GFP_KERNEL); -+ -+ if (!dev || !context) { -+ if (dev) -+ kfree(dev); -+ if (context) -+ kfree(context); -+ dev = NULL; -+ context = NULL; -+ } -+ -+ if (!dev) { -+ /* Deep shit could not allocate device structure */ -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR("yaffs_read_super: Failed trying to allocate " -+ "struct yaffs_dev. \n"))); -+ return NULL; -+ } -+ memset(dev, 0, sizeof(struct yaffs_dev)); -+ param = &(dev->param); -+ -+ memset(context, 0, sizeof(struct yaffs_linux_context)); -+ dev->os_context = context; -+ INIT_LIST_HEAD(&(context->context_list)); -+ context->dev = dev; -+ context->super = sb; -+ -+ dev->read_only = read_only; -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) -+ sb->s_fs_info = dev; -+#else -+ sb->u.generic_sbp = dev; -+#endif -+ -+ dev->driver_context = mtd; -+ param->name = mtd->name; -+ -+ /* Set up the memory size parameters.... */ -+ -+ n_blocks = -+ YCALCBLOCKS(mtd->size, -+ (YAFFS_CHUNKS_PER_BLOCK * YAFFS_BYTES_PER_CHUNK)); -+ -+ param->start_block = 0; -+ param->end_block = n_blocks - 1; -+ param->chunks_per_block = YAFFS_CHUNKS_PER_BLOCK; -+ param->total_bytes_per_chunk = YAFFS_BYTES_PER_CHUNK; -+ param->n_reserved_blocks = 5; -+ param->n_caches = (options.no_cache) ? 0 : 10; -+ param->inband_tags = options.inband_tags; -+ -+#ifdef CONFIG_YAFFS_DISABLE_LAZY_LOAD -+ param->disable_lazy_load = 1; -+#endif -+#ifdef CONFIG_YAFFS_XATTR -+ param->enable_xattr = 1; -+#endif -+ if (options.lazy_loading_overridden) -+ param->disable_lazy_load = !options.lazy_loading_enabled; -+ -+#ifdef CONFIG_YAFFS_DISABLE_TAGS_ECC -+ param->no_tags_ecc = 1; -+#endif -+ -+#ifdef CONFIG_YAFFS_DISABLE_BACKGROUND -+#else -+ param->defered_dir_update = 1; -+#endif -+ -+ if (options.tags_ecc_overridden) -+ param->no_tags_ecc = !options.tags_ecc_on; -+ -+#ifdef CONFIG_YAFFS_EMPTY_LOST_AND_FOUND -+ param->empty_lost_n_found = 1; -+#endif -+ -+#ifdef CONFIG_YAFFS_DISABLE_BLOCK_REFRESHING -+ param->refresh_period = 0; -+#else -+ param->refresh_period = 500; -+#endif -+ -+#ifdef CONFIG_YAFFS__ALWAYS_CHECK_CHUNK_ERASED -+ param->always_check_erased = 1; -+#endif -+ -+ if (options.empty_lost_and_found_overridden) -+ param->empty_lost_n_found = options.empty_lost_and_found; -+ -+ /* ... and the functions. */ -+ if (yaffs_version == 2) { -+ param->write_chunk_tags_fn = nandmtd2_write_chunk_tags; -+ param->read_chunk_tags_fn = nandmtd2_read_chunk_tags; -+ param->bad_block_fn = nandmtd2_mark_block_bad; -+ param->query_block_fn = nandmtd2_query_block; -+ yaffs_dev_to_lc(dev)->spare_buffer = YMALLOC(mtd->oobsize); -+ param->is_yaffs2 = 1; -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17)) -+ param->total_bytes_per_chunk = mtd->writesize; -+ param->chunks_per_block = mtd->erasesize / mtd->writesize; -+#else -+ param->total_bytes_per_chunk = mtd->oobblock; -+ param->chunks_per_block = mtd->erasesize / mtd->oobblock; -+#endif -+ n_blocks = YCALCBLOCKS(mtd->size, mtd->erasesize); -+ -+ param->start_block = 0; -+ param->end_block = n_blocks - 1; -+ } else { -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17)) -+ /* use the MTD interface in yaffs_mtdif1.c */ -+ param->write_chunk_tags_fn = nandmtd1_write_chunk_tags; -+ param->read_chunk_tags_fn = nandmtd1_read_chunk_tags; -+ param->bad_block_fn = nandmtd1_mark_block_bad; -+ param->query_block_fn = nandmtd1_query_block; -+#else -+ param->write_chunk_fn = nandmtd_write_chunk; -+ param->read_chunk_fn = nandmtd_read_chunk; -+#endif -+ param->is_yaffs2 = 0; -+ } -+ /* ... and common functions */ -+ param->erase_fn = nandmtd_erase_block; -+ param->initialise_flash_fn = nandmtd_initialise; -+ -+ yaffs_dev_to_lc(dev)->put_super_fn = yaffs_mtd_put_super; -+ -+ param->sb_dirty_fn = yaffs_touch_super; -+ param->gc_control = yaffs_gc_control_callback; -+ -+ yaffs_dev_to_lc(dev)->super = sb; -+ -+#ifndef CONFIG_YAFFS_DOES_ECC -+ param->use_nand_ecc = 1; -+#endif -+ -+#ifdef CONFIG_YAFFS_DISABLE_WIDE_TNODES -+ param->wide_tnodes_disabled = 1; -+#endif -+ -+ param->skip_checkpt_rd = options.skip_checkpoint_read; -+ param->skip_checkpt_wr = options.skip_checkpoint_write; -+ -+ mutex_lock(&yaffs_context_lock); -+ /* Get a mount id */ -+ found = 0; -+ for (mount_id = 0; !found; mount_id++) { -+ found = 1; -+ list_for_each(l, &yaffs_context_list) { -+ context_iterator = -+ list_entry(l, struct yaffs_linux_context, -+ context_list); -+ if (context_iterator->mount_id == mount_id) -+ found = 0; -+ } -+ } -+ context->mount_id = mount_id; -+ -+ list_add_tail(&(yaffs_dev_to_lc(dev)->context_list), -+ &yaffs_context_list); -+ mutex_unlock(&yaffs_context_lock); -+ -+ /* Directory search handling... */ -+ INIT_LIST_HEAD(&(yaffs_dev_to_lc(dev)->search_contexts)); -+ param->remove_obj_fn = yaffs_remove_obj_callback; -+ -+ mutex_init(&(yaffs_dev_to_lc(dev)->gross_lock)); -+ -+ yaffs_gross_lock(dev); -+ -+ err = yaffs_guts_initialise(dev); -+ -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_read_super: guts initialised %s\n"), -+ (err == YAFFS_OK) ? "OK" : "FAILED")); -+ -+ if (err == YAFFS_OK) -+ yaffs_bg_start(dev); -+ -+ if (!context->bg_thread) -+ param->defered_dir_update = 0; -+ -+ /* Release lock before yaffs_get_inode() */ -+ yaffs_gross_unlock(dev); -+ -+ /* Create root inode */ -+ if (err == YAFFS_OK) -+ inode = yaffs_get_inode(sb, S_IFDIR | 0755, 0, yaffs_root(dev)); -+ -+ if (!inode) -+ return NULL; -+ -+ inode->i_op = &yaffs_dir_inode_operations; -+ inode->i_fop = &yaffs_dir_operations; -+ -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_read_super: got root inode\n"))); -+ -+ root = d_alloc_root(inode); -+ -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_read_super: d_alloc_root done\n"))); -+ -+ if (!root) { -+ iput(inode); -+ return NULL; -+ } -+ sb->s_root = root; -+ sb->s_dirt = !dev->is_checkpointed; -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR("yaffs_read_super: is_checkpointed %d\n"), -+ dev->is_checkpointed)); -+ -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_read_super: done\n"))); -+ return sb; -+} -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) -+static int yaffs_internal_read_super_mtd(struct super_block *sb, void *data, -+ int silent) -+{ -+ return yaffs_internal_read_super(1, sb, data, silent) ? 0 : -EINVAL; -+} -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17)) -+static int yaffs_read_super(struct file_system_type *fs, -+ int flags, const char *dev_name, -+ void *data, struct vfsmount *mnt) -+{ -+ -+ return get_sb_bdev(fs, flags, dev_name, data, -+ yaffs_internal_read_super_mtd, mnt); -+} -+#else -+static struct super_block *yaffs_read_super(struct file_system_type *fs, -+ int flags, const char *dev_name, -+ void *data) -+{ -+ -+ return get_sb_bdev(fs, flags, dev_name, data, -+ yaffs_internal_read_super_mtd); -+} -+#endif -+ -+static struct file_system_type yaffs_fs_type = { -+ .owner = THIS_MODULE, -+ .name = "yaffs", -+ .get_sb = yaffs_read_super, -+ .kill_sb = kill_block_super, -+ .fs_flags = FS_REQUIRES_DEV, -+}; -+#else -+static struct super_block *yaffs_read_super(struct super_block *sb, void *data, -+ int silent) -+{ -+ return yaffs_internal_read_super(1, sb, data, silent); -+} -+ -+static DECLARE_FSTYPE(yaffs_fs_type, "yaffs", yaffs_read_super, -+ FS_REQUIRES_DEV); -+#endif -+ -+#ifdef CONFIG_YAFFS_YAFFS2 -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) -+static int yaffs2_internal_read_super_mtd(struct super_block *sb, void *data, -+ int silent) -+{ -+ return yaffs_internal_read_super(2, sb, data, silent) ? 0 : -EINVAL; -+} -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17)) -+static int yaffs2_read_super(struct file_system_type *fs, -+ int flags, const char *dev_name, void *data, -+ struct vfsmount *mnt) -+{ -+ return get_sb_bdev(fs, flags, dev_name, data, -+ yaffs2_internal_read_super_mtd, mnt); -+} -+#else -+static struct super_block *yaffs2_read_super(struct file_system_type *fs, -+ int flags, const char *dev_name, -+ void *data) -+{ -+ -+ return get_sb_bdev(fs, flags, dev_name, data, -+ yaffs2_internal_read_super_mtd); -+} -+#endif -+ -+static struct file_system_type yaffs2_fs_type = { -+ .owner = THIS_MODULE, -+ .name = "yaffs2", -+ .get_sb = yaffs2_read_super, -+ .kill_sb = kill_block_super, -+ .fs_flags = FS_REQUIRES_DEV, -+}; -+#else -+static struct super_block *yaffs2_read_super(struct super_block *sb, -+ void *data, int silent) -+{ -+ return yaffs_internal_read_super(2, sb, data, silent); -+} -+ -+static DECLARE_FSTYPE(yaffs2_fs_type, "yaffs2", yaffs2_read_super, -+ FS_REQUIRES_DEV); -+#endif -+ -+#endif /* CONFIG_YAFFS_YAFFS2 */ -+ -+static struct proc_dir_entry *my_proc_entry; -+static struct proc_dir_entry *debug_proc_entry; -+ -+static char *yaffs_dump_dev_part0(char *buf, struct yaffs_dev *dev) -+{ -+ buf += -+ sprintf(buf, "start_block.......... %d\n", dev->param.start_block); -+ buf += sprintf(buf, "end_block............ %d\n", dev->param.end_block); -+ buf += -+ sprintf(buf, "total_bytes_per_chunk %d\n", -+ dev->param.total_bytes_per_chunk); -+ buf += -+ sprintf(buf, "use_nand_ecc......... %d\n", dev->param.use_nand_ecc); -+ buf += -+ sprintf(buf, "no_tags_ecc.......... %d\n", dev->param.no_tags_ecc); -+ buf += sprintf(buf, "is_yaffs2............ %d\n", dev->param.is_yaffs2); -+ buf += -+ sprintf(buf, "inband_tags.......... %d\n", dev->param.inband_tags); -+ buf += -+ sprintf(buf, "empty_lost_n_found... %d\n", -+ dev->param.empty_lost_n_found); -+ buf += -+ sprintf(buf, "disable_lazy_load.... %d\n", -+ dev->param.disable_lazy_load); -+ buf += -+ sprintf(buf, "refresh_period....... %d\n", -+ dev->param.refresh_period); -+ buf += sprintf(buf, "n_caches............. %d\n", dev->param.n_caches); -+ buf += -+ sprintf(buf, "n_reserved_blocks.... %d\n", -+ dev->param.n_reserved_blocks); -+ buf += -+ sprintf(buf, "always_check_erased.. %d\n", -+ dev->param.always_check_erased); -+ -+ buf += sprintf(buf, "\n"); -+ -+ return buf; -+} -+ -+static char *yaffs_dump_dev_part1(char *buf, struct yaffs_dev *dev) -+{ -+ buf += -+ sprintf(buf, "data_bytes_per_chunk. %d\n", -+ dev->data_bytes_per_chunk); -+ buf += sprintf(buf, "chunk_grp_bits....... %d\n", dev->chunk_grp_bits); -+ buf += sprintf(buf, "chunk_grp_size....... %d\n", dev->chunk_grp_size); -+ buf += sprintf(buf, "n_erased_blocks...... %d\n", dev->n_erased_blocks); -+ buf += -+ sprintf(buf, "blocks_in_checkpt.... %d\n", dev->blocks_in_checkpt); -+ buf += sprintf(buf, "\n"); -+ buf += sprintf(buf, "n_tnodes............. %d\n", dev->n_tnodes); -+ buf += sprintf(buf, "n_obj................ %d\n", dev->n_obj); -+ buf += sprintf(buf, "n_free_chunks........ %d\n", dev->n_free_chunks); -+ buf += sprintf(buf, "\n"); -+ buf += sprintf(buf, "n_page_writes........ %u\n", dev->n_page_writes); -+ buf += sprintf(buf, "n_page_reads......... %u\n", dev->n_page_reads); -+ buf += sprintf(buf, "n_erasures........... %u\n", dev->n_erasures); -+ buf += sprintf(buf, "n_gc_copies.......... %u\n", dev->n_gc_copies); -+ buf += sprintf(buf, "all_gcs.............. %u\n", dev->all_gcs); -+ buf += -+ sprintf(buf, "passive_gc_count..... %u\n", dev->passive_gc_count); -+ buf += -+ sprintf(buf, "oldest_dirty_gc_count %u\n", -+ dev->oldest_dirty_gc_count); -+ buf += sprintf(buf, "n_gc_blocks.......... %u\n", dev->n_gc_blocks); -+ buf += sprintf(buf, "bg_gcs............... %u\n", dev->bg_gcs); -+ buf += -+ sprintf(buf, "n_retired_writes..... %u\n", dev->n_retired_writes); -+ buf += -+ sprintf(buf, "n_retired_blocks..... %u\n", dev->n_retired_blocks); -+ buf += sprintf(buf, "n_ecc_fixed.......... %u\n", dev->n_ecc_fixed); -+ buf += sprintf(buf, "n_ecc_unfixed........ %u\n", dev->n_ecc_unfixed); -+ buf += -+ sprintf(buf, "n_tags_ecc_fixed..... %u\n", dev->n_tags_ecc_fixed); -+ buf += -+ sprintf(buf, "n_tags_ecc_unfixed... %u\n", dev->n_tags_ecc_unfixed); -+ buf += sprintf(buf, "cache_hits........... %u\n", dev->cache_hits); -+ buf += sprintf(buf, "n_deleted_files...... %u\n", dev->n_deleted_files); -+ buf += -+ sprintf(buf, "n_unlinked_files..... %u\n", dev->n_unlinked_files); -+ buf += sprintf(buf, "refresh_count........ %u\n", dev->refresh_count); -+ buf += sprintf(buf, "n_bg_deletions....... %u\n", dev->n_bg_deletions); -+ -+ return buf; -+} -+ -+static int yaffs_proc_read(char *page, -+ char **start, -+ off_t offset, int count, int *eof, void *data) -+{ -+ struct list_head *item; -+ char *buf = page; -+ int step = offset; -+ int n = 0; -+ -+ /* Get proc_file_read() to step 'offset' by one on each sucessive call. -+ * We use 'offset' (*ppos) to indicate where we are in dev_list. -+ * This also assumes the user has posted a read buffer large -+ * enough to hold the complete output; but that's life in /proc. -+ */ -+ -+ *(int *)start = 1; -+ -+ /* Print header first */ -+ if (step == 0) -+ buf += -+ sprintf(buf, -+ "Multi-version YAFFS built:" __DATE__ " " __TIME__ -+ "\n"); -+ else if (step == 1) -+ buf += sprintf(buf, "\n"); -+ else { -+ step -= 2; -+ -+ mutex_lock(&yaffs_context_lock); -+ -+ /* Locate and print the Nth entry. Order N-squared but N is small. */ -+ list_for_each(item, &yaffs_context_list) { -+ struct yaffs_linux_context *dc = -+ list_entry(item, struct yaffs_linux_context, -+ context_list); -+ struct yaffs_dev *dev = dc->dev; -+ -+ if (n < (step & ~1)) { -+ n += 2; -+ continue; -+ } -+ if ((step & 1) == 0) { -+ buf += -+ sprintf(buf, "\nDevice %d \"%s\"\n", n, -+ dev->param.name); -+ buf = yaffs_dump_dev_part0(buf, dev); -+ } else { -+ buf = yaffs_dump_dev_part1(buf, dev); -+ } -+ -+ break; -+ } -+ mutex_unlock(&yaffs_context_lock); -+ } -+ -+ return buf - page < count ? buf - page : count; -+} -+ -+static int yaffs_stats_proc_read(char *page, -+ char **start, -+ off_t offset, int count, int *eof, void *data) -+{ -+ struct list_head *item; -+ char *buf = page; -+ int n = 0; -+ -+ mutex_lock(&yaffs_context_lock); -+ -+ /* Locate and print the Nth entry. Order N-squared but N is small. */ -+ list_for_each(item, &yaffs_context_list) { -+ struct yaffs_linux_context *dc = -+ list_entry(item, struct yaffs_linux_context, context_list); -+ struct yaffs_dev *dev = dc->dev; -+ -+ int erased_chunks; -+ -+ erased_chunks = -+ dev->n_erased_blocks * dev->param.chunks_per_block; -+ -+ buf += sprintf(buf, "%d, %d, %d, %u, %u, %u, %u\n", -+ n, dev->n_free_chunks, erased_chunks, -+ dev->bg_gcs, dev->oldest_dirty_gc_count, -+ dev->n_obj, dev->n_tnodes); -+ } -+ mutex_unlock(&yaffs_context_lock); -+ -+ return buf - page < count ? buf - page : count; -+} -+ -+/** -+ * Set the verbosity of the warnings and error messages. -+ * -+ * Note that the names can only be a..z or _ with the current code. -+ */ -+ -+static struct { -+ char *mask_name; -+ unsigned mask_bitfield; -+} mask_flags[] = { -+ {"allocate", YAFFS_TRACE_ALLOCATE}, -+ {"always", YAFFS_TRACE_ALWAYS}, -+ {"background", YAFFS_TRACE_BACKGROUND}, -+ {"bad_blocks", YAFFS_TRACE_BAD_BLOCKS}, -+ {"buffers", YAFFS_TRACE_BUFFERS}, -+ {"bug", YAFFS_TRACE_BUG}, -+ {"checkpt", YAFFS_TRACE_CHECKPOINT}, -+ {"deletion", YAFFS_TRACE_DELETION}, -+ {"erase", YAFFS_TRACE_ERASE}, -+ {"error", YAFFS_TRACE_ERROR}, -+ {"gc_detail", YAFFS_TRACE_GC_DETAIL}, -+ {"gc", YAFFS_TRACE_GC}, -+ {"lock", YAFFS_TRACE_LOCK}, -+ {"mtd", YAFFS_TRACE_MTD}, -+ {"nandaccess", YAFFS_TRACE_NANDACCESS}, -+ {"os", YAFFS_TRACE_OS}, -+ {"scan_debug", YAFFS_TRACE_SCAN_DEBUG}, -+ {"scan", YAFFS_TRACE_SCAN}, -+ {"mount", YAFFS_TRACE_MOUNT}, -+ {"tracing", YAFFS_TRACE_TRACING}, -+ {"sync", YAFFS_TRACE_SYNC}, -+ {"write", YAFFS_TRACE_WRITE}, -+ {"verify", YAFFS_TRACE_VERIFY}, -+ {"verify_nand", YAFFS_TRACE_VERIFY_NAND}, -+ {"verify_full", YAFFS_TRACE_VERIFY_FULL}, -+ {"verify_all", YAFFS_TRACE_VERIFY_ALL}, -+ {"all", 0xffffffff}, -+ {"none", 0}, -+ {NULL, 0}, -+}; -+ -+#define MAX_MASK_NAME_LENGTH 40 -+static int yaffs_proc_write_trace_options(struct file *file, const char *buf, -+ unsigned long count, void *data) -+{ -+ unsigned rg = 0, mask_bitfield; -+ char *end; -+ char *mask_name; -+ const char *x; -+ char substring[MAX_MASK_NAME_LENGTH + 1]; -+ int i; -+ int done = 0; -+ int add, len = 0; -+ int pos = 0; -+ -+ rg = yaffs_trace_mask; -+ -+ while (!done && (pos < count)) { -+ done = 1; -+ while ((pos < count) && isspace(buf[pos])) -+ pos++; -+ -+ switch (buf[pos]) { -+ case '+': -+ case '-': -+ case '=': -+ add = buf[pos]; -+ pos++; -+ break; -+ -+ default: -+ add = ' '; -+ break; -+ } -+ mask_name = NULL; -+ -+ mask_bitfield = simple_strtoul(buf + pos, &end, 0); -+ -+ if (end > buf + pos) { -+ mask_name = "numeral"; -+ len = end - (buf + pos); -+ pos += len; -+ done = 0; -+ } else { -+ for (x = buf + pos, i = 0; -+ (*x == '_' || (*x >= 'a' && *x <= 'z')) && -+ i < MAX_MASK_NAME_LENGTH; x++, i++, pos++) -+ substring[i] = *x; -+ substring[i] = '\0'; -+ -+ for (i = 0; mask_flags[i].mask_name != NULL; i++) { -+ if (strcmp(substring, mask_flags[i].mask_name) -+ == 0) { -+ mask_name = mask_flags[i].mask_name; -+ mask_bitfield = -+ mask_flags[i].mask_bitfield; -+ done = 0; -+ break; -+ } -+ } -+ } -+ -+ if (mask_name != NULL) { -+ done = 0; -+ switch (add) { -+ case '-': -+ rg &= ~mask_bitfield; -+ break; -+ case '+': -+ rg |= mask_bitfield; -+ break; -+ case '=': -+ rg = mask_bitfield; -+ break; -+ default: -+ rg |= mask_bitfield; -+ break; -+ } -+ } -+ } -+ -+ yaffs_trace_mask = rg | YAFFS_TRACE_ALWAYS; -+ -+ printk(KERN_DEBUG "new trace = 0x%08X\n", yaffs_trace_mask); -+ -+ if (rg & YAFFS_TRACE_ALWAYS) { -+ for (i = 0; mask_flags[i].mask_name != NULL; i++) { -+ char flag; -+ flag = ((rg & mask_flags[i].mask_bitfield) == -+ mask_flags[i].mask_bitfield) ? '+' : '-'; -+ printk(KERN_DEBUG "%c%s\n", flag, -+ mask_flags[i].mask_name); -+ } -+ } -+ -+ return count; -+} -+ -+static int yaffs_proc_write(struct file *file, const char *buf, -+ unsigned long count, void *data) -+{ -+ return yaffs_proc_write_trace_options(file, buf, count, data); -+} -+ -+/* Stuff to handle installation of file systems */ -+struct file_system_to_install { -+ struct file_system_type *fst; -+ int installed; -+}; -+ -+static struct file_system_to_install fs_to_install[] = { -+ {&yaffs_fs_type, 0}, -+ {&yaffs2_fs_type, 0}, -+ {NULL, 0} -+}; -+ -+static int __init init_yaffs_fs(void) -+{ -+ int error = 0; -+ struct file_system_to_install *fsinst; -+ -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR("yaffs built " __DATE__ " " __TIME__ " Installing. \n"))); -+ -+#ifdef CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR -+ (" \n\n\n\nYAFFS-WARNING CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED selected.\n\n\n\n"))); -+#endif -+ -+ mutex_init(&yaffs_context_lock); -+ -+ /* Install the proc_fs entries */ -+ my_proc_entry = create_proc_entry("yaffs", -+ S_IRUGO | S_IFREG, YPROC_ROOT); -+ -+ if (my_proc_entry) { -+ my_proc_entry->write_proc = yaffs_proc_write; -+ my_proc_entry->read_proc = yaffs_proc_read; -+ my_proc_entry->data = NULL; -+ } else { -+ return -ENOMEM; -+ } -+ -+ debug_proc_entry = create_proc_entry("yaffs_stats", -+ S_IRUGO | S_IFREG, YPROC_ROOT); -+ -+ if (debug_proc_entry) { -+ debug_proc_entry->write_proc = NULL; -+ debug_proc_entry->read_proc = yaffs_stats_proc_read; -+ debug_proc_entry->data = NULL; -+ } else { -+ return -ENOMEM; -+ } -+ -+ /* Now add the file system entries */ -+ -+ fsinst = fs_to_install; -+ -+ while (fsinst->fst && !error) { -+ error = register_filesystem(fsinst->fst); -+ if (!error) -+ fsinst->installed = 1; -+ fsinst++; -+ } -+ -+ /* Any errors? uninstall */ -+ if (error) { -+ fsinst = fs_to_install; -+ -+ while (fsinst->fst) { -+ if (fsinst->installed) { -+ unregister_filesystem(fsinst->fst); -+ fsinst->installed = 0; -+ } -+ fsinst++; -+ } -+ } -+ -+ return error; -+} -+ -+static void __exit exit_yaffs_fs(void) -+{ -+ -+ struct file_system_to_install *fsinst; -+ -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR("yaffs built " __DATE__ " " __TIME__ " removing. \n"))); -+ -+ remove_proc_entry("yaffs", YPROC_ROOT); -+ remove_proc_entry("yaffs_stats", YPROC_ROOT); -+ -+ fsinst = fs_to_install; -+ -+ while (fsinst->fst) { -+ if (fsinst->installed) { -+ unregister_filesystem(fsinst->fst); -+ fsinst->installed = 0; -+ } -+ fsinst++; -+ } -+} -+ -+module_init(init_yaffs_fs) -+ module_exit(exit_yaffs_fs) -+ -+ MODULE_DESCRIPTION("YAFFS2 - a NAND specific flash file system"); -+MODULE_AUTHOR("Charles Manning, Aleph One Ltd., 2002-2010"); -+MODULE_LICENSE("GPL"); -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_yaffs1.c linux-2.6.36/fs/yaffs2/yaffs_yaffs1.c ---- linux-2.6.36.orig/fs/yaffs2/yaffs_yaffs1.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_yaffs1.c 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,437 @@ -+/* -+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include "yaffs_yaffs1.h" -+#include "yportenv.h" -+#include "yaffs_trace.h" -+#include "yaffs_bitmap.h" -+#include "yaffs_getblockinfo.h" -+#include "yaffs_nand.h" -+#include "yaffs_attribs.h" -+ -+int yaffs1_scan(struct yaffs_dev *dev) -+{ -+ struct yaffs_ext_tags tags; -+ int blk; -+ int result; -+ -+ int chunk; -+ int c; -+ int deleted; -+ enum yaffs_block_state state; -+ struct yaffs_obj *hard_list = NULL; -+ struct yaffs_block_info *bi; -+ u32 seq_number; -+ struct yaffs_obj_hdr *oh; -+ struct yaffs_obj *in; -+ struct yaffs_obj *parent; -+ -+ int alloc_failed = 0; -+ -+ struct yaffs_shadow_fixer *shadow_fixers = NULL; -+ -+ u8 *chunk_data; -+ -+ T(YAFFS_TRACE_SCAN, -+ (TSTR("yaffs1_scan starts intstartblk %d intendblk %d..." TENDSTR), -+ dev->internal_start_block, dev->internal_end_block)); -+ -+ chunk_data = yaffs_get_temp_buffer(dev, __LINE__); -+ -+ dev->seq_number = YAFFS_LOWEST_SEQUENCE_NUMBER; -+ -+ /* Scan all the blocks to determine their state */ -+ bi = dev->block_info; -+ for (blk = dev->internal_start_block; blk <= dev->internal_end_block; -+ blk++) { -+ yaffs_clear_chunk_bits(dev, blk); -+ bi->pages_in_use = 0; -+ bi->soft_del_pages = 0; -+ -+ yaffs_query_init_block_state(dev, blk, &state, &seq_number); -+ -+ bi->block_state = state; -+ bi->seq_number = seq_number; -+ -+ if (bi->seq_number == YAFFS_SEQUENCE_BAD_BLOCK) -+ bi->block_state = state = YAFFS_BLOCK_STATE_DEAD; -+ -+ T(YAFFS_TRACE_SCAN_DEBUG, -+ (TSTR("Block scanning block %d state %d seq %d" TENDSTR), blk, -+ state, seq_number)); -+ -+ if (state == YAFFS_BLOCK_STATE_DEAD) { -+ T(YAFFS_TRACE_BAD_BLOCKS, -+ (TSTR("block %d is bad" TENDSTR), blk)); -+ } else if (state == YAFFS_BLOCK_STATE_EMPTY) { -+ T(YAFFS_TRACE_SCAN_DEBUG, -+ (TSTR("Block empty " TENDSTR))); -+ dev->n_erased_blocks++; -+ dev->n_free_chunks += dev->param.chunks_per_block; -+ } -+ bi++; -+ } -+ -+ /* For each block.... */ -+ for (blk = dev->internal_start_block; -+ !alloc_failed && blk <= dev->internal_end_block; blk++) { -+ -+ YYIELD(); -+ -+ bi = yaffs_get_block_info(dev, blk); -+ state = bi->block_state; -+ -+ deleted = 0; -+ -+ /* For each chunk in each block that needs scanning.... */ -+ for (c = 0; !alloc_failed && c < dev->param.chunks_per_block && -+ state == YAFFS_BLOCK_STATE_NEEDS_SCANNING; c++) { -+ /* Read the tags and decide what to do */ -+ chunk = blk * dev->param.chunks_per_block + c; -+ -+ result = yaffs_rd_chunk_tags_nand(dev, chunk, NULL, -+ &tags); -+ -+ /* Let's have a good look at this chunk... */ -+ -+ if (tags.ecc_result == YAFFS_ECC_RESULT_UNFIXED -+ || tags.is_deleted) { -+ /* YAFFS1 only... -+ * A deleted chunk -+ */ -+ deleted++; -+ dev->n_free_chunks++; -+ /*T((" %d %d deleted\n",blk,c)); */ -+ } else if (!tags.chunk_used) { -+ /* An unassigned chunk in the block -+ * This means that either the block is empty or -+ * this is the one being allocated from -+ */ -+ -+ if (c == 0) { -+ /* We're looking at the first chunk in the block so the block is unused */ -+ state = YAFFS_BLOCK_STATE_EMPTY; -+ dev->n_erased_blocks++; -+ } else { -+ /* this is the block being allocated from */ -+ T(YAFFS_TRACE_SCAN, -+ (TSTR -+ (" Allocating from %d %d" TENDSTR), -+ blk, c)); -+ state = YAFFS_BLOCK_STATE_ALLOCATING; -+ dev->alloc_block = blk; -+ dev->alloc_page = c; -+ dev->alloc_block_finder = blk; -+ /* Set block finder here to encourage the allocator to go forth from here. */ -+ -+ } -+ -+ dev->n_free_chunks += -+ (dev->param.chunks_per_block - c); -+ } else if (tags.chunk_id > 0) { -+ /* chunk_id > 0 so it is a data chunk... */ -+ unsigned int endpos; -+ -+ yaffs_set_chunk_bit(dev, blk, c); -+ bi->pages_in_use++; -+ -+ in = yaffs_find_or_create_by_number(dev, -+ tags.obj_id, -+ YAFFS_OBJECT_TYPE_FILE); -+ /* PutChunkIntoFile checks for a clash (two data chunks with -+ * the same chunk_id). -+ */ -+ -+ if (!in) -+ alloc_failed = 1; -+ -+ if (in) { -+ if (!yaffs_put_chunk_in_file -+ (in, tags.chunk_id, chunk, 1)) -+ alloc_failed = 1; -+ } -+ -+ endpos = -+ (tags.chunk_id - -+ 1) * dev->data_bytes_per_chunk + -+ tags.n_bytes; -+ if (in -+ && in->variant_type == -+ YAFFS_OBJECT_TYPE_FILE -+ && in->variant.file_variant.scanned_size < -+ endpos) { -+ in->variant.file_variant.scanned_size = -+ endpos; -+ if (!dev->param.use_header_file_size) { -+ in->variant. -+ file_variant.file_size = -+ in->variant. -+ file_variant.scanned_size; -+ } -+ -+ } -+ /* T((" %d %d data %d %d\n",blk,c,tags.obj_id,tags.chunk_id)); */ -+ } else { -+ /* chunk_id == 0, so it is an ObjectHeader. -+ * Thus, we read in the object header and make the object -+ */ -+ yaffs_set_chunk_bit(dev, blk, c); -+ bi->pages_in_use++; -+ -+ result = yaffs_rd_chunk_tags_nand(dev, chunk, -+ chunk_data, -+ NULL); -+ -+ oh = (struct yaffs_obj_hdr *)chunk_data; -+ -+ in = yaffs_find_by_number(dev, tags.obj_id); -+ if (in && in->variant_type != oh->type) { -+ /* This should not happen, but somehow -+ * Wev'e ended up with an obj_id that has been reused but not yet -+ * deleted, and worse still it has changed type. Delete the old object. -+ */ -+ -+ yaffs_del_obj(in); -+ -+ in = 0; -+ } -+ -+ in = yaffs_find_or_create_by_number(dev, -+ tags.obj_id, -+ oh->type); -+ -+ if (!in) -+ alloc_failed = 1; -+ -+ if (in && oh->shadows_obj > 0) { -+ -+ struct yaffs_shadow_fixer *fixer; -+ fixer = -+ YMALLOC(sizeof -+ (struct -+ yaffs_shadow_fixer)); -+ if (fixer) { -+ fixer->next = shadow_fixers; -+ shadow_fixers = fixer; -+ fixer->obj_id = tags.obj_id; -+ fixer->shadowed_id = -+ oh->shadows_obj; -+ T(YAFFS_TRACE_SCAN, -+ (TSTR -+ (" Shadow fixer: %d shadows %d" -+ TENDSTR), fixer->obj_id, -+ fixer->shadowed_id)); -+ -+ } -+ -+ } -+ -+ if (in && in->valid) { -+ /* We have already filled this one. We have a duplicate and need to resolve it. */ -+ -+ unsigned existing_serial = in->serial; -+ unsigned new_serial = -+ tags.serial_number; -+ -+ if (((existing_serial + 1) & 3) == -+ new_serial) { -+ /* Use new one - destroy the exisiting one */ -+ yaffs_chunk_del(dev, -+ in->hdr_chunk, -+ 1, __LINE__); -+ in->valid = 0; -+ } else { -+ /* Use existing - destroy this one. */ -+ yaffs_chunk_del(dev, chunk, 1, -+ __LINE__); -+ } -+ } -+ -+ if (in && !in->valid && -+ (tags.obj_id == YAFFS_OBJECTID_ROOT || -+ tags.obj_id == -+ YAFFS_OBJECTID_LOSTNFOUND)) { -+ /* We only load some info, don't fiddle with directory structure */ -+ in->valid = 1; -+ in->variant_type = oh->type; -+ -+ in->yst_mode = oh->yst_mode; -+ yaffs_load_attribs(in, oh); -+ in->hdr_chunk = chunk; -+ in->serial = tags.serial_number; -+ -+ } else if (in && !in->valid) { -+ /* we need to load this info */ -+ -+ in->valid = 1; -+ in->variant_type = oh->type; -+ -+ in->yst_mode = oh->yst_mode; -+ yaffs_load_attribs(in, oh); -+ in->hdr_chunk = chunk; -+ in->serial = tags.serial_number; -+ -+ yaffs_set_obj_name_from_oh(in, oh); -+ in->dirty = 0; -+ -+ /* directory stuff... -+ * hook up to parent -+ */ -+ -+ parent = -+ yaffs_find_or_create_by_number -+ (dev, oh->parent_obj_id, -+ YAFFS_OBJECT_TYPE_DIRECTORY); -+ if (!parent) -+ alloc_failed = 1; -+ if (parent && parent->variant_type == -+ YAFFS_OBJECT_TYPE_UNKNOWN) { -+ /* Set up as a directory */ -+ parent->variant_type = -+ YAFFS_OBJECT_TYPE_DIRECTORY; -+ INIT_LIST_HEAD(&parent-> -+ variant.dir_variant.children); -+ } else if (!parent -+ || parent->variant_type != -+ YAFFS_OBJECT_TYPE_DIRECTORY) { -+ /* Hoosterman, another problem.... -+ * We're trying to use a non-directory as a directory -+ */ -+ -+ T(YAFFS_TRACE_ERROR, -+ (TSTR -+ ("yaffs tragedy: attempting to use non-directory as a directory in scan. Put in lost+found." -+ TENDSTR))); -+ parent = dev->lost_n_found; -+ } -+ -+ yaffs_add_obj_to_dir(parent, in); -+ -+ if (0 && (parent == dev->del_dir || -+ parent == -+ dev->unlinked_dir)) { -+ in->deleted = 1; /* If it is unlinked at start up then it wants deleting */ -+ dev->n_deleted_files++; -+ } -+ /* Note re hardlinks. -+ * Since we might scan a hardlink before its equivalent object is scanned -+ * we put them all in a list. -+ * After scanning is complete, we should have all the objects, so we run through this -+ * list and fix up all the chains. -+ */ -+ -+ switch (in->variant_type) { -+ case YAFFS_OBJECT_TYPE_UNKNOWN: -+ /* Todo got a problem */ -+ break; -+ case YAFFS_OBJECT_TYPE_FILE: -+ if (dev->param. -+ use_header_file_size) -+ -+ in->variant. -+ file_variant.file_size -+ = oh->file_size; -+ -+ break; -+ case YAFFS_OBJECT_TYPE_HARDLINK: -+ in->variant. -+ hardlink_variant.equiv_id = -+ oh->equiv_id; -+ in->hard_links.next = -+ (struct list_head *) -+ hard_list; -+ hard_list = in; -+ break; -+ case YAFFS_OBJECT_TYPE_DIRECTORY: -+ /* Do nothing */ -+ break; -+ case YAFFS_OBJECT_TYPE_SPECIAL: -+ /* Do nothing */ -+ break; -+ case YAFFS_OBJECT_TYPE_SYMLINK: -+ in->variant.symlink_variant. -+ alias = -+ yaffs_clone_str(oh->alias); -+ if (!in->variant. -+ symlink_variant.alias) -+ alloc_failed = 1; -+ break; -+ } -+ -+ } -+ } -+ } -+ -+ if (state == YAFFS_BLOCK_STATE_NEEDS_SCANNING) { -+ /* If we got this far while scanning, then the block is fully allocated. */ -+ state = YAFFS_BLOCK_STATE_FULL; -+ } -+ -+ if (state == YAFFS_BLOCK_STATE_ALLOCATING) { -+ /* If the block was partially allocated then treat it as fully allocated. */ -+ state = YAFFS_BLOCK_STATE_FULL; -+ dev->alloc_block = -1; -+ } -+ -+ bi->block_state = state; -+ -+ /* Now let's see if it was dirty */ -+ if (bi->pages_in_use == 0 && -+ !bi->has_shrink_hdr && -+ bi->block_state == YAFFS_BLOCK_STATE_FULL) { -+ yaffs_block_became_dirty(dev, blk); -+ } -+ -+ } -+ -+ /* Ok, we've done all the scanning. -+ * Fix up the hard link chains. -+ * We should now have scanned all the objects, now it's time to add these -+ * hardlinks. -+ */ -+ -+ yaffs_link_fixup(dev, hard_list); -+ -+ /* Fix up any shadowed objects */ -+ { -+ struct yaffs_shadow_fixer *fixer; -+ struct yaffs_obj *obj; -+ -+ while (shadow_fixers) { -+ fixer = shadow_fixers; -+ shadow_fixers = fixer->next; -+ /* Complete the rename transaction by deleting the shadowed object -+ * then setting the object header to unshadowed. -+ */ -+ obj = yaffs_find_by_number(dev, fixer->shadowed_id); -+ if (obj) -+ yaffs_del_obj(obj); -+ -+ obj = yaffs_find_by_number(dev, fixer->obj_id); -+ -+ if (obj) -+ yaffs_update_oh(obj, NULL, 1, 0, 0, NULL); -+ -+ YFREE(fixer); -+ } -+ } -+ -+ yaffs_release_temp_buffer(dev, chunk_data, __LINE__); -+ -+ if (alloc_failed) -+ return YAFFS_FAIL; -+ -+ T(YAFFS_TRACE_SCAN, (TSTR("yaffs1_scan ends" TENDSTR))); -+ -+ return YAFFS_OK; -+} -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_yaffs1.h linux-2.6.36/fs/yaffs2/yaffs_yaffs1.h ---- linux-2.6.36.orig/fs/yaffs2/yaffs_yaffs1.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_yaffs1.h 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,22 @@ -+/* -+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU Lesser General Public License version 2.1 as -+ * published by the Free Software Foundation. -+ * -+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. -+ */ -+ -+#ifndef __YAFFS_YAFFS1_H__ -+#define __YAFFS_YAFFS1_H__ -+ -+#include "yaffs_guts.h" -+int yaffs1_scan(struct yaffs_dev *dev); -+ -+#endif -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_yaffs2.c linux-2.6.36/fs/yaffs2/yaffs_yaffs2.c ---- linux-2.6.36.orig/fs/yaffs2/yaffs_yaffs2.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_yaffs2.c 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,1620 @@ -+/* -+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include "yaffs_guts.h" -+#include "yaffs_trace.h" -+#include "yaffs_yaffs2.h" -+#include "yaffs_checkptrw.h" -+#include "yaffs_bitmap.h" -+#include "yaffs_nand.h" -+#include "yaffs_getblockinfo.h" -+#include "yaffs_verify.h" -+#include "yaffs_attribs.h" -+ -+/* -+ * Checkpoints are really no benefit on very small partitions. -+ * -+ * To save space on small partitions don't bother with checkpoints unless -+ * the partition is at least this big. -+ */ -+#define YAFFS_CHECKPOINT_MIN_BLOCKS 60 -+ -+#define YAFFS_SMALL_HOLE_THRESHOLD 4 -+ -+/* -+ * Oldest Dirty Sequence Number handling. -+ */ -+ -+/* yaffs_calc_oldest_dirty_seq() -+ * yaffs2_find_oldest_dirty_seq() -+ * Calculate the oldest dirty sequence number if we don't know it. -+ */ -+void yaffs_calc_oldest_dirty_seq(struct yaffs_dev *dev) -+{ -+ int i; -+ unsigned seq; -+ unsigned block_no = 0; -+ struct yaffs_block_info *b; -+ -+ if (!dev->param.is_yaffs2) -+ return; -+ -+ /* Find the oldest dirty sequence number. */ -+ seq = dev->seq_number + 1; -+ b = dev->block_info; -+ for (i = dev->internal_start_block; i <= dev->internal_end_block; i++) { -+ if (b->block_state == YAFFS_BLOCK_STATE_FULL && -+ (b->pages_in_use - b->soft_del_pages) < -+ dev->param.chunks_per_block && b->seq_number < seq) { -+ seq = b->seq_number; -+ block_no = i; -+ } -+ b++; -+ } -+ -+ if (block_no) { -+ dev->oldest_dirty_seq = seq; -+ dev->oldest_dirty_block = block_no; -+ } -+ -+} -+ -+void yaffs2_find_oldest_dirty_seq(struct yaffs_dev *dev) -+{ -+ if (!dev->param.is_yaffs2) -+ return; -+ -+ if (!dev->oldest_dirty_seq) -+ yaffs_calc_oldest_dirty_seq(dev); -+} -+ -+/* -+ * yaffs_clear_oldest_dirty_seq() -+ * Called when a block is erased or marked bad. (ie. when its seq_number -+ * becomes invalid). If the value matches the oldest then we clear -+ * dev->oldest_dirty_seq to force its recomputation. -+ */ -+void yaffs2_clear_oldest_dirty_seq(struct yaffs_dev *dev, -+ struct yaffs_block_info *bi) -+{ -+ -+ if (!dev->param.is_yaffs2) -+ return; -+ -+ if (!bi || bi->seq_number == dev->oldest_dirty_seq) { -+ dev->oldest_dirty_seq = 0; -+ dev->oldest_dirty_block = 0; -+ } -+} -+ -+/* -+ * yaffs2_update_oldest_dirty_seq() -+ * Update the oldest dirty sequence number whenever we dirty a block. -+ * Only do this if the oldest_dirty_seq is actually being tracked. -+ */ -+void yaffs2_update_oldest_dirty_seq(struct yaffs_dev *dev, unsigned block_no, -+ struct yaffs_block_info *bi) -+{ -+ if (!dev->param.is_yaffs2) -+ return; -+ -+ if (dev->oldest_dirty_seq) { -+ if (dev->oldest_dirty_seq > bi->seq_number) { -+ dev->oldest_dirty_seq = bi->seq_number; -+ dev->oldest_dirty_block = block_no; -+ } -+ } -+} -+ -+int yaffs_block_ok_for_gc(struct yaffs_dev *dev, struct yaffs_block_info *bi) -+{ -+ -+ if (!dev->param.is_yaffs2) -+ return 1; /* disqualification only applies to yaffs2. */ -+ -+ if (!bi->has_shrink_hdr) -+ return 1; /* can gc */ -+ -+ yaffs2_find_oldest_dirty_seq(dev); -+ -+ /* Can't do gc of this block if there are any blocks older than this one that have -+ * discarded pages. -+ */ -+ return (bi->seq_number <= dev->oldest_dirty_seq); -+} -+ -+/* -+ * yaffs2_find_refresh_block() -+ * periodically finds the oldest full block by sequence number for refreshing. -+ * Only for yaffs2. -+ */ -+u32 yaffs2_find_refresh_block(struct yaffs_dev * dev) -+{ -+ u32 b; -+ -+ u32 oldest = 0; -+ u32 oldest_seq = 0; -+ -+ struct yaffs_block_info *bi; -+ -+ if (!dev->param.is_yaffs2) -+ return oldest; -+ -+ /* -+ * If refresh period < 10 then refreshing is disabled. -+ */ -+ if (dev->param.refresh_period < 10) -+ return oldest; -+ -+ /* -+ * Fix broken values. -+ */ -+ if (dev->refresh_skip > dev->param.refresh_period) -+ dev->refresh_skip = dev->param.refresh_period; -+ -+ if (dev->refresh_skip > 0) -+ return oldest; -+ -+ /* -+ * Refresh skip is now zero. -+ * We'll do a refresh this time around.... -+ * Update the refresh skip and find the oldest block. -+ */ -+ dev->refresh_skip = dev->param.refresh_period; -+ dev->refresh_count++; -+ bi = dev->block_info; -+ for (b = dev->internal_start_block; b <= dev->internal_end_block; b++) { -+ -+ if (bi->block_state == YAFFS_BLOCK_STATE_FULL) { -+ -+ if (oldest < 1 || bi->seq_number < oldest_seq) { -+ oldest = b; -+ oldest_seq = bi->seq_number; -+ } -+ } -+ bi++; -+ } -+ -+ if (oldest > 0) { -+ T(YAFFS_TRACE_GC, -+ (TSTR -+ ("GC refresh count %d selected block %d with seq_number %d" -+ TENDSTR), dev->refresh_count, oldest, oldest_seq)); -+ } -+ -+ return oldest; -+} -+ -+int yaffs2_checkpt_required(struct yaffs_dev *dev) -+{ -+ int nblocks; -+ -+ if (!dev->param.is_yaffs2) -+ return 0; -+ -+ nblocks = dev->internal_end_block - dev->internal_start_block + 1; -+ -+ return !dev->param.skip_checkpt_wr && -+ !dev->read_only && (nblocks >= YAFFS_CHECKPOINT_MIN_BLOCKS); -+} -+ -+int yaffs_calc_checkpt_blocks_required(struct yaffs_dev *dev) -+{ -+ int retval; -+ -+ if (!dev->param.is_yaffs2) -+ return 0; -+ -+ if (!dev->checkpoint_blocks_required && yaffs2_checkpt_required(dev)) { -+ /* Not a valid value so recalculate */ -+ int n_bytes = 0; -+ int n_blocks; -+ int dev_blocks = -+ (dev->param.end_block - dev->param.start_block + 1); -+ -+ n_bytes += sizeof(struct yaffs_checkpt_validity); -+ n_bytes += sizeof(struct yaffs_checkpt_dev); -+ n_bytes += dev_blocks * sizeof(struct yaffs_block_info); -+ n_bytes += dev_blocks * dev->chunk_bit_stride; -+ n_bytes += -+ (sizeof(struct yaffs_checkpt_obj) + -+ sizeof(u32)) * (dev->n_obj); -+ n_bytes += (dev->tnode_size + sizeof(u32)) * (dev->n_tnodes); -+ n_bytes += sizeof(struct yaffs_checkpt_validity); -+ n_bytes += sizeof(u32); /* checksum */ -+ -+ /* Round up and add 2 blocks to allow for some bad blocks, so add 3 */ -+ -+ n_blocks = -+ (n_bytes / -+ (dev->data_bytes_per_chunk * -+ dev->param.chunks_per_block)) + 3; -+ -+ dev->checkpoint_blocks_required = n_blocks; -+ } -+ -+ retval = dev->checkpoint_blocks_required - dev->blocks_in_checkpt; -+ if (retval < 0) -+ retval = 0; -+ return retval; -+} -+ -+/*--------------------- Checkpointing --------------------*/ -+ -+static int yaffs2_wr_checkpt_validity_marker(struct yaffs_dev *dev, int head) -+{ -+ struct yaffs_checkpt_validity cp; -+ -+ memset(&cp, 0, sizeof(cp)); -+ -+ cp.struct_type = sizeof(cp); -+ cp.magic = YAFFS_MAGIC; -+ cp.version = YAFFS_CHECKPOINT_VERSION; -+ cp.head = (head) ? 1 : 0; -+ -+ return (yaffs2_checkpt_wr(dev, &cp, sizeof(cp)) == sizeof(cp)) ? 1 : 0; -+} -+ -+static int yaffs2_rd_checkpt_validity_marker(struct yaffs_dev *dev, int head) -+{ -+ struct yaffs_checkpt_validity cp; -+ int ok; -+ -+ ok = (yaffs2_checkpt_rd(dev, &cp, sizeof(cp)) == sizeof(cp)); -+ -+ if (ok) -+ ok = (cp.struct_type == sizeof(cp)) && -+ (cp.magic == YAFFS_MAGIC) && -+ (cp.version == YAFFS_CHECKPOINT_VERSION) && -+ (cp.head == ((head) ? 1 : 0)); -+ return ok ? 1 : 0; -+} -+ -+static void yaffs2_dev_to_checkpt_dev(struct yaffs_checkpt_dev *cp, -+ struct yaffs_dev *dev) -+{ -+ cp->n_erased_blocks = dev->n_erased_blocks; -+ cp->alloc_block = dev->alloc_block; -+ cp->alloc_page = dev->alloc_page; -+ cp->n_free_chunks = dev->n_free_chunks; -+ -+ cp->n_deleted_files = dev->n_deleted_files; -+ cp->n_unlinked_files = dev->n_unlinked_files; -+ cp->n_bg_deletions = dev->n_bg_deletions; -+ cp->seq_number = dev->seq_number; -+ -+} -+ -+static void yaffs_checkpt_dev_to_dev(struct yaffs_dev *dev, -+ struct yaffs_checkpt_dev *cp) -+{ -+ dev->n_erased_blocks = cp->n_erased_blocks; -+ dev->alloc_block = cp->alloc_block; -+ dev->alloc_page = cp->alloc_page; -+ dev->n_free_chunks = cp->n_free_chunks; -+ -+ dev->n_deleted_files = cp->n_deleted_files; -+ dev->n_unlinked_files = cp->n_unlinked_files; -+ dev->n_bg_deletions = cp->n_bg_deletions; -+ dev->seq_number = cp->seq_number; -+} -+ -+static int yaffs2_wr_checkpt_dev(struct yaffs_dev *dev) -+{ -+ struct yaffs_checkpt_dev cp; -+ u32 n_bytes; -+ u32 n_blocks = -+ (dev->internal_end_block - dev->internal_start_block + 1); -+ -+ int ok; -+ -+ /* Write device runtime values */ -+ yaffs2_dev_to_checkpt_dev(&cp, dev); -+ cp.struct_type = sizeof(cp); -+ -+ ok = (yaffs2_checkpt_wr(dev, &cp, sizeof(cp)) == sizeof(cp)); -+ -+ /* Write block info */ -+ if (ok) { -+ n_bytes = n_blocks * sizeof(struct yaffs_block_info); -+ ok = (yaffs2_checkpt_wr(dev, dev->block_info, n_bytes) == -+ n_bytes); -+ } -+ -+ /* Write chunk bits */ -+ if (ok) { -+ n_bytes = n_blocks * dev->chunk_bit_stride; -+ ok = (yaffs2_checkpt_wr(dev, dev->chunk_bits, n_bytes) == -+ n_bytes); -+ } -+ return ok ? 1 : 0; -+ -+} -+ -+static int yaffs2_rd_checkpt_dev(struct yaffs_dev *dev) -+{ -+ struct yaffs_checkpt_dev cp; -+ u32 n_bytes; -+ u32 n_blocks = -+ (dev->internal_end_block - dev->internal_start_block + 1); -+ -+ int ok; -+ -+ ok = (yaffs2_checkpt_rd(dev, &cp, sizeof(cp)) == sizeof(cp)); -+ if (!ok) -+ return 0; -+ -+ if (cp.struct_type != sizeof(cp)) -+ return 0; -+ -+ yaffs_checkpt_dev_to_dev(dev, &cp); -+ -+ n_bytes = n_blocks * sizeof(struct yaffs_block_info); -+ -+ ok = (yaffs2_checkpt_rd(dev, dev->block_info, n_bytes) == n_bytes); -+ -+ if (!ok) -+ return 0; -+ n_bytes = n_blocks * dev->chunk_bit_stride; -+ -+ ok = (yaffs2_checkpt_rd(dev, dev->chunk_bits, n_bytes) == n_bytes); -+ -+ return ok ? 1 : 0; -+} -+ -+static void yaffs2_obj_checkpt_obj(struct yaffs_checkpt_obj *cp, -+ struct yaffs_obj *obj) -+{ -+ -+ cp->obj_id = obj->obj_id; -+ cp->parent_id = (obj->parent) ? obj->parent->obj_id : 0; -+ cp->hdr_chunk = obj->hdr_chunk; -+ cp->variant_type = obj->variant_type; -+ cp->deleted = obj->deleted; -+ cp->soft_del = obj->soft_del; -+ cp->unlinked = obj->unlinked; -+ cp->fake = obj->fake; -+ cp->rename_allowed = obj->rename_allowed; -+ cp->unlink_allowed = obj->unlink_allowed; -+ cp->serial = obj->serial; -+ cp->n_data_chunks = obj->n_data_chunks; -+ -+ if (obj->variant_type == YAFFS_OBJECT_TYPE_FILE) -+ cp->size_or_equiv_obj = obj->variant.file_variant.file_size; -+ else if (obj->variant_type == YAFFS_OBJECT_TYPE_HARDLINK) -+ cp->size_or_equiv_obj = obj->variant.hardlink_variant.equiv_id; -+} -+ -+static int taffs2_checkpt_obj_to_obj(struct yaffs_obj *obj, -+ struct yaffs_checkpt_obj *cp) -+{ -+ -+ struct yaffs_obj *parent; -+ -+ if (obj->variant_type != cp->variant_type) { -+ T(YAFFS_TRACE_ERROR, (TSTR("Checkpoint read object %d type %d " -+ TCONT -+ ("chunk %d does not match existing object type %d") -+ TENDSTR), cp->obj_id, -+ cp->variant_type, cp->hdr_chunk, -+ obj->variant_type)); -+ return 0; -+ } -+ -+ obj->obj_id = cp->obj_id; -+ -+ if (cp->parent_id) -+ parent = yaffs_find_or_create_by_number(obj->my_dev, -+ cp->parent_id, -+ YAFFS_OBJECT_TYPE_DIRECTORY); -+ else -+ parent = NULL; -+ -+ if (parent) { -+ if (parent->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) { -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR -+ ("Checkpoint read object %d parent %d type %d" -+ TCONT(" chunk %d Parent type, %d, not directory") -+ TENDSTR), cp->obj_id, cp->parent_id, -+ cp->variant_type, cp->hdr_chunk, -+ parent->variant_type)); -+ return 0; -+ } -+ yaffs_add_obj_to_dir(parent, obj); -+ } -+ -+ obj->hdr_chunk = cp->hdr_chunk; -+ obj->variant_type = cp->variant_type; -+ obj->deleted = cp->deleted; -+ obj->soft_del = cp->soft_del; -+ obj->unlinked = cp->unlinked; -+ obj->fake = cp->fake; -+ obj->rename_allowed = cp->rename_allowed; -+ obj->unlink_allowed = cp->unlink_allowed; -+ obj->serial = cp->serial; -+ obj->n_data_chunks = cp->n_data_chunks; -+ -+ if (obj->variant_type == YAFFS_OBJECT_TYPE_FILE) -+ obj->variant.file_variant.file_size = cp->size_or_equiv_obj; -+ else if (obj->variant_type == YAFFS_OBJECT_TYPE_HARDLINK) -+ obj->variant.hardlink_variant.equiv_id = cp->size_or_equiv_obj; -+ -+ if (obj->hdr_chunk > 0) -+ obj->lazy_loaded = 1; -+ return 1; -+} -+ -+static int yaffs2_checkpt_tnode_worker(struct yaffs_obj *in, -+ struct yaffs_tnode *tn, u32 level, -+ int chunk_offset) -+{ -+ int i; -+ struct yaffs_dev *dev = in->my_dev; -+ int ok = 1; -+ -+ if (tn) { -+ if (level > 0) { -+ -+ for (i = 0; i < YAFFS_NTNODES_INTERNAL && ok; i++) { -+ if (tn->internal[i]) { -+ ok = yaffs2_checkpt_tnode_worker(in, -+ tn-> -+ internal -+ [i], -+ level - -+ 1, -+ (chunk_offset -+ << -+ YAFFS_TNODES_INTERNAL_BITS) -+ + i); -+ } -+ } -+ } else if (level == 0) { -+ u32 base_offset = -+ chunk_offset << YAFFS_TNODES_LEVEL0_BITS; -+ ok = (yaffs2_checkpt_wr -+ (dev, &base_offset, -+ sizeof(base_offset)) == sizeof(base_offset)); -+ if (ok) -+ ok = (yaffs2_checkpt_wr -+ (dev, tn, -+ dev->tnode_size) == dev->tnode_size); -+ } -+ } -+ -+ return ok; -+ -+} -+ -+static int yaffs2_wr_checkpt_tnodes(struct yaffs_obj *obj) -+{ -+ u32 end_marker = ~0; -+ int ok = 1; -+ -+ if (obj->variant_type == YAFFS_OBJECT_TYPE_FILE) { -+ ok = yaffs2_checkpt_tnode_worker(obj, -+ obj->variant.file_variant.top, -+ obj->variant.file_variant. -+ top_level, 0); -+ if (ok) -+ ok = (yaffs2_checkpt_wr -+ (obj->my_dev, &end_marker, -+ sizeof(end_marker)) == sizeof(end_marker)); -+ } -+ -+ return ok ? 1 : 0; -+} -+ -+static int yaffs2_rd_checkpt_tnodes(struct yaffs_obj *obj) -+{ -+ u32 base_chunk; -+ int ok = 1; -+ struct yaffs_dev *dev = obj->my_dev; -+ struct yaffs_file_var *file_stuct_ptr = &obj->variant.file_variant; -+ struct yaffs_tnode *tn; -+ int nread = 0; -+ -+ ok = (yaffs2_checkpt_rd(dev, &base_chunk, sizeof(base_chunk)) == -+ sizeof(base_chunk)); -+ -+ while (ok && (~base_chunk)) { -+ nread++; -+ /* Read level 0 tnode */ -+ -+ tn = yaffs_get_tnode(dev); -+ if (tn) { -+ ok = (yaffs2_checkpt_rd(dev, tn, dev->tnode_size) == -+ dev->tnode_size); -+ } else { -+ ok = 0; -+ } -+ -+ if (tn && ok) -+ ok = yaffs_add_find_tnode_0(dev, -+ file_stuct_ptr, -+ base_chunk, tn) ? 1 : 0; -+ -+ if (ok) -+ ok = (yaffs2_checkpt_rd -+ (dev, &base_chunk, -+ sizeof(base_chunk)) == sizeof(base_chunk)); -+ -+ } -+ -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR("Checkpoint read tnodes %d records, last %d. ok %d" TENDSTR), -+ nread, base_chunk, ok)); -+ -+ return ok ? 1 : 0; -+} -+ -+static int yaffs2_wr_checkpt_objs(struct yaffs_dev *dev) -+{ -+ struct yaffs_obj *obj; -+ struct yaffs_checkpt_obj cp; -+ int i; -+ int ok = 1; -+ struct list_head *lh; -+ -+ /* Iterate through the objects in each hash entry, -+ * dumping them to the checkpointing stream. -+ */ -+ -+ for (i = 0; ok && i < YAFFS_NOBJECT_BUCKETS; i++) { -+ list_for_each(lh, &dev->obj_bucket[i].list) { -+ if (lh) { -+ obj = -+ list_entry(lh, struct yaffs_obj, hash_link); -+ if (!obj->defered_free) { -+ yaffs2_obj_checkpt_obj(&cp, obj); -+ cp.struct_type = sizeof(cp); -+ -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR -+ ("Checkpoint write object %d parent %d type %d chunk %d obj addr %p" -+ TENDSTR), cp.obj_id, cp.parent_id, -+ cp.variant_type, cp.hdr_chunk, obj)); -+ -+ ok = (yaffs2_checkpt_wr -+ (dev, &cp, -+ sizeof(cp)) == sizeof(cp)); -+ -+ if (ok -+ && obj->variant_type == -+ YAFFS_OBJECT_TYPE_FILE) -+ ok = yaffs2_wr_checkpt_tnodes -+ (obj); -+ } -+ } -+ } -+ } -+ -+ /* Dump end of list */ -+ memset(&cp, 0xFF, sizeof(struct yaffs_checkpt_obj)); -+ cp.struct_type = sizeof(cp); -+ -+ if (ok) -+ ok = (yaffs2_checkpt_wr(dev, &cp, sizeof(cp)) == sizeof(cp)); -+ -+ return ok ? 1 : 0; -+} -+ -+static int yaffs2_rd_checkpt_objs(struct yaffs_dev *dev) -+{ -+ struct yaffs_obj *obj; -+ struct yaffs_checkpt_obj cp; -+ int ok = 1; -+ int done = 0; -+ struct yaffs_obj *hard_list = NULL; -+ -+ while (ok && !done) { -+ ok = (yaffs2_checkpt_rd(dev, &cp, sizeof(cp)) == sizeof(cp)); -+ if (cp.struct_type != sizeof(cp)) { -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR("struct size %d instead of %d ok %d" TENDSTR), -+ cp.struct_type, (int)sizeof(cp), ok)); -+ ok = 0; -+ } -+ -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR -+ ("Checkpoint read object %d parent %d type %d chunk %d " -+ TENDSTR), cp.obj_id, cp.parent_id, cp.variant_type, -+ cp.hdr_chunk)); -+ -+ if (ok && cp.obj_id == ~0) { -+ done = 1; -+ } else if (ok) { -+ obj = -+ yaffs_find_or_create_by_number(dev, cp.obj_id, -+ cp.variant_type); -+ if (obj) { -+ ok = taffs2_checkpt_obj_to_obj(obj, &cp); -+ if (!ok) -+ break; -+ if (obj->variant_type == YAFFS_OBJECT_TYPE_FILE) { -+ ok = yaffs2_rd_checkpt_tnodes(obj); -+ } else if (obj->variant_type == -+ YAFFS_OBJECT_TYPE_HARDLINK) { -+ obj->hard_links.next = -+ (struct list_head *)hard_list; -+ hard_list = obj; -+ } -+ } else { -+ ok = 0; -+ } -+ } -+ } -+ -+ if (ok) -+ yaffs_link_fixup(dev, hard_list); -+ -+ return ok ? 1 : 0; -+} -+ -+static int yaffs2_wr_checkpt_sum(struct yaffs_dev *dev) -+{ -+ u32 checkpt_sum; -+ int ok; -+ -+ yaffs2_get_checkpt_sum(dev, &checkpt_sum); -+ -+ ok = (yaffs2_checkpt_wr(dev, &checkpt_sum, sizeof(checkpt_sum)) == -+ sizeof(checkpt_sum)); -+ -+ if (!ok) -+ return 0; -+ -+ return 1; -+} -+ -+static int yaffs2_rd_checkpt_sum(struct yaffs_dev *dev) -+{ -+ u32 checkpt_sum0; -+ u32 checkpt_sum1; -+ int ok; -+ -+ yaffs2_get_checkpt_sum(dev, &checkpt_sum0); -+ -+ ok = (yaffs2_checkpt_rd(dev, &checkpt_sum1, sizeof(checkpt_sum1)) == -+ sizeof(checkpt_sum1)); -+ -+ if (!ok) -+ return 0; -+ -+ if (checkpt_sum0 != checkpt_sum1) -+ return 0; -+ -+ return 1; -+} -+ -+static int yaffs2_wr_checkpt_data(struct yaffs_dev *dev) -+{ -+ int ok = 1; -+ -+ if (!yaffs2_checkpt_required(dev)) { -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR("skipping checkpoint write" TENDSTR))); -+ ok = 0; -+ } -+ -+ if (ok) -+ ok = yaffs2_checkpt_open(dev, 1); -+ -+ if (ok) { -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR("write checkpoint validity" TENDSTR))); -+ ok = yaffs2_wr_checkpt_validity_marker(dev, 1); -+ } -+ if (ok) { -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR("write checkpoint device" TENDSTR))); -+ ok = yaffs2_wr_checkpt_dev(dev); -+ } -+ if (ok) { -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR("write checkpoint objects" TENDSTR))); -+ ok = yaffs2_wr_checkpt_objs(dev); -+ } -+ if (ok) { -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR("write checkpoint validity" TENDSTR))); -+ ok = yaffs2_wr_checkpt_validity_marker(dev, 0); -+ } -+ -+ if (ok) -+ ok = yaffs2_wr_checkpt_sum(dev); -+ -+ if (!yaffs_checkpt_close(dev)) -+ ok = 0; -+ -+ if (ok) -+ dev->is_checkpointed = 1; -+ else -+ dev->is_checkpointed = 0; -+ -+ return dev->is_checkpointed; -+} -+ -+static int yaffs2_rd_checkpt_data(struct yaffs_dev *dev) -+{ -+ int ok = 1; -+ -+ if (!dev->param.is_yaffs2) -+ ok = 0; -+ -+ if (ok && dev->param.skip_checkpt_rd) { -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR("skipping checkpoint read" TENDSTR))); -+ ok = 0; -+ } -+ -+ if (ok) -+ ok = yaffs2_checkpt_open(dev, 0); /* open for read */ -+ -+ if (ok) { -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR("read checkpoint validity" TENDSTR))); -+ ok = yaffs2_rd_checkpt_validity_marker(dev, 1); -+ } -+ if (ok) { -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR("read checkpoint device" TENDSTR))); -+ ok = yaffs2_rd_checkpt_dev(dev); -+ } -+ if (ok) { -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR("read checkpoint objects" TENDSTR))); -+ ok = yaffs2_rd_checkpt_objs(dev); -+ } -+ if (ok) { -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR("read checkpoint validity" TENDSTR))); -+ ok = yaffs2_rd_checkpt_validity_marker(dev, 0); -+ } -+ -+ if (ok) { -+ ok = yaffs2_rd_checkpt_sum(dev); -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR("read checkpoint checksum %d" TENDSTR), ok)); -+ } -+ -+ if (!yaffs_checkpt_close(dev)) -+ ok = 0; -+ -+ if (ok) -+ dev->is_checkpointed = 1; -+ else -+ dev->is_checkpointed = 0; -+ -+ return ok ? 1 : 0; -+ -+} -+ -+void yaffs2_checkpt_invalidate(struct yaffs_dev *dev) -+{ -+ if (dev->is_checkpointed || dev->blocks_in_checkpt > 0) { -+ dev->is_checkpointed = 0; -+ yaffs2_checkpt_invalidate_stream(dev); -+ } -+ if (dev->param.sb_dirty_fn) -+ dev->param.sb_dirty_fn(dev); -+} -+ -+int yaffs_checkpoint_save(struct yaffs_dev *dev) -+{ -+ -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR("save entry: is_checkpointed %d" TENDSTR), -+ dev->is_checkpointed)); -+ -+ yaffs_verify_objects(dev); -+ yaffs_verify_blocks(dev); -+ yaffs_verify_free_chunks(dev); -+ -+ if (!dev->is_checkpointed) { -+ yaffs2_checkpt_invalidate(dev); -+ yaffs2_wr_checkpt_data(dev); -+ } -+ -+ T(YAFFS_TRACE_CHECKPOINT | YAFFS_TRACE_MOUNT, -+ (TSTR("save exit: is_checkpointed %d" TENDSTR), -+ dev->is_checkpointed)); -+ -+ return dev->is_checkpointed; -+} -+ -+int yaffs2_checkpt_restore(struct yaffs_dev *dev) -+{ -+ int retval; -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR("restore entry: is_checkpointed %d" TENDSTR), -+ dev->is_checkpointed)); -+ -+ retval = yaffs2_rd_checkpt_data(dev); -+ -+ if (dev->is_checkpointed) { -+ yaffs_verify_objects(dev); -+ yaffs_verify_blocks(dev); -+ yaffs_verify_free_chunks(dev); -+ } -+ -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR("restore exit: is_checkpointed %d" TENDSTR), -+ dev->is_checkpointed)); -+ -+ return retval; -+} -+ -+int yaffs2_handle_hole(struct yaffs_obj *obj, loff_t new_size) -+{ -+ /* if new_size > old_file_size. -+ * We're going to be writing a hole. -+ * If the hole is small then write zeros otherwise write a start of hole marker. -+ */ -+ -+ loff_t old_file_size; -+ int increase; -+ int small_hole; -+ int result = YAFFS_OK; -+ struct yaffs_dev *dev = NULL; -+ -+ u8 *local_buffer = NULL; -+ -+ int small_increase_ok = 0; -+ -+ if (!obj) -+ return YAFFS_FAIL; -+ -+ if (obj->variant_type != YAFFS_OBJECT_TYPE_FILE) -+ return YAFFS_FAIL; -+ -+ dev = obj->my_dev; -+ -+ /* Bail out if not yaffs2 mode */ -+ if (!dev->param.is_yaffs2) -+ return YAFFS_OK; -+ -+ old_file_size = obj->variant.file_variant.file_size; -+ -+ if (new_size <= old_file_size) -+ return YAFFS_OK; -+ -+ increase = new_size - old_file_size; -+ -+ if (increase < YAFFS_SMALL_HOLE_THRESHOLD * dev->data_bytes_per_chunk && -+ yaffs_check_alloc_available(dev, YAFFS_SMALL_HOLE_THRESHOLD + 1)) -+ small_hole = 1; -+ else -+ small_hole = 0; -+ -+ if (small_hole) -+ local_buffer = yaffs_get_temp_buffer(dev, __LINE__); -+ -+ if (local_buffer) { -+ /* fill hole with zero bytes */ -+ int pos = old_file_size; -+ int this_write; -+ int written; -+ memset(local_buffer, 0, dev->data_bytes_per_chunk); -+ small_increase_ok = 1; -+ -+ while (increase > 0 && small_increase_ok) { -+ this_write = increase; -+ if (this_write > dev->data_bytes_per_chunk) -+ this_write = dev->data_bytes_per_chunk; -+ written = -+ yaffs_do_file_wr(obj, local_buffer, pos, this_write, -+ 0); -+ if (written == this_write) { -+ pos += this_write; -+ increase -= this_write; -+ } else { -+ small_increase_ok = 0; -+ } -+ } -+ -+ yaffs_release_temp_buffer(dev, local_buffer, __LINE__); -+ -+ /* If we were out of space then reverse any chunks we've added */ -+ if (!small_increase_ok) -+ yaffs_resize_file_down(obj, old_file_size); -+ } -+ -+ if (!small_increase_ok && -+ obj->parent && -+ obj->parent->obj_id != YAFFS_OBJECTID_UNLINKED && -+ obj->parent->obj_id != YAFFS_OBJECTID_DELETED) { -+ /* Write a hole start header with the old file size */ -+ yaffs_update_oh(obj, NULL, 0, 1, 0, NULL); -+ } -+ -+ return result; -+ -+} -+ -+struct yaffs_block_index { -+ int seq; -+ int block; -+}; -+ -+static int yaffs2_ybicmp(const void *a, const void *b) -+{ -+ int aseq = ((struct yaffs_block_index *)a)->seq; -+ int bseq = ((struct yaffs_block_index *)b)->seq; -+ int ablock = ((struct yaffs_block_index *)a)->block; -+ int bblock = ((struct yaffs_block_index *)b)->block; -+ if (aseq == bseq) -+ return ablock - bblock; -+ else -+ return aseq - bseq; -+} -+ -+int yaffs2_scan_backwards(struct yaffs_dev *dev) -+{ -+ struct yaffs_ext_tags tags; -+ int blk; -+ int block_iter; -+ int start_iter; -+ int end_iter; -+ int n_to_scan = 0; -+ -+ int chunk; -+ int result; -+ int c; -+ int deleted; -+ enum yaffs_block_state state; -+ struct yaffs_obj *hard_list = NULL; -+ struct yaffs_block_info *bi; -+ u32 seq_number; -+ struct yaffs_obj_hdr *oh; -+ struct yaffs_obj *in; -+ struct yaffs_obj *parent; -+ int n_blocks = dev->internal_end_block - dev->internal_start_block + 1; -+ int is_unlinked; -+ u8 *chunk_data; -+ -+ int file_size; -+ int is_shrink; -+ int found_chunks; -+ int equiv_id; -+ int alloc_failed = 0; -+ -+ struct yaffs_block_index *block_index = NULL; -+ int alt_block_index = 0; -+ -+ T(YAFFS_TRACE_SCAN, -+ (TSTR -+ ("yaffs2_scan_backwards starts intstartblk %d intendblk %d..." -+ TENDSTR), dev->internal_start_block, dev->internal_end_block)); -+ -+ dev->seq_number = YAFFS_LOWEST_SEQUENCE_NUMBER; -+ -+ block_index = YMALLOC(n_blocks * sizeof(struct yaffs_block_index)); -+ -+ if (!block_index) { -+ block_index = -+ YMALLOC_ALT(n_blocks * sizeof(struct yaffs_block_index)); -+ alt_block_index = 1; -+ } -+ -+ if (!block_index) { -+ T(YAFFS_TRACE_SCAN, -+ (TSTR -+ ("yaffs2_scan_backwards() could not allocate block index!" -+ TENDSTR))); -+ return YAFFS_FAIL; -+ } -+ -+ dev->blocks_in_checkpt = 0; -+ -+ chunk_data = yaffs_get_temp_buffer(dev, __LINE__); -+ -+ /* Scan all the blocks to determine their state */ -+ bi = dev->block_info; -+ for (blk = dev->internal_start_block; blk <= dev->internal_end_block; -+ blk++) { -+ yaffs_clear_chunk_bits(dev, blk); -+ bi->pages_in_use = 0; -+ bi->soft_del_pages = 0; -+ -+ yaffs_query_init_block_state(dev, blk, &state, &seq_number); -+ -+ bi->block_state = state; -+ bi->seq_number = seq_number; -+ -+ if (bi->seq_number == YAFFS_SEQUENCE_CHECKPOINT_DATA) -+ bi->block_state = state = YAFFS_BLOCK_STATE_CHECKPOINT; -+ if (bi->seq_number == YAFFS_SEQUENCE_BAD_BLOCK) -+ bi->block_state = state = YAFFS_BLOCK_STATE_DEAD; -+ -+ T(YAFFS_TRACE_SCAN_DEBUG, -+ (TSTR("Block scanning block %d state %d seq %d" TENDSTR), blk, -+ state, seq_number)); -+ -+ if (state == YAFFS_BLOCK_STATE_CHECKPOINT) { -+ dev->blocks_in_checkpt++; -+ -+ } else if (state == YAFFS_BLOCK_STATE_DEAD) { -+ T(YAFFS_TRACE_BAD_BLOCKS, -+ (TSTR("block %d is bad" TENDSTR), blk)); -+ } else if (state == YAFFS_BLOCK_STATE_EMPTY) { -+ T(YAFFS_TRACE_SCAN_DEBUG, -+ (TSTR("Block empty " TENDSTR))); -+ dev->n_erased_blocks++; -+ dev->n_free_chunks += dev->param.chunks_per_block; -+ } else if (state == YAFFS_BLOCK_STATE_NEEDS_SCANNING) { -+ -+ /* Determine the highest sequence number */ -+ if (seq_number >= YAFFS_LOWEST_SEQUENCE_NUMBER && -+ seq_number < YAFFS_HIGHEST_SEQUENCE_NUMBER) { -+ -+ block_index[n_to_scan].seq = seq_number; -+ block_index[n_to_scan].block = blk; -+ -+ n_to_scan++; -+ -+ if (seq_number >= dev->seq_number) -+ dev->seq_number = seq_number; -+ } else { -+ /* TODO: Nasty sequence number! */ -+ T(YAFFS_TRACE_SCAN, -+ (TSTR -+ ("Block scanning block %d has bad sequence number %d" -+ TENDSTR), blk, seq_number)); -+ -+ } -+ } -+ bi++; -+ } -+ -+ T(YAFFS_TRACE_SCAN, -+ (TSTR("%d blocks to be sorted..." TENDSTR), n_to_scan)); -+ -+ YYIELD(); -+ -+ /* Sort the blocks by sequence number */ -+ yaffs_sort(block_index, n_to_scan, sizeof(struct yaffs_block_index), -+ yaffs2_ybicmp); -+ -+ YYIELD(); -+ -+ T(YAFFS_TRACE_SCAN, (TSTR("...done" TENDSTR))); -+ -+ /* Now scan the blocks looking at the data. */ -+ start_iter = 0; -+ end_iter = n_to_scan - 1; -+ T(YAFFS_TRACE_SCAN_DEBUG, -+ (TSTR("%d blocks to be scanned" TENDSTR), n_to_scan)); -+ -+ /* For each block.... backwards */ -+ for (block_iter = end_iter; !alloc_failed && block_iter >= start_iter; -+ block_iter--) { -+ /* Cooperative multitasking! This loop can run for so -+ long that watchdog timers expire. */ -+ YYIELD(); -+ -+ /* get the block to scan in the correct order */ -+ blk = block_index[block_iter].block; -+ -+ bi = yaffs_get_block_info(dev, blk); -+ -+ state = bi->block_state; -+ -+ deleted = 0; -+ -+ /* For each chunk in each block that needs scanning.... */ -+ found_chunks = 0; -+ for (c = dev->param.chunks_per_block - 1; -+ !alloc_failed && c >= 0 && -+ (state == YAFFS_BLOCK_STATE_NEEDS_SCANNING || -+ state == YAFFS_BLOCK_STATE_ALLOCATING); c--) { -+ /* Scan backwards... -+ * Read the tags and decide what to do -+ */ -+ -+ chunk = blk * dev->param.chunks_per_block + c; -+ -+ result = yaffs_rd_chunk_tags_nand(dev, chunk, NULL, -+ &tags); -+ -+ /* Let's have a good look at this chunk... */ -+ -+ if (!tags.chunk_used) { -+ /* An unassigned chunk in the block. -+ * If there are used chunks after this one, then -+ * it is a chunk that was skipped due to failing the erased -+ * check. Just skip it so that it can be deleted. -+ * But, more typically, We get here when this is an unallocated -+ * chunk and his means that either the block is empty or -+ * this is the one being allocated from -+ */ -+ -+ if (found_chunks) { -+ /* This is a chunk that was skipped due to failing the erased check */ -+ } else if (c == 0) { -+ /* We're looking at the first chunk in the block so the block is unused */ -+ state = YAFFS_BLOCK_STATE_EMPTY; -+ dev->n_erased_blocks++; -+ } else { -+ if (state == -+ YAFFS_BLOCK_STATE_NEEDS_SCANNING -+ || state == -+ YAFFS_BLOCK_STATE_ALLOCATING) { -+ if (dev->seq_number == -+ bi->seq_number) { -+ /* this is the block being allocated from */ -+ -+ T(YAFFS_TRACE_SCAN, -+ (TSTR -+ (" Allocating from %d %d" -+ TENDSTR), blk, c)); -+ -+ state = -+ YAFFS_BLOCK_STATE_ALLOCATING; -+ dev->alloc_block = blk; -+ dev->alloc_page = c; -+ dev-> -+ alloc_block_finder = -+ blk; -+ } else { -+ /* This is a partially written block that is not -+ * the current allocation block. -+ */ -+ -+ T(YAFFS_TRACE_SCAN, -+ (TSTR -+ ("Partially written block %d detected" -+ TENDSTR), blk)); -+ } -+ } -+ } -+ -+ dev->n_free_chunks++; -+ -+ } else if (tags.ecc_result == YAFFS_ECC_RESULT_UNFIXED) { -+ T(YAFFS_TRACE_SCAN, -+ (TSTR -+ (" Unfixed ECC in chunk(%d:%d), chunk ignored" -+ TENDSTR), blk, c)); -+ -+ dev->n_free_chunks++; -+ -+ } else if (tags.obj_id > YAFFS_MAX_OBJECT_ID || -+ tags.chunk_id > YAFFS_MAX_CHUNK_ID || -+ (tags.chunk_id > 0 -+ && tags.n_bytes > dev->data_bytes_per_chunk) -+ || tags.seq_number != bi->seq_number) { -+ T(YAFFS_TRACE_SCAN, -+ (TSTR -+ ("Chunk (%d:%d) with bad tags:obj = %d, chunk_id = %d, n_bytes = %d, ignored" -+ TENDSTR), blk, c, tags.obj_id, -+ tags.chunk_id, tags.n_bytes)); -+ -+ dev->n_free_chunks++; -+ -+ } else if (tags.chunk_id > 0) { -+ /* chunk_id > 0 so it is a data chunk... */ -+ unsigned int endpos; -+ u32 chunk_base = -+ (tags.chunk_id - -+ 1) * dev->data_bytes_per_chunk; -+ -+ found_chunks = 1; -+ -+ yaffs_set_chunk_bit(dev, blk, c); -+ bi->pages_in_use++; -+ -+ in = yaffs_find_or_create_by_number(dev, -+ tags.obj_id, -+ YAFFS_OBJECT_TYPE_FILE); -+ if (!in) { -+ /* Out of memory */ -+ alloc_failed = 1; -+ } -+ -+ if (in && -+ in->variant_type == YAFFS_OBJECT_TYPE_FILE -+ && chunk_base < -+ in->variant.file_variant.shrink_size) { -+ /* This has not been invalidated by a resize */ -+ if (!yaffs_put_chunk_in_file -+ (in, tags.chunk_id, chunk, -1)) { -+ alloc_failed = 1; -+ } -+ -+ /* File size is calculated by looking at the data chunks if we have not -+ * seen an object header yet. Stop this practice once we find an object header. -+ */ -+ endpos = chunk_base + tags.n_bytes; -+ -+ if (!in->valid && /* have not got an object header yet */ -+ in->variant.file_variant. -+ scanned_size < endpos) { -+ in->variant.file_variant. -+ scanned_size = endpos; -+ in->variant.file_variant. -+ file_size = endpos; -+ } -+ -+ } else if (in) { -+ /* This chunk has been invalidated by a resize, or a past file deletion -+ * so delete the chunk*/ -+ yaffs_chunk_del(dev, chunk, 1, -+ __LINE__); -+ -+ } -+ } else { -+ /* chunk_id == 0, so it is an ObjectHeader. -+ * Thus, we read in the object header and make the object -+ */ -+ found_chunks = 1; -+ -+ yaffs_set_chunk_bit(dev, blk, c); -+ bi->pages_in_use++; -+ -+ oh = NULL; -+ in = NULL; -+ -+ if (tags.extra_available) { -+ in = yaffs_find_or_create_by_number(dev, -+ tags. -+ obj_id, -+ tags. -+ extra_obj_type); -+ if (!in) -+ alloc_failed = 1; -+ } -+ -+ if (!in || -+ (!in->valid && dev->param.disable_lazy_load) -+ || tags.extra_shadows || (!in->valid -+ && (tags.obj_id == -+ YAFFS_OBJECTID_ROOT -+ || tags. -+ obj_id == -+ YAFFS_OBJECTID_LOSTNFOUND))) -+ { -+ -+ /* If we don't have valid info then we need to read the chunk -+ * TODO In future we can probably defer reading the chunk and -+ * living with invalid data until needed. -+ */ -+ -+ result = yaffs_rd_chunk_tags_nand(dev, -+ chunk, -+ chunk_data, -+ NULL); -+ -+ oh = (struct yaffs_obj_hdr *)chunk_data; -+ -+ if (dev->param.inband_tags) { -+ /* Fix up the header if they got corrupted by inband tags */ -+ oh->shadows_obj = -+ oh->inband_shadowed_obj_id; -+ oh->is_shrink = -+ oh->inband_is_shrink; -+ } -+ -+ if (!in) { -+ in = yaffs_find_or_create_by_number(dev, tags.obj_id, oh->type); -+ if (!in) -+ alloc_failed = 1; -+ } -+ -+ } -+ -+ if (!in) { -+ /* TODO Hoosterman we have a problem! */ -+ T(YAFFS_TRACE_ERROR, -+ (TSTR -+ ("yaffs tragedy: Could not make object for object %d at chunk %d during scan" -+ TENDSTR), tags.obj_id, chunk)); -+ continue; -+ } -+ -+ if (in->valid) { -+ /* We have already filled this one. -+ * We have a duplicate that will be discarded, but -+ * we first have to suck out resize info if it is a file. -+ */ -+ -+ if ((in->variant_type == -+ YAFFS_OBJECT_TYPE_FILE) && ((oh -+ && -+ oh-> -+ type -+ == -+ YAFFS_OBJECT_TYPE_FILE) -+ || -+ (tags. -+ extra_available -+ && -+ tags. -+ extra_obj_type -+ == -+ YAFFS_OBJECT_TYPE_FILE))) -+ { -+ u32 this_size = -+ (oh) ? oh-> -+ file_size : -+ tags.extra_length; -+ u32 parent_obj_id = -+ (oh) ? oh->parent_obj_id : -+ tags.extra_parent_id; -+ -+ is_shrink = -+ (oh) ? oh-> -+ is_shrink : -+ tags.extra_is_shrink; -+ -+ /* If it is deleted (unlinked at start also means deleted) -+ * we treat the file size as being zeroed at this point. -+ */ -+ if (parent_obj_id == -+ YAFFS_OBJECTID_DELETED -+ || parent_obj_id == -+ YAFFS_OBJECTID_UNLINKED) { -+ this_size = 0; -+ is_shrink = 1; -+ } -+ -+ if (is_shrink -+ && in->variant.file_variant. -+ shrink_size > this_size) -+ in->variant. -+ file_variant. -+ shrink_size = -+ this_size; -+ -+ if (is_shrink) -+ bi->has_shrink_hdr = 1; -+ -+ } -+ /* Use existing - destroy this one. */ -+ yaffs_chunk_del(dev, chunk, 1, -+ __LINE__); -+ -+ } -+ -+ if (!in->valid && in->variant_type != -+ (oh ? oh->type : tags.extra_obj_type)) -+ T(YAFFS_TRACE_ERROR, -+ (TSTR -+ ("yaffs tragedy: Bad object type, " -+ TCONT -+ ("%d != %d, for object %d at chunk ") -+ TCONT("%d during scan") -+ TENDSTR), oh ? -+ oh->type : tags.extra_obj_type, -+ in->variant_type, tags.obj_id, -+ chunk)); -+ -+ if (!in->valid && -+ (tags.obj_id == YAFFS_OBJECTID_ROOT || -+ tags.obj_id == -+ YAFFS_OBJECTID_LOSTNFOUND)) { -+ /* We only load some info, don't fiddle with directory structure */ -+ in->valid = 1; -+ -+ if (oh) { -+ -+ in->yst_mode = oh->yst_mode; -+ yaffs_load_attribs(in, oh); -+ in->lazy_loaded = 0; -+ } else { -+ in->lazy_loaded = 1; -+ } -+ in->hdr_chunk = chunk; -+ -+ } else if (!in->valid) { -+ /* we need to load this info */ -+ -+ in->valid = 1; -+ in->hdr_chunk = chunk; -+ -+ if (oh) { -+ in->variant_type = oh->type; -+ -+ in->yst_mode = oh->yst_mode; -+ yaffs_load_attribs(in, oh); -+ -+ if (oh->shadows_obj > 0) -+ yaffs_handle_shadowed_obj -+ (dev, -+ oh->shadows_obj, -+ 1); -+ -+ yaffs_set_obj_name_from_oh(in, -+ oh); -+ parent = -+ yaffs_find_or_create_by_number -+ (dev, oh->parent_obj_id, -+ YAFFS_OBJECT_TYPE_DIRECTORY); -+ -+ file_size = oh->file_size; -+ is_shrink = oh->is_shrink; -+ equiv_id = oh->equiv_id; -+ -+ } else { -+ in->variant_type = -+ tags.extra_obj_type; -+ parent = -+ yaffs_find_or_create_by_number -+ (dev, tags.extra_parent_id, -+ YAFFS_OBJECT_TYPE_DIRECTORY); -+ file_size = tags.extra_length; -+ is_shrink = -+ tags.extra_is_shrink; -+ equiv_id = tags.extra_equiv_id; -+ in->lazy_loaded = 1; -+ -+ } -+ in->dirty = 0; -+ -+ if (!parent) -+ alloc_failed = 1; -+ -+ /* directory stuff... -+ * hook up to parent -+ */ -+ -+ if (parent && parent->variant_type == -+ YAFFS_OBJECT_TYPE_UNKNOWN) { -+ /* Set up as a directory */ -+ parent->variant_type = -+ YAFFS_OBJECT_TYPE_DIRECTORY; -+ INIT_LIST_HEAD(&parent-> -+ variant.dir_variant.children); -+ } else if (!parent -+ || parent->variant_type != -+ YAFFS_OBJECT_TYPE_DIRECTORY) { -+ /* Hoosterman, another problem.... -+ * We're trying to use a non-directory as a directory -+ */ -+ -+ T(YAFFS_TRACE_ERROR, -+ (TSTR -+ ("yaffs tragedy: attempting to use non-directory as a directory in scan. Put in lost+found." -+ TENDSTR))); -+ parent = dev->lost_n_found; -+ } -+ -+ yaffs_add_obj_to_dir(parent, in); -+ -+ is_unlinked = (parent == dev->del_dir) -+ || (parent == dev->unlinked_dir); -+ -+ if (is_shrink) { -+ /* Mark the block as having a shrink header */ -+ bi->has_shrink_hdr = 1; -+ } -+ -+ /* Note re hardlinks. -+ * Since we might scan a hardlink before its equivalent object is scanned -+ * we put them all in a list. -+ * After scanning is complete, we should have all the objects, so we run -+ * through this list and fix up all the chains. -+ */ -+ -+ switch (in->variant_type) { -+ case YAFFS_OBJECT_TYPE_UNKNOWN: -+ /* Todo got a problem */ -+ break; -+ case YAFFS_OBJECT_TYPE_FILE: -+ -+ if (in->variant. -+ file_variant.scanned_size < -+ file_size) { -+ /* This covers the case where the file size is greater -+ * than where the data is -+ * This will happen if the file is resized to be larger -+ * than its current data extents. -+ */ -+ in->variant. -+ file_variant. -+ file_size = -+ file_size; -+ in->variant. -+ file_variant. -+ scanned_size = -+ file_size; -+ } -+ -+ if (in->variant.file_variant. -+ shrink_size > file_size) -+ in->variant. -+ file_variant. -+ shrink_size = -+ file_size; -+ -+ break; -+ case YAFFS_OBJECT_TYPE_HARDLINK: -+ if (!is_unlinked) { -+ in->variant. -+ hardlink_variant. -+ equiv_id = equiv_id; -+ in->hard_links.next = -+ (struct list_head *) -+ hard_list; -+ hard_list = in; -+ } -+ break; -+ case YAFFS_OBJECT_TYPE_DIRECTORY: -+ /* Do nothing */ -+ break; -+ case YAFFS_OBJECT_TYPE_SPECIAL: -+ /* Do nothing */ -+ break; -+ case YAFFS_OBJECT_TYPE_SYMLINK: -+ if (oh) { -+ in->variant. -+ symlink_variant. -+ alias = -+ yaffs_clone_str(oh-> -+ alias); -+ if (!in->variant. -+ symlink_variant. -+ alias) -+ alloc_failed = -+ 1; -+ } -+ break; -+ } -+ -+ } -+ -+ } -+ -+ } /* End of scanning for each chunk */ -+ -+ if (state == YAFFS_BLOCK_STATE_NEEDS_SCANNING) { -+ /* If we got this far while scanning, then the block is fully allocated. */ -+ state = YAFFS_BLOCK_STATE_FULL; -+ } -+ -+ bi->block_state = state; -+ -+ /* Now let's see if it was dirty */ -+ if (bi->pages_in_use == 0 && -+ !bi->has_shrink_hdr && -+ bi->block_state == YAFFS_BLOCK_STATE_FULL) { -+ yaffs_block_became_dirty(dev, blk); -+ } -+ -+ } -+ -+ yaffs_skip_rest_of_block(dev); -+ -+ if (alt_block_index) -+ YFREE_ALT(block_index); -+ else -+ YFREE(block_index); -+ -+ /* Ok, we've done all the scanning. -+ * Fix up the hard link chains. -+ * We should now have scanned all the objects, now it's time to add these -+ * hardlinks. -+ */ -+ yaffs_link_fixup(dev, hard_list); -+ -+ yaffs_release_temp_buffer(dev, chunk_data, __LINE__); -+ -+ if (alloc_failed) -+ return YAFFS_FAIL; -+ -+ T(YAFFS_TRACE_SCAN, (TSTR("yaffs2_scan_backwards ends" TENDSTR))); -+ -+ return YAFFS_OK; -+} -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_yaffs2.h linux-2.6.36/fs/yaffs2/yaffs_yaffs2.h ---- linux-2.6.36.orig/fs/yaffs2/yaffs_yaffs2.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_yaffs2.h 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,39 @@ -+/* -+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU Lesser General Public License version 2.1 as -+ * published by the Free Software Foundation. -+ * -+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. -+ */ -+ -+#ifndef __YAFFS_YAFFS2_H__ -+#define __YAFFS_YAFFS2_H__ -+ -+#include "yaffs_guts.h" -+ -+void yaffs_calc_oldest_dirty_seq(struct yaffs_dev *dev); -+void yaffs2_find_oldest_dirty_seq(struct yaffs_dev *dev); -+void yaffs2_clear_oldest_dirty_seq(struct yaffs_dev *dev, -+ struct yaffs_block_info *bi); -+void yaffs2_update_oldest_dirty_seq(struct yaffs_dev *dev, unsigned block_no, -+ struct yaffs_block_info *bi); -+int yaffs_block_ok_for_gc(struct yaffs_dev *dev, struct yaffs_block_info *bi); -+u32 yaffs2_find_refresh_block(struct yaffs_dev *dev); -+int yaffs2_checkpt_required(struct yaffs_dev *dev); -+int yaffs_calc_checkpt_blocks_required(struct yaffs_dev *dev); -+ -+void yaffs2_checkpt_invalidate(struct yaffs_dev *dev); -+int yaffs2_checkpt_save(struct yaffs_dev *dev); -+int yaffs2_checkpt_restore(struct yaffs_dev *dev); -+ -+int yaffs2_handle_hole(struct yaffs_obj *obj, loff_t new_size); -+int yaffs2_scan_backwards(struct yaffs_dev *dev); -+ -+#endif -diff -Nur linux-2.6.36.orig/fs/yaffs2/yportenv.h linux-2.6.36/fs/yaffs2/yportenv.h ---- linux-2.6.36.orig/fs/yaffs2/yportenv.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yportenv.h 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,339 @@ -+/* -+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU Lesser General Public License version 2.1 as -+ * published by the Free Software Foundation. -+ * -+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. -+ */ -+ -+#ifndef __YPORTENV_H__ -+#define __YPORTENV_H__ -+ -+/* -+ * Define the MTD version in terms of Linux Kernel versions -+ * This allows yaffs to be used independantly of the kernel -+ * as well as with it. -+ */ -+ -+#define MTD_VERSION(a, b, c) (((a) << 16) + ((b) << 8) + (c)) -+ -+#if defined CONFIG_YAFFS_WINCE -+ -+#include "ywinceenv.h" -+ -+#elif defined __KERNEL__ -+ -+#include "moduleconfig.h" -+ -+/* Linux kernel */ -+ -+#include -+#define MTD_VERSION_CODE LINUX_VERSION_CODE -+ -+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19)) -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define YCHAR char -+#define YUCHAR unsigned char -+#define _Y(x) x -+#define yaffs_strcat(a, b) strcat(a, b) -+#define yaffs_strcpy(a, b) strcpy(a, b) -+#define yaffs_strncpy(a, b, c) strncpy(a, b, c) -+#define yaffs_strncmp(a, b, c) strncmp(a, b, c) -+#define yaffs_strnlen(s,m) strnlen(s,m) -+#define yaffs_sprintf sprintf -+#define yaffs_toupper(a) toupper(a) -+#define yaffs_sort(base, n, sz, cmp_fn) sort(base, n, sz, cmp_fn, NULL) -+ -+#define Y_INLINE __inline__ -+ -+#define YAFFS_LOSTNFOUND_NAME "lost+found" -+#define YAFFS_LOSTNFOUND_PREFIX "obj" -+ -+/* #define YPRINTF(x) printk x */ -+#define YMALLOC(x) kmalloc(x, GFP_NOFS) -+#define YFREE(x) kfree(x) -+#define YMALLOC_ALT(x) vmalloc(x) -+#define YFREE_ALT(x) vfree(x) -+#define YMALLOC_DMA(x) YMALLOC(x) -+ -+#define YYIELD() schedule() -+#define Y_DUMP_STACK() dump_stack() -+ -+#define YAFFS_ROOT_MODE 0755 -+#define YAFFS_LOSTNFOUND_MODE 0700 -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) -+#define Y_CURRENT_TIME CURRENT_TIME.tv_sec -+#define Y_TIME_CONVERT(x) (x).tv_sec -+#else -+#define Y_CURRENT_TIME CURRENT_TIME -+#define Y_TIME_CONVERT(x) (x) -+#endif -+ -+#define yaffs_sum_cmp(x, y) ((x) == (y)) -+#define yaffs_strcmp(a, b) strcmp(a, b) -+ -+#define TENDSTR "\n" -+#define TSTR(x) KERN_DEBUG x -+#define TCONT(x) x -+#define TOUT(p) printk p -+ -+#define compile_time_assertion(assertion) \ -+ ({ int x = __builtin_choose_expr(assertion, 0, (void)0); (void) x; }) -+ -+#elif defined CONFIG_YAFFS_DIRECT -+ -+#define MTD_VERSION_CODE MTD_VERSION(2, 6, 22) -+ -+/* Direct interface */ -+#include "ydirectenv.h" -+ -+#elif defined CONFIG_YAFFS_UTIL -+ -+/* Stuff for YAFFS utilities */ -+ -+#include "stdlib.h" -+#include "stdio.h" -+#include "string.h" -+ -+#define YMALLOC(x) malloc(x) -+#define YFREE(x) free(x) -+#define YMALLOC_ALT(x) malloc(x) -+#define YFREE_ALT(x) free(x) -+ -+#define YCHAR char -+#define YUCHAR unsigned char -+#define _Y(x) x -+#define yaffs_strcat(a, b) strcat(a, b) -+#define yaffs_strcpy(a, b) strcpy(a, b) -+#define yaffs_strncpy(a, b, c) strncpy(a, b, c) -+#define yaffs_strnlen(s,m) strnlen(s,m) -+#define yaffs_sprintf sprintf -+#define yaffs_toupper(a) toupper(a) -+ -+#define Y_INLINE inline -+ -+/* #define YINFO(s) YPRINTF(( __FILE__ " %d %s\n",__LINE__,s)) */ -+/* #define YALERT(s) YINFO(s) */ -+ -+#define TENDSTR "\n" -+#define TSTR(x) x -+#define TOUT(p) printf p -+ -+#define YAFFS_LOSTNFOUND_NAME "lost+found" -+#define YAFFS_LOSTNFOUND_PREFIX "obj" -+/* #define YPRINTF(x) printf x */ -+ -+#define YAFFS_ROOT_MODE 0755 -+#define YAFFS_LOSTNFOUND_MODE 0700 -+ -+#define yaffs_sum_cmp(x, y) ((x) == (y)) -+#define yaffs_strcmp(a, b) strcmp(a, b) -+ -+#else -+/* Should have specified a configuration type */ -+#error Unknown configuration -+ -+#endif -+ -+#if defined(CONFIG_YAFFS_DIRECT) || defined(CONFIG_YAFFS_WINCE) -+ -+#ifdef CONFIG_YAFFSFS_PROVIDE_VALUES -+ -+#ifndef O_RDONLY -+#define O_RDONLY 00 -+#endif -+ -+#ifndef O_WRONLY -+#define O_WRONLY 01 -+#endif -+ -+#ifndef O_RDWR -+#define O_RDWR 02 -+#endif -+ -+#ifndef O_CREAT -+#define O_CREAT 0100 -+#endif -+ -+#ifndef O_EXCL -+#define O_EXCL 0200 -+#endif -+ -+#ifndef O_TRUNC -+#define O_TRUNC 01000 -+#endif -+ -+#ifndef O_APPEND -+#define O_APPEND 02000 -+#endif -+ -+#ifndef SEEK_SET -+#define SEEK_SET 0 -+#endif -+ -+#ifndef SEEK_CUR -+#define SEEK_CUR 1 -+#endif -+ -+#ifndef SEEK_END -+#define SEEK_END 2 -+#endif -+ -+#ifndef EBUSY -+#define EBUSY 16 -+#endif -+ -+#ifndef ENODEV -+#define ENODEV 19 -+#endif -+ -+#ifndef EINVAL -+#define EINVAL 22 -+#endif -+ -+#ifndef ENFILE -+#define ENFILE 23 -+#endif -+ -+#ifndef EBADF -+#define EBADF 9 -+#endif -+ -+#ifndef EACCES -+#define EACCES 13 -+#endif -+ -+#ifndef EXDEV -+#define EXDEV 18 -+#endif -+ -+#ifndef ENOENT -+#define ENOENT 2 -+#endif -+ -+#ifndef ENOSPC -+#define ENOSPC 28 -+#endif -+ -+#ifndef ERANGE -+#define ERANGE 34 -+#endif -+ -+#ifndef ENODATA -+#define ENODATA 61 -+#endif -+ -+#ifndef ENOTEMPTY -+#define ENOTEMPTY 39 -+#endif -+ -+#ifndef ENAMETOOLONG -+#define ENAMETOOLONG 36 -+#endif -+ -+#ifndef ENOMEM -+#define ENOMEM 12 -+#endif -+ -+#ifndef EEXIST -+#define EEXIST 17 -+#endif -+ -+#ifndef ENOTDIR -+#define ENOTDIR 20 -+#endif -+ -+#ifndef EISDIR -+#define EISDIR 21 -+#endif -+ -+// Mode flags -+ -+#ifndef S_IFMT -+#define S_IFMT 0170000 -+#endif -+ -+#ifndef S_IFLNK -+#define S_IFLNK 0120000 -+#endif -+ -+#ifndef S_IFDIR -+#define S_IFDIR 0040000 -+#endif -+ -+#ifndef S_IFREG -+#define S_IFREG 0100000 -+#endif -+ -+#ifndef S_IREAD -+#define S_IREAD 0000400 -+#endif -+ -+#ifndef S_IWRITE -+#define S_IWRITE 0000200 -+#endif -+ -+#ifndef S_IEXEC -+#define S_IEXEC 0000100 -+#endif -+ -+#ifndef XATTR_CREATE -+#define XATTR_CREATE 1 -+#endif -+ -+#ifndef XATTR_REPLACE -+#define XATTR_REPLACE 2 -+#endif -+ -+#ifndef R_OK -+#define R_OK 4 -+#define W_OK 2 -+#define X_OK 1 -+#define F_OK 0 -+#endif -+ -+#else -+#include -+#include -+#include -+#endif -+ -+#endif -+ -+#ifndef Y_DUMP_STACK -+#define Y_DUMP_STACK() do { } while (0) -+#endif -+ -+#ifndef YBUG -+#define YBUG() do {\ -+ T(YAFFS_TRACE_BUG,\ -+ (TSTR("==>> yaffs bug: " __FILE__ " %d" TENDSTR),\ -+ __LINE__));\ -+ Y_DUMP_STACK();\ -+} while (0) -+#endif -+ -+#endif diff --git a/target/linux/patches/2.6.36/zboot-brcm-reloc.patch b/target/linux/patches/2.6.36/zboot-brcm-reloc.patch deleted file mode 100644 index 2ff2cce15..000000000 --- a/target/linux/patches/2.6.36/zboot-brcm-reloc.patch +++ /dev/null @@ -1,297 +0,0 @@ ---- /dev/null Thu Jan 6 02:10:11 2011 -+++ linux-2.6.36/arch/mips/boot/compressed/invcache.S Thu Jan 6 01:32:57 2011 -@@ -0,0 +1,132 @@ -+/*- -+ * written 2011 by Thorsten Glaser based on -+ * code from LZMA-Loader with the following copyright note: -+ * Copyright 2005 Oleg I. Vdovikin -+ * cache manipulation adapted from Broadcom code -+ * idea taken from original bunzip2 decompressor code -+ * Copyright 2004 Manuel Novoa III -+ */ -+ -+/* -+ * This file is supposed to be #include’d where it’s -+ * needed; we will not trash s0, s1, s2, s3. -+ */ -+ -+#define KSEG0 0x80000000 -+ -+#define C0_CONFIG $16 -+#define C0_TAGLO $28 -+#define C0_TAGHI $29 -+ -+#define CONF1_DA_SHIFT 7 /* D$ associativity */ -+#define CONF1_DA_MASK 0x00000380 -+#define CONF1_DA_BASE 1 -+#define CONF1_DL_SHIFT 10 /* D$ line size */ -+#define CONF1_DL_MASK 0x00001c00 -+#define CONF1_DL_BASE 2 -+#define CONF1_DS_SHIFT 13 /* D$ sets/way */ -+#define CONF1_DS_MASK 0x0000e000 -+#define CONF1_DS_BASE 64 -+#define CONF1_IA_SHIFT 16 /* I$ associativity */ -+#define CONF1_IA_MASK 0x00070000 -+#define CONF1_IA_BASE 1 -+#define CONF1_IL_SHIFT 19 /* I$ line size */ -+#define CONF1_IL_MASK 0x00380000 -+#define CONF1_IL_BASE 2 -+#define CONF1_IS_SHIFT 22 /* Instruction cache sets/way */ -+#define CONF1_IS_MASK 0x01c00000 -+#define CONF1_IS_BASE 64 -+ -+#define Index_Invalidate_I 0x00 -+#define Index_Writeback_Inv_D 0x01 -+ -+ /* Get cache sizes */ -+ .set mips32 -+ mfc0 s4,C0_CONFIG,1 -+ .set mips0 -+ -+ li s5,CONF1_DL_MASK -+ and s5,s4 -+ beq s5,zero,2f -+ nop -+ -+ srl s5,CONF1_DL_SHIFT -+ li t0,CONF1_DL_BASE -+ sll s5,t0,s5 /* s5 has D$ cache line size */ -+ -+ li s6,CONF1_DA_MASK -+ and s6,s4 -+ srl s6,CONF1_DA_SHIFT -+ addiu s6,CONF1_DA_BASE /* s6 now has D$ associativity */ -+ -+ li t0,CONF1_DS_MASK -+ and t0,s4 -+ srl t0,CONF1_DS_SHIFT -+ li s7,CONF1_DS_BASE -+ sll s7,s7,t0 /* s7 has D$ sets per way */ -+ -+ multu s6,s7 /* sets/way * associativity */ -+ mflo t0 /* total cache lines */ -+ -+ multu s5,t0 /* D$ linesize * lines */ -+ mflo s6 /* s6 is now D$ size in bytes */ -+ -+ /* Initilize the D$: */ -+ mtc0 zero,C0_TAGLO -+ mtc0 zero,C0_TAGHI -+ -+ li t0,KSEG0 /* Just an address for the first $ line */ -+ addu t1,t0,s6 /* + size of cache == end */ -+ -+ .set mips3 -+1: cache Index_Writeback_Inv_D,0(t0) -+ .set mips0 -+ bne t0,t1,1b -+ addu t0,s5 -+ -+2: -+ /* Now we get to do it all again for the I$ */ -+ -+ move s7,zero /* just in case there is no icache */ -+ move t8,zero -+ -+ li t0,CONF1_IL_MASK -+ and t0,s4 -+ beq t0,zero,3f -+ nop -+ -+ srl t0,CONF1_IL_SHIFT -+ li s7,CONF1_IL_BASE -+ sll s7,t0 /* s7 has I$ cache line size */ -+ -+ li t0,CONF1_IA_MASK -+ and t0,s4 -+ srl t0,CONF1_IA_SHIFT -+ addiu t8,t0,CONF1_IA_BASE /* t8 now has I$ associativity */ -+ -+ li t0,CONF1_IS_MASK -+ and t0,s4 -+ srl t0,CONF1_IS_SHIFT -+ li t9,CONF1_IS_BASE -+ sll t9,t0 /* t9 has I$ sets per way */ -+ -+ multu t8,t9 /* sets/way * associativity */ -+ mflo t0 /* t8 is now total cache lines */ -+ -+ multu s7,t0 /* I$ linesize * lines */ -+ mflo t8 /* t8 is cache size in bytes */ -+ -+ /* Initilize the I$: */ -+ mtc0 zero,C0_TAGLO -+ mtc0 zero,C0_TAGHI -+ -+ li t0,KSEG0 /* Just an address for the first $ line */ -+ addu t1,t0,t8 /* + size of cache == end */ -+ -+ .set mips3 -+1: cache Index_Invalidate_I,0(t0) -+ .set mips0 -+ bne t0,t1,1b -+ addu t0,s7 -+ -+3: ---- /dev/null Thu Jan 6 00:14:18 2011 -+++ linux-2.6.36/arch/mips/boot/compressed/selfreloc.lds.S Wed Jan 5 23:52:43 2011 -@@ -0,0 +1,39 @@ -+/*- -+ * written 2010 by Thorsten Glaser based on -+ * arch/mips/kernel/vmlinux.lds and arch/mips/boot/compressed/ld.script -+ */ -+ -+#include -+#include -+#include -+ -+#undef mips -+#define mips mips -+OUTPUT_ARCH(mips) -+ENTRY(selfreloc_start) -+PHDRS { -+ text PT_LOAD FLAGS(7); /* RWX */ -+} -+SECTIONS -+{ -+ . = VMLINUX_LOAD_ADDRESS; -+ .text : { -+ *(.text) -+ *(.text.*) -+ *(.rodata) -+ *(.rodata.*) -+ *(.data) -+ *(.data.*) -+ *(.bss) -+ *(.bss.*) -+ } :text -+ /DISCARD/ : { -+ *(.MIPS.options) -+ *(.options) -+ *(.pdr) -+ *(.reginfo) -+ *(.comment) -+ *(.note) -+ *(.gnu.attributes) -+ } -+} ---- /dev/null Thu Jan 6 02:10:14 2011 -+++ linux-2.6.36/arch/mips/boot/compressed/selfreloc.S Thu Jan 6 01:21:44 2011 -@@ -0,0 +1,60 @@ -+/*- -+ * written 2011 by Thorsten Glaser based on -+ * arch/mips/boot/compressed/head.S and code from LZMA-Loader -+ */ -+ -+#include -+#include -+ -+ .set noreorder -+ .cprestore -+ -+ .text -+ LEAF(selfreloc_start) -+selfreloc_start: -+ /* Save boot rom start args */ -+ move s0, a0 -+ move s1, a1 -+ move s2, a2 -+ move s3, a3 -+ -+ /* Copy code to the correct place */ -+ PTR_LI a0, VMLINUZ_LOAD_ADDRESS -+ PTR_LA a1, imgbeg -+ PTR_LA a2, imgend -+1: lw t0, 0(a1) -+ sw t0, 0(a0) -+ add a1, 4 -+ add a0, 4 -+ blt a1, a2, 1b -+ nop -+ -+ /* -+ * At this point we need to invalidate dcache and -+ * icache before jumping to the new code -+ */ -+/* #include "invcache.S" // since this may work only on brcm? */ -+ -+ /* Restore boot rom start args */ -+ move a0, s0 -+ move a1, s1 -+ move a2, s2 -+ move a3, s3 -+ -+ /* Jump to the code at its new location */ -+ PTR_LI k0, VMLINUZ_LOAD_ADDRESS -+ jr k0 -+ nop -+ -+ /* Just in case we come back… */ -+3: -+ b 3b -+ nop -+ END(selfreloc_start) -+ -+ .globl imgbeg -+ .p2align 2 -+imgbeg: .incbin "vmlinuz.bin" -+ .globl imgend -+ .p2align 2 -+imgend: ---- linux-2.6.36/arch/mips/boot/compressed/Makefile~ Wed Jan 5 21:26:40 2011 -+++ linux-2.6.36/arch/mips/boot/compressed/Makefile Wed Jan 5 23:35:58 2011 -@@ -62,8 +62,13 @@ $(obj)/piggy.o: $(obj)/dummy.o $(obj)/vm - # Calculate the load address of the compressed kernel image - hostprogs-y := calc_vmlinuz_load_addr - -+ifdef CONFIG_BCM47XX -+# XXX just after CFE, just pray the address is static -+VMLINUZ_LOAD_ADDRESS = 0xffffffff80480000 -+else - VMLINUZ_LOAD_ADDRESS = $(shell $(obj)/calc_vmlinuz_load_addr \ - $(obj)/vmlinux.bin $(VMLINUX_LOAD_ADDRESS)) -+endif - - vmlinuzobjs-y += $(obj)/piggy.o - -@@ -106,4 +107,12 @@ OBJCOPYFLAGS_vmlinuz.srec := $(OBJCOPYFL - vmlinuz.srec: vmlinuz - $(call cmd,objcopy) - --clean-files := $(objtree)/vmlinuz $(objtree)/vmlinuz.{32,ecoff,bin,srec} -+AFLAGS_selfreloc.o := -DVMLINUZ_LOAD_ADDRESS=$(VMLINUZ_LOAD_ADDRESS) -+arch/mips/boot/compressed/selfreloc.o: arch/mips/boot/compressed/selfreloc.S vmlinuz.bin arch/mips/boot/compressed/invcache.S -+ -+CPPFLAGS_selfreloc.lds := $(KBUILD_CFLAGS) -+ -+vmlinub.elf: arch/mips/boot/compressed/selfreloc.o arch/mips/boot/compressed/selfreloc.lds -+ $(LD) $(LDFLAGS) -T arch/mips/boot/compressed/selfreloc.lds arch/mips/boot/compressed/selfreloc.o -o $@ -+ -+clean-files := $(objtree)/vmlinuz $(objtree)/vmlinuz.{32,ecoff,bin,srec} $(objtree)/vmlinub.elf $(objtree)/arch/mips/boot/compressed/selfreloc.{o,lds} ---- linux-2.6.36/arch/mips/Makefile~ Wed Jan 5 20:26:12 2011 -+++ linux-2.6.36/arch/mips/Makefile Wed Jan 5 22:41:38 2011 -@@ -79,6 +79,7 @@ endif - all-$(CONFIG_BOOT_ELF32) := $(vmlinux-32) - all-$(CONFIG_BOOT_ELF64) := $(vmlinux-64) - all-$(CONFIG_SYS_SUPPORTS_ZBOOT)+= vmlinuz -+all-$(CONFIG_BCM47XX) += vmlinub.elf - - # - # GCC uses -G 0 -mabicalls -fpic as default. We don't want PIC in the kernel -@@ -285,7 +286,7 @@ vmlinux.bin vmlinux.ecoff vmlinux.srec: - $(Q)$(MAKE) $(build)=arch/mips/boot VMLINUX=$(vmlinux-32) arch/mips/boot/$@ - - # boot/compressed --vmlinuz vmlinuz.bin vmlinuz.ecoff vmlinuz.srec: $(vmlinux-32) FORCE -+vmlinuz vmlinuz.bin vmlinuz.ecoff vmlinuz.srec vmlinub.elf: $(vmlinux-32) FORCE - $(Q)$(MAKE) $(build)=arch/mips/boot/compressed \ - VMLINUX_LOAD_ADDRESS=$(load-y) 32bit-bfd=$(32bit-bfd) $@ - -@@ -322,6 +323,7 @@ define archhelp - echo ' vmlinuz.ecoff - ECOFF zboot image' - echo ' vmlinuz.bin - Raw binary zboot image' - echo ' vmlinuz.srec - SREC zboot image' -+ echo ' vmlinub.elf - ELF self-relocating zboot image' - echo - echo ' These will be default as apropriate for a configured platform.' - endef diff --git a/target/linux/patches/2.6.37/ar7.patch b/target/linux/patches/2.6.37/ar7.patch deleted file mode 100644 index 5f3b69ce1..000000000 --- a/target/linux/patches/2.6.37/ar7.patch +++ /dev/null @@ -1,90 +0,0 @@ -diff -Nur linux-2.6.36.orig/arch/mips/Kconfig linux-2.6.36/arch/mips/Kconfig ---- linux-2.6.36.orig/arch/mips/Kconfig 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/arch/mips/Kconfig 2010-12-16 21:02:19.000000000 +0100 -@@ -46,7 +46,6 @@ - select CEVT_R4K - select CSRC_R4K - select IRQ_CPU -- select NO_EXCEPT_FILL - select SWAP_IO_SPACE - select SYS_HAS_CPU_MIPS32_R1 - select SYS_HAS_EARLY_PRINTK -diff -Nur linux-2.6.36.orig/arch/mips/ar7/prom.c linux-2.6.36/arch/mips/ar7/prom.c ---- linux-2.6.36.orig/arch/mips/ar7/prom.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/arch/mips/ar7/prom.c 2010-12-16 21:02:19.000000000 +0100 -@@ -206,6 +206,14 @@ - if (strstr(arcs_cmdline, "console=")) - return; - -+#ifdef CONFIG_KGDB -+ if (!strstr(prom_getcmdline(), "nokgdb")) { -+ strcat(prom_getcmdline(), " console=kgdb"); -+ kgdb_enabled = 1; -+ return; -+ } -+#endif -+ - s = prom_getenv("modetty0"); - if (s) { - baud = simple_strtoul(s, &p, 10); -diff -Nur linux-2.6.36.orig/drivers/mtd/ar7part.c linux-2.6.36/drivers/mtd/ar7part.c ---- linux-2.6.36.orig/drivers/mtd/ar7part.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/drivers/mtd/ar7part.c 2010-12-16 21:02:19.000000000 +0100 -@@ -28,7 +28,7 @@ - #include - #include - --#define AR7_PARTS 4 -+#define AR7_PARTS 5 - #define ROOT_OFFSET 0xe0000 - - #define LOADER_MAGIC1 le32_to_cpu(0xfeedfa42) -@@ -122,14 +122,19 @@ - - ar7_parts[2].name = "linux"; - ar7_parts[2].offset = pre_size; -- ar7_parts[2].size = master->size - pre_size - post_size; -+ ar7_parts[2].size = master->size - pre_size - post_size - 2*master->erasesize; - ar7_parts[2].mask_flags = 0; - - ar7_parts[3].name = "rootfs"; - ar7_parts[3].offset = root_offset; -- ar7_parts[3].size = master->size - root_offset - post_size; -+ ar7_parts[3].size = master->size - root_offset - post_size - 2*master->erasesize; - ar7_parts[3].mask_flags = 0; - -+ ar7_parts[4].name = "cfgfs"; -+ ar7_parts[4].offset = master->size - 2*master->erasesize; -+ ar7_parts[4].size = 2*master->erasesize; -+ ar7_parts[4].mask_flags = 0; -+ - *pparts = ar7_parts; - return AR7_PARTS; - } -diff -Nur linux-2.6.36.orig/drivers/mtd/maps/physmap.c linux-2.6.36/drivers/mtd/maps/physmap.c ---- linux-2.6.36.orig/drivers/mtd/maps/physmap.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/drivers/mtd/maps/physmap.c 2010-12-16 21:02:19.000000000 +0100 -@@ -79,7 +79,7 @@ - "map_rom", - NULL }; - #ifdef CONFIG_MTD_PARTITIONS --static const char *part_probe_types[] = { "cmdlinepart", "RedBoot", NULL }; -+static const char *part_probe_types[] = { "cmdlinepart", "RedBoot", "ar7part", NULL }; - #endif - - static int physmap_flash_probe(struct platform_device *dev) -diff -Nur linux-2.6.36.orig/drivers/serial/8250.c linux-2.6.36/drivers/serial/8250.c ---- linux-2.6.36.orig/drivers/serial/8250.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/drivers/serial/8250.c 2010-12-16 21:02:19.000000000 +0100 -@@ -2761,7 +2761,11 @@ - { - struct uart_8250_port *up = (struct uart_8250_port *)port; - -+#ifdef CONFIG_AR7 -+ wait_for_xmitr(up, BOTH_EMPTY); -+#else - wait_for_xmitr(up, UART_LSR_THRE); -+#endif - serial_out(up, UART_TX, ch); - } - diff --git a/target/linux/patches/2.6.37/ar71xx.patch b/target/linux/patches/2.6.37/ar71xx.patch deleted file mode 100644 index 059ac9dd5..000000000 --- a/target/linux/patches/2.6.37/ar71xx.patch +++ /dev/null @@ -1,18667 +0,0 @@ -diff -Nur linux-2.6.37.orig/arch/mips/Kconfig linux-2.6.37/arch/mips/Kconfig ---- linux-2.6.37.orig/arch/mips/Kconfig 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/mips/Kconfig 2011-01-11 20:25:48.000000000 +0100 -@@ -65,6 +65,23 @@ - Support for the Texas Instruments AR7 System-on-a-Chip - family: TNETD7100, 7200 and 7300. - -+config ATHEROS_AR71XX -+ bool "Atheros AR71xx based boards" -+ select CEVT_R4K -+ select CSRC_R4K -+ select DMA_NONCOHERENT -+ select HW_HAS_PCI -+ select IRQ_CPU -+ select ARCH_REQUIRE_GPIOLIB -+ select SYS_HAS_CPU_MIPS32_R1 -+ select SYS_HAS_CPU_MIPS32_R2 -+ select SYS_SUPPORTS_32BIT_KERNEL -+ select SYS_SUPPORTS_BIG_ENDIAN -+ select SYS_HAS_EARLY_PRINTK -+ select MIPS_MACHINE -+ help -+ Support for Atheros AR71xx based boards. -+ - config BCM47XX - bool "Broadcom BCM47XX based boards" - select CEVT_R4K -@@ -717,6 +734,7 @@ - endchoice - - source "arch/mips/alchemy/Kconfig" -+source "arch/mips/ar71xx/Kconfig" - source "arch/mips/bcm63xx/Kconfig" - source "arch/mips/jazz/Kconfig" - source "arch/mips/jz4740/Kconfig" -@@ -880,9 +898,15 @@ - config MIPS_DISABLE_OBSOLETE_IDE - bool - -+config MYLOADER -+ bool -+ - config SYNC_R4K - bool - -+config MIPS_MACHINE -+ def_bool n -+ - config NO_IOPORT - def_bool n - -diff -Nur linux-2.6.37.orig/arch/mips/Makefile linux-2.6.37/arch/mips/Makefile ---- linux-2.6.37.orig/arch/mips/Makefile 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/mips/Makefile 2011-01-11 20:25:48.000000000 +0100 -@@ -158,6 +158,13 @@ - endif - cflags-$(CONFIG_CAVIUM_CN63XXP1) += -Wa,-mfix-cn63xxp1 - -+# -+# Atheros AR71xx -+# -+core-$(CONFIG_ATHEROS_AR71XX) += arch/mips/ar71xx/ -+cflags-$(CONFIG_ATHEROS_AR71XX) += -I$(srctree)/arch/mips/include/asm/mach-ar71xx -+load-$(CONFIG_ATHEROS_AR71XX) += 0xffffffff80060000 -+ - cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,) - cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += $(call cc-option,-mfix-r4400,) - cflags-$(CONFIG_CPU_DADDI_WORKAROUNDS) += $(call cc-option,-mno-daddi,) -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/Kconfig linux-2.6.37/arch/mips/ar71xx/Kconfig ---- linux-2.6.37.orig/arch/mips/ar71xx/Kconfig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/Kconfig 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,264 @@ -+if ATHEROS_AR71XX -+ -+menu "Atheros AR71xx machine selection" -+ -+config AR71XX_MACH_AP81 -+ bool "Atheros AP81 board support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AR913X_WMAC -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ default n -+ -+config AR71XX_MACH_AP83 -+ bool "Atheros AP83 board support" -+ select AR71XX_DEV_AR913X_WMAC -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ default n -+ -+config AR71XX_MACH_DIR_600_A1 -+ bool "D-Link DIR-600 rev. A1 support" -+ select AR71XX_DEV_AP91_ETH -+ select AR71XX_DEV_AP91_PCI if PCI -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_NVRAM -+ default n -+ -+config AR71XX_MACH_DIR_615_C1 -+ bool "D-Link DIR-615 rev. C1 support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AR913X_WMAC -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_NVRAM -+ default n -+ -+config AR71XX_MACH_DIR_825_B1 -+ bool "D-Link DIR-825 rev. B1 board support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AP94_PCI if PCI -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ default n -+ -+config AR71XX_MACH_PB42 -+ bool "Atheros PB42 board support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_PB42_PCI if PCI -+ default n -+ -+config AR71XX_MACH_PB44 -+ bool "Atheros PB44 board support" -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_PB42_PCI if PCI -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ default n -+ -+config AR71XX_MACH_PB92 -+ bool "Atheros PB92 board support" -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_PB9X_PCI if PCI -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ default n -+ -+config AR71XX_MACH_AW_NR580 -+ bool "AzureWave AW-NR580 board support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_PB42_PCI if PCI -+ select AR71XX_DEV_LEDS_GPIO -+ default n -+ -+config AR71XX_MACH_WZR_HP_G300NH -+ bool "Buffalo WZR-HP-G300NH board support" -+ select AR71XX_DEV_AR913X_WMAC -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ default y -+ -+config AR71XX_MACH_WP543 -+ bool "Compex WP543/WPJ543 board support" -+ select MYLOADER -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_PB42_PCI if PCI -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ default n -+ -+config AR71XX_MACH_WRT160NL -+ bool "Linksys WRT160NL board support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AR913X_WMAC -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ select AR71XX_NVRAM -+ default n -+ -+config AR71XX_MACH_WRT400N -+ bool "Linksys WRT400N board support" -+ select AR71XX_DEV_AP94_PCI if PCI -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ default n -+ -+config AR71XX_MACH_RB4XX -+ bool "MikroTik RouterBOARD 4xx series support" -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ default n -+ -+config AR71XX_MACH_RB750 -+ bool "MikroTik RouterBOARD 750 support" -+ select AR71XX_DEV_AP91_ETH -+ default n -+ -+config AR71XX_MACH_WNDR3700 -+ bool "NETGEAR WNDR3700 board support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AP94_PCI if PCI -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ default n -+ -+config AR71XX_MACH_WNR2000 -+ bool "NETGEAR WNR2000 board support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AR913X_WMAC -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ default n -+ -+config AR71XX_MACH_MZK_W04NU -+ bool "Planex MZK-W04NU board support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AR913X_WMAC -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ default n -+ -+config AR71XX_MACH_MZK_W300NH -+ bool "Planex MZK-W300NH board support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AR913X_WMAC -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ default n -+ -+config AR71XX_MACH_NBG460N -+ bool "Zyxel NBG460N/550N/550NH board support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AR913X_WMAC -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ default n -+ -+config AR71XX_MACH_TL_WR741ND -+ bool "TP-LINK TL-WR741ND support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AP91_ETH -+ select AR71XX_DEV_AP91_PCI if PCI -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ default n -+ -+config AR71XX_MACH_TL_WR841N_V1 -+ bool "TP-LINK TL-WR841N v1 support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_PB42_PCI if PCI -+ select AR71XX_DEV_DSA -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ default n -+ -+config AR71XX_MACH_TL_WR941ND -+ bool "TP-LINK TL-WR941ND support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AR913X_WMAC -+ select AR71XX_DEV_DSA -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ default n -+ -+config AR71XX_MACH_TL_WR1043ND -+ bool "TP-LINK TL-WR1043ND support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AR913X_WMAC -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ default n -+ -+config AR71XX_MACH_TEW_632BRP -+ bool "TRENDnet TEW-632BRP support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AR913X_WMAC -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_NVRAM -+ default n -+ -+config AR71XX_MACH_UBNT -+ bool "Ubiquiti AR71xx based boards support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AP91_PCI if PCI -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_PB42_PCI if PCI -+ select AR71XX_DEV_USB -+ default n -+ -+endmenu -+ -+config AR71XX_DEV_M25P80 -+ def_bool n -+ -+config AR71XX_DEV_AP91_PCI -+ def_bool n -+ -+config AR71XX_DEV_AP91_ETH -+ def_bool n -+ -+config AR71XX_DEV_AP94_PCI -+ def_bool n -+ -+config AR71XX_DEV_AR913X_WMAC -+ def_bool n -+ -+config AR71XX_DEV_DSA -+ def_bool n -+ -+config AR71XX_DEV_GPIO_BUTTONS -+ def_bool n -+ -+config AR71XX_DEV_LEDS_GPIO -+ def_bool n -+ -+config AR71XX_DEV_PB42_PCI -+ def_bool n -+ -+config AR71XX_DEV_PB9X_PCI -+ def_bool n -+ -+config AR71XX_DEV_USB -+ def_bool n -+ -+config AR71XX_NVRAM -+ def_bool n -+ -+endif -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/Makefile linux-2.6.37/arch/mips/ar71xx/Makefile ---- linux-2.6.37.orig/arch/mips/ar71xx/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/Makefile 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,54 @@ -+# -+# Makefile for the Atheros AR71xx SoC specific parts of the kernel -+# -+# Copyright (C) 2008-2009 Gabor Juhos -+# Copyright (C) 2008 Imre Kaloz -+# -+# This program is free software; you can redistribute it and/or modify it -+# under the terms of the GNU General Public License version 2 as published -+# by the Free Software Foundation. -+ -+obj-y := prom.o irq.o setup.o devices.o gpio.o ar71xx.o -+ -+obj-$(CONFIG_EARLY_PRINTK) += early_printk.o -+obj-$(CONFIG_PCI) += pci.o -+ -+obj-$(CONFIG_AR71XX_DEV_AP91_ETH) += dev-ap91-eth.o -+obj-$(CONFIG_AR71XX_DEV_AP91_PCI) += dev-ap91-pci.o -+obj-$(CONFIG_AR71XX_DEV_AP94_PCI) += dev-ap94-pci.o -+obj-$(CONFIG_AR71XX_DEV_AR913X_WMAC) += dev-ar913x-wmac.o -+obj-$(CONFIG_AR71XX_DEV_DSA) += dev-dsa.o -+obj-$(CONFIG_AR71XX_DEV_GPIO_BUTTONS) += dev-gpio-buttons.o -+obj-$(CONFIG_AR71XX_DEV_LEDS_GPIO) += dev-leds-gpio.o -+obj-$(CONFIG_AR71XX_DEV_M25P80) += dev-m25p80.o -+obj-$(CONFIG_AR71XX_DEV_PB42_PCI) += dev-pb42-pci.o -+obj-$(CONFIG_AR71XX_DEV_PB9X_PCI) += dev-pb9x-pci.o -+obj-$(CONFIG_AR71XX_DEV_USB) += dev-usb.o -+ -+obj-$(CONFIG_AR71XX_NVRAM) += nvram.o -+ -+obj-$(CONFIG_AR71XX_MACH_AP81) += mach-ap81.o -+obj-$(CONFIG_AR71XX_MACH_AP83) += mach-ap83.o -+obj-$(CONFIG_AR71XX_MACH_AW_NR580) += mach-aw-nr580.o -+obj-$(CONFIG_AR71XX_MACH_DIR_600_A1) += mach-dir-600-a1.o -+obj-$(CONFIG_AR71XX_MACH_DIR_615_C1) += mach-dir-615-c1.o -+obj-$(CONFIG_AR71XX_MACH_DIR_825_B1) += mach-dir-825-b1.o -+obj-$(CONFIG_AR71XX_MACH_MZK_W04NU) += mach-mzk-w04nu.o -+obj-$(CONFIG_AR71XX_MACH_MZK_W300NH) += mach-mzk-w300nh.o -+obj-$(CONFIG_AR71XX_MACH_NBG460N) += mach-nbg460n.o -+obj-$(CONFIG_AR71XX_MACH_PB42) += mach-pb42.o -+obj-$(CONFIG_AR71XX_MACH_PB44) += mach-pb44.o -+obj-$(CONFIG_AR71XX_MACH_PB92) += mach-pb92.o -+obj-$(CONFIG_AR71XX_MACH_RB4XX) += mach-rb4xx.o -+obj-$(CONFIG_AR71XX_MACH_RB750) += mach-rb750.o -+obj-$(CONFIG_AR71XX_MACH_TEW_632BRP) += mach-tew-632brp.o -+obj-$(CONFIG_AR71XX_MACH_TL_WR741ND) += mach-tl-wr741nd.o -+obj-$(CONFIG_AR71XX_MACH_TL_WR841N_V1) += mach-tl-wr841n.o -+obj-$(CONFIG_AR71XX_MACH_TL_WR941ND) += mach-tl-wr941nd.o -+obj-$(CONFIG_AR71XX_MACH_TL_WR1043ND) += mach-tl-wr1043nd.o -+obj-$(CONFIG_AR71XX_MACH_UBNT) += mach-ubnt.o -+obj-$(CONFIG_AR71XX_MACH_WNDR3700) += mach-wndr3700.o -+obj-$(CONFIG_AR71XX_MACH_WNR2000) += mach-wnr2000.o -+obj-$(CONFIG_AR71XX_MACH_WP543) += mach-wp543.o -+obj-$(CONFIG_AR71XX_MACH_WRT160NL) += mach-wrt160nl.o -+obj-$(CONFIG_AR71XX_MACH_WRT400N) += mach-wrt400n.o -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/ar71xx.c linux-2.6.37/arch/mips/ar71xx/ar71xx.c ---- linux-2.6.37.orig/arch/mips/ar71xx/ar71xx.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/ar71xx.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,177 @@ -+/* -+ * AR71xx SoC routines -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include -+ -+static DEFINE_MUTEX(ar71xx_flash_mutex); -+ -+void __iomem *ar71xx_ddr_base; -+EXPORT_SYMBOL_GPL(ar71xx_ddr_base); -+ -+void __iomem *ar71xx_pll_base; -+EXPORT_SYMBOL_GPL(ar71xx_pll_base); -+ -+void __iomem *ar71xx_reset_base; -+EXPORT_SYMBOL_GPL(ar71xx_reset_base); -+ -+void __iomem *ar71xx_gpio_base; -+EXPORT_SYMBOL_GPL(ar71xx_gpio_base); -+ -+void __iomem *ar71xx_usb_ctrl_base; -+EXPORT_SYMBOL_GPL(ar71xx_usb_ctrl_base); -+ -+void ar71xx_device_stop(u32 mask) -+{ -+ unsigned long flags; -+ u32 mask_inv; -+ u32 t; -+ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7130: -+ case AR71XX_SOC_AR7141: -+ case AR71XX_SOC_AR7161: -+ local_irq_save(flags); -+ t = ar71xx_reset_rr(AR71XX_RESET_REG_RESET_MODULE); -+ ar71xx_reset_wr(AR71XX_RESET_REG_RESET_MODULE, t | mask); -+ local_irq_restore(flags); -+ break; -+ -+ case AR71XX_SOC_AR7240: -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ mask_inv = mask & RESET_MODULE_USB_OHCI_DLL_7240; -+ local_irq_save(flags); -+ t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE); -+ t |= mask; -+ t &= ~mask_inv; -+ ar71xx_reset_wr(AR724X_RESET_REG_RESET_MODULE, t); -+ local_irq_restore(flags); -+ break; -+ -+ case AR71XX_SOC_AR9130: -+ case AR71XX_SOC_AR9132: -+ local_irq_save(flags); -+ t = ar71xx_reset_rr(AR91XX_RESET_REG_RESET_MODULE); -+ ar71xx_reset_wr(AR91XX_RESET_REG_RESET_MODULE, t | mask); -+ local_irq_restore(flags); -+ break; -+ -+ default: -+ BUG(); -+ } -+} -+EXPORT_SYMBOL_GPL(ar71xx_device_stop); -+ -+void ar71xx_device_start(u32 mask) -+{ -+ unsigned long flags; -+ u32 mask_inv; -+ u32 t; -+ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7130: -+ case AR71XX_SOC_AR7141: -+ case AR71XX_SOC_AR7161: -+ local_irq_save(flags); -+ t = ar71xx_reset_rr(AR71XX_RESET_REG_RESET_MODULE); -+ ar71xx_reset_wr(AR71XX_RESET_REG_RESET_MODULE, t & ~mask); -+ local_irq_restore(flags); -+ break; -+ -+ case AR71XX_SOC_AR7240: -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ mask_inv = mask & RESET_MODULE_USB_OHCI_DLL_7240; -+ local_irq_save(flags); -+ t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE); -+ t &= ~mask; -+ t |= mask_inv; -+ ar71xx_reset_wr(AR724X_RESET_REG_RESET_MODULE, t); -+ local_irq_restore(flags); -+ break; -+ -+ case AR71XX_SOC_AR9130: -+ case AR71XX_SOC_AR9132: -+ local_irq_save(flags); -+ t = ar71xx_reset_rr(AR91XX_RESET_REG_RESET_MODULE); -+ ar71xx_reset_wr(AR91XX_RESET_REG_RESET_MODULE, t & ~mask); -+ local_irq_restore(flags); -+ break; -+ -+ default: -+ BUG(); -+ } -+} -+EXPORT_SYMBOL_GPL(ar71xx_device_start); -+ -+int ar71xx_device_stopped(u32 mask) -+{ -+ unsigned long flags; -+ u32 t; -+ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7130: -+ case AR71XX_SOC_AR7141: -+ case AR71XX_SOC_AR7161: -+ local_irq_save(flags); -+ t = ar71xx_reset_rr(AR71XX_RESET_REG_RESET_MODULE); -+ local_irq_restore(flags); -+ break; -+ -+ case AR71XX_SOC_AR7240: -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ local_irq_save(flags); -+ t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE); -+ local_irq_restore(flags); -+ break; -+ -+ case AR71XX_SOC_AR9130: -+ case AR71XX_SOC_AR9132: -+ local_irq_save(flags); -+ t = ar71xx_reset_rr(AR91XX_RESET_REG_RESET_MODULE); -+ local_irq_restore(flags); -+ break; -+ -+ default: -+ BUG(); -+ } -+ -+ return ((t & mask) == mask); -+} -+EXPORT_SYMBOL_GPL(ar71xx_device_stopped); -+ -+void ar71xx_ddr_flush(u32 reg) -+{ -+ ar71xx_ddr_wr(reg, 1); -+ while ((ar71xx_ddr_rr(reg) & 0x1)); -+ -+ ar71xx_ddr_wr(reg, 1); -+ while ((ar71xx_ddr_rr(reg) & 0x1)); -+} -+EXPORT_SYMBOL_GPL(ar71xx_ddr_flush); -+ -+void ar71xx_flash_acquire(void) -+{ -+ mutex_lock(&ar71xx_flash_mutex); -+} -+EXPORT_SYMBOL_GPL(ar71xx_flash_acquire); -+ -+void ar71xx_flash_release(void) -+{ -+ mutex_unlock(&ar71xx_flash_mutex); -+} -+EXPORT_SYMBOL_GPL(ar71xx_flash_release); -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/dev-ap91-eth.c linux-2.6.37/arch/mips/ar71xx/dev-ap91-eth.c ---- linux-2.6.37.orig/arch/mips/ar71xx/dev-ap91-eth.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/dev-ap91-eth.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,70 @@ -+/* -+ * Atheros AP91 reference board ethernet initialization -+ * -+ * Copyright (C) 2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include "devices.h" -+#include "dev-dsa.h" -+#include "dev-ap91-eth.h" -+ -+static struct dsa_chip_data ap91_dsa_chip = { -+ .port_names[0] = "cpu", -+ .port_names[1] = "lan1", -+ .port_names[2] = "lan2", -+ .port_names[3] = "lan3", -+ .port_names[4] = "lan4", -+}; -+ -+static struct dsa_platform_data ap91_dsa_data = { -+ .nr_chips = 1, -+ .chip = &ap91_dsa_chip, -+}; -+ -+static void ap91_eth_set_port_name(unsigned port, const char *name) -+{ -+ if (port < 1 || port > 5) -+ return; -+ -+ if (name) -+ ap91_dsa_chip.port_names[port] = (char *) name; -+} -+ -+void __init ap91_eth_init(u8 *mac_addr, const char *port_names[]) -+{ -+ if (mac_addr) -+ ar71xx_set_mac_base(mac_addr); -+ -+ if (port_names) { -+ int i; -+ -+ for (i = 0; i < AP91_ETH_NUM_PORT_NAMES; i++) -+ ap91_eth_set_port_name(i + 1, port_names[i]); -+ } -+ -+ /* WAN port */ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ ar71xx_eth0_data.fifo_cfg1 = 0x0fff0000; -+ ar71xx_eth0_data.fifo_cfg2 = 0x00001fff; -+ ar71xx_eth0_data.fifo_cfg3 = 0x008001ff; -+ -+ /* LAN ports */ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.speed = SPEED_1000; -+ ar71xx_eth1_data.duplex = DUPLEX_FULL; -+ ar71xx_eth1_data.fifo_cfg1 = 0x0fff0000; -+ ar71xx_eth1_data.fifo_cfg2 = 0x00001fff; -+ ar71xx_eth1_data.fifo_cfg3 = 0x008001ff; -+ -+ ar71xx_add_device_mdio(0x0); -+ ar71xx_add_device_eth(1); -+ ar71xx_add_device_eth(0); -+ -+ ar71xx_add_device_dsa(1, &ap91_dsa_data); -+} -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/dev-ap91-eth.h linux-2.6.37/arch/mips/ar71xx/dev-ap91-eth.h ---- linux-2.6.37.orig/arch/mips/ar71xx/dev-ap91-eth.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/dev-ap91-eth.h 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,23 @@ -+/* -+ * Atheros AP91 reference board ethernet initialization -+ * -+ * Copyright (C) 2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_DEV_AP91_ETH_H -+#define _AR71XX_DEV_AP91_ETH_H -+ -+#define AP91_ETH_NUM_PORT_NAMES 4 -+ -+#if defined(CONFIG_AR71XX_DEV_AP91_ETH) -+void ap91_eth_init(u8 *mac_addr, const char *port_names[]) __init; -+#else -+static inline void ap91_eth_init(u8 *mac_addr) { } -+#endif -+ -+#endif /* _AR71XX_DEV_AP91_ETH_H */ -+ -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/dev-ap91-pci.c linux-2.6.37/arch/mips/ar71xx/dev-ap91-pci.c ---- linux-2.6.37.orig/arch/mips/ar71xx/dev-ap91-pci.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/dev-ap91-pci.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,114 @@ -+/* -+ * Atheros AP91 reference board PCI initialization -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include "dev-ap91-pci.h" -+ -+static struct ath9k_platform_data ap91_wmac_data; -+static char ap91_wmac_mac[6]; -+static int ap91_pci_fixup_enabled; -+ -+static struct ar71xx_pci_irq ap91_pci_irqs[] __initdata = { -+ { -+ .slot = 0, -+ .pin = 1, -+ .irq = AR71XX_PCI_IRQ_DEV0, -+ } -+}; -+ -+static int ap91_pci_plat_dev_init(struct pci_dev *dev) -+{ -+ switch(PCI_SLOT(dev->devfn)) { -+ case 0: -+ dev->dev.platform_data = &ap91_wmac_data; -+ break; -+ } -+ -+ return 0; -+} -+ -+static void ap91_pci_fixup(struct pci_dev *dev) -+{ -+ void __iomem *mem; -+ u16 *cal_data; -+ u16 cmd; -+ u32 val; -+ -+ if (!ap91_pci_fixup_enabled) -+ return; -+ -+ printk(KERN_INFO "PCI: fixup device %s\n", pci_name(dev)); -+ -+ cal_data = ap91_wmac_data.eeprom_data; -+ if (*cal_data != 0xa55a) { -+ printk(KERN_ERR "PCI: no calibration data found for %s\n", -+ pci_name(dev)); -+ return; -+ } -+ -+ mem = ioremap(AR71XX_PCI_MEM_BASE, 0x10000); -+ if (!mem) { -+ printk(KERN_ERR "PCI: ioremap error for device %s\n", -+ pci_name(dev)); -+ return; -+ } -+ -+ /* Setup the PCI device to allow access to the internal registers */ -+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0xffff); -+ pci_read_config_word(dev, PCI_COMMAND, &cmd); -+ cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; -+ pci_write_config_word(dev, PCI_COMMAND, cmd); -+ -+ /* set pointer to first reg address */ -+ cal_data += 3; -+ while (*cal_data != 0xffff) { -+ u32 reg; -+ reg = *cal_data++; -+ val = *cal_data++; -+ val |= (*cal_data++) << 16; -+ -+ __raw_writel(val, mem + reg); -+ udelay(100); -+ } -+ -+ pci_read_config_dword(dev, PCI_VENDOR_ID, &val); -+ dev->vendor = val & 0xffff; -+ dev->device = (val >> 16) & 0xffff; -+ -+ pci_read_config_dword(dev, PCI_CLASS_REVISION, &val); -+ dev->revision = val & 0xff; -+ dev->class = val >> 8; /* upper 3 bytes */ -+ -+ iounmap(mem); -+} -+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ap91_pci_fixup); -+ -+void __init ap91_pci_init(u8 *cal_data, u8 *mac_addr) -+{ -+ if (cal_data) -+ memcpy(ap91_wmac_data.eeprom_data, cal_data, -+ sizeof(ap91_wmac_data.eeprom_data)); -+ -+ if (mac_addr) { -+ memcpy(ap91_wmac_mac, mac_addr, sizeof(ap91_wmac_mac)); -+ ap91_wmac_data.macaddr = ap91_wmac_mac; -+ } -+ -+ ar71xx_pci_plat_dev_init = ap91_pci_plat_dev_init; -+ ar71xx_pci_init(ARRAY_SIZE(ap91_pci_irqs), ap91_pci_irqs); -+ -+ ap91_pci_fixup_enabled = 1; -+} -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/dev-ap91-pci.h linux-2.6.37/arch/mips/ar71xx/dev-ap91-pci.h ---- linux-2.6.37.orig/arch/mips/ar71xx/dev-ap91-pci.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/dev-ap91-pci.h 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,21 @@ -+/* -+ * Atheros AP91 reference board PCI initialization -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_DEV_AP91_PCI_H -+#define _AR71XX_DEV_AP91_PCI_H -+ -+#if defined(CONFIG_AR71XX_DEV_AP91_PCI) -+void ap91_pci_init(u8 *cal_data, u8 *mac_addr) __init; -+#else -+static inline void ap91_pci_init(u8 *cal_data, u8 *mac_addr) { } -+#endif -+ -+#endif /* _AR71XX_DEV_AP91_PCI_H */ -+ -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/dev-ap94-pci.c linux-2.6.37/arch/mips/ar71xx/dev-ap94-pci.c ---- linux-2.6.37.orig/arch/mips/ar71xx/dev-ap94-pci.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/dev-ap94-pci.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,159 @@ -+/* -+ * Atheros AP94 reference board PCI initialization -+ * -+ * Copyright (C) 2009-2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include "dev-ap94-pci.h" -+ -+static struct ath9k_platform_data ap94_wmac0_data; -+static struct ath9k_platform_data ap94_wmac1_data; -+static char ap94_wmac0_mac[6]; -+static char ap94_wmac1_mac[6]; -+static int ap94_pci_fixup_enabled; -+ -+static struct ar71xx_pci_irq ap94_pci_irqs[] __initdata = { -+ { -+ .slot = 0, -+ .pin = 1, -+ .irq = AR71XX_PCI_IRQ_DEV0, -+ }, { -+ .slot = 1, -+ .pin = 1, -+ .irq = AR71XX_PCI_IRQ_DEV1, -+ } -+}; -+ -+static int ap94_pci_plat_dev_init(struct pci_dev *dev) -+{ -+ switch(PCI_SLOT(dev->devfn)) { -+ case 17: -+ dev->dev.platform_data = &ap94_wmac0_data; -+ break; -+ -+ case 18: -+ dev->dev.platform_data = &ap94_wmac1_data; -+ break; -+ } -+ -+ return 0; -+} -+ -+static void ap94_pci_fixup(struct pci_dev *dev) -+{ -+ void __iomem *mem; -+ u16 *cal_data; -+ u16 cmd; -+ u32 bar0; -+ u32 val; -+ -+ if (!ap94_pci_fixup_enabled) -+ return; -+ -+ switch (PCI_SLOT(dev->devfn)) { -+ case 17: -+ cal_data = ap94_wmac0_data.eeprom_data; -+ break; -+ case 18: -+ cal_data = ap94_wmac1_data.eeprom_data; -+ break; -+ default: -+ return; -+ } -+ -+ if (*cal_data != 0xa55a) { -+ printk(KERN_ERR "PCI: no calibration data found for %s\n", -+ pci_name(dev)); -+ return; -+ } -+ -+ mem = ioremap(AR71XX_PCI_MEM_BASE, 0x10000); -+ if (!mem) { -+ printk(KERN_ERR "PCI: ioremap error for device %s\n", -+ pci_name(dev)); -+ return; -+ } -+ -+ printk(KERN_INFO "PCI: fixup device %s\n", pci_name(dev)); -+ -+ pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0); -+ -+ /* Setup the PCI device to allow access to the internal registers */ -+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, AR71XX_PCI_MEM_BASE); -+ pci_read_config_word(dev, PCI_COMMAND, &cmd); -+ cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; -+ pci_write_config_word(dev, PCI_COMMAND, cmd); -+ -+ /* set pointer to first reg address */ -+ cal_data += 3; -+ while (*cal_data != 0xffff) { -+ u32 reg; -+ reg = *cal_data++; -+ val = *cal_data++; -+ val |= (*cal_data++) << 16; -+ -+ __raw_writel(val, mem + reg); -+ udelay(100); -+ } -+ -+ pci_read_config_dword(dev, PCI_VENDOR_ID, &val); -+ dev->vendor = val & 0xffff; -+ dev->device = (val >> 16) & 0xffff; -+ -+ pci_read_config_dword(dev, PCI_CLASS_REVISION, &val); -+ dev->revision = val & 0xff; -+ dev->class = val >> 8; /* upper 3 bytes */ -+ -+ pci_read_config_word(dev, PCI_COMMAND, &cmd); -+ cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); -+ pci_write_config_word(dev, PCI_COMMAND, cmd); -+ -+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, bar0); -+ -+ iounmap(mem); -+} -+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ap94_pci_fixup); -+ -+void __init ap94_pci_enable_quirk_wndr3700(void) -+{ -+ ap94_wmac0_data.quirk_wndr3700 = 1; -+ ap94_wmac1_data.quirk_wndr3700 = 1; -+} -+ -+void __init ap94_pci_init(u8 *cal_data0, u8 *mac_addr0, -+ u8 *cal_data1, u8 *mac_addr1) -+{ -+ if (cal_data0) -+ memcpy(ap94_wmac0_data.eeprom_data, cal_data0, -+ sizeof(ap94_wmac0_data.eeprom_data)); -+ -+ if (cal_data1) -+ memcpy(ap94_wmac1_data.eeprom_data, cal_data1, -+ sizeof(ap94_wmac1_data.eeprom_data)); -+ -+ if (mac_addr0) { -+ memcpy(ap94_wmac0_mac, mac_addr0, sizeof(ap94_wmac0_mac)); -+ ap94_wmac0_data.macaddr = ap94_wmac0_mac; -+ } -+ -+ if (mac_addr1) { -+ memcpy(ap94_wmac1_mac, mac_addr1, sizeof(ap94_wmac1_mac)); -+ ap94_wmac1_data.macaddr = ap94_wmac1_mac; -+ } -+ -+ ar71xx_pci_plat_dev_init = ap94_pci_plat_dev_init; -+ ar71xx_pci_init(ARRAY_SIZE(ap94_pci_irqs), ap94_pci_irqs); -+ -+ ap94_pci_fixup_enabled = 1; -+} -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/dev-ap94-pci.h linux-2.6.37/arch/mips/ar71xx/dev-ap94-pci.h ---- linux-2.6.37.orig/arch/mips/ar71xx/dev-ap94-pci.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/dev-ap94-pci.h 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,28 @@ -+/* -+ * Atheros AP94 reference board PCI initialization -+ * -+ * Copyright (C) 2009-2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_DEV_AP94_PCI_H -+#define _AR71XX_DEV_AP94_PCI_H -+ -+#if defined(CONFIG_AR71XX_DEV_AP94_PCI) -+void ap94_pci_init(u8 *cal_data0, u8 *mac_addr0, -+ u8 *cal_data1, u8 *mac_addr1) __init; -+ -+void ap94_pci_enable_quirk_wndr3700(void) __init; -+ -+#else -+static inline void ap94_pci_init(u8 *cal_data0, u8 *mac_addr0, -+ u8 *cal_data1, u8 *mac_addr1) {} -+ -+static inline void ap94_pci_enable_quirk_wndr3700(void) {} -+#endif -+ -+#endif /* _AR71XX_DEV_AP94_PCI_H */ -+ -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/dev-ar913x-wmac.c linux-2.6.37/arch/mips/ar71xx/dev-ar913x-wmac.c ---- linux-2.6.37.orig/arch/mips/ar71xx/dev-ar913x-wmac.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/dev-ar913x-wmac.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,68 @@ -+/* -+ * Atheros AR913x SoC built-in WMAC device support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "dev-ar913x-wmac.h" -+ -+static struct ath9k_platform_data ar913x_wmac_data; -+static char ar913x_wmac_mac[6]; -+ -+static struct resource ar913x_wmac_resources[] = { -+ { -+ .start = AR91XX_WMAC_BASE, -+ .end = AR91XX_WMAC_BASE + AR91XX_WMAC_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+ }, { -+ .start = AR71XX_CPU_IRQ_IP2, -+ .end = AR71XX_CPU_IRQ_IP2, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct platform_device ar913x_wmac_device = { -+ .name = "ath9k", -+ .id = -1, -+ .resource = ar913x_wmac_resources, -+ .num_resources = ARRAY_SIZE(ar913x_wmac_resources), -+ .dev = { -+ .platform_data = &ar913x_wmac_data, -+ }, -+}; -+ -+void __init ar913x_add_device_wmac(u8 *cal_data, u8 *mac_addr) -+{ -+ if (cal_data) -+ memcpy(ar913x_wmac_data.eeprom_data, cal_data, -+ sizeof(ar913x_wmac_data.eeprom_data)); -+ -+ if (mac_addr) { -+ memcpy(ar913x_wmac_mac, mac_addr, sizeof(ar913x_wmac_mac)); -+ ar913x_wmac_data.macaddr = ar913x_wmac_mac; -+ } -+ -+ ar71xx_device_stop(RESET_MODULE_AMBA2WMAC); -+ mdelay(10); -+ -+ ar71xx_device_start(RESET_MODULE_AMBA2WMAC); -+ mdelay(10); -+ -+ platform_device_register(&ar913x_wmac_device); -+} -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/dev-ar913x-wmac.h linux-2.6.37/arch/mips/ar71xx/dev-ar913x-wmac.h ---- linux-2.6.37.orig/arch/mips/ar71xx/dev-ar913x-wmac.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/dev-ar913x-wmac.h 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,19 @@ -+/* -+ * Atheros AR913x SoC built-in WMAC device support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_DEV_AR913X_WMAC_H -+#define _AR71XX_DEV_AR913X_WMAC_H -+ -+void ar913x_add_device_wmac(u8 *cal_data, u8 *mac_addr) __init; -+ -+#endif /* _AR71XX_DEV_AR913X_WMAC_H */ -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/dev-dsa.c linux-2.6.37/arch/mips/ar71xx/dev-dsa.c ---- linux-2.6.37.orig/arch/mips/ar71xx/dev-dsa.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/dev-dsa.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,50 @@ -+/* -+ * Atheros AR71xx DSA switch device support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "devices.h" -+#include "dev-dsa.h" -+ -+static struct platform_device ar71xx_dsa_switch_device = { -+ .name = "dsa", -+ .id = 0, -+}; -+ -+void __init ar71xx_add_device_dsa(unsigned int id, -+ struct dsa_platform_data *d) -+{ -+ int i; -+ -+ switch (id) { -+ case 0: -+ d->netdev = &ar71xx_eth0_device.dev; -+ break; -+ case 1: -+ d->netdev = &ar71xx_eth1_device.dev; -+ break; -+ default: -+ printk(KERN_ERR -+ "ar71xx: invalid ethernet id %d for DSA switch\n", -+ id); -+ return; -+ } -+ -+ for (i = 0; i < d->nr_chips; i++) -+ d->chip[i].mii_bus = &ar71xx_mdio_device.dev; -+ -+ ar71xx_dsa_switch_device.dev.platform_data = d; -+ -+ platform_device_register(&ar71xx_dsa_switch_device); -+} -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/dev-dsa.h linux-2.6.37/arch/mips/ar71xx/dev-dsa.h ---- linux-2.6.37.orig/arch/mips/ar71xx/dev-dsa.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/dev-dsa.h 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,20 @@ -+/* -+ * Atheros AR71xx DSA switch device support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_DEV_DSA_H -+#define _AR71XX_DEV_DSA_H -+ -+#include -+ -+void ar71xx_add_device_dsa(unsigned int id, -+ struct dsa_platform_data *d) __init; -+ -+#endif /* _AR71XX_DEV_DSA_H */ -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/dev-gpio-buttons.c linux-2.6.37/arch/mips/ar71xx/dev-gpio-buttons.c ---- linux-2.6.37.orig/arch/mips/ar71xx/dev-gpio-buttons.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/dev-gpio-buttons.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,58 @@ -+/* -+ * Atheros AR71xx GPIO button support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include "linux/init.h" -+#include -+ -+#include "dev-gpio-buttons.h" -+ -+void __init ar71xx_add_device_gpio_buttons(int id, -+ unsigned poll_interval, -+ unsigned nbuttons, -+ struct gpio_button *buttons) -+{ -+ struct platform_device *pdev; -+ struct gpio_buttons_platform_data pdata; -+ struct gpio_button *p; -+ int err; -+ -+ p = kmalloc(nbuttons * sizeof(*p), GFP_KERNEL); -+ if (!p) -+ return; -+ -+ memcpy(p, buttons, nbuttons * sizeof(*p)); -+ -+ pdev = platform_device_alloc("gpio-buttons", id); -+ if (!pdev) -+ goto err_free_buttons; -+ -+ memset(&pdata, 0, sizeof(pdata)); -+ pdata.poll_interval = poll_interval; -+ pdata.nbuttons = nbuttons; -+ pdata.buttons = p; -+ -+ err = platform_device_add_data(pdev, &pdata, sizeof(pdata)); -+ if (err) -+ goto err_put_pdev; -+ -+ -+ err = platform_device_add(pdev); -+ if (err) -+ goto err_put_pdev; -+ -+ return; -+ -+err_put_pdev: -+ platform_device_put(pdev); -+ -+err_free_buttons: -+ kfree(p); -+} -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/dev-gpio-buttons.h linux-2.6.37/arch/mips/ar71xx/dev-gpio-buttons.h ---- linux-2.6.37.orig/arch/mips/ar71xx/dev-gpio-buttons.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/dev-gpio-buttons.h 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,25 @@ -+/* -+ * Atheros AR71xx GPIO button support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_DEV_GPIO_BUTTONS_H -+#define _AR71XX_DEV_GPIO_BUTTONS_H -+ -+#include -+#include -+ -+#include -+ -+void ar71xx_add_device_gpio_buttons(int id, -+ unsigned poll_interval, -+ unsigned nbuttons, -+ struct gpio_button *buttons) __init; -+ -+#endif /* _AR71XX_DEV_GPIO_BUTTONS_H */ -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/dev-leds-gpio.c linux-2.6.37/arch/mips/ar71xx/dev-leds-gpio.c ---- linux-2.6.37.orig/arch/mips/ar71xx/dev-leds-gpio.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/dev-leds-gpio.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,57 @@ -+/* -+ * Atheros AR71xx GPIO LED device support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+ -+#include "dev-leds-gpio.h" -+ -+void __init ar71xx_add_device_leds_gpio(int id, unsigned num_leds, -+ struct gpio_led *leds) -+{ -+ struct platform_device *pdev; -+ struct gpio_led_platform_data pdata; -+ struct gpio_led *p; -+ int err; -+ -+ p = kmalloc(num_leds * sizeof(*p), GFP_KERNEL); -+ if (!p) -+ return; -+ -+ memcpy(p, leds, num_leds * sizeof(*p)); -+ -+ pdev = platform_device_alloc("leds-gpio", id); -+ if (!pdev) -+ goto err_free_leds; -+ -+ memset(&pdata, 0, sizeof(pdata)); -+ pdata.num_leds = num_leds; -+ pdata.leds = p; -+ -+ err = platform_device_add_data(pdev, &pdata, sizeof(pdata)); -+ if (err) -+ goto err_put_pdev; -+ -+ err = platform_device_add(pdev); -+ if (err) -+ goto err_put_pdev; -+ -+ return; -+ -+err_put_pdev: -+ platform_device_put(pdev); -+ -+err_free_leds: -+ kfree(p); -+} -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/dev-leds-gpio.h linux-2.6.37/arch/mips/ar71xx/dev-leds-gpio.h ---- linux-2.6.37.orig/arch/mips/ar71xx/dev-leds-gpio.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/dev-leds-gpio.h 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,21 @@ -+/* -+ * Atheros AR71xx GPIO LED device support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_DEV_LEDS_GPIO_H -+#define _AR71XX_DEV_LEDS_GPIO_H -+ -+#include -+ -+void ar71xx_add_device_leds_gpio(int id, -+ unsigned num_leds, -+ struct gpio_led *leds) __init; -+ -+#endif /* _AR71XX_DEV_LEDS_GPIO_H */ -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/dev-m25p80.c linux-2.6.37/arch/mips/ar71xx/dev-m25p80.c ---- linux-2.6.37.orig/arch/mips/ar71xx/dev-m25p80.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/dev-m25p80.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,30 @@ -+/* -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+ -+#include "devices.h" -+#include "dev-m25p80.h" -+ -+static struct spi_board_info ar71xx_spi_info[] = { -+ { -+ .bus_num = 0, -+ .chip_select = 0, -+ .max_speed_hz = 25000000, -+ .modalias = "m25p80", -+ } -+}; -+ -+void __init ar71xx_add_device_m25p80(struct flash_platform_data *pdata) -+{ -+ ar71xx_spi_info[0].platform_data = pdata; -+ ar71xx_add_device_spi(NULL, ar71xx_spi_info, -+ ARRAY_SIZE(ar71xx_spi_info)); -+} -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/dev-m25p80.h linux-2.6.37/arch/mips/ar71xx/dev-m25p80.h ---- linux-2.6.37.orig/arch/mips/ar71xx/dev-m25p80.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/dev-m25p80.h 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,16 @@ -+/* -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_DEV_M25P80_H -+#define _AR71XX_DEV_M25P80_H -+ -+#include -+ -+void ar71xx_add_device_m25p80(struct flash_platform_data *pdata) __init; -+ -+#endif /* _AR71XX_DEV_M25P80_H */ -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/dev-pb42-pci.c linux-2.6.37/arch/mips/ar71xx/dev-pb42-pci.c ---- linux-2.6.37.orig/arch/mips/ar71xx/dev-pb42-pci.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/dev-pb42-pci.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,40 @@ -+/* -+ * Atheros PB42 reference board PCI initialization -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+ -+#include -+#include -+ -+#include "dev-pb42-pci.h" -+ -+static struct ar71xx_pci_irq pb42_pci_irqs[] __initdata = { -+ { -+ .slot = 0, -+ .pin = 1, -+ .irq = AR71XX_PCI_IRQ_DEV0, -+ }, { -+ .slot = 1, -+ .pin = 1, -+ .irq = AR71XX_PCI_IRQ_DEV1, -+ }, { -+ .slot = 2, -+ .pin = 1, -+ .irq = AR71XX_PCI_IRQ_DEV2, -+ } -+}; -+ -+void __init pb42_pci_init(void) -+{ -+ ar71xx_pci_init(ARRAY_SIZE(pb42_pci_irqs), pb42_pci_irqs); -+} -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/dev-pb42-pci.h linux-2.6.37/arch/mips/ar71xx/dev-pb42-pci.h ---- linux-2.6.37.orig/arch/mips/ar71xx/dev-pb42-pci.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/dev-pb42-pci.h 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,21 @@ -+/* -+ * Atheros PB42 reference board PCI initialization -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_DEV_PB42_PCI_H -+#define _AR71XX_DEV_PB42_PCI_H -+ -+#if defined(CONFIG_AR71XX_DEV_PB42_PCI) -+void pb42_pci_init(void) __init; -+#else -+static inline void pb42_pci_init(void) { } -+#endif -+ -+#endif /* _AR71XX_DEV_PB42_PCI_H */ -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/dev-pb9x-pci.c linux-2.6.37/arch/mips/ar71xx/dev-pb9x-pci.c ---- linux-2.6.37.orig/arch/mips/ar71xx/dev-pb9x-pci.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/dev-pb9x-pci.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,33 @@ -+/* -+ * Atheros PB9x reference board PCI initialization -+ * -+ * Copyright (C) 2010 Felix Fietkau -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+ -+#include -+#include -+ -+#include "dev-pb9x-pci.h" -+ -+static struct ar71xx_pci_irq pb9x_pci_irqs[] __initdata = { -+ { -+ .slot = 0, -+ .pin = 1, -+ .irq = AR71XX_PCI_IRQ_DEV0, -+ } -+}; -+ -+void __init pb9x_pci_init(void) -+{ -+ ar71xx_pci_init(ARRAY_SIZE(pb9x_pci_irqs), pb9x_pci_irqs); -+} -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/dev-pb9x-pci.h linux-2.6.37/arch/mips/ar71xx/dev-pb9x-pci.h ---- linux-2.6.37.orig/arch/mips/ar71xx/dev-pb9x-pci.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/dev-pb9x-pci.h 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,22 @@ -+/* -+ * Atheros PB9x reference board PCI initialization -+ * -+ * Copyright (C) 2010 Felix Fietkau -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_DEV_PB9X_PCI_H -+#define _AR71XX_DEV_PB9X_PCI_H -+ -+#if defined(CONFIG_AR71XX_DEV_PB9X_PCI) -+void pb9x_pci_init(void) __init; -+#else -+static inline void pb9x_pci_init(void) { } -+#endif -+ -+#endif /* _AR71XX_DEV_PB9X_PCI_H */ -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/dev-usb.c linux-2.6.37/arch/mips/ar71xx/dev-usb.c ---- linux-2.6.37.orig/arch/mips/ar71xx/dev-usb.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/dev-usb.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,181 @@ -+/* -+ * Atheros AR71xx USB host device support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include "dev-usb.h" -+ -+/* -+ * OHCI (USB full speed host controller) -+ */ -+static struct resource ar71xx_ohci_resources[] = { -+ [0] = { -+ .start = AR71XX_OHCI_BASE, -+ .end = AR71XX_OHCI_BASE + AR71XX_OHCI_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+ [1] = { -+ .start = AR71XX_MISC_IRQ_OHCI, -+ .end = AR71XX_MISC_IRQ_OHCI, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct resource ar7240_ohci_resources[] = { -+ [0] = { -+ .start = AR7240_OHCI_BASE, -+ .end = AR7240_OHCI_BASE + AR7240_OHCI_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+ [1] = { -+ .start = AR71XX_CPU_IRQ_USB, -+ .end = AR71XX_CPU_IRQ_USB, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static u64 ar71xx_ohci_dmamask = DMA_BIT_MASK(32); -+static struct platform_device ar71xx_ohci_device = { -+ .name = "ar71xx-ohci", -+ .id = -1, -+ .resource = ar71xx_ohci_resources, -+ .num_resources = ARRAY_SIZE(ar71xx_ohci_resources), -+ .dev = { -+ .dma_mask = &ar71xx_ohci_dmamask, -+ .coherent_dma_mask = DMA_BIT_MASK(32), -+ }, -+}; -+ -+/* -+ * EHCI (USB full speed host controller) -+ */ -+static struct resource ar71xx_ehci_resources[] = { -+ [0] = { -+ .start = AR71XX_EHCI_BASE, -+ .end = AR71XX_EHCI_BASE + AR71XX_EHCI_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+ [1] = { -+ .start = AR71XX_CPU_IRQ_USB, -+ .end = AR71XX_CPU_IRQ_USB, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static u64 ar71xx_ehci_dmamask = DMA_BIT_MASK(32); -+static struct ar71xx_ehci_platform_data ar71xx_ehci_data; -+ -+static struct platform_device ar71xx_ehci_device = { -+ .name = "ar71xx-ehci", -+ .id = -1, -+ .resource = ar71xx_ehci_resources, -+ .num_resources = ARRAY_SIZE(ar71xx_ehci_resources), -+ .dev = { -+ .dma_mask = &ar71xx_ehci_dmamask, -+ .coherent_dma_mask = DMA_BIT_MASK(32), -+ .platform_data = &ar71xx_ehci_data, -+ }, -+}; -+ -+#define AR71XX_USB_RESET_MASK \ -+ (RESET_MODULE_USB_HOST | RESET_MODULE_USB_PHY \ -+ | RESET_MODULE_USB_OHCI_DLL) -+ -+#define AR7240_USB_RESET_MASK \ -+ (RESET_MODULE_USB_HOST | RESET_MODULE_USB_OHCI_DLL_7240) -+ -+static void __init ar71xx_usb_setup(void) -+{ -+ ar71xx_device_stop(AR71XX_USB_RESET_MASK); -+ mdelay(1000); -+ ar71xx_device_start(AR71XX_USB_RESET_MASK); -+ -+ /* Turning on the Buff and Desc swap bits */ -+ ar71xx_usb_ctrl_wr(USB_CTRL_REG_CONFIG, 0xf0000); -+ -+ /* WAR for HW bug. Here it adjusts the duration between two SOFS */ -+ ar71xx_usb_ctrl_wr(USB_CTRL_REG_FLADJ, 0x20c00); -+ -+ mdelay(900); -+ -+ platform_device_register(&ar71xx_ohci_device); -+ platform_device_register(&ar71xx_ehci_device); -+} -+ -+static void __init ar7240_usb_setup(void) -+{ -+ ar71xx_device_stop(AR7240_USB_RESET_MASK); -+ mdelay(1000); -+ ar71xx_device_start(AR7240_USB_RESET_MASK); -+ -+ /* WAR for HW bug. Here it adjusts the duration between two SOFS */ -+ ar71xx_usb_ctrl_wr(USB_CTRL_REG_FLADJ, 0x3); -+ -+ if (ar71xx_soc == AR71XX_SOC_AR7241 || ar71xx_soc == AR71XX_SOC_AR7242) { -+ ar71xx_ehci_data.is_ar91xx = 1; -+ ar71xx_ehci_device.resource = ar7240_ohci_resources; -+ ar71xx_ehci_device.num_resources = ARRAY_SIZE(ar7240_ohci_resources); -+ platform_device_register(&ar71xx_ehci_device); -+ } else { -+ ar71xx_ohci_device.resource = ar7240_ohci_resources; -+ ar71xx_ohci_device.num_resources = ARRAY_SIZE(ar7240_ohci_resources); -+ platform_device_register(&ar71xx_ohci_device); -+ } -+} -+ -+static void __init ar91xx_usb_setup(void) -+{ -+ ar71xx_device_stop(RESET_MODULE_USBSUS_OVERRIDE); -+ mdelay(10); -+ -+ ar71xx_device_start(RESET_MODULE_USB_HOST); -+ mdelay(10); -+ -+ ar71xx_device_start(RESET_MODULE_USB_PHY); -+ mdelay(10); -+ -+ ar71xx_ehci_data.is_ar91xx = 1; -+ platform_device_register(&ar71xx_ehci_device); -+} -+ -+void __init ar71xx_add_device_usb(void) -+{ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7240: -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ ar7240_usb_setup(); -+ break; -+ -+ case AR71XX_SOC_AR7130: -+ case AR71XX_SOC_AR7141: -+ case AR71XX_SOC_AR7161: -+ ar71xx_usb_setup(); -+ break; -+ -+ case AR71XX_SOC_AR9130: -+ case AR71XX_SOC_AR9132: -+ ar91xx_usb_setup(); -+ break; -+ -+ default: -+ BUG(); -+ } -+} -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/dev-usb.h linux-2.6.37/arch/mips/ar71xx/dev-usb.h ---- linux-2.6.37.orig/arch/mips/ar71xx/dev-usb.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/dev-usb.h 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,17 @@ -+/* -+ * Atheros AR71xx USB host device support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_DEV_USB_H -+#define _AR71XX_DEV_USB_H -+ -+void ar71xx_add_device_usb(void) __init; -+ -+#endif /* _AR71XX_DEV_USB_H */ -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/devices.c linux-2.6.37/arch/mips/ar71xx/devices.c ---- linux-2.6.37.orig/arch/mips/ar71xx/devices.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/devices.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,575 @@ -+/* -+ * Atheros AR71xx SoC platform devices -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "devices.h" -+ -+static u8 ar71xx_mac_base[ETH_ALEN] __initdata; -+ -+static struct resource ar71xx_uart_resources[] = { -+ { -+ .start = AR71XX_UART_BASE, -+ .end = AR71XX_UART_BASE + AR71XX_UART_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+}; -+ -+#define AR71XX_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP) -+static struct plat_serial8250_port ar71xx_uart_data[] = { -+ { -+ .mapbase = AR71XX_UART_BASE, -+ .irq = AR71XX_MISC_IRQ_UART, -+ .flags = AR71XX_UART_FLAGS, -+ .iotype = UPIO_MEM32, -+ .regshift = 2, -+ }, { -+ /* terminating entry */ -+ } -+}; -+ -+static struct platform_device ar71xx_uart_device = { -+ .name = "serial8250", -+ .id = PLAT8250_DEV_PLATFORM, -+ .resource = ar71xx_uart_resources, -+ .num_resources = ARRAY_SIZE(ar71xx_uart_resources), -+ .dev = { -+ .platform_data = ar71xx_uart_data -+ }, -+}; -+ -+void __init ar71xx_add_device_uart(void) -+{ -+ ar71xx_uart_data[0].uartclk = ar71xx_ahb_freq; -+ platform_device_register(&ar71xx_uart_device); -+} -+ -+static struct resource ar71xx_mdio_resources[] = { -+ { -+ .name = "mdio_base", -+ .flags = IORESOURCE_MEM, -+ .start = AR71XX_GE0_BASE, -+ .end = AR71XX_GE0_BASE + 0x200 - 1, -+ } -+}; -+ -+static struct ag71xx_mdio_platform_data ar71xx_mdio_data; -+ -+struct platform_device ar71xx_mdio_device = { -+ .name = "ag71xx-mdio", -+ .id = -1, -+ .resource = ar71xx_mdio_resources, -+ .num_resources = ARRAY_SIZE(ar71xx_mdio_resources), -+ .dev = { -+ .platform_data = &ar71xx_mdio_data, -+ }, -+}; -+ -+void __init ar71xx_add_device_mdio(u32 phy_mask) -+{ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7240: -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ ar71xx_mdio_data.is_ar7240 = 1; -+ break; -+ default: -+ break; -+ } -+ -+ ar71xx_mdio_data.phy_mask = phy_mask; -+ -+ platform_device_register(&ar71xx_mdio_device); -+} -+ -+static void ar71xx_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift) -+{ -+ void __iomem *base; -+ u32 t; -+ -+ base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE); -+ -+ t = __raw_readl(base + cfg_reg); -+ t &= ~(3 << shift); -+ t |= (2 << shift); -+ __raw_writel(t, base + cfg_reg); -+ udelay(100); -+ -+ __raw_writel(pll_val, base + pll_reg); -+ -+ t |= (3 << shift); -+ __raw_writel(t, base + cfg_reg); -+ udelay(100); -+ -+ t &= ~(3 << shift); -+ __raw_writel(t, base + cfg_reg); -+ udelay(100); -+ -+ printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n", -+ (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg)); -+ -+ iounmap(base); -+} -+ -+struct ar71xx_eth_pll_data ar71xx_eth0_pll_data; -+struct ar71xx_eth_pll_data ar71xx_eth1_pll_data; -+ -+static u32 ar71xx_get_eth_pll(unsigned int mac, int speed) -+{ -+ struct ar71xx_eth_pll_data *pll_data; -+ u32 pll_val; -+ -+ switch (mac) { -+ case 0: -+ pll_data = &ar71xx_eth0_pll_data; -+ break; -+ case 1: -+ pll_data = &ar71xx_eth1_pll_data; -+ break; -+ default: -+ BUG(); -+ } -+ -+ switch (speed) { -+ case SPEED_10: -+ pll_val = pll_data->pll_10; -+ break; -+ case SPEED_100: -+ pll_val = pll_data->pll_100; -+ break; -+ case SPEED_1000: -+ pll_val = pll_data->pll_1000; -+ break; -+ default: -+ BUG(); -+ } -+ -+ return pll_val; -+} -+ -+static void ar71xx_set_pll_ge0(int speed) -+{ -+ u32 val = ar71xx_get_eth_pll(0, speed); -+ -+ ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK, -+ val, AR71XX_ETH0_PLL_SHIFT); -+} -+ -+static void ar71xx_set_pll_ge1(int speed) -+{ -+ u32 val = ar71xx_get_eth_pll(1, speed); -+ -+ ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK, -+ val, AR71XX_ETH1_PLL_SHIFT); -+} -+ -+static void ar724x_set_pll_ge0(int speed) -+{ -+ /* TODO */ -+} -+ -+static void ar724x_set_pll_ge1(int speed) -+{ -+ /* TODO */ -+} -+ -+static void ar91xx_set_pll_ge0(int speed) -+{ -+ u32 val = ar71xx_get_eth_pll(0, speed); -+ -+ ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH0_INT_CLOCK, -+ val, AR91XX_ETH0_PLL_SHIFT); -+} -+ -+static void ar91xx_set_pll_ge1(int speed) -+{ -+ u32 val = ar71xx_get_eth_pll(1, speed); -+ -+ ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH1_INT_CLOCK, -+ val, AR91XX_ETH1_PLL_SHIFT); -+} -+ -+static void ar71xx_ddr_flush_ge0(void) -+{ -+ ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE0); -+} -+ -+static void ar71xx_ddr_flush_ge1(void) -+{ -+ ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE1); -+} -+ -+static void ar724x_ddr_flush_ge0(void) -+{ -+ ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE0); -+} -+ -+static void ar724x_ddr_flush_ge1(void) -+{ -+ ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE1); -+} -+ -+static void ar91xx_ddr_flush_ge0(void) -+{ -+ ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0); -+} -+ -+static void ar91xx_ddr_flush_ge1(void) -+{ -+ ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE1); -+} -+ -+static struct resource ar71xx_eth0_resources[] = { -+ { -+ .name = "mac_base", -+ .flags = IORESOURCE_MEM, -+ .start = AR71XX_GE0_BASE, -+ .end = AR71XX_GE0_BASE + 0x200 - 1, -+ }, { -+ .name = "mii_ctrl", -+ .flags = IORESOURCE_MEM, -+ .start = AR71XX_MII_BASE + MII_REG_MII0_CTRL, -+ .end = AR71XX_MII_BASE + MII_REG_MII0_CTRL + 3, -+ }, { -+ .name = "mac_irq", -+ .flags = IORESOURCE_IRQ, -+ .start = AR71XX_CPU_IRQ_GE0, -+ .end = AR71XX_CPU_IRQ_GE0, -+ }, -+}; -+ -+struct ag71xx_platform_data ar71xx_eth0_data = { -+ .reset_bit = RESET_MODULE_GE0_MAC, -+}; -+ -+struct platform_device ar71xx_eth0_device = { -+ .name = "ag71xx", -+ .id = 0, -+ .resource = ar71xx_eth0_resources, -+ .num_resources = ARRAY_SIZE(ar71xx_eth0_resources), -+ .dev = { -+ .platform_data = &ar71xx_eth0_data, -+ }, -+}; -+ -+static struct resource ar71xx_eth1_resources[] = { -+ { -+ .name = "mac_base", -+ .flags = IORESOURCE_MEM, -+ .start = AR71XX_GE1_BASE, -+ .end = AR71XX_GE1_BASE + 0x200 - 1, -+ }, { -+ .name = "mii_ctrl", -+ .flags = IORESOURCE_MEM, -+ .start = AR71XX_MII_BASE + MII_REG_MII1_CTRL, -+ .end = AR71XX_MII_BASE + MII_REG_MII1_CTRL + 3, -+ }, { -+ .name = "mac_irq", -+ .flags = IORESOURCE_IRQ, -+ .start = AR71XX_CPU_IRQ_GE1, -+ .end = AR71XX_CPU_IRQ_GE1, -+ }, -+}; -+ -+struct ag71xx_platform_data ar71xx_eth1_data = { -+ .reset_bit = RESET_MODULE_GE1_MAC, -+}; -+ -+struct platform_device ar71xx_eth1_device = { -+ .name = "ag71xx", -+ .id = 1, -+ .resource = ar71xx_eth1_resources, -+ .num_resources = ARRAY_SIZE(ar71xx_eth1_resources), -+ .dev = { -+ .platform_data = &ar71xx_eth1_data, -+ }, -+}; -+ -+#define AR71XX_PLL_VAL_1000 0x00110000 -+#define AR71XX_PLL_VAL_100 0x00001099 -+#define AR71XX_PLL_VAL_10 0x00991099 -+ -+#define AR724X_PLL_VAL_1000 0x00110000 -+#define AR724X_PLL_VAL_100 0x00001099 -+#define AR724X_PLL_VAL_10 0x00991099 -+ -+#define AR91XX_PLL_VAL_1000 0x1a000000 -+#define AR91XX_PLL_VAL_100 0x13000a44 -+#define AR91XX_PLL_VAL_10 0x00441099 -+ -+static void __init ar71xx_init_eth_pll_data(unsigned int id) -+{ -+ struct ar71xx_eth_pll_data *pll_data; -+ u32 pll_10, pll_100, pll_1000; -+ -+ switch (id) { -+ case 0: -+ pll_data = &ar71xx_eth0_pll_data; -+ break; -+ case 1: -+ pll_data = &ar71xx_eth1_pll_data; -+ break; -+ default: -+ BUG(); -+ } -+ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7130: -+ case AR71XX_SOC_AR7141: -+ case AR71XX_SOC_AR7161: -+ pll_10 = AR71XX_PLL_VAL_10; -+ pll_100 = AR71XX_PLL_VAL_100; -+ pll_1000 = AR71XX_PLL_VAL_1000; -+ break; -+ -+ case AR71XX_SOC_AR7240: -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ pll_10 = AR724X_PLL_VAL_10; -+ pll_100 = AR724X_PLL_VAL_100; -+ pll_1000 = AR724X_PLL_VAL_1000; -+ break; -+ -+ case AR71XX_SOC_AR9130: -+ case AR71XX_SOC_AR9132: -+ pll_10 = AR91XX_PLL_VAL_10; -+ pll_100 = AR91XX_PLL_VAL_100; -+ pll_1000 = AR91XX_PLL_VAL_1000; -+ break; -+ default: -+ BUG(); -+ } -+ -+ if (!pll_data->pll_10) -+ pll_data->pll_10 = pll_10; -+ -+ if (!pll_data->pll_100) -+ pll_data->pll_100 = pll_100; -+ -+ if (!pll_data->pll_1000) -+ pll_data->pll_1000 = pll_1000; -+} -+ -+static int ar71xx_eth_instance __initdata; -+void __init ar71xx_add_device_eth(unsigned int id) -+{ -+ struct platform_device *pdev; -+ struct ag71xx_platform_data *pdata; -+ -+ ar71xx_init_eth_pll_data(id); -+ -+ switch (id) { -+ case 0: -+ switch (ar71xx_eth0_data.phy_if_mode) { -+ case PHY_INTERFACE_MODE_MII: -+ ar71xx_eth0_data.mii_if = MII0_CTRL_IF_MII; -+ break; -+ case PHY_INTERFACE_MODE_GMII: -+ ar71xx_eth0_data.mii_if = MII0_CTRL_IF_GMII; -+ break; -+ case PHY_INTERFACE_MODE_RGMII: -+ ar71xx_eth0_data.mii_if = MII0_CTRL_IF_RGMII; -+ break; -+ case PHY_INTERFACE_MODE_RMII: -+ ar71xx_eth0_data.mii_if = MII0_CTRL_IF_RMII; -+ break; -+ default: -+ printk(KERN_ERR "ar71xx: invalid PHY interface mode " -+ "for eth0\n"); -+ return; -+ } -+ pdev = &ar71xx_eth0_device; -+ break; -+ case 1: -+ switch (ar71xx_eth1_data.phy_if_mode) { -+ case PHY_INTERFACE_MODE_RMII: -+ ar71xx_eth1_data.mii_if = MII1_CTRL_IF_RMII; -+ break; -+ case PHY_INTERFACE_MODE_RGMII: -+ ar71xx_eth1_data.mii_if = MII1_CTRL_IF_RGMII; -+ break; -+ default: -+ printk(KERN_ERR "ar71xx: invalid PHY interface mode " -+ "for eth1\n"); -+ return; -+ } -+ pdev = &ar71xx_eth1_device; -+ break; -+ default: -+ printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id); -+ return; -+ } -+ -+ pdata = pdev->dev.platform_data; -+ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7130: -+ pdata->ddr_flush = id ? ar71xx_ddr_flush_ge1 -+ : ar71xx_ddr_flush_ge0; -+ pdata->set_pll = id ? ar71xx_set_pll_ge1 -+ : ar71xx_set_pll_ge0; -+ break; -+ -+ case AR71XX_SOC_AR7141: -+ case AR71XX_SOC_AR7161: -+ pdata->ddr_flush = id ? ar71xx_ddr_flush_ge1 -+ : ar71xx_ddr_flush_ge0; -+ pdata->set_pll = id ? ar71xx_set_pll_ge1 -+ : ar71xx_set_pll_ge0; -+ pdata->has_gbit = 1; -+ break; -+ -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ ar71xx_eth0_data.reset_bit |= AR724X_RESET_GE0_MDIO; -+ ar71xx_eth1_data.reset_bit |= AR724X_RESET_GE1_MDIO; -+ /* fall through */ -+ case AR71XX_SOC_AR7240: -+ pdata->ddr_flush = id ? ar724x_ddr_flush_ge1 -+ : ar724x_ddr_flush_ge0; -+ pdata->set_pll = id ? ar724x_set_pll_ge1 -+ : ar724x_set_pll_ge0; -+ pdata->is_ar724x = 1; -+ break; -+ -+ case AR71XX_SOC_AR9130: -+ pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1 -+ : ar91xx_ddr_flush_ge0; -+ pdata->set_pll = id ? ar91xx_set_pll_ge1 -+ : ar91xx_set_pll_ge0; -+ pdata->is_ar91xx = 1; -+ break; -+ -+ case AR71XX_SOC_AR9132: -+ pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1 -+ : ar91xx_ddr_flush_ge0; -+ pdata->set_pll = id ? ar91xx_set_pll_ge1 -+ : ar91xx_set_pll_ge0; -+ pdata->is_ar91xx = 1; -+ pdata->has_gbit = 1; -+ break; -+ -+ default: -+ BUG(); -+ } -+ -+ switch (pdata->phy_if_mode) { -+ case PHY_INTERFACE_MODE_GMII: -+ case PHY_INTERFACE_MODE_RGMII: -+ if (!pdata->has_gbit) { -+ printk(KERN_ERR "ar71xx: no gbit available on eth%d\n", -+ id); -+ return; -+ } -+ /* fallthrough */ -+ default: -+ break; -+ } -+ -+ if (is_valid_ether_addr(ar71xx_mac_base)) { -+ memcpy(pdata->mac_addr, ar71xx_mac_base, ETH_ALEN); -+ pdata->mac_addr[5] += ar71xx_eth_instance; -+ } else { -+ random_ether_addr(pdata->mac_addr); -+ printk(KERN_DEBUG -+ "ar71xx: using random MAC address for eth%d\n", -+ ar71xx_eth_instance); -+ } -+ -+ if (pdata->mii_bus_dev == NULL) -+ pdata->mii_bus_dev = &ar71xx_mdio_device.dev; -+ -+ /* Reset the device */ -+ ar71xx_device_stop(pdata->reset_bit); -+ mdelay(100); -+ -+ ar71xx_device_start(pdata->reset_bit); -+ mdelay(100); -+ -+ platform_device_register(pdev); -+ ar71xx_eth_instance++; -+} -+ -+static struct resource ar71xx_spi_resources[] = { -+ [0] = { -+ .start = AR71XX_SPI_BASE, -+ .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+}; -+ -+static struct platform_device ar71xx_spi_device = { -+ .name = "ar71xx-spi", -+ .id = -1, -+ .resource = ar71xx_spi_resources, -+ .num_resources = ARRAY_SIZE(ar71xx_spi_resources), -+}; -+ -+void __init ar71xx_add_device_spi(struct ar71xx_spi_platform_data *pdata, -+ struct spi_board_info const *info, -+ unsigned n) -+{ -+ spi_register_board_info(info, n); -+ ar71xx_spi_device.dev.platform_data = pdata; -+ platform_device_register(&ar71xx_spi_device); -+} -+ -+void __init ar71xx_add_device_wdt(void) -+{ -+ platform_device_register_simple("ar71xx-wdt", -1, NULL, 0); -+} -+ -+void __init ar71xx_set_mac_base(unsigned char *mac) -+{ -+ memcpy(ar71xx_mac_base, mac, ETH_ALEN); -+} -+ -+void __init ar71xx_parse_mac_addr(char *mac_str) -+{ -+ u8 tmp[ETH_ALEN]; -+ int t; -+ -+ t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", -+ &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]); -+ -+ if (t != ETH_ALEN) -+ t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx", -+ &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]); -+ -+ if (t == ETH_ALEN) -+ ar71xx_set_mac_base(tmp); -+ else -+ printk(KERN_DEBUG "ar71xx: failed to parse mac address " -+ "\"%s\"\n", mac_str); -+} -+ -+static int __init ar71xx_ethaddr_setup(char *str) -+{ -+ ar71xx_parse_mac_addr(str); -+ return 1; -+} -+__setup("ethaddr=", ar71xx_ethaddr_setup); -+ -+static int __init ar71xx_kmac_setup(char *str) -+{ -+ ar71xx_parse_mac_addr(str); -+ return 1; -+} -+__setup("kmac=", ar71xx_kmac_setup); -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/devices.h linux-2.6.37/arch/mips/ar71xx/devices.h ---- linux-2.6.37.orig/arch/mips/ar71xx/devices.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/devices.h 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,48 @@ -+/* -+ * Atheros AR71xx SoC device definitions -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef __AR71XX_DEVICES_H -+#define __AR71XX_DEVICES_H -+ -+#include -+ -+struct platform_device; -+ -+void ar71xx_add_device_spi(struct ar71xx_spi_platform_data *pdata, -+ struct spi_board_info const *info, -+ unsigned n) __init; -+ -+void ar71xx_set_mac_base(unsigned char *mac) __init; -+void ar71xx_parse_mac_addr(char *mac_str) __init; -+ -+struct ar71xx_eth_pll_data { -+ u32 pll_10; -+ u32 pll_100; -+ u32 pll_1000; -+}; -+ -+extern struct ar71xx_eth_pll_data ar71xx_eth0_pll_data; -+extern struct ar71xx_eth_pll_data ar71xx_eth1_pll_data; -+ -+extern struct ag71xx_platform_data ar71xx_eth0_data; -+extern struct ag71xx_platform_data ar71xx_eth1_data; -+extern struct platform_device ar71xx_eth0_device; -+extern struct platform_device ar71xx_eth1_device; -+void ar71xx_add_device_eth(unsigned int id) __init; -+ -+extern struct platform_device ar71xx_mdio_device; -+void ar71xx_add_device_mdio(u32 phy_mask) __init; -+ -+void ar71xx_add_device_uart(void) __init; -+ -+void ar71xx_add_device_wdt(void) __init; -+ -+#endif /* __AR71XX_DEVICES_H */ -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/early_printk.c linux-2.6.37/arch/mips/ar71xx/early_printk.c ---- linux-2.6.37.orig/arch/mips/ar71xx/early_printk.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/early_printk.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,30 @@ -+/* -+ * Atheros AR71xx SoC early printk support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+ -+#include -+ -+#define UART_READ(r) \ -+ __raw_readl((void __iomem *)(KSEG1ADDR(AR71XX_UART_BASE) + 4 * (r))) -+ -+#define UART_WRITE(r, v) \ -+ __raw_writel((v), (void __iomem *)(KSEG1ADDR(AR71XX_UART_BASE) + 4*(r))) -+ -+void prom_putchar(unsigned char ch) -+{ -+ while (((UART_READ(UART_LSR)) & UART_LSR_THRE) == 0); -+ UART_WRITE(UART_TX, ch); -+ while (((UART_READ(UART_LSR)) & UART_LSR_THRE) == 0); -+} -+ -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/gpio.c linux-2.6.37/arch/mips/ar71xx/gpio.c ---- linux-2.6.37.orig/arch/mips/ar71xx/gpio.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/gpio.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,182 @@ -+/* -+ * Atheros AR71xx SoC GPIO API support -+ * -+ * Copyright (C) 2008-2010 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+static DEFINE_SPINLOCK(ar71xx_gpio_lock); -+ -+unsigned long ar71xx_gpio_count; -+EXPORT_SYMBOL(ar71xx_gpio_count); -+ -+void __ar71xx_gpio_set_value(unsigned gpio, int value) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ -+ if (value) -+ __raw_writel(1 << gpio, base + GPIO_REG_SET); -+ else -+ __raw_writel(1 << gpio, base + GPIO_REG_CLEAR); -+} -+EXPORT_SYMBOL(__ar71xx_gpio_set_value); -+ -+int __ar71xx_gpio_get_value(unsigned gpio) -+{ -+ return (__raw_readl(ar71xx_gpio_base + GPIO_REG_IN) >> gpio) & 1; -+} -+EXPORT_SYMBOL(__ar71xx_gpio_get_value); -+ -+static int ar71xx_gpio_get_value(struct gpio_chip *chip, unsigned offset) -+{ -+ return __ar71xx_gpio_get_value(offset); -+} -+ -+static void ar71xx_gpio_set_value(struct gpio_chip *chip, -+ unsigned offset, int value) -+{ -+ __ar71xx_gpio_set_value(offset, value); -+} -+ -+static int ar71xx_gpio_direction_input(struct gpio_chip *chip, -+ unsigned offset) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&ar71xx_gpio_lock, flags); -+ -+ __raw_writel(__raw_readl(base + GPIO_REG_OE) & ~(1 << offset), -+ base + GPIO_REG_OE); -+ -+ spin_unlock_irqrestore(&ar71xx_gpio_lock, flags); -+ -+ return 0; -+} -+ -+static int ar71xx_gpio_direction_output(struct gpio_chip *chip, -+ unsigned offset, int value) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&ar71xx_gpio_lock, flags); -+ -+ if (value) -+ __raw_writel(1 << offset, base + GPIO_REG_SET); -+ else -+ __raw_writel(1 << offset, base + GPIO_REG_CLEAR); -+ -+ __raw_writel(__raw_readl(base + GPIO_REG_OE) | (1 << offset), -+ base + GPIO_REG_OE); -+ -+ spin_unlock_irqrestore(&ar71xx_gpio_lock, flags); -+ -+ return 0; -+} -+ -+static struct gpio_chip ar71xx_gpio_chip = { -+ .label = "ar71xx", -+ .get = ar71xx_gpio_get_value, -+ .set = ar71xx_gpio_set_value, -+ .direction_input = ar71xx_gpio_direction_input, -+ .direction_output = ar71xx_gpio_direction_output, -+ .base = 0, -+ .ngpio = AR71XX_GPIO_COUNT, -+}; -+ -+void ar71xx_gpio_function_enable(u32 mask) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&ar71xx_gpio_lock, flags); -+ -+ __raw_writel(__raw_readl(base + GPIO_REG_FUNC) | mask, -+ base + GPIO_REG_FUNC); -+ /* flush write */ -+ (void) __raw_readl(base + GPIO_REG_FUNC); -+ -+ spin_unlock_irqrestore(&ar71xx_gpio_lock, flags); -+} -+ -+void ar71xx_gpio_function_disable(u32 mask) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&ar71xx_gpio_lock, flags); -+ -+ __raw_writel(__raw_readl(base + GPIO_REG_FUNC) & ~mask, -+ base + GPIO_REG_FUNC); -+ /* flush write */ -+ (void) __raw_readl(base + GPIO_REG_FUNC); -+ -+ spin_unlock_irqrestore(&ar71xx_gpio_lock, flags); -+} -+ -+void ar71xx_gpio_function_setup(u32 set, u32 clear) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&ar71xx_gpio_lock, flags); -+ -+ __raw_writel((__raw_readl(base + GPIO_REG_FUNC) & ~clear) | set, -+ base + GPIO_REG_FUNC); -+ /* flush write */ -+ (void) __raw_readl(base + GPIO_REG_FUNC); -+ -+ spin_unlock_irqrestore(&ar71xx_gpio_lock, flags); -+} -+EXPORT_SYMBOL(ar71xx_gpio_function_setup); -+ -+void __init ar71xx_gpio_init(void) -+{ -+ int err; -+ -+ if (!request_mem_region(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE, -+ "AR71xx GPIO controller")) -+ panic("cannot allocate AR71xx GPIO registers page"); -+ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7130: -+ case AR71XX_SOC_AR7141: -+ case AR71XX_SOC_AR7161: -+ ar71xx_gpio_chip.ngpio = AR71XX_GPIO_COUNT; -+ break; -+ -+ case AR71XX_SOC_AR7240: -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ ar71xx_gpio_chip.ngpio = AR724X_GPIO_COUNT; -+ break; -+ -+ case AR71XX_SOC_AR9130: -+ case AR71XX_SOC_AR9132: -+ ar71xx_gpio_chip.ngpio = AR91XX_GPIO_COUNT; -+ break; -+ -+ default: -+ BUG(); -+ } -+ -+ err = gpiochip_add(&ar71xx_gpio_chip); -+ if (err) -+ panic("cannot add AR71xx GPIO chip, error=%d", err); -+} -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/irq.c linux-2.6.37/arch/mips/ar71xx/irq.c ---- linux-2.6.37.orig/arch/mips/ar71xx/irq.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/irq.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,295 @@ -+/* -+ * Atheros AR71xx SoC specific interrupt handling -+ * -+ * Copyright (C) 2008-2010 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include -+ -+static int ip2_flush_reg; -+ -+static void ar71xx_gpio_irq_dispatch(void) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ u32 pending; -+ -+ pending = __raw_readl(base + GPIO_REG_INT_PENDING) & -+ __raw_readl(base + GPIO_REG_INT_ENABLE); -+ -+ if (pending) -+ do_IRQ(AR71XX_GPIO_IRQ_BASE + fls(pending) - 1); -+ else -+ spurious_interrupt(); -+} -+ -+static void ar71xx_gpio_irq_unmask(unsigned int irq) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ u32 t; -+ -+ irq -= AR71XX_GPIO_IRQ_BASE; -+ -+ t = __raw_readl(base + GPIO_REG_INT_ENABLE); -+ __raw_writel(t | (1 << irq), base + GPIO_REG_INT_ENABLE); -+ -+ /* flush write */ -+ (void) __raw_readl(base + GPIO_REG_INT_ENABLE); -+} -+ -+static void ar71xx_gpio_irq_mask(unsigned int irq) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ u32 t; -+ -+ irq -= AR71XX_GPIO_IRQ_BASE; -+ -+ t = __raw_readl(base + GPIO_REG_INT_ENABLE); -+ __raw_writel(t & ~(1 << irq), base + GPIO_REG_INT_ENABLE); -+ -+ /* flush write */ -+ (void) __raw_readl(base + GPIO_REG_INT_ENABLE); -+} -+ -+#if 0 -+static int ar71xx_gpio_irq_set_type(unsigned int irq, unsigned int flow_type) -+{ -+ /* TODO: implement */ -+ return 0; -+} -+#else -+#define ar71xx_gpio_irq_set_type NULL -+#endif -+ -+static struct irq_chip ar71xx_gpio_irq_chip = { -+ .name = "AR71XX GPIO", -+ .unmask = ar71xx_gpio_irq_unmask, -+ .mask = ar71xx_gpio_irq_mask, -+ .mask_ack = ar71xx_gpio_irq_mask, -+ .set_type = ar71xx_gpio_irq_set_type, -+}; -+ -+static struct irqaction ar71xx_gpio_irqaction = { -+ .handler = no_action, -+ .name = "cascade [AR71XX GPIO]", -+}; -+ -+#define GPIO_IRQ_INIT_STATUS (IRQ_LEVEL | IRQ_TYPE_LEVEL_HIGH | IRQ_DISABLED) -+#define GPIO_INT_ALL 0xffff -+ -+static void __init ar71xx_gpio_irq_init(void) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ int i; -+ -+ __raw_writel(0, base + GPIO_REG_INT_ENABLE); -+ __raw_writel(0, base + GPIO_REG_INT_PENDING); -+ -+ /* setup type of all GPIO interrupts to level sensitive */ -+ __raw_writel(GPIO_INT_ALL, base + GPIO_REG_INT_TYPE); -+ -+ /* setup polarity of all GPIO interrupts to active high */ -+ __raw_writel(GPIO_INT_ALL, base + GPIO_REG_INT_POLARITY); -+ -+ for (i = AR71XX_GPIO_IRQ_BASE; -+ i < AR71XX_GPIO_IRQ_BASE + AR71XX_GPIO_IRQ_COUNT; i++) { -+ irq_desc[i].status = GPIO_IRQ_INIT_STATUS; -+ set_irq_chip_and_handler(i, &ar71xx_gpio_irq_chip, -+ handle_level_irq); -+ } -+ -+ setup_irq(AR71XX_MISC_IRQ_GPIO, &ar71xx_gpio_irqaction); -+} -+ -+static void ar71xx_misc_irq_dispatch(void) -+{ -+ u32 pending; -+ -+ pending = ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS) -+ & ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE); -+ -+ if (pending & MISC_INT_UART) -+ do_IRQ(AR71XX_MISC_IRQ_UART); -+ -+ else if (pending & MISC_INT_DMA) -+ do_IRQ(AR71XX_MISC_IRQ_DMA); -+ -+ else if (pending & MISC_INT_PERFC) -+ do_IRQ(AR71XX_MISC_IRQ_PERFC); -+ -+ else if (pending & MISC_INT_TIMER) -+ do_IRQ(AR71XX_MISC_IRQ_TIMER); -+ -+ else if (pending & MISC_INT_OHCI) -+ do_IRQ(AR71XX_MISC_IRQ_OHCI); -+ -+ else if (pending & MISC_INT_ERROR) -+ do_IRQ(AR71XX_MISC_IRQ_ERROR); -+ -+ else if (pending & MISC_INT_GPIO) -+ ar71xx_gpio_irq_dispatch(); -+ -+ else if (pending & MISC_INT_WDOG) -+ do_IRQ(AR71XX_MISC_IRQ_WDOG); -+ -+ else -+ spurious_interrupt(); -+} -+ -+static void ar71xx_misc_irq_unmask(unsigned int irq) -+{ -+ void __iomem *base = ar71xx_reset_base; -+ u32 t; -+ -+ irq -= AR71XX_MISC_IRQ_BASE; -+ -+ t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); -+ __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE); -+ -+ /* flush write */ -+ (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); -+} -+ -+static void ar71xx_misc_irq_mask(unsigned int irq) -+{ -+ void __iomem *base = ar71xx_reset_base; -+ u32 t; -+ -+ irq -= AR71XX_MISC_IRQ_BASE; -+ -+ t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); -+ __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE); -+ -+ /* flush write */ -+ (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); -+} -+ -+static void ar724x_misc_irq_ack(unsigned int irq) -+{ -+ void __iomem *base = ar71xx_reset_base; -+ u32 t; -+ -+ irq -= AR71XX_MISC_IRQ_BASE; -+ -+ t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS); -+ __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_STATUS); -+ -+ /* flush write */ -+ (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS); -+} -+ -+static struct irq_chip ar71xx_misc_irq_chip = { -+ .name = "AR71XX MISC", -+ .unmask = ar71xx_misc_irq_unmask, -+ .mask = ar71xx_misc_irq_mask, -+}; -+ -+static struct irqaction ar71xx_misc_irqaction = { -+ .handler = no_action, -+ .name = "cascade [AR71XX MISC]", -+}; -+ -+static void __init ar71xx_misc_irq_init(void) -+{ -+ void __iomem *base = ar71xx_reset_base; -+ int i; -+ -+ __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE); -+ __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS); -+ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7240: -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ ar71xx_misc_irq_chip.ack = ar724x_misc_irq_ack; -+ break; -+ default: -+ ar71xx_misc_irq_chip.mask_ack = ar71xx_misc_irq_mask; -+ break; -+ } -+ -+ for (i = AR71XX_MISC_IRQ_BASE; -+ i < AR71XX_MISC_IRQ_BASE + AR71XX_MISC_IRQ_COUNT; i++) { -+ irq_desc[i].status = IRQ_DISABLED; -+ set_irq_chip_and_handler(i, &ar71xx_misc_irq_chip, -+ handle_level_irq); -+ } -+ -+ setup_irq(AR71XX_CPU_IRQ_MISC, &ar71xx_misc_irqaction); -+} -+ -+asmlinkage void plat_irq_dispatch(void) -+{ -+ unsigned long pending; -+ -+ pending = read_c0_status() & read_c0_cause() & ST0_IM; -+ -+ if (pending & STATUSF_IP7) -+ do_IRQ(AR71XX_CPU_IRQ_TIMER); -+ -+ else if (pending & STATUSF_IP2) { -+ /* -+ * This IRQ is meant for a PCI device. Drivers for PCI devices -+ * typically allocate coherent DMA memory for the descriptor -+ * ring, however the DMA controller may still have some -+ * unsynchronized data in the FIFO. -+ * Issue a flush here to ensure that the driver sees the update. -+ */ -+ ar71xx_ddr_flush(ip2_flush_reg); -+ do_IRQ(AR71XX_CPU_IRQ_IP2); -+ } -+ -+ else if (pending & STATUSF_IP4) -+ do_IRQ(AR71XX_CPU_IRQ_GE0); -+ -+ else if (pending & STATUSF_IP5) -+ do_IRQ(AR71XX_CPU_IRQ_GE1); -+ -+ else if (pending & STATUSF_IP3) -+ do_IRQ(AR71XX_CPU_IRQ_USB); -+ -+ else if (pending & STATUSF_IP6) -+ ar71xx_misc_irq_dispatch(); -+ -+ else -+ spurious_interrupt(); -+} -+ -+void __init arch_init_irq(void) -+{ -+ switch(ar71xx_soc) { -+ case AR71XX_SOC_AR7240: -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ ip2_flush_reg = AR724X_DDR_REG_FLUSH_PCIE; -+ break; -+ case AR71XX_SOC_AR9130: -+ case AR71XX_SOC_AR9132: -+ ip2_flush_reg = AR91XX_DDR_REG_FLUSH_WMAC; -+ break; -+ default: -+ ip2_flush_reg = AR71XX_DDR_REG_FLUSH_PCI; -+ break; -+ } -+ mips_cpu_irq_init(); -+ -+ ar71xx_misc_irq_init(); -+ -+ cp0_perfcount_irq = AR71XX_MISC_IRQ_PERFC; -+ -+ ar71xx_gpio_irq_init(); -+} -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/mach-ap81.c linux-2.6.37/arch/mips/ar71xx/mach-ap81.c ---- linux-2.6.37.orig/arch/mips/ar71xx/mach-ap81.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/mach-ap81.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,140 @@ -+/* -+ * Atheros AP81 board support -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * Copyright (C) 2009 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ar913x-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-usb.h" -+ -+#define AP81_GPIO_LED_STATUS 1 -+#define AP81_GPIO_LED_AOSS 3 -+#define AP81_GPIO_LED_WLAN 6 -+#define AP81_GPIO_LED_POWER 14 -+ -+#define AP81_GPIO_BTN_SW4 12 -+#define AP81_GPIO_BTN_SW1 21 -+ -+#define AP81_BUTTONS_POLL_INTERVAL 20 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition ap81_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x040000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "u-boot-env", -+ .offset = 0x040000, -+ .size = 0x010000, -+ } , { -+ .name = "rootfs", -+ .offset = 0x050000, -+ .size = 0x500000, -+ } , { -+ .name = "uImage", -+ .offset = 0x550000, -+ .size = 0x100000, -+ } , { -+ .name = "ART", -+ .offset = 0x650000, -+ .size = 0x1b0000, -+ .mask_flags = MTD_WRITEABLE, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data ap81_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = ap81_partitions, -+ .nr_parts = ARRAY_SIZE(ap81_partitions), -+#endif -+}; -+ -+static struct gpio_led ap81_leds_gpio[] __initdata = { -+ { -+ .name = "ap81:green:status", -+ .gpio = AP81_GPIO_LED_STATUS, -+ .active_low = 1, -+ }, { -+ .name = "ap81:amber:aoss", -+ .gpio = AP81_GPIO_LED_AOSS, -+ .active_low = 1, -+ }, { -+ .name = "ap81:green:wlan", -+ .gpio = AP81_GPIO_LED_WLAN, -+ .active_low = 1, -+ }, { -+ .name = "ap81:green:power", -+ .gpio = AP81_GPIO_LED_POWER, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_button ap81_gpio_buttons[] __initdata = { -+ { -+ .desc = "sw1", -+ .type = EV_KEY, -+ .code = BTN_0, -+ .threshold = 3, -+ .gpio = AP81_GPIO_BTN_SW1, -+ .active_low = 1, -+ } , { -+ .desc = "sw4", -+ .type = EV_KEY, -+ .code = BTN_1, -+ .threshold = 3, -+ .gpio = AP81_GPIO_BTN_SW4, -+ .active_low = 1, -+ } -+}; -+ -+static void __init ap81_setup(void) -+{ -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ -+ ar71xx_set_mac_base(eeprom); -+ ar71xx_add_device_mdio(0x0); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ ar71xx_eth0_data.has_ar8216 = 1; -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.phy_mask = 0x10; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_usb(); -+ -+ ar71xx_add_device_m25p80(&ap81_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ap81_leds_gpio), -+ ap81_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, AP81_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(ap81_gpio_buttons), -+ ap81_gpio_buttons); -+ -+ ar913x_add_device_wmac(eeprom, NULL); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_AP81, "AP81", "Atheros AP81", ap81_setup); -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/mach-ap83.c linux-2.6.37/arch/mips/ar71xx/mach-ap83.c ---- linux-2.6.37.orig/arch/mips/ar71xx/mach-ap83.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/mach-ap83.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,266 @@ -+/* -+ * Atheros AP83 board support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-ar913x-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-usb.h" -+ -+#define AP83_GPIO_LED_WLAN 6 -+#define AP83_GPIO_LED_POWER 14 -+#define AP83_GPIO_LED_JUMPSTART 15 -+#define AP83_GPIO_BTN_JUMPSTART 12 -+#define AP83_GPIO_BTN_RESET 21 -+ -+#define AP83_050_GPIO_VSC7385_CS 1 -+#define AP83_050_GPIO_VSC7385_MISO 3 -+#define AP83_050_GPIO_VSC7385_MOSI 16 -+#define AP83_050_GPIO_VSC7385_SCK 17 -+ -+#define AP83_BUTTONS_POLL_INTERVAL 20 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition ap83_flash_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x040000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "u-boot-env", -+ .offset = 0x040000, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "kernel", -+ .offset = 0x060000, -+ .size = 0x140000, -+ } , { -+ .name = "rootfs", -+ .offset = 0x1a0000, -+ .size = 0x650000, -+ } , { -+ .name = "art", -+ .offset = 0x7f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "firmware", -+ .offset = 0x060000, -+ .size = 0x790000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct ar91xx_flash_platform_data ap83_flash_data = { -+ .width = 2, -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = ap83_flash_partitions, -+ .nr_parts = ARRAY_SIZE(ap83_flash_partitions), -+#endif -+}; -+ -+static struct resource ap83_flash_resources[] = { -+ [0] = { -+ .start = AR71XX_SPI_BASE, -+ .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+}; -+ -+static struct platform_device ap83_flash_device = { -+ .name = "ar91xx-flash", -+ .id = -1, -+ .resource = ap83_flash_resources, -+ .num_resources = ARRAY_SIZE(ap83_flash_resources), -+ .dev = { -+ .platform_data = &ap83_flash_data, -+ } -+}; -+ -+static struct gpio_led ap83_leds_gpio[] __initdata = { -+ { -+ .name = "ap83:green:jumpstart", -+ .gpio = AP83_GPIO_LED_JUMPSTART, -+ .active_low = 0, -+ }, { -+ .name = "ap83:green:power", -+ .gpio = AP83_GPIO_LED_POWER, -+ .active_low = 0, -+ }, { -+ .name = "ap83:green:wlan", -+ .gpio = AP83_GPIO_LED_WLAN, -+ .active_low = 0, -+ }, -+}; -+ -+static struct gpio_button ap83_gpio_buttons[] __initdata = { -+ { -+ .desc = "soft_reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = AP83_GPIO_BTN_RESET, -+ .active_low = 1, -+ } , { -+ .desc = "jumpstart", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = AP83_GPIO_BTN_JUMPSTART, -+ .active_low = 1, -+ } -+}; -+ -+static struct resource ap83_040_spi_resources[] = { -+ [0] = { -+ .start = AR71XX_SPI_BASE, -+ .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+}; -+ -+static struct platform_device ap83_040_spi_device = { -+ .name = "ap83-spi", -+ .id = 0, -+ .resource = ap83_040_spi_resources, -+ .num_resources = ARRAY_SIZE(ap83_040_spi_resources), -+}; -+ -+static struct spi_gpio_platform_data ap83_050_spi_data = { -+ .miso = AP83_050_GPIO_VSC7385_MISO, -+ .mosi = AP83_050_GPIO_VSC7385_MOSI, -+ .sck = AP83_050_GPIO_VSC7385_SCK, -+ .num_chipselect = 1, -+}; -+ -+static struct platform_device ap83_050_spi_device = { -+ .name = "spi_gpio", -+ .id = 0, -+ .dev = { -+ .platform_data = &ap83_050_spi_data, -+ } -+}; -+ -+static void ap83_vsc7385_reset(void) -+{ -+ ar71xx_device_stop(RESET_MODULE_GE1_PHY); -+ udelay(10); -+ ar71xx_device_start(RESET_MODULE_GE1_PHY); -+ mdelay(50); -+} -+ -+static struct vsc7385_platform_data ap83_vsc7385_data = { -+ .reset = ap83_vsc7385_reset, -+ .ucode_name = "vsc7385_ucode_ap83.bin", -+ .mac_cfg = { -+ .tx_ipg = 6, -+ .bit2 = 0, -+ .clk_sel = 3, -+ }, -+}; -+ -+static struct spi_board_info ap83_spi_info[] = { -+ { -+ .bus_num = 0, -+ .chip_select = 0, -+ .max_speed_hz = 25000000, -+ .modalias = "spi-vsc7385", -+ .platform_data = &ap83_vsc7385_data, -+ .controller_data = (void *) AP83_050_GPIO_VSC7385_CS, -+ } -+}; -+ -+static void __init ap83_generic_setup(void) -+{ -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ -+ ar71xx_set_mac_base(eeprom); -+ -+ ar71xx_add_device_mdio(0xfffffffe); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth0_data.phy_mask = 0x1; -+ -+ ar71xx_add_device_eth(0); -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth1_data.speed = SPEED_1000; -+ ar71xx_eth1_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_eth1_pll_data.pll_1000 = 0x1f000000; -+ -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ap83_leds_gpio), -+ ap83_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, AP83_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(ap83_gpio_buttons), -+ ap83_gpio_buttons); -+ -+ ar71xx_add_device_usb(); -+ -+ ar913x_add_device_wmac(eeprom, NULL); -+ -+ platform_device_register(&ap83_flash_device); -+ -+ spi_register_board_info(ap83_spi_info, ARRAY_SIZE(ap83_spi_info)); -+} -+ -+static void __init ap83_040_setup(void) -+{ -+ ap83_flash_data.is_shared=1; -+ ap83_generic_setup(); -+ platform_device_register(&ap83_040_spi_device); -+} -+ -+static void __init ap83_050_setup(void) -+{ -+ ap83_generic_setup(); -+ platform_device_register(&ap83_050_spi_device); -+} -+ -+static void __init ap83_setup(void) -+{ -+ u8 *board_id = (u8 *) KSEG1ADDR(0x1fff1244); -+ unsigned int board_version; -+ -+ board_version = (unsigned int)(board_id[0] - '0'); -+ board_version += ((unsigned int)(board_id[1] - '0')) * 10; -+ -+ switch (board_version) { -+ case 40: -+ ap83_040_setup(); -+ break; -+ case 50: -+ ap83_050_setup(); -+ break; -+ default: -+ printk(KERN_WARNING "AP83-%03u board is not yet supported\n", -+ board_version); -+ } -+} -+ -+MIPS_MACHINE(AR71XX_MACH_AP83, "AP83", "Atheros AP83", ap83_setup); -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/mach-aw-nr580.c linux-2.6.37/arch/mips/ar71xx/mach-aw-nr580.c ---- linux-2.6.37.orig/arch/mips/ar71xx/mach-aw-nr580.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/mach-aw-nr580.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,101 @@ -+/* -+ * AzureWave AW-NR580 board support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-gpio-buttons.h" -+#include "dev-pb42-pci.h" -+#include "dev-leds-gpio.h" -+ -+#define AW_NR580_GPIO_LED_READY_RED 0 -+#define AW_NR580_GPIO_LED_WLAN 1 -+#define AW_NR580_GPIO_LED_READY_GREEN 2 -+#define AW_NR580_GPIO_LED_WPS_GREEN 4 -+#define AW_NR580_GPIO_LED_WPS_AMBER 5 -+ -+#define AW_NR580_GPIO_BTN_WPS 3 -+#define AW_NR580_GPIO_BTN_RESET 11 -+ -+#define AW_NR580_BUTTONS_POLL_INTERVAL 20 -+ -+static struct gpio_led aw_nr580_leds_gpio[] __initdata = { -+ { -+ .name = "aw-nr580:red:ready", -+ .gpio = AW_NR580_GPIO_LED_READY_RED, -+ .active_low = 0, -+ }, { -+ .name = "aw-nr580:green:ready", -+ .gpio = AW_NR580_GPIO_LED_READY_GREEN, -+ .active_low = 0, -+ }, { -+ .name = "aw-nr580:green:wps", -+ .gpio = AW_NR580_GPIO_LED_WPS_GREEN, -+ .active_low = 0, -+ }, { -+ .name = "aw-nr580:amber:wps", -+ .gpio = AW_NR580_GPIO_LED_WPS_AMBER, -+ .active_low = 0, -+ }, { -+ .name = "aw-nr580:green:wlan", -+ .gpio = AW_NR580_GPIO_LED_WLAN, -+ .active_low = 0, -+ } -+}; -+ -+static struct gpio_button aw_nr580_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = AW_NR580_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "wps", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = AW_NR580_GPIO_BTN_WPS, -+ .active_low = 1, -+ } -+}; -+ -+static void __init aw_nr580_setup(void) -+{ -+ ar71xx_add_device_mdio(0x0); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_add_device_eth(0); -+ -+ pb42_pci_init(); -+ -+ ar71xx_add_device_m25p80(NULL); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(aw_nr580_leds_gpio), -+ aw_nr580_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, AW_NR580_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(aw_nr580_gpio_buttons), -+ aw_nr580_gpio_buttons); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_AW_NR580, "AW-NR580", "AzureWave AW-NR580", -+ aw_nr580_setup); -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/mach-dir-600-a1.c linux-2.6.37/arch/mips/ar71xx/mach-dir-600-a1.c ---- linux-2.6.37.orig/arch/mips/ar71xx/mach-dir-600-a1.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/mach-dir-600-a1.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,138 @@ -+/* -+ * D-Link DIR-600 rev. A1 board support -+ * -+ * Copyright (C) 2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ap91-eth.h" -+#include "dev-ap91-pci.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "nvram.h" -+ -+#define DIR_600_A1_GPIO_LED_WPS 0 -+#define DIR_600_A1_GPIO_LED_POWER_AMBER 1 -+#define DIR_600_A1_GPIO_LED_POWER_GREEN 6 -+ -+#define DIR_600_A1_GPIO_BTN_RESET 8 -+#define DIR_600_A1_GPIO_BTN_WPS 12 -+ -+#define DIR_600_A1_BUTTONS_POLL_INTERVAL 20 -+ -+#define DIR_600_A1_NVRAM_ADDR 0x1f030000 -+#define DIR_600_A1_NVRAM_SIZE 0x10000 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition dir_600_a1_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x030000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "nvram", -+ .offset = 0x030000, -+ .size = 0x010000, -+ }, { -+ .name = "kernel", -+ .offset = 0x040000, -+ .size = 0x0e0000, -+ }, { -+ .name = "rootfs", -+ .offset = 0x120000, -+ .size = 0x2c0000, -+ }, { -+ .name = "mac", -+ .offset = 0x3e0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "art", -+ .offset = 0x3f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "firmware", -+ .offset = 0x040000, -+ .size = 0x3a0000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data dir_600_a1_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = dir_600_a1_partitions, -+ .nr_parts = ARRAY_SIZE(dir_600_a1_partitions), -+#endif -+}; -+ -+static struct gpio_led dir_600_a1_leds_gpio[] __initdata = { -+ { -+ .name = "dir-600-a1:green:power", -+ .gpio = DIR_600_A1_GPIO_LED_POWER_GREEN, -+ }, { -+ .name = "dir-600-a1:amber:power", -+ .gpio = DIR_600_A1_GPIO_LED_POWER_AMBER, -+ }, { -+ .name = "dir-600-a1:blue:wps", -+ .gpio = DIR_600_A1_GPIO_LED_WPS, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_button dir_600_a1_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = DIR_600_A1_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "wps", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = DIR_600_A1_GPIO_BTN_WPS, -+ .active_low = 1, -+ } -+}; -+ -+static void __init dir_600_a1_setup(void) -+{ -+ const char *nvram = (char *) KSEG1ADDR(DIR_600_A1_NVRAM_ADDR); -+ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); -+ u8 mac_buff[6]; -+ u8 *mac = NULL; -+ -+ if (nvram_parse_mac_addr(nvram, DIR_600_A1_NVRAM_SIZE, -+ "lan_mac=", mac_buff) == 0) -+ mac = mac_buff; -+ -+ ar71xx_add_device_m25p80(&dir_600_a1_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(dir_600_a1_leds_gpio), -+ dir_600_a1_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, DIR_600_A1_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(dir_600_a1_gpio_buttons), -+ dir_600_a1_gpio_buttons); -+ -+ ap91_eth_init(mac, NULL); -+ ap91_pci_init(ee, mac); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_DIR_600_A1, "DIR-600-A1", "D-Link DIR-600 rev. A1", -+ dir_600_a1_setup); -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/mach-dir-615-c1.c linux-2.6.37/arch/mips/ar71xx/mach-dir-615-c1.c ---- linux-2.6.37.orig/arch/mips/ar71xx/mach-dir-615-c1.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/mach-dir-615-c1.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,173 @@ -+/* -+ * D-Link DIR-615 rev C1 board support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ar913x-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "nvram.h" -+ -+#define DIR_615C1_GPIO_LED_ORANGE_STATUS 1 /* ORANGE:STATUS:TRICOLOR */ -+#define DIR_615C1_GPIO_LED_BLUE_WPS 3 /* BLUE:WPS */ -+#define DIR_615C1_GPIO_LED_GREEN_WAN 4 /* GREEN:WAN:TRICOLOR */ -+#define DIR_615C1_GPIO_LED_GREEN_WANCPU 5 /* GREEN:WAN:CPU:TRICOLOR */ -+#define DIR_615C1_GPIO_LED_GREEN_WLAN 6 /* GREEN:WLAN */ -+#define DIR_615C1_GPIO_LED_GREEN_STATUS 14 /* GREEN:STATUS:TRICOLOR */ -+#define DIR_615C1_GPIO_LED_ORANGE_WAN 15 /* ORANGE:WAN:TRICOLOR */ -+ -+/* buttons may need refinement */ -+ -+#define DIR_615C1_GPIO_BTN_WPS 12 -+#define DIR_615C1_GPIO_BTN_RESET 21 -+ -+#define DIR_615C1_BUTTONS_POLL_INTERVAL 20 -+ -+#define DIR_615C1_CONFIG_ADDR 0x1f020000 -+#define DIR_615C1_CONFIG_SIZE 0x10000 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition dir_615c1_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "config", -+ .offset = 0x020000, -+ .size = 0x010000, -+ } , { -+ .name = "kernel", -+ .offset = 0x030000, -+ .size = 0x0d0000, -+ } , { -+ .name = "rootfs", -+ .offset = 0x100000, -+ .size = 0x2f0000, -+ } , { -+ .name = "art", -+ .offset = 0x3f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "firmware", -+ .offset = 0x030000, -+ .size = 0x3c0000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data dir_615c1_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = dir_615c1_partitions, -+ .nr_parts = ARRAY_SIZE(dir_615c1_partitions), -+#endif -+}; -+ -+static struct gpio_led dir_615c1_leds_gpio[] __initdata = { -+ { -+ .name = "dir-615c1:orange:status", -+ .gpio = DIR_615C1_GPIO_LED_ORANGE_STATUS, -+ .active_low = 1, -+ }, { -+ .name = "dir-615c1:blue:wps", -+ .gpio = DIR_615C1_GPIO_LED_BLUE_WPS, -+ .active_low = 1, -+ }, { -+ .name = "dir-615c1:green:wan", -+ .gpio = DIR_615C1_GPIO_LED_GREEN_WAN, -+ .active_low = 1, -+ }, { -+ .name = "dir-615c1:green:wancpu", -+ .gpio = DIR_615C1_GPIO_LED_GREEN_WANCPU, -+ .active_low = 1, -+ }, { -+ .name = "dir-615c1:green:wlan", -+ .gpio = DIR_615C1_GPIO_LED_GREEN_WLAN, -+ .active_low = 1, -+ }, { -+ .name = "dir-615c1:green:status", -+ .gpio = DIR_615C1_GPIO_LED_GREEN_STATUS, -+ .active_low = 1, -+ }, { -+ .name = "dir-615c1:orange:wan", -+ .gpio = DIR_615C1_GPIO_LED_ORANGE_WAN, -+ .active_low = 1, -+ } -+ -+}; -+ -+static struct gpio_button dir_615c1_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = DIR_615C1_GPIO_BTN_RESET, -+ }, { -+ .desc = "wps", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = DIR_615C1_GPIO_BTN_WPS, -+ } -+}; -+ -+#define DIR_615C1_LAN_PHYMASK BIT(0) -+#define DIR_615C1_WAN_PHYMASK BIT(4) -+#define DIR_615C1_MDIO_MASK (~(DIR_615C1_LAN_PHYMASK | \ -+ DIR_615C1_WAN_PHYMASK)) -+ -+static void __init dir_615c1_setup(void) -+{ -+ const char *config = (char *) KSEG1ADDR(DIR_615C1_CONFIG_ADDR); -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ u8 mac[6]; -+ u8 *wlan_mac = NULL; -+ -+ if (nvram_parse_mac_addr(config, DIR_615C1_CONFIG_SIZE, -+ "lan_mac=", mac) == 0) { -+ ar71xx_set_mac_base(mac); -+ wlan_mac = mac; -+ } -+ -+ ar71xx_add_device_mdio(DIR_615C1_MDIO_MASK); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.phy_mask = DIR_615C1_LAN_PHYMASK; -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.phy_mask = DIR_615C1_WAN_PHYMASK; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_m25p80(&dir_615c1_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(dir_615c1_leds_gpio), -+ dir_615c1_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, DIR_615C1_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(dir_615c1_gpio_buttons), -+ dir_615c1_gpio_buttons); -+ -+ ar913x_add_device_wmac(eeprom, wlan_mac); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_DIR_615_C1, "DIR-615-C1", "D-Link DIR-615 rev. C1", -+ dir_615c1_setup); -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/mach-dir-825-b1.c linux-2.6.37/arch/mips/ar71xx/mach-dir-825-b1.c ---- linux-2.6.37.orig/arch/mips/ar71xx/mach-dir-825-b1.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/mach-dir-825-b1.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,192 @@ -+/* -+ * D-Link DIR-825 rev. B1 board support -+ * -+ * Copyright (C) 2009 Lukas Kuna, Evkanet, s.r.o. -+ * -+ * based on mach-wndr3700.c -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ap94-pci.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-usb.h" -+ -+#define DIR825B1_GPIO_LED_BLUE_USB 0 -+#define DIR825B1_GPIO_LED_ORANGE_POWER 1 -+#define DIR825B1_GPIO_LED_BLUE_POWER 2 -+#define DIR825B1_GPIO_LED_BLUE_POWERSAVE 4 -+#define DIR825B1_GPIO_LED_ORANGE_PLANET 6 -+#define DIR825B1_GPIO_LED_BLUE_PLANET 11 -+ -+#define DIR825B1_GPIO_BTN_RESET 3 -+#define DIR825B1_GPIO_BTN_POWERSAVE 8 -+ -+#define DIR825B1_GPIO_RTL8366_SDA 5 -+#define DIR825B1_GPIO_RTL8366_SCK 7 -+ -+#define DIR825B1_BUTTONS_POLL_INTERVAL 20 -+ -+#define DIR825B1_CAL_LOCATION_0 0x1f661000 -+#define DIR825B1_CAL_LOCATION_1 0x1f665000 -+ -+#define DIR825B1_MAC_LOCATION_0 0x2ffa81b8 -+#define DIR825B1_MAC_LOCATION_1 0x2ffa8370 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition dir825b1_partitions[] = { -+ { -+ .name = "uboot", -+ .offset = 0, -+ .size = 0x040000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "config", -+ .offset = 0x040000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "firmware", -+ .offset = 0x050000, -+ .size = 0x610000, -+ } , { -+ .name = "caldata", -+ .offset = 0x660000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "unknown", -+ .offset = 0x670000, -+ .size = 0x190000, -+ .mask_flags = MTD_WRITEABLE, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data dir825b1_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = dir825b1_partitions, -+ .nr_parts = ARRAY_SIZE(dir825b1_partitions), -+#endif -+}; -+ -+static struct gpio_led dir825b1_leds_gpio[] __initdata = { -+ { -+ .name = "dir825b1:blue:usb", -+ .gpio = DIR825B1_GPIO_LED_BLUE_USB, -+ .active_low = 1, -+ }, { -+ .name = "dir825b1:orange:power", -+ .gpio = DIR825B1_GPIO_LED_ORANGE_POWER, -+ .active_low = 1, -+ }, { -+ .name = "dir825b1:blue:power", -+ .gpio = DIR825B1_GPIO_LED_BLUE_POWER, -+ .active_low = 1, -+ }, { -+ .name = "dir825b1:blue:powersave", -+ .gpio = DIR825B1_GPIO_LED_BLUE_POWERSAVE, -+ .active_low = 1, -+ }, { -+ .name = "dir825b1:orange:planet", -+ .gpio = DIR825B1_GPIO_LED_ORANGE_PLANET, -+ .active_low = 1, -+ }, { -+ .name = "dir825b1:blue:planet", -+ .gpio = DIR825B1_GPIO_LED_BLUE_PLANET, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_button dir825b1_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = DIR825B1_GPIO_BTN_RESET, -+ .active_low = 1, -+ } , { -+ .desc = "powersave", -+ .type = EV_KEY, -+ .code = BTN_1, -+ .threshold = 3, -+ .gpio = DIR825B1_GPIO_BTN_POWERSAVE, -+ .active_low = 1, -+ } -+}; -+ -+static struct rtl8366s_platform_data dir825b1_rtl8366s_data = { -+ .gpio_sda = DIR825B1_GPIO_RTL8366_SDA, -+ .gpio_sck = DIR825B1_GPIO_RTL8366_SCK, -+}; -+ -+static struct platform_device dir825b1_rtl8366s_device = { -+ .name = RTL8366S_DRIVER_NAME, -+ .id = -1, -+ .dev = { -+ .platform_data = &dir825b1_rtl8366s_data, -+ } -+}; -+ -+static void __init dir825b1_setup(void) -+{ -+ u8 mac[6], i; -+ -+ memcpy(mac, (u8*)KSEG1ADDR(DIR825B1_MAC_LOCATION_1), 6); -+ for(i = 5; i >= 3; i--) -+ if(++mac[i] != 0x00) break; -+ -+ ar71xx_set_mac_base(mac); -+ -+ ar71xx_add_device_mdio(0x0); -+ -+ ar71xx_eth0_data.mii_bus_dev = &dir825b1_rtl8366s_device.dev; -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth0_data.speed = SPEED_1000; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ ar71xx_eth0_pll_data.pll_1000 = 0x11110000; -+ -+ ar71xx_eth1_data.mii_bus_dev = &dir825b1_rtl8366s_device.dev; -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth1_data.phy_mask = 0x10; -+ ar71xx_eth1_pll_data.pll_1000 = 0x11110000; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_m25p80(&dir825b1_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(dir825b1_leds_gpio), -+ dir825b1_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, DIR825B1_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(dir825b1_gpio_buttons), -+ dir825b1_gpio_buttons); -+ -+ ar71xx_add_device_usb(); -+ -+ platform_device_register(&dir825b1_rtl8366s_device); -+ -+ ap94_pci_init((u8 *) KSEG1ADDR(DIR825B1_CAL_LOCATION_0), -+ (u8 *) KSEG1ADDR(DIR825B1_MAC_LOCATION_0), -+ (u8 *) KSEG1ADDR(DIR825B1_CAL_LOCATION_1), -+ (u8 *) KSEG1ADDR(DIR825B1_MAC_LOCATION_1)); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_DIR_825_B1, "DIR-825-B1", "D-Link DIR-825 rev. B1", -+ dir825b1_setup); -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/mach-mzk-w04nu.c linux-2.6.37/arch/mips/ar71xx/mach-mzk-w04nu.c ---- linux-2.6.37.orig/arch/mips/ar71xx/mach-mzk-w04nu.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/mach-mzk-w04nu.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,165 @@ -+/* -+ * Planex MZK-W04NU board support -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-ar913x-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-m25p80.h" -+#include "dev-usb.h" -+ -+#define MZK_W04NU_GPIO_LED_USB 0 -+#define MZK_W04NU_GPIO_LED_STATUS 1 -+#define MZK_W04NU_GPIO_LED_WPS 3 -+#define MZK_W04NU_GPIO_LED_WLAN 6 -+#define MZK_W04NU_GPIO_LED_AP 15 -+#define MZK_W04NU_GPIO_LED_ROUTER 16 -+ -+#define MZK_W04NU_GPIO_BTN_APROUTER 5 -+#define MZK_W04NU_GPIO_BTN_WPS 12 -+#define MZK_W04NU_GPIO_BTN_RESET 21 -+ -+#define MZK_W04NU_BUTTONS_POLL_INTERVAL 20 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition mzk_w04nu_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x040000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "u-boot-env", -+ .offset = 0x040000, -+ .size = 0x010000, -+ } , { -+ .name = "kernel", -+ .offset = 0x050000, -+ .size = 0x160000, -+ } , { -+ .name = "rootfs", -+ .offset = 0x1b0000, -+ .size = 0x630000, -+ } , { -+ .name = "art", -+ .offset = 0x7e0000, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "firmware", -+ .offset = 0x050000, -+ .size = 0x790000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data mzk_w04nu_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = mzk_w04nu_partitions, -+ .nr_parts = ARRAY_SIZE(mzk_w04nu_partitions), -+#endif -+}; -+ -+static struct gpio_led mzk_w04nu_leds_gpio[] __initdata = { -+ { -+ .name = "mzk-w04nu:green:status", -+ .gpio = MZK_W04NU_GPIO_LED_STATUS, -+ .active_low = 1, -+ }, { -+ .name = "mzk-w04nu:blue:wps", -+ .gpio = MZK_W04NU_GPIO_LED_WPS, -+ .active_low = 1, -+ }, { -+ .name = "mzk-w04nu:green:wlan", -+ .gpio = MZK_W04NU_GPIO_LED_WLAN, -+ .active_low = 1, -+ }, { -+ .name = "mzk-w04nu:green:usb", -+ .gpio = MZK_W04NU_GPIO_LED_USB, -+ .active_low = 1, -+ }, { -+ .name = "mzk-w04nu:green:ap", -+ .gpio = MZK_W04NU_GPIO_LED_AP, -+ .active_low = 1, -+ }, { -+ .name = "mzk-w04nu:green:router", -+ .gpio = MZK_W04NU_GPIO_LED_ROUTER, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_button mzk_w04nu_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = MZK_W04NU_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "wps", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = MZK_W04NU_GPIO_BTN_WPS, -+ .active_low = 1, -+ }, { -+ .desc = "aprouter", -+ .type = EV_KEY, -+ .code = BTN_2, -+ .threshold = 3, -+ .gpio = MZK_W04NU_GPIO_BTN_APROUTER, -+ .active_low = 0, -+ } -+}; -+ -+#define MZK_W04NU_WAN_PHYMASK BIT(4) -+#define MZK_W04NU_MDIO_MASK (~MZK_W04NU_WAN_PHYMASK) -+ -+static void __init mzk_w04nu_setup(void) -+{ -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ -+ ar71xx_set_mac_base(eeprom); -+ -+ ar71xx_add_device_mdio(MZK_W04NU_MDIO_MASK); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ ar71xx_eth0_data.has_ar8216 = 1; -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.phy_mask = MZK_W04NU_WAN_PHYMASK; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_m25p80(&mzk_w04nu_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(mzk_w04nu_leds_gpio), -+ mzk_w04nu_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, MZK_W04NU_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(mzk_w04nu_gpio_buttons), -+ mzk_w04nu_gpio_buttons); -+ ar71xx_add_device_usb(); -+ -+ ar913x_add_device_wmac(eeprom, NULL); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_MZK_W04NU, "MZK-W04NU", "Planex MZK-W04NU", -+ mzk_w04nu_setup); -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/mach-mzk-w300nh.c linux-2.6.37/arch/mips/ar71xx/mach-mzk-w300nh.c ---- linux-2.6.37.orig/arch/mips/ar71xx/mach-mzk-w300nh.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/mach-mzk-w300nh.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,158 @@ -+/* -+ * Planex MZK-W300NH board support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ar913x-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+ -+#define MZK_W300NH_GPIO_LED_STATUS 1 -+#define MZK_W300NH_GPIO_LED_WPS 3 -+#define MZK_W300NH_GPIO_LED_WLAN 6 -+#define MZK_W300NH_GPIO_LED_AP 15 -+#define MZK_W300NH_GPIO_LED_ROUTER 16 -+ -+#define MZK_W300NH_GPIO_BTN_APROUTER 5 -+#define MZK_W300NH_GPIO_BTN_WPS 12 -+#define MZK_W300NH_GPIO_BTN_RESET 21 -+ -+#define MZK_W04NU_BUTTONS_POLL_INTERVAL 20 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition mzk_w300nh_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x040000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "u-boot-env", -+ .offset = 0x040000, -+ .size = 0x010000, -+ } , { -+ .name = "kernel", -+ .offset = 0x050000, -+ .size = 0x160000, -+ } , { -+ .name = "rootfs", -+ .offset = 0x1b0000, -+ .size = 0x630000, -+ } , { -+ .name = "art", -+ .offset = 0x7e0000, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "firmware", -+ .offset = 0x050000, -+ .size = 0x790000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data mzk_w300nh_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = mzk_w300nh_partitions, -+ .nr_parts = ARRAY_SIZE(mzk_w300nh_partitions), -+#endif -+}; -+ -+static struct gpio_led mzk_w300nh_leds_gpio[] __initdata = { -+ { -+ .name = "mzk-w300nh:green:status", -+ .gpio = MZK_W300NH_GPIO_LED_STATUS, -+ .active_low = 1, -+ }, { -+ .name = "mzk-w300nh:blue:wps", -+ .gpio = MZK_W300NH_GPIO_LED_WPS, -+ .active_low = 1, -+ }, { -+ .name = "mzk-w300nh:green:wlan", -+ .gpio = MZK_W300NH_GPIO_LED_WLAN, -+ .active_low = 1, -+ }, { -+ .name = "mzk-w300nh:green:ap", -+ .gpio = MZK_W300NH_GPIO_LED_AP, -+ .active_low = 1, -+ }, { -+ .name = "mzk-w300nh:green:router", -+ .gpio = MZK_W300NH_GPIO_LED_ROUTER, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_button mzk_w300nh_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = MZK_W300NH_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "wps", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = MZK_W300NH_GPIO_BTN_WPS, -+ .active_low = 1, -+ }, { -+ .desc = "aprouter", -+ .type = EV_KEY, -+ .code = BTN_2, -+ .threshold = 3, -+ .gpio = MZK_W300NH_GPIO_BTN_APROUTER, -+ .active_low = 0, -+ } -+}; -+ -+#define MZK_W300NH_WAN_PHYMASK BIT(4) -+#define MZK_W300NH_MDIO_MASK (~MZK_W300NH_WAN_PHYMASK) -+ -+static void __init mzk_w300nh_setup(void) -+{ -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ -+ ar71xx_set_mac_base(eeprom); -+ -+ ar71xx_add_device_mdio(MZK_W300NH_MDIO_MASK); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ ar71xx_eth0_data.has_ar8216 = 1; -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.phy_mask = MZK_W300NH_WAN_PHYMASK; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_m25p80(&mzk_w300nh_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(mzk_w300nh_leds_gpio), -+ mzk_w300nh_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, MZK_W04NU_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(mzk_w300nh_gpio_buttons), -+ mzk_w300nh_gpio_buttons); -+ ar913x_add_device_wmac(eeprom, NULL); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_MZK_W300NH, "MZK-W300NH", "Planex MZK-W300NH", -+ mzk_w300nh_setup); -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/mach-nbg460n.c linux-2.6.37/arch/mips/ar71xx/mach-nbg460n.c ---- linux-2.6.37.orig/arch/mips/ar71xx/mach-nbg460n.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/mach-nbg460n.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,222 @@ -+/* -+ * Zyxel NBG 460N/550N/550NH board support -+ * -+ * Copyright (C) 2010 Michael Kurz -+ * -+ * based on mach-tl-wr1043nd.c -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ar913x-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+ -+/* LEDs */ -+#define NBG460N_GPIO_LED_WPS 3 -+#define NBG460N_GPIO_LED_WAN 6 -+#define NBG460N_GPIO_LED_POWER 14 -+#define NBG460N_GPIO_LED_WLAN 15 -+ -+/* Buttons */ -+#define NBG460N_GPIO_BTN_WPS 12 -+#define NBG460N_GPIO_BTN_RESET 21 -+#define NBG460N_BUTTONS_POLL_INTERVAL 20 -+ -+/* RTC chip PCF8563 I2C interface */ -+#define NBG460N_GPIO_PCF8563_SDA 8 -+#define NBG460N_GPIO_PCF8563_SCK 7 -+ -+/* Switch configuration I2C interface */ -+#define NBG460N_GPIO_RTL8366_SDA 16 -+#define NBG460N_GPIO_RTL8366_SCK 18 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition nbg460n_partitions[] = { -+ { -+ .name = "Bootbase", -+ .offset = 0, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "U-Boot Config", -+ .offset = 0x010000, -+ .size = 0x030000, -+ } , { -+ .name = "U-Boot", -+ .offset = 0x040000, -+ .size = 0x030000, -+ } , { -+ .name = "linux", -+ .offset = 0x070000, -+ .size = 0x0e0000, -+ } , { -+ .name = "rootfs", -+ .offset = 0x150000, -+ .size = 0x2a0000, -+ } , { -+ .name = "CalibData", -+ .offset = 0x3f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "firmware", -+ .offset = 0x070000, -+ .size = 0x380000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data nbg460n_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = nbg460n_partitions, -+ .nr_parts = ARRAY_SIZE(nbg460n_partitions), -+#endif -+}; -+ -+static struct gpio_led nbg460n_leds_gpio[] __initdata = { -+ { -+ .name = "nbg460n:green:power", -+ .gpio = NBG460N_GPIO_LED_POWER, -+ .active_low = 0, -+ .default_trigger = "default-on", -+ }, { -+ .name = "nbg460n:green:wps", -+ .gpio = NBG460N_GPIO_LED_WPS, -+ .active_low = 0, -+ }, { -+ .name = "nbg460n:green:wlan", -+ .gpio = NBG460N_GPIO_LED_WLAN, -+ .active_low = 0, -+ }, { -+ /* Not really for controlling the LED, -+ when set low the LED blinks uncontrollable */ -+ .name = "nbg460n:green:wan", -+ .gpio = NBG460N_GPIO_LED_WAN, -+ .active_low = 0, -+ } -+}; -+ -+static struct gpio_button nbg460n_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = NBG460N_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "wps", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = NBG460N_GPIO_BTN_WPS, -+ .active_low = 1, -+ } -+}; -+ -+static struct i2c_gpio_platform_data nbg460n_i2c_device_platdata = { -+ .sda_pin = NBG460N_GPIO_PCF8563_SDA, -+ .scl_pin = NBG460N_GPIO_PCF8563_SCK, -+ .udelay = 10, -+}; -+ -+static struct platform_device nbg460n_i2c_device = { -+ .name = "i2c-gpio", -+ .id = -1, -+ .num_resources = 0, -+ .resource = NULL, -+ .dev = { -+ .platform_data = &nbg460n_i2c_device_platdata, -+ }, -+}; -+ -+static struct i2c_board_info nbg460n_i2c_devs[] __initdata = { -+ { -+ I2C_BOARD_INFO("pcf8563", 0x51), -+ }, -+}; -+ -+static void __devinit nbg460n_i2c_init(void) -+{ -+ /* The gpio interface */ -+ platform_device_register(&nbg460n_i2c_device); -+ /* I2C devices */ -+ i2c_register_board_info(0, nbg460n_i2c_devs, -+ ARRAY_SIZE(nbg460n_i2c_devs)); -+} -+ -+ -+static struct rtl8366s_platform_data nbg460n_rtl8366s_data = { -+ .gpio_sda = NBG460N_GPIO_RTL8366_SDA, -+ .gpio_sck = NBG460N_GPIO_RTL8366_SCK, -+}; -+ -+static struct platform_device nbg460n_rtl8366s_device = { -+ .name = RTL8366S_DRIVER_NAME, -+ .id = -1, -+ .dev = { -+ .platform_data = &nbg460n_rtl8366s_data, -+ } -+}; -+ -+static void __init nbg460n_setup(void) -+{ -+ /* end of bootloader sector contains mac address*/ -+ u8 *mac = (u8 *) KSEG1ADDR(0x1fc0fff8); -+ /* last sector contains wlan calib data */ -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ -+ ar71xx_set_mac_base(mac); -+ -+ /* LAN Port */ -+ ar71xx_eth0_data.mii_bus_dev = &nbg460n_rtl8366s_device.dev; -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth0_data.speed = SPEED_1000; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ -+ /* WAN Port */ -+ ar71xx_eth1_data.mii_bus_dev = &nbg460n_rtl8366s_device.dev; -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth1_data.phy_mask = 0x10; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ /* register the switch phy */ -+ platform_device_register(&nbg460n_rtl8366s_device); -+ -+ /* register flash */ -+ ar71xx_add_device_m25p80(&nbg460n_flash_data); -+ -+ ar913x_add_device_wmac(eeprom, mac); -+ -+ /* register RTC chip */ -+ nbg460n_i2c_init(); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(nbg460n_leds_gpio), -+ nbg460n_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, NBG460N_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(nbg460n_gpio_buttons), -+ nbg460n_gpio_buttons); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_NBG460N, "NBG460N", "Zyxel NBG460N/550N/550NH", nbg460n_setup); -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/mach-pb42.c linux-2.6.37/arch/mips/ar71xx/mach-pb42.c ---- linux-2.6.37.orig/arch/mips/ar71xx/mach-pb42.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/mach-pb42.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,71 @@ -+/* -+ * Atheros PB42 board support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-gpio-buttons.h" -+#include "dev-pb42-pci.h" -+#include "dev-usb.h" -+ -+#define PB42_BUTTONS_POLL_INTERVAL 20 -+ -+#define PB42_GPIO_BTN_SW4 8 -+#define PB42_GPIO_BTN_SW5 3 -+ -+static struct gpio_button pb42_gpio_buttons[] __initdata = { -+ { -+ .desc = "sw4", -+ .type = EV_KEY, -+ .code = BTN_0, -+ .threshold = 3, -+ .gpio = PB42_GPIO_BTN_SW4, -+ .active_low = 1, -+ } , { -+ .desc = "sw5", -+ .type = EV_KEY, -+ .code = BTN_1, -+ .threshold = 3, -+ .gpio = PB42_GPIO_BTN_SW5, -+ .active_low = 1, -+ } -+}; -+ -+#define PB42_WAN_PHYMASK BIT(20) -+#define PB42_LAN_PHYMASK (BIT(16) | BIT(17) | BIT(18) | BIT(19)) -+#define PB42_MDIO_PHYMASK (PB42_LAN_PHYMASK | PB42_WAN_PHYMASK) -+ -+static void __init pb42_init(void) -+{ -+ ar71xx_add_device_m25p80(NULL); -+ -+ ar71xx_add_device_mdio(~PB42_MDIO_PHYMASK); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; -+ ar71xx_eth0_data.phy_mask = PB42_WAN_PHYMASK; -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.speed = SPEED_100; -+ ar71xx_eth1_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_gpio_buttons(-1, PB42_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(pb42_gpio_buttons), -+ pb42_gpio_buttons); -+ -+ pb42_pci_init(); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_PB42, "PB42", "Atheros PB42", pb42_init); -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/mach-pb44.c linux-2.6.37/arch/mips/ar71xx/mach-pb44.c ---- linux-2.6.37.orig/arch/mips/ar71xx/mach-pb44.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/mach-pb44.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,207 @@ -+/* -+ * Atheros PB44 board support -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-pb42-pci.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-usb.h" -+ -+#define PB44_PCF8757_VSC7395_CS 0 -+#define PB44_PCF8757_STEREO_CS 1 -+#define PB44_PCF8757_SLIC_CS0 2 -+#define PB44_PCF8757_SLIC_TEST 3 -+#define PB44_PCF8757_SLIC_INT0 4 -+#define PB44_PCF8757_SLIC_INT1 5 -+#define PB44_PCF8757_SW_RESET 6 -+#define PB44_PCF8757_SW_JUMP 8 -+#define PB44_PCF8757_LED_JUMP1 9 -+#define PB44_PCF8757_LED_JUMP2 10 -+#define PB44_PCF8757_TP24 11 -+#define PB44_PCF8757_TP25 12 -+#define PB44_PCF8757_TP26 13 -+#define PB44_PCF8757_TP27 14 -+#define PB44_PCF8757_TP28 15 -+ -+#define PB44_GPIO_I2C_SCL 0 -+#define PB44_GPIO_I2C_SDA 1 -+ -+#define PB44_GPIO_EXP_BASE 16 -+#define PB44_GPIO_VSC7395_CS (PB44_GPIO_EXP_BASE + PB44_PCF8757_VSC7395_CS) -+#define PB44_GPIO_SW_RESET (PB44_GPIO_EXP_BASE + PB44_PCF8757_SW_RESET) -+#define PB44_GPIO_SW_JUMP (PB44_GPIO_EXP_BASE + PB44_PCF8757_SW_JUMP) -+#define PB44_GPIO_LED_JUMP1 (PB44_GPIO_EXP_BASE + PB44_PCF8757_LED_JUMP1) -+#define PB44_GPIO_LED_JUMP2 (PB44_GPIO_EXP_BASE + PB44_PCF8757_LED_JUMP2) -+ -+static struct i2c_gpio_platform_data pb44_i2c_gpio_data = { -+ .sda_pin = PB44_GPIO_I2C_SDA, -+ .scl_pin = PB44_GPIO_I2C_SCL, -+}; -+ -+static struct platform_device pb44_i2c_gpio_device = { -+ .name = "i2c-gpio", -+ .id = 0, -+ .dev = { -+ .platform_data = &pb44_i2c_gpio_data, -+ } -+}; -+ -+static struct pcf857x_platform_data pb44_pcf857x_data = { -+ .gpio_base = PB44_GPIO_EXP_BASE, -+}; -+ -+static struct i2c_board_info pb44_i2c_board_info[] __initdata = { -+ { -+ I2C_BOARD_INFO("pcf8575", 0x20), -+ .platform_data = &pb44_pcf857x_data, -+ }, -+}; -+ -+static struct gpio_led pb44_leds_gpio[] __initdata = { -+ { -+ .name = "pb44:amber:jump1", -+ .gpio = PB44_GPIO_LED_JUMP1, -+ .active_low = 1, -+ }, { -+ .name = "pb44:green:jump2", -+ .gpio = PB44_GPIO_LED_JUMP2, -+ .active_low = 1, -+ }, -+}; -+ -+static struct gpio_button pb44_gpio_buttons[] __initdata = { -+ { -+ .desc = "soft_reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = PB44_GPIO_SW_RESET, -+ .active_low = 1, -+ } , { -+ .desc = "jumpstart", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = PB44_GPIO_SW_JUMP, -+ .active_low = 1, -+ } -+}; -+ -+static void pb44_vsc7395_reset(void) -+{ -+ ar71xx_device_stop(RESET_MODULE_GE1_PHY); -+ udelay(10); -+ ar71xx_device_start(RESET_MODULE_GE1_PHY); -+ mdelay(50); -+} -+ -+static struct vsc7385_platform_data pb44_vsc7395_data = { -+ .reset = pb44_vsc7395_reset, -+ .ucode_name = "vsc7395_ucode_pb44.bin", -+ .mac_cfg = { -+ .tx_ipg = 6, -+ .bit2 = 1, -+ .clk_sel = 0, -+ }, -+}; -+ -+static struct spi_board_info pb44_spi_info[] = { -+ { -+ .bus_num = 0, -+ .chip_select = 0, -+ .max_speed_hz = 25000000, -+ .modalias = "m25p80", -+ }, { -+ .bus_num = 0, -+ .chip_select = 1, -+ .max_speed_hz = 25000000, -+ .modalias = "spi-vsc7385", -+ .platform_data = &pb44_vsc7395_data, -+ .controller_data = (void *) PB44_GPIO_VSC7395_CS, -+ }, -+}; -+ -+static struct resource pb44_spi_resources[] = { -+ [0] = { -+ .start = AR71XX_SPI_BASE, -+ .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+}; -+ -+static struct ar71xx_spi_platform_data pb44_spi_data = { -+ .bus_num = 0, -+ .num_chipselect = 2, -+}; -+ -+static struct platform_device pb44_spi_device = { -+ .name = "pb44-spi", -+ .id = -1, -+ .resource = pb44_spi_resources, -+ .num_resources = ARRAY_SIZE(pb44_spi_resources), -+ .dev = { -+ .platform_data = &pb44_spi_data, -+ }, -+}; -+ -+#define PB44_WAN_PHYMASK BIT(0) -+#define PB44_LAN_PHYMASK 0 -+#define PB44_MDIO_PHYMASK (PB44_LAN_PHYMASK | PB44_WAN_PHYMASK) -+ -+static void __init pb44_init(void) -+{ -+ ar71xx_add_device_mdio(~PB44_MDIO_PHYMASK); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth0_data.phy_mask = PB44_WAN_PHYMASK; -+ -+ ar71xx_add_device_eth(0); -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth1_data.speed = SPEED_1000; -+ ar71xx_eth1_data.duplex = DUPLEX_FULL; -+ ar71xx_eth1_pll_data.pll_1000 = 0x110000; -+ -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_usb(); -+ -+ pb42_pci_init(); -+ -+ i2c_register_board_info(0, pb44_i2c_board_info, -+ ARRAY_SIZE(pb44_i2c_board_info)); -+ -+ platform_device_register(&pb44_i2c_gpio_device); -+ -+ spi_register_board_info(pb44_spi_info, ARRAY_SIZE(pb44_spi_info)); -+ platform_device_register(&pb44_spi_device); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(pb44_leds_gpio), -+ pb44_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, 20, ARRAY_SIZE(pb44_gpio_buttons), -+ pb44_gpio_buttons); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_PB44, "PB44", "Atheros PB44", pb44_init); -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/mach-pb92.c linux-2.6.37/arch/mips/ar71xx/mach-pb92.c ---- linux-2.6.37.orig/arch/mips/ar71xx/mach-pb92.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/mach-pb92.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,109 @@ -+/* -+ * Atheros PB92 board support -+ * -+ * Copyright (C) 2010 Felix Fietkau -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-gpio-buttons.h" -+#include "dev-pb9x-pci.h" -+#include "dev-usb.h" -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition pb92_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x040000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "u-boot-env", -+ .offset = 0x040000, -+ .size = 0x010000, -+ } , { -+ .name = "rootfs", -+ .offset = 0x050000, -+ .size = 0x2b0000, -+ } , { -+ .name = "uImage", -+ .offset = 0x300000, -+ .size = 0x0e0000, -+ } , { -+ .name = "ART", -+ .offset = 0x3e0000, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data pb92_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = pb92_partitions, -+ .nr_parts = ARRAY_SIZE(pb92_partitions), -+#endif -+}; -+ -+ -+#define PB92_BUTTONS_POLL_INTERVAL 20 -+ -+#define PB92_GPIO_BTN_SW4 8 -+#define PB92_GPIO_BTN_SW5 3 -+ -+static struct gpio_button pb92_gpio_buttons[] __initdata = { -+ { -+ .desc = "sw4", -+ .type = EV_KEY, -+ .code = BTN_0, -+ .threshold = 3, -+ .gpio = PB92_GPIO_BTN_SW4, -+ .active_low = 1, -+ } , { -+ .desc = "sw5", -+ .type = EV_KEY, -+ .code = BTN_1, -+ .threshold = 3, -+ .gpio = PB92_GPIO_BTN_SW5, -+ .active_low = 1, -+ } -+}; -+ -+static void __init pb92_init(void) -+{ -+ u8 *mac = (u8 *) KSEG1ADDR(0x1fff0000); -+ -+ ar71xx_set_mac_base(mac); -+ ar71xx_add_device_m25p80(&pb92_flash_data); -+ -+ ar71xx_add_device_mdio(~0); -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.speed = SPEED_1000; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.speed = SPEED_1000; -+ ar71xx_eth1_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_gpio_buttons(-1, PB92_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(pb92_gpio_buttons), -+ pb92_gpio_buttons); -+ -+ pb9x_pci_init(); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_PB92, "PB92", "Atheros PB92", pb92_init); -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/mach-rb4xx.c linux-2.6.37/arch/mips/ar71xx/mach-rb4xx.c ---- linux-2.6.37.orig/arch/mips/ar71xx/mach-rb4xx.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/mach-rb4xx.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,290 @@ -+/* -+ * MikroTik RouterBOARD 4xx series support -+ * -+ * Copyright (C) 2008 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-usb.h" -+ -+#define RB4XX_GPIO_USER_LED 4 -+#define RB4XX_GPIO_RESET_SWITCH 7 -+ -+#define RB4XX_BUTTONS_POLL_INTERVAL 20 -+ -+static struct gpio_led rb4xx_leds_gpio[] __initdata = { -+ { -+ .name = "rb4xx:yellow:user", -+ .gpio = RB4XX_GPIO_USER_LED, -+ .active_low = 0, -+ }, -+}; -+ -+static struct gpio_button rb4xx_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset_switch", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = RB4XX_GPIO_RESET_SWITCH, -+ .active_low = 1, -+ } -+}; -+ -+static struct platform_device rb4xx_nand_device = { -+ .name = "rb4xx-nand", -+ .id = -1, -+}; -+ -+static struct ar71xx_pci_irq rb4xx_pci_irqs[] __initdata = { -+ { -+ .slot = 0, -+ .pin = 1, -+ .irq = AR71XX_PCI_IRQ_DEV2, -+ }, { -+ .slot = 1, -+ .pin = 1, -+ .irq = AR71XX_PCI_IRQ_DEV0, -+ }, { -+ .slot = 1, -+ .pin = 2, -+ .irq = AR71XX_PCI_IRQ_DEV1, -+ }, { -+ .slot = 2, -+ .pin = 1, -+ .irq = AR71XX_PCI_IRQ_DEV1, -+ }, { -+ .slot = 3, -+ .pin = 1, -+ .irq = AR71XX_PCI_IRQ_DEV2, -+ } -+}; -+ -+#if 0 -+/* -+ * SPI device support is experimental -+ */ -+static struct flash_platform_data rb4xx_flash_data = { -+ .type = "pm25lv512", -+}; -+ -+static struct spi_board_info rb4xx_spi_info[] = { -+ { -+ .bus_num = 0, -+ .chip_select = 0, -+ .max_speed_hz = 25000000, -+ .modalias = "m25p80", -+ .platform_data = &rb4xx_flash_data, -+ } -+}; -+ -+static struct mmc_spi_platform_data rb433_mmc_data = { -+ .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, -+}; -+ -+static struct spi_board_info rb433_spi_info[] = { -+ { -+ .bus_num = 0, -+ .chip_select = 0, -+ .max_speed_hz = 25000000, -+ .modalias = "m25p80", -+ .platform_data = &rb433_flash_data, -+ }, { -+ .bus_num = 0, -+ .chip_select = 2, -+ .max_speed_hz = 25000000, -+ .modalias = "mmc_spi", -+ .platform_data = &rb433_mmc_data, -+ } -+}; -+ -+static u32 rb433_spi_get_ioc_base(u8 chip_select, int cs_high, int is_on) -+{ -+ u32 ret; -+ -+ if (is_on == AR71XX_SPI_CS_INACTIVE) { -+ ret = SPI_IOC_CS0 | SPI_IOC_CS1; -+ } else { -+ if (cs_high) { -+ ret = SPI_IOC_CS0 | SPI_IOC_CS1; -+ } else { -+ if ((chip_select ^ 2) == 0) -+ ret = SPI_IOC_CS1 ^ (SPI_IOC_CS0 | SPI_IOC_CS1); -+ else -+ ret = SPI_IOC_CS0 ^ (SPI_IOC_CS0 | SPI_IOC_CS1); -+ } -+ } -+ -+ return ret; -+} -+ -+struct ar71xx_spi_platform_data rb433_spi_data = { -+ .bus_num = 0, -+ .num_chipselect = 3, -+ .get_ioc_base = rb433_spi_get_ioc_base, -+}; -+ -+static void rb4xx_add_device_spi(void) -+{ -+ ar71xx_add_device_spi(NULL, rb4xx_spi_info, ARRAY_SIZE(rb4xx_spi_info)); -+} -+ -+static void rb433_add_device_spi(void) -+{ -+ ar71xx_add_device_spi(&rb433_spi_data, rb433_spi_info, -+ ARRAY_SIZE(rb433_spi_info)); -+} -+#else -+static inline void rb4xx_add_device_spi(void) {} -+static inline void rb433_add_device_spi(void) {} -+#endif -+ -+static void __init rb4xx_generic_setup(void) -+{ -+ ar71xx_gpio_function_enable(AR71XX_GPIO_FUNC_SPI_CS1_EN | -+ AR71XX_GPIO_FUNC_SPI_CS2_EN); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(rb4xx_leds_gpio), -+ rb4xx_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, RB4XX_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(rb4xx_gpio_buttons), -+ rb4xx_gpio_buttons); -+ -+ platform_device_register(&rb4xx_nand_device); -+} -+ -+static void __init rb411_setup(void) -+{ -+ rb4xx_generic_setup(); -+ rb4xx_add_device_spi(); -+ -+ ar71xx_add_device_mdio(0xfffffffc); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; -+ ar71xx_eth0_data.phy_mask = 0x00000003; -+ -+ ar71xx_add_device_eth(0); -+ -+ ar71xx_pci_init(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_RB_411, "411", "MikroTik RouterBOARD 411/A/AH", -+ rb411_setup); -+ -+static void __init rb411u_setup(void) -+{ -+ rb411_setup(); -+ ar71xx_add_device_usb(); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_RB_411U, "411U", "MikroTik RouterBOARD 411U", -+ rb411u_setup); -+ -+static void __init rb433_setup(void) -+{ -+ rb4xx_generic_setup(); -+ rb433_add_device_spi(); -+ -+ ar71xx_add_device_mdio(0xffffffe9); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.phy_mask = 0x00000010; -+ -+ ar71xx_add_device_eth(1); -+ ar71xx_add_device_eth(0); -+ -+ ar71xx_pci_init(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_RB_433, "433", "MikroTik RouterBOARD 433/AH", -+ rb433_setup); -+ -+static void __init rb433u_setup(void) -+{ -+ rb433_setup(); -+ ar71xx_add_device_usb(); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_RB_433U, "433U", "MikroTik RouterBOARD 433UAH", -+ rb433u_setup); -+ -+static void __init rb450_generic_setup(int gige) -+{ -+ rb4xx_generic_setup(); -+ rb4xx_add_device_spi(); -+ -+ ar71xx_add_device_mdio(0xffffffe0); -+ -+ ar71xx_eth0_data.phy_if_mode = (gige) ? PHY_INTERFACE_MODE_RGMII : PHY_INTERFACE_MODE_MII; -+ ar71xx_eth0_data.phy_mask = (gige) ? (1 << 0) : 0; -+ ar71xx_eth0_data.speed = (gige) ? SPEED_1000 : SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_eth1_data.phy_if_mode = (gige) ? PHY_INTERFACE_MODE_RGMII : PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.phy_mask = 0x00000010; -+ -+ ar71xx_add_device_eth(1); -+ ar71xx_add_device_eth(0); -+} -+ -+static void __init rb450_setup(void) -+{ -+ rb450_generic_setup(0); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_RB_450, "450", "MikroTik RouterBOARD 450", -+ rb450_setup); -+ -+static void __init rb450g_setup(void) -+{ -+ rb450_generic_setup(1); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_RB_450G, "450G", "MikroTik RouterBOARD 450G", -+ rb450g_setup); -+ -+static void __init rb493_setup(void) -+{ -+ rb4xx_generic_setup(); -+ rb4xx_add_device_spi(); -+ -+ ar71xx_add_device_mdio(0x3fffff00); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.phy_mask = 0x00000001; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_pci_init(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_RB_493, "493", "MikroTik RouterBOARD 493/AH", -+ rb493_setup); -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/mach-rb750.c linux-2.6.37/arch/mips/ar71xx/mach-rb750.c ---- linux-2.6.37.orig/arch/mips/ar71xx/mach-rb750.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/mach-rb750.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,133 @@ -+/* -+ * MikroTik RouterBOARD 750 support -+ * -+ * Copyright (C) 2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+ -+#include "machtype.h" -+#include "dev-ap91-eth.h" -+ -+static struct rb750_led_data rb750_leds[] = { -+ { -+ .name = "rb750:green:act", -+ .mask = RB750_LED_ACT, -+ .active_low = 1, -+ }, { -+ .name = "rb750:green:port1", -+ .mask = RB750_LED_PORT5, -+ .active_low = 1, -+ }, { -+ .name = "rb750:green:port2", -+ .mask = RB750_LED_PORT4, -+ .active_low = 1, -+ }, { -+ .name = "rb750:green:port3", -+ .mask = RB750_LED_PORT3, -+ .active_low = 1, -+ }, { -+ .name = "rb750:green:port4", -+ .mask = RB750_LED_PORT2, -+ .active_low = 1, -+ }, { -+ .name = "rb750:green:port5", -+ .mask = RB750_LED_PORT1, -+ .active_low = 1, -+ } -+}; -+ -+static struct rb750_led_platform_data rb750_leds_data = { -+ .num_leds = ARRAY_SIZE(rb750_leds), -+ .leds = rb750_leds, -+}; -+ -+static struct platform_device rb750_leds_device = { -+ .name = "leds-rb750", -+ .dev = { -+ .platform_data = &rb750_leds_data, -+ } -+}; -+ -+static const char *rb750_port_names[AP91_ETH_NUM_PORT_NAMES] __initdata = { -+ "port5", -+ "port4", -+ "port3", -+ "port2", -+}; -+ -+static struct platform_device rb750_nand_device = { -+ .name = "rb750-nand", -+ .id = -1, -+}; -+ -+int rb750_latch_change(u32 mask_clr, u32 mask_set) -+{ -+ static DEFINE_SPINLOCK(lock); -+ static u32 latch_set = RB750_LED_BITS | RB750_LVC573_LE; -+ static u32 latch_oe; -+ static u32 latch_clr; -+ unsigned long flags; -+ u32 t; -+ int ret = 0; -+ -+ spin_lock_irqsave(&lock, flags); -+ -+ if ((mask_clr & BIT(31)) != 0 && -+ (latch_set & RB750_LVC573_LE) == 0) { -+ goto unlock; -+ } -+ -+ latch_set = (latch_set | mask_set) & ~mask_clr; -+ latch_clr = (latch_clr | mask_clr) & ~mask_set; -+ -+ if (latch_oe == 0) -+ latch_oe = __raw_readl(ar71xx_gpio_base + GPIO_REG_OE); -+ -+ if (likely(latch_set & RB750_LVC573_LE)) { -+ void __iomem *base = ar71xx_gpio_base; -+ -+ t = __raw_readl(base + GPIO_REG_OE); -+ t |= mask_clr | latch_oe | mask_set; -+ -+ __raw_writel(t, base + GPIO_REG_OE); -+ __raw_writel(latch_clr, base + GPIO_REG_CLEAR); -+ __raw_writel(latch_set, base + GPIO_REG_SET); -+ } else if (mask_clr & RB750_LVC573_LE) { -+ void __iomem *base = ar71xx_gpio_base; -+ -+ latch_oe = __raw_readl(base + GPIO_REG_OE); -+ __raw_writel(RB750_LVC573_LE, base + GPIO_REG_CLEAR); -+ /* flush write */ -+ __raw_readl(base + GPIO_REG_CLEAR); -+ } -+ -+ ret = 1; -+ -+ unlock: -+ spin_unlock_irqrestore(&lock, flags); -+ return ret; -+} -+EXPORT_SYMBOL_GPL(rb750_latch_change); -+ -+static void __init rb750_setup(void) -+{ -+ ar71xx_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN | -+ AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN | -+ AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN | -+ AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN | -+ AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN); -+ -+ ap91_eth_init(NULL, rb750_port_names); -+ platform_device_register(&rb750_leds_device); -+ platform_device_register(&rb750_nand_device); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_RB_750, "750i", "MikroTik RouterBOARD 750", -+ rb750_setup); -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/mach-tew-632brp.c linux-2.6.37/arch/mips/ar71xx/mach-tew-632brp.c ---- linux-2.6.37.orig/arch/mips/ar71xx/mach-tew-632brp.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/mach-tew-632brp.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,149 @@ -+/* -+ * TrendNET TEW-632BRP board support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ar913x-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "nvram.h" -+ -+#define TEW_632BRP_GPIO_LED_STATUS 1 -+#define TEW_632BRP_GPIO_LED_WPS 3 -+#define TEW_632BRP_GPIO_LED_WLAN 6 -+#define TEW_632BRP_GPIO_BTN_WPS 12 -+#define TEW_632BRP_GPIO_BTN_RESET 21 -+ -+#define TEW_632BRP_BUTTONS_POLL_INTERVAL 20 -+ -+#define TEW_632BRP_CONFIG_ADDR 0x1f020000 -+#define TEW_632BRP_CONFIG_SIZE 0x10000 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition tew_632brp_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "config", -+ .offset = 0x020000, -+ .size = 0x010000, -+ } , { -+ .name = "kernel", -+ .offset = 0x030000, -+ .size = 0x0d0000, -+ } , { -+ .name = "rootfs", -+ .offset = 0x100000, -+ .size = 0x2f0000, -+ } , { -+ .name = "art", -+ .offset = 0x3f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "firmware", -+ .offset = 0x030000, -+ .size = 0x3c0000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data tew_632brp_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = tew_632brp_partitions, -+ .nr_parts = ARRAY_SIZE(tew_632brp_partitions), -+#endif -+}; -+ -+static struct gpio_led tew_632brp_leds_gpio[] __initdata = { -+ { -+ .name = "tew-632brp:green:status", -+ .gpio = TEW_632BRP_GPIO_LED_STATUS, -+ .active_low = 1, -+ }, { -+ .name = "tew-632brp:blue:wps", -+ .gpio = TEW_632BRP_GPIO_LED_WPS, -+ .active_low = 1, -+ }, { -+ .name = "tew-632brp:green:wlan", -+ .gpio = TEW_632BRP_GPIO_LED_WLAN, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_button tew_632brp_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = TEW_632BRP_GPIO_BTN_RESET, -+ }, { -+ .desc = "wps", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = TEW_632BRP_GPIO_BTN_WPS, -+ } -+}; -+ -+#define TEW_632BRP_LAN_PHYMASK BIT(0) -+#define TEW_632BRP_WAN_PHYMASK BIT(4) -+#define TEW_632BRP_MDIO_MASK (~(TEW_632BRP_LAN_PHYMASK | \ -+ TEW_632BRP_WAN_PHYMASK)) -+ -+static void __init tew_632brp_setup(void) -+{ -+ const char *config = (char *) KSEG1ADDR(TEW_632BRP_CONFIG_ADDR); -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ u8 mac[6]; -+ u8 *wlan_mac = NULL; -+ -+ if (nvram_parse_mac_addr(config, TEW_632BRP_CONFIG_SIZE, -+ "lan_mac=", mac) == 0) { -+ ar71xx_set_mac_base(mac); -+ wlan_mac = mac; -+ } -+ -+ ar71xx_add_device_mdio(TEW_632BRP_MDIO_MASK); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.phy_mask = TEW_632BRP_LAN_PHYMASK; -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.phy_mask = TEW_632BRP_WAN_PHYMASK; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_m25p80(&tew_632brp_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(tew_632brp_leds_gpio), -+ tew_632brp_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, TEW_632BRP_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(tew_632brp_gpio_buttons), -+ tew_632brp_gpio_buttons); -+ -+ ar913x_add_device_wmac(eeprom, wlan_mac); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_TEW_632BRP, "TEW-632BRP", "TRENDnet TEW-632BRP", -+ tew_632brp_setup); -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/mach-tl-wr1043nd.c linux-2.6.37/arch/mips/ar71xx/mach-tl-wr1043nd.c ---- linux-2.6.37.orig/arch/mips/ar71xx/mach-tl-wr1043nd.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/mach-tl-wr1043nd.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,156 @@ -+/* -+ * TP-LINK TL-WR1043ND board support -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ar913x-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-usb.h" -+ -+#define TL_WR1043ND_GPIO_LED_USB 1 -+#define TL_WR1043ND_GPIO_LED_SYSTEM 2 -+#define TL_WR1043ND_GPIO_LED_QSS 5 -+#define TL_WR1043ND_GPIO_LED_WLAN 9 -+ -+#define TL_WR1043ND_GPIO_BTN_RESET 3 -+#define TL_WR1043ND_GPIO_BTN_QSS 7 -+ -+#define TL_WR1043ND_GPIO_RTL8366_SDA 18 -+#define TL_WR1043ND_GPIO_RTL8366_SCK 19 -+ -+#define TL_WR1043ND_BUTTONS_POLL_INTERVAL 20 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition tl_wr1043nd_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "kernel", -+ .offset = 0x020000, -+ .size = 0x140000, -+ } , { -+ .name = "rootfs", -+ .offset = 0x160000, -+ .size = 0x690000, -+ } , { -+ .name = "art", -+ .offset = 0x7f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "firmware", -+ .offset = 0x020000, -+ .size = 0x7d0000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data tl_wr1043nd_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = tl_wr1043nd_partitions, -+ .nr_parts = ARRAY_SIZE(tl_wr1043nd_partitions), -+#endif -+}; -+ -+static struct gpio_led tl_wr1043nd_leds_gpio[] __initdata = { -+ { -+ .name = "tl-wr1043nd:green:usb", -+ .gpio = TL_WR1043ND_GPIO_LED_USB, -+ .active_low = 1, -+ }, { -+ .name = "tl-wr1043nd:green:system", -+ .gpio = TL_WR1043ND_GPIO_LED_SYSTEM, -+ .active_low = 1, -+ }, { -+ .name = "tl-wr1043nd:green:qss", -+ .gpio = TL_WR1043ND_GPIO_LED_QSS, -+ .active_low = 0, -+ }, { -+ .name = "tl-wr1043nd:green:wlan", -+ .gpio = TL_WR1043ND_GPIO_LED_WLAN, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_button tl_wr1043nd_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = TL_WR1043ND_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "qss", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = TL_WR1043ND_GPIO_BTN_QSS, -+ .active_low = 1, -+ } -+}; -+ -+static struct rtl8366rb_platform_data tl_wr1043nd_rtl8366rb_data = { -+ .gpio_sda = TL_WR1043ND_GPIO_RTL8366_SDA, -+ .gpio_sck = TL_WR1043ND_GPIO_RTL8366_SCK, -+}; -+ -+static struct platform_device tl_wr1043nd_rtl8366rb_device = { -+ .name = RTL8366RB_DRIVER_NAME, -+ .id = -1, -+ .dev = { -+ .platform_data = &tl_wr1043nd_rtl8366rb_data, -+ } -+}; -+ -+static void __init tl_wr1043nd_setup(void) -+{ -+ u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ -+ ar71xx_set_mac_base(mac); -+ -+ ar71xx_eth0_data.mii_bus_dev = &tl_wr1043nd_rtl8366rb_device.dev; -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth0_data.speed = SPEED_1000; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ ar71xx_eth0_pll_data.pll_1000 = 0x1a000000; -+ -+ ar71xx_add_device_eth(0); -+ -+ ar71xx_add_device_usb(); -+ -+ ar71xx_add_device_m25p80(&tl_wr1043nd_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(tl_wr1043nd_leds_gpio), -+ tl_wr1043nd_leds_gpio); -+ -+ platform_device_register(&tl_wr1043nd_rtl8366rb_device); -+ -+ ar71xx_add_device_gpio_buttons(-1, TL_WR1043ND_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(tl_wr1043nd_gpio_buttons), -+ tl_wr1043nd_gpio_buttons); -+ -+ ar913x_add_device_wmac(eeprom, mac); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_TL_WR1043ND, "TL-WR1043ND", "TP-LINK TL-WR1043ND", -+ tl_wr1043nd_setup); -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/mach-tl-wr741nd.c linux-2.6.37/arch/mips/ar71xx/mach-tl-wr741nd.c ---- linux-2.6.37.orig/arch/mips/ar71xx/mach-tl-wr741nd.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/mach-tl-wr741nd.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,115 @@ -+/* -+ * TP-LINK TL-WR741ND board support -+ * -+ * Copyright (C) 2009-2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ap91-eth.h" -+#include "dev-ap91-pci.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+ -+#define TL_WR741ND_GPIO_LED_QSS 0 -+#define TL_WR741ND_GPIO_LED_SYSTEM 1 -+ -+#define TL_WR741ND_GPIO_BTN_RESET 11 -+#define TL_WR741ND_GPIO_BTN_QSS 12 -+ -+#define TL_WR741ND_BUTTONS_POLL_INTERVAL 20 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition tl_wr741nd_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "kernel", -+ .offset = 0x020000, -+ .size = 0x140000, -+ } , { -+ .name = "rootfs", -+ .offset = 0x160000, -+ .size = 0x290000, -+ } , { -+ .name = "art", -+ .offset = 0x3f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "firmware", -+ .offset = 0x020000, -+ .size = 0x3d0000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data tl_wr741nd_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = tl_wr741nd_partitions, -+ .nr_parts = ARRAY_SIZE(tl_wr741nd_partitions), -+#endif -+}; -+ -+static struct gpio_led tl_wr741nd_leds_gpio[] __initdata = { -+ { -+ .name = "tl-wr741nd:green:system", -+ .gpio = TL_WR741ND_GPIO_LED_SYSTEM, -+ .active_low = 1, -+ }, { -+ .name = "tl-wr741nd:green:qss", -+ .gpio = TL_WR741ND_GPIO_LED_QSS, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_button tl_wr741nd_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = TL_WR741ND_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "qss", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = TL_WR741ND_GPIO_BTN_QSS, -+ .active_low = 1, -+ } -+}; -+ -+static void __init tl_wr741nd_setup(void) -+{ -+ u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); -+ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); -+ -+ ar71xx_add_device_m25p80(&tl_wr741nd_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(tl_wr741nd_leds_gpio), -+ tl_wr741nd_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, TL_WR741ND_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(tl_wr741nd_gpio_buttons), -+ tl_wr741nd_gpio_buttons); -+ -+ ap91_eth_init(mac, NULL); -+ ap91_pci_init(ee, mac); -+} -+MIPS_MACHINE(AR71XX_MACH_TL_WR741ND, "TL-WR741ND", "TP-LINK TL-WR741ND", -+ tl_wr741nd_setup); -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/mach-tl-wr841n.c linux-2.6.37/arch/mips/ar71xx/mach-tl-wr841n.c ---- linux-2.6.37.orig/arch/mips/ar71xx/mach-tl-wr841n.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/mach-tl-wr841n.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,143 @@ -+/* -+ * TP-LINK TL-WR841N board support -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-dsa.h" -+#include "dev-m25p80.h" -+#include "dev-gpio-buttons.h" -+#include "dev-pb42-pci.h" -+#include "dev-leds-gpio.h" -+ -+#define TL_WR841ND_V1_GPIO_LED_SYSTEM 2 -+#define TL_WR841ND_V1_GPIO_LED_QSS_GREEN 4 -+#define TL_WR841ND_V1_GPIO_LED_QSS_RED 5 -+ -+#define TL_WR841ND_V1_GPIO_BTN_RESET 3 -+#define TL_WR841ND_V1_GPIO_BTN_QSS 7 -+ -+#define TL_WR841ND_V1_BUTTONS_POLL_INTERVAL 20 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition tl_wr841n_v1_partitions[] = { -+ { -+ .name = "redboot", -+ .offset = 0, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "kernel", -+ .offset = 0x020000, -+ .size = 0x140000, -+ } , { -+ .name = "rootfs", -+ .offset = 0x160000, -+ .size = 0x280000, -+ } , { -+ .name = "config", -+ .offset = 0x3e0000, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "firmware", -+ .offset = 0x020000, -+ .size = 0x3c0000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data tl_wr841n_v1_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = tl_wr841n_v1_partitions, -+ .nr_parts = ARRAY_SIZE(tl_wr841n_v1_partitions), -+#endif -+}; -+ -+static struct gpio_led tl_wr841n_v1_leds_gpio[] __initdata = { -+ { -+ .name = "tl-wr841n:green:system", -+ .gpio = TL_WR841ND_V1_GPIO_LED_SYSTEM, -+ .active_low = 1, -+ }, { -+ .name = "tl-wr841n:red:qss", -+ .gpio = TL_WR841ND_V1_GPIO_LED_QSS_RED, -+ }, { -+ .name = "tl-wr841n:green:qss", -+ .gpio = TL_WR841ND_V1_GPIO_LED_QSS_GREEN, -+ } -+}; -+ -+static struct gpio_button tl_wr841n_v1_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = TL_WR841ND_V1_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "qss", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = TL_WR841ND_V1_GPIO_BTN_QSS, -+ .active_low = 1, -+ } -+}; -+ -+static struct dsa_chip_data tl_wr841n_v1_dsa_chip = { -+ .port_names[0] = "wan", -+ .port_names[1] = "lan1", -+ .port_names[2] = "lan2", -+ .port_names[3] = "lan3", -+ .port_names[4] = "lan4", -+ .port_names[5] = "cpu", -+}; -+ -+static struct dsa_platform_data tl_wr841n_v1_dsa_data = { -+ .nr_chips = 1, -+ .chip = &tl_wr841n_v1_dsa_chip, -+}; -+ -+static void __init tl_wr841n_v1_setup(void) -+{ -+ u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); -+ -+ ar71xx_set_mac_base(mac); -+ -+ ar71xx_add_device_mdio(0x0); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_add_device_eth(0); -+ -+ ar71xx_add_device_dsa(0, &tl_wr841n_v1_dsa_data); -+ -+ ar71xx_add_device_m25p80(&tl_wr841n_v1_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(tl_wr841n_v1_leds_gpio), -+ tl_wr841n_v1_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, TL_WR841ND_V1_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(tl_wr841n_v1_gpio_buttons), -+ tl_wr841n_v1_gpio_buttons); -+ -+ pb42_pci_init(); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_TL_WR841N_V1, "TL-WR841N-v1.5", "TP-LINK TL-WR841N v1", -+ tl_wr841n_v1_setup); -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/mach-tl-wr941nd.c linux-2.6.37/arch/mips/ar71xx/mach-tl-wr941nd.c ---- linux-2.6.37.orig/arch/mips/ar71xx/mach-tl-wr941nd.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/mach-tl-wr941nd.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,142 @@ -+/* -+ * TP-LINK TL-WR941ND board support -+ * -+ * Copyright (C) 2009-2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-dsa.h" -+#include "dev-m25p80.h" -+#include "dev-ar913x-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+ -+#define TL_WR941ND_GPIO_LED_SYSTEM 2 -+#define TL_WR941ND_GPIO_LED_QSS_RED 4 -+#define TL_WR941ND_GPIO_LED_QSS_GREEN 5 -+ -+#define TL_WR941ND_GPIO_BTN_RESET 3 -+#define TL_WR941ND_GPIO_BTN_QSS 7 -+ -+#define TL_WR941ND_BUTTONS_POLL_INTERVAL 20 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition tl_wr941nd_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "kernel", -+ .offset = 0x020000, -+ .size = 0x140000, -+ } , { -+ .name = "rootfs", -+ .offset = 0x160000, -+ .size = 0x290000, -+ } , { -+ .name = "art", -+ .offset = 0x3f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "firmware", -+ .offset = 0x020000, -+ .size = 0x3d0000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data tl_wr941nd_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = tl_wr941nd_partitions, -+ .nr_parts = ARRAY_SIZE(tl_wr941nd_partitions), -+#endif -+}; -+ -+static struct gpio_led tl_wr941nd_leds_gpio[] __initdata = { -+ { -+ .name = "tl-wr941nd:green:system", -+ .gpio = TL_WR941ND_GPIO_LED_SYSTEM, -+ .active_low = 1, -+ }, { -+ .name = "tl-wr941nd:red:qss", -+ .gpio = TL_WR941ND_GPIO_LED_QSS_RED, -+ }, { -+ .name = "tl-wr941nd:green:qss", -+ .gpio = TL_WR941ND_GPIO_LED_QSS_GREEN, -+ } -+}; -+ -+static struct gpio_button tl_wr941nd_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = TL_WR941ND_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "qss", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = TL_WR941ND_GPIO_BTN_QSS, -+ .active_low = 1, -+ } -+}; -+ -+static struct dsa_chip_data tl_wr941nd_dsa_chip = { -+ .port_names[0] = "wan", -+ .port_names[1] = "lan1", -+ .port_names[2] = "lan2", -+ .port_names[3] = "lan3", -+ .port_names[4] = "lan4", -+ .port_names[5] = "cpu", -+}; -+ -+static struct dsa_platform_data tl_wr941nd_dsa_data = { -+ .nr_chips = 1, -+ .chip = &tl_wr941nd_dsa_chip, -+}; -+ -+static void __init tl_wr941nd_setup(void) -+{ -+ u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ -+ ar71xx_set_mac_base(mac); -+ -+ ar71xx_add_device_mdio(0x0); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_dsa(0, &tl_wr941nd_dsa_data); -+ -+ ar71xx_add_device_m25p80(&tl_wr941nd_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(tl_wr941nd_leds_gpio), -+ tl_wr941nd_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, TL_WR941ND_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(tl_wr941nd_gpio_buttons), -+ tl_wr941nd_gpio_buttons); -+ ar913x_add_device_wmac(eeprom, mac); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_TL_WR941ND, "TL-WR941ND", "TP-LINK TL-WR941ND", -+ tl_wr941nd_setup); -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/mach-ubnt.c linux-2.6.37/arch/mips/ar71xx/mach-ubnt.c ---- linux-2.6.37.orig/arch/mips/ar71xx/mach-ubnt.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/mach-ubnt.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,281 @@ -+/* -+ * Ubiquiti RouterStation support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * Copyright (C) 2008 Ubiquiti -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ap91-pci.h" -+#include "dev-gpio-buttons.h" -+#include "dev-pb42-pci.h" -+#include "dev-leds-gpio.h" -+#include "dev-usb.h" -+ -+#define UBNT_RS_GPIO_LED_RF 2 -+#define UBNT_RS_GPIO_SW4 8 -+ -+#define UBNT_LS_SR71_GPIO_LED_D25 0 -+#define UBNT_LS_SR71_GPIO_LED_D26 1 -+#define UBNT_LS_SR71_GPIO_LED_D24 2 -+#define UBNT_LS_SR71_GPIO_LED_D23 4 -+#define UBNT_LS_SR71_GPIO_LED_D22 5 -+#define UBNT_LS_SR71_GPIO_LED_D27 6 -+#define UBNT_LS_SR71_GPIO_LED_D28 7 -+ -+#define UBNT_M_GPIO_LED_L1 0 -+#define UBNT_M_GPIO_LED_L2 1 -+#define UBNT_M_GPIO_LED_L3 11 -+#define UBNT_M_GPIO_LED_L4 7 -+#define UBNT_M_GPIO_BTN_RESET 12 -+ -+#define UBNT_BUTTONS_POLL_INTERVAL 20 -+ -+static struct gpio_led ubnt_rs_leds_gpio[] __initdata = { -+ { -+ .name = "ubnt:green:rf", -+ .gpio = UBNT_RS_GPIO_LED_RF, -+ .active_low = 0, -+ } -+}; -+ -+static struct gpio_led ubnt_ls_sr71_leds_gpio[] __initdata = { -+ { -+ .name = "ubnt:green:d22", -+ .gpio = UBNT_LS_SR71_GPIO_LED_D22, -+ .active_low = 0, -+ }, { -+ .name = "ubnt:green:d23", -+ .gpio = UBNT_LS_SR71_GPIO_LED_D23, -+ .active_low = 0, -+ }, { -+ .name = "ubnt:green:d24", -+ .gpio = UBNT_LS_SR71_GPIO_LED_D24, -+ .active_low = 0, -+ }, { -+ .name = "ubnt:red:d25", -+ .gpio = UBNT_LS_SR71_GPIO_LED_D25, -+ .active_low = 0, -+ }, { -+ .name = "ubnt:red:d26", -+ .gpio = UBNT_LS_SR71_GPIO_LED_D26, -+ .active_low = 0, -+ }, { -+ .name = "ubnt:green:d27", -+ .gpio = UBNT_LS_SR71_GPIO_LED_D27, -+ .active_low = 0, -+ }, { -+ .name = "ubnt:green:d28", -+ .gpio = UBNT_LS_SR71_GPIO_LED_D28, -+ .active_low = 0, -+ } -+}; -+ -+static struct gpio_led ubnt_m_leds_gpio[] __initdata = { -+ { -+ .name = "ubnt:red:link1", -+ .gpio = UBNT_M_GPIO_LED_L1, -+ .active_low = 0, -+ }, { -+ .name = "ubnt:orange:link2", -+ .gpio = UBNT_M_GPIO_LED_L2, -+ .active_low = 0, -+ }, { -+ .name = "ubnt:green:link3", -+ .gpio = UBNT_M_GPIO_LED_L3, -+ .active_low = 0, -+ }, { -+ .name = "ubnt:green:link4", -+ .gpio = UBNT_M_GPIO_LED_L4, -+ .active_low = 0, -+ } -+}; -+ -+static struct gpio_button ubnt_gpio_buttons[] __initdata = { -+ { -+ .desc = "sw4", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = UBNT_RS_GPIO_SW4, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_button ubnt_m_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = UBNT_M_GPIO_BTN_RESET, -+ .active_low = 1, -+ } -+}; -+ -+static void __init ubnt_generic_setup(void) -+{ -+ ar71xx_add_device_m25p80(NULL); -+ -+ ar71xx_add_device_gpio_buttons(-1, UBNT_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(ubnt_gpio_buttons), -+ ubnt_gpio_buttons); -+ -+ pb42_pci_init(); -+} -+ -+#define UBNT_RS_WAN_PHYMASK (1 << 20) -+#define UBNT_RS_LAN_PHYMASK ((1 << 16) | (1 << 17) | (1 << 18) | (1 << 19)) -+ -+static void __init ubnt_rs_setup(void) -+{ -+ ubnt_generic_setup(); -+ -+ ar71xx_add_device_mdio(~(UBNT_RS_WAN_PHYMASK | UBNT_RS_LAN_PHYMASK)); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; -+ ar71xx_eth0_data.phy_mask = UBNT_RS_WAN_PHYMASK; -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.speed = SPEED_100; -+ ar71xx_eth1_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_usb(); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ubnt_rs_leds_gpio), -+ ubnt_rs_leds_gpio); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_UBNT_RS, "UBNT-RS", "Ubiquiti RouterStation", -+ ubnt_rs_setup); -+ -+MIPS_MACHINE(AR71XX_MACH_UBNT_AR71XX, "Ubiquiti AR71xx-based board", -+ "Ubiquiti RouterStation", ubnt_rs_setup); -+ -+#define UBNT_RSPRO_WAN_PHYMASK (1 << 4) -+#define UBNT_RSPRO_LAN_PHYMASK ((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)) -+ -+static void __init ubnt_rspro_setup(void) -+{ -+ ubnt_generic_setup(); -+ -+ ar71xx_add_device_mdio(~(UBNT_RSPRO_WAN_PHYMASK | UBNT_RSPRO_LAN_PHYMASK)); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth0_data.phy_mask = UBNT_RSPRO_WAN_PHYMASK; -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth1_data.phy_mask = UBNT_RSPRO_LAN_PHYMASK; -+ ar71xx_eth1_data.speed = SPEED_1000; -+ ar71xx_eth1_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_usb(); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ubnt_rs_leds_gpio), -+ ubnt_rs_leds_gpio); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_UBNT_RSPRO, "UBNT-RSPRO", "Ubiquiti RouterStation Pro", -+ ubnt_rspro_setup); -+ -+static void __init ubnt_lsx_setup(void) -+{ -+ ubnt_generic_setup(); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_UBNT_LSX, "UBNT-LSX", "Ubiquiti LSX", ubnt_lsx_setup); -+ -+#define UBNT_LSSR71_PHY_MASK (1 << 1) -+ -+static void __init ubnt_lssr71_setup(void) -+{ -+ ubnt_generic_setup(); -+ -+ ar71xx_add_device_mdio(~UBNT_LSSR71_PHY_MASK); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; -+ ar71xx_eth0_data.phy_mask = UBNT_LSSR71_PHY_MASK; -+ -+ ar71xx_add_device_eth(0); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ubnt_ls_sr71_leds_gpio), -+ ubnt_ls_sr71_leds_gpio); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_UBNT_LSSR71, "UBNT-LS-SR71", "Ubiquiti LS-SR71", -+ ubnt_lssr71_setup); -+ -+static void __init ubnt_m_setup(void) -+{ -+ u8 *mac = (u8 *) KSEG1ADDR(0x1fff0000); -+ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); -+ -+ ar71xx_set_mac_base(mac); -+ -+ ar71xx_add_device_m25p80(NULL); -+ -+ ar71xx_add_device_mdio(~0); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ ar71xx_eth0_data.fifo_cfg1 = 0x0010ffff; -+ ar71xx_eth0_data.fifo_cfg2 = 0x015500aa; -+ ar71xx_eth0_data.fifo_cfg3 = 0x01f00140; -+ -+ ar71xx_add_device_eth(0); -+ -+ ap91_pci_init(ee, NULL); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ubnt_m_leds_gpio), -+ ubnt_m_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, UBNT_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(ubnt_m_gpio_buttons), -+ ubnt_m_gpio_buttons); -+} -+ -+static void __init ubnt_rocket_m_setup(void) -+{ -+ ubnt_m_setup(); -+ ar71xx_add_device_usb(); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_UBNT_BULLET_M, "UBNT-BM", "Ubiquiti Bullet M", -+ ubnt_m_setup); -+MIPS_MACHINE(AR71XX_MACH_UBNT_ROCKET_M, "UBNT-RM", "Ubiquiti Rocket M", -+ ubnt_rocket_m_setup); -+ -+/* TODO detect the second ethernet port and use one -+ init function for all Ubiquiti MIMO series products */ -+static void __init ubnt_nano_m_setup(void) -+{ -+ ubnt_m_setup(); -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.speed = SPEED_1000; -+ ar71xx_eth1_data.duplex = DUPLEX_FULL; -+ ar71xx_eth1_data.fifo_cfg1 = 0x0010ffff; -+ ar71xx_eth1_data.fifo_cfg2 = 0x015500aa; -+ ar71xx_eth1_data.fifo_cfg3 = 0x01f00140; -+ -+ ar71xx_add_device_eth(1); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_UBNT_NANO_M, "UBNT-NM", "Ubiquiti Nanostation M", -+ ubnt_nano_m_setup); -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/mach-wndr3700.c linux-2.6.37/arch/mips/ar71xx/mach-wndr3700.c ---- linux-2.6.37.orig/arch/mips/ar71xx/mach-wndr3700.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/mach-wndr3700.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,209 @@ -+/* -+ * Netgear WNDR3700 board support -+ * -+ * Copyright (C) 2009 Marco Porsch -+ * Copyright (C) 2009-2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ap94-pci.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-usb.h" -+ -+#define WNDR3700_GPIO_LED_WPS_ORANGE 0 -+#define WNDR3700_GPIO_LED_POWER_ORANGE 1 -+#define WNDR3700_GPIO_LED_POWER_GREEN 2 -+#define WNDR3700_GPIO_LED_WPS_GREEN 4 -+#define WNDR3700_GPIO_LED_WAN_GREEN 6 -+ -+#define WNDR3700_GPIO_BTN_WPS 3 -+#define WNDR3700_GPIO_BTN_RESET 8 -+#define WNDR3700_GPIO_BTN_WIFI 11 -+ -+#define WNDR3700_GPIO_RTL8366_SDA 5 -+#define WNDR3700_GPIO_RTL8366_SCK 7 -+ -+#define WNDR3700_BUTTONS_POLL_INTERVAL 20 -+ -+#define WNDR3700_WMAC0_MAC_OFFSET 0 -+#define WNDR3700_WMAC1_MAC_OFFSET 0xc -+#define WNDR3700_CALDATA0_OFFSET 0x1000 -+#define WNDR3700_CALDATA1_OFFSET 0x5000 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition wndr3700_partitions[] = { -+ { -+ .name = "uboot", -+ .offset = 0, -+ .size = 0x050000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "env", -+ .offset = 0x050000, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "rootfs", -+ .offset = 0x070000, -+ .size = 0x720000, -+ } , { -+ .name = "config", -+ .offset = 0x790000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "config_bak", -+ .offset = 0x7a0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "pot", -+ .offset = 0x7b0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "traffic_meter", -+ .offset = 0x7c0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "language", -+ .offset = 0x7d0000, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "caldata", -+ .offset = 0x7f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data wndr3700_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = wndr3700_partitions, -+ .nr_parts = ARRAY_SIZE(wndr3700_partitions), -+#endif -+}; -+ -+static struct gpio_led wndr3700_leds_gpio[] __initdata = { -+ { -+ .name = "wndr3700:green:power", -+ .gpio = WNDR3700_GPIO_LED_POWER_GREEN, -+ .active_low = 1, -+ }, { -+ .name = "wndr3700:orange:power", -+ .gpio = WNDR3700_GPIO_LED_POWER_ORANGE, -+ .active_low = 1, -+ }, { -+ .name = "wndr3700:green:wps", -+ .gpio = WNDR3700_GPIO_LED_WPS_GREEN, -+ .active_low = 1, -+ }, { -+ .name = "wndr3700:orange:wps", -+ .gpio = WNDR3700_GPIO_LED_WPS_ORANGE, -+ .active_low = 1, -+ }, { -+ .name = "wndr3700:green:wan", -+ .gpio = WNDR3700_GPIO_LED_WAN_GREEN, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_button wndr3700_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = WNDR3700_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "wps", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = WNDR3700_GPIO_BTN_WPS, -+ .active_low = 1, -+ } , { -+ .desc = "wifi", -+ .type = EV_KEY, -+ .code = BTN_2, -+ .threshold = 3, -+ .gpio = WNDR3700_GPIO_BTN_WIFI, -+ .active_low = 1, -+ } -+}; -+ -+static struct rtl8366s_platform_data wndr3700_rtl8366s_data = { -+ .gpio_sda = WNDR3700_GPIO_RTL8366_SDA, -+ .gpio_sck = WNDR3700_GPIO_RTL8366_SCK, -+}; -+ -+static struct platform_device wndr3700_rtl8366s_device = { -+ .name = RTL8366S_DRIVER_NAME, -+ .id = -1, -+ .dev = { -+ .platform_data = &wndr3700_rtl8366s_data, -+ } -+}; -+ -+static void __init wndr3700_setup(void) -+{ -+ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); -+ -+ ar71xx_set_mac_base(art); -+ -+ ar71xx_eth0_pll_data.pll_1000 = 0x11110000; -+ ar71xx_eth0_data.mii_bus_dev = &wndr3700_rtl8366s_device.dev; -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth0_data.speed = SPEED_1000; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_eth1_pll_data.pll_1000 = 0x11110000; -+ ar71xx_eth1_data.mii_bus_dev = &wndr3700_rtl8366s_device.dev; -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth1_data.phy_mask = 0x10; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_usb(); -+ -+ ar71xx_add_device_m25p80(&wndr3700_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(wndr3700_leds_gpio), -+ wndr3700_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, WNDR3700_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(wndr3700_gpio_buttons), -+ wndr3700_gpio_buttons); -+ -+ platform_device_register(&wndr3700_rtl8366s_device); -+ platform_device_register_simple("wndr3700-led-usb", -1, NULL, 0); -+ -+ ap94_pci_enable_quirk_wndr3700(); -+ ap94_pci_init(art + WNDR3700_CALDATA0_OFFSET, -+ art + WNDR3700_WMAC0_MAC_OFFSET, -+ art + WNDR3700_CALDATA1_OFFSET, -+ art + WNDR3700_WMAC1_MAC_OFFSET); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_WNDR3700, "WNDR3700", "NETGEAR WNDR3700", -+ wndr3700_setup); -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/mach-wnr2000.c linux-2.6.37/arch/mips/ar71xx/mach-wnr2000.c ---- linux-2.6.37.orig/arch/mips/ar71xx/mach-wnr2000.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/mach-wnr2000.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,148 @@ -+/* -+ * NETGEAR WNR2000 board support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * Copyright (C) 2008-2009 Andy Boyett -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ar913x-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+ -+#define WNR2000_GPIO_LED_PWR_GREEN 14 -+#define WNR2000_GPIO_LED_PWR_AMBER 7 -+#define WNR2000_GPIO_LED_WPS 4 -+#define WNR2000_GPIO_LED_WLAN 6 -+#define WNR2000_GPIO_BTN_RESET 21 -+#define WNR2000_GPIO_BTN_WPS 8 -+ -+#define WNR2000_BUTTONS_POLL_INTERVAL 20 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition wnr2000_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x040000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "u-boot-env", -+ .offset = 0x040000, -+ .size = 0x010000, -+ } , { -+ .name = "rootfs", -+ .offset = 0x050000, -+ .size = 0x240000, -+ } , { -+ .name = "user-config", -+ .offset = 0x290000, -+ .size = 0x010000, -+ } , { -+ .name = "uImage", -+ .offset = 0x2a0000, -+ .size = 0x120000, -+ } , { -+ .name = "language_table", -+ .offset = 0x3c0000, -+ .size = 0x020000, -+ } , { -+ .name = "rootfs_checksum", -+ .offset = 0x3e0000, -+ .size = 0x010000, -+ } , { -+ .name = "art", -+ .offset = 0x3f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data wnr2000_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = wnr2000_partitions, -+ .nr_parts = ARRAY_SIZE(wnr2000_partitions), -+#endif -+}; -+ -+static struct gpio_led wnr2000_leds_gpio[] __initdata = { -+ { -+ .name = "wnr2000:green:power", -+ .gpio = WNR2000_GPIO_LED_PWR_GREEN, -+ .active_low = 1, -+ }, { -+ .name = "wnr2000:amber:power", -+ .gpio = WNR2000_GPIO_LED_PWR_AMBER, -+ .active_low = 1, -+ }, { -+ .name = "wnr2000:green:wps", -+ .gpio = WNR2000_GPIO_LED_WPS, -+ .active_low = 1, -+ }, { -+ .name = "wnr2000:blue:wlan", -+ .gpio = WNR2000_GPIO_LED_WLAN, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_button wnr2000_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = WNR2000_GPIO_BTN_RESET, -+ }, { -+ .desc = "wps", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = WNR2000_GPIO_BTN_WPS, -+ } -+}; -+ -+static void __init wnr2000_setup(void) -+{ -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ -+ ar71xx_set_mac_base(eeprom); -+ ar71xx_add_device_mdio(0x0); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ ar71xx_eth0_data.has_ar8216 = 1; -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.phy_mask = 0x10; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_m25p80(&wnr2000_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(wnr2000_leds_gpio), -+ wnr2000_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, WNR2000_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(wnr2000_gpio_buttons), -+ wnr2000_gpio_buttons); -+ -+ -+ ar913x_add_device_wmac(eeprom, NULL); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_WNR2000, "WNR2000", "NETGEAR WNR2000", wnr2000_setup); -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/mach-wp543.c linux-2.6.37/arch/mips/ar71xx/mach-wp543.c ---- linux-2.6.37.orig/arch/mips/ar71xx/mach-wp543.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/mach-wp543.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,99 @@ -+/* -+ * Compex WP543/WPJ543 board support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-pb42-pci.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-usb.h" -+ -+#define WP543_GPIO_SW6 2 -+#define WP543_GPIO_LED_1 3 -+#define WP543_GPIO_LED_2 4 -+#define WP543_GPIO_LED_WLAN 5 -+#define WP543_GPIO_LED_CONN 6 -+#define WP543_GPIO_LED_DIAG 7 -+#define WP543_GPIO_SW4 8 -+ -+#define WP543_BUTTONS_POLL_INTERVAL 20 -+ -+static struct gpio_led wp543_leds_gpio[] __initdata = { -+ { -+ .name = "wp543:green:led1", -+ .gpio = WP543_GPIO_LED_1, -+ .active_low = 1, -+ }, { -+ .name = "wp543:green:led2", -+ .gpio = WP543_GPIO_LED_2, -+ .active_low = 1, -+ }, { -+ .name = "wp543:green:wlan", -+ .gpio = WP543_GPIO_LED_WLAN, -+ .active_low = 1, -+ }, { -+ .name = "wp543:green:conn", -+ .gpio = WP543_GPIO_LED_CONN, -+ .active_low = 1, -+ }, { -+ .name = "wp543:green:diag", -+ .gpio = WP543_GPIO_LED_DIAG, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_button wp543_gpio_buttons[] __initdata = { -+ { -+ .desc = "sw6", -+ .type = EV_KEY, -+ .code = BTN_0, -+ .threshold = 3, -+ .gpio = WP543_GPIO_SW6, -+ }, { -+ .desc = "sw4", -+ .type = EV_KEY, -+ .code = BTN_1, -+ .threshold = 3, -+ .gpio = WP543_GPIO_SW4, -+ } -+}; -+ -+static void __init wp543_setup(void) -+{ -+ ar71xx_add_device_m25p80(NULL); -+ -+ ar71xx_add_device_mdio(0xfffffff7); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; -+ ar71xx_eth0_data.phy_mask = 0x08; -+ ar71xx_eth0_data.reset_bit = RESET_MODULE_GE0_MAC | -+ RESET_MODULE_GE0_PHY; -+ ar71xx_add_device_eth(0); -+ -+ ar71xx_add_device_usb(); -+ -+ pb42_pci_init(); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(wp543_leds_gpio), -+ wp543_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, WP543_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(wp543_gpio_buttons), -+ wp543_gpio_buttons); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_WP543, "WP543", "Compex WP543", wp543_setup); -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/mach-wrt160nl.c linux-2.6.37/arch/mips/ar71xx/mach-wrt160nl.c ---- linux-2.6.37.orig/arch/mips/ar71xx/mach-wrt160nl.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/mach-wrt160nl.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,158 @@ -+/* -+ * Linksys WRT160NL board support -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ar913x-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-usb.h" -+#include "nvram.h" -+ -+#define WRT160NL_GPIO_LED_POWER 14 -+#define WRT160NL_GPIO_LED_WPS_AMBER 9 -+#define WRT160NL_GPIO_LED_WPS_BLUE 8 -+#define WRT160NL_GPIO_LED_WLAN 6 -+ -+#define WRT160NL_GPIO_BTN_WPS 7 -+#define WRT160NL_GPIO_BTN_RESET 21 -+ -+#define WRT160NL_BUTTONS_POLL_INTERVAL 20 -+ -+#define WRT160NL_NVRAM_ADDR 0x1f7e0000 -+#define WRT160NL_NVRAM_SIZE 0x10000 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition wrt160nl_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x040000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "kernel", -+ .offset = 0x040000, -+ .size = 0x0e0000, -+ } , { -+ .name = "filesytem", -+ .offset = 0x120000, -+ .size = 0x6c0000, -+ } , { -+ .name = "nvram", -+ .offset = 0x7e0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "ART", -+ .offset = 0x7f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "firmware", -+ .offset = 0x040000, -+ .size = 0x7a0000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data wrt160nl_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = wrt160nl_partitions, -+ .nr_parts = ARRAY_SIZE(wrt160nl_partitions), -+#endif -+}; -+ -+static struct gpio_led wrt160nl_leds_gpio[] __initdata = { -+ { -+ .name = "wrt160nl:blue:power", -+ .gpio = WRT160NL_GPIO_LED_POWER, -+ .active_low = 1, -+ .default_trigger = "default-on", -+ }, { -+ .name = "wrt160nl:amber:wps", -+ .gpio = WRT160NL_GPIO_LED_WPS_AMBER, -+ .active_low = 1, -+ }, { -+ .name = "wrt160nl:blue:wps", -+ .gpio = WRT160NL_GPIO_LED_WPS_BLUE, -+ .active_low = 1, -+ }, { -+ .name = "wrt160nl:blue:wlan", -+ .gpio = WRT160NL_GPIO_LED_WLAN, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_button wrt160nl_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = WRT160NL_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "wps", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = WRT160NL_GPIO_BTN_WPS, -+ .active_low = 1, -+ } -+}; -+ -+static void __init wrt160nl_setup(void) -+{ -+ const char *nvram = (char *) KSEG1ADDR(WRT160NL_NVRAM_ADDR); -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ u8 mac[6]; -+ -+ if (nvram_parse_mac_addr(nvram, WRT160NL_NVRAM_SIZE, -+ "lan_hwaddr=", mac) == 0) -+ ar71xx_set_mac_base(mac); -+ -+ ar71xx_add_device_mdio(0x0); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.phy_mask = 0x01; -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.phy_mask = 0x10; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_m25p80(&wrt160nl_flash_data); -+ -+ ar71xx_add_device_usb(); -+ -+ if (nvram_parse_mac_addr(nvram, WRT160NL_NVRAM_SIZE, -+ "wl0_hwaddr=", mac) == 0) -+ ar913x_add_device_wmac(eeprom, mac); -+ else -+ ar913x_add_device_wmac(eeprom, NULL); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(wrt160nl_leds_gpio), -+ wrt160nl_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, WRT160NL_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(wrt160nl_gpio_buttons), -+ wrt160nl_gpio_buttons); -+ -+} -+ -+MIPS_MACHINE(AR71XX_MACH_WRT160NL, "WRT160NL", "Linksys WRT160NL", -+ wrt160nl_setup); -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/mach-wrt400n.c linux-2.6.37/arch/mips/ar71xx/mach-wrt400n.c ---- linux-2.6.37.orig/arch/mips/ar71xx/mach-wrt400n.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/mach-wrt400n.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,168 @@ -+/* -+ * Linksys WRT400N board support -+ * -+ * Copyright (C) 2009-2010 Gabor Juhos -+ * Copyright (C) 2009 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-ap94-pci.h" -+#include "dev-m25p80.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+ -+#define WRT400N_GPIO_LED_ORANGE 5 -+#define WRT400N_GPIO_LED_GREEN 4 -+#define WRT400N_GPIO_LED_POWER 1 -+#define WRT400N_GPIO_LED_WLAN 0 -+ -+#define WRT400N_GPIO_BTN_RESET 8 -+#define WRT400N_GPIO_BTN_WLSEC 3 -+ -+#define WRT400N_BUTTONS_POLL_INTERVAL 20 -+ -+#define WRT400N_MAC_ADDR_OFFSET 0x120c -+#define WRT400N_CALDATA0_OFFSET 0x1000 -+#define WRT400N_CALDATA1_OFFSET 0x5000 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition wrt400n_partitions[] = { -+ { -+ .name = "uboot", -+ .offset = 0, -+ .size = 0x030000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "env", -+ .offset = 0x030000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "linux", -+ .offset = 0x040000, -+ .size = 0x140000, -+ } , { -+ .name = "rootfs", -+ .offset = 0x180000, -+ .size = 0x630000, -+ } , { -+ .name = "nvram", -+ .offset = 0x7b0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "factory", -+ .offset = 0x7c0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "language", -+ .offset = 0x7d0000, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "caldata", -+ .offset = 0x7f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "firmware", -+ .offset = 0x040000, -+ .size = 0x770000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data wrt400n_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = wrt400n_partitions, -+ .nr_parts = ARRAY_SIZE(wrt400n_partitions), -+#endif -+}; -+ -+static struct gpio_led wrt400n_leds_gpio[] __initdata = { -+ { -+ .name = "wrt400n:green:status", -+ .gpio = WRT400N_GPIO_LED_GREEN, -+ .active_low = 1, -+ }, { -+ .name = "wrt400n:amber:aoss", -+ .gpio = WRT400N_GPIO_LED_ORANGE, -+ .active_low = 1, -+ }, { -+ .name = "wrt400n:green:wlan", -+ .gpio = WRT400N_GPIO_LED_WLAN, -+ .active_low = 1, -+ }, { -+ .name = "wrt400n:green:power", -+ .gpio = WRT400N_GPIO_LED_POWER, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_button wrt400n_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = WRT400N_GPIO_BTN_RESET, -+ .active_low = 1, -+ } , { -+ .desc = "wlsec", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = WRT400N_GPIO_BTN_WLSEC, -+ .active_low = 1, -+ } -+}; -+ -+static void __init wrt400n_setup(void) -+{ -+ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); -+ u8 mac[6]; -+ int i; -+ -+ memcpy(mac, art + WRT400N_MAC_ADDR_OFFSET, 6); -+ for (i = 5; i >= 3; i--) -+ if (++mac[i] != 0x00) break; -+ -+ ar71xx_set_mac_base(mac); -+ -+ ar71xx_add_device_mdio(0x0); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.phy_mask = 0x10; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_m25p80(&wrt400n_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(wrt400n_leds_gpio), -+ wrt400n_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, WRT400N_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(wrt400n_gpio_buttons), -+ wrt400n_gpio_buttons); -+ -+ ap94_pci_init(art + WRT400N_CALDATA0_OFFSET, NULL, -+ art + WRT400N_CALDATA1_OFFSET, NULL); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_WRT400N, "WRT400N", "Linksys WRT400N", wrt400n_setup); -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/mach-wzr-hp-g300nh.c linux-2.6.37/arch/mips/ar71xx/mach-wzr-hp-g300nh.c ---- linux-2.6.37.orig/arch/mips/ar71xx/mach-wzr-hp-g300nh.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/mach-wzr-hp-g300nh.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,265 @@ -+/* -+ * Buffalo WZR-HP-G300NH board support -+ * -+ * Copyright (C) 2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-ar913x-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-usb.h" -+ -+#define WZRHPG300NH_GPIO_LED_USB 0 -+#define WZRHPG300NH_GPIO_LED_DIAG 1 -+#define WZRHPG300NH_GPIO_LED_WIRELESS 6 -+#define WZRHPG300NH_GPIO_LED_SECURITY 17 -+#define WZRHPG300NH_GPIO_LED_ROUTER 18 -+ -+#define WZRHPG300NH_GPIO_RTL8366_SDA 19 -+#define WZRHPG300NH_GPIO_RTL8366_SCK 20 -+ -+#define WZRHPG300NH_GPIO_74HC153_S0 9 -+#define WZRHPG300NH_GPIO_74HC153_S1 11 -+#define WZRHPG300NH_GPIO_74HC153_1Y 12 -+#define WZRHPG300NH_GPIO_74HC153_2Y 14 -+ -+#define WZRHPG300NH_GPIO_EXP_BASE 32 -+#define WZRHPG300NH_GPIO_BTN_AOSS (WZRHPG300NH_GPIO_EXP_BASE + 0) -+#define WZRHPG300NH_GPIO_BTN_RESET (WZRHPG300NH_GPIO_EXP_BASE + 1) -+#define WZRHPG300NH_GPIO_BTN_ROUTER_ON (WZRHPG300NH_GPIO_EXP_BASE + 2) -+#define WZRHPG300NH_GPIO_BTN_QOS_ON (WZRHPG300NH_GPIO_EXP_BASE + 3) -+#define WZRHPG300NH_GPIO_BTN_USB (WZRHPG300NH_GPIO_EXP_BASE + 5) -+#define WZRHPG300NH_GPIO_BTN_ROUTER_AUTO (WZRHPG300NH_GPIO_EXP_BASE + 6) -+#define WZRHPG300NH_GPIO_BTN_QOS_OFF (WZRHPG300NH_GPIO_EXP_BASE + 7) -+ -+#define WZRHPG300NH_BUTTONS_POLL_INTERVAL 20 -+ -+#define WZRHPG300NH_MAC_OFFSET 0x20c -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition wzrhpg300nh_flash_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x0040000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "u-boot-env", -+ .offset = 0x0040000, -+ .size = 0x0020000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "kernel", -+ .offset = 0x0060000, -+ .size = 0x0100000, -+ }, { -+ .name = "rootfs", -+ .offset = 0x0160000, -+ .size = 0x1e60000, -+ }, { -+ .name = "user_property", -+ .offset = 0x1fc0000, -+ .size = 0x0020000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "art", -+ .offset = 0x1fe0000, -+ .size = 0x0020000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "firmware", -+ .offset = 0x0060000, -+ .size = 0x1f60000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct ar91xx_flash_platform_data wzrhpg300nh_flash_data = { -+ .width = 2, -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = wzrhpg300nh_flash_partitions, -+ .nr_parts = ARRAY_SIZE(wzrhpg300nh_flash_partitions), -+#endif -+}; -+ -+#define WZRHPG300NH_FLASH_BASE 0x1e000000 -+#define WZRHPG300NH_FLASH_SIZE (32 * 1024 * 1024) -+ -+static struct resource wzrhpg300nh_flash_resources[] = { -+ [0] = { -+ .start = WZRHPG300NH_FLASH_BASE, -+ .end = WZRHPG300NH_FLASH_BASE + WZRHPG300NH_FLASH_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+}; -+ -+static struct platform_device wzrhpg300nh_flash_device = { -+ .name = "ar91xx-flash", -+ .id = -1, -+ .resource = wzrhpg300nh_flash_resources, -+ .num_resources = ARRAY_SIZE(wzrhpg300nh_flash_resources), -+ .dev = { -+ .platform_data = &wzrhpg300nh_flash_data, -+ } -+}; -+ -+static struct gpio_led wzrhpg300nh_leds_gpio[] __initdata = { -+ { -+ .name = "wzr-hp-g300nh:orange:security", -+ .gpio = WZRHPG300NH_GPIO_LED_SECURITY, -+ .active_low = 1, -+ }, { -+ .name = "wzr-hp-g300nh:green:wireless", -+ .gpio = WZRHPG300NH_GPIO_LED_WIRELESS, -+ .active_low = 1, -+ }, { -+ .name = "wzr-hp-g300nh:green:router", -+ .gpio = WZRHPG300NH_GPIO_LED_ROUTER, -+ .active_low = 1, -+ }, { -+ .name = "wzr-hp-g300nh:red:diag", -+ .gpio = WZRHPG300NH_GPIO_LED_DIAG, -+ .active_low = 1, -+ }, { -+ .name = "wzr-hp-g300nh:blue:usb", -+ .gpio = WZRHPG300NH_GPIO_LED_USB, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_button wzrhpg300nh_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = WZRHPG300NH_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "aoss", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = WZRHPG300NH_GPIO_BTN_AOSS, -+ .active_low = 1, -+ }, { -+ .desc = "usb", -+ .type = EV_KEY, -+ .code = BTN_2, -+ .threshold = 3, -+ .gpio = WZRHPG300NH_GPIO_BTN_USB, -+ .active_low = 1, -+ }, { -+ .desc = "qos_on", -+ .type = EV_KEY, -+ .code = BTN_3, -+ .threshold = 3, -+ .gpio = WZRHPG300NH_GPIO_BTN_QOS_ON, -+ .active_low = 0, -+ }, { -+ .desc = "qos_off", -+ .type = EV_KEY, -+ .code = BTN_4, -+ .threshold = 3, -+ .gpio = WZRHPG300NH_GPIO_BTN_QOS_OFF, -+ .active_low = 0, -+ }, { -+ .desc = "router_on", -+ .type = EV_KEY, -+ .code = BTN_5, -+ .threshold = 3, -+ .gpio = WZRHPG300NH_GPIO_BTN_ROUTER_ON, -+ .active_low = 0, -+ }, { -+ .desc = "router_auto", -+ .type = EV_KEY, -+ .code = BTN_6, -+ .threshold = 3, -+ .gpio = WZRHPG300NH_GPIO_BTN_ROUTER_AUTO, -+ .active_low = 0, -+ } -+}; -+ -+static struct nxp_74hc153_platform_data wzrhpg300nh_74hc153_data = { -+ .gpio_base = WZRHPG300NH_GPIO_EXP_BASE, -+ .gpio_pin_s0 = WZRHPG300NH_GPIO_74HC153_S0, -+ .gpio_pin_s1 = WZRHPG300NH_GPIO_74HC153_S1, -+ .gpio_pin_1y = WZRHPG300NH_GPIO_74HC153_1Y, -+ .gpio_pin_2y = WZRHPG300NH_GPIO_74HC153_2Y, -+}; -+ -+static struct platform_device wzrhpg300nh_74hc153_device = { -+ .name = NXP_74HC153_DRIVER_NAME, -+ .id = -1, -+ .dev = { -+ .platform_data = &wzrhpg300nh_74hc153_data, -+ } -+}; -+ -+static struct rtl8366s_platform_data wzrhpg300nh_rtl8366s_data = { -+ .gpio_sda = WZRHPG300NH_GPIO_RTL8366_SDA, -+ .gpio_sck = WZRHPG300NH_GPIO_RTL8366_SCK, -+}; -+ -+static struct platform_device wzrhpg300nh_rtl8366s_device = { -+ .name = RTL8366S_DRIVER_NAME, -+ .id = -1, -+ .dev = { -+ .platform_data = &wzrhpg300nh_rtl8366s_data, -+ } -+}; -+ -+static void __init wzrhpg300nh_setup(void) -+{ -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ -+ ar71xx_set_mac_base(eeprom + WZRHPG300NH_MAC_OFFSET); -+ -+ ar71xx_eth0_pll_data.pll_1000 = 0x1e000100; -+ ar71xx_eth0_data.mii_bus_dev = &wzrhpg300nh_rtl8366s_device.dev; -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth0_data.speed = SPEED_1000; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_eth1_pll_data.pll_1000 = 0x1e000100; -+ ar71xx_eth1_data.mii_bus_dev = &wzrhpg300nh_rtl8366s_device.dev; -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth1_data.phy_mask = 0x10; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_usb(); -+ ar913x_add_device_wmac(eeprom, NULL); -+ -+ platform_device_register(&wzrhpg300nh_74hc153_device); -+ platform_device_register(&wzrhpg300nh_flash_device); -+ platform_device_register(&wzrhpg300nh_rtl8366s_device); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(wzrhpg300nh_leds_gpio), -+ wzrhpg300nh_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, WZRHPG300NH_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(wzrhpg300nh_gpio_buttons), -+ wzrhpg300nh_gpio_buttons); -+ -+} -+ -+MIPS_MACHINE(AR71XX_MACH_WZR_HP_G300NH, "WZR-HP-G300NH", -+ "Buffalo WZR-HP-G300NH", wzrhpg300nh_setup); -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/machtype.h linux-2.6.37/arch/mips/ar71xx/machtype.h ---- linux-2.6.37.orig/arch/mips/ar71xx/machtype.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/machtype.h 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,60 @@ -+/* -+ * Atheros AR71xx machine type definitions -+ * -+ * Copyright (C) 2008-2010 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_MACHTYPE_H -+#define _AR71XX_MACHTYPE_H -+ -+#include -+ -+enum ar71xx_mach_type { -+ AR71XX_MACH_GENERIC = 0, -+ AR71XX_MACH_AP81, /* Atheros AP81 */ -+ AR71XX_MACH_AP83, /* Atheros AP83 */ -+ AR71XX_MACH_AW_NR580, /* AzureWave AW-NR580 */ -+ AR71XX_MACH_DIR_600_A1, /* D-Link DIR-600 rev. A1 */ -+ AR71XX_MACH_DIR_615_C1, /* D-Link DIR-615 rev. C1 */ -+ AR71XX_MACH_DIR_825_B1, /* D-Link DIR-825 rev. B1 */ -+ AR71XX_MACH_RB_411, /* MikroTik RouterBOARD 411/411A/411AH */ -+ AR71XX_MACH_RB_411U, /* MikroTik RouterBOARD 411U */ -+ AR71XX_MACH_RB_433, /* MikroTik RouterBOARD 433/433AH */ -+ AR71XX_MACH_RB_433U, /* MikroTik RouterBOARD 433UAH */ -+ AR71XX_MACH_RB_450, /* MikroTik RouterBOARD 450 */ -+ AR71XX_MACH_RB_450G, /* MikroTik RouterBOARD 450G */ -+ AR71XX_MACH_RB_493, /* Mikrotik RouterBOARD 493/493AH */ -+ AR71XX_MACH_RB_750, /* MikroTik RouterBOARD 750 */ -+ AR71XX_MACH_PB42, /* Atheros PB42 */ -+ AR71XX_MACH_PB44, /* Atheros PB44 */ -+ AR71XX_MACH_PB92, /* Atheros PB92 */ -+ AR71XX_MACH_MZK_W04NU, /* Planex MZK-W04NU */ -+ AR71XX_MACH_MZK_W300NH, /* Planex MZK-W300NH */ -+ AR71XX_MACH_NBG460N, /* Zyxel NBG460N/550N/550NH */ -+ AR71XX_MACH_TEW_632BRP, /* TRENDnet TEW-632BRP */ -+ AR71XX_MACH_TL_WR741ND, /* TP-LINK TL-WR741ND */ -+ AR71XX_MACH_TL_WR841N_V1, /* TP-LINK TL-WR841N v1 */ -+ AR71XX_MACH_TL_WR941ND, /* TP-LINK TL-WR941ND */ -+ AR71XX_MACH_TL_WR1043ND, /* TP-LINK TL-WR1041ND */ -+ AR71XX_MACH_UBNT_LSSR71, /* Ubiquiti LS-SR71 */ -+ AR71XX_MACH_UBNT_LSX, /* Ubiquiti LSX */ -+ AR71XX_MACH_UBNT_RS, /* Ubiquiti RouterStation */ -+ AR71XX_MACH_UBNT_AR71XX, /* Ubiquiti AR71xx-based board */ -+ AR71XX_MACH_UBNT_RSPRO, /* Ubiquiti RouterStation Pro */ -+ AR71XX_MACH_UBNT_BULLET_M, /* Ubiquiti Bullet M */ -+ AR71XX_MACH_UBNT_ROCKET_M, /* Ubiquiti Rocket M */ -+ AR71XX_MACH_UBNT_NANO_M, /* Ubiquiti NanoStation M */ -+ AR71XX_MACH_WNDR3700, /* NETGEAR WNDR3700 */ -+ AR71XX_MACH_WNR2000, /* NETGEAR WNR2000 */ -+ AR71XX_MACH_WP543, /* Compex WP543 */ -+ AR71XX_MACH_WRT160NL, /* Linksys WRT160NL */ -+ AR71XX_MACH_WRT400N, /* Linksys WRT400N */ -+ AR71XX_MACH_WZR_HP_G300NH, /* Buffalo WZR-HP-G300NH */ -+}; -+ -+#endif /* _AR71XX_MACHTYPE_H */ -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/nvram.c linux-2.6.37/arch/mips/ar71xx/nvram.c ---- linux-2.6.37.orig/arch/mips/ar71xx/nvram.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/nvram.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,75 @@ -+/* -+ * Atheros AR71xx minimal nvram support -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include "nvram.h" -+ -+char *nvram_find_var(const char *name, const char *buf, unsigned buf_len) -+{ -+ unsigned len = strlen(name); -+ char *cur, *last; -+ -+ if (buf_len == 0 || len == 0) -+ return NULL; -+ -+ if (buf_len < len) -+ return NULL; -+ -+ if (len == 1) -+ return memchr(buf, (int) *name, buf_len); -+ -+ last = (char *) buf + buf_len - len; -+ for (cur = (char *) buf; cur <= last; cur++) -+ if (cur[0] == name[0] && memcmp(cur, name, len) == 0) -+ return cur + len; -+ -+ return NULL; -+} -+ -+int nvram_parse_mac_addr(const char *nvram, unsigned nvram_len, -+ const char *name, char *mac) -+{ -+ char *buf; -+ char *mac_str; -+ int ret; -+ int t; -+ -+ buf = vmalloc(nvram_len); -+ if (!buf) -+ return -ENOMEM; -+ -+ memcpy(buf, nvram, nvram_len); -+ buf[nvram_len - 1] = '\0'; -+ -+ mac_str = nvram_find_var(name, buf, nvram_len); -+ if (!mac_str) { -+ ret = -EINVAL; -+ goto free; -+ } -+ -+ t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", -+ &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]); -+ -+ if (t != 6) { -+ ret = -EINVAL; -+ goto free; -+ } -+ -+ ret = 0; -+ -+ free: -+ vfree(buf); -+ return ret; -+} -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/nvram.h linux-2.6.37/arch/mips/ar71xx/nvram.h ---- linux-2.6.37.orig/arch/mips/ar71xx/nvram.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/nvram.h 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,19 @@ -+/* -+ * Atheros AR71xx minimal nvram support -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_NVRAM_H -+#define _AR71XX_NVRAM_H -+ -+char *nvram_find_var(const char *name, const char *buf, -+ unsigned buf_len) __init; -+int nvram_parse_mac_addr(const char *nvram, unsigned nvram_len, -+ const char *name, char *mac) __init; -+ -+#endif /* _AR71XX_NVRAM_H */ -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/pci.c linux-2.6.37/arch/mips/ar71xx/pci.c ---- linux-2.6.37.orig/arch/mips/ar71xx/pci.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/pci.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,93 @@ -+/* -+ * Atheros AR71xx PCI setup code -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+ -+#include -+ -+#include -+#include -+ -+unsigned ar71xx_pci_nr_irqs __initdata; -+struct ar71xx_pci_irq *ar71xx_pci_irq_map __initdata; -+ -+int (*ar71xx_pci_plat_dev_init)(struct pci_dev *dev); -+ -+static int ar71xx_be_handler(struct pt_regs *regs, int is_fixup) -+{ -+ int err = 0; -+ -+ err = ar71xx_pci_be_handler(is_fixup); -+ -+ return (is_fixup && !err) ? MIPS_BE_FIXUP : MIPS_BE_FATAL; -+} -+ -+int pcibios_plat_dev_init(struct pci_dev *dev) -+{ -+ if (ar71xx_pci_plat_dev_init) -+ return ar71xx_pci_plat_dev_init(dev); -+ -+ return 0; -+} -+ -+int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin) -+{ -+ int ret = 0; -+ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7130: -+ case AR71XX_SOC_AR7141: -+ case AR71XX_SOC_AR7161: -+ ret = ar71xx_pcibios_map_irq(dev, slot, pin); -+ break; -+ -+ case AR71XX_SOC_AR7240: -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ ret = ar724x_pcibios_map_irq(dev, slot, pin); -+ break; -+ -+ default: -+ break; -+ } -+ -+ return ret; -+} -+ -+int __init ar71xx_pci_init(unsigned nr_irqs, struct ar71xx_pci_irq *map) -+{ -+ int ret = 0; -+ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7130: -+ case AR71XX_SOC_AR7141: -+ case AR71XX_SOC_AR7161: -+ board_be_handler = ar71xx_be_handler; -+ ret = ar71xx_pcibios_init(); -+ break; -+ -+ case AR71XX_SOC_AR7240: -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ ret = ar724x_pcibios_init(); -+ break; -+ -+ default: -+ return 0; -+ } -+ -+ ar71xx_pci_nr_irqs = nr_irqs; -+ ar71xx_pci_irq_map = map; -+ -+ return ret; -+} -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/prom.c linux-2.6.37/arch/mips/ar71xx/prom.c ---- linux-2.6.37.orig/arch/mips/ar71xx/prom.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/prom.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,105 @@ -+/* -+ * Atheros AR71xx SoC specific prom routines -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include -+ -+static inline int is_valid_ram_addr(void *addr) -+{ -+ if (((u32) addr > KSEG0) && -+ ((u32) addr < (KSEG0 + AR71XX_MEM_SIZE_MAX))) -+ return 1; -+ -+ if (((u32) addr > KSEG1) && -+ ((u32) addr < (KSEG1 + AR71XX_MEM_SIZE_MAX))) -+ return 1; -+ -+ return 0; -+} -+ -+static void __init ar71xx_prom_append_cmdline(const char *name, -+ const char *value) -+{ -+ char buf[COMMAND_LINE_SIZE]; -+ -+ snprintf(buf, sizeof(buf), " %s=%s", name, value); -+ strlcat(arcs_cmdline, buf, sizeof(arcs_cmdline)); -+} -+ -+static void __init ar71xx_prom_find_env(char **envp, const char *name) -+{ -+ int len = strlen(name); -+ char **p; -+ -+ if (!is_valid_ram_addr(envp)) -+ return; -+ -+ for (p = envp; is_valid_ram_addr(*p); p++) { -+ if (strncmp(name, *p, len) == 0 && (*p)[len] == '=') { -+ ar71xx_prom_append_cmdline(name, *p + len + 1); -+ break; -+ } -+ -+ /* RedBoot env comes in pointer pairs - key, value */ -+ if (strncmp(name, *p, len) == 0 && (*p)[len] == 0) -+ if (is_valid_ram_addr(*(++p))) { -+ ar71xx_prom_append_cmdline(name, *p); -+ break; -+ } -+ } -+} -+ -+static int inline ar71xx_use__image_cmdline(void) { return 0; } -+ -+static __init void ar71xx_prom_init_cmdline(int argc, char **argv) -+{ -+ int i; -+ -+ if (ar71xx_use__image_cmdline()) -+ return; -+ -+ if (!is_valid_ram_addr(argv)) -+ return; -+ -+ for (i = 0; i < argc; i++) -+ if (is_valid_ram_addr(argv[i])) { -+ strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline)); -+ strlcat(arcs_cmdline, argv[i], sizeof(arcs_cmdline)); -+ } -+} -+ -+void __init prom_init(void) -+{ -+ char **envp; -+ -+ printk(KERN_DEBUG "prom: fw_arg0=%08x, fw_arg1=%08x, " -+ "fw_arg2=%08x, fw_arg3=%08x\n", -+ (unsigned int)fw_arg0, (unsigned int)fw_arg1, -+ (unsigned int)fw_arg2, (unsigned int)fw_arg3); -+ -+ -+ ar71xx_prom_init_cmdline(fw_arg0, (char **)fw_arg1); -+ -+ envp = (char **)fw_arg2; -+ ar71xx_prom_find_env(envp, "board"); -+} -+ -+void __init prom_free_prom_memory(void) -+{ -+ /* We do not have to prom memory to free */ -+} -diff -Nur linux-2.6.37.orig/arch/mips/ar71xx/setup.c linux-2.6.37/arch/mips/ar71xx/setup.c ---- linux-2.6.37.orig/arch/mips/ar71xx/setup.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar71xx/setup.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,310 @@ -+/* -+ * Atheros AR71xx SoC specific setup -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+ -+#include -+#include /* for mips_hpt_frequency */ -+#include /* for _machine_{restart,halt} */ -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+ -+#define AR71XX_SYS_TYPE_LEN 64 -+#define AR71XX_BASE_FREQ 40000000 -+#define AR91XX_BASE_FREQ 5000000 -+#define AR724X_BASE_FREQ 5000000 -+ -+u32 ar71xx_cpu_freq; -+EXPORT_SYMBOL_GPL(ar71xx_cpu_freq); -+ -+u32 ar71xx_ahb_freq; -+EXPORT_SYMBOL_GPL(ar71xx_ahb_freq); -+ -+u32 ar71xx_ddr_freq; -+EXPORT_SYMBOL_GPL(ar71xx_ddr_freq); -+ -+enum ar71xx_soc_type ar71xx_soc; -+EXPORT_SYMBOL_GPL(ar71xx_soc); -+ -+static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN]; -+ -+static void ar71xx_restart(char *command) -+{ -+ ar71xx_device_stop(RESET_MODULE_FULL_CHIP); -+ for (;;) -+ if (cpu_wait) -+ cpu_wait(); -+} -+ -+static void ar71xx_halt(void) -+{ -+ while (1) -+ cpu_wait(); -+} -+ -+static void __init ar71xx_detect_mem_size(void) -+{ -+ unsigned long size; -+ -+ for (size = AR71XX_MEM_SIZE_MIN; size < AR71XX_MEM_SIZE_MAX; -+ size <<= 1 ) { -+ if (!memcmp(ar71xx_detect_mem_size, -+ ar71xx_detect_mem_size + size, 1024)) -+ break; -+ } -+ -+ add_memory_region(0, size, BOOT_MEM_RAM); -+} -+ -+static void __init ar71xx_detect_sys_type(void) -+{ -+ char *chip = "????"; -+ u32 id; -+ u32 major; -+ u32 minor; -+ u32 rev = 0; -+ -+ id = ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID); -+ major = id & REV_ID_MAJOR_MASK; -+ -+ switch (major) { -+ case REV_ID_MAJOR_AR71XX: -+ minor = id & AR71XX_REV_ID_MINOR_MASK; -+ rev = id >> AR71XX_REV_ID_REVISION_SHIFT; -+ rev &= AR71XX_REV_ID_REVISION_MASK; -+ switch (minor) { -+ case AR71XX_REV_ID_MINOR_AR7130: -+ ar71xx_soc = AR71XX_SOC_AR7130; -+ chip = "7130"; -+ break; -+ -+ case AR71XX_REV_ID_MINOR_AR7141: -+ ar71xx_soc = AR71XX_SOC_AR7141; -+ chip = "7141"; -+ break; -+ -+ case AR71XX_REV_ID_MINOR_AR7161: -+ ar71xx_soc = AR71XX_SOC_AR7161; -+ chip = "7161"; -+ break; -+ } -+ break; -+ -+ case REV_ID_MAJOR_AR7240: -+ ar71xx_soc = AR71XX_SOC_AR7240; -+ chip = "7240"; -+ rev = (id & AR724X_REV_ID_REVISION_MASK); -+ break; -+ -+ case REV_ID_MAJOR_AR7241: -+ ar71xx_soc = AR71XX_SOC_AR7241; -+ chip = "7241"; -+ rev = (id & AR724X_REV_ID_REVISION_MASK); -+ break; -+ -+ case REV_ID_MAJOR_AR7242: -+ ar71xx_soc = AR71XX_SOC_AR7242; -+ chip = "7242"; -+ rev = (id & AR724X_REV_ID_REVISION_MASK); -+ break; -+ -+ case REV_ID_MAJOR_AR913X: -+ minor = id & AR91XX_REV_ID_MINOR_MASK; -+ rev = id >> AR91XX_REV_ID_REVISION_SHIFT; -+ rev &= AR91XX_REV_ID_REVISION_MASK; -+ switch (minor) { -+ case AR91XX_REV_ID_MINOR_AR9130: -+ ar71xx_soc = AR71XX_SOC_AR9130; -+ chip = "9130"; -+ break; -+ -+ case AR91XX_REV_ID_MINOR_AR9132: -+ ar71xx_soc = AR71XX_SOC_AR9132; -+ chip = "9132"; -+ break; -+ } -+ break; -+ -+ default: -+ panic("ar71xx: unknown chip id:0x%08x\n", id); -+ } -+ -+ sprintf(ar71xx_sys_type, "Atheros AR%s rev %u", chip, rev); -+} -+ -+static void __init ar91xx_detect_sys_frequency(void) -+{ -+ u32 pll; -+ u32 freq; -+ u32 div; -+ -+ pll = ar71xx_pll_rr(AR91XX_PLL_REG_CPU_CONFIG); -+ -+ div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK); -+ freq = div * AR91XX_BASE_FREQ; -+ -+ ar71xx_cpu_freq = freq; -+ -+ div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1; -+ ar71xx_ddr_freq = freq / div; -+ -+ div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2; -+ ar71xx_ahb_freq = ar71xx_cpu_freq / div; -+} -+ -+static void __init ar71xx_detect_sys_frequency(void) -+{ -+ u32 pll; -+ u32 freq; -+ u32 div; -+ -+ pll = ar71xx_pll_rr(AR71XX_PLL_REG_CPU_CONFIG); -+ -+ div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1; -+ freq = div * AR71XX_BASE_FREQ; -+ -+ div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1; -+ ar71xx_cpu_freq = freq / div; -+ -+ div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1; -+ ar71xx_ddr_freq = freq / div; -+ -+ div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2; -+ ar71xx_ahb_freq = ar71xx_cpu_freq / div; -+} -+ -+static void __init ar724x_detect_sys_frequency(void) -+{ -+ u32 pll; -+ u32 freq; -+ u32 div; -+ -+ pll = ar71xx_pll_rr(AR724X_PLL_REG_CPU_CONFIG); -+ -+ div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK); -+ freq = div * AR724X_BASE_FREQ; -+ -+ div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK); -+ freq *= div; -+ -+ ar71xx_cpu_freq = freq; -+ -+ div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1; -+ ar71xx_ddr_freq = freq / div; -+ -+ div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2; -+ ar71xx_ahb_freq = ar71xx_cpu_freq / div; -+} -+ -+static void __init detect_sys_frequency(void) -+{ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7130: -+ case AR71XX_SOC_AR7141: -+ case AR71XX_SOC_AR7161: -+ ar71xx_detect_sys_frequency(); -+ break; -+ -+ case AR71XX_SOC_AR7240: -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ ar724x_detect_sys_frequency(); -+ break; -+ -+ case AR71XX_SOC_AR9130: -+ case AR71XX_SOC_AR9132: -+ ar91xx_detect_sys_frequency(); -+ break; -+ -+ default: -+ BUG(); -+ } -+} -+ -+const char *get_system_type(void) -+{ -+ return ar71xx_sys_type; -+} -+ -+unsigned int __cpuinit get_c0_compare_irq(void) -+{ -+ return CP0_LEGACY_COMPARE_IRQ; -+} -+ -+void __init plat_mem_setup(void) -+{ -+ set_io_port_base(KSEG1); -+ -+ ar71xx_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE, -+ AR71XX_DDR_CTRL_SIZE); -+ -+ ar71xx_pll_base = ioremap_nocache(AR71XX_PLL_BASE, -+ AR71XX_PLL_SIZE); -+ -+ ar71xx_reset_base = ioremap_nocache(AR71XX_RESET_BASE, -+ AR71XX_RESET_SIZE); -+ -+ ar71xx_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE); -+ -+ ar71xx_usb_ctrl_base = ioremap_nocache(AR71XX_USB_CTRL_BASE, -+ AR71XX_USB_CTRL_SIZE); -+ -+ ar71xx_detect_mem_size(); -+ ar71xx_detect_sys_type(); -+ detect_sys_frequency(); -+ -+ printk(KERN_INFO -+ "%s, CPU:%u.%03u MHz, AHB:%u.%03u MHz, DDR:%u.%03u MHz\n", -+ ar71xx_sys_type, -+ ar71xx_cpu_freq / 1000000, (ar71xx_cpu_freq / 1000) % 1000, -+ ar71xx_ahb_freq / 1000000, (ar71xx_ahb_freq / 1000) % 1000, -+ ar71xx_ddr_freq / 1000000, (ar71xx_ddr_freq / 1000) % 1000); -+ -+ _machine_restart = ar71xx_restart; -+ _machine_halt = ar71xx_halt; -+ pm_power_off = ar71xx_halt; -+} -+ -+void __init plat_time_init(void) -+{ -+ mips_hpt_frequency = ar71xx_cpu_freq / 2; -+} -+ -+__setup("board=", mips_machtype_setup); -+ -+static int __init ar71xx_machine_setup(void) -+{ -+ ar71xx_gpio_init(); -+ -+ ar71xx_add_device_uart(); -+ ar71xx_add_device_wdt(); -+ -+ mips_machine_setup(); -+ return 0; -+} -+ -+arch_initcall(ar71xx_machine_setup); -+ -+static void __init ar71xx_generic_init(void) -+{ -+ /* Nothing to do */ -+} -+ -+MIPS_MACHINE(AR71XX_MACH_GENERIC, "Generic", "Generic AR71xx board", -+ ar71xx_generic_init); -diff -Nur linux-2.6.37.orig/arch/mips/include/asm/mach-ar71xx/ar71xx.h linux-2.6.37/arch/mips/include/asm/mach-ar71xx/ar71xx.h ---- linux-2.6.37.orig/arch/mips/include/asm/mach-ar71xx/ar71xx.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/include/asm/mach-ar71xx/ar71xx.h 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,514 @@ -+/* -+ * Atheros AR71xx SoC specific definitions -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef __ASM_MACH_AR71XX_H -+#define __ASM_MACH_AR71XX_H -+ -+#include -+#include -+#include -+#include -+ -+#ifndef __ASSEMBLER__ -+ -+#define AR71XX_PCI_MEM_BASE 0x10000000 -+#define AR71XX_PCI_MEM_SIZE 0x08000000 -+#define AR71XX_APB_BASE 0x18000000 -+#define AR71XX_GE0_BASE 0x19000000 -+#define AR71XX_GE0_SIZE 0x01000000 -+#define AR71XX_GE1_BASE 0x1a000000 -+#define AR71XX_GE1_SIZE 0x01000000 -+#define AR71XX_EHCI_BASE 0x1b000000 -+#define AR71XX_EHCI_SIZE 0x01000000 -+#define AR71XX_OHCI_BASE 0x1c000000 -+#define AR71XX_OHCI_SIZE 0x01000000 -+#define AR7240_OHCI_BASE 0x1b000000 -+#define AR7240_OHCI_SIZE 0x01000000 -+#define AR71XX_SPI_BASE 0x1f000000 -+#define AR71XX_SPI_SIZE 0x01000000 -+ -+#define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000) -+#define AR71XX_DDR_CTRL_SIZE 0x10000 -+#define AR71XX_CPU_BASE (AR71XX_APB_BASE + 0x00010000) -+#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000) -+#define AR71XX_UART_SIZE 0x10000 -+#define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) -+#define AR71XX_USB_CTRL_SIZE 0x10000 -+#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000) -+#define AR71XX_GPIO_SIZE 0x10000 -+#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000) -+#define AR71XX_PLL_SIZE 0x10000 -+#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) -+#define AR71XX_RESET_SIZE 0x10000 -+#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000) -+#define AR71XX_MII_SIZE 0x10000 -+#define AR71XX_SLIC_BASE (AR71XX_APB_BASE + 0x00090000) -+#define AR71XX_SLIC_SIZE 0x10000 -+#define AR71XX_DMA_BASE (AR71XX_APB_BASE + 0x000A0000) -+#define AR71XX_DMA_SIZE 0x10000 -+#define AR71XX_STEREO_BASE (AR71XX_APB_BASE + 0x000B0000) -+#define AR71XX_STEREO_SIZE 0x10000 -+ -+#define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000C0000) -+#define AR724X_PCI_CRP_SIZE 0x100 -+ -+#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000F0000) -+#define AR724X_PCI_CTRL_SIZE 0x100 -+ -+#define AR91XX_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000) -+#define AR91XX_WMAC_SIZE 0x30000 -+ -+#define AR71XX_MEM_SIZE_MIN 0x0200000 -+#define AR71XX_MEM_SIZE_MAX 0x10000000 -+ -+#define AR71XX_CPU_IRQ_BASE 0 -+#define AR71XX_MISC_IRQ_BASE 8 -+#define AR71XX_MISC_IRQ_COUNT 8 -+#define AR71XX_GPIO_IRQ_BASE 16 -+#define AR71XX_GPIO_IRQ_COUNT 32 -+#define AR71XX_PCI_IRQ_BASE 48 -+#define AR71XX_PCI_IRQ_COUNT 8 -+ -+#define AR71XX_CPU_IRQ_IP2 (AR71XX_CPU_IRQ_BASE + 2) -+#define AR71XX_CPU_IRQ_USB (AR71XX_CPU_IRQ_BASE + 3) -+#define AR71XX_CPU_IRQ_GE0 (AR71XX_CPU_IRQ_BASE + 4) -+#define AR71XX_CPU_IRQ_GE1 (AR71XX_CPU_IRQ_BASE + 5) -+#define AR71XX_CPU_IRQ_MISC (AR71XX_CPU_IRQ_BASE + 6) -+#define AR71XX_CPU_IRQ_TIMER (AR71XX_CPU_IRQ_BASE + 7) -+ -+#define AR71XX_MISC_IRQ_TIMER (AR71XX_MISC_IRQ_BASE + 0) -+#define AR71XX_MISC_IRQ_ERROR (AR71XX_MISC_IRQ_BASE + 1) -+#define AR71XX_MISC_IRQ_GPIO (AR71XX_MISC_IRQ_BASE + 2) -+#define AR71XX_MISC_IRQ_UART (AR71XX_MISC_IRQ_BASE + 3) -+#define AR71XX_MISC_IRQ_WDOG (AR71XX_MISC_IRQ_BASE + 4) -+#define AR71XX_MISC_IRQ_PERFC (AR71XX_MISC_IRQ_BASE + 5) -+#define AR71XX_MISC_IRQ_OHCI (AR71XX_MISC_IRQ_BASE + 6) -+#define AR71XX_MISC_IRQ_DMA (AR71XX_MISC_IRQ_BASE + 7) -+ -+#define AR71XX_GPIO_IRQ(_x) (AR71XX_GPIO_IRQ_BASE + (_x)) -+ -+#define AR71XX_PCI_IRQ_DEV0 (AR71XX_PCI_IRQ_BASE + 0) -+#define AR71XX_PCI_IRQ_DEV1 (AR71XX_PCI_IRQ_BASE + 1) -+#define AR71XX_PCI_IRQ_DEV2 (AR71XX_PCI_IRQ_BASE + 2) -+#define AR71XX_PCI_IRQ_CORE (AR71XX_PCI_IRQ_BASE + 4) -+ -+extern u32 ar71xx_ahb_freq; -+extern u32 ar71xx_cpu_freq; -+extern u32 ar71xx_ddr_freq; -+ -+enum ar71xx_soc_type { -+ AR71XX_SOC_UNKNOWN, -+ AR71XX_SOC_AR7130, -+ AR71XX_SOC_AR7141, -+ AR71XX_SOC_AR7161, -+ AR71XX_SOC_AR7240, -+ AR71XX_SOC_AR7241, -+ AR71XX_SOC_AR7242, -+ AR71XX_SOC_AR9130, -+ AR71XX_SOC_AR9132 -+}; -+ -+extern enum ar71xx_soc_type ar71xx_soc; -+ -+/* -+ * PLL block -+ */ -+#define AR71XX_PLL_REG_CPU_CONFIG 0x00 -+#define AR71XX_PLL_REG_SEC_CONFIG 0x04 -+#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10 -+#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14 -+ -+#define AR71XX_PLL_DIV_SHIFT 3 -+#define AR71XX_PLL_DIV_MASK 0x1f -+#define AR71XX_CPU_DIV_SHIFT 16 -+#define AR71XX_CPU_DIV_MASK 0x3 -+#define AR71XX_DDR_DIV_SHIFT 18 -+#define AR71XX_DDR_DIV_MASK 0x3 -+#define AR71XX_AHB_DIV_SHIFT 20 -+#define AR71XX_AHB_DIV_MASK 0x7 -+ -+#define AR71XX_ETH0_PLL_SHIFT 17 -+#define AR71XX_ETH1_PLL_SHIFT 19 -+ -+#define AR724X_PLL_REG_CPU_CONFIG 0x00 -+#define AR724X_PLL_REG_PCIE_CONFIG 0x18 -+ -+#define AR724X_PLL_DIV_SHIFT 0 -+#define AR724X_PLL_DIV_MASK 0x3ff -+#define AR724X_PLL_REF_DIV_SHIFT 10 -+#define AR724X_PLL_REF_DIV_MASK 0xf -+#define AR724X_AHB_DIV_SHIFT 19 -+#define AR724X_AHB_DIV_MASK 0x1 -+#define AR724X_DDR_DIV_SHIFT 22 -+#define AR724X_DDR_DIV_MASK 0x3 -+ -+#define AR91XX_PLL_REG_CPU_CONFIG 0x00 -+#define AR91XX_PLL_REG_ETH_CONFIG 0x04 -+#define AR91XX_PLL_REG_ETH0_INT_CLOCK 0x14 -+#define AR91XX_PLL_REG_ETH1_INT_CLOCK 0x18 -+ -+#define AR91XX_PLL_DIV_SHIFT 0 -+#define AR91XX_PLL_DIV_MASK 0x3ff -+#define AR91XX_DDR_DIV_SHIFT 22 -+#define AR91XX_DDR_DIV_MASK 0x3 -+#define AR91XX_AHB_DIV_SHIFT 19 -+#define AR91XX_AHB_DIV_MASK 0x1 -+ -+#define AR91XX_ETH0_PLL_SHIFT 20 -+#define AR91XX_ETH1_PLL_SHIFT 22 -+ -+extern void __iomem *ar71xx_pll_base; -+ -+static inline void ar71xx_pll_wr(unsigned reg, u32 val) -+{ -+ __raw_writel(val, ar71xx_pll_base + reg); -+} -+ -+static inline u32 ar71xx_pll_rr(unsigned reg) -+{ -+ return __raw_readl(ar71xx_pll_base + reg); -+} -+ -+/* -+ * USB_CONFIG block -+ */ -+#define USB_CTRL_REG_FLADJ 0x00 -+#define USB_CTRL_REG_CONFIG 0x04 -+ -+extern void __iomem *ar71xx_usb_ctrl_base; -+ -+static inline void ar71xx_usb_ctrl_wr(unsigned reg, u32 val) -+{ -+ __raw_writel(val, ar71xx_usb_ctrl_base + reg); -+} -+ -+static inline u32 ar71xx_usb_ctrl_rr(unsigned reg) -+{ -+ return __raw_readl(ar71xx_usb_ctrl_base + reg); -+} -+ -+/* -+ * GPIO block -+ */ -+#define GPIO_REG_OE 0x00 -+#define GPIO_REG_IN 0x04 -+#define GPIO_REG_OUT 0x08 -+#define GPIO_REG_SET 0x0c -+#define GPIO_REG_CLEAR 0x10 -+#define GPIO_REG_INT_MODE 0x14 -+#define GPIO_REG_INT_TYPE 0x18 -+#define GPIO_REG_INT_POLARITY 0x1c -+#define GPIO_REG_INT_PENDING 0x20 -+#define GPIO_REG_INT_ENABLE 0x24 -+#define GPIO_REG_FUNC 0x28 -+ -+#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17) -+#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16) -+#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13) -+#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12) -+#define AR71XX_GPIO_FUNC_UART_EN BIT(8) -+#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4) -+#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0) -+ -+#define AR71XX_GPIO_COUNT 16 -+ -+#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19) -+#define AR724X_GPIO_FUNC_SPI_EN BIT(18) -+#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14) -+#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13) -+#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12) -+#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11) -+#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10) -+#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9) -+#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8) -+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) -+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) -+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) -+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) -+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) -+#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) -+#define AR724X_GPIO_FUNC_UART_EN BIT(1) -+#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0) -+ -+#define AR724X_GPIO_COUNT 18 -+ -+#define AR91XX_GPIO_FUNC_WMAC_LED_EN BIT(22) -+#define AR91XX_GPIO_FUNC_EXP_PORT_CS_EN BIT(21) -+#define AR91XX_GPIO_FUNC_I2S_REFCLKEN BIT(20) -+#define AR91XX_GPIO_FUNC_I2S_MCKEN BIT(19) -+#define AR91XX_GPIO_FUNC_I2S1_EN BIT(18) -+#define AR91XX_GPIO_FUNC_I2S0_EN BIT(17) -+#define AR91XX_GPIO_FUNC_SLIC_EN BIT(16) -+#define AR91XX_GPIO_FUNC_UART_RTSCTS_EN BIT(9) -+#define AR91XX_GPIO_FUNC_UART_EN BIT(8) -+#define AR91XX_GPIO_FUNC_USB_CLK_EN BIT(4) -+ -+#define AR91XX_GPIO_COUNT 22 -+ -+extern void __iomem *ar71xx_gpio_base; -+ -+static inline void ar71xx_gpio_wr(unsigned reg, u32 value) -+{ -+ __raw_writel(value, ar71xx_gpio_base + reg); -+} -+ -+static inline u32 ar71xx_gpio_rr(unsigned reg) -+{ -+ return __raw_readl(ar71xx_gpio_base + reg); -+} -+ -+void ar71xx_gpio_init(void) __init; -+void ar71xx_gpio_function_enable(u32 mask); -+void ar71xx_gpio_function_disable(u32 mask); -+void ar71xx_gpio_function_setup(u32 set, u32 clear); -+ -+/* -+ * DDR_CTRL block -+ */ -+#define AR71XX_DDR_REG_PCI_WIN0 0x7c -+#define AR71XX_DDR_REG_PCI_WIN1 0x80 -+#define AR71XX_DDR_REG_PCI_WIN2 0x84 -+#define AR71XX_DDR_REG_PCI_WIN3 0x88 -+#define AR71XX_DDR_REG_PCI_WIN4 0x8c -+#define AR71XX_DDR_REG_PCI_WIN5 0x90 -+#define AR71XX_DDR_REG_PCI_WIN6 0x94 -+#define AR71XX_DDR_REG_PCI_WIN7 0x98 -+#define AR71XX_DDR_REG_FLUSH_GE0 0x9c -+#define AR71XX_DDR_REG_FLUSH_GE1 0xa0 -+#define AR71XX_DDR_REG_FLUSH_USB 0xa4 -+#define AR71XX_DDR_REG_FLUSH_PCI 0xa8 -+ -+#define AR724X_DDR_REG_FLUSH_GE0 0x7c -+#define AR724X_DDR_REG_FLUSH_GE1 0x80 -+#define AR724X_DDR_REG_FLUSH_USB 0x84 -+#define AR724X_DDR_REG_FLUSH_PCIE 0x88 -+ -+#define AR91XX_DDR_REG_FLUSH_GE0 0x7c -+#define AR91XX_DDR_REG_FLUSH_GE1 0x80 -+#define AR91XX_DDR_REG_FLUSH_USB 0x84 -+#define AR91XX_DDR_REG_FLUSH_WMAC 0x88 -+ -+#define PCI_WIN0_OFFS 0x10000000 -+#define PCI_WIN1_OFFS 0x11000000 -+#define PCI_WIN2_OFFS 0x12000000 -+#define PCI_WIN3_OFFS 0x13000000 -+#define PCI_WIN4_OFFS 0x14000000 -+#define PCI_WIN5_OFFS 0x15000000 -+#define PCI_WIN6_OFFS 0x16000000 -+#define PCI_WIN7_OFFS 0x07000000 -+ -+extern void __iomem *ar71xx_ddr_base; -+ -+static inline void ar71xx_ddr_wr(unsigned reg, u32 val) -+{ -+ __raw_writel(val, ar71xx_ddr_base + reg); -+} -+ -+static inline u32 ar71xx_ddr_rr(unsigned reg) -+{ -+ return __raw_readl(ar71xx_ddr_base + reg); -+} -+ -+void ar71xx_ddr_flush(u32 reg); -+ -+/* -+ * PCI block -+ */ -+#define AR71XX_PCI_CFG_BASE (AR71XX_PCI_MEM_BASE + PCI_WIN7_OFFS + 0x10000) -+#define AR71XX_PCI_CFG_SIZE 0x100 -+ -+#define PCI_REG_CRP_AD_CBE 0x00 -+#define PCI_REG_CRP_WRDATA 0x04 -+#define PCI_REG_CRP_RDDATA 0x08 -+#define PCI_REG_CFG_AD 0x0c -+#define PCI_REG_CFG_CBE 0x10 -+#define PCI_REG_CFG_WRDATA 0x14 -+#define PCI_REG_CFG_RDDATA 0x18 -+#define PCI_REG_PCI_ERR 0x1c -+#define PCI_REG_PCI_ERR_ADDR 0x20 -+#define PCI_REG_AHB_ERR 0x24 -+#define PCI_REG_AHB_ERR_ADDR 0x28 -+ -+#define PCI_CRP_CMD_WRITE 0x00010000 -+#define PCI_CRP_CMD_READ 0x00000000 -+#define PCI_CFG_CMD_READ 0x0000000a -+#define PCI_CFG_CMD_WRITE 0x0000000b -+ -+#define PCI_IDSEL_ADL_START 17 -+ -+#define AR724X_PCI_CFG_BASE (AR71XX_PCI_MEM_BASE + 0x4000000) -+#define AR724X_PCI_CFG_SIZE 0x1000 -+ -+#define AR724X_PCI_REG_APP 0x00 -+#define AR724X_PCI_REG_RESET 0x18 -+#define AR724X_PCI_REG_INT_STATUS 0x4c -+#define AR724X_PCI_REG_INT_MASK 0x50 -+ -+#define AR724X_PCI_APP_LTSSM_ENABLE BIT(0) -+#define AR724X_PCI_RESET_LINK_UP BIT(0) -+ -+#define AR724X_PCI_INT_DEV0 BIT(14) -+ -+/* -+ * RESET block -+ */ -+#define AR71XX_RESET_REG_TIMER 0x00 -+#define AR71XX_RESET_REG_TIMER_RELOAD 0x04 -+#define AR71XX_RESET_REG_WDOG_CTRL 0x08 -+#define AR71XX_RESET_REG_WDOG 0x0c -+#define AR71XX_RESET_REG_MISC_INT_STATUS 0x10 -+#define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14 -+#define AR71XX_RESET_REG_PCI_INT_STATUS 0x18 -+#define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c -+#define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20 -+#define AR71XX_RESET_REG_RESET_MODULE 0x24 -+#define AR71XX_RESET_REG_PERFC_CTRL 0x2c -+#define AR71XX_RESET_REG_PERFC0 0x30 -+#define AR71XX_RESET_REG_PERFC1 0x34 -+#define AR71XX_RESET_REG_REV_ID 0x90 -+ -+#define AR91XX_RESET_REG_GLOBAL_INT_STATUS 0x18 -+#define AR91XX_RESET_REG_RESET_MODULE 0x1c -+#define AR91XX_RESET_REG_PERF_CTRL 0x20 -+#define AR91XX_RESET_REG_PERFC0 0x24 -+#define AR91XX_RESET_REG_PERFC1 0x28 -+ -+#define AR724X_RESET_REG_RESET_MODULE 0x1c -+ -+#define WDOG_CTRL_LAST_RESET BIT(31) -+#define WDOG_CTRL_ACTION_MASK 3 -+#define WDOG_CTRL_ACTION_NONE 0 /* no action */ -+#define WDOG_CTRL_ACTION_GPI 1 /* general purpose interrupt */ -+#define WDOG_CTRL_ACTION_NMI 2 /* NMI */ -+#define WDOG_CTRL_ACTION_FCR 3 /* full chip reset */ -+ -+#define MISC_INT_DMA BIT(7) -+#define MISC_INT_OHCI BIT(6) -+#define MISC_INT_PERFC BIT(5) -+#define MISC_INT_WDOG BIT(4) -+#define MISC_INT_UART BIT(3) -+#define MISC_INT_GPIO BIT(2) -+#define MISC_INT_ERROR BIT(1) -+#define MISC_INT_TIMER BIT(0) -+ -+#define PCI_INT_CORE BIT(4) -+#define PCI_INT_DEV2 BIT(2) -+#define PCI_INT_DEV1 BIT(1) -+#define PCI_INT_DEV0 BIT(0) -+ -+#define RESET_MODULE_EXTERNAL BIT(28) -+#define RESET_MODULE_FULL_CHIP BIT(24) -+#define RESET_MODULE_AMBA2WMAC BIT(22) -+#define RESET_MODULE_CPU_NMI BIT(21) -+#define RESET_MODULE_CPU_COLD BIT(20) -+#define RESET_MODULE_DMA BIT(19) -+#define RESET_MODULE_SLIC BIT(18) -+#define RESET_MODULE_STEREO BIT(17) -+#define RESET_MODULE_DDR BIT(16) -+#define RESET_MODULE_GE1_MAC BIT(13) -+#define RESET_MODULE_GE1_PHY BIT(12) -+#define RESET_MODULE_USBSUS_OVERRIDE BIT(10) -+#define RESET_MODULE_GE0_MAC BIT(9) -+#define RESET_MODULE_GE0_PHY BIT(8) -+#define RESET_MODULE_USB_OHCI_DLL BIT(6) -+#define RESET_MODULE_USB_HOST BIT(5) -+#define RESET_MODULE_USB_PHY BIT(4) -+#define RESET_MODULE_USB_OHCI_DLL_7240 BIT(3) -+#define RESET_MODULE_PCI_BUS BIT(1) -+#define RESET_MODULE_PCI_CORE BIT(0) -+ -+#define AR724X_RESET_GE1_MDIO BIT(23) -+#define AR724X_RESET_GE0_MDIO BIT(22) -+#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10) -+#define AR724X_RESET_PCIE_PHY BIT(7) -+#define AR724X_RESET_PCIE BIT(6) -+ -+#define REV_ID_MAJOR_MASK 0xfff0 -+#define REV_ID_MAJOR_AR71XX 0x00a0 -+#define REV_ID_MAJOR_AR913X 0x00b0 -+#define REV_ID_MAJOR_AR7240 0x00c0 -+#define REV_ID_MAJOR_AR7241 0x0100 -+#define REV_ID_MAJOR_AR7242 0x1100 -+ -+#define AR71XX_REV_ID_MINOR_MASK 0x3 -+#define AR71XX_REV_ID_MINOR_AR7130 0x0 -+#define AR71XX_REV_ID_MINOR_AR7141 0x1 -+#define AR71XX_REV_ID_MINOR_AR7161 0x2 -+#define AR71XX_REV_ID_REVISION_MASK 0x3 -+#define AR71XX_REV_ID_REVISION_SHIFT 2 -+ -+#define AR91XX_REV_ID_MINOR_MASK 0x3 -+#define AR91XX_REV_ID_MINOR_AR9130 0x0 -+#define AR91XX_REV_ID_MINOR_AR9132 0x1 -+#define AR91XX_REV_ID_REVISION_MASK 0x3 -+#define AR91XX_REV_ID_REVISION_SHIFT 2 -+ -+#define AR724X_REV_ID_REVISION_MASK 0x3 -+ -+extern void __iomem *ar71xx_reset_base; -+ -+static inline void ar71xx_reset_wr(unsigned reg, u32 val) -+{ -+ __raw_writel(val, ar71xx_reset_base + reg); -+} -+ -+static inline u32 ar71xx_reset_rr(unsigned reg) -+{ -+ return __raw_readl(ar71xx_reset_base + reg); -+} -+ -+void ar71xx_device_stop(u32 mask); -+void ar71xx_device_start(u32 mask); -+int ar71xx_device_stopped(u32 mask); -+ -+/* -+ * SPI block -+ */ -+#define SPI_REG_FS 0x00 /* Function Select */ -+#define SPI_REG_CTRL 0x04 /* SPI Control */ -+#define SPI_REG_IOC 0x08 /* SPI I/O Control */ -+#define SPI_REG_RDS 0x0c /* Read Data Shift */ -+ -+#define SPI_FS_GPIO BIT(0) /* Enable GPIO mode */ -+ -+#define SPI_CTRL_RD BIT(6) /* Remap Disable */ -+#define SPI_CTRL_DIV_MASK 0x3f -+ -+#define SPI_IOC_DO BIT(0) /* Data Out pin */ -+#define SPI_IOC_CLK BIT(8) /* CLK pin */ -+#define SPI_IOC_CS(n) BIT(16 + (n)) -+#define SPI_IOC_CS0 SPI_IOC_CS(0) -+#define SPI_IOC_CS1 SPI_IOC_CS(1) -+#define SPI_IOC_CS2 SPI_IOC_CS(2) -+#define SPI_IOC_CS_ALL (SPI_IOC_CS0 | SPI_IOC_CS1 | SPI_IOC_CS2) -+ -+void ar71xx_flash_acquire(void); -+void ar71xx_flash_release(void); -+ -+/* -+ * MII_CTRL block -+ */ -+#define MII_REG_MII0_CTRL 0x00 -+#define MII_REG_MII1_CTRL 0x04 -+ -+#define MII0_CTRL_IF_GMII 0 -+#define MII0_CTRL_IF_MII 1 -+#define MII0_CTRL_IF_RGMII 2 -+#define MII0_CTRL_IF_RMII 3 -+ -+#define MII1_CTRL_IF_RGMII 0 -+#define MII1_CTRL_IF_RMII 1 -+ -+#endif /* __ASSEMBLER__ */ -+ -+#endif /* __ASM_MACH_AR71XX_H */ -diff -Nur linux-2.6.37.orig/arch/mips/include/asm/mach-ar71xx/ar91xx_flash.h linux-2.6.37/arch/mips/include/asm/mach-ar71xx/ar91xx_flash.h ---- linux-2.6.37.orig/arch/mips/include/asm/mach-ar71xx/ar91xx_flash.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/include/asm/mach-ar71xx/ar91xx_flash.h 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,26 @@ -+/* -+ * AR91xx parallel flash driver platform data definitions -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef __AR91XX_FLASH_H -+#define __AR91XX_FLASH_H -+ -+struct mtd_partition; -+ -+struct ar91xx_flash_platform_data { -+ unsigned int width; -+ u8 is_shared:1; -+#ifdef CONFIG_MTD_PARTITIONS -+ unsigned int nr_parts; -+ struct mtd_partition *parts; -+#endif -+}; -+ -+#endif /* __AR91XX_FLASH_H */ -diff -Nur linux-2.6.37.orig/arch/mips/include/asm/mach-ar71xx/cpu-feature-overrides.h linux-2.6.37/arch/mips/include/asm/mach-ar71xx/cpu-feature-overrides.h ---- linux-2.6.37.orig/arch/mips/include/asm/mach-ar71xx/cpu-feature-overrides.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/include/asm/mach-ar71xx/cpu-feature-overrides.h 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,56 @@ -+/* -+ * Atheros AR71xx specific CPU feature overrides -+ * -+ * Copyright (C) 2008 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This file was derived from: include/asm-mips/cpu-features.h -+ * Copyright (C) 2003, 2004 Ralf Baechle -+ * Copyright (C) 2004 Maciej W. Rozycki -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ */ -+#ifndef __ASM_MACH_AR71XX_CPU_FEATURE_OVERRIDES_H -+#define __ASM_MACH_AR71XX_CPU_FEATURE_OVERRIDES_H -+ -+#define cpu_has_tlb 1 -+#define cpu_has_4kex 1 -+#define cpu_has_3k_cache 0 -+#define cpu_has_4k_cache 1 -+#define cpu_has_tx39_cache 0 -+#define cpu_has_sb1_cache 0 -+#define cpu_has_fpu 0 -+#define cpu_has_32fpr 0 -+#define cpu_has_counter 1 -+#define cpu_has_watch 1 -+#define cpu_has_divec 1 -+ -+#define cpu_has_prefetch 1 -+#define cpu_has_ejtag 1 -+#define cpu_has_llsc 1 -+ -+#define cpu_has_mips16 1 -+#define cpu_has_mdmx 0 -+#define cpu_has_mips3d 0 -+#define cpu_has_smartmips 0 -+ -+#define cpu_has_mips32r1 1 -+#define cpu_has_mips32r2 1 -+#define cpu_has_mips64r1 0 -+#define cpu_has_mips64r2 0 -+ -+#define cpu_has_dsp 0 -+#define cpu_has_mipsmt 0 -+ -+#define cpu_has_64bits 0 -+#define cpu_has_64bit_zero_reg 0 -+#define cpu_has_64bit_gp_regs 0 -+#define cpu_has_64bit_addresses 0 -+ -+#define cpu_dcache_line_size() 32 -+#define cpu_icache_line_size() 32 -+ -+#endif /* __ASM_MACH_AR71XX_CPU_FEATURE_OVERRIDES_H */ -diff -Nur linux-2.6.37.orig/arch/mips/include/asm/mach-ar71xx/gpio.h linux-2.6.37/arch/mips/include/asm/mach-ar71xx/gpio.h ---- linux-2.6.37.orig/arch/mips/include/asm/mach-ar71xx/gpio.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/include/asm/mach-ar71xx/gpio.h 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,53 @@ -+/* -+ * Atheros AR71xx GPIO API definitions -+ * -+ * Copyright (C) 2008 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ */ -+ -+#ifndef __ASM_MACH_AR71XX_GPIO_H -+#define __ASM_MACH_AR71XX_GPIO_H -+ -+#define ARCH_NR_GPIOS 64 -+#include -+ -+#include -+ -+extern unsigned long ar71xx_gpio_count; -+extern void __ar71xx_gpio_set_value(unsigned gpio, int value); -+extern int __ar71xx_gpio_get_value(unsigned gpio); -+ -+static inline int gpio_to_irq(unsigned gpio) -+{ -+ return AR71XX_GPIO_IRQ(gpio); -+} -+ -+static inline int irq_to_gpio(unsigned irq) -+{ -+ return irq - AR71XX_GPIO_IRQ_BASE; -+} -+ -+static inline int gpio_get_value(unsigned gpio) -+{ -+ if (gpio < ar71xx_gpio_count) -+ return __ar71xx_gpio_get_value(gpio); -+ -+ return __gpio_get_value(gpio); -+} -+ -+static inline void gpio_set_value(unsigned gpio, int value) -+{ -+ if (gpio < ar71xx_gpio_count) -+ __ar71xx_gpio_set_value(gpio, value); -+ else -+ __gpio_set_value(gpio, value); -+} -+ -+#define gpio_cansleep __gpio_cansleep -+ -+#endif /* __ASM_MACH_AR71XX_GPIO_H */ -diff -Nur linux-2.6.37.orig/arch/mips/include/asm/mach-ar71xx/irq.h linux-2.6.37/arch/mips/include/asm/mach-ar71xx/irq.h ---- linux-2.6.37.orig/arch/mips/include/asm/mach-ar71xx/irq.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/include/asm/mach-ar71xx/irq.h 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,17 @@ -+/* -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+#ifndef __ASM_MACH_AR71XX_IRQ_H -+#define __ASM_MACH_AR71XX_IRQ_H -+ -+#define MIPS_CPU_IRQ_BASE 0 -+#define NR_IRQS 56 -+ -+#include_next -+ -+#endif /* __ASM_MACH_AR71XX_IRQ_H */ -diff -Nur linux-2.6.37.orig/arch/mips/include/asm/mach-ar71xx/kernel-entry-init.h linux-2.6.37/arch/mips/include/asm/mach-ar71xx/kernel-entry-init.h ---- linux-2.6.37.orig/arch/mips/include/asm/mach-ar71xx/kernel-entry-init.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/include/asm/mach-ar71xx/kernel-entry-init.h 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,32 @@ -+/* -+ * Atheros AR71xx specific kernel entry setup -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ */ -+#ifndef __ASM_MACH_AR71XX_KERNEL_ENTRY_H -+#define __ASM_MACH_AR71XX_KERNEL_ENTRY_H -+ -+ /* -+ * Some bootloaders set the 'Kseg0 coherency algorithm' to -+ * 'Cacheable, noncoherent, write-through, no write allocate' -+ * and this cause performance issues. Let's go and change it to -+ * 'Cacheable, noncoherent, write-back, write allocate' -+ */ -+ .macro kernel_entry_setup -+ mfc0 t0, CP0_CONFIG -+ li t1, ~CONF_CM_CMASK -+ and t0, t1 -+ ori t0, CONF_CM_CACHABLE_NONCOHERENT -+ mtc0 t0, CP0_CONFIG -+ nop -+ .endm -+ -+ .macro smp_slave_setup -+ .endm -+ -+#endif /* __ASM_MACH_AR71XX_KERNEL_ENTRY_H */ -diff -Nur linux-2.6.37.orig/arch/mips/include/asm/mach-ar71xx/mach-rb750.h linux-2.6.37/arch/mips/include/asm/mach-ar71xx/mach-rb750.h ---- linux-2.6.37.orig/arch/mips/include/asm/mach-ar71xx/mach-rb750.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/include/asm/mach-ar71xx/mach-rb750.h 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,66 @@ -+/* -+ * MikroTik RouterBOARD 750 definitions -+ * -+ * Copyright (C) 2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+#ifndef _MACH_RB750_H -+#define _MACH_RB750_H -+ -+#include -+ -+#define RB750_GPIO_LVC573_LE 0 /* Latch enable on LVC573 */ -+#define RB750_GPIO_NAND_IO0 1 /* NAND I/O 0 */ -+#define RB750_GPIO_NAND_IO1 2 /* NAND I/O 1 */ -+#define RB750_GPIO_NAND_IO2 3 /* NAND I/O 2 */ -+#define RB750_GPIO_NAND_IO3 4 /* NAND I/O 3 */ -+#define RB750_GPIO_NAND_IO4 5 /* NAND I/O 4 */ -+#define RB750_GPIO_NAND_IO5 6 /* NAND I/O 5 */ -+#define RB750_GPIO_NAND_IO6 7 /* NAND I/O 6 */ -+#define RB750_GPIO_NAND_IO7 8 /* NAND I/O 7 */ -+#define RB750_GPIO_NAND_NCE 11 /* NAND Chip Enable (active low) */ -+#define RB750_GPIO_NAND_RDY 12 /* NAND Ready */ -+#define RB750_GPIO_NAND_CLE 14 /* NAND Command Latch Enable */ -+#define RB750_GPIO_NAND_ALE 15 /* NAND Address Latch Enable */ -+#define RB750_GPIO_NAND_NRE 16 /* NAND Read Enable (active low) */ -+#define RB750_GPIO_NAND_NWE 17 /* NAND Write Enable (active low) */ -+ -+#define RB750_GPIO_BTN_RESET 1 -+#define RB750_GPIO_SPI_CS0 2 -+#define RB750_GPIO_LED_ACT 12 -+#define RB750_GPIO_LED_PORT1 13 -+#define RB750_GPIO_LED_PORT2 14 -+#define RB750_GPIO_LED_PORT3 15 -+#define RB750_GPIO_LED_PORT4 16 -+#define RB750_GPIO_LED_PORT5 17 -+ -+#define RB750_LED_ACT BIT(RB750_GPIO_LED_ACT) -+#define RB750_LED_PORT1 BIT(RB750_GPIO_LED_PORT1) -+#define RB750_LED_PORT2 BIT(RB750_GPIO_LED_PORT2) -+#define RB750_LED_PORT3 BIT(RB750_GPIO_LED_PORT3) -+#define RB750_LED_PORT4 BIT(RB750_GPIO_LED_PORT4) -+#define RB750_LED_PORT5 BIT(RB750_GPIO_LED_PORT5) -+ -+#define RB750_LVC573_LE BIT(RB750_GPIO_LVC573_LE) -+ -+#define RB750_LED_BITS (RB750_LED_PORT1 | RB750_LED_PORT2 | RB750_LED_PORT3 | \ -+ RB750_LED_PORT4 | RB750_LED_PORT5 | RB750_LED_ACT) -+ -+struct rb750_led_data { -+ char *name; -+ char *default_trigger; -+ u32 mask; -+ int active_low; -+}; -+ -+struct rb750_led_platform_data { -+ int num_leds; -+ struct rb750_led_data *leds; -+}; -+ -+int rb750_latch_change(u32 mask_clr, u32 mask_set); -+ -+#endif /* _MACH_RB750_H */ -\ No newline at end of file -diff -Nur linux-2.6.37.orig/arch/mips/include/asm/mach-ar71xx/mangle-port.h linux-2.6.37/arch/mips/include/asm/mach-ar71xx/mangle-port.h ---- linux-2.6.37.orig/arch/mips/include/asm/mach-ar71xx/mangle-port.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/include/asm/mach-ar71xx/mangle-port.h 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,45 @@ -+/* -+ * Copyright (C) 2008 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This file was derived from: inlude/asm-mips/mach-generic/mangle-port.h -+ * Copyright (C) 2003, 2004 Ralf Baechle -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef __ASM_MACH_AR71XX_MANGLE_PORT_H -+#define __ASM_MACH_AR71XX_MANGLE_PORT_H -+ -+#define __swizzle_addr_b(port) ((port) ^ 3) -+#define __swizzle_addr_w(port) ((port) ^ 2) -+#define __swizzle_addr_l(port) (port) -+#define __swizzle_addr_q(port) (port) -+ -+#if defined(CONFIG_SWAP_IO_SPACE) -+ -+# define ioswabb(a, x) (x) -+# define __mem_ioswabb(a, x) (x) -+# define ioswabw(a, x) le16_to_cpu(x) -+# define __mem_ioswabw(a, x) (x) -+# define ioswabl(a, x) le32_to_cpu(x) -+# define __mem_ioswabl(a, x) (x) -+# define ioswabq(a, x) le64_to_cpu(x) -+# define __mem_ioswabq(a, x) (x) -+ -+#else -+ -+# define ioswabb(a, x) (x) -+# define __mem_ioswabb(a, x) (x) -+# define ioswabw(a, x) (x) -+# define __mem_ioswabw(a, x) cpu_to_le16(x) -+# define ioswabl(a, x) (x) -+# define __mem_ioswabl(a, x) cpu_to_le32(x) -+# define ioswabq(a, x) (x) -+# define __mem_ioswabq(a, x) cpu_to_le64(x) -+ -+#endif -+ -+#endif /* __ASM_MACH_AR71XX_MANGLE_PORT_H */ -diff -Nur linux-2.6.37.orig/arch/mips/include/asm/mach-ar71xx/pci.h linux-2.6.37/arch/mips/include/asm/mach-ar71xx/pci.h ---- linux-2.6.37.orig/arch/mips/include/asm/mach-ar71xx/pci.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/include/asm/mach-ar71xx/pci.h 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,39 @@ -+/* -+ * Atheros AR71xx SoC specific PCI definitions -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef __ASM_MACH_AR71XX_PCI_H -+#define __ASM_MACH_AR71XX_PCI_H -+ -+struct pci_dev; -+ -+struct ar71xx_pci_irq { -+ int irq; -+ u8 slot; -+ u8 pin; -+}; -+ -+extern int (*ar71xx_pci_plat_dev_init)(struct pci_dev *dev); -+extern unsigned ar71xx_pci_nr_irqs __initdata; -+extern struct ar71xx_pci_irq *ar71xx_pci_irq_map __initdata; -+ -+int ar71xx_pcibios_map_irq(const struct pci_dev *dev, -+ uint8_t slot, uint8_t pin) __init; -+int ar71xx_pcibios_init(void) __init; -+ -+int ar71xx_pci_be_handler(int is_fixup); -+ -+int ar724x_pcibios_map_irq(const struct pci_dev *dev, -+ uint8_t slot, uint8_t pin) __init; -+int ar724x_pcibios_init(void) __init; -+ -+int ar71xx_pci_init(unsigned nr_irqs, struct ar71xx_pci_irq *map) __init; -+ -+#endif /* __ASM_MACH_AR71XX_PCI_H */ -diff -Nur linux-2.6.37.orig/arch/mips/include/asm/mach-ar71xx/platform.h linux-2.6.37/arch/mips/include/asm/mach-ar71xx/platform.h ---- linux-2.6.37.orig/arch/mips/include/asm/mach-ar71xx/platform.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/include/asm/mach-ar71xx/platform.h 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,61 @@ -+/* -+ * Atheros AR71xx SoC specific platform data definitions -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef __ASM_MACH_AR71XX_PLATFORM_H -+#define __ASM_MACH_AR71XX_PLATFORM_H -+ -+#include -+#include -+#include -+#include -+ -+struct ag71xx_platform_data { -+ phy_interface_t phy_if_mode; -+ u32 phy_mask; -+ int speed; -+ int duplex; -+ u32 reset_bit; -+ u32 mii_if; -+ u8 mac_addr[ETH_ALEN]; -+ struct device *mii_bus_dev; -+ -+ u8 has_gbit:1; -+ u8 is_ar91xx:1; -+ u8 is_ar724x:1; -+ u8 has_ar8216:1; -+ -+ void (* ddr_flush)(void); -+ void (* set_pll)(int speed); -+ -+ u32 fifo_cfg1; -+ u32 fifo_cfg2; -+ u32 fifo_cfg3; -+}; -+ -+struct ag71xx_mdio_platform_data { -+ u32 phy_mask; -+ int is_ar7240; -+}; -+ -+struct ar71xx_ehci_platform_data { -+ u8 is_ar91xx; -+}; -+ -+struct ar71xx_spi_platform_data { -+ unsigned bus_num; -+ unsigned num_chipselect; -+ u32 (*get_ioc_base)(u8 chip_select, int cs_high, int is_on); -+}; -+ -+#define AR71XX_SPI_CS_INACTIVE 0 -+#define AR71XX_SPI_CS_ACTIVE 1 -+ -+#endif /* __ASM_MACH_AR71XX_PLATFORM_H */ -diff -Nur linux-2.6.37.orig/arch/mips/include/asm/mach-ar71xx/war.h linux-2.6.37/arch/mips/include/asm/mach-ar71xx/war.h ---- linux-2.6.37.orig/arch/mips/include/asm/mach-ar71xx/war.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/include/asm/mach-ar71xx/war.h 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,25 @@ -+/* -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle -+ */ -+#ifndef __ASM_MACH_AR71XX_WAR_H -+#define __ASM_MACH_AR71XX_WAR_H -+ -+#define R4600_V1_INDEX_ICACHEOP_WAR 0 -+#define R4600_V1_HIT_CACHEOP_WAR 0 -+#define R4600_V2_HIT_CACHEOP_WAR 0 -+#define R5432_CP0_INTERRUPT_WAR 0 -+#define BCM1250_M3_WAR 0 -+#define SIBYTE_1956_WAR 0 -+#define MIPS4K_ICACHE_REFILL_WAR 0 -+#define MIPS_CACHE_SYNC_WAR 0 -+#define TX49XX_ICACHE_INDEX_INV_WAR 0 -+#define RM9000_CDEX_SMP_WAR 0 -+#define ICACHE_REFILLS_WORKAROUND_WAR 0 -+#define R10000_LLSC_WAR 0 -+#define MIPS34K_MISSED_ITLB_WAR 0 -+ -+#endif /* __ASM_MACH_AR71XX_WAR_H */ -diff -Nur linux-2.6.37.orig/arch/mips/include/asm/mips_machine.h linux-2.6.37/arch/mips/include/asm/mips_machine.h ---- linux-2.6.37.orig/arch/mips/include/asm/mips_machine.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/include/asm/mips_machine.h 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,54 @@ -+/* -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ */ -+ -+#ifndef __ASM_MIPS_MACHINE_H -+#define __ASM_MIPS_MACHINE_H -+ -+#include -+#include -+ -+#include -+ -+struct mips_machine { -+ unsigned long mach_type; -+ char *mach_id; -+ char *mach_name; -+ void (*mach_setup)(void); -+ struct list_head list; -+}; -+ -+void mips_machine_register(struct mips_machine *) __init; -+void mips_machine_setup(void) __init; -+int mips_machtype_setup(char *id) __init; -+void mips_machine_set_name(char *name) __init; -+ -+extern char *mips_machine_name; -+ -+#define MIPS_MACHINE(_type, _id, _name, _setup) \ -+static const char machine_name_##_type[] __initconst \ -+ __aligned(1) = _name; \ -+static const char machine_id_##_type[] __initconst \ -+ __aligned(1) = _id; \ -+static struct mips_machine machine_##_type __initdata = \ -+{ \ -+ .mach_type = _type, \ -+ .mach_id = (char *) machine_id_##_type, \ -+ .mach_name = (char *) machine_name_##_type, \ -+ .mach_setup = _setup, \ -+}; \ -+ \ -+static int __init register_machine_##_type(void) \ -+{ \ -+ mips_machine_register(&machine_##_type); \ -+ return 0; \ -+} \ -+ \ -+pure_initcall(register_machine_##_type) -+ -+#endif /* __ASM_MIPS_MACHINE_H */ -diff -Nur linux-2.6.37.orig/arch/mips/include/asm/time.h linux-2.6.37/arch/mips/include/asm/time.h ---- linux-2.6.37.orig/arch/mips/include/asm/time.h 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/mips/include/asm/time.h 2011-01-11 20:25:48.000000000 +0100 -@@ -52,6 +52,7 @@ - */ - #ifdef CONFIG_CEVT_R4K_LIB - extern unsigned int __weak get_c0_compare_int(void); -+extern unsigned int __weak get_c0_compare_irq(void); - extern int r4k_clockevent_init(void); - #endif - -diff -Nur linux-2.6.37.orig/arch/mips/kernel/Makefile linux-2.6.37/arch/mips/kernel/Makefile ---- linux-2.6.37.orig/arch/mips/kernel/Makefile 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/mips/kernel/Makefile 2011-01-11 20:25:48.000000000 +0100 -@@ -94,6 +94,7 @@ - - obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o - obj-$(CONFIG_EARLY_PRINTK) += early_printk.o -+obj-$(CONFIG_MIPS_MACHINE) += mips_machine.o - obj-$(CONFIG_SPINLOCK_TEST) += spinlock_test.o - - obj-$(CONFIG_OF) += prom.o -diff -Nur linux-2.6.37.orig/arch/mips/kernel/mips_machine.c linux-2.6.37/arch/mips/kernel/mips_machine.c ---- linux-2.6.37.orig/arch/mips/kernel/mips_machine.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/kernel/mips_machine.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,121 @@ -+/* -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ */ -+#include -+#include -+#include -+ -+#include -+ -+static struct list_head mips_machines __initdata = -+ LIST_HEAD_INIT(mips_machines); -+static char *mips_machid __initdata; -+ -+char *mips_machine_name = "Unknown"; -+ -+static struct mips_machine * __init mips_machine_find(unsigned long machtype) -+{ -+ struct list_head *this; -+ -+ list_for_each(this, &mips_machines) { -+ struct mips_machine *mach; -+ -+ mach = list_entry(this, struct mips_machine, list); -+ if (mach->mach_type == machtype) -+ return mach; -+ } -+ -+ return NULL; -+} -+ -+void __init mips_machine_register(struct mips_machine *mach) -+{ -+ list_add_tail(&mach->list, &mips_machines); -+} -+ -+void __init mips_machine_set_name(char *name) -+{ -+ unsigned int len; -+ char *p; -+ -+ if (name == NULL) -+ return; -+ -+ len = strlen(name); -+ p = kmalloc(len + 1, GFP_KERNEL); -+ if (p) { -+ strncpy(p, name, len); -+ p[len] = '\0'; -+ mips_machine_name = p; -+ } else { -+ printk(KERN_WARNING "MIPS: no memory for machine_name\n"); -+ } -+} -+ -+void __init mips_machine_setup(void) -+{ -+ struct mips_machine *mach; -+ -+ mach = mips_machine_find(mips_machtype); -+ if (!mach) { -+ printk(KERN_WARNING "MIPS: no machine registered for " -+ "machtype %lu\n", mips_machtype); -+ return; -+ } -+ -+ mips_machine_set_name(mach->mach_name); -+ printk(KERN_NOTICE "MIPS: machine is %s\n", mips_machine_name); -+ -+ if (mach->mach_setup) -+ mach->mach_setup(); -+} -+ -+int __init mips_machtype_setup(char *id) -+{ -+ if (mips_machid == NULL) -+ mips_machid = id; -+ -+ return 1; -+} -+ -+__setup("machtype=", mips_machtype_setup); -+ -+static int __init mips_machtype_init(void) -+{ -+ struct list_head *this; -+ struct mips_machine *mach; -+ -+ if (mips_machid == NULL) -+ return 0; -+ -+ list_for_each(this, &mips_machines) { -+ mach = list_entry(this, struct mips_machine, list); -+ if (mach->mach_id == NULL) -+ continue; -+ -+ if (strcmp(mach->mach_id, mips_machid) == 0) { -+ mips_machtype = mach->mach_type; -+ return 0; -+ } -+ } -+ -+ printk(KERN_WARNING -+ "MIPS: no machine found for id: '%s', registered machines:\n", -+ mips_machid); -+ printk(KERN_WARNING "%32s %s\n", "id", "name"); -+ -+ list_for_each(this, &mips_machines) { -+ mach = list_entry(this, struct mips_machine, list); -+ printk(KERN_WARNING "%32s %s\n", -+ mach->mach_id ? mach->mach_id : "", mach->mach_name); -+ } -+ -+ return 0; -+} -+ -+core_initcall(mips_machtype_init); -diff -Nur linux-2.6.37.orig/arch/mips/kernel/proc.c linux-2.6.37/arch/mips/kernel/proc.c ---- linux-2.6.37.orig/arch/mips/kernel/proc.c 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/mips/kernel/proc.c 2011-01-11 20:25:48.000000000 +0100 -@@ -12,6 +12,7 @@ - #include - #include - #include -+#include - - unsigned int vced_count, vcei_count; - -@@ -31,8 +32,12 @@ - /* - * For the first processor also print the system type - */ -- if (n == 0) -+ if (n == 0) { - seq_printf(m, "system type\t\t: %s\n", get_system_type()); -+#ifdef CONFIG_MIPS_MACHINE -+ seq_printf(m, "machine\t\t\t: %s\n", mips_machine_name); -+#endif -+ } - - seq_printf(m, "processor\t\t: %ld\n", n); - sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n", -diff -Nur linux-2.6.37.orig/arch/mips/kernel/traps.c linux-2.6.37/arch/mips/kernel/traps.c ---- linux-2.6.37.orig/arch/mips/kernel/traps.c 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/mips/kernel/traps.c 2011-01-11 20:26:51.000000000 +0100 -@@ -46,6 +46,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -1578,6 +1579,8 @@ - if (cpu_has_mips_r2) { - cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP; - cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7; -+ if (get_c0_compare_irq) -+ cp0_compare_irq = get_c0_compare_irq(); - cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7; - if (cp0_perfcount_irq == cp0_compare_irq) - cp0_perfcount_irq = -1; -diff -Nur linux-2.6.37.orig/arch/mips/pci/Makefile linux-2.6.37/arch/mips/pci/Makefile ---- linux-2.6.37.orig/arch/mips/pci/Makefile 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/mips/pci/Makefile 2011-01-11 20:25:48.000000000 +0100 -@@ -18,6 +18,7 @@ - obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o - obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \ - ops-bcm63xx.o -+obj-$(CONFIG_ATHEROS_AR71XX) += pci-ar71xx.o pci-ar724x.o - - # - # These are still pretty much in the old state, watch, go blind. -diff -Nur linux-2.6.37.orig/arch/mips/pci/pci-ar71xx.c linux-2.6.37/arch/mips/pci/pci-ar71xx.c ---- linux-2.6.37.orig/arch/mips/pci/pci-ar71xx.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/pci/pci-ar71xx.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,409 @@ -+/* -+ * Atheros AR71xx PCI host controller driver -+ * -+ * Copyright (C) 2008-2010 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#undef DEBUG -+#ifdef DEBUG -+#define DBG(fmt, args...) printk(KERN_DEBUG fmt, ## args) -+#else -+#define DBG(fmt, args...) -+#endif -+ -+#define AR71XX_PCI_DELAY 100 /* msecs */ -+ -+#if 0 -+#define PCI_IDSEL_BASE PCI_IDSEL_ADL_START -+#else -+#define PCI_IDSEL_BASE 0 -+#endif -+ -+static void __iomem *ar71xx_pcicfg_base; -+static DEFINE_SPINLOCK(ar71xx_pci_lock); -+static int ar71xx_pci_fixup_enable; -+ -+static inline void ar71xx_pci_delay(void) -+{ -+ mdelay(AR71XX_PCI_DELAY); -+} -+ -+/* Byte lane enable bits */ -+static u8 ble_table[4][4] = { -+ {0x0, 0xf, 0xf, 0xf}, -+ {0xe, 0xd, 0xb, 0x7}, -+ {0xc, 0xf, 0x3, 0xf}, -+ {0xf, 0xf, 0xf, 0xf}, -+}; -+ -+static inline u32 ar71xx_pci_get_ble(int where, int size, int local) -+{ -+ u32 t; -+ -+ t = ble_table[size & 3][where & 3]; -+ BUG_ON(t == 0xf); -+ t <<= (local) ? 20 : 4; -+ return t; -+} -+ -+static inline u32 ar71xx_pci_bus_addr(struct pci_bus *bus, unsigned int devfn, -+ int where) -+{ -+ u32 ret; -+ -+ if (!bus->number) { -+ /* type 0 */ -+ ret = (1 << (PCI_IDSEL_BASE + PCI_SLOT(devfn))) -+ | (PCI_FUNC(devfn) << 8) | (where & ~3); -+ } else { -+ /* type 1 */ -+ ret = (bus->number << 16) | (PCI_SLOT(devfn) << 11) -+ | (PCI_FUNC(devfn) << 8) | (where & ~3) | 1; -+ } -+ -+ return ret; -+} -+ -+int ar71xx_pci_be_handler(int is_fixup) -+{ -+ void __iomem *base = ar71xx_pcicfg_base; -+ u32 pci_err; -+ u32 ahb_err; -+ -+ pci_err = __raw_readl(base + PCI_REG_PCI_ERR) & 3; -+ if (pci_err) { -+ if (!is_fixup) -+ printk(KERN_ALERT "PCI error %d at PCI addr 0x%x\n", -+ pci_err, -+ __raw_readl(base + PCI_REG_PCI_ERR_ADDR)); -+ -+ __raw_writel(pci_err, base + PCI_REG_PCI_ERR); -+ } -+ -+ ahb_err = __raw_readl(base + PCI_REG_AHB_ERR) & 1; -+ if (ahb_err) { -+ if (!is_fixup) -+ printk(KERN_ALERT "AHB error at AHB address 0x%x\n", -+ __raw_readl(base + PCI_REG_AHB_ERR_ADDR)); -+ -+ __raw_writel(ahb_err, base + PCI_REG_AHB_ERR); -+ } -+ -+ return ((ahb_err | pci_err) ? 1 : 0); -+} -+ -+static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus, -+ unsigned int devfn, int where, int size, u32 cmd) -+{ -+ void __iomem *base = ar71xx_pcicfg_base; -+ u32 addr; -+ -+ addr = ar71xx_pci_bus_addr(bus, devfn, where); -+ -+ DBG("PCI: set cfgaddr: %02x:%02x.%01x/%02x:%01d, addr=%08x\n", -+ bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), -+ where, size, addr); -+ -+ __raw_writel(addr, base + PCI_REG_CFG_AD); -+ __raw_writel(cmd | ar71xx_pci_get_ble(where, size, 0), -+ base + PCI_REG_CFG_CBE); -+ -+ return ar71xx_pci_be_handler(1); -+} -+ -+static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, -+ int where, int size, u32 *value) -+{ -+ void __iomem *base = ar71xx_pcicfg_base; -+ static u32 mask[8] = {0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0}; -+ unsigned long flags; -+ u32 data; -+ int ret; -+ -+ ret = PCIBIOS_SUCCESSFUL; -+ -+ DBG("PCI: read config: %02x:%02x.%01x/%02x:%01d\n", bus->number, -+ PCI_SLOT(devfn), PCI_FUNC(devfn), where, size); -+ -+ spin_lock_irqsave(&ar71xx_pci_lock, flags); -+ -+ if (bus->number == 0 && devfn == 0) { -+ u32 t; -+ -+ t = PCI_CRP_CMD_READ | (where & ~3); -+ -+ __raw_writel(t, base + PCI_REG_CRP_AD_CBE); -+ data = __raw_readl(base + PCI_REG_CRP_RDDATA); -+ -+ DBG("PCI: rd local cfg, ad_cbe:%08x, data:%08x\n", t, data); -+ -+ } else { -+ int err; -+ -+ err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size, -+ PCI_CFG_CMD_READ); -+ -+ if (err == 0) { -+ data = __raw_readl(base + PCI_REG_CFG_RDDATA); -+ } else { -+ ret = PCIBIOS_DEVICE_NOT_FOUND; -+ data = ~0; -+ } -+ } -+ -+ spin_unlock_irqrestore(&ar71xx_pci_lock, flags); -+ -+ DBG("PCI: read config: data=%08x raw=%08x\n", -+ (data >> (8 * (where & 3))) & mask[size & 7], data); -+ -+ *value = (data >> (8 * (where & 3))) & mask[size & 7]; -+ -+ return ret; -+} -+ -+static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn, -+ int where, int size, u32 value) -+{ -+ void __iomem *base = ar71xx_pcicfg_base; -+ unsigned long flags; -+ int ret; -+ -+ DBG("PCI: write config: %02x:%02x.%01x/%02x:%01d value=%08x\n", -+ bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), -+ where, size, value); -+ -+ value = value << (8 * (where & 3)); -+ ret = PCIBIOS_SUCCESSFUL; -+ -+ spin_lock_irqsave(&ar71xx_pci_lock, flags); -+ if (bus->number == 0 && devfn == 0) { -+ u32 t; -+ -+ t = PCI_CRP_CMD_WRITE | (where & ~3); -+ t |= ar71xx_pci_get_ble(where, size, 1); -+ -+ DBG("PCI: wr local cfg, ad_cbe:%08x, value:%08x\n", t, value); -+ -+ __raw_writel(t, base + PCI_REG_CRP_AD_CBE); -+ __raw_writel(value, base + PCI_REG_CRP_WRDATA); -+ } else { -+ int err; -+ -+ err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size, -+ PCI_CFG_CMD_WRITE); -+ -+ if (err == 0) -+ __raw_writel(value, base + PCI_REG_CFG_WRDATA); -+ else -+ ret = PCIBIOS_DEVICE_NOT_FOUND; -+ } -+ spin_unlock_irqrestore(&ar71xx_pci_lock, flags); -+ -+ return ret; -+} -+ -+static void ar71xx_pci_fixup(struct pci_dev *dev) -+{ -+ u32 t; -+ -+ if (!ar71xx_pci_fixup_enable) -+ return; -+ -+ if (dev->bus->number != 0 || dev->devfn != 0) -+ return; -+ -+ DBG("PCI: fixup host controller %s (%04x:%04x)\n", pci_name(dev), -+ dev->vendor, dev->device); -+ -+ /* setup COMMAND register */ -+ t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE -+ | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK; -+ -+ pci_write_config_word(dev, PCI_COMMAND, t); -+} -+DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ar71xx_pci_fixup); -+ -+int __init ar71xx_pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, -+ uint8_t pin) -+{ -+ int irq = -1; -+ int i; -+ -+ slot -= PCI_IDSEL_ADL_START - PCI_IDSEL_BASE; -+ -+ for (i = 0; i < ar71xx_pci_nr_irqs; i++) { -+ struct ar71xx_pci_irq *entry; -+ -+ entry = &ar71xx_pci_irq_map[i]; -+ if (entry->slot == slot && entry->pin == pin) { -+ irq = entry->irq; -+ break; -+ } -+ } -+ -+ if (irq < 0) { -+ printk(KERN_ALERT "PCI: no irq found for pin%u@%s\n", -+ pin, pci_name((struct pci_dev *)dev)); -+ } else { -+ printk(KERN_INFO "PCI: mapping irq %d to pin%u@%s\n", -+ irq, pin, pci_name((struct pci_dev *)dev)); -+ } -+ -+ return irq; -+} -+ -+static struct pci_ops ar71xx_pci_ops = { -+ .read = ar71xx_pci_read_config, -+ .write = ar71xx_pci_write_config, -+}; -+ -+static struct resource ar71xx_pci_io_resource = { -+ .name = "PCI IO space", -+ .start = 0, -+ .end = 0, -+ .flags = IORESOURCE_IO, -+}; -+ -+static struct resource ar71xx_pci_mem_resource = { -+ .name = "PCI memory space", -+ .start = AR71XX_PCI_MEM_BASE, -+ .end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1, -+ .flags = IORESOURCE_MEM -+}; -+ -+static struct pci_controller ar71xx_pci_controller = { -+ .pci_ops = &ar71xx_pci_ops, -+ .mem_resource = &ar71xx_pci_mem_resource, -+ .io_resource = &ar71xx_pci_io_resource, -+}; -+ -+static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc) -+{ -+ void __iomem *base = ar71xx_reset_base; -+ u32 pending; -+ -+ pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) & -+ __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); -+ -+ if (pending & PCI_INT_DEV0) -+ generic_handle_irq(AR71XX_PCI_IRQ_DEV0); -+ -+ else if (pending & PCI_INT_DEV1) -+ generic_handle_irq(AR71XX_PCI_IRQ_DEV1); -+ -+ else if (pending & PCI_INT_DEV2) -+ generic_handle_irq(AR71XX_PCI_IRQ_DEV2); -+ -+ else if (pending & PCI_INT_CORE) -+ generic_handle_irq(AR71XX_PCI_IRQ_CORE); -+ -+ else -+ spurious_interrupt(); -+} -+ -+static void ar71xx_pci_irq_unmask(unsigned int irq) -+{ -+ void __iomem *base = ar71xx_reset_base; -+ u32 t; -+ -+ irq -= AR71XX_PCI_IRQ_BASE; -+ -+ t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); -+ __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); -+ -+ /* flush write */ -+ (void) __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); -+} -+ -+static void ar71xx_pci_irq_mask(unsigned int irq) -+{ -+ void __iomem *base = ar71xx_reset_base; -+ u32 t; -+ -+ irq -= AR71XX_PCI_IRQ_BASE; -+ -+ t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); -+ __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); -+ -+ /* flush write */ -+ (void) __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); -+} -+ -+static struct irq_chip ar71xx_pci_irq_chip = { -+ .name = "AR71XX PCI ", -+ .mask = ar71xx_pci_irq_mask, -+ .unmask = ar71xx_pci_irq_unmask, -+ .mask_ack = ar71xx_pci_irq_mask, -+}; -+ -+static void __init ar71xx_pci_irq_init(void) -+{ -+ void __iomem *base = ar71xx_reset_base; -+ int i; -+ -+ __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE); -+ __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS); -+ -+ for (i = AR71XX_PCI_IRQ_BASE; -+ i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) { -+ irq_desc[i].status = IRQ_DISABLED; -+ set_irq_chip_and_handler(i, &ar71xx_pci_irq_chip, -+ handle_level_irq); -+ } -+ -+ set_irq_chained_handler(AR71XX_CPU_IRQ_IP2, ar71xx_pci_irq_handler); -+} -+ -+int __init ar71xx_pcibios_init(void) -+{ -+ void __iomem *ddr_base = ar71xx_ddr_base; -+ -+ ar71xx_device_stop(RESET_MODULE_PCI_BUS | RESET_MODULE_PCI_CORE); -+ ar71xx_pci_delay(); -+ -+ ar71xx_device_start(RESET_MODULE_PCI_BUS | RESET_MODULE_PCI_CORE); -+ ar71xx_pci_delay(); -+ -+ ar71xx_pcicfg_base = ioremap_nocache(AR71XX_PCI_CFG_BASE, -+ AR71XX_PCI_CFG_SIZE); -+ if (ar71xx_pcicfg_base == NULL) -+ return -ENOMEM; -+ -+ __raw_writel(PCI_WIN0_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN0); -+ __raw_writel(PCI_WIN1_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN1); -+ __raw_writel(PCI_WIN2_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN2); -+ __raw_writel(PCI_WIN3_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN3); -+ __raw_writel(PCI_WIN4_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN4); -+ __raw_writel(PCI_WIN5_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN5); -+ __raw_writel(PCI_WIN6_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN6); -+ __raw_writel(PCI_WIN7_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN7); -+ -+ ar71xx_pci_delay(); -+ -+ /* clear bus errors */ -+ (void)ar71xx_pci_be_handler(1); -+ -+ ar71xx_pci_fixup_enable = 1; -+ ar71xx_pci_irq_init(); -+ register_pci_controller(&ar71xx_pci_controller); -+ -+ return 0; -+} -diff -Nur linux-2.6.37.orig/arch/mips/pci/pci-ar724x.c linux-2.6.37/arch/mips/pci/pci-ar724x.c ---- linux-2.6.37.orig/arch/mips/pci/pci-ar724x.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/pci/pci-ar724x.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,395 @@ -+/* -+ * Atheros AR724x PCI host controller driver -+ * -+ * Copyright (C) 2009-2010 Gabor Juhos -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#undef DEBUG -+#ifdef DEBUG -+#define DBG(fmt, args...) printk(KERN_INFO fmt, ## args) -+#else -+#define DBG(fmt, args...) -+#endif -+ -+static void __iomem *ar724x_pci_localcfg_base; -+static void __iomem *ar724x_pci_devcfg_base; -+static void __iomem *ar724x_pci_ctrl_base; -+static int ar724x_pci_fixup_enable; -+ -+static DEFINE_SPINLOCK(ar724x_pci_lock); -+ -+static void ar724x_pci_read(void __iomem *base, int where, int size, u32 *value) -+{ -+ unsigned long flags; -+ u32 data; -+ -+ spin_lock_irqsave(&ar724x_pci_lock, flags); -+ data = __raw_readl(base + (where & ~3)); -+ -+ switch (size) { -+ case 1: -+ if (where & 1) -+ data >>= 8; -+ if (where & 2) -+ data >>= 16; -+ data &= 0xFF; -+ break; -+ case 2: -+ if (where & 2) -+ data >>= 16; -+ data &= 0xFFFF; -+ break; -+ } -+ -+ *value = data; -+ spin_unlock_irqrestore(&ar724x_pci_lock, flags); -+} -+ -+static void ar724x_pci_write(void __iomem *base, int where, int size, u32 value) -+{ -+ unsigned long flags; -+ u32 data; -+ int s; -+ -+ spin_lock_irqsave(&ar724x_pci_lock, flags); -+ data = __raw_readl(base + (where & ~3)); -+ -+ switch (size) { -+ case 1: -+ s = ((where & 3) << 3); -+ data &= ~(0xFF << s); -+ data |= ((value & 0xFF) << s); -+ break; -+ case 2: -+ s = ((where & 2) << 3); -+ data &= ~(0xFFFF << s); -+ data |= ((value & 0xFFFF) << s); -+ break; -+ case 4: -+ data = value; -+ break; -+ } -+ -+ __raw_writel(data, base + (where & ~3)); -+ /* flush write */ -+ (void)__raw_readl(base + (where & ~3)); -+ spin_unlock_irqrestore(&ar724x_pci_lock, flags); -+} -+ -+static int ar724x_pci_read_config(struct pci_bus *bus, unsigned int devfn, -+ int where, int size, u32 *value) -+{ -+ -+ if (bus->number != 0 || devfn != 0) -+ return PCIBIOS_DEVICE_NOT_FOUND; -+ -+ ar724x_pci_read(ar724x_pci_devcfg_base, where, size, value); -+ -+ DBG("PCI: read config: %02x:%02x.%01x/%02x:%01d, value=%08x\n", -+ bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), -+ where, size, *value); -+ -+ /* -+ * WAR for BAR issue - We are unable to access the PCI device space -+ * if we set the BAR with proper base address -+ */ -+ if ((where == 0x10) && (size == 4)) { -+ if (ar71xx_soc == AR71XX_SOC_AR7240) -+ ar724x_pci_write(ar724x_pci_devcfg_base, where, size, 0xffff); -+ else -+ ar724x_pci_write(ar724x_pci_devcfg_base, where, size, 0x1000ffff); -+ } -+ -+ return PCIBIOS_SUCCESSFUL; -+} -+ -+static int ar724x_pci_write_config(struct pci_bus *bus, unsigned int devfn, -+ int where, int size, u32 value) -+{ -+ if (bus->number != 0 || devfn != 0) -+ return PCIBIOS_DEVICE_NOT_FOUND; -+ -+ DBG("PCI: write config: %02x:%02x.%01x/%02x:%01d, value=%08x\n", -+ bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), -+ where, size, value); -+ -+ ar724x_pci_write(ar724x_pci_devcfg_base, where, size, value); -+ -+ return PCIBIOS_SUCCESSFUL; -+} -+ -+static void ar724x_pci_fixup(struct pci_dev *dev) -+{ -+ u16 cmd; -+ -+ if (!ar724x_pci_fixup_enable) -+ return; -+ -+ if (dev->bus->number != 0 || dev->devfn != 0) -+ return; -+ -+ /* setup COMMAND register */ -+ pci_read_config_word(dev, PCI_COMMAND, &cmd); -+ cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | -+ PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | -+ PCI_COMMAND_FAST_BACK; -+ -+ pci_write_config_word(dev, PCI_COMMAND, cmd); -+} -+DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ar724x_pci_fixup); -+ -+int __init ar724x_pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, -+ uint8_t pin) -+{ -+ int irq = -1; -+ int i; -+ -+ for (i = 0; i < ar71xx_pci_nr_irqs; i++) { -+ struct ar71xx_pci_irq *entry; -+ entry = &ar71xx_pci_irq_map[i]; -+ -+ if (entry->slot == slot && entry->pin == pin) { -+ irq = entry->irq; -+ break; -+ } -+ } -+ -+ if (irq < 0) -+ printk(KERN_ALERT "PCI: no irq found for pin%u@%s\n", -+ pin, pci_name((struct pci_dev *)dev)); -+ else -+ printk(KERN_INFO "PCI: mapping irq %d to pin%u@%s\n", -+ irq, pin, pci_name((struct pci_dev *)dev)); -+ -+ return irq; -+} -+ -+static struct pci_ops ar724x_pci_ops = { -+ .read = ar724x_pci_read_config, -+ .write = ar724x_pci_write_config, -+}; -+ -+static struct resource ar724x_pci_io_resource = { -+ .name = "PCI IO space", -+ .start = 0, -+ .end = 0, -+ .flags = IORESOURCE_IO, -+}; -+ -+static struct resource ar724x_pci_mem_resource = { -+ .name = "PCI memory space", -+ .start = AR71XX_PCI_MEM_BASE, -+ .end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1, -+ .flags = IORESOURCE_MEM -+}; -+ -+static struct pci_controller ar724x_pci_controller = { -+ .pci_ops = &ar724x_pci_ops, -+ .mem_resource = &ar724x_pci_mem_resource, -+ .io_resource = &ar724x_pci_io_resource, -+}; -+ -+static void __init ar724x_pci_reset(void) -+{ -+ ar71xx_device_stop(AR724X_RESET_PCIE); -+ ar71xx_device_stop(AR724X_RESET_PCIE_PHY); -+ ar71xx_device_stop(AR724X_RESET_PCIE_PHY_SERIAL); -+ udelay(100); -+ -+ ar71xx_device_start(AR724X_RESET_PCIE_PHY_SERIAL); -+ udelay(100); -+ ar71xx_device_start(AR724X_RESET_PCIE_PHY); -+ ar71xx_device_start(AR724X_RESET_PCIE); -+} -+ -+static int __init ar724x_pci_setup(void) -+{ -+ void __iomem *base = ar724x_pci_ctrl_base; -+ u32 t; -+ -+ /* setup COMMAND register */ -+ t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE | -+ PCI_COMMAND_PARITY|PCI_COMMAND_SERR|PCI_COMMAND_FAST_BACK; -+ -+ ar724x_pci_write(ar724x_pci_localcfg_base, PCI_COMMAND, 4, t); -+ ar724x_pci_write(ar724x_pci_localcfg_base, 0x20, 4, 0x1ff01000); -+ ar724x_pci_write(ar724x_pci_localcfg_base, 0x24, 4, 0x1ff01000); -+ -+ t = __raw_readl(base + AR724X_PCI_REG_RESET); -+ if (t != 0x7) { -+ udelay(100000); -+ __raw_writel(0, base + AR724X_PCI_REG_RESET); -+ udelay(100); -+ __raw_writel(4, base + AR724X_PCI_REG_RESET); -+ udelay(100000); -+ } -+ -+ if (ar71xx_soc == AR71XX_SOC_AR7240) -+ t = AR724X_PCI_APP_LTSSM_ENABLE; -+ else -+ t = 0x1ffc1; -+ __raw_writel(t, base + AR724X_PCI_REG_APP); -+ /* flush write */ -+ (void) __raw_readl(base + AR724X_PCI_REG_APP); -+ udelay(1000); -+ -+ t = __raw_readl(base + AR724X_PCI_REG_RESET); -+ if ((t & AR724X_PCI_RESET_LINK_UP) == 0x0) { -+ printk(KERN_WARNING "PCI: no PCIe module found\n"); -+ return -ENODEV; -+ } -+ -+ if (ar71xx_soc == AR71XX_SOC_AR7241 || ar71xx_soc == AR71XX_SOC_AR7242) { -+ t = __raw_readl(base + AR724X_PCI_REG_APP); -+ t |= BIT(16); -+ __raw_writel(t, base + AR724X_PCI_REG_APP); -+ } -+ -+ return 0; -+} -+ -+static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc) -+{ -+ void __iomem *base = ar724x_pci_ctrl_base; -+ u32 pending; -+ -+ pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) & -+ __raw_readl(base + AR724X_PCI_REG_INT_MASK); -+ -+ if (pending & AR724X_PCI_INT_DEV0) -+ generic_handle_irq(AR71XX_PCI_IRQ_DEV0); -+ -+ else -+ spurious_interrupt(); -+} -+ -+static void ar724x_pci_irq_unmask(unsigned int irq) -+{ -+ void __iomem *base = ar724x_pci_ctrl_base; -+ u32 t; -+ -+ switch (irq) { -+ case AR71XX_PCI_IRQ_DEV0: -+ irq -= AR71XX_PCI_IRQ_BASE; -+ -+ t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); -+ __raw_writel(t | AR724X_PCI_INT_DEV0, -+ base + AR724X_PCI_REG_INT_MASK); -+ /* flush write */ -+ (void) __raw_readl(base + AR724X_PCI_REG_INT_MASK); -+ } -+} -+ -+static void ar724x_pci_irq_mask(unsigned int irq) -+{ -+ void __iomem *base = ar724x_pci_ctrl_base; -+ u32 t; -+ -+ switch (irq) { -+ case AR71XX_PCI_IRQ_DEV0: -+ irq -= AR71XX_PCI_IRQ_BASE; -+ -+ t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); -+ __raw_writel(t & ~AR724X_PCI_INT_DEV0, -+ base + AR724X_PCI_REG_INT_MASK); -+ -+ /* flush write */ -+ (void) __raw_readl(base + AR724X_PCI_REG_INT_MASK); -+ -+ t = __raw_readl(base + AR724X_PCI_REG_INT_STATUS); -+ __raw_writel(t | AR724X_PCI_INT_DEV0, -+ base + AR724X_PCI_REG_INT_STATUS); -+ -+ /* flush write */ -+ (void) __raw_readl(base + AR724X_PCI_REG_INT_STATUS); -+ } -+} -+ -+static struct irq_chip ar724x_pci_irq_chip = { -+ .name = "AR724X PCI ", -+ .mask = ar724x_pci_irq_mask, -+ .unmask = ar724x_pci_irq_unmask, -+ .mask_ack = ar724x_pci_irq_mask, -+}; -+ -+static void __init ar724x_pci_irq_init(void) -+{ -+ void __iomem *base = ar724x_pci_ctrl_base; -+ u32 t; -+ int i; -+ -+ t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE); -+ if (t & (AR724X_RESET_PCIE | AR724X_RESET_PCIE_PHY | -+ AR724X_RESET_PCIE_PHY_SERIAL)) { -+ return; -+ } -+ -+ __raw_writel(0, base + AR724X_PCI_REG_INT_MASK); -+ __raw_writel(0, base + AR724X_PCI_REG_INT_STATUS); -+ -+ for (i = AR71XX_PCI_IRQ_BASE; -+ i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) { -+ irq_desc[i].status = IRQ_DISABLED; -+ set_irq_chip_and_handler(i, &ar724x_pci_irq_chip, -+ handle_level_irq); -+ } -+ -+ set_irq_chained_handler(AR71XX_CPU_IRQ_IP2, ar724x_pci_irq_handler); -+} -+ -+int __init ar724x_pcibios_init(void) -+{ -+ int ret = -ENOMEM; -+ -+ ar724x_pci_localcfg_base = ioremap_nocache(AR724X_PCI_CRP_BASE, -+ AR724X_PCI_CRP_SIZE); -+ if (ar724x_pci_localcfg_base == NULL) -+ goto err; -+ -+ ar724x_pci_devcfg_base = ioremap_nocache(AR724X_PCI_CFG_BASE, -+ AR724X_PCI_CFG_SIZE); -+ if (ar724x_pci_devcfg_base == NULL) -+ goto err_unmap_localcfg; -+ -+ ar724x_pci_ctrl_base = ioremap_nocache(AR724X_PCI_CTRL_BASE, -+ AR724X_PCI_CTRL_SIZE); -+ if (ar724x_pci_ctrl_base == NULL) -+ goto err_unmap_devcfg; -+ -+ ar724x_pci_reset(); -+ ret = ar724x_pci_setup(); -+ if (ret) -+ goto err_unmap_ctrl; -+ -+ ar724x_pci_fixup_enable = 1; -+ ar724x_pci_irq_init(); -+ register_pci_controller(&ar724x_pci_controller); -+ -+ return 0; -+ -+ err_unmap_ctrl: -+ iounmap(ar724x_pci_ctrl_base); -+ err_unmap_devcfg: -+ iounmap(ar724x_pci_devcfg_base); -+ err_unmap_localcfg: -+ iounmap(ar724x_pci_localcfg_base); -+ err: -+ return ret; -+} -diff -Nur linux-2.6.37.orig/drivers/char/Kconfig linux-2.6.37/drivers/char/Kconfig ---- linux-2.6.37.orig/drivers/char/Kconfig 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/char/Kconfig 2011-01-11 20:25:48.000000000 +0100 -@@ -1047,6 +1047,14 @@ - - If compiled as a module, it will be called cs5535_gpio. - -+config GPIO_DEVICE -+ tristate "GPIO device support" -+ depends on GENERIC_GPIO -+ help -+ Say Y to enable Linux GPIO device support. This allows control of -+ GPIO pins using a character device -+ -+ - config RAW_DRIVER - tristate "RAW driver (/dev/raw/rawN)" - depends on BLOCK -diff -Nur linux-2.6.37.orig/drivers/char/Makefile linux-2.6.37/drivers/char/Makefile ---- linux-2.6.37.orig/drivers/char/Makefile 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/char/Makefile 2011-01-11 20:25:48.000000000 +0100 -@@ -82,6 +82,7 @@ - obj-$(CONFIG_PC8736x_GPIO) += pc8736x_gpio.o - obj-$(CONFIG_NSC_GPIO) += nsc_gpio.o - obj-$(CONFIG_CS5535_GPIO) += cs5535_gpio.o -+obj-$(CONFIG_GPIO_DEVICE) += gpio_dev.o - obj-$(CONFIG_GPIO_TB0219) += tb0219.o - obj-$(CONFIG_TELCLOCK) += tlclk.o - -diff -Nur linux-2.6.37.orig/drivers/gpio/nxp_74hc153.c linux-2.6.37/drivers/gpio/nxp_74hc153.c ---- linux-2.6.37.orig/drivers/gpio/nxp_74hc153.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/drivers/gpio/nxp_74hc153.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,246 @@ -+/* -+ * NXP 74HC153 - Dual 4-input multiplexer GPIO driver -+ * -+ * Copyright (C) 2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#define NXP_74HC153_NUM_GPIOS 8 -+#define NXP_74HC153_S0_MASK 0x1 -+#define NXP_74HC153_S1_MASK 0x2 -+#define NXP_74HC153_BANK_MASK 0x4 -+ -+struct nxp_74hc153_chip { -+ struct device *parent; -+ struct gpio_chip gpio_chip; -+ struct mutex lock; -+}; -+ -+static struct nxp_74hc153_chip *gpio_to_nxp(struct gpio_chip *gc) -+{ -+ return container_of(gc, struct nxp_74hc153_chip, gpio_chip); -+} -+ -+static int nxp_74hc153_direction_input(struct gpio_chip *gc, unsigned offset) -+{ -+ return 0; -+} -+ -+static int nxp_74hc153_direction_output(struct gpio_chip *gc, -+ unsigned offset, int val) -+{ -+ return -EINVAL; -+} -+ -+static int nxp_74hc153_get_value(struct gpio_chip *gc, unsigned offset) -+{ -+ struct nxp_74hc153_chip *nxp; -+ struct nxp_74hc153_platform_data *pdata; -+ unsigned s0; -+ unsigned s1; -+ unsigned pin; -+ int ret; -+ -+ nxp = gpio_to_nxp(gc); -+ pdata = nxp->parent->platform_data; -+ -+ s0 = !!(offset & NXP_74HC153_S0_MASK); -+ s1 = !!(offset & NXP_74HC153_S1_MASK); -+ pin = (offset & NXP_74HC153_BANK_MASK) ? pdata->gpio_pin_2y -+ : pdata->gpio_pin_1y; -+ -+ mutex_lock(&nxp->lock); -+ gpio_set_value(pdata->gpio_pin_s0, s0); -+ gpio_set_value(pdata->gpio_pin_s1, s1); -+ ret = gpio_get_value(pin); -+ mutex_unlock(&nxp->lock); -+ -+ return ret; -+} -+ -+static void nxp_74hc153_set_value(struct gpio_chip *gc, -+ unsigned offset, int val) -+{ -+ /* not supported */ -+} -+ -+static int __devinit nxp_74hc153_probe(struct platform_device *pdev) -+{ -+ struct nxp_74hc153_platform_data *pdata; -+ struct nxp_74hc153_chip *nxp; -+ struct gpio_chip *gc; -+ int err; -+ -+ pdata = pdev->dev.platform_data; -+ if (pdata == NULL) { -+ dev_dbg(&pdev->dev, "no platform data specified\n"); -+ return -EINVAL; -+ } -+ -+ nxp = kzalloc(sizeof(struct nxp_74hc153_chip), GFP_KERNEL); -+ if (nxp == NULL) { -+ dev_err(&pdev->dev, "no memory for private data\n"); -+ return -ENOMEM; -+ } -+ -+ err = gpio_request(pdata->gpio_pin_s0, dev_name(&pdev->dev)); -+ if (err) { -+ dev_err(&pdev->dev, "unable to claim gpio %u, err=%d\n", -+ pdata->gpio_pin_s0, err); -+ goto err_free_nxp; -+ } -+ -+ err = gpio_request(pdata->gpio_pin_s1, dev_name(&pdev->dev)); -+ if (err) { -+ dev_err(&pdev->dev, "unable to claim gpio %u, err=%d\n", -+ pdata->gpio_pin_s1, err); -+ goto err_free_s0; -+ } -+ -+ err = gpio_request(pdata->gpio_pin_1y, dev_name(&pdev->dev)); -+ if (err) { -+ dev_err(&pdev->dev, "unable to claim gpio %u, err=%d\n", -+ pdata->gpio_pin_1y, err); -+ goto err_free_s1; -+ } -+ -+ err = gpio_request(pdata->gpio_pin_2y, dev_name(&pdev->dev)); -+ if (err) { -+ dev_err(&pdev->dev, "unable to claim gpio %u, err=%d\n", -+ pdata->gpio_pin_2y, err); -+ goto err_free_1y; -+ } -+ -+ err = gpio_direction_output(pdata->gpio_pin_s0, 0); -+ if (err) { -+ dev_err(&pdev->dev, -+ "unable to set direction of gpio %u, err=%d\n", -+ pdata->gpio_pin_s0, err); -+ goto err_free_2y; -+ } -+ -+ err = gpio_direction_output(pdata->gpio_pin_s1, 0); -+ if (err) { -+ dev_err(&pdev->dev, -+ "unable to set direction of gpio %u, err=%d\n", -+ pdata->gpio_pin_s1, err); -+ goto err_free_2y; -+ } -+ -+ err = gpio_direction_input(pdata->gpio_pin_1y); -+ if (err) { -+ dev_err(&pdev->dev, -+ "unable to set direction of gpio %u, err=%d\n", -+ pdata->gpio_pin_1y, err); -+ goto err_free_2y; -+ } -+ -+ err = gpio_direction_input(pdata->gpio_pin_2y); -+ if (err) { -+ dev_err(&pdev->dev, -+ "unable to set direction of gpio %u, err=%d\n", -+ pdata->gpio_pin_2y, err); -+ goto err_free_2y; -+ } -+ -+ nxp->parent = &pdev->dev; -+ mutex_init(&nxp->lock); -+ -+ gc = &nxp->gpio_chip; -+ -+ gc->direction_input = nxp_74hc153_direction_input; -+ gc->direction_output = nxp_74hc153_direction_output; -+ gc->get = nxp_74hc153_get_value; -+ gc->set = nxp_74hc153_set_value; -+ gc->can_sleep = 1; -+ -+ gc->base = pdata->gpio_base; -+ gc->ngpio = NXP_74HC153_NUM_GPIOS; -+ gc->label = dev_name(nxp->parent); -+ gc->dev = nxp->parent; -+ gc->owner = THIS_MODULE; -+ -+ err = gpiochip_add(&nxp->gpio_chip); -+ if (err) { -+ dev_err(&pdev->dev, "unable to add gpio chip, err=%d\n", err); -+ goto err_free_2y; -+ } -+ -+ platform_set_drvdata(pdev, nxp); -+ return 0; -+ -+ err_free_2y: -+ gpio_free(pdata->gpio_pin_2y); -+ err_free_1y: -+ gpio_free(pdata->gpio_pin_1y); -+ err_free_s1: -+ gpio_free(pdata->gpio_pin_s1); -+ err_free_s0: -+ gpio_free(pdata->gpio_pin_s0); -+ err_free_nxp: -+ kfree(nxp); -+ return err; -+} -+ -+static int nxp_74hc153_remove(struct platform_device *pdev) -+{ -+ struct nxp_74hc153_chip *nxp = platform_get_drvdata(pdev); -+ struct nxp_74hc153_platform_data *pdata = pdev->dev.platform_data; -+ -+ if (nxp) { -+ int err; -+ -+ err = gpiochip_remove(&nxp->gpio_chip); -+ if (err) { -+ dev_err(&pdev->dev, -+ "unable to remove gpio chip, err=%d\n", -+ err); -+ return err; -+ } -+ -+ gpio_free(pdata->gpio_pin_2y); -+ gpio_free(pdata->gpio_pin_1y); -+ gpio_free(pdata->gpio_pin_s1); -+ gpio_free(pdata->gpio_pin_s0); -+ -+ kfree(nxp); -+ platform_set_drvdata(pdev, NULL); -+ } -+ -+ return 0; -+} -+ -+static struct platform_driver nxp_74hc153_driver = { -+ .probe = nxp_74hc153_probe, -+ .remove = __devexit_p(nxp_74hc153_remove), -+ .driver = { -+ .name = NXP_74HC153_DRIVER_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init nxp_74hc153_init(void) -+{ -+ return platform_driver_register(&nxp_74hc153_driver); -+} -+subsys_initcall(nxp_74hc153_init); -+ -+static void __exit nxp_74hc153_exit(void) -+{ -+ platform_driver_unregister(&nxp_74hc153_driver); -+} -+module_exit(nxp_74hc153_exit); -+ -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_DESCRIPTION("GPIO expander driver for NXP 74HC153"); -+MODULE_LICENSE("GPL v2"); -+MODULE_ALIAS("platform:" NXP_74HC153_DRIVER_NAME); -diff -Nur linux-2.6.37.orig/drivers/input/misc/Kconfig linux-2.6.37/drivers/input/misc/Kconfig ---- linux-2.6.37.orig/drivers/input/misc/Kconfig 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/input/misc/Kconfig 2011-01-11 20:25:48.000000000 +0100 -@@ -448,4 +448,20 @@ - To compile this driver as a module, choose M here: the - module will be called adxl34x-spi. - -+config INPUT_GPIO_BUTTONS -+ tristate "Polled GPIO buttons interface" -+ depends on GENERIC_GPIO -+ select INPUT_POLLDEV -+ help -+ This driver implements support for buttons connected -+ to GPIO pins of various CPUs (and some other chips). -+ -+ Say Y here if your device has buttons connected -+ directly to such GPIO pins. Your board-specific -+ setup logic must also provide a platform device, -+ with configuration data saying which GPIOs are used. -+ -+ To compile this driver as a module, choose M here: the -+ module will be called gpio-buttons. -+ - endif -diff -Nur linux-2.6.37.orig/drivers/input/misc/Makefile linux-2.6.37/drivers/input/misc/Makefile ---- linux-2.6.37.orig/drivers/input/misc/Makefile 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/input/misc/Makefile 2011-01-11 20:25:48.000000000 +0100 -@@ -42,4 +42,5 @@ - obj-$(CONFIG_INPUT_WISTRON_BTNS) += wistron_btns.o - obj-$(CONFIG_INPUT_WM831X_ON) += wm831x-on.o - obj-$(CONFIG_INPUT_YEALINK) += yealink.o -+obj-$(CONFIG_INPUT_GPIO_BUTTONS) += gpio_buttons.o - -diff -Nur linux-2.6.37.orig/drivers/input/misc/gpio_buttons.c linux-2.6.37/drivers/input/misc/gpio_buttons.c ---- linux-2.6.37.orig/drivers/input/misc/gpio_buttons.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/drivers/input/misc/gpio_buttons.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,216 @@ -+/* -+ * Driver for buttons on GPIO lines not capable of generating interrupts -+ * -+ * Copyright (C) 2007-2010 Gabor Juhos -+ * Copyright (C) 2010 Nuno Goncalves -+ * -+ * This file was based on: /drivers/input/misc/cobalt_btns.c -+ * Copyright (C) 2007 Yoichi Yuasa -+ * -+ * also was based on: /drivers/input/keyboard/gpio_keys.c -+ * Copyright 2005 Phil Blundell -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include -+ -+#define DRV_NAME "gpio-buttons" -+#define DRV_VERSION "0.1.2" -+#define PFX DRV_NAME ": " -+ -+struct gpio_button_data { -+ int last_state; -+ int count; -+}; -+ -+struct gpio_buttons_dev { -+ struct input_polled_dev *poll_dev; -+ struct gpio_buttons_platform_data *pdata; -+ struct gpio_button_data *data; -+}; -+ -+static void gpio_buttons_poll(struct input_polled_dev *dev) -+{ -+ struct gpio_buttons_dev *bdev = dev->private; -+ struct gpio_buttons_platform_data *pdata = bdev->pdata; -+ struct input_dev *input = dev->input; -+ int i; -+ -+ for (i = 0; i < bdev->pdata->nbuttons; i++) { -+ struct gpio_button *button = &pdata->buttons[i]; -+ unsigned int type = button->type ?: EV_KEY; -+ int state; -+ -+ if (bdev->data[i].count < button->threshold) { -+ bdev->data[i].count++; -+ continue; -+ } -+ -+ state = gpio_get_value(button->gpio) ? 1 : 0; -+ if (state != bdev->data[i].last_state) { -+ input_event(input, type, button->code, -+ !!(state ^ button->active_low)); -+ input_sync(input); -+ bdev->data[i].count = 0; -+ bdev->data[i].last_state = state; -+ } -+ } -+} -+ -+static int __devinit gpio_buttons_probe(struct platform_device *pdev) -+{ -+ struct gpio_buttons_platform_data *pdata = pdev->dev.platform_data; -+ struct gpio_buttons_dev *bdev; -+ struct input_polled_dev *poll_dev; -+ struct input_dev *input; -+ int error, i; -+ -+ if (!pdata) -+ return -ENXIO; -+ -+ bdev = kzalloc(sizeof(struct gpio_buttons_dev) + -+ sizeof(struct gpio_button_data) * pdata->nbuttons, -+ GFP_KERNEL); -+ if (!bdev) { -+ printk(KERN_ERR DRV_NAME "no memory for device\n"); -+ return -ENOMEM; -+ } -+ -+ bdev->data = (struct gpio_button_data *) &bdev[1]; -+ -+ poll_dev = input_allocate_polled_device(); -+ if (!poll_dev) { -+ printk(KERN_ERR DRV_NAME "no memory for polled device\n"); -+ error = -ENOMEM; -+ goto err_free_bdev; -+ } -+ -+ poll_dev->private = bdev; -+ poll_dev->poll = gpio_buttons_poll; -+ poll_dev->poll_interval = pdata->poll_interval; -+ -+ input = poll_dev->input; -+ -+ input->evbit[0] = BIT(EV_KEY); -+ input->name = pdev->name; -+ input->phys = "gpio-buttons/input0"; -+ input->dev.parent = &pdev->dev; -+ -+ input->id.bustype = BUS_HOST; -+ input->id.vendor = 0x0001; -+ input->id.product = 0x0001; -+ input->id.version = 0x0100; -+ -+ for (i = 0; i < pdata->nbuttons; i++) { -+ struct gpio_button *button = &pdata->buttons[i]; -+ unsigned int gpio = button->gpio; -+ unsigned int type = button->type ?: EV_KEY; -+ -+ error = gpio_request(gpio, button->desc ? -+ button->desc : DRV_NAME); -+ if (error) { -+ printk(KERN_ERR PFX "unable to claim gpio %u, " -+ "error %d\n", gpio, error); -+ goto err_free_gpio; -+ } -+ -+ error = gpio_direction_input(gpio); -+ if (error) { -+ printk(KERN_ERR PFX "unable to set direction on " -+ "gpio %u, error %d\n", gpio, error); -+ goto err_free_gpio; -+ } -+ -+ input_set_capability(input, type, button->code); -+ bdev->data[i].last_state = gpio_get_value(button->gpio) ? 1 : 0; -+ } -+ -+ bdev->poll_dev = poll_dev; -+ bdev->pdata = pdata; -+ platform_set_drvdata(pdev, bdev); -+ -+ error = input_register_polled_device(poll_dev); -+ if (error) { -+ printk(KERN_ERR PFX "unable to register polled device, " -+ "error %d\n", error); -+ goto err_free_gpio; -+ } -+ -+ return 0; -+ -+err_free_gpio: -+ for (i = i - 1; i >= 0; i--) -+ gpio_free(pdata->buttons[i].gpio); -+ -+ input_free_polled_device(poll_dev); -+ -+err_free_bdev: -+ kfree(bdev); -+ -+ platform_set_drvdata(pdev, NULL); -+ return error; -+} -+ -+static int __devexit gpio_buttons_remove(struct platform_device *pdev) -+{ -+ struct gpio_buttons_dev *bdev = platform_get_drvdata(pdev); -+ struct gpio_buttons_platform_data *pdata = bdev->pdata; -+ int i; -+ -+ input_unregister_polled_device(bdev->poll_dev); -+ -+ for (i = 0; i < pdata->nbuttons; i++) -+ gpio_free(pdata->buttons[i].gpio); -+ -+ input_free_polled_device(bdev->poll_dev); -+ -+ kfree(bdev); -+ platform_set_drvdata(pdev, NULL); -+ -+ return 0; -+} -+ -+static struct platform_driver gpio_buttons_driver = { -+ .probe = gpio_buttons_probe, -+ .remove = __devexit_p(gpio_buttons_remove), -+ .driver = { -+ .name = DRV_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init gpio_buttons_init(void) -+{ -+ printk(KERN_INFO DRV_NAME " driver version " DRV_VERSION "\n"); -+ return platform_driver_register(&gpio_buttons_driver); -+} -+ -+static void __exit gpio_buttons_exit(void) -+{ -+ platform_driver_unregister(&gpio_buttons_driver); -+} -+ -+module_init(gpio_buttons_init); -+module_exit(gpio_buttons_exit); -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_VERSION(DRV_VERSION); -+MODULE_DESCRIPTION("Polled buttons driver for CPU GPIOs"); -+ -diff -Nur linux-2.6.37.orig/drivers/leds/leds-rb750.c linux-2.6.37/drivers/leds/leds-rb750.c ---- linux-2.6.37.orig/drivers/leds/leds-rb750.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/drivers/leds/leds-rb750.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,140 @@ -+/* -+ * LED driver for the RouterBOARD 750 -+ * -+ * Copyright (C) 2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ */ -+#include -+#include -+#include -+#include -+ -+#include -+ -+#define DRV_NAME "leds-rb750" -+ -+struct rb750_led_dev { -+ struct led_classdev cdev; -+ u32 mask; -+ int active_low; -+}; -+ -+struct rb750_led_drvdata { -+ struct rb750_led_dev *led_devs; -+ int num_leds; -+}; -+ -+static inline struct rb750_led_dev *to_rbled(struct led_classdev *led_cdev) -+{ -+ return (struct rb750_led_dev *)container_of(led_cdev, -+ struct rb750_led_dev, cdev); -+} -+ -+static void rb750_led_brightness_set(struct led_classdev *led_cdev, -+ enum led_brightness value) -+{ -+ struct rb750_led_dev *rbled = to_rbled(led_cdev); -+ int level; -+ -+ level = (value == LED_OFF) ? 0 : 1; -+ level ^= rbled->active_low; -+ -+ if (level) -+ rb750_latch_change(0, rbled->mask); -+ else -+ rb750_latch_change(rbled->mask, 0); -+} -+ -+static int __devinit rb750_led_probe(struct platform_device *pdev) -+{ -+ struct rb750_led_platform_data *pdata; -+ struct rb750_led_drvdata *drvdata; -+ int ret = 0; -+ int i; -+ -+ pdata = pdev->dev.platform_data; -+ if (!pdata) -+ return -EINVAL; -+ -+ drvdata = kzalloc(sizeof(struct rb750_led_drvdata) + -+ sizeof(struct rb750_led_dev) * pdata->num_leds, -+ GFP_KERNEL); -+ if (!drvdata) -+ return -ENOMEM; -+ -+ drvdata->num_leds = pdata->num_leds; -+ drvdata->led_devs = (struct rb750_led_dev *) &drvdata[1]; -+ -+ for (i = 0; i < drvdata->num_leds; i++) { -+ struct rb750_led_dev *rbled = &drvdata->led_devs[i]; -+ struct rb750_led_data *led_data = &pdata->leds[i]; -+ -+ rbled->cdev.name = led_data->name; -+ rbled->cdev.default_trigger = led_data->default_trigger; -+ rbled->cdev.brightness_set = rb750_led_brightness_set; -+ rbled->cdev.brightness = LED_OFF; -+ -+ rbled->mask = led_data->mask; -+ rbled->active_low = !!led_data->active_low; -+ -+ ret = led_classdev_register(&pdev->dev, &rbled->cdev); -+ if (ret) -+ goto err; -+ } -+ -+ platform_set_drvdata(pdev, drvdata); -+ return 0; -+ -+ err: -+ for (i = i - 1; i >= 0; i--) -+ led_classdev_unregister(&drvdata->led_devs[i].cdev); -+ -+ kfree(drvdata); -+ return ret; -+} -+ -+static int __devexit rb750_led_remove(struct platform_device *pdev) -+{ -+ struct rb750_led_drvdata *drvdata; -+ int i; -+ -+ drvdata = platform_get_drvdata(pdev); -+ for (i = 0; i < drvdata->num_leds; i++) -+ led_classdev_unregister(&drvdata->led_devs[i].cdev); -+ -+ kfree(drvdata); -+ return 0; -+} -+ -+static struct platform_driver rb750_led_driver = { -+ .probe = rb750_led_probe, -+ .remove = __devexit_p(rb750_led_remove), -+ .driver = { -+ .name = DRV_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+MODULE_ALIAS("platform:leds-rb750"); -+ -+static int __init rb750_led_init(void) -+{ -+ return platform_driver_register(&rb750_led_driver); -+} -+ -+static void __exit rb750_led_exit(void) -+{ -+ platform_driver_unregister(&rb750_led_driver); -+} -+ -+module_init(rb750_led_init); -+module_exit(rb750_led_exit); -+ -+MODULE_DESCRIPTION(DRV_NAME); -+MODULE_DESCRIPTION("LED driver for the RouterBOARD 750"); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_LICENSE("GPL v2"); -diff -Nur linux-2.6.37.orig/drivers/leds/leds-wndr3700-usb.c linux-2.6.37/drivers/leds/leds-wndr3700-usb.c ---- linux-2.6.37.orig/drivers/leds/leds-wndr3700-usb.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/drivers/leds/leds-wndr3700-usb.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,75 @@ -+/* -+ * USB LED driver for the NETGEAR WNDR3700 -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+ -+#include -+ -+#define DRIVER_NAME "wndr3700-led-usb" -+ -+static void wndr3700_usb_led_set(struct led_classdev *cdev, -+ enum led_brightness brightness) -+{ -+ if (brightness) -+ ar71xx_device_start(RESET_MODULE_GE1_PHY); -+ else -+ ar71xx_device_stop(RESET_MODULE_GE1_PHY); -+} -+ -+static enum led_brightness wndr3700_usb_led_get(struct led_classdev *cdev) -+{ -+ return ar71xx_device_stopped(RESET_MODULE_GE1_PHY) ? LED_OFF : LED_FULL; -+} -+ -+static struct led_classdev wndr3700_usb_led = { -+ .name = "wndr3700:green:usb", -+ .brightness_set = wndr3700_usb_led_set, -+ .brightness_get = wndr3700_usb_led_get, -+}; -+ -+static int __devinit wndr3700_usb_led_probe(struct platform_device *pdev) -+{ -+ return led_classdev_register(&pdev->dev, &wndr3700_usb_led); -+} -+ -+static int __devexit wndr3700_usb_led_remove(struct platform_device *pdev) -+{ -+ led_classdev_unregister(&wndr3700_usb_led); -+ return 0; -+} -+ -+static struct platform_driver wndr3700_usb_led_driver = { -+ .probe = wndr3700_usb_led_probe, -+ .remove = __devexit_p(wndr3700_usb_led_remove), -+ .driver = { -+ .name = DRIVER_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init wndr3700_usb_led_init(void) -+{ -+ return platform_driver_register(&wndr3700_usb_led_driver); -+} -+ -+static void __exit wndr3700_usb_led_exit(void) -+{ -+ platform_driver_unregister(&wndr3700_usb_led_driver); -+} -+ -+module_init(wndr3700_usb_led_init); -+module_exit(wndr3700_usb_led_exit); -+ -+MODULE_DESCRIPTION("USB LED driver for the NETGEAR WNDR3700"); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_LICENSE("GPL v2"); -+MODULE_ALIAS("platform:" DRIVER_NAME); -diff -Nur linux-2.6.37.orig/drivers/mtd/maps/Kconfig linux-2.6.37/drivers/mtd/maps/Kconfig ---- linux-2.6.37.orig/drivers/mtd/maps/Kconfig 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/mtd/maps/Kconfig 2011-01-11 20:25:48.000000000 +0100 -@@ -260,6 +260,13 @@ - Support for parsing CFE image tag and creating MTD partitions on - Broadcom BCM63xx boards. - -+config MTD_AR91XX_FLASH -+ tristate "Atheros AR91xx parallel flash support" -+ depends on ATHEROS_AR71XX -+ select MTD_COMPLEX_MAPPINGS -+ help -+ Parallel flash driver for the Atheros AR91xx based boards. -+ - config MTD_DILNETPC - tristate "CFI Flash device mapped on DIL/Net PC" - depends on X86 && MTD_CONCAT && MTD_PARTITIONS && MTD_CFI_INTELEXT && BROKEN -diff -Nur linux-2.6.37.orig/drivers/mtd/maps/Makefile linux-2.6.37/drivers/mtd/maps/Makefile ---- linux-2.6.37.orig/drivers/mtd/maps/Makefile 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/mtd/maps/Makefile 2011-01-11 20:25:48.000000000 +0100 -@@ -7,6 +7,7 @@ - endif - - # Chip mappings -+obj-$(CONFIG_MTD_AR91XX_FLASH) += ar91xx_flash.o - obj-$(CONFIG_MTD_CDB89712) += cdb89712.o - obj-$(CONFIG_MTD_ARM_INTEGRATOR)+= integrator-flash.o - obj-$(CONFIG_MTD_CFI_FLAGADM) += cfi_flagadm.o -diff -Nur linux-2.6.37.orig/drivers/mtd/maps/ar91xx_flash.c linux-2.6.37/drivers/mtd/maps/ar91xx_flash.c ---- linux-2.6.37.orig/drivers/mtd/maps/ar91xx_flash.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/drivers/mtd/maps/ar91xx_flash.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,310 @@ -+/* -+ * Parallel flash driver for the Atheros AR91xx SoC -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#define DRV_NAME "ar91xx-flash" -+ -+struct ar91xx_flash_info { -+ struct mtd_info *mtd; -+ struct map_info map; -+#ifdef CONFIG_MTD_PARTITIONS -+ int nr_parts; -+ struct mtd_partition *parts; -+#endif -+}; -+ -+static map_word ar91xx_flash_read(struct map_info *map, unsigned long ofs) -+{ -+ map_word val; -+ -+ if (map_bankwidth_is_1(map)) -+ val.x[0] = __raw_readb(map->virt + (ofs ^ 3)); -+ else if (map_bankwidth_is_2(map)) -+ val.x[0] = __raw_readw(map->virt + (ofs ^ 2)); -+ else -+ val = map_word_ff(map); -+ -+ return val; -+} -+ -+static void ar91xx_flash_write(struct map_info *map, map_word d, -+ unsigned long ofs) -+{ -+ if (map_bankwidth_is_1(map)) -+ __raw_writeb(d.x[0], map->virt + (ofs ^ 3)); -+ else if (map_bankwidth_is_2(map)) -+ __raw_writew(d.x[0], map->virt + (ofs ^ 2)); -+ -+ mb(); -+} -+ -+static map_word ar91xx_flash_read_lock(struct map_info *map, unsigned long ofs) -+{ -+ map_word ret; -+ -+ ar71xx_flash_acquire(); -+ ret = ar91xx_flash_read(map, ofs); -+ ar71xx_flash_release(); -+ -+ return ret; -+} -+ -+static void ar91xx_flash_write_lock(struct map_info *map, map_word d, -+ unsigned long ofs) -+{ -+ ar71xx_flash_acquire(); -+ ar91xx_flash_write(map, d, ofs); -+ ar71xx_flash_release(); -+} -+ -+static void ar91xx_flash_copy_from_lock(struct map_info *map, void *to, -+ unsigned long from, ssize_t len) -+{ -+ ar71xx_flash_acquire(); -+ inline_map_copy_from(map, to, from, len); -+ ar71xx_flash_release(); -+} -+ -+static void ar91xx_flash_copy_to_lock(struct map_info *map, unsigned long to, -+ const void *from, ssize_t len) -+{ -+ ar71xx_flash_acquire(); -+ inline_map_copy_to(map, to, from, len); -+ ar71xx_flash_release(); -+} -+ -+static int ar91xx_flash_remove(struct platform_device *pdev) -+{ -+ struct ar91xx_flash_platform_data *pdata; -+ struct ar91xx_flash_info *info; -+ -+ info = platform_get_drvdata(pdev); -+ if (info == NULL) -+ return 0; -+ -+ platform_set_drvdata(pdev, NULL); -+ -+ if (info->mtd == NULL) -+ return 0; -+ -+ pdata = pdev->dev.platform_data; -+#ifdef CONFIG_MTD_PARTITIONS -+ if (info->nr_parts) { -+ del_mtd_partitions(info->mtd); -+ kfree(info->parts); -+ } else if (pdata->nr_parts) { -+ del_mtd_partitions(info->mtd); -+ } else { -+ del_mtd_device(info->mtd); -+ } -+#else -+ del_mtd_device(info->mtd); -+#endif -+ map_destroy(info->mtd); -+ -+ return 0; -+} -+ -+static const char *rom_probe_types[] = { "cfi_probe", "jedec_probe", NULL }; -+#ifdef CONFIG_MTD_PARTITIONS -+static const char *part_probe_types[] = { "cmdlinepart", "RedBoot", NULL }; -+#endif -+ -+static int ar91xx_flash_probe(struct platform_device *pdev) -+{ -+ struct ar91xx_flash_platform_data *pdata; -+ struct ar91xx_flash_info *info; -+ struct resource *res; -+ struct resource *region; -+ const char **probe_type; -+ int err = 0; -+ -+ pdata = pdev->dev.platform_data; -+ if (pdata == NULL) -+ return -EINVAL; -+ -+ info = devm_kzalloc(&pdev->dev, sizeof(struct ar91xx_flash_info), -+ GFP_KERNEL); -+ if (info == NULL) { -+ err = -ENOMEM; -+ goto err_out; -+ } -+ -+ platform_set_drvdata(pdev, info); -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (res == NULL) { -+ err = -ENOENT; -+ goto err_out; -+ } -+ -+ dev_info(&pdev->dev, "%.8llx at %.8llx\n", -+ (unsigned long long)(res->end - res->start + 1), -+ (unsigned long long)res->start); -+ -+ region = devm_request_mem_region(&pdev->dev, -+ res->start, res->end - res->start + 1, -+ dev_name(&pdev->dev)); -+ if (region == NULL) { -+ dev_err(&pdev->dev, "could not reserve memory region\n"); -+ err = -ENOMEM; -+ goto err_out; -+ } -+ -+ info->map.name = dev_name(&pdev->dev); -+ info->map.phys = res->start; -+ info->map.size = res->end - res->start + 1; -+ info->map.bankwidth = pdata->width; -+ -+ info->map.virt = devm_ioremap(&pdev->dev, info->map.phys, -+ info->map.size); -+ if (info->map.virt == NULL) { -+ dev_err(&pdev->dev, "failed to ioremap flash region\n"); -+ err = -EIO; -+ goto err_out; -+ } -+ -+ simple_map_init(&info->map); -+ if (pdata->is_shared) { -+ info->map.read = ar91xx_flash_read_lock; -+ info->map.write = ar91xx_flash_write_lock; -+ info->map.copy_from = ar91xx_flash_copy_from_lock; -+ info->map.copy_to = ar91xx_flash_copy_to_lock; -+ } else { -+ info->map.read = ar91xx_flash_read; -+ info->map.write = ar91xx_flash_write; -+ } -+ -+ probe_type = rom_probe_types; -+ for (; info->mtd == NULL && *probe_type != NULL; probe_type++) -+ info->mtd = do_map_probe(*probe_type, &info->map); -+ -+ if (info->mtd == NULL) { -+ dev_err(&pdev->dev, "map_probe failed\n"); -+ err = -ENXIO; -+ goto err_out; -+ } -+ -+ info->mtd->owner = THIS_MODULE; -+ -+#ifdef CONFIG_MTD_PARTITIONS -+ if (pdata->nr_parts) { -+ dev_info(&pdev->dev, "using static partition mapping\n"); -+ add_mtd_partitions(info->mtd, pdata->parts, pdata->nr_parts); -+ return 0; -+ } -+ -+ err = parse_mtd_partitions(info->mtd, part_probe_types, -+ &info->parts, 0); -+ if (err > 0) { -+ add_mtd_partitions(info->mtd, info->parts, err); -+ return 0; -+ } -+#endif -+ -+ add_mtd_device(info->mtd); -+ return 0; -+ -+ err_out: -+ ar91xx_flash_remove(pdev); -+ return err; -+} -+ -+#ifdef CONFIG_PM -+static int ar91xx_flash_suspend(struct platform_device *dev, pm_message_t state) -+{ -+ struct ar91xx_flash_info *info = platform_get_drvdata(dev); -+ int ret = 0; -+ -+ if (info->mtd->suspend) -+ ret = info->mtd->suspend(info->mtd); -+ -+ if (ret) -+ goto fail; -+ -+ return 0; -+ -+ fail: -+ if (info->mtd->suspend) { -+ BUG_ON(!info->mtd->resume); -+ info->mtd->resume(info->mtd); -+ } -+ -+ return ret; -+} -+ -+static int ar91xx_flash_resume(struct platform_device *pdev) -+{ -+ struct ar91xx_flash_info *info = platform_get_drvdata(pdev); -+ -+ if (info->mtd->resume) -+ info->mtd->resume(info->mtd); -+ -+ return 0; -+} -+ -+static void ar91xx_flash_shutdown(struct platform_device *pdev) -+{ -+ struct ar91xx_flash_info *info = platform_get_drvdata(pdev); -+ -+ if (info->mtd->suspend && info->mtd->resume) -+ if (info->mtd->suspend(info->mtd) == 0) -+ info->mtd->resume(info->mtd); -+} -+#else -+#define ar91xx_flash_suspend NULL -+#define ar91xx_flash_resume NULL -+#define ar91xx_flash_shutdown NULL -+#endif -+ -+static struct platform_driver ar91xx_flash_driver = { -+ .probe = ar91xx_flash_probe, -+ .remove = ar91xx_flash_remove, -+ .suspend = ar91xx_flash_suspend, -+ .resume = ar91xx_flash_resume, -+ .shutdown = ar91xx_flash_shutdown, -+ .driver = { -+ .name = DRV_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init ar91xx_flash_init(void) -+{ -+ return platform_driver_register(&ar91xx_flash_driver); -+} -+ -+static void __exit ar91xx_flash_exit(void) -+{ -+ platform_driver_unregister(&ar91xx_flash_driver); -+} -+ -+module_init(ar91xx_flash_init); -+module_exit(ar91xx_flash_exit); -+ -+MODULE_LICENSE("GPL v2"); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_DESCRIPTION("Parallel flash driver for the Atheros AR91xx SoC"); -+MODULE_ALIAS("platform:" DRV_NAME); -diff -Nur linux-2.6.37.orig/drivers/mtd/nand/Kconfig linux-2.6.37/drivers/mtd/nand/Kconfig ---- linux-2.6.37.orig/drivers/mtd/nand/Kconfig 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/mtd/nand/Kconfig 2011-01-11 20:25:48.000000000 +0100 -@@ -532,4 +532,8 @@ - Enables support for NAND Flash chips on the ST Microelectronics - Flexible Static Memory Controller (FSMC) - -+config MTD_NAND_RB4XX -+ tristate "NAND flash driver for RouterBoard 4xx series" -+ depends on MTD_NAND && AR71XX_MACH_RB4XX -+ - endif # MTD_NAND -diff -Nur linux-2.6.37.orig/drivers/mtd/nand/Makefile linux-2.6.37/drivers/mtd/nand/Makefile ---- linux-2.6.37.orig/drivers/mtd/nand/Makefile 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/mtd/nand/Makefile 2011-01-11 20:25:48.000000000 +0100 -@@ -33,6 +33,7 @@ - obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx_nand.o - obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o - obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o -+obj-$(CONFIG_MTD_NAND_RB4XX) += rb4xx_nand.o - obj-$(CONFIG_MTD_ALAUDA) += alauda.o - obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o - obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o -diff -Nur linux-2.6.37.orig/drivers/mtd/nand/rb4xx_nand.c linux-2.6.37/drivers/mtd/nand/rb4xx_nand.c ---- linux-2.6.37.orig/drivers/mtd/nand/rb4xx_nand.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/drivers/mtd/nand/rb4xx_nand.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,513 @@ -+/* -+ * NAND flash driver for the MikroTik RouterBoard 4xx series -+ * -+ * Copyright (C) 2008 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This file was based on the driver for Linux 2.6.22 published by -+ * MikroTik for their RouterBoard 4xx series devices. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#define DRV_NAME "rb4xx-nand" -+#define DRV_VERSION "0.1.10" -+#define DRV_DESC "NAND flash driver for RouterBoard 4xx series" -+ -+#define USE_FAST_READ 1 -+#define USE_FAST_WRITE 1 -+#undef RB4XX_NAND_DEBUG -+ -+#ifdef RB4XX_NAND_DEBUG -+#define DBG(fmt, arg...) printk(KERN_DEBUG DRV_NAME ": " fmt, ## arg) -+#else -+#define DBG(fmt, arg...) do {} while (0) -+#endif -+ -+#define RB4XX_NAND_GPIO_RDY 5 -+#define RB4XX_FLASH_HZ 33333334 -+#define RB4XX_NAND_HZ 33333334 -+ -+#define SPI_CTRL_FASTEST 0x40 -+#define SPI_CTRL_SAFE 0x43 /* 25 MHz for AHB 200 MHz */ -+#define SBIT_IOC_BASE SPI_IOC_CS1 -+#define SBIT_IOC_DO_SHIFT 0 -+#define SBIT_IOC_DO (1u << SBIT_IOC_DO_SHIFT) -+#define SBIT_IOC_DO2_SHIFT 18 -+#define SBIT_IOC_DO2 (1u << SBIT_IOC_DO2_SHIFT) -+ -+#define CPLD_CMD_WRITE_MULT 0x08 /* send cmd, n x send data, read data */ -+#define CPLD_CMD_WRITE_CFG 0x09 /* send cmd, n x send cfg */ -+#define CPLD_CMD_READ_MULT 0x0a /* send cmd, send idle, n x read data */ -+#define CPLD_CMD_READ_FAST 0x0b /* send cmd, 4 x idle, n x read data */ -+ -+#define CFG_BIT_nCE 0x80 -+#define CFG_BIT_CLE 0x40 -+#define CFG_BIT_ALE 0x20 -+#define CFG_BIT_FAN 0x10 -+#define CFG_BIT_nLED4 0x08 -+#define CFG_BIT_nLED3 0x04 -+#define CFG_BIT_nLED2 0x02 -+#define CFG_BIT_nLED1 0x01 -+ -+#define CFG_BIT_nLEDS \ -+ (CFG_BIT_nLED1 | CFG_BIT_nLED2 | CFG_BIT_nLED3 | CFG_BIT_nLED4) -+ -+struct rb4xx_nand_info { -+ struct nand_chip chip; -+ struct mtd_info mtd; -+}; -+ -+/* -+ * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader -+ * will not be able to find the kernel that we load. -+ */ -+static struct nand_ecclayout rb4xx_nand_ecclayout = { -+ .eccbytes = 6, -+ .eccpos = { 8, 9, 10, 13, 14, 15 }, -+ .oobavail = 9, -+ .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } } -+}; -+ -+static struct mtd_partition rb4xx_nand_partitions[] = { -+ { -+ .name = "booter", -+ .offset = 0, -+ .size = (256 * 1024), -+ .mask_flags = MTD_WRITEABLE, -+ }, -+ { -+ .name = "kernel", -+ .offset = (256 * 1024), -+ .size = (4 * 1024 * 1024) - (256 * 1024), -+ }, -+ { -+ .name = "rootfs", -+ .offset = MTDPART_OFS_NXTBLK, -+ .size = (1024*1024*64) - (1024*256) - (4 * 1024 * 1024) -+ }, -+ { -+ .name = "cfgfs", -+ .offset = (1024*1024*64) - (1024*256), -+ .size = (1024*256), -+ }, -+}; -+ -+#if USE_FAST_READ -+#define SPI_NDATA_BASE 0x00800000 -+static unsigned spi_ctrl_fread = SPI_CTRL_SAFE; -+static unsigned spi_ctrl_flash = SPI_CTRL_SAFE; -+extern unsigned mips_hpt_frequency; -+#endif -+ -+static inline unsigned rb4xx_spi_rreg(unsigned r) -+{ -+ return __raw_readl((void * __iomem)(KSEG1ADDR(AR71XX_SPI_BASE) + r)); -+} -+ -+static inline void rb4xx_spi_wreg(unsigned r, unsigned v) -+{ -+ __raw_writel(v, (void * __iomem)(KSEG1ADDR(AR71XX_SPI_BASE) + r)); -+} -+ -+static inline void do_spi_clk(int bit) -+{ -+ unsigned bval = SBIT_IOC_BASE | (bit & 1); -+ -+ rb4xx_spi_wreg(SPI_REG_IOC, bval); -+ rb4xx_spi_wreg(SPI_REG_IOC, bval | SPI_IOC_CLK); -+} -+ -+static void do_spi_byte(uint8_t byte) -+{ -+ do_spi_clk(byte >> 7); -+ do_spi_clk(byte >> 6); -+ do_spi_clk(byte >> 5); -+ do_spi_clk(byte >> 4); -+ do_spi_clk(byte >> 3); -+ do_spi_clk(byte >> 2); -+ do_spi_clk(byte >> 1); -+ do_spi_clk(byte); -+ -+ DBG("spi_byte sent 0x%02x got 0x%x\n", -+ byte, rb4xx_spi_rreg(SPI_REG_RDS)); -+} -+ -+#if USE_FAST_WRITE -+static inline void do_spi_clk_fast(int bit1, int bit2) -+{ -+ unsigned bval = (SBIT_IOC_BASE | -+ ((bit1 << SBIT_IOC_DO_SHIFT) & SBIT_IOC_DO) | -+ ((bit2 << SBIT_IOC_DO2_SHIFT) & SBIT_IOC_DO2)); -+ -+ rb4xx_spi_wreg(SPI_REG_IOC, bval); -+ rb4xx_spi_wreg(SPI_REG_IOC, bval | SPI_IOC_CLK); -+} -+ -+static inline void do_spi_byte_fast(uint8_t byte) -+{ -+ do_spi_clk_fast(byte >> 7, byte >> 6); -+ do_spi_clk_fast(byte >> 5, byte >> 4); -+ do_spi_clk_fast(byte >> 3, byte >> 2); -+ do_spi_clk_fast(byte >> 1, byte >> 0); -+ -+ DBG("spi_byte_fast sent 0x%02x got 0x%x\n", -+ byte, rb4xx_spi_rreg(SPI_REG_RDS)); -+} -+#else -+static inline void do_spi_byte_fast(uint8_t byte) -+{ -+ do_spi_byte(byte); -+} -+#endif /* USE_FAST_WRITE */ -+ -+static int do_spi_cmd(unsigned cmd, unsigned sendCnt, const uint8_t *sendData, -+ unsigned recvCnt, uint8_t *recvData, -+ const uint8_t *verifyData, int fastWrite) -+{ -+ unsigned i; -+ -+ DBG("SPI cmd 0x%x send %u recv %u\n", cmd, sendCnt, recvCnt); -+ -+ rb4xx_spi_wreg(SPI_REG_FS, SPI_FS_GPIO); -+ rb4xx_spi_wreg(SPI_REG_CTRL, SPI_CTRL_FASTEST); -+ -+ do_spi_byte(cmd); -+#if 0 -+ if (cmd == CPLD_CMD_READ_FAST) { -+ do_spi_byte(0x80); -+ do_spi_byte(0); -+ do_spi_byte(0); -+ } -+#endif -+ for (i = 0; i < sendCnt; ++i) { -+ if (fastWrite) -+ do_spi_byte_fast(sendData[i]); -+ else -+ do_spi_byte(sendData[i]); -+ } -+ -+ for (i = 0; i < recvCnt; ++i) { -+ if (fastWrite) -+ do_spi_byte_fast(0); -+ else -+ do_spi_byte(0); -+ -+ if (recvData) { -+ recvData[i] = rb4xx_spi_rreg(SPI_REG_RDS) & 0xff; -+ } else if (verifyData) { -+ if (verifyData[i] != (rb4xx_spi_rreg(SPI_REG_RDS) -+ & 0xff)) -+ break; -+ } -+ } -+ -+ rb4xx_spi_wreg(SPI_REG_IOC, SBIT_IOC_BASE | SPI_IOC_CS0); -+ rb4xx_spi_wreg(SPI_REG_CTRL, spi_ctrl_flash); -+ rb4xx_spi_wreg(SPI_REG_FS, 0); -+ -+ return i == recvCnt; -+} -+ -+static int got_write = 1; -+ -+static void rb4xx_nand_write_data(const uint8_t *byte, unsigned cnt) -+{ -+ do_spi_cmd(CPLD_CMD_WRITE_MULT, cnt, byte, 1, NULL, NULL, 1); -+ got_write = 1; -+} -+ -+static void rb4xx_nand_write_byte(uint8_t byte) -+{ -+ rb4xx_nand_write_data(&byte, 1); -+} -+ -+#if USE_FAST_READ -+static uint8_t *rb4xx_nand_read_getaddr(unsigned cnt) -+{ -+ static unsigned nboffset = 0x100000; -+ unsigned addr; -+ -+ if (got_write) { -+ nboffset = (nboffset + 31) & ~31; -+ if (nboffset >= 0x100000) /* 1MB */ -+ nboffset = 0; -+ -+ got_write = 0; -+ rb4xx_spi_wreg(SPI_REG_FS, SPI_FS_GPIO); -+ rb4xx_spi_wreg(SPI_REG_CTRL, spi_ctrl_fread); -+ rb4xx_spi_wreg(SPI_REG_FS, 0); -+ } -+ -+ addr = KSEG1ADDR(AR71XX_SPI_BASE + SPI_NDATA_BASE) + nboffset; -+ DBG("rb4xx_nand_read_getaddr 0x%x cnt 0x%x\n", addr, cnt); -+ -+ nboffset += cnt; -+ return (uint8_t *)addr; -+} -+ -+static void rb4xx_nand_read_data(uint8_t *buf, unsigned cnt) -+{ -+ unsigned size32 = cnt & ~31; -+ unsigned remain = cnt & 31; -+ -+ if (size32) { -+ uint8_t *addr = rb4xx_nand_read_getaddr(size32); -+ memcpy(buf, (void *)addr, size32); -+ } -+ -+ if (remain) { -+ do_spi_cmd(CPLD_CMD_READ_MULT, 1, buf, remain, -+ buf + size32, NULL, 0); -+ } -+} -+ -+static int rb4xx_nand_verify_data(const uint8_t *buf, unsigned cnt) -+{ -+ unsigned size32 = cnt & ~31; -+ unsigned remain = cnt & 31; -+ -+ if (size32) { -+ uint8_t *addr = rb4xx_nand_read_getaddr(size32); -+ if (memcmp(buf, (void *)addr, size32) != 0) -+ return 0; -+ } -+ -+ if (remain) { -+ return do_spi_cmd(CPLD_CMD_READ_MULT, 1, buf, remain, -+ NULL, buf + size32, 0); -+ } -+ return 1; -+} -+#else /* USE_FAST_READ */ -+static void rb4xx_nand_read_data(uint8_t *buf, unsigned cnt) -+{ -+ do_spi_cmd(CPLD_CMD_READ_MULT, 1, buf, cnt, buf, NULL, 0); -+} -+ -+static int rb4xx_nand_verify_data(const uint8_t *buf, unsigned cnt) -+{ -+ return do_spi_cmd(CPLD_CMD_READ_MULT, 1, buf, cnt, NULL, buf, 0); -+} -+#endif /* USE_FAST_READ */ -+ -+static void rb4xx_nand_write_cfg(uint8_t byte) -+{ -+ do_spi_cmd(CPLD_CMD_WRITE_CFG, 1, &byte, 0, NULL, NULL, 0); -+ got_write = 1; -+} -+ -+static int rb4xx_nand_dev_ready(struct mtd_info *mtd) -+{ -+ return gpio_get_value(RB4XX_NAND_GPIO_RDY); -+} -+ -+static void rb4xx_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, -+ unsigned int ctrl) -+{ -+ if (ctrl & NAND_CTRL_CHANGE) { -+ uint8_t cfg = CFG_BIT_nLEDS; -+ -+ cfg |= (ctrl & NAND_CLE) ? CFG_BIT_CLE : 0; -+ cfg |= (ctrl & NAND_ALE) ? CFG_BIT_ALE : 0; -+ cfg |= (ctrl & NAND_NCE) ? 0 : CFG_BIT_nCE; -+ -+ rb4xx_nand_write_cfg(cfg); -+ } -+ -+ if (cmd != NAND_CMD_NONE) -+ rb4xx_nand_write_byte(cmd); -+} -+ -+static uint8_t rb4xx_nand_read_byte(struct mtd_info *mtd) -+{ -+ uint8_t byte = 0; -+ -+ rb4xx_nand_read_data(&byte, 1); -+ return byte; -+} -+ -+static void rb4xx_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, -+ int len) -+{ -+ rb4xx_nand_write_data(buf, len); -+} -+ -+static void rb4xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, -+ int len) -+{ -+ rb4xx_nand_read_data(buf, len); -+} -+ -+static int rb4xx_nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, -+ int len) -+{ -+ if (!rb4xx_nand_verify_data(buf, len)) -+ return -EFAULT; -+ -+ return 0; -+} -+ -+static unsigned get_spi_ctrl(unsigned hz_max, const char *name) -+{ -+ unsigned div; -+ -+ div = (ar71xx_ahb_freq - 1) / (2 * hz_max); -+ /* -+ * CPU has a bug at (div == 0) - first bit read is random -+ */ -+ if (div == 0) -+ ++div; -+ -+ if (name) { -+ unsigned ahb_khz = (ar71xx_ahb_freq + 500) / 1000; -+ unsigned div_real = 2 * (div + 1); -+ printk(KERN_INFO "%s SPI clock %u kHz (AHB %u kHz / %u)\n", -+ name, -+ ahb_khz / div_real, -+ ahb_khz, div_real); -+ } -+ -+ return SPI_CTRL_FASTEST + div; -+} -+ -+static int __init rb4xx_nand_probe(struct platform_device *pdev) -+{ -+ struct rb4xx_nand_info *info; -+ int ret; -+ -+ printk(KERN_INFO DRV_DESC " version " DRV_VERSION "\n"); -+ -+ ret = gpio_request(RB4XX_NAND_GPIO_RDY, "NAND RDY"); -+ if (ret) { -+ printk(KERN_ERR "rb4xx-nand: gpio request failed\n"); -+ return ret; -+ } -+ -+ ret = gpio_direction_input(RB4XX_NAND_GPIO_RDY); -+ if (ret) { -+ printk(KERN_ERR "rb4xx-nand: unable to set input mode " -+ "on gpio%d\n", RB4XX_NAND_GPIO_RDY); -+ goto err_free_gpio; -+ } -+ -+ info = kzalloc(sizeof(*info), GFP_KERNEL); -+ if (!info) { -+ printk(KERN_ERR "rb4xx-nand: no memory for private data\n"); -+ ret = -ENOMEM; -+ goto err_free_gpio; -+ } -+ -+#if USE_FAST_READ -+ spi_ctrl_fread = get_spi_ctrl(RB4XX_NAND_HZ, "NAND"); -+#endif -+ spi_ctrl_flash = get_spi_ctrl(RB4XX_FLASH_HZ, "FLASH"); -+ -+ rb4xx_nand_write_cfg(CFG_BIT_nLEDS | CFG_BIT_nCE); -+ -+ info->chip.priv = &info; -+ info->mtd.priv = &info->chip; -+ info->mtd.owner = THIS_MODULE; -+ -+ info->chip.cmd_ctrl = rb4xx_nand_cmd_ctrl; -+ info->chip.dev_ready = rb4xx_nand_dev_ready; -+ info->chip.read_byte = rb4xx_nand_read_byte; -+ info->chip.write_buf = rb4xx_nand_write_buf; -+ info->chip.read_buf = rb4xx_nand_read_buf; -+ info->chip.verify_buf = rb4xx_nand_verify_buf; -+ -+ info->chip.chip_delay = 25; -+ info->chip.ecc.mode = NAND_ECC_SOFT; -+ info->chip.options |= NAND_NO_AUTOINCR; -+ -+ platform_set_drvdata(pdev, info); -+ -+ ret = nand_scan_ident(&info->mtd, 1, NULL); -+ if (ret) { -+ ret = -ENXIO; -+ goto err_free_info; -+ } -+ -+ if (info->mtd.writesize == 512) -+ info->chip.ecc.layout = &rb4xx_nand_ecclayout; -+ -+ ret = nand_scan_tail(&info->mtd); -+ if (ret) { -+ return -ENXIO; -+ goto err_set_drvdata; -+ } -+ -+#ifdef CONFIG_MTD_PARTITIONS -+ ret = add_mtd_partitions(&info->mtd, rb4xx_nand_partitions, -+ ARRAY_SIZE(rb4xx_nand_partitions)); -+#else -+ ret = add_mtd_device(&info->mtd); -+#endif -+ if (ret) -+ goto err_release_nand; -+ -+ return 0; -+ -+err_release_nand: -+ nand_release(&info->mtd); -+err_set_drvdata: -+ platform_set_drvdata(pdev, NULL); -+err_free_info: -+ kfree(info); -+err_free_gpio: -+ gpio_free(RB4XX_NAND_GPIO_RDY); -+ return ret; -+} -+ -+static int __devexit rb4xx_nand_remove(struct platform_device *pdev) -+{ -+ struct rb4xx_nand_info *info = platform_get_drvdata(pdev); -+ -+ nand_release(&info->mtd); -+ platform_set_drvdata(pdev, NULL); -+ kfree(info); -+ -+ return 0; -+} -+ -+static struct platform_driver rb4xx_nand_driver = { -+ .probe = rb4xx_nand_probe, -+ .remove = __devexit_p(rb4xx_nand_remove), -+ .driver = { -+ .name = DRV_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init rb4xx_nand_init(void) -+{ -+ return platform_driver_register(&rb4xx_nand_driver); -+} -+ -+static void __exit rb4xx_nand_exit(void) -+{ -+ platform_driver_unregister(&rb4xx_nand_driver); -+} -+ -+module_init(rb4xx_nand_init); -+module_exit(rb4xx_nand_exit); -+ -+MODULE_DESCRIPTION(DRV_DESC); -+MODULE_VERSION(DRV_VERSION); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_AUTHOR("Imre Kaloz "); -+MODULE_LICENSE("GPL v2"); -diff -Nur linux-2.6.37.orig/drivers/mtd/nand/rb750_nand.c linux-2.6.37/drivers/mtd/nand/rb750_nand.c ---- linux-2.6.37.orig/drivers/mtd/nand/rb750_nand.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/drivers/mtd/nand/rb750_nand.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,360 @@ -+/* -+ * NAND flash driver for the MikroTik RouterBOARD 750 -+ * -+ * Copyright (C) 2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#define DRV_NAME "rb750-nand" -+#define DRV_VERSION "0.1.0" -+#define DRV_DESC "NAND flash driver for the RouterBOARD 750" -+ -+#define RB750_NAND_IO0 BIT(RB750_GPIO_NAND_IO0) -+#define RB750_NAND_ALE BIT(RB750_GPIO_NAND_ALE) -+#define RB750_NAND_CLE BIT(RB750_GPIO_NAND_CLE) -+#define RB750_NAND_NRE BIT(RB750_GPIO_NAND_NRE) -+#define RB750_NAND_NWE BIT(RB750_GPIO_NAND_NWE) -+#define RB750_NAND_RDY BIT(RB750_GPIO_NAND_RDY) -+#define RB750_NAND_NCE BIT(RB750_GPIO_NAND_NCE) -+ -+#define RB750_NAND_DATA_SHIFT 1 -+#define RB750_NAND_DATA_BITS (0xff << RB750_NAND_DATA_SHIFT) -+#define RB750_NAND_INPUT_BITS (RB750_NAND_DATA_BITS | RB750_NAND_RDY) -+#define RB750_NAND_OUTPUT_BITS (RB750_NAND_ALE | RB750_NAND_CLE | \ -+ RB750_NAND_NRE | RB750_NAND_NWE | \ -+ RB750_NAND_NCE) -+ -+struct rb750_nand_info { -+ struct nand_chip chip; -+ struct mtd_info mtd; -+}; -+ -+/* -+ * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader -+ * will not be able to find the kernel that we load. -+ */ -+static struct nand_ecclayout rb750_nand_ecclayout = { -+ .eccbytes = 6, -+ .eccpos = { 8, 9, 10, 13, 14, 15 }, -+ .oobavail = 9, -+ .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } } -+}; -+ -+static struct mtd_partition rb750_nand_partitions[] = { -+ { -+ .name = "booter", -+ .offset = 0, -+ .size = (256 * 1024), -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "kernel", -+ .offset = (256 * 1024), -+ .size = (4 * 1024 * 1024) - (256 * 1024), -+ }, { -+ .name = "rootfs", -+ .offset = MTDPART_OFS_NXTBLK, -+ .size = MTDPART_SIZ_FULL, -+ }, -+}; -+ -+static void rb750_nand_write(const u8 *buf, unsigned len) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ u32 out; -+ unsigned i; -+ -+ /* set data lines to output mode */ -+ __raw_writel(__raw_readl(base + GPIO_REG_OE) | RB750_NAND_DATA_BITS, -+ base + GPIO_REG_OE); -+ -+ out = __raw_readl(base + GPIO_REG_OUT); -+ out &= ~(RB750_NAND_DATA_BITS | RB750_NAND_NWE); -+ for (i = 0; i != len; i++) { -+ u32 data; -+ -+ data = buf[i]; -+ data <<= RB750_NAND_DATA_SHIFT; -+ data |= out; -+ __raw_writel(data, base + GPIO_REG_OUT); -+ -+ __raw_writel(data | RB750_NAND_NWE, base + GPIO_REG_OUT); -+ /* flush write */ -+ __raw_readl(base + GPIO_REG_OUT); -+ } -+ -+ /* set data lines to input mode */ -+ __raw_writel(__raw_readl(base + GPIO_REG_OE) & ~RB750_NAND_DATA_BITS, -+ base + GPIO_REG_OE); -+ /* flush write */ -+ __raw_readl(base + GPIO_REG_OE); -+} -+ -+static int rb750_nand_read_verify(u8 *read_buf, unsigned len, -+ const u8 *verify_buf) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ unsigned i; -+ -+ for (i = 0; i < len; i++) { -+ u8 data; -+ -+ /* activate RE line */ -+ __raw_writel(RB750_NAND_NRE, base + GPIO_REG_CLEAR); -+ /* flush write */ -+ __raw_readl(base + GPIO_REG_CLEAR); -+ -+ /* read input lines */ -+ data = __raw_readl(base + GPIO_REG_IN) >> RB750_NAND_DATA_SHIFT; -+ -+ /* deactivate RE line */ -+ __raw_writel(RB750_NAND_NRE, base + GPIO_REG_SET); -+ -+ if (read_buf) -+ read_buf[i] = data; -+ else if (verify_buf && verify_buf[i] != data) -+ return -EFAULT; -+ } -+ -+ return 0; -+} -+ -+static void rb750_nand_select_chip(struct mtd_info *mtd, int chip) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ u32 func; -+ -+ func = __raw_readl(base + GPIO_REG_FUNC); -+ if (chip >= 0) { -+ /* disable latch */ -+ rb750_latch_change(RB750_LVC573_LE, 0); -+ -+ /* disable alternate functions */ -+ ar71xx_gpio_function_setup(AR724X_GPIO_FUNC_JTAG_DISABLE, -+ AR724X_GPIO_FUNC_SPI_EN); -+ -+ /* set input mode for data lines */ -+ __raw_writel(__raw_readl(base + GPIO_REG_OE) & -+ ~RB750_NAND_INPUT_BITS, -+ base + GPIO_REG_OE); -+ -+ /* deactivate RE and WE lines */ -+ __raw_writel(RB750_NAND_NRE | RB750_NAND_NWE, -+ base + GPIO_REG_SET); -+ /* flush write */ -+ (void) __raw_readl(base + GPIO_REG_SET); -+ -+ /* activate CE line */ -+ __raw_writel(RB750_NAND_NCE, base + GPIO_REG_CLEAR); -+ } else { -+ /* deactivate CE line */ -+ __raw_writel(RB750_NAND_NCE, base + GPIO_REG_SET); -+ /* flush write */ -+ (void) __raw_readl(base + GPIO_REG_SET); -+ -+ __raw_writel(__raw_readl(base + GPIO_REG_OE) | -+ RB750_NAND_IO0 | RB750_NAND_RDY, -+ base + GPIO_REG_OE); -+ -+ /* restore alternate functions */ -+ ar71xx_gpio_function_setup(AR724X_GPIO_FUNC_SPI_EN, -+ AR724X_GPIO_FUNC_JTAG_DISABLE); -+ -+ /* enable latch */ -+ rb750_latch_change(0, RB750_LVC573_LE); -+ } -+} -+ -+static int rb750_nand_dev_ready(struct mtd_info *mtd) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ -+ return !!(__raw_readl(base + GPIO_REG_IN) & RB750_NAND_RDY); -+} -+ -+static void rb750_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, -+ unsigned int ctrl) -+{ -+ if (ctrl & NAND_CTRL_CHANGE) { -+ void __iomem *base = ar71xx_gpio_base; -+ u32 t; -+ -+ t = __raw_readl(base + GPIO_REG_OUT); -+ -+ t &= ~(RB750_NAND_CLE | RB750_NAND_ALE); -+ t |= (ctrl & NAND_CLE) ? RB750_NAND_CLE : 0; -+ t |= (ctrl & NAND_ALE) ? RB750_NAND_ALE : 0; -+ -+ __raw_writel(t, base + GPIO_REG_OUT); -+ /* flush write */ -+ __raw_readl(base + GPIO_REG_OUT); -+ } -+ -+ if (cmd != NAND_CMD_NONE) { -+ u8 t = cmd; -+ rb750_nand_write(&t, 1); -+ } -+} -+ -+static u8 rb750_nand_read_byte(struct mtd_info *mtd) -+{ -+ u8 data = 0; -+ rb750_nand_read_verify(&data, 1, NULL); -+ return data; -+} -+ -+static void rb750_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len) -+{ -+ rb750_nand_read_verify(buf, len, NULL); -+} -+ -+static void rb750_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len) -+{ -+ rb750_nand_write(buf, len); -+} -+ -+static int rb750_nand_verify_buf(struct mtd_info *mtd, const u8 *buf, int len) -+{ -+ return rb750_nand_read_verify(NULL, len, buf); -+} -+ -+static void __init rb750_nand_gpio_init(void) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ u32 out; -+ -+ out = __raw_readl(base + GPIO_REG_OUT); -+ -+ /* setup output levels */ -+ __raw_writel(RB750_NAND_NCE | RB750_NAND_NRE | RB750_NAND_NWE, -+ base + GPIO_REG_SET); -+ -+ __raw_writel(RB750_NAND_ALE | RB750_NAND_CLE, -+ base + GPIO_REG_CLEAR); -+ -+ /* setup input lines */ -+ __raw_writel(__raw_readl(base + GPIO_REG_OE) & ~(RB750_NAND_INPUT_BITS), -+ base + GPIO_REG_OE); -+ -+ /* setup output lines */ -+ __raw_writel(__raw_readl(base + GPIO_REG_OE) | RB750_NAND_OUTPUT_BITS, -+ base + GPIO_REG_OE); -+ -+ rb750_latch_change(~out & RB750_NAND_IO0, out & RB750_NAND_IO0); -+} -+ -+static int __init rb750_nand_probe(struct platform_device *pdev) -+{ -+ struct rb750_nand_info *info; -+ int ret; -+ -+ printk(KERN_INFO DRV_DESC " version " DRV_VERSION "\n"); -+ -+ rb750_nand_gpio_init(); -+ -+ info = kzalloc(sizeof(*info), GFP_KERNEL); -+ if (!info) -+ return -ENOMEM; -+ -+ info->chip.priv = &info; -+ info->mtd.priv = &info->chip; -+ info->mtd.owner = THIS_MODULE; -+ -+ info->chip.select_chip = rb750_nand_select_chip; -+ info->chip.cmd_ctrl = rb750_nand_cmd_ctrl; -+ info->chip.dev_ready = rb750_nand_dev_ready; -+ info->chip.read_byte = rb750_nand_read_byte; -+ info->chip.write_buf = rb750_nand_write_buf; -+ info->chip.read_buf = rb750_nand_read_buf; -+ info->chip.verify_buf = rb750_nand_verify_buf; -+ -+ info->chip.chip_delay = 25; -+ info->chip.ecc.mode = NAND_ECC_SOFT; -+ info->chip.options |= NAND_NO_AUTOINCR; -+ -+ platform_set_drvdata(pdev, info); -+ -+ ret = nand_scan_ident(&info->mtd, 1); -+ if (ret) { -+ ret = -ENXIO; -+ goto err_free_info; -+ } -+ -+ if (info->mtd.writesize == 512) -+ info->chip.ecc.layout = &rb750_nand_ecclayout; -+ -+ ret = nand_scan_tail(&info->mtd); -+ if (ret) { -+ return -ENXIO; -+ goto err_set_drvdata; -+ } -+ -+#ifdef CONFIG_MTD_PARTITIONS -+ ret = add_mtd_partitions(&info->mtd, rb750_nand_partitions, -+ ARRAY_SIZE(rb750_nand_partitions)); -+#else -+ ret = add_mtd_device(&info->mtd); -+#endif -+ if (ret) -+ goto err_release_nand; -+ -+ return 0; -+ -+ err_release_nand: -+ nand_release(&info->mtd); -+ err_set_drvdata: -+ platform_set_drvdata(pdev, NULL); -+ err_free_info: -+ kfree(info); -+ return ret; -+} -+ -+static int __devexit rb750_nand_remove(struct platform_device *pdev) -+{ -+ struct rb750_nand_info *info = platform_get_drvdata(pdev); -+ -+ nand_release(&info->mtd); -+ platform_set_drvdata(pdev, NULL); -+ kfree(info); -+ -+ return 0; -+} -+ -+static struct platform_driver rb750_nand_driver = { -+ .probe = rb750_nand_probe, -+ .remove = __devexit_p(rb750_nand_remove), -+ .driver = { -+ .name = DRV_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init rb750_nand_init(void) -+{ -+ return platform_driver_register(&rb750_nand_driver); -+} -+ -+static void __exit rb750_nand_exit(void) -+{ -+ platform_driver_unregister(&rb750_nand_driver); -+} -+ -+module_init(rb750_nand_init); -+module_exit(rb750_nand_exit); -+ -+MODULE_DESCRIPTION(DRV_DESC); -+MODULE_VERSION(DRV_VERSION); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_LICENSE("GPL v2"); -diff -Nur linux-2.6.37.orig/drivers/mtd/wrt160nl_part.c linux-2.6.37/drivers/mtd/wrt160nl_part.c ---- linux-2.6.37.orig/drivers/mtd/wrt160nl_part.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/drivers/mtd/wrt160nl_part.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,181 @@ -+/* -+ * Copyright (C) 2009 Christian Daniel -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ * -+ * TRX flash partition table. -+ * Based on ar7 map by Felix Fietkau -+ * -+ */ -+ -+#include -+#include -+#include -+ -+#include -+#include -+ -+struct cybertan_header { -+ char magic[4]; -+ u8 res1[4]; -+ char fw_date[3]; -+ char fw_ver[3]; -+ char id[4]; -+ char hw_ver; -+ char unused; -+ u8 flags[2]; -+ u8 res2[10]; -+}; -+ -+#define TRX_PARTS 6 -+#define TRX_MAGIC 0x30524448 -+#define TRX_MAX_OFFSET 3 -+ -+struct trx_header { -+ uint32_t magic; /* "HDR0" */ -+ uint32_t len; /* Length of file including header */ -+ uint32_t crc32; /* 32-bit CRC from flag_version to end of file */ -+ uint32_t flag_version; /* 0:15 flags, 16:31 version */ -+ uint32_t offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */ -+}; -+ -+#define IH_MAGIC 0x27051956 /* Image Magic Number */ -+#define IH_NMLEN 32 /* Image Name Length */ -+ -+struct uimage_header { -+ uint32_t ih_magic; /* Image Header Magic Number */ -+ uint32_t ih_hcrc; /* Image Header CRC Checksum */ -+ uint32_t ih_time; /* Image Creation Timestamp */ -+ uint32_t ih_size; /* Image Data Size */ -+ uint32_t ih_load; /* Data» Load Address */ -+ uint32_t ih_ep; /* Entry Point Address */ -+ uint32_t ih_dcrc; /* Image Data CRC Checksum */ -+ uint8_t ih_os; /* Operating System */ -+ uint8_t ih_arch; /* CPU architecture */ -+ uint8_t ih_type; /* Image Type */ -+ uint8_t ih_comp; /* Compression Type */ -+ uint8_t ih_name[IH_NMLEN]; /* Image Name */ -+}; -+ -+struct wrt160nl_header { -+ struct cybertan_header cybertan; -+ struct trx_header trx; -+ struct uimage_header uimage; -+} __attribute__ ((packed)); -+ -+static struct mtd_partition trx_parts[TRX_PARTS]; -+ -+static int wrt160nl_parse_partitions(struct mtd_info *master, -+ struct mtd_partition **pparts, -+ unsigned long origin) -+{ -+ struct wrt160nl_header *header; -+ struct trx_header *theader; -+ struct uimage_header *uheader; -+ size_t retlen; -+ unsigned int kernel_len; -+ int ret; -+ -+ header = vmalloc(sizeof(*header)); -+ if (!header) { -+ return -ENOMEM; -+ goto out; -+ } -+ -+ ret = master->read(master, 4 * master->erasesize, sizeof(*header), -+ &retlen, (void *) header); -+ if (ret) -+ goto free_hdr; -+ -+ if (retlen != sizeof(*header)) { -+ ret = -EIO; -+ goto free_hdr; -+ } -+ -+ if (strncmp(header->cybertan.magic, "NL16", 4) != 0) { -+ printk(KERN_NOTICE "%s: no WRT160NL signature found\n", -+ master->name); -+ goto free_hdr; -+ } -+ -+ theader = &header->trx; -+ if (le32_to_cpu(theader->magic) != TRX_MAGIC) { -+ printk(KERN_NOTICE "%s: no TRX header found\n", master->name); -+ goto free_hdr; -+ } -+ -+ uheader = &header->uimage; -+ if (uheader->ih_magic != IH_MAGIC) { -+ printk(KERN_NOTICE "%s: no uImage found\n", master->name); -+ goto free_hdr; -+ } -+ -+ kernel_len = le32_to_cpu(theader->offsets[1]) + sizeof(struct cybertan_header); -+ -+ trx_parts[0].name = "u-boot"; -+ trx_parts[0].offset = 0; -+ trx_parts[0].size = 4 * master->erasesize; -+ trx_parts[0].mask_flags = MTD_WRITEABLE; -+ -+ trx_parts[1].name = "kernel"; -+ trx_parts[1].offset = trx_parts[0].offset + trx_parts[0].size; -+ trx_parts[1].size = kernel_len; -+ trx_parts[1].mask_flags = 0; -+ -+ trx_parts[2].name = "rootfs"; -+ trx_parts[2].offset = trx_parts[1].offset + trx_parts[1].size; -+ trx_parts[2].size = master->size - 6 * master->erasesize - trx_parts[1].size; -+ trx_parts[2].mask_flags = 0; -+ -+ trx_parts[3].name = "nvram"; -+ trx_parts[3].offset = master->size - 2 * master->erasesize; -+ trx_parts[3].size = master->erasesize; -+ trx_parts[3].mask_flags = MTD_WRITEABLE; -+ -+ trx_parts[4].name = "art"; -+ trx_parts[4].offset = master->size - master->erasesize; -+ trx_parts[4].size = master->erasesize; -+ trx_parts[4].mask_flags = MTD_WRITEABLE; -+ -+ trx_parts[5].name = "firmware"; -+ trx_parts[5].offset = 4 * master->erasesize; -+ trx_parts[5].size = master->size - 6 * master->erasesize; -+ trx_parts[5].mask_flags = 0; -+ -+ *pparts = trx_parts; -+ ret = TRX_PARTS; -+ -+ free_hdr: -+ vfree(header); -+ out: -+ return ret; -+} -+ -+static struct mtd_part_parser wrt160nl_parser = { -+ .owner = THIS_MODULE, -+ .parse_fn = wrt160nl_parse_partitions, -+ .name = "wrt160nl", -+}; -+ -+static int __init wrt160nl_parser_init(void) -+{ -+ return register_mtd_parser(&wrt160nl_parser); -+} -+ -+module_init(wrt160nl_parser_init); -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Christian Daniel "); -diff -Nur linux-2.6.37.orig/drivers/net/Kconfig linux-2.6.37/drivers/net/Kconfig ---- linux-2.6.37.orig/drivers/net/Kconfig 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/net/Kconfig 2011-01-11 20:25:48.000000000 +0100 -@@ -2068,6 +2068,8 @@ - - The safe and default value for this is N. - -+source drivers/net/ag71xx/Kconfig -+ - config DL2K - tristate "DL2000/TC902x-based Gigabit Ethernet support" - depends on PCI -diff -Nur linux-2.6.37.orig/drivers/net/Makefile linux-2.6.37/drivers/net/Makefile ---- linux-2.6.37.orig/drivers/net/Makefile 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/net/Makefile 2011-01-11 20:25:48.000000000 +0100 -@@ -112,6 +112,7 @@ - # end link order section - # - -+obj-$(CONFIG_AG71XX) += ag71xx/ - obj-$(CONFIG_SUNDANCE) += sundance.o - obj-$(CONFIG_HAMACHI) += hamachi.o - obj-$(CONFIG_NET) += Space.o loopback.o -diff -Nur linux-2.6.37.orig/drivers/net/ag71xx/Kconfig linux-2.6.37/drivers/net/ag71xx/Kconfig ---- linux-2.6.37.orig/drivers/net/ag71xx/Kconfig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/drivers/net/ag71xx/Kconfig 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,33 @@ -+config AG71XX -+ tristate "Atheros AR71xx built-in ethernet mac support" -+ depends on ATHEROS_AR71XX -+ select PHYLIB -+ help -+ If you wish to compile a kernel for AR71xx/91xx and enable -+ ethernet support, then you should always answer Y to this. -+ -+if AG71XX -+ -+config AG71XX_DEBUG -+ bool "Atheros AR71xx built-in ethernet driver debugging" -+ default n -+ help -+ Atheros AR71xx built-in ethernet driver debugging messages. -+ -+config AG71XX_DEBUG_FS -+ bool "Atheros AR71xx built-in ethernet driver debugfs support" -+ depends on DEBUG_FS -+ default n -+ help -+ Say Y, if you need access to various statistics provided by -+ the ag71xx driver. -+ -+config AG71XX_AR8216_SUPPORT -+ bool "special support for the Atheros AR8216 switch" -+ default n -+ default y if AR71XX_MACH_WNR2000 || AR71XX_MACH_MZK_W04NU -+ help -+ Say 'y' here if you want to enable special support for the -+ Atheros AR8216 switch found on some boards. -+ -+endif -diff -Nur linux-2.6.37.orig/drivers/net/ag71xx/Makefile linux-2.6.37/drivers/net/ag71xx/Makefile ---- linux-2.6.37.orig/drivers/net/ag71xx/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/drivers/net/ag71xx/Makefile 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,14 @@ -+# -+# Makefile for the Atheros AR71xx built-in ethernet macs -+# -+ -+ag71xx-y += ag71xx_main.o -+ag71xx-y += ag71xx_ethtool.o -+ag71xx-y += ag71xx_phy.o -+ag71xx-y += ag71xx_mdio.o -+ -+ag71xx-$(CONFIG_AG71XX_DEBUG_FS) += ag71xx_debugfs.o -+ag71xx-$(CONFIG_AG71XX_AR8216_SUPPORT) += ag71xx_ar8216.o -+ -+obj-$(CONFIG_AG71XX) += ag71xx.o -+ -diff -Nur linux-2.6.37.orig/drivers/net/ag71xx/ag71xx.h linux-2.6.37/drivers/net/ag71xx/ag71xx.h ---- linux-2.6.37.orig/drivers/net/ag71xx/ag71xx.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/drivers/net/ag71xx/ag71xx.h 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,500 @@ -+/* -+ * Atheros AR71xx built-in ethernet mac driver -+ * -+ * Copyright (C) 2008-2010 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Based on Atheros' AG7100 driver -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef __AG71XX_H -+#define __AG71XX_H -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include -+#include -+ -+#define ETH_FCS_LEN 4 -+ -+#define AG71XX_DRV_NAME "ag71xx" -+#define AG71XX_DRV_VERSION "0.5.35" -+ -+#define AG71XX_NAPI_WEIGHT 64 -+#define AG71XX_OOM_REFILL (1 + HZ/10) -+ -+#define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE) -+#define AG71XX_INT_TX (AG71XX_INT_TX_PS) -+#define AG71XX_INT_RX (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF) -+ -+#define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX) -+#define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL) -+ -+#define AG71XX_TX_FIFO_LEN 2048 -+#define AG71XX_TX_MTU_LEN 1536 -+#define AG71XX_RX_PKT_RESERVE 64 -+#define AG71XX_RX_PKT_SIZE \ -+ (AG71XX_RX_PKT_RESERVE + ETH_HLEN + ETH_FRAME_LEN + ETH_FCS_LEN) -+ -+#define AG71XX_TX_RING_SIZE 64 -+#define AG71XX_TX_THRES_STOP (AG71XX_TX_RING_SIZE - 4) -+#define AG71XX_TX_THRES_WAKEUP \ -+ (AG71XX_TX_RING_SIZE - (AG71XX_TX_RING_SIZE / 4)) -+ -+#define AG71XX_RX_RING_SIZE 128 -+ -+#ifdef CONFIG_AG71XX_DEBUG -+#define DBG(fmt, args...) printk(KERN_DEBUG fmt, ## args) -+#else -+#define DBG(fmt, args...) do {} while (0) -+#endif -+ -+#define ag71xx_assert(_cond) \ -+do { \ -+ if (_cond) \ -+ break; \ -+ printk("%s,%d: assertion failed\n", __FILE__, __LINE__); \ -+ BUG(); \ -+} while (0) -+ -+struct ag71xx_desc { -+ u32 data; -+ u32 ctrl; -+#define DESC_EMPTY BIT(31) -+#define DESC_MORE BIT(24) -+#define DESC_PKTLEN_M 0xfff -+ u32 next; -+ u32 pad; -+} __attribute__((aligned(4))); -+ -+struct ag71xx_buf { -+ struct sk_buff *skb; -+ struct ag71xx_desc *desc; -+ dma_addr_t dma_addr; -+ u32 pad; -+}; -+ -+struct ag71xx_ring { -+ struct ag71xx_buf *buf; -+ u8 *descs_cpu; -+ dma_addr_t descs_dma; -+ unsigned int desc_size; -+ unsigned int curr; -+ unsigned int dirty; -+ unsigned int size; -+}; -+ -+struct ag71xx_mdio { -+ struct mii_bus *mii_bus; -+ int mii_irq[PHY_MAX_ADDR]; -+ void __iomem *mdio_base; -+ struct ag71xx_mdio_platform_data *pdata; -+}; -+ -+struct ag71xx_int_stats { -+ unsigned long rx_pr; -+ unsigned long rx_be; -+ unsigned long rx_of; -+ unsigned long tx_ps; -+ unsigned long tx_be; -+ unsigned long tx_ur; -+ unsigned long total; -+}; -+ -+struct ag71xx_napi_stats { -+ unsigned long napi_calls; -+ unsigned long rx_count; -+ unsigned long rx_packets; -+ unsigned long rx_packets_max; -+ unsigned long tx_count; -+ unsigned long tx_packets; -+ unsigned long tx_packets_max; -+ -+ unsigned long rx[AG71XX_NAPI_WEIGHT + 1]; -+ unsigned long tx[AG71XX_NAPI_WEIGHT + 1]; -+}; -+ -+struct ag71xx_debug { -+ struct dentry *debugfs_dir; -+ struct dentry *debugfs_int_stats; -+ struct dentry *debugfs_napi_stats; -+ -+ struct ag71xx_int_stats int_stats; -+ struct ag71xx_napi_stats napi_stats; -+}; -+ -+struct ag71xx { -+ void __iomem *mac_base; -+ void __iomem *mii_ctrl; -+ -+ spinlock_t lock; -+ struct platform_device *pdev; -+ struct net_device *dev; -+ struct napi_struct napi; -+ u32 msg_enable; -+ -+ struct ag71xx_ring rx_ring; -+ struct ag71xx_ring tx_ring; -+ -+ struct mii_bus *mii_bus; -+ struct phy_device *phy_dev; -+ -+ unsigned int link; -+ unsigned int speed; -+ int duplex; -+ -+ struct work_struct restart_work; -+ struct timer_list oom_timer; -+ -+#ifdef CONFIG_AG71XX_DEBUG_FS -+ struct ag71xx_debug debug; -+#endif -+}; -+ -+extern struct ethtool_ops ag71xx_ethtool_ops; -+void ag71xx_link_adjust(struct ag71xx *ag); -+ -+int ag71xx_mdio_driver_init(void) __init; -+void ag71xx_mdio_driver_exit(void); -+ -+int ag71xx_phy_connect(struct ag71xx *ag); -+void ag71xx_phy_disconnect(struct ag71xx *ag); -+void ag71xx_phy_start(struct ag71xx *ag); -+void ag71xx_phy_stop(struct ag71xx *ag); -+ -+static inline struct ag71xx_platform_data *ag71xx_get_pdata(struct ag71xx *ag) -+{ -+ return ag->pdev->dev.platform_data; -+} -+ -+static inline int ag71xx_desc_empty(struct ag71xx_desc *desc) -+{ -+ return ((desc->ctrl & DESC_EMPTY) != 0); -+} -+ -+static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc) -+{ -+ return (desc->ctrl & DESC_PKTLEN_M); -+} -+ -+/* Register offsets */ -+#define AG71XX_REG_MAC_CFG1 0x0000 -+#define AG71XX_REG_MAC_CFG2 0x0004 -+#define AG71XX_REG_MAC_IPG 0x0008 -+#define AG71XX_REG_MAC_HDX 0x000c -+#define AG71XX_REG_MAC_MFL 0x0010 -+#define AG71XX_REG_MII_CFG 0x0020 -+#define AG71XX_REG_MII_CMD 0x0024 -+#define AG71XX_REG_MII_ADDR 0x0028 -+#define AG71XX_REG_MII_CTRL 0x002c -+#define AG71XX_REG_MII_STATUS 0x0030 -+#define AG71XX_REG_MII_IND 0x0034 -+#define AG71XX_REG_MAC_IFCTL 0x0038 -+#define AG71XX_REG_MAC_ADDR1 0x0040 -+#define AG71XX_REG_MAC_ADDR2 0x0044 -+#define AG71XX_REG_FIFO_CFG0 0x0048 -+#define AG71XX_REG_FIFO_CFG1 0x004c -+#define AG71XX_REG_FIFO_CFG2 0x0050 -+#define AG71XX_REG_FIFO_CFG3 0x0054 -+#define AG71XX_REG_FIFO_CFG4 0x0058 -+#define AG71XX_REG_FIFO_CFG5 0x005c -+#define AG71XX_REG_FIFO_RAM0 0x0060 -+#define AG71XX_REG_FIFO_RAM1 0x0064 -+#define AG71XX_REG_FIFO_RAM2 0x0068 -+#define AG71XX_REG_FIFO_RAM3 0x006c -+#define AG71XX_REG_FIFO_RAM4 0x0070 -+#define AG71XX_REG_FIFO_RAM5 0x0074 -+#define AG71XX_REG_FIFO_RAM6 0x0078 -+#define AG71XX_REG_FIFO_RAM7 0x007c -+ -+#define AG71XX_REG_TX_CTRL 0x0180 -+#define AG71XX_REG_TX_DESC 0x0184 -+#define AG71XX_REG_TX_STATUS 0x0188 -+#define AG71XX_REG_RX_CTRL 0x018c -+#define AG71XX_REG_RX_DESC 0x0190 -+#define AG71XX_REG_RX_STATUS 0x0194 -+#define AG71XX_REG_INT_ENABLE 0x0198 -+#define AG71XX_REG_INT_STATUS 0x019c -+ -+#define MAC_CFG1_TXE BIT(0) /* Tx Enable */ -+#define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */ -+#define MAC_CFG1_RXE BIT(2) /* Rx Enable */ -+#define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */ -+#define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */ -+#define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */ -+#define MAC_CFG1_LB BIT(8) /* Loopback mode */ -+#define MAC_CFG1_SR BIT(31) /* Soft Reset */ -+ -+#define MAC_CFG2_FDX BIT(0) -+#define MAC_CFG2_CRC_EN BIT(1) -+#define MAC_CFG2_PAD_CRC_EN BIT(2) -+#define MAC_CFG2_LEN_CHECK BIT(4) -+#define MAC_CFG2_HUGE_FRAME_EN BIT(5) -+#define MAC_CFG2_IF_1000 BIT(9) -+#define MAC_CFG2_IF_10_100 BIT(8) -+ -+#define FIFO_CFG0_WTM BIT(0) /* Watermark Module */ -+#define FIFO_CFG0_RXS BIT(1) /* Rx System Module */ -+#define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */ -+#define FIFO_CFG0_TXS BIT(3) /* Tx System Module */ -+#define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */ -+#define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \ -+ | FIFO_CFG0_TXS | FIFO_CFG0_TXF) -+ -+#define FIFO_CFG0_ENABLE_SHIFT 8 -+ -+#define FIFO_CFG4_DE BIT(0) /* Drop Event */ -+#define FIFO_CFG4_DV BIT(1) /* RX_DV Event */ -+#define FIFO_CFG4_FC BIT(2) /* False Carrier */ -+#define FIFO_CFG4_CE BIT(3) /* Code Error */ -+#define FIFO_CFG4_CR BIT(4) /* CRC error */ -+#define FIFO_CFG4_LM BIT(5) /* Length Mismatch */ -+#define FIFO_CFG4_LO BIT(6) /* Length out of range */ -+#define FIFO_CFG4_OK BIT(7) /* Packet is OK */ -+#define FIFO_CFG4_MC BIT(8) /* Multicast Packet */ -+#define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */ -+#define FIFO_CFG4_DR BIT(10) /* Dribble */ -+#define FIFO_CFG4_LE BIT(11) /* Long Event */ -+#define FIFO_CFG4_CF BIT(12) /* Control Frame */ -+#define FIFO_CFG4_PF BIT(13) /* Pause Frame */ -+#define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */ -+#define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */ -+#define FIFO_CFG4_FT BIT(16) /* Frame Truncated */ -+#define FIFO_CFG4_UC BIT(17) /* Unicast Packet */ -+ -+#define FIFO_CFG5_DE BIT(0) /* Drop Event */ -+#define FIFO_CFG5_DV BIT(1) /* RX_DV Event */ -+#define FIFO_CFG5_FC BIT(2) /* False Carrier */ -+#define FIFO_CFG5_CE BIT(3) /* Code Error */ -+#define FIFO_CFG5_LM BIT(4) /* Length Mismatch */ -+#define FIFO_CFG5_LO BIT(5) /* Length Out of Range */ -+#define FIFO_CFG5_OK BIT(6) /* Packet is OK */ -+#define FIFO_CFG5_MC BIT(7) /* Multicast Packet */ -+#define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */ -+#define FIFO_CFG5_DR BIT(9) /* Dribble */ -+#define FIFO_CFG5_CF BIT(10) /* Control Frame */ -+#define FIFO_CFG5_PF BIT(11) /* Pause Frame */ -+#define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */ -+#define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */ -+#define FIFO_CFG5_LE BIT(14) /* Long Event */ -+#define FIFO_CFG5_FT BIT(15) /* Frame Truncated */ -+#define FIFO_CFG5_16 BIT(16) /* unknown */ -+#define FIFO_CFG5_17 BIT(17) /* unknown */ -+#define FIFO_CFG5_SF BIT(18) /* Short Frame */ -+#define FIFO_CFG5_BM BIT(19) /* Byte Mode */ -+ -+#define AG71XX_INT_TX_PS BIT(0) -+#define AG71XX_INT_TX_UR BIT(1) -+#define AG71XX_INT_TX_BE BIT(3) -+#define AG71XX_INT_RX_PR BIT(4) -+#define AG71XX_INT_RX_OF BIT(6) -+#define AG71XX_INT_RX_BE BIT(7) -+ -+#define MAC_IFCTL_SPEED BIT(16) -+ -+#define MII_CFG_CLK_DIV_4 0 -+#define MII_CFG_CLK_DIV_6 2 -+#define MII_CFG_CLK_DIV_8 3 -+#define MII_CFG_CLK_DIV_10 4 -+#define MII_CFG_CLK_DIV_14 5 -+#define MII_CFG_CLK_DIV_20 6 -+#define MII_CFG_CLK_DIV_28 7 -+#define MII_CFG_RESET BIT(31) -+ -+#define MII_CMD_WRITE 0x0 -+#define MII_CMD_READ 0x1 -+#define MII_ADDR_SHIFT 8 -+#define MII_IND_BUSY BIT(0) -+#define MII_IND_INVALID BIT(2) -+ -+#define TX_CTRL_TXE BIT(0) /* Tx Enable */ -+ -+#define TX_STATUS_PS BIT(0) /* Packet Sent */ -+#define TX_STATUS_UR BIT(1) /* Tx Underrun */ -+#define TX_STATUS_BE BIT(3) /* Bus Error */ -+ -+#define RX_CTRL_RXE BIT(0) /* Rx Enable */ -+ -+#define RX_STATUS_PR BIT(0) /* Packet Received */ -+#define RX_STATUS_OF BIT(2) /* Rx Overflow */ -+#define RX_STATUS_BE BIT(3) /* Bus Error */ -+ -+#define MII_CTRL_IF_MASK 3 -+#define MII_CTRL_SPEED_SHIFT 4 -+#define MII_CTRL_SPEED_MASK 3 -+#define MII_CTRL_SPEED_10 0 -+#define MII_CTRL_SPEED_100 1 -+#define MII_CTRL_SPEED_1000 2 -+ -+static inline void ag71xx_check_reg_offset(struct ag71xx *ag, unsigned reg) -+{ -+ switch (reg) { -+ case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL: -+ case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS: -+ break; -+ -+ default: -+ BUG(); -+ } -+} -+ -+static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value) -+{ -+ ag71xx_check_reg_offset(ag, reg); -+ -+ __raw_writel(value, ag->mac_base + reg); -+ /* flush write */ -+ (void) __raw_readl(ag->mac_base + reg); -+} -+ -+static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg) -+{ -+ ag71xx_check_reg_offset(ag, reg); -+ -+ return __raw_readl(ag->mac_base + reg); -+} -+ -+static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask) -+{ -+ void __iomem *r; -+ -+ ag71xx_check_reg_offset(ag, reg); -+ -+ r = ag->mac_base + reg; -+ __raw_writel(__raw_readl(r) | mask, r); -+ /* flush write */ -+ (void)__raw_readl(r); -+} -+ -+static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask) -+{ -+ void __iomem *r; -+ -+ ag71xx_check_reg_offset(ag, reg); -+ -+ r = ag->mac_base + reg; -+ __raw_writel(__raw_readl(r) & ~mask, r); -+ /* flush write */ -+ (void) __raw_readl(r); -+} -+ -+static inline void ag71xx_int_enable(struct ag71xx *ag, u32 ints) -+{ -+ ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints); -+} -+ -+static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints) -+{ -+ ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints); -+} -+ -+static inline void ag71xx_mii_ctrl_wr(struct ag71xx *ag, u32 value) -+{ -+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); -+ -+ if (pdata->is_ar724x) -+ return; -+ -+ __raw_writel(value, ag->mii_ctrl); -+ -+ /* flush write */ -+ __raw_readl(ag->mii_ctrl); -+} -+ -+static inline u32 ag71xx_mii_ctrl_rr(struct ag71xx *ag) -+{ -+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); -+ -+ if (pdata->is_ar724x) -+ return 0xffffffff; -+ -+ return __raw_readl(ag->mii_ctrl); -+} -+ -+static void inline ag71xx_mii_ctrl_set_if(struct ag71xx *ag, -+ unsigned int mii_if) -+{ -+ u32 t; -+ -+ t = ag71xx_mii_ctrl_rr(ag); -+ t &= ~(MII_CTRL_IF_MASK); -+ t |= (mii_if & MII_CTRL_IF_MASK); -+ ag71xx_mii_ctrl_wr(ag, t); -+} -+ -+static void inline ag71xx_mii_ctrl_set_speed(struct ag71xx *ag, -+ unsigned int speed) -+{ -+ u32 t; -+ -+ t = ag71xx_mii_ctrl_rr(ag); -+ t &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT); -+ t |= (speed & MII_CTRL_SPEED_MASK) << MII_CTRL_SPEED_SHIFT; -+ ag71xx_mii_ctrl_wr(ag, t); -+} -+ -+#ifdef CONFIG_AG71XX_AR8216_SUPPORT -+void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb); -+int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb, -+ int pktlen); -+static inline int ag71xx_has_ar8216(struct ag71xx *ag) -+{ -+ return ag71xx_get_pdata(ag)->has_ar8216; -+} -+#else -+static inline void ag71xx_add_ar8216_header(struct ag71xx *ag, -+ struct sk_buff *skb) -+{ -+} -+ -+static inline int ag71xx_remove_ar8216_header(struct ag71xx *ag, -+ struct sk_buff *skb, -+ int pktlen) -+{ -+ return 0; -+} -+static inline int ag71xx_has_ar8216(struct ag71xx *ag) -+{ -+ return 0; -+} -+#endif -+ -+#ifdef CONFIG_AG71XX_DEBUG_FS -+int ag71xx_debugfs_root_init(void); -+void ag71xx_debugfs_root_exit(void); -+int ag71xx_debugfs_init(struct ag71xx *ag); -+void ag71xx_debugfs_exit(struct ag71xx *ag); -+void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, u32 status); -+void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, int rx, int tx); -+#else -+static inline int ag71xx_debugfs_root_init(void) { return 0; } -+static inline void ag71xx_debugfs_root_exit(void) {} -+static inline int ag71xx_debugfs_init(struct ag71xx *ag) { return 0; } -+static inline void ag71xx_debugfs_exit(struct ag71xx *ag) {} -+static inline void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, -+ u32 status) {} -+static inline void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, -+ int rx, int tx) {} -+#endif /* CONFIG_AG71XX_DEBUG_FS */ -+ -+#endif /* _AG71XX_H */ -diff -Nur linux-2.6.37.orig/drivers/net/ag71xx/ag71xx_ar8216.c linux-2.6.37/drivers/net/ag71xx/ag71xx_ar8216.c ---- linux-2.6.37.orig/drivers/net/ag71xx/ag71xx_ar8216.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/drivers/net/ag71xx/ag71xx_ar8216.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,44 @@ -+/* -+ * Atheros AR71xx built-in ethernet mac driver -+ * Special support for the Atheros ar8216 switch chip -+ * -+ * Copyright (C) 2009-2010 Gabor Juhos -+ * -+ * Based on Atheros' AG7100 driver -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include "ag71xx.h" -+ -+#define AR8216_PACKET_TYPE_MASK 0xf -+#define AR8216_PACKET_TYPE_NORMAL 0 -+ -+#define AR8216_HEADER_LEN 2 -+ -+void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb) -+{ -+ skb_push(skb, AR8216_HEADER_LEN); -+ skb->data[0] = 0x10; -+ skb->data[1] = 0x80; -+} -+ -+int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb, -+ int pktlen) -+{ -+ u8 type; -+ -+ type = skb->data[1] & AR8216_PACKET_TYPE_MASK; -+ switch (type) { -+ case AR8216_PACKET_TYPE_NORMAL: -+ break; -+ -+ default: -+ return -EINVAL; -+ } -+ -+ skb_pull(skb, AR8216_HEADER_LEN); -+ return 0; -+} -diff -Nur linux-2.6.37.orig/drivers/net/ag71xx/ag71xx_debugfs.c linux-2.6.37/drivers/net/ag71xx/ag71xx_debugfs.c ---- linux-2.6.37.orig/drivers/net/ag71xx/ag71xx_debugfs.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/drivers/net/ag71xx/ag71xx_debugfs.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,197 @@ -+/* -+ * Atheros AR71xx built-in ethernet mac driver -+ * -+ * Copyright (C) 2008-2010 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Based on Atheros' AG7100 driver -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+ -+#include "ag71xx.h" -+ -+static struct dentry *ag71xx_debugfs_root; -+ -+static int ag71xx_debugfs_generic_open(struct inode *inode, struct file *file) -+{ -+ file->private_data = inode->i_private; -+ return 0; -+} -+ -+void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, u32 status) -+{ -+ if (status) -+ ag->debug.int_stats.total++; -+ if (status & AG71XX_INT_TX_PS) -+ ag->debug.int_stats.tx_ps++; -+ if (status & AG71XX_INT_TX_UR) -+ ag->debug.int_stats.tx_ur++; -+ if (status & AG71XX_INT_TX_BE) -+ ag->debug.int_stats.tx_be++; -+ if (status & AG71XX_INT_RX_PR) -+ ag->debug.int_stats.rx_pr++; -+ if (status & AG71XX_INT_RX_OF) -+ ag->debug.int_stats.rx_of++; -+ if (status & AG71XX_INT_RX_BE) -+ ag->debug.int_stats.rx_be++; -+} -+ -+static ssize_t read_file_int_stats(struct file *file, char __user *user_buf, -+ size_t count, loff_t *ppos) -+{ -+#define PR_INT_STAT(_label, _field) \ -+ len += snprintf(buf + len, sizeof(buf) - len, \ -+ "%20s: %10lu\n", _label, ag->debug.int_stats._field); -+ -+ struct ag71xx *ag = file->private_data; -+ char buf[256]; -+ unsigned int len = 0; -+ -+ PR_INT_STAT("TX Packet Sent", tx_ps); -+ PR_INT_STAT("TX Underrun", tx_ur); -+ PR_INT_STAT("TX Bus Error", tx_be); -+ PR_INT_STAT("RX Packet Received", rx_pr); -+ PR_INT_STAT("RX Overflow", rx_of); -+ PR_INT_STAT("RX Bus Error", rx_be); -+ len += snprintf(buf + len, sizeof(buf) - len, "\n"); -+ PR_INT_STAT("Total", total); -+ -+ return simple_read_from_buffer(user_buf, count, ppos, buf, len); -+#undef PR_INT_STAT -+} -+ -+static const struct file_operations ag71xx_fops_int_stats = { -+ .open = ag71xx_debugfs_generic_open, -+ .read = read_file_int_stats, -+ .owner = THIS_MODULE -+}; -+ -+void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, int rx, int tx) -+{ -+ struct ag71xx_napi_stats *stats = &ag->debug.napi_stats; -+ -+ if (rx) { -+ stats->rx_count++; -+ stats->rx_packets += rx; -+ if (rx <= AG71XX_NAPI_WEIGHT) -+ stats->rx[rx]++; -+ if (rx > stats->rx_packets_max) -+ stats->rx_packets_max = rx; -+ } -+ -+ if (tx) { -+ stats->tx_count++; -+ stats->tx_packets += tx; -+ if (tx <= AG71XX_NAPI_WEIGHT) -+ stats->tx[tx]++; -+ if (tx > stats->tx_packets_max) -+ stats->tx_packets_max = tx; -+ } -+} -+ -+static ssize_t read_file_napi_stats(struct file *file, char __user *user_buf, -+ size_t count, loff_t *ppos) -+{ -+ struct ag71xx *ag = file->private_data; -+ struct ag71xx_napi_stats *stats = &ag->debug.napi_stats; -+ char buf[2048]; -+ unsigned int len = 0; -+ unsigned long rx_avg = 0; -+ unsigned long tx_avg = 0; -+ int i; -+ -+ if (stats->rx_count) -+ rx_avg = stats->rx_packets / stats->rx_count; -+ -+ if (stats->tx_count) -+ tx_avg = stats->tx_packets / stats->tx_count; -+ -+ len += snprintf(buf + len, sizeof(buf) - len, "%3s %10s %10s\n", -+ "len", "rx", "tx"); -+ -+ for (i = 1; i <= AG71XX_NAPI_WEIGHT; i++) -+ len += snprintf(buf + len, sizeof(buf) - len, -+ "%3d: %10lu %10lu\n", -+ i, stats->rx[i], stats->tx[i]); -+ -+ len += snprintf(buf + len, sizeof(buf) - len, "\n"); -+ -+ len += snprintf(buf + len, sizeof(buf) - len, "%3s: %10lu %10lu\n", -+ "sum", stats->rx_count, stats->tx_count); -+ len += snprintf(buf + len, sizeof(buf) - len, "%3s: %10lu %10lu\n", -+ "avg", rx_avg, tx_avg); -+ len += snprintf(buf + len, sizeof(buf) - len, "%3s: %10lu %10lu\n", -+ "max", stats->rx_packets_max, stats->tx_packets_max); -+ len += snprintf(buf + len, sizeof(buf) - len, "%3s: %10lu %10lu\n", -+ "pkt", stats->rx_packets, stats->tx_packets); -+ -+ return simple_read_from_buffer(user_buf, count, ppos, buf, len); -+} -+ -+static const struct file_operations ag71xx_fops_napi_stats = { -+ .open = ag71xx_debugfs_generic_open, -+ .read = read_file_napi_stats, -+ .owner = THIS_MODULE -+}; -+ -+void ag71xx_debugfs_exit(struct ag71xx *ag) -+{ -+ debugfs_remove(ag->debug.debugfs_napi_stats); -+ debugfs_remove(ag->debug.debugfs_int_stats); -+ debugfs_remove(ag->debug.debugfs_dir); -+} -+ -+int ag71xx_debugfs_init(struct ag71xx *ag) -+{ -+ ag->debug.debugfs_dir = debugfs_create_dir(ag->dev->name, -+ ag71xx_debugfs_root); -+ if (!ag->debug.debugfs_dir) -+ goto err; -+ -+ ag->debug.debugfs_int_stats = -+ debugfs_create_file("int_stats", -+ S_IRUGO, -+ ag->debug.debugfs_dir, -+ ag, -+ &ag71xx_fops_int_stats); -+ if (!ag->debug.debugfs_int_stats) -+ goto err; -+ -+ ag->debug.debugfs_napi_stats = -+ debugfs_create_file("napi_stats", -+ S_IRUGO, -+ ag->debug.debugfs_dir, -+ ag, -+ &ag71xx_fops_napi_stats); -+ if (!ag->debug.debugfs_napi_stats) -+ goto err; -+ -+ return 0; -+ -+ err: -+ ag71xx_debugfs_exit(ag); -+ return -ENOMEM; -+} -+ -+int ag71xx_debugfs_root_init(void) -+{ -+ if (ag71xx_debugfs_root) -+ return -EBUSY; -+ -+ ag71xx_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL); -+ if (!ag71xx_debugfs_root) -+ return -ENOENT; -+ -+ return 0; -+} -+ -+void ag71xx_debugfs_root_exit(void) -+{ -+ debugfs_remove(ag71xx_debugfs_root); -+ ag71xx_debugfs_root = NULL; -+} -diff -Nur linux-2.6.37.orig/drivers/net/ag71xx/ag71xx_ethtool.c linux-2.6.37/drivers/net/ag71xx/ag71xx_ethtool.c ---- linux-2.6.37.orig/drivers/net/ag71xx/ag71xx_ethtool.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/drivers/net/ag71xx/ag71xx_ethtool.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,71 @@ -+/* -+ * Atheros AR71xx built-in ethernet mac driver -+ * -+ * Copyright (C) 2008-2010 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Based on Atheros' AG7100 driver -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include "ag71xx.h" -+ -+static int ag71xx_ethtool_get_settings(struct net_device *dev, -+ struct ethtool_cmd *cmd) -+{ -+ struct ag71xx *ag = netdev_priv(dev); -+ struct phy_device *phydev = ag->phy_dev; -+ -+ if (!phydev) -+ return -ENODEV; -+ -+ return phy_ethtool_gset(phydev, cmd); -+} -+ -+static int ag71xx_ethtool_set_settings(struct net_device *dev, -+ struct ethtool_cmd *cmd) -+{ -+ struct ag71xx *ag = netdev_priv(dev); -+ struct phy_device *phydev = ag->phy_dev; -+ -+ if (!phydev) -+ return -ENODEV; -+ -+ return phy_ethtool_sset(phydev, cmd); -+} -+ -+static void ag71xx_ethtool_get_drvinfo(struct net_device *dev, -+ struct ethtool_drvinfo *info) -+{ -+ struct ag71xx *ag = netdev_priv(dev); -+ -+ strcpy(info->driver, ag->pdev->dev.driver->name); -+ strcpy(info->version, AG71XX_DRV_VERSION); -+ strcpy(info->bus_info, dev_name(&ag->pdev->dev)); -+} -+ -+static u32 ag71xx_ethtool_get_msglevel(struct net_device *dev) -+{ -+ struct ag71xx *ag = netdev_priv(dev); -+ -+ return ag->msg_enable; -+} -+ -+static void ag71xx_ethtool_set_msglevel(struct net_device *dev, u32 msg_level) -+{ -+ struct ag71xx *ag = netdev_priv(dev); -+ -+ ag->msg_enable = msg_level; -+} -+ -+struct ethtool_ops ag71xx_ethtool_ops = { -+ .set_settings = ag71xx_ethtool_set_settings, -+ .get_settings = ag71xx_ethtool_get_settings, -+ .get_drvinfo = ag71xx_ethtool_get_drvinfo, -+ .get_msglevel = ag71xx_ethtool_get_msglevel, -+ .set_msglevel = ag71xx_ethtool_set_msglevel, -+ .get_link = ethtool_op_get_link, -+}; -diff -Nur linux-2.6.37.orig/drivers/net/ag71xx/ag71xx_main.c linux-2.6.37/drivers/net/ag71xx/ag71xx_main.c ---- linux-2.6.37.orig/drivers/net/ag71xx/ag71xx_main.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/drivers/net/ag71xx/ag71xx_main.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,1184 @@ -+/* -+ * Atheros AR71xx built-in ethernet mac driver -+ * -+ * Copyright (C) 2008-2010 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Based on Atheros' AG7100 driver -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include "ag71xx.h" -+ -+#define AG71XX_DEFAULT_MSG_ENABLE \ -+ ( NETIF_MSG_DRV \ -+ | NETIF_MSG_PROBE \ -+ | NETIF_MSG_LINK \ -+ | NETIF_MSG_TIMER \ -+ | NETIF_MSG_IFDOWN \ -+ | NETIF_MSG_IFUP \ -+ | NETIF_MSG_RX_ERR \ -+ | NETIF_MSG_TX_ERR ) -+ -+static int ag71xx_msg_level = -1; -+ -+module_param_named(msg_level, ag71xx_msg_level, int, 0); -+MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); -+ -+static void ag71xx_dump_dma_regs(struct ag71xx *ag) -+{ -+ DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n", -+ ag->dev->name, -+ ag71xx_rr(ag, AG71XX_REG_TX_CTRL), -+ ag71xx_rr(ag, AG71XX_REG_TX_DESC), -+ ag71xx_rr(ag, AG71XX_REG_TX_STATUS)); -+ -+ DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n", -+ ag->dev->name, -+ ag71xx_rr(ag, AG71XX_REG_RX_CTRL), -+ ag71xx_rr(ag, AG71XX_REG_RX_DESC), -+ ag71xx_rr(ag, AG71XX_REG_RX_STATUS)); -+} -+ -+static void ag71xx_dump_regs(struct ag71xx *ag) -+{ -+ DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n", -+ ag->dev->name, -+ ag71xx_rr(ag, AG71XX_REG_MAC_CFG1), -+ ag71xx_rr(ag, AG71XX_REG_MAC_CFG2), -+ ag71xx_rr(ag, AG71XX_REG_MAC_IPG), -+ ag71xx_rr(ag, AG71XX_REG_MAC_HDX), -+ ag71xx_rr(ag, AG71XX_REG_MAC_MFL)); -+ DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n", -+ ag->dev->name, -+ ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL), -+ ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1), -+ ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2)); -+ DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n", -+ ag->dev->name, -+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0), -+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1), -+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2)); -+ DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n", -+ ag->dev->name, -+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3), -+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4), -+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5)); -+} -+ -+static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr) -+{ -+ DBG("%s: %s intr=%08x %s%s%s%s%s%s\n", -+ ag->dev->name, label, intr, -+ (intr & AG71XX_INT_TX_PS) ? "TXPS " : "", -+ (intr & AG71XX_INT_TX_UR) ? "TXUR " : "", -+ (intr & AG71XX_INT_TX_BE) ? "TXBE " : "", -+ (intr & AG71XX_INT_RX_PR) ? "RXPR " : "", -+ (intr & AG71XX_INT_RX_OF) ? "RXOF " : "", -+ (intr & AG71XX_INT_RX_BE) ? "RXBE " : ""); -+} -+ -+static void ag71xx_ring_free(struct ag71xx_ring *ring) -+{ -+ kfree(ring->buf); -+ -+ if (ring->descs_cpu) -+ dma_free_coherent(NULL, ring->size * ring->desc_size, -+ ring->descs_cpu, ring->descs_dma); -+} -+ -+static int ag71xx_ring_alloc(struct ag71xx_ring *ring, unsigned int size) -+{ -+ int err; -+ int i; -+ -+ ring->desc_size = sizeof(struct ag71xx_desc); -+ if (ring->desc_size % cache_line_size()) { -+ DBG("ag71xx: ring %p, desc size %u rounded to %u\n", -+ ring, ring->desc_size, -+ roundup(ring->desc_size, cache_line_size())); -+ ring->desc_size = roundup(ring->desc_size, cache_line_size()); -+ } -+ -+ ring->descs_cpu = dma_alloc_coherent(NULL, size * ring->desc_size, -+ &ring->descs_dma, GFP_ATOMIC); -+ if (!ring->descs_cpu) { -+ err = -ENOMEM; -+ goto err; -+ } -+ -+ ring->size = size; -+ -+ ring->buf = kzalloc(size * sizeof(*ring->buf), GFP_KERNEL); -+ if (!ring->buf) { -+ err = -ENOMEM; -+ goto err; -+ } -+ -+ for (i = 0; i < size; i++) { -+ ring->buf[i].desc = (struct ag71xx_desc *)&ring->descs_cpu[i * ring->desc_size]; -+ DBG("ag71xx: ring %p, desc %d at %p\n", -+ ring, i, ring->buf[i].desc); -+ } -+ -+ return 0; -+ -+ err: -+ return err; -+} -+ -+static void ag71xx_ring_tx_clean(struct ag71xx *ag) -+{ -+ struct ag71xx_ring *ring = &ag->tx_ring; -+ struct net_device *dev = ag->dev; -+ -+ while (ring->curr != ring->dirty) { -+ u32 i = ring->dirty % AG71XX_TX_RING_SIZE; -+ -+ if (!ag71xx_desc_empty(ring->buf[i].desc)) { -+ ring->buf[i].desc->ctrl = 0; -+ dev->stats.tx_errors++; -+ } -+ -+ if (ring->buf[i].skb) -+ dev_kfree_skb_any(ring->buf[i].skb); -+ -+ ring->buf[i].skb = NULL; -+ -+ ring->dirty++; -+ } -+ -+ /* flush descriptors */ -+ wmb(); -+ -+} -+ -+static void ag71xx_ring_tx_init(struct ag71xx *ag) -+{ -+ struct ag71xx_ring *ring = &ag->tx_ring; -+ int i; -+ -+ for (i = 0; i < AG71XX_TX_RING_SIZE; i++) { -+ ring->buf[i].desc->next = (u32) (ring->descs_dma + -+ ring->desc_size * ((i + 1) % AG71XX_TX_RING_SIZE)); -+ -+ ring->buf[i].desc->ctrl = DESC_EMPTY; -+ ring->buf[i].skb = NULL; -+ } -+ -+ /* flush descriptors */ -+ wmb(); -+ -+ ring->curr = 0; -+ ring->dirty = 0; -+} -+ -+static void ag71xx_ring_rx_clean(struct ag71xx *ag) -+{ -+ struct ag71xx_ring *ring = &ag->rx_ring; -+ int i; -+ -+ if (!ring->buf) -+ return; -+ -+ for (i = 0; i < AG71XX_RX_RING_SIZE; i++) -+ if (ring->buf[i].skb) { -+ dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr, -+ AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE); -+ kfree_skb(ring->buf[i].skb); -+ } -+} -+ -+static int ag71xx_rx_reserve(struct ag71xx *ag) -+{ -+ int reserve = 0; -+ -+ if (ag71xx_get_pdata(ag)->is_ar724x) { -+ if (!ag71xx_has_ar8216(ag)) -+ reserve = 2; -+ -+ if (ag->phy_dev) -+ reserve += 4 - (ag->phy_dev->pkt_align % 4); -+ -+ reserve %= 4; -+ } -+ -+ return reserve + AG71XX_RX_PKT_RESERVE; -+} -+ -+ -+static int ag71xx_ring_rx_init(struct ag71xx *ag) -+{ -+ struct ag71xx_ring *ring = &ag->rx_ring; -+ unsigned int reserve = ag71xx_rx_reserve(ag); -+ unsigned int i; -+ int ret; -+ -+ ret = 0; -+ for (i = 0; i < AG71XX_RX_RING_SIZE; i++) { -+ ring->buf[i].desc->next = (u32) (ring->descs_dma + -+ ring->desc_size * ((i + 1) % AG71XX_RX_RING_SIZE)); -+ -+ DBG("ag71xx: RX desc at %p, next is %08x\n", -+ ring->buf[i].desc, -+ ring->buf[i].desc->next); -+ } -+ -+ for (i = 0; i < AG71XX_RX_RING_SIZE; i++) { -+ struct sk_buff *skb; -+ dma_addr_t dma_addr; -+ -+ skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + reserve); -+ if (!skb) { -+ ret = -ENOMEM; -+ break; -+ } -+ -+ skb->dev = ag->dev; -+ skb_reserve(skb, reserve); -+ -+ dma_addr = dma_map_single(&ag->dev->dev, skb->data, -+ AG71XX_RX_PKT_SIZE, -+ DMA_FROM_DEVICE); -+ ring->buf[i].skb = skb; -+ ring->buf[i].dma_addr = dma_addr; -+ ring->buf[i].desc->data = (u32) dma_addr; -+ ring->buf[i].desc->ctrl = DESC_EMPTY; -+ } -+ -+ /* flush descriptors */ -+ wmb(); -+ -+ ring->curr = 0; -+ ring->dirty = 0; -+ -+ return ret; -+} -+ -+static int ag71xx_ring_rx_refill(struct ag71xx *ag) -+{ -+ struct ag71xx_ring *ring = &ag->rx_ring; -+ unsigned int reserve = ag71xx_rx_reserve(ag); -+ unsigned int count; -+ -+ count = 0; -+ for (; ring->curr - ring->dirty > 0; ring->dirty++) { -+ unsigned int i; -+ -+ i = ring->dirty % AG71XX_RX_RING_SIZE; -+ -+ if (ring->buf[i].skb == NULL) { -+ dma_addr_t dma_addr; -+ struct sk_buff *skb; -+ -+ skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + reserve); -+ if (skb == NULL) -+ break; -+ -+ skb_reserve(skb, reserve); -+ skb->dev = ag->dev; -+ -+ dma_addr = dma_map_single(&ag->dev->dev, skb->data, -+ AG71XX_RX_PKT_SIZE, -+ DMA_FROM_DEVICE); -+ -+ ring->buf[i].skb = skb; -+ ring->buf[i].dma_addr = dma_addr; -+ ring->buf[i].desc->data = (u32) dma_addr; -+ } -+ -+ ring->buf[i].desc->ctrl = DESC_EMPTY; -+ count++; -+ } -+ -+ /* flush descriptors */ -+ wmb(); -+ -+ DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count); -+ -+ return count; -+} -+ -+static int ag71xx_rings_init(struct ag71xx *ag) -+{ -+ int ret; -+ -+ ret = ag71xx_ring_alloc(&ag->tx_ring, AG71XX_TX_RING_SIZE); -+ if (ret) -+ return ret; -+ -+ ag71xx_ring_tx_init(ag); -+ -+ ret = ag71xx_ring_alloc(&ag->rx_ring, AG71XX_RX_RING_SIZE); -+ if (ret) -+ return ret; -+ -+ ret = ag71xx_ring_rx_init(ag); -+ return ret; -+} -+ -+static void ag71xx_rings_cleanup(struct ag71xx *ag) -+{ -+ ag71xx_ring_rx_clean(ag); -+ ag71xx_ring_free(&ag->rx_ring); -+ -+ ag71xx_ring_tx_clean(ag); -+ ag71xx_ring_free(&ag->tx_ring); -+} -+ -+static unsigned char *ag71xx_speed_str(struct ag71xx *ag) -+{ -+ switch (ag->speed) { -+ case SPEED_1000: -+ return "1000"; -+ case SPEED_100: -+ return "100"; -+ case SPEED_10: -+ return "10"; -+ } -+ -+ return "?"; -+} -+ -+void ag71xx_link_adjust(struct ag71xx *ag) -+{ -+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); -+ u32 cfg2; -+ u32 ifctl; -+ u32 fifo5; -+ u32 mii_speed; -+ -+ if (!ag->link) { -+ netif_carrier_off(ag->dev); -+ if (netif_msg_link(ag)) -+ printk(KERN_INFO "%s: link down\n", ag->dev->name); -+ return; -+ } -+ -+ cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2); -+ cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX); -+ cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0; -+ -+ ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL); -+ ifctl &= ~(MAC_IFCTL_SPEED); -+ -+ fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5); -+ fifo5 &= ~FIFO_CFG5_BM; -+ -+ switch (ag->speed) { -+ case SPEED_1000: -+ mii_speed = MII_CTRL_SPEED_1000; -+ cfg2 |= MAC_CFG2_IF_1000; -+ fifo5 |= FIFO_CFG5_BM; -+ break; -+ case SPEED_100: -+ mii_speed = MII_CTRL_SPEED_100; -+ cfg2 |= MAC_CFG2_IF_10_100; -+ ifctl |= MAC_IFCTL_SPEED; -+ break; -+ case SPEED_10: -+ mii_speed = MII_CTRL_SPEED_10; -+ cfg2 |= MAC_CFG2_IF_10_100; -+ break; -+ default: -+ BUG(); -+ return; -+ } -+ -+ if (pdata->is_ar91xx) -+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x00780fff); -+ else if (pdata->is_ar724x) -+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, pdata->fifo_cfg3); -+ else -+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x008001ff); -+ -+ if (pdata->set_pll) -+ pdata->set_pll(ag->speed); -+ -+ ag71xx_mii_ctrl_set_speed(ag, mii_speed); -+ -+ ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2); -+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5); -+ ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl); -+ -+ netif_carrier_on(ag->dev); -+ if (netif_msg_link(ag)) -+ printk(KERN_INFO "%s: link up (%sMbps/%s duplex)\n", -+ ag->dev->name, -+ ag71xx_speed_str(ag), -+ (DUPLEX_FULL == ag->duplex) ? "Full" : "Half"); -+ -+ DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n", -+ ag->dev->name, -+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0), -+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1), -+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2)); -+ -+ DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n", -+ ag->dev->name, -+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3), -+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4), -+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5)); -+ -+ DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x, mii_ctrl=%#x\n", -+ ag->dev->name, -+ ag71xx_rr(ag, AG71XX_REG_MAC_CFG2), -+ ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL), -+ ag71xx_mii_ctrl_rr(ag)); -+} -+ -+static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac) -+{ -+ u32 t; -+ -+ t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16) -+ | (((u32) mac[3]) << 8) | ((u32) mac[2]); -+ -+ ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t); -+ -+ t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16); -+ ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t); -+} -+ -+static void ag71xx_dma_reset(struct ag71xx *ag) -+{ -+ u32 val; -+ int i; -+ -+ ag71xx_dump_dma_regs(ag); -+ -+ /* stop RX and TX */ -+ ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0); -+ ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0); -+ -+ /* clear descriptor addresses */ -+ ag71xx_wr(ag, AG71XX_REG_TX_DESC, 0); -+ ag71xx_wr(ag, AG71XX_REG_RX_DESC, 0); -+ -+ /* clear pending RX/TX interrupts */ -+ for (i = 0; i < 256; i++) { -+ ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR); -+ ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS); -+ } -+ -+ /* clear pending errors */ -+ ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF); -+ ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR); -+ -+ val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS); -+ if (val) -+ printk(KERN_ALERT "%s: unable to clear DMA Rx status: %08x\n", -+ ag->dev->name, val); -+ -+ val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS); -+ -+ /* mask out reserved bits */ -+ val &= ~0xff000000; -+ -+ if (val) -+ printk(KERN_ALERT "%s: unable to clear DMA Tx status: %08x\n", -+ ag->dev->name, val); -+ -+ ag71xx_dump_dma_regs(ag); -+} -+ -+#define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \ -+ MAC_CFG1_SRX | MAC_CFG1_STX) -+ -+#define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT) -+ -+#define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \ -+ FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \ -+ FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \ -+ FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \ -+ FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \ -+ FIFO_CFG4_VT) -+ -+#define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \ -+ FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \ -+ FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \ -+ FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \ -+ FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \ -+ FIFO_CFG5_17 | FIFO_CFG5_SF) -+ -+static void ag71xx_hw_init(struct ag71xx *ag) -+{ -+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); -+ -+ ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR); -+ udelay(20); -+ -+ ar71xx_device_stop(pdata->reset_bit); -+ mdelay(100); -+ ar71xx_device_start(pdata->reset_bit); -+ mdelay(100); -+ -+ /* setup MAC configuration registers */ -+ if (pdata->is_ar724x) -+ ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, -+ MAC_CFG1_INIT | MAC_CFG1_TFC | MAC_CFG1_RFC); -+ else -+ ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT); -+ -+ ag71xx_sb(ag, AG71XX_REG_MAC_CFG2, -+ MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK); -+ -+ /* setup max frame length */ -+ ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN); -+ -+ /* setup MII interface type */ -+ ag71xx_mii_ctrl_set_if(ag, pdata->mii_if); -+ -+ /* setup FIFO configuration registers */ -+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT); -+ if (pdata->is_ar724x) { -+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1); -+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2); -+ } else { -+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000); -+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff); -+ } -+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT); -+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT); -+ -+ ag71xx_dma_reset(ag); -+} -+ -+static void ag71xx_hw_start(struct ag71xx *ag) -+{ -+ /* start RX engine */ -+ ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE); -+ -+ /* enable interrupts */ -+ ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT); -+} -+ -+static void ag71xx_hw_stop(struct ag71xx *ag) -+{ -+ /* disable all interrupts */ -+ ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0); -+ -+ ag71xx_dma_reset(ag); -+} -+ -+static int ag71xx_open(struct net_device *dev) -+{ -+ struct ag71xx *ag = netdev_priv(dev); -+ int ret; -+ -+ ret = ag71xx_rings_init(ag); -+ if (ret) -+ goto err; -+ -+ napi_enable(&ag->napi); -+ -+ netif_carrier_off(dev); -+ ag71xx_phy_start(ag); -+ -+ ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma); -+ ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma); -+ -+ ag71xx_hw_set_macaddr(ag, dev->dev_addr); -+ -+ ag71xx_hw_start(ag); -+ -+ netif_start_queue(dev); -+ -+ return 0; -+ -+ err: -+ ag71xx_rings_cleanup(ag); -+ return ret; -+} -+ -+static int ag71xx_stop(struct net_device *dev) -+{ -+ struct ag71xx *ag = netdev_priv(dev); -+ unsigned long flags; -+ -+ netif_carrier_off(dev); -+ ag71xx_phy_stop(ag); -+ -+ spin_lock_irqsave(&ag->lock, flags); -+ -+ netif_stop_queue(dev); -+ -+ ag71xx_hw_stop(ag); -+ -+ napi_disable(&ag->napi); -+ del_timer_sync(&ag->oom_timer); -+ -+ spin_unlock_irqrestore(&ag->lock, flags); -+ -+ ag71xx_rings_cleanup(ag); -+ -+ return 0; -+} -+ -+static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb, -+ struct net_device *dev) -+{ -+ struct ag71xx *ag = netdev_priv(dev); -+ struct ag71xx_ring *ring = &ag->tx_ring; -+ struct ag71xx_desc *desc; -+ dma_addr_t dma_addr; -+ int i; -+ -+ i = ring->curr % AG71XX_TX_RING_SIZE; -+ desc = ring->buf[i].desc; -+ -+ if (!ag71xx_desc_empty(desc)) -+ goto err_drop; -+ -+ if (ag71xx_has_ar8216(ag)) -+ ag71xx_add_ar8216_header(ag, skb); -+ -+ if (skb->len <= 0) { -+ DBG("%s: packet len is too small\n", ag->dev->name); -+ goto err_drop; -+ } -+ -+ dma_addr = dma_map_single(&dev->dev, skb->data, skb->len, -+ DMA_TO_DEVICE); -+ -+ ring->buf[i].skb = skb; -+ -+ /* setup descriptor fields */ -+ desc->data = (u32) dma_addr; -+ desc->ctrl = (skb->len & DESC_PKTLEN_M); -+ -+ /* flush descriptor */ -+ wmb(); -+ -+ ring->curr++; -+ if (ring->curr == (ring->dirty + AG71XX_TX_THRES_STOP)) { -+ DBG("%s: tx queue full\n", ag->dev->name); -+ netif_stop_queue(dev); -+ } -+ -+ DBG("%s: packet injected into TX queue\n", ag->dev->name); -+ -+ /* enable TX engine */ -+ ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE); -+ -+ return NETDEV_TX_OK; -+ -+ err_drop: -+ dev->stats.tx_dropped++; -+ -+ dev_kfree_skb(skb); -+ return NETDEV_TX_OK; -+} -+ -+static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) -+{ -+ struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_data; -+ struct ag71xx *ag = netdev_priv(dev); -+ int ret; -+ -+ switch (cmd) { -+ case SIOCETHTOOL: -+ if (ag->phy_dev == NULL) -+ break; -+ -+ spin_lock_irq(&ag->lock); -+ ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data); -+ spin_unlock_irq(&ag->lock); -+ return ret; -+ -+ case SIOCSIFHWADDR: -+ if (copy_from_user -+ (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr))) -+ return -EFAULT; -+ return 0; -+ -+ case SIOCGIFHWADDR: -+ if (copy_to_user -+ (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr))) -+ return -EFAULT; -+ return 0; -+ -+ case SIOCGMIIPHY: -+ case SIOCGMIIREG: -+ case SIOCSMIIREG: -+ if (ag->phy_dev == NULL) -+ break; -+ -+ return phy_mii_ioctl(ag->phy_dev, data, cmd); -+ -+ default: -+ break; -+ } -+ -+ return -EOPNOTSUPP; -+} -+ -+static void ag71xx_oom_timer_handler(unsigned long data) -+{ -+ struct net_device *dev = (struct net_device *) data; -+ struct ag71xx *ag = netdev_priv(dev); -+ -+ napi_schedule(&ag->napi); -+} -+ -+static void ag71xx_tx_timeout(struct net_device *dev) -+{ -+ struct ag71xx *ag = netdev_priv(dev); -+ -+ if (netif_msg_tx_err(ag)) -+ printk(KERN_DEBUG "%s: tx timeout\n", ag->dev->name); -+ -+ schedule_work(&ag->restart_work); -+} -+ -+static void ag71xx_restart_work_func(struct work_struct *work) -+{ -+ struct ag71xx *ag = container_of(work, struct ag71xx, restart_work); -+ -+ ag71xx_stop(ag->dev); -+ ag71xx_open(ag->dev); -+} -+ -+static int ag71xx_tx_packets(struct ag71xx *ag) -+{ -+ struct ag71xx_ring *ring = &ag->tx_ring; -+ int sent; -+ -+ DBG("%s: processing TX ring\n", ag->dev->name); -+ -+ sent = 0; -+ while (ring->dirty != ring->curr) { -+ unsigned int i = ring->dirty % AG71XX_TX_RING_SIZE; -+ struct ag71xx_desc *desc = ring->buf[i].desc; -+ struct sk_buff *skb = ring->buf[i].skb; -+ -+ if (!ag71xx_desc_empty(desc)) -+ break; -+ -+ ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS); -+ -+ ag->dev->stats.tx_bytes += skb->len; -+ ag->dev->stats.tx_packets++; -+ -+ dev_kfree_skb_any(skb); -+ ring->buf[i].skb = NULL; -+ -+ ring->dirty++; -+ sent++; -+ } -+ -+ DBG("%s: %d packets sent out\n", ag->dev->name, sent); -+ -+ if ((ring->curr - ring->dirty) < AG71XX_TX_THRES_WAKEUP) -+ netif_wake_queue(ag->dev); -+ -+ return sent; -+} -+ -+static int ag71xx_rx_packets(struct ag71xx *ag, int limit) -+{ -+ struct net_device *dev = ag->dev; -+ struct ag71xx_ring *ring = &ag->rx_ring; -+ int done = 0; -+ -+ DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n", -+ dev->name, limit, ring->curr, ring->dirty); -+ -+ while (done < limit) { -+ unsigned int i = ring->curr % AG71XX_RX_RING_SIZE; -+ struct ag71xx_desc *desc = ring->buf[i].desc; -+ struct sk_buff *skb; -+ int pktlen; -+ int err = 0; -+ -+ if (ag71xx_desc_empty(desc)) -+ break; -+ -+ if ((ring->dirty + AG71XX_RX_RING_SIZE) == ring->curr) { -+ ag71xx_assert(0); -+ break; -+ } -+ -+ ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR); -+ -+ skb = ring->buf[i].skb; -+ pktlen = ag71xx_desc_pktlen(desc); -+ pktlen -= ETH_FCS_LEN; -+ -+ dma_unmap_single(&dev->dev, ring->buf[i].dma_addr, -+ AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE); -+ -+ dev->last_rx = jiffies; -+ dev->stats.rx_packets++; -+ dev->stats.rx_bytes += pktlen; -+ -+ skb_put(skb, pktlen); -+ if (ag71xx_has_ar8216(ag)) -+ err = ag71xx_remove_ar8216_header(ag, skb, pktlen); -+ -+ if (err) { -+ dev->stats.rx_dropped++; -+ kfree_skb(skb); -+ } else { -+ skb->dev = dev; -+ skb->ip_summed = CHECKSUM_NONE; -+ if (ag->phy_dev) { -+ ag->phy_dev->netif_receive_skb(skb); -+ } else { -+ skb->protocol = eth_type_trans(skb, dev); -+ netif_receive_skb(skb); -+ } -+ } -+ -+ ring->buf[i].skb = NULL; -+ done++; -+ -+ ring->curr++; -+ } -+ -+ ag71xx_ring_rx_refill(ag); -+ -+ DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n", -+ dev->name, ring->curr, ring->dirty, done); -+ -+ return done; -+} -+ -+static int ag71xx_poll(struct napi_struct *napi, int limit) -+{ -+ struct ag71xx *ag = container_of(napi, struct ag71xx, napi); -+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); -+ struct net_device *dev = ag->dev; -+ struct ag71xx_ring *rx_ring; -+ unsigned long flags; -+ u32 status; -+ int tx_done; -+ int rx_done; -+ -+ pdata->ddr_flush(); -+ tx_done = ag71xx_tx_packets(ag); -+ -+ DBG("%s: processing RX ring\n", dev->name); -+ rx_done = ag71xx_rx_packets(ag, limit); -+ -+ ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done); -+ -+ rx_ring = &ag->rx_ring; -+ if (rx_ring->buf[rx_ring->dirty % AG71XX_RX_RING_SIZE].skb == NULL) -+ goto oom; -+ -+ status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS); -+ if (unlikely(status & RX_STATUS_OF)) { -+ ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF); -+ dev->stats.rx_fifo_errors++; -+ -+ /* restart RX */ -+ ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE); -+ } -+ -+ if (rx_done < limit) { -+ if (status & RX_STATUS_PR) -+ goto more; -+ -+ status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS); -+ if (status & TX_STATUS_PS) -+ goto more; -+ -+ DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n", -+ dev->name, rx_done, tx_done, limit); -+ -+ napi_complete(napi); -+ -+ /* enable interrupts */ -+ spin_lock_irqsave(&ag->lock, flags); -+ ag71xx_int_enable(ag, AG71XX_INT_POLL); -+ spin_unlock_irqrestore(&ag->lock, flags); -+ return rx_done; -+ } -+ -+ more: -+ DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n", -+ dev->name, rx_done, tx_done, limit); -+ return rx_done; -+ -+ oom: -+ if (netif_msg_rx_err(ag)) -+ printk(KERN_DEBUG "%s: out of memory\n", dev->name); -+ -+ mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL); -+ napi_complete(napi); -+ return 0; -+} -+ -+static irqreturn_t ag71xx_interrupt(int irq, void *dev_id) -+{ -+ struct net_device *dev = dev_id; -+ struct ag71xx *ag = netdev_priv(dev); -+ u32 status; -+ -+ status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS); -+ ag71xx_dump_intr(ag, "raw", status); -+ -+ if (unlikely(!status)) -+ return IRQ_NONE; -+ -+ if (unlikely(status & AG71XX_INT_ERR)) { -+ if (status & AG71XX_INT_TX_BE) { -+ ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE); -+ dev_err(&dev->dev, "TX BUS error\n"); -+ } -+ if (status & AG71XX_INT_RX_BE) { -+ ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE); -+ dev_err(&dev->dev, "RX BUS error\n"); -+ } -+ } -+ -+ if (likely(status & AG71XX_INT_POLL)) { -+ ag71xx_int_disable(ag, AG71XX_INT_POLL); -+ DBG("%s: enable polling mode\n", dev->name); -+ napi_schedule(&ag->napi); -+ } -+ -+ ag71xx_debugfs_update_int_stats(ag, status); -+ -+ return IRQ_HANDLED; -+} -+ -+static void ag71xx_set_multicast_list(struct net_device *dev) -+{ -+ /* TODO */ -+} -+ -+#ifdef CONFIG_NET_POLL_CONTROLLER -+/* -+ * Polling 'interrupt' - used by things like netconsole to send skbs -+ * without having to re-enable interrupts. It's not called while -+ * the interrupt routine is executing. -+ */ -+static void ag71xx_netpoll(struct net_device *dev) -+{ -+ disable_irq(dev->irq); -+ ag71xx_interrupt(dev->irq, dev); -+ enable_irq(dev->irq); -+} -+#endif -+ -+static const struct net_device_ops ag71xx_netdev_ops = { -+ .ndo_open = ag71xx_open, -+ .ndo_stop = ag71xx_stop, -+ .ndo_start_xmit = ag71xx_hard_start_xmit, -+ .ndo_set_multicast_list = ag71xx_set_multicast_list, -+ .ndo_do_ioctl = ag71xx_do_ioctl, -+ .ndo_tx_timeout = ag71xx_tx_timeout, -+ .ndo_change_mtu = eth_change_mtu, -+ .ndo_set_mac_address = eth_mac_addr, -+ .ndo_validate_addr = eth_validate_addr, -+#ifdef CONFIG_NET_POLL_CONTROLLER -+ .ndo_poll_controller = ag71xx_netpoll, -+#endif -+}; -+ -+static int __init ag71xx_probe(struct platform_device *pdev) -+{ -+ struct net_device *dev; -+ struct resource *res; -+ struct ag71xx *ag; -+ struct ag71xx_platform_data *pdata; -+ int err; -+ -+ pdata = pdev->dev.platform_data; -+ if (!pdata) { -+ dev_err(&pdev->dev, "no platform data specified\n"); -+ err = -ENXIO; -+ goto err_out; -+ } -+ -+ if (pdata->mii_bus_dev == NULL) { -+ dev_err(&pdev->dev, "no MII bus device specified\n"); -+ err = -EINVAL; -+ goto err_out; -+ } -+ -+ dev = alloc_etherdev(sizeof(*ag)); -+ if (!dev) { -+ dev_err(&pdev->dev, "alloc_etherdev failed\n"); -+ err = -ENOMEM; -+ goto err_out; -+ } -+ -+ SET_NETDEV_DEV(dev, &pdev->dev); -+ -+ ag = netdev_priv(dev); -+ ag->pdev = pdev; -+ ag->dev = dev; -+ ag->msg_enable = netif_msg_init(ag71xx_msg_level, -+ AG71XX_DEFAULT_MSG_ENABLE); -+ spin_lock_init(&ag->lock); -+ -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base"); -+ if (!res) { -+ dev_err(&pdev->dev, "no mac_base resource found\n"); -+ err = -ENXIO; -+ goto err_out; -+ } -+ -+ ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1); -+ if (!ag->mac_base) { -+ dev_err(&pdev->dev, "unable to ioremap mac_base\n"); -+ err = -ENOMEM; -+ goto err_free_dev; -+ } -+ -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mii_ctrl"); -+ if (!res) { -+ dev_err(&pdev->dev, "no mii_ctrl resource found\n"); -+ err = -ENXIO; -+ goto err_unmap_base; -+ } -+ -+ ag->mii_ctrl = ioremap_nocache(res->start, res->end - res->start + 1); -+ if (!ag->mii_ctrl) { -+ dev_err(&pdev->dev, "unable to ioremap mii_ctrl\n"); -+ err = -ENOMEM; -+ goto err_unmap_base; -+ } -+ -+ dev->irq = platform_get_irq(pdev, 0); -+ err = request_irq(dev->irq, ag71xx_interrupt, -+ IRQF_DISABLED | IRQF_SAMPLE_RANDOM, -+ dev->name, dev); -+ if (err) { -+ dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq); -+ goto err_unmap_mii_ctrl; -+ } -+ -+ dev->base_addr = (unsigned long)ag->mac_base; -+ dev->netdev_ops = &ag71xx_netdev_ops; -+ dev->ethtool_ops = &ag71xx_ethtool_ops; -+ -+ INIT_WORK(&ag->restart_work, ag71xx_restart_work_func); -+ -+ init_timer(&ag->oom_timer); -+ ag->oom_timer.data = (unsigned long) dev; -+ ag->oom_timer.function = ag71xx_oom_timer_handler; -+ -+ memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN); -+ -+ netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT); -+ -+ err = register_netdev(dev); -+ if (err) { -+ dev_err(&pdev->dev, "unable to register net device\n"); -+ goto err_free_irq; -+ } -+ -+ printk(KERN_INFO "%s: Atheros AG71xx at 0x%08lx, irq %d\n", -+ dev->name, dev->base_addr, dev->irq); -+ -+ ag71xx_dump_regs(ag); -+ -+ ag71xx_hw_init(ag); -+ -+ ag71xx_dump_regs(ag); -+ -+ err = ag71xx_phy_connect(ag); -+ if (err) -+ goto err_unregister_netdev; -+ -+ err = ag71xx_debugfs_init(ag); -+ if (err) -+ goto err_phy_disconnect; -+ -+ platform_set_drvdata(pdev, dev); -+ -+ return 0; -+ -+ err_phy_disconnect: -+ ag71xx_phy_disconnect(ag); -+ err_unregister_netdev: -+ unregister_netdev(dev); -+ err_free_irq: -+ free_irq(dev->irq, dev); -+ err_unmap_mii_ctrl: -+ iounmap(ag->mii_ctrl); -+ err_unmap_base: -+ iounmap(ag->mac_base); -+ err_free_dev: -+ kfree(dev); -+ err_out: -+ platform_set_drvdata(pdev, NULL); -+ return err; -+} -+ -+static int __exit ag71xx_remove(struct platform_device *pdev) -+{ -+ struct net_device *dev = platform_get_drvdata(pdev); -+ -+ if (dev) { -+ struct ag71xx *ag = netdev_priv(dev); -+ -+ ag71xx_debugfs_exit(ag); -+ ag71xx_phy_disconnect(ag); -+ unregister_netdev(dev); -+ free_irq(dev->irq, dev); -+ iounmap(ag->mii_ctrl); -+ iounmap(ag->mac_base); -+ kfree(dev); -+ platform_set_drvdata(pdev, NULL); -+ } -+ -+ return 0; -+} -+ -+static struct platform_driver ag71xx_driver = { -+ .probe = ag71xx_probe, -+ .remove = __exit_p(ag71xx_remove), -+ .driver = { -+ .name = AG71XX_DRV_NAME, -+ } -+}; -+ -+static int __init ag71xx_module_init(void) -+{ -+ int ret; -+ -+ ret = ag71xx_debugfs_root_init(); -+ if (ret) -+ goto err_out; -+ -+ ret = ag71xx_mdio_driver_init(); -+ if (ret) -+ goto err_debugfs_exit; -+ -+ ret = platform_driver_register(&ag71xx_driver); -+ if (ret) -+ goto err_mdio_exit; -+ -+ return 0; -+ -+ err_mdio_exit: -+ ag71xx_mdio_driver_exit(); -+ err_debugfs_exit: -+ ag71xx_debugfs_root_exit(); -+ err_out: -+ return ret; -+} -+ -+static void __exit ag71xx_module_exit(void) -+{ -+ platform_driver_unregister(&ag71xx_driver); -+ ag71xx_mdio_driver_exit(); -+ ag71xx_debugfs_root_exit(); -+} -+ -+module_init(ag71xx_module_init); -+module_exit(ag71xx_module_exit); -+ -+MODULE_VERSION(AG71XX_DRV_VERSION); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_AUTHOR("Imre Kaloz "); -+MODULE_LICENSE("GPL v2"); -+MODULE_ALIAS("platform:" AG71XX_DRV_NAME); -diff -Nur linux-2.6.37.orig/drivers/net/ag71xx/ag71xx_mdio.c linux-2.6.37/drivers/net/ag71xx/ag71xx_mdio.c ---- linux-2.6.37.orig/drivers/net/ag71xx/ag71xx_mdio.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/drivers/net/ag71xx/ag71xx_mdio.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,243 @@ -+/* -+ * Atheros AR71xx built-in ethernet mac driver -+ * -+ * Copyright (C) 2008-2010 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Based on Atheros' AG7100 driver -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include "ag71xx.h" -+ -+#define AG71XX_MDIO_RETRY 1000 -+#define AG71XX_MDIO_DELAY 5 -+ -+static inline void ag71xx_mdio_wr(struct ag71xx_mdio *am, unsigned reg, -+ u32 value) -+{ -+ void __iomem *r; -+ -+ r = am->mdio_base + reg; -+ __raw_writel(value, r); -+ -+ /* flush write */ -+ (void) __raw_readl(r); -+} -+ -+static inline u32 ag71xx_mdio_rr(struct ag71xx_mdio *am, unsigned reg) -+{ -+ return __raw_readl(am->mdio_base + reg); -+} -+ -+static void ag71xx_mdio_dump_regs(struct ag71xx_mdio *am) -+{ -+ DBG("%s: mii_cfg=%08x, mii_cmd=%08x, mii_addr=%08x\n", -+ am->mii_bus->name, -+ ag71xx_mdio_rr(am, AG71XX_REG_MII_CFG), -+ ag71xx_mdio_rr(am, AG71XX_REG_MII_CMD), -+ ag71xx_mdio_rr(am, AG71XX_REG_MII_ADDR)); -+ DBG("%s: mii_ctrl=%08x, mii_status=%08x, mii_ind=%08x\n", -+ am->mii_bus->name, -+ ag71xx_mdio_rr(am, AG71XX_REG_MII_CTRL), -+ ag71xx_mdio_rr(am, AG71XX_REG_MII_STATUS), -+ ag71xx_mdio_rr(am, AG71XX_REG_MII_IND)); -+} -+ -+static int ag71xx_mdio_mii_read(struct ag71xx_mdio *am, int addr, int reg) -+{ -+ int ret; -+ int i; -+ -+ ag71xx_mdio_wr(am, AG71XX_REG_MII_CMD, MII_CMD_WRITE); -+ ag71xx_mdio_wr(am, AG71XX_REG_MII_ADDR, -+ ((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff)); -+ ag71xx_mdio_wr(am, AG71XX_REG_MII_CMD, MII_CMD_READ); -+ -+ i = AG71XX_MDIO_RETRY; -+ while (ag71xx_mdio_rr(am, AG71XX_REG_MII_IND) & MII_IND_BUSY) { -+ if (i-- == 0) { -+ printk(KERN_ERR "%s: mii_read timed out\n", -+ am->mii_bus->name); -+ ret = 0xffff; -+ goto out; -+ } -+ udelay(AG71XX_MDIO_DELAY); -+ } -+ -+ ret = ag71xx_mdio_rr(am, AG71XX_REG_MII_STATUS) & 0xffff; -+ ag71xx_mdio_wr(am, AG71XX_REG_MII_CMD, MII_CMD_WRITE); -+ -+ DBG("mii_read: addr=%04x, reg=%04x, value=%04x\n", addr, reg, ret); -+ -+ out: -+ return ret; -+} -+ -+static void ag71xx_mdio_mii_write(struct ag71xx_mdio *am, -+ int addr, int reg, u16 val) -+{ -+ int i; -+ -+ DBG("mii_write: addr=%04x, reg=%04x, value=%04x\n", addr, reg, val); -+ -+ ag71xx_mdio_wr(am, AG71XX_REG_MII_ADDR, -+ ((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff)); -+ ag71xx_mdio_wr(am, AG71XX_REG_MII_CTRL, val); -+ -+ i = AG71XX_MDIO_RETRY; -+ while (ag71xx_mdio_rr(am, AG71XX_REG_MII_IND) & MII_IND_BUSY) { -+ if (i-- == 0) { -+ printk(KERN_ERR "%s: mii_write timed out\n", -+ am->mii_bus->name); -+ break; -+ } -+ udelay(AG71XX_MDIO_DELAY); -+ } -+} -+ -+static int ag71xx_mdio_reset(struct mii_bus *bus) -+{ -+ struct ag71xx_mdio *am = bus->priv; -+ u32 t; -+ -+ if (am->pdata->is_ar7240) -+ t = MII_CFG_CLK_DIV_6; -+ else -+ t = MII_CFG_CLK_DIV_28; -+ -+ ag71xx_mdio_wr(am, AG71XX_REG_MII_CFG, t | MII_CFG_RESET); -+ udelay(100); -+ -+ ag71xx_mdio_wr(am, AG71XX_REG_MII_CFG, t); -+ udelay(100); -+ -+ return 0; -+} -+ -+static int ag71xx_mdio_read(struct mii_bus *bus, int addr, int reg) -+{ -+ struct ag71xx_mdio *am = bus->priv; -+ -+ return ag71xx_mdio_mii_read(am, addr, reg); -+} -+ -+static int ag71xx_mdio_write(struct mii_bus *bus, int addr, int reg, u16 val) -+{ -+ struct ag71xx_mdio *am = bus->priv; -+ -+ ag71xx_mdio_mii_write(am, addr, reg, val); -+ return 0; -+} -+ -+static int __init ag71xx_mdio_probe(struct platform_device *pdev) -+{ -+ struct ag71xx_mdio_platform_data *pdata; -+ struct ag71xx_mdio *am; -+ struct resource *res; -+ int i; -+ int err; -+ -+ pdata = pdev->dev.platform_data; -+ if (!pdata) { -+ dev_err(&pdev->dev, "no platform data specified\n"); -+ return -EINVAL; -+ } -+ -+ am = kzalloc(sizeof(*am), GFP_KERNEL); -+ if (!am) { -+ err = -ENOMEM; -+ goto err_out; -+ } -+ -+ am->pdata = pdata; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (!res) { -+ dev_err(&pdev->dev, "no iomem resource found\n"); -+ err = -ENXIO; -+ goto err_out; -+ } -+ -+ am->mdio_base = ioremap_nocache(res->start, res->end - res->start + 1); -+ if (!am->mdio_base) { -+ dev_err(&pdev->dev, "unable to ioremap registers\n"); -+ err = -ENOMEM; -+ goto err_free_mdio; -+ } -+ -+ am->mii_bus = mdiobus_alloc(); -+ if (am->mii_bus == NULL) { -+ err = -ENOMEM; -+ goto err_iounmap; -+ } -+ -+ am->mii_bus->name = "ag71xx_mdio"; -+ am->mii_bus->read = ag71xx_mdio_read; -+ am->mii_bus->write = ag71xx_mdio_write; -+ am->mii_bus->reset = ag71xx_mdio_reset; -+ am->mii_bus->irq = am->mii_irq; -+ am->mii_bus->priv = am; -+ am->mii_bus->parent = &pdev->dev; -+ snprintf(am->mii_bus->id, MII_BUS_ID_SIZE, "%s", dev_name(&pdev->dev)); -+ am->mii_bus->phy_mask = pdata->phy_mask; -+ -+ for (i = 0; i < PHY_MAX_ADDR; i++) -+ am->mii_irq[i] = PHY_POLL; -+ -+ ag71xx_mdio_wr(am, AG71XX_REG_MAC_CFG1, 0); -+ -+ err = mdiobus_register(am->mii_bus); -+ if (err) -+ goto err_free_bus; -+ -+ ag71xx_mdio_dump_regs(am); -+ -+ platform_set_drvdata(pdev, am); -+ return 0; -+ -+ err_free_bus: -+ mdiobus_free(am->mii_bus); -+ err_iounmap: -+ iounmap(am->mdio_base); -+ err_free_mdio: -+ kfree(am); -+ err_out: -+ return err; -+} -+ -+static int __exit ag71xx_mdio_remove(struct platform_device *pdev) -+{ -+ struct ag71xx_mdio *am = platform_get_drvdata(pdev); -+ -+ if (am) { -+ mdiobus_unregister(am->mii_bus); -+ mdiobus_free(am->mii_bus); -+ iounmap(am->mdio_base); -+ kfree(am); -+ platform_set_drvdata(pdev, NULL); -+ } -+ -+ return 0; -+} -+ -+static struct platform_driver ag71xx_mdio_driver = { -+ .probe = ag71xx_mdio_probe, -+ .remove = __exit_p(ag71xx_mdio_remove), -+ .driver = { -+ .name = "ag71xx-mdio", -+ } -+}; -+ -+int ag71xx_mdio_driver_init(void) -+{ -+ return platform_driver_register(&ag71xx_mdio_driver); -+} -+ -+void ag71xx_mdio_driver_exit(void) -+{ -+ platform_driver_unregister(&ag71xx_mdio_driver); -+} -diff -Nur linux-2.6.37.orig/drivers/net/ag71xx/ag71xx_phy.c linux-2.6.37/drivers/net/ag71xx/ag71xx_phy.c ---- linux-2.6.37.orig/drivers/net/ag71xx/ag71xx_phy.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/drivers/net/ag71xx/ag71xx_phy.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,213 @@ -+/* -+ * Atheros AR71xx built-in ethernet mac driver -+ * -+ * Copyright (C) 2008-2010 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Based on Atheros' AG7100 driver -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include "ag71xx.h" -+ -+static void ag71xx_phy_link_adjust(struct net_device *dev) -+{ -+ struct ag71xx *ag = netdev_priv(dev); -+ struct phy_device *phydev = ag->phy_dev; -+ unsigned long flags; -+ int status_change = 0; -+ -+ spin_lock_irqsave(&ag->lock, flags); -+ -+ if (phydev->link) { -+ if (ag->duplex != phydev->duplex -+ || ag->speed != phydev->speed) { -+ status_change = 1; -+ } -+ } -+ -+ if (phydev->link != ag->link) -+ status_change = 1; -+ -+ ag->link = phydev->link; -+ ag->duplex = phydev->duplex; -+ ag->speed = phydev->speed; -+ -+ if (status_change) -+ ag71xx_link_adjust(ag); -+ -+ spin_unlock_irqrestore(&ag->lock, flags); -+} -+ -+void ag71xx_phy_start(struct ag71xx *ag) -+{ -+ if (ag->phy_dev) { -+ phy_start(ag->phy_dev); -+ } else { -+ ag->link = 1; -+ ag71xx_link_adjust(ag); -+ } -+} -+ -+void ag71xx_phy_stop(struct ag71xx *ag) -+{ -+ if (ag->phy_dev) { -+ phy_stop(ag->phy_dev); -+ } else { -+ ag->link = 0; -+ ag71xx_link_adjust(ag); -+ } -+} -+ -+static int ag71xx_phy_connect_fixed(struct ag71xx *ag) -+{ -+ struct net_device *dev = ag->dev; -+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); -+ int ret = 0; -+ -+ /* use fixed settings */ -+ switch (pdata->speed) { -+ case SPEED_10: -+ case SPEED_100: -+ case SPEED_1000: -+ break; -+ default: -+ printk(KERN_ERR "%s: invalid speed specified\n", dev->name); -+ ret = -EINVAL; -+ break; -+ } -+ -+ printk(KERN_DEBUG "%s: using fixed link parameters\n", dev->name); -+ -+ ag->duplex = pdata->duplex; -+ ag->speed = pdata->speed; -+ -+ return ret; -+} -+ -+static int ag71xx_phy_connect_multi(struct ag71xx *ag) -+{ -+ struct net_device *dev = ag->dev; -+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); -+ struct phy_device *phydev = NULL; -+ int phy_addr; -+ int ret = 0; -+ -+ for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { -+ if (!(pdata->phy_mask & (1 << phy_addr))) -+ continue; -+ -+ if (ag->mii_bus->phy_map[phy_addr] == NULL) -+ continue; -+ -+ DBG("%s: PHY found at %s, uid=%08x\n", -+ dev->name, -+ dev_name(&ag->mii_bus->phy_map[phy_addr]->dev), -+ ag->mii_bus->phy_map[phy_addr]->phy_id); -+ -+ if (phydev == NULL) -+ phydev = ag->mii_bus->phy_map[phy_addr]; -+ } -+ -+ if (!phydev) { -+ printk(KERN_ERR "%s: no PHY found with phy_mask=%08x\n", -+ dev->name, pdata->phy_mask); -+ return -ENODEV; -+ } -+ -+ ag->phy_dev = phy_connect(dev, dev_name(&phydev->dev), -+ &ag71xx_phy_link_adjust, 0, -+ pdata->phy_if_mode); -+ -+ if (IS_ERR(ag->phy_dev)) { -+ printk(KERN_ERR "%s: could not connect to PHY at %s\n", -+ dev->name, dev_name(&phydev->dev)); -+ return PTR_ERR(ag->phy_dev); -+ } -+ -+ /* mask with MAC supported features */ -+ if (pdata->has_gbit) -+ phydev->supported &= PHY_GBIT_FEATURES; -+ else -+ phydev->supported &= PHY_BASIC_FEATURES; -+ -+ phydev->advertising = phydev->supported; -+ -+ printk(KERN_DEBUG "%s: connected to PHY at %s [uid=%08x, driver=%s]\n", -+ dev->name, dev_name(&phydev->dev), -+ phydev->phy_id, phydev->drv->name); -+ -+ ag->link = 0; -+ ag->speed = 0; -+ ag->duplex = -1; -+ -+ return ret; -+} -+ -+static int dev_is_class(struct device *dev, void *class) -+{ -+ if (dev->class != NULL && !strcmp(dev->class->name, class)) -+ return 1; -+ -+ return 0; -+} -+ -+static struct device *dev_find_class(struct device *parent, char *class) -+{ -+ if (dev_is_class(parent, class)) { -+ get_device(parent); -+ return parent; -+ } -+ -+ return device_find_child(parent, class, dev_is_class); -+} -+ -+static struct mii_bus *dev_to_mii_bus(struct device *dev) -+{ -+ struct device *d; -+ -+ d = dev_find_class(dev, "mdio_bus"); -+ if (d != NULL) { -+ struct mii_bus *bus; -+ -+ bus = to_mii_bus(d); -+ put_device(d); -+ -+ return bus; -+ } -+ -+ return NULL; -+} -+ -+int ag71xx_phy_connect(struct ag71xx *ag) -+{ -+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); -+ -+ ag->mii_bus = dev_to_mii_bus(pdata->mii_bus_dev); -+ if (ag->mii_bus == NULL) { -+ printk(KERN_ERR "%s: unable to find MII bus on device '%s'\n", -+ ag->dev->name, dev_name(pdata->mii_bus_dev)); -+ return -ENODEV; -+ } -+ -+ /* Reset the mdio bus explicitly */ -+ if (ag->mii_bus->reset) { -+ mutex_lock(&ag->mii_bus->mdio_lock); -+ ag->mii_bus->reset(ag->mii_bus); -+ mutex_unlock(&ag->mii_bus->mdio_lock); -+ } -+ -+ if (pdata->phy_mask) -+ return ag71xx_phy_connect_multi(ag); -+ -+ return ag71xx_phy_connect_fixed(ag); -+} -+ -+void ag71xx_phy_disconnect(struct ag71xx *ag) -+{ -+ if (ag->phy_dev) -+ phy_disconnect(ag->phy_dev); -+} -diff -Nur linux-2.6.37.orig/drivers/net/phy/Kconfig linux-2.6.37/drivers/net/phy/Kconfig ---- linux-2.6.37.orig/drivers/net/phy/Kconfig 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/net/phy/Kconfig 2011-01-11 20:25:48.000000000 +0100 -@@ -92,6 +92,10 @@ - ---help--- - Supports the KSZ9021, VSC8201, KS8001 PHYs. - -+config IP175C_PHY -+ tristate "Driver for IC+ IP175C/IP178C switches" -+ select SWCONFIG -+ - config FIXED_PHY - bool "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs" - depends on PHYLIB=y -diff -Nur linux-2.6.37.orig/drivers/net/phy/phy.c linux-2.6.37/drivers/net/phy/phy.c ---- linux-2.6.37.orig/drivers/net/phy/phy.c 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/net/phy/phy.c 2011-01-11 20:25:48.000000000 +0100 -@@ -297,6 +297,50 @@ - } - EXPORT_SYMBOL(phy_ethtool_gset); - -+int phy_ethtool_ioctl(struct phy_device *phydev, void *useraddr) -+{ -+ u32 cmd; -+ int tmp; -+ struct ethtool_cmd ecmd = { ETHTOOL_GSET }; -+ struct ethtool_value edata = { ETHTOOL_GLINK }; -+ -+ if (get_user(cmd, (u32 *) useraddr)) -+ return -EFAULT; -+ -+ switch (cmd) { -+ case ETHTOOL_GSET: -+ phy_ethtool_gset(phydev, &ecmd); -+ if (copy_to_user(useraddr, &ecmd, sizeof(ecmd))) -+ return -EFAULT; -+ return 0; -+ -+ case ETHTOOL_SSET: -+ if (copy_from_user(&ecmd, useraddr, sizeof(ecmd))) -+ return -EFAULT; -+ return phy_ethtool_sset(phydev, &ecmd); -+ -+ case ETHTOOL_NWAY_RST: -+ /* if autoneg is off, it's an error */ -+ tmp = phy_read(phydev, MII_BMCR); -+ if (tmp & BMCR_ANENABLE) { -+ tmp |= (BMCR_ANRESTART); -+ phy_write(phydev, MII_BMCR, tmp); -+ return 0; -+ } -+ return -EINVAL; -+ -+ case ETHTOOL_GLINK: -+ edata.data = (phy_read(phydev, -+ MII_BMSR) & BMSR_LSTATUS) ? 1 : 0; -+ if (copy_to_user(useraddr, &edata, sizeof(edata))) -+ return -EFAULT; -+ return 0; -+ } -+ -+ return -EOPNOTSUPP; -+} -+EXPORT_SYMBOL(phy_ethtool_ioctl); -+ - /** - * phy_mii_ioctl - generic PHY MII ioctl interface - * @phydev: the phy_device struct -@@ -351,7 +395,7 @@ - } - - phy_write(phydev, mii_data->reg_num, val); -- -+ - if (mii_data->reg_num == MII_BMCR && - val & BMCR_RESET && - phydev->drv->config_init) { -@@ -470,7 +514,7 @@ - int idx; - - idx = phy_find_setting(phydev->speed, phydev->duplex); -- -+ - idx++; - - idx = phy_find_valid(idx, phydev->supported); -diff -Nur linux-2.6.37.orig/drivers/net/phy/phy_device.c linux-2.6.37/drivers/net/phy/phy_device.c ---- linux-2.6.37.orig/drivers/net/phy/phy_device.c 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/net/phy/phy_device.c 2011-01-11 20:27:54.000000000 +0100 -@@ -149,6 +149,19 @@ - } - EXPORT_SYMBOL(phy_scan_fixups); - -+static int generic_receive_skb(struct sk_buff *skb) -+{ -+ skb->protocol = eth_type_trans(skb, skb->dev); -+ return netif_receive_skb(skb); -+} -+ -+static int generic_rx(struct sk_buff *skb) -+{ -+ skb->protocol = eth_type_trans(skb, skb->dev); -+ return netif_rx(skb); -+} -+ -+ - static struct phy_device* phy_device_create(struct mii_bus *bus, - int addr, int phy_id) - { -@@ -180,6 +193,8 @@ - dev_set_name(&dev->dev, PHY_ID_FMT, bus->id, addr); - - dev->state = PHY_DOWN; -+ dev->netif_receive_skb = &generic_receive_skb; -+ dev->netif_rx = &generic_rx; - - mutex_init(&dev->lock); - INIT_DELAYED_WORK(&dev->state_queue, phy_state_machine); -diff -Nur linux-2.6.37.orig/drivers/spi/Kconfig linux-2.6.37/drivers/spi/Kconfig ---- linux-2.6.37.orig/drivers/spi/Kconfig 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/spi/Kconfig 2011-01-11 20:25:48.000000000 +0100 -@@ -53,6 +53,13 @@ - - comment "SPI Master Controller Drivers" - -+config SPI_AR71XX -+ tristate "Atheros AR71xx SPI Controller" -+ depends on SPI_MASTER && ATHEROS_AR71XX -+ select SPI_BITBANG -+ help -+ This is the SPI contoller driver for Atheros AR71xx. -+ - config SPI_ATMEL - tristate "Atmel SPI Controller" - depends on (ARCH_AT91 || AVR32) -diff -Nur linux-2.6.37.orig/drivers/spi/Makefile linux-2.6.37/drivers/spi/Makefile ---- linux-2.6.37.orig/drivers/spi/Makefile 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/spi/Makefile 2011-01-11 20:25:48.000000000 +0100 -@@ -9,6 +9,7 @@ - obj-$(CONFIG_SPI_MASTER) += spi.o - - # SPI master controller drivers (bus) -+obj-$(CONFIG_SPI_AR71XX) += ar71xx_spi.o - obj-$(CONFIG_SPI_ATMEL) += atmel_spi.o - obj-$(CONFIG_SPI_BFIN) += spi_bfin5xx.o - obj-$(CONFIG_SPI_BITBANG) += spi_bitbang.o -diff -Nur linux-2.6.37.orig/drivers/spi/ap83_spi.c linux-2.6.37/drivers/spi/ap83_spi.c ---- linux-2.6.37.orig/drivers/spi/ap83_spi.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/drivers/spi/ap83_spi.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,282 @@ -+/* -+ * Atheros AP83 board specific SPI Controller driver -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#define DRV_DESC "Atheros AP83 board SPI Controller driver" -+#define DRV_VERSION "0.1.0" -+#define DRV_NAME "ap83-spi" -+ -+#define AP83_SPI_CLK_HIGH (1 << 23) -+#define AP83_SPI_CLK_LOW 0 -+#define AP83_SPI_MOSI_HIGH (1 << 22) -+#define AP83_SPI_MOSI_LOW 0 -+ -+#define AP83_SPI_GPIO_CS 1 -+#define AP83_SPI_GPIO_MISO 3 -+ -+struct ap83_spi { -+ struct spi_bitbang bitbang; -+ void __iomem *base; -+ u32 addr; -+ -+ struct platform_device *pdev; -+}; -+ -+static inline u32 ap83_spi_rr(struct ap83_spi *sp, u32 reg) -+{ -+ return __raw_readl(sp->base + reg); -+} -+ -+static inline struct ap83_spi *spidev_to_sp(struct spi_device *spi) -+{ -+ return spi_master_get_devdata(spi->master); -+} -+ -+static inline void setsck(struct spi_device *spi, int val) -+{ -+ struct ap83_spi *sp = spidev_to_sp(spi); -+ -+ if (val) -+ sp->addr |= AP83_SPI_CLK_HIGH; -+ else -+ sp->addr &= ~AP83_SPI_CLK_HIGH; -+ -+ dev_dbg(&spi->dev, "addr=%08x, SCK set to %s\n", -+ sp->addr, (val) ? "HIGH" : "LOW"); -+ -+ ap83_spi_rr(sp, sp->addr); -+} -+ -+static inline void setmosi(struct spi_device *spi, int val) -+{ -+ struct ap83_spi *sp = spidev_to_sp(spi); -+ -+ if (val) -+ sp->addr |= AP83_SPI_MOSI_HIGH; -+ else -+ sp->addr &= ~AP83_SPI_MOSI_HIGH; -+ -+ dev_dbg(&spi->dev, "addr=%08x, MOSI set to %s\n", -+ sp->addr, (val) ? "HIGH" : "LOW"); -+ -+ ap83_spi_rr(sp, sp->addr); -+} -+ -+static inline u32 getmiso(struct spi_device *spi) -+{ -+ u32 ret; -+ -+ ret = gpio_get_value(AP83_SPI_GPIO_MISO) ? 1 : 0; -+ dev_dbg(&spi->dev, "get MISO: %d\n", ret); -+ -+ return ret; -+} -+ -+static inline void do_spidelay(struct spi_device *spi, unsigned nsecs) -+{ -+ ndelay(nsecs); -+} -+ -+static void ap83_spi_chipselect(struct spi_device *spi, int on) -+{ -+ struct ap83_spi *sp = spidev_to_sp(spi); -+ -+ dev_dbg(&spi->dev, "set CS to %d\n", (on) ? 0 : 1); -+ -+ if (on) { -+ ar71xx_flash_acquire(); -+ -+ sp->addr = 0; -+ ap83_spi_rr(sp, sp->addr); -+ -+ gpio_set_value(AP83_SPI_GPIO_CS, 0); -+ } else { -+ gpio_set_value(AP83_SPI_GPIO_CS, 1); -+ ar71xx_flash_release(); -+ } -+} -+ -+#define spidelay(nsecs) \ -+ do { \ -+ /* Steal the spi_device pointer from our caller. \ -+ * The bitbang-API should probably get fixed here... */ \ -+ do_spidelay(spi, nsecs); \ -+ } while (0) -+ -+#define EXPAND_BITBANG_TXRX -+#include -+ -+static u32 ap83_spi_txrx_mode0(struct spi_device *spi, -+ unsigned nsecs, u32 word, u8 bits) -+{ -+ dev_dbg(&spi->dev, "TXRX0 word=%08x, bits=%u\n", word, bits); -+ return bitbang_txrx_be_cpha0(spi, nsecs, 0, word, bits); -+} -+ -+static u32 ap83_spi_txrx_mode1(struct spi_device *spi, -+ unsigned nsecs, u32 word, u8 bits) -+{ -+ dev_dbg(&spi->dev, "TXRX1 word=%08x, bits=%u\n", word, bits); -+ return bitbang_txrx_be_cpha1(spi, nsecs, 0, word, bits); -+} -+ -+static u32 ap83_spi_txrx_mode2(struct spi_device *spi, -+ unsigned nsecs, u32 word, u8 bits) -+{ -+ dev_dbg(&spi->dev, "TXRX2 word=%08x, bits=%u\n", word, bits); -+ return bitbang_txrx_be_cpha0(spi, nsecs, 1, word, bits); -+} -+ -+static u32 ap83_spi_txrx_mode3(struct spi_device *spi, -+ unsigned nsecs, u32 word, u8 bits) -+{ -+ dev_dbg(&spi->dev, "TXRX3 word=%08x, bits=%u\n", word, bits); -+ return bitbang_txrx_be_cpha1(spi, nsecs, 1, word, bits); -+} -+ -+static int ap83_spi_probe(struct platform_device *pdev) -+{ -+ struct spi_master *master; -+ struct ap83_spi *sp; -+ struct ap83_spi_platform_data *pdata; -+ struct resource *r; -+ int ret; -+ -+ ret = gpio_request(AP83_SPI_GPIO_MISO, "spi-miso"); -+ if (ret) { -+ dev_err(&pdev->dev, "gpio request failed for MISO\n"); -+ return ret; -+ } -+ -+ ret = gpio_request(AP83_SPI_GPIO_CS, "spi-cs"); -+ if (ret) { -+ dev_err(&pdev->dev, "gpio request failed for CS\n"); -+ goto err_free_miso; -+ } -+ -+ ret = gpio_direction_input(AP83_SPI_GPIO_MISO); -+ if (ret) { -+ dev_err(&pdev->dev, "unable to set direction of MISO\n"); -+ goto err_free_cs; -+ } -+ -+ ret = gpio_direction_output(AP83_SPI_GPIO_CS, 0); -+ if (ret) { -+ dev_err(&pdev->dev, "unable to set direction of CS\n"); -+ goto err_free_cs; -+ } -+ -+ master = spi_alloc_master(&pdev->dev, sizeof(*sp)); -+ if (master == NULL) { -+ dev_err(&pdev->dev, "failed to allocate spi master\n"); -+ return -ENOMEM; -+ } -+ -+ sp = spi_master_get_devdata(master); -+ platform_set_drvdata(pdev, sp); -+ -+ pdata = pdev->dev.platform_data; -+ -+ sp->bitbang.master = spi_master_get(master); -+ sp->bitbang.chipselect = ap83_spi_chipselect; -+ sp->bitbang.txrx_word[SPI_MODE_0] = ap83_spi_txrx_mode0; -+ sp->bitbang.txrx_word[SPI_MODE_1] = ap83_spi_txrx_mode1; -+ sp->bitbang.txrx_word[SPI_MODE_2] = ap83_spi_txrx_mode2; -+ sp->bitbang.txrx_word[SPI_MODE_3] = ap83_spi_txrx_mode3; -+ -+ sp->bitbang.master->bus_num = pdev->id; -+ sp->bitbang.master->num_chipselect = 1; -+ -+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (r == NULL) { -+ ret = -ENOENT; -+ goto err_spi_put; -+ } -+ -+ sp->base = ioremap_nocache(r->start, r->end - r->start + 1); -+ if (!sp->base) { -+ ret = -ENXIO; -+ goto err_spi_put; -+ } -+ -+ ret = spi_bitbang_start(&sp->bitbang); -+ if (!ret) -+ goto err_unmap; -+ -+ dev_info(&pdev->dev, "AP83 SPI adapter at %08x\n", r->start); -+ -+ return 0; -+ -+ err_unmap: -+ iounmap(sp->base); -+ err_spi_put: -+ platform_set_drvdata(pdev, NULL); -+ spi_master_put(sp->bitbang.master); -+ -+ err_free_cs: -+ gpio_free(AP83_SPI_GPIO_CS); -+ err_free_miso: -+ gpio_free(AP83_SPI_GPIO_MISO); -+ return ret; -+} -+ -+static int ap83_spi_remove(struct platform_device *pdev) -+{ -+ struct ap83_spi *sp = platform_get_drvdata(pdev); -+ -+ spi_bitbang_stop(&sp->bitbang); -+ iounmap(sp->base); -+ platform_set_drvdata(pdev, NULL); -+ spi_master_put(sp->bitbang.master); -+ -+ return 0; -+} -+ -+static struct platform_driver ap83_spi_drv = { -+ .probe = ap83_spi_probe, -+ .remove = ap83_spi_remove, -+ .driver = { -+ .name = DRV_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init ap83_spi_init(void) -+{ -+ return platform_driver_register(&ap83_spi_drv); -+} -+module_init(ap83_spi_init); -+ -+static void __exit ap83_spi_exit(void) -+{ -+ platform_driver_unregister(&ap83_spi_drv); -+} -+module_exit(ap83_spi_exit); -+ -+MODULE_ALIAS("platform:" DRV_NAME); -+MODULE_DESCRIPTION(DRV_DESC); -+MODULE_VERSION(DRV_VERSION); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_LICENSE("GPL v2"); -diff -Nur linux-2.6.37.orig/drivers/spi/ar71xx_spi.c linux-2.6.37/drivers/spi/ar71xx_spi.c ---- linux-2.6.37.orig/drivers/spi/ar71xx_spi.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/drivers/spi/ar71xx_spi.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,283 @@ -+/* -+ * Atheros AR71xx SPI Controller driver -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#define DRV_DESC "Atheros AR71xx SPI Controller driver" -+#define DRV_VERSION "0.2.4" -+#define DRV_NAME "ar71xx-spi" -+ -+#undef PER_BIT_READ -+ -+struct ar71xx_spi { -+ struct spi_bitbang bitbang; -+ u32 ioc_base; -+ u32 reg_ctrl; -+ -+ void __iomem *base; -+ -+ struct platform_device *pdev; -+ u32 (*get_ioc_base)(u8 chip_select, int cs_high, -+ int is_on); -+}; -+ -+static inline u32 ar71xx_spi_rr(struct ar71xx_spi *sp, unsigned reg) -+{ -+ return __raw_readl(sp->base + reg); -+} -+ -+static inline void ar71xx_spi_wr(struct ar71xx_spi *sp, unsigned reg, u32 val) -+{ -+ __raw_writel(val, sp->base + reg); -+} -+ -+static inline struct ar71xx_spi *spidev_to_sp(struct spi_device *spi) -+{ -+ return spi_master_get_devdata(spi->master); -+} -+ -+static u32 ar71xx_spi_get_ioc_base(u8 chip_select, int cs_high, int is_on) -+{ -+ u32 ret; -+ -+ if (is_on == AR71XX_SPI_CS_INACTIVE) -+ ret = SPI_IOC_CS_ALL; -+ else -+ ret = SPI_IOC_CS_ALL & ~SPI_IOC_CS(chip_select); -+ -+ return ret; -+} -+ -+static void ar71xx_spi_chipselect(struct spi_device *spi, int value) -+{ -+ struct ar71xx_spi *sp = spidev_to_sp(spi); -+ void __iomem *base = sp->base; -+ u32 ioc_base; -+ -+ switch (value) { -+ case BITBANG_CS_INACTIVE: -+ ioc_base = sp->get_ioc_base(spi->chip_select, -+ (spi->mode & SPI_CS_HIGH) != 0, -+ AR71XX_SPI_CS_INACTIVE); -+ __raw_writel(ioc_base, base + SPI_REG_IOC); -+ break; -+ -+ case BITBANG_CS_ACTIVE: -+ ioc_base = sp->get_ioc_base(spi->chip_select, -+ (spi->mode & SPI_CS_HIGH) != 0, -+ AR71XX_SPI_CS_ACTIVE); -+ -+ __raw_writel(ioc_base, base + SPI_REG_IOC); -+ sp->ioc_base = ioc_base; -+ break; -+ } -+} -+ -+static void ar71xx_spi_setup_regs(struct spi_device *spi) -+{ -+ struct ar71xx_spi *sp = spidev_to_sp(spi); -+ -+ /* enable GPIO mode */ -+ ar71xx_spi_wr(sp, SPI_REG_FS, SPI_FS_GPIO); -+ -+ /* save CTRL register */ -+ sp->reg_ctrl = ar71xx_spi_rr(sp, SPI_REG_CTRL); -+ -+ /* TODO: setup speed? */ -+ ar71xx_spi_wr(sp, SPI_REG_CTRL, 0x43); -+} -+ -+static void ar71xx_spi_restore_regs(struct spi_device *spi) -+{ -+ struct ar71xx_spi *sp = spidev_to_sp(spi); -+ -+ /* restore CTRL register */ -+ ar71xx_spi_wr(sp, SPI_REG_CTRL, sp->reg_ctrl); -+ /* disable GPIO mode */ -+ ar71xx_spi_wr(sp, SPI_REG_FS, 0); -+} -+ -+static int ar71xx_spi_setup(struct spi_device *spi) -+{ -+ int status; -+ -+ if (spi->bits_per_word > 32) -+ return -EINVAL; -+ -+ if (!spi->controller_state) -+ ar71xx_spi_setup_regs(spi); -+ -+ status = spi_bitbang_setup(spi); -+ if (status && !spi->controller_state) -+ ar71xx_spi_restore_regs(spi); -+ -+ return status; -+} -+ -+static void ar71xx_spi_cleanup(struct spi_device *spi) -+{ -+ ar71xx_spi_restore_regs(spi); -+ spi_bitbang_cleanup(spi); -+} -+ -+static u32 ar71xx_spi_txrx_mode0(struct spi_device *spi, unsigned nsecs, -+ u32 word, u8 bits) -+{ -+ struct ar71xx_spi *sp = spidev_to_sp(spi); -+ void __iomem *base = sp->base; -+ u32 ioc = sp->ioc_base; -+ u32 ret; -+ -+ /* clock starts at inactive polarity */ -+ for (word <<= (32 - bits); likely(bits); bits--) { -+ u32 out; -+ -+ if (word & (1 << 31)) -+ out = ioc | SPI_IOC_DO; -+ else -+ out = ioc & ~SPI_IOC_DO; -+ -+ /* setup MSB (to slave) on trailing edge */ -+ __raw_writel(out, base + SPI_REG_IOC); -+ -+ __raw_writel(out | SPI_IOC_CLK, base + SPI_REG_IOC); -+ -+ word <<= 1; -+ -+#ifdef PER_BIT_READ -+ /* sample MSB (from slave) on leading edge */ -+ ret = __raw_readl(base + SPI_REG_RDS); -+ __raw_writel(out, base + SPI_REG_IOC); -+#endif -+ -+ } -+ -+#ifndef PER_BIT_READ -+ ret = __raw_readl(base + SPI_REG_RDS); -+#endif -+ return ret; -+} -+ -+static int ar71xx_spi_probe(struct platform_device *pdev) -+{ -+ struct spi_master *master; -+ struct ar71xx_spi *sp; -+ struct ar71xx_spi_platform_data *pdata; -+ struct resource *r; -+ int ret; -+ -+ master = spi_alloc_master(&pdev->dev, sizeof(*sp)); -+ if (master == NULL) { -+ dev_err(&pdev->dev, "failed to allocate spi master\n"); -+ return -ENOMEM; -+ } -+ -+ sp = spi_master_get_devdata(master); -+ platform_set_drvdata(pdev, sp); -+ -+ pdata = pdev->dev.platform_data; -+ -+ master->setup = ar71xx_spi_setup; -+ master->cleanup = ar71xx_spi_cleanup; -+ -+ sp->bitbang.master = spi_master_get(master); -+ sp->bitbang.chipselect = ar71xx_spi_chipselect; -+ sp->bitbang.txrx_word[SPI_MODE_0] = ar71xx_spi_txrx_mode0; -+ sp->bitbang.setup_transfer = spi_bitbang_setup_transfer; -+ -+ sp->get_ioc_base = ar71xx_spi_get_ioc_base; -+ if (pdata) { -+ sp->bitbang.master->bus_num = pdata->bus_num; -+ sp->bitbang.master->num_chipselect = pdata->num_chipselect; -+ if (pdata->get_ioc_base) -+ sp->get_ioc_base = pdata->get_ioc_base; -+ } else { -+ sp->bitbang.master->bus_num = 0; -+ sp->bitbang.master->num_chipselect = 3; -+ } -+ -+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (r == NULL) { -+ ret = -ENOENT; -+ goto err1; -+ } -+ -+ sp->base = ioremap_nocache(r->start, r->end - r->start + 1); -+ if (!sp->base) { -+ ret = -ENXIO; -+ goto err1; -+ } -+ -+ ret = spi_bitbang_start(&sp->bitbang); -+ if (!ret) -+ return 0; -+ -+ iounmap(sp->base); -+ err1: -+ platform_set_drvdata(pdev, NULL); -+ spi_master_put(sp->bitbang.master); -+ -+ return ret; -+} -+ -+static int ar71xx_spi_remove(struct platform_device *pdev) -+{ -+ struct ar71xx_spi *sp = platform_get_drvdata(pdev); -+ -+ spi_bitbang_stop(&sp->bitbang); -+ iounmap(sp->base); -+ platform_set_drvdata(pdev, NULL); -+ spi_master_put(sp->bitbang.master); -+ -+ return 0; -+} -+ -+static struct platform_driver ar71xx_spi_drv = { -+ .probe = ar71xx_spi_probe, -+ .remove = ar71xx_spi_remove, -+ .driver = { -+ .name = DRV_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init ar71xx_spi_init(void) -+{ -+ printk(KERN_INFO DRV_DESC " version " DRV_VERSION "\n"); -+ return platform_driver_register(&ar71xx_spi_drv); -+} -+module_init(ar71xx_spi_init); -+ -+static void __exit ar71xx_spi_exit(void) -+{ -+ platform_driver_unregister(&ar71xx_spi_drv); -+} -+module_exit(ar71xx_spi_exit); -+ -+MODULE_ALIAS("platform:" DRV_NAME); -+MODULE_DESCRIPTION(DRV_DESC); -+MODULE_VERSION(DRV_VERSION); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_AUTHOR("Imre Kaloz "); -+MODULE_LICENSE("GPL v2"); -diff -Nur linux-2.6.37.orig/drivers/spi/pb44_spi.c linux-2.6.37/drivers/spi/pb44_spi.c ---- linux-2.6.37.orig/drivers/spi/pb44_spi.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/drivers/spi/pb44_spi.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,299 @@ -+/* -+ * Atheros PB44 board SPI controller driver -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#define DRV_DESC "Atheros PB44 SPI Controller driver" -+#define DRV_VERSION "0.1.0" -+#define DRV_NAME "pb44-spi" -+ -+#undef PER_BIT_READ -+ -+struct ar71xx_spi { -+ struct spi_bitbang bitbang; -+ u32 ioc_base; -+ u32 reg_ctrl; -+ -+ void __iomem *base; -+ -+ struct platform_device *pdev; -+}; -+ -+static inline u32 pb44_spi_rr(struct ar71xx_spi *sp, unsigned reg) -+{ -+ return __raw_readl(sp->base + reg); -+} -+ -+static inline void pb44_spi_wr(struct ar71xx_spi *sp, unsigned reg, u32 val) -+{ -+ __raw_writel(val, sp->base + reg); -+} -+ -+static inline struct ar71xx_spi *spidev_to_sp(struct spi_device *spi) -+{ -+ return spi_master_get_devdata(spi->master); -+} -+ -+static void pb44_spi_chipselect(struct spi_device *spi, int is_active) -+{ -+ struct ar71xx_spi *sp = spidev_to_sp(spi); -+ int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active; -+ -+ if (is_active) { -+ /* set initial clock polarity */ -+ if (spi->mode & SPI_CPOL) -+ sp->ioc_base |= SPI_IOC_CLK; -+ else -+ sp->ioc_base &= ~SPI_IOC_CLK; -+ -+ pb44_spi_wr(sp, SPI_REG_IOC, sp->ioc_base); -+ } -+ -+ if (spi->chip_select) { -+ unsigned long gpio = (unsigned long) spi->controller_data; -+ -+ /* SPI is normally active-low */ -+ gpio_set_value(gpio, cs_high); -+ } else { -+ if (cs_high) -+ sp->ioc_base |= SPI_IOC_CS0; -+ else -+ sp->ioc_base &= ~SPI_IOC_CS0; -+ -+ pb44_spi_wr(sp, SPI_REG_IOC, sp->ioc_base); -+ } -+ -+} -+ -+static int pb44_spi_setup_cs(struct spi_device *spi) -+{ -+ struct ar71xx_spi *sp = spidev_to_sp(spi); -+ -+ /* enable GPIO mode */ -+ pb44_spi_wr(sp, SPI_REG_FS, SPI_FS_GPIO); -+ -+ /* save CTRL register */ -+ sp->reg_ctrl = pb44_spi_rr(sp, SPI_REG_CTRL); -+ sp->ioc_base = pb44_spi_rr(sp, SPI_REG_IOC); -+ -+ /* TODO: setup speed? */ -+ pb44_spi_wr(sp, SPI_REG_CTRL, 0x43); -+ -+ if (spi->chip_select) { -+ unsigned long gpio = (unsigned long) spi->controller_data; -+ int status = 0; -+ -+ status = gpio_request(gpio, dev_name(&spi->dev)); -+ if (status) -+ return status; -+ -+ status = gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH); -+ if (status) { -+ gpio_free(gpio); -+ return status; -+ } -+ } else { -+ if (spi->mode & SPI_CS_HIGH) -+ sp->ioc_base |= SPI_IOC_CS0; -+ else -+ sp->ioc_base &= ~SPI_IOC_CS0; -+ pb44_spi_wr(sp, SPI_REG_IOC, sp->ioc_base); -+ } -+ -+ return 0; -+} -+ -+static void pb44_spi_cleanup_cs(struct spi_device *spi) -+{ -+ struct ar71xx_spi *sp = spidev_to_sp(spi); -+ -+ if (spi->chip_select) { -+ unsigned long gpio = (unsigned long) spi->controller_data; -+ gpio_free(gpio); -+ } -+ -+ /* restore CTRL register */ -+ pb44_spi_wr(sp, SPI_REG_CTRL, sp->reg_ctrl); -+ /* disable GPIO mode */ -+ pb44_spi_wr(sp, SPI_REG_FS, 0); -+} -+ -+static int pb44_spi_setup(struct spi_device *spi) -+{ -+ int status = 0; -+ -+ if (spi->bits_per_word > 32) -+ return -EINVAL; -+ -+ if (!spi->controller_state) { -+ status = pb44_spi_setup_cs(spi); -+ if (status) -+ return status; -+ } -+ -+ status = spi_bitbang_setup(spi); -+ if (status && !spi->controller_state) -+ pb44_spi_cleanup_cs(spi); -+ -+ return status; -+} -+ -+static void pb44_spi_cleanup(struct spi_device *spi) -+{ -+ pb44_spi_cleanup_cs(spi); -+ spi_bitbang_cleanup(spi); -+} -+ -+static u32 pb44_spi_txrx_mode0(struct spi_device *spi, unsigned nsecs, -+ u32 word, u8 bits) -+{ -+ struct ar71xx_spi *sp = spidev_to_sp(spi); -+ u32 ioc = sp->ioc_base; -+ u32 ret; -+ -+ /* clock starts at inactive polarity */ -+ for (word <<= (32 - bits); likely(bits); bits--) { -+ u32 out; -+ -+ if (word & (1 << 31)) -+ out = ioc | SPI_IOC_DO; -+ else -+ out = ioc & ~SPI_IOC_DO; -+ -+ /* setup MSB (to slave) on trailing edge */ -+ pb44_spi_wr(sp, SPI_REG_IOC, out); -+ pb44_spi_wr(sp, SPI_REG_IOC, out | SPI_IOC_CLK); -+ -+ word <<= 1; -+ -+#ifdef PER_BIT_READ -+ /* sample MSB (from slave) on leading edge */ -+ ret = pb44_spi_rr(sp, SPI_REG_RDS); -+ pb44_spi_wr(sp, SPI_REG_IOC, out); -+#endif -+ } -+ -+#ifndef PER_BIT_READ -+ ret = pb44_spi_rr(sp, SPI_REG_RDS); -+#endif -+ return ret; -+} -+ -+static int pb44_spi_probe(struct platform_device *pdev) -+{ -+ struct spi_master *master; -+ struct ar71xx_spi *sp; -+ struct ar71xx_spi_platform_data *pdata; -+ struct resource *r; -+ int ret; -+ -+ master = spi_alloc_master(&pdev->dev, sizeof(*sp)); -+ if (master == NULL) { -+ dev_err(&pdev->dev, "failed to allocate spi master\n"); -+ return -ENOMEM; -+ } -+ -+ sp = spi_master_get_devdata(master); -+ platform_set_drvdata(pdev, sp); -+ -+ pdata = pdev->dev.platform_data; -+ -+ master->setup = pb44_spi_setup; -+ master->cleanup = pb44_spi_cleanup; -+ if (pdata) { -+ master->bus_num = pdata->bus_num; -+ master->num_chipselect = pdata->num_chipselect; -+ } else { -+ master->bus_num = 0; -+ master->num_chipselect = 1; -+ } -+ -+ sp->bitbang.master = spi_master_get(master); -+ sp->bitbang.chipselect = pb44_spi_chipselect; -+ sp->bitbang.txrx_word[SPI_MODE_0] = pb44_spi_txrx_mode0; -+ sp->bitbang.setup_transfer = spi_bitbang_setup_transfer; -+ sp->bitbang.flags = SPI_CS_HIGH; -+ -+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (r == NULL) { -+ ret = -ENOENT; -+ goto err1; -+ } -+ -+ sp->base = ioremap_nocache(r->start, r->end - r->start + 1); -+ if (!sp->base) { -+ ret = -ENXIO; -+ goto err1; -+ } -+ -+ ret = spi_bitbang_start(&sp->bitbang); -+ if (!ret) -+ return 0; -+ -+ iounmap(sp->base); -+ err1: -+ platform_set_drvdata(pdev, NULL); -+ spi_master_put(sp->bitbang.master); -+ -+ return ret; -+} -+ -+static int pb44_spi_remove(struct platform_device *pdev) -+{ -+ struct ar71xx_spi *sp = platform_get_drvdata(pdev); -+ -+ spi_bitbang_stop(&sp->bitbang); -+ iounmap(sp->base); -+ platform_set_drvdata(pdev, NULL); -+ spi_master_put(sp->bitbang.master); -+ -+ return 0; -+} -+ -+static struct platform_driver pb44_spi_drv = { -+ .probe = pb44_spi_probe, -+ .remove = pb44_spi_remove, -+ .driver = { -+ .name = DRV_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init pb44_spi_init(void) -+{ -+ return platform_driver_register(&pb44_spi_drv); -+} -+module_init(pb44_spi_init); -+ -+static void __exit pb44_spi_exit(void) -+{ -+ platform_driver_unregister(&pb44_spi_drv); -+} -+module_exit(pb44_spi_exit); -+ -+MODULE_ALIAS("platform:" DRV_NAME); -+MODULE_DESCRIPTION(DRV_DESC); -+MODULE_VERSION(DRV_VERSION); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_LICENSE("GPL v2"); -diff -Nur linux-2.6.37.orig/drivers/spi/spi_vsc7385.c linux-2.6.37/drivers/spi/spi_vsc7385.c ---- linux-2.6.37.orig/drivers/spi/spi_vsc7385.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/drivers/spi/spi_vsc7385.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,620 @@ -+/* -+ * SPI driver for the Vitesse VSC7385 ethernet switch -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define DRV_NAME "spi-vsc7385" -+#define DRV_DESC "Vitesse VSC7385 Gbit ethernet switch driver" -+#define DRV_VERSION "0.1.0" -+ -+#define VSC73XX_BLOCK_MAC 0x1 -+#define VSC73XX_BLOCK_2 0x2 -+#define VSC73XX_BLOCK_MII 0x3 -+#define VSC73XX_BLOCK_4 0x4 -+#define VSC73XX_BLOCK_5 0x5 -+#define VSC73XX_BLOCK_SYSTEM 0x7 -+ -+#define VSC73XX_SUBBLOCK_PORT_0 0 -+#define VSC73XX_SUBBLOCK_PORT_1 1 -+#define VSC73XX_SUBBLOCK_PORT_2 2 -+#define VSC73XX_SUBBLOCK_PORT_3 3 -+#define VSC73XX_SUBBLOCK_PORT_4 4 -+#define VSC73XX_SUBBLOCK_PORT_MAC 6 -+ -+/* MAC Block registers */ -+#define VSC73XX_MAC_CFG 0x0 -+#define VSC73XX_ADVPORTM 0x19 -+#define VSC73XX_RXOCT 0x50 -+#define VSC73XX_TXOCT 0x51 -+#define VSC73XX_C_RX0 0x52 -+#define VSC73XX_C_RX1 0x53 -+#define VSC73XX_C_RX2 0x54 -+#define VSC73XX_C_TX0 0x55 -+#define VSC73XX_C_TX1 0x56 -+#define VSC73XX_C_TX2 0x57 -+#define VSC73XX_C_CFG 0x58 -+ -+/* MAC_CFG register bits */ -+#define VSC73XX_MAC_CFG_WEXC_DIS (1 << 31) -+#define VSC73XX_MAC_CFG_PORT_RST (1 << 29) -+#define VSC73XX_MAC_CFG_TX_EN (1 << 28) -+#define VSC73XX_MAC_CFG_SEED_LOAD (1 << 27) -+#define VSC73XX_MAC_CFG_FDX (1 << 18) -+#define VSC73XX_MAC_CFG_GIGE (1 << 17) -+#define VSC73XX_MAC_CFG_RX_EN (1 << 16) -+#define VSC73XX_MAC_CFG_VLAN_DBLAWR (1 << 15) -+#define VSC73XX_MAC_CFG_VLAN_AWR (1 << 14) -+#define VSC73XX_MAC_CFG_100_BASE_T (1 << 13) -+#define VSC73XX_MAC_CFG_TX_IPG(x) (((x) & 0x1f) << 6) -+#define VSC73XX_MAC_CFG_MAC_RX_RST (1 << 5) -+#define VSC73XX_MAC_CFG_MAC_TX_RST (1 << 4) -+#define VSC73XX_MAC_CFG_BIT2 (1 << 2) -+#define VSC73XX_MAC_CFG_CLK_SEL(x) ((x) & 0x3) -+ -+/* ADVPORTM register bits */ -+#define VSC73XX_ADVPORTM_IFG_PPM (1 << 7) -+#define VSC73XX_ADVPORTM_EXC_COL_CONT (1 << 6) -+#define VSC73XX_ADVPORTM_EXT_PORT (1 << 5) -+#define VSC73XX_ADVPORTM_INV_GTX (1 << 4) -+#define VSC73XX_ADVPORTM_ENA_GTX (1 << 3) -+#define VSC73XX_ADVPORTM_DDR_MODE (1 << 2) -+#define VSC73XX_ADVPORTM_IO_LOOPBACK (1 << 1) -+#define VSC73XX_ADVPORTM_HOST_LOOPBACK (1 << 0) -+ -+/* MII Block registers */ -+#define VSC73XX_MII_STAT 0x0 -+#define VSC73XX_MII_CMD 0x1 -+#define VSC73XX_MII_DATA 0x2 -+ -+/* System Block registers */ -+#define VSC73XX_ICPU_SIPAD 0x01 -+#define VSC73XX_ICPU_CLOCK_DELAY 0x05 -+#define VSC73XX_ICPU_CTRL 0x10 -+#define VSC73XX_ICPU_ADDR 0x11 -+#define VSC73XX_ICPU_SRAM 0x12 -+#define VSC73XX_ICPU_MBOX_VAL 0x15 -+#define VSC73XX_ICPU_MBOX_SET 0x16 -+#define VSC73XX_ICPU_MBOX_CLR 0x17 -+#define VSC73XX_ICPU_CHIPID 0x18 -+#define VSC73XX_ICPU_GPIO 0x34 -+ -+#define VSC73XX_ICPU_CTRL_CLK_DIV (1 << 8) -+#define VSC73XX_ICPU_CTRL_SRST_HOLD (1 << 7) -+#define VSC73XX_ICPU_CTRL_BOOT_EN (1 << 3) -+#define VSC73XX_ICPU_CTRL_EXT_ACC_EN (1 << 2) -+#define VSC73XX_ICPU_CTRL_CLK_EN (1 << 1) -+#define VSC73XX_ICPU_CTRL_SRST (1 << 0) -+ -+#define VSC73XX_ICPU_CHIPID_ID_SHIFT 12 -+#define VSC73XX_ICPU_CHIPID_ID_MASK 0xffff -+#define VSC73XX_ICPU_CHIPID_REV_SHIFT 28 -+#define VSC73XX_ICPU_CHIPID_REV_MASK 0xf -+#define VSC73XX_ICPU_CHIPID_ID_7385 0x7385 -+#define VSC73XX_ICPU_CHIPID_ID_7395 0x7395 -+ -+#define VSC73XX_CMD_MODE_READ 0 -+#define VSC73XX_CMD_MODE_WRITE 1 -+#define VSC73XX_CMD_MODE_SHIFT 4 -+#define VSC73XX_CMD_BLOCK_SHIFT 5 -+#define VSC73XX_CMD_BLOCK_MASK 0x7 -+#define VSC73XX_CMD_SUBBLOCK_MASK 0xf -+ -+#define VSC7385_CLOCK_DELAY ((3 << 4) | 3) -+#define VSC7385_CLOCK_DELAY_MASK ((3 << 4) | 3) -+ -+#define VSC73XX_ICPU_CTRL_STOP (VSC73XX_ICPU_CTRL_SRST_HOLD | \ -+ VSC73XX_ICPU_CTRL_BOOT_EN | \ -+ VSC73XX_ICPU_CTRL_EXT_ACC_EN) -+ -+#define VSC73XX_ICPU_CTRL_START (VSC73XX_ICPU_CTRL_CLK_DIV | \ -+ VSC73XX_ICPU_CTRL_BOOT_EN | \ -+ VSC73XX_ICPU_CTRL_CLK_EN | \ -+ VSC73XX_ICPU_CTRL_SRST) -+ -+#define VSC7385_ADVPORTM_MASK (VSC73XX_ADVPORTM_IFG_PPM | \ -+ VSC73XX_ADVPORTM_EXC_COL_CONT | \ -+ VSC73XX_ADVPORTM_EXT_PORT | \ -+ VSC73XX_ADVPORTM_INV_GTX | \ -+ VSC73XX_ADVPORTM_ENA_GTX | \ -+ VSC73XX_ADVPORTM_DDR_MODE | \ -+ VSC73XX_ADVPORTM_IO_LOOPBACK | \ -+ VSC73XX_ADVPORTM_HOST_LOOPBACK) -+ -+#define VSC7385_ADVPORTM_INIT (VSC73XX_ADVPORTM_EXT_PORT | \ -+ VSC73XX_ADVPORTM_ENA_GTX | \ -+ VSC73XX_ADVPORTM_DDR_MODE) -+ -+#define VSC7385_MAC_CFG_RESET (VSC73XX_MAC_CFG_PORT_RST | \ -+ VSC73XX_MAC_CFG_MAC_RX_RST | \ -+ VSC73XX_MAC_CFG_MAC_TX_RST) -+ -+#define VSC73XX_MAC_CFG_INIT (VSC73XX_MAC_CFG_TX_EN | \ -+ VSC73XX_MAC_CFG_FDX | \ -+ VSC73XX_MAC_CFG_GIGE | \ -+ VSC73XX_MAC_CFG_RX_EN) -+ -+#define VSC73XX_RESET_DELAY 100 -+ -+struct vsc7385 { -+ struct spi_device *spi; -+ struct mutex lock; -+ struct vsc7385_platform_data *pdata; -+}; -+ -+static int vsc7385_is_addr_valid(u8 block, u8 subblock) -+{ -+ switch (block) { -+ case VSC73XX_BLOCK_MAC: -+ switch (subblock) { -+ case 0 ... 4: -+ case 6: -+ return 1; -+ } -+ break; -+ -+ case VSC73XX_BLOCK_2: -+ case VSC73XX_BLOCK_SYSTEM: -+ switch (subblock) { -+ case 0: -+ return 1; -+ } -+ break; -+ -+ case VSC73XX_BLOCK_MII: -+ case VSC73XX_BLOCK_4: -+ case VSC73XX_BLOCK_5: -+ switch (subblock) { -+ case 0 ... 1: -+ return 1; -+ } -+ break; -+ } -+ -+ return 0; -+} -+ -+static inline u8 vsc7385_make_addr(u8 mode, u8 block, u8 subblock) -+{ -+ u8 ret; -+ -+ ret = (block & VSC73XX_CMD_BLOCK_MASK) << VSC73XX_CMD_BLOCK_SHIFT; -+ ret |= (mode & 1) << VSC73XX_CMD_MODE_SHIFT; -+ ret |= subblock & VSC73XX_CMD_SUBBLOCK_MASK; -+ -+ return ret; -+} -+ -+static int vsc7385_read(struct vsc7385 *vsc, u8 block, u8 subblock, u8 reg, -+ u32 *value) -+{ -+ u8 cmd[4]; -+ u8 buf[4]; -+ struct spi_transfer t[2]; -+ struct spi_message m; -+ int err; -+ -+ if (!vsc7385_is_addr_valid(block, subblock)) -+ return -EINVAL; -+ -+ spi_message_init(&m); -+ -+ memset(&t, 0, sizeof(t)); -+ -+ t[0].tx_buf = cmd; -+ t[0].len = sizeof(cmd); -+ spi_message_add_tail(&t[0], &m); -+ -+ t[1].rx_buf = buf; -+ t[1].len = sizeof(buf); -+ spi_message_add_tail(&t[1], &m); -+ -+ cmd[0] = vsc7385_make_addr(VSC73XX_CMD_MODE_READ, block, subblock); -+ cmd[1] = reg; -+ cmd[2] = 0; -+ cmd[3] = 0; -+ -+ mutex_lock(&vsc->lock); -+ err = spi_sync(vsc->spi, &m); -+ mutex_unlock(&vsc->lock); -+ -+ if (err) -+ return err; -+ -+ *value = (((u32) buf[0]) << 24) | (((u32) buf[1]) << 16) | -+ (((u32) buf[2]) << 8) | ((u32) buf[3]); -+ -+ return 0; -+} -+ -+ -+static int vsc7385_write(struct vsc7385 *vsc, u8 block, u8 subblock, u8 reg, -+ u32 value) -+{ -+ u8 cmd[2]; -+ u8 buf[4]; -+ struct spi_transfer t[2]; -+ struct spi_message m; -+ int err; -+ -+ if (!vsc7385_is_addr_valid(block, subblock)) -+ return -EINVAL; -+ -+ spi_message_init(&m); -+ -+ memset(&t, 0, sizeof(t)); -+ -+ t[0].tx_buf = cmd; -+ t[0].len = sizeof(cmd); -+ spi_message_add_tail(&t[0], &m); -+ -+ t[1].tx_buf = buf; -+ t[1].len = sizeof(buf); -+ spi_message_add_tail(&t[1], &m); -+ -+ cmd[0] = vsc7385_make_addr(VSC73XX_CMD_MODE_WRITE, block, subblock); -+ cmd[1] = reg; -+ -+ buf[0] = (value >> 24) & 0xff; -+ buf[1] = (value >> 16) & 0xff; -+ buf[2] = (value >> 8) & 0xff; -+ buf[3] = value & 0xff; -+ -+ mutex_lock(&vsc->lock); -+ err = spi_sync(vsc->spi, &m); -+ mutex_unlock(&vsc->lock); -+ -+ return err; -+} -+ -+static inline int vsc7385_write_verify(struct vsc7385 *vsc, u8 block, -+ u8 subblock, u8 reg, u32 value, -+ u32 read_mask, u32 read_val) -+{ -+ struct spi_device *spi = vsc->spi; -+ u32 t; -+ int err; -+ -+ err = vsc7385_write(vsc, block, subblock, reg, value); -+ if (err) -+ return err; -+ -+ err = vsc7385_read(vsc, block, subblock, reg, &t); -+ if (err) -+ return err; -+ -+ if ((t & read_mask) != read_val) { -+ dev_err(&spi->dev, "register write error\n"); -+ return -EIO; -+ } -+ -+ return 0; -+} -+ -+static inline int vsc7385_set_clock_delay(struct vsc7385 *vsc, u32 val) -+{ -+ return vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, -+ VSC73XX_ICPU_CLOCK_DELAY, val); -+} -+ -+static inline int vsc7385_get_clock_delay(struct vsc7385 *vsc, u32 *val) -+{ -+ return vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, -+ VSC73XX_ICPU_CLOCK_DELAY, val); -+} -+ -+static inline int vsc7385_icpu_stop(struct vsc7385 *vsc) -+{ -+ return vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_ICPU_CTRL, -+ VSC73XX_ICPU_CTRL_STOP); -+} -+ -+static inline int vsc7385_icpu_start(struct vsc7385 *vsc) -+{ -+ return vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_ICPU_CTRL, -+ VSC73XX_ICPU_CTRL_START); -+} -+ -+static inline int vsc7385_icpu_reset(struct vsc7385 *vsc) -+{ -+ int rc; -+ -+ rc = vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_ICPU_ADDR, -+ 0x0000); -+ if (rc) -+ dev_err(&vsc->spi->dev, -+ "could not reset microcode, err=%d\n", rc); -+ -+ return rc; -+} -+ -+static int vsc7385_upload_ucode(struct vsc7385 *vsc) -+{ -+ struct spi_device *spi = vsc->spi; -+ const struct firmware *firmware; -+ char *ucode_name; -+ unsigned char *dp; -+ unsigned int curVal; -+ int i; -+ int diffs; -+ int rc; -+ -+ ucode_name = (vsc->pdata->ucode_name) ? vsc->pdata->ucode_name -+ : "vsc7385_ucode.bin"; -+ rc = request_firmware(&firmware, ucode_name, &spi->dev); -+ if (rc) { -+ dev_err(&spi->dev, "request_firmware failed, err=%d\n", -+ rc); -+ return rc; -+ } -+ -+ rc = vsc7385_icpu_stop(vsc); -+ if (rc) -+ goto out; -+ -+ rc = vsc7385_icpu_reset(vsc); -+ if (rc) -+ goto out; -+ -+ dev_info(&spi->dev, "uploading microcode...\n"); -+ -+ dp = (unsigned char *) firmware->data; -+ for (i = 0; i < firmware->size; i++) { -+ rc = vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, -+ VSC73XX_ICPU_SRAM, *dp++); -+ if (rc) { -+ dev_err(&spi->dev, "could not load microcode, err=%d\n", -+ rc); -+ goto out; -+ } -+ } -+ -+ rc = vsc7385_icpu_reset(vsc); -+ if (rc) -+ goto out; -+ -+ dev_info(&spi->dev, "verifying microcode...\n"); -+ -+ dp = (unsigned char *) firmware->data; -+ diffs = 0; -+ for (i = 0; i < firmware->size; i++) { -+ rc = vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, -+ VSC73XX_ICPU_SRAM, &curVal); -+ if (rc) { -+ dev_err(&spi->dev, "could not read microcode %d\n",rc); -+ goto out; -+ } -+ -+ if (curVal > 0xff) { -+ dev_err(&spi->dev, "bad val read: %04x : %02x %02x\n", -+ i, *dp, curVal); -+ rc = -EIO; -+ goto out; -+ } -+ -+ if ((curVal & 0xff) != *dp) { -+ diffs++; -+ dev_err(&spi->dev, "verify error: %04x : %02x %02x\n", -+ i, *dp, curVal); -+ -+ if (diffs > 4) -+ break; -+ } -+ dp++; -+ } -+ -+ if (diffs) { -+ dev_err(&spi->dev, "microcode verification failed\n"); -+ rc = -EIO; -+ goto out; -+ } -+ -+ dev_info(&spi->dev, "microcode uploaded\n"); -+ -+ rc = vsc7385_icpu_start(vsc); -+ -+ out: -+ release_firmware(firmware); -+ return rc; -+} -+ -+static int vsc7385_setup(struct vsc7385 *vsc) -+{ -+ struct vsc7385_platform_data *pdata = vsc->pdata; -+ u32 t; -+ int err; -+ -+ err = vsc7385_write_verify(vsc, VSC73XX_BLOCK_SYSTEM, 0, -+ VSC73XX_ICPU_CLOCK_DELAY, -+ VSC7385_CLOCK_DELAY, -+ VSC7385_CLOCK_DELAY_MASK, -+ VSC7385_CLOCK_DELAY); -+ if (err) -+ goto err; -+ -+ err = vsc7385_write_verify(vsc, VSC73XX_BLOCK_MAC, -+ VSC73XX_SUBBLOCK_PORT_MAC, VSC73XX_ADVPORTM, -+ VSC7385_ADVPORTM_INIT, -+ VSC7385_ADVPORTM_MASK, -+ VSC7385_ADVPORTM_INIT); -+ if (err) -+ goto err; -+ -+ err = vsc7385_write(vsc, VSC73XX_BLOCK_MAC, VSC73XX_SUBBLOCK_PORT_MAC, -+ VSC73XX_MAC_CFG, VSC7385_MAC_CFG_RESET); -+ if (err) -+ goto err; -+ -+ t = VSC73XX_MAC_CFG_INIT; -+ t |= VSC73XX_MAC_CFG_TX_IPG(pdata->mac_cfg.tx_ipg); -+ t |= VSC73XX_MAC_CFG_CLK_SEL(pdata->mac_cfg.clk_sel); -+ if (pdata->mac_cfg.bit2) -+ t |= VSC73XX_MAC_CFG_BIT2; -+ -+ err = vsc7385_write(vsc, VSC73XX_BLOCK_MAC, VSC73XX_SUBBLOCK_PORT_MAC, -+ VSC73XX_MAC_CFG, t); -+ if (err) -+ goto err; -+ -+ return 0; -+ -+ err: -+ return err; -+} -+ -+static int vsc7385_detect(struct vsc7385 *vsc) -+{ -+ struct spi_device *spi = vsc->spi; -+ u32 t; -+ u32 id; -+ u32 rev; -+ int err; -+ -+ err = vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, -+ VSC73XX_ICPU_MBOX_VAL, &t); -+ if (err) { -+ dev_err(&spi->dev, "unable to read mailbox, err=%d\n", err); -+ return err; -+ } -+ -+ if (t == 0xffffffff) { -+ dev_dbg(&spi->dev, "assert chip reset\n"); -+ if (vsc->pdata->reset) -+ vsc->pdata->reset(); -+ -+ } -+ -+ err = vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, -+ VSC73XX_ICPU_CHIPID, &t); -+ if (err) { -+ dev_err(&spi->dev, "unable to read chip id, err=%d\n", err); -+ return err; -+ } -+ -+ id = (t >> VSC73XX_ICPU_CHIPID_ID_SHIFT) & VSC73XX_ICPU_CHIPID_ID_MASK; -+ switch (id) { -+ case VSC73XX_ICPU_CHIPID_ID_7385: -+ case VSC73XX_ICPU_CHIPID_ID_7395: -+ break; -+ default: -+ dev_err(&spi->dev, "unsupported chip, id=%04x\n", id); -+ return -ENODEV; -+ } -+ -+ rev = (t >> VSC73XX_ICPU_CHIPID_REV_SHIFT) & -+ VSC73XX_ICPU_CHIPID_REV_MASK; -+ dev_info(&spi->dev, "VSC%04X (rev. %d) switch found \n", id, rev); -+ -+ return 0; -+} -+ -+static int __devinit vsc7385_probe(struct spi_device *spi) -+{ -+ struct vsc7385 *vsc; -+ struct vsc7385_platform_data *pdata; -+ int err; -+ -+ printk(KERN_INFO DRV_DESC " version " DRV_VERSION"\n"); -+ -+ pdata = spi->dev.platform_data; -+ if (!pdata) { -+ dev_err(&spi->dev, "no platform data specified\n"); -+ return-ENODEV; -+ } -+ -+ vsc = kzalloc(sizeof(*vsc), GFP_KERNEL); -+ if (!vsc) { -+ dev_err(&spi->dev, "no memory for private data\n"); -+ return-ENOMEM; -+ } -+ -+ mutex_init(&vsc->lock); -+ vsc->pdata = pdata; -+ vsc->spi = spi_dev_get(spi); -+ dev_set_drvdata(&spi->dev, vsc); -+ -+ spi->mode = SPI_MODE_0; -+ spi->bits_per_word = 8; -+ err = spi_setup(spi); -+ if (err) { -+ dev_err(&spi->dev, "spi_setup failed, err=%d \n", err); -+ goto err_drvdata; -+ } -+ -+ err = vsc7385_detect(vsc); -+ if (err) { -+ dev_err(&spi->dev, "no chip found, err=%d \n", err); -+ goto err_drvdata; -+ } -+ -+ err = vsc7385_upload_ucode(vsc); -+ if (err) -+ goto err_drvdata; -+ -+ err = vsc7385_setup(vsc); -+ if (err) -+ goto err_drvdata; -+ -+ return 0; -+ -+ err_drvdata: -+ dev_set_drvdata(&spi->dev, NULL); -+ kfree(vsc); -+ return err; -+} -+ -+static int __devexit vsc7385_remove(struct spi_device *spi) -+{ -+ struct vsc7385_data *vsc; -+ -+ vsc = dev_get_drvdata(&spi->dev); -+ dev_set_drvdata(&spi->dev, NULL); -+ kfree(vsc); -+ -+ return 0; -+} -+ -+static struct spi_driver vsc7385_driver = { -+ .driver = { -+ .name = DRV_NAME, -+ .bus = &spi_bus_type, -+ .owner = THIS_MODULE, -+ }, -+ .probe = vsc7385_probe, -+ .remove = __devexit_p(vsc7385_remove), -+}; -+ -+static int __init vsc7385_init(void) -+{ -+ return spi_register_driver(&vsc7385_driver); -+} -+module_init(vsc7385_init); -+ -+static void __exit vsc7385_exit(void) -+{ -+ spi_unregister_driver(&vsc7385_driver); -+} -+module_exit(vsc7385_exit); -+ -+MODULE_DESCRIPTION(DRV_DESC); -+MODULE_VERSION(DRV_VERSION); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_LICENSE("GPL v2"); -+ -diff -Nur linux-2.6.37.orig/drivers/usb/host/Kconfig linux-2.6.37/drivers/usb/host/Kconfig ---- linux-2.6.37.orig/drivers/usb/host/Kconfig 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/usb/host/Kconfig 2011-01-11 20:25:48.000000000 +0100 -@@ -118,6 +118,13 @@ - config USB_FSL_MPH_DR_OF - tristate - -+config USB_EHCI_AR71XX -+ bool "USB EHCI support for AR71xx" -+ depends on USB_EHCI_HCD && ATHEROS_AR71XX -+ default y -+ help -+ Support for Atheros AR71xx built-in EHCI controller -+ - config USB_EHCI_FSL - bool "Support for Freescale on-chip EHCI USB controller" - depends on USB_EHCI_HCD && FSL_SOC -@@ -232,6 +239,13 @@ - Enables support for the on-chip OHCI controller on - OMAP3 and later chips. - -+config USB_OHCI_AR71XX -+ bool "USB OHCI support for Atheros AR71xx" -+ depends on USB_OHCI_HCD && ATHEROS_AR71XX -+ default y -+ help -+ Support for Atheros AR71xx built-in OHCI controller -+ - config USB_OHCI_HCD_PPC_SOC - bool "OHCI support for on-chip PPC USB controller" - depends on USB_OHCI_HCD && (STB03xxx || PPC_MPC52xx) -diff -Nur linux-2.6.37.orig/drivers/usb/host/ehci-ar71xx.c linux-2.6.37/drivers/usb/host/ehci-ar71xx.c ---- linux-2.6.37.orig/drivers/usb/host/ehci-ar71xx.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/drivers/usb/host/ehci-ar71xx.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,242 @@ -+/* -+ * Bus Glue for Atheros AR71xx built-in EHCI controller. -+ * -+ * Copyright (C) 2008-2010 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * Copyright (C) 2007 Atheros Communications, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+extern int usb_disabled(void); -+ -+static int ehci_ar71xx_init(struct usb_hcd *hcd) -+{ -+ struct ehci_hcd *ehci = hcd_to_ehci(hcd); -+ int ret; -+ -+ ehci->caps = hcd->regs; -+ ehci->regs = hcd->regs + -+ HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); -+ ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); -+ -+ ehci->sbrn = 0x20; -+ ehci->has_synopsys_hc_bug = 1; -+ -+ ehci_reset(ehci); -+ -+ ret = ehci_init(hcd); -+ if (ret) -+ return ret; -+ -+ ehci_port_power(ehci, 0); -+ -+ return 0; -+} -+ -+static int ehci_ar91xx_init(struct usb_hcd *hcd) -+{ -+ struct ehci_hcd *ehci = hcd_to_ehci(hcd); -+ int ret; -+ -+ ehci->caps = hcd->regs + 0x100; -+ ehci->regs = hcd->regs + 0x100 + -+ HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); -+ ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); -+ -+ hcd->has_tt = 1; -+ ehci->sbrn = 0x20; -+ -+ ehci_reset(ehci); -+ -+ ret = ehci_init(hcd); -+ if (ret) -+ return ret; -+ -+ ehci_port_power(ehci, 0); -+ -+ return 0; -+} -+ -+static int ehci_ar71xx_probe(const struct hc_driver *driver, -+ struct usb_hcd **hcd_out, -+ struct platform_device *pdev) -+{ -+ struct usb_hcd *hcd; -+ struct resource *res; -+ int irq; -+ int ret; -+ -+ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); -+ if (!res) { -+ dev_dbg(&pdev->dev, "no IRQ specified for %s\n", -+ dev_name(&pdev->dev)); -+ return -ENODEV; -+ } -+ irq = res->start; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (!res) { -+ dev_dbg(&pdev->dev, "no base address specified for %s\n", -+ dev_name(&pdev->dev)); -+ return -ENODEV; -+ } -+ -+ hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev)); -+ if (!hcd) -+ return -ENOMEM; -+ -+ hcd->rsrc_start = res->start; -+ hcd->rsrc_len = res->end - res->start + 1; -+ -+ if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { -+ dev_dbg(&pdev->dev, "controller already in use\n"); -+ ret = -EBUSY; -+ goto err_put_hcd; -+ } -+ -+ hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); -+ if (!hcd->regs) { -+ dev_dbg(&pdev->dev, "error mapping memory\n"); -+ ret = -EFAULT; -+ goto err_release_region; -+ } -+ -+ ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED); -+ if (ret) -+ goto err_iounmap; -+ -+ return 0; -+ -+ err_iounmap: -+ iounmap(hcd->regs); -+ -+ err_release_region: -+ release_mem_region(hcd->rsrc_start, hcd->rsrc_len); -+ err_put_hcd: -+ usb_put_hcd(hcd); -+ return ret; -+} -+ -+static void ehci_ar71xx_remove(struct usb_hcd *hcd, -+ struct platform_device *pdev) -+{ -+ usb_remove_hcd(hcd); -+ iounmap(hcd->regs); -+ release_mem_region(hcd->rsrc_start, hcd->rsrc_len); -+ usb_put_hcd(hcd); -+} -+ -+static const struct hc_driver ehci_ar71xx_hc_driver = { -+ .description = hcd_name, -+ .product_desc = "Atheros AR71xx built-in EHCI controller", -+ .hcd_priv_size = sizeof(struct ehci_hcd), -+ -+ .irq = ehci_irq, -+ .flags = HCD_MEMORY | HCD_USB2, -+ -+ .reset = ehci_ar71xx_init, -+ .start = ehci_run, -+ .stop = ehci_stop, -+ .shutdown = ehci_shutdown, -+ -+ .urb_enqueue = ehci_urb_enqueue, -+ .urb_dequeue = ehci_urb_dequeue, -+ .endpoint_disable = ehci_endpoint_disable, -+ .endpoint_reset = ehci_endpoint_reset, -+ -+ .get_frame_number = ehci_get_frame, -+ -+ .hub_status_data = ehci_hub_status_data, -+ .hub_control = ehci_hub_control, -+#ifdef CONFIG_PM -+ .hub_suspend = ehci_hub_suspend, -+ .hub_resume = ehci_hub_resume, -+#endif -+ .relinquish_port = ehci_relinquish_port, -+ .port_handed_over = ehci_port_handed_over, -+ -+ .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, -+}; -+ -+static const struct hc_driver ehci_ar91xx_hc_driver = { -+ .description = hcd_name, -+ .product_desc = "Atheros AR91xx built-in EHCI controller", -+ .hcd_priv_size = sizeof(struct ehci_hcd), -+ .irq = ehci_irq, -+ .flags = HCD_MEMORY | HCD_USB2, -+ -+ .reset = ehci_ar91xx_init, -+ .start = ehci_run, -+ .stop = ehci_stop, -+ .shutdown = ehci_shutdown, -+ -+ .urb_enqueue = ehci_urb_enqueue, -+ .urb_dequeue = ehci_urb_dequeue, -+ .endpoint_disable = ehci_endpoint_disable, -+ .endpoint_reset = ehci_endpoint_reset, -+ -+ .get_frame_number = ehci_get_frame, -+ -+ .hub_status_data = ehci_hub_status_data, -+ .hub_control = ehci_hub_control, -+#ifdef CONFIG_PM -+ .hub_suspend = ehci_hub_suspend, -+ .hub_resume = ehci_hub_resume, -+#endif -+ .relinquish_port = ehci_relinquish_port, -+ .port_handed_over = ehci_port_handed_over, -+ -+ .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, -+}; -+ -+static int ehci_ar71xx_driver_probe(struct platform_device *pdev) -+{ -+ struct ar71xx_ehci_platform_data *pdata; -+ struct usb_hcd *hcd = NULL; -+ int ret; -+ -+ if (usb_disabled()) -+ return -ENODEV; -+ -+ pdata = pdev->dev.platform_data; -+ if (!pdata) { -+ dev_err(&pdev->dev, "no platform data specified for %s\n", -+ dev_name(&pdev->dev)); -+ return -ENODEV; -+ } -+ -+ if (pdata->is_ar91xx) -+ ret = ehci_ar71xx_probe(&ehci_ar91xx_hc_driver, &hcd, pdev); -+ else -+ ret = ehci_ar71xx_probe(&ehci_ar71xx_hc_driver, &hcd, pdev); -+ -+ return ret; -+} -+ -+static int ehci_ar71xx_driver_remove(struct platform_device *pdev) -+{ -+ struct usb_hcd *hcd = platform_get_drvdata(pdev); -+ -+ ehci_ar71xx_remove(hcd, pdev); -+ return 0; -+} -+ -+MODULE_ALIAS("platform:ar71xx-ehci"); -+ -+static struct platform_driver ehci_ar71xx_driver = { -+ .probe = ehci_ar71xx_driver_probe, -+ .remove = ehci_ar71xx_driver_remove, -+ .driver = { -+ .name = "ar71xx-ehci", -+ } -+}; -diff -Nur linux-2.6.37.orig/drivers/usb/host/ehci-hcd.c linux-2.6.37/drivers/usb/host/ehci-hcd.c ---- linux-2.6.37.orig/drivers/usb/host/ehci-hcd.c 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/usb/host/ehci-hcd.c 2011-01-11 20:25:48.000000000 +0100 -@@ -1216,6 +1216,11 @@ - #define PLATFORM_DRIVER ehci_octeon_driver - #endif - -+#ifdef CONFIG_USB_EHCI_AR71XX -+#include "ehci-ar71xx.c" -+#define PLATFORM_DRIVER ehci_ar71xx_driver -+#endif -+ - #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ - !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \ - !defined(XILINX_OF_PLATFORM_DRIVER) -diff -Nur linux-2.6.37.orig/drivers/usb/host/ohci-ar71xx.c linux-2.6.37/drivers/usb/host/ohci-ar71xx.c ---- linux-2.6.37.orig/drivers/usb/host/ohci-ar71xx.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/drivers/usb/host/ohci-ar71xx.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,165 @@ -+/* -+ * OHCI HCD (Host Controller Driver) for USB. -+ * -+ * Bus Glue for Atheros AR71xx built-in OHCI controller. -+ * -+ * Copyright (C) 2008 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * Copyright (C) 2007 Atheros Communications, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+extern int usb_disabled(void); -+ -+static int usb_hcd_ar71xx_probe(const struct hc_driver *driver, -+ struct platform_device *pdev) -+{ -+ struct usb_hcd *hcd; -+ struct resource *res; -+ int irq; -+ int ret; -+ -+ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); -+ if (!res) { -+ dev_dbg(&pdev->dev, "no IRQ specified for %s\n", -+ dev_name(&pdev->dev)); -+ return -ENODEV; -+ } -+ irq = res->start; -+ -+ hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev)); -+ if (!hcd) -+ return -ENOMEM; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (!res) { -+ dev_dbg(&pdev->dev, "no base address specified for %s\n", -+ dev_name(&pdev->dev)); -+ ret = -ENODEV; -+ goto err_put_hcd; -+ } -+ hcd->rsrc_start = res->start; -+ hcd->rsrc_len = res->end - res->start + 1; -+ -+ if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { -+ dev_dbg(&pdev->dev, "controller already in use\n"); -+ ret = -EBUSY; -+ goto err_put_hcd; -+ } -+ -+ hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); -+ if (!hcd->regs) { -+ dev_dbg(&pdev->dev, "error mapping memory\n"); -+ ret = -EFAULT; -+ goto err_release_region; -+ } -+ -+ ohci_hcd_init(hcd_to_ohci(hcd)); -+ -+ ret = usb_add_hcd(hcd, irq, IRQF_DISABLED); -+ if (ret) -+ goto err_stop_hcd; -+ -+ return 0; -+ -+ err_stop_hcd: -+ iounmap(hcd->regs); -+ err_release_region: -+ release_mem_region(hcd->rsrc_start, hcd->rsrc_len); -+ err_put_hcd: -+ usb_put_hcd(hcd); -+ return ret; -+} -+ -+void usb_hcd_ar71xx_remove(struct usb_hcd *hcd, struct platform_device *pdev) -+{ -+ usb_remove_hcd(hcd); -+ iounmap(hcd->regs); -+ release_mem_region(hcd->rsrc_start, hcd->rsrc_len); -+ usb_put_hcd(hcd); -+} -+ -+static int __devinit ohci_ar71xx_start(struct usb_hcd *hcd) -+{ -+ struct ohci_hcd *ohci = hcd_to_ohci(hcd); -+ int ret; -+ -+ ret = ohci_init(ohci); -+ if (ret < 0) -+ return ret; -+ -+ ret = ohci_run(ohci); -+ if (ret < 0) -+ goto err; -+ -+ return 0; -+ -+ err: -+ ohci_stop(hcd); -+ return ret; -+} -+ -+static const struct hc_driver ohci_ar71xx_hc_driver = { -+ .description = hcd_name, -+ .product_desc = "Atheros AR71xx built-in OHCI controller", -+ .hcd_priv_size = sizeof(struct ohci_hcd), -+ -+ .irq = ohci_irq, -+ .flags = HCD_USB11 | HCD_MEMORY, -+ -+ .start = ohci_ar71xx_start, -+ .stop = ohci_stop, -+ .shutdown = ohci_shutdown, -+ -+ .urb_enqueue = ohci_urb_enqueue, -+ .urb_dequeue = ohci_urb_dequeue, -+ .endpoint_disable = ohci_endpoint_disable, -+ -+ /* -+ * scheduling support -+ */ -+ .get_frame_number = ohci_get_frame, -+ -+ /* -+ * root hub support -+ */ -+ .hub_status_data = ohci_hub_status_data, -+ .hub_control = ohci_hub_control, -+ .start_port_reset = ohci_start_port_reset, -+}; -+ -+static int ohci_hcd_ar71xx_drv_probe(struct platform_device *pdev) -+{ -+ if (usb_disabled()) -+ return -ENODEV; -+ -+ return usb_hcd_ar71xx_probe(&ohci_ar71xx_hc_driver, pdev); -+} -+ -+static int ohci_hcd_ar71xx_drv_remove(struct platform_device *pdev) -+{ -+ struct usb_hcd *hcd = platform_get_drvdata(pdev); -+ -+ usb_hcd_ar71xx_remove(hcd, pdev); -+ return 0; -+} -+ -+MODULE_ALIAS("platform:ar71xx-ohci"); -+ -+static struct platform_driver ohci_hcd_ar71xx_driver = { -+ .probe = ohci_hcd_ar71xx_drv_probe, -+ .remove = ohci_hcd_ar71xx_drv_remove, -+ .shutdown = usb_hcd_platform_shutdown, -+ .driver = { -+ .name = "ar71xx-ohci", -+ .owner = THIS_MODULE, -+ }, -+}; -diff -Nur linux-2.6.37.orig/drivers/usb/host/ohci-hcd.c linux-2.6.37/drivers/usb/host/ohci-hcd.c ---- linux-2.6.37.orig/drivers/usb/host/ohci-hcd.c 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/usb/host/ohci-hcd.c 2011-01-11 20:25:48.000000000 +0100 -@@ -1111,6 +1111,11 @@ - #define PLATFORM_DRIVER ohci_octeon_driver - #endif - -+#ifdef CONFIG_USB_OHCI_AR71XX -+#include "ohci-ar71xx.c" -+#define PLATFORM_DRIVER ohci_hcd_ar71xx_driver -+#endif -+ - #if !defined(PCI_DRIVER) && \ - !defined(PLATFORM_DRIVER) && \ - !defined(OMAP1_PLATFORM_DRIVER) && \ -diff -Nur linux-2.6.37.orig/drivers/watchdog/Kconfig linux-2.6.37/drivers/watchdog/Kconfig ---- linux-2.6.37.orig/drivers/watchdog/Kconfig 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/watchdog/Kconfig 2011-01-11 20:25:48.000000000 +0100 -@@ -930,6 +930,13 @@ - To compile this driver as a loadable module, choose M here. - The module will be called bcm63xx_wdt. - -+config AR71XX_WDT -+ tristate "Atheros AR71xx Watchdog Timer" -+ depends on ATHEROS_AR71XX -+ help -+ Hardware driver for the built-in watchdog timer on the Atheros -+ AR71xx SoCs. -+ - # PARISC Architecture - - # POWERPC Architecture -diff -Nur linux-2.6.37.orig/drivers/watchdog/Makefile linux-2.6.37/drivers/watchdog/Makefile ---- linux-2.6.37.orig/drivers/watchdog/Makefile 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/watchdog/Makefile 2011-01-11 20:25:48.000000000 +0100 -@@ -117,6 +117,7 @@ - obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o - obj-$(CONFIG_AR7_WDT) += ar7_wdt.o - obj-$(CONFIG_TXX9_WDT) += txx9wdt.o -+obj-$(CONFIG_AR71XX_WDT) += ar71xx_wdt.o - obj-$(CONFIG_OCTEON_WDT) += octeon-wdt.o - octeon-wdt-y := octeon-wdt-main.o octeon-wdt-nmi.o - -diff -Nur linux-2.6.37.orig/drivers/watchdog/ar71xx_wdt.c linux-2.6.37/drivers/watchdog/ar71xx_wdt.c ---- linux-2.6.37.orig/drivers/watchdog/ar71xx_wdt.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/drivers/watchdog/ar71xx_wdt.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,270 @@ -+/* -+ * Driver for the Atheros AR71xx SoC's built-in hardware watchdog timer. -+ * -+ * Copyright (C) 2008 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This driver was based on: drivers/watchdog/ixp4xx_wdt.c -+ * Author: Deepak Saxena -+ * Copyright 2004 (c) MontaVista, Software, Inc. -+ * -+ * which again was based on sa1100 driver, -+ * Copyright (C) 2000 Oleg Drokin -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#define DRV_NAME "ar71xx-wdt" -+#define DRV_DESC "Atheros AR71xx hardware watchdog driver" -+#define DRV_VERSION "0.1.0" -+ -+#define WDT_TIMEOUT 15 /* seconds */ -+ -+static int nowayout = WATCHDOG_NOWAYOUT; -+ -+#ifdef CONFIG_WATCHDOG_NOWAYOUT -+module_param(nowayout, int, 0); -+MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started " -+ "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); -+#endif -+ -+static unsigned long wdt_flags; -+ -+#define WDT_FLAGS_BUSY 0 -+#define WDT_FLAGS_EXPECT_CLOSE 1 -+ -+static int wdt_timeout = WDT_TIMEOUT; -+static int boot_status; -+static int max_timeout; -+ -+static void inline ar71xx_wdt_keepalive(void) -+{ -+ ar71xx_reset_wr(AR71XX_RESET_REG_WDOG, ar71xx_ahb_freq * wdt_timeout); -+} -+ -+static void inline ar71xx_wdt_enable(void) -+{ -+ printk(KERN_DEBUG DRV_NAME ": enabling watchdog timer\n"); -+ ar71xx_wdt_keepalive(); -+ ar71xx_reset_wr(AR71XX_RESET_REG_WDOG_CTRL, WDOG_CTRL_ACTION_FCR); -+} -+ -+static void inline ar71xx_wdt_disable(void) -+{ -+ printk(KERN_DEBUG DRV_NAME ": disabling watchdog timer\n"); -+ ar71xx_reset_wr(AR71XX_RESET_REG_WDOG_CTRL, WDOG_CTRL_ACTION_NONE); -+} -+ -+static int ar71xx_wdt_set_timeout(int val) -+{ -+ if (val < 1 || val > max_timeout) -+ return -EINVAL; -+ -+ wdt_timeout = val; -+ ar71xx_wdt_keepalive(); -+ -+ printk(KERN_DEBUG DRV_NAME ": timeout=%d secs\n", wdt_timeout); -+ -+ return 0; -+} -+ -+static int ar71xx_wdt_open(struct inode *inode, struct file *file) -+{ -+ if (test_and_set_bit(WDT_FLAGS_BUSY, &wdt_flags)) -+ return -EBUSY; -+ -+ clear_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags); -+ -+ ar71xx_wdt_enable(); -+ -+ return nonseekable_open(inode, file); -+} -+ -+static int ar71xx_wdt_release(struct inode *inode, struct file *file) -+{ -+ if (test_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags)) { -+ ar71xx_wdt_disable(); -+ } else { -+ printk(KERN_CRIT DRV_NAME ": device closed unexpectedly, " -+ "watchdog timer will not stop!\n"); -+ } -+ -+ clear_bit(WDT_FLAGS_BUSY, &wdt_flags); -+ clear_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags); -+ -+ return 0; -+} -+ -+static ssize_t ar71xx_wdt_write(struct file *file, const char *data, -+ size_t len, loff_t *ppos) -+{ -+ if (len) { -+ if (!nowayout) { -+ size_t i; -+ -+ clear_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags); -+ -+ for (i = 0; i != len; i++) { -+ char c; -+ -+ if (get_user(c, data + i)) -+ return -EFAULT; -+ -+ if (c == 'V') -+ set_bit(WDT_FLAGS_EXPECT_CLOSE, -+ &wdt_flags); -+ } -+ } -+ -+ ar71xx_wdt_keepalive(); -+ } -+ -+ return len; -+} -+ -+static struct watchdog_info ar71xx_wdt_info = { -+ .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | -+ WDIOF_MAGICCLOSE | WDIOF_CARDRESET, -+ .firmware_version = 0, -+ .identity = "AR71XX watchdog", -+}; -+ -+static int ar71xx_wdt_ioctl(struct inode *inode, struct file *file, -+ unsigned int cmd, unsigned long arg) -+{ -+ int t; -+ int ret; -+ -+ switch (cmd) { -+ case WDIOC_GETSUPPORT: -+ ret = copy_to_user((struct watchdog_info *)arg, -+ &ar71xx_wdt_info, -+ sizeof(&ar71xx_wdt_info)) ? -EFAULT : 0; -+ break; -+ -+ case WDIOC_GETSTATUS: -+ ret = put_user(0, (int *)arg) ? -EFAULT : 0; -+ break; -+ -+ case WDIOC_GETBOOTSTATUS: -+ ret = put_user(boot_status, (int *)arg) ? -EFAULT : 0; -+ break; -+ -+ case WDIOC_KEEPALIVE: -+ ar71xx_wdt_keepalive(); -+ ret = 0; -+ break; -+ -+ case WDIOC_SETTIMEOUT: -+ ret = get_user(t, (int *)arg) ? -EFAULT : 0; -+ if (ret) -+ break; -+ -+ ret = ar71xx_wdt_set_timeout(t); -+ if (ret) -+ break; -+ -+ /* fallthrough */ -+ case WDIOC_GETTIMEOUT: -+ ret = put_user(wdt_timeout, (int *)arg) ? -EFAULT : 0; -+ break; -+ -+ default: -+ ret = -ENOTTY; -+ break; -+ } -+ -+ return ret; -+} -+ -+static const struct file_operations ar71xx_wdt_fops = { -+ .owner = THIS_MODULE, -+ .write = ar71xx_wdt_write, -+ .ioctl = ar71xx_wdt_ioctl, -+ .open = ar71xx_wdt_open, -+ .release = ar71xx_wdt_release, -+}; -+ -+static struct miscdevice ar71xx_wdt_miscdev = { -+ .minor = WATCHDOG_MINOR, -+ .name = "watchdog", -+ .fops = &ar71xx_wdt_fops, -+}; -+ -+static int __devinit ar71xx_wdt_probe(struct platform_device *pdev) -+{ -+ int ret; -+ -+ max_timeout = (0xfffffffful / ar71xx_ahb_freq); -+ wdt_timeout = (max_timeout < WDT_TIMEOUT) ? max_timeout : WDT_TIMEOUT; -+ -+ boot_status = -+ (ar71xx_reset_rr(AR71XX_RESET_REG_WDOG_CTRL) & WDOG_CTRL_LAST_RESET) ? -+ WDIOF_CARDRESET : 0; -+ -+ ret = misc_register(&ar71xx_wdt_miscdev); -+ if (ret) -+ goto err_out; -+ -+ printk(KERN_INFO DRV_DESC " version " DRV_VERSION "\n"); -+ -+ printk(KERN_DEBUG DRV_NAME ": timeout=%d secs (max=%d)\n", -+ wdt_timeout, max_timeout); -+ -+ return 0; -+ -+err_out: -+ return ret; -+} -+ -+static int __devexit ar71xx_wdt_remove(struct platform_device *pdev) -+{ -+ misc_deregister(&ar71xx_wdt_miscdev); -+ return 0; -+} -+ -+static struct platform_driver ar71xx_wdt_driver = { -+ .probe = ar71xx_wdt_probe, -+ .remove = __devexit_p(ar71xx_wdt_remove), -+ .driver = { -+ .name = DRV_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init ar71xx_wdt_init(void) -+{ -+ return platform_driver_register(&ar71xx_wdt_driver); -+} -+module_init(ar71xx_wdt_init); -+ -+static void __exit ar71xx_wdt_exit(void) -+{ -+ platform_driver_unregister(&ar71xx_wdt_driver); -+} -+module_exit(ar71xx_wdt_exit); -+ -+MODULE_DESCRIPTION(DRV_DESC); -+MODULE_VERSION(DRV_VERSION); -+MODULE_AUTHOR("Gabor Juhos -- * Copyright (c) 2009 Imre Kaloz -+ * ath9k platform data defines - * -- * Permission to use, copy, modify, and/or distribute this software for any -- * purpose with or without fee is hereby granted, provided that the above -- * copyright notice and this permission notice appear in all copies. -+ * Copyright (C) 2008 Gabor Juhos - * -- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. - */ - - #ifndef _LINUX_ATH9K_PLATFORM_H -@@ -23,6 +15,9 @@ - - struct ath9k_platform_data { - u16 eeprom_data[ATH9K_PLAT_EEP_MAX_WORDS]; -+ u8 *macaddr; -+ -+ unsigned long quirk_wndr3700:1; - }; - - #endif /* _LINUX_ATH9K_PLATFORM_H */ -diff -Nur linux-2.6.37.orig/include/linux/gpio_buttons.h linux-2.6.37/include/linux/gpio_buttons.h ---- linux-2.6.37.orig/include/linux/gpio_buttons.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/include/linux/gpio_buttons.h 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,33 @@ -+/* -+ * Definitions for the GPIO buttons interface driver -+ * -+ * Copyright (C) 2007-2010 Gabor Juhos -+ * -+ * This file was based on: /include/linux/gpio_keys.h -+ * The original gpio_keys.h seems not to have a license. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ */ -+ -+#ifndef _GPIO_BUTTONS_H_ -+#define _GPIO_BUTTONS_H_ -+ -+struct gpio_button { -+ int gpio; /* GPIO line number */ -+ int active_low; -+ char *desc; /* button description */ -+ int type; /* input event type (EV_KEY, EV_SW) */ -+ int code; /* input event code (KEY_*, SW_*) */ -+ int threshold; /* count threshold */ -+}; -+ -+struct gpio_buttons_platform_data { -+ struct gpio_button *buttons; -+ int nbuttons; /* number of buttons */ -+ int poll_interval; /* polling interval */ -+}; -+ -+#endif /* _GPIO_BUTTONS_H_ */ -diff -Nur linux-2.6.37.orig/include/linux/gpio_dev.h linux-2.6.37/include/linux/gpio_dev.h ---- linux-2.6.37.orig/include/linux/gpio_dev.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/include/linux/gpio_dev.h 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,11 @@ -+#ifndef _GPIODEV_H__ -+#define _GPIODEV_H__ -+ -+#define IOC_GPIODEV_MAGIC 'B' -+#define GPIO_GET _IO(IOC_GPIODEV_MAGIC, 10) -+#define GPIO_SET _IO(IOC_GPIODEV_MAGIC, 11) -+#define GPIO_CLEAR _IO(IOC_GPIODEV_MAGIC, 12) -+#define GPIO_DIR_IN _IO(IOC_GPIODEV_MAGIC, 13) -+#define GPIO_DIR_OUT _IO(IOC_GPIODEV_MAGIC, 14) -+ -+#endif -diff -Nur linux-2.6.37.orig/include/linux/netdevice.h linux-2.6.37/include/linux/netdevice.h ---- linux-2.6.37.orig/include/linux/netdevice.h 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/include/linux/netdevice.h 2011-01-11 20:25:48.000000000 +0100 -@@ -957,6 +957,7 @@ - void *ax25_ptr; /* AX.25 specific data */ - struct wireless_dev *ieee80211_ptr; /* IEEE 802.11 specific data, - assign before registering */ -+ void *phy_ptr; /* PHY device specific data */ - - /* - * Cache lines mostly used on receive path (including eth_type_trans()) -diff -Nur linux-2.6.37.orig/include/linux/nxp_74hc153.h linux-2.6.37/include/linux/nxp_74hc153.h ---- linux-2.6.37.orig/include/linux/nxp_74hc153.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/include/linux/nxp_74hc153.h 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,24 @@ -+/* -+ * NXP 74HC153 - Dual 4-input multiplexer defines -+ * -+ * Copyright (C) 2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#ifndef _NXP_74HC153_H -+#define _NXP_74HC153_H -+ -+#define NXP_74HC153_DRIVER_NAME "nxp-74hc153" -+ -+struct nxp_74hc153_platform_data { -+ unsigned gpio_base; -+ unsigned gpio_pin_s0; -+ unsigned gpio_pin_s1; -+ unsigned gpio_pin_1y; -+ unsigned gpio_pin_2y; -+}; -+ -+#endif /* _NXP_74HC153_H */ -diff -Nur linux-2.6.37.orig/include/linux/phy.h linux-2.6.37/include/linux/phy.h ---- linux-2.6.37.orig/include/linux/phy.h 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/include/linux/phy.h 2011-01-11 20:25:48.000000000 +0100 -@@ -332,6 +332,20 @@ - void (*adjust_link)(struct net_device *dev); - - void (*adjust_state)(struct net_device *dev); -+ -+ /* -+ * By default these point to the original functions -+ * with the same name. adding them to the phy_device -+ * allows the phy driver to override them for packet -+ * mangling if the ethernet driver supports it -+ * This is required to support some really horrible -+ * switches such as the Marvell 88E6060 -+ */ -+ int (*netif_receive_skb)(struct sk_buff *skb); -+ int (*netif_rx)(struct sk_buff *skb); -+ -+ /* alignment offset for packets */ -+ int pkt_align; - }; - #define to_phy_device(d) container_of(d, struct phy_device, dev) - -@@ -508,6 +522,7 @@ - void phy_stop_machine(struct phy_device *phydev); - int phy_ethtool_sset(struct phy_device *phydev, struct ethtool_cmd *cmd); - int phy_ethtool_gset(struct phy_device *phydev, struct ethtool_cmd *cmd); -+int phy_ethtool_ioctl(struct phy_device *phydev, void *useraddr); - int phy_mii_ioctl(struct phy_device *phydev, - struct ifreq *ifr, int cmd); - int phy_start_interrupts(struct phy_device *phydev); -diff -Nur linux-2.6.37.orig/include/linux/spi/vsc7385.h linux-2.6.37/include/linux/spi/vsc7385.h ---- linux-2.6.37.orig/include/linux/spi/vsc7385.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/include/linux/spi/vsc7385.h 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,19 @@ -+/* -+ * Platform data definition for the Vitesse VSC7385 ethernet switch driver -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+struct vsc7385_platform_data { -+ void (* reset)(void); -+ char *ucode_name; -+ struct { -+ u32 tx_ipg:5; -+ u32 bit2:1; -+ u32 clk_sel:3; -+ } mac_cfg; -+}; -diff -Nur linux-2.6.37.orig/net/dsa/ar7240.c linux-2.6.37/net/dsa/ar7240.c ---- linux-2.6.37.orig/net/dsa/ar7240.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/net/dsa/ar7240.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,736 @@ -+/* -+ * DSA driver for the built-in ethernet switch of the Atheros AR7240 SoC -+ * Copyright (c) 2010 Gabor Juhos -+ * -+ * This file was based on: -+ * net/dsa/mv88e6060.c - Driver for Marvell 88e6060 switch chips -+ * Copyright (c) 2008 Marvell Semiconductor -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "dsa_priv.h" -+ -+#define BITM(_count) (BIT(_count) - 1) -+ -+#define AR7240_REG_MASK_CTRL 0x00 -+#define AR7240_MASK_CTRL_REVISION_M BITM(8) -+#define AR7240_MASK_CTRL_VERSION_M BITM(8) -+#define AR7240_MASK_CTRL_VERSION_S 8 -+#define AR7240_MASK_CTRL_SOFT_RESET BIT(31) -+ -+#define AR7240_REG_MAC_ADDR0 0x20 -+#define AR7240_REG_MAC_ADDR1 0x24 -+ -+#define AR7240_REG_FLOOD_MASK 0x2c -+#define AR7240_FLOOD_MASK_BROAD_TO_CPU BIT(26) -+ -+#define AR7240_REG_GLOBAL_CTRL 0x30 -+#define AR7240_GLOBAL_CTRL_MTU_M BITM(12) -+ -+#define AR7240_REG_AT_CTRL 0x5c -+#define AR7240_AT_CTRL_ARP_EN BIT(20) -+ -+#define AR7240_REG_TAG_PRIORITY 0x70 -+ -+#define AR7240_REG_SERVICE_TAG 0x74 -+#define AR7240_SERVICE_TAG_M BITM(16) -+ -+#define AR7240_REG_CPU_PORT 0x78 -+#define AR7240_MIRROR_PORT_S 4 -+#define AR7240_CPU_PORT_EN BIT(8) -+ -+#define AR7240_REG_MIB_FUNCTION0 0x80 -+#define AR7240_MIB_TIMER_M BITM(16) -+#define AR7240_MIB_AT_HALF_EN BIT(16) -+#define AR7240_MIB_BUSY BIT(17) -+#define AR7240_MIB_FUNC_S 24 -+#define AR7240_MIB_FUNC_NO_OP 0x0 -+#define AR7240_MIB_FUNC_FLUSH 0x1 -+#define AR7240_MIB_FUNC_CAPTURE 0x3 -+ -+#define AR7240_REG_MDIO_CTRL 0x98 -+#define AR7240_MDIO_CTRL_DATA_M BITM(16) -+#define AR7240_MDIO_CTRL_REG_ADDR_S 16 -+#define AR7240_MDIO_CTRL_PHY_ADDR_S 21 -+#define AR7240_MDIO_CTRL_CMD_WRITE 0 -+#define AR7240_MDIO_CTRL_CMD_READ BIT(27) -+#define AR7240_MDIO_CTRL_MASTER_EN BIT(30) -+#define AR7240_MDIO_CTRL_BUSY BIT(31) -+ -+#define AR7240_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100) -+ -+#define AR7240_REG_PORT_STATUS(_port) (AR7240_REG_PORT_BASE((_port)) + 0x00) -+#define AR7240_PORT_STATUS_SPEED_M BITM(2) -+#define AR7240_PORT_STATUS_SPEED_10 0 -+#define AR7240_PORT_STATUS_SPEED_100 1 -+#define AR7240_PORT_STATUS_SPEED_1000 2 -+#define AR7240_PORT_STATUS_TXMAC BIT(2) -+#define AR7240_PORT_STATUS_RXMAC BIT(3) -+#define AR7240_PORT_STATUS_TXFLOW BIT(4) -+#define AR7240_PORT_STATUS_RXFLOW BIT(5) -+#define AR7240_PORT_STATUS_DUPLEX BIT(6) -+#define AR7240_PORT_STATUS_LINK_UP BIT(8) -+#define AR7240_PORT_STATUS_LINK_AUTO BIT(9) -+#define AR7240_PORT_STATUS_LINK_PAUSE BIT(10) -+ -+#define AR7240_REG_PORT_CTRL(_port) (AR7240_REG_PORT_BASE((_port)) + 0x04) -+#define AR7240_PORT_CTRL_STATE_M BITM(3) -+#define AR7240_PORT_CTRL_STATE_DISABLED 0 -+#define AR7240_PORT_CTRL_STATE_BLOCK 1 -+#define AR7240_PORT_CTRL_STATE_LISTEN 2 -+#define AR7240_PORT_CTRL_STATE_LEARN 3 -+#define AR7240_PORT_CTRL_STATE_FORWARD 4 -+#define AR7240_PORT_CTRL_LEARN_LOCK BIT(7) -+#define AR7240_PORT_CTRL_VLAN_MODE_S 8 -+#define AR7240_PORT_CTRL_VLAN_MODE_KEEP 0 -+#define AR7240_PORT_CTRL_VLAN_MODE_STRIP 1 -+#define AR7240_PORT_CTRL_VLAN_MODE_ADD 2 -+#define AR7240_PORT_CTRL_VLAN_MODE_DOUBLE_TAG 3 -+#define AR7240_PORT_CTRL_IGMP_SNOOP BIT(10) -+#define AR7240_PORT_CTRL_HEADER BIT(11) -+#define AR7240_PORT_CTRL_MAC_LOOP BIT(12) -+#define AR7240_PORT_CTRL_SINGLE_VLAN BIT(13) -+#define AR7240_PORT_CTRL_LEARN BIT(14) -+#define AR7240_PORT_CTRL_DOUBLE_TAG BIT(15) -+#define AR7240_PORT_CTRL_MIRROR_TX BIT(16) -+#define AR7240_PORT_CTRL_MIRROR_RX BIT(17) -+ -+#define AR7240_REG_PORT_VLAN(_port) (AR7240_REG_PORT_BASE((_port)) + 0x08) -+ -+#define AR7240_PORT_VLAN_DEFAULT_ID_S 0 -+#define AR7240_PORT_VLAN_DEST_PORTS_S 16 -+ -+#define AR7240_REG_STATS_BASE(_port) (0x20000 + (_port) * 0x100) -+ -+#define AR7240_STATS_RXBROAD 0x00 -+#define AR7240_STATS_RXPAUSE 0x04 -+#define AR7240_STATS_RXMULTI 0x08 -+#define AR7240_STATS_RXFCSERR 0x0c -+#define AR7240_STATS_RXALIGNERR 0x10 -+#define AR7240_STATS_RXRUNT 0x14 -+#define AR7240_STATS_RXFRAGMENT 0x18 -+#define AR7240_STATS_RX64BYTE 0x1c -+#define AR7240_STATS_RX128BYTE 0x20 -+#define AR7240_STATS_RX256BYTE 0x24 -+#define AR7240_STATS_RX512BYTE 0x28 -+#define AR7240_STATS_RX1024BYTE 0x2c -+#define AR7240_STATS_RX1518BYTE 0x30 -+#define AR7240_STATS_RXMAXBYTE 0x34 -+#define AR7240_STATS_RXTOOLONG 0x38 -+#define AR7240_STATS_RXGOODBYTE 0x3c -+#define AR7240_STATS_RXBADBYTE 0x44 -+#define AR7240_STATS_RXOVERFLOW 0x4c -+#define AR7240_STATS_FILTERED 0x50 -+#define AR7240_STATS_TXBROAD 0x54 -+#define AR7240_STATS_TXPAUSE 0x58 -+#define AR7240_STATS_TXMULTI 0x5c -+#define AR7240_STATS_TXUNDERRUN 0x60 -+#define AR7240_STATS_TX64BYTE 0x64 -+#define AR7240_STATS_TX128BYTE 0x68 -+#define AR7240_STATS_TX256BYTE 0x6c -+#define AR7240_STATS_TX512BYTE 0x70 -+#define AR7240_STATS_TX1024BYTE 0x74 -+#define AR7240_STATS_TX1518BYTE 0x78 -+#define AR7240_STATS_TXMAXBYTE 0x7c -+#define AR7240_STATS_TXOVERSIZE 0x80 -+#define AR7240_STATS_TXBYTE 0x84 -+#define AR7240_STATS_TXCOLLISION 0x8c -+#define AR7240_STATS_TXABORTCOL 0x90 -+#define AR7240_STATS_TXMULTICOL 0x94 -+#define AR7240_STATS_TXSINGLECOL 0x98 -+#define AR7240_STATS_TXEXCDEFER 0x9c -+#define AR7240_STATS_TXDEFER 0xa0 -+#define AR7240_STATS_TXLATECOL 0xa4 -+ -+#define AR7240_PORT_CPU 0 -+#define AR7240_NUM_PORTS 6 -+#define AR7240_NUM_PHYS 5 -+ -+#define AR7240_PHY_ID1 0x004d -+#define AR7240_PHY_ID2 0xd041 -+ -+#define AR7240_PORT_MASK(_port) BIT((_port)) -+#define AR7240_PORT_MASK_ALL BITM(AR7240_NUM_PORTS) -+#define AR7240_PORT_MASK_BUT(_port) (AR7240_PORT_MASK_ALL & ~BIT((_port))) -+ -+struct ar7240sw { -+ struct mii_bus *mii_bus; -+ struct mutex reg_mutex; -+ struct mutex stats_mutex; -+}; -+ -+struct ar7240sw_hw_stat { -+ char string[ETH_GSTRING_LEN]; -+ int sizeof_stat; -+ int reg; -+}; -+ -+static inline struct ar7240sw *dsa_to_ar7240sw(struct dsa_switch *ds) -+{ -+ return (struct ar7240sw *)(ds + 1); -+} -+ -+static inline void ar7240sw_init(struct ar7240sw *as, struct mii_bus *mii) -+{ -+ as->mii_bus = mii; -+ mutex_init(&as->reg_mutex); -+ mutex_init(&as->stats_mutex); -+} -+ -+static inline u16 mk_phy_addr(u32 reg) -+{ -+ return (0x17 & ((reg >> 4) | 0x10)); -+} -+ -+static inline u16 mk_phy_reg(u32 reg) -+{ -+ return ((reg << 1) & 0x1e); -+} -+ -+static inline u16 mk_high_addr(u32 reg) -+{ -+ return ((reg >> 7) & 0x1ff); -+} -+ -+static u32 __ar7240sw_reg_read(struct ar7240sw *as, u32 reg) -+{ -+ struct mii_bus *mii = as->mii_bus; -+ u16 phy_addr; -+ u16 phy_reg; -+ u32 hi, lo; -+ -+ reg = (reg & 0xfffffffc) >> 2; -+ -+ mdiobus_write(mii, 0x1f, 0x10, mk_high_addr(reg)); -+ -+ phy_addr = mk_phy_addr(reg); -+ phy_reg = mk_phy_reg(reg); -+ -+ lo = (u32) mdiobus_read(mii, phy_addr, phy_reg); -+ hi = (u32) mdiobus_read(mii, phy_addr, phy_reg + 1); -+ -+ return ((hi << 16) | lo); -+} -+ -+static void __ar7240sw_reg_write(struct ar7240sw *as, u32 reg, u32 val) -+{ -+ struct mii_bus *mii = as->mii_bus; -+ u16 phy_addr; -+ u16 phy_reg; -+ -+ reg = (reg & 0xfffffffc) >> 2; -+ -+ mdiobus_write(mii, 0x1f, 0x10, mk_high_addr(reg)); -+ -+ phy_addr = mk_phy_addr(reg); -+ phy_reg = mk_phy_reg(reg); -+ -+ mdiobus_write(mii, phy_addr, phy_reg + 1, (val >> 16)); -+ mdiobus_write(mii, phy_addr, phy_reg, (val & 0xffff)); -+} -+ -+static u32 ar7240sw_reg_read(struct ar7240sw *as, u32 reg_addr) -+{ -+ u32 ret; -+ -+ mutex_lock(&as->reg_mutex); -+ ret = __ar7240sw_reg_read(as, reg_addr); -+ mutex_unlock(&as->reg_mutex); -+ -+ return ret; -+} -+ -+static void ar7240sw_reg_write(struct ar7240sw *as, u32 reg_addr, u32 reg_val) -+{ -+ mutex_lock(&as->reg_mutex); -+ __ar7240sw_reg_write(as, reg_addr, reg_val); -+ mutex_unlock(&as->reg_mutex); -+} -+ -+static u32 ar7240sw_reg_rmw(struct ar7240sw *as, u32 reg, u32 mask, u32 val) -+{ -+ u32 t; -+ -+ mutex_lock(&as->reg_mutex); -+ t = __ar7240sw_reg_read(as, reg); -+ t &= ~mask; -+ t |= val; -+ __ar7240sw_reg_write(as, reg, t); -+ mutex_unlock(&as->reg_mutex); -+ -+ return t; -+} -+ -+static void ar7240sw_reg_set(struct ar7240sw *as, u32 reg, u32 val) -+{ -+ u32 t; -+ -+ mutex_lock(&as->reg_mutex); -+ t = __ar7240sw_reg_read(as, reg); -+ t |= val; -+ __ar7240sw_reg_write(as, reg, t); -+ mutex_unlock(&as->reg_mutex); -+} -+ -+static int ar7240sw_reg_wait(struct ar7240sw *as, u32 reg, u32 mask, u32 val, -+ unsigned timeout) -+{ -+ int i; -+ -+ for (i = 0; i < timeout; i++) { -+ u32 t; -+ -+ t = ar7240sw_reg_read(as, reg); -+ if ((t & mask) == val) -+ return 0; -+ -+ msleep(1); -+ } -+ -+ return -ETIMEDOUT; -+} -+ -+static u16 ar7240sw_phy_read(struct ar7240sw *as, unsigned phy_addr, -+ unsigned reg_addr) -+{ -+ u32 t; -+ int err; -+ -+ if (phy_addr >= AR7240_NUM_PHYS) -+ return 0xffff; -+ -+ t = (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) | -+ (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) | -+ AR7240_MDIO_CTRL_MASTER_EN | -+ AR7240_MDIO_CTRL_BUSY | -+ AR7240_MDIO_CTRL_CMD_READ; -+ -+ ar7240sw_reg_write(as, AR7240_REG_MDIO_CTRL, t); -+ err = ar7240sw_reg_wait(as, AR7240_REG_MDIO_CTRL, -+ AR7240_MDIO_CTRL_BUSY, 0, 5); -+ if (err) -+ return 0xffff; -+ -+ t = ar7240sw_reg_read(as, AR7240_REG_MDIO_CTRL); -+ return (t & AR7240_MDIO_CTRL_DATA_M); -+} -+ -+static int ar7240sw_phy_write(struct ar7240sw *as, unsigned phy_addr, -+ unsigned reg_addr, u16 reg_val) -+{ -+ u32 t; -+ int ret; -+ -+ if (phy_addr >= AR7240_NUM_PHYS) -+ return -EINVAL; -+ -+ t = (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) | -+ (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) | -+ AR7240_MDIO_CTRL_MASTER_EN | -+ AR7240_MDIO_CTRL_BUSY | -+ AR7240_MDIO_CTRL_CMD_WRITE | -+ reg_val; -+ -+ ar7240sw_reg_write(as, AR7240_REG_MDIO_CTRL, t); -+ ret = ar7240sw_reg_wait(as, AR7240_REG_MDIO_CTRL, -+ AR7240_MDIO_CTRL_BUSY, 0, 5); -+ return ret; -+} -+ -+static int ar7240sw_capture_stats(struct ar7240sw *as) -+{ -+ int ret; -+ -+ /* Capture the hardware statistics for all ports */ -+ ar7240sw_reg_write(as, AR7240_REG_MIB_FUNCTION0, -+ (AR7240_MIB_FUNC_CAPTURE << AR7240_MIB_FUNC_S)); -+ -+ /* Wait for the capturing to complete. */ -+ ret = ar7240sw_reg_wait(as, AR7240_REG_MIB_FUNCTION0, -+ AR7240_MIB_BUSY, 0, 10); -+ return ret; -+} -+ -+static void ar7240sw_disable_port(struct ar7240sw *as, unsigned port) -+{ -+ ar7240sw_reg_write(as, AR7240_REG_PORT_CTRL(port), -+ AR7240_PORT_CTRL_STATE_DISABLED); -+} -+ -+static int ar7240sw_reset(struct ar7240sw *as) -+{ -+ int ret; -+ int i; -+ -+ /* Set all ports to disabled state. */ -+ for (i = 0; i < AR7240_NUM_PORTS; i++) -+ ar7240sw_disable_port(as, i); -+ -+ /* Wait for transmit queues to drain. */ -+ msleep(2); -+ -+ /* Reset the switch. */ -+ ar7240sw_reg_write(as, AR7240_REG_MASK_CTRL, -+ AR7240_MASK_CTRL_SOFT_RESET); -+ -+ ret = ar7240sw_reg_wait(as, AR7240_REG_MASK_CTRL, -+ AR7240_MASK_CTRL_SOFT_RESET, 0, 1000); -+ return ret; -+} -+ -+static void ar7240sw_setup(struct ar7240sw *as) -+{ -+ /* Enable CPU port, and disable mirror port */ -+ ar7240sw_reg_write(as, AR7240_REG_CPU_PORT, -+ AR7240_CPU_PORT_EN | -+ (15 << AR7240_MIRROR_PORT_S)); -+ -+ /* Setup TAG priority mapping */ -+ ar7240sw_reg_write(as, AR7240_REG_TAG_PRIORITY, 0xfa50); -+ -+ /* Enable ARP frame acknowledge */ -+ ar7240sw_reg_set(as, AR7240_REG_AT_CTRL, AR7240_AT_CTRL_ARP_EN); -+ -+ /* Enable Broadcast frames transmitted to the CPU */ -+ ar7240sw_reg_set(as, AR7240_REG_FLOOD_MASK, -+ AR7240_FLOOD_MASK_BROAD_TO_CPU); -+ -+ /* setup MTU */ -+ ar7240sw_reg_rmw(as, AR7240_REG_GLOBAL_CTRL, AR7240_GLOBAL_CTRL_MTU_M, -+ 1536); -+ -+ /* setup Service TAG */ -+ ar7240sw_reg_rmw(as, AR7240_REG_SERVICE_TAG, AR7240_SERVICE_TAG_M, -+ ETH_P_QINQ); -+} -+ -+static void ar7240sw_setup_port(struct ar7240sw *as, unsigned port) -+{ -+ u32 ctrl; -+ u32 dest_ports; -+ u32 vlan; -+ -+ ctrl = AR7240_PORT_CTRL_STATE_FORWARD; -+ -+ if (port == AR7240_PORT_CPU) { -+ ar7240sw_reg_write(as, AR7240_REG_PORT_STATUS(port), -+ AR7240_PORT_STATUS_SPEED_1000 | -+ AR7240_PORT_STATUS_TXFLOW | -+ AR7240_PORT_STATUS_RXFLOW | -+ AR7240_PORT_STATUS_TXMAC | -+ AR7240_PORT_STATUS_RXMAC | -+ AR7240_PORT_STATUS_DUPLEX); -+ -+ /* allow the CPU port to talk to each of the 'real' ports */ -+ dest_ports = AR7240_PORT_MASK_BUT(port); -+ -+ /* remove service tag from ingress frames */ -+ ctrl |= AR7240_PORT_CTRL_DOUBLE_TAG; -+ } else { -+ ar7240sw_reg_write(as, AR7240_REG_PORT_STATUS(port), -+ AR7240_PORT_STATUS_LINK_AUTO); -+ -+ /* -+ * allow each of the 'real' ports to only talk to the CPU -+ * port. -+ */ -+ dest_ports = AR7240_PORT_MASK(port) | -+ AR7240_PORT_MASK(AR7240_PORT_CPU); -+ -+ /* add service tag to egress frames */ -+ ctrl |= (AR7240_PORT_CTRL_VLAN_MODE_DOUBLE_TAG << -+ AR7240_PORT_CTRL_VLAN_MODE_S); -+ } -+ -+ /* set default VID and and destination ports for this VLAN */ -+ vlan = port; -+ vlan |= (dest_ports << AR7240_PORT_VLAN_DEST_PORTS_S); -+ -+ ar7240sw_reg_write(as, AR7240_REG_PORT_CTRL(port), ctrl); -+ ar7240sw_reg_write(as, AR7240_REG_PORT_VLAN(port), vlan); -+} -+ -+static char *ar7240_dsa_probe(struct mii_bus *mii, int sw_addr) -+{ -+ struct ar7240sw as; -+ u32 ctrl; -+ u16 phy_id1; -+ u16 phy_id2; -+ u8 ver; -+ -+ ar7240sw_init(&as, mii); -+ -+ ctrl = ar7240sw_reg_read(&as, AR7240_REG_MASK_CTRL); -+ -+ ver = (ctrl >> AR7240_MASK_CTRL_VERSION_S) & AR7240_MASK_CTRL_VERSION_M; -+ if (ver != 1) { -+ pr_err("ar7240_dsa: unsupported chip, ctrl=%08x\n", ctrl); -+ return NULL; -+ } -+ -+ phy_id1 = ar7240sw_phy_read(&as, 0, MII_PHYSID1); -+ phy_id2 = ar7240sw_phy_read(&as, 0, MII_PHYSID2); -+ if (phy_id1 != AR7240_PHY_ID1 || phy_id2 != AR7240_PHY_ID2) { -+ pr_err("ar7240_dsa: unknown phy id '%04x:%04x'\n", -+ phy_id1, phy_id2); -+ return NULL; -+ } -+ -+ return "Atheros AR7240 built-in"; -+} -+ -+static int ar7240_dsa_setup(struct dsa_switch *ds) -+{ -+ struct ar7240sw *as = dsa_to_ar7240sw(ds); -+ int i; -+ int ret; -+ -+ ar7240sw_init(as, ds->master_mii_bus); -+ -+ ret = ar7240sw_reset(as); -+ if (ret) -+ return ret; -+ -+ ar7240sw_setup(as); -+ -+ for (i = 0; i < AR7240_NUM_PORTS; i++) { -+ if (dsa_is_cpu_port(ds, i) || (ds->phys_port_mask & (1 << i))) -+ ar7240sw_setup_port(as, i); -+ else -+ ar7240sw_disable_port(as, i); -+ } -+ -+ return 0; -+} -+ -+static int ar7240_dsa_set_addr(struct dsa_switch *ds, u8 *addr) -+{ -+ struct ar7240sw *as = dsa_to_ar7240sw(ds); -+ u32 t; -+ -+ t = (addr[4] << 8) | addr[5]; -+ ar7240sw_reg_write(as, AR7240_REG_MAC_ADDR0, t); -+ -+ t = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]; -+ ar7240sw_reg_write(as, AR7240_REG_MAC_ADDR1, t); -+ -+ return 0; -+} -+ -+static int ar7240_iort_to_phy_addr(int port) -+{ -+ if (port > 0 && port < AR7240_NUM_PORTS) -+ return port - 1; -+ -+ return -EINVAL; -+} -+ -+static int ar7240_dsa_phy_read(struct dsa_switch *ds, int port, int regnum) -+{ -+ struct ar7240sw *as = dsa_to_ar7240sw(ds); -+ int phy_addr; -+ -+ phy_addr = ar7240_iort_to_phy_addr(port); -+ if (phy_addr < 0) -+ return 0xffff; -+ -+ return ar7240sw_phy_read(as, phy_addr, regnum); -+} -+ -+static int ar7240_dsa_phy_write(struct dsa_switch *ds, int port, int regnum, -+ u16 val) -+{ -+ struct ar7240sw *as = dsa_to_ar7240sw(ds); -+ int phy_addr; -+ -+ phy_addr = ar7240_iort_to_phy_addr(port); -+ if (phy_addr < 0) -+ return 0xffff; -+ -+ return ar7240sw_phy_write(as, phy_addr, regnum, val); -+} -+ -+static const char *ar7240sw_speed_str(unsigned speed) -+{ -+ switch (speed) { -+ case AR7240_PORT_STATUS_SPEED_10: -+ return "10"; -+ case AR7240_PORT_STATUS_SPEED_100: -+ return "100"; -+ case AR7240_PORT_STATUS_SPEED_1000: -+ return "1000"; -+ } -+ -+ return "????"; -+} -+ -+static void ar7240_dsa_poll_link(struct dsa_switch *ds) -+{ -+ struct ar7240sw *as = dsa_to_ar7240sw(ds); -+ int i; -+ -+ for (i = 0; i < DSA_MAX_PORTS; i++) { -+ struct net_device *dev; -+ u32 status; -+ int link; -+ unsigned speed; -+ int duplex; -+ -+ dev = ds->ports[i]; -+ if (dev == NULL) -+ continue; -+ -+ link = 0; -+ if (dev->flags & IFF_UP) { -+ status = ar7240sw_reg_read(as, -+ AR7240_REG_PORT_STATUS(i)); -+ link = !!(status & AR7240_PORT_STATUS_LINK_UP); -+ } -+ -+ if (!link) { -+ if (netif_carrier_ok(dev)) { -+ pr_info("%s: link down\n", dev->name); -+ netif_carrier_off(dev); -+ } -+ continue; -+ } -+ -+ speed = (status & AR7240_PORT_STATUS_SPEED_M); -+ duplex = (status & AR7240_PORT_STATUS_DUPLEX) ? 1 : 0; -+ if (!netif_carrier_ok(dev)) { -+ pr_info("%s: link up, %sMb/s, %s duplex", -+ dev->name, -+ ar7240sw_speed_str(speed), -+ duplex ? "full" : "half"); -+ netif_carrier_on(dev); -+ } -+ } -+} -+ -+static const struct ar7240sw_hw_stat ar7240_hw_stats[] = { -+ { "rx_broadcast" , 4, AR7240_STATS_RXBROAD, }, -+ { "rx_pause" , 4, AR7240_STATS_RXPAUSE, }, -+ { "rx_multicast" , 4, AR7240_STATS_RXMULTI, }, -+ { "rx_fcs_error" , 4, AR7240_STATS_RXFCSERR, }, -+ { "rx_align_error" , 4, AR7240_STATS_RXALIGNERR, }, -+ { "rx_undersize" , 4, AR7240_STATS_RXRUNT, }, -+ { "rx_fragments" , 4, AR7240_STATS_RXFRAGMENT, }, -+ { "rx_64bytes" , 4, AR7240_STATS_RX64BYTE, }, -+ { "rx_65_127bytes" , 4, AR7240_STATS_RX128BYTE, }, -+ { "rx_128_255bytes" , 4, AR7240_STATS_RX256BYTE, }, -+ { "rx_256_511bytes" , 4, AR7240_STATS_RX512BYTE, }, -+ { "rx_512_1023bytes" , 4, AR7240_STATS_RX1024BYTE, }, -+ { "rx_1024_1518bytes" , 4, AR7240_STATS_RX1518BYTE, }, -+ { "rx_1519_max_bytes" , 4, AR7240_STATS_RXMAXBYTE, }, -+ { "rx_oversize" , 4, AR7240_STATS_RXTOOLONG, }, -+ { "rx_good_bytes" , 8, AR7240_STATS_RXGOODBYTE, }, -+ { "rx_bad_bytes" , 8, AR7240_STATS_RXBADBYTE, }, -+ { "rx_overflow" , 4, AR7240_STATS_RXOVERFLOW, }, -+ { "filtered" , 4, AR7240_STATS_FILTERED, }, -+ { "tx_broadcast" , 4, AR7240_STATS_TXBROAD, }, -+ { "tx_pause" , 4, AR7240_STATS_TXPAUSE, }, -+ { "tx_multicast" , 4, AR7240_STATS_TXMULTI, }, -+ { "tx_underrun" , 4, AR7240_STATS_TXUNDERRUN, }, -+ { "tx_64bytes" , 4, AR7240_STATS_TX64BYTE, }, -+ { "tx_65_127bytes" , 4, AR7240_STATS_TX128BYTE, }, -+ { "tx_128_255bytes" , 4, AR7240_STATS_TX256BYTE, }, -+ { "tx_256_511bytes" , 4, AR7240_STATS_TX512BYTE, }, -+ { "tx_512_1023bytes" , 4, AR7240_STATS_TX1024BYTE, }, -+ { "tx_1024_1518bytes" , 4, AR7240_STATS_TX1518BYTE, }, -+ { "tx_1519_max_bytes" , 4, AR7240_STATS_TXMAXBYTE, }, -+ { "tx_oversize" , 4, AR7240_STATS_TXOVERSIZE, }, -+ { "tx_bytes" , 8, AR7240_STATS_TXBYTE, }, -+ { "tx_collisions" , 4, AR7240_STATS_TXCOLLISION, }, -+ { "tx_abort_collisions" , 4, AR7240_STATS_TXABORTCOL, }, -+ { "tx_multi_collisions" , 4, AR7240_STATS_TXMULTICOL, }, -+ { "tx_single_collisions", 4, AR7240_STATS_TXSINGLECOL, }, -+ { "tx_excessive_deferred", 4, AR7240_STATS_TXEXCDEFER, }, -+ { "tx_deferred" , 4, AR7240_STATS_TXDEFER, }, -+ { "tx_late_collisions" , 4, AR7240_STATS_TXLATECOL, }, -+}; -+ -+static void ar7240_dsa_get_strings(struct dsa_switch *ds, int port, -+ uint8_t *data) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(ar7240_hw_stats); i++) { -+ memcpy(data + i * ETH_GSTRING_LEN, -+ ar7240_hw_stats[i].string, ETH_GSTRING_LEN); -+ } -+} -+ -+static void ar7240_dsa_get_ethtool_stats(struct dsa_switch *ds, int port, -+ uint64_t *data) -+{ -+ struct ar7240sw *as = dsa_to_ar7240sw(ds); -+ int err; -+ int i; -+ -+ mutex_lock(&as->stats_mutex); -+ -+ err = ar7240sw_capture_stats(as); -+ if (err) -+ goto unlock; -+ -+ for (i = 0; i < ARRAY_SIZE(ar7240_hw_stats); i++) { -+ const struct ar7240sw_hw_stat *s = &ar7240_hw_stats[i]; -+ u32 reg = AR7240_REG_STATS_BASE(port); -+ u32 low; -+ u32 high; -+ -+ low = ar7240sw_reg_read(as, reg + s->reg); -+ if (s->sizeof_stat == 8) -+ high = ar7240sw_reg_read(as, reg + s->reg); -+ else -+ high = 0; -+ -+ data[i] = (((u64) high) << 32) | low; -+ } -+ -+ unlock: -+ mutex_unlock(&as->stats_mutex); -+} -+ -+static int ar7240_dsa_get_sset_count(struct dsa_switch *ds) -+{ -+ return ARRAY_SIZE(ar7240_hw_stats); -+} -+ -+static struct dsa_switch_driver ar7240_dsa_driver = { -+ .tag_protocol = htons(ETH_P_QINQ), -+ .priv_size = sizeof(struct ar7240sw), -+ .probe = ar7240_dsa_probe, -+ .setup = ar7240_dsa_setup, -+ .set_addr = ar7240_dsa_set_addr, -+ .phy_read = ar7240_dsa_phy_read, -+ .phy_write = ar7240_dsa_phy_write, -+ .poll_link = ar7240_dsa_poll_link, -+ .get_strings = ar7240_dsa_get_strings, -+ .get_ethtool_stats = ar7240_dsa_get_ethtool_stats, -+ .get_sset_count = ar7240_dsa_get_sset_count, -+}; -+ -+int __init dsa_ar7240_init(void) -+{ -+ register_switch_driver(&ar7240_dsa_driver); -+ return 0; -+} -+module_init(dsa_ar7240_init); -+ -+void __exit dsa_ar7240_cleanup(void) -+{ -+ unregister_switch_driver(&ar7240_dsa_driver); -+} -+module_exit(dsa_ar7240_cleanup); -diff -Nur linux-2.6.37.orig/net/dsa/mv88e6063.c linux-2.6.37/net/dsa/mv88e6063.c ---- linux-2.6.37.orig/net/dsa/mv88e6063.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/net/dsa/mv88e6063.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,294 @@ -+/* -+ * net/dsa/mv88e6063.c - Driver for Marvell 88e6063 switch chips -+ * Copyright (c) 2009 Gabor Juhos -+ * -+ * This driver was base on: net/dsa/mv88e6060.c -+ * net/dsa/mv88e6063.c - Driver for Marvell 88e6060 switch chips -+ * Copyright (c) 2008-2009 Marvell Semiconductor -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ */ -+ -+#include -+#include -+#include -+#include "dsa_priv.h" -+ -+#define REG_BASE 0x10 -+#define REG_PHY(p) (REG_BASE + (p)) -+#define REG_PORT(p) (REG_BASE + 8 + (p)) -+#define REG_GLOBAL (REG_BASE + 0x0f) -+#define NUM_PORTS 7 -+ -+static int reg_read(struct dsa_switch *ds, int addr, int reg) -+{ -+ return mdiobus_read(ds->master_mii_bus, addr, reg); -+} -+ -+#define REG_READ(addr, reg) \ -+ ({ \ -+ int __ret; \ -+ \ -+ __ret = reg_read(ds, addr, reg); \ -+ if (__ret < 0) \ -+ return __ret; \ -+ __ret; \ -+ }) -+ -+ -+static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val) -+{ -+ return mdiobus_write(ds->master_mii_bus, addr, reg, val); -+} -+ -+#define REG_WRITE(addr, reg, val) \ -+ ({ \ -+ int __ret; \ -+ \ -+ __ret = reg_write(ds, addr, reg, val); \ -+ if (__ret < 0) \ -+ return __ret; \ -+ }) -+ -+static char *mv88e6063_probe(struct mii_bus *bus, int sw_addr) -+{ -+ int ret; -+ -+ ret = mdiobus_read(bus, REG_PORT(0), 0x03); -+ if (ret >= 0) { -+ ret &= 0xfff0; -+ if (ret == 0x1530) -+ return "Marvell 88E6063"; -+ } -+ -+ return NULL; -+} -+ -+static int mv88e6063_switch_reset(struct dsa_switch *ds) -+{ -+ int i; -+ int ret; -+ -+ /* -+ * Set all ports to the disabled state. -+ */ -+ for (i = 0; i < NUM_PORTS; i++) { -+ ret = REG_READ(REG_PORT(i), 0x04); -+ REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc); -+ } -+ -+ /* -+ * Wait for transmit queues to drain. -+ */ -+ msleep(2); -+ -+ /* -+ * Reset the switch. -+ */ -+ REG_WRITE(REG_GLOBAL, 0x0a, 0xa130); -+ -+ /* -+ * Wait up to one second for reset to complete. -+ */ -+ for (i = 0; i < 1000; i++) { -+ ret = REG_READ(REG_GLOBAL, 0x00); -+ if ((ret & 0x8000) == 0x0000) -+ break; -+ -+ msleep(1); -+ } -+ if (i == 1000) -+ return -ETIMEDOUT; -+ -+ return 0; -+} -+ -+static int mv88e6063_setup_global(struct dsa_switch *ds) -+{ -+ /* -+ * Disable discarding of frames with excessive collisions, -+ * set the maximum frame size to 1536 bytes, and mask all -+ * interrupt sources. -+ */ -+ REG_WRITE(REG_GLOBAL, 0x04, 0x0800); -+ -+ /* -+ * Enable automatic address learning, set the address -+ * database size to 1024 entries, and set the default aging -+ * time to 5 minutes. -+ */ -+ REG_WRITE(REG_GLOBAL, 0x0a, 0x2130); -+ -+ return 0; -+} -+ -+static int mv88e6063_setup_port(struct dsa_switch *ds, int p) -+{ -+ int addr = REG_PORT(p); -+ -+ /* -+ * Do not force flow control, disable Ingress and Egress -+ * Header tagging, disable VLAN tunneling, and set the port -+ * state to Forwarding. Additionally, if this is the CPU -+ * port, enable Ingress and Egress Trailer tagging mode. -+ */ -+ REG_WRITE(addr, 0x04, dsa_is_cpu_port(ds, p) ? 0x4103 : 0x0003); -+ -+ /* -+ * Port based VLAN map: give each port its own address -+ * database, allow the CPU port to talk to each of the 'real' -+ * ports, and allow each of the 'real' ports to only talk to -+ * the CPU port. -+ */ -+ REG_WRITE(addr, 0x06, -+ ((p & 0xf) << 12) | -+ (dsa_is_cpu_port(ds, p) ? -+ ds->phys_port_mask : -+ (1 << ds->dst->cpu_port))); -+ -+ /* -+ * Port Association Vector: when learning source addresses -+ * of packets, add the address to the address database using -+ * a port bitmap that has only the bit for this port set and -+ * the other bits clear. -+ */ -+ REG_WRITE(addr, 0x0b, 1 << p); -+ -+ return 0; -+} -+ -+static int mv88e6063_setup(struct dsa_switch *ds) -+{ -+ int i; -+ int ret; -+ -+ ret = mv88e6063_switch_reset(ds); -+ if (ret < 0) -+ return ret; -+ -+ /* @@@ initialise atu */ -+ -+ ret = mv88e6063_setup_global(ds); -+ if (ret < 0) -+ return ret; -+ -+ for (i = 0; i < NUM_PORTS; i++) { -+ ret = mv88e6063_setup_port(ds, i); -+ if (ret < 0) -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static int mv88e6063_set_addr(struct dsa_switch *ds, u8 *addr) -+{ -+ REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) | addr[1]); -+ REG_WRITE(REG_GLOBAL, 0x02, (addr[2] << 8) | addr[3]); -+ REG_WRITE(REG_GLOBAL, 0x03, (addr[4] << 8) | addr[5]); -+ -+ return 0; -+} -+ -+static int mv88e6063_port_to_phy_addr(int port) -+{ -+ if (port >= 0 && port <= NUM_PORTS) -+ return REG_PHY(port); -+ return -1; -+} -+ -+static int mv88e6063_phy_read(struct dsa_switch *ds, int port, int regnum) -+{ -+ int addr; -+ -+ addr = mv88e6063_port_to_phy_addr(port); -+ if (addr == -1) -+ return 0xffff; -+ -+ return reg_read(ds, addr, regnum); -+} -+ -+static int -+mv88e6063_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val) -+{ -+ int addr; -+ -+ addr = mv88e6063_port_to_phy_addr(port); -+ if (addr == -1) -+ return 0xffff; -+ -+ return reg_write(ds, addr, regnum, val); -+} -+ -+static void mv88e6063_poll_link(struct dsa_switch *ds) -+{ -+ int i; -+ -+ for (i = 0; i < DSA_MAX_PORTS; i++) { -+ struct net_device *dev; -+ int uninitialized_var(port_status); -+ int link; -+ int speed; -+ int duplex; -+ int fc; -+ -+ dev = ds->ports[i]; -+ if (dev == NULL) -+ continue; -+ -+ link = 0; -+ if (dev->flags & IFF_UP) { -+ port_status = reg_read(ds, REG_PORT(i), 0x00); -+ if (port_status < 0) -+ continue; -+ -+ link = !!(port_status & 0x1000); -+ } -+ -+ if (!link) { -+ if (netif_carrier_ok(dev)) { -+ printk(KERN_INFO "%s: link down\n", dev->name); -+ netif_carrier_off(dev); -+ } -+ continue; -+ } -+ -+ speed = (port_status & 0x0100) ? 100 : 10; -+ duplex = (port_status & 0x0200) ? 1 : 0; -+ fc = ((port_status & 0xc000) == 0xc000) ? 1 : 0; -+ -+ if (!netif_carrier_ok(dev)) { -+ printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, " -+ "flow control %sabled\n", dev->name, -+ speed, duplex ? "full" : "half", -+ fc ? "en" : "dis"); -+ netif_carrier_on(dev); -+ } -+ } -+} -+ -+static struct dsa_switch_driver mv88e6063_switch_driver = { -+ .tag_protocol = htons(ETH_P_TRAILER), -+ .probe = mv88e6063_probe, -+ .setup = mv88e6063_setup, -+ .set_addr = mv88e6063_set_addr, -+ .phy_read = mv88e6063_phy_read, -+ .phy_write = mv88e6063_phy_write, -+ .poll_link = mv88e6063_poll_link, -+}; -+ -+static int __init mv88e6063_init(void) -+{ -+ register_switch_driver(&mv88e6063_switch_driver); -+ return 0; -+} -+module_init(mv88e6063_init); -+ -+static void __exit mv88e6063_cleanup(void) -+{ -+ unregister_switch_driver(&mv88e6063_switch_driver); -+} -+module_exit(mv88e6063_cleanup); -diff -Nur linux-2.6.37.orig/net/dsa/tag_qinq.c linux-2.6.37/net/dsa/tag_qinq.c ---- linux-2.6.37.orig/net/dsa/tag_qinq.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/net/dsa/tag_qinq.c 2011-01-11 20:25:48.000000000 +0100 -@@ -0,0 +1,127 @@ -+/* -+ * net/dsa/tag_qinq.c - QinQ tag format handling -+ * Copyright (c) 2010 Gabor Juhos -+ * -+ * This file was based on: -+ * net/dsa/tag_edsa.c - Ethertype DSA tagging -+ * Copyright (c) 2008-2009 Marvell Semiconductor -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include "dsa_priv.h" -+ -+netdev_tx_t qinq_xmit(struct sk_buff *skb, struct net_device *dev) -+{ -+ struct dsa_slave_priv *p = netdev_priv(dev); -+ struct vlan_ethhdr *veth; -+ unsigned int len; -+ int ret; -+ -+ if (skb_cow_head(skb, VLAN_HLEN) < 0) -+ goto out_free_skb; -+ -+ veth = (struct vlan_ethhdr *)skb_push(skb, VLAN_HLEN); -+ -+ /* Move the mac addresses to the beginning of the new header. */ -+ memmove(skb->data, skb->data + VLAN_HLEN, 2 * VLAN_ETH_ALEN); -+ skb->mac_header -= VLAN_HLEN; -+ -+ /* setup VLAN header fields */ -+ veth->h_vlan_proto = htons(ETH_P_QINQ); -+ veth->h_vlan_TCI = htons(p->port); -+ -+ len = skb->len; -+ skb->protocol = htons(ETH_P_QINQ); -+ skb->dev = p->parent->dst->master_netdev; -+ -+ ret = dev_queue_xmit(skb); -+ if (unlikely(ret != NET_XMIT_SUCCESS)) -+ goto out_dropped; -+ -+ dev->stats.tx_packets++; -+ dev->stats.tx_bytes += len; -+ -+ return NETDEV_TX_OK; -+ -+ out_free_skb: -+ kfree_skb(skb); -+ out_dropped: -+ dev->stats.tx_dropped++; -+ return NETDEV_TX_OK; -+} -+ -+static int qinq_rcv(struct sk_buff *skb, struct net_device *dev, -+ struct packet_type *pt, struct net_device *orig_dev) -+{ -+ struct dsa_switch_tree *dst; -+ struct dsa_switch *ds; -+ struct vlan_hdr *vhdr; -+ int source_port; -+ -+ dst = dev->dsa_ptr; -+ if (unlikely(dst == NULL)) -+ goto out_drop; -+ ds = dst->ds[0]; -+ -+ skb = skb_unshare(skb, GFP_ATOMIC); -+ if (skb == NULL) -+ goto out; -+ -+ if (unlikely(!pskb_may_pull(skb, VLAN_HLEN))) -+ goto out_drop; -+ -+ vhdr = (struct vlan_hdr *)skb->data; -+ source_port = ntohs(vhdr->h_vlan_TCI) & VLAN_VID_MASK; -+ if (source_port >= DSA_MAX_PORTS || ds->ports[source_port] == NULL) -+ goto out_drop; -+ -+ /* Remove the outermost VLAN tag and update checksum. */ -+ skb_pull_rcsum(skb, VLAN_HLEN); -+ memmove(skb->data - ETH_HLEN, -+ skb->data - ETH_HLEN - VLAN_HLEN, -+ 2 * ETH_ALEN); -+ -+ skb->dev = ds->ports[source_port]; -+ skb_push(skb, ETH_HLEN); -+ skb->pkt_type = PACKET_HOST; -+ skb->protocol = eth_type_trans(skb, skb->dev); -+ -+ skb->dev->stats.rx_packets++; -+ skb->dev->stats.rx_bytes += skb->len; -+ -+ netif_receive_skb(skb); -+ -+ return 0; -+ -+ out_drop: -+ kfree_skb(skb); -+ out: -+ return 0; -+} -+ -+static struct packet_type qinq_packet_type __read_mostly = { -+ .type = cpu_to_be16(ETH_P_QINQ), -+ .func = qinq_rcv, -+}; -+ -+static int __init qinq_init_module(void) -+{ -+ dev_add_pack(&qinq_packet_type); -+ return 0; -+} -+module_init(qinq_init_module); -+ -+static void __exit qinq_cleanup_module(void) -+{ -+ dev_remove_pack(&qinq_packet_type); -+} -+module_exit(qinq_cleanup_module); diff --git a/target/linux/patches/2.6.37/atheros.patch b/target/linux/patches/2.6.37/atheros.patch deleted file mode 100644 index d67bf0824..000000000 --- a/target/linux/patches/2.6.37/atheros.patch +++ /dev/null @@ -1,6332 +0,0 @@ -diff -Nur linux-2.6.37.orig/arch/mips/Kbuild.platforms linux-2.6.37/arch/mips/Kbuild.platforms ---- linux-2.6.37.orig/arch/mips/Kbuild.platforms 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/mips/Kbuild.platforms 2011-05-15 19:24:57.000000000 +0200 -@@ -5,6 +5,7 @@ - platforms += bcm47xx - platforms += bcm63xx - platforms += cavium-octeon -+platforms += ar231x - platforms += cobalt - platforms += dec - platforms += emma -diff -Nur linux-2.6.37.orig/arch/mips/Kconfig linux-2.6.37/arch/mips/Kconfig ---- linux-2.6.37.orig/arch/mips/Kconfig 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/mips/Kconfig 2011-05-15 19:24:57.000000000 +0200 -@@ -102,6 +102,20 @@ - help - Support for BCM63XX based boards - -+config ATHEROS_AR231X -+ bool "Atheros 231x/531x SoC support" -+ select CEVT_R4K -+ select CSRC_R4K -+ select DMA_NONCOHERENT -+ select IRQ_CPU -+ select SYS_HAS_CPU_MIPS32_R1 -+ select SYS_SUPPORTS_BIG_ENDIAN -+ select SYS_SUPPORTS_32BIT_KERNEL -+ select GENERIC_GPIO -+ select SYS_HAS_EARLY_PRINTK -+ help -+ Support for AR231x and AR531x based boards -+ - config MIPS_COBALT - bool "Cobalt Server" - select CEVT_R4K -@@ -716,6 +730,7 @@ - - endchoice - -+source "arch/mips/ar231x/Kconfig" - source "arch/mips/alchemy/Kconfig" - source "arch/mips/bcm63xx/Kconfig" - source "arch/mips/jazz/Kconfig" -diff -Nur linux-2.6.37.orig/arch/mips/ar231x/Kconfig linux-2.6.37/arch/mips/ar231x/Kconfig ---- linux-2.6.37.orig/arch/mips/ar231x/Kconfig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar231x/Kconfig 2011-05-15 19:25:40.000000000 +0200 -@@ -0,0 +1,27 @@ -+config ATHEROS_AR5312 -+ bool "Atheros 5312/2312+ support" -+ depends on ATHEROS_AR231X -+ default y -+ -+config ATHEROS_AR2315 -+ bool "Atheros 2315+ support" -+ depends on ATHEROS_AR231X -+ select DMA_NONCOHERENT -+ select CEVT_R4K -+ select CSRC_R4K -+ select IRQ_CPU -+ select SYS_HAS_CPU_MIPS32_R1 -+ select SYS_SUPPORTS_32BIT_KERNEL -+ select SYS_SUPPORTS_BIG_ENDIAN -+ select GENERIC_GPIO -+ default y -+ -+config ATHEROS_AR2315_PCI -+ bool "PCI support" -+ depends on ATHEROS_AR2315 -+ select HW_HAS_PCI -+ select PCI -+ select USB_ARCH_HAS_HCD -+ select USB_ARCH_HAS_OHCI -+ select USB_ARCH_HAS_EHCI -+ default n -diff -Nur linux-2.6.37.orig/arch/mips/ar231x/Makefile linux-2.6.37/arch/mips/ar231x/Makefile ---- linux-2.6.37.orig/arch/mips/ar231x/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar231x/Makefile 2011-05-15 19:24:57.000000000 +0200 -@@ -0,0 +1,17 @@ -+# -+# This file is subject to the terms and conditions of the GNU General Public -+# License. See the file "COPYING" in the main directory of this archive -+# for more details. -+# -+# Copyright (C) 2006 FON Technology, SL. -+# Copyright (C) 2006 Imre Kaloz -+# Copyright (C) 2006-2009 Felix Fietkau -+# -+ -+obj-y += board.o prom.o devices.o -+ -+obj-$(CONFIG_EARLY_PRINTK) += early_printk.o -+ -+obj-$(CONFIG_ATHEROS_AR5312) += ar5312.o -+obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o -+obj-$(CONFIG_ATHEROS_AR2315_PCI) += pci.o -diff -Nur linux-2.6.37.orig/arch/mips/ar231x/Platform linux-2.6.37/arch/mips/ar231x/Platform ---- linux-2.6.37.orig/arch/mips/ar231x/Platform 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar231x/Platform 2011-05-15 19:24:57.000000000 +0200 -@@ -0,0 +1,6 @@ -+# -+# Atheros AR5312/AR2312 WiSoC -+# -+platform-$(CONFIG_ATHEROS_AR231X) += ar231x/ -+cflags-$(CONFIG_ATHEROS_AR231X) += -I$(srctree)/arch/mips/include/asm/mach-ar231x -+load-$(CONFIG_ATHEROS_AR231X) += 0xffffffff80041000 -diff -Nur linux-2.6.37.orig/arch/mips/ar231x/ar2315.c linux-2.6.37/arch/mips/ar231x/ar2315.c ---- linux-2.6.37.orig/arch/mips/ar231x/ar2315.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar231x/ar2315.c 2011-05-15 19:24:57.000000000 +0200 -@@ -0,0 +1,683 @@ -+/* -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. -+ * Copyright (C) 2006 FON Technology, SL. -+ * Copyright (C) 2006 Imre Kaloz -+ * Copyright (C) 2006 Felix Fietkau -+ */ -+ -+/* -+ * Platform devices for Atheros SoCs -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include "devices.h" -+#include "ar2315.h" -+ -+static u32 gpiointmask = 0, gpiointval = 0; -+ -+static inline void ar2315_gpio_irq(void) -+{ -+ u32 pend; -+ int bit = -1; -+ -+ /* only do one gpio interrupt at a time */ -+ pend = (ar231x_read_reg(AR2315_GPIO_DI) ^ gpiointval) & gpiointmask; -+ -+ if (pend) { -+ bit = fls(pend) - 1; -+ pend &= ~(1 << bit); -+ gpiointval ^= (1 << bit); -+ } -+ -+ if (!pend) -+ ar231x_write_reg(AR2315_ISR, AR2315_ISR_GPIO); -+ -+ /* Enable interrupt with edge detection */ -+ if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(bit)) != AR2315_GPIO_CR_I(bit)) -+ return; -+ -+ if (bit >= 0) -+ do_IRQ(AR531X_GPIO_IRQ_BASE + bit); -+} -+ -+#ifdef CONFIG_ATHEROS_AR2315_PCI -+static inline void pci_abort_irq(void) -+{ -+ ar231x_write_reg(AR2315_PCI_INT_STATUS, AR2315_PCI_ABORT_INT); -+} -+ -+static inline void pci_ack_irq(void) -+{ -+ ar231x_write_reg(AR2315_PCI_INT_STATUS, AR2315_PCI_EXT_INT); -+} -+ -+void ar2315_pci_irq(int irq) -+{ -+ if (ar231x_read_reg(AR2315_PCI_INT_STATUS) == AR2315_PCI_ABORT_INT) -+ pci_abort_irq(); -+ else { -+ do_IRQ(irq); -+ pci_ack_irq(); -+ } -+} -+#endif /* CONFIG_ATHEROS_AR2315_PCI */ -+ -+/* -+ * Called when an interrupt is received, this function -+ * determines exactly which interrupt it was, and it -+ * invokes the appropriate handler. -+ * -+ * Implicitly, we also define interrupt priority by -+ * choosing which to dispatch first. -+ */ -+static asmlinkage void -+ar2315_irq_dispatch(void) -+{ -+ int pending = read_c0_status() & read_c0_cause(); -+ -+ if (pending & CAUSEF_IP3) -+ do_IRQ(AR2315_IRQ_WLAN0_INTRS); -+ else if (pending & CAUSEF_IP4) -+ do_IRQ(AR2315_IRQ_ENET0_INTRS); -+#ifdef CONFIG_ATHEROS_AR2315_PCI -+ else if (pending & CAUSEF_IP5) -+ ar2315_pci_irq(AR2315_IRQ_LCBUS_PCI); -+#endif -+ else if (pending & CAUSEF_IP2) { -+ unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) & ar231x_read_reg(AR2315_IMR); -+ -+ if (misc_intr & AR2315_ISR_SPI) -+ do_IRQ(AR531X_MISC_IRQ_SPI); -+ else if (misc_intr & AR2315_ISR_TIMER) -+ do_IRQ(AR531X_MISC_IRQ_TIMER); -+ else if (misc_intr & AR2315_ISR_AHB) -+ do_IRQ(AR531X_MISC_IRQ_AHB_PROC); -+ else if (misc_intr & AR2315_ISR_GPIO) -+ ar2315_gpio_irq(); -+ else if (misc_intr & AR2315_ISR_UART0) -+ do_IRQ(AR531X_MISC_IRQ_UART0); -+ else if (misc_intr & AR2315_ISR_WD) -+ do_IRQ(AR531X_MISC_IRQ_WATCHDOG); -+ else -+ do_IRQ(AR531X_MISC_IRQ_NONE); -+ } else if (pending & CAUSEF_IP7) -+ do_IRQ(AR531X_IRQ_CPU_CLOCK); -+} -+ -+static void ar2315_set_gpiointmask(int gpio, int level) -+{ -+ u32 reg; -+ -+ reg = ar231x_read_reg(AR2315_GPIO_INT); -+ reg &= ~(AR2315_GPIO_INT_M | AR2315_GPIO_INT_LVL_M); -+ reg |= gpio | AR2315_GPIO_INT_LVL(level); -+ ar231x_write_reg(AR2315_GPIO_INT, reg); -+} -+ -+static void ar2315_gpio_intr_enable(unsigned int irq) -+{ -+ unsigned int gpio = irq - AR531X_GPIO_IRQ_BASE; -+ -+ /* Enable interrupt with edge detection */ -+ if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(gpio)) != AR2315_GPIO_CR_I(gpio)) -+ return; -+ -+ gpiointmask |= (1 << gpio); -+ ar2315_set_gpiointmask(gpio, 3); -+} -+ -+static unsigned int ar2315_gpio_intr_startup(unsigned int irq) -+{ -+ unsigned int gpio = irq - AR531X_GPIO_IRQ_BASE; -+ -+ /* reconfigure GPIO line as input */ -+ ar231x_mask_reg(AR2315_GPIO_CR, AR2315_GPIO_CR_M(gpio), AR2315_GPIO_CR_I(gpio)); -+ ar2315_gpio_intr_enable(irq); -+ return 0; -+} -+ -+static void ar2315_gpio_intr_disable(unsigned int irq) -+{ -+ unsigned int gpio = irq - AR531X_GPIO_IRQ_BASE; -+ -+ /* Disable interrupt */ -+ gpiointmask &= ~(1 << gpio); -+ ar2315_set_gpiointmask(gpio, 0); -+} -+ -+static void -+ar2315_gpio_intr_end(unsigned int irq) -+{ -+ if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) -+ ar2315_gpio_intr_enable(irq); -+} -+ -+static struct irq_chip ar2315_gpio_intr_controller = { -+ .name = "AR2315-GPIO", -+ .startup = ar2315_gpio_intr_startup, -+ .ack = ar2315_gpio_intr_disable, -+ .mask_ack = ar2315_gpio_intr_disable, -+ .mask = ar2315_gpio_intr_disable, -+ .unmask = ar2315_gpio_intr_enable, -+ .end = ar2315_gpio_intr_end, -+}; -+ -+static void -+ar2315_misc_intr_enable(unsigned int irq) -+{ -+ unsigned int imr; -+ -+ imr = ar231x_read_reg(AR2315_IMR); -+ switch(irq) { -+ case AR531X_MISC_IRQ_SPI: -+ imr |= AR2315_ISR_SPI; -+ break; -+ case AR531X_MISC_IRQ_TIMER: -+ imr |= AR2315_ISR_TIMER; -+ break; -+ case AR531X_MISC_IRQ_AHB_PROC: -+ imr |= AR2315_ISR_AHB; -+ break; -+ case AR531X_MISC_IRQ_GPIO: -+ imr |= AR2315_ISR_GPIO; -+ break; -+ case AR531X_MISC_IRQ_UART0: -+ imr |= AR2315_ISR_UART0; -+ break; -+ case AR531X_MISC_IRQ_WATCHDOG: -+ imr |= AR2315_ISR_WD; -+ break; -+ default: -+ break; -+ } -+ ar231x_write_reg(AR2315_IMR, imr); -+} -+ -+static void -+ar2315_misc_intr_disable(unsigned int irq) -+{ -+ unsigned int imr; -+ -+ imr = ar231x_read_reg(AR2315_IMR); -+ switch(irq) { -+ case AR531X_MISC_IRQ_SPI: -+ imr &= ~AR2315_ISR_SPI; -+ break; -+ case AR531X_MISC_IRQ_TIMER: -+ imr &= ~AR2315_ISR_TIMER; -+ break; -+ case AR531X_MISC_IRQ_AHB_PROC: -+ imr &= ~AR2315_ISR_AHB; -+ break; -+ case AR531X_MISC_IRQ_GPIO: -+ imr &= ~AR2315_ISR_GPIO; -+ break; -+ case AR531X_MISC_IRQ_UART0: -+ imr &= ~AR2315_ISR_UART0; -+ break; -+ case AR531X_MISC_IRQ_WATCHDOG: -+ imr &= ~AR2315_ISR_WD; -+ break; -+ default: -+ break; -+ } -+ ar231x_write_reg(AR2315_IMR, imr); -+} -+ -+static void -+ar2315_misc_intr_end(unsigned int irq) -+{ -+ if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) -+ ar2315_misc_intr_enable(irq); -+} -+ -+ -+static struct irq_chip ar2315_misc_intr_controller = { -+ .name = "AR2315-MISC", -+ .ack = ar2315_misc_intr_disable, -+ .mask_ack = ar2315_misc_intr_disable, -+ .mask = ar2315_misc_intr_disable, -+ .unmask = ar2315_misc_intr_enable, -+ .end = ar2315_misc_intr_end, -+}; -+ -+static irqreturn_t ar2315_ahb_proc_handler(int cpl, void *dev_id) -+{ -+ ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET); -+ ar231x_read_reg(AR2315_AHB_ERR1); -+ -+ printk(KERN_ERR "AHB fatal error\n"); -+ machine_restart("AHB error"); /* Catastrophic failure */ -+ -+ return IRQ_HANDLED; -+} -+ -+static struct irqaction ar2315_ahb_proc_interrupt = { -+ .handler = ar2315_ahb_proc_handler, -+ .flags = IRQF_DISABLED, -+ .name = "ar2315_ahb_proc_interrupt", -+}; -+ -+static struct irqaction cascade = { -+ .handler = no_action, -+ .flags = IRQF_DISABLED, -+ .name = "cascade", -+}; -+ -+void -+ar2315_irq_init(void) -+{ -+ int i; -+ -+ if (!is_2315()) -+ return; -+ -+ ar231x_irq_dispatch = ar2315_irq_dispatch; -+ gpiointval = ar231x_read_reg(AR2315_GPIO_DI); -+ for (i = 0; i < AR531X_MISC_IRQ_COUNT; i++) { -+ int irq = AR531X_MISC_IRQ_BASE + i; -+ set_irq_chip_and_handler(irq, &ar2315_misc_intr_controller, -+ handle_level_irq); -+ } -+ for (i = 0; i < AR531X_GPIO_IRQ_COUNT; i++) { -+ int irq = AR531X_GPIO_IRQ_BASE + i; -+ set_irq_chip_and_handler(irq, &ar2315_gpio_intr_controller, -+ handle_level_irq); -+ } -+ setup_irq(AR531X_MISC_IRQ_GPIO, &cascade); -+ setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar2315_ahb_proc_interrupt); -+ setup_irq(AR2315_IRQ_MISC_INTRS, &cascade); -+} -+ -+const struct ar231x_gpiodev ar2315_gpiodev; -+ -+static u32 -+ar2315_gpio_get_output(void) -+{ -+ u32 reg; -+ reg = ar231x_read_reg(AR2315_GPIO_CR); -+ reg &= ar2315_gpiodev.valid_mask; -+ return reg; -+} -+ -+static u32 -+ar2315_gpio_set_output(u32 mask, u32 val) -+{ -+ u32 reg; -+ -+ reg = ar231x_read_reg(AR2315_GPIO_CR); -+ reg &= ~mask; -+ reg |= val; -+ ar231x_write_reg(AR2315_GPIO_CR, reg); -+ return reg; -+} -+ -+static u32 -+ar2315_gpio_get(void) -+{ -+ u32 reg; -+ reg = ar231x_read_reg(AR2315_GPIO_DI); -+ reg &= ar2315_gpiodev.valid_mask; -+ return reg; -+} -+ -+static u32 -+ar2315_gpio_set(u32 mask, u32 value) -+{ -+ u32 reg; -+ reg = ar231x_read_reg(AR2315_GPIO_DO); -+ reg &= ~mask; -+ reg |= value; -+ ar231x_write_reg(AR2315_GPIO_DO, reg); -+ return reg; -+} -+ -+const struct ar231x_gpiodev ar2315_gpiodev = { -+ .valid_mask = (1 << 22) - 1, -+ .get_output = ar2315_gpio_get_output, -+ .set_output = ar2315_gpio_set_output, -+ .get = ar2315_gpio_get, -+ .set = ar2315_gpio_set, -+}; -+ -+static struct ar231x_eth ar2315_eth_data = { -+ .reset_base = AR2315_RESET, -+ .reset_mac = AR2315_RESET_ENET0, -+ .reset_phy = AR2315_RESET_EPHY0, -+ .phy_base = AR2315_ENET0, -+ .config = &ar231x_board, -+}; -+ -+static struct resource ar2315_spiflash_res[] = { -+ { -+ .name = "flash_base", -+ .flags = IORESOURCE_MEM, -+ .start = KSEG1ADDR(AR2315_SPI_READ), -+ .end = KSEG1ADDR(AR2315_SPI_READ) + 0x1000000 - 1, -+ }, -+ { -+ .name = "flash_regs", -+ .flags = IORESOURCE_MEM, -+ .start = 0x11300000, -+ .end = 0x11300012, -+ }, -+}; -+ -+static struct platform_device ar2315_spiflash = { -+ .id = 0, -+ .name = "spiflash", -+ .resource = ar2315_spiflash_res, -+ .num_resources = ARRAY_SIZE(ar2315_spiflash_res) -+}; -+ -+static struct platform_device ar2315_wdt = { -+ .id = 0, -+ .name = "ar2315_wdt", -+}; -+ -+#define SPI_FLASH_CTL 0x00 -+#define SPI_FLASH_OPCODE 0x04 -+#define SPI_FLASH_DATA 0x08 -+ -+static inline u32 -+spiflash_read_reg(int reg) -+{ -+ return ar231x_read_reg(KSEG1ADDR(AR2315_SPI) + reg); -+} -+ -+static inline void -+spiflash_write_reg(int reg, u32 data) -+{ -+ ar231x_write_reg(KSEG1ADDR(AR2315_SPI) + reg, data); -+} -+ -+static u32 -+spiflash_wait_status(void) -+{ -+ u32 reg; -+ -+ do { -+ reg = spiflash_read_reg(SPI_FLASH_CTL); -+ } while (reg & SPI_CTL_BUSY); -+ -+ return reg; -+} -+ -+static u8 -+spiflash_probe(void) -+{ -+ u32 reg; -+ -+ reg = spiflash_wait_status(); -+ reg &= ~SPI_CTL_TX_RX_CNT_MASK; -+ reg |= (1 << 4) | 4 | SPI_CTL_START; -+ -+ spiflash_write_reg(SPI_FLASH_OPCODE, 0xab); -+ spiflash_write_reg(SPI_FLASH_CTL, reg); -+ -+ reg = spiflash_wait_status(); -+ reg = spiflash_read_reg(SPI_FLASH_DATA); -+ reg &= 0xff; -+ -+ return (u8) reg; -+} -+ -+ -+#define STM_8MBIT_SIGNATURE 0x13 -+#define STM_16MBIT_SIGNATURE 0x14 -+#define STM_32MBIT_SIGNATURE 0x15 -+#define STM_64MBIT_SIGNATURE 0x16 -+#define STM_128MBIT_SIGNATURE 0x17 -+ -+static u8 __init * -+ar2315_flash_limit(void) -+{ -+ u32 flash_size = 0; -+ -+ /* probe the flash chip size */ -+ switch(spiflash_probe()) { -+ case STM_8MBIT_SIGNATURE: -+ flash_size = 0x00100000; -+ break; -+ case STM_16MBIT_SIGNATURE: -+ flash_size = 0x00200000; -+ break; -+ case STM_32MBIT_SIGNATURE: -+ flash_size = 0x00400000; -+ break; -+ case STM_64MBIT_SIGNATURE: -+ flash_size = 0x00800000; -+ break; -+ case STM_128MBIT_SIGNATURE: -+ flash_size = 0x01000000; -+ break; -+ } -+ -+ ar2315_spiflash_res[0].end = ar2315_spiflash_res[0].start + -+ flash_size - 1; -+ return (u8 *) ar2315_spiflash_res[0].end + 1; -+} -+ -+#ifdef CONFIG_LEDS_GPIO -+static struct gpio_led ar2315_leds[6]; -+static struct gpio_led_platform_data ar2315_led_data = { -+ .leds = (void *) ar2315_leds, -+}; -+ -+static struct platform_device ar2315_gpio_leds = { -+ .name = "leds-gpio", -+ .id = -1, -+ .dev = { -+ .platform_data = (void *) &ar2315_led_data, -+ } -+}; -+ -+static void __init -+ar2315_init_gpio(void) -+{ -+ static char led_names[6][6]; -+ int i, led = 0; -+ -+ ar2315_led_data.num_leds = 0; -+ for(i = 1; i < 8; i++) -+ { -+ if((i == AR2315_RESET_GPIO) || -+ (i == ar231x_board.config->resetConfigGpio)) -+ continue; -+ -+ if(i == ar231x_board.config->sysLedGpio) -+ strcpy(led_names[led], "wlan"); -+ else -+ sprintf(led_names[led], "gpio%d", i); -+ -+ ar2315_leds[led].name = led_names[led]; -+ ar2315_leds[led].gpio = i; -+ ar2315_leds[led].active_low = 0; -+ led++; -+ } -+ ar2315_led_data.num_leds = led; -+ platform_device_register(&ar2315_gpio_leds); -+} -+#else -+static inline void ar2315_init_gpio(void) -+{ -+} -+#endif -+ -+int __init -+ar2315_init_devices(void) -+{ -+ if (!is_2315()) -+ return 0; -+ -+ /* Find board configuration */ -+ ar231x_find_config(ar2315_flash_limit()); -+ ar2315_eth_data.macaddr = ar231x_board.config->enet0_mac; -+ -+ ar2315_init_gpio(); -+ platform_device_register(&ar2315_wdt); -+ platform_device_register(&ar2315_spiflash); -+ ar231x_add_ethernet(0, AR2315_ENET0, AR2315_IRQ_ENET0_INTRS, -+ &ar2315_eth_data); -+ ar231x_add_wmac(0, AR2315_WLAN0, AR2315_IRQ_WLAN0_INTRS); -+ -+ return 0; -+} -+ -+static void -+ar2315_restart(char *command) -+{ -+ void (*mips_reset_vec)(void) = (void *) 0xbfc00000; -+ -+ local_irq_disable(); -+ -+ /* try reset the system via reset control */ -+ ar231x_write_reg(AR2315_COLD_RESET,AR2317_RESET_SYSTEM); -+ -+ /* Cold reset does not work on the AR2315/6, use the GPIO reset bits a workaround. -+ * give it some time to attempt a gpio based hardware reset -+ * (atheros reference design workaround) */ -+ gpio_direction_output(AR2315_RESET_GPIO, 0); -+ mdelay(100); -+ -+ /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic -+ * workaround. Attempt to jump to the mips reset location - -+ * the boot loader itself might be able to recover the system */ -+ mips_reset_vec(); -+} -+ -+ -+/* -+ * This table is indexed by bits 5..4 of the CLOCKCTL1 register -+ * to determine the predevisor value. -+ */ -+static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = { 1, 2, 4, 5 }; -+static int __initdata PLLC_DIVIDE_TABLE[5] = { 2, 3, 4, 6, 3 }; -+ -+static unsigned int __init -+ar2315_sys_clk(unsigned int clockCtl) -+{ -+ unsigned int pllcCtrl,cpuDiv; -+ unsigned int pllcOut,refdiv,fdiv,divby2; -+ unsigned int clkDiv; -+ -+ pllcCtrl = ar231x_read_reg(AR2315_PLLC_CTL); -+ refdiv = (pllcCtrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S; -+ refdiv = CLOCKCTL1_PREDIVIDE_TABLE[refdiv]; -+ fdiv = (pllcCtrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S; -+ divby2 = (pllcCtrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S; -+ divby2 += 1; -+ pllcOut = (40000000/refdiv)*(2*divby2)*fdiv; -+ -+ -+ /* clkm input selected */ -+ switch(clockCtl & CPUCLK_CLK_SEL_M) { -+ case 0: -+ case 1: -+ clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKM_DIV_M) >> PLLC_CLKM_DIV_S]; -+ break; -+ case 2: -+ clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKC_DIV_M) >> PLLC_CLKC_DIV_S]; -+ break; -+ default: -+ pllcOut = 40000000; -+ clkDiv = 1; -+ break; -+ } -+ cpuDiv = (clockCtl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S; -+ cpuDiv = cpuDiv * 2 ?: 1; -+ return (pllcOut/(clkDiv * cpuDiv)); -+} -+ -+static inline unsigned int -+ar2315_cpu_frequency(void) -+{ -+ return ar2315_sys_clk(ar231x_read_reg(AR2315_CPUCLK)); -+} -+ -+static inline unsigned int -+ar2315_apb_frequency(void) -+{ -+ return ar2315_sys_clk(ar231x_read_reg(AR2315_AMBACLK)); -+} -+ -+void __init -+ar2315_time_init(void) -+{ -+ if (!is_2315()) -+ return; -+ -+ mips_hpt_frequency = ar2315_cpu_frequency() / 2; -+} -+ -+void __init -+ar2315_prom_init(void) -+{ -+ u32 memsize, memcfg, devid; -+ -+ if (!is_2315()) -+ return; -+ -+ memcfg = ar231x_read_reg(AR2315_MEM_CFG); -+ memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S); -+ memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S); -+ memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S); -+ memsize <<= 3; -+ add_memory_region(0, memsize, BOOT_MEM_RAM); -+ -+ /* Detect the hardware based on the device ID */ -+ devid = ar231x_read_reg(AR2315_SREV) & AR2315_REV_CHIP; -+ switch(devid) { -+ case 0x90: -+ case 0x91: -+ ar231x_devtype = DEV_TYPE_AR2317; -+ break; -+ default: -+ ar231x_devtype = DEV_TYPE_AR2315; -+ break; -+ } -+ ar231x_gpiodev = &ar2315_gpiodev; -+ ar231x_board.devid = devid; -+} -+ -+void __init -+ar2315_plat_setup(void) -+{ -+ u32 config; -+ -+ if (!is_2315()) -+ return; -+ -+ /* Clear any lingering AHB errors */ -+ config = read_c0_config(); -+ write_c0_config(config & ~0x3); -+ ar231x_write_reg(AR2315_AHB_ERR0,AHB_ERROR_DET); -+ ar231x_read_reg(AR2315_AHB_ERR1); -+ ar231x_write_reg(AR2315_WDC, AR2315_WDC_IGNORE_EXPIRATION); -+ -+ _machine_restart = ar2315_restart; -+ ar231x_serial_setup(KSEG1ADDR(AR2315_UART0), ar2315_apb_frequency()); -+} -diff -Nur linux-2.6.37.orig/arch/mips/ar231x/ar2315.h linux-2.6.37/arch/mips/ar231x/ar2315.h ---- linux-2.6.37.orig/arch/mips/ar231x/ar2315.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar231x/ar2315.h 2011-05-15 19:24:57.000000000 +0200 -@@ -0,0 +1,37 @@ -+#ifndef __AR2315_H -+#define __AR2315_H -+ -+#ifdef CONFIG_ATHEROS_AR2315 -+ -+extern void ar2315_irq_init(void); -+extern int ar2315_init_devices(void); -+extern void ar2315_prom_init(void); -+extern void ar2315_plat_setup(void); -+extern void ar2315_time_init(void); -+ -+#else -+ -+static inline void ar2315_irq_init(void) -+{ -+} -+ -+static inline int ar2315_init_devices(void) -+{ -+ return 0; -+} -+ -+static inline void ar2315_prom_init(void) -+{ -+} -+ -+static inline void ar2315_plat_setup(void) -+{ -+} -+ -+static inline void ar2315_time_init(void) -+{ -+} -+ -+#endif -+ -+#endif -diff -Nur linux-2.6.37.orig/arch/mips/ar231x/ar5312.c linux-2.6.37/arch/mips/ar231x/ar5312.c ---- linux-2.6.37.orig/arch/mips/ar231x/ar5312.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar231x/ar5312.c 2011-05-15 19:24:57.000000000 +0200 -@@ -0,0 +1,549 @@ -+/* -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. -+ * Copyright (C) 2006 FON Technology, SL. -+ * Copyright (C) 2006 Imre Kaloz -+ * Copyright (C) 2006-2009 Felix Fietkau -+ */ -+ -+/* -+ * Platform devices for Atheros SoCs -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include "devices.h" -+#include "ar5312.h" -+ -+static void -+ar5312_misc_irq_dispatch(void) -+{ -+ unsigned int ar231x_misc_intrs = ar231x_read_reg(AR531X_ISR) & ar231x_read_reg(AR531X_IMR); -+ -+ if (ar231x_misc_intrs & AR531X_ISR_TIMER) { -+ do_IRQ(AR531X_MISC_IRQ_TIMER); -+ (void)ar231x_read_reg(AR531X_TIMER); -+ } else if (ar231x_misc_intrs & AR531X_ISR_AHBPROC) -+ do_IRQ(AR531X_MISC_IRQ_AHB_PROC); -+ else if ((ar231x_misc_intrs & AR531X_ISR_UART0)) -+ do_IRQ(AR531X_MISC_IRQ_UART0); -+ else if (ar231x_misc_intrs & AR531X_ISR_WD) -+ do_IRQ(AR531X_MISC_IRQ_WATCHDOG); -+ else -+ do_IRQ(AR531X_MISC_IRQ_NONE); -+} -+ -+static asmlinkage void -+ar5312_irq_dispatch(void) -+{ -+ int pending = read_c0_status() & read_c0_cause(); -+ -+ if (pending & CAUSEF_IP2) -+ do_IRQ(AR5312_IRQ_WLAN0_INTRS); -+ else if (pending & CAUSEF_IP3) -+ do_IRQ(AR5312_IRQ_ENET0_INTRS); -+ else if (pending & CAUSEF_IP4) -+ do_IRQ(AR5312_IRQ_ENET1_INTRS); -+ else if (pending & CAUSEF_IP5) -+ do_IRQ(AR5312_IRQ_WLAN1_INTRS); -+ else if (pending & CAUSEF_IP6) -+ ar5312_misc_irq_dispatch(); -+ else if (pending & CAUSEF_IP7) -+ do_IRQ(AR531X_IRQ_CPU_CLOCK); -+} -+ -+ -+/* Enable the specified AR531X_MISC_IRQ interrupt */ -+static void -+ar5312_misc_intr_enable(unsigned int irq) -+{ -+ unsigned int imr; -+ -+ imr = ar231x_read_reg(AR531X_IMR); -+ imr |= (1 << (irq - AR531X_MISC_IRQ_BASE - 1)); -+ ar231x_write_reg(AR531X_IMR, imr); -+} -+ -+/* Disable the specified AR531X_MISC_IRQ interrupt */ -+static void -+ar5312_misc_intr_disable(unsigned int irq) -+{ -+ unsigned int imr; -+ -+ imr = ar231x_read_reg(AR531X_IMR); -+ imr &= ~(1 << (irq - AR531X_MISC_IRQ_BASE - 1)); -+ ar231x_write_reg(AR531X_IMR, imr); -+ ar231x_read_reg(AR531X_IMR); /* flush write buffer */ -+} -+ -+static void -+ar5312_misc_intr_end(unsigned int irq) -+{ -+ if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) -+ ar5312_misc_intr_enable(irq); -+} -+ -+static struct irq_chip ar5312_misc_intr_controller = { -+ .name = "AR5312-MISC", -+ .disable = ar5312_misc_intr_disable, -+ .ack = ar5312_misc_intr_disable, -+ .mask_ack = ar5312_misc_intr_disable, -+ .mask = ar5312_misc_intr_disable, -+ .unmask = ar5312_misc_intr_enable, -+ .end = ar5312_misc_intr_end, -+}; -+ -+ -+static irqreturn_t ar5312_ahb_proc_handler(int cpl, void *dev_id) -+{ -+ u32 proc1 = ar231x_read_reg(AR531X_PROC1); -+ u32 procAddr = ar231x_read_reg(AR531X_PROCADDR); /* clears error state */ -+ u32 dma1 = ar231x_read_reg(AR531X_DMA1); -+ u32 dmaAddr = ar231x_read_reg(AR531X_DMAADDR); /* clears error state */ -+ -+ printk("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n", -+ procAddr, proc1, dmaAddr, dma1); -+ -+ machine_restart("AHB error"); /* Catastrophic failure */ -+ return IRQ_HANDLED; -+} -+ -+ -+static struct irqaction ar5312_ahb_proc_interrupt = { -+ .handler = ar5312_ahb_proc_handler, -+ .flags = IRQF_DISABLED, -+ .name = "ar5312_ahb_proc_interrupt", -+}; -+ -+ -+static struct irqaction cascade = { -+ .handler = no_action, -+ .flags = IRQF_DISABLED, -+ .name = "cascade", -+}; -+ -+void __init ar5312_irq_init(void) -+{ -+ int i; -+ -+ if (!is_5312()) -+ return; -+ -+ ar231x_irq_dispatch = ar5312_irq_dispatch; -+ for (i = 0; i < AR531X_MISC_IRQ_COUNT; i++) { -+ int irq = AR531X_MISC_IRQ_BASE + i; -+ set_irq_chip_and_handler(irq, &ar5312_misc_intr_controller, -+ handle_level_irq); -+ } -+ setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt); -+ setup_irq(AR5312_IRQ_MISC_INTRS, &cascade); -+} -+ -+const struct ar231x_gpiodev ar5312_gpiodev; -+ -+static u32 -+ar5312_gpio_get_output(void) -+{ -+ u32 reg; -+ reg = ~(ar231x_read_reg(AR531X_GPIO_CR)); -+ reg &= ar5312_gpiodev.valid_mask; -+ return reg; -+} -+ -+static u32 -+ar5312_gpio_set_output(u32 mask, u32 val) -+{ -+ u32 reg; -+ -+ reg = ar231x_read_reg(AR531X_GPIO_CR); -+ reg |= mask; -+ reg &= ~val; -+ ar231x_write_reg(AR531X_GPIO_CR, reg); -+ return reg; -+} -+ -+static u32 -+ar5312_gpio_get(void) -+{ -+ u32 reg; -+ reg = ar231x_read_reg(AR531X_GPIO_DI); -+ reg &= ar5312_gpiodev.valid_mask; -+ return reg; -+} -+ -+static u32 -+ar5312_gpio_set(u32 mask, u32 value) -+{ -+ u32 reg; -+ reg = ar231x_read_reg(AR531X_GPIO_DO); -+ reg &= ~mask; -+ reg |= value; -+ ar231x_write_reg(AR531X_GPIO_DO, reg); -+ return reg; -+} -+ -+const struct ar231x_gpiodev ar5312_gpiodev = { -+ .valid_mask = (1 << 8) - 1, -+ .get_output = ar5312_gpio_get_output, -+ .set_output = ar5312_gpio_set_output, -+ .get = ar5312_gpio_get, -+ .set = ar5312_gpio_set, -+}; -+ -+static struct physmap_flash_data ar5312_flash_data = { -+ .width = 2, -+}; -+ -+static struct resource ar5312_flash_resource = { -+ .start = AR531X_FLASH, -+ .end = AR531X_FLASH + 0x800000 - 1, -+ .flags = IORESOURCE_MEM, -+}; -+ -+static struct ar231x_eth ar5312_eth0_data = { -+ .reset_base = AR531X_RESET, -+ .reset_mac = AR531X_RESET_ENET0, -+ .reset_phy = AR531X_RESET_EPHY0, -+ .phy_base = KSEG1ADDR(AR531X_ENET0), -+ .config = &ar231x_board, -+}; -+ -+static struct ar231x_eth ar5312_eth1_data = { -+ .reset_base = AR531X_RESET, -+ .reset_mac = AR531X_RESET_ENET1, -+ .reset_phy = AR531X_RESET_EPHY1, -+ .phy_base = KSEG1ADDR(AR531X_ENET1), -+ .config = &ar231x_board, -+}; -+ -+static struct platform_device ar5312_physmap_flash = { -+ .name = "physmap-flash", -+ .id = 0, -+ .dev.platform_data = &ar5312_flash_data, -+ .resource = &ar5312_flash_resource, -+ .num_resources = 1, -+}; -+ -+#ifdef CONFIG_LEDS_GPIO -+static struct gpio_led ar5312_leds[] = { -+ { .name = "wlan", .gpio = 0, .active_low = 1, }, -+}; -+ -+static const struct gpio_led_platform_data ar5312_led_data = { -+ .num_leds = ARRAY_SIZE(ar5312_leds), -+ .leds = (void *) ar5312_leds, -+}; -+ -+static struct platform_device ar5312_gpio_leds = { -+ .name = "leds-gpio", -+ .id = -1, -+ .dev.platform_data = (void *) &ar5312_led_data, -+}; -+#endif -+ -+/* -+ * NB: This mapping size is larger than the actual flash size, -+ * but this shouldn't be a problem here, because the flash -+ * will simply be mapped multiple times. -+ */ -+static char __init *ar5312_flash_limit(void) -+{ -+ u32 ctl; -+ /* -+ * Configure flash bank 0. -+ * Assume 8M window size. Flash will be aliased if it's smaller -+ */ -+ ctl = FLASHCTL_E | -+ FLASHCTL_AC_8M | -+ FLASHCTL_RBLE | -+ (0x01 << FLASHCTL_IDCY_S) | -+ (0x07 << FLASHCTL_WST1_S) | -+ (0x07 << FLASHCTL_WST2_S) | -+ (ar231x_read_reg(AR531X_FLASHCTL0) & FLASHCTL_MW); -+ -+ ar231x_write_reg(AR531X_FLASHCTL0, ctl); -+ -+ /* Disable other flash banks */ -+ ar231x_write_reg(AR531X_FLASHCTL1, -+ ar231x_read_reg(AR531X_FLASHCTL1) & ~(FLASHCTL_E | FLASHCTL_AC)); -+ -+ ar231x_write_reg(AR531X_FLASHCTL2, -+ ar231x_read_reg(AR531X_FLASHCTL2) & ~(FLASHCTL_E | FLASHCTL_AC)); -+ -+ return (char *) KSEG1ADDR(AR531X_FLASH + 0x800000); -+} -+ -+int __init ar5312_init_devices(void) -+{ -+ struct ar231x_boarddata *config; -+ u32 fctl = 0; -+ const u8 *radio; -+ u8 *c; -+ -+ if (!is_5312()) -+ return 0; -+ -+ /* Locate board/radio config data */ -+ ar231x_find_config(ar5312_flash_limit()); -+ config = ar231x_board.config; -+ -+ -+ /* -+ * Chip IDs and hardware detection for some Atheros -+ * models are really broken! -+ * -+ * Atheros uses a disabled WMAC0 and Silicon ID of AR5312 -+ * as indication for AR2312, which is otherwise -+ * indistinguishable from the real AR5312. -+ */ -+ if (ar231x_board.radio) { -+ radio = ar231x_board.radio + AR531X_RADIO_MASK_OFF; -+ if ((*((const u32 *) radio) & AR531X_RADIO0_MASK) == 0) -+ config->flags |= BD_ISCASPER; -+ } else -+ radio = NULL; -+ -+ /* AR2313 has CPU minor rev. 10 */ -+ if ((current_cpu_data.processor_id & 0xff) == 0x0a) -+ ar231x_devtype = DEV_TYPE_AR2313; -+ -+ /* AR2312 shares the same Silicon ID as AR5312 */ -+ else if (config->flags & BD_ISCASPER) -+ ar231x_devtype = DEV_TYPE_AR2312; -+ -+ /* Everything else is probably AR5312 or compatible */ -+ else -+ ar231x_devtype = DEV_TYPE_AR5312; -+ -+ /* fixup flash width */ -+ fctl = ar231x_read_reg(AR531X_FLASHCTL) & FLASHCTL_MW; -+ switch (fctl) { -+ case FLASHCTL_MWx16: -+ ar5312_flash_data.width = 2; -+ break; -+ case FLASHCTL_MWx8: -+ default: -+ ar5312_flash_data.width = 1; -+ break; -+ } -+ -+ platform_device_register(&ar5312_physmap_flash); -+ -+#ifdef CONFIG_LEDS_GPIO -+ ar5312_leds[0].gpio = config->sysLedGpio; -+ platform_device_register(&ar5312_gpio_leds); -+#endif -+ -+ /* Fix up MAC addresses if necessary */ -+ if (!memcmp(config->enet0_mac, "\xff\xff\xff\xff\xff\xff", 6)) -+ memcpy(config->enet0_mac, config->enet1_mac, 6); -+ -+ /* If ENET0 and ENET1 have the same mac address, -+ * increment the one from ENET1 */ -+ if (memcmp(config->enet0_mac, config->enet1_mac, 6) == 0) { -+ c = config->enet1_mac + 5; -+ while ((c >= config->enet1_mac) && !(++(*c))) -+ c--; -+ } -+ -+ switch(ar231x_devtype) { -+ case DEV_TYPE_AR5312: -+ ar5312_eth0_data.macaddr = config->enet0_mac; -+ ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET0), -+ AR5312_IRQ_ENET0_INTRS, &ar5312_eth0_data); -+ -+ ar5312_eth1_data.macaddr = config->enet1_mac; -+ ar231x_add_ethernet(1, KSEG1ADDR(AR531X_ENET1), -+ AR5312_IRQ_ENET1_INTRS, &ar5312_eth1_data); -+ -+ if (!ar231x_board.radio) -+ return 0; -+ -+ if ((*((u32 *) radio) & AR531X_RADIO0_MASK) && -+ (config->flags & BD_WLAN0)) -+ ar231x_add_wmac(0, AR531X_WLAN0, -+ AR5312_IRQ_WLAN0_INTRS); -+ -+ break; -+ /* -+ * AR2312/3 ethernet uses the PHY of ENET0, but the MAC -+ * of ENET1. Atheros calls it 'twisted' for a reason :) -+ */ -+ case DEV_TYPE_AR2312: -+ case DEV_TYPE_AR2313: -+ ar5312_eth1_data.phy_base = ar5312_eth0_data.phy_base; -+ ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy; -+ ar5312_eth1_data.macaddr = config->enet0_mac; -+ ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET1), -+ AR5312_IRQ_ENET1_INTRS, &ar5312_eth1_data); -+ -+ if (!ar231x_board.radio) -+ return 0; -+ break; -+ default: -+ break; -+ } -+ -+ if ((*((u32 *) radio) & AR531X_RADIO1_MASK) && -+ (config->flags & BD_WLAN1)) -+ ar231x_add_wmac(1, AR531X_WLAN1, -+ AR5312_IRQ_WLAN1_INTRS); -+ -+ return 0; -+} -+ -+ -+static void ar5312_restart(char *command) -+{ -+ /* reset the system */ -+ local_irq_disable(); -+ while(1) { -+ ar231x_write_reg(AR531X_RESET, AR531X_RESET_SYSTEM); -+ } -+} -+ -+ -+/* -+ * This table is indexed by bits 5..4 of the CLOCKCTL1 register -+ * to determine the predevisor value. -+ */ -+static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = { 1, 2, 4, 5 }; -+ -+ -+static int __init -+ar5312_cpu_frequency(void) -+{ -+ unsigned int result; -+ unsigned int predivide_mask, predivide_shift; -+ unsigned int multiplier_mask, multiplier_shift; -+ unsigned int clockCtl1, preDivideSelect, preDivisor, multiplier; -+ unsigned int doubler_mask; -+ u16 devid; -+ -+ /* Trust the bootrom's idea of cpu frequency. */ -+ if ((result = ar231x_read_reg(AR5312_SCRATCH))) -+ return result; -+ -+ devid = ar231x_read_reg(AR531X_REV); -+ devid &= AR531X_REV_MAJ; -+ devid >>= AR531X_REV_MAJ_S; -+ if (devid == AR531X_REV_MAJ_AR2313) { -+ predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK; -+ predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT; -+ multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK; -+ multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT; -+ doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK; -+ } else { /* AR5312 and AR2312 */ -+ predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK; -+ predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT; -+ multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK; -+ multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT; -+ doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK; -+ } -+ -+ /* -+ * Clocking is derived from a fixed 40MHz input clock. -+ * -+ * cpuFreq = InputClock * MULT (where MULT is PLL multiplier) -+ * sysFreq = cpuFreq / 4 (used for APB clock, serial, -+ * flash, Timer, Watchdog Timer) -+ * -+ * cntFreq = cpuFreq / 2 (use for CPU count/compare) -+ * -+ * So, for example, with a PLL multiplier of 5, we have -+ * -+ * cpuFreq = 200MHz -+ * sysFreq = 50MHz -+ * cntFreq = 100MHz -+ * -+ * We compute the CPU frequency, based on PLL settings. -+ */ -+ -+ clockCtl1 = ar231x_read_reg(AR5312_CLOCKCTL1); -+ preDivideSelect = (clockCtl1 & predivide_mask) >> predivide_shift; -+ preDivisor = CLOCKCTL1_PREDIVIDE_TABLE[preDivideSelect]; -+ multiplier = (clockCtl1 & multiplier_mask) >> multiplier_shift; -+ -+ if (clockCtl1 & doubler_mask) { -+ multiplier = multiplier << 1; -+ } -+ return (40000000 / preDivisor) * multiplier; -+} -+ -+static inline int -+ar5312_sys_frequency(void) -+{ -+ return ar5312_cpu_frequency() / 4; -+} -+ -+void __init -+ar5312_time_init(void) -+{ -+ if (!is_5312()) -+ return; -+ -+ mips_hpt_frequency = ar5312_cpu_frequency() / 2; -+} -+ -+ -+void __init -+ar5312_prom_init(void) -+{ -+ u32 memsize, memcfg, bank0AC, bank1AC; -+ u32 devid; -+ -+ if (!is_5312()) -+ return; -+ -+ /* Detect memory size */ -+ memcfg = ar231x_read_reg(AR531X_MEM_CFG1); -+ bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S; -+ bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S; -+ memsize = (bank0AC ? (1 << (bank0AC+1)) : 0) -+ + (bank1AC ? (1 << (bank1AC+1)) : 0); -+ memsize <<= 20; -+ add_memory_region(0, memsize, BOOT_MEM_RAM); -+ -+ devid = ar231x_read_reg(AR531X_REV); -+ devid >>= AR531X_REV_WMAC_MIN_S; -+ devid &= AR531X_REV_CHIP; -+ ar231x_board.devid = (u16) devid; -+ ar231x_gpiodev = &ar5312_gpiodev; -+} -+ -+void __init -+ar5312_plat_setup(void) -+{ -+ if (!is_5312()) -+ return; -+ -+ /* Clear any lingering AHB errors */ -+ ar231x_read_reg(AR531X_PROCADDR); -+ ar231x_read_reg(AR531X_DMAADDR); -+ ar231x_write_reg(AR531X_WD_CTRL, AR531X_WD_CTRL_IGNORE_EXPIRATION); -+ -+ _machine_restart = ar5312_restart; -+ ar231x_serial_setup(KSEG1ADDR(AR531X_UART0), ar5312_sys_frequency()); -+} -+ -diff -Nur linux-2.6.37.orig/arch/mips/ar231x/ar5312.h linux-2.6.37/arch/mips/ar231x/ar5312.h ---- linux-2.6.37.orig/arch/mips/ar231x/ar5312.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar231x/ar5312.h 2011-05-15 19:24:57.000000000 +0200 -@@ -0,0 +1,38 @@ -+#ifndef __AR5312_H -+#define __AR5312_H -+ -+#ifdef CONFIG_ATHEROS_AR5312 -+ -+extern void ar5312_irq_init(void); -+extern int ar5312_init_devices(void); -+extern void ar5312_prom_init(void); -+extern void ar5312_plat_setup(void); -+extern void ar5312_time_init(void); -+extern void ar5312_time_init(void); -+ -+#else -+ -+static inline void ar5312_irq_init(void) -+{ -+} -+ -+static inline int ar5312_init_devices(void) -+{ -+ return 0; -+} -+ -+static inline void ar5312_prom_init(void) -+{ -+} -+ -+static inline void ar5312_plat_setup(void) -+{ -+} -+ -+static inline void ar5312_time_init(void) -+{ -+} -+ -+#endif -+ -+#endif -diff -Nur linux-2.6.37.orig/arch/mips/ar231x/board.c linux-2.6.37/arch/mips/ar231x/board.c ---- linux-2.6.37.orig/arch/mips/ar231x/board.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar231x/board.c 2011-05-15 19:24:57.000000000 +0200 -@@ -0,0 +1,251 @@ -+/* -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. -+ * Copyright (C) 2006 FON Technology, SL. -+ * Copyright (C) 2006 Imre Kaloz -+ * Copyright (C) 2006-2009 Felix Fietkau -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include "devices.h" -+#include "ar5312.h" -+#include "ar2315.h" -+ -+void (*ar231x_irq_dispatch)(void); -+ -+static inline bool -+check_radio_magic(u8 *addr) -+{ -+ addr += 0x7a; /* offset for flash magic */ -+ if ((addr[0] == 0x5a) && (addr[1] == 0xa5)) { -+ return 1; -+ } -+ return 0; -+} -+ -+static inline bool -+check_board_data(u8 *flash_limit, u8 *addr, bool broken) -+{ -+ /* config magic found */ -+ if (*((u32 *)addr) == AR531X_BD_MAGIC) -+ return 1; -+ -+ if (!broken) -+ return 0; -+ -+ if (check_radio_magic(addr + 0xf8)) -+ ar231x_board.radio = addr + 0xf8; -+ if ((addr < flash_limit + 0x10000) && -+ check_radio_magic(addr + 0x10000)) -+ ar231x_board.radio = addr + 0x10000; -+ -+ if (ar231x_board.radio) { -+ /* broken board data detected, use radio data to find the offset, -+ * user will fix this */ -+ return 1; -+ } -+ return 0; -+} -+ -+static u8 * -+find_board_config(u8 *flash_limit, bool broken) -+{ -+ u8 *addr; -+ int found = 0; -+ -+ for (addr = flash_limit - 0x1000; -+ addr >= flash_limit - 0x30000; -+ addr -= 0x1000) { -+ -+ if (check_board_data(flash_limit, addr, broken)) { -+ found = 1; -+ break; -+ } -+ } -+ -+ if (!found) -+ addr = NULL; -+ -+ return addr; -+} -+ -+static u8 * -+find_radio_config(u8 *flash_limit, u8 *board_config) -+{ -+ int found; -+ u8 *radio_config; -+ -+ /* -+ * Now find the start of Radio Configuration data, using heuristics: -+ * Search forward from Board Configuration data by 0x1000 bytes -+ * at a time until we find non-0xffffffff. -+ */ -+ found = 0; -+ for (radio_config = board_config + 0x1000; -+ (radio_config < flash_limit); -+ radio_config += 0x1000) { -+ if ((*(u32 *)radio_config != 0xffffffff) && -+ check_radio_magic(radio_config)) { -+ found = 1; -+ break; -+ } -+ } -+ -+ /* AR2316 relocates radio config to new location */ -+ if (!found) { -+ for (radio_config = board_config + 0xf8; -+ (radio_config < flash_limit - 0x1000 + 0xf8); -+ radio_config += 0x1000) { -+ if ((*(u32 *)radio_config != 0xffffffff) && -+ check_radio_magic(radio_config)) { -+ found = 1; -+ break; -+ } -+ } -+ } -+ -+ if (!found) { -+ printk("Could not find Radio Configuration data\n"); -+ radio_config = 0; -+ } -+ -+ return (u8 *) radio_config; -+} -+ -+int __init -+ar231x_find_config(u8 *flash_limit) -+{ -+ struct ar231x_boarddata *config; -+ unsigned int rcfg_size; -+ int broken_boarddata = 0; -+ u8 *bcfg, *rcfg; -+ u8 *board_data; -+ u8 *radio_data; -+ u32 offset; -+ -+ ar231x_board.config = NULL; -+ ar231x_board.radio = NULL; -+ /* Copy the board and radio data to RAM, because accessing the mapped -+ * memory of the flash directly after booting is not safe */ -+ -+ /* Try to find valid board and radio data */ -+ bcfg = find_board_config(flash_limit, false); -+ -+ /* If that fails, try to at least find valid radio data */ -+ if (!bcfg) { -+ bcfg = find_board_config(flash_limit, true); -+ broken_boarddata = 1; -+ } -+ -+ if (!bcfg) { -+ printk(KERN_WARNING "WARNING: No board configuration data found!\n"); -+ return -ENODEV; -+ } -+ -+ board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL); -+ ar231x_board.config = (struct ar231x_boarddata *) board_data; -+ memcpy(board_data, bcfg, 0x100); -+ if (broken_boarddata) { -+ printk(KERN_WARNING "WARNING: broken board data detected\n"); -+ config = ar231x_board.config; -+ if (!memcmp(config->enet0_mac, "\x00\x00\x00\x00\x00\x00", 6)) { -+ printk(KERN_INFO "Fixing up empty mac addresses\n"); -+ config->resetConfigGpio = 0xffff; -+ config->sysLedGpio = 0xffff; -+ random_ether_addr(config->wlan0_mac); -+ config->wlan0_mac[0] &= ~0x06; -+ random_ether_addr(config->enet0_mac); -+ random_ether_addr(config->enet1_mac); -+ } -+ } -+ -+ -+ /* Radio config starts 0x100 bytes after board config, regardless -+ * of what the physical layout on the flash chip looks like */ -+ -+ if (ar231x_board.radio) -+ rcfg = (u8 *) ar231x_board.radio; -+ else -+ rcfg = find_radio_config(flash_limit, bcfg); -+ -+ if (!rcfg) -+ return -ENODEV; -+ -+ radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff); -+ ar231x_board.radio = radio_data; -+ offset = radio_data - board_data; -+ printk(KERN_INFO "Radio config found at offset 0x%x(0x%x)\n", rcfg - bcfg, offset); -+ rcfg_size = BOARD_CONFIG_BUFSZ - offset; -+ memcpy(radio_data, rcfg, rcfg_size); -+ -+ return 0; -+} -+ -+static void -+ar231x_halt(void) -+{ -+ local_irq_disable(); -+ while (1); -+} -+ -+void __init -+plat_mem_setup(void) -+{ -+ _machine_halt = ar231x_halt; -+ pm_power_off = ar231x_halt; -+ -+ ar5312_plat_setup(); -+ ar2315_plat_setup(); -+ -+ /* Disable data watchpoints */ -+ write_c0_watchlo0(0); -+} -+ -+ -+asmlinkage void -+plat_irq_dispatch(void) -+{ -+ ar231x_irq_dispatch(); -+} -+ -+void __init -+plat_time_init(void) -+{ -+ ar5312_time_init(); -+ ar2315_time_init(); -+} -+ -+unsigned int __cpuinit -+get_c0_compare_int(void) -+{ -+ return CP0_LEGACY_COMPARE_IRQ; -+} -+ -+void __init -+arch_init_irq(void) -+{ -+ clear_c0_status(ST0_IM); -+ mips_cpu_irq_init(); -+ -+ /* Initialize interrupt controllers */ -+ ar5312_irq_init(); -+ ar2315_irq_init(); -+} -+ -+ -diff -Nur linux-2.6.37.orig/arch/mips/ar231x/devices.c linux-2.6.37/arch/mips/ar231x/devices.c ---- linux-2.6.37.orig/arch/mips/ar231x/devices.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar231x/devices.c 2011-05-15 19:24:57.000000000 +0200 -@@ -0,0 +1,175 @@ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "devices.h" -+#include "ar5312.h" -+#include "ar2315.h" -+ -+struct ar231x_board_config ar231x_board; -+int ar231x_devtype = DEV_TYPE_UNKNOWN; -+const struct ar231x_gpiodev *ar231x_gpiodev; -+EXPORT_SYMBOL(ar231x_gpiodev); -+ -+static struct resource ar231x_eth0_res[] = { -+ { -+ .name = "eth0_membase", -+ .flags = IORESOURCE_MEM, -+ }, -+ { -+ .name = "eth0_irq", -+ .flags = IORESOURCE_IRQ, -+ } -+}; -+ -+static struct resource ar231x_eth1_res[] = { -+ { -+ .name = "eth1_membase", -+ .flags = IORESOURCE_MEM, -+ }, -+ { -+ .name = "eth1_irq", -+ .flags = IORESOURCE_IRQ, -+ } -+}; -+ -+static struct platform_device ar231x_eth[] = { -+ { -+ .id = 0, -+ .name = "ar231x-eth", -+ .resource = ar231x_eth0_res, -+ .num_resources = ARRAY_SIZE(ar231x_eth0_res) -+ }, -+ { -+ .id = 1, -+ .name = "ar231x-eth", -+ .resource = ar231x_eth1_res, -+ .num_resources = ARRAY_SIZE(ar231x_eth1_res) -+ } -+}; -+ -+static struct resource ar231x_wmac0_res[] = { -+ { -+ .name = "wmac0_membase", -+ .flags = IORESOURCE_MEM, -+ }, -+ { -+ .name = "wmac0_irq", -+ .flags = IORESOURCE_IRQ, -+ } -+}; -+ -+static struct resource ar231x_wmac1_res[] = { -+ { -+ .name = "wmac1_membase", -+ .flags = IORESOURCE_MEM, -+ }, -+ { -+ .name = "wmac1_irq", -+ .flags = IORESOURCE_IRQ, -+ } -+}; -+ -+ -+static struct platform_device ar231x_wmac[] = { -+ { -+ .id = 0, -+ .name = "ar231x-wmac", -+ .resource = ar231x_wmac0_res, -+ .num_resources = ARRAY_SIZE(ar231x_wmac0_res), -+ .dev.platform_data = &ar231x_board, -+ }, -+ { -+ .id = 1, -+ .name = "ar231x-wmac", -+ .resource = ar231x_wmac1_res, -+ .num_resources = ARRAY_SIZE(ar231x_wmac1_res), -+ .dev.platform_data = &ar231x_board, -+ }, -+}; -+ -+static const char *devtype_strings[] = { -+ [DEV_TYPE_AR5312] = "Atheros AR5312", -+ [DEV_TYPE_AR2312] = "Atheros AR2312", -+ [DEV_TYPE_AR2313] = "Atheros AR2313", -+ [DEV_TYPE_AR2315] = "Atheros AR2315", -+ [DEV_TYPE_AR2316] = "Atheros AR2316", -+ [DEV_TYPE_AR2317] = "Atheros AR2317", -+ [DEV_TYPE_UNKNOWN] = "Atheros (unknown)", -+}; -+ -+const char *get_system_type(void) -+{ -+ if ((ar231x_devtype >= ARRAY_SIZE(devtype_strings)) || -+ !devtype_strings[ar231x_devtype]) -+ return devtype_strings[DEV_TYPE_UNKNOWN]; -+ return devtype_strings[ar231x_devtype]; -+} -+ -+ -+int __init -+ar231x_add_ethernet(int nr, u32 base, int irq, void *pdata) -+{ -+ struct resource *res; -+ -+ ar231x_eth[nr].dev.platform_data = pdata; -+ res = &ar231x_eth[nr].resource[0]; -+ res->start = base; -+ res->end = base + 0x2000 - 1; -+ res++; -+ res->start = irq; -+ res->end = irq; -+ return platform_device_register(&ar231x_eth[nr]); -+} -+ -+void __init -+ar231x_serial_setup(u32 mapbase, unsigned int uartclk) -+{ -+ struct uart_port s; -+ -+ memset(&s, 0, sizeof(s)); -+ -+ s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST; -+ s.iotype = UPIO_MEM; -+ s.irq = AR531X_MISC_IRQ_UART0; -+ s.regshift = 2; -+ s.mapbase = mapbase; -+ s.uartclk = uartclk; -+ s.membase = (void __iomem *)s.mapbase; -+ -+ early_serial_setup(&s); -+} -+ -+int __init -+ar231x_add_wmac(int nr, u32 base, int irq) -+{ -+ struct resource *res; -+ -+ ar231x_wmac[nr].dev.platform_data = &ar231x_board; -+ res = &ar231x_wmac[nr].resource[0]; -+ res->start = base; -+ res->end = base + 0x10000 - 1; -+ res++; -+ res->start = irq; -+ res->end = irq; -+ return platform_device_register(&ar231x_wmac[nr]); -+} -+ -+static int __init ar231x_register_devices(void) -+{ -+ static struct resource res = { -+ .start = 0xFFFFFFFF, -+ }; -+ -+ platform_device_register_simple("GPIODEV", 0, &res, 1); -+ ar5312_init_devices(); -+ ar2315_init_devices(); -+ -+ return 0; -+} -+ -+device_initcall(ar231x_register_devices); -diff -Nur linux-2.6.37.orig/arch/mips/ar231x/devices.h linux-2.6.37/arch/mips/ar231x/devices.h ---- linux-2.6.37.orig/arch/mips/ar231x/devices.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar231x/devices.h 2011-05-15 19:24:57.000000000 +0200 -@@ -0,0 +1,37 @@ -+#ifndef __AR231X_DEVICES_H -+#define __AR231X_DEVICES_H -+ -+enum { -+ /* handled by ar5312.c */ -+ DEV_TYPE_AR2312, -+ DEV_TYPE_AR2313, -+ DEV_TYPE_AR5312, -+ -+ /* handled by ar2315.c */ -+ DEV_TYPE_AR2315, -+ DEV_TYPE_AR2316, -+ DEV_TYPE_AR2317, -+ -+ DEV_TYPE_UNKNOWN -+}; -+ -+extern int ar231x_devtype; -+extern struct ar231x_board_config ar231x_board; -+extern asmlinkage void (*ar231x_irq_dispatch)(void); -+ -+extern int ar231x_find_config(u8 *flash_limit); -+extern void ar231x_serial_setup(u32 mapbase, unsigned int uartclk); -+extern int ar231x_add_wmac(int nr, u32 base, int irq); -+extern int ar231x_add_ethernet(int nr, u32 base, int irq, void *pdata); -+ -+static inline bool is_2315(void) -+{ -+ return (current_cpu_data.cputype == CPU_4KEC); -+} -+ -+static inline bool is_5312(void) -+{ -+ return !is_2315(); -+} -+ -+#endif -diff -Nur linux-2.6.37.orig/arch/mips/ar231x/early_printk.c linux-2.6.37/arch/mips/ar231x/early_printk.c ---- linux-2.6.37.orig/arch/mips/ar231x/early_printk.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar231x/early_printk.c 2011-05-15 19:24:57.000000000 +0200 -@@ -0,0 +1,44 @@ -+/* -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 2010 Gabor Juhos -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include "devices.h" -+ -+static inline void prom_uart_wr(void __iomem *base, unsigned reg, -+ unsigned char ch) -+{ -+ __raw_writeb(ch, base + 4 * reg); -+} -+ -+static inline unsigned char prom_uart_rr(void __iomem *base, unsigned reg) -+{ -+ return __raw_readb(base + 4 * reg); -+} -+ -+void prom_putchar(unsigned char ch) -+{ -+ static void __iomem *base; -+ -+ if (unlikely(base == NULL)) { -+ if (is_2315()) -+ base = (void __iomem *)(KSEG1ADDR(AR2315_UART0)); -+ else -+ base = (void __iomem *)(KSEG1ADDR(AR531X_UART0)); -+ } -+ -+ while ((prom_uart_rr(base, UART_LSR) & UART_LSR_THRE) == 0); -+ prom_uart_wr(base, UART_TX, ch); -+ while ((prom_uart_rr(base, UART_LSR) & UART_LSR_THRE) == 0); -+} -+ -diff -Nur linux-2.6.37.orig/arch/mips/ar231x/pci.c linux-2.6.37/arch/mips/ar231x/pci.c ---- linux-2.6.37.orig/arch/mips/ar231x/pci.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar231x/pci.c 2011-05-15 19:24:57.000000000 +0200 -@@ -0,0 +1,230 @@ -+/* -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "devices.h" -+ -+#define AR531X_MEM_BASE 0x80800000UL -+#define AR531X_MEM_SIZE 0x00ffffffUL -+#define AR531X_IO_SIZE 0x00007fffUL -+ -+static unsigned long configspace; -+ -+static int config_access(int devfn, int where, int size, u32 *ptr, bool write) -+{ -+ unsigned long flags; -+ int func = PCI_FUNC(devfn); -+ int dev = PCI_SLOT(devfn); -+ u32 value = 0; -+ int err = 0; -+ u32 addr; -+ -+ if (((dev != 0) && (dev != 3)) || (func > 2)) -+ return PCIBIOS_DEVICE_NOT_FOUND; -+ -+ /* Select Configuration access */ -+ local_irq_save(flags); -+ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, 0, AR2315_PCIMISC_CFG_SEL); -+ mb(); -+ -+ addr = (u32) configspace + (1 << (13 + dev)) + (func << 8) + where; -+ if (size == 1) -+ addr ^= 0x3; -+ else if (size == 2) -+ addr ^= 0x2; -+ -+ if (write) { -+ value = *ptr; -+ if (size == 1) -+ err = put_dbe(value, (u8 *) addr); -+ else if (size == 2) -+ err = put_dbe(value, (u16 *) addr); -+ else if (size == 4) -+ err = put_dbe(value, (u32 *) addr); -+ } else { -+ if (size == 1) -+ err = get_dbe(value, (u8 *) addr); -+ else if (size == 2) -+ err = get_dbe(value, (u16 *) addr); -+ else if (size == 4) -+ err = get_dbe(value, (u32 *) addr); -+ if (err) -+ *ptr = 0xffffffff; -+ else -+ *ptr = value; -+ } -+ -+ /* Select Memory access */ -+ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_CFG_SEL, 0); -+ local_irq_restore(flags); -+ -+ return (err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL); -+} -+ -+static int ar231x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * value) -+{ -+ return config_access(devfn, where, size, value, 0); -+} -+ -+static int ar231x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value) -+{ -+ return config_access(devfn, where, size, &value, 1); -+} -+ -+struct pci_ops ar231x_pci_ops = { -+ .read = ar231x_pci_read, -+ .write = ar231x_pci_write, -+}; -+ -+static struct resource ar231x_mem_resource = { -+ .name = "AR531x PCI MEM", -+ .start = AR531X_MEM_BASE, -+ .end = AR531X_MEM_BASE + AR531X_MEM_SIZE - AR531X_IO_SIZE - 1 + 0x4000000, -+ .flags = IORESOURCE_MEM, -+}; -+ -+static struct resource ar231x_io_resource = { -+ .name = "AR531x PCI I/O", -+ .start = AR531X_MEM_BASE + AR531X_MEM_SIZE - AR531X_IO_SIZE, -+ .end = AR531X_MEM_BASE + AR531X_MEM_SIZE - 1, -+ .flags = IORESOURCE_IO, -+}; -+ -+struct pci_controller ar231x_pci_controller = { -+ .pci_ops = &ar231x_pci_ops, -+ .mem_resource = &ar231x_mem_resource, -+ .io_resource = &ar231x_io_resource, -+ .mem_offset = 0x00000000UL, -+ .io_offset = 0x00000000UL, -+}; -+ -+int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -+{ -+ return AR2315_IRQ_LCBUS_PCI; -+} -+ -+int pcibios_plat_dev_init(struct pci_dev *dev) -+{ -+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 5); -+ pci_write_config_word(dev, 0x40, 0); -+ -+ /* Clear any pending Abort or external Interrupts -+ * and enable interrupt processing */ -+ ar231x_mask_reg(AR2315_PCI_INTEN_REG, AR2315_PCI_INT_ENABLE, 0); -+ ar231x_write_reg(AR2315_PCI_INT_STATUS, (AR2315_PCI_ABORT_INT | AR2315_PCI_EXT_INT)); -+ ar231x_write_reg(AR2315_PCI_INT_MASK, (AR2315_PCI_ABORT_INT | AR2315_PCI_EXT_INT)); -+ ar231x_mask_reg(AR2315_PCI_INTEN_REG, 0, AR2315_PCI_INT_ENABLE); -+ -+ return 0; -+} -+ -+static void -+ar2315_pci_fixup(struct pci_dev *dev) -+{ -+ unsigned int devfn = dev->devfn; -+ -+ if (dev->bus->number != 0) -+ return; -+ -+ /* Only fix up the PCI host settings */ -+ if ((PCI_SLOT(devfn) != 3) || (PCI_FUNC(devfn) != 0)) -+ return; -+ -+ /* Fix up MBARs */ -+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, HOST_PCI_MBAR0); -+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, HOST_PCI_MBAR1); -+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, HOST_PCI_MBAR2); -+ pci_write_config_dword(dev, PCI_COMMAND, -+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL | -+ PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | -+ PCI_COMMAND_FAST_BACK); -+} -+DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, ar2315_pci_fixup); -+ -+static int __init -+ar2315_pci_init(void) -+{ -+ u32 reg; -+ -+ if (ar231x_devtype != DEV_TYPE_AR2315) -+ return -ENODEV; -+ -+ configspace = (unsigned long) ioremap_nocache(0x80000000, 1*1024*1024); /* Remap PCI config space */ -+ ar231x_pci_controller.io_map_base = -+ (unsigned long) ioremap_nocache(AR531X_MEM_BASE + AR531X_MEM_SIZE, AR531X_IO_SIZE); -+ set_io_port_base(ar231x_pci_controller.io_map_base); /* PCI I/O space */ -+ -+ reg = ar231x_mask_reg(AR2315_RESET, 0, AR2315_RESET_PCIDMA); -+ msleep(10); -+ -+ reg &= ~AR2315_RESET_PCIDMA; -+ ar231x_write_reg(AR2315_RESET, reg); -+ msleep(10); -+ -+ ar231x_mask_reg(AR2315_ENDIAN_CTL, 0, -+ AR2315_CONFIG_PCIAHB | AR2315_CONFIG_PCIAHB_BRIDGE); -+ -+ ar231x_write_reg(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM | -+ (AR2315_PCICLK_IN_FREQ_DIV_6 << AR2315_PCICLK_DIV_S)); -+ ar231x_mask_reg(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI); -+ ar231x_mask_reg(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK | AR2315_IF_MASK, -+ AR2315_IF_PCI | AR2315_IF_PCI_HOST | AR2315_IF_PCI_INTR | -+ (AR2315_IF_PCI_CLK_OUTPUT_CLK << AR2315_IF_PCI_CLK_SHIFT)); -+ -+ /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */ -+ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE, -+ AR2315_PCIRST_LOW); -+ msleep(100); -+ -+ /* Bring the PCI out of reset */ -+ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE, -+ AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8); -+ -+ ar231x_write_reg(AR2315_PCI_UNCACHE_CFG, -+ 0x1E | /* 1GB uncached */ -+ (1 << 5) | /* Enable uncached */ -+ (0x2 << 30) /* Base: 0x80000000 */ -+ ); -+ ar231x_read_reg(AR2315_PCI_UNCACHE_CFG); -+ -+ msleep(500); -+ -+ /* dirty hack - anyone with a datasheet that knows the memory map ? */ -+ ioport_resource.start = 0x10000000; -+ ioport_resource.end = 0xffffffff; -+ iomem_resource.start = 0x10000000; -+ iomem_resource.end = 0xffffffff; -+ -+ register_pci_controller(&ar231x_pci_controller); -+ -+ return 0; -+} -+ -+arch_initcall(ar2315_pci_init); -diff -Nur linux-2.6.37.orig/arch/mips/ar231x/prom.c linux-2.6.37/arch/mips/ar231x/prom.c ---- linux-2.6.37.orig/arch/mips/ar231x/prom.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar231x/prom.c 2011-05-15 19:24:57.000000000 +0200 -@@ -0,0 +1,37 @@ -+/* -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright MontaVista Software Inc -+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. -+ * Copyright (C) 2006 FON Technology, SL. -+ * Copyright (C) 2006 Imre Kaloz -+ * Copyright (C) 2006 Felix Fietkau -+ */ -+ -+/* -+ * Prom setup file for ar531x -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include "ar5312.h" -+#include "ar2315.h" -+ -+void __init prom_init(void) -+{ -+ ar5312_prom_init(); -+ ar2315_prom_init(); -+} -+ -+void __init prom_free_prom_memory(void) -+{ -+} -diff -Nur linux-2.6.37.orig/arch/mips/ar231x/reset.c linux-2.6.37/arch/mips/ar231x/reset.c ---- linux-2.6.37.orig/arch/mips/ar231x/reset.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/ar231x/reset.c 2011-05-15 19:24:57.000000000 +0200 -@@ -0,0 +1,161 @@ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "devices.h" -+ -+#define AR531X_RESET_GPIO_IRQ (AR531X_GPIO_IRQ(ar231x_board.config->resetConfigGpio)) -+ -+struct event_t { -+ struct work_struct wq; -+ int set; -+ unsigned long jiffies; -+}; -+ -+static struct timer_list rst_button_timer; -+static unsigned long seen; -+ -+struct sock *uevent_sock = NULL; -+EXPORT_SYMBOL_GPL(uevent_sock); -+extern u64 uevent_next_seqnum(void); -+ -+static int no_release_workaround = 1; -+module_param(no_release_workaround, int, 0); -+ -+static inline void -+add_msg(struct sk_buff *skb, char *msg) -+{ -+ char *scratch; -+ scratch = skb_put(skb, strlen(msg) + 1); -+ sprintf(scratch, msg); -+} -+ -+static void -+hotplug_button(struct work_struct *wq) -+{ -+ struct sk_buff *skb; -+ struct event_t *event; -+ size_t len; -+ char *scratch, *s; -+ char buf[128]; -+ -+ event = container_of(wq, struct event_t, wq); -+ if (!uevent_sock) -+ goto done; -+ -+ /* allocate message with the maximum possible size */ -+ s = event->set ? "pressed" : "released"; -+ len = strlen(s) + 2; -+ skb = alloc_skb(NLMSG_GOODSIZE, GFP_KERNEL); -+ if (!skb) -+ goto done; -+ -+ /* add header */ -+ scratch = skb_put(skb, len); -+ sprintf(scratch, "%s@",s); -+ -+ /* copy keys to our continuous event payload buffer */ -+ add_msg(skb, "HOME=/"); -+ add_msg(skb, "PATH=/sbin:/bin:/usr/sbin:/usr/bin"); -+ add_msg(skb, "SUBSYSTEM=button"); -+ add_msg(skb, "BUTTON=reset"); -+ add_msg(skb, (event->set ? "ACTION=pressed" : "ACTION=released")); -+ sprintf(buf, "SEEN=%ld", (event->jiffies - seen)/HZ); -+ add_msg(skb, buf); -+ snprintf(buf, 128, "SEQNUM=%llu", uevent_next_seqnum()); -+ add_msg(skb, buf); -+ -+ NETLINK_CB(skb).dst_group = 1; -+ netlink_broadcast(uevent_sock, skb, 0, 1, GFP_KERNEL); -+ -+done: -+ kfree(event); -+} -+ -+static void -+reset_button_poll(unsigned long unused) -+{ -+ struct event_t *event; -+ int gpio = ~0; -+ -+ if(!no_release_workaround) -+ return; -+ -+ gpio = ar231x_gpiodev->get(); -+ gpio &= (1 << (AR531X_RESET_GPIO_IRQ - AR531X_GPIO_IRQ_BASE)); -+ if(gpio) { -+ rst_button_timer.expires = jiffies + (HZ / 4); -+ add_timer(&rst_button_timer); -+ return; -+ } -+ -+ event = (struct event_t *) kzalloc(sizeof(struct event_t), GFP_ATOMIC); -+ if (!event) -+ return; -+ -+ event->set = 0; -+ event->jiffies = jiffies; -+ INIT_WORK(&event->wq, hotplug_button); -+ schedule_work(&event->wq); -+} -+ -+static irqreturn_t -+button_handler(int irq, void *dev_id) -+{ -+ static int pressed = 0; -+ struct event_t *event; -+ u32 gpio = ~0; -+ -+ event = (struct event_t *) kzalloc(sizeof(struct event_t), GFP_ATOMIC); -+ if (!event) -+ return IRQ_NONE; -+ -+ pressed = !pressed; -+ -+ gpio = ar231x_gpiodev->get() & (1 << (irq - AR531X_GPIO_IRQ_BASE)); -+ -+ event->set = gpio; -+ if(!event->set) -+ no_release_workaround = 0; -+ -+ event->jiffies = jiffies; -+ -+ INIT_WORK(&event->wq, hotplug_button); -+ schedule_work(&event->wq); -+ -+ seen = jiffies; -+ if(event->set && no_release_workaround) -+ mod_timer(&rst_button_timer, jiffies + (HZ / 4)); -+ -+ return IRQ_HANDLED; -+} -+ -+ -+static int __init -+ar231x_init_reset(void) -+{ -+ seen = jiffies; -+ -+ if (ar231x_board.config->resetConfigGpio == 0xffff) -+ return -ENODEV; -+ -+ init_timer(&rst_button_timer); -+ rst_button_timer.function = reset_button_poll; -+ rst_button_timer.expires = jiffies + HZ / 50; -+ add_timer(&rst_button_timer); -+ -+ request_irq(AR531X_RESET_GPIO_IRQ, &button_handler, IRQF_SAMPLE_RANDOM, "ar231x_reset", NULL); -+ -+ return 0; -+} -+ -+module_init(ar231x_init_reset); -diff -Nur linux-2.6.37.orig/arch/mips/include/asm/mach-ar231x/ar2315_regs.h linux-2.6.37/arch/mips/include/asm/mach-ar231x/ar2315_regs.h ---- linux-2.6.37.orig/arch/mips/include/asm/mach-ar231x/ar2315_regs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/include/asm/mach-ar231x/ar2315_regs.h 2011-05-15 19:24:57.000000000 +0200 -@@ -0,0 +1,580 @@ -+/* -+ * Register definitions for AR2315+ -+ * -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. -+ * Copyright (C) 2006 FON Technology, SL. -+ * Copyright (C) 2006 Imre Kaloz -+ * Copyright (C) 2006-2008 Felix Fietkau -+ */ -+ -+#ifndef __AR2315_REG_H -+#define __AR2315_REG_H -+ -+/* -+ * IRQs -+ */ -+#define AR2315_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */ -+#define AR2315_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */ -+#define AR2315_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */ -+#define AR2315_IRQ_LCBUS_PCI MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */ -+#define AR2315_IRQ_WLAN0_POLL MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */ -+ -+/* -+ * Address map -+ */ -+#define AR2315_SPI_READ 0x08000000 /* SPI FLASH */ -+#define AR2315_WLAN0 0xB0000000 /* Wireless MMR */ -+#define AR2315_PCI 0xB0100000 /* PCI MMR */ -+#define AR2315_SDRAMCTL 0xB0300000 /* SDRAM MMR */ -+#define AR2315_LOCAL 0xB0400000 /* LOCAL BUS MMR */ -+#define AR2315_ENET0 0xB0500000 /* ETHERNET MMR */ -+#define AR2315_DSLBASE 0xB1000000 /* RESET CONTROL MMR */ -+#define AR2315_UART0 0xB1100003 /* UART MMR */ -+#define AR2315_SPI 0xB1300000 /* SPI FLASH MMR */ -+#define AR2315_PCIEXT 0x80000000 /* pci external */ -+ -+/* -+ * Reset Register -+ */ -+#define AR2315_COLD_RESET (AR2315_DSLBASE + 0x0000) -+ -+#define AR2315_RESET_COLD_AHB 0x00000001 -+#define AR2315_RESET_COLD_APB 0x00000002 -+#define AR2315_RESET_COLD_CPU 0x00000004 -+#define AR2315_RESET_COLD_CPUWARM 0x00000008 -+#define AR2315_RESET_SYSTEM (RESET_COLD_CPU | RESET_COLD_APB | RESET_COLD_AHB) /* full system */ -+#define AR2317_RESET_SYSTEM 0x00000010 -+ -+ -+#define AR2315_RESET (AR2315_DSLBASE + 0x0004) -+ -+#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001 /* warm reset WLAN0 MAC */ -+#define AR2315_RESET_WARM_WLAN0_BB 0x00000002 /* warm reset WLAN0 BaseBand */ -+#define AR2315_RESET_MPEGTS_RSVD 0x00000004 /* warm reset MPEG-TS */ -+#define AR2315_RESET_PCIDMA 0x00000008 /* warm reset PCI ahb/dma */ -+#define AR2315_RESET_MEMCTL 0x00000010 /* warm reset memory controller */ -+#define AR2315_RESET_LOCAL 0x00000020 /* warm reset local bus */ -+#define AR2315_RESET_I2C_RSVD 0x00000040 /* warm reset I2C bus */ -+#define AR2315_RESET_SPI 0x00000080 /* warm reset SPI interface */ -+#define AR2315_RESET_UART0 0x00000100 /* warm reset UART0 */ -+#define AR2315_RESET_IR_RSVD 0x00000200 /* warm reset IR interface */ -+#define AR2315_RESET_EPHY0 0x00000400 /* cold reset ENET0 phy */ -+#define AR2315_RESET_ENET0 0x00000800 /* cold reset ENET0 mac */ -+ -+/* -+ * AHB master arbitration control -+ */ -+#define AR2315_AHB_ARB_CTL (AR2315_DSLBASE + 0x0008) -+ -+#define AR2315_ARB_CPU 0x00000001 /* CPU, default */ -+#define AR2315_ARB_WLAN 0x00000002 /* WLAN */ -+#define AR2315_ARB_MPEGTS_RSVD 0x00000004 /* MPEG-TS */ -+#define AR2315_ARB_LOCAL 0x00000008 /* LOCAL */ -+#define AR2315_ARB_PCI 0x00000010 /* PCI */ -+#define AR2315_ARB_ETHERNET 0x00000020 /* Ethernet */ -+#define AR2315_ARB_RETRY 0x00000100 /* retry policy, debug only */ -+ -+/* -+ * Config Register -+ */ -+#define AR2315_ENDIAN_CTL (AR2315_DSLBASE + 0x000c) -+ -+#define AR2315_CONFIG_AHB 0x00000001 /* EC - AHB bridge endianess */ -+#define AR2315_CONFIG_WLAN 0x00000002 /* WLAN byteswap */ -+#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004 /* MPEG-TS byteswap */ -+#define AR2315_CONFIG_PCI 0x00000008 /* PCI byteswap */ -+#define AR2315_CONFIG_MEMCTL 0x00000010 /* Memory controller endianess */ -+#define AR2315_CONFIG_LOCAL 0x00000020 /* Local bus byteswap */ -+#define AR2315_CONFIG_ETHERNET 0x00000040 /* Ethernet byteswap */ -+ -+#define AR2315_CONFIG_MERGE 0x00000200 /* CPU write buffer merge */ -+#define AR2315_CONFIG_CPU 0x00000400 /* CPU big endian */ -+#define AR2315_CONFIG_PCIAHB 0x00000800 -+#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000 -+#define AR2315_CONFIG_SPI 0x00008000 /* SPI byteswap */ -+#define AR2315_CONFIG_CPU_DRAM 0x00010000 -+#define AR2315_CONFIG_CPU_PCI 0x00020000 -+#define AR2315_CONFIG_CPU_MMR 0x00040000 -+#define AR2315_CONFIG_BIG 0x00000400 -+ -+ -+/* -+ * NMI control -+ */ -+#define AR2315_NMI_CTL (AR2315_DSLBASE + 0x0010) -+ -+#define AR2315_NMI_EN 1 -+ -+/* -+ * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR531X 1.0). -+ */ -+#define AR2315_SREV (AR2315_DSLBASE + 0x0014) -+ -+#define AR2315_REV_MAJ 0x00f0 -+#define AR2315_REV_MAJ_S 4 -+#define AR2315_REV_MIN 0x000f -+#define AR2315_REV_MIN_S 0 -+#define AR2315_REV_CHIP (AR2315_REV_MAJ|AR2315_REV_MIN) -+ -+/* -+ * Interface Enable -+ */ -+#define AR2315_IF_CTL (AR2315_DSLBASE + 0x0018) -+ -+#define AR2315_IF_MASK 0x00000007 -+#define AR2315_IF_DISABLED 0 -+#define AR2315_IF_PCI 1 -+#define AR2315_IF_TS_LOCAL 2 -+#define AR2315_IF_ALL 3 /* only for emulation with separate pins */ -+#define AR2315_IF_LOCAL_HOST 0x00000008 -+#define AR2315_IF_PCI_HOST 0x00000010 -+#define AR2315_IF_PCI_INTR 0x00000020 -+#define AR2315_IF_PCI_CLK_MASK 0x00030000 -+#define AR2315_IF_PCI_CLK_INPUT 0 -+#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1 -+#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2 -+#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3 -+#define AR2315_IF_PCI_CLK_SHIFT 16 -+ -+/* -+ * APB Interrupt control -+ */ -+ -+#define AR2315_ISR (AR2315_DSLBASE + 0x0020) -+#define AR2315_IMR (AR2315_DSLBASE + 0x0024) -+#define AR2315_GISR (AR2315_DSLBASE + 0x0028) -+ -+#define AR2315_ISR_UART0 0x0001 /* high speed UART */ -+#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */ -+#define AR2315_ISR_SPI 0x0004 /* SPI bus */ -+#define AR2315_ISR_AHB 0x0008 /* AHB error */ -+#define AR2315_ISR_APB 0x0010 /* APB error */ -+#define AR2315_ISR_TIMER 0x0020 /* timer */ -+#define AR2315_ISR_GPIO 0x0040 /* GPIO */ -+#define AR2315_ISR_WD 0x0080 /* watchdog */ -+#define AR2315_ISR_IR_RSVD 0x0100 /* IR */ -+ -+#define AR2315_GISR_MISC 0x0001 -+#define AR2315_GISR_WLAN0 0x0002 -+#define AR2315_GISR_MPEGTS_RSVD 0x0004 -+#define AR2315_GISR_LOCALPCI 0x0008 -+#define AR2315_GISR_WMACPOLL 0x0010 -+#define AR2315_GISR_TIMER 0x0020 -+#define AR2315_GISR_ETHERNET 0x0040 -+ -+/* -+ * Interrupt routing from IO to the processor IP bits -+ * Define our inter mask and level -+ */ -+#define AR2315_INTR_MISCIO SR_IBIT3 -+#define AR2315_INTR_WLAN0 SR_IBIT4 -+#define AR2315_INTR_ENET0 SR_IBIT5 -+#define AR2315_INTR_LOCALPCI SR_IBIT6 -+#define AR2315_INTR_WMACPOLL SR_IBIT7 -+#define AR2315_INTR_COMPARE SR_IBIT8 -+ -+/* -+ * Timers -+ */ -+#define AR2315_TIMER (AR2315_DSLBASE + 0x0030) -+#define AR2315_RELOAD (AR2315_DSLBASE + 0x0034) -+#define AR2315_WD (AR2315_DSLBASE + 0x0038) -+#define AR2315_WDC (AR2315_DSLBASE + 0x003c) -+ -+#define AR2315_WDC_IGNORE_EXPIRATION 0x00000000 -+#define AR2315_WDC_NMI 0x00000001 /* NMI on watchdog */ -+#define AR2315_WDC_RESET 0x00000002 /* reset on watchdog */ -+ -+/* -+ * CPU Performance Counters -+ */ -+#define AR2315_PERFCNT0 (AR2315_DSLBASE + 0x0048) -+#define AR2315_PERFCNT1 (AR2315_DSLBASE + 0x004c) -+ -+#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */ -+#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */ -+#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */ -+#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */ -+#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */ -+#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */ -+#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */ -+ -+#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */ -+#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */ -+#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */ -+#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */ -+#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */ -+#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */ -+#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */ -+ -+/* -+ * AHB Error Reporting. -+ */ -+#define AR2315_AHB_ERR0 (AR2315_DSLBASE + 0x0050) /* error */ -+#define AR2315_AHB_ERR1 (AR2315_DSLBASE + 0x0054) /* haddr */ -+#define AR2315_AHB_ERR2 (AR2315_DSLBASE + 0x0058) /* hwdata */ -+#define AR2315_AHB_ERR3 (AR2315_DSLBASE + 0x005c) /* hrdata */ -+#define AR2315_AHB_ERR4 (AR2315_DSLBASE + 0x0060) /* status */ -+ -+#define AHB_ERROR_DET 1 /* AHB Error has been detected, */ -+ /* write 1 to clear all bits in ERR0 */ -+#define AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */ -+#define AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */ -+ -+#define AR2315_PROCERR_HMAST 0x0000000f -+#define AR2315_PROCERR_HMAST_DFLT 0 -+#define AR2315_PROCERR_HMAST_WMAC 1 -+#define AR2315_PROCERR_HMAST_ENET 2 -+#define AR2315_PROCERR_HMAST_PCIENDPT 3 -+#define AR2315_PROCERR_HMAST_LOCAL 4 -+#define AR2315_PROCERR_HMAST_CPU 5 -+#define AR2315_PROCERR_HMAST_PCITGT 6 -+ -+#define AR2315_PROCERR_HMAST_S 0 -+#define AR2315_PROCERR_HWRITE 0x00000010 -+#define AR2315_PROCERR_HSIZE 0x00000060 -+#define AR2315_PROCERR_HSIZE_S 5 -+#define AR2315_PROCERR_HTRANS 0x00000180 -+#define AR2315_PROCERR_HTRANS_S 7 -+#define AR2315_PROCERR_HBURST 0x00000e00 -+#define AR2315_PROCERR_HBURST_S 9 -+ -+/* -+ * Clock Control -+ */ -+#define AR2315_PLLC_CTL (AR2315_DSLBASE + 0x0064) -+#define AR2315_PLLV_CTL (AR2315_DSLBASE + 0x0068) -+#define AR2315_CPUCLK (AR2315_DSLBASE + 0x006c) -+#define AR2315_AMBACLK (AR2315_DSLBASE + 0x0070) -+#define AR2315_SYNCCLK (AR2315_DSLBASE + 0x0074) -+#define AR2315_DSL_SLEEP_CTL (AR2315_DSLBASE + 0x0080) -+#define AR2315_DSL_SLEEP_DUR (AR2315_DSLBASE + 0x0084) -+ -+/* PLLc Control fields */ -+#define PLLC_REF_DIV_M 0x00000003 -+#define PLLC_REF_DIV_S 0 -+#define PLLC_FDBACK_DIV_M 0x0000007C -+#define PLLC_FDBACK_DIV_S 2 -+#define PLLC_ADD_FDBACK_DIV_M 0x00000080 -+#define PLLC_ADD_FDBACK_DIV_S 7 -+#define PLLC_CLKC_DIV_M 0x0001c000 -+#define PLLC_CLKC_DIV_S 14 -+#define PLLC_CLKM_DIV_M 0x00700000 -+#define PLLC_CLKM_DIV_S 20 -+ -+/* CPU CLK Control fields */ -+#define CPUCLK_CLK_SEL_M 0x00000003 -+#define CPUCLK_CLK_SEL_S 0 -+#define CPUCLK_CLK_DIV_M 0x0000000c -+#define CPUCLK_CLK_DIV_S 2 -+ -+/* AMBA CLK Control fields */ -+#define AMBACLK_CLK_SEL_M 0x00000003 -+#define AMBACLK_CLK_SEL_S 0 -+#define AMBACLK_CLK_DIV_M 0x0000000c -+#define AMBACLK_CLK_DIV_S 2 -+ -+/* -+ * GPIO -+ */ -+#define AR2315_GPIO_DI (AR2315_DSLBASE + 0x0088) -+#define AR2315_GPIO_DO (AR2315_DSLBASE + 0x0090) -+#define AR2315_GPIO_CR (AR2315_DSLBASE + 0x0098) -+#define AR2315_GPIO_INT (AR2315_DSLBASE + 0x00a0) -+ -+#define AR2315_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */ -+#define AR2315_GPIO_CR_O(x) (1 << (x)) /* output */ -+#define AR2315_GPIO_CR_I(x) (0) /* input */ -+ -+#define AR2315_GPIO_INT_S(x) (x) /* interrupt enable */ -+#define AR2315_GPIO_INT_M (0x3F) /* mask for int */ -+#define AR2315_GPIO_INT_LVL(x) ((x) << 6) /* interrupt level */ -+#define AR2315_GPIO_INT_LVL_M ((0x3) << 6) /* mask for int level */ -+ -+#define AR2315_GPIO_INT_MAX_Y 1 /* Maximum value of Y for AR5313_GPIO_INT_* macros */ -+#define AR2315_GPIO_INT_LVL_OFF 0 /* Triggerring off */ -+#define AR2315_GPIO_INT_LVL_LOW 1 /* Low Level Triggered */ -+#define AR2315_GPIO_INT_LVL_HIGH 2 /* High Level Triggered */ -+#define AR2315_GPIO_INT_LVL_EDGE 3 /* Edge Triggered */ -+ -+#define AR2315_RESET_GPIO 5 -+#define AR2315_NUM_GPIO 22 -+ -+/* -+ * PCI Clock Control -+ */ -+#define AR2315_PCICLK (AR2315_DSLBASE + 0x00a4) -+ -+#define AR2315_PCICLK_INPUT_M 0x3 -+#define AR2315_PCICLK_INPUT_S 0 -+ -+#define AR2315_PCICLK_PLLC_CLKM 0 -+#define AR2315_PCICLK_PLLC_CLKM1 1 -+#define AR2315_PCICLK_PLLC_CLKC 2 -+#define AR2315_PCICLK_REF_CLK 3 -+ -+#define AR2315_PCICLK_DIV_M 0xc -+#define AR2315_PCICLK_DIV_S 2 -+ -+#define AR2315_PCICLK_IN_FREQ 0 -+#define AR2315_PCICLK_IN_FREQ_DIV_6 1 -+#define AR2315_PCICLK_IN_FREQ_DIV_8 2 -+#define AR2315_PCICLK_IN_FREQ_DIV_10 3 -+ -+/* -+ * Observation Control Register -+ */ -+#define AR2315_OCR (AR2315_DSLBASE + 0x00b0) -+#define OCR_GPIO0_IRIN 0x0040 -+#define OCR_GPIO1_IROUT 0x0080 -+#define OCR_GPIO3_RXCLR 0x0200 -+ -+/* -+ * General Clock Control -+ */ -+ -+#define AR2315_MISCCLK (AR2315_DSLBASE + 0x00b4) -+#define MISCCLK_PLLBYPASS_EN 0x00000001 -+#define MISCCLK_PROCREFCLK 0x00000002 -+ -+/* -+ * SDRAM Controller -+ * - No read or write buffers are included. -+ */ -+#define AR2315_MEM_CFG (AR2315_SDRAMCTL + 0x00) -+#define AR2315_MEM_CTRL (AR2315_SDRAMCTL + 0x0c) -+#define AR2315_MEM_REF (AR2315_SDRAMCTL + 0x10) -+ -+#define SDRAM_DATA_WIDTH_M 0x00006000 -+#define SDRAM_DATA_WIDTH_S 13 -+ -+#define SDRAM_COL_WIDTH_M 0x00001E00 -+#define SDRAM_COL_WIDTH_S 9 -+ -+#define SDRAM_ROW_WIDTH_M 0x000001E0 -+#define SDRAM_ROW_WIDTH_S 5 -+ -+#define SDRAM_BANKADDR_BITS_M 0x00000018 -+#define SDRAM_BANKADDR_BITS_S 3 -+ -+/* -+ * SPI Flash Interface Registers -+ */ -+ -+#define AR2315_SPI_CTL (AR2315_SPI + 0x00) -+#define AR2315_SPI_OPCODE (AR2315_SPI + 0x04) -+#define AR2315_SPI_DATA (AR2315_SPI + 0x08) -+ -+#define SPI_CTL_START 0x00000100 -+#define SPI_CTL_BUSY 0x00010000 -+#define SPI_CTL_TXCNT_MASK 0x0000000f -+#define SPI_CTL_RXCNT_MASK 0x000000f0 -+#define SPI_CTL_TX_RX_CNT_MASK 0x000000ff -+#define SPI_CTL_SIZE_MASK 0x00060000 -+ -+#define SPI_CTL_CLK_SEL_MASK 0x03000000 -+#define SPI_OPCODE_MASK 0x000000ff -+ -+/* -+ * PCI Bus Interface Registers -+ */ -+#define AR2315_PCI_1MS_REG (AR2315_PCI + 0x0008) -+#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */ -+ -+#define AR2315_PCI_MISC_CONFIG (AR2315_PCI + 0x000c) -+#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */ -+#define AR2315_PCIMISC_CFG_SEL 0x00000002 /* mem or config cycles */ -+#define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */ -+#define AR2315_PCIMISC_RST_MODE 0x00000030 -+#define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */ -+#define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */ -+#define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */ -+#define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */ -+#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */ -+#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */ -+#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */ -+#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache disable */ -+ -+#define AR2315_PCI_OUT_TSTAMP (AR2315_PCI + 0x0010) -+ -+#define AR2315_PCI_UNCACHE_CFG (AR2315_PCI + 0x0014) -+ -+#define AR2315_PCI_IN_EN (AR2315_PCI + 0x0100) -+#define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */ -+#define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */ -+#define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */ -+#define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */ -+ -+#define AR2315_PCI_IN_DIS (AR2315_PCI + 0x0104) -+#define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */ -+#define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */ -+#define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */ -+#define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */ -+ -+#define AR2315_PCI_IN_PTR (AR2315_PCI + 0x0200) -+ -+#define AR2315_PCI_OUT_EN (AR2315_PCI + 0x0400) -+#define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */ -+ -+#define AR2315_PCI_OUT_DIS (AR2315_PCI + 0x0404) -+#define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */ -+ -+#define AR2315_PCI_OUT_PTR (AR2315_PCI + 0x0408) -+ -+#define AR2315_PCI_INT_STATUS (AR2315_PCI + 0x0500) /* write one to clr */ -+#define AR2315_PCI_TXINT 0x00000001 /* Desc In Completed */ -+#define AR2315_PCI_TXOK 0x00000002 /* Desc In OK */ -+#define AR2315_PCI_TXERR 0x00000004 /* Desc In ERR */ -+#define AR2315_PCI_TXEOL 0x00000008 /* Desc In End-of-List */ -+#define AR2315_PCI_RXINT 0x00000010 /* Desc Out Completed */ -+#define AR2315_PCI_RXOK 0x00000020 /* Desc Out OK */ -+#define AR2315_PCI_RXERR 0x00000040 /* Desc Out ERR */ -+#define AR2315_PCI_RXEOL 0x00000080 /* Desc Out EOL */ -+#define AR2315_PCI_TXOOD 0x00000200 /* Desc In Out-of-Desc */ -+#define AR2315_PCI_MASK 0x0000FFFF /* Desc Mask */ -+#define AR2315_PCI_EXT_INT 0x02000000 -+#define AR2315_PCI_ABORT_INT 0x04000000 -+ -+#define AR2315_PCI_INT_MASK (AR2315_PCI + 0x0504) /* same as INT_STATUS */ -+ -+#define AR2315_PCI_INTEN_REG (AR2315_PCI + 0x0508) -+#define AR2315_PCI_INT_DISABLE 0x00 /* disable pci interrupts */ -+#define AR2315_PCI_INT_ENABLE 0x01 /* enable pci interrupts */ -+ -+#define AR2315_PCI_HOST_IN_EN (AR2315_PCI + 0x0800) -+#define AR2315_PCI_HOST_IN_DIS (AR2315_PCI + 0x0804) -+#define AR2315_PCI_HOST_IN_PTR (AR2315_PCI + 0x0810) -+#define AR2315_PCI_HOST_OUT_EN (AR2315_PCI + 0x0900) -+#define AR2315_PCI_HOST_OUT_DIS (AR2315_PCI + 0x0904) -+#define AR2315_PCI_HOST_OUT_PTR (AR2315_PCI + 0x0908) -+ -+ -+/* -+ * Local Bus Interface Registers -+ */ -+#define AR2315_LB_CONFIG (AR2315_LOCAL + 0x0000) -+#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */ -+#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */ -+#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */ -+#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */ -+#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */ -+#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */ -+#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */ -+#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */ -+#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */ -+#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */ -+#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */ -+#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */ -+#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */ -+#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */ -+#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */ -+#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */ -+#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */ -+#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */ -+#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */ -+#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */ -+#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */ -+#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */ -+#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */ -+#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */ -+#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */ -+ -+#define AR2315_LB_CLKSEL (AR2315_LOCAL + 0x0004) -+#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */ -+ -+#define AR2315_LB_1MS (AR2315_LOCAL + 0x0008) -+#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */ -+ -+#define AR2315_LB_MISCCFG (AR2315_LOCAL + 0x000C) -+#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */ -+#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */ -+#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */ -+#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */ -+#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */ -+#define AR2315_LBM_TIMEOUT_MASK 0x00FFFF80 -+#define AR2315_LBM_TIMEOUT_SHFT 7 -+#define AR2315_LBM_PORTMUX 0x07000000 -+ -+ -+#define AR2315_LB_RXTSOFF (AR2315_LOCAL + 0x0010) -+ -+#define AR2315_LB_TX_CHAIN_EN (AR2315_LOCAL + 0x0100) -+#define AR2315_LB_TXEN_0 0x01 -+#define AR2315_LB_TXEN_1 0x02 -+#define AR2315_LB_TXEN_2 0x04 -+#define AR2315_LB_TXEN_3 0x08 -+ -+#define AR2315_LB_TX_CHAIN_DIS (AR2315_LOCAL + 0x0104) -+#define AR2315_LB_TX_DESC_PTR (AR2315_LOCAL + 0x0200) -+ -+#define AR2315_LB_RX_CHAIN_EN (AR2315_LOCAL + 0x0400) -+#define AR2315_LB_RXEN 0x01 -+ -+#define AR2315_LB_RX_CHAIN_DIS (AR2315_LOCAL + 0x0404) -+#define AR2315_LB_RX_DESC_PTR (AR2315_LOCAL + 0x0408) -+ -+#define AR2315_LB_INT_STATUS (AR2315_LOCAL + 0x0500) -+#define AR2315_INT_TX_DESC 0x0001 -+#define AR2315_INT_TX_OK 0x0002 -+#define AR2315_INT_TX_ERR 0x0004 -+#define AR2315_INT_TX_EOF 0x0008 -+#define AR2315_INT_RX_DESC 0x0010 -+#define AR2315_INT_RX_OK 0x0020 -+#define AR2315_INT_RX_ERR 0x0040 -+#define AR2315_INT_RX_EOF 0x0080 -+#define AR2315_INT_TX_TRUNC 0x0100 -+#define AR2315_INT_TX_STARVE 0x0200 -+#define AR2315_INT_LB_TIMEOUT 0x0400 -+#define AR2315_INT_LB_ERR 0x0800 -+#define AR2315_INT_MBOX_WR 0x1000 -+#define AR2315_INT_MBOX_RD 0x2000 -+ -+/* Bit definitions for INT MASK are the same as INT_STATUS */ -+#define AR2315_LB_INT_MASK (AR2315_LOCAL + 0x0504) -+ -+#define AR2315_LB_INT_EN (AR2315_LOCAL + 0x0508) -+#define AR2315_LB_MBOX (AR2315_LOCAL + 0x0600) -+ -+/* -+ * IR Interface Registers -+ */ -+#define AR2315_IR_PKTDATA (AR2315_IR + 0x0000) -+ -+#define AR2315_IR_PKTLEN (AR2315_IR + 0x07fc) /* 0 - 63 */ -+ -+#define AR2315_IR_CONTROL (AR2315_IR + 0x0800) -+#define AR2315_IRCTL_TX 0x00000000 /* use as tranmitter */ -+#define AR2315_IRCTL_RX 0x00000001 /* use as receiver */ -+#define AR2315_IRCTL_SAMPLECLK_MASK 0x00003ffe /* Sample clk divisor mask */ -+#define AR2315_IRCTL_SAMPLECLK_SHFT 1 -+#define AR2315_IRCTL_OUTPUTCLK_MASK 0x03ffc000 /* Output clk divisor mask */ -+#define AR2315_IRCTL_OUTPUTCLK_SHFT 14 -+ -+#define AR2315_IR_STATUS (AR2315_IR + 0x0804) -+#define AR2315_IRSTS_RX 0x00000001 /* receive in progress */ -+#define AR2315_IRSTS_TX 0x00000002 /* transmit in progress */ -+ -+#define AR2315_IR_CONFIG (AR2315_IR + 0x0808) -+#define AR2315_IRCFG_INVIN 0x00000001 /* invert input polarity */ -+#define AR2315_IRCFG_INVOUT 0x00000002 /* invert output polarity */ -+#define AR2315_IRCFG_SEQ_START_WIN_SEL 0x00000004 /* 1 => 28, 0 => 7 */ -+#define AR2315_IRCFG_SEQ_START_THRESH 0x000000f0 /* */ -+#define AR2315_IRCFG_SEQ_END_UNIT_SEL 0x00000100 /* */ -+#define AR2315_IRCFG_SEQ_END_UNIT_THRESH 0x00007e00 /* */ -+#define AR2315_IRCFG_SEQ_END_WIN_SEL 0x00008000 /* */ -+#define AR2315_IRCFG_SEQ_END_WIN_THRESH 0x001f0000 /* */ -+#define AR2315_IRCFG_NUM_BACKOFF_WORDS 0x01e00000 /* */ -+ -+#define HOST_PCI_DEV_ID 3 -+#define HOST_PCI_MBAR0 0x10000000 -+#define HOST_PCI_MBAR1 0x20000000 -+#define HOST_PCI_MBAR2 0x30000000 -+ -+#define HOST_PCI_SDRAM_BASEADDR HOST_PCI_MBAR1 -+#define PCI_DEVICE_MEM_SPACE 0x800000 -+ -+#endif /* __AR2315_REG_H */ -diff -Nur linux-2.6.37.orig/arch/mips/include/asm/mach-ar231x/ar2315_spiflash.h linux-2.6.37/arch/mips/include/asm/mach-ar231x/ar2315_spiflash.h ---- linux-2.6.37.orig/arch/mips/include/asm/mach-ar231x/ar2315_spiflash.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/include/asm/mach-ar231x/ar2315_spiflash.h 2011-05-15 19:24:57.000000000 +0200 -@@ -0,0 +1,116 @@ -+/* -+ * SPI Flash Memory support header file. -+ * -+ * Copyright (c) 2005, Atheros Communications Inc. -+ * Copyright (C) 2006 FON Technology, SL. -+ * Copyright (C) 2006 Imre Kaloz -+ * Copyright (C) 2006-2009 Felix Fietkau -+ * -+ * This code is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ */ -+#ifndef __AR2315_SPIFLASH_H -+#define __AR2315_SPIFLASH_H -+ -+#define STM_PAGE_SIZE 256 -+ -+#define SFI_WRITE_BUFFER_SIZE 4 -+#define SFI_FLASH_ADDR_MASK 0x00ffffff -+ -+#define STM_8MBIT_SIGNATURE 0x13 -+#define STM_M25P80_BYTE_COUNT 1048576 -+#define STM_M25P80_SECTOR_COUNT 16 -+#define STM_M25P80_SECTOR_SIZE 0x10000 -+ -+#define STM_16MBIT_SIGNATURE 0x14 -+#define STM_M25P16_BYTE_COUNT 2097152 -+#define STM_M25P16_SECTOR_COUNT 32 -+#define STM_M25P16_SECTOR_SIZE 0x10000 -+ -+#define STM_32MBIT_SIGNATURE 0x15 -+#define STM_M25P32_BYTE_COUNT 4194304 -+#define STM_M25P32_SECTOR_COUNT 64 -+#define STM_M25P32_SECTOR_SIZE 0x10000 -+ -+#define STM_64MBIT_SIGNATURE 0x16 -+#define STM_M25P64_BYTE_COUNT 8388608 -+#define STM_M25P64_SECTOR_COUNT 128 -+#define STM_M25P64_SECTOR_SIZE 0x10000 -+ -+#define STM_128MBIT_SIGNATURE 0x17 -+#define STM_M25P128_BYTE_COUNT 16777216 -+#define STM_M25P128_SECTOR_COUNT 256 -+#define STM_M25P128_SECTOR_SIZE 0x10000 -+ -+#define STM_1MB_BYTE_COUNT STM_M25P80_BYTE_COUNT -+#define STM_1MB_SECTOR_COUNT STM_M25P80_SECTOR_COUNT -+#define STM_1MB_SECTOR_SIZE STM_M25P80_SECTOR_SIZE -+#define STM_2MB_BYTE_COUNT STM_M25P16_BYTE_COUNT -+#define STM_2MB_SECTOR_COUNT STM_M25P16_SECTOR_COUNT -+#define STM_2MB_SECTOR_SIZE STM_M25P16_SECTOR_SIZE -+#define STM_4MB_BYTE_COUNT STM_M25P32_BYTE_COUNT -+#define STM_4MB_SECTOR_COUNT STM_M25P32_SECTOR_COUNT -+#define STM_4MB_SECTOR_SIZE STM_M25P32_SECTOR_SIZE -+#define STM_8MB_BYTE_COUNT STM_M25P64_BYTE_COUNT -+#define STM_8MB_SECTOR_COUNT STM_M25P64_SECTOR_COUNT -+#define STM_8MB_SECTOR_SIZE STM_M25P64_SECTOR_SIZE -+#define STM_16MB_BYTE_COUNT STM_M25P128_BYTE_COUNT -+#define STM_16MB_SECTOR_COUNT STM_M25P128_SECTOR_COUNT -+#define STM_16MB_SECTOR_SIZE STM_M25P128_SECTOR_SIZE -+ -+/* -+ * ST Microelectronics Opcodes for Serial Flash -+ */ -+ -+#define STM_OP_WR_ENABLE 0x06 /* Write Enable */ -+#define STM_OP_WR_DISABLE 0x04 /* Write Disable */ -+#define STM_OP_RD_STATUS 0x05 /* Read Status */ -+#define STM_OP_WR_STATUS 0x01 /* Write Status */ -+#define STM_OP_RD_DATA 0x03 /* Read Data */ -+#define STM_OP_FAST_RD_DATA 0x0b /* Fast Read Data */ -+#define STM_OP_PAGE_PGRM 0x02 /* Page Program */ -+#define STM_OP_SECTOR_ERASE 0xd8 /* Sector Erase */ -+#define STM_OP_BULK_ERASE 0xc7 /* Bulk Erase */ -+#define STM_OP_DEEP_PWRDOWN 0xb9 /* Deep Power-Down Mode */ -+#define STM_OP_RD_SIG 0xab /* Read Electronic Signature */ -+ -+#define STM_STATUS_WIP 0x01 /* Write-In-Progress */ -+#define STM_STATUS_WEL 0x02 /* Write Enable Latch */ -+#define STM_STATUS_BP0 0x04 /* Block Protect 0 */ -+#define STM_STATUS_BP1 0x08 /* Block Protect 1 */ -+#define STM_STATUS_BP2 0x10 /* Block Protect 2 */ -+#define STM_STATUS_SRWD 0x80 /* Status Register Write Disable */ -+ -+/* -+ * SPI Flash Interface Registers -+ */ -+#define AR531XPLUS_SPI_READ 0x08000000 -+#define AR531XPLUS_SPI_MMR 0x11300000 -+#define AR531XPLUS_SPI_MMR_SIZE 12 -+ -+#define AR531XPLUS_SPI_CTL 0x00 -+#define AR531XPLUS_SPI_OPCODE 0x04 -+#define AR531XPLUS_SPI_DATA 0x08 -+ -+#define SPI_FLASH_READ AR531XPLUS_SPI_READ -+#define SPI_FLASH_MMR AR531XPLUS_SPI_MMR -+#define SPI_FLASH_MMR_SIZE AR531XPLUS_SPI_MMR_SIZE -+#define SPI_FLASH_CTL AR531XPLUS_SPI_CTL -+#define SPI_FLASH_OPCODE AR531XPLUS_SPI_OPCODE -+#define SPI_FLASH_DATA AR531XPLUS_SPI_DATA -+ -+#define SPI_CTL_START 0x00000100 -+#define SPI_CTL_BUSY 0x00010000 -+#define SPI_CTL_TXCNT_MASK 0x0000000f -+#define SPI_CTL_RXCNT_MASK 0x000000f0 -+#define SPI_CTL_TX_RX_CNT_MASK 0x000000ff -+#define SPI_CTL_SIZE_MASK 0x00060000 -+ -+#define SPI_CTL_CLK_SEL_MASK 0x03000000 -+#define SPI_OPCODE_MASK 0x000000ff -+ -+#define SPI_STATUS_WIP STM_STATUS_WIP -+ -+#endif -diff -Nur linux-2.6.37.orig/arch/mips/include/asm/mach-ar231x/ar231x.h linux-2.6.37/arch/mips/include/asm/mach-ar231x/ar231x.h ---- linux-2.6.37.orig/arch/mips/include/asm/mach-ar231x/ar231x.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/include/asm/mach-ar231x/ar231x.h 2011-05-15 19:24:57.000000000 +0200 -@@ -0,0 +1,54 @@ -+#ifndef __AR531X_H -+#define __AR531X_H -+ -+#define AR531X_MISC_IRQ_BASE 0x20 -+#define AR531X_GPIO_IRQ_BASE 0x30 -+ -+/* Software's idea of interrupts handled by "CPU Interrupt Controller" */ -+#define AR531X_IRQ_NONE MIPS_CPU_IRQ_BASE+0 -+#define AR531X_IRQ_CPU_CLOCK MIPS_CPU_IRQ_BASE+7 /* C0_CAUSE: 0x8000 */ -+ -+/* Miscellaneous interrupts, which share IP6 */ -+#define AR531X_MISC_IRQ_NONE AR531X_MISC_IRQ_BASE+0 -+#define AR531X_MISC_IRQ_TIMER AR531X_MISC_IRQ_BASE+1 -+#define AR531X_MISC_IRQ_AHB_PROC AR531X_MISC_IRQ_BASE+2 -+#define AR531X_MISC_IRQ_AHB_DMA AR531X_MISC_IRQ_BASE+3 -+#define AR531X_MISC_IRQ_GPIO AR531X_MISC_IRQ_BASE+4 -+#define AR531X_MISC_IRQ_UART0 AR531X_MISC_IRQ_BASE+5 -+#define AR531X_MISC_IRQ_UART0_DMA AR531X_MISC_IRQ_BASE+6 -+#define AR531X_MISC_IRQ_WATCHDOG AR531X_MISC_IRQ_BASE+7 -+#define AR531X_MISC_IRQ_LOCAL AR531X_MISC_IRQ_BASE+8 -+#define AR531X_MISC_IRQ_SPI AR531X_MISC_IRQ_BASE+9 -+#define AR531X_MISC_IRQ_COUNT 10 -+ -+/* GPIO Interrupts [0..7], share AR531X_MISC_IRQ_GPIO */ -+#define AR531X_GPIO_IRQ_NONE AR531X_GPIO_IRQ_BASE+0 -+#define AR531X_GPIO_IRQ(n) AR531X_GPIO_IRQ_BASE+n -+#define AR531X_GPIO_IRQ_COUNT 22 -+ -+static inline u32 -+ar231x_read_reg(u32 reg) -+{ -+ return __raw_readl((u32 *) KSEG1ADDR(reg)); -+} -+ -+static inline void -+ar231x_write_reg(u32 reg, u32 val) -+{ -+ __raw_writel(val, (u32 *) KSEG1ADDR(reg)); -+} -+ -+static inline u32 -+ar231x_mask_reg(u32 reg, u32 mask, u32 val) -+{ -+ u32 ret; -+ -+ ret = ar231x_read_reg(reg); -+ ret &= ~mask; -+ ret |= val; -+ ar231x_write_reg(reg, ret); -+ -+ return ret; -+} -+ -+#endif -diff -Nur linux-2.6.37.orig/arch/mips/include/asm/mach-ar231x/ar231x_platform.h linux-2.6.37/arch/mips/include/asm/mach-ar231x/ar231x_platform.h ---- linux-2.6.37.orig/arch/mips/include/asm/mach-ar231x/ar231x_platform.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/include/asm/mach-ar231x/ar231x_platform.h 2011-05-15 19:24:57.000000000 +0200 -@@ -0,0 +1,83 @@ -+#ifndef __AR531X_PLATFORM_H -+#define __AR531X_PLATFORM_H -+ -+/* -+ * This is board-specific data that is stored in a "fixed" location in flash. -+ * It is shared across operating systems, so it should not be changed lightly. -+ * The main reason we need it is in order to extract the ethernet MAC -+ * address(es). -+ */ -+struct ar231x_boarddata { -+ u32 magic; /* board data is valid */ -+#define AR531X_BD_MAGIC 0x35333131 /* "5311", for all 531x platforms */ -+ u16 cksum; /* checksum (starting with BD_REV 2) */ -+ u16 rev; /* revision of this struct */ -+#define BD_REV 4 -+ char boardName[64]; /* Name of board */ -+ u16 major; /* Board major number */ -+ u16 minor; /* Board minor number */ -+ u32 flags; /* Board configuration */ -+#define BD_ENET0 0x00000001 /* ENET0 is stuffed */ -+#define BD_ENET1 0x00000002 /* ENET1 is stuffed */ -+#define BD_UART1 0x00000004 /* UART1 is stuffed */ -+#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */ -+#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */ -+#define BD_SYSLED 0x00000020 /* System LED stuffed */ -+#define BD_EXTUARTCLK 0x00000040 /* External UART clock */ -+#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */ -+#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */ -+#define BD_WLAN0 0x00000200 /* Enable WLAN0 */ -+#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ memCap for testing */ -+#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */ -+#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */ -+#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */ -+#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */ -+#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */ -+#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */ -+#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */ -+ u16 resetConfigGpio; /* Reset factory GPIO pin */ -+ u16 sysLedGpio; /* System LED GPIO pin */ -+ -+ u32 cpuFreq; /* CPU core frequency in Hz */ -+ u32 sysFreq; /* System frequency in Hz */ -+ u32 cntFreq; /* Calculated C0_COUNT frequency */ -+ -+ u8 wlan0_mac[6]; -+ u8 enet0_mac[6]; -+ u8 enet1_mac[6]; -+ -+ u16 pciId; /* Pseudo PCIID for common code */ -+ u16 memCap; /* cap bank1 in MB */ -+ -+ /* version 3 */ -+ u8 wlan1_mac[6]; /* (ar5212) */ -+}; -+ -+#define BOARD_CONFIG_BUFSZ 0x1000 -+ -+/* -+ * Platform device information for the Wireless MAC -+ */ -+struct ar231x_board_config { -+ u16 devid; -+ -+ /* board config data */ -+ struct ar231x_boarddata *config; -+ -+ /* radio calibration data */ -+ const char *radio; -+}; -+ -+/* -+ * Platform device information for the Ethernet MAC -+ */ -+struct ar231x_eth { -+ u32 reset_base; -+ u32 reset_mac; -+ u32 reset_phy; -+ u32 phy_base; -+ struct ar231x_board_config *config; -+ char *macaddr; -+}; -+ -+#endif /* __AR531X_PLATFORM_H */ -diff -Nur linux-2.6.37.orig/arch/mips/include/asm/mach-ar231x/ar5312_regs.h linux-2.6.37/arch/mips/include/asm/mach-ar231x/ar5312_regs.h ---- linux-2.6.37.orig/arch/mips/include/asm/mach-ar231x/ar5312_regs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/include/asm/mach-ar231x/ar5312_regs.h 2011-05-15 19:24:57.000000000 +0200 -@@ -0,0 +1,236 @@ -+/* -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. -+ * Copyright (C) 2006 Imre Kaloz -+ * Copyright (C) 2006 Felix Fietkau -+ */ -+ -+#ifndef AR5312_H -+#define AR5312_H -+ -+#include -+ -+/* -+ * IRQs -+ */ -+ -+#define AR5312_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */ -+#define AR5312_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */ -+#define AR5312_IRQ_ENET1_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */ -+#define AR5312_IRQ_WLAN1_INTRS MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */ -+#define AR5312_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */ -+ -+ -+/* Address Map */ -+#define AR531X_WLAN0 0x18000000 -+#define AR531X_WLAN1 0x18500000 -+#define AR531X_ENET0 0x18100000 -+#define AR531X_ENET1 0x18200000 -+#define AR531X_SDRAMCTL 0x18300000 -+#define AR531X_FLASHCTL 0x18400000 -+#define AR531X_APBBASE 0x1c000000 -+#define AR531X_FLASH 0x1e000000 -+#define AR531X_UART0 0xbc000003 /* UART MMR */ -+ -+/* -+ * AR531X_NUM_ENET_MAC defines the number of ethernet MACs that -+ * should be considered available. The AR5312 supports 2 enet MACS, -+ * even though many reference boards only actually use 1 of them -+ * (i.e. Only MAC 0 is actually connected to an enet PHY or PHY switch. -+ * The AR2312 supports 1 enet MAC. -+ */ -+#define AR531X_NUM_ENET_MAC 2 -+ -+/* -+ * Need these defines to determine true number of ethernet MACs -+ */ -+#define AR5212_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */ -+#define AR5212_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */ -+#define AR5212_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */ -+#define AR531X_RADIO_MASK_OFF 0xc8 -+#define AR531X_RADIO0_MASK 0x0003 -+#define AR531X_RADIO1_MASK 0x000c -+#define AR531X_RADIO1_S 2 -+ -+/* -+ * AR531X_NUM_WMAC defines the number of Wireless MACs that\ -+ * should be considered available. -+ */ -+#define AR531X_NUM_WMAC 2 -+ -+/* Reset/Timer Block Address Map */ -+#define AR531X_RESETTMR (AR531X_APBBASE + 0x3000) -+#define AR531X_TIMER (AR531X_RESETTMR + 0x0000) /* countdown timer */ -+#define AR531X_WD_CTRL (AR531X_RESETTMR + 0x0008) /* watchdog cntrl */ -+#define AR531X_WD_TIMER (AR531X_RESETTMR + 0x000c) /* watchdog timer */ -+#define AR531X_ISR (AR531X_RESETTMR + 0x0010) /* Intr Status Reg */ -+#define AR531X_IMR (AR531X_RESETTMR + 0x0014) /* Intr Mask Reg */ -+#define AR531X_RESET (AR531X_RESETTMR + 0x0020) -+#define AR5312_CLOCKCTL1 (AR531X_RESETTMR + 0x0064) -+#define AR5312_SCRATCH (AR531X_RESETTMR + 0x006c) -+#define AR531X_PROCADDR (AR531X_RESETTMR + 0x0070) -+#define AR531X_PROC1 (AR531X_RESETTMR + 0x0074) -+#define AR531X_DMAADDR (AR531X_RESETTMR + 0x0078) -+#define AR531X_DMA1 (AR531X_RESETTMR + 0x007c) -+#define AR531X_ENABLE (AR531X_RESETTMR + 0x0080) /* interface enb */ -+#define AR531X_REV (AR531X_RESETTMR + 0x0090) /* revision */ -+ -+/* AR531X_WD_CTRL register bit field definitions */ -+#define AR531X_WD_CTRL_IGNORE_EXPIRATION 0x0000 -+#define AR531X_WD_CTRL_NMI 0x0001 -+#define AR531X_WD_CTRL_RESET 0x0002 -+ -+/* AR531X_ISR register bit field definitions */ -+#define AR531X_ISR_NONE 0x0000 -+#define AR531X_ISR_TIMER 0x0001 -+#define AR531X_ISR_AHBPROC 0x0002 -+#define AR531X_ISR_AHBDMA 0x0004 -+#define AR531X_ISR_GPIO 0x0008 -+#define AR531X_ISR_UART0 0x0010 -+#define AR531X_ISR_UART0DMA 0x0020 -+#define AR531X_ISR_WD 0x0040 -+#define AR531X_ISR_LOCAL 0x0080 -+ -+/* AR531X_RESET register bit field definitions */ -+#define AR531X_RESET_SYSTEM 0x00000001 /* cold reset full system */ -+#define AR531X_RESET_PROC 0x00000002 /* cold reset MIPS core */ -+#define AR531X_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */ -+#define AR531X_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */ -+#define AR531X_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */ -+#define AR531X_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */ -+#define AR531X_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */ -+#define AR531X_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */ -+#define AR531X_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */ -+#define AR531X_RESET_APB 0x00000400 /* cold reset APB (ar5312) */ -+#define AR531X_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */ -+#define AR531X_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */ -+#define AR531X_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */ -+#define AR531X_RESET_NMI 0x00010000 /* send an NMI to the processor */ -+#define AR531X_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */ -+#define AR531X_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */ -+#define AR531X_RESET_LOCAL_BUS 0x00080000 /* reset local bus */ -+#define AR531X_RESET_WDOG 0x00100000 /* last reset was a watchdog */ -+ -+#define AR531X_RESET_WMAC0_BITS \ -+ AR531X_RESET_WLAN0 |\ -+ AR531X_RESET_WARM_WLAN0_MAC |\ -+ AR531X_RESET_WARM_WLAN0_BB -+ -+#define AR531X_RESERT_WMAC1_BITS \ -+ AR531X_RESET_WLAN1 |\ -+ AR531X_RESET_WARM_WLAN1_MAC |\ -+ AR531X_RESET_WARM_WLAN1_BB -+ -+/* AR5312_CLOCKCTL1 register bit field definitions */ -+#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030 -+#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4 -+#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00 -+#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8 -+#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000 -+ -+/* Valid for AR5312 and AR2312 */ -+#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030 -+#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4 -+#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00 -+#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8 -+#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000 -+ -+/* Valid for AR2313 */ -+#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000 -+#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12 -+#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000 -+#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16 -+#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000 -+ -+ -+/* AR531X_ENABLE register bit field definitions */ -+#define AR531X_ENABLE_WLAN0 0x0001 -+#define AR531X_ENABLE_ENET0 0x0002 -+#define AR531X_ENABLE_ENET1 0x0004 -+#define AR531X_ENABLE_UART_AND_WLAN1_PIO 0x0008 /* UART, and WLAN1 PIOs */ -+#define AR531X_ENABLE_WLAN1_DMA 0x0010 /* WLAN1 DMAs */ -+#define AR531X_ENABLE_WLAN1 \ -+ (AR531X_ENABLE_UART_AND_WLAN1_PIO | AR531X_ENABLE_WLAN1_DMA) -+ -+/* AR531X_REV register bit field definitions */ -+#define AR531X_REV_WMAC_MAJ 0xf000 -+#define AR531X_REV_WMAC_MAJ_S 12 -+#define AR531X_REV_WMAC_MIN 0x0f00 -+#define AR531X_REV_WMAC_MIN_S 8 -+#define AR531X_REV_MAJ 0x00f0 -+#define AR531X_REV_MAJ_S 4 -+#define AR531X_REV_MIN 0x000f -+#define AR531X_REV_MIN_S 0 -+#define AR531X_REV_CHIP (AR531X_REV_MAJ|AR531X_REV_MIN) -+ -+/* Major revision numbers, bits 7..4 of Revision ID register */ -+#define AR531X_REV_MAJ_AR5312 0x4 -+#define AR531X_REV_MAJ_AR2313 0x5 -+ -+/* Minor revision numbers, bits 3..0 of Revision ID register */ -+#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */ -+#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */ -+ -+/* AR531X_FLASHCTL register bit field definitions */ -+#define FLASHCTL_IDCY 0x0000000f /* Idle cycle turn around time */ -+#define FLASHCTL_IDCY_S 0 -+#define FLASHCTL_WST1 0x000003e0 /* Wait state 1 */ -+#define FLASHCTL_WST1_S 5 -+#define FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */ -+#define FLASHCTL_WST2 0x0000f800 /* Wait state 2 */ -+#define FLASHCTL_WST2_S 11 -+#define FLASHCTL_AC 0x00070000 /* Flash address check (added) */ -+#define FLASHCTL_AC_S 16 -+#define FLASHCTL_AC_128K 0x00000000 -+#define FLASHCTL_AC_256K 0x00010000 -+#define FLASHCTL_AC_512K 0x00020000 -+#define FLASHCTL_AC_1M 0x00030000 -+#define FLASHCTL_AC_2M 0x00040000 -+#define FLASHCTL_AC_4M 0x00050000 -+#define FLASHCTL_AC_8M 0x00060000 -+#define FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */ -+#define FLASHCTL_E 0x00080000 /* Flash bank enable (added) */ -+#define FLASHCTL_BUSERR 0x01000000 /* Bus transfer error status flag */ -+#define FLASHCTL_WPERR 0x02000000 /* Write protect error status flag */ -+#define FLASHCTL_WP 0x04000000 /* Write protect */ -+#define FLASHCTL_BM 0x08000000 /* Burst mode */ -+#define FLASHCTL_MW 0x30000000 /* Memory width */ -+#define FLASHCTL_MWx8 0x00000000 /* Memory width x8 */ -+#define FLASHCTL_MWx16 0x10000000 /* Memory width x16 */ -+#define FLASHCTL_MWx32 0x20000000 /* Memory width x32 (not supported) */ -+#define FLASHCTL_ATNR 0x00000000 /* Access type == no retry */ -+#define FLASHCTL_ATR 0x80000000 /* Access type == retry every */ -+#define FLASHCTL_ATR4 0xc0000000 /* Access type == retry every 4 */ -+ -+/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */ -+#define AR531X_FLASHCTL0 (AR531X_FLASHCTL + 0x00) -+#define AR531X_FLASHCTL1 (AR531X_FLASHCTL + 0x04) -+#define AR531X_FLASHCTL2 (AR531X_FLASHCTL + 0x08) -+ -+/* ARM SDRAM Controller -- just enough to determine memory size */ -+#define AR531X_MEM_CFG1 (AR531X_SDRAMCTL + 0x04) -+#define MEM_CFG1_AC0 0x00000700 /* bank 0: SDRAM addr check (added) */ -+#define MEM_CFG1_AC0_S 8 -+#define MEM_CFG1_AC1 0x00007000 /* bank 1: SDRAM addr check (added) */ -+#define MEM_CFG1_AC1_S 12 -+ -+/* GPIO Address Map */ -+#define AR531X_GPIO (AR531X_APBBASE + 0x2000) -+#define AR531X_GPIO_DO (AR531X_GPIO + 0x00) /* output register */ -+#define AR531X_GPIO_DI (AR531X_GPIO + 0x04) /* intput register */ -+#define AR531X_GPIO_CR (AR531X_GPIO + 0x08) /* control register */ -+ -+/* GPIO Control Register bit field definitions */ -+#define AR531X_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */ -+#define AR531X_GPIO_CR_O(x) (0 << (x)) /* mask for output */ -+#define AR531X_GPIO_CR_I(x) (1 << (x)) /* mask for input */ -+#define AR531X_GPIO_CR_INT(x) (1 << ((x)+8)) /* mask for interrupt */ -+#define AR531X_GPIO_CR_UART(x) (1 << ((x)+16)) /* uart multiplex */ -+#define AR531X_NUM_GPIO 8 -+ -+ -+#endif -+ -diff -Nur linux-2.6.37.orig/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h linux-2.6.37/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h ---- linux-2.6.37.orig/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h 2011-05-15 19:24:57.000000000 +0200 -@@ -0,0 +1,84 @@ -+/* -+ * Atheros SoC specific CPU feature overrides -+ * -+ * Copyright (C) 2008 Gabor Juhos -+ * -+ * This file was derived from: include/asm-mips/cpu-features.h -+ * Copyright (C) 2003, 2004 Ralf Baechle -+ * Copyright (C) 2004 Maciej W. Rozycki -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ */ -+#ifndef __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H -+#define __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H -+ -+/* -+ * The ATHEROS SoCs have MIPS 4Kc/4KEc core. -+ */ -+#define cpu_has_tlb 1 -+#define cpu_has_4kex 1 -+#define cpu_has_3k_cache 0 -+#define cpu_has_4k_cache 1 -+#define cpu_has_tx39_cache 0 -+#define cpu_has_sb1_cache 0 -+#define cpu_has_fpu 0 -+#define cpu_has_32fpr 0 -+#define cpu_has_counter 1 -+/* #define cpu_has_watch ? */ -+/* #define cpu_has_divec ? */ -+/* #define cpu_has_vce ? */ -+/* #define cpu_has_cache_cdex_p ? */ -+/* #define cpu_has_cache_cdex_s ? */ -+/* #define cpu_has_prefetch ? */ -+/* #define cpu_has_mcheck ? */ -+#define cpu_has_ejtag 1 -+ -+#if !defined(CONFIG_ATHEROS_AR5312) -+# define cpu_has_llsc 1 -+#else -+/* -+ * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the -+ * ll/sc instructions. -+ */ -+# define cpu_has_llsc 0 -+#endif -+ -+#define cpu_has_mips16 0 -+#define cpu_has_mdmx 0 -+#define cpu_has_mips3d 0 -+#define cpu_has_smartmips 0 -+ -+/* #define cpu_has_vtag_icache ? */ -+/* #define cpu_has_dc_aliases ? */ -+/* #define cpu_has_ic_fills_f_dc ? */ -+/* #define cpu_has_pindexed_dcache ? */ -+ -+/* #define cpu_icache_snoops_remote_store ? */ -+ -+#define cpu_has_mips32r1 1 -+ -+#if !defined(CONFIG_ATHEROS_AR5312) -+# define cpu_has_mips32r2 1 -+#endif -+ -+#define cpu_has_mips64r1 0 -+#define cpu_has_mips64r2 0 -+ -+#define cpu_has_dsp 0 -+#define cpu_has_mipsmt 0 -+ -+/* #define cpu_has_nofpuex ? */ -+#define cpu_has_64bits 0 -+#define cpu_has_64bit_zero_reg 0 -+#define cpu_has_64bit_gp_regs 0 -+#define cpu_has_64bit_addresses 0 -+ -+/* #define cpu_has_inclusive_pcaches ? */ -+ -+/* #define cpu_dcache_line_size() ? */ -+/* #define cpu_icache_line_size() ? */ -+ -+#endif /* __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H */ -diff -Nur linux-2.6.37.orig/arch/mips/include/asm/mach-ar231x/dma-coherence.h linux-2.6.37/arch/mips/include/asm/mach-ar231x/dma-coherence.h ---- linux-2.6.37.orig/arch/mips/include/asm/mach-ar231x/dma-coherence.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/include/asm/mach-ar231x/dma-coherence.h 2011-05-15 19:24:57.000000000 +0200 -@@ -0,0 +1,64 @@ -+/* -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 2006 Ralf Baechle -+ * Copyright (C) 2007 Felix Fietkau -+ * -+ */ -+#ifndef __ASM_MACH_GENERIC_DMA_COHERENCE_H -+#define __ASM_MACH_GENERIC_DMA_COHERENCE_H -+ -+#define PCI_DMA_OFFSET 0x20000000 -+ -+struct device; -+ -+static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size) -+{ -+ return virt_to_phys(addr) + (dev != NULL ? PCI_DMA_OFFSET : 0); -+} -+ -+static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page) -+{ -+ return page_to_phys(page) + (dev != NULL ? PCI_DMA_OFFSET : 0); -+} -+ -+static inline unsigned long plat_dma_addr_to_phys(struct device *dev, -+ dma_addr_t dma_addr) -+{ -+ return (dma_addr > PCI_DMA_OFFSET ? dma_addr - PCI_DMA_OFFSET : dma_addr); -+} -+ -+static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, -+ size_t size, enum dma_data_direction direction) -+{ -+} -+ -+static inline int plat_dma_supported(struct device *dev, u64 mask) -+{ -+ return 1; -+} -+ -+static inline void plat_extra_sync_for_device(struct device *dev) -+{ -+ return; -+} -+ -+static inline int plat_dma_mapping_error(struct device *dev, -+ dma_addr_t dma_addr) -+{ -+ return 0; -+} -+ -+static inline int plat_device_is_coherent(struct device *dev) -+{ -+#ifdef CONFIG_DMA_COHERENT -+ return 1; -+#endif -+#ifdef CONFIG_DMA_NONCOHERENT -+ return 0; -+#endif -+} -+ -+#endif /* __ASM_MACH_GENERIC_DMA_COHERENCE_H */ -diff -Nur linux-2.6.37.orig/arch/mips/include/asm/mach-ar231x/gpio.h linux-2.6.37/arch/mips/include/asm/mach-ar231x/gpio.h ---- linux-2.6.37.orig/arch/mips/include/asm/mach-ar231x/gpio.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/include/asm/mach-ar231x/gpio.h 2011-05-15 19:24:57.000000000 +0200 -@@ -0,0 +1,84 @@ -+#ifndef _ATHEROS_GPIO_H_ -+#define _ATHEROS_GPIO_H_ -+ -+#include -+ -+struct ar231x_gpiodev { -+ u32 valid_mask; -+ u32 (*get_output)(void); -+ u32 (*set_output)(u32 mask, u32 val); -+ u32 (*get)(void); -+ u32 (*set)(u32 mask, u32 val); -+}; -+ -+extern const struct ar231x_gpiodev *ar231x_gpiodev; -+ -+/* -+ * Wrappers for the generic GPIO layer -+ */ -+ -+static inline int gpio_direction_input(unsigned gpio) { -+ u32 mask = 1 << gpio; -+ -+ if (!(ar231x_gpiodev->valid_mask & mask)) -+ return -ENXIO; -+ -+ ar231x_gpiodev->set_output(mask, 0); -+ return 0; -+} -+ -+static inline void gpio_set_value(unsigned gpio, int value) { -+ u32 mask = 1 << gpio; -+ -+ if (!(ar231x_gpiodev->valid_mask & mask)) -+ return; -+ -+ ar231x_gpiodev->set(mask, (!!value) * mask); -+} -+ -+static inline int gpio_direction_output(unsigned gpio, int value) { -+ u32 mask = 1 << gpio; -+ -+ if (!(ar231x_gpiodev->valid_mask & mask)) -+ return -ENXIO; -+ -+ ar231x_gpiodev->set_output(mask, mask); -+ ar231x_gpiodev->set(mask, (!!value) * mask); -+ return 0; -+} -+ -+/* Reads the gpio pin. Unchecked function */ -+static inline int gpio_get_value(unsigned gpio) { -+ u32 mask = 1 << gpio; -+ -+ if (!(ar231x_gpiodev->valid_mask & mask)) -+ return 0; -+ -+ return !!(ar231x_gpiodev->get() & mask); -+} -+ -+static inline int gpio_request(unsigned gpio, const char *label) { -+ return 0; -+} -+ -+static inline void gpio_free(unsigned gpio) { -+} -+ -+/* Returns IRQ to attach for gpio. Unchecked function */ -+static inline int gpio_to_irq(unsigned gpio) { -+ return AR531X_GPIO_IRQ(gpio); -+} -+ -+/* Returns gpio for IRQ attached. Unchecked function */ -+static inline int irq_to_gpio(unsigned irq) { -+ return (irq - (AR531X_GPIO_IRQ(0))); -+} -+ -+static inline int gpio_set_debounce(unsigned gpio, unsigned debounce) -+{ -+ return -ENOSYS; -+} -+ -+#include /* cansleep wrappers */ -+ -+#endif -diff -Nur linux-2.6.37.orig/arch/mips/include/asm/mach-ar231x/reset.h linux-2.6.37/arch/mips/include/asm/mach-ar231x/reset.h ---- linux-2.6.37.orig/arch/mips/include/asm/mach-ar231x/reset.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/include/asm/mach-ar231x/reset.h 2011-05-15 19:24:57.000000000 +0200 -@@ -0,0 +1,6 @@ -+#ifndef __AR531X_RESET_H -+#define __AR531X_RESET_H -+ -+void ar531x_disable_reset_button(void); -+ -+#endif /* __AR531X_RESET_H */ -diff -Nur linux-2.6.37.orig/arch/mips/include/asm/mach-ar231x/war.h linux-2.6.37/arch/mips/include/asm/mach-ar231x/war.h ---- linux-2.6.37.orig/arch/mips/include/asm/mach-ar231x/war.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/include/asm/mach-ar231x/war.h 2011-05-15 19:24:57.000000000 +0200 -@@ -0,0 +1,25 @@ -+/* -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 2008 Felix Fietkau -+ */ -+#ifndef __ASM_MIPS_MACH_ATHEROS_WAR_H -+#define __ASM_MIPS_MACH_ATHEROS_WAR_H -+ -+#define R4600_V1_INDEX_ICACHEOP_WAR 0 -+#define R4600_V1_HIT_CACHEOP_WAR 0 -+#define R4600_V2_HIT_CACHEOP_WAR 0 -+#define R5432_CP0_INTERRUPT_WAR 0 -+#define BCM1250_M3_WAR 0 -+#define SIBYTE_1956_WAR 0 -+#define MIPS4K_ICACHE_REFILL_WAR 0 -+#define MIPS_CACHE_SYNC_WAR 0 -+#define TX49XX_ICACHE_INDEX_INV_WAR 0 -+#define RM9000_CDEX_SMP_WAR 0 -+#define ICACHE_REFILLS_WORKAROUND_WAR 0 -+#define R10000_LLSC_WAR 0 -+#define MIPS34K_MISSED_ITLB_WAR 0 -+ -+#endif /* __ASM_MIPS_MACH_ATHEROS_WAR_H */ -diff -Nur linux-2.6.37.orig/arch/mips/kernel/cevt-r4k.c linux-2.6.37/arch/mips/kernel/cevt-r4k.c ---- linux-2.6.37.orig/arch/mips/kernel/cevt-r4k.c 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/mips/kernel/cevt-r4k.c 2011-05-15 19:24:57.000000000 +0200 -@@ -168,20 +168,23 @@ - struct clock_event_device *cd; - unsigned int irq; - -- if (!cpu_has_counter || !mips_hpt_frequency) -- return -ENXIO; -- -- if (!c0_compare_int_usable()) -- return -ENXIO; -- - /* - * With vectored interrupts things are getting platform specific. - * get_c0_compare_int is a hook to allow a platform to return the - * interrupt number of it's liking. - */ - irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; -- if (get_c0_compare_int) -+ if (get_c0_compare_int) { - irq = get_c0_compare_int(); -+ if ((irq >= MIPS_CPU_IRQ_BASE) && (irq < MIPS_CPU_IRQ_BASE + 8)) -+ cp0_compare_irq = irq - MIPS_CPU_IRQ_BASE; -+ } -+ -+ if (!cpu_has_counter || !mips_hpt_frequency) -+ return -ENXIO; -+ -+ if (!c0_compare_int_usable()) -+ return -ENXIO; - - cd = &per_cpu(mips_clockevent_device, cpu); - -diff -Nur linux-2.6.37.orig/drivers/mtd/devices/Kconfig linux-2.6.37/drivers/mtd/devices/Kconfig ---- linux-2.6.37.orig/drivers/mtd/devices/Kconfig 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/mtd/devices/Kconfig 2011-05-15 19:24:57.000000000 +0200 -@@ -112,6 +112,10 @@ - Set up your spi devices with the right board-specific platform data, - if you want to specify device partitioning. - -+config MTD_AR2315 -+ tristate "Atheros AR2315+ SPI Flash support" -+ depends on ATHEROS_AR2315 -+ - config MTD_SLRAM - tristate "Uncached system RAM" - help -diff -Nur linux-2.6.37.orig/drivers/mtd/devices/Makefile linux-2.6.37/drivers/mtd/devices/Makefile ---- linux-2.6.37.orig/drivers/mtd/devices/Makefile 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/mtd/devices/Makefile 2011-05-15 19:24:57.000000000 +0200 -@@ -17,3 +17,4 @@ - obj-$(CONFIG_MTD_DATAFLASH) += mtd_dataflash.o - obj-$(CONFIG_MTD_M25P80) += m25p80.o - obj-$(CONFIG_MTD_SST25L) += sst25l.o -+obj-$(CONFIG_MTD_AR2315) += ar2315.o -diff -Nur linux-2.6.37.orig/drivers/mtd/devices/ar2315.c linux-2.6.37/drivers/mtd/devices/ar2315.c ---- linux-2.6.37.orig/drivers/mtd/devices/ar2315.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/drivers/mtd/devices/ar2315.c 2011-05-15 19:24:57.000000000 +0200 -@@ -0,0 +1,517 @@ -+ -+/* -+ * MTD driver for the SPI Flash Memory support on Atheros AR2315 -+ * -+ * Copyright (c) 2005-2006 Atheros Communications Inc. -+ * Copyright (C) 2006-2007 FON Technology, SL. -+ * Copyright (C) 2006-2007 Imre Kaloz -+ * Copyright (C) 2006-2009 Felix Fietkau -+ * -+ * This code is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+ -+#define SPIFLASH "spiflash: " -+#define busy_wait(_priv, _condition, _wait) do { \ -+ while (_condition) { \ -+ spin_unlock_bh(&_priv->lock); \ -+ if (_wait > 1) \ -+ msleep(_wait); \ -+ else if ((_wait == 1) && need_resched()) \ -+ schedule(); \ -+ else \ -+ udelay(1); \ -+ spin_lock_bh(&_priv->lock); \ -+ } \ -+} while (0) -+ -+enum { -+ FLASH_NONE, -+ FLASH_1MB, -+ FLASH_2MB, -+ FLASH_4MB, -+ FLASH_8MB, -+ FLASH_16MB, -+}; -+ -+/* Flash configuration table */ -+struct flashconfig { -+ u32 byte_cnt; -+ u32 sector_cnt; -+ u32 sector_size; -+}; -+ -+const struct flashconfig flashconfig_tbl[] = { -+ [FLASH_NONE] = { 0, 0, 0}, -+ [FLASH_1MB] = { STM_1MB_BYTE_COUNT, STM_1MB_SECTOR_COUNT, STM_1MB_SECTOR_SIZE}, -+ [FLASH_2MB] = { STM_2MB_BYTE_COUNT, STM_2MB_SECTOR_COUNT, STM_2MB_SECTOR_SIZE}, -+ [FLASH_4MB] = { STM_4MB_BYTE_COUNT, STM_4MB_SECTOR_COUNT, STM_4MB_SECTOR_SIZE}, -+ [FLASH_8MB] = { STM_8MB_BYTE_COUNT, STM_8MB_SECTOR_COUNT, STM_8MB_SECTOR_SIZE}, -+ [FLASH_16MB] = { STM_16MB_BYTE_COUNT, STM_16MB_SECTOR_COUNT, STM_16MB_SECTOR_SIZE} -+}; -+ -+/* Mapping of generic opcodes to STM serial flash opcodes */ -+enum { -+ SPI_WRITE_ENABLE, -+ SPI_WRITE_DISABLE, -+ SPI_RD_STATUS, -+ SPI_WR_STATUS, -+ SPI_RD_DATA, -+ SPI_FAST_RD_DATA, -+ SPI_PAGE_PROGRAM, -+ SPI_SECTOR_ERASE, -+ SPI_BULK_ERASE, -+ SPI_DEEP_PWRDOWN, -+ SPI_RD_SIG, -+}; -+ -+struct opcodes { -+ __u16 code; -+ __s8 tx_cnt; -+ __s8 rx_cnt; -+}; -+const struct opcodes stm_opcodes[] = { -+ [SPI_WRITE_ENABLE] = {STM_OP_WR_ENABLE, 1, 0}, -+ [SPI_WRITE_DISABLE] = {STM_OP_WR_DISABLE, 1, 0}, -+ [SPI_RD_STATUS] = {STM_OP_RD_STATUS, 1, 1}, -+ [SPI_WR_STATUS] = {STM_OP_WR_STATUS, 1, 0}, -+ [SPI_RD_DATA] = {STM_OP_RD_DATA, 4, 4}, -+ [SPI_FAST_RD_DATA] = {STM_OP_FAST_RD_DATA, 5, 0}, -+ [SPI_PAGE_PROGRAM] = {STM_OP_PAGE_PGRM, 8, 0}, -+ [SPI_SECTOR_ERASE] = {STM_OP_SECTOR_ERASE, 4, 0}, -+ [SPI_BULK_ERASE] = {STM_OP_BULK_ERASE, 1, 0}, -+ [SPI_DEEP_PWRDOWN] = {STM_OP_DEEP_PWRDOWN, 1, 0}, -+ [SPI_RD_SIG] = {STM_OP_RD_SIG, 4, 1}, -+}; -+ -+/* Driver private data structure */ -+struct spiflash_priv { -+ struct mtd_info mtd; -+ void *readaddr; /* memory mapped data for read */ -+ void *mmraddr; /* memory mapped register space */ -+ wait_queue_head_t wq; -+ spinlock_t lock; -+ int state; -+}; -+ -+#define to_spiflash(_mtd) container_of(_mtd, struct spiflash_priv, mtd) -+ -+enum { -+ FL_READY, -+ FL_READING, -+ FL_ERASING, -+ FL_WRITING -+}; -+ -+/***************************************************************************************************/ -+ -+static u32 -+spiflash_read_reg(struct spiflash_priv *priv, int reg) -+{ -+ return ar231x_read_reg((u32) priv->mmraddr + reg); -+} -+ -+static void -+spiflash_write_reg(struct spiflash_priv *priv, int reg, u32 data) -+{ -+ ar231x_write_reg((u32) priv->mmraddr + reg, data); -+} -+ -+static u32 -+spiflash_wait_busy(struct spiflash_priv *priv) -+{ -+ u32 reg; -+ -+ busy_wait(priv, (reg = spiflash_read_reg(priv, SPI_FLASH_CTL)) & -+ SPI_CTL_BUSY, 0); -+ return reg; -+} -+ -+static u32 -+spiflash_sendcmd (struct spiflash_priv *priv, int opcode, u32 addr) -+{ -+ const struct opcodes *op; -+ u32 reg, mask; -+ -+ op = &stm_opcodes[opcode]; -+ reg = spiflash_wait_busy(priv); -+ spiflash_write_reg(priv, SPI_FLASH_OPCODE, -+ ((u32) op->code) | (addr << 8)); -+ -+ reg &= ~SPI_CTL_TX_RX_CNT_MASK; -+ reg |= SPI_CTL_START | op->tx_cnt | (op->rx_cnt << 4); -+ -+ spiflash_write_reg(priv, SPI_FLASH_CTL, reg); -+ spiflash_wait_busy(priv); -+ -+ if (!op->rx_cnt) -+ return 0; -+ -+ reg = spiflash_read_reg(priv, SPI_FLASH_DATA); -+ -+ switch (op->rx_cnt) { -+ case 1: -+ mask = 0x000000ff; -+ break; -+ case 2: -+ mask = 0x0000ffff; -+ break; -+ case 3: -+ mask = 0x00ffffff; -+ break; -+ default: -+ mask = 0xffffffff; -+ break; -+ } -+ reg &= mask; -+ -+ return reg; -+} -+ -+ -+/* -+ * Probe SPI flash device -+ * Function returns 0 for failure. -+ * and flashconfig_tbl array index for success. -+ */ -+static int -+spiflash_probe_chip (struct spiflash_priv *priv) -+{ -+ u32 sig; -+ int flash_size; -+ -+ /* Read the signature on the flash device */ -+ spin_lock_bh(&priv->lock); -+ sig = spiflash_sendcmd(priv, SPI_RD_SIG, 0); -+ spin_unlock_bh(&priv->lock); -+ -+ switch (sig) { -+ case STM_8MBIT_SIGNATURE: -+ flash_size = FLASH_1MB; -+ break; -+ case STM_16MBIT_SIGNATURE: -+ flash_size = FLASH_2MB; -+ break; -+ case STM_32MBIT_SIGNATURE: -+ flash_size = FLASH_4MB; -+ break; -+ case STM_64MBIT_SIGNATURE: -+ flash_size = FLASH_8MB; -+ break; -+ case STM_128MBIT_SIGNATURE: -+ flash_size = FLASH_16MB; -+ break; -+ default: -+ printk (KERN_WARNING SPIFLASH "Read of flash device signature failed!\n"); -+ return 0; -+ } -+ -+ return flash_size; -+} -+ -+ -+/* wait until the flash chip is ready and grab a lock */ -+static int spiflash_wait_ready(struct spiflash_priv *priv, int state) -+{ -+ DECLARE_WAITQUEUE(wait, current); -+ -+retry: -+ spin_lock_bh(&priv->lock); -+ if (priv->state != FL_READY) { -+ set_current_state(TASK_UNINTERRUPTIBLE); -+ add_wait_queue(&priv->wq, &wait); -+ spin_unlock_bh(&priv->lock); -+ schedule(); -+ remove_wait_queue(&priv->wq, &wait); -+ -+ if(signal_pending(current)) -+ return 0; -+ -+ goto retry; -+ } -+ priv->state = state; -+ -+ return 1; -+} -+ -+static inline void spiflash_done(struct spiflash_priv *priv) -+{ -+ priv->state = FL_READY; -+ spin_unlock_bh(&priv->lock); -+ wake_up(&priv->wq); -+} -+ -+static void -+spiflash_wait_complete(struct spiflash_priv *priv, unsigned int timeout) -+{ -+ busy_wait(priv, spiflash_sendcmd(priv, SPI_RD_STATUS, 0) & -+ SPI_STATUS_WIP, timeout); -+ spiflash_done(priv); -+} -+ -+ -+ -+static int -+spiflash_erase (struct mtd_info *mtd, struct erase_info *instr) -+{ -+ struct spiflash_priv *priv = to_spiflash(mtd); -+ const struct opcodes *op; -+ u32 temp, reg; -+ -+ if (instr->addr + instr->len > mtd->size) -+ return -EINVAL; -+ -+ if (!spiflash_wait_ready(priv, FL_ERASING)) -+ return -EINTR; -+ -+ spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0); -+ reg = spiflash_wait_busy(priv); -+ -+ op = &stm_opcodes[SPI_SECTOR_ERASE]; -+ temp = ((u32)instr->addr << 8) | (u32)(op->code); -+ spiflash_write_reg(priv, SPI_FLASH_OPCODE, temp); -+ -+ reg &= ~SPI_CTL_TX_RX_CNT_MASK; -+ reg |= op->tx_cnt | SPI_CTL_START; -+ spiflash_write_reg(priv, SPI_FLASH_CTL, reg); -+ -+ spiflash_wait_complete(priv, 20); -+ -+ instr->state = MTD_ERASE_DONE; -+ mtd_erase_callback(instr); -+ -+ return 0; -+} -+ -+static int -+spiflash_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf) -+{ -+ struct spiflash_priv *priv = to_spiflash(mtd); -+ u8 *read_addr; -+ -+ if (!len) -+ return 0; -+ -+ if (from + len > mtd->size) -+ return -EINVAL; -+ -+ *retlen = len; -+ -+ if (!spiflash_wait_ready(priv, FL_READING)) -+ return -EINTR; -+ -+ read_addr = (u8 *)(priv->readaddr + from); -+ memcpy_fromio(buf, read_addr, len); -+ spiflash_done(priv); -+ -+ return 0; -+} -+ -+static int -+spiflash_write (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u8 *buf) -+{ -+ struct spiflash_priv *priv = to_spiflash(mtd); -+ u32 opcode, bytes_left; -+ -+ *retlen = 0; -+ -+ if (!len) -+ return 0; -+ -+ if (to + len > mtd->size) -+ return -EINVAL; -+ -+ bytes_left = len; -+ -+ do { -+ u32 read_len, reg, page_offset, spi_data = 0; -+ -+ read_len = min(bytes_left, sizeof(u32)); -+ -+ /* 32-bit writes cannot span across a page boundary -+ * (256 bytes). This types of writes require two page -+ * program operations to handle it correctly. The STM part -+ * will write the overflow data to the beginning of the -+ * current page as opposed to the subsequent page. -+ */ -+ page_offset = (to & (STM_PAGE_SIZE - 1)) + read_len; -+ -+ if (page_offset > STM_PAGE_SIZE) -+ read_len -= (page_offset - STM_PAGE_SIZE); -+ -+ if (!spiflash_wait_ready(priv, FL_WRITING)) -+ return -EINTR; -+ -+ spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0); -+ spi_data = 0; -+ switch (read_len) { -+ case 4: -+ spi_data |= buf[3] << 24; -+ /* fall through */ -+ case 3: -+ spi_data |= buf[2] << 16; -+ /* fall through */ -+ case 2: -+ spi_data |= buf[1] << 8; -+ /* fall through */ -+ case 1: -+ spi_data |= buf[0] & 0xff; -+ break; -+ default: -+ break; -+ } -+ -+ spiflash_write_reg(priv, SPI_FLASH_DATA, spi_data); -+ opcode = stm_opcodes[SPI_PAGE_PROGRAM].code | -+ (to & 0x00ffffff) << 8; -+ spiflash_write_reg(priv, SPI_FLASH_OPCODE, opcode); -+ -+ reg = spiflash_read_reg(priv, SPI_FLASH_CTL); -+ reg &= ~SPI_CTL_TX_RX_CNT_MASK; -+ reg |= (read_len + 4) | SPI_CTL_START; -+ spiflash_write_reg(priv, SPI_FLASH_CTL, reg); -+ -+ spiflash_wait_complete(priv, 1); -+ -+ bytes_left -= read_len; -+ to += read_len; -+ buf += read_len; -+ -+ *retlen += read_len; -+ } while (bytes_left != 0); -+ -+ return 0; -+} -+ -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static const char *part_probe_types[] = { "cmdlinepart", "RedBoot", "MyLoader", NULL }; -+#endif -+ -+ -+static int -+spiflash_probe(struct platform_device *pdev) -+{ -+ struct spiflash_priv *priv; -+ struct mtd_partition *parts; -+ struct mtd_info *mtd; -+ int index, num_parts; -+ int result = 0; -+ -+ priv = kzalloc(sizeof(struct spiflash_priv), GFP_KERNEL); -+ spin_lock_init(&priv->lock); -+ init_waitqueue_head(&priv->wq); -+ priv->state = FL_READY; -+ mtd = &priv->mtd; -+ -+ priv->mmraddr = ioremap_nocache(SPI_FLASH_MMR, SPI_FLASH_MMR_SIZE); -+ if (!priv->mmraddr) { -+ printk(KERN_WARNING SPIFLASH "Failed to map flash device\n"); -+ goto error; -+ } -+ -+ index = spiflash_probe_chip(priv); -+ if (!index) { -+ printk (KERN_WARNING SPIFLASH "Found no serial flash device\n"); -+ goto error; -+ } -+ -+ priv->readaddr = ioremap_nocache(SPI_FLASH_READ, flashconfig_tbl[index].byte_cnt); -+ if (!priv->readaddr) { -+ printk (KERN_WARNING SPIFLASH "Failed to map flash device\n"); -+ goto error; -+ } -+ -+ platform_set_drvdata(pdev, priv); -+ mtd->name = "spiflash"; -+ mtd->type = MTD_NORFLASH; -+ mtd->flags = (MTD_CAP_NORFLASH|MTD_WRITEABLE); -+ mtd->size = flashconfig_tbl[index].byte_cnt; -+ mtd->erasesize = flashconfig_tbl[index].sector_size; -+ mtd->writesize = 1; -+ mtd->numeraseregions = 0; -+ mtd->eraseregions = NULL; -+ mtd->erase = spiflash_erase; -+ mtd->read = spiflash_read; -+ mtd->write = spiflash_write; -+ mtd->owner = THIS_MODULE; -+ -+#ifdef CONFIG_MTD_PARTITIONS -+ /* parse redboot partitions */ -+ num_parts = parse_mtd_partitions(mtd, part_probe_types, &parts, 0); -+ if (!num_parts) -+ goto error; -+ -+ result = add_mtd_partitions(mtd, parts, num_parts); -+#endif -+ -+ return result; -+ -+error: -+ if (priv->mmraddr) -+ iounmap(priv->mmraddr); -+ kfree(priv); -+ return -ENXIO; -+} -+ -+static int -+spiflash_remove (struct platform_device *pdev) -+{ -+ struct spiflash_priv *priv = platform_get_drvdata(pdev); -+ struct mtd_info *mtd = &priv->mtd; -+ -+ del_mtd_partitions(mtd); -+ iounmap(priv->mmraddr); -+ iounmap(priv->readaddr); -+ kfree(priv); -+ -+ return 0; -+} -+ -+struct platform_driver spiflash_driver = { -+ .driver.name = "spiflash", -+ .probe = spiflash_probe, -+ .remove = spiflash_remove, -+}; -+ -+int __init -+spiflash_init (void) -+{ -+ return platform_driver_register(&spiflash_driver); -+} -+ -+void __exit -+spiflash_exit (void) -+{ -+ return platform_driver_unregister(&spiflash_driver); -+} -+ -+module_init (spiflash_init); -+module_exit (spiflash_exit); -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("OpenWrt.org, Atheros Communications Inc"); -+MODULE_DESCRIPTION("MTD driver for SPI Flash on Atheros SOC"); -+ -diff -Nur linux-2.6.37.orig/drivers/mtd/redboot.c linux-2.6.37/drivers/mtd/redboot.c ---- linux-2.6.37.orig/drivers/mtd/redboot.c 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/mtd/redboot.c 2011-05-15 19:24:57.000000000 +0200 -@@ -55,6 +55,22 @@ - return 1; - } - -+static uint32_t mtd_get_offset_erasesize(struct mtd_info *mtd, uint64_t offset) -+{ -+ struct mtd_erase_region_info *regions = mtd->eraseregions; -+ int i; -+ -+ for (i = 0; i < mtd->numeraseregions; i++) { -+ if (regions[i].offset + -+ regions[i].numblocks * regions[i].erasesize <= offset) -+ continue; -+ -+ return regions[i].erasesize; -+ } -+ -+ return mtd->erasesize; -+} -+ - static int parse_redboot_partitions(struct mtd_info *master, - struct mtd_partition **pparts, - unsigned long fis_origin) -@@ -70,36 +86,38 @@ - int namelen = 0; - int nulllen = 0; - int numslots; -+ int first_slot; - unsigned long offset; - #ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED - static char nullstring[] = "unallocated"; - #endif - -+ buf = vmalloc(master->erasesize); -+ if (!buf) -+ return -ENOMEM; -+ -+ restart: - if ( directory < 0 ) { - offset = master->size + directory * master->erasesize; -- while (master->block_isbad && -+ while (master->block_isbad && - master->block_isbad(master, offset)) { - if (!offset) { - nogood: - printk(KERN_NOTICE "Failed to find a non-bad block to check for RedBoot partition table\n"); -+ vfree(buf); - return -EIO; - } - offset -= master->erasesize; - } - } else { - offset = directory * master->erasesize; -- while (master->block_isbad && -+ while (master->block_isbad && - master->block_isbad(master, offset)) { - offset += master->erasesize; - if (offset == master->size) - goto nogood; - } - } -- buf = vmalloc(master->erasesize); -- -- if (!buf) -- return -ENOMEM; -- - printk(KERN_NOTICE "Searching for RedBoot partition table in %s at offset 0x%lx\n", - master->name, offset); - -@@ -171,13 +189,21 @@ - } - if (i == numslots) { - /* Didn't find it */ -+ if (offset + master->erasesize < master->size) { -+ /* not at the end of the flash yet, maybe next block :) */ -+ directory++; -+ goto restart; -+ } - printk(KERN_NOTICE "No RedBoot partition table detected in %s\n", - master->name); - ret = 0; - goto out; - } - -- for (i = 0; i < numslots; i++) { -+ first_slot = (buf[i].flash_base & (master->erasesize - 1)) / -+ sizeof(struct fis_image_desc); -+ -+ for (i = first_slot; i < first_slot + numslots; i++) { - struct fis_list *new_fl, **prev; - - if (buf[i].name[0] == 0xff) { -diff -Nur linux-2.6.37.orig/drivers/net/Kconfig linux-2.6.37/drivers/net/Kconfig ---- linux-2.6.37.orig/drivers/net/Kconfig 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/net/Kconfig 2011-05-15 19:24:57.000000000 +0200 -@@ -251,6 +251,12 @@ - help - Select this if your platform comes with an external 93CX6 eeprom. - -+config AR231X_ETHERNET -+ tristate "AR231x Ethernet support" -+ depends on ATHEROS_AR231X -+ help -+ Support for the AR231x/531x ethernet controller -+ - config MACE - tristate "MACE (Power Mac ethernet) support" - depends on PPC_PMAC && PPC32 -diff -Nur linux-2.6.37.orig/drivers/net/Makefile linux-2.6.37/drivers/net/Makefile ---- linux-2.6.37.orig/drivers/net/Makefile 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/net/Makefile 2011-05-15 19:24:57.000000000 +0200 -@@ -224,6 +224,7 @@ - obj-$(CONFIG_KORINA) += korina.o - obj-$(CONFIG_MIPS_JAZZ_SONIC) += jazzsonic.o - obj-$(CONFIG_MIPS_AU1X00_ENET) += au1000_eth.o -+obj-$(CONFIG_AR231X_ETHERNET) += ar231x.o - obj-$(CONFIG_MIPS_SIM_NET) += mipsnet.o - obj-$(CONFIG_SGI_IOC3_ETH) += ioc3-eth.o - obj-$(CONFIG_DECLANCE) += declance.o -diff -Nur linux-2.6.37.orig/drivers/net/ar231x.c linux-2.6.37/drivers/net/ar231x.c ---- linux-2.6.37.orig/drivers/net/ar231x.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/drivers/net/ar231x.c 2011-05-15 19:24:57.000000000 +0200 -@@ -0,0 +1,1327 @@ -+/* -+ * ar231x.c: Linux driver for the Atheros AR231x Ethernet device. -+ * -+ * Copyright (C) 2004 by Sameer Dekate -+ * Copyright (C) 2006 Imre Kaloz -+ * Copyright (C) 2006-2009 Felix Fietkau -+ * -+ * Thanks to Atheros for providing hardware and documentation -+ * enabling me to write this driver. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * Additional credits: -+ * This code is taken from John Taylor's Sibyte driver and then -+ * modified for the AR2313. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define AR2313_MTU 1692 -+#define AR2313_PRIOS 1 -+#define AR2313_QUEUES (2*AR2313_PRIOS) -+#define AR2313_DESCR_ENTRIES 64 -+ -+ -+#ifndef min -+#define min(a,b) (((a)<(b))?(a):(b)) -+#endif -+ -+#ifndef SMP_CACHE_BYTES -+#define SMP_CACHE_BYTES L1_CACHE_BYTES -+#endif -+ -+#define AR2313_MBOX_SET_BIT 0x8 -+ -+#include "ar231x.h" -+ -+/* -+ * New interrupt handler strategy: -+ * -+ * An old interrupt handler worked using the traditional method of -+ * replacing an skbuff with a new one when a packet arrives. However -+ * the rx rings do not need to contain a static number of buffer -+ * descriptors, thus it makes sense to move the memory allocation out -+ * of the main interrupt handler and do it in a bottom half handler -+ * and only allocate new buffers when the number of buffers in the -+ * ring is below a certain threshold. In order to avoid starving the -+ * NIC under heavy load it is however necessary to force allocation -+ * when hitting a minimum threshold. The strategy for alloction is as -+ * follows: -+ * -+ * RX_LOW_BUF_THRES - allocate buffers in the bottom half -+ * RX_PANIC_LOW_THRES - we are very low on buffers, allocate -+ * the buffers in the interrupt handler -+ * RX_RING_THRES - maximum number of buffers in the rx ring -+ * -+ * One advantagous side effect of this allocation approach is that the -+ * entire rx processing can be done without holding any spin lock -+ * since the rx rings and registers are totally independent of the tx -+ * ring and its registers. This of course includes the kmalloc's of -+ * new skb's. Thus start_xmit can run in parallel with rx processing -+ * and the memory allocation on SMP systems. -+ * -+ * Note that running the skb reallocation in a bottom half opens up -+ * another can of races which needs to be handled properly. In -+ * particular it can happen that the interrupt handler tries to run -+ * the reallocation while the bottom half is either running on another -+ * CPU or was interrupted on the same CPU. To get around this the -+ * driver uses bitops to prevent the reallocation routines from being -+ * reentered. -+ * -+ * TX handling can also be done without holding any spin lock, wheee -+ * this is fun! since tx_csm is only written to by the interrupt -+ * handler. -+ */ -+ -+/* -+ * Threshold values for RX buffer allocation - the low water marks for -+ * when to start refilling the rings are set to 75% of the ring -+ * sizes. It seems to make sense to refill the rings entirely from the -+ * intrrupt handler once it gets below the panic threshold, that way -+ * we don't risk that the refilling is moved to another CPU when the -+ * one running the interrupt handler just got the slab code hot in its -+ * cache. -+ */ -+#define RX_RING_SIZE AR2313_DESCR_ENTRIES -+#define RX_PANIC_THRES (RX_RING_SIZE/4) -+#define RX_LOW_THRES ((3*RX_RING_SIZE)/4) -+#define CRC_LEN 4 -+#define RX_OFFSET 2 -+ -+#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) -+#define VLAN_HDR 4 -+#else -+#define VLAN_HDR 0 -+#endif -+ -+#define AR2313_BUFSIZE (AR2313_MTU + VLAN_HDR + ETH_HLEN + CRC_LEN + RX_OFFSET) -+ -+#ifdef MODULE -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Sameer Dekate , Imre Kaloz , Felix Fietkau "); -+MODULE_DESCRIPTION("AR231x Ethernet driver"); -+#endif -+ -+#define virt_to_phys(x) ((u32)(x) & 0x1fffffff) -+ -+// prototypes -+static void ar231x_halt(struct net_device *dev); -+static void rx_tasklet_func(unsigned long data); -+static void rx_tasklet_cleanup(struct net_device *dev); -+static void ar231x_multicast_list(struct net_device *dev); -+static void ar231x_tx_timeout(struct net_device *dev); -+ -+static int ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum); -+static int ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, u16 value); -+static int ar231x_mdiobus_reset(struct mii_bus *bus); -+static int ar231x_mdiobus_probe (struct net_device *dev); -+static void ar231x_adjust_link(struct net_device *dev); -+static bool no_phy = false; -+ -+#ifndef ERR -+#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args) -+#endif -+ -+#ifdef CONFIG_NET_POLL_CONTROLLER -+static void -+ar231x_netpoll(struct net_device *dev) -+{ -+ unsigned long flags; -+ -+ local_irq_save(flags); -+ ar231x_interrupt(dev->irq, dev); -+ local_irq_restore(flags); -+} -+#endif -+ -+static const struct net_device_ops ar231x_ops = { -+ .ndo_open = ar231x_open, -+ .ndo_stop = ar231x_close, -+ .ndo_start_xmit = ar231x_start_xmit, -+ .ndo_set_multicast_list = ar231x_multicast_list, -+ .ndo_do_ioctl = ar231x_ioctl, -+ .ndo_change_mtu = eth_change_mtu, -+ .ndo_validate_addr = eth_validate_addr, -+ .ndo_set_mac_address = eth_mac_addr, -+ .ndo_tx_timeout = ar231x_tx_timeout, -+#ifdef CONFIG_NET_POLL_CONTROLLER -+ .ndo_poll_controller = ar231x_netpoll, -+#endif -+}; -+ -+int __init ar231x_probe(struct platform_device *pdev) -+{ -+ struct net_device *dev; -+ struct ar231x_private *sp; -+ struct resource *res; -+ unsigned long ar_eth_base; -+ char buf[64]; -+ -+ dev = alloc_etherdev(sizeof(struct ar231x_private)); -+ -+ if (dev == NULL) { -+ printk(KERN_ERR -+ "ar231x: Unable to allocate net_device structure!\n"); -+ return -ENOMEM; -+ } -+ -+ platform_set_drvdata(pdev, dev); -+ -+ sp = netdev_priv(dev); -+ sp->dev = dev; -+ sp->cfg = pdev->dev.platform_data; -+ -+ sprintf(buf, "eth%d_membase", pdev->id); -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, buf); -+ if (!res) -+ return -ENODEV; -+ -+ sp->link = 0; -+ ar_eth_base = res->start; -+ -+ sprintf(buf, "eth%d_irq", pdev->id); -+ dev->irq = platform_get_irq_byname(pdev, buf); -+ -+ spin_lock_init(&sp->lock); -+ -+ dev->features |= NETIF_F_HIGHDMA; -+ dev->netdev_ops = &ar231x_ops; -+ -+ tasklet_init(&sp->rx_tasklet, rx_tasklet_func, (unsigned long) dev); -+ tasklet_disable(&sp->rx_tasklet); -+ -+ sp->eth_regs = -+ ioremap_nocache(virt_to_phys(ar_eth_base), sizeof(*sp->eth_regs)); -+ if (!sp->eth_regs) { -+ printk("Can't remap eth registers\n"); -+ return (-ENXIO); -+ } -+ -+ /* -+ * When there's only one MAC, PHY regs are typically on ENET0, -+ * even though the MAC might be on ENET1. -+ * Needto remap PHY regs separately in this case -+ */ -+ if (virt_to_phys(ar_eth_base) == virt_to_phys(sp->phy_regs)) -+ sp->phy_regs = sp->eth_regs; -+ else { -+ sp->phy_regs = -+ ioremap_nocache(virt_to_phys(sp->cfg->phy_base), -+ sizeof(*sp->phy_regs)); -+ if (!sp->phy_regs) { -+ printk("Can't remap phy registers\n"); -+ return (-ENXIO); -+ } -+ } -+ -+ sp->dma_regs = -+ ioremap_nocache(virt_to_phys(ar_eth_base + 0x1000), -+ sizeof(*sp->dma_regs)); -+ dev->base_addr = (unsigned int) sp->dma_regs; -+ if (!sp->dma_regs) { -+ printk("Can't remap DMA registers\n"); -+ return (-ENXIO); -+ } -+ -+ sp->int_regs = ioremap_nocache(virt_to_phys(sp->cfg->reset_base), 4); -+ if (!sp->int_regs) { -+ printk("Can't remap INTERRUPT registers\n"); -+ return (-ENXIO); -+ } -+ -+ strncpy(sp->name, "Atheros AR231x", sizeof(sp->name) - 1); -+ sp->name[sizeof(sp->name) - 1] = '\0'; -+ memcpy(dev->dev_addr, sp->cfg->macaddr, 6); -+ -+ if (ar231x_init(dev)) { -+ /* -+ * ar231x_init() calls ar231x_init_cleanup() on error. -+ */ -+ kfree(dev); -+ return -ENODEV; -+ } -+ -+ if (register_netdev(dev)) { -+ printk("%s: register_netdev failed\n", __func__); -+ return -1; -+ } -+ -+ printk("%s: %s: %02x:%02x:%02x:%02x:%02x:%02x, irq %d\n", -+ dev->name, sp->name, -+ dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], -+ dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5], dev->irq); -+ -+ sp->mii_bus = mdiobus_alloc(); -+ if (sp->mii_bus == NULL) -+ return -1; -+ -+ sp->mii_bus->priv = dev; -+ sp->mii_bus->read = ar231x_mdiobus_read; -+ sp->mii_bus->write = ar231x_mdiobus_write; -+ sp->mii_bus->reset = ar231x_mdiobus_reset; -+ sp->mii_bus->name = "ar231x_eth_mii"; -+ snprintf(sp->mii_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id); -+ sp->mii_bus->irq = kmalloc(sizeof(int), GFP_KERNEL); -+ *sp->mii_bus->irq = PHY_POLL; -+ -+ mdiobus_register(sp->mii_bus); -+ -+ /* Workaround for Micrel switch, which is only available on -+ * one PHY and cannot be configured through MDIO */ -+ if (!no_phy) { -+ u32 phy_id = 0; -+ get_phy_id(sp->mii_bus, 1, &phy_id); -+ if (phy_id == 0x00221450) -+ no_phy = true; -+ } -+ if (no_phy) { -+ sp->link = 1; -+ netif_carrier_on(dev); -+ return 0; -+ } -+ no_phy = true; -+ -+ if (ar231x_mdiobus_probe(dev) != 0) { -+ printk(KERN_ERR "%s: mdiobus_probe failed\n", dev->name); -+ rx_tasklet_cleanup(dev); -+ ar231x_init_cleanup(dev); -+ unregister_netdev(dev); -+ kfree(dev); -+ return -ENODEV; -+ } -+ -+ /* start link poll timer */ -+ ar231x_setup_timer(dev); -+ -+ return 0; -+} -+ -+ -+static void ar231x_multicast_list(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ unsigned int filter; -+ -+ filter = sp->eth_regs->mac_control; -+ -+ if (dev->flags & IFF_PROMISC) -+ filter |= MAC_CONTROL_PR; -+ else -+ filter &= ~MAC_CONTROL_PR; -+ if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 0)) -+ filter |= MAC_CONTROL_PM; -+ else -+ filter &= ~MAC_CONTROL_PM; -+ -+ sp->eth_regs->mac_control = filter; -+} -+ -+static void rx_tasklet_cleanup(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ -+ /* -+ * Tasklet may be scheduled. Need to get it removed from the list -+ * since we're about to free the struct. -+ */ -+ -+ sp->unloading = 1; -+ tasklet_enable(&sp->rx_tasklet); -+ tasklet_kill(&sp->rx_tasklet); -+} -+ -+static int __devexit ar231x_remove(struct platform_device *pdev) -+{ -+ struct net_device *dev = platform_get_drvdata(pdev); -+ struct ar231x_private *sp = netdev_priv(dev); -+ rx_tasklet_cleanup(dev); -+ ar231x_init_cleanup(dev); -+ unregister_netdev(dev); -+ if (sp->mii_bus) { -+ mdiobus_unregister(sp->mii_bus); -+ mdiobus_free(sp->mii_bus); -+ } -+ kfree(dev); -+ return 0; -+} -+ -+ -+/* -+ * Restart the AR2313 ethernet controller. -+ */ -+static int ar231x_restart(struct net_device *dev) -+{ -+ /* disable interrupts */ -+ disable_irq(dev->irq); -+ -+ /* stop mac */ -+ ar231x_halt(dev); -+ -+ /* initialize */ -+ ar231x_init(dev); -+ -+ /* enable interrupts */ -+ enable_irq(dev->irq); -+ -+ return 0; -+} -+ -+static struct platform_driver ar231x_driver = { -+ .driver.name = "ar231x-eth", -+ .probe = ar231x_probe, -+ .remove = __devexit_p(ar231x_remove), -+}; -+ -+int __init ar231x_module_init(void) -+{ -+ return platform_driver_register(&ar231x_driver); -+} -+ -+void __exit ar231x_module_cleanup(void) -+{ -+ platform_driver_unregister(&ar231x_driver); -+} -+ -+module_init(ar231x_module_init); -+module_exit(ar231x_module_cleanup); -+ -+ -+static void ar231x_free_descriptors(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ if (sp->rx_ring != NULL) { -+ kfree((void *) KSEG0ADDR(sp->rx_ring)); -+ sp->rx_ring = NULL; -+ sp->tx_ring = NULL; -+ } -+} -+ -+ -+static int ar231x_allocate_descriptors(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ int size; -+ int j; -+ ar231x_descr_t *space; -+ -+ if (sp->rx_ring != NULL) { -+ printk("%s: already done.\n", __FUNCTION__); -+ return 0; -+ } -+ -+ size = -+ (sizeof(ar231x_descr_t) * (AR2313_DESCR_ENTRIES * AR2313_QUEUES)); -+ space = kmalloc(size, GFP_KERNEL); -+ if (space == NULL) -+ return 1; -+ -+ /* invalidate caches */ -+ dma_cache_inv((unsigned int) space, size); -+ -+ /* now convert pointer to KSEG1 */ -+ space = (ar231x_descr_t *) KSEG1ADDR(space); -+ -+ memset((void *) space, 0, size); -+ -+ sp->rx_ring = space; -+ space += AR2313_DESCR_ENTRIES; -+ -+ sp->tx_ring = space; -+ space += AR2313_DESCR_ENTRIES; -+ -+ /* Initialize the transmit Descriptors */ -+ for (j = 0; j < AR2313_DESCR_ENTRIES; j++) { -+ ar231x_descr_t *td = &sp->tx_ring[j]; -+ td->status = 0; -+ td->devcs = DMA_TX1_CHAINED; -+ td->addr = 0; -+ td->descr = -+ virt_to_phys(&sp-> -+ tx_ring[(j + 1) & (AR2313_DESCR_ENTRIES - 1)]); -+ } -+ -+ return 0; -+} -+ -+ -+/* -+ * Generic cleanup handling data allocated during init. Used when the -+ * module is unloaded or if an error occurs during initialization -+ */ -+static void ar231x_init_cleanup(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ struct sk_buff *skb; -+ int j; -+ -+ ar231x_free_descriptors(dev); -+ -+ if (sp->eth_regs) -+ iounmap((void *) sp->eth_regs); -+ if (sp->dma_regs) -+ iounmap((void *) sp->dma_regs); -+ -+ if (sp->rx_skb) { -+ for (j = 0; j < AR2313_DESCR_ENTRIES; j++) { -+ skb = sp->rx_skb[j]; -+ if (skb) { -+ sp->rx_skb[j] = NULL; -+ dev_kfree_skb(skb); -+ } -+ } -+ kfree(sp->rx_skb); -+ sp->rx_skb = NULL; -+ } -+ -+ if (sp->tx_skb) { -+ for (j = 0; j < AR2313_DESCR_ENTRIES; j++) { -+ skb = sp->tx_skb[j]; -+ if (skb) { -+ sp->tx_skb[j] = NULL; -+ dev_kfree_skb(skb); -+ } -+ } -+ kfree(sp->tx_skb); -+ sp->tx_skb = NULL; -+ } -+} -+ -+static int ar231x_setup_timer(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ -+ init_timer(&sp->link_timer); -+ -+ sp->link_timer.function = ar231x_link_timer_fn; -+ sp->link_timer.data = (int) dev; -+ sp->link_timer.expires = jiffies + HZ; -+ -+ add_timer(&sp->link_timer); -+ return 0; -+ -+} -+ -+static void ar231x_link_timer_fn(unsigned long data) -+{ -+ struct net_device *dev = (struct net_device *) data; -+ struct ar231x_private *sp = netdev_priv(dev); -+ -+ // see if the link status changed -+ // This was needed to make sure we set the PHY to the -+ // autonegotiated value of half or full duplex. -+ ar231x_check_link(dev); -+ -+ // Loop faster when we don't have link. -+ // This was needed to speed up the AP bootstrap time. -+ if (sp->link == 0) { -+ mod_timer(&sp->link_timer, jiffies + HZ / 2); -+ } else { -+ mod_timer(&sp->link_timer, jiffies + LINK_TIMER); -+ } -+} -+ -+static void ar231x_check_link(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ u16 phyData; -+ -+ phyData = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_BMSR); -+ if (sp->phyData != phyData) { -+ if (phyData & BMSR_LSTATUS) { -+ /* link is present, ready link partner ability to deterine -+ duplexity */ -+ int duplex = 0; -+ u16 reg; -+ -+ sp->link = 1; -+ reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_BMCR); -+ if (reg & BMCR_ANENABLE) { -+ /* auto neg enabled */ -+ reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_LPA); -+ duplex = (reg & (LPA_100FULL | LPA_10FULL)) ? 1 : 0; -+ } else { -+ /* no auto neg, just read duplex config */ -+ duplex = (reg & BMCR_FULLDPLX) ? 1 : 0; -+ } -+ -+ printk(KERN_INFO "%s: Configuring MAC for %s duplex\n", -+ dev->name, (duplex) ? "full" : "half"); -+ -+ if (duplex) { -+ /* full duplex */ -+ sp->eth_regs->mac_control = -+ ((sp->eth_regs-> -+ mac_control | MAC_CONTROL_F) & ~MAC_CONTROL_DRO); -+ } else { -+ /* half duplex */ -+ sp->eth_regs->mac_control = -+ ((sp->eth_regs-> -+ mac_control | MAC_CONTROL_DRO) & ~MAC_CONTROL_F); -+ } -+ } else { -+ /* no link */ -+ sp->link = 0; -+ } -+ sp->phyData = phyData; -+ } -+} -+ -+static int ar231x_reset_reg(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ unsigned int ethsal, ethsah; -+ unsigned int flags; -+ -+ *sp->int_regs |= sp->cfg->reset_mac; -+ mdelay(10); -+ *sp->int_regs &= ~sp->cfg->reset_mac; -+ mdelay(10); -+ *sp->int_regs |= sp->cfg->reset_phy; -+ mdelay(10); -+ *sp->int_regs &= ~sp->cfg->reset_phy; -+ mdelay(10); -+ -+ sp->dma_regs->bus_mode = (DMA_BUS_MODE_SWR); -+ mdelay(10); -+ sp->dma_regs->bus_mode = -+ ((32 << DMA_BUS_MODE_PBL_SHIFT) | DMA_BUS_MODE_BLE); -+ -+ /* enable interrupts */ -+ sp->dma_regs->intr_ena = (DMA_STATUS_AIS | -+ DMA_STATUS_NIS | -+ DMA_STATUS_RI | -+ DMA_STATUS_TI | DMA_STATUS_FBE); -+ sp->dma_regs->xmt_base = virt_to_phys(sp->tx_ring); -+ sp->dma_regs->rcv_base = virt_to_phys(sp->rx_ring); -+ sp->dma_regs->control = -+ (DMA_CONTROL_SR | DMA_CONTROL_ST | DMA_CONTROL_SF); -+ -+ sp->eth_regs->flow_control = (FLOW_CONTROL_FCE); -+ sp->eth_regs->vlan_tag = (0x8100); -+ -+ /* Enable Ethernet Interface */ -+ flags = (MAC_CONTROL_TE | /* transmit enable */ -+ MAC_CONTROL_PM | /* pass mcast */ -+ MAC_CONTROL_F | /* full duplex */ -+ MAC_CONTROL_HBD); /* heart beat disabled */ -+ -+ if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */ -+ flags |= MAC_CONTROL_PR; -+ } -+ sp->eth_regs->mac_control = flags; -+ -+ /* Set all Ethernet station address registers to their initial values */ -+ ethsah = ((((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) | -+ (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF)); -+ -+ ethsal = ((((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) | -+ (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) | -+ (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) | -+ (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF)); -+ -+ sp->eth_regs->mac_addr[0] = ethsah; -+ sp->eth_regs->mac_addr[1] = ethsal; -+ -+ mdelay(10); -+ -+ return (0); -+} -+ -+ -+static int ar231x_init(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ int ecode = 0; -+ -+ /* -+ * Allocate descriptors -+ */ -+ if (ar231x_allocate_descriptors(dev)) { -+ printk("%s: %s: ar231x_allocate_descriptors failed\n", -+ dev->name, __FUNCTION__); -+ ecode = -EAGAIN; -+ goto init_error; -+ } -+ -+ /* -+ * Get the memory for the skb rings. -+ */ -+ if (sp->rx_skb == NULL) { -+ sp->rx_skb = -+ kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES, -+ GFP_KERNEL); -+ if (!(sp->rx_skb)) { -+ printk("%s: %s: rx_skb kmalloc failed\n", -+ dev->name, __FUNCTION__); -+ ecode = -EAGAIN; -+ goto init_error; -+ } -+ } -+ memset(sp->rx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES); -+ -+ if (sp->tx_skb == NULL) { -+ sp->tx_skb = -+ kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES, -+ GFP_KERNEL); -+ if (!(sp->tx_skb)) { -+ printk("%s: %s: tx_skb kmalloc failed\n", -+ dev->name, __FUNCTION__); -+ ecode = -EAGAIN; -+ goto init_error; -+ } -+ } -+ memset(sp->tx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES); -+ -+ /* -+ * Set tx_csm before we start receiving interrupts, otherwise -+ * the interrupt handler might think it is supposed to process -+ * tx ints before we are up and running, which may cause a null -+ * pointer access in the int handler. -+ */ -+ sp->rx_skbprd = 0; -+ sp->cur_rx = 0; -+ sp->tx_prd = 0; -+ sp->tx_csm = 0; -+ -+ /* -+ * Zero the stats before starting the interface -+ */ -+ memset(&dev->stats, 0, sizeof(dev->stats)); -+ -+ /* -+ * We load the ring here as there seem to be no way to tell the -+ * firmware to wipe the ring without re-initializing it. -+ */ -+ ar231x_load_rx_ring(dev, RX_RING_SIZE); -+ -+ /* -+ * Init hardware -+ */ -+ ar231x_reset_reg(dev); -+ -+ /* -+ * Get the IRQ -+ */ -+ ecode = -+ request_irq(dev->irq, &ar231x_interrupt, -+ IRQF_DISABLED | IRQF_SAMPLE_RANDOM, -+ dev->name, dev); -+ if (ecode) { -+ printk(KERN_WARNING "%s: %s: Requested IRQ %d is busy\n", -+ dev->name, __FUNCTION__, dev->irq); -+ goto init_error; -+ } -+ -+ -+ tasklet_enable(&sp->rx_tasklet); -+ -+ return 0; -+ -+ init_error: -+ ar231x_init_cleanup(dev); -+ return ecode; -+} -+ -+/* -+ * Load the rx ring. -+ * -+ * Loading rings is safe without holding the spin lock since this is -+ * done only before the device is enabled, thus no interrupts are -+ * generated and by the interrupt handler/tasklet handler. -+ */ -+static void ar231x_load_rx_ring(struct net_device *dev, int nr_bufs) -+{ -+ -+ struct ar231x_private *sp = netdev_priv(dev); -+ short i, idx; -+ -+ idx = sp->rx_skbprd; -+ -+ for (i = 0; i < nr_bufs; i++) { -+ struct sk_buff *skb; -+ ar231x_descr_t *rd; -+ int offset = RX_OFFSET; -+ -+ if (sp->rx_skb[idx]) -+ break; -+ -+ skb = netdev_alloc_skb(dev, AR2313_BUFSIZE); -+ if (!skb) { -+ printk("\n\n\n\n %s: No memory in system\n\n\n\n", -+ __FUNCTION__); -+ break; -+ } -+ -+ /* -+ * Make sure IP header starts on a fresh cache line. -+ */ -+ skb->dev = dev; -+ if (sp->phy_dev) -+ offset += sp->phy_dev->pkt_align; -+ skb_reserve(skb, offset); -+ sp->rx_skb[idx] = skb; -+ -+ rd = (ar231x_descr_t *) & sp->rx_ring[idx]; -+ -+ /* initialize dma descriptor */ -+ rd->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) | -+ DMA_RX1_CHAINED); -+ rd->addr = virt_to_phys(skb->data); -+ rd->descr = -+ virt_to_phys(&sp-> -+ rx_ring[(idx + 1) & (AR2313_DESCR_ENTRIES - 1)]); -+ rd->status = DMA_RX_OWN; -+ -+ idx = DSC_NEXT(idx); -+ } -+ -+ if (i) -+ sp->rx_skbprd = idx; -+ -+ return; -+} -+ -+#define AR2313_MAX_PKTS_PER_CALL 64 -+ -+static int ar231x_rx_int(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ struct sk_buff *skb, *skb_new; -+ ar231x_descr_t *rxdesc; -+ unsigned int status; -+ u32 idx; -+ int pkts = 0; -+ int rval; -+ -+ idx = sp->cur_rx; -+ -+ /* process at most the entire ring and then wait for another interrupt -+ */ -+ while (1) { -+ -+ rxdesc = &sp->rx_ring[idx]; -+ status = rxdesc->status; -+ if (status & DMA_RX_OWN) { -+ /* SiByte owns descriptor or descr not yet filled in */ -+ rval = 0; -+ break; -+ } -+ -+ if (++pkts > AR2313_MAX_PKTS_PER_CALL) { -+ rval = 1; -+ break; -+ } -+ -+ if ((status & DMA_RX_ERROR) && !(status & DMA_RX_LONG)) { -+ dev->stats.rx_errors++; -+ dev->stats.rx_dropped++; -+ -+ /* add statistics counters */ -+ if (status & DMA_RX_ERR_CRC) -+ dev->stats.rx_crc_errors++; -+ if (status & DMA_RX_ERR_COL) -+ dev->stats.rx_over_errors++; -+ if (status & DMA_RX_ERR_LENGTH) -+ dev->stats.rx_length_errors++; -+ if (status & DMA_RX_ERR_RUNT) -+ dev->stats.rx_over_errors++; -+ if (status & DMA_RX_ERR_DESC) -+ dev->stats.rx_over_errors++; -+ -+ } else { -+ /* alloc new buffer. */ -+ skb_new = netdev_alloc_skb(dev, AR2313_BUFSIZE + RX_OFFSET); -+ if (skb_new != NULL) { -+ int offset; -+ -+ skb = sp->rx_skb[idx]; -+ /* set skb */ -+ skb_put(skb, -+ ((status >> DMA_RX_LEN_SHIFT) & 0x3fff) - CRC_LEN); -+ dev->stats.rx_bytes += skb->len; -+ -+ /* pass the packet to upper layers */ -+ if (sp->rx) { -+ sp->rx(skb); -+ } else { -+ skb->protocol = eth_type_trans(skb, skb->dev); -+ netif_rx(skb); -+ } -+ skb_new->dev = dev; -+ -+ /* 16 bit align */ -+ offset = RX_OFFSET; -+ if (sp->phy_dev) -+ offset += sp->phy_dev->pkt_align; -+ skb_reserve(skb_new, offset); -+ /* reset descriptor's curr_addr */ -+ rxdesc->addr = virt_to_phys(skb_new->data); -+ -+ dev->stats.rx_packets++; -+ sp->rx_skb[idx] = skb_new; -+ } else { -+ dev->stats.rx_dropped++; -+ } -+ } -+ -+ rxdesc->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) | -+ DMA_RX1_CHAINED); -+ rxdesc->status = DMA_RX_OWN; -+ -+ idx = DSC_NEXT(idx); -+ } -+ -+ sp->cur_rx = idx; -+ -+ return rval; -+} -+ -+ -+static void ar231x_tx_int(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ u32 idx; -+ struct sk_buff *skb; -+ ar231x_descr_t *txdesc; -+ unsigned int status = 0; -+ -+ idx = sp->tx_csm; -+ -+ while (idx != sp->tx_prd) { -+ txdesc = &sp->tx_ring[idx]; -+ -+ if ((status = txdesc->status) & DMA_TX_OWN) { -+ /* ar231x dma still owns descr */ -+ break; -+ } -+ /* done with this descriptor */ -+ dma_unmap_single(NULL, txdesc->addr, -+ txdesc->devcs & DMA_TX1_BSIZE_MASK, -+ DMA_TO_DEVICE); -+ txdesc->status = 0; -+ -+ if (status & DMA_TX_ERROR) { -+ dev->stats.tx_errors++; -+ dev->stats.tx_dropped++; -+ if (status & DMA_TX_ERR_UNDER) -+ dev->stats.tx_fifo_errors++; -+ if (status & DMA_TX_ERR_HB) -+ dev->stats.tx_heartbeat_errors++; -+ if (status & (DMA_TX_ERR_LOSS | DMA_TX_ERR_LINK)) -+ dev->stats.tx_carrier_errors++; -+ if (status & (DMA_TX_ERR_LATE | -+ DMA_TX_ERR_COL | -+ DMA_TX_ERR_JABBER | DMA_TX_ERR_DEFER)) -+ dev->stats.tx_aborted_errors++; -+ } else { -+ /* transmit OK */ -+ dev->stats.tx_packets++; -+ } -+ -+ skb = sp->tx_skb[idx]; -+ sp->tx_skb[idx] = NULL; -+ idx = DSC_NEXT(idx); -+ dev->stats.tx_bytes += skb->len; -+ dev_kfree_skb_irq(skb); -+ } -+ -+ sp->tx_csm = idx; -+ -+ return; -+} -+ -+ -+static void rx_tasklet_func(unsigned long data) -+{ -+ struct net_device *dev = (struct net_device *) data; -+ struct ar231x_private *sp = netdev_priv(dev); -+ -+ if (sp->unloading) { -+ return; -+ } -+ -+ if (ar231x_rx_int(dev)) { -+ tasklet_hi_schedule(&sp->rx_tasklet); -+ } else { -+ unsigned long flags; -+ spin_lock_irqsave(&sp->lock, flags); -+ sp->dma_regs->intr_ena |= DMA_STATUS_RI; -+ spin_unlock_irqrestore(&sp->lock, flags); -+ } -+} -+ -+static void rx_schedule(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ -+ sp->dma_regs->intr_ena &= ~DMA_STATUS_RI; -+ -+ tasklet_hi_schedule(&sp->rx_tasklet); -+} -+ -+static irqreturn_t ar231x_interrupt(int irq, void *dev_id) -+{ -+ struct net_device *dev = (struct net_device *) dev_id; -+ struct ar231x_private *sp = netdev_priv(dev); -+ unsigned int status, enabled; -+ -+ /* clear interrupt */ -+ /* -+ * Don't clear RI bit if currently disabled. -+ */ -+ status = sp->dma_regs->status; -+ enabled = sp->dma_regs->intr_ena; -+ sp->dma_regs->status = status & enabled; -+ -+ if (status & DMA_STATUS_NIS) { -+ /* normal status */ -+ /* -+ * Don't schedule rx processing if interrupt -+ * is already disabled. -+ */ -+ if (status & enabled & DMA_STATUS_RI) { -+ /* receive interrupt */ -+ rx_schedule(dev); -+ } -+ if (status & DMA_STATUS_TI) { -+ /* transmit interrupt */ -+ ar231x_tx_int(dev); -+ } -+ } -+ -+ /* abnormal status */ -+ if (status & (DMA_STATUS_FBE | DMA_STATUS_TPS)) { -+ ar231x_restart(dev); -+ } -+ return IRQ_HANDLED; -+} -+ -+ -+static int ar231x_open(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ unsigned int ethsal, ethsah; -+ -+ /* reset the hardware, in case the MAC address changed */ -+ ethsah = ((((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) | -+ (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF)); -+ -+ ethsal = ((((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) | -+ (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) | -+ (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) | -+ (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF)); -+ -+ sp->eth_regs->mac_addr[0] = ethsah; -+ sp->eth_regs->mac_addr[1] = ethsal; -+ -+ mdelay(10); -+ -+ dev->mtu = 1500; -+ netif_start_queue(dev); -+ -+ sp->eth_regs->mac_control |= MAC_CONTROL_RE; -+ -+ return 0; -+} -+ -+static void ar231x_tx_timeout(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ unsigned long flags; -+ -+ spin_lock_irqsave(&sp->lock, flags); -+ ar231x_restart(dev); -+ spin_unlock_irqrestore(&sp->lock, flags); -+} -+ -+static void ar231x_halt(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ int j; -+ -+ tasklet_disable(&sp->rx_tasklet); -+ -+ /* kill the MAC */ -+ sp->eth_regs->mac_control &= ~(MAC_CONTROL_RE | /* disable Receives */ -+ MAC_CONTROL_TE); /* disable Transmits */ -+ /* stop dma */ -+ sp->dma_regs->control = 0; -+ sp->dma_regs->bus_mode = DMA_BUS_MODE_SWR; -+ -+ /* place phy and MAC in reset */ -+ *sp->int_regs |= (sp->cfg->reset_mac | sp->cfg->reset_phy); -+ -+ /* free buffers on tx ring */ -+ for (j = 0; j < AR2313_DESCR_ENTRIES; j++) { -+ struct sk_buff *skb; -+ ar231x_descr_t *txdesc; -+ -+ txdesc = &sp->tx_ring[j]; -+ txdesc->descr = 0; -+ -+ skb = sp->tx_skb[j]; -+ if (skb) { -+ dev_kfree_skb(skb); -+ sp->tx_skb[j] = NULL; -+ } -+ } -+} -+ -+/* -+ * close should do nothing. Here's why. It's called when -+ * 'ifconfig bond0 down' is run. If it calls free_irq then -+ * the irq is gone forever ! When bond0 is made 'up' again, -+ * the ar231x_open () does not call request_irq (). Worse, -+ * the call to ar231x_halt() generates a WDOG reset due to -+ * the write to 'sp->int_regs' and the box reboots. -+ * Commenting this out is good since it allows the -+ * system to resume when bond0 is made up again. -+ */ -+static int ar231x_close(struct net_device *dev) -+{ -+#if 0 -+ /* -+ * Disable interrupts -+ */ -+ disable_irq(dev->irq); -+ -+ /* -+ * Without (or before) releasing irq and stopping hardware, this -+ * is an absolute non-sense, by the way. It will be reset instantly -+ * by the first irq. -+ */ -+ netif_stop_queue(dev); -+ -+ /* stop the MAC and DMA engines */ -+ ar231x_halt(dev); -+ -+ /* release the interrupt */ -+ free_irq(dev->irq, dev); -+ -+#endif -+ return 0; -+} -+ -+static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ ar231x_descr_t *td; -+ u32 idx; -+ -+ idx = sp->tx_prd; -+ td = &sp->tx_ring[idx]; -+ -+ if (td->status & DMA_TX_OWN) { -+ /* free skbuf and lie to the caller that we sent it out */ -+ dev->stats.tx_dropped++; -+ dev_kfree_skb(skb); -+ -+ /* restart transmitter in case locked */ -+ sp->dma_regs->xmt_poll = 0; -+ return 0; -+ } -+ -+ /* Setup the transmit descriptor. */ -+ td->devcs = ((skb->len << DMA_TX1_BSIZE_SHIFT) | -+ (DMA_TX1_LS | DMA_TX1_IC | DMA_TX1_CHAINED)); -+ td->addr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE); -+ td->status = DMA_TX_OWN; -+ -+ /* kick transmitter last */ -+ sp->dma_regs->xmt_poll = 0; -+ -+ sp->tx_skb[idx] = skb; -+ idx = DSC_NEXT(idx); -+ sp->tx_prd = idx; -+ -+ return 0; -+} -+ -+static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) -+{ -+ struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_data; -+ struct ar231x_private *sp = netdev_priv(dev); -+ int ret; -+ -+ if (!sp->phy_dev) -+ return -ENODEV; -+ -+ switch (cmd) { -+ -+ case SIOCETHTOOL: -+ spin_lock_irq(&sp->lock); -+ ret = phy_ethtool_ioctl(sp->phy_dev, (void *) ifr->ifr_data); -+ spin_unlock_irq(&sp->lock); -+ return ret; -+ -+ case SIOCSIFHWADDR: -+ if (copy_from_user -+ (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr))) -+ return -EFAULT; -+ return 0; -+ -+ case SIOCGIFHWADDR: -+ if (copy_to_user -+ (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr))) -+ return -EFAULT; -+ return 0; -+ -+ case SIOCGMIIPHY: -+ case SIOCGMIIREG: -+ case SIOCSMIIREG: -+ return phy_mii_ioctl(sp->phy_dev, data, cmd); -+ -+ default: -+ break; -+ } -+ -+ return -EOPNOTSUPP; -+} -+ -+static void ar231x_adjust_link(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ unsigned int mc; -+ -+ if (!sp->phy_dev->link) -+ return; -+ -+ if (sp->phy_dev->duplex != sp->oldduplex) { -+ mc = readl(&sp->eth_regs->mac_control); -+ mc &= ~(MAC_CONTROL_F | MAC_CONTROL_DRO); -+ if (sp->phy_dev->duplex) -+ mc |= MAC_CONTROL_F; -+ else -+ mc |= MAC_CONTROL_DRO; -+ writel(mc, &sp->eth_regs->mac_control); -+ sp->oldduplex = sp->phy_dev->duplex; -+ } -+} -+ -+#define MII_ADDR(phy, reg) \ -+ ((reg << MII_ADDR_REG_SHIFT) | (phy << MII_ADDR_PHY_SHIFT)) -+ -+static int -+ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum) -+{ -+ struct net_device *const dev = bus->priv; -+ struct ar231x_private *sp = netdev_priv(dev); -+ volatile ETHERNET_STRUCT *ethernet = sp->phy_regs; -+ -+ ethernet->mii_addr = MII_ADDR(phy_addr, regnum); -+ while (ethernet->mii_addr & MII_ADDR_BUSY); -+ return (ethernet->mii_data >> MII_DATA_SHIFT); -+} -+ -+static int -+ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, -+ u16 value) -+{ -+ struct net_device *const dev = bus->priv; -+ struct ar231x_private *sp = netdev_priv(dev); -+ volatile ETHERNET_STRUCT *ethernet = sp->phy_regs; -+ -+ while (ethernet->mii_addr & MII_ADDR_BUSY); -+ ethernet->mii_data = value << MII_DATA_SHIFT; -+ ethernet->mii_addr = MII_ADDR(phy_addr, regnum) | MII_ADDR_WRITE; -+ -+ return 0; -+} -+ -+static int ar231x_mdiobus_reset(struct mii_bus *bus) -+{ -+ struct net_device *const dev = bus->priv; -+ -+ ar231x_reset_reg(dev); -+ -+ return 0; -+} -+ -+static int ar231x_mdiobus_probe (struct net_device *dev) -+{ -+ struct ar231x_private *const sp = netdev_priv(dev); -+ struct phy_device *phydev = NULL; -+ int phy_addr; -+ -+ /* find the first (lowest address) PHY on the current MAC's MII bus */ -+ for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) -+ if (sp->mii_bus->phy_map[phy_addr]) { -+ phydev = sp->mii_bus->phy_map[phy_addr]; -+ sp->phy = phy_addr; -+ break; /* break out with first one found */ -+ } -+ -+ if (!phydev) { -+ printk (KERN_ERR "ar231x: %s: no PHY found\n", dev->name); -+ return -1; -+ } -+ -+ /* now we are supposed to have a proper phydev, to attach to... */ -+ BUG_ON(!phydev); -+ BUG_ON(phydev->attached_dev); -+ -+ phydev = phy_connect(dev, dev_name(&phydev->dev), &ar231x_adjust_link, 0, -+ PHY_INTERFACE_MODE_MII); -+ -+ if (IS_ERR(phydev)) { -+ printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name); -+ return PTR_ERR(phydev); -+ } -+ -+ sp->rx = phydev->netif_rx; -+ -+ /* mask with MAC supported features */ -+ phydev->supported &= (SUPPORTED_10baseT_Half -+ | SUPPORTED_10baseT_Full -+ | SUPPORTED_100baseT_Half -+ | SUPPORTED_100baseT_Full -+ | SUPPORTED_Autoneg -+ /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */ -+ | SUPPORTED_MII -+ | SUPPORTED_TP); -+ -+ phydev->advertising = phydev->supported; -+ -+ sp->oldduplex = -1; -+ sp->phy_dev = phydev; -+ -+ printk(KERN_INFO "%s: attached PHY driver [%s] " -+ "(mii_bus:phy_addr=%s)\n", -+ dev->name, phydev->drv->name, dev_name(&phydev->dev)); -+ -+ return 0; -+} -+ -diff -Nur linux-2.6.37.orig/drivers/net/ar231x.h linux-2.6.37/drivers/net/ar231x.h ---- linux-2.6.37.orig/drivers/net/ar231x.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/drivers/net/ar231x.h 2011-05-15 19:24:57.000000000 +0200 -@@ -0,0 +1,304 @@ -+/* -+ * ar231x.h: Linux driver for the Atheros AR231x Ethernet device. -+ * -+ * Copyright (C) 2004 by Sameer Dekate -+ * Copyright (C) 2006 Imre Kaloz -+ * Copyright (C) 2006-2009 Felix Fietkau -+ * -+ * Thanks to Atheros for providing hardware and documentation -+ * enabling me to write this driver. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ */ -+ -+#ifndef _AR2313_H_ -+#define _AR2313_H_ -+ -+#include -+#include -+#include -+#include -+ -+/* -+ * probe link timer - 5 secs -+ */ -+#define LINK_TIMER (5*HZ) -+ -+#define IS_DMA_TX_INT(X) (((X) & (DMA_STATUS_TI)) != 0) -+#define IS_DMA_RX_INT(X) (((X) & (DMA_STATUS_RI)) != 0) -+#define IS_DRIVER_OWNED(X) (((X) & (DMA_TX_OWN)) == 0) -+ -+#define AR2313_TX_TIMEOUT (HZ/4) -+ -+/* -+ * Rings -+ */ -+#define DSC_RING_ENTRIES_SIZE (AR2313_DESCR_ENTRIES * sizeof(struct desc)) -+#define DSC_NEXT(idx) ((idx + 1) & (AR2313_DESCR_ENTRIES - 1)) -+ -+#define AR2313_MBGET 2 -+#define AR2313_MBSET 3 -+#define AR2313_PCI_RECONFIG 4 -+#define AR2313_PCI_DUMP 5 -+#define AR2313_TEST_PANIC 6 -+#define AR2313_TEST_NULLPTR 7 -+#define AR2313_READ_DATA 8 -+#define AR2313_WRITE_DATA 9 -+#define AR2313_GET_VERSION 10 -+#define AR2313_TEST_HANG 11 -+#define AR2313_SYNC 12 -+ -+#define DMA_RX_ERR_CRC BIT(1) -+#define DMA_RX_ERR_DRIB BIT(2) -+#define DMA_RX_ERR_MII BIT(3) -+#define DMA_RX_EV2 BIT(5) -+#define DMA_RX_ERR_COL BIT(6) -+#define DMA_RX_LONG BIT(7) -+#define DMA_RX_LS BIT(8) /* last descriptor */ -+#define DMA_RX_FS BIT(9) /* first descriptor */ -+#define DMA_RX_MF BIT(10) /* multicast frame */ -+#define DMA_RX_ERR_RUNT BIT(11) /* runt frame */ -+#define DMA_RX_ERR_LENGTH BIT(12) /* length error */ -+#define DMA_RX_ERR_DESC BIT(14) /* descriptor error */ -+#define DMA_RX_ERROR BIT(15) /* error summary */ -+#define DMA_RX_LEN_MASK 0x3fff0000 -+#define DMA_RX_LEN_SHIFT 16 -+#define DMA_RX_FILT BIT(30) -+#define DMA_RX_OWN BIT(31) /* desc owned by DMA controller */ -+ -+#define DMA_RX1_BSIZE_MASK 0x000007ff -+#define DMA_RX1_BSIZE_SHIFT 0 -+#define DMA_RX1_CHAINED BIT(24) -+#define DMA_RX1_RER BIT(25) -+ -+#define DMA_TX_ERR_UNDER BIT(1) /* underflow error */ -+#define DMA_TX_ERR_DEFER BIT(2) /* excessive deferral */ -+#define DMA_TX_COL_MASK 0x78 -+#define DMA_TX_COL_SHIFT 3 -+#define DMA_TX_ERR_HB BIT(7) /* hearbeat failure */ -+#define DMA_TX_ERR_COL BIT(8) /* excessive collisions */ -+#define DMA_TX_ERR_LATE BIT(9) /* late collision */ -+#define DMA_TX_ERR_LINK BIT(10) /* no carrier */ -+#define DMA_TX_ERR_LOSS BIT(11) /* loss of carrier */ -+#define DMA_TX_ERR_JABBER BIT(14) /* transmit jabber timeout */ -+#define DMA_TX_ERROR BIT(15) /* frame aborted */ -+#define DMA_TX_OWN BIT(31) /* descr owned by DMA controller */ -+ -+#define DMA_TX1_BSIZE_MASK 0x000007ff -+#define DMA_TX1_BSIZE_SHIFT 0 -+#define DMA_TX1_CHAINED BIT(24) /* chained descriptors */ -+#define DMA_TX1_TER BIT(25) /* transmit end of ring */ -+#define DMA_TX1_FS BIT(29) /* first segment */ -+#define DMA_TX1_LS BIT(30) /* last segment */ -+#define DMA_TX1_IC BIT(31) /* interrupt on completion */ -+ -+#define RCVPKT_LENGTH(X) (X >> 16) /* Received pkt Length */ -+ -+#define MAC_CONTROL_RE BIT(2) /* receive enable */ -+#define MAC_CONTROL_TE BIT(3) /* transmit enable */ -+#define MAC_CONTROL_DC BIT(5) /* Deferral check */ -+#define MAC_CONTROL_ASTP BIT(8) /* Auto pad strip */ -+#define MAC_CONTROL_DRTY BIT(10) /* Disable retry */ -+#define MAC_CONTROL_DBF BIT(11) /* Disable bcast frames */ -+#define MAC_CONTROL_LCC BIT(12) /* late collision ctrl */ -+#define MAC_CONTROL_HP BIT(13) /* Hash Perfect filtering */ -+#define MAC_CONTROL_HASH BIT(14) /* Unicast hash filtering */ -+#define MAC_CONTROL_HO BIT(15) /* Hash only filtering */ -+#define MAC_CONTROL_PB BIT(16) /* Pass Bad frames */ -+#define MAC_CONTROL_IF BIT(17) /* Inverse filtering */ -+#define MAC_CONTROL_PR BIT(18) /* promiscuous mode (valid frames only) */ -+#define MAC_CONTROL_PM BIT(19) /* pass multicast */ -+#define MAC_CONTROL_F BIT(20) /* full-duplex */ -+#define MAC_CONTROL_DRO BIT(23) /* Disable Receive Own */ -+#define MAC_CONTROL_HBD BIT(28) /* heart-beat disabled (MUST BE SET) */ -+#define MAC_CONTROL_BLE BIT(30) /* big endian mode */ -+#define MAC_CONTROL_RA BIT(31) /* receive all (valid and invalid frames) */ -+ -+#define MII_ADDR_BUSY BIT(0) -+#define MII_ADDR_WRITE BIT(1) -+#define MII_ADDR_REG_SHIFT 6 -+#define MII_ADDR_PHY_SHIFT 11 -+#define MII_DATA_SHIFT 0 -+ -+#define FLOW_CONTROL_FCE BIT(1) -+ -+#define DMA_BUS_MODE_SWR BIT(0) /* software reset */ -+#define DMA_BUS_MODE_BLE BIT(7) /* big endian mode */ -+#define DMA_BUS_MODE_PBL_SHIFT 8 /* programmable burst length 32 */ -+#define DMA_BUS_MODE_DBO BIT(20) /* big-endian descriptors */ -+ -+#define DMA_STATUS_TI BIT(0) /* transmit interrupt */ -+#define DMA_STATUS_TPS BIT(1) /* transmit process stopped */ -+#define DMA_STATUS_TU BIT(2) /* transmit buffer unavailable */ -+#define DMA_STATUS_TJT BIT(3) /* transmit buffer timeout */ -+#define DMA_STATUS_UNF BIT(5) /* transmit underflow */ -+#define DMA_STATUS_RI BIT(6) /* receive interrupt */ -+#define DMA_STATUS_RU BIT(7) /* receive buffer unavailable */ -+#define DMA_STATUS_RPS BIT(8) /* receive process stopped */ -+#define DMA_STATUS_ETI BIT(10) /* early transmit interrupt */ -+#define DMA_STATUS_FBE BIT(13) /* fatal bus interrupt */ -+#define DMA_STATUS_ERI BIT(14) /* early receive interrupt */ -+#define DMA_STATUS_AIS BIT(15) /* abnormal interrupt summary */ -+#define DMA_STATUS_NIS BIT(16) /* normal interrupt summary */ -+#define DMA_STATUS_RS_SHIFT 17 /* receive process state */ -+#define DMA_STATUS_TS_SHIFT 20 /* transmit process state */ -+#define DMA_STATUS_EB_SHIFT 23 /* error bits */ -+ -+#define DMA_CONTROL_SR BIT(1) /* start receive */ -+#define DMA_CONTROL_ST BIT(13) /* start transmit */ -+#define DMA_CONTROL_SF BIT(21) /* store and forward */ -+ -+ -+typedef struct { -+ volatile unsigned int status; // OWN, Device control and status. -+ volatile unsigned int devcs; // pkt Control bits + Length -+ volatile unsigned int addr; // Current Address. -+ volatile unsigned int descr; // Next descriptor in chain. -+} ar231x_descr_t; -+ -+ -+ -+// -+// New Combo structure for Both Eth0 AND eth1 -+// -+typedef struct { -+ volatile unsigned int mac_control; /* 0x00 */ -+ volatile unsigned int mac_addr[2]; /* 0x04 - 0x08 */ -+ volatile unsigned int mcast_table[2]; /* 0x0c - 0x10 */ -+ volatile unsigned int mii_addr; /* 0x14 */ -+ volatile unsigned int mii_data; /* 0x18 */ -+ volatile unsigned int flow_control; /* 0x1c */ -+ volatile unsigned int vlan_tag; /* 0x20 */ -+ volatile unsigned int pad[7]; /* 0x24 - 0x3c */ -+ volatile unsigned int ucast_table[8]; /* 0x40-0x5c */ -+ -+} ETHERNET_STRUCT; -+ -+/******************************************************************** -+ * Interrupt controller -+ ********************************************************************/ -+ -+typedef struct { -+ volatile unsigned int wdog_control; /* 0x08 */ -+ volatile unsigned int wdog_timer; /* 0x0c */ -+ volatile unsigned int misc_status; /* 0x10 */ -+ volatile unsigned int misc_mask; /* 0x14 */ -+ volatile unsigned int global_status; /* 0x18 */ -+ volatile unsigned int reserved; /* 0x1c */ -+ volatile unsigned int reset_control; /* 0x20 */ -+} INTERRUPT; -+ -+/******************************************************************** -+ * DMA controller -+ ********************************************************************/ -+typedef struct { -+ volatile unsigned int bus_mode; /* 0x00 (CSR0) */ -+ volatile unsigned int xmt_poll; /* 0x04 (CSR1) */ -+ volatile unsigned int rcv_poll; /* 0x08 (CSR2) */ -+ volatile unsigned int rcv_base; /* 0x0c (CSR3) */ -+ volatile unsigned int xmt_base; /* 0x10 (CSR4) */ -+ volatile unsigned int status; /* 0x14 (CSR5) */ -+ volatile unsigned int control; /* 0x18 (CSR6) */ -+ volatile unsigned int intr_ena; /* 0x1c (CSR7) */ -+ volatile unsigned int rcv_missed; /* 0x20 (CSR8) */ -+ volatile unsigned int reserved[11]; /* 0x24-0x4c (CSR9-19) */ -+ volatile unsigned int cur_tx_buf_addr; /* 0x50 (CSR20) */ -+ volatile unsigned int cur_rx_buf_addr; /* 0x50 (CSR21) */ -+} DMA; -+ -+/* -+ * Struct private for the Sibyte. -+ * -+ * Elements are grouped so variables used by the tx handling goes -+ * together, and will go into the same cache lines etc. in order to -+ * avoid cache line contention between the rx and tx handling on SMP. -+ * -+ * Frequently accessed variables are put at the beginning of the -+ * struct to help the compiler generate better/shorter code. -+ */ -+struct ar231x_private { -+ struct net_device *dev; -+ int (*rx)(struct sk_buff *skb); -+ -+ int version; -+ u32 mb[2]; -+ -+ volatile ETHERNET_STRUCT *phy_regs; -+ volatile ETHERNET_STRUCT *eth_regs; -+ volatile DMA *dma_regs; -+ volatile u32 *int_regs; -+ struct ar231x_eth *cfg; -+ -+ spinlock_t lock; /* Serialise access to device */ -+ -+ /* -+ * RX and TX descriptors, must be adjacent -+ */ -+ ar231x_descr_t *rx_ring; -+ ar231x_descr_t *tx_ring; -+ -+ -+ struct sk_buff **rx_skb; -+ struct sk_buff **tx_skb; -+ -+ /* -+ * RX elements -+ */ -+ u32 rx_skbprd; -+ u32 cur_rx; -+ -+ /* -+ * TX elements -+ */ -+ u32 tx_prd; -+ u32 tx_csm; -+ -+ /* -+ * Misc elements -+ */ -+ char name[48]; -+ struct { -+ u32 address; -+ u32 length; -+ char *mapping; -+ } desc; -+ -+ -+ struct timer_list link_timer; -+ unsigned short phy; /* merlot phy = 1, samsung phy = 0x1f */ -+ unsigned short mac; -+ unsigned short link; /* 0 - link down, 1 - link up */ -+ u16 phyData; -+ -+ struct tasklet_struct rx_tasklet; -+ int unloading; -+ -+ struct phy_device *phy_dev; -+ struct mii_bus *mii_bus; -+ int oldduplex; -+}; -+ -+ -+/* -+ * Prototypes -+ */ -+static int ar231x_init(struct net_device *dev); -+#ifdef TX_TIMEOUT -+static void ar231x_tx_timeout(struct net_device *dev); -+#endif -+static int ar231x_restart(struct net_device *dev); -+static void ar231x_load_rx_ring(struct net_device *dev, int bufs); -+static irqreturn_t ar231x_interrupt(int irq, void *dev_id); -+static int ar231x_open(struct net_device *dev); -+static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev); -+static int ar231x_close(struct net_device *dev); -+static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr, -+ int cmd); -+static void ar231x_init_cleanup(struct net_device *dev); -+static int ar231x_setup_timer(struct net_device *dev); -+static void ar231x_link_timer_fn(unsigned long data); -+static void ar231x_check_link(struct net_device *dev); -+#endif /* _AR2313_H_ */ -diff -Nur linux-2.6.37.orig/drivers/watchdog/Kconfig linux-2.6.37/drivers/watchdog/Kconfig ---- linux-2.6.37.orig/drivers/watchdog/Kconfig 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/watchdog/Kconfig 2011-05-15 19:24:57.000000000 +0200 -@@ -930,6 +930,12 @@ - To compile this driver as a loadable module, choose M here. - The module will be called bcm63xx_wdt. - -+config ATHEROS_WDT -+ tristate "Atheros wisoc Watchdog Timer" -+ depends on ATHEROS_AR231X -+ help -+ Hardware driver for the Atheros wisoc Watchdog Timer. -+ - # PARISC Architecture - - # POWERPC Architecture -diff -Nur linux-2.6.37.orig/drivers/watchdog/Makefile linux-2.6.37/drivers/watchdog/Makefile ---- linux-2.6.37.orig/drivers/watchdog/Makefile 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/watchdog/Makefile 2011-05-15 19:24:57.000000000 +0200 -@@ -116,6 +116,7 @@ - obj-$(CONFIG_PNX833X_WDT) += pnx833x_wdt.o - obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o - obj-$(CONFIG_AR7_WDT) += ar7_wdt.o -+obj-$(CONFIG_ATHEROS_WDT) += ar2315-wtd.o - obj-$(CONFIG_TXX9_WDT) += txx9wdt.o - obj-$(CONFIG_OCTEON_WDT) += octeon-wdt.o - octeon-wdt-y := octeon-wdt-main.o octeon-wdt-nmi.o -diff -Nur linux-2.6.37.orig/drivers/watchdog/ar2315-wtd.c linux-2.6.37/drivers/watchdog/ar2315-wtd.c ---- linux-2.6.37.orig/drivers/watchdog/ar2315-wtd.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/drivers/watchdog/ar2315-wtd.c 2011-05-15 19:24:57.000000000 +0200 -@@ -0,0 +1,200 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ * -+ * Copyright (C) 2008 John Crispin -+ * Based on EP93xx and ifxmips wdt driver -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define CLOCK_RATE 40000000 -+#define HEARTBEAT(x) (x < 1 || x > 90)?(20):(x) -+ -+static int wdt_timeout = 20; -+static int started = 0; -+static int in_use = 0; -+ -+static void -+ar2315_wdt_enable(void) -+{ -+ ar231x_write_reg(AR2315_WD, wdt_timeout * CLOCK_RATE); -+ ar231x_write_reg(AR2315_ISR, 0x80); -+} -+ -+static ssize_t -+ar2315_wdt_write(struct file *file, const char __user *data, size_t len, loff_t *ppos) -+{ -+ if(len) -+ ar2315_wdt_enable(); -+ return len; -+} -+ -+static int -+ar2315_wdt_open(struct inode *inode, struct file *file) -+{ -+ if(in_use) -+ return -EBUSY; -+ ar2315_wdt_enable(); -+ in_use = started = 1; -+ return nonseekable_open(inode, file); -+} -+ -+static int -+ar2315_wdt_release(struct inode *inode, struct file *file) -+{ -+ in_use = 0; -+ return 0; -+} -+ -+static irqreturn_t -+ar2315_wdt_interrupt(int irq, void *dev_id) -+{ -+ if(started) -+ { -+ printk(KERN_CRIT "watchdog expired, rebooting system\n"); -+ emergency_restart(); -+ } else { -+ ar231x_write_reg(AR2315_WDC, 0); -+ ar231x_write_reg(AR2315_WD, 0); -+ ar231x_write_reg(AR2315_ISR, 0x80); -+ } -+ return IRQ_HANDLED; -+} -+ -+static struct watchdog_info ident = { -+ .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, -+ .identity = "ar2315 Watchdog", -+}; -+ -+static int -+ar2315_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) -+{ -+ int new_wdt_timeout; -+ int ret = -ENOIOCTLCMD; -+ -+ switch(cmd) -+ { -+ case WDIOC_GETSUPPORT: -+ ret = copy_to_user((struct watchdog_info __user *)arg, &ident, sizeof(ident)) ? -EFAULT : 0; -+ break; -+ -+ case WDIOC_KEEPALIVE: -+ ar2315_wdt_enable(); -+ ret = 0; -+ break; -+ -+ case WDIOC_SETTIMEOUT: -+ if((ret = get_user(new_wdt_timeout, (int __user *)arg))) -+ break; -+ wdt_timeout = HEARTBEAT(new_wdt_timeout); -+ ar2315_wdt_enable(); -+ break; -+ -+ case WDIOC_GETTIMEOUT: -+ ret = put_user(wdt_timeout, (int __user *)arg); -+ break; -+ } -+ return ret; -+} -+ -+static struct file_operations ar2315_wdt_fops = { -+ .owner = THIS_MODULE, -+ .llseek = no_llseek, -+ .write = ar2315_wdt_write, -+ .unlocked_ioctl = ar2315_wdt_ioctl, -+ .open = ar2315_wdt_open, -+ .release = ar2315_wdt_release, -+}; -+ -+static struct miscdevice ar2315_wdt_miscdev = { -+ .minor = WATCHDOG_MINOR, -+ .name = "watchdog", -+ .fops = &ar2315_wdt_fops, -+}; -+ -+static int -+ar2315_wdt_probe(struct platform_device *dev) -+{ -+ int ret = 0; -+ -+ ar2315_wdt_enable(); -+ ret = request_irq(AR531X_MISC_IRQ_WATCHDOG, ar2315_wdt_interrupt, IRQF_DISABLED, "ar2315_wdt", NULL); -+ if(ret) -+ { -+ printk(KERN_ERR "ar2315wdt: failed to register inetrrupt\n"); -+ goto out; -+ } -+ -+ ret = misc_register(&ar2315_wdt_miscdev); -+ if(ret) -+ printk(KERN_ERR "ar2315wdt: failed to register miscdev\n"); -+ -+out: -+ return ret; -+} -+ -+static int -+ar2315_wdt_remove(struct platform_device *dev) -+{ -+ misc_deregister(&ar2315_wdt_miscdev); -+ free_irq(AR531X_MISC_IRQ_WATCHDOG, NULL); -+ return 0; -+} -+ -+static struct platform_driver ar2315_wdt_driver = { -+ .probe = ar2315_wdt_probe, -+ .remove = ar2315_wdt_remove, -+ .driver = { -+ .name = "ar2315_wdt", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init -+init_ar2315_wdt(void) -+{ -+ int ret = platform_driver_register(&ar2315_wdt_driver); -+ if(ret) -+ printk(KERN_INFO "ar2315_wdt: error registering platfom driver!"); -+ return ret; -+} -+ -+static void __exit -+exit_ar2315_wdt(void) -+{ -+ platform_driver_unregister(&ar2315_wdt_driver); -+} -+ -+module_init(init_ar2315_wdt); -+module_exit(exit_ar2315_wdt); diff --git a/target/linux/patches/2.6.37/aufs2.patch b/target/linux/patches/2.6.37/aufs2.patch deleted file mode 100644 index 7cfe43065..000000000 --- a/target/linux/patches/2.6.37/aufs2.patch +++ /dev/null @@ -1,28523 +0,0 @@ -diff -Nur linux-2.6.37.orig/fs/Kconfig linux-2.6.37/fs/Kconfig ---- linux-2.6.37.orig/fs/Kconfig 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/fs/Kconfig 2011-01-11 20:15:11.000000000 +0100 -@@ -191,6 +191,7 @@ - source "fs/sysv/Kconfig" - source "fs/ufs/Kconfig" - source "fs/exofs/Kconfig" -+source "fs/aufs/Kconfig" - - endif # MISC_FILESYSTEMS - -diff -Nur linux-2.6.37.orig/fs/Makefile linux-2.6.37/fs/Makefile ---- linux-2.6.37.orig/fs/Makefile 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/fs/Makefile 2011-01-11 20:15:11.000000000 +0100 -@@ -121,3 +121,4 @@ - obj-$(CONFIG_GFS2_FS) += gfs2/ - obj-$(CONFIG_EXOFS_FS) += exofs/ - obj-$(CONFIG_CEPH_FS) += ceph/ -+obj-$(CONFIG_AUFS_FS) += aufs/ -diff -Nur linux-2.6.37.orig/fs/aufs/Kconfig linux-2.6.37/fs/aufs/Kconfig ---- linux-2.6.37.orig/fs/aufs/Kconfig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/Kconfig 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,180 @@ -+config AUFS_FS -+ tristate "Aufs (Advanced multi layered unification filesystem) support" -+ depends on EXPERIMENTAL -+ help -+ Aufs is a stackable unification filesystem such as Unionfs, -+ which unifies several directories and provides a merged single -+ directory. -+ In the early days, aufs was entirely re-designed and -+ re-implemented Unionfs Version 1.x series. Introducing many -+ original ideas, approaches and improvements, it becomes totally -+ different from Unionfs while keeping the basic features. -+ -+if AUFS_FS -+choice -+ prompt "Maximum number of branches" -+ default AUFS_BRANCH_MAX_127 -+ help -+ Specifies the maximum number of branches (or member directories) -+ in a single aufs. The larger value consumes more system -+ resources and has a minor impact to performance. -+config AUFS_BRANCH_MAX_127 -+ bool "127" -+ help -+ Specifies the maximum number of branches (or member directories) -+ in a single aufs. The larger value consumes more system -+ resources and has a minor impact to performance. -+config AUFS_BRANCH_MAX_511 -+ bool "511" -+ help -+ Specifies the maximum number of branches (or member directories) -+ in a single aufs. The larger value consumes more system -+ resources and has a minor impact to performance. -+config AUFS_BRANCH_MAX_1023 -+ bool "1023" -+ help -+ Specifies the maximum number of branches (or member directories) -+ in a single aufs. The larger value consumes more system -+ resources and has a minor impact to performance. -+config AUFS_BRANCH_MAX_32767 -+ bool "32767" -+ help -+ Specifies the maximum number of branches (or member directories) -+ in a single aufs. The larger value consumes more system -+ resources and has a minor impact to performance. -+endchoice -+ -+config AUFS_SBILIST -+ bool -+ depends on AUFS_MAGIC_SYSRQ || PROC_FS -+ default y -+ help -+ Automatic configuration for internal use. -+ When aufs supports Magic SysRq or /proc, enabled automatically. -+ -+config AUFS_HNOTIFY -+ bool "Detect direct branch access (bypassing aufs)" -+ help -+ If you want to modify files on branches directly, eg. bypassing aufs, -+ and want aufs to detect the changes of them fully, then enable this -+ option and use 'udba=notify' mount option. -+ Currently there is only one available configuration, "fsnotify". -+ It will have a negative impact to the performance. -+ See detail in aufs.5. -+ -+choice -+ prompt "method" if AUFS_HNOTIFY -+ default AUFS_HFSNOTIFY -+config AUFS_HFSNOTIFY -+ bool "fsnotify" -+ select FSNOTIFY -+endchoice -+ -+config AUFS_EXPORT -+ bool "NFS-exportable aufs" -+ depends on (AUFS_FS = y && EXPORTFS = y) || (AUFS_FS = m && EXPORTFS) -+ help -+ If you want to export your mounted aufs via NFS, then enable this -+ option. There are several requirements for this configuration. -+ See detail in aufs.5. -+ -+config AUFS_INO_T_64 -+ bool -+ depends on AUFS_EXPORT -+ depends on 64BIT && !(ALPHA || S390) -+ default y -+ help -+ Automatic configuration for internal use. -+ /* typedef unsigned long/int __kernel_ino_t */ -+ /* alpha and s390x are int */ -+ -+config AUFS_RDU -+ bool "Readdir in userspace" -+ help -+ Aufs has two methods to provide a merged view for a directory, -+ by a user-space library and by kernel-space natively. The latter -+ is always enabled but sometimes large and slow. -+ If you enable this option, install the library in aufs2-util -+ package, and set some environment variables for your readdir(3), -+ then the work will be handled in user-space which generally -+ shows better performance in most cases. -+ See detail in aufs.5. -+ -+config AUFS_SP_IATTR -+ bool "Respect the attributes (mtime/ctime mainly) of special files" -+ help -+ When you write something to a special file, some attributes of it -+ (mtime/ctime mainly) may be updated. Generally such updates are -+ less important (actually some device drivers and NFS ignore -+ it). But some applications (such like test program) requires -+ such updates. If you need these updates, then enable this -+ configuration which introduces some overhead. -+ Currently this configuration handles FIFO only. -+ -+config AUFS_SHWH -+ bool "Show whiteouts" -+ help -+ If you want to make the whiteouts in aufs visible, then enable -+ this option and specify 'shwh' mount option. Although it may -+ sounds like philosophy or something, but in technically it -+ simply shows the name of whiteout with keeping its behaviour. -+ -+config AUFS_BR_RAMFS -+ bool "Ramfs (initramfs/rootfs) as an aufs branch" -+ help -+ If you want to use ramfs as an aufs branch fs, then enable this -+ option. Generally tmpfs is recommended. -+ Aufs prohibited them to be a branch fs by default, because -+ initramfs becomes unusable after switch_root or something -+ generally. If you sets initramfs as an aufs branch and boot your -+ system by switch_root, you will meet a problem easily since the -+ files in initramfs may be inaccessible. -+ Unless you are going to use ramfs as an aufs branch fs without -+ switch_root or something, leave it N. -+ -+config AUFS_BR_FUSE -+ bool "Fuse fs as an aufs branch" -+ depends on FUSE_FS -+ select AUFS_POLL -+ help -+ If you want to use fuse-based userspace filesystem as an aufs -+ branch fs, then enable this option. -+ It implements the internal poll(2) operation which is -+ implemented by fuse only (curretnly). -+ -+config AUFS_POLL -+ bool -+ help -+ Automatic configuration for internal use. -+ -+config AUFS_BR_HFSPLUS -+ bool "Hfsplus as an aufs branch" -+ depends on HFSPLUS_FS -+ default y -+ help -+ If you want to use hfsplus fs as an aufs branch fs, then enable -+ this option. This option introduces a small overhead at -+ copying-up a file on hfsplus. -+ -+config AUFS_BDEV_LOOP -+ bool -+ depends on BLK_DEV_LOOP -+ default y -+ help -+ Automatic configuration for internal use. -+ Convert =[ym] into =y. -+ -+config AUFS_DEBUG -+ bool "Debug aufs" -+ help -+ Enable this to compile aufs internal debug code. -+ It will have a negative impact to the performance. -+ -+config AUFS_MAGIC_SYSRQ -+ bool -+ depends on AUFS_DEBUG && MAGIC_SYSRQ -+ default y -+ help -+ Automatic configuration for internal use. -+ When aufs supports Magic SysRq, enabled automatically. -+endif -diff -Nur linux-2.6.37.orig/fs/aufs/Makefile linux-2.6.37/fs/aufs/Makefile ---- linux-2.6.37.orig/fs/aufs/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/Makefile 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,38 @@ -+ -+include ${src}/magic.mk -+ifeq (${CONFIG_AUFS_FS},m) -+include ${src}/conf.mk -+endif -+-include ${src}/priv_def.mk -+ -+# cf. include/linux/kernel.h -+# enable pr_debug -+ccflags-y += -DDEBUG -+# sparse doesn't allow spaces -+ccflags-y += -D'pr_fmt(fmt)=AUFS_NAME"\040%s:%d:%s[%d]:\040"fmt,__func__,__LINE__,current->comm,current->pid' -+ -+obj-$(CONFIG_AUFS_FS) += aufs.o -+aufs-y := module.o sbinfo.o super.o branch.o xino.o sysaufs.o opts.o \ -+ wkq.o vfsub.o dcsub.o \ -+ cpup.o whout.o wbr_policy.o \ -+ dinfo.o dentry.o \ -+ dynop.o \ -+ finfo.o file.o f_op.o \ -+ dir.o vdir.o \ -+ iinfo.o inode.o i_op.o i_op_add.o i_op_del.o i_op_ren.o \ -+ ioctl.o -+ -+# all are boolean -+aufs-$(CONFIG_PROC_FS) += procfs.o plink.o -+aufs-$(CONFIG_SYSFS) += sysfs.o -+aufs-$(CONFIG_DEBUG_FS) += dbgaufs.o -+aufs-$(CONFIG_AUFS_BDEV_LOOP) += loop.o -+aufs-$(CONFIG_AUFS_HNOTIFY) += hnotify.o -+aufs-$(CONFIG_AUFS_HFSNOTIFY) += hfsnotify.o -+aufs-$(CONFIG_AUFS_EXPORT) += export.o -+aufs-$(CONFIG_AUFS_POLL) += poll.o -+aufs-$(CONFIG_AUFS_RDU) += rdu.o -+aufs-$(CONFIG_AUFS_SP_IATTR) += f_op_sp.o -+aufs-$(CONFIG_AUFS_BR_HFSPLUS) += hfsplus.o -+aufs-$(CONFIG_AUFS_DEBUG) += debug.o -+aufs-$(CONFIG_AUFS_MAGIC_SYSRQ) += sysrq.o -diff -Nur linux-2.6.37.orig/fs/aufs/aufs.h linux-2.6.37/fs/aufs/aufs.h ---- linux-2.6.37.orig/fs/aufs/aufs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/aufs.h 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,61 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * all header files -+ */ -+ -+#ifndef __AUFS_H__ -+#define __AUFS_H__ -+ -+#ifdef __KERNEL__ -+ -+#define AuStub(type, name, body, ...) \ -+ static inline type name(__VA_ARGS__) { body; } -+ -+#define AuStubVoid(name, ...) \ -+ AuStub(void, name, , __VA_ARGS__) -+#define AuStubInt0(name, ...) \ -+ AuStub(int, name, return 0, __VA_ARGS__) -+ -+#include "debug.h" -+ -+#include "branch.h" -+#include "cpup.h" -+#include "dcsub.h" -+#include "dbgaufs.h" -+#include "dentry.h" -+#include "dir.h" -+#include "dynop.h" -+#include "file.h" -+#include "fstype.h" -+#include "inode.h" -+#include "loop.h" -+#include "module.h" -+/* never include ./mtx.h */ -+#include "opts.h" -+#include "rwsem.h" -+#include "spl.h" -+#include "super.h" -+#include "sysaufs.h" -+#include "vfsub.h" -+#include "whout.h" -+#include "wkq.h" -+ -+#endif /* __KERNEL__ */ -+#endif /* __AUFS_H__ */ -diff -Nur linux-2.6.37.orig/fs/aufs/branch.c linux-2.6.37/fs/aufs/branch.c ---- linux-2.6.37.orig/fs/aufs/branch.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/branch.c 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,1071 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * branch management -+ */ -+ -+#include -+#include -+#include "aufs.h" -+ -+/* -+ * free a single branch -+ */ -+static void au_br_do_free(struct au_branch *br) -+{ -+ int i; -+ struct au_wbr *wbr; -+ struct au_dykey **key; -+ -+ au_hnotify_fin_br(br); -+ -+ if (br->br_xino.xi_file) -+ fput(br->br_xino.xi_file); -+ mutex_destroy(&br->br_xino.xi_nondir_mtx); -+ -+ AuDebugOn(atomic_read(&br->br_count)); -+ -+ wbr = br->br_wbr; -+ if (wbr) { -+ for (i = 0; i < AuBrWh_Last; i++) -+ dput(wbr->wbr_wh[i]); -+ AuDebugOn(atomic_read(&wbr->wbr_wh_running)); -+ AuRwDestroy(&wbr->wbr_wh_rwsem); -+ } -+ -+ key = br->br_dykey; -+ for (i = 0; i < AuBrDynOp; i++, key++) -+ if (*key) -+ au_dy_put(*key); -+ else -+ break; -+ -+ mntput(br->br_mnt); -+ kfree(wbr); -+ kfree(br); -+} -+ -+/* -+ * frees all branches -+ */ -+void au_br_free(struct au_sbinfo *sbinfo) -+{ -+ aufs_bindex_t bmax; -+ struct au_branch **br; -+ -+ AuRwMustWriteLock(&sbinfo->si_rwsem); -+ -+ bmax = sbinfo->si_bend + 1; -+ br = sbinfo->si_branch; -+ while (bmax--) -+ au_br_do_free(*br++); -+} -+ -+/* -+ * find the index of a branch which is specified by @br_id. -+ */ -+int au_br_index(struct super_block *sb, aufs_bindex_t br_id) -+{ -+ aufs_bindex_t bindex, bend; -+ -+ bend = au_sbend(sb); -+ for (bindex = 0; bindex <= bend; bindex++) -+ if (au_sbr_id(sb, bindex) == br_id) -+ return bindex; -+ return -1; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * add a branch -+ */ -+ -+static int test_overlap(struct super_block *sb, struct dentry *h_adding, -+ struct dentry *h_root) -+{ -+ if (unlikely(h_adding == h_root -+ || au_test_loopback_overlap(sb, h_adding))) -+ return 1; -+ if (h_adding->d_sb != h_root->d_sb) -+ return 0; -+ return au_test_subdir(h_adding, h_root) -+ || au_test_subdir(h_root, h_adding); -+} -+ -+/* -+ * returns a newly allocated branch. @new_nbranch is a number of branches -+ * after adding a branch. -+ */ -+static struct au_branch *au_br_alloc(struct super_block *sb, int new_nbranch, -+ int perm) -+{ -+ struct au_branch *add_branch; -+ struct dentry *root; -+ int err; -+ -+ err = -ENOMEM; -+ root = sb->s_root; -+ add_branch = kmalloc(sizeof(*add_branch), GFP_NOFS); -+ if (unlikely(!add_branch)) -+ goto out; -+ -+ err = au_hnotify_init_br(add_branch, perm); -+ if (unlikely(err)) -+ goto out_br; -+ -+ add_branch->br_wbr = NULL; -+ if (au_br_writable(perm)) { -+ /* may be freed separately at changing the branch permission */ -+ add_branch->br_wbr = kmalloc(sizeof(*add_branch->br_wbr), -+ GFP_NOFS); -+ if (unlikely(!add_branch->br_wbr)) -+ goto out_hnotify; -+ } -+ -+ err = au_sbr_realloc(au_sbi(sb), new_nbranch); -+ if (!err) -+ err = au_di_realloc(au_di(root), new_nbranch); -+ if (!err) -+ err = au_ii_realloc(au_ii(root->d_inode), new_nbranch); -+ if (!err) -+ return add_branch; /* success */ -+ -+ kfree(add_branch->br_wbr); -+ -+out_hnotify: -+ au_hnotify_fin_br(add_branch); -+out_br: -+ kfree(add_branch); -+out: -+ return ERR_PTR(err); -+} -+ -+/* -+ * test if the branch permission is legal or not. -+ */ -+static int test_br(struct inode *inode, int brperm, char *path) -+{ -+ int err; -+ -+ err = (au_br_writable(brperm) && IS_RDONLY(inode)); -+ if (!err) -+ goto out; -+ -+ err = -EINVAL; -+ pr_err("write permission for readonly mount or inode, %s\n", path); -+ -+out: -+ return err; -+} -+ -+/* -+ * returns: -+ * 0: success, the caller will add it -+ * plus: success, it is already unified, the caller should ignore it -+ * minus: error -+ */ -+static int test_add(struct super_block *sb, struct au_opt_add *add, int remount) -+{ -+ int err; -+ aufs_bindex_t bend, bindex; -+ struct dentry *root; -+ struct inode *inode, *h_inode; -+ -+ root = sb->s_root; -+ bend = au_sbend(sb); -+ if (unlikely(bend >= 0 -+ && au_find_dbindex(root, add->path.dentry) >= 0)) { -+ err = 1; -+ if (!remount) { -+ err = -EINVAL; -+ pr_err("%s duplicated\n", add->pathname); -+ } -+ goto out; -+ } -+ -+ err = -ENOSPC; /* -E2BIG; */ -+ if (unlikely(AUFS_BRANCH_MAX <= add->bindex -+ || AUFS_BRANCH_MAX - 1 <= bend)) { -+ pr_err("number of branches exceeded %s\n", add->pathname); -+ goto out; -+ } -+ -+ err = -EDOM; -+ if (unlikely(add->bindex < 0 || bend + 1 < add->bindex)) { -+ pr_err("bad index %d\n", add->bindex); -+ goto out; -+ } -+ -+ inode = add->path.dentry->d_inode; -+ err = -ENOENT; -+ if (unlikely(!inode->i_nlink)) { -+ pr_err("no existence %s\n", add->pathname); -+ goto out; -+ } -+ -+ err = -EINVAL; -+ if (unlikely(inode->i_sb == sb)) { -+ pr_err("%s must be outside\n", add->pathname); -+ goto out; -+ } -+ -+ if (unlikely(au_test_fs_unsuppoted(inode->i_sb))) { -+ pr_err("unsupported filesystem, %s (%s)\n", -+ add->pathname, au_sbtype(inode->i_sb)); -+ goto out; -+ } -+ -+ err = test_br(add->path.dentry->d_inode, add->perm, add->pathname); -+ if (unlikely(err)) -+ goto out; -+ -+ if (bend < 0) -+ return 0; /* success */ -+ -+ err = -EINVAL; -+ for (bindex = 0; bindex <= bend; bindex++) -+ if (unlikely(test_overlap(sb, add->path.dentry, -+ au_h_dptr(root, bindex)))) { -+ pr_err("%s is overlapped\n", add->pathname); -+ goto out; -+ } -+ -+ err = 0; -+ if (au_opt_test(au_mntflags(sb), WARN_PERM)) { -+ h_inode = au_h_dptr(root, 0)->d_inode; -+ if ((h_inode->i_mode & S_IALLUGO) != (inode->i_mode & S_IALLUGO) -+ || h_inode->i_uid != inode->i_uid -+ || h_inode->i_gid != inode->i_gid) -+ pr_warning("uid/gid/perm %s %u/%u/0%o, %u/%u/0%o\n", -+ add->pathname, -+ inode->i_uid, inode->i_gid, -+ (inode->i_mode & S_IALLUGO), -+ h_inode->i_uid, h_inode->i_gid, -+ (h_inode->i_mode & S_IALLUGO)); -+ } -+ -+out: -+ return err; -+} -+ -+/* -+ * initialize or clean the whiteouts for an adding branch -+ */ -+static int au_br_init_wh(struct super_block *sb, struct au_branch *br, -+ int new_perm, struct dentry *h_root) -+{ -+ int err, old_perm; -+ aufs_bindex_t bindex; -+ struct mutex *h_mtx; -+ struct au_wbr *wbr; -+ struct au_hinode *hdir; -+ -+ wbr = br->br_wbr; -+ old_perm = br->br_perm; -+ br->br_perm = new_perm; -+ hdir = NULL; -+ h_mtx = NULL; -+ bindex = au_br_index(sb, br->br_id); -+ if (0 <= bindex) { -+ hdir = au_hi(sb->s_root->d_inode, bindex); -+ au_hn_imtx_lock_nested(hdir, AuLsc_I_PARENT); -+ } else { -+ h_mtx = &h_root->d_inode->i_mutex; -+ mutex_lock_nested(h_mtx, AuLsc_I_PARENT); -+ } -+ if (!wbr) -+ err = au_wh_init(h_root, br, sb); -+ else { -+ wbr_wh_write_lock(wbr); -+ err = au_wh_init(h_root, br, sb); -+ wbr_wh_write_unlock(wbr); -+ } -+ if (hdir) -+ au_hn_imtx_unlock(hdir); -+ else -+ mutex_unlock(h_mtx); -+ br->br_perm = old_perm; -+ -+ if (!err && wbr && !au_br_writable(new_perm)) { -+ kfree(wbr); -+ br->br_wbr = NULL; -+ } -+ -+ return err; -+} -+ -+static int au_wbr_init(struct au_branch *br, struct super_block *sb, -+ int perm, struct path *path) -+{ -+ int err; -+ struct kstatfs kst; -+ struct au_wbr *wbr; -+ struct dentry *h_dentry; -+ -+ wbr = br->br_wbr; -+ au_rw_init(&wbr->wbr_wh_rwsem); -+ memset(wbr->wbr_wh, 0, sizeof(wbr->wbr_wh)); -+ atomic_set(&wbr->wbr_wh_running, 0); -+ wbr->wbr_bytes = 0; -+ -+ /* -+ * a limit for rmdir/rename a dir -+ * cf. AUFS_MAX_NAMELEN in include/linux/aufs_type.h -+ */ -+ err = vfs_statfs(path, &kst); -+ if (unlikely(err)) -+ goto out; -+ err = -EINVAL; -+ h_dentry = path->dentry; -+ if (kst.f_namelen >= NAME_MAX) -+ err = au_br_init_wh(sb, br, perm, h_dentry); -+ else -+ pr_err("%.*s(%s), unsupported namelen %ld\n", -+ AuDLNPair(h_dentry), au_sbtype(h_dentry->d_sb), -+ kst.f_namelen); -+ -+out: -+ return err; -+} -+ -+/* intialize a new branch */ -+static int au_br_init(struct au_branch *br, struct super_block *sb, -+ struct au_opt_add *add) -+{ -+ int err; -+ -+ err = 0; -+ memset(&br->br_xino, 0, sizeof(br->br_xino)); -+ mutex_init(&br->br_xino.xi_nondir_mtx); -+ br->br_perm = add->perm; -+ br->br_mnt = add->path.mnt; /* set first, mntget() later */ -+ spin_lock_init(&br->br_dykey_lock); -+ memset(br->br_dykey, 0, sizeof(br->br_dykey)); -+ atomic_set(&br->br_count, 0); -+ br->br_xino_upper = AUFS_XINO_TRUNC_INIT; -+ atomic_set(&br->br_xino_running, 0); -+ br->br_id = au_new_br_id(sb); -+ AuDebugOn(br->br_id < 0); -+ -+ if (au_br_writable(add->perm)) { -+ err = au_wbr_init(br, sb, add->perm, &add->path); -+ if (unlikely(err)) -+ goto out_err; -+ } -+ -+ if (au_opt_test(au_mntflags(sb), XINO)) { -+ err = au_xino_br(sb, br, add->path.dentry->d_inode->i_ino, -+ au_sbr(sb, 0)->br_xino.xi_file, /*do_test*/1); -+ if (unlikely(err)) { -+ AuDebugOn(br->br_xino.xi_file); -+ goto out_err; -+ } -+ } -+ -+ sysaufs_br_init(br); -+ mntget(add->path.mnt); -+ goto out; /* success */ -+ -+out_err: -+ br->br_mnt = NULL; -+out: -+ return err; -+} -+ -+static void au_br_do_add_brp(struct au_sbinfo *sbinfo, aufs_bindex_t bindex, -+ struct au_branch *br, aufs_bindex_t bend, -+ aufs_bindex_t amount) -+{ -+ struct au_branch **brp; -+ -+ AuRwMustWriteLock(&sbinfo->si_rwsem); -+ -+ brp = sbinfo->si_branch + bindex; -+ memmove(brp + 1, brp, sizeof(*brp) * amount); -+ *brp = br; -+ sbinfo->si_bend++; -+ if (unlikely(bend < 0)) -+ sbinfo->si_bend = 0; -+} -+ -+static void au_br_do_add_hdp(struct au_dinfo *dinfo, aufs_bindex_t bindex, -+ aufs_bindex_t bend, aufs_bindex_t amount) -+{ -+ struct au_hdentry *hdp; -+ -+ AuRwMustWriteLock(&dinfo->di_rwsem); -+ -+ hdp = dinfo->di_hdentry + bindex; -+ memmove(hdp + 1, hdp, sizeof(*hdp) * amount); -+ au_h_dentry_init(hdp); -+ dinfo->di_bend++; -+ if (unlikely(bend < 0)) -+ dinfo->di_bstart = 0; -+} -+ -+static void au_br_do_add_hip(struct au_iinfo *iinfo, aufs_bindex_t bindex, -+ aufs_bindex_t bend, aufs_bindex_t amount) -+{ -+ struct au_hinode *hip; -+ -+ AuRwMustWriteLock(&iinfo->ii_rwsem); -+ -+ hip = iinfo->ii_hinode + bindex; -+ memmove(hip + 1, hip, sizeof(*hip) * amount); -+ hip->hi_inode = NULL; -+ au_hn_init(hip); -+ iinfo->ii_bend++; -+ if (unlikely(bend < 0)) -+ iinfo->ii_bstart = 0; -+} -+ -+static void au_br_do_add(struct super_block *sb, struct dentry *h_dentry, -+ struct au_branch *br, aufs_bindex_t bindex) -+{ -+ struct dentry *root; -+ struct inode *root_inode; -+ aufs_bindex_t bend, amount; -+ -+ root = sb->s_root; -+ root_inode = root->d_inode; -+ bend = au_sbend(sb); -+ amount = bend + 1 - bindex; -+ au_br_do_add_brp(au_sbi(sb), bindex, br, bend, amount); -+ au_br_do_add_hdp(au_di(root), bindex, bend, amount); -+ au_br_do_add_hip(au_ii(root_inode), bindex, bend, amount); -+ au_set_h_dptr(root, bindex, dget(h_dentry)); -+ au_set_h_iptr(root_inode, bindex, au_igrab(h_dentry->d_inode), -+ /*flags*/0); -+} -+ -+int au_br_add(struct super_block *sb, struct au_opt_add *add, int remount) -+{ -+ int err; -+ aufs_bindex_t bend, add_bindex; -+ struct dentry *root, *h_dentry; -+ struct inode *root_inode; -+ struct au_branch *add_branch; -+ -+ root = sb->s_root; -+ root_inode = root->d_inode; -+ IMustLock(root_inode); -+ err = test_add(sb, add, remount); -+ if (unlikely(err < 0)) -+ goto out; -+ if (err) { -+ err = 0; -+ goto out; /* success */ -+ } -+ -+ bend = au_sbend(sb); -+ add_branch = au_br_alloc(sb, bend + 2, add->perm); -+ err = PTR_ERR(add_branch); -+ if (IS_ERR(add_branch)) -+ goto out; -+ -+ err = au_br_init(add_branch, sb, add); -+ if (unlikely(err)) { -+ au_br_do_free(add_branch); -+ goto out; -+ } -+ -+ add_bindex = add->bindex; -+ h_dentry = add->path.dentry; -+ if (!remount) -+ au_br_do_add(sb, h_dentry, add_branch, add_bindex); -+ else { -+ sysaufs_brs_del(sb, add_bindex); -+ au_br_do_add(sb, h_dentry, add_branch, add_bindex); -+ sysaufs_brs_add(sb, add_bindex); -+ } -+ -+ if (!add_bindex) { -+ au_cpup_attr_all(root_inode, /*force*/1); -+ sb->s_maxbytes = h_dentry->d_sb->s_maxbytes; -+ } else -+ au_add_nlink(root_inode, h_dentry->d_inode); -+ -+ /* -+ * this test/set prevents aufs from handling unnecesary notify events -+ * of xino files, in a case of re-adding a writable branch which was -+ * once detached from aufs. -+ */ -+ if (au_xino_brid(sb) < 0 -+ && au_br_writable(add_branch->br_perm) -+ && !au_test_fs_bad_xino(h_dentry->d_sb) -+ && add_branch->br_xino.xi_file -+ && add_branch->br_xino.xi_file->f_dentry->d_parent == h_dentry) -+ au_xino_brid_set(sb, add_branch->br_id); -+ -+out: -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * delete a branch -+ */ -+ -+/* to show the line number, do not make it inlined function */ -+#define AuVerbose(do_info, fmt, ...) do { \ -+ if (do_info) \ -+ pr_info(fmt, ##__VA_ARGS__); \ -+} while (0) -+ -+/* -+ * test if the branch is deletable or not. -+ */ -+static int test_dentry_busy(struct dentry *root, aufs_bindex_t bindex, -+ unsigned int sigen, const unsigned int verbose) -+{ -+ int err, i, j, ndentry; -+ aufs_bindex_t bstart, bend; -+ struct au_dcsub_pages dpages; -+ struct au_dpage *dpage; -+ struct dentry *d; -+ struct inode *inode; -+ -+ err = au_dpages_init(&dpages, GFP_NOFS); -+ if (unlikely(err)) -+ goto out; -+ err = au_dcsub_pages(&dpages, root, NULL, NULL); -+ if (unlikely(err)) -+ goto out_dpages; -+ -+ for (i = 0; !err && i < dpages.ndpage; i++) { -+ dpage = dpages.dpages + i; -+ ndentry = dpage->ndentry; -+ for (j = 0; !err && j < ndentry; j++) { -+ d = dpage->dentries[j]; -+ AuDebugOn(!atomic_read(&d->d_count)); -+ if (!au_digen_test(d, sigen)) { -+ di_read_lock_child(d, AuLock_IR); -+ if (unlikely(au_dbrange_test(d))) { -+ di_read_unlock(d, AuLock_IR); -+ continue; -+ } -+ } else { -+ di_write_lock_child(d); -+ if (unlikely(au_dbrange_test(d))) { -+ di_write_unlock(d); -+ continue; -+ } -+ err = au_reval_dpath(d, sigen); -+ if (!err) -+ di_downgrade_lock(d, AuLock_IR); -+ else { -+ di_write_unlock(d); -+ break; -+ } -+ } -+ -+ /* AuDbgDentry(d); */ -+ inode = d->d_inode; -+ bstart = au_dbstart(d); -+ bend = au_dbend(d); -+ if (bstart <= bindex -+ && bindex <= bend -+ && au_h_dptr(d, bindex) -+ && ((inode && !S_ISDIR(inode->i_mode)) -+ || bstart == bend)) { -+ err = -EBUSY; -+ AuVerbose(verbose, "busy %.*s\n", AuDLNPair(d)); -+ AuDbgDentry(d); -+ } -+ di_read_unlock(d, AuLock_IR); -+ } -+ } -+ -+out_dpages: -+ au_dpages_free(&dpages); -+out: -+ return err; -+} -+ -+static int test_inode_busy(struct super_block *sb, aufs_bindex_t bindex, -+ unsigned int sigen, const unsigned int verbose) -+{ -+ int err; -+ unsigned long long max, ull; -+ struct inode *i, **array; -+ aufs_bindex_t bstart, bend; -+ -+ array = au_iarray_alloc(sb, &max); -+ err = PTR_ERR(array); -+ if (IS_ERR(array)) -+ goto out; -+ -+ err = 0; -+ AuDbg("b%d\n", bindex); -+ for (ull = 0; !err && ull < max; ull++) { -+ i = array[ull]; -+ if (i->i_ino == AUFS_ROOT_INO) -+ continue; -+ -+ /* AuDbgInode(i); */ -+ if (au_iigen(i) == sigen) -+ ii_read_lock_child(i); -+ else { -+ ii_write_lock_child(i); -+ err = au_refresh_hinode_self(i); -+ au_iigen_dec(i); -+ if (!err) -+ ii_downgrade_lock(i); -+ else { -+ ii_write_unlock(i); -+ break; -+ } -+ } -+ -+ bstart = au_ibstart(i); -+ bend = au_ibend(i); -+ if (bstart <= bindex -+ && bindex <= bend -+ && au_h_iptr(i, bindex) -+ && (!S_ISDIR(i->i_mode) || bstart == bend)) { -+ err = -EBUSY; -+ AuVerbose(verbose, "busy i%lu\n", i->i_ino); -+ AuDbgInode(i); -+ } -+ ii_read_unlock(i); -+ } -+ au_iarray_free(array, max); -+ -+out: -+ return err; -+} -+ -+static int test_children_busy(struct dentry *root, aufs_bindex_t bindex, -+ const unsigned int verbose) -+{ -+ int err; -+ unsigned int sigen; -+ -+ sigen = au_sigen(root->d_sb); -+ DiMustNoWaiters(root); -+ IiMustNoWaiters(root->d_inode); -+ di_write_unlock(root); -+ err = test_dentry_busy(root, bindex, sigen, verbose); -+ if (!err) -+ err = test_inode_busy(root->d_sb, bindex, sigen, verbose); -+ di_write_lock_child(root); /* aufs_write_lock() calls ..._child() */ -+ -+ return err; -+} -+ -+static void au_br_do_del_brp(struct au_sbinfo *sbinfo, -+ const aufs_bindex_t bindex, -+ const aufs_bindex_t bend) -+{ -+ struct au_branch **brp, **p; -+ -+ AuRwMustWriteLock(&sbinfo->si_rwsem); -+ -+ brp = sbinfo->si_branch + bindex; -+ if (bindex < bend) -+ memmove(brp, brp + 1, sizeof(*brp) * (bend - bindex)); -+ sbinfo->si_branch[0 + bend] = NULL; -+ sbinfo->si_bend--; -+ -+ p = krealloc(sbinfo->si_branch, sizeof(*p) * bend, GFP_NOFS); -+ if (p) -+ sbinfo->si_branch = p; -+ /* harmless error */ -+} -+ -+static void au_br_do_del_hdp(struct au_dinfo *dinfo, const aufs_bindex_t bindex, -+ const aufs_bindex_t bend) -+{ -+ struct au_hdentry *hdp, *p; -+ -+ AuRwMustWriteLock(&dinfo->di_rwsem); -+ -+ hdp = dinfo->di_hdentry; -+ if (bindex < bend) -+ memmove(hdp + bindex, hdp + bindex + 1, -+ sizeof(*hdp) * (bend - bindex)); -+ hdp[0 + bend].hd_dentry = NULL; -+ dinfo->di_bend--; -+ -+ p = krealloc(hdp, sizeof(*p) * bend, GFP_NOFS); -+ if (p) -+ dinfo->di_hdentry = p; -+ /* harmless error */ -+} -+ -+static void au_br_do_del_hip(struct au_iinfo *iinfo, const aufs_bindex_t bindex, -+ const aufs_bindex_t bend) -+{ -+ struct au_hinode *hip, *p; -+ -+ AuRwMustWriteLock(&iinfo->ii_rwsem); -+ -+ hip = iinfo->ii_hinode + bindex; -+ if (bindex < bend) -+ memmove(hip, hip + 1, sizeof(*hip) * (bend - bindex)); -+ iinfo->ii_hinode[0 + bend].hi_inode = NULL; -+ au_hn_init(iinfo->ii_hinode + bend); -+ iinfo->ii_bend--; -+ -+ p = krealloc(iinfo->ii_hinode, sizeof(*p) * bend, GFP_NOFS); -+ if (p) -+ iinfo->ii_hinode = p; -+ /* harmless error */ -+} -+ -+static void au_br_do_del(struct super_block *sb, aufs_bindex_t bindex, -+ struct au_branch *br) -+{ -+ aufs_bindex_t bend; -+ struct au_sbinfo *sbinfo; -+ struct dentry *root; -+ struct inode *inode; -+ -+ SiMustWriteLock(sb); -+ -+ root = sb->s_root; -+ inode = root->d_inode; -+ sbinfo = au_sbi(sb); -+ bend = sbinfo->si_bend; -+ -+ dput(au_h_dptr(root, bindex)); -+ au_hiput(au_hi(inode, bindex)); -+ au_br_do_free(br); -+ -+ au_br_do_del_brp(sbinfo, bindex, bend); -+ au_br_do_del_hdp(au_di(root), bindex, bend); -+ au_br_do_del_hip(au_ii(inode), bindex, bend); -+} -+ -+int au_br_del(struct super_block *sb, struct au_opt_del *del, int remount) -+{ -+ int err, rerr, i; -+ unsigned int mnt_flags; -+ aufs_bindex_t bindex, bend, br_id; -+ unsigned char do_wh, verbose; -+ struct au_branch *br; -+ struct au_wbr *wbr; -+ -+ err = 0; -+ bindex = au_find_dbindex(sb->s_root, del->h_path.dentry); -+ if (bindex < 0) { -+ if (remount) -+ goto out; /* success */ -+ err = -ENOENT; -+ pr_err("%s no such branch\n", del->pathname); -+ goto out; -+ } -+ AuDbg("bindex b%d\n", bindex); -+ -+ err = -EBUSY; -+ mnt_flags = au_mntflags(sb); -+ verbose = !!au_opt_test(mnt_flags, VERBOSE); -+ bend = au_sbend(sb); -+ if (unlikely(!bend)) { -+ AuVerbose(verbose, "no more branches left\n"); -+ goto out; -+ } -+ br = au_sbr(sb, bindex); -+ i = atomic_read(&br->br_count); -+ if (unlikely(i)) { -+ AuVerbose(verbose, "%d file(s) opened\n", i); -+ goto out; -+ } -+ -+ wbr = br->br_wbr; -+ do_wh = wbr && (wbr->wbr_whbase || wbr->wbr_plink || wbr->wbr_orph); -+ if (do_wh) { -+ /* instead of WbrWhMustWriteLock(wbr) */ -+ SiMustWriteLock(sb); -+ for (i = 0; i < AuBrWh_Last; i++) { -+ dput(wbr->wbr_wh[i]); -+ wbr->wbr_wh[i] = NULL; -+ } -+ } -+ -+ err = test_children_busy(sb->s_root, bindex, verbose); -+ if (unlikely(err)) { -+ if (do_wh) -+ goto out_wh; -+ goto out; -+ } -+ -+ err = 0; -+ br_id = br->br_id; -+ if (!remount) -+ au_br_do_del(sb, bindex, br); -+ else { -+ sysaufs_brs_del(sb, bindex); -+ au_br_do_del(sb, bindex, br); -+ sysaufs_brs_add(sb, bindex); -+ } -+ -+ if (!bindex) { -+ au_cpup_attr_all(sb->s_root->d_inode, /*force*/1); -+ sb->s_maxbytes = au_sbr_sb(sb, 0)->s_maxbytes; -+ } else -+ au_sub_nlink(sb->s_root->d_inode, del->h_path.dentry->d_inode); -+ if (au_opt_test(mnt_flags, PLINK)) -+ au_plink_half_refresh(sb, br_id); -+ -+ if (au_xino_brid(sb) == br_id) -+ au_xino_brid_set(sb, -1); -+ goto out; /* success */ -+ -+out_wh: -+ /* revert */ -+ rerr = au_br_init_wh(sb, br, br->br_perm, del->h_path.dentry); -+ if (rerr) -+ pr_warning("failed re-creating base whiteout, %s. (%d)\n", -+ del->pathname, rerr); -+out: -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * change a branch permission -+ */ -+ -+static void au_warn_ima(void) -+{ -+#ifdef CONFIG_IMA -+ /* since it doesn't support mark_files_ro() */ -+ AuWarn1("RW -> RO makes IMA to produce wrong message\n"); -+#endif -+} -+ -+static int do_need_sigen_inc(int a, int b) -+{ -+ return au_br_whable(a) && !au_br_whable(b); -+} -+ -+static int need_sigen_inc(int old, int new) -+{ -+ return do_need_sigen_inc(old, new) -+ || do_need_sigen_inc(new, old); -+} -+ -+static unsigned long long au_farray_cb(void *a, -+ unsigned long long max __maybe_unused, -+ void *arg) -+{ -+ unsigned long long n; -+ struct file **p, *f; -+ struct super_block *sb = arg; -+ -+ n = 0; -+ p = a; -+ lg_global_lock(files_lglock); -+ do_file_list_for_each_entry(sb, f) { -+ if (au_fi(f) -+ && !special_file(f->f_dentry->d_inode->i_mode)) { -+ get_file(f); -+ *p++ = f; -+ n++; -+ AuDebugOn(n > max); -+ } -+ } while_file_list_for_each_entry; -+ lg_global_unlock(files_lglock); -+ -+ return n; -+} -+ -+static struct file **au_farray_alloc(struct super_block *sb, -+ unsigned long long *max) -+{ -+ *max = atomic_long_read(&au_sbi(sb)->si_nfiles); -+ return au_array_alloc(max, au_farray_cb, sb); -+} -+ -+static void au_farray_free(struct file **a, unsigned long long max) -+{ -+ unsigned long long ull; -+ -+ for (ull = 0; ull < max; ull++) -+ if (a[ull]) -+ fput(a[ull]); -+ au_array_free(a); -+} -+ -+static int au_br_mod_files_ro(struct super_block *sb, aufs_bindex_t bindex) -+{ -+ int err, do_warn; -+ unsigned long long ull, max; -+ aufs_bindex_t br_id; -+ struct file *file, *hf, **array; -+ struct inode *inode; -+ struct au_hfile *hfile; -+ -+ array = au_farray_alloc(sb, &max); -+ err = PTR_ERR(array); -+ if (IS_ERR(array)) -+ goto out; -+ -+ do_warn = 0; -+ br_id = au_sbr_id(sb, bindex); -+ for (ull = 0; ull < max; ull++) { -+ file = array[ull]; -+ -+ /* AuDbg("%.*s\n", AuDLNPair(file->f_dentry)); */ -+ fi_read_lock(file); -+ if (unlikely(au_test_mmapped(file))) { -+ err = -EBUSY; -+ AuDbgFile(file); -+ FiMustNoWaiters(file); -+ fi_read_unlock(file); -+ goto out_array; -+ } -+ -+ inode = file->f_dentry->d_inode; -+ hfile = &au_fi(file)->fi_htop; -+ hf = hfile->hf_file; -+ if (!S_ISREG(inode->i_mode) -+ || !(file->f_mode & FMODE_WRITE) -+ || hfile->hf_br->br_id != br_id -+ || !(hf->f_mode & FMODE_WRITE)) -+ array[ull] = NULL; -+ else { -+ do_warn = 1; -+ get_file(file); -+ } -+ -+ FiMustNoWaiters(file); -+ fi_read_unlock(file); -+ fput(file); -+ } -+ -+ err = 0; -+ if (do_warn) -+ au_warn_ima(); -+ -+ for (ull = 0; ull < max; ull++) { -+ file = array[ull]; -+ if (!file) -+ continue; -+ -+ /* todo: already flushed? */ -+ /* cf. fs/super.c:mark_files_ro() */ -+ /* fi_read_lock(file); */ -+ hfile = &au_fi(file)->fi_htop; -+ hf = hfile->hf_file; -+ /* fi_read_unlock(file); */ -+ spin_lock(&hf->f_lock); -+ hf->f_mode &= ~FMODE_WRITE; -+ spin_unlock(&hf->f_lock); -+ if (!file_check_writeable(hf)) { -+ file_release_write(hf); -+ mnt_drop_write(hf->f_vfsmnt); -+ } -+ } -+ -+out_array: -+ au_farray_free(array, max); -+out: -+ AuTraceErr(err); -+ return err; -+} -+ -+int au_br_mod(struct super_block *sb, struct au_opt_mod *mod, int remount, -+ int *do_refresh) -+{ -+ int err, rerr; -+ aufs_bindex_t bindex; -+ struct path path; -+ struct dentry *root; -+ struct au_branch *br; -+ -+ root = sb->s_root; -+ bindex = au_find_dbindex(root, mod->h_root); -+ if (bindex < 0) { -+ if (remount) -+ return 0; /* success */ -+ err = -ENOENT; -+ pr_err("%s no such branch\n", mod->path); -+ goto out; -+ } -+ AuDbg("bindex b%d\n", bindex); -+ -+ err = test_br(mod->h_root->d_inode, mod->perm, mod->path); -+ if (unlikely(err)) -+ goto out; -+ -+ br = au_sbr(sb, bindex); -+ if (br->br_perm == mod->perm) -+ return 0; /* success */ -+ -+ if (au_br_writable(br->br_perm)) { -+ /* remove whiteout base */ -+ err = au_br_init_wh(sb, br, mod->perm, mod->h_root); -+ if (unlikely(err)) -+ goto out; -+ -+ if (!au_br_writable(mod->perm)) { -+ /* rw --> ro, file might be mmapped */ -+ DiMustNoWaiters(root); -+ IiMustNoWaiters(root->d_inode); -+ di_write_unlock(root); -+ err = au_br_mod_files_ro(sb, bindex); -+ /* aufs_write_lock() calls ..._child() */ -+ di_write_lock_child(root); -+ -+ if (unlikely(err)) { -+ rerr = -ENOMEM; -+ br->br_wbr = kmalloc(sizeof(*br->br_wbr), -+ GFP_NOFS); -+ if (br->br_wbr) { -+ path.mnt = br->br_mnt; -+ path.dentry = mod->h_root; -+ rerr = au_wbr_init(br, sb, br->br_perm, -+ &path); -+ } -+ if (unlikely(rerr)) { -+ AuIOErr("nested error %d (%d)\n", -+ rerr, err); -+ br->br_perm = mod->perm; -+ } -+ } -+ } -+ } else if (au_br_writable(mod->perm)) { -+ /* ro --> rw */ -+ err = -ENOMEM; -+ br->br_wbr = kmalloc(sizeof(*br->br_wbr), GFP_NOFS); -+ if (br->br_wbr) { -+ path.mnt = br->br_mnt; -+ path.dentry = mod->h_root; -+ err = au_wbr_init(br, sb, mod->perm, &path); -+ if (unlikely(err)) { -+ kfree(br->br_wbr); -+ br->br_wbr = NULL; -+ } -+ } -+ } -+ -+ if (!err) { -+ *do_refresh |= need_sigen_inc(br->br_perm, mod->perm); -+ br->br_perm = mod->perm; -+ } -+ -+out: -+ AuTraceErr(err); -+ return err; -+} -diff -Nur linux-2.6.37.orig/fs/aufs/branch.h linux-2.6.37/fs/aufs/branch.h ---- linux-2.6.37.orig/fs/aufs/branch.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/branch.h 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,229 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * branch filesystems and xino for them -+ */ -+ -+#ifndef __AUFS_BRANCH_H__ -+#define __AUFS_BRANCH_H__ -+ -+#ifdef __KERNEL__ -+ -+#include -+#include -+#include -+#include "dynop.h" -+#include "rwsem.h" -+#include "super.h" -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* a xino file */ -+struct au_xino_file { -+ struct file *xi_file; -+ struct mutex xi_nondir_mtx; -+ -+ /* todo: make xino files an array to support huge inode number */ -+ -+#ifdef CONFIG_DEBUG_FS -+ struct dentry *xi_dbgaufs; -+#endif -+}; -+ -+/* members for writable branch only */ -+enum {AuBrWh_BASE, AuBrWh_PLINK, AuBrWh_ORPH, AuBrWh_Last}; -+struct au_wbr { -+ struct au_rwsem wbr_wh_rwsem; -+ struct dentry *wbr_wh[AuBrWh_Last]; -+ atomic_t wbr_wh_running; -+#define wbr_whbase wbr_wh[AuBrWh_BASE] /* whiteout base */ -+#define wbr_plink wbr_wh[AuBrWh_PLINK] /* pseudo-link dir */ -+#define wbr_orph wbr_wh[AuBrWh_ORPH] /* dir for orphans */ -+ -+ /* mfs mode */ -+ unsigned long long wbr_bytes; -+}; -+ -+/* ext2 has 3 types of operations at least, ext3 has 4 */ -+#define AuBrDynOp (AuDyLast * 4) -+ -+/* protected by superblock rwsem */ -+struct au_branch { -+ struct au_xino_file br_xino; -+ -+ aufs_bindex_t br_id; -+ -+ int br_perm; -+ struct vfsmount *br_mnt; -+ spinlock_t br_dykey_lock; -+ struct au_dykey *br_dykey[AuBrDynOp]; -+ atomic_t br_count; -+ -+ struct au_wbr *br_wbr; -+ -+ /* xino truncation */ -+ blkcnt_t br_xino_upper; /* watermark in blocks */ -+ atomic_t br_xino_running; -+ -+#ifdef CONFIG_AUFS_HFSNOTIFY -+ struct fsnotify_group *br_hfsn_group; -+ struct fsnotify_ops br_hfsn_ops; -+#endif -+ -+#ifdef CONFIG_SYSFS -+ /* an entry under sysfs per mount-point */ -+ char br_name[8]; -+ struct attribute br_attr; -+#endif -+}; -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* branch permission and attribute */ -+enum { -+ AuBrPerm_RW, /* writable, linkable wh */ -+ AuBrPerm_RO, /* readonly, no wh */ -+ AuBrPerm_RR, /* natively readonly, no wh */ -+ -+ AuBrPerm_RWNoLinkWH, /* un-linkable whiteouts */ -+ -+ AuBrPerm_ROWH, /* whiteout-able */ -+ AuBrPerm_RRWH, /* whiteout-able */ -+ -+ AuBrPerm_Last -+}; -+ -+static inline int au_br_writable(int brperm) -+{ -+ return brperm == AuBrPerm_RW || brperm == AuBrPerm_RWNoLinkWH; -+} -+ -+static inline int au_br_whable(int brperm) -+{ -+ return brperm == AuBrPerm_RW -+ || brperm == AuBrPerm_ROWH -+ || brperm == AuBrPerm_RRWH; -+} -+ -+static inline int au_br_rdonly(struct au_branch *br) -+{ -+ return ((br->br_mnt->mnt_sb->s_flags & MS_RDONLY) -+ || !au_br_writable(br->br_perm)) -+ ? -EROFS : 0; -+} -+ -+static inline int au_br_hnotifyable(int brperm __maybe_unused) -+{ -+#ifdef CONFIG_AUFS_HNOTIFY -+ return brperm != AuBrPerm_RR && brperm != AuBrPerm_RRWH; -+#else -+ return 0; -+#endif -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* branch.c */ -+struct au_sbinfo; -+void au_br_free(struct au_sbinfo *sinfo); -+int au_br_index(struct super_block *sb, aufs_bindex_t br_id); -+struct au_opt_add; -+int au_br_add(struct super_block *sb, struct au_opt_add *add, int remount); -+struct au_opt_del; -+int au_br_del(struct super_block *sb, struct au_opt_del *del, int remount); -+struct au_opt_mod; -+int au_br_mod(struct super_block *sb, struct au_opt_mod *mod, int remount, -+ int *do_refresh); -+ -+/* xino.c */ -+static const loff_t au_loff_max = LLONG_MAX; -+ -+int au_xib_trunc(struct super_block *sb); -+ssize_t xino_fread(au_readf_t func, struct file *file, void *buf, size_t size, -+ loff_t *pos); -+ssize_t xino_fwrite(au_writef_t func, struct file *file, void *buf, size_t size, -+ loff_t *pos); -+struct file *au_xino_create2(struct file *base_file, struct file *copy_src); -+struct file *au_xino_create(struct super_block *sb, char *fname, int silent); -+ino_t au_xino_new_ino(struct super_block *sb); -+void au_xino_delete_inode(struct inode *inode, const int unlinked); -+int au_xino_write(struct super_block *sb, aufs_bindex_t bindex, ino_t h_ino, -+ ino_t ino); -+int au_xino_read(struct super_block *sb, aufs_bindex_t bindex, ino_t h_ino, -+ ino_t *ino); -+int au_xino_br(struct super_block *sb, struct au_branch *br, ino_t hino, -+ struct file *base_file, int do_test); -+int au_xino_trunc(struct super_block *sb, aufs_bindex_t bindex); -+ -+struct au_opt_xino; -+int au_xino_set(struct super_block *sb, struct au_opt_xino *xino, int remount); -+void au_xino_clr(struct super_block *sb); -+struct file *au_xino_def(struct super_block *sb); -+int au_xino_path(struct seq_file *seq, struct file *file); -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* Superblock to branch */ -+static inline -+aufs_bindex_t au_sbr_id(struct super_block *sb, aufs_bindex_t bindex) -+{ -+ return au_sbr(sb, bindex)->br_id; -+} -+ -+static inline -+struct vfsmount *au_sbr_mnt(struct super_block *sb, aufs_bindex_t bindex) -+{ -+ return au_sbr(sb, bindex)->br_mnt; -+} -+ -+static inline -+struct super_block *au_sbr_sb(struct super_block *sb, aufs_bindex_t bindex) -+{ -+ return au_sbr_mnt(sb, bindex)->mnt_sb; -+} -+ -+static inline void au_sbr_put(struct super_block *sb, aufs_bindex_t bindex) -+{ -+ atomic_dec(&au_sbr(sb, bindex)->br_count); -+} -+ -+static inline int au_sbr_perm(struct super_block *sb, aufs_bindex_t bindex) -+{ -+ return au_sbr(sb, bindex)->br_perm; -+} -+ -+static inline int au_sbr_whable(struct super_block *sb, aufs_bindex_t bindex) -+{ -+ return au_br_whable(au_sbr_perm(sb, bindex)); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * wbr_wh_read_lock, wbr_wh_write_lock -+ * wbr_wh_read_unlock, wbr_wh_write_unlock, wbr_wh_downgrade_lock -+ */ -+AuSimpleRwsemFuncs(wbr_wh, struct au_wbr *wbr, &wbr->wbr_wh_rwsem); -+ -+#define WbrWhMustNoWaiters(wbr) AuRwMustNoWaiters(&wbr->wbr_wh_rwsem) -+#define WbrWhMustAnyLock(wbr) AuRwMustAnyLock(&wbr->wbr_wh_rwsem) -+#define WbrWhMustWriteLock(wbr) AuRwMustWriteLock(&wbr->wbr_wh_rwsem) -+ -+#endif /* __KERNEL__ */ -+#endif /* __AUFS_BRANCH_H__ */ -diff -Nur linux-2.6.37.orig/fs/aufs/conf.mk linux-2.6.37/fs/aufs/conf.mk ---- linux-2.6.37.orig/fs/aufs/conf.mk 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/conf.mk 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,37 @@ -+ -+AuConfStr = CONFIG_AUFS_FS=${CONFIG_AUFS_FS} -+ -+define AuConf -+ifdef ${1} -+AuConfStr += ${1}=${${1}} -+endif -+endef -+ -+AuConfAll = BRANCH_MAX_127 BRANCH_MAX_511 BRANCH_MAX_1023 BRANCH_MAX_32767 \ -+ SBILIST \ -+ HNOTIFY HFSNOTIFY \ -+ EXPORT INO_T_64 \ -+ RDU \ -+ SP_IATTR \ -+ SHWH \ -+ BR_RAMFS \ -+ BR_FUSE POLL \ -+ BR_HFSPLUS \ -+ BDEV_LOOP \ -+ DEBUG MAGIC_SYSRQ -+$(foreach i, ${AuConfAll}, \ -+ $(eval $(call AuConf,CONFIG_AUFS_${i}))) -+ -+AuConfName = ${obj}/conf.str -+${AuConfName}.tmp: FORCE -+ @echo ${AuConfStr} | tr ' ' '\n' | sed -e 's/^/"/' -e 's/$$/\\n"/' > $@ -+${AuConfName}: ${AuConfName}.tmp -+ @diff -q $< $@ > /dev/null 2>&1 || { \ -+ echo ' GEN ' $@; \ -+ cp -p $< $@; \ -+ } -+FORCE: -+clean-files += ${AuConfName} ${AuConfName}.tmp -+${obj}/sysfs.o: ${AuConfName} -+ -+-include ${srctree}/${src}/conf_priv.mk -diff -Nur linux-2.6.37.orig/fs/aufs/cpup.c linux-2.6.37/fs/aufs/cpup.c ---- linux-2.6.37.orig/fs/aufs/cpup.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/cpup.c 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,1063 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * copy-up functions, see wbr_policy.c for copy-down -+ */ -+ -+#include -+#include -+#include -+#include -+#include "aufs.h" -+ -+void au_cpup_attr_flags(struct inode *dst, struct inode *src) -+{ -+ const unsigned int mask = S_DEAD | S_SWAPFILE | S_PRIVATE -+ | S_NOATIME | S_NOCMTIME; -+ -+ dst->i_flags |= src->i_flags & ~mask; -+ if (au_test_fs_notime(dst->i_sb)) -+ dst->i_flags |= S_NOATIME | S_NOCMTIME; -+} -+ -+void au_cpup_attr_timesizes(struct inode *inode) -+{ -+ struct inode *h_inode; -+ -+ h_inode = au_h_iptr(inode, au_ibstart(inode)); -+ fsstack_copy_attr_times(inode, h_inode); -+ fsstack_copy_inode_size(inode, h_inode); -+} -+ -+void au_cpup_attr_nlink(struct inode *inode, int force) -+{ -+ struct inode *h_inode; -+ struct super_block *sb; -+ aufs_bindex_t bindex, bend; -+ -+ sb = inode->i_sb; -+ bindex = au_ibstart(inode); -+ h_inode = au_h_iptr(inode, bindex); -+ if (!force -+ && !S_ISDIR(h_inode->i_mode) -+ && au_opt_test(au_mntflags(sb), PLINK) -+ && au_plink_test(inode)) -+ return; -+ -+ inode->i_nlink = h_inode->i_nlink; -+ -+ /* -+ * fewer nlink makes find(1) noisy, but larger nlink doesn't. -+ * it may includes whplink directory. -+ */ -+ if (S_ISDIR(h_inode->i_mode)) { -+ bend = au_ibend(inode); -+ for (bindex++; bindex <= bend; bindex++) { -+ h_inode = au_h_iptr(inode, bindex); -+ if (h_inode) -+ au_add_nlink(inode, h_inode); -+ } -+ } -+} -+ -+void au_cpup_attr_changeable(struct inode *inode) -+{ -+ struct inode *h_inode; -+ -+ h_inode = au_h_iptr(inode, au_ibstart(inode)); -+ inode->i_mode = h_inode->i_mode; -+ inode->i_uid = h_inode->i_uid; -+ inode->i_gid = h_inode->i_gid; -+ au_cpup_attr_timesizes(inode); -+ au_cpup_attr_flags(inode, h_inode); -+} -+ -+void au_cpup_igen(struct inode *inode, struct inode *h_inode) -+{ -+ struct au_iinfo *iinfo = au_ii(inode); -+ -+ IiMustWriteLock(inode); -+ -+ iinfo->ii_higen = h_inode->i_generation; -+ iinfo->ii_hsb1 = h_inode->i_sb; -+} -+ -+void au_cpup_attr_all(struct inode *inode, int force) -+{ -+ struct inode *h_inode; -+ -+ h_inode = au_h_iptr(inode, au_ibstart(inode)); -+ au_cpup_attr_changeable(inode); -+ if (inode->i_nlink > 0) -+ au_cpup_attr_nlink(inode, force); -+ inode->i_rdev = h_inode->i_rdev; -+ inode->i_blkbits = h_inode->i_blkbits; -+ au_cpup_igen(inode, h_inode); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* Note: dt_dentry and dt_h_dentry are not dget/dput-ed */ -+ -+/* keep the timestamps of the parent dir when cpup */ -+void au_dtime_store(struct au_dtime *dt, struct dentry *dentry, -+ struct path *h_path) -+{ -+ struct inode *h_inode; -+ -+ dt->dt_dentry = dentry; -+ dt->dt_h_path = *h_path; -+ h_inode = h_path->dentry->d_inode; -+ dt->dt_atime = h_inode->i_atime; -+ dt->dt_mtime = h_inode->i_mtime; -+ /* smp_mb(); */ -+} -+ -+void au_dtime_revert(struct au_dtime *dt) -+{ -+ struct iattr attr; -+ int err; -+ -+ attr.ia_atime = dt->dt_atime; -+ attr.ia_mtime = dt->dt_mtime; -+ attr.ia_valid = ATTR_FORCE | ATTR_MTIME | ATTR_MTIME_SET -+ | ATTR_ATIME | ATTR_ATIME_SET; -+ -+ err = vfsub_notify_change(&dt->dt_h_path, &attr); -+ if (unlikely(err)) -+ pr_warning("restoring timestamps failed(%d). ignored\n", err); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static noinline_for_stack -+int cpup_iattr(struct dentry *dst, aufs_bindex_t bindex, struct dentry *h_src) -+{ -+ int err, sbits; -+ struct iattr ia; -+ struct path h_path; -+ struct inode *h_isrc, *h_idst; -+ -+ h_path.dentry = au_h_dptr(dst, bindex); -+ h_idst = h_path.dentry->d_inode; -+ h_path.mnt = au_sbr_mnt(dst->d_sb, bindex); -+ h_isrc = h_src->d_inode; -+ ia.ia_valid = ATTR_FORCE | ATTR_UID | ATTR_GID -+ | ATTR_ATIME | ATTR_MTIME -+ | ATTR_ATIME_SET | ATTR_MTIME_SET; -+ ia.ia_uid = h_isrc->i_uid; -+ ia.ia_gid = h_isrc->i_gid; -+ ia.ia_atime = h_isrc->i_atime; -+ ia.ia_mtime = h_isrc->i_mtime; -+ if (h_idst->i_mode != h_isrc->i_mode -+ && !S_ISLNK(h_idst->i_mode)) { -+ ia.ia_valid |= ATTR_MODE; -+ ia.ia_mode = h_isrc->i_mode; -+ } -+ sbits = !!(h_isrc->i_mode & (S_ISUID | S_ISGID)); -+ au_cpup_attr_flags(h_idst, h_isrc); -+ err = vfsub_notify_change(&h_path, &ia); -+ -+ /* is this nfs only? */ -+ if (!err && sbits && au_test_nfs(h_path.dentry->d_sb)) { -+ ia.ia_valid = ATTR_FORCE | ATTR_MODE; -+ ia.ia_mode = h_isrc->i_mode; -+ err = vfsub_notify_change(&h_path, &ia); -+ } -+ -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int au_do_copy_file(struct file *dst, struct file *src, loff_t len, -+ char *buf, unsigned long blksize) -+{ -+ int err; -+ size_t sz, rbytes, wbytes; -+ unsigned char all_zero; -+ char *p, *zp; -+ struct mutex *h_mtx; -+ /* reduce stack usage */ -+ struct iattr *ia; -+ -+ zp = page_address(ZERO_PAGE(0)); -+ if (unlikely(!zp)) -+ return -ENOMEM; /* possible? */ -+ -+ err = 0; -+ all_zero = 0; -+ while (len) { -+ AuDbg("len %lld\n", len); -+ sz = blksize; -+ if (len < blksize) -+ sz = len; -+ -+ rbytes = 0; -+ /* todo: signal_pending? */ -+ while (!rbytes || err == -EAGAIN || err == -EINTR) { -+ rbytes = vfsub_read_k(src, buf, sz, &src->f_pos); -+ err = rbytes; -+ } -+ if (unlikely(err < 0)) -+ break; -+ -+ all_zero = 0; -+ if (len >= rbytes && rbytes == blksize) -+ all_zero = !memcmp(buf, zp, rbytes); -+ if (!all_zero) { -+ wbytes = rbytes; -+ p = buf; -+ while (wbytes) { -+ size_t b; -+ -+ b = vfsub_write_k(dst, p, wbytes, &dst->f_pos); -+ err = b; -+ /* todo: signal_pending? */ -+ if (unlikely(err == -EAGAIN || err == -EINTR)) -+ continue; -+ if (unlikely(err < 0)) -+ break; -+ wbytes -= b; -+ p += b; -+ } -+ } else { -+ loff_t res; -+ -+ AuLabel(hole); -+ res = vfsub_llseek(dst, rbytes, SEEK_CUR); -+ err = res; -+ if (unlikely(res < 0)) -+ break; -+ } -+ len -= rbytes; -+ err = 0; -+ } -+ -+ /* the last block may be a hole */ -+ if (!err && all_zero) { -+ AuLabel(last hole); -+ -+ err = 1; -+ if (au_test_nfs(dst->f_dentry->d_sb)) { -+ /* nfs requires this step to make last hole */ -+ /* is this only nfs? */ -+ do { -+ /* todo: signal_pending? */ -+ err = vfsub_write_k(dst, "\0", 1, &dst->f_pos); -+ } while (err == -EAGAIN || err == -EINTR); -+ if (err == 1) -+ dst->f_pos--; -+ } -+ -+ if (err == 1) { -+ ia = (void *)buf; -+ ia->ia_size = dst->f_pos; -+ ia->ia_valid = ATTR_SIZE | ATTR_FILE; -+ ia->ia_file = dst; -+ h_mtx = &dst->f_dentry->d_inode->i_mutex; -+ mutex_lock_nested(h_mtx, AuLsc_I_CHILD2); -+ err = vfsub_notify_change(&dst->f_path, ia); -+ mutex_unlock(h_mtx); -+ } -+ } -+ -+ return err; -+} -+ -+int au_copy_file(struct file *dst, struct file *src, loff_t len) -+{ -+ int err; -+ unsigned long blksize; -+ unsigned char do_kfree; -+ char *buf; -+ -+ err = -ENOMEM; -+ blksize = dst->f_dentry->d_sb->s_blocksize; -+ if (!blksize || PAGE_SIZE < blksize) -+ blksize = PAGE_SIZE; -+ AuDbg("blksize %lu\n", blksize); -+ do_kfree = (blksize != PAGE_SIZE && blksize >= sizeof(struct iattr *)); -+ if (do_kfree) -+ buf = kmalloc(blksize, GFP_NOFS); -+ else -+ buf = (void *)__get_free_page(GFP_NOFS); -+ if (unlikely(!buf)) -+ goto out; -+ -+ if (len > (1 << 22)) -+ AuDbg("copying a large file %lld\n", (long long)len); -+ -+ src->f_pos = 0; -+ dst->f_pos = 0; -+ err = au_do_copy_file(dst, src, len, buf, blksize); -+ if (do_kfree) -+ kfree(buf); -+ else -+ free_page((unsigned long)buf); -+ -+out: -+ return err; -+} -+ -+/* -+ * to support a sparse file which is opened with O_APPEND, -+ * we need to close the file. -+ */ -+static int au_cp_regular(struct dentry *dentry, aufs_bindex_t bdst, -+ aufs_bindex_t bsrc, loff_t len) -+{ -+ int err, i; -+ enum { SRC, DST }; -+ struct { -+ aufs_bindex_t bindex; -+ unsigned int flags; -+ struct dentry *dentry; -+ struct file *file; -+ void *label, *label_file; -+ } *f, file[] = { -+ { -+ .bindex = bsrc, -+ .flags = O_RDONLY | O_NOATIME | O_LARGEFILE, -+ .file = NULL, -+ .label = &&out, -+ .label_file = &&out_src -+ }, -+ { -+ .bindex = bdst, -+ .flags = O_WRONLY | O_NOATIME | O_LARGEFILE, -+ .file = NULL, -+ .label = &&out_src, -+ .label_file = &&out_dst -+ } -+ }; -+ struct super_block *sb; -+ -+ /* bsrc branch can be ro/rw. */ -+ sb = dentry->d_sb; -+ f = file; -+ for (i = 0; i < 2; i++, f++) { -+ f->dentry = au_h_dptr(dentry, f->bindex); -+ f->file = au_h_open(dentry, f->bindex, f->flags, /*file*/NULL); -+ err = PTR_ERR(f->file); -+ if (IS_ERR(f->file)) -+ goto *f->label; -+ err = -EINVAL; -+ if (unlikely(!f->file->f_op)) -+ goto *f->label_file; -+ } -+ -+ /* try stopping to update while we copyup */ -+ IMustLock(file[SRC].dentry->d_inode); -+ err = au_copy_file(file[DST].file, file[SRC].file, len); -+ -+out_dst: -+ fput(file[DST].file); -+ au_sbr_put(sb, file[DST].bindex); -+out_src: -+ fput(file[SRC].file); -+ au_sbr_put(sb, file[SRC].bindex); -+out: -+ return err; -+} -+ -+static int au_do_cpup_regular(struct dentry *dentry, aufs_bindex_t bdst, -+ aufs_bindex_t bsrc, loff_t len, -+ struct inode *h_dir, struct path *h_path) -+{ -+ int err, rerr; -+ loff_t l; -+ -+ err = 0; -+ l = i_size_read(au_h_iptr(dentry->d_inode, bsrc)); -+ if (len == -1 || l < len) -+ len = l; -+ if (len) -+ err = au_cp_regular(dentry, bdst, bsrc, len); -+ if (!err) -+ goto out; /* success */ -+ -+ rerr = vfsub_unlink(h_dir, h_path, /*force*/0); -+ if (rerr) { -+ AuIOErr("failed unlinking cpup-ed %.*s(%d, %d)\n", -+ AuDLNPair(h_path->dentry), err, rerr); -+ err = -EIO; -+ } -+ -+out: -+ return err; -+} -+ -+static int au_do_cpup_symlink(struct path *h_path, struct dentry *h_src, -+ struct inode *h_dir) -+{ -+ int err, symlen; -+ mm_segment_t old_fs; -+ union { -+ char *k; -+ char __user *u; -+ } sym; -+ -+ err = -ENOSYS; -+ if (unlikely(!h_src->d_inode->i_op->readlink)) -+ goto out; -+ -+ err = -ENOMEM; -+ sym.k = __getname_gfp(GFP_NOFS); -+ if (unlikely(!sym.k)) -+ goto out; -+ -+ old_fs = get_fs(); -+ set_fs(KERNEL_DS); -+ symlen = h_src->d_inode->i_op->readlink(h_src, sym.u, PATH_MAX); -+ err = symlen; -+ set_fs(old_fs); -+ -+ if (symlen > 0) { -+ sym.k[symlen] = 0; -+ err = vfsub_symlink(h_dir, h_path, sym.k); -+ } -+ __putname(sym.k); -+ -+out: -+ return err; -+} -+ -+/* return with the lower dst inode is locked */ -+static noinline_for_stack -+int cpup_entry(struct dentry *dentry, aufs_bindex_t bdst, -+ aufs_bindex_t bsrc, loff_t len, unsigned int flags, -+ struct dentry *dst_parent) -+{ -+ int err; -+ umode_t mode; -+ unsigned int mnt_flags; -+ unsigned char isdir; -+ const unsigned char do_dt = !!au_ftest_cpup(flags, DTIME); -+ struct au_dtime dt; -+ struct path h_path; -+ struct dentry *h_src, *h_dst, *h_parent; -+ struct inode *h_inode, *h_dir; -+ struct super_block *sb; -+ -+ /* bsrc branch can be ro/rw. */ -+ h_src = au_h_dptr(dentry, bsrc); -+ h_inode = h_src->d_inode; -+ AuDebugOn(h_inode != au_h_iptr(dentry->d_inode, bsrc)); -+ -+ /* try stopping to be referenced while we are creating */ -+ h_dst = au_h_dptr(dentry, bdst); -+ h_parent = h_dst->d_parent; /* dir inode is locked */ -+ h_dir = h_parent->d_inode; -+ IMustLock(h_dir); -+ AuDebugOn(h_parent != h_dst->d_parent); -+ -+ sb = dentry->d_sb; -+ h_path.mnt = au_sbr_mnt(sb, bdst); -+ if (do_dt) { -+ h_path.dentry = h_parent; -+ au_dtime_store(&dt, dst_parent, &h_path); -+ } -+ h_path.dentry = h_dst; -+ -+ isdir = 0; -+ mode = h_inode->i_mode; -+ switch (mode & S_IFMT) { -+ case S_IFREG: -+ /* try stopping to update while we are referencing */ -+ IMustLock(h_inode); -+ err = vfsub_create(h_dir, &h_path, mode | S_IWUSR); -+ if (!err) -+ err = au_do_cpup_regular -+ (dentry, bdst, bsrc, len, -+ au_h_iptr(dst_parent->d_inode, bdst), &h_path); -+ break; -+ case S_IFDIR: -+ isdir = 1; -+ err = vfsub_mkdir(h_dir, &h_path, mode); -+ if (!err) { -+ /* -+ * strange behaviour from the users view, -+ * particularry setattr case -+ */ -+ if (au_ibstart(dst_parent->d_inode) == bdst) -+ au_cpup_attr_nlink(dst_parent->d_inode, -+ /*force*/1); -+ au_cpup_attr_nlink(dentry->d_inode, /*force*/1); -+ } -+ break; -+ case S_IFLNK: -+ err = au_do_cpup_symlink(&h_path, h_src, h_dir); -+ break; -+ case S_IFCHR: -+ case S_IFBLK: -+ AuDebugOn(!capable(CAP_MKNOD)); -+ /*FALLTHROUGH*/ -+ case S_IFIFO: -+ case S_IFSOCK: -+ err = vfsub_mknod(h_dir, &h_path, mode, h_inode->i_rdev); -+ break; -+ default: -+ AuIOErr("Unknown inode type 0%o\n", mode); -+ err = -EIO; -+ } -+ -+ mnt_flags = au_mntflags(sb); -+ if (!au_opt_test(mnt_flags, UDBA_NONE) -+ && !isdir -+ && au_opt_test(mnt_flags, XINO) -+ && h_inode->i_nlink == 1 -+ /* todo: unnecessary? */ -+ /* && dentry->d_inode->i_nlink == 1 */ -+ && bdst < bsrc -+ && !au_ftest_cpup(flags, KEEPLINO)) -+ au_xino_write(sb, bsrc, h_inode->i_ino, /*ino*/0); -+ /* ignore this error */ -+ -+ if (do_dt) -+ au_dtime_revert(&dt); -+ return err; -+} -+ -+/* -+ * copyup the @dentry from @bsrc to @bdst. -+ * the caller must set the both of lower dentries. -+ * @len is for truncating when it is -1 copyup the entire file. -+ * in link/rename cases, @dst_parent may be different from the real one. -+ */ -+static int au_cpup_single(struct dentry *dentry, aufs_bindex_t bdst, -+ aufs_bindex_t bsrc, loff_t len, unsigned int flags, -+ struct dentry *dst_parent) -+{ -+ int err, rerr; -+ aufs_bindex_t old_ibstart; -+ unsigned char isdir, plink; -+ struct au_dtime dt; -+ struct path h_path; -+ struct dentry *h_src, *h_dst, *h_parent; -+ struct inode *dst_inode, *h_dir, *inode; -+ struct super_block *sb; -+ -+ AuDebugOn(bsrc <= bdst); -+ -+ sb = dentry->d_sb; -+ h_path.mnt = au_sbr_mnt(sb, bdst); -+ h_dst = au_h_dptr(dentry, bdst); -+ h_parent = h_dst->d_parent; /* dir inode is locked */ -+ h_dir = h_parent->d_inode; -+ IMustLock(h_dir); -+ -+ h_src = au_h_dptr(dentry, bsrc); -+ inode = dentry->d_inode; -+ -+ if (!dst_parent) -+ dst_parent = dget_parent(dentry); -+ else -+ dget(dst_parent); -+ -+ plink = !!au_opt_test(au_mntflags(sb), PLINK); -+ dst_inode = au_h_iptr(inode, bdst); -+ if (dst_inode) { -+ if (unlikely(!plink)) { -+ err = -EIO; -+ AuIOErr("hi%lu(i%lu) exists on b%d " -+ "but plink is disabled\n", -+ dst_inode->i_ino, inode->i_ino, bdst); -+ goto out; -+ } -+ -+ if (dst_inode->i_nlink) { -+ const int do_dt = au_ftest_cpup(flags, DTIME); -+ -+ h_src = au_plink_lkup(inode, bdst); -+ err = PTR_ERR(h_src); -+ if (IS_ERR(h_src)) -+ goto out; -+ if (unlikely(!h_src->d_inode)) { -+ err = -EIO; -+ AuIOErr("i%lu exists on a upper branch " -+ "but not pseudo-linked\n", -+ inode->i_ino); -+ dput(h_src); -+ goto out; -+ } -+ -+ if (do_dt) { -+ h_path.dentry = h_parent; -+ au_dtime_store(&dt, dst_parent, &h_path); -+ } -+ h_path.dentry = h_dst; -+ err = vfsub_link(h_src, h_dir, &h_path); -+ if (do_dt) -+ au_dtime_revert(&dt); -+ dput(h_src); -+ goto out; -+ } else -+ /* todo: cpup_wh_file? */ -+ /* udba work */ -+ au_update_ibrange(inode, /*do_put_zero*/1); -+ } -+ -+ old_ibstart = au_ibstart(inode); -+ err = cpup_entry(dentry, bdst, bsrc, len, flags, dst_parent); -+ if (unlikely(err)) -+ goto out; -+ dst_inode = h_dst->d_inode; -+ mutex_lock_nested(&dst_inode->i_mutex, AuLsc_I_CHILD2); -+ -+ err = cpup_iattr(dentry, bdst, h_src); -+ isdir = S_ISDIR(dst_inode->i_mode); -+ if (!err) { -+ if (bdst < old_ibstart) { -+ if (S_ISREG(inode->i_mode)) { -+ err = au_dy_iaop(inode, bdst, dst_inode); -+ if (unlikely(err)) -+ goto out_rev; -+ } -+ au_set_ibstart(inode, bdst); -+ } -+ au_set_h_iptr(inode, bdst, au_igrab(dst_inode), -+ au_hi_flags(inode, isdir)); -+ mutex_unlock(&dst_inode->i_mutex); -+ if (!isdir -+ && h_src->d_inode->i_nlink > 1 -+ && plink) -+ au_plink_append(inode, bdst, h_dst); -+ goto out; /* success */ -+ } -+ -+ /* revert */ -+out_rev: -+ h_path.dentry = h_parent; -+ mutex_unlock(&dst_inode->i_mutex); -+ au_dtime_store(&dt, dst_parent, &h_path); -+ h_path.dentry = h_dst; -+ if (!isdir) -+ rerr = vfsub_unlink(h_dir, &h_path, /*force*/0); -+ else -+ rerr = vfsub_rmdir(h_dir, &h_path); -+ au_dtime_revert(&dt); -+ if (rerr) { -+ AuIOErr("failed removing broken entry(%d, %d)\n", err, rerr); -+ err = -EIO; -+ } -+ -+out: -+ dput(dst_parent); -+ return err; -+} -+ -+struct au_cpup_single_args { -+ int *errp; -+ struct dentry *dentry; -+ aufs_bindex_t bdst, bsrc; -+ loff_t len; -+ unsigned int flags; -+ struct dentry *dst_parent; -+}; -+ -+static void au_call_cpup_single(void *args) -+{ -+ struct au_cpup_single_args *a = args; -+ *a->errp = au_cpup_single(a->dentry, a->bdst, a->bsrc, a->len, -+ a->flags, a->dst_parent); -+} -+ -+int au_sio_cpup_single(struct dentry *dentry, aufs_bindex_t bdst, -+ aufs_bindex_t bsrc, loff_t len, unsigned int flags, -+ struct dentry *dst_parent) -+{ -+ int err, wkq_err; -+ umode_t mode; -+ struct dentry *h_dentry; -+ -+ h_dentry = au_h_dptr(dentry, bsrc); -+ mode = h_dentry->d_inode->i_mode & S_IFMT; -+ if ((mode != S_IFCHR && mode != S_IFBLK) -+ || capable(CAP_MKNOD)) -+ err = au_cpup_single(dentry, bdst, bsrc, len, flags, -+ dst_parent); -+ else { -+ struct au_cpup_single_args args = { -+ .errp = &err, -+ .dentry = dentry, -+ .bdst = bdst, -+ .bsrc = bsrc, -+ .len = len, -+ .flags = flags, -+ .dst_parent = dst_parent -+ }; -+ wkq_err = au_wkq_wait(au_call_cpup_single, &args); -+ if (unlikely(wkq_err)) -+ err = wkq_err; -+ } -+ -+ return err; -+} -+ -+/* -+ * copyup the @dentry from the first active lower branch to @bdst, -+ * using au_cpup_single(). -+ */ -+static int au_cpup_simple(struct dentry *dentry, aufs_bindex_t bdst, loff_t len, -+ unsigned int flags) -+{ -+ int err; -+ aufs_bindex_t bsrc, bend; -+ -+ bend = au_dbend(dentry); -+ for (bsrc = bdst + 1; bsrc <= bend; bsrc++) -+ if (au_h_dptr(dentry, bsrc)) -+ break; -+ -+ err = au_lkup_neg(dentry, bdst); -+ if (!err) { -+ err = au_cpup_single(dentry, bdst, bsrc, len, flags, NULL); -+ if (!err) -+ return 0; /* success */ -+ -+ /* revert */ -+ au_set_h_dptr(dentry, bdst, NULL); -+ au_set_dbstart(dentry, bsrc); -+ } -+ -+ return err; -+} -+ -+struct au_cpup_simple_args { -+ int *errp; -+ struct dentry *dentry; -+ aufs_bindex_t bdst; -+ loff_t len; -+ unsigned int flags; -+}; -+ -+static void au_call_cpup_simple(void *args) -+{ -+ struct au_cpup_simple_args *a = args; -+ *a->errp = au_cpup_simple(a->dentry, a->bdst, a->len, a->flags); -+} -+ -+int au_sio_cpup_simple(struct dentry *dentry, aufs_bindex_t bdst, loff_t len, -+ unsigned int flags) -+{ -+ int err, wkq_err; -+ unsigned char do_sio; -+ struct dentry *parent; -+ struct inode *h_dir; -+ -+ parent = dget_parent(dentry); -+ h_dir = au_h_iptr(parent->d_inode, bdst); -+ do_sio = !!au_test_h_perm_sio(h_dir, MAY_EXEC | MAY_WRITE); -+ if (!do_sio) { -+ /* -+ * testing CAP_MKNOD is for generic fs, -+ * but CAP_FSETID is for xfs only, currently. -+ */ -+ umode_t mode = dentry->d_inode->i_mode; -+ do_sio = (((mode & (S_IFCHR | S_IFBLK)) -+ && !capable(CAP_MKNOD)) -+ || ((mode & (S_ISUID | S_ISGID)) -+ && !capable(CAP_FSETID))); -+ } -+ if (!do_sio) -+ err = au_cpup_simple(dentry, bdst, len, flags); -+ else { -+ struct au_cpup_simple_args args = { -+ .errp = &err, -+ .dentry = dentry, -+ .bdst = bdst, -+ .len = len, -+ .flags = flags -+ }; -+ wkq_err = au_wkq_wait(au_call_cpup_simple, &args); -+ if (unlikely(wkq_err)) -+ err = wkq_err; -+ } -+ -+ dput(parent); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * copyup the deleted file for writing. -+ */ -+static int au_do_cpup_wh(struct dentry *dentry, aufs_bindex_t bdst, -+ struct dentry *wh_dentry, struct file *file, -+ loff_t len) -+{ -+ int err; -+ aufs_bindex_t bstart; -+ struct au_dinfo *dinfo; -+ struct dentry *h_d_dst, *h_d_start; -+ struct au_hdentry *hdp; -+ -+ dinfo = au_di(dentry); -+ AuRwMustWriteLock(&dinfo->di_rwsem); -+ -+ bstart = dinfo->di_bstart; -+ hdp = dinfo->di_hdentry; -+ h_d_dst = hdp[0 + bdst].hd_dentry; -+ dinfo->di_bstart = bdst; -+ hdp[0 + bdst].hd_dentry = wh_dentry; -+ if (file) { -+ h_d_start = hdp[0 + bstart].hd_dentry; -+ hdp[0 + bstart].hd_dentry = au_hf_top(file)->f_dentry; -+ } -+ err = au_cpup_single(dentry, bdst, bstart, len, !AuCpup_DTIME, -+ /*h_parent*/NULL); -+ if (file) { -+ if (!err) -+ err = au_reopen_nondir(file); -+ hdp[0 + bstart].hd_dentry = h_d_start; -+ } -+ hdp[0 + bdst].hd_dentry = h_d_dst; -+ dinfo->di_bstart = bstart; -+ -+ return err; -+} -+ -+static int au_cpup_wh(struct dentry *dentry, aufs_bindex_t bdst, loff_t len, -+ struct file *file) -+{ -+ int err; -+ struct au_dtime dt; -+ struct dentry *parent, *h_parent, *wh_dentry; -+ struct au_branch *br; -+ struct path h_path; -+ -+ br = au_sbr(dentry->d_sb, bdst); -+ parent = dget_parent(dentry); -+ h_parent = au_h_dptr(parent, bdst); -+ wh_dentry = au_whtmp_lkup(h_parent, br, &dentry->d_name); -+ err = PTR_ERR(wh_dentry); -+ if (IS_ERR(wh_dentry)) -+ goto out; -+ -+ h_path.dentry = h_parent; -+ h_path.mnt = br->br_mnt; -+ au_dtime_store(&dt, parent, &h_path); -+ err = au_do_cpup_wh(dentry, bdst, wh_dentry, file, len); -+ if (unlikely(err)) -+ goto out_wh; -+ -+ dget(wh_dentry); -+ h_path.dentry = wh_dentry; -+ if (!S_ISDIR(wh_dentry->d_inode->i_mode)) -+ err = vfsub_unlink(h_parent->d_inode, &h_path, /*force*/0); -+ else -+ err = vfsub_rmdir(h_parent->d_inode, &h_path); -+ if (unlikely(err)) { -+ AuIOErr("failed remove copied-up tmp file %.*s(%d)\n", -+ AuDLNPair(wh_dentry), err); -+ err = -EIO; -+ } -+ au_dtime_revert(&dt); -+ au_set_hi_wh(dentry->d_inode, bdst, wh_dentry); -+ -+out_wh: -+ dput(wh_dentry); -+out: -+ dput(parent); -+ return err; -+} -+ -+struct au_cpup_wh_args { -+ int *errp; -+ struct dentry *dentry; -+ aufs_bindex_t bdst; -+ loff_t len; -+ struct file *file; -+}; -+ -+static void au_call_cpup_wh(void *args) -+{ -+ struct au_cpup_wh_args *a = args; -+ *a->errp = au_cpup_wh(a->dentry, a->bdst, a->len, a->file); -+} -+ -+int au_sio_cpup_wh(struct dentry *dentry, aufs_bindex_t bdst, loff_t len, -+ struct file *file) -+{ -+ int err, wkq_err; -+ struct dentry *parent, *h_orph, *h_parent, *h_dentry; -+ struct inode *dir, *h_dir, *h_tmpdir, *h_inode; -+ struct au_wbr *wbr; -+ -+ parent = dget_parent(dentry); -+ dir = parent->d_inode; -+ h_orph = NULL; -+ h_parent = NULL; -+ h_dir = au_igrab(au_h_iptr(dir, bdst)); -+ h_tmpdir = h_dir; -+ if (!h_dir->i_nlink) { -+ wbr = au_sbr(dentry->d_sb, bdst)->br_wbr; -+ h_orph = wbr->wbr_orph; -+ -+ h_parent = dget(au_h_dptr(parent, bdst)); -+ au_set_h_dptr(parent, bdst, dget(h_orph)); -+ h_tmpdir = h_orph->d_inode; -+ au_set_h_iptr(dir, bdst, au_igrab(h_tmpdir), /*flags*/0); -+ -+ /* this temporary unlock is safe */ -+ if (file) -+ h_dentry = au_hf_top(file)->f_dentry; -+ else -+ h_dentry = au_h_dptr(dentry, au_dbstart(dentry)); -+ h_inode = h_dentry->d_inode; -+ IMustLock(h_inode); -+ mutex_unlock(&h_inode->i_mutex); -+ mutex_lock_nested(&h_tmpdir->i_mutex, AuLsc_I_PARENT3); -+ mutex_lock_nested(&h_inode->i_mutex, AuLsc_I_CHILD); -+ /* todo: au_h_open_pre()? */ -+ } -+ -+ if (!au_test_h_perm_sio(h_tmpdir, MAY_EXEC | MAY_WRITE)) -+ err = au_cpup_wh(dentry, bdst, len, file); -+ else { -+ struct au_cpup_wh_args args = { -+ .errp = &err, -+ .dentry = dentry, -+ .bdst = bdst, -+ .len = len, -+ .file = file -+ }; -+ wkq_err = au_wkq_wait(au_call_cpup_wh, &args); -+ if (unlikely(wkq_err)) -+ err = wkq_err; -+ } -+ -+ if (h_orph) { -+ mutex_unlock(&h_tmpdir->i_mutex); -+ /* todo: au_h_open_post()? */ -+ au_set_h_iptr(dir, bdst, au_igrab(h_dir), /*flags*/0); -+ au_set_h_dptr(parent, bdst, h_parent); -+ } -+ iput(h_dir); -+ dput(parent); -+ -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * generic routine for both of copy-up and copy-down. -+ */ -+/* cf. revalidate function in file.c */ -+int au_cp_dirs(struct dentry *dentry, aufs_bindex_t bdst, -+ int (*cp)(struct dentry *dentry, aufs_bindex_t bdst, -+ struct dentry *h_parent, void *arg), -+ void *arg) -+{ -+ int err; -+ struct au_pin pin; -+ struct dentry *d, *parent, *h_parent, *real_parent; -+ -+ err = 0; -+ parent = dget_parent(dentry); -+ if (IS_ROOT(parent)) -+ goto out; -+ -+ au_pin_init(&pin, dentry, bdst, AuLsc_DI_PARENT2, AuLsc_I_PARENT2, -+ au_opt_udba(dentry->d_sb), AuPin_MNT_WRITE); -+ -+ /* do not use au_dpage */ -+ real_parent = parent; -+ while (1) { -+ dput(parent); -+ parent = dget_parent(dentry); -+ h_parent = au_h_dptr(parent, bdst); -+ if (h_parent) -+ goto out; /* success */ -+ -+ /* find top dir which is necessary to cpup */ -+ do { -+ d = parent; -+ dput(parent); -+ parent = dget_parent(d); -+ di_read_lock_parent3(parent, !AuLock_IR); -+ h_parent = au_h_dptr(parent, bdst); -+ di_read_unlock(parent, !AuLock_IR); -+ } while (!h_parent); -+ -+ if (d != real_parent) -+ di_write_lock_child3(d); -+ -+ /* somebody else might create while we were sleeping */ -+ if (!au_h_dptr(d, bdst) || !au_h_dptr(d, bdst)->d_inode) { -+ if (au_h_dptr(d, bdst)) -+ au_update_dbstart(d); -+ -+ au_pin_set_dentry(&pin, d); -+ err = au_do_pin(&pin); -+ if (!err) { -+ err = cp(d, bdst, h_parent, arg); -+ au_unpin(&pin); -+ } -+ } -+ -+ if (d != real_parent) -+ di_write_unlock(d); -+ if (unlikely(err)) -+ break; -+ } -+ -+out: -+ dput(parent); -+ return err; -+} -+ -+static int au_cpup_dir(struct dentry *dentry, aufs_bindex_t bdst, -+ struct dentry *h_parent __maybe_unused , -+ void *arg __maybe_unused) -+{ -+ return au_sio_cpup_simple(dentry, bdst, -1, AuCpup_DTIME); -+} -+ -+int au_cpup_dirs(struct dentry *dentry, aufs_bindex_t bdst) -+{ -+ return au_cp_dirs(dentry, bdst, au_cpup_dir, NULL); -+} -+ -+int au_test_and_cpup_dirs(struct dentry *dentry, aufs_bindex_t bdst) -+{ -+ int err; -+ struct dentry *parent; -+ struct inode *dir; -+ -+ parent = dget_parent(dentry); -+ dir = parent->d_inode; -+ err = 0; -+ if (au_h_iptr(dir, bdst)) -+ goto out; -+ -+ di_read_unlock(parent, AuLock_IR); -+ di_write_lock_parent(parent); -+ /* someone else might change our inode while we were sleeping */ -+ if (!au_h_iptr(dir, bdst)) -+ err = au_cpup_dirs(dentry, bdst); -+ di_downgrade_lock(parent, AuLock_IR); -+ -+out: -+ dput(parent); -+ return err; -+} -diff -Nur linux-2.6.37.orig/fs/aufs/cpup.h linux-2.6.37/fs/aufs/cpup.h ---- linux-2.6.37.orig/fs/aufs/cpup.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/cpup.h 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,83 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * copy-up/down functions -+ */ -+ -+#ifndef __AUFS_CPUP_H__ -+#define __AUFS_CPUP_H__ -+ -+#ifdef __KERNEL__ -+ -+#include -+#include -+#include -+ -+struct inode; -+struct file; -+ -+void au_cpup_attr_flags(struct inode *dst, struct inode *src); -+void au_cpup_attr_timesizes(struct inode *inode); -+void au_cpup_attr_nlink(struct inode *inode, int force); -+void au_cpup_attr_changeable(struct inode *inode); -+void au_cpup_igen(struct inode *inode, struct inode *h_inode); -+void au_cpup_attr_all(struct inode *inode, int force); -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* cpup flags */ -+#define AuCpup_DTIME 1 /* do dtime_store/revert */ -+#define AuCpup_KEEPLINO (1 << 1) /* do not clear the lower xino, -+ for link(2) */ -+#define au_ftest_cpup(flags, name) ((flags) & AuCpup_##name) -+#define au_fset_cpup(flags, name) \ -+ do { (flags) |= AuCpup_##name; } while (0) -+#define au_fclr_cpup(flags, name) \ -+ do { (flags) &= ~AuCpup_##name; } while (0) -+ -+int au_copy_file(struct file *dst, struct file *src, loff_t len); -+int au_sio_cpup_single(struct dentry *dentry, aufs_bindex_t bdst, -+ aufs_bindex_t bsrc, loff_t len, unsigned int flags, -+ struct dentry *dst_parent); -+int au_sio_cpup_simple(struct dentry *dentry, aufs_bindex_t bdst, loff_t len, -+ unsigned int flags); -+int au_sio_cpup_wh(struct dentry *dentry, aufs_bindex_t bdst, loff_t len, -+ struct file *file); -+ -+int au_cp_dirs(struct dentry *dentry, aufs_bindex_t bdst, -+ int (*cp)(struct dentry *dentry, aufs_bindex_t bdst, -+ struct dentry *h_parent, void *arg), -+ void *arg); -+int au_cpup_dirs(struct dentry *dentry, aufs_bindex_t bdst); -+int au_test_and_cpup_dirs(struct dentry *dentry, aufs_bindex_t bdst); -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* keep timestamps when copyup */ -+struct au_dtime { -+ struct dentry *dt_dentry; -+ struct path dt_h_path; -+ struct timespec dt_atime, dt_mtime; -+}; -+void au_dtime_store(struct au_dtime *dt, struct dentry *dentry, -+ struct path *h_path); -+void au_dtime_revert(struct au_dtime *dt); -+ -+#endif /* __KERNEL__ */ -+#endif /* __AUFS_CPUP_H__ */ -diff -Nur linux-2.6.37.orig/fs/aufs/dbgaufs.c linux-2.6.37/fs/aufs/dbgaufs.c ---- linux-2.6.37.orig/fs/aufs/dbgaufs.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/dbgaufs.c 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,334 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * debugfs interface -+ */ -+ -+#include -+#include "aufs.h" -+ -+#ifndef CONFIG_SYSFS -+#error DEBUG_FS depends upon SYSFS -+#endif -+ -+static struct dentry *dbgaufs; -+static const mode_t dbgaufs_mode = S_IRUSR | S_IRGRP | S_IROTH; -+ -+/* 20 is max digits length of ulong 64 */ -+struct dbgaufs_arg { -+ int n; -+ char a[20 * 4]; -+}; -+ -+/* -+ * common function for all XINO files -+ */ -+static int dbgaufs_xi_release(struct inode *inode __maybe_unused, -+ struct file *file) -+{ -+ kfree(file->private_data); -+ return 0; -+} -+ -+static int dbgaufs_xi_open(struct file *xf, struct file *file, int do_fcnt) -+{ -+ int err; -+ struct kstat st; -+ struct dbgaufs_arg *p; -+ -+ err = -ENOMEM; -+ p = kmalloc(sizeof(*p), GFP_NOFS); -+ if (unlikely(!p)) -+ goto out; -+ -+ err = 0; -+ p->n = 0; -+ file->private_data = p; -+ if (!xf) -+ goto out; -+ -+ err = vfs_getattr(xf->f_vfsmnt, xf->f_dentry, &st); -+ if (!err) { -+ if (do_fcnt) -+ p->n = snprintf -+ (p->a, sizeof(p->a), "%ld, %llux%lu %lld\n", -+ (long)file_count(xf), st.blocks, st.blksize, -+ (long long)st.size); -+ else -+ p->n = snprintf(p->a, sizeof(p->a), "%llux%lu %lld\n", -+ st.blocks, st.blksize, -+ (long long)st.size); -+ AuDebugOn(p->n >= sizeof(p->a)); -+ } else { -+ p->n = snprintf(p->a, sizeof(p->a), "err %d\n", err); -+ err = 0; -+ } -+ -+out: -+ return err; -+ -+} -+ -+static ssize_t dbgaufs_xi_read(struct file *file, char __user *buf, -+ size_t count, loff_t *ppos) -+{ -+ struct dbgaufs_arg *p; -+ -+ p = file->private_data; -+ return simple_read_from_buffer(buf, count, ppos, p->a, p->n); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int dbgaufs_xib_open(struct inode *inode, struct file *file) -+{ -+ int err; -+ struct au_sbinfo *sbinfo; -+ struct super_block *sb; -+ -+ sbinfo = inode->i_private; -+ sb = sbinfo->si_sb; -+ si_noflush_read_lock(sb); -+ err = dbgaufs_xi_open(sbinfo->si_xib, file, /*do_fcnt*/0); -+ si_read_unlock(sb); -+ return err; -+} -+ -+static const struct file_operations dbgaufs_xib_fop = { -+ .owner = THIS_MODULE, -+ .open = dbgaufs_xib_open, -+ .release = dbgaufs_xi_release, -+ .read = dbgaufs_xi_read -+}; -+ -+/* ---------------------------------------------------------------------- */ -+ -+#define DbgaufsXi_PREFIX "xi" -+ -+static int dbgaufs_xino_open(struct inode *inode, struct file *file) -+{ -+ int err; -+ long l; -+ struct au_sbinfo *sbinfo; -+ struct super_block *sb; -+ struct file *xf; -+ struct qstr *name; -+ -+ err = -ENOENT; -+ xf = NULL; -+ name = &file->f_dentry->d_name; -+ if (unlikely(name->len < sizeof(DbgaufsXi_PREFIX) -+ || memcmp(name->name, DbgaufsXi_PREFIX, -+ sizeof(DbgaufsXi_PREFIX) - 1))) -+ goto out; -+ err = strict_strtol(name->name + sizeof(DbgaufsXi_PREFIX) - 1, 10, &l); -+ if (unlikely(err)) -+ goto out; -+ -+ sbinfo = inode->i_private; -+ sb = sbinfo->si_sb; -+ si_noflush_read_lock(sb); -+ if (l <= au_sbend(sb)) { -+ xf = au_sbr(sb, (aufs_bindex_t)l)->br_xino.xi_file; -+ err = dbgaufs_xi_open(xf, file, /*do_fcnt*/1); -+ } else -+ err = -ENOENT; -+ si_read_unlock(sb); -+ -+out: -+ return err; -+} -+ -+static const struct file_operations dbgaufs_xino_fop = { -+ .owner = THIS_MODULE, -+ .open = dbgaufs_xino_open, -+ .release = dbgaufs_xi_release, -+ .read = dbgaufs_xi_read -+}; -+ -+void dbgaufs_brs_del(struct super_block *sb, aufs_bindex_t bindex) -+{ -+ aufs_bindex_t bend; -+ struct au_branch *br; -+ struct au_xino_file *xi; -+ -+ if (!au_sbi(sb)->si_dbgaufs) -+ return; -+ -+ bend = au_sbend(sb); -+ for (; bindex <= bend; bindex++) { -+ br = au_sbr(sb, bindex); -+ xi = &br->br_xino; -+ if (xi->xi_dbgaufs) { -+ debugfs_remove(xi->xi_dbgaufs); -+ xi->xi_dbgaufs = NULL; -+ } -+ } -+} -+ -+void dbgaufs_brs_add(struct super_block *sb, aufs_bindex_t bindex) -+{ -+ struct au_sbinfo *sbinfo; -+ struct dentry *parent; -+ struct au_branch *br; -+ struct au_xino_file *xi; -+ aufs_bindex_t bend; -+ char name[sizeof(DbgaufsXi_PREFIX) + 5]; /* "xi" bindex NULL */ -+ -+ sbinfo = au_sbi(sb); -+ parent = sbinfo->si_dbgaufs; -+ if (!parent) -+ return; -+ -+ bend = au_sbend(sb); -+ for (; bindex <= bend; bindex++) { -+ snprintf(name, sizeof(name), DbgaufsXi_PREFIX "%d", bindex); -+ br = au_sbr(sb, bindex); -+ xi = &br->br_xino; -+ AuDebugOn(xi->xi_dbgaufs); -+ xi->xi_dbgaufs = debugfs_create_file(name, dbgaufs_mode, parent, -+ sbinfo, &dbgaufs_xino_fop); -+ /* ignore an error */ -+ if (unlikely(!xi->xi_dbgaufs)) -+ AuWarn1("failed %s under debugfs\n", name); -+ } -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+#ifdef CONFIG_AUFS_EXPORT -+static int dbgaufs_xigen_open(struct inode *inode, struct file *file) -+{ -+ int err; -+ struct au_sbinfo *sbinfo; -+ struct super_block *sb; -+ -+ sbinfo = inode->i_private; -+ sb = sbinfo->si_sb; -+ si_noflush_read_lock(sb); -+ err = dbgaufs_xi_open(sbinfo->si_xigen, file, /*do_fcnt*/0); -+ si_read_unlock(sb); -+ return err; -+} -+ -+static const struct file_operations dbgaufs_xigen_fop = { -+ .owner = THIS_MODULE, -+ .open = dbgaufs_xigen_open, -+ .release = dbgaufs_xi_release, -+ .read = dbgaufs_xi_read -+}; -+ -+static int dbgaufs_xigen_init(struct au_sbinfo *sbinfo) -+{ -+ int err; -+ -+ /* -+ * This function is a dynamic '__init' fucntion actually, -+ * so the tiny check for si_rwsem is unnecessary. -+ */ -+ /* AuRwMustWriteLock(&sbinfo->si_rwsem); */ -+ -+ err = -EIO; -+ sbinfo->si_dbgaufs_xigen = debugfs_create_file -+ ("xigen", dbgaufs_mode, sbinfo->si_dbgaufs, sbinfo, -+ &dbgaufs_xigen_fop); -+ if (sbinfo->si_dbgaufs_xigen) -+ err = 0; -+ -+ return err; -+} -+#else -+static int dbgaufs_xigen_init(struct au_sbinfo *sbinfo) -+{ -+ return 0; -+} -+#endif /* CONFIG_AUFS_EXPORT */ -+ -+/* ---------------------------------------------------------------------- */ -+ -+void dbgaufs_si_fin(struct au_sbinfo *sbinfo) -+{ -+ /* -+ * This function is a dynamic '__init' fucntion actually, -+ * so the tiny check for si_rwsem is unnecessary. -+ */ -+ /* AuRwMustWriteLock(&sbinfo->si_rwsem); */ -+ -+ debugfs_remove_recursive(sbinfo->si_dbgaufs); -+ sbinfo->si_dbgaufs = NULL; -+ kobject_put(&sbinfo->si_kobj); -+} -+ -+int dbgaufs_si_init(struct au_sbinfo *sbinfo) -+{ -+ int err; -+ char name[SysaufsSiNameLen]; -+ -+ /* -+ * This function is a dynamic '__init' fucntion actually, -+ * so the tiny check for si_rwsem is unnecessary. -+ */ -+ /* AuRwMustWriteLock(&sbinfo->si_rwsem); */ -+ -+ err = -ENOENT; -+ if (!dbgaufs) { -+ AuErr1("/debug/aufs is uninitialized\n"); -+ goto out; -+ } -+ -+ err = -EIO; -+ sysaufs_name(sbinfo, name); -+ sbinfo->si_dbgaufs = debugfs_create_dir(name, dbgaufs); -+ if (unlikely(!sbinfo->si_dbgaufs)) -+ goto out; -+ kobject_get(&sbinfo->si_kobj); -+ -+ sbinfo->si_dbgaufs_xib = debugfs_create_file -+ ("xib", dbgaufs_mode, sbinfo->si_dbgaufs, sbinfo, -+ &dbgaufs_xib_fop); -+ if (unlikely(!sbinfo->si_dbgaufs_xib)) -+ goto out_dir; -+ -+ err = dbgaufs_xigen_init(sbinfo); -+ if (!err) -+ goto out; /* success */ -+ -+out_dir: -+ dbgaufs_si_fin(sbinfo); -+out: -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+void dbgaufs_fin(void) -+{ -+ debugfs_remove(dbgaufs); -+} -+ -+int __init dbgaufs_init(void) -+{ -+ int err; -+ -+ err = -EIO; -+ dbgaufs = debugfs_create_dir(AUFS_NAME, NULL); -+ if (dbgaufs) -+ err = 0; -+ return err; -+} -diff -Nur linux-2.6.37.orig/fs/aufs/dbgaufs.h linux-2.6.37/fs/aufs/dbgaufs.h ---- linux-2.6.37.orig/fs/aufs/dbgaufs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/dbgaufs.h 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,52 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * debugfs interface -+ */ -+ -+#ifndef __DBGAUFS_H__ -+#define __DBGAUFS_H__ -+ -+#ifdef __KERNEL__ -+ -+#include -+#include -+ -+struct super_block; -+struct au_sbinfo; -+ -+#ifdef CONFIG_DEBUG_FS -+/* dbgaufs.c */ -+void dbgaufs_brs_del(struct super_block *sb, aufs_bindex_t bindex); -+void dbgaufs_brs_add(struct super_block *sb, aufs_bindex_t bindex); -+void dbgaufs_si_fin(struct au_sbinfo *sbinfo); -+int dbgaufs_si_init(struct au_sbinfo *sbinfo); -+void dbgaufs_fin(void); -+int __init dbgaufs_init(void); -+#else -+AuStubVoid(dbgaufs_brs_del, struct super_block *sb, aufs_bindex_t bindex) -+AuStubVoid(dbgaufs_brs_add, struct super_block *sb, aufs_bindex_t bindex) -+AuStubVoid(dbgaufs_si_fin, struct au_sbinfo *sbinfo) -+AuStubInt0(dbgaufs_si_init, struct au_sbinfo *sbinfo) -+AuStubVoid(dbgaufs_fin, void) -+AuStubInt0(__init dbgaufs_init, void) -+#endif /* CONFIG_DEBUG_FS */ -+ -+#endif /* __KERNEL__ */ -+#endif /* __DBGAUFS_H__ */ -diff -Nur linux-2.6.37.orig/fs/aufs/dcsub.c linux-2.6.37/fs/aufs/dcsub.c ---- linux-2.6.37.orig/fs/aufs/dcsub.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/dcsub.c 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,210 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * sub-routines for dentry cache -+ */ -+ -+#include "aufs.h" -+ -+static void au_dpage_free(struct au_dpage *dpage) -+{ -+ int i; -+ struct dentry **p; -+ -+ p = dpage->dentries; -+ for (i = 0; i < dpage->ndentry; i++) -+ dput(*p++); -+ free_page((unsigned long)dpage->dentries); -+} -+ -+int au_dpages_init(struct au_dcsub_pages *dpages, gfp_t gfp) -+{ -+ int err; -+ void *p; -+ -+ err = -ENOMEM; -+ dpages->dpages = kmalloc(sizeof(*dpages->dpages), gfp); -+ if (unlikely(!dpages->dpages)) -+ goto out; -+ -+ p = (void *)__get_free_page(gfp); -+ if (unlikely(!p)) -+ goto out_dpages; -+ -+ dpages->dpages[0].ndentry = 0; -+ dpages->dpages[0].dentries = p; -+ dpages->ndpage = 1; -+ return 0; /* success */ -+ -+out_dpages: -+ kfree(dpages->dpages); -+out: -+ return err; -+} -+ -+void au_dpages_free(struct au_dcsub_pages *dpages) -+{ -+ int i; -+ struct au_dpage *p; -+ -+ p = dpages->dpages; -+ for (i = 0; i < dpages->ndpage; i++) -+ au_dpage_free(p++); -+ kfree(dpages->dpages); -+} -+ -+static int au_dpages_append(struct au_dcsub_pages *dpages, -+ struct dentry *dentry, gfp_t gfp) -+{ -+ int err, sz; -+ struct au_dpage *dpage; -+ void *p; -+ -+ dpage = dpages->dpages + dpages->ndpage - 1; -+ sz = PAGE_SIZE / sizeof(dentry); -+ if (unlikely(dpage->ndentry >= sz)) { -+ AuLabel(new dpage); -+ err = -ENOMEM; -+ sz = dpages->ndpage * sizeof(*dpages->dpages); -+ p = au_kzrealloc(dpages->dpages, sz, -+ sz + sizeof(*dpages->dpages), gfp); -+ if (unlikely(!p)) -+ goto out; -+ -+ dpages->dpages = p; -+ dpage = dpages->dpages + dpages->ndpage; -+ p = (void *)__get_free_page(gfp); -+ if (unlikely(!p)) -+ goto out; -+ -+ dpage->ndentry = 0; -+ dpage->dentries = p; -+ dpages->ndpage++; -+ } -+ -+ /* d_count can be zero */ -+ dpage->dentries[dpage->ndentry++] = dget_locked(dentry); -+ return 0; /* success */ -+ -+out: -+ return err; -+} -+ -+int au_dcsub_pages(struct au_dcsub_pages *dpages, struct dentry *root, -+ au_dpages_test test, void *arg) -+{ -+ int err; -+ struct dentry *this_parent = root; -+ struct list_head *next; -+ struct super_block *sb = root->d_sb; -+ -+ err = 0; -+ spin_lock(&dcache_lock); -+repeat: -+ next = this_parent->d_subdirs.next; -+resume: -+ if (this_parent->d_sb == sb -+ && !IS_ROOT(this_parent) -+ && au_di(this_parent) -+ && (!test || test(this_parent, arg))) { -+ err = au_dpages_append(dpages, this_parent, GFP_ATOMIC); -+ if (unlikely(err)) -+ goto out; -+ } -+ -+ while (next != &this_parent->d_subdirs) { -+ struct list_head *tmp = next; -+ struct dentry *dentry = list_entry(tmp, struct dentry, -+ d_u.d_child); -+ next = tmp->next; -+ if (!list_empty(&dentry->d_subdirs)) { -+ this_parent = dentry; -+ goto repeat; -+ } -+ if (dentry->d_sb == sb -+ && au_di(dentry) -+ && (!test || test(dentry, arg))) { -+ err = au_dpages_append(dpages, dentry, GFP_ATOMIC); -+ if (unlikely(err)) -+ goto out; -+ } -+ } -+ -+ if (this_parent != root) { -+ next = this_parent->d_u.d_child.next; -+ this_parent = this_parent->d_parent; /* dcache_lock is locked */ -+ goto resume; -+ } -+out: -+ spin_unlock(&dcache_lock); -+ return err; -+} -+ -+int au_dcsub_pages_rev(struct au_dcsub_pages *dpages, struct dentry *dentry, -+ int do_include, au_dpages_test test, void *arg) -+{ -+ int err; -+ -+ err = 0; -+ spin_lock(&dcache_lock); -+ if (do_include && (!test || test(dentry, arg))) { -+ err = au_dpages_append(dpages, dentry, GFP_ATOMIC); -+ if (unlikely(err)) -+ goto out; -+ } -+ while (!IS_ROOT(dentry)) { -+ dentry = dentry->d_parent; /* dcache_lock is locked */ -+ if (!test || test(dentry, arg)) { -+ err = au_dpages_append(dpages, dentry, GFP_ATOMIC); -+ if (unlikely(err)) -+ break; -+ } -+ } -+ -+out: -+ spin_unlock(&dcache_lock); -+ -+ return err; -+} -+ -+static inline int au_dcsub_dpages_aufs(struct dentry *dentry, void *arg) -+{ -+ return au_di(dentry) && dentry->d_sb == arg; -+} -+ -+int au_dcsub_pages_rev_aufs(struct au_dcsub_pages *dpages, -+ struct dentry *dentry, int do_include) -+{ -+ return au_dcsub_pages_rev(dpages, dentry, do_include, -+ au_dcsub_dpages_aufs, dentry->d_sb); -+} -+ -+int au_test_subdir(struct dentry *d1, struct dentry *d2) -+{ -+ struct path path[2] = { -+ { -+ .dentry = d1 -+ }, -+ { -+ .dentry = d2 -+ } -+ }; -+ -+ return path_is_under(path + 0, path + 1); -+} -diff -Nur linux-2.6.37.orig/fs/aufs/dcsub.h linux-2.6.37/fs/aufs/dcsub.h ---- linux-2.6.37.orig/fs/aufs/dcsub.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/dcsub.h 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,100 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * sub-routines for dentry cache -+ */ -+ -+#ifndef __AUFS_DCSUB_H__ -+#define __AUFS_DCSUB_H__ -+ -+#ifdef __KERNEL__ -+ -+#include -+#include -+#include -+ -+struct dentry; -+ -+struct au_dpage { -+ int ndentry; -+ struct dentry **dentries; -+}; -+ -+struct au_dcsub_pages { -+ int ndpage; -+ struct au_dpage *dpages; -+}; -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* dcsub.c */ -+int au_dpages_init(struct au_dcsub_pages *dpages, gfp_t gfp); -+void au_dpages_free(struct au_dcsub_pages *dpages); -+typedef int (*au_dpages_test)(struct dentry *dentry, void *arg); -+int au_dcsub_pages(struct au_dcsub_pages *dpages, struct dentry *root, -+ au_dpages_test test, void *arg); -+int au_dcsub_pages_rev(struct au_dcsub_pages *dpages, struct dentry *dentry, -+ int do_include, au_dpages_test test, void *arg); -+int au_dcsub_pages_rev_aufs(struct au_dcsub_pages *dpages, -+ struct dentry *dentry, int do_include); -+int au_test_subdir(struct dentry *d1, struct dentry *d2); -+ -+/* ---------------------------------------------------------------------- */ -+ -+static inline int au_d_removed(struct dentry *d) -+{ -+ return !IS_ROOT(d) && d_unhashed(d); -+} -+ -+static inline int au_d_hashed_positive(struct dentry *d) -+{ -+ int err; -+ struct inode *inode = d->d_inode; -+ err = 0; -+ if (unlikely(d_unhashed(d) || !inode || !inode->i_nlink)) -+ err = -ENOENT; -+ return err; -+} -+ -+static inline int au_d_alive(struct dentry *d) -+{ -+ int err; -+ struct inode *inode; -+ err = 0; -+ if (!IS_ROOT(d)) -+ err = au_d_hashed_positive(d); -+ else { -+ inode = d->d_inode; -+ if (unlikely(au_d_removed(d) || !inode || !inode->i_nlink)) -+ err = -ENOENT; -+ } -+ return err; -+} -+ -+static inline int au_alive_dir(struct dentry *d) -+{ -+ int err; -+ err = au_d_alive(d); -+ if (unlikely(err || IS_DEADDIR(d->d_inode))) -+ err = -ENOENT; -+ return err; -+} -+ -+#endif /* __KERNEL__ */ -+#endif /* __AUFS_DCSUB_H__ */ -diff -Nur linux-2.6.37.orig/fs/aufs/debug.c linux-2.6.37/fs/aufs/debug.c ---- linux-2.6.37.orig/fs/aufs/debug.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/debug.c 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,468 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * debug print functions -+ */ -+ -+#include -+#include -+#include "aufs.h" -+ -+int aufs_debug; -+MODULE_PARM_DESC(debug, "debug print"); -+module_param_named(debug, aufs_debug, int, S_IRUGO | S_IWUSR | S_IWGRP); -+ -+char *au_plevel = KERN_DEBUG; -+#define dpri(fmt, ...) do { \ -+ if ((au_plevel \ -+ && strcmp(au_plevel, KERN_DEBUG)) \ -+ || au_debug_test()) \ -+ printk("%s" fmt, au_plevel, ##__VA_ARGS__); \ -+} while (0) -+ -+/* ---------------------------------------------------------------------- */ -+ -+void au_dpri_whlist(struct au_nhash *whlist) -+{ -+ unsigned long ul, n; -+ struct hlist_head *head; -+ struct au_vdir_wh *tpos; -+ struct hlist_node *pos; -+ -+ n = whlist->nh_num; -+ head = whlist->nh_head; -+ for (ul = 0; ul < n; ul++) { -+ hlist_for_each_entry(tpos, pos, head, wh_hash) -+ dpri("b%d, %.*s, %d\n", -+ tpos->wh_bindex, -+ tpos->wh_str.len, tpos->wh_str.name, -+ tpos->wh_str.len); -+ head++; -+ } -+} -+ -+void au_dpri_vdir(struct au_vdir *vdir) -+{ -+ unsigned long ul; -+ union au_vdir_deblk_p p; -+ unsigned char *o; -+ -+ if (!vdir || IS_ERR(vdir)) { -+ dpri("err %ld\n", PTR_ERR(vdir)); -+ return; -+ } -+ -+ dpri("deblk %u, nblk %lu, deblk %p, last{%lu, %p}, ver %lu\n", -+ vdir->vd_deblk_sz, vdir->vd_nblk, vdir->vd_deblk, -+ vdir->vd_last.ul, vdir->vd_last.p.deblk, vdir->vd_version); -+ for (ul = 0; ul < vdir->vd_nblk; ul++) { -+ p.deblk = vdir->vd_deblk[ul]; -+ o = p.deblk; -+ dpri("[%lu]: %p\n", ul, o); -+ } -+} -+ -+static int do_pri_inode(aufs_bindex_t bindex, struct inode *inode, -+ struct dentry *wh) -+{ -+ char *n = NULL; -+ int l = 0; -+ -+ if (!inode || IS_ERR(inode)) { -+ dpri("i%d: err %ld\n", bindex, PTR_ERR(inode)); -+ return -1; -+ } -+ -+ /* the type of i_blocks depends upon CONFIG_LSF */ -+ BUILD_BUG_ON(sizeof(inode->i_blocks) != sizeof(unsigned long) -+ && sizeof(inode->i_blocks) != sizeof(u64)); -+ if (wh) { -+ n = (void *)wh->d_name.name; -+ l = wh->d_name.len; -+ } -+ -+ dpri("i%d: i%lu, %s, cnt %d, nl %u, 0%o, sz %llu, blk %llu," -+ " ct %lld, np %lu, st 0x%lx, f 0x%x, v %llu, g %x%s%.*s\n", -+ bindex, -+ inode->i_ino, inode->i_sb ? au_sbtype(inode->i_sb) : "??", -+ atomic_read(&inode->i_count), inode->i_nlink, inode->i_mode, -+ i_size_read(inode), (unsigned long long)inode->i_blocks, -+ (long long)timespec_to_ns(&inode->i_ctime) & 0x0ffff, -+ inode->i_mapping ? inode->i_mapping->nrpages : 0, -+ inode->i_state, inode->i_flags, inode->i_version, -+ inode->i_generation, -+ l ? ", wh " : "", l, n); -+ return 0; -+} -+ -+void au_dpri_inode(struct inode *inode) -+{ -+ struct au_iinfo *iinfo; -+ aufs_bindex_t bindex; -+ int err; -+ -+ err = do_pri_inode(-1, inode, NULL); -+ if (err || !au_test_aufs(inode->i_sb)) -+ return; -+ -+ iinfo = au_ii(inode); -+ if (!iinfo) -+ return; -+ dpri("i-1: bstart %d, bend %d, gen %d\n", -+ iinfo->ii_bstart, iinfo->ii_bend, au_iigen(inode)); -+ if (iinfo->ii_bstart < 0) -+ return; -+ for (bindex = iinfo->ii_bstart; bindex <= iinfo->ii_bend; bindex++) -+ do_pri_inode(bindex, iinfo->ii_hinode[0 + bindex].hi_inode, -+ iinfo->ii_hinode[0 + bindex].hi_whdentry); -+} -+ -+static int do_pri_dentry(aufs_bindex_t bindex, struct dentry *dentry) -+{ -+ struct dentry *wh = NULL; -+ -+ if (!dentry || IS_ERR(dentry)) { -+ dpri("d%d: err %ld\n", bindex, PTR_ERR(dentry)); -+ return -1; -+ } -+ /* do not call dget_parent() here */ -+ dpri("d%d: %.*s?/%.*s, %s, cnt %d, flags 0x%x\n", -+ bindex, -+ AuDLNPair(dentry->d_parent), AuDLNPair(dentry), -+ dentry->d_sb ? au_sbtype(dentry->d_sb) : "??", -+ atomic_read(&dentry->d_count), dentry->d_flags); -+ if (bindex >= 0 && dentry->d_inode && au_test_aufs(dentry->d_sb)) { -+ struct au_iinfo *iinfo = au_ii(dentry->d_inode); -+ if (iinfo) -+ wh = iinfo->ii_hinode[0 + bindex].hi_whdentry; -+ } -+ do_pri_inode(bindex, dentry->d_inode, wh); -+ return 0; -+} -+ -+void au_dpri_dentry(struct dentry *dentry) -+{ -+ struct au_dinfo *dinfo; -+ aufs_bindex_t bindex; -+ int err; -+ struct au_hdentry *hdp; -+ -+ err = do_pri_dentry(-1, dentry); -+ if (err || !au_test_aufs(dentry->d_sb)) -+ return; -+ -+ dinfo = au_di(dentry); -+ if (!dinfo) -+ return; -+ dpri("d-1: bstart %d, bend %d, bwh %d, bdiropq %d, gen %d\n", -+ dinfo->di_bstart, dinfo->di_bend, -+ dinfo->di_bwh, dinfo->di_bdiropq, au_digen(dentry)); -+ if (dinfo->di_bstart < 0) -+ return; -+ hdp = dinfo->di_hdentry; -+ for (bindex = dinfo->di_bstart; bindex <= dinfo->di_bend; bindex++) -+ do_pri_dentry(bindex, hdp[0 + bindex].hd_dentry); -+} -+ -+static int do_pri_file(aufs_bindex_t bindex, struct file *file) -+{ -+ char a[32]; -+ -+ if (!file || IS_ERR(file)) { -+ dpri("f%d: err %ld\n", bindex, PTR_ERR(file)); -+ return -1; -+ } -+ a[0] = 0; -+ if (bindex < 0 -+ && file->f_dentry -+ && au_test_aufs(file->f_dentry->d_sb) -+ && au_fi(file)) -+ snprintf(a, sizeof(a), ", gen %d, mmapped %d", -+ au_figen(file), !!au_fi(file)->fi_hvmop); -+ dpri("f%d: mode 0x%x, flags 0%o, cnt %ld, v %llu, pos %llu%s\n", -+ bindex, file->f_mode, file->f_flags, (long)file_count(file), -+ file->f_version, file->f_pos, a); -+ if (file->f_dentry) -+ do_pri_dentry(bindex, file->f_dentry); -+ return 0; -+} -+ -+void au_dpri_file(struct file *file) -+{ -+ struct au_finfo *finfo; -+ struct au_fidir *fidir; -+ struct au_hfile *hfile; -+ aufs_bindex_t bindex; -+ int err; -+ -+ err = do_pri_file(-1, file); -+ if (err || !file->f_dentry || !au_test_aufs(file->f_dentry->d_sb)) -+ return; -+ -+ finfo = au_fi(file); -+ if (!finfo) -+ return; -+ if (finfo->fi_btop < 0) -+ return; -+ fidir = finfo->fi_hdir; -+ if (!fidir) -+ do_pri_file(finfo->fi_btop, finfo->fi_htop.hf_file); -+ else -+ for (bindex = finfo->fi_btop; -+ bindex >= 0 && bindex <= fidir->fd_bbot; -+ bindex++) { -+ hfile = fidir->fd_hfile + bindex; -+ do_pri_file(bindex, hfile ? hfile->hf_file : NULL); -+ } -+} -+ -+static int do_pri_br(aufs_bindex_t bindex, struct au_branch *br) -+{ -+ struct vfsmount *mnt; -+ struct super_block *sb; -+ -+ if (!br || IS_ERR(br)) -+ goto out; -+ mnt = br->br_mnt; -+ if (!mnt || IS_ERR(mnt)) -+ goto out; -+ sb = mnt->mnt_sb; -+ if (!sb || IS_ERR(sb)) -+ goto out; -+ -+ dpri("s%d: {perm 0x%x, cnt %d, wbr %p}, " -+ "%s, dev 0x%02x%02x, flags 0x%lx, cnt %d, active %d, " -+ "xino %d\n", -+ bindex, br->br_perm, atomic_read(&br->br_count), br->br_wbr, -+ au_sbtype(sb), MAJOR(sb->s_dev), MINOR(sb->s_dev), -+ sb->s_flags, sb->s_count, -+ atomic_read(&sb->s_active), !!br->br_xino.xi_file); -+ return 0; -+ -+out: -+ dpri("s%d: err %ld\n", bindex, PTR_ERR(br)); -+ return -1; -+} -+ -+void au_dpri_sb(struct super_block *sb) -+{ -+ struct au_sbinfo *sbinfo; -+ aufs_bindex_t bindex; -+ int err; -+ /* to reuduce stack size */ -+ struct { -+ struct vfsmount mnt; -+ struct au_branch fake; -+ } *a; -+ -+ /* this function can be called from magic sysrq */ -+ a = kzalloc(sizeof(*a), GFP_ATOMIC); -+ if (unlikely(!a)) { -+ dpri("no memory\n"); -+ return; -+ } -+ -+ a->mnt.mnt_sb = sb; -+ a->fake.br_perm = 0; -+ a->fake.br_mnt = &a->mnt; -+ a->fake.br_xino.xi_file = NULL; -+ atomic_set(&a->fake.br_count, 0); -+ smp_mb(); /* atomic_set */ -+ err = do_pri_br(-1, &a->fake); -+ kfree(a); -+ dpri("dev 0x%x\n", sb->s_dev); -+ if (err || !au_test_aufs(sb)) -+ return; -+ -+ sbinfo = au_sbi(sb); -+ if (!sbinfo) -+ return; -+ dpri("nw %d, gen %u, kobj %d\n", -+ atomic_read(&sbinfo->si_nowait.nw_len), sbinfo->si_generation, -+ atomic_read(&sbinfo->si_kobj.kref.refcount)); -+ for (bindex = 0; bindex <= sbinfo->si_bend; bindex++) -+ do_pri_br(bindex, sbinfo->si_branch[0 + bindex]); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+void au_dbg_sleep_jiffy(int jiffy) -+{ -+ while (jiffy) -+ jiffy = schedule_timeout_uninterruptible(jiffy); -+} -+ -+void au_dbg_iattr(struct iattr *ia) -+{ -+#define AuBit(name) if (ia->ia_valid & ATTR_ ## name) \ -+ dpri(#name "\n") -+ AuBit(MODE); -+ AuBit(UID); -+ AuBit(GID); -+ AuBit(SIZE); -+ AuBit(ATIME); -+ AuBit(MTIME); -+ AuBit(CTIME); -+ AuBit(ATIME_SET); -+ AuBit(MTIME_SET); -+ AuBit(FORCE); -+ AuBit(ATTR_FLAG); -+ AuBit(KILL_SUID); -+ AuBit(KILL_SGID); -+ AuBit(FILE); -+ AuBit(KILL_PRIV); -+ AuBit(OPEN); -+ AuBit(TIMES_SET); -+#undef AuBit -+ dpri("ia_file %p\n", ia->ia_file); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+void __au_dbg_verify_dinode(struct dentry *dentry, const char *func, int line) -+{ -+ struct inode *h_inode, *inode = dentry->d_inode; -+ struct dentry *h_dentry; -+ aufs_bindex_t bindex, bend, bi; -+ -+ if (!inode /* || au_di(dentry)->di_lsc == AuLsc_DI_TMP */) -+ return; -+ -+ bend = au_dbend(dentry); -+ bi = au_ibend(inode); -+ if (bi < bend) -+ bend = bi; -+ bindex = au_dbstart(dentry); -+ bi = au_ibstart(inode); -+ if (bi > bindex) -+ bindex = bi; -+ -+ for (; bindex <= bend; bindex++) { -+ h_dentry = au_h_dptr(dentry, bindex); -+ if (!h_dentry) -+ continue; -+ h_inode = au_h_iptr(inode, bindex); -+ if (unlikely(h_inode != h_dentry->d_inode)) { -+ int old = au_debug_test(); -+ if (!old) -+ au_debug(1); -+ AuDbg("b%d, %s:%d\n", bindex, func, line); -+ AuDbgDentry(dentry); -+ AuDbgInode(inode); -+ if (!old) -+ au_debug(0); -+ BUG(); -+ } -+ } -+} -+ -+void au_dbg_verify_dir_parent(struct dentry *dentry, unsigned int sigen) -+{ -+ struct dentry *parent; -+ -+ parent = dget_parent(dentry); -+ AuDebugOn(!S_ISDIR(dentry->d_inode->i_mode)); -+ AuDebugOn(IS_ROOT(dentry)); -+ AuDebugOn(au_digen_test(parent, sigen)); -+ dput(parent); -+} -+ -+void au_dbg_verify_nondir_parent(struct dentry *dentry, unsigned int sigen) -+{ -+ struct dentry *parent; -+ struct inode *inode; -+ -+ parent = dget_parent(dentry); -+ inode = dentry->d_inode; -+ AuDebugOn(inode && S_ISDIR(dentry->d_inode->i_mode)); -+ AuDebugOn(au_digen_test(parent, sigen)); -+ dput(parent); -+} -+ -+void au_dbg_verify_gen(struct dentry *parent, unsigned int sigen) -+{ -+ int err, i, j; -+ struct au_dcsub_pages dpages; -+ struct au_dpage *dpage; -+ struct dentry **dentries; -+ -+ err = au_dpages_init(&dpages, GFP_NOFS); -+ AuDebugOn(err); -+ err = au_dcsub_pages_rev_aufs(&dpages, parent, /*do_include*/1); -+ AuDebugOn(err); -+ for (i = dpages.ndpage - 1; !err && i >= 0; i--) { -+ dpage = dpages.dpages + i; -+ dentries = dpage->dentries; -+ for (j = dpage->ndentry - 1; !err && j >= 0; j--) -+ AuDebugOn(au_digen_test(dentries[j], sigen)); -+ } -+ au_dpages_free(&dpages); -+} -+ -+void au_dbg_verify_kthread(void) -+{ -+ if (current->flags & PF_WQ_WORKER) { -+ au_dbg_blocked(); -+ WARN_ON(1); -+ } -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+void au_debug_sbinfo_init(struct au_sbinfo *sbinfo __maybe_unused) -+{ -+#ifdef AuForceNoPlink -+ au_opt_clr(sbinfo->si_mntflags, PLINK); -+#endif -+#ifdef AuForceNoXino -+ au_opt_clr(sbinfo->si_mntflags, XINO); -+#endif -+#ifdef AuForceNoRefrof -+ au_opt_clr(sbinfo->si_mntflags, REFROF); -+#endif -+#ifdef AuForceHnotify -+ au_opt_set_udba(sbinfo->si_mntflags, UDBA_HNOTIFY); -+#endif -+#ifdef AuForceRd0 -+ sbinfo->si_rdblk = 0; -+ sbinfo->si_rdhash = 0; -+#endif -+} -+ -+int __init au_debug_init(void) -+{ -+ aufs_bindex_t bindex; -+ struct au_vdir_destr destr; -+ -+ bindex = -1; -+ AuDebugOn(bindex >= 0); -+ -+ destr.len = -1; -+ AuDebugOn(destr.len < NAME_MAX); -+ -+#ifdef CONFIG_4KSTACKS -+ pr_warning("CONFIG_4KSTACKS is defined.\n"); -+#endif -+ -+#ifdef AuForceNoBrs -+ sysaufs_brs = 0; -+#endif -+ -+ return 0; -+} -diff -Nur linux-2.6.37.orig/fs/aufs/debug.h linux-2.6.37/fs/aufs/debug.h ---- linux-2.6.37.orig/fs/aufs/debug.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/debug.h 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,245 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * debug print functions -+ */ -+ -+#ifndef __AUFS_DEBUG_H__ -+#define __AUFS_DEBUG_H__ -+ -+#ifdef __KERNEL__ -+ -+#include -+#include -+/* #include */ -+#include -+#include -+#include -+/* #include */ -+#include -+/* #include */ -+#include -+#include -+ -+#include -+ -+#ifdef CONFIG_AUFS_DEBUG -+#define AuDebugOn(a) BUG_ON(a) -+ -+/* module parameter */ -+extern int aufs_debug; -+static inline void au_debug(int n) -+{ -+ aufs_debug = n; -+ smp_mb(); -+} -+ -+static inline int au_debug_test(void) -+{ -+ return aufs_debug; -+} -+#else -+#define AuDebugOn(a) do {} while (0) -+AuStubVoid(au_debug, int n) -+AuStubInt0(au_debug_test, void) -+#endif /* CONFIG_AUFS_DEBUG */ -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* debug print */ -+ -+#define AuDbg(fmt, ...) do { \ -+ if (au_debug_test()) \ -+ pr_debug("DEBUG: " fmt, ##__VA_ARGS__); \ -+} while (0) -+#define AuLabel(l) AuDbg(#l "\n") -+#define AuIOErr(fmt, ...) pr_err("I/O Error, " fmt, ##__VA_ARGS__) -+#define AuWarn1(fmt, ...) do { \ -+ static unsigned char _c; \ -+ if (!_c++) \ -+ pr_warning(fmt, ##__VA_ARGS__); \ -+} while (0) -+ -+#define AuErr1(fmt, ...) do { \ -+ static unsigned char _c; \ -+ if (!_c++) \ -+ pr_err(fmt, ##__VA_ARGS__); \ -+} while (0) -+ -+#define AuIOErr1(fmt, ...) do { \ -+ static unsigned char _c; \ -+ if (!_c++) \ -+ AuIOErr(fmt, ##__VA_ARGS__); \ -+} while (0) -+ -+#define AuUnsupportMsg "This operation is not supported." \ -+ " Please report this application to aufs-users ML." -+#define AuUnsupport(fmt, ...) do { \ -+ pr_err(AuUnsupportMsg "\n" fmt, ##__VA_ARGS__); \ -+ dump_stack(); \ -+} while (0) -+ -+#define AuTraceErr(e) do { \ -+ if (unlikely((e) < 0)) \ -+ AuDbg("err %d\n", (int)(e)); \ -+} while (0) -+ -+#define AuTraceErrPtr(p) do { \ -+ if (IS_ERR(p)) \ -+ AuDbg("err %ld\n", PTR_ERR(p)); \ -+} while (0) -+ -+/* dirty macros for debug print, use with "%.*s" and caution */ -+#define AuLNPair(qstr) (qstr)->len, (qstr)->name -+#define AuDLNPair(d) AuLNPair(&(d)->d_name) -+ -+/* ---------------------------------------------------------------------- */ -+ -+struct au_sbinfo; -+struct au_finfo; -+struct dentry; -+#ifdef CONFIG_AUFS_DEBUG -+extern char *au_plevel; -+struct au_nhash; -+void au_dpri_whlist(struct au_nhash *whlist); -+struct au_vdir; -+void au_dpri_vdir(struct au_vdir *vdir); -+struct inode; -+void au_dpri_inode(struct inode *inode); -+void au_dpri_dentry(struct dentry *dentry); -+struct file; -+void au_dpri_file(struct file *filp); -+struct super_block; -+void au_dpri_sb(struct super_block *sb); -+ -+void au_dbg_sleep_jiffy(int jiffy); -+struct iattr; -+void au_dbg_iattr(struct iattr *ia); -+ -+#define au_dbg_verify_dinode(d) __au_dbg_verify_dinode(d, __func__, __LINE__) -+void __au_dbg_verify_dinode(struct dentry *dentry, const char *func, int line); -+void au_dbg_verify_dir_parent(struct dentry *dentry, unsigned int sigen); -+void au_dbg_verify_nondir_parent(struct dentry *dentry, unsigned int sigen); -+void au_dbg_verify_gen(struct dentry *parent, unsigned int sigen); -+void au_dbg_verify_kthread(void); -+ -+int __init au_debug_init(void); -+void au_debug_sbinfo_init(struct au_sbinfo *sbinfo); -+#define AuDbgWhlist(w) do { \ -+ AuDbg(#w "\n"); \ -+ au_dpri_whlist(w); \ -+} while (0) -+ -+#define AuDbgVdir(v) do { \ -+ AuDbg(#v "\n"); \ -+ au_dpri_vdir(v); \ -+} while (0) -+ -+#define AuDbgInode(i) do { \ -+ AuDbg(#i "\n"); \ -+ au_dpri_inode(i); \ -+} while (0) -+ -+#define AuDbgDentry(d) do { \ -+ AuDbg(#d "\n"); \ -+ au_dpri_dentry(d); \ -+} while (0) -+ -+#define AuDbgFile(f) do { \ -+ AuDbg(#f "\n"); \ -+ au_dpri_file(f); \ -+} while (0) -+ -+#define AuDbgSb(sb) do { \ -+ AuDbg(#sb "\n"); \ -+ au_dpri_sb(sb); \ -+} while (0) -+ -+#define AuDbgSleep(sec) do { \ -+ AuDbg("sleep %d sec\n", sec); \ -+ ssleep(sec); \ -+} while (0) -+ -+#define AuDbgSleepJiffy(jiffy) do { \ -+ AuDbg("sleep %d jiffies\n", jiffy); \ -+ au_dbg_sleep_jiffy(jiffy); \ -+} while (0) -+ -+#define AuDbgIAttr(ia) do { \ -+ AuDbg("ia_valid 0x%x\n", (ia)->ia_valid); \ -+ au_dbg_iattr(ia); \ -+} while (0) -+ -+#define AuDbgSym(addr) do { \ -+ char sym[KSYM_SYMBOL_LEN]; \ -+ sprint_symbol(sym, (unsigned long)addr); \ -+ AuDbg("%s\n", sym); \ -+} while (0) -+ -+#define AuInfoSym(addr) do { \ -+ char sym[KSYM_SYMBOL_LEN]; \ -+ sprint_symbol(sym, (unsigned long)addr); \ -+ AuInfo("%s\n", sym); \ -+} while (0) -+#else -+AuStubVoid(au_dbg_verify_dinode, struct dentry *dentry) -+AuStubVoid(au_dbg_verify_dir_parent, struct dentry *dentry, unsigned int sigen) -+AuStubVoid(au_dbg_verify_nondir_parent, struct dentry *dentry, -+ unsigned int sigen) -+AuStubVoid(au_dbg_verify_gen, struct dentry *parent, unsigned int sigen) -+AuStubVoid(au_dbg_verify_kthread, void) -+AuStubInt0(__init au_debug_init, void) -+AuStubVoid(au_debug_sbinfo_init, struct au_sbinfo *sbinfo) -+ -+#define AuDbgWhlist(w) do {} while (0) -+#define AuDbgVdir(v) do {} while (0) -+#define AuDbgInode(i) do {} while (0) -+#define AuDbgDentry(d) do {} while (0) -+#define AuDbgFile(f) do {} while (0) -+#define AuDbgSb(sb) do {} while (0) -+#define AuDbgSleep(sec) do {} while (0) -+#define AuDbgSleepJiffy(jiffy) do {} while (0) -+#define AuDbgIAttr(ia) do {} while (0) -+#define AuDbgSym(addr) do {} while (0) -+#define AuInfoSym(addr) do {} while (0) -+#endif /* CONFIG_AUFS_DEBUG */ -+ -+/* ---------------------------------------------------------------------- */ -+ -+#ifdef CONFIG_AUFS_MAGIC_SYSRQ -+int __init au_sysrq_init(void); -+void au_sysrq_fin(void); -+ -+#ifdef CONFIG_HW_CONSOLE -+#define au_dbg_blocked() do { \ -+ WARN_ON(1); \ -+ handle_sysrq('w'); \ -+} while (0) -+#else -+AuStubVoid(au_dbg_blocked, void) -+#endif -+ -+#else -+AuStubInt0(__init au_sysrq_init, void) -+AuStubVoid(au_sysrq_fin, void) -+AuStubVoid(au_dbg_blocked, void) -+#endif /* CONFIG_AUFS_MAGIC_SYSRQ */ -+ -+#endif /* __KERNEL__ */ -+#endif /* __AUFS_DEBUG_H__ */ -diff -Nur linux-2.6.37.orig/fs/aufs/dentry.c linux-2.6.37/fs/aufs/dentry.c ---- linux-2.6.37.orig/fs/aufs/dentry.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/dentry.c 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,1131 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * lookup and dentry operations -+ */ -+ -+#include -+#include "aufs.h" -+ -+static void au_h_nd(struct nameidata *h_nd, struct nameidata *nd) -+{ -+ if (nd) { -+ *h_nd = *nd; -+ -+ /* -+ * gave up supporting LOOKUP_CREATE/OPEN for lower fs, -+ * due to whiteout and branch permission. -+ */ -+ h_nd->flags &= ~(/*LOOKUP_PARENT |*/ LOOKUP_OPEN | LOOKUP_CREATE -+ | LOOKUP_FOLLOW | LOOKUP_EXCL); -+ /* unnecessary? */ -+ h_nd->intent.open.file = NULL; -+ } else -+ memset(h_nd, 0, sizeof(*h_nd)); -+} -+ -+struct au_lkup_one_args { -+ struct dentry **errp; -+ struct qstr *name; -+ struct dentry *h_parent; -+ struct au_branch *br; -+ struct nameidata *nd; -+}; -+ -+struct dentry *au_lkup_one(struct qstr *name, struct dentry *h_parent, -+ struct au_branch *br, struct nameidata *nd) -+{ -+ struct dentry *h_dentry; -+ int err; -+ struct nameidata h_nd; -+ -+ if (au_test_fs_null_nd(h_parent->d_sb)) -+ return vfsub_lookup_one_len(name->name, h_parent, name->len); -+ -+ au_h_nd(&h_nd, nd); -+ h_nd.path.dentry = h_parent; -+ h_nd.path.mnt = br->br_mnt; -+ -+ err = __lookup_one_len(name->name, &h_nd.last, NULL, name->len); -+ h_dentry = ERR_PTR(err); -+ if (!err) { -+ path_get(&h_nd.path); -+ h_dentry = vfsub_lookup_hash(&h_nd); -+ path_put(&h_nd.path); -+ } -+ -+ AuTraceErrPtr(h_dentry); -+ return h_dentry; -+} -+ -+static void au_call_lkup_one(void *args) -+{ -+ struct au_lkup_one_args *a = args; -+ *a->errp = au_lkup_one(a->name, a->h_parent, a->br, a->nd); -+} -+ -+#define AuLkup_ALLOW_NEG 1 -+#define au_ftest_lkup(flags, name) ((flags) & AuLkup_##name) -+#define au_fset_lkup(flags, name) \ -+ do { (flags) |= AuLkup_##name; } while (0) -+#define au_fclr_lkup(flags, name) \ -+ do { (flags) &= ~AuLkup_##name; } while (0) -+ -+struct au_do_lookup_args { -+ unsigned int flags; -+ mode_t type; -+ struct nameidata *nd; -+}; -+ -+/* -+ * returns positive/negative dentry, NULL or an error. -+ * NULL means whiteout-ed or not-found. -+ */ -+static struct dentry* -+au_do_lookup(struct dentry *h_parent, struct dentry *dentry, -+ aufs_bindex_t bindex, struct qstr *wh_name, -+ struct au_do_lookup_args *args) -+{ -+ struct dentry *h_dentry; -+ struct inode *h_inode, *inode; -+ struct au_branch *br; -+ int wh_found, opq; -+ unsigned char wh_able; -+ const unsigned char allow_neg = !!au_ftest_lkup(args->flags, ALLOW_NEG); -+ -+ wh_found = 0; -+ br = au_sbr(dentry->d_sb, bindex); -+ wh_able = !!au_br_whable(br->br_perm); -+ if (wh_able) -+ wh_found = au_wh_test(h_parent, wh_name, br, /*try_sio*/0); -+ h_dentry = ERR_PTR(wh_found); -+ if (!wh_found) -+ goto real_lookup; -+ if (unlikely(wh_found < 0)) -+ goto out; -+ -+ /* We found a whiteout */ -+ /* au_set_dbend(dentry, bindex); */ -+ au_set_dbwh(dentry, bindex); -+ if (!allow_neg) -+ return NULL; /* success */ -+ -+real_lookup: -+ h_dentry = au_lkup_one(&dentry->d_name, h_parent, br, args->nd); -+ if (IS_ERR(h_dentry)) -+ goto out; -+ -+ h_inode = h_dentry->d_inode; -+ if (!h_inode) { -+ if (!allow_neg) -+ goto out_neg; -+ } else if (wh_found -+ || (args->type && args->type != (h_inode->i_mode & S_IFMT))) -+ goto out_neg; -+ -+ if (au_dbend(dentry) <= bindex) -+ au_set_dbend(dentry, bindex); -+ if (au_dbstart(dentry) < 0 || bindex < au_dbstart(dentry)) -+ au_set_dbstart(dentry, bindex); -+ au_set_h_dptr(dentry, bindex, h_dentry); -+ -+ inode = dentry->d_inode; -+ if (!h_inode || !S_ISDIR(h_inode->i_mode) || !wh_able -+ || (inode && !S_ISDIR(inode->i_mode))) -+ goto out; /* success */ -+ -+ mutex_lock_nested(&h_inode->i_mutex, AuLsc_I_CHILD); -+ opq = au_diropq_test(h_dentry, br); -+ mutex_unlock(&h_inode->i_mutex); -+ if (opq > 0) -+ au_set_dbdiropq(dentry, bindex); -+ else if (unlikely(opq < 0)) { -+ au_set_h_dptr(dentry, bindex, NULL); -+ h_dentry = ERR_PTR(opq); -+ } -+ goto out; -+ -+out_neg: -+ dput(h_dentry); -+ h_dentry = NULL; -+out: -+ return h_dentry; -+} -+ -+static int au_test_shwh(struct super_block *sb, const struct qstr *name) -+{ -+ if (unlikely(!au_opt_test(au_mntflags(sb), SHWH) -+ && !strncmp(name->name, AUFS_WH_PFX, AUFS_WH_PFX_LEN))) -+ return -EPERM; -+ return 0; -+} -+ -+/* -+ * returns the number of lower positive dentries, -+ * otherwise an error. -+ * can be called at unlinking with @type is zero. -+ */ -+int au_lkup_dentry(struct dentry *dentry, aufs_bindex_t bstart, mode_t type, -+ struct nameidata *nd) -+{ -+ int npositive, err; -+ aufs_bindex_t bindex, btail, bdiropq; -+ unsigned char isdir; -+ struct qstr whname; -+ struct au_do_lookup_args args = { -+ .flags = 0, -+ .type = type, -+ .nd = nd -+ }; -+ const struct qstr *name = &dentry->d_name; -+ struct dentry *parent; -+ struct inode *inode; -+ -+ err = au_test_shwh(dentry->d_sb, name); -+ if (unlikely(err)) -+ goto out; -+ -+ err = au_wh_name_alloc(&whname, name); -+ if (unlikely(err)) -+ goto out; -+ -+ inode = dentry->d_inode; -+ isdir = !!(inode && S_ISDIR(inode->i_mode)); -+ if (!type) -+ au_fset_lkup(args.flags, ALLOW_NEG); -+ -+ npositive = 0; -+ parent = dget_parent(dentry); -+ btail = au_dbtaildir(parent); -+ for (bindex = bstart; bindex <= btail; bindex++) { -+ struct dentry *h_parent, *h_dentry; -+ struct inode *h_inode, *h_dir; -+ -+ h_dentry = au_h_dptr(dentry, bindex); -+ if (h_dentry) { -+ if (h_dentry->d_inode) -+ npositive++; -+ if (type != S_IFDIR) -+ break; -+ continue; -+ } -+ h_parent = au_h_dptr(parent, bindex); -+ if (!h_parent) -+ continue; -+ h_dir = h_parent->d_inode; -+ if (!h_dir || !S_ISDIR(h_dir->i_mode)) -+ continue; -+ -+ mutex_lock_nested(&h_dir->i_mutex, AuLsc_I_PARENT); -+ h_dentry = au_do_lookup(h_parent, dentry, bindex, &whname, -+ &args); -+ mutex_unlock(&h_dir->i_mutex); -+ err = PTR_ERR(h_dentry); -+ if (IS_ERR(h_dentry)) -+ goto out_parent; -+ au_fclr_lkup(args.flags, ALLOW_NEG); -+ -+ if (au_dbwh(dentry) >= 0) -+ break; -+ if (!h_dentry) -+ continue; -+ h_inode = h_dentry->d_inode; -+ if (!h_inode) -+ continue; -+ npositive++; -+ if (!args.type) -+ args.type = h_inode->i_mode & S_IFMT; -+ if (args.type != S_IFDIR) -+ break; -+ else if (isdir) { -+ /* the type of lower may be different */ -+ bdiropq = au_dbdiropq(dentry); -+ if (bdiropq >= 0 && bdiropq <= bindex) -+ break; -+ } -+ } -+ -+ if (npositive) { -+ AuLabel(positive); -+ au_update_dbstart(dentry); -+ } -+ err = npositive; -+ if (unlikely(!au_opt_test(au_mntflags(dentry->d_sb), UDBA_NONE) -+ && au_dbstart(dentry) < 0)) { -+ err = -EIO; -+ AuIOErr("both of real entry and whiteout found, %.*s, err %d\n", -+ AuDLNPair(dentry), err); -+ } -+ -+out_parent: -+ dput(parent); -+ kfree(whname.name); -+out: -+ return err; -+} -+ -+struct dentry *au_sio_lkup_one(struct qstr *name, struct dentry *parent, -+ struct au_branch *br) -+{ -+ struct dentry *dentry; -+ int wkq_err; -+ -+ if (!au_test_h_perm_sio(parent->d_inode, MAY_EXEC)) -+ dentry = au_lkup_one(name, parent, br, /*nd*/NULL); -+ else { -+ struct au_lkup_one_args args = { -+ .errp = &dentry, -+ .name = name, -+ .h_parent = parent, -+ .br = br, -+ .nd = NULL -+ }; -+ -+ wkq_err = au_wkq_wait(au_call_lkup_one, &args); -+ if (unlikely(wkq_err)) -+ dentry = ERR_PTR(wkq_err); -+ } -+ -+ return dentry; -+} -+ -+/* -+ * lookup @dentry on @bindex which should be negative. -+ */ -+int au_lkup_neg(struct dentry *dentry, aufs_bindex_t bindex) -+{ -+ int err; -+ struct dentry *parent, *h_parent, *h_dentry; -+ -+ parent = dget_parent(dentry); -+ h_parent = au_h_dptr(parent, bindex); -+ h_dentry = au_sio_lkup_one(&dentry->d_name, h_parent, -+ au_sbr(dentry->d_sb, bindex)); -+ err = PTR_ERR(h_dentry); -+ if (IS_ERR(h_dentry)) -+ goto out; -+ if (unlikely(h_dentry->d_inode)) { -+ err = -EIO; -+ AuIOErr("%.*s should be negative on b%d.\n", -+ AuDLNPair(h_dentry), bindex); -+ dput(h_dentry); -+ goto out; -+ } -+ -+ err = 0; -+ if (bindex < au_dbstart(dentry)) -+ au_set_dbstart(dentry, bindex); -+ if (au_dbend(dentry) < bindex) -+ au_set_dbend(dentry, bindex); -+ au_set_h_dptr(dentry, bindex, h_dentry); -+ -+out: -+ dput(parent); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* subset of struct inode */ -+struct au_iattr { -+ unsigned long i_ino; -+ /* unsigned int i_nlink; */ -+ uid_t i_uid; -+ gid_t i_gid; -+ u64 i_version; -+/* -+ loff_t i_size; -+ blkcnt_t i_blocks; -+*/ -+ umode_t i_mode; -+}; -+ -+static void au_iattr_save(struct au_iattr *ia, struct inode *h_inode) -+{ -+ ia->i_ino = h_inode->i_ino; -+ /* ia->i_nlink = h_inode->i_nlink; */ -+ ia->i_uid = h_inode->i_uid; -+ ia->i_gid = h_inode->i_gid; -+ ia->i_version = h_inode->i_version; -+/* -+ ia->i_size = h_inode->i_size; -+ ia->i_blocks = h_inode->i_blocks; -+*/ -+ ia->i_mode = (h_inode->i_mode & S_IFMT); -+} -+ -+static int au_iattr_test(struct au_iattr *ia, struct inode *h_inode) -+{ -+ return ia->i_ino != h_inode->i_ino -+ /* || ia->i_nlink != h_inode->i_nlink */ -+ || ia->i_uid != h_inode->i_uid -+ || ia->i_gid != h_inode->i_gid -+ || ia->i_version != h_inode->i_version -+/* -+ || ia->i_size != h_inode->i_size -+ || ia->i_blocks != h_inode->i_blocks -+*/ -+ || ia->i_mode != (h_inode->i_mode & S_IFMT); -+} -+ -+static int au_h_verify_dentry(struct dentry *h_dentry, struct dentry *h_parent, -+ struct au_branch *br) -+{ -+ int err; -+ struct au_iattr ia; -+ struct inode *h_inode; -+ struct dentry *h_d; -+ struct super_block *h_sb; -+ -+ err = 0; -+ memset(&ia, -1, sizeof(ia)); -+ h_sb = h_dentry->d_sb; -+ h_inode = h_dentry->d_inode; -+ if (h_inode) -+ au_iattr_save(&ia, h_inode); -+ else if (au_test_nfs(h_sb) || au_test_fuse(h_sb)) -+ /* nfs d_revalidate may return 0 for negative dentry */ -+ /* fuse d_revalidate always return 0 for negative dentry */ -+ goto out; -+ -+ /* main purpose is namei.c:cached_lookup() and d_revalidate */ -+ h_d = au_lkup_one(&h_dentry->d_name, h_parent, br, /*nd*/NULL); -+ err = PTR_ERR(h_d); -+ if (IS_ERR(h_d)) -+ goto out; -+ -+ err = 0; -+ if (unlikely(h_d != h_dentry -+ || h_d->d_inode != h_inode -+ || (h_inode && au_iattr_test(&ia, h_inode)))) -+ err = au_busy_or_stale(); -+ dput(h_d); -+ -+out: -+ AuTraceErr(err); -+ return err; -+} -+ -+int au_h_verify(struct dentry *h_dentry, unsigned int udba, struct inode *h_dir, -+ struct dentry *h_parent, struct au_branch *br) -+{ -+ int err; -+ -+ err = 0; -+ if (udba == AuOpt_UDBA_REVAL) { -+ IMustLock(h_dir); -+ err = (h_dentry->d_parent->d_inode != h_dir); -+ } else if (udba == AuOpt_UDBA_HNOTIFY) -+ err = au_h_verify_dentry(h_dentry, h_parent, br); -+ -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int au_do_refresh_hdentry(struct dentry *dentry, struct dentry *parent) -+{ -+ int err; -+ aufs_bindex_t new_bindex, bindex, bend, bwh, bdiropq; -+ struct au_hdentry tmp, *p, *q; -+ struct au_dinfo *dinfo; -+ struct super_block *sb; -+ -+ DiMustWriteLock(dentry); -+ -+ sb = dentry->d_sb; -+ dinfo = au_di(dentry); -+ bend = dinfo->di_bend; -+ bwh = dinfo->di_bwh; -+ bdiropq = dinfo->di_bdiropq; -+ p = dinfo->di_hdentry + dinfo->di_bstart; -+ for (bindex = dinfo->di_bstart; bindex <= bend; bindex++, p++) { -+ if (!p->hd_dentry) -+ continue; -+ -+ new_bindex = au_br_index(sb, p->hd_id); -+ if (new_bindex == bindex) -+ continue; -+ -+ if (dinfo->di_bwh == bindex) -+ bwh = new_bindex; -+ if (dinfo->di_bdiropq == bindex) -+ bdiropq = new_bindex; -+ if (new_bindex < 0) { -+ au_hdput(p); -+ p->hd_dentry = NULL; -+ continue; -+ } -+ -+ /* swap two lower dentries, and loop again */ -+ q = dinfo->di_hdentry + new_bindex; -+ tmp = *q; -+ *q = *p; -+ *p = tmp; -+ if (tmp.hd_dentry) { -+ bindex--; -+ p--; -+ } -+ } -+ -+ dinfo->di_bwh = -1; -+ if (bwh >= 0 && bwh <= au_sbend(sb) && au_sbr_whable(sb, bwh)) -+ dinfo->di_bwh = bwh; -+ -+ dinfo->di_bdiropq = -1; -+ if (bdiropq >= 0 -+ && bdiropq <= au_sbend(sb) -+ && au_sbr_whable(sb, bdiropq)) -+ dinfo->di_bdiropq = bdiropq; -+ -+ err = -EIO; -+ dinfo->di_bstart = -1; -+ dinfo->di_bend = -1; -+ bend = au_dbend(parent); -+ p = dinfo->di_hdentry; -+ for (bindex = 0; bindex <= bend; bindex++, p++) -+ if (p->hd_dentry) { -+ dinfo->di_bstart = bindex; -+ break; -+ } -+ -+ if (dinfo->di_bstart >= 0) { -+ p = dinfo->di_hdentry + bend; -+ for (bindex = bend; bindex >= 0; bindex--, p--) -+ if (p->hd_dentry) { -+ dinfo->di_bend = bindex; -+ err = 0; -+ break; -+ } -+ } -+ -+ return err; -+} -+ -+static void au_do_hide(struct dentry *dentry) -+{ -+ struct inode *inode; -+ -+ inode = dentry->d_inode; -+ if (inode) { -+ if (!S_ISDIR(inode->i_mode)) { -+ if (inode->i_nlink && !d_unhashed(dentry)) -+ drop_nlink(inode); -+ } else { -+ clear_nlink(inode); -+ /* stop next lookup */ -+ inode->i_flags |= S_DEAD; -+ } -+ smp_mb(); /* necessary? */ -+ } -+ d_drop(dentry); -+} -+ -+static int au_hide_children(struct dentry *parent) -+{ -+ int err, i, j, ndentry; -+ struct au_dcsub_pages dpages; -+ struct au_dpage *dpage; -+ struct dentry *dentry; -+ -+ err = au_dpages_init(&dpages, GFP_NOFS); -+ if (unlikely(err)) -+ goto out; -+ err = au_dcsub_pages(&dpages, parent, NULL, NULL); -+ if (unlikely(err)) -+ goto out_dpages; -+ -+ /* in reverse order */ -+ for (i = dpages.ndpage - 1; i >= 0; i--) { -+ dpage = dpages.dpages + i; -+ ndentry = dpage->ndentry; -+ for (j = ndentry - 1; j >= 0; j--) { -+ dentry = dpage->dentries[j]; -+ if (dentry != parent) -+ au_do_hide(dentry); -+ } -+ } -+ -+out_dpages: -+ au_dpages_free(&dpages); -+out: -+ return err; -+} -+ -+static void au_hide(struct dentry *dentry) -+{ -+ int err; -+ struct inode *inode; -+ -+ AuDbgDentry(dentry); -+ inode = dentry->d_inode; -+ if (inode && S_ISDIR(inode->i_mode)) { -+ /* shrink_dcache_parent(dentry); */ -+ err = au_hide_children(dentry); -+ if (unlikely(err)) -+ AuIOErr("%.*s, failed hiding children, ignored %d\n", -+ AuDLNPair(dentry), err); -+ } -+ au_do_hide(dentry); -+} -+ -+/* -+ * By adding a dirty branch, a cached dentry may be affected in various ways. -+ * -+ * a dirty branch is added -+ * - on the top of layers -+ * - in the middle of layers -+ * - to the bottom of layers -+ * -+ * on the added branch there exists -+ * - a whiteout -+ * - a diropq -+ * - a same named entry -+ * + exist -+ * * negative --> positive -+ * * positive --> positive -+ * - type is unchanged -+ * - type is changed -+ * + doesn't exist -+ * * negative --> negative -+ * * positive --> negative (rejected by au_br_del() for non-dir case) -+ * - none -+ */ -+static int au_refresh_by_dinfo(struct dentry *dentry, struct au_dinfo *dinfo, -+ struct au_dinfo *tmp) -+{ -+ int err; -+ aufs_bindex_t bindex, bend; -+ struct { -+ struct dentry *dentry; -+ struct inode *inode; -+ mode_t mode; -+ } orig_h, tmp_h; -+ struct au_hdentry *hd; -+ struct inode *inode, *h_inode; -+ struct dentry *h_dentry; -+ -+ err = 0; -+ AuDebugOn(dinfo->di_bstart < 0); -+ orig_h.dentry = dinfo->di_hdentry[dinfo->di_bstart].hd_dentry; -+ orig_h.inode = orig_h.dentry->d_inode; -+ orig_h.mode = 0; -+ if (orig_h.inode) -+ orig_h.mode = orig_h.inode->i_mode & S_IFMT; -+ memset(&tmp_h, 0, sizeof(tmp_h)); -+ if (tmp->di_bstart >= 0) { -+ tmp_h.dentry = tmp->di_hdentry[tmp->di_bstart].hd_dentry; -+ tmp_h.inode = tmp_h.dentry->d_inode; -+ if (tmp_h.inode) -+ tmp_h.mode = tmp_h.inode->i_mode & S_IFMT; -+ } -+ -+ inode = dentry->d_inode; -+ if (!orig_h.inode) { -+ AuDbg("nagative originally\n"); -+ if (inode) { -+ au_hide(dentry); -+ goto out; -+ } -+ AuDebugOn(inode); -+ AuDebugOn(dinfo->di_bstart != dinfo->di_bend); -+ AuDebugOn(dinfo->di_bdiropq != -1); -+ -+ if (!tmp_h.inode) { -+ AuDbg("negative --> negative\n"); -+ /* should have only one negative lower */ -+ if (tmp->di_bstart >= 0 -+ && tmp->di_bstart < dinfo->di_bstart) { -+ AuDebugOn(tmp->di_bstart != tmp->di_bend); -+ AuDebugOn(dinfo->di_bstart != dinfo->di_bend); -+ au_set_h_dptr(dentry, dinfo->di_bstart, NULL); -+ au_di_cp(dinfo, tmp); -+ hd = tmp->di_hdentry + tmp->di_bstart; -+ au_set_h_dptr(dentry, tmp->di_bstart, -+ dget(hd->hd_dentry)); -+ } -+ au_dbg_verify_dinode(dentry); -+ } else { -+ AuDbg("negative --> positive\n"); -+ /* -+ * similar to the behaviour of creating with bypassing -+ * aufs. -+ * unhash it in order to force an error in the -+ * succeeding create operation. -+ * we should not set S_DEAD here. -+ */ -+ d_drop(dentry); -+ /* au_di_swap(tmp, dinfo); */ -+ au_dbg_verify_dinode(dentry); -+ } -+ } else { -+ AuDbg("positive originally\n"); -+ /* inode may be NULL */ -+ AuDebugOn(inode && (inode->i_mode & S_IFMT) != orig_h.mode); -+ if (!tmp_h.inode) { -+ AuDbg("positive --> negative\n"); -+ /* or bypassing aufs */ -+ au_hide(dentry); -+ if (tmp->di_bwh >= 0 && tmp->di_bwh <= dinfo->di_bstart) -+ dinfo->di_bwh = tmp->di_bwh; -+ if (inode) -+ err = au_refresh_hinode_self(inode); -+ au_dbg_verify_dinode(dentry); -+ } else if (orig_h.mode == tmp_h.mode) { -+ AuDbg("positive --> positive, same type\n"); -+ if (!S_ISDIR(orig_h.mode) -+ && dinfo->di_bstart > tmp->di_bstart) { -+ /* -+ * similar to the behaviour of removing and -+ * creating. -+ */ -+ au_hide(dentry); -+ if (inode) -+ err = au_refresh_hinode_self(inode); -+ au_dbg_verify_dinode(dentry); -+ } else { -+ /* fill empty slots */ -+ if (dinfo->di_bstart > tmp->di_bstart) -+ dinfo->di_bstart = tmp->di_bstart; -+ if (dinfo->di_bend < tmp->di_bend) -+ dinfo->di_bend = tmp->di_bend; -+ dinfo->di_bwh = tmp->di_bwh; -+ dinfo->di_bdiropq = tmp->di_bdiropq; -+ hd = tmp->di_hdentry; -+ bend = dinfo->di_bend; -+ for (bindex = tmp->di_bstart; bindex <= bend; -+ bindex++) { -+ if (au_h_dptr(dentry, bindex)) -+ continue; -+ h_dentry = hd[bindex].hd_dentry; -+ if (!h_dentry) -+ continue; -+ h_inode = h_dentry->d_inode; -+ AuDebugOn(!h_inode); -+ AuDebugOn(orig_h.mode -+ != (h_inode->i_mode -+ & S_IFMT)); -+ au_set_h_dptr(dentry, bindex, -+ dget(h_dentry)); -+ } -+ err = au_refresh_hinode(inode, dentry); -+ au_dbg_verify_dinode(dentry); -+ } -+ } else { -+ AuDbg("positive --> positive, different type\n"); -+ /* similar to the behaviour of removing and creating */ -+ au_hide(dentry); -+ if (inode) -+ err = au_refresh_hinode_self(inode); -+ au_dbg_verify_dinode(dentry); -+ } -+ } -+ -+out: -+ return err; -+} -+ -+int au_refresh_dentry(struct dentry *dentry, struct dentry *parent) -+{ -+ int err, ebrange; -+ unsigned int sigen; -+ struct au_dinfo *dinfo, *tmp; -+ struct super_block *sb; -+ struct inode *inode; -+ -+ DiMustWriteLock(dentry); -+ AuDebugOn(IS_ROOT(dentry)); -+ AuDebugOn(!parent->d_inode); -+ -+ sb = dentry->d_sb; -+ inode = dentry->d_inode; -+ sigen = au_sigen(sb); -+ err = au_digen_test(parent, sigen); -+ if (unlikely(err)) -+ goto out; -+ -+ dinfo = au_di(dentry); -+ err = au_di_realloc(dinfo, au_sbend(sb) + 1); -+ if (unlikely(err)) -+ goto out; -+ ebrange = au_dbrange_test(dentry); -+ if (!ebrange) -+ ebrange = au_do_refresh_hdentry(dentry, parent); -+ -+ if (d_unhashed(dentry) || ebrange) { -+ AuDebugOn(au_dbstart(dentry) < 0 && au_dbend(dentry) >= 0); -+ if (inode) -+ err = au_refresh_hinode_self(inode); -+ au_dbg_verify_dinode(dentry); -+ if (!err) -+ goto out_dgen; /* success */ -+ goto out; -+ } -+ -+ /* temporary dinfo */ -+ AuDbgDentry(dentry); -+ err = -ENOMEM; -+ tmp = au_di_alloc(sb, AuLsc_DI_TMP); -+ if (unlikely(!tmp)) -+ goto out; -+ au_di_swap(tmp, dinfo); -+ /* returns the number of positive dentries */ -+ /* -+ * if current working dir is removed, it returns an error. -+ * but the dentry is legal. -+ */ -+ err = au_lkup_dentry(dentry, /*bstart*/0, /*type*/0, /*nd*/NULL); -+ AuDbgDentry(dentry); -+ au_di_swap(tmp, dinfo); -+ if (err == -ENOENT) -+ err = 0; -+ if (err >= 0) { -+ /* compare/refresh by dinfo */ -+ AuDbgDentry(dentry); -+ err = au_refresh_by_dinfo(dentry, dinfo, tmp); -+ au_dbg_verify_dinode(dentry); -+ AuTraceErr(err); -+ } -+ au_rw_write_unlock(&tmp->di_rwsem); -+ au_di_free(tmp); -+ if (unlikely(err)) -+ goto out; -+ -+out_dgen: -+ au_update_digen(dentry); -+out: -+ if (unlikely(err && !(dentry->d_flags & DCACHE_NFSFS_RENAMED))) { -+ AuIOErr("failed refreshing %.*s, %d\n", -+ AuDLNPair(dentry), err); -+ AuDbgDentry(dentry); -+ } -+ AuTraceErr(err); -+ return err; -+} -+ -+static noinline_for_stack -+int au_do_h_d_reval(struct dentry *h_dentry, struct nameidata *nd, -+ struct dentry *dentry, aufs_bindex_t bindex) -+{ -+ int err, valid; -+ int (*reval)(struct dentry *, struct nameidata *); -+ -+ err = 0; -+ reval = NULL; -+ if (h_dentry->d_op) -+ reval = h_dentry->d_op->d_revalidate; -+ if (!reval) -+ goto out; -+ -+ AuDbg("b%d\n", bindex); -+ if (au_test_fs_null_nd(h_dentry->d_sb)) -+ /* it may return tri-state */ -+ valid = reval(h_dentry, NULL); -+ else { -+ struct nameidata h_nd; -+ int locked; -+ struct dentry *parent; -+ -+ au_h_nd(&h_nd, nd); -+ parent = nd->path.dentry; -+ locked = (nd && nd->path.dentry != dentry); -+ if (locked) -+ di_read_lock_parent(parent, AuLock_IR); -+ BUG_ON(bindex > au_dbend(parent)); -+ h_nd.path.dentry = au_h_dptr(parent, bindex); -+ BUG_ON(!h_nd.path.dentry); -+ h_nd.path.mnt = au_sbr(parent->d_sb, bindex)->br_mnt; -+ path_get(&h_nd.path); -+ valid = reval(h_dentry, &h_nd); -+ path_put(&h_nd.path); -+ if (locked) -+ di_read_unlock(parent, AuLock_IR); -+ } -+ -+ if (unlikely(valid < 0)) -+ err = valid; -+ else if (!valid) -+ err = -EINVAL; -+ -+out: -+ AuTraceErr(err); -+ return err; -+} -+ -+/* todo: remove this */ -+static int h_d_revalidate(struct dentry *dentry, struct inode *inode, -+ struct nameidata *nd, int do_udba) -+{ -+ int err; -+ umode_t mode, h_mode; -+ aufs_bindex_t bindex, btail, bstart, ibs, ibe; -+ unsigned char plus, unhashed, is_root, h_plus; -+ struct inode *h_inode, *h_cached_inode; -+ struct dentry *h_dentry; -+ struct qstr *name, *h_name; -+ -+ err = 0; -+ plus = 0; -+ mode = 0; -+ ibs = -1; -+ ibe = -1; -+ unhashed = !!d_unhashed(dentry); -+ is_root = !!IS_ROOT(dentry); -+ name = &dentry->d_name; -+ -+ /* -+ * Theoretically, REVAL test should be unnecessary in case of -+ * {FS,I}NOTIFY. -+ * But {fs,i}notify doesn't fire some necessary events, -+ * IN_ATTRIB for atime/nlink/pageio -+ * IN_DELETE for NFS dentry -+ * Let's do REVAL test too. -+ */ -+ if (do_udba && inode) { -+ mode = (inode->i_mode & S_IFMT); -+ plus = (inode->i_nlink > 0); -+ ibs = au_ibstart(inode); -+ ibe = au_ibend(inode); -+ } -+ -+ bstart = au_dbstart(dentry); -+ btail = bstart; -+ if (inode && S_ISDIR(inode->i_mode)) -+ btail = au_dbtaildir(dentry); -+ for (bindex = bstart; bindex <= btail; bindex++) { -+ h_dentry = au_h_dptr(dentry, bindex); -+ if (!h_dentry) -+ continue; -+ -+ AuDbg("b%d, %.*s\n", bindex, AuDLNPair(h_dentry)); -+ h_name = &h_dentry->d_name; -+ if (unlikely(do_udba -+ && !is_root -+ && (unhashed != !!d_unhashed(h_dentry) -+ || name->len != h_name->len -+ || memcmp(name->name, h_name->name, name->len)) -+ )) { -+ AuDbg("unhash 0x%x 0x%x, %.*s %.*s\n", -+ unhashed, d_unhashed(h_dentry), -+ AuDLNPair(dentry), AuDLNPair(h_dentry)); -+ goto err; -+ } -+ -+ err = au_do_h_d_reval(h_dentry, nd, dentry, bindex); -+ if (unlikely(err)) -+ /* do not goto err, to keep the errno */ -+ break; -+ -+ /* todo: plink too? */ -+ if (!do_udba) -+ continue; -+ -+ /* UDBA tests */ -+ h_inode = h_dentry->d_inode; -+ if (unlikely(!!inode != !!h_inode)) -+ goto err; -+ -+ h_plus = plus; -+ h_mode = mode; -+ h_cached_inode = h_inode; -+ if (h_inode) { -+ h_mode = (h_inode->i_mode & S_IFMT); -+ h_plus = (h_inode->i_nlink > 0); -+ } -+ if (inode && ibs <= bindex && bindex <= ibe) -+ h_cached_inode = au_h_iptr(inode, bindex); -+ -+ if (unlikely(plus != h_plus -+ || mode != h_mode -+ || h_cached_inode != h_inode)) -+ goto err; -+ continue; -+ -+ err: -+ err = -EINVAL; -+ break; -+ } -+ -+ return err; -+} -+ -+/* todo: consolidate with do_refresh() and au_reval_for_attr() */ -+static int simple_reval_dpath(struct dentry *dentry, unsigned int sigen) -+{ -+ int err; -+ struct dentry *parent; -+ -+ if (!au_digen_test(dentry, sigen)) -+ return 0; -+ -+ parent = dget_parent(dentry); -+ di_read_lock_parent(parent, AuLock_IR); -+ AuDebugOn(au_digen_test(parent, sigen)); -+ au_dbg_verify_gen(parent, sigen); -+ err = au_refresh_dentry(dentry, parent); -+ di_read_unlock(parent, AuLock_IR); -+ dput(parent); -+ AuTraceErr(err); -+ return err; -+} -+ -+int au_reval_dpath(struct dentry *dentry, unsigned int sigen) -+{ -+ int err; -+ struct dentry *d, *parent; -+ struct inode *inode; -+ -+ if (!au_ftest_si(au_sbi(dentry->d_sb), FAILED_REFRESH_DIR)) -+ return simple_reval_dpath(dentry, sigen); -+ -+ /* slow loop, keep it simple and stupid */ -+ /* cf: au_cpup_dirs() */ -+ err = 0; -+ parent = NULL; -+ while (au_digen_test(dentry, sigen)) { -+ d = dentry; -+ while (1) { -+ dput(parent); -+ parent = dget_parent(d); -+ if (!au_digen_test(parent, sigen)) -+ break; -+ d = parent; -+ } -+ -+ inode = d->d_inode; -+ if (d != dentry) -+ di_write_lock_child2(d); -+ -+ /* someone might update our dentry while we were sleeping */ -+ if (au_digen_test(d, sigen)) { -+ /* -+ * todo: consolidate with simple_reval_dpath(), -+ * do_refresh() and au_reval_for_attr(). -+ */ -+ di_read_lock_parent(parent, AuLock_IR); -+ err = au_refresh_dentry(d, parent); -+ di_read_unlock(parent, AuLock_IR); -+ } -+ -+ if (d != dentry) -+ di_write_unlock(d); -+ dput(parent); -+ if (unlikely(err)) -+ break; -+ } -+ -+ return err; -+} -+ -+/* -+ * if valid returns 1, otherwise 0. -+ */ -+static int aufs_d_revalidate(struct dentry *dentry, struct nameidata *nd) -+{ -+ int valid, err; -+ unsigned int sigen; -+ unsigned char do_udba; -+ struct super_block *sb; -+ struct inode *inode; -+ -+ valid = 0; -+ if (unlikely(!au_di(dentry))) -+ goto out; -+ -+ valid = 1; -+ sb = dentry->d_sb; -+ inode = dentry->d_inode; -+ /* -+ * todo: very ugly -+ * i_mutex of parent dir may be held, -+ * but we should not return 'invalid' due to busy. -+ */ -+ err = aufs_read_lock(dentry, AuLock_FLUSH | AuLock_DW | AuLock_NOPLM); -+ if (unlikely(err)) { -+ valid = err; -+ AuTraceErr(err); -+ goto out; -+ } -+ if (unlikely(au_dbrange_test(dentry))) { -+ err = -EINVAL; -+ AuTraceErr(err); -+ goto out_dgrade; -+ } -+ -+ sigen = au_sigen(sb); -+ if (au_digen_test(dentry, sigen)) { -+ AuDebugOn(IS_ROOT(dentry)); -+ err = au_reval_dpath(dentry, sigen); -+ if (unlikely(err)) { -+ AuTraceErr(err); -+ goto out_dgrade; -+ } -+ } -+ di_downgrade_lock(dentry, AuLock_IR); -+ -+ err = -EINVAL; -+ if (inode && (IS_DEADDIR(inode) || !inode->i_nlink)) -+ goto out_inval; -+ -+ do_udba = !au_opt_test(au_mntflags(sb), UDBA_NONE); -+ if (do_udba && inode) { -+ aufs_bindex_t bstart = au_ibstart(inode); -+ struct inode *h_inode; -+ -+ if (bstart >= 0) { -+ h_inode = au_h_iptr(inode, bstart); -+ if (h_inode && au_test_higen(inode, h_inode)) -+ goto out_inval; -+ } -+ } -+ -+ err = h_d_revalidate(dentry, inode, nd, do_udba); -+ if (unlikely(!err && do_udba && au_dbstart(dentry) < 0)) { -+ err = -EIO; -+ AuDbg("both of real entry and whiteout found, %.*s, err %d\n", -+ AuDLNPair(dentry), err); -+ } -+ goto out_inval; -+ -+out_dgrade: -+ di_downgrade_lock(dentry, AuLock_IR); -+out_inval: -+ aufs_read_unlock(dentry, AuLock_IR); -+ AuTraceErr(err); -+ valid = !err; -+out: -+ if (!valid) { -+ AuDbg("%.*s invalid, %d\n", AuDLNPair(dentry), valid); -+ d_drop(dentry); -+ } -+ return valid; -+} -+ -+static void aufs_d_release(struct dentry *dentry) -+{ -+ if (au_di(dentry)) { -+ au_di_fin(dentry); -+ au_hn_di_reinit(dentry); -+ } -+} -+ -+const struct dentry_operations aufs_dop = { -+ .d_revalidate = aufs_d_revalidate, -+ .d_release = aufs_d_release -+}; -diff -Nur linux-2.6.37.orig/fs/aufs/dentry.h linux-2.6.37/fs/aufs/dentry.h ---- linux-2.6.37.orig/fs/aufs/dentry.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/dentry.h 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,237 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * lookup and dentry operations -+ */ -+ -+#ifndef __AUFS_DENTRY_H__ -+#define __AUFS_DENTRY_H__ -+ -+#ifdef __KERNEL__ -+ -+#include -+#include -+#include "rwsem.h" -+ -+struct au_hdentry { -+ struct dentry *hd_dentry; -+ aufs_bindex_t hd_id; -+}; -+ -+struct au_dinfo { -+ atomic_t di_generation; -+ -+ struct au_rwsem di_rwsem; -+ aufs_bindex_t di_bstart, di_bend, di_bwh, di_bdiropq; -+ struct au_hdentry *di_hdentry; -+} ____cacheline_aligned_in_smp; -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* dentry.c */ -+extern const struct dentry_operations aufs_dop; -+struct au_branch; -+struct dentry *au_lkup_one(struct qstr *name, struct dentry *h_parent, -+ struct au_branch *br, struct nameidata *nd); -+struct dentry *au_sio_lkup_one(struct qstr *name, struct dentry *parent, -+ struct au_branch *br); -+int au_h_verify(struct dentry *h_dentry, unsigned int udba, struct inode *h_dir, -+ struct dentry *h_parent, struct au_branch *br); -+ -+int au_lkup_dentry(struct dentry *dentry, aufs_bindex_t bstart, mode_t type, -+ struct nameidata *nd); -+int au_lkup_neg(struct dentry *dentry, aufs_bindex_t bindex); -+int au_refresh_dentry(struct dentry *dentry, struct dentry *parent); -+int au_reval_dpath(struct dentry *dentry, unsigned int sigen); -+ -+/* dinfo.c */ -+void au_di_init_once(void *_di); -+struct au_dinfo *au_di_alloc(struct super_block *sb, unsigned int lsc); -+void au_di_free(struct au_dinfo *dinfo); -+void au_di_swap(struct au_dinfo *a, struct au_dinfo *b); -+void au_di_cp(struct au_dinfo *dst, struct au_dinfo *src); -+int au_di_init(struct dentry *dentry); -+void au_di_fin(struct dentry *dentry); -+int au_di_realloc(struct au_dinfo *dinfo, int nbr); -+ -+void di_read_lock(struct dentry *d, int flags, unsigned int lsc); -+void di_read_unlock(struct dentry *d, int flags); -+void di_downgrade_lock(struct dentry *d, int flags); -+void di_write_lock(struct dentry *d, unsigned int lsc); -+void di_write_unlock(struct dentry *d); -+void di_write_lock2_child(struct dentry *d1, struct dentry *d2, int isdir); -+void di_write_lock2_parent(struct dentry *d1, struct dentry *d2, int isdir); -+void di_write_unlock2(struct dentry *d1, struct dentry *d2); -+ -+struct dentry *au_h_dptr(struct dentry *dentry, aufs_bindex_t bindex); -+aufs_bindex_t au_dbtail(struct dentry *dentry); -+aufs_bindex_t au_dbtaildir(struct dentry *dentry); -+ -+void au_set_h_dptr(struct dentry *dentry, aufs_bindex_t bindex, -+ struct dentry *h_dentry); -+int au_digen_test(struct dentry *dentry, unsigned int sigen); -+int au_dbrange_test(struct dentry *dentry); -+void au_update_digen(struct dentry *dentry); -+void au_update_dbrange(struct dentry *dentry, int do_put_zero); -+void au_update_dbstart(struct dentry *dentry); -+void au_update_dbend(struct dentry *dentry); -+int au_find_dbindex(struct dentry *dentry, struct dentry *h_dentry); -+ -+/* ---------------------------------------------------------------------- */ -+ -+static inline struct au_dinfo *au_di(struct dentry *dentry) -+{ -+ return dentry->d_fsdata; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* lock subclass for dinfo */ -+enum { -+ AuLsc_DI_CHILD, /* child first */ -+ AuLsc_DI_CHILD2, /* rename(2), link(2), and cpup at hnotify */ -+ AuLsc_DI_CHILD3, /* copyup dirs */ -+ AuLsc_DI_PARENT, -+ AuLsc_DI_PARENT2, -+ AuLsc_DI_PARENT3, -+ AuLsc_DI_TMP /* temp for replacing dinfo */ -+}; -+ -+/* -+ * di_read_lock_child, di_write_lock_child, -+ * di_read_lock_child2, di_write_lock_child2, -+ * di_read_lock_child3, di_write_lock_child3, -+ * di_read_lock_parent, di_write_lock_parent, -+ * di_read_lock_parent2, di_write_lock_parent2, -+ * di_read_lock_parent3, di_write_lock_parent3, -+ */ -+#define AuReadLockFunc(name, lsc) \ -+static inline void di_read_lock_##name(struct dentry *d, int flags) \ -+{ di_read_lock(d, flags, AuLsc_DI_##lsc); } -+ -+#define AuWriteLockFunc(name, lsc) \ -+static inline void di_write_lock_##name(struct dentry *d) \ -+{ di_write_lock(d, AuLsc_DI_##lsc); } -+ -+#define AuRWLockFuncs(name, lsc) \ -+ AuReadLockFunc(name, lsc) \ -+ AuWriteLockFunc(name, lsc) -+ -+AuRWLockFuncs(child, CHILD); -+AuRWLockFuncs(child2, CHILD2); -+AuRWLockFuncs(child3, CHILD3); -+AuRWLockFuncs(parent, PARENT); -+AuRWLockFuncs(parent2, PARENT2); -+AuRWLockFuncs(parent3, PARENT3); -+ -+#undef AuReadLockFunc -+#undef AuWriteLockFunc -+#undef AuRWLockFuncs -+ -+#define DiMustNoWaiters(d) AuRwMustNoWaiters(&au_di(d)->di_rwsem) -+#define DiMustAnyLock(d) AuRwMustAnyLock(&au_di(d)->di_rwsem) -+#define DiMustWriteLock(d) AuRwMustWriteLock(&au_di(d)->di_rwsem) -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* todo: memory barrier? */ -+static inline unsigned int au_digen(struct dentry *d) -+{ -+ return atomic_read(&au_di(d)->di_generation); -+} -+ -+static inline void au_h_dentry_init(struct au_hdentry *hdentry) -+{ -+ hdentry->hd_dentry = NULL; -+} -+ -+static inline void au_hdput(struct au_hdentry *hd) -+{ -+ if (hd) -+ dput(hd->hd_dentry); -+} -+ -+static inline aufs_bindex_t au_dbstart(struct dentry *dentry) -+{ -+ DiMustAnyLock(dentry); -+ return au_di(dentry)->di_bstart; -+} -+ -+static inline aufs_bindex_t au_dbend(struct dentry *dentry) -+{ -+ DiMustAnyLock(dentry); -+ return au_di(dentry)->di_bend; -+} -+ -+static inline aufs_bindex_t au_dbwh(struct dentry *dentry) -+{ -+ DiMustAnyLock(dentry); -+ return au_di(dentry)->di_bwh; -+} -+ -+static inline aufs_bindex_t au_dbdiropq(struct dentry *dentry) -+{ -+ DiMustAnyLock(dentry); -+ return au_di(dentry)->di_bdiropq; -+} -+ -+/* todo: hard/soft set? */ -+static inline void au_set_dbstart(struct dentry *dentry, aufs_bindex_t bindex) -+{ -+ DiMustWriteLock(dentry); -+ au_di(dentry)->di_bstart = bindex; -+} -+ -+static inline void au_set_dbend(struct dentry *dentry, aufs_bindex_t bindex) -+{ -+ DiMustWriteLock(dentry); -+ au_di(dentry)->di_bend = bindex; -+} -+ -+static inline void au_set_dbwh(struct dentry *dentry, aufs_bindex_t bindex) -+{ -+ DiMustWriteLock(dentry); -+ /* dbwh can be outside of bstart - bend range */ -+ au_di(dentry)->di_bwh = bindex; -+} -+ -+static inline void au_set_dbdiropq(struct dentry *dentry, aufs_bindex_t bindex) -+{ -+ DiMustWriteLock(dentry); -+ au_di(dentry)->di_bdiropq = bindex; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+#ifdef CONFIG_AUFS_HNOTIFY -+static inline void au_digen_dec(struct dentry *d) -+{ -+ atomic_dec(&au_di(d)->di_generation); -+} -+ -+static inline void au_hn_di_reinit(struct dentry *dentry) -+{ -+ dentry->d_fsdata = NULL; -+} -+#else -+AuStubVoid(au_hn_di_reinit, struct dentry *dentry __maybe_unused) -+#endif /* CONFIG_AUFS_HNOTIFY */ -+ -+#endif /* __KERNEL__ */ -+#endif /* __AUFS_DENTRY_H__ */ -diff -Nur linux-2.6.37.orig/fs/aufs/dinfo.c linux-2.6.37/fs/aufs/dinfo.c ---- linux-2.6.37.orig/fs/aufs/dinfo.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/dinfo.c 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,494 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * dentry private data -+ */ -+ -+#include "aufs.h" -+ -+void au_di_init_once(void *_dinfo) -+{ -+ struct au_dinfo *dinfo = _dinfo; -+ static struct lock_class_key aufs_di; -+ -+ au_rw_init(&dinfo->di_rwsem); -+ au_rw_class(&dinfo->di_rwsem, &aufs_di); -+} -+ -+struct au_dinfo *au_di_alloc(struct super_block *sb, unsigned int lsc) -+{ -+ struct au_dinfo *dinfo; -+ int nbr, i; -+ -+ dinfo = au_cache_alloc_dinfo(); -+ if (unlikely(!dinfo)) -+ goto out; -+ -+ nbr = au_sbend(sb) + 1; -+ if (nbr <= 0) -+ nbr = 1; -+ dinfo->di_hdentry = kcalloc(nbr, sizeof(*dinfo->di_hdentry), GFP_NOFS); -+ if (dinfo->di_hdentry) { -+ au_rw_write_lock_nested(&dinfo->di_rwsem, lsc); -+ dinfo->di_bstart = -1; -+ dinfo->di_bend = -1; -+ dinfo->di_bwh = -1; -+ dinfo->di_bdiropq = -1; -+ for (i = 0; i < nbr; i++) -+ dinfo->di_hdentry[i].hd_id = -1; -+ goto out; -+ } -+ -+ au_cache_free_dinfo(dinfo); -+ dinfo = NULL; -+ -+out: -+ return dinfo; -+} -+ -+void au_di_free(struct au_dinfo *dinfo) -+{ -+ struct au_hdentry *p; -+ aufs_bindex_t bend, bindex; -+ -+ /* dentry may not be revalidated */ -+ bindex = dinfo->di_bstart; -+ if (bindex >= 0) { -+ bend = dinfo->di_bend; -+ p = dinfo->di_hdentry + bindex; -+ while (bindex++ <= bend) -+ au_hdput(p++); -+ } -+ kfree(dinfo->di_hdentry); -+ au_cache_free_dinfo(dinfo); -+} -+ -+void au_di_swap(struct au_dinfo *a, struct au_dinfo *b) -+{ -+ struct au_hdentry *p; -+ aufs_bindex_t bi; -+ -+ AuRwMustWriteLock(&a->di_rwsem); -+ AuRwMustWriteLock(&b->di_rwsem); -+ -+#define DiSwap(v, name) \ -+ do { \ -+ v = a->di_##name; \ -+ a->di_##name = b->di_##name; \ -+ b->di_##name = v; \ -+ } while (0) -+ -+ DiSwap(p, hdentry); -+ DiSwap(bi, bstart); -+ DiSwap(bi, bend); -+ DiSwap(bi, bwh); -+ DiSwap(bi, bdiropq); -+ /* smp_mb(); */ -+ -+#undef DiSwap -+} -+ -+void au_di_cp(struct au_dinfo *dst, struct au_dinfo *src) -+{ -+ AuRwMustWriteLock(&dst->di_rwsem); -+ AuRwMustWriteLock(&src->di_rwsem); -+ -+ dst->di_bstart = src->di_bstart; -+ dst->di_bend = src->di_bend; -+ dst->di_bwh = src->di_bwh; -+ dst->di_bdiropq = src->di_bdiropq; -+ /* smp_mb(); */ -+} -+ -+int au_di_init(struct dentry *dentry) -+{ -+ int err; -+ struct super_block *sb; -+ struct au_dinfo *dinfo; -+ -+ err = 0; -+ sb = dentry->d_sb; -+ dinfo = au_di_alloc(sb, AuLsc_DI_CHILD); -+ if (dinfo) { -+ atomic_set(&dinfo->di_generation, au_sigen(sb)); -+ /* smp_mb(); */ /* atomic_set */ -+ dentry->d_op = &aufs_dop; -+ dentry->d_fsdata = dinfo; -+ } else -+ err = -ENOMEM; -+ -+ return err; -+} -+ -+void au_di_fin(struct dentry *dentry) -+{ -+ struct au_dinfo *dinfo; -+ -+ dinfo = au_di(dentry); -+ AuRwDestroy(&dinfo->di_rwsem); -+ au_di_free(dinfo); -+} -+ -+int au_di_realloc(struct au_dinfo *dinfo, int nbr) -+{ -+ int err, sz; -+ struct au_hdentry *hdp; -+ -+ AuRwMustWriteLock(&dinfo->di_rwsem); -+ -+ err = -ENOMEM; -+ sz = sizeof(*hdp) * (dinfo->di_bend + 1); -+ if (!sz) -+ sz = sizeof(*hdp); -+ hdp = au_kzrealloc(dinfo->di_hdentry, sz, sizeof(*hdp) * nbr, GFP_NOFS); -+ if (hdp) { -+ dinfo->di_hdentry = hdp; -+ err = 0; -+ } -+ -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static void do_ii_write_lock(struct inode *inode, unsigned int lsc) -+{ -+ switch (lsc) { -+ case AuLsc_DI_CHILD: -+ ii_write_lock_child(inode); -+ break; -+ case AuLsc_DI_CHILD2: -+ ii_write_lock_child2(inode); -+ break; -+ case AuLsc_DI_CHILD3: -+ ii_write_lock_child3(inode); -+ break; -+ case AuLsc_DI_PARENT: -+ ii_write_lock_parent(inode); -+ break; -+ case AuLsc_DI_PARENT2: -+ ii_write_lock_parent2(inode); -+ break; -+ case AuLsc_DI_PARENT3: -+ ii_write_lock_parent3(inode); -+ break; -+ default: -+ BUG(); -+ } -+} -+ -+static void do_ii_read_lock(struct inode *inode, unsigned int lsc) -+{ -+ switch (lsc) { -+ case AuLsc_DI_CHILD: -+ ii_read_lock_child(inode); -+ break; -+ case AuLsc_DI_CHILD2: -+ ii_read_lock_child2(inode); -+ break; -+ case AuLsc_DI_CHILD3: -+ ii_read_lock_child3(inode); -+ break; -+ case AuLsc_DI_PARENT: -+ ii_read_lock_parent(inode); -+ break; -+ case AuLsc_DI_PARENT2: -+ ii_read_lock_parent2(inode); -+ break; -+ case AuLsc_DI_PARENT3: -+ ii_read_lock_parent3(inode); -+ break; -+ default: -+ BUG(); -+ } -+} -+ -+void di_read_lock(struct dentry *d, int flags, unsigned int lsc) -+{ -+ au_rw_read_lock_nested(&au_di(d)->di_rwsem, lsc); -+ if (d->d_inode) { -+ if (au_ftest_lock(flags, IW)) -+ do_ii_write_lock(d->d_inode, lsc); -+ else if (au_ftest_lock(flags, IR)) -+ do_ii_read_lock(d->d_inode, lsc); -+ } -+} -+ -+void di_read_unlock(struct dentry *d, int flags) -+{ -+ if (d->d_inode) { -+ if (au_ftest_lock(flags, IW)) { -+ au_dbg_verify_dinode(d); -+ ii_write_unlock(d->d_inode); -+ } else if (au_ftest_lock(flags, IR)) { -+ au_dbg_verify_dinode(d); -+ ii_read_unlock(d->d_inode); -+ } -+ } -+ au_rw_read_unlock(&au_di(d)->di_rwsem); -+} -+ -+void di_downgrade_lock(struct dentry *d, int flags) -+{ -+ if (d->d_inode && au_ftest_lock(flags, IR)) -+ ii_downgrade_lock(d->d_inode); -+ au_rw_dgrade_lock(&au_di(d)->di_rwsem); -+} -+ -+void di_write_lock(struct dentry *d, unsigned int lsc) -+{ -+ au_rw_write_lock_nested(&au_di(d)->di_rwsem, lsc); -+ if (d->d_inode) -+ do_ii_write_lock(d->d_inode, lsc); -+} -+ -+void di_write_unlock(struct dentry *d) -+{ -+ au_dbg_verify_dinode(d); -+ if (d->d_inode) -+ ii_write_unlock(d->d_inode); -+ au_rw_write_unlock(&au_di(d)->di_rwsem); -+} -+ -+void di_write_lock2_child(struct dentry *d1, struct dentry *d2, int isdir) -+{ -+ AuDebugOn(d1 == d2 -+ || d1->d_inode == d2->d_inode -+ || d1->d_sb != d2->d_sb); -+ -+ if (isdir && au_test_subdir(d1, d2)) { -+ di_write_lock_child(d1); -+ di_write_lock_child2(d2); -+ } else { -+ /* there should be no races */ -+ di_write_lock_child(d2); -+ di_write_lock_child2(d1); -+ } -+} -+ -+void di_write_lock2_parent(struct dentry *d1, struct dentry *d2, int isdir) -+{ -+ AuDebugOn(d1 == d2 -+ || d1->d_inode == d2->d_inode -+ || d1->d_sb != d2->d_sb); -+ -+ if (isdir && au_test_subdir(d1, d2)) { -+ di_write_lock_parent(d1); -+ di_write_lock_parent2(d2); -+ } else { -+ /* there should be no races */ -+ di_write_lock_parent(d2); -+ di_write_lock_parent2(d1); -+ } -+} -+ -+void di_write_unlock2(struct dentry *d1, struct dentry *d2) -+{ -+ di_write_unlock(d1); -+ if (d1->d_inode == d2->d_inode) -+ au_rw_write_unlock(&au_di(d2)->di_rwsem); -+ else -+ di_write_unlock(d2); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+struct dentry *au_h_dptr(struct dentry *dentry, aufs_bindex_t bindex) -+{ -+ struct dentry *d; -+ -+ DiMustAnyLock(dentry); -+ -+ if (au_dbstart(dentry) < 0 || bindex < au_dbstart(dentry)) -+ return NULL; -+ AuDebugOn(bindex < 0); -+ d = au_di(dentry)->di_hdentry[0 + bindex].hd_dentry; -+ AuDebugOn(d && (atomic_read(&d->d_count) <= 0)); -+ return d; -+} -+ -+aufs_bindex_t au_dbtail(struct dentry *dentry) -+{ -+ aufs_bindex_t bend, bwh; -+ -+ bend = au_dbend(dentry); -+ if (0 <= bend) { -+ bwh = au_dbwh(dentry); -+ if (!bwh) -+ return bwh; -+ if (0 < bwh && bwh < bend) -+ return bwh - 1; -+ } -+ return bend; -+} -+ -+aufs_bindex_t au_dbtaildir(struct dentry *dentry) -+{ -+ aufs_bindex_t bend, bopq; -+ -+ bend = au_dbtail(dentry); -+ if (0 <= bend) { -+ bopq = au_dbdiropq(dentry); -+ if (0 <= bopq && bopq < bend) -+ bend = bopq; -+ } -+ return bend; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+void au_set_h_dptr(struct dentry *dentry, aufs_bindex_t bindex, -+ struct dentry *h_dentry) -+{ -+ struct au_hdentry *hd = au_di(dentry)->di_hdentry + bindex; -+ struct au_branch *br; -+ -+ DiMustWriteLock(dentry); -+ -+ au_hdput(hd); -+ hd->hd_dentry = h_dentry; -+ if (h_dentry) { -+ br = au_sbr(dentry->d_sb, bindex); -+ hd->hd_id = br->br_id; -+ } -+} -+ -+int au_dbrange_test(struct dentry *dentry) -+{ -+ int err; -+ aufs_bindex_t bstart, bend; -+ -+ err = 0; -+ bstart = au_dbstart(dentry); -+ bend = au_dbend(dentry); -+ if (bstart >= 0) -+ AuDebugOn(bend < 0 && bstart > bend); -+ else { -+ err = -EIO; -+ AuDebugOn(bend >= 0); -+ } -+ -+ return err; -+} -+ -+int au_digen_test(struct dentry *dentry, unsigned int sigen) -+{ -+ int err; -+ -+ err = 0; -+ if (unlikely(au_digen(dentry) != sigen -+ || au_iigen_test(dentry->d_inode, sigen))) -+ err = -EIO; -+ -+ return err; -+} -+ -+void au_update_digen(struct dentry *dentry) -+{ -+ atomic_set(&au_di(dentry)->di_generation, au_sigen(dentry->d_sb)); -+ /* smp_mb(); */ /* atomic_set */ -+} -+ -+void au_update_dbrange(struct dentry *dentry, int do_put_zero) -+{ -+ struct au_dinfo *dinfo; -+ struct dentry *h_d; -+ struct au_hdentry *hdp; -+ -+ DiMustWriteLock(dentry); -+ -+ dinfo = au_di(dentry); -+ if (!dinfo || dinfo->di_bstart < 0) -+ return; -+ -+ hdp = dinfo->di_hdentry; -+ if (do_put_zero) { -+ aufs_bindex_t bindex, bend; -+ -+ bend = dinfo->di_bend; -+ for (bindex = dinfo->di_bstart; bindex <= bend; bindex++) { -+ h_d = hdp[0 + bindex].hd_dentry; -+ if (h_d && !h_d->d_inode) -+ au_set_h_dptr(dentry, bindex, NULL); -+ } -+ } -+ -+ dinfo->di_bstart = -1; -+ while (++dinfo->di_bstart <= dinfo->di_bend) -+ if (hdp[0 + dinfo->di_bstart].hd_dentry) -+ break; -+ if (dinfo->di_bstart > dinfo->di_bend) { -+ dinfo->di_bstart = -1; -+ dinfo->di_bend = -1; -+ return; -+ } -+ -+ dinfo->di_bend++; -+ while (0 <= --dinfo->di_bend) -+ if (hdp[0 + dinfo->di_bend].hd_dentry) -+ break; -+ AuDebugOn(dinfo->di_bstart > dinfo->di_bend || dinfo->di_bend < 0); -+} -+ -+void au_update_dbstart(struct dentry *dentry) -+{ -+ aufs_bindex_t bindex, bend; -+ struct dentry *h_dentry; -+ -+ bend = au_dbend(dentry); -+ for (bindex = au_dbstart(dentry); bindex <= bend; bindex++) { -+ h_dentry = au_h_dptr(dentry, bindex); -+ if (!h_dentry) -+ continue; -+ if (h_dentry->d_inode) { -+ au_set_dbstart(dentry, bindex); -+ return; -+ } -+ au_set_h_dptr(dentry, bindex, NULL); -+ } -+} -+ -+void au_update_dbend(struct dentry *dentry) -+{ -+ aufs_bindex_t bindex, bstart; -+ struct dentry *h_dentry; -+ -+ bstart = au_dbstart(dentry); -+ for (bindex = au_dbend(dentry); bindex >= bstart; bindex--) { -+ h_dentry = au_h_dptr(dentry, bindex); -+ if (!h_dentry) -+ continue; -+ if (h_dentry->d_inode) { -+ au_set_dbend(dentry, bindex); -+ return; -+ } -+ au_set_h_dptr(dentry, bindex, NULL); -+ } -+} -+ -+int au_find_dbindex(struct dentry *dentry, struct dentry *h_dentry) -+{ -+ aufs_bindex_t bindex, bend; -+ -+ bend = au_dbend(dentry); -+ for (bindex = au_dbstart(dentry); bindex <= bend; bindex++) -+ if (au_h_dptr(dentry, bindex) == h_dentry) -+ return bindex; -+ return -1; -+} -diff -Nur linux-2.6.37.orig/fs/aufs/dir.c linux-2.6.37/fs/aufs/dir.c ---- linux-2.6.37.orig/fs/aufs/dir.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/dir.c 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,648 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * directory operations -+ */ -+ -+#include -+#include -+#include "aufs.h" -+ -+void au_add_nlink(struct inode *dir, struct inode *h_dir) -+{ -+ AuDebugOn(!S_ISDIR(dir->i_mode) || !S_ISDIR(h_dir->i_mode)); -+ -+ dir->i_nlink += h_dir->i_nlink - 2; -+ if (h_dir->i_nlink < 2) -+ dir->i_nlink += 2; -+} -+ -+void au_sub_nlink(struct inode *dir, struct inode *h_dir) -+{ -+ AuDebugOn(!S_ISDIR(dir->i_mode) || !S_ISDIR(h_dir->i_mode)); -+ -+ dir->i_nlink -= h_dir->i_nlink - 2; -+ if (h_dir->i_nlink < 2) -+ dir->i_nlink -= 2; -+} -+ -+loff_t au_dir_size(struct file *file, struct dentry *dentry) -+{ -+ loff_t sz; -+ aufs_bindex_t bindex, bend; -+ struct file *h_file; -+ struct dentry *h_dentry; -+ -+ sz = 0; -+ if (file) { -+ AuDebugOn(!file->f_dentry); -+ AuDebugOn(!file->f_dentry->d_inode); -+ AuDebugOn(!S_ISDIR(file->f_dentry->d_inode->i_mode)); -+ -+ bend = au_fbend_dir(file); -+ for (bindex = au_fbstart(file); -+ bindex <= bend && sz < KMALLOC_MAX_SIZE; -+ bindex++) { -+ h_file = au_hf_dir(file, bindex); -+ if (h_file -+ && h_file->f_dentry -+ && h_file->f_dentry->d_inode) -+ sz += i_size_read(h_file->f_dentry->d_inode); -+ } -+ } else { -+ AuDebugOn(!dentry); -+ AuDebugOn(!dentry->d_inode); -+ AuDebugOn(!S_ISDIR(dentry->d_inode->i_mode)); -+ -+ bend = au_dbtaildir(dentry); -+ for (bindex = au_dbstart(dentry); -+ bindex <= bend && sz < KMALLOC_MAX_SIZE; -+ bindex++) { -+ h_dentry = au_h_dptr(dentry, bindex); -+ if (h_dentry && h_dentry->d_inode) -+ sz += i_size_read(h_dentry->d_inode); -+ } -+ } -+ if (sz < KMALLOC_MAX_SIZE) -+ sz = roundup_pow_of_two(sz); -+ if (sz > KMALLOC_MAX_SIZE) -+ sz = KMALLOC_MAX_SIZE; -+ else if (sz < NAME_MAX) { -+ BUILD_BUG_ON(AUFS_RDBLK_DEF < NAME_MAX); -+ sz = AUFS_RDBLK_DEF; -+ } -+ return sz; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int reopen_dir(struct file *file) -+{ -+ int err; -+ unsigned int flags; -+ aufs_bindex_t bindex, btail, bstart; -+ struct dentry *dentry, *h_dentry; -+ struct file *h_file; -+ -+ /* open all lower dirs */ -+ dentry = file->f_dentry; -+ bstart = au_dbstart(dentry); -+ for (bindex = au_fbstart(file); bindex < bstart; bindex++) -+ au_set_h_fptr(file, bindex, NULL); -+ au_set_fbstart(file, bstart); -+ -+ btail = au_dbtaildir(dentry); -+ for (bindex = au_fbend_dir(file); btail < bindex; bindex--) -+ au_set_h_fptr(file, bindex, NULL); -+ au_set_fbend_dir(file, btail); -+ -+ flags = vfsub_file_flags(file); -+ for (bindex = bstart; bindex <= btail; bindex++) { -+ h_dentry = au_h_dptr(dentry, bindex); -+ if (!h_dentry) -+ continue; -+ h_file = au_hf_dir(file, bindex); -+ if (h_file) -+ continue; -+ -+ h_file = au_h_open(dentry, bindex, flags, file); -+ err = PTR_ERR(h_file); -+ if (IS_ERR(h_file)) -+ goto out; /* close all? */ -+ au_set_h_fptr(file, bindex, h_file); -+ } -+ au_update_figen(file); -+ /* todo: necessary? */ -+ /* file->f_ra = h_file->f_ra; */ -+ err = 0; -+ -+out: -+ return err; -+} -+ -+static int do_open_dir(struct file *file, int flags) -+{ -+ int err; -+ aufs_bindex_t bindex, btail; -+ struct dentry *dentry, *h_dentry; -+ struct file *h_file; -+ -+ FiMustWriteLock(file); -+ -+ dentry = file->f_dentry; -+ err = au_alive_dir(dentry); -+ if (unlikely(err)) -+ goto out; -+ -+ file->f_version = dentry->d_inode->i_version; -+ bindex = au_dbstart(dentry); -+ au_set_fbstart(file, bindex); -+ btail = au_dbtaildir(dentry); -+ au_set_fbend_dir(file, btail); -+ for (; !err && bindex <= btail; bindex++) { -+ h_dentry = au_h_dptr(dentry, bindex); -+ if (!h_dentry) -+ continue; -+ -+ h_file = au_h_open(dentry, bindex, flags, file); -+ if (IS_ERR(h_file)) { -+ err = PTR_ERR(h_file); -+ break; -+ } -+ au_set_h_fptr(file, bindex, h_file); -+ } -+ au_update_figen(file); -+ /* todo: necessary? */ -+ /* file->f_ra = h_file->f_ra; */ -+ if (!err) -+ return 0; /* success */ -+ -+ /* close all */ -+ for (bindex = au_fbstart(file); bindex <= btail; bindex++) -+ au_set_h_fptr(file, bindex, NULL); -+ au_set_fbstart(file, -1); -+ au_set_fbend_dir(file, -1); -+ -+out: -+ return err; -+} -+ -+static int aufs_open_dir(struct inode *inode __maybe_unused, -+ struct file *file) -+{ -+ int err; -+ struct super_block *sb; -+ struct au_fidir *fidir; -+ -+ err = -ENOMEM; -+ sb = file->f_dentry->d_sb; -+ si_read_lock(sb, AuLock_FLUSH); -+ fidir = au_fidir_alloc(sb); -+ if (fidir) { -+ err = au_do_open(file, do_open_dir, fidir); -+ if (unlikely(err)) -+ kfree(fidir); -+ } -+ si_read_unlock(sb); -+ return err; -+} -+ -+static int aufs_release_dir(struct inode *inode __maybe_unused, -+ struct file *file) -+{ -+ struct au_vdir *vdir_cache; -+ struct super_block *sb; -+ struct au_finfo *finfo; -+ struct au_fidir *fidir; -+ aufs_bindex_t bindex, bend; -+ -+ sb = file->f_dentry->d_sb; -+ finfo = au_fi(file); -+ fidir = finfo->fi_hdir; -+ if (fidir) { -+ /* remove me from sb->s_files */ -+ file_sb_list_del(file); -+ -+ vdir_cache = fidir->fd_vdir_cache; /* lock-free */ -+ if (vdir_cache) -+ au_vdir_free(vdir_cache); -+ -+ bindex = finfo->fi_btop; -+ if (bindex >= 0) { -+ /* -+ * calls fput() instead of filp_close(), -+ * since no dnotify or lock for the lower file. -+ */ -+ bend = fidir->fd_bbot; -+ for (; bindex <= bend; bindex++) -+ au_set_h_fptr(file, bindex, NULL); -+ } -+ kfree(fidir); -+ finfo->fi_hdir = NULL; -+ } -+ au_finfo_fin(file); -+ return 0; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int au_do_flush_dir(struct file *file, fl_owner_t id) -+{ -+ int err; -+ aufs_bindex_t bindex, bend; -+ struct file *h_file; -+ -+ err = 0; -+ bend = au_fbend_dir(file); -+ for (bindex = au_fbstart(file); !err && bindex <= bend; bindex++) { -+ h_file = au_hf_dir(file, bindex); -+ if (h_file) -+ err = vfsub_flush(h_file, id); -+ } -+ return err; -+} -+ -+static int aufs_flush_dir(struct file *file, fl_owner_t id) -+{ -+ return au_do_flush(file, id, au_do_flush_dir); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int au_do_fsync_dir_no_file(struct dentry *dentry, int datasync) -+{ -+ int err; -+ aufs_bindex_t bend, bindex; -+ struct inode *inode; -+ struct super_block *sb; -+ -+ err = 0; -+ sb = dentry->d_sb; -+ inode = dentry->d_inode; -+ IMustLock(inode); -+ bend = au_dbend(dentry); -+ for (bindex = au_dbstart(dentry); !err && bindex <= bend; bindex++) { -+ struct path h_path; -+ struct inode *h_inode; -+ -+ if (au_test_ro(sb, bindex, inode)) -+ continue; -+ h_path.dentry = au_h_dptr(dentry, bindex); -+ if (!h_path.dentry) -+ continue; -+ h_inode = h_path.dentry->d_inode; -+ if (!h_inode) -+ continue; -+ -+ /* no mnt_want_write() */ -+ /* cf. fs/nsfd/vfs.c and fs/nfsd/nfs4recover.c */ -+ /* todo: inotiry fired? */ -+ h_path.mnt = au_sbr_mnt(sb, bindex); -+ mutex_lock(&h_inode->i_mutex); -+ err = filemap_fdatawrite(h_inode->i_mapping); -+ AuDebugOn(!h_inode->i_fop); -+ if (!err && h_inode->i_fop->fsync) -+ err = h_inode->i_fop->fsync(NULL, datasync); -+ if (!err) -+ err = filemap_fdatawrite(h_inode->i_mapping); -+ if (!err) -+ vfsub_update_h_iattr(&h_path, /*did*/NULL); /*ignore*/ -+ mutex_unlock(&h_inode->i_mutex); -+ } -+ -+ return err; -+} -+ -+static int au_do_fsync_dir(struct file *file, int datasync) -+{ -+ int err; -+ aufs_bindex_t bend, bindex; -+ struct file *h_file; -+ struct super_block *sb; -+ struct inode *inode; -+ struct mutex *h_mtx; -+ -+ err = au_reval_and_lock_fdi(file, reopen_dir, /*wlock*/1); -+ if (unlikely(err)) -+ goto out; -+ -+ sb = file->f_dentry->d_sb; -+ inode = file->f_dentry->d_inode; -+ bend = au_fbend_dir(file); -+ for (bindex = au_fbstart(file); !err && bindex <= bend; bindex++) { -+ h_file = au_hf_dir(file, bindex); -+ if (!h_file || au_test_ro(sb, bindex, inode)) -+ continue; -+ -+ err = vfs_fsync(h_file, datasync); -+ if (!err) { -+ h_mtx = &h_file->f_dentry->d_inode->i_mutex; -+ mutex_lock(h_mtx); -+ vfsub_update_h_iattr(&h_file->f_path, /*did*/NULL); -+ /*ignore*/ -+ mutex_unlock(h_mtx); -+ } -+ } -+ -+out: -+ return err; -+} -+ -+/* -+ * @file may be NULL -+ */ -+static int aufs_fsync_dir(struct file *file, int datasync) -+{ -+ int err; -+ struct dentry *dentry; -+ struct super_block *sb; -+ -+ dentry = file->f_dentry; -+ IMustLock(dentry->d_inode); -+ -+ err = 0; -+ sb = dentry->d_sb; -+ si_noflush_read_lock(sb); -+ if (file) -+ err = au_do_fsync_dir(file, datasync); -+ else { -+ di_write_lock_child(dentry); -+ err = au_do_fsync_dir_no_file(dentry, datasync); -+ } -+ au_cpup_attr_timesizes(dentry->d_inode); -+ di_write_unlock(dentry); -+ if (file) -+ fi_write_unlock(file); -+ -+ si_read_unlock(sb); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int aufs_readdir(struct file *file, void *dirent, filldir_t filldir) -+{ -+ int err; -+ struct dentry *dentry; -+ struct inode *inode; -+ struct super_block *sb; -+ -+ dentry = file->f_dentry; -+ inode = dentry->d_inode; -+ IMustLock(inode); -+ -+ sb = dentry->d_sb; -+ si_read_lock(sb, AuLock_FLUSH); -+ err = au_reval_and_lock_fdi(file, reopen_dir, /*wlock*/1); -+ if (unlikely(err)) -+ goto out; -+ err = au_alive_dir(dentry); -+ if (!err) -+ err = au_vdir_init(file); -+ di_downgrade_lock(dentry, AuLock_IR); -+ if (unlikely(err)) -+ goto out_unlock; -+ -+ if (!au_test_nfsd()) { -+ err = au_vdir_fill_de(file, dirent, filldir); -+ fsstack_copy_attr_atime(inode, -+ au_h_iptr(inode, au_ibstart(inode))); -+ } else { -+ /* -+ * nfsd filldir may call lookup_one_len(), vfs_getattr(), -+ * encode_fh() and others. -+ */ -+ struct inode *h_inode = au_h_iptr(inode, au_ibstart(inode)); -+ -+ di_read_unlock(dentry, AuLock_IR); -+ si_read_unlock(sb); -+ err = au_vdir_fill_de(file, dirent, filldir); -+ fsstack_copy_attr_atime(inode, h_inode); -+ fi_write_unlock(file); -+ -+ AuTraceErr(err); -+ return err; -+ } -+ -+out_unlock: -+ di_read_unlock(dentry, AuLock_IR); -+ fi_write_unlock(file); -+out: -+ si_read_unlock(sb); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+#define AuTestEmpty_WHONLY 1 -+#define AuTestEmpty_CALLED (1 << 1) -+#define AuTestEmpty_SHWH (1 << 2) -+#define au_ftest_testempty(flags, name) ((flags) & AuTestEmpty_##name) -+#define au_fset_testempty(flags, name) \ -+ do { (flags) |= AuTestEmpty_##name; } while (0) -+#define au_fclr_testempty(flags, name) \ -+ do { (flags) &= ~AuTestEmpty_##name; } while (0) -+ -+#ifndef CONFIG_AUFS_SHWH -+#undef AuTestEmpty_SHWH -+#define AuTestEmpty_SHWH 0 -+#endif -+ -+struct test_empty_arg { -+ struct au_nhash *whlist; -+ unsigned int flags; -+ int err; -+ aufs_bindex_t bindex; -+}; -+ -+static int test_empty_cb(void *__arg, const char *__name, int namelen, -+ loff_t offset __maybe_unused, u64 ino, -+ unsigned int d_type) -+{ -+ struct test_empty_arg *arg = __arg; -+ char *name = (void *)__name; -+ -+ arg->err = 0; -+ au_fset_testempty(arg->flags, CALLED); -+ /* smp_mb(); */ -+ if (name[0] == '.' -+ && (namelen == 1 || (name[1] == '.' && namelen == 2))) -+ goto out; /* success */ -+ -+ if (namelen <= AUFS_WH_PFX_LEN -+ || memcmp(name, AUFS_WH_PFX, AUFS_WH_PFX_LEN)) { -+ if (au_ftest_testempty(arg->flags, WHONLY) -+ && !au_nhash_test_known_wh(arg->whlist, name, namelen)) -+ arg->err = -ENOTEMPTY; -+ goto out; -+ } -+ -+ name += AUFS_WH_PFX_LEN; -+ namelen -= AUFS_WH_PFX_LEN; -+ if (!au_nhash_test_known_wh(arg->whlist, name, namelen)) -+ arg->err = au_nhash_append_wh -+ (arg->whlist, name, namelen, ino, d_type, arg->bindex, -+ au_ftest_testempty(arg->flags, SHWH)); -+ -+out: -+ /* smp_mb(); */ -+ AuTraceErr(arg->err); -+ return arg->err; -+} -+ -+static int do_test_empty(struct dentry *dentry, struct test_empty_arg *arg) -+{ -+ int err; -+ struct file *h_file; -+ -+ h_file = au_h_open(dentry, arg->bindex, -+ O_RDONLY | O_NONBLOCK | O_DIRECTORY | O_LARGEFILE, -+ /*file*/NULL); -+ err = PTR_ERR(h_file); -+ if (IS_ERR(h_file)) -+ goto out; -+ -+ err = 0; -+ if (!au_opt_test(au_mntflags(dentry->d_sb), UDBA_NONE) -+ && !h_file->f_dentry->d_inode->i_nlink) -+ goto out_put; -+ -+ do { -+ arg->err = 0; -+ au_fclr_testempty(arg->flags, CALLED); -+ /* smp_mb(); */ -+ err = vfsub_readdir(h_file, test_empty_cb, arg); -+ if (err >= 0) -+ err = arg->err; -+ } while (!err && au_ftest_testempty(arg->flags, CALLED)); -+ -+out_put: -+ fput(h_file); -+ au_sbr_put(dentry->d_sb, arg->bindex); -+out: -+ return err; -+} -+ -+struct do_test_empty_args { -+ int *errp; -+ struct dentry *dentry; -+ struct test_empty_arg *arg; -+}; -+ -+static void call_do_test_empty(void *args) -+{ -+ struct do_test_empty_args *a = args; -+ *a->errp = do_test_empty(a->dentry, a->arg); -+} -+ -+static int sio_test_empty(struct dentry *dentry, struct test_empty_arg *arg) -+{ -+ int err, wkq_err; -+ struct dentry *h_dentry; -+ struct inode *h_inode; -+ -+ h_dentry = au_h_dptr(dentry, arg->bindex); -+ h_inode = h_dentry->d_inode; -+ mutex_lock_nested(&h_inode->i_mutex, AuLsc_I_CHILD); -+ err = au_test_h_perm_sio(h_inode, MAY_EXEC | MAY_READ); -+ mutex_unlock(&h_inode->i_mutex); -+ if (!err) -+ err = do_test_empty(dentry, arg); -+ else { -+ struct do_test_empty_args args = { -+ .errp = &err, -+ .dentry = dentry, -+ .arg = arg -+ }; -+ unsigned int flags = arg->flags; -+ -+ wkq_err = au_wkq_wait(call_do_test_empty, &args); -+ if (unlikely(wkq_err)) -+ err = wkq_err; -+ arg->flags = flags; -+ } -+ -+ return err; -+} -+ -+int au_test_empty_lower(struct dentry *dentry) -+{ -+ int err; -+ unsigned int rdhash; -+ aufs_bindex_t bindex, bstart, btail; -+ struct au_nhash whlist; -+ struct test_empty_arg arg; -+ -+ SiMustAnyLock(dentry->d_sb); -+ -+ rdhash = au_sbi(dentry->d_sb)->si_rdhash; -+ if (!rdhash) -+ rdhash = au_rdhash_est(au_dir_size(/*file*/NULL, dentry)); -+ err = au_nhash_alloc(&whlist, rdhash, GFP_NOFS); -+ if (unlikely(err)) -+ goto out; -+ -+ arg.flags = 0; -+ arg.whlist = &whlist; -+ bstart = au_dbstart(dentry); -+ if (au_opt_test(au_mntflags(dentry->d_sb), SHWH)) -+ au_fset_testempty(arg.flags, SHWH); -+ arg.bindex = bstart; -+ err = do_test_empty(dentry, &arg); -+ if (unlikely(err)) -+ goto out_whlist; -+ -+ au_fset_testempty(arg.flags, WHONLY); -+ btail = au_dbtaildir(dentry); -+ for (bindex = bstart + 1; !err && bindex <= btail; bindex++) { -+ struct dentry *h_dentry; -+ -+ h_dentry = au_h_dptr(dentry, bindex); -+ if (h_dentry && h_dentry->d_inode) { -+ arg.bindex = bindex; -+ err = do_test_empty(dentry, &arg); -+ } -+ } -+ -+out_whlist: -+ au_nhash_wh_free(&whlist); -+out: -+ return err; -+} -+ -+int au_test_empty(struct dentry *dentry, struct au_nhash *whlist) -+{ -+ int err; -+ struct test_empty_arg arg; -+ aufs_bindex_t bindex, btail; -+ -+ err = 0; -+ arg.whlist = whlist; -+ arg.flags = AuTestEmpty_WHONLY; -+ if (au_opt_test(au_mntflags(dentry->d_sb), SHWH)) -+ au_fset_testempty(arg.flags, SHWH); -+ btail = au_dbtaildir(dentry); -+ for (bindex = au_dbstart(dentry); !err && bindex <= btail; bindex++) { -+ struct dentry *h_dentry; -+ -+ h_dentry = au_h_dptr(dentry, bindex); -+ if (h_dentry && h_dentry->d_inode) { -+ arg.bindex = bindex; -+ err = sio_test_empty(dentry, &arg); -+ } -+ } -+ -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+const struct file_operations aufs_dir_fop = { -+ .owner = THIS_MODULE, -+ .read = generic_read_dir, -+ .readdir = aufs_readdir, -+ .unlocked_ioctl = aufs_ioctl_dir, -+#ifdef CONFIG_COMPAT -+ .compat_ioctl = aufs_compat_ioctl_dir, -+#endif -+ .open = aufs_open_dir, -+ .release = aufs_release_dir, -+ .flush = aufs_flush_dir, -+ .fsync = aufs_fsync_dir -+}; -diff -Nur linux-2.6.37.orig/fs/aufs/dir.h linux-2.6.37/fs/aufs/dir.h ---- linux-2.6.37.orig/fs/aufs/dir.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/dir.h 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,138 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * directory operations -+ */ -+ -+#ifndef __AUFS_DIR_H__ -+#define __AUFS_DIR_H__ -+ -+#ifdef __KERNEL__ -+ -+#include -+#include -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* need to be faster and smaller */ -+ -+struct au_nhash { -+ unsigned int nh_num; -+ struct hlist_head *nh_head; -+}; -+ -+struct au_vdir_destr { -+ unsigned char len; -+ unsigned char name[0]; -+} __packed; -+ -+struct au_vdir_dehstr { -+ struct hlist_node hash; -+ struct au_vdir_destr *str; -+} ____cacheline_aligned_in_smp; -+ -+struct au_vdir_de { -+ ino_t de_ino; -+ unsigned char de_type; -+ /* caution: packed */ -+ struct au_vdir_destr de_str; -+} __packed; -+ -+struct au_vdir_wh { -+ struct hlist_node wh_hash; -+#ifdef CONFIG_AUFS_SHWH -+ ino_t wh_ino; -+ aufs_bindex_t wh_bindex; -+ unsigned char wh_type; -+#else -+ aufs_bindex_t wh_bindex; -+#endif -+ /* caution: packed */ -+ struct au_vdir_destr wh_str; -+} __packed; -+ -+union au_vdir_deblk_p { -+ unsigned char *deblk; -+ struct au_vdir_de *de; -+}; -+ -+struct au_vdir { -+ unsigned char **vd_deblk; -+ unsigned long vd_nblk; -+ struct { -+ unsigned long ul; -+ union au_vdir_deblk_p p; -+ } vd_last; -+ -+ unsigned long vd_version; -+ unsigned int vd_deblk_sz; -+ unsigned long vd_jiffy; -+} ____cacheline_aligned_in_smp; -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* dir.c */ -+extern const struct file_operations aufs_dir_fop; -+void au_add_nlink(struct inode *dir, struct inode *h_dir); -+void au_sub_nlink(struct inode *dir, struct inode *h_dir); -+loff_t au_dir_size(struct file *file, struct dentry *dentry); -+int au_test_empty_lower(struct dentry *dentry); -+int au_test_empty(struct dentry *dentry, struct au_nhash *whlist); -+ -+/* vdir.c */ -+unsigned int au_rdhash_est(loff_t sz); -+int au_nhash_alloc(struct au_nhash *nhash, unsigned int num_hash, gfp_t gfp); -+void au_nhash_wh_free(struct au_nhash *whlist); -+int au_nhash_test_longer_wh(struct au_nhash *whlist, aufs_bindex_t btgt, -+ int limit); -+int au_nhash_test_known_wh(struct au_nhash *whlist, char *name, int nlen); -+int au_nhash_append_wh(struct au_nhash *whlist, char *name, int nlen, ino_t ino, -+ unsigned int d_type, aufs_bindex_t bindex, -+ unsigned char shwh); -+void au_vdir_free(struct au_vdir *vdir); -+int au_vdir_init(struct file *file); -+int au_vdir_fill_de(struct file *file, void *dirent, filldir_t filldir); -+ -+/* ioctl.c */ -+long aufs_ioctl_dir(struct file *file, unsigned int cmd, unsigned long arg); -+ -+#ifdef CONFIG_AUFS_RDU -+/* rdu.c */ -+long au_rdu_ioctl(struct file *file, unsigned int cmd, unsigned long arg); -+#ifdef CONFIG_COMPAT -+long au_rdu_compat_ioctl(struct file *file, unsigned int cmd, -+ unsigned long arg); -+#endif -+#else -+static inline long au_rdu_ioctl(struct file *file, unsigned int cmd, -+ unsigned long arg) -+{ -+ return -EINVAL; -+} -+#ifdef CONFIG_COMPAT -+static inline long au_rdu_compat_ioctl(struct file *file, unsigned int cmd, -+ unsigned long arg) -+{ -+ return -EINVAL; -+} -+#endif -+#endif -+ -+#endif /* __KERNEL__ */ -+#endif /* __AUFS_DIR_H__ */ -diff -Nur linux-2.6.37.orig/fs/aufs/dynop.c linux-2.6.37/fs/aufs/dynop.c ---- linux-2.6.37.orig/fs/aufs/dynop.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/dynop.c 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,425 @@ -+/* -+ * Copyright (C) 2010-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * dynamically customizable operations for regular files -+ */ -+ -+#include "aufs.h" -+ -+#define DyPrSym(key) AuDbgSym(key->dk_op.dy_hop) -+ -+/* -+ * How large will these lists be? -+ * Usually just a few elements, 20-30 at most for each, I guess. -+ */ -+static struct au_splhead dynop[AuDyLast]; -+ -+static struct au_dykey *dy_gfind_get(struct au_splhead *spl, const void *h_op) -+{ -+ struct au_dykey *key, *tmp; -+ struct list_head *head; -+ -+ key = NULL; -+ head = &spl->head; -+ rcu_read_lock(); -+ list_for_each_entry_rcu(tmp, head, dk_list) -+ if (tmp->dk_op.dy_hop == h_op) { -+ key = tmp; -+ kref_get(&key->dk_kref); -+ break; -+ } -+ rcu_read_unlock(); -+ -+ return key; -+} -+ -+static struct au_dykey *dy_bradd(struct au_branch *br, struct au_dykey *key) -+{ -+ struct au_dykey **k, *found; -+ const void *h_op = key->dk_op.dy_hop; -+ int i; -+ -+ found = NULL; -+ k = br->br_dykey; -+ for (i = 0; i < AuBrDynOp; i++) -+ if (k[i]) { -+ if (k[i]->dk_op.dy_hop == h_op) { -+ found = k[i]; -+ break; -+ } -+ } else -+ break; -+ if (!found) { -+ spin_lock(&br->br_dykey_lock); -+ for (; i < AuBrDynOp; i++) -+ if (k[i]) { -+ if (k[i]->dk_op.dy_hop == h_op) { -+ found = k[i]; -+ break; -+ } -+ } else { -+ k[i] = key; -+ break; -+ } -+ spin_unlock(&br->br_dykey_lock); -+ BUG_ON(i == AuBrDynOp); /* expand the array */ -+ } -+ -+ return found; -+} -+ -+/* kref_get() if @key is already added */ -+static struct au_dykey *dy_gadd(struct au_splhead *spl, struct au_dykey *key) -+{ -+ struct au_dykey *tmp, *found; -+ struct list_head *head; -+ const void *h_op = key->dk_op.dy_hop; -+ -+ found = NULL; -+ head = &spl->head; -+ spin_lock(&spl->spin); -+ list_for_each_entry(tmp, head, dk_list) -+ if (tmp->dk_op.dy_hop == h_op) { -+ kref_get(&tmp->dk_kref); -+ found = tmp; -+ break; -+ } -+ if (!found) -+ list_add_rcu(&key->dk_list, head); -+ spin_unlock(&spl->spin); -+ -+ if (!found) -+ DyPrSym(key); -+ return found; -+} -+ -+static void dy_free_rcu(struct rcu_head *rcu) -+{ -+ struct au_dykey *key; -+ -+ key = container_of(rcu, struct au_dykey, dk_rcu); -+ DyPrSym(key); -+ kfree(key); -+} -+ -+static void dy_free(struct kref *kref) -+{ -+ struct au_dykey *key; -+ struct au_splhead *spl; -+ -+ key = container_of(kref, struct au_dykey, dk_kref); -+ spl = dynop + key->dk_op.dy_type; -+ au_spl_del_rcu(&key->dk_list, spl); -+ call_rcu(&key->dk_rcu, dy_free_rcu); -+} -+ -+void au_dy_put(struct au_dykey *key) -+{ -+ kref_put(&key->dk_kref, dy_free); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+#define DyDbgSize(cnt, op) AuDebugOn(cnt != sizeof(op)/sizeof(void *)) -+ -+#ifdef CONFIG_AUFS_DEBUG -+#define DyDbgDeclare(cnt) unsigned int cnt = 0 -+#define DyDbgInc(cnt) do { cnt++; } while (0) -+#else -+#define DyDbgDeclare(cnt) do {} while (0) -+#define DyDbgInc(cnt) do {} while (0) -+#endif -+ -+#define DySet(func, dst, src, h_op, h_sb) do { \ -+ DyDbgInc(cnt); \ -+ if (h_op->func) { \ -+ if (src.func) \ -+ dst.func = src.func; \ -+ else \ -+ AuDbg("%s %s\n", au_sbtype(h_sb), #func); \ -+ } \ -+} while (0) -+ -+#define DySetForce(func, dst, src) do { \ -+ AuDebugOn(!src.func); \ -+ DyDbgInc(cnt); \ -+ dst.func = src.func; \ -+} while (0) -+ -+#define DySetAop(func) \ -+ DySet(func, dyaop->da_op, aufs_aop, h_aop, h_sb) -+#define DySetAopForce(func) \ -+ DySetForce(func, dyaop->da_op, aufs_aop) -+ -+static void dy_aop(struct au_dykey *key, const void *h_op, -+ struct super_block *h_sb __maybe_unused) -+{ -+ struct au_dyaop *dyaop = (void *)key; -+ const struct address_space_operations *h_aop = h_op; -+ DyDbgDeclare(cnt); -+ -+ AuDbg("%s\n", au_sbtype(h_sb)); -+ -+ DySetAop(writepage); -+ DySetAopForce(readpage); /* force */ -+ DySetAop(sync_page); -+ DySetAop(writepages); -+ DySetAop(set_page_dirty); -+ DySetAop(readpages); -+ DySetAop(write_begin); -+ DySetAop(write_end); -+ DySetAop(bmap); -+ DySetAop(invalidatepage); -+ DySetAop(releasepage); -+ /* these two will be changed according to an aufs mount option */ -+ DySetAop(direct_IO); -+ DySetAop(get_xip_mem); -+ DySetAop(migratepage); -+ DySetAop(launder_page); -+ DySetAop(is_partially_uptodate); -+ DySetAop(error_remove_page); -+ -+ DyDbgSize(cnt, *h_aop); -+ dyaop->da_get_xip_mem = h_aop->get_xip_mem; -+} -+ -+#define DySetVmop(func) \ -+ DySet(func, dyvmop->dv_op, aufs_vm_ops, h_vmop, h_sb) -+#define DySetVmopForce(func) \ -+ DySetForce(func, dyvmop->dv_op, aufs_vm_ops) -+ -+static void dy_vmop(struct au_dykey *key, const void *h_op, -+ struct super_block *h_sb __maybe_unused) -+{ -+ struct au_dyvmop *dyvmop = (void *)key; -+ const struct vm_operations_struct *h_vmop = h_op; -+ DyDbgDeclare(cnt); -+ -+ AuDbg("%s\n", au_sbtype(h_sb)); -+ -+ DySetVmop(open); -+ DySetVmop(close); -+ DySetVmop(fault); -+ DySetVmop(page_mkwrite); -+ DySetVmop(access); -+#ifdef CONFIG_NUMA -+ DySetVmop(set_policy); -+ DySetVmop(get_policy); -+ DySetVmop(migrate); -+#endif -+ -+ DyDbgSize(cnt, *h_vmop); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static void dy_bug(struct kref *kref) -+{ -+ BUG(); -+} -+ -+static struct au_dykey *dy_get(struct au_dynop *op, struct au_branch *br) -+{ -+ struct au_dykey *key, *old; -+ struct au_splhead *spl; -+ struct op { -+ unsigned int sz; -+ void (*set)(struct au_dykey *key, const void *h_op, -+ struct super_block *h_sb __maybe_unused); -+ }; -+ static const struct op a[] = { -+ [AuDy_AOP] = { -+ .sz = sizeof(struct au_dyaop), -+ .set = dy_aop -+ }, -+ [AuDy_VMOP] = { -+ .sz = sizeof(struct au_dyvmop), -+ .set = dy_vmop -+ } -+ }; -+ const struct op *p; -+ -+ spl = dynop + op->dy_type; -+ key = dy_gfind_get(spl, op->dy_hop); -+ if (key) -+ goto out_add; /* success */ -+ -+ p = a + op->dy_type; -+ key = kzalloc(p->sz, GFP_NOFS); -+ if (unlikely(!key)) { -+ key = ERR_PTR(-ENOMEM); -+ goto out; -+ } -+ -+ key->dk_op.dy_hop = op->dy_hop; -+ kref_init(&key->dk_kref); -+ p->set(key, op->dy_hop, br->br_mnt->mnt_sb); -+ old = dy_gadd(spl, key); -+ if (old) { -+ kfree(key); -+ key = old; -+ } -+ -+out_add: -+ old = dy_bradd(br, key); -+ if (old) -+ /* its ref-count should never be zero here */ -+ kref_put(&key->dk_kref, dy_bug); -+out: -+ return key; -+} -+ -+/* ---------------------------------------------------------------------- */ -+/* -+ * Aufs prohibits O_DIRECT by defaut even if the branch supports it. -+ * This behaviour is neccessary to return an error from open(O_DIRECT) instead -+ * of the succeeding I/O. The dio mount option enables O_DIRECT and makes -+ * open(O_DIRECT) always succeed, but the succeeding I/O may return an error. -+ * See the aufs manual in detail. -+ * -+ * To keep this behaviour, aufs has to set NULL to ->get_xip_mem too, and the -+ * performance of fadvise() and madvise() may be affected. -+ */ -+static void dy_adx(struct au_dyaop *dyaop, int do_dx) -+{ -+ if (!do_dx) { -+ dyaop->da_op.direct_IO = NULL; -+ dyaop->da_op.get_xip_mem = NULL; -+ } else { -+ dyaop->da_op.direct_IO = aufs_aop.direct_IO; -+ dyaop->da_op.get_xip_mem = aufs_aop.get_xip_mem; -+ if (!dyaop->da_get_xip_mem) -+ dyaop->da_op.get_xip_mem = NULL; -+ } -+} -+ -+static struct au_dyaop *dy_aget(struct au_branch *br, -+ const struct address_space_operations *h_aop, -+ int do_dx) -+{ -+ struct au_dyaop *dyaop; -+ struct au_dynop op; -+ -+ op.dy_type = AuDy_AOP; -+ op.dy_haop = h_aop; -+ dyaop = (void *)dy_get(&op, br); -+ if (IS_ERR(dyaop)) -+ goto out; -+ dy_adx(dyaop, do_dx); -+ -+out: -+ return dyaop; -+} -+ -+int au_dy_iaop(struct inode *inode, aufs_bindex_t bindex, -+ struct inode *h_inode) -+{ -+ int err, do_dx; -+ struct super_block *sb; -+ struct au_branch *br; -+ struct au_dyaop *dyaop; -+ -+ AuDebugOn(!S_ISREG(h_inode->i_mode)); -+ IiMustWriteLock(inode); -+ -+ sb = inode->i_sb; -+ br = au_sbr(sb, bindex); -+ do_dx = !!au_opt_test(au_mntflags(sb), DIO); -+ dyaop = dy_aget(br, h_inode->i_mapping->a_ops, do_dx); -+ err = PTR_ERR(dyaop); -+ if (IS_ERR(dyaop)) -+ /* unnecessary to call dy_fput() */ -+ goto out; -+ -+ err = 0; -+ inode->i_mapping->a_ops = &dyaop->da_op; -+ -+out: -+ return err; -+} -+ -+/* -+ * Is it safe to replace a_ops during the inode/file is in operation? -+ * Yes, I hope so. -+ */ -+int au_dy_irefresh(struct inode *inode) -+{ -+ int err; -+ aufs_bindex_t bstart; -+ struct inode *h_inode; -+ -+ err = 0; -+ if (S_ISREG(inode->i_mode)) { -+ bstart = au_ibstart(inode); -+ h_inode = au_h_iptr(inode, bstart); -+ err = au_dy_iaop(inode, bstart, h_inode); -+ } -+ return err; -+} -+ -+void au_dy_arefresh(int do_dx) -+{ -+ struct au_splhead *spl; -+ struct list_head *head; -+ struct au_dykey *key; -+ -+ spl = dynop + AuDy_AOP; -+ head = &spl->head; -+ spin_lock(&spl->spin); -+ list_for_each_entry(key, head, dk_list) -+ dy_adx((void *)key, do_dx); -+ spin_unlock(&spl->spin); -+} -+ -+const struct vm_operations_struct * -+au_dy_vmop(struct file *file, struct au_branch *br, -+ const struct vm_operations_struct *h_vmop) -+{ -+ struct au_dyvmop *dyvmop; -+ struct au_dynop op; -+ -+ op.dy_type = AuDy_VMOP; -+ op.dy_hvmop = h_vmop; -+ dyvmop = (void *)dy_get(&op, br); -+ if (IS_ERR(dyvmop)) -+ return (void *)dyvmop; -+ return &dyvmop->dv_op; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+void __init au_dy_init(void) -+{ -+ int i; -+ -+ /* make sure that 'struct au_dykey *' can be any type */ -+ BUILD_BUG_ON(offsetof(struct au_dyaop, da_key)); -+ BUILD_BUG_ON(offsetof(struct au_dyvmop, dv_key)); -+ -+ for (i = 0; i < AuDyLast; i++) -+ au_spl_init(dynop + i); -+} -+ -+void au_dy_fin(void) -+{ -+ int i; -+ -+ for (i = 0; i < AuDyLast; i++) -+ WARN_ON(!list_empty(&dynop[i].head)); -+} -diff -Nur linux-2.6.37.orig/fs/aufs/dynop.h linux-2.6.37/fs/aufs/dynop.h ---- linux-2.6.37.orig/fs/aufs/dynop.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/dynop.h 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,89 @@ -+/* -+ * Copyright (C) 2010-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * dynamically customizable operations (for regular files only) -+ */ -+ -+#ifndef __AUFS_DYNOP_H__ -+#define __AUFS_DYNOP_H__ -+ -+#ifdef __KERNEL__ -+ -+#include -+#include -+#include -+#include -+#include "inode.h" -+ -+enum {AuDy_AOP, AuDy_VMOP, AuDyLast}; -+ -+struct au_dynop { -+ int dy_type; -+ union { -+ const void *dy_hop; -+ const struct address_space_operations *dy_haop; -+ const struct vm_operations_struct *dy_hvmop; -+ }; -+}; -+ -+struct au_dykey { -+ union { -+ struct list_head dk_list; -+ struct rcu_head dk_rcu; -+ }; -+ struct au_dynop dk_op; -+ -+ /* -+ * during I am in the branch local array, kref is gotten. when the -+ * branch is removed, kref is put. -+ */ -+ struct kref dk_kref; -+}; -+ -+/* stop unioning since their sizes are very different from each other */ -+struct au_dyaop { -+ struct au_dykey da_key; -+ struct address_space_operations da_op; /* not const */ -+ int (*da_get_xip_mem)(struct address_space *, pgoff_t, int, -+ void **, unsigned long *); -+}; -+ -+struct au_dyvmop { -+ struct au_dykey dv_key; -+ struct vm_operations_struct dv_op; /* not const */ -+}; -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* dynop.c */ -+struct au_branch; -+void au_dy_put(struct au_dykey *key); -+int au_dy_iaop(struct inode *inode, aufs_bindex_t bindex, -+ struct inode *h_inode); -+int au_dy_irefresh(struct inode *inode); -+void au_dy_arefresh(int do_dio); -+const struct vm_operations_struct * -+au_dy_vmop(struct file *file, struct au_branch *br, -+ const struct vm_operations_struct *h_vmop); -+ -+void __init au_dy_init(void); -+void au_dy_fin(void); -+ -+#endif /* __KERNEL__ */ -+#endif /* __AUFS_DYNOP_H__ */ -diff -Nur linux-2.6.37.orig/fs/aufs/export.c linux-2.6.37/fs/aufs/export.c ---- linux-2.6.37.orig/fs/aufs/export.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/export.c 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,798 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * export via nfs -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "aufs.h" -+ -+union conv { -+#ifdef CONFIG_AUFS_INO_T_64 -+ __u32 a[2]; -+#else -+ __u32 a[1]; -+#endif -+ ino_t ino; -+}; -+ -+static ino_t decode_ino(__u32 *a) -+{ -+ union conv u; -+ -+ BUILD_BUG_ON(sizeof(u.ino) != sizeof(u.a)); -+ u.a[0] = a[0]; -+#ifdef CONFIG_AUFS_INO_T_64 -+ u.a[1] = a[1]; -+#endif -+ return u.ino; -+} -+ -+static void encode_ino(__u32 *a, ino_t ino) -+{ -+ union conv u; -+ -+ u.ino = ino; -+ a[0] = u.a[0]; -+#ifdef CONFIG_AUFS_INO_T_64 -+ a[1] = u.a[1]; -+#endif -+} -+ -+/* NFS file handle */ -+enum { -+ Fh_br_id, -+ Fh_sigen, -+#ifdef CONFIG_AUFS_INO_T_64 -+ /* support 64bit inode number */ -+ Fh_ino1, -+ Fh_ino2, -+ Fh_dir_ino1, -+ Fh_dir_ino2, -+#else -+ Fh_ino1, -+ Fh_dir_ino1, -+#endif -+ Fh_igen, -+ Fh_h_type, -+ Fh_tail, -+ -+ Fh_ino = Fh_ino1, -+ Fh_dir_ino = Fh_dir_ino1 -+}; -+ -+static int au_test_anon(struct dentry *dentry) -+{ -+ return !!(dentry->d_flags & DCACHE_DISCONNECTED); -+} -+ -+/* ---------------------------------------------------------------------- */ -+/* inode generation external table */ -+ -+void au_xigen_inc(struct inode *inode) -+{ -+ loff_t pos; -+ ssize_t sz; -+ __u32 igen; -+ struct super_block *sb; -+ struct au_sbinfo *sbinfo; -+ -+ sb = inode->i_sb; -+ AuDebugOn(!au_opt_test(au_mntflags(sb), XINO)); -+ -+ sbinfo = au_sbi(sb); -+ pos = inode->i_ino; -+ pos *= sizeof(igen); -+ igen = inode->i_generation + 1; -+ sz = xino_fwrite(sbinfo->si_xwrite, sbinfo->si_xigen, &igen, -+ sizeof(igen), &pos); -+ if (sz == sizeof(igen)) -+ return; /* success */ -+ -+ if (unlikely(sz >= 0)) -+ AuIOErr("xigen error (%zd)\n", sz); -+} -+ -+int au_xigen_new(struct inode *inode) -+{ -+ int err; -+ loff_t pos; -+ ssize_t sz; -+ struct super_block *sb; -+ struct au_sbinfo *sbinfo; -+ struct file *file; -+ -+ err = 0; -+ /* todo: dirty, at mount time */ -+ if (inode->i_ino == AUFS_ROOT_INO) -+ goto out; -+ sb = inode->i_sb; -+ SiMustAnyLock(sb); -+ if (unlikely(!au_opt_test(au_mntflags(sb), XINO))) -+ goto out; -+ -+ err = -EFBIG; -+ pos = inode->i_ino; -+ if (unlikely(au_loff_max / sizeof(inode->i_generation) - 1 < pos)) { -+ AuIOErr1("too large i%lld\n", pos); -+ goto out; -+ } -+ pos *= sizeof(inode->i_generation); -+ -+ err = 0; -+ sbinfo = au_sbi(sb); -+ file = sbinfo->si_xigen; -+ BUG_ON(!file); -+ -+ if (i_size_read(file->f_dentry->d_inode) -+ < pos + sizeof(inode->i_generation)) { -+ inode->i_generation = atomic_inc_return(&sbinfo->si_xigen_next); -+ sz = xino_fwrite(sbinfo->si_xwrite, file, &inode->i_generation, -+ sizeof(inode->i_generation), &pos); -+ } else -+ sz = xino_fread(sbinfo->si_xread, file, &inode->i_generation, -+ sizeof(inode->i_generation), &pos); -+ if (sz == sizeof(inode->i_generation)) -+ goto out; /* success */ -+ -+ err = sz; -+ if (unlikely(sz >= 0)) { -+ err = -EIO; -+ AuIOErr("xigen error (%zd)\n", sz); -+ } -+ -+out: -+ return err; -+} -+ -+int au_xigen_set(struct super_block *sb, struct file *base) -+{ -+ int err; -+ struct au_sbinfo *sbinfo; -+ struct file *file; -+ -+ SiMustWriteLock(sb); -+ -+ sbinfo = au_sbi(sb); -+ file = au_xino_create2(base, sbinfo->si_xigen); -+ err = PTR_ERR(file); -+ if (IS_ERR(file)) -+ goto out; -+ err = 0; -+ if (sbinfo->si_xigen) -+ fput(sbinfo->si_xigen); -+ sbinfo->si_xigen = file; -+ -+out: -+ return err; -+} -+ -+void au_xigen_clr(struct super_block *sb) -+{ -+ struct au_sbinfo *sbinfo; -+ -+ SiMustWriteLock(sb); -+ -+ sbinfo = au_sbi(sb); -+ if (sbinfo->si_xigen) { -+ fput(sbinfo->si_xigen); -+ sbinfo->si_xigen = NULL; -+ } -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static struct dentry *decode_by_ino(struct super_block *sb, ino_t ino, -+ ino_t dir_ino) -+{ -+ struct dentry *dentry, *d; -+ struct inode *inode; -+ unsigned int sigen; -+ -+ dentry = NULL; -+ inode = ilookup(sb, ino); -+ if (!inode) -+ goto out; -+ -+ dentry = ERR_PTR(-ESTALE); -+ sigen = au_sigen(sb); -+ if (unlikely(is_bad_inode(inode) -+ || IS_DEADDIR(inode) -+ || sigen != au_iigen(inode))) -+ goto out_iput; -+ -+ dentry = NULL; -+ if (!dir_ino || S_ISDIR(inode->i_mode)) -+ dentry = d_find_alias(inode); -+ else { -+ spin_lock(&dcache_lock); -+ list_for_each_entry(d, &inode->i_dentry, d_alias) -+ if (!au_test_anon(d) -+ && d->d_parent->d_inode->i_ino == dir_ino) { -+ dentry = dget_locked(d); -+ break; -+ } -+ spin_unlock(&dcache_lock); -+ } -+ if (unlikely(dentry && au_digen_test(dentry, sigen))) { -+ dput(dentry); -+ dentry = ERR_PTR(-ESTALE); -+ } -+ -+out_iput: -+ iput(inode); -+out: -+ return dentry; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* todo: dirty? */ -+/* if exportfs_decode_fh() passed vfsmount*, we could be happy */ -+ -+struct au_compare_mnt_args { -+ /* input */ -+ struct super_block *sb; -+ -+ /* output */ -+ struct vfsmount *mnt; -+}; -+ -+static int au_compare_mnt(struct vfsmount *mnt, void *arg) -+{ -+ struct au_compare_mnt_args *a = arg; -+ -+ if (mnt->mnt_sb != a->sb) -+ return 0; -+ a->mnt = mntget(mnt); -+ return 1; -+} -+ -+static struct vfsmount *au_mnt_get(struct super_block *sb) -+{ -+ int err; -+ struct au_compare_mnt_args args = { -+ .sb = sb -+ }; -+ struct mnt_namespace *ns; -+ -+ br_read_lock(vfsmount_lock); -+ /* no get/put ?? */ -+ AuDebugOn(!current->nsproxy); -+ ns = current->nsproxy->mnt_ns; -+ AuDebugOn(!ns); -+ err = iterate_mounts(au_compare_mnt, &args, ns->root); -+ br_read_unlock(vfsmount_lock); -+ AuDebugOn(!err); -+ AuDebugOn(!args.mnt); -+ return args.mnt; -+} -+ -+struct au_nfsd_si_lock { -+ unsigned int sigen; -+ aufs_bindex_t bindex, br_id; -+ unsigned char force_lock; -+}; -+ -+static int si_nfsd_read_lock(struct super_block *sb, -+ struct au_nfsd_si_lock *nsi_lock) -+{ -+ int err; -+ aufs_bindex_t bindex; -+ -+ si_read_lock(sb, AuLock_FLUSH); -+ -+ /* branch id may be wrapped around */ -+ err = 0; -+ bindex = au_br_index(sb, nsi_lock->br_id); -+ if (bindex >= 0 && nsi_lock->sigen + AUFS_BRANCH_MAX > au_sigen(sb)) -+ goto out; /* success */ -+ -+ err = -ESTALE; -+ bindex = -1; -+ if (!nsi_lock->force_lock) -+ si_read_unlock(sb); -+ -+out: -+ nsi_lock->bindex = bindex; -+ return err; -+} -+ -+struct find_name_by_ino { -+ int called, found; -+ ino_t ino; -+ char *name; -+ int namelen; -+}; -+ -+static int -+find_name_by_ino(void *arg, const char *name, int namelen, loff_t offset, -+ u64 ino, unsigned int d_type) -+{ -+ struct find_name_by_ino *a = arg; -+ -+ a->called++; -+ if (a->ino != ino) -+ return 0; -+ -+ memcpy(a->name, name, namelen); -+ a->namelen = namelen; -+ a->found = 1; -+ return 1; -+} -+ -+static struct dentry *au_lkup_by_ino(struct path *path, ino_t ino, -+ struct au_nfsd_si_lock *nsi_lock) -+{ -+ struct dentry *dentry, *parent; -+ struct file *file; -+ struct inode *dir; -+ struct find_name_by_ino arg; -+ int err; -+ -+ parent = path->dentry; -+ if (nsi_lock) -+ si_read_unlock(parent->d_sb); -+ file = vfsub_dentry_open(path, au_dir_roflags); -+ dentry = (void *)file; -+ if (IS_ERR(file)) -+ goto out; -+ -+ dentry = ERR_PTR(-ENOMEM); -+ arg.name = __getname_gfp(GFP_NOFS); -+ if (unlikely(!arg.name)) -+ goto out_file; -+ arg.ino = ino; -+ arg.found = 0; -+ do { -+ arg.called = 0; -+ /* smp_mb(); */ -+ err = vfsub_readdir(file, find_name_by_ino, &arg); -+ } while (!err && !arg.found && arg.called); -+ dentry = ERR_PTR(err); -+ if (unlikely(err)) -+ goto out_name; -+ dentry = ERR_PTR(-ENOENT); -+ if (!arg.found) -+ goto out_name; -+ -+ /* do not call au_lkup_one() */ -+ dir = parent->d_inode; -+ mutex_lock(&dir->i_mutex); -+ dentry = vfsub_lookup_one_len(arg.name, parent, arg.namelen); -+ mutex_unlock(&dir->i_mutex); -+ AuTraceErrPtr(dentry); -+ if (IS_ERR(dentry)) -+ goto out_name; -+ AuDebugOn(au_test_anon(dentry)); -+ if (unlikely(!dentry->d_inode)) { -+ dput(dentry); -+ dentry = ERR_PTR(-ENOENT); -+ } -+ -+out_name: -+ __putname(arg.name); -+out_file: -+ fput(file); -+out: -+ if (unlikely(nsi_lock -+ && si_nfsd_read_lock(parent->d_sb, nsi_lock) < 0)) -+ if (!IS_ERR(dentry)) { -+ dput(dentry); -+ dentry = ERR_PTR(-ESTALE); -+ } -+ AuTraceErrPtr(dentry); -+ return dentry; -+} -+ -+static struct dentry *decode_by_dir_ino(struct super_block *sb, ino_t ino, -+ ino_t dir_ino, -+ struct au_nfsd_si_lock *nsi_lock) -+{ -+ struct dentry *dentry; -+ struct path path; -+ -+ if (dir_ino != AUFS_ROOT_INO) { -+ path.dentry = decode_by_ino(sb, dir_ino, 0); -+ dentry = path.dentry; -+ if (!path.dentry || IS_ERR(path.dentry)) -+ goto out; -+ AuDebugOn(au_test_anon(path.dentry)); -+ } else -+ path.dentry = dget(sb->s_root); -+ -+ path.mnt = au_mnt_get(sb); -+ dentry = au_lkup_by_ino(&path, ino, nsi_lock); -+ path_put(&path); -+ -+out: -+ AuTraceErrPtr(dentry); -+ return dentry; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int h_acceptable(void *expv, struct dentry *dentry) -+{ -+ return 1; -+} -+ -+static char *au_build_path(struct dentry *h_parent, struct path *h_rootpath, -+ char *buf, int len, struct super_block *sb) -+{ -+ char *p; -+ int n; -+ struct path path; -+ -+ p = d_path(h_rootpath, buf, len); -+ if (IS_ERR(p)) -+ goto out; -+ n = strlen(p); -+ -+ path.mnt = h_rootpath->mnt; -+ path.dentry = h_parent; -+ p = d_path(&path, buf, len); -+ if (IS_ERR(p)) -+ goto out; -+ if (n != 1) -+ p += n; -+ -+ path.mnt = au_mnt_get(sb); -+ path.dentry = sb->s_root; -+ p = d_path(&path, buf, len - strlen(p)); -+ mntput(path.mnt); -+ if (IS_ERR(p)) -+ goto out; -+ if (n != 1) -+ p[strlen(p)] = '/'; -+ -+out: -+ AuTraceErrPtr(p); -+ return p; -+} -+ -+static -+struct dentry *decode_by_path(struct super_block *sb, ino_t ino, __u32 *fh, -+ int fh_len, struct au_nfsd_si_lock *nsi_lock) -+{ -+ struct dentry *dentry, *h_parent, *root; -+ struct super_block *h_sb; -+ char *pathname, *p; -+ struct vfsmount *h_mnt; -+ struct au_branch *br; -+ int err; -+ struct path path; -+ -+ br = au_sbr(sb, nsi_lock->bindex); -+ h_mnt = br->br_mnt; -+ h_sb = h_mnt->mnt_sb; -+ /* todo: call lower fh_to_dentry()? fh_to_parent()? */ -+ h_parent = exportfs_decode_fh(h_mnt, (void *)(fh + Fh_tail), -+ fh_len - Fh_tail, fh[Fh_h_type], -+ h_acceptable, /*context*/NULL); -+ dentry = h_parent; -+ if (unlikely(!h_parent || IS_ERR(h_parent))) { -+ AuWarn1("%s decode_fh failed, %ld\n", -+ au_sbtype(h_sb), PTR_ERR(h_parent)); -+ goto out; -+ } -+ dentry = NULL; -+ if (unlikely(au_test_anon(h_parent))) { -+ AuWarn1("%s decode_fh returned a disconnected dentry\n", -+ au_sbtype(h_sb)); -+ goto out_h_parent; -+ } -+ -+ dentry = ERR_PTR(-ENOMEM); -+ pathname = (void *)__get_free_page(GFP_NOFS); -+ if (unlikely(!pathname)) -+ goto out_h_parent; -+ -+ root = sb->s_root; -+ path.mnt = h_mnt; -+ di_read_lock_parent(root, !AuLock_IR); -+ path.dentry = au_h_dptr(root, nsi_lock->bindex); -+ di_read_unlock(root, !AuLock_IR); -+ p = au_build_path(h_parent, &path, pathname, PAGE_SIZE, sb); -+ dentry = (void *)p; -+ if (IS_ERR(p)) -+ goto out_pathname; -+ -+ si_read_unlock(sb); -+ err = vfsub_kern_path(p, LOOKUP_FOLLOW | LOOKUP_DIRECTORY, &path); -+ dentry = ERR_PTR(err); -+ if (unlikely(err)) -+ goto out_relock; -+ -+ dentry = ERR_PTR(-ENOENT); -+ AuDebugOn(au_test_anon(path.dentry)); -+ if (unlikely(!path.dentry->d_inode)) -+ goto out_path; -+ -+ if (ino != path.dentry->d_inode->i_ino) -+ dentry = au_lkup_by_ino(&path, ino, /*nsi_lock*/NULL); -+ else -+ dentry = dget(path.dentry); -+ -+out_path: -+ path_put(&path); -+out_relock: -+ if (unlikely(si_nfsd_read_lock(sb, nsi_lock) < 0)) -+ if (!IS_ERR(dentry)) { -+ dput(dentry); -+ dentry = ERR_PTR(-ESTALE); -+ } -+out_pathname: -+ free_page((unsigned long)pathname); -+out_h_parent: -+ dput(h_parent); -+out: -+ AuTraceErrPtr(dentry); -+ return dentry; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static struct dentry * -+aufs_fh_to_dentry(struct super_block *sb, struct fid *fid, int fh_len, -+ int fh_type) -+{ -+ struct dentry *dentry; -+ __u32 *fh = fid->raw; -+ struct au_branch *br; -+ ino_t ino, dir_ino; -+ struct au_nfsd_si_lock nsi_lock = { -+ .force_lock = 0 -+ }; -+ -+ dentry = ERR_PTR(-ESTALE); -+ /* it should never happen, but the file handle is unreliable */ -+ if (unlikely(fh_len < Fh_tail)) -+ goto out; -+ nsi_lock.sigen = fh[Fh_sigen]; -+ nsi_lock.br_id = fh[Fh_br_id]; -+ -+ /* branch id may be wrapped around */ -+ br = NULL; -+ if (unlikely(si_nfsd_read_lock(sb, &nsi_lock))) -+ goto out; -+ nsi_lock.force_lock = 1; -+ -+ /* is this inode still cached? */ -+ ino = decode_ino(fh + Fh_ino); -+ /* it should never happen */ -+ if (unlikely(ino == AUFS_ROOT_INO)) -+ goto out; -+ -+ dir_ino = decode_ino(fh + Fh_dir_ino); -+ dentry = decode_by_ino(sb, ino, dir_ino); -+ if (IS_ERR(dentry)) -+ goto out_unlock; -+ if (dentry) -+ goto accept; -+ -+ /* is the parent dir cached? */ -+ br = au_sbr(sb, nsi_lock.bindex); -+ atomic_inc(&br->br_count); -+ dentry = decode_by_dir_ino(sb, ino, dir_ino, &nsi_lock); -+ if (IS_ERR(dentry)) -+ goto out_unlock; -+ if (dentry) -+ goto accept; -+ -+ /* lookup path */ -+ dentry = decode_by_path(sb, ino, fh, fh_len, &nsi_lock); -+ if (IS_ERR(dentry)) -+ goto out_unlock; -+ if (unlikely(!dentry)) -+ /* todo?: make it ESTALE */ -+ goto out_unlock; -+ -+accept: -+ if (!au_digen_test(dentry, au_sigen(sb)) -+ && dentry->d_inode->i_generation == fh[Fh_igen]) -+ goto out_unlock; /* success */ -+ -+ dput(dentry); -+ dentry = ERR_PTR(-ESTALE); -+out_unlock: -+ if (br) -+ atomic_dec(&br->br_count); -+ si_read_unlock(sb); -+out: -+ AuTraceErrPtr(dentry); -+ return dentry; -+} -+ -+#if 0 /* reserved for future use */ -+/* support subtreecheck option */ -+static struct dentry *aufs_fh_to_parent(struct super_block *sb, struct fid *fid, -+ int fh_len, int fh_type) -+{ -+ struct dentry *parent; -+ __u32 *fh = fid->raw; -+ ino_t dir_ino; -+ -+ dir_ino = decode_ino(fh + Fh_dir_ino); -+ parent = decode_by_ino(sb, dir_ino, 0); -+ if (IS_ERR(parent)) -+ goto out; -+ if (!parent) -+ parent = decode_by_path(sb, au_br_index(sb, fh[Fh_br_id]), -+ dir_ino, fh, fh_len); -+ -+out: -+ AuTraceErrPtr(parent); -+ return parent; -+} -+#endif -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int aufs_encode_fh(struct dentry *dentry, __u32 *fh, int *max_len, -+ int connectable) -+{ -+ int err; -+ aufs_bindex_t bindex, bend; -+ struct super_block *sb, *h_sb; -+ struct inode *inode; -+ struct dentry *parent, *h_parent; -+ struct au_branch *br; -+ -+ AuDebugOn(au_test_anon(dentry)); -+ -+ parent = NULL; -+ err = -ENOSPC; -+ if (unlikely(*max_len <= Fh_tail)) { -+ AuWarn1("NFSv2 client (max_len %d)?\n", *max_len); -+ goto out; -+ } -+ -+ err = FILEID_ROOT; -+ if (IS_ROOT(dentry)) { -+ AuDebugOn(dentry->d_inode->i_ino != AUFS_ROOT_INO); -+ goto out; -+ } -+ -+ h_parent = NULL; -+ err = aufs_read_lock(dentry, AuLock_FLUSH | AuLock_IR | AuLock_GEN); -+ if (unlikely(err)) -+ goto out; -+ -+ inode = dentry->d_inode; -+ AuDebugOn(!inode); -+ sb = dentry->d_sb; -+#ifdef CONFIG_AUFS_DEBUG -+ if (unlikely(!au_opt_test(au_mntflags(sb), XINO))) -+ AuWarn1("NFS-exporting requires xino\n"); -+#endif -+ err = -EIO; -+ parent = dget_parent(dentry); -+ di_read_lock_parent(parent, !AuLock_IR); -+ bend = au_dbtaildir(parent); -+ for (bindex = au_dbstart(parent); bindex <= bend; bindex++) { -+ h_parent = au_h_dptr(parent, bindex); -+ if (h_parent) { -+ dget(h_parent); -+ break; -+ } -+ } -+ if (unlikely(!h_parent)) -+ goto out_unlock; -+ -+ err = -EPERM; -+ br = au_sbr(sb, bindex); -+ h_sb = br->br_mnt->mnt_sb; -+ if (unlikely(!h_sb->s_export_op)) { -+ AuErr1("%s branch is not exportable\n", au_sbtype(h_sb)); -+ goto out_dput; -+ } -+ -+ fh[Fh_br_id] = br->br_id; -+ fh[Fh_sigen] = au_sigen(sb); -+ encode_ino(fh + Fh_ino, inode->i_ino); -+ encode_ino(fh + Fh_dir_ino, parent->d_inode->i_ino); -+ fh[Fh_igen] = inode->i_generation; -+ -+ *max_len -= Fh_tail; -+ fh[Fh_h_type] = exportfs_encode_fh(h_parent, (void *)(fh + Fh_tail), -+ max_len, -+ /*connectable or subtreecheck*/0); -+ err = fh[Fh_h_type]; -+ *max_len += Fh_tail; -+ /* todo: macros? */ -+ if (err != 255) -+ err = 99; -+ else -+ AuWarn1("%s encode_fh failed\n", au_sbtype(h_sb)); -+ -+out_dput: -+ dput(h_parent); -+out_unlock: -+ di_read_unlock(parent, !AuLock_IR); -+ dput(parent); -+ aufs_read_unlock(dentry, AuLock_IR); -+out: -+ if (unlikely(err < 0)) -+ err = 255; -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int aufs_commit_metadata(struct inode *inode) -+{ -+ int err; -+ aufs_bindex_t bindex; -+ struct super_block *sb; -+ struct inode *h_inode; -+ int (*f)(struct inode *inode); -+ -+ sb = inode->i_sb; -+ si_read_lock(sb, AuLock_FLUSH | AuLock_NOPLMW); -+ ii_write_lock_child(inode); -+ bindex = au_ibstart(inode); -+ AuDebugOn(bindex < 0); -+ h_inode = au_h_iptr(inode, bindex); -+ -+ f = h_inode->i_sb->s_export_op->commit_metadata; -+ if (f) -+ err = f(h_inode); -+ else { -+ struct writeback_control wbc = { -+ .sync_mode = WB_SYNC_ALL, -+ .nr_to_write = 0 /* metadata only */ -+ }; -+ -+ err = sync_inode(h_inode, &wbc); -+ } -+ -+ au_cpup_attr_timesizes(inode); -+ ii_write_unlock(inode); -+ si_read_unlock(sb); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static struct export_operations aufs_export_op = { -+ .fh_to_dentry = aufs_fh_to_dentry, -+ /* .fh_to_parent = aufs_fh_to_parent, */ -+ .encode_fh = aufs_encode_fh, -+ .commit_metadata = aufs_commit_metadata -+}; -+ -+void au_export_init(struct super_block *sb) -+{ -+ struct au_sbinfo *sbinfo; -+ __u32 u; -+ -+ sb->s_export_op = &aufs_export_op; -+ sbinfo = au_sbi(sb); -+ sbinfo->si_xigen = NULL; -+ get_random_bytes(&u, sizeof(u)); -+ BUILD_BUG_ON(sizeof(u) != sizeof(int)); -+ atomic_set(&sbinfo->si_xigen_next, u); -+} -diff -Nur linux-2.6.37.orig/fs/aufs/f_op.c linux-2.6.37/fs/aufs/f_op.c ---- linux-2.6.37.orig/fs/aufs/f_op.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/f_op.c 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,906 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * file and vm operations -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include "aufs.h" -+ -+int au_do_open_nondir(struct file *file, int flags) -+{ -+ int err; -+ aufs_bindex_t bindex; -+ struct file *h_file; -+ struct dentry *dentry; -+ struct au_finfo *finfo; -+ -+ FiMustWriteLock(file); -+ -+ dentry = file->f_dentry; -+ err = au_d_alive(dentry); -+ if (unlikely(err)) -+ goto out; -+ -+ finfo = au_fi(file); -+ memset(&finfo->fi_htop, 0, sizeof(finfo->fi_htop)); -+ finfo->fi_hvmop = NULL; -+ bindex = au_dbstart(dentry); -+ h_file = au_h_open(dentry, bindex, flags, file); -+ if (IS_ERR(h_file)) -+ err = PTR_ERR(h_file); -+ else { -+ au_set_fbstart(file, bindex); -+ au_set_h_fptr(file, bindex, h_file); -+ au_update_figen(file); -+ /* todo: necessary? */ -+ /* file->f_ra = h_file->f_ra; */ -+ } -+ -+out: -+ return err; -+} -+ -+static int aufs_open_nondir(struct inode *inode __maybe_unused, -+ struct file *file) -+{ -+ int err; -+ struct super_block *sb; -+ -+ AuDbg("%.*s, f_ flags 0x%x, f_mode 0x%x\n", -+ AuDLNPair(file->f_dentry), vfsub_file_flags(file), -+ file->f_mode); -+ -+ sb = file->f_dentry->d_sb; -+ si_read_lock(sb, AuLock_FLUSH); -+ err = au_do_open(file, au_do_open_nondir, /*fidir*/NULL); -+ si_read_unlock(sb); -+ return err; -+} -+ -+int aufs_release_nondir(struct inode *inode __maybe_unused, struct file *file) -+{ -+ struct au_finfo *finfo; -+ aufs_bindex_t bindex; -+ -+ finfo = au_fi(file); -+ bindex = finfo->fi_btop; -+ if (bindex >= 0) { -+ /* remove me from sb->s_files */ -+ file_sb_list_del(file); -+ au_set_h_fptr(file, bindex, NULL); -+ } -+ -+ au_finfo_fin(file); -+ return 0; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int au_do_flush_nondir(struct file *file, fl_owner_t id) -+{ -+ int err; -+ struct file *h_file; -+ -+ err = 0; -+ h_file = au_hf_top(file); -+ if (h_file) -+ err = vfsub_flush(h_file, id); -+ return err; -+} -+ -+static int aufs_flush_nondir(struct file *file, fl_owner_t id) -+{ -+ return au_do_flush(file, id, au_do_flush_nondir); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static ssize_t aufs_read(struct file *file, char __user *buf, size_t count, -+ loff_t *ppos) -+{ -+ ssize_t err; -+ struct dentry *dentry; -+ struct file *h_file; -+ struct super_block *sb; -+ -+ dentry = file->f_dentry; -+ sb = dentry->d_sb; -+ si_read_lock(sb, AuLock_FLUSH | AuLock_NOPLMW); -+ err = au_reval_and_lock_fdi(file, au_reopen_nondir, /*wlock*/0); -+ if (unlikely(err)) -+ goto out; -+ -+ h_file = au_hf_top(file); -+ err = vfsub_read_u(h_file, buf, count, ppos); -+ /* todo: necessary? */ -+ /* file->f_ra = h_file->f_ra; */ -+ fsstack_copy_attr_atime(dentry->d_inode, h_file->f_dentry->d_inode); -+ -+ di_read_unlock(dentry, AuLock_IR); -+ fi_read_unlock(file); -+out: -+ si_read_unlock(sb); -+ return err; -+} -+ -+/* -+ * todo: very ugly -+ * it locks both of i_mutex and si_rwsem for read in safe. -+ * if the plink maintenance mode continues forever (that is the problem), -+ * may loop forever. -+ */ -+static void au_mtx_and_read_lock(struct inode *inode) -+{ -+ int err; -+ struct super_block *sb = inode->i_sb; -+ -+ while (1) { -+ mutex_lock(&inode->i_mutex); -+ err = si_read_lock(sb, AuLock_FLUSH | AuLock_NOPLM); -+ if (!err) -+ break; -+ mutex_unlock(&inode->i_mutex); -+ si_read_lock(sb, AuLock_NOPLMW); -+ si_read_unlock(sb); -+ } -+} -+ -+static ssize_t aufs_write(struct file *file, const char __user *ubuf, -+ size_t count, loff_t *ppos) -+{ -+ ssize_t err; -+ struct au_pin pin; -+ struct dentry *dentry; -+ struct inode *inode; -+ struct file *h_file; -+ char __user *buf = (char __user *)ubuf; -+ -+ dentry = file->f_dentry; -+ inode = dentry->d_inode; -+ au_mtx_and_read_lock(inode); -+ -+ err = au_reval_and_lock_fdi(file, au_reopen_nondir, /*wlock*/1); -+ if (unlikely(err)) -+ goto out; -+ -+ err = au_ready_to_write(file, -1, &pin); -+ di_downgrade_lock(dentry, AuLock_IR); -+ if (unlikely(err)) -+ goto out_unlock; -+ -+ h_file = au_hf_top(file); -+ au_unpin(&pin); -+ err = vfsub_write_u(h_file, buf, count, ppos); -+ au_cpup_attr_timesizes(inode); -+ inode->i_mode = h_file->f_dentry->d_inode->i_mode; -+ -+out_unlock: -+ di_read_unlock(dentry, AuLock_IR); -+ fi_write_unlock(file); -+out: -+ si_read_unlock(inode->i_sb); -+ mutex_unlock(&inode->i_mutex); -+ return err; -+} -+ -+static ssize_t au_do_aio(struct file *h_file, int rw, struct kiocb *kio, -+ const struct iovec *iov, unsigned long nv, loff_t pos) -+{ -+ ssize_t err; -+ struct file *file; -+ ssize_t (*func)(struct kiocb *, const struct iovec *, unsigned long, -+ loff_t); -+ -+ err = security_file_permission(h_file, rw); -+ if (unlikely(err)) -+ goto out; -+ -+ err = -ENOSYS; -+ func = NULL; -+ if (rw == MAY_READ) -+ func = h_file->f_op->aio_read; -+ else if (rw == MAY_WRITE) -+ func = h_file->f_op->aio_write; -+ if (func) { -+ file = kio->ki_filp; -+ kio->ki_filp = h_file; -+ err = func(kio, iov, nv, pos); -+ kio->ki_filp = file; -+ } else -+ /* currently there is no such fs */ -+ WARN_ON_ONCE(1); -+ -+out: -+ return err; -+} -+ -+static ssize_t aufs_aio_read(struct kiocb *kio, const struct iovec *iov, -+ unsigned long nv, loff_t pos) -+{ -+ ssize_t err; -+ struct file *file, *h_file; -+ struct dentry *dentry; -+ struct super_block *sb; -+ -+ file = kio->ki_filp; -+ dentry = file->f_dentry; -+ sb = dentry->d_sb; -+ si_read_lock(sb, AuLock_FLUSH | AuLock_NOPLMW); -+ err = au_reval_and_lock_fdi(file, au_reopen_nondir, /*wlock*/0); -+ if (unlikely(err)) -+ goto out; -+ -+ h_file = au_hf_top(file); -+ err = au_do_aio(h_file, MAY_READ, kio, iov, nv, pos); -+ /* todo: necessary? */ -+ /* file->f_ra = h_file->f_ra; */ -+ fsstack_copy_attr_atime(dentry->d_inode, h_file->f_dentry->d_inode); -+ di_read_unlock(dentry, AuLock_IR); -+ fi_read_unlock(file); -+ -+out: -+ si_read_unlock(sb); -+ return err; -+} -+ -+static ssize_t aufs_aio_write(struct kiocb *kio, const struct iovec *iov, -+ unsigned long nv, loff_t pos) -+{ -+ ssize_t err; -+ struct au_pin pin; -+ struct dentry *dentry; -+ struct inode *inode; -+ struct file *file, *h_file; -+ -+ file = kio->ki_filp; -+ dentry = file->f_dentry; -+ inode = dentry->d_inode; -+ au_mtx_and_read_lock(inode); -+ -+ err = au_reval_and_lock_fdi(file, au_reopen_nondir, /*wlock*/1); -+ if (unlikely(err)) -+ goto out; -+ -+ err = au_ready_to_write(file, -1, &pin); -+ di_downgrade_lock(dentry, AuLock_IR); -+ if (unlikely(err)) -+ goto out_unlock; -+ -+ au_unpin(&pin); -+ h_file = au_hf_top(file); -+ err = au_do_aio(h_file, MAY_WRITE, kio, iov, nv, pos); -+ au_cpup_attr_timesizes(inode); -+ inode->i_mode = h_file->f_dentry->d_inode->i_mode; -+ -+out_unlock: -+ di_read_unlock(dentry, AuLock_IR); -+ fi_write_unlock(file); -+out: -+ si_read_unlock(inode->i_sb); -+ mutex_unlock(&inode->i_mutex); -+ return err; -+} -+ -+static ssize_t aufs_splice_read(struct file *file, loff_t *ppos, -+ struct pipe_inode_info *pipe, size_t len, -+ unsigned int flags) -+{ -+ ssize_t err; -+ struct file *h_file; -+ struct dentry *dentry; -+ struct super_block *sb; -+ -+ dentry = file->f_dentry; -+ sb = dentry->d_sb; -+ si_read_lock(sb, AuLock_FLUSH | AuLock_NOPLMW); -+ err = au_reval_and_lock_fdi(file, au_reopen_nondir, /*wlock*/0); -+ if (unlikely(err)) -+ goto out; -+ -+ err = -EINVAL; -+ h_file = au_hf_top(file); -+ if (au_test_loopback_kthread()) { -+ file->f_mapping = h_file->f_mapping; -+ smp_mb(); /* unnecessary? */ -+ } -+ err = vfsub_splice_to(h_file, ppos, pipe, len, flags); -+ /* todo: necessasry? */ -+ /* file->f_ra = h_file->f_ra; */ -+ fsstack_copy_attr_atime(dentry->d_inode, h_file->f_dentry->d_inode); -+ -+ di_read_unlock(dentry, AuLock_IR); -+ fi_read_unlock(file); -+ -+out: -+ si_read_unlock(sb); -+ return err; -+} -+ -+static ssize_t -+aufs_splice_write(struct pipe_inode_info *pipe, struct file *file, loff_t *ppos, -+ size_t len, unsigned int flags) -+{ -+ ssize_t err; -+ struct au_pin pin; -+ struct dentry *dentry; -+ struct inode *inode; -+ struct file *h_file; -+ -+ dentry = file->f_dentry; -+ inode = dentry->d_inode; -+ au_mtx_and_read_lock(inode); -+ err = au_reval_and_lock_fdi(file, au_reopen_nondir, /*wlock*/1); -+ if (unlikely(err)) -+ goto out; -+ -+ err = au_ready_to_write(file, -1, &pin); -+ di_downgrade_lock(dentry, AuLock_IR); -+ if (unlikely(err)) -+ goto out_unlock; -+ -+ h_file = au_hf_top(file); -+ au_unpin(&pin); -+ err = vfsub_splice_from(pipe, h_file, ppos, len, flags); -+ au_cpup_attr_timesizes(inode); -+ inode->i_mode = h_file->f_dentry->d_inode->i_mode; -+ -+out_unlock: -+ di_read_unlock(dentry, AuLock_IR); -+ fi_write_unlock(file); -+out: -+ si_read_unlock(inode->i_sb); -+ mutex_unlock(&inode->i_mutex); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static struct file *au_safe_file(struct vm_area_struct *vma) -+{ -+ struct file *file; -+ -+ file = vma->vm_file; -+ if (au_fi(file) && au_test_aufs(file->f_dentry->d_sb)) -+ return file; -+ return NULL; -+} -+ -+static void au_reset_file(struct vm_area_struct *vma, struct file *file) -+{ -+ vma->vm_file = file; -+ /* smp_mb(); */ /* flush vm_file */ -+} -+ -+static int aufs_fault(struct vm_area_struct *vma, struct vm_fault *vmf) -+{ -+ int err; -+ static DECLARE_WAIT_QUEUE_HEAD(wq); -+ struct file *file, *h_file; -+ struct au_finfo *finfo; -+ -+ /* todo: non-robr mode, user vm_file as it is? */ -+ wait_event(wq, (file = au_safe_file(vma))); -+ -+ /* do not revalidate, no si lock */ -+ finfo = au_fi(file); -+ AuDebugOn(finfo->fi_hdir); -+ h_file = finfo->fi_htop.hf_file; -+ AuDebugOn(!h_file || !finfo->fi_hvmop); -+ -+ mutex_lock(&finfo->fi_vm_mtx); -+ vma->vm_file = h_file; -+ err = finfo->fi_hvmop->fault(vma, vmf); -+ /* todo: necessary? */ -+ /* file->f_ra = h_file->f_ra; */ -+ au_reset_file(vma, file); -+ mutex_unlock(&finfo->fi_vm_mtx); -+#if 0 /* def CONFIG_SMP */ -+ /* wake_up_nr(&wq, online_cpu - 1); */ -+ wake_up_all(&wq); -+#else -+ wake_up(&wq); -+#endif -+ -+ return err; -+} -+ -+static int aufs_page_mkwrite(struct vm_area_struct *vma, struct vm_fault *vmf) -+{ -+ int err; -+ static DECLARE_WAIT_QUEUE_HEAD(wq); -+ struct file *file, *h_file; -+ struct au_finfo *finfo; -+ -+ wait_event(wq, (file = au_safe_file(vma))); -+ -+ finfo = au_fi(file); -+ AuDebugOn(finfo->fi_hdir); -+ h_file = finfo->fi_htop.hf_file; -+ AuDebugOn(!h_file || !finfo->fi_hvmop); -+ -+ mutex_lock(&finfo->fi_vm_mtx); -+ vma->vm_file = h_file; -+ err = finfo->fi_hvmop->page_mkwrite(vma, vmf); -+ au_reset_file(vma, file); -+ mutex_unlock(&finfo->fi_vm_mtx); -+ wake_up(&wq); -+ -+ return err; -+} -+ -+static void aufs_vm_close(struct vm_area_struct *vma) -+{ -+ static DECLARE_WAIT_QUEUE_HEAD(wq); -+ struct file *file, *h_file; -+ struct au_finfo *finfo; -+ -+ wait_event(wq, (file = au_safe_file(vma))); -+ -+ finfo = au_fi(file); -+ AuDebugOn(finfo->fi_hdir); -+ h_file = finfo->fi_htop.hf_file; -+ AuDebugOn(!h_file || !finfo->fi_hvmop); -+ -+ mutex_lock(&finfo->fi_vm_mtx); -+ vma->vm_file = h_file; -+ finfo->fi_hvmop->close(vma); -+ au_reset_file(vma, file); -+ mutex_unlock(&finfo->fi_vm_mtx); -+ wake_up(&wq); -+} -+ -+const struct vm_operations_struct aufs_vm_ops = { -+ .close = aufs_vm_close, -+ .fault = aufs_fault, -+ .page_mkwrite = aufs_page_mkwrite -+}; -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* cf. linux/include/linux/mman.h: calc_vm_prot_bits() */ -+#define AuConv_VM_PROT(f, b) _calc_vm_trans(f, VM_##b, PROT_##b) -+ -+static unsigned long au_arch_prot_conv(unsigned long flags) -+{ -+ /* currently ppc64 only */ -+#ifdef CONFIG_PPC64 -+ /* cf. linux/arch/powerpc/include/asm/mman.h */ -+ AuDebugOn(arch_calc_vm_prot_bits(-1) != VM_SAO); -+ return AuConv_VM_PROT(flags, SAO); -+#else -+ AuDebugOn(arch_calc_vm_prot_bits(-1)); -+ return 0; -+#endif -+} -+ -+static unsigned long au_prot_conv(unsigned long flags) -+{ -+ return AuConv_VM_PROT(flags, READ) -+ | AuConv_VM_PROT(flags, WRITE) -+ | AuConv_VM_PROT(flags, EXEC) -+ | au_arch_prot_conv(flags); -+} -+ -+/* cf. linux/include/linux/mman.h: calc_vm_flag_bits() */ -+#define AuConv_VM_MAP(f, b) _calc_vm_trans(f, VM_##b, MAP_##b) -+ -+static unsigned long au_flag_conv(unsigned long flags) -+{ -+ return AuConv_VM_MAP(flags, GROWSDOWN) -+ | AuConv_VM_MAP(flags, DENYWRITE) -+ | AuConv_VM_MAP(flags, EXECUTABLE) -+ | AuConv_VM_MAP(flags, LOCKED); -+} -+ -+static struct vm_operations_struct * -+au_hvmop(struct file *h_file, struct vm_area_struct *vma, unsigned long *flags) -+{ -+ struct vm_operations_struct *h_vmop; -+ unsigned long prot; -+ int err; -+ -+ h_vmop = ERR_PTR(-ENODEV); -+ if (!h_file->f_op || !h_file->f_op->mmap) -+ goto out; -+ -+ prot = au_prot_conv(vma->vm_flags); -+ err = security_file_mmap(h_file, /*reqprot*/prot, prot, -+ au_flag_conv(vma->vm_flags), vma->vm_start, 0); -+ h_vmop = ERR_PTR(err); -+ if (unlikely(err)) -+ goto out; -+ -+ err = h_file->f_op->mmap(h_file, vma); -+ h_vmop = ERR_PTR(err); -+ if (unlikely(err)) -+ goto out; -+ -+ /* oops, it became 'const' */ -+ h_vmop = (struct vm_operations_struct *)vma->vm_ops; -+ *flags = vma->vm_flags; -+ err = do_munmap(current->mm, vma->vm_start, -+ vma->vm_end - vma->vm_start); -+ if (unlikely(err)) { -+ AuIOErr("failed internal unmapping %.*s, %d\n", -+ AuDLNPair(h_file->f_dentry), err); -+ h_vmop = ERR_PTR(-EIO); -+ } -+ -+out: -+ return h_vmop; -+} -+ -+/* -+ * This is another ugly approach to keep the lock order, particularly -+ * mm->mmap_sem and aufs rwsem. The previous approach was reverted and you can -+ * find it in git-log, if you want. -+ * -+ * native readdir: i_mutex, copy_to_user, mmap_sem -+ * aufs readdir: i_mutex, rwsem, nested-i_mutex, copy_to_user, mmap_sem -+ * -+ * Before aufs_mmap() mmap_sem is acquired already, but aufs_mmap() has to -+ * acquire aufs rwsem. It introduces a circular locking dependency. -+ * To address this problem, aufs_mmap() delegates the part which requires aufs -+ * rwsem to its internal workqueue. -+ */ -+ -+/* very ugly approach */ -+#include "mtx.h" -+ -+struct au_mmap_pre_args { -+ /* input */ -+ struct file *file; -+ struct vm_area_struct *vma; -+ -+ /* output */ -+ int *errp; -+ struct file *h_file; -+ struct au_branch *br; -+ int mmapped; -+}; -+ -+static int au_mmap_pre(struct file *file, struct vm_area_struct *vma, -+ struct file **h_file, struct au_branch **br, -+ int *mmapped) -+{ -+ int err; -+ aufs_bindex_t bstart; -+ const unsigned char wlock -+ = !!(file->f_mode & FMODE_WRITE) && (vma->vm_flags & VM_SHARED); -+ struct dentry *dentry; -+ struct super_block *sb; -+ -+ dentry = file->f_dentry; -+ sb = dentry->d_sb; -+ si_read_lock(sb, AuLock_NOPLMW); -+ err = au_reval_and_lock_fdi(file, au_reopen_nondir, /*wlock*/1); -+ if (unlikely(err)) -+ goto out; -+ -+ *mmapped = !!au_test_mmapped(file); -+ if (wlock) { -+ struct au_pin pin; -+ -+ err = au_ready_to_write(file, -1, &pin); -+ di_write_unlock(dentry); -+ if (unlikely(err)) -+ goto out_unlock; -+ au_unpin(&pin); -+ } else -+ di_write_unlock(dentry); -+ bstart = au_fbstart(file); -+ *br = au_sbr(sb, bstart); -+ *h_file = au_hf_top(file); -+ get_file(*h_file); -+ au_fi_mmap_lock(file); -+ -+out_unlock: -+ fi_write_unlock(file); -+out: -+ si_read_unlock(sb); -+ return err; -+} -+ -+static void au_call_mmap_pre(void *args) -+{ -+ struct au_mmap_pre_args *a = args; -+ *a->errp = au_mmap_pre(a->file, a->vma, &a->h_file, &a->br, -+ &a->mmapped); -+} -+ -+static int aufs_mmap(struct file *file, struct vm_area_struct *vma) -+{ -+ int err, wkq_err; -+ unsigned long h_vmflags; -+ struct au_finfo *finfo; -+ struct dentry *h_dentry; -+ struct vm_operations_struct *h_vmop, *vmop; -+ struct au_mmap_pre_args args = { -+ .file = file, -+ .vma = vma, -+ .errp = &err -+ }; -+ -+ wkq_err = au_wkq_wait_pre(au_call_mmap_pre, &args); -+ if (unlikely(wkq_err)) -+ err = wkq_err; -+ if (unlikely(err)) -+ goto out; -+ finfo = au_fi(file); -+ mutex_set_owner(&finfo->fi_mmap); -+ -+ h_dentry = args.h_file->f_dentry; -+ if (!args.mmapped && au_test_fs_bad_mapping(h_dentry->d_sb)) { -+ /* -+ * by this assignment, f_mapping will differs from aufs inode -+ * i_mapping. -+ * if someone else mixes the use of f_dentry->d_inode and -+ * f_mapping->host, then a problem may arise. -+ */ -+ file->f_mapping = args.h_file->f_mapping; -+ } -+ -+ /* always try this internal mmap to get vma flags */ -+ h_vmflags = 0; /* gcc warning */ -+ h_vmop = au_hvmop(args.h_file, vma, &h_vmflags); -+ err = PTR_ERR(h_vmop); -+ if (IS_ERR(h_vmop)) -+ goto out_unlock; -+ AuDebugOn(args.mmapped && h_vmop != finfo->fi_hvmop); -+ -+ vmop = (void *)au_dy_vmop(file, args.br, h_vmop); -+ err = PTR_ERR(vmop); -+ if (IS_ERR(vmop)) -+ goto out_unlock; -+ -+ /* -+ * unnecessary to handle MAP_DENYWRITE and deny_write_access()? -+ * currently MAP_DENYWRITE from userspace is ignored, but elf loader -+ * sets it. when FMODE_EXEC is set (by open_exec() or sys_uselib()), -+ * both of the aufs file and the lower file is deny_write_access()-ed. -+ * finally I hope we can skip handlling MAP_DENYWRITE here. -+ */ -+ err = generic_file_mmap(file, vma); -+ if (unlikely(err)) -+ goto out_unlock; -+ -+ vma->vm_ops = vmop; -+ vma->vm_flags = h_vmflags; -+ if (!args.mmapped) -+ finfo->fi_hvmop = h_vmop; -+ -+ vfsub_file_accessed(args.h_file); -+ /* update without lock, I don't think it a problem */ -+ fsstack_copy_attr_atime(file->f_dentry->d_inode, h_dentry->d_inode); -+ -+out_unlock: -+ au_fi_mmap_unlock(file); -+ fput(args.h_file); -+out: -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int aufs_fsync_nondir(struct file *file, int datasync) -+{ -+ int err; -+ struct au_pin pin; -+ struct dentry *dentry; -+ struct inode *inode; -+ struct file *h_file; -+ struct super_block *sb; -+ -+ dentry = file->f_dentry; -+ inode = dentry->d_inode; -+ IMustLock(file->f_mapping->host); -+ if (inode != file->f_mapping->host) { -+ mutex_unlock(&file->f_mapping->host->i_mutex); -+ mutex_lock(&inode->i_mutex); -+ } -+ IMustLock(inode); -+ -+ sb = dentry->d_sb; -+ err = si_read_lock(sb, AuLock_FLUSH | AuLock_NOPLM); -+ if (unlikely(err)) -+ goto out; -+ -+ err = 0; /* -EBADF; */ /* posix? */ -+ if (unlikely(!(file->f_mode & FMODE_WRITE))) -+ goto out_si; -+ err = au_reval_and_lock_fdi(file, au_reopen_nondir, /*wlock*/1); -+ if (unlikely(err)) -+ goto out_si; -+ -+ err = au_ready_to_write(file, -1, &pin); -+ di_downgrade_lock(dentry, AuLock_IR); -+ if (unlikely(err)) -+ goto out_unlock; -+ au_unpin(&pin); -+ -+ err = -EINVAL; -+ h_file = au_hf_top(file); -+ if (h_file->f_op && h_file->f_op->fsync) { -+ struct mutex *h_mtx; -+ -+ /* -+ * no filemap_fdatawrite() since aufs file has no its own -+ * mapping, but dir. -+ */ -+ h_mtx = &h_file->f_dentry->d_inode->i_mutex; -+ mutex_lock_nested(h_mtx, AuLsc_I_CHILD); -+ err = h_file->f_op->fsync(h_file, datasync); -+ if (!err) -+ vfsub_update_h_iattr(&h_file->f_path, /*did*/NULL); -+ /*ignore*/ -+ au_cpup_attr_timesizes(inode); -+ mutex_unlock(h_mtx); -+ } -+ -+out_unlock: -+ di_read_unlock(dentry, AuLock_IR); -+ fi_write_unlock(file); -+out_si: -+ si_read_unlock(sb); -+out: -+ if (inode != file->f_mapping->host) { -+ mutex_unlock(&inode->i_mutex); -+ mutex_lock(&file->f_mapping->host->i_mutex); -+ } -+ return err; -+} -+ -+/* no one supports this operation, currently */ -+#if 0 -+static int aufs_aio_fsync_nondir(struct kiocb *kio, int datasync) -+{ -+ int err; -+ struct au_pin pin; -+ struct dentry *dentry; -+ struct inode *inode; -+ struct file *file, *h_file; -+ -+ file = kio->ki_filp; -+ dentry = file->f_dentry; -+ inode = dentry->d_inode; -+ au_mtx_and_read_lock(inode); -+ -+ err = 0; /* -EBADF; */ /* posix? */ -+ if (unlikely(!(file->f_mode & FMODE_WRITE))) -+ goto out; -+ err = au_reval_and_lock_fdi(file, au_reopen_nondir, /*wlock*/1); -+ if (unlikely(err)) -+ goto out; -+ -+ err = au_ready_to_write(file, -1, &pin); -+ di_downgrade_lock(dentry, AuLock_IR); -+ if (unlikely(err)) -+ goto out_unlock; -+ au_unpin(&pin); -+ -+ err = -ENOSYS; -+ h_file = au_hf_top(file); -+ if (h_file->f_op && h_file->f_op->aio_fsync) { -+ struct dentry *h_d; -+ struct mutex *h_mtx; -+ -+ h_d = h_file->f_dentry; -+ h_mtx = &h_d->d_inode->i_mutex; -+ if (!is_sync_kiocb(kio)) { -+ get_file(h_file); -+ fput(file); -+ } -+ kio->ki_filp = h_file; -+ err = h_file->f_op->aio_fsync(kio, datasync); -+ mutex_lock_nested(h_mtx, AuLsc_I_CHILD); -+ if (!err) -+ vfsub_update_h_iattr(&h_file->f_path, /*did*/NULL); -+ /*ignore*/ -+ au_cpup_attr_timesizes(inode); -+ mutex_unlock(h_mtx); -+ } -+ -+out_unlock: -+ di_read_unlock(dentry, AuLock_IR); -+ fi_write_unlock(file); -+out: -+ si_read_unlock(inode->sb); -+ mutex_unlock(&inode->i_mutex); -+ return err; -+} -+#endif -+ -+static int aufs_fasync(int fd, struct file *file, int flag) -+{ -+ int err; -+ struct file *h_file; -+ struct dentry *dentry; -+ struct super_block *sb; -+ -+ dentry = file->f_dentry; -+ sb = dentry->d_sb; -+ si_read_lock(sb, AuLock_FLUSH | AuLock_NOPLMW); -+ err = au_reval_and_lock_fdi(file, au_reopen_nondir, /*wlock*/0); -+ if (unlikely(err)) -+ goto out; -+ -+ h_file = au_hf_top(file); -+ if (h_file->f_op && h_file->f_op->fasync) -+ err = h_file->f_op->fasync(fd, h_file, flag); -+ -+ di_read_unlock(dentry, AuLock_IR); -+ fi_read_unlock(file); -+ -+out: -+ si_read_unlock(sb); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* no one supports this operation, currently */ -+#if 0 -+static ssize_t aufs_sendpage(struct file *file, struct page *page, int offset, -+ size_t len, loff_t *pos , int more) -+{ -+} -+#endif -+ -+/* ---------------------------------------------------------------------- */ -+ -+const struct file_operations aufs_file_fop = { -+ .owner = THIS_MODULE, -+ /* -+ * while generic_file_llseek/_unlocked() don't use BKL, -+ * don't use it since it operates file->f_mapping->host. -+ * in aufs, it may be a real file and may confuse users by UDBA. -+ */ -+ /* .llseek = generic_file_llseek, */ -+ -+ .read = aufs_read, -+ .write = aufs_write, -+ .aio_read = aufs_aio_read, -+ .aio_write = aufs_aio_write, -+#ifdef CONFIG_AUFS_POLL -+ .poll = aufs_poll, -+#endif -+ .unlocked_ioctl = aufs_ioctl_nondir, -+#ifdef CONFIG_COMPAT -+ .compat_ioctl = aufs_ioctl_nondir, /* same */ -+#endif -+ .mmap = aufs_mmap, -+ .open = aufs_open_nondir, -+ .flush = aufs_flush_nondir, -+ .release = aufs_release_nondir, -+ .fsync = aufs_fsync_nondir, -+ /* .aio_fsync = aufs_aio_fsync_nondir, */ -+ .fasync = aufs_fasync, -+ /* .sendpage = aufs_sendpage, */ -+ .splice_write = aufs_splice_write, -+ .splice_read = aufs_splice_read, -+#if 0 -+ .aio_splice_write = aufs_aio_splice_write, -+ .aio_splice_read = aufs_aio_splice_read -+#endif -+}; -diff -Nur linux-2.6.37.orig/fs/aufs/f_op_sp.c linux-2.6.37/fs/aufs/f_op_sp.c ---- linux-2.6.37.orig/fs/aufs/f_op_sp.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/f_op_sp.c 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,299 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * file operations for special files. -+ * while they exist in aufs virtually, -+ * their file I/O is handled out of aufs. -+ */ -+ -+#include -+#include "aufs.h" -+ -+static ssize_t aufs_aio_read_sp(struct kiocb *kio, const struct iovec *iov, -+ unsigned long nv, loff_t pos) -+{ -+ ssize_t err; -+ aufs_bindex_t bstart; -+ unsigned char wbr; -+ struct file *file, *h_file; -+ struct super_block *sb; -+ -+ file = kio->ki_filp; -+ sb = file->f_dentry->d_sb; -+ si_read_lock(sb, AuLock_FLUSH); -+ fi_read_lock(file); -+ bstart = au_fbstart(file); -+ h_file = au_hf_top(file); -+ fi_read_unlock(file); -+ wbr = !!au_br_writable(au_sbr(sb, bstart)->br_perm); -+ si_read_unlock(sb); -+ -+ /* do not change the file in kio */ -+ AuDebugOn(!h_file->f_op || !h_file->f_op->aio_read); -+ err = h_file->f_op->aio_read(kio, iov, nv, pos); -+ if (err > 0 && wbr) -+ file_accessed(h_file); -+ -+ return err; -+} -+ -+static ssize_t aufs_aio_write_sp(struct kiocb *kio, const struct iovec *iov, -+ unsigned long nv, loff_t pos) -+{ -+ ssize_t err; -+ aufs_bindex_t bstart; -+ unsigned char wbr; -+ struct super_block *sb; -+ struct file *file, *h_file; -+ -+ file = kio->ki_filp; -+ sb = file->f_dentry->d_sb; -+ si_read_lock(sb, AuLock_FLUSH); -+ fi_read_lock(file); -+ bstart = au_fbstart(file); -+ h_file = au_hf_top(file); -+ fi_read_unlock(file); -+ wbr = !!au_br_writable(au_sbr(sb, bstart)->br_perm); -+ si_read_unlock(sb); -+ -+ /* do not change the file in kio */ -+ AuDebugOn(!h_file->f_op || !h_file->f_op->aio_write); -+ err = h_file->f_op->aio_write(kio, iov, nv, pos); -+ if (err > 0 && wbr) -+ file_update_time(h_file); -+ -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int aufs_release_sp(struct inode *inode, struct file *file) -+{ -+ int err; -+ struct file *h_file; -+ -+ fi_read_lock(file); -+ h_file = au_hf_top(file); -+ fi_read_unlock(file); -+ /* close this fifo in aufs */ -+ err = h_file->f_op->release(inode, file); /* ignore */ -+ aufs_release_nondir(inode, file); /* ignore */ -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* currently, support only FIFO */ -+enum { -+ AuSp_FIFO, AuSp_FIFO_R, AuSp_FIFO_W, AuSp_FIFO_RW, -+ /* AuSp_SOCK, AuSp_CHR, AuSp_BLK, */ -+ AuSp_Last -+}; -+static int aufs_open_sp(struct inode *inode, struct file *file); -+static struct au_sp_fop { -+ int done; -+ struct file_operations fop; /* not 'const' */ -+ spinlock_t spin; -+} au_sp_fop[AuSp_Last] = { -+ [AuSp_FIFO] = { -+ .fop = { -+ .owner = THIS_MODULE, -+ .open = aufs_open_sp -+ } -+ } -+}; -+ -+static void au_init_fop_sp(struct file *file) -+{ -+ struct au_sp_fop *p; -+ int i; -+ struct file *h_file; -+ -+ p = au_sp_fop; -+ if (unlikely(!p->done)) { -+ /* initialize first time only */ -+ static DEFINE_SPINLOCK(spin); -+ -+ spin_lock(&spin); -+ if (!p->done) { -+ BUILD_BUG_ON(sizeof(au_sp_fop)/sizeof(*au_sp_fop) -+ != AuSp_Last); -+ for (i = 0; i < AuSp_Last; i++) -+ spin_lock_init(&p[i].spin); -+ p->done = 1; -+ } -+ spin_unlock(&spin); -+ } -+ -+ switch (file->f_mode & (FMODE_READ | FMODE_WRITE)) { -+ case FMODE_READ: -+ i = AuSp_FIFO_R; -+ break; -+ case FMODE_WRITE: -+ i = AuSp_FIFO_W; -+ break; -+ case FMODE_READ | FMODE_WRITE: -+ i = AuSp_FIFO_RW; -+ break; -+ default: -+ BUG(); -+ } -+ -+ p += i; -+ if (unlikely(!p->done)) { -+ /* initialize first time only */ -+ h_file = au_hf_top(file); -+ spin_lock(&p->spin); -+ if (!p->done) { -+ p->fop = *h_file->f_op; -+ p->fop.owner = THIS_MODULE; -+ if (p->fop.aio_read) -+ p->fop.aio_read = aufs_aio_read_sp; -+ if (p->fop.aio_write) -+ p->fop.aio_write = aufs_aio_write_sp; -+ p->fop.release = aufs_release_sp; -+ p->done = 1; -+ } -+ spin_unlock(&p->spin); -+ } -+ file->f_op = &p->fop; -+} -+ -+static int au_cpup_sp(struct dentry *dentry) -+{ -+ int err; -+ aufs_bindex_t bcpup; -+ struct au_pin pin; -+ struct au_wr_dir_args wr_dir_args = { -+ .force_btgt = -1, -+ .flags = 0 -+ }; -+ -+ AuDbg("%.*s\n", AuDLNPair(dentry)); -+ -+ di_read_unlock(dentry, AuLock_IR); -+ di_write_lock_child(dentry); -+ err = au_wr_dir(dentry, /*src_dentry*/NULL, &wr_dir_args); -+ if (unlikely(err < 0)) -+ goto out; -+ bcpup = err; -+ err = 0; -+ if (bcpup == au_dbstart(dentry)) -+ goto out; /* success */ -+ -+ err = au_pin(&pin, dentry, bcpup, au_opt_udba(dentry->d_sb), -+ AuPin_MNT_WRITE); -+ if (!err) { -+ err = au_sio_cpup_simple(dentry, bcpup, -1, AuCpup_DTIME); -+ au_unpin(&pin); -+ } -+ -+out: -+ di_downgrade_lock(dentry, AuLock_IR); -+ return err; -+} -+ -+static int au_do_open_sp(struct file *file, int flags) -+{ -+ int err; -+ struct dentry *dentry; -+ struct super_block *sb; -+ struct file *h_file; -+ struct inode *h_inode; -+ -+ dentry = file->f_dentry; -+ AuDbg("%.*s\n", AuDLNPair(dentry)); -+ -+ /* -+ * try copying-up. -+ * operate on the ro branch is not an error. -+ */ -+ au_cpup_sp(dentry); /* ignore */ -+ -+ /* prepare h_file */ -+ err = au_do_open_nondir(file, vfsub_file_flags(file)); -+ if (unlikely(err)) -+ goto out; -+ -+ sb = dentry->d_sb; -+ h_file = au_hf_top(file); -+ h_inode = h_file->f_dentry->d_inode; -+ di_read_unlock(dentry, AuLock_IR); -+ fi_write_unlock(file); -+ si_read_unlock(sb); -+ /* open this fifo in aufs */ -+ err = h_inode->i_fop->open(file->f_dentry->d_inode, file); -+ si_noflush_read_lock(sb); -+ fi_write_lock(file); -+ di_read_lock_child(dentry, AuLock_IR); -+ if (!err) -+ au_init_fop_sp(file); -+ -+out: -+ return err; -+} -+ -+static int aufs_open_sp(struct inode *inode, struct file *file) -+{ -+ int err; -+ struct super_block *sb; -+ -+ sb = file->f_dentry->d_sb; -+ si_read_lock(sb, AuLock_FLUSH); -+ err = au_do_open(file, au_do_open_sp, /*fidir*/NULL); -+ si_read_unlock(sb); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+void au_init_special_fop(struct inode *inode, umode_t mode, dev_t rdev) -+{ -+ init_special_inode(inode, mode, rdev); -+ -+ switch (mode & S_IFMT) { -+ case S_IFIFO: -+ inode->i_fop = &au_sp_fop[AuSp_FIFO].fop; -+ /*FALLTHROUGH*/ -+ case S_IFCHR: -+ case S_IFBLK: -+ case S_IFSOCK: -+ break; -+ default: -+ AuDebugOn(1); -+ } -+} -+ -+int au_special_file(umode_t mode) -+{ -+ int ret; -+ -+ ret = 0; -+ switch (mode & S_IFMT) { -+ case S_IFIFO: -+#if 0 -+ case S_IFCHR: -+ case S_IFBLK: -+ case S_IFSOCK: -+#endif -+ ret = 1; -+ } -+ -+ return ret; -+} -diff -Nur linux-2.6.37.orig/fs/aufs/file.c linux-2.6.37/fs/aufs/file.c ---- linux-2.6.37.orig/fs/aufs/file.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/file.c 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,676 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * handling file/dir, and address_space operation -+ */ -+ -+#include -+#include -+#include -+#include -+#include "aufs.h" -+ -+/* drop flags for writing */ -+unsigned int au_file_roflags(unsigned int flags) -+{ -+ flags &= ~(O_WRONLY | O_RDWR | O_APPEND | O_CREAT | O_TRUNC); -+ flags |= O_RDONLY | O_NOATIME; -+ return flags; -+} -+ -+/* common functions to regular file and dir */ -+struct file *au_h_open(struct dentry *dentry, aufs_bindex_t bindex, int flags, -+ struct file *file) -+{ -+ struct file *h_file; -+ struct dentry *h_dentry; -+ struct inode *h_inode; -+ struct super_block *sb; -+ struct au_branch *br; -+ struct path h_path; -+ int err, exec_flag; -+ -+ /* a race condition can happen between open and unlink/rmdir */ -+ h_file = ERR_PTR(-ENOENT); -+ h_dentry = au_h_dptr(dentry, bindex); -+ if (au_test_nfsd() && !h_dentry) -+ goto out; -+ h_inode = h_dentry->d_inode; -+ if (au_test_nfsd() && !h_inode) -+ goto out; -+ if (unlikely((!d_unhashed(dentry) && au_d_removed(h_dentry)) -+ || !h_inode -+ /* || !dentry->d_inode->i_nlink */ -+ )) -+ goto out; -+ -+ sb = dentry->d_sb; -+ br = au_sbr(sb, bindex); -+ h_file = ERR_PTR(-EACCES); -+ exec_flag = flags & vfsub_fmode_to_uint(FMODE_EXEC); -+ if (exec_flag && (br->br_mnt->mnt_flags & MNT_NOEXEC)) -+ goto out; -+ -+ /* drop flags for writing */ -+ if (au_test_ro(sb, bindex, dentry->d_inode)) -+ flags = au_file_roflags(flags); -+ flags &= ~O_CREAT; -+ atomic_inc(&br->br_count); -+ h_path.dentry = h_dentry; -+ h_path.mnt = br->br_mnt; -+ if (!au_special_file(h_inode->i_mode)) -+ h_file = vfsub_dentry_open(&h_path, flags); -+ else { -+ /* this block depends upon the configuration */ -+ di_read_unlock(dentry, AuLock_IR); -+ fi_write_unlock(file); -+ si_read_unlock(sb); -+ h_file = vfsub_dentry_open(&h_path, flags); -+ si_noflush_read_lock(sb); -+ fi_write_lock(file); -+ di_read_lock_child(dentry, AuLock_IR); -+ } -+ if (IS_ERR(h_file)) -+ goto out_br; -+ -+ if (exec_flag) { -+ err = deny_write_access(h_file); -+ if (unlikely(err)) { -+ fput(h_file); -+ h_file = ERR_PTR(err); -+ goto out_br; -+ } -+ } -+ fsnotify_open(h_file); -+ goto out; /* success */ -+ -+out_br: -+ atomic_dec(&br->br_count); -+out: -+ return h_file; -+} -+ -+int au_do_open(struct file *file, int (*open)(struct file *file, int flags), -+ struct au_fidir *fidir) -+{ -+ int err; -+ struct dentry *dentry; -+ -+ err = au_finfo_init(file, fidir); -+ if (unlikely(err)) -+ goto out; -+ -+ dentry = file->f_dentry; -+ di_read_lock_child(dentry, AuLock_IR); -+ err = open(file, vfsub_file_flags(file)); -+ di_read_unlock(dentry, AuLock_IR); -+ -+ fi_write_unlock(file); -+ if (unlikely(err)) { -+ au_fi(file)->fi_hdir = NULL; -+ au_finfo_fin(file); -+ } -+ -+out: -+ return err; -+} -+ -+int au_reopen_nondir(struct file *file) -+{ -+ int err; -+ aufs_bindex_t bstart; -+ struct dentry *dentry; -+ struct file *h_file, *h_file_tmp; -+ -+ dentry = file->f_dentry; -+ AuDebugOn(au_special_file(dentry->d_inode->i_mode)); -+ bstart = au_dbstart(dentry); -+ h_file_tmp = NULL; -+ if (au_fbstart(file) == bstart) { -+ h_file = au_hf_top(file); -+ if (file->f_mode == h_file->f_mode) -+ return 0; /* success */ -+ h_file_tmp = h_file; -+ get_file(h_file_tmp); -+ au_set_h_fptr(file, bstart, NULL); -+ } -+ AuDebugOn(au_fi(file)->fi_hdir); -+ AuDebugOn(au_fbstart(file) < bstart); -+ -+ h_file = au_h_open(dentry, bstart, vfsub_file_flags(file) & ~O_TRUNC, -+ file); -+ err = PTR_ERR(h_file); -+ if (IS_ERR(h_file)) -+ goto out; /* todo: close all? */ -+ -+ err = 0; -+ au_set_fbstart(file, bstart); -+ au_set_h_fptr(file, bstart, h_file); -+ au_update_figen(file); -+ /* todo: necessary? */ -+ /* file->f_ra = h_file->f_ra; */ -+ -+out: -+ if (h_file_tmp) -+ fput(h_file_tmp); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int au_reopen_wh(struct file *file, aufs_bindex_t btgt, -+ struct dentry *hi_wh) -+{ -+ int err; -+ aufs_bindex_t bstart; -+ struct au_dinfo *dinfo; -+ struct dentry *h_dentry; -+ struct au_hdentry *hdp; -+ -+ dinfo = au_di(file->f_dentry); -+ AuRwMustWriteLock(&dinfo->di_rwsem); -+ -+ bstart = dinfo->di_bstart; -+ dinfo->di_bstart = btgt; -+ hdp = dinfo->di_hdentry; -+ h_dentry = hdp[0 + btgt].hd_dentry; -+ hdp[0 + btgt].hd_dentry = hi_wh; -+ err = au_reopen_nondir(file); -+ hdp[0 + btgt].hd_dentry = h_dentry; -+ dinfo->di_bstart = bstart; -+ -+ return err; -+} -+ -+static int au_ready_to_write_wh(struct file *file, loff_t len, -+ aufs_bindex_t bcpup) -+{ -+ int err; -+ struct inode *inode, *h_inode; -+ struct dentry *dentry, *h_dentry, *hi_wh; -+ -+ dentry = file->f_dentry; -+ au_update_dbstart(dentry); -+ inode = dentry->d_inode; -+ h_inode = NULL; -+ if (au_dbstart(dentry) <= bcpup && au_dbend(dentry) >= bcpup) { -+ h_dentry = au_h_dptr(dentry, bcpup); -+ if (h_dentry) -+ h_inode = h_dentry->d_inode; -+ } -+ hi_wh = au_hi_wh(inode, bcpup); -+ if (!hi_wh && !h_inode) -+ err = au_sio_cpup_wh(dentry, bcpup, len, file); -+ else -+ /* already copied-up after unlink */ -+ err = au_reopen_wh(file, bcpup, hi_wh); -+ -+ if (!err -+ && inode->i_nlink > 1 -+ && au_opt_test(au_mntflags(dentry->d_sb), PLINK)) -+ au_plink_append(inode, bcpup, au_h_dptr(dentry, bcpup)); -+ -+ return err; -+} -+ -+/* -+ * prepare the @file for writing. -+ */ -+int au_ready_to_write(struct file *file, loff_t len, struct au_pin *pin) -+{ -+ int err; -+ aufs_bindex_t bstart, bcpup, dbstart; -+ struct dentry *dentry, *parent, *h_dentry; -+ struct inode *h_inode, *inode; -+ struct super_block *sb; -+ struct file *h_file; -+ -+ dentry = file->f_dentry; -+ sb = dentry->d_sb; -+ inode = dentry->d_inode; -+ AuDebugOn(au_special_file(inode->i_mode)); -+ bstart = au_fbstart(file); -+ err = au_test_ro(sb, bstart, inode); -+ if (!err && (au_hf_top(file)->f_mode & FMODE_WRITE)) { -+ err = au_pin(pin, dentry, bstart, AuOpt_UDBA_NONE, /*flags*/0); -+ goto out; -+ } -+ -+ /* need to cpup or reopen */ -+ parent = dget_parent(dentry); -+ di_write_lock_parent(parent); -+ err = AuWbrCopyup(au_sbi(sb), dentry); -+ bcpup = err; -+ if (unlikely(err < 0)) -+ goto out_dgrade; -+ err = 0; -+ -+ if (!d_unhashed(dentry) && !au_h_dptr(parent, bcpup)) { -+ err = au_cpup_dirs(dentry, bcpup); -+ if (unlikely(err)) -+ goto out_dgrade; -+ } -+ -+ err = au_pin(pin, dentry, bcpup, AuOpt_UDBA_NONE, -+ AuPin_DI_LOCKED | AuPin_MNT_WRITE); -+ if (unlikely(err)) -+ goto out_dgrade; -+ -+ h_dentry = au_hf_top(file)->f_dentry; -+ h_inode = h_dentry->d_inode; -+ dbstart = au_dbstart(dentry); -+ if (dbstart <= bcpup) { -+ h_dentry = au_h_dptr(dentry, bcpup); -+ AuDebugOn(!h_dentry); -+ h_inode = h_dentry->d_inode; -+ AuDebugOn(!h_inode); -+ bstart = bcpup; -+ } -+ -+ if (dbstart <= bcpup /* just reopen */ -+ || !d_unhashed(dentry) /* copyup and reopen */ -+ ) { -+ mutex_lock_nested(&h_inode->i_mutex, AuLsc_I_CHILD); -+ h_file = au_h_open_pre(dentry, bstart); -+ if (IS_ERR(h_file)) { -+ err = PTR_ERR(h_file); -+ h_file = NULL; -+ } else { -+ di_downgrade_lock(parent, AuLock_IR); -+ if (dbstart > bcpup) -+ err = au_sio_cpup_simple(dentry, bcpup, len, -+ AuCpup_DTIME); -+ if (!err) -+ err = au_reopen_nondir(file); -+ } -+ mutex_unlock(&h_inode->i_mutex); -+ au_h_open_post(dentry, bstart, h_file); -+ } else { /* copyup as wh and reopen */ -+ /* -+ * since writable hfsplus branch is not supported, -+ * h_open_pre/post() are unnecessary. -+ */ -+ mutex_lock_nested(&h_inode->i_mutex, AuLsc_I_CHILD); -+ err = au_ready_to_write_wh(file, len, bcpup); -+ di_downgrade_lock(parent, AuLock_IR); -+ mutex_unlock(&h_inode->i_mutex); -+ } -+ -+ if (!err) { -+ au_pin_set_parent_lflag(pin, /*lflag*/0); -+ goto out_dput; /* success */ -+ } -+ au_unpin(pin); -+ goto out_unlock; -+ -+out_dgrade: -+ di_downgrade_lock(parent, AuLock_IR); -+out_unlock: -+ di_read_unlock(parent, AuLock_IR); -+out_dput: -+ dput(parent); -+out: -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+int au_do_flush(struct file *file, fl_owner_t id, -+ int (*flush)(struct file *file, fl_owner_t id)) -+{ -+ int err; -+ struct dentry *dentry; -+ struct super_block *sb; -+ struct inode *inode; -+ -+ dentry = file->f_dentry; -+ sb = dentry->d_sb; -+ inode = dentry->d_inode; -+ si_noflush_read_lock(sb); -+ fi_read_lock(file); -+ ii_read_lock_child(inode); -+ -+ err = flush(file, id); -+ au_cpup_attr_timesizes(inode); -+ -+ ii_read_unlock(inode); -+ fi_read_unlock(file); -+ si_read_unlock(sb); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int au_file_refresh_by_inode(struct file *file, int *need_reopen) -+{ -+ int err; -+ aufs_bindex_t bstart; -+ struct au_pin pin; -+ struct au_finfo *finfo; -+ struct dentry *dentry, *parent, *hi_wh; -+ struct inode *inode; -+ struct super_block *sb; -+ -+ FiMustWriteLock(file); -+ -+ err = 0; -+ finfo = au_fi(file); -+ dentry = file->f_dentry; -+ sb = dentry->d_sb; -+ inode = dentry->d_inode; -+ bstart = au_ibstart(inode); -+ if (bstart == finfo->fi_btop || IS_ROOT(dentry)) -+ goto out; -+ -+ parent = dget_parent(dentry); -+ if (au_test_ro(sb, bstart, inode)) { -+ di_read_lock_parent(parent, !AuLock_IR); -+ err = AuWbrCopyup(au_sbi(sb), dentry); -+ bstart = err; -+ di_read_unlock(parent, !AuLock_IR); -+ if (unlikely(err < 0)) -+ goto out_parent; -+ err = 0; -+ } -+ -+ di_read_lock_parent(parent, AuLock_IR); -+ hi_wh = au_hi_wh(inode, bstart); -+ if (!S_ISDIR(inode->i_mode) -+ && au_opt_test(au_mntflags(sb), PLINK) -+ && au_plink_test(inode) -+ && !d_unhashed(dentry)) { -+ err = au_test_and_cpup_dirs(dentry, bstart); -+ if (unlikely(err)) -+ goto out_unlock; -+ -+ /* always superio. */ -+ err = au_pin(&pin, dentry, bstart, AuOpt_UDBA_NONE, -+ AuPin_DI_LOCKED | AuPin_MNT_WRITE); -+ if (!err) -+ err = au_sio_cpup_simple(dentry, bstart, -1, -+ AuCpup_DTIME); -+ au_unpin(&pin); -+ } else if (hi_wh) { -+ /* already copied-up after unlink */ -+ err = au_reopen_wh(file, bstart, hi_wh); -+ *need_reopen = 0; -+ } -+ -+out_unlock: -+ di_read_unlock(parent, AuLock_IR); -+out_parent: -+ dput(parent); -+out: -+ return err; -+} -+ -+static void au_do_refresh_dir(struct file *file) -+{ -+ aufs_bindex_t bindex, bend, new_bindex, brid; -+ struct au_hfile *p, tmp, *q; -+ struct au_finfo *finfo; -+ struct super_block *sb; -+ struct au_fidir *fidir; -+ -+ FiMustWriteLock(file); -+ -+ sb = file->f_dentry->d_sb; -+ finfo = au_fi(file); -+ fidir = finfo->fi_hdir; -+ AuDebugOn(!fidir); -+ p = fidir->fd_hfile + finfo->fi_btop; -+ brid = p->hf_br->br_id; -+ bend = fidir->fd_bbot; -+ for (bindex = finfo->fi_btop; bindex <= bend; bindex++, p++) { -+ if (!p->hf_file) -+ continue; -+ -+ new_bindex = au_br_index(sb, p->hf_br->br_id); -+ if (new_bindex == bindex) -+ continue; -+ if (new_bindex < 0) { -+ au_set_h_fptr(file, bindex, NULL); -+ continue; -+ } -+ -+ /* swap two lower inode, and loop again */ -+ q = fidir->fd_hfile + new_bindex; -+ tmp = *q; -+ *q = *p; -+ *p = tmp; -+ if (tmp.hf_file) { -+ bindex--; -+ p--; -+ } -+ } -+ -+ p = fidir->fd_hfile; -+ if (!au_test_mmapped(file) && !au_d_removed(file->f_dentry)) { -+ bend = au_sbend(sb); -+ for (finfo->fi_btop = 0; finfo->fi_btop <= bend; -+ finfo->fi_btop++, p++) -+ if (p->hf_file) { -+ if (p->hf_file->f_dentry -+ && p->hf_file->f_dentry->d_inode) -+ break; -+ else -+ au_hfput(p, file); -+ } -+ } else { -+ bend = au_br_index(sb, brid); -+ for (finfo->fi_btop = 0; finfo->fi_btop < bend; -+ finfo->fi_btop++, p++) -+ if (p->hf_file) -+ au_hfput(p, file); -+ bend = au_sbend(sb); -+ } -+ -+ p = fidir->fd_hfile + bend; -+ for (fidir->fd_bbot = bend; fidir->fd_bbot >= finfo->fi_btop; -+ fidir->fd_bbot--, p--) -+ if (p->hf_file) { -+ if (p->hf_file->f_dentry -+ && p->hf_file->f_dentry->d_inode) -+ break; -+ else -+ au_hfput(p, file); -+ } -+ AuDebugOn(fidir->fd_bbot < finfo->fi_btop); -+} -+ -+/* -+ * after branch manipulating, refresh the file. -+ */ -+static int refresh_file(struct file *file, int (*reopen)(struct file *file)) -+{ -+ int err, need_reopen; -+ aufs_bindex_t bend, bindex; -+ struct dentry *dentry; -+ struct au_finfo *finfo; -+ struct au_hfile *hfile; -+ -+ dentry = file->f_dentry; -+ finfo = au_fi(file); -+ if (!finfo->fi_hdir) { -+ hfile = &finfo->fi_htop; -+ AuDebugOn(!hfile->hf_file); -+ bindex = au_br_index(dentry->d_sb, hfile->hf_br->br_id); -+ AuDebugOn(bindex < 0); -+ if (bindex != finfo->fi_btop) -+ au_set_fbstart(file, bindex); -+ } else { -+ err = au_fidir_realloc(finfo, au_sbend(dentry->d_sb) + 1); -+ if (unlikely(err)) -+ goto out; -+ au_do_refresh_dir(file); -+ } -+ -+ err = 0; -+ need_reopen = 1; -+ if (!au_test_mmapped(file)) -+ err = au_file_refresh_by_inode(file, &need_reopen); -+ if (!err && need_reopen && !au_d_removed(dentry)) -+ err = reopen(file); -+ if (!err) { -+ au_update_figen(file); -+ goto out; /* success */ -+ } -+ -+ /* error, close all lower files */ -+ if (finfo->fi_hdir) { -+ bend = au_fbend_dir(file); -+ for (bindex = au_fbstart(file); bindex <= bend; bindex++) -+ au_set_h_fptr(file, bindex, NULL); -+ } -+ -+out: -+ return err; -+} -+ -+/* common function to regular file and dir */ -+int au_reval_and_lock_fdi(struct file *file, int (*reopen)(struct file *file), -+ int wlock) -+{ -+ int err; -+ unsigned int sigen, figen; -+ aufs_bindex_t bstart; -+ unsigned char pseudo_link; -+ struct dentry *dentry; -+ struct inode *inode; -+ -+ err = 0; -+ dentry = file->f_dentry; -+ inode = dentry->d_inode; -+ AuDebugOn(au_special_file(inode->i_mode)); -+ sigen = au_sigen(dentry->d_sb); -+ fi_write_lock(file); -+ figen = au_figen(file); -+ di_write_lock_child(dentry); -+ bstart = au_dbstart(dentry); -+ pseudo_link = (bstart != au_ibstart(inode)); -+ if (sigen == figen && !pseudo_link && au_fbstart(file) == bstart) { -+ if (!wlock) { -+ di_downgrade_lock(dentry, AuLock_IR); -+ fi_downgrade_lock(file); -+ } -+ goto out; /* success */ -+ } -+ -+ AuDbg("sigen %d, figen %d\n", sigen, figen); -+ if (au_digen_test(dentry, sigen)) { -+ err = au_reval_dpath(dentry, sigen); -+ AuDebugOn(!err && au_digen_test(dentry, sigen)); -+ } -+ -+ if (!err) -+ err = refresh_file(file, reopen); -+ if (!err) { -+ if (!wlock) { -+ di_downgrade_lock(dentry, AuLock_IR); -+ fi_downgrade_lock(file); -+ } -+ } else { -+ di_write_unlock(dentry); -+ fi_write_unlock(file); -+ } -+ -+out: -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* cf. aufs_nopage() */ -+/* for madvise(2) */ -+static int aufs_readpage(struct file *file __maybe_unused, struct page *page) -+{ -+ unlock_page(page); -+ return 0; -+} -+ -+/* it will never be called, but necessary to support O_DIRECT */ -+static ssize_t aufs_direct_IO(int rw, struct kiocb *iocb, -+ const struct iovec *iov, loff_t offset, -+ unsigned long nr_segs) -+{ BUG(); return 0; } -+ -+/* -+ * it will never be called, but madvise and fadvise behaves differently -+ * when get_xip_mem is defined -+ */ -+static int aufs_get_xip_mem(struct address_space *mapping, pgoff_t pgoff, -+ int create, void **kmem, unsigned long *pfn) -+{ BUG(); return 0; } -+ -+/* they will never be called. */ -+#ifdef CONFIG_AUFS_DEBUG -+static int aufs_write_begin(struct file *file, struct address_space *mapping, -+ loff_t pos, unsigned len, unsigned flags, -+ struct page **pagep, void **fsdata) -+{ AuUnsupport(); return 0; } -+static int aufs_write_end(struct file *file, struct address_space *mapping, -+ loff_t pos, unsigned len, unsigned copied, -+ struct page *page, void *fsdata) -+{ AuUnsupport(); return 0; } -+static int aufs_writepage(struct page *page, struct writeback_control *wbc) -+{ AuUnsupport(); return 0; } -+static void aufs_sync_page(struct page *page) -+{ AuUnsupport(); } -+ -+static int aufs_set_page_dirty(struct page *page) -+{ AuUnsupport(); return 0; } -+static void aufs_invalidatepage(struct page *page, unsigned long offset) -+{ AuUnsupport(); } -+static int aufs_releasepage(struct page *page, gfp_t gfp) -+{ AuUnsupport(); return 0; } -+static int aufs_migratepage(struct address_space *mapping, struct page *newpage, -+ struct page *page) -+{ AuUnsupport(); return 0; } -+static int aufs_launder_page(struct page *page) -+{ AuUnsupport(); return 0; } -+static int aufs_is_partially_uptodate(struct page *page, -+ read_descriptor_t *desc, -+ unsigned long from) -+{ AuUnsupport(); return 0; } -+static int aufs_error_remove_page(struct address_space *mapping, -+ struct page *page) -+{ AuUnsupport(); return 0; } -+#endif /* CONFIG_AUFS_DEBUG */ -+ -+const struct address_space_operations aufs_aop = { -+ .readpage = aufs_readpage, -+ .direct_IO = aufs_direct_IO, -+ .get_xip_mem = aufs_get_xip_mem, -+#ifdef CONFIG_AUFS_DEBUG -+ .writepage = aufs_writepage, -+ .sync_page = aufs_sync_page, -+ /* no writepages, because of writepage */ -+ .set_page_dirty = aufs_set_page_dirty, -+ /* no readpages, because of readpage */ -+ .write_begin = aufs_write_begin, -+ .write_end = aufs_write_end, -+ /* no bmap, no block device */ -+ .invalidatepage = aufs_invalidatepage, -+ .releasepage = aufs_releasepage, -+ .migratepage = aufs_migratepage, -+ .launder_page = aufs_launder_page, -+ .is_partially_uptodate = aufs_is_partially_uptodate, -+ .error_remove_page = aufs_error_remove_page -+#endif /* CONFIG_AUFS_DEBUG */ -+}; -diff -Nur linux-2.6.37.orig/fs/aufs/file.h linux-2.6.37/fs/aufs/file.h ---- linux-2.6.37.orig/fs/aufs/file.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/file.h 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,238 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * file operations -+ */ -+ -+#ifndef __AUFS_FILE_H__ -+#define __AUFS_FILE_H__ -+ -+#ifdef __KERNEL__ -+ -+#include -+#include -+#include -+#include "rwsem.h" -+ -+struct au_branch; -+struct au_hfile { -+ struct file *hf_file; -+ struct au_branch *hf_br; -+}; -+ -+struct au_vdir; -+struct au_fidir { -+ aufs_bindex_t fd_bbot; -+ aufs_bindex_t fd_nent; -+ struct au_vdir *fd_vdir_cache; -+ struct au_hfile fd_hfile[]; -+}; -+ -+static inline int au_fidir_sz(int nent) -+{ -+ AuDebugOn(nent < 0); -+ return sizeof(struct au_fidir) + sizeof(struct au_hfile) * nent; -+} -+ -+struct au_finfo { -+ atomic_t fi_generation; -+ -+ struct au_rwsem fi_rwsem; -+ aufs_bindex_t fi_btop; -+ -+ /* do not union them */ -+ struct { /* for non-dir */ -+ struct au_hfile fi_htop; -+ struct vm_operations_struct *fi_hvmop; -+ struct mutex fi_vm_mtx; -+ struct mutex fi_mmap; -+ }; -+ struct au_fidir *fi_hdir; /* for dir only */ -+} ____cacheline_aligned_in_smp; -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* file.c */ -+extern const struct address_space_operations aufs_aop; -+unsigned int au_file_roflags(unsigned int flags); -+struct file *au_h_open(struct dentry *dentry, aufs_bindex_t bindex, int flags, -+ struct file *file); -+int au_do_open(struct file *file, int (*open)(struct file *file, int flags), -+ struct au_fidir *fidir); -+int au_reopen_nondir(struct file *file); -+struct au_pin; -+int au_ready_to_write(struct file *file, loff_t len, struct au_pin *pin); -+int au_reval_and_lock_fdi(struct file *file, int (*reopen)(struct file *file), -+ int wlock); -+int au_do_flush(struct file *file, fl_owner_t id, -+ int (*flush)(struct file *file, fl_owner_t id)); -+ -+/* poll.c */ -+#ifdef CONFIG_AUFS_POLL -+unsigned int aufs_poll(struct file *file, poll_table *wait); -+#endif -+ -+#ifdef CONFIG_AUFS_BR_HFSPLUS -+/* hfsplus.c */ -+struct file *au_h_open_pre(struct dentry *dentry, aufs_bindex_t bindex); -+void au_h_open_post(struct dentry *dentry, aufs_bindex_t bindex, -+ struct file *h_file); -+#else -+static inline -+struct file *au_h_open_pre(struct dentry *dentry, aufs_bindex_t bindex) -+{ -+ return NULL; -+} -+ -+AuStubVoid(au_h_open_post, struct dentry *dentry, aufs_bindex_t bindex, -+ struct file *h_file); -+#endif -+ -+/* f_op.c */ -+extern const struct file_operations aufs_file_fop; -+extern const struct vm_operations_struct aufs_vm_ops; -+int au_do_open_nondir(struct file *file, int flags); -+int aufs_release_nondir(struct inode *inode __maybe_unused, struct file *file); -+ -+#ifdef CONFIG_AUFS_SP_IATTR -+/* f_op_sp.c */ -+int au_special_file(umode_t mode); -+void au_init_special_fop(struct inode *inode, umode_t mode, dev_t rdev); -+#else -+AuStubInt0(au_special_file, umode_t mode) -+static inline void au_init_special_fop(struct inode *inode, umode_t mode, -+ dev_t rdev) -+{ -+ init_special_inode(inode, mode, rdev); -+} -+#endif -+ -+/* finfo.c */ -+void au_hfput(struct au_hfile *hf, struct file *file); -+void au_set_h_fptr(struct file *file, aufs_bindex_t bindex, -+ struct file *h_file); -+ -+void au_update_figen(struct file *file); -+void au_fi_mmap_lock(struct file *file); -+void au_fi_mmap_unlock(struct file *file); -+struct au_fidir *au_fidir_alloc(struct super_block *sb); -+int au_fidir_realloc(struct au_finfo *finfo, int nbr); -+ -+void au_fi_init_once(void *_fi); -+void au_finfo_fin(struct file *file); -+int au_finfo_init(struct file *file, struct au_fidir *fidir); -+ -+/* ioctl.c */ -+long aufs_ioctl_nondir(struct file *file, unsigned int cmd, unsigned long arg); -+#ifdef CONFIG_COMPAT -+long aufs_compat_ioctl_dir(struct file *file, unsigned int cmd, -+ unsigned long arg); -+#endif -+ -+/* ---------------------------------------------------------------------- */ -+ -+static inline struct au_finfo *au_fi(struct file *file) -+{ -+ return file->private_data; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * fi_read_lock, fi_write_lock, -+ * fi_read_unlock, fi_write_unlock, fi_downgrade_lock -+ */ -+AuSimpleRwsemFuncs(fi, struct file *f, &au_fi(f)->fi_rwsem); -+ -+#define FiMustNoWaiters(f) AuRwMustNoWaiters(&au_fi(f)->fi_rwsem) -+#define FiMustAnyLock(f) AuRwMustAnyLock(&au_fi(f)->fi_rwsem) -+#define FiMustWriteLock(f) AuRwMustWriteLock(&au_fi(f)->fi_rwsem) -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* todo: hard/soft set? */ -+static inline aufs_bindex_t au_fbstart(struct file *file) -+{ -+ FiMustAnyLock(file); -+ return au_fi(file)->fi_btop; -+} -+ -+static inline aufs_bindex_t au_fbend_dir(struct file *file) -+{ -+ FiMustAnyLock(file); -+ AuDebugOn(!au_fi(file)->fi_hdir); -+ return au_fi(file)->fi_hdir->fd_bbot; -+} -+ -+static inline struct au_vdir *au_fvdir_cache(struct file *file) -+{ -+ FiMustAnyLock(file); -+ AuDebugOn(!au_fi(file)->fi_hdir); -+ return au_fi(file)->fi_hdir->fd_vdir_cache; -+} -+ -+static inline void au_set_fbstart(struct file *file, aufs_bindex_t bindex) -+{ -+ FiMustWriteLock(file); -+ au_fi(file)->fi_btop = bindex; -+} -+ -+static inline void au_set_fbend_dir(struct file *file, aufs_bindex_t bindex) -+{ -+ FiMustWriteLock(file); -+ AuDebugOn(!au_fi(file)->fi_hdir); -+ au_fi(file)->fi_hdir->fd_bbot = bindex; -+} -+ -+static inline void au_set_fvdir_cache(struct file *file, -+ struct au_vdir *vdir_cache) -+{ -+ FiMustWriteLock(file); -+ AuDebugOn(!au_fi(file)->fi_hdir); -+ au_fi(file)->fi_hdir->fd_vdir_cache = vdir_cache; -+} -+ -+static inline struct file *au_hf_top(struct file *file) -+{ -+ FiMustAnyLock(file); -+ AuDebugOn(au_fi(file)->fi_hdir); -+ return au_fi(file)->fi_htop.hf_file; -+} -+ -+static inline struct file *au_hf_dir(struct file *file, aufs_bindex_t bindex) -+{ -+ FiMustAnyLock(file); -+ AuDebugOn(!au_fi(file)->fi_hdir); -+ return au_fi(file)->fi_hdir->fd_hfile[0 + bindex].hf_file; -+} -+ -+/* todo: memory barrier? */ -+static inline unsigned int au_figen(struct file *f) -+{ -+ return atomic_read(&au_fi(f)->fi_generation); -+} -+ -+static inline int au_test_mmapped(struct file *f) -+{ -+ FiMustAnyLock(f); -+ return !!(au_fi(f)->fi_hvmop); -+} -+ -+#endif /* __KERNEL__ */ -+#endif /* __AUFS_FILE_H__ */ -diff -Nur linux-2.6.37.orig/fs/aufs/finfo.c linux-2.6.37/fs/aufs/finfo.c ---- linux-2.6.37.orig/fs/aufs/finfo.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/finfo.c 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,174 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * file private data -+ */ -+ -+#include -+#include "aufs.h" -+ -+void au_hfput(struct au_hfile *hf, struct file *file) -+{ -+ /* todo: direct access f_flags */ -+ if (vfsub_file_flags(file) & vfsub_fmode_to_uint(FMODE_EXEC)) -+ allow_write_access(hf->hf_file); -+ fput(hf->hf_file); -+ hf->hf_file = NULL; -+ atomic_dec(&hf->hf_br->br_count); -+ hf->hf_br = NULL; -+} -+ -+void au_set_h_fptr(struct file *file, aufs_bindex_t bindex, struct file *val) -+{ -+ struct au_finfo *finfo = au_fi(file); -+ struct au_hfile *hf; -+ struct au_fidir *fidir; -+ -+ fidir = finfo->fi_hdir; -+ if (!fidir) { -+ AuDebugOn(finfo->fi_btop != bindex); -+ hf = &finfo->fi_htop; -+ } else -+ hf = fidir->fd_hfile + bindex; -+ -+ if (hf && hf->hf_file) -+ au_hfput(hf, file); -+ if (val) { -+ FiMustWriteLock(file); -+ hf->hf_file = val; -+ hf->hf_br = au_sbr(file->f_dentry->d_sb, bindex); -+ } -+} -+ -+void au_update_figen(struct file *file) -+{ -+ atomic_set(&au_fi(file)->fi_generation, au_digen(file->f_dentry)); -+ /* smp_mb(); */ /* atomic_set */ -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+void au_fi_mmap_lock(struct file *file) -+{ -+ FiMustWriteLock(file); -+ lockdep_off(); -+ mutex_lock(&au_fi(file)->fi_mmap); -+ lockdep_on(); -+} -+ -+void au_fi_mmap_unlock(struct file *file) -+{ -+ lockdep_off(); -+ mutex_unlock(&au_fi(file)->fi_mmap); -+ lockdep_on(); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+struct au_fidir *au_fidir_alloc(struct super_block *sb) -+{ -+ struct au_fidir *fidir; -+ int nbr; -+ -+ nbr = au_sbend(sb) + 1; -+ if (nbr < 2) -+ nbr = 2; /* initial allocate for 2 branches */ -+ fidir = kzalloc(au_fidir_sz(nbr), GFP_NOFS); -+ if (fidir) { -+ fidir->fd_bbot = -1; -+ fidir->fd_nent = nbr; -+ fidir->fd_vdir_cache = NULL; -+ } -+ -+ return fidir; -+} -+ -+int au_fidir_realloc(struct au_finfo *finfo, int nbr) -+{ -+ int err; -+ struct au_fidir *fidir, *p; -+ -+ AuRwMustWriteLock(&finfo->fi_rwsem); -+ fidir = finfo->fi_hdir; -+ AuDebugOn(!fidir); -+ -+ err = -ENOMEM; -+ p = au_kzrealloc(fidir, au_fidir_sz(fidir->fd_nent), au_fidir_sz(nbr), -+ GFP_NOFS); -+ if (p) { -+ p->fd_nent = nbr; -+ finfo->fi_hdir = p; -+ err = 0; -+ } -+ -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+void au_finfo_fin(struct file *file) -+{ -+ struct au_finfo *finfo; -+ -+ au_nfiles_dec(file->f_dentry->d_sb); -+ -+ finfo = au_fi(file); -+ AuDebugOn(finfo->fi_hdir); -+ AuRwDestroy(&finfo->fi_rwsem); -+ au_cache_free_finfo(finfo); -+} -+ -+void au_fi_init_once(void *_finfo) -+{ -+ struct au_finfo *finfo = _finfo; -+ static struct lock_class_key aufs_fi, aufs_fi_vm, aufs_fi_mmap; -+ -+ au_rw_init(&finfo->fi_rwsem); -+ au_rw_class(&finfo->fi_rwsem, &aufs_fi); -+ mutex_init(&finfo->fi_vm_mtx); -+ lockdep_set_class(&finfo->fi_vm_mtx, &aufs_fi_vm); -+ mutex_init(&finfo->fi_mmap); -+ lockdep_set_class(&finfo->fi_mmap, &aufs_fi_mmap); -+} -+ -+int au_finfo_init(struct file *file, struct au_fidir *fidir) -+{ -+ int err; -+ struct au_finfo *finfo; -+ struct dentry *dentry; -+ -+ err = -ENOMEM; -+ dentry = file->f_dentry; -+ finfo = au_cache_alloc_finfo(); -+ if (unlikely(!finfo)) -+ goto out; -+ -+ err = 0; -+ au_nfiles_inc(dentry->d_sb); -+ au_rw_write_lock(&finfo->fi_rwsem); -+ finfo->fi_btop = -1; -+ finfo->fi_hdir = fidir; -+ atomic_set(&finfo->fi_generation, au_digen(dentry)); -+ /* smp_mb(); */ /* atomic_set */ -+ -+ file->private_data = finfo; -+ -+out: -+ return err; -+} -diff -Nur linux-2.6.37.orig/fs/aufs/fstype.h linux-2.6.37/fs/aufs/fstype.h ---- linux-2.6.37.orig/fs/aufs/fstype.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/fstype.h 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,497 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * judging filesystem type -+ */ -+ -+#ifndef __AUFS_FSTYPE_H__ -+#define __AUFS_FSTYPE_H__ -+ -+#ifdef __KERNEL__ -+ -+#include -+#include -+#include -+#include -+ -+static inline int au_test_aufs(struct super_block *sb) -+{ -+ return sb->s_magic == AUFS_SUPER_MAGIC; -+} -+ -+static inline const char *au_sbtype(struct super_block *sb) -+{ -+ return sb->s_type->name; -+} -+ -+static inline int au_test_iso9660(struct super_block *sb __maybe_unused) -+{ -+#if defined(CONFIG_ROMFS_FS) || defined(CONFIG_ROMFS_FS_MODULE) -+ return sb->s_magic == ROMFS_MAGIC; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_romfs(struct super_block *sb __maybe_unused) -+{ -+#if defined(CONFIG_ISO9660_FS) || defined(CONFIG_ISO9660_FS_MODULE) -+ return sb->s_magic == ISOFS_SUPER_MAGIC; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_cramfs(struct super_block *sb __maybe_unused) -+{ -+#if defined(CONFIG_CRAMFS) || defined(CONFIG_CRAMFS_MODULE) -+ return sb->s_magic == CRAMFS_MAGIC; -+#endif -+ return 0; -+} -+ -+static inline int au_test_nfs(struct super_block *sb __maybe_unused) -+{ -+#if defined(CONFIG_NFS_FS) || defined(CONFIG_NFS_FS_MODULE) -+ return sb->s_magic == NFS_SUPER_MAGIC; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_fuse(struct super_block *sb __maybe_unused) -+{ -+#if defined(CONFIG_FUSE_FS) || defined(CONFIG_FUSE_FS_MODULE) -+ return sb->s_magic == FUSE_SUPER_MAGIC; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_xfs(struct super_block *sb __maybe_unused) -+{ -+#if defined(CONFIG_XFS_FS) || defined(CONFIG_XFS_FS_MODULE) -+ return sb->s_magic == XFS_SB_MAGIC; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_tmpfs(struct super_block *sb __maybe_unused) -+{ -+#ifdef CONFIG_TMPFS -+ return sb->s_magic == TMPFS_MAGIC; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_ecryptfs(struct super_block *sb __maybe_unused) -+{ -+#if defined(CONFIG_ECRYPT_FS) || defined(CONFIG_ECRYPT_FS_MODULE) -+ return !strcmp(au_sbtype(sb), "ecryptfs"); -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_smbfs(struct super_block *sb __maybe_unused) -+{ -+#if defined(CONFIG_SMB_FS) || defined(CONFIG_SMB_FS_MODULE) -+ return sb->s_magic == SMB_SUPER_MAGIC; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_ocfs2(struct super_block *sb __maybe_unused) -+{ -+#if defined(CONFIG_OCFS2_FS) || defined(CONFIG_OCFS2_FS_MODULE) -+ return sb->s_magic == OCFS2_SUPER_MAGIC; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_ocfs2_dlmfs(struct super_block *sb __maybe_unused) -+{ -+#if defined(CONFIG_OCFS2_FS_O2CB) || defined(CONFIG_OCFS2_FS_O2CB_MODULE) -+ return sb->s_magic == DLMFS_MAGIC; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_coda(struct super_block *sb __maybe_unused) -+{ -+#if defined(CONFIG_CODA_FS) || defined(CONFIG_CODA_FS_MODULE) -+ return sb->s_magic == CODA_SUPER_MAGIC; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_v9fs(struct super_block *sb __maybe_unused) -+{ -+#if defined(CONFIG_9P_FS) || defined(CONFIG_9P_FS_MODULE) -+ return sb->s_magic == V9FS_MAGIC; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_ext4(struct super_block *sb __maybe_unused) -+{ -+#if defined(CONFIG_EXT4DEV_FS) || defined(CONFIG_EXT4DEV_FS_MODULE) -+ return sb->s_magic == EXT4_SUPER_MAGIC; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_sysv(struct super_block *sb __maybe_unused) -+{ -+#if defined(CONFIG_SYSV_FS) || defined(CONFIG_SYSV_FS_MODULE) -+ return !strcmp(au_sbtype(sb), "sysv"); -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_ramfs(struct super_block *sb) -+{ -+ return sb->s_magic == RAMFS_MAGIC; -+} -+ -+static inline int au_test_ubifs(struct super_block *sb __maybe_unused) -+{ -+#if defined(CONFIG_UBIFS_FS) || defined(CONFIG_UBIFS_FS_MODULE) -+ return sb->s_magic == UBIFS_SUPER_MAGIC; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_procfs(struct super_block *sb __maybe_unused) -+{ -+#ifdef CONFIG_PROC_FS -+ return sb->s_magic == PROC_SUPER_MAGIC; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_sysfs(struct super_block *sb __maybe_unused) -+{ -+#ifdef CONFIG_SYSFS -+ return sb->s_magic == SYSFS_MAGIC; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_configfs(struct super_block *sb __maybe_unused) -+{ -+#if defined(CONFIG_CONFIGFS_FS) || defined(CONFIG_CONFIGFS_FS_MODULE) -+ return sb->s_magic == CONFIGFS_MAGIC; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_minix(struct super_block *sb __maybe_unused) -+{ -+#if defined(CONFIG_MINIX_FS) || defined(CONFIG_MINIX_FS_MODULE) -+ return sb->s_magic == MINIX3_SUPER_MAGIC -+ || sb->s_magic == MINIX2_SUPER_MAGIC -+ || sb->s_magic == MINIX2_SUPER_MAGIC2 -+ || sb->s_magic == MINIX_SUPER_MAGIC -+ || sb->s_magic == MINIX_SUPER_MAGIC2; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_cifs(struct super_block *sb __maybe_unused) -+{ -+#if defined(CONFIG_CIFS_FS) || defined(CONFIGCIFS_FS_MODULE) -+ return sb->s_magic == CIFS_MAGIC_NUMBER; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_fat(struct super_block *sb __maybe_unused) -+{ -+#if defined(CONFIG_FAT_FS) || defined(CONFIG_FAT_FS_MODULE) -+ return sb->s_magic == MSDOS_SUPER_MAGIC; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_msdos(struct super_block *sb) -+{ -+ return au_test_fat(sb); -+} -+ -+static inline int au_test_vfat(struct super_block *sb) -+{ -+ return au_test_fat(sb); -+} -+ -+static inline int au_test_securityfs(struct super_block *sb __maybe_unused) -+{ -+#ifdef CONFIG_SECURITYFS -+ return sb->s_magic == SECURITYFS_MAGIC; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_squashfs(struct super_block *sb __maybe_unused) -+{ -+#if defined(CONFIG_SQUASHFS) || defined(CONFIG_SQUASHFS_MODULE) -+ return sb->s_magic == SQUASHFS_MAGIC; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_btrfs(struct super_block *sb __maybe_unused) -+{ -+#if defined(CONFIG_BTRFS_FS) || defined(CONFIG_BTRFS_FS_MODULE) -+ return sb->s_magic == BTRFS_SUPER_MAGIC; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_xenfs(struct super_block *sb __maybe_unused) -+{ -+#if defined(CONFIG_XENFS) || defined(CONFIG_XENFS_MODULE) -+ return sb->s_magic == XENFS_SUPER_MAGIC; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_debugfs(struct super_block *sb __maybe_unused) -+{ -+#ifdef CONFIG_DEBUG_FS -+ return sb->s_magic == DEBUGFS_MAGIC; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_nilfs(struct super_block *sb __maybe_unused) -+{ -+#if defined(CONFIG_NILFS) || defined(CONFIG_NILFS_MODULE) -+ return sb->s_magic == NILFS_SUPER_MAGIC; -+#else -+ return 0; -+#endif -+} -+ -+static inline int au_test_hfsplus(struct super_block *sb __maybe_unused) -+{ -+#if defined(CONFIG_HFSPLUS_FS) || defined(CONFIG_HFSPLUS_FS_MODULE) -+ return sb->s_magic == HFSPLUS_SUPER_MAGIC; -+#else -+ return 0; -+#endif -+} -+ -+/* ---------------------------------------------------------------------- */ -+/* -+ * they can't be an aufs branch. -+ */ -+static inline int au_test_fs_unsuppoted(struct super_block *sb) -+{ -+ return -+#ifndef CONFIG_AUFS_BR_RAMFS -+ au_test_ramfs(sb) || -+#endif -+ au_test_procfs(sb) -+ || au_test_sysfs(sb) -+ || au_test_configfs(sb) -+ || au_test_debugfs(sb) -+ || au_test_securityfs(sb) -+ || au_test_xenfs(sb) -+ || au_test_ecryptfs(sb) -+ /* || !strcmp(au_sbtype(sb), "unionfs") */ -+ || au_test_aufs(sb); /* will be supported in next version */ -+} -+ -+/* -+ * If the filesystem supports NFS-export, then it has to support NULL as -+ * a nameidata parameter for ->create(), ->lookup() and ->d_revalidate(). -+ * We can apply this principle when we handle a lower filesystem. -+ */ -+static inline int au_test_fs_null_nd(struct super_block *sb) -+{ -+ return !!sb->s_export_op; -+} -+ -+static inline int au_test_fs_remote(struct super_block *sb) -+{ -+ return !au_test_tmpfs(sb) -+#ifdef CONFIG_AUFS_BR_RAMFS -+ && !au_test_ramfs(sb) -+#endif -+ && !(sb->s_type->fs_flags & FS_REQUIRES_DEV); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * Note: these functions (below) are created after reading ->getattr() in all -+ * filesystems under linux/fs. it means we have to do so in every update... -+ */ -+ -+/* -+ * some filesystems require getattr to refresh the inode attributes before -+ * referencing. -+ * in most cases, we can rely on the inode attribute in NFS (or every remote fs) -+ * and leave the work for d_revalidate() -+ */ -+static inline int au_test_fs_refresh_iattr(struct super_block *sb) -+{ -+ return au_test_nfs(sb) -+ || au_test_fuse(sb) -+ /* || au_test_smbfs(sb) */ /* untested */ -+ /* || au_test_ocfs2(sb) */ /* untested */ -+ /* || au_test_btrfs(sb) */ /* untested */ -+ /* || au_test_coda(sb) */ /* untested */ -+ /* || au_test_v9fs(sb) */ /* untested */ -+ ; -+} -+ -+/* -+ * filesystems which don't maintain i_size or i_blocks. -+ */ -+static inline int au_test_fs_bad_iattr_size(struct super_block *sb) -+{ -+ return au_test_xfs(sb) -+ || au_test_btrfs(sb) -+ || au_test_ubifs(sb) -+ || au_test_hfsplus(sb) /* maintained, but incorrect */ -+ /* || au_test_ext4(sb) */ /* untested */ -+ /* || au_test_ocfs2(sb) */ /* untested */ -+ /* || au_test_ocfs2_dlmfs(sb) */ /* untested */ -+ /* || au_test_sysv(sb) */ /* untested */ -+ /* || au_test_minix(sb) */ /* untested */ -+ ; -+} -+ -+/* -+ * filesystems which don't store the correct value in some of their inode -+ * attributes. -+ */ -+static inline int au_test_fs_bad_iattr(struct super_block *sb) -+{ -+ return au_test_fs_bad_iattr_size(sb) -+ /* || au_test_cifs(sb) */ /* untested */ -+ || au_test_fat(sb) -+ || au_test_msdos(sb) -+ || au_test_vfat(sb); -+} -+ -+/* they don't check i_nlink in link(2) */ -+static inline int au_test_fs_no_limit_nlink(struct super_block *sb) -+{ -+ return au_test_tmpfs(sb) -+#ifdef CONFIG_AUFS_BR_RAMFS -+ || au_test_ramfs(sb) -+#endif -+ || au_test_ubifs(sb) -+ || au_test_btrfs(sb) -+ || au_test_hfsplus(sb); -+} -+ -+/* -+ * filesystems which sets S_NOATIME and S_NOCMTIME. -+ */ -+static inline int au_test_fs_notime(struct super_block *sb) -+{ -+ return au_test_nfs(sb) -+ || au_test_fuse(sb) -+ || au_test_ubifs(sb) -+ /* || au_test_cifs(sb) */ /* untested */ -+ ; -+} -+ -+/* -+ * filesystems which requires replacing i_mapping. -+ */ -+static inline int au_test_fs_bad_mapping(struct super_block *sb) -+{ -+ return au_test_fuse(sb) -+ || au_test_ubifs(sb); -+} -+ -+/* temporary support for i#1 in cramfs */ -+static inline int au_test_fs_unique_ino(struct inode *inode) -+{ -+ if (au_test_cramfs(inode->i_sb)) -+ return inode->i_ino != 1; -+ return 1; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * the filesystem where the xino files placed must support i/o after unlink and -+ * maintain i_size and i_blocks. -+ */ -+static inline int au_test_fs_bad_xino(struct super_block *sb) -+{ -+ return au_test_fs_remote(sb) -+ || au_test_fs_bad_iattr_size(sb) -+#ifdef CONFIG_AUFS_BR_RAMFS -+ || !(au_test_ramfs(sb) || au_test_fs_null_nd(sb)) -+#else -+ || !au_test_fs_null_nd(sb) /* to keep xino code simple */ -+#endif -+ /* don't want unnecessary work for xino */ -+ || au_test_aufs(sb) -+ || au_test_ecryptfs(sb) -+ || au_test_nilfs(sb); -+} -+ -+static inline int au_test_fs_trunc_xino(struct super_block *sb) -+{ -+ return au_test_tmpfs(sb) -+ || au_test_ramfs(sb); -+} -+ -+/* -+ * test if the @sb is real-readonly. -+ */ -+static inline int au_test_fs_rr(struct super_block *sb) -+{ -+ return au_test_squashfs(sb) -+ || au_test_iso9660(sb) -+ || au_test_cramfs(sb) -+ || au_test_romfs(sb); -+} -+ -+#endif /* __KERNEL__ */ -+#endif /* __AUFS_FSTYPE_H__ */ -diff -Nur linux-2.6.37.orig/fs/aufs/hfsnotify.c linux-2.6.37/fs/aufs/hfsnotify.c ---- linux-2.6.37.orig/fs/aufs/hfsnotify.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/hfsnotify.c 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,247 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * fsnotify for the lower directories -+ */ -+ -+#include "aufs.h" -+ -+/* FS_IN_IGNORED is unnecessary */ -+static const __u32 AuHfsnMask = (FS_MOVED_TO | FS_MOVED_FROM | FS_DELETE -+ | FS_CREATE | FS_EVENT_ON_CHILD); -+static DECLARE_WAIT_QUEUE_HEAD(au_hfsn_wq); -+ -+static void au_hfsn_free_mark(struct fsnotify_mark *mark) -+{ -+ struct au_hnotify *hn = container_of(mark, struct au_hnotify, -+ hn_mark); -+ AuDbg("here\n"); -+ hn->hn_mark_dead = 1; -+ smp_mb(); -+ wake_up_all(&au_hfsn_wq); -+} -+ -+static int au_hfsn_alloc(struct au_hinode *hinode) -+{ -+ struct au_hnotify *hn; -+ struct super_block *sb; -+ struct au_branch *br; -+ struct fsnotify_mark *mark; -+ aufs_bindex_t bindex; -+ -+ hn = hinode->hi_notify; -+ sb = hn->hn_aufs_inode->i_sb; -+ bindex = au_br_index(sb, hinode->hi_id); -+ br = au_sbr(sb, bindex); -+ hn->hn_mark_dead = 0; -+ mark = &hn->hn_mark; -+ fsnotify_init_mark(mark, au_hfsn_free_mark); -+ mark->mask = AuHfsnMask; -+ /* -+ * by udba rename or rmdir, aufs assign a new inode to the known -+ * h_inode, so specify 1 to allow dups. -+ */ -+ return fsnotify_add_mark(mark, br->br_hfsn_group, hinode->hi_inode, -+ /*mnt*/NULL, /*allow_dups*/1); -+} -+ -+static void au_hfsn_free(struct au_hinode *hinode) -+{ -+ struct au_hnotify *hn; -+ struct fsnotify_mark *mark; -+ -+ hn = hinode->hi_notify; -+ mark = &hn->hn_mark; -+ fsnotify_destroy_mark(mark); -+ fsnotify_put_mark(mark); -+ -+ /* TODO: bad approach */ -+ wait_event(au_hfsn_wq, hn->hn_mark_dead); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static void au_hfsn_ctl(struct au_hinode *hinode, int do_set) -+{ -+ struct fsnotify_mark *mark; -+ -+ mark = &hinode->hi_notify->hn_mark; -+ spin_lock(&mark->lock); -+ if (do_set) { -+ AuDebugOn(mark->mask & AuHfsnMask); -+ mark->mask |= AuHfsnMask; -+ } else { -+ AuDebugOn(!(mark->mask & AuHfsnMask)); -+ mark->mask &= ~AuHfsnMask; -+ } -+ spin_unlock(&mark->lock); -+ /* fsnotify_recalc_inode_mask(hinode->hi_inode); */ -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* #define AuDbgHnotify */ -+#ifdef AuDbgHnotify -+static char *au_hfsn_name(u32 mask) -+{ -+#ifdef CONFIG_AUFS_DEBUG -+#define test_ret(flag) if (mask & flag) \ -+ return #flag; -+ test_ret(FS_ACCESS); -+ test_ret(FS_MODIFY); -+ test_ret(FS_ATTRIB); -+ test_ret(FS_CLOSE_WRITE); -+ test_ret(FS_CLOSE_NOWRITE); -+ test_ret(FS_OPEN); -+ test_ret(FS_MOVED_FROM); -+ test_ret(FS_MOVED_TO); -+ test_ret(FS_CREATE); -+ test_ret(FS_DELETE); -+ test_ret(FS_DELETE_SELF); -+ test_ret(FS_MOVE_SELF); -+ test_ret(FS_UNMOUNT); -+ test_ret(FS_Q_OVERFLOW); -+ test_ret(FS_IN_IGNORED); -+ test_ret(FS_IN_ISDIR); -+ test_ret(FS_IN_ONESHOT); -+ test_ret(FS_EVENT_ON_CHILD); -+ return ""; -+#undef test_ret -+#else -+ return "??"; -+#endif -+} -+#endif -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int au_hfsn_handle_event(struct fsnotify_group *group, -+ struct fsnotify_mark *inode_mark, -+ struct fsnotify_mark *vfsmount_mark, -+ struct fsnotify_event *event) -+{ -+ int err; -+ struct au_hnotify *hnotify; -+ struct inode *h_dir, *h_inode; -+ __u32 mask; -+ struct qstr h_child_qstr = { -+ .name = event->file_name, -+ .len = event->name_len -+ }; -+ -+ AuDebugOn(event->data_type != FSNOTIFY_EVENT_INODE); -+ -+ err = 0; -+ /* if FS_UNMOUNT happens, there must be another bug */ -+ mask = event->mask; -+ AuDebugOn(mask & FS_UNMOUNT); -+ if (mask & (FS_IN_IGNORED | FS_UNMOUNT)) -+ goto out; -+ -+ h_dir = event->to_tell; -+ h_inode = event->inode; -+#ifdef AuDbgHnotify -+ au_debug(1); -+ if (1 || h_child_qstr.len != sizeof(AUFS_XINO_FNAME) - 1 -+ || strncmp(h_child_qstr.name, AUFS_XINO_FNAME, h_child_qstr.len)) { -+ AuDbg("i%lu, mask 0x%x %s, hcname %.*s, hi%lu\n", -+ h_dir->i_ino, mask, au_hfsn_name(mask), -+ AuLNPair(&h_child_qstr), h_inode ? h_inode->i_ino : 0); -+ /* WARN_ON(1); */ -+ } -+ au_debug(0); -+#endif -+ -+ AuDebugOn(!inode_mark); -+ hnotify = container_of(inode_mark, struct au_hnotify, hn_mark); -+ err = au_hnotify(h_dir, hnotify, mask, &h_child_qstr, h_inode); -+ -+out: -+ return err; -+} -+ -+/* isn't it waste to ask every registered 'group'? */ -+/* copied from linux/fs/notify/inotify/inotify_fsnotiry.c */ -+/* it should be exported to modules */ -+static bool au_hfsn_should_send_event(struct fsnotify_group *group, -+ struct inode *h_inode, -+ struct fsnotify_mark *inode_mark, -+ struct fsnotify_mark *vfsmount_mark, -+ __u32 mask, void *data, int data_type) -+{ -+ mask = (mask & ~FS_EVENT_ON_CHILD); -+ return inode_mark->mask & mask; -+} -+ -+static struct fsnotify_ops au_hfsn_ops = { -+ .should_send_event = au_hfsn_should_send_event, -+ .handle_event = au_hfsn_handle_event -+}; -+ -+/* ---------------------------------------------------------------------- */ -+ -+static void au_hfsn_fin_br(struct au_branch *br) -+{ -+ if (br->br_hfsn_group) -+ fsnotify_put_group(br->br_hfsn_group); -+} -+ -+static int au_hfsn_init_br(struct au_branch *br, int perm) -+{ -+ br->br_hfsn_group = NULL; -+ br->br_hfsn_ops = au_hfsn_ops; -+ return 0; -+} -+ -+static int au_hfsn_reset_br(unsigned int udba, struct au_branch *br, int perm) -+{ -+ int err; -+ -+ err = 0; -+ if (udba != AuOpt_UDBA_HNOTIFY -+ || !au_br_hnotifyable(perm)) { -+ au_hfsn_fin_br(br); -+ br->br_hfsn_group = NULL; -+ goto out; -+ } -+ -+ if (br->br_hfsn_group) -+ goto out; -+ -+ br->br_hfsn_group = fsnotify_alloc_group(&br->br_hfsn_ops); -+ if (IS_ERR(br->br_hfsn_group)) { -+ err = PTR_ERR(br->br_hfsn_group); -+ pr_err("fsnotify_alloc_group() failed, %d\n", err); -+ br->br_hfsn_group = NULL; -+ } -+ -+out: -+ AuTraceErr(err); -+ return err; -+} -+ -+const struct au_hnotify_op au_hnotify_op = { -+ .ctl = au_hfsn_ctl, -+ .alloc = au_hfsn_alloc, -+ .free = au_hfsn_free, -+ -+ .reset_br = au_hfsn_reset_br, -+ .fin_br = au_hfsn_fin_br, -+ .init_br = au_hfsn_init_br -+}; -diff -Nur linux-2.6.37.orig/fs/aufs/hfsplus.c linux-2.6.37/fs/aufs/hfsplus.c ---- linux-2.6.37.orig/fs/aufs/hfsplus.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/hfsplus.c 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,58 @@ -+/* -+ * Copyright (C) 2010-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * special support for filesystems which aqucires an inode mutex -+ * at final closing a file, eg, hfsplus. -+ * -+ * This trick is very simple and stupid, just to open the file before really -+ * neceeary open to tell hfsplus that this is not the final closing. -+ * The caller should call au_h_open_pre() after acquiring the inode mutex, -+ * and au_h_open_post() after releasing it. -+ */ -+ -+#include -+#include "aufs.h" -+ -+struct file *au_h_open_pre(struct dentry *dentry, aufs_bindex_t bindex) -+{ -+ struct file *h_file; -+ struct dentry *h_dentry; -+ -+ h_dentry = au_h_dptr(dentry, bindex); -+ AuDebugOn(!h_dentry); -+ AuDebugOn(!h_dentry->d_inode); -+ IMustLock(h_dentry->d_inode); -+ -+ h_file = NULL; -+ if (au_test_hfsplus(h_dentry->d_sb) -+ && S_ISREG(h_dentry->d_inode->i_mode)) -+ h_file = au_h_open(dentry, bindex, -+ O_RDONLY | O_NOATIME | O_LARGEFILE, -+ /*file*/NULL); -+ return h_file; -+} -+ -+void au_h_open_post(struct dentry *dentry, aufs_bindex_t bindex, -+ struct file *h_file) -+{ -+ if (h_file) { -+ fput(h_file); -+ au_sbr_put(dentry->d_sb, bindex); -+ } -+} -diff -Nur linux-2.6.37.orig/fs/aufs/hnotify.c linux-2.6.37/fs/aufs/hnotify.c ---- linux-2.6.37.orig/fs/aufs/hnotify.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/hnotify.c 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,694 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * abstraction to notify the direct changes on lower directories -+ */ -+ -+#include "aufs.h" -+ -+int au_hn_alloc(struct au_hinode *hinode, struct inode *inode) -+{ -+ int err; -+ struct au_hnotify *hn; -+ -+ err = -ENOMEM; -+ hn = au_cache_alloc_hnotify(); -+ if (hn) { -+ hn->hn_aufs_inode = inode; -+ hinode->hi_notify = hn; -+ err = au_hnotify_op.alloc(hinode); -+ AuTraceErr(err); -+ if (unlikely(err)) { -+ hinode->hi_notify = NULL; -+ au_cache_free_hnotify(hn); -+ /* -+ * The upper dir was removed by udba, but the same named -+ * dir left. In this case, aufs assignes a new inode -+ * number and set the monitor again. -+ * For the lower dir, the old monitnor is still left. -+ */ -+ if (err == -EEXIST) -+ err = 0; -+ } -+ } -+ -+ AuTraceErr(err); -+ return err; -+} -+ -+void au_hn_free(struct au_hinode *hinode) -+{ -+ struct au_hnotify *hn; -+ -+ hn = hinode->hi_notify; -+ if (hn) { -+ au_hnotify_op.free(hinode); -+ au_cache_free_hnotify(hn); -+ hinode->hi_notify = NULL; -+ } -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+void au_hn_ctl(struct au_hinode *hinode, int do_set) -+{ -+ if (hinode->hi_notify) -+ au_hnotify_op.ctl(hinode, do_set); -+} -+ -+void au_hn_reset(struct inode *inode, unsigned int flags) -+{ -+ aufs_bindex_t bindex, bend; -+ struct inode *hi; -+ struct dentry *iwhdentry; -+ -+ bend = au_ibend(inode); -+ for (bindex = au_ibstart(inode); bindex <= bend; bindex++) { -+ hi = au_h_iptr(inode, bindex); -+ if (!hi) -+ continue; -+ -+ /* mutex_lock_nested(&hi->i_mutex, AuLsc_I_CHILD); */ -+ iwhdentry = au_hi_wh(inode, bindex); -+ if (iwhdentry) -+ dget(iwhdentry); -+ au_igrab(hi); -+ au_set_h_iptr(inode, bindex, NULL, 0); -+ au_set_h_iptr(inode, bindex, au_igrab(hi), -+ flags & ~AuHi_XINO); -+ iput(hi); -+ dput(iwhdentry); -+ /* mutex_unlock(&hi->i_mutex); */ -+ } -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int hn_xino(struct inode *inode, struct inode *h_inode) -+{ -+ int err; -+ aufs_bindex_t bindex, bend, bfound, bstart; -+ struct inode *h_i; -+ -+ err = 0; -+ if (unlikely(inode->i_ino == AUFS_ROOT_INO)) { -+ pr_warning("branch root dir was changed\n"); -+ goto out; -+ } -+ -+ bfound = -1; -+ bend = au_ibend(inode); -+ bstart = au_ibstart(inode); -+#if 0 /* reserved for future use */ -+ if (bindex == bend) { -+ /* keep this ino in rename case */ -+ goto out; -+ } -+#endif -+ for (bindex = bstart; bindex <= bend; bindex++) -+ if (au_h_iptr(inode, bindex) == h_inode) { -+ bfound = bindex; -+ break; -+ } -+ if (bfound < 0) -+ goto out; -+ -+ for (bindex = bstart; bindex <= bend; bindex++) { -+ h_i = au_h_iptr(inode, bindex); -+ if (!h_i) -+ continue; -+ -+ err = au_xino_write(inode->i_sb, bindex, h_i->i_ino, /*ino*/0); -+ /* ignore this error */ -+ /* bad action? */ -+ } -+ -+ /* children inode number will be broken */ -+ -+out: -+ AuTraceErr(err); -+ return err; -+} -+ -+static int hn_gen_tree(struct dentry *dentry) -+{ -+ int err, i, j, ndentry; -+ struct au_dcsub_pages dpages; -+ struct au_dpage *dpage; -+ struct dentry **dentries; -+ -+ err = au_dpages_init(&dpages, GFP_NOFS); -+ if (unlikely(err)) -+ goto out; -+ err = au_dcsub_pages(&dpages, dentry, NULL, NULL); -+ if (unlikely(err)) -+ goto out_dpages; -+ -+ for (i = 0; i < dpages.ndpage; i++) { -+ dpage = dpages.dpages + i; -+ dentries = dpage->dentries; -+ ndentry = dpage->ndentry; -+ for (j = 0; j < ndentry; j++) { -+ struct dentry *d; -+ -+ d = dentries[j]; -+ if (IS_ROOT(d)) -+ continue; -+ -+ au_digen_dec(d); -+ if (d->d_inode) -+ /* todo: reset children xino? -+ cached children only? */ -+ au_iigen_dec(d->d_inode); -+ } -+ } -+ -+out_dpages: -+ au_dpages_free(&dpages); -+ -+ /* discard children */ -+ dentry_unhash(dentry); -+ dput(dentry); -+out: -+ return err; -+} -+ -+/* -+ * return 0 if processed. -+ */ -+static int hn_gen_by_inode(char *name, unsigned int nlen, struct inode *inode, -+ const unsigned int isdir) -+{ -+ int err; -+ struct dentry *d; -+ struct qstr *dname; -+ -+ err = 1; -+ if (unlikely(inode->i_ino == AUFS_ROOT_INO)) { -+ pr_warning("branch root dir was changed\n"); -+ err = 0; -+ goto out; -+ } -+ -+ if (!isdir) { -+ AuDebugOn(!name); -+ au_iigen_dec(inode); -+ spin_lock(&dcache_lock); -+ list_for_each_entry(d, &inode->i_dentry, d_alias) { -+ dname = &d->d_name; -+ if (dname->len != nlen -+ && memcmp(dname->name, name, nlen)) -+ continue; -+ err = 0; -+ au_digen_dec(d); -+ break; -+ } -+ spin_unlock(&dcache_lock); -+ } else { -+ au_fset_si(au_sbi(inode->i_sb), FAILED_REFRESH_DIR); -+ d = d_find_alias(inode); -+ if (!d) { -+ au_iigen_dec(inode); -+ goto out; -+ } -+ -+ dname = &d->d_name; -+ if (dname->len == nlen && !memcmp(dname->name, name, nlen)) -+ err = hn_gen_tree(d); -+ dput(d); -+ } -+ -+out: -+ AuTraceErr(err); -+ return err; -+} -+ -+static int hn_gen_by_name(struct dentry *dentry, const unsigned int isdir) -+{ -+ int err; -+ struct inode *inode; -+ -+ inode = dentry->d_inode; -+ if (IS_ROOT(dentry) -+ /* || (inode && inode->i_ino == AUFS_ROOT_INO) */ -+ ) { -+ pr_warning("branch root dir was changed\n"); -+ return 0; -+ } -+ -+ err = 0; -+ if (!isdir) { -+ au_digen_dec(dentry); -+ if (inode) -+ au_iigen_dec(inode); -+ } else { -+ au_fset_si(au_sbi(dentry->d_sb), FAILED_REFRESH_DIR); -+ if (inode) -+ err = hn_gen_tree(dentry); -+ } -+ -+ AuTraceErr(err); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* hnotify job flags */ -+#define AuHnJob_XINO0 1 -+#define AuHnJob_GEN (1 << 1) -+#define AuHnJob_DIRENT (1 << 2) -+#define AuHnJob_ISDIR (1 << 3) -+#define AuHnJob_TRYXINO0 (1 << 4) -+#define AuHnJob_MNTPNT (1 << 5) -+#define au_ftest_hnjob(flags, name) ((flags) & AuHnJob_##name) -+#define au_fset_hnjob(flags, name) \ -+ do { (flags) |= AuHnJob_##name; } while (0) -+#define au_fclr_hnjob(flags, name) \ -+ do { (flags) &= ~AuHnJob_##name; } while (0) -+ -+enum { -+ AuHn_CHILD, -+ AuHn_PARENT, -+ AuHnLast -+}; -+ -+struct au_hnotify_args { -+ struct inode *h_dir, *dir, *h_child_inode; -+ u32 mask; -+ unsigned int flags[AuHnLast]; -+ unsigned int h_child_nlen; -+ char h_child_name[]; -+}; -+ -+struct hn_job_args { -+ unsigned int flags; -+ struct inode *inode, *h_inode, *dir, *h_dir; -+ struct dentry *dentry; -+ char *h_name; -+ int h_nlen; -+}; -+ -+static int hn_job(struct hn_job_args *a) -+{ -+ const unsigned int isdir = au_ftest_hnjob(a->flags, ISDIR); -+ -+ /* reset xino */ -+ if (au_ftest_hnjob(a->flags, XINO0) && a->inode) -+ hn_xino(a->inode, a->h_inode); /* ignore this error */ -+ -+ if (au_ftest_hnjob(a->flags, TRYXINO0) -+ && a->inode -+ && a->h_inode) { -+ mutex_lock_nested(&a->h_inode->i_mutex, AuLsc_I_CHILD); -+ if (!a->h_inode->i_nlink) -+ hn_xino(a->inode, a->h_inode); /* ignore this error */ -+ mutex_unlock(&a->h_inode->i_mutex); -+ } -+ -+ /* make the generation obsolete */ -+ if (au_ftest_hnjob(a->flags, GEN)) { -+ int err = -1; -+ if (a->inode) -+ err = hn_gen_by_inode(a->h_name, a->h_nlen, a->inode, -+ isdir); -+ if (err && a->dentry) -+ hn_gen_by_name(a->dentry, isdir); -+ /* ignore this error */ -+ } -+ -+ /* make dir entries obsolete */ -+ if (au_ftest_hnjob(a->flags, DIRENT) && a->inode) { -+ struct au_vdir *vdir; -+ -+ vdir = au_ivdir(a->inode); -+ if (vdir) -+ vdir->vd_jiffy = 0; -+ /* IMustLock(a->inode); */ -+ /* a->inode->i_version++; */ -+ } -+ -+ /* can do nothing but warn */ -+ if (au_ftest_hnjob(a->flags, MNTPNT) -+ && a->dentry -+ && d_mountpoint(a->dentry)) -+ pr_warning("mount-point %.*s is removed or renamed\n", -+ AuDLNPair(a->dentry)); -+ -+ return 0; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static struct dentry *lookup_wlock_by_name(char *name, unsigned int nlen, -+ struct inode *dir) -+{ -+ struct dentry *dentry, *d, *parent; -+ struct qstr *dname; -+ -+ parent = d_find_alias(dir); -+ if (!parent) -+ return NULL; -+ -+ dentry = NULL; -+ spin_lock(&dcache_lock); -+ list_for_each_entry(d, &parent->d_subdirs, d_u.d_child) { -+ /* AuDbg("%.*s\n", AuDLNPair(d)); */ -+ dname = &d->d_name; -+ if (dname->len != nlen || memcmp(dname->name, name, nlen)) -+ continue; -+ if (au_di(d)) -+ au_digen_dec(d); -+ else -+ continue; -+ if (!atomic_read(&d->d_count)) -+ continue; -+ -+ dentry = dget(d); -+ break; -+ } -+ spin_unlock(&dcache_lock); -+ dput(parent); -+ -+ if (dentry) -+ di_write_lock_child(dentry); -+ -+ return dentry; -+} -+ -+static struct inode *lookup_wlock_by_ino(struct super_block *sb, -+ aufs_bindex_t bindex, ino_t h_ino) -+{ -+ struct inode *inode; -+ ino_t ino; -+ int err; -+ -+ inode = NULL; -+ err = au_xino_read(sb, bindex, h_ino, &ino); -+ if (!err && ino) -+ inode = ilookup(sb, ino); -+ if (!inode) -+ goto out; -+ -+ if (unlikely(inode->i_ino == AUFS_ROOT_INO)) { -+ pr_warning("wrong root branch\n"); -+ iput(inode); -+ inode = NULL; -+ goto out; -+ } -+ -+ ii_write_lock_child(inode); -+ -+out: -+ return inode; -+} -+ -+static void au_hn_bh(void *_args) -+{ -+ struct au_hnotify_args *a = _args; -+ struct super_block *sb; -+ aufs_bindex_t bindex, bend, bfound; -+ unsigned char xino, try_iput; -+ int err; -+ struct inode *inode; -+ ino_t h_ino; -+ struct hn_job_args args; -+ struct dentry *dentry; -+ struct au_sbinfo *sbinfo; -+ -+ AuDebugOn(!_args); -+ AuDebugOn(!a->h_dir); -+ AuDebugOn(!a->dir); -+ AuDebugOn(!a->mask); -+ AuDbg("mask 0x%x, i%lu, hi%lu, hci%lu\n", -+ a->mask, a->dir->i_ino, a->h_dir->i_ino, -+ a->h_child_inode ? a->h_child_inode->i_ino : 0); -+ -+ inode = NULL; -+ dentry = NULL; -+ /* -+ * do not lock a->dir->i_mutex here -+ * because of d_revalidate() may cause a deadlock. -+ */ -+ sb = a->dir->i_sb; -+ AuDebugOn(!sb); -+ sbinfo = au_sbi(sb); -+ AuDebugOn(!sbinfo); -+ si_write_lock(sb, AuLock_NOPLMW); -+ -+ ii_read_lock_parent(a->dir); -+ bfound = -1; -+ bend = au_ibend(a->dir); -+ for (bindex = au_ibstart(a->dir); bindex <= bend; bindex++) -+ if (au_h_iptr(a->dir, bindex) == a->h_dir) { -+ bfound = bindex; -+ break; -+ } -+ ii_read_unlock(a->dir); -+ if (unlikely(bfound < 0)) -+ goto out; -+ -+ xino = !!au_opt_test(au_mntflags(sb), XINO); -+ h_ino = 0; -+ if (a->h_child_inode) -+ h_ino = a->h_child_inode->i_ino; -+ -+ if (a->h_child_nlen -+ && (au_ftest_hnjob(a->flags[AuHn_CHILD], GEN) -+ || au_ftest_hnjob(a->flags[AuHn_CHILD], MNTPNT))) -+ dentry = lookup_wlock_by_name(a->h_child_name, a->h_child_nlen, -+ a->dir); -+ try_iput = 0; -+ if (dentry) -+ inode = dentry->d_inode; -+ if (xino && !inode && h_ino -+ && (au_ftest_hnjob(a->flags[AuHn_CHILD], XINO0) -+ || au_ftest_hnjob(a->flags[AuHn_CHILD], TRYXINO0) -+ || au_ftest_hnjob(a->flags[AuHn_CHILD], GEN))) { -+ inode = lookup_wlock_by_ino(sb, bfound, h_ino); -+ try_iput = 1; -+ } -+ -+ args.flags = a->flags[AuHn_CHILD]; -+ args.dentry = dentry; -+ args.inode = inode; -+ args.h_inode = a->h_child_inode; -+ args.dir = a->dir; -+ args.h_dir = a->h_dir; -+ args.h_name = a->h_child_name; -+ args.h_nlen = a->h_child_nlen; -+ err = hn_job(&args); -+ if (dentry) { -+ if (au_di(dentry)) -+ di_write_unlock(dentry); -+ dput(dentry); -+ } -+ if (inode && try_iput) { -+ ii_write_unlock(inode); -+ iput(inode); -+ } -+ -+ ii_write_lock_parent(a->dir); -+ args.flags = a->flags[AuHn_PARENT]; -+ args.dentry = NULL; -+ args.inode = a->dir; -+ args.h_inode = a->h_dir; -+ args.dir = NULL; -+ args.h_dir = NULL; -+ args.h_name = NULL; -+ args.h_nlen = 0; -+ err = hn_job(&args); -+ ii_write_unlock(a->dir); -+ -+out: -+ iput(a->h_child_inode); -+ iput(a->h_dir); -+ iput(a->dir); -+ si_write_unlock(sb); -+ au_nwt_done(&sbinfo->si_nowait); -+ kfree(a); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+int au_hnotify(struct inode *h_dir, struct au_hnotify *hnotify, u32 mask, -+ struct qstr *h_child_qstr, struct inode *h_child_inode) -+{ -+ int err, len; -+ unsigned int flags[AuHnLast]; -+ unsigned char isdir, isroot, wh; -+ struct inode *dir; -+ struct au_hnotify_args *args; -+ char *p, *h_child_name; -+ -+ err = 0; -+ AuDebugOn(!hnotify || !hnotify->hn_aufs_inode); -+ dir = igrab(hnotify->hn_aufs_inode); -+ if (!dir) -+ goto out; -+ -+ isroot = (dir->i_ino == AUFS_ROOT_INO); -+ wh = 0; -+ h_child_name = (void *)h_child_qstr->name; -+ len = h_child_qstr->len; -+ if (h_child_name) { -+ if (len > AUFS_WH_PFX_LEN -+ && !memcmp(h_child_name, AUFS_WH_PFX, AUFS_WH_PFX_LEN)) { -+ h_child_name += AUFS_WH_PFX_LEN; -+ len -= AUFS_WH_PFX_LEN; -+ wh = 1; -+ } -+ } -+ -+ isdir = 0; -+ if (h_child_inode) -+ isdir = !!S_ISDIR(h_child_inode->i_mode); -+ flags[AuHn_PARENT] = AuHnJob_ISDIR; -+ flags[AuHn_CHILD] = 0; -+ if (isdir) -+ flags[AuHn_CHILD] = AuHnJob_ISDIR; -+ au_fset_hnjob(flags[AuHn_PARENT], DIRENT); -+ au_fset_hnjob(flags[AuHn_CHILD], GEN); -+ switch (mask & FS_EVENTS_POSS_ON_CHILD) { -+ case FS_MOVED_FROM: -+ case FS_MOVED_TO: -+ au_fset_hnjob(flags[AuHn_CHILD], XINO0); -+ au_fset_hnjob(flags[AuHn_CHILD], MNTPNT); -+ /*FALLTHROUGH*/ -+ case FS_CREATE: -+ AuDebugOn(!h_child_name || !h_child_inode); -+ break; -+ -+ case FS_DELETE: -+ /* -+ * aufs never be able to get this child inode. -+ * revalidation should be in d_revalidate() -+ * by checking i_nlink, i_generation or d_unhashed(). -+ */ -+ AuDebugOn(!h_child_name); -+ au_fset_hnjob(flags[AuHn_CHILD], TRYXINO0); -+ au_fset_hnjob(flags[AuHn_CHILD], MNTPNT); -+ break; -+ -+ default: -+ AuDebugOn(1); -+ } -+ -+ if (wh) -+ h_child_inode = NULL; -+ -+ err = -ENOMEM; -+ /* iput() and kfree() will be called in au_hnotify() */ -+ args = kmalloc(sizeof(*args) + len + 1, GFP_NOFS); -+ if (unlikely(!args)) { -+ AuErr1("no memory\n"); -+ iput(dir); -+ goto out; -+ } -+ args->flags[AuHn_PARENT] = flags[AuHn_PARENT]; -+ args->flags[AuHn_CHILD] = flags[AuHn_CHILD]; -+ args->mask = mask; -+ args->dir = dir; -+ args->h_dir = igrab(h_dir); -+ if (h_child_inode) -+ h_child_inode = igrab(h_child_inode); /* can be NULL */ -+ args->h_child_inode = h_child_inode; -+ args->h_child_nlen = len; -+ if (len) { -+ p = (void *)args; -+ p += sizeof(*args); -+ memcpy(p, h_child_name, len); -+ p[len] = 0; -+ } -+ -+ err = au_wkq_nowait(au_hn_bh, args, dir->i_sb); -+ if (unlikely(err)) { -+ pr_err("wkq %d\n", err); -+ iput(args->h_child_inode); -+ iput(args->h_dir); -+ iput(args->dir); -+ kfree(args); -+ } -+ -+out: -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+int au_hnotify_reset_br(unsigned int udba, struct au_branch *br, int perm) -+{ -+ int err; -+ -+ AuDebugOn(!(udba & AuOptMask_UDBA)); -+ -+ err = 0; -+ if (au_hnotify_op.reset_br) -+ err = au_hnotify_op.reset_br(udba, br, perm); -+ -+ return err; -+} -+ -+int au_hnotify_init_br(struct au_branch *br, int perm) -+{ -+ int err; -+ -+ err = 0; -+ if (au_hnotify_op.init_br) -+ err = au_hnotify_op.init_br(br, perm); -+ -+ return err; -+} -+ -+void au_hnotify_fin_br(struct au_branch *br) -+{ -+ if (au_hnotify_op.fin_br) -+ au_hnotify_op.fin_br(br); -+} -+ -+static void au_hn_destroy_cache(void) -+{ -+ kmem_cache_destroy(au_cachep[AuCache_HNOTIFY]); -+ au_cachep[AuCache_HNOTIFY] = NULL; -+} -+ -+int __init au_hnotify_init(void) -+{ -+ int err; -+ -+ err = -ENOMEM; -+ au_cachep[AuCache_HNOTIFY] = AuCache(au_hnotify); -+ if (au_cachep[AuCache_HNOTIFY]) { -+ err = 0; -+ if (au_hnotify_op.init) -+ err = au_hnotify_op.init(); -+ if (unlikely(err)) -+ au_hn_destroy_cache(); -+ } -+ AuTraceErr(err); -+ return err; -+} -+ -+void au_hnotify_fin(void) -+{ -+ if (au_hnotify_op.fin) -+ au_hnotify_op.fin(); -+ /* cf. au_cache_fin() */ -+ if (au_cachep[AuCache_HNOTIFY]) -+ au_hn_destroy_cache(); -+} -diff -Nur linux-2.6.37.orig/fs/aufs/i_op.c linux-2.6.37/fs/aufs/i_op.c ---- linux-2.6.37.orig/fs/aufs/i_op.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/i_op.c 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,971 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * inode operations (except add/del/rename) -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include "aufs.h" -+ -+static int h_permission(struct inode *h_inode, int mask, -+ struct vfsmount *h_mnt, int brperm) -+{ -+ int err; -+ const unsigned char write_mask = !!(mask & (MAY_WRITE | MAY_APPEND)); -+ -+ err = -EACCES; -+ if ((write_mask && IS_IMMUTABLE(h_inode)) -+ || ((mask & MAY_EXEC) -+ && S_ISREG(h_inode->i_mode) -+ && ((h_mnt->mnt_flags & MNT_NOEXEC) -+ || !(h_inode->i_mode & S_IXUGO)))) -+ goto out; -+ -+ /* -+ * - skip the lower fs test in the case of write to ro branch. -+ * - nfs dir permission write check is optimized, but a policy for -+ * link/rename requires a real check. -+ */ -+ if ((write_mask && !au_br_writable(brperm)) -+ || (au_test_nfs(h_inode->i_sb) && S_ISDIR(h_inode->i_mode) -+ && write_mask && !(mask & MAY_READ)) -+ || !h_inode->i_op->permission) { -+ /* AuLabel(generic_permission); */ -+ err = generic_permission(h_inode, mask, -+ h_inode->i_op->check_acl); -+ } else { -+ /* AuLabel(h_inode->permission); */ -+ err = h_inode->i_op->permission(h_inode, mask); -+ AuTraceErr(err); -+ } -+ -+ if (!err) -+ err = devcgroup_inode_permission(h_inode, mask); -+ if (!err) -+ err = security_inode_permission(h_inode, mask); -+ -+#if 0 -+ if (!err) { -+ /* todo: do we need to call ima_path_check()? */ -+ struct path h_path = { -+ .dentry = -+ .mnt = h_mnt -+ }; -+ err = ima_path_check(&h_path, -+ mask & (MAY_READ | MAY_WRITE | MAY_EXEC), -+ IMA_COUNT_LEAVE); -+ } -+#endif -+ -+out: -+ return err; -+} -+ -+static int aufs_permission(struct inode *inode, int mask) -+{ -+ int err; -+ aufs_bindex_t bindex, bend; -+ const unsigned char isdir = !!S_ISDIR(inode->i_mode), -+ write_mask = !!(mask & (MAY_WRITE | MAY_APPEND)); -+ struct inode *h_inode; -+ struct super_block *sb; -+ struct au_branch *br; -+ -+ sb = inode->i_sb; -+ si_read_lock(sb, AuLock_FLUSH); -+ ii_read_lock_child(inode); -+#if 0 -+ err = au_iigen_test(inode, au_sigen(sb)); -+ if (unlikely(err)) -+ goto out; -+#endif -+ -+ if (!isdir || write_mask) { -+ err = au_busy_or_stale(); -+ h_inode = au_h_iptr(inode, au_ibstart(inode)); -+ if (unlikely(!h_inode -+ || (h_inode->i_mode & S_IFMT) -+ != (inode->i_mode & S_IFMT))) -+ goto out; -+ -+ err = 0; -+ bindex = au_ibstart(inode); -+ br = au_sbr(sb, bindex); -+ err = h_permission(h_inode, mask, br->br_mnt, br->br_perm); -+ if (write_mask -+ && !err -+ && !special_file(h_inode->i_mode)) { -+ /* test whether the upper writable branch exists */ -+ err = -EROFS; -+ for (; bindex >= 0; bindex--) -+ if (!au_br_rdonly(au_sbr(sb, bindex))) { -+ err = 0; -+ break; -+ } -+ } -+ goto out; -+ } -+ -+ /* non-write to dir */ -+ err = 0; -+ bend = au_ibend(inode); -+ for (bindex = au_ibstart(inode); !err && bindex <= bend; bindex++) { -+ h_inode = au_h_iptr(inode, bindex); -+ if (h_inode) { -+ err = au_busy_or_stale(); -+ if (unlikely(!S_ISDIR(h_inode->i_mode))) -+ break; -+ -+ br = au_sbr(sb, bindex); -+ err = h_permission(h_inode, mask, br->br_mnt, -+ br->br_perm); -+ } -+ } -+ -+out: -+ ii_read_unlock(inode); -+ si_read_unlock(sb); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static struct dentry *aufs_lookup(struct inode *dir, struct dentry *dentry, -+ struct nameidata *nd) -+{ -+ struct dentry *ret, *parent; -+ struct inode *inode; -+ struct super_block *sb; -+ int err, npositive; -+ -+ IMustLock(dir); -+ -+ sb = dir->i_sb; -+ err = si_read_lock(sb, AuLock_FLUSH | AuLock_NOPLM); -+ ret = ERR_PTR(err); -+ if (unlikely(err)) -+ goto out; -+ -+ ret = ERR_PTR(-ENAMETOOLONG); -+ if (unlikely(dentry->d_name.len > AUFS_MAX_NAMELEN)) -+ goto out_si; -+ err = au_di_init(dentry); -+ ret = ERR_PTR(err); -+ if (unlikely(err)) -+ goto out_si; -+ -+ npositive = 0; /* suppress a warning */ -+ parent = dentry->d_parent; /* dir inode is locked */ -+ di_read_lock_parent(parent, AuLock_IR); -+ err = au_alive_dir(parent); -+ if (!err) -+ err = au_digen_test(parent, au_sigen(sb)); -+ if (!err) { -+ npositive = au_lkup_dentry(dentry, au_dbstart(parent), -+ /*type*/0, nd); -+ err = npositive; -+ } -+ di_read_unlock(parent, AuLock_IR); -+ ret = ERR_PTR(err); -+ if (unlikely(err < 0)) -+ goto out_unlock; -+ -+ inode = NULL; -+ if (npositive) { -+ inode = au_new_inode(dentry, /*must_new*/0); -+ ret = (void *)inode; -+ } -+ if (IS_ERR(inode)) -+ goto out_unlock; -+ -+ ret = d_splice_alias(inode, dentry); -+ if (unlikely(IS_ERR(ret) && inode)) { -+ ii_write_unlock(inode); -+ iput(inode); -+ } -+ -+out_unlock: -+ di_write_unlock(dentry); -+out_si: -+ si_read_unlock(sb); -+out: -+ return ret; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int au_wr_dir_cpup(struct dentry *dentry, struct dentry *parent, -+ const unsigned char add_entry, aufs_bindex_t bcpup, -+ aufs_bindex_t bstart) -+{ -+ int err; -+ struct dentry *h_parent; -+ struct inode *h_dir; -+ -+ if (add_entry) -+ IMustLock(parent->d_inode); -+ else -+ di_write_lock_parent(parent); -+ -+ err = 0; -+ if (!au_h_dptr(parent, bcpup)) { -+ if (bstart < bcpup) -+ err = au_cpdown_dirs(dentry, bcpup); -+ else -+ err = au_cpup_dirs(dentry, bcpup); -+ } -+ if (!err && add_entry) { -+ h_parent = au_h_dptr(parent, bcpup); -+ h_dir = h_parent->d_inode; -+ mutex_lock_nested(&h_dir->i_mutex, AuLsc_I_PARENT); -+ err = au_lkup_neg(dentry, bcpup); -+ /* todo: no unlock here */ -+ mutex_unlock(&h_dir->i_mutex); -+ -+ AuDbg("bcpup %d\n", bcpup); -+ if (!err) { -+ if (!dentry->d_inode) -+ au_set_h_dptr(dentry, bstart, NULL); -+ au_update_dbrange(dentry, /*do_put_zero*/0); -+ } -+ } -+ -+ if (!add_entry) -+ di_write_unlock(parent); -+ if (!err) -+ err = bcpup; /* success */ -+ -+ AuTraceErr(err); -+ return err; -+} -+ -+/* -+ * decide the branch and the parent dir where we will create a new entry. -+ * returns new bindex or an error. -+ * copyup the parent dir if needed. -+ */ -+int au_wr_dir(struct dentry *dentry, struct dentry *src_dentry, -+ struct au_wr_dir_args *args) -+{ -+ int err; -+ aufs_bindex_t bcpup, bstart, src_bstart; -+ const unsigned char add_entry = !!au_ftest_wrdir(args->flags, -+ ADD_ENTRY); -+ struct super_block *sb; -+ struct dentry *parent; -+ struct au_sbinfo *sbinfo; -+ -+ sb = dentry->d_sb; -+ sbinfo = au_sbi(sb); -+ parent = dget_parent(dentry); -+ bstart = au_dbstart(dentry); -+ bcpup = bstart; -+ if (args->force_btgt < 0) { -+ if (src_dentry) { -+ src_bstart = au_dbstart(src_dentry); -+ if (src_bstart < bstart) -+ bcpup = src_bstart; -+ } else if (add_entry) { -+ err = AuWbrCreate(sbinfo, dentry, -+ au_ftest_wrdir(args->flags, ISDIR)); -+ bcpup = err; -+ } -+ -+ if (bcpup < 0 || au_test_ro(sb, bcpup, dentry->d_inode)) { -+ if (add_entry) -+ err = AuWbrCopyup(sbinfo, dentry); -+ else { -+ if (!IS_ROOT(dentry)) { -+ di_read_lock_parent(parent, !AuLock_IR); -+ err = AuWbrCopyup(sbinfo, dentry); -+ di_read_unlock(parent, !AuLock_IR); -+ } else -+ err = AuWbrCopyup(sbinfo, dentry); -+ } -+ bcpup = err; -+ if (unlikely(err < 0)) -+ goto out; -+ } -+ } else { -+ bcpup = args->force_btgt; -+ AuDebugOn(au_test_ro(sb, bcpup, dentry->d_inode)); -+ } -+ -+ AuDbg("bstart %d, bcpup %d\n", bstart, bcpup); -+ err = bcpup; -+ if (bcpup == bstart) -+ goto out; /* success */ -+ -+ /* copyup the new parent into the branch we process */ -+ err = au_wr_dir_cpup(dentry, parent, add_entry, bcpup, bstart); -+ if (err >= 0) { -+ if (!dentry->d_inode) { -+ au_set_h_dptr(dentry, bstart, NULL); -+ au_set_dbstart(dentry, bcpup); -+ au_set_dbend(dentry, bcpup); -+ } -+ AuDebugOn(add_entry && !au_h_dptr(dentry, bcpup)); -+ } -+ -+out: -+ dput(parent); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+struct dentry *au_pinned_h_parent(struct au_pin *pin) -+{ -+ if (pin && pin->parent) -+ return au_h_dptr(pin->parent, pin->bindex); -+ return NULL; -+} -+ -+void au_unpin(struct au_pin *p) -+{ -+ if (p->h_mnt && au_ftest_pin(p->flags, MNT_WRITE)) -+ mnt_drop_write(p->h_mnt); -+ if (!p->hdir) -+ return; -+ -+ au_hn_imtx_unlock(p->hdir); -+ if (!au_ftest_pin(p->flags, DI_LOCKED)) -+ di_read_unlock(p->parent, AuLock_IR); -+ iput(p->hdir->hi_inode); -+ dput(p->parent); -+ p->parent = NULL; -+ p->hdir = NULL; -+ p->h_mnt = NULL; -+} -+ -+int au_do_pin(struct au_pin *p) -+{ -+ int err; -+ struct super_block *sb; -+ struct dentry *h_dentry, *h_parent; -+ struct au_branch *br; -+ struct inode *h_dir; -+ -+ err = 0; -+ sb = p->dentry->d_sb; -+ br = au_sbr(sb, p->bindex); -+ if (IS_ROOT(p->dentry)) { -+ if (au_ftest_pin(p->flags, MNT_WRITE)) { -+ p->h_mnt = br->br_mnt; -+ err = mnt_want_write(p->h_mnt); -+ if (unlikely(err)) { -+ au_fclr_pin(p->flags, MNT_WRITE); -+ goto out_err; -+ } -+ } -+ goto out; -+ } -+ -+ h_dentry = NULL; -+ if (p->bindex <= au_dbend(p->dentry)) -+ h_dentry = au_h_dptr(p->dentry, p->bindex); -+ -+ p->parent = dget_parent(p->dentry); -+ if (!au_ftest_pin(p->flags, DI_LOCKED)) -+ di_read_lock(p->parent, AuLock_IR, p->lsc_di); -+ -+ h_dir = NULL; -+ h_parent = au_h_dptr(p->parent, p->bindex); -+ p->hdir = au_hi(p->parent->d_inode, p->bindex); -+ if (p->hdir) -+ h_dir = p->hdir->hi_inode; -+ -+ /* -+ * udba case, or -+ * if DI_LOCKED is not set, then p->parent may be different -+ * and h_parent can be NULL. -+ */ -+ if (unlikely(!p->hdir || !h_dir || !h_parent)) { -+ err = -EBUSY; -+ if (!au_ftest_pin(p->flags, DI_LOCKED)) -+ di_read_unlock(p->parent, AuLock_IR); -+ dput(p->parent); -+ p->parent = NULL; -+ goto out_err; -+ } -+ -+ au_igrab(h_dir); -+ au_hn_imtx_lock_nested(p->hdir, p->lsc_hi); -+ -+ if (unlikely(p->hdir->hi_inode != h_parent->d_inode)) { -+ err = -EBUSY; -+ goto out_unpin; -+ } -+ if (h_dentry) { -+ err = au_h_verify(h_dentry, p->udba, h_dir, h_parent, br); -+ if (unlikely(err)) { -+ au_fclr_pin(p->flags, MNT_WRITE); -+ goto out_unpin; -+ } -+ } -+ -+ if (au_ftest_pin(p->flags, MNT_WRITE)) { -+ p->h_mnt = br->br_mnt; -+ err = mnt_want_write(p->h_mnt); -+ if (unlikely(err)) { -+ au_fclr_pin(p->flags, MNT_WRITE); -+ goto out_unpin; -+ } -+ } -+ goto out; /* success */ -+ -+out_unpin: -+ au_unpin(p); -+out_err: -+ pr_err("err %d\n", err); -+ err = au_busy_or_stale(); -+out: -+ return err; -+} -+ -+void au_pin_init(struct au_pin *p, struct dentry *dentry, -+ aufs_bindex_t bindex, int lsc_di, int lsc_hi, -+ unsigned int udba, unsigned char flags) -+{ -+ p->dentry = dentry; -+ p->udba = udba; -+ p->lsc_di = lsc_di; -+ p->lsc_hi = lsc_hi; -+ p->flags = flags; -+ p->bindex = bindex; -+ -+ p->parent = NULL; -+ p->hdir = NULL; -+ p->h_mnt = NULL; -+} -+ -+int au_pin(struct au_pin *pin, struct dentry *dentry, aufs_bindex_t bindex, -+ unsigned int udba, unsigned char flags) -+{ -+ au_pin_init(pin, dentry, bindex, AuLsc_DI_PARENT, AuLsc_I_PARENT2, -+ udba, flags); -+ return au_do_pin(pin); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * ->setattr() and ->getattr() are called in various cases. -+ * chmod, stat: dentry is revalidated. -+ * fchmod, fstat: file and dentry are not revalidated, additionally they may be -+ * unhashed. -+ * for ->setattr(), ia->ia_file is passed from ftruncate only. -+ */ -+/* todo: consolidate with do_refresh() and simple_reval_dpath() */ -+static int au_reval_for_attr(struct dentry *dentry, unsigned int sigen) -+{ -+ int err; -+ struct inode *inode; -+ struct dentry *parent; -+ -+ err = 0; -+ inode = dentry->d_inode; -+ if (au_digen_test(dentry, sigen)) { -+ parent = dget_parent(dentry); -+ di_read_lock_parent(parent, AuLock_IR); -+ err = au_refresh_dentry(dentry, parent); -+ di_read_unlock(parent, AuLock_IR); -+ dput(parent); -+ } -+ -+ AuTraceErr(err); -+ return err; -+} -+ -+#define AuIcpup_DID_CPUP 1 -+#define au_ftest_icpup(flags, name) ((flags) & AuIcpup_##name) -+#define au_fset_icpup(flags, name) \ -+ do { (flags) |= AuIcpup_##name; } while (0) -+#define au_fclr_icpup(flags, name) \ -+ do { (flags) &= ~AuIcpup_##name; } while (0) -+ -+struct au_icpup_args { -+ unsigned char flags; -+ unsigned char pin_flags; -+ aufs_bindex_t btgt; -+ unsigned int udba; -+ struct au_pin pin; -+ struct path h_path; -+ struct inode *h_inode; -+}; -+ -+static int au_pin_and_icpup(struct dentry *dentry, struct iattr *ia, -+ struct au_icpup_args *a) -+{ -+ int err; -+ loff_t sz; -+ aufs_bindex_t bstart, ibstart; -+ struct dentry *hi_wh, *parent; -+ struct inode *inode; -+ struct file *h_file; -+ struct au_wr_dir_args wr_dir_args = { -+ .force_btgt = -1, -+ .flags = 0 -+ }; -+ -+ bstart = au_dbstart(dentry); -+ inode = dentry->d_inode; -+ if (S_ISDIR(inode->i_mode)) -+ au_fset_wrdir(wr_dir_args.flags, ISDIR); -+ /* plink or hi_wh() case */ -+ ibstart = au_ibstart(inode); -+ if (bstart != ibstart && !au_test_ro(inode->i_sb, ibstart, inode)) -+ wr_dir_args.force_btgt = ibstart; -+ err = au_wr_dir(dentry, /*src_dentry*/NULL, &wr_dir_args); -+ if (unlikely(err < 0)) -+ goto out; -+ a->btgt = err; -+ if (err != bstart) -+ au_fset_icpup(a->flags, DID_CPUP); -+ -+ err = 0; -+ a->pin_flags = AuPin_MNT_WRITE; -+ parent = NULL; -+ if (!IS_ROOT(dentry)) { -+ au_fset_pin(a->pin_flags, DI_LOCKED); -+ parent = dget_parent(dentry); -+ di_write_lock_parent(parent); -+ } -+ -+ err = au_pin(&a->pin, dentry, a->btgt, a->udba, a->pin_flags); -+ if (unlikely(err)) -+ goto out_parent; -+ -+ a->h_path.dentry = au_h_dptr(dentry, bstart); -+ a->h_inode = a->h_path.dentry->d_inode; -+ mutex_lock_nested(&a->h_inode->i_mutex, AuLsc_I_CHILD); -+ sz = -1; -+ if ((ia->ia_valid & ATTR_SIZE) && ia->ia_size < i_size_read(a->h_inode)) -+ sz = ia->ia_size; -+ -+ h_file = NULL; -+ hi_wh = NULL; -+ if (au_ftest_icpup(a->flags, DID_CPUP) && au_d_removed(dentry)) { -+ hi_wh = au_hi_wh(inode, a->btgt); -+ if (!hi_wh) { -+ err = au_sio_cpup_wh(dentry, a->btgt, sz, /*file*/NULL); -+ if (unlikely(err)) -+ goto out_unlock; -+ hi_wh = au_hi_wh(inode, a->btgt); -+ /* todo: revalidate hi_wh? */ -+ } -+ } -+ -+ if (parent) { -+ au_pin_set_parent_lflag(&a->pin, /*lflag*/0); -+ di_downgrade_lock(parent, AuLock_IR); -+ dput(parent); -+ parent = NULL; -+ } -+ if (!au_ftest_icpup(a->flags, DID_CPUP)) -+ goto out; /* success */ -+ -+ if (!d_unhashed(dentry)) { -+ h_file = au_h_open_pre(dentry, bstart); -+ if (IS_ERR(h_file)) { -+ err = PTR_ERR(h_file); -+ h_file = NULL; -+ } else -+ err = au_sio_cpup_simple(dentry, a->btgt, sz, -+ AuCpup_DTIME); -+ if (!err) -+ a->h_path.dentry = au_h_dptr(dentry, a->btgt); -+ } else if (!hi_wh) -+ a->h_path.dentry = au_h_dptr(dentry, a->btgt); -+ else -+ a->h_path.dentry = hi_wh; /* do not dget here */ -+ -+out_unlock: -+ mutex_unlock(&a->h_inode->i_mutex); -+ au_h_open_post(dentry, bstart, h_file); -+ a->h_inode = a->h_path.dentry->d_inode; -+ if (!err) { -+ mutex_lock_nested(&a->h_inode->i_mutex, AuLsc_I_CHILD); -+ goto out; /* success */ -+ } -+ -+ au_unpin(&a->pin); -+out_parent: -+ if (parent) { -+ di_write_unlock(parent); -+ dput(parent); -+ } -+out: -+ return err; -+} -+ -+static int aufs_setattr(struct dentry *dentry, struct iattr *ia) -+{ -+ int err; -+ struct inode *inode; -+ struct super_block *sb; -+ struct file *file; -+ struct au_icpup_args *a; -+ -+ inode = dentry->d_inode; -+ IMustLock(inode); -+ -+ err = -ENOMEM; -+ a = kzalloc(sizeof(*a), GFP_NOFS); -+ if (unlikely(!a)) -+ goto out; -+ -+ if (ia->ia_valid & (ATTR_KILL_SUID | ATTR_KILL_SGID)) -+ ia->ia_valid &= ~ATTR_MODE; -+ -+ file = NULL; -+ sb = dentry->d_sb; -+ err = si_read_lock(sb, AuLock_FLUSH | AuLock_NOPLM); -+ if (unlikely(err)) -+ goto out_kfree; -+ -+ if (ia->ia_valid & ATTR_FILE) { -+ /* currently ftruncate(2) only */ -+ AuDebugOn(!S_ISREG(inode->i_mode)); -+ file = ia->ia_file; -+ err = au_reval_and_lock_fdi(file, au_reopen_nondir, /*wlock*/1); -+ if (unlikely(err)) -+ goto out_si; -+ ia->ia_file = au_hf_top(file); -+ a->udba = AuOpt_UDBA_NONE; -+ } else { -+ /* fchmod() doesn't pass ia_file */ -+ a->udba = au_opt_udba(sb); -+ /* no au_d_removed(), to set UDBA_NONE for root */ -+ if (d_unhashed(dentry)) -+ a->udba = AuOpt_UDBA_NONE; -+ di_write_lock_child(dentry); -+ if (a->udba != AuOpt_UDBA_NONE) { -+ AuDebugOn(IS_ROOT(dentry)); -+ err = au_reval_for_attr(dentry, au_sigen(sb)); -+ if (unlikely(err)) -+ goto out_dentry; -+ } -+ } -+ -+ err = au_pin_and_icpup(dentry, ia, a); -+ if (unlikely(err < 0)) -+ goto out_dentry; -+ if (au_ftest_icpup(a->flags, DID_CPUP)) { -+ ia->ia_file = NULL; -+ ia->ia_valid &= ~ATTR_FILE; -+ } -+ -+ a->h_path.mnt = au_sbr_mnt(sb, a->btgt); -+ if ((ia->ia_valid & (ATTR_MODE | ATTR_CTIME)) -+ == (ATTR_MODE | ATTR_CTIME)) { -+ err = security_path_chmod(a->h_path.dentry, a->h_path.mnt, -+ ia->ia_mode); -+ if (unlikely(err)) -+ goto out_unlock; -+ } else if ((ia->ia_valid & (ATTR_UID | ATTR_GID)) -+ && (ia->ia_valid & ATTR_CTIME)) { -+ err = security_path_chown(&a->h_path, ia->ia_uid, ia->ia_gid); -+ if (unlikely(err)) -+ goto out_unlock; -+ } -+ -+ if (ia->ia_valid & ATTR_SIZE) { -+ struct file *f; -+ -+ if (ia->ia_size < i_size_read(inode)) -+ /* unmap only */ -+ truncate_setsize(inode, ia->ia_size); -+ -+ f = NULL; -+ if (ia->ia_valid & ATTR_FILE) -+ f = ia->ia_file; -+ mutex_unlock(&a->h_inode->i_mutex); -+ err = vfsub_trunc(&a->h_path, ia->ia_size, ia->ia_valid, f); -+ mutex_lock_nested(&a->h_inode->i_mutex, AuLsc_I_CHILD); -+ } else -+ err = vfsub_notify_change(&a->h_path, ia); -+ if (!err) -+ au_cpup_attr_changeable(inode); -+ -+out_unlock: -+ mutex_unlock(&a->h_inode->i_mutex); -+ au_unpin(&a->pin); -+ if (unlikely(err)) -+ au_update_dbstart(dentry); -+out_dentry: -+ di_write_unlock(dentry); -+ if (file) { -+ fi_write_unlock(file); -+ ia->ia_file = file; -+ ia->ia_valid |= ATTR_FILE; -+ } -+out_si: -+ si_read_unlock(sb); -+out_kfree: -+ kfree(a); -+out: -+ AuTraceErr(err); -+ return err; -+} -+ -+static void au_refresh_iattr(struct inode *inode, struct kstat *st, -+ unsigned int nlink) -+{ -+ inode->i_mode = st->mode; -+ inode->i_uid = st->uid; -+ inode->i_gid = st->gid; -+ inode->i_atime = st->atime; -+ inode->i_mtime = st->mtime; -+ inode->i_ctime = st->ctime; -+ -+ au_cpup_attr_nlink(inode, /*force*/0); -+ if (S_ISDIR(inode->i_mode)) { -+ inode->i_nlink -= nlink; -+ inode->i_nlink += st->nlink; -+ } -+ -+ spin_lock(&inode->i_lock); -+ inode->i_blocks = st->blocks; -+ i_size_write(inode, st->size); -+ spin_unlock(&inode->i_lock); -+} -+ -+static int aufs_getattr(struct vfsmount *mnt __maybe_unused, -+ struct dentry *dentry, struct kstat *st) -+{ -+ int err; -+ unsigned int mnt_flags; -+ aufs_bindex_t bindex; -+ unsigned char udba_none, positive; -+ struct super_block *sb, *h_sb; -+ struct inode *inode; -+ struct vfsmount *h_mnt; -+ struct dentry *h_dentry; -+ -+ sb = dentry->d_sb; -+ inode = dentry->d_inode; -+ err = si_read_lock(sb, AuLock_FLUSH | AuLock_NOPLM); -+ if (unlikely(err)) -+ goto out; -+ mnt_flags = au_mntflags(sb); -+ udba_none = !!au_opt_test(mnt_flags, UDBA_NONE); -+ -+ /* support fstat(2) */ -+ if (!au_d_removed(dentry) && !udba_none) { -+ unsigned int sigen = au_sigen(sb); -+ err = au_digen_test(dentry, sigen); -+ if (!err) { -+ di_read_lock_child(dentry, AuLock_IR); -+ err = au_dbrange_test(dentry); -+ if (unlikely(err)) -+ goto out_unlock; -+ } else { -+ AuDebugOn(IS_ROOT(dentry)); -+ di_write_lock_child(dentry); -+ err = au_dbrange_test(dentry); -+ if (!err) -+ err = au_reval_for_attr(dentry, sigen); -+ di_downgrade_lock(dentry, AuLock_IR); -+ if (unlikely(err)) -+ goto out_unlock; -+ } -+ } else -+ di_read_lock_child(dentry, AuLock_IR); -+ -+ bindex = au_ibstart(inode); -+ h_mnt = au_sbr_mnt(sb, bindex); -+ h_sb = h_mnt->mnt_sb; -+ if (!au_test_fs_bad_iattr(h_sb) && udba_none) -+ goto out_fill; /* success */ -+ -+ h_dentry = NULL; -+ if (au_dbstart(dentry) == bindex) -+ h_dentry = dget(au_h_dptr(dentry, bindex)); -+ else if (au_opt_test(mnt_flags, PLINK) && au_plink_test(inode)) { -+ h_dentry = au_plink_lkup(inode, bindex); -+ if (IS_ERR(h_dentry)) -+ goto out_fill; /* pretending success */ -+ } -+ /* illegally overlapped or something */ -+ if (unlikely(!h_dentry)) -+ goto out_fill; /* pretending success */ -+ -+ positive = !!h_dentry->d_inode; -+ if (positive) -+ err = vfs_getattr(h_mnt, h_dentry, st); -+ dput(h_dentry); -+ if (!err) { -+ if (positive) -+ au_refresh_iattr(inode, st, h_dentry->d_inode->i_nlink); -+ goto out_fill; /* success */ -+ } -+ AuTraceErr(err); -+ goto out_unlock; -+ -+out_fill: -+ generic_fillattr(inode, st); -+out_unlock: -+ di_read_unlock(dentry, AuLock_IR); -+ si_read_unlock(sb); -+out: -+ AuTraceErr(err); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int h_readlink(struct dentry *dentry, int bindex, char __user *buf, -+ int bufsiz) -+{ -+ int err; -+ struct super_block *sb; -+ struct dentry *h_dentry; -+ -+ err = -EINVAL; -+ h_dentry = au_h_dptr(dentry, bindex); -+ if (unlikely(!h_dentry->d_inode->i_op->readlink)) -+ goto out; -+ -+ err = security_inode_readlink(h_dentry); -+ if (unlikely(err)) -+ goto out; -+ -+ sb = dentry->d_sb; -+ if (!au_test_ro(sb, bindex, dentry->d_inode)) { -+ vfsub_touch_atime(au_sbr_mnt(sb, bindex), h_dentry); -+ fsstack_copy_attr_atime(dentry->d_inode, h_dentry->d_inode); -+ } -+ err = h_dentry->d_inode->i_op->readlink(h_dentry, buf, bufsiz); -+ -+out: -+ return err; -+} -+ -+static int aufs_readlink(struct dentry *dentry, char __user *buf, int bufsiz) -+{ -+ int err; -+ -+ err = aufs_read_lock(dentry, AuLock_IR | AuLock_GEN); -+ if (unlikely(err)) -+ goto out; -+ err = au_d_hashed_positive(dentry); -+ if (!err) -+ err = h_readlink(dentry, au_dbstart(dentry), buf, bufsiz); -+ aufs_read_unlock(dentry, AuLock_IR); -+ -+out: -+ return err; -+} -+ -+static void *aufs_follow_link(struct dentry *dentry, struct nameidata *nd) -+{ -+ int err; -+ mm_segment_t old_fs; -+ union { -+ char *k; -+ char __user *u; -+ } buf; -+ -+ err = -ENOMEM; -+ buf.k = __getname_gfp(GFP_NOFS); -+ if (unlikely(!buf.k)) -+ goto out; -+ -+ err = aufs_read_lock(dentry, AuLock_IR | AuLock_GEN); -+ if (unlikely(err)) -+ goto out_name; -+ -+ err = au_d_hashed_positive(dentry); -+ if (!err) { -+ old_fs = get_fs(); -+ set_fs(KERNEL_DS); -+ err = h_readlink(dentry, au_dbstart(dentry), buf.u, PATH_MAX); -+ set_fs(old_fs); -+ } -+ aufs_read_unlock(dentry, AuLock_IR); -+ -+ if (err >= 0) { -+ buf.k[err] = 0; -+ /* will be freed by put_link */ -+ nd_set_link(nd, buf.k); -+ return NULL; /* success */ -+ } -+ -+out_name: -+ __putname(buf.k); -+out: -+ path_put(&nd->path); -+ AuTraceErr(err); -+ return ERR_PTR(err); -+} -+ -+static void aufs_put_link(struct dentry *dentry __maybe_unused, -+ struct nameidata *nd, void *cookie __maybe_unused) -+{ -+ __putname(nd_get_link(nd)); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static void aufs_truncate_range(struct inode *inode __maybe_unused, -+ loff_t start __maybe_unused, -+ loff_t end __maybe_unused) -+{ -+ AuUnsupport(); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+struct inode_operations aufs_symlink_iop = { -+ .permission = aufs_permission, -+ .setattr = aufs_setattr, -+ .getattr = aufs_getattr, -+ .readlink = aufs_readlink, -+ .follow_link = aufs_follow_link, -+ .put_link = aufs_put_link -+}; -+ -+struct inode_operations aufs_dir_iop = { -+ .create = aufs_create, -+ .lookup = aufs_lookup, -+ .link = aufs_link, -+ .unlink = aufs_unlink, -+ .symlink = aufs_symlink, -+ .mkdir = aufs_mkdir, -+ .rmdir = aufs_rmdir, -+ .mknod = aufs_mknod, -+ .rename = aufs_rename, -+ -+ .permission = aufs_permission, -+ .setattr = aufs_setattr, -+ .getattr = aufs_getattr -+}; -+ -+struct inode_operations aufs_iop = { -+ .permission = aufs_permission, -+ .setattr = aufs_setattr, -+ .getattr = aufs_getattr, -+ .truncate_range = aufs_truncate_range -+}; -diff -Nur linux-2.6.37.orig/fs/aufs/i_op_add.c linux-2.6.37/fs/aufs/i_op_add.c ---- linux-2.6.37.orig/fs/aufs/i_op_add.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/i_op_add.c 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,702 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * inode operations (add entry) -+ */ -+ -+#include "aufs.h" -+ -+/* -+ * final procedure of adding a new entry, except link(2). -+ * remove whiteout, instantiate, copyup the parent dir's times and size -+ * and update version. -+ * if it failed, re-create the removed whiteout. -+ */ -+static int epilog(struct inode *dir, aufs_bindex_t bindex, -+ struct dentry *wh_dentry, struct dentry *dentry) -+{ -+ int err, rerr; -+ aufs_bindex_t bwh; -+ struct path h_path; -+ struct inode *inode, *h_dir; -+ struct dentry *wh; -+ -+ bwh = -1; -+ if (wh_dentry) { -+ h_dir = wh_dentry->d_parent->d_inode; /* dir inode is locked */ -+ IMustLock(h_dir); -+ AuDebugOn(au_h_iptr(dir, bindex) != h_dir); -+ bwh = au_dbwh(dentry); -+ h_path.dentry = wh_dentry; -+ h_path.mnt = au_sbr_mnt(dir->i_sb, bindex); -+ err = au_wh_unlink_dentry(au_h_iptr(dir, bindex), &h_path, -+ dentry); -+ if (unlikely(err)) -+ goto out; -+ } -+ -+ inode = au_new_inode(dentry, /*must_new*/1); -+ if (!IS_ERR(inode)) { -+ d_instantiate(dentry, inode); -+ dir = dentry->d_parent->d_inode; /* dir inode is locked */ -+ IMustLock(dir); -+ if (au_ibstart(dir) == au_dbstart(dentry)) -+ au_cpup_attr_timesizes(dir); -+ dir->i_version++; -+ return 0; /* success */ -+ } -+ -+ err = PTR_ERR(inode); -+ if (!wh_dentry) -+ goto out; -+ -+ /* revert */ -+ /* dir inode is locked */ -+ wh = au_wh_create(dentry, bwh, wh_dentry->d_parent); -+ rerr = PTR_ERR(wh); -+ if (IS_ERR(wh)) { -+ AuIOErr("%.*s reverting whiteout failed(%d, %d)\n", -+ AuDLNPair(dentry), err, rerr); -+ err = -EIO; -+ } else -+ dput(wh); -+ -+out: -+ return err; -+} -+ -+static int au_d_may_add(struct dentry *dentry) -+{ -+ int err; -+ -+ err = 0; -+ if (unlikely(d_unhashed(dentry))) -+ err = -ENOENT; -+ if (unlikely(dentry->d_inode)) -+ err = -EEXIST; -+ return err; -+} -+ -+/* -+ * simple tests for the adding inode operations. -+ * following the checks in vfs, plus the parent-child relationship. -+ */ -+int au_may_add(struct dentry *dentry, aufs_bindex_t bindex, -+ struct dentry *h_parent, int isdir) -+{ -+ int err; -+ umode_t h_mode; -+ struct dentry *h_dentry; -+ struct inode *h_inode; -+ -+ err = -ENAMETOOLONG; -+ if (unlikely(dentry->d_name.len > AUFS_MAX_NAMELEN)) -+ goto out; -+ -+ h_dentry = au_h_dptr(dentry, bindex); -+ h_inode = h_dentry->d_inode; -+ if (!dentry->d_inode) { -+ err = -EEXIST; -+ if (unlikely(h_inode)) -+ goto out; -+ } else { -+ /* rename(2) case */ -+ err = -EIO; -+ if (unlikely(!h_inode || !h_inode->i_nlink)) -+ goto out; -+ -+ h_mode = h_inode->i_mode; -+ if (!isdir) { -+ err = -EISDIR; -+ if (unlikely(S_ISDIR(h_mode))) -+ goto out; -+ } else if (unlikely(!S_ISDIR(h_mode))) { -+ err = -ENOTDIR; -+ goto out; -+ } -+ } -+ -+ err = 0; -+ /* expected parent dir is locked */ -+ if (unlikely(h_parent != h_dentry->d_parent)) -+ err = -EIO; -+ -+out: -+ AuTraceErr(err); -+ return err; -+} -+ -+/* -+ * initial procedure of adding a new entry. -+ * prepare writable branch and the parent dir, lock it, -+ * and lookup whiteout for the new entry. -+ */ -+static struct dentry* -+lock_hdir_lkup_wh(struct dentry *dentry, struct au_dtime *dt, -+ struct dentry *src_dentry, struct au_pin *pin, -+ struct au_wr_dir_args *wr_dir_args) -+{ -+ struct dentry *wh_dentry, *h_parent; -+ struct super_block *sb; -+ struct au_branch *br; -+ int err; -+ unsigned int udba; -+ aufs_bindex_t bcpup; -+ -+ AuDbg("%.*s\n", AuDLNPair(dentry)); -+ -+ err = au_wr_dir(dentry, src_dentry, wr_dir_args); -+ bcpup = err; -+ wh_dentry = ERR_PTR(err); -+ if (unlikely(err < 0)) -+ goto out; -+ -+ sb = dentry->d_sb; -+ udba = au_opt_udba(sb); -+ err = au_pin(pin, dentry, bcpup, udba, -+ AuPin_DI_LOCKED | AuPin_MNT_WRITE); -+ wh_dentry = ERR_PTR(err); -+ if (unlikely(err)) -+ goto out; -+ -+ h_parent = au_pinned_h_parent(pin); -+ if (udba != AuOpt_UDBA_NONE -+ && au_dbstart(dentry) == bcpup) -+ err = au_may_add(dentry, bcpup, h_parent, -+ au_ftest_wrdir(wr_dir_args->flags, ISDIR)); -+ else if (unlikely(dentry->d_name.len > AUFS_MAX_NAMELEN)) -+ err = -ENAMETOOLONG; -+ wh_dentry = ERR_PTR(err); -+ if (unlikely(err)) -+ goto out_unpin; -+ -+ br = au_sbr(sb, bcpup); -+ if (dt) { -+ struct path tmp = { -+ .dentry = h_parent, -+ .mnt = br->br_mnt -+ }; -+ au_dtime_store(dt, au_pinned_parent(pin), &tmp); -+ } -+ -+ wh_dentry = NULL; -+ if (bcpup != au_dbwh(dentry)) -+ goto out; /* success */ -+ -+ wh_dentry = au_wh_lkup(h_parent, &dentry->d_name, br); -+ -+out_unpin: -+ if (IS_ERR(wh_dentry)) -+ au_unpin(pin); -+out: -+ return wh_dentry; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+enum { Mknod, Symlink, Creat }; -+struct simple_arg { -+ int type; -+ union { -+ struct { -+ int mode; -+ struct nameidata *nd; -+ } c; -+ struct { -+ const char *symname; -+ } s; -+ struct { -+ int mode; -+ dev_t dev; -+ } m; -+ } u; -+}; -+ -+static int add_simple(struct inode *dir, struct dentry *dentry, -+ struct simple_arg *arg) -+{ -+ int err; -+ aufs_bindex_t bstart; -+ unsigned char created; -+ struct au_dtime dt; -+ struct au_pin pin; -+ struct path h_path; -+ struct dentry *wh_dentry, *parent; -+ struct inode *h_dir; -+ struct au_wr_dir_args wr_dir_args = { -+ .force_btgt = -1, -+ .flags = AuWrDir_ADD_ENTRY -+ }; -+ -+ AuDbg("%.*s\n", AuDLNPair(dentry)); -+ IMustLock(dir); -+ -+ parent = dentry->d_parent; /* dir inode is locked */ -+ err = aufs_read_lock(dentry, AuLock_DW | AuLock_GEN); -+ if (unlikely(err)) -+ goto out; -+ err = au_d_may_add(dentry); -+ if (unlikely(err)) -+ goto out_unlock; -+ di_write_lock_parent(parent); -+ wh_dentry = lock_hdir_lkup_wh(dentry, &dt, /*src_dentry*/NULL, &pin, -+ &wr_dir_args); -+ err = PTR_ERR(wh_dentry); -+ if (IS_ERR(wh_dentry)) -+ goto out_parent; -+ -+ bstart = au_dbstart(dentry); -+ h_path.dentry = au_h_dptr(dentry, bstart); -+ h_path.mnt = au_sbr_mnt(dentry->d_sb, bstart); -+ h_dir = au_pinned_h_dir(&pin); -+ switch (arg->type) { -+ case Creat: -+ err = vfsub_create(h_dir, &h_path, arg->u.c.mode); -+ break; -+ case Symlink: -+ err = vfsub_symlink(h_dir, &h_path, arg->u.s.symname); -+ break; -+ case Mknod: -+ err = vfsub_mknod(h_dir, &h_path, arg->u.m.mode, arg->u.m.dev); -+ break; -+ default: -+ BUG(); -+ } -+ created = !err; -+ if (!err) -+ err = epilog(dir, bstart, wh_dentry, dentry); -+ -+ /* revert */ -+ if (unlikely(created && err && h_path.dentry->d_inode)) { -+ int rerr; -+ rerr = vfsub_unlink(h_dir, &h_path, /*force*/0); -+ if (rerr) { -+ AuIOErr("%.*s revert failure(%d, %d)\n", -+ AuDLNPair(dentry), err, rerr); -+ err = -EIO; -+ } -+ au_dtime_revert(&dt); -+ } -+ -+ au_unpin(&pin); -+ dput(wh_dentry); -+ -+out_parent: -+ di_write_unlock(parent); -+out_unlock: -+ if (unlikely(err)) { -+ au_update_dbstart(dentry); -+ d_drop(dentry); -+ } -+ aufs_read_unlock(dentry, AuLock_DW); -+out: -+ return err; -+} -+ -+int aufs_mknod(struct inode *dir, struct dentry *dentry, int mode, dev_t dev) -+{ -+ struct simple_arg arg = { -+ .type = Mknod, -+ .u.m = { -+ .mode = mode, -+ .dev = dev -+ } -+ }; -+ return add_simple(dir, dentry, &arg); -+} -+ -+int aufs_symlink(struct inode *dir, struct dentry *dentry, const char *symname) -+{ -+ struct simple_arg arg = { -+ .type = Symlink, -+ .u.s.symname = symname -+ }; -+ return add_simple(dir, dentry, &arg); -+} -+ -+int aufs_create(struct inode *dir, struct dentry *dentry, int mode, -+ struct nameidata *nd) -+{ -+ struct simple_arg arg = { -+ .type = Creat, -+ .u.c = { -+ .mode = mode, -+ .nd = nd -+ } -+ }; -+ return add_simple(dir, dentry, &arg); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+struct au_link_args { -+ aufs_bindex_t bdst, bsrc; -+ struct au_pin pin; -+ struct path h_path; -+ struct dentry *src_parent, *parent; -+}; -+ -+static int au_cpup_before_link(struct dentry *src_dentry, -+ struct au_link_args *a) -+{ -+ int err; -+ struct dentry *h_src_dentry; -+ struct mutex *h_mtx; -+ struct file *h_file; -+ -+ di_read_lock_parent(a->src_parent, AuLock_IR); -+ err = au_test_and_cpup_dirs(src_dentry, a->bdst); -+ if (unlikely(err)) -+ goto out; -+ -+ h_src_dentry = au_h_dptr(src_dentry, a->bsrc); -+ h_mtx = &h_src_dentry->d_inode->i_mutex; -+ err = au_pin(&a->pin, src_dentry, a->bdst, -+ au_opt_udba(src_dentry->d_sb), -+ AuPin_DI_LOCKED | AuPin_MNT_WRITE); -+ if (unlikely(err)) -+ goto out; -+ mutex_lock_nested(h_mtx, AuLsc_I_CHILD); -+ h_file = au_h_open_pre(src_dentry, a->bsrc); -+ if (IS_ERR(h_file)) { -+ err = PTR_ERR(h_file); -+ h_file = NULL; -+ } else -+ err = au_sio_cpup_simple(src_dentry, a->bdst, a->bsrc, -+ AuCpup_DTIME /* | AuCpup_KEEPLINO */); -+ mutex_unlock(h_mtx); -+ au_h_open_post(src_dentry, a->bsrc, h_file); -+ au_unpin(&a->pin); -+ -+out: -+ di_read_unlock(a->src_parent, AuLock_IR); -+ return err; -+} -+ -+static int au_cpup_or_link(struct dentry *src_dentry, struct au_link_args *a) -+{ -+ int err; -+ unsigned char plink; -+ struct inode *h_inode, *inode; -+ struct dentry *h_src_dentry; -+ struct super_block *sb; -+ struct file *h_file; -+ -+ plink = 0; -+ h_inode = NULL; -+ sb = src_dentry->d_sb; -+ inode = src_dentry->d_inode; -+ if (au_ibstart(inode) <= a->bdst) -+ h_inode = au_h_iptr(inode, a->bdst); -+ if (!h_inode || !h_inode->i_nlink) { -+ /* copyup src_dentry as the name of dentry. */ -+ au_set_dbstart(src_dentry, a->bdst); -+ au_set_h_dptr(src_dentry, a->bdst, dget(a->h_path.dentry)); -+ h_inode = au_h_dptr(src_dentry, a->bsrc)->d_inode; -+ mutex_lock_nested(&h_inode->i_mutex, AuLsc_I_CHILD); -+ h_file = au_h_open_pre(src_dentry, a->bsrc); -+ if (IS_ERR(h_file)) { -+ err = PTR_ERR(h_file); -+ h_file = NULL; -+ } else -+ err = au_sio_cpup_single(src_dentry, a->bdst, a->bsrc, -+ -1, AuCpup_KEEPLINO, -+ a->parent); -+ mutex_unlock(&h_inode->i_mutex); -+ au_h_open_post(src_dentry, a->bsrc, h_file); -+ au_set_h_dptr(src_dentry, a->bdst, NULL); -+ au_set_dbstart(src_dentry, a->bsrc); -+ } else { -+ /* the inode of src_dentry already exists on a.bdst branch */ -+ h_src_dentry = d_find_alias(h_inode); -+ if (!h_src_dentry && au_plink_test(inode)) { -+ plink = 1; -+ h_src_dentry = au_plink_lkup(inode, a->bdst); -+ err = PTR_ERR(h_src_dentry); -+ if (IS_ERR(h_src_dentry)) -+ goto out; -+ -+ if (unlikely(!h_src_dentry->d_inode)) { -+ dput(h_src_dentry); -+ h_src_dentry = NULL; -+ } -+ -+ } -+ if (h_src_dentry) { -+ err = vfsub_link(h_src_dentry, au_pinned_h_dir(&a->pin), -+ &a->h_path); -+ dput(h_src_dentry); -+ } else { -+ AuIOErr("no dentry found for hi%lu on b%d\n", -+ h_inode->i_ino, a->bdst); -+ err = -EIO; -+ } -+ } -+ -+ if (!err && !plink) -+ au_plink_append(inode, a->bdst, a->h_path.dentry); -+ -+out: -+ return err; -+} -+ -+int aufs_link(struct dentry *src_dentry, struct inode *dir, -+ struct dentry *dentry) -+{ -+ int err, rerr; -+ struct au_dtime dt; -+ struct au_link_args *a; -+ struct dentry *wh_dentry, *h_src_dentry; -+ struct inode *inode; -+ struct super_block *sb; -+ struct au_wr_dir_args wr_dir_args = { -+ /* .force_btgt = -1, */ -+ .flags = AuWrDir_ADD_ENTRY -+ }; -+ -+ IMustLock(dir); -+ inode = src_dentry->d_inode; -+ IMustLock(inode); -+ -+ err = -ENOMEM; -+ a = kzalloc(sizeof(*a), GFP_NOFS); -+ if (unlikely(!a)) -+ goto out; -+ -+ a->parent = dentry->d_parent; /* dir inode is locked */ -+ err = aufs_read_and_write_lock2(dentry, src_dentry, -+ AuLock_NOPLM | AuLock_GEN); -+ if (unlikely(err)) -+ goto out_kfree; -+ err = au_d_hashed_positive(src_dentry); -+ if (unlikely(err)) -+ goto out_unlock; -+ err = au_d_may_add(dentry); -+ if (unlikely(err)) -+ goto out_unlock; -+ -+ a->src_parent = dget_parent(src_dentry); -+ wr_dir_args.force_btgt = au_dbstart(src_dentry); -+ -+ di_write_lock_parent(a->parent); -+ wr_dir_args.force_btgt = au_wbr(dentry, wr_dir_args.force_btgt); -+ wh_dentry = lock_hdir_lkup_wh(dentry, &dt, src_dentry, &a->pin, -+ &wr_dir_args); -+ err = PTR_ERR(wh_dentry); -+ if (IS_ERR(wh_dentry)) -+ goto out_parent; -+ -+ err = 0; -+ sb = dentry->d_sb; -+ a->bdst = au_dbstart(dentry); -+ a->h_path.dentry = au_h_dptr(dentry, a->bdst); -+ a->h_path.mnt = au_sbr_mnt(sb, a->bdst); -+ a->bsrc = au_dbstart(src_dentry); -+ if (au_opt_test(au_mntflags(sb), PLINK)) { -+ if (a->bdst < a->bsrc -+ /* && h_src_dentry->d_sb != a->h_path.dentry->d_sb */) -+ err = au_cpup_or_link(src_dentry, a); -+ else { -+ h_src_dentry = au_h_dptr(src_dentry, a->bdst); -+ err = vfsub_link(h_src_dentry, au_pinned_h_dir(&a->pin), -+ &a->h_path); -+ } -+ } else { -+ /* -+ * copyup src_dentry to the branch we process, -+ * and then link(2) to it. -+ */ -+ if (a->bdst < a->bsrc -+ /* && h_src_dentry->d_sb != a->h_path.dentry->d_sb */) { -+ au_unpin(&a->pin); -+ di_write_unlock(a->parent); -+ err = au_cpup_before_link(src_dentry, a); -+ di_write_lock_parent(a->parent); -+ if (!err) -+ err = au_pin(&a->pin, dentry, a->bdst, -+ au_opt_udba(sb), -+ AuPin_DI_LOCKED | AuPin_MNT_WRITE); -+ if (unlikely(err)) -+ goto out_wh; -+ } -+ if (!err) { -+ h_src_dentry = au_h_dptr(src_dentry, a->bdst); -+ err = -ENOENT; -+ if (h_src_dentry && h_src_dentry->d_inode) -+ err = vfsub_link(h_src_dentry, -+ au_pinned_h_dir(&a->pin), -+ &a->h_path); -+ } -+ } -+ if (unlikely(err)) -+ goto out_unpin; -+ -+ if (wh_dentry) { -+ a->h_path.dentry = wh_dentry; -+ err = au_wh_unlink_dentry(au_pinned_h_dir(&a->pin), &a->h_path, -+ dentry); -+ if (unlikely(err)) -+ goto out_revert; -+ } -+ -+ dir->i_version++; -+ if (au_ibstart(dir) == au_dbstart(dentry)) -+ au_cpup_attr_timesizes(dir); -+ inc_nlink(inode); -+ inode->i_ctime = dir->i_ctime; -+ d_instantiate(dentry, au_igrab(inode)); -+ if (d_unhashed(a->h_path.dentry)) -+ /* some filesystem calls d_drop() */ -+ d_drop(dentry); -+ goto out_unpin; /* success */ -+ -+out_revert: -+ rerr = vfsub_unlink(au_pinned_h_dir(&a->pin), &a->h_path, /*force*/0); -+ if (unlikely(rerr)) { -+ AuIOErr("%.*s reverting failed(%d, %d)\n", -+ AuDLNPair(dentry), err, rerr); -+ err = -EIO; -+ } -+ au_dtime_revert(&dt); -+out_unpin: -+ au_unpin(&a->pin); -+out_wh: -+ dput(wh_dentry); -+out_parent: -+ di_write_unlock(a->parent); -+ dput(a->src_parent); -+out_unlock: -+ if (unlikely(err)) { -+ au_update_dbstart(dentry); -+ d_drop(dentry); -+ } -+ aufs_read_and_write_unlock2(dentry, src_dentry); -+out_kfree: -+ kfree(a); -+out: -+ return err; -+} -+ -+int aufs_mkdir(struct inode *dir, struct dentry *dentry, int mode) -+{ -+ int err, rerr; -+ aufs_bindex_t bindex; -+ unsigned char diropq; -+ struct path h_path; -+ struct dentry *wh_dentry, *parent, *opq_dentry; -+ struct mutex *h_mtx; -+ struct super_block *sb; -+ struct { -+ struct au_pin pin; -+ struct au_dtime dt; -+ } *a; /* reduce the stack usage */ -+ struct au_wr_dir_args wr_dir_args = { -+ .force_btgt = -1, -+ .flags = AuWrDir_ADD_ENTRY | AuWrDir_ISDIR -+ }; -+ -+ IMustLock(dir); -+ -+ err = -ENOMEM; -+ a = kmalloc(sizeof(*a), GFP_NOFS); -+ if (unlikely(!a)) -+ goto out; -+ -+ err = aufs_read_lock(dentry, AuLock_DW | AuLock_GEN); -+ if (unlikely(err)) -+ goto out_free; -+ err = au_d_may_add(dentry); -+ if (unlikely(err)) -+ goto out_unlock; -+ -+ parent = dentry->d_parent; /* dir inode is locked */ -+ di_write_lock_parent(parent); -+ wh_dentry = lock_hdir_lkup_wh(dentry, &a->dt, /*src_dentry*/NULL, -+ &a->pin, &wr_dir_args); -+ err = PTR_ERR(wh_dentry); -+ if (IS_ERR(wh_dentry)) -+ goto out_parent; -+ -+ sb = dentry->d_sb; -+ bindex = au_dbstart(dentry); -+ h_path.dentry = au_h_dptr(dentry, bindex); -+ h_path.mnt = au_sbr_mnt(sb, bindex); -+ err = vfsub_mkdir(au_pinned_h_dir(&a->pin), &h_path, mode); -+ if (unlikely(err)) -+ goto out_unpin; -+ -+ /* make the dir opaque */ -+ diropq = 0; -+ h_mtx = &h_path.dentry->d_inode->i_mutex; -+ if (wh_dentry -+ || au_opt_test(au_mntflags(sb), ALWAYS_DIROPQ)) { -+ mutex_lock_nested(h_mtx, AuLsc_I_CHILD); -+ opq_dentry = au_diropq_create(dentry, bindex); -+ mutex_unlock(h_mtx); -+ err = PTR_ERR(opq_dentry); -+ if (IS_ERR(opq_dentry)) -+ goto out_dir; -+ dput(opq_dentry); -+ diropq = 1; -+ } -+ -+ err = epilog(dir, bindex, wh_dentry, dentry); -+ if (!err) { -+ inc_nlink(dir); -+ goto out_unpin; /* success */ -+ } -+ -+ /* revert */ -+ if (diropq) { -+ AuLabel(revert opq); -+ mutex_lock_nested(h_mtx, AuLsc_I_CHILD); -+ rerr = au_diropq_remove(dentry, bindex); -+ mutex_unlock(h_mtx); -+ if (rerr) { -+ AuIOErr("%.*s reverting diropq failed(%d, %d)\n", -+ AuDLNPair(dentry), err, rerr); -+ err = -EIO; -+ } -+ } -+ -+out_dir: -+ AuLabel(revert dir); -+ rerr = vfsub_rmdir(au_pinned_h_dir(&a->pin), &h_path); -+ if (rerr) { -+ AuIOErr("%.*s reverting dir failed(%d, %d)\n", -+ AuDLNPair(dentry), err, rerr); -+ err = -EIO; -+ } -+ au_dtime_revert(&a->dt); -+out_unpin: -+ au_unpin(&a->pin); -+ dput(wh_dentry); -+out_parent: -+ di_write_unlock(parent); -+out_unlock: -+ if (unlikely(err)) { -+ au_update_dbstart(dentry); -+ d_drop(dentry); -+ } -+ aufs_read_unlock(dentry, AuLock_DW); -+out_free: -+ kfree(a); -+out: -+ return err; -+} -diff -Nur linux-2.6.37.orig/fs/aufs/i_op_del.c linux-2.6.37/fs/aufs/i_op_del.c ---- linux-2.6.37.orig/fs/aufs/i_op_del.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/i_op_del.c 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,481 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * inode operations (del entry) -+ */ -+ -+#include "aufs.h" -+ -+/* -+ * decide if a new whiteout for @dentry is necessary or not. -+ * when it is necessary, prepare the parent dir for the upper branch whose -+ * branch index is @bcpup for creation. the actual creation of the whiteout will -+ * be done by caller. -+ * return value: -+ * 0: wh is unnecessary -+ * plus: wh is necessary -+ * minus: error -+ */ -+int au_wr_dir_need_wh(struct dentry *dentry, int isdir, aufs_bindex_t *bcpup) -+{ -+ int need_wh, err; -+ aufs_bindex_t bstart; -+ struct super_block *sb; -+ -+ sb = dentry->d_sb; -+ bstart = au_dbstart(dentry); -+ if (*bcpup < 0) { -+ *bcpup = bstart; -+ if (au_test_ro(sb, bstart, dentry->d_inode)) { -+ err = AuWbrCopyup(au_sbi(sb), dentry); -+ *bcpup = err; -+ if (unlikely(err < 0)) -+ goto out; -+ } -+ } else -+ AuDebugOn(bstart < *bcpup -+ || au_test_ro(sb, *bcpup, dentry->d_inode)); -+ AuDbg("bcpup %d, bstart %d\n", *bcpup, bstart); -+ -+ if (*bcpup != bstart) { -+ err = au_cpup_dirs(dentry, *bcpup); -+ if (unlikely(err)) -+ goto out; -+ need_wh = 1; -+ } else { -+ struct au_dinfo *dinfo, *tmp; -+ -+ need_wh = -ENOMEM; -+ dinfo = au_di(dentry); -+ tmp = au_di_alloc(sb, AuLsc_DI_TMP); -+ if (tmp) { -+ au_di_cp(tmp, dinfo); -+ au_di_swap(tmp, dinfo); -+ /* returns the number of positive dentries */ -+ need_wh = au_lkup_dentry(dentry, bstart + 1, /*type*/0, -+ /*nd*/NULL); -+ au_di_swap(tmp, dinfo); -+ au_rw_write_unlock(&tmp->di_rwsem); -+ au_di_free(tmp); -+ } -+ } -+ AuDbg("need_wh %d\n", need_wh); -+ err = need_wh; -+ -+out: -+ return err; -+} -+ -+/* -+ * simple tests for the del-entry operations. -+ * following the checks in vfs, plus the parent-child relationship. -+ */ -+int au_may_del(struct dentry *dentry, aufs_bindex_t bindex, -+ struct dentry *h_parent, int isdir) -+{ -+ int err; -+ umode_t h_mode; -+ struct dentry *h_dentry, *h_latest; -+ struct inode *h_inode; -+ -+ h_dentry = au_h_dptr(dentry, bindex); -+ h_inode = h_dentry->d_inode; -+ if (dentry->d_inode) { -+ err = -ENOENT; -+ if (unlikely(!h_inode || !h_inode->i_nlink)) -+ goto out; -+ -+ h_mode = h_inode->i_mode; -+ if (!isdir) { -+ err = -EISDIR; -+ if (unlikely(S_ISDIR(h_mode))) -+ goto out; -+ } else if (unlikely(!S_ISDIR(h_mode))) { -+ err = -ENOTDIR; -+ goto out; -+ } -+ } else { -+ /* rename(2) case */ -+ err = -EIO; -+ if (unlikely(h_inode)) -+ goto out; -+ } -+ -+ err = -ENOENT; -+ /* expected parent dir is locked */ -+ if (unlikely(h_parent != h_dentry->d_parent)) -+ goto out; -+ err = 0; -+ -+ /* -+ * rmdir a dir may break the consistency on some filesystem. -+ * let's try heavy test. -+ */ -+ err = -EACCES; -+ if (unlikely(au_test_h_perm(h_parent->d_inode, MAY_EXEC | MAY_WRITE))) -+ goto out; -+ -+ h_latest = au_sio_lkup_one(&dentry->d_name, h_parent, -+ au_sbr(dentry->d_sb, bindex)); -+ err = -EIO; -+ if (IS_ERR(h_latest)) -+ goto out; -+ if (h_latest == h_dentry) -+ err = 0; -+ dput(h_latest); -+ -+out: -+ return err; -+} -+ -+/* -+ * decide the branch where we operate for @dentry. the branch index will be set -+ * @rbcpup. after diciding it, 'pin' it and store the timestamps of the parent -+ * dir for reverting. -+ * when a new whiteout is necessary, create it. -+ */ -+static struct dentry* -+lock_hdir_create_wh(struct dentry *dentry, int isdir, aufs_bindex_t *rbcpup, -+ struct au_dtime *dt, struct au_pin *pin) -+{ -+ struct dentry *wh_dentry; -+ struct super_block *sb; -+ struct path h_path; -+ int err, need_wh; -+ unsigned int udba; -+ aufs_bindex_t bcpup; -+ -+ need_wh = au_wr_dir_need_wh(dentry, isdir, rbcpup); -+ wh_dentry = ERR_PTR(need_wh); -+ if (unlikely(need_wh < 0)) -+ goto out; -+ -+ sb = dentry->d_sb; -+ udba = au_opt_udba(sb); -+ bcpup = *rbcpup; -+ err = au_pin(pin, dentry, bcpup, udba, -+ AuPin_DI_LOCKED | AuPin_MNT_WRITE); -+ wh_dentry = ERR_PTR(err); -+ if (unlikely(err)) -+ goto out; -+ -+ h_path.dentry = au_pinned_h_parent(pin); -+ if (udba != AuOpt_UDBA_NONE -+ && au_dbstart(dentry) == bcpup) { -+ err = au_may_del(dentry, bcpup, h_path.dentry, isdir); -+ wh_dentry = ERR_PTR(err); -+ if (unlikely(err)) -+ goto out_unpin; -+ } -+ -+ h_path.mnt = au_sbr_mnt(sb, bcpup); -+ au_dtime_store(dt, au_pinned_parent(pin), &h_path); -+ wh_dentry = NULL; -+ if (!need_wh) -+ goto out; /* success, no need to create whiteout */ -+ -+ wh_dentry = au_wh_create(dentry, bcpup, h_path.dentry); -+ if (IS_ERR(wh_dentry)) -+ goto out_unpin; -+ -+ /* returns with the parent is locked and wh_dentry is dget-ed */ -+ goto out; /* success */ -+ -+out_unpin: -+ au_unpin(pin); -+out: -+ return wh_dentry; -+} -+ -+/* -+ * when removing a dir, rename it to a unique temporary whiteout-ed name first -+ * in order to be revertible and save time for removing many child whiteouts -+ * under the dir. -+ * returns 1 when there are too many child whiteout and caller should remove -+ * them asynchronously. returns 0 when the number of children is enough small to -+ * remove now or the branch fs is a remote fs. -+ * otherwise return an error. -+ */ -+static int renwh_and_rmdir(struct dentry *dentry, aufs_bindex_t bindex, -+ struct au_nhash *whlist, struct inode *dir) -+{ -+ int rmdir_later, err, dirwh; -+ struct dentry *h_dentry; -+ struct super_block *sb; -+ -+ sb = dentry->d_sb; -+ SiMustAnyLock(sb); -+ h_dentry = au_h_dptr(dentry, bindex); -+ err = au_whtmp_ren(h_dentry, au_sbr(sb, bindex)); -+ if (unlikely(err)) -+ goto out; -+ -+ /* stop monitoring */ -+ au_hn_free(au_hi(dentry->d_inode, bindex)); -+ -+ if (!au_test_fs_remote(h_dentry->d_sb)) { -+ dirwh = au_sbi(sb)->si_dirwh; -+ rmdir_later = (dirwh <= 1); -+ if (!rmdir_later) -+ rmdir_later = au_nhash_test_longer_wh(whlist, bindex, -+ dirwh); -+ if (rmdir_later) -+ return rmdir_later; -+ } -+ -+ err = au_whtmp_rmdir(dir, bindex, h_dentry, whlist); -+ if (unlikely(err)) { -+ AuIOErr("rmdir %.*s, b%d failed, %d. ignored\n", -+ AuDLNPair(h_dentry), bindex, err); -+ err = 0; -+ } -+ -+out: -+ AuTraceErr(err); -+ return err; -+} -+ -+/* -+ * final procedure for deleting a entry. -+ * maintain dentry and iattr. -+ */ -+static void epilog(struct inode *dir, struct dentry *dentry, -+ aufs_bindex_t bindex) -+{ -+ struct inode *inode; -+ -+ inode = dentry->d_inode; -+ d_drop(dentry); -+ inode->i_ctime = dir->i_ctime; -+ -+ if (au_ibstart(dir) == bindex) -+ au_cpup_attr_timesizes(dir); -+ dir->i_version++; -+} -+ -+/* -+ * when an error happened, remove the created whiteout and revert everything. -+ */ -+static int do_revert(int err, struct inode *dir, aufs_bindex_t bindex, -+ aufs_bindex_t bwh, struct dentry *wh_dentry, -+ struct dentry *dentry, struct au_dtime *dt) -+{ -+ int rerr; -+ struct path h_path = { -+ .dentry = wh_dentry, -+ .mnt = au_sbr_mnt(dir->i_sb, bindex) -+ }; -+ -+ rerr = au_wh_unlink_dentry(au_h_iptr(dir, bindex), &h_path, dentry); -+ if (!rerr) { -+ au_set_dbwh(dentry, bwh); -+ au_dtime_revert(dt); -+ return 0; -+ } -+ -+ AuIOErr("%.*s reverting whiteout failed(%d, %d)\n", -+ AuDLNPair(dentry), err, rerr); -+ return -EIO; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+int aufs_unlink(struct inode *dir, struct dentry *dentry) -+{ -+ int err; -+ aufs_bindex_t bwh, bindex, bstart; -+ struct au_dtime dt; -+ struct au_pin pin; -+ struct path h_path; -+ struct inode *inode, *h_dir; -+ struct dentry *parent, *wh_dentry; -+ -+ IMustLock(dir); -+ -+ err = aufs_read_lock(dentry, AuLock_DW | AuLock_GEN); -+ if (unlikely(err)) -+ goto out; -+ err = au_d_hashed_positive(dentry); -+ if (unlikely(err)) -+ goto out_unlock; -+ inode = dentry->d_inode; -+ IMustLock(inode); -+ err = -EISDIR; -+ if (unlikely(S_ISDIR(inode->i_mode))) -+ goto out_unlock; /* possible? */ -+ -+ bstart = au_dbstart(dentry); -+ bwh = au_dbwh(dentry); -+ bindex = -1; -+ parent = dentry->d_parent; /* dir inode is locked */ -+ di_write_lock_parent(parent); -+ wh_dentry = lock_hdir_create_wh(dentry, /*isdir*/0, &bindex, &dt, &pin); -+ err = PTR_ERR(wh_dentry); -+ if (IS_ERR(wh_dentry)) -+ goto out_parent; -+ -+ h_path.mnt = au_sbr_mnt(dentry->d_sb, bstart); -+ h_path.dentry = au_h_dptr(dentry, bstart); -+ dget(h_path.dentry); -+ if (bindex == bstart) { -+ h_dir = au_pinned_h_dir(&pin); -+ err = vfsub_unlink(h_dir, &h_path, /*force*/0); -+ } else { -+ /* dir inode is locked */ -+ h_dir = wh_dentry->d_parent->d_inode; -+ IMustLock(h_dir); -+ err = 0; -+ } -+ -+ if (!err) { -+ vfsub_drop_nlink(inode); -+ epilog(dir, dentry, bindex); -+ -+ /* update target timestamps */ -+ if (bindex == bstart) { -+ vfsub_update_h_iattr(&h_path, /*did*/NULL); /*ignore*/ -+ inode->i_ctime = h_path.dentry->d_inode->i_ctime; -+ } else -+ /* todo: this timestamp may be reverted later */ -+ inode->i_ctime = h_dir->i_ctime; -+ goto out_unpin; /* success */ -+ } -+ -+ /* revert */ -+ if (wh_dentry) { -+ int rerr; -+ -+ rerr = do_revert(err, dir, bindex, bwh, wh_dentry, dentry, &dt); -+ if (rerr) -+ err = rerr; -+ } -+ -+out_unpin: -+ au_unpin(&pin); -+ dput(wh_dentry); -+ dput(h_path.dentry); -+out_parent: -+ di_write_unlock(parent); -+out_unlock: -+ aufs_read_unlock(dentry, AuLock_DW); -+out: -+ return err; -+} -+ -+int aufs_rmdir(struct inode *dir, struct dentry *dentry) -+{ -+ int err, rmdir_later; -+ aufs_bindex_t bwh, bindex, bstart; -+ struct au_dtime dt; -+ struct au_pin pin; -+ struct inode *inode; -+ struct dentry *parent, *wh_dentry, *h_dentry; -+ struct au_whtmp_rmdir *args; -+ -+ IMustLock(dir); -+ -+ err = aufs_read_lock(dentry, AuLock_DW | AuLock_FLUSH | AuLock_GEN); -+ if (unlikely(err)) -+ goto out; -+ -+ /* VFS already unhashes it */ -+ inode = dentry->d_inode; -+ err = -ENOENT; -+ if (unlikely(!inode || !inode->i_nlink -+ || IS_DEADDIR(inode))) -+ goto out_unlock; -+ IMustLock(inode); -+ err = -ENOTDIR; -+ if (unlikely(!S_ISDIR(inode->i_mode))) -+ goto out_unlock; /* possible? */ -+ -+ err = -ENOMEM; -+ args = au_whtmp_rmdir_alloc(dir->i_sb, GFP_NOFS); -+ if (unlikely(!args)) -+ goto out_unlock; -+ -+ parent = dentry->d_parent; /* dir inode is locked */ -+ di_write_lock_parent(parent); -+ err = au_test_empty(dentry, &args->whlist); -+ if (unlikely(err)) -+ goto out_parent; -+ -+ bstart = au_dbstart(dentry); -+ bwh = au_dbwh(dentry); -+ bindex = -1; -+ wh_dentry = lock_hdir_create_wh(dentry, /*isdir*/1, &bindex, &dt, &pin); -+ err = PTR_ERR(wh_dentry); -+ if (IS_ERR(wh_dentry)) -+ goto out_parent; -+ -+ h_dentry = au_h_dptr(dentry, bstart); -+ dget(h_dentry); -+ rmdir_later = 0; -+ if (bindex == bstart) { -+ err = renwh_and_rmdir(dentry, bstart, &args->whlist, dir); -+ if (err > 0) { -+ rmdir_later = err; -+ err = 0; -+ } -+ } else { -+ /* stop monitoring */ -+ au_hn_free(au_hi(inode, bstart)); -+ -+ /* dir inode is locked */ -+ IMustLock(wh_dentry->d_parent->d_inode); -+ err = 0; -+ } -+ -+ if (!err) { -+ vfsub_dead_dir(inode); -+ au_set_dbdiropq(dentry, -1); -+ epilog(dir, dentry, bindex); -+ -+ if (rmdir_later) { -+ au_whtmp_kick_rmdir(dir, bstart, h_dentry, args); -+ args = NULL; -+ } -+ -+ goto out_unpin; /* success */ -+ } -+ -+ /* revert */ -+ AuLabel(revert); -+ if (wh_dentry) { -+ int rerr; -+ -+ rerr = do_revert(err, dir, bindex, bwh, wh_dentry, dentry, &dt); -+ if (rerr) -+ err = rerr; -+ } -+ -+out_unpin: -+ au_unpin(&pin); -+ dput(wh_dentry); -+ dput(h_dentry); -+out_parent: -+ di_write_unlock(parent); -+ if (args) -+ au_whtmp_rmdir_free(args); -+out_unlock: -+ aufs_read_unlock(dentry, AuLock_DW); -+out: -+ AuTraceErr(err); -+ return err; -+} -diff -Nur linux-2.6.37.orig/fs/aufs/i_op_ren.c linux-2.6.37/fs/aufs/i_op_ren.c ---- linux-2.6.37.orig/fs/aufs/i_op_ren.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/i_op_ren.c 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,1017 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * inode operation (rename entry) -+ * todo: this is crazy monster -+ */ -+ -+#include "aufs.h" -+ -+enum { AuSRC, AuDST, AuSrcDst }; -+enum { AuPARENT, AuCHILD, AuParentChild }; -+ -+#define AuRen_ISDIR 1 -+#define AuRen_ISSAMEDIR (1 << 1) -+#define AuRen_WHSRC (1 << 2) -+#define AuRen_WHDST (1 << 3) -+#define AuRen_MNT_WRITE (1 << 4) -+#define AuRen_DT_DSTDIR (1 << 5) -+#define AuRen_DIROPQ (1 << 6) -+#define AuRen_CPUP (1 << 7) -+#define au_ftest_ren(flags, name) ((flags) & AuRen_##name) -+#define au_fset_ren(flags, name) \ -+ do { (flags) |= AuRen_##name; } while (0) -+#define au_fclr_ren(flags, name) \ -+ do { (flags) &= ~AuRen_##name; } while (0) -+ -+struct au_ren_args { -+ struct { -+ struct dentry *dentry, *h_dentry, *parent, *h_parent, -+ *wh_dentry; -+ struct inode *dir, *inode; -+ struct au_hinode *hdir; -+ struct au_dtime dt[AuParentChild]; -+ aufs_bindex_t bstart; -+ } sd[AuSrcDst]; -+ -+#define src_dentry sd[AuSRC].dentry -+#define src_dir sd[AuSRC].dir -+#define src_inode sd[AuSRC].inode -+#define src_h_dentry sd[AuSRC].h_dentry -+#define src_parent sd[AuSRC].parent -+#define src_h_parent sd[AuSRC].h_parent -+#define src_wh_dentry sd[AuSRC].wh_dentry -+#define src_hdir sd[AuSRC].hdir -+#define src_h_dir sd[AuSRC].hdir->hi_inode -+#define src_dt sd[AuSRC].dt -+#define src_bstart sd[AuSRC].bstart -+ -+#define dst_dentry sd[AuDST].dentry -+#define dst_dir sd[AuDST].dir -+#define dst_inode sd[AuDST].inode -+#define dst_h_dentry sd[AuDST].h_dentry -+#define dst_parent sd[AuDST].parent -+#define dst_h_parent sd[AuDST].h_parent -+#define dst_wh_dentry sd[AuDST].wh_dentry -+#define dst_hdir sd[AuDST].hdir -+#define dst_h_dir sd[AuDST].hdir->hi_inode -+#define dst_dt sd[AuDST].dt -+#define dst_bstart sd[AuDST].bstart -+ -+ struct dentry *h_trap; -+ struct au_branch *br; -+ struct au_hinode *src_hinode; -+ struct path h_path; -+ struct au_nhash whlist; -+ aufs_bindex_t btgt, src_bwh, src_bdiropq; -+ -+ unsigned int flags; -+ -+ struct au_whtmp_rmdir *thargs; -+ struct dentry *h_dst; -+}; -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * functions for reverting. -+ * when an error happened in a single rename systemcall, we should revert -+ * everything as if nothing happend. -+ * we don't need to revert the copied-up/down the parent dir since they are -+ * harmless. -+ */ -+ -+#define RevertFailure(fmt, ...) do { \ -+ AuIOErr("revert failure: " fmt " (%d, %d)\n", \ -+ ##__VA_ARGS__, err, rerr); \ -+ err = -EIO; \ -+} while (0) -+ -+static void au_ren_rev_diropq(int err, struct au_ren_args *a) -+{ -+ int rerr; -+ -+ au_hn_imtx_lock_nested(a->src_hinode, AuLsc_I_CHILD); -+ rerr = au_diropq_remove(a->src_dentry, a->btgt); -+ au_hn_imtx_unlock(a->src_hinode); -+ au_set_dbdiropq(a->src_dentry, a->src_bdiropq); -+ if (rerr) -+ RevertFailure("remove diropq %.*s", AuDLNPair(a->src_dentry)); -+} -+ -+static void au_ren_rev_rename(int err, struct au_ren_args *a) -+{ -+ int rerr; -+ -+ a->h_path.dentry = au_lkup_one(&a->src_dentry->d_name, a->src_h_parent, -+ a->br, /*nd*/NULL); -+ rerr = PTR_ERR(a->h_path.dentry); -+ if (IS_ERR(a->h_path.dentry)) { -+ RevertFailure("au_lkup_one %.*s", AuDLNPair(a->src_dentry)); -+ return; -+ } -+ -+ rerr = vfsub_rename(a->dst_h_dir, -+ au_h_dptr(a->src_dentry, a->btgt), -+ a->src_h_dir, &a->h_path); -+ d_drop(a->h_path.dentry); -+ dput(a->h_path.dentry); -+ /* au_set_h_dptr(a->src_dentry, a->btgt, NULL); */ -+ if (rerr) -+ RevertFailure("rename %.*s", AuDLNPair(a->src_dentry)); -+} -+ -+static void au_ren_rev_cpup(int err, struct au_ren_args *a) -+{ -+ int rerr; -+ -+ a->h_path.dentry = a->dst_h_dentry; -+ rerr = vfsub_unlink(a->dst_h_dir, &a->h_path, /*force*/0); -+ au_set_h_dptr(a->src_dentry, a->btgt, NULL); -+ au_set_dbstart(a->src_dentry, a->src_bstart); -+ if (rerr) -+ RevertFailure("unlink %.*s", AuDLNPair(a->dst_h_dentry)); -+} -+ -+static void au_ren_rev_whtmp(int err, struct au_ren_args *a) -+{ -+ int rerr; -+ -+ a->h_path.dentry = au_lkup_one(&a->dst_dentry->d_name, a->dst_h_parent, -+ a->br, /*nd*/NULL); -+ rerr = PTR_ERR(a->h_path.dentry); -+ if (IS_ERR(a->h_path.dentry)) { -+ RevertFailure("lookup %.*s", AuDLNPair(a->dst_dentry)); -+ return; -+ } -+ if (a->h_path.dentry->d_inode) { -+ d_drop(a->h_path.dentry); -+ dput(a->h_path.dentry); -+ return; -+ } -+ -+ rerr = vfsub_rename(a->dst_h_dir, a->h_dst, a->dst_h_dir, &a->h_path); -+ d_drop(a->h_path.dentry); -+ dput(a->h_path.dentry); -+ if (!rerr) -+ au_set_h_dptr(a->dst_dentry, a->btgt, dget(a->h_dst)); -+ else -+ RevertFailure("rename %.*s", AuDLNPair(a->h_dst)); -+} -+ -+static void au_ren_rev_whsrc(int err, struct au_ren_args *a) -+{ -+ int rerr; -+ -+ a->h_path.dentry = a->src_wh_dentry; -+ rerr = au_wh_unlink_dentry(a->src_h_dir, &a->h_path, a->src_dentry); -+ au_set_dbwh(a->src_dentry, a->src_bwh); -+ if (rerr) -+ RevertFailure("unlink %.*s", AuDLNPair(a->src_wh_dentry)); -+} -+#undef RevertFailure -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * when we have to copyup the renaming entry, do it with the rename-target name -+ * in order to minimize the cost (the later actual rename is unnecessary). -+ * otherwise rename it on the target branch. -+ */ -+static int au_ren_or_cpup(struct au_ren_args *a) -+{ -+ int err; -+ struct dentry *d; -+ -+ d = a->src_dentry; -+ if (au_dbstart(d) == a->btgt) { -+ a->h_path.dentry = a->dst_h_dentry; -+ if (au_ftest_ren(a->flags, DIROPQ) -+ && au_dbdiropq(d) == a->btgt) -+ au_fclr_ren(a->flags, DIROPQ); -+ AuDebugOn(au_dbstart(d) != a->btgt); -+ err = vfsub_rename(a->src_h_dir, au_h_dptr(d, a->btgt), -+ a->dst_h_dir, &a->h_path); -+ } else { -+ struct mutex *h_mtx = &a->src_h_dentry->d_inode->i_mutex; -+ struct file *h_file; -+ -+ au_fset_ren(a->flags, CPUP); -+ mutex_lock_nested(h_mtx, AuLsc_I_CHILD); -+ au_set_dbstart(d, a->btgt); -+ au_set_h_dptr(d, a->btgt, dget(a->dst_h_dentry)); -+ h_file = au_h_open_pre(d, a->src_bstart); -+ if (IS_ERR(h_file)) { -+ err = PTR_ERR(h_file); -+ h_file = NULL; -+ } else -+ err = au_sio_cpup_single(d, a->btgt, a->src_bstart, -1, -+ !AuCpup_DTIME, a->dst_parent); -+ mutex_unlock(h_mtx); -+ au_h_open_post(d, a->src_bstart, h_file); -+ if (!err) { -+ d = a->dst_dentry; -+ au_set_h_dptr(d, a->btgt, NULL); -+ au_update_dbstart(d); -+ } else { -+ au_set_h_dptr(d, a->btgt, NULL); -+ au_set_dbstart(d, a->src_bstart); -+ } -+ } -+ if (!err && a->h_dst) -+ /* it will be set to dinfo later */ -+ dget(a->h_dst); -+ -+ return err; -+} -+ -+/* cf. aufs_rmdir() */ -+static int au_ren_del_whtmp(struct au_ren_args *a) -+{ -+ int err; -+ struct inode *dir; -+ -+ dir = a->dst_dir; -+ SiMustAnyLock(dir->i_sb); -+ if (!au_nhash_test_longer_wh(&a->whlist, a->btgt, -+ au_sbi(dir->i_sb)->si_dirwh) -+ || au_test_fs_remote(a->h_dst->d_sb)) { -+ err = au_whtmp_rmdir(dir, a->btgt, a->h_dst, &a->whlist); -+ if (unlikely(err)) -+ pr_warning("failed removing whtmp dir %.*s (%d), " -+ "ignored.\n", AuDLNPair(a->h_dst), err); -+ } else { -+ au_nhash_wh_free(&a->thargs->whlist); -+ a->thargs->whlist = a->whlist; -+ a->whlist.nh_num = 0; -+ au_whtmp_kick_rmdir(dir, a->btgt, a->h_dst, a->thargs); -+ dput(a->h_dst); -+ a->thargs = NULL; -+ } -+ -+ return 0; -+} -+ -+/* make it 'opaque' dir. */ -+static int au_ren_diropq(struct au_ren_args *a) -+{ -+ int err; -+ struct dentry *diropq; -+ -+ err = 0; -+ a->src_bdiropq = au_dbdiropq(a->src_dentry); -+ a->src_hinode = au_hi(a->src_inode, a->btgt); -+ au_hn_imtx_lock_nested(a->src_hinode, AuLsc_I_CHILD); -+ diropq = au_diropq_create(a->src_dentry, a->btgt); -+ au_hn_imtx_unlock(a->src_hinode); -+ if (IS_ERR(diropq)) -+ err = PTR_ERR(diropq); -+ dput(diropq); -+ -+ return err; -+} -+ -+static int do_rename(struct au_ren_args *a) -+{ -+ int err; -+ struct dentry *d, *h_d; -+ -+ /* prepare workqueue args for asynchronous rmdir */ -+ h_d = a->dst_h_dentry; -+ if (au_ftest_ren(a->flags, ISDIR) && h_d->d_inode) { -+ err = -ENOMEM; -+ a->thargs = au_whtmp_rmdir_alloc(a->src_dentry->d_sb, GFP_NOFS); -+ if (unlikely(!a->thargs)) -+ goto out; -+ a->h_dst = dget(h_d); -+ } -+ -+ /* create whiteout for src_dentry */ -+ if (au_ftest_ren(a->flags, WHSRC)) { -+ a->src_bwh = au_dbwh(a->src_dentry); -+ AuDebugOn(a->src_bwh >= 0); -+ a->src_wh_dentry -+ = au_wh_create(a->src_dentry, a->btgt, a->src_h_parent); -+ err = PTR_ERR(a->src_wh_dentry); -+ if (IS_ERR(a->src_wh_dentry)) -+ goto out_thargs; -+ } -+ -+ /* lookup whiteout for dentry */ -+ if (au_ftest_ren(a->flags, WHDST)) { -+ h_d = au_wh_lkup(a->dst_h_parent, &a->dst_dentry->d_name, -+ a->br); -+ err = PTR_ERR(h_d); -+ if (IS_ERR(h_d)) -+ goto out_whsrc; -+ if (!h_d->d_inode) -+ dput(h_d); -+ else -+ a->dst_wh_dentry = h_d; -+ } -+ -+ /* rename dentry to tmpwh */ -+ if (a->thargs) { -+ err = au_whtmp_ren(a->dst_h_dentry, a->br); -+ if (unlikely(err)) -+ goto out_whdst; -+ -+ d = a->dst_dentry; -+ au_set_h_dptr(d, a->btgt, NULL); -+ err = au_lkup_neg(d, a->btgt); -+ if (unlikely(err)) -+ goto out_whtmp; -+ a->dst_h_dentry = au_h_dptr(d, a->btgt); -+ } -+ -+ /* cpup src */ -+ if (a->dst_h_dentry->d_inode && a->src_bstart != a->btgt) { -+ struct mutex *h_mtx = &a->src_h_dentry->d_inode->i_mutex; -+ struct file *h_file; -+ -+ mutex_lock_nested(h_mtx, AuLsc_I_CHILD); -+ AuDebugOn(au_dbstart(a->src_dentry) != a->src_bstart); -+ h_file = au_h_open_pre(a->src_dentry, a->src_bstart); -+ if (IS_ERR(h_file)) { -+ err = PTR_ERR(h_file); -+ h_file = NULL; -+ } else -+ err = au_sio_cpup_simple(a->src_dentry, a->btgt, -1, -+ !AuCpup_DTIME); -+ mutex_unlock(h_mtx); -+ au_h_open_post(a->src_dentry, a->src_bstart, h_file); -+ if (unlikely(err)) -+ goto out_whtmp; -+ } -+ -+ /* rename by vfs_rename or cpup */ -+ d = a->dst_dentry; -+ if (au_ftest_ren(a->flags, ISDIR) -+ && (a->dst_wh_dentry -+ || au_dbdiropq(d) == a->btgt -+ /* hide the lower to keep xino */ -+ || a->btgt < au_dbend(d) -+ || au_opt_test(au_mntflags(d->d_sb), ALWAYS_DIROPQ))) -+ au_fset_ren(a->flags, DIROPQ); -+ err = au_ren_or_cpup(a); -+ if (unlikely(err)) -+ /* leave the copied-up one */ -+ goto out_whtmp; -+ -+ /* make dir opaque */ -+ if (au_ftest_ren(a->flags, DIROPQ)) { -+ err = au_ren_diropq(a); -+ if (unlikely(err)) -+ goto out_rename; -+ } -+ -+ /* update target timestamps */ -+ AuDebugOn(au_dbstart(a->src_dentry) != a->btgt); -+ a->h_path.dentry = au_h_dptr(a->src_dentry, a->btgt); -+ vfsub_update_h_iattr(&a->h_path, /*did*/NULL); /*ignore*/ -+ a->src_inode->i_ctime = a->h_path.dentry->d_inode->i_ctime; -+ -+ /* remove whiteout for dentry */ -+ if (a->dst_wh_dentry) { -+ a->h_path.dentry = a->dst_wh_dentry; -+ err = au_wh_unlink_dentry(a->dst_h_dir, &a->h_path, -+ a->dst_dentry); -+ if (unlikely(err)) -+ goto out_diropq; -+ } -+ -+ /* remove whtmp */ -+ if (a->thargs) -+ au_ren_del_whtmp(a); /* ignore this error */ -+ -+ err = 0; -+ goto out_success; -+ -+out_diropq: -+ if (au_ftest_ren(a->flags, DIROPQ)) -+ au_ren_rev_diropq(err, a); -+out_rename: -+ if (!au_ftest_ren(a->flags, CPUP)) -+ au_ren_rev_rename(err, a); -+ else -+ au_ren_rev_cpup(err, a); -+ dput(a->h_dst); -+out_whtmp: -+ if (a->thargs) -+ au_ren_rev_whtmp(err, a); -+out_whdst: -+ dput(a->dst_wh_dentry); -+ a->dst_wh_dentry = NULL; -+out_whsrc: -+ if (a->src_wh_dentry) -+ au_ren_rev_whsrc(err, a); -+out_success: -+ dput(a->src_wh_dentry); -+ dput(a->dst_wh_dentry); -+out_thargs: -+ if (a->thargs) { -+ dput(a->h_dst); -+ au_whtmp_rmdir_free(a->thargs); -+ a->thargs = NULL; -+ } -+out: -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * test if @dentry dir can be rename destination or not. -+ * success means, it is a logically empty dir. -+ */ -+static int may_rename_dstdir(struct dentry *dentry, struct au_nhash *whlist) -+{ -+ return au_test_empty(dentry, whlist); -+} -+ -+/* -+ * test if @dentry dir can be rename source or not. -+ * if it can, return 0 and @children is filled. -+ * success means, -+ * - it is a logically empty dir. -+ * - or, it exists on writable branch and has no children including whiteouts -+ * on the lower branch. -+ */ -+static int may_rename_srcdir(struct dentry *dentry, aufs_bindex_t btgt) -+{ -+ int err; -+ unsigned int rdhash; -+ aufs_bindex_t bstart; -+ -+ bstart = au_dbstart(dentry); -+ if (bstart != btgt) { -+ struct au_nhash whlist; -+ -+ SiMustAnyLock(dentry->d_sb); -+ rdhash = au_sbi(dentry->d_sb)->si_rdhash; -+ if (!rdhash) -+ rdhash = au_rdhash_est(au_dir_size(/*file*/NULL, -+ dentry)); -+ err = au_nhash_alloc(&whlist, rdhash, GFP_NOFS); -+ if (unlikely(err)) -+ goto out; -+ err = au_test_empty(dentry, &whlist); -+ au_nhash_wh_free(&whlist); -+ goto out; -+ } -+ -+ if (bstart == au_dbtaildir(dentry)) -+ return 0; /* success */ -+ -+ err = au_test_empty_lower(dentry); -+ -+out: -+ if (err == -ENOTEMPTY) { -+ AuWarn1("renaming dir who has child(ren) on multiple branches," -+ " is not supported\n"); -+ err = -EXDEV; -+ } -+ return err; -+} -+ -+/* side effect: sets whlist and h_dentry */ -+static int au_ren_may_dir(struct au_ren_args *a) -+{ -+ int err; -+ unsigned int rdhash; -+ struct dentry *d; -+ -+ d = a->dst_dentry; -+ SiMustAnyLock(d->d_sb); -+ -+ err = 0; -+ if (au_ftest_ren(a->flags, ISDIR) && a->dst_inode) { -+ rdhash = au_sbi(d->d_sb)->si_rdhash; -+ if (!rdhash) -+ rdhash = au_rdhash_est(au_dir_size(/*file*/NULL, d)); -+ err = au_nhash_alloc(&a->whlist, rdhash, GFP_NOFS); -+ if (unlikely(err)) -+ goto out; -+ -+ au_set_dbstart(d, a->dst_bstart); -+ err = may_rename_dstdir(d, &a->whlist); -+ au_set_dbstart(d, a->btgt); -+ } -+ a->dst_h_dentry = au_h_dptr(d, au_dbstart(d)); -+ if (unlikely(err)) -+ goto out; -+ -+ d = a->src_dentry; -+ a->src_h_dentry = au_h_dptr(d, au_dbstart(d)); -+ if (au_ftest_ren(a->flags, ISDIR)) { -+ err = may_rename_srcdir(d, a->btgt); -+ if (unlikely(err)) { -+ au_nhash_wh_free(&a->whlist); -+ a->whlist.nh_num = 0; -+ } -+ } -+out: -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * simple tests for rename. -+ * following the checks in vfs, plus the parent-child relationship. -+ */ -+static int au_may_ren(struct au_ren_args *a) -+{ -+ int err, isdir; -+ struct inode *h_inode; -+ -+ if (a->src_bstart == a->btgt) { -+ err = au_may_del(a->src_dentry, a->btgt, a->src_h_parent, -+ au_ftest_ren(a->flags, ISDIR)); -+ if (unlikely(err)) -+ goto out; -+ err = -EINVAL; -+ if (unlikely(a->src_h_dentry == a->h_trap)) -+ goto out; -+ } -+ -+ err = 0; -+ if (a->dst_bstart != a->btgt) -+ goto out; -+ -+ err = -EIO; -+ h_inode = a->dst_h_dentry->d_inode; -+ isdir = !!au_ftest_ren(a->flags, ISDIR); -+ if (!a->dst_dentry->d_inode) { -+ if (unlikely(h_inode)) -+ goto out; -+ err = au_may_add(a->dst_dentry, a->btgt, a->dst_h_parent, -+ isdir); -+ } else { -+ if (unlikely(!h_inode || !h_inode->i_nlink)) -+ goto out; -+ err = au_may_del(a->dst_dentry, a->btgt, a->dst_h_parent, -+ isdir); -+ if (unlikely(err)) -+ goto out; -+ err = -ENOTEMPTY; -+ if (unlikely(a->dst_h_dentry == a->h_trap)) -+ goto out; -+ err = 0; -+ } -+ -+out: -+ if (unlikely(err == -ENOENT || err == -EEXIST)) -+ err = -EIO; -+ AuTraceErr(err); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * locking order -+ * (VFS) -+ * - src_dir and dir by lock_rename() -+ * - inode if exitsts -+ * (aufs) -+ * - lock all -+ * + src_dentry and dentry by aufs_read_and_write_lock2() which calls, -+ * + si_read_lock -+ * + di_write_lock2_child() -+ * + di_write_lock_child() -+ * + ii_write_lock_child() -+ * + di_write_lock_child2() -+ * + ii_write_lock_child2() -+ * + src_parent and parent -+ * + di_write_lock_parent() -+ * + ii_write_lock_parent() -+ * + di_write_lock_parent2() -+ * + ii_write_lock_parent2() -+ * + lower src_dir and dir by vfsub_lock_rename() -+ * + verify the every relationships between child and parent. if any -+ * of them failed, unlock all and return -EBUSY. -+ */ -+static void au_ren_unlock(struct au_ren_args *a) -+{ -+ struct super_block *sb; -+ -+ sb = a->dst_dentry->d_sb; -+ if (au_ftest_ren(a->flags, MNT_WRITE)) -+ mnt_drop_write(a->br->br_mnt); -+ vfsub_unlock_rename(a->src_h_parent, a->src_hdir, -+ a->dst_h_parent, a->dst_hdir); -+} -+ -+static int au_ren_lock(struct au_ren_args *a) -+{ -+ int err; -+ unsigned int udba; -+ -+ err = 0; -+ a->src_h_parent = au_h_dptr(a->src_parent, a->btgt); -+ a->src_hdir = au_hi(a->src_dir, a->btgt); -+ a->dst_h_parent = au_h_dptr(a->dst_parent, a->btgt); -+ a->dst_hdir = au_hi(a->dst_dir, a->btgt); -+ a->h_trap = vfsub_lock_rename(a->src_h_parent, a->src_hdir, -+ a->dst_h_parent, a->dst_hdir); -+ udba = au_opt_udba(a->src_dentry->d_sb); -+ if (unlikely(a->src_hdir->hi_inode != a->src_h_parent->d_inode -+ || a->dst_hdir->hi_inode != a->dst_h_parent->d_inode)) -+ err = au_busy_or_stale(); -+ if (!err && au_dbstart(a->src_dentry) == a->btgt) -+ err = au_h_verify(a->src_h_dentry, udba, -+ a->src_h_parent->d_inode, a->src_h_parent, -+ a->br); -+ if (!err && au_dbstart(a->dst_dentry) == a->btgt) -+ err = au_h_verify(a->dst_h_dentry, udba, -+ a->dst_h_parent->d_inode, a->dst_h_parent, -+ a->br); -+ if (!err) { -+ err = mnt_want_write(a->br->br_mnt); -+ if (unlikely(err)) -+ goto out_unlock; -+ au_fset_ren(a->flags, MNT_WRITE); -+ goto out; /* success */ -+ } -+ -+ err = au_busy_or_stale(); -+ -+out_unlock: -+ au_ren_unlock(a); -+out: -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static void au_ren_refresh_dir(struct au_ren_args *a) -+{ -+ struct inode *dir; -+ -+ dir = a->dst_dir; -+ dir->i_version++; -+ if (au_ftest_ren(a->flags, ISDIR)) { -+ /* is this updating defined in POSIX? */ -+ au_cpup_attr_timesizes(a->src_inode); -+ au_cpup_attr_nlink(dir, /*force*/1); -+ } -+ -+ if (au_ibstart(dir) == a->btgt) -+ au_cpup_attr_timesizes(dir); -+ -+ if (au_ftest_ren(a->flags, ISSAMEDIR)) -+ return; -+ -+ dir = a->src_dir; -+ dir->i_version++; -+ if (au_ftest_ren(a->flags, ISDIR)) -+ au_cpup_attr_nlink(dir, /*force*/1); -+ if (au_ibstart(dir) == a->btgt) -+ au_cpup_attr_timesizes(dir); -+} -+ -+static void au_ren_refresh(struct au_ren_args *a) -+{ -+ aufs_bindex_t bend, bindex; -+ struct dentry *d, *h_d; -+ struct inode *i, *h_i; -+ struct super_block *sb; -+ -+ d = a->dst_dentry; -+ d_drop(d); -+ if (a->h_dst) -+ /* already dget-ed by au_ren_or_cpup() */ -+ au_set_h_dptr(d, a->btgt, a->h_dst); -+ -+ i = a->dst_inode; -+ if (i) { -+ if (!au_ftest_ren(a->flags, ISDIR)) -+ vfsub_drop_nlink(i); -+ else { -+ vfsub_dead_dir(i); -+ au_cpup_attr_timesizes(i); -+ } -+ au_update_dbrange(d, /*do_put_zero*/1); -+ } else { -+ bend = a->btgt; -+ for (bindex = au_dbstart(d); bindex < bend; bindex++) -+ au_set_h_dptr(d, bindex, NULL); -+ bend = au_dbend(d); -+ for (bindex = a->btgt + 1; bindex <= bend; bindex++) -+ au_set_h_dptr(d, bindex, NULL); -+ au_update_dbrange(d, /*do_put_zero*/0); -+ } -+ -+ d = a->src_dentry; -+ au_set_dbwh(d, -1); -+ bend = au_dbend(d); -+ for (bindex = a->btgt + 1; bindex <= bend; bindex++) { -+ h_d = au_h_dptr(d, bindex); -+ if (h_d) -+ au_set_h_dptr(d, bindex, NULL); -+ } -+ au_set_dbend(d, a->btgt); -+ -+ sb = d->d_sb; -+ i = a->src_inode; -+ if (au_opt_test(au_mntflags(sb), PLINK) && au_plink_test(i)) -+ return; /* success */ -+ -+ bend = au_ibend(i); -+ for (bindex = a->btgt + 1; bindex <= bend; bindex++) { -+ h_i = au_h_iptr(i, bindex); -+ if (h_i) { -+ au_xino_write(sb, bindex, h_i->i_ino, /*ino*/0); -+ /* ignore this error */ -+ au_set_h_iptr(i, bindex, NULL, 0); -+ } -+ } -+ au_set_ibend(i, a->btgt); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* mainly for link(2) and rename(2) */ -+int au_wbr(struct dentry *dentry, aufs_bindex_t btgt) -+{ -+ aufs_bindex_t bdiropq, bwh; -+ struct dentry *parent; -+ struct au_branch *br; -+ -+ parent = dentry->d_parent; -+ IMustLock(parent->d_inode); /* dir is locked */ -+ -+ bdiropq = au_dbdiropq(parent); -+ bwh = au_dbwh(dentry); -+ br = au_sbr(dentry->d_sb, btgt); -+ if (au_br_rdonly(br) -+ || (0 <= bdiropq && bdiropq < btgt) -+ || (0 <= bwh && bwh < btgt)) -+ btgt = -1; -+ -+ AuDbg("btgt %d\n", btgt); -+ return btgt; -+} -+ -+/* sets src_bstart, dst_bstart and btgt */ -+static int au_ren_wbr(struct au_ren_args *a) -+{ -+ int err; -+ struct au_wr_dir_args wr_dir_args = { -+ /* .force_btgt = -1, */ -+ .flags = AuWrDir_ADD_ENTRY -+ }; -+ -+ a->src_bstart = au_dbstart(a->src_dentry); -+ a->dst_bstart = au_dbstart(a->dst_dentry); -+ if (au_ftest_ren(a->flags, ISDIR)) -+ au_fset_wrdir(wr_dir_args.flags, ISDIR); -+ wr_dir_args.force_btgt = a->src_bstart; -+ if (a->dst_inode && a->dst_bstart < a->src_bstart) -+ wr_dir_args.force_btgt = a->dst_bstart; -+ wr_dir_args.force_btgt = au_wbr(a->dst_dentry, wr_dir_args.force_btgt); -+ err = au_wr_dir(a->dst_dentry, a->src_dentry, &wr_dir_args); -+ a->btgt = err; -+ -+ return err; -+} -+ -+static void au_ren_dt(struct au_ren_args *a) -+{ -+ a->h_path.dentry = a->src_h_parent; -+ au_dtime_store(a->src_dt + AuPARENT, a->src_parent, &a->h_path); -+ if (!au_ftest_ren(a->flags, ISSAMEDIR)) { -+ a->h_path.dentry = a->dst_h_parent; -+ au_dtime_store(a->dst_dt + AuPARENT, a->dst_parent, &a->h_path); -+ } -+ -+ au_fclr_ren(a->flags, DT_DSTDIR); -+ if (!au_ftest_ren(a->flags, ISDIR)) -+ return; -+ -+ a->h_path.dentry = a->src_h_dentry; -+ au_dtime_store(a->src_dt + AuCHILD, a->src_dentry, &a->h_path); -+ if (a->dst_h_dentry->d_inode) { -+ au_fset_ren(a->flags, DT_DSTDIR); -+ a->h_path.dentry = a->dst_h_dentry; -+ au_dtime_store(a->dst_dt + AuCHILD, a->dst_dentry, &a->h_path); -+ } -+} -+ -+static void au_ren_rev_dt(int err, struct au_ren_args *a) -+{ -+ struct dentry *h_d; -+ struct mutex *h_mtx; -+ -+ au_dtime_revert(a->src_dt + AuPARENT); -+ if (!au_ftest_ren(a->flags, ISSAMEDIR)) -+ au_dtime_revert(a->dst_dt + AuPARENT); -+ -+ if (au_ftest_ren(a->flags, ISDIR) && err != -EIO) { -+ h_d = a->src_dt[AuCHILD].dt_h_path.dentry; -+ h_mtx = &h_d->d_inode->i_mutex; -+ mutex_lock_nested(h_mtx, AuLsc_I_CHILD); -+ au_dtime_revert(a->src_dt + AuCHILD); -+ mutex_unlock(h_mtx); -+ -+ if (au_ftest_ren(a->flags, DT_DSTDIR)) { -+ h_d = a->dst_dt[AuCHILD].dt_h_path.dentry; -+ h_mtx = &h_d->d_inode->i_mutex; -+ mutex_lock_nested(h_mtx, AuLsc_I_CHILD); -+ au_dtime_revert(a->dst_dt + AuCHILD); -+ mutex_unlock(h_mtx); -+ } -+ } -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+int aufs_rename(struct inode *_src_dir, struct dentry *_src_dentry, -+ struct inode *_dst_dir, struct dentry *_dst_dentry) -+{ -+ int err, flags; -+ /* reduce stack space */ -+ struct au_ren_args *a; -+ -+ AuDbg("%.*s, %.*s\n", AuDLNPair(_src_dentry), AuDLNPair(_dst_dentry)); -+ IMustLock(_src_dir); -+ IMustLock(_dst_dir); -+ -+ err = -ENOMEM; -+ BUILD_BUG_ON(sizeof(*a) > PAGE_SIZE); -+ a = kzalloc(sizeof(*a), GFP_NOFS); -+ if (unlikely(!a)) -+ goto out; -+ -+ a->src_dir = _src_dir; -+ a->src_dentry = _src_dentry; -+ a->src_inode = a->src_dentry->d_inode; -+ a->src_parent = a->src_dentry->d_parent; /* dir inode is locked */ -+ a->dst_dir = _dst_dir; -+ a->dst_dentry = _dst_dentry; -+ a->dst_inode = a->dst_dentry->d_inode; -+ a->dst_parent = a->dst_dentry->d_parent; /* dir inode is locked */ -+ if (a->dst_inode) { -+ IMustLock(a->dst_inode); -+ au_igrab(a->dst_inode); -+ } -+ -+ err = -ENOTDIR; -+ flags = AuLock_FLUSH | AuLock_NOPLM | AuLock_GEN; -+ if (S_ISDIR(a->src_inode->i_mode)) { -+ au_fset_ren(a->flags, ISDIR); -+ if (unlikely(a->dst_inode && !S_ISDIR(a->dst_inode->i_mode))) -+ goto out_free; -+ err = aufs_read_and_write_lock2(a->dst_dentry, a->src_dentry, -+ AuLock_DIR | flags); -+ } else -+ err = aufs_read_and_write_lock2(a->dst_dentry, a->src_dentry, -+ flags); -+ if (unlikely(err)) -+ goto out_free; -+ -+ err = au_d_hashed_positive(a->src_dentry); -+ if (unlikely(err)) -+ goto out_unlock; -+ err = -ENOENT; -+ if (a->dst_inode) { -+ /* -+ * If it is a dir, VFS unhash dst_dentry before this -+ * function. It means we cannot rely upon d_unhashed(). -+ */ -+ if (unlikely(!a->dst_inode->i_nlink)) -+ goto out_unlock; -+ if (!S_ISDIR(a->dst_inode->i_mode)) { -+ err = au_d_hashed_positive(a->dst_dentry); -+ if (unlikely(err)) -+ goto out_unlock; -+ } else if (unlikely(IS_DEADDIR(a->dst_inode))) -+ goto out_unlock; -+ } else if (unlikely(d_unhashed(a->dst_dentry))) -+ goto out_unlock; -+ -+ au_fset_ren(a->flags, ISSAMEDIR); /* temporary */ -+ di_write_lock_parent(a->dst_parent); -+ -+ /* which branch we process */ -+ err = au_ren_wbr(a); -+ if (unlikely(err < 0)) -+ goto out_parent; -+ a->br = au_sbr(a->dst_dentry->d_sb, a->btgt); -+ a->h_path.mnt = a->br->br_mnt; -+ -+ /* are they available to be renamed */ -+ err = au_ren_may_dir(a); -+ if (unlikely(err)) -+ goto out_children; -+ -+ /* prepare the writable parent dir on the same branch */ -+ if (a->dst_bstart == a->btgt) { -+ au_fset_ren(a->flags, WHDST); -+ } else { -+ err = au_cpup_dirs(a->dst_dentry, a->btgt); -+ if (unlikely(err)) -+ goto out_children; -+ } -+ -+ if (a->src_dir != a->dst_dir) { -+ /* -+ * this temporary unlock is safe, -+ * because both dir->i_mutex are locked. -+ */ -+ di_write_unlock(a->dst_parent); -+ di_write_lock_parent(a->src_parent); -+ err = au_wr_dir_need_wh(a->src_dentry, -+ au_ftest_ren(a->flags, ISDIR), -+ &a->btgt); -+ di_write_unlock(a->src_parent); -+ di_write_lock2_parent(a->src_parent, a->dst_parent, /*isdir*/1); -+ au_fclr_ren(a->flags, ISSAMEDIR); -+ } else -+ err = au_wr_dir_need_wh(a->src_dentry, -+ au_ftest_ren(a->flags, ISDIR), -+ &a->btgt); -+ if (unlikely(err < 0)) -+ goto out_children; -+ if (err) -+ au_fset_ren(a->flags, WHSRC); -+ -+ /* lock them all */ -+ err = au_ren_lock(a); -+ if (unlikely(err)) -+ goto out_children; -+ -+ if (!au_opt_test(au_mntflags(a->dst_dir->i_sb), UDBA_NONE)) -+ err = au_may_ren(a); -+ else if (unlikely(a->dst_dentry->d_name.len > AUFS_MAX_NAMELEN)) -+ err = -ENAMETOOLONG; -+ if (unlikely(err)) -+ goto out_hdir; -+ -+ /* store timestamps to be revertible */ -+ au_ren_dt(a); -+ -+ /* here we go */ -+ err = do_rename(a); -+ if (unlikely(err)) -+ goto out_dt; -+ -+ /* update dir attributes */ -+ au_ren_refresh_dir(a); -+ -+ /* dput/iput all lower dentries */ -+ au_ren_refresh(a); -+ -+ goto out_hdir; /* success */ -+ -+out_dt: -+ au_ren_rev_dt(err, a); -+out_hdir: -+ au_ren_unlock(a); -+out_children: -+ au_nhash_wh_free(&a->whlist); -+ if (err && a->dst_inode && a->dst_bstart != a->btgt) { -+ AuDbg("bstart %d, btgt %d\n", a->dst_bstart, a->btgt); -+ au_set_h_dptr(a->dst_dentry, a->btgt, NULL); -+ au_set_dbstart(a->dst_dentry, a->dst_bstart); -+ } -+out_parent: -+ if (!err) -+ d_move(a->src_dentry, a->dst_dentry); -+ else { -+ au_update_dbstart(a->dst_dentry); -+ if (!a->dst_inode) -+ d_drop(a->dst_dentry); -+ } -+ if (au_ftest_ren(a->flags, ISSAMEDIR)) -+ di_write_unlock(a->dst_parent); -+ else -+ di_write_unlock2(a->src_parent, a->dst_parent); -+out_unlock: -+ aufs_read_and_write_unlock2(a->dst_dentry, a->src_dentry); -+out_free: -+ iput(a->dst_inode); -+ if (a->thargs) -+ au_whtmp_rmdir_free(a->thargs); -+ kfree(a); -+out: -+ AuTraceErr(err); -+ return err; -+} -diff -Nur linux-2.6.37.orig/fs/aufs/iinfo.c linux-2.6.37/fs/aufs/iinfo.c ---- linux-2.6.37.orig/fs/aufs/iinfo.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/iinfo.c 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,263 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * inode private data -+ */ -+ -+#include "aufs.h" -+ -+struct inode *au_h_iptr(struct inode *inode, aufs_bindex_t bindex) -+{ -+ struct inode *h_inode; -+ -+ IiMustAnyLock(inode); -+ -+ h_inode = au_ii(inode)->ii_hinode[0 + bindex].hi_inode; -+ AuDebugOn(h_inode && atomic_read(&h_inode->i_count) <= 0); -+ return h_inode; -+} -+ -+/* todo: hard/soft set? */ -+void au_hiput(struct au_hinode *hinode) -+{ -+ au_hn_free(hinode); -+ dput(hinode->hi_whdentry); -+ iput(hinode->hi_inode); -+} -+ -+unsigned int au_hi_flags(struct inode *inode, int isdir) -+{ -+ unsigned int flags; -+ const unsigned int mnt_flags = au_mntflags(inode->i_sb); -+ -+ flags = 0; -+ if (au_opt_test(mnt_flags, XINO)) -+ au_fset_hi(flags, XINO); -+ if (isdir && au_opt_test(mnt_flags, UDBA_HNOTIFY)) -+ au_fset_hi(flags, HNOTIFY); -+ return flags; -+} -+ -+void au_set_h_iptr(struct inode *inode, aufs_bindex_t bindex, -+ struct inode *h_inode, unsigned int flags) -+{ -+ struct au_hinode *hinode; -+ struct inode *hi; -+ struct au_iinfo *iinfo = au_ii(inode); -+ -+ IiMustWriteLock(inode); -+ -+ hinode = iinfo->ii_hinode + bindex; -+ hi = hinode->hi_inode; -+ AuDebugOn(h_inode && atomic_read(&h_inode->i_count) <= 0); -+ -+ if (hi) -+ au_hiput(hinode); -+ hinode->hi_inode = h_inode; -+ if (h_inode) { -+ int err; -+ struct super_block *sb = inode->i_sb; -+ struct au_branch *br; -+ -+ AuDebugOn(inode->i_mode -+ && (h_inode->i_mode & S_IFMT) -+ != (inode->i_mode & S_IFMT)); -+ if (bindex == iinfo->ii_bstart) -+ au_cpup_igen(inode, h_inode); -+ br = au_sbr(sb, bindex); -+ hinode->hi_id = br->br_id; -+ if (au_ftest_hi(flags, XINO)) { -+ err = au_xino_write(sb, bindex, h_inode->i_ino, -+ inode->i_ino); -+ if (unlikely(err)) -+ AuIOErr1("failed au_xino_write() %d\n", err); -+ } -+ -+ if (au_ftest_hi(flags, HNOTIFY) -+ && au_br_hnotifyable(br->br_perm)) { -+ err = au_hn_alloc(hinode, inode); -+ if (unlikely(err)) -+ AuIOErr1("au_hn_alloc() %d\n", err); -+ } -+ } -+} -+ -+void au_set_hi_wh(struct inode *inode, aufs_bindex_t bindex, -+ struct dentry *h_wh) -+{ -+ struct au_hinode *hinode; -+ -+ IiMustWriteLock(inode); -+ -+ hinode = au_ii(inode)->ii_hinode + bindex; -+ AuDebugOn(hinode->hi_whdentry); -+ hinode->hi_whdentry = h_wh; -+} -+ -+void au_update_iigen(struct inode *inode) -+{ -+ atomic_set(&au_ii(inode)->ii_generation, au_sigen(inode->i_sb)); -+ /* smp_mb(); */ /* atomic_set */ -+} -+ -+/* it may be called at remount time, too */ -+void au_update_ibrange(struct inode *inode, int do_put_zero) -+{ -+ struct au_iinfo *iinfo; -+ aufs_bindex_t bindex, bend; -+ -+ iinfo = au_ii(inode); -+ if (!iinfo) -+ return; -+ -+ IiMustWriteLock(inode); -+ -+ if (do_put_zero && iinfo->ii_bstart >= 0) { -+ for (bindex = iinfo->ii_bstart; bindex <= iinfo->ii_bend; -+ bindex++) { -+ struct inode *h_i; -+ -+ h_i = iinfo->ii_hinode[0 + bindex].hi_inode; -+ if (h_i && !h_i->i_nlink) -+ au_set_h_iptr(inode, bindex, NULL, 0); -+ } -+ } -+ -+ iinfo->ii_bstart = -1; -+ iinfo->ii_bend = -1; -+ bend = au_sbend(inode->i_sb); -+ for (bindex = 0; bindex <= bend; bindex++) -+ if (iinfo->ii_hinode[0 + bindex].hi_inode) { -+ iinfo->ii_bstart = bindex; -+ break; -+ } -+ if (iinfo->ii_bstart >= 0) -+ for (bindex = bend; bindex >= iinfo->ii_bstart; bindex--) -+ if (iinfo->ii_hinode[0 + bindex].hi_inode) { -+ iinfo->ii_bend = bindex; -+ break; -+ } -+ AuDebugOn(iinfo->ii_bstart > iinfo->ii_bend); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+void au_icntnr_init_once(void *_c) -+{ -+ struct au_icntnr *c = _c; -+ struct au_iinfo *iinfo = &c->iinfo; -+ static struct lock_class_key aufs_ii; -+ -+ au_rw_init(&iinfo->ii_rwsem); -+ au_rw_class(&iinfo->ii_rwsem, &aufs_ii); -+ inode_init_once(&c->vfs_inode); -+} -+ -+int au_iinfo_init(struct inode *inode) -+{ -+ struct au_iinfo *iinfo; -+ struct super_block *sb; -+ int nbr, i; -+ -+ sb = inode->i_sb; -+ iinfo = &(container_of(inode, struct au_icntnr, vfs_inode)->iinfo); -+ nbr = au_sbend(sb) + 1; -+ if (unlikely(nbr <= 0)) -+ nbr = 1; -+ iinfo->ii_hinode = kcalloc(nbr, sizeof(*iinfo->ii_hinode), GFP_NOFS); -+ if (iinfo->ii_hinode) { -+ au_ninodes_inc(sb); -+ for (i = 0; i < nbr; i++) -+ iinfo->ii_hinode[i].hi_id = -1; -+ -+ atomic_set(&iinfo->ii_generation, au_sigen(sb)); -+ /* smp_mb(); */ /* atomic_set */ -+ iinfo->ii_bstart = -1; -+ iinfo->ii_bend = -1; -+ iinfo->ii_vdir = NULL; -+ return 0; -+ } -+ return -ENOMEM; -+} -+ -+int au_ii_realloc(struct au_iinfo *iinfo, int nbr) -+{ -+ int err, sz; -+ struct au_hinode *hip; -+ -+ AuRwMustWriteLock(&iinfo->ii_rwsem); -+ -+ err = -ENOMEM; -+ sz = sizeof(*hip) * (iinfo->ii_bend + 1); -+ if (!sz) -+ sz = sizeof(*hip); -+ hip = au_kzrealloc(iinfo->ii_hinode, sz, sizeof(*hip) * nbr, GFP_NOFS); -+ if (hip) { -+ iinfo->ii_hinode = hip; -+ err = 0; -+ } -+ -+ return err; -+} -+ -+void au_iinfo_fin(struct inode *inode) -+{ -+ struct au_iinfo *iinfo; -+ struct au_hinode *hi; -+ struct super_block *sb; -+ aufs_bindex_t bindex, bend; -+ const unsigned char unlinked = !inode->i_nlink; -+ -+ iinfo = au_ii(inode); -+ /* bad_inode case */ -+ if (!iinfo) -+ return; -+ -+ sb = inode->i_sb; -+ au_ninodes_dec(sb); -+ if (si_pid_test(sb)) -+ au_xino_delete_inode(inode, unlinked); -+ else { -+ /* -+ * it is safe to hide the dependency between sbinfo and -+ * sb->s_umount. -+ */ -+ lockdep_off(); -+ si_noflush_read_lock(sb); -+ au_xino_delete_inode(inode, unlinked); -+ si_read_unlock(sb); -+ lockdep_on(); -+ } -+ -+ if (iinfo->ii_vdir) -+ au_vdir_free(iinfo->ii_vdir); -+ -+ bindex = iinfo->ii_bstart; -+ if (bindex >= 0) { -+ hi = iinfo->ii_hinode + bindex; -+ bend = iinfo->ii_bend; -+ while (bindex++ <= bend) { -+ if (hi->hi_inode) -+ au_hiput(hi); -+ hi++; -+ } -+ } -+ kfree(iinfo->ii_hinode); -+ AuRwDestroy(&iinfo->ii_rwsem); -+} -diff -Nur linux-2.6.37.orig/fs/aufs/inode.c linux-2.6.37/fs/aufs/inode.c ---- linux-2.6.37.orig/fs/aufs/inode.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/inode.c 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,471 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * inode functions -+ */ -+ -+#include "aufs.h" -+ -+struct inode *au_igrab(struct inode *inode) -+{ -+ if (inode) { -+ AuDebugOn(!atomic_read(&inode->i_count)); -+ atomic_inc(&inode->i_count); -+ } -+ return inode; -+} -+ -+static void au_refresh_hinode_attr(struct inode *inode, int do_version) -+{ -+ au_cpup_attr_all(inode, /*force*/0); -+ au_update_iigen(inode); -+ if (do_version) -+ inode->i_version++; -+} -+ -+static int au_ii_refresh(struct inode *inode, int *update) -+{ -+ int err, e; -+ umode_t type; -+ aufs_bindex_t bindex, new_bindex; -+ struct super_block *sb; -+ struct au_iinfo *iinfo; -+ struct au_hinode *p, *q, tmp; -+ -+ IiMustWriteLock(inode); -+ -+ *update = 0; -+ sb = inode->i_sb; -+ type = inode->i_mode & S_IFMT; -+ iinfo = au_ii(inode); -+ err = au_ii_realloc(iinfo, au_sbend(sb) + 1); -+ if (unlikely(err)) -+ goto out; -+ -+ AuDebugOn(iinfo->ii_bstart < 0); -+ p = iinfo->ii_hinode + iinfo->ii_bstart; -+ for (bindex = iinfo->ii_bstart; bindex <= iinfo->ii_bend; -+ bindex++, p++) { -+ if (!p->hi_inode) -+ continue; -+ -+ AuDebugOn(type != (p->hi_inode->i_mode & S_IFMT)); -+ new_bindex = au_br_index(sb, p->hi_id); -+ if (new_bindex == bindex) -+ continue; -+ -+ if (new_bindex < 0) { -+ *update = 1; -+ au_hiput(p); -+ p->hi_inode = NULL; -+ continue; -+ } -+ -+ if (new_bindex < iinfo->ii_bstart) -+ iinfo->ii_bstart = new_bindex; -+ if (iinfo->ii_bend < new_bindex) -+ iinfo->ii_bend = new_bindex; -+ /* swap two lower inode, and loop again */ -+ q = iinfo->ii_hinode + new_bindex; -+ tmp = *q; -+ *q = *p; -+ *p = tmp; -+ if (tmp.hi_inode) { -+ bindex--; -+ p--; -+ } -+ } -+ au_update_ibrange(inode, /*do_put_zero*/0); -+ e = au_dy_irefresh(inode); -+ if (unlikely(e && !err)) -+ err = e; -+ -+out: -+ AuTraceErr(err); -+ return err; -+} -+ -+int au_refresh_hinode_self(struct inode *inode) -+{ -+ int err, update; -+ -+ err = au_ii_refresh(inode, &update); -+ if (!err) -+ au_refresh_hinode_attr(inode, update && S_ISDIR(inode->i_mode)); -+ -+ AuTraceErr(err); -+ return err; -+} -+ -+int au_refresh_hinode(struct inode *inode, struct dentry *dentry) -+{ -+ int err, e, update; -+ unsigned int flags; -+ umode_t mode; -+ aufs_bindex_t bindex, bend; -+ unsigned char isdir; -+ struct au_hinode *p; -+ struct au_iinfo *iinfo; -+ -+ err = au_ii_refresh(inode, &update); -+ if (unlikely(err)) -+ goto out; -+ -+ update = 0; -+ iinfo = au_ii(inode); -+ p = iinfo->ii_hinode + iinfo->ii_bstart; -+ mode = (inode->i_mode & S_IFMT); -+ isdir = S_ISDIR(mode); -+ flags = au_hi_flags(inode, isdir); -+ bend = au_dbend(dentry); -+ for (bindex = au_dbstart(dentry); bindex <= bend; bindex++) { -+ struct inode *h_i; -+ struct dentry *h_d; -+ -+ h_d = au_h_dptr(dentry, bindex); -+ if (!h_d || !h_d->d_inode) -+ continue; -+ -+ AuDebugOn(mode != (h_d->d_inode->i_mode & S_IFMT)); -+ if (iinfo->ii_bstart <= bindex && bindex <= iinfo->ii_bend) { -+ h_i = au_h_iptr(inode, bindex); -+ if (h_i) { -+ if (h_i == h_d->d_inode) -+ continue; -+ err = -EIO; -+ break; -+ } -+ } -+ if (bindex < iinfo->ii_bstart) -+ iinfo->ii_bstart = bindex; -+ if (iinfo->ii_bend < bindex) -+ iinfo->ii_bend = bindex; -+ au_set_h_iptr(inode, bindex, au_igrab(h_d->d_inode), flags); -+ update = 1; -+ } -+ au_update_ibrange(inode, /*do_put_zero*/0); -+ e = au_dy_irefresh(inode); -+ if (unlikely(e && !err)) -+ err = e; -+ if (!err) -+ au_refresh_hinode_attr(inode, update && isdir); -+ -+out: -+ AuTraceErr(err); -+ return err; -+} -+ -+static int set_inode(struct inode *inode, struct dentry *dentry) -+{ -+ int err; -+ unsigned int flags; -+ umode_t mode; -+ aufs_bindex_t bindex, bstart, btail; -+ unsigned char isdir; -+ struct dentry *h_dentry; -+ struct inode *h_inode; -+ struct au_iinfo *iinfo; -+ -+ IiMustWriteLock(inode); -+ -+ err = 0; -+ isdir = 0; -+ bstart = au_dbstart(dentry); -+ h_inode = au_h_dptr(dentry, bstart)->d_inode; -+ mode = h_inode->i_mode; -+ switch (mode & S_IFMT) { -+ case S_IFREG: -+ btail = au_dbtail(dentry); -+ inode->i_op = &aufs_iop; -+ inode->i_fop = &aufs_file_fop; -+ err = au_dy_iaop(inode, bstart, h_inode); -+ if (unlikely(err)) -+ goto out; -+ break; -+ case S_IFDIR: -+ isdir = 1; -+ btail = au_dbtaildir(dentry); -+ inode->i_op = &aufs_dir_iop; -+ inode->i_fop = &aufs_dir_fop; -+ break; -+ case S_IFLNK: -+ btail = au_dbtail(dentry); -+ inode->i_op = &aufs_symlink_iop; -+ break; -+ case S_IFBLK: -+ case S_IFCHR: -+ case S_IFIFO: -+ case S_IFSOCK: -+ btail = au_dbtail(dentry); -+ inode->i_op = &aufs_iop; -+ au_init_special_fop(inode, mode, h_inode->i_rdev); -+ break; -+ default: -+ AuIOErr("Unknown file type 0%o\n", mode); -+ err = -EIO; -+ goto out; -+ } -+ -+ /* do not set hnotify for whiteouted dirs (SHWH mode) */ -+ flags = au_hi_flags(inode, isdir); -+ if (au_opt_test(au_mntflags(dentry->d_sb), SHWH) -+ && au_ftest_hi(flags, HNOTIFY) -+ && dentry->d_name.len > AUFS_WH_PFX_LEN -+ && !memcmp(dentry->d_name.name, AUFS_WH_PFX, AUFS_WH_PFX_LEN)) -+ au_fclr_hi(flags, HNOTIFY); -+ iinfo = au_ii(inode); -+ iinfo->ii_bstart = bstart; -+ iinfo->ii_bend = btail; -+ for (bindex = bstart; bindex <= btail; bindex++) { -+ h_dentry = au_h_dptr(dentry, bindex); -+ if (h_dentry) -+ au_set_h_iptr(inode, bindex, -+ au_igrab(h_dentry->d_inode), flags); -+ } -+ au_cpup_attr_all(inode, /*force*/1); -+ -+out: -+ return err; -+} -+ -+/* -+ * successful returns with iinfo write_locked -+ * minus: errno -+ * zero: success, matched -+ * plus: no error, but unmatched -+ */ -+static int reval_inode(struct inode *inode, struct dentry *dentry) -+{ -+ int err; -+ aufs_bindex_t bindex, bend; -+ struct inode *h_inode, *h_dinode; -+ -+ /* -+ * before this function, if aufs got any iinfo lock, it must be only -+ * one, the parent dir. -+ * it can happen by UDBA and the obsoleted inode number. -+ */ -+ err = -EIO; -+ if (unlikely(inode->i_ino == parent_ino(dentry))) -+ goto out; -+ -+ err = 1; -+ ii_write_lock_new_child(inode); -+ h_dinode = au_h_dptr(dentry, au_dbstart(dentry))->d_inode; -+ bend = au_ibend(inode); -+ for (bindex = au_ibstart(inode); bindex <= bend; bindex++) { -+ h_inode = au_h_iptr(inode, bindex); -+ if (h_inode && h_inode == h_dinode) { -+ err = 0; -+ if (au_iigen_test(inode, au_digen(dentry))) -+ err = au_refresh_hinode(inode, dentry); -+ break; -+ } -+ } -+ -+ if (unlikely(err)) -+ ii_write_unlock(inode); -+out: -+ return err; -+} -+ -+int au_ino(struct super_block *sb, aufs_bindex_t bindex, ino_t h_ino, -+ unsigned int d_type, ino_t *ino) -+{ -+ int err; -+ struct mutex *mtx; -+ -+ /* prevent hardlinked inode number from race condition */ -+ mtx = NULL; -+ if (d_type != DT_DIR) { -+ mtx = &au_sbr(sb, bindex)->br_xino.xi_nondir_mtx; -+ mutex_lock(mtx); -+ } -+ err = au_xino_read(sb, bindex, h_ino, ino); -+ if (unlikely(err)) -+ goto out; -+ -+ if (!*ino) { -+ err = -EIO; -+ *ino = au_xino_new_ino(sb); -+ if (unlikely(!*ino)) -+ goto out; -+ err = au_xino_write(sb, bindex, h_ino, *ino); -+ if (unlikely(err)) -+ goto out; -+ } -+ -+out: -+ if (mtx) -+ mutex_unlock(mtx); -+ return err; -+} -+ -+/* successful returns with iinfo write_locked */ -+/* todo: return with unlocked? */ -+struct inode *au_new_inode(struct dentry *dentry, int must_new) -+{ -+ struct inode *inode, *h_inode; -+ struct dentry *h_dentry; -+ struct super_block *sb; -+ struct mutex *mtx; -+ ino_t h_ino, ino; -+ int err; -+ aufs_bindex_t bstart; -+ -+ sb = dentry->d_sb; -+ bstart = au_dbstart(dentry); -+ h_dentry = au_h_dptr(dentry, bstart); -+ h_inode = h_dentry->d_inode; -+ h_ino = h_inode->i_ino; -+ -+ /* -+ * stop 'race'-ing between hardlinks under different -+ * parents. -+ */ -+ mtx = NULL; -+ if (!S_ISDIR(h_inode->i_mode)) -+ mtx = &au_sbr(sb, bstart)->br_xino.xi_nondir_mtx; -+ -+new_ino: -+ if (mtx) -+ mutex_lock(mtx); -+ err = au_xino_read(sb, bstart, h_ino, &ino); -+ inode = ERR_PTR(err); -+ if (unlikely(err)) -+ goto out; -+ -+ if (!ino) { -+ ino = au_xino_new_ino(sb); -+ if (unlikely(!ino)) { -+ inode = ERR_PTR(-EIO); -+ goto out; -+ } -+ } -+ -+ AuDbg("i%lu\n", (unsigned long)ino); -+ inode = au_iget_locked(sb, ino); -+ err = PTR_ERR(inode); -+ if (IS_ERR(inode)) -+ goto out; -+ -+ AuDbg("%lx, new %d\n", inode->i_state, !!(inode->i_state & I_NEW)); -+ if (inode->i_state & I_NEW) { -+ ii_write_lock_new_child(inode); -+ err = set_inode(inode, dentry); -+ if (!err) { -+ unlock_new_inode(inode); -+ goto out; /* success */ -+ } -+ -+ /* -+ * iget_failed() calls iput(), but we need to call -+ * ii_write_unlock() after iget_failed(). so dirty hack for -+ * i_count. -+ */ -+ atomic_inc(&inode->i_count); -+ iget_failed(inode); -+ ii_write_unlock(inode); -+ au_xino_write(sb, bstart, h_ino, /*ino*/0); -+ /* ignore this error */ -+ goto out_iput; -+ } else if (!must_new && !IS_DEADDIR(inode) && inode->i_nlink) { -+ /* -+ * horrible race condition between lookup, readdir and copyup -+ * (or something). -+ */ -+ if (mtx) -+ mutex_unlock(mtx); -+ err = reval_inode(inode, dentry); -+ if (unlikely(err < 0)) { -+ mtx = NULL; -+ goto out_iput; -+ } -+ -+ if (!err) { -+ mtx = NULL; -+ goto out; /* success */ -+ } else if (mtx) -+ mutex_lock(mtx); -+ } -+ -+ if (unlikely(au_test_fs_unique_ino(h_dentry->d_inode))) -+ AuWarn1("Warning: Un-notified UDBA or repeatedly renamed dir," -+ " b%d, %s, %.*s, hi%lu, i%lu.\n", -+ bstart, au_sbtype(h_dentry->d_sb), AuDLNPair(dentry), -+ (unsigned long)h_ino, (unsigned long)ino); -+ ino = 0; -+ err = au_xino_write(sb, bstart, h_ino, /*ino*/0); -+ if (!err) { -+ iput(inode); -+ if (mtx) -+ mutex_unlock(mtx); -+ goto new_ino; -+ } -+ -+out_iput: -+ iput(inode); -+ inode = ERR_PTR(err); -+out: -+ if (mtx) -+ mutex_unlock(mtx); -+ return inode; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+int au_test_ro(struct super_block *sb, aufs_bindex_t bindex, -+ struct inode *inode) -+{ -+ int err; -+ -+ err = au_br_rdonly(au_sbr(sb, bindex)); -+ -+ /* pseudo-link after flushed may happen out of bounds */ -+ if (!err -+ && inode -+ && au_ibstart(inode) <= bindex -+ && bindex <= au_ibend(inode)) { -+ /* -+ * permission check is unnecessary since vfsub routine -+ * will be called later -+ */ -+ struct inode *hi = au_h_iptr(inode, bindex); -+ if (hi) -+ err = IS_IMMUTABLE(hi) ? -EROFS : 0; -+ } -+ -+ return err; -+} -+ -+int au_test_h_perm(struct inode *h_inode, int mask) -+{ -+ if (!current_fsuid()) -+ return 0; -+ return inode_permission(h_inode, mask); -+} -+ -+int au_test_h_perm_sio(struct inode *h_inode, int mask) -+{ -+ if (au_test_nfs(h_inode->i_sb) -+ && (mask & MAY_WRITE) -+ && S_ISDIR(h_inode->i_mode)) -+ mask |= MAY_READ; /* force permission check */ -+ return au_test_h_perm(h_inode, mask); -+} -diff -Nur linux-2.6.37.orig/fs/aufs/inode.h linux-2.6.37/fs/aufs/inode.h ---- linux-2.6.37.orig/fs/aufs/inode.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/inode.h 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,546 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * inode operations -+ */ -+ -+#ifndef __AUFS_INODE_H__ -+#define __AUFS_INODE_H__ -+ -+#ifdef __KERNEL__ -+ -+#include -+#include -+#include -+#include "rwsem.h" -+ -+struct vfsmount; -+ -+struct au_hnotify { -+#ifdef CONFIG_AUFS_HNOTIFY -+#ifdef CONFIG_AUFS_HFSNOTIFY -+ /* never use fsnotify_add_vfsmount_mark() */ -+ struct fsnotify_mark hn_mark; -+ int hn_mark_dead; -+#endif -+ struct inode *hn_aufs_inode; /* no get/put */ -+#endif -+} ____cacheline_aligned_in_smp; -+ -+struct au_hinode { -+ struct inode *hi_inode; -+ aufs_bindex_t hi_id; -+#ifdef CONFIG_AUFS_HNOTIFY -+ struct au_hnotify *hi_notify; -+#endif -+ -+ /* reference to the copied-up whiteout with get/put */ -+ struct dentry *hi_whdentry; -+}; -+ -+struct au_vdir; -+struct au_iinfo { -+ atomic_t ii_generation; -+ struct super_block *ii_hsb1; /* no get/put */ -+ -+ struct au_rwsem ii_rwsem; -+ aufs_bindex_t ii_bstart, ii_bend; -+ __u32 ii_higen; -+ struct au_hinode *ii_hinode; -+ struct au_vdir *ii_vdir; -+}; -+ -+struct au_icntnr { -+ struct au_iinfo iinfo; -+ struct inode vfs_inode; -+} ____cacheline_aligned_in_smp; -+ -+/* au_pin flags */ -+#define AuPin_DI_LOCKED 1 -+#define AuPin_MNT_WRITE (1 << 1) -+#define au_ftest_pin(flags, name) ((flags) & AuPin_##name) -+#define au_fset_pin(flags, name) \ -+ do { (flags) |= AuPin_##name; } while (0) -+#define au_fclr_pin(flags, name) \ -+ do { (flags) &= ~AuPin_##name; } while (0) -+ -+struct au_pin { -+ /* input */ -+ struct dentry *dentry; -+ unsigned int udba; -+ unsigned char lsc_di, lsc_hi, flags; -+ aufs_bindex_t bindex; -+ -+ /* output */ -+ struct dentry *parent; -+ struct au_hinode *hdir; -+ struct vfsmount *h_mnt; -+}; -+ -+/* ---------------------------------------------------------------------- */ -+ -+static inline struct au_iinfo *au_ii(struct inode *inode) -+{ -+ struct au_iinfo *iinfo; -+ -+ iinfo = &(container_of(inode, struct au_icntnr, vfs_inode)->iinfo); -+ if (iinfo->ii_hinode) -+ return iinfo; -+ return NULL; /* debugging bad_inode case */ -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* inode.c */ -+struct inode *au_igrab(struct inode *inode); -+int au_refresh_hinode_self(struct inode *inode); -+int au_refresh_hinode(struct inode *inode, struct dentry *dentry); -+int au_ino(struct super_block *sb, aufs_bindex_t bindex, ino_t h_ino, -+ unsigned int d_type, ino_t *ino); -+struct inode *au_new_inode(struct dentry *dentry, int must_new); -+int au_test_ro(struct super_block *sb, aufs_bindex_t bindex, -+ struct inode *inode); -+int au_test_h_perm(struct inode *h_inode, int mask); -+int au_test_h_perm_sio(struct inode *h_inode, int mask); -+ -+static inline int au_wh_ino(struct super_block *sb, aufs_bindex_t bindex, -+ ino_t h_ino, unsigned int d_type, ino_t *ino) -+{ -+#ifdef CONFIG_AUFS_SHWH -+ return au_ino(sb, bindex, h_ino, d_type, ino); -+#else -+ return 0; -+#endif -+} -+ -+/* i_op.c */ -+extern struct inode_operations aufs_iop, aufs_symlink_iop, aufs_dir_iop; -+ -+/* au_wr_dir flags */ -+#define AuWrDir_ADD_ENTRY 1 -+#define AuWrDir_ISDIR (1 << 1) -+#define au_ftest_wrdir(flags, name) ((flags) & AuWrDir_##name) -+#define au_fset_wrdir(flags, name) \ -+ do { (flags) |= AuWrDir_##name; } while (0) -+#define au_fclr_wrdir(flags, name) \ -+ do { (flags) &= ~AuWrDir_##name; } while (0) -+ -+struct au_wr_dir_args { -+ aufs_bindex_t force_btgt; -+ unsigned char flags; -+}; -+int au_wr_dir(struct dentry *dentry, struct dentry *src_dentry, -+ struct au_wr_dir_args *args); -+ -+struct dentry *au_pinned_h_parent(struct au_pin *pin); -+void au_pin_init(struct au_pin *pin, struct dentry *dentry, -+ aufs_bindex_t bindex, int lsc_di, int lsc_hi, -+ unsigned int udba, unsigned char flags); -+int au_pin(struct au_pin *pin, struct dentry *dentry, aufs_bindex_t bindex, -+ unsigned int udba, unsigned char flags) __must_check; -+int au_do_pin(struct au_pin *pin) __must_check; -+void au_unpin(struct au_pin *pin); -+ -+/* i_op_add.c */ -+int au_may_add(struct dentry *dentry, aufs_bindex_t bindex, -+ struct dentry *h_parent, int isdir); -+int aufs_mknod(struct inode *dir, struct dentry *dentry, int mode, dev_t dev); -+int aufs_symlink(struct inode *dir, struct dentry *dentry, const char *symname); -+int aufs_create(struct inode *dir, struct dentry *dentry, int mode, -+ struct nameidata *nd); -+int aufs_link(struct dentry *src_dentry, struct inode *dir, -+ struct dentry *dentry); -+int aufs_mkdir(struct inode *dir, struct dentry *dentry, int mode); -+ -+/* i_op_del.c */ -+int au_wr_dir_need_wh(struct dentry *dentry, int isdir, aufs_bindex_t *bcpup); -+int au_may_del(struct dentry *dentry, aufs_bindex_t bindex, -+ struct dentry *h_parent, int isdir); -+int aufs_unlink(struct inode *dir, struct dentry *dentry); -+int aufs_rmdir(struct inode *dir, struct dentry *dentry); -+ -+/* i_op_ren.c */ -+int au_wbr(struct dentry *dentry, aufs_bindex_t btgt); -+int aufs_rename(struct inode *src_dir, struct dentry *src_dentry, -+ struct inode *dir, struct dentry *dentry); -+ -+/* iinfo.c */ -+struct inode *au_h_iptr(struct inode *inode, aufs_bindex_t bindex); -+void au_hiput(struct au_hinode *hinode); -+void au_set_hi_wh(struct inode *inode, aufs_bindex_t bindex, -+ struct dentry *h_wh); -+unsigned int au_hi_flags(struct inode *inode, int isdir); -+ -+/* hinode flags */ -+#define AuHi_XINO 1 -+#define AuHi_HNOTIFY (1 << 1) -+#define au_ftest_hi(flags, name) ((flags) & AuHi_##name) -+#define au_fset_hi(flags, name) \ -+ do { (flags) |= AuHi_##name; } while (0) -+#define au_fclr_hi(flags, name) \ -+ do { (flags) &= ~AuHi_##name; } while (0) -+ -+#ifndef CONFIG_AUFS_HNOTIFY -+#undef AuHi_HNOTIFY -+#define AuHi_HNOTIFY 0 -+#endif -+ -+void au_set_h_iptr(struct inode *inode, aufs_bindex_t bindex, -+ struct inode *h_inode, unsigned int flags); -+ -+void au_update_iigen(struct inode *inode); -+void au_update_ibrange(struct inode *inode, int do_put_zero); -+ -+void au_icntnr_init_once(void *_c); -+int au_iinfo_init(struct inode *inode); -+void au_iinfo_fin(struct inode *inode); -+int au_ii_realloc(struct au_iinfo *iinfo, int nbr); -+ -+#ifdef CONFIG_PROC_FS -+/* plink.c */ -+int au_plink_maint(struct super_block *sb, int flags); -+void au_plink_maint_leave(struct au_sbinfo *sbinfo); -+int au_plink_maint_enter(struct super_block *sb); -+#ifdef CONFIG_AUFS_DEBUG -+void au_plink_list(struct super_block *sb); -+#else -+AuStubVoid(au_plink_list, struct super_block *sb) -+#endif -+int au_plink_test(struct inode *inode); -+struct dentry *au_plink_lkup(struct inode *inode, aufs_bindex_t bindex); -+void au_plink_append(struct inode *inode, aufs_bindex_t bindex, -+ struct dentry *h_dentry); -+void au_plink_put(struct super_block *sb, int verbose); -+void au_plink_clean(struct super_block *sb, int verbose); -+void au_plink_half_refresh(struct super_block *sb, aufs_bindex_t br_id); -+#else -+AuStubInt0(au_plink_maint, struct super_block *sb, int flags); -+AuStubVoid(au_plink_maint_leave, struct au_sbinfo *sbinfo); -+AuStubInt0(au_plink_maint_enter, struct super_block *sb); -+AuStubVoid(au_plink_list, struct super_block *sb); -+AuStubInt0(au_plink_test, struct inode *inode); -+AuStub(struct dentry *, au_plink_lkup, return NULL, -+ struct inode *inode, aufs_bindex_t bindex); -+AuStubVoid(au_plink_append, struct inode *inode, aufs_bindex_t bindex, -+ struct dentry *h_dentry); -+AuStubVoid(au_plink_put, struct super_block *sb, int verbose); -+AuStubVoid(au_plink_clean, struct super_block *sb, int verbose); -+AuStubVoid(au_plink_half_refresh, struct super_block *sb, aufs_bindex_t br_id); -+#endif /* CONFIG_PROC_FS */ -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* lock subclass for iinfo */ -+enum { -+ AuLsc_II_CHILD, /* child first */ -+ AuLsc_II_CHILD2, /* rename(2), link(2), and cpup at hnotify */ -+ AuLsc_II_CHILD3, /* copyup dirs */ -+ AuLsc_II_PARENT, /* see AuLsc_I_PARENT in vfsub.h */ -+ AuLsc_II_PARENT2, -+ AuLsc_II_PARENT3, /* copyup dirs */ -+ AuLsc_II_NEW_CHILD -+}; -+ -+/* -+ * ii_read_lock_child, ii_write_lock_child, -+ * ii_read_lock_child2, ii_write_lock_child2, -+ * ii_read_lock_child3, ii_write_lock_child3, -+ * ii_read_lock_parent, ii_write_lock_parent, -+ * ii_read_lock_parent2, ii_write_lock_parent2, -+ * ii_read_lock_parent3, ii_write_lock_parent3, -+ * ii_read_lock_new_child, ii_write_lock_new_child, -+ */ -+#define AuReadLockFunc(name, lsc) \ -+static inline void ii_read_lock_##name(struct inode *i) \ -+{ \ -+ au_rw_read_lock_nested(&au_ii(i)->ii_rwsem, AuLsc_II_##lsc); \ -+} -+ -+#define AuWriteLockFunc(name, lsc) \ -+static inline void ii_write_lock_##name(struct inode *i) \ -+{ \ -+ au_rw_write_lock_nested(&au_ii(i)->ii_rwsem, AuLsc_II_##lsc); \ -+} -+ -+#define AuRWLockFuncs(name, lsc) \ -+ AuReadLockFunc(name, lsc) \ -+ AuWriteLockFunc(name, lsc) -+ -+AuRWLockFuncs(child, CHILD); -+AuRWLockFuncs(child2, CHILD2); -+AuRWLockFuncs(child3, CHILD3); -+AuRWLockFuncs(parent, PARENT); -+AuRWLockFuncs(parent2, PARENT2); -+AuRWLockFuncs(parent3, PARENT3); -+AuRWLockFuncs(new_child, NEW_CHILD); -+ -+#undef AuReadLockFunc -+#undef AuWriteLockFunc -+#undef AuRWLockFuncs -+ -+/* -+ * ii_read_unlock, ii_write_unlock, ii_downgrade_lock -+ */ -+AuSimpleUnlockRwsemFuncs(ii, struct inode *i, &au_ii(i)->ii_rwsem); -+ -+#define IiMustNoWaiters(i) AuRwMustNoWaiters(&au_ii(i)->ii_rwsem) -+#define IiMustAnyLock(i) AuRwMustAnyLock(&au_ii(i)->ii_rwsem) -+#define IiMustWriteLock(i) AuRwMustWriteLock(&au_ii(i)->ii_rwsem) -+ -+/* ---------------------------------------------------------------------- */ -+ -+static inline void au_icntnr_init(struct au_icntnr *c) -+{ -+#ifdef CONFIG_AUFS_DEBUG -+ c->vfs_inode.i_mode = 0; -+#endif -+} -+ -+static inline unsigned int au_iigen(struct inode *inode) -+{ -+ return atomic_read(&au_ii(inode)->ii_generation); -+} -+ -+/* tiny test for inode number */ -+/* tmpfs generation is too rough */ -+static inline int au_test_higen(struct inode *inode, struct inode *h_inode) -+{ -+ struct au_iinfo *iinfo; -+ -+ iinfo = au_ii(inode); -+ AuRwMustAnyLock(&iinfo->ii_rwsem); -+ return !(iinfo->ii_hsb1 == h_inode->i_sb -+ && iinfo->ii_higen == h_inode->i_generation); -+} -+ -+static inline void au_iigen_dec(struct inode *inode) -+{ -+ atomic_dec(&au_ii(inode)->ii_generation); -+} -+ -+static inline int au_iigen_test(struct inode *inode, unsigned int sigen) -+{ -+ int err; -+ -+ err = 0; -+ if (unlikely(inode && au_iigen(inode) != sigen)) -+ err = -EIO; -+ -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static inline aufs_bindex_t au_ii_br_id(struct inode *inode, -+ aufs_bindex_t bindex) -+{ -+ IiMustAnyLock(inode); -+ return au_ii(inode)->ii_hinode[0 + bindex].hi_id; -+} -+ -+static inline aufs_bindex_t au_ibstart(struct inode *inode) -+{ -+ IiMustAnyLock(inode); -+ return au_ii(inode)->ii_bstart; -+} -+ -+static inline aufs_bindex_t au_ibend(struct inode *inode) -+{ -+ IiMustAnyLock(inode); -+ return au_ii(inode)->ii_bend; -+} -+ -+static inline struct au_vdir *au_ivdir(struct inode *inode) -+{ -+ IiMustAnyLock(inode); -+ return au_ii(inode)->ii_vdir; -+} -+ -+static inline struct dentry *au_hi_wh(struct inode *inode, aufs_bindex_t bindex) -+{ -+ IiMustAnyLock(inode); -+ return au_ii(inode)->ii_hinode[0 + bindex].hi_whdentry; -+} -+ -+static inline void au_set_ibstart(struct inode *inode, aufs_bindex_t bindex) -+{ -+ IiMustWriteLock(inode); -+ au_ii(inode)->ii_bstart = bindex; -+} -+ -+static inline void au_set_ibend(struct inode *inode, aufs_bindex_t bindex) -+{ -+ IiMustWriteLock(inode); -+ au_ii(inode)->ii_bend = bindex; -+} -+ -+static inline void au_set_ivdir(struct inode *inode, struct au_vdir *vdir) -+{ -+ IiMustWriteLock(inode); -+ au_ii(inode)->ii_vdir = vdir; -+} -+ -+static inline struct au_hinode *au_hi(struct inode *inode, aufs_bindex_t bindex) -+{ -+ IiMustAnyLock(inode); -+ return au_ii(inode)->ii_hinode + bindex; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static inline struct dentry *au_pinned_parent(struct au_pin *pin) -+{ -+ if (pin) -+ return pin->parent; -+ return NULL; -+} -+ -+static inline struct inode *au_pinned_h_dir(struct au_pin *pin) -+{ -+ if (pin && pin->hdir) -+ return pin->hdir->hi_inode; -+ return NULL; -+} -+ -+static inline struct au_hinode *au_pinned_hdir(struct au_pin *pin) -+{ -+ if (pin) -+ return pin->hdir; -+ return NULL; -+} -+ -+static inline void au_pin_set_dentry(struct au_pin *pin, struct dentry *dentry) -+{ -+ if (pin) -+ pin->dentry = dentry; -+} -+ -+static inline void au_pin_set_parent_lflag(struct au_pin *pin, -+ unsigned char lflag) -+{ -+ if (pin) { -+ if (lflag) -+ au_fset_pin(pin->flags, DI_LOCKED); -+ else -+ au_fclr_pin(pin->flags, DI_LOCKED); -+ } -+} -+ -+static inline void au_pin_set_parent(struct au_pin *pin, struct dentry *parent) -+{ -+ if (pin) { -+ dput(pin->parent); -+ pin->parent = dget(parent); -+ } -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+struct au_branch; -+#ifdef CONFIG_AUFS_HNOTIFY -+struct au_hnotify_op { -+ void (*ctl)(struct au_hinode *hinode, int do_set); -+ int (*alloc)(struct au_hinode *hinode); -+ void (*free)(struct au_hinode *hinode); -+ -+ void (*fin)(void); -+ int (*init)(void); -+ -+ int (*reset_br)(unsigned int udba, struct au_branch *br, int perm); -+ void (*fin_br)(struct au_branch *br); -+ int (*init_br)(struct au_branch *br, int perm); -+}; -+ -+/* hnotify.c */ -+int au_hn_alloc(struct au_hinode *hinode, struct inode *inode); -+void au_hn_free(struct au_hinode *hinode); -+void au_hn_ctl(struct au_hinode *hinode, int do_set); -+void au_hn_reset(struct inode *inode, unsigned int flags); -+int au_hnotify(struct inode *h_dir, struct au_hnotify *hnotify, u32 mask, -+ struct qstr *h_child_qstr, struct inode *h_child_inode); -+int au_hnotify_reset_br(unsigned int udba, struct au_branch *br, int perm); -+int au_hnotify_init_br(struct au_branch *br, int perm); -+void au_hnotify_fin_br(struct au_branch *br); -+int __init au_hnotify_init(void); -+void au_hnotify_fin(void); -+ -+/* hfsnotify.c */ -+extern const struct au_hnotify_op au_hnotify_op; -+ -+static inline -+void au_hn_init(struct au_hinode *hinode) -+{ -+ hinode->hi_notify = NULL; -+} -+ -+#else -+static inline -+int au_hn_alloc(struct au_hinode *hinode __maybe_unused, -+ struct inode *inode __maybe_unused) -+{ -+ return -EOPNOTSUPP; -+} -+ -+AuStubVoid(au_hn_free, struct au_hinode *hinode __maybe_unused) -+AuStubVoid(au_hn_ctl, struct au_hinode *hinode __maybe_unused, -+ int do_set __maybe_unused) -+AuStubVoid(au_hn_reset, struct inode *inode __maybe_unused, -+ unsigned int flags __maybe_unused) -+AuStubInt0(au_hnotify_reset_br, unsigned int udba __maybe_unused, -+ struct au_branch *br __maybe_unused, -+ int perm __maybe_unused) -+AuStubInt0(au_hnotify_init_br, struct au_branch *br __maybe_unused, -+ int perm __maybe_unused) -+AuStubVoid(au_hnotify_fin_br, struct au_branch *br __maybe_unused) -+AuStubInt0(__init au_hnotify_init, void) -+AuStubVoid(au_hnotify_fin, void) -+AuStubVoid(au_hn_init, struct au_hinode *hinode __maybe_unused) -+#endif /* CONFIG_AUFS_HNOTIFY */ -+ -+static inline void au_hn_suspend(struct au_hinode *hdir) -+{ -+ au_hn_ctl(hdir, /*do_set*/0); -+} -+ -+static inline void au_hn_resume(struct au_hinode *hdir) -+{ -+ au_hn_ctl(hdir, /*do_set*/1); -+} -+ -+static inline void au_hn_imtx_lock(struct au_hinode *hdir) -+{ -+ mutex_lock(&hdir->hi_inode->i_mutex); -+ au_hn_suspend(hdir); -+} -+ -+static inline void au_hn_imtx_lock_nested(struct au_hinode *hdir, -+ unsigned int sc __maybe_unused) -+{ -+ mutex_lock_nested(&hdir->hi_inode->i_mutex, sc); -+ au_hn_suspend(hdir); -+} -+ -+static inline void au_hn_imtx_unlock(struct au_hinode *hdir) -+{ -+ au_hn_resume(hdir); -+ mutex_unlock(&hdir->hi_inode->i_mutex); -+} -+ -+#endif /* __KERNEL__ */ -+#endif /* __AUFS_INODE_H__ */ -diff -Nur linux-2.6.37.orig/fs/aufs/ioctl.c linux-2.6.37/fs/aufs/ioctl.c ---- linux-2.6.37.orig/fs/aufs/ioctl.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/ioctl.c 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,150 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * ioctl -+ * plink-management and readdir in userspace. -+ * assist the pathconf(3) wrapper library. -+ */ -+ -+#include -+#include "aufs.h" -+ -+static int au_wbr_fd(struct path *path) -+{ -+ int err, fd; -+ aufs_bindex_t wbi, bindex, bend; -+ struct file *h_file; -+ struct super_block *sb; -+ struct dentry *root; -+ struct au_branch *wbr; -+ -+ err = get_unused_fd(); -+ if (unlikely(err < 0)) -+ goto out; -+ fd = err; -+ -+ wbi = 0; -+ sb = path->dentry->d_sb; -+ root = sb->s_root; -+ aufs_read_lock(root, AuLock_IR); -+ wbr = au_sbr(sb, wbi); -+ if (!(path->mnt->mnt_flags & MNT_READONLY) -+ && !au_br_writable(wbr->br_perm)) { -+ bend = au_sbend(sb); -+ for (bindex = 1; bindex <= bend; bindex++) { -+ wbr = au_sbr(sb, bindex); -+ if (au_br_writable(wbr->br_perm)) { -+ wbi = bindex; -+ break; -+ } -+ } -+ wbr = au_sbr(sb, wbi); -+ } -+ AuDbg("wbi %d\n", wbi); -+ h_file = au_h_open(root, wbi, O_RDONLY | O_DIRECTORY | O_LARGEFILE, -+ NULL); -+ aufs_read_unlock(root, AuLock_IR); -+ err = PTR_ERR(h_file); -+ if (IS_ERR(h_file)) -+ goto out_fd; -+ -+ atomic_dec(&wbr->br_count); /* cf. au_h_open() */ -+ fd_install(fd, h_file); -+ err = fd; -+ goto out; /* success */ -+ -+out_fd: -+ put_unused_fd(fd); -+out: -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+long aufs_ioctl_dir(struct file *file, unsigned int cmd, unsigned long arg) -+{ -+ long err; -+ -+ switch (cmd) { -+ case AUFS_CTL_RDU: -+ case AUFS_CTL_RDU_INO: -+ err = au_rdu_ioctl(file, cmd, arg); -+ break; -+ -+ case AUFS_CTL_WBR_FD: -+ err = au_wbr_fd(&file->f_path); -+ break; -+ -+ default: -+ /* do not call the lower */ -+ AuDbg("0x%x\n", cmd); -+ err = -ENOTTY; -+ } -+ -+ AuTraceErr(err); -+ return err; -+} -+ -+long aufs_ioctl_nondir(struct file *file, unsigned int cmd, unsigned long arg) -+{ -+ long err; -+ -+ switch (cmd) { -+ case AUFS_CTL_WBR_FD: -+ err = au_wbr_fd(&file->f_path); -+ break; -+ -+ default: -+ /* do not call the lower */ -+ AuDbg("0x%x\n", cmd); -+ err = -ENOTTY; -+ } -+ -+ AuTraceErr(err); -+ return err; -+} -+ -+#ifdef CONFIG_COMPAT -+long aufs_compat_ioctl_dir(struct file *file, unsigned int cmd, -+ unsigned long arg) -+{ -+ long err; -+ -+ switch (cmd) { -+ case AUFS_CTL_RDU: -+ case AUFS_CTL_RDU_INO: -+ err = au_rdu_compat_ioctl(file, cmd, arg); -+ break; -+ -+ default: -+ err = aufs_ioctl_dir(file, cmd, arg); -+ } -+ -+ AuTraceErr(err); -+ return err; -+} -+ -+#if 0 /* unused yet */ -+long aufs_compat_ioctl_nondir(struct file *file, unsigned int cmd, -+ unsigned long arg) -+{ -+ return aufs_ioctl_nondir(file, cmd, (unsigned long)compat_ptr(arg)); -+} -+#endif -+#endif -diff -Nur linux-2.6.37.orig/fs/aufs/loop.c linux-2.6.37/fs/aufs/loop.c ---- linux-2.6.37.orig/fs/aufs/loop.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/loop.c 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,63 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * support for loopback block device as a branch -+ */ -+ -+#include -+#include "aufs.h" -+ -+/* -+ * test if two lower dentries have overlapping branches. -+ */ -+int au_test_loopback_overlap(struct super_block *sb, struct dentry *h_adding) -+{ -+ struct super_block *h_sb; -+ struct loop_device *l; -+ -+ h_sb = h_adding->d_sb; -+ if (MAJOR(h_sb->s_dev) != LOOP_MAJOR) -+ return 0; -+ -+ l = h_sb->s_bdev->bd_disk->private_data; -+ h_adding = l->lo_backing_file->f_dentry; -+ /* -+ * h_adding can be local NFS. -+ * in this case aufs cannot detect the loop. -+ */ -+ if (unlikely(h_adding->d_sb == sb)) -+ return 1; -+ return !!au_test_subdir(h_adding, sb->s_root); -+} -+ -+/* true if a kernel thread named 'loop[0-9].*' accesses a file */ -+int au_test_loopback_kthread(void) -+{ -+ int ret; -+ struct task_struct *tsk = current; -+ -+ ret = 0; -+ if (tsk->flags & PF_KTHREAD) { -+ const char c = tsk->comm[4]; -+ ret = ('0' <= c && c <= '9' -+ && !strncmp(tsk->comm, "loop", 4)); -+ } -+ -+ return ret; -+} -diff -Nur linux-2.6.37.orig/fs/aufs/loop.h linux-2.6.37/fs/aufs/loop.h ---- linux-2.6.37.orig/fs/aufs/loop.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/loop.h 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,42 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * support for loopback mount as a branch -+ */ -+ -+#ifndef __AUFS_LOOP_H__ -+#define __AUFS_LOOP_H__ -+ -+#ifdef __KERNEL__ -+ -+struct dentry; -+struct super_block; -+ -+#ifdef CONFIG_AUFS_BDEV_LOOP -+/* loop.c */ -+int au_test_loopback_overlap(struct super_block *sb, struct dentry *h_adding); -+int au_test_loopback_kthread(void); -+#else -+AuStubInt0(au_test_loopback_overlap, struct super_block *sb, -+ struct dentry *h_adding) -+AuStubInt0(au_test_loopback_kthread, void) -+#endif /* BLK_DEV_LOOP */ -+ -+#endif /* __KERNEL__ */ -+#endif /* __AUFS_LOOP_H__ */ -diff -Nur linux-2.6.37.orig/fs/aufs/magic.mk linux-2.6.37/fs/aufs/magic.mk ---- linux-2.6.37.orig/fs/aufs/magic.mk 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/magic.mk 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,54 @@ -+ -+# defined in ${srctree}/fs/fuse/inode.c -+# tristate -+ifdef CONFIG_FUSE_FS -+ccflags-y += -DFUSE_SUPER_MAGIC=0x65735546 -+endif -+ -+# defined in ${srctree}/fs/ocfs2/ocfs2_fs.h -+# tristate -+ifdef CONFIG_OCFS2_FS -+ccflags-y += -DOCFS2_SUPER_MAGIC=0x7461636f -+endif -+ -+# defined in ${srctree}/fs/ocfs2/dlm/userdlm.h -+# tristate -+ifdef CONFIG_OCFS2_FS_O2CB -+ccflags-y += -DDLMFS_MAGIC=0x76a9f425 -+endif -+ -+# defined in ${srctree}/fs/cifs/cifsfs.c -+# tristate -+ifdef CONFIG_CIFS_FS -+ccflags-y += -DCIFS_MAGIC_NUMBER=0xFF534D42 -+endif -+ -+# defined in ${srctree}/fs/xfs/xfs_sb.h -+# tristate -+ifdef CONFIG_XFS_FS -+ccflags-y += -DXFS_SB_MAGIC=0x58465342 -+endif -+ -+# defined in ${srctree}/fs/configfs/mount.c -+# tristate -+ifdef CONFIG_CONFIGFS_FS -+ccflags-y += -DCONFIGFS_MAGIC=0x62656570 -+endif -+ -+# defined in ${srctree}/fs/9p/v9fs.h -+# tristate -+ifdef CONFIG_9P_FS -+ccflags-y += -DV9FS_MAGIC=0x01021997 -+endif -+ -+# defined in ${srctree}/fs/ubifs/ubifs.h -+# tristate -+ifdef CONFIG_UBIFS_FS -+ccflags-y += -DUBIFS_SUPER_MAGIC=0x24051905 -+endif -+ -+# defined in ${srctree}/fs/hfsplus/hfsplus_raw.h -+# tristate -+ifdef CONFIG_HFSPLUS_FS -+ccflags-y += -DHFSPLUS_SUPER_MAGIC=0x482b -+endif -diff -Nur linux-2.6.37.orig/fs/aufs/module.c linux-2.6.37/fs/aufs/module.c ---- linux-2.6.37.orig/fs/aufs/module.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/module.c 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,182 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * module global variables and operations -+ */ -+ -+#include -+#include -+#include "aufs.h" -+ -+void *au_kzrealloc(void *p, unsigned int nused, unsigned int new_sz, gfp_t gfp) -+{ -+ if (new_sz <= nused) -+ return p; -+ -+ p = krealloc(p, new_sz, gfp); -+ if (p) -+ memset(p + nused, 0, new_sz - nused); -+ return p; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * aufs caches -+ */ -+struct kmem_cache *au_cachep[AuCache_Last]; -+static int __init au_cache_init(void) -+{ -+ au_cachep[AuCache_DINFO] = AuCacheCtor(au_dinfo, au_di_init_once); -+ if (au_cachep[AuCache_DINFO]) -+ au_cachep[AuCache_ICNTNR] = AuCacheCtor(au_icntnr, -+ au_icntnr_init_once); -+ if (au_cachep[AuCache_ICNTNR]) -+ au_cachep[AuCache_FINFO] = AuCacheCtor(au_finfo, -+ au_fi_init_once); -+ if (au_cachep[AuCache_FINFO]) -+ au_cachep[AuCache_VDIR] = AuCache(au_vdir); -+ if (au_cachep[AuCache_VDIR]) -+ au_cachep[AuCache_DEHSTR] = AuCache(au_vdir_dehstr); -+ if (au_cachep[AuCache_DEHSTR]) -+ return 0; -+ -+ return -ENOMEM; -+} -+ -+static void au_cache_fin(void) -+{ -+ int i; -+ -+ /* including AuCache_HNOTIFY */ -+ for (i = 0; i < AuCache_Last; i++) -+ if (au_cachep[i]) { -+ kmem_cache_destroy(au_cachep[i]); -+ au_cachep[i] = NULL; -+ } -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+int au_dir_roflags; -+ -+#ifdef CONFIG_AUFS_SBILIST -+struct au_splhead au_sbilist; -+#endif -+ -+/* -+ * functions for module interface. -+ */ -+MODULE_LICENSE("GPL"); -+/* MODULE_LICENSE("GPL v2"); */ -+MODULE_AUTHOR("Junjiro R. Okajima "); -+MODULE_DESCRIPTION(AUFS_NAME -+ " -- Advanced multi layered unification filesystem"); -+MODULE_VERSION(AUFS_VERSION); -+ -+/* this module parameter has no meaning when SYSFS is disabled */ -+int sysaufs_brs = 1; -+MODULE_PARM_DESC(brs, "use /fs/aufs/si_*/brN"); -+module_param_named(brs, sysaufs_brs, int, S_IRUGO); -+ -+/* ---------------------------------------------------------------------- */ -+ -+static char au_esc_chars[0x20 + 3]; /* 0x01-0x20, backslash, del, and NULL */ -+ -+int au_seq_path(struct seq_file *seq, struct path *path) -+{ -+ return seq_path(seq, path, au_esc_chars); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int __init aufs_init(void) -+{ -+ int err, i; -+ char *p; -+ -+ p = au_esc_chars; -+ for (i = 1; i <= ' '; i++) -+ *p++ = i; -+ *p++ = '\\'; -+ *p++ = '\x7f'; -+ *p = 0; -+ -+ au_dir_roflags = au_file_roflags(O_DIRECTORY | O_LARGEFILE); -+ -+ au_sbilist_init(); -+ sysaufs_brs_init(); -+ au_debug_init(); -+ au_dy_init(); -+ err = sysaufs_init(); -+ if (unlikely(err)) -+ goto out; -+ err = au_procfs_init(); -+ if (unlikely(err)) -+ goto out_sysaufs; -+ err = au_wkq_init(); -+ if (unlikely(err)) -+ goto out_procfs; -+ err = au_hnotify_init(); -+ if (unlikely(err)) -+ goto out_wkq; -+ err = au_sysrq_init(); -+ if (unlikely(err)) -+ goto out_hin; -+ err = au_cache_init(); -+ if (unlikely(err)) -+ goto out_sysrq; -+ err = register_filesystem(&aufs_fs_type); -+ if (unlikely(err)) -+ goto out_cache; -+ /* since we define pr_fmt, call printk directly */ -+ printk(KERN_INFO AUFS_NAME " " AUFS_VERSION "\n"); -+ goto out; /* success */ -+ -+out_cache: -+ au_cache_fin(); -+out_sysrq: -+ au_sysrq_fin(); -+out_hin: -+ au_hnotify_fin(); -+out_wkq: -+ au_wkq_fin(); -+out_procfs: -+ au_procfs_fin(); -+out_sysaufs: -+ sysaufs_fin(); -+ au_dy_fin(); -+out: -+ return err; -+} -+ -+static void __exit aufs_exit(void) -+{ -+ unregister_filesystem(&aufs_fs_type); -+ au_cache_fin(); -+ au_sysrq_fin(); -+ au_hnotify_fin(); -+ au_wkq_fin(); -+ au_procfs_fin(); -+ sysaufs_fin(); -+ au_dy_fin(); -+} -+ -+module_init(aufs_init); -+module_exit(aufs_exit); -diff -Nur linux-2.6.37.orig/fs/aufs/module.h linux-2.6.37/fs/aufs/module.h ---- linux-2.6.37.orig/fs/aufs/module.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/module.h 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,91 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * module initialization and module-global -+ */ -+ -+#ifndef __AUFS_MODULE_H__ -+#define __AUFS_MODULE_H__ -+ -+#ifdef __KERNEL__ -+ -+#include -+ -+struct path; -+struct seq_file; -+ -+/* module parameters */ -+extern int sysaufs_brs; -+ -+/* ---------------------------------------------------------------------- */ -+ -+extern int au_dir_roflags; -+ -+void *au_kzrealloc(void *p, unsigned int nused, unsigned int new_sz, gfp_t gfp); -+int au_seq_path(struct seq_file *seq, struct path *path); -+ -+#ifdef CONFIG_PROC_FS -+/* procfs.c */ -+int __init au_procfs_init(void); -+void au_procfs_fin(void); -+#else -+AuStubInt0(au_procfs_init, void); -+AuStubVoid(au_procfs_fin, void); -+#endif -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* kmem cache */ -+enum { -+ AuCache_DINFO, -+ AuCache_ICNTNR, -+ AuCache_FINFO, -+ AuCache_VDIR, -+ AuCache_DEHSTR, -+#ifdef CONFIG_AUFS_HNOTIFY -+ AuCache_HNOTIFY, -+#endif -+ AuCache_Last -+}; -+ -+#define AuCacheFlags (SLAB_RECLAIM_ACCOUNT | SLAB_MEM_SPREAD) -+#define AuCache(type) KMEM_CACHE(type, AuCacheFlags) -+#define AuCacheCtor(type, ctor) \ -+ kmem_cache_create(#type, sizeof(struct type), \ -+ __alignof__(struct type), AuCacheFlags, ctor) -+ -+extern struct kmem_cache *au_cachep[]; -+ -+#define AuCacheFuncs(name, index) \ -+static inline struct au_##name *au_cache_alloc_##name(void) \ -+{ return kmem_cache_alloc(au_cachep[AuCache_##index], GFP_NOFS); } \ -+static inline void au_cache_free_##name(struct au_##name *p) \ -+{ kmem_cache_free(au_cachep[AuCache_##index], p); } -+ -+AuCacheFuncs(dinfo, DINFO); -+AuCacheFuncs(icntnr, ICNTNR); -+AuCacheFuncs(finfo, FINFO); -+AuCacheFuncs(vdir, VDIR); -+AuCacheFuncs(vdir_dehstr, DEHSTR); -+#ifdef CONFIG_AUFS_HNOTIFY -+AuCacheFuncs(hnotify, HNOTIFY); -+#endif -+ -+#endif /* __KERNEL__ */ -+#endif /* __AUFS_MODULE_H__ */ -diff -Nur linux-2.6.37.orig/fs/aufs/mtx.h linux-2.6.37/fs/aufs/mtx.h ---- linux-2.6.37.orig/fs/aufs/mtx.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/mtx.h 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,48 @@ -+/* -+ * Copyright (C) 2010-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * very ugly approach for aufs_mmap() -+ * never include this file from other than f_op.c. -+ * see f_op.c in detail. -+ */ -+ -+#ifndef __AUFS_MTX_H__ -+#define __AUFS_MTX_H__ -+ -+#ifdef __KERNEL__ -+ -+/* copied from ../kernel/mutex{,-debug}.h */ -+struct mutex; -+struct thread_info; -+#ifdef CONFIG_DEBUG_MUTEXES -+static inline void mutex_set_owner(struct mutex *lock) -+{ -+ lock->owner = current_thread_info(); -+} -+#else -+static inline void mutex_set_owner(struct mutex *lock) -+{ -+#ifdef CONFIG_SMP -+ lock->owner = current_thread_info(); -+#endif -+} -+#endif -+ -+#endif /* __KERNEL__ */ -+#endif /* __AUFS_MTX_H__ */ -diff -Nur linux-2.6.37.orig/fs/aufs/opts.c linux-2.6.37/fs/aufs/opts.c ---- linux-2.6.37.orig/fs/aufs/opts.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/opts.c 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,1595 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * mount options/flags -+ */ -+ -+#include -+#include -+#include -+#include /* a distribution requires */ -+#include -+#include "aufs.h" -+ -+/* ---------------------------------------------------------------------- */ -+ -+enum { -+ Opt_br, -+ Opt_add, Opt_del, Opt_mod, Opt_reorder, Opt_append, Opt_prepend, -+ Opt_idel, Opt_imod, Opt_ireorder, -+ Opt_dirwh, Opt_rdcache, Opt_rdblk, Opt_rdhash, Opt_rendir, -+ Opt_rdblk_def, Opt_rdhash_def, -+ Opt_xino, Opt_zxino, Opt_noxino, -+ Opt_trunc_xino, Opt_trunc_xino_v, Opt_notrunc_xino, -+ Opt_trunc_xino_path, Opt_itrunc_xino, -+ Opt_trunc_xib, Opt_notrunc_xib, -+ Opt_shwh, Opt_noshwh, -+ Opt_plink, Opt_noplink, Opt_list_plink, -+ Opt_udba, -+ Opt_dio, Opt_nodio, -+ /* Opt_lock, Opt_unlock, */ -+ Opt_cmd, Opt_cmd_args, -+ Opt_diropq_a, Opt_diropq_w, -+ Opt_warn_perm, Opt_nowarn_perm, -+ Opt_wbr_copyup, Opt_wbr_create, -+ Opt_refrof, Opt_norefrof, -+ Opt_verbose, Opt_noverbose, -+ Opt_sum, Opt_nosum, Opt_wsum, -+ Opt_tail, Opt_ignore, Opt_ignore_silent, Opt_err -+}; -+ -+static match_table_t options = { -+ {Opt_br, "br=%s"}, -+ {Opt_br, "br:%s"}, -+ -+ {Opt_add, "add=%d:%s"}, -+ {Opt_add, "add:%d:%s"}, -+ {Opt_add, "ins=%d:%s"}, -+ {Opt_add, "ins:%d:%s"}, -+ {Opt_append, "append=%s"}, -+ {Opt_append, "append:%s"}, -+ {Opt_prepend, "prepend=%s"}, -+ {Opt_prepend, "prepend:%s"}, -+ -+ {Opt_del, "del=%s"}, -+ {Opt_del, "del:%s"}, -+ /* {Opt_idel, "idel:%d"}, */ -+ {Opt_mod, "mod=%s"}, -+ {Opt_mod, "mod:%s"}, -+ /* {Opt_imod, "imod:%d:%s"}, */ -+ -+ {Opt_dirwh, "dirwh=%d"}, -+ -+ {Opt_xino, "xino=%s"}, -+ {Opt_noxino, "noxino"}, -+ {Opt_trunc_xino, "trunc_xino"}, -+ {Opt_trunc_xino_v, "trunc_xino_v=%d:%d"}, -+ {Opt_notrunc_xino, "notrunc_xino"}, -+ {Opt_trunc_xino_path, "trunc_xino=%s"}, -+ {Opt_itrunc_xino, "itrunc_xino=%d"}, -+ /* {Opt_zxino, "zxino=%s"}, */ -+ {Opt_trunc_xib, "trunc_xib"}, -+ {Opt_notrunc_xib, "notrunc_xib"}, -+ -+#ifdef CONFIG_PROC_FS -+ {Opt_plink, "plink"}, -+#else -+ {Opt_ignore_silent, "plink"}, -+#endif -+ -+ {Opt_noplink, "noplink"}, -+ -+#ifdef CONFIG_AUFS_DEBUG -+ {Opt_list_plink, "list_plink"}, -+#endif -+ -+ {Opt_udba, "udba=%s"}, -+ -+ {Opt_dio, "dio"}, -+ {Opt_nodio, "nodio"}, -+ -+ {Opt_diropq_a, "diropq=always"}, -+ {Opt_diropq_a, "diropq=a"}, -+ {Opt_diropq_w, "diropq=whiteouted"}, -+ {Opt_diropq_w, "diropq=w"}, -+ -+ {Opt_warn_perm, "warn_perm"}, -+ {Opt_nowarn_perm, "nowarn_perm"}, -+ -+ /* keep them temporary */ -+ {Opt_ignore_silent, "coo=%s"}, -+ {Opt_ignore_silent, "nodlgt"}, -+ {Opt_ignore_silent, "nodirperm1"}, -+ {Opt_ignore_silent, "clean_plink"}, -+ -+#ifdef CONFIG_AUFS_SHWH -+ {Opt_shwh, "shwh"}, -+#endif -+ {Opt_noshwh, "noshwh"}, -+ -+ {Opt_rendir, "rendir=%d"}, -+ -+ {Opt_refrof, "refrof"}, -+ {Opt_norefrof, "norefrof"}, -+ -+ {Opt_verbose, "verbose"}, -+ {Opt_verbose, "v"}, -+ {Opt_noverbose, "noverbose"}, -+ {Opt_noverbose, "quiet"}, -+ {Opt_noverbose, "q"}, -+ {Opt_noverbose, "silent"}, -+ -+ {Opt_sum, "sum"}, -+ {Opt_nosum, "nosum"}, -+ {Opt_wsum, "wsum"}, -+ -+ {Opt_rdcache, "rdcache=%d"}, -+ {Opt_rdblk, "rdblk=%d"}, -+ {Opt_rdblk_def, "rdblk=def"}, -+ {Opt_rdhash, "rdhash=%d"}, -+ {Opt_rdhash_def, "rdhash=def"}, -+ -+ {Opt_wbr_create, "create=%s"}, -+ {Opt_wbr_create, "create_policy=%s"}, -+ {Opt_wbr_copyup, "cpup=%s"}, -+ {Opt_wbr_copyup, "copyup=%s"}, -+ {Opt_wbr_copyup, "copyup_policy=%s"}, -+ -+ /* internal use for the scripts */ -+ {Opt_ignore_silent, "si=%s"}, -+ -+ {Opt_br, "dirs=%s"}, -+ {Opt_ignore, "debug=%d"}, -+ {Opt_ignore, "delete=whiteout"}, -+ {Opt_ignore, "delete=all"}, -+ {Opt_ignore, "imap=%s"}, -+ -+ /* temporary workaround, due to old mount(8)? */ -+ {Opt_ignore_silent, "relatime"}, -+ -+ {Opt_err, NULL} -+}; -+ -+/* ---------------------------------------------------------------------- */ -+ -+static const char *au_parser_pattern(int val, struct match_token *token) -+{ -+ while (token->pattern) { -+ if (token->token == val) -+ return token->pattern; -+ token++; -+ } -+ BUG(); -+ return "??"; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static match_table_t brperms = { -+ {AuBrPerm_RO, AUFS_BRPERM_RO}, -+ {AuBrPerm_RR, AUFS_BRPERM_RR}, -+ {AuBrPerm_RW, AUFS_BRPERM_RW}, -+ -+ {AuBrPerm_ROWH, AUFS_BRPERM_ROWH}, -+ {AuBrPerm_RRWH, AUFS_BRPERM_RRWH}, -+ {AuBrPerm_RWNoLinkWH, AUFS_BRPERM_RWNLWH}, -+ -+ {AuBrPerm_ROWH, "nfsro"}, -+ {AuBrPerm_RO, NULL} -+}; -+ -+static int noinline_for_stack br_perm_val(char *perm) -+{ -+ int val; -+ substring_t args[MAX_OPT_ARGS]; -+ -+ val = match_token(perm, brperms, args); -+ return val; -+} -+ -+const char *au_optstr_br_perm(int brperm) -+{ -+ return au_parser_pattern(brperm, (void *)brperms); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static match_table_t udbalevel = { -+ {AuOpt_UDBA_REVAL, "reval"}, -+ {AuOpt_UDBA_NONE, "none"}, -+#ifdef CONFIG_AUFS_HNOTIFY -+ {AuOpt_UDBA_HNOTIFY, "notify"}, /* abstraction */ -+#ifdef CONFIG_AUFS_HFSNOTIFY -+ {AuOpt_UDBA_HNOTIFY, "fsnotify"}, -+#endif -+#endif -+ {-1, NULL} -+}; -+ -+static int noinline_for_stack udba_val(char *str) -+{ -+ substring_t args[MAX_OPT_ARGS]; -+ -+ return match_token(str, udbalevel, args); -+} -+ -+const char *au_optstr_udba(int udba) -+{ -+ return au_parser_pattern(udba, (void *)udbalevel); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static match_table_t au_wbr_create_policy = { -+ {AuWbrCreate_TDP, "tdp"}, -+ {AuWbrCreate_TDP, "top-down-parent"}, -+ {AuWbrCreate_RR, "rr"}, -+ {AuWbrCreate_RR, "round-robin"}, -+ {AuWbrCreate_MFS, "mfs"}, -+ {AuWbrCreate_MFS, "most-free-space"}, -+ {AuWbrCreate_MFSV, "mfs:%d"}, -+ {AuWbrCreate_MFSV, "most-free-space:%d"}, -+ -+ {AuWbrCreate_MFSRR, "mfsrr:%d"}, -+ {AuWbrCreate_MFSRRV, "mfsrr:%d:%d"}, -+ {AuWbrCreate_PMFS, "pmfs"}, -+ {AuWbrCreate_PMFSV, "pmfs:%d"}, -+ -+ {-1, NULL} -+}; -+ -+/* -+ * cf. linux/lib/parser.c and cmdline.c -+ * gave up calling memparse() since it uses simple_strtoull() instead of -+ * strict_...(). -+ */ -+static int noinline_for_stack -+au_match_ull(substring_t *s, unsigned long long *result) -+{ -+ int err; -+ unsigned int len; -+ char a[32]; -+ -+ err = -ERANGE; -+ len = s->to - s->from; -+ if (len + 1 <= sizeof(a)) { -+ memcpy(a, s->from, len); -+ a[len] = '\0'; -+ err = strict_strtoull(a, 0, result); -+ } -+ return err; -+} -+ -+static int au_wbr_mfs_wmark(substring_t *arg, char *str, -+ struct au_opt_wbr_create *create) -+{ -+ int err; -+ unsigned long long ull; -+ -+ err = 0; -+ if (!au_match_ull(arg, &ull)) -+ create->mfsrr_watermark = ull; -+ else { -+ pr_err("bad integer in %s\n", str); -+ err = -EINVAL; -+ } -+ -+ return err; -+} -+ -+static int au_wbr_mfs_sec(substring_t *arg, char *str, -+ struct au_opt_wbr_create *create) -+{ -+ int n, err; -+ -+ err = 0; -+ if (!match_int(arg, &n) && 0 <= n && n <= AUFS_MFS_MAX_SEC) -+ create->mfs_second = n; -+ else { -+ pr_err("bad integer in %s\n", str); -+ err = -EINVAL; -+ } -+ -+ return err; -+} -+ -+static int noinline_for_stack -+au_wbr_create_val(char *str, struct au_opt_wbr_create *create) -+{ -+ int err, e; -+ substring_t args[MAX_OPT_ARGS]; -+ -+ err = match_token(str, au_wbr_create_policy, args); -+ create->wbr_create = err; -+ switch (err) { -+ case AuWbrCreate_MFSRRV: -+ e = au_wbr_mfs_wmark(&args[0], str, create); -+ if (!e) -+ e = au_wbr_mfs_sec(&args[1], str, create); -+ if (unlikely(e)) -+ err = e; -+ break; -+ case AuWbrCreate_MFSRR: -+ e = au_wbr_mfs_wmark(&args[0], str, create); -+ if (unlikely(e)) { -+ err = e; -+ break; -+ } -+ /*FALLTHROUGH*/ -+ case AuWbrCreate_MFS: -+ case AuWbrCreate_PMFS: -+ create->mfs_second = AUFS_MFS_DEF_SEC; -+ break; -+ case AuWbrCreate_MFSV: -+ case AuWbrCreate_PMFSV: -+ e = au_wbr_mfs_sec(&args[0], str, create); -+ if (unlikely(e)) -+ err = e; -+ break; -+ } -+ -+ return err; -+} -+ -+const char *au_optstr_wbr_create(int wbr_create) -+{ -+ return au_parser_pattern(wbr_create, (void *)au_wbr_create_policy); -+} -+ -+static match_table_t au_wbr_copyup_policy = { -+ {AuWbrCopyup_TDP, "tdp"}, -+ {AuWbrCopyup_TDP, "top-down-parent"}, -+ {AuWbrCopyup_BUP, "bup"}, -+ {AuWbrCopyup_BUP, "bottom-up-parent"}, -+ {AuWbrCopyup_BU, "bu"}, -+ {AuWbrCopyup_BU, "bottom-up"}, -+ {-1, NULL} -+}; -+ -+static int noinline_for_stack au_wbr_copyup_val(char *str) -+{ -+ substring_t args[MAX_OPT_ARGS]; -+ -+ return match_token(str, au_wbr_copyup_policy, args); -+} -+ -+const char *au_optstr_wbr_copyup(int wbr_copyup) -+{ -+ return au_parser_pattern(wbr_copyup, (void *)au_wbr_copyup_policy); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static const int lkup_dirflags = LOOKUP_FOLLOW | LOOKUP_DIRECTORY; -+ -+static void dump_opts(struct au_opts *opts) -+{ -+#ifdef CONFIG_AUFS_DEBUG -+ /* reduce stack space */ -+ union { -+ struct au_opt_add *add; -+ struct au_opt_del *del; -+ struct au_opt_mod *mod; -+ struct au_opt_xino *xino; -+ struct au_opt_xino_itrunc *xino_itrunc; -+ struct au_opt_wbr_create *create; -+ } u; -+ struct au_opt *opt; -+ -+ opt = opts->opt; -+ while (opt->type != Opt_tail) { -+ switch (opt->type) { -+ case Opt_add: -+ u.add = &opt->add; -+ AuDbg("add {b%d, %s, 0x%x, %p}\n", -+ u.add->bindex, u.add->pathname, u.add->perm, -+ u.add->path.dentry); -+ break; -+ case Opt_del: -+ case Opt_idel: -+ u.del = &opt->del; -+ AuDbg("del {%s, %p}\n", -+ u.del->pathname, u.del->h_path.dentry); -+ break; -+ case Opt_mod: -+ case Opt_imod: -+ u.mod = &opt->mod; -+ AuDbg("mod {%s, 0x%x, %p}\n", -+ u.mod->path, u.mod->perm, u.mod->h_root); -+ break; -+ case Opt_append: -+ u.add = &opt->add; -+ AuDbg("append {b%d, %s, 0x%x, %p}\n", -+ u.add->bindex, u.add->pathname, u.add->perm, -+ u.add->path.dentry); -+ break; -+ case Opt_prepend: -+ u.add = &opt->add; -+ AuDbg("prepend {b%d, %s, 0x%x, %p}\n", -+ u.add->bindex, u.add->pathname, u.add->perm, -+ u.add->path.dentry); -+ break; -+ case Opt_dirwh: -+ AuDbg("dirwh %d\n", opt->dirwh); -+ break; -+ case Opt_rdcache: -+ AuDbg("rdcache %d\n", opt->rdcache); -+ break; -+ case Opt_rdblk: -+ AuDbg("rdblk %u\n", opt->rdblk); -+ break; -+ case Opt_rdblk_def: -+ AuDbg("rdblk_def\n"); -+ break; -+ case Opt_rdhash: -+ AuDbg("rdhash %u\n", opt->rdhash); -+ break; -+ case Opt_rdhash_def: -+ AuDbg("rdhash_def\n"); -+ break; -+ case Opt_xino: -+ u.xino = &opt->xino; -+ AuDbg("xino {%s %.*s}\n", -+ u.xino->path, -+ AuDLNPair(u.xino->file->f_dentry)); -+ break; -+ case Opt_trunc_xino: -+ AuLabel(trunc_xino); -+ break; -+ case Opt_notrunc_xino: -+ AuLabel(notrunc_xino); -+ break; -+ case Opt_trunc_xino_path: -+ case Opt_itrunc_xino: -+ u.xino_itrunc = &opt->xino_itrunc; -+ AuDbg("trunc_xino %d\n", u.xino_itrunc->bindex); -+ break; -+ -+ case Opt_noxino: -+ AuLabel(noxino); -+ break; -+ case Opt_trunc_xib: -+ AuLabel(trunc_xib); -+ break; -+ case Opt_notrunc_xib: -+ AuLabel(notrunc_xib); -+ break; -+ case Opt_shwh: -+ AuLabel(shwh); -+ break; -+ case Opt_noshwh: -+ AuLabel(noshwh); -+ break; -+ case Opt_plink: -+ AuLabel(plink); -+ break; -+ case Opt_noplink: -+ AuLabel(noplink); -+ break; -+ case Opt_list_plink: -+ AuLabel(list_plink); -+ break; -+ case Opt_udba: -+ AuDbg("udba %d, %s\n", -+ opt->udba, au_optstr_udba(opt->udba)); -+ break; -+ case Opt_dio: -+ AuLabel(dio); -+ break; -+ case Opt_nodio: -+ AuLabel(nodio); -+ break; -+ case Opt_diropq_a: -+ AuLabel(diropq_a); -+ break; -+ case Opt_diropq_w: -+ AuLabel(diropq_w); -+ break; -+ case Opt_warn_perm: -+ AuLabel(warn_perm); -+ break; -+ case Opt_nowarn_perm: -+ AuLabel(nowarn_perm); -+ break; -+ case Opt_refrof: -+ AuLabel(refrof); -+ break; -+ case Opt_norefrof: -+ AuLabel(norefrof); -+ break; -+ case Opt_verbose: -+ AuLabel(verbose); -+ break; -+ case Opt_noverbose: -+ AuLabel(noverbose); -+ break; -+ case Opt_sum: -+ AuLabel(sum); -+ break; -+ case Opt_nosum: -+ AuLabel(nosum); -+ break; -+ case Opt_wsum: -+ AuLabel(wsum); -+ break; -+ case Opt_wbr_create: -+ u.create = &opt->wbr_create; -+ AuDbg("create %d, %s\n", u.create->wbr_create, -+ au_optstr_wbr_create(u.create->wbr_create)); -+ switch (u.create->wbr_create) { -+ case AuWbrCreate_MFSV: -+ case AuWbrCreate_PMFSV: -+ AuDbg("%d sec\n", u.create->mfs_second); -+ break; -+ case AuWbrCreate_MFSRR: -+ AuDbg("%llu watermark\n", -+ u.create->mfsrr_watermark); -+ break; -+ case AuWbrCreate_MFSRRV: -+ AuDbg("%llu watermark, %d sec\n", -+ u.create->mfsrr_watermark, -+ u.create->mfs_second); -+ break; -+ } -+ break; -+ case Opt_wbr_copyup: -+ AuDbg("copyup %d, %s\n", opt->wbr_copyup, -+ au_optstr_wbr_copyup(opt->wbr_copyup)); -+ break; -+ default: -+ BUG(); -+ } -+ opt++; -+ } -+#endif -+} -+ -+void au_opts_free(struct au_opts *opts) -+{ -+ struct au_opt *opt; -+ -+ opt = opts->opt; -+ while (opt->type != Opt_tail) { -+ switch (opt->type) { -+ case Opt_add: -+ case Opt_append: -+ case Opt_prepend: -+ path_put(&opt->add.path); -+ break; -+ case Opt_del: -+ case Opt_idel: -+ path_put(&opt->del.h_path); -+ break; -+ case Opt_mod: -+ case Opt_imod: -+ dput(opt->mod.h_root); -+ break; -+ case Opt_xino: -+ fput(opt->xino.file); -+ break; -+ } -+ opt++; -+ } -+} -+ -+static int opt_add(struct au_opt *opt, char *opt_str, unsigned long sb_flags, -+ aufs_bindex_t bindex) -+{ -+ int err; -+ struct au_opt_add *add = &opt->add; -+ char *p; -+ -+ add->bindex = bindex; -+ add->perm = AuBrPerm_Last; -+ add->pathname = opt_str; -+ p = strchr(opt_str, '='); -+ if (p) { -+ *p++ = 0; -+ if (*p) -+ add->perm = br_perm_val(p); -+ } -+ -+ err = vfsub_kern_path(add->pathname, lkup_dirflags, &add->path); -+ if (!err) { -+ if (!p) { -+ add->perm = AuBrPerm_RO; -+ if (au_test_fs_rr(add->path.dentry->d_sb)) -+ add->perm = AuBrPerm_RR; -+ else if (!bindex && !(sb_flags & MS_RDONLY)) -+ add->perm = AuBrPerm_RW; -+ } -+ opt->type = Opt_add; -+ goto out; -+ } -+ pr_err("lookup failed %s (%d)\n", add->pathname, err); -+ err = -EINVAL; -+ -+out: -+ return err; -+} -+ -+static int au_opts_parse_del(struct au_opt_del *del, substring_t args[]) -+{ -+ int err; -+ -+ del->pathname = args[0].from; -+ AuDbg("del path %s\n", del->pathname); -+ -+ err = vfsub_kern_path(del->pathname, lkup_dirflags, &del->h_path); -+ if (unlikely(err)) -+ pr_err("lookup failed %s (%d)\n", del->pathname, err); -+ -+ return err; -+} -+ -+#if 0 /* reserved for future use */ -+static int au_opts_parse_idel(struct super_block *sb, aufs_bindex_t bindex, -+ struct au_opt_del *del, substring_t args[]) -+{ -+ int err; -+ struct dentry *root; -+ -+ err = -EINVAL; -+ root = sb->s_root; -+ aufs_read_lock(root, AuLock_FLUSH); -+ if (bindex < 0 || au_sbend(sb) < bindex) { -+ pr_err("out of bounds, %d\n", bindex); -+ goto out; -+ } -+ -+ err = 0; -+ del->h_path.dentry = dget(au_h_dptr(root, bindex)); -+ del->h_path.mnt = mntget(au_sbr_mnt(sb, bindex)); -+ -+out: -+ aufs_read_unlock(root, !AuLock_IR); -+ return err; -+} -+#endif -+ -+static int noinline_for_stack -+au_opts_parse_mod(struct au_opt_mod *mod, substring_t args[]) -+{ -+ int err; -+ struct path path; -+ char *p; -+ -+ err = -EINVAL; -+ mod->path = args[0].from; -+ p = strchr(mod->path, '='); -+ if (unlikely(!p)) { -+ pr_err("no permssion %s\n", args[0].from); -+ goto out; -+ } -+ -+ *p++ = 0; -+ err = vfsub_kern_path(mod->path, lkup_dirflags, &path); -+ if (unlikely(err)) { -+ pr_err("lookup failed %s (%d)\n", mod->path, err); -+ goto out; -+ } -+ -+ mod->perm = br_perm_val(p); -+ AuDbg("mod path %s, perm 0x%x, %s\n", mod->path, mod->perm, p); -+ mod->h_root = dget(path.dentry); -+ path_put(&path); -+ -+out: -+ return err; -+} -+ -+#if 0 /* reserved for future use */ -+static int au_opts_parse_imod(struct super_block *sb, aufs_bindex_t bindex, -+ struct au_opt_mod *mod, substring_t args[]) -+{ -+ int err; -+ struct dentry *root; -+ -+ err = -EINVAL; -+ root = sb->s_root; -+ aufs_read_lock(root, AuLock_FLUSH); -+ if (bindex < 0 || au_sbend(sb) < bindex) { -+ pr_err("out of bounds, %d\n", bindex); -+ goto out; -+ } -+ -+ err = 0; -+ mod->perm = br_perm_val(args[1].from); -+ AuDbg("mod path %s, perm 0x%x, %s\n", -+ mod->path, mod->perm, args[1].from); -+ mod->h_root = dget(au_h_dptr(root, bindex)); -+ -+out: -+ aufs_read_unlock(root, !AuLock_IR); -+ return err; -+} -+#endif -+ -+static int au_opts_parse_xino(struct super_block *sb, struct au_opt_xino *xino, -+ substring_t args[]) -+{ -+ int err; -+ struct file *file; -+ -+ file = au_xino_create(sb, args[0].from, /*silent*/0); -+ err = PTR_ERR(file); -+ if (IS_ERR(file)) -+ goto out; -+ -+ err = -EINVAL; -+ if (unlikely(file->f_dentry->d_sb == sb)) { -+ fput(file); -+ pr_err("%s must be outside\n", args[0].from); -+ goto out; -+ } -+ -+ err = 0; -+ xino->file = file; -+ xino->path = args[0].from; -+ -+out: -+ return err; -+} -+ -+static int noinline_for_stack -+au_opts_parse_xino_itrunc_path(struct super_block *sb, -+ struct au_opt_xino_itrunc *xino_itrunc, -+ substring_t args[]) -+{ -+ int err; -+ aufs_bindex_t bend, bindex; -+ struct path path; -+ struct dentry *root; -+ -+ err = vfsub_kern_path(args[0].from, lkup_dirflags, &path); -+ if (unlikely(err)) { -+ pr_err("lookup failed %s (%d)\n", args[0].from, err); -+ goto out; -+ } -+ -+ xino_itrunc->bindex = -1; -+ root = sb->s_root; -+ aufs_read_lock(root, AuLock_FLUSH); -+ bend = au_sbend(sb); -+ for (bindex = 0; bindex <= bend; bindex++) { -+ if (au_h_dptr(root, bindex) == path.dentry) { -+ xino_itrunc->bindex = bindex; -+ break; -+ } -+ } -+ aufs_read_unlock(root, !AuLock_IR); -+ path_put(&path); -+ -+ if (unlikely(xino_itrunc->bindex < 0)) { -+ pr_err("no such branch %s\n", args[0].from); -+ err = -EINVAL; -+ } -+ -+out: -+ return err; -+} -+ -+/* called without aufs lock */ -+int au_opts_parse(struct super_block *sb, char *str, struct au_opts *opts) -+{ -+ int err, n, token; -+ aufs_bindex_t bindex; -+ unsigned char skipped; -+ struct dentry *root; -+ struct au_opt *opt, *opt_tail; -+ char *opt_str; -+ /* reduce the stack space */ -+ union { -+ struct au_opt_xino_itrunc *xino_itrunc; -+ struct au_opt_wbr_create *create; -+ } u; -+ struct { -+ substring_t args[MAX_OPT_ARGS]; -+ } *a; -+ -+ err = -ENOMEM; -+ a = kmalloc(sizeof(*a), GFP_NOFS); -+ if (unlikely(!a)) -+ goto out; -+ -+ root = sb->s_root; -+ err = 0; -+ bindex = 0; -+ opt = opts->opt; -+ opt_tail = opt + opts->max_opt - 1; -+ opt->type = Opt_tail; -+ while (!err && (opt_str = strsep(&str, ",")) && *opt_str) { -+ err = -EINVAL; -+ skipped = 0; -+ token = match_token(opt_str, options, a->args); -+ switch (token) { -+ case Opt_br: -+ err = 0; -+ while (!err && (opt_str = strsep(&a->args[0].from, ":")) -+ && *opt_str) { -+ err = opt_add(opt, opt_str, opts->sb_flags, -+ bindex++); -+ if (unlikely(!err && ++opt > opt_tail)) { -+ err = -E2BIG; -+ break; -+ } -+ opt->type = Opt_tail; -+ skipped = 1; -+ } -+ break; -+ case Opt_add: -+ if (unlikely(match_int(&a->args[0], &n))) { -+ pr_err("bad integer in %s\n", opt_str); -+ break; -+ } -+ bindex = n; -+ err = opt_add(opt, a->args[1].from, opts->sb_flags, -+ bindex); -+ if (!err) -+ opt->type = token; -+ break; -+ case Opt_append: -+ err = opt_add(opt, a->args[0].from, opts->sb_flags, -+ /*dummy bindex*/1); -+ if (!err) -+ opt->type = token; -+ break; -+ case Opt_prepend: -+ err = opt_add(opt, a->args[0].from, opts->sb_flags, -+ /*bindex*/0); -+ if (!err) -+ opt->type = token; -+ break; -+ case Opt_del: -+ err = au_opts_parse_del(&opt->del, a->args); -+ if (!err) -+ opt->type = token; -+ break; -+#if 0 /* reserved for future use */ -+ case Opt_idel: -+ del->pathname = "(indexed)"; -+ if (unlikely(match_int(&args[0], &n))) { -+ pr_err("bad integer in %s\n", opt_str); -+ break; -+ } -+ err = au_opts_parse_idel(sb, n, &opt->del, a->args); -+ if (!err) -+ opt->type = token; -+ break; -+#endif -+ case Opt_mod: -+ err = au_opts_parse_mod(&opt->mod, a->args); -+ if (!err) -+ opt->type = token; -+ break; -+#ifdef IMOD /* reserved for future use */ -+ case Opt_imod: -+ u.mod->path = "(indexed)"; -+ if (unlikely(match_int(&a->args[0], &n))) { -+ pr_err("bad integer in %s\n", opt_str); -+ break; -+ } -+ err = au_opts_parse_imod(sb, n, &opt->mod, a->args); -+ if (!err) -+ opt->type = token; -+ break; -+#endif -+ case Opt_xino: -+ err = au_opts_parse_xino(sb, &opt->xino, a->args); -+ if (!err) -+ opt->type = token; -+ break; -+ -+ case Opt_trunc_xino_path: -+ err = au_opts_parse_xino_itrunc_path -+ (sb, &opt->xino_itrunc, a->args); -+ if (!err) -+ opt->type = token; -+ break; -+ -+ case Opt_itrunc_xino: -+ u.xino_itrunc = &opt->xino_itrunc; -+ if (unlikely(match_int(&a->args[0], &n))) { -+ pr_err("bad integer in %s\n", opt_str); -+ break; -+ } -+ u.xino_itrunc->bindex = n; -+ aufs_read_lock(root, AuLock_FLUSH); -+ if (n < 0 || au_sbend(sb) < n) { -+ pr_err("out of bounds, %d\n", n); -+ aufs_read_unlock(root, !AuLock_IR); -+ break; -+ } -+ aufs_read_unlock(root, !AuLock_IR); -+ err = 0; -+ opt->type = token; -+ break; -+ -+ case Opt_dirwh: -+ if (unlikely(match_int(&a->args[0], &opt->dirwh))) -+ break; -+ err = 0; -+ opt->type = token; -+ break; -+ -+ case Opt_rdcache: -+ if (unlikely(match_int(&a->args[0], &n))) { -+ pr_err("bad integer in %s\n", opt_str); -+ break; -+ } -+ if (unlikely(n > AUFS_RDCACHE_MAX)) { -+ pr_err("rdcache must be smaller than %d\n", -+ AUFS_RDCACHE_MAX); -+ break; -+ } -+ opt->rdcache = n; -+ err = 0; -+ opt->type = token; -+ break; -+ case Opt_rdblk: -+ if (unlikely(match_int(&a->args[0], &n) -+ || n < 0 -+ || n > KMALLOC_MAX_SIZE)) { -+ pr_err("bad integer in %s\n", opt_str); -+ break; -+ } -+ if (unlikely(n && n < NAME_MAX)) { -+ pr_err("rdblk must be larger than %d\n", -+ NAME_MAX); -+ break; -+ } -+ opt->rdblk = n; -+ err = 0; -+ opt->type = token; -+ break; -+ case Opt_rdhash: -+ if (unlikely(match_int(&a->args[0], &n) -+ || n < 0 -+ || n * sizeof(struct hlist_head) -+ > KMALLOC_MAX_SIZE)) { -+ pr_err("bad integer in %s\n", opt_str); -+ break; -+ } -+ opt->rdhash = n; -+ err = 0; -+ opt->type = token; -+ break; -+ -+ case Opt_trunc_xino: -+ case Opt_notrunc_xino: -+ case Opt_noxino: -+ case Opt_trunc_xib: -+ case Opt_notrunc_xib: -+ case Opt_shwh: -+ case Opt_noshwh: -+ case Opt_plink: -+ case Opt_noplink: -+ case Opt_list_plink: -+ case Opt_dio: -+ case Opt_nodio: -+ case Opt_diropq_a: -+ case Opt_diropq_w: -+ case Opt_warn_perm: -+ case Opt_nowarn_perm: -+ case Opt_refrof: -+ case Opt_norefrof: -+ case Opt_verbose: -+ case Opt_noverbose: -+ case Opt_sum: -+ case Opt_nosum: -+ case Opt_wsum: -+ case Opt_rdblk_def: -+ case Opt_rdhash_def: -+ err = 0; -+ opt->type = token; -+ break; -+ -+ case Opt_udba: -+ opt->udba = udba_val(a->args[0].from); -+ if (opt->udba >= 0) { -+ err = 0; -+ opt->type = token; -+ } else -+ pr_err("wrong value, %s\n", opt_str); -+ break; -+ -+ case Opt_wbr_create: -+ u.create = &opt->wbr_create; -+ u.create->wbr_create -+ = au_wbr_create_val(a->args[0].from, u.create); -+ if (u.create->wbr_create >= 0) { -+ err = 0; -+ opt->type = token; -+ } else -+ pr_err("wrong value, %s\n", opt_str); -+ break; -+ case Opt_wbr_copyup: -+ opt->wbr_copyup = au_wbr_copyup_val(a->args[0].from); -+ if (opt->wbr_copyup >= 0) { -+ err = 0; -+ opt->type = token; -+ } else -+ pr_err("wrong value, %s\n", opt_str); -+ break; -+ -+ case Opt_ignore: -+ pr_warning("ignored %s\n", opt_str); -+ /*FALLTHROUGH*/ -+ case Opt_ignore_silent: -+ skipped = 1; -+ err = 0; -+ break; -+ case Opt_err: -+ pr_err("unknown option %s\n", opt_str); -+ break; -+ } -+ -+ if (!err && !skipped) { -+ if (unlikely(++opt > opt_tail)) { -+ err = -E2BIG; -+ opt--; -+ opt->type = Opt_tail; -+ break; -+ } -+ opt->type = Opt_tail; -+ } -+ } -+ -+ kfree(a); -+ dump_opts(opts); -+ if (unlikely(err)) -+ au_opts_free(opts); -+ -+out: -+ return err; -+} -+ -+static int au_opt_wbr_create(struct super_block *sb, -+ struct au_opt_wbr_create *create) -+{ -+ int err; -+ struct au_sbinfo *sbinfo; -+ -+ SiMustWriteLock(sb); -+ -+ err = 1; /* handled */ -+ sbinfo = au_sbi(sb); -+ if (sbinfo->si_wbr_create_ops->fin) { -+ err = sbinfo->si_wbr_create_ops->fin(sb); -+ if (!err) -+ err = 1; -+ } -+ -+ sbinfo->si_wbr_create = create->wbr_create; -+ sbinfo->si_wbr_create_ops = au_wbr_create_ops + create->wbr_create; -+ switch (create->wbr_create) { -+ case AuWbrCreate_MFSRRV: -+ case AuWbrCreate_MFSRR: -+ sbinfo->si_wbr_mfs.mfsrr_watermark = create->mfsrr_watermark; -+ /*FALLTHROUGH*/ -+ case AuWbrCreate_MFS: -+ case AuWbrCreate_MFSV: -+ case AuWbrCreate_PMFS: -+ case AuWbrCreate_PMFSV: -+ sbinfo->si_wbr_mfs.mfs_expire -+ = msecs_to_jiffies(create->mfs_second * MSEC_PER_SEC); -+ break; -+ } -+ -+ if (sbinfo->si_wbr_create_ops->init) -+ sbinfo->si_wbr_create_ops->init(sb); /* ignore */ -+ -+ return err; -+} -+ -+/* -+ * returns, -+ * plus: processed without an error -+ * zero: unprocessed -+ */ -+static int au_opt_simple(struct super_block *sb, struct au_opt *opt, -+ struct au_opts *opts) -+{ -+ int err; -+ struct au_sbinfo *sbinfo; -+ -+ SiMustWriteLock(sb); -+ -+ err = 1; /* handled */ -+ sbinfo = au_sbi(sb); -+ switch (opt->type) { -+ case Opt_udba: -+ sbinfo->si_mntflags &= ~AuOptMask_UDBA; -+ sbinfo->si_mntflags |= opt->udba; -+ opts->given_udba |= opt->udba; -+ break; -+ -+ case Opt_plink: -+ au_opt_set(sbinfo->si_mntflags, PLINK); -+ break; -+ case Opt_noplink: -+ if (au_opt_test(sbinfo->si_mntflags, PLINK)) -+ au_plink_put(sb, /*verbose*/1); -+ au_opt_clr(sbinfo->si_mntflags, PLINK); -+ break; -+ case Opt_list_plink: -+ if (au_opt_test(sbinfo->si_mntflags, PLINK)) -+ au_plink_list(sb); -+ break; -+ -+ case Opt_dio: -+ au_opt_set(sbinfo->si_mntflags, DIO); -+ au_fset_opts(opts->flags, REFRESH_DYAOP); -+ break; -+ case Opt_nodio: -+ au_opt_clr(sbinfo->si_mntflags, DIO); -+ au_fset_opts(opts->flags, REFRESH_DYAOP); -+ break; -+ -+ case Opt_diropq_a: -+ au_opt_set(sbinfo->si_mntflags, ALWAYS_DIROPQ); -+ break; -+ case Opt_diropq_w: -+ au_opt_clr(sbinfo->si_mntflags, ALWAYS_DIROPQ); -+ break; -+ -+ case Opt_warn_perm: -+ au_opt_set(sbinfo->si_mntflags, WARN_PERM); -+ break; -+ case Opt_nowarn_perm: -+ au_opt_clr(sbinfo->si_mntflags, WARN_PERM); -+ break; -+ -+ case Opt_refrof: -+ au_opt_set(sbinfo->si_mntflags, REFROF); -+ break; -+ case Opt_norefrof: -+ au_opt_clr(sbinfo->si_mntflags, REFROF); -+ break; -+ -+ case Opt_verbose: -+ au_opt_set(sbinfo->si_mntflags, VERBOSE); -+ break; -+ case Opt_noverbose: -+ au_opt_clr(sbinfo->si_mntflags, VERBOSE); -+ break; -+ -+ case Opt_sum: -+ au_opt_set(sbinfo->si_mntflags, SUM); -+ break; -+ case Opt_wsum: -+ au_opt_clr(sbinfo->si_mntflags, SUM); -+ au_opt_set(sbinfo->si_mntflags, SUM_W); -+ case Opt_nosum: -+ au_opt_clr(sbinfo->si_mntflags, SUM); -+ au_opt_clr(sbinfo->si_mntflags, SUM_W); -+ break; -+ -+ case Opt_wbr_create: -+ err = au_opt_wbr_create(sb, &opt->wbr_create); -+ break; -+ case Opt_wbr_copyup: -+ sbinfo->si_wbr_copyup = opt->wbr_copyup; -+ sbinfo->si_wbr_copyup_ops = au_wbr_copyup_ops + opt->wbr_copyup; -+ break; -+ -+ case Opt_dirwh: -+ sbinfo->si_dirwh = opt->dirwh; -+ break; -+ -+ case Opt_rdcache: -+ sbinfo->si_rdcache -+ = msecs_to_jiffies(opt->rdcache * MSEC_PER_SEC); -+ break; -+ case Opt_rdblk: -+ sbinfo->si_rdblk = opt->rdblk; -+ break; -+ case Opt_rdblk_def: -+ sbinfo->si_rdblk = AUFS_RDBLK_DEF; -+ break; -+ case Opt_rdhash: -+ sbinfo->si_rdhash = opt->rdhash; -+ break; -+ case Opt_rdhash_def: -+ sbinfo->si_rdhash = AUFS_RDHASH_DEF; -+ break; -+ -+ case Opt_shwh: -+ au_opt_set(sbinfo->si_mntflags, SHWH); -+ break; -+ case Opt_noshwh: -+ au_opt_clr(sbinfo->si_mntflags, SHWH); -+ break; -+ -+ case Opt_trunc_xino: -+ au_opt_set(sbinfo->si_mntflags, TRUNC_XINO); -+ break; -+ case Opt_notrunc_xino: -+ au_opt_clr(sbinfo->si_mntflags, TRUNC_XINO); -+ break; -+ -+ case Opt_trunc_xino_path: -+ case Opt_itrunc_xino: -+ err = au_xino_trunc(sb, opt->xino_itrunc.bindex); -+ if (!err) -+ err = 1; -+ break; -+ -+ case Opt_trunc_xib: -+ au_fset_opts(opts->flags, TRUNC_XIB); -+ break; -+ case Opt_notrunc_xib: -+ au_fclr_opts(opts->flags, TRUNC_XIB); -+ break; -+ -+ default: -+ err = 0; -+ break; -+ } -+ -+ return err; -+} -+ -+/* -+ * returns tri-state. -+ * plus: processed without an error -+ * zero: unprocessed -+ * minus: error -+ */ -+static int au_opt_br(struct super_block *sb, struct au_opt *opt, -+ struct au_opts *opts) -+{ -+ int err, do_refresh; -+ -+ err = 0; -+ switch (opt->type) { -+ case Opt_append: -+ opt->add.bindex = au_sbend(sb) + 1; -+ if (opt->add.bindex < 0) -+ opt->add.bindex = 0; -+ goto add; -+ case Opt_prepend: -+ opt->add.bindex = 0; -+ add: -+ case Opt_add: -+ err = au_br_add(sb, &opt->add, -+ au_ftest_opts(opts->flags, REMOUNT)); -+ if (!err) { -+ err = 1; -+ au_fset_opts(opts->flags, REFRESH); -+ } -+ break; -+ -+ case Opt_del: -+ case Opt_idel: -+ err = au_br_del(sb, &opt->del, -+ au_ftest_opts(opts->flags, REMOUNT)); -+ if (!err) { -+ err = 1; -+ au_fset_opts(opts->flags, TRUNC_XIB); -+ au_fset_opts(opts->flags, REFRESH); -+ } -+ break; -+ -+ case Opt_mod: -+ case Opt_imod: -+ err = au_br_mod(sb, &opt->mod, -+ au_ftest_opts(opts->flags, REMOUNT), -+ &do_refresh); -+ if (!err) { -+ err = 1; -+ if (do_refresh) -+ au_fset_opts(opts->flags, REFRESH); -+ } -+ break; -+ } -+ -+ return err; -+} -+ -+static int au_opt_xino(struct super_block *sb, struct au_opt *opt, -+ struct au_opt_xino **opt_xino, -+ struct au_opts *opts) -+{ -+ int err; -+ aufs_bindex_t bend, bindex; -+ struct dentry *root, *parent, *h_root; -+ -+ err = 0; -+ switch (opt->type) { -+ case Opt_xino: -+ err = au_xino_set(sb, &opt->xino, -+ !!au_ftest_opts(opts->flags, REMOUNT)); -+ if (unlikely(err)) -+ break; -+ -+ *opt_xino = &opt->xino; -+ au_xino_brid_set(sb, -1); -+ -+ /* safe d_parent access */ -+ parent = opt->xino.file->f_dentry->d_parent; -+ root = sb->s_root; -+ bend = au_sbend(sb); -+ for (bindex = 0; bindex <= bend; bindex++) { -+ h_root = au_h_dptr(root, bindex); -+ if (h_root == parent) { -+ au_xino_brid_set(sb, au_sbr_id(sb, bindex)); -+ break; -+ } -+ } -+ break; -+ -+ case Opt_noxino: -+ au_xino_clr(sb); -+ au_xino_brid_set(sb, -1); -+ *opt_xino = (void *)-1; -+ break; -+ } -+ -+ return err; -+} -+ -+int au_opts_verify(struct super_block *sb, unsigned long sb_flags, -+ unsigned int pending) -+{ -+ int err; -+ aufs_bindex_t bindex, bend; -+ unsigned char do_plink, skip, do_free; -+ struct au_branch *br; -+ struct au_wbr *wbr; -+ struct dentry *root; -+ struct inode *dir, *h_dir; -+ struct au_sbinfo *sbinfo; -+ struct au_hinode *hdir; -+ -+ SiMustAnyLock(sb); -+ -+ sbinfo = au_sbi(sb); -+ AuDebugOn(!(sbinfo->si_mntflags & AuOptMask_UDBA)); -+ -+ if (!(sb_flags & MS_RDONLY)) { -+ if (unlikely(!au_br_writable(au_sbr_perm(sb, 0)))) -+ pr_warning("first branch should be rw\n"); -+ if (unlikely(au_opt_test(sbinfo->si_mntflags, SHWH))) -+ pr_warning("shwh should be used with ro\n"); -+ } -+ -+ if (au_opt_test((sbinfo->si_mntflags | pending), UDBA_HNOTIFY) -+ && !au_opt_test(sbinfo->si_mntflags, XINO)) -+ pr_warning("udba=*notify requires xino\n"); -+ -+ err = 0; -+ root = sb->s_root; -+ dir = root->d_inode; -+ do_plink = !!au_opt_test(sbinfo->si_mntflags, PLINK); -+ bend = au_sbend(sb); -+ for (bindex = 0; !err && bindex <= bend; bindex++) { -+ skip = 0; -+ h_dir = au_h_iptr(dir, bindex); -+ br = au_sbr(sb, bindex); -+ do_free = 0; -+ -+ wbr = br->br_wbr; -+ if (wbr) -+ wbr_wh_read_lock(wbr); -+ -+ switch (br->br_perm) { -+ case AuBrPerm_RO: -+ case AuBrPerm_ROWH: -+ case AuBrPerm_RR: -+ case AuBrPerm_RRWH: -+ do_free = !!wbr; -+ skip = (!wbr -+ || (!wbr->wbr_whbase -+ && !wbr->wbr_plink -+ && !wbr->wbr_orph)); -+ break; -+ -+ case AuBrPerm_RWNoLinkWH: -+ /* skip = (!br->br_whbase && !br->br_orph); */ -+ skip = (!wbr || !wbr->wbr_whbase); -+ if (skip && wbr) { -+ if (do_plink) -+ skip = !!wbr->wbr_plink; -+ else -+ skip = !wbr->wbr_plink; -+ } -+ break; -+ -+ case AuBrPerm_RW: -+ /* skip = (br->br_whbase && br->br_ohph); */ -+ skip = (wbr && wbr->wbr_whbase); -+ if (skip) { -+ if (do_plink) -+ skip = !!wbr->wbr_plink; -+ else -+ skip = !wbr->wbr_plink; -+ } -+ break; -+ -+ default: -+ BUG(); -+ } -+ if (wbr) -+ wbr_wh_read_unlock(wbr); -+ -+ if (skip) -+ continue; -+ -+ hdir = au_hi(dir, bindex); -+ au_hn_imtx_lock_nested(hdir, AuLsc_I_PARENT); -+ if (wbr) -+ wbr_wh_write_lock(wbr); -+ err = au_wh_init(au_h_dptr(root, bindex), br, sb); -+ if (wbr) -+ wbr_wh_write_unlock(wbr); -+ au_hn_imtx_unlock(hdir); -+ -+ if (!err && do_free) { -+ kfree(wbr); -+ br->br_wbr = NULL; -+ } -+ } -+ -+ return err; -+} -+ -+int au_opts_mount(struct super_block *sb, struct au_opts *opts) -+{ -+ int err; -+ unsigned int tmp; -+ aufs_bindex_t bindex, bend; -+ struct au_opt *opt; -+ struct au_opt_xino *opt_xino, xino; -+ struct au_sbinfo *sbinfo; -+ struct au_branch *br; -+ -+ SiMustWriteLock(sb); -+ -+ err = 0; -+ opt_xino = NULL; -+ opt = opts->opt; -+ while (err >= 0 && opt->type != Opt_tail) -+ err = au_opt_simple(sb, opt++, opts); -+ if (err > 0) -+ err = 0; -+ else if (unlikely(err < 0)) -+ goto out; -+ -+ /* disable xino and udba temporary */ -+ sbinfo = au_sbi(sb); -+ tmp = sbinfo->si_mntflags; -+ au_opt_clr(sbinfo->si_mntflags, XINO); -+ au_opt_set_udba(sbinfo->si_mntflags, UDBA_REVAL); -+ -+ opt = opts->opt; -+ while (err >= 0 && opt->type != Opt_tail) -+ err = au_opt_br(sb, opt++, opts); -+ if (err > 0) -+ err = 0; -+ else if (unlikely(err < 0)) -+ goto out; -+ -+ bend = au_sbend(sb); -+ if (unlikely(bend < 0)) { -+ err = -EINVAL; -+ pr_err("no branches\n"); -+ goto out; -+ } -+ -+ if (au_opt_test(tmp, XINO)) -+ au_opt_set(sbinfo->si_mntflags, XINO); -+ opt = opts->opt; -+ while (!err && opt->type != Opt_tail) -+ err = au_opt_xino(sb, opt++, &opt_xino, opts); -+ if (unlikely(err)) -+ goto out; -+ -+ err = au_opts_verify(sb, sb->s_flags, tmp); -+ if (unlikely(err)) -+ goto out; -+ -+ /* restore xino */ -+ if (au_opt_test(tmp, XINO) && !opt_xino) { -+ xino.file = au_xino_def(sb); -+ err = PTR_ERR(xino.file); -+ if (IS_ERR(xino.file)) -+ goto out; -+ -+ err = au_xino_set(sb, &xino, /*remount*/0); -+ fput(xino.file); -+ if (unlikely(err)) -+ goto out; -+ } -+ -+ /* restore udba */ -+ tmp &= AuOptMask_UDBA; -+ sbinfo->si_mntflags &= ~AuOptMask_UDBA; -+ sbinfo->si_mntflags |= tmp; -+ bend = au_sbend(sb); -+ for (bindex = 0; bindex <= bend; bindex++) { -+ br = au_sbr(sb, bindex); -+ err = au_hnotify_reset_br(tmp, br, br->br_perm); -+ if (unlikely(err)) -+ AuIOErr("hnotify failed on br %d, %d, ignored\n", -+ bindex, err); -+ /* go on even if err */ -+ } -+ if (au_opt_test(tmp, UDBA_HNOTIFY)) { -+ struct inode *dir = sb->s_root->d_inode; -+ au_hn_reset(dir, au_hi_flags(dir, /*isdir*/1) & ~AuHi_XINO); -+ } -+ -+out: -+ return err; -+} -+ -+int au_opts_remount(struct super_block *sb, struct au_opts *opts) -+{ -+ int err, rerr; -+ struct inode *dir; -+ struct au_opt_xino *opt_xino; -+ struct au_opt *opt; -+ struct au_sbinfo *sbinfo; -+ -+ SiMustWriteLock(sb); -+ -+ dir = sb->s_root->d_inode; -+ sbinfo = au_sbi(sb); -+ err = 0; -+ opt_xino = NULL; -+ opt = opts->opt; -+ while (err >= 0 && opt->type != Opt_tail) { -+ err = au_opt_simple(sb, opt, opts); -+ if (!err) -+ err = au_opt_br(sb, opt, opts); -+ if (!err) -+ err = au_opt_xino(sb, opt, &opt_xino, opts); -+ opt++; -+ } -+ if (err > 0) -+ err = 0; -+ AuTraceErr(err); -+ /* go on even err */ -+ -+ rerr = au_opts_verify(sb, opts->sb_flags, /*pending*/0); -+ if (unlikely(rerr && !err)) -+ err = rerr; -+ -+ if (au_ftest_opts(opts->flags, TRUNC_XIB)) { -+ rerr = au_xib_trunc(sb); -+ if (unlikely(rerr && !err)) -+ err = rerr; -+ } -+ -+ /* will be handled by the caller */ -+ if (!au_ftest_opts(opts->flags, REFRESH) -+ && (opts->given_udba || au_opt_test(sbinfo->si_mntflags, XINO))) -+ au_fset_opts(opts->flags, REFRESH); -+ -+ AuDbg("status 0x%x\n", opts->flags); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+unsigned int au_opt_udba(struct super_block *sb) -+{ -+ return au_mntflags(sb) & AuOptMask_UDBA; -+} -diff -Nur linux-2.6.37.orig/fs/aufs/opts.h linux-2.6.37/fs/aufs/opts.h ---- linux-2.6.37.orig/fs/aufs/opts.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/opts.h 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,210 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * mount options/flags -+ */ -+ -+#ifndef __AUFS_OPTS_H__ -+#define __AUFS_OPTS_H__ -+ -+#ifdef __KERNEL__ -+ -+#include -+#include -+ -+struct file; -+struct super_block; -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* mount flags */ -+#define AuOpt_XINO 1 /* external inode number bitmap -+ and translation table */ -+#define AuOpt_TRUNC_XINO (1 << 1) /* truncate xino files */ -+#define AuOpt_UDBA_NONE (1 << 2) /* users direct branch access */ -+#define AuOpt_UDBA_REVAL (1 << 3) -+#define AuOpt_UDBA_HNOTIFY (1 << 4) -+#define AuOpt_SHWH (1 << 5) /* show whiteout */ -+#define AuOpt_PLINK (1 << 6) /* pseudo-link */ -+#define AuOpt_DIRPERM1 (1 << 7) /* unimplemented */ -+#define AuOpt_REFROF (1 << 8) /* unimplemented */ -+#define AuOpt_ALWAYS_DIROPQ (1 << 9) /* policy to creating diropq */ -+#define AuOpt_SUM (1 << 10) /* summation for statfs(2) */ -+#define AuOpt_SUM_W (1 << 11) /* unimplemented */ -+#define AuOpt_WARN_PERM (1 << 12) /* warn when add-branch */ -+#define AuOpt_VERBOSE (1 << 13) /* busy inode when del-branch */ -+#define AuOpt_DIO (1 << 14) /* direct io */ -+ -+#ifndef CONFIG_AUFS_HNOTIFY -+#undef AuOpt_UDBA_HNOTIFY -+#define AuOpt_UDBA_HNOTIFY 0 -+#endif -+#ifndef CONFIG_AUFS_SHWH -+#undef AuOpt_SHWH -+#define AuOpt_SHWH 0 -+#endif -+ -+#define AuOpt_Def (AuOpt_XINO \ -+ | AuOpt_UDBA_REVAL \ -+ | AuOpt_PLINK \ -+ /* | AuOpt_DIRPERM1 */ \ -+ | AuOpt_WARN_PERM) -+#define AuOptMask_UDBA (AuOpt_UDBA_NONE \ -+ | AuOpt_UDBA_REVAL \ -+ | AuOpt_UDBA_HNOTIFY) -+ -+#define au_opt_test(flags, name) (flags & AuOpt_##name) -+#define au_opt_set(flags, name) do { \ -+ BUILD_BUG_ON(AuOpt_##name & AuOptMask_UDBA); \ -+ ((flags) |= AuOpt_##name); \ -+} while (0) -+#define au_opt_set_udba(flags, name) do { \ -+ (flags) &= ~AuOptMask_UDBA; \ -+ ((flags) |= AuOpt_##name); \ -+} while (0) -+#define au_opt_clr(flags, name) do { \ -+ ((flags) &= ~AuOpt_##name); \ -+} while (0) -+ -+static inline unsigned int au_opts_plink(unsigned int mntflags) -+{ -+#ifdef CONFIG_PROC_FS -+ return mntflags; -+#else -+ return mntflags & ~AuOpt_PLINK; -+#endif -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* policies to select one among multiple writable branches */ -+enum { -+ AuWbrCreate_TDP, /* top down parent */ -+ AuWbrCreate_RR, /* round robin */ -+ AuWbrCreate_MFS, /* most free space */ -+ AuWbrCreate_MFSV, /* mfs with seconds */ -+ AuWbrCreate_MFSRR, /* mfs then rr */ -+ AuWbrCreate_MFSRRV, /* mfs then rr with seconds */ -+ AuWbrCreate_PMFS, /* parent and mfs */ -+ AuWbrCreate_PMFSV, /* parent and mfs with seconds */ -+ -+ AuWbrCreate_Def = AuWbrCreate_TDP -+}; -+ -+enum { -+ AuWbrCopyup_TDP, /* top down parent */ -+ AuWbrCopyup_BUP, /* bottom up parent */ -+ AuWbrCopyup_BU, /* bottom up */ -+ -+ AuWbrCopyup_Def = AuWbrCopyup_TDP -+}; -+ -+/* ---------------------------------------------------------------------- */ -+ -+struct au_opt_add { -+ aufs_bindex_t bindex; -+ char *pathname; -+ int perm; -+ struct path path; -+}; -+ -+struct au_opt_del { -+ char *pathname; -+ struct path h_path; -+}; -+ -+struct au_opt_mod { -+ char *path; -+ int perm; -+ struct dentry *h_root; -+}; -+ -+struct au_opt_xino { -+ char *path; -+ struct file *file; -+}; -+ -+struct au_opt_xino_itrunc { -+ aufs_bindex_t bindex; -+}; -+ -+struct au_opt_wbr_create { -+ int wbr_create; -+ int mfs_second; -+ unsigned long long mfsrr_watermark; -+}; -+ -+struct au_opt { -+ int type; -+ union { -+ struct au_opt_xino xino; -+ struct au_opt_xino_itrunc xino_itrunc; -+ struct au_opt_add add; -+ struct au_opt_del del; -+ struct au_opt_mod mod; -+ int dirwh; -+ int rdcache; -+ unsigned int rdblk; -+ unsigned int rdhash; -+ int udba; -+ struct au_opt_wbr_create wbr_create; -+ int wbr_copyup; -+ }; -+}; -+ -+/* opts flags */ -+#define AuOpts_REMOUNT 1 -+#define AuOpts_REFRESH (1 << 1) -+#define AuOpts_TRUNC_XIB (1 << 2) -+#define AuOpts_REFRESH_DYAOP (1 << 3) -+#define au_ftest_opts(flags, name) ((flags) & AuOpts_##name) -+#define au_fset_opts(flags, name) \ -+ do { (flags) |= AuOpts_##name; } while (0) -+#define au_fclr_opts(flags, name) \ -+ do { (flags) &= ~AuOpts_##name; } while (0) -+ -+struct au_opts { -+ struct au_opt *opt; -+ int max_opt; -+ -+ unsigned int given_udba; -+ unsigned int flags; -+ unsigned long sb_flags; -+}; -+ -+/* ---------------------------------------------------------------------- */ -+ -+const char *au_optstr_br_perm(int brperm); -+const char *au_optstr_udba(int udba); -+const char *au_optstr_wbr_copyup(int wbr_copyup); -+const char *au_optstr_wbr_create(int wbr_create); -+ -+void au_opts_free(struct au_opts *opts); -+int au_opts_parse(struct super_block *sb, char *str, struct au_opts *opts); -+int au_opts_verify(struct super_block *sb, unsigned long sb_flags, -+ unsigned int pending); -+int au_opts_mount(struct super_block *sb, struct au_opts *opts); -+int au_opts_remount(struct super_block *sb, struct au_opts *opts); -+ -+unsigned int au_opt_udba(struct super_block *sb); -+ -+/* ---------------------------------------------------------------------- */ -+ -+#endif /* __KERNEL__ */ -+#endif /* __AUFS_OPTS_H__ */ -diff -Nur linux-2.6.37.orig/fs/aufs/plink.c linux-2.6.37/fs/aufs/plink.c ---- linux-2.6.37.orig/fs/aufs/plink.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/plink.c 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,515 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * pseudo-link -+ */ -+ -+#include "aufs.h" -+ -+/* -+ * the pseudo-link maintenance mode. -+ * during a user process maintains the pseudo-links, -+ * prohibit adding a new plink and branch manipulation. -+ * -+ * Flags -+ * NOPLM: -+ * For entry functions which will handle plink, and i_mutex is already held -+ * in VFS. -+ * They cannot wait and should return an error at once. -+ * Callers has to check the error. -+ * NOPLMW: -+ * For entry functions which will handle plink, but i_mutex is not held -+ * in VFS. -+ * They can wait the plink maintenance mode to finish. -+ * -+ * They behave like F_SETLK and F_SETLKW. -+ * If the caller never handle plink, then both flags are unnecessary. -+ */ -+ -+int au_plink_maint(struct super_block *sb, int flags) -+{ -+ int err; -+ pid_t pid, ppid; -+ struct au_sbinfo *sbi; -+ -+ SiMustAnyLock(sb); -+ -+ err = 0; -+ if (!au_opt_test(au_mntflags(sb), PLINK)) -+ goto out; -+ -+ sbi = au_sbi(sb); -+ pid = sbi->si_plink_maint_pid; -+ if (!pid || pid == current->pid) -+ goto out; -+ -+ /* todo: it highly depends upon /sbin/mount.aufs */ -+ rcu_read_lock(); -+ ppid = task_pid_vnr(rcu_dereference(current->real_parent)); -+ rcu_read_unlock(); -+ if (pid == ppid) -+ goto out; -+ -+ if (au_ftest_lock(flags, NOPLMW)) { -+ /* if there is no i_mutex lock in VFS, we don't need to wait */ -+ /* AuDebugOn(!lockdep_depth(current)); */ -+ while (sbi->si_plink_maint_pid) { -+ si_read_unlock(sb); -+ /* gave up wake_up_bit() */ -+ wait_event(sbi->si_plink_wq, !sbi->si_plink_maint_pid); -+ -+ if (au_ftest_lock(flags, FLUSH)) -+ au_nwt_flush(&sbi->si_nowait); -+ si_noflush_read_lock(sb); -+ } -+ } else if (au_ftest_lock(flags, NOPLM)) { -+ AuDbg("ppid %d, pid %d\n", ppid, pid); -+ err = -EAGAIN; -+ } -+ -+out: -+ return err; -+} -+ -+void au_plink_maint_leave(struct au_sbinfo *sbinfo) -+{ -+ spin_lock(&sbinfo->si_plink_maint_lock); -+ sbinfo->si_plink_maint_pid = 0; -+ spin_unlock(&sbinfo->si_plink_maint_lock); -+ wake_up_all(&sbinfo->si_plink_wq); -+} -+ -+int au_plink_maint_enter(struct super_block *sb) -+{ -+ int err; -+ struct au_sbinfo *sbinfo; -+ -+ err = 0; -+ sbinfo = au_sbi(sb); -+ /* make sure i am the only one in this fs */ -+ si_write_lock(sb, AuLock_FLUSH); -+ if (au_opt_test(au_mntflags(sb), PLINK)) { -+ spin_lock(&sbinfo->si_plink_maint_lock); -+ if (!sbinfo->si_plink_maint_pid) -+ sbinfo->si_plink_maint_pid = current->pid; -+ else -+ err = -EBUSY; -+ spin_unlock(&sbinfo->si_plink_maint_lock); -+ } -+ si_write_unlock(sb); -+ -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+struct pseudo_link { -+ union { -+ struct list_head list; -+ struct rcu_head rcu; -+ }; -+ struct inode *inode; -+}; -+ -+#ifdef CONFIG_AUFS_DEBUG -+void au_plink_list(struct super_block *sb) -+{ -+ struct au_sbinfo *sbinfo; -+ struct list_head *plink_list; -+ struct pseudo_link *plink; -+ -+ SiMustAnyLock(sb); -+ -+ sbinfo = au_sbi(sb); -+ AuDebugOn(!au_opt_test(au_mntflags(sb), PLINK)); -+ AuDebugOn(au_plink_maint(sb, AuLock_NOPLM)); -+ -+ plink_list = &sbinfo->si_plink.head; -+ rcu_read_lock(); -+ list_for_each_entry_rcu(plink, plink_list, list) -+ AuDbg("%lu\n", plink->inode->i_ino); -+ rcu_read_unlock(); -+} -+#endif -+ -+/* is the inode pseudo-linked? */ -+int au_plink_test(struct inode *inode) -+{ -+ int found; -+ struct au_sbinfo *sbinfo; -+ struct list_head *plink_list; -+ struct pseudo_link *plink; -+ -+ sbinfo = au_sbi(inode->i_sb); -+ AuRwMustAnyLock(&sbinfo->si_rwsem); -+ AuDebugOn(!au_opt_test(au_mntflags(inode->i_sb), PLINK)); -+ AuDebugOn(au_plink_maint(inode->i_sb, AuLock_NOPLM)); -+ -+ found = 0; -+ plink_list = &sbinfo->si_plink.head; -+ rcu_read_lock(); -+ list_for_each_entry_rcu(plink, plink_list, list) -+ if (plink->inode == inode) { -+ found = 1; -+ break; -+ } -+ rcu_read_unlock(); -+ return found; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * generate a name for plink. -+ * the file will be stored under AUFS_WH_PLINKDIR. -+ */ -+/* 20 is max digits length of ulong 64 */ -+#define PLINK_NAME_LEN ((20 + 1) * 2) -+ -+static int plink_name(char *name, int len, struct inode *inode, -+ aufs_bindex_t bindex) -+{ -+ int rlen; -+ struct inode *h_inode; -+ -+ h_inode = au_h_iptr(inode, bindex); -+ rlen = snprintf(name, len, "%lu.%lu", inode->i_ino, h_inode->i_ino); -+ return rlen; -+} -+ -+struct au_do_plink_lkup_args { -+ struct dentry **errp; -+ struct qstr *tgtname; -+ struct dentry *h_parent; -+ struct au_branch *br; -+}; -+ -+static struct dentry *au_do_plink_lkup(struct qstr *tgtname, -+ struct dentry *h_parent, -+ struct au_branch *br) -+{ -+ struct dentry *h_dentry; -+ struct mutex *h_mtx; -+ -+ h_mtx = &h_parent->d_inode->i_mutex; -+ mutex_lock_nested(h_mtx, AuLsc_I_CHILD2); -+ h_dentry = au_lkup_one(tgtname, h_parent, br, /*nd*/NULL); -+ mutex_unlock(h_mtx); -+ return h_dentry; -+} -+ -+static void au_call_do_plink_lkup(void *args) -+{ -+ struct au_do_plink_lkup_args *a = args; -+ *a->errp = au_do_plink_lkup(a->tgtname, a->h_parent, a->br); -+} -+ -+/* lookup the plink-ed @inode under the branch at @bindex */ -+struct dentry *au_plink_lkup(struct inode *inode, aufs_bindex_t bindex) -+{ -+ struct dentry *h_dentry, *h_parent; -+ struct au_branch *br; -+ struct inode *h_dir; -+ int wkq_err; -+ char a[PLINK_NAME_LEN]; -+ struct qstr tgtname = { -+ .name = a -+ }; -+ -+ AuDebugOn(au_plink_maint(inode->i_sb, AuLock_NOPLM)); -+ -+ br = au_sbr(inode->i_sb, bindex); -+ h_parent = br->br_wbr->wbr_plink; -+ h_dir = h_parent->d_inode; -+ tgtname.len = plink_name(a, sizeof(a), inode, bindex); -+ -+ if (current_fsuid()) { -+ struct au_do_plink_lkup_args args = { -+ .errp = &h_dentry, -+ .tgtname = &tgtname, -+ .h_parent = h_parent, -+ .br = br -+ }; -+ -+ wkq_err = au_wkq_wait(au_call_do_plink_lkup, &args); -+ if (unlikely(wkq_err)) -+ h_dentry = ERR_PTR(wkq_err); -+ } else -+ h_dentry = au_do_plink_lkup(&tgtname, h_parent, br); -+ -+ return h_dentry; -+} -+ -+/* create a pseudo-link */ -+static int do_whplink(struct qstr *tgt, struct dentry *h_parent, -+ struct dentry *h_dentry, struct au_branch *br) -+{ -+ int err; -+ struct path h_path = { -+ .mnt = br->br_mnt -+ }; -+ struct inode *h_dir; -+ -+ h_dir = h_parent->d_inode; -+ mutex_lock_nested(&h_dir->i_mutex, AuLsc_I_CHILD2); -+again: -+ h_path.dentry = au_lkup_one(tgt, h_parent, br, /*nd*/NULL); -+ err = PTR_ERR(h_path.dentry); -+ if (IS_ERR(h_path.dentry)) -+ goto out; -+ -+ err = 0; -+ /* wh.plink dir is not monitored */ -+ /* todo: is it really safe? */ -+ if (h_path.dentry->d_inode -+ && h_path.dentry->d_inode != h_dentry->d_inode) { -+ err = vfsub_unlink(h_dir, &h_path, /*force*/0); -+ dput(h_path.dentry); -+ h_path.dentry = NULL; -+ if (!err) -+ goto again; -+ } -+ if (!err && !h_path.dentry->d_inode) -+ err = vfsub_link(h_dentry, h_dir, &h_path); -+ dput(h_path.dentry); -+ -+out: -+ mutex_unlock(&h_dir->i_mutex); -+ return err; -+} -+ -+struct do_whplink_args { -+ int *errp; -+ struct qstr *tgt; -+ struct dentry *h_parent; -+ struct dentry *h_dentry; -+ struct au_branch *br; -+}; -+ -+static void call_do_whplink(void *args) -+{ -+ struct do_whplink_args *a = args; -+ *a->errp = do_whplink(a->tgt, a->h_parent, a->h_dentry, a->br); -+} -+ -+static int whplink(struct dentry *h_dentry, struct inode *inode, -+ aufs_bindex_t bindex, struct au_branch *br) -+{ -+ int err, wkq_err; -+ struct au_wbr *wbr; -+ struct dentry *h_parent; -+ struct inode *h_dir; -+ char a[PLINK_NAME_LEN]; -+ struct qstr tgtname = { -+ .name = a -+ }; -+ -+ wbr = au_sbr(inode->i_sb, bindex)->br_wbr; -+ h_parent = wbr->wbr_plink; -+ h_dir = h_parent->d_inode; -+ tgtname.len = plink_name(a, sizeof(a), inode, bindex); -+ -+ /* always superio. */ -+ if (current_fsuid()) { -+ struct do_whplink_args args = { -+ .errp = &err, -+ .tgt = &tgtname, -+ .h_parent = h_parent, -+ .h_dentry = h_dentry, -+ .br = br -+ }; -+ wkq_err = au_wkq_wait(call_do_whplink, &args); -+ if (unlikely(wkq_err)) -+ err = wkq_err; -+ } else -+ err = do_whplink(&tgtname, h_parent, h_dentry, br); -+ -+ return err; -+} -+ -+/* free a single plink */ -+static void do_put_plink(struct pseudo_link *plink, int do_del) -+{ -+ if (do_del) -+ list_del(&plink->list); -+ iput(plink->inode); -+ kfree(plink); -+} -+ -+static void do_put_plink_rcu(struct rcu_head *rcu) -+{ -+ struct pseudo_link *plink; -+ -+ plink = container_of(rcu, struct pseudo_link, rcu); -+ iput(plink->inode); -+ kfree(plink); -+} -+ -+/* -+ * create a new pseudo-link for @h_dentry on @bindex. -+ * the linked inode is held in aufs @inode. -+ */ -+void au_plink_append(struct inode *inode, aufs_bindex_t bindex, -+ struct dentry *h_dentry) -+{ -+ struct super_block *sb; -+ struct au_sbinfo *sbinfo; -+ struct list_head *plink_list; -+ struct pseudo_link *plink, *tmp; -+ int found, err, cnt; -+ -+ sb = inode->i_sb; -+ sbinfo = au_sbi(sb); -+ AuDebugOn(!au_opt_test(au_mntflags(sb), PLINK)); -+ AuDebugOn(au_plink_maint(sb, AuLock_NOPLM)); -+ -+ cnt = 0; -+ found = 0; -+ plink_list = &sbinfo->si_plink.head; -+ rcu_read_lock(); -+ list_for_each_entry_rcu(plink, plink_list, list) { -+ cnt++; -+ if (plink->inode == inode) { -+ found = 1; -+ break; -+ } -+ } -+ rcu_read_unlock(); -+ if (found) -+ return; -+ -+ tmp = kmalloc(sizeof(*plink), GFP_NOFS); -+ if (tmp) -+ tmp->inode = au_igrab(inode); -+ else { -+ err = -ENOMEM; -+ goto out; -+ } -+ -+ spin_lock(&sbinfo->si_plink.spin); -+ list_for_each_entry(plink, plink_list, list) { -+ if (plink->inode == inode) { -+ found = 1; -+ break; -+ } -+ } -+ if (!found) -+ list_add_rcu(&tmp->list, plink_list); -+ spin_unlock(&sbinfo->si_plink.spin); -+ if (!found) { -+ cnt++; -+ WARN_ONCE(cnt > AUFS_PLINK_WARN, -+ "unexpectedly many pseudo links, %d\n", cnt); -+ err = whplink(h_dentry, inode, bindex, au_sbr(sb, bindex)); -+ } else { -+ do_put_plink(tmp, 0); -+ return; -+ } -+ -+out: -+ if (unlikely(err)) { -+ pr_warning("err %d, damaged pseudo link.\n", err); -+ if (tmp) { -+ au_spl_del_rcu(&tmp->list, &sbinfo->si_plink); -+ call_rcu(&tmp->rcu, do_put_plink_rcu); -+ } -+ } -+} -+ -+/* free all plinks */ -+void au_plink_put(struct super_block *sb, int verbose) -+{ -+ struct au_sbinfo *sbinfo; -+ struct list_head *plink_list; -+ struct pseudo_link *plink, *tmp; -+ -+ SiMustWriteLock(sb); -+ -+ sbinfo = au_sbi(sb); -+ AuDebugOn(!au_opt_test(au_mntflags(sb), PLINK)); -+ AuDebugOn(au_plink_maint(sb, AuLock_NOPLM)); -+ -+ plink_list = &sbinfo->si_plink.head; -+ /* no spin_lock since sbinfo is write-locked */ -+ WARN(verbose && !list_empty(plink_list), "pseudo-link is not flushed"); -+ list_for_each_entry_safe(plink, tmp, plink_list, list) -+ do_put_plink(plink, 0); -+ INIT_LIST_HEAD(plink_list); -+} -+ -+void au_plink_clean(struct super_block *sb, int verbose) -+{ -+ struct dentry *root; -+ -+ root = sb->s_root; -+ aufs_write_lock(root); -+ if (au_opt_test(au_mntflags(sb), PLINK)) -+ au_plink_put(sb, verbose); -+ aufs_write_unlock(root); -+} -+ -+/* free the plinks on a branch specified by @br_id */ -+void au_plink_half_refresh(struct super_block *sb, aufs_bindex_t br_id) -+{ -+ struct au_sbinfo *sbinfo; -+ struct list_head *plink_list; -+ struct pseudo_link *plink, *tmp; -+ struct inode *inode; -+ aufs_bindex_t bstart, bend, bindex; -+ unsigned char do_put; -+ -+ SiMustWriteLock(sb); -+ -+ sbinfo = au_sbi(sb); -+ AuDebugOn(!au_opt_test(au_mntflags(sb), PLINK)); -+ AuDebugOn(au_plink_maint(sb, AuLock_NOPLM)); -+ -+ plink_list = &sbinfo->si_plink.head; -+ /* no spin_lock since sbinfo is write-locked */ -+ list_for_each_entry_safe(plink, tmp, plink_list, list) { -+ do_put = 0; -+ inode = au_igrab(plink->inode); -+ ii_write_lock_child(inode); -+ bstart = au_ibstart(inode); -+ bend = au_ibend(inode); -+ if (bstart >= 0) { -+ for (bindex = bstart; bindex <= bend; bindex++) { -+ if (!au_h_iptr(inode, bindex) -+ || au_ii_br_id(inode, bindex) != br_id) -+ continue; -+ au_set_h_iptr(inode, bindex, NULL, 0); -+ do_put = 1; -+ break; -+ } -+ } else -+ do_put_plink(plink, 1); -+ -+ if (do_put) { -+ for (bindex = bstart; bindex <= bend; bindex++) -+ if (au_h_iptr(inode, bindex)) { -+ do_put = 0; -+ break; -+ } -+ if (do_put) -+ do_put_plink(plink, 1); -+ } -+ ii_write_unlock(inode); -+ iput(inode); -+ } -+} -diff -Nur linux-2.6.37.orig/fs/aufs/poll.c linux-2.6.37/fs/aufs/poll.c ---- linux-2.6.37.orig/fs/aufs/poll.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/poll.c 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,56 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * poll operation -+ * There is only one filesystem which implements ->poll operation, currently. -+ */ -+ -+#include "aufs.h" -+ -+unsigned int aufs_poll(struct file *file, poll_table *wait) -+{ -+ unsigned int mask; -+ int err; -+ struct file *h_file; -+ struct dentry *dentry; -+ struct super_block *sb; -+ -+ /* We should pretend an error happened. */ -+ mask = POLLERR /* | POLLIN | POLLOUT */; -+ dentry = file->f_dentry; -+ sb = dentry->d_sb; -+ si_read_lock(sb, AuLock_FLUSH | AuLock_NOPLMW); -+ err = au_reval_and_lock_fdi(file, au_reopen_nondir, /*wlock*/0); -+ if (unlikely(err)) -+ goto out; -+ -+ /* it is not an error if h_file has no operation */ -+ mask = DEFAULT_POLLMASK; -+ h_file = au_hf_top(file); -+ if (h_file->f_op && h_file->f_op->poll) -+ mask = h_file->f_op->poll(h_file, wait); -+ -+ di_read_unlock(dentry, AuLock_IR); -+ fi_read_unlock(file); -+ -+out: -+ si_read_unlock(sb); -+ AuTraceErr((int)mask); -+ return mask; -+} -diff -Nur linux-2.6.37.orig/fs/aufs/procfs.c linux-2.6.37/fs/aufs/procfs.c ---- linux-2.6.37.orig/fs/aufs/procfs.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/procfs.c 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,169 @@ -+/* -+ * Copyright (C) 2010-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * procfs interfaces -+ */ -+ -+#include -+#include "aufs.h" -+ -+static int au_procfs_plm_release(struct inode *inode, struct file *file) -+{ -+ struct au_sbinfo *sbinfo; -+ -+ sbinfo = file->private_data; -+ if (sbinfo) { -+ au_plink_maint_leave(sbinfo); -+ kobject_put(&sbinfo->si_kobj); -+ } -+ -+ return 0; -+} -+ -+static void au_procfs_plm_write_clean(struct file *file) -+{ -+ struct au_sbinfo *sbinfo; -+ -+ sbinfo = file->private_data; -+ if (sbinfo) -+ au_plink_clean(sbinfo->si_sb, /*verbose*/0); -+} -+ -+static int au_procfs_plm_write_si(struct file *file, unsigned long id) -+{ -+ int err; -+ struct super_block *sb; -+ struct au_sbinfo *sbinfo; -+ -+ err = -EBUSY; -+ if (unlikely(file->private_data)) -+ goto out; -+ -+ sb = NULL; -+ spin_lock(&au_sbilist.spin); -+ list_for_each_entry(sbinfo, &au_sbilist.head, si_list) -+ if (id == sysaufs_si_id(sbinfo)) { -+ kobject_get(&sbinfo->si_kobj); -+ sb = sbinfo->si_sb; -+ break; -+ } -+ spin_unlock(&au_sbilist.spin); -+ -+ err = -EINVAL; -+ if (unlikely(!sb)) -+ goto out; -+ -+ err = au_plink_maint_enter(sb); -+ if (!err) -+ /* keep kobject_get() */ -+ file->private_data = sbinfo; -+ else -+ kobject_put(&sbinfo->si_kobj); -+out: -+ return err; -+} -+ -+/* -+ * Accept a valid "si=xxxx" only. -+ * Once it is accepted successfully, accept "clean" too. -+ */ -+static ssize_t au_procfs_plm_write(struct file *file, const char __user *ubuf, -+ size_t count, loff_t *ppos) -+{ -+ ssize_t err; -+ unsigned long id; -+ /* last newline is allowed */ -+ char buf[3 + sizeof(unsigned long) * 2 + 1]; -+ -+ err = -EACCES; -+ if (unlikely(!capable(CAP_SYS_ADMIN))) -+ goto out; -+ -+ err = -EINVAL; -+ if (unlikely(count > sizeof(buf))) -+ goto out; -+ -+ err = copy_from_user(buf, ubuf, count); -+ if (unlikely(err)) { -+ err = -EFAULT; -+ goto out; -+ } -+ buf[count] = 0; -+ -+ err = -EINVAL; -+ if (!strcmp("clean", buf)) { -+ au_procfs_plm_write_clean(file); -+ goto out_success; -+ } else if (unlikely(strncmp("si=", buf, 3))) -+ goto out; -+ -+ err = strict_strtoul(buf + 3, 16, &id); -+ if (unlikely(err)) -+ goto out; -+ -+ err = au_procfs_plm_write_si(file, id); -+ if (unlikely(err)) -+ goto out; -+ -+out_success: -+ err = count; /* success */ -+out: -+ return err; -+} -+ -+static const struct file_operations au_procfs_plm_fop = { -+ .write = au_procfs_plm_write, -+ .release = au_procfs_plm_release, -+ .owner = THIS_MODULE -+}; -+ -+/* ---------------------------------------------------------------------- */ -+ -+static struct proc_dir_entry *au_procfs_dir; -+ -+void au_procfs_fin(void) -+{ -+ remove_proc_entry(AUFS_PLINK_MAINT_NAME, au_procfs_dir); -+ remove_proc_entry(AUFS_PLINK_MAINT_DIR, NULL); -+} -+ -+int __init au_procfs_init(void) -+{ -+ int err; -+ struct proc_dir_entry *entry; -+ -+ err = -ENOMEM; -+ au_procfs_dir = proc_mkdir(AUFS_PLINK_MAINT_DIR, NULL); -+ if (unlikely(!au_procfs_dir)) -+ goto out; -+ -+ entry = proc_create(AUFS_PLINK_MAINT_NAME, S_IFREG | S_IWUSR, -+ au_procfs_dir, &au_procfs_plm_fop); -+ if (unlikely(!entry)) -+ goto out_dir; -+ -+ err = 0; -+ goto out; /* success */ -+ -+ -+out_dir: -+ remove_proc_entry(AUFS_PLINK_MAINT_DIR, NULL); -+out: -+ return err; -+} -diff -Nur linux-2.6.37.orig/fs/aufs/rdu.c linux-2.6.37/fs/aufs/rdu.c ---- linux-2.6.37.orig/fs/aufs/rdu.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/rdu.c 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,383 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * readdir in userspace. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include "aufs.h" -+ -+/* bits for struct aufs_rdu.flags */ -+#define AuRdu_CALLED 1 -+#define AuRdu_CONT (1 << 1) -+#define AuRdu_FULL (1 << 2) -+#define au_ftest_rdu(flags, name) ((flags) & AuRdu_##name) -+#define au_fset_rdu(flags, name) \ -+ do { (flags) |= AuRdu_##name; } while (0) -+#define au_fclr_rdu(flags, name) \ -+ do { (flags) &= ~AuRdu_##name; } while (0) -+ -+struct au_rdu_arg { -+ struct aufs_rdu *rdu; -+ union au_rdu_ent_ul ent; -+ unsigned long end; -+ -+ struct super_block *sb; -+ int err; -+}; -+ -+static int au_rdu_fill(void *__arg, const char *name, int nlen, -+ loff_t offset, u64 h_ino, unsigned int d_type) -+{ -+ int err, len; -+ struct au_rdu_arg *arg = __arg; -+ struct aufs_rdu *rdu = arg->rdu; -+ struct au_rdu_ent ent; -+ -+ err = 0; -+ arg->err = 0; -+ au_fset_rdu(rdu->cookie.flags, CALLED); -+ len = au_rdu_len(nlen); -+ if (arg->ent.ul + len < arg->end) { -+ ent.ino = h_ino; -+ ent.bindex = rdu->cookie.bindex; -+ ent.type = d_type; -+ ent.nlen = nlen; -+ if (unlikely(nlen > AUFS_MAX_NAMELEN)) -+ ent.type = DT_UNKNOWN; -+ -+ err = -EFAULT; -+ if (copy_to_user(arg->ent.e, &ent, sizeof(ent))) -+ goto out; -+ if (copy_to_user(arg->ent.e->name, name, nlen)) -+ goto out; -+ /* the terminating NULL */ -+ if (__put_user(0, arg->ent.e->name + nlen)) -+ goto out; -+ err = 0; -+ /* AuDbg("%p, %.*s\n", arg->ent.p, nlen, name); */ -+ arg->ent.ul += len; -+ rdu->rent++; -+ } else { -+ err = -EFAULT; -+ au_fset_rdu(rdu->cookie.flags, FULL); -+ rdu->full = 1; -+ rdu->tail = arg->ent; -+ } -+ -+out: -+ /* AuTraceErr(err); */ -+ return err; -+} -+ -+static int au_rdu_do(struct file *h_file, struct au_rdu_arg *arg) -+{ -+ int err; -+ loff_t offset; -+ struct au_rdu_cookie *cookie = &arg->rdu->cookie; -+ -+ offset = vfsub_llseek(h_file, cookie->h_pos, SEEK_SET); -+ err = offset; -+ if (unlikely(offset != cookie->h_pos)) -+ goto out; -+ -+ err = 0; -+ do { -+ arg->err = 0; -+ au_fclr_rdu(cookie->flags, CALLED); -+ /* smp_mb(); */ -+ err = vfsub_readdir(h_file, au_rdu_fill, arg); -+ if (err >= 0) -+ err = arg->err; -+ } while (!err -+ && au_ftest_rdu(cookie->flags, CALLED) -+ && !au_ftest_rdu(cookie->flags, FULL)); -+ cookie->h_pos = h_file->f_pos; -+ -+out: -+ AuTraceErr(err); -+ return err; -+} -+ -+static int au_rdu(struct file *file, struct aufs_rdu *rdu) -+{ -+ int err; -+ aufs_bindex_t bend; -+ struct au_rdu_arg arg; -+ struct dentry *dentry; -+ struct inode *inode; -+ struct file *h_file; -+ struct au_rdu_cookie *cookie = &rdu->cookie; -+ -+ err = !access_ok(VERIFY_WRITE, rdu->ent.e, rdu->sz); -+ if (unlikely(err)) { -+ err = -EFAULT; -+ AuTraceErr(err); -+ goto out; -+ } -+ rdu->rent = 0; -+ rdu->tail = rdu->ent; -+ rdu->full = 0; -+ arg.rdu = rdu; -+ arg.ent = rdu->ent; -+ arg.end = arg.ent.ul; -+ arg.end += rdu->sz; -+ -+ err = -ENOTDIR; -+ if (unlikely(!file->f_op || !file->f_op->readdir)) -+ goto out; -+ -+ err = security_file_permission(file, MAY_READ); -+ AuTraceErr(err); -+ if (unlikely(err)) -+ goto out; -+ -+ dentry = file->f_dentry; -+ inode = dentry->d_inode; -+#if 1 -+ mutex_lock(&inode->i_mutex); -+#else -+ err = mutex_lock_killable(&inode->i_mutex); -+ AuTraceErr(err); -+ if (unlikely(err)) -+ goto out; -+#endif -+ -+ arg.sb = inode->i_sb; -+ err = si_read_lock(arg.sb, AuLock_FLUSH | AuLock_NOPLM); -+ if (unlikely(err)) -+ goto out_mtx; -+ err = au_alive_dir(dentry); -+ if (unlikely(err)) -+ goto out_si; -+ /* todo: reval? */ -+ fi_read_lock(file); -+ -+ err = -EAGAIN; -+ if (unlikely(au_ftest_rdu(cookie->flags, CONT) -+ && cookie->generation != au_figen(file))) -+ goto out_unlock; -+ -+ err = 0; -+ if (!rdu->blk) { -+ rdu->blk = au_sbi(arg.sb)->si_rdblk; -+ if (!rdu->blk) -+ rdu->blk = au_dir_size(file, /*dentry*/NULL); -+ } -+ bend = au_fbstart(file); -+ if (cookie->bindex < bend) -+ cookie->bindex = bend; -+ bend = au_fbend_dir(file); -+ /* AuDbg("b%d, b%d\n", cookie->bindex, bend); */ -+ for (; !err && cookie->bindex <= bend; -+ cookie->bindex++, cookie->h_pos = 0) { -+ h_file = au_hf_dir(file, cookie->bindex); -+ if (!h_file) -+ continue; -+ -+ au_fclr_rdu(cookie->flags, FULL); -+ err = au_rdu_do(h_file, &arg); -+ AuTraceErr(err); -+ if (unlikely(au_ftest_rdu(cookie->flags, FULL) || err)) -+ break; -+ } -+ AuDbg("rent %llu\n", rdu->rent); -+ -+ if (!err && !au_ftest_rdu(cookie->flags, CONT)) { -+ rdu->shwh = !!au_opt_test(au_sbi(arg.sb)->si_mntflags, SHWH); -+ au_fset_rdu(cookie->flags, CONT); -+ cookie->generation = au_figen(file); -+ } -+ -+ ii_read_lock_child(inode); -+ fsstack_copy_attr_atime(inode, au_h_iptr(inode, au_ibstart(inode))); -+ ii_read_unlock(inode); -+ -+out_unlock: -+ fi_read_unlock(file); -+out_si: -+ si_read_unlock(arg.sb); -+out_mtx: -+ mutex_unlock(&inode->i_mutex); -+out: -+ AuTraceErr(err); -+ return err; -+} -+ -+static int au_rdu_ino(struct file *file, struct aufs_rdu *rdu) -+{ -+ int err; -+ ino_t ino; -+ unsigned long long nent; -+ union au_rdu_ent_ul *u; -+ struct au_rdu_ent ent; -+ struct super_block *sb; -+ -+ err = 0; -+ nent = rdu->nent; -+ u = &rdu->ent; -+ sb = file->f_dentry->d_sb; -+ si_read_lock(sb, AuLock_FLUSH); -+ while (nent-- > 0) { -+ err = copy_from_user(&ent, u->e, sizeof(ent)); -+ if (!err) -+ err = !access_ok(VERIFY_WRITE, &u->e->ino, sizeof(ino)); -+ if (unlikely(err)) { -+ err = -EFAULT; -+ AuTraceErr(err); -+ break; -+ } -+ -+ /* AuDbg("b%d, i%llu\n", ent.bindex, ent.ino); */ -+ if (!ent.wh) -+ err = au_ino(sb, ent.bindex, ent.ino, ent.type, &ino); -+ else -+ err = au_wh_ino(sb, ent.bindex, ent.ino, ent.type, -+ &ino); -+ if (unlikely(err)) { -+ AuTraceErr(err); -+ break; -+ } -+ -+ err = __put_user(ino, &u->e->ino); -+ if (unlikely(err)) { -+ err = -EFAULT; -+ AuTraceErr(err); -+ break; -+ } -+ u->ul += au_rdu_len(ent.nlen); -+ } -+ si_read_unlock(sb); -+ -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int au_rdu_verify(struct aufs_rdu *rdu) -+{ -+ AuDbg("rdu{%llu, %p, %u | %u | %llu, %u, %u | " -+ "%llu, b%d, 0x%x, g%u}\n", -+ rdu->sz, rdu->ent.e, rdu->verify[AufsCtlRduV_SZ], -+ rdu->blk, -+ rdu->rent, rdu->shwh, rdu->full, -+ rdu->cookie.h_pos, rdu->cookie.bindex, rdu->cookie.flags, -+ rdu->cookie.generation); -+ -+ if (rdu->verify[AufsCtlRduV_SZ] == sizeof(*rdu)) -+ return 0; -+ -+ AuDbg("%u:%u\n", -+ rdu->verify[AufsCtlRduV_SZ], (unsigned int)sizeof(*rdu)); -+ return -EINVAL; -+} -+ -+long au_rdu_ioctl(struct file *file, unsigned int cmd, unsigned long arg) -+{ -+ long err, e; -+ struct aufs_rdu rdu; -+ void __user *p = (void __user *)arg; -+ -+ err = copy_from_user(&rdu, p, sizeof(rdu)); -+ if (unlikely(err)) { -+ err = -EFAULT; -+ AuTraceErr(err); -+ goto out; -+ } -+ err = au_rdu_verify(&rdu); -+ if (unlikely(err)) -+ goto out; -+ -+ switch (cmd) { -+ case AUFS_CTL_RDU: -+ err = au_rdu(file, &rdu); -+ if (unlikely(err)) -+ break; -+ -+ e = copy_to_user(p, &rdu, sizeof(rdu)); -+ if (unlikely(e)) { -+ err = -EFAULT; -+ AuTraceErr(err); -+ } -+ break; -+ case AUFS_CTL_RDU_INO: -+ err = au_rdu_ino(file, &rdu); -+ break; -+ -+ default: -+ /* err = -ENOTTY; */ -+ err = -EINVAL; -+ } -+ -+out: -+ AuTraceErr(err); -+ return err; -+} -+ -+#ifdef CONFIG_COMPAT -+long au_rdu_compat_ioctl(struct file *file, unsigned int cmd, unsigned long arg) -+{ -+ long err, e; -+ struct aufs_rdu rdu; -+ void __user *p = compat_ptr(arg); -+ -+ /* todo: get_user()? */ -+ err = copy_from_user(&rdu, p, sizeof(rdu)); -+ if (unlikely(err)) { -+ err = -EFAULT; -+ AuTraceErr(err); -+ goto out; -+ } -+ rdu.ent.e = compat_ptr(rdu.ent.ul); -+ err = au_rdu_verify(&rdu); -+ if (unlikely(err)) -+ goto out; -+ -+ switch (cmd) { -+ case AUFS_CTL_RDU: -+ err = au_rdu(file, &rdu); -+ if (unlikely(err)) -+ break; -+ -+ rdu.ent.ul = ptr_to_compat(rdu.ent.e); -+ rdu.tail.ul = ptr_to_compat(rdu.tail.e); -+ e = copy_to_user(p, &rdu, sizeof(rdu)); -+ if (unlikely(e)) { -+ err = -EFAULT; -+ AuTraceErr(err); -+ } -+ break; -+ case AUFS_CTL_RDU_INO: -+ err = au_rdu_ino(file, &rdu); -+ break; -+ -+ default: -+ /* err = -ENOTTY; */ -+ err = -EINVAL; -+ } -+ -+out: -+ AuTraceErr(err); -+ return err; -+} -+#endif -diff -Nur linux-2.6.37.orig/fs/aufs/rwsem.h linux-2.6.37/fs/aufs/rwsem.h ---- linux-2.6.37.orig/fs/aufs/rwsem.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/rwsem.h 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,189 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * simple read-write semaphore wrappers -+ */ -+ -+#ifndef __AUFS_RWSEM_H__ -+#define __AUFS_RWSEM_H__ -+ -+#ifdef __KERNEL__ -+ -+#include -+#include "debug.h" -+ -+struct au_rwsem { -+ struct rw_semaphore rwsem; -+#ifdef CONFIG_AUFS_DEBUG -+ /* just for debugging, not almighty counter */ -+ atomic_t rcnt, wcnt; -+#endif -+}; -+ -+#ifdef CONFIG_AUFS_DEBUG -+#define AuDbgCntInit(rw) do { \ -+ atomic_set(&(rw)->rcnt, 0); \ -+ atomic_set(&(rw)->wcnt, 0); \ -+ smp_mb(); /* atomic set */ \ -+} while (0) -+ -+#define AuDbgRcntInc(rw) atomic_inc(&(rw)->rcnt) -+#define AuDbgRcntDec(rw) WARN_ON(atomic_dec_return(&(rw)->rcnt) < 0) -+#define AuDbgWcntInc(rw) atomic_inc(&(rw)->wcnt) -+#define AuDbgWcntDec(rw) WARN_ON(atomic_dec_return(&(rw)->wcnt) < 0) -+#else -+#define AuDbgCntInit(rw) do {} while (0) -+#define AuDbgRcntInc(rw) do {} while (0) -+#define AuDbgRcntDec(rw) do {} while (0) -+#define AuDbgWcntInc(rw) do {} while (0) -+#define AuDbgWcntDec(rw) do {} while (0) -+#endif /* CONFIG_AUFS_DEBUG */ -+ -+/* to debug easier, do not make them inlined functions */ -+#define AuRwMustNoWaiters(rw) AuDebugOn(!list_empty(&(rw)->rwsem.wait_list)) -+/* rwsem_is_locked() is unusable */ -+#define AuRwMustReadLock(rw) AuDebugOn(atomic_read(&(rw)->rcnt) <= 0) -+#define AuRwMustWriteLock(rw) AuDebugOn(atomic_read(&(rw)->wcnt) <= 0) -+#define AuRwMustAnyLock(rw) AuDebugOn(atomic_read(&(rw)->rcnt) <= 0 \ -+ && atomic_read(&(rw)->wcnt) <= 0) -+#define AuRwDestroy(rw) AuDebugOn(atomic_read(&(rw)->rcnt) \ -+ || atomic_read(&(rw)->wcnt)) -+ -+#define au_rw_class(rw, key) lockdep_set_class(&(rw)->rwsem, key) -+ -+static inline void au_rw_init(struct au_rwsem *rw) -+{ -+ AuDbgCntInit(rw); -+ init_rwsem(&rw->rwsem); -+} -+ -+static inline void au_rw_init_wlock(struct au_rwsem *rw) -+{ -+ au_rw_init(rw); -+ down_write(&rw->rwsem); -+ AuDbgWcntInc(rw); -+} -+ -+static inline void au_rw_init_wlock_nested(struct au_rwsem *rw, -+ unsigned int lsc) -+{ -+ au_rw_init(rw); -+ down_write_nested(&rw->rwsem, lsc); -+ AuDbgWcntInc(rw); -+} -+ -+static inline void au_rw_read_lock(struct au_rwsem *rw) -+{ -+ down_read(&rw->rwsem); -+ AuDbgRcntInc(rw); -+} -+ -+static inline void au_rw_read_lock_nested(struct au_rwsem *rw, unsigned int lsc) -+{ -+ down_read_nested(&rw->rwsem, lsc); -+ AuDbgRcntInc(rw); -+} -+ -+static inline void au_rw_read_unlock(struct au_rwsem *rw) -+{ -+ AuRwMustReadLock(rw); -+ AuDbgRcntDec(rw); -+ up_read(&rw->rwsem); -+} -+ -+static inline void au_rw_dgrade_lock(struct au_rwsem *rw) -+{ -+ AuRwMustWriteLock(rw); -+ AuDbgRcntInc(rw); -+ AuDbgWcntDec(rw); -+ downgrade_write(&rw->rwsem); -+} -+ -+static inline void au_rw_write_lock(struct au_rwsem *rw) -+{ -+ down_write(&rw->rwsem); -+ AuDbgWcntInc(rw); -+} -+ -+static inline void au_rw_write_lock_nested(struct au_rwsem *rw, -+ unsigned int lsc) -+{ -+ down_write_nested(&rw->rwsem, lsc); -+ AuDbgWcntInc(rw); -+} -+ -+static inline void au_rw_write_unlock(struct au_rwsem *rw) -+{ -+ AuRwMustWriteLock(rw); -+ AuDbgWcntDec(rw); -+ up_write(&rw->rwsem); -+} -+ -+/* why is not _nested version defined */ -+static inline int au_rw_read_trylock(struct au_rwsem *rw) -+{ -+ int ret = down_read_trylock(&rw->rwsem); -+ if (ret) -+ AuDbgRcntInc(rw); -+ return ret; -+} -+ -+static inline int au_rw_write_trylock(struct au_rwsem *rw) -+{ -+ int ret = down_write_trylock(&rw->rwsem); -+ if (ret) -+ AuDbgWcntInc(rw); -+ return ret; -+} -+ -+#undef AuDbgCntInit -+#undef AuDbgRcntInc -+#undef AuDbgRcntDec -+#undef AuDbgWcntInc -+#undef AuDbgWcntDec -+ -+#define AuSimpleLockRwsemFuncs(prefix, param, rwsem) \ -+static inline void prefix##_read_lock(param) \ -+{ au_rw_read_lock(rwsem); } \ -+static inline void prefix##_write_lock(param) \ -+{ au_rw_write_lock(rwsem); } \ -+static inline int prefix##_read_trylock(param) \ -+{ return au_rw_read_trylock(rwsem); } \ -+static inline int prefix##_write_trylock(param) \ -+{ return au_rw_write_trylock(rwsem); } -+/* why is not _nested version defined */ -+/* static inline void prefix##_read_trylock_nested(param, lsc) -+{ au_rw_read_trylock_nested(rwsem, lsc)); } -+static inline void prefix##_write_trylock_nestd(param, lsc) -+{ au_rw_write_trylock_nested(rwsem, lsc); } */ -+ -+#define AuSimpleUnlockRwsemFuncs(prefix, param, rwsem) \ -+static inline void prefix##_read_unlock(param) \ -+{ au_rw_read_unlock(rwsem); } \ -+static inline void prefix##_write_unlock(param) \ -+{ au_rw_write_unlock(rwsem); } \ -+static inline void prefix##_downgrade_lock(param) \ -+{ au_rw_dgrade_lock(rwsem); } -+ -+#define AuSimpleRwsemFuncs(prefix, param, rwsem) \ -+ AuSimpleLockRwsemFuncs(prefix, param, rwsem) \ -+ AuSimpleUnlockRwsemFuncs(prefix, param, rwsem) -+ -+#endif /* __KERNEL__ */ -+#endif /* __AUFS_RWSEM_H__ */ -diff -Nur linux-2.6.37.orig/fs/aufs/sbinfo.c linux-2.6.37/fs/aufs/sbinfo.c ---- linux-2.6.37.orig/fs/aufs/sbinfo.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/sbinfo.c 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,345 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * superblock private data -+ */ -+ -+#include -+#include "aufs.h" -+ -+/* -+ * they are necessary regardless sysfs is disabled. -+ */ -+void au_si_free(struct kobject *kobj) -+{ -+ struct au_sbinfo *sbinfo; -+ char *locked __maybe_unused; /* debug only */ -+ -+ sbinfo = container_of(kobj, struct au_sbinfo, si_kobj); -+ AuDebugOn(!list_empty(&sbinfo->si_plink.head)); -+ AuDebugOn(atomic_read(&sbinfo->si_nowait.nw_len)); -+ -+ au_rw_write_lock(&sbinfo->si_rwsem); -+ au_br_free(sbinfo); -+ au_rw_write_unlock(&sbinfo->si_rwsem); -+ -+ AuDebugOn(radix_tree_gang_lookup -+ (&sbinfo->au_si_pid.tree, (void **)&locked, -+ /*first_index*/PID_MAX_DEFAULT - 1, -+ /*max_items*/sizeof(locked)/sizeof(*locked))); -+ -+ kfree(sbinfo->si_branch); -+ kfree(sbinfo->au_si_pid.bitmap); -+ mutex_destroy(&sbinfo->si_xib_mtx); -+ AuRwDestroy(&sbinfo->si_rwsem); -+ -+ kfree(sbinfo); -+} -+ -+int au_si_alloc(struct super_block *sb) -+{ -+ int err; -+ struct au_sbinfo *sbinfo; -+ static struct lock_class_key aufs_si; -+ -+ err = -ENOMEM; -+ sbinfo = kzalloc(sizeof(*sbinfo), GFP_NOFS); -+ if (unlikely(!sbinfo)) -+ goto out; -+ -+ BUILD_BUG_ON(sizeof(unsigned long) != -+ sizeof(*sbinfo->au_si_pid.bitmap)); -+ sbinfo->au_si_pid.bitmap = kcalloc(BITS_TO_LONGS(PID_MAX_DEFAULT), -+ sizeof(*sbinfo->au_si_pid.bitmap), -+ GFP_NOFS); -+ if (unlikely(!sbinfo->au_si_pid.bitmap)) -+ goto out_sbinfo; -+ -+ /* will be reallocated separately */ -+ sbinfo->si_branch = kzalloc(sizeof(*sbinfo->si_branch), GFP_NOFS); -+ if (unlikely(!sbinfo->si_branch)) -+ goto out_pidmap; -+ -+ err = sysaufs_si_init(sbinfo); -+ if (unlikely(err)) -+ goto out_br; -+ -+ au_nwt_init(&sbinfo->si_nowait); -+ au_rw_init_wlock(&sbinfo->si_rwsem); -+ au_rw_class(&sbinfo->si_rwsem, &aufs_si); -+ spin_lock_init(&sbinfo->au_si_pid.tree_lock); -+ INIT_RADIX_TREE(&sbinfo->au_si_pid.tree, GFP_ATOMIC | __GFP_NOFAIL); -+ -+ atomic_long_set(&sbinfo->si_ninodes, 0); -+ atomic_long_set(&sbinfo->si_nfiles, 0); -+ -+ sbinfo->si_bend = -1; -+ -+ sbinfo->si_wbr_copyup = AuWbrCopyup_Def; -+ sbinfo->si_wbr_create = AuWbrCreate_Def; -+ sbinfo->si_wbr_copyup_ops = au_wbr_copyup_ops + sbinfo->si_wbr_copyup; -+ sbinfo->si_wbr_create_ops = au_wbr_create_ops + sbinfo->si_wbr_create; -+ -+ sbinfo->si_mntflags = au_opts_plink(AuOpt_Def); -+ -+ mutex_init(&sbinfo->si_xib_mtx); -+ sbinfo->si_xino_brid = -1; -+ /* leave si_xib_last_pindex and si_xib_next_bit */ -+ -+ sbinfo->si_rdcache = msecs_to_jiffies(AUFS_RDCACHE_DEF * MSEC_PER_SEC); -+ sbinfo->si_rdblk = AUFS_RDBLK_DEF; -+ sbinfo->si_rdhash = AUFS_RDHASH_DEF; -+ sbinfo->si_dirwh = AUFS_DIRWH_DEF; -+ -+ au_spl_init(&sbinfo->si_plink); -+ init_waitqueue_head(&sbinfo->si_plink_wq); -+ spin_lock_init(&sbinfo->si_plink_maint_lock); -+ -+ /* leave other members for sysaufs and si_mnt. */ -+ sbinfo->si_sb = sb; -+ sb->s_fs_info = sbinfo; -+ si_pid_set(sb); -+ au_debug_sbinfo_init(sbinfo); -+ return 0; /* success */ -+ -+out_br: -+ kfree(sbinfo->si_branch); -+out_pidmap: -+ kfree(sbinfo->au_si_pid.bitmap); -+out_sbinfo: -+ kfree(sbinfo); -+out: -+ return err; -+} -+ -+int au_sbr_realloc(struct au_sbinfo *sbinfo, int nbr) -+{ -+ int err, sz; -+ struct au_branch **brp; -+ -+ AuRwMustWriteLock(&sbinfo->si_rwsem); -+ -+ err = -ENOMEM; -+ sz = sizeof(*brp) * (sbinfo->si_bend + 1); -+ if (unlikely(!sz)) -+ sz = sizeof(*brp); -+ brp = au_kzrealloc(sbinfo->si_branch, sz, sizeof(*brp) * nbr, GFP_NOFS); -+ if (brp) { -+ sbinfo->si_branch = brp; -+ err = 0; -+ } -+ -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+unsigned int au_sigen_inc(struct super_block *sb) -+{ -+ unsigned int gen; -+ -+ SiMustWriteLock(sb); -+ -+ gen = ++au_sbi(sb)->si_generation; -+ au_update_digen(sb->s_root); -+ au_update_iigen(sb->s_root->d_inode); -+ sb->s_root->d_inode->i_version++; -+ return gen; -+} -+ -+aufs_bindex_t au_new_br_id(struct super_block *sb) -+{ -+ aufs_bindex_t br_id; -+ int i; -+ struct au_sbinfo *sbinfo; -+ -+ SiMustWriteLock(sb); -+ -+ sbinfo = au_sbi(sb); -+ for (i = 0; i <= AUFS_BRANCH_MAX; i++) { -+ br_id = ++sbinfo->si_last_br_id; -+ AuDebugOn(br_id < 0); -+ if (br_id && au_br_index(sb, br_id) < 0) -+ return br_id; -+ } -+ -+ return -1; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* it is ok that new 'nwt' tasks are appended while we are sleeping */ -+int si_read_lock(struct super_block *sb, int flags) -+{ -+ int err; -+ -+ err = 0; -+ if (au_ftest_lock(flags, FLUSH)) -+ au_nwt_flush(&au_sbi(sb)->si_nowait); -+ -+ si_noflush_read_lock(sb); -+ err = au_plink_maint(sb, flags); -+ if (unlikely(err)) -+ si_read_unlock(sb); -+ -+ return err; -+} -+ -+int si_write_lock(struct super_block *sb, int flags) -+{ -+ int err; -+ -+ if (au_ftest_lock(flags, FLUSH)) -+ au_nwt_flush(&au_sbi(sb)->si_nowait); -+ -+ si_noflush_write_lock(sb); -+ err = au_plink_maint(sb, flags); -+ if (unlikely(err)) -+ si_write_unlock(sb); -+ -+ return err; -+} -+ -+/* dentry and super_block lock. call at entry point */ -+int aufs_read_lock(struct dentry *dentry, int flags) -+{ -+ int err; -+ struct super_block *sb; -+ -+ sb = dentry->d_sb; -+ err = si_read_lock(sb, flags); -+ if (unlikely(err)) -+ goto out; -+ -+ if (au_ftest_lock(flags, DW)) -+ di_write_lock_child(dentry); -+ else -+ di_read_lock_child(dentry, flags); -+ -+ if (au_ftest_lock(flags, GEN)) { -+ err = au_digen_test(dentry, au_sigen(sb)); -+ AuDebugOn(!err && au_dbrange_test(dentry)); -+ if (unlikely(err)) -+ aufs_read_unlock(dentry, flags); -+ } -+ -+out: -+ return err; -+} -+ -+void aufs_read_unlock(struct dentry *dentry, int flags) -+{ -+ if (au_ftest_lock(flags, DW)) -+ di_write_unlock(dentry); -+ else -+ di_read_unlock(dentry, flags); -+ si_read_unlock(dentry->d_sb); -+} -+ -+void aufs_write_lock(struct dentry *dentry) -+{ -+ si_write_lock(dentry->d_sb, AuLock_FLUSH | AuLock_NOPLMW); -+ di_write_lock_child(dentry); -+} -+ -+void aufs_write_unlock(struct dentry *dentry) -+{ -+ di_write_unlock(dentry); -+ si_write_unlock(dentry->d_sb); -+} -+ -+int aufs_read_and_write_lock2(struct dentry *d1, struct dentry *d2, int flags) -+{ -+ int err; -+ unsigned int sigen; -+ struct super_block *sb; -+ -+ sb = d1->d_sb; -+ err = si_read_lock(sb, flags); -+ if (unlikely(err)) -+ goto out; -+ -+ di_write_lock2_child(d1, d2, au_ftest_lock(flags, DIR)); -+ -+ if (au_ftest_lock(flags, GEN)) { -+ sigen = au_sigen(sb); -+ err = au_digen_test(d1, sigen); -+ AuDebugOn(!err && au_dbrange_test(d1)); -+ if (!err) { -+ err = au_digen_test(d2, sigen); -+ AuDebugOn(!err && au_dbrange_test(d2)); -+ } -+ if (unlikely(err)) -+ aufs_read_and_write_unlock2(d1, d2); -+ } -+ -+out: -+ return err; -+} -+ -+void aufs_read_and_write_unlock2(struct dentry *d1, struct dentry *d2) -+{ -+ di_write_unlock2(d1, d2); -+ si_read_unlock(d1->d_sb); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+int si_pid_test_slow(struct super_block *sb) -+{ -+ void *p; -+ -+ rcu_read_lock(); -+ p = radix_tree_lookup(&au_sbi(sb)->au_si_pid.tree, current->pid); -+ rcu_read_unlock(); -+ -+ return (long)p; -+} -+ -+void si_pid_set_slow(struct super_block *sb) -+{ -+ int err; -+ struct au_sbinfo *sbinfo; -+ -+ AuDebugOn(si_pid_test_slow(sb)); -+ -+ sbinfo = au_sbi(sb); -+ err = radix_tree_preload(GFP_NOFS | __GFP_NOFAIL); -+ AuDebugOn(err); -+ spin_lock(&sbinfo->au_si_pid.tree_lock); -+ err = radix_tree_insert(&sbinfo->au_si_pid.tree, current->pid, -+ (void *)1); -+ spin_unlock(&sbinfo->au_si_pid.tree_lock); -+ AuDebugOn(err); -+ radix_tree_preload_end(); -+} -+ -+void si_pid_clr_slow(struct super_block *sb) -+{ -+ void *p; -+ struct au_sbinfo *sbinfo; -+ -+ AuDebugOn(!si_pid_test_slow(sb)); -+ -+ sbinfo = au_sbi(sb); -+ spin_lock(&sbinfo->au_si_pid.tree_lock); -+ p = radix_tree_delete(&sbinfo->au_si_pid.tree, current->pid); -+ spin_unlock(&sbinfo->au_si_pid.tree_lock); -+ AuDebugOn(1 != (long)p); -+} -diff -Nur linux-2.6.37.orig/fs/aufs/spl.h linux-2.6.37/fs/aufs/spl.h ---- linux-2.6.37.orig/fs/aufs/spl.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/spl.h 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,66 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * simple list protected by a spinlock -+ */ -+ -+#ifndef __AUFS_SPL_H__ -+#define __AUFS_SPL_H__ -+ -+#ifdef __KERNEL__ -+ -+#include -+#include -+#include -+ -+struct au_splhead { -+ spinlock_t spin; -+ struct list_head head; -+}; -+ -+static inline void au_spl_init(struct au_splhead *spl) -+{ -+ spin_lock_init(&spl->spin); -+ INIT_LIST_HEAD(&spl->head); -+} -+ -+static inline void au_spl_add(struct list_head *list, struct au_splhead *spl) -+{ -+ spin_lock(&spl->spin); -+ list_add(list, &spl->head); -+ spin_unlock(&spl->spin); -+} -+ -+static inline void au_spl_del(struct list_head *list, struct au_splhead *spl) -+{ -+ spin_lock(&spl->spin); -+ list_del(list); -+ spin_unlock(&spl->spin); -+} -+ -+static inline void au_spl_del_rcu(struct list_head *list, -+ struct au_splhead *spl) -+{ -+ spin_lock(&spl->spin); -+ list_del_rcu(list); -+ spin_unlock(&spl->spin); -+} -+ -+#endif /* __KERNEL__ */ -+#endif /* __AUFS_SPL_H__ */ -diff -Nur linux-2.6.37.orig/fs/aufs/super.c linux-2.6.37/fs/aufs/super.c ---- linux-2.6.37.orig/fs/aufs/super.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/super.c 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,913 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * mount and super_block operations -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "aufs.h" -+ -+/* -+ * super_operations -+ */ -+static struct inode *aufs_alloc_inode(struct super_block *sb __maybe_unused) -+{ -+ struct au_icntnr *c; -+ -+ c = au_cache_alloc_icntnr(); -+ if (c) { -+ au_icntnr_init(c); -+ c->vfs_inode.i_version = 1; /* sigen(sb); */ -+ c->iinfo.ii_hinode = NULL; -+ return &c->vfs_inode; -+ } -+ return NULL; -+} -+ -+static void aufs_destroy_inode(struct inode *inode) -+{ -+ au_iinfo_fin(inode); -+ au_cache_free_icntnr(container_of(inode, struct au_icntnr, vfs_inode)); -+} -+ -+struct inode *au_iget_locked(struct super_block *sb, ino_t ino) -+{ -+ struct inode *inode; -+ int err; -+ -+ inode = iget_locked(sb, ino); -+ if (unlikely(!inode)) { -+ inode = ERR_PTR(-ENOMEM); -+ goto out; -+ } -+ if (!(inode->i_state & I_NEW)) -+ goto out; -+ -+ err = au_xigen_new(inode); -+ if (!err) -+ err = au_iinfo_init(inode); -+ if (!err) -+ inode->i_version++; -+ else { -+ iget_failed(inode); -+ inode = ERR_PTR(err); -+ } -+ -+out: -+ /* never return NULL */ -+ AuDebugOn(!inode); -+ AuTraceErrPtr(inode); -+ return inode; -+} -+ -+/* lock free root dinfo */ -+static int au_show_brs(struct seq_file *seq, struct super_block *sb) -+{ -+ int err; -+ aufs_bindex_t bindex, bend; -+ struct path path; -+ struct au_hdentry *hdp; -+ struct au_branch *br; -+ -+ err = 0; -+ bend = au_sbend(sb); -+ hdp = au_di(sb->s_root)->di_hdentry; -+ for (bindex = 0; !err && bindex <= bend; bindex++) { -+ br = au_sbr(sb, bindex); -+ path.mnt = br->br_mnt; -+ path.dentry = hdp[bindex].hd_dentry; -+ err = au_seq_path(seq, &path); -+ if (err > 0) -+ err = seq_printf(seq, "=%s", -+ au_optstr_br_perm(br->br_perm)); -+ if (!err && bindex != bend) -+ err = seq_putc(seq, ':'); -+ } -+ -+ return err; -+} -+ -+static void au_show_wbr_create(struct seq_file *m, int v, -+ struct au_sbinfo *sbinfo) -+{ -+ const char *pat; -+ -+ AuRwMustAnyLock(&sbinfo->si_rwsem); -+ -+ seq_printf(m, ",create="); -+ pat = au_optstr_wbr_create(v); -+ switch (v) { -+ case AuWbrCreate_TDP: -+ case AuWbrCreate_RR: -+ case AuWbrCreate_MFS: -+ case AuWbrCreate_PMFS: -+ seq_printf(m, pat); -+ break; -+ case AuWbrCreate_MFSV: -+ seq_printf(m, /*pat*/"mfs:%lu", -+ jiffies_to_msecs(sbinfo->si_wbr_mfs.mfs_expire) -+ / MSEC_PER_SEC); -+ break; -+ case AuWbrCreate_PMFSV: -+ seq_printf(m, /*pat*/"pmfs:%lu", -+ jiffies_to_msecs(sbinfo->si_wbr_mfs.mfs_expire) -+ / MSEC_PER_SEC); -+ break; -+ case AuWbrCreate_MFSRR: -+ seq_printf(m, /*pat*/"mfsrr:%llu", -+ sbinfo->si_wbr_mfs.mfsrr_watermark); -+ break; -+ case AuWbrCreate_MFSRRV: -+ seq_printf(m, /*pat*/"mfsrr:%llu:%lu", -+ sbinfo->si_wbr_mfs.mfsrr_watermark, -+ jiffies_to_msecs(sbinfo->si_wbr_mfs.mfs_expire) -+ / MSEC_PER_SEC); -+ break; -+ } -+} -+ -+static int au_show_xino(struct seq_file *seq, struct vfsmount *mnt) -+{ -+#ifdef CONFIG_SYSFS -+ return 0; -+#else -+ int err; -+ const int len = sizeof(AUFS_XINO_FNAME) - 1; -+ aufs_bindex_t bindex, brid; -+ struct super_block *sb; -+ struct qstr *name; -+ struct file *f; -+ struct dentry *d, *h_root; -+ struct au_hdentry *hdp; -+ -+ AuRwMustAnyLock(&sbinfo->si_rwsem); -+ -+ err = 0; -+ sb = mnt->mnt_sb; -+ f = au_sbi(sb)->si_xib; -+ if (!f) -+ goto out; -+ -+ /* stop printing the default xino path on the first writable branch */ -+ h_root = NULL; -+ brid = au_xino_brid(sb); -+ if (brid >= 0) { -+ bindex = au_br_index(sb, brid); -+ hdp = au_di(sb->s_root)->di_hdentry; -+ h_root = hdp[0 + bindex].hd_dentry; -+ } -+ d = f->f_dentry; -+ name = &d->d_name; -+ /* safe ->d_parent because the file is unlinked */ -+ if (d->d_parent == h_root -+ && name->len == len -+ && !memcmp(name->name, AUFS_XINO_FNAME, len)) -+ goto out; -+ -+ seq_puts(seq, ",xino="); -+ err = au_xino_path(seq, f); -+ -+out: -+ return err; -+#endif -+} -+ -+/* seq_file will re-call me in case of too long string */ -+static int aufs_show_options(struct seq_file *m, struct vfsmount *mnt) -+{ -+ int err; -+ unsigned int mnt_flags, v; -+ struct super_block *sb; -+ struct au_sbinfo *sbinfo; -+ -+#define AuBool(name, str) do { \ -+ v = au_opt_test(mnt_flags, name); \ -+ if (v != au_opt_test(AuOpt_Def, name)) \ -+ seq_printf(m, ",%s" #str, v ? "" : "no"); \ -+} while (0) -+ -+#define AuStr(name, str) do { \ -+ v = mnt_flags & AuOptMask_##name; \ -+ if (v != (AuOpt_Def & AuOptMask_##name)) \ -+ seq_printf(m, "," #str "=%s", au_optstr_##str(v)); \ -+} while (0) -+ -+#define AuUInt(name, str, val) do { \ -+ if (val != AUFS_##name##_DEF) \ -+ seq_printf(m, "," #str "=%u", val); \ -+} while (0) -+ -+ /* lock free root dinfo */ -+ sb = mnt->mnt_sb; -+ si_noflush_read_lock(sb); -+ sbinfo = au_sbi(sb); -+ seq_printf(m, ",si=%lx", sysaufs_si_id(sbinfo)); -+ -+ mnt_flags = au_mntflags(sb); -+ if (au_opt_test(mnt_flags, XINO)) { -+ err = au_show_xino(m, mnt); -+ if (unlikely(err)) -+ goto out; -+ } else -+ seq_puts(m, ",noxino"); -+ -+ AuBool(TRUNC_XINO, trunc_xino); -+ AuStr(UDBA, udba); -+ AuBool(SHWH, shwh); -+ AuBool(PLINK, plink); -+ AuBool(DIO, dio); -+ /* AuBool(DIRPERM1, dirperm1); */ -+ /* AuBool(REFROF, refrof); */ -+ -+ v = sbinfo->si_wbr_create; -+ if (v != AuWbrCreate_Def) -+ au_show_wbr_create(m, v, sbinfo); -+ -+ v = sbinfo->si_wbr_copyup; -+ if (v != AuWbrCopyup_Def) -+ seq_printf(m, ",cpup=%s", au_optstr_wbr_copyup(v)); -+ -+ v = au_opt_test(mnt_flags, ALWAYS_DIROPQ); -+ if (v != au_opt_test(AuOpt_Def, ALWAYS_DIROPQ)) -+ seq_printf(m, ",diropq=%c", v ? 'a' : 'w'); -+ -+ AuUInt(DIRWH, dirwh, sbinfo->si_dirwh); -+ -+ v = jiffies_to_msecs(sbinfo->si_rdcache) / MSEC_PER_SEC; -+ AuUInt(RDCACHE, rdcache, v); -+ -+ AuUInt(RDBLK, rdblk, sbinfo->si_rdblk); -+ AuUInt(RDHASH, rdhash, sbinfo->si_rdhash); -+ -+ AuBool(SUM, sum); -+ /* AuBool(SUM_W, wsum); */ -+ AuBool(WARN_PERM, warn_perm); -+ AuBool(VERBOSE, verbose); -+ -+out: -+ /* be sure to print "br:" last */ -+ if (!sysaufs_brs) { -+ seq_puts(m, ",br:"); -+ au_show_brs(m, sb); -+ } -+ si_read_unlock(sb); -+ return 0; -+ -+#undef AuBool -+#undef AuStr -+#undef AuUInt -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* sum mode which returns the summation for statfs(2) */ -+ -+static u64 au_add_till_max(u64 a, u64 b) -+{ -+ u64 old; -+ -+ old = a; -+ a += b; -+ if (old < a) -+ return a; -+ return ULLONG_MAX; -+} -+ -+static int au_statfs_sum(struct super_block *sb, struct kstatfs *buf) -+{ -+ int err; -+ u64 blocks, bfree, bavail, files, ffree; -+ aufs_bindex_t bend, bindex, i; -+ unsigned char shared; -+ struct path h_path; -+ struct super_block *h_sb; -+ -+ blocks = 0; -+ bfree = 0; -+ bavail = 0; -+ files = 0; -+ ffree = 0; -+ -+ err = 0; -+ bend = au_sbend(sb); -+ for (bindex = bend; bindex >= 0; bindex--) { -+ h_path.mnt = au_sbr_mnt(sb, bindex); -+ h_sb = h_path.mnt->mnt_sb; -+ shared = 0; -+ for (i = bindex + 1; !shared && i <= bend; i++) -+ shared = (au_sbr_sb(sb, i) == h_sb); -+ if (shared) -+ continue; -+ -+ /* sb->s_root for NFS is unreliable */ -+ h_path.dentry = h_path.mnt->mnt_root; -+ err = vfs_statfs(&h_path, buf); -+ if (unlikely(err)) -+ goto out; -+ -+ blocks = au_add_till_max(blocks, buf->f_blocks); -+ bfree = au_add_till_max(bfree, buf->f_bfree); -+ bavail = au_add_till_max(bavail, buf->f_bavail); -+ files = au_add_till_max(files, buf->f_files); -+ ffree = au_add_till_max(ffree, buf->f_ffree); -+ } -+ -+ buf->f_blocks = blocks; -+ buf->f_bfree = bfree; -+ buf->f_bavail = bavail; -+ buf->f_files = files; -+ buf->f_ffree = ffree; -+ -+out: -+ return err; -+} -+ -+static int aufs_statfs(struct dentry *dentry, struct kstatfs *buf) -+{ -+ int err; -+ struct path h_path; -+ struct super_block *sb; -+ -+ /* lock free root dinfo */ -+ sb = dentry->d_sb; -+ si_noflush_read_lock(sb); -+ if (!au_opt_test(au_mntflags(sb), SUM)) { -+ /* sb->s_root for NFS is unreliable */ -+ h_path.mnt = au_sbr_mnt(sb, 0); -+ h_path.dentry = h_path.mnt->mnt_root; -+ err = vfs_statfs(&h_path, buf); -+ } else -+ err = au_statfs_sum(sb, buf); -+ si_read_unlock(sb); -+ -+ if (!err) { -+ buf->f_type = AUFS_SUPER_MAGIC; -+ buf->f_namelen = AUFS_MAX_NAMELEN; -+ memset(&buf->f_fsid, 0, sizeof(buf->f_fsid)); -+ } -+ /* buf->f_bsize = buf->f_blocks = buf->f_bfree = buf->f_bavail = -1; */ -+ -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* final actions when unmounting a file system */ -+static void aufs_put_super(struct super_block *sb) -+{ -+ struct au_sbinfo *sbinfo; -+ -+ sbinfo = au_sbi(sb); -+ if (!sbinfo) -+ return; -+ -+ dbgaufs_si_fin(sbinfo); -+ kobject_put(&sbinfo->si_kobj); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+void au_array_free(void *array) -+{ -+ if (array) { -+ if (!is_vmalloc_addr(array)) -+ kfree(array); -+ else -+ vfree(array); -+ } -+} -+ -+void *au_array_alloc(unsigned long long *hint, au_arraycb_t cb, void *arg) -+{ -+ void *array; -+ unsigned long long n; -+ -+ array = NULL; -+ n = 0; -+ if (!*hint) -+ goto out; -+ -+ if (*hint > ULLONG_MAX / sizeof(array)) { -+ array = ERR_PTR(-EMFILE); -+ pr_err("hint %llu\n", *hint); -+ goto out; -+ } -+ -+ array = kmalloc(sizeof(array) * *hint, GFP_NOFS); -+ if (unlikely(!array)) -+ array = vmalloc(sizeof(array) * *hint); -+ if (unlikely(!array)) { -+ array = ERR_PTR(-ENOMEM); -+ goto out; -+ } -+ -+ n = cb(array, *hint, arg); -+ AuDebugOn(n > *hint); -+ -+out: -+ *hint = n; -+ return array; -+} -+ -+static unsigned long long au_iarray_cb(void *a, -+ unsigned long long max __maybe_unused, -+ void *arg) -+{ -+ unsigned long long n; -+ struct inode **p, *inode; -+ struct list_head *head; -+ -+ n = 0; -+ p = a; -+ head = arg; -+ spin_lock(&inode_lock); -+ list_for_each_entry(inode, head, i_sb_list) { -+ if (!is_bad_inode(inode) -+ && au_ii(inode)->ii_bstart >= 0) { -+ au_igrab(inode); -+ *p++ = inode; -+ n++; -+ AuDebugOn(n > max); -+ } -+ } -+ spin_unlock(&inode_lock); -+ -+ return n; -+} -+ -+struct inode **au_iarray_alloc(struct super_block *sb, unsigned long long *max) -+{ -+ *max = atomic_long_read(&au_sbi(sb)->si_ninodes); -+ return au_array_alloc(max, au_iarray_cb, &sb->s_inodes); -+} -+ -+void au_iarray_free(struct inode **a, unsigned long long max) -+{ -+ unsigned long long ull; -+ -+ for (ull = 0; ull < max; ull++) -+ iput(a[ull]); -+ au_array_free(a); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * refresh dentry and inode at remount time. -+ */ -+/* todo: consolidate with simple_reval_dpath() and au_reval_for_attr() */ -+static int au_do_refresh(struct dentry *dentry, unsigned int dir_flags, -+ struct dentry *parent) -+{ -+ int err; -+ -+ di_write_lock_child(dentry); -+ di_read_lock_parent(parent, AuLock_IR); -+ err = au_refresh_dentry(dentry, parent); -+ if (!err && dir_flags) -+ au_hn_reset(dentry->d_inode, dir_flags); -+ di_read_unlock(parent, AuLock_IR); -+ di_write_unlock(dentry); -+ -+ return err; -+} -+ -+static int au_do_refresh_d(struct dentry *dentry, unsigned int sigen, -+ struct au_sbinfo *sbinfo, -+ const unsigned int dir_flags) -+{ -+ int err; -+ struct dentry *parent; -+ struct inode *inode; -+ -+ err = 0; -+ parent = dget_parent(dentry); -+ if (!au_digen_test(parent, sigen) && au_digen_test(dentry, sigen)) { -+ inode = dentry->d_inode; -+ if (inode) { -+ if (!S_ISDIR(inode->i_mode)) -+ err = au_do_refresh(dentry, /*dir_flags*/0, -+ parent); -+ else { -+ err = au_do_refresh(dentry, dir_flags, parent); -+ if (unlikely(err)) -+ au_fset_si(sbinfo, FAILED_REFRESH_DIR); -+ } -+ } else -+ err = au_do_refresh(dentry, /*dir_flags*/0, parent); -+ AuDbgDentry(dentry); -+ } -+ dput(parent); -+ -+ AuTraceErr(err); -+ return err; -+} -+ -+static int au_refresh_d(struct super_block *sb) -+{ -+ int err, i, j, ndentry, e; -+ unsigned int sigen; -+ struct au_dcsub_pages dpages; -+ struct au_dpage *dpage; -+ struct dentry **dentries, *d; -+ struct au_sbinfo *sbinfo; -+ struct dentry *root = sb->s_root; -+ const unsigned int dir_flags = au_hi_flags(root->d_inode, /*isdir*/1); -+ -+ err = au_dpages_init(&dpages, GFP_NOFS); -+ if (unlikely(err)) -+ goto out; -+ err = au_dcsub_pages(&dpages, root, NULL, NULL); -+ if (unlikely(err)) -+ goto out_dpages; -+ -+ sigen = au_sigen(sb); -+ sbinfo = au_sbi(sb); -+ for (i = 0; i < dpages.ndpage; i++) { -+ dpage = dpages.dpages + i; -+ dentries = dpage->dentries; -+ ndentry = dpage->ndentry; -+ for (j = 0; j < ndentry; j++) { -+ d = dentries[j]; -+ e = au_do_refresh_d(d, sigen, sbinfo, dir_flags); -+ if (unlikely(e && !err)) -+ err = e; -+ /* go on even err */ -+ } -+ } -+ -+out_dpages: -+ au_dpages_free(&dpages); -+out: -+ return err; -+} -+ -+static int au_refresh_i(struct super_block *sb) -+{ -+ int err, e; -+ unsigned int sigen; -+ unsigned long long max, ull; -+ struct inode *inode, **array; -+ -+ array = au_iarray_alloc(sb, &max); -+ err = PTR_ERR(array); -+ if (IS_ERR(array)) -+ goto out; -+ -+ err = 0; -+ sigen = au_sigen(sb); -+ for (ull = 0; ull < max; ull++) { -+ inode = array[ull]; -+ if (au_iigen(inode) != sigen) { -+ ii_write_lock_child(inode); -+ e = au_refresh_hinode_self(inode); -+ ii_write_unlock(inode); -+ if (unlikely(e)) { -+ pr_err("error %d, i%lu\n", e, inode->i_ino); -+ if (!err) -+ err = e; -+ /* go on even if err */ -+ } -+ } -+ } -+ -+ au_iarray_free(array, max); -+ -+out: -+ return err; -+} -+ -+static void au_remount_refresh(struct super_block *sb) -+{ -+ int err, e; -+ unsigned int udba; -+ aufs_bindex_t bindex, bend; -+ struct dentry *root; -+ struct inode *inode; -+ struct au_branch *br; -+ -+ au_sigen_inc(sb); -+ au_fclr_si(au_sbi(sb), FAILED_REFRESH_DIR); -+ -+ root = sb->s_root; -+ DiMustNoWaiters(root); -+ inode = root->d_inode; -+ IiMustNoWaiters(inode); -+ -+ udba = au_opt_udba(sb); -+ bend = au_sbend(sb); -+ for (bindex = 0; bindex <= bend; bindex++) { -+ br = au_sbr(sb, bindex); -+ err = au_hnotify_reset_br(udba, br, br->br_perm); -+ if (unlikely(err)) -+ AuIOErr("hnotify failed on br %d, %d, ignored\n", -+ bindex, err); -+ /* go on even if err */ -+ } -+ au_hn_reset(inode, au_hi_flags(inode, /*isdir*/1)); -+ -+ di_write_unlock(root); -+ err = au_refresh_d(sb); -+ e = au_refresh_i(sb); -+ if (unlikely(e && !err)) -+ err = e; -+ /* aufs_write_lock() calls ..._child() */ -+ di_write_lock_child(root); -+ -+ au_cpup_attr_all(inode, /*force*/1); -+ -+ if (unlikely(err)) -+ AuIOErr("refresh failed, ignored, %d\n", err); -+} -+ -+/* stop extra interpretation of errno in mount(8), and strange error messages */ -+static int cvt_err(int err) -+{ -+ AuTraceErr(err); -+ -+ switch (err) { -+ case -ENOENT: -+ case -ENOTDIR: -+ case -EEXIST: -+ case -EIO: -+ err = -EINVAL; -+ } -+ return err; -+} -+ -+static int aufs_remount_fs(struct super_block *sb, int *flags, char *data) -+{ -+ int err, do_dx; -+ unsigned int mntflags; -+ struct au_opts opts; -+ struct dentry *root; -+ struct inode *inode; -+ struct au_sbinfo *sbinfo; -+ -+ err = 0; -+ root = sb->s_root; -+ if (!data || !*data) { -+ err = si_write_lock(sb, AuLock_FLUSH | AuLock_NOPLM); -+ if (!err) { -+ di_write_lock_child(root); -+ err = au_opts_verify(sb, *flags, /*pending*/0); -+ aufs_write_unlock(root); -+ } -+ goto out; -+ } -+ -+ err = -ENOMEM; -+ memset(&opts, 0, sizeof(opts)); -+ opts.opt = (void *)__get_free_page(GFP_NOFS); -+ if (unlikely(!opts.opt)) -+ goto out; -+ opts.max_opt = PAGE_SIZE / sizeof(*opts.opt); -+ opts.flags = AuOpts_REMOUNT; -+ opts.sb_flags = *flags; -+ -+ /* parse it before aufs lock */ -+ err = au_opts_parse(sb, data, &opts); -+ if (unlikely(err)) -+ goto out_opts; -+ -+ sbinfo = au_sbi(sb); -+ inode = root->d_inode; -+ mutex_lock(&inode->i_mutex); -+ err = si_write_lock(sb, AuLock_FLUSH | AuLock_NOPLM); -+ if (unlikely(err)) -+ goto out_mtx; -+ di_write_lock_child(root); -+ -+ /* au_opts_remount() may return an error */ -+ err = au_opts_remount(sb, &opts); -+ au_opts_free(&opts); -+ -+ if (au_ftest_opts(opts.flags, REFRESH)) -+ au_remount_refresh(sb); -+ -+ if (au_ftest_opts(opts.flags, REFRESH_DYAOP)) { -+ mntflags = au_mntflags(sb); -+ do_dx = !!au_opt_test(mntflags, DIO); -+ au_dy_arefresh(do_dx); -+ } -+ -+ aufs_write_unlock(root); -+ -+out_mtx: -+ mutex_unlock(&inode->i_mutex); -+out_opts: -+ free_page((unsigned long)opts.opt); -+out: -+ err = cvt_err(err); -+ AuTraceErr(err); -+ return err; -+} -+ -+static const struct super_operations aufs_sop = { -+ .alloc_inode = aufs_alloc_inode, -+ .destroy_inode = aufs_destroy_inode, -+ /* always deleting, no clearing */ -+ .drop_inode = generic_delete_inode, -+ .show_options = aufs_show_options, -+ .statfs = aufs_statfs, -+ .put_super = aufs_put_super, -+ .remount_fs = aufs_remount_fs -+}; -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int alloc_root(struct super_block *sb) -+{ -+ int err; -+ struct inode *inode; -+ struct dentry *root; -+ -+ err = -ENOMEM; -+ inode = au_iget_locked(sb, AUFS_ROOT_INO); -+ err = PTR_ERR(inode); -+ if (IS_ERR(inode)) -+ goto out; -+ -+ inode->i_op = &aufs_dir_iop; -+ inode->i_fop = &aufs_dir_fop; -+ inode->i_mode = S_IFDIR; -+ inode->i_nlink = 2; -+ unlock_new_inode(inode); -+ -+ root = d_alloc_root(inode); -+ if (unlikely(!root)) -+ goto out_iput; -+ err = PTR_ERR(root); -+ if (IS_ERR(root)) -+ goto out_iput; -+ -+ err = au_di_init(root); -+ if (!err) { -+ sb->s_root = root; -+ return 0; /* success */ -+ } -+ dput(root); -+ goto out; /* do not iput */ -+ -+out_iput: -+ iget_failed(inode); -+out: -+ return err; -+ -+} -+ -+static int aufs_fill_super(struct super_block *sb, void *raw_data, -+ int silent __maybe_unused) -+{ -+ int err; -+ struct au_opts opts; -+ struct dentry *root; -+ struct inode *inode; -+ char *arg = raw_data; -+ -+ if (unlikely(!arg || !*arg)) { -+ err = -EINVAL; -+ pr_err("no arg\n"); -+ goto out; -+ } -+ -+ err = -ENOMEM; -+ memset(&opts, 0, sizeof(opts)); -+ opts.opt = (void *)__get_free_page(GFP_NOFS); -+ if (unlikely(!opts.opt)) -+ goto out; -+ opts.max_opt = PAGE_SIZE / sizeof(*opts.opt); -+ opts.sb_flags = sb->s_flags; -+ -+ err = au_si_alloc(sb); -+ if (unlikely(err)) -+ goto out_opts; -+ -+ /* all timestamps always follow the ones on the branch */ -+ sb->s_flags |= MS_NOATIME | MS_NODIRATIME; -+ sb->s_op = &aufs_sop; -+ sb->s_magic = AUFS_SUPER_MAGIC; -+ sb->s_maxbytes = 0; -+ au_export_init(sb); -+ -+ err = alloc_root(sb); -+ if (unlikely(err)) { -+ si_write_unlock(sb); -+ goto out_info; -+ } -+ root = sb->s_root; -+ inode = root->d_inode; -+ -+ /* -+ * actually we can parse options regardless aufs lock here. -+ * but at remount time, parsing must be done before aufs lock. -+ * so we follow the same rule. -+ */ -+ ii_write_lock_parent(inode); -+ aufs_write_unlock(root); -+ err = au_opts_parse(sb, arg, &opts); -+ if (unlikely(err)) -+ goto out_root; -+ -+ /* lock vfs_inode first, then aufs. */ -+ mutex_lock(&inode->i_mutex); -+ aufs_write_lock(root); -+ err = au_opts_mount(sb, &opts); -+ au_opts_free(&opts); -+ aufs_write_unlock(root); -+ mutex_unlock(&inode->i_mutex); -+ if (!err) -+ goto out_opts; /* success */ -+ -+out_root: -+ dput(root); -+ sb->s_root = NULL; -+out_info: -+ kobject_put(&au_sbi(sb)->si_kobj); -+ sb->s_fs_info = NULL; -+out_opts: -+ free_page((unsigned long)opts.opt); -+out: -+ AuTraceErr(err); -+ err = cvt_err(err); -+ AuTraceErr(err); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int aufs_get_sb(struct file_system_type *fs_type, int flags, -+ const char *dev_name __maybe_unused, void *raw_data, -+ struct vfsmount *mnt) -+{ -+ int err; -+ struct super_block *sb; -+ -+ /* all timestamps always follow the ones on the branch */ -+ /* mnt->mnt_flags |= MNT_NOATIME | MNT_NODIRATIME; */ -+ err = get_sb_nodev(fs_type, flags, raw_data, aufs_fill_super, mnt); -+ if (!err) { -+ sb = mnt->mnt_sb; -+ si_write_lock(sb, !AuLock_FLUSH); -+ sysaufs_brs_add(sb, 0); -+ si_write_unlock(sb); -+ au_sbilist_add(sb); -+ } -+ return err; -+} -+ -+static void aufs_kill_sb(struct super_block *sb) -+{ -+ struct au_sbinfo *sbinfo; -+ -+ sbinfo = au_sbi(sb); -+ if (sbinfo) { -+ au_sbilist_del(sb); -+ aufs_write_lock(sb->s_root); -+ if (sbinfo->si_wbr_create_ops->fin) -+ sbinfo->si_wbr_create_ops->fin(sb); -+ if (au_opt_test(sbinfo->si_mntflags, UDBA_HNOTIFY)) { -+ au_opt_set_udba(sbinfo->si_mntflags, UDBA_NONE); -+ au_remount_refresh(sb); -+ } -+ if (au_opt_test(sbinfo->si_mntflags, PLINK)) -+ au_plink_put(sb, /*verbose*/1); -+ au_xino_clr(sb); -+ aufs_write_unlock(sb->s_root); -+ au_nwt_flush(&sbinfo->si_nowait); -+ } -+ generic_shutdown_super(sb); -+} -+ -+struct file_system_type aufs_fs_type = { -+ .name = AUFS_FSTYPE, -+ .fs_flags = -+ FS_RENAME_DOES_D_MOVE /* a race between rename and others */ -+ | FS_REVAL_DOT, /* for NFS branch and udba */ -+ .get_sb = aufs_get_sb, -+ .kill_sb = aufs_kill_sb, -+ /* no need to __module_get() and module_put(). */ -+ .owner = THIS_MODULE, -+}; -diff -Nur linux-2.6.37.orig/fs/aufs/super.h linux-2.6.37/fs/aufs/super.h ---- linux-2.6.37.orig/fs/aufs/super.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/super.h 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,527 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * super_block operations -+ */ -+ -+#ifndef __AUFS_SUPER_H__ -+#define __AUFS_SUPER_H__ -+ -+#ifdef __KERNEL__ -+ -+#include -+#include -+#include "rwsem.h" -+#include "spl.h" -+#include "wkq.h" -+ -+typedef ssize_t (*au_readf_t)(struct file *, char __user *, size_t, loff_t *); -+typedef ssize_t (*au_writef_t)(struct file *, const char __user *, size_t, -+ loff_t *); -+ -+/* policies to select one among multiple writable branches */ -+struct au_wbr_copyup_operations { -+ int (*copyup)(struct dentry *dentry); -+}; -+ -+struct au_wbr_create_operations { -+ int (*create)(struct dentry *dentry, int isdir); -+ int (*init)(struct super_block *sb); -+ int (*fin)(struct super_block *sb); -+}; -+ -+struct au_wbr_mfs { -+ struct mutex mfs_lock; /* protect this structure */ -+ unsigned long mfs_jiffy; -+ unsigned long mfs_expire; -+ aufs_bindex_t mfs_bindex; -+ -+ unsigned long long mfsrr_bytes; -+ unsigned long long mfsrr_watermark; -+}; -+ -+struct au_branch; -+struct au_sbinfo { -+ /* nowait tasks in the system-wide workqueue */ -+ struct au_nowait_tasks si_nowait; -+ -+ /* -+ * tried sb->s_umount, but failed due to the dependecy between i_mutex. -+ * rwsem for au_sbinfo is necessary. -+ */ -+ struct au_rwsem si_rwsem; -+ -+ /* prevent recursive locking in deleting inode */ -+ struct { -+ unsigned long *bitmap; -+ spinlock_t tree_lock; -+ struct radix_tree_root tree; -+ } au_si_pid; -+ -+ /* -+ * dirty approach to protect sb->sb_inodes and ->s_files from remount. -+ */ -+ atomic_long_t si_ninodes, si_nfiles; -+ -+ /* branch management */ -+ unsigned int si_generation; -+ -+ /* see above flags */ -+ unsigned char au_si_status; -+ -+ aufs_bindex_t si_bend; -+ -+ /* dirty trick to keep br_id plus */ -+ unsigned int si_last_br_id : -+ sizeof(aufs_bindex_t) * BITS_PER_BYTE - 1; -+ struct au_branch **si_branch; -+ -+ /* policy to select a writable branch */ -+ unsigned char si_wbr_copyup; -+ unsigned char si_wbr_create; -+ struct au_wbr_copyup_operations *si_wbr_copyup_ops; -+ struct au_wbr_create_operations *si_wbr_create_ops; -+ -+ /* round robin */ -+ atomic_t si_wbr_rr_next; -+ -+ /* most free space */ -+ struct au_wbr_mfs si_wbr_mfs; -+ -+ /* mount flags */ -+ /* include/asm-ia64/siginfo.h defines a macro named si_flags */ -+ unsigned int si_mntflags; -+ -+ /* external inode number (bitmap and translation table) */ -+ au_readf_t si_xread; -+ au_writef_t si_xwrite; -+ struct file *si_xib; -+ struct mutex si_xib_mtx; /* protect xib members */ -+ unsigned long *si_xib_buf; -+ unsigned long si_xib_last_pindex; -+ int si_xib_next_bit; -+ aufs_bindex_t si_xino_brid; -+ /* reserved for future use */ -+ /* unsigned long long si_xib_limit; */ /* Max xib file size */ -+ -+#ifdef CONFIG_AUFS_EXPORT -+ /* i_generation */ -+ struct file *si_xigen; -+ atomic_t si_xigen_next; -+#endif -+ -+ /* vdir parameters */ -+ unsigned long si_rdcache; /* max cache time in jiffies */ -+ unsigned int si_rdblk; /* deblk size */ -+ unsigned int si_rdhash; /* hash size */ -+ -+ /* -+ * If the number of whiteouts are larger than si_dirwh, leave all of -+ * them after au_whtmp_ren to reduce the cost of rmdir(2). -+ * future fsck.aufs or kernel thread will remove them later. -+ * Otherwise, remove all whiteouts and the dir in rmdir(2). -+ */ -+ unsigned int si_dirwh; -+ -+ /* -+ * rename(2) a directory with all children. -+ */ -+ /* reserved for future use */ -+ /* int si_rendir; */ -+ -+ /* pseudo_link list */ -+ struct au_splhead si_plink; -+ wait_queue_head_t si_plink_wq; -+ spinlock_t si_plink_maint_lock; -+ pid_t si_plink_maint_pid; -+ -+ /* -+ * sysfs and lifetime management. -+ * this is not a small structure and it may be a waste of memory in case -+ * of sysfs is disabled, particulary when many aufs-es are mounted. -+ * but using sysfs is majority. -+ */ -+ struct kobject si_kobj; -+#ifdef CONFIG_DEBUG_FS -+ struct dentry *si_dbgaufs, *si_dbgaufs_xib; -+#ifdef CONFIG_AUFS_EXPORT -+ struct dentry *si_dbgaufs_xigen; -+#endif -+#endif -+ -+#ifdef CONFIG_AUFS_SBILIST -+ struct list_head si_list; -+#endif -+ -+ /* dirty, necessary for unmounting, sysfs and sysrq */ -+ struct super_block *si_sb; -+}; -+ -+/* sbinfo status flags */ -+/* -+ * set true when refresh_dirs() failed at remount time. -+ * then try refreshing dirs at access time again. -+ * if it is false, refreshing dirs at access time is unnecesary -+ */ -+#define AuSi_FAILED_REFRESH_DIR 1 -+static inline unsigned char au_do_ftest_si(struct au_sbinfo *sbi, -+ unsigned int flag) -+{ -+ AuRwMustAnyLock(&sbi->si_rwsem); -+ return sbi->au_si_status & flag; -+} -+#define au_ftest_si(sbinfo, name) au_do_ftest_si(sbinfo, AuSi_##name) -+#define au_fset_si(sbinfo, name) do { \ -+ AuRwMustWriteLock(&(sbinfo)->si_rwsem); \ -+ (sbinfo)->au_si_status |= AuSi_##name; \ -+} while (0) -+#define au_fclr_si(sbinfo, name) do { \ -+ AuRwMustWriteLock(&(sbinfo)->si_rwsem); \ -+ (sbinfo)->au_si_status &= ~AuSi_##name; \ -+} while (0) -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* policy to select one among writable branches */ -+#define AuWbrCopyup(sbinfo, ...) \ -+ ((sbinfo)->si_wbr_copyup_ops->copyup(__VA_ARGS__)) -+#define AuWbrCreate(sbinfo, ...) \ -+ ((sbinfo)->si_wbr_create_ops->create(__VA_ARGS__)) -+ -+/* flags for si_read_lock()/aufs_read_lock()/di_read_lock() */ -+#define AuLock_DW 1 /* write-lock dentry */ -+#define AuLock_IR (1 << 1) /* read-lock inode */ -+#define AuLock_IW (1 << 2) /* write-lock inode */ -+#define AuLock_FLUSH (1 << 3) /* wait for 'nowait' tasks */ -+#define AuLock_DIR (1 << 4) /* target is a dir */ -+#define AuLock_NOPLM (1 << 5) /* return err in plm mode */ -+#define AuLock_NOPLMW (1 << 6) /* wait for plm mode ends */ -+#define AuLock_GEN (1 << 7) /* test digen/iigen */ -+#define au_ftest_lock(flags, name) ((flags) & AuLock_##name) -+#define au_fset_lock(flags, name) \ -+ do { (flags) |= AuLock_##name; } while (0) -+#define au_fclr_lock(flags, name) \ -+ do { (flags) &= ~AuLock_##name; } while (0) -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* super.c */ -+extern struct file_system_type aufs_fs_type; -+struct inode *au_iget_locked(struct super_block *sb, ino_t ino); -+typedef unsigned long long (*au_arraycb_t)(void *array, unsigned long long max, -+ void *arg); -+void au_array_free(void *array); -+void *au_array_alloc(unsigned long long *hint, au_arraycb_t cb, void *arg); -+struct inode **au_iarray_alloc(struct super_block *sb, unsigned long long *max); -+void au_iarray_free(struct inode **a, unsigned long long max); -+ -+/* sbinfo.c */ -+void au_si_free(struct kobject *kobj); -+int au_si_alloc(struct super_block *sb); -+int au_sbr_realloc(struct au_sbinfo *sbinfo, int nbr); -+ -+unsigned int au_sigen_inc(struct super_block *sb); -+aufs_bindex_t au_new_br_id(struct super_block *sb); -+ -+int si_read_lock(struct super_block *sb, int flags); -+int si_write_lock(struct super_block *sb, int flags); -+int aufs_read_lock(struct dentry *dentry, int flags); -+void aufs_read_unlock(struct dentry *dentry, int flags); -+void aufs_write_lock(struct dentry *dentry); -+void aufs_write_unlock(struct dentry *dentry); -+int aufs_read_and_write_lock2(struct dentry *d1, struct dentry *d2, int flags); -+void aufs_read_and_write_unlock2(struct dentry *d1, struct dentry *d2); -+ -+int si_pid_test_slow(struct super_block *sb); -+void si_pid_set_slow(struct super_block *sb); -+void si_pid_clr_slow(struct super_block *sb); -+ -+/* wbr_policy.c */ -+extern struct au_wbr_copyup_operations au_wbr_copyup_ops[]; -+extern struct au_wbr_create_operations au_wbr_create_ops[]; -+int au_cpdown_dirs(struct dentry *dentry, aufs_bindex_t bdst); -+ -+/* ---------------------------------------------------------------------- */ -+ -+static inline struct au_sbinfo *au_sbi(struct super_block *sb) -+{ -+ return sb->s_fs_info; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+#ifdef CONFIG_AUFS_EXPORT -+void au_export_init(struct super_block *sb); -+ -+static inline int au_test_nfsd(void) -+{ -+ struct task_struct *tsk = current; -+ -+ return (tsk->flags & PF_KTHREAD) -+ && !strcmp(tsk->comm, "nfsd"); -+} -+ -+void au_xigen_inc(struct inode *inode); -+int au_xigen_new(struct inode *inode); -+int au_xigen_set(struct super_block *sb, struct file *base); -+void au_xigen_clr(struct super_block *sb); -+ -+static inline int au_busy_or_stale(void) -+{ -+ if (!au_test_nfsd()) -+ return -EBUSY; -+ return -ESTALE; -+} -+#else -+AuStubVoid(au_export_init, struct super_block *sb) -+AuStubInt0(au_test_nfsd, void) -+AuStubVoid(au_xigen_inc, struct inode *inode) -+AuStubInt0(au_xigen_new, struct inode *inode) -+AuStubInt0(au_xigen_set, struct super_block *sb, struct file *base) -+AuStubVoid(au_xigen_clr, struct super_block *sb) -+static inline int au_busy_or_stale(void) -+{ -+ return -EBUSY; -+} -+#endif /* CONFIG_AUFS_EXPORT */ -+ -+/* ---------------------------------------------------------------------- */ -+ -+#ifdef CONFIG_AUFS_SBILIST -+/* module.c */ -+extern struct au_splhead au_sbilist; -+ -+static inline void au_sbilist_init(void) -+{ -+ au_spl_init(&au_sbilist); -+} -+ -+static inline void au_sbilist_add(struct super_block *sb) -+{ -+ au_spl_add(&au_sbi(sb)->si_list, &au_sbilist); -+} -+ -+static inline void au_sbilist_del(struct super_block *sb) -+{ -+ au_spl_del(&au_sbi(sb)->si_list, &au_sbilist); -+} -+#else -+AuStubVoid(au_sbilist_init, void) -+AuStubVoid(au_sbilist_add, struct super_block*) -+AuStubVoid(au_sbilist_del, struct super_block*) -+#endif -+ -+/* ---------------------------------------------------------------------- */ -+ -+static inline void dbgaufs_si_null(struct au_sbinfo *sbinfo) -+{ -+ /* -+ * This function is a dynamic '__init' fucntion actually, -+ * so the tiny check for si_rwsem is unnecessary. -+ */ -+ /* AuRwMustWriteLock(&sbinfo->si_rwsem); */ -+#ifdef CONFIG_DEBUG_FS -+ sbinfo->si_dbgaufs = NULL; -+ sbinfo->si_dbgaufs_xib = NULL; -+#ifdef CONFIG_AUFS_EXPORT -+ sbinfo->si_dbgaufs_xigen = NULL; -+#endif -+#endif -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static inline pid_t si_pid_bit(void) -+{ -+ /* the origin of pid is 1, but the bitmap's is 0 */ -+ return current->pid - 1; -+} -+ -+static inline int si_pid_test(struct super_block *sb) -+{ -+ pid_t bit = si_pid_bit(); -+ if (bit < PID_MAX_DEFAULT) -+ return test_bit(bit, au_sbi(sb)->au_si_pid.bitmap); -+ else -+ return si_pid_test_slow(sb); -+} -+ -+static inline void si_pid_set(struct super_block *sb) -+{ -+ pid_t bit = si_pid_bit(); -+ if (bit < PID_MAX_DEFAULT) { -+ AuDebugOn(test_bit(bit, au_sbi(sb)->au_si_pid.bitmap)); -+ set_bit(bit, au_sbi(sb)->au_si_pid.bitmap); -+ /* smp_mb(); */ -+ } else -+ si_pid_set_slow(sb); -+} -+ -+static inline void si_pid_clr(struct super_block *sb) -+{ -+ pid_t bit = si_pid_bit(); -+ if (bit < PID_MAX_DEFAULT) { -+ AuDebugOn(!test_bit(bit, au_sbi(sb)->au_si_pid.bitmap)); -+ clear_bit(bit, au_sbi(sb)->au_si_pid.bitmap); -+ /* smp_mb(); */ -+ } else -+ si_pid_clr_slow(sb); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* lock superblock. mainly for entry point functions */ -+/* -+ * __si_read_lock, __si_write_lock, -+ * __si_read_unlock, __si_write_unlock, __si_downgrade_lock -+ */ -+AuSimpleRwsemFuncs(__si, struct super_block *sb, &au_sbi(sb)->si_rwsem); -+ -+#define SiMustNoWaiters(sb) AuRwMustNoWaiters(&au_sbi(sb)->si_rwsem) -+#define SiMustAnyLock(sb) AuRwMustAnyLock(&au_sbi(sb)->si_rwsem) -+#define SiMustWriteLock(sb) AuRwMustWriteLock(&au_sbi(sb)->si_rwsem) -+ -+static inline void si_noflush_read_lock(struct super_block *sb) -+{ -+ __si_read_lock(sb); -+ si_pid_set(sb); -+} -+ -+static inline int si_noflush_read_trylock(struct super_block *sb) -+{ -+ int locked = __si_read_trylock(sb); -+ if (locked) -+ si_pid_set(sb); -+ return locked; -+} -+ -+static inline void si_noflush_write_lock(struct super_block *sb) -+{ -+ __si_write_lock(sb); -+ si_pid_set(sb); -+} -+ -+static inline int si_noflush_write_trylock(struct super_block *sb) -+{ -+ int locked = __si_write_trylock(sb); -+ if (locked) -+ si_pid_set(sb); -+ return locked; -+} -+ -+#if 0 /* unused */ -+static inline int si_read_trylock(struct super_block *sb, int flags) -+{ -+ if (au_ftest_lock(flags, FLUSH)) -+ au_nwt_flush(&au_sbi(sb)->si_nowait); -+ return si_noflush_read_trylock(sb); -+} -+#endif -+ -+static inline void si_read_unlock(struct super_block *sb) -+{ -+ si_pid_clr(sb); -+ __si_read_unlock(sb); -+} -+ -+#if 0 /* unused */ -+static inline int si_write_trylock(struct super_block *sb, int flags) -+{ -+ if (au_ftest_lock(flags, FLUSH)) -+ au_nwt_flush(&au_sbi(sb)->si_nowait); -+ return si_noflush_write_trylock(sb); -+} -+#endif -+ -+static inline void si_write_unlock(struct super_block *sb) -+{ -+ si_pid_clr(sb); -+ __si_write_unlock(sb); -+} -+ -+#if 0 /* unused */ -+static inline void si_downgrade_lock(struct super_block *sb) -+{ -+ __si_downgrade_lock(sb); -+} -+#endif -+ -+/* ---------------------------------------------------------------------- */ -+ -+static inline aufs_bindex_t au_sbend(struct super_block *sb) -+{ -+ SiMustAnyLock(sb); -+ return au_sbi(sb)->si_bend; -+} -+ -+static inline unsigned int au_mntflags(struct super_block *sb) -+{ -+ SiMustAnyLock(sb); -+ return au_sbi(sb)->si_mntflags; -+} -+ -+static inline unsigned int au_sigen(struct super_block *sb) -+{ -+ SiMustAnyLock(sb); -+ return au_sbi(sb)->si_generation; -+} -+ -+static inline void au_ninodes_inc(struct super_block *sb) -+{ -+ atomic_long_inc(&au_sbi(sb)->si_ninodes); -+} -+ -+static inline void au_ninodes_dec(struct super_block *sb) -+{ -+ AuDebugOn(!atomic_long_read(&au_sbi(sb)->si_ninodes)); -+ atomic_long_dec(&au_sbi(sb)->si_ninodes); -+} -+ -+static inline void au_nfiles_inc(struct super_block *sb) -+{ -+ atomic_long_inc(&au_sbi(sb)->si_nfiles); -+} -+ -+static inline void au_nfiles_dec(struct super_block *sb) -+{ -+ AuDebugOn(!atomic_long_read(&au_sbi(sb)->si_nfiles)); -+ atomic_long_dec(&au_sbi(sb)->si_nfiles); -+} -+ -+static inline struct au_branch *au_sbr(struct super_block *sb, -+ aufs_bindex_t bindex) -+{ -+ SiMustAnyLock(sb); -+ return au_sbi(sb)->si_branch[0 + bindex]; -+} -+ -+static inline void au_xino_brid_set(struct super_block *sb, aufs_bindex_t brid) -+{ -+ SiMustWriteLock(sb); -+ au_sbi(sb)->si_xino_brid = brid; -+} -+ -+static inline aufs_bindex_t au_xino_brid(struct super_block *sb) -+{ -+ SiMustAnyLock(sb); -+ return au_sbi(sb)->si_xino_brid; -+} -+ -+#endif /* __KERNEL__ */ -+#endif /* __AUFS_SUPER_H__ */ -diff -Nur linux-2.6.37.orig/fs/aufs/sysaufs.c linux-2.6.37/fs/aufs/sysaufs.c ---- linux-2.6.37.orig/fs/aufs/sysaufs.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/sysaufs.c 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,107 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * sysfs interface and lifetime management -+ * they are necessary regardless sysfs is disabled. -+ */ -+ -+#include -+#include -+#include -+#include "aufs.h" -+ -+unsigned long sysaufs_si_mask; -+struct kset *sysaufs_kset; -+ -+#define AuSiAttr(_name) { \ -+ .attr = { .name = __stringify(_name), .mode = 0444 }, \ -+ .show = sysaufs_si_##_name, \ -+} -+ -+static struct sysaufs_si_attr sysaufs_si_attr_xi_path = AuSiAttr(xi_path); -+struct attribute *sysaufs_si_attrs[] = { -+ &sysaufs_si_attr_xi_path.attr, -+ NULL, -+}; -+ -+static const struct sysfs_ops au_sbi_ops = { -+ .show = sysaufs_si_show -+}; -+ -+static struct kobj_type au_sbi_ktype = { -+ .release = au_si_free, -+ .sysfs_ops = &au_sbi_ops, -+ .default_attrs = sysaufs_si_attrs -+}; -+ -+/* ---------------------------------------------------------------------- */ -+ -+int sysaufs_si_init(struct au_sbinfo *sbinfo) -+{ -+ int err; -+ -+ sbinfo->si_kobj.kset = sysaufs_kset; -+ /* cf. sysaufs_name() */ -+ err = kobject_init_and_add -+ (&sbinfo->si_kobj, &au_sbi_ktype, /*&sysaufs_kset->kobj*/NULL, -+ SysaufsSiNamePrefix "%lx", sysaufs_si_id(sbinfo)); -+ -+ dbgaufs_si_null(sbinfo); -+ if (!err) { -+ err = dbgaufs_si_init(sbinfo); -+ if (unlikely(err)) -+ kobject_put(&sbinfo->si_kobj); -+ } -+ return err; -+} -+ -+void sysaufs_fin(void) -+{ -+ dbgaufs_fin(); -+ sysfs_remove_group(&sysaufs_kset->kobj, sysaufs_attr_group); -+ kset_unregister(sysaufs_kset); -+} -+ -+int __init sysaufs_init(void) -+{ -+ int err; -+ -+ do { -+ get_random_bytes(&sysaufs_si_mask, sizeof(sysaufs_si_mask)); -+ } while (!sysaufs_si_mask); -+ -+ err = -EINVAL; -+ sysaufs_kset = kset_create_and_add(AUFS_NAME, NULL, fs_kobj); -+ if (unlikely(!sysaufs_kset)) -+ goto out; -+ err = PTR_ERR(sysaufs_kset); -+ if (IS_ERR(sysaufs_kset)) -+ goto out; -+ err = sysfs_create_group(&sysaufs_kset->kobj, sysaufs_attr_group); -+ if (unlikely(err)) { -+ kset_unregister(sysaufs_kset); -+ goto out; -+ } -+ -+ err = dbgaufs_init(); -+ if (unlikely(err)) -+ sysaufs_fin(); -+out: -+ return err; -+} -diff -Nur linux-2.6.37.orig/fs/aufs/sysaufs.h linux-2.6.37/fs/aufs/sysaufs.h ---- linux-2.6.37.orig/fs/aufs/sysaufs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/sysaufs.h 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,105 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * sysfs interface and mount lifetime management -+ */ -+ -+#ifndef __SYSAUFS_H__ -+#define __SYSAUFS_H__ -+ -+#ifdef __KERNEL__ -+ -+#include -+#include -+#include "module.h" -+ -+struct super_block; -+struct au_sbinfo; -+ -+struct sysaufs_si_attr { -+ struct attribute attr; -+ int (*show)(struct seq_file *seq, struct super_block *sb); -+}; -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* sysaufs.c */ -+extern unsigned long sysaufs_si_mask; -+extern struct kset *sysaufs_kset; -+extern struct attribute *sysaufs_si_attrs[]; -+int sysaufs_si_init(struct au_sbinfo *sbinfo); -+int __init sysaufs_init(void); -+void sysaufs_fin(void); -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* some people doesn't like to show a pointer in kernel */ -+static inline unsigned long sysaufs_si_id(struct au_sbinfo *sbinfo) -+{ -+ return sysaufs_si_mask ^ (unsigned long)sbinfo; -+} -+ -+#define SysaufsSiNamePrefix "si_" -+#define SysaufsSiNameLen (sizeof(SysaufsSiNamePrefix) + 16) -+static inline void sysaufs_name(struct au_sbinfo *sbinfo, char *name) -+{ -+ snprintf(name, SysaufsSiNameLen, SysaufsSiNamePrefix "%lx", -+ sysaufs_si_id(sbinfo)); -+} -+ -+struct au_branch; -+#ifdef CONFIG_SYSFS -+/* sysfs.c */ -+extern struct attribute_group *sysaufs_attr_group; -+ -+int sysaufs_si_xi_path(struct seq_file *seq, struct super_block *sb); -+ssize_t sysaufs_si_show(struct kobject *kobj, struct attribute *attr, -+ char *buf); -+ -+void sysaufs_br_init(struct au_branch *br); -+void sysaufs_brs_add(struct super_block *sb, aufs_bindex_t bindex); -+void sysaufs_brs_del(struct super_block *sb, aufs_bindex_t bindex); -+ -+#define sysaufs_brs_init() do {} while (0) -+ -+#else -+#define sysaufs_attr_group NULL -+ -+AuStubInt0(sysaufs_si_xi_path, struct seq_file *seq, struct super_block *sb) -+ -+static inline -+ssize_t sysaufs_si_show(struct kobject *kobj, struct attribute *attr, -+ char *buf) -+{ -+ return 0; -+} -+ -+AuStubVoid(sysaufs_br_init, struct au_branch *br) -+AuStubVoid(sysaufs_brs_add, struct super_block *sb, aufs_bindex_t bindex) -+AuStubVoid(sysaufs_brs_del, struct super_block *sb, aufs_bindex_t bindex) -+ -+static inline void sysaufs_brs_init(void) -+{ -+ sysaufs_brs = 0; -+} -+ -+#endif /* CONFIG_SYSFS */ -+ -+#endif /* __KERNEL__ */ -+#endif /* __SYSAUFS_H__ */ -diff -Nur linux-2.6.37.orig/fs/aufs/sysfs.c linux-2.6.37/fs/aufs/sysfs.c ---- linux-2.6.37.orig/fs/aufs/sysfs.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/sysfs.c 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,250 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * sysfs interface -+ */ -+ -+#include -+#include -+#include -+#include -+#include "aufs.h" -+ -+#ifdef CONFIG_AUFS_FS_MODULE -+/* this entry violates the "one line per file" policy of sysfs */ -+static ssize_t config_show(struct kobject *kobj, struct kobj_attribute *attr, -+ char *buf) -+{ -+ ssize_t err; -+ static char *conf = -+/* this file is generated at compiling */ -+#include "conf.str" -+ ; -+ -+ err = snprintf(buf, PAGE_SIZE, conf); -+ if (unlikely(err >= PAGE_SIZE)) -+ err = -EFBIG; -+ return err; -+} -+ -+static struct kobj_attribute au_config_attr = __ATTR_RO(config); -+#endif -+ -+static struct attribute *au_attr[] = { -+#ifdef CONFIG_AUFS_FS_MODULE -+ &au_config_attr.attr, -+#endif -+ NULL, /* need to NULL terminate the list of attributes */ -+}; -+ -+static struct attribute_group sysaufs_attr_group_body = { -+ .attrs = au_attr -+}; -+ -+struct attribute_group *sysaufs_attr_group = &sysaufs_attr_group_body; -+ -+/* ---------------------------------------------------------------------- */ -+ -+int sysaufs_si_xi_path(struct seq_file *seq, struct super_block *sb) -+{ -+ int err; -+ -+ SiMustAnyLock(sb); -+ -+ err = 0; -+ if (au_opt_test(au_mntflags(sb), XINO)) { -+ err = au_xino_path(seq, au_sbi(sb)->si_xib); -+ seq_putc(seq, '\n'); -+ } -+ return err; -+} -+ -+/* -+ * the lifetime of branch is independent from the entry under sysfs. -+ * sysfs handles the lifetime of the entry, and never call ->show() after it is -+ * unlinked. -+ */ -+static int sysaufs_si_br(struct seq_file *seq, struct super_block *sb, -+ aufs_bindex_t bindex) -+{ -+ struct path path; -+ struct dentry *root; -+ struct au_branch *br; -+ -+ AuDbg("b%d\n", bindex); -+ -+ root = sb->s_root; -+ di_read_lock_parent(root, !AuLock_IR); -+ br = au_sbr(sb, bindex); -+ path.mnt = br->br_mnt; -+ path.dentry = au_h_dptr(root, bindex); -+ au_seq_path(seq, &path); -+ di_read_unlock(root, !AuLock_IR); -+ seq_printf(seq, "=%s\n", au_optstr_br_perm(br->br_perm)); -+ return 0; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static struct seq_file *au_seq(char *p, ssize_t len) -+{ -+ struct seq_file *seq; -+ -+ seq = kzalloc(sizeof(*seq), GFP_NOFS); -+ if (seq) { -+ /* mutex_init(&seq.lock); */ -+ seq->buf = p; -+ seq->size = len; -+ return seq; /* success */ -+ } -+ -+ seq = ERR_PTR(-ENOMEM); -+ return seq; -+} -+ -+#define SysaufsBr_PREFIX "br" -+ -+/* todo: file size may exceed PAGE_SIZE */ -+ssize_t sysaufs_si_show(struct kobject *kobj, struct attribute *attr, -+ char *buf) -+{ -+ ssize_t err; -+ long l; -+ aufs_bindex_t bend; -+ struct au_sbinfo *sbinfo; -+ struct super_block *sb; -+ struct seq_file *seq; -+ char *name; -+ struct attribute **cattr; -+ -+ sbinfo = container_of(kobj, struct au_sbinfo, si_kobj); -+ sb = sbinfo->si_sb; -+ -+ /* -+ * prevent a race condition between sysfs and aufs. -+ * for instance, sysfs_file_read() calls sysfs_get_active_two() which -+ * prohibits maintaining the sysfs entries. -+ * hew we acquire read lock after sysfs_get_active_two(). -+ * on the other hand, the remount process may maintain the sysfs/aufs -+ * entries after acquiring write lock. -+ * it can cause a deadlock. -+ * simply we gave up processing read here. -+ */ -+ err = -EBUSY; -+ if (unlikely(!si_noflush_read_trylock(sb))) -+ goto out; -+ -+ seq = au_seq(buf, PAGE_SIZE); -+ err = PTR_ERR(seq); -+ if (IS_ERR(seq)) -+ goto out_unlock; -+ -+ name = (void *)attr->name; -+ cattr = sysaufs_si_attrs; -+ while (*cattr) { -+ if (!strcmp(name, (*cattr)->name)) { -+ err = container_of(*cattr, struct sysaufs_si_attr, attr) -+ ->show(seq, sb); -+ goto out_seq; -+ } -+ cattr++; -+ } -+ -+ bend = au_sbend(sb); -+ if (!strncmp(name, SysaufsBr_PREFIX, sizeof(SysaufsBr_PREFIX) - 1)) { -+ name += sizeof(SysaufsBr_PREFIX) - 1; -+ err = strict_strtol(name, 10, &l); -+ if (!err) { -+ if (l <= bend) -+ err = sysaufs_si_br(seq, sb, (aufs_bindex_t)l); -+ else -+ err = -ENOENT; -+ } -+ goto out_seq; -+ } -+ BUG(); -+ -+out_seq: -+ if (!err) { -+ err = seq->count; -+ /* sysfs limit */ -+ if (unlikely(err == PAGE_SIZE)) -+ err = -EFBIG; -+ } -+ kfree(seq); -+out_unlock: -+ si_read_unlock(sb); -+out: -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+void sysaufs_br_init(struct au_branch *br) -+{ -+ struct attribute *attr = &br->br_attr; -+ -+ sysfs_attr_init(attr); -+ attr->name = br->br_name; -+ attr->mode = S_IRUGO; -+} -+ -+void sysaufs_brs_del(struct super_block *sb, aufs_bindex_t bindex) -+{ -+ struct au_branch *br; -+ struct kobject *kobj; -+ aufs_bindex_t bend; -+ -+ dbgaufs_brs_del(sb, bindex); -+ -+ if (!sysaufs_brs) -+ return; -+ -+ kobj = &au_sbi(sb)->si_kobj; -+ bend = au_sbend(sb); -+ for (; bindex <= bend; bindex++) { -+ br = au_sbr(sb, bindex); -+ sysfs_remove_file(kobj, &br->br_attr); -+ } -+} -+ -+void sysaufs_brs_add(struct super_block *sb, aufs_bindex_t bindex) -+{ -+ int err; -+ aufs_bindex_t bend; -+ struct kobject *kobj; -+ struct au_branch *br; -+ -+ dbgaufs_brs_add(sb, bindex); -+ -+ if (!sysaufs_brs) -+ return; -+ -+ kobj = &au_sbi(sb)->si_kobj; -+ bend = au_sbend(sb); -+ for (; bindex <= bend; bindex++) { -+ br = au_sbr(sb, bindex); -+ snprintf(br->br_name, sizeof(br->br_name), SysaufsBr_PREFIX -+ "%d", bindex); -+ err = sysfs_create_file(kobj, &br->br_attr); -+ if (unlikely(err)) -+ pr_warning("failed %s under sysfs(%d)\n", -+ br->br_name, err); -+ } -+} -diff -Nur linux-2.6.37.orig/fs/aufs/sysrq.c linux-2.6.37/fs/aufs/sysrq.c ---- linux-2.6.37.orig/fs/aufs/sysrq.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/sysrq.c 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,148 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * magic sysrq hanlder -+ */ -+ -+#include -+#include -+#include -+/* #include */ -+#include -+#include "aufs.h" -+ -+/* ---------------------------------------------------------------------- */ -+ -+static void sysrq_sb(struct super_block *sb) -+{ -+ char *plevel; -+ struct au_sbinfo *sbinfo; -+ struct file *file; -+ -+ plevel = au_plevel; -+ au_plevel = KERN_WARNING; -+ -+ sbinfo = au_sbi(sb); -+ /* since we define pr_fmt, call printk directly */ -+ printk(KERN_WARNING "si=%lx\n", sysaufs_si_id(sbinfo)); -+ printk(KERN_WARNING AUFS_NAME ": superblock\n"); -+ au_dpri_sb(sb); -+ -+#if 0 -+ printk(KERN_WARNING AUFS_NAME ": root dentry\n"); -+ au_dpri_dentry(sb->s_root); -+ printk(KERN_WARNING AUFS_NAME ": root inode\n"); -+ au_dpri_inode(sb->s_root->d_inode); -+#endif -+ -+#if 0 -+ do { -+ int err, i, j, ndentry; -+ struct au_dcsub_pages dpages; -+ struct au_dpage *dpage; -+ -+ err = au_dpages_init(&dpages, GFP_ATOMIC); -+ if (unlikely(err)) -+ break; -+ err = au_dcsub_pages(&dpages, sb->s_root, NULL, NULL); -+ if (!err) -+ for (i = 0; i < dpages.ndpage; i++) { -+ dpage = dpages.dpages + i; -+ ndentry = dpage->ndentry; -+ for (j = 0; j < ndentry; j++) -+ au_dpri_dentry(dpage->dentries[j]); -+ } -+ au_dpages_free(&dpages); -+ } while (0); -+#endif -+ -+#if 1 -+ { -+ struct inode *i; -+ printk(KERN_WARNING AUFS_NAME ": isolated inode\n"); -+ spin_lock(&inode_lock); -+ list_for_each_entry(i, &sb->s_inodes, i_sb_list) -+ if (1 || list_empty(&i->i_dentry)) -+ au_dpri_inode(i); -+ spin_unlock(&inode_lock); -+ } -+#endif -+ printk(KERN_WARNING AUFS_NAME ": files\n"); -+ lg_global_lock(files_lglock); -+ do_file_list_for_each_entry(sb, file) { -+ umode_t mode; -+ mode = file->f_dentry->d_inode->i_mode; -+ if (!special_file(mode) || au_special_file(mode)) -+ au_dpri_file(file); -+ } while_file_list_for_each_entry; -+ lg_global_unlock(files_lglock); -+ printk(KERN_WARNING AUFS_NAME ": done\n"); -+ -+ au_plevel = plevel; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* module parameter */ -+static char *aufs_sysrq_key = "a"; -+module_param_named(sysrq, aufs_sysrq_key, charp, S_IRUGO); -+MODULE_PARM_DESC(sysrq, "MagicSysRq key for " AUFS_NAME); -+ -+static void au_sysrq(int key __maybe_unused) -+{ -+ struct au_sbinfo *sbinfo; -+ -+ lockdep_off(); -+ spin_lock(&au_sbilist.spin); -+ list_for_each_entry(sbinfo, &au_sbilist.head, si_list) -+ sysrq_sb(sbinfo->si_sb); -+ spin_unlock(&au_sbilist.spin); -+ lockdep_on(); -+} -+ -+static struct sysrq_key_op au_sysrq_op = { -+ .handler = au_sysrq, -+ .help_msg = "Aufs", -+ .action_msg = "Aufs", -+ .enable_mask = SYSRQ_ENABLE_DUMP -+}; -+ -+/* ---------------------------------------------------------------------- */ -+ -+int __init au_sysrq_init(void) -+{ -+ int err; -+ char key; -+ -+ err = -1; -+ key = *aufs_sysrq_key; -+ if ('a' <= key && key <= 'z') -+ err = register_sysrq_key(key, &au_sysrq_op); -+ if (unlikely(err)) -+ pr_err("err %d, sysrq=%c\n", err, key); -+ return err; -+} -+ -+void au_sysrq_fin(void) -+{ -+ int err; -+ err = unregister_sysrq_key(*aufs_sysrq_key, &au_sysrq_op); -+ if (unlikely(err)) -+ pr_err("err %d (ignored)\n", err); -+} -diff -Nur linux-2.6.37.orig/fs/aufs/vdir.c linux-2.6.37/fs/aufs/vdir.c ---- linux-2.6.37.orig/fs/aufs/vdir.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/vdir.c 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,886 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * virtual or vertical directory -+ */ -+ -+#include -+#include "aufs.h" -+ -+static unsigned int calc_size(int nlen) -+{ -+ return ALIGN(sizeof(struct au_vdir_de) + nlen, sizeof(ino_t)); -+} -+ -+static int set_deblk_end(union au_vdir_deblk_p *p, -+ union au_vdir_deblk_p *deblk_end) -+{ -+ if (calc_size(0) <= deblk_end->deblk - p->deblk) { -+ p->de->de_str.len = 0; -+ /* smp_mb(); */ -+ return 0; -+ } -+ return -1; /* error */ -+} -+ -+/* returns true or false */ -+static int is_deblk_end(union au_vdir_deblk_p *p, -+ union au_vdir_deblk_p *deblk_end) -+{ -+ if (calc_size(0) <= deblk_end->deblk - p->deblk) -+ return !p->de->de_str.len; -+ return 1; -+} -+ -+static unsigned char *last_deblk(struct au_vdir *vdir) -+{ -+ return vdir->vd_deblk[vdir->vd_nblk - 1]; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* estimate the apropriate size for name hash table */ -+unsigned int au_rdhash_est(loff_t sz) -+{ -+ unsigned int n; -+ -+ n = UINT_MAX; -+ sz >>= 10; -+ if (sz < n) -+ n = sz; -+ if (sz < AUFS_RDHASH_DEF) -+ n = AUFS_RDHASH_DEF; -+ /* pr_info("n %u\n", n); */ -+ return n; -+} -+ -+/* -+ * the allocated memory has to be freed by -+ * au_nhash_wh_free() or au_nhash_de_free(). -+ */ -+int au_nhash_alloc(struct au_nhash *nhash, unsigned int num_hash, gfp_t gfp) -+{ -+ struct hlist_head *head; -+ unsigned int u; -+ -+ head = kmalloc(sizeof(*nhash->nh_head) * num_hash, gfp); -+ if (head) { -+ nhash->nh_num = num_hash; -+ nhash->nh_head = head; -+ for (u = 0; u < num_hash; u++) -+ INIT_HLIST_HEAD(head++); -+ return 0; /* success */ -+ } -+ -+ return -ENOMEM; -+} -+ -+static void nhash_count(struct hlist_head *head) -+{ -+#if 0 -+ unsigned long n; -+ struct hlist_node *pos; -+ -+ n = 0; -+ hlist_for_each(pos, head) -+ n++; -+ pr_info("%lu\n", n); -+#endif -+} -+ -+static void au_nhash_wh_do_free(struct hlist_head *head) -+{ -+ struct au_vdir_wh *tpos; -+ struct hlist_node *pos, *node; -+ -+ hlist_for_each_entry_safe(tpos, pos, node, head, wh_hash) { -+ /* hlist_del(pos); */ -+ kfree(tpos); -+ } -+} -+ -+static void au_nhash_de_do_free(struct hlist_head *head) -+{ -+ struct au_vdir_dehstr *tpos; -+ struct hlist_node *pos, *node; -+ -+ hlist_for_each_entry_safe(tpos, pos, node, head, hash) { -+ /* hlist_del(pos); */ -+ au_cache_free_vdir_dehstr(tpos); -+ } -+} -+ -+static void au_nhash_do_free(struct au_nhash *nhash, -+ void (*free)(struct hlist_head *head)) -+{ -+ unsigned int n; -+ struct hlist_head *head; -+ -+ n = nhash->nh_num; -+ if (!n) -+ return; -+ -+ head = nhash->nh_head; -+ while (n-- > 0) { -+ nhash_count(head); -+ free(head++); -+ } -+ kfree(nhash->nh_head); -+} -+ -+void au_nhash_wh_free(struct au_nhash *whlist) -+{ -+ au_nhash_do_free(whlist, au_nhash_wh_do_free); -+} -+ -+static void au_nhash_de_free(struct au_nhash *delist) -+{ -+ au_nhash_do_free(delist, au_nhash_de_do_free); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+int au_nhash_test_longer_wh(struct au_nhash *whlist, aufs_bindex_t btgt, -+ int limit) -+{ -+ int num; -+ unsigned int u, n; -+ struct hlist_head *head; -+ struct au_vdir_wh *tpos; -+ struct hlist_node *pos; -+ -+ num = 0; -+ n = whlist->nh_num; -+ head = whlist->nh_head; -+ for (u = 0; u < n; u++, head++) -+ hlist_for_each_entry(tpos, pos, head, wh_hash) -+ if (tpos->wh_bindex == btgt && ++num > limit) -+ return 1; -+ return 0; -+} -+ -+static struct hlist_head *au_name_hash(struct au_nhash *nhash, -+ unsigned char *name, -+ unsigned int len) -+{ -+ unsigned int v; -+ /* const unsigned int magic_bit = 12; */ -+ -+ AuDebugOn(!nhash->nh_num || !nhash->nh_head); -+ -+ v = 0; -+ while (len--) -+ v += *name++; -+ /* v = hash_long(v, magic_bit); */ -+ v %= nhash->nh_num; -+ return nhash->nh_head + v; -+} -+ -+static int au_nhash_test_name(struct au_vdir_destr *str, const char *name, -+ int nlen) -+{ -+ return str->len == nlen && !memcmp(str->name, name, nlen); -+} -+ -+/* returns found or not */ -+int au_nhash_test_known_wh(struct au_nhash *whlist, char *name, int nlen) -+{ -+ struct hlist_head *head; -+ struct au_vdir_wh *tpos; -+ struct hlist_node *pos; -+ struct au_vdir_destr *str; -+ -+ head = au_name_hash(whlist, name, nlen); -+ hlist_for_each_entry(tpos, pos, head, wh_hash) { -+ str = &tpos->wh_str; -+ AuDbg("%.*s\n", str->len, str->name); -+ if (au_nhash_test_name(str, name, nlen)) -+ return 1; -+ } -+ return 0; -+} -+ -+/* returns found(true) or not */ -+static int test_known(struct au_nhash *delist, char *name, int nlen) -+{ -+ struct hlist_head *head; -+ struct au_vdir_dehstr *tpos; -+ struct hlist_node *pos; -+ struct au_vdir_destr *str; -+ -+ head = au_name_hash(delist, name, nlen); -+ hlist_for_each_entry(tpos, pos, head, hash) { -+ str = tpos->str; -+ AuDbg("%.*s\n", str->len, str->name); -+ if (au_nhash_test_name(str, name, nlen)) -+ return 1; -+ } -+ return 0; -+} -+ -+static void au_shwh_init_wh(struct au_vdir_wh *wh, ino_t ino, -+ unsigned char d_type) -+{ -+#ifdef CONFIG_AUFS_SHWH -+ wh->wh_ino = ino; -+ wh->wh_type = d_type; -+#endif -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+int au_nhash_append_wh(struct au_nhash *whlist, char *name, int nlen, ino_t ino, -+ unsigned int d_type, aufs_bindex_t bindex, -+ unsigned char shwh) -+{ -+ int err; -+ struct au_vdir_destr *str; -+ struct au_vdir_wh *wh; -+ -+ AuDbg("%.*s\n", nlen, name); -+ AuDebugOn(!whlist->nh_num || !whlist->nh_head); -+ -+ err = -ENOMEM; -+ wh = kmalloc(sizeof(*wh) + nlen, GFP_NOFS); -+ if (unlikely(!wh)) -+ goto out; -+ -+ err = 0; -+ wh->wh_bindex = bindex; -+ if (shwh) -+ au_shwh_init_wh(wh, ino, d_type); -+ str = &wh->wh_str; -+ str->len = nlen; -+ memcpy(str->name, name, nlen); -+ hlist_add_head(&wh->wh_hash, au_name_hash(whlist, name, nlen)); -+ /* smp_mb(); */ -+ -+out: -+ return err; -+} -+ -+static int append_deblk(struct au_vdir *vdir) -+{ -+ int err; -+ unsigned long ul; -+ const unsigned int deblk_sz = vdir->vd_deblk_sz; -+ union au_vdir_deblk_p p, deblk_end; -+ unsigned char **o; -+ -+ err = -ENOMEM; -+ o = krealloc(vdir->vd_deblk, sizeof(*o) * (vdir->vd_nblk + 1), -+ GFP_NOFS); -+ if (unlikely(!o)) -+ goto out; -+ -+ vdir->vd_deblk = o; -+ p.deblk = kmalloc(deblk_sz, GFP_NOFS); -+ if (p.deblk) { -+ ul = vdir->vd_nblk++; -+ vdir->vd_deblk[ul] = p.deblk; -+ vdir->vd_last.ul = ul; -+ vdir->vd_last.p.deblk = p.deblk; -+ deblk_end.deblk = p.deblk + deblk_sz; -+ err = set_deblk_end(&p, &deblk_end); -+ } -+ -+out: -+ return err; -+} -+ -+static int append_de(struct au_vdir *vdir, char *name, int nlen, ino_t ino, -+ unsigned int d_type, struct au_nhash *delist) -+{ -+ int err; -+ unsigned int sz; -+ const unsigned int deblk_sz = vdir->vd_deblk_sz; -+ union au_vdir_deblk_p p, *room, deblk_end; -+ struct au_vdir_dehstr *dehstr; -+ -+ p.deblk = last_deblk(vdir); -+ deblk_end.deblk = p.deblk + deblk_sz; -+ room = &vdir->vd_last.p; -+ AuDebugOn(room->deblk < p.deblk || deblk_end.deblk <= room->deblk -+ || !is_deblk_end(room, &deblk_end)); -+ -+ sz = calc_size(nlen); -+ if (unlikely(sz > deblk_end.deblk - room->deblk)) { -+ err = append_deblk(vdir); -+ if (unlikely(err)) -+ goto out; -+ -+ p.deblk = last_deblk(vdir); -+ deblk_end.deblk = p.deblk + deblk_sz; -+ /* smp_mb(); */ -+ AuDebugOn(room->deblk != p.deblk); -+ } -+ -+ err = -ENOMEM; -+ dehstr = au_cache_alloc_vdir_dehstr(); -+ if (unlikely(!dehstr)) -+ goto out; -+ -+ dehstr->str = &room->de->de_str; -+ hlist_add_head(&dehstr->hash, au_name_hash(delist, name, nlen)); -+ room->de->de_ino = ino; -+ room->de->de_type = d_type; -+ room->de->de_str.len = nlen; -+ memcpy(room->de->de_str.name, name, nlen); -+ -+ err = 0; -+ room->deblk += sz; -+ if (unlikely(set_deblk_end(room, &deblk_end))) -+ err = append_deblk(vdir); -+ /* smp_mb(); */ -+ -+out: -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+void au_vdir_free(struct au_vdir *vdir) -+{ -+ unsigned char **deblk; -+ -+ deblk = vdir->vd_deblk; -+ while (vdir->vd_nblk--) -+ kfree(*deblk++); -+ kfree(vdir->vd_deblk); -+ au_cache_free_vdir(vdir); -+} -+ -+static struct au_vdir *alloc_vdir(struct file *file) -+{ -+ struct au_vdir *vdir; -+ struct super_block *sb; -+ int err; -+ -+ sb = file->f_dentry->d_sb; -+ SiMustAnyLock(sb); -+ -+ err = -ENOMEM; -+ vdir = au_cache_alloc_vdir(); -+ if (unlikely(!vdir)) -+ goto out; -+ -+ vdir->vd_deblk = kzalloc(sizeof(*vdir->vd_deblk), GFP_NOFS); -+ if (unlikely(!vdir->vd_deblk)) -+ goto out_free; -+ -+ vdir->vd_deblk_sz = au_sbi(sb)->si_rdblk; -+ if (!vdir->vd_deblk_sz) { -+ /* estimate the apropriate size for deblk */ -+ vdir->vd_deblk_sz = au_dir_size(file, /*dentry*/NULL); -+ /* pr_info("vd_deblk_sz %u\n", vdir->vd_deblk_sz); */ -+ } -+ vdir->vd_nblk = 0; -+ vdir->vd_version = 0; -+ vdir->vd_jiffy = 0; -+ err = append_deblk(vdir); -+ if (!err) -+ return vdir; /* success */ -+ -+ kfree(vdir->vd_deblk); -+ -+out_free: -+ au_cache_free_vdir(vdir); -+out: -+ vdir = ERR_PTR(err); -+ return vdir; -+} -+ -+static int reinit_vdir(struct au_vdir *vdir) -+{ -+ int err; -+ union au_vdir_deblk_p p, deblk_end; -+ -+ while (vdir->vd_nblk > 1) { -+ kfree(vdir->vd_deblk[vdir->vd_nblk - 1]); -+ /* vdir->vd_deblk[vdir->vd_nblk - 1] = NULL; */ -+ vdir->vd_nblk--; -+ } -+ p.deblk = vdir->vd_deblk[0]; -+ deblk_end.deblk = p.deblk + vdir->vd_deblk_sz; -+ err = set_deblk_end(&p, &deblk_end); -+ /* keep vd_dblk_sz */ -+ vdir->vd_last.ul = 0; -+ vdir->vd_last.p.deblk = vdir->vd_deblk[0]; -+ vdir->vd_version = 0; -+ vdir->vd_jiffy = 0; -+ /* smp_mb(); */ -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+#define AuFillVdir_CALLED 1 -+#define AuFillVdir_WHABLE (1 << 1) -+#define AuFillVdir_SHWH (1 << 2) -+#define au_ftest_fillvdir(flags, name) ((flags) & AuFillVdir_##name) -+#define au_fset_fillvdir(flags, name) \ -+ do { (flags) |= AuFillVdir_##name; } while (0) -+#define au_fclr_fillvdir(flags, name) \ -+ do { (flags) &= ~AuFillVdir_##name; } while (0) -+ -+#ifndef CONFIG_AUFS_SHWH -+#undef AuFillVdir_SHWH -+#define AuFillVdir_SHWH 0 -+#endif -+ -+struct fillvdir_arg { -+ struct file *file; -+ struct au_vdir *vdir; -+ struct au_nhash delist; -+ struct au_nhash whlist; -+ aufs_bindex_t bindex; -+ unsigned int flags; -+ int err; -+}; -+ -+static int fillvdir(void *__arg, const char *__name, int nlen, -+ loff_t offset __maybe_unused, u64 h_ino, -+ unsigned int d_type) -+{ -+ struct fillvdir_arg *arg = __arg; -+ char *name = (void *)__name; -+ struct super_block *sb; -+ ino_t ino; -+ const unsigned char shwh = !!au_ftest_fillvdir(arg->flags, SHWH); -+ -+ arg->err = 0; -+ sb = arg->file->f_dentry->d_sb; -+ au_fset_fillvdir(arg->flags, CALLED); -+ /* smp_mb(); */ -+ if (nlen <= AUFS_WH_PFX_LEN -+ || memcmp(name, AUFS_WH_PFX, AUFS_WH_PFX_LEN)) { -+ if (test_known(&arg->delist, name, nlen) -+ || au_nhash_test_known_wh(&arg->whlist, name, nlen)) -+ goto out; /* already exists or whiteouted */ -+ -+ sb = arg->file->f_dentry->d_sb; -+ arg->err = au_ino(sb, arg->bindex, h_ino, d_type, &ino); -+ if (!arg->err) { -+ if (unlikely(nlen > AUFS_MAX_NAMELEN)) -+ d_type = DT_UNKNOWN; -+ arg->err = append_de(arg->vdir, name, nlen, ino, -+ d_type, &arg->delist); -+ } -+ } else if (au_ftest_fillvdir(arg->flags, WHABLE)) { -+ name += AUFS_WH_PFX_LEN; -+ nlen -= AUFS_WH_PFX_LEN; -+ if (au_nhash_test_known_wh(&arg->whlist, name, nlen)) -+ goto out; /* already whiteouted */ -+ -+ if (shwh) -+ arg->err = au_wh_ino(sb, arg->bindex, h_ino, d_type, -+ &ino); -+ if (!arg->err) { -+ if (nlen <= AUFS_MAX_NAMELEN + AUFS_WH_PFX_LEN) -+ d_type = DT_UNKNOWN; -+ arg->err = au_nhash_append_wh -+ (&arg->whlist, name, nlen, ino, d_type, -+ arg->bindex, shwh); -+ } -+ } -+ -+out: -+ if (!arg->err) -+ arg->vdir->vd_jiffy = jiffies; -+ /* smp_mb(); */ -+ AuTraceErr(arg->err); -+ return arg->err; -+} -+ -+static int au_handle_shwh(struct super_block *sb, struct au_vdir *vdir, -+ struct au_nhash *whlist, struct au_nhash *delist) -+{ -+#ifdef CONFIG_AUFS_SHWH -+ int err; -+ unsigned int nh, u; -+ struct hlist_head *head; -+ struct au_vdir_wh *tpos; -+ struct hlist_node *pos, *n; -+ char *p, *o; -+ struct au_vdir_destr *destr; -+ -+ AuDebugOn(!au_opt_test(au_mntflags(sb), SHWH)); -+ -+ err = -ENOMEM; -+ o = p = __getname_gfp(GFP_NOFS); -+ if (unlikely(!p)) -+ goto out; -+ -+ err = 0; -+ nh = whlist->nh_num; -+ memcpy(p, AUFS_WH_PFX, AUFS_WH_PFX_LEN); -+ p += AUFS_WH_PFX_LEN; -+ for (u = 0; u < nh; u++) { -+ head = whlist->nh_head + u; -+ hlist_for_each_entry_safe(tpos, pos, n, head, wh_hash) { -+ destr = &tpos->wh_str; -+ memcpy(p, destr->name, destr->len); -+ err = append_de(vdir, o, destr->len + AUFS_WH_PFX_LEN, -+ tpos->wh_ino, tpos->wh_type, delist); -+ if (unlikely(err)) -+ break; -+ } -+ } -+ -+ __putname(o); -+ -+out: -+ AuTraceErr(err); -+ return err; -+#else -+ return 0; -+#endif -+} -+ -+static int au_do_read_vdir(struct fillvdir_arg *arg) -+{ -+ int err; -+ unsigned int rdhash; -+ loff_t offset; -+ aufs_bindex_t bend, bindex, bstart; -+ unsigned char shwh; -+ struct file *hf, *file; -+ struct super_block *sb; -+ -+ file = arg->file; -+ sb = file->f_dentry->d_sb; -+ SiMustAnyLock(sb); -+ -+ rdhash = au_sbi(sb)->si_rdhash; -+ if (!rdhash) -+ rdhash = au_rdhash_est(au_dir_size(file, /*dentry*/NULL)); -+ err = au_nhash_alloc(&arg->delist, rdhash, GFP_NOFS); -+ if (unlikely(err)) -+ goto out; -+ err = au_nhash_alloc(&arg->whlist, rdhash, GFP_NOFS); -+ if (unlikely(err)) -+ goto out_delist; -+ -+ err = 0; -+ arg->flags = 0; -+ shwh = 0; -+ if (au_opt_test(au_mntflags(sb), SHWH)) { -+ shwh = 1; -+ au_fset_fillvdir(arg->flags, SHWH); -+ } -+ bstart = au_fbstart(file); -+ bend = au_fbend_dir(file); -+ for (bindex = bstart; !err && bindex <= bend; bindex++) { -+ hf = au_hf_dir(file, bindex); -+ if (!hf) -+ continue; -+ -+ offset = vfsub_llseek(hf, 0, SEEK_SET); -+ err = offset; -+ if (unlikely(offset)) -+ break; -+ -+ arg->bindex = bindex; -+ au_fclr_fillvdir(arg->flags, WHABLE); -+ if (shwh -+ || (bindex != bend -+ && au_br_whable(au_sbr_perm(sb, bindex)))) -+ au_fset_fillvdir(arg->flags, WHABLE); -+ do { -+ arg->err = 0; -+ au_fclr_fillvdir(arg->flags, CALLED); -+ /* smp_mb(); */ -+ err = vfsub_readdir(hf, fillvdir, arg); -+ if (err >= 0) -+ err = arg->err; -+ } while (!err && au_ftest_fillvdir(arg->flags, CALLED)); -+ } -+ -+ if (!err && shwh) -+ err = au_handle_shwh(sb, arg->vdir, &arg->whlist, &arg->delist); -+ -+ au_nhash_wh_free(&arg->whlist); -+ -+out_delist: -+ au_nhash_de_free(&arg->delist); -+out: -+ return err; -+} -+ -+static int read_vdir(struct file *file, int may_read) -+{ -+ int err; -+ unsigned long expire; -+ unsigned char do_read; -+ struct fillvdir_arg arg; -+ struct inode *inode; -+ struct au_vdir *vdir, *allocated; -+ -+ err = 0; -+ inode = file->f_dentry->d_inode; -+ IMustLock(inode); -+ SiMustAnyLock(inode->i_sb); -+ -+ allocated = NULL; -+ do_read = 0; -+ expire = au_sbi(inode->i_sb)->si_rdcache; -+ vdir = au_ivdir(inode); -+ if (!vdir) { -+ do_read = 1; -+ vdir = alloc_vdir(file); -+ err = PTR_ERR(vdir); -+ if (IS_ERR(vdir)) -+ goto out; -+ err = 0; -+ allocated = vdir; -+ } else if (may_read -+ && (inode->i_version != vdir->vd_version -+ || time_after(jiffies, vdir->vd_jiffy + expire))) { -+ do_read = 1; -+ err = reinit_vdir(vdir); -+ if (unlikely(err)) -+ goto out; -+ } -+ -+ if (!do_read) -+ return 0; /* success */ -+ -+ arg.file = file; -+ arg.vdir = vdir; -+ err = au_do_read_vdir(&arg); -+ if (!err) { -+ /* file->f_pos = 0; */ -+ vdir->vd_version = inode->i_version; -+ vdir->vd_last.ul = 0; -+ vdir->vd_last.p.deblk = vdir->vd_deblk[0]; -+ if (allocated) -+ au_set_ivdir(inode, allocated); -+ } else if (allocated) -+ au_vdir_free(allocated); -+ -+out: -+ return err; -+} -+ -+static int copy_vdir(struct au_vdir *tgt, struct au_vdir *src) -+{ -+ int err, rerr; -+ unsigned long ul, n; -+ const unsigned int deblk_sz = src->vd_deblk_sz; -+ -+ AuDebugOn(tgt->vd_nblk != 1); -+ -+ err = -ENOMEM; -+ if (tgt->vd_nblk < src->vd_nblk) { -+ unsigned char **p; -+ -+ p = krealloc(tgt->vd_deblk, sizeof(*p) * src->vd_nblk, -+ GFP_NOFS); -+ if (unlikely(!p)) -+ goto out; -+ tgt->vd_deblk = p; -+ } -+ -+ if (tgt->vd_deblk_sz != deblk_sz) { -+ unsigned char *p; -+ -+ tgt->vd_deblk_sz = deblk_sz; -+ p = krealloc(tgt->vd_deblk[0], deblk_sz, GFP_NOFS); -+ if (unlikely(!p)) -+ goto out; -+ tgt->vd_deblk[0] = p; -+ } -+ memcpy(tgt->vd_deblk[0], src->vd_deblk[0], deblk_sz); -+ tgt->vd_version = src->vd_version; -+ tgt->vd_jiffy = src->vd_jiffy; -+ -+ n = src->vd_nblk; -+ for (ul = 1; ul < n; ul++) { -+ tgt->vd_deblk[ul] = kmemdup(src->vd_deblk[ul], deblk_sz, -+ GFP_NOFS); -+ if (unlikely(!tgt->vd_deblk[ul])) -+ goto out; -+ tgt->vd_nblk++; -+ } -+ tgt->vd_nblk = n; -+ tgt->vd_last.ul = tgt->vd_last.ul; -+ tgt->vd_last.p.deblk = tgt->vd_deblk[tgt->vd_last.ul]; -+ tgt->vd_last.p.deblk += src->vd_last.p.deblk -+ - src->vd_deblk[src->vd_last.ul]; -+ /* smp_mb(); */ -+ return 0; /* success */ -+ -+out: -+ rerr = reinit_vdir(tgt); -+ BUG_ON(rerr); -+ return err; -+} -+ -+int au_vdir_init(struct file *file) -+{ -+ int err; -+ struct inode *inode; -+ struct au_vdir *vdir_cache, *allocated; -+ -+ err = read_vdir(file, !file->f_pos); -+ if (unlikely(err)) -+ goto out; -+ -+ allocated = NULL; -+ vdir_cache = au_fvdir_cache(file); -+ if (!vdir_cache) { -+ vdir_cache = alloc_vdir(file); -+ err = PTR_ERR(vdir_cache); -+ if (IS_ERR(vdir_cache)) -+ goto out; -+ allocated = vdir_cache; -+ } else if (!file->f_pos && vdir_cache->vd_version != file->f_version) { -+ err = reinit_vdir(vdir_cache); -+ if (unlikely(err)) -+ goto out; -+ } else -+ return 0; /* success */ -+ -+ inode = file->f_dentry->d_inode; -+ err = copy_vdir(vdir_cache, au_ivdir(inode)); -+ if (!err) { -+ file->f_version = inode->i_version; -+ if (allocated) -+ au_set_fvdir_cache(file, allocated); -+ } else if (allocated) -+ au_vdir_free(allocated); -+ -+out: -+ return err; -+} -+ -+static loff_t calc_offset(struct au_vdir *vdir) -+{ -+ loff_t offset; -+ union au_vdir_deblk_p p; -+ -+ p.deblk = vdir->vd_deblk[vdir->vd_last.ul]; -+ offset = vdir->vd_last.p.deblk - p.deblk; -+ offset += vdir->vd_deblk_sz * vdir->vd_last.ul; -+ return offset; -+} -+ -+/* returns true or false */ -+static int seek_vdir(struct file *file) -+{ -+ int valid; -+ unsigned int deblk_sz; -+ unsigned long ul, n; -+ loff_t offset; -+ union au_vdir_deblk_p p, deblk_end; -+ struct au_vdir *vdir_cache; -+ -+ valid = 1; -+ vdir_cache = au_fvdir_cache(file); -+ offset = calc_offset(vdir_cache); -+ AuDbg("offset %lld\n", offset); -+ if (file->f_pos == offset) -+ goto out; -+ -+ vdir_cache->vd_last.ul = 0; -+ vdir_cache->vd_last.p.deblk = vdir_cache->vd_deblk[0]; -+ if (!file->f_pos) -+ goto out; -+ -+ valid = 0; -+ deblk_sz = vdir_cache->vd_deblk_sz; -+ ul = div64_u64(file->f_pos, deblk_sz); -+ AuDbg("ul %lu\n", ul); -+ if (ul >= vdir_cache->vd_nblk) -+ goto out; -+ -+ n = vdir_cache->vd_nblk; -+ for (; ul < n; ul++) { -+ p.deblk = vdir_cache->vd_deblk[ul]; -+ deblk_end.deblk = p.deblk + deblk_sz; -+ offset = ul; -+ offset *= deblk_sz; -+ while (!is_deblk_end(&p, &deblk_end) && offset < file->f_pos) { -+ unsigned int l; -+ -+ l = calc_size(p.de->de_str.len); -+ offset += l; -+ p.deblk += l; -+ } -+ if (!is_deblk_end(&p, &deblk_end)) { -+ valid = 1; -+ vdir_cache->vd_last.ul = ul; -+ vdir_cache->vd_last.p = p; -+ break; -+ } -+ } -+ -+out: -+ /* smp_mb(); */ -+ AuTraceErr(!valid); -+ return valid; -+} -+ -+int au_vdir_fill_de(struct file *file, void *dirent, filldir_t filldir) -+{ -+ int err; -+ unsigned int l, deblk_sz; -+ union au_vdir_deblk_p deblk_end; -+ struct au_vdir *vdir_cache; -+ struct au_vdir_de *de; -+ -+ vdir_cache = au_fvdir_cache(file); -+ if (!seek_vdir(file)) -+ return 0; -+ -+ deblk_sz = vdir_cache->vd_deblk_sz; -+ while (1) { -+ deblk_end.deblk = vdir_cache->vd_deblk[vdir_cache->vd_last.ul]; -+ deblk_end.deblk += deblk_sz; -+ while (!is_deblk_end(&vdir_cache->vd_last.p, &deblk_end)) { -+ de = vdir_cache->vd_last.p.de; -+ AuDbg("%.*s, off%lld, i%lu, dt%d\n", -+ de->de_str.len, de->de_str.name, file->f_pos, -+ (unsigned long)de->de_ino, de->de_type); -+ err = filldir(dirent, de->de_str.name, de->de_str.len, -+ file->f_pos, de->de_ino, de->de_type); -+ if (unlikely(err)) { -+ AuTraceErr(err); -+ /* todo: ignore the error caused by udba? */ -+ /* return err; */ -+ return 0; -+ } -+ -+ l = calc_size(de->de_str.len); -+ vdir_cache->vd_last.p.deblk += l; -+ file->f_pos += l; -+ } -+ if (vdir_cache->vd_last.ul < vdir_cache->vd_nblk - 1) { -+ vdir_cache->vd_last.ul++; -+ vdir_cache->vd_last.p.deblk -+ = vdir_cache->vd_deblk[vdir_cache->vd_last.ul]; -+ file->f_pos = deblk_sz * vdir_cache->vd_last.ul; -+ continue; -+ } -+ break; -+ } -+ -+ /* smp_mb(); */ -+ return 0; -+} -diff -Nur linux-2.6.37.orig/fs/aufs/vfsub.c linux-2.6.37/fs/aufs/vfsub.c ---- linux-2.6.37.orig/fs/aufs/vfsub.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/vfsub.c 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,790 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * sub-routines for VFS -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include "aufs.h" -+ -+int vfsub_update_h_iattr(struct path *h_path, int *did) -+{ -+ int err; -+ struct kstat st; -+ struct super_block *h_sb; -+ -+ /* for remote fs, leave work for its getattr or d_revalidate */ -+ /* for bad i_attr fs, handle them in aufs_getattr() */ -+ /* still some fs may acquire i_mutex. we need to skip them */ -+ err = 0; -+ if (!did) -+ did = &err; -+ h_sb = h_path->dentry->d_sb; -+ *did = (!au_test_fs_remote(h_sb) && au_test_fs_refresh_iattr(h_sb)); -+ if (*did) -+ err = vfs_getattr(h_path->mnt, h_path->dentry, &st); -+ -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int au_conv_oflags(int flags) -+{ -+ int mask = 0; -+ -+#ifdef CONFIG_IMA -+ fmode_t fmode; -+ -+ /* mask = MAY_OPEN; */ -+ fmode = OPEN_FMODE(flags); -+ if (fmode & FMODE_READ) -+ mask |= MAY_READ; -+ if ((fmode & FMODE_WRITE) -+ || (flags & O_TRUNC)) -+ mask |= MAY_WRITE; -+ /* -+ * if (flags & O_APPEND) -+ * mask |= MAY_APPEND; -+ */ -+ if (flags & vfsub_fmode_to_uint(FMODE_EXEC)) -+ mask |= MAY_EXEC; -+ -+ AuDbg("flags 0x%x, mask 0x%x\n", flags, mask); -+#endif -+ -+ return mask; -+} -+ -+struct file *vfsub_dentry_open(struct path *path, int flags) -+{ -+ struct file *file; -+ int err; -+ -+ path_get(path); -+ file = dentry_open(path->dentry, path->mnt, -+ flags /* | vfsub_fmode_to_uint(FMODE_NONOTIFY) */, -+ current_cred()); -+ if (IS_ERR(file)) -+ goto out; -+ -+ err = ima_file_check(file, au_conv_oflags(flags)); -+ if (unlikely(err)) { -+ fput(file); -+ file = ERR_PTR(err); -+ } -+out: -+ return file; -+} -+ -+struct file *vfsub_filp_open(const char *path, int oflags, int mode) -+{ -+ struct file *file; -+ -+ file = filp_open(path, -+ oflags /* | vfsub_fmode_to_uint(FMODE_NONOTIFY) */, -+ mode); -+ if (IS_ERR(file)) -+ goto out; -+ vfsub_update_h_iattr(&file->f_path, /*did*/NULL); /*ignore*/ -+ -+out: -+ return file; -+} -+ -+int vfsub_kern_path(const char *name, unsigned int flags, struct path *path) -+{ -+ int err; -+ -+ err = kern_path(name, flags, path); -+ if (!err && path->dentry->d_inode) -+ vfsub_update_h_iattr(path, /*did*/NULL); /*ignore*/ -+ return err; -+} -+ -+struct dentry *vfsub_lookup_one_len(const char *name, struct dentry *parent, -+ int len) -+{ -+ struct path path = { -+ .mnt = NULL -+ }; -+ -+ /* VFS checks it too, but by WARN_ON_ONCE() */ -+ IMustLock(parent->d_inode); -+ -+ path.dentry = lookup_one_len(name, parent, len); -+ if (IS_ERR(path.dentry)) -+ goto out; -+ if (path.dentry->d_inode) -+ vfsub_update_h_iattr(&path, /*did*/NULL); /*ignore*/ -+ -+out: -+ AuTraceErrPtr(path.dentry); -+ return path.dentry; -+} -+ -+struct dentry *vfsub_lookup_hash(struct nameidata *nd) -+{ -+ struct path path = { -+ .mnt = nd->path.mnt -+ }; -+ -+ IMustLock(nd->path.dentry->d_inode); -+ -+ path.dentry = lookup_hash(nd); -+ if (IS_ERR(path.dentry)) -+ goto out; -+ if (path.dentry->d_inode) -+ vfsub_update_h_iattr(&path, /*did*/NULL); /*ignore*/ -+ -+out: -+ AuTraceErrPtr(path.dentry); -+ return path.dentry; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+struct dentry *vfsub_lock_rename(struct dentry *d1, struct au_hinode *hdir1, -+ struct dentry *d2, struct au_hinode *hdir2) -+{ -+ struct dentry *d; -+ -+ d = lock_rename(d1, d2); -+ au_hn_suspend(hdir1); -+ if (hdir1 != hdir2) -+ au_hn_suspend(hdir2); -+ -+ return d; -+} -+ -+void vfsub_unlock_rename(struct dentry *d1, struct au_hinode *hdir1, -+ struct dentry *d2, struct au_hinode *hdir2) -+{ -+ au_hn_resume(hdir1); -+ if (hdir1 != hdir2) -+ au_hn_resume(hdir2); -+ unlock_rename(d1, d2); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+int vfsub_create(struct inode *dir, struct path *path, int mode) -+{ -+ int err; -+ struct dentry *d; -+ -+ IMustLock(dir); -+ -+ d = path->dentry; -+ path->dentry = d->d_parent; -+ err = security_path_mknod(path, d, mode, 0); -+ path->dentry = d; -+ if (unlikely(err)) -+ goto out; -+ -+ if (au_test_fs_null_nd(dir->i_sb)) -+ err = vfs_create(dir, path->dentry, mode, NULL); -+ else { -+ struct nameidata h_nd; -+ -+ memset(&h_nd, 0, sizeof(h_nd)); -+ h_nd.flags = LOOKUP_CREATE; -+ h_nd.intent.open.flags = O_CREAT -+ | vfsub_fmode_to_uint(FMODE_READ); -+ h_nd.intent.open.create_mode = mode; -+ h_nd.path.dentry = path->dentry->d_parent; -+ h_nd.path.mnt = path->mnt; -+ path_get(&h_nd.path); -+ err = vfs_create(dir, path->dentry, mode, &h_nd); -+ path_put(&h_nd.path); -+ } -+ -+ if (!err) { -+ struct path tmp = *path; -+ int did; -+ -+ vfsub_update_h_iattr(&tmp, &did); -+ if (did) { -+ tmp.dentry = path->dentry->d_parent; -+ vfsub_update_h_iattr(&tmp, /*did*/NULL); -+ } -+ /*ignore*/ -+ } -+ -+out: -+ return err; -+} -+ -+int vfsub_symlink(struct inode *dir, struct path *path, const char *symname) -+{ -+ int err; -+ struct dentry *d; -+ -+ IMustLock(dir); -+ -+ d = path->dentry; -+ path->dentry = d->d_parent; -+ err = security_path_symlink(path, d, symname); -+ path->dentry = d; -+ if (unlikely(err)) -+ goto out; -+ -+ err = vfs_symlink(dir, path->dentry, symname); -+ if (!err) { -+ struct path tmp = *path; -+ int did; -+ -+ vfsub_update_h_iattr(&tmp, &did); -+ if (did) { -+ tmp.dentry = path->dentry->d_parent; -+ vfsub_update_h_iattr(&tmp, /*did*/NULL); -+ } -+ /*ignore*/ -+ } -+ -+out: -+ return err; -+} -+ -+int vfsub_mknod(struct inode *dir, struct path *path, int mode, dev_t dev) -+{ -+ int err; -+ struct dentry *d; -+ -+ IMustLock(dir); -+ -+ d = path->dentry; -+ path->dentry = d->d_parent; -+ err = security_path_mknod(path, d, mode, dev); -+ path->dentry = d; -+ if (unlikely(err)) -+ goto out; -+ -+ err = vfs_mknod(dir, path->dentry, mode, dev); -+ if (!err) { -+ struct path tmp = *path; -+ int did; -+ -+ vfsub_update_h_iattr(&tmp, &did); -+ if (did) { -+ tmp.dentry = path->dentry->d_parent; -+ vfsub_update_h_iattr(&tmp, /*did*/NULL); -+ } -+ /*ignore*/ -+ } -+ -+out: -+ return err; -+} -+ -+static int au_test_nlink(struct inode *inode) -+{ -+ const unsigned int link_max = UINT_MAX >> 1; /* rough margin */ -+ -+ if (!au_test_fs_no_limit_nlink(inode->i_sb) -+ || inode->i_nlink < link_max) -+ return 0; -+ return -EMLINK; -+} -+ -+int vfsub_link(struct dentry *src_dentry, struct inode *dir, struct path *path) -+{ -+ int err; -+ struct dentry *d; -+ -+ IMustLock(dir); -+ -+ err = au_test_nlink(src_dentry->d_inode); -+ if (unlikely(err)) -+ return err; -+ -+ d = path->dentry; -+ path->dentry = d->d_parent; -+ err = security_path_link(src_dentry, path, d); -+ path->dentry = d; -+ if (unlikely(err)) -+ goto out; -+ -+ err = vfs_link(src_dentry, dir, path->dentry); -+ if (!err) { -+ struct path tmp = *path; -+ int did; -+ -+ /* fuse has different memory inode for the same inumber */ -+ vfsub_update_h_iattr(&tmp, &did); -+ if (did) { -+ tmp.dentry = path->dentry->d_parent; -+ vfsub_update_h_iattr(&tmp, /*did*/NULL); -+ tmp.dentry = src_dentry; -+ vfsub_update_h_iattr(&tmp, /*did*/NULL); -+ } -+ /*ignore*/ -+ } -+ -+out: -+ return err; -+} -+ -+int vfsub_rename(struct inode *src_dir, struct dentry *src_dentry, -+ struct inode *dir, struct path *path) -+{ -+ int err; -+ struct path tmp = { -+ .mnt = path->mnt -+ }; -+ struct dentry *d; -+ -+ IMustLock(dir); -+ IMustLock(src_dir); -+ -+ d = path->dentry; -+ path->dentry = d->d_parent; -+ tmp.dentry = src_dentry->d_parent; -+ err = security_path_rename(&tmp, src_dentry, path, d); -+ path->dentry = d; -+ if (unlikely(err)) -+ goto out; -+ -+ err = vfs_rename(src_dir, src_dentry, dir, path->dentry); -+ if (!err) { -+ int did; -+ -+ tmp.dentry = d->d_parent; -+ vfsub_update_h_iattr(&tmp, &did); -+ if (did) { -+ tmp.dentry = src_dentry; -+ vfsub_update_h_iattr(&tmp, /*did*/NULL); -+ tmp.dentry = src_dentry->d_parent; -+ vfsub_update_h_iattr(&tmp, /*did*/NULL); -+ } -+ /*ignore*/ -+ } -+ -+out: -+ return err; -+} -+ -+int vfsub_mkdir(struct inode *dir, struct path *path, int mode) -+{ -+ int err; -+ struct dentry *d; -+ -+ IMustLock(dir); -+ -+ d = path->dentry; -+ path->dentry = d->d_parent; -+ err = security_path_mkdir(path, d, mode); -+ path->dentry = d; -+ if (unlikely(err)) -+ goto out; -+ -+ err = vfs_mkdir(dir, path->dentry, mode); -+ if (!err) { -+ struct path tmp = *path; -+ int did; -+ -+ vfsub_update_h_iattr(&tmp, &did); -+ if (did) { -+ tmp.dentry = path->dentry->d_parent; -+ vfsub_update_h_iattr(&tmp, /*did*/NULL); -+ } -+ /*ignore*/ -+ } -+ -+out: -+ return err; -+} -+ -+int vfsub_rmdir(struct inode *dir, struct path *path) -+{ -+ int err; -+ struct dentry *d; -+ -+ IMustLock(dir); -+ -+ d = path->dentry; -+ path->dentry = d->d_parent; -+ err = security_path_rmdir(path, d); -+ path->dentry = d; -+ if (unlikely(err)) -+ goto out; -+ -+ err = vfs_rmdir(dir, path->dentry); -+ if (!err) { -+ struct path tmp = { -+ .dentry = path->dentry->d_parent, -+ .mnt = path->mnt -+ }; -+ -+ vfsub_update_h_iattr(&tmp, /*did*/NULL); /*ignore*/ -+ } -+ -+out: -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+ssize_t vfsub_read_u(struct file *file, char __user *ubuf, size_t count, -+ loff_t *ppos) -+{ -+ ssize_t err; -+ -+ err = vfs_read(file, ubuf, count, ppos); -+ if (err >= 0) -+ vfsub_update_h_iattr(&file->f_path, /*did*/NULL); /*ignore*/ -+ return err; -+} -+ -+/* todo: kernel_read()? */ -+ssize_t vfsub_read_k(struct file *file, void *kbuf, size_t count, -+ loff_t *ppos) -+{ -+ ssize_t err; -+ mm_segment_t oldfs; -+ union { -+ void *k; -+ char __user *u; -+ } buf; -+ -+ buf.k = kbuf; -+ oldfs = get_fs(); -+ set_fs(KERNEL_DS); -+ err = vfsub_read_u(file, buf.u, count, ppos); -+ set_fs(oldfs); -+ return err; -+} -+ -+ssize_t vfsub_write_u(struct file *file, const char __user *ubuf, size_t count, -+ loff_t *ppos) -+{ -+ ssize_t err; -+ -+ err = vfs_write(file, ubuf, count, ppos); -+ if (err >= 0) -+ vfsub_update_h_iattr(&file->f_path, /*did*/NULL); /*ignore*/ -+ return err; -+} -+ -+ssize_t vfsub_write_k(struct file *file, void *kbuf, size_t count, loff_t *ppos) -+{ -+ ssize_t err; -+ mm_segment_t oldfs; -+ union { -+ void *k; -+ const char __user *u; -+ } buf; -+ -+ buf.k = kbuf; -+ oldfs = get_fs(); -+ set_fs(KERNEL_DS); -+ err = vfsub_write_u(file, buf.u, count, ppos); -+ set_fs(oldfs); -+ return err; -+} -+ -+int vfsub_flush(struct file *file, fl_owner_t id) -+{ -+ int err; -+ -+ err = 0; -+ if (file->f_op && file->f_op->flush) { -+ err = file->f_op->flush(file, id); -+ if (!err) -+ vfsub_update_h_iattr(&file->f_path, /*did*/NULL); -+ /*ignore*/ -+ } -+ return err; -+} -+ -+int vfsub_readdir(struct file *file, filldir_t filldir, void *arg) -+{ -+ int err; -+ -+ err = vfs_readdir(file, filldir, arg); -+ if (err >= 0) -+ vfsub_update_h_iattr(&file->f_path, /*did*/NULL); /*ignore*/ -+ return err; -+} -+ -+long vfsub_splice_to(struct file *in, loff_t *ppos, -+ struct pipe_inode_info *pipe, size_t len, -+ unsigned int flags) -+{ -+ long err; -+ -+ err = do_splice_to(in, ppos, pipe, len, flags); -+ file_accessed(in); -+ if (err >= 0) -+ vfsub_update_h_iattr(&in->f_path, /*did*/NULL); /*ignore*/ -+ return err; -+} -+ -+long vfsub_splice_from(struct pipe_inode_info *pipe, struct file *out, -+ loff_t *ppos, size_t len, unsigned int flags) -+{ -+ long err; -+ -+ err = do_splice_from(pipe, out, ppos, len, flags); -+ if (err >= 0) -+ vfsub_update_h_iattr(&out->f_path, /*did*/NULL); /*ignore*/ -+ return err; -+} -+ -+/* cf. open.c:do_sys_truncate() and do_sys_ftruncate() */ -+int vfsub_trunc(struct path *h_path, loff_t length, unsigned int attr, -+ struct file *h_file) -+{ -+ int err; -+ struct inode *h_inode; -+ -+ h_inode = h_path->dentry->d_inode; -+ if (!h_file) { -+ err = mnt_want_write(h_path->mnt); -+ if (err) -+ goto out; -+ err = inode_permission(h_inode, MAY_WRITE); -+ if (err) -+ goto out_mnt; -+ err = get_write_access(h_inode); -+ if (err) -+ goto out_mnt; -+ err = break_lease(h_inode, O_WRONLY); -+ if (err) -+ goto out_inode; -+ } -+ -+ err = locks_verify_truncate(h_inode, h_file, length); -+ if (!err) -+ err = security_path_truncate(h_path); -+ if (!err) -+ err = do_truncate(h_path->dentry, length, attr, h_file); -+ -+out_inode: -+ if (!h_file) -+ put_write_access(h_inode); -+out_mnt: -+ if (!h_file) -+ mnt_drop_write(h_path->mnt); -+out: -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+struct au_vfsub_mkdir_args { -+ int *errp; -+ struct inode *dir; -+ struct path *path; -+ int mode; -+}; -+ -+static void au_call_vfsub_mkdir(void *args) -+{ -+ struct au_vfsub_mkdir_args *a = args; -+ *a->errp = vfsub_mkdir(a->dir, a->path, a->mode); -+} -+ -+int vfsub_sio_mkdir(struct inode *dir, struct path *path, int mode) -+{ -+ int err, do_sio, wkq_err; -+ -+ do_sio = au_test_h_perm_sio(dir, MAY_EXEC | MAY_WRITE); -+ if (!do_sio) -+ err = vfsub_mkdir(dir, path, mode); -+ else { -+ struct au_vfsub_mkdir_args args = { -+ .errp = &err, -+ .dir = dir, -+ .path = path, -+ .mode = mode -+ }; -+ wkq_err = au_wkq_wait(au_call_vfsub_mkdir, &args); -+ if (unlikely(wkq_err)) -+ err = wkq_err; -+ } -+ -+ return err; -+} -+ -+struct au_vfsub_rmdir_args { -+ int *errp; -+ struct inode *dir; -+ struct path *path; -+}; -+ -+static void au_call_vfsub_rmdir(void *args) -+{ -+ struct au_vfsub_rmdir_args *a = args; -+ *a->errp = vfsub_rmdir(a->dir, a->path); -+} -+ -+int vfsub_sio_rmdir(struct inode *dir, struct path *path) -+{ -+ int err, do_sio, wkq_err; -+ -+ do_sio = au_test_h_perm_sio(dir, MAY_EXEC | MAY_WRITE); -+ if (!do_sio) -+ err = vfsub_rmdir(dir, path); -+ else { -+ struct au_vfsub_rmdir_args args = { -+ .errp = &err, -+ .dir = dir, -+ .path = path -+ }; -+ wkq_err = au_wkq_wait(au_call_vfsub_rmdir, &args); -+ if (unlikely(wkq_err)) -+ err = wkq_err; -+ } -+ -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+struct notify_change_args { -+ int *errp; -+ struct path *path; -+ struct iattr *ia; -+}; -+ -+static void call_notify_change(void *args) -+{ -+ struct notify_change_args *a = args; -+ struct inode *h_inode; -+ -+ h_inode = a->path->dentry->d_inode; -+ IMustLock(h_inode); -+ -+ *a->errp = -EPERM; -+ if (!IS_IMMUTABLE(h_inode) && !IS_APPEND(h_inode)) { -+ *a->errp = notify_change(a->path->dentry, a->ia); -+ if (!*a->errp) -+ vfsub_update_h_iattr(a->path, /*did*/NULL); /*ignore*/ -+ } -+ AuTraceErr(*a->errp); -+} -+ -+int vfsub_notify_change(struct path *path, struct iattr *ia) -+{ -+ int err; -+ struct notify_change_args args = { -+ .errp = &err, -+ .path = path, -+ .ia = ia -+ }; -+ -+ call_notify_change(&args); -+ -+ return err; -+} -+ -+int vfsub_sio_notify_change(struct path *path, struct iattr *ia) -+{ -+ int err, wkq_err; -+ struct notify_change_args args = { -+ .errp = &err, -+ .path = path, -+ .ia = ia -+ }; -+ -+ wkq_err = au_wkq_wait(call_notify_change, &args); -+ if (unlikely(wkq_err)) -+ err = wkq_err; -+ -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+struct unlink_args { -+ int *errp; -+ struct inode *dir; -+ struct path *path; -+}; -+ -+static void call_unlink(void *args) -+{ -+ struct unlink_args *a = args; -+ struct dentry *d = a->path->dentry; -+ struct inode *h_inode; -+ const int stop_sillyrename = (au_test_nfs(d->d_sb) -+ && atomic_read(&d->d_count) == 1); -+ -+ IMustLock(a->dir); -+ -+ a->path->dentry = d->d_parent; -+ *a->errp = security_path_unlink(a->path, d); -+ a->path->dentry = d; -+ if (unlikely(*a->errp)) -+ return; -+ -+ if (!stop_sillyrename) -+ dget(d); -+ h_inode = d->d_inode; -+ if (h_inode) -+ atomic_inc(&h_inode->i_count); -+ -+ *a->errp = vfs_unlink(a->dir, d); -+ if (!*a->errp) { -+ struct path tmp = { -+ .dentry = d->d_parent, -+ .mnt = a->path->mnt -+ }; -+ vfsub_update_h_iattr(&tmp, /*did*/NULL); /*ignore*/ -+ } -+ -+ if (!stop_sillyrename) -+ dput(d); -+ if (h_inode) -+ iput(h_inode); -+ -+ AuTraceErr(*a->errp); -+} -+ -+/* -+ * @dir: must be locked. -+ * @dentry: target dentry. -+ */ -+int vfsub_unlink(struct inode *dir, struct path *path, int force) -+{ -+ int err; -+ struct unlink_args args = { -+ .errp = &err, -+ .dir = dir, -+ .path = path -+ }; -+ -+ if (!force) -+ call_unlink(&args); -+ else { -+ int wkq_err; -+ -+ wkq_err = au_wkq_wait(call_unlink, &args); -+ if (unlikely(wkq_err)) -+ err = wkq_err; -+ } -+ -+ return err; -+} -diff -Nur linux-2.6.37.orig/fs/aufs/vfsub.h linux-2.6.37/fs/aufs/vfsub.h ---- linux-2.6.37.orig/fs/aufs/vfsub.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/vfsub.h 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,226 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * sub-routines for VFS -+ */ -+ -+#ifndef __AUFS_VFSUB_H__ -+#define __AUFS_VFSUB_H__ -+ -+#ifdef __KERNEL__ -+ -+#include -+#include -+#include "debug.h" -+ -+/* copied from linux/fs/internal.h */ -+DECLARE_BRLOCK(vfsmount_lock); -+extern void file_sb_list_del(struct file *f); -+ -+/* copied from linux/fs/file_table.c */ -+DECLARE_LGLOCK(files_lglock); -+#ifdef CONFIG_SMP -+/* -+ * These macros iterate all files on all CPUs for a given superblock. -+ * files_lglock must be held globally. -+ */ -+#define do_file_list_for_each_entry(__sb, __file) \ -+{ \ -+ int i; \ -+ for_each_possible_cpu(i) { \ -+ struct list_head *list; \ -+ list = per_cpu_ptr((__sb)->s_files, i); \ -+ list_for_each_entry((__file), list, f_u.fu_list) -+ -+#define while_file_list_for_each_entry \ -+ } \ -+} -+ -+#else -+ -+#define do_file_list_for_each_entry(__sb, __file) \ -+{ \ -+ struct list_head *list; \ -+ list = &(sb)->s_files; \ -+ list_for_each_entry((__file), list, f_u.fu_list) -+ -+#define while_file_list_for_each_entry \ -+} -+#endif -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* lock subclass for lower inode */ -+/* default MAX_LOCKDEP_SUBCLASSES(8) is not enough */ -+/* reduce? gave up. */ -+enum { -+ AuLsc_I_Begin = I_MUTEX_QUOTA, /* 4 */ -+ AuLsc_I_PARENT, /* lower inode, parent first */ -+ AuLsc_I_PARENT2, /* copyup dirs */ -+ AuLsc_I_PARENT3, /* copyup wh */ -+ AuLsc_I_CHILD, -+ AuLsc_I_CHILD2, -+ AuLsc_I_End -+}; -+ -+/* to debug easier, do not make them inlined functions */ -+#define MtxMustLock(mtx) AuDebugOn(!mutex_is_locked(mtx)) -+#define IMustLock(i) MtxMustLock(&(i)->i_mutex) -+ -+/* ---------------------------------------------------------------------- */ -+ -+static inline void vfsub_drop_nlink(struct inode *inode) -+{ -+ AuDebugOn(!inode->i_nlink); -+ drop_nlink(inode); -+} -+ -+static inline void vfsub_dead_dir(struct inode *inode) -+{ -+ AuDebugOn(!S_ISDIR(inode->i_mode)); -+ inode->i_flags |= S_DEAD; -+ clear_nlink(inode); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+int vfsub_update_h_iattr(struct path *h_path, int *did); -+struct file *vfsub_dentry_open(struct path *path, int flags); -+struct file *vfsub_filp_open(const char *path, int oflags, int mode); -+int vfsub_kern_path(const char *name, unsigned int flags, struct path *path); -+struct dentry *vfsub_lookup_one_len(const char *name, struct dentry *parent, -+ int len); -+struct dentry *vfsub_lookup_hash(struct nameidata *nd); -+ -+/* ---------------------------------------------------------------------- */ -+ -+struct au_hinode; -+struct dentry *vfsub_lock_rename(struct dentry *d1, struct au_hinode *hdir1, -+ struct dentry *d2, struct au_hinode *hdir2); -+void vfsub_unlock_rename(struct dentry *d1, struct au_hinode *hdir1, -+ struct dentry *d2, struct au_hinode *hdir2); -+ -+int vfsub_create(struct inode *dir, struct path *path, int mode); -+int vfsub_symlink(struct inode *dir, struct path *path, -+ const char *symname); -+int vfsub_mknod(struct inode *dir, struct path *path, int mode, dev_t dev); -+int vfsub_link(struct dentry *src_dentry, struct inode *dir, -+ struct path *path); -+int vfsub_rename(struct inode *src_hdir, struct dentry *src_dentry, -+ struct inode *hdir, struct path *path); -+int vfsub_mkdir(struct inode *dir, struct path *path, int mode); -+int vfsub_rmdir(struct inode *dir, struct path *path); -+ -+/* ---------------------------------------------------------------------- */ -+ -+ssize_t vfsub_read_u(struct file *file, char __user *ubuf, size_t count, -+ loff_t *ppos); -+ssize_t vfsub_read_k(struct file *file, void *kbuf, size_t count, -+ loff_t *ppos); -+ssize_t vfsub_write_u(struct file *file, const char __user *ubuf, size_t count, -+ loff_t *ppos); -+ssize_t vfsub_write_k(struct file *file, void *kbuf, size_t count, -+ loff_t *ppos); -+int vfsub_flush(struct file *file, fl_owner_t id); -+int vfsub_readdir(struct file *file, filldir_t filldir, void *arg); -+ -+static inline unsigned int vfsub_file_flags(struct file *file) -+{ -+ unsigned int flags; -+ -+ spin_lock(&file->f_lock); -+ flags = file->f_flags; -+ spin_unlock(&file->f_lock); -+ -+ return flags; -+} -+ -+static inline void vfsub_file_accessed(struct file *h_file) -+{ -+ file_accessed(h_file); -+ vfsub_update_h_iattr(&h_file->f_path, /*did*/NULL); /*ignore*/ -+} -+ -+static inline void vfsub_touch_atime(struct vfsmount *h_mnt, -+ struct dentry *h_dentry) -+{ -+ struct path h_path = { -+ .dentry = h_dentry, -+ .mnt = h_mnt -+ }; -+ touch_atime(h_mnt, h_dentry); -+ vfsub_update_h_iattr(&h_path, /*did*/NULL); /*ignore*/ -+} -+ -+long vfsub_splice_to(struct file *in, loff_t *ppos, -+ struct pipe_inode_info *pipe, size_t len, -+ unsigned int flags); -+long vfsub_splice_from(struct pipe_inode_info *pipe, struct file *out, -+ loff_t *ppos, size_t len, unsigned int flags); -+int vfsub_trunc(struct path *h_path, loff_t length, unsigned int attr, -+ struct file *h_file); -+ -+/* ---------------------------------------------------------------------- */ -+ -+static inline loff_t vfsub_llseek(struct file *file, loff_t offset, int origin) -+{ -+ loff_t err; -+ -+ err = vfs_llseek(file, offset, origin); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* dirty workaround for strict type of fmode_t */ -+union vfsub_fmu { -+ fmode_t fm; -+ unsigned int ui; -+}; -+ -+static inline unsigned int vfsub_fmode_to_uint(fmode_t fm) -+{ -+ union vfsub_fmu u = { -+ .fm = fm -+ }; -+ -+ BUILD_BUG_ON(sizeof(u.fm) != sizeof(u.ui)); -+ -+ return u.ui; -+} -+ -+static inline fmode_t vfsub_uint_to_fmode(unsigned int ui) -+{ -+ union vfsub_fmu u = { -+ .ui = ui -+ }; -+ -+ return u.fm; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+int vfsub_sio_mkdir(struct inode *dir, struct path *path, int mode); -+int vfsub_sio_rmdir(struct inode *dir, struct path *path); -+int vfsub_sio_notify_change(struct path *path, struct iattr *ia); -+int vfsub_notify_change(struct path *path, struct iattr *ia); -+int vfsub_unlink(struct inode *dir, struct path *path, int force); -+ -+#endif /* __KERNEL__ */ -+#endif /* __AUFS_VFSUB_H__ */ -diff -Nur linux-2.6.37.orig/fs/aufs/wbr_policy.c linux-2.6.37/fs/aufs/wbr_policy.c ---- linux-2.6.37.orig/fs/aufs/wbr_policy.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/wbr_policy.c 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,700 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * policies for selecting one among multiple writable branches -+ */ -+ -+#include -+#include "aufs.h" -+ -+/* subset of cpup_attr() */ -+static noinline_for_stack -+int au_cpdown_attr(struct path *h_path, struct dentry *h_src) -+{ -+ int err, sbits; -+ struct iattr ia; -+ struct inode *h_isrc; -+ -+ h_isrc = h_src->d_inode; -+ ia.ia_valid = ATTR_FORCE | ATTR_MODE | ATTR_UID | ATTR_GID; -+ ia.ia_mode = h_isrc->i_mode; -+ ia.ia_uid = h_isrc->i_uid; -+ ia.ia_gid = h_isrc->i_gid; -+ sbits = !!(ia.ia_mode & (S_ISUID | S_ISGID)); -+ au_cpup_attr_flags(h_path->dentry->d_inode, h_isrc); -+ err = vfsub_sio_notify_change(h_path, &ia); -+ -+ /* is this nfs only? */ -+ if (!err && sbits && au_test_nfs(h_path->dentry->d_sb)) { -+ ia.ia_valid = ATTR_FORCE | ATTR_MODE; -+ ia.ia_mode = h_isrc->i_mode; -+ err = vfsub_sio_notify_change(h_path, &ia); -+ } -+ -+ return err; -+} -+ -+#define AuCpdown_PARENT_OPQ 1 -+#define AuCpdown_WHED (1 << 1) -+#define AuCpdown_MADE_DIR (1 << 2) -+#define AuCpdown_DIROPQ (1 << 3) -+#define au_ftest_cpdown(flags, name) ((flags) & AuCpdown_##name) -+#define au_fset_cpdown(flags, name) \ -+ do { (flags) |= AuCpdown_##name; } while (0) -+#define au_fclr_cpdown(flags, name) \ -+ do { (flags) &= ~AuCpdown_##name; } while (0) -+ -+struct au_cpdown_dir_args { -+ struct dentry *parent; -+ unsigned int flags; -+}; -+ -+static int au_cpdown_dir_opq(struct dentry *dentry, aufs_bindex_t bdst, -+ struct au_cpdown_dir_args *a) -+{ -+ int err; -+ struct dentry *opq_dentry; -+ -+ opq_dentry = au_diropq_create(dentry, bdst); -+ err = PTR_ERR(opq_dentry); -+ if (IS_ERR(opq_dentry)) -+ goto out; -+ dput(opq_dentry); -+ au_fset_cpdown(a->flags, DIROPQ); -+ -+out: -+ return err; -+} -+ -+static int au_cpdown_dir_wh(struct dentry *dentry, struct dentry *h_parent, -+ struct inode *dir, aufs_bindex_t bdst) -+{ -+ int err; -+ struct path h_path; -+ struct au_branch *br; -+ -+ br = au_sbr(dentry->d_sb, bdst); -+ h_path.dentry = au_wh_lkup(h_parent, &dentry->d_name, br); -+ err = PTR_ERR(h_path.dentry); -+ if (IS_ERR(h_path.dentry)) -+ goto out; -+ -+ err = 0; -+ if (h_path.dentry->d_inode) { -+ h_path.mnt = br->br_mnt; -+ err = au_wh_unlink_dentry(au_h_iptr(dir, bdst), &h_path, -+ dentry); -+ } -+ dput(h_path.dentry); -+ -+out: -+ return err; -+} -+ -+static int au_cpdown_dir(struct dentry *dentry, aufs_bindex_t bdst, -+ struct dentry *h_parent, void *arg) -+{ -+ int err, rerr; -+ aufs_bindex_t bopq, bstart; -+ struct path h_path; -+ struct dentry *parent; -+ struct inode *h_dir, *h_inode, *inode, *dir; -+ struct au_cpdown_dir_args *args = arg; -+ -+ bstart = au_dbstart(dentry); -+ /* dentry is di-locked */ -+ parent = dget_parent(dentry); -+ dir = parent->d_inode; -+ h_dir = h_parent->d_inode; -+ AuDebugOn(h_dir != au_h_iptr(dir, bdst)); -+ IMustLock(h_dir); -+ -+ err = au_lkup_neg(dentry, bdst); -+ if (unlikely(err < 0)) -+ goto out; -+ h_path.dentry = au_h_dptr(dentry, bdst); -+ h_path.mnt = au_sbr_mnt(dentry->d_sb, bdst); -+ err = vfsub_sio_mkdir(au_h_iptr(dir, bdst), &h_path, -+ S_IRWXU | S_IRUGO | S_IXUGO); -+ if (unlikely(err)) -+ goto out_put; -+ au_fset_cpdown(args->flags, MADE_DIR); -+ -+ bopq = au_dbdiropq(dentry); -+ au_fclr_cpdown(args->flags, WHED); -+ au_fclr_cpdown(args->flags, DIROPQ); -+ if (au_dbwh(dentry) == bdst) -+ au_fset_cpdown(args->flags, WHED); -+ if (!au_ftest_cpdown(args->flags, PARENT_OPQ) && bopq <= bdst) -+ au_fset_cpdown(args->flags, PARENT_OPQ); -+ h_inode = h_path.dentry->d_inode; -+ mutex_lock_nested(&h_inode->i_mutex, AuLsc_I_CHILD); -+ if (au_ftest_cpdown(args->flags, WHED)) { -+ err = au_cpdown_dir_opq(dentry, bdst, args); -+ if (unlikely(err)) { -+ mutex_unlock(&h_inode->i_mutex); -+ goto out_dir; -+ } -+ } -+ -+ err = au_cpdown_attr(&h_path, au_h_dptr(dentry, bstart)); -+ mutex_unlock(&h_inode->i_mutex); -+ if (unlikely(err)) -+ goto out_opq; -+ -+ if (au_ftest_cpdown(args->flags, WHED)) { -+ err = au_cpdown_dir_wh(dentry, h_parent, dir, bdst); -+ if (unlikely(err)) -+ goto out_opq; -+ } -+ -+ inode = dentry->d_inode; -+ if (au_ibend(inode) < bdst) -+ au_set_ibend(inode, bdst); -+ au_set_h_iptr(inode, bdst, au_igrab(h_inode), -+ au_hi_flags(inode, /*isdir*/1)); -+ goto out; /* success */ -+ -+ /* revert */ -+out_opq: -+ if (au_ftest_cpdown(args->flags, DIROPQ)) { -+ mutex_lock_nested(&h_inode->i_mutex, AuLsc_I_CHILD); -+ rerr = au_diropq_remove(dentry, bdst); -+ mutex_unlock(&h_inode->i_mutex); -+ if (unlikely(rerr)) { -+ AuIOErr("failed removing diropq for %.*s b%d (%d)\n", -+ AuDLNPair(dentry), bdst, rerr); -+ err = -EIO; -+ goto out; -+ } -+ } -+out_dir: -+ if (au_ftest_cpdown(args->flags, MADE_DIR)) { -+ rerr = vfsub_sio_rmdir(au_h_iptr(dir, bdst), &h_path); -+ if (unlikely(rerr)) { -+ AuIOErr("failed removing %.*s b%d (%d)\n", -+ AuDLNPair(dentry), bdst, rerr); -+ err = -EIO; -+ } -+ } -+out_put: -+ au_set_h_dptr(dentry, bdst, NULL); -+ if (au_dbend(dentry) == bdst) -+ au_update_dbend(dentry); -+out: -+ dput(parent); -+ return err; -+} -+ -+int au_cpdown_dirs(struct dentry *dentry, aufs_bindex_t bdst) -+{ -+ int err; -+ struct au_cpdown_dir_args args = { -+ .parent = dget_parent(dentry), -+ .flags = 0 -+ }; -+ -+ err = au_cp_dirs(dentry, bdst, au_cpdown_dir, &args); -+ dput(args.parent); -+ -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* policies for create */ -+ -+static int au_wbr_nonopq(struct dentry *dentry, aufs_bindex_t bindex) -+{ -+ int err, i, j, ndentry; -+ aufs_bindex_t bopq; -+ struct au_dcsub_pages dpages; -+ struct au_dpage *dpage; -+ struct dentry **dentries, *parent, *d; -+ -+ err = au_dpages_init(&dpages, GFP_NOFS); -+ if (unlikely(err)) -+ goto out; -+ parent = dget_parent(dentry); -+ err = au_dcsub_pages_rev_aufs(&dpages, parent, /*do_include*/0); -+ if (unlikely(err)) -+ goto out_free; -+ -+ err = bindex; -+ for (i = 0; i < dpages.ndpage; i++) { -+ dpage = dpages.dpages + i; -+ dentries = dpage->dentries; -+ ndentry = dpage->ndentry; -+ for (j = 0; j < ndentry; j++) { -+ d = dentries[j]; -+ di_read_lock_parent2(d, !AuLock_IR); -+ bopq = au_dbdiropq(d); -+ di_read_unlock(d, !AuLock_IR); -+ if (bopq >= 0 && bopq < err) -+ err = bopq; -+ } -+ } -+ -+out_free: -+ dput(parent); -+ au_dpages_free(&dpages); -+out: -+ return err; -+} -+ -+static int au_wbr_bu(struct super_block *sb, aufs_bindex_t bindex) -+{ -+ for (; bindex >= 0; bindex--) -+ if (!au_br_rdonly(au_sbr(sb, bindex))) -+ return bindex; -+ return -EROFS; -+} -+ -+/* top down parent */ -+static int au_wbr_create_tdp(struct dentry *dentry, int isdir __maybe_unused) -+{ -+ int err; -+ aufs_bindex_t bstart, bindex; -+ struct super_block *sb; -+ struct dentry *parent, *h_parent; -+ -+ sb = dentry->d_sb; -+ bstart = au_dbstart(dentry); -+ err = bstart; -+ if (!au_br_rdonly(au_sbr(sb, bstart))) -+ goto out; -+ -+ err = -EROFS; -+ parent = dget_parent(dentry); -+ for (bindex = au_dbstart(parent); bindex < bstart; bindex++) { -+ h_parent = au_h_dptr(parent, bindex); -+ if (!h_parent || !h_parent->d_inode) -+ continue; -+ -+ if (!au_br_rdonly(au_sbr(sb, bindex))) { -+ err = bindex; -+ break; -+ } -+ } -+ dput(parent); -+ -+ /* bottom up here */ -+ if (unlikely(err < 0)) { -+ err = au_wbr_bu(sb, bstart - 1); -+ if (err >= 0) -+ err = au_wbr_nonopq(dentry, err); -+ } -+ -+out: -+ AuDbg("b%d\n", err); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* an exception for the policy other than tdp */ -+static int au_wbr_create_exp(struct dentry *dentry) -+{ -+ int err; -+ aufs_bindex_t bwh, bdiropq; -+ struct dentry *parent; -+ -+ err = -1; -+ bwh = au_dbwh(dentry); -+ parent = dget_parent(dentry); -+ bdiropq = au_dbdiropq(parent); -+ if (bwh >= 0) { -+ if (bdiropq >= 0) -+ err = min(bdiropq, bwh); -+ else -+ err = bwh; -+ AuDbg("%d\n", err); -+ } else if (bdiropq >= 0) { -+ err = bdiropq; -+ AuDbg("%d\n", err); -+ } -+ dput(parent); -+ -+ if (err >= 0) -+ err = au_wbr_nonopq(dentry, err); -+ -+ if (err >= 0 && au_br_rdonly(au_sbr(dentry->d_sb, err))) -+ err = -1; -+ -+ AuDbg("%d\n", err); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* round robin */ -+static int au_wbr_create_init_rr(struct super_block *sb) -+{ -+ int err; -+ -+ err = au_wbr_bu(sb, au_sbend(sb)); -+ atomic_set(&au_sbi(sb)->si_wbr_rr_next, -err); /* less important */ -+ /* smp_mb(); */ -+ -+ AuDbg("b%d\n", err); -+ return err; -+} -+ -+static int au_wbr_create_rr(struct dentry *dentry, int isdir) -+{ -+ int err, nbr; -+ unsigned int u; -+ aufs_bindex_t bindex, bend; -+ struct super_block *sb; -+ atomic_t *next; -+ -+ err = au_wbr_create_exp(dentry); -+ if (err >= 0) -+ goto out; -+ -+ sb = dentry->d_sb; -+ next = &au_sbi(sb)->si_wbr_rr_next; -+ bend = au_sbend(sb); -+ nbr = bend + 1; -+ for (bindex = 0; bindex <= bend; bindex++) { -+ if (!isdir) { -+ err = atomic_dec_return(next) + 1; -+ /* modulo for 0 is meaningless */ -+ if (unlikely(!err)) -+ err = atomic_dec_return(next) + 1; -+ } else -+ err = atomic_read(next); -+ AuDbg("%d\n", err); -+ u = err; -+ err = u % nbr; -+ AuDbg("%d\n", err); -+ if (!au_br_rdonly(au_sbr(sb, err))) -+ break; -+ err = -EROFS; -+ } -+ -+ if (err >= 0) -+ err = au_wbr_nonopq(dentry, err); -+ -+out: -+ AuDbg("%d\n", err); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* most free space */ -+static void au_mfs(struct dentry *dentry) -+{ -+ struct super_block *sb; -+ struct au_branch *br; -+ struct au_wbr_mfs *mfs; -+ aufs_bindex_t bindex, bend; -+ int err; -+ unsigned long long b, bavail; -+ struct path h_path; -+ /* reduce the stack usage */ -+ struct kstatfs *st; -+ -+ st = kmalloc(sizeof(*st), GFP_NOFS); -+ if (unlikely(!st)) { -+ AuWarn1("failed updating mfs(%d), ignored\n", -ENOMEM); -+ return; -+ } -+ -+ bavail = 0; -+ sb = dentry->d_sb; -+ mfs = &au_sbi(sb)->si_wbr_mfs; -+ MtxMustLock(&mfs->mfs_lock); -+ mfs->mfs_bindex = -EROFS; -+ mfs->mfsrr_bytes = 0; -+ bend = au_sbend(sb); -+ for (bindex = 0; bindex <= bend; bindex++) { -+ br = au_sbr(sb, bindex); -+ if (au_br_rdonly(br)) -+ continue; -+ -+ /* sb->s_root for NFS is unreliable */ -+ h_path.mnt = br->br_mnt; -+ h_path.dentry = h_path.mnt->mnt_root; -+ err = vfs_statfs(&h_path, st); -+ if (unlikely(err)) { -+ AuWarn1("failed statfs, b%d, %d\n", bindex, err); -+ continue; -+ } -+ -+ /* when the available size is equal, select the lower one */ -+ BUILD_BUG_ON(sizeof(b) < sizeof(st->f_bavail) -+ || sizeof(b) < sizeof(st->f_bsize)); -+ b = st->f_bavail * st->f_bsize; -+ br->br_wbr->wbr_bytes = b; -+ if (b >= bavail) { -+ bavail = b; -+ mfs->mfs_bindex = bindex; -+ mfs->mfs_jiffy = jiffies; -+ } -+ } -+ -+ mfs->mfsrr_bytes = bavail; -+ AuDbg("b%d\n", mfs->mfs_bindex); -+ kfree(st); -+} -+ -+static int au_wbr_create_mfs(struct dentry *dentry, int isdir __maybe_unused) -+{ -+ int err; -+ struct super_block *sb; -+ struct au_wbr_mfs *mfs; -+ -+ err = au_wbr_create_exp(dentry); -+ if (err >= 0) -+ goto out; -+ -+ sb = dentry->d_sb; -+ mfs = &au_sbi(sb)->si_wbr_mfs; -+ mutex_lock(&mfs->mfs_lock); -+ if (time_after(jiffies, mfs->mfs_jiffy + mfs->mfs_expire) -+ || mfs->mfs_bindex < 0 -+ || au_br_rdonly(au_sbr(sb, mfs->mfs_bindex))) -+ au_mfs(dentry); -+ mutex_unlock(&mfs->mfs_lock); -+ err = mfs->mfs_bindex; -+ -+ if (err >= 0) -+ err = au_wbr_nonopq(dentry, err); -+ -+out: -+ AuDbg("b%d\n", err); -+ return err; -+} -+ -+static int au_wbr_create_init_mfs(struct super_block *sb) -+{ -+ struct au_wbr_mfs *mfs; -+ -+ mfs = &au_sbi(sb)->si_wbr_mfs; -+ mutex_init(&mfs->mfs_lock); -+ mfs->mfs_jiffy = 0; -+ mfs->mfs_bindex = -EROFS; -+ -+ return 0; -+} -+ -+static int au_wbr_create_fin_mfs(struct super_block *sb __maybe_unused) -+{ -+ mutex_destroy(&au_sbi(sb)->si_wbr_mfs.mfs_lock); -+ return 0; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* most free space and then round robin */ -+static int au_wbr_create_mfsrr(struct dentry *dentry, int isdir) -+{ -+ int err; -+ struct au_wbr_mfs *mfs; -+ -+ err = au_wbr_create_mfs(dentry, isdir); -+ if (err >= 0) { -+ mfs = &au_sbi(dentry->d_sb)->si_wbr_mfs; -+ mutex_lock(&mfs->mfs_lock); -+ if (mfs->mfsrr_bytes < mfs->mfsrr_watermark) -+ err = au_wbr_create_rr(dentry, isdir); -+ mutex_unlock(&mfs->mfs_lock); -+ } -+ -+ AuDbg("b%d\n", err); -+ return err; -+} -+ -+static int au_wbr_create_init_mfsrr(struct super_block *sb) -+{ -+ int err; -+ -+ au_wbr_create_init_mfs(sb); /* ignore */ -+ err = au_wbr_create_init_rr(sb); -+ -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* top down parent and most free space */ -+static int au_wbr_create_pmfs(struct dentry *dentry, int isdir) -+{ -+ int err, e2; -+ unsigned long long b; -+ aufs_bindex_t bindex, bstart, bend; -+ struct super_block *sb; -+ struct dentry *parent, *h_parent; -+ struct au_branch *br; -+ -+ err = au_wbr_create_tdp(dentry, isdir); -+ if (unlikely(err < 0)) -+ goto out; -+ parent = dget_parent(dentry); -+ bstart = au_dbstart(parent); -+ bend = au_dbtaildir(parent); -+ if (bstart == bend) -+ goto out_parent; /* success */ -+ -+ e2 = au_wbr_create_mfs(dentry, isdir); -+ if (e2 < 0) -+ goto out_parent; /* success */ -+ -+ /* when the available size is equal, select upper one */ -+ sb = dentry->d_sb; -+ br = au_sbr(sb, err); -+ b = br->br_wbr->wbr_bytes; -+ AuDbg("b%d, %llu\n", err, b); -+ -+ for (bindex = bstart; bindex <= bend; bindex++) { -+ h_parent = au_h_dptr(parent, bindex); -+ if (!h_parent || !h_parent->d_inode) -+ continue; -+ -+ br = au_sbr(sb, bindex); -+ if (!au_br_rdonly(br) && br->br_wbr->wbr_bytes > b) { -+ b = br->br_wbr->wbr_bytes; -+ err = bindex; -+ AuDbg("b%d, %llu\n", err, b); -+ } -+ } -+ -+ if (err >= 0) -+ err = au_wbr_nonopq(dentry, err); -+ -+out_parent: -+ dput(parent); -+out: -+ AuDbg("b%d\n", err); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* policies for copyup */ -+ -+/* top down parent */ -+static int au_wbr_copyup_tdp(struct dentry *dentry) -+{ -+ return au_wbr_create_tdp(dentry, /*isdir, anything is ok*/0); -+} -+ -+/* bottom up parent */ -+static int au_wbr_copyup_bup(struct dentry *dentry) -+{ -+ int err; -+ aufs_bindex_t bindex, bstart; -+ struct dentry *parent, *h_parent; -+ struct super_block *sb; -+ -+ err = -EROFS; -+ sb = dentry->d_sb; -+ parent = dget_parent(dentry); -+ bstart = au_dbstart(parent); -+ for (bindex = au_dbstart(dentry); bindex >= bstart; bindex--) { -+ h_parent = au_h_dptr(parent, bindex); -+ if (!h_parent || !h_parent->d_inode) -+ continue; -+ -+ if (!au_br_rdonly(au_sbr(sb, bindex))) { -+ err = bindex; -+ break; -+ } -+ } -+ dput(parent); -+ -+ /* bottom up here */ -+ if (unlikely(err < 0)) -+ err = au_wbr_bu(sb, bstart - 1); -+ -+ AuDbg("b%d\n", err); -+ return err; -+} -+ -+/* bottom up */ -+static int au_wbr_copyup_bu(struct dentry *dentry) -+{ -+ int err; -+ aufs_bindex_t bstart; -+ -+ bstart = au_dbstart(dentry); -+ err = au_wbr_bu(dentry->d_sb, bstart); -+ AuDbg("b%d\n", err); -+ if (err > bstart) -+ err = au_wbr_nonopq(dentry, err); -+ -+ AuDbg("b%d\n", err); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+struct au_wbr_copyup_operations au_wbr_copyup_ops[] = { -+ [AuWbrCopyup_TDP] = { -+ .copyup = au_wbr_copyup_tdp -+ }, -+ [AuWbrCopyup_BUP] = { -+ .copyup = au_wbr_copyup_bup -+ }, -+ [AuWbrCopyup_BU] = { -+ .copyup = au_wbr_copyup_bu -+ } -+}; -+ -+struct au_wbr_create_operations au_wbr_create_ops[] = { -+ [AuWbrCreate_TDP] = { -+ .create = au_wbr_create_tdp -+ }, -+ [AuWbrCreate_RR] = { -+ .create = au_wbr_create_rr, -+ .init = au_wbr_create_init_rr -+ }, -+ [AuWbrCreate_MFS] = { -+ .create = au_wbr_create_mfs, -+ .init = au_wbr_create_init_mfs, -+ .fin = au_wbr_create_fin_mfs -+ }, -+ [AuWbrCreate_MFSV] = { -+ .create = au_wbr_create_mfs, -+ .init = au_wbr_create_init_mfs, -+ .fin = au_wbr_create_fin_mfs -+ }, -+ [AuWbrCreate_MFSRR] = { -+ .create = au_wbr_create_mfsrr, -+ .init = au_wbr_create_init_mfsrr, -+ .fin = au_wbr_create_fin_mfs -+ }, -+ [AuWbrCreate_MFSRRV] = { -+ .create = au_wbr_create_mfsrr, -+ .init = au_wbr_create_init_mfsrr, -+ .fin = au_wbr_create_fin_mfs -+ }, -+ [AuWbrCreate_PMFS] = { -+ .create = au_wbr_create_pmfs, -+ .init = au_wbr_create_init_mfs, -+ .fin = au_wbr_create_fin_mfs -+ }, -+ [AuWbrCreate_PMFSV] = { -+ .create = au_wbr_create_pmfs, -+ .init = au_wbr_create_init_mfs, -+ .fin = au_wbr_create_fin_mfs -+ } -+}; -diff -Nur linux-2.6.37.orig/fs/aufs/whout.c linux-2.6.37/fs/aufs/whout.c ---- linux-2.6.37.orig/fs/aufs/whout.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/whout.c 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,1062 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * whiteout for logical deletion and opaque directory -+ */ -+ -+#include -+#include "aufs.h" -+ -+#define WH_MASK S_IRUGO -+ -+/* -+ * If a directory contains this file, then it is opaque. We start with the -+ * .wh. flag so that it is blocked by lookup. -+ */ -+static struct qstr diropq_name = { -+ .name = AUFS_WH_DIROPQ, -+ .len = sizeof(AUFS_WH_DIROPQ) - 1 -+}; -+ -+/* -+ * generate whiteout name, which is NOT terminated by NULL. -+ * @name: original d_name.name -+ * @len: original d_name.len -+ * @wh: whiteout qstr -+ * returns zero when succeeds, otherwise error. -+ * succeeded value as wh->name should be freed by kfree(). -+ */ -+int au_wh_name_alloc(struct qstr *wh, const struct qstr *name) -+{ -+ char *p; -+ -+ if (unlikely(name->len > PATH_MAX - AUFS_WH_PFX_LEN)) -+ return -ENAMETOOLONG; -+ -+ wh->len = name->len + AUFS_WH_PFX_LEN; -+ p = kmalloc(wh->len, GFP_NOFS); -+ wh->name = p; -+ if (p) { -+ memcpy(p, AUFS_WH_PFX, AUFS_WH_PFX_LEN); -+ memcpy(p + AUFS_WH_PFX_LEN, name->name, name->len); -+ /* smp_mb(); */ -+ return 0; -+ } -+ return -ENOMEM; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * test if the @wh_name exists under @h_parent. -+ * @try_sio specifies the necessary of super-io. -+ */ -+int au_wh_test(struct dentry *h_parent, struct qstr *wh_name, -+ struct au_branch *br, int try_sio) -+{ -+ int err; -+ struct dentry *wh_dentry; -+ -+ if (!try_sio) -+ wh_dentry = au_lkup_one(wh_name, h_parent, br, /*nd*/NULL); -+ else -+ wh_dentry = au_sio_lkup_one(wh_name, h_parent, br); -+ err = PTR_ERR(wh_dentry); -+ if (IS_ERR(wh_dentry)) -+ goto out; -+ -+ err = 0; -+ if (!wh_dentry->d_inode) -+ goto out_wh; /* success */ -+ -+ err = 1; -+ if (S_ISREG(wh_dentry->d_inode->i_mode)) -+ goto out_wh; /* success */ -+ -+ err = -EIO; -+ AuIOErr("%.*s Invalid whiteout entry type 0%o.\n", -+ AuDLNPair(wh_dentry), wh_dentry->d_inode->i_mode); -+ -+out_wh: -+ dput(wh_dentry); -+out: -+ return err; -+} -+ -+/* -+ * test if the @h_dentry sets opaque or not. -+ */ -+int au_diropq_test(struct dentry *h_dentry, struct au_branch *br) -+{ -+ int err; -+ struct inode *h_dir; -+ -+ h_dir = h_dentry->d_inode; -+ err = au_wh_test(h_dentry, &diropq_name, br, -+ au_test_h_perm_sio(h_dir, MAY_EXEC)); -+ return err; -+} -+ -+/* -+ * returns a negative dentry whose name is unique and temporary. -+ */ -+struct dentry *au_whtmp_lkup(struct dentry *h_parent, struct au_branch *br, -+ struct qstr *prefix) -+{ -+ struct dentry *dentry; -+ int i; -+ char defname[NAME_MAX - AUFS_MAX_NAMELEN + DNAME_INLINE_LEN_MIN + 1], -+ *name, *p; -+ /* strict atomic_t is unnecessary here */ -+ static unsigned short cnt; -+ struct qstr qs; -+ -+ BUILD_BUG_ON(sizeof(cnt) * 2 > AUFS_WH_TMP_LEN); -+ -+ name = defname; -+ qs.len = sizeof(defname) - DNAME_INLINE_LEN_MIN + prefix->len - 1; -+ if (unlikely(prefix->len > DNAME_INLINE_LEN_MIN)) { -+ dentry = ERR_PTR(-ENAMETOOLONG); -+ if (unlikely(qs.len > NAME_MAX)) -+ goto out; -+ dentry = ERR_PTR(-ENOMEM); -+ name = kmalloc(qs.len + 1, GFP_NOFS); -+ if (unlikely(!name)) -+ goto out; -+ } -+ -+ /* doubly whiteout-ed */ -+ memcpy(name, AUFS_WH_PFX AUFS_WH_PFX, AUFS_WH_PFX_LEN * 2); -+ p = name + AUFS_WH_PFX_LEN * 2; -+ memcpy(p, prefix->name, prefix->len); -+ p += prefix->len; -+ *p++ = '.'; -+ AuDebugOn(name + qs.len + 1 - p <= AUFS_WH_TMP_LEN); -+ -+ qs.name = name; -+ for (i = 0; i < 3; i++) { -+ sprintf(p, "%.*x", AUFS_WH_TMP_LEN, cnt++); -+ dentry = au_sio_lkup_one(&qs, h_parent, br); -+ if (IS_ERR(dentry) || !dentry->d_inode) -+ goto out_name; -+ dput(dentry); -+ } -+ /* pr_warning("could not get random name\n"); */ -+ dentry = ERR_PTR(-EEXIST); -+ AuDbg("%.*s\n", AuLNPair(&qs)); -+ BUG(); -+ -+out_name: -+ if (name != defname) -+ kfree(name); -+out: -+ AuTraceErrPtr(dentry); -+ return dentry; -+} -+ -+/* -+ * rename the @h_dentry on @br to the whiteouted temporary name. -+ */ -+int au_whtmp_ren(struct dentry *h_dentry, struct au_branch *br) -+{ -+ int err; -+ struct path h_path = { -+ .mnt = br->br_mnt -+ }; -+ struct inode *h_dir; -+ struct dentry *h_parent; -+ -+ h_parent = h_dentry->d_parent; /* dir inode is locked */ -+ h_dir = h_parent->d_inode; -+ IMustLock(h_dir); -+ -+ h_path.dentry = au_whtmp_lkup(h_parent, br, &h_dentry->d_name); -+ err = PTR_ERR(h_path.dentry); -+ if (IS_ERR(h_path.dentry)) -+ goto out; -+ -+ /* under the same dir, no need to lock_rename() */ -+ err = vfsub_rename(h_dir, h_dentry, h_dir, &h_path); -+ AuTraceErr(err); -+ dput(h_path.dentry); -+ -+out: -+ AuTraceErr(err); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+/* -+ * functions for removing a whiteout -+ */ -+ -+static int do_unlink_wh(struct inode *h_dir, struct path *h_path) -+{ -+ int force; -+ -+ /* -+ * forces superio when the dir has a sticky bit. -+ * this may be a violation of unix fs semantics. -+ */ -+ force = (h_dir->i_mode & S_ISVTX) -+ && h_path->dentry->d_inode->i_uid != current_fsuid(); -+ return vfsub_unlink(h_dir, h_path, force); -+} -+ -+int au_wh_unlink_dentry(struct inode *h_dir, struct path *h_path, -+ struct dentry *dentry) -+{ -+ int err; -+ -+ err = do_unlink_wh(h_dir, h_path); -+ if (!err && dentry) -+ au_set_dbwh(dentry, -1); -+ -+ return err; -+} -+ -+static int unlink_wh_name(struct dentry *h_parent, struct qstr *wh, -+ struct au_branch *br) -+{ -+ int err; -+ struct path h_path = { -+ .mnt = br->br_mnt -+ }; -+ -+ err = 0; -+ h_path.dentry = au_lkup_one(wh, h_parent, br, /*nd*/NULL); -+ if (IS_ERR(h_path.dentry)) -+ err = PTR_ERR(h_path.dentry); -+ else { -+ if (h_path.dentry->d_inode -+ && S_ISREG(h_path.dentry->d_inode->i_mode)) -+ err = do_unlink_wh(h_parent->d_inode, &h_path); -+ dput(h_path.dentry); -+ } -+ -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+/* -+ * initialize/clean whiteout for a branch -+ */ -+ -+static void au_wh_clean(struct inode *h_dir, struct path *whpath, -+ const int isdir) -+{ -+ int err; -+ -+ if (!whpath->dentry->d_inode) -+ return; -+ -+ err = mnt_want_write(whpath->mnt); -+ if (!err) { -+ if (isdir) -+ err = vfsub_rmdir(h_dir, whpath); -+ else -+ err = vfsub_unlink(h_dir, whpath, /*force*/0); -+ mnt_drop_write(whpath->mnt); -+ } -+ if (unlikely(err)) -+ pr_warning("failed removing %.*s (%d), ignored.\n", -+ AuDLNPair(whpath->dentry), err); -+} -+ -+static int test_linkable(struct dentry *h_root) -+{ -+ struct inode *h_dir = h_root->d_inode; -+ -+ if (h_dir->i_op->link) -+ return 0; -+ -+ pr_err("%.*s (%s) doesn't support link(2), use noplink and rw+nolwh\n", -+ AuDLNPair(h_root), au_sbtype(h_root->d_sb)); -+ return -ENOSYS; -+} -+ -+/* todo: should this mkdir be done in /sbin/mount.aufs helper? */ -+static int au_whdir(struct inode *h_dir, struct path *path) -+{ -+ int err; -+ -+ err = -EEXIST; -+ if (!path->dentry->d_inode) { -+ int mode = S_IRWXU; -+ -+ if (au_test_nfs(path->dentry->d_sb)) -+ mode |= S_IXUGO; -+ err = mnt_want_write(path->mnt); -+ if (!err) { -+ err = vfsub_mkdir(h_dir, path, mode); -+ mnt_drop_write(path->mnt); -+ } -+ } else if (S_ISDIR(path->dentry->d_inode->i_mode)) -+ err = 0; -+ else -+ pr_err("unknown %.*s exists\n", AuDLNPair(path->dentry)); -+ -+ return err; -+} -+ -+struct au_wh_base { -+ const struct qstr *name; -+ struct dentry *dentry; -+}; -+ -+static void au_wh_init_ro(struct inode *h_dir, struct au_wh_base base[], -+ struct path *h_path) -+{ -+ h_path->dentry = base[AuBrWh_BASE].dentry; -+ au_wh_clean(h_dir, h_path, /*isdir*/0); -+ h_path->dentry = base[AuBrWh_PLINK].dentry; -+ au_wh_clean(h_dir, h_path, /*isdir*/1); -+ h_path->dentry = base[AuBrWh_ORPH].dentry; -+ au_wh_clean(h_dir, h_path, /*isdir*/1); -+} -+ -+/* -+ * returns tri-state, -+ * minus: error, caller should print the mesage -+ * zero: succuess -+ * plus: error, caller should NOT print the mesage -+ */ -+static int au_wh_init_rw_nolink(struct dentry *h_root, struct au_wbr *wbr, -+ int do_plink, struct au_wh_base base[], -+ struct path *h_path) -+{ -+ int err; -+ struct inode *h_dir; -+ -+ h_dir = h_root->d_inode; -+ h_path->dentry = base[AuBrWh_BASE].dentry; -+ au_wh_clean(h_dir, h_path, /*isdir*/0); -+ h_path->dentry = base[AuBrWh_PLINK].dentry; -+ if (do_plink) { -+ err = test_linkable(h_root); -+ if (unlikely(err)) { -+ err = 1; -+ goto out; -+ } -+ -+ err = au_whdir(h_dir, h_path); -+ if (unlikely(err)) -+ goto out; -+ wbr->wbr_plink = dget(base[AuBrWh_PLINK].dentry); -+ } else -+ au_wh_clean(h_dir, h_path, /*isdir*/1); -+ h_path->dentry = base[AuBrWh_ORPH].dentry; -+ err = au_whdir(h_dir, h_path); -+ if (unlikely(err)) -+ goto out; -+ wbr->wbr_orph = dget(base[AuBrWh_ORPH].dentry); -+ -+out: -+ return err; -+} -+ -+/* -+ * for the moment, aufs supports the branch filesystem which does not support -+ * link(2). testing on FAT which does not support i_op->setattr() fully either, -+ * copyup failed. finally, such filesystem will not be used as the writable -+ * branch. -+ * -+ * returns tri-state, see above. -+ */ -+static int au_wh_init_rw(struct dentry *h_root, struct au_wbr *wbr, -+ int do_plink, struct au_wh_base base[], -+ struct path *h_path) -+{ -+ int err; -+ struct inode *h_dir; -+ -+ WbrWhMustWriteLock(wbr); -+ -+ err = test_linkable(h_root); -+ if (unlikely(err)) { -+ err = 1; -+ goto out; -+ } -+ -+ /* -+ * todo: should this create be done in /sbin/mount.aufs helper? -+ */ -+ err = -EEXIST; -+ h_dir = h_root->d_inode; -+ if (!base[AuBrWh_BASE].dentry->d_inode) { -+ err = mnt_want_write(h_path->mnt); -+ if (!err) { -+ h_path->dentry = base[AuBrWh_BASE].dentry; -+ err = vfsub_create(h_dir, h_path, WH_MASK); -+ mnt_drop_write(h_path->mnt); -+ } -+ } else if (S_ISREG(base[AuBrWh_BASE].dentry->d_inode->i_mode)) -+ err = 0; -+ else -+ pr_err("unknown %.*s/%.*s exists\n", -+ AuDLNPair(h_root), AuDLNPair(base[AuBrWh_BASE].dentry)); -+ if (unlikely(err)) -+ goto out; -+ -+ h_path->dentry = base[AuBrWh_PLINK].dentry; -+ if (do_plink) { -+ err = au_whdir(h_dir, h_path); -+ if (unlikely(err)) -+ goto out; -+ wbr->wbr_plink = dget(base[AuBrWh_PLINK].dentry); -+ } else -+ au_wh_clean(h_dir, h_path, /*isdir*/1); -+ wbr->wbr_whbase = dget(base[AuBrWh_BASE].dentry); -+ -+ h_path->dentry = base[AuBrWh_ORPH].dentry; -+ err = au_whdir(h_dir, h_path); -+ if (unlikely(err)) -+ goto out; -+ wbr->wbr_orph = dget(base[AuBrWh_ORPH].dentry); -+ -+out: -+ return err; -+} -+ -+/* -+ * initialize the whiteout base file/dir for @br. -+ */ -+int au_wh_init(struct dentry *h_root, struct au_branch *br, -+ struct super_block *sb) -+{ -+ int err, i; -+ const unsigned char do_plink -+ = !!au_opt_test(au_mntflags(sb), PLINK); -+ struct path path = { -+ .mnt = br->br_mnt -+ }; -+ struct inode *h_dir; -+ struct au_wbr *wbr = br->br_wbr; -+ static const struct qstr base_name[] = { -+ [AuBrWh_BASE] = { -+ .name = AUFS_BASE_NAME, -+ .len = sizeof(AUFS_BASE_NAME) - 1 -+ }, -+ [AuBrWh_PLINK] = { -+ .name = AUFS_PLINKDIR_NAME, -+ .len = sizeof(AUFS_PLINKDIR_NAME) - 1 -+ }, -+ [AuBrWh_ORPH] = { -+ .name = AUFS_ORPHDIR_NAME, -+ .len = sizeof(AUFS_ORPHDIR_NAME) - 1 -+ } -+ }; -+ struct au_wh_base base[] = { -+ [AuBrWh_BASE] = { -+ .name = base_name + AuBrWh_BASE, -+ .dentry = NULL -+ }, -+ [AuBrWh_PLINK] = { -+ .name = base_name + AuBrWh_PLINK, -+ .dentry = NULL -+ }, -+ [AuBrWh_ORPH] = { -+ .name = base_name + AuBrWh_ORPH, -+ .dentry = NULL -+ } -+ }; -+ -+ if (wbr) -+ WbrWhMustWriteLock(wbr); -+ -+ for (i = 0; i < AuBrWh_Last; i++) { -+ /* doubly whiteouted */ -+ struct dentry *d; -+ -+ d = au_wh_lkup(h_root, (void *)base[i].name, br); -+ err = PTR_ERR(d); -+ if (IS_ERR(d)) -+ goto out; -+ -+ base[i].dentry = d; -+ AuDebugOn(wbr -+ && wbr->wbr_wh[i] -+ && wbr->wbr_wh[i] != base[i].dentry); -+ } -+ -+ if (wbr) -+ for (i = 0; i < AuBrWh_Last; i++) { -+ dput(wbr->wbr_wh[i]); -+ wbr->wbr_wh[i] = NULL; -+ } -+ -+ err = 0; -+ switch (br->br_perm) { -+ case AuBrPerm_RO: -+ case AuBrPerm_ROWH: -+ case AuBrPerm_RR: -+ case AuBrPerm_RRWH: -+ h_dir = h_root->d_inode; -+ au_wh_init_ro(h_dir, base, &path); -+ break; -+ -+ case AuBrPerm_RWNoLinkWH: -+ err = au_wh_init_rw_nolink(h_root, wbr, do_plink, base, &path); -+ if (err > 0) -+ goto out; -+ else if (err) -+ goto out_err; -+ break; -+ -+ case AuBrPerm_RW: -+ err = au_wh_init_rw(h_root, wbr, do_plink, base, &path); -+ if (err > 0) -+ goto out; -+ else if (err) -+ goto out_err; -+ break; -+ -+ default: -+ BUG(); -+ } -+ goto out; /* success */ -+ -+out_err: -+ pr_err("an error(%d) on the writable branch %.*s(%s)\n", -+ err, AuDLNPair(h_root), au_sbtype(h_root->d_sb)); -+out: -+ for (i = 0; i < AuBrWh_Last; i++) -+ dput(base[i].dentry); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+/* -+ * whiteouts are all hard-linked usually. -+ * when its link count reaches a ceiling, we create a new whiteout base -+ * asynchronously. -+ */ -+ -+struct reinit_br_wh { -+ struct super_block *sb; -+ struct au_branch *br; -+}; -+ -+static void reinit_br_wh(void *arg) -+{ -+ int err; -+ aufs_bindex_t bindex; -+ struct path h_path; -+ struct reinit_br_wh *a = arg; -+ struct au_wbr *wbr; -+ struct inode *dir; -+ struct dentry *h_root; -+ struct au_hinode *hdir; -+ -+ err = 0; -+ wbr = a->br->br_wbr; -+ /* big aufs lock */ -+ si_noflush_write_lock(a->sb); -+ if (!au_br_writable(a->br->br_perm)) -+ goto out; -+ bindex = au_br_index(a->sb, a->br->br_id); -+ if (unlikely(bindex < 0)) -+ goto out; -+ -+ di_read_lock_parent(a->sb->s_root, AuLock_IR); -+ dir = a->sb->s_root->d_inode; -+ hdir = au_hi(dir, bindex); -+ h_root = au_h_dptr(a->sb->s_root, bindex); -+ -+ au_hn_imtx_lock_nested(hdir, AuLsc_I_PARENT); -+ wbr_wh_write_lock(wbr); -+ err = au_h_verify(wbr->wbr_whbase, au_opt_udba(a->sb), hdir->hi_inode, -+ h_root, a->br); -+ if (!err) { -+ err = mnt_want_write(a->br->br_mnt); -+ if (!err) { -+ h_path.dentry = wbr->wbr_whbase; -+ h_path.mnt = a->br->br_mnt; -+ err = vfsub_unlink(hdir->hi_inode, &h_path, /*force*/0); -+ mnt_drop_write(a->br->br_mnt); -+ } -+ } else { -+ pr_warning("%.*s is moved, ignored\n", -+ AuDLNPair(wbr->wbr_whbase)); -+ err = 0; -+ } -+ dput(wbr->wbr_whbase); -+ wbr->wbr_whbase = NULL; -+ if (!err) -+ err = au_wh_init(h_root, a->br, a->sb); -+ wbr_wh_write_unlock(wbr); -+ au_hn_imtx_unlock(hdir); -+ di_read_unlock(a->sb->s_root, AuLock_IR); -+ -+out: -+ if (wbr) -+ atomic_dec(&wbr->wbr_wh_running); -+ atomic_dec(&a->br->br_count); -+ si_write_unlock(a->sb); -+ au_nwt_done(&au_sbi(a->sb)->si_nowait); -+ kfree(arg); -+ if (unlikely(err)) -+ AuIOErr("err %d\n", err); -+} -+ -+static void kick_reinit_br_wh(struct super_block *sb, struct au_branch *br) -+{ -+ int do_dec, wkq_err; -+ struct reinit_br_wh *arg; -+ -+ do_dec = 1; -+ if (atomic_inc_return(&br->br_wbr->wbr_wh_running) != 1) -+ goto out; -+ -+ /* ignore ENOMEM */ -+ arg = kmalloc(sizeof(*arg), GFP_NOFS); -+ if (arg) { -+ /* -+ * dec(wh_running), kfree(arg) and dec(br_count) -+ * in reinit function -+ */ -+ arg->sb = sb; -+ arg->br = br; -+ atomic_inc(&br->br_count); -+ wkq_err = au_wkq_nowait(reinit_br_wh, arg, sb); -+ if (unlikely(wkq_err)) { -+ atomic_dec(&br->br_wbr->wbr_wh_running); -+ atomic_dec(&br->br_count); -+ kfree(arg); -+ } -+ do_dec = 0; -+ } -+ -+out: -+ if (do_dec) -+ atomic_dec(&br->br_wbr->wbr_wh_running); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * create the whiteout @wh. -+ */ -+static int link_or_create_wh(struct super_block *sb, aufs_bindex_t bindex, -+ struct dentry *wh) -+{ -+ int err; -+ struct path h_path = { -+ .dentry = wh -+ }; -+ struct au_branch *br; -+ struct au_wbr *wbr; -+ struct dentry *h_parent; -+ struct inode *h_dir; -+ -+ h_parent = wh->d_parent; /* dir inode is locked */ -+ h_dir = h_parent->d_inode; -+ IMustLock(h_dir); -+ -+ br = au_sbr(sb, bindex); -+ h_path.mnt = br->br_mnt; -+ wbr = br->br_wbr; -+ wbr_wh_read_lock(wbr); -+ if (wbr->wbr_whbase) { -+ err = vfsub_link(wbr->wbr_whbase, h_dir, &h_path); -+ if (!err || err != -EMLINK) -+ goto out; -+ -+ /* link count full. re-initialize br_whbase. */ -+ kick_reinit_br_wh(sb, br); -+ } -+ -+ /* return this error in this context */ -+ err = vfsub_create(h_dir, &h_path, WH_MASK); -+ -+out: -+ wbr_wh_read_unlock(wbr); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * create or remove the diropq. -+ */ -+static struct dentry *do_diropq(struct dentry *dentry, aufs_bindex_t bindex, -+ unsigned int flags) -+{ -+ struct dentry *opq_dentry, *h_dentry; -+ struct super_block *sb; -+ struct au_branch *br; -+ int err; -+ -+ sb = dentry->d_sb; -+ br = au_sbr(sb, bindex); -+ h_dentry = au_h_dptr(dentry, bindex); -+ opq_dentry = au_lkup_one(&diropq_name, h_dentry, br, /*nd*/NULL); -+ if (IS_ERR(opq_dentry)) -+ goto out; -+ -+ if (au_ftest_diropq(flags, CREATE)) { -+ err = link_or_create_wh(sb, bindex, opq_dentry); -+ if (!err) { -+ au_set_dbdiropq(dentry, bindex); -+ goto out; /* success */ -+ } -+ } else { -+ struct path tmp = { -+ .dentry = opq_dentry, -+ .mnt = br->br_mnt -+ }; -+ err = do_unlink_wh(au_h_iptr(dentry->d_inode, bindex), &tmp); -+ if (!err) -+ au_set_dbdiropq(dentry, -1); -+ } -+ dput(opq_dentry); -+ opq_dentry = ERR_PTR(err); -+ -+out: -+ return opq_dentry; -+} -+ -+struct do_diropq_args { -+ struct dentry **errp; -+ struct dentry *dentry; -+ aufs_bindex_t bindex; -+ unsigned int flags; -+}; -+ -+static void call_do_diropq(void *args) -+{ -+ struct do_diropq_args *a = args; -+ *a->errp = do_diropq(a->dentry, a->bindex, a->flags); -+} -+ -+struct dentry *au_diropq_sio(struct dentry *dentry, aufs_bindex_t bindex, -+ unsigned int flags) -+{ -+ struct dentry *diropq, *h_dentry; -+ -+ h_dentry = au_h_dptr(dentry, bindex); -+ if (!au_test_h_perm_sio(h_dentry->d_inode, MAY_EXEC | MAY_WRITE)) -+ diropq = do_diropq(dentry, bindex, flags); -+ else { -+ int wkq_err; -+ struct do_diropq_args args = { -+ .errp = &diropq, -+ .dentry = dentry, -+ .bindex = bindex, -+ .flags = flags -+ }; -+ -+ wkq_err = au_wkq_wait(call_do_diropq, &args); -+ if (unlikely(wkq_err)) -+ diropq = ERR_PTR(wkq_err); -+ } -+ -+ return diropq; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * lookup whiteout dentry. -+ * @h_parent: lower parent dentry which must exist and be locked -+ * @base_name: name of dentry which will be whiteouted -+ * returns dentry for whiteout. -+ */ -+struct dentry *au_wh_lkup(struct dentry *h_parent, struct qstr *base_name, -+ struct au_branch *br) -+{ -+ int err; -+ struct qstr wh_name; -+ struct dentry *wh_dentry; -+ -+ err = au_wh_name_alloc(&wh_name, base_name); -+ wh_dentry = ERR_PTR(err); -+ if (!err) { -+ wh_dentry = au_lkup_one(&wh_name, h_parent, br, /*nd*/NULL); -+ kfree(wh_name.name); -+ } -+ return wh_dentry; -+} -+ -+/* -+ * link/create a whiteout for @dentry on @bindex. -+ */ -+struct dentry *au_wh_create(struct dentry *dentry, aufs_bindex_t bindex, -+ struct dentry *h_parent) -+{ -+ struct dentry *wh_dentry; -+ struct super_block *sb; -+ int err; -+ -+ sb = dentry->d_sb; -+ wh_dentry = au_wh_lkup(h_parent, &dentry->d_name, au_sbr(sb, bindex)); -+ if (!IS_ERR(wh_dentry) && !wh_dentry->d_inode) { -+ err = link_or_create_wh(sb, bindex, wh_dentry); -+ if (!err) -+ au_set_dbwh(dentry, bindex); -+ else { -+ dput(wh_dentry); -+ wh_dentry = ERR_PTR(err); -+ } -+ } -+ -+ return wh_dentry; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* Delete all whiteouts in this directory on branch bindex. */ -+static int del_wh_children(struct dentry *h_dentry, struct au_nhash *whlist, -+ aufs_bindex_t bindex, struct au_branch *br) -+{ -+ int err; -+ unsigned long ul, n; -+ struct qstr wh_name; -+ char *p; -+ struct hlist_head *head; -+ struct au_vdir_wh *tpos; -+ struct hlist_node *pos; -+ struct au_vdir_destr *str; -+ -+ err = -ENOMEM; -+ p = __getname_gfp(GFP_NOFS); -+ wh_name.name = p; -+ if (unlikely(!wh_name.name)) -+ goto out; -+ -+ err = 0; -+ memcpy(p, AUFS_WH_PFX, AUFS_WH_PFX_LEN); -+ p += AUFS_WH_PFX_LEN; -+ n = whlist->nh_num; -+ head = whlist->nh_head; -+ for (ul = 0; !err && ul < n; ul++, head++) { -+ hlist_for_each_entry(tpos, pos, head, wh_hash) { -+ if (tpos->wh_bindex != bindex) -+ continue; -+ -+ str = &tpos->wh_str; -+ if (str->len + AUFS_WH_PFX_LEN <= PATH_MAX) { -+ memcpy(p, str->name, str->len); -+ wh_name.len = AUFS_WH_PFX_LEN + str->len; -+ err = unlink_wh_name(h_dentry, &wh_name, br); -+ if (!err) -+ continue; -+ break; -+ } -+ AuIOErr("whiteout name too long %.*s\n", -+ str->len, str->name); -+ err = -EIO; -+ break; -+ } -+ } -+ __putname(wh_name.name); -+ -+out: -+ return err; -+} -+ -+struct del_wh_children_args { -+ int *errp; -+ struct dentry *h_dentry; -+ struct au_nhash *whlist; -+ aufs_bindex_t bindex; -+ struct au_branch *br; -+}; -+ -+static void call_del_wh_children(void *args) -+{ -+ struct del_wh_children_args *a = args; -+ *a->errp = del_wh_children(a->h_dentry, a->whlist, a->bindex, a->br); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+struct au_whtmp_rmdir *au_whtmp_rmdir_alloc(struct super_block *sb, gfp_t gfp) -+{ -+ struct au_whtmp_rmdir *whtmp; -+ int err; -+ unsigned int rdhash; -+ -+ SiMustAnyLock(sb); -+ -+ whtmp = kmalloc(sizeof(*whtmp), gfp); -+ if (unlikely(!whtmp)) { -+ whtmp = ERR_PTR(-ENOMEM); -+ goto out; -+ } -+ -+ whtmp->dir = NULL; -+ whtmp->br = NULL; -+ whtmp->wh_dentry = NULL; -+ /* no estimation for dir size */ -+ rdhash = au_sbi(sb)->si_rdhash; -+ if (!rdhash) -+ rdhash = AUFS_RDHASH_DEF; -+ err = au_nhash_alloc(&whtmp->whlist, rdhash, gfp); -+ if (unlikely(err)) { -+ kfree(whtmp); -+ whtmp = ERR_PTR(err); -+ } -+ -+out: -+ return whtmp; -+} -+ -+void au_whtmp_rmdir_free(struct au_whtmp_rmdir *whtmp) -+{ -+ if (whtmp->br) -+ atomic_dec(&whtmp->br->br_count); -+ dput(whtmp->wh_dentry); -+ iput(whtmp->dir); -+ au_nhash_wh_free(&whtmp->whlist); -+ kfree(whtmp); -+} -+ -+/* -+ * rmdir the whiteouted temporary named dir @h_dentry. -+ * @whlist: whiteouted children. -+ */ -+int au_whtmp_rmdir(struct inode *dir, aufs_bindex_t bindex, -+ struct dentry *wh_dentry, struct au_nhash *whlist) -+{ -+ int err; -+ struct path h_tmp; -+ struct inode *wh_inode, *h_dir; -+ struct au_branch *br; -+ -+ h_dir = wh_dentry->d_parent->d_inode; /* dir inode is locked */ -+ IMustLock(h_dir); -+ -+ br = au_sbr(dir->i_sb, bindex); -+ wh_inode = wh_dentry->d_inode; -+ mutex_lock_nested(&wh_inode->i_mutex, AuLsc_I_CHILD); -+ -+ /* -+ * someone else might change some whiteouts while we were sleeping. -+ * it means this whlist may have an obsoleted entry. -+ */ -+ if (!au_test_h_perm_sio(wh_inode, MAY_EXEC | MAY_WRITE)) -+ err = del_wh_children(wh_dentry, whlist, bindex, br); -+ else { -+ int wkq_err; -+ struct del_wh_children_args args = { -+ .errp = &err, -+ .h_dentry = wh_dentry, -+ .whlist = whlist, -+ .bindex = bindex, -+ .br = br -+ }; -+ -+ wkq_err = au_wkq_wait(call_del_wh_children, &args); -+ if (unlikely(wkq_err)) -+ err = wkq_err; -+ } -+ mutex_unlock(&wh_inode->i_mutex); -+ -+ if (!err) { -+ h_tmp.dentry = wh_dentry; -+ h_tmp.mnt = br->br_mnt; -+ err = vfsub_rmdir(h_dir, &h_tmp); -+ } -+ -+ if (!err) { -+ if (au_ibstart(dir) == bindex) { -+ /* todo: dir->i_mutex is necessary */ -+ au_cpup_attr_timesizes(dir); -+ vfsub_drop_nlink(dir); -+ } -+ return 0; /* success */ -+ } -+ -+ pr_warning("failed removing %.*s(%d), ignored\n", -+ AuDLNPair(wh_dentry), err); -+ return err; -+} -+ -+static void call_rmdir_whtmp(void *args) -+{ -+ int err; -+ aufs_bindex_t bindex; -+ struct au_whtmp_rmdir *a = args; -+ struct super_block *sb; -+ struct dentry *h_parent; -+ struct inode *h_dir; -+ struct au_hinode *hdir; -+ -+ /* rmdir by nfsd may cause deadlock with this i_mutex */ -+ /* mutex_lock(&a->dir->i_mutex); */ -+ err = -EROFS; -+ sb = a->dir->i_sb; -+ si_read_lock(sb, !AuLock_FLUSH); -+ if (!au_br_writable(a->br->br_perm)) -+ goto out; -+ bindex = au_br_index(sb, a->br->br_id); -+ if (unlikely(bindex < 0)) -+ goto out; -+ -+ err = -EIO; -+ ii_write_lock_parent(a->dir); -+ h_parent = dget_parent(a->wh_dentry); -+ h_dir = h_parent->d_inode; -+ hdir = au_hi(a->dir, bindex); -+ au_hn_imtx_lock_nested(hdir, AuLsc_I_PARENT); -+ err = au_h_verify(a->wh_dentry, au_opt_udba(sb), h_dir, h_parent, -+ a->br); -+ if (!err) { -+ err = mnt_want_write(a->br->br_mnt); -+ if (!err) { -+ err = au_whtmp_rmdir(a->dir, bindex, a->wh_dentry, -+ &a->whlist); -+ mnt_drop_write(a->br->br_mnt); -+ } -+ } -+ au_hn_imtx_unlock(hdir); -+ dput(h_parent); -+ ii_write_unlock(a->dir); -+ -+out: -+ /* mutex_unlock(&a->dir->i_mutex); */ -+ au_whtmp_rmdir_free(a); -+ si_read_unlock(sb); -+ au_nwt_done(&au_sbi(sb)->si_nowait); -+ if (unlikely(err)) -+ AuIOErr("err %d\n", err); -+} -+ -+void au_whtmp_kick_rmdir(struct inode *dir, aufs_bindex_t bindex, -+ struct dentry *wh_dentry, struct au_whtmp_rmdir *args) -+{ -+ int wkq_err; -+ struct super_block *sb; -+ -+ IMustLock(dir); -+ -+ /* all post-process will be done in do_rmdir_whtmp(). */ -+ sb = dir->i_sb; -+ args->dir = au_igrab(dir); -+ args->br = au_sbr(sb, bindex); -+ atomic_inc(&args->br->br_count); -+ args->wh_dentry = dget(wh_dentry); -+ wkq_err = au_wkq_nowait(call_rmdir_whtmp, args, sb); -+ if (unlikely(wkq_err)) { -+ pr_warning("rmdir error %.*s (%d), ignored\n", -+ AuDLNPair(wh_dentry), wkq_err); -+ au_whtmp_rmdir_free(args); -+ } -+} -diff -Nur linux-2.6.37.orig/fs/aufs/whout.h linux-2.6.37/fs/aufs/whout.h ---- linux-2.6.37.orig/fs/aufs/whout.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/whout.h 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,89 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * whiteout for logical deletion and opaque directory -+ */ -+ -+#ifndef __AUFS_WHOUT_H__ -+#define __AUFS_WHOUT_H__ -+ -+#ifdef __KERNEL__ -+ -+#include -+#include "dir.h" -+ -+/* whout.c */ -+int au_wh_name_alloc(struct qstr *wh, const struct qstr *name); -+struct au_branch; -+int au_wh_test(struct dentry *h_parent, struct qstr *wh_name, -+ struct au_branch *br, int try_sio); -+int au_diropq_test(struct dentry *h_dentry, struct au_branch *br); -+struct dentry *au_whtmp_lkup(struct dentry *h_parent, struct au_branch *br, -+ struct qstr *prefix); -+int au_whtmp_ren(struct dentry *h_dentry, struct au_branch *br); -+int au_wh_unlink_dentry(struct inode *h_dir, struct path *h_path, -+ struct dentry *dentry); -+int au_wh_init(struct dentry *h_parent, struct au_branch *br, -+ struct super_block *sb); -+ -+/* diropq flags */ -+#define AuDiropq_CREATE 1 -+#define au_ftest_diropq(flags, name) ((flags) & AuDiropq_##name) -+#define au_fset_diropq(flags, name) \ -+ do { (flags) |= AuDiropq_##name; } while (0) -+#define au_fclr_diropq(flags, name) \ -+ do { (flags) &= ~AuDiropq_##name; } while (0) -+ -+struct dentry *au_diropq_sio(struct dentry *dentry, aufs_bindex_t bindex, -+ unsigned int flags); -+struct dentry *au_wh_lkup(struct dentry *h_parent, struct qstr *base_name, -+ struct au_branch *br); -+struct dentry *au_wh_create(struct dentry *dentry, aufs_bindex_t bindex, -+ struct dentry *h_parent); -+ -+/* real rmdir for the whiteout-ed dir */ -+struct au_whtmp_rmdir { -+ struct inode *dir; -+ struct au_branch *br; -+ struct dentry *wh_dentry; -+ struct au_nhash whlist; -+}; -+ -+struct au_whtmp_rmdir *au_whtmp_rmdir_alloc(struct super_block *sb, gfp_t gfp); -+void au_whtmp_rmdir_free(struct au_whtmp_rmdir *whtmp); -+int au_whtmp_rmdir(struct inode *dir, aufs_bindex_t bindex, -+ struct dentry *wh_dentry, struct au_nhash *whlist); -+void au_whtmp_kick_rmdir(struct inode *dir, aufs_bindex_t bindex, -+ struct dentry *wh_dentry, struct au_whtmp_rmdir *args); -+ -+/* ---------------------------------------------------------------------- */ -+ -+static inline struct dentry *au_diropq_create(struct dentry *dentry, -+ aufs_bindex_t bindex) -+{ -+ return au_diropq_sio(dentry, bindex, AuDiropq_CREATE); -+} -+ -+static inline int au_diropq_remove(struct dentry *dentry, aufs_bindex_t bindex) -+{ -+ return PTR_ERR(au_diropq_sio(dentry, bindex, !AuDiropq_CREATE)); -+} -+ -+#endif /* __KERNEL__ */ -+#endif /* __AUFS_WHOUT_H__ */ -diff -Nur linux-2.6.37.orig/fs/aufs/wkq.c linux-2.6.37/fs/aufs/wkq.c ---- linux-2.6.37.orig/fs/aufs/wkq.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/wkq.c 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,236 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * workqueue for asynchronous/super-io operations -+ * todo: try new dredential scheme -+ */ -+ -+#include -+#include "aufs.h" -+ -+/* internal workqueue named AUFS_WKQ_NAME and AUFS_WKQ_PRE_NAME */ -+enum { -+ AuWkq_INORMAL, -+ AuWkq_IPRE -+}; -+ -+static struct { -+ char *name; -+ struct workqueue_struct *wkq; -+} au_wkq[] = { -+ [AuWkq_INORMAL] = { -+ .name = AUFS_WKQ_NAME -+ }, -+ [AuWkq_IPRE] = { -+ .name = AUFS_WKQ_PRE_NAME -+ } -+}; -+ -+struct au_wkinfo { -+ struct work_struct wk; -+ struct kobject *kobj; -+ -+ unsigned int flags; /* see wkq.h */ -+ -+ au_wkq_func_t func; -+ void *args; -+ -+ struct completion *comp; -+}; -+ -+/* ---------------------------------------------------------------------- */ -+ -+static void wkq_func(struct work_struct *wk) -+{ -+ struct au_wkinfo *wkinfo = container_of(wk, struct au_wkinfo, wk); -+ -+ AuDebugOn(current_fsuid()); -+ AuDebugOn(rlimit(RLIMIT_FSIZE) != RLIM_INFINITY); -+ -+ wkinfo->func(wkinfo->args); -+ if (au_ftest_wkq(wkinfo->flags, WAIT)) -+ complete(wkinfo->comp); -+ else { -+ kobject_put(wkinfo->kobj); -+ module_put(THIS_MODULE); -+ kfree(wkinfo); -+ } -+} -+ -+/* -+ * Since struct completion is large, try allocating it dynamically. -+ */ -+#if defined(CONFIG_4KSTACKS) || defined(AuTest4KSTACKS) -+#define AuWkqCompDeclare(name) struct completion *comp = NULL -+ -+static int au_wkq_comp_alloc(struct au_wkinfo *wkinfo, struct completion **comp) -+{ -+ *comp = kmalloc(sizeof(**comp), GFP_NOFS); -+ if (*comp) { -+ init_completion(*comp); -+ wkinfo->comp = *comp; -+ return 0; -+ } -+ return -ENOMEM; -+} -+ -+static void au_wkq_comp_free(struct completion *comp) -+{ -+ kfree(comp); -+} -+ -+#else -+ -+/* no braces */ -+#define AuWkqCompDeclare(name) \ -+ DECLARE_COMPLETION_ONSTACK(_ ## name); \ -+ struct completion *comp = &_ ## name -+ -+static int au_wkq_comp_alloc(struct au_wkinfo *wkinfo, struct completion **comp) -+{ -+ wkinfo->comp = *comp; -+ return 0; -+} -+ -+static void au_wkq_comp_free(struct completion *comp __maybe_unused) -+{ -+ /* empty */ -+} -+#endif /* 4KSTACKS */ -+ -+static void au_wkq_run(struct au_wkinfo *wkinfo, unsigned int flags) -+{ -+ struct workqueue_struct *wkq; -+ -+ au_dbg_verify_kthread(); -+ if (flags & AuWkq_WAIT) { -+ INIT_WORK_ONSTACK(&wkinfo->wk, wkq_func); -+ wkq = au_wkq[AuWkq_INORMAL].wkq; -+ if (flags & AuWkq_PRE) -+ wkq = au_wkq[AuWkq_IPRE].wkq; -+ queue_work(wkq, &wkinfo->wk); -+ } else { -+ INIT_WORK(&wkinfo->wk, wkq_func); -+ schedule_work(&wkinfo->wk); -+ } -+} -+ -+/* -+ * Be careful. It is easy to make deadlock happen. -+ * processA: lock, wkq and wait -+ * processB: wkq and wait, lock in wkq -+ * --> deadlock -+ */ -+int au_wkq_do_wait(unsigned int flags, au_wkq_func_t func, void *args) -+{ -+ int err; -+ AuWkqCompDeclare(comp); -+ struct au_wkinfo wkinfo = { -+ .flags = flags, -+ .func = func, -+ .args = args -+ }; -+ -+ err = au_wkq_comp_alloc(&wkinfo, &comp); -+ if (!err) { -+ au_wkq_run(&wkinfo, flags); -+ /* no timeout, no interrupt */ -+ wait_for_completion(wkinfo.comp); -+ au_wkq_comp_free(comp); -+ destroy_work_on_stack(&wkinfo.wk); -+ } -+ -+ return err; -+ -+} -+ -+/* -+ * Note: dget/dput() in func for aufs dentries are not supported. It will be a -+ * problem in a concurrent umounting. -+ */ -+int au_wkq_nowait(au_wkq_func_t func, void *args, struct super_block *sb) -+{ -+ int err; -+ struct au_wkinfo *wkinfo; -+ -+ atomic_inc(&au_sbi(sb)->si_nowait.nw_len); -+ -+ /* -+ * wkq_func() must free this wkinfo. -+ * it highly depends upon the implementation of workqueue. -+ */ -+ err = 0; -+ wkinfo = kmalloc(sizeof(*wkinfo), GFP_NOFS); -+ if (wkinfo) { -+ wkinfo->kobj = &au_sbi(sb)->si_kobj; -+ wkinfo->flags = !AuWkq_WAIT; -+ wkinfo->func = func; -+ wkinfo->args = args; -+ wkinfo->comp = NULL; -+ kobject_get(wkinfo->kobj); -+ __module_get(THIS_MODULE); -+ -+ au_wkq_run(wkinfo, !AuWkq_WAIT); -+ } else { -+ err = -ENOMEM; -+ au_nwt_done(&au_sbi(sb)->si_nowait); -+ } -+ -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+void au_nwt_init(struct au_nowait_tasks *nwt) -+{ -+ atomic_set(&nwt->nw_len, 0); -+ /* smp_mb(); */ /* atomic_set */ -+ init_waitqueue_head(&nwt->nw_wq); -+} -+ -+void au_wkq_fin(void) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(au_wkq); i++) -+ if (au_wkq[i].wkq) -+ destroy_workqueue(au_wkq[i].wkq); -+} -+ -+int __init au_wkq_init(void) -+{ -+ int err, i; -+ -+ err = 0; -+ for (i = 0; !err && i < ARRAY_SIZE(au_wkq); i++) { -+ BUILD_BUG_ON(!WQ_RESCUER); -+ au_wkq[i].wkq = alloc_workqueue(au_wkq[i].name, !WQ_RESCUER, -+ WQ_DFL_ACTIVE); -+ if (IS_ERR(au_wkq[i].wkq)) -+ err = PTR_ERR(au_wkq[i].wkq); -+ else if (!au_wkq[i].wkq) -+ err = -ENOMEM; -+ if (unlikely(err)) -+ au_wkq[i].wkq = NULL; -+ } -+ if (unlikely(err)) -+ au_wkq_fin(); -+ -+ return err; -+} -diff -Nur linux-2.6.37.orig/fs/aufs/wkq.h linux-2.6.37/fs/aufs/wkq.h ---- linux-2.6.37.orig/fs/aufs/wkq.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/wkq.h 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,90 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * workqueue for asynchronous/super-io operations -+ * todo: try new credentials management scheme -+ */ -+ -+#ifndef __AUFS_WKQ_H__ -+#define __AUFS_WKQ_H__ -+ -+#ifdef __KERNEL__ -+ -+#include -+#include -+#include -+ -+struct super_block; -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * in the next operation, wait for the 'nowait' tasks in system-wide workqueue -+ */ -+struct au_nowait_tasks { -+ atomic_t nw_len; -+ wait_queue_head_t nw_wq; -+}; -+ -+/* ---------------------------------------------------------------------- */ -+ -+typedef void (*au_wkq_func_t)(void *args); -+ -+/* wkq flags */ -+#define AuWkq_WAIT 1 -+#define AuWkq_PRE (1 << 1) -+#define au_ftest_wkq(flags, name) ((flags) & AuWkq_##name) -+#define au_fset_wkq(flags, name) \ -+ do { (flags) |= AuWkq_##name; } while (0) -+#define au_fclr_wkq(flags, name) \ -+ do { (flags) &= ~AuWkq_##name; } while (0) -+ -+/* wkq.c */ -+int au_wkq_do_wait(unsigned int flags, au_wkq_func_t func, void *args); -+int au_wkq_nowait(au_wkq_func_t func, void *args, struct super_block *sb); -+void au_nwt_init(struct au_nowait_tasks *nwt); -+int __init au_wkq_init(void); -+void au_wkq_fin(void); -+ -+/* ---------------------------------------------------------------------- */ -+ -+static inline int au_wkq_wait_pre(au_wkq_func_t func, void *args) -+{ -+ return au_wkq_do_wait(AuWkq_WAIT | AuWkq_PRE, func, args); -+} -+ -+static inline int au_wkq_wait(au_wkq_func_t func, void *args) -+{ -+ return au_wkq_do_wait(AuWkq_WAIT, func, args); -+} -+ -+static inline void au_nwt_done(struct au_nowait_tasks *nwt) -+{ -+ if (atomic_dec_and_test(&nwt->nw_len)) -+ wake_up_all(&nwt->nw_wq); -+} -+ -+static inline int au_nwt_flush(struct au_nowait_tasks *nwt) -+{ -+ wait_event(nwt->nw_wq, !atomic_read(&nwt->nw_len)); -+ return 0; -+} -+ -+#endif /* __KERNEL__ */ -+#endif /* __AUFS_WKQ_H__ */ -diff -Nur linux-2.6.37.orig/fs/aufs/xino.c linux-2.6.37/fs/aufs/xino.c ---- linux-2.6.37.orig/fs/aufs/xino.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/fs/aufs/xino.c 2011-01-11 20:15:11.000000000 +0100 -@@ -0,0 +1,1265 @@ -+/* -+ * Copyright (C) 2005-2011 Junjiro R. Okajima -+ * -+ * This program, aufs is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ */ -+ -+/* -+ * external inode number translation table and bitmap -+ */ -+ -+#include -+#include -+#include -+#include "aufs.h" -+ -+ssize_t xino_fread(au_readf_t func, struct file *file, void *kbuf, size_t size, -+ loff_t *pos) -+{ -+ ssize_t err; -+ mm_segment_t oldfs; -+ union { -+ void *k; -+ char __user *u; -+ } buf; -+ -+ buf.k = kbuf; -+ oldfs = get_fs(); -+ set_fs(KERNEL_DS); -+ do { -+ /* todo: signal_pending? */ -+ err = func(file, buf.u, size, pos); -+ } while (err == -EAGAIN || err == -EINTR); -+ set_fs(oldfs); -+ -+#if 0 /* reserved for future use */ -+ if (err > 0) -+ fsnotify_access(file->f_dentry); -+#endif -+ -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static ssize_t do_xino_fwrite(au_writef_t func, struct file *file, void *kbuf, -+ size_t size, loff_t *pos) -+{ -+ ssize_t err; -+ mm_segment_t oldfs; -+ union { -+ void *k; -+ const char __user *u; -+ } buf; -+ -+ buf.k = kbuf; -+ oldfs = get_fs(); -+ set_fs(KERNEL_DS); -+ do { -+ /* todo: signal_pending? */ -+ err = func(file, buf.u, size, pos); -+ } while (err == -EAGAIN || err == -EINTR); -+ set_fs(oldfs); -+ -+#if 0 /* reserved for future use */ -+ if (err > 0) -+ fsnotify_modify(file->f_dentry); -+#endif -+ -+ return err; -+} -+ -+struct do_xino_fwrite_args { -+ ssize_t *errp; -+ au_writef_t func; -+ struct file *file; -+ void *buf; -+ size_t size; -+ loff_t *pos; -+}; -+ -+static void call_do_xino_fwrite(void *args) -+{ -+ struct do_xino_fwrite_args *a = args; -+ *a->errp = do_xino_fwrite(a->func, a->file, a->buf, a->size, a->pos); -+} -+ -+ssize_t xino_fwrite(au_writef_t func, struct file *file, void *buf, size_t size, -+ loff_t *pos) -+{ -+ ssize_t err; -+ -+ /* todo: signal block and no wkq? */ -+ if (rlimit(RLIMIT_FSIZE) == RLIM_INFINITY) { -+ lockdep_off(); -+ err = do_xino_fwrite(func, file, buf, size, pos); -+ lockdep_on(); -+ } else { -+ /* -+ * it breaks RLIMIT_FSIZE and normal user's limit, -+ * users should care about quota and real 'filesystem full.' -+ */ -+ int wkq_err; -+ struct do_xino_fwrite_args args = { -+ .errp = &err, -+ .func = func, -+ .file = file, -+ .buf = buf, -+ .size = size, -+ .pos = pos -+ }; -+ -+ wkq_err = au_wkq_wait(call_do_xino_fwrite, &args); -+ if (unlikely(wkq_err)) -+ err = wkq_err; -+ } -+ -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * create a new xinofile at the same place/path as @base_file. -+ */ -+struct file *au_xino_create2(struct file *base_file, struct file *copy_src) -+{ -+ struct file *file; -+ struct dentry *base, *parent; -+ struct inode *dir; -+ struct qstr *name; -+ struct path path; -+ int err; -+ -+ base = base_file->f_dentry; -+ parent = base->d_parent; /* dir inode is locked */ -+ dir = parent->d_inode; -+ IMustLock(dir); -+ -+ file = ERR_PTR(-EINVAL); -+ name = &base->d_name; -+ path.dentry = vfsub_lookup_one_len(name->name, parent, name->len); -+ if (IS_ERR(path.dentry)) { -+ file = (void *)path.dentry; -+ pr_err("%.*s lookup err %ld\n", -+ AuLNPair(name), PTR_ERR(path.dentry)); -+ goto out; -+ } -+ -+ /* no need to mnt_want_write() since we call dentry_open() later */ -+ err = vfs_create(dir, path.dentry, S_IRUGO | S_IWUGO, NULL); -+ if (unlikely(err)) { -+ file = ERR_PTR(err); -+ pr_err("%.*s create err %d\n", AuLNPair(name), err); -+ goto out_dput; -+ } -+ -+ path.mnt = base_file->f_vfsmnt; -+ file = vfsub_dentry_open(&path, -+ O_RDWR | O_CREAT | O_EXCL | O_LARGEFILE -+ /* | FMODE_NONOTIFY */); -+ if (IS_ERR(file)) { -+ pr_err("%.*s open err %ld\n", AuLNPair(name), PTR_ERR(file)); -+ goto out_dput; -+ } -+ -+ err = vfsub_unlink(dir, &file->f_path, /*force*/0); -+ if (unlikely(err)) { -+ pr_err("%.*s unlink err %d\n", AuLNPair(name), err); -+ goto out_fput; -+ } -+ -+ if (copy_src) { -+ /* no one can touch copy_src xino */ -+ err = au_copy_file(file, copy_src, -+ i_size_read(copy_src->f_dentry->d_inode)); -+ if (unlikely(err)) { -+ pr_err("%.*s copy err %d\n", AuLNPair(name), err); -+ goto out_fput; -+ } -+ } -+ goto out_dput; /* success */ -+ -+out_fput: -+ fput(file); -+ file = ERR_PTR(err); -+out_dput: -+ dput(path.dentry); -+out: -+ return file; -+} -+ -+struct au_xino_lock_dir { -+ struct au_hinode *hdir; -+ struct dentry *parent; -+ struct mutex *mtx; -+}; -+ -+static void au_xino_lock_dir(struct super_block *sb, struct file *xino, -+ struct au_xino_lock_dir *ldir) -+{ -+ aufs_bindex_t brid, bindex; -+ -+ ldir->hdir = NULL; -+ bindex = -1; -+ brid = au_xino_brid(sb); -+ if (brid >= 0) -+ bindex = au_br_index(sb, brid); -+ if (bindex >= 0) { -+ ldir->hdir = au_hi(sb->s_root->d_inode, bindex); -+ au_hn_imtx_lock_nested(ldir->hdir, AuLsc_I_PARENT); -+ } else { -+ ldir->parent = dget_parent(xino->f_dentry); -+ ldir->mtx = &ldir->parent->d_inode->i_mutex; -+ mutex_lock_nested(ldir->mtx, AuLsc_I_PARENT); -+ } -+} -+ -+static void au_xino_unlock_dir(struct au_xino_lock_dir *ldir) -+{ -+ if (ldir->hdir) -+ au_hn_imtx_unlock(ldir->hdir); -+ else { -+ mutex_unlock(ldir->mtx); -+ dput(ldir->parent); -+ } -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* trucate xino files asynchronously */ -+ -+int au_xino_trunc(struct super_block *sb, aufs_bindex_t bindex) -+{ -+ int err; -+ aufs_bindex_t bi, bend; -+ struct au_branch *br; -+ struct file *new_xino, *file; -+ struct super_block *h_sb; -+ struct au_xino_lock_dir ldir; -+ -+ err = -EINVAL; -+ bend = au_sbend(sb); -+ if (unlikely(bindex < 0 || bend < bindex)) -+ goto out; -+ br = au_sbr(sb, bindex); -+ file = br->br_xino.xi_file; -+ if (!file) -+ goto out; -+ -+ au_xino_lock_dir(sb, file, &ldir); -+ /* mnt_want_write() is unnecessary here */ -+ new_xino = au_xino_create2(file, file); -+ au_xino_unlock_dir(&ldir); -+ err = PTR_ERR(new_xino); -+ if (IS_ERR(new_xino)) -+ goto out; -+ err = 0; -+ fput(file); -+ br->br_xino.xi_file = new_xino; -+ -+ h_sb = br->br_mnt->mnt_sb; -+ for (bi = 0; bi <= bend; bi++) { -+ if (unlikely(bi == bindex)) -+ continue; -+ br = au_sbr(sb, bi); -+ if (br->br_mnt->mnt_sb != h_sb) -+ continue; -+ -+ fput(br->br_xino.xi_file); -+ br->br_xino.xi_file = new_xino; -+ get_file(new_xino); -+ } -+ -+out: -+ return err; -+} -+ -+struct xino_do_trunc_args { -+ struct super_block *sb; -+ struct au_branch *br; -+}; -+ -+static void xino_do_trunc(void *_args) -+{ -+ struct xino_do_trunc_args *args = _args; -+ struct super_block *sb; -+ struct au_branch *br; -+ struct inode *dir; -+ int err; -+ aufs_bindex_t bindex; -+ -+ err = 0; -+ sb = args->sb; -+ dir = sb->s_root->d_inode; -+ br = args->br; -+ -+ si_noflush_write_lock(sb); -+ ii_read_lock_parent(dir); -+ bindex = au_br_index(sb, br->br_id); -+ err = au_xino_trunc(sb, bindex); -+ if (!err -+ && br->br_xino.xi_file->f_dentry->d_inode->i_blocks -+ >= br->br_xino_upper) -+ br->br_xino_upper += AUFS_XINO_TRUNC_STEP; -+ -+ ii_read_unlock(dir); -+ if (unlikely(err)) -+ pr_warning("err b%d, (%d)\n", bindex, err); -+ atomic_dec(&br->br_xino_running); -+ atomic_dec(&br->br_count); -+ si_write_unlock(sb); -+ au_nwt_done(&au_sbi(sb)->si_nowait); -+ kfree(args); -+} -+ -+static void xino_try_trunc(struct super_block *sb, struct au_branch *br) -+{ -+ struct xino_do_trunc_args *args; -+ int wkq_err; -+ -+ if (br->br_xino.xi_file->f_dentry->d_inode->i_blocks -+ < br->br_xino_upper) -+ return; -+ -+ if (atomic_inc_return(&br->br_xino_running) > 1) -+ goto out; -+ -+ /* lock and kfree() will be called in trunc_xino() */ -+ args = kmalloc(sizeof(*args), GFP_NOFS); -+ if (unlikely(!args)) { -+ AuErr1("no memory\n"); -+ goto out_args; -+ } -+ -+ atomic_inc(&br->br_count); -+ args->sb = sb; -+ args->br = br; -+ wkq_err = au_wkq_nowait(xino_do_trunc, args, sb); -+ if (!wkq_err) -+ return; /* success */ -+ -+ pr_err("wkq %d\n", wkq_err); -+ atomic_dec(&br->br_count); -+ -+out_args: -+ kfree(args); -+out: -+ atomic_dec(&br->br_xino_running); -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static int au_xino_do_write(au_writef_t write, struct file *file, -+ ino_t h_ino, ino_t ino) -+{ -+ loff_t pos; -+ ssize_t sz; -+ -+ pos = h_ino; -+ if (unlikely(au_loff_max / sizeof(ino) - 1 < pos)) { -+ AuIOErr1("too large hi%lu\n", (unsigned long)h_ino); -+ return -EFBIG; -+ } -+ pos *= sizeof(ino); -+ sz = xino_fwrite(write, file, &ino, sizeof(ino), &pos); -+ if (sz == sizeof(ino)) -+ return 0; /* success */ -+ -+ AuIOErr("write failed (%zd)\n", sz); -+ return -EIO; -+} -+ -+/* -+ * write @ino to the xinofile for the specified branch{@sb, @bindex} -+ * at the position of @h_ino. -+ * even if @ino is zero, it is written to the xinofile and means no entry. -+ * if the size of the xino file on a specific filesystem exceeds the watermark, -+ * try truncating it. -+ */ -+int au_xino_write(struct super_block *sb, aufs_bindex_t bindex, ino_t h_ino, -+ ino_t ino) -+{ -+ int err; -+ unsigned int mnt_flags; -+ struct au_branch *br; -+ -+ BUILD_BUG_ON(sizeof(long long) != sizeof(au_loff_max) -+ || ((loff_t)-1) > 0); -+ SiMustAnyLock(sb); -+ -+ mnt_flags = au_mntflags(sb); -+ if (!au_opt_test(mnt_flags, XINO)) -+ return 0; -+ -+ br = au_sbr(sb, bindex); -+ err = au_xino_do_write(au_sbi(sb)->si_xwrite, br->br_xino.xi_file, -+ h_ino, ino); -+ if (!err) { -+ if (au_opt_test(mnt_flags, TRUNC_XINO) -+ && au_test_fs_trunc_xino(br->br_mnt->mnt_sb)) -+ xino_try_trunc(sb, br); -+ return 0; /* success */ -+ } -+ -+ AuIOErr("write failed (%d)\n", err); -+ return -EIO; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* aufs inode number bitmap */ -+ -+static const int page_bits = (int)PAGE_SIZE * BITS_PER_BYTE; -+static ino_t xib_calc_ino(unsigned long pindex, int bit) -+{ -+ ino_t ino; -+ -+ AuDebugOn(bit < 0 || page_bits <= bit); -+ ino = AUFS_FIRST_INO + pindex * page_bits + bit; -+ return ino; -+} -+ -+static void xib_calc_bit(ino_t ino, unsigned long *pindex, int *bit) -+{ -+ AuDebugOn(ino < AUFS_FIRST_INO); -+ ino -= AUFS_FIRST_INO; -+ *pindex = ino / page_bits; -+ *bit = ino % page_bits; -+} -+ -+static int xib_pindex(struct super_block *sb, unsigned long pindex) -+{ -+ int err; -+ loff_t pos; -+ ssize_t sz; -+ struct au_sbinfo *sbinfo; -+ struct file *xib; -+ unsigned long *p; -+ -+ sbinfo = au_sbi(sb); -+ MtxMustLock(&sbinfo->si_xib_mtx); -+ AuDebugOn(pindex > ULONG_MAX / PAGE_SIZE -+ || !au_opt_test(sbinfo->si_mntflags, XINO)); -+ -+ if (pindex == sbinfo->si_xib_last_pindex) -+ return 0; -+ -+ xib = sbinfo->si_xib; -+ p = sbinfo->si_xib_buf; -+ pos = sbinfo->si_xib_last_pindex; -+ pos *= PAGE_SIZE; -+ sz = xino_fwrite(sbinfo->si_xwrite, xib, p, PAGE_SIZE, &pos); -+ if (unlikely(sz != PAGE_SIZE)) -+ goto out; -+ -+ pos = pindex; -+ pos *= PAGE_SIZE; -+ if (i_size_read(xib->f_dentry->d_inode) >= pos + PAGE_SIZE) -+ sz = xino_fread(sbinfo->si_xread, xib, p, PAGE_SIZE, &pos); -+ else { -+ memset(p, 0, PAGE_SIZE); -+ sz = xino_fwrite(sbinfo->si_xwrite, xib, p, PAGE_SIZE, &pos); -+ } -+ if (sz == PAGE_SIZE) { -+ sbinfo->si_xib_last_pindex = pindex; -+ return 0; /* success */ -+ } -+ -+out: -+ AuIOErr1("write failed (%zd)\n", sz); -+ err = sz; -+ if (sz >= 0) -+ err = -EIO; -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+static void au_xib_clear_bit(struct inode *inode) -+{ -+ int err, bit; -+ unsigned long pindex; -+ struct super_block *sb; -+ struct au_sbinfo *sbinfo; -+ -+ AuDebugOn(inode->i_nlink); -+ -+ sb = inode->i_sb; -+ xib_calc_bit(inode->i_ino, &pindex, &bit); -+ AuDebugOn(page_bits <= bit); -+ sbinfo = au_sbi(sb); -+ mutex_lock(&sbinfo->si_xib_mtx); -+ err = xib_pindex(sb, pindex); -+ if (!err) { -+ clear_bit(bit, sbinfo->si_xib_buf); -+ sbinfo->si_xib_next_bit = bit; -+ } -+ mutex_unlock(&sbinfo->si_xib_mtx); -+} -+ -+/* for s_op->delete_inode() */ -+void au_xino_delete_inode(struct inode *inode, const int unlinked) -+{ -+ int err; -+ unsigned int mnt_flags; -+ aufs_bindex_t bindex, bend, bi; -+ unsigned char try_trunc; -+ struct au_iinfo *iinfo; -+ struct super_block *sb; -+ struct au_hinode *hi; -+ struct inode *h_inode; -+ struct au_branch *br; -+ au_writef_t xwrite; -+ -+ sb = inode->i_sb; -+ mnt_flags = au_mntflags(sb); -+ if (!au_opt_test(mnt_flags, XINO) -+ || inode->i_ino == AUFS_ROOT_INO) -+ return; -+ -+ if (unlinked) { -+ au_xigen_inc(inode); -+ au_xib_clear_bit(inode); -+ } -+ -+ iinfo = au_ii(inode); -+ if (!iinfo) -+ return; -+ -+ bindex = iinfo->ii_bstart; -+ if (bindex < 0) -+ return; -+ -+ xwrite = au_sbi(sb)->si_xwrite; -+ try_trunc = !!au_opt_test(mnt_flags, TRUNC_XINO); -+ hi = iinfo->ii_hinode + bindex; -+ bend = iinfo->ii_bend; -+ for (; bindex <= bend; bindex++, hi++) { -+ h_inode = hi->hi_inode; -+ if (!h_inode -+ || (!unlinked && h_inode->i_nlink)) -+ continue; -+ -+ /* inode may not be revalidated */ -+ bi = au_br_index(sb, hi->hi_id); -+ if (bi < 0) -+ continue; -+ -+ br = au_sbr(sb, bi); -+ err = au_xino_do_write(xwrite, br->br_xino.xi_file, -+ h_inode->i_ino, /*ino*/0); -+ if (!err && try_trunc -+ && au_test_fs_trunc_xino(br->br_mnt->mnt_sb)) -+ xino_try_trunc(sb, br); -+ } -+} -+ -+/* get an unused inode number from bitmap */ -+ino_t au_xino_new_ino(struct super_block *sb) -+{ -+ ino_t ino; -+ unsigned long *p, pindex, ul, pend; -+ struct au_sbinfo *sbinfo; -+ struct file *file; -+ int free_bit, err; -+ -+ if (!au_opt_test(au_mntflags(sb), XINO)) -+ return iunique(sb, AUFS_FIRST_INO); -+ -+ sbinfo = au_sbi(sb); -+ mutex_lock(&sbinfo->si_xib_mtx); -+ p = sbinfo->si_xib_buf; -+ free_bit = sbinfo->si_xib_next_bit; -+ if (free_bit < page_bits && !test_bit(free_bit, p)) -+ goto out; /* success */ -+ free_bit = find_first_zero_bit(p, page_bits); -+ if (free_bit < page_bits) -+ goto out; /* success */ -+ -+ pindex = sbinfo->si_xib_last_pindex; -+ for (ul = pindex - 1; ul < ULONG_MAX; ul--) { -+ err = xib_pindex(sb, ul); -+ if (unlikely(err)) -+ goto out_err; -+ free_bit = find_first_zero_bit(p, page_bits); -+ if (free_bit < page_bits) -+ goto out; /* success */ -+ } -+ -+ file = sbinfo->si_xib; -+ pend = i_size_read(file->f_dentry->d_inode) / PAGE_SIZE; -+ for (ul = pindex + 1; ul <= pend; ul++) { -+ err = xib_pindex(sb, ul); -+ if (unlikely(err)) -+ goto out_err; -+ free_bit = find_first_zero_bit(p, page_bits); -+ if (free_bit < page_bits) -+ goto out; /* success */ -+ } -+ BUG(); -+ -+out: -+ set_bit(free_bit, p); -+ sbinfo->si_xib_next_bit = free_bit + 1; -+ pindex = sbinfo->si_xib_last_pindex; -+ mutex_unlock(&sbinfo->si_xib_mtx); -+ ino = xib_calc_ino(pindex, free_bit); -+ AuDbg("i%lu\n", (unsigned long)ino); -+ return ino; -+out_err: -+ mutex_unlock(&sbinfo->si_xib_mtx); -+ AuDbg("i0\n"); -+ return 0; -+} -+ -+/* -+ * read @ino from xinofile for the specified branch{@sb, @bindex} -+ * at the position of @h_ino. -+ * if @ino does not exist and @do_new is true, get new one. -+ */ -+int au_xino_read(struct super_block *sb, aufs_bindex_t bindex, ino_t h_ino, -+ ino_t *ino) -+{ -+ int err; -+ ssize_t sz; -+ loff_t pos; -+ struct file *file; -+ struct au_sbinfo *sbinfo; -+ -+ *ino = 0; -+ if (!au_opt_test(au_mntflags(sb), XINO)) -+ return 0; /* no xino */ -+ -+ err = 0; -+ sbinfo = au_sbi(sb); -+ pos = h_ino; -+ if (unlikely(au_loff_max / sizeof(*ino) - 1 < pos)) { -+ AuIOErr1("too large hi%lu\n", (unsigned long)h_ino); -+ return -EFBIG; -+ } -+ pos *= sizeof(*ino); -+ -+ file = au_sbr(sb, bindex)->br_xino.xi_file; -+ if (i_size_read(file->f_dentry->d_inode) < pos + sizeof(*ino)) -+ return 0; /* no ino */ -+ -+ sz = xino_fread(sbinfo->si_xread, file, ino, sizeof(*ino), &pos); -+ if (sz == sizeof(*ino)) -+ return 0; /* success */ -+ -+ err = sz; -+ if (unlikely(sz >= 0)) { -+ err = -EIO; -+ AuIOErr("xino read error (%zd)\n", sz); -+ } -+ -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* create and set a new xino file */ -+ -+struct file *au_xino_create(struct super_block *sb, char *fname, int silent) -+{ -+ struct file *file; -+ struct dentry *h_parent, *d; -+ struct inode *h_dir; -+ int err; -+ -+ /* -+ * at mount-time, and the xino file is the default path, -+ * hnotify is disabled so we have no notify events to ignore. -+ * when a user specified the xino, we cannot get au_hdir to be ignored. -+ */ -+ file = vfsub_filp_open(fname, O_RDWR | O_CREAT | O_EXCL | O_LARGEFILE -+ /* | FMODE_NONOTIFY */, -+ S_IRUGO | S_IWUGO); -+ if (IS_ERR(file)) { -+ if (!silent) -+ pr_err("open %s(%ld)\n", fname, PTR_ERR(file)); -+ return file; -+ } -+ -+ /* keep file count */ -+ h_parent = dget_parent(file->f_dentry); -+ h_dir = h_parent->d_inode; -+ mutex_lock_nested(&h_dir->i_mutex, AuLsc_I_PARENT); -+ /* mnt_want_write() is unnecessary here */ -+ err = vfsub_unlink(h_dir, &file->f_path, /*force*/0); -+ mutex_unlock(&h_dir->i_mutex); -+ dput(h_parent); -+ if (unlikely(err)) { -+ if (!silent) -+ pr_err("unlink %s(%d)\n", fname, err); -+ goto out; -+ } -+ -+ err = -EINVAL; -+ d = file->f_dentry; -+ if (unlikely(sb == d->d_sb)) { -+ if (!silent) -+ pr_err("%s must be outside\n", fname); -+ goto out; -+ } -+ if (unlikely(au_test_fs_bad_xino(d->d_sb))) { -+ if (!silent) -+ pr_err("xino doesn't support %s(%s)\n", -+ fname, au_sbtype(d->d_sb)); -+ goto out; -+ } -+ return file; /* success */ -+ -+out: -+ fput(file); -+ file = ERR_PTR(err); -+ return file; -+} -+ -+/* -+ * find another branch who is on the same filesystem of the specified -+ * branch{@btgt}. search until @bend. -+ */ -+static int is_sb_shared(struct super_block *sb, aufs_bindex_t btgt, -+ aufs_bindex_t bend) -+{ -+ aufs_bindex_t bindex; -+ struct super_block *tgt_sb = au_sbr_sb(sb, btgt); -+ -+ for (bindex = 0; bindex < btgt; bindex++) -+ if (unlikely(tgt_sb == au_sbr_sb(sb, bindex))) -+ return bindex; -+ for (bindex++; bindex <= bend; bindex++) -+ if (unlikely(tgt_sb == au_sbr_sb(sb, bindex))) -+ return bindex; -+ return -1; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * initialize the xinofile for the specified branch @br -+ * at the place/path where @base_file indicates. -+ * test whether another branch is on the same filesystem or not, -+ * if @do_test is true. -+ */ -+int au_xino_br(struct super_block *sb, struct au_branch *br, ino_t h_ino, -+ struct file *base_file, int do_test) -+{ -+ int err; -+ ino_t ino; -+ aufs_bindex_t bend, bindex; -+ struct au_branch *shared_br, *b; -+ struct file *file; -+ struct super_block *tgt_sb; -+ -+ shared_br = NULL; -+ bend = au_sbend(sb); -+ if (do_test) { -+ tgt_sb = br->br_mnt->mnt_sb; -+ for (bindex = 0; bindex <= bend; bindex++) { -+ b = au_sbr(sb, bindex); -+ if (tgt_sb == b->br_mnt->mnt_sb) { -+ shared_br = b; -+ break; -+ } -+ } -+ } -+ -+ if (!shared_br || !shared_br->br_xino.xi_file) { -+ struct au_xino_lock_dir ldir; -+ -+ au_xino_lock_dir(sb, base_file, &ldir); -+ /* mnt_want_write() is unnecessary here */ -+ file = au_xino_create2(base_file, NULL); -+ au_xino_unlock_dir(&ldir); -+ err = PTR_ERR(file); -+ if (IS_ERR(file)) -+ goto out; -+ br->br_xino.xi_file = file; -+ } else { -+ br->br_xino.xi_file = shared_br->br_xino.xi_file; -+ get_file(br->br_xino.xi_file); -+ } -+ -+ ino = AUFS_ROOT_INO; -+ err = au_xino_do_write(au_sbi(sb)->si_xwrite, br->br_xino.xi_file, -+ h_ino, ino); -+ if (unlikely(err)) { -+ fput(br->br_xino.xi_file); -+ br->br_xino.xi_file = NULL; -+ } -+ -+out: -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* trucate a xino bitmap file */ -+ -+/* todo: slow */ -+static int do_xib_restore(struct super_block *sb, struct file *file, void *page) -+{ -+ int err, bit; -+ ssize_t sz; -+ unsigned long pindex; -+ loff_t pos, pend; -+ struct au_sbinfo *sbinfo; -+ au_readf_t func; -+ ino_t *ino; -+ unsigned long *p; -+ -+ err = 0; -+ sbinfo = au_sbi(sb); -+ MtxMustLock(&sbinfo->si_xib_mtx); -+ p = sbinfo->si_xib_buf; -+ func = sbinfo->si_xread; -+ pend = i_size_read(file->f_dentry->d_inode); -+ pos = 0; -+ while (pos < pend) { -+ sz = xino_fread(func, file, page, PAGE_SIZE, &pos); -+ err = sz; -+ if (unlikely(sz <= 0)) -+ goto out; -+ -+ err = 0; -+ for (ino = page; sz > 0; ino++, sz -= sizeof(ino)) { -+ if (unlikely(*ino < AUFS_FIRST_INO)) -+ continue; -+ -+ xib_calc_bit(*ino, &pindex, &bit); -+ AuDebugOn(page_bits <= bit); -+ err = xib_pindex(sb, pindex); -+ if (!err) -+ set_bit(bit, p); -+ else -+ goto out; -+ } -+ } -+ -+out: -+ return err; -+} -+ -+static int xib_restore(struct super_block *sb) -+{ -+ int err; -+ aufs_bindex_t bindex, bend; -+ void *page; -+ -+ err = -ENOMEM; -+ page = (void *)__get_free_page(GFP_NOFS); -+ if (unlikely(!page)) -+ goto out; -+ -+ err = 0; -+ bend = au_sbend(sb); -+ for (bindex = 0; !err && bindex <= bend; bindex++) -+ if (!bindex || is_sb_shared(sb, bindex, bindex - 1) < 0) -+ err = do_xib_restore -+ (sb, au_sbr(sb, bindex)->br_xino.xi_file, page); -+ else -+ AuDbg("b%d\n", bindex); -+ free_page((unsigned long)page); -+ -+out: -+ return err; -+} -+ -+int au_xib_trunc(struct super_block *sb) -+{ -+ int err; -+ ssize_t sz; -+ loff_t pos; -+ struct au_xino_lock_dir ldir; -+ struct au_sbinfo *sbinfo; -+ unsigned long *p; -+ struct file *file; -+ -+ SiMustWriteLock(sb); -+ -+ err = 0; -+ sbinfo = au_sbi(sb); -+ if (!au_opt_test(sbinfo->si_mntflags, XINO)) -+ goto out; -+ -+ file = sbinfo->si_xib; -+ if (i_size_read(file->f_dentry->d_inode) <= PAGE_SIZE) -+ goto out; -+ -+ au_xino_lock_dir(sb, file, &ldir); -+ /* mnt_want_write() is unnecessary here */ -+ file = au_xino_create2(sbinfo->si_xib, NULL); -+ au_xino_unlock_dir(&ldir); -+ err = PTR_ERR(file); -+ if (IS_ERR(file)) -+ goto out; -+ fput(sbinfo->si_xib); -+ sbinfo->si_xib = file; -+ -+ p = sbinfo->si_xib_buf; -+ memset(p, 0, PAGE_SIZE); -+ pos = 0; -+ sz = xino_fwrite(sbinfo->si_xwrite, sbinfo->si_xib, p, PAGE_SIZE, &pos); -+ if (unlikely(sz != PAGE_SIZE)) { -+ err = sz; -+ AuIOErr("err %d\n", err); -+ if (sz >= 0) -+ err = -EIO; -+ goto out; -+ } -+ -+ mutex_lock(&sbinfo->si_xib_mtx); -+ /* mnt_want_write() is unnecessary here */ -+ err = xib_restore(sb); -+ mutex_unlock(&sbinfo->si_xib_mtx); -+ -+out: -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * xino mount option handlers -+ */ -+static au_readf_t find_readf(struct file *h_file) -+{ -+ const struct file_operations *fop = h_file->f_op; -+ -+ if (fop) { -+ if (fop->read) -+ return fop->read; -+ if (fop->aio_read) -+ return do_sync_read; -+ } -+ return ERR_PTR(-ENOSYS); -+} -+ -+static au_writef_t find_writef(struct file *h_file) -+{ -+ const struct file_operations *fop = h_file->f_op; -+ -+ if (fop) { -+ if (fop->write) -+ return fop->write; -+ if (fop->aio_write) -+ return do_sync_write; -+ } -+ return ERR_PTR(-ENOSYS); -+} -+ -+/* xino bitmap */ -+static void xino_clear_xib(struct super_block *sb) -+{ -+ struct au_sbinfo *sbinfo; -+ -+ SiMustWriteLock(sb); -+ -+ sbinfo = au_sbi(sb); -+ sbinfo->si_xread = NULL; -+ sbinfo->si_xwrite = NULL; -+ if (sbinfo->si_xib) -+ fput(sbinfo->si_xib); -+ sbinfo->si_xib = NULL; -+ free_page((unsigned long)sbinfo->si_xib_buf); -+ sbinfo->si_xib_buf = NULL; -+} -+ -+static int au_xino_set_xib(struct super_block *sb, struct file *base) -+{ -+ int err; -+ loff_t pos; -+ struct au_sbinfo *sbinfo; -+ struct file *file; -+ -+ SiMustWriteLock(sb); -+ -+ sbinfo = au_sbi(sb); -+ file = au_xino_create2(base, sbinfo->si_xib); -+ err = PTR_ERR(file); -+ if (IS_ERR(file)) -+ goto out; -+ if (sbinfo->si_xib) -+ fput(sbinfo->si_xib); -+ sbinfo->si_xib = file; -+ sbinfo->si_xread = find_readf(file); -+ sbinfo->si_xwrite = find_writef(file); -+ -+ err = -ENOMEM; -+ if (!sbinfo->si_xib_buf) -+ sbinfo->si_xib_buf = (void *)get_zeroed_page(GFP_NOFS); -+ if (unlikely(!sbinfo->si_xib_buf)) -+ goto out_unset; -+ -+ sbinfo->si_xib_last_pindex = 0; -+ sbinfo->si_xib_next_bit = 0; -+ if (i_size_read(file->f_dentry->d_inode) < PAGE_SIZE) { -+ pos = 0; -+ err = xino_fwrite(sbinfo->si_xwrite, file, sbinfo->si_xib_buf, -+ PAGE_SIZE, &pos); -+ if (unlikely(err != PAGE_SIZE)) -+ goto out_free; -+ } -+ err = 0; -+ goto out; /* success */ -+ -+out_free: -+ free_page((unsigned long)sbinfo->si_xib_buf); -+ sbinfo->si_xib_buf = NULL; -+ if (err >= 0) -+ err = -EIO; -+out_unset: -+ fput(sbinfo->si_xib); -+ sbinfo->si_xib = NULL; -+ sbinfo->si_xread = NULL; -+ sbinfo->si_xwrite = NULL; -+out: -+ return err; -+} -+ -+/* xino for each branch */ -+static void xino_clear_br(struct super_block *sb) -+{ -+ aufs_bindex_t bindex, bend; -+ struct au_branch *br; -+ -+ bend = au_sbend(sb); -+ for (bindex = 0; bindex <= bend; bindex++) { -+ br = au_sbr(sb, bindex); -+ if (!br || !br->br_xino.xi_file) -+ continue; -+ -+ fput(br->br_xino.xi_file); -+ br->br_xino.xi_file = NULL; -+ } -+} -+ -+static int au_xino_set_br(struct super_block *sb, struct file *base) -+{ -+ int err; -+ ino_t ino; -+ aufs_bindex_t bindex, bend, bshared; -+ struct { -+ struct file *old, *new; -+ } *fpair, *p; -+ struct au_branch *br; -+ struct inode *inode; -+ au_writef_t writef; -+ -+ SiMustWriteLock(sb); -+ -+ err = -ENOMEM; -+ bend = au_sbend(sb); -+ fpair = kcalloc(bend + 1, sizeof(*fpair), GFP_NOFS); -+ if (unlikely(!fpair)) -+ goto out; -+ -+ inode = sb->s_root->d_inode; -+ ino = AUFS_ROOT_INO; -+ writef = au_sbi(sb)->si_xwrite; -+ for (bindex = 0, p = fpair; bindex <= bend; bindex++, p++) { -+ br = au_sbr(sb, bindex); -+ bshared = is_sb_shared(sb, bindex, bindex - 1); -+ if (bshared >= 0) { -+ /* shared xino */ -+ *p = fpair[bshared]; -+ get_file(p->new); -+ } -+ -+ if (!p->new) { -+ /* new xino */ -+ p->old = br->br_xino.xi_file; -+ p->new = au_xino_create2(base, br->br_xino.xi_file); -+ err = PTR_ERR(p->new); -+ if (IS_ERR(p->new)) { -+ p->new = NULL; -+ goto out_pair; -+ } -+ } -+ -+ err = au_xino_do_write(writef, p->new, -+ au_h_iptr(inode, bindex)->i_ino, ino); -+ if (unlikely(err)) -+ goto out_pair; -+ } -+ -+ for (bindex = 0, p = fpair; bindex <= bend; bindex++, p++) { -+ br = au_sbr(sb, bindex); -+ if (br->br_xino.xi_file) -+ fput(br->br_xino.xi_file); -+ get_file(p->new); -+ br->br_xino.xi_file = p->new; -+ } -+ -+out_pair: -+ for (bindex = 0, p = fpair; bindex <= bend; bindex++, p++) -+ if (p->new) -+ fput(p->new); -+ else -+ break; -+ kfree(fpair); -+out: -+ return err; -+} -+ -+void au_xino_clr(struct super_block *sb) -+{ -+ struct au_sbinfo *sbinfo; -+ -+ au_xigen_clr(sb); -+ xino_clear_xib(sb); -+ xino_clear_br(sb); -+ sbinfo = au_sbi(sb); -+ /* lvalue, do not call au_mntflags() */ -+ au_opt_clr(sbinfo->si_mntflags, XINO); -+} -+ -+int au_xino_set(struct super_block *sb, struct au_opt_xino *xino, int remount) -+{ -+ int err, skip; -+ struct dentry *parent, *cur_parent; -+ struct qstr *dname, *cur_name; -+ struct file *cur_xino; -+ struct inode *dir; -+ struct au_sbinfo *sbinfo; -+ -+ SiMustWriteLock(sb); -+ -+ err = 0; -+ sbinfo = au_sbi(sb); -+ parent = dget_parent(xino->file->f_dentry); -+ if (remount) { -+ skip = 0; -+ dname = &xino->file->f_dentry->d_name; -+ cur_xino = sbinfo->si_xib; -+ if (cur_xino) { -+ cur_parent = dget_parent(cur_xino->f_dentry); -+ cur_name = &cur_xino->f_dentry->d_name; -+ skip = (cur_parent == parent -+ && dname->len == cur_name->len -+ && !memcmp(dname->name, cur_name->name, -+ dname->len)); -+ dput(cur_parent); -+ } -+ if (skip) -+ goto out; -+ } -+ -+ au_opt_set(sbinfo->si_mntflags, XINO); -+ dir = parent->d_inode; -+ mutex_lock_nested(&dir->i_mutex, AuLsc_I_PARENT); -+ /* mnt_want_write() is unnecessary here */ -+ err = au_xino_set_xib(sb, xino->file); -+ if (!err) -+ err = au_xigen_set(sb, xino->file); -+ if (!err) -+ err = au_xino_set_br(sb, xino->file); -+ mutex_unlock(&dir->i_mutex); -+ if (!err) -+ goto out; /* success */ -+ -+ /* reset all */ -+ AuIOErr("failed creating xino(%d).\n", err); -+ -+out: -+ dput(parent); -+ return err; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+/* -+ * create a xinofile at the default place/path. -+ */ -+struct file *au_xino_def(struct super_block *sb) -+{ -+ struct file *file; -+ char *page, *p; -+ struct au_branch *br; -+ struct super_block *h_sb; -+ struct path path; -+ aufs_bindex_t bend, bindex, bwr; -+ -+ br = NULL; -+ bend = au_sbend(sb); -+ bwr = -1; -+ for (bindex = 0; bindex <= bend; bindex++) { -+ br = au_sbr(sb, bindex); -+ if (au_br_writable(br->br_perm) -+ && !au_test_fs_bad_xino(br->br_mnt->mnt_sb)) { -+ bwr = bindex; -+ break; -+ } -+ } -+ -+ if (bwr >= 0) { -+ file = ERR_PTR(-ENOMEM); -+ page = __getname_gfp(GFP_NOFS); -+ if (unlikely(!page)) -+ goto out; -+ path.mnt = br->br_mnt; -+ path.dentry = au_h_dptr(sb->s_root, bwr); -+ p = d_path(&path, page, PATH_MAX - sizeof(AUFS_XINO_FNAME)); -+ file = (void *)p; -+ if (!IS_ERR(p)) { -+ strcat(p, "/" AUFS_XINO_FNAME); -+ AuDbg("%s\n", p); -+ file = au_xino_create(sb, p, /*silent*/0); -+ if (!IS_ERR(file)) -+ au_xino_brid_set(sb, br->br_id); -+ } -+ __putname(page); -+ } else { -+ file = au_xino_create(sb, AUFS_XINO_DEFPATH, /*silent*/0); -+ if (IS_ERR(file)) -+ goto out; -+ h_sb = file->f_dentry->d_sb; -+ if (unlikely(au_test_fs_bad_xino(h_sb))) { -+ pr_err("xino doesn't support %s(%s)\n", -+ AUFS_XINO_DEFPATH, au_sbtype(h_sb)); -+ fput(file); -+ file = ERR_PTR(-EINVAL); -+ } -+ if (!IS_ERR(file)) -+ au_xino_brid_set(sb, -1); -+ } -+ -+out: -+ return file; -+} -+ -+/* ---------------------------------------------------------------------- */ -+ -+int au_xino_path(struct seq_file *seq, struct file *file) -+{ -+ int err; -+ -+ err = au_seq_path(seq, &file->f_path); -+ if (unlikely(err < 0)) -+ goto out; -+ -+ err = 0; -+#define Deleted "\\040(deleted)" -+ seq->count -= sizeof(Deleted) - 1; -+ AuDebugOn(memcmp(seq->buf + seq->count, Deleted, -+ sizeof(Deleted) - 1)); -+#undef Deleted -+ -+out: -+ return err; -+} -diff -Nur linux-2.6.37.orig/fs/file_table.c linux-2.6.37/fs/file_table.c ---- linux-2.6.37.orig/fs/file_table.c 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/fs/file_table.c 2011-01-11 20:15:11.000000000 +0100 -@@ -393,6 +393,8 @@ - } - } - -+EXPORT_SYMBOL(file_sb_list_del); -+ - #ifdef CONFIG_SMP - - /* -diff -Nur linux-2.6.37.orig/fs/inode.c linux-2.6.37/fs/inode.c ---- linux-2.6.37.orig/fs/inode.c 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/fs/inode.c 2011-01-11 20:15:11.000000000 +0100 -@@ -82,6 +82,7 @@ - * the i_state of an inode while it is in use.. - */ - DEFINE_SPINLOCK(inode_lock); -+EXPORT_SYMBOL(inode_lock); - - /* - * iprune_sem provides exclusion between the kswapd or try_to_free_pages -diff -Nur linux-2.6.37.orig/fs/namei.c linux-2.6.37/fs/namei.c ---- linux-2.6.37.orig/fs/namei.c 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/fs/namei.c 2011-01-11 20:15:11.000000000 +0100 -@@ -347,6 +347,7 @@ - - return 0; - } -+EXPORT_SYMBOL(deny_write_access); - - /** - * path_get - get a reference to a path -@@ -1161,12 +1162,13 @@ - * needs parent already locked. Doesn't follow mounts. - * SMP-safe. - */ --static struct dentry *lookup_hash(struct nameidata *nd) -+struct dentry *lookup_hash(struct nameidata *nd) - { - return __lookup_hash(&nd->last, nd->path.dentry, nd); - } -+EXPORT_SYMBOL(lookup_hash); - --static int __lookup_one_len(const char *name, struct qstr *this, -+int __lookup_one_len(const char *name, struct qstr *this, - struct dentry *base, int len) - { - unsigned long hash; -@@ -1187,6 +1189,7 @@ - this->hash = end_name_hash(hash); - return 0; - } -+EXPORT_SYMBOL(__lookup_one_len); - - /** - * lookup_one_len - filesystem helper to lookup single pathname component -diff -Nur linux-2.6.37.orig/fs/namespace.c linux-2.6.37/fs/namespace.c ---- linux-2.6.37.orig/fs/namespace.c 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/fs/namespace.c 2011-01-11 20:15:13.000000000 +0100 -@@ -1321,6 +1321,7 @@ - } - return 0; - } -+EXPORT_SYMBOL(iterate_mounts); - - static void cleanup_group_ids(struct vfsmount *mnt, struct vfsmount *end) - { -diff -Nur linux-2.6.37.orig/fs/notify/group.c linux-2.6.37/fs/notify/group.c ---- linux-2.6.37.orig/fs/notify/group.c 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/fs/notify/group.c 2011-01-11 20:15:13.000000000 +0100 -@@ -22,6 +22,7 @@ - #include - #include - #include -+#include - - #include - #include "fsnotify.h" -@@ -70,6 +71,7 @@ - if (atomic_dec_and_test(&group->refcnt)) - fsnotify_destroy_group(group); - } -+EXPORT_SYMBOL(fsnotify_put_group); - - /* - * Create a new fsnotify_group and hold a reference for the group returned. -@@ -102,3 +104,4 @@ - - return group; - } -+EXPORT_SYMBOL(fsnotify_alloc_group); -diff -Nur linux-2.6.37.orig/fs/notify/mark.c linux-2.6.37/fs/notify/mark.c ---- linux-2.6.37.orig/fs/notify/mark.c 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/fs/notify/mark.c 2011-01-11 20:15:13.000000000 +0100 -@@ -113,6 +113,7 @@ - if (atomic_dec_and_test(&mark->refcnt)) - mark->free_mark(mark); - } -+EXPORT_SYMBOL(fsnotify_put_mark); - - /* - * Any time a mark is getting freed we end up here. -@@ -190,6 +191,7 @@ - if (unlikely(atomic_dec_and_test(&group->num_marks))) - fsnotify_final_destroy_group(group); - } -+EXPORT_SYMBOL(fsnotify_destroy_mark); - - void fsnotify_set_mark_mask_locked(struct fsnotify_mark *mark, __u32 mask) - { -@@ -277,6 +279,7 @@ - - return ret; - } -+EXPORT_SYMBOL(fsnotify_add_mark); - - /* - * clear any marks in a group in which mark->flags & flags is true -@@ -332,6 +335,7 @@ - atomic_set(&mark->refcnt, 1); - mark->free_mark = free_mark; - } -+EXPORT_SYMBOL(fsnotify_init_mark); - - static int fsnotify_mark_destroy(void *ignored) - { -diff -Nur linux-2.6.37.orig/fs/open.c linux-2.6.37/fs/open.c ---- linux-2.6.37.orig/fs/open.c 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/fs/open.c 2011-01-11 20:15:13.000000000 +0100 -@@ -60,6 +60,7 @@ - mutex_unlock(&dentry->d_inode->i_mutex); - return ret; - } -+EXPORT_SYMBOL(do_truncate); - - static long do_sys_truncate(const char __user *pathname, loff_t length) - { -diff -Nur linux-2.6.37.orig/fs/splice.c linux-2.6.37/fs/splice.c ---- linux-2.6.37.orig/fs/splice.c 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/fs/splice.c 2011-01-11 20:15:13.000000000 +0100 -@@ -1092,8 +1092,8 @@ - /* - * Attempt to initiate a splice from pipe to file. - */ --static long do_splice_from(struct pipe_inode_info *pipe, struct file *out, -- loff_t *ppos, size_t len, unsigned int flags) -+long do_splice_from(struct pipe_inode_info *pipe, struct file *out, -+ loff_t *ppos, size_t len, unsigned int flags) - { - ssize_t (*splice_write)(struct pipe_inode_info *, struct file *, - loff_t *, size_t, unsigned int); -@@ -1116,13 +1116,14 @@ - - return splice_write(pipe, out, ppos, len, flags); - } -+EXPORT_SYMBOL(do_splice_from); - - /* - * Attempt to initiate a splice from a file to a pipe. - */ --static long do_splice_to(struct file *in, loff_t *ppos, -- struct pipe_inode_info *pipe, size_t len, -- unsigned int flags) -+long do_splice_to(struct file *in, loff_t *ppos, -+ struct pipe_inode_info *pipe, size_t len, -+ unsigned int flags) - { - ssize_t (*splice_read)(struct file *, loff_t *, - struct pipe_inode_info *, size_t, unsigned int); -@@ -1142,6 +1143,7 @@ - - return splice_read(in, ppos, pipe, len, flags); - } -+EXPORT_SYMBOL(do_splice_to); - - /** - * splice_direct_to_actor - splices data directly between two non-pipes -diff -Nur linux-2.6.37.orig/security/commoncap.c linux-2.6.37/security/commoncap.c ---- linux-2.6.37.orig/security/commoncap.c 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/security/commoncap.c 2011-01-11 20:15:13.000000000 +0100 -@@ -929,3 +929,4 @@ - } - return ret; - } -+EXPORT_SYMBOL(cap_file_mmap); -diff -Nur linux-2.6.37.orig/security/device_cgroup.c linux-2.6.37/security/device_cgroup.c ---- linux-2.6.37.orig/security/device_cgroup.c 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/security/device_cgroup.c 2011-01-11 20:15:13.000000000 +0100 -@@ -515,6 +515,7 @@ - - return -EPERM; - } -+EXPORT_SYMBOL(devcgroup_inode_permission); - - int devcgroup_inode_mknod(int mode, dev_t dev) - { -diff -Nur linux-2.6.37.orig/security/security.c linux-2.6.37/security/security.c ---- linux-2.6.37.orig/security/security.c 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/security/security.c 2011-01-11 20:15:13.000000000 +0100 -@@ -360,6 +360,7 @@ - return 0; - return security_ops->path_mkdir(dir, dentry, mode); - } -+EXPORT_SYMBOL(security_path_mkdir); - - int security_path_rmdir(struct path *dir, struct dentry *dentry) - { -@@ -367,6 +368,7 @@ - return 0; - return security_ops->path_rmdir(dir, dentry); - } -+EXPORT_SYMBOL(security_path_rmdir); - - int security_path_unlink(struct path *dir, struct dentry *dentry) - { -@@ -374,6 +376,7 @@ - return 0; - return security_ops->path_unlink(dir, dentry); - } -+EXPORT_SYMBOL(security_path_unlink); - - int security_path_symlink(struct path *dir, struct dentry *dentry, - const char *old_name) -@@ -382,6 +385,7 @@ - return 0; - return security_ops->path_symlink(dir, dentry, old_name); - } -+EXPORT_SYMBOL(security_path_symlink); - - int security_path_link(struct dentry *old_dentry, struct path *new_dir, - struct dentry *new_dentry) -@@ -390,6 +394,7 @@ - return 0; - return security_ops->path_link(old_dentry, new_dir, new_dentry); - } -+EXPORT_SYMBOL(security_path_link); - - int security_path_rename(struct path *old_dir, struct dentry *old_dentry, - struct path *new_dir, struct dentry *new_dentry) -@@ -400,6 +405,7 @@ - return security_ops->path_rename(old_dir, old_dentry, new_dir, - new_dentry); - } -+EXPORT_SYMBOL(security_path_rename); - - int security_path_truncate(struct path *path) - { -@@ -407,6 +413,7 @@ - return 0; - return security_ops->path_truncate(path); - } -+EXPORT_SYMBOL(security_path_truncate); - - int security_path_chmod(struct dentry *dentry, struct vfsmount *mnt, - mode_t mode) -@@ -415,6 +422,7 @@ - return 0; - return security_ops->path_chmod(dentry, mnt, mode); - } -+EXPORT_SYMBOL(security_path_chmod); - - int security_path_chown(struct path *path, uid_t uid, gid_t gid) - { -@@ -422,6 +430,7 @@ - return 0; - return security_ops->path_chown(path, uid, gid); - } -+EXPORT_SYMBOL(security_path_chown); - - int security_path_chroot(struct path *path) - { -@@ -498,6 +507,7 @@ - return 0; - return security_ops->inode_readlink(dentry); - } -+EXPORT_SYMBOL(security_inode_readlink); - - int security_inode_follow_link(struct dentry *dentry, struct nameidata *nd) - { -@@ -512,6 +522,7 @@ - return 0; - return security_ops->inode_permission(inode, mask); - } -+EXPORT_SYMBOL(security_inode_permission); - - int security_inode_setattr(struct dentry *dentry, struct iattr *attr) - { -@@ -611,6 +622,7 @@ - - return fsnotify_perm(file, mask); - } -+EXPORT_SYMBOL(security_file_permission); - - int security_file_alloc(struct file *file) - { -@@ -638,6 +650,7 @@ - return ret; - return ima_file_mmap(file, prot); - } -+EXPORT_SYMBOL(security_file_mmap); - - int security_file_mprotect(struct vm_area_struct *vma, unsigned long reqprot, - unsigned long prot) diff --git a/target/linux/patches/2.6.37/brcm.patch b/target/linux/patches/2.6.37/brcm.patch deleted file mode 100644 index e1f0ecbde..000000000 --- a/target/linux/patches/2.6.37/brcm.patch +++ /dev/null @@ -1,396 +0,0 @@ -diff -Nur linux-2.6.37.orig/arch/mips/bcm47xx/Makefile linux-2.6.37/arch/mips/bcm47xx/Makefile ---- linux-2.6.37.orig/arch/mips/bcm47xx/Makefile 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/mips/bcm47xx/Makefile 2011-04-26 20:26:19.777672932 +0200 -@@ -3,4 +3,4 @@ - # under Linux. - # - --obj-y := gpio.o irq.o nvram.o prom.o serial.o setup.o time.o wgt634u.o -+obj-y := gpio.o irq.o nvram.o prom.o serial.o setup.o time.o platform.o -diff -Nur linux-2.6.37.orig/arch/mips/bcm47xx/platform.c linux-2.6.37/arch/mips/bcm47xx/platform.c ---- linux-2.6.37.orig/arch/mips/bcm47xx/platform.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/bcm47xx/platform.c 2011-04-27 09:51:38.177664121 +0200 -@@ -0,0 +1,146 @@ -+/* -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 2010, 2011 Waldemar Brodkorb -+ * Copyright © 2007, 2011 Thorsten Glaser -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#define CFGFS_FLASH_SIZE (128 * 1024) -+ -+static struct mtd_partition bcm47xx_partitions[] = { -+#define SLOT_CFE 0 -+ { -+ .name = "cfe", -+ .offset = 0, -+ .size = BCM47XX_OVERRIDE_CFESIZE, -+ .mask_flags = MTD_WRITEABLE /* force read-only */ -+ }, -+#define SLOT_LINUX 1 -+ { -+ .name = "linux", -+ .offset = 0, -+ .size = 0, -+ }, -+#define SLOT_ROOTFS 2 -+ { -+ .name = "rootfs", -+ .offset = 0, -+ .size = 0, -+ }, -+#define SLOT_CFGFS 3 -+ { -+ .name = "cfgfs", -+ .offset = 0, -+ .size = 0, -+ }, -+#define SLOT_NVRAM 4 -+ { -+ .name = "nvram", -+ .offset = 0, -+ .size = 0, -+ }, -+}; -+ -+static struct physmap_flash_data bcm47xx_flash_data = { -+ .parts = bcm47xx_partitions, -+ .nr_parts = ARRAY_SIZE(bcm47xx_partitions) -+}; -+ -+static struct resource bcm47xx_flash_resource = { -+ .flags = IORESOURCE_MEM, -+}; -+ -+static struct platform_device bcm47xx_flash = { -+ .name = "physmap-flash", -+ .id = 0, -+ .dev = { .platform_data = &bcm47xx_flash_data, }, -+ .resource = &bcm47xx_flash_resource, -+ .num_resources = 1, -+}; -+ -+static struct platform_device *bcm47xx_devices[] __initdata = { -+ &bcm47xx_flash, -+}; -+ -+struct bcm47xx_trx_header { -+#define BCM47XX_TRX_MAGIC 0x30524448 -+ u32 magic; -+ u32 len; -+ u32 crc32; -+ u32 flag_version; -+ u32 offsets[3]; -+}; -+ -+#define UPTODOWN(slot, psize) do { \ -+ posn -= psize; left -= psize; \ -+ bcm47xx_partitions[slot].offset = posn; \ -+ bcm47xx_partitions[slot].size = psize; \ -+} while (/* CONSTCOND */ 0) -+ -+static int __init bcm47xx_register_devices(void) -+{ -+ u32 flash_size; -+ size_t left, posn; -+ struct ssb_mipscore *mcore = &ssb_bcm47xx.mipscore; -+ struct bcm47xx_trx_header *trx_hdr; -+ -+ trx_hdr = (void *)KSEG1ADDR(mcore->flash_window + BCM47XX_OVERRIDE_CFESIZE); -+ -+ /* devices might have 2, 4 or 8 MB flash size */ -+#ifdef BCM47XX_OVERRIDE_FLASHSIZE -+ flash_size = BCM47XX_OVERRIDE_FLASHSIZE; -+ mcore->flash_window_size = flash_size; -+#define BCM47XX_OVERRODE_FLASHSIZE " (overridden)" -+#else -+ flash_size = mcore->flash_window_size; -+#define BCM47XX_OVERRODE_FLASHSIZE "" -+#endif -+ printk(KERN_INFO "FLASH SIZE%s: %x\n", BCM47XX_OVERRODE_FLASHSIZE, -+ flash_size); -+ -+ left = flash_size - BCM47XX_OVERRIDE_CFESIZE; -+ posn = flash_size; -+ UPTODOWN(SLOT_NVRAM, BCM47XX_OVERRIDE_NVRAMSIZE); -+ UPTODOWN(SLOT_CFGFS, CFGFS_FLASH_SIZE); -+ bcm47xx_partitions[SLOT_LINUX].offset = BCM47XX_OVERRIDE_CFESIZE; -+ bcm47xx_partitions[SLOT_LINUX].size = left; -+ -+ if (trx_hdr->magic == BCM47XX_TRX_MAGIC) { -+ bcm47xx_partitions[SLOT_ROOTFS].offset = -+ bcm47xx_partitions[SLOT_LINUX].offset + -+ trx_hdr->offsets[1]; -+ bcm47xx_partitions[SLOT_ROOTFS].size = -+ bcm47xx_partitions[SLOT_LINUX].size - -+ trx_hdr->offsets[1]; -+ } else -+ printk("bcm47xx/platform: no TRX header found\n"); -+ -+ printk(KERN_INFO "=== Flash map dump ===\n"); -+ for (posn = 0; posn < bcm47xx_flash_data.nr_parts; ++posn) -+ printk(KERN_INFO " #%u %08X @%08X '%s'\n", -+ (unsigned int)posn, -+ (unsigned int)bcm47xx_partitions[posn].size, -+ (unsigned int)bcm47xx_partitions[posn].offset, -+ bcm47xx_partitions[posn].name); -+ printk(KERN_INFO "=== Hope this works, have a nice day\n"); -+ -+ bcm47xx_flash_data.width = mcore->flash_buswidth; -+ bcm47xx_flash_resource.start = mcore->flash_window; -+ bcm47xx_flash_resource.end = mcore->flash_window -+ + mcore->flash_window_size -+ - 1; -+ return platform_add_devices(bcm47xx_devices, -+ ARRAY_SIZE(bcm47xx_devices)); -+} -+ -+device_initcall(bcm47xx_register_devices); -diff -Nur linux-2.6.37.orig/arch/mips/boot/compressed/Makefile linux-2.6.37/arch/mips/boot/compressed/Makefile ---- linux-2.6.37.orig/arch/mips/boot/compressed/Makefile 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/mips/boot/compressed/Makefile 2011-04-26 20:44:04.607661119 +0200 -@@ -58,8 +58,13 @@ - # Calculate the load address of the compressed kernel image - hostprogs-y := calc_vmlinuz_load_addr - -+ifdef CONFIG_BCM47XX -+# XXX just after CFE, just pray the address is static -+VMLINUZ_LOAD_ADDRESS = 0xffffffff80480000 -+else - VMLINUZ_LOAD_ADDRESS = $(shell $(obj)/calc_vmlinuz_load_addr \ - $(obj)/vmlinux.bin $(VMLINUX_LOAD_ADDRESS)) -+endif - - vmlinuzobjs-y += $(obj)/piggy.o - -@@ -105,4 +110,12 @@ - vmlinuz.srec: vmlinuz - $(call cmd,objcopy) - --clean-files := $(objtree)/vmlinuz $(objtree)/vmlinuz.{32,ecoff,bin,srec} -+AFLAGS_selfreloc.o := -DVMLINUZ_LOAD_ADDRESS=$(VMLINUZ_LOAD_ADDRESS) -+CPPFLAGS_selfreloc.lds := $(KBUILD_CFLAGS) -+ -+arch/mips/boot/compressed/selfreloc.o: arch/mips/boot/compressed/selfreloc.S vmlinuz.bin FORCE -+ -+vmlinuz.elf: arch/mips/boot/compressed/selfreloc.o arch/mips/boot/compressed/selfreloc.lds FORCE -+ $(LD) $(LDFLAGS) -T arch/mips/boot/compressed/selfreloc.lds arch/mips/boot/compressed/selfreloc.o -o $@ -+ -+clean-files := $(objtree)/vmlinuz $(objtree)/vmlinuz.{32,ecoff,bin,srec,elf} $(objtree)/arch/mips/boot/compressed/selfreloc.{o,lds} -diff -Nur linux-2.6.37.orig/arch/mips/boot/compressed/selfreloc.lds.S linux-2.6.37/arch/mips/boot/compressed/selfreloc.lds.S ---- linux-2.6.37.orig/arch/mips/boot/compressed/selfreloc.lds.S 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/boot/compressed/selfreloc.lds.S 2011-04-26 20:26:20.347764678 +0200 -@@ -0,0 +1,39 @@ -+/*- -+ * written 2010 by Thorsten Glaser based on -+ * arch/mips/kernel/vmlinux.lds and arch/mips/boot/compressed/ld.script -+ */ -+ -+#include -+#include -+#include -+ -+#undef mips -+#define mips mips -+OUTPUT_ARCH(mips) -+ENTRY(selfreloc_start) -+PHDRS { -+ text PT_LOAD FLAGS(7); /* RWX */ -+} -+SECTIONS -+{ -+ . = VMLINUX_LOAD_ADDRESS; -+ .text : { -+ *(.text) -+ *(.text.*) -+ *(.rodata) -+ *(.rodata.*) -+ *(.data) -+ *(.data.*) -+ *(.bss) -+ *(.bss.*) -+ } :text -+ /DISCARD/ : { -+ *(.MIPS.options) -+ *(.options) -+ *(.pdr) -+ *(.reginfo) -+ *(.comment) -+ *(.note) -+ *(.gnu.attributes) -+ } -+} -diff -Nur linux-2.6.37.orig/arch/mips/boot/compressed/selfreloc.S linux-2.6.37/arch/mips/boot/compressed/selfreloc.S ---- linux-2.6.37.orig/arch/mips/boot/compressed/selfreloc.S 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/boot/compressed/selfreloc.S 2011-04-26 20:26:20.197673829 +0200 -@@ -0,0 +1,54 @@ -+/*- -+ * written 2011 by Thorsten Glaser based on -+ * arch/mips/boot/compressed/head.S -+ */ -+ -+#include -+#include -+ -+ .set noreorder -+ .cprestore -+ -+ .text -+ LEAF(selfreloc_start) -+selfreloc_start: -+ /* Save boot rom start args */ -+ move s0, a0 -+ move s1, a1 -+ move s2, a2 -+ move s3, a3 -+ -+ /* Copy code to the correct place */ -+ PTR_LI a0, VMLINUZ_LOAD_ADDRESS -+ PTR_LA a1, imgbeg -+ PTR_LA a2, imgend -+1: lw t0, 0(a1) -+ sw t0, 0(a0) -+ add a1, 4 -+ add a0, 4 -+ blt a1, a2, 1b -+ nop -+ -+ /* Restore boot rom start args */ -+ move a0, s0 -+ move a1, s1 -+ move a2, s2 -+ move a3, s3 -+ -+ /* Jump to the code at its new location */ -+ PTR_LI k0, VMLINUZ_LOAD_ADDRESS -+ jr k0 -+ nop -+ -+ /* Just in case we come back… */ -+3: -+ b 3b -+ nop -+ END(selfreloc_start) -+ -+ .globl imgbeg -+ .p2align 2 -+imgbeg: .incbin "vmlinuz.bin" -+ .globl imgend -+ .p2align 2 -+imgend: -diff -Nur linux-2.6.37.orig/arch/mips/boot/compressed/uart-16550.c linux-2.6.37/arch/mips/boot/compressed/uart-16550.c ---- linux-2.6.37.orig/arch/mips/boot/compressed/uart-16550.c 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/mips/boot/compressed/uart-16550.c 2011-04-26 20:26:20.467673519 +0200 -@@ -18,6 +18,11 @@ - #define PORT(offset) (CKSEG1ADDR(AR7_REGS_UART0) + (4 * offset)) - #endif - -+#ifdef CONFIG_BCM47XX -+#define UART_BASE 0x18000300 -+#define PORT(offset) (CKSEG1ADDR(UART_BASE) + (offset)) -+#endif -+ - #ifndef PORT - #error please define the serial port address for your own machine - #endif -diff -Nur linux-2.6.37.orig/arch/mips/Kconfig linux-2.6.37/arch/mips/Kconfig ---- linux-2.6.37.orig/arch/mips/Kconfig 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/mips/Kconfig 2011-04-26 20:26:19.637668480 +0200 -@@ -84,6 +84,7 @@ - select GENERIC_GPIO - select SYS_HAS_EARLY_PRINTK - select CFE -+ select SYS_SUPPORTS_ZBOOT_UART16550 - help - Support for BCM47XX based boards - -diff -Nur linux-2.6.37.orig/arch/mips/Makefile linux-2.6.37/arch/mips/Makefile ---- linux-2.6.37.orig/arch/mips/Makefile 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/mips/Makefile 2011-04-26 20:26:19.647661042 +0200 -@@ -76,6 +76,7 @@ - all-$(CONFIG_BOOT_ELF32) := $(vmlinux-32) - all-$(CONFIG_BOOT_ELF64) := $(vmlinux-64) - all-$(CONFIG_SYS_SUPPORTS_ZBOOT)+= vmlinuz -+all-$(CONFIG_BCM47XX) += vmlinuz.elf - - # - # GCC uses -G 0 -mabicalls -fpic as default. We don't want PIC in the kernel -@@ -276,7 +277,7 @@ - $(Q)$(MAKE) $(build)=arch/mips/boot VMLINUX=$(vmlinux-32) arch/mips/boot/$@ - - # boot/compressed --vmlinuz vmlinuz.bin vmlinuz.ecoff vmlinuz.srec: $(vmlinux-32) FORCE -+vmlinuz vmlinuz.bin vmlinuz.ecoff vmlinuz.srec vmlinuz.elf: $(vmlinux-32) FORCE - $(Q)$(MAKE) $(build)=arch/mips/boot/compressed \ - VMLINUX_LOAD_ADDRESS=$(load-y) 32bit-bfd=$(32bit-bfd) $@ - -@@ -313,6 +314,7 @@ - echo ' vmlinuz.ecoff - ECOFF zboot image' - echo ' vmlinuz.bin - Raw binary zboot image' - echo ' vmlinuz.srec - SREC zboot image' -+ echo ' vmlinuz.elf - ELF self-relocating zboot image' - echo - echo ' These will be default as apropriate for a configured platform.' - endef -diff -Nur linux-2.6.37.orig/drivers/ssb/driver_mipscore.c linux-2.6.37/drivers/ssb/driver_mipscore.c ---- linux-2.6.37.orig/drivers/ssb/driver_mipscore.c 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/ssb/driver_mipscore.c 2011-04-26 20:26:20.597672444 +0200 -@@ -190,10 +190,11 @@ - { - struct ssb_bus *bus = mcore->dev->bus; - -+ printk("Check for vendor with value: %d", bus->chipco.dev->id.vendor); - mcore->flash_buswidth = 2; - if (bus->chipco.dev) { - mcore->flash_window = 0x1c000000; -- mcore->flash_window_size = 0x02000000; -+ mcore->flash_window_size = 0x00800000; - if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG) - & SSB_CHIPCO_CFG_DS16) == 0) - mcore->flash_buswidth = 1; -diff -Nur linux-2.6.37.orig/init/Kconfig linux-2.6.37/init/Kconfig ---- linux-2.6.37.orig/init/Kconfig 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/init/Kconfig 2011-04-26 20:26:20.727673059 +0200 -@@ -158,6 +158,7 @@ - config KERNEL_GZIP - bool "Gzip" - depends on HAVE_KERNEL_GZIP -+ select DECOMPRESS_GZIP - help - The old and tried gzip compression. It provides a good balance - between compression ratio and decompression speed. -@@ -165,6 +166,7 @@ - config KERNEL_BZIP2 - bool "Bzip2" - depends on HAVE_KERNEL_BZIP2 -+ select DECOMPRESS_BZIP2 - help - Its compression ratio and speed is intermediate. - Decompression speed is slowest among the three. The kernel -@@ -175,6 +177,7 @@ - config KERNEL_LZMA - bool "LZMA" - depends on HAVE_KERNEL_LZMA -+ select DECOMPRESS_LZMA - help - The most recent compression algorithm. - Its ratio is best, decompression speed is between the other -@@ -184,6 +187,7 @@ - config KERNEL_LZO - bool "LZO" - depends on HAVE_KERNEL_LZO -+ select DECOMPRESS_LZO - help - Its compression ratio is the poorest among the 4. The kernel - size is about 10% bigger than gzip; however its speed diff --git a/target/linux/patches/2.6.37/bsd-compatibility.patch b/target/linux/patches/2.6.37/bsd-compatibility.patch deleted file mode 100644 index 9e91a62de..000000000 --- a/target/linux/patches/2.6.37/bsd-compatibility.patch +++ /dev/null @@ -1,2512 +0,0 @@ -diff -Nur linux-2.6.36.orig/scripts/Makefile.lib linux-2.6.36/scripts/Makefile.lib ---- linux-2.6.36.orig/scripts/Makefile.lib 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/scripts/Makefile.lib 2010-11-28 18:34:22.000000000 +0100 -@@ -216,7 +216,12 @@ - size_append = printf $(shell \ - dec_size=0; \ - for F in $1; do \ -- fsize=$$(stat -c "%s" $$F); \ -+ if stat -qs .>/dev/null 2>&1; then \ -+ statcmd='stat -f %z'; \ -+ else \ -+ statcmd='stat -c %s'; \ -+ fi; \ -+ fsize=$$($$statcmd $$F); \ - dec_size=$$(expr $$dec_size + $$fsize); \ - done; \ - printf "%08x\n" $$dec_size | \ -diff -Nur linux-2.6.36.orig/scripts/mod/mk_elfconfig.c linux-2.6.36/scripts/mod/mk_elfconfig.c ---- linux-2.6.36.orig/scripts/mod/mk_elfconfig.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/scripts/mod/mk_elfconfig.c 2010-11-28 18:33:24.000000000 +0100 -@@ -1,7 +1,18 @@ - #include - #include - #include --#include -+ -+#define EI_NIDENT (16) -+#define ELFMAG "\177ELF" -+ -+#define SELFMAG 4 -+#define EI_CLASS 4 -+#define ELFCLASS32 1 /* 32-bit objects */ -+#define ELFCLASS64 2 /* 64-bit objects */ -+ -+#define EI_DATA 5 /* Data encoding byte index */ -+#define ELFDATA2LSB 1 /* 2's complement, little endian */ -+#define ELFDATA2MSB 2 /* 2's complement, big endian */ - - int - main(int argc, char **argv) -diff -Nur linux-2.6.36.orig/scripts/mod/modpost.h linux-2.6.36/scripts/mod/modpost.h ---- linux-2.6.36.orig/scripts/mod/modpost.h 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/scripts/mod/modpost.h 2010-11-28 18:33:24.000000000 +0100 -@@ -7,7 +7,2453 @@ - #include - #include - #include --#include -+ -+ -+/* This file defines standard ELF types, structures, and macros. -+ Copyright (C) 1995-1999,2000,2001,2002,2003 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#ifndef _ELF_H -+#define _ELF_H 1 -+ -+__BEGIN_DECLS -+ -+/* Standard ELF types. */ -+ -+#include -+ -+/* Type for a 16-bit quantity. */ -+typedef uint16_t Elf32_Half; -+typedef uint16_t Elf64_Half; -+ -+/* Types for signed and unsigned 32-bit quantities. */ -+typedef uint32_t Elf32_Word; -+typedef int32_t Elf32_Sword; -+typedef uint32_t Elf64_Word; -+typedef int32_t Elf64_Sword; -+ -+/* Types for signed and unsigned 64-bit quantities. */ -+typedef uint64_t Elf32_Xword; -+typedef int64_t Elf32_Sxword; -+typedef uint64_t Elf64_Xword; -+typedef int64_t Elf64_Sxword; -+ -+/* Type of addresses. */ -+typedef uint32_t Elf32_Addr; -+typedef uint64_t Elf64_Addr; -+ -+/* Type of file offsets. */ -+typedef uint32_t Elf32_Off; -+typedef uint64_t Elf64_Off; -+ -+/* Type for section indices, which are 16-bit quantities. */ -+typedef uint16_t Elf32_Section; -+typedef uint16_t Elf64_Section; -+ -+/* Type for version symbol information. */ -+typedef Elf32_Half Elf32_Versym; -+typedef Elf64_Half Elf64_Versym; -+ -+ -+/* The ELF file header. This appears at the start of every ELF file. */ -+ -+#define EI_NIDENT (16) -+ -+typedef struct -+{ -+ unsigned char e_ident[EI_NIDENT]; /* Magic number and other info */ -+ Elf32_Half e_type; /* Object file type */ -+ Elf32_Half e_machine; /* Architecture */ -+ Elf32_Word e_version; /* Object file version */ -+ Elf32_Addr e_entry; /* Entry point virtual address */ -+ Elf32_Off e_phoff; /* Program header table file offset */ -+ Elf32_Off e_shoff; /* Section header table file offset */ -+ Elf32_Word e_flags; /* Processor-specific flags */ -+ Elf32_Half e_ehsize; /* ELF header size in bytes */ -+ Elf32_Half e_phentsize; /* Program header table entry size */ -+ Elf32_Half e_phnum; /* Program header table entry count */ -+ Elf32_Half e_shentsize; /* Section header table entry size */ -+ Elf32_Half e_shnum; /* Section header table entry count */ -+ Elf32_Half e_shstrndx; /* Section header string table index */ -+} Elf32_Ehdr; -+ -+typedef struct -+{ -+ unsigned char e_ident[EI_NIDENT]; /* Magic number and other info */ -+ Elf64_Half e_type; /* Object file type */ -+ Elf64_Half e_machine; /* Architecture */ -+ Elf64_Word e_version; /* Object file version */ -+ Elf64_Addr e_entry; /* Entry point virtual address */ -+ Elf64_Off e_phoff; /* Program header table file offset */ -+ Elf64_Off e_shoff; /* Section header table file offset */ -+ Elf64_Word e_flags; /* Processor-specific flags */ -+ Elf64_Half e_ehsize; /* ELF header size in bytes */ -+ Elf64_Half e_phentsize; /* Program header table entry size */ -+ Elf64_Half e_phnum; /* Program header table entry count */ -+ Elf64_Half e_shentsize; /* Section header table entry size */ -+ Elf64_Half e_shnum; /* Section header table entry count */ -+ Elf64_Half e_shstrndx; /* Section header string table index */ -+} Elf64_Ehdr; -+ -+/* Fields in the e_ident array. The EI_* macros are indices into the -+ array. The macros under each EI_* macro are the values the byte -+ may have. */ -+ -+#define EI_MAG0 0 /* File identification byte 0 index */ -+#define ELFMAG0 0x7f /* Magic number byte 0 */ -+ -+#define EI_MAG1 1 /* File identification byte 1 index */ -+#define ELFMAG1 'E' /* Magic number byte 1 */ -+ -+#define EI_MAG2 2 /* File identification byte 2 index */ -+#define ELFMAG2 'L' /* Magic number byte 2 */ -+ -+#define EI_MAG3 3 /* File identification byte 3 index */ -+#define ELFMAG3 'F' /* Magic number byte 3 */ -+ -+/* Conglomeration of the identification bytes, for easy testing as a word. */ -+#define ELFMAG "\177ELF" -+#define SELFMAG 4 -+ -+#define EI_CLASS 4 /* File class byte index */ -+#define ELFCLASSNONE 0 /* Invalid class */ -+#define ELFCLASS32 1 /* 32-bit objects */ -+#define ELFCLASS64 2 /* 64-bit objects */ -+#define ELFCLASSNUM 3 -+ -+#define EI_DATA 5 /* Data encoding byte index */ -+#define ELFDATANONE 0 /* Invalid data encoding */ -+#define ELFDATA2LSB 1 /* 2's complement, little endian */ -+#define ELFDATA2MSB 2 /* 2's complement, big endian */ -+#define ELFDATANUM 3 -+ -+#define EI_VERSION 6 /* File version byte index */ -+ /* Value must be EV_CURRENT */ -+ -+#define EI_OSABI 7 /* OS ABI identification */ -+#define ELFOSABI_NONE 0 /* UNIX System V ABI */ -+#define ELFOSABI_SYSV 0 /* Alias. */ -+#define ELFOSABI_HPUX 1 /* HP-UX */ -+#define ELFOSABI_NETBSD 2 /* NetBSD. */ -+#define ELFOSABI_LINUX 3 /* Linux. */ -+#define ELFOSABI_SOLARIS 6 /* Sun Solaris. */ -+#define ELFOSABI_AIX 7 /* IBM AIX. */ -+#define ELFOSABI_IRIX 8 /* SGI Irix. */ -+#define ELFOSABI_FREEBSD 9 /* FreeBSD. */ -+#define ELFOSABI_TRU64 10 /* Compaq TRU64 UNIX. */ -+#define ELFOSABI_MODESTO 11 /* Novell Modesto. */ -+#define ELFOSABI_OPENBSD 12 /* OpenBSD. */ -+#define ELFOSABI_ARM 97 /* ARM */ -+#define ELFOSABI_STANDALONE 255 /* Standalone (embedded) application */ -+ -+#define EI_ABIVERSION 8 /* ABI version */ -+ -+#define EI_PAD 9 /* Byte index of padding bytes */ -+ -+/* Legal values for e_type (object file type). */ -+ -+#define ET_NONE 0 /* No file type */ -+#define ET_REL 1 /* Relocatable file */ -+#define ET_EXEC 2 /* Executable file */ -+#define ET_DYN 3 /* Shared object file */ -+#define ET_CORE 4 /* Core file */ -+#define ET_NUM 5 /* Number of defined types */ -+#define ET_LOOS 0xfe00 /* OS-specific range start */ -+#define ET_HIOS 0xfeff /* OS-specific range end */ -+#define ET_LOPROC 0xff00 /* Processor-specific range start */ -+#define ET_HIPROC 0xffff /* Processor-specific range end */ -+ -+/* Legal values for e_machine (architecture). */ -+ -+#define EM_NONE 0 /* No machine */ -+#define EM_M32 1 /* AT&T WE 32100 */ -+#define EM_SPARC 2 /* SUN SPARC */ -+#define EM_386 3 /* Intel 80386 */ -+#define EM_68K 4 /* Motorola m68k family */ -+#define EM_88K 5 /* Motorola m88k family */ -+#define EM_860 7 /* Intel 80860 */ -+#define EM_MIPS 8 /* MIPS R3000 big-endian */ -+#define EM_S370 9 /* IBM System/370 */ -+#define EM_MIPS_RS3_LE 10 /* MIPS R3000 little-endian */ -+ -+#define EM_PARISC 15 /* HPPA */ -+#define EM_VPP500 17 /* Fujitsu VPP500 */ -+#define EM_SPARC32PLUS 18 /* Sun's "v8plus" */ -+#define EM_960 19 /* Intel 80960 */ -+#define EM_PPC 20 /* PowerPC */ -+#define EM_PPC64 21 /* PowerPC 64-bit */ -+#define EM_S390 22 /* IBM S390 */ -+ -+#define EM_V800 36 /* NEC V800 series */ -+#define EM_FR20 37 /* Fujitsu FR20 */ -+#define EM_RH32 38 /* TRW RH-32 */ -+#define EM_RCE 39 /* Motorola RCE */ -+#define EM_ARM 40 /* ARM */ -+#define EM_FAKE_ALPHA 41 /* Digital Alpha */ -+#define EM_SH 42 /* Hitachi SH */ -+#define EM_SPARCV9 43 /* SPARC v9 64-bit */ -+#define EM_TRICORE 44 /* Siemens Tricore */ -+#define EM_ARC 45 /* Argonaut RISC Core */ -+#define EM_H8_300 46 /* Hitachi H8/300 */ -+#define EM_H8_300H 47 /* Hitachi H8/300H */ -+#define EM_H8S 48 /* Hitachi H8S */ -+#define EM_H8_500 49 /* Hitachi H8/500 */ -+#define EM_IA_64 50 /* Intel Merced */ -+#define EM_MIPS_X 51 /* Stanford MIPS-X */ -+#define EM_COLDFIRE 52 /* Motorola Coldfire */ -+#define EM_68HC12 53 /* Motorola M68HC12 */ -+#define EM_MMA 54 /* Fujitsu MMA Multimedia Accelerator*/ -+#define EM_PCP 55 /* Siemens PCP */ -+#define EM_NCPU 56 /* Sony nCPU embeeded RISC */ -+#define EM_NDR1 57 /* Denso NDR1 microprocessor */ -+#define EM_STARCORE 58 /* Motorola Start*Core processor */ -+#define EM_ME16 59 /* Toyota ME16 processor */ -+#define EM_ST100 60 /* STMicroelectronic ST100 processor */ -+#define EM_TINYJ 61 /* Advanced Logic Corp. Tinyj emb.fam*/ -+#define EM_X86_64 62 /* AMD x86-64 architecture */ -+#define EM_PDSP 63 /* Sony DSP Processor */ -+ -+#define EM_FX66 66 /* Siemens FX66 microcontroller */ -+#define EM_ST9PLUS 67 /* STMicroelectronics ST9+ 8/16 mc */ -+#define EM_ST7 68 /* STmicroelectronics ST7 8 bit mc */ -+#define EM_68HC16 69 /* Motorola MC68HC16 microcontroller */ -+#define EM_68HC11 70 /* Motorola MC68HC11 microcontroller */ -+#define EM_68HC08 71 /* Motorola MC68HC08 microcontroller */ -+#define EM_68HC05 72 /* Motorola MC68HC05 microcontroller */ -+#define EM_SVX 73 /* Silicon Graphics SVx */ -+#define EM_ST19 74 /* STMicroelectronics ST19 8 bit mc */ -+#define EM_VAX 75 /* Digital VAX */ -+#define EM_CRIS 76 /* Axis Communications 32-bit embedded processor */ -+#define EM_JAVELIN 77 /* Infineon Technologies 32-bit embedded processor */ -+#define EM_FIREPATH 78 /* Element 14 64-bit DSP Processor */ -+#define EM_ZSP 79 /* LSI Logic 16-bit DSP Processor */ -+#define EM_MMIX 80 /* Donald Knuth's educational 64-bit processor */ -+#define EM_HUANY 81 /* Harvard University machine-independent object files */ -+#define EM_PRISM 82 /* SiTera Prism */ -+#define EM_AVR 83 /* Atmel AVR 8-bit microcontroller */ -+#define EM_FR30 84 /* Fujitsu FR30 */ -+#define EM_D10V 85 /* Mitsubishi D10V */ -+#define EM_D30V 86 /* Mitsubishi D30V */ -+#define EM_V850 87 /* NEC v850 */ -+#define EM_M32R 88 /* Mitsubishi M32R */ -+#define EM_MN10300 89 /* Matsushita MN10300 */ -+#define EM_MN10200 90 /* Matsushita MN10200 */ -+#define EM_PJ 91 /* picoJava */ -+#define EM_OPENRISC 92 /* OpenRISC 32-bit embedded processor */ -+#define EM_ARC_A5 93 /* ARC Cores Tangent-A5 */ -+#define EM_XTENSA 94 /* Tensilica Xtensa Architecture */ -+#define EM_NUM 95 -+ -+/* If it is necessary to assign new unofficial EM_* values, please -+ pick large random numbers (0x8523, 0xa7f2, etc.) to minimize the -+ chances of collision with official or non-GNU unofficial values. */ -+ -+#define EM_ALPHA 0x9026 -+ -+/* Legal values for e_version (version). */ -+ -+#define EV_NONE 0 /* Invalid ELF version */ -+#define EV_CURRENT 1 /* Current version */ -+#define EV_NUM 2 -+ -+/* Section header. */ -+ -+typedef struct -+{ -+ Elf32_Word sh_name; /* Section name (string tbl index) */ -+ Elf32_Word sh_type; /* Section type */ -+ Elf32_Word sh_flags; /* Section flags */ -+ Elf32_Addr sh_addr; /* Section virtual addr at execution */ -+ Elf32_Off sh_offset; /* Section file offset */ -+ Elf32_Word sh_size; /* Section size in bytes */ -+ Elf32_Word sh_link; /* Link to another section */ -+ Elf32_Word sh_info; /* Additional section information */ -+ Elf32_Word sh_addralign; /* Section alignment */ -+ Elf32_Word sh_entsize; /* Entry size if section holds table */ -+} Elf32_Shdr; -+ -+typedef struct -+{ -+ Elf64_Word sh_name; /* Section name (string tbl index) */ -+ Elf64_Word sh_type; /* Section type */ -+ Elf64_Xword sh_flags; /* Section flags */ -+ Elf64_Addr sh_addr; /* Section virtual addr at execution */ -+ Elf64_Off sh_offset; /* Section file offset */ -+ Elf64_Xword sh_size; /* Section size in bytes */ -+ Elf64_Word sh_link; /* Link to another section */ -+ Elf64_Word sh_info; /* Additional section information */ -+ Elf64_Xword sh_addralign; /* Section alignment */ -+ Elf64_Xword sh_entsize; /* Entry size if section holds table */ -+} Elf64_Shdr; -+ -+/* Special section indices. */ -+ -+#define SHN_UNDEF 0 /* Undefined section */ -+#define SHN_LORESERVE 0xff00 /* Start of reserved indices */ -+#define SHN_LOPROC 0xff00 /* Start of processor-specific */ -+#define SHN_HIPROC 0xff1f /* End of processor-specific */ -+#define SHN_LOOS 0xff20 /* Start of OS-specific */ -+#define SHN_HIOS 0xff3f /* End of OS-specific */ -+#define SHN_ABS 0xfff1 /* Associated symbol is absolute */ -+#define SHN_COMMON 0xfff2 /* Associated symbol is common */ -+#define SHN_XINDEX 0xffff /* Index is in extra table. */ -+#define SHN_HIRESERVE 0xffff /* End of reserved indices */ -+ -+/* Legal values for sh_type (section type). */ -+ -+#define SHT_NULL 0 /* Section header table entry unused */ -+#define SHT_PROGBITS 1 /* Program data */ -+#define SHT_SYMTAB 2 /* Symbol table */ -+#define SHT_STRTAB 3 /* String table */ -+#define SHT_RELA 4 /* Relocation entries with addends */ -+#define SHT_HASH 5 /* Symbol hash table */ -+#define SHT_DYNAMIC 6 /* Dynamic linking information */ -+#define SHT_NOTE 7 /* Notes */ -+#define SHT_NOBITS 8 /* Program space with no data (bss) */ -+#define SHT_REL 9 /* Relocation entries, no addends */ -+#define SHT_SHLIB 10 /* Reserved */ -+#define SHT_DYNSYM 11 /* Dynamic linker symbol table */ -+#define SHT_INIT_ARRAY 14 /* Array of constructors */ -+#define SHT_FINI_ARRAY 15 /* Array of destructors */ -+#define SHT_PREINIT_ARRAY 16 /* Array of pre-constructors */ -+#define SHT_GROUP 17 /* Section group */ -+#define SHT_SYMTAB_SHNDX 18 /* Extended section indeces */ -+#define SHT_NUM 19 /* Number of defined types. */ -+#define SHT_LOOS 0x60000000 /* Start OS-specific */ -+#define SHT_GNU_LIBLIST 0x6ffffff7 /* Prelink library list */ -+#define SHT_CHECKSUM 0x6ffffff8 /* Checksum for DSO content. */ -+#define SHT_LOSUNW 0x6ffffffa /* Sun-specific low bound. */ -+#define SHT_SUNW_move 0x6ffffffa -+#define SHT_SUNW_COMDAT 0x6ffffffb -+#define SHT_SUNW_syminfo 0x6ffffffc -+#define SHT_GNU_verdef 0x6ffffffd /* Version definition section. */ -+#define SHT_GNU_verneed 0x6ffffffe /* Version needs section. */ -+#define SHT_GNU_versym 0x6fffffff /* Version symbol table. */ -+#define SHT_HISUNW 0x6fffffff /* Sun-specific high bound. */ -+#define SHT_HIOS 0x6fffffff /* End OS-specific type */ -+#define SHT_LOPROC 0x70000000 /* Start of processor-specific */ -+#define SHT_HIPROC 0x7fffffff /* End of processor-specific */ -+#define SHT_LOUSER 0x80000000 /* Start of application-specific */ -+#define SHT_HIUSER 0x8fffffff /* End of application-specific */ -+ -+/* Legal values for sh_flags (section flags). */ -+ -+#define SHF_WRITE (1 << 0) /* Writable */ -+#define SHF_ALLOC (1 << 1) /* Occupies memory during execution */ -+#define SHF_EXECINSTR (1 << 2) /* Executable */ -+#define SHF_MERGE (1 << 4) /* Might be merged */ -+#define SHF_STRINGS (1 << 5) /* Contains nul-terminated strings */ -+#define SHF_INFO_LINK (1 << 6) /* `sh_info' contains SHT index */ -+#define SHF_LINK_ORDER (1 << 7) /* Preserve order after combining */ -+#define SHF_OS_NONCONFORMING (1 << 8) /* Non-standard OS specific handling -+ required */ -+#define SHF_GROUP (1 << 9) /* Section is member of a group. */ -+#define SHF_TLS (1 << 10) /* Section hold thread-local data. */ -+#define SHF_MASKOS 0x0ff00000 /* OS-specific. */ -+#define SHF_MASKPROC 0xf0000000 /* Processor-specific */ -+ -+/* Section group handling. */ -+#define GRP_COMDAT 0x1 /* Mark group as COMDAT. */ -+ -+/* Symbol table entry. */ -+ -+typedef struct -+{ -+ Elf32_Word st_name; /* Symbol name (string tbl index) */ -+ Elf32_Addr st_value; /* Symbol value */ -+ Elf32_Word st_size; /* Symbol size */ -+ unsigned char st_info; /* Symbol type and binding */ -+ unsigned char st_other; /* Symbol visibility */ -+ Elf32_Section st_shndx; /* Section index */ -+} Elf32_Sym; -+ -+typedef struct -+{ -+ Elf64_Word st_name; /* Symbol name (string tbl index) */ -+ unsigned char st_info; /* Symbol type and binding */ -+ unsigned char st_other; /* Symbol visibility */ -+ Elf64_Section st_shndx; /* Section index */ -+ Elf64_Addr st_value; /* Symbol value */ -+ Elf64_Xword st_size; /* Symbol size */ -+} Elf64_Sym; -+ -+/* The syminfo section if available contains additional information about -+ every dynamic symbol. */ -+ -+typedef struct -+{ -+ Elf32_Half si_boundto; /* Direct bindings, symbol bound to */ -+ Elf32_Half si_flags; /* Per symbol flags */ -+} Elf32_Syminfo; -+ -+typedef struct -+{ -+ Elf64_Half si_boundto; /* Direct bindings, symbol bound to */ -+ Elf64_Half si_flags; /* Per symbol flags */ -+} Elf64_Syminfo; -+ -+/* Possible values for si_boundto. */ -+#define SYMINFO_BT_SELF 0xffff /* Symbol bound to self */ -+#define SYMINFO_BT_PARENT 0xfffe /* Symbol bound to parent */ -+#define SYMINFO_BT_LOWRESERVE 0xff00 /* Beginning of reserved entries */ -+ -+/* Possible bitmasks for si_flags. */ -+#define SYMINFO_FLG_DIRECT 0x0001 /* Direct bound symbol */ -+#define SYMINFO_FLG_PASSTHRU 0x0002 /* Pass-thru symbol for translator */ -+#define SYMINFO_FLG_COPY 0x0004 /* Symbol is a copy-reloc */ -+#define SYMINFO_FLG_LAZYLOAD 0x0008 /* Symbol bound to object to be lazy -+ loaded */ -+/* Syminfo version values. */ -+#define SYMINFO_NONE 0 -+#define SYMINFO_CURRENT 1 -+#define SYMINFO_NUM 2 -+ -+ -+/* How to extract and insert information held in the st_info field. */ -+ -+#define ELF32_ST_BIND(val) (((unsigned char) (val)) >> 4) -+#define ELF32_ST_TYPE(val) ((val) & 0xf) -+#define ELF32_ST_INFO(bind, type) (((bind) << 4) + ((type) & 0xf)) -+ -+/* Both Elf32_Sym and Elf64_Sym use the same one-byte st_info field. */ -+#define ELF64_ST_BIND(val) ELF32_ST_BIND (val) -+#define ELF64_ST_TYPE(val) ELF32_ST_TYPE (val) -+#define ELF64_ST_INFO(bind, type) ELF32_ST_INFO ((bind), (type)) -+ -+/* Legal values for ST_BIND subfield of st_info (symbol binding). */ -+ -+#define STB_LOCAL 0 /* Local symbol */ -+#define STB_GLOBAL 1 /* Global symbol */ -+#define STB_WEAK 2 /* Weak symbol */ -+#define STB_NUM 3 /* Number of defined types. */ -+#define STB_LOOS 10 /* Start of OS-specific */ -+#define STB_HIOS 12 /* End of OS-specific */ -+#define STB_LOPROC 13 /* Start of processor-specific */ -+#define STB_HIPROC 15 /* End of processor-specific */ -+ -+/* Legal values for ST_TYPE subfield of st_info (symbol type). */ -+ -+#define STT_NOTYPE 0 /* Symbol type is unspecified */ -+#define STT_OBJECT 1 /* Symbol is a data object */ -+#define STT_FUNC 2 /* Symbol is a code object */ -+#define STT_SECTION 3 /* Symbol associated with a section */ -+#define STT_FILE 4 /* Symbol's name is file name */ -+#define STT_COMMON 5 /* Symbol is a common data object */ -+#define STT_TLS 6 /* Symbol is thread-local data object*/ -+#define STT_NUM 7 /* Number of defined types. */ -+#define STT_LOOS 10 /* Start of OS-specific */ -+#define STT_HIOS 12 /* End of OS-specific */ -+#define STT_LOPROC 13 /* Start of processor-specific */ -+#define STT_HIPROC 15 /* End of processor-specific */ -+ -+ -+/* Symbol table indices are found in the hash buckets and chain table -+ of a symbol hash table section. This special index value indicates -+ the end of a chain, meaning no further symbols are found in that bucket. */ -+ -+#define STN_UNDEF 0 /* End of a chain. */ -+ -+ -+/* How to extract and insert information held in the st_other field. */ -+ -+#define ELF32_ST_VISIBILITY(o) ((o) & 0x03) -+ -+/* For ELF64 the definitions are the same. */ -+#define ELF64_ST_VISIBILITY(o) ELF32_ST_VISIBILITY (o) -+ -+/* Symbol visibility specification encoded in the st_other field. */ -+#define STV_DEFAULT 0 /* Default symbol visibility rules */ -+#define STV_INTERNAL 1 /* Processor specific hidden class */ -+#define STV_HIDDEN 2 /* Sym unavailable in other modules */ -+#define STV_PROTECTED 3 /* Not preemptible, not exported */ -+ -+ -+/* Relocation table entry without addend (in section of type SHT_REL). */ -+ -+typedef struct -+{ -+ Elf32_Addr r_offset; /* Address */ -+ Elf32_Word r_info; /* Relocation type and symbol index */ -+} Elf32_Rel; -+ -+/* I have seen two different definitions of the Elf64_Rel and -+ Elf64_Rela structures, so we'll leave them out until Novell (or -+ whoever) gets their act together. */ -+/* The following, at least, is used on Sparc v9, MIPS, and Alpha. */ -+ -+typedef struct -+{ -+ Elf64_Addr r_offset; /* Address */ -+ Elf64_Xword r_info; /* Relocation type and symbol index */ -+} Elf64_Rel; -+ -+/* Relocation table entry with addend (in section of type SHT_RELA). */ -+ -+typedef struct -+{ -+ Elf32_Addr r_offset; /* Address */ -+ Elf32_Word r_info; /* Relocation type and symbol index */ -+ Elf32_Sword r_addend; /* Addend */ -+} Elf32_Rela; -+ -+typedef struct -+{ -+ Elf64_Addr r_offset; /* Address */ -+ Elf64_Xword r_info; /* Relocation type and symbol index */ -+ Elf64_Sxword r_addend; /* Addend */ -+} Elf64_Rela; -+ -+/* How to extract and insert information held in the r_info field. */ -+ -+#define ELF32_R_SYM(val) ((val) >> 8) -+#define ELF32_R_TYPE(val) ((val) & 0xff) -+#define ELF32_R_INFO(sym, type) (((sym) << 8) + ((type) & 0xff)) -+ -+#define ELF64_R_SYM(i) ((i) >> 32) -+#define ELF64_R_TYPE(i) ((i) & 0xffffffff) -+#define ELF64_R_INFO(sym,type) ((((Elf64_Xword) (sym)) << 32) + (type)) -+ -+/* Program segment header. */ -+ -+typedef struct -+{ -+ Elf32_Word p_type; /* Segment type */ -+ Elf32_Off p_offset; /* Segment file offset */ -+ Elf32_Addr p_vaddr; /* Segment virtual address */ -+ Elf32_Addr p_paddr; /* Segment physical address */ -+ Elf32_Word p_filesz; /* Segment size in file */ -+ Elf32_Word p_memsz; /* Segment size in memory */ -+ Elf32_Word p_flags; /* Segment flags */ -+ Elf32_Word p_align; /* Segment alignment */ -+} Elf32_Phdr; -+ -+typedef struct -+{ -+ Elf64_Word p_type; /* Segment type */ -+ Elf64_Word p_flags; /* Segment flags */ -+ Elf64_Off p_offset; /* Segment file offset */ -+ Elf64_Addr p_vaddr; /* Segment virtual address */ -+ Elf64_Addr p_paddr; /* Segment physical address */ -+ Elf64_Xword p_filesz; /* Segment size in file */ -+ Elf64_Xword p_memsz; /* Segment size in memory */ -+ Elf64_Xword p_align; /* Segment alignment */ -+} Elf64_Phdr; -+ -+/* Legal values for p_type (segment type). */ -+ -+#define PT_NULL 0 /* Program header table entry unused */ -+#define PT_LOAD 1 /* Loadable program segment */ -+#define PT_DYNAMIC 2 /* Dynamic linking information */ -+#define PT_INTERP 3 /* Program interpreter */ -+#define PT_NOTE 4 /* Auxiliary information */ -+#define PT_SHLIB 5 /* Reserved */ -+#define PT_PHDR 6 /* Entry for header table itself */ -+#define PT_TLS 7 /* Thread-local storage segment */ -+#define PT_NUM 8 /* Number of defined types */ -+#define PT_LOOS 0x60000000 /* Start of OS-specific */ -+#define PT_GNU_EH_FRAME 0x6474e550 /* GCC .eh_frame_hdr segment */ -+#define PT_GNU_STACK 0x6474e551 /* Indicates stack executability */ -+#define PT_LOSUNW 0x6ffffffa -+#define PT_SUNWBSS 0x6ffffffa /* Sun Specific segment */ -+#define PT_SUNWSTACK 0x6ffffffb /* Stack segment */ -+#define PT_HISUNW 0x6fffffff -+#define PT_HIOS 0x6fffffff /* End of OS-specific */ -+#define PT_LOPROC 0x70000000 /* Start of processor-specific */ -+#define PT_HIPROC 0x7fffffff /* End of processor-specific */ -+ -+/* Legal values for p_flags (segment flags). */ -+ -+#define PF_X (1 << 0) /* Segment is executable */ -+#define PF_W (1 << 1) /* Segment is writable */ -+#define PF_R (1 << 2) /* Segment is readable */ -+#define PF_MASKOS 0x0ff00000 /* OS-specific */ -+#define PF_MASKPROC 0xf0000000 /* Processor-specific */ -+ -+/* Legal values for note segment descriptor types for core files. */ -+ -+#define NT_PRSTATUS 1 /* Contains copy of prstatus struct */ -+#define NT_FPREGSET 2 /* Contains copy of fpregset struct */ -+#define NT_PRPSINFO 3 /* Contains copy of prpsinfo struct */ -+#define NT_PRXREG 4 /* Contains copy of prxregset struct */ -+#define NT_TASKSTRUCT 4 /* Contains copy of task structure */ -+#define NT_PLATFORM 5 /* String from sysinfo(SI_PLATFORM) */ -+#define NT_AUXV 6 /* Contains copy of auxv array */ -+#define NT_GWINDOWS 7 /* Contains copy of gwindows struct */ -+#define NT_ASRS 8 /* Contains copy of asrset struct */ -+#define NT_PSTATUS 10 /* Contains copy of pstatus struct */ -+#define NT_PSINFO 13 /* Contains copy of psinfo struct */ -+#define NT_PRCRED 14 /* Contains copy of prcred struct */ -+#define NT_UTSNAME 15 /* Contains copy of utsname struct */ -+#define NT_LWPSTATUS 16 /* Contains copy of lwpstatus struct */ -+#define NT_LWPSINFO 17 /* Contains copy of lwpinfo struct */ -+#define NT_PRFPXREG 20 /* Contains copy of fprxregset struct*/ -+ -+/* Legal values for the note segment descriptor types for object files. */ -+ -+#define NT_VERSION 1 /* Contains a version string. */ -+ -+ -+/* Dynamic section entry. */ -+ -+typedef struct -+{ -+ Elf32_Sword d_tag; /* Dynamic entry type */ -+ union -+ { -+ Elf32_Word d_val; /* Integer value */ -+ Elf32_Addr d_ptr; /* Address value */ -+ } d_un; -+} Elf32_Dyn; -+ -+typedef struct -+{ -+ Elf64_Sxword d_tag; /* Dynamic entry type */ -+ union -+ { -+ Elf64_Xword d_val; /* Integer value */ -+ Elf64_Addr d_ptr; /* Address value */ -+ } d_un; -+} Elf64_Dyn; -+ -+/* Legal values for d_tag (dynamic entry type). */ -+ -+#define DT_NULL 0 /* Marks end of dynamic section */ -+#define DT_NEEDED 1 /* Name of needed library */ -+#define DT_PLTRELSZ 2 /* Size in bytes of PLT relocs */ -+#define DT_PLTGOT 3 /* Processor defined value */ -+#define DT_HASH 4 /* Address of symbol hash table */ -+#define DT_STRTAB 5 /* Address of string table */ -+#define DT_SYMTAB 6 /* Address of symbol table */ -+#define DT_RELA 7 /* Address of Rela relocs */ -+#define DT_RELASZ 8 /* Total size of Rela relocs */ -+#define DT_RELAENT 9 /* Size of one Rela reloc */ -+#define DT_STRSZ 10 /* Size of string table */ -+#define DT_SYMENT 11 /* Size of one symbol table entry */ -+#define DT_INIT 12 /* Address of init function */ -+#define DT_FINI 13 /* Address of termination function */ -+#define DT_SONAME 14 /* Name of shared object */ -+#define DT_RPATH 15 /* Library search path (deprecated) */ -+#define DT_SYMBOLIC 16 /* Start symbol search here */ -+#define DT_REL 17 /* Address of Rel relocs */ -+#define DT_RELSZ 18 /* Total size of Rel relocs */ -+#define DT_RELENT 19 /* Size of one Rel reloc */ -+#define DT_PLTREL 20 /* Type of reloc in PLT */ -+#define DT_DEBUG 21 /* For debugging; unspecified */ -+#define DT_TEXTREL 22 /* Reloc might modify .text */ -+#define DT_JMPREL 23 /* Address of PLT relocs */ -+#define DT_BIND_NOW 24 /* Process relocations of object */ -+#define DT_INIT_ARRAY 25 /* Array with addresses of init fct */ -+#define DT_FINI_ARRAY 26 /* Array with addresses of fini fct */ -+#define DT_INIT_ARRAYSZ 27 /* Size in bytes of DT_INIT_ARRAY */ -+#define DT_FINI_ARRAYSZ 28 /* Size in bytes of DT_FINI_ARRAY */ -+#define DT_RUNPATH 29 /* Library search path */ -+#define DT_FLAGS 30 /* Flags for the object being loaded */ -+#define DT_ENCODING 32 /* Start of encoded range */ -+#define DT_PREINIT_ARRAY 32 /* Array with addresses of preinit fct*/ -+#define DT_PREINIT_ARRAYSZ 33 /* size in bytes of DT_PREINIT_ARRAY */ -+#define DT_NUM 34 /* Number used */ -+#define DT_LOOS 0x6000000d /* Start of OS-specific */ -+#define DT_HIOS 0x6ffff000 /* End of OS-specific */ -+#define DT_LOPROC 0x70000000 /* Start of processor-specific */ -+#define DT_HIPROC 0x7fffffff /* End of processor-specific */ -+#define DT_PROCNUM DT_MIPS_NUM /* Most used by any processor */ -+ -+/* DT_* entries which fall between DT_VALRNGHI & DT_VALRNGLO use the -+ Dyn.d_un.d_val field of the Elf*_Dyn structure. This follows Sun's -+ approach. */ -+#define DT_VALRNGLO 0x6ffffd00 -+#define DT_GNU_PRELINKED 0x6ffffdf5 /* Prelinking timestamp */ -+#define DT_GNU_CONFLICTSZ 0x6ffffdf6 /* Size of conflict section */ -+#define DT_GNU_LIBLISTSZ 0x6ffffdf7 /* Size of library list */ -+#define DT_CHECKSUM 0x6ffffdf8 -+#define DT_PLTPADSZ 0x6ffffdf9 -+#define DT_MOVEENT 0x6ffffdfa -+#define DT_MOVESZ 0x6ffffdfb -+#define DT_FEATURE_1 0x6ffffdfc /* Feature selection (DTF_*). */ -+#define DT_POSFLAG_1 0x6ffffdfd /* Flags for DT_* entries, effecting -+ the following DT_* entry. */ -+#define DT_SYMINSZ 0x6ffffdfe /* Size of syminfo table (in bytes) */ -+#define DT_SYMINENT 0x6ffffdff /* Entry size of syminfo */ -+#define DT_VALRNGHI 0x6ffffdff -+#define DT_VALTAGIDX(tag) (DT_VALRNGHI - (tag)) /* Reverse order! */ -+#define DT_VALNUM 12 -+ -+/* DT_* entries which fall between DT_ADDRRNGHI & DT_ADDRRNGLO use the -+ Dyn.d_un.d_ptr field of the Elf*_Dyn structure. -+ -+ If any adjustment is made to the ELF object after it has been -+ built these entries will need to be adjusted. */ -+#define DT_ADDRRNGLO 0x6ffffe00 -+#define DT_GNU_CONFLICT 0x6ffffef8 /* Start of conflict section */ -+#define DT_GNU_LIBLIST 0x6ffffef9 /* Library list */ -+#define DT_CONFIG 0x6ffffefa /* Configuration information. */ -+#define DT_DEPAUDIT 0x6ffffefb /* Dependency auditing. */ -+#define DT_AUDIT 0x6ffffefc /* Object auditing. */ -+#define DT_PLTPAD 0x6ffffefd /* PLT padding. */ -+#define DT_MOVETAB 0x6ffffefe /* Move table. */ -+#define DT_SYMINFO 0x6ffffeff /* Syminfo table. */ -+#define DT_ADDRRNGHI 0x6ffffeff -+#define DT_ADDRTAGIDX(tag) (DT_ADDRRNGHI - (tag)) /* Reverse order! */ -+#define DT_ADDRNUM 10 -+ -+/* The versioning entry types. The next are defined as part of the -+ GNU extension. */ -+#define DT_VERSYM 0x6ffffff0 -+ -+#define DT_RELACOUNT 0x6ffffff9 -+#define DT_RELCOUNT 0x6ffffffa -+ -+/* These were chosen by Sun. */ -+#define DT_FLAGS_1 0x6ffffffb /* State flags, see DF_1_* below. */ -+#define DT_VERDEF 0x6ffffffc /* Address of version definition -+ table */ -+#define DT_VERDEFNUM 0x6ffffffd /* Number of version definitions */ -+#define DT_VERNEED 0x6ffffffe /* Address of table with needed -+ versions */ -+#define DT_VERNEEDNUM 0x6fffffff /* Number of needed versions */ -+#define DT_VERSIONTAGIDX(tag) (DT_VERNEEDNUM - (tag)) /* Reverse order! */ -+#define DT_VERSIONTAGNUM 16 -+ -+/* Sun added these machine-independent extensions in the "processor-specific" -+ range. Be compatible. */ -+#define DT_AUXILIARY 0x7ffffffd /* Shared object to load before self */ -+#define DT_FILTER 0x7fffffff /* Shared object to get values from */ -+#define DT_EXTRATAGIDX(tag) ((Elf32_Word)-((Elf32_Sword) (tag) <<1>>1)-1) -+#define DT_EXTRANUM 3 -+ -+/* Values of `d_un.d_val' in the DT_FLAGS entry. */ -+#define DF_ORIGIN 0x00000001 /* Object may use DF_ORIGIN */ -+#define DF_SYMBOLIC 0x00000002 /* Symbol resolutions starts here */ -+#define DF_TEXTREL 0x00000004 /* Object contains text relocations */ -+#define DF_BIND_NOW 0x00000008 /* No lazy binding for this object */ -+#define DF_STATIC_TLS 0x00000010 /* Module uses the static TLS model */ -+ -+/* State flags selectable in the `d_un.d_val' element of the DT_FLAGS_1 -+ entry in the dynamic section. */ -+#define DF_1_NOW 0x00000001 /* Set RTLD_NOW for this object. */ -+#define DF_1_GLOBAL 0x00000002 /* Set RTLD_GLOBAL for this object. */ -+#define DF_1_GROUP 0x00000004 /* Set RTLD_GROUP for this object. */ -+#define DF_1_NODELETE 0x00000008 /* Set RTLD_NODELETE for this object.*/ -+#define DF_1_LOADFLTR 0x00000010 /* Trigger filtee loading at runtime.*/ -+#define DF_1_INITFIRST 0x00000020 /* Set RTLD_INITFIRST for this object*/ -+#define DF_1_NOOPEN 0x00000040 /* Set RTLD_NOOPEN for this object. */ -+#define DF_1_ORIGIN 0x00000080 /* $ORIGIN must be handled. */ -+#define DF_1_DIRECT 0x00000100 /* Direct binding enabled. */ -+#define DF_1_TRANS 0x00000200 -+#define DF_1_INTERPOSE 0x00000400 /* Object is used to interpose. */ -+#define DF_1_NODEFLIB 0x00000800 /* Ignore default lib search path. */ -+#define DF_1_NODUMP 0x00001000 /* Object can't be dldump'ed. */ -+#define DF_1_CONFALT 0x00002000 /* Configuration alternative created.*/ -+#define DF_1_ENDFILTEE 0x00004000 /* Filtee terminates filters search. */ -+#define DF_1_DISPRELDNE 0x00008000 /* Disp reloc applied at build time. */ -+#define DF_1_DISPRELPND 0x00010000 /* Disp reloc applied at run-time. */ -+ -+/* Flags for the feature selection in DT_FEATURE_1. */ -+#define DTF_1_PARINIT 0x00000001 -+#define DTF_1_CONFEXP 0x00000002 -+ -+/* Flags in the DT_POSFLAG_1 entry effecting only the next DT_* entry. */ -+#define DF_P1_LAZYLOAD 0x00000001 /* Lazyload following object. */ -+#define DF_P1_GROUPPERM 0x00000002 /* Symbols from next object are not -+ generally available. */ -+ -+/* Version definition sections. */ -+ -+typedef struct -+{ -+ Elf32_Half vd_version; /* Version revision */ -+ Elf32_Half vd_flags; /* Version information */ -+ Elf32_Half vd_ndx; /* Version Index */ -+ Elf32_Half vd_cnt; /* Number of associated aux entries */ -+ Elf32_Word vd_hash; /* Version name hash value */ -+ Elf32_Word vd_aux; /* Offset in bytes to verdaux array */ -+ Elf32_Word vd_next; /* Offset in bytes to next verdef -+ entry */ -+} Elf32_Verdef; -+ -+typedef struct -+{ -+ Elf64_Half vd_version; /* Version revision */ -+ Elf64_Half vd_flags; /* Version information */ -+ Elf64_Half vd_ndx; /* Version Index */ -+ Elf64_Half vd_cnt; /* Number of associated aux entries */ -+ Elf64_Word vd_hash; /* Version name hash value */ -+ Elf64_Word vd_aux; /* Offset in bytes to verdaux array */ -+ Elf64_Word vd_next; /* Offset in bytes to next verdef -+ entry */ -+} Elf64_Verdef; -+ -+ -+/* Legal values for vd_version (version revision). */ -+#define VER_DEF_NONE 0 /* No version */ -+#define VER_DEF_CURRENT 1 /* Current version */ -+#define VER_DEF_NUM 2 /* Given version number */ -+ -+/* Legal values for vd_flags (version information flags). */ -+#define VER_FLG_BASE 0x1 /* Version definition of file itself */ -+#define VER_FLG_WEAK 0x2 /* Weak version identifier */ -+ -+/* Versym symbol index values. */ -+#define VER_NDX_LOCAL 0 /* Symbol is local. */ -+#define VER_NDX_GLOBAL 1 /* Symbol is global. */ -+#define VER_NDX_LORESERVE 0xff00 /* Beginning of reserved entries. */ -+#define VER_NDX_ELIMINATE 0xff01 /* Symbol is to be eliminated. */ -+ -+/* Auxialiary version information. */ -+ -+typedef struct -+{ -+ Elf32_Word vda_name; /* Version or dependency names */ -+ Elf32_Word vda_next; /* Offset in bytes to next verdaux -+ entry */ -+} Elf32_Verdaux; -+ -+typedef struct -+{ -+ Elf64_Word vda_name; /* Version or dependency names */ -+ Elf64_Word vda_next; /* Offset in bytes to next verdaux -+ entry */ -+} Elf64_Verdaux; -+ -+ -+/* Version dependency section. */ -+ -+typedef struct -+{ -+ Elf32_Half vn_version; /* Version of structure */ -+ Elf32_Half vn_cnt; /* Number of associated aux entries */ -+ Elf32_Word vn_file; /* Offset of filename for this -+ dependency */ -+ Elf32_Word vn_aux; /* Offset in bytes to vernaux array */ -+ Elf32_Word vn_next; /* Offset in bytes to next verneed -+ entry */ -+} Elf32_Verneed; -+ -+typedef struct -+{ -+ Elf64_Half vn_version; /* Version of structure */ -+ Elf64_Half vn_cnt; /* Number of associated aux entries */ -+ Elf64_Word vn_file; /* Offset of filename for this -+ dependency */ -+ Elf64_Word vn_aux; /* Offset in bytes to vernaux array */ -+ Elf64_Word vn_next; /* Offset in bytes to next verneed -+ entry */ -+} Elf64_Verneed; -+ -+ -+/* Legal values for vn_version (version revision). */ -+#define VER_NEED_NONE 0 /* No version */ -+#define VER_NEED_CURRENT 1 /* Current version */ -+#define VER_NEED_NUM 2 /* Given version number */ -+ -+/* Auxiliary needed version information. */ -+ -+typedef struct -+{ -+ Elf32_Word vna_hash; /* Hash value of dependency name */ -+ Elf32_Half vna_flags; /* Dependency specific information */ -+ Elf32_Half vna_other; /* Unused */ -+ Elf32_Word vna_name; /* Dependency name string offset */ -+ Elf32_Word vna_next; /* Offset in bytes to next vernaux -+ entry */ -+} Elf32_Vernaux; -+ -+typedef struct -+{ -+ Elf64_Word vna_hash; /* Hash value of dependency name */ -+ Elf64_Half vna_flags; /* Dependency specific information */ -+ Elf64_Half vna_other; /* Unused */ -+ Elf64_Word vna_name; /* Dependency name string offset */ -+ Elf64_Word vna_next; /* Offset in bytes to next vernaux -+ entry */ -+} Elf64_Vernaux; -+ -+ -+/* Legal values for vna_flags. */ -+#define VER_FLG_WEAK 0x2 /* Weak version identifier */ -+ -+ -+/* Auxiliary vector. */ -+ -+/* This vector is normally only used by the program interpreter. The -+ usual definition in an ABI supplement uses the name auxv_t. The -+ vector is not usually defined in a standard file, but it -+ can't hurt. We rename it to avoid conflicts. The sizes of these -+ types are an arrangement between the exec server and the program -+ interpreter, so we don't fully specify them here. */ -+ -+typedef struct -+{ -+ int a_type; /* Entry type */ -+ union -+ { -+ long int a_val; /* Integer value */ -+ void *a_ptr; /* Pointer value */ -+ void (*a_fcn) (void); /* Function pointer value */ -+ } a_un; -+} Elf32_auxv_t; -+ -+typedef struct -+{ -+ long int a_type; /* Entry type */ -+ union -+ { -+ long int a_val; /* Integer value */ -+ void *a_ptr; /* Pointer value */ -+ void (*a_fcn) (void); /* Function pointer value */ -+ } a_un; -+} Elf64_auxv_t; -+ -+/* Legal values for a_type (entry type). */ -+ -+#define AT_NULL 0 /* End of vector */ -+#define AT_IGNORE 1 /* Entry should be ignored */ -+#define AT_EXECFD 2 /* File descriptor of program */ -+#define AT_PHDR 3 /* Program headers for program */ -+#define AT_PHENT 4 /* Size of program header entry */ -+#define AT_PHNUM 5 /* Number of program headers */ -+#define AT_PAGESZ 6 /* System page size */ -+#define AT_BASE 7 /* Base address of interpreter */ -+#define AT_FLAGS 8 /* Flags */ -+#define AT_ENTRY 9 /* Entry point of program */ -+#define AT_NOTELF 10 /* Program is not ELF */ -+#define AT_UID 11 /* Real uid */ -+#define AT_EUID 12 /* Effective uid */ -+#define AT_GID 13 /* Real gid */ -+#define AT_EGID 14 /* Effective gid */ -+#define AT_CLKTCK 17 /* Frequency of times() */ -+ -+/* Some more special a_type values describing the hardware. */ -+#define AT_PLATFORM 15 /* String identifying platform. */ -+#define AT_HWCAP 16 /* Machine dependent hints about -+ processor capabilities. */ -+ -+/* This entry gives some information about the FPU initialization -+ performed by the kernel. */ -+#define AT_FPUCW 18 /* Used FPU control word. */ -+ -+/* Cache block sizes. */ -+#define AT_DCACHEBSIZE 19 /* Data cache block size. */ -+#define AT_ICACHEBSIZE 20 /* Instruction cache block size. */ -+#define AT_UCACHEBSIZE 21 /* Unified cache block size. */ -+ -+/* A special ignored value for PPC, used by the kernel to control the -+ interpretation of the AUXV. Must be > 16. */ -+#define AT_IGNOREPPC 22 /* Entry should be ignored. */ -+ -+#define AT_SECURE 23 /* Boolean, was exec setuid-like? */ -+ -+/* Pointer to the global system page used for system calls and other -+ nice things. */ -+#define AT_SYSINFO 32 -+#define AT_SYSINFO_EHDR 33 -+ -+ -+/* Note section contents. Each entry in the note section begins with -+ a header of a fixed form. */ -+ -+typedef struct -+{ -+ Elf32_Word n_namesz; /* Length of the note's name. */ -+ Elf32_Word n_descsz; /* Length of the note's descriptor. */ -+ Elf32_Word n_type; /* Type of the note. */ -+} Elf32_Nhdr; -+ -+typedef struct -+{ -+ Elf64_Word n_namesz; /* Length of the note's name. */ -+ Elf64_Word n_descsz; /* Length of the note's descriptor. */ -+ Elf64_Word n_type; /* Type of the note. */ -+} Elf64_Nhdr; -+ -+/* Known names of notes. */ -+ -+/* Solaris entries in the note section have this name. */ -+#define ELF_NOTE_SOLARIS "SUNW Solaris" -+ -+/* Note entries for GNU systems have this name. */ -+#define ELF_NOTE_GNU "GNU" -+ -+ -+/* Defined types of notes for Solaris. */ -+ -+/* Value of descriptor (one word) is desired pagesize for the binary. */ -+#define ELF_NOTE_PAGESIZE_HINT 1 -+ -+ -+/* Defined note types for GNU systems. */ -+ -+/* ABI information. The descriptor consists of words: -+ word 0: OS descriptor -+ word 1: major version of the ABI -+ word 2: minor version of the ABI -+ word 3: subminor version of the ABI -+*/ -+#define ELF_NOTE_ABI 1 -+ -+/* Known OSes. These value can appear in word 0 of an ELF_NOTE_ABI -+ note section entry. */ -+#define ELF_NOTE_OS_LINUX 0 -+#define ELF_NOTE_OS_GNU 1 -+#define ELF_NOTE_OS_SOLARIS2 2 -+#define ELF_NOTE_OS_FREEBSD 3 -+ -+ -+/* Move records. */ -+typedef struct -+{ -+ Elf32_Xword m_value; /* Symbol value. */ -+ Elf32_Word m_info; /* Size and index. */ -+ Elf32_Word m_poffset; /* Symbol offset. */ -+ Elf32_Half m_repeat; /* Repeat count. */ -+ Elf32_Half m_stride; /* Stride info. */ -+} Elf32_Move; -+ -+typedef struct -+{ -+ Elf64_Xword m_value; /* Symbol value. */ -+ Elf64_Xword m_info; /* Size and index. */ -+ Elf64_Xword m_poffset; /* Symbol offset. */ -+ Elf64_Half m_repeat; /* Repeat count. */ -+ Elf64_Half m_stride; /* Stride info. */ -+} Elf64_Move; -+ -+/* Macro to construct move records. */ -+#define ELF32_M_SYM(info) ((info) >> 8) -+#define ELF32_M_SIZE(info) ((unsigned char) (info)) -+#define ELF32_M_INFO(sym, size) (((sym) << 8) + (unsigned char) (size)) -+ -+#define ELF64_M_SYM(info) ELF32_M_SYM (info) -+#define ELF64_M_SIZE(info) ELF32_M_SIZE (info) -+#define ELF64_M_INFO(sym, size) ELF32_M_INFO (sym, size) -+ -+ -+/* Motorola 68k specific definitions. */ -+ -+/* Values for Elf32_Ehdr.e_flags. */ -+#define EF_CPU32 0x00810000 -+ -+/* m68k relocs. */ -+ -+#define R_68K_NONE 0 /* No reloc */ -+#define R_68K_32 1 /* Direct 32 bit */ -+#define R_68K_16 2 /* Direct 16 bit */ -+#define R_68K_8 3 /* Direct 8 bit */ -+#define R_68K_PC32 4 /* PC relative 32 bit */ -+#define R_68K_PC16 5 /* PC relative 16 bit */ -+#define R_68K_PC8 6 /* PC relative 8 bit */ -+#define R_68K_GOT32 7 /* 32 bit PC relative GOT entry */ -+#define R_68K_GOT16 8 /* 16 bit PC relative GOT entry */ -+#define R_68K_GOT8 9 /* 8 bit PC relative GOT entry */ -+#define R_68K_GOT32O 10 /* 32 bit GOT offset */ -+#define R_68K_GOT16O 11 /* 16 bit GOT offset */ -+#define R_68K_GOT8O 12 /* 8 bit GOT offset */ -+#define R_68K_PLT32 13 /* 32 bit PC relative PLT address */ -+#define R_68K_PLT16 14 /* 16 bit PC relative PLT address */ -+#define R_68K_PLT8 15 /* 8 bit PC relative PLT address */ -+#define R_68K_PLT32O 16 /* 32 bit PLT offset */ -+#define R_68K_PLT16O 17 /* 16 bit PLT offset */ -+#define R_68K_PLT8O 18 /* 8 bit PLT offset */ -+#define R_68K_COPY 19 /* Copy symbol at runtime */ -+#define R_68K_GLOB_DAT 20 /* Create GOT entry */ -+#define R_68K_JMP_SLOT 21 /* Create PLT entry */ -+#define R_68K_RELATIVE 22 /* Adjust by program base */ -+/* Keep this the last entry. */ -+#define R_68K_NUM 23 -+ -+/* Intel 80386 specific definitions. */ -+ -+/* i386 relocs. */ -+ -+#define R_386_NONE 0 /* No reloc */ -+#define R_386_32 1 /* Direct 32 bit */ -+#define R_386_PC32 2 /* PC relative 32 bit */ -+#define R_386_GOT32 3 /* 32 bit GOT entry */ -+#define R_386_PLT32 4 /* 32 bit PLT address */ -+#define R_386_COPY 5 /* Copy symbol at runtime */ -+#define R_386_GLOB_DAT 6 /* Create GOT entry */ -+#define R_386_JMP_SLOT 7 /* Create PLT entry */ -+#define R_386_RELATIVE 8 /* Adjust by program base */ -+#define R_386_GOTOFF 9 /* 32 bit offset to GOT */ -+#define R_386_GOTPC 10 /* 32 bit PC relative offset to GOT */ -+#define R_386_32PLT 11 -+#define R_386_TLS_TPOFF 14 /* Offset in static TLS block */ -+#define R_386_TLS_IE 15 /* Address of GOT entry for static TLS -+ block offset */ -+#define R_386_TLS_GOTIE 16 /* GOT entry for static TLS block -+ offset */ -+#define R_386_TLS_LE 17 /* Offset relative to static TLS -+ block */ -+#define R_386_TLS_GD 18 /* Direct 32 bit for GNU version of -+ general dynamic thread local data */ -+#define R_386_TLS_LDM 19 /* Direct 32 bit for GNU version of -+ local dynamic thread local data -+ in LE code */ -+#define R_386_16 20 -+#define R_386_PC16 21 -+#define R_386_8 22 -+#define R_386_PC8 23 -+#define R_386_TLS_GD_32 24 /* Direct 32 bit for general dynamic -+ thread local data */ -+#define R_386_TLS_GD_PUSH 25 /* Tag for pushl in GD TLS code */ -+#define R_386_TLS_GD_CALL 26 /* Relocation for call to -+ __tls_get_addr() */ -+#define R_386_TLS_GD_POP 27 /* Tag for popl in GD TLS code */ -+#define R_386_TLS_LDM_32 28 /* Direct 32 bit for local dynamic -+ thread local data in LE code */ -+#define R_386_TLS_LDM_PUSH 29 /* Tag for pushl in LDM TLS code */ -+#define R_386_TLS_LDM_CALL 30 /* Relocation for call to -+ __tls_get_addr() in LDM code */ -+#define R_386_TLS_LDM_POP 31 /* Tag for popl in LDM TLS code */ -+#define R_386_TLS_LDO_32 32 /* Offset relative to TLS block */ -+#define R_386_TLS_IE_32 33 /* GOT entry for negated static TLS -+ block offset */ -+#define R_386_TLS_LE_32 34 /* Negated offset relative to static -+ TLS block */ -+#define R_386_TLS_DTPMOD32 35 /* ID of module containing symbol */ -+#define R_386_TLS_DTPOFF32 36 /* Offset in TLS block */ -+#define R_386_TLS_TPOFF32 37 /* Negated offset in static TLS block */ -+/* Keep this the last entry. */ -+#define R_386_NUM 38 -+ -+/* SUN SPARC specific definitions. */ -+ -+/* Legal values for ST_TYPE subfield of st_info (symbol type). */ -+ -+#define STT_REGISTER 13 /* Global register reserved to app. */ -+ -+/* Values for Elf64_Ehdr.e_flags. */ -+ -+#define EF_SPARCV9_MM 3 -+#define EF_SPARCV9_TSO 0 -+#define EF_SPARCV9_PSO 1 -+#define EF_SPARCV9_RMO 2 -+#define EF_SPARC_LEDATA 0x800000 /* little endian data */ -+#define EF_SPARC_EXT_MASK 0xFFFF00 -+#define EF_SPARC_32PLUS 0x000100 /* generic V8+ features */ -+#define EF_SPARC_SUN_US1 0x000200 /* Sun UltraSPARC1 extensions */ -+#define EF_SPARC_HAL_R1 0x000400 /* HAL R1 extensions */ -+#define EF_SPARC_SUN_US3 0x000800 /* Sun UltraSPARCIII extensions */ -+ -+/* SPARC relocs. */ -+ -+#define R_SPARC_NONE 0 /* No reloc */ -+#define R_SPARC_8 1 /* Direct 8 bit */ -+#define R_SPARC_16 2 /* Direct 16 bit */ -+#define R_SPARC_32 3 /* Direct 32 bit */ -+#define R_SPARC_DISP8 4 /* PC relative 8 bit */ -+#define R_SPARC_DISP16 5 /* PC relative 16 bit */ -+#define R_SPARC_DISP32 6 /* PC relative 32 bit */ -+#define R_SPARC_WDISP30 7 /* PC relative 30 bit shifted */ -+#define R_SPARC_WDISP22 8 /* PC relative 22 bit shifted */ -+#define R_SPARC_HI22 9 /* High 22 bit */ -+#define R_SPARC_22 10 /* Direct 22 bit */ -+#define R_SPARC_13 11 /* Direct 13 bit */ -+#define R_SPARC_LO10 12 /* Truncated 10 bit */ -+#define R_SPARC_GOT10 13 /* Truncated 10 bit GOT entry */ -+#define R_SPARC_GOT13 14 /* 13 bit GOT entry */ -+#define R_SPARC_GOT22 15 /* 22 bit GOT entry shifted */ -+#define R_SPARC_PC10 16 /* PC relative 10 bit truncated */ -+#define R_SPARC_PC22 17 /* PC relative 22 bit shifted */ -+#define R_SPARC_WPLT30 18 /* 30 bit PC relative PLT address */ -+#define R_SPARC_COPY 19 /* Copy symbol at runtime */ -+#define R_SPARC_GLOB_DAT 20 /* Create GOT entry */ -+#define R_SPARC_JMP_SLOT 21 /* Create PLT entry */ -+#define R_SPARC_RELATIVE 22 /* Adjust by program base */ -+#define R_SPARC_UA32 23 /* Direct 32 bit unaligned */ -+ -+/* Additional Sparc64 relocs. */ -+ -+#define R_SPARC_PLT32 24 /* Direct 32 bit ref to PLT entry */ -+#define R_SPARC_HIPLT22 25 /* High 22 bit PLT entry */ -+#define R_SPARC_LOPLT10 26 /* Truncated 10 bit PLT entry */ -+#define R_SPARC_PCPLT32 27 /* PC rel 32 bit ref to PLT entry */ -+#define R_SPARC_PCPLT22 28 /* PC rel high 22 bit PLT entry */ -+#define R_SPARC_PCPLT10 29 /* PC rel trunc 10 bit PLT entry */ -+#define R_SPARC_10 30 /* Direct 10 bit */ -+#define R_SPARC_11 31 /* Direct 11 bit */ -+#define R_SPARC_64 32 /* Direct 64 bit */ -+#define R_SPARC_OLO10 33 /* 10bit with secondary 13bit addend */ -+#define R_SPARC_HH22 34 /* Top 22 bits of direct 64 bit */ -+#define R_SPARC_HM10 35 /* High middle 10 bits of ... */ -+#define R_SPARC_LM22 36 /* Low middle 22 bits of ... */ -+#define R_SPARC_PC_HH22 37 /* Top 22 bits of pc rel 64 bit */ -+#define R_SPARC_PC_HM10 38 /* High middle 10 bit of ... */ -+#define R_SPARC_PC_LM22 39 /* Low miggle 22 bits of ... */ -+#define R_SPARC_WDISP16 40 /* PC relative 16 bit shifted */ -+#define R_SPARC_WDISP19 41 /* PC relative 19 bit shifted */ -+#define R_SPARC_7 43 /* Direct 7 bit */ -+#define R_SPARC_5 44 /* Direct 5 bit */ -+#define R_SPARC_6 45 /* Direct 6 bit */ -+#define R_SPARC_DISP64 46 /* PC relative 64 bit */ -+#define R_SPARC_PLT64 47 /* Direct 64 bit ref to PLT entry */ -+#define R_SPARC_HIX22 48 /* High 22 bit complemented */ -+#define R_SPARC_LOX10 49 /* Truncated 11 bit complemented */ -+#define R_SPARC_H44 50 /* Direct high 12 of 44 bit */ -+#define R_SPARC_M44 51 /* Direct mid 22 of 44 bit */ -+#define R_SPARC_L44 52 /* Direct low 10 of 44 bit */ -+#define R_SPARC_REGISTER 53 /* Global register usage */ -+#define R_SPARC_UA64 54 /* Direct 64 bit unaligned */ -+#define R_SPARC_UA16 55 /* Direct 16 bit unaligned */ -+#define R_SPARC_TLS_GD_HI22 56 -+#define R_SPARC_TLS_GD_LO10 57 -+#define R_SPARC_TLS_GD_ADD 58 -+#define R_SPARC_TLS_GD_CALL 59 -+#define R_SPARC_TLS_LDM_HI22 60 -+#define R_SPARC_TLS_LDM_LO10 61 -+#define R_SPARC_TLS_LDM_ADD 62 -+#define R_SPARC_TLS_LDM_CALL 63 -+#define R_SPARC_TLS_LDO_HIX22 64 -+#define R_SPARC_TLS_LDO_LOX10 65 -+#define R_SPARC_TLS_LDO_ADD 66 -+#define R_SPARC_TLS_IE_HI22 67 -+#define R_SPARC_TLS_IE_LO10 68 -+#define R_SPARC_TLS_IE_LD 69 -+#define R_SPARC_TLS_IE_LDX 70 -+#define R_SPARC_TLS_IE_ADD 71 -+#define R_SPARC_TLS_LE_HIX22 72 -+#define R_SPARC_TLS_LE_LOX10 73 -+#define R_SPARC_TLS_DTPMOD32 74 -+#define R_SPARC_TLS_DTPMOD64 75 -+#define R_SPARC_TLS_DTPOFF32 76 -+#define R_SPARC_TLS_DTPOFF64 77 -+#define R_SPARC_TLS_TPOFF32 78 -+#define R_SPARC_TLS_TPOFF64 79 -+/* Keep this the last entry. */ -+#define R_SPARC_NUM 80 -+ -+/* For Sparc64, legal values for d_tag of Elf64_Dyn. */ -+ -+#define DT_SPARC_REGISTER 0x70000001 -+#define DT_SPARC_NUM 2 -+ -+/* Bits present in AT_HWCAP, primarily for Sparc32. */ -+ -+#define HWCAP_SPARC_FLUSH 1 /* The cpu supports flush insn. */ -+#define HWCAP_SPARC_STBAR 2 -+#define HWCAP_SPARC_SWAP 4 -+#define HWCAP_SPARC_MULDIV 8 -+#define HWCAP_SPARC_V9 16 /* The cpu is v9, so v8plus is ok. */ -+#define HWCAP_SPARC_ULTRA3 32 -+ -+/* MIPS R3000 specific definitions. */ -+ -+/* Legal values for e_flags field of Elf32_Ehdr. */ -+ -+#define EF_MIPS_NOREORDER 1 /* A .noreorder directive was used */ -+#define EF_MIPS_PIC 2 /* Contains PIC code */ -+#define EF_MIPS_CPIC 4 /* Uses PIC calling sequence */ -+#define EF_MIPS_XGOT 8 -+#define EF_MIPS_64BIT_WHIRL 16 -+#define EF_MIPS_ABI2 32 -+#define EF_MIPS_ABI_ON32 64 -+#define EF_MIPS_ARCH 0xf0000000 /* MIPS architecture level */ -+ -+/* Legal values for MIPS architecture level. */ -+ -+#define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ -+#define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ -+#define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ -+#define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ -+#define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ -+#define EF_MIPS_ARCH_32 0x60000000 /* MIPS32 code. */ -+#define EF_MIPS_ARCH_64 0x70000000 /* MIPS64 code. */ -+ -+/* The following are non-official names and should not be used. */ -+ -+#define E_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ -+#define E_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ -+#define E_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ -+#define E_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ -+#define E_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ -+#define E_MIPS_ARCH_32 0x60000000 /* MIPS32 code. */ -+#define E_MIPS_ARCH_64 0x70000000 /* MIPS64 code. */ -+ -+/* Special section indices. */ -+ -+#define SHN_MIPS_ACOMMON 0xff00 /* Allocated common symbols */ -+#define SHN_MIPS_TEXT 0xff01 /* Allocated test symbols. */ -+#define SHN_MIPS_DATA 0xff02 /* Allocated data symbols. */ -+#define SHN_MIPS_SCOMMON 0xff03 /* Small common symbols */ -+#define SHN_MIPS_SUNDEFINED 0xff04 /* Small undefined symbols */ -+ -+/* Legal values for sh_type field of Elf32_Shdr. */ -+ -+#define SHT_MIPS_LIBLIST 0x70000000 /* Shared objects used in link */ -+#define SHT_MIPS_MSYM 0x70000001 -+#define SHT_MIPS_CONFLICT 0x70000002 /* Conflicting symbols */ -+#define SHT_MIPS_GPTAB 0x70000003 /* Global data area sizes */ -+#define SHT_MIPS_UCODE 0x70000004 /* Reserved for SGI/MIPS compilers */ -+#define SHT_MIPS_DEBUG 0x70000005 /* MIPS ECOFF debugging information*/ -+#define SHT_MIPS_REGINFO 0x70000006 /* Register usage information */ -+#define SHT_MIPS_PACKAGE 0x70000007 -+#define SHT_MIPS_PACKSYM 0x70000008 -+#define SHT_MIPS_RELD 0x70000009 -+#define SHT_MIPS_IFACE 0x7000000b -+#define SHT_MIPS_CONTENT 0x7000000c -+#define SHT_MIPS_OPTIONS 0x7000000d /* Miscellaneous options. */ -+#define SHT_MIPS_SHDR 0x70000010 -+#define SHT_MIPS_FDESC 0x70000011 -+#define SHT_MIPS_EXTSYM 0x70000012 -+#define SHT_MIPS_DENSE 0x70000013 -+#define SHT_MIPS_PDESC 0x70000014 -+#define SHT_MIPS_LOCSYM 0x70000015 -+#define SHT_MIPS_AUXSYM 0x70000016 -+#define SHT_MIPS_OPTSYM 0x70000017 -+#define SHT_MIPS_LOCSTR 0x70000018 -+#define SHT_MIPS_LINE 0x70000019 -+#define SHT_MIPS_RFDESC 0x7000001a -+#define SHT_MIPS_DELTASYM 0x7000001b -+#define SHT_MIPS_DELTAINST 0x7000001c -+#define SHT_MIPS_DELTACLASS 0x7000001d -+#define SHT_MIPS_DWARF 0x7000001e /* DWARF debugging information. */ -+#define SHT_MIPS_DELTADECL 0x7000001f -+#define SHT_MIPS_SYMBOL_LIB 0x70000020 -+#define SHT_MIPS_EVENTS 0x70000021 /* Event section. */ -+#define SHT_MIPS_TRANSLATE 0x70000022 -+#define SHT_MIPS_PIXIE 0x70000023 -+#define SHT_MIPS_XLATE 0x70000024 -+#define SHT_MIPS_XLATE_DEBUG 0x70000025 -+#define SHT_MIPS_WHIRL 0x70000026 -+#define SHT_MIPS_EH_REGION 0x70000027 -+#define SHT_MIPS_XLATE_OLD 0x70000028 -+#define SHT_MIPS_PDR_EXCEPTION 0x70000029 -+ -+/* Legal values for sh_flags field of Elf32_Shdr. */ -+ -+#define SHF_MIPS_GPREL 0x10000000 /* Must be part of global data area */ -+#define SHF_MIPS_MERGE 0x20000000 -+#define SHF_MIPS_ADDR 0x40000000 -+#define SHF_MIPS_STRINGS 0x80000000 -+#define SHF_MIPS_NOSTRIP 0x08000000 -+#define SHF_MIPS_LOCAL 0x04000000 -+#define SHF_MIPS_NAMES 0x02000000 -+#define SHF_MIPS_NODUPE 0x01000000 -+ -+ -+/* Symbol tables. */ -+ -+/* MIPS specific values for `st_other'. */ -+#define STO_MIPS_DEFAULT 0x0 -+#define STO_MIPS_INTERNAL 0x1 -+#define STO_MIPS_HIDDEN 0x2 -+#define STO_MIPS_PROTECTED 0x3 -+#define STO_MIPS_SC_ALIGN_UNUSED 0xff -+ -+/* MIPS specific values for `st_info'. */ -+#define STB_MIPS_SPLIT_COMMON 13 -+ -+/* Entries found in sections of type SHT_MIPS_GPTAB. */ -+ -+typedef union -+{ -+ struct -+ { -+ Elf32_Word gt_current_g_value; /* -G value used for compilation */ -+ Elf32_Word gt_unused; /* Not used */ -+ } gt_header; /* First entry in section */ -+ struct -+ { -+ Elf32_Word gt_g_value; /* If this value were used for -G */ -+ Elf32_Word gt_bytes; /* This many bytes would be used */ -+ } gt_entry; /* Subsequent entries in section */ -+} Elf32_gptab; -+ -+/* Entry found in sections of type SHT_MIPS_REGINFO. */ -+ -+typedef struct -+{ -+ Elf32_Word ri_gprmask; /* General registers used */ -+ Elf32_Word ri_cprmask[4]; /* Coprocessor registers used */ -+ Elf32_Sword ri_gp_value; /* $gp register value */ -+} Elf32_RegInfo; -+ -+/* Entries found in sections of type SHT_MIPS_OPTIONS. */ -+ -+typedef struct -+{ -+ unsigned char kind; /* Determines interpretation of the -+ variable part of descriptor. */ -+ unsigned char size; /* Size of descriptor, including header. */ -+ Elf32_Section section; /* Section header index of section affected, -+ 0 for global options. */ -+ Elf32_Word info; /* Kind-specific information. */ -+} Elf_Options; -+ -+/* Values for `kind' field in Elf_Options. */ -+ -+#define ODK_NULL 0 /* Undefined. */ -+#define ODK_REGINFO 1 /* Register usage information. */ -+#define ODK_EXCEPTIONS 2 /* Exception processing options. */ -+#define ODK_PAD 3 /* Section padding options. */ -+#define ODK_HWPATCH 4 /* Hardware workarounds performed */ -+#define ODK_FILL 5 /* record the fill value used by the linker. */ -+#define ODK_TAGS 6 /* reserve space for desktop tools to write. */ -+#define ODK_HWAND 7 /* HW workarounds. 'AND' bits when merging. */ -+#define ODK_HWOR 8 /* HW workarounds. 'OR' bits when merging. */ -+ -+/* Values for `info' in Elf_Options for ODK_EXCEPTIONS entries. */ -+ -+#define OEX_FPU_MIN 0x1f /* FPE's which MUST be enabled. */ -+#define OEX_FPU_MAX 0x1f00 /* FPE's which MAY be enabled. */ -+#define OEX_PAGE0 0x10000 /* page zero must be mapped. */ -+#define OEX_SMM 0x20000 /* Force sequential memory mode? */ -+#define OEX_FPDBUG 0x40000 /* Force floating point debug mode? */ -+#define OEX_PRECISEFP OEX_FPDBUG -+#define OEX_DISMISS 0x80000 /* Dismiss invalid address faults? */ -+ -+#define OEX_FPU_INVAL 0x10 -+#define OEX_FPU_DIV0 0x08 -+#define OEX_FPU_OFLO 0x04 -+#define OEX_FPU_UFLO 0x02 -+#define OEX_FPU_INEX 0x01 -+ -+/* Masks for `info' in Elf_Options for an ODK_HWPATCH entry. */ -+ -+#define OHW_R4KEOP 0x1 /* R4000 end-of-page patch. */ -+#define OHW_R8KPFETCH 0x2 /* may need R8000 prefetch patch. */ -+#define OHW_R5KEOP 0x4 /* R5000 end-of-page patch. */ -+#define OHW_R5KCVTL 0x8 /* R5000 cvt.[ds].l bug. clean=1. */ -+ -+#define OPAD_PREFIX 0x1 -+#define OPAD_POSTFIX 0x2 -+#define OPAD_SYMBOL 0x4 -+ -+/* Entry found in `.options' section. */ -+ -+typedef struct -+{ -+ Elf32_Word hwp_flags1; /* Extra flags. */ -+ Elf32_Word hwp_flags2; /* Extra flags. */ -+} Elf_Options_Hw; -+ -+/* Masks for `info' in ElfOptions for ODK_HWAND and ODK_HWOR entries. */ -+ -+#define OHWA0_R4KEOP_CHECKED 0x00000001 -+#define OHWA1_R4KEOP_CLEAN 0x00000002 -+ -+/* MIPS relocs. */ -+ -+#define R_MIPS_NONE 0 /* No reloc */ -+#define R_MIPS_16 1 /* Direct 16 bit */ -+#define R_MIPS_32 2 /* Direct 32 bit */ -+#define R_MIPS_REL32 3 /* PC relative 32 bit */ -+#define R_MIPS_26 4 /* Direct 26 bit shifted */ -+#define R_MIPS_HI16 5 /* High 16 bit */ -+#define R_MIPS_LO16 6 /* Low 16 bit */ -+#define R_MIPS_GPREL16 7 /* GP relative 16 bit */ -+#define R_MIPS_LITERAL 8 /* 16 bit literal entry */ -+#define R_MIPS_GOT16 9 /* 16 bit GOT entry */ -+#define R_MIPS_PC16 10 /* PC relative 16 bit */ -+#define R_MIPS_CALL16 11 /* 16 bit GOT entry for function */ -+#define R_MIPS_GPREL32 12 /* GP relative 32 bit */ -+ -+#define R_MIPS_SHIFT5 16 -+#define R_MIPS_SHIFT6 17 -+#define R_MIPS_64 18 -+#define R_MIPS_GOT_DISP 19 -+#define R_MIPS_GOT_PAGE 20 -+#define R_MIPS_GOT_OFST 21 -+#define R_MIPS_GOT_HI16 22 -+#define R_MIPS_GOT_LO16 23 -+#define R_MIPS_SUB 24 -+#define R_MIPS_INSERT_A 25 -+#define R_MIPS_INSERT_B 26 -+#define R_MIPS_DELETE 27 -+#define R_MIPS_HIGHER 28 -+#define R_MIPS_HIGHEST 29 -+#define R_MIPS_CALL_HI16 30 -+#define R_MIPS_CALL_LO16 31 -+#define R_MIPS_SCN_DISP 32 -+#define R_MIPS_REL16 33 -+#define R_MIPS_ADD_IMMEDIATE 34 -+#define R_MIPS_PJUMP 35 -+#define R_MIPS_RELGOT 36 -+#define R_MIPS_JALR 37 -+/* Keep this the last entry. */ -+#define R_MIPS_NUM 38 -+ -+/* Legal values for p_type field of Elf32_Phdr. */ -+ -+#define PT_MIPS_REGINFO 0x70000000 /* Register usage information */ -+#define PT_MIPS_RTPROC 0x70000001 /* Runtime procedure table. */ -+#define PT_MIPS_OPTIONS 0x70000002 -+ -+/* Special program header types. */ -+ -+#define PF_MIPS_LOCAL 0x10000000 -+ -+/* Legal values for d_tag field of Elf32_Dyn. */ -+ -+#define DT_MIPS_RLD_VERSION 0x70000001 /* Runtime linker interface version */ -+#define DT_MIPS_TIME_STAMP 0x70000002 /* Timestamp */ -+#define DT_MIPS_ICHECKSUM 0x70000003 /* Checksum */ -+#define DT_MIPS_IVERSION 0x70000004 /* Version string (string tbl index) */ -+#define DT_MIPS_FLAGS 0x70000005 /* Flags */ -+#define DT_MIPS_BASE_ADDRESS 0x70000006 /* Base address */ -+#define DT_MIPS_MSYM 0x70000007 -+#define DT_MIPS_CONFLICT 0x70000008 /* Address of CONFLICT section */ -+#define DT_MIPS_LIBLIST 0x70000009 /* Address of LIBLIST section */ -+#define DT_MIPS_LOCAL_GOTNO 0x7000000a /* Number of local GOT entries */ -+#define DT_MIPS_CONFLICTNO 0x7000000b /* Number of CONFLICT entries */ -+#define DT_MIPS_LIBLISTNO 0x70000010 /* Number of LIBLIST entries */ -+#define DT_MIPS_SYMTABNO 0x70000011 /* Number of DYNSYM entries */ -+#define DT_MIPS_UNREFEXTNO 0x70000012 /* First external DYNSYM */ -+#define DT_MIPS_GOTSYM 0x70000013 /* First GOT entry in DYNSYM */ -+#define DT_MIPS_HIPAGENO 0x70000014 /* Number of GOT page table entries */ -+#define DT_MIPS_RLD_MAP 0x70000016 /* Address of run time loader map. */ -+#define DT_MIPS_DELTA_CLASS 0x70000017 /* Delta C++ class definition. */ -+#define DT_MIPS_DELTA_CLASS_NO 0x70000018 /* Number of entries in -+ DT_MIPS_DELTA_CLASS. */ -+#define DT_MIPS_DELTA_INSTANCE 0x70000019 /* Delta C++ class instances. */ -+#define DT_MIPS_DELTA_INSTANCE_NO 0x7000001a /* Number of entries in -+ DT_MIPS_DELTA_INSTANCE. */ -+#define DT_MIPS_DELTA_RELOC 0x7000001b /* Delta relocations. */ -+#define DT_MIPS_DELTA_RELOC_NO 0x7000001c /* Number of entries in -+ DT_MIPS_DELTA_RELOC. */ -+#define DT_MIPS_DELTA_SYM 0x7000001d /* Delta symbols that Delta -+ relocations refer to. */ -+#define DT_MIPS_DELTA_SYM_NO 0x7000001e /* Number of entries in -+ DT_MIPS_DELTA_SYM. */ -+#define DT_MIPS_DELTA_CLASSSYM 0x70000020 /* Delta symbols that hold the -+ class declaration. */ -+#define DT_MIPS_DELTA_CLASSSYM_NO 0x70000021 /* Number of entries in -+ DT_MIPS_DELTA_CLASSSYM. */ -+#define DT_MIPS_CXX_FLAGS 0x70000022 /* Flags indicating for C++ flavor. */ -+#define DT_MIPS_PIXIE_INIT 0x70000023 -+#define DT_MIPS_SYMBOL_LIB 0x70000024 -+#define DT_MIPS_LOCALPAGE_GOTIDX 0x70000025 -+#define DT_MIPS_LOCAL_GOTIDX 0x70000026 -+#define DT_MIPS_HIDDEN_GOTIDX 0x70000027 -+#define DT_MIPS_PROTECTED_GOTIDX 0x70000028 -+#define DT_MIPS_OPTIONS 0x70000029 /* Address of .options. */ -+#define DT_MIPS_INTERFACE 0x7000002a /* Address of .interface. */ -+#define DT_MIPS_DYNSTR_ALIGN 0x7000002b -+#define DT_MIPS_INTERFACE_SIZE 0x7000002c /* Size of the .interface section. */ -+#define DT_MIPS_RLD_TEXT_RESOLVE_ADDR 0x7000002d /* Address of rld_text_rsolve -+ function stored in GOT. */ -+#define DT_MIPS_PERF_SUFFIX 0x7000002e /* Default suffix of dso to be added -+ by rld on dlopen() calls. */ -+#define DT_MIPS_COMPACT_SIZE 0x7000002f /* (O32)Size of compact rel section. */ -+#define DT_MIPS_GP_VALUE 0x70000030 /* GP value for aux GOTs. */ -+#define DT_MIPS_AUX_DYNAMIC 0x70000031 /* Address of aux .dynamic. */ -+#define DT_MIPS_NUM 0x32 -+ -+/* Legal values for DT_MIPS_FLAGS Elf32_Dyn entry. */ -+ -+#define RHF_NONE 0 /* No flags */ -+#define RHF_QUICKSTART (1 << 0) /* Use quickstart */ -+#define RHF_NOTPOT (1 << 1) /* Hash size not power of 2 */ -+#define RHF_NO_LIBRARY_REPLACEMENT (1 << 2) /* Ignore LD_LIBRARY_PATH */ -+#define RHF_NO_MOVE (1 << 3) -+#define RHF_SGI_ONLY (1 << 4) -+#define RHF_GUARANTEE_INIT (1 << 5) -+#define RHF_DELTA_C_PLUS_PLUS (1 << 6) -+#define RHF_GUARANTEE_START_INIT (1 << 7) -+#define RHF_PIXIE (1 << 8) -+#define RHF_DEFAULT_DELAY_LOAD (1 << 9) -+#define RHF_REQUICKSTART (1 << 10) -+#define RHF_REQUICKSTARTED (1 << 11) -+#define RHF_CORD (1 << 12) -+#define RHF_NO_UNRES_UNDEF (1 << 13) -+#define RHF_RLD_ORDER_SAFE (1 << 14) -+ -+/* Entries found in sections of type SHT_MIPS_LIBLIST. */ -+ -+typedef struct -+{ -+ Elf32_Word l_name; /* Name (string table index) */ -+ Elf32_Word l_time_stamp; /* Timestamp */ -+ Elf32_Word l_checksum; /* Checksum */ -+ Elf32_Word l_version; /* Interface version */ -+ Elf32_Word l_flags; /* Flags */ -+} Elf32_Lib; -+ -+typedef struct -+{ -+ Elf64_Word l_name; /* Name (string table index) */ -+ Elf64_Word l_time_stamp; /* Timestamp */ -+ Elf64_Word l_checksum; /* Checksum */ -+ Elf64_Word l_version; /* Interface version */ -+ Elf64_Word l_flags; /* Flags */ -+} Elf64_Lib; -+ -+ -+/* Legal values for l_flags. */ -+ -+#define LL_NONE 0 -+#define LL_EXACT_MATCH (1 << 0) /* Require exact match */ -+#define LL_IGNORE_INT_VER (1 << 1) /* Ignore interface version */ -+#define LL_REQUIRE_MINOR (1 << 2) -+#define LL_EXPORTS (1 << 3) -+#define LL_DELAY_LOAD (1 << 4) -+#define LL_DELTA (1 << 5) -+ -+/* Entries found in sections of type SHT_MIPS_CONFLICT. */ -+ -+typedef Elf32_Addr Elf32_Conflict; -+ -+ -+/* HPPA specific definitions. */ -+ -+/* Legal values for e_flags field of Elf32_Ehdr. */ -+ -+#define EF_PARISC_TRAPNIL 0x00010000 /* Trap nil pointer dereference. */ -+#define EF_PARISC_EXT 0x00020000 /* Program uses arch. extensions. */ -+#define EF_PARISC_LSB 0x00040000 /* Program expects little endian. */ -+#define EF_PARISC_WIDE 0x00080000 /* Program expects wide mode. */ -+#define EF_PARISC_NO_KABP 0x00100000 /* No kernel assisted branch -+ prediction. */ -+#define EF_PARISC_LAZYSWAP 0x00400000 /* Allow lazy swapping. */ -+#define EF_PARISC_ARCH 0x0000ffff /* Architecture version. */ -+ -+/* Defined values for `e_flags & EF_PARISC_ARCH' are: */ -+ -+#define EFA_PARISC_1_0 0x020b /* PA-RISC 1.0 big-endian. */ -+#define EFA_PARISC_1_1 0x0210 /* PA-RISC 1.1 big-endian. */ -+#define EFA_PARISC_2_0 0x0214 /* PA-RISC 2.0 big-endian. */ -+ -+/* Additional section indeces. */ -+ -+#define SHN_PARISC_ANSI_COMMON 0xff00 /* Section for tenatively declared -+ symbols in ANSI C. */ -+#define SHN_PARISC_HUGE_COMMON 0xff01 /* Common blocks in huge model. */ -+ -+/* Legal values for sh_type field of Elf32_Shdr. */ -+ -+#define SHT_PARISC_EXT 0x70000000 /* Contains product specific ext. */ -+#define SHT_PARISC_UNWIND 0x70000001 /* Unwind information. */ -+#define SHT_PARISC_DOC 0x70000002 /* Debug info for optimized code. */ -+ -+/* Legal values for sh_flags field of Elf32_Shdr. */ -+ -+#define SHF_PARISC_SHORT 0x20000000 /* Section with short addressing. */ -+#define SHF_PARISC_HUGE 0x40000000 /* Section far from gp. */ -+#define SHF_PARISC_SBP 0x80000000 /* Static branch prediction code. */ -+ -+/* Legal values for ST_TYPE subfield of st_info (symbol type). */ -+ -+#define STT_PARISC_MILLICODE 13 /* Millicode function entry point. */ -+ -+#define STT_HP_OPAQUE (STT_LOOS + 0x1) -+#define STT_HP_STUB (STT_LOOS + 0x2) -+ -+/* HPPA relocs. */ -+ -+#define R_PARISC_NONE 0 /* No reloc. */ -+#define R_PARISC_DIR32 1 /* Direct 32-bit reference. */ -+#define R_PARISC_DIR21L 2 /* Left 21 bits of eff. address. */ -+#define R_PARISC_DIR17R 3 /* Right 17 bits of eff. address. */ -+#define R_PARISC_DIR17F 4 /* 17 bits of eff. address. */ -+#define R_PARISC_DIR14R 6 /* Right 14 bits of eff. address. */ -+#define R_PARISC_PCREL32 9 /* 32-bit rel. address. */ -+#define R_PARISC_PCREL21L 10 /* Left 21 bits of rel. address. */ -+#define R_PARISC_PCREL17R 11 /* Right 17 bits of rel. address. */ -+#define R_PARISC_PCREL17F 12 /* 17 bits of rel. address. */ -+#define R_PARISC_PCREL14R 14 /* Right 14 bits of rel. address. */ -+#define R_PARISC_DPREL21L 18 /* Left 21 bits of rel. address. */ -+#define R_PARISC_DPREL14R 22 /* Right 14 bits of rel. address. */ -+#define R_PARISC_GPREL21L 26 /* GP-relative, left 21 bits. */ -+#define R_PARISC_GPREL14R 30 /* GP-relative, right 14 bits. */ -+#define R_PARISC_LTOFF21L 34 /* LT-relative, left 21 bits. */ -+#define R_PARISC_LTOFF14R 38 /* LT-relative, right 14 bits. */ -+#define R_PARISC_SECREL32 41 /* 32 bits section rel. address. */ -+#define R_PARISC_SEGBASE 48 /* No relocation, set segment base. */ -+#define R_PARISC_SEGREL32 49 /* 32 bits segment rel. address. */ -+#define R_PARISC_PLTOFF21L 50 /* PLT rel. address, left 21 bits. */ -+#define R_PARISC_PLTOFF14R 54 /* PLT rel. address, right 14 bits. */ -+#define R_PARISC_LTOFF_FPTR32 57 /* 32 bits LT-rel. function pointer. */ -+#define R_PARISC_LTOFF_FPTR21L 58 /* LT-rel. fct ptr, left 21 bits. */ -+#define R_PARISC_LTOFF_FPTR14R 62 /* LT-rel. fct ptr, right 14 bits. */ -+#define R_PARISC_FPTR64 64 /* 64 bits function address. */ -+#define R_PARISC_PLABEL32 65 /* 32 bits function address. */ -+#define R_PARISC_PCREL64 72 /* 64 bits PC-rel. address. */ -+#define R_PARISC_PCREL22F 74 /* 22 bits PC-rel. address. */ -+#define R_PARISC_PCREL14WR 75 /* PC-rel. address, right 14 bits. */ -+#define R_PARISC_PCREL14DR 76 /* PC rel. address, right 14 bits. */ -+#define R_PARISC_PCREL16F 77 /* 16 bits PC-rel. address. */ -+#define R_PARISC_PCREL16WF 78 /* 16 bits PC-rel. address. */ -+#define R_PARISC_PCREL16DF 79 /* 16 bits PC-rel. address. */ -+#define R_PARISC_DIR64 80 /* 64 bits of eff. address. */ -+#define R_PARISC_DIR14WR 83 /* 14 bits of eff. address. */ -+#define R_PARISC_DIR14DR 84 /* 14 bits of eff. address. */ -+#define R_PARISC_DIR16F 85 /* 16 bits of eff. address. */ -+#define R_PARISC_DIR16WF 86 /* 16 bits of eff. address. */ -+#define R_PARISC_DIR16DF 87 /* 16 bits of eff. address. */ -+#define R_PARISC_GPREL64 88 /* 64 bits of GP-rel. address. */ -+#define R_PARISC_GPREL14WR 91 /* GP-rel. address, right 14 bits. */ -+#define R_PARISC_GPREL14DR 92 /* GP-rel. address, right 14 bits. */ -+#define R_PARISC_GPREL16F 93 /* 16 bits GP-rel. address. */ -+#define R_PARISC_GPREL16WF 94 /* 16 bits GP-rel. address. */ -+#define R_PARISC_GPREL16DF 95 /* 16 bits GP-rel. address. */ -+#define R_PARISC_LTOFF64 96 /* 64 bits LT-rel. address. */ -+#define R_PARISC_LTOFF14WR 99 /* LT-rel. address, right 14 bits. */ -+#define R_PARISC_LTOFF14DR 100 /* LT-rel. address, right 14 bits. */ -+#define R_PARISC_LTOFF16F 101 /* 16 bits LT-rel. address. */ -+#define R_PARISC_LTOFF16WF 102 /* 16 bits LT-rel. address. */ -+#define R_PARISC_LTOFF16DF 103 /* 16 bits LT-rel. address. */ -+#define R_PARISC_SECREL64 104 /* 64 bits section rel. address. */ -+#define R_PARISC_SEGREL64 112 /* 64 bits segment rel. address. */ -+#define R_PARISC_PLTOFF14WR 115 /* PLT-rel. address, right 14 bits. */ -+#define R_PARISC_PLTOFF14DR 116 /* PLT-rel. address, right 14 bits. */ -+#define R_PARISC_PLTOFF16F 117 /* 16 bits LT-rel. address. */ -+#define R_PARISC_PLTOFF16WF 118 /* 16 bits PLT-rel. address. */ -+#define R_PARISC_PLTOFF16DF 119 /* 16 bits PLT-rel. address. */ -+#define R_PARISC_LTOFF_FPTR64 120 /* 64 bits LT-rel. function ptr. */ -+#define R_PARISC_LTOFF_FPTR14WR 123 /* LT-rel. fct. ptr., right 14 bits. */ -+#define R_PARISC_LTOFF_FPTR14DR 124 /* LT-rel. fct. ptr., right 14 bits. */ -+#define R_PARISC_LTOFF_FPTR16F 125 /* 16 bits LT-rel. function ptr. */ -+#define R_PARISC_LTOFF_FPTR16WF 126 /* 16 bits LT-rel. function ptr. */ -+#define R_PARISC_LTOFF_FPTR16DF 127 /* 16 bits LT-rel. function ptr. */ -+#define R_PARISC_LORESERVE 128 -+#define R_PARISC_COPY 128 /* Copy relocation. */ -+#define R_PARISC_IPLT 129 /* Dynamic reloc, imported PLT */ -+#define R_PARISC_EPLT 130 /* Dynamic reloc, exported PLT */ -+#define R_PARISC_TPREL32 153 /* 32 bits TP-rel. address. */ -+#define R_PARISC_TPREL21L 154 /* TP-rel. address, left 21 bits. */ -+#define R_PARISC_TPREL14R 158 /* TP-rel. address, right 14 bits. */ -+#define R_PARISC_LTOFF_TP21L 162 /* LT-TP-rel. address, left 21 bits. */ -+#define R_PARISC_LTOFF_TP14R 166 /* LT-TP-rel. address, right 14 bits.*/ -+#define R_PARISC_LTOFF_TP14F 167 /* 14 bits LT-TP-rel. address. */ -+#define R_PARISC_TPREL64 216 /* 64 bits TP-rel. address. */ -+#define R_PARISC_TPREL14WR 219 /* TP-rel. address, right 14 bits. */ -+#define R_PARISC_TPREL14DR 220 /* TP-rel. address, right 14 bits. */ -+#define R_PARISC_TPREL16F 221 /* 16 bits TP-rel. address. */ -+#define R_PARISC_TPREL16WF 222 /* 16 bits TP-rel. address. */ -+#define R_PARISC_TPREL16DF 223 /* 16 bits TP-rel. address. */ -+#define R_PARISC_LTOFF_TP64 224 /* 64 bits LT-TP-rel. address. */ -+#define R_PARISC_LTOFF_TP14WR 227 /* LT-TP-rel. address, right 14 bits.*/ -+#define R_PARISC_LTOFF_TP14DR 228 /* LT-TP-rel. address, right 14 bits.*/ -+#define R_PARISC_LTOFF_TP16F 229 /* 16 bits LT-TP-rel. address. */ -+#define R_PARISC_LTOFF_TP16WF 230 /* 16 bits LT-TP-rel. address. */ -+#define R_PARISC_LTOFF_TP16DF 231 /* 16 bits LT-TP-rel. address. */ -+#define R_PARISC_HIRESERVE 255 -+ -+/* Legal values for p_type field of Elf32_Phdr/Elf64_Phdr. */ -+ -+#define PT_HP_TLS (PT_LOOS + 0x0) -+#define PT_HP_CORE_NONE (PT_LOOS + 0x1) -+#define PT_HP_CORE_VERSION (PT_LOOS + 0x2) -+#define PT_HP_CORE_KERNEL (PT_LOOS + 0x3) -+#define PT_HP_CORE_COMM (PT_LOOS + 0x4) -+#define PT_HP_CORE_PROC (PT_LOOS + 0x5) -+#define PT_HP_CORE_LOADABLE (PT_LOOS + 0x6) -+#define PT_HP_CORE_STACK (PT_LOOS + 0x7) -+#define PT_HP_CORE_SHM (PT_LOOS + 0x8) -+#define PT_HP_CORE_MMF (PT_LOOS + 0x9) -+#define PT_HP_PARALLEL (PT_LOOS + 0x10) -+#define PT_HP_FASTBIND (PT_LOOS + 0x11) -+#define PT_HP_OPT_ANNOT (PT_LOOS + 0x12) -+#define PT_HP_HSL_ANNOT (PT_LOOS + 0x13) -+#define PT_HP_STACK (PT_LOOS + 0x14) -+ -+#define PT_PARISC_ARCHEXT 0x70000000 -+#define PT_PARISC_UNWIND 0x70000001 -+ -+/* Legal values for p_flags field of Elf32_Phdr/Elf64_Phdr. */ -+ -+#define PF_PARISC_SBP 0x08000000 -+ -+#define PF_HP_PAGE_SIZE 0x00100000 -+#define PF_HP_FAR_SHARED 0x00200000 -+#define PF_HP_NEAR_SHARED 0x00400000 -+#define PF_HP_CODE 0x01000000 -+#define PF_HP_MODIFY 0x02000000 -+#define PF_HP_LAZYSWAP 0x04000000 -+#define PF_HP_SBP 0x08000000 -+ -+ -+/* Alpha specific definitions. */ -+ -+/* Legal values for e_flags field of Elf64_Ehdr. */ -+ -+#define EF_ALPHA_32BIT 1 /* All addresses must be < 2GB. */ -+#define EF_ALPHA_CANRELAX 2 /* Relocations for relaxing exist. */ -+ -+/* Legal values for sh_type field of Elf64_Shdr. */ -+ -+/* These two are primerily concerned with ECOFF debugging info. */ -+#define SHT_ALPHA_DEBUG 0x70000001 -+#define SHT_ALPHA_REGINFO 0x70000002 -+ -+/* Legal values for sh_flags field of Elf64_Shdr. */ -+ -+#define SHF_ALPHA_GPREL 0x10000000 -+ -+/* Legal values for st_other field of Elf64_Sym. */ -+#define STO_ALPHA_NOPV 0x80 /* No PV required. */ -+#define STO_ALPHA_STD_GPLOAD 0x88 /* PV only used for initial ldgp. */ -+ -+/* Alpha relocs. */ -+ -+#define R_ALPHA_NONE 0 /* No reloc */ -+#define R_ALPHA_REFLONG 1 /* Direct 32 bit */ -+#define R_ALPHA_REFQUAD 2 /* Direct 64 bit */ -+#define R_ALPHA_GPREL32 3 /* GP relative 32 bit */ -+#define R_ALPHA_LITERAL 4 /* GP relative 16 bit w/optimization */ -+#define R_ALPHA_LITUSE 5 /* Optimization hint for LITERAL */ -+#define R_ALPHA_GPDISP 6 /* Add displacement to GP */ -+#define R_ALPHA_BRADDR 7 /* PC+4 relative 23 bit shifted */ -+#define R_ALPHA_HINT 8 /* PC+4 relative 16 bit shifted */ -+#define R_ALPHA_SREL16 9 /* PC relative 16 bit */ -+#define R_ALPHA_SREL32 10 /* PC relative 32 bit */ -+#define R_ALPHA_SREL64 11 /* PC relative 64 bit */ -+#define R_ALPHA_GPRELHIGH 17 /* GP relative 32 bit, high 16 bits */ -+#define R_ALPHA_GPRELLOW 18 /* GP relative 32 bit, low 16 bits */ -+#define R_ALPHA_GPREL16 19 /* GP relative 16 bit */ -+#define R_ALPHA_COPY 24 /* Copy symbol at runtime */ -+#define R_ALPHA_GLOB_DAT 25 /* Create GOT entry */ -+#define R_ALPHA_JMP_SLOT 26 /* Create PLT entry */ -+#define R_ALPHA_RELATIVE 27 /* Adjust by program base */ -+#define R_ALPHA_TLS_GD_HI 28 -+#define R_ALPHA_TLSGD 29 -+#define R_ALPHA_TLS_LDM 30 -+#define R_ALPHA_DTPMOD64 31 -+#define R_ALPHA_GOTDTPREL 32 -+#define R_ALPHA_DTPREL64 33 -+#define R_ALPHA_DTPRELHI 34 -+#define R_ALPHA_DTPRELLO 35 -+#define R_ALPHA_DTPREL16 36 -+#define R_ALPHA_GOTTPREL 37 -+#define R_ALPHA_TPREL64 38 -+#define R_ALPHA_TPRELHI 39 -+#define R_ALPHA_TPRELLO 40 -+#define R_ALPHA_TPREL16 41 -+/* Keep this the last entry. */ -+#define R_ALPHA_NUM 46 -+ -+/* Magic values of the LITUSE relocation addend. */ -+#define LITUSE_ALPHA_ADDR 0 -+#define LITUSE_ALPHA_BASE 1 -+#define LITUSE_ALPHA_BYTOFF 2 -+#define LITUSE_ALPHA_JSR 3 -+#define LITUSE_ALPHA_TLS_GD 4 -+#define LITUSE_ALPHA_TLS_LDM 5 -+ -+ -+/* PowerPC specific declarations */ -+ -+/* Values for Elf32/64_Ehdr.e_flags. */ -+#define EF_PPC_EMB 0x80000000 /* PowerPC embedded flag */ -+ -+/* Cygnus local bits below */ -+#define EF_PPC_RELOCATABLE 0x00010000 /* PowerPC -mrelocatable flag*/ -+#define EF_PPC_RELOCATABLE_LIB 0x00008000 /* PowerPC -mrelocatable-lib -+ flag */ -+ -+/* PowerPC relocations defined by the ABIs */ -+#define R_PPC_NONE 0 -+#define R_PPC_ADDR32 1 /* 32bit absolute address */ -+#define R_PPC_ADDR24 2 /* 26bit address, 2 bits ignored. */ -+#define R_PPC_ADDR16 3 /* 16bit absolute address */ -+#define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */ -+#define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */ -+#define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */ -+#define R_PPC_ADDR14 7 /* 16bit address, 2 bits ignored */ -+#define R_PPC_ADDR14_BRTAKEN 8 -+#define R_PPC_ADDR14_BRNTAKEN 9 -+#define R_PPC_REL24 10 /* PC relative 26 bit */ -+#define R_PPC_REL14 11 /* PC relative 16 bit */ -+#define R_PPC_REL14_BRTAKEN 12 -+#define R_PPC_REL14_BRNTAKEN 13 -+#define R_PPC_GOT16 14 -+#define R_PPC_GOT16_LO 15 -+#define R_PPC_GOT16_HI 16 -+#define R_PPC_GOT16_HA 17 -+#define R_PPC_PLTREL24 18 -+#define R_PPC_COPY 19 -+#define R_PPC_GLOB_DAT 20 -+#define R_PPC_JMP_SLOT 21 -+#define R_PPC_RELATIVE 22 -+#define R_PPC_LOCAL24PC 23 -+#define R_PPC_UADDR32 24 -+#define R_PPC_UADDR16 25 -+#define R_PPC_REL32 26 -+#define R_PPC_PLT32 27 -+#define R_PPC_PLTREL32 28 -+#define R_PPC_PLT16_LO 29 -+#define R_PPC_PLT16_HI 30 -+#define R_PPC_PLT16_HA 31 -+#define R_PPC_SDAREL16 32 -+#define R_PPC_SECTOFF 33 -+#define R_PPC_SECTOFF_LO 34 -+#define R_PPC_SECTOFF_HI 35 -+#define R_PPC_SECTOFF_HA 36 -+ -+/* PowerPC relocations defined for the TLS access ABI. */ -+#define R_PPC_TLS 67 /* none (sym+add)@tls */ -+#define R_PPC_DTPMOD32 68 /* word32 (sym+add)@dtpmod */ -+#define R_PPC_TPREL16 69 /* half16* (sym+add)@tprel */ -+#define R_PPC_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */ -+#define R_PPC_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */ -+#define R_PPC_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */ -+#define R_PPC_TPREL32 73 /* word32 (sym+add)@tprel */ -+#define R_PPC_DTPREL16 74 /* half16* (sym+add)@dtprel */ -+#define R_PPC_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */ -+#define R_PPC_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */ -+#define R_PPC_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */ -+#define R_PPC_DTPREL32 78 /* word32 (sym+add)@dtprel */ -+#define R_PPC_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */ -+#define R_PPC_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */ -+#define R_PPC_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */ -+#define R_PPC_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */ -+#define R_PPC_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */ -+#define R_PPC_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */ -+#define R_PPC_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */ -+#define R_PPC_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */ -+#define R_PPC_GOT_TPREL16 87 /* half16* (sym+add)@got@tprel */ -+#define R_PPC_GOT_TPREL16_LO 88 /* half16 (sym+add)@got@tprel@l */ -+#define R_PPC_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */ -+#define R_PPC_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */ -+#define R_PPC_GOT_DTPREL16 91 /* half16* (sym+add)@got@dtprel */ -+#define R_PPC_GOT_DTPREL16_LO 92 /* half16* (sym+add)@got@dtprel@l */ -+#define R_PPC_GOT_DTPREL16_HI 93 /* half16* (sym+add)@got@dtprel@h */ -+#define R_PPC_GOT_DTPREL16_HA 94 /* half16* (sym+add)@got@dtprel@ha */ -+ -+/* Keep this the last entry. */ -+#define R_PPC_NUM 95 -+ -+/* The remaining relocs are from the Embedded ELF ABI, and are not -+ in the SVR4 ELF ABI. */ -+#define R_PPC_EMB_NADDR32 101 -+#define R_PPC_EMB_NADDR16 102 -+#define R_PPC_EMB_NADDR16_LO 103 -+#define R_PPC_EMB_NADDR16_HI 104 -+#define R_PPC_EMB_NADDR16_HA 105 -+#define R_PPC_EMB_SDAI16 106 -+#define R_PPC_EMB_SDA2I16 107 -+#define R_PPC_EMB_SDA2REL 108 -+#define R_PPC_EMB_SDA21 109 /* 16 bit offset in SDA */ -+#define R_PPC_EMB_MRKREF 110 -+#define R_PPC_EMB_RELSEC16 111 -+#define R_PPC_EMB_RELST_LO 112 -+#define R_PPC_EMB_RELST_HI 113 -+#define R_PPC_EMB_RELST_HA 114 -+#define R_PPC_EMB_BIT_FLD 115 -+#define R_PPC_EMB_RELSDA 116 /* 16 bit relative offset in SDA */ -+ -+/* Diab tool relocations. */ -+#define R_PPC_DIAB_SDA21_LO 180 /* like EMB_SDA21, but lower 16 bit */ -+#define R_PPC_DIAB_SDA21_HI 181 /* like EMB_SDA21, but high 16 bit */ -+#define R_PPC_DIAB_SDA21_HA 182 /* like EMB_SDA21, adjusted high 16 */ -+#define R_PPC_DIAB_RELSDA_LO 183 /* like EMB_RELSDA, but lower 16 bit */ -+#define R_PPC_DIAB_RELSDA_HI 184 /* like EMB_RELSDA, but high 16 bit */ -+#define R_PPC_DIAB_RELSDA_HA 185 /* like EMB_RELSDA, adjusted high 16 */ -+ -+/* This is a phony reloc to handle any old fashioned TOC16 references -+ that may still be in object files. */ -+#define R_PPC_TOC16 255 -+ -+ -+/* PowerPC64 relocations defined by the ABIs */ -+#define R_PPC64_NONE R_PPC_NONE -+#define R_PPC64_ADDR32 R_PPC_ADDR32 /* 32bit absolute address */ -+#define R_PPC64_ADDR24 R_PPC_ADDR24 /* 26bit address, word aligned */ -+#define R_PPC64_ADDR16 R_PPC_ADDR16 /* 16bit absolute address */ -+#define R_PPC64_ADDR16_LO R_PPC_ADDR16_LO /* lower 16bits of address */ -+#define R_PPC64_ADDR16_HI R_PPC_ADDR16_HI /* high 16bits of address. */ -+#define R_PPC64_ADDR16_HA R_PPC_ADDR16_HA /* adjusted high 16bits. */ -+#define R_PPC64_ADDR14 R_PPC_ADDR14 /* 16bit address, word aligned */ -+#define R_PPC64_ADDR14_BRTAKEN R_PPC_ADDR14_BRTAKEN -+#define R_PPC64_ADDR14_BRNTAKEN R_PPC_ADDR14_BRNTAKEN -+#define R_PPC64_REL24 R_PPC_REL24 /* PC-rel. 26 bit, word aligned */ -+#define R_PPC64_REL14 R_PPC_REL14 /* PC relative 16 bit */ -+#define R_PPC64_REL14_BRTAKEN R_PPC_REL14_BRTAKEN -+#define R_PPC64_REL14_BRNTAKEN R_PPC_REL14_BRNTAKEN -+#define R_PPC64_GOT16 R_PPC_GOT16 -+#define R_PPC64_GOT16_LO R_PPC_GOT16_LO -+#define R_PPC64_GOT16_HI R_PPC_GOT16_HI -+#define R_PPC64_GOT16_HA R_PPC_GOT16_HA -+ -+#define R_PPC64_COPY R_PPC_COPY -+#define R_PPC64_GLOB_DAT R_PPC_GLOB_DAT -+#define R_PPC64_JMP_SLOT R_PPC_JMP_SLOT -+#define R_PPC64_RELATIVE R_PPC_RELATIVE -+ -+#define R_PPC64_UADDR32 R_PPC_UADDR32 -+#define R_PPC64_UADDR16 R_PPC_UADDR16 -+#define R_PPC64_REL32 R_PPC_REL32 -+#define R_PPC64_PLT32 R_PPC_PLT32 -+#define R_PPC64_PLTREL32 R_PPC_PLTREL32 -+#define R_PPC64_PLT16_LO R_PPC_PLT16_LO -+#define R_PPC64_PLT16_HI R_PPC_PLT16_HI -+#define R_PPC64_PLT16_HA R_PPC_PLT16_HA -+ -+#define R_PPC64_SECTOFF R_PPC_SECTOFF -+#define R_PPC64_SECTOFF_LO R_PPC_SECTOFF_LO -+#define R_PPC64_SECTOFF_HI R_PPC_SECTOFF_HI -+#define R_PPC64_SECTOFF_HA R_PPC_SECTOFF_HA -+#define R_PPC64_ADDR30 37 /* word30 (S + A - P) >> 2 */ -+#define R_PPC64_ADDR64 38 /* doubleword64 S + A */ -+#define R_PPC64_ADDR16_HIGHER 39 /* half16 #higher(S + A) */ -+#define R_PPC64_ADDR16_HIGHERA 40 /* half16 #highera(S + A) */ -+#define R_PPC64_ADDR16_HIGHEST 41 /* half16 #highest(S + A) */ -+#define R_PPC64_ADDR16_HIGHESTA 42 /* half16 #highesta(S + A) */ -+#define R_PPC64_UADDR64 43 /* doubleword64 S + A */ -+#define R_PPC64_REL64 44 /* doubleword64 S + A - P */ -+#define R_PPC64_PLT64 45 /* doubleword64 L + A */ -+#define R_PPC64_PLTREL64 46 /* doubleword64 L + A - P */ -+#define R_PPC64_TOC16 47 /* half16* S + A - .TOC */ -+#define R_PPC64_TOC16_LO 48 /* half16 #lo(S + A - .TOC.) */ -+#define R_PPC64_TOC16_HI 49 /* half16 #hi(S + A - .TOC.) */ -+#define R_PPC64_TOC16_HA 50 /* half16 #ha(S + A - .TOC.) */ -+#define R_PPC64_TOC 51 /* doubleword64 .TOC */ -+#define R_PPC64_PLTGOT16 52 /* half16* M + A */ -+#define R_PPC64_PLTGOT16_LO 53 /* half16 #lo(M + A) */ -+#define R_PPC64_PLTGOT16_HI 54 /* half16 #hi(M + A) */ -+#define R_PPC64_PLTGOT16_HA 55 /* half16 #ha(M + A) */ -+ -+#define R_PPC64_ADDR16_DS 56 /* half16ds* (S + A) >> 2 */ -+#define R_PPC64_ADDR16_LO_DS 57 /* half16ds #lo(S + A) >> 2 */ -+#define R_PPC64_GOT16_DS 58 /* half16ds* (G + A) >> 2 */ -+#define R_PPC64_GOT16_LO_DS 59 /* half16ds #lo(G + A) >> 2 */ -+#define R_PPC64_PLT16_LO_DS 60 /* half16ds #lo(L + A) >> 2 */ -+#define R_PPC64_SECTOFF_DS 61 /* half16ds* (R + A) >> 2 */ -+#define R_PPC64_SECTOFF_LO_DS 62 /* half16ds #lo(R + A) >> 2 */ -+#define R_PPC64_TOC16_DS 63 /* half16ds* (S + A - .TOC.) >> 2 */ -+#define R_PPC64_TOC16_LO_DS 64 /* half16ds #lo(S + A - .TOC.) >> 2 */ -+#define R_PPC64_PLTGOT16_DS 65 /* half16ds* (M + A) >> 2 */ -+#define R_PPC64_PLTGOT16_LO_DS 66 /* half16ds #lo(M + A) >> 2 */ -+ -+/* PowerPC64 relocations defined for the TLS access ABI. */ -+#define R_PPC64_TLS 67 /* none (sym+add)@tls */ -+#define R_PPC64_DTPMOD64 68 /* doubleword64 (sym+add)@dtpmod */ -+#define R_PPC64_TPREL16 69 /* half16* (sym+add)@tprel */ -+#define R_PPC64_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */ -+#define R_PPC64_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */ -+#define R_PPC64_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */ -+#define R_PPC64_TPREL64 73 /* doubleword64 (sym+add)@tprel */ -+#define R_PPC64_DTPREL16 74 /* half16* (sym+add)@dtprel */ -+#define R_PPC64_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */ -+#define R_PPC64_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */ -+#define R_PPC64_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */ -+#define R_PPC64_DTPREL64 78 /* doubleword64 (sym+add)@dtprel */ -+#define R_PPC64_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */ -+#define R_PPC64_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */ -+#define R_PPC64_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */ -+#define R_PPC64_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */ -+#define R_PPC64_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */ -+#define R_PPC64_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */ -+#define R_PPC64_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */ -+#define R_PPC64_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */ -+#define R_PPC64_GOT_TPREL16_DS 87 /* half16ds* (sym+add)@got@tprel */ -+#define R_PPC64_GOT_TPREL16_LO_DS 88 /* half16ds (sym+add)@got@tprel@l */ -+#define R_PPC64_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */ -+#define R_PPC64_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */ -+#define R_PPC64_GOT_DTPREL16_DS 91 /* half16ds* (sym+add)@got@dtprel */ -+#define R_PPC64_GOT_DTPREL16_LO_DS 92 /* half16ds (sym+add)@got@dtprel@l */ -+#define R_PPC64_GOT_DTPREL16_HI 93 /* half16 (sym+add)@got@dtprel@h */ -+#define R_PPC64_GOT_DTPREL16_HA 94 /* half16 (sym+add)@got@dtprel@ha */ -+#define R_PPC64_TPREL16_DS 95 /* half16ds* (sym+add)@tprel */ -+#define R_PPC64_TPREL16_LO_DS 96 /* half16ds (sym+add)@tprel@l */ -+#define R_PPC64_TPREL16_HIGHER 97 /* half16 (sym+add)@tprel@higher */ -+#define R_PPC64_TPREL16_HIGHERA 98 /* half16 (sym+add)@tprel@highera */ -+#define R_PPC64_TPREL16_HIGHEST 99 /* half16 (sym+add)@tprel@highest */ -+#define R_PPC64_TPREL16_HIGHESTA 100 /* half16 (sym+add)@tprel@highesta */ -+#define R_PPC64_DTPREL16_DS 101 /* half16ds* (sym+add)@dtprel */ -+#define R_PPC64_DTPREL16_LO_DS 102 /* half16ds (sym+add)@dtprel@l */ -+#define R_PPC64_DTPREL16_HIGHER 103 /* half16 (sym+add)@dtprel@higher */ -+#define R_PPC64_DTPREL16_HIGHERA 104 /* half16 (sym+add)@dtprel@highera */ -+#define R_PPC64_DTPREL16_HIGHEST 105 /* half16 (sym+add)@dtprel@highest */ -+#define R_PPC64_DTPREL16_HIGHESTA 106 /* half16 (sym+add)@dtprel@highesta */ -+ -+/* Keep this the last entry. */ -+#define R_PPC64_NUM 107 -+ -+/* PowerPC64 specific values for the Dyn d_tag field. */ -+#define DT_PPC64_GLINK (DT_LOPROC + 0) -+#define DT_PPC64_NUM 1 -+ -+ -+/* ARM specific declarations */ -+ -+/* Processor specific flags for the ELF header e_flags field. */ -+#define EF_ARM_RELEXEC 0x01 -+#define EF_ARM_HASENTRY 0x02 -+#define EF_ARM_INTERWORK 0x04 -+#define EF_ARM_APCS_26 0x08 -+#define EF_ARM_APCS_FLOAT 0x10 -+#define EF_ARM_PIC 0x20 -+#define EF_ARM_ALIGN8 0x40 /* 8-bit structure alignment is in use */ -+#define EF_ARM_NEW_ABI 0x80 -+#define EF_ARM_OLD_ABI 0x100 -+ -+/* Other constants defined in the ARM ELF spec. version B-01. */ -+/* NB. These conflict with values defined above. */ -+#define EF_ARM_SYMSARESORTED 0x04 -+#define EF_ARM_DYNSYMSUSESEGIDX 0x08 -+#define EF_ARM_MAPSYMSFIRST 0x10 -+#define EF_ARM_EABIMASK 0XFF000000 -+ -+#define EF_ARM_EABI_VERSION(flags) ((flags) & EF_ARM_EABIMASK) -+#define EF_ARM_EABI_UNKNOWN 0x00000000 -+#define EF_ARM_EABI_VER1 0x01000000 -+#define EF_ARM_EABI_VER2 0x02000000 -+ -+/* Additional symbol types for Thumb */ -+#define STT_ARM_TFUNC 0xd -+ -+/* ARM-specific values for sh_flags */ -+#define SHF_ARM_ENTRYSECT 0x10000000 /* Section contains an entry point */ -+#define SHF_ARM_COMDEF 0x80000000 /* Section may be multiply defined -+ in the input to a link step */ -+ -+/* ARM-specific program header flags */ -+#define PF_ARM_SB 0x10000000 /* Segment contains the location -+ addressed by the static base */ -+ -+/* ARM relocs. */ -+#define R_ARM_NONE 0 /* No reloc */ -+#define R_ARM_PC24 1 /* PC relative 26 bit branch */ -+#define R_ARM_ABS32 2 /* Direct 32 bit */ -+#define R_ARM_REL32 3 /* PC relative 32 bit */ -+#define R_ARM_PC13 4 -+#define R_ARM_ABS16 5 /* Direct 16 bit */ -+#define R_ARM_ABS12 6 /* Direct 12 bit */ -+#define R_ARM_THM_ABS5 7 -+#define R_ARM_ABS8 8 /* Direct 8 bit */ -+#define R_ARM_SBREL32 9 -+#define R_ARM_THM_PC22 10 -+#define R_ARM_THM_PC8 11 -+#define R_ARM_AMP_VCALL9 12 -+#define R_ARM_SWI24 13 -+#define R_ARM_THM_SWI8 14 -+#define R_ARM_XPC25 15 -+#define R_ARM_THM_XPC22 16 -+#define R_ARM_COPY 20 /* Copy symbol at runtime */ -+#define R_ARM_GLOB_DAT 21 /* Create GOT entry */ -+#define R_ARM_JUMP_SLOT 22 /* Create PLT entry */ -+#define R_ARM_RELATIVE 23 /* Adjust by program base */ -+#define R_ARM_GOTOFF 24 /* 32 bit offset to GOT */ -+#define R_ARM_GOTPC 25 /* 32 bit PC relative offset to GOT */ -+#define R_ARM_GOT32 26 /* 32 bit GOT entry */ -+#define R_ARM_PLT32 27 /* 32 bit PLT address */ -+#define R_ARM_ALU_PCREL_7_0 32 -+#define R_ARM_ALU_PCREL_15_8 33 -+#define R_ARM_ALU_PCREL_23_15 34 -+#define R_ARM_LDR_SBREL_11_0 35 -+#define R_ARM_ALU_SBREL_19_12 36 -+#define R_ARM_ALU_SBREL_27_20 37 -+#define R_ARM_GNU_VTENTRY 100 -+#define R_ARM_GNU_VTINHERIT 101 -+#define R_ARM_THM_PC11 102 /* thumb unconditional branch */ -+#define R_ARM_THM_PC9 103 /* thumb conditional branch */ -+#define R_ARM_RXPC25 249 -+#define R_ARM_RSBREL32 250 -+#define R_ARM_THM_RPC22 251 -+#define R_ARM_RREL32 252 -+#define R_ARM_RABS22 253 -+#define R_ARM_RPC24 254 -+#define R_ARM_RBASE 255 -+/* Keep this the last entry. */ -+#define R_ARM_NUM 256 -+ -+/* IA-64 specific declarations. */ -+ -+/* Processor specific flags for the Ehdr e_flags field. */ -+#define EF_IA_64_MASKOS 0x0000000f /* os-specific flags */ -+#define EF_IA_64_ABI64 0x00000010 /* 64-bit ABI */ -+#define EF_IA_64_ARCH 0xff000000 /* arch. version mask */ -+ -+/* Processor specific values for the Phdr p_type field. */ -+#define PT_IA_64_ARCHEXT (PT_LOPROC + 0) /* arch extension bits */ -+#define PT_IA_64_UNWIND (PT_LOPROC + 1) /* ia64 unwind bits */ -+ -+/* Processor specific flags for the Phdr p_flags field. */ -+#define PF_IA_64_NORECOV 0x80000000 /* spec insns w/o recovery */ -+ -+/* Processor specific values for the Shdr sh_type field. */ -+#define SHT_IA_64_EXT (SHT_LOPROC + 0) /* extension bits */ -+#define SHT_IA_64_UNWIND (SHT_LOPROC + 1) /* unwind bits */ -+ -+/* Processor specific flags for the Shdr sh_flags field. */ -+#define SHF_IA_64_SHORT 0x10000000 /* section near gp */ -+#define SHF_IA_64_NORECOV 0x20000000 /* spec insns w/o recovery */ -+ -+/* Processor specific values for the Dyn d_tag field. */ -+#define DT_IA_64_PLT_RESERVE (DT_LOPROC + 0) -+#define DT_IA_64_NUM 1 -+ -+/* IA-64 relocations. */ -+#define R_IA64_NONE 0x00 /* none */ -+#define R_IA64_IMM14 0x21 /* symbol + addend, add imm14 */ -+#define R_IA64_IMM22 0x22 /* symbol + addend, add imm22 */ -+#define R_IA64_IMM64 0x23 /* symbol + addend, mov imm64 */ -+#define R_IA64_DIR32MSB 0x24 /* symbol + addend, data4 MSB */ -+#define R_IA64_DIR32LSB 0x25 /* symbol + addend, data4 LSB */ -+#define R_IA64_DIR64MSB 0x26 /* symbol + addend, data8 MSB */ -+#define R_IA64_DIR64LSB 0x27 /* symbol + addend, data8 LSB */ -+#define R_IA64_GPREL22 0x2a /* @gprel(sym + add), add imm22 */ -+#define R_IA64_GPREL64I 0x2b /* @gprel(sym + add), mov imm64 */ -+#define R_IA64_GPREL32MSB 0x2c /* @gprel(sym + add), data4 MSB */ -+#define R_IA64_GPREL32LSB 0x2d /* @gprel(sym + add), data4 LSB */ -+#define R_IA64_GPREL64MSB 0x2e /* @gprel(sym + add), data8 MSB */ -+#define R_IA64_GPREL64LSB 0x2f /* @gprel(sym + add), data8 LSB */ -+#define R_IA64_LTOFF22 0x32 /* @ltoff(sym + add), add imm22 */ -+#define R_IA64_LTOFF64I 0x33 /* @ltoff(sym + add), mov imm64 */ -+#define R_IA64_PLTOFF22 0x3a /* @pltoff(sym + add), add imm22 */ -+#define R_IA64_PLTOFF64I 0x3b /* @pltoff(sym + add), mov imm64 */ -+#define R_IA64_PLTOFF64MSB 0x3e /* @pltoff(sym + add), data8 MSB */ -+#define R_IA64_PLTOFF64LSB 0x3f /* @pltoff(sym + add), data8 LSB */ -+#define R_IA64_FPTR64I 0x43 /* @fptr(sym + add), mov imm64 */ -+#define R_IA64_FPTR32MSB 0x44 /* @fptr(sym + add), data4 MSB */ -+#define R_IA64_FPTR32LSB 0x45 /* @fptr(sym + add), data4 LSB */ -+#define R_IA64_FPTR64MSB 0x46 /* @fptr(sym + add), data8 MSB */ -+#define R_IA64_FPTR64LSB 0x47 /* @fptr(sym + add), data8 LSB */ -+#define R_IA64_PCREL60B 0x48 /* @pcrel(sym + add), brl */ -+#define R_IA64_PCREL21B 0x49 /* @pcrel(sym + add), ptb, call */ -+#define R_IA64_PCREL21M 0x4a /* @pcrel(sym + add), chk.s */ -+#define R_IA64_PCREL21F 0x4b /* @pcrel(sym + add), fchkf */ -+#define R_IA64_PCREL32MSB 0x4c /* @pcrel(sym + add), data4 MSB */ -+#define R_IA64_PCREL32LSB 0x4d /* @pcrel(sym + add), data4 LSB */ -+#define R_IA64_PCREL64MSB 0x4e /* @pcrel(sym + add), data8 MSB */ -+#define R_IA64_PCREL64LSB 0x4f /* @pcrel(sym + add), data8 LSB */ -+#define R_IA64_LTOFF_FPTR22 0x52 /* @ltoff(@fptr(s+a)), imm22 */ -+#define R_IA64_LTOFF_FPTR64I 0x53 /* @ltoff(@fptr(s+a)), imm64 */ -+#define R_IA64_LTOFF_FPTR32MSB 0x54 /* @ltoff(@fptr(s+a)), data4 MSB */ -+#define R_IA64_LTOFF_FPTR32LSB 0x55 /* @ltoff(@fptr(s+a)), data4 LSB */ -+#define R_IA64_LTOFF_FPTR64MSB 0x56 /* @ltoff(@fptr(s+a)), data8 MSB */ -+#define R_IA64_LTOFF_FPTR64LSB 0x57 /* @ltoff(@fptr(s+a)), data8 LSB */ -+#define R_IA64_SEGREL32MSB 0x5c /* @segrel(sym + add), data4 MSB */ -+#define R_IA64_SEGREL32LSB 0x5d /* @segrel(sym + add), data4 LSB */ -+#define R_IA64_SEGREL64MSB 0x5e /* @segrel(sym + add), data8 MSB */ -+#define R_IA64_SEGREL64LSB 0x5f /* @segrel(sym + add), data8 LSB */ -+#define R_IA64_SECREL32MSB 0x64 /* @secrel(sym + add), data4 MSB */ -+#define R_IA64_SECREL32LSB 0x65 /* @secrel(sym + add), data4 LSB */ -+#define R_IA64_SECREL64MSB 0x66 /* @secrel(sym + add), data8 MSB */ -+#define R_IA64_SECREL64LSB 0x67 /* @secrel(sym + add), data8 LSB */ -+#define R_IA64_REL32MSB 0x6c /* data 4 + REL */ -+#define R_IA64_REL32LSB 0x6d /* data 4 + REL */ -+#define R_IA64_REL64MSB 0x6e /* data 8 + REL */ -+#define R_IA64_REL64LSB 0x6f /* data 8 + REL */ -+#define R_IA64_LTV32MSB 0x74 /* symbol + addend, data4 MSB */ -+#define R_IA64_LTV32LSB 0x75 /* symbol + addend, data4 LSB */ -+#define R_IA64_LTV64MSB 0x76 /* symbol + addend, data8 MSB */ -+#define R_IA64_LTV64LSB 0x77 /* symbol + addend, data8 LSB */ -+#define R_IA64_PCREL21BI 0x79 /* @pcrel(sym + add), 21bit inst */ -+#define R_IA64_PCREL22 0x7a /* @pcrel(sym + add), 22bit inst */ -+#define R_IA64_PCREL64I 0x7b /* @pcrel(sym + add), 64bit inst */ -+#define R_IA64_IPLTMSB 0x80 /* dynamic reloc, imported PLT, MSB */ -+#define R_IA64_IPLTLSB 0x81 /* dynamic reloc, imported PLT, LSB */ -+#define R_IA64_COPY 0x84 /* copy relocation */ -+#define R_IA64_SUB 0x85 /* Addend and symbol difference */ -+#define R_IA64_LTOFF22X 0x86 /* LTOFF22, relaxable. */ -+#define R_IA64_LDXMOV 0x87 /* Use of LTOFF22X. */ -+#define R_IA64_TPREL14 0x91 /* @tprel(sym + add), imm14 */ -+#define R_IA64_TPREL22 0x92 /* @tprel(sym + add), imm22 */ -+#define R_IA64_TPREL64I 0x93 /* @tprel(sym + add), imm64 */ -+#define R_IA64_TPREL64MSB 0x96 /* @tprel(sym + add), data8 MSB */ -+#define R_IA64_TPREL64LSB 0x97 /* @tprel(sym + add), data8 LSB */ -+#define R_IA64_LTOFF_TPREL22 0x9a /* @ltoff(@tprel(s+a)), imm2 */ -+#define R_IA64_DTPMOD64MSB 0xa6 /* @dtpmod(sym + add), data8 MSB */ -+#define R_IA64_DTPMOD64LSB 0xa7 /* @dtpmod(sym + add), data8 LSB */ -+#define R_IA64_LTOFF_DTPMOD22 0xaa /* @ltoff(@dtpmod(sym + add)), imm22 */ -+#define R_IA64_DTPREL14 0xb1 /* @dtprel(sym + add), imm14 */ -+#define R_IA64_DTPREL22 0xb2 /* @dtprel(sym + add), imm22 */ -+#define R_IA64_DTPREL64I 0xb3 /* @dtprel(sym + add), imm64 */ -+#define R_IA64_DTPREL32MSB 0xb4 /* @dtprel(sym + add), data4 MSB */ -+#define R_IA64_DTPREL32LSB 0xb5 /* @dtprel(sym + add), data4 LSB */ -+#define R_IA64_DTPREL64MSB 0xb6 /* @dtprel(sym + add), data8 MSB */ -+#define R_IA64_DTPREL64LSB 0xb7 /* @dtprel(sym + add), data8 LSB */ -+#define R_IA64_LTOFF_DTPREL22 0xba /* @ltoff(@dtprel(s+a)), imm22 */ -+ -+/* SH specific declarations */ -+ -+/* SH relocs. */ -+#define R_SH_NONE 0 -+#define R_SH_DIR32 1 -+#define R_SH_REL32 2 -+#define R_SH_DIR8WPN 3 -+#define R_SH_IND12W 4 -+#define R_SH_DIR8WPL 5 -+#define R_SH_DIR8WPZ 6 -+#define R_SH_DIR8BP 7 -+#define R_SH_DIR8W 8 -+#define R_SH_DIR8L 9 -+#define R_SH_SWITCH16 25 -+#define R_SH_SWITCH32 26 -+#define R_SH_USES 27 -+#define R_SH_COUNT 28 -+#define R_SH_ALIGN 29 -+#define R_SH_CODE 30 -+#define R_SH_DATA 31 -+#define R_SH_LABEL 32 -+#define R_SH_SWITCH8 33 -+#define R_SH_GNU_VTINHERIT 34 -+#define R_SH_GNU_VTENTRY 35 -+#define R_SH_TLS_GD_32 144 -+#define R_SH_TLS_LD_32 145 -+#define R_SH_TLS_LDO_32 146 -+#define R_SH_TLS_IE_32 147 -+#define R_SH_TLS_LE_32 148 -+#define R_SH_TLS_DTPMOD32 149 -+#define R_SH_TLS_DTPOFF32 150 -+#define R_SH_TLS_TPOFF32 151 -+#define R_SH_GOT32 160 -+#define R_SH_PLT32 161 -+#define R_SH_COPY 162 -+#define R_SH_GLOB_DAT 163 -+#define R_SH_JMP_SLOT 164 -+#define R_SH_RELATIVE 165 -+#define R_SH_GOTOFF 166 -+#define R_SH_GOTPC 167 -+/* Keep this the last entry. */ -+#define R_SH_NUM 256 -+ -+/* Additional s390 relocs */ -+ -+#define R_390_NONE 0 /* No reloc. */ -+#define R_390_8 1 /* Direct 8 bit. */ -+#define R_390_12 2 /* Direct 12 bit. */ -+#define R_390_16 3 /* Direct 16 bit. */ -+#define R_390_32 4 /* Direct 32 bit. */ -+#define R_390_PC32 5 /* PC relative 32 bit. */ -+#define R_390_GOT12 6 /* 12 bit GOT offset. */ -+#define R_390_GOT32 7 /* 32 bit GOT offset. */ -+#define R_390_PLT32 8 /* 32 bit PC relative PLT address. */ -+#define R_390_COPY 9 /* Copy symbol at runtime. */ -+#define R_390_GLOB_DAT 10 /* Create GOT entry. */ -+#define R_390_JMP_SLOT 11 /* Create PLT entry. */ -+#define R_390_RELATIVE 12 /* Adjust by program base. */ -+#define R_390_GOTOFF32 13 /* 32 bit offset to GOT. */ -+#define R_390_GOTPC 14 /* 32 bit PC relative offset to GOT. */ -+#define R_390_GOT16 15 /* 16 bit GOT offset. */ -+#define R_390_PC16 16 /* PC relative 16 bit. */ -+#define R_390_PC16DBL 17 /* PC relative 16 bit shifted by 1. */ -+#define R_390_PLT16DBL 18 /* 16 bit PC rel. PLT shifted by 1. */ -+#define R_390_PC32DBL 19 /* PC relative 32 bit shifted by 1. */ -+#define R_390_PLT32DBL 20 /* 32 bit PC rel. PLT shifted by 1. */ -+#define R_390_GOTPCDBL 21 /* 32 bit PC rel. GOT shifted by 1. */ -+#define R_390_64 22 /* Direct 64 bit. */ -+#define R_390_PC64 23 /* PC relative 64 bit. */ -+#define R_390_GOT64 24 /* 64 bit GOT offset. */ -+#define R_390_PLT64 25 /* 64 bit PC relative PLT address. */ -+#define R_390_GOTENT 26 /* 32 bit PC rel. to GOT entry >> 1. */ -+#define R_390_GOTOFF16 27 /* 16 bit offset to GOT. */ -+#define R_390_GOTOFF64 28 /* 64 bit offset to GOT. */ -+#define R_390_GOTPLT12 29 /* 12 bit offset to jump slot. */ -+#define R_390_GOTPLT16 30 /* 16 bit offset to jump slot. */ -+#define R_390_GOTPLT32 31 /* 32 bit offset to jump slot. */ -+#define R_390_GOTPLT64 32 /* 64 bit offset to jump slot. */ -+#define R_390_GOTPLTENT 33 /* 32 bit rel. offset to jump slot. */ -+#define R_390_PLTOFF16 34 /* 16 bit offset from GOT to PLT. */ -+#define R_390_PLTOFF32 35 /* 32 bit offset from GOT to PLT. */ -+#define R_390_PLTOFF64 36 /* 16 bit offset from GOT to PLT. */ -+#define R_390_TLS_LOAD 37 /* Tag for load insn in TLS code. */ -+#define R_390_TLS_GDCALL 38 /* Tag for function call in general -+ dynamic TLS code. */ -+#define R_390_TLS_LDCALL 39 /* Tag for function call in local -+ dynamic TLS code. */ -+#define R_390_TLS_GD32 40 /* Direct 32 bit for general dynamic -+ thread local data. */ -+#define R_390_TLS_GD64 41 /* Direct 64 bit for general dynamic -+ thread local data. */ -+#define R_390_TLS_GOTIE12 42 /* 12 bit GOT offset for static TLS -+ block offset. */ -+#define R_390_TLS_GOTIE32 43 /* 32 bit GOT offset for static TLS -+ block offset. */ -+#define R_390_TLS_GOTIE64 44 /* 64 bit GOT offset for static TLS -+ block offset. */ -+#define R_390_TLS_LDM32 45 /* Direct 32 bit for local dynamic -+ thread local data in LE code. */ -+#define R_390_TLS_LDM64 46 /* Direct 64 bit for local dynamic -+ thread local data in LE code. */ -+#define R_390_TLS_IE32 47 /* 32 bit address of GOT entry for -+ negated static TLS block offset. */ -+#define R_390_TLS_IE64 48 /* 64 bit address of GOT entry for -+ negated static TLS block offset. */ -+#define R_390_TLS_IEENT 49 /* 32 bit rel. offset to GOT entry for -+ negated static TLS block offset. */ -+#define R_390_TLS_LE32 50 /* 32 bit negated offset relative to -+ static TLS block. */ -+#define R_390_TLS_LE64 51 /* 64 bit negated offset relative to -+ static TLS block. */ -+#define R_390_TLS_LDO32 52 /* 32 bit offset relative to TLS -+ block. */ -+#define R_390_TLS_LDO64 53 /* 64 bit offset relative to TLS -+ block. */ -+#define R_390_TLS_DTPMOD 54 /* ID of module containing symbol. */ -+#define R_390_TLS_DTPOFF 55 /* Offset in TLS block. */ -+#define R_390_TLS_TPOFF 56 /* Negated offset in static TLS -+ block. */ -+ -+/* Keep this the last entry. */ -+#define R_390_NUM 57 -+ -+/* CRIS relocations. */ -+#define R_CRIS_NONE 0 -+#define R_CRIS_8 1 -+#define R_CRIS_16 2 -+#define R_CRIS_32 3 -+#define R_CRIS_8_PCREL 4 -+#define R_CRIS_16_PCREL 5 -+#define R_CRIS_32_PCREL 6 -+#define R_CRIS_GNU_VTINHERIT 7 -+#define R_CRIS_GNU_VTENTRY 8 -+#define R_CRIS_COPY 9 -+#define R_CRIS_GLOB_DAT 10 -+#define R_CRIS_JUMP_SLOT 11 -+#define R_CRIS_RELATIVE 12 -+#define R_CRIS_16_GOT 13 -+#define R_CRIS_32_GOT 14 -+#define R_CRIS_16_GOTPLT 15 -+#define R_CRIS_32_GOTPLT 16 -+#define R_CRIS_32_GOTREL 17 -+#define R_CRIS_32_PLT_GOTREL 18 -+#define R_CRIS_32_PLT_PCREL 19 -+ -+#define R_CRIS_NUM 20 -+ -+/* AMD x86-64 relocations. */ -+#define R_X86_64_NONE 0 /* No reloc */ -+#define R_X86_64_64 1 /* Direct 64 bit */ -+#define R_X86_64_PC32 2 /* PC relative 32 bit signed */ -+#define R_X86_64_GOT32 3 /* 32 bit GOT entry */ -+#define R_X86_64_PLT32 4 /* 32 bit PLT address */ -+#define R_X86_64_COPY 5 /* Copy symbol at runtime */ -+#define R_X86_64_GLOB_DAT 6 /* Create GOT entry */ -+#define R_X86_64_JUMP_SLOT 7 /* Create PLT entry */ -+#define R_X86_64_RELATIVE 8 /* Adjust by program base */ -+#define R_X86_64_GOTPCREL 9 /* 32 bit signed PC relative -+ offset to GOT */ -+#define R_X86_64_32 10 /* Direct 32 bit zero extended */ -+#define R_X86_64_32S 11 /* Direct 32 bit sign extended */ -+#define R_X86_64_16 12 /* Direct 16 bit zero extended */ -+#define R_X86_64_PC16 13 /* 16 bit sign extended pc relative */ -+#define R_X86_64_8 14 /* Direct 8 bit sign extended */ -+#define R_X86_64_PC8 15 /* 8 bit sign extended pc relative */ -+#define R_X86_64_DTPMOD64 16 /* ID of module containing symbol */ -+#define R_X86_64_DTPOFF64 17 /* Offset in module's TLS block */ -+#define R_X86_64_TPOFF64 18 /* Offset in initial TLS block */ -+#define R_X86_64_TLSGD 19 /* 32 bit signed PC relative offset -+ to two GOT entries for GD symbol */ -+#define R_X86_64_TLSLD 20 /* 32 bit signed PC relative offset -+ to two GOT entries for LD symbol */ -+#define R_X86_64_DTPOFF32 21 /* Offset in TLS block */ -+#define R_X86_64_GOTTPOFF 22 /* 32 bit signed PC relative offset -+ to GOT entry for IE symbol */ -+#define R_X86_64_TPOFF32 23 /* Offset in initial TLS block */ -+ -+#define R_X86_64_NUM 24 -+ -+__END_DECLS -+ -+#endif /* elf.h */ - - #include "elfconfig.h" - -@@ -195,3 +2641,4 @@ - void fatal(const char *fmt, ...); - void warn(const char *fmt, ...); - void merror(const char *fmt, ...); -+ -diff -Nur linux-2.6.36.orig/scripts/mod/sumversion.c linux-2.6.36/scripts/mod/sumversion.c ---- linux-2.6.36.orig/scripts/mod/sumversion.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/scripts/mod/sumversion.c 2010-11-28 18:33:24.000000000 +0100 -@@ -1,4 +1,4 @@ --#include -+/* #include */ - #ifdef __sun__ - #include - #else diff --git a/target/linux/patches/2.6.37/cc-abstract.patch b/target/linux/patches/2.6.37/cc-abstract.patch deleted file mode 100644 index dc5d87f0d..000000000 --- a/target/linux/patches/2.6.37/cc-abstract.patch +++ /dev/null @@ -1,14 +0,0 @@ -diff -Nur linux-2.6.32.orig/Makefile linux-2.6.32/Makefile ---- linux-2.6.32.orig/Makefile Thu Dec 3 04:50:57 2009 -+++ linux-2.6.32/Makefile Fri Dec 18 20:53:57 2009 -@@ -219,8 +219,8 @@ - else if [ -x /bin/bash ]; then echo /bin/bash; \ - else echo sh; fi ; fi) - --HOSTCC = gcc --HOSTCXX = g++ -+HOSTCC ?= gcc -+HOSTCXX ?= g++ - HOSTCFLAGS = -Wall -Wmissing-prototypes -Wstrict-prototypes -O2 -fomit-frame-pointer - HOSTCXXFLAGS = -O2 - diff --git a/target/linux/patches/2.6.37/cris.patch b/target/linux/patches/2.6.37/cris.patch deleted file mode 100644 index 7f692ed30..000000000 --- a/target/linux/patches/2.6.37/cris.patch +++ /dev/null @@ -1,5745 +0,0 @@ -diff -Nur linux-2.6.37.orig/arch/cris/arch-v10/drivers/axisflashmap.c linux-2.6.37/arch/cris/arch-v10/drivers/axisflashmap.c ---- linux-2.6.37.orig/arch/cris/arch-v10/drivers/axisflashmap.c 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/cris/arch-v10/drivers/axisflashmap.c 2011-04-27 12:05:31.277662574 +0200 -@@ -113,7 +113,7 @@ - - /* If no partition-table was found, we use this default-set. */ - #define MAX_PARTITIONS 7 --#define NUM_DEFAULT_PARTITIONS 3 -+#define NUM_DEFAULT_PARTITIONS 4 - - /* - * Default flash size is 2MB. CONFIG_ETRAX_PTABLE_SECTOR is most likely the -@@ -122,19 +122,24 @@ - */ - static struct mtd_partition axis_default_partitions[NUM_DEFAULT_PARTITIONS] = { - { -- .name = "boot firmware", -- .size = CONFIG_ETRAX_PTABLE_SECTOR, -+ .name = "kernel", -+ .size = 0x00, - .offset = 0 - }, - { -- .name = "kernel", -- .size = 0x200000 - (6 * CONFIG_ETRAX_PTABLE_SECTOR), -- .offset = CONFIG_ETRAX_PTABLE_SECTOR -+ .name = "rootfs", -+ .size = 0x200000 , -+ .offset = 0x200000 - }, - { -- .name = "filesystem", -- .size = 5 * CONFIG_ETRAX_PTABLE_SECTOR, -- .offset = 0x200000 - (5 * CONFIG_ETRAX_PTABLE_SECTOR) -+ .name = "cfgfs", -+ .size = 0x20000 , -+ .offset = CONFIG_ETRAX_MTD_SIZE - 0x20000 -+ }, -+ { -+ .name = "linux", -+ .size = CONFIG_ETRAX_MTD_SIZE - 0x20000, -+ .offset = 0 - } - }; - -@@ -281,6 +286,11 @@ - struct partitiontable_entry *ptable; - int use_default_ptable = 1; /* Until proven otherwise. */ - const char pmsg[] = " /dev/flash%d at 0x%08x, size 0x%08x\n"; -+ unsigned int kernel_part_size = 0; -+ unsigned char *flash_mem = (unsigned char*)(FLASH_CACHED_ADDR); -+ unsigned int flash_scan_count = 0; -+ const char *part_magic = "ACME_PART_MAGIC"; -+ unsigned int magic_len = strlen(part_magic); - - if (!(mymtd = flash_probe())) { - /* There's no reason to use this module if no flash chip can -@@ -292,6 +302,31 @@ - mymtd->name, mymtd->size); - axisflash_mtd = mymtd; - } -+ /* scan flash to findout where out partition starts */ -+ -+ printk(KERN_INFO "Scanning flash for end of kernel magic\n"); -+ for(flash_scan_count = 0; flash_scan_count < 100000; flash_scan_count++){ -+ if(strncmp(&flash_mem[flash_scan_count], part_magic, magic_len - 1) == 0) -+ { -+ kernel_part_size = flash_mem[flash_scan_count + magic_len ]; -+ kernel_part_size <<= 8; -+ kernel_part_size += flash_mem[flash_scan_count + magic_len + 2]; -+ kernel_part_size <<= 8; -+ kernel_part_size += flash_mem[flash_scan_count + magic_len + 1]; -+ kernel_part_size <<= 8; -+ kernel_part_size += flash_mem[flash_scan_count + magic_len + 3]; -+ printk(KERN_INFO "Kernel ends at 0x%.08X\n", kernel_part_size); -+ flash_scan_count = 1100000; -+ } -+ } -+ -+ -+ if(kernel_part_size){ -+ kernel_part_size = (kernel_part_size & 0xffff0000); -+ axis_default_partitions[0].size = kernel_part_size; -+ axis_default_partitions[1].size = mymtd->size - axis_default_partitions[0].size - axis_default_partitions[2].size; -+ axis_default_partitions[1].offset = axis_default_partitions[0].size; -+ } - - if (mymtd) { - mymtd->owner = THIS_MODULE; -@@ -360,21 +395,6 @@ - use_default_ptable = !ptable_ok; - } - -- if (romfs_in_flash) { -- /* Add an overlapping device for the root partition (romfs). */ -- -- axis_partitions[pidx].name = "romfs"; -- axis_partitions[pidx].size = romfs_length; -- axis_partitions[pidx].offset = romfs_start - FLASH_CACHED_ADDR; -- axis_partitions[pidx].mask_flags |= MTD_WRITEABLE; -- -- printk(KERN_INFO -- " Adding readonly flash partition for romfs image:\n"); -- printk(pmsg, pidx, axis_partitions[pidx].offset, -- axis_partitions[pidx].size); -- pidx++; -- } -- - #ifdef CONFIG_ETRAX_AXISFLASHMAP_MTD0WHOLE - if (mymtd) { - main_partition.size = mymtd->size; -@@ -397,36 +417,6 @@ - if (err) - panic("axisflashmap could not add MTD partitions!\n"); - } -- -- if (!romfs_in_flash) { -- /* Create an RAM device for the root partition (romfs). */ -- --#if !defined(CONFIG_MTD_MTDRAM) || (CONFIG_MTDRAM_TOTAL_SIZE != 0) || (CONFIG_MTDRAM_ABS_POS != 0) -- /* No use trying to boot this kernel from RAM. Panic! */ -- printk(KERN_EMERG "axisflashmap: Cannot create an MTD RAM " -- "device due to kernel (mis)configuration!\n"); -- panic("This kernel cannot boot from RAM!\n"); --#else -- struct mtd_info *mtd_ram; -- -- mtd_ram = kmalloc(sizeof(struct mtd_info), GFP_KERNEL); -- if (!mtd_ram) -- panic("axisflashmap couldn't allocate memory for " -- "mtd_info!\n"); -- -- printk(KERN_INFO " Adding RAM partition for romfs image:\n"); -- printk(pmsg, pidx, (unsigned)romfs_start, -- (unsigned)romfs_length); -- -- err = mtdram_init_device(mtd_ram, -- (void *)romfs_start, -- romfs_length, -- "romfs"); -- if (err) -- panic("axisflashmap could not initialize MTD RAM " -- "device!\n"); --#endif -- } - return err; - } - -diff -Nur linux-2.6.37.orig/arch/cris/arch-v10/drivers/ds1302.c linux-2.6.37/arch/cris/arch-v10/drivers/ds1302.c ---- linux-2.6.37.orig/arch/cris/arch-v10/drivers/ds1302.c 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/cris/arch-v10/drivers/ds1302.c 2011-04-27 12:05:31.337661896 +0200 -@@ -22,6 +22,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -501,6 +502,10 @@ - return 0; - } - -+#ifdef CONFIG_SYSFS -+static struct class *rtc_class; -+#endif -+ - static int __init ds1302_register(void) - { - ds1302_init(); -@@ -509,6 +514,12 @@ - ds1302_name, RTC_MAJOR_NR); - return -1; - } -+ #ifdef CONFIG_SYSFS -+ rtc_class = class_create(THIS_MODULE, "rtc"); -+ class_device_create(rtc_class, NULL, MKDEV(RTC_MAJOR_NR, 0), -+ NULL, "rtc"); -+ #endif -+ - return 0; - - } -diff -Nur linux-2.6.37.orig/arch/cris/arch-v10/drivers/gpio.c linux-2.6.37/arch/cris/arch-v10/drivers/gpio.c ---- linux-2.6.37.orig/arch/cris/arch-v10/drivers/gpio.c 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/cris/arch-v10/drivers/gpio.c 2011-04-27 12:05:31.377662210 +0200 -@@ -20,6 +20,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -798,6 +799,10 @@ - - /* main driver initialization routine, called from mem.c */ - -+#ifdef CONFIG_SYSFS -+static struct class *gpio_class; -+#endif -+ - static int __init gpio_init(void) - { - int res; -@@ -811,6 +816,13 @@ - return res; - } - -+#ifdef CONFIG_SYSFS -+ gpio_class = class_create(THIS_MODULE, "gpio"); -+ device_create(gpio_class, NULL, MKDEV(GPIO_MAJOR, 0), NULL, "gpioa"); -+ device_create(gpio_class, NULL, MKDEV(GPIO_MAJOR, 1), NULL, "gpiob"); -+ device_create(gpio_class, NULL, MKDEV(GPIO_MAJOR, 2), NULL, "leds"); -+ device_create(gpio_class, NULL, MKDEV(GPIO_MAJOR, 3), NULL, "gpiog"); -+#endif - /* Clear all leds */ - #if defined (CONFIG_ETRAX_CSP0_LEDS) || defined (CONFIG_ETRAX_PA_LEDS) || defined (CONFIG_ETRAX_PB_LEDS) - CRIS_LED_NETWORK_SET(0); -diff -Nur linux-2.6.37.orig/arch/cris/arch-v10/lib/hw_settings.S linux-2.6.37/arch/cris/arch-v10/lib/hw_settings.S ---- linux-2.6.37.orig/arch/cris/arch-v10/lib/hw_settings.S 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/cris/arch-v10/lib/hw_settings.S 2011-04-27 12:05:31.417662330 +0200 -@@ -58,3 +58,5 @@ - .dword R_PORT_PB_SET - .dword PB_SET_VALUE - .dword 0 ; No more register values -+ .ascii "ACME_PART_MAGIC" -+ .dword 0xdeadc0de -diff -Nur linux-2.6.37.orig/arch/cris/arch-v10/mm/init.c linux-2.6.37/arch/cris/arch-v10/mm/init.c ---- linux-2.6.37.orig/arch/cris/arch-v10/mm/init.c 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/cris/arch-v10/mm/init.c 2011-04-27 12:23:55.347672203 +0200 -@@ -184,6 +184,9 @@ - - free_area_init_node(0, zones_size, PAGE_OFFSET >> PAGE_SHIFT, 0); - } -+void free_initrd_mem(unsigned long start, unsigned long end) -+{ -+} - - /* Initialize remaps of some I/O-ports. It is important that this - * is called before any driver is initialized. -diff -Nur linux-2.6.37.orig/arch/cris/boot/compressed/Makefile linux-2.6.37/arch/cris/boot/compressed/Makefile ---- linux-2.6.37.orig/arch/cris/boot/compressed/Makefile 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/cris/boot/compressed/Makefile 2011-04-27 12:05:31.567661802 +0200 -@@ -18,7 +18,7 @@ - OBJECTS-$(CONFIG_ETRAX_ARCH_V32) = $(obj)/head_v32.o - OBJECTS-$(CONFIG_ETRAX_ARCH_V10) = $(obj)/head_v10.o - OBJECTS= $(OBJECTS-y) $(obj)/misc.o --OBJCOPYFLAGS = -O binary --remove-section=.bss -+#OBJCOPYFLAGS = -O binary --remove-section=.bss - - quiet_cmd_image = BUILD $@ - cmd_image = cat $(obj)/decompress.bin $(obj)/piggy.gz > $@ -diff -Nur linux-2.6.37.orig/arch/cris/boot/Makefile linux-2.6.37/arch/cris/boot/Makefile ---- linux-2.6.37.orig/arch/cris/boot/Makefile 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/cris/boot/Makefile 2011-04-27 12:05:31.527662141 +0200 -@@ -5,7 +5,7 @@ - objcopyflags-$(CONFIG_ETRAX_ARCH_V10) += -R .note -R .comment - objcopyflags-$(CONFIG_ETRAX_ARCH_V32) += --remove-section=.bss --remove-section=.note.gnu.build-id - --OBJCOPYFLAGS = -O binary $(objcopyflags-y) -+#OBJCOPYFLAGS = -O binary $(objcopyflags-y) - - - subdir- := compressed rescue -@@ -17,7 +17,6 @@ - - $(obj)/compressed/vmlinux: $(obj)/Image FORCE - $(Q)$(MAKE) $(build)=$(obj)/compressed $@ -- $(Q)$(MAKE) $(build)=$(obj)/rescue $(obj)/rescue/rescue.bin - - $(obj)/zImage: $(obj)/compressed/vmlinux - @cp $< $@ -diff -Nur linux-2.6.37.orig/arch/cris/Kconfig linux-2.6.37/arch/cris/Kconfig ---- linux-2.6.37.orig/arch/cris/Kconfig 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/cris/Kconfig 2011-04-27 12:05:31.187667361 +0200 -@@ -170,6 +170,12 @@ - help - Size of DRAM (decimal in MB) typically 2, 8 or 16. - -+config ETRAX_MTD_SIZE -+ hex "MTD size (hex)" -+ default "0x00800000" -+ help -+ Size of MTD device typically 4 or 8 MB. -+ - config ETRAX_VMEM_SIZE - int "Video memory size (dec, in MB)" - depends on ETRAX_ARCH_V32 && !ETRAXFS -@@ -275,7 +281,7 @@ - select MTD_CFI_AMDSTD - select MTD_JEDECPROBE if ETRAX_ARCH_V32 - select MTD_CHAR -- select MTD_BLOCK -+ select MTD_BLOCK_RO - select MTD_PARTITIONS - select MTD_CONCAT - select MTD_COMPLEX_MAPPINGS -@@ -664,6 +670,11 @@ - - source "drivers/ide/Kconfig" - -+#mysteriously part of this standard linux driver was removed from cris build! - info@crisos.org -+source "drivers/scsi/Kconfig" -+ -+source "drivers/media/Kconfig" -+ - source "drivers/net/Kconfig" - - source "drivers/i2c/Kconfig" -@@ -679,6 +690,8 @@ - - source "fs/Kconfig" - -+source "sound/Kconfig" -+ - source "drivers/usb/Kconfig" - - source "drivers/uwb/Kconfig" -diff -Nur linux-2.6.37.orig/arch/cris/Makefile linux-2.6.37/arch/cris/Makefile ---- linux-2.6.37.orig/arch/cris/Makefile 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/cris/Makefile 2011-04-27 12:05:31.217662105 +0200 -@@ -40,10 +40,10 @@ - - LD = $(CROSS_COMPILE)ld -mcrislinux - --OBJCOPYFLAGS := -O binary -R .note -R .comment -S -+OBJCOPYFLAGS := -O binary -R .bss -R .note -R .note.gnu.build-id -R .comment -S - - KBUILD_AFLAGS += -mlinux -march=$(arch-y) $(inc) --KBUILD_CFLAGS += -mlinux -march=$(arch-y) -pipe $(inc) -+KBUILD_CFLAGS += -mlinux -march=$(arch-y) -pipe -fno-peephole2 $(inc) - KBUILD_CPPFLAGS += $(inc) - - ifdef CONFIG_FRAME_POINTER -diff -Nur linux-2.6.37.orig/arch/cris/mm/init.c linux-2.6.37/arch/cris/mm/init.c ---- linux-2.6.37.orig/arch/cris/mm/init.c 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/cris/mm/init.c 2011-04-27 12:23:46.628914539 +0200 -@@ -16,6 +16,7 @@ - DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); - - unsigned long empty_zero_page; -+EXPORT_SYMBOL(empty_zero_page); - - extern char _stext, _edata, _etext; /* From linkerscript */ - extern char __init_begin, __init_end; -@@ -81,3 +82,10 @@ - printk (KERN_INFO "Freeing unused kernel memory: %luk freed\n", - (unsigned long)((&__init_end - &__init_begin) >> 10)); - } -+ -+#ifdef CONFIG_BLK_DEV_INITRD -+void free_initrd_mem(unsigned long start, unsigned long end) -+{ -+ return 0; -+} -+#endif -diff -Nur linux-2.6.37.orig/drivers/net/cris/eth_v10.c linux-2.6.37/drivers/net/cris/eth_v10.c ---- linux-2.6.37.orig/drivers/net/cris/eth_v10.c 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/net/cris/eth_v10.c 2011-04-27 12:05:31.647661894 +0200 -@@ -1718,7 +1718,7 @@ - static void - e100_netpoll(struct net_device* netdev) - { -- e100rxtx_interrupt(NETWORK_DMA_TX_IRQ_NBR, netdev, NULL); -+ e100rxtx_interrupt(NETWORK_DMA_TX_IRQ_NBR, netdev); - } - #endif - -diff -Nur linux-2.6.37.orig/drivers/serial/crisv10.c linux-2.6.37/drivers/serial/crisv10.c ---- linux-2.6.37.orig/drivers/serial/crisv10.c 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/serial/crisv10.c 2011-04-27 12:05:31.657662263 +0200 -@@ -13,6 +13,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -26,6 +27,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -4431,6 +4433,7 @@ - #endif - }; - -+static struct class *rs_class; - static int __init rs_init(void) - { - int i; -@@ -4565,6 +4568,24 @@ - #endif - #endif /* CONFIG_SVINTO_SIM */ - -+ rs_class = class_create(THIS_MODULE, "rs_tty"); -+#ifdef CONFIG_ETRAX_SERIAL_PORT0 -+ device_create(rs_class, NULL, -+ MKDEV(TTY_MAJOR, 64), NULL, "ttyS0"); -+#endif -+#ifdef CONFIG_ETRAX_SERIAL_PORT1 -+ device_create(rs_class, NULL, -+ MKDEV(TTY_MAJOR, 65), NULL, "ttyS1"); -+#endif -+#ifdef CONFIG_ETRAX_SERIAL_PORT2 -+ device_create(rs_class, NULL, -+ MKDEV(TTY_MAJOR, 66), NULL, "ttyS2"); -+#endif -+#ifdef CONFIG_ETRAX_SERIAL_PORT3 -+ device_create(rs_class, NULL, -+ MKDEV(TTY_MAJOR, 67), NULL, "ttyS3"); -+#endif -+ - return 0; - } - -diff -Nur linux-2.6.37.orig/drivers/usb/host/hc-cris-dbg.h linux-2.6.37/drivers/usb/host/hc-cris-dbg.h ---- linux-2.6.37.orig/drivers/usb/host/hc-cris-dbg.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/drivers/usb/host/hc-cris-dbg.h 2011-04-27 12:05:31.847661851 +0200 -@@ -0,0 +1,146 @@ -+ -+/* macros for debug output */ -+ -+#define warn(fmt, args...) \ -+ printk(KERN_INFO "crisv10 warn: ");printk(fmt, ## args) -+ -+#define hcd_dbg(hcd, fmt, args...) \ -+ dev_info(hcd->self.controller, fmt, ## args) -+#define hcd_err(hcd, fmt, args...) \ -+ dev_err(hcd->self.controller, fmt, ## args) -+#define hcd_info(hcd, fmt, args...) \ -+ dev_info(hcd->self.controller, fmt, ## args) -+#define hcd_warn(hcd, fmt, args...) \ -+ dev_warn(hcd->self.controller, fmt, ## args) -+ -+/* -+#define devdrv_dbg(fmt, args...) \ -+ printk(KERN_INFO "usb_devdrv dbg: ");printk(fmt, ## args) -+*/ -+#define devdrv_dbg(fmt, args...) {} -+ -+#define devdrv_err(fmt, args...) \ -+ printk(KERN_ERR "usb_devdrv error: ");printk(fmt, ## args) -+#define devdrv_info(fmt, args...) \ -+ printk(KERN_INFO "usb_devdrv: ");printk(fmt, ## args) -+ -+#define irq_dbg(fmt, args...) \ -+ printk(KERN_INFO "crisv10_irq dbg: ");printk(fmt, ## args) -+#define irq_err(fmt, args...) \ -+ printk(KERN_ERR "crisv10_irq error: ");printk(fmt, ## args) -+#define irq_warn(fmt, args...) \ -+ printk(KERN_INFO "crisv10_irq warn: ");printk(fmt, ## args) -+#define irq_info(fmt, args...) \ -+ printk(KERN_INFO "crisv10_hcd: ");printk(fmt, ## args) -+ -+/* -+#define rh_dbg(fmt, args...) \ -+ printk(KERN_DEBUG "crisv10_rh dbg: ");printk(fmt, ## args) -+*/ -+#define rh_dbg(fmt, args...) {} -+ -+#define rh_err(fmt, args...) \ -+ printk(KERN_ERR "crisv10_rh error: ");printk(fmt, ## args) -+#define rh_warn(fmt, args...) \ -+ printk(KERN_INFO "crisv10_rh warning: ");printk(fmt, ## args) -+#define rh_info(fmt, args...) \ -+ printk(KERN_INFO "crisv10_rh: ");printk(fmt, ## args) -+ -+/* -+#define tc_dbg(fmt, args...) \ -+ printk(KERN_INFO "crisv10_tc dbg: ");printk(fmt, ## args) -+*/ -+#define tc_dbg(fmt, args...) {while(0){}} -+ -+#define tc_err(fmt, args...) \ -+ printk(KERN_ERR "crisv10_tc error: ");printk(fmt, ## args) -+/* -+#define tc_warn(fmt, args...) \ -+ printk(KERN_INFO "crisv10_tc warning: ");printk(fmt, ## args) -+*/ -+#define tc_warn(fmt, args...) {while(0){}} -+ -+#define tc_info(fmt, args...) \ -+ printk(KERN_INFO "crisv10_tc: ");printk(fmt, ## args) -+ -+ -+/* Debug print-outs for various traffic types */ -+ -+#define intr_warn(fmt, args...) \ -+ printk(KERN_INFO "crisv10_intr warning: ");printk(fmt, ## args) -+ -+#define intr_dbg(fmt, args...) \ -+ printk(KERN_DEBUG "crisv10_intr dbg: ");printk(fmt, ## args) -+/* -+#define intr_dbg(fmt, args...) {while(0){}} -+*/ -+ -+ -+#define isoc_err(fmt, args...) \ -+ printk(KERN_ERR "crisv10_isoc error: ");printk(fmt, ## args) -+/* -+#define isoc_warn(fmt, args...) \ -+ printk(KERN_INFO "crisv10_isoc warning: ");printk(fmt, ## args) -+*/ -+#define isoc_warn(fmt, args...) {while(0){}} -+ -+/* -+#define isoc_dbg(fmt, args...) \ -+ printk(KERN_INFO "crisv10_isoc dbg: ");printk(fmt, ## args) -+*/ -+#define isoc_dbg(fmt, args...) {while(0){}} -+ -+/* -+#define timer_warn(fmt, args...) \ -+ printk(KERN_INFO "crisv10_timer warning: ");printk(fmt, ## args) -+*/ -+#define timer_warn(fmt, args...) {while(0){}} -+ -+/* -+#define timer_dbg(fmt, args...) \ -+ printk(KERN_INFO "crisv10_timer dbg: ");printk(fmt, ## args) -+*/ -+#define timer_dbg(fmt, args...) {while(0){}} -+ -+ -+/* Debug printouts for events related to late finishing of URBs */ -+ -+#define late_dbg(fmt, args...) \ -+ printk(KERN_INFO "crisv10_late dbg: ");printk(fmt, ## args) -+/* -+#define late_dbg(fmt, args...) {while(0){}} -+*/ -+ -+#define late_warn(fmt, args...) \ -+ printk(KERN_INFO "crisv10_late warning: ");printk(fmt, ## args) -+/* -+#define errno_dbg(fmt, args...) \ -+ printk(KERN_INFO "crisv10_errno dbg: ");printk(fmt, ## args) -+*/ -+#define errno_dbg(fmt, args...) {while(0){}} -+ -+ -+#define dma_dbg(fmt, args...) \ -+ printk(KERN_INFO "crisv10_dma dbg: ");printk(fmt, ## args) -+#define dma_err(fmt, args...) \ -+ printk(KERN_ERR "crisv10_dma error: ");printk(fmt, ## args) -+#define dma_warn(fmt, args...) \ -+ printk(KERN_INFO "crisv10_dma warning: ");printk(fmt, ## args) -+#define dma_info(fmt, args...) \ -+ printk(KERN_INFO "crisv10_dma: ");printk(fmt, ## args) -+ -+ -+ -+#define str_dir(pipe) \ -+ (usb_pipeout(pipe) ? "out" : "in") -+#define str_type(pipe) \ -+ ({ \ -+ char *s = "?"; \ -+ switch (usb_pipetype(pipe)) { \ -+ case PIPE_ISOCHRONOUS: s = "iso"; break; \ -+ case PIPE_INTERRUPT: s = "intr"; break; \ -+ case PIPE_CONTROL: s = "ctrl"; break; \ -+ case PIPE_BULK: s = "bulk"; break; \ -+ }; \ -+ s; \ -+ }) -diff -Nur linux-2.6.37.orig/drivers/usb/host/hc-crisv10.c linux-2.6.37/drivers/usb/host/hc-crisv10.c ---- linux-2.6.37.orig/drivers/usb/host/hc-crisv10.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/drivers/usb/host/hc-crisv10.c 2011-04-27 12:05:31.867662137 +0200 -@@ -0,0 +1,4801 @@ -+/* -+ * -+ * ETRAX 100LX USB Host Controller Driver -+ * -+ * Copyright (C) 2005, 2006 Axis Communications AB -+ * -+ * Author: Konrad Eriksson -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+ -+#include "hc-crisv10.h" -+#include "hc-cris-dbg.h" -+ -+ -+/***************************************************************************/ -+/***************************************************************************/ -+/* Host Controller settings */ -+/***************************************************************************/ -+/***************************************************************************/ -+ -+#define VERSION "1.00 hinko.4" -+#define COPYRIGHT "(c) 2005, 2006 Axis Communications AB" -+#define DESCRIPTION "ETRAX 100LX USB Host Controller" -+ -+#define ETRAX_USB_HC_IRQ USB_HC_IRQ_NBR -+#define ETRAX_USB_RX_IRQ USB_DMA_RX_IRQ_NBR -+#define ETRAX_USB_TX_IRQ USB_DMA_TX_IRQ_NBR -+ -+/* Number of physical ports in Etrax 100LX */ -+#define USB_ROOT_HUB_PORTS 2 -+ -+const char hc_name[] = "hc-crisv10"; -+const char product_desc[] = DESCRIPTION; -+ -+/* The number of epids is, among other things, used for pre-allocating -+ ctrl, bulk and isoc EP descriptors (one for each epid). -+ Assumed to be > 1 when initiating the DMA lists. */ -+#define NBR_OF_EPIDS 32 -+ -+/* Support interrupt traffic intervals up to 128 ms. */ -+#define MAX_INTR_INTERVAL 128 -+ -+/* If periodic traffic (intr or isoc) is to be used, then one entry in the EP -+ table must be "invalid". By this we mean that we shouldn't care about epid -+ attentions for this epid, or at least handle them differently from epid -+ attentions for "valid" epids. This define determines which one to use -+ (don't change it). */ -+#define INVALID_EPID 31 -+/* A special epid for the bulk dummys. */ -+#define DUMMY_EPID 30 -+ -+/* Module settings */ -+ -+MODULE_DESCRIPTION(DESCRIPTION); -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Konrad Eriksson "); -+ -+ -+/* Module parameters */ -+ -+/* 0 = No ports enabled -+ 1 = Only port 1 enabled (on board ethernet on devboard) -+ 2 = Only port 2 enabled (external connector on devboard) -+ 3 = Both ports enabled -+*/ -+static unsigned int ports = 3; -+module_param(ports, uint, S_IRUGO); -+MODULE_PARM_DESC(ports, "Bitmask indicating USB ports to use"); -+ -+ -+/***************************************************************************/ -+/***************************************************************************/ -+/* Shared global variables for this module */ -+/***************************************************************************/ -+/***************************************************************************/ -+ -+/* EP descriptor lists for non period transfers. Must be 32-bit aligned. */ -+static volatile struct USB_EP_Desc TxBulkEPList[NBR_OF_EPIDS] __attribute__ ((aligned (4))); -+ -+static volatile struct USB_EP_Desc TxCtrlEPList[NBR_OF_EPIDS] __attribute__ ((aligned (4))); -+ -+/* EP descriptor lists for period transfers. Must be 32-bit aligned. */ -+static volatile struct USB_EP_Desc TxIntrEPList[MAX_INTR_INTERVAL] __attribute__ ((aligned (4))); -+static volatile struct USB_SB_Desc TxIntrSB_zout __attribute__ ((aligned (4))); -+ -+static volatile struct USB_EP_Desc TxIsocEPList[NBR_OF_EPIDS] __attribute__ ((aligned (4))); -+static volatile struct USB_SB_Desc TxIsocSB_zout __attribute__ ((aligned (4))); -+ -+//static volatile struct USB_SB_Desc TxIsocSBList[NBR_OF_EPIDS] __attribute__ ((aligned (4))); -+ -+/* After each enabled bulk EP IN we put two disabled EP descriptors with the eol flag set, -+ causing the DMA to stop the DMA channel. The first of these two has the intr flag set, which -+ gives us a dma8_sub0_descr interrupt. When we receive this, we advance the DMA one step in the -+ EP list and then restart the bulk channel, thus forcing a switch between bulk EP descriptors -+ in each frame. */ -+static volatile struct USB_EP_Desc TxBulkDummyEPList[NBR_OF_EPIDS][2] __attribute__ ((aligned (4))); -+ -+/* List of URB pointers, where each points to the active URB for a epid. -+ For Bulk, Ctrl and Intr this means which URB that currently is added to -+ DMA lists (Isoc URBs are all directly added to DMA lists). As soon as -+ URB has completed is the queue examined and the first URB in queue is -+ removed and moved to the activeUrbList while its state change to STARTED and -+ its transfer(s) gets added to DMA list (exception Isoc where URBs enter -+ state STARTED directly and added transfers added to DMA lists). */ -+static struct urb *activeUrbList[NBR_OF_EPIDS]; -+ -+/* Additional software state info for each epid */ -+static struct etrax_epid epid_state[NBR_OF_EPIDS]; -+ -+/* Timer handles for bulk traffic timer used to avoid DMA bug where DMA stops -+ even if there is new data waiting to be processed */ -+static struct timer_list bulk_start_timer = TIMER_INITIALIZER(NULL, 0, 0); -+static struct timer_list bulk_eot_timer = TIMER_INITIALIZER(NULL, 0, 0); -+ -+/* We want the start timer to expire before the eot timer, because the former -+ might start traffic, thus making it unnecessary for the latter to time -+ out. */ -+#define BULK_START_TIMER_INTERVAL (HZ/50) /* 20 ms */ -+#define BULK_EOT_TIMER_INTERVAL (HZ/16) /* 60 ms */ -+ -+/* Delay before a URB completion happen when it's scheduled to be delayed */ -+#define LATER_TIMER_DELAY (HZ/50) /* 20 ms */ -+ -+/* Simplifying macros for checking software state info of a epid */ -+/* ----------------------------------------------------------------------- */ -+#define epid_inuse(epid) epid_state[epid].inuse -+#define epid_out_traffic(epid) epid_state[epid].out_traffic -+#define epid_isoc(epid) (epid_state[epid].type == PIPE_ISOCHRONOUS ? 1 : 0) -+#define epid_intr(epid) (epid_state[epid].type == PIPE_INTERRUPT ? 1 : 0) -+ -+ -+/***************************************************************************/ -+/***************************************************************************/ -+/* DEBUG FUNCTIONS */ -+/***************************************************************************/ -+/***************************************************************************/ -+/* Note that these functions are always available in their "__" variants, -+ for use in error situations. The "__" missing variants are controlled by -+ the USB_DEBUG_DESC/USB_DEBUG_URB macros. */ -+static void __dump_urb(struct urb* purb) -+{ -+ struct crisv10_urb_priv *urb_priv = purb->hcpriv; -+ int urb_num = -1; -+ if(urb_priv) { -+ urb_num = urb_priv->urb_num; -+ } -+ printk("\nURB:0x%x[%d]\n", (unsigned int)purb, urb_num); -+ printk("dev :0x%08lx\n", (unsigned long)purb->dev); -+ printk("pipe :0x%08x\n", purb->pipe); -+ printk("status :%d\n", purb->status); -+ printk("transfer_flags :0x%08x\n", purb->transfer_flags); -+ printk("transfer_buffer :0x%08lx\n", (unsigned long)purb->transfer_buffer); -+ printk("transfer_buffer_length:%d\n", purb->transfer_buffer_length); -+ printk("actual_length :%d\n", purb->actual_length); -+ printk("setup_packet :0x%08lx\n", (unsigned long)purb->setup_packet); -+ printk("start_frame :%d\n", purb->start_frame); -+ printk("number_of_packets :%d\n", purb->number_of_packets); -+ printk("interval :%d\n", purb->interval); -+ printk("error_count :%d\n", purb->error_count); -+ printk("context :0x%08lx\n", (unsigned long)purb->context); -+ printk("complete :0x%08lx\n\n", (unsigned long)purb->complete); -+} -+ -+static void __dump_in_desc(volatile struct USB_IN_Desc *in) -+{ -+ printk("\nUSB_IN_Desc at 0x%08lx\n", (unsigned long)in); -+ printk(" sw_len : 0x%04x (%d)\n", in->sw_len, in->sw_len); -+ printk(" command : 0x%04x\n", in->command); -+ printk(" next : 0x%08lx\n", in->next); -+ printk(" buf : 0x%08lx\n", in->buf); -+ printk(" hw_len : 0x%04x (%d)\n", in->hw_len, in->hw_len); -+ printk(" status : 0x%04x\n\n", in->status); -+} -+ -+static void __dump_sb_desc(volatile struct USB_SB_Desc *sb) -+{ -+ char tt = (sb->command & 0x30) >> 4; -+ char *tt_string; -+ -+ switch (tt) { -+ case 0: -+ tt_string = "zout"; -+ break; -+ case 1: -+ tt_string = "in"; -+ break; -+ case 2: -+ tt_string = "out"; -+ break; -+ case 3: -+ tt_string = "setup"; -+ break; -+ default: -+ tt_string = "unknown (weird)"; -+ } -+ -+ printk(" USB_SB_Desc at 0x%08lx ", (unsigned long)sb); -+ printk(" command:0x%04x (", sb->command); -+ printk("rem:%d ", (sb->command & 0x3f00) >> 8); -+ printk("full:%d ", (sb->command & 0x40) >> 6); -+ printk("tt:%d(%s) ", tt, tt_string); -+ printk("intr:%d ", (sb->command & 0x8) >> 3); -+ printk("eot:%d ", (sb->command & 0x2) >> 1); -+ printk("eol:%d)", sb->command & 0x1); -+ printk(" sw_len:0x%04x(%d)", sb->sw_len, sb->sw_len); -+ printk(" next:0x%08lx", sb->next); -+ printk(" buf:0x%08lx\n", sb->buf); -+} -+ -+ -+static void __dump_ep_desc(volatile struct USB_EP_Desc *ep) -+{ -+ printk("USB_EP_Desc at 0x%08lx ", (unsigned long)ep); -+ printk(" command:0x%04x (", ep->command); -+ printk("ep_id:%d ", (ep->command & 0x1f00) >> 8); -+ printk("enable:%d ", (ep->command & 0x10) >> 4); -+ printk("intr:%d ", (ep->command & 0x8) >> 3); -+ printk("eof:%d ", (ep->command & 0x2) >> 1); -+ printk("eol:%d)", ep->command & 0x1); -+ printk(" hw_len:0x%04x(%d)", ep->hw_len, ep->hw_len); -+ printk(" next:0x%08lx", ep->next); -+ printk(" sub:0x%08lx\n", ep->sub); -+} -+ -+static inline void __dump_ep_list(int pipe_type) -+{ -+ volatile struct USB_EP_Desc *ep; -+ volatile struct USB_EP_Desc *first_ep; -+ volatile struct USB_SB_Desc *sb; -+ -+ switch (pipe_type) -+ { -+ case PIPE_BULK: -+ first_ep = &TxBulkEPList[0]; -+ break; -+ case PIPE_CONTROL: -+ first_ep = &TxCtrlEPList[0]; -+ break; -+ case PIPE_INTERRUPT: -+ first_ep = &TxIntrEPList[0]; -+ break; -+ case PIPE_ISOCHRONOUS: -+ first_ep = &TxIsocEPList[0]; -+ break; -+ default: -+ warn("Cannot dump unknown traffic type"); -+ return; -+ } -+ ep = first_ep; -+ -+ printk("\n\nDumping EP list...\n\n"); -+ -+ do { -+ __dump_ep_desc(ep); -+ /* Cannot phys_to_virt on 0 as it turns into 80000000, which is != 0. */ -+ sb = ep->sub ? phys_to_virt(ep->sub) : 0; -+ while (sb) { -+ __dump_sb_desc(sb); -+ sb = sb->next ? phys_to_virt(sb->next) : 0; -+ } -+ ep = (volatile struct USB_EP_Desc *)(phys_to_virt(ep->next)); -+ -+ } while (ep != first_ep); -+} -+ -+static inline void __dump_ept_data(int epid) -+{ -+ unsigned long flags; -+ __u32 r_usb_ept_data; -+ -+ if (epid < 0 || epid > 31) { -+ printk("Cannot dump ept data for invalid epid %d\n", epid); -+ return; -+ } -+ -+ local_irq_save(flags); -+ *R_USB_EPT_INDEX = IO_FIELD(R_USB_EPT_INDEX, value, epid); -+ nop(); -+ r_usb_ept_data = *R_USB_EPT_DATA; -+ local_irq_restore(flags); -+ -+ printk(" R_USB_EPT_DATA = 0x%x for epid %d :\n", r_usb_ept_data, epid); -+ if (r_usb_ept_data == 0) { -+ /* No need for more detailed printing. */ -+ return; -+ } -+ printk(" valid : %d\n", (r_usb_ept_data & 0x80000000) >> 31); -+ printk(" hold : %d\n", (r_usb_ept_data & 0x40000000) >> 30); -+ printk(" error_count_in : %d\n", (r_usb_ept_data & 0x30000000) >> 28); -+ printk(" t_in : %d\n", (r_usb_ept_data & 0x08000000) >> 27); -+ printk(" low_speed : %d\n", (r_usb_ept_data & 0x04000000) >> 26); -+ printk(" port : %d\n", (r_usb_ept_data & 0x03000000) >> 24); -+ printk(" error_code : %d\n", (r_usb_ept_data & 0x00c00000) >> 22); -+ printk(" t_out : %d\n", (r_usb_ept_data & 0x00200000) >> 21); -+ printk(" error_count_out : %d\n", (r_usb_ept_data & 0x00180000) >> 19); -+ printk(" max_len : %d\n", (r_usb_ept_data & 0x0003f800) >> 11); -+ printk(" ep : %d\n", (r_usb_ept_data & 0x00000780) >> 7); -+ printk(" dev : %d\n", (r_usb_ept_data & 0x0000003f)); -+} -+ -+static inline void __dump_ept_data_iso(int epid) -+{ -+ unsigned long flags; -+ __u32 ept_data; -+ -+ if (epid < 0 || epid > 31) { -+ printk("Cannot dump ept data for invalid epid %d\n", epid); -+ return; -+ } -+ -+ local_irq_save(flags); -+ *R_USB_EPT_INDEX = IO_FIELD(R_USB_EPT_INDEX, value, epid); -+ nop(); -+ ept_data = *R_USB_EPT_DATA_ISO; -+ local_irq_restore(flags); -+ -+ printk(" R_USB_EPT_DATA = 0x%x for epid %d :\n", ept_data, epid); -+ if (ept_data == 0) { -+ /* No need for more detailed printing. */ -+ return; -+ } -+ printk(" valid : %d\n", IO_EXTRACT(R_USB_EPT_DATA_ISO, valid, -+ ept_data)); -+ printk(" port : %d\n", IO_EXTRACT(R_USB_EPT_DATA_ISO, port, -+ ept_data)); -+ printk(" error_code : %d\n", IO_EXTRACT(R_USB_EPT_DATA_ISO, error_code, -+ ept_data)); -+ printk(" max_len : %d\n", IO_EXTRACT(R_USB_EPT_DATA_ISO, max_len, -+ ept_data)); -+ printk(" ep : %d\n", IO_EXTRACT(R_USB_EPT_DATA_ISO, ep, -+ ept_data)); -+ printk(" dev : %d\n", IO_EXTRACT(R_USB_EPT_DATA_ISO, dev, -+ ept_data)); -+} -+ -+static inline void __dump_ept_data_list(void) -+{ -+ int i; -+ -+ printk("Dumping the whole R_USB_EPT_DATA list\n"); -+ -+ for (i = 0; i < 32; i++) { -+ __dump_ept_data(i); -+ } -+} -+ -+static void debug_epid(int epid) { -+ int i; -+ -+ if(epid_isoc(epid)) { -+ __dump_ept_data_iso(epid); -+ } else { -+ __dump_ept_data(epid); -+ } -+ -+ printk("Bulk:\n"); -+ for(i = 0; i < 32; i++) { -+ if(IO_EXTRACT(USB_EP_command, epid, TxBulkEPList[i].command) == -+ epid) { -+ printk("%d: ", i); __dump_ep_desc(&(TxBulkEPList[i])); -+ } -+ } -+ -+ printk("Ctrl:\n"); -+ for(i = 0; i < 32; i++) { -+ if(IO_EXTRACT(USB_EP_command, epid, TxCtrlEPList[i].command) == -+ epid) { -+ printk("%d: ", i); __dump_ep_desc(&(TxCtrlEPList[i])); -+ } -+ } -+ -+ printk("Intr:\n"); -+ for(i = 0; i < MAX_INTR_INTERVAL; i++) { -+ if(IO_EXTRACT(USB_EP_command, epid, TxIntrEPList[i].command) == -+ epid) { -+ printk("%d: ", i); __dump_ep_desc(&(TxIntrEPList[i])); -+ } -+ } -+ -+ printk("Isoc:\n"); -+ for(i = 0; i < 32; i++) { -+ if(IO_EXTRACT(USB_EP_command, epid, TxIsocEPList[i].command) == -+ epid) { -+ printk("%d: ", i); __dump_ep_desc(&(TxIsocEPList[i])); -+ } -+ } -+ -+ __dump_ept_data_list(); -+ __dump_ep_list(PIPE_INTERRUPT); -+ printk("\n\n"); -+} -+ -+ -+ -+char* hcd_status_to_str(__u8 bUsbStatus) { -+ static char hcd_status_str[128]; -+ hcd_status_str[0] = '\0'; -+ if(bUsbStatus & IO_STATE(R_USB_STATUS, ourun, yes)) { -+ strcat(hcd_status_str, "ourun "); -+ } -+ if(bUsbStatus & IO_STATE(R_USB_STATUS, perror, yes)) { -+ strcat(hcd_status_str, "perror "); -+ } -+ if(bUsbStatus & IO_STATE(R_USB_STATUS, device_mode, yes)) { -+ strcat(hcd_status_str, "device_mode "); -+ } -+ if(bUsbStatus & IO_STATE(R_USB_STATUS, host_mode, yes)) { -+ strcat(hcd_status_str, "host_mode "); -+ } -+ if(bUsbStatus & IO_STATE(R_USB_STATUS, started, yes)) { -+ strcat(hcd_status_str, "started "); -+ } -+ if(bUsbStatus & IO_STATE(R_USB_STATUS, running, yes)) { -+ strcat(hcd_status_str, "running "); -+ } -+ return hcd_status_str; -+} -+ -+ -+char* sblist_to_str(struct USB_SB_Desc* sb_desc) { -+ static char sblist_to_str_buff[128]; -+ char tmp[32], tmp2[32]; -+ sblist_to_str_buff[0] = '\0'; -+ while(sb_desc != NULL) { -+ switch(IO_EXTRACT(USB_SB_command, tt, sb_desc->command)) { -+ case 0: sprintf(tmp, "zout"); break; -+ case 1: sprintf(tmp, "in"); break; -+ case 2: sprintf(tmp, "out"); break; -+ case 3: sprintf(tmp, "setup"); break; -+ } -+ sprintf(tmp2, "(%s %d)", tmp, sb_desc->sw_len); -+ strcat(sblist_to_str_buff, tmp2); -+ if(sb_desc->next != 0) { -+ sb_desc = phys_to_virt(sb_desc->next); -+ } else { -+ sb_desc = NULL; -+ } -+ } -+ return sblist_to_str_buff; -+} -+ -+char* port_status_to_str(__u16 wPortStatus) { -+ static char port_status_str[128]; -+ port_status_str[0] = '\0'; -+ if(wPortStatus & IO_STATE(R_USB_RH_PORT_STATUS_1, connected, yes)) { -+ strcat(port_status_str, "connected "); -+ } -+ if(wPortStatus & IO_STATE(R_USB_RH_PORT_STATUS_1, enabled, yes)) { -+ strcat(port_status_str, "enabled "); -+ } -+ if(wPortStatus & IO_STATE(R_USB_RH_PORT_STATUS_1, suspended, yes)) { -+ strcat(port_status_str, "suspended "); -+ } -+ if(wPortStatus & IO_STATE(R_USB_RH_PORT_STATUS_1, reset, yes)) { -+ strcat(port_status_str, "reset "); -+ } -+ if(wPortStatus & IO_STATE(R_USB_RH_PORT_STATUS_1, speed, full)) { -+ strcat(port_status_str, "full-speed "); -+ } else { -+ strcat(port_status_str, "low-speed "); -+ } -+ return port_status_str; -+} -+ -+ -+char* endpoint_to_str(struct usb_endpoint_descriptor *ed) { -+ static char endpoint_to_str_buff[128]; -+ char tmp[32]; -+ int epnum = ed->bEndpointAddress & 0x0F; -+ int dir = ed->bEndpointAddress & 0x80; -+ int type = ed->bmAttributes & 0x03; -+ endpoint_to_str_buff[0] = '\0'; -+ sprintf(endpoint_to_str_buff, "ep:%d ", epnum); -+ switch(type) { -+ case 0: -+ sprintf(tmp, " ctrl"); -+ break; -+ case 1: -+ sprintf(tmp, " isoc"); -+ break; -+ case 2: -+ sprintf(tmp, " bulk"); -+ break; -+ case 3: -+ sprintf(tmp, " intr"); -+ break; -+ } -+ strcat(endpoint_to_str_buff, tmp); -+ if(dir) { -+ sprintf(tmp, " in"); -+ } else { -+ sprintf(tmp, " out"); -+ } -+ strcat(endpoint_to_str_buff, tmp); -+ -+ return endpoint_to_str_buff; -+} -+ -+/* Debug helper functions for Transfer Controller */ -+char* pipe_to_str(unsigned int pipe) { -+ static char pipe_to_str_buff[128]; -+ char tmp[64]; -+ sprintf(pipe_to_str_buff, "dir:%s", str_dir(pipe)); -+ sprintf(tmp, " type:%s", str_type(pipe)); -+ strcat(pipe_to_str_buff, tmp); -+ -+ sprintf(tmp, " dev:%d", usb_pipedevice(pipe)); -+ strcat(pipe_to_str_buff, tmp); -+ sprintf(tmp, " ep:%d", usb_pipeendpoint(pipe)); -+ strcat(pipe_to_str_buff, tmp); -+ return pipe_to_str_buff; -+} -+ -+ -+#define USB_DEBUG_DESC 1 -+ -+#ifdef USB_DEBUG_DESC -+#define dump_in_desc(x) __dump_in_desc(x) -+#define dump_sb_desc(...) __dump_sb_desc(...) -+#define dump_ep_desc(x) __dump_ep_desc(x) -+#define dump_ept_data(x) __dump_ept_data(x) -+#else -+#define dump_in_desc(...) do {} while (0) -+#define dump_sb_desc(...) do {} while (0) -+#define dump_ep_desc(...) do {} while (0) -+#endif -+ -+ -+/* Uncomment this to enable massive function call trace -+ #define USB_DEBUG_TRACE */ -+//#define USB_DEBUG_TRACE 1 -+ -+#ifdef USB_DEBUG_TRACE -+#define DBFENTER (printk(": Entering: %s\n", __FUNCTION__)) -+#define DBFEXIT (printk(": Exiting: %s\n", __FUNCTION__)) -+#else -+#define DBFENTER do {} while (0) -+#define DBFEXIT do {} while (0) -+#endif -+ -+#define CHECK_ALIGN(x) if (((__u32)(x)) & 0x00000003) \ -+{panic("Alignment check (DWORD) failed at %s:%s:%d\n", __FILE__, __FUNCTION__, __LINE__);} -+ -+/* Most helpful debugging aid */ -+#define ASSERT(expr) ((void) ((expr) ? 0 : (err("assert failed at: %s %d",__FUNCTION__, __LINE__)))) -+ -+ -+/***************************************************************************/ -+/***************************************************************************/ -+/* Forward declarations */ -+/***************************************************************************/ -+/***************************************************************************/ -+void crisv10_hcd_epid_attn_irq(struct crisv10_irq_reg *reg); -+void crisv10_hcd_port_status_irq(struct crisv10_irq_reg *reg); -+void crisv10_hcd_ctl_status_irq(struct crisv10_irq_reg *reg); -+void crisv10_hcd_isoc_eof_irq(struct crisv10_irq_reg *reg); -+ -+void rh_port_status_change(__u16[]); -+int rh_clear_port_feature(__u8, __u16); -+int rh_set_port_feature(__u8, __u16); -+static void rh_disable_port(unsigned int port); -+ -+static void check_finished_bulk_tx_epids(struct usb_hcd *hcd, -+ int timer); -+ -+//static int tc_setup_epid(struct usb_host_endpoint *ep, struct urb *urb, -+// int mem_flags); -+static int tc_setup_epid(struct urb *urb, int mem_flags); -+static void tc_free_epid(struct usb_host_endpoint *ep); -+static int tc_allocate_epid(void); -+static void tc_finish_urb(struct usb_hcd *hcd, struct urb *urb, int status); -+static void tc_finish_urb_later(struct usb_hcd *hcd, struct urb *urb, -+ int status); -+ -+static int urb_priv_create(struct usb_hcd *hcd, struct urb *urb, int epid, -+ int mem_flags); -+static void urb_priv_free(struct usb_hcd *hcd, struct urb *urb); -+ -+static inline struct urb *urb_list_first(int epid); -+static inline void urb_list_add(struct urb *urb, int epid, -+ int mem_flags); -+static inline urb_entry_t *urb_list_entry(struct urb *urb, int epid); -+static inline void urb_list_del(struct urb *urb, int epid); -+static inline void urb_list_move_last(struct urb *urb, int epid); -+static inline struct urb *urb_list_next(struct urb *urb, int epid); -+ -+int create_sb_for_urb(struct urb *urb, int mem_flags); -+int init_intr_urb(struct urb *urb, int mem_flags); -+ -+static inline void etrax_epid_set(__u8 index, __u32 data); -+static inline void etrax_epid_clear_error(__u8 index); -+static inline void etrax_epid_set_toggle(__u8 index, __u8 dirout, -+ __u8 toggle); -+static inline __u8 etrax_epid_get_toggle(__u8 index, __u8 dirout); -+static inline __u32 etrax_epid_get(__u8 index); -+ -+/* We're accessing the same register position in Etrax so -+ when we do full access the internal difference doesn't matter */ -+#define etrax_epid_iso_set(index, data) etrax_epid_set(index, data) -+#define etrax_epid_iso_get(index) etrax_epid_get(index) -+ -+ -+//static void tc_dma_process_isoc_urb(struct urb *urb); -+static void tc_dma_process_queue(int epid); -+static void tc_dma_unlink_intr_urb(struct urb *urb); -+static irqreturn_t tc_dma_tx_interrupt(int irq, void *vhc); -+static irqreturn_t tc_dma_rx_interrupt(int irq, void *vhc); -+ -+static void tc_bulk_start_timer_func(unsigned long dummy); -+static void tc_bulk_eot_timer_func(unsigned long dummy); -+ -+ -+/*************************************************************/ -+/*************************************************************/ -+/* Host Controler Driver block */ -+/*************************************************************/ -+/*************************************************************/ -+ -+/* HCD operations */ -+static irqreturn_t crisv10_hcd_top_irq(int irq, void*); -+static int crisv10_hcd_reset(struct usb_hcd *); -+static int crisv10_hcd_start(struct usb_hcd *); -+static void crisv10_hcd_stop(struct usb_hcd *); -+#ifdef CONFIG_PM -+static int crisv10_hcd_suspend(struct device *, u32, u32); -+static int crisv10_hcd_resume(struct device *, u32); -+#endif /* CONFIG_PM */ -+static int crisv10_hcd_get_frame(struct usb_hcd *); -+ -+//static int tc_urb_enqueue(struct usb_hcd *, struct usb_host_endpoint *ep, struct urb *, gfp_t mem_flags); -+static int tc_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags); -+//static int tc_urb_dequeue(struct usb_hcd *, struct urb *); -+static int tc_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status); -+static void tc_endpoint_disable(struct usb_hcd *, struct usb_host_endpoint *ep); -+ -+static int rh_status_data_request(struct usb_hcd *, char *); -+static int rh_control_request(struct usb_hcd *, u16, u16, u16, char*, u16); -+ -+#ifdef CONFIG_PM -+static int crisv10_hcd_hub_suspend(struct usb_hcd *); -+static int crisv10_hcd_hub_resume(struct usb_hcd *); -+#endif /* CONFIG_PM */ -+#ifdef CONFIG_USB_OTG -+static int crisv10_hcd_start_port_reset(struct usb_hcd *, unsigned); -+#endif /* CONFIG_USB_OTG */ -+ -+/* host controller driver interface */ -+static const struct hc_driver crisv10_hc_driver = -+ { -+ .description = hc_name, -+ .product_desc = product_desc, -+ .hcd_priv_size = sizeof(struct crisv10_hcd), -+ -+ /* Attaching IRQ handler manualy in probe() */ -+ /* .irq = crisv10_hcd_irq, */ -+ -+ .flags = HCD_USB11, -+ -+ /* called to init HCD and root hub */ -+ .reset = crisv10_hcd_reset, -+ .start = crisv10_hcd_start, -+ -+ /* cleanly make HCD stop writing memory and doing I/O */ -+ .stop = crisv10_hcd_stop, -+ -+ /* return current frame number */ -+ .get_frame_number = crisv10_hcd_get_frame, -+ -+ -+ /* Manage i/o requests via the Transfer Controller */ -+ .urb_enqueue = tc_urb_enqueue, -+ .urb_dequeue = tc_urb_dequeue, -+ -+ /* hw synch, freeing endpoint resources that urb_dequeue can't */ -+ .endpoint_disable = tc_endpoint_disable, -+ -+ -+ /* Root Hub support */ -+ .hub_status_data = rh_status_data_request, -+ .hub_control = rh_control_request, -+#ifdef CONFIG_PM -+ .hub_suspend = rh_suspend_request, -+ .hub_resume = rh_resume_request, -+#endif /* CONFIG_PM */ -+#ifdef CONFIG_USB_OTG -+ .start_port_reset = crisv10_hcd_start_port_reset, -+#endif /* CONFIG_USB_OTG */ -+ }; -+ -+ -+/* -+ * conversion between pointers to a hcd and the corresponding -+ * crisv10_hcd -+ */ -+ -+static inline struct crisv10_hcd *hcd_to_crisv10_hcd(struct usb_hcd *hcd) -+{ -+ return (struct crisv10_hcd *) hcd->hcd_priv; -+} -+ -+static inline struct usb_hcd *crisv10_hcd_to_hcd(struct crisv10_hcd *hcd) -+{ -+ return container_of((void *) hcd, struct usb_hcd, hcd_priv); -+} -+ -+/* check if specified port is in use */ -+static inline int port_in_use(unsigned int port) -+{ -+ return ports & (1 << port); -+} -+ -+/* number of ports in use */ -+static inline unsigned int num_ports(void) -+{ -+ unsigned int i, num = 0; -+ for (i = 0; i < USB_ROOT_HUB_PORTS; i++) -+ if (port_in_use(i)) -+ num++; -+ return num; -+} -+ -+/* map hub port number to the port number used internally by the HC */ -+static inline unsigned int map_port(unsigned int port) -+{ -+ unsigned int i, num = 0; -+ for (i = 0; i < USB_ROOT_HUB_PORTS; i++) -+ if (port_in_use(i)) -+ if (++num == port) -+ return i; -+ return -1; -+} -+ -+/* size of descriptors in slab cache */ -+#ifndef MAX -+#define MAX(x, y) ((x) > (y) ? (x) : (y)) -+#endif -+ -+ -+/******************************************************************/ -+/* Hardware Interrupt functions */ -+/******************************************************************/ -+ -+/* Fast interrupt handler for HC */ -+static irqreturn_t crisv10_hcd_top_irq(int irq, void *vcd) -+{ -+ struct usb_hcd *hcd = vcd; -+ struct crisv10_irq_reg reg; -+ __u32 irq_mask; -+ unsigned long flags; -+ -+ DBFENTER; -+ -+ ASSERT(hcd != NULL); -+ reg.hcd = hcd; -+ -+ /* Turn of other interrupts while handling these sensitive cases */ -+ local_irq_save(flags); -+ -+ /* Read out which interrupts that are flaged */ -+ irq_mask = *R_USB_IRQ_MASK_READ; -+ reg.r_usb_irq_mask_read = irq_mask; -+ -+ /* Reading R_USB_STATUS clears the ctl_status interrupt. Note that -+ R_USB_STATUS must be read before R_USB_EPID_ATTN since reading the latter -+ clears the ourun and perror fields of R_USB_STATUS. */ -+ reg.r_usb_status = *R_USB_STATUS; -+ -+ /* Reading R_USB_EPID_ATTN clears the iso_eof, bulk_eot and epid_attn -+ interrupts. */ -+ reg.r_usb_epid_attn = *R_USB_EPID_ATTN; -+ -+ /* Reading R_USB_RH_PORT_STATUS_1 and R_USB_RH_PORT_STATUS_2 clears the -+ port_status interrupt. */ -+ reg.r_usb_rh_port_status_1 = *R_USB_RH_PORT_STATUS_1; -+ reg.r_usb_rh_port_status_2 = *R_USB_RH_PORT_STATUS_2; -+ -+ /* Reading R_USB_FM_NUMBER clears the sof interrupt. */ -+ /* Note: the lower 11 bits contain the actual frame number, sent with each -+ sof. */ -+ reg.r_usb_fm_number = *R_USB_FM_NUMBER; -+ -+ /* Interrupts are handled in order of priority. */ -+ if (irq_mask & IO_MASK(R_USB_IRQ_MASK_READ, port_status)) { -+ crisv10_hcd_port_status_irq(®); -+ } -+ if (irq_mask & IO_MASK(R_USB_IRQ_MASK_READ, epid_attn)) { -+ crisv10_hcd_epid_attn_irq(®); -+ } -+ if (irq_mask & IO_MASK(R_USB_IRQ_MASK_READ, ctl_status)) { -+ crisv10_hcd_ctl_status_irq(®); -+ } -+ if (irq_mask & IO_MASK(R_USB_IRQ_MASK_READ, iso_eof)) { -+ crisv10_hcd_isoc_eof_irq(®); -+ } -+ if (irq_mask & IO_MASK(R_USB_IRQ_MASK_READ, bulk_eot)) { -+ /* Update/restart the bulk start timer since obviously the channel is -+ running. */ -+ mod_timer(&bulk_start_timer, jiffies + BULK_START_TIMER_INTERVAL); -+ /* Update/restart the bulk eot timer since we just received an bulk eot -+ interrupt. */ -+ mod_timer(&bulk_eot_timer, jiffies + BULK_EOT_TIMER_INTERVAL); -+ -+ /* Check for finished bulk transfers on epids */ -+ check_finished_bulk_tx_epids(hcd, 0); -+ } -+ local_irq_restore(flags); -+ -+ DBFEXIT; -+ return IRQ_HANDLED; -+} -+ -+ -+void crisv10_hcd_epid_attn_irq(struct crisv10_irq_reg *reg) { -+ struct usb_hcd *hcd = reg->hcd; -+ struct crisv10_urb_priv *urb_priv; -+ int epid; -+ DBFENTER; -+ -+ for (epid = 0; epid < NBR_OF_EPIDS; epid++) { -+ if (test_bit(epid, (void *)®->r_usb_epid_attn)) { -+ struct urb *urb; -+ __u32 ept_data; -+ int error_code; -+ -+ if (epid == DUMMY_EPID || epid == INVALID_EPID) { -+ /* We definitely don't care about these ones. Besides, they are -+ always disabled, so any possible disabling caused by the -+ epid attention interrupt is irrelevant. */ -+ warn("Got epid_attn for INVALID_EPID or DUMMY_EPID (%d).", epid); -+ continue; -+ } -+ -+ if(!epid_inuse(epid)) { -+ irq_err("Epid attention on epid:%d that isn't in use\n", epid); -+ printk("R_USB_STATUS: 0x%x\n", reg->r_usb_status); -+ debug_epid(epid); -+ continue; -+ } -+ -+ /* Note that although there are separate R_USB_EPT_DATA and -+ R_USB_EPT_DATA_ISO registers, they are located at the same address and -+ are of the same size. In other words, this read should be ok for isoc -+ also. */ -+ ept_data = etrax_epid_get(epid); -+ error_code = IO_EXTRACT(R_USB_EPT_DATA, error_code, ept_data); -+ -+ /* Get the active URB for this epid. We blatantly assume -+ that only this URB could have caused the epid attention. */ -+ urb = activeUrbList[epid]; -+ if (urb == NULL) { -+ irq_err("Attention on epid:%d error:%d with no active URB.\n", -+ epid, error_code); -+ printk("R_USB_STATUS: 0x%x\n", reg->r_usb_status); -+ debug_epid(epid); -+ continue; -+ } -+ -+ urb_priv = (struct crisv10_urb_priv *)urb->hcpriv; -+ ASSERT(urb_priv); -+ -+ /* Using IO_STATE_VALUE on R_USB_EPT_DATA should be ok for isoc also. */ -+ if (error_code == IO_STATE_VALUE(R_USB_EPT_DATA, error_code, no_error)) { -+ -+ /* Isoc traffic doesn't have error_count_in/error_count_out. */ -+ if ((usb_pipetype(urb->pipe) != PIPE_ISOCHRONOUS) && -+ (IO_EXTRACT(R_USB_EPT_DATA, error_count_in, ept_data) == 3 || -+ IO_EXTRACT(R_USB_EPT_DATA, error_count_out, ept_data) == 3)) { -+ /* Check if URB allready is marked for late-finish, we can get -+ several 3rd error for Intr traffic when a device is unplugged */ -+ if(urb_priv->later_data == NULL) { -+ /* 3rd error. */ -+ irq_warn("3rd error for epid:%d (%s %s) URB:0x%x[%d]\n", epid, -+ str_dir(urb->pipe), str_type(urb->pipe), -+ (unsigned int)urb, urb_priv->urb_num); -+ -+ tc_finish_urb_later(hcd, urb, -EPROTO); -+ } -+ -+ } else if (reg->r_usb_status & IO_MASK(R_USB_STATUS, perror)) { -+ irq_warn("Perror for epid:%d\n", epid); -+ printk("FM_NUMBER: %d\n", reg->r_usb_fm_number & 0x7ff); -+ printk("R_USB_STATUS: 0x%x\n", reg->r_usb_status); -+ __dump_urb(urb); -+ debug_epid(epid); -+ -+ if (!(ept_data & IO_MASK(R_USB_EPT_DATA, valid))) { -+ /* invalid ep_id */ -+ panic("Perror because of invalid epid." -+ " Deconfigured too early?"); -+ } else { -+ /* past eof1, near eof, zout transfer, setup transfer */ -+ /* Dump the urb and the relevant EP descriptor. */ -+ panic("Something wrong with DMA descriptor contents." -+ " Too much traffic inserted?"); -+ } -+ } else if (reg->r_usb_status & IO_MASK(R_USB_STATUS, ourun)) { -+ /* buffer ourun */ -+ printk("FM_NUMBER: %d\n", reg->r_usb_fm_number & 0x7ff); -+ printk("R_USB_STATUS: 0x%x\n", reg->r_usb_status); -+ __dump_urb(urb); -+ debug_epid(epid); -+ -+ panic("Buffer overrun/underrun for epid:%d. DMA too busy?", epid); -+ } else { -+ irq_warn("Attention on epid:%d (%s %s) with no error code\n", epid, -+ str_dir(urb->pipe), str_type(urb->pipe)); -+ printk("R_USB_STATUS: 0x%x\n", reg->r_usb_status); -+ __dump_urb(urb); -+ debug_epid(epid); -+ } -+ -+ } else if (error_code == IO_STATE_VALUE(R_USB_EPT_DATA, error_code, -+ stall)) { -+ /* Not really a protocol error, just says that the endpoint gave -+ a stall response. Note that error_code cannot be stall for isoc. */ -+ if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { -+ panic("Isoc traffic cannot stall"); -+ } -+ -+ tc_dbg("Stall for epid:%d (%s %s) URB:0x%x\n", epid, -+ str_dir(urb->pipe), str_type(urb->pipe), (unsigned int)urb); -+ tc_finish_urb(hcd, urb, -EPIPE); -+ -+ } else if (error_code == IO_STATE_VALUE(R_USB_EPT_DATA, error_code, -+ bus_error)) { -+ /* Two devices responded to a transaction request. Must be resolved -+ by software. FIXME: Reset ports? */ -+ panic("Bus error for epid %d." -+ " Two devices responded to transaction request\n", -+ epid); -+ -+ } else if (error_code == IO_STATE_VALUE(R_USB_EPT_DATA, error_code, -+ buffer_error)) { -+ /* DMA overrun or underrun. */ -+ irq_warn("Buffer overrun/underrun for epid:%d (%s %s)\n", epid, -+ str_dir(urb->pipe), str_type(urb->pipe)); -+ -+ /* It seems that error_code = buffer_error in -+ R_USB_EPT_DATA/R_USB_EPT_DATA_ISO and ourun = yes in R_USB_STATUS -+ are the same error. */ -+ tc_finish_urb(hcd, urb, -EPROTO); -+ } else { -+ irq_warn("Unknown attention on epid:%d (%s %s)\n", epid, -+ str_dir(urb->pipe), str_type(urb->pipe)); -+ dump_ept_data(epid); -+ } -+ } -+ } -+ DBFEXIT; -+} -+ -+void crisv10_hcd_port_status_irq(struct crisv10_irq_reg *reg) -+{ -+ __u16 port_reg[USB_ROOT_HUB_PORTS]; -+ DBFENTER; -+ port_reg[0] = reg->r_usb_rh_port_status_1; -+ port_reg[1] = reg->r_usb_rh_port_status_2; -+ rh_port_status_change(port_reg); -+ DBFEXIT; -+} -+ -+void crisv10_hcd_isoc_eof_irq(struct crisv10_irq_reg *reg) -+{ -+ int epid; -+ struct urb *urb; -+ struct crisv10_urb_priv *urb_priv; -+ -+ DBFENTER; -+ -+ for (epid = 0; epid < NBR_OF_EPIDS - 1; epid++) { -+ -+ /* Only check epids that are in use, is valid and has SB list */ -+ if (!epid_inuse(epid) || epid == INVALID_EPID || -+ TxIsocEPList[epid].sub == 0 || epid == DUMMY_EPID) { -+ /* Nothing here to see. */ -+ continue; -+ } -+ ASSERT(epid_isoc(epid)); -+ -+ /* Get the active URB for this epid (if any). */ -+ urb = activeUrbList[epid]; -+ if (urb == 0) { -+ isoc_warn("Ignoring NULL urb for epid:%d\n", epid); -+ continue; -+ } -+ if(!epid_out_traffic(epid)) { -+ /* Sanity check. */ -+ ASSERT(usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS); -+ -+ urb_priv = (struct crisv10_urb_priv *)urb->hcpriv; -+ ASSERT(urb_priv); -+ -+ if (urb_priv->urb_state == NOT_STARTED) { -+ /* If ASAP is not set and urb->start_frame is the current frame, -+ start the transfer. */ -+ if (!(urb->transfer_flags & URB_ISO_ASAP) && -+ (urb->start_frame == (*R_USB_FM_NUMBER & 0x7ff))) { -+ /* EP should not be enabled if we're waiting for start_frame */ -+ ASSERT((TxIsocEPList[epid].command & -+ IO_STATE(USB_EP_command, enable, yes)) == 0); -+ -+ isoc_warn("Enabling isoc IN EP descr for epid %d\n", epid); -+ TxIsocEPList[epid].command |= IO_STATE(USB_EP_command, enable, yes); -+ -+ /* This urb is now active. */ -+ urb_priv->urb_state = STARTED; -+ continue; -+ } -+ } -+ } -+ } -+ -+ DBFEXIT; -+} -+ -+void crisv10_hcd_ctl_status_irq(struct crisv10_irq_reg *reg) -+{ -+ struct crisv10_hcd* crisv10_hcd = hcd_to_crisv10_hcd(reg->hcd); -+ -+ DBFENTER; -+ ASSERT(crisv10_hcd); -+ -+ irq_dbg("ctr_status_irq, controller status: %s\n", -+ hcd_status_to_str(reg->r_usb_status)); -+ -+ /* FIXME: What should we do if we get ourun or perror? Dump the EP and SB -+ list for the corresponding epid? */ -+ if (reg->r_usb_status & IO_MASK(R_USB_STATUS, ourun)) { -+ panic("USB controller got ourun."); -+ } -+ if (reg->r_usb_status & IO_MASK(R_USB_STATUS, perror)) { -+ -+ /* Before, etrax_usb_do_intr_recover was called on this epid if it was -+ an interrupt pipe. I don't see how re-enabling all EP descriptors -+ will help if there was a programming error. */ -+ panic("USB controller got perror."); -+ } -+ -+ /* Keep track of USB Controller, if it's running or not */ -+ if(reg->r_usb_status & IO_STATE(R_USB_STATUS, running, yes)) { -+ crisv10_hcd->running = 1; -+ } else { -+ crisv10_hcd->running = 0; -+ } -+ -+ if (reg->r_usb_status & IO_MASK(R_USB_STATUS, device_mode)) { -+ /* We should never operate in device mode. */ -+ panic("USB controller in device mode."); -+ } -+ -+ /* Set the flag to avoid getting "Unlink after no-IRQ? Controller is probably -+ using the wrong IRQ" from hcd_unlink_urb() in drivers/usb/core/hcd.c */ -+ set_bit(HCD_FLAG_SAW_IRQ, ®->hcd->flags); -+ -+ DBFEXIT; -+} -+ -+ -+/******************************************************************/ -+/* Host Controller interface functions */ -+/******************************************************************/ -+ -+static inline void crisv10_ready_wait(void) { -+ volatile int timeout = 10000; -+ /* Check the busy bit of USB controller in Etrax */ -+ while((*R_USB_COMMAND & IO_MASK(R_USB_COMMAND, busy)) && -+ (timeout-- > 0)); -+ if(timeout == 0) { -+ warn("Timeout while waiting for USB controller to be idle\n"); -+ } -+} -+ -+/* reset host controller */ -+static int crisv10_hcd_reset(struct usb_hcd *hcd) -+{ -+ DBFENTER; -+ hcd_dbg(hcd, "reset\n"); -+ -+ -+ /* Reset the USB interface. */ -+ /* -+ *R_USB_COMMAND = -+ IO_STATE(R_USB_COMMAND, port_sel, nop) | -+ IO_STATE(R_USB_COMMAND, port_cmd, reset) | -+ IO_STATE(R_USB_COMMAND, ctrl_cmd, reset); -+ nop(); -+ */ -+ DBFEXIT; -+ return 0; -+} -+ -+/* start host controller */ -+static int crisv10_hcd_start(struct usb_hcd *hcd) -+{ -+ DBFENTER; -+ hcd_dbg(hcd, "start\n"); -+ -+ crisv10_ready_wait(); -+ -+ /* Start processing of USB traffic. */ -+ *R_USB_COMMAND = -+ IO_STATE(R_USB_COMMAND, port_sel, nop) | -+ IO_STATE(R_USB_COMMAND, port_cmd, reset) | -+ IO_STATE(R_USB_COMMAND, ctrl_cmd, host_run); -+ -+ nop(); -+ -+ hcd->state = HC_STATE_RUNNING; -+ -+ DBFEXIT; -+ return 0; -+} -+ -+/* stop host controller */ -+static void crisv10_hcd_stop(struct usb_hcd *hcd) -+{ -+ DBFENTER; -+ hcd_dbg(hcd, "stop\n"); -+ crisv10_hcd_reset(hcd); -+ DBFEXIT; -+} -+ -+/* return the current frame number */ -+static int crisv10_hcd_get_frame(struct usb_hcd *hcd) -+{ -+ DBFENTER; -+ DBFEXIT; -+ return (*R_USB_FM_NUMBER & 0x7ff); -+} -+ -+#ifdef CONFIG_USB_OTG -+ -+static int crisv10_hcd_start_port_reset(struct usb_hcd *hcd, unsigned port) -+{ -+ return 0; /* no-op for now */ -+} -+ -+#endif /* CONFIG_USB_OTG */ -+ -+ -+/******************************************************************/ -+/* Root Hub functions */ -+/******************************************************************/ -+ -+/* root hub status */ -+static const struct usb_hub_status rh_hub_status = -+ { -+ .wHubStatus = 0, -+ .wHubChange = 0, -+ }; -+ -+/* root hub descriptor */ -+static const u8 rh_hub_descr[] = -+ { -+ 0x09, /* bDescLength */ -+ 0x29, /* bDescriptorType */ -+ USB_ROOT_HUB_PORTS, /* bNbrPorts */ -+ 0x00, /* wHubCharacteristics */ -+ 0x00, -+ 0x01, /* bPwrOn2pwrGood */ -+ 0x00, /* bHubContrCurrent */ -+ 0x00, /* DeviceRemovable */ -+ 0xff /* PortPwrCtrlMask */ -+ }; -+ -+/* Actual holder of root hub status*/ -+struct crisv10_rh rh; -+ -+/* Initialize root hub data structures (called from dvdrv_hcd_probe()) */ -+int rh_init(void) { -+ int i; -+ /* Reset port status flags */ -+ for (i = 0; i < USB_ROOT_HUB_PORTS; i++) { -+ rh.wPortChange[i] = 0; -+ rh.wPortStatusPrev[i] = 0; -+ } -+ return 0; -+} -+ -+#define RH_FEAT_MASK ((1<lock); -+ for (i = 1; i <= crisv10_hcd->num_ports; i++) { -+ if (rh.wPortChange[map_port(i)]) { -+ *buf |= (1 << i); -+ rh_dbg("rh_status_data_request, change on port %d: %s Current Status: %s\n", i, -+ port_status_to_str(rh.wPortChange[map_port(i)]), -+ port_status_to_str(rh.wPortStatusPrev[map_port(i)])); -+ } -+ } -+ spin_unlock(&crisv10_hcd->lock); -+ -+// DBFEXIT; -+ -+ return *buf == 0 ? 0 : 1; -+} -+ -+/* Handle a control request for the root hub (called from hcd_driver) */ -+static int rh_control_request(struct usb_hcd *hcd, -+ u16 typeReq, -+ u16 wValue, -+ u16 wIndex, -+ char *buf, -+ u16 wLength) { -+ -+ struct crisv10_hcd *crisv10_hcd = hcd_to_crisv10_hcd(hcd); -+ int retval = 0; -+ int len; -+ DBFENTER; -+ -+ switch (typeReq) { -+ case GetHubDescriptor: -+ rh_dbg("GetHubDescriptor\n"); -+ len = min_t(unsigned int, sizeof rh_hub_descr, wLength); -+ memcpy(buf, rh_hub_descr, len); -+ buf[2] = crisv10_hcd->num_ports; -+ break; -+ case GetHubStatus: -+ rh_dbg("GetHubStatus\n"); -+ len = min_t(unsigned int, sizeof rh_hub_status, wLength); -+ memcpy(buf, &rh_hub_status, len); -+ break; -+ case GetPortStatus: -+ if (!wIndex || wIndex > crisv10_hcd->num_ports) -+ goto error; -+ rh_dbg("GetportStatus, port:%d change:%s status:%s\n", wIndex, -+ port_status_to_str(rh.wPortChange[map_port(wIndex)]), -+ port_status_to_str(rh.wPortStatusPrev[map_port(wIndex)])); -+ *(u16 *) buf = cpu_to_le16(rh.wPortStatusPrev[map_port(wIndex)]); -+ *(u16 *) (buf + 2) = cpu_to_le16(rh.wPortChange[map_port(wIndex)]); -+ break; -+ case SetHubFeature: -+ rh_dbg("SetHubFeature\n"); -+ case ClearHubFeature: -+ rh_dbg("ClearHubFeature\n"); -+ switch (wValue) { -+ case C_HUB_OVER_CURRENT: -+ case C_HUB_LOCAL_POWER: -+ rh_warn("Not implemented hub request:%d \n", typeReq); -+ /* not implemented */ -+ break; -+ default: -+ goto error; -+ } -+ break; -+ case SetPortFeature: -+ if (!wIndex || wIndex > crisv10_hcd->num_ports) -+ goto error; -+ if(rh_set_port_feature(map_port(wIndex), wValue)) -+ goto error; -+ break; -+ case ClearPortFeature: -+ if (!wIndex || wIndex > crisv10_hcd->num_ports) -+ goto error; -+ if(rh_clear_port_feature(map_port(wIndex), wValue)) -+ goto error; -+ break; -+ default: -+ rh_warn("Unknown hub request: %d\n", typeReq); -+ error: -+ retval = -EPIPE; -+ } -+ DBFEXIT; -+ return retval; -+} -+ -+int rh_set_port_feature(__u8 bPort, __u16 wFeature) { -+ __u8 bUsbCommand = 0; -+ switch(wFeature) { -+ case USB_PORT_FEAT_RESET: -+ rh_dbg("SetPortFeature: reset\n"); -+ bUsbCommand |= IO_STATE(R_USB_COMMAND, port_cmd, reset); -+ goto set; -+ break; -+ case USB_PORT_FEAT_SUSPEND: -+ rh_dbg("SetPortFeature: suspend\n"); -+ bUsbCommand |= IO_STATE(R_USB_COMMAND, port_cmd, suspend); -+ goto set; -+ break; -+ case USB_PORT_FEAT_POWER: -+ rh_dbg("SetPortFeature: power\n"); -+ break; -+ case USB_PORT_FEAT_C_CONNECTION: -+ rh_dbg("SetPortFeature: c_connection\n"); -+ break; -+ case USB_PORT_FEAT_C_RESET: -+ rh_dbg("SetPortFeature: c_reset\n"); -+ break; -+ case USB_PORT_FEAT_C_OVER_CURRENT: -+ rh_dbg("SetPortFeature: c_over_current\n"); -+ break; -+ -+ set: -+ /* Select which port via the port_sel field */ -+ bUsbCommand |= IO_FIELD(R_USB_COMMAND, port_sel, bPort+1); -+ -+ /* Make sure the controller isn't busy. */ -+ crisv10_ready_wait(); -+ /* Send out the actual command to the USB controller */ -+ *R_USB_COMMAND = bUsbCommand; -+ -+ /* If port reset then also bring USB controller into running state */ -+ if(wFeature == USB_PORT_FEAT_RESET) { -+ /* Wait a while for controller to first become started after port reset */ -+ udelay(12000); /* 12ms blocking wait */ -+ -+ /* Make sure the controller isn't busy. */ -+ crisv10_ready_wait(); -+ -+ /* If all enabled ports were disabled the host controller goes down into -+ started mode, so we need to bring it back into the running state. -+ (This is safe even if it's already in the running state.) */ -+ *R_USB_COMMAND = -+ IO_STATE(R_USB_COMMAND, port_sel, nop) | -+ IO_STATE(R_USB_COMMAND, port_cmd, reset) | -+ IO_STATE(R_USB_COMMAND, ctrl_cmd, host_run); -+ } -+ -+ break; -+ default: -+ rh_dbg("SetPortFeature: unknown feature\n"); -+ return -1; -+ } -+ return 0; -+} -+ -+int rh_clear_port_feature(__u8 bPort, __u16 wFeature) { -+ switch(wFeature) { -+ case USB_PORT_FEAT_ENABLE: -+ rh_dbg("ClearPortFeature: enable\n"); -+ rh_disable_port(bPort); -+ break; -+ case USB_PORT_FEAT_SUSPEND: -+ rh_dbg("ClearPortFeature: suspend\n"); -+ break; -+ case USB_PORT_FEAT_POWER: -+ rh_dbg("ClearPortFeature: power\n"); -+ break; -+ -+ case USB_PORT_FEAT_C_ENABLE: -+ rh_dbg("ClearPortFeature: c_enable\n"); -+ goto clear; -+ case USB_PORT_FEAT_C_SUSPEND: -+ rh_dbg("ClearPortFeature: c_suspend\n"); -+ goto clear; -+ case USB_PORT_FEAT_C_CONNECTION: -+ rh_dbg("ClearPortFeature: c_connection\n"); -+ goto clear; -+ case USB_PORT_FEAT_C_OVER_CURRENT: -+ rh_dbg("ClearPortFeature: c_over_current\n"); -+ goto clear; -+ case USB_PORT_FEAT_C_RESET: -+ rh_dbg("ClearPortFeature: c_reset\n"); -+ goto clear; -+ clear: -+ rh.wPortChange[bPort] &= ~(1 << (wFeature - 16)); -+ break; -+ default: -+ rh_dbg("ClearPortFeature: unknown feature\n"); -+ return -1; -+ } -+ return 0; -+} -+ -+ -+#ifdef CONFIG_PM -+/* Handle a suspend request for the root hub (called from hcd_driver) */ -+static int rh_suspend_request(struct usb_hcd *hcd) -+{ -+ return 0; /* no-op for now */ -+} -+ -+/* Handle a resume request for the root hub (called from hcd_driver) */ -+static int rh_resume_request(struct usb_hcd *hcd) -+{ -+ return 0; /* no-op for now */ -+} -+#endif /* CONFIG_PM */ -+ -+ -+ -+/* Wrapper function for workaround port disable registers in USB controller */ -+static void rh_disable_port(unsigned int port) { -+ volatile int timeout = 10000; -+ volatile char* usb_portx_disable; -+ switch(port) { -+ case 0: -+ usb_portx_disable = R_USB_PORT1_DISABLE; -+ break; -+ case 1: -+ usb_portx_disable = R_USB_PORT2_DISABLE; -+ break; -+ default: -+ /* Invalid port index */ -+ return; -+ } -+ /* Set disable flag in special register */ -+ *usb_portx_disable = IO_STATE(R_USB_PORT1_DISABLE, disable, yes); -+ /* Wait until not enabled anymore */ -+ while((rh.wPortStatusPrev[port] & -+ IO_STATE(R_USB_RH_PORT_STATUS_1, enabled, yes)) && -+ (timeout-- > 0)); -+ if(timeout == 0) { -+ warn("Timeout while waiting for port %d to become disabled\n", port); -+ } -+ /* clear disable flag in special register */ -+ *usb_portx_disable = IO_STATE(R_USB_PORT1_DISABLE, disable, no); -+ rh_info("Physical port %d disabled\n", port+1); -+} -+ -+ -+/******************************************************************/ -+/* Transfer Controller (TC) functions */ -+/******************************************************************/ -+ -+/* FIXME: Should RX_BUF_SIZE be a config option, or maybe we should adjust it -+ dynamically? -+ To adjust it dynamically we would have to get an interrupt when we reach -+ the end of the rx descriptor list, or when we get close to the end, and -+ then allocate more descriptors. */ -+#define NBR_OF_RX_DESC 512 -+#define RX_DESC_BUF_SIZE 1024 -+#define RX_BUF_SIZE (NBR_OF_RX_DESC * RX_DESC_BUF_SIZE) -+ -+ -+/* Local variables for Transfer Controller */ -+/* --------------------------------------- */ -+ -+/* This is a circular (double-linked) list of the active urbs for each epid. -+ The head is never removed, and new urbs are linked onto the list as -+ urb_entry_t elements. Don't reference urb_list directly; use the wrapper -+ functions instead (which includes spin_locks) */ -+static struct list_head urb_list[NBR_OF_EPIDS]; -+ -+/* Read about the need and usage of this lock in submit_ctrl_urb. */ -+/* Lock for URB lists for each EPID */ -+static spinlock_t urb_list_lock; -+ -+/* Lock for EPID array register (R_USB_EPT_x) in Etrax */ -+static spinlock_t etrax_epid_lock; -+ -+/* Lock for dma8 sub0 handling */ -+static spinlock_t etrax_dma8_sub0_lock; -+ -+/* DMA IN cache bug. Align the DMA IN buffers to 32 bytes, i.e. a cache line. -+ Since RX_DESC_BUF_SIZE is 1024 is a multiple of 32, all rx buffers will be -+ cache aligned. */ -+static volatile unsigned char RxBuf[RX_BUF_SIZE] __attribute__ ((aligned (32))); -+static volatile struct USB_IN_Desc RxDescList[NBR_OF_RX_DESC] __attribute__ ((aligned (4))); -+ -+/* Pointers into RxDescList. */ -+static volatile struct USB_IN_Desc *myNextRxDesc; -+static volatile struct USB_IN_Desc *myLastRxDesc; -+ -+/* A zout transfer makes a memory access at the address of its buf pointer, -+ which means that setting this buf pointer to 0 will cause an access to the -+ flash. In addition to this, setting sw_len to 0 results in a 16/32 bytes -+ (depending on DMA burst size) transfer. -+ Instead, we set it to 1, and point it to this buffer. */ -+static int zout_buffer[4] __attribute__ ((aligned (4))); -+ -+/* Cache for allocating new EP and SB descriptors. */ -+//static kmem_cache_t *usb_desc_cache; -+static struct kmem_cache *usb_desc_cache; -+ -+/* Cache for the data allocated in the isoc descr top half. */ -+//static kmem_cache_t *isoc_compl_cache; -+static struct kmem_cache *isoc_compl_cache; -+ -+/* Cache for the data allocated when delayed finishing of URBs */ -+//static kmem_cache_t *later_data_cache; -+static struct kmem_cache *later_data_cache; -+ -+/* Counter to keep track of how many Isoc EP we have sat up. Used to enable -+ and disable iso_eof interrupt. We only need these interrupts when we have -+ Isoc data endpoints (consumes CPU cycles). -+ FIXME: This could be more fine granular, so this interrupt is only enabled -+ when we have a In Isoc URB not URB_ISO_ASAP flaged queued. */ -+static int isoc_epid_counter; -+ -+/* Protecting wrapper functions for R_USB_EPT_x */ -+/* -------------------------------------------- */ -+static inline void etrax_epid_set(__u8 index, __u32 data) { -+ unsigned long flags; -+ spin_lock_irqsave(&etrax_epid_lock, flags); -+ *R_USB_EPT_INDEX = IO_FIELD(R_USB_EPT_INDEX, value, index); -+ nop(); -+ *R_USB_EPT_DATA = data; -+ spin_unlock_irqrestore(&etrax_epid_lock, flags); -+} -+ -+static inline void etrax_epid_clear_error(__u8 index) { -+ unsigned long flags; -+ spin_lock_irqsave(&etrax_epid_lock, flags); -+ *R_USB_EPT_INDEX = IO_FIELD(R_USB_EPT_INDEX, value, index); -+ nop(); -+ *R_USB_EPT_DATA &= -+ ~(IO_MASK(R_USB_EPT_DATA, error_count_in) | -+ IO_MASK(R_USB_EPT_DATA, error_count_out) | -+ IO_MASK(R_USB_EPT_DATA, error_code)); -+ spin_unlock_irqrestore(&etrax_epid_lock, flags); -+} -+ -+static inline void etrax_epid_set_toggle(__u8 index, __u8 dirout, -+ __u8 toggle) { -+ unsigned long flags; -+ spin_lock_irqsave(&etrax_epid_lock, flags); -+ *R_USB_EPT_INDEX = IO_FIELD(R_USB_EPT_INDEX, value, index); -+ nop(); -+ if(dirout) { -+ *R_USB_EPT_DATA &= ~IO_MASK(R_USB_EPT_DATA, t_out); -+ *R_USB_EPT_DATA |= IO_FIELD(R_USB_EPT_DATA, t_out, toggle); -+ } else { -+ *R_USB_EPT_DATA &= ~IO_MASK(R_USB_EPT_DATA, t_in); -+ *R_USB_EPT_DATA |= IO_FIELD(R_USB_EPT_DATA, t_in, toggle); -+ } -+ spin_unlock_irqrestore(&etrax_epid_lock, flags); -+} -+ -+static inline __u8 etrax_epid_get_toggle(__u8 index, __u8 dirout) { -+ unsigned long flags; -+ __u8 toggle; -+ spin_lock_irqsave(&etrax_epid_lock, flags); -+ *R_USB_EPT_INDEX = IO_FIELD(R_USB_EPT_INDEX, value, index); -+ nop(); -+ if (dirout) { -+ toggle = IO_EXTRACT(R_USB_EPT_DATA, t_out, *R_USB_EPT_DATA); -+ } else { -+ toggle = IO_EXTRACT(R_USB_EPT_DATA, t_in, *R_USB_EPT_DATA); -+ } -+ spin_unlock_irqrestore(&etrax_epid_lock, flags); -+ return toggle; -+} -+ -+ -+static inline __u32 etrax_epid_get(__u8 index) { -+ unsigned long flags; -+ __u32 data; -+ spin_lock_irqsave(&etrax_epid_lock, flags); -+ *R_USB_EPT_INDEX = IO_FIELD(R_USB_EPT_INDEX, value, index); -+ nop(); -+ data = *R_USB_EPT_DATA; -+ spin_unlock_irqrestore(&etrax_epid_lock, flags); -+ return data; -+} -+ -+ -+ -+ -+/* Main functions for Transfer Controller */ -+/* -------------------------------------- */ -+ -+/* Init structs, memories and lists used by Transfer Controller */ -+int tc_init(struct usb_hcd *hcd) { -+ int i; -+ /* Clear software state info for all epids */ -+ memset(epid_state, 0, sizeof(struct etrax_epid) * NBR_OF_EPIDS); -+ -+ /* Set Invalid and Dummy as being in use and disabled */ -+ epid_state[INVALID_EPID].inuse = 1; -+ epid_state[DUMMY_EPID].inuse = 1; -+ epid_state[INVALID_EPID].disabled = 1; -+ epid_state[DUMMY_EPID].disabled = 1; -+ -+ /* Clear counter for how many Isoc epids we have sat up */ -+ isoc_epid_counter = 0; -+ -+ /* Initialize the urb list by initiating a head for each list. -+ Also reset list hodling active URB for each epid */ -+ for (i = 0; i < NBR_OF_EPIDS; i++) { -+ INIT_LIST_HEAD(&urb_list[i]); -+ activeUrbList[i] = NULL; -+ } -+ -+ /* Init lock for URB lists */ -+ spin_lock_init(&urb_list_lock); -+ /* Init lock for Etrax R_USB_EPT register */ -+ spin_lock_init(&etrax_epid_lock); -+ /* Init lock for Etrax dma8 sub0 handling */ -+ spin_lock_init(&etrax_dma8_sub0_lock); -+ -+ /* We use kmem_cache_* to make sure that all DMA desc. are dword aligned */ -+ -+ /* Note that we specify sizeof(struct USB_EP_Desc) as the size, but also -+ allocate SB descriptors from this cache. This is ok since -+ sizeof(struct USB_EP_Desc) == sizeof(struct USB_SB_Desc). */ -+// usb_desc_cache = kmem_cache_create("usb_desc_cache", -+// sizeof(struct USB_EP_Desc), 0, -+// SLAB_HWCACHE_ALIGN, 0, 0); -+ usb_desc_cache = kmem_cache_create( -+ "usb_desc_cache", -+ sizeof(struct USB_EP_Desc), -+ 0, -+ SLAB_HWCACHE_ALIGN, -+ NULL); -+ if(usb_desc_cache == NULL) { -+ return -ENOMEM; -+ } -+ -+ /* Create slab cache for speedy allocation of memory for isoc bottom-half -+ interrupt handling */ -+// isoc_compl_cache = -+// kmem_cache_create("isoc_compl_cache", -+// sizeof(struct crisv10_isoc_complete_data), -+// 0, SLAB_HWCACHE_ALIGN, 0, 0); -+ isoc_compl_cache = kmem_cache_create( -+ "isoc_compl_cache", -+ sizeof(struct crisv10_isoc_complete_data), -+ 0, -+ SLAB_HWCACHE_ALIGN, -+ NULL -+ ); -+ -+ if(isoc_compl_cache == NULL) { -+ return -ENOMEM; -+ } -+ -+ /* Create slab cache for speedy allocation of memory for later URB finish -+ struct */ -+// later_data_cache = -+// kmem_cache_create("later_data_cache", -+// sizeof(struct urb_later_data), -+// 0, SLAB_HWCACHE_ALIGN, 0, 0); -+ -+ later_data_cache = kmem_cache_create( -+ "later_data_cache", -+ sizeof(struct urb_later_data), -+ 0, -+ SLAB_HWCACHE_ALIGN, -+ NULL -+ ); -+ -+ if(later_data_cache == NULL) { -+ return -ENOMEM; -+ } -+ -+ -+ /* Initiate the bulk start timer. */ -+ init_timer(&bulk_start_timer); -+ bulk_start_timer.expires = jiffies + BULK_START_TIMER_INTERVAL; -+ bulk_start_timer.function = tc_bulk_start_timer_func; -+ add_timer(&bulk_start_timer); -+ -+ -+ /* Initiate the bulk eot timer. */ -+ init_timer(&bulk_eot_timer); -+ bulk_eot_timer.expires = jiffies + BULK_EOT_TIMER_INTERVAL; -+ bulk_eot_timer.function = tc_bulk_eot_timer_func; -+ bulk_eot_timer.data = (unsigned long)hcd; -+ add_timer(&bulk_eot_timer); -+ -+ return 0; -+} -+ -+/* Uninitialize all resources used by Transfer Controller */ -+void tc_destroy(void) { -+ -+ /* Destroy all slab cache */ -+ kmem_cache_destroy(usb_desc_cache); -+ kmem_cache_destroy(isoc_compl_cache); -+ kmem_cache_destroy(later_data_cache); -+ -+ /* Remove timers */ -+ del_timer(&bulk_start_timer); -+ del_timer(&bulk_eot_timer); -+} -+ -+static void restart_dma8_sub0(void) { -+ unsigned long flags; -+ spin_lock_irqsave(&etrax_dma8_sub0_lock, flags); -+ /* Verify that the dma is not running */ -+ if ((*R_DMA_CH8_SUB0_CMD & IO_MASK(R_DMA_CH8_SUB0_CMD, cmd)) == 0) { -+ struct USB_EP_Desc *ep = (struct USB_EP_Desc *)phys_to_virt(*R_DMA_CH8_SUB0_EP); -+ while (DUMMY_EPID == IO_EXTRACT(USB_EP_command, epid, ep->command)) { -+ ep = (struct USB_EP_Desc *)phys_to_virt(ep->next); -+ } -+ /* Advance the DMA to the next EP descriptor that is not a DUMMY_EPID. -+ * ep->next is already a physical address. virt_to_phys is needed, see -+ * http://mhonarc.axis.se/dev-etrax/msg08630.html -+ */ -+ //*R_DMA_CH8_SUB0_EP = ep->next; -+ *R_DMA_CH8_SUB0_EP = virt_to_phys(ep); -+ /* Restart the DMA */ -+ *R_DMA_CH8_SUB0_CMD = IO_STATE(R_DMA_CH8_SUB0_CMD, cmd, start); -+ } -+ spin_unlock_irqrestore(&etrax_dma8_sub0_lock, flags); -+} -+ -+/* queue an URB with the transfer controller (called from hcd_driver) */ -+//static int tc_urb_enqueue(struct usb_hcd *hcd, -+// struct usb_host_endpoint *ep, -+// struct urb *urb, -+// gfp_t mem_flags) { -+static int tc_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags) -+{ -+ int epid; -+ int retval; -+// int bustime = 0; -+ int maxpacket; -+ unsigned long flags; -+ struct crisv10_urb_priv *urb_priv; -+ struct crisv10_hcd* crisv10_hcd = hcd_to_crisv10_hcd(hcd); -+ DBFENTER; -+ -+ if(!(crisv10_hcd->running)) { -+ /* The USB Controller is not running, probably because no device is -+ attached. No idea to enqueue URBs then */ -+ tc_warn("Rejected enqueueing of URB:0x%x because no dev attached\n", -+ (unsigned int)urb); -+ return -ENOENT; -+ } -+ -+ maxpacket = usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)); -+ -+ /* hinko ignore usb_pipeisoc */ -+#if 0 -+ /* Special case check for In Isoc transfers. Specification states that each -+ In Isoc transfer consists of one packet and therefore it should fit into -+ the transfer-buffer of an URB. -+ We do the check here to be sure (an invalid scenario can be produced with -+ parameters to the usbtest suite) */ -+ if(usb_pipeisoc(urb->pipe) && usb_pipein(urb->pipe) && -+ (urb->transfer_buffer_length < maxpacket)) { -+ tc_err("Submit In Isoc URB with buffer length:%d to pipe with maxpacketlen: %d\n", urb->transfer_buffer_length, maxpacket); -+ return -EMSGSIZE; -+ } -+ -+ /* Check if there is enough bandwidth for periodic transfer */ -+ if(usb_pipeint(urb->pipe) || usb_pipeisoc(urb->pipe)) { -+ /* only check (and later claim) if not already claimed */ -+ if (urb->bandwidth == 0) { -+ bustime = usb_check_bandwidth(urb->dev, urb); -+ if (bustime < 0) { -+ tc_err("Not enough periodic bandwidth\n"); -+ return -ENOSPC; -+ } -+ } -+ } -+#endif -+ -+ /* Check if there is a epid for URBs destination, if not this function -+ set up one. */ -+ //epid = tc_setup_epid(ep, urb, mem_flags); -+ epid = tc_setup_epid(urb, mem_flags); -+ if (epid < 0) { -+ tc_err("Failed setup epid:%d for URB:0x%x\n", epid, (unsigned int)urb); -+ DBFEXIT; -+ return -ENOMEM; -+ } -+ -+ if(urb == activeUrbList[epid]) { -+ tc_err("Resubmition of allready active URB:0x%x\n", (unsigned int)urb); -+ return -ENXIO; -+ } -+ -+ if(urb_list_entry(urb, epid)) { -+ tc_err("Resubmition of allready queued URB:0x%x\n", (unsigned int)urb); -+ return -ENXIO; -+ } -+ -+ /* If we actively have flaged endpoint as disabled then refuse submition */ -+ if(epid_state[epid].disabled) { -+ return -ENOENT; -+ } -+ -+ /* Allocate and init HC-private data for URB */ -+ if(urb_priv_create(hcd, urb, epid, mem_flags) != 0) { -+ DBFEXIT; -+ return -ENOMEM; -+ } -+ urb_priv = urb->hcpriv; -+ -+ tc_dbg("Enqueue URB:0x%x[%d] epid:%d (%s) bufflen:%d\n", -+ (unsigned int)urb, urb_priv->urb_num, epid, -+ pipe_to_str(urb->pipe), urb->transfer_buffer_length); -+ -+ /* Create and link SBs required for this URB */ -+ retval = create_sb_for_urb(urb, mem_flags); -+ if(retval != 0) { -+ tc_err("Failed to create SBs for URB:0x%x[%d]\n", (unsigned int)urb, -+ urb_priv->urb_num); -+ urb_priv_free(hcd, urb); -+ DBFEXIT; -+ return retval; -+ } -+ -+ /* Init intr EP pool if this URB is a INTR transfer. This pool is later -+ used when inserting EPs in the TxIntrEPList. We do the alloc here -+ so we can't run out of memory later */ -+ if(usb_pipeint(urb->pipe)) { -+ retval = init_intr_urb(urb, mem_flags); -+ if(retval != 0) { -+ tc_warn("Failed to init Intr URB\n"); -+ urb_priv_free(hcd, urb); -+ DBFEXIT; -+ return retval; -+ } -+ } -+ -+ /* Disable other access when inserting USB */ -+ -+ /* BUG on sleeping inside int disabled if using local_irq_save/local_irq_restore -+ * her - because urb_list_add() and tc_dma_process_queue() save irqs again !??! -+ */ -+// local_irq_save(flags); -+ -+ /* hinko ignore usb_pipeisoc */ -+#if 0 -+ /* Claim bandwidth, if needed */ -+ if(bustime) { -+ usb_claim_bandwidth(urb->dev, urb, bustime, 0); -+ } -+ -+ /* Add URB to EP queue */ -+ urb_list_add(urb, epid, mem_flags); -+ -+ if(usb_pipeisoc(urb->pipe)) { -+ /* Special processing of Isoc URBs. */ -+ tc_dma_process_isoc_urb(urb); -+ } else { -+ /* Process EP queue for rest of the URB types (Bulk, Ctrl, Intr) */ -+ tc_dma_process_queue(epid); -+ } -+#endif -+ /* Add URB to EP queue */ -+ urb_list_add(urb, epid, mem_flags); -+ -+ /*hinko link/unlink urb -> ep */ -+ spin_lock_irqsave(&crisv10_hcd->lock, flags); -+ //spin_lock(&crisv10_hcd->lock); -+ retval = usb_hcd_link_urb_to_ep(hcd, urb); -+ if (retval) { -+ spin_unlock_irqrestore(&crisv10_hcd->lock, flags); -+ tc_warn("Failed to link urb to ep\n"); -+ urb_priv_free(hcd, urb); -+ DBFEXIT; -+ return retval; -+ } -+ spin_unlock_irqrestore(&crisv10_hcd->lock, flags); -+ //spin_unlock(&crisv10_hcd->lock); -+ -+ /* Process EP queue for rest of the URB types (Bulk, Ctrl, Intr) */ -+ tc_dma_process_queue(epid); -+ -+// local_irq_restore(flags); -+ -+ DBFEXIT; -+ return 0; -+} -+ -+/* remove an URB from the transfer controller queues (called from hcd_driver)*/ -+//static int tc_urb_dequeue(struct usb_hcd *hcd, struct urb *urb) -+static int tc_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) -+{ -+ struct crisv10_urb_priv *urb_priv; -+ unsigned long flags; -+ int epid; -+ -+ DBFENTER; -+ /* Disable interrupts here since a descriptor interrupt for the isoc epid -+ will modify the sb list. This could possibly be done more granular, but -+ urb_dequeue should not be used frequently anyway. -+ */ -+ local_irq_save(flags); -+ -+ urb_priv = urb->hcpriv; -+ -+ if (!urb_priv) { -+ /* This happens if a device driver calls unlink on an urb that -+ was never submitted (lazy driver) or if the urb was completed -+ while dequeue was being called. */ -+ tc_warn("Dequeing of not enqueued URB:0x%x\n", (unsigned int)urb); -+ local_irq_restore(flags); -+ return 0; -+ } -+ epid = urb_priv->epid; -+ -+ tc_warn("Dequeing %s URB:0x%x[%d] (%s %s epid:%d) status:%d %s\n", -+ (urb == activeUrbList[epid]) ? "active" : "queued", -+ (unsigned int)urb, urb_priv->urb_num, str_dir(urb->pipe), -+ str_type(urb->pipe), epid, urb->status, -+ (urb_priv->later_data) ? "later-sched" : ""); -+ -+ /* For Bulk, Ctrl and Intr are only one URB active at a time. So any URB -+ that isn't active can be dequeued by just removing it from the queue */ -+ if(usb_pipebulk(urb->pipe) || usb_pipecontrol(urb->pipe) || -+ usb_pipeint(urb->pipe)) { -+ -+ /* Check if URB haven't gone further than the queue */ -+ if(urb != activeUrbList[epid]) { -+ ASSERT(urb_priv->later_data == NULL); -+ tc_warn("Dequeing URB:0x%x[%d] (%s %s epid:%d) from queue" -+ " (not active)\n", (unsigned int)urb, urb_priv->urb_num, -+ str_dir(urb->pipe), str_type(urb->pipe), epid); -+ -+ /* Finish the URB with error status from USB core */ -+ tc_finish_urb(hcd, urb, urb->status); -+ local_irq_restore(flags); -+ return 0; -+ } -+ } -+ -+ /* Set URB status to Unlink for handling when interrupt comes. */ -+ urb_priv->urb_state = UNLINK; -+ -+ /* Differentiate dequeing of Bulk and Ctrl from Isoc and Intr */ -+ switch(usb_pipetype(urb->pipe)) { -+ case PIPE_BULK: -+ /* Check if EP still is enabled */ -+ if (TxBulkEPList[epid].command & IO_MASK(USB_EP_command, enable)) { -+ /* The EP was enabled, disable it. */ -+ TxBulkEPList[epid].command &= ~IO_MASK(USB_EP_command, enable); -+ } -+ /* Kicking dummy list out of the party. */ -+ TxBulkEPList[epid].next = virt_to_phys(&TxBulkEPList[(epid + 1) % NBR_OF_EPIDS]); -+ break; -+ case PIPE_CONTROL: -+ /* Check if EP still is enabled */ -+ if (TxCtrlEPList[epid].command & IO_MASK(USB_EP_command, enable)) { -+ /* The EP was enabled, disable it. */ -+ TxCtrlEPList[epid].command &= ~IO_MASK(USB_EP_command, enable); -+ } -+ break; -+ case PIPE_ISOCHRONOUS: -+ /* Disabling, busy-wait and unlinking of Isoc SBs will be done in -+ finish_isoc_urb(). Because there might the case when URB is dequeued -+ but there are other valid URBs waiting */ -+ -+ /* Check if In Isoc EP still is enabled */ -+ if (TxIsocEPList[epid].command & IO_MASK(USB_EP_command, enable)) { -+ /* The EP was enabled, disable it. */ -+ TxIsocEPList[epid].command &= ~IO_MASK(USB_EP_command, enable); -+ } -+ break; -+ case PIPE_INTERRUPT: -+ /* Special care is taken for interrupt URBs. EPs are unlinked in -+ tc_finish_urb */ -+ break; -+ default: -+ break; -+ } -+ -+ /* Asynchronous unlink, finish the URB later from scheduled or other -+ event (data finished, error) */ -+ tc_finish_urb_later(hcd, urb, urb->status); -+ -+ local_irq_restore(flags); -+ DBFEXIT; -+ return 0; -+} -+ -+ -+static void tc_sync_finish_epid(struct usb_hcd *hcd, int epid) { -+ volatile int timeout = 10000; -+ struct urb* urb; -+ struct crisv10_urb_priv* urb_priv; -+ unsigned long flags; -+ -+ volatile struct USB_EP_Desc *first_ep; /* First EP in the list. */ -+ volatile struct USB_EP_Desc *curr_ep; /* Current EP, the iterator. */ -+ volatile struct USB_EP_Desc *next_ep; /* The EP after current. */ -+ -+ int type = epid_state[epid].type; -+ -+ /* Setting this flag will cause enqueue() to return -ENOENT for new -+ submitions on this endpoint and finish_urb() wont process queue further */ -+ epid_state[epid].disabled = 1; -+ -+ switch(type) { -+ case PIPE_BULK: -+ /* Check if EP still is enabled */ -+ if (TxBulkEPList[epid].command & IO_MASK(USB_EP_command, enable)) { -+ /* The EP was enabled, disable it. */ -+ TxBulkEPList[epid].command &= ~IO_MASK(USB_EP_command, enable); -+ tc_warn("sync_finish: Disabling EP for epid:%d\n", epid); -+ -+ /* Do busy-wait until DMA not using this EP descriptor anymore */ -+ while((*R_DMA_CH8_SUB0_EP == -+ virt_to_phys(&TxBulkEPList[epid])) && -+ (timeout-- > 0)); -+ if(timeout == 0) { -+ warn("Timeout while waiting for DMA-TX-Bulk to leave EP for" -+ " epid:%d\n", epid); -+ } -+ } -+ break; -+ -+ case PIPE_CONTROL: -+ /* Check if EP still is enabled */ -+ if (TxCtrlEPList[epid].command & IO_MASK(USB_EP_command, enable)) { -+ /* The EP was enabled, disable it. */ -+ TxCtrlEPList[epid].command &= ~IO_MASK(USB_EP_command, enable); -+ tc_warn("sync_finish: Disabling EP for epid:%d\n", epid); -+ -+ /* Do busy-wait until DMA not using this EP descriptor anymore */ -+ while((*R_DMA_CH8_SUB1_EP == -+ virt_to_phys(&TxCtrlEPList[epid])) && -+ (timeout-- > 0)); -+ if(timeout == 0) { -+ warn("Timeout while waiting for DMA-TX-Ctrl to leave EP for" -+ " epid:%d\n", epid); -+ } -+ } -+ break; -+ -+ case PIPE_INTERRUPT: -+ local_irq_save(flags); -+ /* Disable all Intr EPs belonging to epid */ -+ first_ep = &TxIntrEPList[0]; -+ curr_ep = first_ep; -+ do { -+ next_ep = (struct USB_EP_Desc *)phys_to_virt(curr_ep->next); -+ if (IO_EXTRACT(USB_EP_command, epid, next_ep->command) == epid) { -+ /* Disable EP */ -+ next_ep->command &= ~IO_MASK(USB_EP_command, enable); -+ } -+ curr_ep = phys_to_virt(curr_ep->next); -+ } while (curr_ep != first_ep); -+ -+ local_irq_restore(flags); -+ break; -+ -+ case PIPE_ISOCHRONOUS: -+ /* Check if EP still is enabled */ -+ if (TxIsocEPList[epid].command & IO_MASK(USB_EP_command, enable)) { -+ tc_warn("sync_finish: Disabling Isoc EP for epid:%d\n", epid); -+ /* The EP was enabled, disable it. */ -+ TxIsocEPList[epid].command &= ~IO_MASK(USB_EP_command, enable); -+ -+ while((*R_DMA_CH8_SUB3_EP == virt_to_phys(&TxIsocEPList[epid])) && -+ (timeout-- > 0)); -+ if(timeout == 0) { -+ warn("Timeout while waiting for DMA-TX-Isoc to leave EP for" -+ " epid:%d\n", epid); -+ } -+ } -+ break; -+ } -+ -+ local_irq_save(flags); -+ -+ /* Finish if there is active URB for this endpoint */ -+ if(activeUrbList[epid] != NULL) { -+ urb = activeUrbList[epid]; -+ urb_priv = urb->hcpriv; -+ ASSERT(urb_priv); -+ tc_warn("Sync finish %s URB:0x%x[%d] (%s %s epid:%d) status:%d %s\n", -+ (urb == activeUrbList[epid]) ? "active" : "queued", -+ (unsigned int)urb, urb_priv->urb_num, str_dir(urb->pipe), -+ str_type(urb->pipe), epid, urb->status, -+ (urb_priv->later_data) ? "later-sched" : ""); -+ -+ tc_finish_urb(hcd, activeUrbList[epid], -ENOENT); -+ ASSERT(activeUrbList[epid] == NULL); -+ } -+ -+ /* Finish any queued URBs for this endpoint. There won't be any resubmitions -+ because epid_disabled causes enqueue() to fail for this endpoint */ -+ while((urb = urb_list_first(epid)) != NULL) { -+ urb_priv = urb->hcpriv; -+ ASSERT(urb_priv); -+ -+ tc_warn("Sync finish %s URB:0x%x[%d] (%s %s epid:%d) status:%d %s\n", -+ (urb == activeUrbList[epid]) ? "active" : "queued", -+ (unsigned int)urb, urb_priv->urb_num, str_dir(urb->pipe), -+ str_type(urb->pipe), epid, urb->status, -+ (urb_priv->later_data) ? "later-sched" : ""); -+ -+ tc_finish_urb(hcd, urb, -ENOENT); -+ } -+ epid_state[epid].disabled = 0; -+ local_irq_restore(flags); -+} -+ -+/* free resources associated with an endpoint (called from hcd_driver) */ -+static void tc_endpoint_disable(struct usb_hcd *hcd, -+ struct usb_host_endpoint *ep) { -+ DBFENTER; -+ /* Only free epid if it has been allocated. We get two endpoint_disable -+ requests for ctrl endpoints so ignore the second one */ -+ if(ep->hcpriv != NULL) { -+ struct crisv10_ep_priv *ep_priv = ep->hcpriv; -+ int epid = ep_priv->epid; -+ tc_warn("endpoint_disable ep:0x%x ep-priv:0x%x (%s) (epid:%d freed)\n", -+ (unsigned int)ep, (unsigned int)ep->hcpriv, -+ endpoint_to_str(&(ep->desc)), epid); -+ -+ tc_sync_finish_epid(hcd, epid); -+ -+ ASSERT(activeUrbList[epid] == NULL); -+ ASSERT(list_empty(&urb_list[epid])); -+ -+ tc_free_epid(ep); -+ } else { -+ tc_dbg("endpoint_disable ep:0x%x ep-priv:0x%x (%s)\n", (unsigned int)ep, -+ (unsigned int)ep->hcpriv, endpoint_to_str(&(ep->desc))); -+ } -+ DBFEXIT; -+} -+ -+//static void tc_finish_urb_later_proc(void *data) { -+static void tc_finish_urb_later_proc(struct work_struct *work) { -+ unsigned long flags; -+ //struct urb_later_data* uld = (struct urb_later_data*)data; -+ struct urb_later_data* uld = container_of(work, struct urb_later_data, ws.work); -+ local_irq_save(flags); -+ if(uld->urb == NULL) { -+ late_dbg("Later finish of URB = NULL (allready finished)\n"); -+ } else { -+ struct crisv10_urb_priv* urb_priv = uld->urb->hcpriv; -+ ASSERT(urb_priv); -+ if(urb_priv->urb_num == uld->urb_num) { -+ late_dbg("Later finish of URB:0x%x[%d]\n", (unsigned int)(uld->urb), -+ urb_priv->urb_num); -+ if(uld->status != uld->urb->status) { -+ errno_dbg("Later-finish URB with status:%d, later-status:%d\n", -+ uld->urb->status, uld->status); -+ } -+ if(uld != urb_priv->later_data) { -+ panic("Scheduled uld not same as URBs uld\n"); -+ } -+ tc_finish_urb(uld->hcd, uld->urb, uld->status); -+ } else { -+ late_warn("Ignoring later finish of URB:0x%x[%d]" -+ ", urb_num doesn't match current URB:0x%x[%d]", -+ (unsigned int)(uld->urb), uld->urb_num, -+ (unsigned int)(uld->urb), urb_priv->urb_num); -+ } -+ } -+ local_irq_restore(flags); -+ kmem_cache_free(later_data_cache, uld); -+} -+ -+static void tc_finish_urb_later(struct usb_hcd *hcd, struct urb *urb, -+ int status) { -+ struct crisv10_urb_priv *urb_priv = urb->hcpriv; -+ struct urb_later_data* uld; -+ -+ ASSERT(urb_priv); -+ -+ if(urb_priv->later_data != NULL) { -+ /* Later-finish allready scheduled for this URB, just update status to -+ return when finishing later */ -+ errno_dbg("Later-finish schedule change URB status:%d with new" -+ " status:%d\n", urb_priv->later_data->status, status); -+ -+ urb_priv->later_data->status = status; -+ return; -+ } -+ -+ uld = kmem_cache_alloc(later_data_cache, GFP_ATOMIC); -+ ASSERT(uld); -+ -+ uld->hcd = hcd; -+ uld->urb = urb; -+ uld->urb_num = urb_priv->urb_num; -+ uld->status = status; -+ -+ //INIT_WORK(&uld->ws, tc_finish_urb_later_proc, uld); -+ INIT_DELAYED_WORK(&uld->ws, tc_finish_urb_later_proc); -+ urb_priv->later_data = uld; -+ -+ /* Schedule the finishing of the URB to happen later */ -+ schedule_delayed_work(&uld->ws, LATER_TIMER_DELAY); -+} -+ -+ /* hinko ignore usb_pipeisoc */ -+#if 0 -+static void tc_finish_isoc_urb(struct usb_hcd *hcd, struct urb *urb, -+ int status); -+#endif -+ -+static void tc_finish_urb(struct usb_hcd *hcd, struct urb *urb, int status) { -+ struct crisv10_hcd* crisv10_hcd = hcd_to_crisv10_hcd(hcd); -+ struct crisv10_urb_priv *urb_priv = urb->hcpriv; -+ int epid; -+ char toggle; -+ int urb_num; -+ unsigned long flags; -+ -+ DBFENTER; -+ ASSERT(urb_priv != NULL); -+ epid = urb_priv->epid; -+ urb_num = urb_priv->urb_num; -+ -+ if(urb != activeUrbList[epid]) { -+ if(urb_list_entry(urb, epid)) { -+ /* Remove this URB from the list. Only happens when URB are finished -+ before having been processed (dequeing) */ -+ urb_list_del(urb, epid); -+ } else { -+ tc_warn("Finishing of URB:0x%x[%d] neither active or in queue for" -+ " epid:%d\n", (unsigned int)urb, urb_num, epid); -+ } -+ } -+ -+ /* Cancel any pending later-finish of this URB */ -+ if(urb_priv->later_data) { -+ urb_priv->later_data->urb = NULL; -+ } -+ -+ /* For an IN pipe, we always set the actual length, regardless of whether -+ there was an error or not (which means the device driver can use the data -+ if it wants to). */ -+ if(usb_pipein(urb->pipe)) { -+ urb->actual_length = urb_priv->rx_offset; -+ } else { -+ /* Set actual_length for OUT urbs also; the USB mass storage driver seems -+ to want that. */ -+ if (status == 0 && urb->status == -EINPROGRESS) { -+ urb->actual_length = urb->transfer_buffer_length; -+ } else { -+ /* We wouldn't know of any partial writes if there was an error. */ -+ urb->actual_length = 0; -+ } -+ } -+ -+ -+ /* URB status mangling */ -+ if(urb->status == -EINPROGRESS) { -+ /* The USB core hasn't changed the status, let's set our finish status */ -+ urb->status = status; -+ -+ if ((status == 0) && (urb->transfer_flags & URB_SHORT_NOT_OK) && -+ usb_pipein(urb->pipe) && -+ (urb->actual_length != urb->transfer_buffer_length)) { -+ /* URB_SHORT_NOT_OK means that short reads (shorter than the endpoint's -+ max length) is to be treated as an error. */ -+ errno_dbg("Finishing URB:0x%x[%d] with SHORT_NOT_OK flag and short" -+ " data:%d\n", (unsigned int)urb, urb_num, -+ urb->actual_length); -+ urb->status = -EREMOTEIO; -+ } -+ -+ if(urb_priv->urb_state == UNLINK) { -+ /* URB has been requested to be unlinked asynchronously */ -+ urb->status = -ECONNRESET; -+ errno_dbg("Fixing unlink status of URB:0x%x[%d] to:%d\n", -+ (unsigned int)urb, urb_num, urb->status); -+ } -+ } else { -+ /* The USB Core wants to signal some error via the URB, pass it through */ -+ } -+ -+ /* hinko ignore usb_pipeisoc */ -+#if 0 -+ /* use completely different finish function for Isoc URBs */ -+ if(usb_pipeisoc(urb->pipe)) { -+ tc_finish_isoc_urb(hcd, urb, status); -+ return; -+ } -+#endif -+ -+ /* Do special unlinking of EPs for Intr traffic */ -+ if(usb_pipeint(urb->pipe)) { -+ tc_dma_unlink_intr_urb(urb); -+ } -+ -+ /* hinko ignore usb_pipeisoc */ -+#if 0 -+ /* Release allocated bandwidth for periodic transfers */ -+ if(usb_pipeint(urb->pipe) || usb_pipeisoc(urb->pipe)) -+ usb_release_bandwidth(urb->dev, urb, 0); -+#endif -+ -+ /* This URB is active on EP */ -+ if(urb == activeUrbList[epid]) { -+ /* We need to fiddle with the toggle bits because the hardware doesn't do -+ it for us. */ -+ toggle = etrax_epid_get_toggle(epid, usb_pipeout(urb->pipe)); -+ usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), -+ usb_pipeout(urb->pipe), toggle); -+ -+ /* Checks for Ctrl and Bulk EPs */ -+ switch(usb_pipetype(urb->pipe)) { -+ case PIPE_BULK: -+ /* Check so Bulk EP realy is disabled before finishing active URB */ -+ ASSERT((TxBulkEPList[epid].command & IO_MASK(USB_EP_command, enable)) == -+ IO_STATE(USB_EP_command, enable, no)); -+ /* Disable sub-pointer for EP to avoid next tx_interrupt() to -+ process Bulk EP. */ -+ TxBulkEPList[epid].sub = 0; -+ /* No need to wait for the DMA before changing the next pointer. -+ The modulo NBR_OF_EPIDS isn't actually necessary, since we will never use -+ the last one (INVALID_EPID) for actual traffic. */ -+ TxBulkEPList[epid].next = -+ virt_to_phys(&TxBulkEPList[(epid + 1) % NBR_OF_EPIDS]); -+ break; -+ case PIPE_CONTROL: -+ /* Check so Ctrl EP realy is disabled before finishing active URB */ -+ ASSERT((TxCtrlEPList[epid].command & IO_MASK(USB_EP_command, enable)) == -+ IO_STATE(USB_EP_command, enable, no)); -+ /* Disable sub-pointer for EP to avoid next tx_interrupt() to -+ process Ctrl EP. */ -+ TxCtrlEPList[epid].sub = 0; -+ break; -+ } -+ } -+ -+ /* Free HC-private URB data*/ -+ urb_priv_free(hcd, urb); -+ -+ if(urb->status) { -+ errno_dbg("finish_urb (URB:0x%x[%d] %s %s) (data:%d) status:%d\n", -+ (unsigned int)urb, urb_num, str_dir(urb->pipe), -+ str_type(urb->pipe), urb->actual_length, urb->status); -+ } else { -+ tc_dbg("finish_urb (URB:0x%x[%d] %s %s) (data:%d) status:%d\n", -+ (unsigned int)urb, urb_num, str_dir(urb->pipe), -+ str_type(urb->pipe), urb->actual_length, urb->status); -+ } -+ -+ /* If we just finished an active URB, clear active pointer. */ -+ if (urb == activeUrbList[epid]) { -+ /* Make URB not active on EP anymore */ -+ activeUrbList[epid] = NULL; -+ -+ if(urb->status == 0) { -+ /* URB finished sucessfully, process queue to see if there are any more -+ URBs waiting before we call completion function.*/ -+ if(crisv10_hcd->running) { -+ /* Only process queue if USB controller is running */ -+ tc_dma_process_queue(epid); -+ } else { -+ tc_warn("No processing of queue for epid:%d, USB Controller not" -+ " running\n", epid); -+ } -+ } -+ } -+ -+ /* Hand the URB from HCD to its USB device driver, using its completion -+ functions */ -+// usb_hcd_giveback_urb (hcd, urb); -+ /** -+ * usb_hcd_unlink_urb_from_ep - remove an URB from its endpoint queue -+ * @hcd: host controller to which @urb was submitted -+ * @urb: URB being unlinked -+ * -+ * Host controller drivers should call this routine before calling -+ * usb_hcd_giveback_urb(). The HCD's private spinlock must be held and -+ * interrupts must be disabled. The actions carried out here are required -+ * for URB completion. -+ */ -+ -+ /*hinko link/unlink urb -> ep */ -+ //spin_lock(&crisv10_hcd->lock); -+ spin_lock_irqsave(&crisv10_hcd->lock, flags); -+ usb_hcd_unlink_urb_from_ep(hcd, urb); -+ usb_hcd_giveback_urb(hcd, urb, status); -+ //spin_unlock(&crisv10_hcd->lock); -+ spin_unlock_irqrestore(&crisv10_hcd->lock, flags); -+ -+ /* Check the queue once more if the URB returned with error, because we -+ didn't do it before the completion function because the specification -+ states that the queue should not restart until all it's unlinked -+ URBs have been fully retired, with the completion functions run */ -+ if(crisv10_hcd->running) { -+ /* Only process queue if USB controller is running */ -+ tc_dma_process_queue(epid); -+ } else { -+ tc_warn("No processing of queue for epid:%d, USB Controller not running\n", -+ epid); -+ } -+ -+ DBFEXIT; -+} -+ -+ /* hinko ignore usb_pipeisoc */ -+#if 0 -+static void tc_finish_isoc_urb(struct usb_hcd *hcd, struct urb *urb, -+ int status) { -+ struct crisv10_urb_priv *urb_priv = urb->hcpriv; -+ int epid, i; -+ volatile int timeout = 10000; -+ -+ ASSERT(urb_priv); -+ epid = urb_priv->epid; -+ -+ ASSERT(usb_pipeisoc(urb->pipe)); -+ -+ /* Set that all isoc packets have status and length set before -+ completing the urb. */ -+ for (i = urb_priv->isoc_packet_counter; i < urb->number_of_packets; i++){ -+ urb->iso_frame_desc[i].actual_length = 0; -+ urb->iso_frame_desc[i].status = -EPROTO; -+ } -+ -+ /* Check if the URB is currently active (done or error) */ -+ if(urb == activeUrbList[epid]) { -+ /* Check if there are another In Isoc URB queued for this epid */ -+ if (!list_empty(&urb_list[epid])&& !epid_state[epid].disabled) { -+ /* Move it from queue to active and mark it started so Isoc transfers -+ won't be interrupted. -+ All Isoc URBs data transfers are already added to DMA lists so we -+ don't have to insert anything in DMA lists here. */ -+ activeUrbList[epid] = urb_list_first(epid); -+ ((struct crisv10_urb_priv *)(activeUrbList[epid]->hcpriv))->urb_state = -+ STARTED; -+ urb_list_del(activeUrbList[epid], epid); -+ -+ if(urb->status) { -+ errno_dbg("finish_isoc_urb (URB:0x%x[%d] %s %s) (%d of %d packets)" -+ " status:%d, new waiting URB:0x%x[%d]\n", -+ (unsigned int)urb, urb_priv->urb_num, str_dir(urb->pipe), -+ str_type(urb->pipe), urb_priv->isoc_packet_counter, -+ urb->number_of_packets, urb->status, -+ (unsigned int)activeUrbList[epid], -+ ((struct crisv10_urb_priv *)(activeUrbList[epid]->hcpriv))->urb_num); -+ } -+ -+ } else { /* No other URB queued for this epid */ -+ if(urb->status) { -+ errno_dbg("finish_isoc_urb (URB:0x%x[%d] %s %s) (%d of %d packets)" -+ " status:%d, no new URB waiting\n", -+ (unsigned int)urb, urb_priv->urb_num, str_dir(urb->pipe), -+ str_type(urb->pipe), urb_priv->isoc_packet_counter, -+ urb->number_of_packets, urb->status); -+ } -+ -+ /* Check if EP is still enabled, then shut it down. */ -+ if (TxIsocEPList[epid].command & IO_MASK(USB_EP_command, enable)) { -+ isoc_dbg("Isoc EP enabled for epid:%d, disabling it\n", epid); -+ -+ /* Should only occur for In Isoc EPs where SB isn't consumed. */ -+ ASSERT(usb_pipein(urb->pipe)); -+ -+ /* Disable it and wait for it to stop */ -+ TxIsocEPList[epid].command &= ~IO_MASK(USB_EP_command, enable); -+ -+ /* Ah, the luxury of busy-wait. */ -+ while((*R_DMA_CH8_SUB3_EP == virt_to_phys(&TxIsocEPList[epid])) && -+ (timeout-- > 0)); -+ if(timeout == 0) { -+ warn("Timeout while waiting for DMA-TX-Isoc to leave EP for epid:%d\n", epid); -+ } -+ } -+ -+ /* Unlink SB to say that epid is finished. */ -+ TxIsocEPList[epid].sub = 0; -+ TxIsocEPList[epid].hw_len = 0; -+ -+ /* No URB active for EP anymore */ -+ activeUrbList[epid] = NULL; -+ } -+ } else { /* Finishing of not active URB (queued up with SBs thought) */ -+ isoc_warn("finish_isoc_urb (URB:0x%x %s) (%d of %d packets) status:%d," -+ " SB queued but not active\n", -+ (unsigned int)urb, str_dir(urb->pipe), -+ urb_priv->isoc_packet_counter, urb->number_of_packets, -+ urb->status); -+ if(usb_pipeout(urb->pipe)) { -+ /* Finishing of not yet active Out Isoc URB needs unlinking of SBs. */ -+ struct USB_SB_Desc *iter_sb, *prev_sb, *next_sb; -+ -+ iter_sb = TxIsocEPList[epid].sub ? -+ phys_to_virt(TxIsocEPList[epid].sub) : 0; -+ prev_sb = 0; -+ -+ /* SB that is linked before this URBs first SB */ -+ while (iter_sb && (iter_sb != urb_priv->first_sb)) { -+ prev_sb = iter_sb; -+ iter_sb = iter_sb->next ? phys_to_virt(iter_sb->next) : 0; -+ } -+ -+ if (iter_sb == 0) { -+ /* Unlink of the URB currently being transmitted. */ -+ prev_sb = 0; -+ iter_sb = TxIsocEPList[epid].sub ? phys_to_virt(TxIsocEPList[epid].sub) : 0; -+ } -+ -+ while (iter_sb && (iter_sb != urb_priv->last_sb)) { -+ iter_sb = iter_sb->next ? phys_to_virt(iter_sb->next) : 0; -+ } -+ -+ if (iter_sb) { -+ next_sb = iter_sb->next ? phys_to_virt(iter_sb->next) : 0; -+ } else { -+ /* This should only happen if the DMA has completed -+ processing the SB list for this EP while interrupts -+ are disabled. */ -+ isoc_dbg("Isoc urb not found, already sent?\n"); -+ next_sb = 0; -+ } -+ if (prev_sb) { -+ prev_sb->next = next_sb ? virt_to_phys(next_sb) : 0; -+ } else { -+ TxIsocEPList[epid].sub = next_sb ? virt_to_phys(next_sb) : 0; -+ } -+ } -+ } -+ -+ /* Free HC-private URB data*/ -+ urb_priv_free(hcd, urb); -+ -+ usb_release_bandwidth(urb->dev, urb, 0); -+ -+ /* Hand the URB from HCD to its USB device driver, using its completion -+ functions */ -+ usb_hcd_giveback_urb (hcd, urb); -+} -+#endif -+ -+static __u32 urb_num = 0; -+ -+/* allocate and initialize URB private data */ -+static int urb_priv_create(struct usb_hcd *hcd, struct urb *urb, int epid, -+ int mem_flags) { -+ struct crisv10_urb_priv *urb_priv; -+ -+ urb_priv = kmalloc(sizeof *urb_priv, mem_flags); -+ if (!urb_priv) -+ return -ENOMEM; -+ memset(urb_priv, 0, sizeof *urb_priv); -+ -+ urb_priv->epid = epid; -+ urb_priv->urb_state = NOT_STARTED; -+ -+ urb->hcpriv = urb_priv; -+ /* Assign URB a sequence number, and increment counter */ -+ urb_priv->urb_num = urb_num; -+ urb_num++; -+ return 0; -+} -+ -+/* free URB private data */ -+static void urb_priv_free(struct usb_hcd *hcd, struct urb *urb) { -+ int i; -+ struct crisv10_urb_priv *urb_priv = urb->hcpriv; -+ ASSERT(urb_priv != 0); -+ -+ /* Check it has any SBs linked that needs to be freed*/ -+ if(urb_priv->first_sb != NULL) { -+ struct USB_SB_Desc *next_sb, *first_sb, *last_sb; -+ int i = 0; -+ first_sb = urb_priv->first_sb; -+ last_sb = urb_priv->last_sb; -+ ASSERT(last_sb); -+ while(first_sb != last_sb) { -+ next_sb = (struct USB_SB_Desc *)phys_to_virt(first_sb->next); -+ kmem_cache_free(usb_desc_cache, first_sb); -+ first_sb = next_sb; -+ i++; -+ } -+ kmem_cache_free(usb_desc_cache, last_sb); -+ i++; -+ } -+ -+ /* Check if it has any EPs in its Intr pool that also needs to be freed */ -+ if(urb_priv->intr_ep_pool_length > 0) { -+ for(i = 0; i < urb_priv->intr_ep_pool_length; i++) { -+ kfree(urb_priv->intr_ep_pool[i]); -+ } -+ /* -+ tc_dbg("Freed %d EPs from URB:0x%x EP pool\n", -+ urb_priv->intr_ep_pool_length, (unsigned int)urb); -+ */ -+ } -+ -+ kfree(urb_priv); -+ urb->hcpriv = NULL; -+} -+ -+static int ep_priv_create(struct usb_host_endpoint *ep, int mem_flags) { -+ struct crisv10_ep_priv *ep_priv; -+ -+ ep_priv = kmalloc(sizeof *ep_priv, mem_flags); -+ if (!ep_priv) -+ return -ENOMEM; -+ memset(ep_priv, 0, sizeof *ep_priv); -+ -+ ep->hcpriv = ep_priv; -+ return 0; -+} -+ -+static void ep_priv_free(struct usb_host_endpoint *ep) { -+ struct crisv10_ep_priv *ep_priv = ep->hcpriv; -+ ASSERT(ep_priv); -+ kfree(ep_priv); -+ ep->hcpriv = NULL; -+} -+ -+/* EPID handling functions, managing EP-list in Etrax through wrappers */ -+/* ------------------------------------------------------------------- */ -+ -+/* Sets up a new EPID for an endpoint or returns existing if found */ -+//static int tc_setup_epid(struct usb_host_endpoint *ep, struct urb *urb, -+// int mem_flags) { -+static int tc_setup_epid(struct urb *urb, int mem_flags) -+{ -+ int epid; -+ char devnum, endpoint, out_traffic, slow; -+ int maxlen; -+ __u32 epid_data; -+ struct usb_host_endpoint *ep = urb->ep; -+ struct crisv10_ep_priv *ep_priv = ep->hcpriv; -+ -+ DBFENTER; -+ -+ /* Check if a valid epid already is setup for this endpoint */ -+ if(ep_priv != NULL) { -+ return ep_priv->epid; -+ } -+ -+ /* We must find and initiate a new epid for this urb. */ -+ epid = tc_allocate_epid(); -+ -+ if (epid == -1) { -+ /* Failed to allocate a new epid. */ -+ DBFEXIT; -+ return epid; -+ } -+ -+ /* We now have a new epid to use. Claim it. */ -+ epid_state[epid].inuse = 1; -+ -+ /* Init private data for new endpoint */ -+ if(ep_priv_create(ep, mem_flags) != 0) { -+ return -ENOMEM; -+ } -+ ep_priv = ep->hcpriv; -+ ep_priv->epid = epid; -+ -+ devnum = usb_pipedevice(urb->pipe); -+ endpoint = usb_pipeendpoint(urb->pipe); -+ slow = (urb->dev->speed == USB_SPEED_LOW); -+ maxlen = usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)); -+ -+ if (usb_pipetype(urb->pipe) == PIPE_CONTROL) { -+ /* We want both IN and OUT control traffic to be put on the same -+ EP/SB list. */ -+ out_traffic = 1; -+ } else { -+ out_traffic = usb_pipeout(urb->pipe); -+ } -+ -+ if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { -+ epid_data = IO_STATE(R_USB_EPT_DATA_ISO, valid, yes) | -+ /* FIXME: Change any to the actual port? */ -+ IO_STATE(R_USB_EPT_DATA_ISO, port, any) | -+ IO_FIELD(R_USB_EPT_DATA_ISO, max_len, maxlen) | -+ IO_FIELD(R_USB_EPT_DATA_ISO, ep, endpoint) | -+ IO_FIELD(R_USB_EPT_DATA_ISO, dev, devnum); -+ etrax_epid_iso_set(epid, epid_data); -+ } else { -+ epid_data = IO_STATE(R_USB_EPT_DATA, valid, yes) | -+ IO_FIELD(R_USB_EPT_DATA, low_speed, slow) | -+ /* FIXME: Change any to the actual port? */ -+ IO_STATE(R_USB_EPT_DATA, port, any) | -+ IO_FIELD(R_USB_EPT_DATA, max_len, maxlen) | -+ IO_FIELD(R_USB_EPT_DATA, ep, endpoint) | -+ IO_FIELD(R_USB_EPT_DATA, dev, devnum); -+ etrax_epid_set(epid, epid_data); -+ } -+ -+ epid_state[epid].out_traffic = out_traffic; -+ epid_state[epid].type = usb_pipetype(urb->pipe); -+ -+ tc_warn("Setting up ep:0x%x epid:%d (addr:%d endp:%d max_len:%d %s %s %s)\n", -+ (unsigned int)ep, epid, devnum, endpoint, maxlen, -+ str_type(urb->pipe), out_traffic ? "out" : "in", -+ slow ? "low" : "full"); -+ -+ /* Enable Isoc eof interrupt if we set up the first Isoc epid */ -+ if(usb_pipeisoc(urb->pipe)) { -+ isoc_epid_counter++; -+ if(isoc_epid_counter == 1) { -+ isoc_warn("Enabled Isoc eof interrupt\n"); -+ *R_USB_IRQ_MASK_SET |= IO_STATE(R_USB_IRQ_MASK_SET, iso_eof, set); -+ } -+ } -+ -+ DBFEXIT; -+ return epid; -+} -+ -+static void tc_free_epid(struct usb_host_endpoint *ep) { -+ unsigned long flags; -+ struct crisv10_ep_priv *ep_priv = ep->hcpriv; -+ int epid; -+ volatile int timeout = 10000; -+ -+ DBFENTER; -+ -+ if (ep_priv == NULL) { -+ tc_warn("Trying to free unused epid on ep:0x%x\n", (unsigned int)ep); -+ DBFEXIT; -+ return; -+ } -+ -+ epid = ep_priv->epid; -+ -+ /* Disable Isoc eof interrupt if we free the last Isoc epid */ -+ if(epid_isoc(epid)) { -+ ASSERT(isoc_epid_counter > 0); -+ isoc_epid_counter--; -+ if(isoc_epid_counter == 0) { -+ *R_USB_IRQ_MASK_SET &= ~IO_STATE(R_USB_IRQ_MASK_SET, iso_eof, set); -+ isoc_warn("Disabled Isoc eof interrupt\n"); -+ } -+ } -+ -+ /* Take lock manualy instead of in epid_x_x wrappers, -+ because we need to be polling here */ -+ spin_lock_irqsave(&etrax_epid_lock, flags); -+ -+ *R_USB_EPT_INDEX = IO_FIELD(R_USB_EPT_INDEX, value, epid); -+ nop(); -+ while((*R_USB_EPT_DATA & IO_MASK(R_USB_EPT_DATA, hold)) && -+ (timeout-- > 0)); -+ if(timeout == 0) { -+ warn("Timeout while waiting for epid:%d to drop hold\n", epid); -+ } -+ /* This will, among other things, set the valid field to 0. */ -+ *R_USB_EPT_DATA = 0; -+ spin_unlock_irqrestore(&etrax_epid_lock, flags); -+ -+ /* Free resource in software state info list */ -+ epid_state[epid].inuse = 0; -+ -+ /* Free private endpoint data */ -+ ep_priv_free(ep); -+ -+ DBFEXIT; -+} -+ -+static int tc_allocate_epid(void) { -+ int i; -+ DBFENTER; -+ for (i = 0; i < NBR_OF_EPIDS; i++) { -+ if (!epid_inuse(i)) { -+ DBFEXIT; -+ return i; -+ } -+ } -+ -+ tc_warn("Found no free epids\n"); -+ DBFEXIT; -+ return -1; -+} -+ -+ -+/* Wrappers around the list functions (include/linux/list.h). */ -+/* ---------------------------------------------------------- */ -+static inline int __urb_list_empty(int epid) { -+ int retval; -+ retval = list_empty(&urb_list[epid]); -+ return retval; -+} -+ -+/* Returns first urb for this epid, or NULL if list is empty. */ -+static inline struct urb *urb_list_first(int epid) { -+ unsigned long flags; -+ struct urb *first_urb = 0; -+ spin_lock_irqsave(&urb_list_lock, flags); -+ if (!__urb_list_empty(epid)) { -+ /* Get the first urb (i.e. head->next). */ -+ urb_entry_t *urb_entry = list_entry((&urb_list[epid])->next, urb_entry_t, list); -+ first_urb = urb_entry->urb; -+ } -+ spin_unlock_irqrestore(&urb_list_lock, flags); -+ return first_urb; -+} -+ -+/* Adds an urb_entry last in the list for this epid. */ -+static inline void urb_list_add(struct urb *urb, int epid, int mem_flags) { -+ unsigned long flags; -+ urb_entry_t *urb_entry = (urb_entry_t *)kmalloc(sizeof(urb_entry_t), mem_flags); -+ ASSERT(urb_entry); -+ -+ urb_entry->urb = urb; -+ spin_lock_irqsave(&urb_list_lock, flags); -+ list_add_tail(&urb_entry->list, &urb_list[epid]); -+ spin_unlock_irqrestore(&urb_list_lock, flags); -+} -+ -+/* Search through the list for an element that contains this urb. (The list -+ is expected to be short and the one we are about to delete will often be -+ the first in the list.) -+ Should be protected by spin_locks in calling function */ -+static inline urb_entry_t *__urb_list_entry(struct urb *urb, int epid) { -+ struct list_head *entry; -+ struct list_head *tmp; -+ urb_entry_t *urb_entry; -+ -+ list_for_each_safe(entry, tmp, &urb_list[epid]) { -+ urb_entry = list_entry(entry, urb_entry_t, list); -+ ASSERT(urb_entry); -+ ASSERT(urb_entry->urb); -+ -+ if (urb_entry->urb == urb) { -+ return urb_entry; -+ } -+ } -+ return 0; -+} -+ -+/* Same function as above but for global use. Protects list by spinlock */ -+static inline urb_entry_t *urb_list_entry(struct urb *urb, int epid) { -+ unsigned long flags; -+ urb_entry_t *urb_entry; -+ spin_lock_irqsave(&urb_list_lock, flags); -+ urb_entry = __urb_list_entry(urb, epid); -+ spin_unlock_irqrestore(&urb_list_lock, flags); -+ return (urb_entry); -+} -+ -+/* Delete an urb from the list. */ -+static inline void urb_list_del(struct urb *urb, int epid) { -+ unsigned long flags; -+ urb_entry_t *urb_entry; -+ -+ /* Delete entry and free. */ -+ spin_lock_irqsave(&urb_list_lock, flags); -+ urb_entry = __urb_list_entry(urb, epid); -+ ASSERT(urb_entry); -+ -+ list_del(&urb_entry->list); -+ spin_unlock_irqrestore(&urb_list_lock, flags); -+ kfree(urb_entry); -+} -+ -+/* Move an urb to the end of the list. */ -+static inline void urb_list_move_last(struct urb *urb, int epid) { -+ unsigned long flags; -+ urb_entry_t *urb_entry; -+ -+ spin_lock_irqsave(&urb_list_lock, flags); -+ urb_entry = __urb_list_entry(urb, epid); -+ ASSERT(urb_entry); -+ -+ list_del(&urb_entry->list); -+ list_add_tail(&urb_entry->list, &urb_list[epid]); -+ spin_unlock_irqrestore(&urb_list_lock, flags); -+} -+ -+/* Get the next urb in the list. */ -+static inline struct urb *urb_list_next(struct urb *urb, int epid) { -+ unsigned long flags; -+ urb_entry_t *urb_entry; -+ -+ spin_lock_irqsave(&urb_list_lock, flags); -+ urb_entry = __urb_list_entry(urb, epid); -+ ASSERT(urb_entry); -+ -+ if (urb_entry->list.next != &urb_list[epid]) { -+ struct list_head *elem = urb_entry->list.next; -+ urb_entry = list_entry(elem, urb_entry_t, list); -+ spin_unlock_irqrestore(&urb_list_lock, flags); -+ return urb_entry->urb; -+ } else { -+ spin_unlock_irqrestore(&urb_list_lock, flags); -+ return NULL; -+ } -+} -+ -+struct USB_EP_Desc* create_ep(int epid, struct USB_SB_Desc* sb_desc, -+ int mem_flags) { -+ struct USB_EP_Desc *ep_desc; -+ ep_desc = (struct USB_EP_Desc *) kmem_cache_alloc(usb_desc_cache, mem_flags); -+ if(ep_desc == NULL) -+ return NULL; -+ memset(ep_desc, 0, sizeof(struct USB_EP_Desc)); -+ -+ ep_desc->hw_len = 0; -+ ep_desc->command = (IO_FIELD(USB_EP_command, epid, epid) | -+ IO_STATE(USB_EP_command, enable, yes)); -+ if(sb_desc == NULL) { -+ ep_desc->sub = 0; -+ } else { -+ ep_desc->sub = virt_to_phys(sb_desc); -+ } -+ return ep_desc; -+} -+ -+#define TT_ZOUT 0 -+#define TT_IN 1 -+#define TT_OUT 2 -+#define TT_SETUP 3 -+ -+#define CMD_EOL IO_STATE(USB_SB_command, eol, yes) -+#define CMD_INTR IO_STATE(USB_SB_command, intr, yes) -+#define CMD_FULL IO_STATE(USB_SB_command, full, yes) -+ -+/* Allocation and setup of a generic SB. Used to create SETUP, OUT and ZOUT -+ SBs. Also used by create_sb_in() to avoid same allocation procedure at two -+ places */ -+struct USB_SB_Desc* create_sb(struct USB_SB_Desc* sb_prev, int tt, void* data, -+ int datalen, int mem_flags) { -+ struct USB_SB_Desc *sb_desc; -+ sb_desc = (struct USB_SB_Desc*)kmem_cache_alloc(usb_desc_cache, mem_flags); -+ if(sb_desc == NULL) -+ return NULL; -+ memset(sb_desc, 0, sizeof(struct USB_SB_Desc)); -+ -+ sb_desc->command = IO_FIELD(USB_SB_command, tt, tt) | -+ IO_STATE(USB_SB_command, eot, yes); -+ -+ sb_desc->sw_len = datalen; -+ if(data != NULL) { -+ sb_desc->buf = virt_to_phys(data); -+ } else { -+ sb_desc->buf = 0; -+ } -+ if(sb_prev != NULL) { -+ sb_prev->next = virt_to_phys(sb_desc); -+ } -+ return sb_desc; -+} -+ -+/* Creates a copy of an existing SB by allocation space for it and copy -+ settings */ -+struct USB_SB_Desc* create_sb_copy(struct USB_SB_Desc* sb_orig, int mem_flags) { -+ struct USB_SB_Desc *sb_desc; -+ sb_desc = (struct USB_SB_Desc*)kmem_cache_alloc(usb_desc_cache, mem_flags); -+ if(sb_desc == NULL) -+ return NULL; -+ -+ memcpy(sb_desc, sb_orig, sizeof(struct USB_SB_Desc)); -+ return sb_desc; -+} -+ -+/* A specific create_sb function for creation of in SBs. This is due to -+ that datalen in In SBs shows how many packets we are expecting. It also -+ sets up the rem field to show if how many bytes we expect in last packet -+ if it's not a full one */ -+struct USB_SB_Desc* create_sb_in(struct USB_SB_Desc* sb_prev, int datalen, -+ int maxlen, int mem_flags) { -+ struct USB_SB_Desc *sb_desc; -+ sb_desc = create_sb(sb_prev, TT_IN, NULL, -+ datalen ? (datalen - 1) / maxlen + 1 : 0, mem_flags); -+ if(sb_desc == NULL) -+ return NULL; -+ sb_desc->command |= IO_FIELD(USB_SB_command, rem, datalen % maxlen); -+ return sb_desc; -+} -+ -+void set_sb_cmds(struct USB_SB_Desc *sb_desc, __u16 flags) { -+ sb_desc->command |= flags; -+} -+ -+int create_sb_for_urb(struct urb *urb, int mem_flags) { -+ int is_out = !usb_pipein(urb->pipe); -+ int type = usb_pipetype(urb->pipe); -+ int maxlen = usb_maxpacket(urb->dev, urb->pipe, is_out); -+ int buf_len = urb->transfer_buffer_length; -+ void *buf = buf_len > 0 ? urb->transfer_buffer : NULL; -+ struct USB_SB_Desc *sb_desc = NULL; -+ -+ struct crisv10_urb_priv *urb_priv = (struct crisv10_urb_priv *)urb->hcpriv; -+ ASSERT(urb_priv != NULL); -+ -+ switch(type) { -+ case PIPE_CONTROL: -+ /* Setup stage */ -+ sb_desc = create_sb(NULL, TT_SETUP, urb->setup_packet, 8, mem_flags); -+ if(sb_desc == NULL) -+ return -ENOMEM; -+ set_sb_cmds(sb_desc, CMD_FULL); -+ -+ /* Attach first SB to URB */ -+ urb_priv->first_sb = sb_desc; -+ -+ if (is_out) { /* Out Control URB */ -+ /* If this Control OUT transfer has an optional data stage we add -+ an OUT token before the mandatory IN (status) token */ -+ if ((buf_len > 0) && buf) { -+ sb_desc = create_sb(sb_desc, TT_OUT, buf, buf_len, mem_flags); -+ if(sb_desc == NULL) -+ return -ENOMEM; -+ set_sb_cmds(sb_desc, CMD_FULL); -+ } -+ -+ /* Status stage */ -+ /* The data length has to be exactly 1. This is due to a requirement -+ of the USB specification that a host must be prepared to receive -+ data in the status phase */ -+ sb_desc = create_sb(sb_desc, TT_IN, NULL, 1, mem_flags); -+ if(sb_desc == NULL) -+ return -ENOMEM; -+ } else { /* In control URB */ -+ /* Data stage */ -+ sb_desc = create_sb_in(sb_desc, buf_len, maxlen, mem_flags); -+ if(sb_desc == NULL) -+ return -ENOMEM; -+ -+ /* Status stage */ -+ /* Read comment at zout_buffer declaration for an explanation to this. */ -+ sb_desc = create_sb(sb_desc, TT_ZOUT, &zout_buffer[0], 1, mem_flags); -+ if(sb_desc == NULL) -+ return -ENOMEM; -+ /* Set descriptor interrupt flag for in URBs so we can finish URB after -+ zout-packet has been sent */ -+ set_sb_cmds(sb_desc, CMD_INTR | CMD_FULL); -+ } -+ /* Set end-of-list flag in last SB */ -+ set_sb_cmds(sb_desc, CMD_EOL); -+ /* Attach last SB to URB */ -+ urb_priv->last_sb = sb_desc; -+ break; -+ -+ case PIPE_BULK: -+ if (is_out) { /* Out Bulk URB */ -+ sb_desc = create_sb(NULL, TT_OUT, buf, buf_len, mem_flags); -+ if(sb_desc == NULL) -+ return -ENOMEM; -+ /* The full field is set to yes, even if we don't actually check that -+ this is a full-length transfer (i.e., that transfer_buffer_length % -+ maxlen = 0). -+ Setting full prevents the USB controller from sending an empty packet -+ in that case. However, if URB_ZERO_PACKET was set we want that. */ -+ if (!(urb->transfer_flags & URB_ZERO_PACKET)) { -+ set_sb_cmds(sb_desc, CMD_FULL); -+ } -+ } else { /* In Bulk URB */ -+ sb_desc = create_sb_in(NULL, buf_len, maxlen, mem_flags); -+ if(sb_desc == NULL) -+ return -ENOMEM; -+ } -+ /* Set end-of-list flag for last SB */ -+ set_sb_cmds(sb_desc, CMD_EOL); -+ -+ /* Attach SB to URB */ -+ urb_priv->first_sb = sb_desc; -+ urb_priv->last_sb = sb_desc; -+ break; -+ -+ case PIPE_INTERRUPT: -+ if(is_out) { /* Out Intr URB */ -+ sb_desc = create_sb(NULL, TT_OUT, buf, buf_len, mem_flags); -+ if(sb_desc == NULL) -+ return -ENOMEM; -+ -+ /* The full field is set to yes, even if we don't actually check that -+ this is a full-length transfer (i.e., that transfer_buffer_length % -+ maxlen = 0). -+ Setting full prevents the USB controller from sending an empty packet -+ in that case. However, if URB_ZERO_PACKET was set we want that. */ -+ if (!(urb->transfer_flags & URB_ZERO_PACKET)) { -+ set_sb_cmds(sb_desc, CMD_FULL); -+ } -+ /* Only generate TX interrupt if it's a Out URB*/ -+ set_sb_cmds(sb_desc, CMD_INTR); -+ -+ } else { /* In Intr URB */ -+ sb_desc = create_sb_in(NULL, buf_len, maxlen, mem_flags); -+ if(sb_desc == NULL) -+ return -ENOMEM; -+ } -+ /* Set end-of-list flag for last SB */ -+ set_sb_cmds(sb_desc, CMD_EOL); -+ -+ /* Attach SB to URB */ -+ urb_priv->first_sb = sb_desc; -+ urb_priv->last_sb = sb_desc; -+ -+ break; -+ case PIPE_ISOCHRONOUS: -+ if(is_out) { /* Out Isoc URB */ -+ int i; -+ if(urb->number_of_packets == 0) { -+ tc_err("Can't create SBs for Isoc URB with zero packets\n"); -+ return -EPIPE; -+ } -+ /* Create one SB descriptor for each packet and link them together. */ -+ for(i = 0; i < urb->number_of_packets; i++) { -+ if (urb->iso_frame_desc[i].length > 0) { -+ -+ sb_desc = create_sb(sb_desc, TT_OUT, urb->transfer_buffer + -+ urb->iso_frame_desc[i].offset, -+ urb->iso_frame_desc[i].length, mem_flags); -+ if(sb_desc == NULL) -+ return -ENOMEM; -+ -+ /* Check if it's a full length packet */ -+ if (urb->iso_frame_desc[i].length == -+ usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe))) { -+ set_sb_cmds(sb_desc, CMD_FULL); -+ } -+ -+ } else { /* zero length packet */ -+ sb_desc = create_sb(sb_desc, TT_ZOUT, &zout_buffer[0], 1, mem_flags); -+ if(sb_desc == NULL) -+ return -ENOMEM; -+ set_sb_cmds(sb_desc, CMD_FULL); -+ } -+ /* Attach first SB descriptor to URB */ -+ if (i == 0) { -+ urb_priv->first_sb = sb_desc; -+ } -+ } -+ /* Set interrupt and end-of-list flags in last SB */ -+ set_sb_cmds(sb_desc, CMD_INTR | CMD_EOL); -+ /* Attach last SB descriptor to URB */ -+ urb_priv->last_sb = sb_desc; -+ tc_dbg("Created %d out SBs for Isoc URB:0x%x\n", -+ urb->number_of_packets, (unsigned int)urb); -+ } else { /* In Isoc URB */ -+ /* Actual number of packets is not relevant for periodic in traffic as -+ long as it is more than zero. Set to 1 always. */ -+ sb_desc = create_sb(sb_desc, TT_IN, NULL, 1, mem_flags); -+ if(sb_desc == NULL) -+ return -ENOMEM; -+ /* Set end-of-list flags for SB */ -+ set_sb_cmds(sb_desc, CMD_EOL); -+ -+ /* Attach SB to URB */ -+ urb_priv->first_sb = sb_desc; -+ urb_priv->last_sb = sb_desc; -+ } -+ break; -+ default: -+ tc_err("Unknown pipe-type\n"); -+ return -EPIPE; -+ break; -+ } -+ return 0; -+} -+ -+int init_intr_urb(struct urb *urb, int mem_flags) { -+ struct crisv10_urb_priv *urb_priv = (struct crisv10_urb_priv *)urb->hcpriv; -+ struct USB_EP_Desc* ep_desc; -+ int interval; -+ int i; -+ int ep_count; -+ -+ ASSERT(urb_priv != NULL); -+ ASSERT(usb_pipeint(urb->pipe)); -+ /* We can't support interval longer than amount of eof descriptors in -+ TxIntrEPList */ -+ if(urb->interval > MAX_INTR_INTERVAL) { -+ tc_err("Interrupt interval %dms too big (max: %dms)\n", urb->interval, -+ MAX_INTR_INTERVAL); -+ return -EINVAL; -+ } -+ -+ /* We assume that the SB descriptors already have been setup */ -+ ASSERT(urb_priv->first_sb != NULL); -+ -+ /* Round of the interval to 2^n, it is obvious that this code favours -+ smaller numbers, but that is actually a good thing */ -+ /* FIXME: The "rounding error" for larger intervals will be quite -+ large. For in traffic this shouldn't be a problem since it will only -+ mean that we "poll" more often. */ -+ interval = urb->interval; -+ for (i = 0; interval; i++) { -+ interval = interval >> 1; -+ } -+ urb_priv->interval = 1 << (i - 1); -+ -+ /* We can only have max interval for Out Interrupt due to that we can only -+ handle one linked in EP for a certain epid in the Intr descr array at the -+ time. The USB Controller in the Etrax 100LX continues to process Intr EPs -+ so we have no way of knowing which one that caused the actual transfer if -+ we have several linked in. */ -+ if(usb_pipeout(urb->pipe)) { -+ urb_priv->interval = MAX_INTR_INTERVAL; -+ } -+ -+ /* Calculate amount of EPs needed */ -+ ep_count = MAX_INTR_INTERVAL / urb_priv->interval; -+ -+ for(i = 0; i < ep_count; i++) { -+ ep_desc = create_ep(urb_priv->epid, urb_priv->first_sb, mem_flags); -+ if(ep_desc == NULL) { -+ /* Free any descriptors that we may have allocated before failure */ -+ while(i > 0) { -+ i--; -+ kfree(urb_priv->intr_ep_pool[i]); -+ } -+ return -ENOMEM; -+ } -+ urb_priv->intr_ep_pool[i] = ep_desc; -+ } -+ urb_priv->intr_ep_pool_length = ep_count; -+ return 0; -+} -+ -+/* DMA RX/TX functions */ -+/* ----------------------- */ -+ -+static void tc_dma_init_rx_list(void) { -+ int i; -+ -+ /* Setup descriptor list except last one */ -+ for (i = 0; i < (NBR_OF_RX_DESC - 1); i++) { -+ RxDescList[i].sw_len = RX_DESC_BUF_SIZE; -+ RxDescList[i].command = 0; -+ RxDescList[i].next = virt_to_phys(&RxDescList[i + 1]); -+ RxDescList[i].buf = virt_to_phys(RxBuf + (i * RX_DESC_BUF_SIZE)); -+ RxDescList[i].hw_len = 0; -+ RxDescList[i].status = 0; -+ -+ /* DMA IN cache bug. (struct etrax_dma_descr has the same layout as -+ USB_IN_Desc for the relevant fields.) */ -+ prepare_rx_descriptor((struct etrax_dma_descr*)&RxDescList[i]); -+ -+ } -+ /* Special handling of last descriptor */ -+ RxDescList[i].sw_len = RX_DESC_BUF_SIZE; -+ RxDescList[i].command = IO_STATE(USB_IN_command, eol, yes); -+ RxDescList[i].next = virt_to_phys(&RxDescList[0]); -+ RxDescList[i].buf = virt_to_phys(RxBuf + (i * RX_DESC_BUF_SIZE)); -+ RxDescList[i].hw_len = 0; -+ RxDescList[i].status = 0; -+ -+ /* Setup list pointers that show progress in list */ -+ myNextRxDesc = &RxDescList[0]; -+ myLastRxDesc = &RxDescList[NBR_OF_RX_DESC - 1]; -+ -+ flush_etrax_cache(); -+ /* Point DMA to first descriptor in list and start it */ -+ *R_DMA_CH9_FIRST = virt_to_phys(myNextRxDesc); -+ *R_DMA_CH9_CMD = IO_STATE(R_DMA_CH9_CMD, cmd, start); -+} -+ -+ -+static void tc_dma_init_tx_bulk_list(void) { -+ int i; -+ volatile struct USB_EP_Desc *epDescr; -+ -+ for (i = 0; i < (NBR_OF_EPIDS - 1); i++) { -+ epDescr = &(TxBulkEPList[i]); -+ CHECK_ALIGN(epDescr); -+ epDescr->hw_len = 0; -+ epDescr->command = IO_FIELD(USB_EP_command, epid, i); -+ epDescr->sub = 0; -+ epDescr->next = virt_to_phys(&TxBulkEPList[i + 1]); -+ -+ /* Initiate two EPs, disabled and with the eol flag set. No need for any -+ preserved epid. */ -+ -+ /* The first one has the intr flag set so we get an interrupt when the DMA -+ channel is about to become disabled. */ -+ CHECK_ALIGN(&TxBulkDummyEPList[i][0]); -+ TxBulkDummyEPList[i][0].hw_len = 0; -+ TxBulkDummyEPList[i][0].command = (IO_FIELD(USB_EP_command, epid, DUMMY_EPID) | -+ IO_STATE(USB_EP_command, eol, yes) | -+ IO_STATE(USB_EP_command, intr, yes)); -+ TxBulkDummyEPList[i][0].sub = 0; -+ TxBulkDummyEPList[i][0].next = virt_to_phys(&TxBulkDummyEPList[i][1]); -+ -+ /* The second one. */ -+ CHECK_ALIGN(&TxBulkDummyEPList[i][1]); -+ TxBulkDummyEPList[i][1].hw_len = 0; -+ TxBulkDummyEPList[i][1].command = (IO_FIELD(USB_EP_command, epid, DUMMY_EPID) | -+ IO_STATE(USB_EP_command, eol, yes)); -+ TxBulkDummyEPList[i][1].sub = 0; -+ /* The last dummy's next pointer is the same as the current EP's next pointer. */ -+ TxBulkDummyEPList[i][1].next = virt_to_phys(&TxBulkEPList[i + 1]); -+ } -+ -+ /* Special handling of last descr in list, make list circular */ -+ epDescr = &TxBulkEPList[i]; -+ CHECK_ALIGN(epDescr); -+ epDescr->hw_len = 0; -+ epDescr->command = IO_STATE(USB_EP_command, eol, yes) | -+ IO_FIELD(USB_EP_command, epid, i); -+ epDescr->sub = 0; -+ epDescr->next = virt_to_phys(&TxBulkEPList[0]); -+ -+ /* Init DMA sub-channel pointers to last item in each list */ -+ *R_DMA_CH8_SUB0_EP = virt_to_phys(&TxBulkEPList[i]); -+ /* No point in starting the bulk channel yet. -+ *R_DMA_CH8_SUB0_CMD = IO_STATE(R_DMA_CH8_SUB0_CMD, cmd, start); */ -+} -+ -+static void tc_dma_init_tx_ctrl_list(void) { -+ int i; -+ volatile struct USB_EP_Desc *epDescr; -+ -+ for (i = 0; i < (NBR_OF_EPIDS - 1); i++) { -+ epDescr = &(TxCtrlEPList[i]); -+ CHECK_ALIGN(epDescr); -+ epDescr->hw_len = 0; -+ epDescr->command = IO_FIELD(USB_EP_command, epid, i); -+ epDescr->sub = 0; -+ epDescr->next = virt_to_phys(&TxCtrlEPList[i + 1]); -+ } -+ /* Special handling of last descr in list, make list circular */ -+ epDescr = &TxCtrlEPList[i]; -+ CHECK_ALIGN(epDescr); -+ epDescr->hw_len = 0; -+ epDescr->command = IO_STATE(USB_EP_command, eol, yes) | -+ IO_FIELD(USB_EP_command, epid, i); -+ epDescr->sub = 0; -+ epDescr->next = virt_to_phys(&TxCtrlEPList[0]); -+ -+ /* Init DMA sub-channel pointers to last item in each list */ -+ *R_DMA_CH8_SUB1_EP = virt_to_phys(&TxCtrlEPList[i]); -+ /* No point in starting the ctrl channel yet. -+ *R_DMA_CH8_SUB1_CMD = IO_STATE(R_DMA_CH8_SUB0_CMD, cmd, start); */ -+} -+ -+ -+static void tc_dma_init_tx_intr_list(void) { -+ int i; -+ -+ TxIntrSB_zout.sw_len = 1; -+ TxIntrSB_zout.next = 0; -+ TxIntrSB_zout.buf = virt_to_phys(&zout_buffer[0]); -+ TxIntrSB_zout.command = (IO_FIELD(USB_SB_command, rem, 0) | -+ IO_STATE(USB_SB_command, tt, zout) | -+ IO_STATE(USB_SB_command, full, yes) | -+ IO_STATE(USB_SB_command, eot, yes) | -+ IO_STATE(USB_SB_command, eol, yes)); -+ -+ for (i = 0; i < (MAX_INTR_INTERVAL - 1); i++) { -+ CHECK_ALIGN(&TxIntrEPList[i]); -+ TxIntrEPList[i].hw_len = 0; -+ TxIntrEPList[i].command = -+ (IO_STATE(USB_EP_command, eof, yes) | -+ IO_STATE(USB_EP_command, enable, yes) | -+ IO_FIELD(USB_EP_command, epid, INVALID_EPID)); -+ TxIntrEPList[i].sub = virt_to_phys(&TxIntrSB_zout); -+ TxIntrEPList[i].next = virt_to_phys(&TxIntrEPList[i + 1]); -+ } -+ -+ /* Special handling of last descr in list, make list circular */ -+ CHECK_ALIGN(&TxIntrEPList[i]); -+ TxIntrEPList[i].hw_len = 0; -+ TxIntrEPList[i].command = -+ (IO_STATE(USB_EP_command, eof, yes) | -+ IO_STATE(USB_EP_command, eol, yes) | -+ IO_STATE(USB_EP_command, enable, yes) | -+ IO_FIELD(USB_EP_command, epid, INVALID_EPID)); -+ TxIntrEPList[i].sub = virt_to_phys(&TxIntrSB_zout); -+ TxIntrEPList[i].next = virt_to_phys(&TxIntrEPList[0]); -+ -+ intr_dbg("Initiated Intr EP descriptor list\n"); -+ -+ -+ /* Connect DMA 8 sub-channel 2 to first in list */ -+ *R_DMA_CH8_SUB2_EP = virt_to_phys(&TxIntrEPList[0]); -+} -+ -+static void tc_dma_init_tx_isoc_list(void) { -+ int i; -+ -+ DBFENTER; -+ -+ /* Read comment at zout_buffer declaration for an explanation to this. */ -+ TxIsocSB_zout.sw_len = 1; -+ TxIsocSB_zout.next = 0; -+ TxIsocSB_zout.buf = virt_to_phys(&zout_buffer[0]); -+ TxIsocSB_zout.command = (IO_FIELD(USB_SB_command, rem, 0) | -+ IO_STATE(USB_SB_command, tt, zout) | -+ IO_STATE(USB_SB_command, full, yes) | -+ IO_STATE(USB_SB_command, eot, yes) | -+ IO_STATE(USB_SB_command, eol, yes)); -+ -+ /* The last isochronous EP descriptor is a dummy. */ -+ for (i = 0; i < (NBR_OF_EPIDS - 1); i++) { -+ CHECK_ALIGN(&TxIsocEPList[i]); -+ TxIsocEPList[i].hw_len = 0; -+ TxIsocEPList[i].command = IO_FIELD(USB_EP_command, epid, i); -+ TxIsocEPList[i].sub = 0; -+ TxIsocEPList[i].next = virt_to_phys(&TxIsocEPList[i + 1]); -+ } -+ -+ CHECK_ALIGN(&TxIsocEPList[i]); -+ TxIsocEPList[i].hw_len = 0; -+ -+ /* Must enable the last EP descr to get eof interrupt. */ -+ TxIsocEPList[i].command = (IO_STATE(USB_EP_command, enable, yes) | -+ IO_STATE(USB_EP_command, eof, yes) | -+ IO_STATE(USB_EP_command, eol, yes) | -+ IO_FIELD(USB_EP_command, epid, INVALID_EPID)); -+ TxIsocEPList[i].sub = virt_to_phys(&TxIsocSB_zout); -+ TxIsocEPList[i].next = virt_to_phys(&TxIsocEPList[0]); -+ -+ *R_DMA_CH8_SUB3_EP = virt_to_phys(&TxIsocEPList[0]); -+ *R_DMA_CH8_SUB3_CMD = IO_STATE(R_DMA_CH8_SUB3_CMD, cmd, start); -+} -+ -+static int tc_dma_init(struct usb_hcd *hcd) { -+ tc_dma_init_rx_list(); -+ tc_dma_init_tx_bulk_list(); -+ tc_dma_init_tx_ctrl_list(); -+ tc_dma_init_tx_intr_list(); -+ tc_dma_init_tx_isoc_list(); -+ -+ if (cris_request_dma(USB_TX_DMA_NBR, -+ "ETRAX 100LX built-in USB (Tx)", -+ DMA_VERBOSE_ON_ERROR, -+ dma_usb)) { -+ err("Could not allocate DMA ch 8 for USB"); -+ return -EBUSY; -+ } -+ -+ if (cris_request_dma(USB_RX_DMA_NBR, -+ "ETRAX 100LX built-in USB (Rx)", -+ DMA_VERBOSE_ON_ERROR, -+ dma_usb)) { -+ err("Could not allocate DMA ch 9 for USB"); -+ return -EBUSY; -+ } -+ -+ *R_IRQ_MASK2_SET = -+ /* Note that these interrupts are not used. */ -+ IO_STATE(R_IRQ_MASK2_SET, dma8_sub0_descr, set) | -+ /* Sub channel 1 (ctrl) descr. interrupts are used. */ -+ IO_STATE(R_IRQ_MASK2_SET, dma8_sub1_descr, set) | -+ IO_STATE(R_IRQ_MASK2_SET, dma8_sub2_descr, set) | -+ /* Sub channel 3 (isoc) descr. interrupts are used. */ -+ IO_STATE(R_IRQ_MASK2_SET, dma8_sub3_descr, set); -+ -+ /* Note that the dma9_descr interrupt is not used. */ -+ *R_IRQ_MASK2_SET = -+ IO_STATE(R_IRQ_MASK2_SET, dma9_eop, set) | -+ IO_STATE(R_IRQ_MASK2_SET, dma9_descr, set); -+ -+ if (request_irq(ETRAX_USB_RX_IRQ, tc_dma_rx_interrupt, 0, -+ "ETRAX 100LX built-in USB (Rx)", hcd)) { -+ err("Could not allocate IRQ %d for USB", ETRAX_USB_RX_IRQ); -+ return -EBUSY; -+ } -+ -+ if (request_irq(ETRAX_USB_TX_IRQ, tc_dma_tx_interrupt, 0, -+ "ETRAX 100LX built-in USB (Tx)", hcd)) { -+ err("Could not allocate IRQ %d for USB", ETRAX_USB_TX_IRQ); -+ return -EBUSY; -+ } -+ -+ return 0; -+} -+ -+static void tc_dma_destroy(void) { -+ free_irq(ETRAX_USB_RX_IRQ, NULL); -+ free_irq(ETRAX_USB_TX_IRQ, NULL); -+ -+ cris_free_dma(USB_TX_DMA_NBR, "ETRAX 100LX built-in USB (Tx)"); -+ cris_free_dma(USB_RX_DMA_NBR, "ETRAX 100LX built-in USB (Rx)"); -+ -+} -+ -+static void tc_dma_link_intr_urb(struct urb *urb); -+ -+/* Handle processing of Bulk, Ctrl and Intr queues */ -+static void tc_dma_process_queue(int epid) { -+ struct urb *urb; -+ struct crisv10_urb_priv *urb_priv = urb->hcpriv; -+ unsigned long flags; -+ char toggle; -+ -+ if(epid_state[epid].disabled) { -+ /* Don't process any URBs on a disabled endpoint */ -+ return; -+ } -+ -+ /* Do not disturb us while fiddling with EPs and epids */ -+ local_irq_save(flags); -+ -+ /* For bulk, Ctrl and Intr can we only have one URB active at a time for -+ a specific EP. */ -+ if(activeUrbList[epid] != NULL) { -+ /* An URB is already active on EP, skip checking queue */ -+ local_irq_restore(flags); -+ return; -+ } -+ -+ urb = urb_list_first(epid); -+ if(urb == NULL) { -+ /* No URB waiting in EP queue. Nothing do to */ -+ local_irq_restore(flags); -+ return; -+ } -+ -+ urb_priv = urb->hcpriv; -+ ASSERT(urb_priv != NULL); -+ ASSERT(urb_priv->urb_state == NOT_STARTED); -+ ASSERT(!usb_pipeisoc(urb->pipe)); -+ -+ /* Remove this URB from the queue and move it to active */ -+ activeUrbList[epid] = urb; -+ urb_list_del(urb, epid); -+ -+ urb_priv->urb_state = STARTED; -+ -+ /* Reset error counters (regardless of which direction this traffic is). */ -+ etrax_epid_clear_error(epid); -+ -+ /* Special handling of Intr EP lists */ -+ if(usb_pipeint(urb->pipe)) { -+ tc_dma_link_intr_urb(urb); -+ local_irq_restore(flags); -+ return; -+ } -+ -+ /* Software must preset the toggle bits for Bulk and Ctrl */ -+ if(usb_pipecontrol(urb->pipe)) { -+ /* Toggle bits are initialized only during setup transaction in a -+ CTRL transfer */ -+ etrax_epid_set_toggle(epid, 0, 0); -+ etrax_epid_set_toggle(epid, 1, 0); -+ } else { -+ toggle = usb_gettoggle(urb->dev, usb_pipeendpoint(urb->pipe), -+ usb_pipeout(urb->pipe)); -+ etrax_epid_set_toggle(epid, usb_pipeout(urb->pipe), toggle); -+ } -+ -+ tc_dbg("Added SBs from (URB:0x%x %s %s) to epid %d: %s\n", -+ (unsigned int)urb, str_dir(urb->pipe), str_type(urb->pipe), epid, -+ sblist_to_str(urb_priv->first_sb)); -+ -+ /* We start the DMA sub channel without checking if it's running or not, -+ because: -+ 1) If it's already running, issuing the start command is a nop. -+ 2) We avoid a test-and-set race condition. */ -+ switch(usb_pipetype(urb->pipe)) { -+ case PIPE_BULK: -+ /* Assert that the EP descriptor is disabled. */ -+ ASSERT(!(TxBulkEPList[epid].command & IO_MASK(USB_EP_command, enable))); -+ -+ /* Set up and enable the EP descriptor. */ -+ TxBulkEPList[epid].sub = virt_to_phys(urb_priv->first_sb); -+ TxBulkEPList[epid].hw_len = 0; -+ TxBulkEPList[epid].command |= IO_STATE(USB_EP_command, enable, yes); -+ -+ /* Check if the dummy list is already with us (if several urbs were queued). */ -+ if (usb_pipein(urb->pipe) && (TxBulkEPList[epid].next != virt_to_phys(&TxBulkDummyEPList[epid][0]))) { -+ tc_dbg("Inviting dummy list to the party for urb 0x%lx, epid %d", -+ (unsigned long)urb, epid); -+ -+ /* We don't need to check if the DMA is at this EP or not before changing the -+ next pointer, since we will do it in one 32-bit write (EP descriptors are -+ 32-bit aligned). */ -+ TxBulkEPList[epid].next = virt_to_phys(&TxBulkDummyEPList[epid][0]); -+ } -+ -+ restart_dma8_sub0(); -+ -+ /* Update/restart the bulk start timer since we just started the channel.*/ -+ mod_timer(&bulk_start_timer, jiffies + BULK_START_TIMER_INTERVAL); -+ /* Update/restart the bulk eot timer since we just inserted traffic. */ -+ mod_timer(&bulk_eot_timer, jiffies + BULK_EOT_TIMER_INTERVAL); -+ break; -+ case PIPE_CONTROL: -+ /* Assert that the EP descriptor is disabled. */ -+ ASSERT(!(TxCtrlEPList[epid].command & IO_MASK(USB_EP_command, enable))); -+ -+ /* Set up and enable the EP descriptor. */ -+ TxCtrlEPList[epid].sub = virt_to_phys(urb_priv->first_sb); -+ TxCtrlEPList[epid].hw_len = 0; -+ TxCtrlEPList[epid].command |= IO_STATE(USB_EP_command, enable, yes); -+ -+ *R_DMA_CH8_SUB1_CMD = IO_STATE(R_DMA_CH8_SUB1_CMD, cmd, start); -+ break; -+ } -+ local_irq_restore(flags); -+} -+ -+static void tc_dma_link_intr_urb(struct urb *urb) { -+ struct crisv10_urb_priv *urb_priv = urb->hcpriv; -+ volatile struct USB_EP_Desc *tmp_ep; -+ struct USB_EP_Desc *ep_desc; -+ int i = 0, epid; -+ int pool_idx = 0; -+ -+ ASSERT(urb_priv != NULL); -+ epid = urb_priv->epid; -+ ASSERT(urb_priv->interval > 0); -+ ASSERT(urb_priv->intr_ep_pool_length > 0); -+ -+ tmp_ep = &TxIntrEPList[0]; -+ -+ /* Only insert one EP descriptor in list for Out Intr URBs. -+ We can only handle Out Intr with interval of 128ms because -+ it's not possible to insert several Out Intr EPs because they -+ are not consumed by the DMA. */ -+ if(usb_pipeout(urb->pipe)) { -+ ep_desc = urb_priv->intr_ep_pool[0]; -+ ASSERT(ep_desc); -+ ep_desc->next = tmp_ep->next; -+ tmp_ep->next = virt_to_phys(ep_desc); -+ i++; -+ } else { -+ /* Loop through Intr EP descriptor list and insert EP for URB at -+ specified interval */ -+ do { -+ /* Each EP descriptor with eof flag sat signals a new frame */ -+ if (tmp_ep->command & IO_MASK(USB_EP_command, eof)) { -+ /* Insert a EP from URBs EP pool at correct interval */ -+ if ((i % urb_priv->interval) == 0) { -+ ep_desc = urb_priv->intr_ep_pool[pool_idx]; -+ ASSERT(ep_desc); -+ ep_desc->next = tmp_ep->next; -+ tmp_ep->next = virt_to_phys(ep_desc); -+ pool_idx++; -+ ASSERT(pool_idx <= urb_priv->intr_ep_pool_length); -+ } -+ i++; -+ } -+ tmp_ep = (struct USB_EP_Desc *)phys_to_virt(tmp_ep->next); -+ } while(tmp_ep != &TxIntrEPList[0]); -+ } -+ -+ intr_dbg("Added SBs to intr epid %d: %s interval:%d (%d EP)\n", epid, -+ sblist_to_str(urb_priv->first_sb), urb_priv->interval, pool_idx); -+ -+ /* We start the DMA sub channel without checking if it's running or not, -+ because: -+ 1) If it's already running, issuing the start command is a nop. -+ 2) We avoid a test-and-set race condition. */ -+ *R_DMA_CH8_SUB2_CMD = IO_STATE(R_DMA_CH8_SUB2_CMD, cmd, start); -+} -+ -+ /* hinko ignore usb_pipeisoc */ -+#if 0 -+static void tc_dma_process_isoc_urb(struct urb *urb) { -+ unsigned long flags; -+ struct crisv10_urb_priv *urb_priv = urb->hcpriv; -+ int epid; -+ -+ /* Do not disturb us while fiddling with EPs and epids */ -+ local_irq_save(flags); -+ -+ ASSERT(urb_priv); -+ ASSERT(urb_priv->first_sb); -+ epid = urb_priv->epid; -+ -+ if(activeUrbList[epid] == NULL) { -+ /* EP is idle, so make this URB active */ -+ activeUrbList[epid] = urb; -+ urb_list_del(urb, epid); -+ ASSERT(TxIsocEPList[epid].sub == 0); -+ ASSERT(!(TxIsocEPList[epid].command & -+ IO_STATE(USB_EP_command, enable, yes))); -+ -+ /* Differentiate between In and Out Isoc. Because In SBs are not consumed*/ -+ if(usb_pipein(urb->pipe)) { -+ /* Each EP for In Isoc will have only one SB descriptor, setup when -+ submitting the first active urb. We do it here by copying from URBs -+ pre-allocated SB. */ -+ memcpy((void *)&(TxIsocSBList[epid]), urb_priv->first_sb, -+ sizeof(TxIsocSBList[epid])); -+ TxIsocEPList[epid].hw_len = 0; -+ TxIsocEPList[epid].sub = virt_to_phys(&(TxIsocSBList[epid])); -+ } else { -+ /* For Out Isoc we attach the pre-allocated list of SBs for the URB */ -+ TxIsocEPList[epid].hw_len = 0; -+ TxIsocEPList[epid].sub = virt_to_phys(urb_priv->first_sb); -+ -+ isoc_dbg("Attached first URB:0x%x[%d] to epid:%d first_sb:0x%x" -+ " last_sb::0x%x\n", -+ (unsigned int)urb, urb_priv->urb_num, epid, -+ (unsigned int)(urb_priv->first_sb), -+ (unsigned int)(urb_priv->last_sb)); -+ } -+ -+ if (urb->transfer_flags & URB_ISO_ASAP) { -+ /* The isoc transfer should be started as soon as possible. The -+ start_frame field is a return value if URB_ISO_ASAP was set. Comparing -+ R_USB_FM_NUMBER with a USB Chief trace shows that the first isoc IN -+ token is sent 2 frames later. I'm not sure how this affects usage of -+ the start_frame field by the device driver, or how it affects things -+ when USB_ISO_ASAP is not set, so therefore there's no compensation for -+ the 2 frame "lag" here. */ -+ urb->start_frame = (*R_USB_FM_NUMBER & 0x7ff); -+ TxIsocEPList[epid].command |= IO_STATE(USB_EP_command, enable, yes); -+ urb_priv->urb_state = STARTED; -+ isoc_dbg("URB_ISO_ASAP set, urb->start_frame set to %d\n", -+ urb->start_frame); -+ } else { -+ /* Not started yet. */ -+ urb_priv->urb_state = NOT_STARTED; -+ isoc_warn("urb_priv->urb_state set to NOT_STARTED for URB:0x%x\n", -+ (unsigned int)urb); -+ } -+ -+ } else { -+ /* An URB is already active on the EP. Leave URB in queue and let -+ finish_isoc_urb process it after current active URB */ -+ ASSERT(TxIsocEPList[epid].sub != 0); -+ -+ if(usb_pipein(urb->pipe)) { -+ /* Because there already is a active In URB on this epid we do nothing -+ and the finish_isoc_urb() function will handle switching to next URB*/ -+ -+ } else { /* For Out Isoc, insert new URBs traffic last in SB-list. */ -+ struct USB_SB_Desc *temp_sb_desc; -+ -+ /* Set state STARTED to all Out Isoc URBs added to SB list because we -+ don't know how many of them that are finished before descr interrupt*/ -+ urb_priv->urb_state = STARTED; -+ -+ /* Find end of current SB list by looking for SB with eol flag sat */ -+ temp_sb_desc = phys_to_virt(TxIsocEPList[epid].sub); -+ while ((temp_sb_desc->command & IO_MASK(USB_SB_command, eol)) != -+ IO_STATE(USB_SB_command, eol, yes)) { -+ ASSERT(temp_sb_desc->next); -+ temp_sb_desc = phys_to_virt(temp_sb_desc->next); -+ } -+ -+ isoc_dbg("Appended URB:0x%x[%d] (first:0x%x last:0x%x) to epid:%d" -+ " sub:0x%x eol:0x%x\n", -+ (unsigned int)urb, urb_priv->urb_num, -+ (unsigned int)(urb_priv->first_sb), -+ (unsigned int)(urb_priv->last_sb), epid, -+ (unsigned int)phys_to_virt(TxIsocEPList[epid].sub), -+ (unsigned int)temp_sb_desc); -+ -+ /* Next pointer must be set before eol is removed. */ -+ temp_sb_desc->next = virt_to_phys(urb_priv->first_sb); -+ /* Clear the previous end of list flag since there is a new in the -+ added SB descriptor list. */ -+ temp_sb_desc->command &= ~IO_MASK(USB_SB_command, eol); -+ -+ if (!(TxIsocEPList[epid].command & IO_MASK(USB_EP_command, enable))) { -+ __u32 epid_data; -+ /* 8.8.5 in Designer's Reference says we should check for and correct -+ any errors in the EP here. That should not be necessary if -+ epid_attn is handled correctly, so we assume all is ok. */ -+ epid_data = etrax_epid_iso_get(epid); -+ if (IO_EXTRACT(R_USB_EPT_DATA, error_code, epid_data) != -+ IO_STATE_VALUE(R_USB_EPT_DATA, error_code, no_error)) { -+ isoc_err("Disabled Isoc EP with error:%d on epid:%d when appending" -+ " URB:0x%x[%d]\n", -+ IO_EXTRACT(R_USB_EPT_DATA, error_code, epid_data), epid, -+ (unsigned int)urb, urb_priv->urb_num); -+ } -+ -+ /* The SB list was exhausted. */ -+ if (virt_to_phys(urb_priv->last_sb) != TxIsocEPList[epid].sub) { -+ /* The new sublist did not get processed before the EP was -+ disabled. Setup the EP again. */ -+ -+ if(virt_to_phys(temp_sb_desc) == TxIsocEPList[epid].sub) { -+ isoc_dbg("EP for epid:%d stoped at SB:0x%x before newly inserted" -+ ", restarting from this URBs SB:0x%x\n", -+ epid, (unsigned int)temp_sb_desc, -+ (unsigned int)(urb_priv->first_sb)); -+ TxIsocEPList[epid].hw_len = 0; -+ TxIsocEPList[epid].sub = virt_to_phys(urb_priv->first_sb); -+ urb->start_frame = (*R_USB_FM_NUMBER & 0x7ff); -+ /* Enable the EP again so data gets processed this time */ -+ TxIsocEPList[epid].command |= -+ IO_STATE(USB_EP_command, enable, yes); -+ -+ } else { -+ /* The EP has been disabled but not at end this URB (god knows -+ where). This should generate an epid_attn so we should not be -+ here */ -+ isoc_warn("EP was disabled on sb:0x%x before SB list for" -+ " URB:0x%x[%d] got processed\n", -+ (unsigned int)phys_to_virt(TxIsocEPList[epid].sub), -+ (unsigned int)urb, urb_priv->urb_num); -+ } -+ } else { -+ /* This might happend if we are slow on this function and isn't -+ an error. */ -+ isoc_dbg("EP was disabled and finished with SBs from appended" -+ " URB:0x%x[%d]\n", (unsigned int)urb, urb_priv->urb_num); -+ } -+ } -+ } -+ } -+ -+ /* Start the DMA sub channel */ -+ *R_DMA_CH8_SUB3_CMD = IO_STATE(R_DMA_CH8_SUB3_CMD, cmd, start); -+ -+ local_irq_restore(flags); -+} -+#endif -+ -+static void tc_dma_unlink_intr_urb(struct urb *urb) { -+ struct crisv10_urb_priv *urb_priv = urb->hcpriv; -+ volatile struct USB_EP_Desc *first_ep; /* First EP in the list. */ -+ volatile struct USB_EP_Desc *curr_ep; /* Current EP, the iterator. */ -+ volatile struct USB_EP_Desc *next_ep; /* The EP after current. */ -+ volatile struct USB_EP_Desc *unlink_ep; /* The one we should remove from -+ the list. */ -+ int count = 0; -+ volatile int timeout = 10000; -+ int epid; -+ -+ /* Read 8.8.4 in Designer's Reference, "Removing an EP Descriptor from the -+ List". */ -+ ASSERT(urb_priv); -+ ASSERT(urb_priv->intr_ep_pool_length > 0); -+ epid = urb_priv->epid; -+ -+ /* First disable all Intr EPs belonging to epid for this URB */ -+ first_ep = &TxIntrEPList[0]; -+ curr_ep = first_ep; -+ do { -+ next_ep = (struct USB_EP_Desc *)phys_to_virt(curr_ep->next); -+ if (IO_EXTRACT(USB_EP_command, epid, next_ep->command) == epid) { -+ /* Disable EP */ -+ next_ep->command &= ~IO_MASK(USB_EP_command, enable); -+ } -+ curr_ep = phys_to_virt(curr_ep->next); -+ } while (curr_ep != first_ep); -+ -+ -+ /* Now unlink all EPs belonging to this epid from Descr list */ -+ first_ep = &TxIntrEPList[0]; -+ curr_ep = first_ep; -+ do { -+ next_ep = (struct USB_EP_Desc *)phys_to_virt(curr_ep->next); -+ if (IO_EXTRACT(USB_EP_command, epid, next_ep->command) == epid) { -+ /* This is the one we should unlink. */ -+ unlink_ep = next_ep; -+ -+ /* Actually unlink the EP from the DMA list. */ -+ curr_ep->next = unlink_ep->next; -+ -+ /* Wait until the DMA is no longer at this descriptor. */ -+ while((*R_DMA_CH8_SUB2_EP == virt_to_phys(unlink_ep)) && -+ (timeout-- > 0)); -+ if(timeout == 0) { -+ warn("Timeout while waiting for DMA-TX-Intr to leave unlink EP\n"); -+ } -+ -+ count++; -+ } -+ curr_ep = phys_to_virt(curr_ep->next); -+ } while (curr_ep != first_ep); -+ -+ if(count != urb_priv->intr_ep_pool_length) { -+ intr_warn("Unlinked %d of %d Intr EPs for URB:0x%x[%d]\n", count, -+ urb_priv->intr_ep_pool_length, (unsigned int)urb, -+ urb_priv->urb_num); -+ } else { -+ intr_dbg("Unlinked %d of %d interrupt EPs for URB:0x%x\n", count, -+ urb_priv->intr_ep_pool_length, (unsigned int)urb); -+ } -+} -+ -+static void check_finished_bulk_tx_epids(struct usb_hcd *hcd, -+ int timer) { -+ unsigned long flags; -+ int epid; -+ struct urb *urb; -+ struct crisv10_urb_priv * urb_priv; -+ __u32 epid_data; -+ -+ /* Protect TxEPList */ -+ local_irq_save(flags); -+ -+ for (epid = 0; epid < NBR_OF_EPIDS; epid++) { -+ /* A finished EP descriptor is disabled and has a valid sub pointer */ -+ if (!(TxBulkEPList[epid].command & IO_MASK(USB_EP_command, enable)) && -+ (TxBulkEPList[epid].sub != 0)) { -+ -+ /* Get the active URB for this epid */ -+ urb = activeUrbList[epid]; -+ /* Sanity checks */ -+ ASSERT(urb); -+ urb_priv = (struct crisv10_urb_priv *)urb->hcpriv; -+ ASSERT(urb_priv); -+ -+ /* Only handle finished out Bulk EPs here, -+ and let RX interrupt take care of the rest */ -+ if(!epid_out_traffic(epid)) { -+ continue; -+ } -+ -+ if(timer) { -+ tc_warn("Found finished %s Bulk epid:%d URB:0x%x[%d] from timeout\n", -+ epid_out_traffic(epid) ? "Out" : "In", epid, (unsigned int)urb, -+ urb_priv->urb_num); -+ } else { -+ tc_dbg("Found finished %s Bulk epid:%d URB:0x%x[%d] from interrupt\n", -+ epid_out_traffic(epid) ? "Out" : "In", epid, (unsigned int)urb, -+ urb_priv->urb_num); -+ } -+ -+ if(urb_priv->urb_state == UNLINK) { -+ /* This Bulk URB is requested to be unlinked, that means that the EP -+ has been disabled and we might not have sent all data */ -+ tc_finish_urb(hcd, urb, urb->status); -+ continue; -+ } -+ -+ ASSERT(urb_priv->urb_state == STARTED); -+ if (phys_to_virt(TxBulkEPList[epid].sub) != urb_priv->last_sb) { -+ tc_err("Endpoint got disabled before reaching last sb\n"); -+ } -+ -+ epid_data = etrax_epid_get(epid); -+ if (IO_EXTRACT(R_USB_EPT_DATA, error_code, epid_data) == -+ IO_STATE_VALUE(R_USB_EPT_DATA, error_code, no_error)) { -+ /* This means that the endpoint has no error, is disabled -+ and had inserted traffic, i.e. transfer successfully completed. */ -+ tc_finish_urb(hcd, urb, 0); -+ } else { -+ /* Shouldn't happen. We expect errors to be caught by epid -+ attention. */ -+ tc_err("Found disabled bulk EP desc (epid:%d error:%d)\n", -+ epid, IO_EXTRACT(R_USB_EPT_DATA, error_code, epid_data)); -+ } -+ } else { -+ tc_dbg("Ignoring In Bulk epid:%d, let RX interrupt handle it\n", epid); -+ } -+ } -+ -+ local_irq_restore(flags); -+} -+ -+static void check_finished_ctrl_tx_epids(struct usb_hcd *hcd) { -+ unsigned long flags; -+ int epid; -+ struct urb *urb; -+ struct crisv10_urb_priv * urb_priv; -+ __u32 epid_data; -+ -+ /* Protect TxEPList */ -+ local_irq_save(flags); -+ -+ for (epid = 0; epid < NBR_OF_EPIDS; epid++) { -+ if(epid == DUMMY_EPID) -+ continue; -+ -+ /* A finished EP descriptor is disabled and has a valid sub pointer */ -+ if (!(TxCtrlEPList[epid].command & IO_MASK(USB_EP_command, enable)) && -+ (TxCtrlEPList[epid].sub != 0)) { -+ -+ /* Get the active URB for this epid */ -+ urb = activeUrbList[epid]; -+ -+ if(urb == NULL) { -+ tc_warn("Found finished Ctrl epid:%d with no active URB\n", epid); -+ continue; -+ } -+ -+ /* Sanity checks */ -+ ASSERT(usb_pipein(urb->pipe)); -+ urb_priv = (struct crisv10_urb_priv *)urb->hcpriv; -+ ASSERT(urb_priv); -+ if (phys_to_virt(TxCtrlEPList[epid].sub) != urb_priv->last_sb) { -+ tc_err("Endpoint got disabled before reaching last sb\n"); -+ } -+ -+ epid_data = etrax_epid_get(epid); -+ if (IO_EXTRACT(R_USB_EPT_DATA, error_code, epid_data) == -+ IO_STATE_VALUE(R_USB_EPT_DATA, error_code, no_error)) { -+ /* This means that the endpoint has no error, is disabled -+ and had inserted traffic, i.e. transfer successfully completed. */ -+ -+ /* Check if RX-interrupt for In Ctrl has been processed before -+ finishing the URB */ -+ if(urb_priv->ctrl_rx_done) { -+ tc_dbg("Finishing In Ctrl URB:0x%x[%d] in tx_interrupt\n", -+ (unsigned int)urb, urb_priv->urb_num); -+ tc_finish_urb(hcd, urb, 0); -+ } else { -+ /* If we get zout descriptor interrupt before RX was done for a -+ In Ctrl transfer, then we flag that and it will be finished -+ in the RX-Interrupt */ -+ urb_priv->ctrl_zout_done = 1; -+ tc_dbg("Got zout descr interrupt before RX interrupt\n"); -+ } -+ } else { -+ /* Shouldn't happen. We expect errors to be caught by epid -+ attention. */ -+ tc_err("Found disabled Ctrl EP desc (epid:%d URB:0x%x[%d]) error_code:%d\n", epid, (unsigned int)urb, urb_priv->urb_num, IO_EXTRACT(R_USB_EPT_DATA, error_code, epid_data)); -+ __dump_ep_desc(&(TxCtrlEPList[epid])); -+ __dump_ept_data(epid); -+ } -+ } -+ } -+ local_irq_restore(flags); -+} -+ -+ /* hinko ignore usb_pipeisoc */ -+#if 0 -+/* This function goes through all epids that are setup for Out Isoc transfers -+ and marks (isoc_out_done) all queued URBs that the DMA has finished -+ transfer for. -+ No URB completetion is done here to make interrupt routine return quickly. -+ URBs are completed later with help of complete_isoc_bottom_half() that -+ becomes schedules when this functions is finished. */ -+static void check_finished_isoc_tx_epids(void) { -+ unsigned long flags; -+ int epid; -+ struct urb *urb; -+ struct crisv10_urb_priv * urb_priv; -+ struct USB_SB_Desc* sb_desc; -+ int epid_done; -+ -+ /* Protect TxIsocEPList */ -+ local_irq_save(flags); -+ -+ for (epid = 0; epid < NBR_OF_EPIDS; epid++) { -+ if (TxIsocEPList[epid].sub == 0 || epid == INVALID_EPID || -+ !epid_out_traffic(epid)) { -+ /* Nothing here to see. */ -+ continue; -+ } -+ ASSERT(epid_inuse(epid)); -+ ASSERT(epid_isoc(epid)); -+ -+ sb_desc = phys_to_virt(TxIsocEPList[epid].sub); -+ /* Find the last descriptor of the currently active URB for this ep. -+ This is the first descriptor in the sub list marked for a descriptor -+ interrupt. */ -+ while (sb_desc && !IO_EXTRACT(USB_SB_command, intr, sb_desc->command)) { -+ sb_desc = sb_desc->next ? phys_to_virt(sb_desc->next) : 0; -+ } -+ ASSERT(sb_desc); -+ -+ isoc_dbg("Descr IRQ checking epid:%d sub:0x%x intr:0x%x\n", -+ epid, (unsigned int)phys_to_virt(TxIsocEPList[epid].sub), -+ (unsigned int)sb_desc); -+ -+ urb = activeUrbList[epid]; -+ if(urb == NULL) { -+ isoc_err("Isoc Descr irq on epid:%d with no active URB\n", epid); -+ continue; -+ } -+ -+ epid_done = 0; -+ while(urb && !epid_done) { -+ /* Sanity check. */ -+ ASSERT(usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS); -+ ASSERT(usb_pipeout(urb->pipe)); -+ -+ urb_priv = (struct crisv10_urb_priv *)urb->hcpriv; -+ ASSERT(urb_priv); -+ ASSERT(urb_priv->urb_state == STARTED || -+ urb_priv->urb_state == UNLINK); -+ -+ if (sb_desc != urb_priv->last_sb) { -+ /* This urb has been sent. */ -+ urb_priv->isoc_out_done = 1; -+ -+ } else { /* Found URB that has last_sb as the interrupt reason */ -+ -+ /* Check if EP has been disabled, meaning that all transfers are done*/ -+ if(!(TxIsocEPList[epid].command & IO_MASK(USB_EP_command, enable))) { -+ ASSERT((sb_desc->command & IO_MASK(USB_SB_command, eol)) == -+ IO_STATE(USB_SB_command, eol, yes)); -+ ASSERT(sb_desc->next == 0); -+ urb_priv->isoc_out_done = 1; -+ } else { -+ isoc_dbg("Skipping URB:0x%x[%d] because EP not disabled yet\n", -+ (unsigned int)urb, urb_priv->urb_num); -+ } -+ /* Stop looking any further in queue */ -+ epid_done = 1; -+ } -+ -+ if (!epid_done) { -+ if(urb == activeUrbList[epid]) { -+ urb = urb_list_first(epid); -+ } else { -+ urb = urb_list_next(urb, epid); -+ } -+ } -+ } /* END: while(urb && !epid_done) */ -+ } -+ -+ local_irq_restore(flags); -+} -+ -+ -+/* This is where the Out Isoc URBs are realy completed. This function is -+ scheduled from tc_dma_tx_interrupt() when one or more Out Isoc transfers -+ are done. This functions completes all URBs earlier marked with -+ isoc_out_done by fast interrupt routine check_finished_isoc_tx_epids() */ -+ -+static void complete_isoc_bottom_half(void *data) { -+ struct crisv10_isoc_complete_data *comp_data; -+ struct usb_iso_packet_descriptor *packet; -+ struct crisv10_urb_priv * urb_priv; -+ unsigned long flags; -+ struct urb* urb; -+ int epid_done; -+ int epid; -+ int i; -+ -+ comp_data = (struct crisv10_isoc_complete_data*)data; -+ -+ local_irq_save(flags); -+ -+ for (epid = 0; epid < NBR_OF_EPIDS - 1; epid++) { -+ if(!epid_inuse(epid) || !epid_isoc(epid) || !epid_out_traffic(epid) || epid == DUMMY_EPID) { -+ /* Only check valid Out Isoc epids */ -+ continue; -+ } -+ -+ isoc_dbg("Isoc bottom-half checking epid:%d, sub:0x%x\n", epid, -+ (unsigned int)phys_to_virt(TxIsocEPList[epid].sub)); -+ -+ /* The descriptor interrupt handler has marked all transmitted Out Isoc -+ URBs with isoc_out_done. Now we traverse all epids and for all that -+ have out Isoc traffic we traverse its URB list and complete the -+ transmitted URBs. */ -+ epid_done = 0; -+ while (!epid_done) { -+ -+ /* Get the active urb (if any) */ -+ urb = activeUrbList[epid]; -+ if (urb == 0) { -+ isoc_dbg("No active URB on epid:%d anymore\n", epid); -+ epid_done = 1; -+ continue; -+ } -+ -+ /* Sanity check. */ -+ ASSERT(usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS); -+ ASSERT(usb_pipeout(urb->pipe)); -+ -+ urb_priv = (struct crisv10_urb_priv *)urb->hcpriv; -+ ASSERT(urb_priv); -+ -+ if (!(urb_priv->isoc_out_done)) { -+ /* We have reached URB that isn't flaged done yet, stop traversing. */ -+ isoc_dbg("Stoped traversing Out Isoc URBs on epid:%d" -+ " before not yet flaged URB:0x%x[%d]\n", -+ epid, (unsigned int)urb, urb_priv->urb_num); -+ epid_done = 1; -+ continue; -+ } -+ -+ /* This urb has been sent. */ -+ isoc_dbg("Found URB:0x%x[%d] that is flaged isoc_out_done\n", -+ (unsigned int)urb, urb_priv->urb_num); -+ -+ /* Set ok on transfered packets for this URB and finish it */ -+ for (i = 0; i < urb->number_of_packets; i++) { -+ packet = &urb->iso_frame_desc[i]; -+ packet->status = 0; -+ packet->actual_length = packet->length; -+ } -+ urb_priv->isoc_packet_counter = urb->number_of_packets; -+ tc_finish_urb(comp_data->hcd, urb, 0); -+ -+ } /* END: while(!epid_done) */ -+ } /* END: for(epid...) */ -+ -+ local_irq_restore(flags); -+ kmem_cache_free(isoc_compl_cache, comp_data); -+} -+#endif -+ -+static void check_finished_intr_tx_epids(struct usb_hcd *hcd) { -+ unsigned long flags; -+ int epid; -+ struct urb *urb; -+ struct crisv10_urb_priv * urb_priv; -+ volatile struct USB_EP_Desc *curr_ep; /* Current EP, the iterator. */ -+ volatile struct USB_EP_Desc *next_ep; /* The EP after current. */ -+ -+ /* Protect TxintrEPList */ -+ local_irq_save(flags); -+ -+ for (epid = 0; epid < NBR_OF_EPIDS; epid++) { -+ if(!epid_inuse(epid) || !epid_intr(epid) || !epid_out_traffic(epid)) { -+ /* Nothing to see on this epid. Only check valid Out Intr epids */ -+ continue; -+ } -+ -+ urb = activeUrbList[epid]; -+ if(urb == 0) { -+ intr_warn("Found Out Intr epid:%d with no active URB\n", epid); -+ continue; -+ } -+ -+ /* Sanity check. */ -+ ASSERT(usb_pipetype(urb->pipe) == PIPE_INTERRUPT); -+ ASSERT(usb_pipeout(urb->pipe)); -+ -+ urb_priv = (struct crisv10_urb_priv *)urb->hcpriv; -+ ASSERT(urb_priv); -+ -+ /* Go through EPs between first and second sof-EP. It's here Out Intr EPs -+ are inserted.*/ -+ curr_ep = &TxIntrEPList[0]; -+ do { -+ next_ep = (struct USB_EP_Desc *)phys_to_virt(curr_ep->next); -+ if(next_ep == urb_priv->intr_ep_pool[0]) { -+ /* We found the Out Intr EP for this epid */ -+ -+ /* Disable it so it doesn't get processed again */ -+ next_ep->command &= ~IO_MASK(USB_EP_command, enable); -+ -+ /* Finish the active Out Intr URB with status OK */ -+ tc_finish_urb(hcd, urb, 0); -+ } -+ curr_ep = phys_to_virt(curr_ep->next); -+ } while (curr_ep != &TxIntrEPList[1]); -+ -+ } -+ local_irq_restore(flags); -+} -+ -+/* Interrupt handler for DMA8/IRQ24 with subchannels (called from hardware intr) */ -+static irqreturn_t tc_dma_tx_interrupt(int irq, void *vhc) { -+ struct usb_hcd *hcd = (struct usb_hcd*)vhc; -+ ASSERT(hcd); -+ -+ if (*R_IRQ_READ2 & IO_MASK(R_IRQ_READ2, dma8_sub0_descr)) { -+ /* Clear this interrupt */ -+ *R_DMA_CH8_SUB0_CLR_INTR = IO_STATE(R_DMA_CH8_SUB0_CLR_INTR, clr_descr, do); -+ restart_dma8_sub0(); -+ } -+ -+ if (*R_IRQ_READ2 & IO_MASK(R_IRQ_READ2, dma8_sub1_descr)) { -+ /* Clear this interrupt */ -+ *R_DMA_CH8_SUB1_CLR_INTR = IO_STATE(R_DMA_CH8_SUB1_CLR_INTR, clr_descr, do); -+ check_finished_ctrl_tx_epids(hcd); -+ } -+ -+ if (*R_IRQ_READ2 & IO_MASK(R_IRQ_READ2, dma8_sub2_descr)) { -+ /* Clear this interrupt */ -+ *R_DMA_CH8_SUB2_CLR_INTR = IO_STATE(R_DMA_CH8_SUB2_CLR_INTR, clr_descr, do); -+ check_finished_intr_tx_epids(hcd); -+ } -+ -+ /* hinko ignore usb_pipeisoc */ -+#if 0 -+ if (*R_IRQ_READ2 & IO_MASK(R_IRQ_READ2, dma8_sub3_descr)) { -+ struct crisv10_isoc_complete_data* comp_data; -+ -+ /* Flag done Out Isoc for later completion */ -+ check_finished_isoc_tx_epids(); -+ -+ /* Clear this interrupt */ -+ *R_DMA_CH8_SUB3_CLR_INTR = IO_STATE(R_DMA_CH8_SUB3_CLR_INTR, clr_descr, do); -+ /* Schedule bottom half of Out Isoc completion function. This function -+ finishes the URBs marked with isoc_out_done */ -+ comp_data = (struct crisv10_isoc_complete_data*) -+ kmem_cache_alloc(isoc_compl_cache, GFP_ATOMIC); -+ ASSERT(comp_data != NULL); -+ comp_data ->hcd = hcd; -+ -+ //INIT_WORK(&comp_data->usb_bh, complete_isoc_bottom_half, comp_data); -+ INIT_WORK(&comp_data->usb_bh, complete_isoc_bottom_half); -+ schedule_work(&comp_data->usb_bh); -+ } -+#endif -+ -+ return IRQ_HANDLED; -+} -+ -+/* Interrupt handler for DMA9/IRQ25 (called from hardware intr) */ -+static irqreturn_t tc_dma_rx_interrupt(int irq, void *vhc) { -+ unsigned long flags; -+ struct urb *urb; -+ struct usb_hcd *hcd = (struct usb_hcd*)vhc; -+ struct crisv10_urb_priv *urb_priv; -+ int epid = 0; -+ int real_error; -+ -+ ASSERT(hcd); -+ -+ /* Clear this interrupt. */ -+ *R_DMA_CH9_CLR_INTR = IO_STATE(R_DMA_CH9_CLR_INTR, clr_eop, do); -+ -+ /* Custom clear interrupt for this interrupt */ -+ /* The reason we cli here is that we call the driver's callback functions. */ -+ local_irq_save(flags); -+ -+ /* Note that this while loop assumes that all packets span only -+ one rx descriptor. */ -+ while(myNextRxDesc->status & IO_MASK(USB_IN_status, eop)) { -+ epid = IO_EXTRACT(USB_IN_status, epid, myNextRxDesc->status); -+ /* Get the active URB for this epid */ -+ urb = activeUrbList[epid]; -+ -+ ASSERT(epid_inuse(epid)); -+ if (!urb) { -+ dma_err("No urb for epid %d in rx interrupt\n", epid); -+ goto skip_out; -+ } -+ -+ /* Check if any errors on epid */ -+ real_error = 0; -+ if (myNextRxDesc->status & IO_MASK(USB_IN_status, error)) { -+ __u32 r_usb_ept_data; -+ -+ if (usb_pipeisoc(urb->pipe)) { -+ r_usb_ept_data = etrax_epid_iso_get(epid); -+ if((r_usb_ept_data & IO_MASK(R_USB_EPT_DATA_ISO, valid)) && -+ (IO_EXTRACT(R_USB_EPT_DATA_ISO, error_code, r_usb_ept_data) == 0) && -+ (myNextRxDesc->status & IO_MASK(USB_IN_status, nodata))) { -+ /* Not an error, just a failure to receive an expected iso -+ in packet in this frame. This is not documented -+ in the designers reference. Continue processing. -+ */ -+ } else real_error = 1; -+ } else real_error = 1; -+ } -+ -+ if(real_error) { -+ dma_err("Error in RX descr on epid:%d for URB 0x%x", -+ epid, (unsigned int)urb); -+ dump_ept_data(epid); -+ dump_in_desc(myNextRxDesc); -+ goto skip_out; -+ } -+ -+ urb_priv = (struct crisv10_urb_priv *)urb->hcpriv; -+ ASSERT(urb_priv); -+ ASSERT(urb_priv->urb_state == STARTED || -+ urb_priv->urb_state == UNLINK); -+ -+ if ((usb_pipetype(urb->pipe) == PIPE_BULK) || -+ (usb_pipetype(urb->pipe) == PIPE_CONTROL) || -+ (usb_pipetype(urb->pipe) == PIPE_INTERRUPT)) { -+ -+ /* We get nodata for empty data transactions, and the rx descriptor's -+ hw_len field is not valid in that case. No data to copy in other -+ words. */ -+ if (myNextRxDesc->status & IO_MASK(USB_IN_status, nodata)) { -+ /* No data to copy */ -+ } else { -+ /* -+ dma_dbg("Processing RX for URB:0x%x epid:%d (data:%d ofs:%d)\n", -+ (unsigned int)urb, epid, myNextRxDesc->hw_len, -+ urb_priv->rx_offset); -+ */ -+ /* Only copy data if URB isn't flaged to be unlinked*/ -+ if(urb_priv->urb_state != UNLINK) { -+ /* Make sure the data fits in the buffer. */ -+ if(urb_priv->rx_offset + myNextRxDesc->hw_len -+ <= urb->transfer_buffer_length) { -+ -+ /* Copy the data to URBs buffer */ -+ memcpy(urb->transfer_buffer + urb_priv->rx_offset, -+ phys_to_virt(myNextRxDesc->buf), myNextRxDesc->hw_len); -+ urb_priv->rx_offset += myNextRxDesc->hw_len; -+ } else { -+ /* Signal overflow when returning URB */ -+ urb->status = -EOVERFLOW; -+ tc_finish_urb_later(hcd, urb, urb->status); -+ } -+ } -+ } -+ -+ /* Check if it was the last packet in the transfer */ -+ if (myNextRxDesc->status & IO_MASK(USB_IN_status, eot)) { -+ /* Special handling for In Ctrl URBs. */ -+ if(usb_pipecontrol(urb->pipe) && usb_pipein(urb->pipe) && -+ !(urb_priv->ctrl_zout_done)) { -+ /* Flag that RX part of Ctrl transfer is done. Because zout descr -+ interrupt hasn't happend yet will the URB be finished in the -+ TX-Interrupt. */ -+ urb_priv->ctrl_rx_done = 1; -+ tc_dbg("Not finishing In Ctrl URB:0x%x from rx_interrupt, waiting" -+ " for zout\n", (unsigned int)urb); -+ } else { -+ tc_finish_urb(hcd, urb, 0); -+ } -+ } -+ } else { /* ISOC RX */ -+ /* -+ isoc_dbg("Processing RX for epid:%d (URB:0x%x) ISOC pipe\n", -+ epid, (unsigned int)urb); -+ */ -+ -+ struct usb_iso_packet_descriptor *packet; -+ -+ if (urb_priv->urb_state == UNLINK) { -+ isoc_warn("Ignoring Isoc Rx data for urb being unlinked.\n"); -+ goto skip_out; -+ } else if (urb_priv->urb_state == NOT_STARTED) { -+ isoc_err("What? Got Rx data for Isoc urb that isn't started?\n"); -+ goto skip_out; -+ } -+ -+ packet = &urb->iso_frame_desc[urb_priv->isoc_packet_counter]; -+ ASSERT(packet); -+ packet->status = 0; -+ -+ if (myNextRxDesc->status & IO_MASK(USB_IN_status, nodata)) { -+ /* We get nodata for empty data transactions, and the rx descriptor's -+ hw_len field is not valid in that case. We copy 0 bytes however to -+ stay in synch. */ -+ packet->actual_length = 0; -+ } else { -+ packet->actual_length = myNextRxDesc->hw_len; -+ /* Make sure the data fits in the buffer. */ -+ ASSERT(packet->actual_length <= packet->length); -+ memcpy(urb->transfer_buffer + packet->offset, -+ phys_to_virt(myNextRxDesc->buf), packet->actual_length); -+ if(packet->actual_length > 0) -+ isoc_dbg("Copied %d bytes, packet %d for URB:0x%x[%d]\n", -+ packet->actual_length, urb_priv->isoc_packet_counter, -+ (unsigned int)urb, urb_priv->urb_num); -+ } -+ -+ /* Increment the packet counter. */ -+ urb_priv->isoc_packet_counter++; -+ -+ /* Note that we don't care about the eot field in the rx descriptor's -+ status. It will always be set for isoc traffic. */ -+ if (urb->number_of_packets == urb_priv->isoc_packet_counter) { -+ /* Complete the urb with status OK. */ -+ tc_finish_urb(hcd, urb, 0); -+ } -+ } -+ -+ skip_out: -+ myNextRxDesc->status = 0; -+ myNextRxDesc->command |= IO_MASK(USB_IN_command, eol); -+ myLastRxDesc->command &= ~IO_MASK(USB_IN_command, eol); -+ myLastRxDesc = myNextRxDesc; -+ myNextRxDesc = phys_to_virt(myNextRxDesc->next); -+ flush_etrax_cache(); -+ *R_DMA_CH9_CMD = IO_STATE(R_DMA_CH9_CMD, cmd, restart); -+ } -+ -+ local_irq_restore(flags); -+ -+ return IRQ_HANDLED; -+} -+ -+static void tc_bulk_start_timer_func(unsigned long dummy) { -+ /* We might enable an EP descriptor behind the current DMA position when -+ it's about to decide that there are no more bulk traffic and it should -+ stop the bulk channel. -+ Therefore we periodically check if the bulk channel is stopped and there -+ is an enabled bulk EP descriptor, in which case we start the bulk -+ channel. */ -+ -+ if (!(*R_DMA_CH8_SUB0_CMD & IO_MASK(R_DMA_CH8_SUB0_CMD, cmd))) { -+ int epid; -+ -+ timer_dbg("bulk_start_timer: Bulk DMA channel not running.\n"); -+ -+ for (epid = 0; epid < NBR_OF_EPIDS; epid++) { -+ if (TxBulkEPList[epid].command & IO_MASK(USB_EP_command, enable)) { -+ timer_warn("Found enabled EP for epid %d, starting bulk channel.\n", -+ epid); -+ restart_dma8_sub0(); -+ -+ /* Restart the bulk eot timer since we just started the bulk channel.*/ -+ mod_timer(&bulk_eot_timer, jiffies + BULK_EOT_TIMER_INTERVAL); -+ -+ /* No need to search any further. */ -+ break; -+ } -+ } -+ } else { -+ timer_dbg("bulk_start_timer: Bulk DMA channel running.\n"); -+ } -+} -+ -+static void tc_bulk_eot_timer_func(unsigned long dummy) { -+ struct usb_hcd *hcd = (struct usb_hcd*)dummy; -+ ASSERT(hcd); -+ /* Because of a race condition in the top half, we might miss a bulk eot. -+ This timer "simulates" a bulk eot if we don't get one for a while, -+ hopefully correcting the situation. */ -+ timer_dbg("bulk_eot_timer timed out.\n"); -+ check_finished_bulk_tx_epids(hcd, 1); -+} -+ -+ -+/*************************************************************/ -+/*************************************************************/ -+/* Device driver block */ -+/*************************************************************/ -+/*************************************************************/ -+ -+/* Forward declarations for device driver functions */ -+static int devdrv_hcd_probe(struct device *); -+static int devdrv_hcd_remove(struct device *); -+#ifdef CONFIG_PM -+static int devdrv_hcd_suspend(struct device *, u32, u32); -+static int devdrv_hcd_resume(struct device *, u32); -+#endif /* CONFIG_PM */ -+ -+/* the device */ -+static struct platform_device *devdrv_hc_platform_device; -+ -+/* device driver interface */ -+static struct device_driver devdrv_hc_device_driver = { -+ .name = (char *) hc_name, -+ .bus = &platform_bus_type, -+ -+ .probe = devdrv_hcd_probe, -+ .remove = devdrv_hcd_remove, -+ -+#ifdef CONFIG_PM -+ .suspend = devdrv_hcd_suspend, -+ .resume = devdrv_hcd_resume, -+#endif /* CONFIG_PM */ -+}; -+ -+/* initialize the host controller and driver */ -+static int __init_or_module devdrv_hcd_probe(struct device *dev) -+{ -+ struct usb_hcd *hcd; -+ struct crisv10_hcd *crisv10_hcd; -+ int retval; -+ int rev_maj, rev_min; -+ -+ /* Check DMA burst length */ -+ if(IO_EXTRACT(R_BUS_CONFIG, dma_burst, *R_BUS_CONFIG) != -+ IO_STATE(R_BUS_CONFIG, dma_burst, burst32)) { -+ devdrv_err("Invalid DMA burst length in Etrax 100LX," -+ " needs to be 32\n"); -+ return -EPERM; -+ } -+ -+ hcd = usb_create_hcd(&crisv10_hc_driver, dev, dev_name(dev)); -+ if (!hcd) -+ return -ENOMEM; -+ -+ crisv10_hcd = hcd_to_crisv10_hcd(hcd); -+ spin_lock_init(&crisv10_hcd->lock); -+ crisv10_hcd->num_ports = num_ports(); -+ crisv10_hcd->running = 0; -+ -+ dev_set_drvdata(dev, crisv10_hcd); -+ -+ devdrv_dbg("ETRAX USB IRQs HC:%d RX:%d TX:%d\n", ETRAX_USB_HC_IRQ, -+ ETRAX_USB_RX_IRQ, ETRAX_USB_TX_IRQ); -+ -+ /* Print out chip version read from registers */ -+ rev_maj = *R_USB_REVISION & IO_MASK(R_USB_REVISION, major); -+ rev_min = *R_USB_REVISION & IO_MASK(R_USB_REVISION, minor); -+ if(rev_min == 0) { -+ devdrv_info("Etrax 100LX USB Revision %d v1,2\n", rev_maj); -+ } else { -+ devdrv_info("Etrax 100LX USB Revision %d v%d\n", rev_maj, rev_min); -+ } -+ -+ devdrv_info("Bulk timer interval, start:%d eot:%d\n", -+ BULK_START_TIMER_INTERVAL, -+ BULK_EOT_TIMER_INTERVAL); -+ -+ -+ /* Init root hub data structures */ -+ if(rh_init()) { -+ devdrv_err("Failed init data for Root Hub\n"); -+ retval = -ENOMEM; -+ } -+ -+ if(port_in_use(0)) { -+ if (cris_request_io_interface(if_usb_1, "ETRAX100LX USB-HCD")) { -+ printk(KERN_CRIT "usb-host: request IO interface usb1 failed"); -+ retval = -EBUSY; -+ goto out; -+ } -+ devdrv_info("Claimed interface for USB physical port 1\n"); -+ } -+ if(port_in_use(1)) { -+ if (cris_request_io_interface(if_usb_2, "ETRAX100LX USB-HCD")) { -+ /* Free first interface if second failed to be claimed */ -+ if(port_in_use(0)) { -+ cris_free_io_interface(if_usb_1); -+ } -+ printk(KERN_CRIT "usb-host: request IO interface usb2 failed"); -+ retval = -EBUSY; -+ goto out; -+ } -+ devdrv_info("Claimed interface for USB physical port 2\n"); -+ } -+ -+ /* Init transfer controller structs and locks */ -+ if((retval = tc_init(hcd)) != 0) { -+ goto out; -+ } -+ -+ /* Attach interrupt functions for DMA and init DMA controller */ -+ if((retval = tc_dma_init(hcd)) != 0) { -+ goto out; -+ } -+ -+ /* Attach the top IRQ handler for USB controller interrupts */ -+ if (request_irq(ETRAX_USB_HC_IRQ, crisv10_hcd_top_irq, 0, -+ "ETRAX 100LX built-in USB (HC)", hcd)) { -+ err("Could not allocate IRQ %d for USB", ETRAX_USB_HC_IRQ); -+ retval = -EBUSY; -+ goto out; -+ } -+ -+ /* iso_eof is only enabled when isoc traffic is running. */ -+ *R_USB_IRQ_MASK_SET = -+ /* IO_STATE(R_USB_IRQ_MASK_SET, iso_eof, set) | */ -+ IO_STATE(R_USB_IRQ_MASK_SET, bulk_eot, set) | -+ IO_STATE(R_USB_IRQ_MASK_SET, epid_attn, set) | -+ IO_STATE(R_USB_IRQ_MASK_SET, port_status, set) | -+ IO_STATE(R_USB_IRQ_MASK_SET, ctl_status, set); -+ -+ -+ crisv10_ready_wait(); -+ /* Reset the USB interface. */ -+ *R_USB_COMMAND = -+ IO_STATE(R_USB_COMMAND, port_sel, nop) | -+ IO_STATE(R_USB_COMMAND, port_cmd, reset) | -+ IO_STATE(R_USB_COMMAND, ctrl_cmd, reset); -+ -+ /* Designer's Reference, p. 8 - 10 says we should Initate R_USB_FM_PSTART to -+ 0x2A30 (10800), to guarantee that control traffic gets 10% of the -+ bandwidth, and periodic transfer may allocate the rest (90%). -+ This doesn't work though. -+ The value 11960 is chosen to be just after the SOF token, with a couple -+ of bit times extra for possible bit stuffing. */ -+ *R_USB_FM_PSTART = IO_FIELD(R_USB_FM_PSTART, value, 11960); -+ -+ crisv10_ready_wait(); -+ /* Configure the USB interface as a host controller. */ -+ *R_USB_COMMAND = -+ IO_STATE(R_USB_COMMAND, port_sel, nop) | -+ IO_STATE(R_USB_COMMAND, port_cmd, reset) | -+ IO_STATE(R_USB_COMMAND, ctrl_cmd, host_config); -+ -+ -+ /* Check so controller not busy before enabling ports */ -+ crisv10_ready_wait(); -+ -+ /* Enable selected USB ports */ -+ if(port_in_use(0)) { -+ *R_USB_PORT1_DISABLE = IO_STATE(R_USB_PORT1_DISABLE, disable, no); -+ } else { -+ *R_USB_PORT1_DISABLE = IO_STATE(R_USB_PORT1_DISABLE, disable, yes); -+ } -+ if(port_in_use(1)) { -+ *R_USB_PORT2_DISABLE = IO_STATE(R_USB_PORT2_DISABLE, disable, no); -+ } else { -+ *R_USB_PORT2_DISABLE = IO_STATE(R_USB_PORT2_DISABLE, disable, yes); -+ } -+ -+ crisv10_ready_wait(); -+ /* Start processing of USB traffic. */ -+ *R_USB_COMMAND = -+ IO_STATE(R_USB_COMMAND, port_sel, nop) | -+ IO_STATE(R_USB_COMMAND, port_cmd, reset) | -+ IO_STATE(R_USB_COMMAND, ctrl_cmd, host_run); -+ -+ /* Do not continue probing initialization before USB interface is done */ -+ crisv10_ready_wait(); -+ -+ /* Register our Host Controller to USB Core -+ * Finish the remaining parts of generic HCD initialization: allocate the -+ * buffers of consistent memory, register the bus -+ * and call the driver's reset() and start() routines. */ -+ retval = usb_add_hcd(hcd, ETRAX_USB_HC_IRQ, IRQF_DISABLED); -+ if (retval != 0) { -+ devdrv_err("Failed registering HCD driver\n"); -+ goto out; -+ } -+ -+ return 0; -+ -+ out: -+ devdrv_hcd_remove(dev); -+ return retval; -+} -+ -+ -+/* cleanup after the host controller and driver */ -+static int __init_or_module devdrv_hcd_remove(struct device *dev) -+{ -+ struct crisv10_hcd *crisv10_hcd = dev_get_drvdata(dev); -+ struct usb_hcd *hcd; -+ -+ if (!crisv10_hcd) -+ return 0; -+ hcd = crisv10_hcd_to_hcd(crisv10_hcd); -+ -+ -+ /* Stop USB Controller in Etrax 100LX */ -+ crisv10_hcd_reset(hcd); -+ -+ usb_remove_hcd(hcd); -+ devdrv_dbg("Removed HCD from USB Core\n"); -+ -+ /* Free USB Controller IRQ */ -+ free_irq(ETRAX_USB_HC_IRQ, NULL); -+ -+ /* Free resources */ -+ tc_dma_destroy(); -+ tc_destroy(); -+ -+ -+ if(port_in_use(0)) { -+ cris_free_io_interface(if_usb_1); -+ } -+ if(port_in_use(1)) { -+ cris_free_io_interface(if_usb_2); -+ } -+ -+ devdrv_dbg("Freed all claimed resources\n"); -+ -+ return 0; -+} -+ -+ -+#ifdef CONFIG_PM -+ -+static int devdrv_hcd_suspend(struct usb_hcd *hcd, u32 state, u32 level) -+{ -+ return 0; /* no-op for now */ -+} -+ -+static int devdrv_hcd_resume(struct usb_hcd *hcd, u32 level) -+{ -+ return 0; /* no-op for now */ -+} -+ -+#endif /* CONFIG_PM */ -+ -+ -+ -+/*************************************************************/ -+/*************************************************************/ -+/* Module block */ -+/*************************************************************/ -+/*************************************************************/ -+ -+/* register driver */ -+static int __init module_hcd_init(void) -+{ -+ -+ if (usb_disabled()) -+ return -ENODEV; -+ -+ /* Here we select enabled ports by following defines created from -+ menuconfig */ -+#ifndef CONFIG_ETRAX_USB_HOST_PORT1 -+ ports &= ~(1<<0); -+#endif -+#ifndef CONFIG_ETRAX_USB_HOST_PORT2 -+ ports &= ~(1<<1); -+#endif -+ -+ printk(KERN_INFO "%s version "VERSION" "COPYRIGHT"\n", product_desc); -+ -+ devdrv_hc_platform_device = -+ platform_device_register_simple((char *) hc_name, 0, NULL, 0); -+ -+ if (IS_ERR(devdrv_hc_platform_device)) -+ return PTR_ERR(devdrv_hc_platform_device); -+ return driver_register(&devdrv_hc_device_driver); -+ /* -+ * Note that we do not set the DMA mask for the device, -+ * i.e. we pretend that we will use PIO, since no specific -+ * allocation routines are needed for DMA buffers. This will -+ * cause the HCD buffer allocation routines to fall back to -+ * kmalloc(). -+ */ -+} -+ -+/* unregister driver */ -+static void __exit module_hcd_exit(void) -+{ -+ driver_unregister(&devdrv_hc_device_driver); -+} -+ -+ -+/* Module hooks */ -+module_init(module_hcd_init); -+module_exit(module_hcd_exit); -diff -Nur linux-2.6.37.orig/drivers/usb/host/hc-crisv10.h linux-2.6.37/drivers/usb/host/hc-crisv10.h ---- linux-2.6.37.orig/drivers/usb/host/hc-crisv10.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/drivers/usb/host/hc-crisv10.h 2011-04-27 12:05:31.917663433 +0200 -@@ -0,0 +1,331 @@ -+#ifndef __LINUX_ETRAX_USB_H -+#define __LINUX_ETRAX_USB_H -+ -+#include -+#include -+ -+struct USB_IN_Desc { -+ volatile __u16 sw_len; -+ volatile __u16 command; -+ volatile unsigned long next; -+ volatile unsigned long buf; -+ volatile __u16 hw_len; -+ volatile __u16 status; -+}; -+ -+struct USB_SB_Desc { -+ volatile __u16 sw_len; -+ volatile __u16 command; -+ volatile unsigned long next; -+ volatile unsigned long buf; -+}; -+ -+struct USB_EP_Desc { -+ volatile __u16 hw_len; -+ volatile __u16 command; -+ volatile unsigned long sub; -+ volatile unsigned long next; -+}; -+ -+ -+/* Root Hub port status struct */ -+struct crisv10_rh { -+ volatile __u16 wPortChange[2]; -+ volatile __u16 wPortStatusPrev[2]; -+}; -+ -+/* HCD description */ -+struct crisv10_hcd { -+ spinlock_t lock; -+ __u8 num_ports; -+ __u8 running; -+}; -+ -+ -+/* Endpoint HC private data description */ -+struct crisv10_ep_priv { -+ int epid; -+}; -+ -+/* Additional software state info for a USB Controller epid */ -+struct etrax_epid { -+ __u8 inuse; /* !0 = setup in Etrax and used for a endpoint */ -+ __u8 disabled; /* !0 = Temporarly disabled to avoid resubmission */ -+ __u8 type; /* Setup as: PIPE_BULK, PIPE_CONTROL ... */ -+ __u8 out_traffic; /* !0 = This epid is for out traffic */ -+}; -+ -+/* Struct to hold information of scheduled later URB completion */ -+struct urb_later_data { -+// struct work_struct ws; -+ struct delayed_work ws; -+ struct usb_hcd *hcd; -+ struct urb *urb; -+ int urb_num; -+ int status; -+}; -+ -+ -+typedef enum { -+ STARTED, -+ NOT_STARTED, -+ UNLINK, -+} crisv10_urb_state_t; -+ -+ -+struct crisv10_urb_priv { -+ /* Sequence number for this URB. Every new submited URB gets this from -+ a incrementing counter. Used when a URB is scheduled for later finish to -+ be sure that the intended URB hasn't already been completed (device -+ drivers has a tendency to reuse URBs once they are completed, causing us -+ to not be able to single old ones out only based on the URB pointer.) */ -+ __u32 urb_num; -+ -+ /* The first_sb field is used for freeing all SB descriptors belonging -+ to an urb. The corresponding ep descriptor's sub pointer cannot be -+ used for this since the DMA advances the sub pointer as it processes -+ the sb list. */ -+ struct USB_SB_Desc *first_sb; -+ -+ /* The last_sb field referes to the last SB descriptor that belongs to -+ this urb. This is important to know so we can free the SB descriptors -+ that ranges between first_sb and last_sb. */ -+ struct USB_SB_Desc *last_sb; -+ -+ /* The rx_offset field is used in ctrl and bulk traffic to keep track -+ of the offset in the urb's transfer_buffer where incoming data should be -+ copied to. */ -+ __u32 rx_offset; -+ -+ /* Counter used in isochronous transfers to keep track of the -+ number of packets received/transmitted. */ -+ __u32 isoc_packet_counter; -+ -+ /* Flag that marks if this Isoc Out URB has finished it's transfer. Used -+ because several URBs can be finished before list is processed */ -+ __u8 isoc_out_done; -+ -+ /* This field is used to pass information about the urb's current state -+ between the various interrupt handlers (thus marked volatile). */ -+ volatile crisv10_urb_state_t urb_state; -+ -+ /* In Ctrl transfers consist of (at least) 3 packets: SETUP, IN and ZOUT. -+ When DMA8 sub-channel 2 has processed the SB list for this sequence we -+ get a interrupt. We also get a interrupt for In transfers and which -+ one of these interrupts that comes first depends of data size and device. -+ To be sure that we have got both interrupts before we complete the URB -+ we have these to flags that shows which part that has completed. -+ We can then check when we get one of the interrupts that if the other has -+ occured it's safe for us to complete the URB, otherwise we set appropriate -+ flag and do the completion when we get the other interrupt. */ -+ volatile unsigned char ctrl_zout_done; -+ volatile unsigned char ctrl_rx_done; -+ -+ /* Connection between the submitted urb and ETRAX epid number */ -+ __u8 epid; -+ -+ /* The rx_data_list field is used for periodic traffic, to hold -+ received data for later processing in the the complete_urb functions, -+ where the data us copied to the urb's transfer_buffer. Basically, we -+ use this intermediate storage because we don't know when it's safe to -+ reuse the transfer_buffer (FIXME?). */ -+ struct list_head rx_data_list; -+ -+ -+ /* The interval time rounded up to closest 2^N */ -+ int interval; -+ -+ /* Pool of EP descriptors needed if it's a INTR transfer. -+ Amount of EPs in pool correspons to how many INTR that should -+ be inserted in TxIntrEPList (max 128, defined by MAX_INTR_INTERVAL) */ -+ struct USB_EP_Desc* intr_ep_pool[128]; -+ -+ /* The mount of EPs allocated for this INTR URB */ -+ int intr_ep_pool_length; -+ -+ /* Pointer to info struct if URB is scheduled to be finished later */ -+ struct urb_later_data* later_data; -+}; -+ -+ -+/* This struct is for passing data from the top half to the bottom half irq -+ handlers */ -+struct crisv10_irq_reg { -+ struct usb_hcd* hcd; -+ __u32 r_usb_epid_attn; -+ __u8 r_usb_status; -+ __u16 r_usb_rh_port_status_1; -+ __u16 r_usb_rh_port_status_2; -+ __u32 r_usb_irq_mask_read; -+ __u32 r_usb_fm_number; -+ struct work_struct usb_bh; -+}; -+ -+ -+/* This struct is for passing data from the isoc top half to the isoc bottom -+ half. */ -+struct crisv10_isoc_complete_data { -+ struct usb_hcd *hcd; -+ struct urb *urb; -+ struct work_struct usb_bh; -+}; -+ -+/* Entry item for URB lists for each endpint */ -+typedef struct urb_entry -+{ -+ struct urb *urb; -+ struct list_head list; -+} urb_entry_t; -+ -+/* --------------------------------------------------------------------------- -+ Virtual Root HUB -+ ------------------------------------------------------------------------- */ -+/* destination of request */ -+#define RH_INTERFACE 0x01 -+#define RH_ENDPOINT 0x02 -+#define RH_OTHER 0x03 -+ -+#define RH_CLASS 0x20 -+#define RH_VENDOR 0x40 -+ -+/* Requests: bRequest << 8 | bmRequestType */ -+#define RH_GET_STATUS 0x0080 -+#define RH_CLEAR_FEATURE 0x0100 -+#define RH_SET_FEATURE 0x0300 -+#define RH_SET_ADDRESS 0x0500 -+#define RH_GET_DESCRIPTOR 0x0680 -+#define RH_SET_DESCRIPTOR 0x0700 -+#define RH_GET_CONFIGURATION 0x0880 -+#define RH_SET_CONFIGURATION 0x0900 -+#define RH_GET_STATE 0x0280 -+#define RH_GET_INTERFACE 0x0A80 -+#define RH_SET_INTERFACE 0x0B00 -+#define RH_SYNC_FRAME 0x0C80 -+/* Our Vendor Specific Request */ -+#define RH_SET_EP 0x2000 -+ -+ -+/* Hub port features */ -+#define RH_PORT_CONNECTION 0x00 -+#define RH_PORT_ENABLE 0x01 -+#define RH_PORT_SUSPEND 0x02 -+#define RH_PORT_OVER_CURRENT 0x03 -+#define RH_PORT_RESET 0x04 -+#define RH_PORT_POWER 0x08 -+#define RH_PORT_LOW_SPEED 0x09 -+#define RH_C_PORT_CONNECTION 0x10 -+#define RH_C_PORT_ENABLE 0x11 -+#define RH_C_PORT_SUSPEND 0x12 -+#define RH_C_PORT_OVER_CURRENT 0x13 -+#define RH_C_PORT_RESET 0x14 -+ -+/* Hub features */ -+#define RH_C_HUB_LOCAL_POWER 0x00 -+#define RH_C_HUB_OVER_CURRENT 0x01 -+ -+#define RH_DEVICE_REMOTE_WAKEUP 0x00 -+#define RH_ENDPOINT_STALL 0x01 -+ -+/* Our Vendor Specific feature */ -+#define RH_REMOVE_EP 0x00 -+ -+ -+#define RH_ACK 0x01 -+#define RH_REQ_ERR -1 -+#define RH_NACK 0x00 -+ -+/* Field definitions for */ -+ -+#define USB_IN_command__eol__BITNR 0 /* command macros */ -+#define USB_IN_command__eol__WIDTH 1 -+#define USB_IN_command__eol__no 0 -+#define USB_IN_command__eol__yes 1 -+ -+#define USB_IN_command__intr__BITNR 3 -+#define USB_IN_command__intr__WIDTH 1 -+#define USB_IN_command__intr__no 0 -+#define USB_IN_command__intr__yes 1 -+ -+#define USB_IN_status__eop__BITNR 1 /* status macros. */ -+#define USB_IN_status__eop__WIDTH 1 -+#define USB_IN_status__eop__no 0 -+#define USB_IN_status__eop__yes 1 -+ -+#define USB_IN_status__eot__BITNR 5 -+#define USB_IN_status__eot__WIDTH 1 -+#define USB_IN_status__eot__no 0 -+#define USB_IN_status__eot__yes 1 -+ -+#define USB_IN_status__error__BITNR 6 -+#define USB_IN_status__error__WIDTH 1 -+#define USB_IN_status__error__no 0 -+#define USB_IN_status__error__yes 1 -+ -+#define USB_IN_status__nodata__BITNR 7 -+#define USB_IN_status__nodata__WIDTH 1 -+#define USB_IN_status__nodata__no 0 -+#define USB_IN_status__nodata__yes 1 -+ -+#define USB_IN_status__epid__BITNR 8 -+#define USB_IN_status__epid__WIDTH 5 -+ -+#define USB_EP_command__eol__BITNR 0 -+#define USB_EP_command__eol__WIDTH 1 -+#define USB_EP_command__eol__no 0 -+#define USB_EP_command__eol__yes 1 -+ -+#define USB_EP_command__eof__BITNR 1 -+#define USB_EP_command__eof__WIDTH 1 -+#define USB_EP_command__eof__no 0 -+#define USB_EP_command__eof__yes 1 -+ -+#define USB_EP_command__intr__BITNR 3 -+#define USB_EP_command__intr__WIDTH 1 -+#define USB_EP_command__intr__no 0 -+#define USB_EP_command__intr__yes 1 -+ -+#define USB_EP_command__enable__BITNR 4 -+#define USB_EP_command__enable__WIDTH 1 -+#define USB_EP_command__enable__no 0 -+#define USB_EP_command__enable__yes 1 -+ -+#define USB_EP_command__hw_valid__BITNR 5 -+#define USB_EP_command__hw_valid__WIDTH 1 -+#define USB_EP_command__hw_valid__no 0 -+#define USB_EP_command__hw_valid__yes 1 -+ -+#define USB_EP_command__epid__BITNR 8 -+#define USB_EP_command__epid__WIDTH 5 -+ -+#define USB_SB_command__eol__BITNR 0 /* command macros. */ -+#define USB_SB_command__eol__WIDTH 1 -+#define USB_SB_command__eol__no 0 -+#define USB_SB_command__eol__yes 1 -+ -+#define USB_SB_command__eot__BITNR 1 -+#define USB_SB_command__eot__WIDTH 1 -+#define USB_SB_command__eot__no 0 -+#define USB_SB_command__eot__yes 1 -+ -+#define USB_SB_command__intr__BITNR 3 -+#define USB_SB_command__intr__WIDTH 1 -+#define USB_SB_command__intr__no 0 -+#define USB_SB_command__intr__yes 1 -+ -+#define USB_SB_command__tt__BITNR 4 -+#define USB_SB_command__tt__WIDTH 2 -+#define USB_SB_command__tt__zout 0 -+#define USB_SB_command__tt__in 1 -+#define USB_SB_command__tt__out 2 -+#define USB_SB_command__tt__setup 3 -+ -+ -+#define USB_SB_command__rem__BITNR 8 -+#define USB_SB_command__rem__WIDTH 6 -+ -+#define USB_SB_command__full__BITNR 6 -+#define USB_SB_command__full__WIDTH 1 -+#define USB_SB_command__full__no 0 -+#define USB_SB_command__full__yes 1 -+ -+#endif -diff -Nur linux-2.6.37.orig/drivers/usb/host/Makefile linux-2.6.37/drivers/usb/host/Makefile ---- linux-2.6.37.orig/drivers/usb/host/Makefile 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/usb/host/Makefile 2011-04-27 12:05:31.787668204 +0200 -@@ -32,6 +32,7 @@ - obj-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o - obj-$(CONFIG_USB_ISP1760_HCD) += isp1760.o - obj-$(CONFIG_USB_HWA_HCD) += hwa-hc.o -+obj-$(CONFIG_ETRAX_USB_HOST) += hc-crisv10.o - obj-$(CONFIG_USB_IMX21_HCD) += imx21-hcd.o - obj-$(CONFIG_USB_FSL_MPH_DR_OF) += fsl-mph-dr-of.o - obj-$(CONFIG_USB_OCTEON2_COMMON) += octeon2-common.o -diff -Nur linux-2.6.37.orig/drivers/usb/Makefile linux-2.6.37/drivers/usb/Makefile ---- linux-2.6.37.orig/drivers/usb/Makefile 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/usb/Makefile 2011-04-27 12:05:31.717665249 +0200 -@@ -21,6 +21,7 @@ - obj-$(CONFIG_USB_R8A66597_HCD) += host/ - obj-$(CONFIG_USB_HWA_HCD) += host/ - obj-$(CONFIG_USB_ISP1760_HCD) += host/ -+obj-$(CONFIG_ETRAX_USB_HOST) += host/ - obj-$(CONFIG_USB_IMX21_HCD) += host/ - - obj-$(CONFIG_USB_C67X00_HCD) += c67x00/ -diff -Nur linux-2.6.37.orig/lib/klist.c linux-2.6.37/lib/klist.c ---- linux-2.6.37.orig/lib/klist.c 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/lib/klist.c 2011-04-27 12:05:31.967661872 +0200 -@@ -60,7 +60,7 @@ - { - knode->n_klist = klist; - /* no knode deserves to start its life dead */ -- WARN_ON(knode_dead(knode)); -+ //WARN_ON(knode_dead(knode)); - } - - static void knode_kill(struct klist_node *knode) diff --git a/target/linux/patches/2.6.37/cygwin-compat.patch b/target/linux/patches/2.6.37/cygwin-compat.patch deleted file mode 100644 index 17258e565..000000000 --- a/target/linux/patches/2.6.37/cygwin-compat.patch +++ /dev/null @@ -1,14 +0,0 @@ -diff -Nur linux-2.6.30.orig/scripts/mod/file2alias.c linux-2.6.30/scripts/mod/file2alias.c ---- linux-2.6.30.orig/scripts/mod/file2alias.c 2009-06-10 05:05:27.000000000 +0200 -+++ linux-2.6.30/scripts/mod/file2alias.c 2009-06-11 09:17:10.000000000 +0200 -@@ -29,7 +29,11 @@ - - #include - -+#ifdef __CYGWIN__ -+typedef __uint32_t __u32; -+#else - typedef uint32_t __u32; -+#endif - typedef uint16_t __u16; - typedef unsigned char __u8; diff --git a/target/linux/patches/2.6.37/drm-kconfig.patch b/target/linux/patches/2.6.37/drm-kconfig.patch deleted file mode 100644 index cfeb599f8..000000000 --- a/target/linux/patches/2.6.37/drm-kconfig.patch +++ /dev/null @@ -1,36 +0,0 @@ -diff -Nur linux-2.6.37.orig/drivers/gpu/drm/Kconfig linux-2.6.37/drivers/gpu/drm/Kconfig ---- linux-2.6.37.orig/drivers/gpu/drm/Kconfig 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/gpu/drm/Kconfig 2011-01-11 20:20:26.000000000 +0100 -@@ -80,23 +80,6 @@ - selected, the module will be called i810. AGP support is required - for this driver to work. - --choice -- prompt "Intel 830M, 845G, 852GM, 855GM, 865G" -- depends on DRM && AGP && AGP_INTEL -- optional -- --config DRM_I830 -- tristate "i830 driver" -- # BKL usage in order to avoid AB-BA deadlocks, i830 may get removed -- depends on BKL -- help -- Choose this option if you have a system that has Intel 830M, 845G, -- 852GM, 855GM or 865G integrated graphics. If M is selected, the -- module will be called i830. AGP support is required for this driver -- to work. This driver is used by the older X releases X.org 6.7 and -- XFree86 4.3. If unsure, build this and i915 as modules and the X server -- will load the correct one. -- - config DRM_I915 - tristate "i915 driver" - depends on AGP_INTEL -@@ -130,8 +113,6 @@ - the driver to bind to PCI devices, which precludes loading things - like intelfb. - --endchoice -- - config DRM_MGA - tristate "Matrox g200/g400" - depends on DRM && PCI diff --git a/target/linux/patches/2.6.37/exmap.patch b/target/linux/patches/2.6.37/exmap.patch deleted file mode 100644 index 012e4794e..000000000 --- a/target/linux/patches/2.6.37/exmap.patch +++ /dev/null @@ -1,11 +0,0 @@ -diff -Nur linux-2.6.32.orig/kernel/pid.c linux-2.6.32/kernel/pid.c ---- linux-2.6.32.orig/kernel/pid.c 2009-12-03 04:51:21.000000000 +0100 -+++ linux-2.6.32/kernel/pid.c 2009-12-06 01:04:41.000000000 +0100 -@@ -387,6 +387,7 @@ - { - return find_task_by_pid_ns(vnr, current->nsproxy->pid_ns); - } -+EXPORT_SYMBOL(find_task_by_vpid); - - struct pid *get_task_pid(struct task_struct *task, enum pid_type type) - { diff --git a/target/linux/patches/2.6.37/foxg20.patch b/target/linux/patches/2.6.37/foxg20.patch deleted file mode 100644 index d00c4c111..000000000 --- a/target/linux/patches/2.6.37/foxg20.patch +++ /dev/null @@ -1,520 +0,0 @@ -diff -Nur linux-2.6.37.orig/arch/arm/Kconfig linux-2.6.37/arch/arm/Kconfig ---- linux-2.6.37.orig/arch/arm/Kconfig 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/arm/Kconfig 2011-01-19 22:07:18.000000000 +0100 -@@ -16,6 +16,8 @@ - select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) - select HAVE_GENERIC_DMA_COHERENT - select HAVE_KERNEL_GZIP -+ select HAVE_KERNEL_BZIP2 -+ select HAVE_KERNEL_LZMA - select HAVE_KERNEL_LZO - select HAVE_KERNEL_LZMA - select HAVE_IRQ_WORK -diff -Nur linux-2.6.37.orig/arch/arm/include/asm/setup.h linux-2.6.37/arch/arm/include/asm/setup.h ---- linux-2.6.37.orig/arch/arm/include/asm/setup.h 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/arm/include/asm/setup.h 2011-01-19 22:07:18.000000000 +0100 -@@ -18,6 +18,8 @@ - - #define COMMAND_LINE_SIZE 1024 - -+const char *get_system_type(void); -+ - /* The list ends with an ATAG_NONE node. */ - #define ATAG_NONE 0x00000000 - -diff -Nur linux-2.6.37.orig/arch/arm/kernel/setup.c linux-2.6.37/arch/arm/kernel/setup.c ---- linux-2.6.37.orig/arch/arm/kernel/setup.c 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/arm/kernel/setup.c 2011-01-19 22:07:18.000000000 +0100 -@@ -935,8 +935,12 @@ - - static int c_show(struct seq_file *m, void *v) - { -+ unsigned long n = (unsigned long) v - 1; - int i; - -+ if (n == 0) -+ seq_printf(m, "system type\t\t: %s\n", get_system_type()); -+ - seq_printf(m, "Processor\t: %s rev %d (%s)\n", - cpu_name, read_cpuid_id() & 15, elf_platform); - -diff -Nur linux-2.6.37.orig/arch/arm/mach-at91/Kconfig linux-2.6.37/arch/arm/mach-at91/Kconfig ---- linux-2.6.37.orig/arch/arm/mach-at91/Kconfig 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/arm/mach-at91/Kconfig 2011-01-19 22:08:47.000000000 +0100 -@@ -347,6 +347,15 @@ - Select this if you are using Atmel's AT91SAM9G20-EK Evaluation Kit - that embeds only one SD/MMC slot. - -+config MACH_FOXG20 -+ bool "Acme Systems FOX G20" -+ select HAVE_AT91_DATAFLASH_CARD -+ select HAVE_NAND_ATMEL_BUSWIDTH_16 -+ depends on ARCH_AT91SAM9G20 -+ help -+ Select this if you are using Acme Systems -+ FOX Board G20 -+ - config MACH_AT91SAM9G20EK_2MMC - depends on MACH_AT91SAM9G20EK - bool "Atmel AT91SAM9G20-EK Evaluation Kit with 2 SD/MMC Slots" -diff -Nur linux-2.6.37.orig/arch/arm/mach-at91/Makefile linux-2.6.37/arch/arm/mach-at91/Makefile ---- linux-2.6.37.orig/arch/arm/mach-at91/Makefile 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/arm/mach-at91/Makefile 2011-01-19 22:07:18.000000000 +0100 -@@ -73,6 +73,9 @@ - # AT91SAM9G45 board-specific support - obj-$(CONFIG_MACH_AT91SAM9M10G45EK) += board-sam9m10g45ek.o - -+# FOXG20 board-specific support -+obj-$(CONFIG_MACH_FOXG20) += board-foxg20.o -+ - # AT91CAP9 board-specific support - obj-$(CONFIG_MACH_AT91CAP9ADK) += board-cap9adk.o - -diff -Nur linux-2.6.37.orig/arch/arm/mach-at91/at91sam9260_devices.c linux-2.6.37/arch/arm/mach-at91/at91sam9260_devices.c ---- linux-2.6.37.orig/arch/arm/mach-at91/at91sam9260_devices.c 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/arm/mach-at91/at91sam9260_devices.c 2011-01-19 22:07:18.000000000 +0100 -@@ -454,7 +454,15 @@ - .sda_is_open_drain = 1, - .scl_pin = AT91_PIN_PA24, - .scl_is_open_drain = 1, -+#if defined(CONFIG_MACH_FOXG20) -+ /* Some I2C devices are limited to 100 kHz and i2c-gpio.h -+ * says "frequency is (500 / udelay) kHz" so 5 is best (and is -+ * used in i2c-gpio.c) -+ */ -+ .udelay = 5, /* ~100 kHz */ -+#else - .udelay = 2, /* ~100 kHz */ -+#endif - }; - - static struct platform_device at91sam9260_twi_device = { -diff -Nur linux-2.6.37.orig/arch/arm/mach-at91/board-foxg20.c linux-2.6.37/arch/arm/mach-at91/board-foxg20.c ---- linux-2.6.37.orig/arch/arm/mach-at91/board-foxg20.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/arm/mach-at91/board-foxg20.c 2011-01-19 22:30:43.000000000 +0100 -@@ -0,0 +1,374 @@ -+/* -+ * Copyright (C) 2005 SAN People -+ * Copyright (C) 2008 Atmel -+ * Copyright (C) 2010 Lee McLoughlin - lee@lmmrtech.com -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+#include "sam9_smc.h" -+#include "generic.h" -+ -+/* -+ * The FOX hardware comes as the "Netus" board with just the cpu, ram, -+ * dataflash and two header connectors. This is plugged into the Fox board -+ * which provides the ethernet, usb, rtc, leds, switch, ... -+ * Other version of the Fox board are planned which could contain -+ * both NAND and sound (WM8731). -+ * -+ * By default USART4 and USART5 are not enabled (freeing up those pins -+ * for general use) -+ * -+ * Note: Enabling the NAND without a NAND device present doesn't cause -+ * any issues as on boot the probe will fail. -+ */ -+/* #define FOXG20_NAND */ -+/* #define FOXG20_WM8731 */ -+/* #define FOX_USART4 */ -+/* #define FOX_USART5 */ -+ -+const char *get_system_type(void) -+{ -+ return "FoxBoard FOXG20"; -+} -+ -+static void __init foxg20_map_io(void) -+{ -+ /* Initialize processor: 18.432 MHz crystal */ -+ at91sam9260_initialize(18432000); -+ -+ /* DBGU on ttyS0. (Rx & Tx only) */ -+ at91_register_uart(0, 0, 0); -+ -+ /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ -+ at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS -+ | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD -+ | ATMEL_UART_RI); -+ -+ /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ -+ at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); -+ -+ /* USART2 on ttyS3. (Rx & Tx only) */ -+ at91_register_uart(AT91SAM9260_ID_US2, 3, 0); -+ -+ /* USART3 on ttyS4. (Rx, Tx, RTS, CTS) */ -+ at91_register_uart(AT91SAM9260_ID_US3, 4, ATMEL_UART_CTS | ATMEL_UART_RTS); -+ -+#if defined(FOX_USART4) -+ /* USART4 on ttyS5. (Rx & Tx only) */ -+ at91_register_uart(AT91SAM9260_ID_US4, 5, 0); -+#endif -+ -+#if defined(FOX_USART5) -+ /* USART5 on ttyS6. (Rx & Tx only) */ -+ at91_register_uart(AT91SAM9260_ID_US5, 6, 0); -+#endif -+ -+ /* set serial console to ttyS0 (ie, DBGU) */ -+ at91_set_serial_console(0); -+} -+ -+static void __init foxg20_init_irq(void) -+{ -+ at91sam9260_init_interrupts(NULL); -+} -+ -+ -+/* -+ * USB Host port -+ */ -+static struct at91_usbh_data __initdata foxg20_usbh_data = { -+ .ports = 2, -+}; -+ -+/* -+ * USB Device port -+ */ -+static struct at91_udc_data __initdata foxg20_udc_data = { -+ .vbus_pin = AT91_PIN_PC6, -+ .pullup_pin = 0, /* pull-up driven by UDC */ -+}; -+ -+ -+/* -+ * SPI devices. -+ */ -+static struct spi_board_info foxg20_spi_devices[] = { -+#if !defined(CONFIG_MMC_AT91) -+ { -+ .modalias = "mtd_dataflash", -+ .chip_select = 1, -+ .max_speed_hz = 15 * 1000 * 1000, -+ .bus_num = 0, -+ }, -+#endif -+}; -+ -+ -+/* -+ * MACB Ethernet device -+ */ -+static struct at91_eth_data __initdata foxg20_macb_data = { -+ .phy_irq_pin = AT91_PIN_PA7, -+ .is_rmii = 1, -+}; -+ -+ -+#ifdef FOXG20_NAND -+/* The Fox doesn't have NAND memory */ -+/* -+ * NAND flash -+ */ -+static struct mtd_partition __initdata foxg20_nand_partition[] = { -+ { -+ .name = "Bootstrap", -+ .offset = 0, -+ .size = 4 * SZ_1M, -+ }, -+ { -+ .name = "Partition 1", -+ .offset = MTDPART_OFS_NXTBLK, -+ .size = 60 * SZ_1M, -+ }, -+ { -+ .name = "Partition 2", -+ .offset = MTDPART_OFS_NXTBLK, -+ .size = MTDPART_SIZ_FULL, -+ }, -+}; -+ -+static struct mtd_partition * __init nand_partitions(int size, int *num_partitions) -+{ -+ *num_partitions = ARRAY_SIZE(foxg20_nand_partition); -+ return foxg20_nand_partition; -+} -+ -+/* det_pin is not connected */ -+static struct atmel_nand_data __initdata foxg20_nand_data = { -+ .ale = 21, -+ .cle = 22, -+ .rdy_pin = AT91_PIN_PC13, -+ .enable_pin = AT91_PIN_PC14, -+ .partition_info = nand_partitions, -+#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16) -+ .bus_width_16 = 1, -+#else -+ .bus_width_16 = 0, -+#endif -+}; -+ -+static struct sam9_smc_config __initdata foxg20_nand_smc_config = { -+ .ncs_read_setup = 0, -+ .nrd_setup = 2, -+ .ncs_write_setup = 0, -+ .nwe_setup = 2, -+ -+ .ncs_read_pulse = 4, -+ .nrd_pulse = 4, -+ .ncs_write_pulse = 4, -+ .nwe_pulse = 4, -+ -+ .read_cycle = 7, -+ .write_cycle = 7, -+ -+ .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE, -+ .tdf_cycles = 3, -+}; -+ -+static void __init foxg20_add_device_nand(void) -+{ -+ /* setup bus-width (8 or 16) */ -+ if (foxg20_nand_data.bus_width_16) -+ foxg20_nand_smc_config.mode |= AT91_SMC_DBW_16; -+ else -+ foxg20_nand_smc_config.mode |= AT91_SMC_DBW_8; -+ -+ /* configure chip-select 3 (NAND) */ -+ sam9_smc_configure(3, &foxg20_nand_smc_config); -+ -+ at91_add_device_nand(&foxg20_nand_data); -+} -+#endif -+ -+ -+/* -+ * MCI (SD/MMC) -+ * det_pin, wp_pin and vcc_pin are not connected -+ */ -+static struct at91_mmc_data __initdata foxg20_mmc_data = { -+ .slot_b = 1, -+ .wire4 = 1, -+}; -+ -+ -+/* -+ * LEDs -+ */ -+static struct gpio_led foxg20_leds[] = { -+ { /* user led, red */ -+ .name = "user_led", -+ .gpio = AT91_PIN_PC7, -+ .active_low = 0, -+ .default_trigger = "heartbeat", -+ }, -+}; -+ -+ -+/* -+ * GPIO Buttons -+ */ -+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) -+static struct gpio_keys_button foxg20_buttons[] = { -+ { -+ .gpio = AT91_PIN_PC4, -+ .code = BTN_1, -+ .desc = "Button 1", -+ .active_low = 1, -+ .wakeup = 1, -+ }, -+}; -+ -+static struct gpio_keys_platform_data foxg20_button_data = { -+ .buttons = foxg20_buttons, -+ .nbuttons = ARRAY_SIZE(foxg20_buttons), -+}; -+ -+static struct platform_device foxg20_button_device = { -+ .name = "gpio-keys", -+ .id = -1, -+ .num_resources = 0, -+ .dev = { -+ .platform_data = &foxg20_button_data, -+ } -+}; -+ -+static void __init foxg20_add_device_buttons(void) -+{ -+ at91_set_gpio_input(AT91_PIN_PC4, 1); /* btn1 */ -+ at91_set_deglitch(AT91_PIN_PC4, 1); -+ -+ platform_device_register(&foxg20_button_device); -+} -+#else -+static void __init foxg20_add_device_buttons(void) {} -+#endif -+ -+ -+#if !defined(FOXG20_WM8731) -+#if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE) -+static struct w1_gpio_platform_data w1_gpio_pdata = { -+ /* If you choose to use a pin other than PB16 it needs to be 3.3V */ -+ .pin = AT91_PIN_PB16, -+ .is_open_drain = 1, -+}; -+ -+static struct platform_device w1_device = { -+ .name = "w1-gpio", -+ .id = -1, -+ .dev.platform_data = &w1_gpio_pdata, -+}; -+ -+static void __init at91_add_device_w1(void) -+{ -+ at91_set_GPIO_periph(w1_gpio_pdata.pin, 1); -+ at91_set_multi_drive(w1_gpio_pdata.pin, 1); -+ platform_device_register(&w1_device); -+} -+ -+#endif -+#endif -+ -+ -+static struct i2c_board_info __initdata foxg20_i2c_devices[] = { -+ { -+ I2C_BOARD_INFO("24c512", 0x50), -+#ifdef FOXG20_WM8731 -+ I2C_BOARD_INFO("wm8731", 0x1b), -+#endif -+ }, -+}; -+ -+ -+static void __init foxg20_board_init(void) -+{ -+ /* Serial */ -+ at91_add_device_serial(); -+ /* USB Host */ -+ at91_add_device_usbh(&foxg20_usbh_data); -+ /* USB Device */ -+ at91_add_device_udc(&foxg20_udc_data); -+ /* SPI */ -+ at91_add_device_spi(foxg20_spi_devices, ARRAY_SIZE(foxg20_spi_devices)); -+#ifdef FOXG20_NAND -+ /* The Fox doesn't have NAND memory */ -+ /* NAND */ -+ foxg20_add_device_nand(); -+#endif -+ /* Ethernet */ -+ at91_add_device_eth(&foxg20_macb_data); -+ /* MMC */ -+ at91_add_device_mmc(0, &foxg20_mmc_data); -+ /* I2C */ -+ at91_add_device_i2c(foxg20_i2c_devices, ARRAY_SIZE(foxg20_i2c_devices)); -+ /* LEDs */ -+ at91_gpio_leds(foxg20_leds, ARRAY_SIZE(foxg20_leds)); -+ /* Push Buttons */ -+ foxg20_add_device_buttons(); -+#ifdef FOXG20_WM8731 -+ /* The Fox doesn't have this sound chip */ -+ /* PCK0 provides MCLK to the WM8731 */ -+ at91_set_B_periph(AT91_PIN_PC1, 0); -+ /* SSC (for WM8731) */ -+ at91_add_device_ssc(AT91SAM9260_ID_SSC, ATMEL_SSC_TX); -+#else -+#if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE) -+ at91_add_device_w1(); -+#endif -+#endif -+} -+ -+MACHINE_START(AT91SAM9G20EK, "Acme Systems FOXG20") -+ /* Maintainer: Lee McLoughlin */ -+ .boot_params = AT91_SDRAM_BASE + 0x100, -+ .timer = &at91sam926x_timer, -+ .map_io = foxg20_map_io, -+ .init_irq = foxg20_init_irq, -+ .init_machine = foxg20_board_init, -+MACHINE_END -diff -Nur linux-2.6.37.orig/drivers/mmc/host/Kconfig linux-2.6.37/drivers/mmc/host/Kconfig ---- linux-2.6.37.orig/drivers/mmc/host/Kconfig 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/mmc/host/Kconfig 2011-01-19 22:07:18.000000000 +0100 -@@ -230,12 +230,12 @@ - - If unsure, say N. - --choice -- prompt "Atmel SD/MMC Driver" -- depends on AVR32 || ARCH_AT91 -- default MMC_ATMELMCI if AVR32 -- help -- Choose which driver to use for the Atmel MCI Silicon -+#choice -+# prompt "Atmel SD/MMC Driver" -+# depends on AVR32 || ARCH_AT91 -+# default MMC_ATMELMCI if AVR32 -+# help -+# Choose which driver to use for the Atmel MCI Silicon - - config MMC_AT91 - tristate "AT91 SD/MMC Card Interface support" -@@ -245,17 +245,17 @@ - - If unsure, say N. - --config MMC_ATMELMCI -- tristate "Atmel Multimedia Card Interface support" -- depends on AVR32 || ARCH_AT91 -- help -- This selects the Atmel Multimedia Card Interface driver. If -- you have an AT32 (AVR32) or AT91 platform with a Multimedia -- Card slot, say Y or M here. -- -- If unsure, say N. -- --endchoice -+#config MMC_ATMELMCI -+# tristate "Atmel Multimedia Card Interface support" -+# depends on AVR32 || ARCH_AT91 -+# help -+# This selects the Atmel Multimedia Card Interface driver. If -+# you have an AT32 (AVR32) or AT91 platform with a Multimedia -+# Card slot, say Y or M here. -+# -+# If unsure, say N. -+# -+#endchoice - - config MMC_ATMELMCI_DMA - bool "Atmel MCI DMA support (EXPERIMENTAL)" diff --git a/target/linux/patches/2.6.37/freebsd-compat.patch b/target/linux/patches/2.6.37/freebsd-compat.patch deleted file mode 100644 index 051fdc63e..000000000 --- a/target/linux/patches/2.6.37/freebsd-compat.patch +++ /dev/null @@ -1,11 +0,0 @@ -diff -Nur linux-2.6.30.orig/arch/x86/boot/tools/build.c linux-2.6.30/arch/x86/boot/tools/build.c ---- linux-2.6.30.orig/arch/x86/boot/tools/build.c 2009-06-10 05:05:27.000000000 +0200 -+++ linux-2.6.30/arch/x86/boot/tools/build.c 2009-06-11 09:18:50.000000000 +0200 -@@ -29,7 +29,6 @@ - #include - #include - #include --#include - #include - #include - #include diff --git a/target/linux/patches/2.6.37/gemalto.patch b/target/linux/patches/2.6.37/gemalto.patch deleted file mode 100644 index 9461d0317..000000000 --- a/target/linux/patches/2.6.37/gemalto.patch +++ /dev/null @@ -1,11 +0,0 @@ -diff -Nur linux-2.6.36.orig/drivers/serial/serial_cs.c linux-2.6.36/drivers/serial/serial_cs.c ---- linux-2.6.36.orig/drivers/serial/serial_cs.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/drivers/serial/serial_cs.c 2010-12-13 23:03:40.000000000 +0100 -@@ -794,6 +794,7 @@ - PCMCIA_DEVICE_MANF_CARD(0x0137, 0x0025), - PCMCIA_DEVICE_MANF_CARD(0x0137, 0x0045), - PCMCIA_DEVICE_MANF_CARD(0x0137, 0x0052), -+ PCMCIA_DEVICE_MANF_CARD(0x0157, 0x0100), /* Gemalto SCR */ - PCMCIA_DEVICE_MANF_CARD(0x016c, 0x0006), /* Psion 56K+Fax */ - PCMCIA_DEVICE_MANF_CARD(0x0200, 0x0001), /* MultiMobile */ - PCMCIA_DEVICE_PROD_ID134("ADV", "TECH", "COMpad-32/85", 0x67459937, 0x916d02ba, 0x8fbe92ae), diff --git a/target/linux/patches/2.6.37/lemote.patch b/target/linux/patches/2.6.37/lemote.patch deleted file mode 100644 index 513292e96..000000000 --- a/target/linux/patches/2.6.37/lemote.patch +++ /dev/null @@ -1,4271 +0,0 @@ -diff -Nur linux-2.6.37.orig/arch/mips/Kconfig linux-2.6.37/arch/mips/Kconfig ---- linux-2.6.37.orig/arch/mips/Kconfig 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/mips/Kconfig 2011-01-11 20:44:43.000000000 +0100 -@@ -210,7 +210,7 @@ - - config MACH_LOONGSON - bool "Loongson family of machines" -- select SYS_SUPPORTS_ZBOOT -+ select SYS_SUPPORTS_ZBOOT_UART16550 - help - This enables the support of Loongson family of machines. - -@@ -1101,6 +1101,8 @@ - bool "Loongson 2E" - depends on SYS_HAS_CPU_LOONGSON2E - select CPU_LOONGSON2 -+ select GENERIC_GPIO -+ select ARCH_REQUIRE_GPIOLIB - help - The Loongson 2E processor implements the MIPS III instruction set - with many extensions. -@@ -2099,6 +2101,18 @@ - source "kernel/time/Kconfig" - - # -+# High Resolution sched_clock() Configuration -+# -+ -+config CPU_HAS_FIXED_C0_COUNT -+ bool -+ -+config CPU_SUPPORTS_HR_SCHED_CLOCK -+ bool -+ depends on CPU_HAS_FIXED_C0_COUNT || !CPU_FREQ -+ default y -+ -+# - # Timer Interrupt Frequency Configuration - # - -diff -Nur linux-2.6.37.orig/arch/mips/include/asm/dma-mapping.h linux-2.6.37/arch/mips/include/asm/dma-mapping.h ---- linux-2.6.37.orig/arch/mips/include/asm/dma-mapping.h 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/mips/include/asm/dma-mapping.h 2011-01-11 20:44:43.000000000 +0100 -@@ -85,4 +85,8 @@ - void dma_free_noncoherent(struct device *dev, size_t size, - void *vaddr, dma_addr_t dma_handle); - -+#define ARCH_HAS_DMA_MMAP_COHERENT -+extern int dma_mmap_coherent(struct device *dev, struct vm_area_struct *vma, -+ void *cpu_addr, dma_addr_t handle, size_t size); -+ - #endif /* _ASM_DMA_MAPPING_H */ -diff -Nur linux-2.6.37.orig/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h linux-2.6.37/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h ---- linux-2.6.37.orig/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h 2011-01-11 20:44:43.000000000 +0100 -@@ -255,21 +255,12 @@ - * IDE STANDARD - */ - #define IDE_CAP 0x00 --#define IDE_CONFIG 0x01 --#define IDE_SMI 0x02 --#define IDE_ERROR 0x03 --#define IDE_PM 0x04 --#define IDE_DIAG 0x05 -- --/* -- * IDE SPEC. -- */ - #define IDE_IO_BAR 0x08 - #define IDE_CFG 0x10 - #define IDE_DTC 0x12 - #define IDE_CAST 0x13 - #define IDE_ETC 0x14 --#define IDE_INTERNAL_PM 0x15 -+#define IDE_PM 0x15 - - /* - * ACC STANDARD -@@ -301,5 +292,40 @@ - /* GPIO : I/O SPACE; REG : 32BITS */ - #define GPIOL_OUT_VAL 0x00 - #define GPIOL_OUT_EN 0x04 -+#define GPIOL_OUT_AUX1_SEL 0x10 -+/* SMB : I/O SPACE, REG : 8BITS WIDTH */ -+#define SMB_SDA 0x00 -+#define SMB_STS 0x01 -+#define SMB_STS_SLVSTP (1 << 7) -+#define SMB_STS_SDAST (1 << 6) -+#define SMB_STS_BER (1 << 5) -+#define SMB_STS_NEGACK (1 << 4) -+#define SMB_STS_STASTR (1 << 3) -+#define SMB_STS_NMATCH (1 << 2) -+#define SMB_STS_MASTER (1 << 1) -+#define SMB_STS_XMIT (1 << 0) -+#define SMB_CTRL_STS 0x02 -+#define SMB_CSTS_TGSTL (1 << 5) -+#define SMB_CSTS_TSDA (1 << 4) -+#define SMB_CSTS_GCMTCH (1 << 3) -+#define SMB_CSTS_MATCH (1 << 2) -+#define SMB_CSTS_BB (1 << 1) -+#define SMB_CSTS_BUSY (1 << 0) -+#define SMB_CTRL1 0x03 -+#define SMB_CTRL1_STASTRE (1 << 7) -+#define SMB_CTRL1_NMINTE (1 << 6) -+#define SMB_CTRL1_GCMEN (1 << 5) -+#define SMB_CTRL1_ACK (1 << 4) -+#define SMB_CTRL1_RSVD (1 << 3) -+#define SMB_CTRL1_INTEN (1 << 2) -+#define SMB_CTRL1_STOP (1 << 1) -+#define SMB_CTRL1_START (1 << 0) -+#define SMB_ADDR 0x04 -+#define SMB_ADDR_SAEN (1 << 7) -+#define SMB_CONTROLLER_ADDR (0xef << 0) -+#define SMB_CTRL2 0x05 -+#define SMB_FREQ (0x20 << 1) -+#define SMB_ENABLE (0x01 << 0) -+#define SMB_CTRL3 0x06 - - #endif /* _CS5536_H */ -diff -Nur linux-2.6.37.orig/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h linux-2.6.37/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h ---- linux-2.6.37.orig/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h 2011-01-11 20:44:43.000000000 +0100 -@@ -32,4 +32,9 @@ - #define MFGPT0_CNT (MFGPT_BASE + 4) - #define MFGPT0_SETUP (MFGPT_BASE + 6) - -+#define MFGPT2_CMP1 (MFGPT_BASE + 0x10) -+#define MFGPT2_CMP2 (MFGPT_BASE + 0x12) -+#define MFGPT2_CNT (MFGPT_BASE + 0x14) -+#define MFGPT2_SETUP (MFGPT_BASE + 0x16) -+ - #endif /*!_CS5536_MFGPT_H */ -diff -Nur linux-2.6.37.orig/arch/mips/include/asm/mach-loongson/ec_kb3310b.h linux-2.6.37/arch/mips/include/asm/mach-loongson/ec_kb3310b.h ---- linux-2.6.37.orig/arch/mips/include/asm/mach-loongson/ec_kb3310b.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/include/asm/mach-loongson/ec_kb3310b.h 2011-01-11 20:44:43.000000000 +0100 -@@ -0,0 +1,191 @@ -+/* -+ * KB3310B Embedded Controller -+ * -+ * Copyright (C) 2008 Lemote Inc. -+ * Author: liujl , 2008-03-14 -+ * Copyright (C) 2009 Lemote Inc. -+ * Author: Wu Zhangjin -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ */ -+ -+#ifndef _EC_KB3310B_H -+#define _EC_KB3310B_H -+ -+extern unsigned char ec_read(unsigned short addr); -+extern void ec_write(unsigned short addr, unsigned char val); -+extern int ec_query_seq(unsigned char cmd); -+extern int ec_query_event_num(void); -+extern int ec_get_event_num(void); -+ -+typedef int (*sci_handler) (int status); -+extern sci_handler yeeloong_report_lid_status; -+ -+#define SCI_IRQ_NUM 0x0A -+ -+/* -+ * The following registers are determined by the EC index configuration. -+ * 1, fill the PORT_HIGH as EC register high part. -+ * 2, fill the PORT_LOW as EC register low part. -+ * 3, fill the PORT_DATA as EC register write data or get the data from it. -+ */ -+#define EC_IO_PORT_HIGH 0x0381 -+#define EC_IO_PORT_LOW 0x0382 -+#define EC_IO_PORT_DATA 0x0383 -+ -+/* -+ * EC delay time is 500us for register and status access -+ */ -+#define EC_REG_DELAY 500 /* unit : us */ -+#define EC_CMD_TIMEOUT 0x1000 -+ -+/* -+ * EC access port for SCI communication -+ */ -+#define EC_CMD_PORT 0x66 -+#define EC_STS_PORT 0x66 -+#define EC_DAT_PORT 0x62 -+#define CMD_INIT_IDLE_MODE 0xdd -+#define CMD_EXIT_IDLE_MODE 0xdf -+#define CMD_INIT_RESET_MODE 0xd8 -+#define CMD_REBOOT_SYSTEM 0x8c -+#define CMD_GET_EVENT_NUM 0x84 -+#define CMD_PROGRAM_PIECE 0xda -+ -+/* Temperature & Fan registers */ -+#define REG_TEMPERATURE_VALUE 0xF458 -+#define REG_FAN_AUTO_MAN_SWITCH 0xF459 -+#define BIT_FAN_AUTO 0 -+#define BIT_FAN_MANUAL 1 -+#define REG_FAN_CONTROL 0xF4D2 -+#define BIT_FAN_CONTROL_ON (1 << 0) -+#define BIT_FAN_CONTROL_OFF (0 << 0) -+#define REG_FAN_STATUS 0xF4DA -+#define BIT_FAN_STATUS_ON (1 << 0) -+#define BIT_FAN_STATUS_OFF (0 << 0) -+#define REG_FAN_SPEED_HIGH 0xFE22 -+#define REG_FAN_SPEED_LOW 0xFE23 -+#define REG_FAN_SPEED_LEVEL 0xF4CC -+/* Fan speed divider */ -+#define FAN_SPEED_DIVIDER 480000 /* (60*1000*1000/62.5/2)*/ -+ -+/* Battery registers */ -+#define REG_BAT_DESIGN_CAP_HIGH 0xF77D -+#define REG_BAT_DESIGN_CAP_LOW 0xF77E -+#define REG_BAT_FULLCHG_CAP_HIGH 0xF780 -+#define REG_BAT_FULLCHG_CAP_LOW 0xF781 -+#define REG_BAT_DESIGN_VOL_HIGH 0xF782 -+#define REG_BAT_DESIGN_VOL_LOW 0xF783 -+#define REG_BAT_CURRENT_HIGH 0xF784 -+#define REG_BAT_CURRENT_LOW 0xF785 -+#define REG_BAT_VOLTAGE_HIGH 0xF786 -+#define REG_BAT_VOLTAGE_LOW 0xF787 -+#define REG_BAT_TEMPERATURE_HIGH 0xF788 -+#define REG_BAT_TEMPERATURE_LOW 0xF789 -+#define REG_BAT_RELATIVE_CAP_HIGH 0xF492 -+#define REG_BAT_RELATIVE_CAP_LOW 0xF493 -+#define REG_BAT_VENDOR 0xF4C4 -+#define FLAG_BAT_VENDOR_SANYO 0x01 -+#define FLAG_BAT_VENDOR_SIMPLO 0x02 -+#define REG_BAT_CELL_COUNT 0xF4C6 -+#define FLAG_BAT_CELL_3S1P 0x03 -+#define FLAG_BAT_CELL_3S2P 0x06 -+#define REG_BAT_CHARGE 0xF4A2 -+#define FLAG_BAT_CHARGE_DISCHARGE 0x01 -+#define FLAG_BAT_CHARGE_CHARGE 0x02 -+#define FLAG_BAT_CHARGE_ACPOWER 0x00 -+#define REG_BAT_STATUS 0xF4B0 -+#define BIT_BAT_STATUS_LOW (1 << 5) -+#define BIT_BAT_STATUS_DESTROY (1 << 2) -+#define BIT_BAT_STATUS_FULL (1 << 1) -+#define BIT_BAT_STATUS_IN (1 << 0) -+#define REG_BAT_CHARGE_STATUS 0xF4B1 -+#define BIT_BAT_CHARGE_STATUS_OVERTEMP (1 << 2) -+#define BIT_BAT_CHARGE_STATUS_PRECHG (1 << 1) -+#define REG_BAT_STATE 0xF482 -+#define BIT_BAT_STATE_CHARGING (1 << 1) -+#define BIT_BAT_STATE_DISCHARGING (1 << 0) -+#define REG_BAT_POWER 0xF440 -+#define BIT_BAT_POWER_S3 (1 << 2) -+#define BIT_BAT_POWER_ON (1 << 1) -+#define BIT_BAT_POWER_ACIN (1 << 0) -+ -+/* Audio: rd/wr */ -+#define REG_AUDIO_VOLUME 0xF46C -+#define REG_AUDIO_MUTE 0xF4E7 -+#define REG_AUDIO_BEEP 0xF4D0 -+/* USB port power or not: rd/wr */ -+#define REG_USB0_FLAG 0xF461 -+#define REG_USB1_FLAG 0xF462 -+#define REG_USB2_FLAG 0xF463 -+#define BIT_USB_FLAG_ON 1 -+#define BIT_USB_FLAG_OFF 0 -+/* LID */ -+#define REG_LID_DETECT 0xF4BD -+#define BIT_LID_DETECT_ON 1 -+#define BIT_LID_DETECT_OFF 0 -+/* CRT */ -+#define REG_CRT_DETECT 0xF4AD -+#define BIT_CRT_DETECT_PLUG 1 -+#define BIT_CRT_DETECT_UNPLUG 0 -+/* LCD backlight brightness adjust: 9 levels */ -+#define REG_DISPLAY_BRIGHTNESS 0xF4F5 -+/* Black screen Status */ -+#define BIT_DISPLAY_LCD_ON 1 -+#define BIT_DISPLAY_LCD_OFF 0 -+/* LCD backlight control: off/restore */ -+#define REG_BACKLIGHT_CTRL 0xF7BD -+#define BIT_BACKLIGHT_ON 1 -+#define BIT_BACKLIGHT_OFF 0 -+/* Reset the machine auto-clear: rd/wr */ -+#define REG_RESET 0xF4EC -+#define BIT_RESET_ON 1 -+/* Light the led: rd/wr */ -+#define REG_LED 0xF4C8 -+#define BIT_LED_RED_POWER (1 << 0) -+#define BIT_LED_ORANGE_POWER (1 << 1) -+#define BIT_LED_GREEN_CHARGE (1 << 2) -+#define BIT_LED_RED_CHARGE (1 << 3) -+#define BIT_LED_NUMLOCK (1 << 4) -+/* Test led mode, all led on/off */ -+#define REG_LED_TEST 0xF4C2 -+#define BIT_LED_TEST_IN 1 -+#define BIT_LED_TEST_OUT 0 -+/* Camera on/off */ -+#define REG_CAMERA_STATUS 0xF46A -+#define BIT_CAMERA_STATUS_ON 1 -+#define BIT_CAMERA_STATUS_OFF 0 -+#define REG_CAMERA_CONTROL 0xF7B7 -+#define BIT_CAMERA_CONTROL_OFF 0 -+#define BIT_CAMERA_CONTROL_ON 1 -+/* Wlan Status */ -+#define REG_WLAN 0xF4FA -+#define BIT_WLAN_ON 1 -+#define BIT_WLAN_OFF 0 -+#define REG_DISPLAY_LCD 0xF79F -+ -+/* SCI Event Number from EC */ -+enum { -+ EVENT_LID = 0x23, /* Turn on/off LID */ -+ EVENT_SWITCHVIDEOMODE, /* Fn+F3 for display switch */ -+ EVENT_SLEEP, /* Fn+F1 for entering sleep mode */ -+ EVENT_OVERTEMP, /* Over-temperature happened */ -+ EVENT_CRT_DETECT, /* CRT is connected */ -+ EVENT_CAMERA, /* Camera on/off */ -+ EVENT_USB_OC2, /* USB2 Over Current occurred */ -+ EVENT_USB_OC0, /* USB0 Over Current occurred */ -+ EVENT_DISPLAYTOGGLE, /* Fn+F2, Turn on/off backlight */ -+ EVENT_AUDIO_MUTE, /* Fn+F4, Mute on/off */ -+ EVENT_DISPLAY_BRIGHTNESS,/* Fn+^/V, LCD backlight brightness adjust */ -+ EVENT_AC_BAT, /* AC & Battery relative issue */ -+ EVENT_AUDIO_VOLUME, /* Fn+<|>, Volume adjust */ -+ EVENT_WLAN, /* Wlan on/off */ -+}; -+ -+#define EVENT_START EVENT_LID -+#define EVENT_END EVENT_WLAN -+ -+#endif /* !_EC_KB3310B_H */ -diff -Nur linux-2.6.37.orig/arch/mips/include/asm/mach-loongson/loongson.h linux-2.6.37/arch/mips/include/asm/mach-loongson/loongson.h ---- linux-2.6.37.orig/arch/mips/include/asm/mach-loongson/loongson.h 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/mips/include/asm/mach-loongson/loongson.h 2011-01-11 20:44:43.000000000 +0100 -@@ -43,6 +43,12 @@ - #endif - } - -+/* -+ * Copy kernel command line from arcs_cmdline -+ */ -+#include -+extern char loongson_cmdline[COMMAND_LINE_SIZE]; -+ - /* irq operation functions */ - extern void bonito_irqdispatch(void); - extern void __init bonito_irq_init(void); -diff -Nur linux-2.6.37.orig/arch/mips/kernel/csrc-r4k.c linux-2.6.37/arch/mips/kernel/csrc-r4k.c ---- linux-2.6.37.orig/arch/mips/kernel/csrc-r4k.c 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/mips/kernel/csrc-r4k.c 2011-01-11 20:44:43.000000000 +0100 -@@ -6,10 +6,66 @@ - * Copyright (C) 2007 by Ralf Baechle - */ - #include -+#include - #include -+#include - - #include - -+#ifdef CONFIG_CPU_SUPPORTS_HR_SCHED_CLOCK -+/* -+ * MIPS sched_clock implementation. -+ * -+ * Because the hardware timer period is quite short and because cnt32_to_63() -+ * needs to be called at least once per half period to work properly, a kernel -+ * timer is set up to ensure this requirement is always met. -+ * -+ * Please refer to include/linux/cnt32_to_63.h and arch/arm/plat-orion/time.c -+ */ -+#define CLOCK2NS_SCALE_FACTOR 8 -+ -+static unsigned long clock2ns_scale __read_mostly; -+ -+unsigned long long notrace sched_clock(void) -+{ -+ unsigned long long v = cnt32_to_63(read_c0_count()); -+ return (v * clock2ns_scale) >> CLOCK2NS_SCALE_FACTOR; -+} -+ -+static struct timer_list cnt32_to_63_keepwarm_timer; -+ -+static void cnt32_to_63_keepwarm(unsigned long data) -+{ -+ mod_timer(&cnt32_to_63_keepwarm_timer, round_jiffies(jiffies + data)); -+ sched_clock(); -+} -+#endif -+ -+static inline void setup_hres_sched_clock(unsigned long clock) -+{ -+#ifdef CONFIG_CPU_SUPPORTS_HR_SCHED_CLOCK -+ unsigned long long v; -+ unsigned long data; -+ -+ v = NSEC_PER_SEC; -+ v <<= CLOCK2NS_SCALE_FACTOR; -+ v += clock/2; -+ do_div(v, clock); -+ /* -+ * We want an even value to automatically clear the top bit -+ * returned by cnt32_to_63() without an additional run time -+ * instruction. So if the LSB is 1 then round it up. -+ */ -+ if (v & 1) -+ v++; -+ clock2ns_scale = v; -+ -+ data = 0x80000000UL / clock * HZ; -+ setup_timer(&cnt32_to_63_keepwarm_timer, cnt32_to_63_keepwarm, data); -+ mod_timer(&cnt32_to_63_keepwarm_timer, round_jiffies(jiffies + data)); -+#endif -+} -+ - static cycle_t c0_hpt_read(struct clocksource *cs) - { - return read_c0_count(); -@@ -27,6 +83,8 @@ - if (!cpu_has_counter || !mips_hpt_frequency) - return -ENXIO; - -+ setup_hres_sched_clock(mips_hpt_frequency); -+ - /* Calculate a somewhat reasonable rating value */ - clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000; - -diff -Nur linux-2.6.37.orig/arch/mips/kernel/time.c linux-2.6.37/arch/mips/kernel/time.c ---- linux-2.6.37.orig/arch/mips/kernel/time.c 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/mips/kernel/time.c 2011-01-11 20:44:43.000000000 +0100 -@@ -119,6 +119,11 @@ - - void __init time_init(void) - { -+#ifdef CONFIG_HR_SCHED_CLOCK -+ if (!mips_clockevent_init() || !cpu_has_mfc0_count_bug()) -+ write_c0_count(0); -+#endif -+ - plat_time_init(); - - if (!mips_clockevent_init() || !cpu_has_mfc0_count_bug()) -diff -Nur linux-2.6.37.orig/arch/mips/loongson/common/cmdline.c linux-2.6.37/arch/mips/loongson/common/cmdline.c ---- linux-2.6.37.orig/arch/mips/loongson/common/cmdline.c 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/mips/loongson/common/cmdline.c 2011-01-11 20:44:43.000000000 +0100 -@@ -17,10 +17,15 @@ - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -+#include - #include - - #include - -+/* the kernel command line copied from arcs_cmdline */ -+char loongson_cmdline[COMMAND_LINE_SIZE]; -+EXPORT_SYMBOL(loongson_cmdline); -+ - void __init prom_init_cmdline(void) - { - int prom_argc; -@@ -50,4 +55,26 @@ - strcat(arcs_cmdline, " root=/dev/hda1"); - - prom_init_machtype(); -+ -+ /* append machine specific command line */ -+ switch (mips_machtype) { -+ case MACH_LEMOTE_LL2F: -+ if ((strstr(arcs_cmdline, "video=")) == NULL) -+ strcat(arcs_cmdline, " video=sisfb:1360x768-16@60"); -+ break; -+ case MACH_LEMOTE_FL2F: -+ if ((strstr(arcs_cmdline, "ide_core.ignore_cable=")) == NULL) -+ strcat(arcs_cmdline, " ide_core.ignore_cable=0"); -+ break; -+ case MACH_LEMOTE_ML2F7: -+ /* Mengloong-2F has a 800x480 screen */ -+ if ((strstr(arcs_cmdline, "vga=")) == NULL) -+ strcat(arcs_cmdline, " vga=0x313"); -+ break; -+ default: -+ break; -+ } -+ -+ /* copy arcs_cmdline into loongson_cmdline */ -+ strncpy(loongson_cmdline, arcs_cmdline, COMMAND_LINE_SIZE); - } -diff -Nur linux-2.6.37.orig/arch/mips/loongson/common/cs5536/cs5536_acc.c linux-2.6.37/arch/mips/loongson/common/cs5536/cs5536_acc.c ---- linux-2.6.37.orig/arch/mips/loongson/common/cs5536/cs5536_acc.c 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/mips/loongson/common/cs5536/cs5536_acc.c 2011-01-11 20:44:43.000000000 +0100 -@@ -18,7 +18,7 @@ - - void pci_acc_write_reg(int reg, u32 value) - { -- u32 hi = 0, lo = value; -+ u32 hi, lo; - - switch (reg) { - case PCI_COMMAND: -@@ -66,75 +66,73 @@ - u32 pci_acc_read_reg(int reg) - { - u32 hi, lo; -- u32 conf_data = 0; -+ u32 cfg = 0; - - switch (reg) { - case PCI_VENDOR_ID: -- conf_data = -- CFG_PCI_VENDOR_ID(CS5536_ACC_DEVICE_ID, CS5536_VENDOR_ID); -+ cfg = CFG_PCI_VENDOR_ID(CS5536_ACC_DEVICE_ID, -+ CS5536_VENDOR_ID); - break; - case PCI_COMMAND: - _rdmsr(GLIU_MSR_REG(GLIU_IOD_BM1), &hi, &lo); - if (((lo & 0xfff00000) || (hi & 0x000000ff)) - && ((hi & 0xf0000000) == 0xa0000000)) -- conf_data |= PCI_COMMAND_IO; -+ cfg |= PCI_COMMAND_IO; - _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo); - if ((lo & 0x300) == 0x300) -- conf_data |= PCI_COMMAND_MASTER; -+ cfg |= PCI_COMMAND_MASTER; - break; - case PCI_STATUS: -- conf_data |= PCI_STATUS_66MHZ; -- conf_data |= PCI_STATUS_FAST_BACK; -+ cfg |= PCI_STATUS_66MHZ; -+ cfg |= PCI_STATUS_FAST_BACK; - _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); - if (lo & SB_PARE_ERR_FLAG) -- conf_data |= PCI_STATUS_PARITY; -- conf_data |= PCI_STATUS_DEVSEL_MEDIUM; -+ cfg |= PCI_STATUS_PARITY; -+ cfg |= PCI_STATUS_DEVSEL_MEDIUM; - break; - case PCI_CLASS_REVISION: - _rdmsr(ACC_MSR_REG(ACC_CAP), &hi, &lo); -- conf_data = lo & 0x000000ff; -- conf_data |= (CS5536_ACC_CLASS_CODE << 8); -+ cfg = lo & 0x000000ff; -+ cfg |= (CS5536_ACC_CLASS_CODE << 8); - break; - case PCI_CACHE_LINE_SIZE: -- conf_data = -- CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, -- PCI_NORMAL_LATENCY_TIMER); -+ cfg = CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, -+ PCI_NORMAL_LATENCY_TIMER); - break; - case PCI_BAR0_REG: - _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); - if (lo & SOFT_BAR_ACC_FLAG) { -- conf_data = CS5536_ACC_RANGE | -+ cfg = CS5536_ACC_RANGE | - PCI_BASE_ADDRESS_SPACE_IO; - lo &= ~SOFT_BAR_ACC_FLAG; - _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); - } else { - _rdmsr(GLIU_MSR_REG(GLIU_IOD_BM1), &hi, &lo); -- conf_data = (hi & 0x000000ff) << 12; -- conf_data |= (lo & 0xfff00000) >> 20; -- conf_data |= 0x01; -- conf_data &= ~0x02; -+ cfg = (hi & 0x000000ff) << 12; -+ cfg |= (lo & 0xfff00000) >> 20; -+ cfg |= 0x01; -+ cfg &= ~0x02; - } - break; - case PCI_CARDBUS_CIS: -- conf_data = PCI_CARDBUS_CIS_POINTER; -+ cfg = PCI_CARDBUS_CIS_POINTER; - break; - case PCI_SUBSYSTEM_VENDOR_ID: -- conf_data = -- CFG_PCI_VENDOR_ID(CS5536_ACC_SUB_ID, CS5536_SUB_VENDOR_ID); -+ cfg = CFG_PCI_VENDOR_ID(CS5536_ACC_SUB_ID, -+ CS5536_SUB_VENDOR_ID); - break; - case PCI_ROM_ADDRESS: -- conf_data = PCI_EXPANSION_ROM_BAR; -+ cfg = PCI_EXPANSION_ROM_BAR; - break; - case PCI_CAPABILITY_LIST: -- conf_data = PCI_CAPLIST_USB_POINTER; -+ cfg = PCI_CAPLIST_USB_POINTER; - break; - case PCI_INTERRUPT_LINE: -- conf_data = -- CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_ACC_INTR); -+ cfg = CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_ACC_INTR); - break; - default: - break; - } - -- return conf_data; -+ return cfg; - } -diff -Nur linux-2.6.37.orig/arch/mips/loongson/common/cs5536/cs5536_ehci.c linux-2.6.37/arch/mips/loongson/common/cs5536/cs5536_ehci.c ---- linux-2.6.37.orig/arch/mips/loongson/common/cs5536/cs5536_ehci.c 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/mips/loongson/common/cs5536/cs5536_ehci.c 2011-01-11 20:44:43.000000000 +0100 -@@ -18,7 +18,7 @@ - - void pci_ehci_write_reg(int reg, u32 value) - { -- u32 hi = 0, lo = value; -+ u32 hi, lo; - - switch (reg) { - case PCI_COMMAND: -@@ -78,83 +78,81 @@ - - u32 pci_ehci_read_reg(int reg) - { -- u32 conf_data = 0; -+ u32 cfg = 0; - u32 hi, lo; - - switch (reg) { - case PCI_VENDOR_ID: -- conf_data = -- CFG_PCI_VENDOR_ID(CS5536_EHCI_DEVICE_ID, CS5536_VENDOR_ID); -+ cfg = CFG_PCI_VENDOR_ID(CS5536_EHCI_DEVICE_ID, -+ CS5536_VENDOR_ID); - break; - case PCI_COMMAND: - _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); - if (hi & PCI_COMMAND_MASTER) -- conf_data |= PCI_COMMAND_MASTER; -+ cfg |= PCI_COMMAND_MASTER; - if (hi & PCI_COMMAND_MEMORY) -- conf_data |= PCI_COMMAND_MEMORY; -+ cfg |= PCI_COMMAND_MEMORY; - break; - case PCI_STATUS: -- conf_data |= PCI_STATUS_66MHZ; -- conf_data |= PCI_STATUS_FAST_BACK; -+ cfg |= PCI_STATUS_66MHZ; -+ cfg |= PCI_STATUS_FAST_BACK; - _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); - if (lo & SB_PARE_ERR_FLAG) -- conf_data |= PCI_STATUS_PARITY; -- conf_data |= PCI_STATUS_DEVSEL_MEDIUM; -+ cfg |= PCI_STATUS_PARITY; -+ cfg |= PCI_STATUS_DEVSEL_MEDIUM; - break; - case PCI_CLASS_REVISION: - _rdmsr(USB_MSR_REG(USB_CAP), &hi, &lo); -- conf_data = lo & 0x000000ff; -- conf_data |= (CS5536_EHCI_CLASS_CODE << 8); -+ cfg = lo & 0x000000ff; -+ cfg |= (CS5536_EHCI_CLASS_CODE << 8); - break; - case PCI_CACHE_LINE_SIZE: -- conf_data = -- CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, -- PCI_NORMAL_LATENCY_TIMER); -+ cfg = CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, -+ PCI_NORMAL_LATENCY_TIMER); - break; - case PCI_BAR0_REG: - _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); - if (lo & SOFT_BAR_EHCI_FLAG) { -- conf_data = CS5536_EHCI_RANGE | -+ cfg = CS5536_EHCI_RANGE | - PCI_BASE_ADDRESS_SPACE_MEMORY; - lo &= ~SOFT_BAR_EHCI_FLAG; - _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); - } else { - _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); -- conf_data = lo & 0xfffff000; -+ cfg = lo & 0xfffff000; - } - break; - case PCI_CARDBUS_CIS: -- conf_data = PCI_CARDBUS_CIS_POINTER; -+ cfg = PCI_CARDBUS_CIS_POINTER; - break; - case PCI_SUBSYSTEM_VENDOR_ID: -- conf_data = -- CFG_PCI_VENDOR_ID(CS5536_EHCI_SUB_ID, CS5536_SUB_VENDOR_ID); -+ cfg = CFG_PCI_VENDOR_ID(CS5536_EHCI_SUB_ID, -+ CS5536_SUB_VENDOR_ID); - break; - case PCI_ROM_ADDRESS: -- conf_data = PCI_EXPANSION_ROM_BAR; -+ cfg = PCI_EXPANSION_ROM_BAR; - break; - case PCI_CAPABILITY_LIST: -- conf_data = PCI_CAPLIST_USB_POINTER; -+ cfg = PCI_CAPLIST_USB_POINTER; - break; - case PCI_INTERRUPT_LINE: -- conf_data = -- CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR); -+ cfg = CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR); - break; - case PCI_EHCI_LEGSMIEN_REG: - _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); -- conf_data = (hi & 0x003f0000) >> 16; -+ cfg = (hi & 0x003f0000) >> 16; - break; - case PCI_EHCI_LEGSMISTS_REG: - _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); -- conf_data = (hi & 0x3f000000) >> 24; -+ cfg = (hi & 0x3f000000) >> 24; - break; - case PCI_EHCI_FLADJ_REG: - _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); -- conf_data = hi & 0x00003f00; -+ cfg = hi & 0x00003f00; - break; - default: - break; - } - -- return conf_data; -+ return cfg; - } -diff -Nur linux-2.6.37.orig/arch/mips/loongson/common/cs5536/cs5536_ide.c linux-2.6.37/arch/mips/loongson/common/cs5536/cs5536_ide.c ---- linux-2.6.37.orig/arch/mips/loongson/common/cs5536/cs5536_ide.c 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/mips/loongson/common/cs5536/cs5536_ide.c 2011-01-11 20:44:43.000000000 +0100 -@@ -18,7 +18,7 @@ - - void pci_ide_write_reg(int reg, u32 value) - { -- u32 hi = 0, lo = value; -+ u32 hi, lo; - - switch (reg) { - case PCI_COMMAND: -@@ -72,26 +72,16 @@ - _wrmsr(IDE_MSR_REG(IDE_CFG), hi, lo); - } - break; -- case PCI_IDE_DTC_REG: -- _rdmsr(IDE_MSR_REG(IDE_DTC), &hi, &lo); -- lo = value; -- _wrmsr(IDE_MSR_REG(IDE_DTC), hi, lo); -- break; -- case PCI_IDE_CAST_REG: -- _rdmsr(IDE_MSR_REG(IDE_CAST), &hi, &lo); -- lo = value; -- _wrmsr(IDE_MSR_REG(IDE_CAST), hi, lo); -- break; -- case PCI_IDE_ETC_REG: -- _rdmsr(IDE_MSR_REG(IDE_ETC), &hi, &lo); -- lo = value; -- _wrmsr(IDE_MSR_REG(IDE_ETC), hi, lo); -- break; -- case PCI_IDE_PM_REG: -- _rdmsr(IDE_MSR_REG(IDE_INTERNAL_PM), &hi, &lo); -- lo = value; -- _wrmsr(IDE_MSR_REG(IDE_INTERNAL_PM), hi, lo); -- break; -+#define SET_PCI_IDE_REG(r) \ -+ case PCI_IDE_##r##_REG: \ -+ _rdmsr(IDE_MSR_REG(IDE_##r), &hi, &lo); \ -+ lo = value; \ -+ _wrmsr(IDE_MSR_REG(IDE_##r), hi, lo); \ -+ break; -+ SET_PCI_IDE_REG(DTC) -+ SET_PCI_IDE_REG(CAST) -+ SET_PCI_IDE_REG(ETC) -+ SET_PCI_IDE_REG(PM) - default: - break; - } -@@ -99,94 +89,82 @@ - - u32 pci_ide_read_reg(int reg) - { -- u32 conf_data = 0; -+ u32 cfg = 0; - u32 hi, lo; - - switch (reg) { - case PCI_VENDOR_ID: -- conf_data = -- CFG_PCI_VENDOR_ID(CS5536_IDE_DEVICE_ID, CS5536_VENDOR_ID); -+ cfg = CFG_PCI_VENDOR_ID(CS5536_IDE_DEVICE_ID, -+ CS5536_VENDOR_ID); - break; - case PCI_COMMAND: - _rdmsr(IDE_MSR_REG(IDE_IO_BAR), &hi, &lo); - if (lo & 0xfffffff0) -- conf_data |= PCI_COMMAND_IO; -+ cfg |= PCI_COMMAND_IO; - _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo); - if ((lo & 0x30) == 0x30) -- conf_data |= PCI_COMMAND_MASTER; -+ cfg |= PCI_COMMAND_MASTER; - break; - case PCI_STATUS: -- conf_data |= PCI_STATUS_66MHZ; -- conf_data |= PCI_STATUS_FAST_BACK; -+ cfg |= PCI_STATUS_66MHZ; -+ cfg |= PCI_STATUS_FAST_BACK; - _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); - if (lo & SB_PARE_ERR_FLAG) -- conf_data |= PCI_STATUS_PARITY; -- conf_data |= PCI_STATUS_DEVSEL_MEDIUM; -+ cfg |= PCI_STATUS_PARITY; -+ cfg |= PCI_STATUS_DEVSEL_MEDIUM; - break; - case PCI_CLASS_REVISION: - _rdmsr(IDE_MSR_REG(IDE_CAP), &hi, &lo); -- conf_data = lo & 0x000000ff; -- conf_data |= (CS5536_IDE_CLASS_CODE << 8); -+ cfg = lo & 0x000000ff; -+ cfg |= (CS5536_IDE_CLASS_CODE << 8); - break; - case PCI_CACHE_LINE_SIZE: - _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo); - hi &= 0x000000f8; -- conf_data = CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, hi); -+ cfg = CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, hi); - break; - case PCI_BAR4_REG: - _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); - if (lo & SOFT_BAR_IDE_FLAG) { -- conf_data = CS5536_IDE_RANGE | -+ cfg = CS5536_IDE_RANGE | - PCI_BASE_ADDRESS_SPACE_IO; - lo &= ~SOFT_BAR_IDE_FLAG; - _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); - } else { - _rdmsr(IDE_MSR_REG(IDE_IO_BAR), &hi, &lo); -- conf_data = lo & 0xfffffff0; -- conf_data |= 0x01; -- conf_data &= ~0x02; -+ cfg = lo & 0xfffffff0; -+ cfg |= 0x01; -+ cfg &= ~0x02; - } - break; - case PCI_CARDBUS_CIS: -- conf_data = PCI_CARDBUS_CIS_POINTER; -+ cfg = PCI_CARDBUS_CIS_POINTER; - break; - case PCI_SUBSYSTEM_VENDOR_ID: -- conf_data = -- CFG_PCI_VENDOR_ID(CS5536_IDE_SUB_ID, CS5536_SUB_VENDOR_ID); -+ cfg = CFG_PCI_VENDOR_ID(CS5536_IDE_SUB_ID, -+ CS5536_SUB_VENDOR_ID); - break; - case PCI_ROM_ADDRESS: -- conf_data = PCI_EXPANSION_ROM_BAR; -+ cfg = PCI_EXPANSION_ROM_BAR; - break; - case PCI_CAPABILITY_LIST: -- conf_data = PCI_CAPLIST_POINTER; -+ cfg = PCI_CAPLIST_POINTER; - break; - case PCI_INTERRUPT_LINE: -- conf_data = -- CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_IDE_INTR); -- break; -- case PCI_IDE_CFG_REG: -- _rdmsr(IDE_MSR_REG(IDE_CFG), &hi, &lo); -- conf_data = lo; -- break; -- case PCI_IDE_DTC_REG: -- _rdmsr(IDE_MSR_REG(IDE_DTC), &hi, &lo); -- conf_data = lo; -- break; -- case PCI_IDE_CAST_REG: -- _rdmsr(IDE_MSR_REG(IDE_CAST), &hi, &lo); -- conf_data = lo; -- break; -- case PCI_IDE_ETC_REG: -- _rdmsr(IDE_MSR_REG(IDE_ETC), &hi, &lo); -- conf_data = lo; -- break; -- case PCI_IDE_PM_REG: -- _rdmsr(IDE_MSR_REG(IDE_INTERNAL_PM), &hi, &lo); -- conf_data = lo; -+ cfg = CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_IDE_INTR); - break; -+#define GET_PCI_IDE_REG(r) \ -+ case PCI_IDE_##r##_REG: \ -+ _rdmsr(IDE_MSR_REG(IDE_##r), &hi, &cfg); \ -+ break; -+ GET_PCI_IDE_REG(CFG) -+ GET_PCI_IDE_REG(DTC) -+ GET_PCI_IDE_REG(CAST) -+ GET_PCI_IDE_REG(ETC) -+ GET_PCI_IDE_REG(PM) - default: - break; - } - -- return conf_data; -+ return cfg; - } -diff -Nur linux-2.6.37.orig/arch/mips/loongson/common/cs5536/cs5536_ohci.c linux-2.6.37/arch/mips/loongson/common/cs5536/cs5536_ohci.c ---- linux-2.6.37.orig/arch/mips/loongson/common/cs5536/cs5536_ohci.c 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/mips/loongson/common/cs5536/cs5536_ohci.c 2011-01-11 20:44:43.000000000 +0100 -@@ -18,7 +18,7 @@ - - void pci_ohci_write_reg(int reg, u32 value) - { -- u32 hi = 0, lo = value; -+ u32 hi, lo; - - switch (reg) { - case PCI_COMMAND: -@@ -73,77 +73,75 @@ - - u32 pci_ohci_read_reg(int reg) - { -- u32 conf_data = 0; -+ u32 cfg = 0; - u32 hi, lo; - - switch (reg) { - case PCI_VENDOR_ID: -- conf_data = -- CFG_PCI_VENDOR_ID(CS5536_OHCI_DEVICE_ID, CS5536_VENDOR_ID); -+ cfg = CFG_PCI_VENDOR_ID(CS5536_OHCI_DEVICE_ID, -+ CS5536_VENDOR_ID); - break; - case PCI_COMMAND: - _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo); - if (hi & PCI_COMMAND_MASTER) -- conf_data |= PCI_COMMAND_MASTER; -+ cfg |= PCI_COMMAND_MASTER; - if (hi & PCI_COMMAND_MEMORY) -- conf_data |= PCI_COMMAND_MEMORY; -+ cfg |= PCI_COMMAND_MEMORY; - break; - case PCI_STATUS: -- conf_data |= PCI_STATUS_66MHZ; -- conf_data |= PCI_STATUS_FAST_BACK; -+ cfg |= PCI_STATUS_66MHZ; -+ cfg |= PCI_STATUS_FAST_BACK; - _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); - if (lo & SB_PARE_ERR_FLAG) -- conf_data |= PCI_STATUS_PARITY; -- conf_data |= PCI_STATUS_DEVSEL_MEDIUM; -+ cfg |= PCI_STATUS_PARITY; -+ cfg |= PCI_STATUS_DEVSEL_MEDIUM; - break; - case PCI_CLASS_REVISION: - _rdmsr(USB_MSR_REG(USB_CAP), &hi, &lo); -- conf_data = lo & 0x000000ff; -- conf_data |= (CS5536_OHCI_CLASS_CODE << 8); -+ cfg = lo & 0x000000ff; -+ cfg |= (CS5536_OHCI_CLASS_CODE << 8); - break; - case PCI_CACHE_LINE_SIZE: -- conf_data = -- CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, -- PCI_NORMAL_LATENCY_TIMER); -+ cfg = CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, -+ PCI_NORMAL_LATENCY_TIMER); - break; - case PCI_BAR0_REG: - _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); - if (lo & SOFT_BAR_OHCI_FLAG) { -- conf_data = CS5536_OHCI_RANGE | -+ cfg = CS5536_OHCI_RANGE | - PCI_BASE_ADDRESS_SPACE_MEMORY; - lo &= ~SOFT_BAR_OHCI_FLAG; - _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); - } else { - _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo); -- conf_data = lo & 0xffffff00; -- conf_data &= ~0x0000000f; /* 32bit mem */ -+ cfg = lo & 0xffffff00; -+ cfg &= ~0x0000000f; /* 32bit mem */ - } - break; - case PCI_CARDBUS_CIS: -- conf_data = PCI_CARDBUS_CIS_POINTER; -+ cfg = PCI_CARDBUS_CIS_POINTER; - break; - case PCI_SUBSYSTEM_VENDOR_ID: -- conf_data = -- CFG_PCI_VENDOR_ID(CS5536_OHCI_SUB_ID, CS5536_SUB_VENDOR_ID); -+ cfg = CFG_PCI_VENDOR_ID(CS5536_OHCI_SUB_ID, -+ CS5536_SUB_VENDOR_ID); - break; - case PCI_ROM_ADDRESS: -- conf_data = PCI_EXPANSION_ROM_BAR; -+ cfg = PCI_EXPANSION_ROM_BAR; - break; - case PCI_CAPABILITY_LIST: -- conf_data = PCI_CAPLIST_USB_POINTER; -+ cfg = PCI_CAPLIST_USB_POINTER; - break; - case PCI_INTERRUPT_LINE: -- conf_data = -- CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR); -+ cfg = CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR); - break; - case PCI_OHCI_INT_REG: - _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo); - if ((lo & 0x00000f00) == CS5536_USB_INTR) -- conf_data = 1; -+ cfg = 1; - break; - default: - break; - } - -- return conf_data; -+ return cfg; - } -diff -Nur linux-2.6.37.orig/arch/mips/loongson/common/mtd.c linux-2.6.37/arch/mips/loongson/common/mtd.c ---- linux-2.6.37.orig/arch/mips/loongson/common/mtd.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/loongson/common/mtd.c 2011-01-11 20:44:43.000000000 +0100 -@@ -0,0 +1,91 @@ -+/* -+ * Driver for flushing/dumping ROM of PMON on loongson family machines -+ * -+ * Copyright (C) 2008-2009 Lemote Inc. -+ * Author: Yan Hua -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include -+ -+#define FLASH_PHYS_ADDR LOONGSON_BOOT_BASE -+#define FLASH_SIZE 0x080000 -+ -+#define FLASH_PARTITION0_ADDR 0x00000000 -+#define FLASH_PARTITION0_SIZE 0x00080000 -+ -+struct map_info flash_map = { -+ .name = "flash device", -+ .size = FLASH_SIZE, -+ .bankwidth = 1, -+}; -+ -+struct mtd_partition flash_parts[] = { -+ { -+ .name = "Bootloader", -+ .offset = FLASH_PARTITION0_ADDR, -+ .size = FLASH_PARTITION0_SIZE}, -+}; -+ -+#define PARTITION_COUNT ARRAY_SIZE(flash_parts) -+ -+static struct mtd_info *mymtd; -+ -+int __init init_flash(void) -+{ -+ printk(KERN_NOTICE "flash device: %x at %x\n", -+ FLASH_SIZE, FLASH_PHYS_ADDR); -+ -+ flash_map.phys = FLASH_PHYS_ADDR; -+ flash_map.virt = ioremap(FLASH_PHYS_ADDR, FLASH_SIZE); -+ -+ if (!flash_map.virt) { -+ printk(KERN_NOTICE "Failed to ioremap\n"); -+ return -EIO; -+ } -+ -+ simple_map_init(&flash_map); -+ -+ mymtd = do_map_probe("cfi_probe", &flash_map); -+ if (mymtd) { -+ add_mtd_partitions(mymtd, flash_parts, PARTITION_COUNT); -+ printk(KERN_NOTICE "pmon flash device initialized\n"); -+ return 0; -+ } -+ -+ iounmap((void *)flash_map.virt); -+ return -ENXIO; -+} -+ -+static void __exit cleanup_flash(void) -+{ -+ if (mymtd) { -+ del_mtd_partitions(mymtd); -+ map_destroy(mymtd); -+ } -+ if (flash_map.virt) { -+ iounmap((void *)flash_map.virt); -+ flash_map.virt = 0; -+ } -+} -+ -+module_init(init_flash); -+module_exit(cleanup_flash); -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Yanhua "); -+MODULE_DESCRIPTION("MTD driver for pmon flushing/dumping"); -diff -Nur linux-2.6.37.orig/arch/mips/loongson/lemote-2f/Makefile linux-2.6.37/arch/mips/loongson/lemote-2f/Makefile ---- linux-2.6.37.orig/arch/mips/loongson/lemote-2f/Makefile 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/mips/loongson/lemote-2f/Makefile 2011-01-11 20:44:43.000000000 +0100 -@@ -2,7 +2,7 @@ - # Makefile for lemote loongson2f family machines - # - --obj-y += machtype.o irq.o reset.o ec_kb3310b.o -+obj-y += machtype.o irq.o reset.o ec_kb3310b.o platform.o - - # - # Suspend Support -diff -Nur linux-2.6.37.orig/arch/mips/loongson/lemote-2f/ec_kb3310b.c linux-2.6.37/arch/mips/loongson/lemote-2f/ec_kb3310b.c ---- linux-2.6.37.orig/arch/mips/loongson/lemote-2f/ec_kb3310b.c 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/mips/loongson/lemote-2f/ec_kb3310b.c 2011-01-11 20:44:43.000000000 +0100 -@@ -14,7 +14,7 @@ - #include - #include - --#include "ec_kb3310b.h" -+#include - - static DEFINE_SPINLOCK(index_access_lock); - static DEFINE_SPINLOCK(port_access_lock); -@@ -78,12 +78,9 @@ - spin_unlock_irqrestore(&port_access_lock, flags); - - if (timeout <= 0) { -- printk(KERN_ERR "%s: deadable error : timeout...\n", __func__); -+ pr_err("%s: deadable error : timeout...\n", __func__); - ret = -EINVAL; -- } else -- printk(KERN_INFO -- "(%x/%d)ec issued command %d status : 0x%x\n", -- timeout, EC_CMD_TIMEOUT - timeout, cmd, status); -+ } - - return ret; - } -@@ -118,8 +115,7 @@ - udelay(EC_REG_DELAY); - } - if (timeout <= 0) { -- pr_info("%s: get event number timeout.\n", __func__); -- -+ pr_err("%s: get event number timeout.\n", __func__); - return -EINVAL; - } - value = inb(EC_DAT_PORT); -diff -Nur linux-2.6.37.orig/arch/mips/loongson/lemote-2f/ec_kb3310b.h linux-2.6.37/arch/mips/loongson/lemote-2f/ec_kb3310b.h ---- linux-2.6.37.orig/arch/mips/loongson/lemote-2f/ec_kb3310b.h 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/mips/loongson/lemote-2f/ec_kb3310b.h 1970-01-01 01:00:00.000000000 +0100 -@@ -1,188 +0,0 @@ --/* -- * KB3310B Embedded Controller -- * -- * Copyright (C) 2008 Lemote Inc. -- * Author: liujl , 2008-03-14 -- * -- * This program is free software; you can redistribute it and/or modify -- * it under the terms of the GNU General Public License as published by -- * the Free Software Foundation; either version 2 of the License, or -- * (at your option) any later version. -- */ -- --#ifndef _EC_KB3310B_H --#define _EC_KB3310B_H -- --extern unsigned char ec_read(unsigned short addr); --extern void ec_write(unsigned short addr, unsigned char val); --extern int ec_query_seq(unsigned char cmd); --extern int ec_query_event_num(void); --extern int ec_get_event_num(void); -- --typedef int (*sci_handler) (int status); --extern sci_handler yeeloong_report_lid_status; -- --#define SCI_IRQ_NUM 0x0A -- --/* -- * The following registers are determined by the EC index configuration. -- * 1, fill the PORT_HIGH as EC register high part. -- * 2, fill the PORT_LOW as EC register low part. -- * 3, fill the PORT_DATA as EC register write data or get the data from it. -- */ --#define EC_IO_PORT_HIGH 0x0381 --#define EC_IO_PORT_LOW 0x0382 --#define EC_IO_PORT_DATA 0x0383 -- --/* -- * EC delay time is 500us for register and status access -- */ --#define EC_REG_DELAY 500 /* unit : us */ --#define EC_CMD_TIMEOUT 0x1000 -- --/* -- * EC access port for SCI communication -- */ --#define EC_CMD_PORT 0x66 --#define EC_STS_PORT 0x66 --#define EC_DAT_PORT 0x62 --#define CMD_INIT_IDLE_MODE 0xdd --#define CMD_EXIT_IDLE_MODE 0xdf --#define CMD_INIT_RESET_MODE 0xd8 --#define CMD_REBOOT_SYSTEM 0x8c --#define CMD_GET_EVENT_NUM 0x84 --#define CMD_PROGRAM_PIECE 0xda -- --/* temperature & fan registers */ --#define REG_TEMPERATURE_VALUE 0xF458 --#define REG_FAN_AUTO_MAN_SWITCH 0xF459 --#define BIT_FAN_AUTO 0 --#define BIT_FAN_MANUAL 1 --#define REG_FAN_CONTROL 0xF4D2 --#define BIT_FAN_CONTROL_ON (1 << 0) --#define BIT_FAN_CONTROL_OFF (0 << 0) --#define REG_FAN_STATUS 0xF4DA --#define BIT_FAN_STATUS_ON (1 << 0) --#define BIT_FAN_STATUS_OFF (0 << 0) --#define REG_FAN_SPEED_HIGH 0xFE22 --#define REG_FAN_SPEED_LOW 0xFE23 --#define REG_FAN_SPEED_LEVEL 0xF4CC --/* fan speed divider */ --#define FAN_SPEED_DIVIDER 480000 /* (60*1000*1000/62.5/2)*/ -- --/* battery registers */ --#define REG_BAT_DESIGN_CAP_HIGH 0xF77D --#define REG_BAT_DESIGN_CAP_LOW 0xF77E --#define REG_BAT_FULLCHG_CAP_HIGH 0xF780 --#define REG_BAT_FULLCHG_CAP_LOW 0xF781 --#define REG_BAT_DESIGN_VOL_HIGH 0xF782 --#define REG_BAT_DESIGN_VOL_LOW 0xF783 --#define REG_BAT_CURRENT_HIGH 0xF784 --#define REG_BAT_CURRENT_LOW 0xF785 --#define REG_BAT_VOLTAGE_HIGH 0xF786 --#define REG_BAT_VOLTAGE_LOW 0xF787 --#define REG_BAT_TEMPERATURE_HIGH 0xF788 --#define REG_BAT_TEMPERATURE_LOW 0xF789 --#define REG_BAT_RELATIVE_CAP_HIGH 0xF492 --#define REG_BAT_RELATIVE_CAP_LOW 0xF493 --#define REG_BAT_VENDOR 0xF4C4 --#define FLAG_BAT_VENDOR_SANYO 0x01 --#define FLAG_BAT_VENDOR_SIMPLO 0x02 --#define REG_BAT_CELL_COUNT 0xF4C6 --#define FLAG_BAT_CELL_3S1P 0x03 --#define FLAG_BAT_CELL_3S2P 0x06 --#define REG_BAT_CHARGE 0xF4A2 --#define FLAG_BAT_CHARGE_DISCHARGE 0x01 --#define FLAG_BAT_CHARGE_CHARGE 0x02 --#define FLAG_BAT_CHARGE_ACPOWER 0x00 --#define REG_BAT_STATUS 0xF4B0 --#define BIT_BAT_STATUS_LOW (1 << 5) --#define BIT_BAT_STATUS_DESTROY (1 << 2) --#define BIT_BAT_STATUS_FULL (1 << 1) --#define BIT_BAT_STATUS_IN (1 << 0) --#define REG_BAT_CHARGE_STATUS 0xF4B1 --#define BIT_BAT_CHARGE_STATUS_OVERTEMP (1 << 2) --#define BIT_BAT_CHARGE_STATUS_PRECHG (1 << 1) --#define REG_BAT_STATE 0xF482 --#define BIT_BAT_STATE_CHARGING (1 << 1) --#define BIT_BAT_STATE_DISCHARGING (1 << 0) --#define REG_BAT_POWER 0xF440 --#define BIT_BAT_POWER_S3 (1 << 2) --#define BIT_BAT_POWER_ON (1 << 1) --#define BIT_BAT_POWER_ACIN (1 << 0) -- --/* other registers */ --/* Audio: rd/wr */ --#define REG_AUDIO_VOLUME 0xF46C --#define REG_AUDIO_MUTE 0xF4E7 --#define REG_AUDIO_BEEP 0xF4D0 --/* USB port power or not: rd/wr */ --#define REG_USB0_FLAG 0xF461 --#define REG_USB1_FLAG 0xF462 --#define REG_USB2_FLAG 0xF463 --#define BIT_USB_FLAG_ON 1 --#define BIT_USB_FLAG_OFF 0 --/* LID */ --#define REG_LID_DETECT 0xF4BD --#define BIT_LID_DETECT_ON 1 --#define BIT_LID_DETECT_OFF 0 --/* CRT */ --#define REG_CRT_DETECT 0xF4AD --#define BIT_CRT_DETECT_PLUG 1 --#define BIT_CRT_DETECT_UNPLUG 0 --/* LCD backlight brightness adjust: 9 levels */ --#define REG_DISPLAY_BRIGHTNESS 0xF4F5 --/* Black screen Status */ --#define BIT_DISPLAY_LCD_ON 1 --#define BIT_DISPLAY_LCD_OFF 0 --/* LCD backlight control: off/restore */ --#define REG_BACKLIGHT_CTRL 0xF7BD --#define BIT_BACKLIGHT_ON 1 --#define BIT_BACKLIGHT_OFF 0 --/* Reset the machine auto-clear: rd/wr */ --#define REG_RESET 0xF4EC --#define BIT_RESET_ON 1 --/* Light the led: rd/wr */ --#define REG_LED 0xF4C8 --#define BIT_LED_RED_POWER (1 << 0) --#define BIT_LED_ORANGE_POWER (1 << 1) --#define BIT_LED_GREEN_CHARGE (1 << 2) --#define BIT_LED_RED_CHARGE (1 << 3) --#define BIT_LED_NUMLOCK (1 << 4) --/* Test led mode, all led on/off */ --#define REG_LED_TEST 0xF4C2 --#define BIT_LED_TEST_IN 1 --#define BIT_LED_TEST_OUT 0 --/* Camera on/off */ --#define REG_CAMERA_STATUS 0xF46A --#define BIT_CAMERA_STATUS_ON 1 --#define BIT_CAMERA_STATUS_OFF 0 --#define REG_CAMERA_CONTROL 0xF7B7 --#define BIT_CAMERA_CONTROL_OFF 0 --#define BIT_CAMERA_CONTROL_ON 1 --/* Wlan Status */ --#define REG_WLAN 0xF4FA --#define BIT_WLAN_ON 1 --#define BIT_WLAN_OFF 0 --#define REG_DISPLAY_LCD 0xF79F -- --/* SCI Event Number from EC */ --enum { -- EVENT_LID = 0x23, /* LID open/close */ -- EVENT_DISPLAY_TOGGLE, /* Fn+F3 for display switch */ -- EVENT_SLEEP, /* Fn+F1 for entering sleep mode */ -- EVENT_OVERTEMP, /* Over-temperature happened */ -- EVENT_CRT_DETECT, /* CRT is connected */ -- EVENT_CAMERA, /* Camera on/off */ -- EVENT_USB_OC2, /* USB2 Over Current occurred */ -- EVENT_USB_OC0, /* USB0 Over Current occurred */ -- EVENT_BLACK_SCREEN, /* Turn on/off backlight */ -- EVENT_AUDIO_MUTE, /* Mute on/off */ -- EVENT_DISPLAY_BRIGHTNESS,/* LCD backlight brightness adjust */ -- EVENT_AC_BAT, /* AC & Battery relative issue */ -- EVENT_AUDIO_VOLUME, /* Volume adjust */ -- EVENT_WLAN, /* Wlan on/off */ -- EVENT_END --}; -- --#endif /* !_EC_KB3310B_H */ -diff -Nur linux-2.6.37.orig/arch/mips/loongson/lemote-2f/platform.c linux-2.6.37/arch/mips/loongson/lemote-2f/platform.c ---- linux-2.6.37.orig/arch/mips/loongson/lemote-2f/platform.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/arch/mips/loongson/lemote-2f/platform.c 2011-01-11 20:44:43.000000000 +0100 -@@ -0,0 +1,48 @@ -+/* -+ * Copyright (C) 2009 Lemote Inc. -+ * Author: Wu Zhangjin, wuzhangjin@gmail.com -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ */ -+ -+#include -+#include -+ -+#include -+ -+static struct platform_device yeeloong_pdev = { -+ .name = "yeeloong_laptop", -+ .id = -1, -+}; -+ -+static struct platform_device lynloong_pdev = { -+ .name = "lynloong_pc", -+ .id = -1, -+}; -+ -+static int __init lemote2f_platform_init(void) -+{ -+ struct platform_device *pdev = NULL; -+ -+ switch (mips_machtype) { -+ case MACH_LEMOTE_YL2F89: -+ pdev = &yeeloong_pdev; -+ break; -+ case MACH_LEMOTE_LL2F: -+ pdev = &lynloong_pdev; -+ break; -+ default: -+ break; -+ -+ } -+ -+ if (pdev != NULL) -+ return platform_device_register(pdev); -+ -+ return -ENODEV; -+} -+ -+arch_initcall(lemote2f_platform_init); -diff -Nur linux-2.6.37.orig/arch/mips/loongson/lemote-2f/pm.c linux-2.6.37/arch/mips/loongson/lemote-2f/pm.c ---- linux-2.6.37.orig/arch/mips/loongson/lemote-2f/pm.c 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/mips/loongson/lemote-2f/pm.c 2011-01-11 20:44:43.000000000 +0100 -@@ -23,7 +23,7 @@ - #include - - #include --#include "ec_kb3310b.h" -+#include - - #define I8042_KBD_IRQ 1 - #define I8042_CTR_KBDINT 0x01 -@@ -100,7 +100,7 @@ - if (irq < 0) - return 0; - -- printk(KERN_INFO "%s: irq = %d\n", __func__, irq); -+ pr_info("%s: irq = %d\n", __func__, irq); - - if (irq == I8042_KBD_IRQ) - return 1; -diff -Nur linux-2.6.37.orig/arch/mips/loongson/lemote-2f/reset.c linux-2.6.37/arch/mips/loongson/lemote-2f/reset.c ---- linux-2.6.37.orig/arch/mips/loongson/lemote-2f/reset.c 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/mips/loongson/lemote-2f/reset.c 2011-01-11 20:44:43.000000000 +0100 -@@ -20,7 +20,7 @@ - #include - - #include --#include "ec_kb3310b.h" -+#include - - static void reset_cpu(void) - { -diff -Nur linux-2.6.37.orig/arch/mips/mm/dma-default.c linux-2.6.37/arch/mips/mm/dma-default.c ---- linux-2.6.37.orig/arch/mips/mm/dma-default.c 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/arch/mips/mm/dma-default.c 2011-01-11 20:46:19.000000000 +0100 -@@ -300,6 +300,20 @@ - - EXPORT_SYMBOL(dma_cache_sync); - -+int __weak dma_mmap_coherent(struct device *dev, struct vm_area_struct *vma, -+ void *cpu_addr, dma_addr_t handle, size_t size) -+{ -+ struct page *pg; -+ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); -+ cpu_addr = (void *)dma_addr_to_virt(dev, handle); -+ pg = virt_to_page(cpu_addr); -+ return remap_pfn_range(vma, vma->vm_start, -+ page_to_pfn(pg) + vma->vm_pgoff, -+ size, vma->vm_page_prot); -+} -+EXPORT_SYMBOL(dma_mmap_coherent); -+ -+ - static struct dma_map_ops mips_default_dma_map_ops = { - .alloc_coherent = mips_dma_alloc_coherent, - .free_coherent = mips_dma_free_coherent, -diff -Nur linux-2.6.37.orig/drivers/ide/ide-iops.c linux-2.6.37/drivers/ide/ide-iops.c ---- linux-2.6.37.orig/drivers/ide/ide-iops.c 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/ide/ide-iops.c 2011-01-11 20:44:43.000000000 +0100 -@@ -27,6 +27,8 @@ - #include - #include - -+#include -+ - void SELECT_MASK(ide_drive_t *drive, int mask) - { - const struct ide_port_ops *port_ops = drive->hwif->port_ops; -@@ -300,6 +302,9 @@ - { - const char **list, *m = (char *)&drive->id[ATA_ID_PROD]; - -+ if (mips_machtype != MACH_LEMOTE_YL2F89) -+ return; -+ - for (list = nien_quirk_list; *list != NULL; list++) - if (strstr(m, *list) != NULL) { - drive->dev_flags |= IDE_DFLAG_NIEN_QUIRK; -diff -Nur linux-2.6.37.orig/drivers/platform/Kconfig linux-2.6.37/drivers/platform/Kconfig ---- linux-2.6.37.orig/drivers/platform/Kconfig 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/platform/Kconfig 2011-01-11 20:44:43.000000000 +0100 -@@ -1,3 +1,7 @@ - if X86 - source "drivers/platform/x86/Kconfig" - endif -+ -+if MIPS -+source "drivers/platform/mips/Kconfig" -+endif -diff -Nur linux-2.6.37.orig/drivers/platform/Makefile linux-2.6.37/drivers/platform/Makefile ---- linux-2.6.37.orig/drivers/platform/Makefile 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/platform/Makefile 2011-01-11 20:44:43.000000000 +0100 -@@ -3,3 +3,4 @@ - # - - obj-$(CONFIG_X86) += x86/ -+obj-$(CONFIG_MIPS) += mips/ -diff -Nur linux-2.6.37.orig/drivers/platform/mips/Kconfig linux-2.6.37/drivers/platform/mips/Kconfig ---- linux-2.6.37.orig/drivers/platform/mips/Kconfig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/drivers/platform/mips/Kconfig 2011-01-11 20:44:43.000000000 +0100 -@@ -0,0 +1,43 @@ -+# -+# MIPS Platform Specific Drivers -+# -+ -+menuconfig MIPS_PLATFORM_DEVICES -+ bool "MIPS Platform Specific Device Drivers" -+ default y -+ help -+ Say Y here to get to see options for device drivers of various -+ MIPS platforms, including vendor-specific netbook/laptop/pc extension -+ drivers. This option alone does not add any kernel code. -+ -+ If you say N, all options in this submenu will be skipped and disabled. -+ -+if MIPS_PLATFORM_DEVICES -+ -+config LEMOTE_YEELOONG2F -+ tristate "Lemote YeeLoong Laptop" -+ depends on LEMOTE_MACH2F -+ select BACKLIGHT_CLASS_DEVICE -+ select POWER_SUPPLY -+ select HWMON -+ select VIDEO_OUTPUT_CONTROL -+ select INPUT_SPARSEKMAP -+ depends on INPUT -+ help -+ YeeLoong netbook is a mini laptop made by Lemote, which is basically -+ compatible to FuLoong2F mini PC, but it has an extra Embedded -+ Controller(kb3310b) for battery, hotkey, backlight, temperature and -+ fan management. -+ -+config LEMOTE_LYNLOONG2F -+ tristate "Lemote LynLoong PC" -+ depends on LEMOTE_MACH2F -+ select BACKLIGHT_CLASS_DEVICE -+ select VIDEO_OUTPUT_CONTROL -+ help -+ LynLoong PC is an AllINONE machine made by Lemote, which is basically -+ compatible to FuLoong2F Mini PC, the only difference is that it has a -+ size-fixed screen: 1360x768 with sisfb video driver. and also, it has -+ its own specific suspend support. -+ -+endif # MIPS_PLATFORM_DEVICES -diff -Nur linux-2.6.37.orig/drivers/platform/mips/Makefile linux-2.6.37/drivers/platform/mips/Makefile ---- linux-2.6.37.orig/drivers/platform/mips/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/drivers/platform/mips/Makefile 2011-01-11 20:44:43.000000000 +0100 -@@ -0,0 +1,7 @@ -+# -+# Makefile for MIPS Platform-Specific Drivers -+# -+ -+obj-$(CONFIG_LEMOTE_YEELOONG2F) += yeeloong_laptop.o -+ -+obj-$(CONFIG_LEMOTE_LYNLOONG2F) += lynloong_pc.o -diff -Nur linux-2.6.37.orig/drivers/platform/mips/lynloong_pc.c linux-2.6.37/drivers/platform/mips/lynloong_pc.c ---- linux-2.6.37.orig/drivers/platform/mips/lynloong_pc.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/drivers/platform/mips/lynloong_pc.c 2011-01-11 20:44:43.000000000 +0100 -@@ -0,0 +1,513 @@ -+/* -+ * Driver for LynLoong PC extras -+ * -+ * Copyright (C) 2009 Lemote Inc. -+ * Author: Wu Zhangjin , Xiang Yu -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include /* for backlight subdriver */ -+#include -+#include /* for video output subdriver */ -+#include /* for suspend support */ -+ -+#include -+#include -+ -+#include -+ -+static u32 gpio_base, mfgpt_base; -+ -+static void set_gpio_reg_high(int gpio, int reg) -+{ -+ u32 val; -+ -+ val = inl(gpio_base + reg); -+ val |= (1 << gpio); -+ val &= ~(1 << (16 + gpio)); -+ outl(val, gpio_base + reg); -+ mmiowb(); -+} -+ -+static void set_gpio_reg_low(int gpio, int reg) -+{ -+ u32 val; -+ -+ val = inl(gpio_base + reg); -+ val |= (1 << (16 + gpio)); -+ val &= ~(1 << gpio); -+ outl(val, gpio_base + reg); -+ mmiowb(); -+} -+ -+static void set_gpio_output_low(int gpio) -+{ -+ set_gpio_reg_high(gpio, GPIOL_OUT_EN); -+ set_gpio_reg_low(gpio, GPIOL_OUT_VAL); -+} -+ -+static void set_gpio_output_high(int gpio) -+{ -+ set_gpio_reg_high(gpio, GPIOL_OUT_EN); -+ set_gpio_reg_high(gpio, GPIOL_OUT_VAL); -+} -+ -+/* backlight subdriver */ -+ -+#define MAX_BRIGHTNESS 100 -+#define DEFAULT_BRIGHTNESS 50 -+#define MIN_BRIGHTNESS 0 -+static unsigned int level; -+ -+DEFINE_SPINLOCK(backlight_lock); -+/* Tune the brightness */ -+static void setup_mfgpt2(void) -+{ -+ unsigned long flags; -+ -+ spin_lock_irqsave(&backlight_lock, flags); -+ -+ /* Set MFGPT2 comparator 1,2 */ -+ outw(MAX_BRIGHTNESS-level, MFGPT2_CMP1); -+ outw(MAX_BRIGHTNESS, MFGPT2_CMP2); -+ /* Clear MFGPT2 UP COUNTER */ -+ outw(0, MFGPT2_CNT); -+ /* Enable counter, compare mode, 32k */ -+ outw(0x8280, MFGPT2_SETUP); -+ -+ spin_unlock_irqrestore(&backlight_lock, flags); -+} -+ -+static int lynloong_set_brightness(struct backlight_device *bd) -+{ -+ level = (bd->props.fb_blank == FB_BLANK_UNBLANK && -+ bd->props.power == FB_BLANK_UNBLANK) ? -+ bd->props.brightness : 0; -+ -+ if (level > MAX_BRIGHTNESS) -+ level = MAX_BRIGHTNESS; -+ else if (level < MIN_BRIGHTNESS) -+ level = MIN_BRIGHTNESS; -+ -+ setup_mfgpt2(); -+ -+ return 0; -+} -+ -+static int lynloong_get_brightness(struct backlight_device *bd) -+{ -+ return level; -+} -+ -+static struct backlight_ops backlight_ops = { -+ .get_brightness = lynloong_get_brightness, -+ .update_status = lynloong_set_brightness, -+}; -+ -+static struct backlight_device *lynloong_backlight_dev; -+ -+static int lynloong_backlight_init(void) -+{ -+ int ret; -+ u32 hi; -+ struct backlight_properties props; -+ -+ /* Get gpio_base */ -+ _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_GPIO), &hi, &gpio_base); -+ /* Get mfgpt_base */ -+ _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), &hi, &mfgpt_base); -+ /* Get gpio_base */ -+ _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_GPIO), &hi, &gpio_base); -+ -+ /* Select for mfgpt */ -+ set_gpio_reg_high(7, GPIOL_OUT_AUX1_SEL); -+ /* Enable brightness controlling */ -+ set_gpio_output_high(7); -+ -+ memset(&props, 0, sizeof(struct backlight_properties)); -+ props.max_brightness = MAX_BRIGHTNESS; -+ lynloong_backlight_dev = backlight_device_register("backlight0", NULL, -+ NULL, &backlight_ops, &props); -+ -+ if (IS_ERR(lynloong_backlight_dev)) { -+ ret = PTR_ERR(lynloong_backlight_dev); -+ return ret; -+ } -+ -+ lynloong_backlight_dev->props.brightness = DEFAULT_BRIGHTNESS; -+ backlight_update_status(lynloong_backlight_dev); -+ -+ return 0; -+} -+ -+static void lynloong_backlight_exit(void) -+{ -+ if (lynloong_backlight_dev) { -+ backlight_device_unregister(lynloong_backlight_dev); -+ lynloong_backlight_dev = NULL; -+ } -+ /* Disable brightness controlling */ -+ set_gpio_output_low(7); -+} -+ -+/* video output driver */ -+static int vo_status = 1; -+ -+static int lcd_video_output_get(struct output_device *od) -+{ -+ return vo_status; -+} -+ -+static int lcd_video_output_set(struct output_device *od) -+{ -+ int i; -+ unsigned long status; -+ -+ status = !!od->request_state; -+ -+ if (status == 0) { -+ /* Set the current status as off */ -+ vo_status = 0; -+ /* Turn off the backlight */ -+ set_gpio_output_low(11); -+ for (i = 0; i < 0x500; i++) -+ delay(); -+ /* Turn off the LCD */ -+ set_gpio_output_high(8); -+ } else { -+ /* Turn on the LCD */ -+ set_gpio_output_low(8); -+ for (i = 0; i < 0x500; i++) -+ delay(); -+ /* Turn on the backlight */ -+ set_gpio_output_high(11); -+ /* Set the current status as on */ -+ vo_status = 1; -+ } -+ -+ return 0; -+} -+ -+static struct output_properties lcd_output_properties = { -+ .set_state = lcd_video_output_set, -+ .get_status = lcd_video_output_get, -+}; -+ -+static struct output_device *lcd_output_dev; -+ -+static void lynloong_lcd_vo_set(int status) -+{ -+ lcd_output_dev->request_state = status; -+ lcd_video_output_set(lcd_output_dev); -+} -+ -+static int lynloong_vo_init(void) -+{ -+ int ret; -+ -+ /* Register video output device: lcd */ -+ lcd_output_dev = video_output_register("LCD", NULL, NULL, -+ &lcd_output_properties); -+ -+ if (IS_ERR(lcd_output_dev)) { -+ ret = PTR_ERR(lcd_output_dev); -+ lcd_output_dev = NULL; -+ return ret; -+ } -+ /* Ensure LCD is on by default */ -+ lynloong_lcd_vo_set(1); -+ -+ return 0; -+} -+ -+static void lynloong_vo_exit(void) -+{ -+ if (lcd_output_dev) { -+ video_output_unregister(lcd_output_dev); -+ lcd_output_dev = NULL; -+ } -+} -+ -+/* suspend support */ -+ -+#ifdef CONFIG_PM -+ -+static u32 smb_base; -+ -+/* I2C operations */ -+ -+static int i2c_wait(void) -+{ -+ char c; -+ int i; -+ -+ udelay(1000); -+ for (i = 0; i < 20; i++) { -+ c = inb(smb_base | SMB_STS); -+ if (c & (SMB_STS_BER | SMB_STS_NEGACK)) -+ return -1; -+ if (c & SMB_STS_SDAST) -+ return 0; -+ udelay(100); -+ } -+ return -2; -+} -+ -+static void i2c_read_single(int addr, int regNo, char *value) -+{ -+ unsigned char c; -+ -+ /* Start condition */ -+ c = inb(smb_base | SMB_CTRL1); -+ outb(c | SMB_CTRL1_START, smb_base | SMB_CTRL1); -+ i2c_wait(); -+ -+ /* Send slave address */ -+ outb(addr & 0xfe, smb_base | SMB_SDA); -+ i2c_wait(); -+ -+ /* Acknowledge smbus */ -+ c = inb(smb_base | SMB_CTRL1); -+ outb(c | SMB_CTRL1_ACK, smb_base | SMB_CTRL1); -+ -+ /* Send register index */ -+ outb(regNo, smb_base | SMB_SDA); -+ i2c_wait(); -+ -+ /* Acknowledge smbus */ -+ c = inb(smb_base | SMB_CTRL1); -+ outb(c | SMB_CTRL1_ACK, smb_base | SMB_CTRL1); -+ -+ /* Start condition again */ -+ c = inb(smb_base | SMB_CTRL1); -+ outb(c | SMB_CTRL1_START, smb_base | SMB_CTRL1); -+ i2c_wait(); -+ -+ /* Send salve address again */ -+ outb(1 | addr, smb_base | SMB_SDA); -+ i2c_wait(); -+ -+ /* Acknowledge smbus */ -+ c = inb(smb_base | SMB_CTRL1); -+ outb(c | SMB_CTRL1_ACK, smb_base | SMB_CTRL1); -+ -+ /* Read data */ -+ *value = inb(smb_base | SMB_SDA); -+ -+ /* Stop condition */ -+ outb(SMB_CTRL1_STOP, smb_base | SMB_CTRL1); -+ i2c_wait(); -+} -+ -+static void i2c_write_single(int addr, int regNo, char value) -+{ -+ unsigned char c; -+ -+ /* Start condition */ -+ c = inb(smb_base | SMB_CTRL1); -+ outb(c | SMB_CTRL1_START, smb_base | SMB_CTRL1); -+ i2c_wait(); -+ /* Send slave address */ -+ outb(addr & 0xfe, smb_base | SMB_SDA); -+ i2c_wait();; -+ -+ /* Send register index */ -+ outb(regNo, smb_base | SMB_SDA); -+ i2c_wait(); -+ -+ /* Write data */ -+ outb(value, smb_base | SMB_SDA); -+ i2c_wait(); -+ /* Stop condition */ -+ outb(SMB_CTRL1_STOP, smb_base | SMB_CTRL1); -+ i2c_wait(); -+} -+ -+static void stop_clock(int clk_reg, int clk_sel) -+{ -+ u8 value; -+ -+ i2c_read_single(0xd3, clk_reg, &value); -+ value &= ~(1 << clk_sel); -+ i2c_write_single(0xd2, clk_reg, value); -+} -+ -+static void enable_clock(int clk_reg, int clk_sel) -+{ -+ u8 value; -+ -+ i2c_read_single(0xd3, clk_reg, &value); -+ value |= (1 << clk_sel); -+ i2c_write_single(0xd2, clk_reg, value); -+} -+ -+static char cached_clk_freq; -+static char cached_pci_fixed_freq; -+ -+static void decrease_clk_freq(void) -+{ -+ char value; -+ -+ i2c_read_single(0xd3, 1, &value); -+ cached_clk_freq = value; -+ -+ /* Select frequency by software */ -+ value |= (1 << 1); -+ /* CPU, 3V66, PCI : 100, 66, 33(1) */ -+ value |= (1 << 2); -+ i2c_write_single(0xd2, 1, value); -+ -+ /* Cache the pci frequency */ -+ i2c_read_single(0xd3, 14, &value); -+ cached_pci_fixed_freq = value; -+ -+ /* Enable PCI fix mode */ -+ value |= (1 << 5); -+ /* 3V66, PCI : 64MHz, 32MHz */ -+ value |= (1 << 3); -+ i2c_write_single(0xd2, 14, value); -+ -+} -+ -+static void resume_clk_freq(void) -+{ -+ i2c_write_single(0xd2, 1, cached_clk_freq); -+ i2c_write_single(0xd2, 14, cached_pci_fixed_freq); -+} -+ -+static void stop_clocks(void) -+{ -+ /* CPU Clock Register */ -+ stop_clock(2, 5); /* not used */ -+ stop_clock(2, 6); /* not used */ -+ stop_clock(2, 7); /* not used */ -+ -+ /* PCI Clock Register */ -+ stop_clock(3, 1); /* 8100 */ -+ stop_clock(3, 5); /* SIS */ -+ stop_clock(3, 0); /* not used */ -+ stop_clock(3, 6); /* not used */ -+ -+ /* PCI 48M Clock Register */ -+ stop_clock(4, 6); /* USB grounding */ -+ stop_clock(4, 5); /* REF(5536_14M) */ -+ -+ /* 3V66 Control Register */ -+ stop_clock(5, 0); /* VCH_CLK..., grounding */ -+} -+ -+static void enable_clocks(void) -+{ -+ enable_clock(3, 1); /* 8100 */ -+ enable_clock(3, 5); /* SIS */ -+ -+ enable_clock(4, 6); -+ enable_clock(4, 5); /* REF(5536_14M) */ -+ -+ enable_clock(5, 0); /* VCH_CLOCK, grounding */ -+} -+ -+static int lynloong_suspend(struct device *dev) -+{ -+ /* Disable AMP */ -+ set_gpio_output_high(6); -+ /* Turn off LCD */ -+ lynloong_lcd_vo_set(0); -+ -+ /* Stop the clocks of some devices */ -+ stop_clocks(); -+ -+ /* Decrease the external clock frequency */ -+ decrease_clk_freq(); -+ -+ return 0; -+} -+ -+static int lynloong_resume(struct device *dev) -+{ -+ /* Turn on the LCD */ -+ lynloong_lcd_vo_set(1); -+ -+ /* Resume clock frequency, enable the relative clocks */ -+ resume_clk_freq(); -+ enable_clocks(); -+ -+ /* Enable AMP */ -+ set_gpio_output_low(6); -+ -+ return 0; -+} -+ -+static const SIMPLE_DEV_PM_OPS(lynloong_pm_ops, lynloong_suspend, -+ lynloong_resume); -+#endif /* !CONFIG_PM */ -+ -+static struct platform_device_id platform_device_ids[] = { -+ { -+ .name = "lynloong_pc", -+ }, -+ {} -+}; -+ -+MODULE_DEVICE_TABLE(platform, platform_device_ids); -+ -+static struct platform_driver platform_driver = { -+ .driver = { -+ .name = "lynloong_pc", -+ .owner = THIS_MODULE, -+#ifdef CONFIG_PM -+ .pm = &lynloong_pm_ops, -+#endif -+ }, -+ .id_table = platform_device_ids, -+}; -+ -+static int __init lynloong_init(void) -+{ -+ int ret; -+ -+ pr_info("Load LynLoong Platform Specific Driver.\n"); -+ -+ /* Register platform stuff */ -+ ret = platform_driver_register(&platform_driver); -+ if (ret) { -+ pr_err("Fail to register lynloong platform driver.\n"); -+ return ret; -+ } -+ -+ ret = lynloong_backlight_init(); -+ if (ret) { -+ pr_err("Fail to register lynloong backlight driver.\n"); -+ return ret; -+ } -+ -+ ret = lynloong_vo_init(); -+ if (ret) { -+ pr_err("Fail to register lynloong backlight driver.\n"); -+ lynloong_vo_exit(); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static void __exit lynloong_exit(void) -+{ -+ lynloong_vo_exit(); -+ lynloong_backlight_exit(); -+ platform_driver_unregister(&platform_driver); -+ -+ pr_info("Unload LynLoong Platform Specific Driver.\n"); -+} -+ -+module_init(lynloong_init); -+module_exit(lynloong_exit); -+ -+MODULE_AUTHOR("Wu Zhangjin ; Xiang Yu "); -+MODULE_DESCRIPTION("LynLoong PC driver"); -+MODULE_LICENSE("GPL"); -diff -Nur linux-2.6.37.orig/drivers/platform/mips/yeeloong_ecrom.c linux-2.6.37/drivers/platform/mips/yeeloong_ecrom.c ---- linux-2.6.37.orig/drivers/platform/mips/yeeloong_ecrom.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/drivers/platform/mips/yeeloong_ecrom.c 2011-01-11 20:44:43.000000000 +0100 -@@ -0,0 +1,943 @@ -+/* -+ * Driver for flushing/dumping ROM of EC on YeeLoong laptop -+ * -+ * Copyright (C) 2009 Lemote Inc. -+ * Author: liujl -+ * -+ * NOTE : -+ * The EC resources accessing and programming are supported. -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include -+ -+#define EC_MISC_DEV "ec_misc" -+#define EC_IOC_MAGIC 'E' -+ -+/* ec registers range */ -+#define EC_MAX_REGADDR 0xFFFF -+#define EC_MIN_REGADDR 0xF000 -+#define EC_RAM_ADDR 0xF800 -+ -+/* version burned address */ -+#define VER_ADDR 0xf7a1 -+#define VER_MAX_SIZE 7 -+#define EC_ROM_MAX_SIZE 0x10000 -+ -+/* ec internal register */ -+#define REG_POWER_MODE 0xF710 -+#define FLAG_NORMAL_MODE 0x00 -+#define FLAG_IDLE_MODE 0x01 -+#define FLAG_RESET_MODE 0x02 -+ -+/* ec update program flag */ -+#define PROGRAM_FLAG_NONE 0x00 -+#define PROGRAM_FLAG_IE 0x01 -+#define PROGRAM_FLAG_ROM 0x02 -+ -+/* XBI relative registers */ -+#define REG_XBISEG0 0xFEA0 -+#define REG_XBISEG1 0xFEA1 -+#define REG_XBIRSV2 0xFEA2 -+#define REG_XBIRSV3 0xFEA3 -+#define REG_XBIRSV4 0xFEA4 -+#define REG_XBICFG 0xFEA5 -+#define REG_XBICS 0xFEA6 -+#define REG_XBIWE 0xFEA7 -+#define REG_XBISPIA0 0xFEA8 -+#define REG_XBISPIA1 0xFEA9 -+#define REG_XBISPIA2 0xFEAA -+#define REG_XBISPIDAT 0xFEAB -+#define REG_XBISPICMD 0xFEAC -+#define REG_XBISPICFG 0xFEAD -+#define REG_XBISPIDATR 0xFEAE -+#define REG_XBISPICFG2 0xFEAF -+ -+/* commands definition for REG_XBISPICMD */ -+#define SPICMD_WRITE_STATUS 0x01 -+#define SPICMD_BYTE_PROGRAM 0x02 -+#define SPICMD_READ_BYTE 0x03 -+#define SPICMD_WRITE_DISABLE 0x04 -+#define SPICMD_READ_STATUS 0x05 -+#define SPICMD_WRITE_ENABLE 0x06 -+#define SPICMD_HIGH_SPEED_READ 0x0B -+#define SPICMD_POWER_DOWN 0xB9 -+#define SPICMD_SST_EWSR 0x50 -+#define SPICMD_SST_SEC_ERASE 0x20 -+#define SPICMD_SST_BLK_ERASE 0x52 -+#define SPICMD_SST_CHIP_ERASE 0x60 -+#define SPICMD_FRDO 0x3B -+#define SPICMD_SEC_ERASE 0xD7 -+#define SPICMD_BLK_ERASE 0xD8 -+#define SPICMD_CHIP_ERASE 0xC7 -+ -+/* bits definition for REG_XBISPICFG */ -+#define SPICFG_AUTO_CHECK 0x01 -+#define SPICFG_SPI_BUSY 0x02 -+#define SPICFG_DUMMY_READ 0x04 -+#define SPICFG_EN_SPICMD 0x08 -+#define SPICFG_LOW_SPICS 0x10 -+#define SPICFG_EN_SHORT_READ 0x20 -+#define SPICFG_EN_OFFSET_READ 0x40 -+#define SPICFG_EN_FAST_READ 0x80 -+ -+/* watchdog timer registers */ -+#define REG_WDTCFG 0xfe80 -+#define REG_WDTPF 0xfe81 -+#define REG_WDT 0xfe82 -+ -+/* lpc configure register */ -+#define REG_LPCCFG 0xfe95 -+ -+/* 8051 reg */ -+#define REG_PXCFG 0xff14 -+ -+/* Fan register in KB3310 */ -+#define REG_ECFAN_SPEED_LEVEL 0xf4e4 -+#define REG_ECFAN_SWITCH 0xf4d2 -+ -+/* the ec flash rom id number */ -+#define EC_ROM_PRODUCT_ID_SPANSION 0x01 -+#define EC_ROM_PRODUCT_ID_MXIC 0xC2 -+#define EC_ROM_PRODUCT_ID_AMIC 0x37 -+#define EC_ROM_PRODUCT_ID_EONIC 0x1C -+ -+/* misc ioctl operations */ -+#define IOCTL_RDREG _IOR(EC_IOC_MAGIC, 1, int) -+#define IOCTL_WRREG _IOW(EC_IOC_MAGIC, 2, int) -+#define IOCTL_READ_EC _IOR(EC_IOC_MAGIC, 3, int) -+#define IOCTL_PROGRAM_IE _IOW(EC_IOC_MAGIC, 4, int) -+#define IOCTL_PROGRAM_EC _IOW(EC_IOC_MAGIC, 5, int) -+ -+/* start address for programming of EC content or IE */ -+/* ec running code start address */ -+#define EC_START_ADDR 0x00000000 -+/* ec information element storing address */ -+#define IE_START_ADDR 0x00020000 -+ -+/* EC state */ -+#define EC_STATE_IDLE 0x00 /* ec in idle state */ -+#define EC_STATE_BUSY 0x01 /* ec in busy state */ -+ -+/* timeout value for programming */ -+#define EC_FLASH_TIMEOUT 0x1000 /* ec program timeout */ -+/* command checkout timeout including cmd to port or state flag check */ -+#define EC_CMD_TIMEOUT 0x1000 -+#define EC_SPICMD_STANDARD_TIMEOUT (4 * 1000) /* unit : us */ -+#define EC_MAX_DELAY_UNIT (10) /* every time for polling */ -+#define SPI_FINISH_WAIT_TIME 10 -+/* EC content max size */ -+#define EC_CONTENT_MAX_SIZE (64 * 1024) -+#define IE_CONTENT_MAX_SIZE (0x100000 - IE_START_ADDR) -+ -+/* the register operation access struct */ -+struct ec_reg { -+ u32 addr; /* the address of kb3310 registers */ -+ u8 val; /* the register value */ -+}; -+ -+struct ec_info { -+ u32 start_addr; -+ u32 size; -+ u8 *buf; -+}; -+ -+/* open for using rom protection action */ -+#define EC_ROM_PROTECTION -+ -+/* enable the chip reset mode */ -+static int ec_init_reset_mode(void) -+{ -+ int timeout; -+ unsigned char status = 0; -+ int ret = 0; -+ -+ /* make chip goto reset mode */ -+ ret = ec_query_seq(CMD_INIT_RESET_MODE); -+ if (ret < 0) { -+ printk(KERN_ERR "ec init reset mode failed.\n"); -+ goto out; -+ } -+ -+ /* make the action take active */ -+ timeout = EC_CMD_TIMEOUT; -+ status = ec_read(REG_POWER_MODE) & FLAG_RESET_MODE; -+ while (timeout--) { -+ if (status) { -+ udelay(EC_REG_DELAY); -+ break; -+ } -+ status = ec_read(REG_POWER_MODE) & FLAG_RESET_MODE; -+ udelay(EC_REG_DELAY); -+ } -+ if (timeout <= 0) { -+ printk(KERN_ERR "ec rom fixup : can't check reset status.\n"); -+ ret = -EINVAL; -+ } else -+ printk(KERN_INFO "(%d/%d)reset 0xf710 : 0x%x\n", timeout, -+ EC_CMD_TIMEOUT - timeout, status); -+ -+ /* set MCU to reset mode */ -+ udelay(EC_REG_DELAY); -+ status = ec_read(REG_PXCFG); -+ status |= (1 << 0); -+ ec_write(REG_PXCFG, status); -+ udelay(EC_REG_DELAY); -+ -+ /* disable FWH/LPC */ -+ udelay(EC_REG_DELAY); -+ status = ec_read(REG_LPCCFG); -+ status &= ~(1 << 7); -+ ec_write(REG_LPCCFG, status); -+ udelay(EC_REG_DELAY); -+ -+ printk(KERN_INFO "entering reset mode ok..............\n"); -+ -+ out: -+ return ret; -+} -+ -+/* make ec exit from reset mode */ -+static void ec_exit_reset_mode(void) -+{ -+ unsigned char regval; -+ -+ udelay(EC_REG_DELAY); -+ regval = ec_read(REG_LPCCFG); -+ regval |= (1 << 7); -+ ec_write(REG_LPCCFG, regval); -+ regval = ec_read(REG_PXCFG); -+ regval &= ~(1 << 0); -+ ec_write(REG_PXCFG, regval); -+ printk(KERN_INFO "exit reset mode ok..................\n"); -+ -+ return; -+} -+ -+/* make ec disable WDD */ -+static void ec_disable_WDD(void) -+{ -+ unsigned char status; -+ -+ udelay(EC_REG_DELAY); -+ status = ec_read(REG_WDTCFG); -+ ec_write(REG_WDTPF, 0x03); -+ ec_write(REG_WDTCFG, (status & 0x80) | 0x48); -+ printk(KERN_INFO "Disable WDD ok..................\n"); -+ -+ return; -+} -+ -+/* make ec enable WDD */ -+static void ec_enable_WDD(void) -+{ -+ unsigned char status; -+ -+ udelay(EC_REG_DELAY); -+ status = ec_read(REG_WDTCFG); -+ ec_write(REG_WDT, 0x28); /* set WDT 5sec(0x28) */ -+ ec_write(REG_WDTCFG, (status & 0x80) | 0x03); -+ printk(KERN_INFO "Enable WDD ok..................\n"); -+ -+ return; -+} -+ -+/* make ec goto idle mode */ -+static int ec_init_idle_mode(void) -+{ -+ int timeout; -+ unsigned char status = 0; -+ int ret = 0; -+ -+ ec_query_seq(CMD_INIT_IDLE_MODE); -+ -+ /* make the action take active */ -+ timeout = EC_CMD_TIMEOUT; -+ status = ec_read(REG_POWER_MODE) & FLAG_IDLE_MODE; -+ while (timeout--) { -+ if (status) { -+ udelay(EC_REG_DELAY); -+ break; -+ } -+ status = ec_read(REG_POWER_MODE) & FLAG_IDLE_MODE; -+ udelay(EC_REG_DELAY); -+ } -+ if (timeout <= 0) { -+ printk(KERN_ERR "ec rom fixup : can't check out the status.\n"); -+ ret = -EINVAL; -+ } else -+ printk(KERN_INFO "(%d/%d)0xf710 : 0x%x\n", timeout, -+ EC_CMD_TIMEOUT - timeout, ec_read(REG_POWER_MODE)); -+ -+ printk(KERN_INFO "entering idle mode ok...................\n"); -+ -+ return ret; -+} -+ -+/* make ec exit from idle mode */ -+static int ec_exit_idle_mode(void) -+{ -+ -+ ec_query_seq(CMD_EXIT_IDLE_MODE); -+ -+ printk(KERN_INFO "exit idle mode ok...................\n"); -+ -+ return 0; -+} -+ -+static int ec_instruction_cycle(void) -+{ -+ unsigned long timeout; -+ int ret = 0; -+ -+ timeout = EC_FLASH_TIMEOUT; -+ while (timeout-- >= 0) { -+ if (!(ec_read(REG_XBISPICFG) & SPICFG_SPI_BUSY)) -+ break; -+ } -+ if (timeout <= 0) { -+ printk(KERN_ERR -+ "EC_INSTRUCTION_CYCLE : timeout for check flag.\n"); -+ ret = -EINVAL; -+ goto out; -+ } -+ -+ out: -+ return ret; -+} -+ -+/* To see if the ec is in busy state or not. */ -+static inline int ec_flash_busy(unsigned long timeout) -+{ -+ /* assurance the first command be going to rom */ -+ if (ec_instruction_cycle() < 0) -+ return EC_STATE_BUSY; -+#if 1 -+ timeout = timeout / EC_MAX_DELAY_UNIT; -+ while (timeout-- > 0) { -+ /* check the rom's status of busy flag */ -+ ec_write(REG_XBISPICMD, SPICMD_READ_STATUS); -+ if (ec_instruction_cycle() < 0) -+ return EC_STATE_BUSY; -+ if ((ec_read(REG_XBISPIDAT) & 0x01) == 0x00) -+ return EC_STATE_IDLE; -+ udelay(EC_MAX_DELAY_UNIT); -+ } -+ if (timeout <= 0) { -+ printk(KERN_ERR -+ "EC_FLASH_BUSY : timeout for check rom flag.\n"); -+ return EC_STATE_BUSY; -+ } -+#else -+ /* check the rom's status of busy flag */ -+ ec_write(REG_XBISPICMD, SPICMD_READ_STATUS); -+ if (ec_instruction_cycle() < 0) -+ return EC_STATE_BUSY; -+ -+ timeout = timeout / EC_MAX_DELAY_UNIT; -+ while (timeout-- > 0) { -+ if ((ec_read(REG_XBISPIDAT) & 0x01) == 0x00) -+ return EC_STATE_IDLE; -+ udelay(EC_MAX_DELAY_UNIT); -+ } -+ if (timeout <= 0) { -+ printk(KERN_ERR -+ "EC_FLASH_BUSY : timeout for check rom flag.\n"); -+ return EC_STATE_BUSY; -+ } -+#endif -+ -+ return EC_STATE_IDLE; -+} -+ -+static int rom_instruction_cycle(unsigned char cmd) -+{ -+ unsigned long timeout = 0; -+ -+ switch (cmd) { -+ case SPICMD_READ_STATUS: -+ case SPICMD_WRITE_ENABLE: -+ case SPICMD_WRITE_DISABLE: -+ case SPICMD_READ_BYTE: -+ case SPICMD_HIGH_SPEED_READ: -+ timeout = 0; -+ break; -+ case SPICMD_WRITE_STATUS: -+ timeout = 300 * 1000; -+ break; -+ case SPICMD_BYTE_PROGRAM: -+ timeout = 5 * 1000; -+ break; -+ case SPICMD_SST_SEC_ERASE: -+ case SPICMD_SEC_ERASE: -+ timeout = 1000 * 1000; -+ break; -+ case SPICMD_SST_BLK_ERASE: -+ case SPICMD_BLK_ERASE: -+ timeout = 3 * 1000 * 1000; -+ break; -+ case SPICMD_SST_CHIP_ERASE: -+ case SPICMD_CHIP_ERASE: -+ timeout = 20 * 1000 * 1000; -+ break; -+ default: -+ timeout = EC_SPICMD_STANDARD_TIMEOUT; -+ } -+ if (timeout == 0) -+ return ec_instruction_cycle(); -+ if (timeout < EC_SPICMD_STANDARD_TIMEOUT) -+ timeout = EC_SPICMD_STANDARD_TIMEOUT; -+ -+ return ec_flash_busy(timeout); -+} -+ -+/* delay for start/stop action */ -+static void delay_spi(int n) -+{ -+ while (n--) -+ inb(EC_IO_PORT_HIGH); -+} -+ -+/* start the action to spi rom function */ -+static void ec_start_spi(void) -+{ -+ unsigned char val; -+ -+ delay_spi(SPI_FINISH_WAIT_TIME); -+ val = ec_read(REG_XBISPICFG) | SPICFG_EN_SPICMD | SPICFG_AUTO_CHECK; -+ ec_write(REG_XBISPICFG, val); -+ delay_spi(SPI_FINISH_WAIT_TIME); -+} -+ -+/* stop the action to spi rom function */ -+static void ec_stop_spi(void) -+{ -+ unsigned char val; -+ -+ delay_spi(SPI_FINISH_WAIT_TIME); -+ val = -+ ec_read(REG_XBISPICFG) & (~(SPICFG_EN_SPICMD | SPICFG_AUTO_CHECK)); -+ ec_write(REG_XBISPICFG, val); -+ delay_spi(SPI_FINISH_WAIT_TIME); -+} -+ -+/* read one byte from xbi interface */ -+static int ec_read_byte(unsigned int addr, unsigned char *byte) -+{ -+ int ret = 0; -+ -+ /* enable spicmd writing. */ -+ ec_start_spi(); -+ -+ /* enable write spi flash */ -+ ec_write(REG_XBISPICMD, SPICMD_WRITE_ENABLE); -+ if (rom_instruction_cycle(SPICMD_WRITE_ENABLE) == EC_STATE_BUSY) { -+ printk(KERN_ERR "EC_READ_BYTE : SPICMD_WRITE_ENABLE failed.\n"); -+ ret = -EINVAL; -+ goto out; -+ } -+ -+ /* write the address */ -+ ec_write(REG_XBISPIA2, (addr & 0xff0000) >> 16); -+ ec_write(REG_XBISPIA1, (addr & 0x00ff00) >> 8); -+ ec_write(REG_XBISPIA0, (addr & 0x0000ff) >> 0); -+ /* start action */ -+ ec_write(REG_XBISPICMD, SPICMD_HIGH_SPEED_READ); -+ if (rom_instruction_cycle(SPICMD_HIGH_SPEED_READ) == EC_STATE_BUSY) { -+ printk(KERN_ERR -+ "EC_READ_BYTE : SPICMD_HIGH_SPEED_READ failed.\n"); -+ ret = -EINVAL; -+ goto out; -+ } -+ -+ *byte = ec_read(REG_XBISPIDAT); -+ -+ out: -+ /* disable spicmd writing. */ -+ ec_stop_spi(); -+ -+ return ret; -+} -+ -+/* write one byte to ec rom */ -+static int ec_write_byte(unsigned int addr, unsigned char byte) -+{ -+ int ret = 0; -+ -+ /* enable spicmd writing. */ -+ ec_start_spi(); -+ -+ /* enable write spi flash */ -+ ec_write(REG_XBISPICMD, SPICMD_WRITE_ENABLE); -+ if (rom_instruction_cycle(SPICMD_WRITE_ENABLE) == EC_STATE_BUSY) { -+ printk(KERN_ERR -+ "EC_WRITE_BYTE : SPICMD_WRITE_ENABLE failed.\n"); -+ ret = -EINVAL; -+ goto out; -+ } -+ -+ /* write the address */ -+ ec_write(REG_XBISPIA2, (addr & 0xff0000) >> 16); -+ ec_write(REG_XBISPIA1, (addr & 0x00ff00) >> 8); -+ ec_write(REG_XBISPIA0, (addr & 0x0000ff) >> 0); -+ ec_write(REG_XBISPIDAT, byte); -+ /* start action */ -+ ec_write(REG_XBISPICMD, SPICMD_BYTE_PROGRAM); -+ if (rom_instruction_cycle(SPICMD_BYTE_PROGRAM) == EC_STATE_BUSY) { -+ printk(KERN_ERR -+ "EC_WRITE_BYTE : SPICMD_BYTE_PROGRAM failed.\n"); -+ ret = -EINVAL; -+ goto out; -+ } -+ -+ out: -+ /* disable spicmd writing. */ -+ ec_stop_spi(); -+ -+ return ret; -+} -+ -+/* unprotect SPI ROM */ -+/* EC_ROM_unprotect function code */ -+static int EC_ROM_unprotect(void) -+{ -+ unsigned char status; -+ -+ /* enable write spi flash */ -+ ec_write(REG_XBISPICMD, SPICMD_WRITE_ENABLE); -+ if (rom_instruction_cycle(SPICMD_WRITE_ENABLE) == EC_STATE_BUSY) { -+ printk(KERN_ERR -+ "EC_UNIT_ERASE : SPICMD_WRITE_ENABLE failed.\n"); -+ return 1; -+ } -+ -+ /* unprotect the status register of rom */ -+ ec_write(REG_XBISPICMD, SPICMD_READ_STATUS); -+ if (rom_instruction_cycle(SPICMD_READ_STATUS) == EC_STATE_BUSY) { -+ printk(KERN_ERR "EC_UNIT_ERASE : SPICMD_READ_STATUS failed.\n"); -+ return 1; -+ } -+ status = ec_read(REG_XBISPIDAT); -+ ec_write(REG_XBISPIDAT, status & 0x02); -+ if (ec_instruction_cycle() < 0) { -+ printk(KERN_ERR "EC_UNIT_ERASE : write status value failed.\n"); -+ return 1; -+ } -+ -+ ec_write(REG_XBISPICMD, SPICMD_WRITE_STATUS); -+ if (rom_instruction_cycle(SPICMD_WRITE_STATUS) == EC_STATE_BUSY) { -+ printk(KERN_ERR -+ "EC_UNIT_ERASE : SPICMD_WRITE_STATUS failed.\n"); -+ return 1; -+ } -+ -+ /* enable write spi flash */ -+ ec_write(REG_XBISPICMD, SPICMD_WRITE_ENABLE); -+ if (rom_instruction_cycle(SPICMD_WRITE_ENABLE) == EC_STATE_BUSY) { -+ printk(KERN_ERR -+ "EC_UNIT_ERASE : SPICMD_WRITE_ENABLE failed.\n"); -+ return 1; -+ } -+ -+ return 0; -+} -+ -+/* erase one block or chip or sector as needed */ -+static int ec_unit_erase(unsigned char erase_cmd, unsigned int addr) -+{ -+ unsigned char status; -+ int ret = 0, i = 0; -+ int unprotect_count = 3; -+ int check_flag = 0; -+ -+ /* enable spicmd writing. */ -+ ec_start_spi(); -+ -+#ifdef EC_ROM_PROTECTION -+ /* added for re-check SPICMD_READ_STATUS */ -+ while (unprotect_count-- > 0) { -+ if (EC_ROM_unprotect()) { -+ ret = -EINVAL; -+ goto out; -+ } -+ -+ /* first time:500ms --> 5.5sec -->10.5sec */ -+ for (i = 0; i < ((2 - unprotect_count) * 100 + 10); i++) -+ udelay(50000); -+ ec_write(REG_XBISPICMD, SPICMD_READ_STATUS); -+ if (rom_instruction_cycle(SPICMD_READ_STATUS) -+ == EC_STATE_BUSY) { -+ printk(KERN_ERR -+ "EC_PROGRAM_ROM : SPICMD_READ_STATUS failed.\n"); -+ } else { -+ status = ec_read(REG_XBISPIDAT); -+ printk(KERN_INFO "Read unprotect status : 0x%x\n", -+ status); -+ if ((status & 0x1C) == 0x00) { -+ printk(KERN_INFO -+ "Read unprotect status OK1 : 0x%x\n", -+ status & 0x1C); -+ check_flag = 1; -+ break; -+ } -+ } -+ } -+ -+ if (!check_flag) { -+ printk(KERN_INFO "SPI ROM unprotect fail.\n"); -+ return 1; -+ } -+#endif -+ -+ /* block address fill */ -+ if (erase_cmd == SPICMD_BLK_ERASE) { -+ ec_write(REG_XBISPIA2, (addr & 0x00ff0000) >> 16); -+ ec_write(REG_XBISPIA1, (addr & 0x0000ff00) >> 8); -+ ec_write(REG_XBISPIA0, (addr & 0x000000ff) >> 0); -+ } -+ -+ /* erase the whole chip first */ -+ ec_write(REG_XBISPICMD, erase_cmd); -+ if (rom_instruction_cycle(erase_cmd) == EC_STATE_BUSY) { -+ printk(KERN_ERR "EC_UNIT_ERASE : erase failed.\n"); -+ ret = -EINVAL; -+ goto out; -+ } -+ -+ out: -+ /* disable spicmd writing. */ -+ ec_stop_spi(); -+ -+ return ret; -+} -+ -+/* update the whole rom content with H/W mode -+ * PLEASE USING ec_unit_erase() FIRSTLY -+ */ -+static int ec_program_rom(struct ec_info *info, int flag) -+{ -+ unsigned int addr = 0; -+ unsigned long size = 0; -+ unsigned char *ptr = NULL; -+ unsigned char data; -+ unsigned char val = 0; -+ int ret = 0; -+ int i, j; -+ unsigned char status; -+ -+ /* modify for program serial No. -+ * set IE_START_ADDR & use idle mode, -+ * disable WDD -+ */ -+ if (flag == PROGRAM_FLAG_ROM) { -+ ret = ec_init_reset_mode(); -+ addr = info->start_addr + EC_START_ADDR; -+ printk(KERN_INFO "PROGRAM_FLAG_ROM..............\n"); -+ } else if (flag == PROGRAM_FLAG_IE) { -+ ret = ec_init_idle_mode(); -+ ec_disable_WDD(); -+ addr = info->start_addr + IE_START_ADDR; -+ printk(KERN_INFO "PROGRAM_FLAG_IE..............\n"); -+ } else { -+ return 0; -+ } -+ -+ if (ret < 0) { -+ if (flag == PROGRAM_FLAG_IE) -+ ec_enable_WDD(); -+ return ret; -+ } -+ -+ size = info->size; -+ ptr = info->buf; -+ printk(KERN_INFO "starting update ec ROM..............\n"); -+ -+ ret = ec_unit_erase(SPICMD_BLK_ERASE, addr); -+ if (ret) { -+ printk(KERN_ERR "program ec : erase block failed.\n"); -+ goto out; -+ } -+ printk(KERN_ERR "program ec : erase block OK.\n"); -+ -+ i = 0; -+ while (i < size) { -+ data = *(ptr + i); -+ ec_write_byte(addr, data); -+ ec_read_byte(addr, &val); -+ if (val != data) { -+ ec_write_byte(addr, data); -+ ec_read_byte(addr, &val); -+ if (val != data) { -+ printk(KERN_INFO -+ "EC : Second flash program failed at:\t"); -+ printk(KERN_INFO -+ "addr : 0x%x, source : 0x%x, dest: 0x%x\n", -+ addr, data, val); -+ printk(KERN_INFO "This should not happen... STOP\n"); -+ break; -+ } -+ } -+ i++; -+ addr++; -+ } -+ -+#ifdef EC_ROM_PROTECTION -+ /* we should start spi access firstly */ -+ ec_start_spi(); -+ -+ /* enable write spi flash */ -+ ec_write(REG_XBISPICMD, SPICMD_WRITE_ENABLE); -+ if (rom_instruction_cycle(SPICMD_WRITE_ENABLE) == EC_STATE_BUSY) { -+ printk(KERN_ERR -+ "EC_PROGRAM_ROM : SPICMD_WRITE_ENABLE failed.\n"); -+ goto out1; -+ } -+ -+ /* protect the status register of rom */ -+ ec_write(REG_XBISPICMD, SPICMD_READ_STATUS); -+ if (rom_instruction_cycle(SPICMD_READ_STATUS) == EC_STATE_BUSY) { -+ printk(KERN_ERR -+ "EC_PROGRAM_ROM : SPICMD_READ_STATUS failed.\n"); -+ goto out1; -+ } -+ status = ec_read(REG_XBISPIDAT); -+ -+ ec_write(REG_XBISPIDAT, status | 0x1C); -+ if (ec_instruction_cycle() < 0) { -+ printk(KERN_ERR -+ "EC_PROGRAM_ROM : write status value failed.\n"); -+ goto out1; -+ } -+ -+ ec_write(REG_XBISPICMD, SPICMD_WRITE_STATUS); -+ if (rom_instruction_cycle(SPICMD_WRITE_STATUS) == EC_STATE_BUSY) { -+ printk(KERN_ERR -+ "EC_PROGRAM_ROM : SPICMD_WRITE_STATUS failed.\n"); -+ goto out1; -+ } -+#endif -+ -+ /* disable the write action to spi rom */ -+ ec_write(REG_XBISPICMD, SPICMD_WRITE_DISABLE); -+ if (rom_instruction_cycle(SPICMD_WRITE_DISABLE) == EC_STATE_BUSY) { -+ printk(KERN_ERR -+ "EC_PROGRAM_ROM : SPICMD_WRITE_DISABLE failed.\n"); -+ goto out1; -+ } -+ -+ out1: -+ /* we should stop spi access firstly */ -+ ec_stop_spi(); -+ out: -+ /* for security */ -+ for (j = 0; j < 2000; j++) -+ udelay(1000); -+ -+ /* modify for program serial No. -+ * after program No exit idle mode -+ * and enable WDD -+ */ -+ if (flag == PROGRAM_FLAG_ROM) { -+ /* exit from the reset mode */ -+ ec_exit_reset_mode(); -+ } else { -+ /* ec exit from idle mode */ -+ ret = ec_exit_idle_mode(); -+ ec_enable_WDD(); -+ if (ret < 0) -+ return ret; -+ } -+ -+ return 0; -+} -+ -+/* ioctl */ -+static int misc_ioctl(struct inode *inode, struct file *filp, u_int cmd, -+ u_long arg) -+{ -+ struct ec_info ecinfo; -+ void __user *ptr = (void __user *)arg; -+ struct ec_reg *ecreg = (struct ec_reg *)(filp->private_data); -+ int ret = 0; -+ -+ switch (cmd) { -+ case IOCTL_RDREG: -+ ret = copy_from_user(ecreg, ptr, sizeof(struct ec_reg)); -+ if (ret) { -+ printk(KERN_ERR "reg read : copy from user error.\n"); -+ return -EFAULT; -+ } -+ if ((ecreg->addr > EC_MAX_REGADDR) -+ || (ecreg->addr < EC_MIN_REGADDR)) { -+ printk(KERN_ERR -+ "reg read : out of register address range.\n"); -+ return -EINVAL; -+ } -+ ecreg->val = ec_read(ecreg->addr); -+ ret = copy_to_user(ptr, ecreg, sizeof(struct ec_reg)); -+ if (ret) { -+ printk(KERN_ERR "reg read : copy to user error.\n"); -+ return -EFAULT; -+ } -+ break; -+ case IOCTL_WRREG: -+ ret = copy_from_user(ecreg, ptr, sizeof(struct ec_reg)); -+ if (ret) { -+ printk(KERN_ERR "reg write : copy from user error.\n"); -+ return -EFAULT; -+ } -+ if ((ecreg->addr > EC_MAX_REGADDR) -+ || (ecreg->addr < EC_MIN_REGADDR)) { -+ printk(KERN_ERR -+ "reg write : out of register address range.\n"); -+ return -EINVAL; -+ } -+ ec_write(ecreg->addr, ecreg->val); -+ break; -+ case IOCTL_READ_EC: -+ ret = copy_from_user(ecreg, ptr, sizeof(struct ec_reg)); -+ if (ret) { -+ printk(KERN_ERR "spi read : copy from user error.\n"); -+ return -EFAULT; -+ } -+ if ((ecreg->addr > EC_RAM_ADDR) -+ && (ecreg->addr < EC_MAX_REGADDR)) { -+ printk(KERN_ERR -+ "spi read : out of register address range.\n"); -+ return -EINVAL; -+ } -+ ec_read_byte(ecreg->addr, &(ecreg->val)); -+ ret = copy_to_user(ptr, ecreg, sizeof(struct ec_reg)); -+ if (ret) { -+ printk(KERN_ERR "spi read : copy to user error.\n"); -+ return -EFAULT; -+ } -+ break; -+ case IOCTL_PROGRAM_IE: -+ ecinfo.start_addr = EC_START_ADDR; -+ ecinfo.size = EC_CONTENT_MAX_SIZE; -+ ecinfo.buf = (u8 *) kmalloc(ecinfo.size, GFP_KERNEL); -+ if (ecinfo.buf == NULL) { -+ printk(KERN_ERR "program ie : kmalloc failed.\n"); -+ return -ENOMEM; -+ } -+ ret = copy_from_user(ecinfo.buf, (u8 *) ptr, ecinfo.size); -+ if (ret) { -+ printk(KERN_ERR "program ie : copy from user error.\n"); -+ kfree(ecinfo.buf); -+ ecinfo.buf = NULL; -+ return -EFAULT; -+ } -+ -+ /* use ec_program_rom to write serial No */ -+ ec_program_rom(&ecinfo, PROGRAM_FLAG_IE); -+ -+ kfree(ecinfo.buf); -+ ecinfo.buf = NULL; -+ break; -+ case IOCTL_PROGRAM_EC: -+ ecinfo.start_addr = EC_START_ADDR; -+ if (get_user((ecinfo.size), (u32 *) ptr)) { -+ printk(KERN_ERR "program ec : get user error.\n"); -+ return -EFAULT; -+ } -+ if ((ecinfo.size) > EC_CONTENT_MAX_SIZE) { -+ printk(KERN_ERR "program ec : size out of limited.\n"); -+ return -EINVAL; -+ } -+ ecinfo.buf = (u8 *) kmalloc(ecinfo.size, GFP_KERNEL); -+ if (ecinfo.buf == NULL) { -+ printk(KERN_ERR "program ec : kmalloc failed.\n"); -+ return -ENOMEM; -+ } -+ ret = copy_from_user(ecinfo.buf, ((u8 *) ptr + 4), ecinfo.size); -+ if (ret) { -+ printk(KERN_ERR "program ec : copy from user error.\n"); -+ kfree(ecinfo.buf); -+ ecinfo.buf = NULL; -+ return -EFAULT; -+ } -+ -+ ec_program_rom(&ecinfo, PROGRAM_FLAG_ROM); -+ -+ kfree(ecinfo.buf); -+ ecinfo.buf = NULL; -+ break; -+ -+ default: -+ break; -+ } -+ -+ return 0; -+} -+ -+static long misc_compat_ioctl(struct file *file, unsigned int cmd, -+ unsigned long arg) -+{ -+ return misc_ioctl(file->f_dentry->d_inode, file, cmd, arg); -+} -+ -+static int misc_open(struct inode *inode, struct file *filp) -+{ -+ struct ec_reg *ecreg = NULL; -+ ecreg = kmalloc(sizeof(struct ec_reg), GFP_KERNEL); -+ if (ecreg) -+ filp->private_data = ecreg; -+ -+ return ecreg ? 0 : -ENOMEM; -+} -+ -+static int misc_release(struct inode *inode, struct file *filp) -+{ -+ struct ec_reg *ecreg = (struct ec_reg *)(filp->private_data); -+ -+ filp->private_data = NULL; -+ kfree(ecreg); -+ -+ return 0; -+} -+ -+static const struct file_operations ecmisc_fops = { -+ .open = misc_open, -+ .release = misc_release, -+ .read = NULL, -+ .write = NULL, -+#ifdef CONFIG_64BIT -+ .compat_ioctl = misc_compat_ioctl, -+#else -+ .ioctl = misc_ioctl, -+#endif -+}; -+ -+static struct miscdevice ecmisc_device = { -+ .minor = MISC_DYNAMIC_MINOR, -+ .name = EC_MISC_DEV, -+ .fops = &ecmisc_fops -+}; -+ -+static int __init ecmisc_init(void) -+{ -+ int ret; -+ -+ printk(KERN_INFO "EC misc device init.\n"); -+ ret = misc_register(&ecmisc_device); -+ -+ return ret; -+} -+ -+static void __exit ecmisc_exit(void) -+{ -+ printk(KERN_INFO "EC misc device exit.\n"); -+ misc_deregister(&ecmisc_device); -+} -+ -+module_init(ecmisc_init); -+module_exit(ecmisc_exit); -+ -+MODULE_AUTHOR("liujl "); -+MODULE_DESCRIPTION("Driver for flushing/dumping ROM of EC on YeeLoong laptop"); -+MODULE_LICENSE("GPL"); -diff -Nur linux-2.6.37.orig/drivers/platform/mips/yeeloong_laptop.c linux-2.6.37/drivers/platform/mips/yeeloong_laptop.c ---- linux-2.6.37.orig/drivers/platform/mips/yeeloong_laptop.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.37/drivers/platform/mips/yeeloong_laptop.c 2011-01-11 20:44:43.000000000 +0100 -@@ -0,0 +1,1200 @@ -+/* -+ * Driver for YeeLoong laptop extras -+ * -+ * Copyright (C) 2009 Lemote Inc. -+ * Author: Wu Zhangjin , Liu Junliang -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include /* for backlight subdriver */ -+#include -+#include /* for hwmon subdriver */ -+#include -+#include /* for video output subdriver */ -+#include /* for hotkey subdriver */ -+#include -+#include -+#include -+#include /* for AC & Battery subdriver */ -+ -+#include -+ -+#include /* for loongson_cmdline */ -+#include -+ -+/* common function */ -+#define EC_VER_LEN 64 -+ -+static int ec_version_before(char *version) -+{ -+ char *p, ec_ver[EC_VER_LEN]; -+ -+ p = strstr(loongson_cmdline, "EC_VER="); -+ if (!p) -+ memset(ec_ver, 0, EC_VER_LEN); -+ else { -+ strncpy(ec_ver, p, EC_VER_LEN); -+ p = strstr(ec_ver, " "); -+ if (p) -+ *p = '\0'; -+ } -+ -+ return (strncasecmp(ec_ver, version, 64) < 0); -+} -+ -+/* backlight subdriver */ -+#define MAX_BRIGHTNESS 8 -+ -+static int yeeloong_set_brightness(struct backlight_device *bd) -+{ -+ unsigned int level, current_level; -+ static unsigned int old_level; -+ -+ level = (bd->props.fb_blank == FB_BLANK_UNBLANK && -+ bd->props.power == FB_BLANK_UNBLANK) ? -+ bd->props.brightness : 0; -+ -+ level = SENSORS_LIMIT(level, 0, MAX_BRIGHTNESS); -+ -+ /* Avoid to modify the brightness when EC is tuning it */ -+ if (old_level != level) { -+ current_level = ec_read(REG_DISPLAY_BRIGHTNESS); -+ if (old_level == current_level) -+ ec_write(REG_DISPLAY_BRIGHTNESS, level); -+ old_level = level; -+ } -+ -+ return 0; -+} -+ -+static int yeeloong_get_brightness(struct backlight_device *bd) -+{ -+ return ec_read(REG_DISPLAY_BRIGHTNESS); -+} -+ -+static struct backlight_ops backlight_ops = { -+ .get_brightness = yeeloong_get_brightness, -+ .update_status = yeeloong_set_brightness, -+}; -+ -+static struct backlight_device *yeeloong_backlight_dev; -+ -+static int yeeloong_backlight_init(void) -+{ -+ int ret; -+ struct backlight_properties props; -+ -+ memset(&props, 0, sizeof(struct backlight_properties)); -+ props.max_brightness = MAX_BRIGHTNESS; -+ yeeloong_backlight_dev = backlight_device_register("backlight0", NULL, -+ NULL, &backlight_ops, &props); -+ -+ if (IS_ERR(yeeloong_backlight_dev)) { -+ ret = PTR_ERR(yeeloong_backlight_dev); -+ yeeloong_backlight_dev = NULL; -+ return ret; -+ } -+ -+ yeeloong_backlight_dev->props.brightness = -+ yeeloong_get_brightness(yeeloong_backlight_dev); -+ backlight_update_status(yeeloong_backlight_dev); -+ -+ return 0; -+} -+ -+static void yeeloong_backlight_exit(void) -+{ -+ if (yeeloong_backlight_dev) { -+ backlight_device_unregister(yeeloong_backlight_dev); -+ yeeloong_backlight_dev = NULL; -+ } -+} -+ -+/* AC & Battery subdriver */ -+ -+static struct power_supply yeeloong_ac, yeeloong_bat; -+ -+#define AC_OFFLINE 0 -+#define AC_ONLINE 1 -+ -+static int yeeloong_get_ac_props(struct power_supply *psy, -+ enum power_supply_property psp, -+ union power_supply_propval *val) -+{ -+ switch (psp) { -+ case POWER_SUPPLY_PROP_ONLINE: -+ val->intval = ((ec_read(REG_BAT_POWER)) & BIT_BAT_POWER_ACIN) ? -+ AC_ONLINE : AC_OFFLINE; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+static enum power_supply_property yeeloong_ac_props[] = { -+ POWER_SUPPLY_PROP_ONLINE, -+}; -+ -+static struct power_supply yeeloong_ac = { -+ .name = "yeeloong-ac", -+ .type = POWER_SUPPLY_TYPE_MAINS, -+ .properties = yeeloong_ac_props, -+ .num_properties = ARRAY_SIZE(yeeloong_ac_props), -+ .get_property = yeeloong_get_ac_props, -+}; -+ -+#define BAT_CAP_CRITICAL 5 -+#define BAT_CAP_HIGH 99 -+ -+#define get_bat_info(type) \ -+ ((ec_read(REG_BAT_##type##_HIGH) << 8) | \ -+ (ec_read(REG_BAT_##type##_LOW))) -+ -+static int yeeloong_bat_get_ex_property(enum power_supply_property psp, -+ union power_supply_propval *val) -+{ -+ int bat_in, curr_cap, cap_level, status, charge, health; -+ -+ status = ec_read(REG_BAT_STATUS); -+ bat_in = status & BIT_BAT_STATUS_IN; -+ curr_cap = get_bat_info(RELATIVE_CAP); -+ if (status & BIT_BAT_STATUS_FULL) -+ curr_cap = 100; -+ -+ switch (psp) { -+ case POWER_SUPPLY_PROP_PRESENT: -+ val->intval = bat_in; -+ break; -+ case POWER_SUPPLY_PROP_CAPACITY: -+ val->intval = curr_cap; -+ break; -+ case POWER_SUPPLY_PROP_CAPACITY_LEVEL: -+ cap_level = POWER_SUPPLY_CAPACITY_LEVEL_NORMAL; -+ if (status & BIT_BAT_STATUS_LOW) { -+ cap_level = POWER_SUPPLY_CAPACITY_LEVEL_LOW; -+ if (curr_cap <= BAT_CAP_CRITICAL) -+ cap_level = -+ POWER_SUPPLY_CAPACITY_LEVEL_CRITICAL; -+ } else if (status & BIT_BAT_STATUS_FULL) { -+ cap_level = POWER_SUPPLY_CAPACITY_LEVEL_FULL; -+ if (curr_cap >= BAT_CAP_HIGH) -+ cap_level = POWER_SUPPLY_CAPACITY_LEVEL_HIGH; -+ } else if (status & BIT_BAT_STATUS_DESTROY) -+ cap_level = POWER_SUPPLY_CAPACITY_LEVEL_UNKNOWN; -+ val->intval = cap_level; -+ break; -+ case POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW: -+ /* seconds */ -+ val->intval = bat_in ? (curr_cap - 3) * 54 + 142 : 0; -+ break; -+ case POWER_SUPPLY_PROP_STATUS: -+ if (!bat_in) -+ charge = POWER_SUPPLY_STATUS_UNKNOWN; -+ else { -+ if (status & BIT_BAT_STATUS_FULL) { -+ val->intval = POWER_SUPPLY_STATUS_FULL; -+ break; -+ } -+ -+ charge = ec_read(REG_BAT_CHARGE); -+ if (charge & FLAG_BAT_CHARGE_DISCHARGE) -+ charge = POWER_SUPPLY_STATUS_DISCHARGING; -+ else if (charge & FLAG_BAT_CHARGE_CHARGE) -+ charge = POWER_SUPPLY_STATUS_CHARGING; -+ else -+ charge = POWER_SUPPLY_STATUS_NOT_CHARGING; -+ } -+ val->intval = charge; -+ break; -+ case POWER_SUPPLY_PROP_HEALTH: -+ if (!bat_in) /* no battery present */ -+ health = POWER_SUPPLY_HEALTH_UNKNOWN; -+ else { /* Assume it is good */ -+ health = POWER_SUPPLY_HEALTH_GOOD; -+ if (status & -+ (BIT_BAT_STATUS_DESTROY | BIT_BAT_STATUS_LOW)) -+ health = POWER_SUPPLY_HEALTH_DEAD; -+ if (ec_read(REG_BAT_CHARGE_STATUS) & -+ BIT_BAT_CHARGE_STATUS_OVERTEMP) -+ health = POWER_SUPPLY_HEALTH_OVERHEAT; -+ } -+ val->intval = health; -+ break; -+ case POWER_SUPPLY_PROP_CHARGE_NOW: /* 1/100(%)*1000 µAh */ -+ val->intval = curr_cap * get_bat_info(FULLCHG_CAP) * 10; -+ break; -+ default: -+ return -EINVAL; -+ } -+ return 0; -+} -+ -+static int get_battery_temp(void) -+{ -+ int value; -+ -+ value = get_bat_info(TEMPERATURE); -+ -+ return value * 1000; -+} -+ -+static int get_battery_current(void) -+{ -+ s16 value; -+ -+ value = get_bat_info(CURRENT); -+ -+ return -value; -+} -+ -+static int get_battery_voltage(void) -+{ -+ int value; -+ -+ value = get_bat_info(VOLTAGE); -+ -+ return value; -+} -+ -+static int yeeloong_get_bat_props(struct power_supply *psy, -+ enum power_supply_property psp, -+ union power_supply_propval *val) -+{ -+ switch (psp) { -+ /* Fixed information */ -+ case POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN: -+ val->intval = get_bat_info(DESIGN_VOL) * 1000; /* mV -> µV */ -+ break; -+ case POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN: -+ val->intval = get_bat_info(DESIGN_CAP) * 1000; /* mAh->µAh */ -+ break; -+ case POWER_SUPPLY_PROP_CHARGE_FULL: -+ val->intval = get_bat_info(FULLCHG_CAP) * 1000; /* µAh */ -+ break; -+ case POWER_SUPPLY_PROP_MANUFACTURER: -+ val->strval = (ec_read(REG_BAT_VENDOR) == -+ FLAG_BAT_VENDOR_SANYO) ? "SANYO" : "SIMPLO"; -+ break; -+ /* Dynamic information */ -+ case POWER_SUPPLY_PROP_CURRENT_NOW: -+ val->intval = get_battery_current() * 1000; /* mA -> µA */ -+ break; -+ case POWER_SUPPLY_PROP_VOLTAGE_NOW: -+ val->intval = get_battery_voltage() * 1000; /* mV -> µV */ -+ break; -+ case POWER_SUPPLY_PROP_TEMP: -+ val->intval = get_battery_temp(); /* Celcius */ -+ break; -+ /* Dynamic but related information */ -+ default: -+ return yeeloong_bat_get_ex_property(psp, val); -+ } -+ -+ return 0; -+} -+ -+static enum power_supply_property yeeloong_bat_props[] = { -+ POWER_SUPPLY_PROP_STATUS, -+ POWER_SUPPLY_PROP_PRESENT, -+ POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN, -+ POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN, -+ POWER_SUPPLY_PROP_CHARGE_FULL, -+ POWER_SUPPLY_PROP_CHARGE_NOW, -+ POWER_SUPPLY_PROP_CURRENT_NOW, -+ POWER_SUPPLY_PROP_VOLTAGE_NOW, -+ POWER_SUPPLY_PROP_HEALTH, -+ POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW, -+ POWER_SUPPLY_PROP_CAPACITY, -+ POWER_SUPPLY_PROP_CAPACITY_LEVEL, -+ POWER_SUPPLY_PROP_TEMP, -+ POWER_SUPPLY_PROP_MANUFACTURER, -+}; -+ -+static struct power_supply yeeloong_bat = { -+ .name = "yeeloong-bat", -+ .type = POWER_SUPPLY_TYPE_BATTERY, -+ .properties = yeeloong_bat_props, -+ .num_properties = ARRAY_SIZE(yeeloong_bat_props), -+ .get_property = yeeloong_get_bat_props, -+}; -+ -+static int ac_bat_initialized; -+ -+static int yeeloong_bat_init(void) -+{ -+ int ret; -+ -+ ret = power_supply_register(NULL, &yeeloong_ac); -+ if (ret) -+ return ret; -+ ret = power_supply_register(NULL, &yeeloong_bat); -+ if (ret) { -+ power_supply_unregister(&yeeloong_ac); -+ return ret; -+ } -+ ac_bat_initialized = 1; -+ -+ return 0; -+} -+ -+static void yeeloong_bat_exit(void) -+{ -+ ac_bat_initialized = 0; -+ -+ power_supply_unregister(&yeeloong_ac); -+ power_supply_unregister(&yeeloong_bat); -+} -+/* hwmon subdriver */ -+ -+#define MIN_FAN_SPEED 0 -+#define MAX_FAN_SPEED 3 -+ -+static int get_fan_pwm_enable(void) -+{ -+ int level, mode; -+ -+ level = ec_read(REG_FAN_SPEED_LEVEL); -+ mode = ec_read(REG_FAN_AUTO_MAN_SWITCH); -+ -+ if (level == MAX_FAN_SPEED && mode == BIT_FAN_MANUAL) -+ mode = 0; -+ else if (mode == BIT_FAN_MANUAL) -+ mode = 1; -+ else -+ mode = 2; -+ -+ return mode; -+} -+ -+static void set_fan_pwm_enable(int mode) -+{ -+ switch (mode) { -+ case 0: -+ /* fullspeed */ -+ ec_write(REG_FAN_AUTO_MAN_SWITCH, BIT_FAN_MANUAL); -+ ec_write(REG_FAN_SPEED_LEVEL, MAX_FAN_SPEED); -+ break; -+ case 1: -+ ec_write(REG_FAN_AUTO_MAN_SWITCH, BIT_FAN_MANUAL); -+ break; -+ case 2: -+ ec_write(REG_FAN_AUTO_MAN_SWITCH, BIT_FAN_AUTO); -+ break; -+ default: -+ break; -+ } -+} -+ -+static int get_fan_pwm(void) -+{ -+ return ec_read(REG_FAN_SPEED_LEVEL); -+} -+ -+static void set_fan_pwm(int value) -+{ -+ int mode; -+ -+ mode = ec_read(REG_FAN_AUTO_MAN_SWITCH); -+ if (mode != BIT_FAN_MANUAL) -+ return; -+ -+ value = SENSORS_LIMIT(value, 0, 3); -+ -+ /* We must ensure the fan is on */ -+ if (value > 0) -+ ec_write(REG_FAN_CONTROL, BIT_FAN_CONTROL_ON); -+ -+ ec_write(REG_FAN_SPEED_LEVEL, value); -+} -+ -+static int get_fan_rpm(void) -+{ -+ int value; -+ -+ value = FAN_SPEED_DIVIDER / -+ (((ec_read(REG_FAN_SPEED_HIGH) & 0x0f) << 8) | -+ ec_read(REG_FAN_SPEED_LOW)); -+ -+ return value; -+} -+ -+static int get_cpu_temp(void) -+{ -+ s8 value; -+ -+ value = ec_read(REG_TEMPERATURE_VALUE); -+ -+ return value * 1000; -+} -+ -+static int get_cpu_temp_max(void) -+{ -+ return 60 * 1000; -+} -+ -+static int get_battery_temp_alarm(void) -+{ -+ int status; -+ -+ status = (ec_read(REG_BAT_CHARGE_STATUS) & -+ BIT_BAT_CHARGE_STATUS_OVERTEMP); -+ -+ return !!status; -+} -+ -+static ssize_t store_sys_hwmon(void (*set) (int), const char *buf, size_t count) -+{ -+ int ret; -+ unsigned long value; -+ -+ if (!count) -+ return 0; -+ -+ ret = strict_strtoul(buf, 10, &value); -+ if (ret) -+ return ret; -+ -+ set(value); -+ -+ return count; -+} -+ -+static ssize_t show_sys_hwmon(int (*get) (void), char *buf) -+{ -+ return sprintf(buf, "%d\n", get()); -+} -+ -+#define CREATE_SENSOR_ATTR(_name, _mode, _set, _get) \ -+ static ssize_t show_##_name(struct device *dev, \ -+ struct device_attribute *attr, \ -+ char *buf) \ -+ { \ -+ return show_sys_hwmon(_set, buf); \ -+ } \ -+ static ssize_t store_##_name(struct device *dev, \ -+ struct device_attribute *attr, \ -+ const char *buf, size_t count) \ -+ { \ -+ return store_sys_hwmon(_get, buf, count); \ -+ } \ -+ static SENSOR_DEVICE_ATTR(_name, _mode, show_##_name, store_##_name, 0); -+ -+CREATE_SENSOR_ATTR(fan1_input, S_IRUGO, get_fan_rpm, NULL); -+CREATE_SENSOR_ATTR(pwm1, S_IRUGO | S_IWUSR, get_fan_pwm, set_fan_pwm); -+CREATE_SENSOR_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, get_fan_pwm_enable, -+ set_fan_pwm_enable); -+CREATE_SENSOR_ATTR(temp1_input, S_IRUGO, get_cpu_temp, NULL); -+CREATE_SENSOR_ATTR(temp1_max, S_IRUGO, get_cpu_temp_max, NULL); -+CREATE_SENSOR_ATTR(temp2_input, S_IRUGO, get_battery_temp, NULL); -+CREATE_SENSOR_ATTR(temp2_max_alarm, S_IRUGO, get_battery_temp_alarm, NULL); -+CREATE_SENSOR_ATTR(curr1_input, S_IRUGO, get_battery_current, NULL); -+CREATE_SENSOR_ATTR(in1_input, S_IRUGO, get_battery_voltage, NULL); -+ -+static ssize_t -+show_name(struct device *dev, struct device_attribute *attr, char *buf) -+{ -+ return sprintf(buf, "yeeloong\n"); -+} -+ -+static SENSOR_DEVICE_ATTR(name, S_IRUGO, show_name, NULL, 0); -+ -+static struct attribute *hwmon_attributes[] = { -+ &sensor_dev_attr_pwm1.dev_attr.attr, -+ &sensor_dev_attr_pwm1_enable.dev_attr.attr, -+ &sensor_dev_attr_fan1_input.dev_attr.attr, -+ &sensor_dev_attr_temp1_input.dev_attr.attr, -+ &sensor_dev_attr_temp1_max.dev_attr.attr, -+ &sensor_dev_attr_temp2_input.dev_attr.attr, -+ &sensor_dev_attr_temp2_max_alarm.dev_attr.attr, -+ &sensor_dev_attr_curr1_input.dev_attr.attr, -+ &sensor_dev_attr_in1_input.dev_attr.attr, -+ &sensor_dev_attr_name.dev_attr.attr, -+ NULL -+}; -+ -+static struct attribute_group hwmon_attribute_group = { -+ .attrs = hwmon_attributes -+}; -+ -+static struct device *yeeloong_hwmon_dev; -+ -+static int yeeloong_hwmon_init(void) -+{ -+ int ret; -+ -+ yeeloong_hwmon_dev = hwmon_device_register(NULL); -+ if (IS_ERR(yeeloong_hwmon_dev)) { -+ pr_err("Fail to register yeeloong hwmon device\n"); -+ yeeloong_hwmon_dev = NULL; -+ return PTR_ERR(yeeloong_hwmon_dev); -+ } -+ ret = sysfs_create_group(&yeeloong_hwmon_dev->kobj, -+ &hwmon_attribute_group); -+ if (ret) { -+ hwmon_device_unregister(yeeloong_hwmon_dev); -+ yeeloong_hwmon_dev = NULL; -+ return ret; -+ } -+ /* ensure fan is set to auto mode */ -+ set_fan_pwm_enable(2); -+ -+ return 0; -+} -+ -+static void yeeloong_hwmon_exit(void) -+{ -+ if (yeeloong_hwmon_dev) { -+ sysfs_remove_group(&yeeloong_hwmon_dev->kobj, -+ &hwmon_attribute_group); -+ hwmon_device_unregister(yeeloong_hwmon_dev); -+ yeeloong_hwmon_dev = NULL; -+ } -+} -+ -+/* video output subdriver */ -+ -+static int lcd_video_output_get(struct output_device *od) -+{ -+ return ec_read(REG_DISPLAY_LCD); -+} -+ -+#define LCD 0 -+#define CRT 1 -+ -+static void display_vo_set(int display, int on) -+{ -+ int addr; -+ unsigned long value; -+ -+ addr = (display == LCD) ? 0x31 : 0x21; -+ -+ outb(addr, 0x3c4); -+ value = inb(0x3c5); -+ -+ if (display == LCD) -+ value |= (on ? 0x03 : 0x02); -+ else { -+ if (on) -+ clear_bit(7, &value); -+ else -+ set_bit(7, &value); -+ } -+ -+ outb(addr, 0x3c4); -+ outb(value, 0x3c5); -+} -+ -+static int lcd_video_output_set(struct output_device *od) -+{ -+ unsigned long status; -+ -+ status = !!od->request_state; -+ -+ display_vo_set(LCD, status); -+ ec_write(REG_BACKLIGHT_CTRL, status); -+ -+ return 0; -+} -+ -+static struct output_properties lcd_output_properties = { -+ .set_state = lcd_video_output_set, -+ .get_status = lcd_video_output_get, -+}; -+ -+static int crt_video_output_get(struct output_device *od) -+{ -+ return ec_read(REG_CRT_DETECT); -+} -+ -+static int crt_video_output_set(struct output_device *od) -+{ -+ unsigned long status; -+ -+ status = !!od->request_state; -+ -+ if (ec_read(REG_CRT_DETECT) == BIT_CRT_DETECT_PLUG) -+ display_vo_set(CRT, status); -+ -+ return 0; -+} -+ -+static struct output_properties crt_output_properties = { -+ .set_state = crt_video_output_set, -+ .get_status = crt_video_output_get, -+}; -+ -+static struct output_device *lcd_output_dev, *crt_output_dev; -+ -+static void yeeloong_lcd_vo_set(int status) -+{ -+ lcd_output_dev->request_state = status; -+ lcd_video_output_set(lcd_output_dev); -+} -+ -+static void yeeloong_crt_vo_set(int status) -+{ -+ crt_output_dev->request_state = status; -+ crt_video_output_set(crt_output_dev); -+} -+ -+static int yeeloong_vo_init(void) -+{ -+ int ret; -+ -+ /* Register video output device: lcd, crt */ -+ lcd_output_dev = video_output_register("LCD", NULL, NULL, -+ &lcd_output_properties); -+ -+ if (IS_ERR(lcd_output_dev)) { -+ ret = PTR_ERR(lcd_output_dev); -+ lcd_output_dev = NULL; -+ return ret; -+ } -+ /* Ensure LCD is on by default */ -+ yeeloong_lcd_vo_set(BIT_DISPLAY_LCD_ON); -+ -+ crt_output_dev = video_output_register("CRT", NULL, NULL, -+ &crt_output_properties); -+ -+ if (IS_ERR(crt_output_dev)) { -+ ret = PTR_ERR(crt_output_dev); -+ crt_output_dev = NULL; -+ return ret; -+ } -+ -+ /* Turn off CRT by default, and will be enabled when the CRT -+ * connectting event reported by SCI */ -+ yeeloong_crt_vo_set(BIT_CRT_DETECT_UNPLUG); -+ -+ return 0; -+} -+ -+static void yeeloong_vo_exit(void) -+{ -+ if (lcd_output_dev) { -+ video_output_unregister(lcd_output_dev); -+ lcd_output_dev = NULL; -+ } -+ if (crt_output_dev) { -+ video_output_unregister(crt_output_dev); -+ crt_output_dev = NULL; -+ } -+} -+ -+/* hotkey subdriver */ -+ -+static struct input_dev *yeeloong_hotkey_dev; -+ -+static const struct key_entry yeeloong_keymap[] = { -+ {KE_SW, EVENT_LID, { SW_LID } }, -+ {KE_KEY, EVENT_CAMERA, { KEY_CAMERA } }, /* Fn + ESC */ -+ {KE_KEY, EVENT_SLEEP, { KEY_SLEEP } }, /* Fn + F1 */ -+ {KE_KEY, EVENT_DISPLAYTOGGLE, { KEY_DISPLAYTOGGLE } }, /* Fn + F2 */ -+ {KE_KEY, EVENT_SWITCHVIDEOMODE, { KEY_SWITCHVIDEOMODE } }, /* Fn + F3 */ -+ {KE_KEY, EVENT_AUDIO_MUTE, { KEY_MUTE } }, /* Fn + F4 */ -+ {KE_KEY, EVENT_WLAN, { KEY_WLAN } }, /* Fn + F5 */ -+ {KE_KEY, EVENT_DISPLAY_BRIGHTNESS, { KEY_BRIGHTNESSUP } }, /* Fn + up */ -+ {KE_KEY, EVENT_DISPLAY_BRIGHTNESS, { KEY_BRIGHTNESSDOWN } }, /* Fn + down */ -+ {KE_KEY, EVENT_AUDIO_VOLUME, { KEY_VOLUMEUP } }, /* Fn + right */ -+ {KE_KEY, EVENT_AUDIO_VOLUME, { KEY_VOLUMEDOWN } }, /* Fn + left */ -+ {KE_END, 0} -+}; -+ -+static struct key_entry *get_event_key_entry(int event, int status) -+{ -+ struct key_entry *ke; -+ static int old_brightness_status = -1; -+ static int old_volume_status = -1; -+ -+ ke = sparse_keymap_entry_from_scancode(yeeloong_hotkey_dev, event); -+ if (!ke) -+ return NULL; -+ -+ switch (event) { -+ case EVENT_DISPLAY_BRIGHTNESS: -+ /* current status > old one, means up */ -+ if ((status < old_brightness_status) || (0 == status)) -+ ke++; -+ old_brightness_status = status; -+ break; -+ case EVENT_AUDIO_VOLUME: -+ if ((status < old_volume_status) || (0 == status)) -+ ke++; -+ old_volume_status = status; -+ break; -+ default: -+ break; -+ } -+ -+ return ke; -+} -+ -+static int report_lid_switch(int status) -+{ -+ input_report_switch(yeeloong_hotkey_dev, SW_LID, !status); -+ input_sync(yeeloong_hotkey_dev); -+ -+ return status; -+} -+ -+static int crt_detect_handler(int status) -+{ -+ if (status) { -+ yeeloong_crt_vo_set(BIT_CRT_DETECT_PLUG); -+ yeeloong_lcd_vo_set(BIT_DISPLAY_LCD_OFF); -+ } else { -+ yeeloong_lcd_vo_set(BIT_DISPLAY_LCD_ON); -+ yeeloong_crt_vo_set(BIT_CRT_DETECT_UNPLUG); -+ } -+ return status; -+} -+ -+static int displaytoggle_handler(int status) -+{ -+ /* EC(>=PQ1D26) does this job for us, we can not do it again, -+ * otherwise, the brightness will not resume to the normal level! */ -+ if (ec_version_before("EC_VER=PQ1D26")) -+ yeeloong_lcd_vo_set(status); -+ -+ return status; -+} -+ -+static int switchvideomode_handler(int status) -+{ -+ static int video_output_status; -+ -+ /* Only enable switch video output button -+ * when CRT is connected */ -+ if (ec_read(REG_CRT_DETECT) == BIT_CRT_DETECT_UNPLUG) -+ return 0; -+ /* 0. no CRT connected: LCD on, CRT off -+ * 1. BOTH on -+ * 2. LCD off, CRT on -+ * 3. BOTH off -+ * 4. LCD on, CRT off -+ */ -+ video_output_status++; -+ if (video_output_status > 4) -+ video_output_status = 1; -+ -+ switch (video_output_status) { -+ case 1: -+ yeeloong_lcd_vo_set(BIT_DISPLAY_LCD_ON); -+ yeeloong_crt_vo_set(BIT_CRT_DETECT_PLUG); -+ break; -+ case 2: -+ yeeloong_lcd_vo_set(BIT_DISPLAY_LCD_OFF); -+ yeeloong_crt_vo_set(BIT_CRT_DETECT_PLUG); -+ break; -+ case 3: -+ yeeloong_lcd_vo_set(BIT_DISPLAY_LCD_OFF); -+ yeeloong_crt_vo_set(BIT_CRT_DETECT_UNPLUG); -+ break; -+ case 4: -+ yeeloong_lcd_vo_set(BIT_DISPLAY_LCD_ON); -+ yeeloong_crt_vo_set(BIT_CRT_DETECT_UNPLUG); -+ break; -+ default: -+ /* Ensure LCD is on */ -+ yeeloong_lcd_vo_set(BIT_DISPLAY_LCD_ON); -+ break; -+ } -+ return video_output_status; -+} -+ -+static int camera_handler(int status) -+{ -+ int value; -+ -+ value = ec_read(REG_CAMERA_CONTROL); -+ ec_write(REG_CAMERA_CONTROL, value | (1 << 1)); -+ -+ return status; -+} -+ -+static int usb2_handler(int status) -+{ -+ pr_emerg("USB2 Over Current occurred\n"); -+ -+ return status; -+} -+ -+static int usb0_handler(int status) -+{ -+ pr_emerg("USB0 Over Current occurred\n"); -+ -+ return status; -+} -+ -+static int ac_bat_handler(int status) -+{ -+ if (ac_bat_initialized) { -+ power_supply_changed(&yeeloong_ac); -+ power_supply_changed(&yeeloong_bat); -+ } -+ return status; -+} -+ -+static void do_event_action(int event) -+{ -+ sci_handler handler; -+ int reg, status; -+ struct key_entry *ke; -+ -+ reg = 0; -+ handler = NULL; -+ -+ switch (event) { -+ case EVENT_LID: -+ reg = REG_LID_DETECT; -+ break; -+ case EVENT_SWITCHVIDEOMODE: -+ handler = switchvideomode_handler; -+ break; -+ case EVENT_CRT_DETECT: -+ reg = REG_CRT_DETECT; -+ handler = crt_detect_handler; -+ break; -+ case EVENT_CAMERA: -+ reg = REG_CAMERA_STATUS; -+ handler = camera_handler; -+ break; -+ case EVENT_USB_OC2: -+ reg = REG_USB2_FLAG; -+ handler = usb2_handler; -+ break; -+ case EVENT_USB_OC0: -+ reg = REG_USB0_FLAG; -+ handler = usb0_handler; -+ break; -+ case EVENT_DISPLAYTOGGLE: -+ reg = REG_DISPLAY_LCD; -+ handler = displaytoggle_handler; -+ break; -+ case EVENT_AUDIO_MUTE: -+ reg = REG_AUDIO_MUTE; -+ break; -+ case EVENT_DISPLAY_BRIGHTNESS: -+ reg = REG_DISPLAY_BRIGHTNESS; -+ break; -+ case EVENT_AUDIO_VOLUME: -+ reg = REG_AUDIO_VOLUME; -+ break; -+ case EVENT_AC_BAT: -+ handler = ac_bat_handler; -+ break; -+ default: -+ break; -+ } -+ -+ if (reg != 0) -+ status = ec_read(reg); -+ -+ if (handler != NULL) -+ status = handler(status); -+ -+ pr_info("%s: event: %d status: %d\n", __func__, event, status); -+ -+ /* Report current key to user-space */ -+ ke = get_event_key_entry(event, status); -+ if (ke) { -+ if (ke->keycode == SW_LID) -+ report_lid_switch(status); -+ else -+ sparse_keymap_report_entry(yeeloong_hotkey_dev, ke, 1, -+ true); -+ } -+} -+ -+/* -+ * SCI(system control interrupt) main interrupt routine -+ * -+ * We will do the query and get event number together so the interrupt routine -+ * should be longer than 120us now at least 3ms elpase for it. -+ */ -+static irqreturn_t sci_irq_handler(int irq, void *dev_id) -+{ -+ int ret, event; -+ -+ if (SCI_IRQ_NUM != irq) -+ return IRQ_NONE; -+ -+ /* Query the event number */ -+ ret = ec_query_event_num(); -+ if (ret < 0) -+ return IRQ_NONE; -+ -+ event = ec_get_event_num(); -+ if (event < EVENT_START || event > EVENT_END) -+ return IRQ_NONE; -+ -+ /* Execute corresponding actions */ -+ do_event_action(event); -+ -+ return IRQ_HANDLED; -+} -+ -+/* -+ * Config and init some msr and gpio register properly. -+ */ -+static int sci_irq_init(void) -+{ -+ u32 hi, lo; -+ u32 gpio_base; -+ unsigned long flags; -+ int ret; -+ -+ /* Get gpio base */ -+ _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_GPIO), &hi, &lo); -+ gpio_base = lo & 0xff00; -+ -+ /* Filter the former kb3310 interrupt for security */ -+ ret = ec_query_event_num(); -+ if (ret) -+ return ret; -+ -+ /* For filtering next number interrupt */ -+ udelay(10000); -+ -+ /* Set gpio native registers and msrs for GPIO27 SCI EVENT PIN -+ * gpio : -+ * input, pull-up, no-invert, event-count and value 0, -+ * no-filter, no edge mode -+ * gpio27 map to Virtual gpio0 -+ * msr : -+ * no primary and lpc -+ * Unrestricted Z input to IG10 from Virtual gpio 0. -+ */ -+ local_irq_save(flags); -+ _rdmsr(0x80000024, &hi, &lo); -+ lo &= ~(1 << 10); -+ _wrmsr(0x80000024, hi, lo); -+ _rdmsr(0x80000025, &hi, &lo); -+ lo &= ~(1 << 10); -+ _wrmsr(0x80000025, hi, lo); -+ _rdmsr(0x80000023, &hi, &lo); -+ lo |= (0x0a << 0); -+ _wrmsr(0x80000023, hi, lo); -+ local_irq_restore(flags); -+ -+ /* Set gpio27 as sci interrupt -+ * -+ * input, pull-up, no-fliter, no-negedge, invert -+ * the sci event is just about 120us -+ */ -+ asm(".set noreorder\n"); -+ /* input enable */ -+ outl(0x00000800, (gpio_base | 0xA0)); -+ /* revert the input */ -+ outl(0x00000800, (gpio_base | 0xA4)); -+ /* event-int enable */ -+ outl(0x00000800, (gpio_base | 0xB8)); -+ asm(".set reorder\n"); -+ -+ return 0; -+} -+ -+static struct irqaction sci_irqaction = { -+ .handler = sci_irq_handler, -+ .name = "sci", -+ .flags = IRQF_SHARED, -+}; -+ -+static int yeeloong_hotkey_init(void) -+{ -+ int ret; -+ -+ ret = sci_irq_init(); -+ if (ret) -+ return -EFAULT; -+ -+ ret = setup_irq(SCI_IRQ_NUM, &sci_irqaction); -+ if (ret) -+ return -EFAULT; -+ -+ yeeloong_hotkey_dev = input_allocate_device(); -+ -+ if (!yeeloong_hotkey_dev) { -+ remove_irq(SCI_IRQ_NUM, &sci_irqaction); -+ return -ENOMEM; -+ } -+ -+ yeeloong_hotkey_dev->name = "HotKeys"; -+ yeeloong_hotkey_dev->phys = "button/input0"; -+ yeeloong_hotkey_dev->id.bustype = BUS_HOST; -+ yeeloong_hotkey_dev->dev.parent = NULL; -+ -+ ret = sparse_keymap_setup(yeeloong_hotkey_dev, yeeloong_keymap, NULL); -+ if (ret) { -+ pr_err("Fail to setup input device keymap\n"); -+ input_free_device(yeeloong_hotkey_dev); -+ return ret; -+ } -+ -+ ret = input_register_device(yeeloong_hotkey_dev); -+ if (ret) { -+ sparse_keymap_free(yeeloong_hotkey_dev); -+ input_free_device(yeeloong_hotkey_dev); -+ return ret; -+ } -+ -+ /* Update the current status of LID */ -+ report_lid_switch(BIT_LID_DETECT_ON); -+ -+#ifdef CONFIG_LOONGSON_SUSPEND -+ /* Install the real yeeloong_report_lid_status for pm.c */ -+ yeeloong_report_lid_status = report_lid_switch; -+#endif -+ -+ return 0; -+} -+ -+static void yeeloong_hotkey_exit(void) -+{ -+ /* Free irq */ -+ remove_irq(SCI_IRQ_NUM, &sci_irqaction); -+ -+#ifdef CONFIG_LOONGSON_SUSPEND -+ /* Uninstall yeeloong_report_lid_status for pm.c */ -+ if (yeeloong_report_lid_status == report_lid_switch) -+ yeeloong_report_lid_status = NULL; -+#endif -+ -+ if (yeeloong_hotkey_dev) { -+ sparse_keymap_free(yeeloong_hotkey_dev); -+ input_unregister_device(yeeloong_hotkey_dev); -+ yeeloong_hotkey_dev = NULL; -+ } -+} -+ -+#ifdef CONFIG_PM -+static void usb_ports_set(int status) -+{ -+ status = !!status; -+ -+ ec_write(REG_USB0_FLAG, status); -+ ec_write(REG_USB1_FLAG, status); -+ ec_write(REG_USB2_FLAG, status); -+} -+ -+static int yeeloong_suspend(struct device *dev) -+ -+{ -+ if (ec_version_before("EC_VER=PQ1D27")) -+ yeeloong_lcd_vo_set(BIT_DISPLAY_LCD_OFF); -+ yeeloong_crt_vo_set(BIT_CRT_DETECT_UNPLUG); -+ usb_ports_set(BIT_USB_FLAG_OFF); -+ -+ return 0; -+} -+ -+static int yeeloong_resume(struct device *dev) -+{ -+ if (ec_version_before("EC_VER=PQ1D27")) -+ yeeloong_lcd_vo_set(BIT_DISPLAY_LCD_ON); -+ yeeloong_crt_vo_set(BIT_CRT_DETECT_PLUG); -+ usb_ports_set(BIT_USB_FLAG_ON); -+ -+ return 0; -+} -+ -+static const SIMPLE_DEV_PM_OPS(yeeloong_pm_ops, yeeloong_suspend, -+ yeeloong_resume); -+#endif -+ -+static struct platform_device_id platform_device_ids[] = { -+ { -+ .name = "yeeloong_laptop", -+ }, -+ {} -+}; -+ -+MODULE_DEVICE_TABLE(platform, platform_device_ids); -+ -+static struct platform_driver platform_driver = { -+ .driver = { -+ .name = "yeeloong_laptop", -+ .owner = THIS_MODULE, -+#ifdef CONFIG_PM -+ .pm = &yeeloong_pm_ops, -+#endif -+ }, -+ .id_table = platform_device_ids, -+}; -+ -+static int __init yeeloong_init(void) -+{ -+ int ret; -+ -+ pr_info("Load YeeLoong Laptop Platform Specific Driver.\n"); -+ -+ /* Register platform stuff */ -+ ret = platform_driver_register(&platform_driver); -+ if (ret) { -+ pr_err("Fail to register yeeloong platform driver.\n"); -+ return ret; -+ } -+ -+ ret = yeeloong_backlight_init(); -+ if (ret) { -+ pr_err("Fail to register yeeloong backlight driver.\n"); -+ yeeloong_backlight_exit(); -+ return ret; -+ } -+ -+ ret = yeeloong_bat_init(); -+ if (ret) { -+ pr_err("Fail to register yeeloong battery driver.\n"); -+ yeeloong_bat_exit(); -+ return ret; -+ } -+ -+ ret = yeeloong_hwmon_init(); -+ if (ret) { -+ pr_err("Fail to register yeeloong hwmon driver.\n"); -+ yeeloong_hwmon_exit(); -+ return ret; -+ } -+ -+ ret = yeeloong_vo_init(); -+ if (ret) { -+ pr_err("Fail to register yeeloong video output driver.\n"); -+ yeeloong_vo_exit(); -+ return ret; -+ } -+ -+ ret = yeeloong_hotkey_init(); -+ if (ret) { -+ pr_err("Fail to register yeeloong hotkey driver.\n"); -+ yeeloong_hotkey_exit(); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static void __exit yeeloong_exit(void) -+{ -+ yeeloong_hotkey_exit(); -+ yeeloong_vo_exit(); -+ yeeloong_hwmon_exit(); -+ yeeloong_bat_exit(); -+ yeeloong_backlight_exit(); -+ platform_driver_unregister(&platform_driver); -+ -+ pr_info("Unload YeeLoong Platform Specific Driver.\n"); -+} -+ -+module_init(yeeloong_init); -+module_exit(yeeloong_exit); -+ -+MODULE_AUTHOR("Wu Zhangjin ; Liu Junliang "); -+MODULE_DESCRIPTION("YeeLoong laptop driver"); -+MODULE_LICENSE("GPL"); -diff -Nur linux-2.6.37.orig/drivers/staging/sm7xx/smtcfb.c linux-2.6.37/drivers/staging/sm7xx/smtcfb.c ---- linux-2.6.37.orig/drivers/staging/sm7xx/smtcfb.c 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/staging/sm7xx/smtcfb.c 2011-01-11 20:44:43.000000000 +0100 -@@ -12,6 +12,8 @@ - * License. See the file COPYING in the main directory of this archive for - * more details. - * -+ * - Remove the buggy 2D support for Lynx, 2010/01/06, Wu Zhangjin -+ * - * Version 0.10.26192.21.01 - * - Add PowerPC/Big endian support - * - Add 2D support for Lynx -@@ -107,6 +109,7 @@ - {"0x307", 1280, 1024, 8}, - - {"0x311", 640, 480, 16}, -+ {"0x313", 800, 480, 16}, - {"0x314", 800, 600, 16}, - {"0x317", 1024, 768, 16}, - {"0x31A", 1280, 1024, 16}, -diff -Nur linux-2.6.37.orig/drivers/usb/host/ohci-hcd.c linux-2.6.37/drivers/usb/host/ohci-hcd.c ---- linux-2.6.37.orig/drivers/usb/host/ohci-hcd.c 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/usb/host/ohci-hcd.c 2011-01-11 20:44:43.000000000 +0100 -@@ -838,9 +838,13 @@ - } - - if (ints & OHCI_INTR_WDH) { -- spin_lock (&ohci->lock); -- dl_done_list (ohci); -- spin_unlock (&ohci->lock); -+ if (ohci->hcca->done_head == 0) { -+ ints &= ~OHCI_INTR_WDH; -+ } else { -+ spin_lock (&ohci->lock); -+ dl_done_list (ohci); -+ spin_unlock (&ohci->lock); -+ } - } - - if (quirk_zfmicro(ohci) && (ints & OHCI_INTR_SF)) { -diff -Nur linux-2.6.37.orig/net/rfkill/core.c linux-2.6.37/net/rfkill/core.c ---- linux-2.6.37.orig/net/rfkill/core.c 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/net/rfkill/core.c 2011-01-11 20:44:43.000000000 +0100 -@@ -112,7 +112,7 @@ - static DEFINE_MUTEX(rfkill_global_mutex); - static LIST_HEAD(rfkill_fds); /* list of open fds of /dev/rfkill */ - --static unsigned int rfkill_default_state = 1; -+static unsigned int rfkill_default_state; /* default: 0 = radio off */ - module_param_named(default_state, rfkill_default_state, uint, 0444); - MODULE_PARM_DESC(default_state, - "Default initial state for all radio types, 0 = radio off"); diff --git a/target/linux/patches/2.6.37/mtd-rootfs.patch b/target/linux/patches/2.6.37/mtd-rootfs.patch deleted file mode 100644 index 9db687c90..000000000 --- a/target/linux/patches/2.6.37/mtd-rootfs.patch +++ /dev/null @@ -1,25 +0,0 @@ ---- linux-2.6.37.orig/drivers/mtd/mtdpart.c -+++ linux-2.6.37/drivers/mtd/mtdpart.c -@@ -30,6 +30,7 @@ - #include - #include - #include -+#include - - /* Our partition linked list */ - static LIST_HEAD(mtd_partitions); -@@ -641,6 +642,14 @@ - slave = allocate_partition(master, parts + i, i, cur_offset); - if (IS_ERR(slave)) - return PTR_ERR(slave); -+ -+ if (strcmp(parts[i].name, "rootfs") == 0) { -+ if (ROOT_DEV == 0) { -+ printk(KERN_NOTICE "mtd: partition \"rootfs\" " -+ "set to be root filesystem\n"); -+ ROOT_DEV = MKDEV(MTD_BLOCK_MAJOR, i); -+ } -+ } - - mutex_lock(&mtd_partitions_mutex); - list_add(&slave->list, &mtd_partitions); diff --git a/target/linux/patches/2.6.37/ocf-20100325.patch b/target/linux/patches/2.6.37/ocf-20100325.patch deleted file mode 100644 index bb4e537d5..000000000 --- a/target/linux/patches/2.6.37/ocf-20100325.patch +++ /dev/null @@ -1,87545 +0,0 @@ -diff -Nur linux-2.6.36.orig/crypto/Kconfig linux-2.6.36/crypto/Kconfig ---- linux-2.6.36.orig/crypto/Kconfig 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/crypto/Kconfig 2010-11-09 20:28:04.004996902 +0100 -@@ -845,3 +845,6 @@ - source "drivers/crypto/Kconfig" - - endif # if CRYPTO -+ -+source "crypto/ocf/Kconfig" -+ -diff -Nur linux-2.6.36.orig/crypto/Makefile linux-2.6.36/crypto/Makefile ---- linux-2.6.36.orig/crypto/Makefile 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/crypto/Makefile 2010-11-09 20:28:04.014995662 +0100 -@@ -86,6 +86,8 @@ - obj-$(CONFIG_CRYPTO_TEST) += tcrypt.o - obj-$(CONFIG_CRYPTO_GHASH) += ghash-generic.o - -+obj-$(CONFIG_OCF_OCF) += ocf/ -+ - # - # generic algorithms and the async_tx api - # -diff -Nur linux-2.6.36.orig/crypto/ocf/c7108/aes-7108.c linux-2.6.36/crypto/ocf/c7108/aes-7108.c ---- linux-2.6.36.orig/crypto/ocf/c7108/aes-7108.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/c7108/aes-7108.c 2010-11-09 20:28:04.061247304 +0100 -@@ -0,0 +1,839 @@ -+/* -+ * Copyright (C) 2006 Micronas USA -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored in part by the Defense Advanced Research Projects -+ * Agency (DARPA) and Air Force Research Laboratory, Air Force -+ * Materiel Command, USAF, under agreement number F30602-01-2-0537. -+ * -+ */ -+ -+//#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+//#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* Runtime mode */ -+static int c7108_crypto_mode = C7108_AES_CTRL_MODE_CTR; -+//static int c7108_crypto_mode = C7108_AES_CTRL_MODE_CBC; -+ -+static int32_t c7108_id = -1; -+static struct cipher_7108 **c7108_sessions = NULL; -+static u_int32_t c7108_sesnum = 0; -+static unsigned long iobar; -+ -+/* Crypto entry points */ -+static int c7108_process(void *, struct cryptop *, int); -+static int c7108_newsession(void *, u_int32_t *, struct cryptoini *); -+static int c7108_freesession(void *, u_int64_t); -+ -+/* Globals */ -+static int debug = 0; -+static spinlock_t csr_mutex; -+ -+/* Generic controller-based lock */ -+#define AES_LOCK()\ -+ spin_lock(&csr_mutex) -+#define AES_UNLOCK()\ -+ spin_unlock(&csr_mutex) -+ -+/* 7108 AES register access */ -+#define c7108_reg_wr8(a,d) iowrite8(d, (void*)(iobar+(a))) -+#define c7108_reg_wr16(a,d) iowrite16(d, (void*)(iobar+(a))) -+#define c7108_reg_wr32(a,d) iowrite32(d, (void*)(iobar+(a))) -+#define c7108_reg_rd8(a) ioread8((void*)(iobar+(a))) -+#define c7108_reg_rd16(a) ioread16((void*)(iobar+(a))) -+#define c7108_reg_rd32(a) ioread32((void*)(iobar+(a))) -+ -+static int -+c7108_xlate_key(int klen, u8* k8ptr, u32* k32ptr) -+{ -+ int i, nw=0; -+ nw = ((klen >= 256) ? 8 : (klen >= 192) ? 6 : 4); -+ for ( i = 0; i < nw; i++) { -+ k32ptr[i] = (k8ptr[i+3] << 24) | (k8ptr[i+2] << 16) | -+ (k8ptr[i+1] << 8) | k8ptr[i]; -+ -+ } -+ return 0; -+} -+ -+static int -+c7108_cache_key(int klen, u32* k32ptr, u8* k8ptr) -+{ -+ int i, nb=0; -+ u8* ptr = (u8*)k32ptr; -+ nb = ((klen >= 256) ? 32 : (klen >= 192) ? 24 : 16); -+ for ( i = 0; i < nb; i++) -+ k8ptr[i] = ptr[i]; -+ return 0; -+} -+ -+static int -+c7108_aes_setup_dma(u32 src, u32 dst, u32 len) -+{ -+ if (len < 16) { -+ printk("len < 16\n"); -+ return -10; -+ } -+ if (len % 16) { -+ printk("len not multiple of 16\n"); -+ return -11; -+ } -+ c7108_reg_wr16(C7108_AES_DMA_SRC0_LO, (u16) src); -+ c7108_reg_wr16(C7108_AES_DMA_SRC0_HI, (u16)((src & 0xffff0000) >> 16)); -+ c7108_reg_wr16(C7108_AES_DMA_DST0_LO, (u16) dst); -+ c7108_reg_wr16(C7108_AES_DMA_DST0_HI, (u16)((dst & 0xffff0000) >> 16)); -+ c7108_reg_wr16(C7108_AES_DMA_LEN, (u16) ((len / 16) - 1)); -+ -+ return 0; -+} -+ -+static int -+c7108_aes_set_hw_iv(u8 iv[16]) -+{ -+ c7108_reg_wr16(C7108_AES_IV0_LO, (u16) ((iv[1] << 8) | iv[0])); -+ c7108_reg_wr16(C7108_AES_IV0_HI, (u16) ((iv[3] << 8) | iv[2])); -+ c7108_reg_wr16(C7108_AES_IV1_LO, (u16) ((iv[5] << 8) | iv[4])); -+ c7108_reg_wr16(C7108_AES_IV1_HI, (u16) ((iv[7] << 8) | iv[6])); -+ c7108_reg_wr16(C7108_AES_IV2_LO, (u16) ((iv[9] << 8) | iv[8])); -+ c7108_reg_wr16(C7108_AES_IV2_HI, (u16) ((iv[11] << 8) | iv[10])); -+ c7108_reg_wr16(C7108_AES_IV3_LO, (u16) ((iv[13] << 8) | iv[12])); -+ c7108_reg_wr16(C7108_AES_IV3_HI, (u16) ((iv[15] << 8) | iv[14])); -+ -+ return 0; -+} -+ -+static void -+c7108_aes_read_dkey(u32 * dkey) -+{ -+ dkey[0] = (c7108_reg_rd16(C7108_AES_EKEY0_HI) << 16) | -+ c7108_reg_rd16(C7108_AES_EKEY0_LO); -+ dkey[1] = (c7108_reg_rd16(C7108_AES_EKEY1_HI) << 16) | -+ c7108_reg_rd16(C7108_AES_EKEY1_LO); -+ dkey[2] = (c7108_reg_rd16(C7108_AES_EKEY2_HI) << 16) | -+ c7108_reg_rd16(C7108_AES_EKEY2_LO); -+ dkey[3] = (c7108_reg_rd16(C7108_AES_EKEY3_HI) << 16) | -+ c7108_reg_rd16(C7108_AES_EKEY3_LO); -+ dkey[4] = (c7108_reg_rd16(C7108_AES_EKEY4_HI) << 16) | -+ c7108_reg_rd16(C7108_AES_EKEY4_LO); -+ dkey[5] = (c7108_reg_rd16(C7108_AES_EKEY5_HI) << 16) | -+ c7108_reg_rd16(C7108_AES_EKEY5_LO); -+ dkey[6] = (c7108_reg_rd16(C7108_AES_EKEY6_HI) << 16) | -+ c7108_reg_rd16(C7108_AES_EKEY6_LO); -+ dkey[7] = (c7108_reg_rd16(C7108_AES_EKEY7_HI) << 16) | -+ c7108_reg_rd16(C7108_AES_EKEY7_LO); -+} -+ -+static int -+c7108_aes_cipher(int op, -+ u32 dst, -+ u32 src, -+ u32 len, -+ int klen, -+ u16 mode, -+ u32 key[8], -+ u8 iv[16]) -+{ -+ int rv = 0, cnt=0; -+ u16 ctrl = 0, stat = 0; -+ -+ AES_LOCK(); -+ -+ /* Setup key length */ -+ if (klen == 128) { -+ ctrl |= C7108_AES_KEY_LEN_128; -+ } else if (klen == 192) { -+ ctrl |= C7108_AES_KEY_LEN_192; -+ } else if (klen == 256) { -+ ctrl |= C7108_AES_KEY_LEN_256; -+ } else { -+ AES_UNLOCK(); -+ return -3; -+ } -+ -+ /* Check opcode */ -+ if (C7108_AES_ENCRYPT == op) { -+ ctrl |= C7108_AES_ENCRYPT; -+ } else if (C7108_AES_DECRYPT == op) { -+ ctrl |= C7108_AES_DECRYPT; -+ } else { -+ AES_UNLOCK(); -+ return -4; -+ } -+ -+ /* check mode */ -+ if ( (mode != C7108_AES_CTRL_MODE_CBC) && -+ (mode != C7108_AES_CTRL_MODE_CFB) && -+ (mode != C7108_AES_CTRL_MODE_OFB) && -+ (mode != C7108_AES_CTRL_MODE_CTR) && -+ (mode != C7108_AES_CTRL_MODE_ECB) ) { -+ AES_UNLOCK(); -+ return -5; -+ } -+ -+ /* Now set mode */ -+ ctrl |= mode; -+ -+ /* For CFB, OFB, and CTR, neither backward key -+ * expansion nor key inversion is required. -+ */ -+ if ( (C7108_AES_DECRYPT == op) && -+ (C7108_AES_CTRL_MODE_CBC == mode || -+ C7108_AES_CTRL_MODE_ECB == mode ) ){ -+ -+ /* Program Key */ -+ c7108_reg_wr16(C7108_AES_KEY0_LO, (u16) key[4]); -+ c7108_reg_wr16(C7108_AES_KEY0_HI, (u16) (key[4] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY1_LO, (u16) key[5]); -+ c7108_reg_wr16(C7108_AES_KEY1_HI, (u16) (key[5] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY2_LO, (u16) key[6]); -+ c7108_reg_wr16(C7108_AES_KEY2_HI, (u16) (key[6] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY3_LO, (u16) key[7]); -+ c7108_reg_wr16(C7108_AES_KEY3_HI, (u16) (key[7] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY6_LO, (u16) key[2]); -+ c7108_reg_wr16(C7108_AES_KEY6_HI, (u16) (key[2] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY7_LO, (u16) key[3]); -+ c7108_reg_wr16(C7108_AES_KEY7_HI, (u16) (key[3] >> 16)); -+ -+ -+ if (192 == klen) { -+ c7108_reg_wr16(C7108_AES_KEY4_LO, (u16) key[7]); -+ c7108_reg_wr16(C7108_AES_KEY4_HI, (u16) (key[7] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY5_LO, (u16) key[7]); -+ c7108_reg_wr16(C7108_AES_KEY5_HI, (u16) (key[7] >> 16)); -+ -+ } else if (256 == klen) { -+ /* 256 */ -+ c7108_reg_wr16(C7108_AES_KEY4_LO, (u16) key[0]); -+ c7108_reg_wr16(C7108_AES_KEY4_HI, (u16) (key[0] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY5_LO, (u16) key[1]); -+ c7108_reg_wr16(C7108_AES_KEY5_HI, (u16) (key[1] >> 16)); -+ -+ } -+ -+ } else { -+ /* Program Key */ -+ c7108_reg_wr16(C7108_AES_KEY0_LO, (u16) key[0]); -+ c7108_reg_wr16(C7108_AES_KEY0_HI, (u16) (key[0] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY1_LO, (u16) key[1]); -+ c7108_reg_wr16(C7108_AES_KEY1_HI, (u16) (key[1] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY2_LO, (u16) key[2]); -+ c7108_reg_wr16(C7108_AES_KEY2_HI, (u16) (key[2] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY3_LO, (u16) key[3]); -+ c7108_reg_wr16(C7108_AES_KEY3_HI, (u16) (key[3] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY4_LO, (u16) key[4]); -+ c7108_reg_wr16(C7108_AES_KEY4_HI, (u16) (key[4] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY5_LO, (u16) key[5]); -+ c7108_reg_wr16(C7108_AES_KEY5_HI, (u16) (key[5] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY6_LO, (u16) key[6]); -+ c7108_reg_wr16(C7108_AES_KEY6_HI, (u16) (key[6] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY7_LO, (u16) key[7]); -+ c7108_reg_wr16(C7108_AES_KEY7_HI, (u16) (key[7] >> 16)); -+ -+ } -+ -+ /* Set IV always */ -+ c7108_aes_set_hw_iv(iv); -+ -+ /* Program DMA addresses */ -+ if ((rv = c7108_aes_setup_dma(src, dst, len)) < 0) { -+ AES_UNLOCK(); -+ return rv; -+ } -+ -+ -+ /* Start AES cipher */ -+ c7108_reg_wr16(C7108_AES_CTRL, ctrl | C7108_AES_GO); -+ -+ //printk("Ctrl: 0x%x\n", ctrl | C7108_AES_GO); -+ do { -+ /* TODO: interrupt mode */ -+ // printk("aes_stat=0x%x\n", stat); -+ //udelay(100); -+ } while ((cnt++ < 1000000) && -+ !((stat=c7108_reg_rd16(C7108_AES_CTRL))&C7108_AES_OP_DONE)); -+ -+ -+ if ((mode == C7108_AES_CTRL_MODE_ECB)|| -+ (mode == C7108_AES_CTRL_MODE_CBC)) { -+ /* Save out key when the lock is held ... */ -+ c7108_aes_read_dkey(key); -+ } -+ -+ AES_UNLOCK(); -+ return 0; -+ -+} -+ -+/* -+ * Generate a new crypto device session. -+ */ -+static int -+c7108_newsession(void *arg, u_int32_t *sid, struct cryptoini *cri) -+{ -+ struct cipher_7108 **swd; -+ u_int32_t i; -+ char *algo; -+ int mode, xfm_type; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid == NULL || cri == NULL) { -+ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ if (c7108_sessions) { -+ for (i = 1; i < c7108_sesnum; i++) -+ if (c7108_sessions[i] == NULL) -+ break; -+ } else -+ i = 1; /* NB: to silence compiler warning */ -+ -+ if (c7108_sessions == NULL || i == c7108_sesnum) { -+ if (c7108_sessions == NULL) { -+ i = 1; /* We leave c7108_sessions[0] empty */ -+ c7108_sesnum = CRYPTO_SW_SESSIONS; -+ } else -+ c7108_sesnum *= 2; -+ -+ swd = kmalloc(c7108_sesnum * sizeof(struct cipher_7108 *), -+ GFP_ATOMIC); -+ if (swd == NULL) { -+ /* Reset session number */ -+ if (c7108_sesnum == CRYPTO_SW_SESSIONS) -+ c7108_sesnum = 0; -+ else -+ c7108_sesnum /= 2; -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memset(swd, 0, c7108_sesnum * sizeof(struct cipher_7108 *)); -+ -+ /* Copy existing sessions */ -+ if (c7108_sessions) { -+ memcpy(swd, c7108_sessions, -+ (c7108_sesnum / 2) * sizeof(struct cipher_7108 *)); -+ kfree(c7108_sessions); -+ } -+ -+ c7108_sessions = swd; -+ -+ } -+ -+ swd = &c7108_sessions[i]; -+ *sid = i; -+ -+ while (cri) { -+ *swd = (struct cipher_7108 *) -+ kmalloc(sizeof(struct cipher_7108), GFP_ATOMIC); -+ if (*swd == NULL) { -+ c7108_freesession(NULL, i); -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memset(*swd, 0, sizeof(struct cipher_7108)); -+ -+ algo = NULL; -+ mode = 0; -+ xfm_type = HW_TYPE_CIPHER; -+ -+ switch (cri->cri_alg) { -+ -+ case CRYPTO_AES_CBC: -+ algo = "aes"; -+ mode = CRYPTO_TFM_MODE_CBC; -+ c7108_crypto_mode = C7108_AES_CTRL_MODE_CBC; -+ break; -+#if 0 -+ case CRYPTO_AES_CTR: -+ algo = "aes_ctr"; -+ mode = CRYPTO_TFM_MODE_CBC; -+ c7108_crypto_mode = C7108_AES_CTRL_MODE_CTR; -+ break; -+ case CRYPTO_AES_ECB: -+ algo = "aes_ecb"; -+ mode = CRYPTO_TFM_MODE_CBC; -+ c7108_crypto_mode = C7108_AES_CTRL_MODE_ECB; -+ break; -+ case CRYPTO_AES_OFB: -+ algo = "aes_ofb"; -+ mode = CRYPTO_TFM_MODE_CBC; -+ c7108_crypto_mode = C7108_AES_CTRL_MODE_OFB; -+ break; -+ case CRYPTO_AES_CFB: -+ algo = "aes_cfb"; -+ mode = CRYPTO_TFM_MODE_CBC; -+ c7108_crypto_mode = C7108_AES_CTRL_MODE_CFB; -+ break; -+#endif -+ default: -+ printk("unsupported crypto algorithm: %d\n", -+ cri->cri_alg); -+ return -EINVAL; -+ break; -+ } -+ -+ -+ if (!algo || !*algo) { -+ printk("cypher_7108_crypto: Unknown algo 0x%x\n", -+ cri->cri_alg); -+ c7108_freesession(NULL, i); -+ return EINVAL; -+ } -+ -+ if (xfm_type == HW_TYPE_CIPHER) { -+ if (debug) { -+ dprintk("%s key:", __FUNCTION__); -+ for (i = 0; i < (cri->cri_klen + 7) / 8; i++) -+ dprintk("%s0x%02x", (i % 8) ? " " : "\n ", -+ cri->cri_key[i]); -+ dprintk("\n"); -+ } -+ -+ } else if (xfm_type == SW_TYPE_HMAC || -+ xfm_type == SW_TYPE_HASH) { -+ printk("cypher_7108_crypto: HMAC unsupported!\n"); -+ return -EINVAL; -+ c7108_freesession(NULL, i); -+ } else { -+ printk("cypher_7108_crypto: " -+ "Unhandled xfm_type %d\n", xfm_type); -+ c7108_freesession(NULL, i); -+ return EINVAL; -+ } -+ -+ (*swd)->cri_alg = cri->cri_alg; -+ (*swd)->xfm_type = xfm_type; -+ -+ cri = cri->cri_next; -+ swd = &((*swd)->next); -+ } -+ return 0; -+} -+ -+/* -+ * Free a session. -+ */ -+static int -+c7108_freesession(void *arg, u_int64_t tid) -+{ -+ struct cipher_7108 *swd; -+ u_int32_t sid = CRYPTO_SESID2LID(tid); -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid > c7108_sesnum || c7108_sessions == NULL || -+ c7108_sessions[sid] == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return(EINVAL); -+ } -+ -+ /* Silently accept and return */ -+ if (sid == 0) -+ return(0); -+ -+ while ((swd = c7108_sessions[sid]) != NULL) { -+ c7108_sessions[sid] = swd->next; -+ kfree(swd); -+ } -+ return 0; -+} -+ -+/* -+ * Process a hardware request. -+ */ -+static int -+c7108_process(void *arg, struct cryptop *crp, int hint) -+{ -+ struct cryptodesc *crd; -+ struct cipher_7108 *sw; -+ u_int32_t lid; -+ int type; -+ u32 hwkey[8]; -+ -+#define SCATTERLIST_MAX 16 -+ struct scatterlist sg[SCATTERLIST_MAX]; -+ int sg_num, sg_len, skip; -+ struct sk_buff *skb = NULL; -+ struct uio *uiop = NULL; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ /* Sanity check */ -+ if (crp == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ crp->crp_etype = 0; -+ -+ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ lid = crp->crp_sid & 0xffffffff; -+ if (lid >= c7108_sesnum || lid == 0 || c7108_sessions == NULL || -+ c7108_sessions[lid] == NULL) { -+ crp->crp_etype = ENOENT; -+ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); -+ goto done; -+ } -+ -+ /* -+ * do some error checking outside of the loop for SKB and IOV -+ * processing this leaves us with valid skb or uiop pointers -+ * for later -+ */ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ skb = (struct sk_buff *) crp->crp_buf; -+ if (skb_shinfo(skb)->nr_frags >= SCATTERLIST_MAX) { -+ printk("%s,%d: %d nr_frags > SCATTERLIST_MAX", -+ __FILE__, __LINE__, -+ skb_shinfo(skb)->nr_frags); -+ goto done; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ uiop = (struct uio *) crp->crp_buf; -+ if (uiop->uio_iovcnt > SCATTERLIST_MAX) { -+ printk("%s,%d: %d uio_iovcnt > SCATTERLIST_MAX", -+ __FILE__, __LINE__, -+ uiop->uio_iovcnt); -+ goto done; -+ } -+ } -+ -+ /* Go through crypto descriptors, processing as we go */ -+ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { -+ /* -+ * Find the crypto context. -+ * -+ * XXX Note that the logic here prevents us from having -+ * XXX the same algorithm multiple times in a session -+ * XXX (or rather, we can but it won't give us the right -+ * XXX results). To do that, we'd need some way of differentiating -+ * XXX between the various instances of an algorithm (so we can -+ * XXX locate the correct crypto context). -+ */ -+ for (sw = c7108_sessions[lid]; -+ sw && sw->cri_alg != crd->crd_alg; -+ sw = sw->next) -+ ; -+ -+ /* No such context ? */ -+ if (sw == NULL) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ goto done; -+ } -+ -+ skip = crd->crd_skip; -+ -+ /* -+ * setup the SG list skip from the start of the buffer -+ */ -+ memset(sg, 0, sizeof(sg)); -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ int i, len; -+ type = CRYPTO_BUF_SKBUF; -+ -+ sg_num = 0; -+ sg_len = 0; -+ -+ if (skip < skb_headlen(skb)) { -+ //sg[sg_num].page = virt_to_page(skb->data + skip); -+ //sg[sg_num].offset = offset_in_page(skb->data + skip); -+ len = skb_headlen(skb) - skip; -+ if (len + sg_len > crd->crd_len) -+ len = crd->crd_len - sg_len; -+ //sg[sg_num].length = len; -+ sg_set_page(&sg[sg_num], virt_to_page(skb->data + skip), len, offset_in_page(skb->data + skip)); -+ sg_len += sg[sg_num].length; -+ sg_num++; -+ skip = 0; -+ } else -+ skip -= skb_headlen(skb); -+ -+ for (i = 0; sg_len < crd->crd_len && -+ i < skb_shinfo(skb)->nr_frags && -+ sg_num < SCATTERLIST_MAX; i++) { -+ if (skip < skb_shinfo(skb)->frags[i].size) { -+ //sg[sg_num].page = skb_shinfo(skb)->frags[i].page; -+ //sg[sg_num].offset = skb_shinfo(skb)->frags[i].page_offset + skip; -+ len = skb_shinfo(skb)->frags[i].size - skip; -+ if (len + sg_len > crd->crd_len) -+ len = crd->crd_len - sg_len; -+ //sg[sg_num].length = len; -+ sg_set_page(&sg[sg_num], skb_shinfo(skb)->frags[i].page, len, skb_shinfo(skb)->frags[i].page_offset + skip); -+ sg_len += sg[sg_num].length; -+ sg_num++; -+ skip = 0; -+ } else -+ skip -= skb_shinfo(skb)->frags[i].size; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ int len; -+ type = CRYPTO_BUF_IOV; -+ sg_len = 0; -+ for (sg_num = 0; sg_len < crd->crd_len && -+ sg_num < uiop->uio_iovcnt && -+ sg_num < SCATTERLIST_MAX; sg_num++) { -+ if (skip < uiop->uio_iov[sg_num].iov_len) { -+ //sg[sg_num].page = virt_to_page(uiop->uio_iov[sg_num].iov_base+skip); -+ //sg[sg_num].offset = offset_in_page(uiop->uio_iov[sg_num].iov_base+skip); -+ len = uiop->uio_iov[sg_num].iov_len - skip; -+ if (len + sg_len > crd->crd_len) -+ len = crd->crd_len - sg_len; -+ //sg[sg_num].length = len; -+ sg_set_page(&sg[sg_num], virt_to_page(uiop->uio_iov[sg_num].iov_base+skip), len, offset_in_page(uiop->uio_iov[sg_num].iov_base+skip)); -+ sg_len += sg[sg_num].length; -+ skip = 0; -+ } else -+ skip -= uiop->uio_iov[sg_num].iov_len; -+ } -+ } else { -+ type = CRYPTO_BUF_CONTIG; -+ //sg[0].page = virt_to_page(crp->crp_buf + skip); -+ //sg[0].offset = offset_in_page(crp->crp_buf + skip); -+ sg_len = (crp->crp_ilen - skip); -+ if (sg_len > crd->crd_len) -+ sg_len = crd->crd_len; -+ //sg[0].length = sg_len; -+ sg_set_page(&sg[0], virt_to_page(crp->crp_buf + skip), sg_len, offset_in_page(crp->crp_buf + skip)); -+ sg_num = 1; -+ } -+ -+ -+ switch (sw->xfm_type) { -+ -+ case HW_TYPE_CIPHER: { -+ -+ unsigned char iv[64]; -+ unsigned char *ivp = iv; -+ int i; -+ int ivsize = 16; /* fixed for AES */ -+ int blocksize = 16; /* fixed for AES */ -+ -+ if (sg_len < blocksize) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: EINVAL len %d < %d\n", -+ __FILE__, __LINE__, -+ sg_len, -+ blocksize); -+ goto done; -+ } -+ -+ if (ivsize > sizeof(iv)) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ goto done; -+ } -+ -+ if (crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ -+ -+ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { -+ ivp = crd->crd_iv; -+ } else { -+ get_random_bytes(ivp, ivsize); -+ } -+ /* -+ * do we have to copy the IV back to the buffer ? -+ */ -+ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { -+ crypto_copyback(crp->crp_buf, -+ crd->crd_inject, -+ ivsize, -+ (caddr_t)ivp); -+ } -+ -+ c7108_xlate_key(crd->crd_klen, -+ (u8*)crd->crd_key, (u32*)hwkey); -+ -+ /* Encrypt SG list */ -+ for (i = 0; i < sg_num; i++) { -+ sg[i].dma_address = -+ dma_map_single(NULL, -+ kmap(sg_page(&sg[i])) + sg[i].offset, sg_len, DMA_BIDIRECTIONAL); -+#if 0 -+ printk("sg[%d]:0x%08x, off 0x%08x " -+ "kmap 0x%08x phys 0x%08x\n", -+ i, sg[i].page, sg[i].offset, -+ kmap(sg[i].page) + sg[i].offset, -+ sg[i].dma_address); -+#endif -+ c7108_aes_cipher(C7108_AES_ENCRYPT, -+ sg[i].dma_address, -+ sg[i].dma_address, -+ sg_len, -+ crd->crd_klen, -+ c7108_crypto_mode, -+ hwkey, -+ ivp); -+ -+ if ((c7108_crypto_mode == C7108_AES_CTRL_MODE_CBC)|| -+ (c7108_crypto_mode == C7108_AES_CTRL_MODE_ECB)) { -+ /* Read back expanded key and cache it in key -+ * context. -+ * NOTE: for ECB/CBC modes only (not CTR, CFB, OFB) -+ * where you set the key once. -+ */ -+ c7108_cache_key(crd->crd_klen, -+ (u32*)hwkey, (u8*)crd->crd_key); -+#if 0 -+ printk("%s expanded key:", __FUNCTION__); -+ for (i = 0; i < (crd->crd_klen + 7) / 8; i++) -+ printk("%s0x%02x", (i % 8) ? " " : "\n ", -+ crd->crd_key[i]); -+ printk("\n"); -+#endif -+ } -+ } -+ } -+ else { /*decrypt */ -+ -+ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { -+ ivp = crd->crd_iv; -+ } else { -+ crypto_copydata(crp->crp_buf, crd->crd_inject, -+ ivsize, (caddr_t)ivp); -+ } -+ -+ c7108_xlate_key(crd->crd_klen, -+ (u8*)crd->crd_key, (u32*)hwkey); -+ -+ /* Decrypt SG list */ -+ for (i = 0; i < sg_num; i++) { -+ sg[i].dma_address = -+ dma_map_single(NULL, -+ kmap(sg_page(&sg[i])) + sg[i].offset, -+ sg_len, DMA_BIDIRECTIONAL); -+ -+#if 0 -+ printk("sg[%d]:0x%08x, off 0x%08x " -+ "kmap 0x%08x phys 0x%08x\n", -+ i, sg[i].page, sg[i].offset, -+ kmap(sg[i].page) + sg[i].offset, -+ sg[i].dma_address); -+#endif -+ c7108_aes_cipher(C7108_AES_DECRYPT, -+ sg[i].dma_address, -+ sg[i].dma_address, -+ sg_len, -+ crd->crd_klen, -+ c7108_crypto_mode, -+ hwkey, -+ ivp); -+ } -+ } -+ } break; -+ case SW_TYPE_HMAC: -+ case SW_TYPE_HASH: -+ crp->crp_etype = EINVAL; -+ goto done; -+ break; -+ -+ case SW_TYPE_COMP: -+ crp->crp_etype = EINVAL; -+ goto done; -+ break; -+ -+ default: -+ /* Unknown/unsupported algorithm */ -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ } -+ -+done: -+ crypto_done(crp); -+ return 0; -+} -+ -+static struct { -+ softc_device_decl sc_dev; -+} a7108dev; -+ -+static device_method_t a7108_methods = { -+/* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, c7108_newsession), -+ DEVMETHOD(cryptodev_freesession, c7108_freesession), -+ DEVMETHOD(cryptodev_process, c7108_process), -+ DEVMETHOD(cryptodev_kprocess, NULL) -+}; -+ -+static int -+cypher_7108_crypto_init(void) -+{ -+ dprintk("%s(%p)\n", __FUNCTION__, cypher_7108_crypto_init); -+ -+ iobar = (unsigned long)ioremap(CCU_AES_REG_BASE, 0x4000); -+ printk("7108: AES @ 0x%08x (0x%08x phys) %s mode\n", -+ iobar, CCU_AES_REG_BASE, -+ c7108_crypto_mode & C7108_AES_CTRL_MODE_CBC ? "CBC" : -+ c7108_crypto_mode & C7108_AES_CTRL_MODE_ECB ? "ECB" : -+ c7108_crypto_mode & C7108_AES_CTRL_MODE_CTR ? "CTR" : -+ c7108_crypto_mode & C7108_AES_CTRL_MODE_CFB ? "CFB" : -+ c7108_crypto_mode & C7108_AES_CTRL_MODE_OFB ? "OFB" : "???"); -+ csr_mutex = SPIN_LOCK_UNLOCKED; -+ -+ memset(&a7108dev, 0, sizeof(a7108dev)); -+ softc_device_init(&a7108dev, "aes7108", 0, a7108_methods); -+ -+ c7108_id = crypto_get_driverid(softc_get_device(&a7108dev), CRYPTOCAP_F_HARDWARE); -+ if (c7108_id < 0) -+ panic("7108: crypto device cannot initialize!"); -+ -+// crypto_register(c7108_id, CRYPTO_AES_CBC, 0, 0, c7108_newsession, c7108_freesession, c7108_process, NULL); -+ crypto_register(c7108_id, CRYPTO_AES_CBC, 0, 0); -+ -+ return(0); -+} -+ -+static void -+cypher_7108_crypto_exit(void) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ crypto_unregister_all(c7108_id); -+ c7108_id = -1; -+} -+ -+module_init(cypher_7108_crypto_init); -+module_exit(cypher_7108_crypto_exit); -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_DESCRIPTION("Cypher 7108 Crypto (OCF module for kernel crypto)"); -diff -Nur linux-2.6.36.orig/crypto/ocf/c7108/aes-7108.h linux-2.6.36/crypto/ocf/c7108/aes-7108.h ---- linux-2.6.36.orig/crypto/ocf/c7108/aes-7108.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/c7108/aes-7108.h 2010-11-09 20:28:04.102495305 +0100 -@@ -0,0 +1,134 @@ -+/* -+ * Copyright (C) 2006 Micronas USA -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored in part by the Defense Advanced Research Projects -+ * Agency (DARPA) and Air Force Research Laboratory, Air Force -+ * Materiel Command, USAF, under agreement number F30602-01-2-0537. -+ * -+ */ -+ -+#ifndef __AES_7108_H__ -+#define __AES_7108_H__ -+ -+/* Cypher 7108 AES Controller Hardware */ -+#define CCU_REG_BASE 0x1b500000 -+#define CCU_AES_REG_BASE (CCU_REG_BASE + 0x100) -+#define C7108_AES_KEY0_LO (0x0000) -+#define C7108_AES_KEY0_HI (0x0004) -+#define C7108_AES_KEY1_LO (0x0008) -+#define C7108_AES_KEY1_HI (0x000c) -+#define C7108_AES_KEY2_LO (0x0010) -+#define C7108_AES_KEY2_HI (0x0014) -+#define C7108_AES_KEY3_LO (0x0018) -+#define C7108_AES_KEY3_HI (0x001c) -+#define C7108_AES_KEY4_LO (0x0020) -+#define C7108_AES_KEY4_HI (0x0024) -+#define C7108_AES_KEY5_LO (0x0028) -+#define C7108_AES_KEY5_HI (0x002c) -+#define C7108_AES_KEY6_LO (0x0030) -+#define C7108_AES_KEY6_HI (0x0034) -+#define C7108_AES_KEY7_LO (0x0038) -+#define C7108_AES_KEY7_HI (0x003c) -+#define C7108_AES_IV0_LO (0x0040) -+#define C7108_AES_IV0_HI (0x0044) -+#define C7108_AES_IV1_LO (0x0048) -+#define C7108_AES_IV1_HI (0x004c) -+#define C7108_AES_IV2_LO (0x0050) -+#define C7108_AES_IV2_HI (0x0054) -+#define C7108_AES_IV3_LO (0x0058) -+#define C7108_AES_IV3_HI (0x005c) -+ -+#define C7108_AES_DMA_SRC0_LO (0x0068) /* Bits 0:15 */ -+#define C7108_AES_DMA_SRC0_HI (0x006c) /* Bits 27:16 */ -+#define C7108_AES_DMA_DST0_LO (0x0070) /* Bits 0:15 */ -+#define C7108_AES_DMA_DST0_HI (0x0074) /* Bits 27:16 */ -+#define C7108_AES_DMA_LEN (0x0078) /*Bytes:(Count+1)x16 */ -+ -+/* AES/Copy engine control register */ -+#define C7108_AES_CTRL (0x007c) /* AES control */ -+#define C7108_AES_CTRL_RS (1<<0) /* Which set of src/dst to use */ -+ -+/* AES Cipher mode, controlled by setting Bits 2:0 */ -+#define C7108_AES_CTRL_MODE_CBC 0 -+#define C7108_AES_CTRL_MODE_CFB (1<<0) -+#define C7108_AES_CTRL_MODE_OFB (1<<1) -+#define C7108_AES_CTRL_MODE_CTR ((1<<0)|(1<<1)) -+#define C7108_AES_CTRL_MODE_ECB (1<<2) -+ -+/* AES Key length , Bits 5:4 */ -+#define C7108_AES_KEY_LEN_128 0 /* 00 */ -+#define C7108_AES_KEY_LEN_192 (1<<4) /* 01 */ -+#define C7108_AES_KEY_LEN_256 (1<<5) /* 10 */ -+ -+/* AES Operation (crypt/decrypt), Bit 3 */ -+#define C7108_AES_DECRYPT (1<<3) /* Clear for encrypt */ -+#define C7108_AES_ENCRYPT 0 -+#define C7108_AES_INTR (1<<13) /* Set on done trans from 0->1*/ -+#define C7108_AES_GO (1<<14) /* Run */ -+#define C7108_AES_OP_DONE (1<<15) /* Set when complete */ -+ -+ -+/* Expanded key registers */ -+#define C7108_AES_EKEY0_LO (0x0080) -+#define C7108_AES_EKEY0_HI (0x0084) -+#define C7108_AES_EKEY1_LO (0x0088) -+#define C7108_AES_EKEY1_HI (0x008c) -+#define C7108_AES_EKEY2_LO (0x0090) -+#define C7108_AES_EKEY2_HI (0x0094) -+#define C7108_AES_EKEY3_LO (0x0098) -+#define C7108_AES_EKEY3_HI (0x009c) -+#define C7108_AES_EKEY4_LO (0x00a0) -+#define C7108_AES_EKEY4_HI (0x00a4) -+#define C7108_AES_EKEY5_LO (0x00a8) -+#define C7108_AES_EKEY5_HI (0x00ac) -+#define C7108_AES_EKEY6_LO (0x00b0) -+#define C7108_AES_EKEY6_HI (0x00b4) -+#define C7108_AES_EKEY7_LO (0x00b8) -+#define C7108_AES_EKEY7_HI (0x00bc) -+#define C7108_AES_OK (0x00fc) /* Reset: "OK" */ -+ -+#define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK) -+ -+/* Software session entry */ -+ -+#define HW_TYPE_CIPHER 0 -+#define SW_TYPE_HMAC 1 -+#define SW_TYPE_AUTH2 2 -+#define SW_TYPE_HASH 3 -+#define SW_TYPE_COMP 4 -+ -+struct cipher_7108 { -+ int xfm_type; -+ int cri_alg; -+ union { -+ struct { -+ char sw_key[HMAC_BLOCK_LEN]; -+ int sw_klen; -+ int sw_authlen; -+ } hmac; -+ } u; -+ struct cipher_7108 *next; -+}; -+ -+ -+ -+#endif /* __C7108_AES_7108_H__ */ -diff -Nur linux-2.6.36.orig/crypto/ocf/c7108/Makefile linux-2.6.36/crypto/ocf/c7108/Makefile ---- linux-2.6.36.orig/crypto/ocf/c7108/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/c7108/Makefile 2010-11-09 20:28:04.152495478 +0100 -@@ -0,0 +1,12 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+obj-$(CONFIG_OCF_C7108) += aes-7108.o -+ -+obj ?= . -+EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/Config.in linux-2.6.36/crypto/ocf/Config.in ---- linux-2.6.36.orig/crypto/ocf/Config.in 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/Config.in 2010-11-09 20:28:04.191247583 +0100 -@@ -0,0 +1,36 @@ -+############################################################################# -+ -+mainmenu_option next_comment -+comment 'OCF Configuration' -+tristate 'OCF (Open Cryptograhic Framework)' CONFIG_OCF_OCF -+dep_mbool ' enable fips RNG checks (fips check on RNG data before use)' \ -+ CONFIG_OCF_FIPS $CONFIG_OCF_OCF -+dep_mbool ' enable harvesting entropy for /dev/random' \ -+ CONFIG_OCF_RANDOMHARVEST $CONFIG_OCF_OCF -+dep_tristate ' cryptodev (user space support)' \ -+ CONFIG_OCF_CRYPTODEV $CONFIG_OCF_OCF -+dep_tristate ' cryptosoft (software crypto engine)' \ -+ CONFIG_OCF_CRYPTOSOFT $CONFIG_OCF_OCF -+dep_tristate ' safenet (HW crypto engine)' \ -+ CONFIG_OCF_SAFE $CONFIG_OCF_OCF -+dep_tristate ' IXP4xx (HW crypto engine)' \ -+ CONFIG_OCF_IXP4XX $CONFIG_OCF_OCF -+dep_mbool ' Enable IXP4xx HW to perform SHA1 and MD5 hashing (very slow)' \ -+ CONFIG_OCF_IXP4XX_SHA1_MD5 $CONFIG_OCF_IXP4XX -+dep_tristate ' hifn (HW crypto engine)' \ -+ CONFIG_OCF_HIFN $CONFIG_OCF_OCF -+dep_tristate ' talitos (HW crypto engine)' \ -+ CONFIG_OCF_TALITOS $CONFIG_OCF_OCF -+dep_tristate ' pasemi (HW crypto engine)' \ -+ CONFIG_OCF_PASEMI $CONFIG_OCF_OCF -+dep_tristate ' ep80579 (HW crypto engine)' \ -+ CONFIG_OCF_EP80579 $CONFIG_OCF_OCF -+dep_tristate ' Micronas c7108 (HW crypto engine)' \ -+ CONFIG_OCF_C7108 $CONFIG_OCF_OCF -+dep_tristate ' ocfnull (does no crypto)' \ -+ CONFIG_OCF_OCFNULL $CONFIG_OCF_OCF -+dep_tristate ' ocf-bench (HW crypto in-kernel benchmark)' \ -+ CONFIG_OCF_BENCH $CONFIG_OCF_OCF -+endmenu -+ -+############################################################################# -diff -Nur linux-2.6.36.orig/crypto/ocf/criov.c linux-2.6.36/crypto/ocf/criov.c ---- linux-2.6.36.orig/crypto/ocf/criov.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/criov.c 2010-11-09 20:28:04.232050075 +0100 -@@ -0,0 +1,215 @@ -+/* $OpenBSD: criov.c,v 1.9 2002/01/29 15:48:29 jason Exp $ */ -+ -+/* -+ * Linux port done by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * The license and original author are listed below. -+ * -+ * Copyright (c) 1999 Theo de Raadt -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+__FBSDID("$FreeBSD: src/sys/opencrypto/criov.c,v 1.5 2006/06/04 22:15:13 pjd Exp $"); -+ */ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+/* -+ * This macro is only for avoiding code duplication, as we need to skip -+ * given number of bytes in the same way in three functions below. -+ */ -+#define CUIO_SKIP() do { \ -+ KASSERT(off >= 0, ("%s: off %d < 0", __func__, off)); \ -+ KASSERT(len >= 0, ("%s: len %d < 0", __func__, len)); \ -+ while (off > 0) { \ -+ KASSERT(iol >= 0, ("%s: empty in skip", __func__)); \ -+ if (off < iov->iov_len) \ -+ break; \ -+ off -= iov->iov_len; \ -+ iol--; \ -+ iov++; \ -+ } \ -+} while (0) -+ -+void -+cuio_copydata(struct uio* uio, int off, int len, caddr_t cp) -+{ -+ struct iovec *iov = uio->uio_iov; -+ int iol = uio->uio_iovcnt; -+ unsigned count; -+ -+ CUIO_SKIP(); -+ while (len > 0) { -+ KASSERT(iol >= 0, ("%s: empty", __func__)); -+ count = min((int)(iov->iov_len - off), len); -+ memcpy(cp, ((caddr_t)iov->iov_base) + off, count); -+ len -= count; -+ cp += count; -+ off = 0; -+ iol--; -+ iov++; -+ } -+} -+ -+void -+cuio_copyback(struct uio* uio, int off, int len, caddr_t cp) -+{ -+ struct iovec *iov = uio->uio_iov; -+ int iol = uio->uio_iovcnt; -+ unsigned count; -+ -+ CUIO_SKIP(); -+ while (len > 0) { -+ KASSERT(iol >= 0, ("%s: empty", __func__)); -+ count = min((int)(iov->iov_len - off), len); -+ memcpy(((caddr_t)iov->iov_base) + off, cp, count); -+ len -= count; -+ cp += count; -+ off = 0; -+ iol--; -+ iov++; -+ } -+} -+ -+/* -+ * Return a pointer to iov/offset of location in iovec list. -+ */ -+struct iovec * -+cuio_getptr(struct uio *uio, int loc, int *off) -+{ -+ struct iovec *iov = uio->uio_iov; -+ int iol = uio->uio_iovcnt; -+ -+ while (loc >= 0) { -+ /* Normal end of search */ -+ if (loc < iov->iov_len) { -+ *off = loc; -+ return (iov); -+ } -+ -+ loc -= iov->iov_len; -+ if (iol == 0) { -+ if (loc == 0) { -+ /* Point at the end of valid data */ -+ *off = iov->iov_len; -+ return (iov); -+ } else -+ return (NULL); -+ } else { -+ iov++, iol--; -+ } -+ } -+ -+ return (NULL); -+} -+ -+EXPORT_SYMBOL(cuio_copyback); -+EXPORT_SYMBOL(cuio_copydata); -+EXPORT_SYMBOL(cuio_getptr); -+ -+ -+static void -+skb_copy_bits_back(struct sk_buff *skb, int offset, caddr_t cp, int len) -+{ -+ int i; -+ if (offset < skb_headlen(skb)) { -+ memcpy(skb->data + offset, cp, min_t(int, skb_headlen(skb), len)); -+ len -= skb_headlen(skb); -+ cp += skb_headlen(skb); -+ } -+ offset -= skb_headlen(skb); -+ for (i = 0; len > 0 && i < skb_shinfo(skb)->nr_frags; i++) { -+ if (offset < skb_shinfo(skb)->frags[i].size) { -+ memcpy(page_address(skb_shinfo(skb)->frags[i].page) + -+ skb_shinfo(skb)->frags[i].page_offset, -+ cp, min_t(int, skb_shinfo(skb)->frags[i].size, len)); -+ len -= skb_shinfo(skb)->frags[i].size; -+ cp += skb_shinfo(skb)->frags[i].size; -+ } -+ offset -= skb_shinfo(skb)->frags[i].size; -+ } -+} -+ -+void -+crypto_copyback(int flags, caddr_t buf, int off, int size, caddr_t in) -+{ -+ -+ if ((flags & CRYPTO_F_SKBUF) != 0) -+ skb_copy_bits_back((struct sk_buff *)buf, off, in, size); -+ else if ((flags & CRYPTO_F_IOV) != 0) -+ cuio_copyback((struct uio *)buf, off, size, in); -+ else -+ bcopy(in, buf + off, size); -+} -+ -+void -+crypto_copydata(int flags, caddr_t buf, int off, int size, caddr_t out) -+{ -+ -+ if ((flags & CRYPTO_F_SKBUF) != 0) -+ skb_copy_bits((struct sk_buff *)buf, off, out, size); -+ else if ((flags & CRYPTO_F_IOV) != 0) -+ cuio_copydata((struct uio *)buf, off, size, out); -+ else -+ bcopy(buf + off, out, size); -+} -+ -+int -+crypto_apply(int flags, caddr_t buf, int off, int len, -+ int (*f)(void *, void *, u_int), void *arg) -+{ -+#if 0 -+ int error; -+ -+ if ((flags & CRYPTO_F_SKBUF) != 0) -+ error = XXXXXX((struct mbuf *)buf, off, len, f, arg); -+ else if ((flags & CRYPTO_F_IOV) != 0) -+ error = cuio_apply((struct uio *)buf, off, len, f, arg); -+ else -+ error = (*f)(arg, buf + off, len); -+ return (error); -+#else -+ KASSERT(0, ("crypto_apply not implemented!\n")); -+#endif -+ return 0; -+} -+ -+EXPORT_SYMBOL(crypto_copyback); -+EXPORT_SYMBOL(crypto_copydata); -+EXPORT_SYMBOL(crypto_apply); -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/crypto.c linux-2.6.36/crypto/ocf/crypto.c ---- linux-2.6.36.orig/crypto/ocf/crypto.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/crypto.c 2010-11-09 20:28:04.272495385 +0100 -@@ -0,0 +1,1784 @@ -+/*- -+ * Linux port done by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * The license and original author are listed below. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * Copyright (c) 2002-2006 Sam Leffler. All rights reserved. -+ * -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#if 0 -+#include -+__FBSDID("$FreeBSD: src/sys/opencrypto/crypto.c,v 1.27 2007/03/21 03:42:51 sam Exp $"); -+#endif -+ -+/* -+ * Cryptographic Subsystem. -+ * -+ * This code is derived from the Openbsd Cryptographic Framework (OCF) -+ * that has the copyright shown below. Very little of the original -+ * code remains. -+ */ -+/*- -+ * The author of this code is Angelos D. Keromytis (angelos@cis.upenn.edu) -+ * -+ * This code was written by Angelos D. Keromytis in Athens, Greece, in -+ * February 2000. Network Security Technologies Inc. (NSTI) kindly -+ * supported the development of this code. -+ * -+ * Copyright (c) 2000, 2001 Angelos D. Keromytis -+ * -+ * Permission to use, copy, and modify this software with or without fee -+ * is hereby granted, provided that this entire notice is included in -+ * all source code copies of any software which is or includes a copy or -+ * modification of this software. -+ * -+ * THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR -+ * IMPLIED WARRANTY. IN PARTICULAR, NONE OF THE AUTHORS MAKES ANY -+ * REPRESENTATION OR WARRANTY OF ANY KIND CONCERNING THE -+ * MERCHANTABILITY OF THIS SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR -+ * PURPOSE. -+ * -+__FBSDID("$FreeBSD: src/sys/opencrypto/crypto.c,v 1.16 2005/01/07 02:29:16 imp Exp $"); -+ */ -+ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* -+ * keep track of whether or not we have been initialised, a big -+ * issue if we are linked into the kernel and a driver gets started before -+ * us -+ */ -+static int crypto_initted = 0; -+ -+/* -+ * Crypto drivers register themselves by allocating a slot in the -+ * crypto_drivers table with crypto_get_driverid() and then registering -+ * each algorithm they support with crypto_register() and crypto_kregister(). -+ */ -+ -+/* -+ * lock on driver table -+ * we track its state as spin_is_locked does not do anything on non-SMP boxes -+ */ -+static spinlock_t crypto_drivers_lock; -+static int crypto_drivers_locked; /* for non-SMP boxes */ -+ -+#define CRYPTO_DRIVER_LOCK() \ -+ ({ \ -+ spin_lock_irqsave(&crypto_drivers_lock, d_flags); \ -+ crypto_drivers_locked = 1; \ -+ dprintk("%s,%d: DRIVER_LOCK()\n", __FILE__, __LINE__); \ -+ }) -+#define CRYPTO_DRIVER_UNLOCK() \ -+ ({ \ -+ dprintk("%s,%d: DRIVER_UNLOCK()\n", __FILE__, __LINE__); \ -+ crypto_drivers_locked = 0; \ -+ spin_unlock_irqrestore(&crypto_drivers_lock, d_flags); \ -+ }) -+#define CRYPTO_DRIVER_ASSERT() \ -+ ({ \ -+ if (!crypto_drivers_locked) { \ -+ dprintk("%s,%d: DRIVER_ASSERT!\n", __FILE__, __LINE__); \ -+ } \ -+ }) -+ -+/* -+ * Crypto device/driver capabilities structure. -+ * -+ * Synchronization: -+ * (d) - protected by CRYPTO_DRIVER_LOCK() -+ * (q) - protected by CRYPTO_Q_LOCK() -+ * Not tagged fields are read-only. -+ */ -+struct cryptocap { -+ device_t cc_dev; /* (d) device/driver */ -+ u_int32_t cc_sessions; /* (d) # of sessions */ -+ u_int32_t cc_koperations; /* (d) # os asym operations */ -+ /* -+ * Largest possible operator length (in bits) for each type of -+ * encryption algorithm. XXX not used -+ */ -+ u_int16_t cc_max_op_len[CRYPTO_ALGORITHM_MAX + 1]; -+ u_int8_t cc_alg[CRYPTO_ALGORITHM_MAX + 1]; -+ u_int8_t cc_kalg[CRK_ALGORITHM_MAX + 1]; -+ -+ int cc_flags; /* (d) flags */ -+#define CRYPTOCAP_F_CLEANUP 0x80000000 /* needs resource cleanup */ -+ int cc_qblocked; /* (q) symmetric q blocked */ -+ int cc_kqblocked; /* (q) asymmetric q blocked */ -+ -+ int cc_unqblocked; /* (q) symmetric q blocked */ -+ int cc_unkqblocked; /* (q) asymmetric q blocked */ -+}; -+static struct cryptocap *crypto_drivers = NULL; -+static int crypto_drivers_num = 0; -+ -+/* -+ * There are two queues for crypto requests; one for symmetric (e.g. -+ * cipher) operations and one for asymmetric (e.g. MOD)operations. -+ * A single mutex is used to lock access to both queues. We could -+ * have one per-queue but having one simplifies handling of block/unblock -+ * operations. -+ */ -+static int crp_sleep = 0; -+static LIST_HEAD(crp_q); /* request queues */ -+static LIST_HEAD(crp_kq); -+ -+static spinlock_t crypto_q_lock; -+ -+int crypto_all_qblocked = 0; /* protect with Q_LOCK */ -+module_param(crypto_all_qblocked, int, 0444); -+MODULE_PARM_DESC(crypto_all_qblocked, "Are all crypto queues blocked"); -+ -+int crypto_all_kqblocked = 0; /* protect with Q_LOCK */ -+module_param(crypto_all_kqblocked, int, 0444); -+MODULE_PARM_DESC(crypto_all_kqblocked, "Are all asym crypto queues blocked"); -+ -+#define CRYPTO_Q_LOCK() \ -+ ({ \ -+ spin_lock_irqsave(&crypto_q_lock, q_flags); \ -+ dprintk("%s,%d: Q_LOCK()\n", __FILE__, __LINE__); \ -+ }) -+#define CRYPTO_Q_UNLOCK() \ -+ ({ \ -+ dprintk("%s,%d: Q_UNLOCK()\n", __FILE__, __LINE__); \ -+ spin_unlock_irqrestore(&crypto_q_lock, q_flags); \ -+ }) -+ -+/* -+ * There are two queues for processing completed crypto requests; one -+ * for the symmetric and one for the asymmetric ops. We only need one -+ * but have two to avoid type futzing (cryptop vs. cryptkop). A single -+ * mutex is used to lock access to both queues. Note that this lock -+ * must be separate from the lock on request queues to insure driver -+ * callbacks don't generate lock order reversals. -+ */ -+static LIST_HEAD(crp_ret_q); /* callback queues */ -+static LIST_HEAD(crp_ret_kq); -+ -+static spinlock_t crypto_ret_q_lock; -+#define CRYPTO_RETQ_LOCK() \ -+ ({ \ -+ spin_lock_irqsave(&crypto_ret_q_lock, r_flags); \ -+ dprintk("%s,%d: RETQ_LOCK\n", __FILE__, __LINE__); \ -+ }) -+#define CRYPTO_RETQ_UNLOCK() \ -+ ({ \ -+ dprintk("%s,%d: RETQ_UNLOCK\n", __FILE__, __LINE__); \ -+ spin_unlock_irqrestore(&crypto_ret_q_lock, r_flags); \ -+ }) -+#define CRYPTO_RETQ_EMPTY() (list_empty(&crp_ret_q) && list_empty(&crp_ret_kq)) -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) -+static kmem_cache_t *cryptop_zone; -+static kmem_cache_t *cryptodesc_zone; -+#else -+static struct kmem_cache *cryptop_zone; -+static struct kmem_cache *cryptodesc_zone; -+#endif -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) -+#include -+#define kill_proc(p,s,v) send_sig(s,find_task_by_vpid(p),0) -+#endif -+ -+#define debug crypto_debug -+int crypto_debug = 0; -+module_param(crypto_debug, int, 0644); -+MODULE_PARM_DESC(crypto_debug, "Enable debug"); -+EXPORT_SYMBOL(crypto_debug); -+ -+/* -+ * Maximum number of outstanding crypto requests before we start -+ * failing requests. We need this to prevent DOS when too many -+ * requests are arriving for us to keep up. Otherwise we will -+ * run the system out of memory. Since crypto is slow, we are -+ * usually the bottleneck that needs to say, enough is enough. -+ * -+ * We cannot print errors when this condition occurs, we are already too -+ * slow, printing anything will just kill us -+ */ -+ -+static int crypto_q_cnt = 0; -+module_param(crypto_q_cnt, int, 0444); -+MODULE_PARM_DESC(crypto_q_cnt, -+ "Current number of outstanding crypto requests"); -+ -+static int crypto_q_max = 1000; -+module_param(crypto_q_max, int, 0644); -+MODULE_PARM_DESC(crypto_q_max, -+ "Maximum number of outstanding crypto requests"); -+ -+#define bootverbose crypto_verbose -+static int crypto_verbose = 0; -+module_param(crypto_verbose, int, 0644); -+MODULE_PARM_DESC(crypto_verbose, -+ "Enable verbose crypto startup"); -+ -+int crypto_usercrypto = 1; /* userland may do crypto reqs */ -+module_param(crypto_usercrypto, int, 0644); -+MODULE_PARM_DESC(crypto_usercrypto, -+ "Enable/disable user-mode access to crypto support"); -+ -+int crypto_userasymcrypto = 1; /* userland may do asym crypto reqs */ -+module_param(crypto_userasymcrypto, int, 0644); -+MODULE_PARM_DESC(crypto_userasymcrypto, -+ "Enable/disable user-mode access to asymmetric crypto support"); -+ -+int crypto_devallowsoft = 0; /* only use hardware crypto */ -+module_param(crypto_devallowsoft, int, 0644); -+MODULE_PARM_DESC(crypto_devallowsoft, -+ "Enable/disable use of software crypto support"); -+ -+/* -+ * This parameter controls the maximum number of crypto operations to -+ * do consecutively in the crypto kernel thread before scheduling to allow -+ * other processes to run. Without it, it is possible to get into a -+ * situation where the crypto thread never allows any other processes to run. -+ * Default to 1000 which should be less than one second. -+ */ -+static int crypto_max_loopcount = 1000; -+module_param(crypto_max_loopcount, int, 0644); -+MODULE_PARM_DESC(crypto_max_loopcount, -+ "Maximum number of crypto ops to do before yielding to other processes"); -+ -+static pid_t cryptoproc = (pid_t) -1; -+static struct completion cryptoproc_exited; -+static DECLARE_WAIT_QUEUE_HEAD(cryptoproc_wait); -+static pid_t cryptoretproc = (pid_t) -1; -+static struct completion cryptoretproc_exited; -+static DECLARE_WAIT_QUEUE_HEAD(cryptoretproc_wait); -+ -+static int crypto_proc(void *arg); -+static int crypto_ret_proc(void *arg); -+static int crypto_invoke(struct cryptocap *cap, struct cryptop *crp, int hint); -+static int crypto_kinvoke(struct cryptkop *krp, int flags); -+static void crypto_exit(void); -+static int crypto_init(void); -+ -+static struct cryptostats cryptostats; -+ -+static struct cryptocap * -+crypto_checkdriver(u_int32_t hid) -+{ -+ if (crypto_drivers == NULL) -+ return NULL; -+ return (hid >= crypto_drivers_num ? NULL : &crypto_drivers[hid]); -+} -+ -+/* -+ * Compare a driver's list of supported algorithms against another -+ * list; return non-zero if all algorithms are supported. -+ */ -+static int -+driver_suitable(const struct cryptocap *cap, const struct cryptoini *cri) -+{ -+ const struct cryptoini *cr; -+ -+ /* See if all the algorithms are supported. */ -+ for (cr = cri; cr; cr = cr->cri_next) -+ if (cap->cc_alg[cr->cri_alg] == 0) -+ return 0; -+ return 1; -+} -+ -+/* -+ * Select a driver for a new session that supports the specified -+ * algorithms and, optionally, is constrained according to the flags. -+ * The algorithm we use here is pretty stupid; just use the -+ * first driver that supports all the algorithms we need. If there -+ * are multiple drivers we choose the driver with the fewest active -+ * sessions. We prefer hardware-backed drivers to software ones. -+ * -+ * XXX We need more smarts here (in real life too, but that's -+ * XXX another story altogether). -+ */ -+static struct cryptocap * -+crypto_select_driver(const struct cryptoini *cri, int flags) -+{ -+ struct cryptocap *cap, *best; -+ int match, hid; -+ -+ CRYPTO_DRIVER_ASSERT(); -+ -+ /* -+ * Look first for hardware crypto devices if permitted. -+ */ -+ if (flags & CRYPTOCAP_F_HARDWARE) -+ match = CRYPTOCAP_F_HARDWARE; -+ else -+ match = CRYPTOCAP_F_SOFTWARE; -+ best = NULL; -+again: -+ for (hid = 0; hid < crypto_drivers_num; hid++) { -+ cap = &crypto_drivers[hid]; -+ /* -+ * If it's not initialized, is in the process of -+ * going away, or is not appropriate (hardware -+ * or software based on match), then skip. -+ */ -+ if (cap->cc_dev == NULL || -+ (cap->cc_flags & CRYPTOCAP_F_CLEANUP) || -+ (cap->cc_flags & match) == 0) -+ continue; -+ -+ /* verify all the algorithms are supported. */ -+ if (driver_suitable(cap, cri)) { -+ if (best == NULL || -+ cap->cc_sessions < best->cc_sessions) -+ best = cap; -+ } -+ } -+ if (best != NULL) -+ return best; -+ if (match == CRYPTOCAP_F_HARDWARE && (flags & CRYPTOCAP_F_SOFTWARE)) { -+ /* sort of an Algol 68-style for loop */ -+ match = CRYPTOCAP_F_SOFTWARE; -+ goto again; -+ } -+ return best; -+} -+ -+/* -+ * Create a new session. The crid argument specifies a crypto -+ * driver to use or constraints on a driver to select (hardware -+ * only, software only, either). Whatever driver is selected -+ * must be capable of the requested crypto algorithms. -+ */ -+int -+crypto_newsession(u_int64_t *sid, struct cryptoini *cri, int crid) -+{ -+ struct cryptocap *cap; -+ u_int32_t hid, lid; -+ int err; -+ unsigned long d_flags; -+ -+ CRYPTO_DRIVER_LOCK(); -+ if ((crid & (CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE)) == 0) { -+ /* -+ * Use specified driver; verify it is capable. -+ */ -+ cap = crypto_checkdriver(crid); -+ if (cap != NULL && !driver_suitable(cap, cri)) -+ cap = NULL; -+ } else { -+ /* -+ * No requested driver; select based on crid flags. -+ */ -+ cap = crypto_select_driver(cri, crid); -+ /* -+ * if NULL then can't do everything in one session. -+ * XXX Fix this. We need to inject a "virtual" session -+ * XXX layer right about here. -+ */ -+ } -+ if (cap != NULL) { -+ /* Call the driver initialization routine. */ -+ hid = cap - crypto_drivers; -+ lid = hid; /* Pass the driver ID. */ -+ cap->cc_sessions++; -+ CRYPTO_DRIVER_UNLOCK(); -+ err = CRYPTODEV_NEWSESSION(cap->cc_dev, &lid, cri); -+ CRYPTO_DRIVER_LOCK(); -+ if (err == 0) { -+ (*sid) = (cap->cc_flags & 0xff000000) -+ | (hid & 0x00ffffff); -+ (*sid) <<= 32; -+ (*sid) |= (lid & 0xffffffff); -+ } else -+ cap->cc_sessions--; -+ } else -+ err = EINVAL; -+ CRYPTO_DRIVER_UNLOCK(); -+ return err; -+} -+ -+static void -+crypto_remove(struct cryptocap *cap) -+{ -+ CRYPTO_DRIVER_ASSERT(); -+ if (cap->cc_sessions == 0 && cap->cc_koperations == 0) -+ bzero(cap, sizeof(*cap)); -+} -+ -+/* -+ * Delete an existing session (or a reserved session on an unregistered -+ * driver). -+ */ -+int -+crypto_freesession(u_int64_t sid) -+{ -+ struct cryptocap *cap; -+ u_int32_t hid; -+ int err = 0; -+ unsigned long d_flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ CRYPTO_DRIVER_LOCK(); -+ -+ if (crypto_drivers == NULL) { -+ err = EINVAL; -+ goto done; -+ } -+ -+ /* Determine two IDs. */ -+ hid = CRYPTO_SESID2HID(sid); -+ -+ if (hid >= crypto_drivers_num) { -+ dprintk("%s - INVALID DRIVER NUM %d\n", __FUNCTION__, hid); -+ err = ENOENT; -+ goto done; -+ } -+ cap = &crypto_drivers[hid]; -+ -+ if (cap->cc_dev) { -+ CRYPTO_DRIVER_UNLOCK(); -+ /* Call the driver cleanup routine, if available, unlocked. */ -+ err = CRYPTODEV_FREESESSION(cap->cc_dev, sid); -+ CRYPTO_DRIVER_LOCK(); -+ } -+ -+ if (cap->cc_sessions) -+ cap->cc_sessions--; -+ -+ if (cap->cc_flags & CRYPTOCAP_F_CLEANUP) -+ crypto_remove(cap); -+ -+done: -+ CRYPTO_DRIVER_UNLOCK(); -+ return err; -+} -+ -+/* -+ * Return an unused driver id. Used by drivers prior to registering -+ * support for the algorithms they handle. -+ */ -+int32_t -+crypto_get_driverid(device_t dev, int flags) -+{ -+ struct cryptocap *newdrv; -+ int i; -+ unsigned long d_flags; -+ -+ if ((flags & (CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE)) == 0) { -+ printf("%s: no flags specified when registering driver\n", -+ device_get_nameunit(dev)); -+ return -1; -+ } -+ -+ CRYPTO_DRIVER_LOCK(); -+ -+ for (i = 0; i < crypto_drivers_num; i++) { -+ if (crypto_drivers[i].cc_dev == NULL && -+ (crypto_drivers[i].cc_flags & CRYPTOCAP_F_CLEANUP) == 0) { -+ break; -+ } -+ } -+ -+ /* Out of entries, allocate some more. */ -+ if (i == crypto_drivers_num) { -+ /* Be careful about wrap-around. */ -+ if (2 * crypto_drivers_num <= crypto_drivers_num) { -+ CRYPTO_DRIVER_UNLOCK(); -+ printk("crypto: driver count wraparound!\n"); -+ return -1; -+ } -+ -+ newdrv = kmalloc(2 * crypto_drivers_num * sizeof(struct cryptocap), -+ GFP_KERNEL); -+ if (newdrv == NULL) { -+ CRYPTO_DRIVER_UNLOCK(); -+ printk("crypto: no space to expand driver table!\n"); -+ return -1; -+ } -+ -+ memcpy(newdrv, crypto_drivers, -+ crypto_drivers_num * sizeof(struct cryptocap)); -+ memset(&newdrv[crypto_drivers_num], 0, -+ crypto_drivers_num * sizeof(struct cryptocap)); -+ -+ crypto_drivers_num *= 2; -+ -+ kfree(crypto_drivers); -+ crypto_drivers = newdrv; -+ } -+ -+ /* NB: state is zero'd on free */ -+ crypto_drivers[i].cc_sessions = 1; /* Mark */ -+ crypto_drivers[i].cc_dev = dev; -+ crypto_drivers[i].cc_flags = flags; -+ if (bootverbose) -+ printf("crypto: assign %s driver id %u, flags %u\n", -+ device_get_nameunit(dev), i, flags); -+ -+ CRYPTO_DRIVER_UNLOCK(); -+ -+ return i; -+} -+ -+/* -+ * Lookup a driver by name. We match against the full device -+ * name and unit, and against just the name. The latter gives -+ * us a simple widlcarding by device name. On success return the -+ * driver/hardware identifier; otherwise return -1. -+ */ -+int -+crypto_find_driver(const char *match) -+{ -+ int i, len = strlen(match); -+ unsigned long d_flags; -+ -+ CRYPTO_DRIVER_LOCK(); -+ for (i = 0; i < crypto_drivers_num; i++) { -+ device_t dev = crypto_drivers[i].cc_dev; -+ if (dev == NULL || -+ (crypto_drivers[i].cc_flags & CRYPTOCAP_F_CLEANUP)) -+ continue; -+ if (strncmp(match, device_get_nameunit(dev), len) == 0 || -+ strncmp(match, device_get_name(dev), len) == 0) -+ break; -+ } -+ CRYPTO_DRIVER_UNLOCK(); -+ return i < crypto_drivers_num ? i : -1; -+} -+ -+/* -+ * Return the device_t for the specified driver or NULL -+ * if the driver identifier is invalid. -+ */ -+device_t -+crypto_find_device_byhid(int hid) -+{ -+ struct cryptocap *cap = crypto_checkdriver(hid); -+ return cap != NULL ? cap->cc_dev : NULL; -+} -+ -+/* -+ * Return the device/driver capabilities. -+ */ -+int -+crypto_getcaps(int hid) -+{ -+ struct cryptocap *cap = crypto_checkdriver(hid); -+ return cap != NULL ? cap->cc_flags : 0; -+} -+ -+/* -+ * Register support for a key-related algorithm. This routine -+ * is called once for each algorithm supported a driver. -+ */ -+int -+crypto_kregister(u_int32_t driverid, int kalg, u_int32_t flags) -+{ -+ struct cryptocap *cap; -+ int err; -+ unsigned long d_flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ CRYPTO_DRIVER_LOCK(); -+ -+ cap = crypto_checkdriver(driverid); -+ if (cap != NULL && -+ (CRK_ALGORITM_MIN <= kalg && kalg <= CRK_ALGORITHM_MAX)) { -+ /* -+ * XXX Do some performance testing to determine placing. -+ * XXX We probably need an auxiliary data structure that -+ * XXX describes relative performances. -+ */ -+ -+ cap->cc_kalg[kalg] = flags | CRYPTO_ALG_FLAG_SUPPORTED; -+ if (bootverbose) -+ printf("crypto: %s registers key alg %u flags %u\n" -+ , device_get_nameunit(cap->cc_dev) -+ , kalg -+ , flags -+ ); -+ err = 0; -+ } else -+ err = EINVAL; -+ -+ CRYPTO_DRIVER_UNLOCK(); -+ return err; -+} -+ -+/* -+ * Register support for a non-key-related algorithm. This routine -+ * is called once for each such algorithm supported by a driver. -+ */ -+int -+crypto_register(u_int32_t driverid, int alg, u_int16_t maxoplen, -+ u_int32_t flags) -+{ -+ struct cryptocap *cap; -+ int err; -+ unsigned long d_flags; -+ -+ dprintk("%s(id=0x%x, alg=%d, maxoplen=%d, flags=0x%x)\n", __FUNCTION__, -+ driverid, alg, maxoplen, flags); -+ -+ CRYPTO_DRIVER_LOCK(); -+ -+ cap = crypto_checkdriver(driverid); -+ /* NB: algorithms are in the range [1..max] */ -+ if (cap != NULL && -+ (CRYPTO_ALGORITHM_MIN <= alg && alg <= CRYPTO_ALGORITHM_MAX)) { -+ /* -+ * XXX Do some performance testing to determine placing. -+ * XXX We probably need an auxiliary data structure that -+ * XXX describes relative performances. -+ */ -+ -+ cap->cc_alg[alg] = flags | CRYPTO_ALG_FLAG_SUPPORTED; -+ cap->cc_max_op_len[alg] = maxoplen; -+ if (bootverbose) -+ printf("crypto: %s registers alg %u flags %u maxoplen %u\n" -+ , device_get_nameunit(cap->cc_dev) -+ , alg -+ , flags -+ , maxoplen -+ ); -+ cap->cc_sessions = 0; /* Unmark */ -+ err = 0; -+ } else -+ err = EINVAL; -+ -+ CRYPTO_DRIVER_UNLOCK(); -+ return err; -+} -+ -+static void -+driver_finis(struct cryptocap *cap) -+{ -+ u_int32_t ses, kops; -+ -+ CRYPTO_DRIVER_ASSERT(); -+ -+ ses = cap->cc_sessions; -+ kops = cap->cc_koperations; -+ bzero(cap, sizeof(*cap)); -+ if (ses != 0 || kops != 0) { -+ /* -+ * If there are pending sessions, -+ * just mark as invalid. -+ */ -+ cap->cc_flags |= CRYPTOCAP_F_CLEANUP; -+ cap->cc_sessions = ses; -+ cap->cc_koperations = kops; -+ } -+} -+ -+/* -+ * Unregister a crypto driver. If there are pending sessions using it, -+ * leave enough information around so that subsequent calls using those -+ * sessions will correctly detect the driver has been unregistered and -+ * reroute requests. -+ */ -+int -+crypto_unregister(u_int32_t driverid, int alg) -+{ -+ struct cryptocap *cap; -+ int i, err; -+ unsigned long d_flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ CRYPTO_DRIVER_LOCK(); -+ -+ cap = crypto_checkdriver(driverid); -+ if (cap != NULL && -+ (CRYPTO_ALGORITHM_MIN <= alg && alg <= CRYPTO_ALGORITHM_MAX) && -+ cap->cc_alg[alg] != 0) { -+ cap->cc_alg[alg] = 0; -+ cap->cc_max_op_len[alg] = 0; -+ -+ /* Was this the last algorithm ? */ -+ for (i = 1; i <= CRYPTO_ALGORITHM_MAX; i++) -+ if (cap->cc_alg[i] != 0) -+ break; -+ -+ if (i == CRYPTO_ALGORITHM_MAX + 1) -+ driver_finis(cap); -+ err = 0; -+ } else -+ err = EINVAL; -+ CRYPTO_DRIVER_UNLOCK(); -+ return err; -+} -+ -+/* -+ * Unregister all algorithms associated with a crypto driver. -+ * If there are pending sessions using it, leave enough information -+ * around so that subsequent calls using those sessions will -+ * correctly detect the driver has been unregistered and reroute -+ * requests. -+ */ -+int -+crypto_unregister_all(u_int32_t driverid) -+{ -+ struct cryptocap *cap; -+ int err; -+ unsigned long d_flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ CRYPTO_DRIVER_LOCK(); -+ cap = crypto_checkdriver(driverid); -+ if (cap != NULL) { -+ driver_finis(cap); -+ err = 0; -+ } else -+ err = EINVAL; -+ CRYPTO_DRIVER_UNLOCK(); -+ -+ return err; -+} -+ -+/* -+ * Clear blockage on a driver. The what parameter indicates whether -+ * the driver is now ready for cryptop's and/or cryptokop's. -+ */ -+int -+crypto_unblock(u_int32_t driverid, int what) -+{ -+ struct cryptocap *cap; -+ int err; -+ unsigned long q_flags; -+ -+ CRYPTO_Q_LOCK(); -+ cap = crypto_checkdriver(driverid); -+ if (cap != NULL) { -+ if (what & CRYPTO_SYMQ) { -+ cap->cc_qblocked = 0; -+ cap->cc_unqblocked = 0; -+ crypto_all_qblocked = 0; -+ } -+ if (what & CRYPTO_ASYMQ) { -+ cap->cc_kqblocked = 0; -+ cap->cc_unkqblocked = 0; -+ crypto_all_kqblocked = 0; -+ } -+ if (crp_sleep) -+ wake_up_interruptible(&cryptoproc_wait); -+ err = 0; -+ } else -+ err = EINVAL; -+ CRYPTO_Q_UNLOCK(); //DAVIDM should this be a driver lock -+ -+ return err; -+} -+ -+/* -+ * Add a crypto request to a queue, to be processed by the kernel thread. -+ */ -+int -+crypto_dispatch(struct cryptop *crp) -+{ -+ struct cryptocap *cap; -+ int result = -1; -+ unsigned long q_flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ cryptostats.cs_ops++; -+ -+ CRYPTO_Q_LOCK(); -+ if (crypto_q_cnt >= crypto_q_max) { -+ CRYPTO_Q_UNLOCK(); -+ cryptostats.cs_drops++; -+ return ENOMEM; -+ } -+ crypto_q_cnt++; -+ -+ /* make sure we are starting a fresh run on this crp. */ -+ crp->crp_flags &= ~CRYPTO_F_DONE; -+ crp->crp_etype = 0; -+ -+ /* -+ * Caller marked the request to be processed immediately; dispatch -+ * it directly to the driver unless the driver is currently blocked. -+ */ -+ if ((crp->crp_flags & CRYPTO_F_BATCH) == 0) { -+ int hid = CRYPTO_SESID2HID(crp->crp_sid); -+ cap = crypto_checkdriver(hid); -+ /* Driver cannot disappear when there is an active session. */ -+ KASSERT(cap != NULL, ("%s: Driver disappeared.", __func__)); -+ if (!cap->cc_qblocked) { -+ crypto_all_qblocked = 0; -+ crypto_drivers[hid].cc_unqblocked = 1; -+ CRYPTO_Q_UNLOCK(); -+ result = crypto_invoke(cap, crp, 0); -+ CRYPTO_Q_LOCK(); -+ if (result == ERESTART) -+ if (crypto_drivers[hid].cc_unqblocked) -+ crypto_drivers[hid].cc_qblocked = 1; -+ crypto_drivers[hid].cc_unqblocked = 0; -+ } -+ } -+ if (result == ERESTART) { -+ /* -+ * The driver ran out of resources, mark the -+ * driver ``blocked'' for cryptop's and put -+ * the request back in the queue. It would -+ * best to put the request back where we got -+ * it but that's hard so for now we put it -+ * at the front. This should be ok; putting -+ * it at the end does not work. -+ */ -+ list_add(&crp->crp_next, &crp_q); -+ cryptostats.cs_blocks++; -+ result = 0; -+ } else if (result == -1) { -+ TAILQ_INSERT_TAIL(&crp_q, crp, crp_next); -+ result = 0; -+ } -+ if (crp_sleep) -+ wake_up_interruptible(&cryptoproc_wait); -+ CRYPTO_Q_UNLOCK(); -+ return result; -+} -+ -+/* -+ * Add an asymetric crypto request to a queue, -+ * to be processed by the kernel thread. -+ */ -+int -+crypto_kdispatch(struct cryptkop *krp) -+{ -+ int error; -+ unsigned long q_flags; -+ -+ cryptostats.cs_kops++; -+ -+ error = crypto_kinvoke(krp, krp->krp_crid); -+ if (error == ERESTART) { -+ CRYPTO_Q_LOCK(); -+ TAILQ_INSERT_TAIL(&crp_kq, krp, krp_next); -+ if (crp_sleep) -+ wake_up_interruptible(&cryptoproc_wait); -+ CRYPTO_Q_UNLOCK(); -+ error = 0; -+ } -+ return error; -+} -+ -+/* -+ * Verify a driver is suitable for the specified operation. -+ */ -+static __inline int -+kdriver_suitable(const struct cryptocap *cap, const struct cryptkop *krp) -+{ -+ return (cap->cc_kalg[krp->krp_op] & CRYPTO_ALG_FLAG_SUPPORTED) != 0; -+} -+ -+/* -+ * Select a driver for an asym operation. The driver must -+ * support the necessary algorithm. The caller can constrain -+ * which device is selected with the flags parameter. The -+ * algorithm we use here is pretty stupid; just use the first -+ * driver that supports the algorithms we need. If there are -+ * multiple suitable drivers we choose the driver with the -+ * fewest active operations. We prefer hardware-backed -+ * drivers to software ones when either may be used. -+ */ -+static struct cryptocap * -+crypto_select_kdriver(const struct cryptkop *krp, int flags) -+{ -+ struct cryptocap *cap, *best, *blocked; -+ int match, hid; -+ -+ CRYPTO_DRIVER_ASSERT(); -+ -+ /* -+ * Look first for hardware crypto devices if permitted. -+ */ -+ if (flags & CRYPTOCAP_F_HARDWARE) -+ match = CRYPTOCAP_F_HARDWARE; -+ else -+ match = CRYPTOCAP_F_SOFTWARE; -+ best = NULL; -+ blocked = NULL; -+again: -+ for (hid = 0; hid < crypto_drivers_num; hid++) { -+ cap = &crypto_drivers[hid]; -+ /* -+ * If it's not initialized, is in the process of -+ * going away, or is not appropriate (hardware -+ * or software based on match), then skip. -+ */ -+ if (cap->cc_dev == NULL || -+ (cap->cc_flags & CRYPTOCAP_F_CLEANUP) || -+ (cap->cc_flags & match) == 0) -+ continue; -+ -+ /* verify all the algorithms are supported. */ -+ if (kdriver_suitable(cap, krp)) { -+ if (best == NULL || -+ cap->cc_koperations < best->cc_koperations) -+ best = cap; -+ } -+ } -+ if (best != NULL) -+ return best; -+ if (match == CRYPTOCAP_F_HARDWARE && (flags & CRYPTOCAP_F_SOFTWARE)) { -+ /* sort of an Algol 68-style for loop */ -+ match = CRYPTOCAP_F_SOFTWARE; -+ goto again; -+ } -+ return best; -+} -+ -+/* -+ * Dispatch an assymetric crypto request. -+ */ -+static int -+crypto_kinvoke(struct cryptkop *krp, int crid) -+{ -+ struct cryptocap *cap = NULL; -+ int error; -+ unsigned long d_flags; -+ -+ KASSERT(krp != NULL, ("%s: krp == NULL", __func__)); -+ KASSERT(krp->krp_callback != NULL, -+ ("%s: krp->crp_callback == NULL", __func__)); -+ -+ CRYPTO_DRIVER_LOCK(); -+ if ((crid & (CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE)) == 0) { -+ cap = crypto_checkdriver(crid); -+ if (cap != NULL) { -+ /* -+ * Driver present, it must support the necessary -+ * algorithm and, if s/w drivers are excluded, -+ * it must be registered as hardware-backed. -+ */ -+ if (!kdriver_suitable(cap, krp) || -+ (!crypto_devallowsoft && -+ (cap->cc_flags & CRYPTOCAP_F_HARDWARE) == 0)) -+ cap = NULL; -+ } -+ } else { -+ /* -+ * No requested driver; select based on crid flags. -+ */ -+ if (!crypto_devallowsoft) /* NB: disallow s/w drivers */ -+ crid &= ~CRYPTOCAP_F_SOFTWARE; -+ cap = crypto_select_kdriver(krp, crid); -+ } -+ if (cap != NULL && !cap->cc_kqblocked) { -+ krp->krp_hid = cap - crypto_drivers; -+ cap->cc_koperations++; -+ CRYPTO_DRIVER_UNLOCK(); -+ error = CRYPTODEV_KPROCESS(cap->cc_dev, krp, 0); -+ CRYPTO_DRIVER_LOCK(); -+ if (error == ERESTART) { -+ cap->cc_koperations--; -+ CRYPTO_DRIVER_UNLOCK(); -+ return (error); -+ } -+ /* return the actual device used */ -+ krp->krp_crid = krp->krp_hid; -+ } else { -+ /* -+ * NB: cap is !NULL if device is blocked; in -+ * that case return ERESTART so the operation -+ * is resubmitted if possible. -+ */ -+ error = (cap == NULL) ? ENODEV : ERESTART; -+ } -+ CRYPTO_DRIVER_UNLOCK(); -+ -+ if (error) { -+ krp->krp_status = error; -+ crypto_kdone(krp); -+ } -+ return 0; -+} -+ -+ -+/* -+ * Dispatch a crypto request to the appropriate crypto devices. -+ */ -+static int -+crypto_invoke(struct cryptocap *cap, struct cryptop *crp, int hint) -+{ -+ KASSERT(crp != NULL, ("%s: crp == NULL", __func__)); -+ KASSERT(crp->crp_callback != NULL, -+ ("%s: crp->crp_callback == NULL", __func__)); -+ KASSERT(crp->crp_desc != NULL, ("%s: crp->crp_desc == NULL", __func__)); -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+#ifdef CRYPTO_TIMING -+ if (crypto_timing) -+ crypto_tstat(&cryptostats.cs_invoke, &crp->crp_tstamp); -+#endif -+ if (cap->cc_flags & CRYPTOCAP_F_CLEANUP) { -+ struct cryptodesc *crd; -+ u_int64_t nid; -+ -+ /* -+ * Driver has unregistered; migrate the session and return -+ * an error to the caller so they'll resubmit the op. -+ * -+ * XXX: What if there are more already queued requests for this -+ * session? -+ */ -+ crypto_freesession(crp->crp_sid); -+ -+ for (crd = crp->crp_desc; crd->crd_next; crd = crd->crd_next) -+ crd->CRD_INI.cri_next = &(crd->crd_next->CRD_INI); -+ -+ /* XXX propagate flags from initial session? */ -+ if (crypto_newsession(&nid, &(crp->crp_desc->CRD_INI), -+ CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE) == 0) -+ crp->crp_sid = nid; -+ -+ crp->crp_etype = EAGAIN; -+ crypto_done(crp); -+ return 0; -+ } else { -+ /* -+ * Invoke the driver to process the request. -+ */ -+ return CRYPTODEV_PROCESS(cap->cc_dev, crp, hint); -+ } -+} -+ -+/* -+ * Release a set of crypto descriptors. -+ */ -+void -+crypto_freereq(struct cryptop *crp) -+{ -+ struct cryptodesc *crd; -+ -+ if (crp == NULL) -+ return; -+ -+#ifdef DIAGNOSTIC -+ { -+ struct cryptop *crp2; -+ unsigned long q_flags; -+ -+ CRYPTO_Q_LOCK(); -+ TAILQ_FOREACH(crp2, &crp_q, crp_next) { -+ KASSERT(crp2 != crp, -+ ("Freeing cryptop from the crypto queue (%p).", -+ crp)); -+ } -+ CRYPTO_Q_UNLOCK(); -+ CRYPTO_RETQ_LOCK(); -+ TAILQ_FOREACH(crp2, &crp_ret_q, crp_next) { -+ KASSERT(crp2 != crp, -+ ("Freeing cryptop from the return queue (%p).", -+ crp)); -+ } -+ CRYPTO_RETQ_UNLOCK(); -+ } -+#endif -+ -+ while ((crd = crp->crp_desc) != NULL) { -+ crp->crp_desc = crd->crd_next; -+ kmem_cache_free(cryptodesc_zone, crd); -+ } -+ kmem_cache_free(cryptop_zone, crp); -+} -+ -+/* -+ * Acquire a set of crypto descriptors. -+ */ -+struct cryptop * -+crypto_getreq(int num) -+{ -+ struct cryptodesc *crd; -+ struct cryptop *crp; -+ -+ crp = kmem_cache_alloc(cryptop_zone, SLAB_ATOMIC); -+ if (crp != NULL) { -+ memset(crp, 0, sizeof(*crp)); -+ INIT_LIST_HEAD(&crp->crp_next); -+ init_waitqueue_head(&crp->crp_waitq); -+ while (num--) { -+ crd = kmem_cache_alloc(cryptodesc_zone, SLAB_ATOMIC); -+ if (crd == NULL) { -+ crypto_freereq(crp); -+ return NULL; -+ } -+ memset(crd, 0, sizeof(*crd)); -+ crd->crd_next = crp->crp_desc; -+ crp->crp_desc = crd; -+ } -+ } -+ return crp; -+} -+ -+/* -+ * Invoke the callback on behalf of the driver. -+ */ -+void -+crypto_done(struct cryptop *crp) -+{ -+ unsigned long q_flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if ((crp->crp_flags & CRYPTO_F_DONE) == 0) { -+ crp->crp_flags |= CRYPTO_F_DONE; -+ CRYPTO_Q_LOCK(); -+ crypto_q_cnt--; -+ CRYPTO_Q_UNLOCK(); -+ } else -+ printk("crypto: crypto_done op already done, flags 0x%x", -+ crp->crp_flags); -+ if (crp->crp_etype != 0) -+ cryptostats.cs_errs++; -+ /* -+ * CBIMM means unconditionally do the callback immediately; -+ * CBIFSYNC means do the callback immediately only if the -+ * operation was done synchronously. Both are used to avoid -+ * doing extraneous context switches; the latter is mostly -+ * used with the software crypto driver. -+ */ -+ if ((crp->crp_flags & CRYPTO_F_CBIMM) || -+ ((crp->crp_flags & CRYPTO_F_CBIFSYNC) && -+ (CRYPTO_SESID2CAPS(crp->crp_sid) & CRYPTOCAP_F_SYNC))) { -+ /* -+ * Do the callback directly. This is ok when the -+ * callback routine does very little (e.g. the -+ * /dev/crypto callback method just does a wakeup). -+ */ -+ crp->crp_callback(crp); -+ } else { -+ unsigned long r_flags; -+ /* -+ * Normal case; queue the callback for the thread. -+ */ -+ CRYPTO_RETQ_LOCK(); -+ if (CRYPTO_RETQ_EMPTY()) -+ wake_up_interruptible(&cryptoretproc_wait);/* shared wait channel */ -+ TAILQ_INSERT_TAIL(&crp_ret_q, crp, crp_next); -+ CRYPTO_RETQ_UNLOCK(); -+ } -+} -+ -+/* -+ * Invoke the callback on behalf of the driver. -+ */ -+void -+crypto_kdone(struct cryptkop *krp) -+{ -+ struct cryptocap *cap; -+ unsigned long d_flags; -+ -+ if ((krp->krp_flags & CRYPTO_KF_DONE) != 0) -+ printk("crypto: crypto_kdone op already done, flags 0x%x", -+ krp->krp_flags); -+ krp->krp_flags |= CRYPTO_KF_DONE; -+ if (krp->krp_status != 0) -+ cryptostats.cs_kerrs++; -+ -+ CRYPTO_DRIVER_LOCK(); -+ /* XXX: What if driver is loaded in the meantime? */ -+ if (krp->krp_hid < crypto_drivers_num) { -+ cap = &crypto_drivers[krp->krp_hid]; -+ cap->cc_koperations--; -+ KASSERT(cap->cc_koperations >= 0, ("cc_koperations < 0")); -+ if (cap->cc_flags & CRYPTOCAP_F_CLEANUP) -+ crypto_remove(cap); -+ } -+ CRYPTO_DRIVER_UNLOCK(); -+ -+ /* -+ * CBIMM means unconditionally do the callback immediately; -+ * This is used to avoid doing extraneous context switches -+ */ -+ if ((krp->krp_flags & CRYPTO_KF_CBIMM)) { -+ /* -+ * Do the callback directly. This is ok when the -+ * callback routine does very little (e.g. the -+ * /dev/crypto callback method just does a wakeup). -+ */ -+ krp->krp_callback(krp); -+ } else { -+ unsigned long r_flags; -+ /* -+ * Normal case; queue the callback for the thread. -+ */ -+ CRYPTO_RETQ_LOCK(); -+ if (CRYPTO_RETQ_EMPTY()) -+ wake_up_interruptible(&cryptoretproc_wait);/* shared wait channel */ -+ TAILQ_INSERT_TAIL(&crp_ret_kq, krp, krp_next); -+ CRYPTO_RETQ_UNLOCK(); -+ } -+} -+ -+int -+crypto_getfeat(int *featp) -+{ -+ int hid, kalg, feat = 0; -+ unsigned long d_flags; -+ -+ CRYPTO_DRIVER_LOCK(); -+ for (hid = 0; hid < crypto_drivers_num; hid++) { -+ const struct cryptocap *cap = &crypto_drivers[hid]; -+ -+ if ((cap->cc_flags & CRYPTOCAP_F_SOFTWARE) && -+ !crypto_devallowsoft) { -+ continue; -+ } -+ for (kalg = 0; kalg < CRK_ALGORITHM_MAX; kalg++) -+ if (cap->cc_kalg[kalg] & CRYPTO_ALG_FLAG_SUPPORTED) -+ feat |= 1 << kalg; -+ } -+ CRYPTO_DRIVER_UNLOCK(); -+ *featp = feat; -+ return (0); -+} -+ -+/* -+ * Crypto thread, dispatches crypto requests. -+ */ -+static int -+crypto_proc(void *arg) -+{ -+ struct cryptop *crp, *submit; -+ struct cryptkop *krp, *krpp; -+ struct cryptocap *cap; -+ u_int32_t hid; -+ int result, hint; -+ unsigned long q_flags; -+ int loopcount = 0; -+ -+ ocf_daemonize("crypto"); -+ -+ CRYPTO_Q_LOCK(); -+ for (;;) { -+ /* -+ * we need to make sure we don't get into a busy loop with nothing -+ * to do, the two crypto_all_*blocked vars help us find out when -+ * we are all full and can do nothing on any driver or Q. If so we -+ * wait for an unblock. -+ */ -+ crypto_all_qblocked = !list_empty(&crp_q); -+ -+ /* -+ * Find the first element in the queue that can be -+ * processed and look-ahead to see if multiple ops -+ * are ready for the same driver. -+ */ -+ submit = NULL; -+ hint = 0; -+ list_for_each_entry(crp, &crp_q, crp_next) { -+ hid = CRYPTO_SESID2HID(crp->crp_sid); -+ cap = crypto_checkdriver(hid); -+ /* -+ * Driver cannot disappear when there is an active -+ * session. -+ */ -+ KASSERT(cap != NULL, ("%s:%u Driver disappeared.", -+ __func__, __LINE__)); -+ if (cap == NULL || cap->cc_dev == NULL) { -+ /* Op needs to be migrated, process it. */ -+ if (submit == NULL) -+ submit = crp; -+ break; -+ } -+ if (!cap->cc_qblocked) { -+ if (submit != NULL) { -+ /* -+ * We stop on finding another op, -+ * regardless whether its for the same -+ * driver or not. We could keep -+ * searching the queue but it might be -+ * better to just use a per-driver -+ * queue instead. -+ */ -+ if (CRYPTO_SESID2HID(submit->crp_sid) == hid) -+ hint = CRYPTO_HINT_MORE; -+ break; -+ } else { -+ submit = crp; -+ if ((submit->crp_flags & CRYPTO_F_BATCH) == 0) -+ break; -+ /* keep scanning for more are q'd */ -+ } -+ } -+ } -+ if (submit != NULL) { -+ hid = CRYPTO_SESID2HID(submit->crp_sid); -+ crypto_all_qblocked = 0; -+ list_del(&submit->crp_next); -+ crypto_drivers[hid].cc_unqblocked = 1; -+ cap = crypto_checkdriver(hid); -+ CRYPTO_Q_UNLOCK(); -+ KASSERT(cap != NULL, ("%s:%u Driver disappeared.", -+ __func__, __LINE__)); -+ result = crypto_invoke(cap, submit, hint); -+ CRYPTO_Q_LOCK(); -+ if (result == ERESTART) { -+ /* -+ * The driver ran out of resources, mark the -+ * driver ``blocked'' for cryptop's and put -+ * the request back in the queue. It would -+ * best to put the request back where we got -+ * it but that's hard so for now we put it -+ * at the front. This should be ok; putting -+ * it at the end does not work. -+ */ -+ /* XXX validate sid again? */ -+ list_add(&submit->crp_next, &crp_q); -+ cryptostats.cs_blocks++; -+ if (crypto_drivers[hid].cc_unqblocked) -+ crypto_drivers[hid].cc_qblocked=0; -+ crypto_drivers[hid].cc_unqblocked=0; -+ } -+ crypto_drivers[hid].cc_unqblocked = 0; -+ } -+ -+ crypto_all_kqblocked = !list_empty(&crp_kq); -+ -+ /* As above, but for key ops */ -+ krp = NULL; -+ list_for_each_entry(krpp, &crp_kq, krp_next) { -+ cap = crypto_checkdriver(krpp->krp_hid); -+ if (cap == NULL || cap->cc_dev == NULL) { -+ /* -+ * Operation needs to be migrated, invalidate -+ * the assigned device so it will reselect a -+ * new one below. Propagate the original -+ * crid selection flags if supplied. -+ */ -+ krp->krp_hid = krp->krp_crid & -+ (CRYPTOCAP_F_SOFTWARE|CRYPTOCAP_F_HARDWARE); -+ if (krp->krp_hid == 0) -+ krp->krp_hid = -+ CRYPTOCAP_F_SOFTWARE|CRYPTOCAP_F_HARDWARE; -+ break; -+ } -+ if (!cap->cc_kqblocked) { -+ krp = krpp; -+ break; -+ } -+ } -+ if (krp != NULL) { -+ crypto_all_kqblocked = 0; -+ list_del(&krp->krp_next); -+ crypto_drivers[krp->krp_hid].cc_kqblocked = 1; -+ CRYPTO_Q_UNLOCK(); -+ result = crypto_kinvoke(krp, krp->krp_hid); -+ CRYPTO_Q_LOCK(); -+ if (result == ERESTART) { -+ /* -+ * The driver ran out of resources, mark the -+ * driver ``blocked'' for cryptkop's and put -+ * the request back in the queue. It would -+ * best to put the request back where we got -+ * it but that's hard so for now we put it -+ * at the front. This should be ok; putting -+ * it at the end does not work. -+ */ -+ /* XXX validate sid again? */ -+ list_add(&krp->krp_next, &crp_kq); -+ cryptostats.cs_kblocks++; -+ } else -+ crypto_drivers[krp->krp_hid].cc_kqblocked = 0; -+ } -+ -+ if (submit == NULL && krp == NULL) { -+ /* -+ * Nothing more to be processed. Sleep until we're -+ * woken because there are more ops to process. -+ * This happens either by submission or by a driver -+ * becoming unblocked and notifying us through -+ * crypto_unblock. Note that when we wakeup we -+ * start processing each queue again from the -+ * front. It's not clear that it's important to -+ * preserve this ordering since ops may finish -+ * out of order if dispatched to different devices -+ * and some become blocked while others do not. -+ */ -+ dprintk("%s - sleeping (qe=%d qb=%d kqe=%d kqb=%d)\n", -+ __FUNCTION__, -+ list_empty(&crp_q), crypto_all_qblocked, -+ list_empty(&crp_kq), crypto_all_kqblocked); -+ loopcount = 0; -+ CRYPTO_Q_UNLOCK(); -+ crp_sleep = 1; -+ wait_event_interruptible(cryptoproc_wait, -+ !(list_empty(&crp_q) || crypto_all_qblocked) || -+ !(list_empty(&crp_kq) || crypto_all_kqblocked) || -+ cryptoproc == (pid_t) -1); -+ crp_sleep = 0; -+ if (signal_pending (current)) { -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ spin_lock_irq(¤t->sigmask_lock); -+#endif -+ flush_signals(current); -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ spin_unlock_irq(¤t->sigmask_lock); -+#endif -+ } -+ CRYPTO_Q_LOCK(); -+ dprintk("%s - awake\n", __FUNCTION__); -+ if (cryptoproc == (pid_t) -1) -+ break; -+ cryptostats.cs_intrs++; -+ } else if (loopcount > crypto_max_loopcount) { -+ /* -+ * Give other processes a chance to run if we've -+ * been using the CPU exclusively for a while. -+ */ -+ loopcount = 0; -+ schedule(); -+ } -+ loopcount++; -+ } -+ CRYPTO_Q_UNLOCK(); -+ complete_and_exit(&cryptoproc_exited, 0); -+} -+ -+/* -+ * Crypto returns thread, does callbacks for processed crypto requests. -+ * Callbacks are done here, rather than in the crypto drivers, because -+ * callbacks typically are expensive and would slow interrupt handling. -+ */ -+static int -+crypto_ret_proc(void *arg) -+{ -+ struct cryptop *crpt; -+ struct cryptkop *krpt; -+ unsigned long r_flags; -+ -+ ocf_daemonize("crypto_ret"); -+ -+ CRYPTO_RETQ_LOCK(); -+ for (;;) { -+ /* Harvest return q's for completed ops */ -+ crpt = NULL; -+ if (!list_empty(&crp_ret_q)) -+ crpt = list_entry(crp_ret_q.next, typeof(*crpt), crp_next); -+ if (crpt != NULL) -+ list_del(&crpt->crp_next); -+ -+ krpt = NULL; -+ if (!list_empty(&crp_ret_kq)) -+ krpt = list_entry(crp_ret_kq.next, typeof(*krpt), krp_next); -+ if (krpt != NULL) -+ list_del(&krpt->krp_next); -+ -+ if (crpt != NULL || krpt != NULL) { -+ CRYPTO_RETQ_UNLOCK(); -+ /* -+ * Run callbacks unlocked. -+ */ -+ if (crpt != NULL) -+ crpt->crp_callback(crpt); -+ if (krpt != NULL) -+ krpt->krp_callback(krpt); -+ CRYPTO_RETQ_LOCK(); -+ } else { -+ /* -+ * Nothing more to be processed. Sleep until we're -+ * woken because there are more returns to process. -+ */ -+ dprintk("%s - sleeping\n", __FUNCTION__); -+ CRYPTO_RETQ_UNLOCK(); -+ wait_event_interruptible(cryptoretproc_wait, -+ cryptoretproc == (pid_t) -1 || -+ !list_empty(&crp_ret_q) || -+ !list_empty(&crp_ret_kq)); -+ if (signal_pending (current)) { -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ spin_lock_irq(¤t->sigmask_lock); -+#endif -+ flush_signals(current); -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ spin_unlock_irq(¤t->sigmask_lock); -+#endif -+ } -+ CRYPTO_RETQ_LOCK(); -+ dprintk("%s - awake\n", __FUNCTION__); -+ if (cryptoretproc == (pid_t) -1) { -+ dprintk("%s - EXITING!\n", __FUNCTION__); -+ break; -+ } -+ cryptostats.cs_rets++; -+ } -+ } -+ CRYPTO_RETQ_UNLOCK(); -+ complete_and_exit(&cryptoretproc_exited, 0); -+} -+ -+ -+#if 0 /* should put this into /proc or something */ -+static void -+db_show_drivers(void) -+{ -+ int hid; -+ -+ db_printf("%12s %4s %4s %8s %2s %2s\n" -+ , "Device" -+ , "Ses" -+ , "Kops" -+ , "Flags" -+ , "QB" -+ , "KB" -+ ); -+ for (hid = 0; hid < crypto_drivers_num; hid++) { -+ const struct cryptocap *cap = &crypto_drivers[hid]; -+ if (cap->cc_dev == NULL) -+ continue; -+ db_printf("%-12s %4u %4u %08x %2u %2u\n" -+ , device_get_nameunit(cap->cc_dev) -+ , cap->cc_sessions -+ , cap->cc_koperations -+ , cap->cc_flags -+ , cap->cc_qblocked -+ , cap->cc_kqblocked -+ ); -+ } -+} -+ -+DB_SHOW_COMMAND(crypto, db_show_crypto) -+{ -+ struct cryptop *crp; -+ -+ db_show_drivers(); -+ db_printf("\n"); -+ -+ db_printf("%4s %8s %4s %4s %4s %4s %8s %8s\n", -+ "HID", "Caps", "Ilen", "Olen", "Etype", "Flags", -+ "Desc", "Callback"); -+ TAILQ_FOREACH(crp, &crp_q, crp_next) { -+ db_printf("%4u %08x %4u %4u %4u %04x %8p %8p\n" -+ , (int) CRYPTO_SESID2HID(crp->crp_sid) -+ , (int) CRYPTO_SESID2CAPS(crp->crp_sid) -+ , crp->crp_ilen, crp->crp_olen -+ , crp->crp_etype -+ , crp->crp_flags -+ , crp->crp_desc -+ , crp->crp_callback -+ ); -+ } -+ if (!TAILQ_EMPTY(&crp_ret_q)) { -+ db_printf("\n%4s %4s %4s %8s\n", -+ "HID", "Etype", "Flags", "Callback"); -+ TAILQ_FOREACH(crp, &crp_ret_q, crp_next) { -+ db_printf("%4u %4u %04x %8p\n" -+ , (int) CRYPTO_SESID2HID(crp->crp_sid) -+ , crp->crp_etype -+ , crp->crp_flags -+ , crp->crp_callback -+ ); -+ } -+ } -+} -+ -+DB_SHOW_COMMAND(kcrypto, db_show_kcrypto) -+{ -+ struct cryptkop *krp; -+ -+ db_show_drivers(); -+ db_printf("\n"); -+ -+ db_printf("%4s %5s %4s %4s %8s %4s %8s\n", -+ "Op", "Status", "#IP", "#OP", "CRID", "HID", "Callback"); -+ TAILQ_FOREACH(krp, &crp_kq, krp_next) { -+ db_printf("%4u %5u %4u %4u %08x %4u %8p\n" -+ , krp->krp_op -+ , krp->krp_status -+ , krp->krp_iparams, krp->krp_oparams -+ , krp->krp_crid, krp->krp_hid -+ , krp->krp_callback -+ ); -+ } -+ if (!TAILQ_EMPTY(&crp_ret_q)) { -+ db_printf("%4s %5s %8s %4s %8s\n", -+ "Op", "Status", "CRID", "HID", "Callback"); -+ TAILQ_FOREACH(krp, &crp_ret_kq, krp_next) { -+ db_printf("%4u %5u %08x %4u %8p\n" -+ , krp->krp_op -+ , krp->krp_status -+ , krp->krp_crid, krp->krp_hid -+ , krp->krp_callback -+ ); -+ } -+ } -+} -+#endif -+ -+ -+static int -+crypto_init(void) -+{ -+ int error; -+ -+ dprintk("%s(%p)\n", __FUNCTION__, (void *) crypto_init); -+ -+ if (crypto_initted) -+ return 0; -+ crypto_initted = 1; -+ -+ spin_lock_init(&crypto_drivers_lock); -+ spin_lock_init(&crypto_q_lock); -+ spin_lock_init(&crypto_ret_q_lock); -+ -+ cryptop_zone = kmem_cache_create("cryptop", sizeof(struct cryptop), -+ 0, SLAB_HWCACHE_ALIGN, NULL -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) -+ , NULL -+#endif -+ ); -+ -+ cryptodesc_zone = kmem_cache_create("cryptodesc", sizeof(struct cryptodesc), -+ 0, SLAB_HWCACHE_ALIGN, NULL -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) -+ , NULL -+#endif -+ ); -+ -+ if (cryptodesc_zone == NULL || cryptop_zone == NULL) { -+ printk("crypto: crypto_init cannot setup crypto zones\n"); -+ error = ENOMEM; -+ goto bad; -+ } -+ -+ crypto_drivers_num = CRYPTO_DRIVERS_INITIAL; -+ crypto_drivers = kmalloc(crypto_drivers_num * sizeof(struct cryptocap), -+ GFP_KERNEL); -+ if (crypto_drivers == NULL) { -+ printk("crypto: crypto_init cannot setup crypto drivers\n"); -+ error = ENOMEM; -+ goto bad; -+ } -+ -+ memset(crypto_drivers, 0, crypto_drivers_num * sizeof(struct cryptocap)); -+ -+ init_completion(&cryptoproc_exited); -+ init_completion(&cryptoretproc_exited); -+ -+ cryptoproc = 0; /* to avoid race condition where proc runs first */ -+ cryptoproc = kernel_thread(crypto_proc, NULL, CLONE_FS|CLONE_FILES); -+ if (cryptoproc < 0) { -+ error = cryptoproc; -+ printk("crypto: crypto_init cannot start crypto thread; error %d", -+ error); -+ goto bad; -+ } -+ -+ cryptoretproc = 0; /* to avoid race condition where proc runs first */ -+ cryptoretproc = kernel_thread(crypto_ret_proc, NULL, CLONE_FS|CLONE_FILES); -+ if (cryptoretproc < 0) { -+ error = cryptoretproc; -+ printk("crypto: crypto_init cannot start cryptoret thread; error %d", -+ error); -+ goto bad; -+ } -+ -+ return 0; -+bad: -+ crypto_exit(); -+ return error; -+} -+ -+ -+static void -+crypto_exit(void) -+{ -+ pid_t p; -+ unsigned long d_flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ /* -+ * Terminate any crypto threads. -+ */ -+ -+ CRYPTO_DRIVER_LOCK(); -+ p = cryptoproc; -+ cryptoproc = (pid_t) -1; -+ kill_proc(p, SIGTERM, 1); -+ wake_up_interruptible(&cryptoproc_wait); -+ CRYPTO_DRIVER_UNLOCK(); -+ -+ wait_for_completion(&cryptoproc_exited); -+ -+ CRYPTO_DRIVER_LOCK(); -+ p = cryptoretproc; -+ cryptoretproc = (pid_t) -1; -+ kill_proc(p, SIGTERM, 1); -+ wake_up_interruptible(&cryptoretproc_wait); -+ CRYPTO_DRIVER_UNLOCK(); -+ -+ wait_for_completion(&cryptoretproc_exited); -+ -+ /* XXX flush queues??? */ -+ -+ /* -+ * Reclaim dynamically allocated resources. -+ */ -+ if (crypto_drivers != NULL) -+ kfree(crypto_drivers); -+ -+ if (cryptodesc_zone != NULL) -+ kmem_cache_destroy(cryptodesc_zone); -+ if (cryptop_zone != NULL) -+ kmem_cache_destroy(cryptop_zone); -+} -+ -+ -+EXPORT_SYMBOL(crypto_newsession); -+EXPORT_SYMBOL(crypto_freesession); -+EXPORT_SYMBOL(crypto_get_driverid); -+EXPORT_SYMBOL(crypto_kregister); -+EXPORT_SYMBOL(crypto_register); -+EXPORT_SYMBOL(crypto_unregister); -+EXPORT_SYMBOL(crypto_unregister_all); -+EXPORT_SYMBOL(crypto_unblock); -+EXPORT_SYMBOL(crypto_dispatch); -+EXPORT_SYMBOL(crypto_kdispatch); -+EXPORT_SYMBOL(crypto_freereq); -+EXPORT_SYMBOL(crypto_getreq); -+EXPORT_SYMBOL(crypto_done); -+EXPORT_SYMBOL(crypto_kdone); -+EXPORT_SYMBOL(crypto_getfeat); -+EXPORT_SYMBOL(crypto_userasymcrypto); -+EXPORT_SYMBOL(crypto_getcaps); -+EXPORT_SYMBOL(crypto_find_driver); -+EXPORT_SYMBOL(crypto_find_device_byhid); -+ -+module_init(crypto_init); -+module_exit(crypto_exit); -+ -+MODULE_LICENSE("BSD"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("OCF (OpenBSD Cryptographic Framework)"); -diff -Nur linux-2.6.36.orig/crypto/ocf/cryptocteon/cavium_crypto.c linux-2.6.36/crypto/ocf/cryptocteon/cavium_crypto.c ---- linux-2.6.36.orig/crypto/ocf/cryptocteon/cavium_crypto.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/cryptocteon/cavium_crypto.c 2010-11-09 20:28:04.311245450 +0100 -@@ -0,0 +1,2283 @@ -+/* -+ * Copyright (c) 2009 David McCullough -+ * -+ * Copyright (c) 2003-2007 Cavium Networks (support@cavium.com). All rights -+ * reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * 1. Redistributions of source code must retain the above copyright notice, -+ * this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright notice, -+ * this list of conditions and the following disclaimer in the documentation -+ * and/or other materials provided with the distribution. -+ * 3. All advertising materials mentioning features or use of this software -+ * must display the following acknowledgement: -+ * This product includes software developed by Cavium Networks -+ * 4. Cavium Networks' name may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * This Software, including technical data, may be subject to U.S. export -+ * control laws, including the U.S. Export Administration Act and its -+ * associated regulations, and may be subject to export or import regulations -+ * in other countries. You warrant that You will comply strictly in all -+ * respects with all such regulations and acknowledge that you have the -+ * responsibility to obtain licenses to export, re-export or import the -+ * Software. -+ * -+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" AND -+ * WITH ALL FAULTS AND CAVIUM MAKES NO PROMISES, REPRESENTATIONS OR WARRANTIES, -+ * EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO THE -+ * SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR -+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM -+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, -+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF -+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR -+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR -+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. -+*/ -+/****************************************************************************/ -+ -+#include -+#include -+#include "octeon-asm.h" -+ -+/****************************************************************************/ -+ -+extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *); -+extern void octeon_crypto_disable(struct octeon_cop2_state *, unsigned long); -+ -+#define SG_INIT(s, p, i, l) \ -+ { \ -+ (i) = 0; \ -+ (l) = (s)[0].length; \ -+ (p) = (typeof(p)) sg_virt((s)); \ -+ CVMX_PREFETCH0((p)); \ -+ } -+ -+#define SG_CONSUME(s, p, i, l) \ -+ { \ -+ (p)++; \ -+ (l) -= sizeof(*(p)); \ -+ if ((l) < 0) { \ -+ dprintk("%s, %d: l = %d\n", __FILE__, __LINE__, l); \ -+ } else if ((l) == 0) { \ -+ (i)++; \ -+ (l) = (s)[0].length; \ -+ (p) = (typeof(p)) sg_virt(s); \ -+ CVMX_PREFETCH0((p)); \ -+ } \ -+ } -+ -+#define ESP_HEADER_LENGTH 8 -+#define DES_CBC_IV_LENGTH 8 -+#define AES_CBC_IV_LENGTH 16 -+#define ESP_HMAC_LEN 12 -+ -+#define ESP_HEADER_LENGTH 8 -+#define DES_CBC_IV_LENGTH 8 -+ -+/****************************************************************************/ -+ -+#define CVM_LOAD_SHA_UNIT(dat, next) { \ -+ if (next == 0) { \ -+ next = 1; \ -+ CVMX_MT_HSH_DAT (dat, 0); \ -+ } else if (next == 1) { \ -+ next = 2; \ -+ CVMX_MT_HSH_DAT (dat, 1); \ -+ } else if (next == 2) { \ -+ next = 3; \ -+ CVMX_MT_HSH_DAT (dat, 2); \ -+ } else if (next == 3) { \ -+ next = 4; \ -+ CVMX_MT_HSH_DAT (dat, 3); \ -+ } else if (next == 4) { \ -+ next = 5; \ -+ CVMX_MT_HSH_DAT (dat, 4); \ -+ } else if (next == 5) { \ -+ next = 6; \ -+ CVMX_MT_HSH_DAT (dat, 5); \ -+ } else if (next == 6) { \ -+ next = 7; \ -+ CVMX_MT_HSH_DAT (dat, 6); \ -+ } else { \ -+ CVMX_MT_HSH_STARTSHA (dat); \ -+ next = 0; \ -+ } \ -+} -+ -+#define CVM_LOAD2_SHA_UNIT(dat1, dat2, next) { \ -+ if (next == 0) { \ -+ CVMX_MT_HSH_DAT (dat1, 0); \ -+ CVMX_MT_HSH_DAT (dat2, 1); \ -+ next = 2; \ -+ } else if (next == 1) { \ -+ CVMX_MT_HSH_DAT (dat1, 1); \ -+ CVMX_MT_HSH_DAT (dat2, 2); \ -+ next = 3; \ -+ } else if (next == 2) { \ -+ CVMX_MT_HSH_DAT (dat1, 2); \ -+ CVMX_MT_HSH_DAT (dat2, 3); \ -+ next = 4; \ -+ } else if (next == 3) { \ -+ CVMX_MT_HSH_DAT (dat1, 3); \ -+ CVMX_MT_HSH_DAT (dat2, 4); \ -+ next = 5; \ -+ } else if (next == 4) { \ -+ CVMX_MT_HSH_DAT (dat1, 4); \ -+ CVMX_MT_HSH_DAT (dat2, 5); \ -+ next = 6; \ -+ } else if (next == 5) { \ -+ CVMX_MT_HSH_DAT (dat1, 5); \ -+ CVMX_MT_HSH_DAT (dat2, 6); \ -+ next = 7; \ -+ } else if (next == 6) { \ -+ CVMX_MT_HSH_DAT (dat1, 6); \ -+ CVMX_MT_HSH_STARTSHA (dat2); \ -+ next = 0; \ -+ } else { \ -+ CVMX_MT_HSH_STARTSHA (dat1); \ -+ CVMX_MT_HSH_DAT (dat2, 0); \ -+ next = 1; \ -+ } \ -+} -+ -+/****************************************************************************/ -+ -+#define CVM_LOAD_MD5_UNIT(dat, next) { \ -+ if (next == 0) { \ -+ next = 1; \ -+ CVMX_MT_HSH_DAT (dat, 0); \ -+ } else if (next == 1) { \ -+ next = 2; \ -+ CVMX_MT_HSH_DAT (dat, 1); \ -+ } else if (next == 2) { \ -+ next = 3; \ -+ CVMX_MT_HSH_DAT (dat, 2); \ -+ } else if (next == 3) { \ -+ next = 4; \ -+ CVMX_MT_HSH_DAT (dat, 3); \ -+ } else if (next == 4) { \ -+ next = 5; \ -+ CVMX_MT_HSH_DAT (dat, 4); \ -+ } else if (next == 5) { \ -+ next = 6; \ -+ CVMX_MT_HSH_DAT (dat, 5); \ -+ } else if (next == 6) { \ -+ next = 7; \ -+ CVMX_MT_HSH_DAT (dat, 6); \ -+ } else { \ -+ CVMX_MT_HSH_STARTMD5 (dat); \ -+ next = 0; \ -+ } \ -+} -+ -+#define CVM_LOAD2_MD5_UNIT(dat1, dat2, next) { \ -+ if (next == 0) { \ -+ CVMX_MT_HSH_DAT (dat1, 0); \ -+ CVMX_MT_HSH_DAT (dat2, 1); \ -+ next = 2; \ -+ } else if (next == 1) { \ -+ CVMX_MT_HSH_DAT (dat1, 1); \ -+ CVMX_MT_HSH_DAT (dat2, 2); \ -+ next = 3; \ -+ } else if (next == 2) { \ -+ CVMX_MT_HSH_DAT (dat1, 2); \ -+ CVMX_MT_HSH_DAT (dat2, 3); \ -+ next = 4; \ -+ } else if (next == 3) { \ -+ CVMX_MT_HSH_DAT (dat1, 3); \ -+ CVMX_MT_HSH_DAT (dat2, 4); \ -+ next = 5; \ -+ } else if (next == 4) { \ -+ CVMX_MT_HSH_DAT (dat1, 4); \ -+ CVMX_MT_HSH_DAT (dat2, 5); \ -+ next = 6; \ -+ } else if (next == 5) { \ -+ CVMX_MT_HSH_DAT (dat1, 5); \ -+ CVMX_MT_HSH_DAT (dat2, 6); \ -+ next = 7; \ -+ } else if (next == 6) { \ -+ CVMX_MT_HSH_DAT (dat1, 6); \ -+ CVMX_MT_HSH_STARTMD5 (dat2); \ -+ next = 0; \ -+ } else { \ -+ CVMX_MT_HSH_STARTMD5 (dat1); \ -+ CVMX_MT_HSH_DAT (dat2, 0); \ -+ next = 1; \ -+ } \ -+} -+ -+/****************************************************************************/ -+ -+static inline uint64_t -+swap64(uint64_t a) -+{ -+ return ((a >> 56) | -+ (((a >> 48) & 0xfful) << 8) | -+ (((a >> 40) & 0xfful) << 16) | -+ (((a >> 32) & 0xfful) << 24) | -+ (((a >> 24) & 0xfful) << 32) | -+ (((a >> 16) & 0xfful) << 40) | -+ (((a >> 8) & 0xfful) << 48) | (((a >> 0) & 0xfful) << 56)); -+} -+ -+/****************************************************************************/ -+ -+void -+octo_calc_hash(__u8 auth, unsigned char *key, uint64_t *inner, uint64_t *outer) -+{ -+ uint8_t hash_key[64]; -+ uint64_t *key1; -+ register uint64_t xor1 = 0x3636363636363636ULL; -+ register uint64_t xor2 = 0x5c5c5c5c5c5c5c5cULL; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ memset(hash_key, 0, sizeof(hash_key)); -+ memcpy(hash_key, (uint8_t *) key, (auth ? 20 : 16)); -+ key1 = (uint64_t *) hash_key; -+ flags = octeon_crypto_enable(&state); -+ if (auth) { -+ CVMX_MT_HSH_IV(0x67452301EFCDAB89ULL, 0); -+ CVMX_MT_HSH_IV(0x98BADCFE10325476ULL, 1); -+ CVMX_MT_HSH_IV(0xC3D2E1F000000000ULL, 2); -+ } else { -+ CVMX_MT_HSH_IV(0x0123456789ABCDEFULL, 0); -+ CVMX_MT_HSH_IV(0xFEDCBA9876543210ULL, 1); -+ } -+ -+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 0); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 1); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 2); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 3); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 4); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 5); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 6); -+ key1++; -+ if (auth) -+ CVMX_MT_HSH_STARTSHA((*key1 ^ xor1)); -+ else -+ CVMX_MT_HSH_STARTMD5((*key1 ^ xor1)); -+ -+ CVMX_MF_HSH_IV(inner[0], 0); -+ CVMX_MF_HSH_IV(inner[1], 1); -+ if (auth) { -+ inner[2] = 0; -+ CVMX_MF_HSH_IV(((uint64_t *) inner)[2], 2); -+ } -+ -+ memset(hash_key, 0, sizeof(hash_key)); -+ memcpy(hash_key, (uint8_t *) key, (auth ? 20 : 16)); -+ key1 = (uint64_t *) hash_key; -+ if (auth) { -+ CVMX_MT_HSH_IV(0x67452301EFCDAB89ULL, 0); -+ CVMX_MT_HSH_IV(0x98BADCFE10325476ULL, 1); -+ CVMX_MT_HSH_IV(0xC3D2E1F000000000ULL, 2); -+ } else { -+ CVMX_MT_HSH_IV(0x0123456789ABCDEFULL, 0); -+ CVMX_MT_HSH_IV(0xFEDCBA9876543210ULL, 1); -+ } -+ -+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 0); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 1); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 2); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 3); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 4); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 5); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 6); -+ key1++; -+ if (auth) -+ CVMX_MT_HSH_STARTSHA((*key1 ^ xor2)); -+ else -+ CVMX_MT_HSH_STARTMD5((*key1 ^ xor2)); -+ -+ CVMX_MF_HSH_IV(outer[0], 0); -+ CVMX_MF_HSH_IV(outer[1], 1); -+ if (auth) { -+ outer[2] = 0; -+ CVMX_MF_HSH_IV(outer[2], 2); -+ } -+ octeon_crypto_disable(&state, flags); -+ return; -+} -+ -+/****************************************************************************/ -+/* DES functions */ -+ -+int -+octo_des_cbc_encrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ uint64_t *data; -+ int data_i, data_l; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x7) || (crypt_off + crypt_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load 3DES Key */ -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ if (od->octo_encklen == 24) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ } else if (od->octo_encklen == 8) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ -+ CVMX_MT_3DES_IV(* (uint64_t *) ivp); -+ -+ while (crypt_off > 0) { -+ SG_CONSUME(sg, data, data_i, data_l); -+ crypt_off -= 8; -+ } -+ -+ while (crypt_len > 0) { -+ CVMX_MT_3DES_ENC_CBC(*data); -+ CVMX_MF_3DES_RESULT(*data); -+ SG_CONSUME(sg, data, data_i, data_l); -+ crypt_len -= 8; -+ } -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+ -+int -+octo_des_cbc_decrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ uint64_t *data; -+ int data_i, data_l; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x7) || (crypt_off + crypt_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load 3DES Key */ -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ if (od->octo_encklen == 24) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ } else if (od->octo_encklen == 8) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ -+ CVMX_MT_3DES_IV(* (uint64_t *) ivp); -+ -+ while (crypt_off > 0) { -+ SG_CONSUME(sg, data, data_i, data_l); -+ crypt_off -= 8; -+ } -+ -+ while (crypt_len > 0) { -+ CVMX_MT_3DES_DEC_CBC(*data); -+ CVMX_MF_3DES_RESULT(*data); -+ SG_CONSUME(sg, data, data_i, data_l); -+ crypt_len -= 8; -+ } -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+/****************************************************************************/ -+/* AES functions */ -+ -+int -+octo_aes_cbc_encrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ uint64_t *data, *pdata; -+ int data_i, data_l; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x7) || (crypt_off + crypt_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load AES Key */ -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ -+ if (od->octo_encklen == 16) { -+ CVMX_MT_AES_KEY(0x0, 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 24) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 32) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); -+ -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); -+ -+ while (crypt_off > 0) { -+ SG_CONSUME(sg, data, data_i, data_l); -+ crypt_off -= 8; -+ } -+ -+ while (crypt_len > 0) { -+ pdata = data; -+ CVMX_MT_AES_ENC_CBC0(*data); -+ SG_CONSUME(sg, data, data_i, data_l); -+ CVMX_MT_AES_ENC_CBC1(*data); -+ CVMX_MF_AES_RESULT(*pdata, 0); -+ CVMX_MF_AES_RESULT(*data, 1); -+ SG_CONSUME(sg, data, data_i, data_l); -+ crypt_len -= 16; -+ } -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+ -+int -+octo_aes_cbc_decrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ uint64_t *data, *pdata; -+ int data_i, data_l; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x7) || (crypt_off + crypt_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load AES Key */ -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ -+ if (od->octo_encklen == 16) { -+ CVMX_MT_AES_KEY(0x0, 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 24) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 32) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); -+ -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); -+ -+ while (crypt_off > 0) { -+ SG_CONSUME(sg, data, data_i, data_l); -+ crypt_off -= 8; -+ } -+ -+ while (crypt_len > 0) { -+ pdata = data; -+ CVMX_MT_AES_DEC_CBC0(*data); -+ SG_CONSUME(sg, data, data_i, data_l); -+ CVMX_MT_AES_DEC_CBC1(*data); -+ CVMX_MF_AES_RESULT(*pdata, 0); -+ CVMX_MF_AES_RESULT(*data, 1); -+ SG_CONSUME(sg, data, data_i, data_l); -+ crypt_len -= 16; -+ } -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+/****************************************************************************/ -+/* MD5 */ -+ -+int -+octo_null_md5_encrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ uint64_t *data; -+ uint64_t tmp1, tmp2; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || -+ (auth_off & 0x7) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data, data_i, data_l); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* Load MD5 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ -+ while (auth_off > 0) { -+ SG_CONSUME(sg, data, data_i, data_l); -+ auth_off -= 8; -+ } -+ -+ while (auth_len > 0) { -+ CVM_LOAD_MD5_UNIT(*data, next); -+ auth_len -= 8; -+ SG_CONSUME(sg, data, data_i, data_l); -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_MD5_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVMX_ES64(tmp1, ((alen + 64) << 3)); -+ CVM_LOAD_MD5_UNIT(tmp1, next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_ES64(tmp1, ((64 + 16) << 3)); -+ CVMX_MT_HSH_STARTMD5(tmp1); -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data, data_i, data_l); -+ icv_off -= 8; -+ } -+ CVMX_MF_HSH_IV(*data, 0); -+ SG_CONSUME(sg, data, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *(uint32_t *)data = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+/****************************************************************************/ -+/* SHA1 */ -+ -+int -+octo_null_sha1_encrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ uint64_t *data; -+ uint64_t tmp1, tmp2, tmp3; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || -+ (auth_off & 0x7) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data, data_i, data_l); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* Load SHA1 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); -+ -+ while (auth_off > 0) { -+ SG_CONSUME(sg, data, data_i, data_l); -+ auth_off -= 8; -+ } -+ -+ while (auth_len > 0) { -+ CVM_LOAD_SHA_UNIT(*data, next); -+ auth_len -= 8; -+ SG_CONSUME(sg, data, data_i, data_l); -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_MD5_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ tmp3 = 0; -+ CVMX_MF_HSH_IV(tmp3, 2); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ tmp3 |= 0x0000000080000000; -+ CVMX_MT_HSH_DAT(tmp3, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data, data_i, data_l); -+ icv_off -= 8; -+ } -+ CVMX_MF_HSH_IV(*data, 0); -+ SG_CONSUME(sg, data, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *(uint32_t *)data = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+/****************************************************************************/ -+/* DES MD5 */ -+ -+int -+octo_des_cbc_md5_encrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ union { -+ uint32_t data32[2]; -+ uint64_t data64[1]; -+ } mydata; -+ uint64_t *data = &mydata.data64[0]; -+ uint32_t *data32; -+ uint64_t tmp1, tmp2; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || -+ (crypt_len & 0x7) || -+ (auth_len & 0x7) || -+ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data32, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load 3DES Key */ -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ if (od->octo_encklen == 24) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ } else if (od->octo_encklen == 8) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ -+ CVMX_MT_3DES_IV(* (uint64_t *) ivp); -+ -+ /* Load MD5 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ -+ while (crypt_off > 0 && auth_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ crypt_off -= 4; -+ auth_off -= 4; -+ } -+ -+ while (crypt_len > 0 || auth_len > 0) { -+ uint32_t *first = data32; -+ mydata.data32[0] = *first; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata.data32[1] = *data32; -+ if (crypt_off <= 0) { -+ if (crypt_len > 0) { -+ CVMX_MT_3DES_ENC_CBC(*data); -+ CVMX_MF_3DES_RESULT(*data); -+ crypt_len -= 8; -+ } -+ } else -+ crypt_off -= 8; -+ if (auth_off <= 0) { -+ if (auth_len > 0) { -+ CVM_LOAD_MD5_UNIT(*data, next); -+ auth_len -= 8; -+ } -+ } else -+ auth_off -= 8; -+ *first = mydata.data32[0]; -+ *data32 = mydata.data32[1]; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_MD5_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVMX_ES64(tmp1, ((alen + 64) << 3)); -+ CVM_LOAD_MD5_UNIT(tmp1, next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_ES64(tmp1, ((64 + 16) << 3)); -+ CVMX_MT_HSH_STARTMD5(tmp1); -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data32, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ icv_off -= 4; -+ } -+ CVMX_MF_HSH_IV(tmp1, 0); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ SG_CONSUME(sg, data32, data_i, data_l); -+ *data32 = (uint32_t) tmp1; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+int -+octo_des_cbc_md5_decrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ union { -+ uint32_t data32[2]; -+ uint64_t data64[1]; -+ } mydata; -+ uint64_t *data = &mydata.data64[0]; -+ uint32_t *data32; -+ uint64_t tmp1, tmp2; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || -+ (crypt_len & 0x7) || -+ (auth_len & 0x7) || -+ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data32, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load 3DES Key */ -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ if (od->octo_encklen == 24) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ } else if (od->octo_encklen == 8) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ -+ CVMX_MT_3DES_IV(* (uint64_t *) ivp); -+ -+ /* Load MD5 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ -+ while (crypt_off > 0 && auth_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ crypt_off -= 4; -+ auth_off -= 4; -+ } -+ -+ while (crypt_len > 0 || auth_len > 0) { -+ uint32_t *first = data32; -+ mydata.data32[0] = *first; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata.data32[1] = *data32; -+ if (auth_off <= 0) { -+ if (auth_len > 0) { -+ CVM_LOAD_MD5_UNIT(*data, next); -+ auth_len -= 8; -+ } -+ } else -+ auth_off -= 8; -+ if (crypt_off <= 0) { -+ if (crypt_len > 0) { -+ CVMX_MT_3DES_DEC_CBC(*data); -+ CVMX_MF_3DES_RESULT(*data); -+ crypt_len -= 8; -+ } -+ } else -+ crypt_off -= 8; -+ *first = mydata.data32[0]; -+ *data32 = mydata.data32[1]; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_MD5_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVMX_ES64(tmp1, ((alen + 64) << 3)); -+ CVM_LOAD_MD5_UNIT(tmp1, next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_ES64(tmp1, ((64 + 16) << 3)); -+ CVMX_MT_HSH_STARTMD5(tmp1); -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data32, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ icv_off -= 4; -+ } -+ CVMX_MF_HSH_IV(tmp1, 0); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ SG_CONSUME(sg, data32, data_i, data_l); -+ *data32 = (uint32_t) tmp1; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+/****************************************************************************/ -+/* DES SHA */ -+ -+int -+octo_des_cbc_sha1_encrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ union { -+ uint32_t data32[2]; -+ uint64_t data64[1]; -+ } mydata; -+ uint64_t *data = &mydata.data64[0]; -+ uint32_t *data32; -+ uint64_t tmp1, tmp2, tmp3; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || -+ (crypt_len & 0x7) || -+ (auth_len & 0x7) || -+ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data32, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load 3DES Key */ -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ if (od->octo_encklen == 24) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ } else if (od->octo_encklen == 8) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ -+ CVMX_MT_3DES_IV(* (uint64_t *) ivp); -+ -+ /* Load SHA1 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); -+ -+ while (crypt_off > 0 && auth_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ crypt_off -= 4; -+ auth_off -= 4; -+ } -+ -+ while (crypt_len > 0 || auth_len > 0) { -+ uint32_t *first = data32; -+ mydata.data32[0] = *first; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata.data32[1] = *data32; -+ if (crypt_off <= 0) { -+ if (crypt_len > 0) { -+ CVMX_MT_3DES_ENC_CBC(*data); -+ CVMX_MF_3DES_RESULT(*data); -+ crypt_len -= 8; -+ } -+ } else -+ crypt_off -= 8; -+ if (auth_off <= 0) { -+ if (auth_len > 0) { -+ CVM_LOAD_SHA_UNIT(*data, next); -+ auth_len -= 8; -+ } -+ } else -+ auth_off -= 8; -+ *first = mydata.data32[0]; -+ *data32 = mydata.data32[1]; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_SHA_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ tmp3 = 0; -+ CVMX_MF_HSH_IV(tmp3, 2); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ tmp3 |= 0x0000000080000000; -+ CVMX_MT_HSH_DAT(tmp3, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data32, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ icv_off -= 4; -+ } -+ CVMX_MF_HSH_IV(tmp1, 0); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ SG_CONSUME(sg, data32, data_i, data_l); -+ *data32 = (uint32_t) tmp1; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+int -+octo_des_cbc_sha1_decrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ union { -+ uint32_t data32[2]; -+ uint64_t data64[1]; -+ } mydata; -+ uint64_t *data = &mydata.data64[0]; -+ uint32_t *data32; -+ uint64_t tmp1, tmp2, tmp3; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || -+ (crypt_len & 0x7) || -+ (auth_len & 0x7) || -+ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data32, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load 3DES Key */ -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ if (od->octo_encklen == 24) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ } else if (od->octo_encklen == 8) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ -+ CVMX_MT_3DES_IV(* (uint64_t *) ivp); -+ -+ /* Load SHA1 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); -+ -+ while (crypt_off > 0 && auth_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ crypt_off -= 4; -+ auth_off -= 4; -+ } -+ -+ while (crypt_len > 0 || auth_len > 0) { -+ uint32_t *first = data32; -+ mydata.data32[0] = *first; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata.data32[1] = *data32; -+ if (auth_off <= 0) { -+ if (auth_len > 0) { -+ CVM_LOAD_SHA_UNIT(*data, next); -+ auth_len -= 8; -+ } -+ } else -+ auth_off -= 8; -+ if (crypt_off <= 0) { -+ if (crypt_len > 0) { -+ CVMX_MT_3DES_DEC_CBC(*data); -+ CVMX_MF_3DES_RESULT(*data); -+ crypt_len -= 8; -+ } -+ } else -+ crypt_off -= 8; -+ *first = mydata.data32[0]; -+ *data32 = mydata.data32[1]; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_SHA_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ tmp3 = 0; -+ CVMX_MF_HSH_IV(tmp3, 2); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ tmp3 |= 0x0000000080000000; -+ CVMX_MT_HSH_DAT(tmp3, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); -+ /* save the HMAC */ -+ SG_INIT(sg, data32, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ icv_off -= 4; -+ } -+ CVMX_MF_HSH_IV(tmp1, 0); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ SG_CONSUME(sg, data32, data_i, data_l); -+ *data32 = (uint32_t) tmp1; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+/****************************************************************************/ -+/* AES MD5 */ -+ -+int -+octo_aes_cbc_md5_encrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ union { -+ uint32_t data32[2]; -+ uint64_t data64[1]; -+ } mydata[2]; -+ uint64_t *pdata = &mydata[0].data64[0]; -+ uint64_t *data = &mydata[1].data64[0]; -+ uint32_t *data32; -+ uint64_t tmp1, tmp2; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || -+ (crypt_len & 0x7) || -+ (auth_len & 0x7) || -+ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data32, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load AES Key */ -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ -+ if (od->octo_encklen == 16) { -+ CVMX_MT_AES_KEY(0x0, 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 24) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 32) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); -+ -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); -+ -+ /* Load MD5 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ -+ while (crypt_off > 0 && auth_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ crypt_off -= 4; -+ auth_off -= 4; -+ } -+ -+ /* align auth and crypt */ -+ while (crypt_off > 0 && auth_len > 0) { -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVM_LOAD_MD5_UNIT(*pdata, next); -+ crypt_off -= 8; -+ auth_len -= 8; -+ } -+ -+ while (crypt_len > 0) { -+ uint32_t *pdata32[3]; -+ -+ pdata32[0] = data32; -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ -+ pdata32[1] = data32; -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ -+ pdata32[2] = data32; -+ mydata[1].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ -+ mydata[1].data32[1] = *data32; -+ -+ CVMX_MT_AES_ENC_CBC0(*pdata); -+ CVMX_MT_AES_ENC_CBC1(*data); -+ CVMX_MF_AES_RESULT(*pdata, 0); -+ CVMX_MF_AES_RESULT(*data, 1); -+ crypt_len -= 16; -+ -+ if (auth_len > 0) { -+ CVM_LOAD_MD5_UNIT(*pdata, next); -+ auth_len -= 8; -+ } -+ if (auth_len > 0) { -+ CVM_LOAD_MD5_UNIT(*data, next); -+ auth_len -= 8; -+ } -+ -+ *pdata32[0] = mydata[0].data32[0]; -+ *pdata32[1] = mydata[0].data32[1]; -+ *pdata32[2] = mydata[1].data32[0]; -+ *data32 = mydata[1].data32[1]; -+ -+ SG_CONSUME(sg, data32, data_i, data_l); -+ } -+ -+ /* finish any left over hashing */ -+ while (auth_len > 0) { -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVM_LOAD_MD5_UNIT(*pdata, next); -+ auth_len -= 8; -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_MD5_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVMX_ES64(tmp1, ((alen + 64) << 3)); -+ CVM_LOAD_MD5_UNIT(tmp1, next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_ES64(tmp1, ((64 + 16) << 3)); -+ CVMX_MT_HSH_STARTMD5(tmp1); -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data32, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ icv_off -= 4; -+ } -+ CVMX_MF_HSH_IV(tmp1, 0); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ SG_CONSUME(sg, data32, data_i, data_l); -+ *data32 = (uint32_t) tmp1; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+int -+octo_aes_cbc_md5_decrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ union { -+ uint32_t data32[2]; -+ uint64_t data64[1]; -+ } mydata[2]; -+ uint64_t *pdata = &mydata[0].data64[0]; -+ uint64_t *data = &mydata[1].data64[0]; -+ uint32_t *data32; -+ uint64_t tmp1, tmp2; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || -+ (crypt_len & 0x7) || -+ (auth_len & 0x7) || -+ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data32, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load AES Key */ -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ -+ if (od->octo_encklen == 16) { -+ CVMX_MT_AES_KEY(0x0, 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 24) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 32) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); -+ -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); -+ -+ /* Load MD5 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ -+ while (crypt_off > 0 && auth_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ crypt_off -= 4; -+ auth_off -= 4; -+ } -+ -+ /* align auth and crypt */ -+ while (crypt_off > 0 && auth_len > 0) { -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVM_LOAD_MD5_UNIT(*pdata, next); -+ crypt_off -= 8; -+ auth_len -= 8; -+ } -+ -+ while (crypt_len > 0) { -+ uint32_t *pdata32[3]; -+ -+ pdata32[0] = data32; -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ pdata32[1] = data32; -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ pdata32[2] = data32; -+ mydata[1].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[1].data32[1] = *data32; -+ -+ if (auth_len > 0) { -+ CVM_LOAD_MD5_UNIT(*pdata, next); -+ auth_len -= 8; -+ } -+ -+ if (auth_len > 0) { -+ CVM_LOAD_MD5_UNIT(*data, next); -+ auth_len -= 8; -+ } -+ -+ CVMX_MT_AES_DEC_CBC0(*pdata); -+ CVMX_MT_AES_DEC_CBC1(*data); -+ CVMX_MF_AES_RESULT(*pdata, 0); -+ CVMX_MF_AES_RESULT(*data, 1); -+ crypt_len -= 16; -+ -+ *pdata32[0] = mydata[0].data32[0]; -+ *pdata32[1] = mydata[0].data32[1]; -+ *pdata32[2] = mydata[1].data32[0]; -+ *data32 = mydata[1].data32[1]; -+ -+ SG_CONSUME(sg, data32, data_i, data_l); -+ } -+ -+ /* finish left over hash if any */ -+ while (auth_len > 0) { -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVM_LOAD_MD5_UNIT(*pdata, next); -+ auth_len -= 8; -+ } -+ -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_MD5_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVMX_ES64(tmp1, ((alen + 64) << 3)); -+ CVM_LOAD_MD5_UNIT(tmp1, next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_ES64(tmp1, ((64 + 16) << 3)); -+ CVMX_MT_HSH_STARTMD5(tmp1); -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data32, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ icv_off -= 4; -+ } -+ CVMX_MF_HSH_IV(tmp1, 0); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ SG_CONSUME(sg, data32, data_i, data_l); -+ *data32 = (uint32_t) tmp1; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+/****************************************************************************/ -+/* AES SHA1 */ -+ -+int -+octo_aes_cbc_sha1_encrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ union { -+ uint32_t data32[2]; -+ uint64_t data64[1]; -+ } mydata[2]; -+ uint64_t *pdata = &mydata[0].data64[0]; -+ uint64_t *data = &mydata[1].data64[0]; -+ uint32_t *data32; -+ uint64_t tmp1, tmp2, tmp3; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s(a_off=%d a_len=%d c_off=%d c_len=%d icv_off=%d)\n", -+ __FUNCTION__, auth_off, auth_len, crypt_off, crypt_len, icv_off); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || -+ (crypt_len & 0x7) || -+ (auth_len & 0x7) || -+ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data32, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load AES Key */ -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ -+ if (od->octo_encklen == 16) { -+ CVMX_MT_AES_KEY(0x0, 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 24) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 32) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); -+ -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); -+ -+ /* Load SHA IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); -+ -+ while (crypt_off > 0 && auth_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ crypt_off -= 4; -+ auth_off -= 4; -+ } -+ -+ /* align auth and crypt */ -+ while (crypt_off > 0 && auth_len > 0) { -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVM_LOAD_SHA_UNIT(*pdata, next); -+ crypt_off -= 8; -+ auth_len -= 8; -+ } -+ -+ while (crypt_len > 0) { -+ uint32_t *pdata32[3]; -+ -+ pdata32[0] = data32; -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ pdata32[1] = data32; -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ pdata32[2] = data32; -+ mydata[1].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[1].data32[1] = *data32; -+ -+ CVMX_MT_AES_ENC_CBC0(*pdata); -+ CVMX_MT_AES_ENC_CBC1(*data); -+ CVMX_MF_AES_RESULT(*pdata, 0); -+ CVMX_MF_AES_RESULT(*data, 1); -+ crypt_len -= 16; -+ -+ if (auth_len > 0) { -+ CVM_LOAD_SHA_UNIT(*pdata, next); -+ auth_len -= 8; -+ } -+ if (auth_len > 0) { -+ CVM_LOAD_SHA_UNIT(*data, next); -+ auth_len -= 8; -+ } -+ -+ *pdata32[0] = mydata[0].data32[0]; -+ *pdata32[1] = mydata[0].data32[1]; -+ *pdata32[2] = mydata[1].data32[0]; -+ *data32 = mydata[1].data32[1]; -+ -+ SG_CONSUME(sg, data32, data_i, data_l); -+ } -+ -+ /* finish and hashing */ -+ while (auth_len > 0) { -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVM_LOAD_SHA_UNIT(*pdata, next); -+ auth_len -= 8; -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_SHA_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ tmp3 = 0; -+ CVMX_MF_HSH_IV(tmp3, 2); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ tmp3 |= 0x0000000080000000; -+ CVMX_MT_HSH_DAT(tmp3, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_MD5_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data32, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ icv_off -= 4; -+ } -+ CVMX_MF_HSH_IV(tmp1, 0); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ SG_CONSUME(sg, data32, data_i, data_l); -+ *data32 = (uint32_t) tmp1; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+int -+octo_aes_cbc_sha1_decrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ union { -+ uint32_t data32[2]; -+ uint64_t data64[1]; -+ } mydata[2]; -+ uint64_t *pdata = &mydata[0].data64[0]; -+ uint64_t *data = &mydata[1].data64[0]; -+ uint32_t *data32; -+ uint64_t tmp1, tmp2, tmp3; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s(a_off=%d a_len=%d c_off=%d c_len=%d icv_off=%d)\n", -+ __FUNCTION__, auth_off, auth_len, crypt_off, crypt_len, icv_off); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || -+ (crypt_len & 0x7) || -+ (auth_len & 0x7) || -+ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data32, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load AES Key */ -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ -+ if (od->octo_encklen == 16) { -+ CVMX_MT_AES_KEY(0x0, 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 24) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 32) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); -+ -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); -+ -+ /* Load SHA1 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); -+ -+ while (crypt_off > 0 && auth_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ crypt_off -= 4; -+ auth_off -= 4; -+ } -+ -+ /* align auth and crypt */ -+ while (crypt_off > 0 && auth_len > 0) { -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVM_LOAD_SHA_UNIT(*pdata, next); -+ crypt_off -= 8; -+ auth_len -= 8; -+ } -+ -+ while (crypt_len > 0) { -+ uint32_t *pdata32[3]; -+ -+ pdata32[0] = data32; -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ pdata32[1] = data32; -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ pdata32[2] = data32; -+ mydata[1].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[1].data32[1] = *data32; -+ -+ if (auth_len > 0) { -+ CVM_LOAD_SHA_UNIT(*pdata, next); -+ auth_len -= 8; -+ } -+ if (auth_len > 0) { -+ CVM_LOAD_SHA_UNIT(*data, next); -+ auth_len -= 8; -+ } -+ -+ CVMX_MT_AES_DEC_CBC0(*pdata); -+ CVMX_MT_AES_DEC_CBC1(*data); -+ CVMX_MF_AES_RESULT(*pdata, 0); -+ CVMX_MF_AES_RESULT(*data, 1); -+ crypt_len -= 16; -+ -+ *pdata32[0] = mydata[0].data32[0]; -+ *pdata32[1] = mydata[0].data32[1]; -+ *pdata32[2] = mydata[1].data32[0]; -+ *data32 = mydata[1].data32[1]; -+ -+ SG_CONSUME(sg, data32, data_i, data_l); -+ } -+ -+ /* finish and leftover hashing */ -+ while (auth_len > 0) { -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVM_LOAD_SHA_UNIT(*pdata, next); -+ auth_len -= 8; -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_SHA_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ tmp3 = 0; -+ CVMX_MF_HSH_IV(tmp3, 2); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ tmp3 |= 0x0000000080000000; -+ CVMX_MT_HSH_DAT(tmp3, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_MD5_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data32, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ icv_off -= 4; -+ } -+ CVMX_MF_HSH_IV(tmp1, 0); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ SG_CONSUME(sg, data32, data_i, data_l); -+ *data32 = (uint32_t) tmp1; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+/****************************************************************************/ -diff -Nur linux-2.6.36.orig/crypto/ocf/cryptocteon/cryptocteon.c linux-2.6.36/crypto/ocf/cryptocteon/cryptocteon.c ---- linux-2.6.36.orig/crypto/ocf/cryptocteon/cryptocteon.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/cryptocteon/cryptocteon.c 2010-11-09 20:28:04.371247488 +0100 -@@ -0,0 +1,574 @@ -+/* -+ * Octeon Crypto for OCF -+ * -+ * Written by David McCullough -+ * Copyright (C) 2009-2010 David McCullough -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ * --------------------------------------------------------------------------- -+ */ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+struct { -+ softc_device_decl sc_dev; -+} octo_softc; -+ -+#define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK) -+ -+struct octo_sess { -+ int octo_encalg; -+ #define MAX_CIPHER_KEYLEN 64 -+ char octo_enckey[MAX_CIPHER_KEYLEN]; -+ int octo_encklen; -+ -+ int octo_macalg; -+ #define MAX_HASH_KEYLEN 64 -+ char octo_mackey[MAX_HASH_KEYLEN]; -+ int octo_macklen; -+ int octo_mackey_set; -+ -+ int octo_mlen; -+ int octo_ivsize; -+ -+#if 0 -+ int (*octo_decrypt)(struct scatterlist *sg, int sg_len, -+ uint8_t *key, int key_len, uint8_t * iv, -+ uint64_t *hminner, uint64_t *hmouter); -+ -+ int (*octo_encrypt)(struct scatterlist *sg, int sg_len, -+ uint8_t *key, int key_len, uint8_t * iv, -+ uint64_t *hminner, uint64_t *hmouter); -+#else -+ int (*octo_encrypt)(struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp); -+ int (*octo_decrypt)(struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp); -+#endif -+ -+ uint64_t octo_hminner[3]; -+ uint64_t octo_hmouter[3]; -+}; -+ -+int32_t octo_id = -1; -+module_param(octo_id, int, 0444); -+MODULE_PARM_DESC(octo_id, "Read-Only OCF ID for cryptocteon driver"); -+ -+static struct octo_sess **octo_sessions = NULL; -+static u_int32_t octo_sesnum = 0; -+ -+static int octo_process(device_t, struct cryptop *, int); -+static int octo_newsession(device_t, u_int32_t *, struct cryptoini *); -+static int octo_freesession(device_t, u_int64_t); -+ -+static device_method_t octo_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, octo_newsession), -+ DEVMETHOD(cryptodev_freesession,octo_freesession), -+ DEVMETHOD(cryptodev_process, octo_process), -+}; -+ -+#define debug octo_debug -+int octo_debug = 0; -+module_param(octo_debug, int, 0644); -+MODULE_PARM_DESC(octo_debug, "Enable debug"); -+ -+ -+#include "cavium_crypto.c" -+ -+ -+/* -+ * Generate a new octo session. We artifically limit it to a single -+ * hash/cipher or hash-cipher combo just to make it easier, most callers -+ * do not expect more than this anyway. -+ */ -+static int -+octo_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) -+{ -+ struct cryptoini *c, *encini = NULL, *macini = NULL; -+ struct octo_sess **ocd; -+ int i; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid == NULL || cri == NULL) { -+ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ /* -+ * To keep it simple, we only handle hash, cipher or hash/cipher in a -+ * session, you cannot currently do multiple ciphers/hashes in one -+ * session even though it would be possibel to code this driver to -+ * handle it. -+ */ -+ for (i = 0, c = cri; c && i < 2; i++) { -+ if (c->cri_alg == CRYPTO_MD5_HMAC || -+ c->cri_alg == CRYPTO_SHA1_HMAC || -+ c->cri_alg == CRYPTO_NULL_HMAC) { -+ if (macini) { -+ break; -+ } -+ macini = c; -+ } -+ if (c->cri_alg == CRYPTO_DES_CBC || -+ c->cri_alg == CRYPTO_3DES_CBC || -+ c->cri_alg == CRYPTO_AES_CBC || -+ c->cri_alg == CRYPTO_NULL_CBC) { -+ if (encini) { -+ break; -+ } -+ encini = c; -+ } -+ c = c->cri_next; -+ } -+ if (!macini && !encini) { -+ dprintk("%s,%d - EINVAL bad cipher/hash or combination\n", -+ __FILE__, __LINE__); -+ return EINVAL; -+ } -+ if (c) { -+ dprintk("%s,%d - EINVAL cannot handle chained cipher/hash combos\n", -+ __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ /* -+ * So we have something we can do, lets setup the session -+ */ -+ -+ if (octo_sessions) { -+ for (i = 1; i < octo_sesnum; i++) -+ if (octo_sessions[i] == NULL) -+ break; -+ } else -+ i = 1; /* NB: to silence compiler warning */ -+ -+ if (octo_sessions == NULL || i == octo_sesnum) { -+ if (octo_sessions == NULL) { -+ i = 1; /* We leave octo_sessions[0] empty */ -+ octo_sesnum = CRYPTO_SW_SESSIONS; -+ } else -+ octo_sesnum *= 2; -+ -+ ocd = kmalloc(octo_sesnum * sizeof(struct octo_sess *), SLAB_ATOMIC); -+ if (ocd == NULL) { -+ /* Reset session number */ -+ if (octo_sesnum == CRYPTO_SW_SESSIONS) -+ octo_sesnum = 0; -+ else -+ octo_sesnum /= 2; -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memset(ocd, 0, octo_sesnum * sizeof(struct octo_sess *)); -+ -+ /* Copy existing sessions */ -+ if (octo_sessions) { -+ memcpy(ocd, octo_sessions, -+ (octo_sesnum / 2) * sizeof(struct octo_sess *)); -+ kfree(octo_sessions); -+ } -+ -+ octo_sessions = ocd; -+ } -+ -+ ocd = &octo_sessions[i]; -+ *sid = i; -+ -+ -+ *ocd = (struct octo_sess *) kmalloc(sizeof(struct octo_sess), SLAB_ATOMIC); -+ if (*ocd == NULL) { -+ octo_freesession(NULL, i); -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memset(*ocd, 0, sizeof(struct octo_sess)); -+ -+ if (encini && encini->cri_key) { -+ (*ocd)->octo_encklen = (encini->cri_klen + 7) / 8; -+ memcpy((*ocd)->octo_enckey, encini->cri_key, (*ocd)->octo_encklen); -+ } -+ -+ if (macini && macini->cri_key) { -+ (*ocd)->octo_macklen = (macini->cri_klen + 7) / 8; -+ memcpy((*ocd)->octo_mackey, macini->cri_key, (*ocd)->octo_macklen); -+ } -+ -+ (*ocd)->octo_mlen = 0; -+ if (encini && encini->cri_mlen) -+ (*ocd)->octo_mlen = encini->cri_mlen; -+ else if (macini && macini->cri_mlen) -+ (*ocd)->octo_mlen = macini->cri_mlen; -+ else -+ (*ocd)->octo_mlen = 12; -+ -+ /* -+ * point c at the enc if it exists, otherwise the mac -+ */ -+ c = encini ? encini : macini; -+ -+ switch (c->cri_alg) { -+ case CRYPTO_DES_CBC: -+ case CRYPTO_3DES_CBC: -+ (*ocd)->octo_ivsize = 8; -+ switch (macini ? macini->cri_alg : -1) { -+ case CRYPTO_MD5_HMAC: -+ (*ocd)->octo_encrypt = octo_des_cbc_md5_encrypt; -+ (*ocd)->octo_decrypt = octo_des_cbc_md5_decrypt; -+ octo_calc_hash(0, macini->cri_key, (*ocd)->octo_hminner, -+ (*ocd)->octo_hmouter); -+ break; -+ case CRYPTO_SHA1_HMAC: -+ (*ocd)->octo_encrypt = octo_des_cbc_sha1_encrypt; -+ (*ocd)->octo_decrypt = octo_des_cbc_sha1_encrypt; -+ octo_calc_hash(1, macini->cri_key, (*ocd)->octo_hminner, -+ (*ocd)->octo_hmouter); -+ break; -+ case -1: -+ (*ocd)->octo_encrypt = octo_des_cbc_encrypt; -+ (*ocd)->octo_decrypt = octo_des_cbc_decrypt; -+ break; -+ default: -+ octo_freesession(NULL, i); -+ dprintk("%s,%d: EINVALn", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ break; -+ case CRYPTO_AES_CBC: -+ (*ocd)->octo_ivsize = 16; -+ switch (macini ? macini->cri_alg : -1) { -+ case CRYPTO_MD5_HMAC: -+ (*ocd)->octo_encrypt = octo_aes_cbc_md5_encrypt; -+ (*ocd)->octo_decrypt = octo_aes_cbc_md5_decrypt; -+ octo_calc_hash(0, macini->cri_key, (*ocd)->octo_hminner, -+ (*ocd)->octo_hmouter); -+ break; -+ case CRYPTO_SHA1_HMAC: -+ (*ocd)->octo_encrypt = octo_aes_cbc_sha1_encrypt; -+ (*ocd)->octo_decrypt = octo_aes_cbc_sha1_decrypt; -+ octo_calc_hash(1, macini->cri_key, (*ocd)->octo_hminner, -+ (*ocd)->octo_hmouter); -+ break; -+ case -1: -+ (*ocd)->octo_encrypt = octo_aes_cbc_encrypt; -+ (*ocd)->octo_decrypt = octo_aes_cbc_decrypt; -+ break; -+ default: -+ octo_freesession(NULL, i); -+ dprintk("%s,%d: EINVALn", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ break; -+ case CRYPTO_MD5_HMAC: -+ (*ocd)->octo_encrypt = octo_null_md5_encrypt; -+ (*ocd)->octo_decrypt = octo_null_md5_encrypt; -+ octo_calc_hash(0, macini->cri_key, (*ocd)->octo_hminner, -+ (*ocd)->octo_hmouter); -+ break; -+ case CRYPTO_SHA1_HMAC: -+ (*ocd)->octo_encrypt = octo_null_sha1_encrypt; -+ (*ocd)->octo_decrypt = octo_null_sha1_encrypt; -+ octo_calc_hash(1, macini->cri_key, (*ocd)->octo_hminner, -+ (*ocd)->octo_hmouter); -+ break; -+ default: -+ octo_freesession(NULL, i); -+ dprintk("%s,%d: EINVALn", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ (*ocd)->octo_encalg = encini ? encini->cri_alg : -1; -+ (*ocd)->octo_macalg = macini ? macini->cri_alg : -1; -+ -+ return 0; -+} -+ -+/* -+ * Free a session. -+ */ -+static int -+octo_freesession(device_t dev, u_int64_t tid) -+{ -+ u_int32_t sid = CRYPTO_SESID2LID(tid); -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid > octo_sesnum || octo_sessions == NULL || -+ octo_sessions[sid] == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return(EINVAL); -+ } -+ -+ /* Silently accept and return */ -+ if (sid == 0) -+ return(0); -+ -+ if (octo_sessions[sid]) -+ kfree(octo_sessions[sid]); -+ octo_sessions[sid] = NULL; -+ return 0; -+} -+ -+/* -+ * Process a request. -+ */ -+static int -+octo_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ struct cryptodesc *crd; -+ struct octo_sess *od; -+ u_int32_t lid; -+#define SCATTERLIST_MAX 16 -+ struct scatterlist sg[SCATTERLIST_MAX]; -+ int sg_num, sg_len; -+ struct sk_buff *skb = NULL; -+ struct uio *uiop = NULL; -+ struct cryptodesc *enccrd = NULL, *maccrd = NULL; -+ unsigned char *ivp = NULL; -+ unsigned char iv_data[HASH_MAX_LEN]; -+ int auth_off = 0, auth_len = 0, crypt_off = 0, crypt_len = 0, icv_off = 0; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ /* Sanity check */ -+ if (crp == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ crp->crp_etype = 0; -+ -+ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ lid = crp->crp_sid & 0xffffffff; -+ if (lid >= octo_sesnum || lid == 0 || octo_sessions == NULL || -+ octo_sessions[lid] == NULL) { -+ crp->crp_etype = ENOENT; -+ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); -+ goto done; -+ } -+ od = octo_sessions[lid]; -+ -+ /* -+ * do some error checking outside of the loop for SKB and IOV processing -+ * this leaves us with valid skb or uiop pointers for later -+ */ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ skb = (struct sk_buff *) crp->crp_buf; -+ if (skb_shinfo(skb)->nr_frags >= SCATTERLIST_MAX) { -+ printk("%s,%d: %d nr_frags > SCATTERLIST_MAX", __FILE__, __LINE__, -+ skb_shinfo(skb)->nr_frags); -+ goto done; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ uiop = (struct uio *) crp->crp_buf; -+ if (uiop->uio_iovcnt > SCATTERLIST_MAX) { -+ printk("%s,%d: %d uio_iovcnt > SCATTERLIST_MAX", __FILE__, __LINE__, -+ uiop->uio_iovcnt); -+ goto done; -+ } -+ } -+ -+ /* point our enccrd and maccrd appropriately */ -+ crd = crp->crp_desc; -+ if (crd->crd_alg == od->octo_encalg) enccrd = crd; -+ if (crd->crd_alg == od->octo_macalg) maccrd = crd; -+ crd = crd->crd_next; -+ if (crd) { -+ if (crd->crd_alg == od->octo_encalg) enccrd = crd; -+ if (crd->crd_alg == od->octo_macalg) maccrd = crd; -+ crd = crd->crd_next; -+ } -+ if (crd) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: ENOENT - descriptors do not match session\n", -+ __FILE__, __LINE__); -+ goto done; -+ } -+ -+ if (enccrd) { -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) { -+ ivp = enccrd->crd_iv; -+ } else { -+ ivp = iv_data; -+ crypto_copydata(crp->crp_flags, crp->crp_buf, -+ enccrd->crd_inject, od->octo_ivsize, (caddr_t) ivp); -+ } -+ -+ if (maccrd) { -+ auth_off = maccrd->crd_skip; -+ auth_len = maccrd->crd_len; -+ icv_off = maccrd->crd_inject; -+ } -+ -+ crypt_off = enccrd->crd_skip; -+ crypt_len = enccrd->crd_len; -+ } else { /* if (maccrd) */ -+ auth_off = maccrd->crd_skip; -+ auth_len = maccrd->crd_len; -+ icv_off = maccrd->crd_inject; -+ } -+ -+ -+ /* -+ * setup the SG list to cover the buffer -+ */ -+ memset(sg, 0, sizeof(sg)); -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ int i, len; -+ -+ sg_num = 0; -+ sg_len = 0; -+ -+ len = skb_headlen(skb); -+ sg_set_page(&sg[sg_num], virt_to_page(skb->data), len, -+ offset_in_page(skb->data)); -+ sg_len += len; -+ sg_num++; -+ -+ for (i = 0; i < skb_shinfo(skb)->nr_frags && sg_num < SCATTERLIST_MAX; -+ i++) { -+ len = skb_shinfo(skb)->frags[i].size; -+ sg_set_page(&sg[sg_num], skb_shinfo(skb)->frags[i].page, -+ len, skb_shinfo(skb)->frags[i].page_offset); -+ sg_len += len; -+ sg_num++; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ int len; -+ -+ sg_len = 0; -+ for (sg_num = 0; sg_len < crp->crp_ilen && -+ sg_num < uiop->uio_iovcnt && -+ sg_num < SCATTERLIST_MAX; sg_num++) { -+ len = uiop->uio_iov[sg_num].iov_len; -+ sg_set_page(&sg[sg_num], -+ virt_to_page(uiop->uio_iov[sg_num].iov_base), len, -+ offset_in_page(uiop->uio_iov[sg_num].iov_base)); -+ sg_len += len; -+ } -+ } else { -+ sg_len = crp->crp_ilen; -+ sg_set_page(&sg[0], virt_to_page(crp->crp_buf), sg_len, -+ offset_in_page(crp->crp_buf)); -+ sg_num = 1; -+ } -+ -+ -+ /* -+ * setup a new explicit key -+ */ -+ if (enccrd) { -+ if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) { -+ od->octo_encklen = (enccrd->crd_klen + 7) / 8; -+ memcpy(od->octo_enckey, enccrd->crd_key, od->octo_encklen); -+ } -+ } -+ if (maccrd) { -+ if (maccrd->crd_flags & CRD_F_KEY_EXPLICIT) { -+ od->octo_macklen = (maccrd->crd_klen + 7) / 8; -+ memcpy(od->octo_mackey, maccrd->crd_key, od->octo_macklen); -+ od->octo_mackey_set = 0; -+ } -+ if (!od->octo_mackey_set) { -+ octo_calc_hash(maccrd->crd_alg == CRYPTO_MD5_HMAC ? 0 : 1, -+ maccrd->crd_key, od->octo_hminner, od->octo_hmouter); -+ od->octo_mackey_set = 1; -+ } -+ } -+ -+ -+ if (!enccrd || (enccrd->crd_flags & CRD_F_ENCRYPT)) -+ (*od->octo_encrypt)(od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ else -+ (*od->octo_decrypt)(od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ -+done: -+ crypto_done(crp); -+ return 0; -+} -+ -+static int -+cryptocteon_init(void) -+{ -+ dprintk("%s(%p)\n", __FUNCTION__, cryptocteon_init); -+ -+ softc_device_init(&octo_softc, "cryptocteon", 0, octo_methods); -+ -+ octo_id = crypto_get_driverid(softc_get_device(&octo_softc), -+ CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SYNC); -+ if (octo_id < 0) { -+ printk("Cryptocteon device cannot initialize!"); -+ return -ENODEV; -+ } -+ -+ crypto_register(octo_id, CRYPTO_MD5_HMAC, 0,0); -+ crypto_register(octo_id, CRYPTO_SHA1_HMAC, 0,0); -+ //crypto_register(octo_id, CRYPTO_MD5, 0,0); -+ //crypto_register(octo_id, CRYPTO_SHA1, 0,0); -+ crypto_register(octo_id, CRYPTO_DES_CBC, 0,0); -+ crypto_register(octo_id, CRYPTO_3DES_CBC, 0,0); -+ crypto_register(octo_id, CRYPTO_AES_CBC, 0,0); -+ -+ return(0); -+} -+ -+static void -+cryptocteon_exit(void) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ crypto_unregister_all(octo_id); -+ octo_id = -1; -+} -+ -+module_init(cryptocteon_init); -+module_exit(cryptocteon_exit); -+ -+MODULE_LICENSE("BSD"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("Cryptocteon (OCF module for Cavium OCTEON crypto)"); -diff -Nur linux-2.6.36.orig/crypto/ocf/cryptocteon/Makefile linux-2.6.36/crypto/ocf/cryptocteon/Makefile ---- linux-2.6.36.orig/crypto/ocf/cryptocteon/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/cryptocteon/Makefile 2010-11-09 20:28:04.411246358 +0100 -@@ -0,0 +1,17 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+obj-$(CONFIG_OCF_CRYPTOCTEON) += cryptocteon.o -+ -+obj ?= . -+EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ -+ -+ifdef CONFIG_OCF_CRYPTOCTEON -+# you need the cavium crypto component installed -+EXTRA_CFLAGS += -I$(ROOTDIR)/prop/include -+endif -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/cryptodev.c linux-2.6.36/crypto/ocf/cryptodev.c ---- linux-2.6.36.orig/crypto/ocf/cryptodev.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/cryptodev.c 2010-11-09 20:29:09.284996310 +0100 -@@ -0,0 +1,1060 @@ -+/* $OpenBSD: cryptodev.c,v 1.52 2002/06/19 07:22:46 deraadt Exp $ */ -+ -+/*- -+ * Linux port done by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * The license and original author are listed below. -+ * -+ * Copyright (c) 2001 Theo de Raadt -+ * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored in part by the Defense Advanced Research Projects -+ * Agency (DARPA) and Air Force Research Laboratory, Air Force -+ * Materiel Command, USAF, under agreement number F30602-01-2-0537. -+ * -+__FBSDID("$FreeBSD: src/sys/opencrypto/cryptodev.c,v 1.34 2007/05/09 19:37:02 gnn Exp $"); -+ */ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+extern asmlinkage long sys_dup(unsigned int fildes); -+ -+#define debug cryptodev_debug -+int cryptodev_debug = 0; -+module_param(cryptodev_debug, int, 0644); -+MODULE_PARM_DESC(cryptodev_debug, "Enable cryptodev debug"); -+ -+struct csession_info { -+ u_int16_t blocksize; -+ u_int16_t minkey, maxkey; -+ -+ u_int16_t keysize; -+ /* u_int16_t hashsize; */ -+ u_int16_t authsize; -+ u_int16_t authkey; -+ /* u_int16_t ctxsize; */ -+}; -+ -+struct csession { -+ struct list_head list; -+ u_int64_t sid; -+ u_int32_t ses; -+ -+ wait_queue_head_t waitq; -+ -+ u_int32_t cipher; -+ -+ u_int32_t mac; -+ -+ caddr_t key; -+ int keylen; -+ u_char tmp_iv[EALG_MAX_BLOCK_LEN]; -+ -+ caddr_t mackey; -+ int mackeylen; -+ -+ struct csession_info info; -+ -+ struct iovec iovec; -+ struct uio uio; -+ int error; -+}; -+ -+struct fcrypt { -+ struct list_head csessions; -+ int sesn; -+}; -+ -+static struct csession *csefind(struct fcrypt *, u_int); -+static int csedelete(struct fcrypt *, struct csession *); -+static struct csession *cseadd(struct fcrypt *, struct csession *); -+static struct csession *csecreate(struct fcrypt *, u_int64_t, -+ struct cryptoini *crie, struct cryptoini *cria, struct csession_info *); -+static int csefree(struct csession *); -+ -+static int cryptodev_op(struct csession *, struct crypt_op *); -+static int cryptodev_key(struct crypt_kop *); -+static int cryptodev_find(struct crypt_find_op *); -+ -+static int cryptodev_cb(void *); -+static int cryptodev_open(struct inode *inode, struct file *filp); -+ -+/* -+ * Check a crypto identifier to see if it requested -+ * a valid crid and it's capabilities match. -+ */ -+static int -+checkcrid(int crid) -+{ -+ int hid = crid & ~(CRYPTOCAP_F_SOFTWARE | CRYPTOCAP_F_HARDWARE); -+ int typ = crid & (CRYPTOCAP_F_SOFTWARE | CRYPTOCAP_F_HARDWARE); -+ int caps = 0; -+ -+ /* if the user hasn't selected a driver, then just call newsession */ -+ if (hid == 0 && typ != 0) -+ return 0; -+ -+ caps = crypto_getcaps(hid); -+ -+ /* didn't find anything with capabilities */ -+ if (caps == 0) { -+ dprintk("%s: hid=%x typ=%x not matched\n", __FUNCTION__, hid, typ); -+ return EINVAL; -+ } -+ -+ /* the user didn't specify SW or HW, so the driver is ok */ -+ if (typ == 0) -+ return 0; -+ -+ /* if the type specified didn't match */ -+ if (typ != (caps & (CRYPTOCAP_F_SOFTWARE | CRYPTOCAP_F_HARDWARE))) { -+ dprintk("%s: hid=%x typ=%x caps=%x not matched\n", __FUNCTION__, -+ hid, typ, caps); -+ return EINVAL; -+ } -+ -+ return 0; -+} -+ -+static int -+cryptodev_op(struct csession *cse, struct crypt_op *cop) -+{ -+ struct cryptop *crp = NULL; -+ struct cryptodesc *crde = NULL, *crda = NULL; -+ int error = 0; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (cop->len > CRYPTO_MAX_DATA_LEN) { -+ dprintk("%s: %d > %d\n", __FUNCTION__, cop->len, CRYPTO_MAX_DATA_LEN); -+ return (E2BIG); -+ } -+ -+ if (cse->info.blocksize && (cop->len % cse->info.blocksize) != 0) { -+ dprintk("%s: blocksize=%d len=%d\n", __FUNCTION__, cse->info.blocksize, -+ cop->len); -+ return (EINVAL); -+ } -+ -+ cse->uio.uio_iov = &cse->iovec; -+ cse->uio.uio_iovcnt = 1; -+ cse->uio.uio_offset = 0; -+#if 0 -+ cse->uio.uio_resid = cop->len; -+ cse->uio.uio_segflg = UIO_SYSSPACE; -+ cse->uio.uio_rw = UIO_WRITE; -+ cse->uio.uio_td = td; -+#endif -+ cse->uio.uio_iov[0].iov_len = cop->len; -+ if (cse->info.authsize) -+ cse->uio.uio_iov[0].iov_len += cse->info.authsize; -+ cse->uio.uio_iov[0].iov_base = kmalloc(cse->uio.uio_iov[0].iov_len, -+ GFP_KERNEL); -+ -+ if (cse->uio.uio_iov[0].iov_base == NULL) { -+ dprintk("%s: iov_base kmalloc(%d) failed\n", __FUNCTION__, -+ (int)cse->uio.uio_iov[0].iov_len); -+ return (ENOMEM); -+ } -+ -+ crp = crypto_getreq((cse->info.blocksize != 0) + (cse->info.authsize != 0)); -+ if (crp == NULL) { -+ dprintk("%s: ENOMEM\n", __FUNCTION__); -+ error = ENOMEM; -+ goto bail; -+ } -+ -+ if (cse->info.authsize && cse->info.blocksize) { -+ if (cop->op == COP_ENCRYPT) { -+ crde = crp->crp_desc; -+ crda = crde->crd_next; -+ } else { -+ crda = crp->crp_desc; -+ crde = crda->crd_next; -+ } -+ } else if (cse->info.authsize) { -+ crda = crp->crp_desc; -+ } else if (cse->info.blocksize) { -+ crde = crp->crp_desc; -+ } else { -+ dprintk("%s: bad request\n", __FUNCTION__); -+ error = EINVAL; -+ goto bail; -+ } -+ -+ if ((error = copy_from_user(cse->uio.uio_iov[0].iov_base, cop->src, -+ cop->len))) { -+ dprintk("%s: bad copy\n", __FUNCTION__); -+ goto bail; -+ } -+ -+ if (crda) { -+ crda->crd_skip = 0; -+ crda->crd_len = cop->len; -+ crda->crd_inject = cop->len; -+ -+ crda->crd_alg = cse->mac; -+ crda->crd_key = cse->mackey; -+ crda->crd_klen = cse->mackeylen * 8; -+ } -+ -+ if (crde) { -+ if (cop->op == COP_ENCRYPT) -+ crde->crd_flags |= CRD_F_ENCRYPT; -+ else -+ crde->crd_flags &= ~CRD_F_ENCRYPT; -+ crde->crd_len = cop->len; -+ crde->crd_inject = 0; -+ -+ crde->crd_alg = cse->cipher; -+ crde->crd_key = cse->key; -+ crde->crd_klen = cse->keylen * 8; -+ } -+ -+ crp->crp_ilen = cse->uio.uio_iov[0].iov_len; -+ crp->crp_flags = CRYPTO_F_IOV | CRYPTO_F_CBIMM -+ | (cop->flags & COP_F_BATCH); -+ crp->crp_buf = (caddr_t)&cse->uio; -+ crp->crp_callback = (int (*) (struct cryptop *)) cryptodev_cb; -+ crp->crp_sid = cse->sid; -+ crp->crp_opaque = (void *)cse; -+ -+ if (cop->iv) { -+ if (crde == NULL) { -+ error = EINVAL; -+ dprintk("%s no crde\n", __FUNCTION__); -+ goto bail; -+ } -+ if (cse->cipher == CRYPTO_ARC4) { /* XXX use flag? */ -+ error = EINVAL; -+ dprintk("%s arc4 with IV\n", __FUNCTION__); -+ goto bail; -+ } -+ if ((error = copy_from_user(cse->tmp_iv, cop->iv, -+ cse->info.blocksize))) { -+ dprintk("%s bad iv copy\n", __FUNCTION__); -+ goto bail; -+ } -+ memcpy(crde->crd_iv, cse->tmp_iv, cse->info.blocksize); -+ crde->crd_flags |= CRD_F_IV_EXPLICIT | CRD_F_IV_PRESENT; -+ crde->crd_skip = 0; -+ } else if (cse->cipher == CRYPTO_ARC4) { /* XXX use flag? */ -+ crde->crd_skip = 0; -+ } else if (crde) { -+ crde->crd_flags |= CRD_F_IV_PRESENT; -+ crde->crd_skip = cse->info.blocksize; -+ crde->crd_len -= cse->info.blocksize; -+ } -+ -+ if (cop->mac && crda == NULL) { -+ error = EINVAL; -+ dprintk("%s no crda\n", __FUNCTION__); -+ goto bail; -+ } -+ -+ /* -+ * Let the dispatch run unlocked, then, interlock against the -+ * callback before checking if the operation completed and going -+ * to sleep. This insures drivers don't inherit our lock which -+ * results in a lock order reversal between crypto_dispatch forced -+ * entry and the crypto_done callback into us. -+ */ -+ error = crypto_dispatch(crp); -+ if (error) { -+ dprintk("%s error in crypto_dispatch\n", __FUNCTION__); -+ goto bail; -+ } -+ -+ dprintk("%s about to WAIT\n", __FUNCTION__); -+ /* -+ * we really need to wait for driver to complete to maintain -+ * state, luckily interrupts will be remembered -+ */ -+ do { -+ error = wait_event_interruptible(crp->crp_waitq, -+ ((crp->crp_flags & CRYPTO_F_DONE) != 0)); -+ /* -+ * we can't break out of this loop or we will leave behind -+ * a huge mess, however, staying here means if your driver -+ * is broken user applications can hang and not be killed. -+ * The solution, fix your driver :-) -+ */ -+ if (error) { -+ schedule(); -+ error = 0; -+ } -+ } while ((crp->crp_flags & CRYPTO_F_DONE) == 0); -+ dprintk("%s finished WAITING error=%d\n", __FUNCTION__, error); -+ -+ if (crp->crp_etype != 0) { -+ error = crp->crp_etype; -+ dprintk("%s error in crp processing\n", __FUNCTION__); -+ goto bail; -+ } -+ -+ if (cse->error) { -+ error = cse->error; -+ dprintk("%s error in cse processing\n", __FUNCTION__); -+ goto bail; -+ } -+ -+ if (cop->dst && (error = copy_to_user(cop->dst, -+ cse->uio.uio_iov[0].iov_base, cop->len))) { -+ dprintk("%s bad dst copy\n", __FUNCTION__); -+ goto bail; -+ } -+ -+ if (cop->mac && -+ (error=copy_to_user(cop->mac, -+ (caddr_t)cse->uio.uio_iov[0].iov_base + cop->len, -+ cse->info.authsize))) { -+ dprintk("%s bad mac copy\n", __FUNCTION__); -+ goto bail; -+ } -+ -+bail: -+ if (crp) -+ crypto_freereq(crp); -+ if (cse->uio.uio_iov[0].iov_base) -+ kfree(cse->uio.uio_iov[0].iov_base); -+ -+ return (error); -+} -+ -+static int -+cryptodev_cb(void *op) -+{ -+ struct cryptop *crp = (struct cryptop *) op; -+ struct csession *cse = (struct csession *)crp->crp_opaque; -+ int error; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ error = crp->crp_etype; -+ if (error == EAGAIN) { -+ crp->crp_flags &= ~CRYPTO_F_DONE; -+#ifdef NOTYET -+ /* -+ * DAVIDM I am fairly sure that we should turn this into a batch -+ * request to stop bad karma/lockup, revisit -+ */ -+ crp->crp_flags |= CRYPTO_F_BATCH; -+#endif -+ return crypto_dispatch(crp); -+ } -+ if (error != 0 || (crp->crp_flags & CRYPTO_F_DONE)) { -+ cse->error = error; -+ wake_up_interruptible(&crp->crp_waitq); -+ } -+ return (0); -+} -+ -+static int -+cryptodevkey_cb(void *op) -+{ -+ struct cryptkop *krp = (struct cryptkop *) op; -+ dprintk("%s()\n", __FUNCTION__); -+ wake_up_interruptible(&krp->krp_waitq); -+ return (0); -+} -+ -+static int -+cryptodev_key(struct crypt_kop *kop) -+{ -+ struct cryptkop *krp = NULL; -+ int error = EINVAL; -+ int in, out, size, i; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (kop->crk_iparams + kop->crk_oparams > CRK_MAXPARAM) { -+ dprintk("%s params too big\n", __FUNCTION__); -+ return (EFBIG); -+ } -+ -+ in = kop->crk_iparams; -+ out = kop->crk_oparams; -+ switch (kop->crk_op) { -+ case CRK_MOD_EXP: -+ if (in == 3 && out == 1) -+ break; -+ return (EINVAL); -+ case CRK_MOD_EXP_CRT: -+ if (in == 6 && out == 1) -+ break; -+ return (EINVAL); -+ case CRK_DSA_SIGN: -+ if (in == 5 && out == 2) -+ break; -+ return (EINVAL); -+ case CRK_DSA_VERIFY: -+ if (in == 7 && out == 0) -+ break; -+ return (EINVAL); -+ case CRK_DH_COMPUTE_KEY: -+ if (in == 3 && out == 1) -+ break; -+ return (EINVAL); -+ default: -+ return (EINVAL); -+ } -+ -+ krp = (struct cryptkop *)kmalloc(sizeof *krp, GFP_KERNEL); -+ if (!krp) -+ return (ENOMEM); -+ bzero(krp, sizeof *krp); -+ krp->krp_op = kop->crk_op; -+ krp->krp_status = kop->crk_status; -+ krp->krp_iparams = kop->crk_iparams; -+ krp->krp_oparams = kop->crk_oparams; -+ krp->krp_crid = kop->crk_crid; -+ krp->krp_status = 0; -+ krp->krp_flags = CRYPTO_KF_CBIMM; -+ krp->krp_callback = (int (*) (struct cryptkop *)) cryptodevkey_cb; -+ init_waitqueue_head(&krp->krp_waitq); -+ -+ for (i = 0; i < CRK_MAXPARAM; i++) -+ krp->krp_param[i].crp_nbits = kop->crk_param[i].crp_nbits; -+ for (i = 0; i < krp->krp_iparams + krp->krp_oparams; i++) { -+ size = (krp->krp_param[i].crp_nbits + 7) / 8; -+ if (size == 0) -+ continue; -+ krp->krp_param[i].crp_p = (caddr_t) kmalloc(size, GFP_KERNEL); -+ if (i >= krp->krp_iparams) -+ continue; -+ error = copy_from_user(krp->krp_param[i].crp_p, -+ kop->crk_param[i].crp_p, size); -+ if (error) -+ goto fail; -+ } -+ -+ error = crypto_kdispatch(krp); -+ if (error) -+ goto fail; -+ -+ do { -+ error = wait_event_interruptible(krp->krp_waitq, -+ ((krp->krp_flags & CRYPTO_KF_DONE) != 0)); -+ /* -+ * we can't break out of this loop or we will leave behind -+ * a huge mess, however, staying here means if your driver -+ * is broken user applications can hang and not be killed. -+ * The solution, fix your driver :-) -+ */ -+ if (error) { -+ schedule(); -+ error = 0; -+ } -+ } while ((krp->krp_flags & CRYPTO_KF_DONE) == 0); -+ -+ dprintk("%s finished WAITING error=%d\n", __FUNCTION__, error); -+ -+ kop->crk_crid = krp->krp_crid; /* device that did the work */ -+ if (krp->krp_status != 0) { -+ error = krp->krp_status; -+ goto fail; -+ } -+ -+ for (i = krp->krp_iparams; i < krp->krp_iparams + krp->krp_oparams; i++) { -+ size = (krp->krp_param[i].crp_nbits + 7) / 8; -+ if (size == 0) -+ continue; -+ error = copy_to_user(kop->crk_param[i].crp_p, krp->krp_param[i].crp_p, -+ size); -+ if (error) -+ goto fail; -+ } -+ -+fail: -+ if (krp) { -+ kop->crk_status = krp->krp_status; -+ for (i = 0; i < CRK_MAXPARAM; i++) { -+ if (krp->krp_param[i].crp_p) -+ kfree(krp->krp_param[i].crp_p); -+ } -+ kfree(krp); -+ } -+ return (error); -+} -+ -+static int -+cryptodev_find(struct crypt_find_op *find) -+{ -+ device_t dev; -+ -+ if (find->crid != -1) { -+ dev = crypto_find_device_byhid(find->crid); -+ if (dev == NULL) -+ return (ENOENT); -+ strlcpy(find->name, device_get_nameunit(dev), -+ sizeof(find->name)); -+ } else { -+ find->crid = crypto_find_driver(find->name); -+ if (find->crid == -1) -+ return (ENOENT); -+ } -+ return (0); -+} -+ -+static struct csession * -+csefind(struct fcrypt *fcr, u_int ses) -+{ -+ struct csession *cse; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ list_for_each_entry(cse, &fcr->csessions, list) -+ if (cse->ses == ses) -+ return (cse); -+ return (NULL); -+} -+ -+static int -+csedelete(struct fcrypt *fcr, struct csession *cse_del) -+{ -+ struct csession *cse; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ list_for_each_entry(cse, &fcr->csessions, list) { -+ if (cse == cse_del) { -+ list_del(&cse->list); -+ return (1); -+ } -+ } -+ return (0); -+} -+ -+static struct csession * -+cseadd(struct fcrypt *fcr, struct csession *cse) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ list_add_tail(&cse->list, &fcr->csessions); -+ cse->ses = fcr->sesn++; -+ return (cse); -+} -+ -+static struct csession * -+csecreate(struct fcrypt *fcr, u_int64_t sid, struct cryptoini *crie, -+ struct cryptoini *cria, struct csession_info *info) -+{ -+ struct csession *cse; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ cse = (struct csession *) kmalloc(sizeof(struct csession), GFP_KERNEL); -+ if (cse == NULL) -+ return NULL; -+ memset(cse, 0, sizeof(struct csession)); -+ -+ INIT_LIST_HEAD(&cse->list); -+ init_waitqueue_head(&cse->waitq); -+ -+ cse->key = crie->cri_key; -+ cse->keylen = crie->cri_klen/8; -+ cse->mackey = cria->cri_key; -+ cse->mackeylen = cria->cri_klen/8; -+ cse->sid = sid; -+ cse->cipher = crie->cri_alg; -+ cse->mac = cria->cri_alg; -+ cse->info = *info; -+ cseadd(fcr, cse); -+ return (cse); -+} -+ -+static int -+csefree(struct csession *cse) -+{ -+ int error; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ error = crypto_freesession(cse->sid); -+ if (cse->key) -+ kfree(cse->key); -+ if (cse->mackey) -+ kfree(cse->mackey); -+ kfree(cse); -+ return(error); -+} -+ -+static int -+cryptodev_ioctl( -+ struct inode *inode, -+ struct file *filp, -+ unsigned int cmd, -+ unsigned long arg) -+{ -+ struct cryptoini cria, crie; -+ struct fcrypt *fcr = filp->private_data; -+ struct csession *cse; -+ struct csession_info info; -+ struct session2_op sop; -+ struct crypt_op cop; -+ struct crypt_kop kop; -+ struct crypt_find_op fop; -+ u_int64_t sid; -+ u_int32_t ses = 0; -+ int feat, fd, error = 0, crid; -+ mm_segment_t fs; -+ -+ dprintk("%s(cmd=%x arg=%lx)\n", __FUNCTION__, cmd, arg); -+ -+ switch (cmd) { -+ -+ case CRIOGET: { -+ dprintk("%s(CRIOGET)\n", __FUNCTION__); -+ fs = get_fs(); -+ set_fs(get_ds()); -+ for (fd = 0; fd < files_fdtable(current->files)->max_fds; fd++) -+ if (files_fdtable(current->files)->fd[fd] == filp) -+ break; -+ fd = sys_dup(fd); -+ set_fs(fs); -+ put_user(fd, (int *) arg); -+ return IS_ERR_VALUE(fd) ? fd : 0; -+ } -+ -+#define CIOCGSESSSTR (cmd == CIOCGSESSION ? "CIOCGSESSION" : "CIOCGSESSION2") -+ case CIOCGSESSION: -+ case CIOCGSESSION2: -+ dprintk("%s(%s)\n", __FUNCTION__, CIOCGSESSSTR); -+ memset(&crie, 0, sizeof(crie)); -+ memset(&cria, 0, sizeof(cria)); -+ memset(&info, 0, sizeof(info)); -+ memset(&sop, 0, sizeof(sop)); -+ -+ if (copy_from_user(&sop, (void*)arg, (cmd == CIOCGSESSION) ? -+ sizeof(struct session_op) : sizeof(sop))) { -+ dprintk("%s(%s) - bad copy\n", __FUNCTION__, CIOCGSESSSTR); -+ error = EFAULT; -+ goto bail; -+ } -+ -+ switch (sop.cipher) { -+ case 0: -+ dprintk("%s(%s) - no cipher\n", __FUNCTION__, CIOCGSESSSTR); -+ break; -+ case CRYPTO_NULL_CBC: -+ info.blocksize = NULL_BLOCK_LEN; -+ info.minkey = NULL_MIN_KEY_LEN; -+ info.maxkey = NULL_MAX_KEY_LEN; -+ break; -+ case CRYPTO_DES_CBC: -+ info.blocksize = DES_BLOCK_LEN; -+ info.minkey = DES_MIN_KEY_LEN; -+ info.maxkey = DES_MAX_KEY_LEN; -+ break; -+ case CRYPTO_3DES_CBC: -+ info.blocksize = DES3_BLOCK_LEN; -+ info.minkey = DES3_MIN_KEY_LEN; -+ info.maxkey = DES3_MAX_KEY_LEN; -+ break; -+ case CRYPTO_BLF_CBC: -+ info.blocksize = BLOWFISH_BLOCK_LEN; -+ info.minkey = BLOWFISH_MIN_KEY_LEN; -+ info.maxkey = BLOWFISH_MAX_KEY_LEN; -+ break; -+ case CRYPTO_CAST_CBC: -+ info.blocksize = CAST128_BLOCK_LEN; -+ info.minkey = CAST128_MIN_KEY_LEN; -+ info.maxkey = CAST128_MAX_KEY_LEN; -+ break; -+ case CRYPTO_SKIPJACK_CBC: -+ info.blocksize = SKIPJACK_BLOCK_LEN; -+ info.minkey = SKIPJACK_MIN_KEY_LEN; -+ info.maxkey = SKIPJACK_MAX_KEY_LEN; -+ break; -+ case CRYPTO_AES_CBC: -+ info.blocksize = AES_BLOCK_LEN; -+ info.minkey = AES_MIN_KEY_LEN; -+ info.maxkey = AES_MAX_KEY_LEN; -+ break; -+ case CRYPTO_ARC4: -+ info.blocksize = ARC4_BLOCK_LEN; -+ info.minkey = ARC4_MIN_KEY_LEN; -+ info.maxkey = ARC4_MAX_KEY_LEN; -+ break; -+ case CRYPTO_CAMELLIA_CBC: -+ info.blocksize = CAMELLIA_BLOCK_LEN; -+ info.minkey = CAMELLIA_MIN_KEY_LEN; -+ info.maxkey = CAMELLIA_MAX_KEY_LEN; -+ break; -+ default: -+ dprintk("%s(%s) - bad cipher\n", __FUNCTION__, CIOCGSESSSTR); -+ error = EINVAL; -+ goto bail; -+ } -+ -+ switch (sop.mac) { -+ case 0: -+ dprintk("%s(%s) - no mac\n", __FUNCTION__, CIOCGSESSSTR); -+ break; -+ case CRYPTO_NULL_HMAC: -+ info.authsize = NULL_HASH_LEN; -+ break; -+ case CRYPTO_MD5: -+ info.authsize = MD5_HASH_LEN; -+ break; -+ case CRYPTO_SHA1: -+ info.authsize = SHA1_HASH_LEN; -+ break; -+ case CRYPTO_SHA2_256: -+ info.authsize = SHA2_256_HASH_LEN; -+ break; -+ case CRYPTO_SHA2_384: -+ info.authsize = SHA2_384_HASH_LEN; -+ break; -+ case CRYPTO_SHA2_512: -+ info.authsize = SHA2_512_HASH_LEN; -+ break; -+ case CRYPTO_RIPEMD160: -+ info.authsize = RIPEMD160_HASH_LEN; -+ break; -+ case CRYPTO_MD5_HMAC: -+ info.authsize = MD5_HASH_LEN; -+ info.authkey = 16; -+ break; -+ case CRYPTO_SHA1_HMAC: -+ info.authsize = SHA1_HASH_LEN; -+ info.authkey = 20; -+ break; -+ case CRYPTO_SHA2_256_HMAC: -+ info.authsize = SHA2_256_HASH_LEN; -+ info.authkey = 32; -+ break; -+ case CRYPTO_SHA2_384_HMAC: -+ info.authsize = SHA2_384_HASH_LEN; -+ info.authkey = 48; -+ break; -+ case CRYPTO_SHA2_512_HMAC: -+ info.authsize = SHA2_512_HASH_LEN; -+ info.authkey = 64; -+ break; -+ case CRYPTO_RIPEMD160_HMAC: -+ info.authsize = RIPEMD160_HASH_LEN; -+ info.authkey = 20; -+ break; -+ default: -+ dprintk("%s(%s) - bad mac\n", __FUNCTION__, CIOCGSESSSTR); -+ error = EINVAL; -+ goto bail; -+ } -+ -+ if (info.blocksize) { -+ crie.cri_alg = sop.cipher; -+ crie.cri_klen = sop.keylen * 8; -+ if ((info.maxkey && sop.keylen > info.maxkey) || -+ sop.keylen < info.minkey) { -+ dprintk("%s(%s) - bad key\n", __FUNCTION__, CIOCGSESSSTR); -+ error = EINVAL; -+ goto bail; -+ } -+ -+ crie.cri_key = (u_int8_t *) kmalloc(crie.cri_klen/8+1, GFP_KERNEL); -+ if (copy_from_user(crie.cri_key, sop.key, -+ crie.cri_klen/8)) { -+ dprintk("%s(%s) - bad copy\n", __FUNCTION__, CIOCGSESSSTR); -+ error = EFAULT; -+ goto bail; -+ } -+ if (info.authsize) -+ crie.cri_next = &cria; -+ } -+ -+ if (info.authsize) { -+ cria.cri_alg = sop.mac; -+ cria.cri_klen = sop.mackeylen * 8; -+ if (info.authkey && sop.mackeylen != info.authkey) { -+ dprintk("%s(%s) - mackeylen %d != %d\n", __FUNCTION__, -+ CIOCGSESSSTR, sop.mackeylen, info.authkey); -+ error = EINVAL; -+ goto bail; -+ } -+ -+ if (cria.cri_klen) { -+ cria.cri_key = (u_int8_t *) kmalloc(cria.cri_klen/8,GFP_KERNEL); -+ if (copy_from_user(cria.cri_key, sop.mackey, -+ cria.cri_klen / 8)) { -+ dprintk("%s(%s) - bad copy\n", __FUNCTION__, CIOCGSESSSTR); -+ error = EFAULT; -+ goto bail; -+ } -+ } -+ } -+ -+ /* NB: CIOGSESSION2 has the crid */ -+ if (cmd == CIOCGSESSION2) { -+ crid = sop.crid; -+ error = checkcrid(crid); -+ if (error) { -+ dprintk("%s(%s) - checkcrid %x\n", __FUNCTION__, -+ CIOCGSESSSTR, error); -+ goto bail; -+ } -+ } else { -+ /* allow either HW or SW to be used */ -+ crid = CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE; -+ } -+ error = crypto_newsession(&sid, (info.blocksize ? &crie : &cria), crid); -+ if (error) { -+ dprintk("%s(%s) - newsession %d\n",__FUNCTION__,CIOCGSESSSTR,error); -+ goto bail; -+ } -+ -+ cse = csecreate(fcr, sid, &crie, &cria, &info); -+ if (cse == NULL) { -+ crypto_freesession(sid); -+ error = EINVAL; -+ dprintk("%s(%s) - csecreate failed\n", __FUNCTION__, CIOCGSESSSTR); -+ goto bail; -+ } -+ sop.ses = cse->ses; -+ -+ if (cmd == CIOCGSESSION2) { -+ /* return hardware/driver id */ -+ sop.crid = CRYPTO_SESID2HID(cse->sid); -+ } -+ -+ if (copy_to_user((void*)arg, &sop, (cmd == CIOCGSESSION) ? -+ sizeof(struct session_op) : sizeof(sop))) { -+ dprintk("%s(%s) - bad copy\n", __FUNCTION__, CIOCGSESSSTR); -+ error = EFAULT; -+ } -+bail: -+ if (error) { -+ dprintk("%s(%s) - bail %d\n", __FUNCTION__, CIOCGSESSSTR, error); -+ if (crie.cri_key) -+ kfree(crie.cri_key); -+ if (cria.cri_key) -+ kfree(cria.cri_key); -+ } -+ break; -+ case CIOCFSESSION: -+ dprintk("%s(CIOCFSESSION)\n", __FUNCTION__); -+ get_user(ses, (uint32_t*)arg); -+ cse = csefind(fcr, ses); -+ if (cse == NULL) { -+ error = EINVAL; -+ dprintk("%s(CIOCFSESSION) - Fail %d\n", __FUNCTION__, error); -+ break; -+ } -+ csedelete(fcr, cse); -+ error = csefree(cse); -+ break; -+ case CIOCCRYPT: -+ dprintk("%s(CIOCCRYPT)\n", __FUNCTION__); -+ if(copy_from_user(&cop, (void*)arg, sizeof(cop))) { -+ dprintk("%s(CIOCCRYPT) - bad copy\n", __FUNCTION__); -+ error = EFAULT; -+ goto bail; -+ } -+ cse = csefind(fcr, cop.ses); -+ if (cse == NULL) { -+ error = EINVAL; -+ dprintk("%s(CIOCCRYPT) - Fail %d\n", __FUNCTION__, error); -+ break; -+ } -+ error = cryptodev_op(cse, &cop); -+ if(copy_to_user((void*)arg, &cop, sizeof(cop))) { -+ dprintk("%s(CIOCCRYPT) - bad return copy\n", __FUNCTION__); -+ error = EFAULT; -+ goto bail; -+ } -+ break; -+ case CIOCKEY: -+ case CIOCKEY2: -+ dprintk("%s(CIOCKEY)\n", __FUNCTION__); -+ if (!crypto_userasymcrypto) -+ return (EPERM); /* XXX compat? */ -+ if(copy_from_user(&kop, (void*)arg, sizeof(kop))) { -+ dprintk("%s(CIOCKEY) - bad copy\n", __FUNCTION__); -+ error = EFAULT; -+ goto bail; -+ } -+ if (cmd == CIOCKEY) { -+ /* NB: crypto core enforces s/w driver use */ -+ kop.crk_crid = -+ CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE; -+ } -+ error = cryptodev_key(&kop); -+ if(copy_to_user((void*)arg, &kop, sizeof(kop))) { -+ dprintk("%s(CIOCGKEY) - bad return copy\n", __FUNCTION__); -+ error = EFAULT; -+ goto bail; -+ } -+ break; -+ case CIOCASYMFEAT: -+ dprintk("%s(CIOCASYMFEAT)\n", __FUNCTION__); -+ if (!crypto_userasymcrypto) { -+ /* -+ * NB: if user asym crypto operations are -+ * not permitted return "no algorithms" -+ * so well-behaved applications will just -+ * fallback to doing them in software. -+ */ -+ feat = 0; -+ } else -+ error = crypto_getfeat(&feat); -+ if (!error) { -+ error = copy_to_user((void*)arg, &feat, sizeof(feat)); -+ } -+ break; -+ case CIOCFINDDEV: -+ if (copy_from_user(&fop, (void*)arg, sizeof(fop))) { -+ dprintk("%s(CIOCFINDDEV) - bad copy\n", __FUNCTION__); -+ error = EFAULT; -+ goto bail; -+ } -+ error = cryptodev_find(&fop); -+ if (copy_to_user((void*)arg, &fop, sizeof(fop))) { -+ dprintk("%s(CIOCFINDDEV) - bad return copy\n", __FUNCTION__); -+ error = EFAULT; -+ goto bail; -+ } -+ break; -+ default: -+ dprintk("%s(unknown ioctl 0x%x)\n", __FUNCTION__, cmd); -+ error = EINVAL; -+ break; -+ } -+ return(-error); -+} -+ -+#ifdef HAVE_UNLOCKED_IOCTL -+static long -+cryptodev_unlocked_ioctl( -+ struct file *filp, -+ unsigned int cmd, -+ unsigned long arg) -+{ -+ return cryptodev_ioctl(NULL, filp, cmd, arg); -+} -+#endif -+ -+static int -+cryptodev_open(struct inode *inode, struct file *filp) -+{ -+ struct fcrypt *fcr; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (filp->private_data) { -+ printk("cryptodev: Private data already exists !\n"); -+ return(0); -+ } -+ -+ fcr = kmalloc(sizeof(*fcr), GFP_KERNEL); -+ if (!fcr) { -+ dprintk("%s() - malloc failed\n", __FUNCTION__); -+ return(-ENOMEM); -+ } -+ memset(fcr, 0, sizeof(*fcr)); -+ -+ INIT_LIST_HEAD(&fcr->csessions); -+ filp->private_data = fcr; -+ return(0); -+} -+ -+static int -+cryptodev_release(struct inode *inode, struct file *filp) -+{ -+ struct fcrypt *fcr = filp->private_data; -+ struct csession *cse, *tmp; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (!filp) { -+ printk("cryptodev: No private data on release\n"); -+ return(0); -+ } -+ -+ list_for_each_entry_safe(cse, tmp, &fcr->csessions, list) { -+ list_del(&cse->list); -+ (void)csefree(cse); -+ } -+ filp->private_data = NULL; -+ kfree(fcr); -+ return(0); -+} -+ -+static struct file_operations cryptodev_fops = { -+ .owner = THIS_MODULE, -+ .open = cryptodev_open, -+ .release = cryptodev_release, -+#ifdef HAVE_UNLOCKED_IOCTL -+ .unlocked_ioctl = cryptodev_unlocked_ioctl, -+#endif -+}; -+ -+static struct miscdevice cryptodev = { -+ .minor = CRYPTODEV_MINOR, -+ .name = "crypto", -+ .fops = &cryptodev_fops, -+}; -+ -+static int __init -+cryptodev_init(void) -+{ -+ int rc; -+ -+ dprintk("%s(%p)\n", __FUNCTION__, cryptodev_init); -+ rc = misc_register(&cryptodev); -+ if (rc) { -+ printk(KERN_ERR "cryptodev: registration of /dev/crypto failed\n"); -+ return(rc); -+ } -+ -+ return(0); -+} -+ -+static void __exit -+cryptodev_exit(void) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ misc_deregister(&cryptodev); -+} -+ -+module_init(cryptodev_init); -+module_exit(cryptodev_exit); -+ -+MODULE_LICENSE("BSD"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("Cryptodev (user interface to OCF)"); -diff -Nur linux-2.6.36.orig/crypto/ocf/cryptodev.h linux-2.6.36/crypto/ocf/cryptodev.h ---- linux-2.6.36.orig/crypto/ocf/cryptodev.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/cryptodev.h 2010-11-09 20:28:04.492495480 +0100 -@@ -0,0 +1,479 @@ -+/* $FreeBSD: src/sys/opencrypto/cryptodev.h,v 1.25 2007/05/09 19:37:02 gnn Exp $ */ -+/* $OpenBSD: cryptodev.h,v 1.31 2002/06/11 11:14:29 beck Exp $ */ -+ -+/*- -+ * Linux port done by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * The license and original author are listed below. -+ * -+ * The author of this code is Angelos D. Keromytis (angelos@cis.upenn.edu) -+ * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting -+ * -+ * This code was written by Angelos D. Keromytis in Athens, Greece, in -+ * February 2000. Network Security Technologies Inc. (NSTI) kindly -+ * supported the development of this code. -+ * -+ * Copyright (c) 2000 Angelos D. Keromytis -+ * -+ * Permission to use, copy, and modify this software with or without fee -+ * is hereby granted, provided that this entire notice is included in -+ * all source code copies of any software which is or includes a copy or -+ * modification of this software. -+ * -+ * THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR -+ * IMPLIED WARRANTY. IN PARTICULAR, NONE OF THE AUTHORS MAKES ANY -+ * REPRESENTATION OR WARRANTY OF ANY KIND CONCERNING THE -+ * MERCHANTABILITY OF THIS SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR -+ * PURPOSE. -+ * -+ * Copyright (c) 2001 Theo de Raadt -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored in part by the Defense Advanced Research Projects -+ * Agency (DARPA) and Air Force Research Laboratory, Air Force -+ * Materiel Command, USAF, under agreement number F30602-01-2-0537. -+ * -+ */ -+ -+#ifndef _CRYPTO_CRYPTO_H_ -+#define _CRYPTO_CRYPTO_H_ -+ -+/* Some initial values */ -+#define CRYPTO_DRIVERS_INITIAL 4 -+#define CRYPTO_SW_SESSIONS 32 -+ -+/* Hash values */ -+#define NULL_HASH_LEN 0 -+#define MD5_HASH_LEN 16 -+#define SHA1_HASH_LEN 20 -+#define RIPEMD160_HASH_LEN 20 -+#define SHA2_256_HASH_LEN 32 -+#define SHA2_384_HASH_LEN 48 -+#define SHA2_512_HASH_LEN 64 -+#define MD5_KPDK_HASH_LEN 16 -+#define SHA1_KPDK_HASH_LEN 20 -+/* Maximum hash algorithm result length */ -+#define HASH_MAX_LEN SHA2_512_HASH_LEN /* Keep this updated */ -+ -+/* HMAC values */ -+#define NULL_HMAC_BLOCK_LEN 1 -+#define MD5_HMAC_BLOCK_LEN 64 -+#define SHA1_HMAC_BLOCK_LEN 64 -+#define RIPEMD160_HMAC_BLOCK_LEN 64 -+#define SHA2_256_HMAC_BLOCK_LEN 64 -+#define SHA2_384_HMAC_BLOCK_LEN 128 -+#define SHA2_512_HMAC_BLOCK_LEN 128 -+/* Maximum HMAC block length */ -+#define HMAC_MAX_BLOCK_LEN SHA2_512_HMAC_BLOCK_LEN /* Keep this updated */ -+#define HMAC_IPAD_VAL 0x36 -+#define HMAC_OPAD_VAL 0x5C -+ -+/* Encryption algorithm block sizes */ -+#define NULL_BLOCK_LEN 1 -+#define DES_BLOCK_LEN 8 -+#define DES3_BLOCK_LEN 8 -+#define BLOWFISH_BLOCK_LEN 8 -+#define SKIPJACK_BLOCK_LEN 8 -+#define CAST128_BLOCK_LEN 8 -+#define RIJNDAEL128_BLOCK_LEN 16 -+#define AES_BLOCK_LEN RIJNDAEL128_BLOCK_LEN -+#define CAMELLIA_BLOCK_LEN 16 -+#define ARC4_BLOCK_LEN 1 -+#define EALG_MAX_BLOCK_LEN AES_BLOCK_LEN /* Keep this updated */ -+ -+/* Encryption algorithm min and max key sizes */ -+#define NULL_MIN_KEY_LEN 0 -+#define NULL_MAX_KEY_LEN 0 -+#define DES_MIN_KEY_LEN 8 -+#define DES_MAX_KEY_LEN 8 -+#define DES3_MIN_KEY_LEN 24 -+#define DES3_MAX_KEY_LEN 24 -+#define BLOWFISH_MIN_KEY_LEN 4 -+#define BLOWFISH_MAX_KEY_LEN 56 -+#define SKIPJACK_MIN_KEY_LEN 10 -+#define SKIPJACK_MAX_KEY_LEN 10 -+#define CAST128_MIN_KEY_LEN 5 -+#define CAST128_MAX_KEY_LEN 16 -+#define RIJNDAEL128_MIN_KEY_LEN 16 -+#define RIJNDAEL128_MAX_KEY_LEN 32 -+#define AES_MIN_KEY_LEN RIJNDAEL128_MIN_KEY_LEN -+#define AES_MAX_KEY_LEN RIJNDAEL128_MAX_KEY_LEN -+#define CAMELLIA_MIN_KEY_LEN 16 -+#define CAMELLIA_MAX_KEY_LEN 32 -+#define ARC4_MIN_KEY_LEN 1 -+#define ARC4_MAX_KEY_LEN 256 -+ -+/* Max size of data that can be processed */ -+#define CRYPTO_MAX_DATA_LEN 64*1024 - 1 -+ -+#define CRYPTO_ALGORITHM_MIN 1 -+#define CRYPTO_DES_CBC 1 -+#define CRYPTO_3DES_CBC 2 -+#define CRYPTO_BLF_CBC 3 -+#define CRYPTO_CAST_CBC 4 -+#define CRYPTO_SKIPJACK_CBC 5 -+#define CRYPTO_MD5_HMAC 6 -+#define CRYPTO_SHA1_HMAC 7 -+#define CRYPTO_RIPEMD160_HMAC 8 -+#define CRYPTO_MD5_KPDK 9 -+#define CRYPTO_SHA1_KPDK 10 -+#define CRYPTO_RIJNDAEL128_CBC 11 /* 128 bit blocksize */ -+#define CRYPTO_AES_CBC 11 /* 128 bit blocksize -- the same as above */ -+#define CRYPTO_ARC4 12 -+#define CRYPTO_MD5 13 -+#define CRYPTO_SHA1 14 -+#define CRYPTO_NULL_HMAC 15 -+#define CRYPTO_NULL_CBC 16 -+#define CRYPTO_DEFLATE_COMP 17 /* Deflate compression algorithm */ -+#define CRYPTO_SHA2_256_HMAC 18 -+#define CRYPTO_SHA2_384_HMAC 19 -+#define CRYPTO_SHA2_512_HMAC 20 -+#define CRYPTO_CAMELLIA_CBC 21 -+#define CRYPTO_SHA2_256 22 -+#define CRYPTO_SHA2_384 23 -+#define CRYPTO_SHA2_512 24 -+#define CRYPTO_RIPEMD160 25 -+#define CRYPTO_ALGORITHM_MAX 25 /* Keep updated - see below */ -+ -+/* Algorithm flags */ -+#define CRYPTO_ALG_FLAG_SUPPORTED 0x01 /* Algorithm is supported */ -+#define CRYPTO_ALG_FLAG_RNG_ENABLE 0x02 /* Has HW RNG for DH/DSA */ -+#define CRYPTO_ALG_FLAG_DSA_SHA 0x04 /* Can do SHA on msg */ -+ -+/* -+ * Crypto driver/device flags. They can set in the crid -+ * parameter when creating a session or submitting a key -+ * op to affect the device/driver assigned. If neither -+ * of these are specified then the crid is assumed to hold -+ * the driver id of an existing (and suitable) device that -+ * must be used to satisfy the request. -+ */ -+#define CRYPTO_FLAG_HARDWARE 0x01000000 /* hardware accelerated */ -+#define CRYPTO_FLAG_SOFTWARE 0x02000000 /* software implementation */ -+ -+/* NB: deprecated */ -+struct session_op { -+ u_int32_t cipher; /* ie. CRYPTO_DES_CBC */ -+ u_int32_t mac; /* ie. CRYPTO_MD5_HMAC */ -+ -+ u_int32_t keylen; /* cipher key */ -+ caddr_t key; -+ int mackeylen; /* mac key */ -+ caddr_t mackey; -+ -+ u_int32_t ses; /* returns: session # */ -+}; -+ -+struct session2_op { -+ u_int32_t cipher; /* ie. CRYPTO_DES_CBC */ -+ u_int32_t mac; /* ie. CRYPTO_MD5_HMAC */ -+ -+ u_int32_t keylen; /* cipher key */ -+ caddr_t key; -+ int mackeylen; /* mac key */ -+ caddr_t mackey; -+ -+ u_int32_t ses; /* returns: session # */ -+ int crid; /* driver id + flags (rw) */ -+ int pad[4]; /* for future expansion */ -+}; -+ -+struct crypt_op { -+ u_int32_t ses; -+ u_int16_t op; /* i.e. COP_ENCRYPT */ -+#define COP_NONE 0 -+#define COP_ENCRYPT 1 -+#define COP_DECRYPT 2 -+ u_int16_t flags; -+#define COP_F_BATCH 0x0008 /* Batch op if possible */ -+ u_int len; -+ caddr_t src, dst; /* become iov[] inside kernel */ -+ caddr_t mac; /* must be big enough for chosen MAC */ -+ caddr_t iv; -+}; -+ -+/* -+ * Parameters for looking up a crypto driver/device by -+ * device name or by id. The latter are returned for -+ * created sessions (crid) and completed key operations. -+ */ -+struct crypt_find_op { -+ int crid; /* driver id + flags */ -+ char name[32]; /* device/driver name */ -+}; -+ -+/* bignum parameter, in packed bytes, ... */ -+struct crparam { -+ caddr_t crp_p; -+ u_int crp_nbits; -+}; -+ -+#define CRK_MAXPARAM 8 -+ -+struct crypt_kop { -+ u_int crk_op; /* ie. CRK_MOD_EXP or other */ -+ u_int crk_status; /* return status */ -+ u_short crk_iparams; /* # of input parameters */ -+ u_short crk_oparams; /* # of output parameters */ -+ u_int crk_crid; /* NB: only used by CIOCKEY2 (rw) */ -+ struct crparam crk_param[CRK_MAXPARAM]; -+}; -+#define CRK_ALGORITM_MIN 0 -+#define CRK_MOD_EXP 0 -+#define CRK_MOD_EXP_CRT 1 -+#define CRK_DSA_SIGN 2 -+#define CRK_DSA_VERIFY 3 -+#define CRK_DH_COMPUTE_KEY 4 -+#define CRK_ALGORITHM_MAX 4 /* Keep updated - see below */ -+ -+#define CRF_MOD_EXP (1 << CRK_MOD_EXP) -+#define CRF_MOD_EXP_CRT (1 << CRK_MOD_EXP_CRT) -+#define CRF_DSA_SIGN (1 << CRK_DSA_SIGN) -+#define CRF_DSA_VERIFY (1 << CRK_DSA_VERIFY) -+#define CRF_DH_COMPUTE_KEY (1 << CRK_DH_COMPUTE_KEY) -+ -+/* -+ * done against open of /dev/crypto, to get a cloned descriptor. -+ * Please use F_SETFD against the cloned descriptor. -+ */ -+#define CRIOGET _IOWR('c', 100, u_int32_t) -+#define CRIOASYMFEAT CIOCASYMFEAT -+#define CRIOFINDDEV CIOCFINDDEV -+ -+/* the following are done against the cloned descriptor */ -+#define CIOCGSESSION _IOWR('c', 101, struct session_op) -+#define CIOCFSESSION _IOW('c', 102, u_int32_t) -+#define CIOCCRYPT _IOWR('c', 103, struct crypt_op) -+#define CIOCKEY _IOWR('c', 104, struct crypt_kop) -+#define CIOCASYMFEAT _IOR('c', 105, u_int32_t) -+#define CIOCGSESSION2 _IOWR('c', 106, struct session2_op) -+#define CIOCKEY2 _IOWR('c', 107, struct crypt_kop) -+#define CIOCFINDDEV _IOWR('c', 108, struct crypt_find_op) -+ -+struct cryptotstat { -+ struct timespec acc; /* total accumulated time */ -+ struct timespec min; /* min time */ -+ struct timespec max; /* max time */ -+ u_int32_t count; /* number of observations */ -+}; -+ -+struct cryptostats { -+ u_int32_t cs_ops; /* symmetric crypto ops submitted */ -+ u_int32_t cs_errs; /* symmetric crypto ops that failed */ -+ u_int32_t cs_kops; /* asymetric/key ops submitted */ -+ u_int32_t cs_kerrs; /* asymetric/key ops that failed */ -+ u_int32_t cs_intrs; /* crypto swi thread activations */ -+ u_int32_t cs_rets; /* crypto return thread activations */ -+ u_int32_t cs_blocks; /* symmetric op driver block */ -+ u_int32_t cs_kblocks; /* symmetric op driver block */ -+ /* -+ * When CRYPTO_TIMING is defined at compile time and the -+ * sysctl debug.crypto is set to 1, the crypto system will -+ * accumulate statistics about how long it takes to process -+ * crypto requests at various points during processing. -+ */ -+ struct cryptotstat cs_invoke; /* crypto_dipsatch -> crypto_invoke */ -+ struct cryptotstat cs_done; /* crypto_invoke -> crypto_done */ -+ struct cryptotstat cs_cb; /* crypto_done -> callback */ -+ struct cryptotstat cs_finis; /* callback -> callback return */ -+ -+ u_int32_t cs_drops; /* crypto ops dropped due to congestion */ -+}; -+ -+#ifdef __KERNEL__ -+ -+/* Standard initialization structure beginning */ -+struct cryptoini { -+ int cri_alg; /* Algorithm to use */ -+ int cri_klen; /* Key length, in bits */ -+ int cri_mlen; /* Number of bytes we want from the -+ entire hash. 0 means all. */ -+ caddr_t cri_key; /* key to use */ -+ u_int8_t cri_iv[EALG_MAX_BLOCK_LEN]; /* IV to use */ -+ struct cryptoini *cri_next; -+}; -+ -+/* Describe boundaries of a single crypto operation */ -+struct cryptodesc { -+ int crd_skip; /* How many bytes to ignore from start */ -+ int crd_len; /* How many bytes to process */ -+ int crd_inject; /* Where to inject results, if applicable */ -+ int crd_flags; -+ -+#define CRD_F_ENCRYPT 0x01 /* Set when doing encryption */ -+#define CRD_F_IV_PRESENT 0x02 /* When encrypting, IV is already in -+ place, so don't copy. */ -+#define CRD_F_IV_EXPLICIT 0x04 /* IV explicitly provided */ -+#define CRD_F_DSA_SHA_NEEDED 0x08 /* Compute SHA-1 of buffer for DSA */ -+#define CRD_F_KEY_EXPLICIT 0x10 /* Key explicitly provided */ -+#define CRD_F_COMP 0x0f /* Set when doing compression */ -+ -+ struct cryptoini CRD_INI; /* Initialization/context data */ -+#define crd_iv CRD_INI.cri_iv -+#define crd_key CRD_INI.cri_key -+#define crd_alg CRD_INI.cri_alg -+#define crd_klen CRD_INI.cri_klen -+#define crd_mlen CRD_INI.cri_mlen -+ -+ struct cryptodesc *crd_next; -+}; -+ -+/* Structure describing complete operation */ -+struct cryptop { -+ struct list_head crp_next; -+ wait_queue_head_t crp_waitq; -+ -+ u_int64_t crp_sid; /* Session ID */ -+ int crp_ilen; /* Input data total length */ -+ int crp_olen; /* Result total length */ -+ -+ int crp_etype; /* -+ * Error type (zero means no error). -+ * All error codes except EAGAIN -+ * indicate possible data corruption (as in, -+ * the data have been touched). On all -+ * errors, the crp_sid may have changed -+ * (reset to a new one), so the caller -+ * should always check and use the new -+ * value on future requests. -+ */ -+ int crp_flags; -+ -+#define CRYPTO_F_SKBUF 0x0001 /* Input/output are skbuf chains */ -+#define CRYPTO_F_IOV 0x0002 /* Input/output are uio */ -+#define CRYPTO_F_REL 0x0004 /* Must return data in same place */ -+#define CRYPTO_F_BATCH 0x0008 /* Batch op if possible */ -+#define CRYPTO_F_CBIMM 0x0010 /* Do callback immediately */ -+#define CRYPTO_F_DONE 0x0020 /* Operation completed */ -+#define CRYPTO_F_CBIFSYNC 0x0040 /* Do CBIMM if op is synchronous */ -+ -+ caddr_t crp_buf; /* Data to be processed */ -+ caddr_t crp_opaque; /* Opaque pointer, passed along */ -+ struct cryptodesc *crp_desc; /* Linked list of processing descriptors */ -+ -+ int (*crp_callback)(struct cryptop *); /* Callback function */ -+}; -+ -+#define CRYPTO_BUF_CONTIG 0x0 -+#define CRYPTO_BUF_IOV 0x1 -+#define CRYPTO_BUF_SKBUF 0x2 -+ -+#define CRYPTO_OP_DECRYPT 0x0 -+#define CRYPTO_OP_ENCRYPT 0x1 -+ -+/* -+ * Hints passed to process methods. -+ */ -+#define CRYPTO_HINT_MORE 0x1 /* more ops coming shortly */ -+ -+struct cryptkop { -+ struct list_head krp_next; -+ wait_queue_head_t krp_waitq; -+ -+ int krp_flags; -+#define CRYPTO_KF_DONE 0x0001 /* Operation completed */ -+#define CRYPTO_KF_CBIMM 0x0002 /* Do callback immediately */ -+ -+ u_int krp_op; /* ie. CRK_MOD_EXP or other */ -+ u_int krp_status; /* return status */ -+ u_short krp_iparams; /* # of input parameters */ -+ u_short krp_oparams; /* # of output parameters */ -+ u_int krp_crid; /* desired device, etc. */ -+ u_int32_t krp_hid; -+ struct crparam krp_param[CRK_MAXPARAM]; /* kvm */ -+ int (*krp_callback)(struct cryptkop *); -+}; -+ -+#include -+ -+/* -+ * Session ids are 64 bits. The lower 32 bits contain a "local id" which -+ * is a driver-private session identifier. The upper 32 bits contain a -+ * "hardware id" used by the core crypto code to identify the driver and -+ * a copy of the driver's capabilities that can be used by client code to -+ * optimize operation. -+ */ -+#define CRYPTO_SESID2HID(_sid) (((_sid) >> 32) & 0x00ffffff) -+#define CRYPTO_SESID2CAPS(_sid) (((_sid) >> 32) & 0xff000000) -+#define CRYPTO_SESID2LID(_sid) (((u_int32_t) (_sid)) & 0xffffffff) -+ -+extern int crypto_newsession(u_int64_t *sid, struct cryptoini *cri, int hard); -+extern int crypto_freesession(u_int64_t sid); -+#define CRYPTOCAP_F_HARDWARE CRYPTO_FLAG_HARDWARE -+#define CRYPTOCAP_F_SOFTWARE CRYPTO_FLAG_SOFTWARE -+#define CRYPTOCAP_F_SYNC 0x04000000 /* operates synchronously */ -+extern int32_t crypto_get_driverid(device_t dev, int flags); -+extern int crypto_find_driver(const char *); -+extern device_t crypto_find_device_byhid(int hid); -+extern int crypto_getcaps(int hid); -+extern int crypto_register(u_int32_t driverid, int alg, u_int16_t maxoplen, -+ u_int32_t flags); -+extern int crypto_kregister(u_int32_t, int, u_int32_t); -+extern int crypto_unregister(u_int32_t driverid, int alg); -+extern int crypto_unregister_all(u_int32_t driverid); -+extern int crypto_dispatch(struct cryptop *crp); -+extern int crypto_kdispatch(struct cryptkop *); -+#define CRYPTO_SYMQ 0x1 -+#define CRYPTO_ASYMQ 0x2 -+extern int crypto_unblock(u_int32_t, int); -+extern void crypto_done(struct cryptop *crp); -+extern void crypto_kdone(struct cryptkop *); -+extern int crypto_getfeat(int *); -+ -+extern void crypto_freereq(struct cryptop *crp); -+extern struct cryptop *crypto_getreq(int num); -+ -+extern int crypto_usercrypto; /* userland may do crypto requests */ -+extern int crypto_userasymcrypto; /* userland may do asym crypto reqs */ -+extern int crypto_devallowsoft; /* only use hardware crypto */ -+ -+/* -+ * random number support, crypto_unregister_all will unregister -+ */ -+extern int crypto_rregister(u_int32_t driverid, -+ int (*read_random)(void *arg, u_int32_t *buf, int len), void *arg); -+extern int crypto_runregister_all(u_int32_t driverid); -+ -+/* -+ * Crypto-related utility routines used mainly by drivers. -+ * -+ * XXX these don't really belong here; but for now they're -+ * kept apart from the rest of the system. -+ */ -+struct uio; -+extern void cuio_copydata(struct uio* uio, int off, int len, caddr_t cp); -+extern void cuio_copyback(struct uio* uio, int off, int len, caddr_t cp); -+extern struct iovec *cuio_getptr(struct uio *uio, int loc, int *off); -+ -+extern void crypto_copyback(int flags, caddr_t buf, int off, int size, -+ caddr_t in); -+extern void crypto_copydata(int flags, caddr_t buf, int off, int size, -+ caddr_t out); -+extern int crypto_apply(int flags, caddr_t buf, int off, int len, -+ int (*f)(void *, void *, u_int), void *arg); -+ -+#endif /* __KERNEL__ */ -+#endif /* _CRYPTO_CRYPTO_H_ */ -diff -Nur linux-2.6.36.orig/crypto/ocf/cryptosoft.c linux-2.6.36/crypto/ocf/cryptosoft.c ---- linux-2.6.36.orig/crypto/ocf/cryptosoft.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/cryptosoft.c 2010-11-09 20:28:04.532495450 +0100 -@@ -0,0 +1,1210 @@ -+/* -+ * An OCF module that uses the linux kernel cryptoapi, based on the -+ * original cryptosoft for BSD by Angelos D. Keromytis (angelos@cis.upenn.edu) -+ * but is mostly unrecognisable, -+ * -+ * Written by David McCullough -+ * Copyright (C) 2004-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * ALTERNATIVELY, provided that this notice is retained in full, this product -+ * may be distributed under the terms of the GNU General Public License (GPL), -+ * in which case the provisions of the GPL apply INSTEAD OF those given above. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ * --------------------------------------------------------------------------- -+ */ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,10) -+#include -+#endif -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29) -+#include -+#endif -+ -+#include -+#include -+ -+struct { -+ softc_device_decl sc_dev; -+} swcr_softc; -+ -+#define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK) -+ -+#define SW_TYPE_CIPHER 0x01 -+#define SW_TYPE_HMAC 0x02 -+#define SW_TYPE_HASH 0x04 -+#define SW_TYPE_COMP 0x08 -+#define SW_TYPE_BLKCIPHER 0x10 -+#define SW_TYPE_ALG_MASK 0x1f -+ -+#define SW_TYPE_ASYNC 0x8000 -+ -+/* We change some of the above if we have an async interface */ -+ -+#define SW_TYPE_ALG_AMASK (SW_TYPE_ALG_MASK | SW_TYPE_ASYNC) -+ -+#define SW_TYPE_ABLKCIPHER (SW_TYPE_BLKCIPHER | SW_TYPE_ASYNC) -+#define SW_TYPE_AHASH (SW_TYPE_HASH | SW_TYPE_ASYNC) -+#define SW_TYPE_AHMAC (SW_TYPE_HMAC | SW_TYPE_ASYNC) -+ -+#define SCATTERLIST_MAX 16 -+ -+struct swcr_data { -+ int sw_type; -+ int sw_alg; -+ struct crypto_tfm *sw_tfm; -+ union { -+ struct { -+ char *sw_key; -+ int sw_klen; -+ int sw_mlen; -+ } hmac; -+ void *sw_comp_buf; -+ } u; -+ struct swcr_data *sw_next; -+}; -+ -+struct swcr_req { -+ struct swcr_data *sw_head; -+ struct swcr_data *sw; -+ struct cryptop *crp; -+ struct cryptodesc *crd; -+ struct scatterlist sg[SCATTERLIST_MAX]; -+ unsigned char iv[EALG_MAX_BLOCK_LEN]; -+ char result[HASH_MAX_LEN]; -+ void *crypto_req; -+}; -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) -+static kmem_cache_t *swcr_req_cache; -+#else -+static struct kmem_cache *swcr_req_cache; -+#endif -+ -+#ifndef CRYPTO_TFM_MODE_CBC -+/* -+ * As of linux-2.6.21 this is no longer defined, and presumably no longer -+ * needed to be passed into the crypto core code. -+ */ -+#define CRYPTO_TFM_MODE_CBC 0 -+#define CRYPTO_TFM_MODE_ECB 0 -+#endif -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) -+ /* -+ * Linux 2.6.19 introduced a new Crypto API, setup macro's to convert new -+ * API into old API. -+ */ -+ -+ /* Symmetric/Block Cipher */ -+ struct blkcipher_desc -+ { -+ struct crypto_tfm *tfm; -+ void *info; -+ }; -+ #define ecb(X) #X , CRYPTO_TFM_MODE_ECB -+ #define cbc(X) #X , CRYPTO_TFM_MODE_CBC -+ #define crypto_has_blkcipher(X, Y, Z) crypto_alg_available(X, 0) -+ #define crypto_blkcipher_cast(X) X -+ #define crypto_blkcipher_tfm(X) X -+ #define crypto_alloc_blkcipher(X, Y, Z) crypto_alloc_tfm(X, mode) -+ #define crypto_blkcipher_ivsize(X) crypto_tfm_alg_ivsize(X) -+ #define crypto_blkcipher_blocksize(X) crypto_tfm_alg_blocksize(X) -+ #define crypto_blkcipher_setkey(X, Y, Z) crypto_cipher_setkey(X, Y, Z) -+ #define crypto_blkcipher_encrypt_iv(W, X, Y, Z) \ -+ crypto_cipher_encrypt_iv((W)->tfm, X, Y, Z, (u8 *)((W)->info)) -+ #define crypto_blkcipher_decrypt_iv(W, X, Y, Z) \ -+ crypto_cipher_decrypt_iv((W)->tfm, X, Y, Z, (u8 *)((W)->info)) -+ #define crypto_blkcipher_set_flags(x, y) /* nop */ -+ -+ /* Hash/HMAC/Digest */ -+ struct hash_desc -+ { -+ struct crypto_tfm *tfm; -+ }; -+ #define hmac(X) #X , 0 -+ #define crypto_has_hash(X, Y, Z) crypto_alg_available(X, 0) -+ #define crypto_hash_cast(X) X -+ #define crypto_hash_tfm(X) X -+ #define crypto_alloc_hash(X, Y, Z) crypto_alloc_tfm(X, mode) -+ #define crypto_hash_digestsize(X) crypto_tfm_alg_digestsize(X) -+ #define crypto_hash_digest(W, X, Y, Z) \ -+ crypto_digest_digest((W)->tfm, X, sg_num, Z) -+ -+ /* Asymmetric Cipher */ -+ #define crypto_has_cipher(X, Y, Z) crypto_alg_available(X, 0) -+ -+ /* Compression */ -+ #define crypto_has_comp(X, Y, Z) crypto_alg_available(X, 0) -+ #define crypto_comp_tfm(X) X -+ #define crypto_comp_cast(X) X -+ #define crypto_alloc_comp(X, Y, Z) crypto_alloc_tfm(X, mode) -+ #define plain(X) #X , 0 -+#else -+ #define ecb(X) "ecb(" #X ")" , 0 -+ #define cbc(X) "cbc(" #X ")" , 0 -+ #define hmac(X) "hmac(" #X ")" , 0 -+ #define plain(X) #X , 0 -+#endif /* if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) */ -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22) -+/* no ablkcipher in older kernels */ -+#define crypto_alloc_ablkcipher(a,b,c) (NULL) -+#define crypto_ablkcipher_tfm(x) ((struct crypto_tfm *)(x)) -+#define crypto_ablkcipher_set_flags(a, b) /* nop */ -+#define crypto_ablkcipher_setkey(x, y, z) (-EINVAL) -+#define crypto_has_ablkcipher(a,b,c) (0) -+#else -+#define HAVE_ABLKCIPHER -+#endif -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,32) -+/* no ahash in older kernels */ -+#define crypto_ahash_tfm(x) ((struct crypto_tfm *)(x)) -+#define crypto_alloc_ahash(a,b,c) (NULL) -+#define crypto_ahash_digestsize(x) 0 -+#else -+#define HAVE_AHASH -+#endif -+ -+struct crypto_details { -+ char *alg_name; -+ int mode; -+ int sw_type; -+}; -+ -+static struct crypto_details crypto_details[] = { -+ [CRYPTO_DES_CBC] = { cbc(des), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_3DES_CBC] = { cbc(des3_ede), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_BLF_CBC] = { cbc(blowfish), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_CAST_CBC] = { cbc(cast5), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_SKIPJACK_CBC] = { cbc(skipjack), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_MD5_HMAC] = { hmac(md5), SW_TYPE_HMAC, }, -+ [CRYPTO_SHA1_HMAC] = { hmac(sha1), SW_TYPE_HMAC, }, -+ [CRYPTO_RIPEMD160_HMAC] = { hmac(ripemd160), SW_TYPE_HMAC, }, -+ [CRYPTO_MD5_KPDK] = { plain(md5-kpdk), SW_TYPE_HASH, }, -+ [CRYPTO_SHA1_KPDK] = { plain(sha1-kpdk), SW_TYPE_HASH, }, -+ [CRYPTO_AES_CBC] = { cbc(aes), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_ARC4] = { ecb(arc4), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_MD5] = { plain(md5), SW_TYPE_HASH, }, -+ [CRYPTO_SHA1] = { plain(sha1), SW_TYPE_HASH, }, -+ [CRYPTO_NULL_HMAC] = { hmac(digest_null), SW_TYPE_HMAC, }, -+ [CRYPTO_NULL_CBC] = { cbc(cipher_null), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_DEFLATE_COMP] = { plain(deflate), SW_TYPE_COMP, }, -+ [CRYPTO_SHA2_256_HMAC] = { hmac(sha256), SW_TYPE_HMAC, }, -+ [CRYPTO_SHA2_384_HMAC] = { hmac(sha384), SW_TYPE_HMAC, }, -+ [CRYPTO_SHA2_512_HMAC] = { hmac(sha512), SW_TYPE_HMAC, }, -+ [CRYPTO_CAMELLIA_CBC] = { cbc(camellia), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_SHA2_256] = { plain(sha256), SW_TYPE_HASH, }, -+ [CRYPTO_SHA2_384] = { plain(sha384), SW_TYPE_HASH, }, -+ [CRYPTO_SHA2_512] = { plain(sha512), SW_TYPE_HASH, }, -+ [CRYPTO_RIPEMD160] = { plain(ripemd160), SW_TYPE_HASH, }, -+}; -+ -+int32_t swcr_id = -1; -+module_param(swcr_id, int, 0444); -+MODULE_PARM_DESC(swcr_id, "Read-Only OCF ID for cryptosoft driver"); -+ -+int swcr_fail_if_compression_grows = 1; -+module_param(swcr_fail_if_compression_grows, int, 0644); -+MODULE_PARM_DESC(swcr_fail_if_compression_grows, -+ "Treat compression that results in more data as a failure"); -+ -+int swcr_no_ahash = 0; -+module_param(swcr_no_ahash, int, 0644); -+MODULE_PARM_DESC(swcr_no_ahash, -+ "Do not use async hash/hmac even if available"); -+ -+int swcr_no_ablk = 0; -+module_param(swcr_no_ablk, int, 0644); -+MODULE_PARM_DESC(swcr_no_ablk, -+ "Do not use async blk ciphers even if available"); -+ -+static struct swcr_data **swcr_sessions = NULL; -+static u_int32_t swcr_sesnum = 0; -+ -+static int swcr_process(device_t, struct cryptop *, int); -+static int swcr_newsession(device_t, u_int32_t *, struct cryptoini *); -+static int swcr_freesession(device_t, u_int64_t); -+ -+static device_method_t swcr_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, swcr_newsession), -+ DEVMETHOD(cryptodev_freesession,swcr_freesession), -+ DEVMETHOD(cryptodev_process, swcr_process), -+}; -+ -+#define debug swcr_debug -+int swcr_debug = 0; -+module_param(swcr_debug, int, 0644); -+MODULE_PARM_DESC(swcr_debug, "Enable debug"); -+ -+static void swcr_process_req(struct swcr_req *req); -+ -+/* -+ * Generate a new software session. -+ */ -+static int -+swcr_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) -+{ -+ struct swcr_data **swd; -+ u_int32_t i; -+ int error; -+ char *algo; -+ int mode; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid == NULL || cri == NULL) { -+ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ if (swcr_sessions) { -+ for (i = 1; i < swcr_sesnum; i++) -+ if (swcr_sessions[i] == NULL) -+ break; -+ } else -+ i = 1; /* NB: to silence compiler warning */ -+ -+ if (swcr_sessions == NULL || i == swcr_sesnum) { -+ if (swcr_sessions == NULL) { -+ i = 1; /* We leave swcr_sessions[0] empty */ -+ swcr_sesnum = CRYPTO_SW_SESSIONS; -+ } else -+ swcr_sesnum *= 2; -+ -+ swd = kmalloc(swcr_sesnum * sizeof(struct swcr_data *), SLAB_ATOMIC); -+ if (swd == NULL) { -+ /* Reset session number */ -+ if (swcr_sesnum == CRYPTO_SW_SESSIONS) -+ swcr_sesnum = 0; -+ else -+ swcr_sesnum /= 2; -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memset(swd, 0, swcr_sesnum * sizeof(struct swcr_data *)); -+ -+ /* Copy existing sessions */ -+ if (swcr_sessions) { -+ memcpy(swd, swcr_sessions, -+ (swcr_sesnum / 2) * sizeof(struct swcr_data *)); -+ kfree(swcr_sessions); -+ } -+ -+ swcr_sessions = swd; -+ } -+ -+ swd = &swcr_sessions[i]; -+ *sid = i; -+ -+ while (cri) { -+ *swd = (struct swcr_data *) kmalloc(sizeof(struct swcr_data), -+ SLAB_ATOMIC); -+ if (*swd == NULL) { -+ swcr_freesession(NULL, i); -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memset(*swd, 0, sizeof(struct swcr_data)); -+ -+ if (cri->cri_alg < 0 || -+ cri->cri_alg>=sizeof(crypto_details)/sizeof(crypto_details[0])){ -+ printk("cryptosoft: Unknown algorithm 0x%x\n", cri->cri_alg); -+ swcr_freesession(NULL, i); -+ return EINVAL; -+ } -+ -+ algo = crypto_details[cri->cri_alg].alg_name; -+ if (!algo || !*algo) { -+ printk("cryptosoft: Unsupported algorithm 0x%x\n", cri->cri_alg); -+ swcr_freesession(NULL, i); -+ return EINVAL; -+ } -+ -+ mode = crypto_details[cri->cri_alg].mode; -+ (*swd)->sw_type = crypto_details[cri->cri_alg].sw_type; -+ (*swd)->sw_alg = cri->cri_alg; -+ -+ /* Algorithm specific configuration */ -+ switch (cri->cri_alg) { -+ case CRYPTO_NULL_CBC: -+ cri->cri_klen = 0; /* make it work with crypto API */ -+ break; -+ default: -+ break; -+ } -+ -+ if ((*swd)->sw_type & SW_TYPE_BLKCIPHER) { -+ dprintk("%s crypto_alloc_*blkcipher(%s, 0x%x)\n", __FUNCTION__, -+ algo, mode); -+ -+ /* try async first */ -+ (*swd)->sw_tfm = swcr_no_ablk ? NULL : -+ crypto_ablkcipher_tfm(crypto_alloc_ablkcipher(algo, 0, 0)); -+ if ((*swd)->sw_tfm) { -+ dprintk("%s %s cipher is async\n", __FUNCTION__, algo); -+ (*swd)->sw_type |= SW_TYPE_ASYNC; -+ } else { -+ dprintk("%s %s cipher is sync\n", __FUNCTION__, algo); -+ (*swd)->sw_tfm = crypto_blkcipher_tfm( -+ crypto_alloc_blkcipher(algo, 0, CRYPTO_ALG_ASYNC)); -+ } -+ if (!(*swd)->sw_tfm) { -+ dprintk("cryptosoft: crypto_alloc_blkcipher failed(%s, 0x%x)\n", -+ algo,mode); -+ swcr_freesession(NULL, i); -+ return EINVAL; -+ } -+ -+ if (debug) { -+ dprintk("%s key:cri->cri_klen=%d,(cri->cri_klen + 7)/8=%d", -+ __FUNCTION__, cri->cri_klen, (cri->cri_klen + 7) / 8); -+ for (i = 0; i < (cri->cri_klen + 7) / 8; i++) -+ dprintk("%s0x%x", (i % 8) ? " " : "\n ", -+ cri->cri_key[i] & 0xff); -+ dprintk("\n"); -+ } -+ if ((*swd)->sw_type & SW_TYPE_ASYNC) { -+ /* OCF doesn't enforce keys */ -+ crypto_ablkcipher_set_flags( -+ __crypto_ablkcipher_cast((*swd)->sw_tfm), -+ CRYPTO_TFM_REQ_WEAK_KEY); -+ error = crypto_ablkcipher_setkey( -+ __crypto_ablkcipher_cast((*swd)->sw_tfm), -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ } else { -+ /* OCF doesn't enforce keys */ -+ crypto_blkcipher_set_flags( -+ crypto_blkcipher_cast((*swd)->sw_tfm), -+ CRYPTO_TFM_REQ_WEAK_KEY); -+ error = crypto_blkcipher_setkey( -+ crypto_blkcipher_cast((*swd)->sw_tfm), -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ } -+ if (error) { -+ printk("cryptosoft: setkey failed %d (crt_flags=0x%x)\n", error, -+ (*swd)->sw_tfm->crt_flags); -+ swcr_freesession(NULL, i); -+ return error; -+ } -+ } else if ((*swd)->sw_type & (SW_TYPE_HMAC | SW_TYPE_HASH)) { -+ dprintk("%s crypto_alloc_*hash(%s, 0x%x)\n", __FUNCTION__, -+ algo, mode); -+ -+ /* try async first */ -+ (*swd)->sw_tfm = swcr_no_ahash ? NULL : -+ crypto_ahash_tfm(crypto_alloc_ahash(algo, 0, 0)); -+ if ((*swd)->sw_tfm) { -+ dprintk("%s %s hash is async\n", __FUNCTION__, algo); -+ (*swd)->sw_type |= SW_TYPE_ASYNC; -+ } else { -+ dprintk("%s %s hash is sync\n", __FUNCTION__, algo); -+ (*swd)->sw_tfm = crypto_hash_tfm( -+ crypto_alloc_hash(algo, 0, CRYPTO_ALG_ASYNC)); -+ } -+ -+ if (!(*swd)->sw_tfm) { -+ dprintk("cryptosoft: crypto_alloc_hash failed(%s,0x%x)\n", -+ algo, mode); -+ swcr_freesession(NULL, i); -+ return EINVAL; -+ } -+ -+ (*swd)->u.hmac.sw_klen = (cri->cri_klen + 7) / 8; -+ (*swd)->u.hmac.sw_key = (char *)kmalloc((*swd)->u.hmac.sw_klen, -+ SLAB_ATOMIC); -+ if ((*swd)->u.hmac.sw_key == NULL) { -+ swcr_freesession(NULL, i); -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memcpy((*swd)->u.hmac.sw_key, cri->cri_key, (*swd)->u.hmac.sw_klen); -+ if (cri->cri_mlen) { -+ (*swd)->u.hmac.sw_mlen = cri->cri_mlen; -+ } else if ((*swd)->sw_type & SW_TYPE_ASYNC) { -+ (*swd)->u.hmac.sw_mlen = crypto_ahash_digestsize( -+ __crypto_ahash_cast((*swd)->sw_tfm)); -+ } else { -+ (*swd)->u.hmac.sw_mlen = crypto_hash_digestsize( -+ crypto_hash_cast((*swd)->sw_tfm)); -+ } -+ } else if ((*swd)->sw_type & SW_TYPE_COMP) { -+ (*swd)->sw_tfm = crypto_comp_tfm( -+ crypto_alloc_comp(algo, 0, CRYPTO_ALG_ASYNC)); -+ if (!(*swd)->sw_tfm) { -+ dprintk("cryptosoft: crypto_alloc_comp failed(%s,0x%x)\n", -+ algo, mode); -+ swcr_freesession(NULL, i); -+ return EINVAL; -+ } -+ (*swd)->u.sw_comp_buf = kmalloc(CRYPTO_MAX_DATA_LEN, SLAB_ATOMIC); -+ if ((*swd)->u.sw_comp_buf == NULL) { -+ swcr_freesession(NULL, i); -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ } else { -+ printk("cryptosoft: Unhandled sw_type %d\n", (*swd)->sw_type); -+ swcr_freesession(NULL, i); -+ return EINVAL; -+ } -+ -+ cri = cri->cri_next; -+ swd = &((*swd)->sw_next); -+ } -+ return 0; -+} -+ -+/* -+ * Free a session. -+ */ -+static int -+swcr_freesession(device_t dev, u_int64_t tid) -+{ -+ struct swcr_data *swd; -+ u_int32_t sid = CRYPTO_SESID2LID(tid); -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid > swcr_sesnum || swcr_sessions == NULL || -+ swcr_sessions[sid] == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return(EINVAL); -+ } -+ -+ /* Silently accept and return */ -+ if (sid == 0) -+ return(0); -+ -+ while ((swd = swcr_sessions[sid]) != NULL) { -+ swcr_sessions[sid] = swd->sw_next; -+ if (swd->sw_tfm) { -+ switch (swd->sw_type & SW_TYPE_ALG_AMASK) { -+#ifdef HAVE_AHASH -+ case SW_TYPE_AHMAC: -+ case SW_TYPE_AHASH: -+ crypto_free_ahash(__crypto_ahash_cast(swd->sw_tfm)); -+ break; -+#endif -+#ifdef HAVE_ABLKCIPHER -+ case SW_TYPE_ABLKCIPHER: -+ crypto_free_ablkcipher(__crypto_ablkcipher_cast(swd->sw_tfm)); -+ break; -+#endif -+ case SW_TYPE_BLKCIPHER: -+ crypto_free_blkcipher(crypto_blkcipher_cast(swd->sw_tfm)); -+ break; -+ case SW_TYPE_HMAC: -+ case SW_TYPE_HASH: -+ crypto_free_hash(crypto_hash_cast(swd->sw_tfm)); -+ break; -+ case SW_TYPE_COMP: -+ crypto_free_comp(crypto_comp_cast(swd->sw_tfm)); -+ default: -+ crypto_free_tfm(swd->sw_tfm); -+ break; -+ } -+ swd->sw_tfm = NULL; -+ } -+ if (swd->sw_type & SW_TYPE_COMP) { -+ if (swd->u.sw_comp_buf) -+ kfree(swd->u.sw_comp_buf); -+ } else { -+ if (swd->u.hmac.sw_key) -+ kfree(swd->u.hmac.sw_key); -+ } -+ kfree(swd); -+ } -+ return 0; -+} -+ -+#if defined(HAVE_ABLKCIPHER) || defined(HAVE_AHASH) -+/* older kernels had no async interface */ -+ -+static void swcr_process_callback(struct crypto_async_request *creq, int err) -+{ -+ struct swcr_req *req = creq->data; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (err) { -+ if (err == -EINPROGRESS) -+ return; -+ dprintk("%s() fail %d\n", __FUNCTION__, -err); -+ req->crp->crp_etype = -err; -+ goto done; -+ } -+ -+ switch (req->sw->sw_type & SW_TYPE_ALG_AMASK) { -+ case SW_TYPE_AHMAC: -+ case SW_TYPE_AHASH: -+ crypto_copyback(req->crp->crp_flags, req->crp->crp_buf, -+ req->crd->crd_inject, req->sw->u.hmac.sw_mlen, req->result); -+ ahash_request_free(req->crypto_req); -+ break; -+ case SW_TYPE_ABLKCIPHER: -+ ablkcipher_request_free(req->crypto_req); -+ break; -+ default: -+ req->crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ req->crd = req->crd->crd_next; -+ if (req->crd) { -+ swcr_process_req(req); -+ return; -+ } -+ -+done: -+ dprintk("%s crypto_done %p\n", __FUNCTION__, req); -+ crypto_done(req->crp); -+ kmem_cache_free(swcr_req_cache, req); -+} -+#endif /* defined(HAVE_ABLKCIPHER) || defined(HAVE_AHASH) */ -+ -+ -+static void swcr_process_req(struct swcr_req *req) -+{ -+ struct swcr_data *sw; -+ struct cryptop *crp = req->crp; -+ struct cryptodesc *crd = req->crd; -+ struct sk_buff *skb = (struct sk_buff *) crp->crp_buf; -+ struct uio *uiop = (struct uio *) crp->crp_buf; -+ int sg_num, sg_len, skip; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ /* -+ * Find the crypto context. -+ * -+ * XXX Note that the logic here prevents us from having -+ * XXX the same algorithm multiple times in a session -+ * XXX (or rather, we can but it won't give us the right -+ * XXX results). To do that, we'd need some way of differentiating -+ * XXX between the various instances of an algorithm (so we can -+ * XXX locate the correct crypto context). -+ */ -+ for (sw = req->sw_head; sw && sw->sw_alg != crd->crd_alg; sw = sw->sw_next) -+ ; -+ -+ /* No such context ? */ -+ if (sw == NULL) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ goto done; -+ } -+ -+ req->sw = sw; -+ skip = crd->crd_skip; -+ -+ /* -+ * setup the SG list skip from the start of the buffer -+ */ -+ memset(req->sg, 0, sizeof(req->sg)); -+ sg_init_table(req->sg, SCATTERLIST_MAX); -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ int i, len; -+ -+ sg_num = 0; -+ sg_len = 0; -+ -+ if (skip < skb_headlen(skb)) { -+ len = skb_headlen(skb) - skip; -+ if (len + sg_len > crd->crd_len) -+ len = crd->crd_len - sg_len; -+ sg_set_page(&req->sg[sg_num], -+ virt_to_page(skb->data + skip), len, -+ offset_in_page(skb->data + skip)); -+ sg_len += len; -+ sg_num++; -+ skip = 0; -+ } else -+ skip -= skb_headlen(skb); -+ -+ for (i = 0; sg_len < crd->crd_len && -+ i < skb_shinfo(skb)->nr_frags && -+ sg_num < SCATTERLIST_MAX; i++) { -+ if (skip < skb_shinfo(skb)->frags[i].size) { -+ len = skb_shinfo(skb)->frags[i].size - skip; -+ if (len + sg_len > crd->crd_len) -+ len = crd->crd_len - sg_len; -+ sg_set_page(&req->sg[sg_num], -+ skb_shinfo(skb)->frags[i].page, -+ len, -+ skb_shinfo(skb)->frags[i].page_offset + skip); -+ sg_len += len; -+ sg_num++; -+ skip = 0; -+ } else -+ skip -= skb_shinfo(skb)->frags[i].size; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ int len; -+ -+ sg_len = 0; -+ for (sg_num = 0; sg_len < crd->crd_len && -+ sg_num < uiop->uio_iovcnt && -+ sg_num < SCATTERLIST_MAX; sg_num++) { -+ if (skip <= uiop->uio_iov[sg_num].iov_len) { -+ len = uiop->uio_iov[sg_num].iov_len - skip; -+ if (len + sg_len > crd->crd_len) -+ len = crd->crd_len - sg_len; -+ sg_set_page(&req->sg[sg_num], -+ virt_to_page(uiop->uio_iov[sg_num].iov_base+skip), -+ len, -+ offset_in_page(uiop->uio_iov[sg_num].iov_base+skip)); -+ sg_len += len; -+ skip = 0; -+ } else -+ skip -= uiop->uio_iov[sg_num].iov_len; -+ } -+ } else { -+ sg_len = (crp->crp_ilen - skip); -+ if (sg_len > crd->crd_len) -+ sg_len = crd->crd_len; -+ sg_set_page(&req->sg[0], virt_to_page(crp->crp_buf + skip), -+ sg_len, offset_in_page(crp->crp_buf + skip)); -+ sg_num = 1; -+ } -+ -+ switch (sw->sw_type & SW_TYPE_ALG_AMASK) { -+ -+#ifdef HAVE_AHASH -+ case SW_TYPE_AHMAC: -+ case SW_TYPE_AHASH: -+ { -+ int ret; -+ -+ /* check we have room for the result */ -+ if (crp->crp_ilen - crd->crd_inject < sw->u.hmac.sw_mlen) { -+ dprintk("cryptosoft: EINVAL crp_ilen=%d, len=%d, inject=%d " -+ "digestsize=%d\n", crp->crp_ilen, crd->crd_skip + sg_len, -+ crd->crd_inject, sw->u.hmac.sw_mlen); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ req->crypto_req = -+ ahash_request_alloc(__crypto_ahash_cast(sw->sw_tfm),GFP_KERNEL); -+ if (!req->crypto_req) { -+ crp->crp_etype = ENOMEM; -+ dprintk("%s,%d: ENOMEM ahash_request_alloc", __FILE__, __LINE__); -+ goto done; -+ } -+ -+ ahash_request_set_callback(req->crypto_req, -+ CRYPTO_TFM_REQ_MAY_BACKLOG, swcr_process_callback, req); -+ -+ memset(req->result, 0, sizeof(req->result)); -+ -+ if (sw->sw_type & SW_TYPE_AHMAC) -+ crypto_ahash_setkey(__crypto_ahash_cast(sw->sw_tfm), -+ sw->u.hmac.sw_key, sw->u.hmac.sw_klen); -+ ahash_request_set_crypt(req->crypto_req, req->sg, req->result, sg_len); -+ ret = crypto_ahash_digest(req->crypto_req); -+ switch (ret) { -+ case -EINPROGRESS: -+ case -EBUSY: -+ return; -+ default: -+ case 0: -+ dprintk("hash OP %s %d\n", ret ? "failed" : "success", ret); -+ crp->crp_etype = ret; -+ ahash_request_free(req->crypto_req); -+ goto done; -+ } -+ } break; -+#endif /* HAVE_AHASH */ -+ -+#ifdef HAVE_ABLKCIPHER -+ case SW_TYPE_ABLKCIPHER: { -+ int ret; -+ unsigned char *ivp = req->iv; -+ int ivsize = -+ crypto_ablkcipher_ivsize(__crypto_ablkcipher_cast(sw->sw_tfm)); -+ -+ if (sg_len < crypto_ablkcipher_blocksize( -+ __crypto_ablkcipher_cast(sw->sw_tfm))) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: EINVAL len %d < %d\n", __FILE__, __LINE__, -+ sg_len, crypto_ablkcipher_blocksize( -+ __crypto_ablkcipher_cast(sw->sw_tfm))); -+ goto done; -+ } -+ -+ if (ivsize > sizeof(req->iv)) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ goto done; -+ } -+ -+ req->crypto_req = ablkcipher_request_alloc( -+ __crypto_ablkcipher_cast(sw->sw_tfm), GFP_KERNEL); -+ if (!req->crypto_req) { -+ crp->crp_etype = ENOMEM; -+ dprintk("%s,%d: ENOMEM ablkcipher_request_alloc", -+ __FILE__, __LINE__); -+ goto done; -+ } -+ -+ ablkcipher_request_set_callback(req->crypto_req, -+ CRYPTO_TFM_REQ_MAY_BACKLOG, swcr_process_callback, req); -+ -+ if (crd->crd_flags & CRD_F_KEY_EXPLICIT) { -+ int i, error; -+ -+ if (debug) { -+ dprintk("%s key:", __FUNCTION__); -+ for (i = 0; i < (crd->crd_klen + 7) / 8; i++) -+ dprintk("%s0x%x", (i % 8) ? " " : "\n ", -+ crd->crd_key[i] & 0xff); -+ dprintk("\n"); -+ } -+ /* OCF doesn't enforce keys */ -+ crypto_ablkcipher_set_flags(__crypto_ablkcipher_cast(sw->sw_tfm), -+ CRYPTO_TFM_REQ_WEAK_KEY); -+ error = crypto_ablkcipher_setkey( -+ __crypto_ablkcipher_cast(sw->sw_tfm), crd->crd_key, -+ (crd->crd_klen + 7) / 8); -+ if (error) { -+ dprintk("cryptosoft: setkey failed %d (crt_flags=0x%x)\n", -+ error, sw->sw_tfm->crt_flags); -+ crp->crp_etype = -error; -+ } -+ } -+ -+ if (crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ -+ -+ if (crd->crd_flags & CRD_F_IV_EXPLICIT) -+ ivp = crd->crd_iv; -+ else -+ get_random_bytes(ivp, ivsize); -+ /* -+ * do we have to copy the IV back to the buffer ? -+ */ -+ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, ivsize, (caddr_t)ivp); -+ } -+ ablkcipher_request_set_crypt(req->crypto_req, req->sg, req->sg, -+ sg_len, ivp); -+ ret = crypto_ablkcipher_encrypt(req->crypto_req); -+ -+ } else { /*decrypt */ -+ -+ if (crd->crd_flags & CRD_F_IV_EXPLICIT) -+ ivp = crd->crd_iv; -+ else -+ crypto_copydata(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, ivsize, (caddr_t)ivp); -+ ablkcipher_request_set_crypt(req->crypto_req, req->sg, req->sg, -+ sg_len, ivp); -+ ret = crypto_ablkcipher_decrypt(req->crypto_req); -+ } -+ -+ switch (ret) { -+ case -EINPROGRESS: -+ case -EBUSY: -+ return; -+ default: -+ case 0: -+ dprintk("crypto OP %s %d\n", ret ? "failed" : "success", ret); -+ crp->crp_etype = ret; -+ goto done; -+ } -+ } break; -+#endif /* HAVE_ABLKCIPHER */ -+ -+ case SW_TYPE_BLKCIPHER: { -+ unsigned char iv[EALG_MAX_BLOCK_LEN]; -+ unsigned char *ivp = iv; -+ struct blkcipher_desc desc; -+ int ivsize = crypto_blkcipher_ivsize(crypto_blkcipher_cast(sw->sw_tfm)); -+ -+ if (sg_len < crypto_blkcipher_blocksize( -+ crypto_blkcipher_cast(sw->sw_tfm))) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: EINVAL len %d < %d\n", __FILE__, __LINE__, -+ sg_len, crypto_blkcipher_blocksize( -+ crypto_blkcipher_cast(sw->sw_tfm))); -+ goto done; -+ } -+ -+ if (ivsize > sizeof(iv)) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ goto done; -+ } -+ -+ if (crd->crd_flags & CRD_F_KEY_EXPLICIT) { -+ int i, error; -+ -+ if (debug) { -+ dprintk("%s key:", __FUNCTION__); -+ for (i = 0; i < (crd->crd_klen + 7) / 8; i++) -+ dprintk("%s0x%x", (i % 8) ? " " : "\n ", -+ crd->crd_key[i] & 0xff); -+ dprintk("\n"); -+ } -+ /* OCF doesn't enforce keys */ -+ crypto_blkcipher_set_flags(crypto_blkcipher_cast(sw->sw_tfm), -+ CRYPTO_TFM_REQ_WEAK_KEY); -+ error = crypto_blkcipher_setkey( -+ crypto_blkcipher_cast(sw->sw_tfm), crd->crd_key, -+ (crd->crd_klen + 7) / 8); -+ if (error) { -+ dprintk("cryptosoft: setkey failed %d (crt_flags=0x%x)\n", -+ error, sw->sw_tfm->crt_flags); -+ crp->crp_etype = -error; -+ } -+ } -+ -+ memset(&desc, 0, sizeof(desc)); -+ desc.tfm = crypto_blkcipher_cast(sw->sw_tfm); -+ -+ if (crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ -+ -+ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { -+ ivp = crd->crd_iv; -+ } else { -+ get_random_bytes(ivp, ivsize); -+ } -+ /* -+ * do we have to copy the IV back to the buffer ? -+ */ -+ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, ivsize, (caddr_t)ivp); -+ } -+ desc.info = ivp; -+ crypto_blkcipher_encrypt_iv(&desc, req->sg, req->sg, sg_len); -+ -+ } else { /*decrypt */ -+ -+ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { -+ ivp = crd->crd_iv; -+ } else { -+ crypto_copydata(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, ivsize, (caddr_t)ivp); -+ } -+ desc.info = ivp; -+ crypto_blkcipher_decrypt_iv(&desc, req->sg, req->sg, sg_len); -+ } -+ } break; -+ -+ case SW_TYPE_HMAC: -+ case SW_TYPE_HASH: -+ { -+ char result[HASH_MAX_LEN]; -+ struct hash_desc desc; -+ -+ /* check we have room for the result */ -+ if (crp->crp_ilen - crd->crd_inject < sw->u.hmac.sw_mlen) { -+ dprintk("cryptosoft: EINVAL crp_ilen=%d, len=%d, inject=%d " -+ "digestsize=%d\n", crp->crp_ilen, crd->crd_skip + sg_len, -+ crd->crd_inject, sw->u.hmac.sw_mlen); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ memset(&desc, 0, sizeof(desc)); -+ desc.tfm = crypto_hash_cast(sw->sw_tfm); -+ -+ memset(result, 0, sizeof(result)); -+ -+ if (sw->sw_type & SW_TYPE_HMAC) { -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) -+ crypto_hmac(sw->sw_tfm, sw->u.hmac.sw_key, &sw->u.hmac.sw_klen, -+ req->sg, sg_num, result); -+#else -+ crypto_hash_setkey(desc.tfm, sw->u.hmac.sw_key, -+ sw->u.hmac.sw_klen); -+ crypto_hash_digest(&desc, req->sg, sg_len, result); -+#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) */ -+ -+ } else { /* SW_TYPE_HASH */ -+ crypto_hash_digest(&desc, req->sg, sg_len, result); -+ } -+ -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, sw->u.hmac.sw_mlen, result); -+ } -+ break; -+ -+ case SW_TYPE_COMP: { -+ void *ibuf = NULL; -+ void *obuf = sw->u.sw_comp_buf; -+ int ilen = sg_len, olen = CRYPTO_MAX_DATA_LEN; -+ int ret = 0; -+ -+ /* -+ * we need to use an additional copy if there is more than one -+ * input chunk since the kernel comp routines do not handle -+ * SG yet. Otherwise we just use the input buffer as is. -+ * Rather than allocate another buffer we just split the tmp -+ * buffer we already have. -+ * Perhaps we should just use zlib directly ? -+ */ -+ if (sg_num > 1) { -+ int blk; -+ -+ ibuf = obuf; -+ for (blk = 0; blk < sg_num; blk++) { -+ memcpy(obuf, sg_virt(&req->sg[blk]), -+ req->sg[blk].length); -+ obuf += req->sg[blk].length; -+ } -+ olen -= sg_len; -+ } else -+ ibuf = sg_virt(&req->sg[0]); -+ -+ if (crd->crd_flags & CRD_F_ENCRYPT) { /* compress */ -+ ret = crypto_comp_compress(crypto_comp_cast(sw->sw_tfm), -+ ibuf, ilen, obuf, &olen); -+ if (!ret && olen > crd->crd_len) { -+ dprintk("cryptosoft: ERANGE compress %d into %d\n", -+ crd->crd_len, olen); -+ if (swcr_fail_if_compression_grows) -+ ret = ERANGE; -+ } -+ } else { /* decompress */ -+ ret = crypto_comp_decompress(crypto_comp_cast(sw->sw_tfm), -+ ibuf, ilen, obuf, &olen); -+ if (!ret && (olen + crd->crd_inject) > crp->crp_olen) { -+ dprintk("cryptosoft: ETOOSMALL decompress %d into %d, " -+ "space for %d,at offset %d\n", -+ crd->crd_len, olen, crp->crp_olen, crd->crd_inject); -+ ret = ETOOSMALL; -+ } -+ } -+ if (ret) -+ dprintk("%s,%d: ret = %d\n", __FILE__, __LINE__, ret); -+ -+ /* -+ * on success copy result back, -+ * linux crpyto API returns -errno, we need to fix that -+ */ -+ crp->crp_etype = ret < 0 ? -ret : ret; -+ if (ret == 0) { -+ /* copy back the result and return it's size */ -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, olen, obuf); -+ crp->crp_olen = olen; -+ } -+ -+ -+ } break; -+ -+ default: -+ /* Unknown/unsupported algorithm */ -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+done: -+ crypto_done(crp); -+ kmem_cache_free(swcr_req_cache, req); -+} -+ -+ -+/* -+ * Process a crypto request. -+ */ -+static int -+swcr_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ struct swcr_req *req = NULL; -+ u_int32_t lid; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ /* Sanity check */ -+ if (crp == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ crp->crp_etype = 0; -+ -+ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ lid = crp->crp_sid & 0xffffffff; -+ if (lid >= swcr_sesnum || lid == 0 || swcr_sessions == NULL || -+ swcr_sessions[lid] == NULL) { -+ crp->crp_etype = ENOENT; -+ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); -+ goto done; -+ } -+ -+ /* -+ * do some error checking outside of the loop for SKB and IOV processing -+ * this leaves us with valid skb or uiop pointers for later -+ */ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ struct sk_buff *skb = (struct sk_buff *) crp->crp_buf; -+ if (skb_shinfo(skb)->nr_frags >= SCATTERLIST_MAX) { -+ printk("%s,%d: %d nr_frags > SCATTERLIST_MAX", __FILE__, __LINE__, -+ skb_shinfo(skb)->nr_frags); -+ goto done; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ struct uio *uiop = (struct uio *) crp->crp_buf; -+ if (uiop->uio_iovcnt > SCATTERLIST_MAX) { -+ printk("%s,%d: %d uio_iovcnt > SCATTERLIST_MAX", __FILE__, __LINE__, -+ uiop->uio_iovcnt); -+ goto done; -+ } -+ } -+ -+ /* -+ * setup a new request ready for queuing -+ */ -+ req = kmem_cache_alloc(swcr_req_cache, SLAB_ATOMIC); -+ if (req == NULL) { -+ dprintk("%s,%d: ENOMEM\n", __FILE__, __LINE__); -+ crp->crp_etype = ENOMEM; -+ goto done; -+ } -+ memset(req, 0, sizeof(*req)); -+ -+ req->sw_head = swcr_sessions[lid]; -+ req->crp = crp; -+ req->crd = crp->crp_desc; -+ -+ swcr_process_req(req); -+ return 0; -+ -+done: -+ crypto_done(crp); -+ if (req) -+ kmem_cache_free(swcr_req_cache, req); -+ return 0; -+} -+ -+ -+static int -+cryptosoft_init(void) -+{ -+ int i, sw_type, mode; -+ char *algo; -+ -+ dprintk("%s(%p)\n", __FUNCTION__, cryptosoft_init); -+ -+ swcr_req_cache = kmem_cache_create("cryptosoft_req", -+ sizeof(struct swcr_req), 0, SLAB_HWCACHE_ALIGN, NULL -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) -+ , NULL -+#endif -+ ); -+ if (!swcr_req_cache) { -+ printk("cryptosoft: failed to create request cache\n"); -+ return -ENOENT; -+ } -+ -+ softc_device_init(&swcr_softc, "cryptosoft", 0, swcr_methods); -+ -+ swcr_id = crypto_get_driverid(softc_get_device(&swcr_softc), -+ CRYPTOCAP_F_SOFTWARE | CRYPTOCAP_F_SYNC); -+ if (swcr_id < 0) { -+ printk("cryptosoft: Software crypto device cannot initialize!"); -+ return -ENODEV; -+ } -+ -+#define REGISTER(alg) \ -+ crypto_register(swcr_id, alg, 0,0) -+ -+ for (i = 0; i < sizeof(crypto_details)/sizeof(crypto_details[0]); i++) { -+ int found; -+ -+ algo = crypto_details[i].alg_name; -+ if (!algo || !*algo) { -+ dprintk("%s:Algorithm %d not supported\n", __FUNCTION__, i); -+ continue; -+ } -+ -+ mode = crypto_details[i].mode; -+ sw_type = crypto_details[i].sw_type; -+ -+ found = 0; -+ switch (sw_type & SW_TYPE_ALG_MASK) { -+ case SW_TYPE_CIPHER: -+ found = crypto_has_cipher(algo, 0, CRYPTO_ALG_ASYNC); -+ break; -+ case SW_TYPE_HMAC: -+ found = crypto_has_hash(algo, 0, swcr_no_ahash?CRYPTO_ALG_ASYNC:0); -+ break; -+ case SW_TYPE_HASH: -+ found = crypto_has_hash(algo, 0, swcr_no_ahash?CRYPTO_ALG_ASYNC:0); -+ break; -+ case SW_TYPE_COMP: -+ found = crypto_has_comp(algo, 0, CRYPTO_ALG_ASYNC); -+ break; -+ case SW_TYPE_BLKCIPHER: -+ found = crypto_has_blkcipher(algo, 0, CRYPTO_ALG_ASYNC); -+ if (!found && !swcr_no_ablk) -+ found = crypto_has_ablkcipher(algo, 0, 0); -+ break; -+ } -+ if (found) { -+ REGISTER(i); -+ } else { -+ dprintk("%s:Algorithm Type %d not supported (algorithm %d:'%s')\n", -+ __FUNCTION__, sw_type, i, algo); -+ } -+ } -+ return 0; -+} -+ -+static void -+cryptosoft_exit(void) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ crypto_unregister_all(swcr_id); -+ swcr_id = -1; -+ kmem_cache_destroy(swcr_req_cache); -+} -+ -+late_initcall(cryptosoft_init); -+module_exit(cryptosoft_exit); -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("Cryptosoft (OCF module for kernel crypto)"); -diff -Nur linux-2.6.36.orig/crypto/ocf/ep80579/icp_asym.c linux-2.6.36/crypto/ocf/ep80579/icp_asym.c ---- linux-2.6.36.orig/crypto/ocf/ep80579/icp_asym.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/ep80579/icp_asym.c 2010-11-09 20:28:04.572486503 +0100 -@@ -0,0 +1,1334 @@ -+/*************************************************************************** -+ * -+ * This file is provided under a dual BSD/GPLv2 license. When using or -+ * redistributing this file, you may do so under either license. -+ * -+ * GPL LICENSE SUMMARY -+ * -+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of version 2 of the GNU General Public License as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. -+ * The full GNU General Public License is included in this distribution -+ * in the file called LICENSE.GPL. -+ * -+ * Contact Information: -+ * Intel Corporation -+ * -+ * BSD LICENSE -+ * -+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * * Neither the name of Intel Corporation nor the names of its -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * -+ * version: Security.L.1.0.2-229 -+ * -+ ***************************************************************************/ -+ -+#include "icp_ocf.h" -+ -+/*The following define values (containing the word 'INDEX') are used to find -+the index of each input buffer of the crypto_kop struct (see OCF cryptodev.h). -+These values were found through analysis of the OCF OpenSSL patch. If the -+calling program uses different input buffer positions, these defines will have -+to be changed.*/ -+ -+/*DIFFIE HELLMAN buffer index values*/ -+#define ICP_DH_KRP_PARAM_PRIME_INDEX (0) -+#define ICP_DH_KRP_PARAM_BASE_INDEX (1) -+#define ICP_DH_KRP_PARAM_PRIVATE_VALUE_INDEX (2) -+#define ICP_DH_KRP_PARAM_RESULT_INDEX (3) -+ -+/*MOD EXP buffer index values*/ -+#define ICP_MOD_EXP_KRP_PARAM_BASE_INDEX (0) -+#define ICP_MOD_EXP_KRP_PARAM_EXPONENT_INDEX (1) -+#define ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX (2) -+#define ICP_MOD_EXP_KRP_PARAM_RESULT_INDEX (3) -+ -+/*MOD EXP CRT buffer index values*/ -+#define ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_P_INDEX (0) -+#define ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_Q_INDEX (1) -+#define ICP_MOD_EXP_CRT_KRP_PARAM_I_INDEX (2) -+#define ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DP_INDEX (3) -+#define ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DQ_INDEX (4) -+#define ICP_MOD_EXP_CRT_KRP_PARAM_COEFF_QINV_INDEX (5) -+#define ICP_MOD_EXP_CRT_KRP_PARAM_RESULT_INDEX (6) -+ -+/*DSA sign buffer index values*/ -+#define ICP_DSA_SIGN_KRP_PARAM_DGST_INDEX (0) -+#define ICP_DSA_SIGN_KRP_PARAM_PRIME_P_INDEX (1) -+#define ICP_DSA_SIGN_KRP_PARAM_PRIME_Q_INDEX (2) -+#define ICP_DSA_SIGN_KRP_PARAM_G_INDEX (3) -+#define ICP_DSA_SIGN_KRP_PARAM_X_INDEX (4) -+#define ICP_DSA_SIGN_KRP_PARAM_R_RESULT_INDEX (5) -+#define ICP_DSA_SIGN_KRP_PARAM_S_RESULT_INDEX (6) -+ -+/*DSA verify buffer index values*/ -+#define ICP_DSA_VERIFY_KRP_PARAM_DGST_INDEX (0) -+#define ICP_DSA_VERIFY_KRP_PARAM_PRIME_P_INDEX (1) -+#define ICP_DSA_VERIFY_KRP_PARAM_PRIME_Q_INDEX (2) -+#define ICP_DSA_VERIFY_KRP_PARAM_G_INDEX (3) -+#define ICP_DSA_VERIFY_KRP_PARAM_PUBKEY_INDEX (4) -+#define ICP_DSA_VERIFY_KRP_PARAM_SIG_R_INDEX (5) -+#define ICP_DSA_VERIFY_KRP_PARAM_SIG_S_INDEX (6) -+ -+/*DSA sign prime Q vs random number K size check values*/ -+#define DONT_RUN_LESS_THAN_CHECK (0) -+#define FAIL_A_IS_GREATER_THAN_B (1) -+#define FAIL_A_IS_EQUAL_TO_B (1) -+#define SUCCESS_A_IS_LESS_THAN_B (0) -+#define DSA_SIGN_RAND_GEN_VAL_CHECK_MAX_ITERATIONS (500) -+ -+/* We need to set a cryptokp success value just in case it is set or allocated -+ and not set to zero outside of this module */ -+#define CRYPTO_OP_SUCCESS (0) -+ -+/*Function to compute Diffie Hellman (DH) phase 1 or phase 2 key values*/ -+static int icp_ocfDrvDHComputeKey(struct cryptkop *krp); -+ -+/*Function to compute a Modular Exponentiation (Mod Exp)*/ -+static int icp_ocfDrvModExp(struct cryptkop *krp); -+ -+/*Function to compute a Mod Exp using the Chinease Remainder Theorem*/ -+static int icp_ocfDrvModExpCRT(struct cryptkop *krp); -+ -+/*Helper function to compute whether the first big number argument is less than -+ the second big number argument */ -+static int -+icp_ocfDrvCheckALessThanB(CpaFlatBuffer * pK, CpaFlatBuffer * pQ, int *doCheck); -+ -+/*Function to sign an input with DSA R and S keys*/ -+static int icp_ocfDrvDsaSign(struct cryptkop *krp); -+ -+/*Function to Verify a DSA buffer signature*/ -+static int icp_ocfDrvDsaVerify(struct cryptkop *krp); -+ -+/*Callback function for DH operation*/ -+static void -+icp_ocfDrvDhP1CallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, CpaFlatBuffer * pLocalOctetStringPV); -+ -+/*Callback function for ME operation*/ -+static void -+icp_ocfDrvModExpCallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, CpaFlatBuffer * pResult); -+ -+/*Callback function for ME CRT operation*/ -+static void -+icp_ocfDrvModExpCRTCallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, CpaFlatBuffer * pOutputData); -+ -+/*Callback function for DSA sign operation*/ -+static void -+icp_ocfDrvDsaRSSignCallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, -+ CpaBoolean protocolStatus, -+ CpaFlatBuffer * pR, CpaFlatBuffer * pS); -+ -+/*Callback function for DSA Verify operation*/ -+static void -+icp_ocfDrvDsaVerifyCallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, CpaBoolean verifyStatus); -+ -+/* Name : icp_ocfDrvPkeProcess -+ * -+ * Description : This function will choose which PKE process to follow -+ * based on the input arguments -+ */ -+int icp_ocfDrvPkeProcess(icp_device_t dev, struct cryptkop *krp, int hint) -+{ -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ -+ if (NULL == krp) { -+ DPRINTK("%s(): Invalid input parameters, cryptkop = %p\n", -+ __FUNCTION__, krp); -+ return EINVAL; -+ } -+ -+ if (CPA_TRUE == icp_atomic_read(&icp_ocfDrvIsExiting)) { -+ krp->krp_status = ECANCELED; -+ return ECANCELED; -+ } -+ -+ switch (krp->krp_op) { -+ case CRK_DH_COMPUTE_KEY: -+ DPRINTK("%s() doing DH_COMPUTE_KEY\n", __FUNCTION__); -+ lacStatus = icp_ocfDrvDHComputeKey(krp); -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): icp_ocfDrvDHComputeKey failed " -+ "(%d).\n", __FUNCTION__, lacStatus); -+ krp->krp_status = ECANCELED; -+ return ECANCELED; -+ } -+ -+ break; -+ -+ case CRK_MOD_EXP: -+ DPRINTK("%s() doing MOD_EXP \n", __FUNCTION__); -+ lacStatus = icp_ocfDrvModExp(krp); -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): icp_ocfDrvModExp failed (%d).\n", -+ __FUNCTION__, lacStatus); -+ krp->krp_status = ECANCELED; -+ return ECANCELED; -+ } -+ -+ break; -+ -+ case CRK_MOD_EXP_CRT: -+ DPRINTK("%s() doing MOD_EXP_CRT \n", __FUNCTION__); -+ lacStatus = icp_ocfDrvModExpCRT(krp); -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): icp_ocfDrvModExpCRT " -+ "failed (%d).\n", __FUNCTION__, lacStatus); -+ krp->krp_status = ECANCELED; -+ return ECANCELED; -+ } -+ -+ break; -+ -+ case CRK_DSA_SIGN: -+ DPRINTK("%s() doing DSA_SIGN \n", __FUNCTION__); -+ lacStatus = icp_ocfDrvDsaSign(krp); -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): icp_ocfDrvDsaSign " -+ "failed (%d).\n", __FUNCTION__, lacStatus); -+ krp->krp_status = ECANCELED; -+ return ECANCELED; -+ } -+ -+ break; -+ -+ case CRK_DSA_VERIFY: -+ DPRINTK("%s() doing DSA_VERIFY \n", __FUNCTION__); -+ lacStatus = icp_ocfDrvDsaVerify(krp); -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): icp_ocfDrvDsaVerify " -+ "failed (%d).\n", __FUNCTION__, lacStatus); -+ krp->krp_status = ECANCELED; -+ return ECANCELED; -+ } -+ -+ break; -+ -+ default: -+ EPRINTK("%s(): Asymettric function not " -+ "supported (%d).\n", __FUNCTION__, krp->krp_op); -+ krp->krp_status = EOPNOTSUPP; -+ return EOPNOTSUPP; -+ } -+ -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+} -+ -+/* Name : icp_ocfDrvSwapBytes -+ * -+ * Description : This function is used to swap the byte order of a buffer. -+ * It has been seen that in general we are passed little endian byte order -+ * buffers, but LAC only accepts big endian byte order buffers. -+ */ -+static void inline icp_ocfDrvSwapBytes(u_int8_t * num, u_int32_t buff_len_bytes) -+{ -+ -+ int i; -+ u_int8_t *end_ptr; -+ u_int8_t hold_val; -+ -+ end_ptr = num + (buff_len_bytes - 1); -+ buff_len_bytes = buff_len_bytes >> 1; -+ for (i = 0; i < buff_len_bytes; i++) { -+ hold_val = *num; -+ *num = *end_ptr; -+ num++; -+ *end_ptr = hold_val; -+ end_ptr--; -+ } -+} -+ -+/* Name : icp_ocfDrvDHComputeKey -+ * -+ * Description : This function will map Diffie Hellman calls from OCF -+ * to the LAC API. OCF uses this function for Diffie Hellman Phase1 and -+ * Phase2. LAC has a separate Diffie Hellman Phase2 call, however both phases -+ * break down to a modular exponentiation. -+ */ -+static int icp_ocfDrvDHComputeKey(struct cryptkop *krp) -+{ -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ void *callbackTag = NULL; -+ CpaCyDhPhase1KeyGenOpData *pPhase1OpData = NULL; -+ CpaFlatBuffer *pLocalOctetStringPV = NULL; -+ uint32_t dh_prime_len_bytes = 0, dh_prime_len_bits = 0; -+ -+ /* Input checks - check prime is a multiple of 8 bits to allow for -+ allocation later */ -+ dh_prime_len_bits = -+ (krp->krp_param[ICP_DH_KRP_PARAM_PRIME_INDEX].crp_nbits); -+ -+ /* LAC can reject prime lengths based on prime key sizes, we just -+ need to make sure we can allocate space for the base and -+ exponent buffers correctly */ -+ if ((dh_prime_len_bits % NUM_BITS_IN_BYTE) != 0) { -+ APRINTK("%s(): Warning Prime number buffer size is not a " -+ "multiple of 8 bits\n", __FUNCTION__); -+ } -+ -+ /* Result storage space should be the same size as the prime as this -+ value can take up the same amount of storage space */ -+ if (dh_prime_len_bits != -+ krp->krp_param[ICP_DH_KRP_PARAM_RESULT_INDEX].crp_nbits) { -+ DPRINTK("%s(): Return Buffer must be the same size " -+ "as the Prime buffer\n", __FUNCTION__); -+ krp->krp_status = EINVAL; -+ return EINVAL; -+ } -+ /* Switch to size in bytes */ -+ BITS_TO_BYTES(dh_prime_len_bytes, dh_prime_len_bits); -+ -+ callbackTag = krp; -+ -+/*All allocations are set to ICP_M_NOWAIT due to the possibility of getting -+called in interrupt context*/ -+ pPhase1OpData = icp_kmem_cache_zalloc(drvDH_zone, ICP_M_NOWAIT); -+ if (NULL == pPhase1OpData) { -+ APRINTK("%s():Failed to get memory for key gen data\n", -+ __FUNCTION__); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ pLocalOctetStringPV = -+ icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); -+ if (NULL == pLocalOctetStringPV) { -+ APRINTK("%s():Failed to get memory for pLocalOctetStringPV\n", -+ __FUNCTION__); -+ ICP_CACHE_FREE(drvDH_zone, pPhase1OpData); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ /* Link parameters */ -+ pPhase1OpData->primeP.pData = -+ krp->krp_param[ICP_DH_KRP_PARAM_PRIME_INDEX].crp_p; -+ -+ pPhase1OpData->primeP.dataLenInBytes = dh_prime_len_bytes; -+ -+ icp_ocfDrvSwapBytes(pPhase1OpData->primeP.pData, dh_prime_len_bytes); -+ -+ pPhase1OpData->baseG.pData = -+ krp->krp_param[ICP_DH_KRP_PARAM_BASE_INDEX].crp_p; -+ -+ BITS_TO_BYTES(pPhase1OpData->baseG.dataLenInBytes, -+ krp->krp_param[ICP_DH_KRP_PARAM_BASE_INDEX].crp_nbits); -+ -+ icp_ocfDrvSwapBytes(pPhase1OpData->baseG.pData, -+ pPhase1OpData->baseG.dataLenInBytes); -+ -+ pPhase1OpData->privateValueX.pData = -+ krp->krp_param[ICP_DH_KRP_PARAM_PRIVATE_VALUE_INDEX].crp_p; -+ -+ BITS_TO_BYTES(pPhase1OpData->privateValueX.dataLenInBytes, -+ krp->krp_param[ICP_DH_KRP_PARAM_PRIVATE_VALUE_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(pPhase1OpData->privateValueX.pData, -+ pPhase1OpData->privateValueX.dataLenInBytes); -+ -+ /* Output parameters */ -+ pLocalOctetStringPV->pData = -+ krp->krp_param[ICP_DH_KRP_PARAM_RESULT_INDEX].crp_p; -+ -+ BITS_TO_BYTES(pLocalOctetStringPV->dataLenInBytes, -+ krp->krp_param[ICP_DH_KRP_PARAM_RESULT_INDEX].crp_nbits); -+ -+ lacStatus = cpaCyDhKeyGenPhase1(CPA_INSTANCE_HANDLE_SINGLE, -+ icp_ocfDrvDhP1CallBack, -+ callbackTag, pPhase1OpData, -+ pLocalOctetStringPV); -+ -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): DH Phase 1 Key Gen failed (%d).\n", -+ __FUNCTION__, lacStatus); -+ icp_ocfDrvFreeFlatBuffer(pLocalOctetStringPV); -+ ICP_CACHE_FREE(drvDH_zone, pPhase1OpData); -+ } -+ -+ return lacStatus; -+} -+ -+/* Name : icp_ocfDrvModExp -+ * -+ * Description : This function will map ordinary Modular Exponentiation calls -+ * from OCF to the LAC API. -+ * -+ */ -+static int icp_ocfDrvModExp(struct cryptkop *krp) -+{ -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ void *callbackTag = NULL; -+ CpaCyLnModExpOpData *pModExpOpData = NULL; -+ CpaFlatBuffer *pResult = NULL; -+ -+ if ((krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX].crp_nbits % -+ NUM_BITS_IN_BYTE) != 0) { -+ DPRINTK("%s(): Warning - modulus buffer size (%d) is not a " -+ "multiple of 8 bits\n", __FUNCTION__, -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX]. -+ crp_nbits); -+ } -+ -+ /* Result storage space should be the same size as the prime as this -+ value can take up the same amount of storage space */ -+ if (krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX].crp_nbits > -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_RESULT_INDEX].crp_nbits) { -+ APRINTK("%s(): Return Buffer size must be the same or" -+ " greater than the Modulus buffer\n", __FUNCTION__); -+ krp->krp_status = EINVAL; -+ return EINVAL; -+ } -+ -+ callbackTag = krp; -+ -+ pModExpOpData = icp_kmem_cache_zalloc(drvLnModExp_zone, ICP_M_NOWAIT); -+ if (NULL == pModExpOpData) { -+ APRINTK("%s():Failed to get memory for key gen data\n", -+ __FUNCTION__); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ pResult = icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); -+ if (NULL == pResult) { -+ APRINTK("%s():Failed to get memory for ModExp result\n", -+ __FUNCTION__); -+ ICP_CACHE_FREE(drvLnModExp_zone, pModExpOpData); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ /* Link parameters */ -+ pModExpOpData->modulus.pData = -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX].crp_p; -+ BITS_TO_BYTES(pModExpOpData->modulus.dataLenInBytes, -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(pModExpOpData->modulus.pData, -+ pModExpOpData->modulus.dataLenInBytes); -+ -+ DPRINTK("%s : base (%d)\n", __FUNCTION__, krp-> -+ krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX].crp_nbits); -+ pModExpOpData->base.pData = -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX].crp_p; -+ BITS_TO_BYTES(pModExpOpData->base.dataLenInBytes, -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX]. -+ crp_nbits); -+ icp_ocfDrvSwapBytes(pModExpOpData->base.pData, -+ pModExpOpData->base.dataLenInBytes); -+ -+ pModExpOpData->exponent.pData = -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_EXPONENT_INDEX].crp_p; -+ BITS_TO_BYTES(pModExpOpData->exponent.dataLenInBytes, -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_EXPONENT_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(pModExpOpData->exponent.pData, -+ pModExpOpData->exponent.dataLenInBytes); -+ /* Output parameters */ -+ pResult->pData = -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_RESULT_INDEX].crp_p, -+ BITS_TO_BYTES(pResult->dataLenInBytes, -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_RESULT_INDEX]. -+ crp_nbits); -+ -+ lacStatus = cpaCyLnModExp(CPA_INSTANCE_HANDLE_SINGLE, -+ icp_ocfDrvModExpCallBack, -+ callbackTag, pModExpOpData, pResult); -+ -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): Mod Exp Operation failed (%d).\n", -+ __FUNCTION__, lacStatus); -+ krp->krp_status = ECANCELED; -+ icp_ocfDrvFreeFlatBuffer(pResult); -+ ICP_CACHE_FREE(drvLnModExp_zone, pModExpOpData); -+ } -+ -+ return lacStatus; -+} -+ -+/* Name : icp_ocfDrvModExpCRT -+ * -+ * Description : This function will map ordinary Modular Exponentiation Chinese -+ * Remainder Theorem implementaion calls from OCF to the LAC API. -+ * -+ * Note : Mod Exp CRT for this driver is accelerated through LAC RSA type 2 -+ * decrypt operation. Therefore P and Q input values must always be prime -+ * numbers. Although basic primality checks are done in LAC, it is up to the -+ * user to do any correct prime number checking before passing the inputs. -+ */ -+static int icp_ocfDrvModExpCRT(struct cryptkop *krp) -+{ -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ CpaCyRsaDecryptOpData *rsaDecryptOpData = NULL; -+ void *callbackTag = NULL; -+ CpaFlatBuffer *pOutputData = NULL; -+ -+ /*Parameter input checks are all done by LAC, no need to repeat -+ them here. */ -+ callbackTag = krp; -+ -+ rsaDecryptOpData = -+ icp_kmem_cache_zalloc(drvRSADecrypt_zone, ICP_M_NOWAIT); -+ if (NULL == rsaDecryptOpData) { -+ APRINTK("%s():Failed to get memory" -+ " for MOD EXP CRT Op data struct\n", __FUNCTION__); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ rsaDecryptOpData->pRecipientPrivateKey -+ = icp_kmem_cache_zalloc(drvRSAPrivateKey_zone, ICP_M_NOWAIT); -+ if (NULL == rsaDecryptOpData->pRecipientPrivateKey) { -+ APRINTK("%s():Failed to get memory for MOD EXP CRT" -+ " private key values struct\n", __FUNCTION__); -+ ICP_CACHE_FREE(drvRSADecrypt_zone, rsaDecryptOpData); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ version = CPA_CY_RSA_VERSION_TWO_PRIME; -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRepType = CPA_CY_RSA_PRIVATE_KEY_REP_TYPE_2; -+ -+ pOutputData = icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); -+ if (NULL == pOutputData) { -+ APRINTK("%s():Failed to get memory" -+ " for MOD EXP CRT output data\n", __FUNCTION__); -+ ICP_CACHE_FREE(drvRSAPrivateKey_zone, -+ rsaDecryptOpData->pRecipientPrivateKey); -+ ICP_CACHE_FREE(drvRSADecrypt_zone, rsaDecryptOpData); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ version = CPA_CY_RSA_VERSION_TWO_PRIME; -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRepType = CPA_CY_RSA_PRIVATE_KEY_REP_TYPE_2; -+ -+ /* Link parameters */ -+ rsaDecryptOpData->inputData.pData = -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_I_INDEX].crp_p; -+ BITS_TO_BYTES(rsaDecryptOpData->inputData.dataLenInBytes, -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_I_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(rsaDecryptOpData->inputData.pData, -+ rsaDecryptOpData->inputData.dataLenInBytes); -+ -+ rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2.prime1P.pData = -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_P_INDEX].crp_p; -+ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2. -+ prime1P.dataLenInBytes, -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_P_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.prime1P.pData, -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.prime1P.dataLenInBytes); -+ -+ rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2.prime2Q.pData = -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_Q_INDEX].crp_p; -+ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2. -+ prime2Q.dataLenInBytes, -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_Q_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.prime2Q.pData, -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.prime2Q.dataLenInBytes); -+ -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.exponent1Dp.pData = -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DP_INDEX].crp_p; -+ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2. -+ exponent1Dp.dataLenInBytes, -+ krp-> -+ krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DP_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.exponent1Dp.pData, -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.exponent1Dp.dataLenInBytes); -+ -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.exponent2Dq.pData = -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DQ_INDEX].crp_p; -+ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.exponent2Dq.dataLenInBytes, -+ krp-> -+ krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DQ_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.exponent2Dq.pData, -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.exponent2Dq.dataLenInBytes); -+ -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.coefficientQInv.pData = -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_COEFF_QINV_INDEX].crp_p; -+ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.coefficientQInv.dataLenInBytes, -+ krp-> -+ krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_COEFF_QINV_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.coefficientQInv.pData, -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.coefficientQInv.dataLenInBytes); -+ -+ /* Output Parameter */ -+ pOutputData->pData = -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_RESULT_INDEX].crp_p; -+ BITS_TO_BYTES(pOutputData->dataLenInBytes, -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_RESULT_INDEX]. -+ crp_nbits); -+ -+ lacStatus = cpaCyRsaDecrypt(CPA_INSTANCE_HANDLE_SINGLE, -+ icp_ocfDrvModExpCRTCallBack, -+ callbackTag, rsaDecryptOpData, pOutputData); -+ -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): Mod Exp CRT Operation failed (%d).\n", -+ __FUNCTION__, lacStatus); -+ krp->krp_status = ECANCELED; -+ icp_ocfDrvFreeFlatBuffer(pOutputData); -+ ICP_CACHE_FREE(drvRSAPrivateKey_zone, -+ rsaDecryptOpData->pRecipientPrivateKey); -+ ICP_CACHE_FREE(drvRSADecrypt_zone, rsaDecryptOpData); -+ } -+ -+ return lacStatus; -+} -+ -+/* Name : icp_ocfDrvCheckALessThanB -+ * -+ * Description : This function will check whether the first argument is less -+ * than the second. It is used to check whether the DSA RS sign Random K -+ * value is less than the Prime Q value (as defined in the specification) -+ * -+ */ -+static int -+icp_ocfDrvCheckALessThanB(CpaFlatBuffer * pK, CpaFlatBuffer * pQ, int *doCheck) -+{ -+ -+ uint8_t *MSB_K = pK->pData; -+ uint8_t *MSB_Q = pQ->pData; -+ uint32_t buffer_lengths_in_bytes = pQ->dataLenInBytes; -+ -+ if (DONT_RUN_LESS_THAN_CHECK == *doCheck) { -+ return FAIL_A_IS_GREATER_THAN_B; -+ } -+ -+/*Check MSBs -+if A == B, check next MSB -+if A > B, return A_IS_GREATER_THAN_B -+if A < B, return A_IS_LESS_THAN_B (success) -+*/ -+ while (*MSB_K == *MSB_Q) { -+ MSB_K++; -+ MSB_Q++; -+ -+ buffer_lengths_in_bytes--; -+ if (0 == buffer_lengths_in_bytes) { -+ DPRINTK("%s() Buffers have equal value!!\n", -+ __FUNCTION__); -+ return FAIL_A_IS_EQUAL_TO_B; -+ } -+ -+ } -+ -+ if (*MSB_K < *MSB_Q) { -+ return SUCCESS_A_IS_LESS_THAN_B; -+ } else { -+ return FAIL_A_IS_GREATER_THAN_B; -+ } -+ -+} -+ -+/* Name : icp_ocfDrvDsaSign -+ * -+ * Description : This function will map DSA RS Sign from OCF to the LAC API. -+ * -+ * NOTE: From looking at OCF patch to OpenSSL and even the number of input -+ * parameters, OCF expects us to generate the random seed value. This value -+ * is generated and passed to LAC, however the number is discared in the -+ * callback and not returned to the user. -+ */ -+static int icp_ocfDrvDsaSign(struct cryptkop *krp) -+{ -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ CpaCyDsaRSSignOpData *dsaRsSignOpData = NULL; -+ void *callbackTag = NULL; -+ CpaCyRandGenOpData randGenOpData; -+ int primeQSizeInBytes = 0; -+ int doCheck = 0; -+ CpaFlatBuffer randData; -+ CpaBoolean protocolStatus = CPA_FALSE; -+ CpaFlatBuffer *pR = NULL; -+ CpaFlatBuffer *pS = NULL; -+ -+ callbackTag = krp; -+ -+ BITS_TO_BYTES(primeQSizeInBytes, -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_Q_INDEX]. -+ crp_nbits); -+ -+ if (DSA_RS_SIGN_PRIMEQ_SIZE_IN_BYTES != primeQSizeInBytes) { -+ APRINTK("%s(): DSA PRIME Q size not equal to the " -+ "FIPS defined 20bytes, = %d\n", -+ __FUNCTION__, primeQSizeInBytes); -+ krp->krp_status = EDOM; -+ return EDOM; -+ } -+ -+ dsaRsSignOpData = -+ icp_kmem_cache_zalloc(drvDSARSSign_zone, ICP_M_NOWAIT); -+ if (NULL == dsaRsSignOpData) { -+ APRINTK("%s():Failed to get memory" -+ " for DSA RS Sign Op data struct\n", __FUNCTION__); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ dsaRsSignOpData->K.pData = -+ icp_kmem_cache_alloc(drvDSARSSignKValue_zone, ICP_M_NOWAIT); -+ -+ if (NULL == dsaRsSignOpData->K.pData) { -+ APRINTK("%s():Failed to get memory" -+ " for DSA RS Sign Op Random value\n", __FUNCTION__); -+ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ pR = icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); -+ if (NULL == pR) { -+ APRINTK("%s():Failed to get memory" -+ " for DSA signature R\n", __FUNCTION__); -+ ICP_CACHE_FREE(drvDSARSSignKValue_zone, -+ dsaRsSignOpData->K.pData); -+ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ pS = icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); -+ if (NULL == pS) { -+ APRINTK("%s():Failed to get memory" -+ " for DSA signature S\n", __FUNCTION__); -+ icp_ocfDrvFreeFlatBuffer(pR); -+ ICP_CACHE_FREE(drvDSARSSignKValue_zone, -+ dsaRsSignOpData->K.pData); -+ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ /*link prime number parameter for ease of processing */ -+ dsaRsSignOpData->P.pData = -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_P_INDEX].crp_p; -+ BITS_TO_BYTES(dsaRsSignOpData->P.dataLenInBytes, -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_P_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(dsaRsSignOpData->P.pData, -+ dsaRsSignOpData->P.dataLenInBytes); -+ -+ dsaRsSignOpData->Q.pData = -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_Q_INDEX].crp_p; -+ BITS_TO_BYTES(dsaRsSignOpData->Q.dataLenInBytes, -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_Q_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(dsaRsSignOpData->Q.pData, -+ dsaRsSignOpData->Q.dataLenInBytes); -+ -+ /*generate random number with equal buffer size to Prime value Q, -+ but value less than Q */ -+ dsaRsSignOpData->K.dataLenInBytes = dsaRsSignOpData->Q.dataLenInBytes; -+ -+ randGenOpData.generateBits = CPA_TRUE; -+ randGenOpData.lenInBytes = dsaRsSignOpData->K.dataLenInBytes; -+ -+ icp_ocfDrvPtrAndLenToFlatBuffer(dsaRsSignOpData->K.pData, -+ dsaRsSignOpData->K.dataLenInBytes, -+ &randData); -+ -+ doCheck = 0; -+ while (icp_ocfDrvCheckALessThanB(&(dsaRsSignOpData->K), -+ &(dsaRsSignOpData->Q), &doCheck)) { -+ -+ if (CPA_STATUS_SUCCESS -+ != cpaCyRandGen(CPA_INSTANCE_HANDLE_SINGLE, -+ NULL, NULL, &randGenOpData, &randData)) { -+ APRINTK("%s(): ERROR - Failed to generate DSA RS Sign K" -+ "value\n", __FUNCTION__); -+ icp_ocfDrvFreeFlatBuffer(pS); -+ icp_ocfDrvFreeFlatBuffer(pR); -+ ICP_CACHE_FREE(drvDSARSSignKValue_zone, -+ dsaRsSignOpData->K.pData); -+ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); -+ krp->krp_status = EAGAIN; -+ return EAGAIN; -+ } -+ -+ doCheck++; -+ if (DSA_SIGN_RAND_GEN_VAL_CHECK_MAX_ITERATIONS == doCheck) { -+ APRINTK("%s(): ERROR - Failed to find DSA RS Sign K " -+ "value less than Q value\n", __FUNCTION__); -+ icp_ocfDrvFreeFlatBuffer(pS); -+ icp_ocfDrvFreeFlatBuffer(pR); -+ ICP_CACHE_FREE(drvDSARSSignKValue_zone, -+ dsaRsSignOpData->K.pData); -+ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); -+ krp->krp_status = EAGAIN; -+ return EAGAIN; -+ } -+ -+ } -+ /*Rand Data - no need to swap bytes for pK */ -+ -+ /* Link parameters */ -+ dsaRsSignOpData->G.pData = -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_G_INDEX].crp_p; -+ BITS_TO_BYTES(dsaRsSignOpData->G.dataLenInBytes, -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_G_INDEX].crp_nbits); -+ -+ icp_ocfDrvSwapBytes(dsaRsSignOpData->G.pData, -+ dsaRsSignOpData->G.dataLenInBytes); -+ -+ dsaRsSignOpData->X.pData = -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_X_INDEX].crp_p; -+ BITS_TO_BYTES(dsaRsSignOpData->X.dataLenInBytes, -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_X_INDEX].crp_nbits); -+ icp_ocfDrvSwapBytes(dsaRsSignOpData->X.pData, -+ dsaRsSignOpData->X.dataLenInBytes); -+ -+ /*OpenSSL dgst parameter is left in big endian byte order, -+ therefore no byte swap is required */ -+ dsaRsSignOpData->M.pData = -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_DGST_INDEX].crp_p; -+ BITS_TO_BYTES(dsaRsSignOpData->M.dataLenInBytes, -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_DGST_INDEX]. -+ crp_nbits); -+ -+ /* Output Parameters */ -+ pS->pData = krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_S_RESULT_INDEX].crp_p; -+ BITS_TO_BYTES(pS->dataLenInBytes, -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_S_RESULT_INDEX]. -+ crp_nbits); -+ -+ pR->pData = krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_R_RESULT_INDEX].crp_p; -+ BITS_TO_BYTES(pR->dataLenInBytes, -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_R_RESULT_INDEX]. -+ crp_nbits); -+ -+ lacStatus = cpaCyDsaSignRS(CPA_INSTANCE_HANDLE_SINGLE, -+ icp_ocfDrvDsaRSSignCallBack, -+ callbackTag, dsaRsSignOpData, -+ &protocolStatus, pR, pS); -+ -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): DSA RS Sign Operation failed (%d).\n", -+ __FUNCTION__, lacStatus); -+ krp->krp_status = ECANCELED; -+ icp_ocfDrvFreeFlatBuffer(pS); -+ icp_ocfDrvFreeFlatBuffer(pR); -+ ICP_CACHE_FREE(drvDSARSSignKValue_zone, -+ dsaRsSignOpData->K.pData); -+ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); -+ } -+ -+ return lacStatus; -+} -+ -+/* Name : icp_ocfDrvDsaVerify -+ * -+ * Description : This function will map DSA RS Verify from OCF to the LAC API. -+ * -+ */ -+static int icp_ocfDrvDsaVerify(struct cryptkop *krp) -+{ -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ CpaCyDsaVerifyOpData *dsaVerifyOpData = NULL; -+ void *callbackTag = NULL; -+ CpaBoolean verifyStatus = CPA_FALSE; -+ -+ callbackTag = krp; -+ -+ dsaVerifyOpData = -+ icp_kmem_cache_zalloc(drvDSAVerify_zone, ICP_M_NOWAIT); -+ if (NULL == dsaVerifyOpData) { -+ APRINTK("%s():Failed to get memory" -+ " for DSA Verify Op data struct\n", __FUNCTION__); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ /* Link parameters */ -+ dsaVerifyOpData->P.pData = -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PRIME_P_INDEX].crp_p; -+ BITS_TO_BYTES(dsaVerifyOpData->P.dataLenInBytes, -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PRIME_P_INDEX]. -+ crp_nbits); -+ icp_ocfDrvSwapBytes(dsaVerifyOpData->P.pData, -+ dsaVerifyOpData->P.dataLenInBytes); -+ -+ dsaVerifyOpData->Q.pData = -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PRIME_Q_INDEX].crp_p; -+ BITS_TO_BYTES(dsaVerifyOpData->Q.dataLenInBytes, -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PRIME_Q_INDEX]. -+ crp_nbits); -+ icp_ocfDrvSwapBytes(dsaVerifyOpData->Q.pData, -+ dsaVerifyOpData->Q.dataLenInBytes); -+ -+ dsaVerifyOpData->G.pData = -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_G_INDEX].crp_p; -+ BITS_TO_BYTES(dsaVerifyOpData->G.dataLenInBytes, -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_G_INDEX]. -+ crp_nbits); -+ icp_ocfDrvSwapBytes(dsaVerifyOpData->G.pData, -+ dsaVerifyOpData->G.dataLenInBytes); -+ -+ dsaVerifyOpData->Y.pData = -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PUBKEY_INDEX].crp_p; -+ BITS_TO_BYTES(dsaVerifyOpData->Y.dataLenInBytes, -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PUBKEY_INDEX]. -+ crp_nbits); -+ icp_ocfDrvSwapBytes(dsaVerifyOpData->Y.pData, -+ dsaVerifyOpData->Y.dataLenInBytes); -+ -+ /*OpenSSL dgst parameter is left in big endian byte order, -+ therefore no byte swap is required */ -+ dsaVerifyOpData->M.pData = -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_DGST_INDEX].crp_p; -+ BITS_TO_BYTES(dsaVerifyOpData->M.dataLenInBytes, -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_DGST_INDEX]. -+ crp_nbits); -+ -+ dsaVerifyOpData->R.pData = -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_SIG_R_INDEX].crp_p; -+ BITS_TO_BYTES(dsaVerifyOpData->R.dataLenInBytes, -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_SIG_R_INDEX]. -+ crp_nbits); -+ icp_ocfDrvSwapBytes(dsaVerifyOpData->R.pData, -+ dsaVerifyOpData->R.dataLenInBytes); -+ -+ dsaVerifyOpData->S.pData = -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_SIG_S_INDEX].crp_p; -+ BITS_TO_BYTES(dsaVerifyOpData->S.dataLenInBytes, -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_SIG_S_INDEX]. -+ crp_nbits); -+ icp_ocfDrvSwapBytes(dsaVerifyOpData->S.pData, -+ dsaVerifyOpData->S.dataLenInBytes); -+ -+ lacStatus = cpaCyDsaVerify(CPA_INSTANCE_HANDLE_SINGLE, -+ icp_ocfDrvDsaVerifyCallBack, -+ callbackTag, dsaVerifyOpData, &verifyStatus); -+ -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): DSA Verify Operation failed (%d).\n", -+ __FUNCTION__, lacStatus); -+ ICP_CACHE_FREE(drvDSAVerify_zone, dsaVerifyOpData); -+ krp->krp_status = ECANCELED; -+ } -+ -+ return lacStatus; -+} -+ -+/* Name : icp_ocfDrvDhP1Callback -+ * -+ * Description : When this function returns it signifies that the LAC -+ * component has completed the DH operation. -+ */ -+static void -+icp_ocfDrvDhP1CallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, CpaFlatBuffer * pLocalOctetStringPV) -+{ -+ struct cryptkop *krp = NULL; -+ CpaCyDhPhase1KeyGenOpData *pPhase1OpData = NULL; -+ -+ if (NULL == callbackTag) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "callbackTag data is NULL\n", __FUNCTION__); -+ return; -+ } -+ krp = (struct cryptkop *)callbackTag; -+ -+ if (NULL == pOpData) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "Operation Data is NULL\n", __FUNCTION__); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ pPhase1OpData = (CpaCyDhPhase1KeyGenOpData *) pOpData; -+ -+ if (NULL == pLocalOctetStringPV) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "pLocalOctetStringPV Data is NULL\n", __FUNCTION__); -+ memset(pPhase1OpData, 0, sizeof(CpaCyDhPhase1KeyGenOpData)); -+ ICP_CACHE_FREE(drvDH_zone, pPhase1OpData); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ -+ if (CPA_STATUS_SUCCESS == status) { -+ krp->krp_status = CRYPTO_OP_SUCCESS; -+ } else { -+ APRINTK("%s(): Diffie Hellman Phase1 Key Gen failed - " -+ "Operation Status = %d\n", __FUNCTION__, status); -+ krp->krp_status = ECANCELED; -+ } -+ -+ icp_ocfDrvSwapBytes(pLocalOctetStringPV->pData, -+ pLocalOctetStringPV->dataLenInBytes); -+ -+ icp_ocfDrvFreeFlatBuffer(pLocalOctetStringPV); -+ memset(pPhase1OpData, 0, sizeof(CpaCyDhPhase1KeyGenOpData)); -+ ICP_CACHE_FREE(drvDH_zone, pPhase1OpData); -+ -+ crypto_kdone(krp); -+ -+ return; -+} -+ -+/* Name : icp_ocfDrvModExpCallBack -+ * -+ * Description : When this function returns it signifies that the LAC -+ * component has completed the Mod Exp operation. -+ */ -+static void -+icp_ocfDrvModExpCallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpdata, CpaFlatBuffer * pResult) -+{ -+ struct cryptkop *krp = NULL; -+ CpaCyLnModExpOpData *pLnModExpOpData = NULL; -+ -+ if (NULL == callbackTag) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "callbackTag data is NULL\n", __FUNCTION__); -+ return; -+ } -+ krp = (struct cryptkop *)callbackTag; -+ -+ if (NULL == pOpdata) { -+ DPRINTK("%s(): Invalid Mod Exp input parameters - " -+ "Operation Data is NULL\n", __FUNCTION__); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ pLnModExpOpData = (CpaCyLnModExpOpData *) pOpdata; -+ -+ if (NULL == pResult) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "pResult data is NULL\n", __FUNCTION__); -+ krp->krp_status = ECANCELED; -+ memset(pLnModExpOpData, 0, sizeof(CpaCyLnModExpOpData)); -+ ICP_CACHE_FREE(drvLnModExp_zone, pLnModExpOpData); -+ crypto_kdone(krp); -+ return; -+ } -+ -+ if (CPA_STATUS_SUCCESS == status) { -+ krp->krp_status = CRYPTO_OP_SUCCESS; -+ } else { -+ APRINTK("%s(): LAC Mod Exp Operation failed - " -+ "Operation Status = %d\n", __FUNCTION__, status); -+ krp->krp_status = ECANCELED; -+ } -+ -+ icp_ocfDrvSwapBytes(pResult->pData, pResult->dataLenInBytes); -+ -+ /*switch base size value back to original */ -+ if (pLnModExpOpData->base.pData == -+ (uint8_t *) & (krp-> -+ krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX]. -+ crp_nbits)) { -+ *((uint32_t *) pLnModExpOpData->base.pData) = -+ ntohl(*((uint32_t *) pLnModExpOpData->base.pData)); -+ } -+ icp_ocfDrvFreeFlatBuffer(pResult); -+ memset(pLnModExpOpData, 0, sizeof(CpaCyLnModExpOpData)); -+ ICP_CACHE_FREE(drvLnModExp_zone, pLnModExpOpData); -+ -+ crypto_kdone(krp); -+ -+ return; -+ -+} -+ -+/* Name : icp_ocfDrvModExpCRTCallBack -+ * -+ * Description : When this function returns it signifies that the LAC -+ * component has completed the Mod Exp CRT operation. -+ */ -+static void -+icp_ocfDrvModExpCRTCallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, CpaFlatBuffer * pOutputData) -+{ -+ struct cryptkop *krp = NULL; -+ CpaCyRsaDecryptOpData *pDecryptData = NULL; -+ -+ if (NULL == callbackTag) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "callbackTag data is NULL\n", __FUNCTION__); -+ return; -+ } -+ -+ krp = (struct cryptkop *)callbackTag; -+ -+ if (NULL == pOpData) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "Operation Data is NULL\n", __FUNCTION__); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ pDecryptData = (CpaCyRsaDecryptOpData *) pOpData; -+ -+ if (NULL == pOutputData) { -+ DPRINTK("%s(): Invalid input parameter - " -+ "pOutputData is NULL\n", __FUNCTION__); -+ memset(pDecryptData->pRecipientPrivateKey, 0, -+ sizeof(CpaCyRsaPrivateKey)); -+ ICP_CACHE_FREE(drvRSAPrivateKey_zone, -+ pDecryptData->pRecipientPrivateKey); -+ memset(pDecryptData, 0, sizeof(CpaCyRsaDecryptOpData)); -+ ICP_CACHE_FREE(drvRSADecrypt_zone, pDecryptData); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ -+ if (CPA_STATUS_SUCCESS == status) { -+ krp->krp_status = CRYPTO_OP_SUCCESS; -+ } else { -+ APRINTK("%s(): LAC Mod Exp CRT operation failed - " -+ "Operation Status = %d\n", __FUNCTION__, status); -+ krp->krp_status = ECANCELED; -+ } -+ -+ icp_ocfDrvSwapBytes(pOutputData->pData, pOutputData->dataLenInBytes); -+ -+ icp_ocfDrvFreeFlatBuffer(pOutputData); -+ memset(pDecryptData->pRecipientPrivateKey, 0, -+ sizeof(CpaCyRsaPrivateKey)); -+ ICP_CACHE_FREE(drvRSAPrivateKey_zone, -+ pDecryptData->pRecipientPrivateKey); -+ memset(pDecryptData, 0, sizeof(CpaCyRsaDecryptOpData)); -+ ICP_CACHE_FREE(drvRSADecrypt_zone, pDecryptData); -+ -+ crypto_kdone(krp); -+ -+ return; -+} -+ -+/* Name : icp_ocfDrvDsaRSSignCallBack -+ * -+ * Description : When this function returns it signifies that the LAC -+ * component has completed the DSA RS sign operation. -+ */ -+static void -+icp_ocfDrvDsaRSSignCallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, -+ CpaBoolean protocolStatus, -+ CpaFlatBuffer * pR, CpaFlatBuffer * pS) -+{ -+ struct cryptkop *krp = NULL; -+ CpaCyDsaRSSignOpData *pSignData = NULL; -+ -+ if (NULL == callbackTag) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "callbackTag data is NULL\n", __FUNCTION__); -+ return; -+ } -+ -+ krp = (struct cryptkop *)callbackTag; -+ -+ if (NULL == pOpData) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "Operation Data is NULL\n", __FUNCTION__); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ pSignData = (CpaCyDsaRSSignOpData *) pOpData; -+ -+ if (NULL == pR) { -+ DPRINTK("%s(): Invalid input parameter - " -+ "pR sign is NULL\n", __FUNCTION__); -+ icp_ocfDrvFreeFlatBuffer(pS); -+ ICP_CACHE_FREE(drvDSARSSign_zone, pSignData); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ -+ if (NULL == pS) { -+ DPRINTK("%s(): Invalid input parameter - " -+ "pS sign is NULL\n", __FUNCTION__); -+ icp_ocfDrvFreeFlatBuffer(pR); -+ ICP_CACHE_FREE(drvDSARSSign_zone, pSignData); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ -+ if (CPA_STATUS_SUCCESS != status) { -+ APRINTK("%s(): LAC DSA RS Sign operation failed - " -+ "Operation Status = %d\n", __FUNCTION__, status); -+ krp->krp_status = ECANCELED; -+ } else { -+ krp->krp_status = CRYPTO_OP_SUCCESS; -+ -+ if (CPA_TRUE != protocolStatus) { -+ DPRINTK("%s(): LAC DSA RS Sign operation failed due " -+ "to protocol error\n", __FUNCTION__); -+ krp->krp_status = EIO; -+ } -+ } -+ -+ /* Swap bytes only when the callback status is successful and -+ protocolStatus is set to true */ -+ if (CPA_STATUS_SUCCESS == status && CPA_TRUE == protocolStatus) { -+ icp_ocfDrvSwapBytes(pR->pData, pR->dataLenInBytes); -+ icp_ocfDrvSwapBytes(pS->pData, pS->dataLenInBytes); -+ } -+ -+ icp_ocfDrvFreeFlatBuffer(pR); -+ icp_ocfDrvFreeFlatBuffer(pS); -+ memset(pSignData->K.pData, 0, pSignData->K.dataLenInBytes); -+ ICP_CACHE_FREE(drvDSARSSignKValue_zone, pSignData->K.pData); -+ memset(pSignData, 0, sizeof(CpaCyDsaRSSignOpData)); -+ ICP_CACHE_FREE(drvDSARSSign_zone, pSignData); -+ crypto_kdone(krp); -+ -+ return; -+} -+ -+/* Name : icp_ocfDrvDsaVerifyCallback -+ * -+ * Description : When this function returns it signifies that the LAC -+ * component has completed the DSA Verify operation. -+ */ -+static void -+icp_ocfDrvDsaVerifyCallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, CpaBoolean verifyStatus) -+{ -+ -+ struct cryptkop *krp = NULL; -+ CpaCyDsaVerifyOpData *pVerData = NULL; -+ -+ if (NULL == callbackTag) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "callbackTag data is NULL\n", __FUNCTION__); -+ return; -+ } -+ -+ krp = (struct cryptkop *)callbackTag; -+ -+ if (NULL == pOpData) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "Operation Data is NULL\n", __FUNCTION__); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ pVerData = (CpaCyDsaVerifyOpData *) pOpData; -+ -+ if (CPA_STATUS_SUCCESS != status) { -+ APRINTK("%s(): LAC DSA Verify operation failed - " -+ "Operation Status = %d\n", __FUNCTION__, status); -+ krp->krp_status = ECANCELED; -+ } else { -+ krp->krp_status = CRYPTO_OP_SUCCESS; -+ -+ if (CPA_TRUE != verifyStatus) { -+ DPRINTK("%s(): DSA signature invalid\n", __FUNCTION__); -+ krp->krp_status = EIO; -+ } -+ } -+ -+ /* Swap bytes only when the callback status is successful and -+ verifyStatus is set to true */ -+ /*Just swapping back the key values for now. Possibly all -+ swapped buffers need to be reverted */ -+ if (CPA_STATUS_SUCCESS == status && CPA_TRUE == verifyStatus) { -+ icp_ocfDrvSwapBytes(pVerData->R.pData, -+ pVerData->R.dataLenInBytes); -+ icp_ocfDrvSwapBytes(pVerData->S.pData, -+ pVerData->S.dataLenInBytes); -+ } -+ -+ memset(pVerData, 0, sizeof(CpaCyDsaVerifyOpData)); -+ ICP_CACHE_FREE(drvDSAVerify_zone, pVerData); -+ crypto_kdone(krp); -+ -+ return; -+} -diff -Nur linux-2.6.36.orig/crypto/ocf/ep80579/icp_common.c linux-2.6.36/crypto/ocf/ep80579/icp_common.c ---- linux-2.6.36.orig/crypto/ocf/ep80579/icp_common.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/ep80579/icp_common.c 2010-11-09 20:28:04.612495446 +0100 -@@ -0,0 +1,773 @@ -+/************************************************************************* -+ * -+ * This file is provided under a dual BSD/GPLv2 license. When using or -+ * redistributing this file, you may do so under either license. -+ * -+ * GPL LICENSE SUMMARY -+ * -+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of version 2 of the GNU General Public License as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. -+ * The full GNU General Public License is included in this distribution -+ * in the file called LICENSE.GPL. -+ * -+ * Contact Information: -+ * Intel Corporation -+ * -+ * BSD LICENSE -+ * -+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * * Neither the name of Intel Corporation nor the names of its -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * -+ * version: Security.L.1.0.2-229 -+ * -+ ***************************************************************************/ -+ -+/* -+ * An OCF module that uses Intel® QuickAssist Integrated Accelerator to do the -+ * crypto. -+ * -+ * This driver requires the ICP Access Library that is available from Intel in -+ * order to operate. -+ */ -+ -+#include "icp_ocf.h" -+ -+#define ICP_OCF_COMP_NAME "ICP_OCF" -+#define ICP_OCF_VER_MAIN (2) -+#define ICP_OCF_VER_MJR (1) -+#define ICP_OCF_VER_MNR (0) -+ -+#define MAX_DEREG_RETRIES (100) -+#define DEFAULT_DEREG_RETRIES (10) -+#define DEFAULT_DEREG_DELAY_IN_JIFFIES (10) -+ -+/* This defines the maximum number of sessions possible between OCF -+ and the OCF EP80579 Driver. If set to zero, there is no limit. */ -+#define DEFAULT_OCF_TO_DRV_MAX_SESSION_COUNT (0) -+#define NUM_SUPPORTED_CAPABILITIES (21) -+ -+/*Slab zone names*/ -+#define ICP_SESSION_DATA_NAME "icp_ocf.SesDat" -+#define ICP_OP_DATA_NAME "icp_ocf.OpDat" -+#define ICP_DH_NAME "icp_ocf.DH" -+#define ICP_MODEXP_NAME "icp_ocf.ModExp" -+#define ICP_RSA_DECRYPT_NAME "icp_ocf.RSAdec" -+#define ICP_RSA_PKEY_NAME "icp_ocf.RSApk" -+#define ICP_DSA_SIGN_NAME "icp_ocf.DSAsg" -+#define ICP_DSA_VER_NAME "icp_ocf.DSAver" -+#define ICP_RAND_VAL_NAME "icp_ocf.DSArnd" -+#define ICP_FLAT_BUFF_NAME "icp_ocf.FB" -+ -+/*Slabs zones*/ -+icp_kmem_cache drvSessionData_zone = NULL; -+icp_kmem_cache drvOpData_zone = NULL; -+icp_kmem_cache drvDH_zone = NULL; -+icp_kmem_cache drvLnModExp_zone = NULL; -+icp_kmem_cache drvRSADecrypt_zone = NULL; -+icp_kmem_cache drvRSAPrivateKey_zone = NULL; -+icp_kmem_cache drvDSARSSign_zone = NULL; -+icp_kmem_cache drvDSARSSignKValue_zone = NULL; -+icp_kmem_cache drvDSAVerify_zone = NULL; -+ -+/*Slab zones for flatbuffers and bufferlist*/ -+icp_kmem_cache drvFlatBuffer_zone = NULL; -+ -+static inline int icp_cache_null_check(void) -+{ -+ return (drvSessionData_zone && drvOpData_zone -+ && drvDH_zone && drvLnModExp_zone && drvRSADecrypt_zone -+ && drvRSAPrivateKey_zone && drvDSARSSign_zone -+ && drvDSARSSign_zone && drvDSARSSignKValue_zone -+ && drvDSAVerify_zone && drvFlatBuffer_zone); -+} -+ -+/*Function to free all allocated slab caches before exiting the module*/ -+static void icp_ocfDrvFreeCaches(void); -+ -+int32_t icp_ocfDrvDriverId = INVALID_DRIVER_ID; -+ -+/* Module parameter - gives the number of times LAC deregistration shall be -+ re-tried */ -+int num_dereg_retries = DEFAULT_DEREG_RETRIES; -+ -+/* Module parameter - gives the delay time in jiffies before a LAC session -+ shall be attempted to be deregistered again */ -+int dereg_retry_delay_in_jiffies = DEFAULT_DEREG_DELAY_IN_JIFFIES; -+ -+/* Module parameter - gives the maximum number of sessions possible between -+ OCF and the OCF EP80579 Driver. If set to zero, there is no limit.*/ -+int max_sessions = DEFAULT_OCF_TO_DRV_MAX_SESSION_COUNT; -+ -+/* This is set when the module is removed from the system, no further -+ processing can take place if this is set */ -+icp_atomic_t icp_ocfDrvIsExiting = ICP_ATOMIC_INIT(0); -+ -+/* This is used to show how many lac sessions were not deregistered*/ -+icp_atomic_t lac_session_failed_dereg_count = ICP_ATOMIC_INIT(0); -+ -+/* This is used to track the number of registered sessions between OCF and -+ * and the OCF EP80579 driver, when max_session is set to value other than -+ * zero. This ensures that the max_session set for the OCF and the driver -+ * is equal to the LAC registered sessions */ -+icp_atomic_t num_ocf_to_drv_registered_sessions = ICP_ATOMIC_INIT(0); -+ -+/* Head of linked list used to store session data */ -+icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead; -+icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead_FreeMemList; -+ -+icp_spinlock_t icp_ocfDrvSymSessInfoListSpinlock; -+ -+/*Below pointer is only used in linux, FreeBSD uses the name to -+create its own variable name*/ -+icp_workqueue *icp_ocfDrvFreeLacSessionWorkQ = NULL; -+ICP_WORKQUEUE_DEFINE_THREAD(icp_ocfDrvFreeLacSessionWorkQ); -+ -+struct icp_drvBuffListInfo defBuffListInfo; -+ -+/* Name : icp_ocfDrvInit -+ * -+ * Description : This function will register all the symmetric and asymmetric -+ * functionality that will be accelerated by the hardware. It will also -+ * get a unique driver ID from the OCF and initialise all slab caches -+ */ -+ICP_MODULE_INIT_FUNC(icp_ocfDrvInit) -+{ -+ int ocfStatus = 0; -+ -+ IPRINTK("=== %s ver %d.%d.%d ===\n", ICP_OCF_COMP_NAME, -+ ICP_OCF_VER_MAIN, ICP_OCF_VER_MJR, ICP_OCF_VER_MNR); -+ -+ if (MAX_DEREG_RETRIES < num_dereg_retries) { -+ EPRINTK("Session deregistration retry count set to greater " -+ "than %d", MAX_DEREG_RETRIES); -+ icp_module_return_code(EINVAL); -+ } -+ -+ /* Initialize and Start the Cryptographic component */ -+ if (CPA_STATUS_SUCCESS != -+ cpaCyStartInstance(CPA_INSTANCE_HANDLE_SINGLE)) { -+ EPRINTK("Failed to initialize and start the instance " -+ "of the Cryptographic component.\n"); -+ return icp_module_return_code(EINVAL); -+ } -+ -+ icp_spin_lock_init(&icp_ocfDrvSymSessInfoListSpinlock); -+ -+ /* Set the default size of BufferList to allocate */ -+ memset(&defBuffListInfo, 0, sizeof(struct icp_drvBuffListInfo)); -+ if (ICP_OCF_DRV_STATUS_SUCCESS != -+ icp_ocfDrvBufferListMemInfo(ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS, -+ &defBuffListInfo)) { -+ EPRINTK("Failed to get bufferlist memory info.\n"); -+ return icp_module_return_code(ENOMEM); -+ } -+ -+ /*Register OCF EP80579 Driver with OCF */ -+ icp_ocfDrvDriverId = ICP_CRYPTO_GET_DRIVERID(); -+ -+ if (icp_ocfDrvDriverId < 0) { -+ EPRINTK("%s : ICP driver failed to register with OCF!\n", -+ __FUNCTION__); -+ return icp_module_return_code(ENODEV); -+ } -+ -+ /*Create all the slab caches used by the OCF EP80579 Driver */ -+ drvSessionData_zone = -+ ICP_CACHE_CREATE(ICP_SESSION_DATA_NAME, struct icp_drvSessionData); -+ -+ /* -+ * Allocation of the OpData includes the allocation space for meta data. -+ * The memory after the opData structure is reserved for this meta data. -+ */ -+ drvOpData_zone = -+ icp_kmem_cache_create(ICP_OP_DATA_NAME, -+ sizeof(struct icp_drvOpData) + -+ defBuffListInfo.metaSize, -+ ICP_KERNEL_CACHE_ALIGN, -+ ICP_KERNEL_CACHE_NOINIT); -+ -+ drvDH_zone = ICP_CACHE_CREATE(ICP_DH_NAME, CpaCyDhPhase1KeyGenOpData); -+ -+ drvLnModExp_zone = -+ ICP_CACHE_CREATE(ICP_MODEXP_NAME, CpaCyLnModExpOpData); -+ -+ drvRSADecrypt_zone = -+ ICP_CACHE_CREATE(ICP_RSA_DECRYPT_NAME, CpaCyRsaDecryptOpData); -+ -+ drvRSAPrivateKey_zone = -+ ICP_CACHE_CREATE(ICP_RSA_PKEY_NAME, CpaCyRsaPrivateKey); -+ -+ drvDSARSSign_zone = -+ ICP_CACHE_CREATE(ICP_DSA_SIGN_NAME, CpaCyDsaRSSignOpData); -+ -+ /*too awkward to use a macro here */ -+ drvDSARSSignKValue_zone = -+ ICP_CACHE_CREATE(ICP_RAND_VAL_NAME, -+ DSA_RS_SIGN_PRIMEQ_SIZE_IN_BYTES); -+ -+ drvDSAVerify_zone = -+ ICP_CACHE_CREATE(ICP_DSA_VER_NAME, CpaCyDsaVerifyOpData); -+ -+ drvFlatBuffer_zone = -+ ICP_CACHE_CREATE(ICP_FLAT_BUFF_NAME, CpaFlatBuffer); -+ -+ if (0 == icp_cache_null_check()) { -+ icp_ocfDrvFreeCaches(); -+ EPRINTK("%s() line %d: Not enough memory!\n", -+ __FUNCTION__, __LINE__); -+ return ENOMEM; -+ } -+ -+ /* Register the ICP symmetric crypto support. */ -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_NULL_CBC, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_DES_CBC, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_3DES_CBC, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_AES_CBC, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_ARC4, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_MD5, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_MD5_HMAC, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA1, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA1_HMAC, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_256, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_256_HMAC, -+ ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_384, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_384_HMAC, -+ ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_512, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_512_HMAC, -+ ocfStatus); -+ -+ /* Register the ICP asymmetric algorithm support */ -+ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_DH_COMPUTE_KEY, -+ ocfStatus); -+ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_MOD_EXP, ocfStatus); -+ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_MOD_EXP_CRT, ocfStatus); -+ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_DSA_SIGN, ocfStatus); -+ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_DSA_VERIFY, ocfStatus); -+ -+ /* Register the ICP random number generator support */ -+ ICP_REG_RAND_WITH_OCF(icp_ocfDrvDriverId, -+ icp_ocfDrvReadRandom, NULL, ocfStatus); -+ -+ if (OCF_ZERO_FUNCTIONALITY_REGISTERED == ocfStatus) { -+ DPRINTK("%s: Failed to register any device capabilities\n", -+ __FUNCTION__); -+ icp_ocfDrvFreeCaches(); -+ icp_ocfDrvDriverId = INVALID_DRIVER_ID; -+ return icp_module_return_code(ECANCELED); -+ } -+ -+ DPRINTK("%s: Registered %d of %d device capabilities\n", -+ __FUNCTION__, ocfStatus, NUM_SUPPORTED_CAPABILITIES); -+ -+ /*Session data linked list used during module exit */ -+ ICP_INIT_LIST_HEAD(&icp_ocfDrvGlobalSymListHead); -+ ICP_INIT_LIST_HEAD(&icp_ocfDrvGlobalSymListHead_FreeMemList); -+ -+ ICP_WORKQUEUE_CREATE(icp_ocfDrvFreeLacSessionWorkQ, "icpwq"); -+ if (ICP_WORKQUEUE_NULL_CHECK(icp_ocfDrvFreeLacSessionWorkQ)) { -+ EPRINTK("%s: Failed to create single " -+ "thread workqueue\n", __FUNCTION__); -+ icp_ocfDrvFreeCaches(); -+ icp_ocfDrvDriverId = INVALID_DRIVER_ID; -+ return icp_module_return_code(ENOMEM); -+ } -+ -+ return icp_module_return_code(0); -+} -+ -+/* Name : icp_ocfDrvExit -+ * -+ * Description : This function will deregister all the symmetric sessions -+ * registered with the LAC component. It will also deregister all symmetric -+ * and asymmetric functionality that can be accelerated by the hardware via OCF -+ * and random number generation if it is enabled. -+ */ -+ICP_MODULE_EXIT_FUNC(icp_ocfDrvExit) -+{ -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ struct icp_drvSessionData *sessionData = NULL; -+ struct icp_drvSessionData *tempSessionData = NULL; -+ int i, remaining_delay_time_in_jiffies = 0; -+ -+ /* For FreeBSD the invariant macro below makes function to return */ -+ /* with EBUSY value in the case of any session which has been regi- */ -+ /* stered with LAC not being deregistered. */ -+ /* The Linux implementation is empty since it is purely to compensate */ -+ /* for a limitation of the FreeBSD 7.1 Opencrypto framework. */ -+ -+ ICP_MODULE_EXIT_INV(); -+ -+ /* There is a possibility of a process or new session command being */ -+ /* sent before this variable is incremented. The aim of this variable */ -+ /* is to stop a loop of calls creating a deadlock situation which */ -+ /* would prevent the driver from exiting. */ -+ icp_atomic_set(&icp_ocfDrvIsExiting, 1); -+ -+ /*Existing sessions will be routed to another driver after these calls */ -+ crypto_unregister_all(icp_ocfDrvDriverId); -+ crypto_runregister_all(icp_ocfDrvDriverId); -+ -+ if (ICP_WORKQUEUE_NULL_CHECK(icp_ocfDrvFreeLacSessionWorkQ)) { -+ DPRINTK("%s: workqueue already " -+ "destroyed, therefore module exit " -+ " function already called. Exiting.\n", __FUNCTION__); -+ return ICP_MODULE_EXIT_FUNC_RETURN_VAL; -+ } -+ /*If any sessions are waiting to be deregistered, do that. This also -+ flushes the work queue */ -+ ICP_WORKQUEUE_DESTROY(icp_ocfDrvFreeLacSessionWorkQ); -+ -+ /*ENTER CRITICAL SECTION */ -+ icp_spin_lockbh_lock(&icp_ocfDrvSymSessInfoListSpinlock); -+ -+ ICP_LIST_FOR_EACH_ENTRY_SAFE(tempSessionData, sessionData, -+ &icp_ocfDrvGlobalSymListHead, listNode) { -+ for (i = 0; i < num_dereg_retries; i++) { -+ /*No harm if bad input - LAC will handle error cases */ -+ if (ICP_SESSION_RUNNING == tempSessionData->inUse) { -+ lacStatus = -+ cpaCySymRemoveSession -+ (CPA_INSTANCE_HANDLE_SINGLE, -+ tempSessionData->sessHandle); -+ if (CPA_STATUS_SUCCESS == lacStatus) { -+ /* Succesfully deregistered */ -+ break; -+ } else if (CPA_STATUS_RETRY != lacStatus) { -+ icp_atomic_inc -+ (&lac_session_failed_dereg_count); -+ break; -+ } -+ -+ /*schedule_timout returns the time left for completion if -+ * this task is set to TASK_INTERRUPTIBLE */ -+ remaining_delay_time_in_jiffies = -+ dereg_retry_delay_in_jiffies; -+ while (0 > remaining_delay_time_in_jiffies) { -+ remaining_delay_time_in_jiffies = -+ icp_schedule_timeout -+ (&icp_ocfDrvSymSessInfoListSpinlock, -+ remaining_delay_time_in_jiffies); -+ } -+ -+ DPRINTK -+ ("%s(): Retry %d to deregistrate the session\n", -+ __FUNCTION__, i); -+ } -+ } -+ -+ /*remove from current list */ -+ ICP_LIST_DEL(tempSessionData, listNode); -+ /*add to free mem linked list */ -+ ICP_LIST_ADD(tempSessionData, -+ &icp_ocfDrvGlobalSymListHead_FreeMemList, -+ listNode); -+ -+ } -+ -+ /*EXIT CRITICAL SECTION */ -+ icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock); -+ -+ /*set back to initial values */ -+ sessionData = NULL; -+ /*still have a reference in our list! */ -+ tempSessionData = NULL; -+ /*free memory */ -+ -+ ICP_LIST_FOR_EACH_ENTRY_SAFE(tempSessionData, sessionData, -+ &icp_ocfDrvGlobalSymListHead_FreeMemList, -+ listNode) { -+ -+ ICP_LIST_DEL(tempSessionData, listNode); -+ /* Free allocated CpaCySymSessionCtx */ -+ if (NULL != tempSessionData->sessHandle) { -+ icp_kfree(tempSessionData->sessHandle); -+ } -+ memset(tempSessionData, 0, sizeof(struct icp_drvSessionData)); -+ ICP_CACHE_FREE(drvSessionData_zone, tempSessionData); -+ } -+ -+ if (0 != icp_atomic_read(&lac_session_failed_dereg_count)) { -+ DPRINTK("%s(): %d LAC sessions were not deregistered " -+ "correctly. This is not a clean exit! \n", -+ __FUNCTION__, -+ icp_atomic_read(&lac_session_failed_dereg_count)); -+ } -+ -+ icp_ocfDrvFreeCaches(); -+ icp_ocfDrvDriverId = INVALID_DRIVER_ID; -+ -+ icp_spin_lock_destroy(&icp_ocfDrvSymSessInfoListSpinlock); -+ -+ /* Shutdown the Cryptographic component */ -+ lacStatus = cpaCyStopInstance(CPA_INSTANCE_HANDLE_SINGLE); -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ DPRINTK("%s(): Failed to stop instance of the " -+ "Cryptographic component.(status == %d)\n", -+ __FUNCTION__, lacStatus); -+ } -+ -+ return ICP_MODULE_EXIT_FUNC_RETURN_VAL; -+} -+ -+/* Name : icp_ocfDrvFreeCaches -+ * -+ * Description : This function deregisters all slab caches -+ */ -+static void icp_ocfDrvFreeCaches(void) -+{ -+ icp_atomic_set(&icp_ocfDrvIsExiting, 1); -+ -+ /*Sym Zones */ -+ ICP_CACHE_DESTROY(drvSessionData_zone); -+ ICP_CACHE_DESTROY(drvOpData_zone); -+ -+ /*Asym zones */ -+ ICP_CACHE_DESTROY(drvDH_zone); -+ ICP_CACHE_DESTROY(drvLnModExp_zone); -+ ICP_CACHE_DESTROY(drvRSADecrypt_zone); -+ ICP_CACHE_DESTROY(drvRSAPrivateKey_zone); -+ ICP_CACHE_DESTROY(drvDSARSSignKValue_zone); -+ ICP_CACHE_DESTROY(drvDSARSSign_zone); -+ ICP_CACHE_DESTROY(drvDSAVerify_zone); -+ -+ /*FlatBuffer and BufferList Zones */ -+ ICP_CACHE_DESTROY(drvFlatBuffer_zone); -+ -+} -+ -+/* Name : icp_ocfDrvDeregRetry -+ * -+ * Description : This function will try to farm the session deregistration -+ * off to a work queue. If it fails, nothing more can be done and it -+ * returns an error -+ */ -+int icp_ocfDrvDeregRetry(CpaCySymSessionCtx sessionToDeregister) -+{ -+ struct icp_ocfDrvFreeLacSession *workstore = NULL; -+ -+ DPRINTK("%s(): Retry - Deregistering session (%p)\n", -+ __FUNCTION__, sessionToDeregister); -+ -+ /*make sure the session is not available to be allocated during this -+ process */ -+ icp_atomic_inc(&lac_session_failed_dereg_count); -+ -+ /*Farm off to work queue */ -+ workstore = -+ icp_kmalloc(sizeof(struct icp_ocfDrvFreeLacSession), ICP_M_NOWAIT); -+ if (NULL == workstore) { -+ DPRINTK("%s(): unable to free session - no memory available " -+ "for work queue\n", __FUNCTION__); -+ return ENOMEM; -+ } -+ -+ workstore->sessionToDeregister = sessionToDeregister; -+ -+ icp_init_work(&(workstore->work), -+ icp_ocfDrvDeferedFreeLacSessionTaskFn, workstore); -+ -+ ICP_WORKQUEUE_ENQUEUE(icp_ocfDrvFreeLacSessionWorkQ, -+ &(workstore->work)); -+ -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+ -+} -+ -+/* Name : icp_ocfDrvDeferedFreeLacSessionProcess -+ * -+ * Description : This function will retry (module input parameter) -+ * 'num_dereg_retries' times to deregister any symmetric session that recieves a -+ * CPA_STATUS_RETRY message from the LAC component. This function is run in -+ * Thread context because it is called from a worker thread -+ */ -+void icp_ocfDrvDeferedFreeLacSessionProcess(void *arg) -+{ -+ struct icp_ocfDrvFreeLacSession *workstore = NULL; -+ CpaCySymSessionCtx sessionToDeregister = NULL; -+ int i = 0; -+ int remaining_delay_time_in_jiffies = 0; -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ -+ workstore = (struct icp_ocfDrvFreeLacSession *)arg; -+ if (NULL == workstore) { -+ DPRINTK("%s() function called with null parameter \n", -+ __FUNCTION__); -+ return; -+ } -+ -+ sessionToDeregister = workstore->sessionToDeregister; -+ icp_kfree(workstore); -+ -+ /*if exiting, give deregistration one more blast only */ -+ if (icp_atomic_read(&icp_ocfDrvIsExiting) == CPA_TRUE) { -+ lacStatus = cpaCySymRemoveSession(CPA_INSTANCE_HANDLE_SINGLE, -+ sessionToDeregister); -+ -+ if (lacStatus != CPA_STATUS_SUCCESS) { -+ DPRINTK("%s() Failed to Dereg LAC session %p " -+ "during module exit\n", __FUNCTION__, -+ sessionToDeregister); -+ return; -+ } -+ -+ icp_atomic_dec(&lac_session_failed_dereg_count); -+ return; -+ } -+ -+ for (i = 0; i <= num_dereg_retries; i++) { -+ lacStatus = cpaCySymRemoveSession(CPA_INSTANCE_HANDLE_SINGLE, -+ sessionToDeregister); -+ -+ if (lacStatus == CPA_STATUS_SUCCESS) { -+ icp_atomic_dec(&lac_session_failed_dereg_count); -+ return; -+ } -+ if (lacStatus != CPA_STATUS_RETRY) { -+ DPRINTK("%s() Failed to deregister session - lacStatus " -+ " = %d", __FUNCTION__, lacStatus); -+ break; -+ } -+ -+ /*schedule_timout returns the time left for completion if this -+ task is set to TASK_INTERRUPTIBLE */ -+ remaining_delay_time_in_jiffies = dereg_retry_delay_in_jiffies; -+ while (0 < remaining_delay_time_in_jiffies) { -+ remaining_delay_time_in_jiffies = -+ icp_schedule_timeout(NULL, -+ remaining_delay_time_in_jiffies); -+ } -+ -+ } -+ -+ DPRINTK("%s(): Unable to deregister session\n", __FUNCTION__); -+ DPRINTK("%s(): Number of unavailable LAC sessions = %d\n", __FUNCTION__, -+ icp_atomic_read(&lac_session_failed_dereg_count)); -+} -+ -+/* Name : icp_ocfDrvPtrAndLenToFlatBuffer -+ * -+ * Description : This function converts a "pointer and length" buffer -+ * structure to Fredericksburg Flat Buffer (CpaFlatBuffer) format. -+ * -+ * This function assumes that the data passed in are valid. -+ */ -+inline void -+icp_ocfDrvPtrAndLenToFlatBuffer(void *pData, uint32_t len, -+ CpaFlatBuffer * pFlatBuffer) -+{ -+ pFlatBuffer->pData = pData; -+ pFlatBuffer->dataLenInBytes = len; -+} -+ -+/* Name : icp_ocfDrvPtrAndLenToBufferList -+ * -+ * Description : This function converts a "pointer and length" buffer -+ * structure to Fredericksburg Scatter/Gather Buffer (CpaBufferList) format. -+ * -+ * This function assumes that the data passed in are valid. -+ */ -+inline void -+icp_ocfDrvPtrAndLenToBufferList(void *pDataIn, uint32_t length, -+ CpaBufferList * pBufferList) -+{ -+ pBufferList->numBuffers = 1; -+ pBufferList->pBuffers->pData = pDataIn; -+ pBufferList->pBuffers->dataLenInBytes = length; -+} -+ -+/* Name : icp_ocfDrvBufferListToPtrAndLen -+ * -+ * Description : This function converts Fredericksburg Scatter/Gather Buffer -+ * (CpaBufferList) format to a "pointer and length" buffer structure. -+ * -+ * This function assumes that the data passed in are valid. -+ */ -+inline void -+icp_ocfDrvBufferListToPtrAndLen(CpaBufferList * pBufferList, -+ void **ppDataOut, uint32_t * pLength) -+{ -+ *ppDataOut = pBufferList->pBuffers->pData; -+ *pLength = pBufferList->pBuffers->dataLenInBytes; -+} -+ -+/* Name : icp_ocfDrvBufferListMemInfo -+ * -+ * Description : This function will set the number of flat buffers in -+ * bufferlist, the size of memory to allocate for the pPrivateMetaData -+ * member of the CpaBufferList. -+ */ -+int -+icp_ocfDrvBufferListMemInfo(uint16_t numBuffers, -+ struct icp_drvBuffListInfo *buffListInfo) -+{ -+ buffListInfo->numBuffers = numBuffers; -+ -+ if (CPA_STATUS_SUCCESS != -+ cpaCyBufferListGetMetaSize(CPA_INSTANCE_HANDLE_SINGLE, -+ buffListInfo->numBuffers, -+ &(buffListInfo->metaSize))) { -+ EPRINTK("%s() Failed to get buffer list meta size.\n", -+ __FUNCTION__); -+ return ICP_OCF_DRV_STATUS_FAIL; -+ } -+ -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+} -+ -+/* Name : icp_ocfDrvFreeFlatBuffer -+ * -+ * Description : This function will deallocate flat buffer. -+ */ -+inline void icp_ocfDrvFreeFlatBuffer(CpaFlatBuffer * pFlatBuffer) -+{ -+ if (pFlatBuffer != NULL) { -+ memset(pFlatBuffer, 0, sizeof(CpaFlatBuffer)); -+ ICP_CACHE_FREE(drvFlatBuffer_zone, pFlatBuffer); -+ } -+} -+ -+/* Name : icp_ocfDrvAllocMetaData -+ * -+ * Description : This function will allocate memory for the -+ * pPrivateMetaData member of CpaBufferList. -+ */ -+inline int -+icp_ocfDrvAllocMetaData(CpaBufferList * pBufferList, -+ struct icp_drvOpData *pOpData) -+{ -+ Cpa32U metaSize = 0; -+ -+ if (pBufferList->numBuffers <= ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) { -+ uint8_t *pOpDataStartAddr = (uint8_t *) pOpData; -+ -+ if (0 == defBuffListInfo.metaSize) { -+ pBufferList->pPrivateMetaData = NULL; -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+ } -+ /* -+ * The meta data allocation has been included as part of the -+ * op data. It has been pre-allocated in memory just after the -+ * icp_drvOpData structure. -+ */ -+ pBufferList->pPrivateMetaData = (void *)(pOpDataStartAddr + -+ sizeof(struct -+ icp_drvOpData)); -+ } else { -+ if (CPA_STATUS_SUCCESS != -+ cpaCyBufferListGetMetaSize(CPA_INSTANCE_HANDLE_SINGLE, -+ pBufferList->numBuffers, -+ &metaSize)) { -+ EPRINTK("%s() Failed to get buffer list meta size.\n", -+ __FUNCTION__); -+ return ICP_OCF_DRV_STATUS_FAIL; -+ } -+ -+ if (0 == metaSize) { -+ pBufferList->pPrivateMetaData = NULL; -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+ } -+ -+ pBufferList->pPrivateMetaData = -+ icp_kmalloc(metaSize, ICP_M_NOWAIT); -+ } -+ if (NULL == pBufferList->pPrivateMetaData) { -+ EPRINTK("%s() Failed to allocate pPrivateMetaData.\n", -+ __FUNCTION__); -+ return ICP_OCF_DRV_STATUS_FAIL; -+ } -+ -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+} -+ -+/* Name : icp_ocfDrvFreeMetaData -+ * -+ * Description : This function will deallocate pPrivateMetaData memory. -+ */ -+inline void icp_ocfDrvFreeMetaData(CpaBufferList * pBufferList) -+{ -+ if (NULL == pBufferList->pPrivateMetaData) { -+ return; -+ } -+ -+ /* -+ * Only free the meta data if the BufferList has more than -+ * ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS number of buffers. -+ * Otherwise, the meta data shall be freed when the icp_drvOpData is -+ * freed. -+ */ -+ if (ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS < pBufferList->numBuffers) { -+ icp_kfree(pBufferList->pPrivateMetaData); -+ } -+} -+ -+/* Module declaration, init and exit functions */ -+ICP_DECLARE_MODULE(icp_ocf, icp_ocfDrvInit, icp_ocfDrvExit); -+ICP_MODULE_DESCRIPTION("OCF Driver for Intel Quick Assist crypto acceleration"); -+ICP_MODULE_VERSION(icp_ocf, ICP_OCF_VER_MJR); -+ICP_MODULE_LICENSE("Dual BSD/GPL"); -+ICP_MODULE_AUTHOR("Intel"); -+ -+/* Module parameters */ -+ICP_MODULE_PARAM_INT(icp_ocf, num_dereg_retries, -+ "Number of times to retry LAC Sym Session Deregistration. " -+ "Default 10, Max 100"); -+ICP_MODULE_PARAM_INT(icp_ocf, dereg_retry_delay_in_jiffies, "Delay in jiffies " -+ "(added to a schedule() function call) before a LAC Sym " -+ "Session Dereg is retried. Default 10"); -+ICP_MODULE_PARAM_INT(icp_ocf, max_sessions, -+ "This sets the maximum number of sessions " -+ "between OCF and this driver. If this value is set to zero," -+ "max session count checking is disabled. Default is zero(0)"); -+ -+/* Module dependencies */ -+#define MODULE_MIN_VER 1 -+#define CRYPTO_MAX_VER 3 -+#define LAC_MAX_VER 2 -+ -+ICP_MODULE_DEPEND(icp_ocf, crypto, MODULE_MIN_VER, MODULE_MIN_VER, -+ CRYPTO_MAX_VER); -+ICP_MODULE_DEPEND(icp_ocf, cryptodev, MODULE_MIN_VER, MODULE_MIN_VER, -+ CRYPTO_MAX_VER); -+ICP_MODULE_DEPEND(icp_ocf, icp_crypto, MODULE_MIN_VER, MODULE_MIN_VER, -+ LAC_MAX_VER); -diff -Nur linux-2.6.36.orig/crypto/ocf/ep80579/icp_ocf.h linux-2.6.36/crypto/ocf/ep80579/icp_ocf.h ---- linux-2.6.36.orig/crypto/ocf/ep80579/icp_ocf.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/ep80579/icp_ocf.h 2010-11-09 20:28:04.662495462 +0100 -@@ -0,0 +1,376 @@ -+/*************************************************************************** -+ * -+ * This file is provided under a dual BSD/GPLv2 license. When using or -+ * redistributing this file, you may do so under either license. -+ * -+ * GPL LICENSE SUMMARY -+ * -+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of version 2 of the GNU General Public License as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. -+ * The full GNU General Public License is included in this distribution -+ * in the file called LICENSE.GPL. -+ * -+ * Contact Information: -+ * Intel Corporation -+ * -+ * BSD LICENSE -+ * -+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * * Neither the name of Intel Corporation nor the names of its -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * -+ * version: Security.L.1.0.2-229 -+ * -+ ***************************************************************************/ -+ -+/* -+ * OCF driver header file for the Intel ICP processor. -+ */ -+ -+#ifndef ICP_OCF_H_ -+#define ICP_OCF_H_ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "icp_os.h" -+ -+#define NUM_BITS_IN_BYTE (8) -+#define NUM_BITS_IN_BYTE_MINUS_ONE (NUM_BITS_IN_BYTE -1) -+#define INVALID_DRIVER_ID (-1) -+#define RETURN_RAND_NUM_GEN_FAILED (-1) -+ -+/*This is the max block cipher initialisation vector*/ -+#define MAX_IV_LEN_IN_BYTES (20) -+/*This is used to check whether the OCF to this driver session limit has -+ been disabled*/ -+#define NO_OCF_TO_DRV_MAX_SESSIONS (0) -+ -+/*OCF values mapped here*/ -+#define ICP_SHA1_DIGEST_SIZE_IN_BYTES (SHA1_HASH_LEN) -+#define ICP_SHA256_DIGEST_SIZE_IN_BYTES (SHA2_256_HASH_LEN) -+#define ICP_SHA384_DIGEST_SIZE_IN_BYTES (SHA2_384_HASH_LEN) -+#define ICP_SHA512_DIGEST_SIZE_IN_BYTES (SHA2_512_HASH_LEN) -+#define ICP_MD5_DIGEST_SIZE_IN_BYTES (MD5_HASH_LEN) -+#define ARC4_COUNTER_LEN (ARC4_BLOCK_LEN) -+ -+#define OCF_REGISTRATION_STATUS_SUCCESS (0) -+#define OCF_ZERO_FUNCTIONALITY_REGISTERED (0) -+#define ICP_OCF_DRV_NO_CRYPTO_PROCESS_ERROR (0) -+#define ICP_OCF_DRV_STATUS_SUCCESS (0) -+#define ICP_OCF_DRV_STATUS_FAIL (1) -+ -+/*Turn on/off debug options*/ -+#define ICP_OCF_PRINT_DEBUG_MESSAGES (0) -+#define ICP_OCF_PRINT_KERN_ALERT (1) -+#define ICP_OCF_PRINT_KERN_ERRS (1) -+ -+#if ICP_OCF_PRINT_DEBUG_MESSAGES == 1 -+#define DPRINTK(args...) \ -+{ \ -+ ICP_IPRINTK(args); \ -+} -+ -+#else //ICP_OCF_PRINT_DEBUG_MESSAGES == 1 -+ -+#define DPRINTK(args...) -+ -+#endif //ICP_OCF_PRINT_DEBUG_MESSAGES == 1 -+ -+#if ICP_OCF_PRINT_KERN_ALERT == 1 -+#define APRINTK(args...) \ -+{ \ -+ ICP_APRINTK(args); \ -+} -+ -+#else //ICP_OCF_PRINT_KERN_ALERT == 1 -+ -+#define APRINTK(args...) -+ -+#endif //ICP_OCF_PRINT_KERN_ALERT == 1 -+ -+#if ICP_OCF_PRINT_KERN_ERRS == 1 -+#define EPRINTK(args...) \ -+{ \ -+ ICP_EPRINTK(args); \ -+} -+ -+#else //ICP_OCF_PRINT_KERN_ERRS == 1 -+ -+#define EPRINTK(args...) -+ -+#endif //ICP_OCF_PRINT_KERN_ERRS == 1 -+ -+#define IPRINTK(args...) \ -+{ \ -+ ICP_IPRINTK(args); \ -+} -+ -+/*DSA Prime Q size in bytes (as defined in the standard) */ -+#define DSA_RS_SIGN_PRIMEQ_SIZE_IN_BYTES (20) -+ -+#define BITS_TO_BYTES(bytes, bits) \ -+ bytes = (bits + NUM_BITS_IN_BYTE_MINUS_ONE) / NUM_BITS_IN_BYTE -+ -+typedef enum { -+ ICP_OCF_DRV_ALG_CIPHER = 0, -+ ICP_OCF_DRV_ALG_HASH -+} icp_ocf_drv_alg_type_t; -+ -+typedef ICP_LIST_HEAD(icp_drvSessionListHead_s, -+ icp_drvSessionData) icp_drvSessionListHead_t; -+ -+/*Values used to derisk chances of performs being called against -+deregistered sessions (for which the slab page has been reclaimed) -+This is not a fix - since page frames are reclaimed from a slab, one cannot -+rely on that memory not being re-used by another app.*/ -+typedef enum { -+ ICP_SESSION_INITIALISED = 0x5C5C5C, -+ ICP_SESSION_RUNNING = 0x005C00, -+ ICP_SESSION_DEREGISTERED = 0xC5C5C5 -+} usage_derisk; -+ -+/* This struct is required for deferred session -+ deregistration as a work queue function can -+ only have one argument*/ -+struct icp_ocfDrvFreeLacSession { -+ CpaCySymSessionCtx sessionToDeregister; -+ icp_workstruct work; -+}; -+ -+/* -+This is the OCF<->OCF_DRV session object: -+ -+1.listNode -+ The first member is a listNode. These session objects are added to a linked -+ list in order to make it easier to remove them all at session exit time. -+ -+2.inUse -+ The second member is used to give the session object state and derisk the -+ possibility of OCF batch calls executing against a deregistered session (as -+ described above). -+ -+3.sessHandle -+ The third member is a LAC<->OCF_DRV session handle (initialised with the first -+ perform request for that session). -+ -+4.lacSessCtx -+ The fourth is the LAC session context. All the parameters for this structure -+ are only known when the first perform request for this session occurs. That is -+ why the OCF EP80579 Driver only registers a new LAC session at perform time -+*/ -+struct icp_drvSessionData { -+ ICP_LIST_ENTRY(icp_drvSessionData) listNode; -+ usage_derisk inUse; -+ CpaCySymSessionCtx sessHandle; -+ CpaCySymSessionSetupData lacSessCtx; -+}; -+ -+/* These are all defined in icp_common.c */ -+extern icp_atomic_t lac_session_failed_dereg_count; -+extern icp_atomic_t icp_ocfDrvIsExiting; -+extern icp_atomic_t num_ocf_to_drv_registered_sessions; -+ -+extern int32_t icp_ocfDrvDriverId; -+ -+extern icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead; -+extern icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead_FreeMemList; -+extern icp_workqueue *icp_ocfDrvFreeLacSessionWorkQ; -+extern icp_spinlock_t icp_ocfDrvSymSessInfoListSpinlock; -+ -+/*Slab zones for symettric functionality, instantiated in icp_common.c*/ -+extern icp_kmem_cache drvSessionData_zone; -+extern icp_kmem_cache drvOpData_zone; -+ -+/*Slabs zones for asymettric functionality, instantiated in icp_common.c*/ -+extern icp_kmem_cache drvDH_zone; -+extern icp_kmem_cache drvLnModExp_zone; -+extern icp_kmem_cache drvRSADecrypt_zone; -+extern icp_kmem_cache drvRSAPrivateKey_zone; -+extern icp_kmem_cache drvDSARSSign_zone; -+extern icp_kmem_cache drvDSARSSignKValue_zone; -+extern icp_kmem_cache drvDSAVerify_zone; -+ -+/* Module parameters defined in icp_cpmmon.c*/ -+ -+/* Module parameters - gives the number of times LAC deregistration shall be -+ re-tried */ -+extern int num_dereg_retries; -+ -+/* Module parameter - gives the delay time in jiffies before a LAC session -+ shall be attempted to be deregistered again */ -+extern int dereg_retry_delay_in_jiffies; -+ -+/* Module parameter - gives the maximum number of sessions possible between -+ OCF and the OCF EP80579 Driver. If set to zero, there is no limit.*/ -+extern int max_sessions; -+ -+/*Slab zones for flatbuffers and bufferlist*/ -+extern icp_kmem_cache drvFlatBuffer_zone; -+ -+#define ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS (16) -+ -+struct icp_drvBuffListInfo { -+ Cpa16U numBuffers; -+ Cpa32U metaSize; -+ Cpa32U metaOffset; -+ Cpa32U buffListSize; -+}; -+ -+extern struct icp_drvBuffListInfo defBuffListInfo; -+ -+/* This struct is used to keep a reference to the relevant node in the list -+ of sessionData structs, to the buffer type required by OCF and to the OCF -+ provided crp struct that needs to be returned. All this info is needed in -+ the callback function.*/ -+struct icp_drvOpData { -+ CpaCySymOpData lacOpData; -+ uint32_t digestSizeInBytes; -+ struct cryptop *crp; -+ uint8_t bufferType; -+ uint8_t ivData[MAX_IV_LEN_IN_BYTES]; -+ uint16_t numBufferListArray; -+ CpaBufferList srcBuffer; -+ CpaFlatBuffer bufferListArray[ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS]; -+ CpaBoolean verifyResult; -+}; -+ -+/* Create a new session between OCF and this driver*/ -+int icp_ocfDrvNewSession(icp_device_t dev, uint32_t * sild, -+ struct cryptoini *cri); -+ -+/* Free a session between this driver and the Quick Assist Framework*/ -+int icp_ocfDrvFreeLACSession(icp_device_t dev, uint64_t sid); -+ -+/* Defer freeing a Quick Assist session*/ -+void icp_ocfDrvDeferedFreeLacSessionProcess(void *arg); -+ -+/* Process OCF cryptographic request for a symmetric algorithm*/ -+int icp_ocfDrvSymProcess(icp_device_t dev, struct cryptop *crp, int hint); -+ -+/* Process OCF cryptographic request for an asymmetric algorithm*/ -+int icp_ocfDrvPkeProcess(icp_device_t dev, struct cryptkop *krp, int hint); -+ -+/* Populate a buffer with random data*/ -+int icp_ocfDrvReadRandom(void *arg, uint32_t * buf, int maxwords); -+ -+/* Retry Quick Assist session deregistration*/ -+int icp_ocfDrvDeregRetry(CpaCySymSessionCtx sessionToDeregister); -+ -+/* Convert an OS scatter gather list to a CPA buffer list*/ -+int icp_ocfDrvPacketBuffToBufferList(icp_packet_buffer_t * pPacketBuffer, -+ CpaBufferList * bufferList); -+ -+/* Convert a CPA buffer list to an OS scatter gather list*/ -+int icp_ocfDrvBufferListToPacketBuff(CpaBufferList * bufferList, -+ icp_packet_buffer_t ** pPacketBuffer); -+ -+/* Get the number of buffers in an OS scatter gather list*/ -+uint16_t icp_ocfDrvGetPacketBuffFrags(icp_packet_buffer_t * pPacketBuffer); -+ -+/* Convert a single OS buffer to a CPA Flat Buffer*/ -+void icp_ocfDrvSinglePacketBuffToFlatBuffer(icp_packet_buffer_t * pPacketBuffer, -+ CpaFlatBuffer * pFlatBuffer); -+ -+/* Add pointer and length to a CPA Flat Buffer structure*/ -+void icp_ocfDrvPtrAndLenToFlatBuffer(void *pData, uint32_t len, -+ CpaFlatBuffer * pFlatBuffer); -+ -+/* Convert pointer and length values to a CPA buffer list*/ -+void icp_ocfDrvPtrAndLenToBufferList(void *pDataIn, uint32_t length, -+ CpaBufferList * pBufferList); -+ -+/* Convert a CPA buffer list to pointer and length values*/ -+void icp_ocfDrvBufferListToPtrAndLen(CpaBufferList * pBufferList, -+ void **ppDataOut, uint32_t * pLength); -+ -+/* Set the number of flat buffers in bufferlist and the size of memory -+ to allocate for the pPrivateMetaData member of the CpaBufferList.*/ -+int icp_ocfDrvBufferListMemInfo(uint16_t numBuffers, -+ struct icp_drvBuffListInfo *buffListInfo); -+ -+/* Find pointer position of the digest within an OS scatter gather list*/ -+uint8_t *icp_ocfDrvPacketBufferDigestPointerFind(struct icp_drvOpData -+ *drvOpData, -+ int offsetInBytes, -+ uint32_t digestSizeInBytes); -+ -+/*This top level function is used to find a pointer to where a digest is -+ stored/needs to be inserted. */ -+uint8_t *icp_ocfDrvDigestPointerFind(struct icp_drvOpData *drvOpData, -+ struct cryptodesc *crp_desc); -+ -+/* Free a CPA flat buffer*/ -+void icp_ocfDrvFreeFlatBuffer(CpaFlatBuffer * pFlatBuffer); -+ -+/* This function will allocate memory for the pPrivateMetaData -+ member of CpaBufferList. */ -+int icp_ocfDrvAllocMetaData(CpaBufferList * pBufferList, -+ struct icp_drvOpData *pOpData); -+ -+/* Free data allocated for the pPrivateMetaData -+ member of CpaBufferList.*/ -+void icp_ocfDrvFreeMetaData(CpaBufferList * pBufferList); -+ -+#define ICP_CACHE_CREATE(cache_ID, cache_name) \ -+ icp_kmem_cache_create(cache_ID, sizeof(cache_name),ICP_KERNEL_CACHE_ALIGN,\ -+ ICP_KERNEL_CACHE_NOINIT) -+ -+#define ICP_CACHE_FREE(args...) \ -+ icp_kmem_cache_free (args) -+ -+#define ICP_CACHE_DESTROY(slab_zone)\ -+{\ -+ if(NULL != slab_zone){\ -+ icp_kmem_cache_destroy(slab_zone);\ -+ slab_zone = NULL;\ -+ }\ -+} -+ -+#endif -+/* ICP_OCF_H_ */ -diff -Nur linux-2.6.36.orig/crypto/ocf/ep80579/icp_sym.c linux-2.6.36/crypto/ocf/ep80579/icp_sym.c ---- linux-2.6.36.orig/crypto/ocf/ep80579/icp_sym.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/ep80579/icp_sym.c 2010-11-09 20:28:04.702495471 +0100 -@@ -0,0 +1,1153 @@ -+/*************************************************************************** -+ * -+ * This file is provided under a dual BSD/GPLv2 license. When using or -+ * redistributing this file, you may do so under either license. -+ * -+ * GPL LICENSE SUMMARY -+ * -+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of version 2 of the GNU General Public License as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. -+ * The full GNU General Public License is included in this distribution -+ * in the file called LICENSE.GPL. -+ * -+ * Contact Information: -+ * Intel Corporation -+ * -+ * BSD LICENSE -+ * -+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * * Neither the name of Intel Corporation nor the names of its -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * -+ * version: Security.L.1.0.2-229 -+ * -+ ***************************************************************************/ -+/* -+ * An OCF module that uses the API for Intel® QuickAssist Technology to do the -+ * cryptography. -+ * -+ * This driver requires the ICP Access Library that is available from Intel in -+ * order to operate. -+ */ -+ -+#include "icp_ocf.h" -+ -+/*This is the call back function for all symmetric cryptographic processes. -+ Its main functionality is to free driver crypto operation structure and to -+ call back to OCF*/ -+static void -+icp_ocfDrvSymCallBack(void *callbackTag, -+ CpaStatus status, -+ const CpaCySymOp operationType, -+ void *pOpData, -+ CpaBufferList * pDstBuffer, CpaBoolean verifyResult); -+ -+/*This function is used to extract crypto processing information from the OCF -+ inputs, so as that it may be passed onto LAC*/ -+static int -+icp_ocfDrvProcessDataSetup(struct icp_drvOpData *drvOpData, -+ struct cryptodesc *crp_desc); -+ -+/*This function checks whether the crp_desc argument pertains to a digest or a -+ cipher operation*/ -+static int icp_ocfDrvAlgCheck(struct cryptodesc *crp_desc); -+ -+/*This function copies all the passed in session context information and stores -+ it in a LAC context structure*/ -+static int -+icp_ocfDrvAlgorithmSetup(struct cryptoini *cri, -+ CpaCySymSessionSetupData * lacSessCtx); -+ -+/*This function is used to free an OCF->OCF_DRV session object*/ -+static void icp_ocfDrvFreeOCFSession(struct icp_drvSessionData *sessionData); -+ -+/*max IOV buffs supported in a UIO structure*/ -+#define NUM_IOV_SUPPORTED (1) -+ -+/* Name : icp_ocfDrvSymCallBack -+ * -+ * Description : When this function returns it signifies that the LAC -+ * component has completed the relevant symmetric operation. -+ * -+ * Notes : The callbackTag is a pointer to an icp_drvOpData. This memory -+ * object was passed to LAC for the cryptographic processing and contains all -+ * the relevant information for cleaning up buffer handles etc. so that the -+ * OCF EP80579 Driver portion of this crypto operation can be fully completed. -+ */ -+static void -+icp_ocfDrvSymCallBack(void *callbackTag, -+ CpaStatus status, -+ const CpaCySymOp operationType, -+ void *pOpData, -+ CpaBufferList * pDstBuffer, CpaBoolean verifyResult) -+{ -+ struct cryptop *crp = NULL; -+ struct icp_drvOpData *temp_drvOpData = -+ (struct icp_drvOpData *)callbackTag; -+ uint64_t *tempBasePtr = NULL; -+ uint32_t tempLen = 0; -+ -+ if (NULL == temp_drvOpData) { -+ DPRINTK("%s(): The callback from the LAC component" -+ " has failed due to Null userOpaque data" -+ "(status == %d).\n", __FUNCTION__, status); -+ DPRINTK("%s(): Unable to call OCF back! \n", __FUNCTION__); -+ return; -+ } -+ -+ crp = temp_drvOpData->crp; -+ crp->crp_etype = ICP_OCF_DRV_NO_CRYPTO_PROCESS_ERROR; -+ -+ if (NULL == pOpData) { -+ DPRINTK("%s(): The callback from the LAC component" -+ " has failed due to Null Symmetric Op data" -+ "(status == %d).\n", __FUNCTION__, status); -+ crp->crp_etype = ECANCELED; -+ crypto_done(crp); -+ return; -+ } -+ -+ if (NULL == pDstBuffer) { -+ DPRINTK("%s(): The callback from the LAC component" -+ " has failed due to Null Dst Bufferlist data" -+ "(status == %d).\n", __FUNCTION__, status); -+ crp->crp_etype = ECANCELED; -+ crypto_done(crp); -+ return; -+ } -+ -+ if (CPA_STATUS_SUCCESS == status) { -+ -+ if (temp_drvOpData->bufferType == ICP_CRYPTO_F_PACKET_BUF) { -+ if (ICP_OCF_DRV_STATUS_SUCCESS != -+ icp_ocfDrvBufferListToPacketBuff(pDstBuffer, -+ (icp_packet_buffer_t -+ **) -+ & (crp->crp_buf))) { -+ EPRINTK("%s(): BufferList to SkBuff " -+ "conversion error.\n", __FUNCTION__); -+ crp->crp_etype = EPERM; -+ } -+ } else { -+ icp_ocfDrvBufferListToPtrAndLen(pDstBuffer, -+ (void **)&tempBasePtr, -+ &tempLen); -+ crp->crp_olen = (int)tempLen; -+ } -+ -+ } else { -+ DPRINTK("%s(): The callback from the LAC component has failed" -+ "(status == %d).\n", __FUNCTION__, status); -+ -+ crp->crp_etype = ECANCELED; -+ } -+ -+ if (temp_drvOpData->numBufferListArray > -+ ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) { -+ icp_kfree(pDstBuffer->pBuffers); -+ } -+ icp_ocfDrvFreeMetaData(pDstBuffer); -+ ICP_CACHE_FREE(drvOpData_zone, temp_drvOpData); -+ -+ /* Invoke the OCF callback function */ -+ crypto_done(crp); -+ -+ return; -+} -+ -+/* Name : icp_ocfDrvNewSession -+ * -+ * Description : This function will create a new Driver<->OCF session -+ * -+ * Notes : LAC session registration happens during the first perform call. -+ * That is the first time we know all information about a given session. -+ */ -+int icp_ocfDrvNewSession(icp_device_t dev, uint32_t * sid, -+ struct cryptoini *cri) -+{ -+ struct icp_drvSessionData *sessionData = NULL; -+ uint32_t delete_session = 0; -+ -+ /* The SID passed in should be our driver ID. We can return the */ -+ /* local ID (LID) which is a unique identifier which we can use */ -+ /* to differentiate between the encrypt/decrypt LAC session handles */ -+ if (NULL == sid) { -+ EPRINTK("%s(): Invalid input parameters - NULL sid.\n", -+ __FUNCTION__); -+ return EINVAL; -+ } -+ -+ if (NULL == cri) { -+ EPRINTK("%s(): Invalid input parameters - NULL cryptoini.\n", -+ __FUNCTION__); -+ return EINVAL; -+ } -+ -+ if (icp_ocfDrvDriverId != *sid) { -+ EPRINTK("%s(): Invalid input parameters - bad driver ID\n", -+ __FUNCTION__); -+ EPRINTK("\t sid = 0x08%p \n \t cri = 0x08%p \n", sid, cri); -+ return EINVAL; -+ } -+ -+ sessionData = icp_kmem_cache_zalloc(drvSessionData_zone, ICP_M_NOWAIT); -+ if (NULL == sessionData) { -+ DPRINTK("%s():No memory for Session Data\n", __FUNCTION__); -+ return ENOMEM; -+ } -+ -+ /*ENTER CRITICAL SECTION */ -+ icp_spin_lockbh_lock(&icp_ocfDrvSymSessInfoListSpinlock); -+ /*put this check in the spinlock so no new sessions can be added to the -+ linked list when we are exiting */ -+ if (CPA_TRUE == icp_atomic_read(&icp_ocfDrvIsExiting)) { -+ delete_session++; -+ -+ } else if (NO_OCF_TO_DRV_MAX_SESSIONS != max_sessions) { -+ if (icp_atomic_read(&num_ocf_to_drv_registered_sessions) >= -+ (max_sessions - -+ icp_atomic_read(&lac_session_failed_dereg_count))) { -+ delete_session++; -+ } else { -+ icp_atomic_inc(&num_ocf_to_drv_registered_sessions); -+ /* Add to session data linked list */ -+ ICP_LIST_ADD(sessionData, &icp_ocfDrvGlobalSymListHead, -+ listNode); -+ } -+ -+ } else if (NO_OCF_TO_DRV_MAX_SESSIONS == max_sessions) { -+ ICP_LIST_ADD(sessionData, &icp_ocfDrvGlobalSymListHead, -+ listNode); -+ } -+ -+ sessionData->inUse = ICP_SESSION_INITIALISED; -+ -+ /*EXIT CRITICAL SECTION */ -+ icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock); -+ -+ if (delete_session) { -+ DPRINTK("%s():No Session handles available\n", __FUNCTION__); -+ ICP_CACHE_FREE(drvSessionData_zone, sessionData); -+ return EPERM; -+ } -+ -+ if (ICP_OCF_DRV_STATUS_SUCCESS != -+ icp_ocfDrvAlgorithmSetup(cri, &(sessionData->lacSessCtx))) { -+ DPRINTK("%s():algorithm not supported\n", __FUNCTION__); -+ icp_ocfDrvFreeOCFSession(sessionData); -+ return EINVAL; -+ } -+ -+ if (cri->cri_next) { -+ if (cri->cri_next->cri_next != NULL) { -+ DPRINTK("%s():only two chained algorithms supported\n", -+ __FUNCTION__); -+ icp_ocfDrvFreeOCFSession(sessionData); -+ return EPERM; -+ } -+ -+ if (ICP_OCF_DRV_STATUS_SUCCESS != -+ icp_ocfDrvAlgorithmSetup(cri->cri_next, -+ &(sessionData->lacSessCtx))) { -+ DPRINTK("%s():second algorithm not supported\n", -+ __FUNCTION__); -+ icp_ocfDrvFreeOCFSession(sessionData); -+ return EINVAL; -+ } -+ -+ sessionData->lacSessCtx.symOperation = -+ CPA_CY_SYM_OP_ALGORITHM_CHAINING; -+ } -+ -+ *sid = (uint32_t) sessionData; -+ -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+} -+ -+/* Name : icp_ocfDrvAlgorithmSetup -+ * -+ * Description : This function builds the session context data from the -+ * information supplied through OCF. Algorithm chain order and whether the -+ * session is Encrypt/Decrypt can only be found out at perform time however, so -+ * the session is registered with LAC at that time. -+ */ -+static int -+icp_ocfDrvAlgorithmSetup(struct cryptoini *cri, -+ CpaCySymSessionSetupData * lacSessCtx) -+{ -+ -+ lacSessCtx->sessionPriority = CPA_CY_PRIORITY_NORMAL; -+ -+ switch (cri->cri_alg) { -+ -+ case CRYPTO_NULL_CBC: -+ DPRINTK("%s(): NULL CBC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; -+ lacSessCtx->cipherSetupData.cipherAlgorithm = -+ CPA_CY_SYM_CIPHER_NULL; -+ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; -+ break; -+ -+ case CRYPTO_DES_CBC: -+ DPRINTK("%s(): DES CBC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; -+ lacSessCtx->cipherSetupData.cipherAlgorithm = -+ CPA_CY_SYM_CIPHER_DES_CBC; -+ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; -+ break; -+ -+ case CRYPTO_3DES_CBC: -+ DPRINTK("%s(): 3DES CBC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; -+ lacSessCtx->cipherSetupData.cipherAlgorithm = -+ CPA_CY_SYM_CIPHER_3DES_CBC; -+ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; -+ break; -+ -+ case CRYPTO_AES_CBC: -+ DPRINTK("%s(): AES CBC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; -+ lacSessCtx->cipherSetupData.cipherAlgorithm = -+ CPA_CY_SYM_CIPHER_AES_CBC; -+ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; -+ break; -+ -+ case CRYPTO_ARC4: -+ DPRINTK("%s(): ARC4\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; -+ lacSessCtx->cipherSetupData.cipherAlgorithm = -+ CPA_CY_SYM_CIPHER_ARC4; -+ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; -+ break; -+ -+ case CRYPTO_SHA1: -+ DPRINTK("%s(): SHA1\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_SHA1; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_SHA1_DIGEST_SIZE_IN_BYTES); -+ -+ break; -+ -+ case CRYPTO_SHA1_HMAC: -+ DPRINTK("%s(): SHA1_HMAC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_SHA1; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_SHA1_DIGEST_SIZE_IN_BYTES); -+ lacSessCtx->hashSetupData.authModeSetupData.authKey = -+ cri->cri_key; -+ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; -+ -+ break; -+ -+ case CRYPTO_SHA2_256: -+ DPRINTK("%s(): SHA256\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = -+ CPA_CY_SYM_HASH_SHA256; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_SHA256_DIGEST_SIZE_IN_BYTES); -+ -+ break; -+ -+ case CRYPTO_SHA2_256_HMAC: -+ DPRINTK("%s(): SHA256_HMAC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = -+ CPA_CY_SYM_HASH_SHA256; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_SHA256_DIGEST_SIZE_IN_BYTES); -+ lacSessCtx->hashSetupData.authModeSetupData.authKey = -+ cri->cri_key; -+ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; -+ -+ break; -+ -+ case CRYPTO_SHA2_384: -+ DPRINTK("%s(): SHA384\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = -+ CPA_CY_SYM_HASH_SHA384; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_SHA384_DIGEST_SIZE_IN_BYTES); -+ -+ break; -+ -+ case CRYPTO_SHA2_384_HMAC: -+ DPRINTK("%s(): SHA384_HMAC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = -+ CPA_CY_SYM_HASH_SHA384; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_SHA384_DIGEST_SIZE_IN_BYTES); -+ lacSessCtx->hashSetupData.authModeSetupData.authKey = -+ cri->cri_key; -+ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; -+ -+ break; -+ -+ case CRYPTO_SHA2_512: -+ DPRINTK("%s(): SHA512\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = -+ CPA_CY_SYM_HASH_SHA512; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_SHA512_DIGEST_SIZE_IN_BYTES); -+ -+ break; -+ -+ case CRYPTO_SHA2_512_HMAC: -+ DPRINTK("%s(): SHA512_HMAC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = -+ CPA_CY_SYM_HASH_SHA512; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_SHA512_DIGEST_SIZE_IN_BYTES); -+ lacSessCtx->hashSetupData.authModeSetupData.authKey = -+ cri->cri_key; -+ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; -+ -+ break; -+ -+ case CRYPTO_MD5: -+ DPRINTK("%s(): MD5\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_MD5; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_MD5_DIGEST_SIZE_IN_BYTES); -+ -+ break; -+ -+ case CRYPTO_MD5_HMAC: -+ DPRINTK("%s(): MD5_HMAC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_MD5; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_MD5_DIGEST_SIZE_IN_BYTES); -+ lacSessCtx->hashSetupData.authModeSetupData.authKey = -+ cri->cri_key; -+ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; -+ -+ break; -+ -+ default: -+ DPRINTK("%s(): ALG Setup FAIL\n", __FUNCTION__); -+ return ICP_OCF_DRV_STATUS_FAIL; -+ } -+ -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+} -+ -+/* Name : icp_ocfDrvFreeOCFSession -+ * -+ * Description : This function deletes all existing Session data representing -+ * the Cryptographic session established between OCF and this driver. This -+ * also includes freeing the memory allocated for the session context. The -+ * session object is also removed from the session linked list. -+ */ -+static void icp_ocfDrvFreeOCFSession(struct icp_drvSessionData *sessionData) -+{ -+ -+ sessionData->inUse = ICP_SESSION_DEREGISTERED; -+ -+ /*ENTER CRITICAL SECTION */ -+ icp_spin_lockbh_lock(&icp_ocfDrvSymSessInfoListSpinlock); -+ -+ if (CPA_TRUE == icp_atomic_read(&icp_ocfDrvIsExiting)) { -+ /*If the Driver is exiting, allow that process to -+ handle any deletions */ -+ /*EXIT CRITICAL SECTION */ -+ icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock); -+ return; -+ } -+ -+ icp_atomic_dec(&num_ocf_to_drv_registered_sessions); -+ -+ ICP_LIST_DEL(sessionData, listNode); -+ -+ /*EXIT CRITICAL SECTION */ -+ icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock); -+ -+ if (NULL != sessionData->sessHandle) { -+ icp_kfree(sessionData->sessHandle); -+ } -+ ICP_CACHE_FREE(drvSessionData_zone, sessionData); -+} -+ -+/* Name : icp_ocfDrvFreeLACSession -+ * -+ * Description : This attempts to deregister a LAC session. If it fails, the -+ * deregistation retry function is called. -+ */ -+int icp_ocfDrvFreeLACSession(icp_device_t dev, uint64_t sid) -+{ -+ CpaCySymSessionCtx sessionToDeregister = NULL; -+ struct icp_drvSessionData *sessionData = NULL; -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ int retval = 0; -+ -+ sessionData = (struct icp_drvSessionData *)CRYPTO_SESID2LID(sid); -+ if (NULL == sessionData) { -+ EPRINTK("%s(): OCF Free session called with Null Session ID.\n", -+ __FUNCTION__); -+ return EINVAL; -+ } -+ -+ sessionToDeregister = sessionData->sessHandle; -+ -+ if ((ICP_SESSION_INITIALISED != sessionData->inUse) && -+ (ICP_SESSION_RUNNING != sessionData->inUse) && -+ (ICP_SESSION_DEREGISTERED != sessionData->inUse)) { -+ DPRINTK("%s() Session not initialised.\n", __FUNCTION__); -+ return EINVAL; -+ } -+ -+ if (ICP_SESSION_RUNNING == sessionData->inUse) { -+ lacStatus = cpaCySymRemoveSession(CPA_INSTANCE_HANDLE_SINGLE, -+ sessionToDeregister); -+ if (CPA_STATUS_RETRY == lacStatus) { -+ if (ICP_OCF_DRV_STATUS_SUCCESS != -+ icp_ocfDrvDeregRetry(&sessionToDeregister)) { -+ /* the retry function increments the -+ dereg failed count */ -+ DPRINTK("%s(): LAC failed to deregister the " -+ "session. (localSessionId= %p)\n", -+ __FUNCTION__, sessionToDeregister); -+ retval = EPERM; -+ } -+ -+ } else if (CPA_STATUS_SUCCESS != lacStatus) { -+ DPRINTK("%s(): LAC failed to deregister the session. " -+ "localSessionId= %p, lacStatus = %d\n", -+ __FUNCTION__, sessionToDeregister, lacStatus); -+ icp_atomic_inc(&lac_session_failed_dereg_count); -+ retval = EPERM; -+ } -+ } else { -+ DPRINTK("%s() Session not registered with LAC.\n", -+ __FUNCTION__); -+ } -+ -+ icp_ocfDrvFreeOCFSession(sessionData); -+ return retval; -+ -+} -+ -+/* Name : icp_ocfDrvAlgCheck -+ * -+ * Description : This function checks whether the cryptodesc argument pertains -+ * to a sym or hash function -+ */ -+static int icp_ocfDrvAlgCheck(struct cryptodesc *crp_desc) -+{ -+ -+ if (crp_desc->crd_alg == CRYPTO_3DES_CBC || -+ crp_desc->crd_alg == CRYPTO_AES_CBC || -+ crp_desc->crd_alg == CRYPTO_DES_CBC || -+ crp_desc->crd_alg == CRYPTO_NULL_CBC || -+ crp_desc->crd_alg == CRYPTO_ARC4) { -+ return ICP_OCF_DRV_ALG_CIPHER; -+ } -+ -+ return ICP_OCF_DRV_ALG_HASH; -+} -+ -+/* Name : icp_ocfDrvSymProcess -+ * -+ * Description : This function will map symmetric functionality calls from OCF -+ * to the LAC API. It will also allocate memory to store the session context. -+ * -+ * Notes: If it is the first perform call for a given session, then a LAC -+ * session is registered. After the session is registered, no checks as -+ * to whether session paramaters have changed (e.g. alg chain order) are -+ * done. -+ */ -+int icp_ocfDrvSymProcess(icp_device_t dev, struct cryptop *crp, int hint) -+{ -+ struct icp_drvSessionData *sessionData = NULL; -+ struct icp_drvOpData *drvOpData = NULL; -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ Cpa32U sessionCtxSizeInBytes = 0; -+ -+ if (NULL == crp) { -+ DPRINTK("%s(): Invalid input parameters, cryptop is NULL\n", -+ __FUNCTION__); -+ return EINVAL; -+ } -+ -+ if (NULL == crp->crp_desc) { -+ DPRINTK("%s(): Invalid input parameters, no crp_desc attached " -+ "to crp\n", __FUNCTION__); -+ crp->crp_etype = EINVAL; -+ return EINVAL; -+ } -+ -+ if (NULL == crp->crp_buf) { -+ DPRINTK("%s(): Invalid input parameters, no buffer attached " -+ "to crp\n", __FUNCTION__); -+ crp->crp_etype = EINVAL; -+ return EINVAL; -+ } -+ -+ if (CPA_TRUE == icp_atomic_read(&icp_ocfDrvIsExiting)) { -+ crp->crp_etype = EFAULT; -+ return EFAULT; -+ } -+ -+ sessionData = (struct icp_drvSessionData *) -+ (CRYPTO_SESID2LID(crp->crp_sid)); -+ if (NULL == sessionData) { -+ DPRINTK("%s(): Invalid input parameters, Null Session ID \n", -+ __FUNCTION__); -+ crp->crp_etype = EINVAL; -+ return EINVAL; -+ } -+ -+/*If we get a request against a deregisted session, cancel operation*/ -+ if (ICP_SESSION_DEREGISTERED == sessionData->inUse) { -+ DPRINTK("%s(): Session ID %d was deregistered \n", -+ __FUNCTION__, (int)(CRYPTO_SESID2LID(crp->crp_sid))); -+ crp->crp_etype = EFAULT; -+ return EFAULT; -+ } -+ -+/*If none of the session states are set, then the session structure was either -+ not initialised properly or we are reading from a freed memory area (possible -+ due to OCF batch mode not removing queued requests against deregistered -+ sessions*/ -+ if (ICP_SESSION_INITIALISED != sessionData->inUse && -+ ICP_SESSION_RUNNING != sessionData->inUse) { -+ DPRINTK("%s(): Session - ID %d - not properly initialised or " -+ "memory freed back to the kernel \n", -+ __FUNCTION__, (int)(CRYPTO_SESID2LID(crp->crp_sid))); -+ crp->crp_etype = EINVAL; -+ return EINVAL; -+ } -+ -+ /*For the below checks, remember error checking is already done in LAC. -+ We're not validating inputs subsequent to registration */ -+ if (sessionData->inUse == ICP_SESSION_INITIALISED) { -+ DPRINTK("%s(): Initialising session\n", __FUNCTION__); -+ -+ if (NULL != crp->crp_desc->crd_next) { -+ if (ICP_OCF_DRV_ALG_CIPHER == -+ icp_ocfDrvAlgCheck(crp->crp_desc)) { -+ -+ sessionData->lacSessCtx.algChainOrder = -+ CPA_CY_SYM_ALG_CHAIN_ORDER_CIPHER_THEN_HASH; -+ -+ if (crp->crp_desc->crd_flags & CRD_F_ENCRYPT) { -+ sessionData->lacSessCtx.cipherSetupData. -+ cipherDirection = -+ CPA_CY_SYM_CIPHER_DIRECTION_ENCRYPT; -+ } else { -+ sessionData->lacSessCtx.cipherSetupData. -+ cipherDirection = -+ CPA_CY_SYM_CIPHER_DIRECTION_DECRYPT; -+ } -+ } else { -+ sessionData->lacSessCtx.algChainOrder = -+ CPA_CY_SYM_ALG_CHAIN_ORDER_HASH_THEN_CIPHER; -+ -+ if (crp->crp_desc->crd_next->crd_flags & -+ CRD_F_ENCRYPT) { -+ sessionData->lacSessCtx.cipherSetupData. -+ cipherDirection = -+ CPA_CY_SYM_CIPHER_DIRECTION_ENCRYPT; -+ } else { -+ sessionData->lacSessCtx.cipherSetupData. -+ cipherDirection = -+ CPA_CY_SYM_CIPHER_DIRECTION_DECRYPT; -+ } -+ -+ } -+ -+ } else if (ICP_OCF_DRV_ALG_CIPHER == -+ icp_ocfDrvAlgCheck(crp->crp_desc)) { -+ if (crp->crp_desc->crd_flags & CRD_F_ENCRYPT) { -+ sessionData->lacSessCtx.cipherSetupData. -+ cipherDirection = -+ CPA_CY_SYM_CIPHER_DIRECTION_ENCRYPT; -+ } else { -+ sessionData->lacSessCtx.cipherSetupData. -+ cipherDirection = -+ CPA_CY_SYM_CIPHER_DIRECTION_DECRYPT; -+ } -+ -+ } -+ -+ /*No action required for standalone Auth here */ -+ -+ /* Allocate memory for SymSessionCtx before the Session Registration */ -+ lacStatus = -+ cpaCySymSessionCtxGetSize(CPA_INSTANCE_HANDLE_SINGLE, -+ &(sessionData->lacSessCtx), -+ &sessionCtxSizeInBytes); -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): cpaCySymSessionCtxGetSize failed - %d\n", -+ __FUNCTION__, lacStatus); -+ crp->crp_etype = EINVAL; -+ return EINVAL; -+ } -+ sessionData->sessHandle = -+ icp_kmalloc(sessionCtxSizeInBytes, ICP_M_NOWAIT); -+ if (NULL == sessionData->sessHandle) { -+ EPRINTK -+ ("%s(): Failed to get memory for SymSessionCtx\n", -+ __FUNCTION__); -+ crp->crp_etype = ENOMEM; -+ return ENOMEM; -+ } -+ -+ lacStatus = cpaCySymInitSession(CPA_INSTANCE_HANDLE_SINGLE, -+ icp_ocfDrvSymCallBack, -+ &(sessionData->lacSessCtx), -+ sessionData->sessHandle); -+ -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): cpaCySymInitSession failed -%d \n", -+ __FUNCTION__, lacStatus); -+ crp->crp_etype = EFAULT; -+ return EFAULT; -+ } -+ -+ sessionData->inUse = ICP_SESSION_RUNNING; -+ } -+ -+ drvOpData = icp_kmem_cache_zalloc(drvOpData_zone, ICP_M_NOWAIT); -+ if (NULL == drvOpData) { -+ EPRINTK("%s():Failed to get memory for drvOpData\n", -+ __FUNCTION__); -+ crp->crp_etype = ENOMEM; -+ return ENOMEM; -+ } -+ -+ drvOpData->lacOpData.pSessionCtx = sessionData->sessHandle; -+ drvOpData->digestSizeInBytes = sessionData->lacSessCtx.hashSetupData. -+ digestResultLenInBytes; -+ drvOpData->crp = crp; -+ -+ /* Set the default buffer list array memory allocation */ -+ drvOpData->srcBuffer.pBuffers = drvOpData->bufferListArray; -+ drvOpData->numBufferListArray = ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS; -+ -+ if (ICP_OCF_DRV_STATUS_SUCCESS != -+ icp_ocfDrvProcessDataSetup(drvOpData, drvOpData->crp->crp_desc)) { -+ crp->crp_etype = EINVAL; -+ goto err; -+ } -+ -+ if (drvOpData->crp->crp_desc->crd_next != NULL) { -+ if (icp_ocfDrvProcessDataSetup(drvOpData, drvOpData->crp-> -+ crp_desc->crd_next)) { -+ crp->crp_etype = EINVAL; -+ goto err; -+ } -+ -+ } -+ -+ /* -+ * Allocate buffer list array memory if the data fragment is more than -+ * the default number (ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) and not -+ * calculated already -+ */ -+ if (crp->crp_flags & ICP_CRYPTO_F_PACKET_BUF) { -+ if (NULL == drvOpData->lacOpData.pDigestResult) { -+ drvOpData->numBufferListArray = -+ icp_ocfDrvGetPacketBuffFrags((icp_packet_buffer_t *) -+ crp->crp_buf); -+ } -+ -+ if (ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS < -+ drvOpData->numBufferListArray) { -+ DPRINTK("%s() numBufferListArray more than default\n", -+ __FUNCTION__); -+ drvOpData->srcBuffer.pBuffers = NULL; -+ drvOpData->srcBuffer.pBuffers = -+ icp_kmalloc(drvOpData->numBufferListArray * -+ sizeof(CpaFlatBuffer), ICP_M_NOWAIT); -+ if (NULL == drvOpData->srcBuffer.pBuffers) { -+ EPRINTK("%s() Failed to get memory for " -+ "pBuffers\n", __FUNCTION__); -+ ICP_CACHE_FREE(drvOpData_zone, drvOpData); -+ crp->crp_etype = ENOMEM; -+ return ENOMEM; -+ } -+ } -+ } -+ -+ /* -+ * Check the type of buffer structure we got and convert it into -+ * CpaBufferList format. -+ */ -+ if (crp->crp_flags & ICP_CRYPTO_F_PACKET_BUF) { -+ if (ICP_OCF_DRV_STATUS_SUCCESS != -+ icp_ocfDrvPacketBuffToBufferList((icp_packet_buffer_t *) -+ crp->crp_buf, -+ &(drvOpData->srcBuffer))) { -+ EPRINTK("%s():Failed to translate from packet buffer " -+ "to bufferlist\n", __FUNCTION__); -+ crp->crp_etype = EINVAL; -+ goto err; -+ } -+ -+ drvOpData->bufferType = ICP_CRYPTO_F_PACKET_BUF; -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ /* OCF only supports IOV of one entry. */ -+ if (NUM_IOV_SUPPORTED == -+ ((struct uio *)(crp->crp_buf))->uio_iovcnt) { -+ -+ icp_ocfDrvPtrAndLenToBufferList(((struct uio *)(crp-> -+ crp_buf))-> -+ uio_iov[0].iov_base, -+ ((struct uio *)(crp-> -+ crp_buf))-> -+ uio_iov[0].iov_len, -+ &(drvOpData-> -+ srcBuffer)); -+ -+ drvOpData->bufferType = CRYPTO_F_IOV; -+ -+ } else { -+ DPRINTK("%s():Unable to handle IOVs with lengths of " -+ "greater than one!\n", __FUNCTION__); -+ crp->crp_etype = EINVAL; -+ goto err; -+ } -+ -+ } else { -+ icp_ocfDrvPtrAndLenToBufferList(crp->crp_buf, -+ crp->crp_ilen, -+ &(drvOpData->srcBuffer)); -+ -+ drvOpData->bufferType = CRYPTO_BUF_CONTIG; -+ } -+ -+ /* Allocate srcBuffer's private meta data */ -+ if (ICP_OCF_DRV_STATUS_SUCCESS != -+ icp_ocfDrvAllocMetaData(&(drvOpData->srcBuffer), drvOpData)) { -+ EPRINTK("%s() icp_ocfDrvAllocMetaData failed\n", __FUNCTION__); -+ memset(&(drvOpData->lacOpData), 0, sizeof(CpaCySymOpData)); -+ crp->crp_etype = EINVAL; -+ goto err; -+ } -+ -+ /* Perform "in-place" crypto operation */ -+ lacStatus = cpaCySymPerformOp(CPA_INSTANCE_HANDLE_SINGLE, -+ (void *)drvOpData, -+ &(drvOpData->lacOpData), -+ &(drvOpData->srcBuffer), -+ &(drvOpData->srcBuffer), -+ &(drvOpData->verifyResult)); -+ if (CPA_STATUS_RETRY == lacStatus) { -+ DPRINTK("%s(): cpaCySymPerformOp retry, lacStatus = %d\n", -+ __FUNCTION__, lacStatus); -+ memset(&(drvOpData->lacOpData), 0, sizeof(CpaCySymOpData)); -+ crp->crp_etype = ERESTART; -+ goto err; -+ } -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): cpaCySymPerformOp failed, lacStatus = %d\n", -+ __FUNCTION__, lacStatus); -+ memset(&(drvOpData->lacOpData), 0, sizeof(CpaCySymOpData)); -+ crp->crp_etype = EINVAL; -+ goto err; -+ } -+ -+ return 0; //OCF success status value -+ -+ err: -+ if (drvOpData->numBufferListArray > ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) { -+ icp_kfree(drvOpData->srcBuffer.pBuffers); -+ } -+ icp_ocfDrvFreeMetaData(&(drvOpData->srcBuffer)); -+ ICP_CACHE_FREE(drvOpData_zone, drvOpData); -+ -+ return crp->crp_etype; -+} -+ -+/* Name : icp_ocfDrvProcessDataSetup -+ * -+ * Description : This function will setup all the cryptographic operation data -+ * that is required by LAC to execute the operation. -+ */ -+static int icp_ocfDrvProcessDataSetup(struct icp_drvOpData *drvOpData, -+ struct cryptodesc *crp_desc) -+{ -+ CpaCyRandGenOpData randGenOpData; -+ CpaFlatBuffer randData; -+ -+ drvOpData->lacOpData.packetType = CPA_CY_SYM_PACKET_TYPE_FULL; -+ -+ /* Convert from the cryptop to the ICP LAC crypto parameters */ -+ switch (crp_desc->crd_alg) { -+ case CRYPTO_NULL_CBC: -+ drvOpData->lacOpData. -+ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; -+ drvOpData->lacOpData. -+ messageLenToCipherInBytes = crp_desc->crd_len; -+ drvOpData->verifyResult = CPA_FALSE; -+ drvOpData->lacOpData.ivLenInBytes = NULL_BLOCK_LEN; -+ break; -+ case CRYPTO_DES_CBC: -+ drvOpData->lacOpData. -+ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; -+ drvOpData->lacOpData. -+ messageLenToCipherInBytes = crp_desc->crd_len; -+ drvOpData->verifyResult = CPA_FALSE; -+ drvOpData->lacOpData.ivLenInBytes = DES_BLOCK_LEN; -+ break; -+ case CRYPTO_3DES_CBC: -+ drvOpData->lacOpData. -+ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; -+ drvOpData->lacOpData. -+ messageLenToCipherInBytes = crp_desc->crd_len; -+ drvOpData->verifyResult = CPA_FALSE; -+ drvOpData->lacOpData.ivLenInBytes = DES3_BLOCK_LEN; -+ break; -+ case CRYPTO_ARC4: -+ drvOpData->lacOpData. -+ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; -+ drvOpData->lacOpData. -+ messageLenToCipherInBytes = crp_desc->crd_len; -+ drvOpData->verifyResult = CPA_FALSE; -+ drvOpData->lacOpData.ivLenInBytes = ARC4_COUNTER_LEN; -+ break; -+ case CRYPTO_AES_CBC: -+ drvOpData->lacOpData. -+ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; -+ drvOpData->lacOpData. -+ messageLenToCipherInBytes = crp_desc->crd_len; -+ drvOpData->verifyResult = CPA_FALSE; -+ drvOpData->lacOpData.ivLenInBytes = RIJNDAEL128_BLOCK_LEN; -+ break; -+ case CRYPTO_SHA1: -+ case CRYPTO_SHA1_HMAC: -+ case CRYPTO_SHA2_256: -+ case CRYPTO_SHA2_256_HMAC: -+ case CRYPTO_SHA2_384: -+ case CRYPTO_SHA2_384_HMAC: -+ case CRYPTO_SHA2_512: -+ case CRYPTO_SHA2_512_HMAC: -+ case CRYPTO_MD5: -+ case CRYPTO_MD5_HMAC: -+ drvOpData->lacOpData. -+ hashStartSrcOffsetInBytes = crp_desc->crd_skip; -+ drvOpData->lacOpData. -+ messageLenToHashInBytes = crp_desc->crd_len; -+ drvOpData->lacOpData. -+ pDigestResult = -+ icp_ocfDrvDigestPointerFind(drvOpData, crp_desc); -+ -+ if (NULL == drvOpData->lacOpData.pDigestResult) { -+ DPRINTK("%s(): ERROR - could not calculate " -+ "Digest Result memory address\n", __FUNCTION__); -+ return ICP_OCF_DRV_STATUS_FAIL; -+ } -+ -+ drvOpData->lacOpData.digestVerify = CPA_FALSE; -+ break; -+ default: -+ DPRINTK("%s(): Crypto process error - algorithm not " -+ "found \n", __FUNCTION__); -+ return ICP_OCF_DRV_STATUS_FAIL; -+ } -+ -+ /* Figure out what the IV is supposed to be */ -+ if ((crp_desc->crd_alg == CRYPTO_DES_CBC) || -+ (crp_desc->crd_alg == CRYPTO_3DES_CBC) || -+ (crp_desc->crd_alg == CRYPTO_AES_CBC)) { -+ /*ARC4 doesn't use an IV */ -+ if (crp_desc->crd_flags & CRD_F_IV_EXPLICIT) { -+ /* Explicit IV provided to OCF */ -+ drvOpData->lacOpData.pIv = crp_desc->crd_iv; -+ } else { -+ /* IV is not explicitly provided to OCF */ -+ -+ /* Point the LAC OP Data IV pointer to our allocated -+ storage location for this session. */ -+ drvOpData->lacOpData.pIv = drvOpData->ivData; -+ -+ if ((crp_desc->crd_flags & CRD_F_ENCRYPT) && -+ ((crp_desc->crd_flags & CRD_F_IV_PRESENT) == 0)) { -+ -+ /* Encrypting - need to create IV */ -+ randGenOpData.generateBits = CPA_TRUE; -+ randGenOpData.lenInBytes = MAX_IV_LEN_IN_BYTES; -+ -+ icp_ocfDrvPtrAndLenToFlatBuffer((Cpa8U *) -+ drvOpData-> -+ ivData, -+ MAX_IV_LEN_IN_BYTES, -+ &randData); -+ -+ if (CPA_STATUS_SUCCESS != -+ cpaCyRandGen(CPA_INSTANCE_HANDLE_SINGLE, -+ NULL, NULL, -+ &randGenOpData, &randData)) { -+ DPRINTK("%s(): ERROR - Failed to" -+ " generate" -+ " Initialisation Vector\n", -+ __FUNCTION__); -+ return ICP_OCF_DRV_STATUS_FAIL; -+ } -+ -+ crypto_copyback(drvOpData->crp-> -+ crp_flags, -+ drvOpData->crp->crp_buf, -+ crp_desc->crd_inject, -+ drvOpData->lacOpData. -+ ivLenInBytes, -+ (caddr_t) (drvOpData->lacOpData. -+ pIv)); -+ } else { -+ /* Reading IV from buffer */ -+ crypto_copydata(drvOpData->crp-> -+ crp_flags, -+ drvOpData->crp->crp_buf, -+ crp_desc->crd_inject, -+ drvOpData->lacOpData. -+ ivLenInBytes, -+ (caddr_t) (drvOpData->lacOpData. -+ pIv)); -+ } -+ -+ } -+ -+ } -+ -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+} -+ -+/* Name : icp_ocfDrvDigestPointerFind -+ * -+ * Description : This function is used to find the memory address of where the -+ * digest information shall be stored in. Input buffer types are an skbuff, iov -+ * or flat buffer. The address is found using the buffer data start address and -+ * an offset. -+ * -+ * Note: In the case of a linux skbuff, the digest address may exist within -+ * a memory space linked to from the start buffer. These linked memory spaces -+ * must be traversed by the data length offset in order to find the digest start -+ * address. Whether there is enough space for the digest must also be checked. -+ */ -+uint8_t *icp_ocfDrvDigestPointerFind(struct icp_drvOpData * drvOpData, -+ struct cryptodesc * crp_desc) -+{ -+ -+ int offsetInBytes = crp_desc->crd_inject; -+ uint32_t digestSizeInBytes = drvOpData->digestSizeInBytes; -+ uint8_t *flat_buffer_base = NULL; -+ int flat_buffer_length = 0; -+ -+ if (drvOpData->crp->crp_flags & ICP_CRYPTO_F_PACKET_BUF) { -+ -+ return icp_ocfDrvPacketBufferDigestPointerFind(drvOpData, -+ offsetInBytes, -+ digestSizeInBytes); -+ -+ } else { -+ /* IOV or flat buffer */ -+ if (drvOpData->crp->crp_flags & CRYPTO_F_IOV) { -+ /*single IOV check has already been done */ -+ flat_buffer_base = ((struct uio *) -+ (drvOpData->crp->crp_buf))-> -+ uio_iov[0].iov_base; -+ flat_buffer_length = ((struct uio *) -+ (drvOpData->crp->crp_buf))-> -+ uio_iov[0].iov_len; -+ } else { -+ flat_buffer_base = (uint8_t *) drvOpData->crp->crp_buf; -+ flat_buffer_length = drvOpData->crp->crp_ilen; -+ } -+ -+ if (flat_buffer_length < (offsetInBytes + digestSizeInBytes)) { -+ DPRINTK("%s() Not enough space for Digest " -+ "(IOV/Flat Buffer) \n", __FUNCTION__); -+ return NULL; -+ } else { -+ return (uint8_t *) (flat_buffer_base + offsetInBytes); -+ } -+ } -+ DPRINTK("%s() Should not reach this point\n", __FUNCTION__); -+ return NULL; -+} -diff -Nur linux-2.6.36.orig/crypto/ocf/ep80579/Makefile linux-2.6.36/crypto/ocf/ep80579/Makefile ---- linux-2.6.36.orig/crypto/ocf/ep80579/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/ep80579/Makefile 2010-11-09 20:28:04.742495461 +0100 -@@ -0,0 +1,119 @@ -+######################################################################### -+# -+# Targets supported -+# all - builds everything and installs -+# install - identical to all -+# depend - build dependencies -+# clean - clears derived objects except the .depend files -+# distclean- clears all derived objects and the .depend file -+# -+# @par -+# This file is provided under a dual BSD/GPLv2 license. When using or -+# redistributing this file, you may do so under either license. -+# -+# GPL LICENSE SUMMARY -+# -+# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+# -+# This program is free software; you can redistribute it and/or modify -+# it under the terms of version 2 of the GNU General Public License as -+# published by the Free Software Foundation. -+# -+# This program is distributed in the hope that it will be useful, but -+# WITHOUT ANY WARRANTY; without even the implied warranty of -+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+# General Public License for more details. -+# -+# You should have received a copy of the GNU General Public License -+# along with this program; if not, write to the Free Software -+# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. -+# The full GNU General Public License is included in this distribution -+# in the file called LICENSE.GPL. -+# -+# Contact Information: -+# Intel Corporation -+# -+# BSD LICENSE -+# -+# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+# All rights reserved. -+# -+# Redistribution and use in source and binary forms, with or without -+# modification, are permitted provided that the following conditions -+# are met: -+# -+# * Redistributions of source code must retain the above copyright -+# notice, this list of conditions and the following disclaimer. -+# * Redistributions in binary form must reproduce the above copyright -+# notice, this list of conditions and the following disclaimer in -+# the documentation and/or other materials provided with the -+# distribution. -+# * Neither the name of Intel Corporation nor the names of its -+# contributors may be used to endorse or promote products derived -+# from this software without specific prior written permission. -+# -+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+# -+# -+# version: Security.L.1.0.2-229 -+############################################################################ -+ -+ -+####################Common variables and definitions######################## -+ -+ifndef ICP_ROOT -+$(warning ICP_ROOT is undefined. Please set the path to EP80579 release package directory \ -+ "-> setenv ICP_ROOT ") -+all fastdep: -+ : -+else -+ -+ifndef KERNEL_SOURCE_ROOT -+$(error KERNEL_SOURCE_ROOT is undefined. Please set the path to the kernel source directory \ -+ "-> setenv KERNEL_SOURCE_ROOT ") -+endif -+ -+# Ensure The ENV_DIR environmental var is defined. -+ifndef ICP_ENV_DIR -+$(error ICP_ENV_DIR is undefined. Please set the path to EP80579 driver environment.mk file \ -+ "-> setenv ICP_ENV_DIR ") -+endif -+ -+#Add your project environment Makefile -+include ${ICP_ENV_DIR}/environment.mk -+ -+#include the makefile with all the default and common Make variable definitions -+include ${ICP_BUILDSYSTEM_PATH}/build_files/common.mk -+ -+#Add the name for the executable, Library or Module output definitions -+OUTPUT_NAME= icp_ocf -+ -+# List of Source Files to be compiled -+SOURCES= icp_common.c icp_sym.c icp_asym.c icp_ocf_linux.c -+ -+#common includes between all supported OSes -+INCLUDES= -I ${ICP_API_DIR} -I${ICP_LAC_API} \ -+-I${ICP_OCF_SRC_DIR} -+ -+# The location of the os level makefile needs to be changed. -+include ${ICP_ENV_DIR}/${ICP_OS}_${ICP_OS_LEVEL}.mk -+ -+# On the line directly below list the outputs you wish to build for, -+# e.g "lib_static lib_shared exe module" as shown below -+install: module -+ -+###################Include rules makefiles######################## -+include ${ICP_BUILDSYSTEM_PATH}/build_files/rules.mk -+###################End of Rules inclusion######################### -+ -+endif -diff -Nur linux-2.6.36.orig/crypto/ocf/hifn/hifn7751.c linux-2.6.36/crypto/ocf/hifn/hifn7751.c ---- linux-2.6.36.orig/crypto/ocf/hifn/hifn7751.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/hifn/hifn7751.c 2010-11-09 20:28:04.752495537 +0100 -@@ -0,0 +1,2976 @@ -+/* $OpenBSD: hifn7751.c,v 1.120 2002/05/17 00:33:34 deraadt Exp $ */ -+ -+/*- -+ * Invertex AEON / Hifn 7751 driver -+ * Copyright (c) 1999 Invertex Inc. All rights reserved. -+ * Copyright (c) 1999 Theo de Raadt -+ * Copyright (c) 2000-2001 Network Security Technologies, Inc. -+ * http://www.netsec.net -+ * Copyright (c) 2003 Hifn Inc. -+ * -+ * This driver is based on a previous driver by Invertex, for which they -+ * requested: Please send any comments, feedback, bug-fixes, or feature -+ * requests to software@invertex.com. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored in part by the Defense Advanced Research Projects -+ * Agency (DARPA) and Air Force Research Laboratory, Air Force -+ * Materiel Command, USAF, under agreement number F30602-01-2-0537. -+ * -+ * -+__FBSDID("$FreeBSD: src/sys/dev/hifn/hifn7751.c,v 1.40 2007/03/21 03:42:49 sam Exp $"); -+ */ -+ -+/* -+ * Driver for various Hifn encryption processors. -+ */ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+ -+#if 1 -+#define DPRINTF(a...) if (hifn_debug) { \ -+ printk("%s: ", sc ? \ -+ device_get_nameunit(sc->sc_dev) : "hifn"); \ -+ printk(a); \ -+ } else -+#else -+#define DPRINTF(a...) -+#endif -+ -+static inline int -+pci_get_revid(struct pci_dev *dev) -+{ -+ u8 rid = 0; -+ pci_read_config_byte(dev, PCI_REVISION_ID, &rid); -+ return rid; -+} -+ -+static struct hifn_stats hifnstats; -+ -+#define debug hifn_debug -+int hifn_debug = 0; -+module_param(hifn_debug, int, 0644); -+MODULE_PARM_DESC(hifn_debug, "Enable debug"); -+ -+int hifn_maxbatch = 1; -+module_param(hifn_maxbatch, int, 0644); -+MODULE_PARM_DESC(hifn_maxbatch, "max ops to batch w/o interrupt"); -+ -+int hifn_cache_linesize = 0x10; -+module_param(hifn_cache_linesize, int, 0444); -+MODULE_PARM_DESC(hifn_cache_linesize, "PCI config cache line size"); -+ -+#ifdef MODULE_PARM -+char *hifn_pllconfig = NULL; -+MODULE_PARM(hifn_pllconfig, "s"); -+#else -+char hifn_pllconfig[32]; /* This setting is RO after loading */ -+module_param_string(hifn_pllconfig, hifn_pllconfig, 32, 0444); -+#endif -+MODULE_PARM_DESC(hifn_pllconfig, "PLL config, ie., pci66, ext33, ..."); -+ -+#ifdef HIFN_VULCANDEV -+#include -+#include -+ -+static struct cdevsw vulcanpk_cdevsw; /* forward declaration */ -+#endif -+ -+/* -+ * Prototypes and count for the pci_device structure -+ */ -+static int hifn_probe(struct pci_dev *dev, const struct pci_device_id *ent); -+static void hifn_remove(struct pci_dev *dev); -+ -+static int hifn_newsession(device_t, u_int32_t *, struct cryptoini *); -+static int hifn_freesession(device_t, u_int64_t); -+static int hifn_process(device_t, struct cryptop *, int); -+ -+static device_method_t hifn_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, hifn_newsession), -+ DEVMETHOD(cryptodev_freesession,hifn_freesession), -+ DEVMETHOD(cryptodev_process, hifn_process), -+}; -+ -+static void hifn_reset_board(struct hifn_softc *, int); -+static void hifn_reset_puc(struct hifn_softc *); -+static void hifn_puc_wait(struct hifn_softc *); -+static int hifn_enable_crypto(struct hifn_softc *); -+static void hifn_set_retry(struct hifn_softc *sc); -+static void hifn_init_dma(struct hifn_softc *); -+static void hifn_init_pci_registers(struct hifn_softc *); -+static int hifn_sramsize(struct hifn_softc *); -+static int hifn_dramsize(struct hifn_softc *); -+static int hifn_ramtype(struct hifn_softc *); -+static void hifn_sessions(struct hifn_softc *); -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) -+static irqreturn_t hifn_intr(int irq, void *arg); -+#else -+static irqreturn_t hifn_intr(int irq, void *arg, struct pt_regs *regs); -+#endif -+static u_int hifn_write_command(struct hifn_command *, u_int8_t *); -+static u_int32_t hifn_next_signature(u_int32_t a, u_int cnt); -+static void hifn_callback(struct hifn_softc *, struct hifn_command *, u_int8_t *); -+static int hifn_crypto(struct hifn_softc *, struct hifn_command *, struct cryptop *, int); -+static int hifn_readramaddr(struct hifn_softc *, int, u_int8_t *); -+static int hifn_writeramaddr(struct hifn_softc *, int, u_int8_t *); -+static int hifn_dmamap_load_src(struct hifn_softc *, struct hifn_command *); -+static int hifn_dmamap_load_dst(struct hifn_softc *, struct hifn_command *); -+static int hifn_init_pubrng(struct hifn_softc *); -+static void hifn_tick(unsigned long arg); -+static void hifn_abort(struct hifn_softc *); -+static void hifn_alloc_slot(struct hifn_softc *, int *, int *, int *, int *); -+ -+static void hifn_write_reg_0(struct hifn_softc *, bus_size_t, u_int32_t); -+static void hifn_write_reg_1(struct hifn_softc *, bus_size_t, u_int32_t); -+ -+#ifdef CONFIG_OCF_RANDOMHARVEST -+static int hifn_read_random(void *arg, u_int32_t *buf, int len); -+#endif -+ -+#define HIFN_MAX_CHIPS 8 -+static struct hifn_softc *hifn_chip_idx[HIFN_MAX_CHIPS]; -+ -+static __inline u_int32_t -+READ_REG_0(struct hifn_softc *sc, bus_size_t reg) -+{ -+ u_int32_t v = readl(sc->sc_bar0 + reg); -+ sc->sc_bar0_lastreg = (bus_size_t) -1; -+ return (v); -+} -+#define WRITE_REG_0(sc, reg, val) hifn_write_reg_0(sc, reg, val) -+ -+static __inline u_int32_t -+READ_REG_1(struct hifn_softc *sc, bus_size_t reg) -+{ -+ u_int32_t v = readl(sc->sc_bar1 + reg); -+ sc->sc_bar1_lastreg = (bus_size_t) -1; -+ return (v); -+} -+#define WRITE_REG_1(sc, reg, val) hifn_write_reg_1(sc, reg, val) -+ -+/* -+ * map in a given buffer (great on some arches :-) -+ */ -+ -+static int -+pci_map_uio(struct hifn_softc *sc, struct hifn_operand *buf, struct uio *uio) -+{ -+ struct iovec *iov = uio->uio_iov; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ buf->mapsize = 0; -+ for (buf->nsegs = 0; buf->nsegs < uio->uio_iovcnt; ) { -+ buf->segs[buf->nsegs].ds_addr = pci_map_single(sc->sc_pcidev, -+ iov->iov_base, iov->iov_len, -+ PCI_DMA_BIDIRECTIONAL); -+ buf->segs[buf->nsegs].ds_len = iov->iov_len; -+ buf->mapsize += iov->iov_len; -+ iov++; -+ buf->nsegs++; -+ } -+ /* identify this buffer by the first segment */ -+ buf->map = (void *) buf->segs[0].ds_addr; -+ return(0); -+} -+ -+/* -+ * map in a given sk_buff -+ */ -+ -+static int -+pci_map_skb(struct hifn_softc *sc,struct hifn_operand *buf,struct sk_buff *skb) -+{ -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ buf->mapsize = 0; -+ -+ buf->segs[0].ds_addr = pci_map_single(sc->sc_pcidev, -+ skb->data, skb_headlen(skb), PCI_DMA_BIDIRECTIONAL); -+ buf->segs[0].ds_len = skb_headlen(skb); -+ buf->mapsize += buf->segs[0].ds_len; -+ -+ buf->nsegs = 1; -+ -+ for (i = 0; i < skb_shinfo(skb)->nr_frags; ) { -+ buf->segs[buf->nsegs].ds_len = skb_shinfo(skb)->frags[i].size; -+ buf->segs[buf->nsegs].ds_addr = pci_map_single(sc->sc_pcidev, -+ page_address(skb_shinfo(skb)->frags[i].page) + -+ skb_shinfo(skb)->frags[i].page_offset, -+ buf->segs[buf->nsegs].ds_len, PCI_DMA_BIDIRECTIONAL); -+ buf->mapsize += buf->segs[buf->nsegs].ds_len; -+ buf->nsegs++; -+ } -+ -+ /* identify this buffer by the first segment */ -+ buf->map = (void *) buf->segs[0].ds_addr; -+ return(0); -+} -+ -+/* -+ * map in a given contiguous buffer -+ */ -+ -+static int -+pci_map_buf(struct hifn_softc *sc,struct hifn_operand *buf, void *b, int len) -+{ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ buf->mapsize = 0; -+ buf->segs[0].ds_addr = pci_map_single(sc->sc_pcidev, -+ b, len, PCI_DMA_BIDIRECTIONAL); -+ buf->segs[0].ds_len = len; -+ buf->mapsize += buf->segs[0].ds_len; -+ buf->nsegs = 1; -+ -+ /* identify this buffer by the first segment */ -+ buf->map = (void *) buf->segs[0].ds_addr; -+ return(0); -+} -+ -+#if 0 /* not needed at this time */ -+static void -+pci_sync_iov(struct hifn_softc *sc, struct hifn_operand *buf) -+{ -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ for (i = 0; i < buf->nsegs; i++) -+ pci_dma_sync_single_for_cpu(sc->sc_pcidev, buf->segs[i].ds_addr, -+ buf->segs[i].ds_len, PCI_DMA_BIDIRECTIONAL); -+} -+#endif -+ -+static void -+pci_unmap_buf(struct hifn_softc *sc, struct hifn_operand *buf) -+{ -+ int i; -+ DPRINTF("%s()\n", __FUNCTION__); -+ for (i = 0; i < buf->nsegs; i++) { -+ pci_unmap_single(sc->sc_pcidev, buf->segs[i].ds_addr, -+ buf->segs[i].ds_len, PCI_DMA_BIDIRECTIONAL); -+ buf->segs[i].ds_addr = 0; -+ buf->segs[i].ds_len = 0; -+ } -+ buf->nsegs = 0; -+ buf->mapsize = 0; -+ buf->map = 0; -+} -+ -+static const char* -+hifn_partname(struct hifn_softc *sc) -+{ -+ /* XXX sprintf numbers when not decoded */ -+ switch (pci_get_vendor(sc->sc_pcidev)) { -+ case PCI_VENDOR_HIFN: -+ switch (pci_get_device(sc->sc_pcidev)) { -+ case PCI_PRODUCT_HIFN_6500: return "Hifn 6500"; -+ case PCI_PRODUCT_HIFN_7751: return "Hifn 7751"; -+ case PCI_PRODUCT_HIFN_7811: return "Hifn 7811"; -+ case PCI_PRODUCT_HIFN_7951: return "Hifn 7951"; -+ case PCI_PRODUCT_HIFN_7955: return "Hifn 7955"; -+ case PCI_PRODUCT_HIFN_7956: return "Hifn 7956"; -+ } -+ return "Hifn unknown-part"; -+ case PCI_VENDOR_INVERTEX: -+ switch (pci_get_device(sc->sc_pcidev)) { -+ case PCI_PRODUCT_INVERTEX_AEON: return "Invertex AEON"; -+ } -+ return "Invertex unknown-part"; -+ case PCI_VENDOR_NETSEC: -+ switch (pci_get_device(sc->sc_pcidev)) { -+ case PCI_PRODUCT_NETSEC_7751: return "NetSec 7751"; -+ } -+ return "NetSec unknown-part"; -+ } -+ return "Unknown-vendor unknown-part"; -+} -+ -+static u_int -+checkmaxmin(struct pci_dev *dev, const char *what, u_int v, u_int min, u_int max) -+{ -+ struct hifn_softc *sc = pci_get_drvdata(dev); -+ if (v > max) { -+ device_printf(sc->sc_dev, "Warning, %s %u out of range, " -+ "using max %u\n", what, v, max); -+ v = max; -+ } else if (v < min) { -+ device_printf(sc->sc_dev, "Warning, %s %u out of range, " -+ "using min %u\n", what, v, min); -+ v = min; -+ } -+ return v; -+} -+ -+/* -+ * Select PLL configuration for 795x parts. This is complicated in -+ * that we cannot determine the optimal parameters without user input. -+ * The reference clock is derived from an external clock through a -+ * multiplier. The external clock is either the host bus (i.e. PCI) -+ * or an external clock generator. When using the PCI bus we assume -+ * the clock is either 33 or 66 MHz; for an external source we cannot -+ * tell the speed. -+ * -+ * PLL configuration is done with a string: "pci" for PCI bus, or "ext" -+ * for an external source, followed by the frequency. We calculate -+ * the appropriate multiplier and PLL register contents accordingly. -+ * When no configuration is given we default to "pci66" since that -+ * always will allow the card to work. If a card is using the PCI -+ * bus clock and in a 33MHz slot then it will be operating at half -+ * speed until the correct information is provided. -+ * -+ * We use a default setting of "ext66" because according to Mike Ham -+ * of HiFn, almost every board in existence has an external crystal -+ * populated at 66Mhz. Using PCI can be a problem on modern motherboards, -+ * because PCI33 can have clocks from 0 to 33Mhz, and some have -+ * non-PCI-compliant spread-spectrum clocks, which can confuse the pll. -+ */ -+static void -+hifn_getpllconfig(struct pci_dev *dev, u_int *pll) -+{ -+ const char *pllspec = hifn_pllconfig; -+ u_int freq, mul, fl, fh; -+ u_int32_t pllconfig; -+ char *nxt; -+ -+ if (pllspec == NULL) -+ pllspec = "ext66"; -+ fl = 33, fh = 66; -+ pllconfig = 0; -+ if (strncmp(pllspec, "ext", 3) == 0) { -+ pllspec += 3; -+ pllconfig |= HIFN_PLL_REF_SEL; -+ switch (pci_get_device(dev)) { -+ case PCI_PRODUCT_HIFN_7955: -+ case PCI_PRODUCT_HIFN_7956: -+ fl = 20, fh = 100; -+ break; -+#ifdef notyet -+ case PCI_PRODUCT_HIFN_7954: -+ fl = 20, fh = 66; -+ break; -+#endif -+ } -+ } else if (strncmp(pllspec, "pci", 3) == 0) -+ pllspec += 3; -+ freq = strtoul(pllspec, &nxt, 10); -+ if (nxt == pllspec) -+ freq = 66; -+ else -+ freq = checkmaxmin(dev, "frequency", freq, fl, fh); -+ /* -+ * Calculate multiplier. We target a Fck of 266 MHz, -+ * allowing only even values, possibly rounded down. -+ * Multipliers > 8 must set the charge pump current. -+ */ -+ mul = checkmaxmin(dev, "PLL divisor", (266 / freq) &~ 1, 2, 12); -+ pllconfig |= (mul / 2 - 1) << HIFN_PLL_ND_SHIFT; -+ if (mul > 8) -+ pllconfig |= HIFN_PLL_IS; -+ *pll = pllconfig; -+} -+ -+/* -+ * Attach an interface that successfully probed. -+ */ -+static int -+hifn_probe(struct pci_dev *dev, const struct pci_device_id *ent) -+{ -+ struct hifn_softc *sc = NULL; -+ char rbase; -+ u_int16_t ena, rev; -+ int rseg, rc; -+ unsigned long mem_start, mem_len; -+ static int num_chips = 0; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (pci_enable_device(dev) < 0) -+ return(-ENODEV); -+ -+ if (pci_set_mwi(dev)) -+ return(-ENODEV); -+ -+ if (!dev->irq) { -+ printk("hifn: found device with no IRQ assigned. check BIOS settings!"); -+ pci_disable_device(dev); -+ return(-ENODEV); -+ } -+ -+ sc = (struct hifn_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); -+ if (!sc) -+ return(-ENOMEM); -+ memset(sc, 0, sizeof(*sc)); -+ -+ softc_device_init(sc, "hifn", num_chips, hifn_methods); -+ -+ sc->sc_pcidev = dev; -+ sc->sc_irq = -1; -+ sc->sc_cid = -1; -+ sc->sc_num = num_chips++; -+ if (sc->sc_num < HIFN_MAX_CHIPS) -+ hifn_chip_idx[sc->sc_num] = sc; -+ -+ pci_set_drvdata(sc->sc_pcidev, sc); -+ -+ spin_lock_init(&sc->sc_mtx); -+ -+ /* XXX handle power management */ -+ -+ /* -+ * The 7951 and 795x have a random number generator and -+ * public key support; note this. -+ */ -+ if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && -+ (pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 || -+ pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 || -+ pci_get_device(dev) == PCI_PRODUCT_HIFN_7956)) -+ sc->sc_flags = HIFN_HAS_RNG | HIFN_HAS_PUBLIC; -+ /* -+ * The 7811 has a random number generator and -+ * we also note it's identity 'cuz of some quirks. -+ */ -+ if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && -+ pci_get_device(dev) == PCI_PRODUCT_HIFN_7811) -+ sc->sc_flags |= HIFN_IS_7811 | HIFN_HAS_RNG; -+ -+ /* -+ * The 795x parts support AES. -+ */ -+ if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && -+ (pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 || -+ pci_get_device(dev) == PCI_PRODUCT_HIFN_7956)) { -+ sc->sc_flags |= HIFN_IS_7956 | HIFN_HAS_AES; -+ /* -+ * Select PLL configuration. This depends on the -+ * bus and board design and must be manually configured -+ * if the default setting is unacceptable. -+ */ -+ hifn_getpllconfig(dev, &sc->sc_pllconfig); -+ } -+ -+ /* -+ * Setup PCI resources. Note that we record the bus -+ * tag and handle for each register mapping, this is -+ * used by the READ_REG_0, WRITE_REG_0, READ_REG_1, -+ * and WRITE_REG_1 macros throughout the driver. -+ */ -+ mem_start = pci_resource_start(sc->sc_pcidev, 0); -+ mem_len = pci_resource_len(sc->sc_pcidev, 0); -+ sc->sc_bar0 = (ocf_iomem_t) ioremap(mem_start, mem_len); -+ if (!sc->sc_bar0) { -+ device_printf(sc->sc_dev, "cannot map bar%d register space\n", 0); -+ goto fail; -+ } -+ sc->sc_bar0_lastreg = (bus_size_t) -1; -+ -+ mem_start = pci_resource_start(sc->sc_pcidev, 1); -+ mem_len = pci_resource_len(sc->sc_pcidev, 1); -+ sc->sc_bar1 = (ocf_iomem_t) ioremap(mem_start, mem_len); -+ if (!sc->sc_bar1) { -+ device_printf(sc->sc_dev, "cannot map bar%d register space\n", 1); -+ goto fail; -+ } -+ sc->sc_bar1_lastreg = (bus_size_t) -1; -+ -+ /* fix up the bus size */ -+ if (pci_set_dma_mask(dev, DMA_32BIT_MASK)) { -+ device_printf(sc->sc_dev, "No usable DMA configuration, aborting.\n"); -+ goto fail; -+ } -+ if (pci_set_consistent_dma_mask(dev, DMA_32BIT_MASK)) { -+ device_printf(sc->sc_dev, -+ "No usable consistent DMA configuration, aborting.\n"); -+ goto fail; -+ } -+ -+ hifn_set_retry(sc); -+ -+ /* -+ * Setup the area where the Hifn DMA's descriptors -+ * and associated data structures. -+ */ -+ sc->sc_dma = (struct hifn_dma *) pci_alloc_consistent(dev, -+ sizeof(*sc->sc_dma), -+ &sc->sc_dma_physaddr); -+ if (!sc->sc_dma) { -+ device_printf(sc->sc_dev, "cannot alloc sc_dma\n"); -+ goto fail; -+ } -+ bzero(sc->sc_dma, sizeof(*sc->sc_dma)); -+ -+ /* -+ * Reset the board and do the ``secret handshake'' -+ * to enable the crypto support. Then complete the -+ * initialization procedure by setting up the interrupt -+ * and hooking in to the system crypto support so we'll -+ * get used for system services like the crypto device, -+ * IPsec, RNG device, etc. -+ */ -+ hifn_reset_board(sc, 0); -+ -+ if (hifn_enable_crypto(sc) != 0) { -+ device_printf(sc->sc_dev, "crypto enabling failed\n"); -+ goto fail; -+ } -+ hifn_reset_puc(sc); -+ -+ hifn_init_dma(sc); -+ hifn_init_pci_registers(sc); -+ -+ pci_set_master(sc->sc_pcidev); -+ -+ /* XXX can't dynamically determine ram type for 795x; force dram */ -+ if (sc->sc_flags & HIFN_IS_7956) -+ sc->sc_drammodel = 1; -+ else if (hifn_ramtype(sc)) -+ goto fail; -+ -+ if (sc->sc_drammodel == 0) -+ hifn_sramsize(sc); -+ else -+ hifn_dramsize(sc); -+ -+ /* -+ * Workaround for NetSec 7751 rev A: half ram size because two -+ * of the address lines were left floating -+ */ -+ if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC && -+ pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751 && -+ pci_get_revid(dev) == 0x61) /*XXX???*/ -+ sc->sc_ramsize >>= 1; -+ -+ /* -+ * Arrange the interrupt line. -+ */ -+ rc = request_irq(dev->irq, hifn_intr, IRQF_SHARED, "hifn", sc); -+ if (rc) { -+ device_printf(sc->sc_dev, "could not map interrupt: %d\n", rc); -+ goto fail; -+ } -+ sc->sc_irq = dev->irq; -+ -+ hifn_sessions(sc); -+ -+ /* -+ * NB: Keep only the low 16 bits; this masks the chip id -+ * from the 7951. -+ */ -+ rev = READ_REG_1(sc, HIFN_1_REVID) & 0xffff; -+ -+ rseg = sc->sc_ramsize / 1024; -+ rbase = 'K'; -+ if (sc->sc_ramsize >= (1024 * 1024)) { -+ rbase = 'M'; -+ rseg /= 1024; -+ } -+ device_printf(sc->sc_dev, "%s, rev %u, %d%cB %cram", -+ hifn_partname(sc), rev, -+ rseg, rbase, sc->sc_drammodel ? 'd' : 's'); -+ if (sc->sc_flags & HIFN_IS_7956) -+ printf(", pll=0x%x<%s clk, %ux mult>", -+ sc->sc_pllconfig, -+ sc->sc_pllconfig & HIFN_PLL_REF_SEL ? "ext" : "pci", -+ 2 + 2*((sc->sc_pllconfig & HIFN_PLL_ND) >> 11)); -+ printf("\n"); -+ -+ sc->sc_cid = crypto_get_driverid(softc_get_device(sc),CRYPTOCAP_F_HARDWARE); -+ if (sc->sc_cid < 0) { -+ device_printf(sc->sc_dev, "could not get crypto driver id\n"); -+ goto fail; -+ } -+ -+ WRITE_REG_0(sc, HIFN_0_PUCNFG, -+ READ_REG_0(sc, HIFN_0_PUCNFG) | HIFN_PUCNFG_CHIPID); -+ ena = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; -+ -+ switch (ena) { -+ case HIFN_PUSTAT_ENA_2: -+ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0); -+ if (sc->sc_flags & HIFN_HAS_AES) -+ crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); -+ /*FALLTHROUGH*/ -+ case HIFN_PUSTAT_ENA_1: -+ crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); -+ break; -+ } -+ -+ if (sc->sc_flags & (HIFN_HAS_PUBLIC | HIFN_HAS_RNG)) -+ hifn_init_pubrng(sc); -+ -+ init_timer(&sc->sc_tickto); -+ sc->sc_tickto.function = hifn_tick; -+ sc->sc_tickto.data = (unsigned long) sc->sc_num; -+ mod_timer(&sc->sc_tickto, jiffies + HZ); -+ -+ return (0); -+ -+fail: -+ if (sc->sc_cid >= 0) -+ crypto_unregister_all(sc->sc_cid); -+ if (sc->sc_irq != -1) -+ free_irq(sc->sc_irq, sc); -+ if (sc->sc_dma) { -+ /* Turn off DMA polling */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | -+ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); -+ -+ pci_free_consistent(sc->sc_pcidev, -+ sizeof(*sc->sc_dma), -+ sc->sc_dma, sc->sc_dma_physaddr); -+ } -+ kfree(sc); -+ return (-ENXIO); -+} -+ -+/* -+ * Detach an interface that successfully probed. -+ */ -+static void -+hifn_remove(struct pci_dev *dev) -+{ -+ struct hifn_softc *sc = pci_get_drvdata(dev); -+ unsigned long l_flags; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ KASSERT(sc != NULL, ("hifn_detach: null software carrier!")); -+ -+ /* disable interrupts */ -+ HIFN_LOCK(sc); -+ WRITE_REG_1(sc, HIFN_1_DMA_IER, 0); -+ HIFN_UNLOCK(sc); -+ -+ /*XXX other resources */ -+ del_timer_sync(&sc->sc_tickto); -+ -+ /* Turn off DMA polling */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | -+ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); -+ -+ crypto_unregister_all(sc->sc_cid); -+ -+ free_irq(sc->sc_irq, sc); -+ -+ pci_free_consistent(sc->sc_pcidev, sizeof(*sc->sc_dma), -+ sc->sc_dma, sc->sc_dma_physaddr); -+} -+ -+ -+static int -+hifn_init_pubrng(struct hifn_softc *sc) -+{ -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if ((sc->sc_flags & HIFN_IS_7811) == 0) { -+ /* Reset 7951 public key/rng engine */ -+ WRITE_REG_1(sc, HIFN_1_PUB_RESET, -+ READ_REG_1(sc, HIFN_1_PUB_RESET) | HIFN_PUBRST_RESET); -+ -+ for (i = 0; i < 100; i++) { -+ DELAY(1000); -+ if ((READ_REG_1(sc, HIFN_1_PUB_RESET) & -+ HIFN_PUBRST_RESET) == 0) -+ break; -+ } -+ -+ if (i == 100) { -+ device_printf(sc->sc_dev, "public key init failed\n"); -+ return (1); -+ } -+ } -+ -+ /* Enable the rng, if available */ -+#ifdef CONFIG_OCF_RANDOMHARVEST -+ if (sc->sc_flags & HIFN_HAS_RNG) { -+ if (sc->sc_flags & HIFN_IS_7811) { -+ u_int32_t r; -+ r = READ_REG_1(sc, HIFN_1_7811_RNGENA); -+ if (r & HIFN_7811_RNGENA_ENA) { -+ r &= ~HIFN_7811_RNGENA_ENA; -+ WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); -+ } -+ WRITE_REG_1(sc, HIFN_1_7811_RNGCFG, -+ HIFN_7811_RNGCFG_DEFL); -+ r |= HIFN_7811_RNGENA_ENA; -+ WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); -+ } else -+ WRITE_REG_1(sc, HIFN_1_RNG_CONFIG, -+ READ_REG_1(sc, HIFN_1_RNG_CONFIG) | -+ HIFN_RNGCFG_ENA); -+ -+ sc->sc_rngfirst = 1; -+ crypto_rregister(sc->sc_cid, hifn_read_random, sc); -+ } -+#endif -+ -+ /* Enable public key engine, if available */ -+ if (sc->sc_flags & HIFN_HAS_PUBLIC) { -+ WRITE_REG_1(sc, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE); -+ sc->sc_dmaier |= HIFN_DMAIER_PUBDONE; -+ WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); -+#ifdef HIFN_VULCANDEV -+ sc->sc_pkdev = make_dev(&vulcanpk_cdevsw, 0, -+ UID_ROOT, GID_WHEEL, 0666, -+ "vulcanpk"); -+ sc->sc_pkdev->si_drv1 = sc; -+#endif -+ } -+ -+ return (0); -+} -+ -+#ifdef CONFIG_OCF_RANDOMHARVEST -+static int -+hifn_read_random(void *arg, u_int32_t *buf, int len) -+{ -+ struct hifn_softc *sc = (struct hifn_softc *) arg; -+ u_int32_t sts; -+ int i, rc = 0; -+ -+ if (len <= 0) -+ return rc; -+ -+ if (sc->sc_flags & HIFN_IS_7811) { -+ /* ONLY VALID ON 7811!!!! */ -+ for (i = 0; i < 5; i++) { -+ sts = READ_REG_1(sc, HIFN_1_7811_RNGSTS); -+ if (sts & HIFN_7811_RNGSTS_UFL) { -+ device_printf(sc->sc_dev, -+ "RNG underflow: disabling\n"); -+ /* DAVIDM perhaps return -1 */ -+ break; -+ } -+ if ((sts & HIFN_7811_RNGSTS_RDY) == 0) -+ break; -+ -+ /* -+ * There are at least two words in the RNG FIFO -+ * at this point. -+ */ -+ if (rc < len) -+ buf[rc++] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); -+ if (rc < len) -+ buf[rc++] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); -+ } -+ } else -+ buf[rc++] = READ_REG_1(sc, HIFN_1_RNG_DATA); -+ -+ /* NB: discard first data read */ -+ if (sc->sc_rngfirst) { -+ sc->sc_rngfirst = 0; -+ rc = 0; -+ } -+ -+ return(rc); -+} -+#endif /* CONFIG_OCF_RANDOMHARVEST */ -+ -+static void -+hifn_puc_wait(struct hifn_softc *sc) -+{ -+ int i; -+ int reg = HIFN_0_PUCTRL; -+ -+ if (sc->sc_flags & HIFN_IS_7956) { -+ reg = HIFN_0_PUCTRL2; -+ } -+ -+ for (i = 5000; i > 0; i--) { -+ DELAY(1); -+ if (!(READ_REG_0(sc, reg) & HIFN_PUCTRL_RESET)) -+ break; -+ } -+ if (!i) -+ device_printf(sc->sc_dev, "proc unit did not reset(0x%x)\n", -+ READ_REG_0(sc, HIFN_0_PUCTRL)); -+} -+ -+/* -+ * Reset the processing unit. -+ */ -+static void -+hifn_reset_puc(struct hifn_softc *sc) -+{ -+ /* Reset processing unit */ -+ int reg = HIFN_0_PUCTRL; -+ -+ if (sc->sc_flags & HIFN_IS_7956) { -+ reg = HIFN_0_PUCTRL2; -+ } -+ WRITE_REG_0(sc, reg, HIFN_PUCTRL_DMAENA); -+ -+ hifn_puc_wait(sc); -+} -+ -+/* -+ * Set the Retry and TRDY registers; note that we set them to -+ * zero because the 7811 locks up when forced to retry (section -+ * 3.6 of "Specification Update SU-0014-04". Not clear if we -+ * should do this for all Hifn parts, but it doesn't seem to hurt. -+ */ -+static void -+hifn_set_retry(struct hifn_softc *sc) -+{ -+ DPRINTF("%s()\n", __FUNCTION__); -+ /* NB: RETRY only responds to 8-bit reads/writes */ -+ pci_write_config_byte(sc->sc_pcidev, HIFN_RETRY_TIMEOUT, 0); -+ pci_write_config_dword(sc->sc_pcidev, HIFN_TRDY_TIMEOUT, 0); -+ /* piggy back the cache line setting here */ -+ pci_write_config_byte(sc->sc_pcidev, PCI_CACHE_LINE_SIZE, hifn_cache_linesize); -+} -+ -+/* -+ * Resets the board. Values in the regesters are left as is -+ * from the reset (i.e. initial values are assigned elsewhere). -+ */ -+static void -+hifn_reset_board(struct hifn_softc *sc, int full) -+{ -+ u_int32_t reg; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ /* -+ * Set polling in the DMA configuration register to zero. 0x7 avoids -+ * resetting the board and zeros out the other fields. -+ */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | -+ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); -+ -+ /* -+ * Now that polling has been disabled, we have to wait 1 ms -+ * before resetting the board. -+ */ -+ DELAY(1000); -+ -+ /* Reset the DMA unit */ -+ if (full) { -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE); -+ DELAY(1000); -+ } else { -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, -+ HIFN_DMACNFG_MODE | HIFN_DMACNFG_MSTRESET); -+ hifn_reset_puc(sc); -+ } -+ -+ KASSERT(sc->sc_dma != NULL, ("hifn_reset_board: null DMA tag!")); -+ bzero(sc->sc_dma, sizeof(*sc->sc_dma)); -+ -+ /* Bring dma unit out of reset */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | -+ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); -+ -+ hifn_puc_wait(sc); -+ hifn_set_retry(sc); -+ -+ if (sc->sc_flags & HIFN_IS_7811) { -+ for (reg = 0; reg < 1000; reg++) { -+ if (READ_REG_1(sc, HIFN_1_7811_MIPSRST) & -+ HIFN_MIPSRST_CRAMINIT) -+ break; -+ DELAY(1000); -+ } -+ if (reg == 1000) -+ device_printf(sc->sc_dev, ": cram init timeout\n"); -+ } else { -+ /* set up DMA configuration register #2 */ -+ /* turn off all PK and BAR0 swaps */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG2, -+ (3 << HIFN_DMACNFG2_INIT_WRITE_BURST_SHIFT)| -+ (3 << HIFN_DMACNFG2_INIT_READ_BURST_SHIFT)| -+ (2 << HIFN_DMACNFG2_TGT_WRITE_BURST_SHIFT)| -+ (2 << HIFN_DMACNFG2_TGT_READ_BURST_SHIFT)); -+ } -+} -+ -+static u_int32_t -+hifn_next_signature(u_int32_t a, u_int cnt) -+{ -+ int i; -+ u_int32_t v; -+ -+ for (i = 0; i < cnt; i++) { -+ -+ /* get the parity */ -+ v = a & 0x80080125; -+ v ^= v >> 16; -+ v ^= v >> 8; -+ v ^= v >> 4; -+ v ^= v >> 2; -+ v ^= v >> 1; -+ -+ a = (v & 1) ^ (a << 1); -+ } -+ -+ return a; -+} -+ -+ -+/* -+ * Checks to see if crypto is already enabled. If crypto isn't enable, -+ * "hifn_enable_crypto" is called to enable it. The check is important, -+ * as enabling crypto twice will lock the board. -+ */ -+static int -+hifn_enable_crypto(struct hifn_softc *sc) -+{ -+ u_int32_t dmacfg, ramcfg, encl, addr, i; -+ char offtbl[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00 }; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ ramcfg = READ_REG_0(sc, HIFN_0_PUCNFG); -+ dmacfg = READ_REG_1(sc, HIFN_1_DMA_CNFG); -+ -+ /* -+ * The RAM config register's encrypt level bit needs to be set before -+ * every read performed on the encryption level register. -+ */ -+ WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); -+ -+ encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; -+ -+ /* -+ * Make sure we don't re-unlock. Two unlocks kills chip until the -+ * next reboot. -+ */ -+ if (encl == HIFN_PUSTAT_ENA_1 || encl == HIFN_PUSTAT_ENA_2) { -+#ifdef HIFN_DEBUG -+ if (hifn_debug) -+ device_printf(sc->sc_dev, -+ "Strong crypto already enabled!\n"); -+#endif -+ goto report; -+ } -+ -+ if (encl != 0 && encl != HIFN_PUSTAT_ENA_0) { -+#ifdef HIFN_DEBUG -+ if (hifn_debug) -+ device_printf(sc->sc_dev, -+ "Unknown encryption level 0x%x\n", encl); -+#endif -+ return 1; -+ } -+ -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_UNLOCK | -+ HIFN_DMACNFG_MSTRESET | HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); -+ DELAY(1000); -+ addr = READ_REG_1(sc, HIFN_UNLOCK_SECRET1); -+ DELAY(1000); -+ WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, 0); -+ DELAY(1000); -+ -+ for (i = 0; i <= 12; i++) { -+ addr = hifn_next_signature(addr, offtbl[i] + 0x101); -+ WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, addr); -+ -+ DELAY(1000); -+ } -+ -+ WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); -+ encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; -+ -+#ifdef HIFN_DEBUG -+ if (hifn_debug) { -+ if (encl != HIFN_PUSTAT_ENA_1 && encl != HIFN_PUSTAT_ENA_2) -+ device_printf(sc->sc_dev, "Engine is permanently " -+ "locked until next system reset!\n"); -+ else -+ device_printf(sc->sc_dev, "Engine enabled " -+ "successfully!\n"); -+ } -+#endif -+ -+report: -+ WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg); -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, dmacfg); -+ -+ switch (encl) { -+ case HIFN_PUSTAT_ENA_1: -+ case HIFN_PUSTAT_ENA_2: -+ break; -+ case HIFN_PUSTAT_ENA_0: -+ default: -+ device_printf(sc->sc_dev, "disabled\n"); -+ break; -+ } -+ -+ return 0; -+} -+ -+/* -+ * Give initial values to the registers listed in the "Register Space" -+ * section of the HIFN Software Development reference manual. -+ */ -+static void -+hifn_init_pci_registers(struct hifn_softc *sc) -+{ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ /* write fixed values needed by the Initialization registers */ -+ WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA); -+ WRITE_REG_0(sc, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD); -+ WRITE_REG_0(sc, HIFN_0_PUIER, HIFN_PUIER_DSTOVER); -+ -+ /* write all 4 ring address registers */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CRAR, sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, cmdr[0])); -+ WRITE_REG_1(sc, HIFN_1_DMA_SRAR, sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, srcr[0])); -+ WRITE_REG_1(sc, HIFN_1_DMA_DRAR, sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, dstr[0])); -+ WRITE_REG_1(sc, HIFN_1_DMA_RRAR, sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, resr[0])); -+ -+ DELAY(2000); -+ -+ /* write status register */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CSR, -+ HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS | -+ HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS | -+ HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST | -+ HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER | -+ HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST | -+ HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER | -+ HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST | -+ HIFN_DMACSR_S_WAIT | -+ HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST | -+ HIFN_DMACSR_C_WAIT | -+ HIFN_DMACSR_ENGINE | -+ ((sc->sc_flags & HIFN_HAS_PUBLIC) ? -+ HIFN_DMACSR_PUBDONE : 0) | -+ ((sc->sc_flags & HIFN_IS_7811) ? -+ HIFN_DMACSR_ILLW | HIFN_DMACSR_ILLR : 0)); -+ -+ sc->sc_d_busy = sc->sc_r_busy = sc->sc_s_busy = sc->sc_c_busy = 0; -+ sc->sc_dmaier |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT | -+ HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER | -+ HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT | -+ ((sc->sc_flags & HIFN_IS_7811) ? -+ HIFN_DMAIER_ILLW | HIFN_DMAIER_ILLR : 0); -+ sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; -+ WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); -+ -+ -+ if (sc->sc_flags & HIFN_IS_7956) { -+ u_int32_t pll; -+ -+ WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING | -+ HIFN_PUCNFG_TCALLPHASES | -+ HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32); -+ -+ /* turn off the clocks and insure bypass is set */ -+ pll = READ_REG_1(sc, HIFN_1_PLL); -+ pll = (pll &~ (HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL)) -+ | HIFN_PLL_BP | HIFN_PLL_MBSET; -+ WRITE_REG_1(sc, HIFN_1_PLL, pll); -+ DELAY(10*1000); /* 10ms */ -+ -+ /* change configuration */ -+ pll = (pll &~ HIFN_PLL_CONFIG) | sc->sc_pllconfig; -+ WRITE_REG_1(sc, HIFN_1_PLL, pll); -+ DELAY(10*1000); /* 10ms */ -+ -+ /* disable bypass */ -+ pll &= ~HIFN_PLL_BP; -+ WRITE_REG_1(sc, HIFN_1_PLL, pll); -+ /* enable clocks with new configuration */ -+ pll |= HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL; -+ WRITE_REG_1(sc, HIFN_1_PLL, pll); -+ } else { -+ WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING | -+ HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES | -+ HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 | -+ (sc->sc_drammodel ? HIFN_PUCNFG_DRAM : HIFN_PUCNFG_SRAM)); -+ } -+ -+ WRITE_REG_0(sc, HIFN_0_PUISR, HIFN_PUISR_DSTOVER); -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | -+ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST | -+ ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) | -+ ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL)); -+} -+ -+/* -+ * The maximum number of sessions supported by the card -+ * is dependent on the amount of context ram, which -+ * encryption algorithms are enabled, and how compression -+ * is configured. This should be configured before this -+ * routine is called. -+ */ -+static void -+hifn_sessions(struct hifn_softc *sc) -+{ -+ u_int32_t pucnfg; -+ int ctxsize; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ pucnfg = READ_REG_0(sc, HIFN_0_PUCNFG); -+ -+ if (pucnfg & HIFN_PUCNFG_COMPSING) { -+ if (pucnfg & HIFN_PUCNFG_ENCCNFG) -+ ctxsize = 128; -+ else -+ ctxsize = 512; -+ /* -+ * 7955/7956 has internal context memory of 32K -+ */ -+ if (sc->sc_flags & HIFN_IS_7956) -+ sc->sc_maxses = 32768 / ctxsize; -+ else -+ sc->sc_maxses = 1 + -+ ((sc->sc_ramsize - 32768) / ctxsize); -+ } else -+ sc->sc_maxses = sc->sc_ramsize / 16384; -+ -+ if (sc->sc_maxses > 2048) -+ sc->sc_maxses = 2048; -+} -+ -+/* -+ * Determine ram type (sram or dram). Board should be just out of a reset -+ * state when this is called. -+ */ -+static int -+hifn_ramtype(struct hifn_softc *sc) -+{ -+ u_int8_t data[8], dataexpect[8]; -+ int i; -+ -+ for (i = 0; i < sizeof(data); i++) -+ data[i] = dataexpect[i] = 0x55; -+ if (hifn_writeramaddr(sc, 0, data)) -+ return (-1); -+ if (hifn_readramaddr(sc, 0, data)) -+ return (-1); -+ if (bcmp(data, dataexpect, sizeof(data)) != 0) { -+ sc->sc_drammodel = 1; -+ return (0); -+ } -+ -+ for (i = 0; i < sizeof(data); i++) -+ data[i] = dataexpect[i] = 0xaa; -+ if (hifn_writeramaddr(sc, 0, data)) -+ return (-1); -+ if (hifn_readramaddr(sc, 0, data)) -+ return (-1); -+ if (bcmp(data, dataexpect, sizeof(data)) != 0) { -+ sc->sc_drammodel = 1; -+ return (0); -+ } -+ -+ return (0); -+} -+ -+#define HIFN_SRAM_MAX (32 << 20) -+#define HIFN_SRAM_STEP_SIZE 16384 -+#define HIFN_SRAM_GRANULARITY (HIFN_SRAM_MAX / HIFN_SRAM_STEP_SIZE) -+ -+static int -+hifn_sramsize(struct hifn_softc *sc) -+{ -+ u_int32_t a; -+ u_int8_t data[8]; -+ u_int8_t dataexpect[sizeof(data)]; -+ int32_t i; -+ -+ for (i = 0; i < sizeof(data); i++) -+ data[i] = dataexpect[i] = i ^ 0x5a; -+ -+ for (i = HIFN_SRAM_GRANULARITY - 1; i >= 0; i--) { -+ a = i * HIFN_SRAM_STEP_SIZE; -+ bcopy(&i, data, sizeof(i)); -+ hifn_writeramaddr(sc, a, data); -+ } -+ -+ for (i = 0; i < HIFN_SRAM_GRANULARITY; i++) { -+ a = i * HIFN_SRAM_STEP_SIZE; -+ bcopy(&i, dataexpect, sizeof(i)); -+ if (hifn_readramaddr(sc, a, data) < 0) -+ return (0); -+ if (bcmp(data, dataexpect, sizeof(data)) != 0) -+ return (0); -+ sc->sc_ramsize = a + HIFN_SRAM_STEP_SIZE; -+ } -+ -+ return (0); -+} -+ -+/* -+ * XXX For dram boards, one should really try all of the -+ * HIFN_PUCNFG_DSZ_*'s. This just assumes that PUCNFG -+ * is already set up correctly. -+ */ -+static int -+hifn_dramsize(struct hifn_softc *sc) -+{ -+ u_int32_t cnfg; -+ -+ if (sc->sc_flags & HIFN_IS_7956) { -+ /* -+ * 7955/7956 have a fixed internal ram of only 32K. -+ */ -+ sc->sc_ramsize = 32768; -+ } else { -+ cnfg = READ_REG_0(sc, HIFN_0_PUCNFG) & -+ HIFN_PUCNFG_DRAMMASK; -+ sc->sc_ramsize = 1 << ((cnfg >> 13) + 18); -+ } -+ return (0); -+} -+ -+static void -+hifn_alloc_slot(struct hifn_softc *sc, int *cmdp, int *srcp, int *dstp, int *resp) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (dma->cmdi == HIFN_D_CMD_RSIZE) { -+ dma->cmdi = 0; -+ dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); -+ wmb(); -+ dma->cmdr[HIFN_D_CMD_RSIZE].l |= htole32(HIFN_D_VALID); -+ HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, -+ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); -+ } -+ *cmdp = dma->cmdi++; -+ dma->cmdk = dma->cmdi; -+ -+ if (dma->srci == HIFN_D_SRC_RSIZE) { -+ dma->srci = 0; -+ dma->srcr[HIFN_D_SRC_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); -+ wmb(); -+ dma->srcr[HIFN_D_SRC_RSIZE].l |= htole32(HIFN_D_VALID); -+ HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, -+ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); -+ } -+ *srcp = dma->srci++; -+ dma->srck = dma->srci; -+ -+ if (dma->dsti == HIFN_D_DST_RSIZE) { -+ dma->dsti = 0; -+ dma->dstr[HIFN_D_DST_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); -+ wmb(); -+ dma->dstr[HIFN_D_DST_RSIZE].l |= htole32(HIFN_D_VALID); -+ HIFN_DSTR_SYNC(sc, HIFN_D_DST_RSIZE, -+ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); -+ } -+ *dstp = dma->dsti++; -+ dma->dstk = dma->dsti; -+ -+ if (dma->resi == HIFN_D_RES_RSIZE) { -+ dma->resi = 0; -+ dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); -+ wmb(); -+ dma->resr[HIFN_D_RES_RSIZE].l |= htole32(HIFN_D_VALID); -+ HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, -+ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); -+ } -+ *resp = dma->resi++; -+ dma->resk = dma->resi; -+} -+ -+static int -+hifn_writeramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ hifn_base_command_t wc; -+ const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; -+ int r, cmdi, resi, srci, dsti; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ wc.masks = htole16(3 << 13); -+ wc.session_num = htole16(addr >> 14); -+ wc.total_source_count = htole16(8); -+ wc.total_dest_count = htole16(addr & 0x3fff); -+ -+ hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); -+ -+ WRITE_REG_1(sc, HIFN_1_DMA_CSR, -+ HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | -+ HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); -+ -+ /* build write command */ -+ bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); -+ *(hifn_base_command_t *)dma->command_bufs[cmdi] = wc; -+ bcopy(data, &dma->test_src, sizeof(dma->test_src)); -+ -+ dma->srcr[srci].p = htole32(sc->sc_dma_physaddr -+ + offsetof(struct hifn_dma, test_src)); -+ dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr -+ + offsetof(struct hifn_dma, test_dst)); -+ -+ dma->cmdr[cmdi].l = htole32(16 | masks); -+ dma->srcr[srci].l = htole32(8 | masks); -+ dma->dstr[dsti].l = htole32(4 | masks); -+ dma->resr[resi].l = htole32(4 | masks); -+ -+ for (r = 10000; r >= 0; r--) { -+ DELAY(10); -+ if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) -+ break; -+ } -+ if (r == 0) { -+ device_printf(sc->sc_dev, "writeramaddr -- " -+ "result[%d](addr %d) still valid\n", resi, addr); -+ r = -1; -+ return (-1); -+ } else -+ r = 0; -+ -+ WRITE_REG_1(sc, HIFN_1_DMA_CSR, -+ HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | -+ HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); -+ -+ return (r); -+} -+ -+static int -+hifn_readramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ hifn_base_command_t rc; -+ const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; -+ int r, cmdi, srci, dsti, resi; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ rc.masks = htole16(2 << 13); -+ rc.session_num = htole16(addr >> 14); -+ rc.total_source_count = htole16(addr & 0x3fff); -+ rc.total_dest_count = htole16(8); -+ -+ hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); -+ -+ WRITE_REG_1(sc, HIFN_1_DMA_CSR, -+ HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | -+ HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); -+ -+ bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); -+ *(hifn_base_command_t *)dma->command_bufs[cmdi] = rc; -+ -+ dma->srcr[srci].p = htole32(sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, test_src)); -+ dma->test_src = 0; -+ dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, test_dst)); -+ dma->test_dst = 0; -+ dma->cmdr[cmdi].l = htole32(8 | masks); -+ dma->srcr[srci].l = htole32(8 | masks); -+ dma->dstr[dsti].l = htole32(8 | masks); -+ dma->resr[resi].l = htole32(HIFN_MAX_RESULT | masks); -+ -+ for (r = 10000; r >= 0; r--) { -+ DELAY(10); -+ if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) -+ break; -+ } -+ if (r == 0) { -+ device_printf(sc->sc_dev, "readramaddr -- " -+ "result[%d](addr %d) still valid\n", resi, addr); -+ r = -1; -+ } else { -+ r = 0; -+ bcopy(&dma->test_dst, data, sizeof(dma->test_dst)); -+ } -+ -+ WRITE_REG_1(sc, HIFN_1_DMA_CSR, -+ HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | -+ HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); -+ -+ return (r); -+} -+ -+/* -+ * Initialize the descriptor rings. -+ */ -+static void -+hifn_init_dma(struct hifn_softc *sc) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ hifn_set_retry(sc); -+ -+ /* initialize static pointer values */ -+ for (i = 0; i < HIFN_D_CMD_RSIZE; i++) -+ dma->cmdr[i].p = htole32(sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, command_bufs[i][0])); -+ for (i = 0; i < HIFN_D_RES_RSIZE; i++) -+ dma->resr[i].p = htole32(sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, result_bufs[i][0])); -+ -+ dma->cmdr[HIFN_D_CMD_RSIZE].p = -+ htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, cmdr[0])); -+ dma->srcr[HIFN_D_SRC_RSIZE].p = -+ htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, srcr[0])); -+ dma->dstr[HIFN_D_DST_RSIZE].p = -+ htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, dstr[0])); -+ dma->resr[HIFN_D_RES_RSIZE].p = -+ htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, resr[0])); -+ -+ dma->cmdu = dma->srcu = dma->dstu = dma->resu = 0; -+ dma->cmdi = dma->srci = dma->dsti = dma->resi = 0; -+ dma->cmdk = dma->srck = dma->dstk = dma->resk = 0; -+} -+ -+/* -+ * Writes out the raw command buffer space. Returns the -+ * command buffer size. -+ */ -+static u_int -+hifn_write_command(struct hifn_command *cmd, u_int8_t *buf) -+{ -+ struct hifn_softc *sc = NULL; -+ u_int8_t *buf_pos; -+ hifn_base_command_t *base_cmd; -+ hifn_mac_command_t *mac_cmd; -+ hifn_crypt_command_t *cry_cmd; -+ int using_mac, using_crypt, len, ivlen; -+ u_int32_t dlen, slen; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ buf_pos = buf; -+ using_mac = cmd->base_masks & HIFN_BASE_CMD_MAC; -+ using_crypt = cmd->base_masks & HIFN_BASE_CMD_CRYPT; -+ -+ base_cmd = (hifn_base_command_t *)buf_pos; -+ base_cmd->masks = htole16(cmd->base_masks); -+ slen = cmd->src_mapsize; -+ if (cmd->sloplen) -+ dlen = cmd->dst_mapsize - cmd->sloplen + sizeof(u_int32_t); -+ else -+ dlen = cmd->dst_mapsize; -+ base_cmd->total_source_count = htole16(slen & HIFN_BASE_CMD_LENMASK_LO); -+ base_cmd->total_dest_count = htole16(dlen & HIFN_BASE_CMD_LENMASK_LO); -+ dlen >>= 16; -+ slen >>= 16; -+ base_cmd->session_num = htole16( -+ ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) | -+ ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M)); -+ buf_pos += sizeof(hifn_base_command_t); -+ -+ if (using_mac) { -+ mac_cmd = (hifn_mac_command_t *)buf_pos; -+ dlen = cmd->maccrd->crd_len; -+ mac_cmd->source_count = htole16(dlen & 0xffff); -+ dlen >>= 16; -+ mac_cmd->masks = htole16(cmd->mac_masks | -+ ((dlen << HIFN_MAC_CMD_SRCLEN_S) & HIFN_MAC_CMD_SRCLEN_M)); -+ mac_cmd->header_skip = htole16(cmd->maccrd->crd_skip); -+ mac_cmd->reserved = 0; -+ buf_pos += sizeof(hifn_mac_command_t); -+ } -+ -+ if (using_crypt) { -+ cry_cmd = (hifn_crypt_command_t *)buf_pos; -+ dlen = cmd->enccrd->crd_len; -+ cry_cmd->source_count = htole16(dlen & 0xffff); -+ dlen >>= 16; -+ cry_cmd->masks = htole16(cmd->cry_masks | -+ ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) & HIFN_CRYPT_CMD_SRCLEN_M)); -+ cry_cmd->header_skip = htole16(cmd->enccrd->crd_skip); -+ cry_cmd->reserved = 0; -+ buf_pos += sizeof(hifn_crypt_command_t); -+ } -+ -+ if (using_mac && cmd->mac_masks & HIFN_MAC_CMD_NEW_KEY) { -+ bcopy(cmd->mac, buf_pos, HIFN_MAC_KEY_LENGTH); -+ buf_pos += HIFN_MAC_KEY_LENGTH; -+ } -+ -+ if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_KEY) { -+ switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) { -+ case HIFN_CRYPT_CMD_ALG_3DES: -+ bcopy(cmd->ck, buf_pos, HIFN_3DES_KEY_LENGTH); -+ buf_pos += HIFN_3DES_KEY_LENGTH; -+ break; -+ case HIFN_CRYPT_CMD_ALG_DES: -+ bcopy(cmd->ck, buf_pos, HIFN_DES_KEY_LENGTH); -+ buf_pos += HIFN_DES_KEY_LENGTH; -+ break; -+ case HIFN_CRYPT_CMD_ALG_RC4: -+ len = 256; -+ do { -+ int clen; -+ -+ clen = MIN(cmd->cklen, len); -+ bcopy(cmd->ck, buf_pos, clen); -+ len -= clen; -+ buf_pos += clen; -+ } while (len > 0); -+ bzero(buf_pos, 4); -+ buf_pos += 4; -+ break; -+ case HIFN_CRYPT_CMD_ALG_AES: -+ /* -+ * AES keys are variable 128, 192 and -+ * 256 bits (16, 24 and 32 bytes). -+ */ -+ bcopy(cmd->ck, buf_pos, cmd->cklen); -+ buf_pos += cmd->cklen; -+ break; -+ } -+ } -+ -+ if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_IV) { -+ switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) { -+ case HIFN_CRYPT_CMD_ALG_AES: -+ ivlen = HIFN_AES_IV_LENGTH; -+ break; -+ default: -+ ivlen = HIFN_IV_LENGTH; -+ break; -+ } -+ bcopy(cmd->iv, buf_pos, ivlen); -+ buf_pos += ivlen; -+ } -+ -+ if ((cmd->base_masks & (HIFN_BASE_CMD_MAC|HIFN_BASE_CMD_CRYPT)) == 0) { -+ bzero(buf_pos, 8); -+ buf_pos += 8; -+ } -+ -+ return (buf_pos - buf); -+} -+ -+static int -+hifn_dmamap_aligned(struct hifn_operand *op) -+{ -+ struct hifn_softc *sc = NULL; -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ for (i = 0; i < op->nsegs; i++) { -+ if (op->segs[i].ds_addr & 3) -+ return (0); -+ if ((i != (op->nsegs - 1)) && (op->segs[i].ds_len & 3)) -+ return (0); -+ } -+ return (1); -+} -+ -+static __inline int -+hifn_dmamap_dstwrap(struct hifn_softc *sc, int idx) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ -+ if (++idx == HIFN_D_DST_RSIZE) { -+ dma->dstr[idx].l = htole32(HIFN_D_VALID | HIFN_D_JUMP | -+ HIFN_D_MASKDONEIRQ); -+ HIFN_DSTR_SYNC(sc, idx, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ idx = 0; -+ } -+ return (idx); -+} -+ -+static int -+hifn_dmamap_load_dst(struct hifn_softc *sc, struct hifn_command *cmd) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ struct hifn_operand *dst = &cmd->dst; -+ u_int32_t p, l; -+ int idx, used = 0, i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ idx = dma->dsti; -+ for (i = 0; i < dst->nsegs - 1; i++) { -+ dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); -+ dma->dstr[idx].l = htole32(HIFN_D_MASKDONEIRQ | dst->segs[i].ds_len); -+ wmb(); -+ dma->dstr[idx].l |= htole32(HIFN_D_VALID); -+ HIFN_DSTR_SYNC(sc, idx, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ used++; -+ -+ idx = hifn_dmamap_dstwrap(sc, idx); -+ } -+ -+ if (cmd->sloplen == 0) { -+ p = dst->segs[i].ds_addr; -+ l = HIFN_D_MASKDONEIRQ | HIFN_D_LAST | -+ dst->segs[i].ds_len; -+ } else { -+ p = sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, slop[cmd->slopidx]); -+ l = HIFN_D_MASKDONEIRQ | HIFN_D_LAST | -+ sizeof(u_int32_t); -+ -+ if ((dst->segs[i].ds_len - cmd->sloplen) != 0) { -+ dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); -+ dma->dstr[idx].l = htole32(HIFN_D_MASKDONEIRQ | -+ (dst->segs[i].ds_len - cmd->sloplen)); -+ wmb(); -+ dma->dstr[idx].l |= htole32(HIFN_D_VALID); -+ HIFN_DSTR_SYNC(sc, idx, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ used++; -+ -+ idx = hifn_dmamap_dstwrap(sc, idx); -+ } -+ } -+ dma->dstr[idx].p = htole32(p); -+ dma->dstr[idx].l = htole32(l); -+ wmb(); -+ dma->dstr[idx].l |= htole32(HIFN_D_VALID); -+ HIFN_DSTR_SYNC(sc, idx, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ used++; -+ -+ idx = hifn_dmamap_dstwrap(sc, idx); -+ -+ dma->dsti = idx; -+ dma->dstu += used; -+ return (idx); -+} -+ -+static __inline int -+hifn_dmamap_srcwrap(struct hifn_softc *sc, int idx) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ -+ if (++idx == HIFN_D_SRC_RSIZE) { -+ dma->srcr[idx].l = htole32(HIFN_D_VALID | -+ HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); -+ HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, -+ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); -+ idx = 0; -+ } -+ return (idx); -+} -+ -+static int -+hifn_dmamap_load_src(struct hifn_softc *sc, struct hifn_command *cmd) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ struct hifn_operand *src = &cmd->src; -+ int idx, i; -+ u_int32_t last = 0; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ idx = dma->srci; -+ for (i = 0; i < src->nsegs; i++) { -+ if (i == src->nsegs - 1) -+ last = HIFN_D_LAST; -+ -+ dma->srcr[idx].p = htole32(src->segs[i].ds_addr); -+ dma->srcr[idx].l = htole32(src->segs[i].ds_len | -+ HIFN_D_MASKDONEIRQ | last); -+ wmb(); -+ dma->srcr[idx].l |= htole32(HIFN_D_VALID); -+ HIFN_SRCR_SYNC(sc, idx, -+ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); -+ -+ idx = hifn_dmamap_srcwrap(sc, idx); -+ } -+ dma->srci = idx; -+ dma->srcu += src->nsegs; -+ return (idx); -+} -+ -+ -+static int -+hifn_crypto( -+ struct hifn_softc *sc, -+ struct hifn_command *cmd, -+ struct cryptop *crp, -+ int hint) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ u_int32_t cmdlen, csr; -+ int cmdi, resi, err = 0; -+ unsigned long l_flags; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ /* -+ * need 1 cmd, and 1 res -+ * -+ * NB: check this first since it's easy. -+ */ -+ HIFN_LOCK(sc); -+ if ((dma->cmdu + 1) > HIFN_D_CMD_RSIZE || -+ (dma->resu + 1) > HIFN_D_RES_RSIZE) { -+#ifdef HIFN_DEBUG -+ if (hifn_debug) { -+ device_printf(sc->sc_dev, -+ "cmd/result exhaustion, cmdu %u resu %u\n", -+ dma->cmdu, dma->resu); -+ } -+#endif -+ hifnstats.hst_nomem_cr++; -+ sc->sc_needwakeup |= CRYPTO_SYMQ; -+ HIFN_UNLOCK(sc); -+ return (ERESTART); -+ } -+ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ if (pci_map_skb(sc, &cmd->src, cmd->src_skb)) { -+ hifnstats.hst_nomem_load++; -+ err = ENOMEM; -+ goto err_srcmap1; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ if (pci_map_uio(sc, &cmd->src, cmd->src_io)) { -+ hifnstats.hst_nomem_load++; -+ err = ENOMEM; -+ goto err_srcmap1; -+ } -+ } else { -+ if (pci_map_buf(sc, &cmd->src, cmd->src_buf, crp->crp_ilen)) { -+ hifnstats.hst_nomem_load++; -+ err = ENOMEM; -+ goto err_srcmap1; -+ } -+ } -+ -+ if (hifn_dmamap_aligned(&cmd->src)) { -+ cmd->sloplen = cmd->src_mapsize & 3; -+ cmd->dst = cmd->src; -+ } else { -+ if (crp->crp_flags & CRYPTO_F_IOV) { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ err = EINVAL; -+ goto err_srcmap; -+ } else if (crp->crp_flags & CRYPTO_F_SKBUF) { -+#ifdef NOTYET -+ int totlen, len; -+ struct mbuf *m, *m0, *mlast; -+ -+ KASSERT(cmd->dst_m == cmd->src_m, -+ ("hifn_crypto: dst_m initialized improperly")); -+ hifnstats.hst_unaligned++; -+ /* -+ * Source is not aligned on a longword boundary. -+ * Copy the data to insure alignment. If we fail -+ * to allocate mbufs or clusters while doing this -+ * we return ERESTART so the operation is requeued -+ * at the crypto later, but only if there are -+ * ops already posted to the hardware; otherwise we -+ * have no guarantee that we'll be re-entered. -+ */ -+ totlen = cmd->src_mapsize; -+ if (cmd->src_m->m_flags & M_PKTHDR) { -+ len = MHLEN; -+ MGETHDR(m0, M_DONTWAIT, MT_DATA); -+ if (m0 && !m_dup_pkthdr(m0, cmd->src_m, M_DONTWAIT)) { -+ m_free(m0); -+ m0 = NULL; -+ } -+ } else { -+ len = MLEN; -+ MGET(m0, M_DONTWAIT, MT_DATA); -+ } -+ if (m0 == NULL) { -+ hifnstats.hst_nomem_mbuf++; -+ err = dma->cmdu ? ERESTART : ENOMEM; -+ goto err_srcmap; -+ } -+ if (totlen >= MINCLSIZE) { -+ MCLGET(m0, M_DONTWAIT); -+ if ((m0->m_flags & M_EXT) == 0) { -+ hifnstats.hst_nomem_mcl++; -+ err = dma->cmdu ? ERESTART : ENOMEM; -+ m_freem(m0); -+ goto err_srcmap; -+ } -+ len = MCLBYTES; -+ } -+ totlen -= len; -+ m0->m_pkthdr.len = m0->m_len = len; -+ mlast = m0; -+ -+ while (totlen > 0) { -+ MGET(m, M_DONTWAIT, MT_DATA); -+ if (m == NULL) { -+ hifnstats.hst_nomem_mbuf++; -+ err = dma->cmdu ? ERESTART : ENOMEM; -+ m_freem(m0); -+ goto err_srcmap; -+ } -+ len = MLEN; -+ if (totlen >= MINCLSIZE) { -+ MCLGET(m, M_DONTWAIT); -+ if ((m->m_flags & M_EXT) == 0) { -+ hifnstats.hst_nomem_mcl++; -+ err = dma->cmdu ? ERESTART : ENOMEM; -+ mlast->m_next = m; -+ m_freem(m0); -+ goto err_srcmap; -+ } -+ len = MCLBYTES; -+ } -+ -+ m->m_len = len; -+ m0->m_pkthdr.len += len; -+ totlen -= len; -+ -+ mlast->m_next = m; -+ mlast = m; -+ } -+ cmd->dst_m = m0; -+#else -+ device_printf(sc->sc_dev, -+ "%s,%d: CRYPTO_F_SKBUF unaligned not implemented\n", -+ __FILE__, __LINE__); -+ err = EINVAL; -+ goto err_srcmap; -+#endif -+ } else { -+ device_printf(sc->sc_dev, -+ "%s,%d: unaligned contig buffers not implemented\n", -+ __FILE__, __LINE__); -+ err = EINVAL; -+ goto err_srcmap; -+ } -+ } -+ -+ if (cmd->dst_map == NULL) { -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ if (pci_map_skb(sc, &cmd->dst, cmd->dst_skb)) { -+ hifnstats.hst_nomem_map++; -+ err = ENOMEM; -+ goto err_dstmap1; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ if (pci_map_uio(sc, &cmd->dst, cmd->dst_io)) { -+ hifnstats.hst_nomem_load++; -+ err = ENOMEM; -+ goto err_dstmap1; -+ } -+ } else { -+ if (pci_map_buf(sc, &cmd->dst, cmd->dst_buf, crp->crp_ilen)) { -+ hifnstats.hst_nomem_load++; -+ err = ENOMEM; -+ goto err_dstmap1; -+ } -+ } -+ } -+ -+#ifdef HIFN_DEBUG -+ if (hifn_debug) { -+ device_printf(sc->sc_dev, -+ "Entering cmd: stat %8x ien %8x u %d/%d/%d/%d n %d/%d\n", -+ READ_REG_1(sc, HIFN_1_DMA_CSR), -+ READ_REG_1(sc, HIFN_1_DMA_IER), -+ dma->cmdu, dma->srcu, dma->dstu, dma->resu, -+ cmd->src_nsegs, cmd->dst_nsegs); -+ } -+#endif -+ -+#if 0 -+ if (cmd->src_map == cmd->dst_map) { -+ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, -+ BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); -+ } else { -+ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, -+ BUS_DMASYNC_PREWRITE); -+ bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, -+ BUS_DMASYNC_PREREAD); -+ } -+#endif -+ -+ /* -+ * need N src, and N dst -+ */ -+ if ((dma->srcu + cmd->src_nsegs) > HIFN_D_SRC_RSIZE || -+ (dma->dstu + cmd->dst_nsegs + 1) > HIFN_D_DST_RSIZE) { -+#ifdef HIFN_DEBUG -+ if (hifn_debug) { -+ device_printf(sc->sc_dev, -+ "src/dst exhaustion, srcu %u+%u dstu %u+%u\n", -+ dma->srcu, cmd->src_nsegs, -+ dma->dstu, cmd->dst_nsegs); -+ } -+#endif -+ hifnstats.hst_nomem_sd++; -+ err = ERESTART; -+ goto err_dstmap; -+ } -+ -+ if (dma->cmdi == HIFN_D_CMD_RSIZE) { -+ dma->cmdi = 0; -+ dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); -+ wmb(); -+ dma->cmdr[HIFN_D_CMD_RSIZE].l |= htole32(HIFN_D_VALID); -+ HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, -+ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); -+ } -+ cmdi = dma->cmdi++; -+ cmdlen = hifn_write_command(cmd, dma->command_bufs[cmdi]); -+ HIFN_CMD_SYNC(sc, cmdi, BUS_DMASYNC_PREWRITE); -+ -+ /* .p for command/result already set */ -+ dma->cmdr[cmdi].l = htole32(cmdlen | HIFN_D_LAST | -+ HIFN_D_MASKDONEIRQ); -+ wmb(); -+ dma->cmdr[cmdi].l |= htole32(HIFN_D_VALID); -+ HIFN_CMDR_SYNC(sc, cmdi, -+ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); -+ dma->cmdu++; -+ -+ /* -+ * We don't worry about missing an interrupt (which a "command wait" -+ * interrupt salvages us from), unless there is more than one command -+ * in the queue. -+ */ -+ if (dma->cmdu > 1) { -+ sc->sc_dmaier |= HIFN_DMAIER_C_WAIT; -+ WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); -+ } -+ -+ hifnstats.hst_ipackets++; -+ hifnstats.hst_ibytes += cmd->src_mapsize; -+ -+ hifn_dmamap_load_src(sc, cmd); -+ -+ /* -+ * Unlike other descriptors, we don't mask done interrupt from -+ * result descriptor. -+ */ -+#ifdef HIFN_DEBUG -+ if (hifn_debug) -+ device_printf(sc->sc_dev, "load res\n"); -+#endif -+ if (dma->resi == HIFN_D_RES_RSIZE) { -+ dma->resi = 0; -+ dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); -+ wmb(); -+ dma->resr[HIFN_D_RES_RSIZE].l |= htole32(HIFN_D_VALID); -+ HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ } -+ resi = dma->resi++; -+ KASSERT(dma->hifn_commands[resi] == NULL, -+ ("hifn_crypto: command slot %u busy", resi)); -+ dma->hifn_commands[resi] = cmd; -+ HIFN_RES_SYNC(sc, resi, BUS_DMASYNC_PREREAD); -+ if ((hint & CRYPTO_HINT_MORE) && sc->sc_curbatch < hifn_maxbatch) { -+ dma->resr[resi].l = htole32(HIFN_MAX_RESULT | -+ HIFN_D_LAST | HIFN_D_MASKDONEIRQ); -+ wmb(); -+ dma->resr[resi].l |= htole32(HIFN_D_VALID); -+ sc->sc_curbatch++; -+ if (sc->sc_curbatch > hifnstats.hst_maxbatch) -+ hifnstats.hst_maxbatch = sc->sc_curbatch; -+ hifnstats.hst_totbatch++; -+ } else { -+ dma->resr[resi].l = htole32(HIFN_MAX_RESULT | HIFN_D_LAST); -+ wmb(); -+ dma->resr[resi].l |= htole32(HIFN_D_VALID); -+ sc->sc_curbatch = 0; -+ } -+ HIFN_RESR_SYNC(sc, resi, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ dma->resu++; -+ -+ if (cmd->sloplen) -+ cmd->slopidx = resi; -+ -+ hifn_dmamap_load_dst(sc, cmd); -+ -+ csr = 0; -+ if (sc->sc_c_busy == 0) { -+ csr |= HIFN_DMACSR_C_CTRL_ENA; -+ sc->sc_c_busy = 1; -+ } -+ if (sc->sc_s_busy == 0) { -+ csr |= HIFN_DMACSR_S_CTRL_ENA; -+ sc->sc_s_busy = 1; -+ } -+ if (sc->sc_r_busy == 0) { -+ csr |= HIFN_DMACSR_R_CTRL_ENA; -+ sc->sc_r_busy = 1; -+ } -+ if (sc->sc_d_busy == 0) { -+ csr |= HIFN_DMACSR_D_CTRL_ENA; -+ sc->sc_d_busy = 1; -+ } -+ if (csr) -+ WRITE_REG_1(sc, HIFN_1_DMA_CSR, csr); -+ -+#ifdef HIFN_DEBUG -+ if (hifn_debug) { -+ device_printf(sc->sc_dev, "command: stat %8x ier %8x\n", -+ READ_REG_1(sc, HIFN_1_DMA_CSR), -+ READ_REG_1(sc, HIFN_1_DMA_IER)); -+ } -+#endif -+ -+ sc->sc_active = 5; -+ HIFN_UNLOCK(sc); -+ KASSERT(err == 0, ("hifn_crypto: success with error %u", err)); -+ return (err); /* success */ -+ -+err_dstmap: -+ if (cmd->src_map != cmd->dst_map) -+ pci_unmap_buf(sc, &cmd->dst); -+err_dstmap1: -+err_srcmap: -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ if (cmd->src_skb != cmd->dst_skb) -+#ifdef NOTYET -+ m_freem(cmd->dst_m); -+#else -+ device_printf(sc->sc_dev, -+ "%s,%d: CRYPTO_F_SKBUF src != dst not implemented\n", -+ __FILE__, __LINE__); -+#endif -+ } -+ pci_unmap_buf(sc, &cmd->src); -+err_srcmap1: -+ HIFN_UNLOCK(sc); -+ return (err); -+} -+ -+static void -+hifn_tick(unsigned long arg) -+{ -+ struct hifn_softc *sc; -+ unsigned long l_flags; -+ -+ if (arg >= HIFN_MAX_CHIPS) -+ return; -+ sc = hifn_chip_idx[arg]; -+ if (!sc) -+ return; -+ -+ HIFN_LOCK(sc); -+ if (sc->sc_active == 0) { -+ struct hifn_dma *dma = sc->sc_dma; -+ u_int32_t r = 0; -+ -+ if (dma->cmdu == 0 && sc->sc_c_busy) { -+ sc->sc_c_busy = 0; -+ r |= HIFN_DMACSR_C_CTRL_DIS; -+ } -+ if (dma->srcu == 0 && sc->sc_s_busy) { -+ sc->sc_s_busy = 0; -+ r |= HIFN_DMACSR_S_CTRL_DIS; -+ } -+ if (dma->dstu == 0 && sc->sc_d_busy) { -+ sc->sc_d_busy = 0; -+ r |= HIFN_DMACSR_D_CTRL_DIS; -+ } -+ if (dma->resu == 0 && sc->sc_r_busy) { -+ sc->sc_r_busy = 0; -+ r |= HIFN_DMACSR_R_CTRL_DIS; -+ } -+ if (r) -+ WRITE_REG_1(sc, HIFN_1_DMA_CSR, r); -+ } else -+ sc->sc_active--; -+ HIFN_UNLOCK(sc); -+ mod_timer(&sc->sc_tickto, jiffies + HZ); -+} -+ -+static irqreturn_t -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) -+hifn_intr(int irq, void *arg) -+#else -+hifn_intr(int irq, void *arg, struct pt_regs *regs) -+#endif -+{ -+ struct hifn_softc *sc = arg; -+ struct hifn_dma *dma; -+ u_int32_t dmacsr, restart; -+ int i, u; -+ unsigned long l_flags; -+ -+ dmacsr = READ_REG_1(sc, HIFN_1_DMA_CSR); -+ -+ /* Nothing in the DMA unit interrupted */ -+ if ((dmacsr & sc->sc_dmaier) == 0) -+ return IRQ_NONE; -+ -+ HIFN_LOCK(sc); -+ -+ dma = sc->sc_dma; -+ -+#ifdef HIFN_DEBUG -+ if (hifn_debug) { -+ device_printf(sc->sc_dev, -+ "irq: stat %08x ien %08x damier %08x i %d/%d/%d/%d k %d/%d/%d/%d u %d/%d/%d/%d\n", -+ dmacsr, READ_REG_1(sc, HIFN_1_DMA_IER), sc->sc_dmaier, -+ dma->cmdi, dma->srci, dma->dsti, dma->resi, -+ dma->cmdk, dma->srck, dma->dstk, dma->resk, -+ dma->cmdu, dma->srcu, dma->dstu, dma->resu); -+ } -+#endif -+ -+ WRITE_REG_1(sc, HIFN_1_DMA_CSR, dmacsr & sc->sc_dmaier); -+ -+ if ((sc->sc_flags & HIFN_HAS_PUBLIC) && -+ (dmacsr & HIFN_DMACSR_PUBDONE)) -+ WRITE_REG_1(sc, HIFN_1_PUB_STATUS, -+ READ_REG_1(sc, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE); -+ -+ restart = dmacsr & (HIFN_DMACSR_D_OVER | HIFN_DMACSR_R_OVER); -+ if (restart) -+ device_printf(sc->sc_dev, "overrun %x\n", dmacsr); -+ -+ if (sc->sc_flags & HIFN_IS_7811) { -+ if (dmacsr & HIFN_DMACSR_ILLR) -+ device_printf(sc->sc_dev, "illegal read\n"); -+ if (dmacsr & HIFN_DMACSR_ILLW) -+ device_printf(sc->sc_dev, "illegal write\n"); -+ } -+ -+ restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT | -+ HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT); -+ if (restart) { -+ device_printf(sc->sc_dev, "abort, resetting.\n"); -+ hifnstats.hst_abort++; -+ hifn_abort(sc); -+ HIFN_UNLOCK(sc); -+ return IRQ_HANDLED; -+ } -+ -+ if ((dmacsr & HIFN_DMACSR_C_WAIT) && (dma->cmdu == 0)) { -+ /* -+ * If no slots to process and we receive a "waiting on -+ * command" interrupt, we disable the "waiting on command" -+ * (by clearing it). -+ */ -+ sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; -+ WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); -+ } -+ -+ /* clear the rings */ -+ i = dma->resk; u = dma->resu; -+ while (u != 0) { -+ HIFN_RESR_SYNC(sc, i, -+ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); -+ if (dma->resr[i].l & htole32(HIFN_D_VALID)) { -+ HIFN_RESR_SYNC(sc, i, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ break; -+ } -+ -+ if (i != HIFN_D_RES_RSIZE) { -+ struct hifn_command *cmd; -+ u_int8_t *macbuf = NULL; -+ -+ HIFN_RES_SYNC(sc, i, BUS_DMASYNC_POSTREAD); -+ cmd = dma->hifn_commands[i]; -+ KASSERT(cmd != NULL, -+ ("hifn_intr: null command slot %u", i)); -+ dma->hifn_commands[i] = NULL; -+ -+ if (cmd->base_masks & HIFN_BASE_CMD_MAC) { -+ macbuf = dma->result_bufs[i]; -+ macbuf += 12; -+ } -+ -+ hifn_callback(sc, cmd, macbuf); -+ hifnstats.hst_opackets++; -+ u--; -+ } -+ -+ if (++i == (HIFN_D_RES_RSIZE + 1)) -+ i = 0; -+ } -+ dma->resk = i; dma->resu = u; -+ -+ i = dma->srck; u = dma->srcu; -+ while (u != 0) { -+ if (i == HIFN_D_SRC_RSIZE) -+ i = 0; -+ HIFN_SRCR_SYNC(sc, i, -+ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); -+ if (dma->srcr[i].l & htole32(HIFN_D_VALID)) { -+ HIFN_SRCR_SYNC(sc, i, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ break; -+ } -+ i++, u--; -+ } -+ dma->srck = i; dma->srcu = u; -+ -+ i = dma->cmdk; u = dma->cmdu; -+ while (u != 0) { -+ HIFN_CMDR_SYNC(sc, i, -+ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); -+ if (dma->cmdr[i].l & htole32(HIFN_D_VALID)) { -+ HIFN_CMDR_SYNC(sc, i, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ break; -+ } -+ if (i != HIFN_D_CMD_RSIZE) { -+ u--; -+ HIFN_CMD_SYNC(sc, i, BUS_DMASYNC_POSTWRITE); -+ } -+ if (++i == (HIFN_D_CMD_RSIZE + 1)) -+ i = 0; -+ } -+ dma->cmdk = i; dma->cmdu = u; -+ -+ HIFN_UNLOCK(sc); -+ -+ if (sc->sc_needwakeup) { /* XXX check high watermark */ -+ int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); -+#ifdef HIFN_DEBUG -+ if (hifn_debug) -+ device_printf(sc->sc_dev, -+ "wakeup crypto (%x) u %d/%d/%d/%d\n", -+ sc->sc_needwakeup, -+ dma->cmdu, dma->srcu, dma->dstu, dma->resu); -+#endif -+ sc->sc_needwakeup &= ~wakeup; -+ crypto_unblock(sc->sc_cid, wakeup); -+ } -+ -+ return IRQ_HANDLED; -+} -+ -+/* -+ * Allocate a new 'session' and return an encoded session id. 'sidp' -+ * contains our registration id, and should contain an encoded session -+ * id on successful allocation. -+ */ -+static int -+hifn_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) -+{ -+ struct hifn_softc *sc = device_get_softc(dev); -+ struct cryptoini *c; -+ int mac = 0, cry = 0, sesn; -+ struct hifn_session *ses = NULL; -+ unsigned long l_flags; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ KASSERT(sc != NULL, ("hifn_newsession: null softc")); -+ if (sidp == NULL || cri == NULL || sc == NULL) { -+ DPRINTF("%s,%d: %s - EINVAL\n", __FILE__, __LINE__, __FUNCTION__); -+ return (EINVAL); -+ } -+ -+ HIFN_LOCK(sc); -+ if (sc->sc_sessions == NULL) { -+ ses = sc->sc_sessions = (struct hifn_session *)kmalloc(sizeof(*ses), -+ SLAB_ATOMIC); -+ if (ses == NULL) { -+ HIFN_UNLOCK(sc); -+ return (ENOMEM); -+ } -+ sesn = 0; -+ sc->sc_nsessions = 1; -+ } else { -+ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { -+ if (!sc->sc_sessions[sesn].hs_used) { -+ ses = &sc->sc_sessions[sesn]; -+ break; -+ } -+ } -+ -+ if (ses == NULL) { -+ sesn = sc->sc_nsessions; -+ ses = (struct hifn_session *)kmalloc((sesn + 1) * sizeof(*ses), -+ SLAB_ATOMIC); -+ if (ses == NULL) { -+ HIFN_UNLOCK(sc); -+ return (ENOMEM); -+ } -+ bcopy(sc->sc_sessions, ses, sesn * sizeof(*ses)); -+ bzero(sc->sc_sessions, sesn * sizeof(*ses)); -+ kfree(sc->sc_sessions); -+ sc->sc_sessions = ses; -+ ses = &sc->sc_sessions[sesn]; -+ sc->sc_nsessions++; -+ } -+ } -+ HIFN_UNLOCK(sc); -+ -+ bzero(ses, sizeof(*ses)); -+ ses->hs_used = 1; -+ -+ for (c = cri; c != NULL; c = c->cri_next) { -+ switch (c->cri_alg) { -+ case CRYPTO_MD5: -+ case CRYPTO_SHA1: -+ case CRYPTO_MD5_HMAC: -+ case CRYPTO_SHA1_HMAC: -+ if (mac) { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ return (EINVAL); -+ } -+ mac = 1; -+ ses->hs_mlen = c->cri_mlen; -+ if (ses->hs_mlen == 0) { -+ switch (c->cri_alg) { -+ case CRYPTO_MD5: -+ case CRYPTO_MD5_HMAC: -+ ses->hs_mlen = 16; -+ break; -+ case CRYPTO_SHA1: -+ case CRYPTO_SHA1_HMAC: -+ ses->hs_mlen = 20; -+ break; -+ } -+ } -+ break; -+ case CRYPTO_DES_CBC: -+ case CRYPTO_3DES_CBC: -+ case CRYPTO_AES_CBC: -+ /* XXX this may read fewer, does it matter? */ -+ read_random(ses->hs_iv, -+ c->cri_alg == CRYPTO_AES_CBC ? -+ HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH); -+ /*FALLTHROUGH*/ -+ case CRYPTO_ARC4: -+ if (cry) { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ return (EINVAL); -+ } -+ cry = 1; -+ break; -+ default: -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ return (EINVAL); -+ } -+ } -+ if (mac == 0 && cry == 0) { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ return (EINVAL); -+ } -+ -+ *sidp = HIFN_SID(device_get_unit(sc->sc_dev), sesn); -+ -+ return (0); -+} -+ -+/* -+ * Deallocate a session. -+ * XXX this routine should run a zero'd mac/encrypt key into context ram. -+ * XXX to blow away any keys already stored there. -+ */ -+static int -+hifn_freesession(device_t dev, u_int64_t tid) -+{ -+ struct hifn_softc *sc = device_get_softc(dev); -+ int session, error; -+ u_int32_t sid = CRYPTO_SESID2LID(tid); -+ unsigned long l_flags; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ KASSERT(sc != NULL, ("hifn_freesession: null softc")); -+ if (sc == NULL) { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ return (EINVAL); -+ } -+ -+ HIFN_LOCK(sc); -+ session = HIFN_SESSION(sid); -+ if (session < sc->sc_nsessions) { -+ bzero(&sc->sc_sessions[session], sizeof(struct hifn_session)); -+ error = 0; -+ } else { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ error = EINVAL; -+ } -+ HIFN_UNLOCK(sc); -+ -+ return (error); -+} -+ -+static int -+hifn_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ struct hifn_softc *sc = device_get_softc(dev); -+ struct hifn_command *cmd = NULL; -+ int session, err, ivlen; -+ struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (crp == NULL || crp->crp_callback == NULL) { -+ hifnstats.hst_invalid++; -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ return (EINVAL); -+ } -+ session = HIFN_SESSION(crp->crp_sid); -+ -+ if (sc == NULL || session >= sc->sc_nsessions) { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ err = EINVAL; -+ goto errout; -+ } -+ -+ cmd = kmalloc(sizeof(struct hifn_command), SLAB_ATOMIC); -+ if (cmd == NULL) { -+ hifnstats.hst_nomem++; -+ err = ENOMEM; -+ goto errout; -+ } -+ memset(cmd, 0, sizeof(*cmd)); -+ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ cmd->src_skb = (struct sk_buff *)crp->crp_buf; -+ cmd->dst_skb = (struct sk_buff *)crp->crp_buf; -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ cmd->src_io = (struct uio *)crp->crp_buf; -+ cmd->dst_io = (struct uio *)crp->crp_buf; -+ } else { -+ cmd->src_buf = crp->crp_buf; -+ cmd->dst_buf = crp->crp_buf; -+ } -+ -+ crd1 = crp->crp_desc; -+ if (crd1 == NULL) { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ err = EINVAL; -+ goto errout; -+ } -+ crd2 = crd1->crd_next; -+ -+ if (crd2 == NULL) { -+ if (crd1->crd_alg == CRYPTO_MD5_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1 || -+ crd1->crd_alg == CRYPTO_MD5) { -+ maccrd = crd1; -+ enccrd = NULL; -+ } else if (crd1->crd_alg == CRYPTO_DES_CBC || -+ crd1->crd_alg == CRYPTO_3DES_CBC || -+ crd1->crd_alg == CRYPTO_AES_CBC || -+ crd1->crd_alg == CRYPTO_ARC4) { -+ if ((crd1->crd_flags & CRD_F_ENCRYPT) == 0) -+ cmd->base_masks |= HIFN_BASE_CMD_DECODE; -+ maccrd = NULL; -+ enccrd = crd1; -+ } else { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ err = EINVAL; -+ goto errout; -+ } -+ } else { -+ if ((crd1->crd_alg == CRYPTO_MD5_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1_HMAC || -+ crd1->crd_alg == CRYPTO_MD5 || -+ crd1->crd_alg == CRYPTO_SHA1) && -+ (crd2->crd_alg == CRYPTO_DES_CBC || -+ crd2->crd_alg == CRYPTO_3DES_CBC || -+ crd2->crd_alg == CRYPTO_AES_CBC || -+ crd2->crd_alg == CRYPTO_ARC4) && -+ ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { -+ cmd->base_masks = HIFN_BASE_CMD_DECODE; -+ maccrd = crd1; -+ enccrd = crd2; -+ } else if ((crd1->crd_alg == CRYPTO_DES_CBC || -+ crd1->crd_alg == CRYPTO_ARC4 || -+ crd1->crd_alg == CRYPTO_3DES_CBC || -+ crd1->crd_alg == CRYPTO_AES_CBC) && -+ (crd2->crd_alg == CRYPTO_MD5_HMAC || -+ crd2->crd_alg == CRYPTO_SHA1_HMAC || -+ crd2->crd_alg == CRYPTO_MD5 || -+ crd2->crd_alg == CRYPTO_SHA1) && -+ (crd1->crd_flags & CRD_F_ENCRYPT)) { -+ enccrd = crd1; -+ maccrd = crd2; -+ } else { -+ /* -+ * We cannot order the 7751 as requested -+ */ -+ DPRINTF("%s,%d: %s %d,%d,%d - EINVAL\n",__FILE__,__LINE__,__FUNCTION__, crd1->crd_alg, crd2->crd_alg, crd1->crd_flags & CRD_F_ENCRYPT); -+ err = EINVAL; -+ goto errout; -+ } -+ } -+ -+ if (enccrd) { -+ cmd->enccrd = enccrd; -+ cmd->base_masks |= HIFN_BASE_CMD_CRYPT; -+ switch (enccrd->crd_alg) { -+ case CRYPTO_ARC4: -+ cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_RC4; -+ break; -+ case CRYPTO_DES_CBC: -+ cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_DES | -+ HIFN_CRYPT_CMD_MODE_CBC | -+ HIFN_CRYPT_CMD_NEW_IV; -+ break; -+ case CRYPTO_3DES_CBC: -+ cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_3DES | -+ HIFN_CRYPT_CMD_MODE_CBC | -+ HIFN_CRYPT_CMD_NEW_IV; -+ break; -+ case CRYPTO_AES_CBC: -+ cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_AES | -+ HIFN_CRYPT_CMD_MODE_CBC | -+ HIFN_CRYPT_CMD_NEW_IV; -+ break; -+ default: -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ err = EINVAL; -+ goto errout; -+ } -+ if (enccrd->crd_alg != CRYPTO_ARC4) { -+ ivlen = ((enccrd->crd_alg == CRYPTO_AES_CBC) ? -+ HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH); -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) { -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) -+ bcopy(enccrd->crd_iv, cmd->iv, ivlen); -+ else -+ bcopy(sc->sc_sessions[session].hs_iv, -+ cmd->iv, ivlen); -+ -+ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) -+ == 0) { -+ crypto_copyback(crp->crp_flags, -+ crp->crp_buf, enccrd->crd_inject, -+ ivlen, cmd->iv); -+ } -+ } else { -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) -+ bcopy(enccrd->crd_iv, cmd->iv, ivlen); -+ else { -+ crypto_copydata(crp->crp_flags, -+ crp->crp_buf, enccrd->crd_inject, -+ ivlen, cmd->iv); -+ } -+ } -+ } -+ -+ if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) -+ cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY; -+ cmd->ck = enccrd->crd_key; -+ cmd->cklen = enccrd->crd_klen >> 3; -+ cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY; -+ -+ /* -+ * Need to specify the size for the AES key in the masks. -+ */ -+ if ((cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) == -+ HIFN_CRYPT_CMD_ALG_AES) { -+ switch (cmd->cklen) { -+ case 16: -+ cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_128; -+ break; -+ case 24: -+ cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_192; -+ break; -+ case 32: -+ cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_256; -+ break; -+ default: -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ err = EINVAL; -+ goto errout; -+ } -+ } -+ } -+ -+ if (maccrd) { -+ cmd->maccrd = maccrd; -+ cmd->base_masks |= HIFN_BASE_CMD_MAC; -+ -+ switch (maccrd->crd_alg) { -+ case CRYPTO_MD5: -+ cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | -+ HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | -+ HIFN_MAC_CMD_POS_IPSEC; -+ break; -+ case CRYPTO_MD5_HMAC: -+ cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | -+ HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | -+ HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; -+ break; -+ case CRYPTO_SHA1: -+ cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | -+ HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | -+ HIFN_MAC_CMD_POS_IPSEC; -+ break; -+ case CRYPTO_SHA1_HMAC: -+ cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | -+ HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | -+ HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; -+ break; -+ } -+ -+ if (maccrd->crd_alg == CRYPTO_SHA1_HMAC || -+ maccrd->crd_alg == CRYPTO_MD5_HMAC) { -+ cmd->mac_masks |= HIFN_MAC_CMD_NEW_KEY; -+ bcopy(maccrd->crd_key, cmd->mac, maccrd->crd_klen >> 3); -+ bzero(cmd->mac + (maccrd->crd_klen >> 3), -+ HIFN_MAC_KEY_LENGTH - (maccrd->crd_klen >> 3)); -+ } -+ } -+ -+ cmd->crp = crp; -+ cmd->session_num = session; -+ cmd->softc = sc; -+ -+ err = hifn_crypto(sc, cmd, crp, hint); -+ if (!err) { -+ return 0; -+ } else if (err == ERESTART) { -+ /* -+ * There weren't enough resources to dispatch the request -+ * to the part. Notify the caller so they'll requeue this -+ * request and resubmit it again soon. -+ */ -+#ifdef HIFN_DEBUG -+ if (hifn_debug) -+ device_printf(sc->sc_dev, "requeue request\n"); -+#endif -+ kfree(cmd); -+ sc->sc_needwakeup |= CRYPTO_SYMQ; -+ return (err); -+ } -+ -+errout: -+ if (cmd != NULL) -+ kfree(cmd); -+ if (err == EINVAL) -+ hifnstats.hst_invalid++; -+ else -+ hifnstats.hst_nomem++; -+ crp->crp_etype = err; -+ crypto_done(crp); -+ return (err); -+} -+ -+static void -+hifn_abort(struct hifn_softc *sc) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ struct hifn_command *cmd; -+ struct cryptop *crp; -+ int i, u; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ i = dma->resk; u = dma->resu; -+ while (u != 0) { -+ cmd = dma->hifn_commands[i]; -+ KASSERT(cmd != NULL, ("hifn_abort: null command slot %u", i)); -+ dma->hifn_commands[i] = NULL; -+ crp = cmd->crp; -+ -+ if ((dma->resr[i].l & htole32(HIFN_D_VALID)) == 0) { -+ /* Salvage what we can. */ -+ u_int8_t *macbuf; -+ -+ if (cmd->base_masks & HIFN_BASE_CMD_MAC) { -+ macbuf = dma->result_bufs[i]; -+ macbuf += 12; -+ } else -+ macbuf = NULL; -+ hifnstats.hst_opackets++; -+ hifn_callback(sc, cmd, macbuf); -+ } else { -+#if 0 -+ if (cmd->src_map == cmd->dst_map) { -+ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, -+ BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); -+ } else { -+ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, -+ BUS_DMASYNC_POSTWRITE); -+ bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, -+ BUS_DMASYNC_POSTREAD); -+ } -+#endif -+ -+ if (cmd->src_skb != cmd->dst_skb) { -+#ifdef NOTYET -+ m_freem(cmd->src_m); -+ crp->crp_buf = (caddr_t)cmd->dst_m; -+#else -+ device_printf(sc->sc_dev, -+ "%s,%d: CRYPTO_F_SKBUF src != dst not implemented\n", -+ __FILE__, __LINE__); -+#endif -+ } -+ -+ /* non-shared buffers cannot be restarted */ -+ if (cmd->src_map != cmd->dst_map) { -+ /* -+ * XXX should be EAGAIN, delayed until -+ * after the reset. -+ */ -+ crp->crp_etype = ENOMEM; -+ pci_unmap_buf(sc, &cmd->dst); -+ } else -+ crp->crp_etype = ENOMEM; -+ -+ pci_unmap_buf(sc, &cmd->src); -+ -+ kfree(cmd); -+ if (crp->crp_etype != EAGAIN) -+ crypto_done(crp); -+ } -+ -+ if (++i == HIFN_D_RES_RSIZE) -+ i = 0; -+ u--; -+ } -+ dma->resk = i; dma->resu = u; -+ -+ hifn_reset_board(sc, 1); -+ hifn_init_dma(sc); -+ hifn_init_pci_registers(sc); -+} -+ -+static void -+hifn_callback(struct hifn_softc *sc, struct hifn_command *cmd, u_int8_t *macbuf) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ struct cryptop *crp = cmd->crp; -+ struct cryptodesc *crd; -+ int i, u, ivlen; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+#if 0 -+ if (cmd->src_map == cmd->dst_map) { -+ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, -+ BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); -+ } else { -+ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, -+ BUS_DMASYNC_POSTWRITE); -+ bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, -+ BUS_DMASYNC_POSTREAD); -+ } -+#endif -+ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ if (cmd->src_skb != cmd->dst_skb) { -+#ifdef NOTYET -+ crp->crp_buf = (caddr_t)cmd->dst_m; -+ totlen = cmd->src_mapsize; -+ for (m = cmd->dst_m; m != NULL; m = m->m_next) { -+ if (totlen < m->m_len) { -+ m->m_len = totlen; -+ totlen = 0; -+ } else -+ totlen -= m->m_len; -+ } -+ cmd->dst_m->m_pkthdr.len = cmd->src_m->m_pkthdr.len; -+ m_freem(cmd->src_m); -+#else -+ device_printf(sc->sc_dev, -+ "%s,%d: CRYPTO_F_SKBUF src != dst not implemented\n", -+ __FILE__, __LINE__); -+#endif -+ } -+ } -+ -+ if (cmd->sloplen != 0) { -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ cmd->src_mapsize - cmd->sloplen, cmd->sloplen, -+ (caddr_t)&dma->slop[cmd->slopidx]); -+ } -+ -+ i = dma->dstk; u = dma->dstu; -+ while (u != 0) { -+ if (i == HIFN_D_DST_RSIZE) -+ i = 0; -+#if 0 -+ bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, -+ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); -+#endif -+ if (dma->dstr[i].l & htole32(HIFN_D_VALID)) { -+#if 0 -+ bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+#endif -+ break; -+ } -+ i++, u--; -+ } -+ dma->dstk = i; dma->dstu = u; -+ -+ hifnstats.hst_obytes += cmd->dst_mapsize; -+ -+ if ((cmd->base_masks & (HIFN_BASE_CMD_CRYPT | HIFN_BASE_CMD_DECODE)) == -+ HIFN_BASE_CMD_CRYPT) { -+ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { -+ if (crd->crd_alg != CRYPTO_DES_CBC && -+ crd->crd_alg != CRYPTO_3DES_CBC && -+ crd->crd_alg != CRYPTO_AES_CBC) -+ continue; -+ ivlen = ((crd->crd_alg == CRYPTO_AES_CBC) ? -+ HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH); -+ crypto_copydata(crp->crp_flags, crp->crp_buf, -+ crd->crd_skip + crd->crd_len - ivlen, ivlen, -+ cmd->softc->sc_sessions[cmd->session_num].hs_iv); -+ break; -+ } -+ } -+ -+ if (macbuf != NULL) { -+ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { -+ int len; -+ -+ if (crd->crd_alg != CRYPTO_MD5 && -+ crd->crd_alg != CRYPTO_SHA1 && -+ crd->crd_alg != CRYPTO_MD5_HMAC && -+ crd->crd_alg != CRYPTO_SHA1_HMAC) { -+ continue; -+ } -+ len = cmd->softc->sc_sessions[cmd->session_num].hs_mlen; -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, len, macbuf); -+ break; -+ } -+ } -+ -+ if (cmd->src_map != cmd->dst_map) -+ pci_unmap_buf(sc, &cmd->dst); -+ pci_unmap_buf(sc, &cmd->src); -+ kfree(cmd); -+ crypto_done(crp); -+} -+ -+/* -+ * 7811 PB3 rev/2 parts lock-up on burst writes to Group 0 -+ * and Group 1 registers; avoid conditions that could create -+ * burst writes by doing a read in between the writes. -+ * -+ * NB: The read we interpose is always to the same register; -+ * we do this because reading from an arbitrary (e.g. last) -+ * register may not always work. -+ */ -+static void -+hifn_write_reg_0(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) -+{ -+ if (sc->sc_flags & HIFN_IS_7811) { -+ if (sc->sc_bar0_lastreg == reg - 4) -+ readl(sc->sc_bar0 + HIFN_0_PUCNFG); -+ sc->sc_bar0_lastreg = reg; -+ } -+ writel(val, sc->sc_bar0 + reg); -+} -+ -+static void -+hifn_write_reg_1(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) -+{ -+ if (sc->sc_flags & HIFN_IS_7811) { -+ if (sc->sc_bar1_lastreg == reg - 4) -+ readl(sc->sc_bar1 + HIFN_1_REVID); -+ sc->sc_bar1_lastreg = reg; -+ } -+ writel(val, sc->sc_bar1 + reg); -+} -+ -+ -+static struct pci_device_id hifn_pci_tbl[] = { -+ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7951, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7955, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7956, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ { PCI_VENDOR_NETSEC, PCI_PRODUCT_NETSEC_7751, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ { PCI_VENDOR_INVERTEX, PCI_PRODUCT_INVERTEX_AEON, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7811, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ /* -+ * Other vendors share this PCI ID as well, such as -+ * http://www.powercrypt.com, and obviously they also -+ * use the same key. -+ */ -+ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7751, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ { 0, 0, 0, 0, 0, 0, } -+}; -+MODULE_DEVICE_TABLE(pci, hifn_pci_tbl); -+ -+static struct pci_driver hifn_driver = { -+ .name = "hifn", -+ .id_table = hifn_pci_tbl, -+ .probe = hifn_probe, -+ .remove = hifn_remove, -+ /* add PM stuff here one day */ -+}; -+ -+static int __init hifn_init (void) -+{ -+ struct hifn_softc *sc = NULL; -+ int rc; -+ -+ DPRINTF("%s(%p)\n", __FUNCTION__, hifn_init); -+ -+ rc = pci_register_driver(&hifn_driver); -+ pci_register_driver_compat(&hifn_driver, rc); -+ -+ return rc; -+} -+ -+static void __exit hifn_exit (void) -+{ -+ pci_unregister_driver(&hifn_driver); -+} -+ -+module_init(hifn_init); -+module_exit(hifn_exit); -+ -+MODULE_LICENSE("BSD"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("OCF driver for hifn PCI crypto devices"); -diff -Nur linux-2.6.36.orig/crypto/ocf/hifn/hifn7751reg.h linux-2.6.36/crypto/ocf/hifn/hifn7751reg.h ---- linux-2.6.36.orig/crypto/ocf/hifn/hifn7751reg.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/hifn/hifn7751reg.h 2010-11-09 20:28:04.792495416 +0100 -@@ -0,0 +1,540 @@ -+/* $FreeBSD: src/sys/dev/hifn/hifn7751reg.h,v 1.7 2007/03/21 03:42:49 sam Exp $ */ -+/* $OpenBSD: hifn7751reg.h,v 1.35 2002/04/08 17:49:42 jason Exp $ */ -+ -+/*- -+ * Invertex AEON / Hifn 7751 driver -+ * Copyright (c) 1999 Invertex Inc. All rights reserved. -+ * Copyright (c) 1999 Theo de Raadt -+ * Copyright (c) 2000-2001 Network Security Technologies, Inc. -+ * http://www.netsec.net -+ * -+ * Please send any comments, feedback, bug-fixes, or feature requests to -+ * software@invertex.com. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored in part by the Defense Advanced Research Projects -+ * Agency (DARPA) and Air Force Research Laboratory, Air Force -+ * Materiel Command, USAF, under agreement number F30602-01-2-0537. -+ * -+ */ -+#ifndef __HIFN_H__ -+#define __HIFN_H__ -+ -+/* -+ * Some PCI configuration space offset defines. The names were made -+ * identical to the names used by the Linux kernel. -+ */ -+#define HIFN_BAR0 PCIR_BAR(0) /* PUC register map */ -+#define HIFN_BAR1 PCIR_BAR(1) /* DMA register map */ -+#define HIFN_TRDY_TIMEOUT 0x40 -+#define HIFN_RETRY_TIMEOUT 0x41 -+ -+/* -+ * PCI vendor and device identifiers -+ * (the names are preserved from their OpenBSD source). -+ */ -+#define PCI_VENDOR_HIFN 0x13a3 /* Hifn */ -+#define PCI_PRODUCT_HIFN_7751 0x0005 /* 7751 */ -+#define PCI_PRODUCT_HIFN_6500 0x0006 /* 6500 */ -+#define PCI_PRODUCT_HIFN_7811 0x0007 /* 7811 */ -+#define PCI_PRODUCT_HIFN_7855 0x001f /* 7855 */ -+#define PCI_PRODUCT_HIFN_7951 0x0012 /* 7951 */ -+#define PCI_PRODUCT_HIFN_7955 0x0020 /* 7954/7955 */ -+#define PCI_PRODUCT_HIFN_7956 0x001d /* 7956 */ -+ -+#define PCI_VENDOR_INVERTEX 0x14e1 /* Invertex */ -+#define PCI_PRODUCT_INVERTEX_AEON 0x0005 /* AEON */ -+ -+#define PCI_VENDOR_NETSEC 0x1660 /* NetSec */ -+#define PCI_PRODUCT_NETSEC_7751 0x7751 /* 7751 */ -+ -+/* -+ * The values below should multiple of 4 -- and be large enough to handle -+ * any command the driver implements. -+ * -+ * MAX_COMMAND = base command + mac command + encrypt command + -+ * mac-key + rc4-key -+ * MAX_RESULT = base result + mac result + mac + encrypt result -+ * -+ * -+ */ -+#define HIFN_MAX_COMMAND (8 + 8 + 8 + 64 + 260) -+#define HIFN_MAX_RESULT (8 + 4 + 20 + 4) -+ -+/* -+ * hifn_desc_t -+ * -+ * Holds an individual descriptor for any of the rings. -+ */ -+typedef struct hifn_desc { -+ volatile u_int32_t l; /* length and status bits */ -+ volatile u_int32_t p; -+} hifn_desc_t; -+ -+/* -+ * Masks for the "length" field of struct hifn_desc. -+ */ -+#define HIFN_D_LENGTH 0x0000ffff /* length bit mask */ -+#define HIFN_D_MASKDONEIRQ 0x02000000 /* mask the done interrupt */ -+#define HIFN_D_DESTOVER 0x04000000 /* destination overflow */ -+#define HIFN_D_OVER 0x08000000 /* overflow */ -+#define HIFN_D_LAST 0x20000000 /* last descriptor in chain */ -+#define HIFN_D_JUMP 0x40000000 /* jump descriptor */ -+#define HIFN_D_VALID 0x80000000 /* valid bit */ -+ -+ -+/* -+ * Processing Unit Registers (offset from BASEREG0) -+ */ -+#define HIFN_0_PUDATA 0x00 /* Processing Unit Data */ -+#define HIFN_0_PUCTRL 0x04 /* Processing Unit Control */ -+#define HIFN_0_PUISR 0x08 /* Processing Unit Interrupt Status */ -+#define HIFN_0_PUCNFG 0x0c /* Processing Unit Configuration */ -+#define HIFN_0_PUIER 0x10 /* Processing Unit Interrupt Enable */ -+#define HIFN_0_PUSTAT 0x14 /* Processing Unit Status/Chip ID */ -+#define HIFN_0_FIFOSTAT 0x18 /* FIFO Status */ -+#define HIFN_0_FIFOCNFG 0x1c /* FIFO Configuration */ -+#define HIFN_0_PUCTRL2 0x28 /* Processing Unit Control (2nd map) */ -+#define HIFN_0_MUTE1 0x80 -+#define HIFN_0_MUTE2 0x90 -+#define HIFN_0_SPACESIZE 0x100 /* Register space size */ -+ -+/* Processing Unit Control Register (HIFN_0_PUCTRL) */ -+#define HIFN_PUCTRL_CLRSRCFIFO 0x0010 /* clear source fifo */ -+#define HIFN_PUCTRL_STOP 0x0008 /* stop pu */ -+#define HIFN_PUCTRL_LOCKRAM 0x0004 /* lock ram */ -+#define HIFN_PUCTRL_DMAENA 0x0002 /* enable dma */ -+#define HIFN_PUCTRL_RESET 0x0001 /* Reset processing unit */ -+ -+/* Processing Unit Interrupt Status Register (HIFN_0_PUISR) */ -+#define HIFN_PUISR_CMDINVAL 0x8000 /* Invalid command interrupt */ -+#define HIFN_PUISR_DATAERR 0x4000 /* Data error interrupt */ -+#define HIFN_PUISR_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ -+#define HIFN_PUISR_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ -+#define HIFN_PUISR_DSTOVER 0x0200 /* Destination overrun interrupt */ -+#define HIFN_PUISR_SRCCMD 0x0080 /* Source command interrupt */ -+#define HIFN_PUISR_SRCCTX 0x0040 /* Source context interrupt */ -+#define HIFN_PUISR_SRCDATA 0x0020 /* Source data interrupt */ -+#define HIFN_PUISR_DSTDATA 0x0010 /* Destination data interrupt */ -+#define HIFN_PUISR_DSTRESULT 0x0004 /* Destination result interrupt */ -+ -+/* Processing Unit Configuration Register (HIFN_0_PUCNFG) */ -+#define HIFN_PUCNFG_DRAMMASK 0xe000 /* DRAM size mask */ -+#define HIFN_PUCNFG_DSZ_256K 0x0000 /* 256k dram */ -+#define HIFN_PUCNFG_DSZ_512K 0x2000 /* 512k dram */ -+#define HIFN_PUCNFG_DSZ_1M 0x4000 /* 1m dram */ -+#define HIFN_PUCNFG_DSZ_2M 0x6000 /* 2m dram */ -+#define HIFN_PUCNFG_DSZ_4M 0x8000 /* 4m dram */ -+#define HIFN_PUCNFG_DSZ_8M 0xa000 /* 8m dram */ -+#define HIFN_PUNCFG_DSZ_16M 0xc000 /* 16m dram */ -+#define HIFN_PUCNFG_DSZ_32M 0xe000 /* 32m dram */ -+#define HIFN_PUCNFG_DRAMREFRESH 0x1800 /* DRAM refresh rate mask */ -+#define HIFN_PUCNFG_DRFR_512 0x0000 /* 512 divisor of ECLK */ -+#define HIFN_PUCNFG_DRFR_256 0x0800 /* 256 divisor of ECLK */ -+#define HIFN_PUCNFG_DRFR_128 0x1000 /* 128 divisor of ECLK */ -+#define HIFN_PUCNFG_TCALLPHASES 0x0200 /* your guess is as good as mine... */ -+#define HIFN_PUCNFG_TCDRVTOTEM 0x0100 /* your guess is as good as mine... */ -+#define HIFN_PUCNFG_BIGENDIAN 0x0080 /* DMA big endian mode */ -+#define HIFN_PUCNFG_BUS32 0x0040 /* Bus width 32bits */ -+#define HIFN_PUCNFG_BUS16 0x0000 /* Bus width 16 bits */ -+#define HIFN_PUCNFG_CHIPID 0x0020 /* Allow chipid from PUSTAT */ -+#define HIFN_PUCNFG_DRAM 0x0010 /* Context RAM is DRAM */ -+#define HIFN_PUCNFG_SRAM 0x0000 /* Context RAM is SRAM */ -+#define HIFN_PUCNFG_COMPSING 0x0004 /* Enable single compression context */ -+#define HIFN_PUCNFG_ENCCNFG 0x0002 /* Encryption configuration */ -+ -+/* Processing Unit Interrupt Enable Register (HIFN_0_PUIER) */ -+#define HIFN_PUIER_CMDINVAL 0x8000 /* Invalid command interrupt */ -+#define HIFN_PUIER_DATAERR 0x4000 /* Data error interrupt */ -+#define HIFN_PUIER_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ -+#define HIFN_PUIER_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ -+#define HIFN_PUIER_DSTOVER 0x0200 /* Destination overrun interrupt */ -+#define HIFN_PUIER_SRCCMD 0x0080 /* Source command interrupt */ -+#define HIFN_PUIER_SRCCTX 0x0040 /* Source context interrupt */ -+#define HIFN_PUIER_SRCDATA 0x0020 /* Source data interrupt */ -+#define HIFN_PUIER_DSTDATA 0x0010 /* Destination data interrupt */ -+#define HIFN_PUIER_DSTRESULT 0x0004 /* Destination result interrupt */ -+ -+/* Processing Unit Status Register/Chip ID (HIFN_0_PUSTAT) */ -+#define HIFN_PUSTAT_CMDINVAL 0x8000 /* Invalid command interrupt */ -+#define HIFN_PUSTAT_DATAERR 0x4000 /* Data error interrupt */ -+#define HIFN_PUSTAT_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ -+#define HIFN_PUSTAT_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ -+#define HIFN_PUSTAT_DSTOVER 0x0200 /* Destination overrun interrupt */ -+#define HIFN_PUSTAT_SRCCMD 0x0080 /* Source command interrupt */ -+#define HIFN_PUSTAT_SRCCTX 0x0040 /* Source context interrupt */ -+#define HIFN_PUSTAT_SRCDATA 0x0020 /* Source data interrupt */ -+#define HIFN_PUSTAT_DSTDATA 0x0010 /* Destination data interrupt */ -+#define HIFN_PUSTAT_DSTRESULT 0x0004 /* Destination result interrupt */ -+#define HIFN_PUSTAT_CHIPREV 0x00ff /* Chip revision mask */ -+#define HIFN_PUSTAT_CHIPENA 0xff00 /* Chip enabled mask */ -+#define HIFN_PUSTAT_ENA_2 0x1100 /* Level 2 enabled */ -+#define HIFN_PUSTAT_ENA_1 0x1000 /* Level 1 enabled */ -+#define HIFN_PUSTAT_ENA_0 0x3000 /* Level 0 enabled */ -+#define HIFN_PUSTAT_REV_2 0x0020 /* 7751 PT6/2 */ -+#define HIFN_PUSTAT_REV_3 0x0030 /* 7751 PT6/3 */ -+ -+/* FIFO Status Register (HIFN_0_FIFOSTAT) */ -+#define HIFN_FIFOSTAT_SRC 0x7f00 /* Source FIFO available */ -+#define HIFN_FIFOSTAT_DST 0x007f /* Destination FIFO available */ -+ -+/* FIFO Configuration Register (HIFN_0_FIFOCNFG) */ -+#define HIFN_FIFOCNFG_THRESHOLD 0x0400 /* must be written as this value */ -+ -+/* -+ * DMA Interface Registers (offset from BASEREG1) -+ */ -+#define HIFN_1_DMA_CRAR 0x0c /* DMA Command Ring Address */ -+#define HIFN_1_DMA_SRAR 0x1c /* DMA Source Ring Address */ -+#define HIFN_1_DMA_RRAR 0x2c /* DMA Result Ring Address */ -+#define HIFN_1_DMA_DRAR 0x3c /* DMA Destination Ring Address */ -+#define HIFN_1_DMA_CSR 0x40 /* DMA Status and Control */ -+#define HIFN_1_DMA_IER 0x44 /* DMA Interrupt Enable */ -+#define HIFN_1_DMA_CNFG 0x48 /* DMA Configuration */ -+#define HIFN_1_PLL 0x4c /* 7955/7956: PLL config */ -+#define HIFN_1_7811_RNGENA 0x60 /* 7811: rng enable */ -+#define HIFN_1_7811_RNGCFG 0x64 /* 7811: rng config */ -+#define HIFN_1_7811_RNGDAT 0x68 /* 7811: rng data */ -+#define HIFN_1_7811_RNGSTS 0x6c /* 7811: rng status */ -+#define HIFN_1_DMA_CNFG2 0x6c /* 7955/7956: dma config #2 */ -+#define HIFN_1_7811_MIPSRST 0x94 /* 7811: MIPS reset */ -+#define HIFN_1_REVID 0x98 /* Revision ID */ -+ -+#define HIFN_1_PUB_RESET 0x204 /* Public/RNG Reset */ -+#define HIFN_1_PUB_BASE 0x300 /* Public Base Address */ -+#define HIFN_1_PUB_OPLEN 0x304 /* 7951-compat Public Operand Length */ -+#define HIFN_1_PUB_OP 0x308 /* 7951-compat Public Operand */ -+#define HIFN_1_PUB_STATUS 0x30c /* 7951-compat Public Status */ -+#define HIFN_1_PUB_IEN 0x310 /* Public Interrupt enable */ -+#define HIFN_1_RNG_CONFIG 0x314 /* RNG config */ -+#define HIFN_1_RNG_DATA 0x318 /* RNG data */ -+#define HIFN_1_PUB_MODE 0x320 /* PK mode */ -+#define HIFN_1_PUB_FIFO_OPLEN 0x380 /* first element of oplen fifo */ -+#define HIFN_1_PUB_FIFO_OP 0x384 /* first element of op fifo */ -+#define HIFN_1_PUB_MEM 0x400 /* start of Public key memory */ -+#define HIFN_1_PUB_MEMEND 0xbff /* end of Public key memory */ -+ -+/* DMA Status and Control Register (HIFN_1_DMA_CSR) */ -+#define HIFN_DMACSR_D_CTRLMASK 0xc0000000 /* Destinition Ring Control */ -+#define HIFN_DMACSR_D_CTRL_NOP 0x00000000 /* Dest. Control: no-op */ -+#define HIFN_DMACSR_D_CTRL_DIS 0x40000000 /* Dest. Control: disable */ -+#define HIFN_DMACSR_D_CTRL_ENA 0x80000000 /* Dest. Control: enable */ -+#define HIFN_DMACSR_D_ABORT 0x20000000 /* Destinition Ring PCIAbort */ -+#define HIFN_DMACSR_D_DONE 0x10000000 /* Destinition Ring Done */ -+#define HIFN_DMACSR_D_LAST 0x08000000 /* Destinition Ring Last */ -+#define HIFN_DMACSR_D_WAIT 0x04000000 /* Destinition Ring Waiting */ -+#define HIFN_DMACSR_D_OVER 0x02000000 /* Destinition Ring Overflow */ -+#define HIFN_DMACSR_R_CTRL 0x00c00000 /* Result Ring Control */ -+#define HIFN_DMACSR_R_CTRL_NOP 0x00000000 /* Result Control: no-op */ -+#define HIFN_DMACSR_R_CTRL_DIS 0x00400000 /* Result Control: disable */ -+#define HIFN_DMACSR_R_CTRL_ENA 0x00800000 /* Result Control: enable */ -+#define HIFN_DMACSR_R_ABORT 0x00200000 /* Result Ring PCI Abort */ -+#define HIFN_DMACSR_R_DONE 0x00100000 /* Result Ring Done */ -+#define HIFN_DMACSR_R_LAST 0x00080000 /* Result Ring Last */ -+#define HIFN_DMACSR_R_WAIT 0x00040000 /* Result Ring Waiting */ -+#define HIFN_DMACSR_R_OVER 0x00020000 /* Result Ring Overflow */ -+#define HIFN_DMACSR_S_CTRL 0x0000c000 /* Source Ring Control */ -+#define HIFN_DMACSR_S_CTRL_NOP 0x00000000 /* Source Control: no-op */ -+#define HIFN_DMACSR_S_CTRL_DIS 0x00004000 /* Source Control: disable */ -+#define HIFN_DMACSR_S_CTRL_ENA 0x00008000 /* Source Control: enable */ -+#define HIFN_DMACSR_S_ABORT 0x00002000 /* Source Ring PCI Abort */ -+#define HIFN_DMACSR_S_DONE 0x00001000 /* Source Ring Done */ -+#define HIFN_DMACSR_S_LAST 0x00000800 /* Source Ring Last */ -+#define HIFN_DMACSR_S_WAIT 0x00000400 /* Source Ring Waiting */ -+#define HIFN_DMACSR_ILLW 0x00000200 /* Illegal write (7811 only) */ -+#define HIFN_DMACSR_ILLR 0x00000100 /* Illegal read (7811 only) */ -+#define HIFN_DMACSR_C_CTRL 0x000000c0 /* Command Ring Control */ -+#define HIFN_DMACSR_C_CTRL_NOP 0x00000000 /* Command Control: no-op */ -+#define HIFN_DMACSR_C_CTRL_DIS 0x00000040 /* Command Control: disable */ -+#define HIFN_DMACSR_C_CTRL_ENA 0x00000080 /* Command Control: enable */ -+#define HIFN_DMACSR_C_ABORT 0x00000020 /* Command Ring PCI Abort */ -+#define HIFN_DMACSR_C_DONE 0x00000010 /* Command Ring Done */ -+#define HIFN_DMACSR_C_LAST 0x00000008 /* Command Ring Last */ -+#define HIFN_DMACSR_C_WAIT 0x00000004 /* Command Ring Waiting */ -+#define HIFN_DMACSR_PUBDONE 0x00000002 /* Public op done (7951 only) */ -+#define HIFN_DMACSR_ENGINE 0x00000001 /* Command Ring Engine IRQ */ -+ -+/* DMA Interrupt Enable Register (HIFN_1_DMA_IER) */ -+#define HIFN_DMAIER_D_ABORT 0x20000000 /* Destination Ring PCIAbort */ -+#define HIFN_DMAIER_D_DONE 0x10000000 /* Destination Ring Done */ -+#define HIFN_DMAIER_D_LAST 0x08000000 /* Destination Ring Last */ -+#define HIFN_DMAIER_D_WAIT 0x04000000 /* Destination Ring Waiting */ -+#define HIFN_DMAIER_D_OVER 0x02000000 /* Destination Ring Overflow */ -+#define HIFN_DMAIER_R_ABORT 0x00200000 /* Result Ring PCI Abort */ -+#define HIFN_DMAIER_R_DONE 0x00100000 /* Result Ring Done */ -+#define HIFN_DMAIER_R_LAST 0x00080000 /* Result Ring Last */ -+#define HIFN_DMAIER_R_WAIT 0x00040000 /* Result Ring Waiting */ -+#define HIFN_DMAIER_R_OVER 0x00020000 /* Result Ring Overflow */ -+#define HIFN_DMAIER_S_ABORT 0x00002000 /* Source Ring PCI Abort */ -+#define HIFN_DMAIER_S_DONE 0x00001000 /* Source Ring Done */ -+#define HIFN_DMAIER_S_LAST 0x00000800 /* Source Ring Last */ -+#define HIFN_DMAIER_S_WAIT 0x00000400 /* Source Ring Waiting */ -+#define HIFN_DMAIER_ILLW 0x00000200 /* Illegal write (7811 only) */ -+#define HIFN_DMAIER_ILLR 0x00000100 /* Illegal read (7811 only) */ -+#define HIFN_DMAIER_C_ABORT 0x00000020 /* Command Ring PCI Abort */ -+#define HIFN_DMAIER_C_DONE 0x00000010 /* Command Ring Done */ -+#define HIFN_DMAIER_C_LAST 0x00000008 /* Command Ring Last */ -+#define HIFN_DMAIER_C_WAIT 0x00000004 /* Command Ring Waiting */ -+#define HIFN_DMAIER_PUBDONE 0x00000002 /* public op done (7951 only) */ -+#define HIFN_DMAIER_ENGINE 0x00000001 /* Engine IRQ */ -+ -+/* DMA Configuration Register (HIFN_1_DMA_CNFG) */ -+#define HIFN_DMACNFG_BIGENDIAN 0x10000000 /* big endian mode */ -+#define HIFN_DMACNFG_POLLFREQ 0x00ff0000 /* Poll frequency mask */ -+#define HIFN_DMACNFG_UNLOCK 0x00000800 -+#define HIFN_DMACNFG_POLLINVAL 0x00000700 /* Invalid Poll Scalar */ -+#define HIFN_DMACNFG_LAST 0x00000010 /* Host control LAST bit */ -+#define HIFN_DMACNFG_MODE 0x00000004 /* DMA mode */ -+#define HIFN_DMACNFG_DMARESET 0x00000002 /* DMA Reset # */ -+#define HIFN_DMACNFG_MSTRESET 0x00000001 /* Master Reset # */ -+ -+/* DMA Configuration Register (HIFN_1_DMA_CNFG2) */ -+#define HIFN_DMACNFG2_PKSWAP32 (1 << 19) /* swap the OPLEN/OP reg */ -+#define HIFN_DMACNFG2_PKSWAP8 (1 << 18) /* swap the bits of OPLEN/OP */ -+#define HIFN_DMACNFG2_BAR0_SWAP32 (1<<17) /* swap the bytes of BAR0 */ -+#define HIFN_DMACNFG2_BAR1_SWAP8 (1<<16) /* swap the bits of BAR0 */ -+#define HIFN_DMACNFG2_INIT_WRITE_BURST_SHIFT 12 -+#define HIFN_DMACNFG2_INIT_READ_BURST_SHIFT 8 -+#define HIFN_DMACNFG2_TGT_WRITE_BURST_SHIFT 4 -+#define HIFN_DMACNFG2_TGT_READ_BURST_SHIFT 0 -+ -+/* 7811 RNG Enable Register (HIFN_1_7811_RNGENA) */ -+#define HIFN_7811_RNGENA_ENA 0x00000001 /* enable RNG */ -+ -+/* 7811 RNG Config Register (HIFN_1_7811_RNGCFG) */ -+#define HIFN_7811_RNGCFG_PRE1 0x00000f00 /* first prescalar */ -+#define HIFN_7811_RNGCFG_OPRE 0x00000080 /* output prescalar */ -+#define HIFN_7811_RNGCFG_DEFL 0x00000f80 /* 2 words/ 1/100 sec */ -+ -+/* 7811 RNG Status Register (HIFN_1_7811_RNGSTS) */ -+#define HIFN_7811_RNGSTS_RDY 0x00004000 /* two numbers in FIFO */ -+#define HIFN_7811_RNGSTS_UFL 0x00001000 /* rng underflow */ -+ -+/* 7811 MIPS Reset Register (HIFN_1_7811_MIPSRST) */ -+#define HIFN_MIPSRST_BAR2SIZE 0xffff0000 /* sdram size */ -+#define HIFN_MIPSRST_GPRAMINIT 0x00008000 /* gpram can be accessed */ -+#define HIFN_MIPSRST_CRAMINIT 0x00004000 /* ctxram can be accessed */ -+#define HIFN_MIPSRST_LED2 0x00000400 /* external LED2 */ -+#define HIFN_MIPSRST_LED1 0x00000200 /* external LED1 */ -+#define HIFN_MIPSRST_LED0 0x00000100 /* external LED0 */ -+#define HIFN_MIPSRST_MIPSDIS 0x00000004 /* disable MIPS */ -+#define HIFN_MIPSRST_MIPSRST 0x00000002 /* warm reset MIPS */ -+#define HIFN_MIPSRST_MIPSCOLD 0x00000001 /* cold reset MIPS */ -+ -+/* Public key reset register (HIFN_1_PUB_RESET) */ -+#define HIFN_PUBRST_RESET 0x00000001 /* reset public/rng unit */ -+ -+/* Public operation register (HIFN_1_PUB_OP) */ -+#define HIFN_PUBOP_AOFFSET 0x0000003e /* A offset */ -+#define HIFN_PUBOP_BOFFSET 0x00000fc0 /* B offset */ -+#define HIFN_PUBOP_MOFFSET 0x0003f000 /* M offset */ -+#define HIFN_PUBOP_OP_MASK 0x003c0000 /* Opcode: */ -+#define HIFN_PUBOP_OP_NOP 0x00000000 /* NOP */ -+#define HIFN_PUBOP_OP_ADD 0x00040000 /* ADD */ -+#define HIFN_PUBOP_OP_ADDC 0x00080000 /* ADD w/carry */ -+#define HIFN_PUBOP_OP_SUB 0x000c0000 /* SUB */ -+#define HIFN_PUBOP_OP_SUBC 0x00100000 /* SUB w/carry */ -+#define HIFN_PUBOP_OP_MODADD 0x00140000 /* Modular ADD */ -+#define HIFN_PUBOP_OP_MODSUB 0x00180000 /* Modular SUB */ -+#define HIFN_PUBOP_OP_INCA 0x001c0000 /* INC A */ -+#define HIFN_PUBOP_OP_DECA 0x00200000 /* DEC A */ -+#define HIFN_PUBOP_OP_MULT 0x00240000 /* MULT */ -+#define HIFN_PUBOP_OP_MODMULT 0x00280000 /* Modular MULT */ -+#define HIFN_PUBOP_OP_MODRED 0x002c0000 /* Modular Red */ -+#define HIFN_PUBOP_OP_MODEXP 0x00300000 /* Modular Exp */ -+ -+/* Public operand length register (HIFN_1_PUB_OPLEN) */ -+#define HIFN_PUBOPLEN_MODLEN 0x0000007f -+#define HIFN_PUBOPLEN_EXPLEN 0x0003ff80 -+#define HIFN_PUBOPLEN_REDLEN 0x003c0000 -+ -+/* Public status register (HIFN_1_PUB_STATUS) */ -+#define HIFN_PUBSTS_DONE 0x00000001 /* operation done */ -+#define HIFN_PUBSTS_CARRY 0x00000002 /* carry */ -+#define HIFN_PUBSTS_FIFO_EMPTY 0x00000100 /* fifo empty */ -+#define HIFN_PUBSTS_FIFO_FULL 0x00000200 /* fifo full */ -+#define HIFN_PUBSTS_FIFO_OVFL 0x00000400 /* fifo overflow */ -+#define HIFN_PUBSTS_FIFO_WRITE 0x000f0000 /* fifo write */ -+#define HIFN_PUBSTS_FIFO_READ 0x0f000000 /* fifo read */ -+ -+/* Public interrupt enable register (HIFN_1_PUB_IEN) */ -+#define HIFN_PUBIEN_DONE 0x00000001 /* operation done interrupt */ -+ -+/* Random number generator config register (HIFN_1_RNG_CONFIG) */ -+#define HIFN_RNGCFG_ENA 0x00000001 /* enable rng */ -+ -+/* -+ * Register offsets in register set 1 -+ */ -+ -+#define HIFN_UNLOCK_SECRET1 0xf4 -+#define HIFN_UNLOCK_SECRET2 0xfc -+ -+/* -+ * PLL config register -+ * -+ * This register is present only on 7954/7955/7956 parts. It must be -+ * programmed according to the bus interface method used by the h/w. -+ * Note that the parts require a stable clock. Since the PCI clock -+ * may vary the reference clock must usually be used. To avoid -+ * overclocking the core logic, setup must be done carefully, refer -+ * to the driver for details. The exact multiplier required varies -+ * by part and system configuration; refer to the Hifn documentation. -+ */ -+#define HIFN_PLL_REF_SEL 0x00000001 /* REF/HBI clk selection */ -+#define HIFN_PLL_BP 0x00000002 /* bypass (used during setup) */ -+/* bit 2 reserved */ -+#define HIFN_PLL_PK_CLK_SEL 0x00000008 /* public key clk select */ -+#define HIFN_PLL_PE_CLK_SEL 0x00000010 /* packet engine clk select */ -+/* bits 5-9 reserved */ -+#define HIFN_PLL_MBSET 0x00000400 /* must be set to 1 */ -+#define HIFN_PLL_ND 0x00003800 /* Fpll_ref multiplier select */ -+#define HIFN_PLL_ND_SHIFT 11 -+#define HIFN_PLL_ND_2 0x00000000 /* 2x */ -+#define HIFN_PLL_ND_4 0x00000800 /* 4x */ -+#define HIFN_PLL_ND_6 0x00001000 /* 6x */ -+#define HIFN_PLL_ND_8 0x00001800 /* 8x */ -+#define HIFN_PLL_ND_10 0x00002000 /* 10x */ -+#define HIFN_PLL_ND_12 0x00002800 /* 12x */ -+/* bits 14-15 reserved */ -+#define HIFN_PLL_IS 0x00010000 /* charge pump current select */ -+/* bits 17-31 reserved */ -+ -+/* -+ * Board configuration specifies only these bits. -+ */ -+#define HIFN_PLL_CONFIG (HIFN_PLL_IS|HIFN_PLL_ND|HIFN_PLL_REF_SEL) -+ -+/* -+ * Public Key Engine Mode Register -+ */ -+#define HIFN_PKMODE_HOSTINVERT (1 << 0) /* HOST INVERT */ -+#define HIFN_PKMODE_ENHANCED (1 << 1) /* Enable enhanced mode */ -+ -+ -+/********************************************************************* -+ * Structs for board commands -+ * -+ *********************************************************************/ -+ -+/* -+ * Structure to help build up the command data structure. -+ */ -+typedef struct hifn_base_command { -+ volatile u_int16_t masks; -+ volatile u_int16_t session_num; -+ volatile u_int16_t total_source_count; -+ volatile u_int16_t total_dest_count; -+} hifn_base_command_t; -+ -+#define HIFN_BASE_CMD_MAC 0x0400 -+#define HIFN_BASE_CMD_CRYPT 0x0800 -+#define HIFN_BASE_CMD_DECODE 0x2000 -+#define HIFN_BASE_CMD_SRCLEN_M 0xc000 -+#define HIFN_BASE_CMD_SRCLEN_S 14 -+#define HIFN_BASE_CMD_DSTLEN_M 0x3000 -+#define HIFN_BASE_CMD_DSTLEN_S 12 -+#define HIFN_BASE_CMD_LENMASK_HI 0x30000 -+#define HIFN_BASE_CMD_LENMASK_LO 0x0ffff -+ -+/* -+ * Structure to help build up the command data structure. -+ */ -+typedef struct hifn_crypt_command { -+ volatile u_int16_t masks; -+ volatile u_int16_t header_skip; -+ volatile u_int16_t source_count; -+ volatile u_int16_t reserved; -+} hifn_crypt_command_t; -+ -+#define HIFN_CRYPT_CMD_ALG_MASK 0x0003 /* algorithm: */ -+#define HIFN_CRYPT_CMD_ALG_DES 0x0000 /* DES */ -+#define HIFN_CRYPT_CMD_ALG_3DES 0x0001 /* 3DES */ -+#define HIFN_CRYPT_CMD_ALG_RC4 0x0002 /* RC4 */ -+#define HIFN_CRYPT_CMD_ALG_AES 0x0003 /* AES */ -+#define HIFN_CRYPT_CMD_MODE_MASK 0x0018 /* Encrypt mode: */ -+#define HIFN_CRYPT_CMD_MODE_ECB 0x0000 /* ECB */ -+#define HIFN_CRYPT_CMD_MODE_CBC 0x0008 /* CBC */ -+#define HIFN_CRYPT_CMD_MODE_CFB 0x0010 /* CFB */ -+#define HIFN_CRYPT_CMD_MODE_OFB 0x0018 /* OFB */ -+#define HIFN_CRYPT_CMD_CLR_CTX 0x0040 /* clear context */ -+#define HIFN_CRYPT_CMD_NEW_KEY 0x0800 /* expect new key */ -+#define HIFN_CRYPT_CMD_NEW_IV 0x1000 /* expect new iv */ -+ -+#define HIFN_CRYPT_CMD_SRCLEN_M 0xc000 -+#define HIFN_CRYPT_CMD_SRCLEN_S 14 -+ -+#define HIFN_CRYPT_CMD_KSZ_MASK 0x0600 /* AES key size: */ -+#define HIFN_CRYPT_CMD_KSZ_128 0x0000 /* 128 bit */ -+#define HIFN_CRYPT_CMD_KSZ_192 0x0200 /* 192 bit */ -+#define HIFN_CRYPT_CMD_KSZ_256 0x0400 /* 256 bit */ -+ -+/* -+ * Structure to help build up the command data structure. -+ */ -+typedef struct hifn_mac_command { -+ volatile u_int16_t masks; -+ volatile u_int16_t header_skip; -+ volatile u_int16_t source_count; -+ volatile u_int16_t reserved; -+} hifn_mac_command_t; -+ -+#define HIFN_MAC_CMD_ALG_MASK 0x0001 -+#define HIFN_MAC_CMD_ALG_SHA1 0x0000 -+#define HIFN_MAC_CMD_ALG_MD5 0x0001 -+#define HIFN_MAC_CMD_MODE_MASK 0x000c -+#define HIFN_MAC_CMD_MODE_HMAC 0x0000 -+#define HIFN_MAC_CMD_MODE_SSL_MAC 0x0004 -+#define HIFN_MAC_CMD_MODE_HASH 0x0008 -+#define HIFN_MAC_CMD_MODE_FULL 0x0004 -+#define HIFN_MAC_CMD_TRUNC 0x0010 -+#define HIFN_MAC_CMD_RESULT 0x0020 -+#define HIFN_MAC_CMD_APPEND 0x0040 -+#define HIFN_MAC_CMD_SRCLEN_M 0xc000 -+#define HIFN_MAC_CMD_SRCLEN_S 14 -+ -+/* -+ * MAC POS IPsec initiates authentication after encryption on encodes -+ * and before decryption on decodes. -+ */ -+#define HIFN_MAC_CMD_POS_IPSEC 0x0200 -+#define HIFN_MAC_CMD_NEW_KEY 0x0800 -+ -+/* -+ * The poll frequency and poll scalar defines are unshifted values used -+ * to set fields in the DMA Configuration Register. -+ */ -+#ifndef HIFN_POLL_FREQUENCY -+#define HIFN_POLL_FREQUENCY 0x1 -+#endif -+ -+#ifndef HIFN_POLL_SCALAR -+#define HIFN_POLL_SCALAR 0x0 -+#endif -+ -+#define HIFN_MAX_SEGLEN 0xffff /* maximum dma segment len */ -+#define HIFN_MAX_DMALEN 0x3ffff /* maximum dma length */ -+#endif /* __HIFN_H__ */ -diff -Nur linux-2.6.36.orig/crypto/ocf/hifn/hifn7751var.h linux-2.6.36/crypto/ocf/hifn/hifn7751var.h ---- linux-2.6.36.orig/crypto/ocf/hifn/hifn7751var.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/hifn/hifn7751var.h 2010-11-09 20:28:04.832495385 +0100 -@@ -0,0 +1,369 @@ -+/* $FreeBSD: src/sys/dev/hifn/hifn7751var.h,v 1.9 2007/03/21 03:42:49 sam Exp $ */ -+/* $OpenBSD: hifn7751var.h,v 1.42 2002/04/08 17:49:42 jason Exp $ */ -+ -+/*- -+ * Invertex AEON / Hifn 7751 driver -+ * Copyright (c) 1999 Invertex Inc. All rights reserved. -+ * Copyright (c) 1999 Theo de Raadt -+ * Copyright (c) 2000-2001 Network Security Technologies, Inc. -+ * http://www.netsec.net -+ * -+ * Please send any comments, feedback, bug-fixes, or feature requests to -+ * software@invertex.com. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored in part by the Defense Advanced Research Projects -+ * Agency (DARPA) and Air Force Research Laboratory, Air Force -+ * Materiel Command, USAF, under agreement number F30602-01-2-0537. -+ * -+ */ -+ -+#ifndef __HIFN7751VAR_H__ -+#define __HIFN7751VAR_H__ -+ -+#ifdef __KERNEL__ -+ -+/* -+ * Some configurable values for the driver. By default command+result -+ * descriptor rings are the same size. The src+dst descriptor rings -+ * are sized at 3.5x the number of potential commands. Slower parts -+ * (e.g. 7951) tend to run out of src descriptors; faster parts (7811) -+ * src+cmd/result descriptors. It's not clear that increasing the size -+ * of the descriptor rings helps performance significantly as other -+ * factors tend to come into play (e.g. copying misaligned packets). -+ */ -+#define HIFN_D_CMD_RSIZE 24 /* command descriptors */ -+#define HIFN_D_SRC_RSIZE ((HIFN_D_CMD_RSIZE * 7) / 2) /* source descriptors */ -+#define HIFN_D_RES_RSIZE HIFN_D_CMD_RSIZE /* result descriptors */ -+#define HIFN_D_DST_RSIZE HIFN_D_SRC_RSIZE /* destination descriptors */ -+ -+/* -+ * Length values for cryptography -+ */ -+#define HIFN_DES_KEY_LENGTH 8 -+#define HIFN_3DES_KEY_LENGTH 24 -+#define HIFN_MAX_CRYPT_KEY_LENGTH HIFN_3DES_KEY_LENGTH -+#define HIFN_IV_LENGTH 8 -+#define HIFN_AES_IV_LENGTH 16 -+#define HIFN_MAX_IV_LENGTH HIFN_AES_IV_LENGTH -+ -+/* -+ * Length values for authentication -+ */ -+#define HIFN_MAC_KEY_LENGTH 64 -+#define HIFN_MD5_LENGTH 16 -+#define HIFN_SHA1_LENGTH 20 -+#define HIFN_MAC_TRUNC_LENGTH 12 -+ -+#define MAX_SCATTER 64 -+ -+/* -+ * Data structure to hold all 4 rings and any other ring related data. -+ */ -+struct hifn_dma { -+ /* -+ * Descriptor rings. We add +1 to the size to accomidate the -+ * jump descriptor. -+ */ -+ struct hifn_desc cmdr[HIFN_D_CMD_RSIZE+1]; -+ struct hifn_desc srcr[HIFN_D_SRC_RSIZE+1]; -+ struct hifn_desc dstr[HIFN_D_DST_RSIZE+1]; -+ struct hifn_desc resr[HIFN_D_RES_RSIZE+1]; -+ -+ struct hifn_command *hifn_commands[HIFN_D_RES_RSIZE]; -+ -+ u_char command_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_COMMAND]; -+ u_char result_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_RESULT]; -+ u_int32_t slop[HIFN_D_CMD_RSIZE]; -+ -+ u_int64_t test_src, test_dst; -+ -+ /* -+ * Our current positions for insertion and removal from the desriptor -+ * rings. -+ */ -+ int cmdi, srci, dsti, resi; -+ volatile int cmdu, srcu, dstu, resu; -+ int cmdk, srck, dstk, resk; -+}; -+ -+struct hifn_session { -+ int hs_used; -+ int hs_mlen; -+ u_int8_t hs_iv[HIFN_MAX_IV_LENGTH]; -+}; -+ -+#define HIFN_RING_SYNC(sc, r, i, f) \ -+ /* DAVIDM bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, (f)) */ -+ -+#define HIFN_CMDR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), cmdr, (i), (f)) -+#define HIFN_RESR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), resr, (i), (f)) -+#define HIFN_SRCR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), srcr, (i), (f)) -+#define HIFN_DSTR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), dstr, (i), (f)) -+ -+#define HIFN_CMD_SYNC(sc, i, f) \ -+ /* DAVIDM bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, (f)) */ -+ -+#define HIFN_RES_SYNC(sc, i, f) \ -+ /* DAVIDM bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, (f)) */ -+ -+typedef int bus_size_t; -+ -+/* -+ * Holds data specific to a single HIFN board. -+ */ -+struct hifn_softc { -+ softc_device_decl sc_dev; -+ -+ struct pci_dev *sc_pcidev; /* PCI device pointer */ -+ spinlock_t sc_mtx; /* per-instance lock */ -+ -+ int sc_num; /* for multiple devs */ -+ -+ ocf_iomem_t sc_bar0; -+ bus_size_t sc_bar0_lastreg;/* bar0 last reg written */ -+ ocf_iomem_t sc_bar1; -+ bus_size_t sc_bar1_lastreg;/* bar1 last reg written */ -+ -+ int sc_irq; -+ -+ u_int32_t sc_dmaier; -+ u_int32_t sc_drammodel; /* 1=dram, 0=sram */ -+ u_int32_t sc_pllconfig; /* 7954/7955/7956 PLL config */ -+ -+ struct hifn_dma *sc_dma; -+ dma_addr_t sc_dma_physaddr;/* physical address of sc_dma */ -+ -+ int sc_dmansegs; -+ int32_t sc_cid; -+ int sc_maxses; -+ int sc_nsessions; -+ struct hifn_session *sc_sessions; -+ int sc_ramsize; -+ int sc_flags; -+#define HIFN_HAS_RNG 0x1 /* includes random number generator */ -+#define HIFN_HAS_PUBLIC 0x2 /* includes public key support */ -+#define HIFN_HAS_AES 0x4 /* includes AES support */ -+#define HIFN_IS_7811 0x8 /* Hifn 7811 part */ -+#define HIFN_IS_7956 0x10 /* Hifn 7956/7955 don't have SDRAM */ -+ -+ struct timer_list sc_tickto; /* for managing DMA */ -+ -+ int sc_rngfirst; -+ int sc_rnghz; /* RNG polling frequency */ -+ -+ int sc_c_busy; /* command ring busy */ -+ int sc_s_busy; /* source data ring busy */ -+ int sc_d_busy; /* destination data ring busy */ -+ int sc_r_busy; /* result ring busy */ -+ int sc_active; /* for initial countdown */ -+ int sc_needwakeup; /* ops q'd wating on resources */ -+ int sc_curbatch; /* # ops submitted w/o int */ -+ int sc_suspended; -+#ifdef HIFN_VULCANDEV -+ struct cdev *sc_pkdev; -+#endif -+}; -+ -+#define HIFN_LOCK(_sc) spin_lock_irqsave(&(_sc)->sc_mtx, l_flags) -+#define HIFN_UNLOCK(_sc) spin_unlock_irqrestore(&(_sc)->sc_mtx, l_flags) -+ -+/* -+ * hifn_command_t -+ * -+ * This is the control structure used to pass commands to hifn_encrypt(). -+ * -+ * flags -+ * ----- -+ * Flags is the bitwise "or" values for command configuration. A single -+ * encrypt direction needs to be set: -+ * -+ * HIFN_ENCODE or HIFN_DECODE -+ * -+ * To use cryptography, a single crypto algorithm must be included: -+ * -+ * HIFN_CRYPT_3DES or HIFN_CRYPT_DES -+ * -+ * To use authentication is used, a single MAC algorithm must be included: -+ * -+ * HIFN_MAC_MD5 or HIFN_MAC_SHA1 -+ * -+ * By default MD5 uses a 16 byte hash and SHA-1 uses a 20 byte hash. -+ * If the value below is set, hash values are truncated or assumed -+ * truncated to 12 bytes: -+ * -+ * HIFN_MAC_TRUNC -+ * -+ * Keys for encryption and authentication can be sent as part of a command, -+ * or the last key value used with a particular session can be retrieved -+ * and used again if either of these flags are not specified. -+ * -+ * HIFN_CRYPT_NEW_KEY, HIFN_MAC_NEW_KEY -+ * -+ * session_num -+ * ----------- -+ * A number between 0 and 2048 (for DRAM models) or a number between -+ * 0 and 768 (for SRAM models). Those who don't want to use session -+ * numbers should leave value at zero and send a new crypt key and/or -+ * new MAC key on every command. If you use session numbers and -+ * don't send a key with a command, the last key sent for that same -+ * session number will be used. -+ * -+ * Warning: Using session numbers and multiboard at the same time -+ * is currently broken. -+ * -+ * mbuf -+ * ---- -+ * Either fill in the mbuf pointer and npa=0 or -+ * fill packp[] and packl[] and set npa to > 0 -+ * -+ * mac_header_skip -+ * --------------- -+ * The number of bytes of the source_buf that are skipped over before -+ * authentication begins. This must be a number between 0 and 2^16-1 -+ * and can be used by IPsec implementers to skip over IP headers. -+ * *** Value ignored if authentication not used *** -+ * -+ * crypt_header_skip -+ * ----------------- -+ * The number of bytes of the source_buf that are skipped over before -+ * the cryptographic operation begins. This must be a number between 0 -+ * and 2^16-1. For IPsec, this number will always be 8 bytes larger -+ * than the auth_header_skip (to skip over the ESP header). -+ * *** Value ignored if cryptography not used *** -+ * -+ */ -+struct hifn_operand { -+ union { -+ struct sk_buff *skb; -+ struct uio *io; -+ unsigned char *buf; -+ } u; -+ void *map; -+ bus_size_t mapsize; -+ int nsegs; -+ struct { -+ dma_addr_t ds_addr; -+ int ds_len; -+ } segs[MAX_SCATTER]; -+}; -+ -+struct hifn_command { -+ u_int16_t session_num; -+ u_int16_t base_masks, cry_masks, mac_masks; -+ u_int8_t iv[HIFN_MAX_IV_LENGTH], *ck, mac[HIFN_MAC_KEY_LENGTH]; -+ int cklen; -+ int sloplen, slopidx; -+ -+ struct hifn_operand src; -+ struct hifn_operand dst; -+ -+ struct hifn_softc *softc; -+ struct cryptop *crp; -+ struct cryptodesc *enccrd, *maccrd; -+}; -+ -+#define src_skb src.u.skb -+#define src_io src.u.io -+#define src_map src.map -+#define src_mapsize src.mapsize -+#define src_segs src.segs -+#define src_nsegs src.nsegs -+#define src_buf src.u.buf -+ -+#define dst_skb dst.u.skb -+#define dst_io dst.u.io -+#define dst_map dst.map -+#define dst_mapsize dst.mapsize -+#define dst_segs dst.segs -+#define dst_nsegs dst.nsegs -+#define dst_buf dst.u.buf -+ -+/* -+ * Return values for hifn_crypto() -+ */ -+#define HIFN_CRYPTO_SUCCESS 0 -+#define HIFN_CRYPTO_BAD_INPUT (-1) -+#define HIFN_CRYPTO_RINGS_FULL (-2) -+ -+/************************************************************************** -+ * -+ * Function: hifn_crypto -+ * -+ * Purpose: Called by external drivers to begin an encryption on the -+ * HIFN board. -+ * -+ * Blocking/Non-blocking Issues -+ * ============================ -+ * The driver cannot block in hifn_crypto (no calls to tsleep) currently. -+ * hifn_crypto() returns HIFN_CRYPTO_RINGS_FULL if there is not enough -+ * room in any of the rings for the request to proceed. -+ * -+ * Return Values -+ * ============= -+ * 0 for success, negative values on error -+ * -+ * Defines for negative error codes are: -+ * -+ * HIFN_CRYPTO_BAD_INPUT : The passed in command had invalid settings. -+ * HIFN_CRYPTO_RINGS_FULL : All DMA rings were full and non-blocking -+ * behaviour was requested. -+ * -+ *************************************************************************/ -+ -+/* -+ * Convert back and forth from 'sid' to 'card' and 'session' -+ */ -+#define HIFN_CARD(sid) (((sid) & 0xf0000000) >> 28) -+#define HIFN_SESSION(sid) ((sid) & 0x000007ff) -+#define HIFN_SID(crd,ses) (((crd) << 28) | ((ses) & 0x7ff)) -+ -+#endif /* _KERNEL */ -+ -+struct hifn_stats { -+ u_int64_t hst_ibytes; -+ u_int64_t hst_obytes; -+ u_int32_t hst_ipackets; -+ u_int32_t hst_opackets; -+ u_int32_t hst_invalid; -+ u_int32_t hst_nomem; /* malloc or one of hst_nomem_* */ -+ u_int32_t hst_abort; -+ u_int32_t hst_noirq; /* IRQ for no reason */ -+ u_int32_t hst_totbatch; /* ops submitted w/o interrupt */ -+ u_int32_t hst_maxbatch; /* max ops submitted together */ -+ u_int32_t hst_unaligned; /* unaligned src caused copy */ -+ /* -+ * The following divides hst_nomem into more specific buckets. -+ */ -+ u_int32_t hst_nomem_map; /* bus_dmamap_create failed */ -+ u_int32_t hst_nomem_load; /* bus_dmamap_load_* failed */ -+ u_int32_t hst_nomem_mbuf; /* MGET* failed */ -+ u_int32_t hst_nomem_mcl; /* MCLGET* failed */ -+ u_int32_t hst_nomem_cr; /* out of command/result descriptor */ -+ u_int32_t hst_nomem_sd; /* out of src/dst descriptors */ -+}; -+ -+#endif /* __HIFN7751VAR_H__ */ -diff -Nur linux-2.6.36.orig/crypto/ocf/hifn/hifnHIPP.c linux-2.6.36/crypto/ocf/hifn/hifnHIPP.c ---- linux-2.6.36.orig/crypto/ocf/hifn/hifnHIPP.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/hifn/hifnHIPP.c 2010-11-09 20:28:04.881244876 +0100 -@@ -0,0 +1,420 @@ -+/*- -+ * Driver for Hifn HIPP-I/II chipset -+ * Copyright (c) 2006 Michael Richardson -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored by Hifn Inc. -+ * -+ */ -+ -+/* -+ * Driver for various Hifn encryption processors. -+ */ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "hifnHIPPreg.h" -+#include "hifnHIPPvar.h" -+ -+#if 1 -+#define DPRINTF(a...) if (hipp_debug) { \ -+ printk("%s: ", sc ? \ -+ device_get_nameunit(sc->sc_dev) : "hifn"); \ -+ printk(a); \ -+ } else -+#else -+#define DPRINTF(a...) -+#endif -+ -+typedef int bus_size_t; -+ -+static inline int -+pci_get_revid(struct pci_dev *dev) -+{ -+ u8 rid = 0; -+ pci_read_config_byte(dev, PCI_REVISION_ID, &rid); -+ return rid; -+} -+ -+#define debug hipp_debug -+int hipp_debug = 0; -+module_param(hipp_debug, int, 0644); -+MODULE_PARM_DESC(hipp_debug, "Enable debug"); -+ -+int hipp_maxbatch = 1; -+module_param(hipp_maxbatch, int, 0644); -+MODULE_PARM_DESC(hipp_maxbatch, "max ops to batch w/o interrupt"); -+ -+static int hipp_probe(struct pci_dev *dev, const struct pci_device_id *ent); -+static void hipp_remove(struct pci_dev *dev); -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) -+static irqreturn_t hipp_intr(int irq, void *arg); -+#else -+static irqreturn_t hipp_intr(int irq, void *arg, struct pt_regs *regs); -+#endif -+ -+static int hipp_num_chips = 0; -+static struct hipp_softc *hipp_chip_idx[HIPP_MAX_CHIPS]; -+ -+static int hipp_newsession(device_t, u_int32_t *, struct cryptoini *); -+static int hipp_freesession(device_t, u_int64_t); -+static int hipp_process(device_t, struct cryptop *, int); -+ -+static device_method_t hipp_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, hipp_newsession), -+ DEVMETHOD(cryptodev_freesession,hipp_freesession), -+ DEVMETHOD(cryptodev_process, hipp_process), -+}; -+ -+static __inline u_int32_t -+READ_REG(struct hipp_softc *sc, unsigned int barno, bus_size_t reg) -+{ -+ u_int32_t v = readl(sc->sc_bar[barno] + reg); -+ //sc->sc_bar0_lastreg = (bus_size_t) -1; -+ return (v); -+} -+static __inline void -+WRITE_REG(struct hipp_softc *sc, unsigned int barno, bus_size_t reg, u_int32_t val) -+{ -+ writel(val, sc->sc_bar[barno] + reg); -+} -+ -+#define READ_REG_0(sc, reg) READ_REG(sc, 0, reg) -+#define WRITE_REG_0(sc, reg, val) WRITE_REG(sc,0, reg, val) -+#define READ_REG_1(sc, reg) READ_REG(sc, 1, reg) -+#define WRITE_REG_1(sc, reg, val) WRITE_REG(sc,1, reg, val) -+ -+static int -+hipp_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) -+{ -+ return EINVAL; -+} -+ -+static int -+hipp_freesession(device_t dev, u_int64_t tid) -+{ -+ return EINVAL; -+} -+ -+static int -+hipp_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ return EINVAL; -+} -+ -+static const char* -+hipp_partname(struct hipp_softc *sc, char buf[128], size_t blen) -+{ -+ char *n = NULL; -+ -+ switch (pci_get_vendor(sc->sc_pcidev)) { -+ case PCI_VENDOR_HIFN: -+ switch (pci_get_device(sc->sc_pcidev)) { -+ case PCI_PRODUCT_HIFN_7855: n = "Hifn 7855"; -+ case PCI_PRODUCT_HIFN_8155: n = "Hifn 8155"; -+ case PCI_PRODUCT_HIFN_6500: n = "Hifn 6500"; -+ } -+ } -+ -+ if(n==NULL) { -+ snprintf(buf, blen, "VID=%02x,PID=%02x", -+ pci_get_vendor(sc->sc_pcidev), -+ pci_get_device(sc->sc_pcidev)); -+ } else { -+ buf[0]='\0'; -+ strncat(buf, n, blen); -+ } -+ return buf; -+} -+ -+struct hipp_fs_entry { -+ struct attribute attr; -+ /* other stuff */ -+}; -+ -+ -+static ssize_t -+cryptoid_show(struct device *dev, -+ struct device_attribute *attr, -+ char *buf) -+{ -+ struct hipp_softc *sc; -+ -+ sc = pci_get_drvdata(to_pci_dev (dev)); -+ return sprintf (buf, "%d\n", sc->sc_cid); -+} -+ -+struct device_attribute hipp_dev_cryptoid = __ATTR_RO(cryptoid); -+ -+/* -+ * Attach an interface that successfully probed. -+ */ -+static int -+hipp_probe(struct pci_dev *dev, const struct pci_device_id *ent) -+{ -+ struct hipp_softc *sc = NULL; -+ int i; -+ //char rbase; -+ //u_int16_t ena; -+ int rev; -+ //int rseg; -+ int rc; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (pci_enable_device(dev) < 0) -+ return(-ENODEV); -+ -+ if (pci_set_mwi(dev)) -+ return(-ENODEV); -+ -+ if (!dev->irq) { -+ printk("hifn: found device with no IRQ assigned. check BIOS settings!"); -+ pci_disable_device(dev); -+ return(-ENODEV); -+ } -+ -+ sc = (struct hipp_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); -+ if (!sc) -+ return(-ENOMEM); -+ memset(sc, 0, sizeof(*sc)); -+ -+ softc_device_init(sc, "hifn-hipp", hipp_num_chips, hipp_methods); -+ -+ sc->sc_pcidev = dev; -+ sc->sc_irq = -1; -+ sc->sc_cid = -1; -+ sc->sc_num = hipp_num_chips++; -+ -+ if (sc->sc_num < HIPP_MAX_CHIPS) -+ hipp_chip_idx[sc->sc_num] = sc; -+ -+ pci_set_drvdata(sc->sc_pcidev, sc); -+ -+ spin_lock_init(&sc->sc_mtx); -+ -+ /* -+ * Setup PCI resources. -+ * The READ_REG_0, WRITE_REG_0, READ_REG_1, -+ * and WRITE_REG_1 macros throughout the driver are used -+ * to permit better debugging. -+ */ -+ for(i=0; i<4; i++) { -+ unsigned long mem_start, mem_len; -+ mem_start = pci_resource_start(sc->sc_pcidev, i); -+ mem_len = pci_resource_len(sc->sc_pcidev, i); -+ sc->sc_barphy[i] = (caddr_t)mem_start; -+ sc->sc_bar[i] = (ocf_iomem_t) ioremap(mem_start, mem_len); -+ if (!sc->sc_bar[i]) { -+ device_printf(sc->sc_dev, "cannot map bar%d register space\n", i); -+ goto fail; -+ } -+ } -+ -+ //hipp_reset_board(sc, 0); -+ pci_set_master(sc->sc_pcidev); -+ -+ /* -+ * Arrange the interrupt line. -+ */ -+ rc = request_irq(dev->irq, hipp_intr, IRQF_SHARED, "hifn", sc); -+ if (rc) { -+ device_printf(sc->sc_dev, "could not map interrupt: %d\n", rc); -+ goto fail; -+ } -+ sc->sc_irq = dev->irq; -+ -+ rev = READ_REG_1(sc, HIPP_1_REVID) & 0xffff; -+ -+ { -+ char b[32]; -+ device_printf(sc->sc_dev, "%s, rev %u", -+ hipp_partname(sc, b, sizeof(b)), rev); -+ } -+ -+#if 0 -+ if (sc->sc_flags & HIFN_IS_7956) -+ printf(", pll=0x%x<%s clk, %ux mult>", -+ sc->sc_pllconfig, -+ sc->sc_pllconfig & HIFN_PLL_REF_SEL ? "ext" : "pci", -+ 2 + 2*((sc->sc_pllconfig & HIFN_PLL_ND) >> 11)); -+#endif -+ printf("\n"); -+ -+ sc->sc_cid = crypto_get_driverid(softc_get_device(sc),CRYPTOCAP_F_HARDWARE); -+ if (sc->sc_cid < 0) { -+ device_printf(sc->sc_dev, "could not get crypto driver id\n"); -+ goto fail; -+ } -+ -+#if 0 /* cannot work with a non-GPL module */ -+ /* make a sysfs entry to let the world know what entry we got */ -+ sysfs_create_file(&sc->sc_pcidev->dev.kobj, &hipp_dev_cryptoid.attr); -+#endif -+ -+#if 0 -+ init_timer(&sc->sc_tickto); -+ sc->sc_tickto.function = hifn_tick; -+ sc->sc_tickto.data = (unsigned long) sc->sc_num; -+ mod_timer(&sc->sc_tickto, jiffies + HZ); -+#endif -+ -+#if 0 /* no code here yet ?? */ -+ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); -+#endif -+ -+ return (0); -+ -+fail: -+ if (sc->sc_cid >= 0) -+ crypto_unregister_all(sc->sc_cid); -+ if (sc->sc_irq != -1) -+ free_irq(sc->sc_irq, sc); -+ -+#if 0 -+ if (sc->sc_dma) { -+ /* Turn off DMA polling */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | -+ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); -+ -+ pci_free_consistent(sc->sc_pcidev, -+ sizeof(*sc->sc_dma), -+ sc->sc_dma, sc->sc_dma_physaddr); -+ } -+#endif -+ kfree(sc); -+ return (-ENXIO); -+} -+ -+/* -+ * Detach an interface that successfully probed. -+ */ -+static void -+hipp_remove(struct pci_dev *dev) -+{ -+ struct hipp_softc *sc = pci_get_drvdata(dev); -+ unsigned long l_flags; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ /* disable interrupts */ -+ HIPP_LOCK(sc); -+ -+#if 0 -+ WRITE_REG_1(sc, HIFN_1_DMA_IER, 0); -+ HIFN_UNLOCK(sc); -+ -+ /*XXX other resources */ -+ del_timer_sync(&sc->sc_tickto); -+ -+ /* Turn off DMA polling */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | -+ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); -+#endif -+ -+ crypto_unregister_all(sc->sc_cid); -+ -+ free_irq(sc->sc_irq, sc); -+ -+#if 0 -+ pci_free_consistent(sc->sc_pcidev, sizeof(*sc->sc_dma), -+ sc->sc_dma, sc->sc_dma_physaddr); -+#endif -+} -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) -+static irqreturn_t hipp_intr(int irq, void *arg) -+#else -+static irqreturn_t hipp_intr(int irq, void *arg, struct pt_regs *regs) -+#endif -+{ -+ struct hipp_softc *sc = arg; -+ -+ sc = sc; /* shut up compiler */ -+ -+ return IRQ_HANDLED; -+} -+ -+static struct pci_device_id hipp_pci_tbl[] = { -+ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7855, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_8155, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+}; -+MODULE_DEVICE_TABLE(pci, hipp_pci_tbl); -+ -+static struct pci_driver hipp_driver = { -+ .name = "hipp", -+ .id_table = hipp_pci_tbl, -+ .probe = hipp_probe, -+ .remove = hipp_remove, -+ /* add PM stuff here one day */ -+}; -+ -+static int __init hipp_init (void) -+{ -+ struct hipp_softc *sc = NULL; -+ int rc; -+ -+ DPRINTF("%s(%p)\n", __FUNCTION__, hipp_init); -+ -+ rc = pci_register_driver(&hipp_driver); -+ pci_register_driver_compat(&hipp_driver, rc); -+ -+ return rc; -+} -+ -+static void __exit hipp_exit (void) -+{ -+ pci_unregister_driver(&hipp_driver); -+} -+ -+module_init(hipp_init); -+module_exit(hipp_exit); -+ -+MODULE_LICENSE("BSD"); -+MODULE_AUTHOR("Michael Richardson "); -+MODULE_DESCRIPTION("OCF driver for hifn HIPP-I/II PCI crypto devices"); -diff -Nur linux-2.6.36.orig/crypto/ocf/hifn/hifnHIPPreg.h linux-2.6.36/crypto/ocf/hifn/hifnHIPPreg.h ---- linux-2.6.36.orig/crypto/ocf/hifn/hifnHIPPreg.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/hifn/hifnHIPPreg.h 2010-11-09 20:28:04.922495399 +0100 -@@ -0,0 +1,46 @@ -+/*- -+ * Hifn HIPP-I/HIPP-II (7855/8155) driver. -+ * Copyright (c) 2006 Michael Richardson -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored by Hifn inc. -+ * -+ */ -+ -+#ifndef __HIFNHIPP_H__ -+#define __HIFNHIPP_H__ -+ -+/* -+ * PCI vendor and device identifiers -+ */ -+#define PCI_VENDOR_HIFN 0x13a3 /* Hifn */ -+#define PCI_PRODUCT_HIFN_6500 0x0006 /* 6500 */ -+#define PCI_PRODUCT_HIFN_7855 0x001f /* 7855 */ -+#define PCI_PRODUCT_HIFN_8155 0x999 /* XXX 8155 */ -+ -+#define HIPP_1_REVID 0x01 /* BOGUS */ -+ -+#endif /* __HIPP_H__ */ -diff -Nur linux-2.6.36.orig/crypto/ocf/hifn/hifnHIPPvar.h linux-2.6.36/crypto/ocf/hifn/hifnHIPPvar.h ---- linux-2.6.36.orig/crypto/ocf/hifn/hifnHIPPvar.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/hifn/hifnHIPPvar.h 2010-11-09 20:28:04.964807923 +0100 -@@ -0,0 +1,93 @@ -+/* -+ * Hifn HIPP-I/HIPP-II (7855/8155) driver. -+ * Copyright (c) 2006 Michael Richardson * -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored by Hifn inc. -+ * -+ */ -+ -+#ifndef __HIFNHIPPVAR_H__ -+#define __HIFNHIPPVAR_H__ -+ -+#define HIPP_MAX_CHIPS 8 -+ -+/* -+ * Holds data specific to a single Hifn HIPP-I board. -+ */ -+struct hipp_softc { -+ softc_device_decl sc_dev; -+ -+ struct pci_dev *sc_pcidev; /* device backpointer */ -+ ocf_iomem_t sc_bar[5]; -+ caddr_t sc_barphy[5]; /* physical address */ -+ int sc_num; /* for multiple devs */ -+ spinlock_t sc_mtx; /* per-instance lock */ -+ int32_t sc_cid; -+ int sc_irq; -+ -+#if 0 -+ -+ u_int32_t sc_dmaier; -+ u_int32_t sc_drammodel; /* 1=dram, 0=sram */ -+ u_int32_t sc_pllconfig; /* 7954/7955/7956 PLL config */ -+ -+ struct hifn_dma *sc_dma; -+ dma_addr_t sc_dma_physaddr;/* physical address of sc_dma */ -+ -+ int sc_dmansegs; -+ int sc_maxses; -+ int sc_nsessions; -+ struct hifn_session *sc_sessions; -+ int sc_ramsize; -+ int sc_flags; -+#define HIFN_HAS_RNG 0x1 /* includes random number generator */ -+#define HIFN_HAS_PUBLIC 0x2 /* includes public key support */ -+#define HIFN_HAS_AES 0x4 /* includes AES support */ -+#define HIFN_IS_7811 0x8 /* Hifn 7811 part */ -+#define HIFN_IS_7956 0x10 /* Hifn 7956/7955 don't have SDRAM */ -+ -+ struct timer_list sc_tickto; /* for managing DMA */ -+ -+ int sc_rngfirst; -+ int sc_rnghz; /* RNG polling frequency */ -+ -+ int sc_c_busy; /* command ring busy */ -+ int sc_s_busy; /* source data ring busy */ -+ int sc_d_busy; /* destination data ring busy */ -+ int sc_r_busy; /* result ring busy */ -+ int sc_active; /* for initial countdown */ -+ int sc_needwakeup; /* ops q'd wating on resources */ -+ int sc_curbatch; /* # ops submitted w/o int */ -+ int sc_suspended; -+ struct miscdevice sc_miscdev; -+#endif -+}; -+ -+#define HIPP_LOCK(_sc) spin_lock_irqsave(&(_sc)->sc_mtx, l_flags) -+#define HIPP_UNLOCK(_sc) spin_unlock_irqrestore(&(_sc)->sc_mtx, l_flags) -+ -+#endif /* __HIFNHIPPVAR_H__ */ -diff -Nur linux-2.6.36.orig/crypto/ocf/hifn/Makefile linux-2.6.36/crypto/ocf/hifn/Makefile ---- linux-2.6.36.orig/crypto/ocf/hifn/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/hifn/Makefile 2010-11-09 20:28:05.002825564 +0100 -@@ -0,0 +1,13 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+obj-$(CONFIG_OCF_HIFN) += hifn7751.o -+obj-$(CONFIG_OCF_HIFNHIPP) += hifnHIPP.o -+ -+obj ?= . -+EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/ixp4xx/ixp4xx.c linux-2.6.36/crypto/ocf/ixp4xx/ixp4xx.c ---- linux-2.6.36.orig/crypto/ocf/ixp4xx/ixp4xx.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/ixp4xx/ixp4xx.c 2010-11-09 20:28:05.051258556 +0100 -@@ -0,0 +1,1324 @@ -+/* -+ * An OCF module that uses Intels IXP CryptACC API to do the crypto. -+ * This driver requires the IXP400 Access Library that is available -+ * from Intel in order to operate (or compile). -+ * -+ * Written by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * ALTERNATIVELY, provided that this notice is retained in full, this product -+ * may be distributed under the terms of the GNU General Public License (GPL), -+ * in which case the provisions of the GPL apply INSTEAD OF those given above. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ */ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#ifndef IX_MBUF_PRIV -+#define IX_MBUF_PRIV(x) ((x)->priv) -+#endif -+ -+struct ixp_data; -+ -+struct ixp_q { -+ struct list_head ixp_q_list; -+ struct ixp_data *ixp_q_data; -+ struct cryptop *ixp_q_crp; -+ struct cryptodesc *ixp_q_ccrd; -+ struct cryptodesc *ixp_q_acrd; -+ IX_MBUF ixp_q_mbuf; -+ UINT8 *ixp_hash_dest; /* Location for hash in client buffer */ -+ UINT8 *ixp_hash_src; /* Location of hash in internal buffer */ -+ unsigned char ixp_q_iv_data[IX_CRYPTO_ACC_MAX_CIPHER_IV_LENGTH]; -+ unsigned char *ixp_q_iv; -+}; -+ -+struct ixp_data { -+ int ixp_registered; /* is the context registered */ -+ int ixp_crd_flags; /* detect direction changes */ -+ -+ int ixp_cipher_alg; -+ int ixp_auth_alg; -+ -+ UINT32 ixp_ctx_id; -+ UINT32 ixp_hash_key_id; /* used when hashing */ -+ IxCryptoAccCtx ixp_ctx; -+ IX_MBUF ixp_pri_mbuf; -+ IX_MBUF ixp_sec_mbuf; -+ -+ struct work_struct ixp_pending_work; -+ struct work_struct ixp_registration_work; -+ struct list_head ixp_q; /* unprocessed requests */ -+}; -+ -+#ifdef __ixp46X -+ -+#define MAX_IOP_SIZE 64 /* words */ -+#define MAX_OOP_SIZE 128 -+ -+#define MAX_PARAMS 3 -+ -+struct ixp_pkq { -+ struct list_head pkq_list; -+ struct cryptkop *pkq_krp; -+ -+ IxCryptoAccPkeEauInOperands pkq_op; -+ IxCryptoAccPkeEauOpResult pkq_result; -+ -+ UINT32 pkq_ibuf0[MAX_IOP_SIZE]; -+ UINT32 pkq_ibuf1[MAX_IOP_SIZE]; -+ UINT32 pkq_ibuf2[MAX_IOP_SIZE]; -+ UINT32 pkq_obuf[MAX_OOP_SIZE]; -+}; -+ -+static LIST_HEAD(ixp_pkq); /* current PK wait list */ -+static struct ixp_pkq *ixp_pk_cur; -+static spinlock_t ixp_pkq_lock; -+ -+#endif /* __ixp46X */ -+ -+static int ixp_blocked = 0; -+ -+static int32_t ixp_id = -1; -+static struct ixp_data **ixp_sessions = NULL; -+static u_int32_t ixp_sesnum = 0; -+ -+static int ixp_process(device_t, struct cryptop *, int); -+static int ixp_newsession(device_t, u_int32_t *, struct cryptoini *); -+static int ixp_freesession(device_t, u_int64_t); -+#ifdef __ixp46X -+static int ixp_kprocess(device_t, struct cryptkop *krp, int hint); -+#endif -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) -+static kmem_cache_t *qcache; -+#else -+static struct kmem_cache *qcache; -+#endif -+ -+#define debug ixp_debug -+static int ixp_debug = 0; -+module_param(ixp_debug, int, 0644); -+MODULE_PARM_DESC(ixp_debug, "Enable debug"); -+ -+static int ixp_init_crypto = 1; -+module_param(ixp_init_crypto, int, 0444); /* RO after load/boot */ -+MODULE_PARM_DESC(ixp_init_crypto, "Call ixCryptoAccInit (default is 1)"); -+ -+static void ixp_process_pending(void *arg); -+static void ixp_registration(void *arg); -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void ixp_process_pending_wq(struct work_struct *work); -+static void ixp_registration_wq(struct work_struct *work); -+#endif -+ -+/* -+ * dummy device structure -+ */ -+ -+static struct { -+ softc_device_decl sc_dev; -+} ixpdev; -+ -+static device_method_t ixp_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, ixp_newsession), -+ DEVMETHOD(cryptodev_freesession,ixp_freesession), -+ DEVMETHOD(cryptodev_process, ixp_process), -+#ifdef __ixp46X -+ DEVMETHOD(cryptodev_kprocess, ixp_kprocess), -+#endif -+}; -+ -+/* -+ * Generate a new software session. -+ */ -+static int -+ixp_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) -+{ -+ struct ixp_data *ixp; -+ u_int32_t i; -+#define AUTH_LEN(cri, def) \ -+ (cri->cri_mlen ? cri->cri_mlen : (def)) -+ -+ dprintk("%s():alg %d\n", __FUNCTION__,cri->cri_alg); -+ if (sid == NULL || cri == NULL) { -+ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ if (ixp_sessions) { -+ for (i = 1; i < ixp_sesnum; i++) -+ if (ixp_sessions[i] == NULL) -+ break; -+ } else -+ i = 1; /* NB: to silence compiler warning */ -+ -+ if (ixp_sessions == NULL || i == ixp_sesnum) { -+ struct ixp_data **ixpd; -+ -+ if (ixp_sessions == NULL) { -+ i = 1; /* We leave ixp_sessions[0] empty */ -+ ixp_sesnum = CRYPTO_SW_SESSIONS; -+ } else -+ ixp_sesnum *= 2; -+ -+ ixpd = kmalloc(ixp_sesnum * sizeof(struct ixp_data *), SLAB_ATOMIC); -+ if (ixpd == NULL) { -+ /* Reset session number */ -+ if (ixp_sesnum == CRYPTO_SW_SESSIONS) -+ ixp_sesnum = 0; -+ else -+ ixp_sesnum /= 2; -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memset(ixpd, 0, ixp_sesnum * sizeof(struct ixp_data *)); -+ -+ /* Copy existing sessions */ -+ if (ixp_sessions) { -+ memcpy(ixpd, ixp_sessions, -+ (ixp_sesnum / 2) * sizeof(struct ixp_data *)); -+ kfree(ixp_sessions); -+ } -+ -+ ixp_sessions = ixpd; -+ } -+ -+ ixp_sessions[i] = (struct ixp_data *) kmalloc(sizeof(struct ixp_data), -+ SLAB_ATOMIC); -+ if (ixp_sessions[i] == NULL) { -+ ixp_freesession(NULL, i); -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ -+ *sid = i; -+ -+ ixp = ixp_sessions[i]; -+ memset(ixp, 0, sizeof(*ixp)); -+ -+ ixp->ixp_cipher_alg = -1; -+ ixp->ixp_auth_alg = -1; -+ ixp->ixp_ctx_id = -1; -+ INIT_LIST_HEAD(&ixp->ixp_q); -+ -+ ixp->ixp_ctx.useDifferentSrcAndDestMbufs = 0; -+ -+ while (cri) { -+ switch (cri->cri_alg) { -+ case CRYPTO_DES_CBC: -+ ixp->ixp_cipher_alg = cri->cri_alg; -+ ixp->ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_DES; -+ ixp->ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; -+ ixp->ixp_ctx.cipherCtx.cipherKeyLen = (cri->cri_klen + 7) / 8; -+ ixp->ixp_ctx.cipherCtx.cipherBlockLen = IX_CRYPTO_ACC_DES_BLOCK_64; -+ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen = -+ IX_CRYPTO_ACC_DES_IV_64; -+ memcpy(ixp->ixp_ctx.cipherCtx.key.cipherKey, -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ break; -+ -+ case CRYPTO_3DES_CBC: -+ ixp->ixp_cipher_alg = cri->cri_alg; -+ ixp->ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_3DES; -+ ixp->ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; -+ ixp->ixp_ctx.cipherCtx.cipherKeyLen = (cri->cri_klen + 7) / 8; -+ ixp->ixp_ctx.cipherCtx.cipherBlockLen = IX_CRYPTO_ACC_DES_BLOCK_64; -+ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen = -+ IX_CRYPTO_ACC_DES_IV_64; -+ memcpy(ixp->ixp_ctx.cipherCtx.key.cipherKey, -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ break; -+ -+ case CRYPTO_RIJNDAEL128_CBC: -+ ixp->ixp_cipher_alg = cri->cri_alg; -+ ixp->ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_AES; -+ ixp->ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; -+ ixp->ixp_ctx.cipherCtx.cipherKeyLen = (cri->cri_klen + 7) / 8; -+ ixp->ixp_ctx.cipherCtx.cipherBlockLen = 16; -+ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen = 16; -+ memcpy(ixp->ixp_ctx.cipherCtx.key.cipherKey, -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ break; -+ -+ case CRYPTO_MD5: -+ case CRYPTO_MD5_HMAC: -+ ixp->ixp_auth_alg = cri->cri_alg; -+ ixp->ixp_ctx.authCtx.authAlgo = IX_CRYPTO_ACC_AUTH_MD5; -+ ixp->ixp_ctx.authCtx.authDigestLen = AUTH_LEN(cri, MD5_HASH_LEN); -+ ixp->ixp_ctx.authCtx.aadLen = 0; -+ /* Only MD5_HMAC needs a key */ -+ if (cri->cri_alg == CRYPTO_MD5_HMAC) { -+ ixp->ixp_ctx.authCtx.authKeyLen = (cri->cri_klen + 7) / 8; -+ if (ixp->ixp_ctx.authCtx.authKeyLen > -+ sizeof(ixp->ixp_ctx.authCtx.key.authKey)) { -+ printk( -+ "ixp4xx: Invalid key length for MD5_HMAC - %d bits\n", -+ cri->cri_klen); -+ ixp_freesession(NULL, i); -+ return EINVAL; -+ } -+ memcpy(ixp->ixp_ctx.authCtx.key.authKey, -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ } -+ break; -+ -+ case CRYPTO_SHA1: -+ case CRYPTO_SHA1_HMAC: -+ ixp->ixp_auth_alg = cri->cri_alg; -+ ixp->ixp_ctx.authCtx.authAlgo = IX_CRYPTO_ACC_AUTH_SHA1; -+ ixp->ixp_ctx.authCtx.authDigestLen = AUTH_LEN(cri, SHA1_HASH_LEN); -+ ixp->ixp_ctx.authCtx.aadLen = 0; -+ /* Only SHA1_HMAC needs a key */ -+ if (cri->cri_alg == CRYPTO_SHA1_HMAC) { -+ ixp->ixp_ctx.authCtx.authKeyLen = (cri->cri_klen + 7) / 8; -+ if (ixp->ixp_ctx.authCtx.authKeyLen > -+ sizeof(ixp->ixp_ctx.authCtx.key.authKey)) { -+ printk( -+ "ixp4xx: Invalid key length for SHA1_HMAC - %d bits\n", -+ cri->cri_klen); -+ ixp_freesession(NULL, i); -+ return EINVAL; -+ } -+ memcpy(ixp->ixp_ctx.authCtx.key.authKey, -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ } -+ break; -+ -+ default: -+ printk("ixp: unknown algo 0x%x\n", cri->cri_alg); -+ ixp_freesession(NULL, i); -+ return EINVAL; -+ } -+ cri = cri->cri_next; -+ } -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ INIT_WORK(&ixp->ixp_pending_work, ixp_process_pending_wq); -+ INIT_WORK(&ixp->ixp_registration_work, ixp_registration_wq); -+#else -+ INIT_WORK(&ixp->ixp_pending_work, ixp_process_pending, ixp); -+ INIT_WORK(&ixp->ixp_registration_work, ixp_registration, ixp); -+#endif -+ -+ return 0; -+} -+ -+ -+/* -+ * Free a session. -+ */ -+static int -+ixp_freesession(device_t dev, u_int64_t tid) -+{ -+ u_int32_t sid = CRYPTO_SESID2LID(tid); -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid > ixp_sesnum || ixp_sessions == NULL || -+ ixp_sessions[sid] == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ /* Silently accept and return */ -+ if (sid == 0) -+ return 0; -+ -+ if (ixp_sessions[sid]) { -+ if (ixp_sessions[sid]->ixp_ctx_id != -1) { -+ ixCryptoAccCtxUnregister(ixp_sessions[sid]->ixp_ctx_id); -+ ixp_sessions[sid]->ixp_ctx_id = -1; -+ } -+ kfree(ixp_sessions[sid]); -+ } -+ ixp_sessions[sid] = NULL; -+ if (ixp_blocked) { -+ ixp_blocked = 0; -+ crypto_unblock(ixp_id, CRYPTO_SYMQ); -+ } -+ return 0; -+} -+ -+ -+/* -+ * callback for when hash processing is complete -+ */ -+ -+static void -+ixp_hash_perform_cb( -+ UINT32 hash_key_id, -+ IX_MBUF *bufp, -+ IxCryptoAccStatus status) -+{ -+ struct ixp_q *q; -+ -+ dprintk("%s(%u, %p, 0x%x)\n", __FUNCTION__, hash_key_id, bufp, status); -+ -+ if (bufp == NULL) { -+ printk("ixp: NULL buf in %s\n", __FUNCTION__); -+ return; -+ } -+ -+ q = IX_MBUF_PRIV(bufp); -+ if (q == NULL) { -+ printk("ixp: NULL priv in %s\n", __FUNCTION__); -+ return; -+ } -+ -+ if (status == IX_CRYPTO_ACC_STATUS_SUCCESS) { -+ /* On success, need to copy hash back into original client buffer */ -+ memcpy(q->ixp_hash_dest, q->ixp_hash_src, -+ (q->ixp_q_data->ixp_auth_alg == CRYPTO_SHA1) ? -+ SHA1_HASH_LEN : MD5_HASH_LEN); -+ } -+ else { -+ printk("ixp: hash perform failed status=%d\n", status); -+ q->ixp_q_crp->crp_etype = EINVAL; -+ } -+ -+ /* Free internal buffer used for hashing */ -+ kfree(IX_MBUF_MDATA(&q->ixp_q_mbuf)); -+ -+ crypto_done(q->ixp_q_crp); -+ kmem_cache_free(qcache, q); -+} -+ -+/* -+ * setup a request and perform it -+ */ -+static void -+ixp_q_process(struct ixp_q *q) -+{ -+ IxCryptoAccStatus status; -+ struct ixp_data *ixp = q->ixp_q_data; -+ int auth_off = 0; -+ int auth_len = 0; -+ int crypt_off = 0; -+ int crypt_len = 0; -+ int icv_off = 0; -+ char *crypt_func; -+ -+ dprintk("%s(%p)\n", __FUNCTION__, q); -+ -+ if (q->ixp_q_ccrd) { -+ if (q->ixp_q_ccrd->crd_flags & CRD_F_IV_EXPLICIT) { -+ q->ixp_q_iv = q->ixp_q_ccrd->crd_iv; -+ } else { -+ q->ixp_q_iv = q->ixp_q_iv_data; -+ crypto_copydata(q->ixp_q_crp->crp_flags, q->ixp_q_crp->crp_buf, -+ q->ixp_q_ccrd->crd_inject, -+ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen, -+ (caddr_t) q->ixp_q_iv); -+ } -+ -+ if (q->ixp_q_acrd) { -+ auth_off = q->ixp_q_acrd->crd_skip; -+ auth_len = q->ixp_q_acrd->crd_len; -+ icv_off = q->ixp_q_acrd->crd_inject; -+ } -+ -+ crypt_off = q->ixp_q_ccrd->crd_skip; -+ crypt_len = q->ixp_q_ccrd->crd_len; -+ } else { /* if (q->ixp_q_acrd) */ -+ auth_off = q->ixp_q_acrd->crd_skip; -+ auth_len = q->ixp_q_acrd->crd_len; -+ icv_off = q->ixp_q_acrd->crd_inject; -+ } -+ -+ if (q->ixp_q_crp->crp_flags & CRYPTO_F_SKBUF) { -+ struct sk_buff *skb = (struct sk_buff *) q->ixp_q_crp->crp_buf; -+ if (skb_shinfo(skb)->nr_frags) { -+ /* -+ * DAVIDM fix this limitation one day by using -+ * a buffer pool and chaining, it is not currently -+ * needed for current user/kernel space acceleration -+ */ -+ printk("ixp: Cannot handle fragmented skb's yet !\n"); -+ q->ixp_q_crp->crp_etype = ENOENT; -+ goto done; -+ } -+ IX_MBUF_MLEN(&q->ixp_q_mbuf) = -+ IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = skb->len; -+ IX_MBUF_MDATA(&q->ixp_q_mbuf) = skb->data; -+ } else if (q->ixp_q_crp->crp_flags & CRYPTO_F_IOV) { -+ struct uio *uiop = (struct uio *) q->ixp_q_crp->crp_buf; -+ if (uiop->uio_iovcnt != 1) { -+ /* -+ * DAVIDM fix this limitation one day by using -+ * a buffer pool and chaining, it is not currently -+ * needed for current user/kernel space acceleration -+ */ -+ printk("ixp: Cannot handle more than 1 iovec yet !\n"); -+ q->ixp_q_crp->crp_etype = ENOENT; -+ goto done; -+ } -+ IX_MBUF_MLEN(&q->ixp_q_mbuf) = -+ IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = uiop->uio_iov[0].iov_len; -+ IX_MBUF_MDATA(&q->ixp_q_mbuf) = uiop->uio_iov[0].iov_base; -+ } else /* contig buffer */ { -+ IX_MBUF_MLEN(&q->ixp_q_mbuf) = -+ IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = q->ixp_q_crp->crp_ilen; -+ IX_MBUF_MDATA(&q->ixp_q_mbuf) = q->ixp_q_crp->crp_buf; -+ } -+ -+ IX_MBUF_PRIV(&q->ixp_q_mbuf) = q; -+ -+ if (ixp->ixp_auth_alg == CRYPTO_SHA1 || ixp->ixp_auth_alg == CRYPTO_MD5) { -+ /* -+ * For SHA1 and MD5 hash, need to create an internal buffer that is big -+ * enough to hold the original data + the appropriate padding for the -+ * hash algorithm. -+ */ -+ UINT8 *tbuf = NULL; -+ -+ IX_MBUF_MLEN(&q->ixp_q_mbuf) = IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = -+ ((IX_MBUF_MLEN(&q->ixp_q_mbuf) * 8) + 72 + 511) / 8; -+ tbuf = kmalloc(IX_MBUF_MLEN(&q->ixp_q_mbuf), SLAB_ATOMIC); -+ -+ if (IX_MBUF_MDATA(&q->ixp_q_mbuf) == NULL) { -+ printk("ixp: kmalloc(%u, SLAB_ATOMIC) failed\n", -+ IX_MBUF_MLEN(&q->ixp_q_mbuf)); -+ q->ixp_q_crp->crp_etype = ENOMEM; -+ goto done; -+ } -+ memcpy(tbuf, &(IX_MBUF_MDATA(&q->ixp_q_mbuf))[auth_off], auth_len); -+ -+ /* Set location in client buffer to copy hash into */ -+ q->ixp_hash_dest = -+ &(IX_MBUF_MDATA(&q->ixp_q_mbuf))[auth_off + auth_len]; -+ -+ IX_MBUF_MDATA(&q->ixp_q_mbuf) = tbuf; -+ -+ /* Set location in internal buffer for where hash starts */ -+ q->ixp_hash_src = &(IX_MBUF_MDATA(&q->ixp_q_mbuf))[auth_len]; -+ -+ crypt_func = "ixCryptoAccHashPerform"; -+ status = ixCryptoAccHashPerform(ixp->ixp_ctx.authCtx.authAlgo, -+ &q->ixp_q_mbuf, ixp_hash_perform_cb, 0, auth_len, auth_len, -+ &ixp->ixp_hash_key_id); -+ } -+ else { -+ crypt_func = "ixCryptoAccAuthCryptPerform"; -+ status = ixCryptoAccAuthCryptPerform(ixp->ixp_ctx_id, &q->ixp_q_mbuf, -+ NULL, auth_off, auth_len, crypt_off, crypt_len, icv_off, -+ q->ixp_q_iv); -+ } -+ -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) -+ return; -+ -+ if (IX_CRYPTO_ACC_STATUS_QUEUE_FULL == status) { -+ q->ixp_q_crp->crp_etype = ENOMEM; -+ goto done; -+ } -+ -+ printk("ixp: %s failed %u\n", crypt_func, status); -+ q->ixp_q_crp->crp_etype = EINVAL; -+ -+done: -+ crypto_done(q->ixp_q_crp); -+ kmem_cache_free(qcache, q); -+} -+ -+ -+/* -+ * because we cannot process the Q from the Register callback -+ * we do it here on a task Q. -+ */ -+ -+static void -+ixp_process_pending(void *arg) -+{ -+ struct ixp_data *ixp = arg; -+ struct ixp_q *q = NULL; -+ -+ dprintk("%s(%p)\n", __FUNCTION__, arg); -+ -+ if (!ixp) -+ return; -+ -+ while (!list_empty(&ixp->ixp_q)) { -+ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); -+ list_del(&q->ixp_q_list); -+ ixp_q_process(q); -+ } -+} -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void -+ixp_process_pending_wq(struct work_struct *work) -+{ -+ struct ixp_data *ixp = container_of(work, struct ixp_data, ixp_pending_work); -+ ixp_process_pending(ixp); -+} -+#endif -+ -+/* -+ * callback for when context registration is complete -+ */ -+ -+static void -+ixp_register_cb(UINT32 ctx_id, IX_MBUF *bufp, IxCryptoAccStatus status) -+{ -+ int i; -+ struct ixp_data *ixp; -+ struct ixp_q *q; -+ -+ dprintk("%s(%d, %p, %d)\n", __FUNCTION__, ctx_id, bufp, status); -+ -+ /* -+ * free any buffer passed in to this routine -+ */ -+ if (bufp) { -+ IX_MBUF_MLEN(bufp) = IX_MBUF_PKT_LEN(bufp) = 0; -+ kfree(IX_MBUF_MDATA(bufp)); -+ IX_MBUF_MDATA(bufp) = NULL; -+ } -+ -+ for (i = 0; i < ixp_sesnum; i++) { -+ ixp = ixp_sessions[i]; -+ if (ixp && ixp->ixp_ctx_id == ctx_id) -+ break; -+ } -+ if (i >= ixp_sesnum) { -+ printk("ixp: invalid context id %d\n", ctx_id); -+ return; -+ } -+ -+ if (IX_CRYPTO_ACC_STATUS_WAIT == status) { -+ /* this is normal to free the first of two buffers */ -+ dprintk("ixp: register not finished yet.\n"); -+ return; -+ } -+ -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS != status) { -+ printk("ixp: register failed 0x%x\n", status); -+ while (!list_empty(&ixp->ixp_q)) { -+ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); -+ list_del(&q->ixp_q_list); -+ q->ixp_q_crp->crp_etype = EINVAL; -+ crypto_done(q->ixp_q_crp); -+ kmem_cache_free(qcache, q); -+ } -+ return; -+ } -+ -+ /* -+ * we are now registered, we cannot start processing the Q here -+ * or we get strange errors with AES (DES/3DES seem to be ok). -+ */ -+ ixp->ixp_registered = 1; -+ schedule_work(&ixp->ixp_pending_work); -+} -+ -+ -+/* -+ * callback for when data processing is complete -+ */ -+ -+static void -+ixp_perform_cb( -+ UINT32 ctx_id, -+ IX_MBUF *sbufp, -+ IX_MBUF *dbufp, -+ IxCryptoAccStatus status) -+{ -+ struct ixp_q *q; -+ -+ dprintk("%s(%d, %p, %p, 0x%x)\n", __FUNCTION__, ctx_id, sbufp, -+ dbufp, status); -+ -+ if (sbufp == NULL) { -+ printk("ixp: NULL sbuf in ixp_perform_cb\n"); -+ return; -+ } -+ -+ q = IX_MBUF_PRIV(sbufp); -+ if (q == NULL) { -+ printk("ixp: NULL priv in ixp_perform_cb\n"); -+ return; -+ } -+ -+ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { -+ printk("ixp: perform failed status=%d\n", status); -+ q->ixp_q_crp->crp_etype = EINVAL; -+ } -+ -+ crypto_done(q->ixp_q_crp); -+ kmem_cache_free(qcache, q); -+} -+ -+ -+/* -+ * registration is not callable at IRQ time, so we defer -+ * to a task queue, this routines completes the registration for us -+ * when the task queue runs -+ * -+ * Unfortunately this means we cannot tell OCF that the driver is blocked, -+ * we do that on the next request. -+ */ -+ -+static void -+ixp_registration(void *arg) -+{ -+ struct ixp_data *ixp = arg; -+ struct ixp_q *q = NULL; -+ IX_MBUF *pri = NULL, *sec = NULL; -+ int status = IX_CRYPTO_ACC_STATUS_SUCCESS; -+ -+ if (!ixp) { -+ printk("ixp: ixp_registration with no arg\n"); -+ return; -+ } -+ -+ if (ixp->ixp_ctx_id != -1) { -+ ixCryptoAccCtxUnregister(ixp->ixp_ctx_id); -+ ixp->ixp_ctx_id = -1; -+ } -+ -+ if (list_empty(&ixp->ixp_q)) { -+ printk("ixp: ixp_registration with no Q\n"); -+ return; -+ } -+ -+ /* -+ * setup the primary and secondary buffers -+ */ -+ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); -+ if (q->ixp_q_acrd) { -+ pri = &ixp->ixp_pri_mbuf; -+ sec = &ixp->ixp_sec_mbuf; -+ IX_MBUF_MLEN(pri) = IX_MBUF_PKT_LEN(pri) = 128; -+ IX_MBUF_MDATA(pri) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); -+ IX_MBUF_MLEN(sec) = IX_MBUF_PKT_LEN(sec) = 128; -+ IX_MBUF_MDATA(sec) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); -+ } -+ -+ /* Only need to register if a crypt op or HMAC op */ -+ if (!(ixp->ixp_auth_alg == CRYPTO_SHA1 || -+ ixp->ixp_auth_alg == CRYPTO_MD5)) { -+ status = ixCryptoAccCtxRegister( -+ &ixp->ixp_ctx, -+ pri, sec, -+ ixp_register_cb, -+ ixp_perform_cb, -+ &ixp->ixp_ctx_id); -+ } -+ else { -+ /* Otherwise we start processing pending q */ -+ schedule_work(&ixp->ixp_pending_work); -+ } -+ -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) -+ return; -+ -+ if (IX_CRYPTO_ACC_STATUS_EXCEED_MAX_TUNNELS == status) { -+ printk("ixp: ixCryptoAccCtxRegister failed (out of tunnels)\n"); -+ ixp_blocked = 1; -+ /* perhaps we should return EGAIN on queued ops ? */ -+ return; -+ } -+ -+ printk("ixp: ixCryptoAccCtxRegister failed %d\n", status); -+ ixp->ixp_ctx_id = -1; -+ -+ /* -+ * everything waiting is toasted -+ */ -+ while (!list_empty(&ixp->ixp_q)) { -+ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); -+ list_del(&q->ixp_q_list); -+ q->ixp_q_crp->crp_etype = ENOENT; -+ crypto_done(q->ixp_q_crp); -+ kmem_cache_free(qcache, q); -+ } -+} -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void -+ixp_registration_wq(struct work_struct *work) -+{ -+ struct ixp_data *ixp = container_of(work, struct ixp_data, -+ ixp_registration_work); -+ ixp_registration(ixp); -+} -+#endif -+ -+/* -+ * Process a request. -+ */ -+static int -+ixp_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ struct ixp_data *ixp; -+ unsigned int lid; -+ struct ixp_q *q = NULL; -+ int status; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ /* Sanity check */ -+ if (crp == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ crp->crp_etype = 0; -+ -+ if (ixp_blocked) -+ return ERESTART; -+ -+ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ /* -+ * find the session we are using -+ */ -+ -+ lid = crp->crp_sid & 0xffffffff; -+ if (lid >= ixp_sesnum || lid == 0 || ixp_sessions == NULL || -+ ixp_sessions[lid] == NULL) { -+ crp->crp_etype = ENOENT; -+ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); -+ goto done; -+ } -+ ixp = ixp_sessions[lid]; -+ -+ /* -+ * setup a new request ready for queuing -+ */ -+ q = kmem_cache_alloc(qcache, SLAB_ATOMIC); -+ if (q == NULL) { -+ dprintk("%s,%d: ENOMEM\n", __FILE__, __LINE__); -+ crp->crp_etype = ENOMEM; -+ goto done; -+ } -+ /* -+ * save some cycles by only zeroing the important bits -+ */ -+ memset(&q->ixp_q_mbuf, 0, sizeof(q->ixp_q_mbuf)); -+ q->ixp_q_ccrd = NULL; -+ q->ixp_q_acrd = NULL; -+ q->ixp_q_crp = crp; -+ q->ixp_q_data = ixp; -+ -+ /* -+ * point the cipher and auth descriptors appropriately -+ * check that we have something to do -+ */ -+ if (crp->crp_desc->crd_alg == ixp->ixp_cipher_alg) -+ q->ixp_q_ccrd = crp->crp_desc; -+ else if (crp->crp_desc->crd_alg == ixp->ixp_auth_alg) -+ q->ixp_q_acrd = crp->crp_desc; -+ else { -+ crp->crp_etype = ENOENT; -+ dprintk("%s,%d: bad desc match: ENOENT\n", __FILE__, __LINE__); -+ goto done; -+ } -+ if (crp->crp_desc->crd_next) { -+ if (crp->crp_desc->crd_next->crd_alg == ixp->ixp_cipher_alg) -+ q->ixp_q_ccrd = crp->crp_desc->crd_next; -+ else if (crp->crp_desc->crd_next->crd_alg == ixp->ixp_auth_alg) -+ q->ixp_q_acrd = crp->crp_desc->crd_next; -+ else { -+ crp->crp_etype = ENOENT; -+ dprintk("%s,%d: bad desc match: ENOENT\n", __FILE__, __LINE__); -+ goto done; -+ } -+ } -+ -+ /* -+ * If there is a direction change for this context then we mark it as -+ * unregistered and re-register is for the new direction. This is not -+ * a very expensive operation and currently only tends to happen when -+ * user-space application are doing benchmarks -+ * -+ * DM - we should be checking for pending requests before unregistering. -+ */ -+ if (q->ixp_q_ccrd && ixp->ixp_registered && -+ ixp->ixp_crd_flags != (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT)) { -+ dprintk("%s - detected direction change on session\n", __FUNCTION__); -+ ixp->ixp_registered = 0; -+ } -+ -+ /* -+ * if we are registered, call straight into the perform code -+ */ -+ if (ixp->ixp_registered) { -+ ixp_q_process(q); -+ return 0; -+ } -+ -+ /* -+ * the only part of the context not set in newsession is the direction -+ * dependent parts -+ */ -+ if (q->ixp_q_ccrd) { -+ ixp->ixp_crd_flags = (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT); -+ if (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT) { -+ ixp->ixp_ctx.operation = q->ixp_q_acrd ? -+ IX_CRYPTO_ACC_OP_ENCRYPT_AUTH : IX_CRYPTO_ACC_OP_ENCRYPT; -+ } else { -+ ixp->ixp_ctx.operation = q->ixp_q_acrd ? -+ IX_CRYPTO_ACC_OP_AUTH_DECRYPT : IX_CRYPTO_ACC_OP_DECRYPT; -+ } -+ } else { -+ /* q->ixp_q_acrd must be set if we are here */ -+ ixp->ixp_ctx.operation = IX_CRYPTO_ACC_OP_AUTH_CALC; -+ } -+ -+ status = list_empty(&ixp->ixp_q); -+ list_add_tail(&q->ixp_q_list, &ixp->ixp_q); -+ if (status) -+ schedule_work(&ixp->ixp_registration_work); -+ return 0; -+ -+done: -+ if (q) -+ kmem_cache_free(qcache, q); -+ crypto_done(crp); -+ return 0; -+} -+ -+ -+#ifdef __ixp46X -+/* -+ * key processing support for the ixp465 -+ */ -+ -+ -+/* -+ * copy a BN (LE) into a buffer (BE) an fill out the op appropriately -+ * assume zeroed and only copy bits that are significant -+ */ -+ -+static int -+ixp_copy_ibuf(struct crparam *p, IxCryptoAccPkeEauOperand *op, UINT32 *buf) -+{ -+ unsigned char *src = (unsigned char *) p->crp_p; -+ unsigned char *dst; -+ int len, bits = p->crp_nbits; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (bits > MAX_IOP_SIZE * sizeof(UINT32) * 8) { -+ dprintk("%s - ibuf too big (%d > %d)\n", __FUNCTION__, -+ bits, MAX_IOP_SIZE * sizeof(UINT32) * 8); -+ return -1; -+ } -+ -+ len = (bits + 31) / 32; /* the number UINT32's needed */ -+ -+ dst = (unsigned char *) &buf[len]; -+ dst--; -+ -+ while (bits > 0) { -+ *dst-- = *src++; -+ bits -= 8; -+ } -+ -+#if 0 /* no need to zero remaining bits as it is done during request alloc */ -+ while (dst > (unsigned char *) buf) -+ *dst-- = '\0'; -+#endif -+ -+ op->pData = buf; -+ op->dataLen = len; -+ return 0; -+} -+ -+/* -+ * copy out the result, be as forgiving as we can about small output buffers -+ */ -+ -+static int -+ixp_copy_obuf(struct crparam *p, IxCryptoAccPkeEauOpResult *op, UINT32 *buf) -+{ -+ unsigned char *dst = (unsigned char *) p->crp_p; -+ unsigned char *src = (unsigned char *) buf; -+ int len, z, bits = p->crp_nbits; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ len = op->dataLen * sizeof(UINT32); -+ -+ /* skip leading zeroes to be small buffer friendly */ -+ z = 0; -+ while (z < len && src[z] == '\0') -+ z++; -+ -+ src += len; -+ src--; -+ len -= z; -+ -+ while (len > 0 && bits > 0) { -+ *dst++ = *src--; -+ len--; -+ bits -= 8; -+ } -+ -+ while (bits > 0) { -+ *dst++ = '\0'; -+ bits -= 8; -+ } -+ -+ if (len > 0) { -+ dprintk("%s - obuf is %d (z=%d, ob=%d) bytes too small\n", -+ __FUNCTION__, len, z, p->crp_nbits / 8); -+ return -1; -+ } -+ -+ return 0; -+} -+ -+ -+/* -+ * the parameter offsets for exp_mod -+ */ -+ -+#define IXP_PARAM_BASE 0 -+#define IXP_PARAM_EXP 1 -+#define IXP_PARAM_MOD 2 -+#define IXP_PARAM_RES 3 -+ -+/* -+ * key processing complete callback, is also used to start processing -+ * by passing a NULL for pResult -+ */ -+ -+static void -+ixp_kperform_cb( -+ IxCryptoAccPkeEauOperation operation, -+ IxCryptoAccPkeEauOpResult *pResult, -+ BOOL carryOrBorrow, -+ IxCryptoAccStatus status) -+{ -+ struct ixp_pkq *q, *tmp; -+ unsigned long flags; -+ -+ dprintk("%s(0x%x, %p, %d, 0x%x)\n", __FUNCTION__, operation, pResult, -+ carryOrBorrow, status); -+ -+ /* handle a completed request */ -+ if (pResult) { -+ if (ixp_pk_cur && &ixp_pk_cur->pkq_result == pResult) { -+ q = ixp_pk_cur; -+ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { -+ dprintk("%s() - op failed 0x%x\n", __FUNCTION__, status); -+ q->pkq_krp->krp_status = ERANGE; /* could do better */ -+ } else { -+ /* copy out the result */ -+ if (ixp_copy_obuf(&q->pkq_krp->krp_param[IXP_PARAM_RES], -+ &q->pkq_result, q->pkq_obuf)) -+ q->pkq_krp->krp_status = ERANGE; -+ } -+ crypto_kdone(q->pkq_krp); -+ kfree(q); -+ ixp_pk_cur = NULL; -+ } else -+ printk("%s - callback with invalid result pointer\n", __FUNCTION__); -+ } -+ -+ spin_lock_irqsave(&ixp_pkq_lock, flags); -+ if (ixp_pk_cur || list_empty(&ixp_pkq)) { -+ spin_unlock_irqrestore(&ixp_pkq_lock, flags); -+ return; -+ } -+ -+ list_for_each_entry_safe(q, tmp, &ixp_pkq, pkq_list) { -+ -+ list_del(&q->pkq_list); -+ ixp_pk_cur = q; -+ -+ spin_unlock_irqrestore(&ixp_pkq_lock, flags); -+ -+ status = ixCryptoAccPkeEauPerform( -+ IX_CRYPTO_ACC_OP_EAU_MOD_EXP, -+ &q->pkq_op, -+ ixp_kperform_cb, -+ &q->pkq_result); -+ -+ if (status == IX_CRYPTO_ACC_STATUS_SUCCESS) { -+ dprintk("%s() - ixCryptoAccPkeEauPerform SUCCESS\n", __FUNCTION__); -+ return; /* callback will return here for callback */ -+ } else if (status == IX_CRYPTO_ACC_STATUS_RETRY) { -+ printk("%s() - ixCryptoAccPkeEauPerform RETRY\n", __FUNCTION__); -+ } else { -+ printk("%s() - ixCryptoAccPkeEauPerform failed %d\n", -+ __FUNCTION__, status); -+ } -+ q->pkq_krp->krp_status = ERANGE; /* could do better */ -+ crypto_kdone(q->pkq_krp); -+ kfree(q); -+ spin_lock_irqsave(&ixp_pkq_lock, flags); -+ } -+ spin_unlock_irqrestore(&ixp_pkq_lock, flags); -+} -+ -+ -+static int -+ixp_kprocess(device_t dev, struct cryptkop *krp, int hint) -+{ -+ struct ixp_pkq *q; -+ int rc = 0; -+ unsigned long flags; -+ -+ dprintk("%s l1=%d l2=%d l3=%d l4=%d\n", __FUNCTION__, -+ krp->krp_param[IXP_PARAM_BASE].crp_nbits, -+ krp->krp_param[IXP_PARAM_EXP].crp_nbits, -+ krp->krp_param[IXP_PARAM_MOD].crp_nbits, -+ krp->krp_param[IXP_PARAM_RES].crp_nbits); -+ -+ -+ if (krp->krp_op != CRK_MOD_EXP) { -+ krp->krp_status = EOPNOTSUPP; -+ goto err; -+ } -+ -+ q = (struct ixp_pkq *) kmalloc(sizeof(*q), GFP_KERNEL); -+ if (q == NULL) { -+ krp->krp_status = ENOMEM; -+ goto err; -+ } -+ -+ /* -+ * The PKE engine does not appear to zero the output buffer -+ * appropriately, so we need to do it all here. -+ */ -+ memset(q, 0, sizeof(*q)); -+ -+ q->pkq_krp = krp; -+ INIT_LIST_HEAD(&q->pkq_list); -+ -+ if (ixp_copy_ibuf(&krp->krp_param[IXP_PARAM_BASE], &q->pkq_op.modExpOpr.M, -+ q->pkq_ibuf0)) -+ rc = 1; -+ if (!rc && ixp_copy_ibuf(&krp->krp_param[IXP_PARAM_EXP], -+ &q->pkq_op.modExpOpr.e, q->pkq_ibuf1)) -+ rc = 2; -+ if (!rc && ixp_copy_ibuf(&krp->krp_param[IXP_PARAM_MOD], -+ &q->pkq_op.modExpOpr.N, q->pkq_ibuf2)) -+ rc = 3; -+ -+ if (rc) { -+ kfree(q); -+ krp->krp_status = ERANGE; -+ goto err; -+ } -+ -+ q->pkq_result.pData = q->pkq_obuf; -+ q->pkq_result.dataLen = -+ (krp->krp_param[IXP_PARAM_RES].crp_nbits + 31) / 32; -+ -+ spin_lock_irqsave(&ixp_pkq_lock, flags); -+ list_add_tail(&q->pkq_list, &ixp_pkq); -+ spin_unlock_irqrestore(&ixp_pkq_lock, flags); -+ -+ if (!ixp_pk_cur) -+ ixp_kperform_cb(0, NULL, 0, 0); -+ return (0); -+ -+err: -+ crypto_kdone(krp); -+ return (0); -+} -+ -+ -+ -+#ifdef CONFIG_OCF_RANDOMHARVEST -+/* -+ * We run the random number generator output through SHA so that it -+ * is FIPS compliant. -+ */ -+ -+static volatile int sha_done = 0; -+static unsigned char sha_digest[20]; -+ -+static void -+ixp_hash_cb(UINT8 *digest, IxCryptoAccStatus status) -+{ -+ dprintk("%s(%p, %d)\n", __FUNCTION__, digest, status); -+ if (sha_digest != digest) -+ printk("digest error\n"); -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) -+ sha_done = 1; -+ else -+ sha_done = -status; -+} -+ -+static int -+ixp_read_random(void *arg, u_int32_t *buf, int maxwords) -+{ -+ IxCryptoAccStatus status; -+ int i, n, rc; -+ -+ dprintk("%s(%p, %d)\n", __FUNCTION__, buf, maxwords); -+ memset(buf, 0, maxwords * sizeof(*buf)); -+ status = ixCryptoAccPkePseudoRandomNumberGet(maxwords, buf); -+ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { -+ dprintk("%s: ixCryptoAccPkePseudoRandomNumberGet failed %d\n", -+ __FUNCTION__, status); -+ return 0; -+ } -+ -+ /* -+ * run the random data through SHA to make it look more random -+ */ -+ -+ n = sizeof(sha_digest); /* process digest bytes at a time */ -+ -+ rc = 0; -+ for (i = 0; i < maxwords; i += n / sizeof(*buf)) { -+ if ((maxwords - i) * sizeof(*buf) < n) -+ n = (maxwords - i) * sizeof(*buf); -+ sha_done = 0; -+ status = ixCryptoAccPkeHashPerform(IX_CRYPTO_ACC_AUTH_SHA1, -+ (UINT8 *) &buf[i], n, ixp_hash_cb, sha_digest); -+ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { -+ dprintk("ixCryptoAccPkeHashPerform failed %d\n", status); -+ return -EIO; -+ } -+ while (!sha_done) -+ schedule(); -+ if (sha_done < 0) { -+ dprintk("ixCryptoAccPkeHashPerform failed CB %d\n", -sha_done); -+ return 0; -+ } -+ memcpy(&buf[i], sha_digest, n); -+ rc += n / sizeof(*buf);; -+ } -+ -+ return rc; -+} -+#endif /* CONFIG_OCF_RANDOMHARVEST */ -+ -+#endif /* __ixp46X */ -+ -+ -+ -+/* -+ * our driver startup and shutdown routines -+ */ -+ -+static int -+ixp_init(void) -+{ -+ dprintk("%s(%p)\n", __FUNCTION__, ixp_init); -+ -+ if (ixp_init_crypto && ixCryptoAccInit() != IX_CRYPTO_ACC_STATUS_SUCCESS) -+ printk("ixCryptoAccInit failed, assuming already initialised!\n"); -+ -+ qcache = kmem_cache_create("ixp4xx_q", sizeof(struct ixp_q), 0, -+ SLAB_HWCACHE_ALIGN, NULL -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) -+ , NULL -+#endif -+ ); -+ if (!qcache) { -+ printk("failed to create Qcache\n"); -+ return -ENOENT; -+ } -+ -+ memset(&ixpdev, 0, sizeof(ixpdev)); -+ softc_device_init(&ixpdev, "ixp4xx", 0, ixp_methods); -+ -+ ixp_id = crypto_get_driverid(softc_get_device(&ixpdev), -+ CRYPTOCAP_F_HARDWARE); -+ if (ixp_id < 0) -+ panic("IXP/OCF crypto device cannot initialize!"); -+ -+#define REGISTER(alg) \ -+ crypto_register(ixp_id,alg,0,0) -+ -+ REGISTER(CRYPTO_DES_CBC); -+ REGISTER(CRYPTO_3DES_CBC); -+ REGISTER(CRYPTO_RIJNDAEL128_CBC); -+#ifdef CONFIG_OCF_IXP4XX_SHA1_MD5 -+ REGISTER(CRYPTO_MD5); -+ REGISTER(CRYPTO_SHA1); -+#endif -+ REGISTER(CRYPTO_MD5_HMAC); -+ REGISTER(CRYPTO_SHA1_HMAC); -+#undef REGISTER -+ -+#ifdef __ixp46X -+ spin_lock_init(&ixp_pkq_lock); -+ /* -+ * we do not enable the go fast options here as they can potentially -+ * allow timing based attacks -+ * -+ * http://www.openssl.org/news/secadv_20030219.txt -+ */ -+ ixCryptoAccPkeEauExpConfig(0, 0); -+ crypto_kregister(ixp_id, CRK_MOD_EXP, 0); -+#ifdef CONFIG_OCF_RANDOMHARVEST -+ crypto_rregister(ixp_id, ixp_read_random, NULL); -+#endif -+#endif -+ -+ return 0; -+} -+ -+static void -+ixp_exit(void) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ crypto_unregister_all(ixp_id); -+ ixp_id = -1; -+ kmem_cache_destroy(qcache); -+ qcache = NULL; -+} -+ -+module_init(ixp_init); -+module_exit(ixp_exit); -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("ixp (OCF module for IXP4xx crypto)"); -diff -Nur linux-2.6.36.orig/crypto/ocf/ixp4xx/Makefile linux-2.6.36/crypto/ocf/ixp4xx/Makefile ---- linux-2.6.36.orig/crypto/ocf/ixp4xx/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/ixp4xx/Makefile 2010-11-09 20:28:05.113478850 +0100 -@@ -0,0 +1,104 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+# -+# You will need to point this at your Intel ixp425 includes, this portion -+# of the Makefile only really works under SGLinux with the appropriate libs -+# installed. They can be downloaded from http://www.snapgear.org/ -+# -+ifeq ($(CONFIG_CPU_IXP46X),y) -+IXPLATFORM = ixp46X -+else -+ifeq ($(CONFIG_CPU_IXP43X),y) -+IXPLATFORM = ixp43X -+else -+IXPLATFORM = ixp42X -+endif -+endif -+ -+ifdef CONFIG_IXP400_LIB_2_4 -+IX_XSCALE_SW = $(ROOTDIR)/modules/ixp425/ixp400-2.4/ixp400_xscale_sw -+OSAL_DIR = $(ROOTDIR)/modules/ixp425/ixp400-2.4/ixp_osal -+endif -+ifdef CONFIG_IXP400_LIB_2_1 -+IX_XSCALE_SW = $(ROOTDIR)/modules/ixp425/ixp400-2.1/ixp400_xscale_sw -+OSAL_DIR = $(ROOTDIR)/modules/ixp425/ixp400-2.1/ixp_osal -+endif -+ifdef CONFIG_IXP400_LIB_2_0 -+IX_XSCALE_SW = $(ROOTDIR)/modules/ixp425/ixp400-2.0/ixp400_xscale_sw -+OSAL_DIR = $(ROOTDIR)/modules/ixp425/ixp400-2.0/ixp_osal -+endif -+ifdef IX_XSCALE_SW -+ifdef CONFIG_IXP400_LIB_2_4 -+IXP_CFLAGS = \ -+ -I$(ROOTDIR)/. \ -+ -I$(IX_XSCALE_SW)/src/include \ -+ -I$(OSAL_DIR)/common/include/ \ -+ -I$(OSAL_DIR)/common/include/modules/ \ -+ -I$(OSAL_DIR)/common/include/modules/ddk/ \ -+ -I$(OSAL_DIR)/common/include/modules/bufferMgt/ \ -+ -I$(OSAL_DIR)/common/include/modules/ioMem/ \ -+ -I$(OSAL_DIR)/common/os/linux/include/ \ -+ -I$(OSAL_DIR)/common/os/linux/include/core/ \ -+ -I$(OSAL_DIR)/common/os/linux/include/modules/ \ -+ -I$(OSAL_DIR)/common/os/linux/include/modules/ddk/ \ -+ -I$(OSAL_DIR)/common/os/linux/include/modules/bufferMgt/ \ -+ -I$(OSAL_DIR)/common/os/linux/include/modules/ioMem/ \ -+ -I$(OSAL_DIR)/platforms/$(IXPLATFORM)/include/ \ -+ -I$(OSAL_DIR)/platforms/$(IXPLATFORM)/os/linux/include/ \ -+ -DENABLE_IOMEM -DENABLE_BUFFERMGT -DENABLE_DDK \ -+ -DUSE_IXP4XX_CRYPTO -+else -+IXP_CFLAGS = \ -+ -I$(ROOTDIR)/. \ -+ -I$(IX_XSCALE_SW)/src/include \ -+ -I$(OSAL_DIR)/ \ -+ -I$(OSAL_DIR)/os/linux/include/ \ -+ -I$(OSAL_DIR)/os/linux/include/modules/ \ -+ -I$(OSAL_DIR)/os/linux/include/modules/ioMem/ \ -+ -I$(OSAL_DIR)/os/linux/include/modules/bufferMgt/ \ -+ -I$(OSAL_DIR)/os/linux/include/core/ \ -+ -I$(OSAL_DIR)/os/linux/include/platforms/ \ -+ -I$(OSAL_DIR)/os/linux/include/platforms/ixp400/ \ -+ -I$(OSAL_DIR)/os/linux/include/platforms/ixp400/ixp425 \ -+ -I$(OSAL_DIR)/os/linux/include/platforms/ixp400/ixp465 \ -+ -I$(OSAL_DIR)/os/linux/include/core/ \ -+ -I$(OSAL_DIR)/include/ \ -+ -I$(OSAL_DIR)/include/modules/ \ -+ -I$(OSAL_DIR)/include/modules/bufferMgt/ \ -+ -I$(OSAL_DIR)/include/modules/ioMem/ \ -+ -I$(OSAL_DIR)/include/platforms/ \ -+ -I$(OSAL_DIR)/include/platforms/ixp400/ \ -+ -DUSE_IXP4XX_CRYPTO -+endif -+endif -+ifdef CONFIG_IXP400_LIB_1_4 -+IXP_CFLAGS = \ -+ -I$(ROOTDIR)/. \ -+ -I$(ROOTDIR)/modules/ixp425/ixp400-1.4/ixp400_xscale_sw/src/include \ -+ -I$(ROOTDIR)/modules/ixp425/ixp400-1.4/ixp400_xscale_sw/src/linux \ -+ -DUSE_IXP4XX_CRYPTO -+endif -+ifndef IXPDIR -+IXPDIR = ixp-version-is-not-supported -+endif -+ -+ifeq ($(CONFIG_CPU_IXP46X),y) -+IXP_CFLAGS += -D__ixp46X -+else -+ifeq ($(CONFIG_CPU_IXP43X),y) -+IXP_CFLAGS += -D__ixp43X -+else -+IXP_CFLAGS += -D__ixp42X -+endif -+endif -+ -+obj-$(CONFIG_OCF_IXP4XX) += ixp4xx.o -+ -+obj ?= . -+EXTRA_CFLAGS += $(IXP_CFLAGS) -I$(obj)/.. -I$(obj)/. -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/Kconfig linux-2.6.36/crypto/ocf/Kconfig ---- linux-2.6.36.orig/crypto/ocf/Kconfig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/Kconfig 2010-11-09 20:28:05.141255099 +0100 -@@ -0,0 +1,119 @@ -+menu "OCF Configuration" -+ -+config OCF_OCF -+ tristate "OCF (Open Cryptograhic Framework)" -+ help -+ A linux port of the OpenBSD/FreeBSD crypto framework. -+ -+config OCF_RANDOMHARVEST -+ bool "crypto random --- harvest entropy for /dev/random" -+ depends on OCF_OCF -+ help -+ Includes code to harvest random numbers from devices that support it. -+ -+config OCF_FIPS -+ bool "enable fips RNG checks" -+ depends on OCF_OCF && OCF_RANDOMHARVEST -+ help -+ Run all RNG provided data through a fips check before -+ adding it /dev/random's entropy pool. -+ -+config OCF_CRYPTODEV -+ tristate "cryptodev (user space support)" -+ depends on OCF_OCF -+ help -+ The user space API to access crypto hardware. -+ -+config OCF_CRYPTOSOFT -+ tristate "cryptosoft (software crypto engine)" -+ depends on OCF_OCF -+ help -+ A software driver for the OCF framework that uses -+ the kernel CryptoAPI. -+ -+config OCF_SAFE -+ tristate "safenet (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ A driver for a number of the safenet Excel crypto accelerators. -+ Currently tested and working on the 1141 and 1741. -+ -+config OCF_IXP4XX -+ tristate "IXP4xx (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ XScale IXP4xx crypto accelerator driver. Requires the -+ Intel Access library. -+ -+config OCF_IXP4XX_SHA1_MD5 -+ bool "IXP4xx SHA1 and MD5 Hashing" -+ depends on OCF_IXP4XX -+ help -+ Allows the IXP4xx crypto accelerator to perform SHA1 and MD5 hashing. -+ Note: this is MUCH slower than using cryptosoft (software crypto engine). -+ -+config OCF_HIFN -+ tristate "hifn (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for various HIFN based crypto accelerators. -+ (7951, 7955, 7956, 7751, 7811) -+ -+config OCF_HIFNHIPP -+ tristate "Hifn HIPP (HW packet crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for various HIFN (HIPP) based crypto accelerators -+ (7855) -+ -+config OCF_TALITOS -+ tristate "talitos (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for Freescale's security engine (SEC/talitos). -+ -+config OCF_PASEMI -+ tristate "pasemi (HW crypto engine)" -+ depends on OCF_OCF && PPC_PASEMI -+ help -+ OCF driver for the PA Semi PWRficient DMA Engine -+ -+config OCF_EP80579 -+ tristate "ep80579 (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for the Intel EP80579 Integrated Processor Product Line. -+ -+config OCF_CRYPTOCTEON -+ tristate "cryptocteon (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for the Cavium OCTEON Processors. -+ -+config OCF_KIRKWOOD -+ tristate "kirkwood (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for the Marvell Kirkwood (88F6xxx) Processors. -+ -+config OCF_C7108 -+ tristate "Micronas 7108 (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for the Microna 7108 Cipher processors. -+ -+config OCF_OCFNULL -+ tristate "ocfnull (fake crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for measuring ipsec overheads (does no crypto) -+ -+config OCF_BENCH -+ tristate "ocf-bench (HW crypto in-kernel benchmark)" -+ depends on OCF_OCF -+ help -+ A very simple encryption test for the in-kernel interface -+ of OCF. Also includes code to benchmark the IXP Access library -+ for comparison. -+ -+endmenu -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.c linux-2.6.36/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.c 2010-11-09 20:28:05.189557501 +0100 -@@ -0,0 +1,317 @@ -+/* rijndael-alg-ref.c v2.0 August '99 -+ * Reference ANSI C code -+ * authors: Paulo Barreto -+ * Vincent Rijmen, K.U.Leuven -+ * -+ * This code is placed in the public domain. -+ */ -+ -+#include "mvOs.h" -+ -+#include "mvAesAlg.h" -+ -+#include "mvAesBoxes.dat" -+ -+ -+MV_U8 mul1(MV_U8 aa, MV_U8 bb); -+void KeyAddition(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC], MV_U8 BC); -+void ShiftRow128Enc(MV_U8 a[4][MAXBC]); -+void ShiftRow128Dec(MV_U8 a[4][MAXBC]); -+void Substitution(MV_U8 a[4][MAXBC], MV_U8 box[256]); -+void MixColumn(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC]); -+void InvMixColumn(MV_U8 a[4][MAXBC]); -+ -+ -+#define mul(aa, bb) (mask[bb] & Alogtable[aa + Logtable[bb]]) -+ -+MV_U8 mul1(MV_U8 aa, MV_U8 bb) -+{ -+ return mask[bb] & Alogtable[aa + Logtable[bb]]; -+} -+ -+ -+void KeyAddition(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC], MV_U8 BC) -+{ -+ /* Exor corresponding text input and round key input bytes -+ */ -+ ((MV_U32*)(&(a[0][0])))[0] ^= ((MV_U32*)(&(rk[0][0])))[0]; -+ ((MV_U32*)(&(a[1][0])))[0] ^= ((MV_U32*)(&(rk[1][0])))[0]; -+ ((MV_U32*)(&(a[2][0])))[0] ^= ((MV_U32*)(&(rk[2][0])))[0]; -+ ((MV_U32*)(&(a[3][0])))[0] ^= ((MV_U32*)(&(rk[3][0])))[0]; -+ -+} -+ -+void ShiftRow128Enc(MV_U8 a[4][MAXBC]) { -+ /* Row 0 remains unchanged -+ * The other three rows are shifted a variable amount -+ */ -+ MV_U8 tmp[MAXBC]; -+ -+ tmp[0] = a[1][1]; -+ tmp[1] = a[1][2]; -+ tmp[2] = a[1][3]; -+ tmp[3] = a[1][0]; -+ -+ ((MV_U32*)(&(a[1][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; -+ /* -+ a[1][0] = tmp[0]; -+ a[1][1] = tmp[1]; -+ a[1][2] = tmp[2]; -+ a[1][3] = tmp[3]; -+ */ -+ tmp[0] = a[2][2]; -+ tmp[1] = a[2][3]; -+ tmp[2] = a[2][0]; -+ tmp[3] = a[2][1]; -+ -+ ((MV_U32*)(&(a[2][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; -+ /* -+ a[2][0] = tmp[0]; -+ a[2][1] = tmp[1]; -+ a[2][2] = tmp[2]; -+ a[2][3] = tmp[3]; -+ */ -+ tmp[0] = a[3][3]; -+ tmp[1] = a[3][0]; -+ tmp[2] = a[3][1]; -+ tmp[3] = a[3][2]; -+ -+ ((MV_U32*)(&(a[3][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; -+ /* -+ a[3][0] = tmp[0]; -+ a[3][1] = tmp[1]; -+ a[3][2] = tmp[2]; -+ a[3][3] = tmp[3]; -+ */ -+} -+ -+void ShiftRow128Dec(MV_U8 a[4][MAXBC]) { -+ /* Row 0 remains unchanged -+ * The other three rows are shifted a variable amount -+ */ -+ MV_U8 tmp[MAXBC]; -+ -+ tmp[0] = a[1][3]; -+ tmp[1] = a[1][0]; -+ tmp[2] = a[1][1]; -+ tmp[3] = a[1][2]; -+ -+ ((MV_U32*)(&(a[1][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; -+ /* -+ a[1][0] = tmp[0]; -+ a[1][1] = tmp[1]; -+ a[1][2] = tmp[2]; -+ a[1][3] = tmp[3]; -+ */ -+ -+ tmp[0] = a[2][2]; -+ tmp[1] = a[2][3]; -+ tmp[2] = a[2][0]; -+ tmp[3] = a[2][1]; -+ -+ ((MV_U32*)(&(a[2][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; -+ /* -+ a[2][0] = tmp[0]; -+ a[2][1] = tmp[1]; -+ a[2][2] = tmp[2]; -+ a[2][3] = tmp[3]; -+ */ -+ -+ tmp[0] = a[3][1]; -+ tmp[1] = a[3][2]; -+ tmp[2] = a[3][3]; -+ tmp[3] = a[3][0]; -+ -+ ((MV_U32*)(&(a[3][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; -+ /* -+ a[3][0] = tmp[0]; -+ a[3][1] = tmp[1]; -+ a[3][2] = tmp[2]; -+ a[3][3] = tmp[3]; -+ */ -+} -+ -+void Substitution(MV_U8 a[4][MAXBC], MV_U8 box[256]) { -+ /* Replace every byte of the input by the byte at that place -+ * in the nonlinear S-box -+ */ -+ int i, j; -+ -+ for(i = 0; i < 4; i++) -+ for(j = 0; j < 4; j++) a[i][j] = box[a[i][j]] ; -+} -+ -+void MixColumn(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC]) { -+ /* Mix the four bytes of every column in a linear way -+ */ -+ MV_U8 b[4][MAXBC]; -+ int i, j; -+ -+ for(j = 0; j < 4; j++){ -+ b[0][j] = mul(25,a[0][j]) ^ mul(1,a[1][j]) ^ a[2][j] ^ a[3][j]; -+ b[1][j] = mul(25,a[1][j]) ^ mul(1,a[2][j]) ^ a[3][j] ^ a[0][j]; -+ b[2][j] = mul(25,a[2][j]) ^ mul(1,a[3][j]) ^ a[0][j] ^ a[1][j]; -+ b[3][j] = mul(25,a[3][j]) ^ mul(1,a[0][j]) ^ a[1][j] ^ a[2][j]; -+ } -+ for(i = 0; i < 4; i++) -+ /*for(j = 0; j < BC; j++) a[i][j] = b[i][j];*/ -+ ((MV_U32*)(&(a[i][0])))[0] = ((MV_U32*)(&(b[i][0])))[0] ^ ((MV_U32*)(&(rk[i][0])))[0];; -+} -+ -+void InvMixColumn(MV_U8 a[4][MAXBC]) { -+ /* Mix the four bytes of every column in a linear way -+ * This is the opposite operation of Mixcolumn -+ */ -+ MV_U8 b[4][MAXBC]; -+ int i, j; -+ -+ for(j = 0; j < 4; j++){ -+ b[0][j] = mul(223,a[0][j]) ^ mul(104,a[1][j]) ^ mul(238,a[2][j]) ^ mul(199,a[3][j]); -+ b[1][j] = mul(223,a[1][j]) ^ mul(104,a[2][j]) ^ mul(238,a[3][j]) ^ mul(199,a[0][j]); -+ b[2][j] = mul(223,a[2][j]) ^ mul(104,a[3][j]) ^ mul(238,a[0][j]) ^ mul(199,a[1][j]); -+ b[3][j] = mul(223,a[3][j]) ^ mul(104,a[0][j]) ^ mul(238,a[1][j]) ^ mul(199,a[2][j]); -+ } -+ for(i = 0; i < 4; i++) -+ /*for(j = 0; j < BC; j++) a[i][j] = b[i][j];*/ -+ ((MV_U32*)(&(a[i][0])))[0] = ((MV_U32*)(&(b[i][0])))[0]; -+} -+ -+int rijndaelKeySched (MV_U8 k[4][MAXKC], int keyBits, int blockBits, MV_U8 W[MAXROUNDS+1][4][MAXBC]) -+{ -+ /* Calculate the necessary round keys -+ * The number of calculations depends on keyBits and blockBits -+ */ -+ int KC, BC, ROUNDS; -+ int i, j, t, rconpointer = 0; -+ MV_U8 tk[4][MAXKC]; -+ -+ switch (keyBits) { -+ case 128: KC = 4; break; -+ case 192: KC = 6; break; -+ case 256: KC = 8; break; -+ default : return (-1); -+ } -+ -+ switch (blockBits) { -+ case 128: BC = 4; break; -+ case 192: BC = 6; break; -+ case 256: BC = 8; break; -+ default : return (-2); -+ } -+ -+ switch (keyBits >= blockBits ? keyBits : blockBits) { -+ case 128: ROUNDS = 10; break; -+ case 192: ROUNDS = 12; break; -+ case 256: ROUNDS = 14; break; -+ default : return (-3); /* this cannot happen */ -+ } -+ -+ -+ for(j = 0; j < KC; j++) -+ for(i = 0; i < 4; i++) -+ tk[i][j] = k[i][j]; -+ t = 0; -+ /* copy values into round key array */ -+ for(j = 0; (j < KC) && (t < (ROUNDS+1)*BC); j++, t++) -+ for(i = 0; i < 4; i++) W[t / BC][i][t % BC] = tk[i][j]; -+ -+ while (t < (ROUNDS+1)*BC) { /* while not enough round key material calculated */ -+ /* calculate new values */ -+ for(i = 0; i < 4; i++) -+ tk[i][0] ^= S[tk[(i+1)%4][KC-1]]; -+ tk[0][0] ^= rcon[rconpointer++]; -+ -+ if (KC != 8) -+ for(j = 1; j < KC; j++) -+ for(i = 0; i < 4; i++) tk[i][j] ^= tk[i][j-1]; -+ else { -+ for(j = 1; j < KC/2; j++) -+ for(i = 0; i < 4; i++) tk[i][j] ^= tk[i][j-1]; -+ for(i = 0; i < 4; i++) tk[i][KC/2] ^= S[tk[i][KC/2 - 1]]; -+ for(j = KC/2 + 1; j < KC; j++) -+ for(i = 0; i < 4; i++) tk[i][j] ^= tk[i][j-1]; -+ } -+ /* copy values into round key array */ -+ for(j = 0; (j < KC) && (t < (ROUNDS+1)*BC); j++, t++) -+ for(i = 0; i < 4; i++) W[t / BC][i][t % BC] = tk[i][j]; -+ } -+ -+ return 0; -+} -+ -+ -+ -+int rijndaelEncrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds) -+{ -+ /* Encryption of one block. -+ */ -+ int r, BC, ROUNDS; -+ -+ BC = 4; -+ ROUNDS = rounds; -+ -+ /* begin with a key addition -+ */ -+ -+ KeyAddition(a,rk[0],BC); -+ -+ /* ROUNDS-1 ordinary rounds -+ */ -+ for(r = 1; r < ROUNDS; r++) { -+ Substitution(a,S); -+ ShiftRow128Enc(a); -+ MixColumn(a, rk[r]); -+ /*KeyAddition(a,rk[r],BC);*/ -+ } -+ -+ /* Last round is special: there is no MixColumn -+ */ -+ Substitution(a,S); -+ ShiftRow128Enc(a); -+ KeyAddition(a,rk[ROUNDS],BC); -+ -+ return 0; -+} -+ -+ -+int rijndaelDecrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds) -+{ -+ int r, BC, ROUNDS; -+ -+ BC = 4; -+ ROUNDS = rounds; -+ -+ /* To decrypt: apply the inverse operations of the encrypt routine, -+ * in opposite order -+ * -+ * (KeyAddition is an involution: it 's equal to its inverse) -+ * (the inverse of Substitution with table S is Substitution with the inverse table of S) -+ * (the inverse of Shiftrow is Shiftrow over a suitable distance) -+ */ -+ -+ /* First the special round: -+ * without InvMixColumn -+ * with extra KeyAddition -+ */ -+ KeyAddition(a,rk[ROUNDS],BC); -+ ShiftRow128Dec(a); -+ Substitution(a,Si); -+ -+ /* ROUNDS-1 ordinary rounds -+ */ -+ for(r = ROUNDS-1; r > 0; r--) { -+ KeyAddition(a,rk[r],BC); -+ InvMixColumn(a); -+ ShiftRow128Dec(a); -+ Substitution(a,Si); -+ -+ } -+ -+ /* End with the extra key addition -+ */ -+ -+ KeyAddition(a,rk[0],BC); -+ -+ return 0; -+} -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.h linux-2.6.36/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.h 2010-11-09 20:28:05.222495460 +0100 -@@ -0,0 +1,19 @@ -+/* rijndael-alg-ref.h v2.0 August '99 -+ * Reference ANSI C code -+ * authors: Paulo Barreto -+ * Vincent Rijmen, K.U.Leuven -+ */ -+#ifndef __RIJNDAEL_ALG_H -+#define __RIJNDAEL_ALG_H -+ -+#define MAXBC (128/32) -+#define MAXKC (256/32) -+#define MAXROUNDS 14 -+ -+ -+int rijndaelKeySched (MV_U8 k[4][MAXKC], int keyBits, int blockBits, MV_U8 rk[MAXROUNDS+1][4][MAXBC]); -+ -+int rijndaelEncrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds); -+int rijndaelDecrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds); -+ -+#endif /* __RIJNDAEL_ALG_H */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/cesa/AES/mvAesApi.c linux-2.6.36/crypto/ocf/kirkwood/cesa/AES/mvAesApi.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/cesa/AES/mvAesApi.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/cesa/AES/mvAesApi.c 2010-11-09 20:28:05.264499847 +0100 -@@ -0,0 +1,312 @@ -+/* rijndael-api-ref.c v2.1 April 2000 -+ * Reference ANSI C code -+ * authors: v2.0 Paulo Barreto -+ * Vincent Rijmen, K.U.Leuven -+ * v2.1 Vincent Rijmen, K.U.Leuven -+ * -+ * This code is placed in the public domain. -+ */ -+#include "mvOs.h" -+ -+#include "mvAes.h" -+#include "mvAesAlg.h" -+ -+ -+/* Defines: -+ Add any additional defines you need -+*/ -+ -+#define MODE_ECB 1 /* Are we ciphering in ECB mode? */ -+#define MODE_CBC 2 /* Are we ciphering in CBC mode? */ -+#define MODE_CFB1 3 /* Are we ciphering in 1-bit CFB mode? */ -+ -+ -+int aesMakeKey(MV_U8 *expandedKey, MV_U8 *keyMaterial, int keyLen, int blockLen) -+{ -+ MV_U8 W[MAXROUNDS+1][4][MAXBC]; -+ MV_U8 k[4][MAXKC]; -+ MV_U8 j; -+ int i, rounds, KC; -+ -+ if (expandedKey == NULL) -+ { -+ return AES_BAD_KEY_INSTANCE; -+ } -+ -+ if (!((keyLen == 128) || (keyLen == 192) || (keyLen == 256))) -+ { -+ return AES_BAD_KEY_MAT; -+ } -+ -+ if (keyMaterial == NULL) -+ { -+ return AES_BAD_KEY_MAT; -+ } -+ -+ /* initialize key schedule: */ -+ for(i=0; i= 3) -+MV_U32 cesaChainLength = 0; -+int chainReqNum = 0; -+MV_U32 chainIndex = 0; -+MV_CESA_REQ* pNextActiveChain = 0; -+MV_CESA_REQ* pEndCurrChain = 0; -+MV_BOOL isFirstReq = MV_TRUE; -+#endif -+ -+static INLINE MV_U8* mvCesaSramAddrGet(void) -+{ -+#ifdef MV_CESA_NO_SRAM -+ return (MV_U8*)cesaSramVirtPtr; -+#else -+ return (MV_U8*)cesaCryptEngBase; -+#endif /* MV_CESA_NO_SRAM */ -+} -+ -+static INLINE MV_ULONG mvCesaSramVirtToPhys(void* pDev, MV_U8* pSramVirt) -+{ -+#ifdef MV_CESA_NO_SRAM -+ return (MV_ULONG)mvOsIoVirtToPhy(NULL, pSramVirt); -+#else -+ return (MV_ULONG)pSramVirt; -+#endif /* MV_CESA_NO_SRAM */ -+} -+ -+/* Internal Function prototypes */ -+ -+static INLINE void mvCesaSramDescrBuild(MV_U32 config, int frag, -+ int cryptoOffset, int ivOffset, int cryptoLength, -+ int macOffset, int digestOffset, int macLength, int macTotalLen, -+ MV_CESA_REQ *pCesaReq, MV_DMA_DESC* pDmaDesc); -+ -+static INLINE void mvCesaSramSaUpdate(short sid, MV_DMA_DESC *pDmaDesc); -+ -+static INLINE int mvCesaDmaCopyPrepare(MV_CESA_MBUF* pMbuf, MV_U8* pSramBuf, -+ MV_DMA_DESC* pDmaDesc, MV_BOOL isToMbuf, -+ int offset, int copySize, MV_BOOL skipFlush); -+ -+static void mvCesaHmacIvGet(MV_CESA_MAC_MODE macMode, unsigned char key[], int keyLength, -+ unsigned char innerIV[], unsigned char outerIV[]); -+ -+static MV_STATUS mvCesaFragAuthComplete(MV_CESA_REQ* pReq, MV_CESA_SA* pSA, -+ int macDataSize); -+ -+static MV_CESA_COMMAND* mvCesaCtrModeInit(void); -+ -+static MV_STATUS mvCesaCtrModePrepare(MV_CESA_COMMAND *pCtrModeCmd, MV_CESA_COMMAND *pCmd); -+static MV_STATUS mvCesaCtrModeComplete(MV_CESA_COMMAND *pOrgCmd, MV_CESA_COMMAND *pCmd); -+static void mvCesaCtrModeFinish(MV_CESA_COMMAND *pCmd); -+ -+static INLINE MV_STATUS mvCesaReqProcess(MV_CESA_REQ* pReq); -+static MV_STATUS mvCesaFragReqProcess(MV_CESA_REQ* pReq, MV_U8 frag); -+ -+static INLINE MV_STATUS mvCesaParamCheck(MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, MV_U8* pFixOffset); -+static INLINE MV_STATUS mvCesaFragParamCheck(MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd); -+ -+static INLINE void mvCesaFragSizeFind(MV_CESA_SA* pSA, MV_CESA_REQ* pReq, -+ int cryptoOffset, int macOffset, -+ int* pCopySize, int* pCryptoDataSize, int* pMacDataSize); -+static MV_STATUS mvCesaMbufCacheUnmap(MV_CESA_MBUF* pMbuf, int offset, int size); -+ -+ -+/* Go to the next request in the request queue */ -+static INLINE MV_CESA_REQ* MV_CESA_REQ_NEXT_PTR(MV_CESA_REQ* pReq) -+{ -+ if(pReq == pCesaReqLast) -+ return pCesaReqFirst; -+ -+ return pReq+1; -+} -+ -+#if (MV_CESA_VERSION >= 3) -+/* Go to the previous request in the request queue */ -+static INLINE MV_CESA_REQ* MV_CESA_REQ_PREV_PTR(MV_CESA_REQ* pReq) -+{ -+ if(pReq == pCesaReqFirst) -+ return pCesaReqLast; -+ -+ return pReq-1; -+} -+ -+#endif -+ -+ -+static INLINE void mvCesaReqProcessStart(MV_CESA_REQ* pReq) -+{ -+ int frag; -+ -+#if (MV_CESA_VERSION >= 3) -+ pReq->state = MV_CESA_CHAIN; -+#else -+ pReq->state = MV_CESA_PROCESS; -+#endif -+ cesaStats.startCount++; -+ -+ if(pReq->fragMode == MV_CESA_FRAG_NONE) -+ { -+ frag = 0; -+ } -+ else -+ { -+ frag = pReq->frags.nextFrag; -+ pReq->frags.nextFrag++; -+ } -+#if (MV_CESA_VERSION >= 2) -+ /* Enable TDMA engine */ -+ MV_REG_WRITE(MV_CESA_TDMA_CURR_DESC_PTR_REG, 0); -+ MV_REG_WRITE(MV_CESA_TDMA_NEXT_DESC_PTR_REG, -+ (MV_U32)mvCesaVirtToPhys(&pReq->dmaDescBuf, pReq->dma[frag].pDmaFirst)); -+#else -+ /* Enable IDMA engine */ -+ MV_REG_WRITE(IDMA_CURR_DESC_PTR_REG(0), 0); -+ MV_REG_WRITE(IDMA_NEXT_DESC_PTR_REG(0), -+ (MV_U32)mvCesaVirtToPhys(&pReq->dmaDescBuf, pReq->dma[frag].pDmaFirst)); -+#endif /* MV_CESA_VERSION >= 2 */ -+ -+#if defined(MV_BRIDGE_SYNC_REORDER) -+ mvOsBridgeReorderWA(); -+#endif -+ -+ /* Start Accelerator */ -+ MV_REG_WRITE(MV_CESA_CMD_REG, MV_CESA_CMD_CHAN_ENABLE_MASK); -+} -+ -+ -+/******************************************************************************* -+* mvCesaHalInit - Initialize the CESA driver -+* -+* DESCRIPTION: -+* This function initialize the CESA driver. -+* 1) Session database -+* 2) Request queue -+* 4) DMA descriptor lists - one list per request. Each list -+* has MV_CESA_MAX_DMA_DESC descriptors. -+* -+* INPUT: -+* numOfSession - maximum number of supported sessions -+* queueDepth - number of elements in the request queue. -+* pSramBase - virtual address of Sram -+* osHandle - A handle used by the OS to allocate memory for the -+* module (Passed to the OS Services layer) -+* -+* RETURN: -+* MV_OK - Success -+* MV_NO_RESOURCE - Fail, can't allocate resources: -+* Session database, request queue, -+* DMA descriptors list, LRU cache database. -+* MV_NOT_ALIGNED - Sram base address is not 8 byte aligned. -+* -+*******************************************************************************/ -+MV_STATUS mvCesaHalInit (int numOfSession, int queueDepth, char* pSramBase, MV_U32 cryptEngBase, -+ void *osHandle) -+{ -+ int i, req; -+ MV_U32 descOffsetReg, configReg; -+ MV_CESA_SRAM_SA *pSramSA; -+ -+ -+ mvOsPrintf("mvCesaInit: sessions=%d, queue=%d, pSram=%p\n", -+ numOfSession, queueDepth, pSramBase); -+ -+ cesaOsHandle = osHandle; -+ /* Create Session database */ -+ pCesaSAD = mvOsMalloc(sizeof(MV_CESA_SA)*numOfSession); -+ if(pCesaSAD == NULL) -+ { -+ mvOsPrintf("mvCesaInit: Can't allocate %u bytes for %d SAs\n", -+ sizeof(MV_CESA_SA)*numOfSession, numOfSession); -+ mvCesaFinish(); -+ return MV_NO_RESOURCE; -+ } -+ memset(pCesaSAD, 0, sizeof(MV_CESA_SA)*numOfSession); -+ cesaMaxSA = numOfSession; -+ -+ /* Allocate imag of sramSA in the DRAM */ -+ cesaSramSaBuf.bufSize = sizeof(MV_CESA_SRAM_SA)*numOfSession + -+ CPU_D_CACHE_LINE_SIZE; -+ -+ cesaSramSaBuf.bufVirtPtr = mvOsIoCachedMalloc(osHandle,cesaSramSaBuf.bufSize, -+ &cesaSramSaBuf.bufPhysAddr, -+ &cesaSramSaBuf.memHandle); -+ -+ if(cesaSramSaBuf.bufVirtPtr == NULL) -+ { -+ mvOsPrintf("mvCesaInit: Can't allocate %d bytes for sramSA structures\n", -+ cesaSramSaBuf.bufSize); -+ mvCesaFinish(); -+ return MV_NO_RESOURCE; -+ } -+ memset(cesaSramSaBuf.bufVirtPtr, 0, cesaSramSaBuf.bufSize); -+ pSramSA = (MV_CESA_SRAM_SA*)MV_ALIGN_UP((MV_ULONG)cesaSramSaBuf.bufVirtPtr, -+ CPU_D_CACHE_LINE_SIZE); -+ for(i=0; i= 3) -+ cesaChainLength = MAX_CESA_CHAIN_LENGTH; -+#endif -+ /* pSramBase must be 8 byte aligned */ -+ if( MV_IS_NOT_ALIGN((MV_ULONG)pSramBase, 8) ) -+ { -+ mvOsPrintf("mvCesaInit: pSramBase (%p) must be 8 byte aligned\n", -+ pSramBase); -+ mvCesaFinish(); -+ return MV_NOT_ALIGNED; -+ } -+ cesaSramVirtPtr = (MV_CESA_SRAM_MAP*)pSramBase; -+ -+ cesaCryptEngBase = cryptEngBase; -+ -+ /*memset(cesaSramVirtPtr, 0, sizeof(MV_CESA_SRAM_MAP));*/ -+ -+ /* Clear registers */ -+ MV_REG_WRITE( MV_CESA_CFG_REG, 0); -+ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); -+ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, 0); -+ -+ /* Initialize DMA descriptor lists for all requests in Request queue */ -+ descOffsetReg = configReg = 0; -+ for(req=0; reqcesaDescBuf.bufSize = sizeof(MV_CESA_DESC)*MV_CESA_MAX_REQ_FRAGS + -+ CPU_D_CACHE_LINE_SIZE; -+ -+ pReq->cesaDescBuf.bufVirtPtr = -+ mvOsIoCachedMalloc(osHandle,pReq->cesaDescBuf.bufSize, -+ &pReq->cesaDescBuf.bufPhysAddr, -+ &pReq->cesaDescBuf.memHandle); -+ -+ if(pReq->cesaDescBuf.bufVirtPtr == NULL) -+ { -+ mvOsPrintf("mvCesaInit: req=%d, Can't allocate %d bytes for CESA descriptors\n", -+ req, pReq->cesaDescBuf.bufSize); -+ mvCesaFinish(); -+ return MV_NO_RESOURCE; -+ } -+ memset(pReq->cesaDescBuf.bufVirtPtr, 0, pReq->cesaDescBuf.bufSize); -+ pReq->pCesaDesc = (MV_CESA_DESC*)MV_ALIGN_UP((MV_ULONG)pReq->cesaDescBuf.bufVirtPtr, -+ CPU_D_CACHE_LINE_SIZE); -+ -+ pReq->dmaDescBuf.bufSize = sizeof(MV_DMA_DESC)*MV_CESA_MAX_DMA_DESC*MV_CESA_MAX_REQ_FRAGS + -+ CPU_D_CACHE_LINE_SIZE; -+ -+ pReq->dmaDescBuf.bufVirtPtr = -+ mvOsIoCachedMalloc(osHandle,pReq->dmaDescBuf.bufSize, -+ &pReq->dmaDescBuf.bufPhysAddr, -+ &pReq->dmaDescBuf.memHandle); -+ -+ if(pReq->dmaDescBuf.bufVirtPtr == NULL) -+ { -+ mvOsPrintf("mvCesaInit: req=%d, Can't allocate %d bytes for DMA descriptor list\n", -+ req, pReq->dmaDescBuf.bufSize); -+ mvCesaFinish(); -+ return MV_NO_RESOURCE; -+ } -+ memset(pReq->dmaDescBuf.bufVirtPtr, 0, pReq->dmaDescBuf.bufSize); -+ pDmaDesc = (MV_DMA_DESC*)MV_ALIGN_UP((MV_ULONG)pReq->dmaDescBuf.bufVirtPtr, -+ CPU_D_CACHE_LINE_SIZE); -+ -+ for(frag=0; fragdma[frag]; -+ -+ pDma->pDmaFirst = pDmaDesc; -+ pDma->pDmaLast = NULL; -+ -+ for(i=0; ipDmaFirst[i].phyNextDescPtr = -+ MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, &pDmaDesc[i+1])); -+ } -+ pDma->pDmaFirst[i].phyNextDescPtr = 0; -+ mvOsCacheFlush(NULL, &pDma->pDmaFirst[0], MV_CESA_MAX_DMA_DESC*sizeof(MV_DMA_DESC)); -+ -+ pDmaDesc += MV_CESA_MAX_DMA_DESC; -+ } -+ } -+ /*mvCesaCryptoIvSet(NULL, MV_CESA_MAX_IV_LENGTH);*/ -+ descOffsetReg = (MV_U16)((MV_U8*)&cesaSramVirtPtr->desc - mvCesaSramAddrGet()); -+ MV_REG_WRITE(MV_CESA_CHAN_DESC_OFFSET_REG, descOffsetReg); -+ -+ configReg |= (MV_CESA_CFG_WAIT_DMA_MASK | MV_CESA_CFG_ACT_DMA_MASK); -+#if (MV_CESA_VERSION >= 3) -+ configReg |= MV_CESA_CFG_CHAIN_MODE_MASK; -+#endif -+ -+#if (MV_CESA_VERSION >= 2) -+ /* Initialize TDMA engine */ -+ MV_REG_WRITE(MV_CESA_TDMA_CTRL_REG, MV_CESA_TDMA_CTRL_VALUE); -+ MV_REG_WRITE(MV_CESA_TDMA_BYTE_COUNT_REG, 0); -+ MV_REG_WRITE(MV_CESA_TDMA_CURR_DESC_PTR_REG, 0); -+#else -+ /* Initialize IDMA #0 engine */ -+ MV_REG_WRITE(IDMA_CTRL_LOW_REG(0), 0); -+ MV_REG_WRITE(IDMA_BYTE_COUNT_REG(0), 0); -+ MV_REG_WRITE(IDMA_CURR_DESC_PTR_REG(0), 0); -+ MV_REG_WRITE(IDMA_CTRL_HIGH_REG(0), ICCHR_ENDIAN_LITTLE -+#ifdef MV_CPU_LE -+ | ICCHR_DESC_BYTE_SWAP_EN -+#endif -+ ); -+ /* Clear Cause Byte of IDMA channel to be used */ -+ MV_REG_WRITE( IDMA_CAUSE_REG, ~ICICR_CAUSE_MASK_ALL(0)); -+ MV_REG_WRITE(IDMA_CTRL_LOW_REG(0), MV_CESA_IDMA_CTRL_LOW_VALUE); -+#endif /* (MV_CESA_VERSION >= 2) */ -+ -+ /* Set CESA configuration registers */ -+ MV_REG_WRITE( MV_CESA_CFG_REG, configReg); -+ mvCesaDebugStatsClear(); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaFinish - Shutdown the CESA driver -+* -+* DESCRIPTION: -+* This function shutdown the CESA driver and free all allocted resources. -+* -+* INPUT: None -+* -+* RETURN: -+* MV_OK - Success -+* Other - Fail -+* -+*******************************************************************************/ -+MV_STATUS mvCesaFinish (void) -+{ -+ int req; -+ MV_CESA_REQ* pReq; -+ -+ mvOsPrintf("mvCesaFinish: \n"); -+ -+ cesaSramVirtPtr = NULL; -+ -+ /* Free all resources: DMA list, etc. */ -+ for(req=0; reqdmaDescBuf.bufVirtPtr != NULL) -+ { -+ mvOsIoCachedFree(cesaOsHandle,pReq->dmaDescBuf.bufSize, -+ pReq->dmaDescBuf.bufPhysAddr, -+ pReq->dmaDescBuf.bufVirtPtr, -+ pReq->dmaDescBuf.memHandle); -+ } -+ if(pReq->cesaDescBuf.bufVirtPtr != NULL) -+ { -+ mvOsIoCachedFree(cesaOsHandle,pReq->cesaDescBuf.bufSize, -+ pReq->cesaDescBuf.bufPhysAddr, -+ pReq->cesaDescBuf.bufVirtPtr, -+ pReq->cesaDescBuf.memHandle); -+ } -+ } -+#if (MV_CESA_VERSION < 2) -+ MV_REG_WRITE(IDMA_CTRL_LOW_REG(0), 0); -+#endif /* (MV_CESA_VERSION < 2) */ -+ -+ /* Free request queue */ -+ if(pCesaReqFirst != NULL) -+ { -+ mvOsFree(pCesaReqFirst); -+ pCesaReqFirst = pCesaReqLast = NULL; -+ pCesaReqEmpty = pCesaReqProcess = NULL; -+ cesaQueueDepth = cesaReqResources = 0; -+ } -+ /* Free SA database */ -+ if(pCesaSAD != NULL) -+ { -+ mvOsFree(pCesaSAD); -+ pCesaSAD = NULL; -+ cesaMaxSA = 0; -+ } -+ MV_REG_WRITE( MV_CESA_CFG_REG, 0); -+ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); -+ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, 0); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaCryptoIvSet - Set IV value for Crypto algorithm working in CBC mode -+* -+* DESCRIPTION: -+* This function set IV value using by Crypto algorithms in CBC mode. -+* Each channel has its own IV value. -+* This function gets IV value from the caller. If no IV value passed from -+* the caller or only part of IV passed, the function will init the rest part -+* of IV value (or the whole IV) by random value. -+* -+* INPUT: -+* MV_U8* pIV - Pointer to IV value supplied by user. If pIV==NULL -+* the function will generate random IV value. -+* int ivSize - size (in bytes) of IV provided by user. If ivSize is -+* smaller than maximum IV size, the function will complete -+* IV by random value. -+* -+* RETURN: -+* MV_OK - Success -+* Other - Fail -+* -+*******************************************************************************/ -+MV_STATUS mvCesaCryptoIvSet(MV_U8* pIV, int ivSize) -+{ -+ MV_U8* pSramIV; -+#if defined(MV646xx) -+ mvOsPrintf("mvCesaCryptoIvSet: ERR. shouldn't use this call on MV64660\n"); -+#endif -+ pSramIV = cesaSramVirtPtr->cryptoIV; -+ if(ivSize > MV_CESA_MAX_IV_LENGTH) -+ { -+ mvOsPrintf("mvCesaCryptoIvSet: ivSize (%d) is too large\n", ivSize); -+ ivSize = MV_CESA_MAX_IV_LENGTH; -+ } -+ if(pIV != NULL) -+ { -+ memcpy(pSramIV, pIV, ivSize); -+ ivSize = MV_CESA_MAX_IV_LENGTH - ivSize; -+ pSramIV += ivSize; -+ } -+ -+ while(ivSize > 0) -+ { -+ int size, mv_random = mvOsRand(); -+ -+ size = MV_MIN(ivSize, sizeof(mv_random)); -+ memcpy(pSramIV, (void*)&mv_random, size); -+ -+ pSramIV += size; -+ ivSize -= size; -+ } -+/* -+ mvOsCacheFlush(NULL, cesaSramVirtPtr->cryptoIV, -+ MV_CESA_MAX_IV_LENGTH); -+ mvOsCacheInvalidate(NULL, cesaSramVirtPtr->cryptoIV, -+ MV_CESA_MAX_IV_LENGTH); -+*/ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaSessionOpen - Open new uni-directional crypto session -+* -+* DESCRIPTION: -+* This function open new session. -+* -+* INPUT: -+* MV_CESA_OPEN_SESSION *pSession - pointer to new session input parameters -+* -+* OUTPUT: -+* short *pSid - session ID, should be used for all future -+* requests over this session. -+* -+* RETURN: -+* MV_OK - Session opend successfully. -+* MV_FULL - All sessions are in use, no free place in -+* SA database. -+* MV_BAD_PARAM - One of session input parameters is invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvCesaSessionOpen(MV_CESA_OPEN_SESSION *pSession, short* pSid) -+{ -+ short sid; -+ MV_U32 config = 0; -+ int digestSize; -+ -+ cesaStats.openedCount++; -+ -+ /* Find free entry in SAD */ -+ for(sid=0; sidoperation >= MV_CESA_MAX_OPERATION) -+ { -+ mvOsPrintf("mvCesaSessionOpen: Unexpected operation %d\n", -+ pSession->operation); -+ return MV_BAD_PARAM; -+ } -+ config |= (pSession->operation << MV_CESA_OPERATION_OFFSET); -+ -+ if( (pSession->direction != MV_CESA_DIR_ENCODE) && -+ (pSession->direction != MV_CESA_DIR_DECODE) ) -+ { -+ mvOsPrintf("mvCesaSessionOpen: Unexpected direction %d\n", -+ pSession->direction); -+ return MV_BAD_PARAM; -+ } -+ config |= (pSession->direction << MV_CESA_DIRECTION_BIT); -+ /* Clear SA entry */ -+ /* memset(&pCesaSAD[sid], 0, sizeof(pCesaSAD[sid])); */ -+ -+ /* Check AUTH parameters and update SA entry */ -+ if(pSession->operation != MV_CESA_CRYPTO_ONLY) -+ { -+ /* For HMAC (MD5 and SHA1) - Maximum Key size is 64 bytes */ -+ if( (pSession->macMode == MV_CESA_MAC_HMAC_MD5) || -+ (pSession->macMode == MV_CESA_MAC_HMAC_SHA1) ) -+ { -+ if(pSession->macKeyLength > MV_CESA_MAX_MAC_KEY_LENGTH) -+ { -+ mvOsPrintf("mvCesaSessionOpen: macKeyLength %d is too large\n", -+ pSession->macKeyLength); -+ return MV_BAD_PARAM; -+ } -+ mvCesaHmacIvGet(pSession->macMode, pSession->macKey, pSession->macKeyLength, -+ pCesaSAD[sid].pSramSA->macInnerIV, -+ pCesaSAD[sid].pSramSA->macOuterIV); -+ pCesaSAD[sid].macKeyLength = pSession->macKeyLength; -+ } -+ switch(pSession->macMode) -+ { -+ case MV_CESA_MAC_MD5: -+ case MV_CESA_MAC_HMAC_MD5: -+ digestSize = MV_CESA_MD5_DIGEST_SIZE; -+ break; -+ -+ case MV_CESA_MAC_SHA1: -+ case MV_CESA_MAC_HMAC_SHA1: -+ digestSize = MV_CESA_SHA1_DIGEST_SIZE; -+ break; -+ -+ default: -+ mvOsPrintf("mvCesaSessionOpen: Unexpected macMode %d\n", -+ pSession->macMode); -+ return MV_BAD_PARAM; -+ } -+ config |= (pSession->macMode << MV_CESA_MAC_MODE_OFFSET); -+ -+ /* Supported digest sizes: MD5 - 16 bytes (128 bits), */ -+ /* SHA1 - 20 bytes (160 bits) or 12 bytes (96 bits) for both */ -+ if( (pSession->digestSize != digestSize) && (pSession->digestSize != 12)) -+ { -+ mvOsPrintf("mvCesaSessionOpen: Unexpected digest size %d\n", -+ pSession->digestSize); -+ mvOsPrintf("\t Valid values [bytes]: MD5-16, SHA1-20, Both-12\n"); -+ return MV_BAD_PARAM; -+ } -+ pCesaSAD[sid].digestSize = pSession->digestSize; -+ -+ if(pCesaSAD[sid].digestSize == 12) -+ { -+ /* Set MV_CESA_MAC_DIGEST_SIZE_BIT if digest size is 96 bits */ -+ config |= (MV_CESA_MAC_DIGEST_96B << MV_CESA_MAC_DIGEST_SIZE_BIT); -+ } -+ } -+ -+ /* Check CRYPTO parameters and update SA entry */ -+ if(pSession->operation != MV_CESA_MAC_ONLY) -+ { -+ switch(pSession->cryptoAlgorithm) -+ { -+ case MV_CESA_CRYPTO_DES: -+ pCesaSAD[sid].cryptoKeyLength = MV_CESA_DES_KEY_LENGTH; -+ pCesaSAD[sid].cryptoBlockSize = MV_CESA_DES_BLOCK_SIZE; -+ break; -+ -+ case MV_CESA_CRYPTO_3DES: -+ pCesaSAD[sid].cryptoKeyLength = MV_CESA_3DES_KEY_LENGTH; -+ pCesaSAD[sid].cryptoBlockSize = MV_CESA_DES_BLOCK_SIZE; -+ /* Only EDE mode is supported */ -+ config |= (MV_CESA_CRYPTO_3DES_EDE << -+ MV_CESA_CRYPTO_3DES_MODE_BIT); -+ break; -+ -+ case MV_CESA_CRYPTO_AES: -+ switch(pSession->cryptoKeyLength) -+ { -+ case 16: -+ pCesaSAD[sid].cryptoKeyLength = MV_CESA_AES_128_KEY_LENGTH; -+ config |= (MV_CESA_CRYPTO_AES_KEY_128 << -+ MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET); -+ break; -+ -+ case 24: -+ pCesaSAD[sid].cryptoKeyLength = MV_CESA_AES_192_KEY_LENGTH; -+ config |= (MV_CESA_CRYPTO_AES_KEY_192 << -+ MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET); -+ break; -+ -+ case 32: -+ default: -+ pCesaSAD[sid].cryptoKeyLength = MV_CESA_AES_256_KEY_LENGTH; -+ config |= (MV_CESA_CRYPTO_AES_KEY_256 << -+ MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET); -+ break; -+ } -+ pCesaSAD[sid].cryptoBlockSize = MV_CESA_AES_BLOCK_SIZE; -+ break; -+ -+ default: -+ mvOsPrintf("mvCesaSessionOpen: Unexpected cryptoAlgorithm %d\n", -+ pSession->cryptoAlgorithm); -+ return MV_BAD_PARAM; -+ } -+ config |= (pSession->cryptoAlgorithm << MV_CESA_CRYPTO_ALG_OFFSET); -+ -+ if(pSession->cryptoKeyLength != pCesaSAD[sid].cryptoKeyLength) -+ { -+ mvOsPrintf("cesaSessionOpen: Wrong CryptoKeySize %d != %d\n", -+ pSession->cryptoKeyLength, pCesaSAD[sid].cryptoKeyLength); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Copy Crypto key */ -+ if( (pSession->cryptoAlgorithm == MV_CESA_CRYPTO_AES) && -+ (pSession->direction == MV_CESA_DIR_DECODE)) -+ { -+ /* Crypto Key for AES decode is computed from original key material */ -+ /* and depend on cryptoKeyLength (128/192/256 bits) */ -+ aesMakeKey(pCesaSAD[sid].pSramSA->cryptoKey, pSession->cryptoKey, -+ pSession->cryptoKeyLength*8, MV_CESA_AES_BLOCK_SIZE*8); -+ } -+ else -+ { -+ /*panic("mvCesaSessionOpen2");*/ -+ memcpy(pCesaSAD[sid].pSramSA->cryptoKey, pSession->cryptoKey, -+ pCesaSAD[sid].cryptoKeyLength); -+ -+ } -+ -+ switch(pSession->cryptoMode) -+ { -+ case MV_CESA_CRYPTO_ECB: -+ pCesaSAD[sid].cryptoIvSize = 0; -+ break; -+ -+ case MV_CESA_CRYPTO_CBC: -+ pCesaSAD[sid].cryptoIvSize = pCesaSAD[sid].cryptoBlockSize; -+ break; -+ -+ case MV_CESA_CRYPTO_CTR: -+ /* Supported only for AES algorithm */ -+ if(pSession->cryptoAlgorithm != MV_CESA_CRYPTO_AES) -+ { -+ mvOsPrintf("mvCesaSessionOpen: CRYPTO CTR mode supported for AES only\n"); -+ return MV_BAD_PARAM; -+ } -+ pCesaSAD[sid].cryptoIvSize = 0; -+ pCesaSAD[sid].ctrMode = 1; -+ /* Replace to ECB mode for HW */ -+ pSession->cryptoMode = MV_CESA_CRYPTO_ECB; -+ break; -+ -+ default: -+ mvOsPrintf("mvCesaSessionOpen: Unexpected cryptoMode %d\n", -+ pSession->cryptoMode); -+ return MV_BAD_PARAM; -+ } -+ -+ config |= (pSession->cryptoMode << MV_CESA_CRYPTO_MODE_BIT); -+ } -+ pCesaSAD[sid].config = config; -+ -+ mvOsCacheFlush(NULL, pCesaSAD[sid].pSramSA, sizeof(MV_CESA_SRAM_SA)); -+ if(pSid != NULL) -+ *pSid = sid; -+ -+ pCesaSAD[sid].valid = 1; -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaSessionClose - Close active crypto session -+* -+* DESCRIPTION: -+* This function closes existing session -+* -+* INPUT: -+* short sid - Unique identifier of the session to be closed -+* -+* RETURN: -+* MV_OK - Session closed successfully. -+* MV_BAD_PARAM - Session identifier is out of valid range. -+* MV_NOT_FOUND - There is no active session with such ID. -+* -+*******************************************************************************/ -+MV_STATUS mvCesaSessionClose(short sid) -+{ -+ cesaStats.closedCount++; -+ -+ if(sid >= cesaMaxSA) -+ { -+ mvOsPrintf("CESA Error: sid (%d) is too big\n", sid); -+ return MV_BAD_PARAM; -+ } -+ if(pCesaSAD[sid].valid == 0) -+ { -+ mvOsPrintf("CESA Warning: Session (sid=%d) is invalid\n", sid); -+ return MV_NOT_FOUND; -+ } -+ if(cesaLastSid == sid) -+ cesaLastSid = -1; -+ -+ pCesaSAD[sid].valid = 0; -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaAction - Perform crypto operation -+* -+* DESCRIPTION: -+* This function set new CESA request FIFO queue for further HW processing. -+* The function checks request parameters before set new request to the queue. -+* If one of the CESA channels is ready for processing the request will be -+* passed to HW. When request processing is finished the CESA interrupt will -+* be generated by HW. The caller should call mvCesaReadyGet() function to -+* complete request processing and get result. -+* -+* INPUT: -+* MV_CESA_COMMAND *pCmd - pointer to new CESA request. -+* It includes pointers to Source and Destination -+* buffers, session identifier get from -+* mvCesaSessionOpen() function, pointer to caller -+* private data and all needed crypto parameters. -+* -+* RETURN: -+* MV_OK - request successfully added to request queue -+* and will be processed. -+* MV_NO_MORE - request successfully added to request queue and will -+* be processed, but request queue became Full and next -+* request will not be accepted. -+* MV_NO_RESOURCE - request queue is FULL and the request can not -+* be processed. -+* MV_OUT_OF_CPU_MEM - memory allocation needed for request processing is -+* failed. Request can not be processed. -+* MV_NOT_ALLOWED - This mixed request (CRYPTO+MAC) can not be processed -+* as one request and should be splitted for two requests: -+* CRYPTO_ONLY and MAC_ONLY. -+* MV_BAD_PARAM - One of the request parameters is out of valid range. -+* The request can not be processed. -+* -+*******************************************************************************/ -+MV_STATUS mvCesaAction (MV_CESA_COMMAND *pCmd) -+{ -+ MV_STATUS status; -+ MV_CESA_REQ* pReq = pCesaReqEmpty; -+ int sid = pCmd->sessionId; -+ MV_CESA_SA* pSA = &pCesaSAD[sid]; -+#if (MV_CESA_VERSION >= 3) -+ MV_CESA_REQ* pFromReq; -+ MV_CESA_REQ* pToReq; -+#endif -+ cesaStats.reqCount++; -+ -+ /* Check that the request queue is not FULL */ -+ if(cesaReqResources == 0) -+ return MV_NO_RESOURCE; -+ -+ if( (sid >= cesaMaxSA) || (!pSA->valid) ) -+ { -+ mvOsPrintf("CESA Action Error: Session sid=%d is INVALID\n", sid); -+ return MV_BAD_PARAM; -+ } -+ pSA->count++; -+ -+ if(pSA->ctrMode) -+ { -+ /* AES in CTR mode can't be mixed with Authentication */ -+ if( (pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ mvOsPrintf("mvCesaAction : CRYPTO CTR mode can't be mixed with AUTH\n"); -+ return MV_NOT_ALLOWED; -+ } -+ /* All other request parameters should not be checked because key stream */ -+ /* (not user data) processed by AES HW engine */ -+ pReq->pOrgCmd = pCmd; -+ /* Allocate temporary pCmd structure for Key stream */ -+ pCmd = mvCesaCtrModeInit(); -+ if(pCmd == NULL) -+ return MV_OUT_OF_CPU_MEM; -+ -+ /* Prepare Key stream */ -+ mvCesaCtrModePrepare(pCmd, pReq->pOrgCmd); -+ pReq->fixOffset = 0; -+ } -+ else -+ { -+ /* Check request parameters and calculae fixOffset */ -+ status = mvCesaParamCheck(pSA, pCmd, &pReq->fixOffset); -+ if(status != MV_OK) -+ { -+ return status; -+ } -+ } -+ pReq->pCmd = pCmd; -+ -+ /* Check if the packet need fragmentation */ -+ if(pCmd->pSrc->mbufSize <= sizeof(cesaSramVirtPtr->buf) ) -+ { -+ /* request size is smaller than single buffer size */ -+ pReq->fragMode = MV_CESA_FRAG_NONE; -+ -+ /* Prepare NOT fragmented packets */ -+ status = mvCesaReqProcess(pReq); -+ if(status != MV_OK) -+ { -+ mvOsPrintf("CesaReady: ReqProcess error: pReq=%p, status=0x%x\n", -+ pReq, status); -+ } -+#if (MV_CESA_VERSION >= 3) -+ pReq->frags.numFrag = 1; -+#endif -+ } -+ else -+ { -+ MV_U8 frag = 0; -+ -+ /* request size is larger than buffer size - needs fragmentation */ -+ -+ /* Check restrictions for processing fragmented packets */ -+ status = mvCesaFragParamCheck(pSA, pCmd); -+ if(status != MV_OK) -+ return status; -+ -+ pReq->fragMode = MV_CESA_FRAG_FIRST; -+ pReq->frags.nextFrag = 0; -+ -+ /* Prepare Process Fragmented packets */ -+ while(pReq->fragMode != MV_CESA_FRAG_LAST) -+ { -+ if(frag >= MV_CESA_MAX_REQ_FRAGS) -+ { -+ mvOsPrintf("mvCesaAction Error: Too large request frag=%d\n", frag); -+ return MV_OUT_OF_CPU_MEM; -+ } -+ status = mvCesaFragReqProcess(pReq, frag); -+ if(status == MV_OK) { -+#if (MV_CESA_VERSION >= 3) -+ if(frag) { -+ pReq->dma[frag-1].pDmaLast->phyNextDescPtr = -+ MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, pReq->dma[frag].pDmaFirst)); -+ mvOsCacheFlush(NULL, pReq->dma[frag-1].pDmaLast, sizeof(MV_DMA_DESC)); -+ } -+#endif -+ frag++; -+ } -+ } -+ pReq->frags.numFrag = frag; -+#if (MV_CESA_VERSION >= 3) -+ if(chainReqNum) { -+ chainReqNum += pReq->frags.numFrag; -+ if(chainReqNum >= MAX_CESA_CHAIN_LENGTH) -+ chainReqNum = MAX_CESA_CHAIN_LENGTH; -+ } -+#endif -+ } -+ -+ pReq->state = MV_CESA_PENDING; -+ -+ pCesaReqEmpty = MV_CESA_REQ_NEXT_PTR(pReq); -+ cesaReqResources -= 1; -+ -+/* #ifdef CESA_DEBUG */ -+ if( (cesaQueueDepth - cesaReqResources) > cesaStats.maxReqCount) -+ cesaStats.maxReqCount = (cesaQueueDepth - cesaReqResources); -+/* #endif CESA_DEBUG */ -+ -+ cesaLastSid = sid; -+ -+#if (MV_CESA_VERSION >= 3) -+ /* Are we within chain bounderies and follows the first request ? */ -+ if((chainReqNum > 0) && (chainReqNum < MAX_CESA_CHAIN_LENGTH)) { -+ if(chainIndex) { -+ pFromReq = MV_CESA_REQ_PREV_PTR(pReq); -+ pToReq = pReq; -+ pReq->state = MV_CESA_CHAIN; -+ /* assume concatenating is possible */ -+ pFromReq->dma[pFromReq->frags.numFrag-1].pDmaLast->phyNextDescPtr = -+ MV_32BIT_LE(mvCesaVirtToPhys(&pToReq->dmaDescBuf, pToReq->dma[0].pDmaFirst)); -+ mvOsCacheFlush(NULL, pFromReq->dma[pFromReq->frags.numFrag-1].pDmaLast, sizeof(MV_DMA_DESC)); -+ -+ /* align active & next pointers */ -+ if(pNextActiveChain->state != MV_CESA_PENDING) -+ pEndCurrChain = pNextActiveChain = MV_CESA_REQ_NEXT_PTR(pReq); -+ } -+ else { /* we have only one chain, start new one */ -+ chainReqNum = 0; -+ chainIndex++; -+ /* align active & next pointers */ -+ if(pNextActiveChain->state != MV_CESA_PENDING) -+ pEndCurrChain = pNextActiveChain = pReq; -+ } -+ } -+ else { -+ /* In case we concatenate full chain */ -+ if(chainReqNum == MAX_CESA_CHAIN_LENGTH) { -+ chainIndex++; -+ if(pNextActiveChain->state != MV_CESA_PENDING) -+ pEndCurrChain = pNextActiveChain = pReq; -+ chainReqNum = 0; -+ } -+ -+ pReq = pCesaReqProcess; -+ if(pReq->state == MV_CESA_PENDING) { -+ pNextActiveChain = pReq; -+ pEndCurrChain = MV_CESA_REQ_NEXT_PTR(pReq); -+ /* Start Process new request */ -+ mvCesaReqProcessStart(pReq); -+ } -+ } -+ -+ chainReqNum++; -+ -+ if((chainIndex < MAX_CESA_CHAIN_LENGTH) && (chainReqNum > cesaStats.maxChainUsage)) -+ cesaStats.maxChainUsage = chainReqNum; -+ -+#else -+ -+ /* Check status of CESA channels and process requests if possible */ -+ pReq = pCesaReqProcess; -+ if(pReq->state == MV_CESA_PENDING) -+ { -+ /* Start Process new request */ -+ mvCesaReqProcessStart(pReq); -+ } -+#endif -+ /* If request queue became FULL - return MV_NO_MORE */ -+ if(cesaReqResources == 0) -+ return MV_NO_MORE; -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvCesaReadyGet - Get crypto request that processing is finished -+* -+* DESCRIPTION: -+* This function complete request processing and return ready request to -+* caller. To don't miss interrupts the caller must call this function -+* while MV_OK or MV_TERMINATE values returned. -+* -+* INPUT: -+* MV_U32 chanMap - map of CESA channels finished thier job -+* accordingly with CESA Cause register. -+* MV_CESA_RESULT* pResult - pointer to structure contains information -+* about ready request. It includes pointer to -+* user private structure "pReqPrv", session identifier -+* for this request "sessionId" and return code. -+* Return code set to MV_FAIL if calculated digest value -+* on decode direction is different than digest value -+* in the packet. -+* -+* RETURN: -+* MV_OK - Success, ready request is returned. -+* MV_NOT_READY - Next request is not ready yet. New interrupt will -+* be generated for futher request processing. -+* MV_EMPTY - There is no more request for processing. -+* MV_BUSY - Fragmented request is not ready yet. -+* MV_TERMINATE - Call this function once more to complete processing -+* of fragmented request. -+* -+*******************************************************************************/ -+MV_STATUS mvCesaReadyGet(MV_CESA_RESULT* pResult) -+{ -+ MV_STATUS status, readyStatus = MV_NOT_READY; -+ MV_U32 statusReg; -+ MV_CESA_REQ* pReq; -+ MV_CESA_SA* pSA; -+ -+#if (MV_CESA_VERSION >= 3) -+ if(isFirstReq == MV_TRUE) { -+ if(chainIndex == 0) -+ chainReqNum = 0; -+ -+ isFirstReq = MV_FALSE; -+ -+ if(pNextActiveChain->state == MV_CESA_PENDING) { -+ /* Start request Process */ -+ mvCesaReqProcessStart(pNextActiveChain); -+ pEndCurrChain = pNextActiveChain; -+ if(chainIndex > 0) -+ chainIndex--; -+ /* Update pNextActiveChain to next chain head */ -+ while(pNextActiveChain->state == MV_CESA_CHAIN) -+ pNextActiveChain = MV_CESA_REQ_NEXT_PTR(pNextActiveChain); -+ } -+ } -+ -+ /* Check if there are more processed requests - can we remove pEndCurrChain ??? */ -+ if(pCesaReqProcess == pEndCurrChain) { -+ isFirstReq = MV_TRUE; -+ pEndCurrChain = pNextActiveChain; -+#else -+ if(pCesaReqProcess->state != MV_CESA_PROCESS) { -+#endif -+ return MV_EMPTY; -+ } -+ -+#ifdef CESA_DEBUG -+ statusReg = MV_REG_READ(MV_CESA_STATUS_REG); -+ if( statusReg & MV_CESA_STATUS_ACTIVE_MASK ) -+ { -+ mvOsPrintf("mvCesaReadyGet: Not Ready, Status = 0x%x\n", statusReg); -+ cesaStats.notReadyCount++; -+ return MV_NOT_READY; -+ } -+#endif /* CESA_DEBUG */ -+ -+ cesaStats.readyCount++; -+ -+ pReq = pCesaReqProcess; -+ pSA = &pCesaSAD[pReq->pCmd->sessionId]; -+ -+ pResult->retCode = MV_OK; -+ if(pReq->fragMode != MV_CESA_FRAG_NONE) -+ { -+ MV_U8* pNewDigest; -+ int frag; -+#if (MV_CESA_VERSION >= 3) -+ pReq->frags.nextFrag = 1; -+ while(pReq->frags.nextFrag <= pReq->frags.numFrag) { -+#endif -+ frag = (pReq->frags.nextFrag - 1); -+ -+ /* Restore DMA descriptor list */ -+ pReq->dma[frag].pDmaLast->phyNextDescPtr = -+ MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, &pReq->dma[frag].pDmaLast[1])); -+ pReq->dma[frag].pDmaLast = NULL; -+ -+ /* Special processing for finished fragmented request */ -+ if(pReq->frags.nextFrag >= pReq->frags.numFrag) -+ { -+ mvCesaMbufCacheUnmap(pReq->pCmd->pDst, 0, pReq->pCmd->pDst->mbufSize); -+ -+ /* Fragmented packet is ready */ -+ if( (pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ int macDataSize = pReq->pCmd->macLength - pReq->frags.macSize; -+ -+ if(macDataSize != 0) -+ { -+ /* Calculate all other blocks by SW */ -+ mvCesaFragAuthComplete(pReq, pSA, macDataSize); -+ } -+ -+ /* Copy new digest from SRAM to the Destination buffer */ -+ pNewDigest = cesaSramVirtPtr->buf + pReq->frags.newDigestOffset; -+ status = mvCesaCopyToMbuf(pNewDigest, pReq->pCmd->pDst, -+ pReq->pCmd->digestOffset, pSA->digestSize); -+ -+ /* For decryption: Compare new digest value with original one */ -+ if((pSA->config & MV_CESA_DIRECTION_MASK) == -+ (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) -+ { -+ if( memcmp(pNewDigest, pReq->frags.orgDigest, pSA->digestSize) != 0) -+ { -+/* -+ mvOsPrintf("Digest error: chan=%d, newDigest=%p, orgDigest=%p, status = 0x%x\n", -+ chan, pNewDigest, pReq->frags.orgDigest, MV_REG_READ(MV_CESA_STATUS_REG)); -+*/ -+ /* Signiture verification is failed */ -+ pResult->retCode = MV_FAIL; -+ } -+ } -+ } -+ readyStatus = MV_OK; -+ } -+#if (MV_CESA_VERSION >= 3) -+ pReq->frags.nextFrag++; -+ } -+#endif -+ } -+ else -+ { -+ mvCesaMbufCacheUnmap(pReq->pCmd->pDst, 0, pReq->pCmd->pDst->mbufSize); -+ -+ /* Restore DMA descriptor list */ -+ pReq->dma[0].pDmaLast->phyNextDescPtr = -+ MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, &pReq->dma[0].pDmaLast[1])); -+ pReq->dma[0].pDmaLast = NULL; -+ if( ((pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) && -+ ((pSA->config & MV_CESA_DIRECTION_MASK) == -+ (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) ) -+ { -+ /* For AUTH on decode : Check Digest result in Status register */ -+ statusReg = MV_REG_READ(MV_CESA_STATUS_REG); -+ if(statusReg & MV_CESA_STATUS_DIGEST_ERR_MASK) -+ { -+/* -+ mvOsPrintf("Digest error: chan=%d, status = 0x%x\n", -+ chan, statusReg); -+*/ -+ /* Signiture verification is failed */ -+ pResult->retCode = MV_FAIL; -+ } -+ } -+ readyStatus = MV_OK; -+ } -+ -+ if(readyStatus == MV_OK) -+ { -+ /* If Request is ready - Prepare pResult structure */ -+ pResult->pReqPrv = pReq->pCmd->pReqPrv; -+ pResult->sessionId = pReq->pCmd->sessionId; -+ -+ pReq->state = MV_CESA_IDLE; -+ pCesaReqProcess = MV_CESA_REQ_NEXT_PTR(pReq); -+ cesaReqResources++; -+ -+ if(pSA->ctrMode) -+ { -+ /* For AES CTR mode - complete processing and free allocated resources */ -+ mvCesaCtrModeComplete(pReq->pOrgCmd, pReq->pCmd); -+ mvCesaCtrModeFinish(pReq->pCmd); -+ pReq->pOrgCmd = NULL; -+ } -+ } -+ -+#if (MV_CESA_VERSION < 3) -+ if(pCesaReqProcess->state == MV_CESA_PROCESS) -+ { -+ /* Start request Process */ -+ mvCesaReqProcessStart(pCesaReqProcess); -+ if(readyStatus == MV_NOT_READY) -+ readyStatus = MV_BUSY; -+ } -+ else if(pCesaReqProcess != pCesaReqEmpty) -+ { -+ /* Start process new request from the queue */ -+ mvCesaReqProcessStart(pCesaReqProcess); -+ } -+#endif -+ return readyStatus; -+} -+ -+/***************** Functions to work with CESA_MBUF structure ******************/ -+ -+/******************************************************************************* -+* mvCesaMbufOffset - Locate offset in the Mbuf structure -+* -+* DESCRIPTION: -+* This function locates offset inside Multi-Bufeer structure. -+* It get fragment number and place in the fragment where the offset -+* is located. -+* -+* -+* INPUT: -+* MV_CESA_MBUF* pMbuf - Pointer to multi-buffer structure -+* int offset - Offset from the beginning of the data presented by -+* the Mbuf structure. -+* -+* OUTPUT: -+* int* pBufOffset - Offset from the beginning of the fragment where -+* the offset is located. -+* -+* RETURN: -+* int - Number of fragment, where the offset is located\ -+* -+*******************************************************************************/ -+int mvCesaMbufOffset(MV_CESA_MBUF* pMbuf, int offset, int* pBufOffset) -+{ -+ int frag = 0; -+ -+ while(offset > 0) -+ { -+ if(frag >= pMbuf->numFrags) -+ { -+ mvOsPrintf("mvCesaMbufOffset: Error: frag (%d) > numFrags (%d)\n", -+ frag, pMbuf->numFrags); -+ return MV_INVALID; -+ } -+ if(offset < pMbuf->pFrags[frag].bufSize) -+ { -+ break; -+ } -+ offset -= pMbuf->pFrags[frag].bufSize; -+ frag++; -+ } -+ if(pBufOffset != NULL) -+ *pBufOffset = offset; -+ -+ return frag; -+} -+ -+/******************************************************************************* -+* mvCesaCopyFromMbuf - Copy data from the Mbuf structure to continuous buffer -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_U8* pDstBuf - Pointer to continuous buffer, where data is -+* copied to. -+* MV_CESA_MBUF* pSrcMbuf - Pointer to multi-buffer structure where data is -+* copied from. -+* int offset - Offset in the Mbuf structure where located first -+* byte of data should be copied. -+* int size - Size of data should be copied -+* -+* RETURN: -+* MV_OK - Success, all data is copied successfully. -+* MV_OUT_OF_RANGE - Failed, offset is out of Multi-buffer data range. -+* No data is copied. -+* MV_EMPTY - Multi-buffer structure has not enough data to copy -+* Data from the offset to end of Mbuf data is copied. -+* -+*******************************************************************************/ -+MV_STATUS mvCesaCopyFromMbuf(MV_U8* pDstBuf, MV_CESA_MBUF* pSrcMbuf, -+ int offset, int size) -+{ -+ int frag, fragOffset, bufSize; -+ MV_U8* pBuf; -+ -+ if(size == 0) -+ return MV_OK; -+ -+ frag = mvCesaMbufOffset(pSrcMbuf, offset, &fragOffset); -+ if(frag == MV_INVALID) -+ { -+ mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); -+ return MV_OUT_OF_RANGE; -+ } -+ -+ bufSize = pSrcMbuf->pFrags[frag].bufSize - fragOffset; -+ pBuf = pSrcMbuf->pFrags[frag].bufVirtPtr + fragOffset; -+ while(MV_TRUE) -+ { -+ if(size <= bufSize) -+ { -+ memcpy(pDstBuf, pBuf, size); -+ return MV_OK; -+ } -+ memcpy(pDstBuf, pBuf, bufSize); -+ size -= bufSize; -+ frag++; -+ pDstBuf += bufSize; -+ if(frag >= pSrcMbuf->numFrags) -+ break; -+ -+ bufSize = pSrcMbuf->pFrags[frag].bufSize; -+ pBuf = pSrcMbuf->pFrags[frag].bufVirtPtr; -+ } -+ mvOsPrintf("mvCesaCopyFromMbuf: Mbuf is EMPTY - %d bytes isn't copied\n", -+ size); -+ return MV_EMPTY; -+} -+ -+/******************************************************************************* -+* mvCesaCopyToMbuf - Copy data from continuous buffer to the Mbuf structure -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_U8* pSrcBuf - Pointer to continuous buffer, where data is -+* copied from. -+* MV_CESA_MBUF* pDstMbuf - Pointer to multi-buffer structure where data is -+* copied to. -+* int offset - Offset in the Mbuf structure where located first -+* byte of data should be copied. -+* int size - Size of data should be copied -+* -+* RETURN: -+* MV_OK - Success, all data is copied successfully. -+* MV_OUT_OF_RANGE - Failed, offset is out of Multi-buffer data range. -+* No data is copied. -+* MV_FULL - Multi-buffer structure has not enough place to copy -+* all data. Data from the offset to end of Mbuf data -+* is copied. -+* -+*******************************************************************************/ -+MV_STATUS mvCesaCopyToMbuf(MV_U8* pSrcBuf, MV_CESA_MBUF* pDstMbuf, -+ int offset, int size) -+{ -+ int frag, fragOffset, bufSize; -+ MV_U8* pBuf; -+ -+ if(size == 0) -+ return MV_OK; -+ -+ frag = mvCesaMbufOffset(pDstMbuf, offset, &fragOffset); -+ if(frag == MV_INVALID) -+ { -+ mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); -+ return MV_OUT_OF_RANGE; -+ } -+ -+ bufSize = pDstMbuf->pFrags[frag].bufSize - fragOffset; -+ pBuf = pDstMbuf->pFrags[frag].bufVirtPtr + fragOffset; -+ while(MV_TRUE) -+ { -+ if(size <= bufSize) -+ { -+ memcpy(pBuf, pSrcBuf, size); -+ return MV_OK; -+ } -+ memcpy(pBuf, pSrcBuf, bufSize); -+ size -= bufSize; -+ frag++; -+ pSrcBuf += bufSize; -+ if(frag >= pDstMbuf->numFrags) -+ break; -+ -+ bufSize = pDstMbuf->pFrags[frag].bufSize; -+ pBuf = pDstMbuf->pFrags[frag].bufVirtPtr; -+ } -+ mvOsPrintf("mvCesaCopyToMbuf: Mbuf is FULL - %d bytes isn't copied\n", -+ size); -+ return MV_FULL; -+} -+ -+/******************************************************************************* -+* mvCesaMbufCopy - Copy data from one Mbuf structure to the other Mbuf structure -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* -+* MV_CESA_MBUF* pDstMbuf - Pointer to multi-buffer structure where data is -+* copied to. -+* int dstMbufOffset - Offset in the dstMbuf structure where first byte -+* of data should be copied to. -+* MV_CESA_MBUF* pSrcMbuf - Pointer to multi-buffer structure where data is -+* copied from. -+* int srcMbufOffset - Offset in the srcMbuf structure where first byte -+* of data should be copied from. -+* int size - Size of data should be copied -+* -+* RETURN: -+* MV_OK - Success, all data is copied successfully. -+* MV_OUT_OF_RANGE - Failed, srcMbufOffset or dstMbufOffset is out of -+* srcMbuf or dstMbuf structure correspondently. -+* No data is copied. -+* MV_BAD_SIZE - srcMbuf or dstMbuf structure is too small to copy -+* all data. Partial data is copied -+* -+*******************************************************************************/ -+MV_STATUS mvCesaMbufCopy(MV_CESA_MBUF* pMbufDst, int dstMbufOffset, -+ MV_CESA_MBUF* pMbufSrc, int srcMbufOffset, int size) -+{ -+ int srcFrag, dstFrag, srcSize, dstSize, srcOffset, dstOffset; -+ int copySize; -+ MV_U8 *pSrc, *pDst; -+ -+ if(size == 0) -+ return MV_OK; -+ -+ srcFrag = mvCesaMbufOffset(pMbufSrc, srcMbufOffset, &srcOffset); -+ if(srcFrag == MV_INVALID) -+ { -+ mvOsPrintf("CESA srcMbuf Error: offset (%d) out of range\n", srcMbufOffset); -+ return MV_OUT_OF_RANGE; -+ } -+ pSrc = pMbufSrc->pFrags[srcFrag].bufVirtPtr + srcOffset; -+ srcSize = pMbufSrc->pFrags[srcFrag].bufSize - srcOffset; -+ -+ dstFrag = mvCesaMbufOffset(pMbufDst, dstMbufOffset, &dstOffset); -+ if(dstFrag == MV_INVALID) -+ { -+ mvOsPrintf("CESA dstMbuf Error: offset (%d) out of range\n", dstMbufOffset); -+ return MV_OUT_OF_RANGE; -+ } -+ pDst = pMbufDst->pFrags[dstFrag].bufVirtPtr + dstOffset; -+ dstSize = pMbufDst->pFrags[dstFrag].bufSize - dstOffset; -+ -+ while(size > 0) -+ { -+ copySize = MV_MIN(srcSize, dstSize); -+ if(size <= copySize) -+ { -+ memcpy(pDst, pSrc, size); -+ return MV_OK; -+ } -+ memcpy(pDst, pSrc, copySize); -+ size -= copySize; -+ srcSize -= copySize; -+ dstSize -= copySize; -+ -+ if(srcSize == 0) -+ { -+ srcFrag++; -+ if(srcFrag >= pMbufSrc->numFrags) -+ break; -+ -+ pSrc = pMbufSrc->pFrags[srcFrag].bufVirtPtr; -+ srcSize = pMbufSrc->pFrags[srcFrag].bufSize; -+ } -+ -+ if(dstSize == 0) -+ { -+ dstFrag++; -+ if(dstFrag >= pMbufDst->numFrags) -+ break; -+ -+ pDst = pMbufDst->pFrags[dstFrag].bufVirtPtr; -+ dstSize = pMbufDst->pFrags[dstFrag].bufSize; -+ } -+ } -+ mvOsPrintf("mvCesaMbufCopy: BAD size - %d bytes isn't copied\n", -+ size); -+ -+ return MV_BAD_SIZE; -+} -+ -+static MV_STATUS mvCesaMbufCacheUnmap(MV_CESA_MBUF* pMbuf, int offset, int size) -+{ -+ int frag, fragOffset, bufSize; -+ MV_U8* pBuf; -+ -+ if(size == 0) -+ return MV_OK; -+ -+ frag = mvCesaMbufOffset(pMbuf, offset, &fragOffset); -+ if(frag == MV_INVALID) -+ { -+ mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); -+ return MV_OUT_OF_RANGE; -+ } -+ -+ bufSize = pMbuf->pFrags[frag].bufSize - fragOffset; -+ pBuf = pMbuf->pFrags[frag].bufVirtPtr + fragOffset; -+ while(MV_TRUE) -+ { -+ if(size <= bufSize) -+ { -+ mvOsCacheUnmap(NULL, mvOsIoVirtToPhy(NULL, pBuf), size); -+ return MV_OK; -+ } -+ -+ mvOsCacheUnmap(NULL, mvOsIoVirtToPhy(NULL, pBuf), bufSize); -+ size -= bufSize; -+ frag++; -+ if(frag >= pMbuf->numFrags) -+ break; -+ -+ bufSize = pMbuf->pFrags[frag].bufSize; -+ pBuf = pMbuf->pFrags[frag].bufVirtPtr; -+ } -+ mvOsPrintf("%s: Mbuf is FULL - %d bytes isn't Unmapped\n", -+ __FUNCTION__, size); -+ return MV_FULL; -+} -+ -+ -+/*************************************** Local Functions ******************************/ -+ -+/******************************************************************************* -+* mvCesaFragReqProcess - Process fragmented request -+* -+* DESCRIPTION: -+* This function processes a fragment of fragmented request (First, Middle or Last) -+* -+* -+* INPUT: -+* MV_CESA_REQ* pReq - Pointer to the request in the request queue. -+* -+* RETURN: -+* MV_OK - The fragment is successfully passed to HW for processing. -+* MV_TERMINATE - Means, that HW finished its work on this packet and no more -+* interrupts will be generated for this request. -+* Function mvCesaReadyGet() must be called to complete request -+* processing and get request result. -+* -+*******************************************************************************/ -+static MV_STATUS mvCesaFragReqProcess(MV_CESA_REQ* pReq, MV_U8 frag) -+{ -+ int i, copySize, cryptoDataSize, macDataSize, sid; -+ int cryptoIvOffset, digestOffset; -+ MV_U32 config; -+ MV_CESA_COMMAND* pCmd = pReq->pCmd; -+ MV_CESA_SA* pSA; -+ MV_CESA_MBUF* pMbuf; -+ MV_DMA_DESC* pDmaDesc = pReq->dma[frag].pDmaFirst; -+ MV_U8* pSramBuf = cesaSramVirtPtr->buf; -+ int macTotalLen = 0; -+ int fixOffset, cryptoOffset, macOffset; -+ -+ cesaStats.fragCount++; -+ -+ sid = pReq->pCmd->sessionId; -+ -+ pSA = &pCesaSAD[sid]; -+ -+ cryptoIvOffset = digestOffset = 0; -+ i = macDataSize = 0; -+ cryptoDataSize = 0; -+ -+ /* First fragment processing */ -+ if(pReq->fragMode == MV_CESA_FRAG_FIRST) -+ { -+ /* pReq->frags monitors processing of fragmented request between fragments */ -+ pReq->frags.bufOffset = 0; -+ pReq->frags.cryptoSize = 0; -+ pReq->frags.macSize = 0; -+ -+ config = pSA->config | (MV_CESA_FRAG_FIRST << MV_CESA_FRAG_MODE_OFFSET); -+ -+ /* fixOffset can be not equal to zero only for FIRST fragment */ -+ fixOffset = pReq->fixOffset; -+ /* For FIRST fragment crypto and mac offsets are taken from pCmd */ -+ cryptoOffset = pCmd->cryptoOffset; -+ macOffset = pCmd->macOffset; -+ -+ copySize = sizeof(cesaSramVirtPtr->buf) - pReq->fixOffset; -+ -+ /* Find fragment size: Must meet all requirements for CRYPTO and MAC -+ * cryptoDataSize - size of data will be encrypted/decrypted in this fragment -+ * macDataSize - size of data will be signed/verified in this fragment -+ * copySize - size of data will be copied from srcMbuf to SRAM and -+ * back to dstMbuf for this fragment -+ */ -+ mvCesaFragSizeFind(pSA, pReq, cryptoOffset, macOffset, -+ ©Size, &cryptoDataSize, &macDataSize); -+ -+ if( (pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) -+ { -+ /* CryptoIV special processing */ -+ if( (pSA->config & MV_CESA_CRYPTO_MODE_MASK) == -+ (MV_CESA_CRYPTO_CBC << MV_CESA_CRYPTO_MODE_BIT) ) -+ { -+ /* In CBC mode for encode direction when IV from user */ -+ if( (pCmd->ivFromUser) && -+ ((pSA->config & MV_CESA_DIRECTION_MASK) == -+ (MV_CESA_DIR_ENCODE << MV_CESA_DIRECTION_BIT)) ) -+ { -+ -+ /* For Crypto Encode in CBC mode HW always takes IV from SRAM IVPointer, -+ * (not from IVBufPointer). So when ivFromUser==1, we should copy IV from user place -+ * in the buffer to SRAM IVPointer -+ */ -+ i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->cryptoIV, &pDmaDesc[i], -+ MV_FALSE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); -+ } -+ -+ /* Special processing when IV is not located in the first fragment */ -+ if(pCmd->ivOffset > (copySize - pSA->cryptoIvSize)) -+ { -+ /* Prepare dummy place for cryptoIV in SRAM */ -+ cryptoIvOffset = cesaSramVirtPtr->tempCryptoIV - mvCesaSramAddrGet(); -+ -+ /* For Decryption: Copy IV value from pCmd->ivOffset to Special SRAM place */ -+ if((pSA->config & MV_CESA_DIRECTION_MASK) == -+ (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) -+ { -+ i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->tempCryptoIV, &pDmaDesc[i], -+ MV_FALSE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); -+ } -+ else -+ { -+ /* For Encryption when IV is NOT from User: */ -+ /* Copy IV from SRAM to buffer (pCmd->ivOffset) */ -+ if(pCmd->ivFromUser == 0) -+ { -+ /* copy IV value from cryptoIV to Buffer (pCmd->ivOffset) */ -+ i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->cryptoIV, &pDmaDesc[i], -+ MV_TRUE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); -+ } -+ } -+ } -+ else -+ { -+ cryptoIvOffset = pCmd->ivOffset; -+ } -+ } -+ } -+ -+ if( (pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ /* MAC digest special processing on Decode direction */ -+ if((pSA->config & MV_CESA_DIRECTION_MASK) == -+ (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) -+ { -+ /* Save digest from pCmd->digestOffset */ -+ mvCesaCopyFromMbuf(pReq->frags.orgDigest, -+ pCmd->pSrc, pCmd->digestOffset, pSA->digestSize); -+ -+ /* If pCmd->digestOffset is not located on the first */ -+ if(pCmd->digestOffset > (copySize - pSA->digestSize)) -+ { -+ MV_U8 digestZero[MV_CESA_MAX_DIGEST_SIZE]; -+ -+ /* Set zeros to pCmd->digestOffset (DRAM) */ -+ memset(digestZero, 0, MV_CESA_MAX_DIGEST_SIZE); -+ mvCesaCopyToMbuf(digestZero, pCmd->pSrc, pCmd->digestOffset, pSA->digestSize); -+ -+ /* Prepare dummy place for digest in SRAM */ -+ digestOffset = cesaSramVirtPtr->tempDigest - mvCesaSramAddrGet(); -+ } -+ else -+ { -+ digestOffset = pCmd->digestOffset; -+ } -+ } -+ } -+ /* Update SA in SRAM */ -+ if(cesaLastSid != sid) -+ { -+ mvCesaSramSaUpdate(sid, &pDmaDesc[i]); -+ i++; -+ } -+ -+ pReq->fragMode = MV_CESA_FRAG_MIDDLE; -+ } -+ else -+ { -+ /* Continue fragment */ -+ fixOffset = 0; -+ cryptoOffset = 0; -+ macOffset = 0; -+ if( (pCmd->pSrc->mbufSize - pReq->frags.bufOffset) <= sizeof(cesaSramVirtPtr->buf)) -+ { -+ /* Last fragment */ -+ config = pSA->config | (MV_CESA_FRAG_LAST << MV_CESA_FRAG_MODE_OFFSET); -+ pReq->fragMode = MV_CESA_FRAG_LAST; -+ copySize = pCmd->pSrc->mbufSize - pReq->frags.bufOffset; -+ -+ if( (pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ macDataSize = pCmd->macLength - pReq->frags.macSize; -+ -+ /* If pCmd->digestOffset is not located on last fragment */ -+ if(pCmd->digestOffset < pReq->frags.bufOffset) -+ { -+ /* Prepare dummy place for digest in SRAM */ -+ digestOffset = cesaSramVirtPtr->tempDigest - mvCesaSramAddrGet(); -+ } -+ else -+ { -+ digestOffset = pCmd->digestOffset - pReq->frags.bufOffset; -+ } -+ pReq->frags.newDigestOffset = digestOffset; -+ macTotalLen = pCmd->macLength; -+ -+ /* HW can't calculate the Digest correctly for fragmented packets -+ * in the following cases: -+ * - MV88F5182 || -+ * - MV88F5181L when total macLength more that 16 Kbytes || -+ * - total macLength more that 64 Kbytes -+ */ -+ if( (mvCtrlModelGet() == MV_5182_DEV_ID) || -+ ( (mvCtrlModelGet() == MV_5181_DEV_ID) && -+ (mvCtrlRevGet() >= MV_5181L_A0_REV) && -+ (pCmd->macLength >= (1 << 14)) ) ) -+ { -+ return MV_TERMINATE; -+ } -+ } -+ if( (pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ cryptoDataSize = pCmd->cryptoLength - pReq->frags.cryptoSize; -+ } -+ -+ /* cryptoIvOffset - don't care */ -+ } -+ else -+ { -+ /* WA for MV88F5182 SHA1 and MD5 fragmentation mode */ -+ if( (mvCtrlModelGet() == MV_5182_DEV_ID) && -+ (((pSA->config & MV_CESA_MAC_MODE_MASK) == -+ (MV_CESA_MAC_MD5 << MV_CESA_MAC_MODE_OFFSET)) || -+ ((pSA->config & MV_CESA_MAC_MODE_MASK) == -+ (MV_CESA_MAC_SHA1 << MV_CESA_MAC_MODE_OFFSET))) ) -+ { -+ pReq->frags.newDigestOffset = cesaSramVirtPtr->tempDigest - mvCesaSramAddrGet(); -+ pReq->fragMode = MV_CESA_FRAG_LAST; -+ -+ return MV_TERMINATE; -+ } -+ /* Middle fragment */ -+ config = pSA->config | (MV_CESA_FRAG_MIDDLE << MV_CESA_FRAG_MODE_OFFSET); -+ copySize = sizeof(cesaSramVirtPtr->buf); -+ /* digestOffset and cryptoIvOffset - don't care */ -+ -+ /* Find fragment size */ -+ mvCesaFragSizeFind(pSA, pReq, cryptoOffset, macOffset, -+ ©Size, &cryptoDataSize, &macDataSize); -+ } -+ } -+ /********* Prepare DMA descriptors to copy from pSrc to SRAM *********/ -+ pMbuf = pCmd->pSrc; -+ i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], -+ MV_FALSE, pReq->frags.bufOffset, copySize, pCmd->skipFlush); -+ -+ /* Prepare CESA descriptor to copy from DRAM to SRAM by DMA */ -+ mvCesaSramDescrBuild(config, frag, -+ cryptoOffset + fixOffset, cryptoIvOffset + fixOffset, -+ cryptoDataSize, macOffset + fixOffset, -+ digestOffset + fixOffset, macDataSize, macTotalLen, -+ pReq, &pDmaDesc[i]); -+ i++; -+ -+ /* Add special descriptor Ownership for CPU */ -+ pDmaDesc[i].byteCnt = 0; -+ pDmaDesc[i].phySrcAdd = 0; -+ pDmaDesc[i].phyDestAdd = 0; -+ i++; -+ -+ /********* Prepare DMA descriptors to copy from SRAM to pDst *********/ -+ pMbuf = pCmd->pDst; -+ i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], -+ MV_TRUE, pReq->frags.bufOffset, copySize, pCmd->skipFlush); -+ -+ /* Next field of Last DMA descriptor must be NULL */ -+ pDmaDesc[i-1].phyNextDescPtr = 0; -+ pReq->dma[frag].pDmaLast = &pDmaDesc[i-1]; -+ mvOsCacheFlush(NULL, pReq->dma[frag].pDmaFirst, -+ i*sizeof(MV_DMA_DESC)); -+ -+ /*mvCesaDebugDescriptor(&cesaSramVirtPtr->desc[frag]);*/ -+ -+ pReq->frags.bufOffset += copySize; -+ pReq->frags.cryptoSize += cryptoDataSize; -+ pReq->frags.macSize += macDataSize; -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvCesaReqProcess - Process regular (Non-fragmented) request -+* -+* DESCRIPTION: -+* This function processes the whole (not fragmented) request -+* -+* INPUT: -+* MV_CESA_REQ* pReq - Pointer to the request in the request queue. -+* -+* RETURN: -+* MV_OK - The request is successfully passed to HW for processing. -+* Other - Failure. The request will not be processed -+* -+*******************************************************************************/ -+static MV_STATUS mvCesaReqProcess(MV_CESA_REQ* pReq) -+{ -+ MV_CESA_MBUF *pMbuf; -+ MV_DMA_DESC *pDmaDesc; -+ MV_U8 *pSramBuf; -+ int sid, i, fixOffset; -+ MV_CESA_SA *pSA; -+ MV_CESA_COMMAND *pCmd = pReq->pCmd; -+ -+ cesaStats.procCount++; -+ -+ sid = pCmd->sessionId; -+ pSA = &pCesaSAD[sid]; -+ pDmaDesc = pReq->dma[0].pDmaFirst; -+ pSramBuf = cesaSramVirtPtr->buf; -+ fixOffset = pReq->fixOffset; -+ -+/* -+ mvOsPrintf("mvCesaReqProcess: sid=%d, pSA=%p, pDmaDesc=%p, pSramBuf=%p\n", -+ sid, pSA, pDmaDesc, pSramBuf); -+*/ -+ i = 0; -+ -+ /* Crypto IV Special processing in CBC mode for Encryption direction */ -+ if( ((pSA->config & MV_CESA_OPERATION_MASK) != (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) && -+ ((pSA->config & MV_CESA_CRYPTO_MODE_MASK) == (MV_CESA_CRYPTO_CBC << MV_CESA_CRYPTO_MODE_BIT)) && -+ ((pSA->config & MV_CESA_DIRECTION_MASK) == (MV_CESA_DIR_ENCODE << MV_CESA_DIRECTION_BIT)) && -+ (pCmd->ivFromUser) ) -+ { -+ /* For Crypto Encode in CBC mode HW always takes IV from SRAM IVPointer, -+ * (not from IVBufPointer). So when ivFromUser==1, we should copy IV from user place -+ * in the buffer to SRAM IVPointer -+ */ -+ i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->cryptoIV, &pDmaDesc[i], -+ MV_FALSE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); -+ } -+ -+ /* Update SA in SRAM */ -+ if(cesaLastSid != sid) -+ { -+ mvCesaSramSaUpdate(sid, &pDmaDesc[i]); -+ i++; -+ } -+ -+ /********* Prepare DMA descriptors to copy from pSrc to SRAM *********/ -+ pMbuf = pCmd->pSrc; -+ i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], -+ MV_FALSE, 0, pMbuf->mbufSize, pCmd->skipFlush); -+ -+ /* Prepare Security Accelerator descriptor to SRAM words 0 - 7 */ -+ mvCesaSramDescrBuild(pSA->config, 0, pCmd->cryptoOffset + fixOffset, -+ pCmd->ivOffset + fixOffset, pCmd->cryptoLength, -+ pCmd->macOffset + fixOffset, pCmd->digestOffset + fixOffset, -+ pCmd->macLength, pCmd->macLength, pReq, &pDmaDesc[i]); -+ i++; -+ -+ /* Add special descriptor Ownership for CPU */ -+ pDmaDesc[i].byteCnt = 0; -+ pDmaDesc[i].phySrcAdd = 0; -+ pDmaDesc[i].phyDestAdd = 0; -+ i++; -+ -+ /********* Prepare DMA descriptors to copy from SRAM to pDst *********/ -+ pMbuf = pCmd->pDst; -+ i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], -+ MV_TRUE, 0, pMbuf->mbufSize, pCmd->skipFlush); -+ -+ /* Next field of Last DMA descriptor must be NULL */ -+ pDmaDesc[i-1].phyNextDescPtr = 0; -+ pReq->dma[0].pDmaLast = &pDmaDesc[i-1]; -+ mvOsCacheFlush(NULL, pReq->dma[0].pDmaFirst, i*sizeof(MV_DMA_DESC)); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvCesaSramDescrBuild - Set CESA descriptor in SRAM -+* -+* DESCRIPTION: -+* This function builds CESA descriptor in SRAM from all Command parameters -+* -+* -+* INPUT: -+* int chan - CESA channel uses the descriptor -+* MV_U32 config - 32 bits of WORD_0 in CESA descriptor structure -+* int cryptoOffset - Offset from the beginning of SRAM buffer where -+* data for encryption/decription is started. -+* int ivOffset - Offset of crypto IV from the SRAM base. Valid only -+* for first fragment. -+* int cryptoLength - Size (in bytes) of data for encryption/descryption -+* operation on this fragment. -+* int macOffset - Offset from the beginning of SRAM buffer where -+* data for Authentication is started -+* int digestOffset - Offset from the beginning of SRAM buffer where -+* digest is located. Valid for first and last fragments. -+* int macLength - Size (in bytes) of data for Authentication -+* operation on this fragment. -+* int macTotalLen - Toatl size (in bytes) of data for Authentication -+* operation on the whole request (packet). Valid for -+* last fragment only. -+* -+* RETURN: None -+* -+*******************************************************************************/ -+static void mvCesaSramDescrBuild(MV_U32 config, int frag, -+ int cryptoOffset, int ivOffset, int cryptoLength, -+ int macOffset, int digestOffset, int macLength, -+ int macTotalLen, MV_CESA_REQ* pReq, MV_DMA_DESC* pDmaDesc) -+{ -+ MV_CESA_DESC* pCesaDesc = &pReq->pCesaDesc[frag]; -+ MV_CESA_DESC* pSramDesc = pSramDesc = &cesaSramVirtPtr->desc; -+ MV_U16 sramBufOffset = (MV_U16)((MV_U8*)cesaSramVirtPtr->buf - mvCesaSramAddrGet()); -+ -+ pCesaDesc->config = MV_32BIT_LE(config); -+ -+ if( (config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ /* word 1 */ -+ pCesaDesc->cryptoSrcOffset = MV_16BIT_LE(sramBufOffset + cryptoOffset); -+ pCesaDesc->cryptoDstOffset = MV_16BIT_LE(sramBufOffset + cryptoOffset); -+ /* word 2 */ -+ pCesaDesc->cryptoDataLen = MV_16BIT_LE(cryptoLength); -+ /* word 3 */ -+ pCesaDesc->cryptoKeyOffset = MV_16BIT_LE((MV_U16)(cesaSramVirtPtr->sramSA.cryptoKey - -+ mvCesaSramAddrGet())); -+ /* word 4 */ -+ pCesaDesc->cryptoIvOffset = MV_16BIT_LE((MV_U16)(cesaSramVirtPtr->cryptoIV - -+ mvCesaSramAddrGet())); -+ pCesaDesc->cryptoIvBufOffset = MV_16BIT_LE(sramBufOffset + ivOffset); -+ } -+ -+ if( (config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ /* word 5 */ -+ pCesaDesc->macSrcOffset = MV_16BIT_LE(sramBufOffset + macOffset); -+ pCesaDesc->macTotalLen = MV_16BIT_LE(macTotalLen); -+ -+ /* word 6 */ -+ pCesaDesc->macDigestOffset = MV_16BIT_LE(sramBufOffset + digestOffset); -+ pCesaDesc->macDataLen = MV_16BIT_LE(macLength); -+ -+ /* word 7 */ -+ pCesaDesc->macInnerIvOffset = MV_16BIT_LE((MV_U16)(cesaSramVirtPtr->sramSA.macInnerIV - -+ mvCesaSramAddrGet())); -+ pCesaDesc->macOuterIvOffset = MV_16BIT_LE((MV_U16)(cesaSramVirtPtr->sramSA.macOuterIV - -+ mvCesaSramAddrGet())); -+ } -+ /* Prepare DMA descriptor to CESA descriptor from DRAM to SRAM */ -+ pDmaDesc->phySrcAdd = MV_32BIT_LE(mvCesaVirtToPhys(&pReq->cesaDescBuf, pCesaDesc)); -+ pDmaDesc->phyDestAdd = MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (MV_U8*)pSramDesc)); -+ pDmaDesc->byteCnt = MV_32BIT_LE(sizeof(MV_CESA_DESC) | BIT31); -+ -+ /* flush Source buffer */ -+ mvOsCacheFlush(NULL, pCesaDesc, sizeof(MV_CESA_DESC)); -+} -+ -+/******************************************************************************* -+* mvCesaSramSaUpdate - Move required SA information to SRAM if needed. -+* -+* DESCRIPTION: -+* Copy to SRAM values of the required SA. -+* -+* -+* INPUT: -+* short sid - Session ID needs SRAM Cache update -+* MV_DMA_DESC *pDmaDesc - Pointer to DMA descriptor used to -+* copy SA values from DRAM to SRAM. -+* -+* RETURN: -+* MV_OK - Cache entry for this SA copied to SRAM. -+* MV_NO_CHANGE - Cache entry for this SA already exist in SRAM -+* -+*******************************************************************************/ -+static INLINE void mvCesaSramSaUpdate(short sid, MV_DMA_DESC *pDmaDesc) -+{ -+ MV_CESA_SA *pSA = &pCesaSAD[sid]; -+ -+ /* Prepare DMA descriptor to Copy CACHE_SA from SA database in DRAM to SRAM */ -+ pDmaDesc->byteCnt = MV_32BIT_LE(sizeof(MV_CESA_SRAM_SA) | BIT31); -+ pDmaDesc->phySrcAdd = MV_32BIT_LE(mvCesaVirtToPhys(&cesaSramSaBuf, pSA->pSramSA)); -+ pDmaDesc->phyDestAdd = -+ MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (MV_U8*)&cesaSramVirtPtr->sramSA)); -+ -+ /* Source buffer is already flushed during OpenSession*/ -+ /*mvOsCacheFlush(NULL, &pSA->sramSA, sizeof(MV_CESA_SRAM_SA));*/ -+} -+ -+/******************************************************************************* -+* mvCesaDmaCopyPrepare - prepare DMA descriptor list to copy data presented by -+* Mbuf structure from DRAM to SRAM -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_CESA_MBUF* pMbuf - pointer to Mbuf structure contains request -+* data in DRAM -+* MV_U8* pSramBuf - pointer to buffer in SRAM where data should -+* be copied to. -+* MV_DMA_DESC* pDmaDesc - pointer to first DMA descriptor for this copy. -+* The function set number of DMA descriptors needed -+* to copy the copySize bytes from Mbuf. -+* MV_BOOL isToMbuf - Copy direction. -+* MV_TRUE means copy from SRAM buffer to Mbuf in DRAM. -+* MV_FALSE means copy from Mbuf in DRAM to SRAM buffer. -+* int offset - Offset in the Mbuf structure that copy should be -+* started from. -+* int copySize - Size of data should be copied. -+* -+* RETURN: -+* int - number of DMA descriptors used for the copy. -+* -+*******************************************************************************/ -+#ifndef MV_NETBSD -+static INLINE int mvCesaDmaCopyPrepare(MV_CESA_MBUF* pMbuf, MV_U8* pSramBuf, -+ MV_DMA_DESC* pDmaDesc, MV_BOOL isToMbuf, -+ int offset, int copySize, MV_BOOL skipFlush) -+{ -+ int bufOffset, bufSize, size, frag, i; -+ MV_U8* pBuf; -+ -+ i = 0; -+ -+ /* Calculate start place for copy: fragment number and offset in the fragment */ -+ frag = mvCesaMbufOffset(pMbuf, offset, &bufOffset); -+ bufSize = pMbuf->pFrags[frag].bufSize - bufOffset; -+ pBuf = pMbuf->pFrags[frag].bufVirtPtr + bufOffset; -+ -+ /* Size accumulate total copy size */ -+ size = 0; -+ -+ /* Create DMA lists to copy mBuf from pSrc to SRAM */ -+ while(size < copySize) -+ { -+ /* Find copy size for each DMA descriptor */ -+ bufSize = MV_MIN(bufSize, (copySize - size)); -+ pDmaDesc[i].byteCnt = MV_32BIT_LE(bufSize | BIT31); -+ if(isToMbuf) -+ { -+ pDmaDesc[i].phyDestAdd = MV_32BIT_LE(mvOsIoVirtToPhy(NULL, pBuf)); -+ pDmaDesc[i].phySrcAdd = -+ MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (pSramBuf + size))); -+ /* invalidate the buffer */ -+ if(skipFlush == MV_FALSE) -+ mvOsCacheInvalidate(NULL, pBuf, bufSize); -+ } -+ else -+ { -+ pDmaDesc[i].phySrcAdd = MV_32BIT_LE(mvOsIoVirtToPhy(NULL, pBuf)); -+ pDmaDesc[i].phyDestAdd = -+ MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (pSramBuf + size))); -+ /* flush the buffer */ -+ if(skipFlush == MV_FALSE) -+ mvOsCacheFlush(NULL, pBuf, bufSize); -+ } -+ -+ /* Count number of used DMA descriptors */ -+ i++; -+ size += bufSize; -+ -+ /* go to next fragment in the Mbuf */ -+ frag++; -+ pBuf = pMbuf->pFrags[frag].bufVirtPtr; -+ bufSize = pMbuf->pFrags[frag].bufSize; -+ } -+ return i; -+} -+#else /* MV_NETBSD */ -+static int mvCesaDmaCopyPrepare(MV_CESA_MBUF* pMbuf, MV_U8* pSramBuf, -+ MV_DMA_DESC* pDmaDesc, MV_BOOL isToMbuf, -+ int offset, int copySize, MV_BOOL skipFlush) -+{ -+ int bufOffset, bufSize, thisSize, size, frag, i; -+ MV_ULONG bufPhys, sramPhys; -+ MV_U8* pBuf; -+ -+ /* -+ * Calculate start place for copy: fragment number and offset in -+ * the fragment -+ */ -+ frag = mvCesaMbufOffset(pMbuf, offset, &bufOffset); -+ -+ /* -+ * Get SRAM physical address only once. We can update it in-place -+ * as we build the descriptor chain. -+ */ -+ sramPhys = mvCesaSramVirtToPhys(NULL, pSramBuf); -+ -+ /* -+ * 'size' accumulates total copy size, 'i' counts desccriptors. -+ */ -+ size = i = 0; -+ -+ /* Create DMA lists to copy mBuf from pSrc to SRAM */ -+ while (size < copySize) { -+ /* -+ * Calculate # of bytes to copy from the current fragment, -+ * and the pointer to the start of data -+ */ -+ bufSize = pMbuf->pFrags[frag].bufSize - bufOffset; -+ pBuf = pMbuf->pFrags[frag].bufVirtPtr + bufOffset; -+ bufOffset = 0; /* First frag may be non-zero */ -+ frag++; -+ -+ /* -+ * As long as there is data in the current fragment... -+ */ -+ while (bufSize > 0) { -+ /* -+ * Ensure we don't cross an MMU page boundary. -+ * XXX: This is NetBSD-specific, but it is a -+ * quick and dirty way to fix the problem. -+ * A true HAL would rely on the OS-specific -+ * driver to do this... -+ */ -+ thisSize = PAGE_SIZE - -+ (((MV_ULONG)pBuf) & (PAGE_SIZE - 1)); -+ thisSize = MV_MIN(bufSize, thisSize); -+ /* -+ * Make sure we don't copy more than requested -+ */ -+ if (thisSize > (copySize - size)) { -+ thisSize = copySize - size; -+ bufSize = 0; -+ } -+ -+ /* -+ * Physicall address of this fragment -+ */ -+ bufPhys = MV_32BIT_LE(mvOsIoVirtToPhy(NULL, pBuf)); -+ -+ /* -+ * Set up the descriptor -+ */ -+ pDmaDesc[i].byteCnt = MV_32BIT_LE(thisSize | BIT31); -+ if(isToMbuf) { -+ pDmaDesc[i].phyDestAdd = bufPhys; -+ pDmaDesc[i].phySrcAdd = MV_32BIT_LE(sramPhys); -+ /* invalidate the buffer */ -+ if(skipFlush == MV_FALSE) -+ mvOsCacheInvalidate(NULL, pBuf, thisSize); -+ } else { -+ pDmaDesc[i].phySrcAdd = bufPhys; -+ pDmaDesc[i].phyDestAdd = MV_32BIT_LE(sramPhys); -+ /* flush the buffer */ -+ if(skipFlush == MV_FALSE) -+ mvOsCacheFlush(NULL, pBuf, thisSize); -+ } -+ -+ pDmaDesc[i].phyNextDescPtr = -+ MV_32BIT_LE(mvOsIoVirtToPhy(NULL,(&pDmaDesc[i+1]))); -+ -+ /* flush the DMA desc */ -+ mvOsCacheFlush(NULL, &pDmaDesc[i], sizeof(MV_DMA_DESC)); -+ -+ /* Update state */ -+ bufSize -= thisSize; -+ sramPhys += thisSize; -+ pBuf += thisSize; -+ size += thisSize; -+ i++; -+ } -+ } -+ -+ return i; -+} -+#endif /* MV_NETBSD */ -+/******************************************************************************* -+* mvCesaHmacIvGet - Calculate Inner and Outter values from HMAC key -+* -+* DESCRIPTION: -+* This function calculate Inner and Outer values used for HMAC algorithm. -+* This operation allows improve performance fro the whole HMAC processing. -+* -+* INPUT: -+* MV_CESA_MAC_MODE macMode - Authentication mode: HMAC_MD5 or HMAC_SHA1. -+* unsigned char key[] - Pointer to HMAC key. -+* int keyLength - Size of HMAC key (maximum 64 bytes) -+* -+* OUTPUT: -+* unsigned char innerIV[] - HASH(key^inner) -+* unsigned char outerIV[] - HASH(key^outter) -+* -+* RETURN: None -+* -+*******************************************************************************/ -+static void mvCesaHmacIvGet(MV_CESA_MAC_MODE macMode, unsigned char key[], int keyLength, -+ unsigned char innerIV[], unsigned char outerIV[]) -+{ -+ unsigned char inner[MV_CESA_MAX_MAC_KEY_LENGTH]; -+ unsigned char outer[MV_CESA_MAX_MAC_KEY_LENGTH]; -+ int i, digestSize = 0; -+#if defined(MV_CPU_LE) || defined(MV_PPC) -+ MV_U32 swapped32, val32, *pVal32; -+#endif -+ for(i=0; ipFrags[frag].bufVirtPtr + fragOffset; -+ size = pMbuf->pFrags[frag].bufSize - fragOffset; -+ -+ /* Complete Inner part */ -+ while(macLeftSize > 0) -+ { -+ if(macLeftSize <= size) -+ { -+ mvSHA1Update(&ctx, pData, macLeftSize); -+ break; -+ } -+ mvSHA1Update(&ctx, pData, size); -+ macLeftSize -= size; -+ frag++; -+ pData = pMbuf->pFrags[frag].bufVirtPtr; -+ size = pMbuf->pFrags[frag].bufSize; -+ } -+ mvSHA1Final(pDigest, &ctx); -+/* -+ mvOsPrintf("mvCesaFragSha1Complete: pOuterIV=%p, macLeftSize=%d, macTotalSize=%d\n", -+ pOuterIV, macLeftSize, macTotalSize); -+ mvDebugMemDump(pDigest, MV_CESA_SHA1_DIGEST_SIZE, 1); -+*/ -+ -+ if(pOuterIV != NULL) -+ { -+ /* If HMAC - Complete Outer part */ -+ for(i=0; ipFrags[frag].bufVirtPtr + fragOffset; -+ size = pMbuf->pFrags[frag].bufSize - fragOffset; -+ -+ /* Complete Inner part */ -+ while(macLeftSize > 0) -+ { -+ if(macLeftSize <= size) -+ { -+ mvMD5Update(&ctx, pData, macLeftSize); -+ break; -+ } -+ mvMD5Update(&ctx, pData, size); -+ macLeftSize -= size; -+ frag++; -+ pData = pMbuf->pFrags[frag].bufVirtPtr; -+ size = pMbuf->pFrags[frag].bufSize; -+ } -+ mvMD5Final(pDigest, &ctx); -+ -+/* -+ mvOsPrintf("mvCesaFragMd5Complete: pOuterIV=%p, macLeftSize=%d, macTotalSize=%d\n", -+ pOuterIV, macLeftSize, macTotalSize); -+ mvDebugMemDump(pDigest, MV_CESA_MD5_DIGEST_SIZE, 1); -+*/ -+ if(pOuterIV != NULL) -+ { -+ /* Complete Outer part */ -+ for(i=0; ipCmd; -+ MV_U8* pDigest; -+ MV_CESA_MAC_MODE macMode; -+ MV_U8* pOuterIV = NULL; -+ -+ /* Copy data from Source fragment to Destination */ -+ if(pCmd->pSrc != pCmd->pDst) -+ { -+ mvCesaMbufCopy(pCmd->pDst, pReq->frags.bufOffset, -+ pCmd->pSrc, pReq->frags.bufOffset, macDataSize); -+ } -+ -+/* -+ mvCesaCopyFromMbuf(cesaSramVirtPtr->buf[0], pCmd->pSrc, pReq->frags.bufOffset, macDataSize); -+ mvCesaCopyToMbuf(cesaSramVirtPtr->buf[0], pCmd->pDst, pReq->frags.bufOffset, macDataSize); -+*/ -+ pDigest = (mvCesaSramAddrGet() + pReq->frags.newDigestOffset); -+ -+ macMode = (pSA->config & MV_CESA_MAC_MODE_MASK) >> MV_CESA_MAC_MODE_OFFSET; -+/* -+ mvOsPrintf("macDataSize=%d, macLength=%d, digestOffset=%d, macMode=%d\n", -+ macDataSize, pCmd->macLength, pCmd->digestOffset, macMode); -+*/ -+ switch(macMode) -+ { -+ case MV_CESA_MAC_HMAC_MD5: -+ pOuterIV = pSA->pSramSA->macOuterIV; -+ -+ case MV_CESA_MAC_MD5: -+ mvCesaFragMd5Complete(pCmd->pDst, pReq->frags.bufOffset, pOuterIV, -+ macDataSize, pCmd->macLength, pDigest); -+ break; -+ -+ case MV_CESA_MAC_HMAC_SHA1: -+ pOuterIV = pSA->pSramSA->macOuterIV; -+ -+ case MV_CESA_MAC_SHA1: -+ mvCesaFragSha1Complete(pCmd->pDst, pReq->frags.bufOffset, pOuterIV, -+ macDataSize, pCmd->macLength, pDigest); -+ break; -+ -+ default: -+ mvOsPrintf("mvCesaFragAuthComplete: Unexpected macMode %d\n", macMode); -+ return MV_BAD_PARAM; -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaCtrModeInit - -+* -+* DESCRIPTION: -+* -+* -+* INPUT: NONE -+* -+* -+* RETURN: -+* MV_CESA_COMMAND* -+* -+*******************************************************************************/ -+static MV_CESA_COMMAND* mvCesaCtrModeInit(void) -+{ -+ MV_CESA_MBUF *pMbuf; -+ MV_U8 *pBuf; -+ MV_CESA_COMMAND *pCmd; -+ -+ pBuf = mvOsMalloc(sizeof(MV_CESA_COMMAND) + -+ sizeof(MV_CESA_MBUF) + sizeof(MV_BUF_INFO) + 100); -+ if(pBuf == NULL) -+ { -+ mvOsPrintf("mvCesaSessionOpen: Can't allocate %u bytes for CTR Mode\n", -+ sizeof(MV_CESA_COMMAND) + sizeof(MV_CESA_MBUF) + sizeof(MV_BUF_INFO) ); -+ return NULL; -+ } -+ pCmd = (MV_CESA_COMMAND*)pBuf; -+ pBuf += sizeof(MV_CESA_COMMAND); -+ -+ pMbuf = (MV_CESA_MBUF*)pBuf; -+ pBuf += sizeof(MV_CESA_MBUF); -+ -+ pMbuf->pFrags = (MV_BUF_INFO*)pBuf; -+ -+ pMbuf->numFrags = 1; -+ pCmd->pSrc = pMbuf; -+ pCmd->pDst = pMbuf; -+/* -+ mvOsPrintf("CtrModeInit: pCmd=%p, pSrc=%p, pDst=%p, pFrags=%p\n", -+ pCmd, pCmd->pSrc, pCmd->pDst, -+ pMbuf->pFrags); -+*/ -+ return pCmd; -+} -+ -+/******************************************************************************* -+* mvCesaCtrModePrepare - -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_CESA_COMMAND *pCtrModeCmd, MV_CESA_COMMAND *pCmd -+* -+* RETURN: -+* MV_STATUS -+* -+*******************************************************************************/ -+static MV_STATUS mvCesaCtrModePrepare(MV_CESA_COMMAND *pCtrModeCmd, MV_CESA_COMMAND *pCmd) -+{ -+ MV_CESA_MBUF *pMbuf; -+ MV_U8 *pBuf, *pIV; -+ MV_U32 counter, *pCounter; -+ int cryptoSize = MV_ALIGN_UP(pCmd->cryptoLength, MV_CESA_AES_BLOCK_SIZE); -+/* -+ mvOsPrintf("CtrModePrepare: pCmd=%p, pCtrSrc=%p, pCtrDst=%p, pOrgCmd=%p, pOrgSrc=%p, pOrgDst=%p\n", -+ pCmd, pCmd->pSrc, pCmd->pDst, -+ pCtrModeCmd, pCtrModeCmd->pSrc, pCtrModeCmd->pDst); -+*/ -+ pMbuf = pCtrModeCmd->pSrc; -+ -+ /* Allocate buffer for Key stream */ -+ pBuf = mvOsIoCachedMalloc(cesaOsHandle,cryptoSize, -+ &pMbuf->pFrags[0].bufPhysAddr, -+ &pMbuf->pFrags[0].memHandle); -+ if(pBuf == NULL) -+ { -+ mvOsPrintf("mvCesaCtrModePrepare: Can't allocate %d bytes\n", cryptoSize); -+ return MV_OUT_OF_CPU_MEM; -+ } -+ memset(pBuf, 0, cryptoSize); -+ mvOsCacheFlush(NULL, pBuf, cryptoSize); -+ -+ pMbuf->pFrags[0].bufVirtPtr = pBuf; -+ pMbuf->mbufSize = cryptoSize; -+ pMbuf->pFrags[0].bufSize = cryptoSize; -+ -+ pCtrModeCmd->pReqPrv = pCmd->pReqPrv; -+ pCtrModeCmd->sessionId = pCmd->sessionId; -+ -+ /* ivFromUser and ivOffset are don't care */ -+ pCtrModeCmd->cryptoOffset = 0; -+ pCtrModeCmd->cryptoLength = cryptoSize; -+ -+ /* digestOffset, macOffset and macLength are don't care */ -+ -+ mvCesaCopyFromMbuf(pBuf, pCmd->pSrc, pCmd->ivOffset, MV_CESA_AES_BLOCK_SIZE); -+ pCounter = (MV_U32*)(pBuf + (MV_CESA_AES_BLOCK_SIZE - sizeof(counter))); -+ counter = *pCounter; -+ counter = MV_32BIT_BE(counter); -+ pIV = pBuf; -+ cryptoSize -= MV_CESA_AES_BLOCK_SIZE; -+ -+ /* fill key stream */ -+ while(cryptoSize > 0) -+ { -+ pBuf += MV_CESA_AES_BLOCK_SIZE; -+ memcpy(pBuf, pIV, MV_CESA_AES_BLOCK_SIZE - sizeof(counter)); -+ pCounter = (MV_U32*)(pBuf + (MV_CESA_AES_BLOCK_SIZE - sizeof(counter))); -+ counter++; -+ *pCounter = MV_32BIT_BE(counter); -+ cryptoSize -= MV_CESA_AES_BLOCK_SIZE; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaCtrModeComplete - -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_CESA_COMMAND *pOrgCmd, MV_CESA_COMMAND *pCmd -+* -+* RETURN: -+* MV_STATUS -+* -+*******************************************************************************/ -+static MV_STATUS mvCesaCtrModeComplete(MV_CESA_COMMAND *pOrgCmd, MV_CESA_COMMAND *pCmd) -+{ -+ int srcFrag, dstFrag, srcOffset, dstOffset, keyOffset, srcSize, dstSize; -+ int cryptoSize = pCmd->cryptoLength; -+ MV_U8 *pSrc, *pDst, *pKey; -+ MV_STATUS status = MV_OK; -+/* -+ mvOsPrintf("CtrModeComplete: pCmd=%p, pCtrSrc=%p, pCtrDst=%p, pOrgCmd=%p, pOrgSrc=%p, pOrgDst=%p\n", -+ pCmd, pCmd->pSrc, pCmd->pDst, -+ pOrgCmd, pOrgCmd->pSrc, pOrgCmd->pDst); -+*/ -+ /* XOR source data with key stream to destination data */ -+ pKey = pCmd->pDst->pFrags[0].bufVirtPtr; -+ keyOffset = 0; -+ -+ if( (pOrgCmd->pSrc != pOrgCmd->pDst) && -+ (pOrgCmd->cryptoOffset > 0) ) -+ { -+ /* Copy Prefix from source buffer to destination buffer */ -+ -+ status = mvCesaMbufCopy(pOrgCmd->pDst, 0, -+ pOrgCmd->pSrc, 0, pOrgCmd->cryptoOffset); -+/* -+ status = mvCesaCopyFromMbuf(tempBuf, pOrgCmd->pSrc, -+ 0, pOrgCmd->cryptoOffset); -+ status = mvCesaCopyToMbuf(tempBuf, pOrgCmd->pDst, -+ 0, pOrgCmd->cryptoOffset); -+*/ -+ } -+ -+ srcFrag = mvCesaMbufOffset(pOrgCmd->pSrc, pOrgCmd->cryptoOffset, &srcOffset); -+ pSrc = pOrgCmd->pSrc->pFrags[srcFrag].bufVirtPtr; -+ srcSize = pOrgCmd->pSrc->pFrags[srcFrag].bufSize; -+ -+ dstFrag = mvCesaMbufOffset(pOrgCmd->pDst, pOrgCmd->cryptoOffset, &dstOffset); -+ pDst = pOrgCmd->pDst->pFrags[dstFrag].bufVirtPtr; -+ dstSize = pOrgCmd->pDst->pFrags[dstFrag].bufSize; -+ -+ while(cryptoSize > 0) -+ { -+ pDst[dstOffset] = (pSrc[srcOffset] ^ pKey[keyOffset]); -+ -+ cryptoSize--; -+ dstOffset++; -+ srcOffset++; -+ keyOffset++; -+ -+ if(srcOffset >= srcSize) -+ { -+ srcFrag++; -+ srcOffset = 0; -+ pSrc = pOrgCmd->pSrc->pFrags[srcFrag].bufVirtPtr; -+ srcSize = pOrgCmd->pSrc->pFrags[srcFrag].bufSize; -+ } -+ -+ if(dstOffset >= dstSize) -+ { -+ dstFrag++; -+ dstOffset = 0; -+ pDst = pOrgCmd->pDst->pFrags[dstFrag].bufVirtPtr; -+ dstSize = pOrgCmd->pDst->pFrags[dstFrag].bufSize; -+ } -+ } -+ -+ if(pOrgCmd->pSrc != pOrgCmd->pDst) -+ { -+ /* Copy Suffix from source buffer to destination buffer */ -+ srcOffset = pOrgCmd->cryptoOffset + pOrgCmd->cryptoLength; -+ -+ if( (pOrgCmd->pDst->mbufSize - srcOffset) > 0) -+ { -+ status = mvCesaMbufCopy(pOrgCmd->pDst, srcOffset, -+ pOrgCmd->pSrc, srcOffset, -+ pOrgCmd->pDst->mbufSize - srcOffset); -+ } -+ -+/* -+ status = mvCesaCopyFromMbuf(tempBuf, pOrgCmd->pSrc, -+ srcOffset, pOrgCmd->pSrc->mbufSize - srcOffset); -+ status = mvCesaCopyToMbuf(tempBuf, pOrgCmd->pDst, -+ srcOffset, pOrgCmd->pDst->mbufSize - srcOffset); -+*/ -+ } -+ -+ /* Free buffer used for Key stream */ -+ mvOsIoCachedFree(cesaOsHandle,pCmd->pDst->pFrags[0].bufSize, -+ pCmd->pDst->pFrags[0].bufPhysAddr, -+ pCmd->pDst->pFrags[0].bufVirtPtr, -+ pCmd->pDst->pFrags[0].memHandle); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaCtrModeFinish - -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_CESA_COMMAND* pCmd -+* -+* RETURN: -+* MV_STATUS -+* -+*******************************************************************************/ -+static void mvCesaCtrModeFinish(MV_CESA_COMMAND* pCmd) -+{ -+ mvOsFree(pCmd); -+} -+ -+/******************************************************************************* -+* mvCesaParamCheck - -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, MV_U8* pFixOffset -+* -+* RETURN: -+* MV_STATUS -+* -+*******************************************************************************/ -+static MV_STATUS mvCesaParamCheck(MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, -+ MV_U8* pFixOffset) -+{ -+ MV_U8 fixOffset = 0xFF; -+ -+ /* Check AUTH operation parameters */ -+ if( ((pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET)) ) -+ { -+ /* MAC offset should be at least 4 byte aligned */ -+ if( MV_IS_NOT_ALIGN(pCmd->macOffset, 4) ) -+ { -+ mvOsPrintf("mvCesaAction: macOffset %d must be 4 byte aligned\n", -+ pCmd->macOffset); -+ return MV_BAD_PARAM; -+ } -+ /* Digest offset must be 4 byte aligned */ -+ if( MV_IS_NOT_ALIGN(pCmd->digestOffset, 4) ) -+ { -+ mvOsPrintf("mvCesaAction: digestOffset %d must be 4 byte aligned\n", -+ pCmd->digestOffset); -+ return MV_BAD_PARAM; -+ } -+ /* In addition all offsets should be the same alignment: 8 or 4 */ -+ if(fixOffset == 0xFF) -+ { -+ fixOffset = (pCmd->macOffset % 8); -+ } -+ else -+ { -+ if( (pCmd->macOffset % 8) != fixOffset) -+ { -+ mvOsPrintf("mvCesaAction: macOffset %d mod 8 must be equal %d\n", -+ pCmd->macOffset, fixOffset); -+ return MV_BAD_PARAM; -+ } -+ } -+ if( (pCmd->digestOffset % 8) != fixOffset) -+ { -+ mvOsPrintf("mvCesaAction: digestOffset %d mod 8 must be equal %d\n", -+ pCmd->digestOffset, fixOffset); -+ return MV_BAD_PARAM; -+ } -+ } -+ /* Check CRYPTO operation parameters */ -+ if( ((pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) ) -+ { -+ /* CryptoOffset should be at least 4 byte aligned */ -+ if( MV_IS_NOT_ALIGN(pCmd->cryptoOffset, 4) ) -+ { -+ mvOsPrintf("CesaAction: cryptoOffset=%d must be 4 byte aligned\n", -+ pCmd->cryptoOffset); -+ return MV_BAD_PARAM; -+ } -+ /* cryptoLength should be the whole number of blocks */ -+ if( MV_IS_NOT_ALIGN(pCmd->cryptoLength, pSA->cryptoBlockSize) ) -+ { -+ mvOsPrintf("mvCesaAction: cryptoLength=%d must be %d byte aligned\n", -+ pCmd->cryptoLength, pSA->cryptoBlockSize); -+ return MV_BAD_PARAM; -+ } -+ if(fixOffset == 0xFF) -+ { -+ fixOffset = (pCmd->cryptoOffset % 8); -+ } -+ else -+ { -+ /* In addition all offsets should be the same alignment: 8 or 4 */ -+ if( (pCmd->cryptoOffset % 8) != fixOffset) -+ { -+ mvOsPrintf("mvCesaAction: cryptoOffset %d mod 8 must be equal %d \n", -+ pCmd->cryptoOffset, fixOffset); -+ return MV_BAD_PARAM; -+ } -+ } -+ -+ /* check for CBC mode */ -+ if(pSA->cryptoIvSize > 0) -+ { -+ /* cryptoIV must not be part of CryptoLength */ -+ if( ((pCmd->ivOffset + pSA->cryptoIvSize) > pCmd->cryptoOffset) && -+ (pCmd->ivOffset < (pCmd->cryptoOffset + pCmd->cryptoLength)) ) -+ { -+ mvOsPrintf("mvCesaFragParamCheck: cryptoIvOffset (%d) is part of cryptoLength (%d+%d)\n", -+ pCmd->ivOffset, pCmd->macOffset, pCmd->macLength); -+ return MV_BAD_PARAM; -+ } -+ -+ /* ivOffset must be 4 byte aligned */ -+ if( MV_IS_NOT_ALIGN(pCmd->ivOffset, 4) ) -+ { -+ mvOsPrintf("CesaAction: ivOffset=%d must be 4 byte aligned\n", -+ pCmd->ivOffset); -+ return MV_BAD_PARAM; -+ } -+ /* In addition all offsets should be the same alignment: 8 or 4 */ -+ if( (pCmd->ivOffset % 8) != fixOffset) -+ { -+ mvOsPrintf("mvCesaAction: ivOffset %d mod 8 must be %d\n", -+ pCmd->ivOffset, fixOffset); -+ return MV_BAD_PARAM; -+ } -+ } -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaFragParamCheck - -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd -+* -+* RETURN: -+* MV_STATUS -+* -+*******************************************************************************/ -+static MV_STATUS mvCesaFragParamCheck(MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd) -+{ -+ int offset; -+ -+ if( ((pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET)) ) -+ { -+ /* macOffset must be less that SRAM buffer size */ -+ if(pCmd->macOffset > (sizeof(cesaSramVirtPtr->buf) - MV_CESA_AUTH_BLOCK_SIZE)) -+ { -+ mvOsPrintf("mvCesaFragParamCheck: macOffset is too large (%d)\n", -+ pCmd->macOffset); -+ return MV_BAD_PARAM; -+ } -+ /* macOffset+macSize must be more than mbufSize - SRAM buffer size */ -+ if( ((pCmd->macOffset + pCmd->macLength) > pCmd->pSrc->mbufSize) || -+ ((pCmd->pSrc->mbufSize - (pCmd->macOffset + pCmd->macLength)) >= -+ sizeof(cesaSramVirtPtr->buf)) ) -+ { -+ mvOsPrintf("mvCesaFragParamCheck: macLength is too large (%d), mbufSize=%d\n", -+ pCmd->macLength, pCmd->pSrc->mbufSize); -+ return MV_BAD_PARAM; -+ } -+ } -+ -+ if( ((pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) ) -+ { -+ /* cryptoOffset must be less that SRAM buffer size */ -+ /* 4 for possible fixOffset */ -+ if( (pCmd->cryptoOffset + 4) > (sizeof(cesaSramVirtPtr->buf) - pSA->cryptoBlockSize)) -+ { -+ mvOsPrintf("mvCesaFragParamCheck: cryptoOffset is too large (%d)\n", -+ pCmd->cryptoOffset); -+ return MV_BAD_PARAM; -+ } -+ -+ /* cryptoOffset+cryptoSize must be more than mbufSize - SRAM buffer size */ -+ if( ((pCmd->cryptoOffset + pCmd->cryptoLength) > pCmd->pSrc->mbufSize) || -+ ((pCmd->pSrc->mbufSize - (pCmd->cryptoOffset + pCmd->cryptoLength)) >= -+ (sizeof(cesaSramVirtPtr->buf) - pSA->cryptoBlockSize)) ) -+ { -+ mvOsPrintf("mvCesaFragParamCheck: cryptoLength is too large (%d), mbufSize=%d\n", -+ pCmd->cryptoLength, pCmd->pSrc->mbufSize); -+ return MV_BAD_PARAM; -+ } -+ } -+ -+ /* When MAC_THEN_CRYPTO or CRYPTO_THEN_MAC */ -+ if( ((pSA->config & MV_CESA_OPERATION_MASK) == -+ (MV_CESA_MAC_THEN_CRYPTO << MV_CESA_OPERATION_OFFSET)) || -+ ((pSA->config & MV_CESA_OPERATION_MASK) == -+ (MV_CESA_CRYPTO_THEN_MAC << MV_CESA_OPERATION_OFFSET)) ) -+ { -+ if( (mvCtrlModelGet() == MV_5182_DEV_ID) || -+ ( (mvCtrlModelGet() == MV_5181_DEV_ID) && -+ (mvCtrlRevGet() >= MV_5181L_A0_REV) && -+ (pCmd->macLength >= (1 << 14)) ) ) -+ { -+ return MV_NOT_ALLOWED; -+ } -+ -+ /* abs(cryptoOffset-macOffset) must be aligned cryptoBlockSize */ -+ if(pCmd->cryptoOffset > pCmd->macOffset) -+ { -+ offset = pCmd->cryptoOffset - pCmd->macOffset; -+ } -+ else -+ { -+ offset = pCmd->macOffset - pCmd->cryptoOffset; -+ } -+ -+ if( MV_IS_NOT_ALIGN(offset, pSA->cryptoBlockSize) ) -+ { -+/* -+ mvOsPrintf("mvCesaFragParamCheck: (cryptoOffset - macOffset) must be %d byte aligned\n", -+ pSA->cryptoBlockSize); -+*/ -+ return MV_NOT_ALLOWED; -+ } -+ /* Digest must not be part of CryptoLength */ -+ if( ((pCmd->digestOffset + pSA->digestSize) > pCmd->cryptoOffset) && -+ (pCmd->digestOffset < (pCmd->cryptoOffset + pCmd->cryptoLength)) ) -+ { -+/* -+ mvOsPrintf("mvCesaFragParamCheck: digestOffset (%d) is part of cryptoLength (%d+%d)\n", -+ pCmd->digestOffset, pCmd->cryptoOffset, pCmd->cryptoLength); -+*/ -+ return MV_NOT_ALLOWED; -+ } -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaFragSizeFind - -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, -+* int cryptoOffset, int macOffset, -+* -+* OUTPUT: -+* int* pCopySize, int* pCryptoDataSize, int* pMacDataSize -+* -+* RETURN: -+* MV_STATUS -+* -+*******************************************************************************/ -+static void mvCesaFragSizeFind(MV_CESA_SA* pSA, MV_CESA_REQ* pReq, -+ int cryptoOffset, int macOffset, -+ int* pCopySize, int* pCryptoDataSize, int* pMacDataSize) -+{ -+ MV_CESA_COMMAND *pCmd = pReq->pCmd; -+ int cryptoDataSize, macDataSize, copySize; -+ -+ cryptoDataSize = macDataSize = 0; -+ copySize = *pCopySize; -+ -+ if( (pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ cryptoDataSize = MV_MIN( (copySize - cryptoOffset), -+ (pCmd->cryptoLength - (pReq->frags.cryptoSize + 1)) ); -+ -+ /* cryptoSize for each fragment must be the whole number of blocksSize */ -+ if( MV_IS_NOT_ALIGN(cryptoDataSize, pSA->cryptoBlockSize) ) -+ { -+ cryptoDataSize = MV_ALIGN_DOWN(cryptoDataSize, pSA->cryptoBlockSize); -+ copySize = cryptoOffset + cryptoDataSize; -+ } -+ } -+ if( (pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ macDataSize = MV_MIN( (copySize - macOffset), -+ (pCmd->macLength - (pReq->frags.macSize + 1))); -+ -+ /* macSize for each fragment (except last) must be the whole number of blocksSize */ -+ if( MV_IS_NOT_ALIGN(macDataSize, MV_CESA_AUTH_BLOCK_SIZE) ) -+ { -+ macDataSize = MV_ALIGN_DOWN(macDataSize, MV_CESA_AUTH_BLOCK_SIZE); -+ copySize = macOffset + macDataSize; -+ } -+ cryptoDataSize = copySize - cryptoOffset; -+ } -+ *pCopySize = copySize; -+ -+ if(pCryptoDataSize != NULL) -+ *pCryptoDataSize = cryptoDataSize; -+ -+ if(pMacDataSize != NULL) -+ *pMacDataSize = macDataSize; -+} -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/cesa/mvCesaDebug.c linux-2.6.36/crypto/ocf/kirkwood/cesa/mvCesaDebug.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/cesa/mvCesaDebug.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/cesa/mvCesaDebug.c 2010-11-09 20:28:05.342495385 +0100 -@@ -0,0 +1,484 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "mvOs.h" -+#include "mvDebug.h" -+ -+#include "cesa/mvMD5.h" -+#include "cesa/mvSHA1.h" -+ -+#include "cesa/mvCesa.h" -+#include "cesa/mvCesaRegs.h" -+#include "cesa/AES/mvAes.h" -+ -+static const char* mvCesaDebugStateStr(MV_CESA_STATE state) -+{ -+ switch(state) -+ { -+ case MV_CESA_IDLE: -+ return "Idle"; -+ -+ case MV_CESA_PENDING: -+ return "Pend"; -+ -+ case MV_CESA_PROCESS: -+ return "Proc"; -+ -+ case MV_CESA_READY: -+ return "Ready"; -+ -+ default: -+ break; -+ } -+ return "Unknown"; -+} -+ -+static const char* mvCesaDebugOperStr(MV_CESA_OPERATION oper) -+{ -+ switch(oper) -+ { -+ case MV_CESA_MAC_ONLY: -+ return "MacOnly"; -+ -+ case MV_CESA_CRYPTO_ONLY: -+ return "CryptoOnly"; -+ -+ case MV_CESA_MAC_THEN_CRYPTO: -+ return "MacCrypto"; -+ -+ case MV_CESA_CRYPTO_THEN_MAC: -+ return "CryptoMac"; -+ -+ default: -+ break; -+ } -+ return "Null"; -+} -+ -+static const char* mvCesaDebugCryptoAlgStr(MV_CESA_CRYPTO_ALG cryptoAlg) -+{ -+ switch(cryptoAlg) -+ { -+ case MV_CESA_CRYPTO_DES: -+ return "DES"; -+ -+ case MV_CESA_CRYPTO_3DES: -+ return "3DES"; -+ -+ case MV_CESA_CRYPTO_AES: -+ return "AES"; -+ -+ default: -+ break; -+ } -+ return "Null"; -+} -+ -+static const char* mvCesaDebugMacModeStr(MV_CESA_MAC_MODE macMode) -+{ -+ switch(macMode) -+ { -+ case MV_CESA_MAC_MD5: -+ return "MD5"; -+ -+ case MV_CESA_MAC_SHA1: -+ return "SHA1"; -+ -+ case MV_CESA_MAC_HMAC_MD5: -+ return "HMAC-MD5"; -+ -+ case MV_CESA_MAC_HMAC_SHA1: -+ return "HMAC_SHA1"; -+ -+ default: -+ break; -+ } -+ return "Null"; -+} -+ -+void mvCesaDebugCmd(MV_CESA_COMMAND* pCmd, int mode) -+{ -+ mvOsPrintf("pCmd=%p, pReqPrv=%p, pSrc=%p, pDst=%p, pCB=%p, sid=%d\n", -+ pCmd, pCmd->pReqPrv, pCmd->pSrc, pCmd->pDst, -+ pCmd->pFuncCB, pCmd->sessionId); -+ mvOsPrintf("isUser=%d, ivOffs=%d, crOffs=%d, crLen=%d, digest=%d, macOffs=%d, macLen=%d\n", -+ pCmd->ivFromUser, pCmd->ivOffset, pCmd->cryptoOffset, pCmd->cryptoLength, -+ pCmd->digestOffset, pCmd->macOffset, pCmd->macLength); -+} -+ -+/* no need to use in tool */ -+void mvCesaDebugMbuf(const char* str, MV_CESA_MBUF *pMbuf, int offset, int size) -+{ -+ int frag, len, fragOffset; -+ -+ if(str != NULL) -+ mvOsPrintf("%s: pMbuf=%p, numFrags=%d, mbufSize=%d\n", -+ str, pMbuf, pMbuf->numFrags, pMbuf->mbufSize); -+ -+ frag = mvCesaMbufOffset(pMbuf, offset, &fragOffset); -+ if(frag == MV_INVALID) -+ { -+ mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); -+ return; -+ } -+ -+ for(; fragnumFrags; frag++) -+ { -+ mvOsPrintf("#%2d. bufVirt=%p, bufSize=%d\n", -+ frag, pMbuf->pFrags[frag].bufVirtPtr, -+ pMbuf->pFrags[frag].bufSize); -+ if(size > 0) -+ { -+ len = MV_MIN(pMbuf->pFrags[frag].bufSize, size); -+ mvDebugMemDump(pMbuf->pFrags[frag].bufVirtPtr+fragOffset, len, 1); -+ size -= len; -+ fragOffset = 0; -+ } -+ } -+} -+ -+void mvCesaDebugRegs(void) -+{ -+ mvOsPrintf("\t CESA Registers:\n"); -+ -+ mvOsPrintf("MV_CESA_CMD_REG : 0x%X = 0x%08x\n", -+ MV_CESA_CMD_REG, -+ MV_REG_READ( MV_CESA_CMD_REG ) ); -+ -+ mvOsPrintf("MV_CESA_CHAN_DESC_OFFSET_REG : 0x%X = 0x%08x\n", -+ MV_CESA_CHAN_DESC_OFFSET_REG, -+ MV_REG_READ(MV_CESA_CHAN_DESC_OFFSET_REG) ); -+ -+ mvOsPrintf("MV_CESA_CFG_REG : 0x%X = 0x%08x\n", -+ MV_CESA_CFG_REG, -+ MV_REG_READ( MV_CESA_CFG_REG ) ); -+ -+ mvOsPrintf("MV_CESA_STATUS_REG : 0x%X = 0x%08x\n", -+ MV_CESA_STATUS_REG, -+ MV_REG_READ( MV_CESA_STATUS_REG ) ); -+ -+ mvOsPrintf("MV_CESA_ISR_CAUSE_REG : 0x%X = 0x%08x\n", -+ MV_CESA_ISR_CAUSE_REG, -+ MV_REG_READ( MV_CESA_ISR_CAUSE_REG ) ); -+ -+ mvOsPrintf("MV_CESA_ISR_MASK_REG : 0x%X = 0x%08x\n", -+ MV_CESA_ISR_MASK_REG, -+ MV_REG_READ( MV_CESA_ISR_MASK_REG ) ); -+#if (MV_CESA_VERSION >= 2) -+ mvOsPrintf("MV_CESA_TDMA_CTRL_REG : 0x%X = 0x%08x\n", -+ MV_CESA_TDMA_CTRL_REG, -+ MV_REG_READ( MV_CESA_TDMA_CTRL_REG ) ); -+ -+ mvOsPrintf("MV_CESA_TDMA_BYTE_COUNT_REG : 0x%X = 0x%08x\n", -+ MV_CESA_TDMA_BYTE_COUNT_REG, -+ MV_REG_READ( MV_CESA_TDMA_BYTE_COUNT_REG ) ); -+ -+ mvOsPrintf("MV_CESA_TDMA_SRC_ADDR_REG : 0x%X = 0x%08x\n", -+ MV_CESA_TDMA_SRC_ADDR_REG, -+ MV_REG_READ( MV_CESA_TDMA_SRC_ADDR_REG ) ); -+ -+ mvOsPrintf("MV_CESA_TDMA_DST_ADDR_REG : 0x%X = 0x%08x\n", -+ MV_CESA_TDMA_DST_ADDR_REG, -+ MV_REG_READ( MV_CESA_TDMA_DST_ADDR_REG ) ); -+ -+ mvOsPrintf("MV_CESA_TDMA_NEXT_DESC_PTR_REG : 0x%X = 0x%08x\n", -+ MV_CESA_TDMA_NEXT_DESC_PTR_REG, -+ MV_REG_READ( MV_CESA_TDMA_NEXT_DESC_PTR_REG ) ); -+ -+ mvOsPrintf("MV_CESA_TDMA_CURR_DESC_PTR_REG : 0x%X = 0x%08x\n", -+ MV_CESA_TDMA_CURR_DESC_PTR_REG, -+ MV_REG_READ( MV_CESA_TDMA_CURR_DESC_PTR_REG ) ); -+ -+ mvOsPrintf("MV_CESA_TDMA_ERROR_CAUSE_REG : 0x%X = 0x%08x\n", -+ MV_CESA_TDMA_ERROR_CAUSE_REG, -+ MV_REG_READ( MV_CESA_TDMA_ERROR_CAUSE_REG ) ); -+ -+ mvOsPrintf("MV_CESA_TDMA_ERROR_MASK_REG : 0x%X = 0x%08x\n", -+ MV_CESA_TDMA_ERROR_MASK_REG, -+ MV_REG_READ( MV_CESA_TDMA_ERROR_CAUSE_REG ) ); -+ -+#endif -+} -+ -+void mvCesaDebugStatus(void) -+{ -+ mvOsPrintf("\n\t CESA Status\n\n"); -+ -+ mvOsPrintf("pReqQ=%p, qDepth=%d, reqSize=%ld bytes, qRes=%d, ", -+ pCesaReqFirst, cesaQueueDepth, sizeof(MV_CESA_REQ), -+ cesaReqResources); -+#if (MV_CESA_VERSION >= 3) -+ mvOsPrintf("chainLength=%u\n",cesaChainLength); -+#else -+ mvOsPrintf("\n"); -+#endif -+ -+ mvOsPrintf("pSAD=%p, maxSA=%d, sizeSA=%ld bytes\n", -+ pCesaSAD, cesaMaxSA, sizeof(MV_CESA_SA)); -+ -+ mvOsPrintf("\n"); -+ -+ mvCesaDebugRegs(); -+ mvCesaDebugStats(); -+ mvCesaDebugStatsClear(); -+} -+ -+void mvCesaDebugDescriptor(MV_CESA_DESC* pDesc) -+{ -+ mvOsPrintf("config=0x%08x, crSrcOffs=0x%04x, crDstOffs=0x%04x\n", -+ pDesc->config, pDesc->cryptoSrcOffset, pDesc->cryptoDstOffset); -+ -+ mvOsPrintf("crLen=0x%04x, crKeyOffs=0x%04x, ivOffs=0x%04x, ivBufOffs=0x%04x\n", -+ pDesc->cryptoDataLen, pDesc->cryptoKeyOffset, -+ pDesc->cryptoIvOffset, pDesc->cryptoIvBufOffset); -+ -+ mvOsPrintf("macSrc=0x%04x, digest=0x%04x, macLen=0x%04x, inIv=0x%04x, outIv=0x%04x\n", -+ pDesc->macSrcOffset, pDesc->macDigestOffset, pDesc->macDataLen, -+ pDesc->macInnerIvOffset, pDesc->macOuterIvOffset); -+} -+ -+void mvCesaDebugQueue(int mode) -+{ -+ mvOsPrintf("\n\t CESA Request Queue:\n\n"); -+ -+ mvOsPrintf("pFirstReq=%p, pLastReq=%p, qDepth=%d, reqSize=%ld bytes\n", -+ pCesaReqFirst, pCesaReqLast, cesaQueueDepth, sizeof(MV_CESA_REQ)); -+ -+ mvOsPrintf("pEmpty=%p, pProcess=%p, qResources=%d\n", -+ pCesaReqEmpty, pCesaReqProcess, -+ cesaReqResources); -+ -+ if(mode != 0) -+ { -+ int count = 0; -+ MV_CESA_REQ* pReq = pCesaReqFirst; -+ -+ for(count=0; countstate), -+ pReq->fragMode, pReq->pCmd, pReq->dma[0].pDmaFirst, &pReq->pCesaDesc[0]); -+ if(pReq->fragMode != MV_CESA_FRAG_NONE) -+ { -+ int frag; -+ -+ mvOsPrintf("pFrags=%p, num=%d, next=%d, bufOffset=%d, cryptoSize=%d, macSize=%d\n", -+ &pReq->frags, pReq->frags.numFrag, pReq->frags.nextFrag, -+ pReq->frags.bufOffset, pReq->frags.cryptoSize, pReq->frags.macSize); -+ for(frag=0; fragfrags.numFrag; frag++) -+ { -+ mvOsPrintf("#%d: pDmaFirst=%p, pDesc=%p\n", frag, -+ pReq->dma[frag].pDmaFirst, &pReq->pCesaDesc[frag]); -+ } -+ } -+ if(mode > 1) -+ { -+ /* Print out Command */ -+ mvCesaDebugCmd(pReq->pCmd, mode); -+ -+ /* Print out Descriptor */ -+ mvCesaDebugDescriptor(&pReq->pCesaDesc[0]); -+ } -+ pReq++; -+ } -+ } -+} -+ -+ -+void mvCesaDebugSramSA(MV_CESA_SRAM_SA* pSramSA, int mode) -+{ -+ if(pSramSA == NULL) -+ { -+ mvOsPrintf("cesaSramSA: Unexpected pSramSA=%p\n", pSramSA); -+ return; -+ } -+ mvOsPrintf("pSramSA=%p, sizeSramSA=%ld bytes\n", -+ pSramSA, sizeof(MV_CESA_SRAM_SA)); -+ -+ if(mode != 0) -+ { -+ mvOsPrintf("cryptoKey=%p, maxCryptoKey=%d bytes\n", -+ pSramSA->cryptoKey, MV_CESA_MAX_CRYPTO_KEY_LENGTH); -+ mvDebugMemDump(pSramSA->cryptoKey, MV_CESA_MAX_CRYPTO_KEY_LENGTH, 1); -+ -+ mvOsPrintf("macInnerIV=%p, maxInnerIV=%d bytes\n", -+ pSramSA->macInnerIV, MV_CESA_MAX_DIGEST_SIZE); -+ mvDebugMemDump(pSramSA->macInnerIV, MV_CESA_MAX_DIGEST_SIZE, 1); -+ -+ mvOsPrintf("macOuterIV=%p, maxOuterIV=%d bytes\n", -+ pSramSA->macOuterIV, MV_CESA_MAX_DIGEST_SIZE); -+ mvDebugMemDump(pSramSA->macOuterIV, MV_CESA_MAX_DIGEST_SIZE, 1); -+ } -+} -+ -+void mvCesaDebugSA(short sid, int mode) -+{ -+ MV_CESA_OPERATION oper; -+ MV_CESA_DIRECTION dir; -+ MV_CESA_CRYPTO_ALG cryptoAlg; -+ MV_CESA_CRYPTO_MODE cryptoMode; -+ MV_CESA_MAC_MODE macMode; -+ MV_CESA_SA* pSA = &pCesaSAD[sid]; -+ -+ if( (pSA->valid) || ((pSA->count != 0) && (mode > 0)) || (mode >= 2) ) -+ { -+ mvOsPrintf("\n\nCESA SA Entry #%d (%p) - %s (count=%d)\n", -+ sid, pSA, -+ pSA->valid ? "Valid" : "Invalid", pSA->count); -+ -+ oper = (pSA->config & MV_CESA_OPERATION_MASK) >> MV_CESA_OPERATION_OFFSET; -+ dir = (pSA->config & MV_CESA_DIRECTION_MASK) >> MV_CESA_DIRECTION_BIT; -+ mvOsPrintf("%s - %s ", mvCesaDebugOperStr(oper), -+ (dir == MV_CESA_DIR_ENCODE) ? "Encode" : "Decode"); -+ if(oper != MV_CESA_MAC_ONLY) -+ { -+ cryptoAlg = (pSA->config & MV_CESA_CRYPTO_ALG_MASK) >> MV_CESA_CRYPTO_ALG_OFFSET; -+ cryptoMode = (pSA->config & MV_CESA_CRYPTO_MODE_MASK) >> MV_CESA_CRYPTO_MODE_BIT; -+ mvOsPrintf("- %s - %s ", mvCesaDebugCryptoAlgStr(cryptoAlg), -+ (cryptoMode == MV_CESA_CRYPTO_ECB) ? "ECB" : "CBC"); -+ } -+ if(oper != MV_CESA_CRYPTO_ONLY) -+ { -+ macMode = (pSA->config & MV_CESA_MAC_MODE_MASK) >> MV_CESA_MAC_MODE_OFFSET; -+ mvOsPrintf("- %s ", mvCesaDebugMacModeStr(macMode)); -+ } -+ mvOsPrintf("\n"); -+ -+ if(mode > 0) -+ { -+ mvOsPrintf("config=0x%08x, cryptoKeySize=%d, digestSize=%d\n", -+ pCesaSAD[sid].config, pCesaSAD[sid].cryptoKeyLength, -+ pCesaSAD[sid].digestSize); -+ -+ mvCesaDebugSramSA(pCesaSAD[sid].pSramSA, mode); -+ } -+ } -+} -+ -+ -+/**/ -+void mvCesaDebugSram(int mode) -+{ -+ mvOsPrintf("\n\t SRAM contents: size=%ld, pVirt=%p\n\n", -+ sizeof(MV_CESA_SRAM_MAP), cesaSramVirtPtr); -+ -+ mvOsPrintf("\n\t Sram buffer: size=%d, pVirt=%p\n", -+ MV_CESA_MAX_BUF_SIZE, cesaSramVirtPtr->buf); -+ if(mode != 0) -+ mvDebugMemDump(cesaSramVirtPtr->buf, 64, 1); -+ -+ mvOsPrintf("\n"); -+ mvOsPrintf("\n\t Sram descriptor: size=%ld, pVirt=%p\n", -+ sizeof(MV_CESA_DESC), &cesaSramVirtPtr->desc); -+ if(mode != 0) -+ { -+ mvOsPrintf("\n"); -+ mvCesaDebugDescriptor(&cesaSramVirtPtr->desc); -+ } -+ mvOsPrintf("\n\t Sram IV: size=%d, pVirt=%p\n", -+ MV_CESA_MAX_IV_LENGTH, &cesaSramVirtPtr->cryptoIV); -+ if(mode != 0) -+ { -+ mvOsPrintf("\n"); -+ mvDebugMemDump(cesaSramVirtPtr->cryptoIV, MV_CESA_MAX_IV_LENGTH, 1); -+ } -+ mvOsPrintf("\n"); -+ mvCesaDebugSramSA(&cesaSramVirtPtr->sramSA, 0); -+} -+ -+void mvCesaDebugSAD(int mode) -+{ -+ int sid; -+ -+ mvOsPrintf("\n\t Cesa SAD status: pSAD=%p, maxSA=%d\n", -+ pCesaSAD, cesaMaxSA); -+ -+ for(sid=0; sid= 3) -+ mvOsPrintf("maxChainUsage=%u\n",cesaStats.maxChainUsage); -+#endif -+ mvOsPrintf("\n"); -+ mvOsPrintf("proc=%u, ready=%u, notReady=%u\n", -+ cesaStats.procCount, cesaStats.readyCount, cesaStats.notReadyCount); -+} -+ -+void mvCesaDebugStatsClear(void) -+{ -+ memset(&cesaStats, 0, sizeof(cesaStats)); -+} -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/cesa/mvCesa.h linux-2.6.36/crypto/ocf/kirkwood/cesa/mvCesa.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/cesa/mvCesa.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/cesa/mvCesa.h 2010-11-09 20:28:05.737859537 +0100 -@@ -0,0 +1,412 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+/******************************************************************************* -+* mvCesa.h - Header File for Cryptographic Engines and Security Accelerator -+* -+* DESCRIPTION: -+* This header file contains macros typedefs and function declaration for -+* the Marvell Cryptographic Engines and Security Accelerator. -+* -+*******************************************************************************/ -+ -+#ifndef __mvCesa_h__ -+#define __mvCesa_h__ -+ -+#include "mvOs.h" -+#include "mvCommon.h" -+#include "mvDebug.h" -+ -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+ -+#include "cesa/mvMD5.h" -+#include "cesa/mvSHA1.h" -+ -+#include "cesa/mvCesa.h" -+#include "cesa/AES/mvAes.h" -+#include "mvSysHwConfig.h" -+ -+#ifdef MV_INCLUDE_IDMA -+#include "idma/mvIdma.h" -+#include "idma/mvIdmaRegs.h" -+#else -+/* Redefine MV_DMA_DESC structure */ -+typedef struct _mvDmaDesc -+{ -+ MV_U32 byteCnt; /* The total number of bytes to transfer */ -+ MV_U32 phySrcAdd; /* The physical source address */ -+ MV_U32 phyDestAdd; /* The physical destination address */ -+ MV_U32 phyNextDescPtr; /* If we are using chain mode DMA transfer, */ -+ /* then this pointer should point to the */ -+ /* physical address of the next descriptor, */ -+ /* otherwise it should be NULL. */ -+}MV_DMA_DESC; -+#endif /* MV_INCLUDE_IDMA */ -+ -+#include "cesa/mvCesaRegs.h" -+ -+#define MV_CESA_AUTH_BLOCK_SIZE 64 /* bytes */ -+ -+#define MV_CESA_MD5_DIGEST_SIZE 16 /* bytes */ -+#define MV_CESA_SHA1_DIGEST_SIZE 20 /* bytes */ -+ -+#define MV_CESA_MAX_DIGEST_SIZE MV_CESA_SHA1_DIGEST_SIZE -+ -+#define MV_CESA_DES_KEY_LENGTH 8 /* bytes = 64 bits */ -+#define MV_CESA_3DES_KEY_LENGTH 24 /* bytes = 192 bits */ -+#define MV_CESA_AES_128_KEY_LENGTH 16 /* bytes = 128 bits */ -+#define MV_CESA_AES_192_KEY_LENGTH 24 /* bytes = 192 bits */ -+#define MV_CESA_AES_256_KEY_LENGTH 32 /* bytes = 256 bits */ -+ -+#define MV_CESA_MAX_CRYPTO_KEY_LENGTH MV_CESA_AES_256_KEY_LENGTH -+ -+#define MV_CESA_DES_BLOCK_SIZE 8 /* bytes = 64 bits */ -+#define MV_CESA_3DES_BLOCK_SIZE 8 /* bytes = 64 bits */ -+ -+#define MV_CESA_AES_BLOCK_SIZE 16 /* bytes = 128 bits */ -+ -+#define MV_CESA_MAX_IV_LENGTH MV_CESA_AES_BLOCK_SIZE -+ -+#define MV_CESA_MAX_MAC_KEY_LENGTH 64 /* bytes */ -+ -+typedef struct -+{ -+ MV_U8 cryptoKey[MV_CESA_MAX_CRYPTO_KEY_LENGTH]; -+ MV_U8 macKey[MV_CESA_MAX_MAC_KEY_LENGTH]; -+ MV_CESA_OPERATION operation; -+ MV_CESA_DIRECTION direction; -+ MV_CESA_CRYPTO_ALG cryptoAlgorithm; -+ MV_CESA_CRYPTO_MODE cryptoMode; -+ MV_U8 cryptoKeyLength; -+ MV_CESA_MAC_MODE macMode; -+ MV_U8 macKeyLength; -+ MV_U8 digestSize; -+ -+} MV_CESA_OPEN_SESSION; -+ -+typedef struct -+{ -+ MV_BUF_INFO *pFrags; -+ MV_U16 numFrags; -+ MV_U16 mbufSize; -+ -+} MV_CESA_MBUF; -+ -+typedef struct -+{ -+ void* pReqPrv; /* instead of reqId */ -+ MV_U32 retCode; -+ MV_16 sessionId; -+ -+} MV_CESA_RESULT; -+ -+typedef void (*MV_CESA_CALLBACK) (MV_CESA_RESULT* pResult); -+ -+ -+typedef struct -+{ -+ void* pReqPrv; /* instead of reqId */ -+ MV_CESA_MBUF* pSrc; -+ MV_CESA_MBUF* pDst; -+ MV_CESA_CALLBACK* pFuncCB; -+ MV_16 sessionId; -+ MV_U16 ivFromUser; -+ MV_U16 ivOffset; -+ MV_U16 cryptoOffset; -+ MV_U16 cryptoLength; -+ MV_U16 digestOffset; -+ MV_U16 macOffset; -+ MV_U16 macLength; -+ MV_BOOL skipFlush; -+} MV_CESA_COMMAND; -+ -+ -+ -+MV_STATUS mvCesaHalInit (int numOfSession, int queueDepth, char* pSramBase, MV_U32 cryptEngBase, void *osHandle); -+MV_STATUS mvCesaFinish (void); -+MV_STATUS mvCesaSessionOpen(MV_CESA_OPEN_SESSION *pSession, short* pSid); -+MV_STATUS mvCesaSessionClose(short sid); -+MV_STATUS mvCesaCryptoIvSet(MV_U8* pIV, int ivSize); -+ -+MV_STATUS mvCesaAction (MV_CESA_COMMAND* pCmd); -+ -+MV_U32 mvCesaInProcessGet(void); -+MV_STATUS mvCesaReadyDispatch(void); -+MV_STATUS mvCesaReadyGet(MV_CESA_RESULT* pResult); -+MV_BOOL mvCesaIsReady(void); -+ -+int mvCesaMbufOffset(MV_CESA_MBUF* pMbuf, int offset, int* pBufOffset); -+MV_STATUS mvCesaCopyFromMbuf(MV_U8* pDst, MV_CESA_MBUF* pSrcMbuf, -+ int offset, int size); -+MV_STATUS mvCesaCopyToMbuf(MV_U8* pSrc, MV_CESA_MBUF* pDstMbuf, -+ int offset, int size); -+MV_STATUS mvCesaMbufCopy(MV_CESA_MBUF* pMbufDst, int dstMbufOffset, -+ MV_CESA_MBUF* pMbufSrc, int srcMbufOffset, int size); -+ -+/********** Debug functions ********/ -+ -+void mvCesaDebugMbuf(const char* str, MV_CESA_MBUF *pMbuf, int offset, int size); -+void mvCesaDebugSA(short sid, int mode); -+void mvCesaDebugStats(void); -+void mvCesaDebugStatsClear(void); -+void mvCesaDebugRegs(void); -+void mvCesaDebugStatus(void); -+void mvCesaDebugQueue(int mode); -+void mvCesaDebugSram(int mode); -+void mvCesaDebugSAD(int mode); -+ -+ -+/******** CESA Private definitions ********/ -+#if (MV_CESA_VERSION >= 2) -+#if (MV_CACHE_COHERENCY == MV_CACHE_COHER_SW) -+#define MV_CESA_TDMA_CTRL_VALUE MV_CESA_TDMA_DST_BURST_MASK(MV_CESA_TDMA_BURST_128B) \ -+ | MV_CESA_TDMA_SRC_BURST_MASK(MV_CESA_TDMA_BURST_128B) \ -+ | MV_CESA_TDMA_OUTSTAND_READ_EN_MASK \ -+ | MV_CESA_TDMA_NO_BYTE_SWAP_MASK \ -+ | MV_CESA_TDMA_ENABLE_MASK -+#else -+#define MV_CESA_TDMA_CTRL_VALUE MV_CESA_TDMA_DST_BURST_MASK(MV_CESA_TDMA_BURST_32B) \ -+ | MV_CESA_TDMA_SRC_BURST_MASK(MV_CESA_TDMA_BURST_128B) \ -+ /*| MV_CESA_TDMA_OUTSTAND_READ_EN_MASK */\ -+ | MV_CESA_TDMA_ENABLE_MASK -+ -+#endif -+#else -+#define MV_CESA_IDMA_CTRL_LOW_VALUE ICCLR_DST_BURST_LIM_128BYTE \ -+ | ICCLR_SRC_BURST_LIM_128BYTE \ -+ | ICCLR_INT_MODE_MASK \ -+ | ICCLR_BLOCK_MODE \ -+ | ICCLR_CHAN_ENABLE \ -+ | ICCLR_DESC_MODE_16M -+#endif /* MV_CESA_VERSION >= 2 */ -+ -+#define MV_CESA_MAX_PKT_SIZE (64 * 1024) -+#define MV_CESA_MAX_MBUF_FRAGS 20 -+ -+#define MV_CESA_MAX_REQ_FRAGS ( (MV_CESA_MAX_PKT_SIZE / MV_CESA_MAX_BUF_SIZE) + 1) -+ -+#define MV_CESA_MAX_DMA_DESC (MV_CESA_MAX_MBUF_FRAGS*2 + 5) -+ -+#define MAX_CESA_CHAIN_LENGTH 20 -+ -+typedef enum -+{ -+ MV_CESA_IDLE = 0, -+ MV_CESA_PENDING, -+ MV_CESA_PROCESS, -+ MV_CESA_READY, -+#if (MV_CESA_VERSION >= 3) -+ MV_CESA_CHAIN, -+#endif -+} MV_CESA_STATE; -+ -+ -+/* Session database */ -+ -+/* Map of Key materials of the session in SRAM. -+ * Each field must be 8 byte aligned -+ * Total size: 32 + 24 + 24 = 80 bytes -+ */ -+typedef struct -+{ -+ MV_U8 cryptoKey[MV_CESA_MAX_CRYPTO_KEY_LENGTH]; -+ MV_U8 macInnerIV[MV_CESA_MAX_DIGEST_SIZE]; -+ MV_U8 reservedInner[4]; -+ MV_U8 macOuterIV[MV_CESA_MAX_DIGEST_SIZE]; -+ MV_U8 reservedOuter[4]; -+ -+} MV_CESA_SRAM_SA; -+ -+typedef struct -+{ -+ MV_CESA_SRAM_SA* pSramSA; -+ MV_U32 config; -+ MV_U8 cryptoKeyLength; -+ MV_U8 cryptoIvSize; -+ MV_U8 cryptoBlockSize; -+ MV_U8 digestSize; -+ MV_U8 macKeyLength; -+ MV_U8 valid; -+ MV_U8 ctrMode; -+ MV_U32 count; -+ -+} MV_CESA_SA; -+ -+/* DMA list management */ -+typedef struct -+{ -+ MV_DMA_DESC* pDmaFirst; -+ MV_DMA_DESC* pDmaLast; -+ -+} MV_CESA_DMA; -+ -+ -+typedef struct -+{ -+ MV_U8 numFrag; -+ MV_U8 nextFrag; -+ int bufOffset; -+ int cryptoSize; -+ int macSize; -+ int newDigestOffset; -+ MV_U8 orgDigest[MV_CESA_MAX_DIGEST_SIZE]; -+ -+} MV_CESA_FRAGS; -+ -+/* Request queue */ -+typedef struct -+{ -+ MV_U8 state; -+ MV_U8 fragMode; -+ MV_U8 fixOffset; -+ MV_CESA_COMMAND* pCmd; -+ MV_CESA_COMMAND* pOrgCmd; -+ MV_BUF_INFO dmaDescBuf; -+ MV_CESA_DMA dma[MV_CESA_MAX_REQ_FRAGS]; -+ MV_BUF_INFO cesaDescBuf; -+ MV_CESA_DESC* pCesaDesc; -+ MV_CESA_FRAGS frags; -+ -+ -+} MV_CESA_REQ; -+ -+ -+/* SRAM map */ -+/* Total SRAM size calculation */ -+/* SRAM size = -+ * MV_CESA_MAX_BUF_SIZE + -+ * sizeof(MV_CESA_DESC) + -+ * MV_CESA_MAX_IV_LENGTH + -+ * MV_CESA_MAX_IV_LENGTH + -+ * MV_CESA_MAX_DIGEST_SIZE + -+ * sizeof(MV_CESA_SRAM_SA) -+ * = 1600 + 32 + 16 + 16 + 24 + 80 + 280 (reserved) = 2048 bytes -+ * = 3200 + 32 + 16 + 16 + 24 + 80 + 728 (reserved) = 4096 bytes -+ */ -+typedef struct -+{ -+ MV_U8 buf[MV_CESA_MAX_BUF_SIZE]; -+ MV_CESA_DESC desc; -+ MV_U8 cryptoIV[MV_CESA_MAX_IV_LENGTH]; -+ MV_U8 tempCryptoIV[MV_CESA_MAX_IV_LENGTH]; -+ MV_U8 tempDigest[MV_CESA_MAX_DIGEST_SIZE+4]; -+ MV_CESA_SRAM_SA sramSA; -+ -+} MV_CESA_SRAM_MAP; -+ -+ -+typedef struct -+{ -+ MV_U32 openedCount; -+ MV_U32 closedCount; -+ MV_U32 fragCount; -+ MV_U32 reqCount; -+ MV_U32 maxReqCount; -+ MV_U32 procCount; -+ MV_U32 readyCount; -+ MV_U32 notReadyCount; -+ MV_U32 startCount; -+#if (MV_CESA_VERSION >= 3) -+ MV_U32 maxChainUsage; -+#endif -+ -+} MV_CESA_STATS; -+ -+ -+/* External variables */ -+ -+extern MV_CESA_STATS cesaStats; -+extern MV_CESA_FRAGS cesaFrags; -+ -+extern MV_BUF_INFO cesaSramSaBuf; -+ -+extern MV_CESA_SA* pCesaSAD; -+extern MV_U16 cesaMaxSA; -+ -+extern MV_CESA_REQ* pCesaReqFirst; -+extern MV_CESA_REQ* pCesaReqLast; -+extern MV_CESA_REQ* pCesaReqEmpty; -+extern MV_CESA_REQ* pCesaReqProcess; -+extern int cesaQueueDepth; -+extern int cesaReqResources; -+#if (MV_CESA_VERSION>= 3) -+extern MV_U32 cesaChainLength; -+#endif -+ -+extern MV_CESA_SRAM_MAP* cesaSramVirtPtr; -+extern MV_U32 cesaSramPhysAddr; -+ -+static INLINE MV_ULONG mvCesaVirtToPhys(MV_BUF_INFO* pBufInfo, void* pVirt) -+{ -+ return (pBufInfo->bufPhysAddr + ((MV_U8*)pVirt - pBufInfo->bufVirtPtr)); -+} -+ -+/* Additional DEBUG functions */ -+void mvCesaDebugSramSA(MV_CESA_SRAM_SA* pSramSA, int mode); -+void mvCesaDebugCmd(MV_CESA_COMMAND* pCmd, int mode); -+void mvCesaDebugDescriptor(MV_CESA_DESC* pDesc); -+ -+ -+ -+#endif /* __mvCesa_h__ */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/cesa/mvCesaRegs.h linux-2.6.36/crypto/ocf/kirkwood/cesa/mvCesaRegs.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/cesa/mvCesaRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/cesa/mvCesaRegs.h 2010-11-09 20:28:05.772495441 +0100 -@@ -0,0 +1,357 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __mvCesaRegs_h__ -+#define __mvCesaRegs_h__ -+ -+#include "mvTypes.h" -+ -+typedef struct -+{ -+ /* word 0 */ -+ MV_U32 config; -+ /* word 1 */ -+ MV_U16 cryptoSrcOffset; -+ MV_U16 cryptoDstOffset; -+ /* word 2 */ -+ MV_U16 cryptoDataLen; -+ MV_U16 reserved1; -+ /* word 3 */ -+ MV_U16 cryptoKeyOffset; -+ MV_U16 reserved2; -+ /* word 4 */ -+ MV_U16 cryptoIvOffset; -+ MV_U16 cryptoIvBufOffset; -+ /* word 5 */ -+ MV_U16 macSrcOffset; -+ MV_U16 macTotalLen; -+ /* word 6 */ -+ MV_U16 macDigestOffset; -+ MV_U16 macDataLen; -+ /* word 7 */ -+ MV_U16 macInnerIvOffset; -+ MV_U16 macOuterIvOffset; -+ -+} MV_CESA_DESC; -+ -+/* operation */ -+typedef enum -+{ -+ MV_CESA_MAC_ONLY = 0, -+ MV_CESA_CRYPTO_ONLY = 1, -+ MV_CESA_MAC_THEN_CRYPTO = 2, -+ MV_CESA_CRYPTO_THEN_MAC = 3, -+ -+ MV_CESA_MAX_OPERATION -+ -+} MV_CESA_OPERATION; -+ -+#define MV_CESA_OPERATION_OFFSET 0 -+#define MV_CESA_OPERATION_MASK (0x3 << MV_CESA_OPERATION_OFFSET) -+ -+/* mac algorithm */ -+typedef enum -+{ -+ MV_CESA_MAC_NULL = 0, -+ MV_CESA_MAC_MD5 = 4, -+ MV_CESA_MAC_SHA1 = 5, -+ MV_CESA_MAC_HMAC_MD5 = 6, -+ MV_CESA_MAC_HMAC_SHA1 = 7, -+ -+} MV_CESA_MAC_MODE; -+ -+#define MV_CESA_MAC_MODE_OFFSET 4 -+#define MV_CESA_MAC_MODE_MASK (0x7 << MV_CESA_MAC_MODE_OFFSET) -+ -+typedef enum -+{ -+ MV_CESA_MAC_DIGEST_FULL = 0, -+ MV_CESA_MAC_DIGEST_96B = 1, -+ -+} MV_CESA_MAC_DIGEST_SIZE; -+ -+#define MV_CESA_MAC_DIGEST_SIZE_BIT 7 -+#define MV_CESA_MAC_DIGEST_SIZE_MASK (1 << MV_CESA_MAC_DIGEST_SIZE_BIT) -+ -+ -+typedef enum -+{ -+ MV_CESA_CRYPTO_NULL = 0, -+ MV_CESA_CRYPTO_DES = 1, -+ MV_CESA_CRYPTO_3DES = 2, -+ MV_CESA_CRYPTO_AES = 3, -+ -+} MV_CESA_CRYPTO_ALG; -+ -+#define MV_CESA_CRYPTO_ALG_OFFSET 8 -+#define MV_CESA_CRYPTO_ALG_MASK (0x3 << MV_CESA_CRYPTO_ALG_OFFSET) -+ -+ -+/* direction */ -+typedef enum -+{ -+ MV_CESA_DIR_ENCODE = 0, -+ MV_CESA_DIR_DECODE = 1, -+ -+} MV_CESA_DIRECTION; -+ -+#define MV_CESA_DIRECTION_BIT 12 -+#define MV_CESA_DIRECTION_MASK (1 << MV_CESA_DIRECTION_BIT) -+ -+/* crypto IV mode */ -+typedef enum -+{ -+ MV_CESA_CRYPTO_ECB = 0, -+ MV_CESA_CRYPTO_CBC = 1, -+ -+ /* NO HW Support */ -+ MV_CESA_CRYPTO_CTR = 10, -+ -+} MV_CESA_CRYPTO_MODE; -+ -+#define MV_CESA_CRYPTO_MODE_BIT 16 -+#define MV_CESA_CRYPTO_MODE_MASK (1 << MV_CESA_CRYPTO_MODE_BIT) -+ -+/* 3DES mode */ -+typedef enum -+{ -+ MV_CESA_CRYPTO_3DES_EEE = 0, -+ MV_CESA_CRYPTO_3DES_EDE = 1, -+ -+} MV_CESA_CRYPTO_3DES_MODE; -+ -+#define MV_CESA_CRYPTO_3DES_MODE_BIT 20 -+#define MV_CESA_CRYPTO_3DES_MODE_MASK (1 << MV_CESA_CRYPTO_3DES_MODE_BIT) -+ -+ -+/* AES Key Length */ -+typedef enum -+{ -+ MV_CESA_CRYPTO_AES_KEY_128 = 0, -+ MV_CESA_CRYPTO_AES_KEY_192 = 1, -+ MV_CESA_CRYPTO_AES_KEY_256 = 2, -+ -+} MV_CESA_CRYPTO_AES_KEY_LEN; -+ -+#define MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET 24 -+#define MV_CESA_CRYPTO_AES_KEY_LEN_MASK (0x3 << MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET) -+ -+/* Fragmentation mode */ -+typedef enum -+{ -+ MV_CESA_FRAG_NONE = 0, -+ MV_CESA_FRAG_FIRST = 1, -+ MV_CESA_FRAG_LAST = 2, -+ MV_CESA_FRAG_MIDDLE = 3, -+ -+} MV_CESA_FRAG_MODE; -+ -+#define MV_CESA_FRAG_MODE_OFFSET 30 -+#define MV_CESA_FRAG_MODE_MASK (0x3 << MV_CESA_FRAG_MODE_OFFSET) -+/*---------------------------------------------------------------------------*/ -+ -+/********** Security Accelerator Command Register **************/ -+#define MV_CESA_CMD_REG (MV_CESA_REG_BASE + 0xE00) -+ -+#define MV_CESA_CMD_CHAN_ENABLE_BIT 0 -+#define MV_CESA_CMD_CHAN_ENABLE_MASK (1 << MV_CESA_CMD_CHAN_ENABLE_BIT) -+ -+#define MV_CESA_CMD_CHAN_DISABLE_BIT 2 -+#define MV_CESA_CMD_CHAN_DISABLE_MASK (1 << MV_CESA_CMD_CHAN_DISABLE_BIT) -+ -+/********** Security Accelerator Descriptor Pointers Register **********/ -+#define MV_CESA_CHAN_DESC_OFFSET_REG (MV_CESA_REG_BASE + 0xE04) -+ -+/********** Security Accelerator Configuration Register **********/ -+#define MV_CESA_CFG_REG (MV_CESA_REG_BASE + 0xE08) -+ -+#define MV_CESA_CFG_STOP_DIGEST_ERR_BIT 0 -+#define MV_CESA_CFG_STOP_DIGEST_ERR_MASK (1 << MV_CESA_CFG_STOP_DIGEST_ERR_BIT) -+ -+#define MV_CESA_CFG_WAIT_DMA_BIT 7 -+#define MV_CESA_CFG_WAIT_DMA_MASK (1 << MV_CESA_CFG_WAIT_DMA_BIT) -+ -+#define MV_CESA_CFG_ACT_DMA_BIT 9 -+#define MV_CESA_CFG_ACT_DMA_MASK (1 << MV_CESA_CFG_ACT_DMA_BIT) -+ -+#define MV_CESA_CFG_CHAIN_MODE_BIT 11 -+#define MV_CESA_CFG_CHAIN_MODE_MASK (1 << MV_CESA_CFG_CHAIN_MODE_BIT) -+ -+/********** Security Accelerator Status Register ***********/ -+#define MV_CESA_STATUS_REG (MV_CESA_REG_BASE + 0xE0C) -+ -+#define MV_CESA_STATUS_ACTIVE_BIT 0 -+#define MV_CESA_STATUS_ACTIVE_MASK (1 << MV_CESA_STATUS_ACTIVE_BIT) -+ -+#define MV_CESA_STATUS_DIGEST_ERR_BIT 8 -+#define MV_CESA_STATUS_DIGEST_ERR_MASK (1 << MV_CESA_STATUS_DIGEST_ERR_BIT) -+ -+ -+/* Cryptographic Engines and Security Accelerator Interrupt Cause Register */ -+#define MV_CESA_ISR_CAUSE_REG (MV_CESA_REG_BASE + 0xE20) -+ -+/* Cryptographic Engines and Security Accelerator Interrupt Mask Register */ -+#define MV_CESA_ISR_MASK_REG (MV_CESA_REG_BASE + 0xE24) -+ -+#define MV_CESA_CAUSE_AUTH_MASK (1 << 0) -+#define MV_CESA_CAUSE_DES_MASK (1 << 1) -+#define MV_CESA_CAUSE_AES_ENCR_MASK (1 << 2) -+#define MV_CESA_CAUSE_AES_DECR_MASK (1 << 3) -+#define MV_CESA_CAUSE_DES_ALL_MASK (1 << 4) -+ -+#define MV_CESA_CAUSE_ACC_BIT 5 -+#define MV_CESA_CAUSE_ACC_MASK (1 << MV_CESA_CAUSE_ACC_BIT) -+ -+#define MV_CESA_CAUSE_ACC_DMA_BIT 7 -+#define MV_CESA_CAUSE_ACC_DMA_MASK (1 << MV_CESA_CAUSE_ACC_DMA_BIT) -+#define MV_CESA_CAUSE_ACC_DMA_ALL_MASK (3 << MV_CESA_CAUSE_ACC_DMA_BIT) -+ -+#define MV_CESA_CAUSE_DMA_COMPL_BIT 9 -+#define MV_CESA_CAUSE_DMA_COMPL_MASK (1 << MV_CESA_CAUSE_DMA_COMPL_BIT) -+ -+#define MV_CESA_CAUSE_DMA_OWN_ERR_BIT 10 -+#define MV_CESA_CAUSE_DMA_OWN_ERR_MASK (1 < MV_CESA_CAUSE_DMA_OWN_ERR_BIT) -+ -+#define MV_CESA_CAUSE_DMA_CHAIN_PKT_BIT 11 -+#define MV_CESA_CAUSE_DMA_CHAIN_PKT_MASK (1 < MV_CESA_CAUSE_DMA_CHAIN_PKT_BIT) -+ -+ -+#define MV_CESA_AUTH_DATA_IN_REG (MV_CESA_REG_BASE + 0xd38) -+#define MV_CESA_AUTH_BIT_COUNT_LOW_REG (MV_CESA_REG_BASE + 0xd20) -+#define MV_CESA_AUTH_BIT_COUNT_HIGH_REG (MV_CESA_REG_BASE + 0xd24) -+ -+#define MV_CESA_AUTH_INIT_VAL_DIGEST_REG(i) (MV_CESA_REG_BASE + 0xd00 + (i<<2)) -+ -+#define MV_CESA_AUTH_INIT_VAL_DIGEST_A_REG (MV_CESA_REG_BASE + 0xd00) -+#define MV_CESA_AUTH_INIT_VAL_DIGEST_B_REG (MV_CESA_REG_BASE + 0xd04) -+#define MV_CESA_AUTH_INIT_VAL_DIGEST_C_REG (MV_CESA_REG_BASE + 0xd08) -+#define MV_CESA_AUTH_INIT_VAL_DIGEST_D_REG (MV_CESA_REG_BASE + 0xd0c) -+#define MV_CESA_AUTH_INIT_VAL_DIGEST_E_REG (MV_CESA_REG_BASE + 0xd10) -+#define MV_CESA_AUTH_COMMAND_REG (MV_CESA_REG_BASE + 0xd18) -+ -+#define MV_CESA_AUTH_ALGORITHM_BIT 0 -+#define MV_CESA_AUTH_ALGORITHM_MD5 (0< -+wait_queue_head_t cesaTest_waitq; -+spinlock_t cesaLock; -+ -+#define CESA_TEST_LOCK(flags) spin_lock_irqsave( &cesaLock, flags) -+#define CESA_TEST_UNLOCK(flags) spin_unlock_irqrestore( &cesaLock, flags); -+ -+#define CESA_TEST_WAIT_INIT() init_waitqueue_head(&cesaTest_waitq) -+#define CESA_TEST_WAKE_UP() wake_up(&cesaTest_waitq) -+#define CESA_TEST_WAIT(cond, ms) wait_event_timeout(cesaTest_waitq, (cond), msecs_to_jiffies(ms)) -+ -+#define CESA_TEST_TICK_GET() jiffies -+#define CESA_TEST_TICK_TO_MS(tick) jiffies_to_msecs(tick) -+ -+#elif defined(MV_NETBSD) -+ -+#include -+#include -+static int cesaLock; -+ -+#define CESA_TEST_LOCK(flags) flags = splnet() -+#define CESA_TEST_UNLOCK(flags) splx(flags) -+ -+#define CESA_TEST_WAIT_INIT() /* nothing */ -+#define CESA_TEST_WAKE_UP() wakeup(&cesaLock) -+#define CESA_TEST_WAIT(cond, ms) \ -+do { \ -+ while (!(cond)) \ -+ tsleep(&cesaLock, PWAIT, "cesatest",mstohz(ms)); \ -+} while (/*CONSTCOND*/0) -+ -+#define CESA_TEST_TICK_GET() hardclock_ticks -+#define CESA_TEST_TICK_TO_MS(tick) ((1000/hz)*(tick)) -+ -+#define request_irq(i,h,t,n,a) \ -+ !mv_intr_establish((i),IPL_NET,(int(*)(void *))(h),(a)) -+ -+#else -+#error "Only Linux, VxWorks, or NetBSD OS are supported" -+#endif -+ -+#include "mvDebug.h" -+ -+#include "mvSysHwConfig.h" -+#include "boardEnv/mvBoardEnvLib.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+#include "cntmr/mvCntmr.h" -+#include "cesa/mvCesa.h" -+#include "cesa/mvCesaRegs.h" -+#include "cesa/mvMD5.h" -+#include "cesa/mvSHA1.h" -+ -+#if defined(CONFIG_MV646xx) -+#include "marvell_pic.h" -+#endif -+ -+#define MV_CESA_USE_TIMER_ID 0 -+#define CESA_DEF_BUF_SIZE 1500 -+#define CESA_DEF_BUF_NUM 1 -+#define CESA_DEF_SESSION_NUM 32 -+ -+#define CESA_DEF_ITER_NUM 100 -+ -+#define CESA_DEF_REQ_SIZE 256 -+ -+ -+/* CESA Tests Debug */ -+#undef CESA_TEST_DEBUG -+ -+#ifdef CESA_TEST_DEBUG -+ -+# define CESA_TEST_DEBUG_PRINT(msg) mvOsPrintf msg -+# define CESA_TEST_DEBUG_CODE(code) code -+ -+typedef struct -+{ -+ int type; /* 0 - isrEmpty, 1 - cesaReadyGet, 2 - cesaAction */ -+ MV_U32 timeStamp; -+ MV_U32 cause; -+ MV_U32 realCause; -+ MV_U32 dmaCause; -+ int resources; -+ MV_CESA_REQ* pReqReady; -+ MV_CESA_REQ* pReqEmpty; -+ MV_CESA_REQ* pReqProcess; -+} MV_CESA_TEST_TRACE; -+ -+#define MV_CESA_TEST_TRACE_SIZE 25 -+ -+static int cesaTestTraceIdx = 0; -+static MV_CESA_TEST_TRACE cesaTestTrace[MV_CESA_TEST_TRACE_SIZE]; -+ -+static void cesaTestTraceAdd(int type, MV_U32 cause) -+{ -+ cesaTestTrace[cesaTestTraceIdx].type = type; -+ cesaTestTrace[cesaTestTraceIdx].cause = cause; -+ cesaTestTrace[cesaTestTraceIdx].realCause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); -+ cesaTestTrace[cesaTestTraceIdx].dmaCause = MV_REG_READ(IDMA_CAUSE_REG); -+ cesaTestTrace[cesaTestTraceIdx].resources = cesaReqResources; -+ cesaTestTrace[cesaTestTraceIdx].pReqReady = pCesaReqReady; -+ cesaTestTrace[cesaTestTraceIdx].pReqEmpty = pCesaReqEmpty; -+ cesaTestTrace[cesaTestTraceIdx].pReqProcess = pCesaReqProcess; -+ cesaTestTrace[cesaTestTraceIdx].timeStamp = mvCntmrRead(MV_CESA_USE_TIMER_ID); -+ cesaTestTraceIdx++; -+ if(cesaTestTraceIdx == MV_CESA_TEST_TRACE_SIZE) -+ cesaTestTraceIdx = 0; -+} -+ -+#else -+ -+# define CESA_TEST_DEBUG_PRINT(msg) -+# define CESA_TEST_DEBUG_CODE(code) -+ -+#endif /* CESA_TEST_DEBUG */ -+ -+int cesaExpReqId=0; -+int cesaCbIter=0; -+ -+int cesaIdx; -+int cesaIteration; -+int cesaRateSize; -+int cesaReqSize; -+unsigned long cesaTaskId; -+int cesaBufNum; -+int cesaBufSize; -+int cesaCheckOffset; -+int cesaCheckSize; -+int cesaCheckMode; -+int cesaTestIdx; -+int cesaCaseIdx; -+ -+ -+MV_U32 cesaTestIsrCount = 0; -+MV_U32 cesaTestIsrMissCount = 0; -+ -+MV_U32 cesaCryptoError = 0; -+MV_U32 cesaReqIdError = 0; -+MV_U32 cesaError = 0; -+ -+char* cesaHexBuffer = NULL; -+ -+char* cesaBinBuffer = NULL; -+char* cesaExpBinBuffer = NULL; -+ -+char* cesaInputHexStr = NULL; -+char* cesaOutputHexStr = NULL; -+ -+MV_BUF_INFO cesaReqBufs[CESA_DEF_REQ_SIZE]; -+ -+MV_CESA_COMMAND* cesaCmdRing; -+MV_CESA_RESULT cesaResult; -+ -+int cesaTestFull = 0; -+ -+MV_BOOL cesaIsReady = MV_FALSE; -+MV_U32 cesaCycles = 0; -+MV_U32 cesaBeginTicks = 0; -+MV_U32 cesaEndTicks = 0; -+MV_U32 cesaRate = 0; -+MV_U32 cesaRateAfterDot = 0; -+ -+void *cesaTestOSHandle = NULL; -+ -+enum -+{ -+ CESA_FAST_CHECK_MODE = 0, -+ CESA_FULL_CHECK_MODE, -+ CESA_NULL_CHECK_MODE, -+ CESA_SHOW_CHECK_MODE, -+ CESA_SW_SHOW_CHECK_MODE, -+ CESA_SW_NULL_CHECK_MODE, -+ -+ CESA_MAX_CHECK_MODE -+}; -+ -+enum -+{ -+ DES_TEST_TYPE = 0, -+ TRIPLE_DES_TEST_TYPE = 1, -+ AES_TEST_TYPE = 2, -+ MD5_TEST_TYPE = 3, -+ SHA_TEST_TYPE = 4, -+ COMBINED_TEST_TYPE = 5, -+ -+ MAX_TEST_TYPE -+}; -+ -+/* Tests data base */ -+typedef struct -+{ -+ short sid; -+ char cryptoAlgorithm; /* DES/3DES/AES */ -+ char cryptoMode; /* ECB or CBC */ -+ char macAlgorithm; /* MD5 / SHA1 */ -+ char operation; /* CRYPTO/HMAC/CRYPTO+HMAC/HMAC+CRYPTO */ -+ char direction; /* ENCODE(SIGN)/DECODE(VERIFY) */ -+ unsigned char* pCryptoKey; -+ int cryptoKeySize; -+ unsigned char* pMacKey; -+ int macKeySize; -+ const char* name; -+ -+} MV_CESA_TEST_SESSION; -+ -+typedef struct -+{ -+ MV_CESA_TEST_SESSION* pSessions; -+ int numSessions; -+ -+} MV_CESA_TEST_DB_ENTRY; -+ -+typedef struct -+{ -+ char* plainHexStr; -+ char* cipherHexStr; -+ unsigned char* pCryptoIV; -+ int cryptoLength; -+ int macLength; -+ int digestOffset; -+ -+} MV_CESA_TEST_CASE; -+ -+typedef struct -+{ -+ int size; -+ const char* outputHexStr; -+ -+} MV_CESA_SIZE_TEST; -+ -+static unsigned char cryptoKey1[] = {0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, -+ 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, -+ 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef}; -+ -+static unsigned char cryptoKey7[] = {0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef}; -+static unsigned char iv1[] = {0x12, 0x34, 0x56, 0x78, 0x90, 0xab, 0xcd, 0xef}; -+ -+ -+static unsigned char cryptoKey2[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, -+ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F}; -+ -+static unsigned char cryptoKey3[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, -+ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, -+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17}; -+ -+static unsigned char cryptoKey4[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, -+ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, -+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, -+ 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f}; -+ -+static unsigned char cryptoKey5[] = {0x56, 0xe4, 0x7a, 0x38, 0xc5, 0x59, 0x89, 0x74, -+ 0xbc, 0x46, 0x90, 0x3d, 0xba, 0x29, 0x03, 0x49}; -+ -+ -+static unsigned char key3des1[] = {0x01, 0x23, 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF, -+ 0x23, 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF, 0x01, -+ 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF, 0x01, 0x23}; -+ -+/* Input ASCII string: The quick brown fox jump */ -+static char plain3des1[] = "54686520717566636B2062726F776E20666F78206A756D70"; -+static char cipher3des1[] = "A826FD8CE53B855FCCE21C8112256FE668D5C05DD9B6B900"; -+ -+static unsigned char key3des2[] = {0x62, 0x7f, 0x46, 0x0e, 0x08, 0x10, 0x4a, 0x10, -+ 0x43, 0xcd, 0x26, 0x5d, 0x58, 0x40, 0xea, 0xf1, -+ 0x31, 0x3e, 0xdf, 0x97, 0xdf, 0x2a, 0x8a, 0x8c}; -+ -+static unsigned char iv3des2[] = {0x8e, 0x29, 0xf7, 0x5e, 0xa7, 0x7e, 0x54, 0x75}; -+ -+static char plain3des2[] = "326a494cd33fe756"; -+ -+static char cipher3desCbc2[] = "8e29f75ea77e5475" -+ "b22b8d66de970692"; -+ -+static unsigned char key3des3[] = {0x37, 0xae, 0x5e, 0xbf, 0x46, 0xdf, 0xf2, 0xdc, -+ 0x07, 0x54, 0xb9, 0x4f, 0x31, 0xcb, 0xb3, 0x85, -+ 0x5e, 0x7f, 0xd3, 0x6d, 0xc8, 0x70, 0xbf, 0xae}; -+ -+static unsigned char iv3des3[] = {0x3d, 0x1d, 0xe3, 0xcc, 0x13, 0x2e, 0x3b, 0x65}; -+ -+static char plain3des3[] = "84401f78fe6c10876d8ea23094ea5309"; -+ -+static char cipher3desCbc3[] = "3d1de3cc132e3b65" -+ "7b1f7c7e3b1c948ebd04a75ffba7d2f5"; -+ -+static unsigned char iv5[] = {0x8c, 0xe8, 0x2e, 0xef, 0xbe, 0xa0, 0xda, 0x3c, -+ 0x44, 0x69, 0x9e, 0xd7, 0xdb, 0x51, 0xb7, 0xd9}; -+ -+static unsigned char aesCtrKey[] = {0x76, 0x91, 0xBE, 0x03, 0x5E, 0x50, 0x20, 0xA8, -+ 0xAC, 0x6E, 0x61, 0x85, 0x29, 0xF9, 0xA0, 0xDC}; -+ -+static unsigned char mdKey1[] = {0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, -+ 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b}; -+ -+static unsigned char mdKey2[] = {0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -+ 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa}; -+ -+static unsigned char shaKey1[] = {0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, -+ 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, -+ 0x0b, 0x0b, 0x0b, 0x0b}; -+ -+static unsigned char shaKey2[] = {0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -+ 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -+ 0xaa, 0xaa, 0xaa, 0xaa}; -+ -+static unsigned char mdKey4[] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10}; -+ -+static unsigned char shaKey4[] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10, -+ 0x11, 0x12, 0x13, 0x14}; -+ -+ -+static MV_CESA_TEST_SESSION desTestSessions[] = -+{ -+/*000*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey7, sizeof(cryptoKey7)/sizeof(cryptoKey7[0]), -+ NULL, 0, -+ "DES ECB encode", -+ }, -+/*001*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_DECODE, -+ cryptoKey7, sizeof(cryptoKey7)/sizeof(cryptoKey7[0]), -+ NULL, 0, -+ "DES ECB decode", -+ }, -+/*002*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey7, sizeof(cryptoKey7)/sizeof(cryptoKey7[0]), -+ NULL, 0, -+ "DES CBC encode" -+ }, -+/*003*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_DECODE, -+ cryptoKey7, sizeof(cryptoKey7)/sizeof(cryptoKey7[0]), -+ NULL, 0, -+ "DES CBC decode" -+ }, -+/*004*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, NULL, 0, -+ "NULL Crypto Algorithm encode" -+ }, -+}; -+ -+ -+static MV_CESA_TEST_SESSION tripleDesTestSessions[] = -+{ -+/*100*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ NULL, 0, -+ "3DES ECB encode", -+ }, -+/*101*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_DECODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ NULL, 0, -+ "3DES ECB decode", -+ }, -+/*102*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ NULL, 0, -+ "3DES CBC encode" -+ }, -+/*103*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_DECODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ NULL, 0, -+ "3DES CBC decode" -+ }, -+/*104*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ key3des1, sizeof(key3des1), -+ NULL, 0, -+ "3DES ECB encode" -+ }, -+/*105*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ key3des2, sizeof(key3des2), -+ NULL, 0, -+ "3DES ECB encode" -+ }, -+/*106*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ key3des3, sizeof(key3des3), -+ NULL, 0, -+ "3DES ECB encode" -+ }, -+}; -+ -+ -+static MV_CESA_TEST_SESSION aesTestSessions[] = -+{ -+/*200*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey2, sizeof(cryptoKey2)/sizeof(cryptoKey2[0]), -+ NULL, 0, -+ "AES-128 ECB encode" -+ }, -+/*201*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_DECODE, -+ cryptoKey2, sizeof(cryptoKey2)/sizeof(cryptoKey2[0]), -+ NULL, 0, -+ "AES-128 ECB decode" -+ }, -+/*202*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey5, sizeof(cryptoKey5)/sizeof(cryptoKey5[0]), -+ NULL, 0, -+ "AES-128 CBC encode" -+ }, -+/*203*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_DECODE, -+ cryptoKey5, sizeof(cryptoKey5)/sizeof(cryptoKey5[0]), -+ NULL, 0, -+ "AES-128 CBC decode" -+ }, -+/*204*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey3, sizeof(cryptoKey3)/sizeof(cryptoKey3[0]), -+ NULL, 0, -+ "AES-192 ECB encode" -+ }, -+/*205*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_DECODE, -+ cryptoKey3, sizeof(cryptoKey3)/sizeof(cryptoKey3[0]), -+ NULL, 0, -+ "AES-192 ECB decode" -+ }, -+/*206*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey4, sizeof(cryptoKey4)/sizeof(cryptoKey4[0]), -+ NULL, 0, -+ "AES-256 ECB encode" -+ }, -+/*207*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_DECODE, -+ cryptoKey4, sizeof(cryptoKey4)/sizeof(cryptoKey4[0]), -+ NULL, 0, -+ "AES-256 ECB decode" -+ }, -+/*208*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CTR, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ aesCtrKey, sizeof(aesCtrKey)/sizeof(aesCtrKey[0]), -+ NULL, 0, -+ "AES-128 CTR encode" -+ }, -+}; -+ -+ -+static MV_CESA_TEST_SESSION md5TestSessions[] = -+{ -+/*300*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, -+ mdKey1, sizeof(mdKey1), -+ "HMAC-MD5 Generate Signature" -+ }, -+/*301*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_DECODE, -+ NULL, 0, -+ mdKey1, sizeof(mdKey1), -+ "HMAC-MD5 Verify Signature" -+ }, -+/*302*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, -+ mdKey2, sizeof(mdKey2), -+ "HMAC-MD5 Generate Signature" -+ }, -+/*303*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_DECODE, -+ NULL, 0, -+ mdKey2, sizeof(mdKey2), -+ "HMAC-MD5 Verify Signature" -+ }, -+/*304*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, -+ mdKey4, sizeof(mdKey4), -+ "HMAC-MD5 Generate Signature" -+ }, -+/*305*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_MD5, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, -+ NULL, 0, -+ "HASH-MD5 Generate Signature" -+ }, -+}; -+ -+ -+static MV_CESA_TEST_SESSION shaTestSessions[] = -+{ -+/*400*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, -+ shaKey1, sizeof(shaKey1), -+ "HMAC-SHA1 Generate Signature" -+ }, -+/*401*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_DECODE, -+ NULL, 0, -+ shaKey1, sizeof(shaKey1), -+ "HMAC-SHA1 Verify Signature" -+ }, -+/*402*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, -+ shaKey2, sizeof(shaKey2), -+ "HMAC-SHA1 Generate Signature" -+ }, -+/*403*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_DECODE, -+ NULL, 0, -+ shaKey2, sizeof(shaKey2), -+ "HMAC-SHA1 Verify Signature" -+ }, -+/*404*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, -+ shaKey4, sizeof(shaKey4), -+ "HMAC-SHA1 Generate Signature" -+ }, -+/*405*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_SHA1, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, -+ NULL, 0, -+ "HASH-SHA1 Generate Signature" -+ }, -+}; -+ -+static MV_CESA_TEST_SESSION combinedTestSessions[] = -+{ -+/*500*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey1, MV_CESA_DES_KEY_LENGTH, -+ mdKey4, sizeof(mdKey4), -+ "DES + MD5 encode" -+ }, -+/*501*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey1, MV_CESA_DES_KEY_LENGTH, -+ shaKey4, sizeof(shaKey4), -+ "DES + SHA1 encode" -+ }, -+/*502*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ mdKey4, sizeof(mdKey4), -+ "3DES + MD5 encode" -+ }, -+/*503*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ shaKey4, sizeof(shaKey4), -+ "3DES + SHA1 encode" -+ }, -+/*504*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ mdKey4, sizeof(mdKey4), -+ "3DES CBC + MD5 encode" -+ }, -+/*505*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ shaKey4, sizeof(shaKey4), -+ "3DES CBC + SHA1 encode" -+ }, -+/*506*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey5, sizeof(cryptoKey5)/sizeof(cryptoKey5[0]), -+ mdKey4, sizeof(mdKey4), -+ "AES-128 CBC + MD5 encode" -+ }, -+/*507*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey5, sizeof(cryptoKey5)/sizeof(cryptoKey5[0]), -+ shaKey4, sizeof(shaKey4), -+ "AES-128 CBC + SHA1 encode" -+ }, -+/*508*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_THEN_CRYPTO, -+ MV_CESA_DIR_DECODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ mdKey4, sizeof(mdKey4), -+ "HMAC-MD5 + 3DES decode" -+ }, -+}; -+ -+ -+static MV_CESA_TEST_DB_ENTRY cesaTestsDB[MAX_TEST_TYPE+1] = -+{ -+ { desTestSessions, sizeof(desTestSessions)/sizeof(desTestSessions[0]) }, -+ { tripleDesTestSessions, sizeof(tripleDesTestSessions)/sizeof(tripleDesTestSessions[0]) }, -+ { aesTestSessions, sizeof(aesTestSessions)/sizeof(aesTestSessions[0]) }, -+ { md5TestSessions, sizeof(md5TestSessions)/sizeof(md5TestSessions[0]) }, -+ { shaTestSessions, sizeof(shaTestSessions)/sizeof(shaTestSessions[0]) }, -+ { combinedTestSessions, sizeof(combinedTestSessions)/sizeof(combinedTestSessions[0]) }, -+ { NULL, 0 } -+}; -+ -+ -+char cesaNullPlainHexText[] = "000000000000000000000000000000000000000000000000"; -+ -+char cesaPlainAsciiText[] = "Now is the time for all "; -+char cesaPlainHexEbc[] = "4e6f77206973207468652074696d6520666f7220616c6c20"; -+char cesaCipherHexEcb[] = "3fa40e8a984d48156a271787ab8883f9893d51ec4b563b53"; -+char cesaPlainHexCbc[] = "1234567890abcdef4e6f77206973207468652074696d6520666f7220616c6c20"; -+char cesaCipherHexCbc[] = "1234567890abcdefe5c7cdde872bf27c43e934008c389c0f683788499a7c05f6"; -+ -+char cesaAesPlainHexEcb[] = "000102030405060708090a0b0c0d0e0f"; -+char cesaAes128cipherHexEcb[] = "0a940bb5416ef045f1c39458c653ea5a"; -+char cesaAes192cipherHexEcb[] = "0060bffe46834bb8da5cf9a61ff220ae"; -+char cesaAes256cipherHexEcb[] = "5a6e045708fb7196f02e553d02c3a692"; -+ -+char cesaAsciiStr1[] = "Hi There"; -+char cesaDataHexStr1[] = "4869205468657265"; -+char cesaHmacMd5digestHex1[] = "9294727a3638bb1c13f48ef8158bfc9d"; -+char cesaHmacSha1digestHex1[] = "b617318655057264e28bc0b6fb378c8ef146be00"; -+char cesaDataAndMd5digest1[] = "48692054686572659294727a3638bb1c13f48ef8158bfc9d"; -+char cesaDataAndSha1digest1[] = "4869205468657265b617318655057264e28bc0b6fb378c8ef146be00"; -+ -+char cesaAesPlainText[] = "a0a1a2a3a4a5a6a7a8a9aaabacadaeaf" -+ "b0b1b2b3b4b5b6b7b8b9babbbcbdbebf" -+ "c0c1c2c3c4c5c6c7c8c9cacbcccdcecf" -+ "d0d1d2d3d4d5d6d7d8d9dadbdcdddedf"; -+ -+char cesaAes128CipherCbc[] = "c30e32ffedc0774e6aff6af0869f71aa" -+ "0f3af07a9a31a9c684db207eb0ef8e4e" -+ "35907aa632c3ffdf868bb7b29d3d46ad" -+ "83ce9f9a102ee99d49a53e87f4c3da55"; -+ -+char cesaAesIvPlainText[] = "8ce82eefbea0da3c44699ed7db51b7d9" -+ "a0a1a2a3a4a5a6a7a8a9aaabacadaeaf" -+ "b0b1b2b3b4b5b6b7b8b9babbbcbdbebf" -+ "c0c1c2c3c4c5c6c7c8c9cacbcccdcecf" -+ "d0d1d2d3d4d5d6d7d8d9dadbdcdddedf"; -+ -+char cesaAes128IvCipherCbc[] = "8ce82eefbea0da3c44699ed7db51b7d9" -+ "c30e32ffedc0774e6aff6af0869f71aa" -+ "0f3af07a9a31a9c684db207eb0ef8e4e" -+ "35907aa632c3ffdf868bb7b29d3d46ad" -+ "83ce9f9a102ee99d49a53e87f4c3da55"; -+ -+char cesaAesCtrPlain[] = "00E0017B27777F3F4A1786F000000001" -+ "000102030405060708090A0B0C0D0E0F" -+ "101112131415161718191A1B1C1D1E1F" -+ "20212223"; -+ -+char cesaAesCtrCipher[] = "00E0017B27777F3F4A1786F000000001" -+ "C1CF48A89F2FFDD9CF4652E9EFDB72D7" -+ "4540A42BDE6D7836D59A5CEAAEF31053" -+ "25B2072F"; -+ -+ -+ -+/* Input cesaHmacHex3 is '0xdd' repeated 50 times */ -+char cesaHmacMd5digestHex3[] = "56be34521d144c88dbb8c733f0e8b3f6"; -+char cesaHmacSha1digestHex3[] = "125d7342b9ac11cd91a39af48aa17b4f63f175d3"; -+char cesaDataHexStr3[50*2+1] = ""; -+char cesaDataAndMd5digest3[sizeof(cesaDataHexStr3)+sizeof(cesaHmacMd5digestHex3)+8*2+1] = ""; -+char cesaDataAndSha1digest3[sizeof(cesaDataHexStr3)+sizeof(cesaHmacSha1digestHex3)+8*2+1] = ""; -+ -+/* Ascii string is "abc" */ -+char hashHexStr3[] = "616263"; -+char hashMd5digest3[] = "900150983cd24fb0d6963f7d28e17f72"; -+char hashSha1digest3[] = "a9993e364706816aba3e25717850c26c9cd0d89d"; -+ -+char hashHexStr80[] = "31323334353637383930" -+ "31323334353637383930" -+ "31323334353637383930" -+ "31323334353637383930" -+ "31323334353637383930" -+ "31323334353637383930" -+ "31323334353637383930" -+ "31323334353637383930"; -+ -+char hashMd5digest80[] = "57edf4a22be3c955ac49da2e2107b67a"; -+ -+char tripleDesThenMd5digest80[] = "b7726a03aad490bd6c5a452a89a1b271"; -+char tripleDesThenSha1digest80[] = "b2ddeaca91030eab5b95a234ef2c0f6e738ff883"; -+ -+char cbc3desThenMd5digest80[] = "6f463057e1a90e0e91ae505b527bcec0"; -+char cbc3desThenSha1digest80[] = "1b002ed050be743aa98860cf35659646bb8efcc0"; -+ -+char cbcAes128ThenMd5digest80[] = "6b6e863ac5a71d15e3e9b1c86c9ba05f"; -+char cbcAes128ThenSha1digest80[] = "13558472d1fc1c90dffec6e5136c7203452d509b"; -+ -+ -+static MV_CESA_TEST_CASE cesaTestCases[] = -+{ -+ /* plainHexStr cipherHexStr IV crypto mac digest */ -+ /* Length Length Offset */ -+ /*0*/ { NULL, NULL, NULL, 0, 0, -1 }, -+ /*1*/ { cesaPlainHexEbc, cesaCipherHexEcb, NULL, 24, 0, -1 }, -+ /*2*/ { cesaPlainHexCbc, cesaCipherHexCbc, NULL, 24, 0, -1 }, -+ /*3*/ { cesaAesPlainHexEcb, cesaAes128cipherHexEcb, NULL, 16, 0, -1 }, -+ /*4*/ { cesaAesPlainHexEcb, cesaAes192cipherHexEcb, NULL, 16, 0, -1 }, -+ /*5*/ { cesaAesPlainHexEcb, cesaAes256cipherHexEcb, NULL, 16, 0, -1 }, -+ /*6*/ { cesaDataHexStr1, cesaHmacMd5digestHex1, NULL, 0, 8, -1 }, -+ /*7*/ { NULL, cesaDataAndMd5digest1, NULL, 0, 8, -1 }, -+ /*8*/ { cesaDataHexStr3, cesaHmacMd5digestHex3, NULL, 0, 50, -1 }, -+ /*9*/ { NULL, cesaDataAndMd5digest3, NULL, 0, 50, -1 }, -+/*10*/ { cesaAesPlainText, cesaAes128IvCipherCbc, iv5, 64, 0, -1 }, -+/*11*/ { cesaDataHexStr1, cesaHmacSha1digestHex1, NULL, 0, 8, -1 }, -+/*12*/ { NULL, cesaDataAndSha1digest1, NULL, 0, 8, -1 }, -+/*13*/ { cesaDataHexStr3, cesaHmacSha1digestHex3, NULL, 0, 50, -1 }, -+/*14*/ { NULL, cesaDataAndSha1digest3, NULL, 0, 50, -1 }, -+/*15*/ { hashHexStr3, hashMd5digest3, NULL, 0, 3, -1 }, -+/*16*/ { hashHexStr3, hashSha1digest3, NULL, 0, 3, -1 }, -+/*17*/ { hashHexStr80, tripleDesThenMd5digest80, NULL, 80, 80, -1 }, -+/*18*/ { hashHexStr80, tripleDesThenSha1digest80, NULL, 80, 80, -1 }, -+/*19*/ { hashHexStr80, cbc3desThenMd5digest80, iv1, 80, 80, -1 }, -+/*20*/ { hashHexStr80, cbc3desThenSha1digest80, iv1, 80, 80, -1 }, -+/*21*/ { hashHexStr80, cbcAes128ThenMd5digest80, iv5, 80, 80, -1 }, -+/*22*/ { hashHexStr80, cbcAes128ThenSha1digest80, iv5, 80, 80, -1 }, -+/*23*/ { cesaAesCtrPlain, cesaAesCtrCipher, NULL, 36, 0, -1 }, -+/*24*/ { cesaAesIvPlainText, cesaAes128IvCipherCbc, NULL, 64, 0, -1 }, -+/*25*/ { plain3des1, cipher3des1, NULL, 0, 0, -1 }, -+/*26*/ { plain3des2, cipher3desCbc2, iv3des2,0, 0, -1 }, -+/*27*/ { plain3des3, cipher3desCbc3, iv3des3,0, 0, -1 }, -+}; -+ -+ -+/* Key = 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -+ * 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa -+ * Input 0xdd repeated "size" times -+ */ -+static MV_CESA_SIZE_TEST mdMultiSizeTest302[] = -+{ -+ { 80, "7a031a640c14a4872814930b1ef3a5b2" }, -+ { 512, "5488e6c5a14dc72a79f28312ca5b939b" }, -+ { 1000, "d00814f586a8b78a05724239d2531821" }, -+ { 1001, "bf07df7b7f49d3f5b5ecacd4e9e63281" }, -+ { 1002, "1ed4a1a802e87817a819d4e37bb4d0f7" }, -+ { 1003, "5972ab64a4f265ee371dac2f2f137f90" }, -+ { 1004, "71f95e7ec3aa7df2548e90898abdb28e" }, -+ { 1005, "e082790b4857fcfc266e92e59e608814" }, -+ { 1006, "9500f02fd8ac7fde8b10e4fece9a920d" }, -+ { 1336, "e42edcce57d0b75b01aa09d71427948b" }, -+ { 1344, "bb5454ada0deb49ba0a97ffd60f57071" }, -+ { 1399, "0f44d793e744b24d53f44f295082ee8c" }, -+ { 1400, "359de8a03a9b707928c6c60e0e8d79f1" }, -+ { 1401, "e913858b484cbe2b384099ea88d8855b" }, -+ { 1402, "d9848a164af53620e0540c1d7d87629e" }, -+ { 1403, "0c9ee1c2c9ef45e9b625c26cbaf3e822" }, -+ { 1404, "12edd4f609416e3c936170360561b064" }, -+ { 1405, "7fc912718a05446395345009132bf562" }, -+ { 1406, "882f17425e579ff0d85a91a59f308aa0" }, -+ { 1407, "005cae408630a2fb5db82ad9db7e59da" }, -+ { 1408, "64655f8b404b3fea7a3e3e609bc5088f" }, -+ { 1409, "4a145284a7f74e01b6bb1a0ec6a0dd80" }, -+ { 2048, "67caf64475650732def374ebb8bde3fd" }, -+ { 2049, "6c84f11f472825f7e6cd125c2981884b" }, -+ { 2050, "8999586754a73a99efbe4dbad2816d41" }, -+ { 2051, "ba6946b610e098d286bc81091659dfff" }, -+ { 2052, "d0afa01c92d4d13def2b024f36faed83" }, -+ { 3072, "61d8beac61806afa2585d74a9a0e6974" }, -+ { 3074, "f6501a28dcc24d1e4770505c51a87ed3" }, -+ { 3075, "ea4a6929be67e33e61ff475369248b73" }, -+ { 4048, "aa8c4d68f282a07e7385acdfa69f4bed" }, -+ { 4052, "afb5ed2c0e1d430ea59e59ed5ed6b18a" }, -+ { 4058, "9e8553f9bdd43aebe0bd729f0e600c99" }, -+ { 6144, "f628f3e5d183fe5cdd3a5abee39cf872" }, -+ { 6150, "89a3efcea9a2f25f919168ad4a1fd292" }, -+ { 6400, "cdd176b7fb747873efa4da5e32bdf88f" }, -+ { 6528, "b1d707b027354aca152c45ee559ccd3f" }, -+ { 8192, "c600ea4429ac47f9941f09182166e51a" }, -+ {16384, "16e8754bfbeb4c649218422792267a37" }, -+ {18432, "0fd0607521b0aa8b52219cfbe215f63e" }, -+ { 0, NULL }, -+}; -+ -+/* Key = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ */ -+static MV_CESA_SIZE_TEST mdMultiSizeTest304[] = -+{ -+ { 80, "a456c4723fee6068530af5a2afa71627" }, -+ { 512, "f85c2a2344f5de68b432208ad13e5794" }, -+ { 1000, "35464d6821fd4a293a41eb84e274c8c5" }, -+ { 1001, "c08eedbdce60cceb54bc2d732bb32c8b" }, -+ { 1002, "5664f71800c011cc311cb6943339c1b8" }, -+ { 1003, "779c723b044c585dc7802b13e8501bdc" }, -+ { 1004, "55e500766a2c307bc5c5fdd15e4cacd4" }, -+ { 1005, "d5f978954f5c38529d1679d2b714f068" }, -+ { 1006, "cd3efc827ce628b7281b72172693abf9" }, -+ { 1336, "6f04479910785878ae6335b8d1e87edf" }, -+ { 1344, "b6d27b50c2bce1ba2a8e1b5cc4324368" }, -+ { 1399, "65f70a1d4c86e5eaeb0704c8a7816795" }, -+ { 1400, "3394b5adc4cb3ff98843ca260a44a88a" }, -+ { 1401, "3a06f3582033a66a4e57e0603ce94e74" }, -+ { 1402, "e4d97f5ed51edc48abfa46eeb5c31752" }, -+ { 1403, "3d05e40b080ee3bedf293cb87b7140e7" }, -+ { 1404, "8cf294fc3cd153ab18dccb2a52cbf244" }, -+ { 1405, "d1487bd42f6edd9b4dab316631159221" }, -+ { 1406, "0527123b6bf6936cf5d369dc18c6c70f" }, -+ { 1407, "3224a06639db70212a0cd1ae1fcc570a" }, -+ { 1408, "a9e13335612c0356f5e2c27086e86c43" }, -+ { 1409, "a86d1f37d1ed8a3552e9a4f04dceea98" }, -+ { 2048, "396905c9b961cd0f6152abfb69c4449c" }, -+ { 2049, "49f39bff85d9dcf059fadb89efc4a70f" }, -+ { 2050, "3a2b4823bc4d0415656550226a63e34a" }, -+ { 2051, "dec60580d406c782540f398ad0bcc7e0" }, -+ { 2052, "32f76610a14310309eb748fe025081bf" }, -+ { 3072, "45edc1a42bf9d708a621076b63b774da" }, -+ { 3074, "9be1b333fe7c0c9f835fb369dc45f778" }, -+ { 3075, "8c06fcac7bd0e7b7a17fd6508c09a549" }, -+ { 4048, "0ddaef848184bf0ad98507a10f1e90e4" }, -+ { 4052, "81976bcaeb274223983996c137875cb8" }, -+ { 4058, "0b0a7a1c82bc7cbc64d8b7cd2dc2bb22" }, -+ { 6144, "1c24056f52725ede2dff0d7f9fc9855f" }, -+ { 6150, "b7f4b65681c4e43ee68ca466ca9ca4ec" }, -+ { 6400, "443bbaab9f7331ddd4bf11b659cd43c8" }, -+ { 6528, "216f44f23047cfee03a7a64f88f9a995" }, -+ { 8192, "ac7a993b2cad54879dba1bde63e39097" }, -+ { 8320, "55ed7be9682d6c0025b3221a62088d08" }, -+ {16384, "c6c722087653b62007aea668277175e5" }, -+ {18432, "f1faca8e907872c809e14ffbd85792d6" }, -+ { 0, NULL }, -+}; -+ -+/* HASH-MD5 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ * repeated "size" times -+ */ -+static MV_CESA_SIZE_TEST mdMultiSizeTest305[] = -+{ -+ { 80, "57edf4a22be3c955ac49da2e2107b67a" }, -+ { 512, "c729ae8f0736cc377a9767a660eaa04e" }, -+ { 1000, "f1257a8659eb92d36fe14c6bf3852a6a" }, -+ { 1001, "f8a46fe8ea04fdc8c7de0e84042d3878" }, -+ { 1002, "da188dd67bff87d58aa3c02af2d0cc0f" }, -+ { 1003, "961753017feee04c9b93a8e51658a829" }, -+ { 1004, "dd68c4338608dcc87807a711636bf2af" }, -+ { 1005, "e338d567d3ce66bf69ada29658a8759b" }, -+ { 1006, "443c9811e8b92599b0b149e8d7ec700a" }, -+ { 1336, "89a98511706008ba4cbd0b4a24fa5646" }, -+ { 1344, "335a919805f370b9e402a62c6fe01739" }, -+ { 1399, "5d18d0eddcd84212fe28d812b5e80e3b" }, -+ { 1400, "6b695c240d2dffd0dffc99459ca76db6" }, -+ { 1401, "49590f61298a76719bc93a57a30136f5" }, -+ { 1402, "94c2999fa3ef1910a683d69b2b8476f2" }, -+ { 1403, "37073a02ab00ecba2645c57c228860db" }, -+ { 1404, "1bcd06994fce28b624f0c5fdc2dcdd2b" }, -+ { 1405, "11b93671a64c95079e8cf9e7cddc8b3d" }, -+ { 1406, "4b6695772a4c66313fa4871017d05f36" }, -+ { 1407, "d1539b97fbfda1c075624e958de19c5b" }, -+ { 1408, "b801b9b69920907cd018e8063092ede9" }, -+ { 1409, "b765f1406cfe78e238273ed01bbcaf7e" }, -+ { 2048, "1d7e2c64ac29e2b3fb4c272844ed31f5" }, -+ { 2049, "71d38fac49c6b1f4478d8d88447bcdd0" }, -+ { 2050, "141c34a5592b1bebfa731e0b23d0cdba" }, -+ { 2051, "c5e1853f21c59f5d6039bd13d4b380d8" }, -+ { 2052, "dd44a0d128b63d4b5cccd967906472d7" }, -+ { 3072, "37d158e33b21390822739d13db7b87fe" }, -+ { 3074, "aef3b209d01d39d0597fe03634bbf441" }, -+ { 3075, "335ffb428eabf210bada96d74d5a4012" }, -+ { 4048, "2434c2b43d798d2819487a886261fc64" }, -+ { 4052, "ac2fa84a8a33065b2e92e36432e861f8" }, -+ { 4058, "856781f85616c341c3533d090c1e1e84" }, -+ { 6144, "e5d134c652c18bf19833e115f7a82e9b" }, -+ { 6150, "a09a353be7795fac2401dac5601872e6" }, -+ { 6400, "08b9033ac6a1821398f50af75a2dbc83" }, -+ { 6528, "3d47aa193a8540c091e7e02f779e6751" }, -+ { 8192, "d3164e710c0626f6f395b38f20141cb7" }, -+ { 8320, "b727589d9183ff4e8491dd24466974a3" }, -+ {16384, "3f54d970793d2274d5b20d10a69938ac" }, -+ {18432, "f558511dcf81985b7a1bb57fad970531" }, -+ { 0, NULL }, -+}; -+ -+ -+/* Key = 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -+ * 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa -+ * 0xaa, 0xaa, 0xaa, 0xaa -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ */ -+static MV_CESA_SIZE_TEST shaMultiSizeTest402[] = -+{ -+ { 80, "e812f370e659705a1649940d1f78cd7af18affd3" }, -+ { 512, "e547f886b2c15d995ed76a8a924cb408c8080f66" }, -+ { 1000, "239443194409f1a5342ecde1a092c8f3a3ed790a" }, -+ { 1001, "f278ab9a102850a9f48dc4e9e6822afe2d0c52b5" }, -+ { 1002, "8bcc667df5ab6ece988b3af361d09747c77f4e72" }, -+ { 1003, "0fae6046c7dc1d3e356b25af836f6077a363f338" }, -+ { 1004, "0ea48401cc92ae6bc92ae76685269cb0167fbe1a" }, -+ { 1005, "ecbcd7c879b295bafcd8766cbeac58cc371e31d1" }, -+ { 1006, "eb4a4a3d07d1e9a15e6f1ab8a9c47f243e27324c" }, -+ { 1336, "f5950ee1d77c10e9011d2149699c9366fe52529c" }, -+ { 1344, "b04263604a63c351b0b3b9cf1785b4bdba6c8838" }, -+ { 1399, "8cb1cff61d5b784045974a2fc69386e3b8d24218" }, -+ { 1400, "9bb2f3fcbeddb2b90f0be797cd647334a2816d51" }, -+ { 1401, "23ae462a7a0cb440f7445791079a5d75a535dd33" }, -+ { 1402, "832974b524a4d3f9cc2f45a3cabf5ccef65cd2aa" }, -+ { 1403, "d1c683742fe404c3c20d5704a5430e7832a7ec95" }, -+ { 1404, "867c79042e64f310628e219d8b85594cd0c7adc3" }, -+ { 1405, "c9d81d49d13d94358f56ccfd61af02b36c69f7c3" }, -+ { 1406, "0df43daab2786172f9b8d07d61f14a070cf1287a" }, -+ { 1407, "0fd8f3ad7f169534b274d4c66bbddd89f759e391" }, -+ { 1408, "3987511182b18473a564436003139b808fa46343" }, -+ { 1409, "ef667e063c9e9f539a8987a8d0bd3066ee85d901" }, -+ { 2048, "921109c99f3fedaca21727156d5f2b4460175327" }, -+ { 2049, "47188600dd165eb45f27c27196d3c46f4f042c1b" }, -+ { 2050, "8831939904009338de10e7fa670847041387807d" }, -+ { 2051, "2f8ebb5db2997d614e767be1050366f3641e7520" }, -+ { 2052, "669e51cd730dae158d3bef8adba075bd95a0d011" }, -+ { 3072, "cfee66cfd83abc8451af3c96c6b35a41cc6c55f5" }, -+ { 3074, "216ea26f02976a261b7d21a4dd3085157bedfabd" }, -+ { 3075, "bd612ebba021fd8e012b14c3bd60c8c5161fabc0" }, -+ { 4048, "c2564c1fdf2d5e9d7dde7aace2643428e90662e8" }, -+ { 4052, "91ce61fe924b445dfe7b5a1dcd10a27caec16df6" }, -+ { 4058, "db2a9be5ee8124f091c7ebd699266c5de223c164" }, -+ { 6144, "855109903feae2ba3a7a05a326b8a171116eb368" }, -+ { 6150, "37520bb3a668294d9c7b073e7e3daf8fee248a78" }, -+ { 6400, "60a353c841b6d2b1a05890349dad2fa33c7536b7" }, -+ { 6528, "9e53a43a69bb42d7c8522ca8bd632e421d5edb36" }, -+ { 8192, "a918cb0da862eaea0a33ee0efea50243e6b4927c" }, -+ { 8320, "29a5dcf55d1db29cd113fcf0572ae414f1c71329" }, -+ {16384, "6fb27966138e0c8d5a0d65ace817ebd53633cee1" }, -+ {18432, "ca09900d891c7c9ae2a559b10f63a217003341c1" }, -+ { 0, NULL }, -+}; -+ -+/* Key = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 -+ * 0x11, 0x12, 0x13, 0x14 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ */ -+static MV_CESA_SIZE_TEST shaMultiSizeTest404[] = -+{ -+ { 80, "beaf20a34b06a87558d156c0949bc3957d40222e" }, -+ { 512, "3353955358d886bc2940a3c7f337ff7dafb59c7b" }, -+ { 1000, "8737a542c5e9b2b6244b757ebb69d5bd602a829f" }, -+ { 1001, "fd9e7582d8a5d3c9fe3b923e4e6a41b07a1eb4d4" }, -+ { 1002, "a146d14a6fc3c274ff600568f4d75b977989e00d" }, -+ { 1003, "be22601bbc027ddef2dec97d30b3dc424fd803c5" }, -+ { 1004, "3e71fe99b2fe2b7bfdf4dbf0c7f3da25d7ea35e7" }, -+ { 1005, "2c422735d7295408fddd76f5e8a83a2a8da13df3" }, -+ { 1006, "6d875319049314b61855101a647b9ba3313428e6" }, -+ { 1336, "c1631ea80bad9dc43a180712461b65a0598c711c" }, -+ { 1344, "816069bf91d34581005746e2e0283d0f9c7b7605" }, -+ { 1399, "4e139866dc61cfcb8b67ca2ebd637b3a538593af" }, -+ { 1400, "ff2a0f8dd2b02c5417910f6f55d33a78e081a723" }, -+ { 1401, "ab00c12be62336964cbce31ae97fe2a0002984d5" }, -+ { 1402, "61349e7f999f3a1acc56c3e9a5060a9c4a7b05b6" }, -+ { 1403, "3edbc0f61e435bc1317fa27d840076093fb79353" }, -+ { 1404, "d052c6dfdbe63d45dab23ef9893e2aa4636aca1e" }, -+ { 1405, "0cc16b7388d67bf0add15a31e6e6c753cfae4987" }, -+ { 1406, "c96ba7eaad74253c38c22101b558d2850b1d1b90" }, -+ { 1407, "3445428a40d2c6556e7c55797ad8d323b61a48d9" }, -+ { 1408, "8d6444f937a09317c89834187b8ea9b8d3a8c56b" }, -+ { 1409, "c700acd3ecd19014ea2bdb4d42510c467e088475" }, -+ { 2048, "ee27d2a0cb77470c2f496212dfd68b5bb7b04e4b" }, -+ { 2049, "683762d7a02983b26a6d046e6451d9cd82c25932" }, -+ { 2050, "0fd20f1d55a9ee18363c2a6fd54aa13aee69992f" }, -+ { 2051, "86c267d8cc4bc8d59090e4f8b303da960fd228b7" }, -+ { 2052, "452395ae05b3ec503eea34f86fc0832485ad97c1" }, -+ { 3072, "75198e3cfd0b9bcff2dabdf8e38e6fdaa33ca49a" }, -+ { 3074, "4e24785ef080141ce4aab4675986d9acea624d7c" }, -+ { 3075, "3a20c5978dd637ec0e809bf84f0d9ccf30bc65bf" }, -+ { 4048, "3c32da256be7a7554922bf5fed51b0d2d09e59ad" }, -+ { 4052, "fff898426ea16e54325ae391a32c6c9bce4c23c0" }, -+ { 4058, "c800b9e562e1c91e1310116341a3c91d37f848ec" }, -+ { 6144, "d91d509d0cc4376c2d05bf9a5097717a373530e6" }, -+ { 6150, "d957030e0f13c5df07d9eec298542d8f94a07f12" }, -+ { 6400, "bb745313c3d7dc17b3f955e5534ad500a1082613" }, -+ { 6528, "77905f80d9ca82080bbb3e5654896dabfcfd1bdb" }, -+ { 8192, "5237fd9a81830c974396f99f32047586612ff3c0" }, -+ { 8320, "57668e28d5f2dba0839518a11db0f6af3d7e08bf" }, -+ {16384, "62e093fde467f0748087beea32e9af97d5c61241" }, -+ {18432, "845fb33130c7d6ea554fd5aacb9c50cf7ccb5929" }, -+ { 0, NULL }, -+}; -+ -+/* HASH-SHA1 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ * repeated "size" times -+ */ -+static MV_CESA_SIZE_TEST shaMultiSizeTest405[] = -+{ -+ { 80, "50abf5706a150990a08b2c5ea40fa0e585554732" }, -+ { 512, "f14516a08948fa27917a974d219741a697ba0087" }, -+ { 1000, "0bd18c378d5788817eb4f1e5dc07d867efa5cbf4" }, -+ { 1001, "ca29b85c35db1b8aef83c977893a11159d1b7aa2" }, -+ { 1002, "d83bc973eaaedb8a31437994dabbb3304b0be086" }, -+ { 1003, "2cf7bbef0acd6c00536b5c58ca470df9a3a90b6c" }, -+ { 1004, "e4375d09b1223385a8a393066f8209acfd936a80" }, -+ { 1005, "1029b38043e027745d019ce1d2d68e3d8b9d8f99" }, -+ { 1006, "deea16dcebbd8ac137e2b984deb639b9fb5e9680" }, -+ { 1336, "ea031b065fff63dcfb6a41956e4777520cdbc55d" }, -+ { 1344, "b52096c6445e6c0a8355995c70dc36ae186c863c" }, -+ { 1399, "cde2f6f8379870db4b32cf17471dc828a8dbff2b" }, -+ { 1400, "e53ff664064bc09fe5054c650806bd42d8179518" }, -+ { 1401, "d1156db5ddafcace64cdb510ff0d4af9b9a8ad64" }, -+ { 1402, "34ede0e9a909dd84a2ae291539105c0507b958e1" }, -+ { 1403, "a772ca3536da77e6ad3251e4f9e1234a4d7b87c0" }, -+ { 1404, "29740fd2b04e7a8bfd32242db6233156ad699948" }, -+ { 1405, "65b17397495b70ce4865dad93bf991b74c97cce1" }, -+ { 1406, "a7ee89cd0754061fdb91af7ea6abad2c69d542e3" }, -+ { 1407, "3eebf82f7420188e23d328b7ce93580b279a5715" }, -+ { 1408, "e08d3363a8b9a490dfb3a4c453452b8f114deeec" }, -+ { 1409, "95d74df739181a4ff30b8c39e28793a36598e924" }, -+ { 2048, "aa40262509c2abf84aab0197f83187fc90056d91" }, -+ { 2049, "7dec28ef105bc313bade8d9a7cdeac58b99de5ea" }, -+ { 2050, "d2e30f77ec81197de20f56588a156094ecb88450" }, -+ { 2051, "6b22ccc874833e96551a39da0c0edcaa0d969d92" }, -+ { 2052, "f843141e57875cd669af58744bc60aa9ea59549c" }, -+ { 3072, "09c5fedeaa62c132e673cc3c608a00142273d086" }, -+ { 3074, "b09e95eea9c7b1b007a58accec488301901a7f3d" }, -+ { 3075, "e6226b77b4ada287a8c9bbcf4ed71eec5ce632dc" }, -+ { 4048, "e99394894f855821951ddddf5bfc628547435f5c" }, -+ { 4052, "32d2f1af38be9cfba6cd03d55a254d0b3e1eb382" }, -+ { 4058, "d906552a4f2aca3a22e1fecccbcd183d7289d0ef" }, -+ { 6144, "2e7f62d35a860988e1224dc0543204af19316041" }, -+ { 6150, "d6b89698ee133df46fec9d552fadc328aa5a1b51" }, -+ { 6400, "dff50e90c46853988fa3a4b4ce5dda6945aae976" }, -+ { 6528, "9e63ec0430b96db02d38bc78357a2f63de2ab7f8" }, -+ { 8192, "971eb71ed60394d5ab5abb12e88420bdd41b5992" }, -+ { 8320, "91606a31b46afeaac965cecf87297e791b211013" }, -+ {16384, "547f830a5ec1f5f170ce818f156b1002cabc7569" }, -+ {18432, "f16f272787f3b8d539652e4dc315af6ab4fda0ef" }, -+ { 0, NULL }, -+}; -+ -+/* CryptoKey = 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef; -+ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ * Note: only sizes aligned to 3DES block size (8 bytes) allowed -+ */ -+static MV_CESA_SIZE_TEST tripleDesMdMultiSizeTest502[] = -+{ -+ { 64, "9586962a2aaaef28803dec2e17807a7f" }, -+ { 80, "b7726a03aad490bd6c5a452a89a1b271" }, -+ { 352, "f1ed9563aecc3c0d2766eb2bed3b4e4c" }, -+ { 512, "0f9decb11ab40fe86f4d4d9397bc020e" }, -+ { 1000, "3ba69deac12cab8ff9dff7dbd9669927" }, -+ { 1336, "6cf47bf1e80e03e2c1d0945bc50d37d2" }, -+ { 1344, "4be388dab21ceb3fa1b8d302e9b821f7" }, -+ { 1400, "a58b79fb21dd9bfc6ec93e3b99fb0ef1" }, -+ { 1408, "8bc97379fc2ac3237effcdd4f7a86528" }, -+ { 2048, "1339f03ab3076f25a20bc4cba16eb5bf" }, -+ { 3072, "731204d2d90c4b36ae41f5e1fb874288" }, -+ { 4048, "c028d998cfda5642547b7e1ed5ea16e4" }, -+ { 6144, "b1b19cd910cc51bd22992f1e59f1e068" }, -+ { 6400, "44e4613496ba622deb0e7cb768135a2f" }, -+ { 6528, "3b06b0a86f8db9cd67f9448dfcf10549" }, -+ { 8192, "d581780b7163138a0f412be681457d82" }, -+ {16384, "03b8ac05527faaf1bed03df149c65ccf" }, -+ {18432, "677c8a86a41dab6c5d81b85b8fb10ff6" }, -+ { 0, NULL }, -+}; -+ -+ -+/* CryptoKey = 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef; -+ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 -+ * 0x11, 0x12, 0x13, 0x14 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ * Note: only sizes aligned to 3DES block size (8 bytes) allowed -+ */ -+static MV_CESA_SIZE_TEST tripleDesShaMultiSizeTest503[] = -+{ -+ { 64, "44a1e9bcbfc1429630d9ea68b7a48b0427a684f2" }, -+ { 80, "b2ddeaca91030eab5b95a234ef2c0f6e738ff883" }, -+ { 352, "4b91864c7ff629bdff75d9726421f76705452aaf" }, -+ { 512, "6dd37faceeb2aa98ba74f4242ed6734a4d546af5" }, -+ { 1000, "463661c30300be512a9df40904f0757cde5f1141" }, -+ { 1336, "b931f831d9034fe59c65176400b039fe9c1f44a5" }, -+ { 1344, "af8866b1cd4a4887d6185bfe72470ffdfb3648e1" }, -+ { 1400, "49c6caf07296d5e31d2504d088bc5b20c3ee7cdb" }, -+ { 1408, "fcae8deedbc6ebf0763575dc7e9de075b448a0f4" }, -+ { 2048, "edece5012146c1faa0dd10f50b183ba5d2af58ac" }, -+ { 3072, "5b83625adb43a488b8d64fecf39bb766818547b7" }, -+ { 4048, "d2c533678d26c970293af60f14c8279dc708bfc9" }, -+ { 6144, "b8f67af4f991b08b725f969b049ebf813bfacc5c" }, -+ { 6400, "d9a6c7f746ac7a60ef2edbed2841cf851c25cfb0" }, -+ { 6528, "376792b8c8d18161d15579fb7829e6e3a27e9946" }, -+ { 8192, "d890eabdca195b34ef8724b28360cffa92ae5655" }, -+ {16384, "a167ee52639ec7bf19aee9c6e8f76667c14134b9" }, -+ {18432, "e4396ab56f67296b220985a12078f4a0e365d2cc" }, -+ { 0, NULL }, -+}; -+ -+/* CryptoKey = 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef -+ * IV = 0x12345678, 0x90abcdef -+ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ * Note: only sizes aligned to 3DES block size (8 bytes) allowed -+ */ -+static MV_CESA_SIZE_TEST cbc3desMdMultiSizeTest504[] = -+{ -+ { 64, "8d10e00802460ede0058c139ba48bd2d" }, -+ { 80, "6f463057e1a90e0e91ae505b527bcec0" }, -+ { 352, "4938d48bdf86aece2c6851e7c6079788" }, -+ { 512, "516705d59f3cf810ebf2a13a23a7d42e" }, -+ { 1000, "a5a000ee5c830e67ddc6a2d2e5644b31" }, -+ { 1336, "44af60087b74ed07950088efbe3b126a" }, -+ { 1344, "1f5b39e0577920af731dabbfcf6dfc2a" }, -+ { 1400, "6804ea640e29b9cd39e08bc37dbce734" }, -+ { 1408, "4fb436624b02516fc9d1535466574bf9" }, -+ { 2048, "c909b0985c423d8d86719f701e9e83db" }, -+ { 3072, "cfe0bc34ef97213ee3d3f8b10122db21" }, -+ { 4048, "03ea10b5ae4ddeb20aed6af373082ed1" }, -+ { 6144, "b9a0ff4f87fc14b3c2dc6f0ed0998fdf" }, -+ { 6400, "6995f85d9d4985dd99e974ec7dda9dd6" }, -+ { 6528, "bbbb548ce2fa3d58467f6a6a5168a0e6" }, -+ { 8192, "afe101fbe745bb449ae4f50d10801456" }, -+ {16384, "9741706d0b1c923340c4660ff97cacdf" }, -+ {18432, "b0217becb73cb8f61fd79c7ce9d023fb" }, -+ { 0, NULL }, -+}; -+ -+ -+/* CryptoKey = 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef; -+ * IV = 0x12345678, 0x90abcdef -+ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 -+ * 0x11, 0x12, 0x13, 0x14 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ * Note: only sizes aligned to 3DES block size (8 bytes) allowed -+ */ -+static MV_CESA_SIZE_TEST cbc3desShaMultiSizeTest505[] = -+{ -+ { 64, "409187e5bdb0be4a7754ca3747f7433dc4f01b98" }, -+ { 80, "1b002ed050be743aa98860cf35659646bb8efcc0" }, -+ { 352, "6cbf7ebe50fa4fa6eecc19eca23f9eae553ccfff" }, -+ { 512, "cfb5253fb4bf72b743320c30c7e48c54965853b0" }, -+ { 1000, "95e04e1ca2937e7c5a9aba9e42d2bcdb8a7af21f" }, -+ { 1336, "3b5c1f5eee5837ebf67b83ae01405542d77a6627" }, -+ { 1344, "2b3d42ab25615437f98a1ee310b81d07a02badc2" }, -+ { 1400, "7f8687df7c1af44e4baf3c934b6cca5ab6bc993e" }, -+ { 1408, "473a581c5f04f7527d50793c845471ac87e86430" }, -+ { 2048, "e41d20cae7ebe34e6e828ed62b1e5734019037bb" }, -+ { 3072, "275664afd7a561d804e6b0d204e53939cde653ae" }, -+ { 4048, "0d220cc5b34aeeb46bbbd637dde6290b5a8285a3" }, -+ { 6144, "cb393ddcc8b1c206060625b7d822ef9839e67bc5" }, -+ { 6400, "dd3317e2a627fc04800f74a4b05bfda00fab0347" }, -+ { 6528, "8a74c3b2441ab3f5a7e08895cc432566219a7c41" }, -+ { 8192, "b8e6ef3a549ed0e005bd5b8b1a5fe6689e9711a7" }, -+ {16384, "55f59404008276cdac0e2ba0d193af2d40eac5ce" }, -+ {18432, "86ae6c4fc72369a54cce39938e2d0296cd9c6ec5" }, -+ { 0, NULL }, -+}; -+ -+ -+/* CryptoKey = 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef -+ * IV = 0x12345678, 0x90abcdef -+ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ * Note: only sizes aligned to AES block size (16 bytes) allowed -+ */ -+static MV_CESA_SIZE_TEST cbcAes128md5multiSizeTest506[] = -+{ -+ { 16, "7ca4c2ba866751598720c5c4aa0d6786" }, -+ { 64, "7dba7fb988e80da609b1fea7254bced8" }, -+ { 80, "6b6e863ac5a71d15e3e9b1c86c9ba05f" }, -+ { 352, "a1ceb9c2e3021002400d525187a9f38c" }, -+ { 512, "596c055c1c55db748379223164075641" }, -+ { 1008, "f920989c02f3b3603f53c99d89492377" }, -+ { 1344, "2e496b73759d77ed32ea222dbd2e7b41" }, -+ { 1408, "7178c046b3a8d772efdb6a71c4991ea4" }, -+ { 2048, "a917f0099c69eb94079a8421714b6aad" }, -+ { 3072, "693cd5033d7f5391d3c958519fa9e934" }, -+ { 4048, "139dca91bcff65b3c40771749052906b" }, -+ { 6144, "428d9cef6df4fb70a6e9b6bbe4819e55" }, -+ { 6400, "9c0b909e76daa811e12b1fc17000a0c4" }, -+ { 6528, "ad876f6297186a7be1f1b907ed860eda" }, -+ { 8192, "479cbbaca37dd3191ea1f3e8134a0ef4" }, -+ {16384, "60fda559c74f91df538100c9842f2f15" }, -+ {18432, "4a3eb1cba1fa45f3981270953f720c42" }, -+ { 0, NULL }, -+}; -+ -+ -+/* CryptoKey = 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef; -+ * IV = 0x12345678, 0x90abcdef -+ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 -+ * 0x11, 0x12, 0x13, 0x14 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ * Note: only sizes aligned to AES block size (16 bytes) allowed -+ */ -+static MV_CESA_SIZE_TEST cbcAes128sha1multiSizeTest507[] = -+{ -+ { 16, "9aa8dc1c45f0946daf78057fa978759c625c1fee" }, -+ { 64, "9f588fc1ede851e5f8b20256abc9979465ae2189" }, -+ { 80, "13558472d1fc1c90dffec6e5136c7203452d509b" }, -+ { 352, "6b93518e006cfaa1f7adb24615e7291fb0a27e06" }, -+ { 512, "096874951a77fbbf333e49d80c096ee2016e09bd" }, -+ { 1008, "696fc203c2e4b5ae0ec5d1db3f623c490bc6dbac" }, -+ { 1344, "79bf77509935ccd3528caaac6a5eb6481f74029b" }, -+ { 1408, "627f9462b95fc188e8cfa7eec15119bdc5d4fcf1" }, -+ { 2048, "3d50d0c005feba92fe41502d609fced9c882b4d1" }, -+ { 3072, "758807e5b983e3a91c06fb218fe0f73f77111e94" }, -+ { 4048, "ca90e85242e33f005da3504416a52098d0d31fb2" }, -+ { 6144, "8044c1d4fd06642dfc46990b4f18b61ef1e972cf" }, -+ { 6400, "166f1f4ea57409f04feba9fb1e39af0e00bd6f43" }, -+ { 6528, "0389016a39485d6e330f8b4215ddf718b404f7e9" }, -+ { 8192, "6df7ee2a8b61d6f7f860ce8dbf778f0c2a5b508b" }, -+ {16384, "a70a6d8dfa1f91ded621c3dbaed34162bc48783f" }, -+ {18432, "8dfad627922ce15df1eed10bdbed49244efa57db" }, -+ { 0, NULL }, -+}; -+ -+ -+void cesaTestPrintStatus(void); -+ -+ -+/*------------------------- LOCAL FUNCTIONs ---------------------------------*/ -+MV_STATUS testCmd(int sid, int iter, MV_CESA_COMMAND* pCmd, -+ MV_CESA_TEST_SESSION* pTestSession, MV_U8* pIV, int ivSize); -+MV_STATUS testClose(int idx); -+MV_STATUS testOpen(int idx); -+void close_session(int sid); -+void cesaTestCheckReady(const MV_CESA_RESULT *r); -+void cesaCheckReady(MV_CESA_RESULT* r); -+void printTestResults(int idx, MV_STATUS status, int checkMode); -+void cesaLastResult(void); -+void cesaTestPrintReq(int req, int offset, int size); -+ -+void cesaTestPrintStatus(void); -+void cesaTestPrintSession(int idx); -+void sizeTest(int testIdx, int iter, int checkMode); -+void multiTest(int iter, int reqSize, int checkMode); -+void oneTest(int testIdx, int caseIdx,int iter, int reqSize, int checkMode); -+void multiSizeTest(int idx, int iter, int checkMode, char* inputData); -+void cesaTest(int iter, int reqSize, int checkMode); -+void cesaOneTest(int testIdx, int caseIdx,int iter, int reqSize, int checkMode); -+void combiTest(int iter, int reqSize, int checkMode); -+void shaTest(int iter, int reqSize, int checkMode); -+void mdTest(int iter, int reqSize, int checkMode); -+void aesTest(int iter, int reqSize, int checkMode); -+void tripleDesTest(int iter, int reqSize, int checkMode); -+void desTest(int iter, int reqSize, int checkMode); -+void cesaTestStop(void); -+MV_STATUS testRun(int idx, int caseIdx, int iter,int reqSize, int checkMode); -+void cesaTestStart(int bufNum, int bufSize); -+ -+ -+static MV_U32 getRate(MV_U32* remainder) -+{ -+ MV_U32 kBits, milliSec, rate; -+ -+ milliSec = 0; -+ if( (cesaEndTicks - cesaBeginTicks) > 0) -+ { -+ milliSec = CESA_TEST_TICK_TO_MS(cesaEndTicks - cesaBeginTicks); -+ } -+ if(milliSec == 0) -+ { -+ if(remainder != NULL) -+ *remainder = 0; -+ return 0; -+ } -+ -+ kBits = (cesaIteration*cesaRateSize*8)/1000; -+ rate = kBits/milliSec; -+ if(remainder != NULL) -+ *remainder = ((kBits % milliSec)*10)/milliSec; -+ -+ return rate; -+} -+ -+static char* extractMbuf(MV_CESA_MBUF *pMbuf, -+ int offset, int size, char* hexStr) -+{ -+ mvCesaCopyFromMbuf((MV_U8*)cesaBinBuffer, pMbuf, offset, size); -+ mvBinToHex((const MV_U8*)cesaBinBuffer, hexStr, size); -+ -+ return hexStr; -+} -+ -+static MV_BOOL cesaCheckMbuf(MV_CESA_MBUF *pMbuf, -+ const char* hexString, int offset, -+ int checkSize) -+{ -+ MV_BOOL isFailed = MV_FALSE; -+ MV_STATUS status; -+ int size = strlen(hexString)/2; -+ int checkedSize = 0; -+/* -+ mvOsPrintf("cesaCheckMbuf: pMbuf=%p, offset=%d, checkSize=%d, mBufSize=%d\n", -+ pMbuf, offset, checkSize, pMbuf->mbufSize); -+*/ -+ if(pMbuf->mbufSize < (checkSize + offset)) -+ { -+ mvOsPrintf("checkSize (%d) is too large: offset=%d, mbufSize=%d\n", -+ checkSize, offset, pMbuf->mbufSize); -+ return MV_TRUE; -+ } -+ status = mvCesaCopyFromMbuf((MV_U8*)cesaBinBuffer, pMbuf, offset, checkSize); -+ if(status != MV_OK) -+ { -+ mvOsPrintf("CesaTest: Can't copy %d bytes from Mbuf=%p to checkBuf=%p\n", -+ checkSize, pMbuf, cesaBinBuffer); -+ return MV_TRUE; -+ } -+/* -+ mvDebugMemDump(cesaBinBuffer, size, 1); -+*/ -+ mvHexToBin(hexString, (MV_U8*)cesaExpBinBuffer, size); -+ -+ /* Compare buffers */ -+ while(checkSize > checkedSize) -+ { -+ size = MV_MIN(size, (checkSize - checkedSize)); -+ if(memcmp(cesaExpBinBuffer, &cesaBinBuffer[checkedSize], size) != 0) -+ { -+ mvOsPrintf("CheckMbuf failed: checkSize=%d, size=%d, checkedSize=%d\n", -+ checkSize, size, checkedSize); -+ mvDebugMemDump(&cesaBinBuffer[checkedSize], size, 1); -+ mvDebugMemDump(cesaExpBinBuffer, size, 1); -+ -+ isFailed = MV_TRUE; -+ break; -+ } -+ checkedSize += size; -+ } -+ -+ return isFailed; -+} -+ -+static MV_STATUS cesaSetMbuf(MV_CESA_MBUF *pMbuf, -+ const char* hexString, -+ int offset, int reqSize) -+{ -+ MV_STATUS status = MV_OK; -+ int copySize, size = strlen(hexString)/2; -+ -+ mvHexToBin(hexString, (MV_U8*)cesaBinBuffer, size); -+ -+ copySize = 0; -+ while(reqSize > copySize) -+ { -+ size = MV_MIN(size, (reqSize - copySize)); -+ -+ status = mvCesaCopyToMbuf((MV_U8*)cesaBinBuffer, pMbuf, offset+copySize, size); -+ if(status != MV_OK) -+ { -+ mvOsPrintf("cesaSetMbuf Error: Copy %d of %d bytes to MBuf\n", -+ copySize, reqSize); -+ break; -+ } -+ copySize += size; -+ } -+ pMbuf->mbufSize = offset+copySize; -+ return status; -+} -+ -+static MV_CESA_TEST_SESSION* getTestSessionDb(int idx, int* pTestIdx) -+{ -+ int testIdx, dbIdx = idx/100; -+ -+ if(dbIdx > MAX_TEST_TYPE) -+ { -+ mvOsPrintf("Wrong index %d - No such test type\n", idx); -+ return NULL; -+ } -+ testIdx = idx % 100; -+ -+ if(testIdx >= cesaTestsDB[dbIdx].numSessions) -+ { -+ mvOsPrintf("Wrong index %d - No such test\n", idx); -+ return NULL; -+ } -+ if(pTestIdx != NULL) -+ *pTestIdx = testIdx; -+ -+ return cesaTestsDB[dbIdx].pSessions; -+} -+ -+/* Debug */ -+void cesaTestPrintReq(int req, int offset, int size) -+{ -+ MV_CESA_MBUF* pMbuf; -+ -+ mvOsPrintf("cesaTestPrintReq: req=%d, offset=%d, size=%d\n", -+ req, offset, size); -+ mvDebugMemDump(cesaCmdRing, 128, 4); -+ -+ pMbuf = cesaCmdRing[req].pSrc; -+ mvCesaDebugMbuf("src", pMbuf, offset,size); -+ pMbuf = cesaCmdRing[req].pDst; -+ mvCesaDebugMbuf("dst", pMbuf, offset, size); -+ -+ cesaTestPrintStatus(); -+} -+ -+void cesaLastResult(void) -+{ -+ mvOsPrintf("Last Result: ReqId = %d, SessionId = %d, rc = (%d)\n", -+ (MV_U32)cesaResult.pReqPrv, cesaResult.sessionId, -+ cesaResult.retCode); -+} -+ -+void printTestResults(int idx, MV_STATUS status, int checkMode) -+{ -+ int testIdx; -+ MV_CESA_TEST_SESSION* pTestSessions = getTestSessionDb(idx, &testIdx); -+ -+ if(pTestSessions == NULL) -+ return; -+ -+ mvOsPrintf("%-35s %4dx%-4d : ", pTestSessions[testIdx].name, -+ cesaIteration, cesaReqSize); -+ if( (status == MV_OK) && -+ (cesaCryptoError == 0) && -+ (cesaError == 0) && -+ (cesaReqIdError == 0) ) -+ { -+ mvOsPrintf("Passed, Rate=%3u.%u Mbps (%5u cpp)\n", -+ cesaRate, cesaRateAfterDot, cesaEndTicks - cesaBeginTicks); -+ } -+ else -+ { -+ mvOsPrintf("Failed, Status = 0x%x\n", status); -+ if(cesaCryptoError > 0) -+ mvOsPrintf("cryptoError : %d\n", cesaCryptoError); -+ if(cesaReqIdError > 0) -+ mvOsPrintf("reqIdError : %d\n", cesaReqIdError); -+ if(cesaError > 0) -+ mvOsPrintf("cesaError : %d\n", cesaError); -+ } -+ if(cesaTestIsrMissCount > 0) -+ mvOsPrintf("cesaIsrMissed : %d\n", cesaTestIsrMissCount); -+} -+ -+void cesaCheckReady(MV_CESA_RESULT* r) -+{ -+ int reqId; -+ MV_CESA_MBUF *pMbuf; -+ MV_BOOL isFailed; -+ -+ cesaResult = *r; -+ reqId = (int)cesaResult.pReqPrv; -+ pMbuf = cesaCmdRing[reqId].pDst; -+ -+/* -+ mvOsPrintf("cesaCheckReady: reqId=%d, checkOffset=%d, checkSize=%d\n", -+ reqId, cesaCheckOffset, cesaCheckSize); -+*/ -+ /* Check expected reqId */ -+ if(reqId != cesaExpReqId) -+ { -+ cesaReqIdError++; -+/* -+ mvOsPrintf("CESA reqId Error: cbIter=%d (%d), reqId=%d, expReqId=%d\n", -+ cesaCbIter, cesaIteration, reqId, cesaExpReqId); -+*/ -+ } -+ else -+ { -+ if( (cesaCheckMode == CESA_FULL_CHECK_MODE) || -+ (cesaCheckMode == CESA_FAST_CHECK_MODE) ) -+ { -+ if(cesaResult.retCode != MV_OK) -+ { -+ cesaError++; -+ -+ mvOsPrintf("CESA Error: cbIter=%d (%d), reqId=%d, rc=%d\n", -+ cesaCbIter, cesaIteration, reqId, cesaResult.retCode); -+ } -+ else -+ { -+ if( (cesaCheckSize > 0) && (cesaOutputHexStr != NULL) ) -+ { -+ /* Check expected output */ -+ -+ isFailed = cesaCheckMbuf(pMbuf, cesaOutputHexStr, cesaCheckOffset, cesaCheckSize); -+ if(isFailed) -+ { -+ mvOsPrintf("CESA Crypto Error: cbIter=%d (%d), reqId=%d\n", -+ cesaCbIter, cesaIteration, reqId); -+ -+ CESA_TEST_DEBUG_PRINT(("Error: reqId=%d, reqSize=%d, checkOffset=%d, checkSize=%d\n", -+ reqId, cesaReqSize, cesaCheckOffset, cesaCheckSize)); -+ -+ CESA_TEST_DEBUG_PRINT(("Output str: %s\n", cesaOutputHexStr)); -+ -+ CESA_TEST_DEBUG_CODE( mvCesaDebugMbuf("error", pMbuf, 0, cesaCheckOffset+cesaCheckSize) ); -+ -+ cesaCryptoError++; -+ } -+ } -+ } -+ } -+ } -+ if(cesaCheckMode == CESA_SHOW_CHECK_MODE) -+ { -+ extractMbuf(pMbuf, cesaCheckOffset, cesaCheckSize, cesaHexBuffer); -+ mvOsPrintf("%4d, %s\n", cesaCheckOffset, cesaHexBuffer); -+ } -+ -+ cesaCbIter++; -+ if(cesaCbIter >= cesaIteration) -+ { -+ cesaCbIter = 0; -+ cesaExpReqId = 0; -+ cesaIsReady = MV_TRUE; -+ -+ cesaEndTicks = CESA_TEST_TICK_GET(); -+ cesaRate = getRate(&cesaRateAfterDot); -+ } -+ else -+ { -+ cesaExpReqId = reqId + 1; -+ if(cesaExpReqId == CESA_DEF_REQ_SIZE) -+ cesaExpReqId = 0; -+ } -+} -+ -+ -+#ifdef MV_NETBSD -+static int cesaTestReadyIsr(void *arg) -+#else -+#ifdef __KERNEL__ -+static irqreturn_t cesaTestReadyIsr( int irq , void *dev_id) -+#endif -+#ifdef MV_VXWORKS -+void cesaTestReadyIsr(void) -+#endif -+#endif -+{ -+ MV_U32 cause; -+ MV_STATUS status; -+ MV_CESA_RESULT result; -+ -+ cesaTestIsrCount++; -+ /* Clear cause register */ -+ cause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); -+ if( (cause & MV_CESA_CAUSE_ACC_DMA_ALL_MASK) == 0) -+ { -+ mvOsPrintf("cesaTestReadyIsr: cause=0x%x\n", cause); -+#ifdef MV_NETBSD -+ return 0; -+#else -+#ifdef __KERNEL__ -+ return 1; -+#else -+ return; -+#endif -+#endif -+ } -+ -+ MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); -+ -+ while(MV_TRUE) -+ { -+ /* Get Ready requests */ -+ status = mvCesaReadyGet(&result); -+ if(status == MV_OK) -+ cesaCheckReady(&result); -+ -+ break; -+ } -+ if( (cesaTestFull == 1) && (status != MV_BUSY) ) -+ { -+ cesaTestFull = 0; -+ CESA_TEST_WAKE_UP(); -+ } -+ -+#ifdef __KERNEL__ -+ return 1; -+#endif -+} -+ -+void -+cesaTestCheckReady(const MV_CESA_RESULT *r) -+{ -+ MV_CESA_RESULT result = *r; -+ -+ cesaCheckReady(&result); -+ -+ if (cesaTestFull == 1) { -+ cesaTestFull = 0; -+ CESA_TEST_WAKE_UP(); -+ } -+} -+ -+static INLINE int open_session(MV_CESA_OPEN_SESSION* pOs) -+{ -+ MV_U16 sid; -+ MV_STATUS status; -+ -+ status = mvCesaSessionOpen(pOs, (short*)&sid); -+ if(status != MV_OK) -+ { -+ mvOsPrintf("CesaTest: Can't open new session - status = 0x%x\n", -+ status); -+ return -1; -+ } -+ -+ return (int)sid; -+} -+ -+void close_session(int sid) -+{ -+ MV_STATUS status; -+ -+ status = mvCesaSessionClose(sid); -+ if(status != MV_OK) -+ { -+ mvOsPrintf("CesaTest: Can't close session %d - status = 0x%x\n", -+ sid, status); -+ } -+} -+ -+MV_STATUS testOpen(int idx) -+{ -+ MV_CESA_OPEN_SESSION os; -+ int sid, i, testIdx; -+ MV_CESA_TEST_SESSION* pTestSession; -+ MV_U16 digestSize = 0; -+ -+ pTestSession = getTestSessionDb(idx, &testIdx); -+ if(pTestSession == NULL) -+ { -+ mvOsPrintf("Test %d is not exist\n", idx); -+ return MV_BAD_PARAM; -+ } -+ pTestSession = &pTestSession[testIdx]; -+ -+ if(pTestSession->sid != -1) -+ { -+ mvOsPrintf("Session for test %d already created: sid=%d\n", -+ idx, pTestSession->sid); -+ return MV_OK; -+ } -+ -+ os.cryptoAlgorithm = pTestSession->cryptoAlgorithm; -+ os.macMode = pTestSession->macAlgorithm; -+ switch(os.macMode) -+ { -+ case MV_CESA_MAC_MD5: -+ case MV_CESA_MAC_HMAC_MD5: -+ digestSize = MV_CESA_MD5_DIGEST_SIZE; -+ break; -+ -+ case MV_CESA_MAC_SHA1: -+ case MV_CESA_MAC_HMAC_SHA1: -+ digestSize = MV_CESA_SHA1_DIGEST_SIZE; -+ break; -+ -+ case MV_CESA_MAC_NULL: -+ digestSize = 0; -+ } -+ os.cryptoMode = pTestSession->cryptoMode; -+ os.direction = pTestSession->direction; -+ os.operation = pTestSession->operation; -+ -+ for(i=0; icryptoKeySize; i++) -+ os.cryptoKey[i] = pTestSession->pCryptoKey[i]; -+ -+ os.cryptoKeyLength = pTestSession->cryptoKeySize; -+ -+ for(i=0; imacKeySize; i++) -+ os.macKey[i] = pTestSession->pMacKey[i]; -+ -+ os.macKeyLength = pTestSession->macKeySize; -+ os.digestSize = digestSize; -+ -+ sid = open_session(&os); -+ if(sid == -1) -+ { -+ mvOsPrintf("Can't open session for test %d: rc=0x%x\n", -+ idx, cesaResult.retCode); -+ return cesaResult.retCode; -+ } -+ CESA_TEST_DEBUG_PRINT(("Opened session: sid = %d\n", sid)); -+ pTestSession->sid = sid; -+ return MV_OK; -+} -+ -+MV_STATUS testClose(int idx) -+{ -+ int testIdx; -+ MV_CESA_TEST_SESSION* pTestSession; -+ -+ pTestSession = getTestSessionDb(idx, &testIdx); -+ if(pTestSession == NULL) -+ { -+ mvOsPrintf("Test %d is not exist\n", idx); -+ return MV_BAD_PARAM; -+ } -+ pTestSession = &pTestSession[testIdx]; -+ -+ if(pTestSession->sid == -1) -+ { -+ mvOsPrintf("Test session %d is not opened\n", idx); -+ return MV_NO_SUCH; -+ } -+ -+ close_session(pTestSession->sid); -+ pTestSession->sid = -1; -+ -+ return MV_OK; -+} -+ -+MV_STATUS testCmd(int sid, int iter, MV_CESA_COMMAND* pCmd, -+ MV_CESA_TEST_SESSION* pTestSession, MV_U8* pIV, int ivSize) -+{ -+ int cmdReqId = 0; -+ int i; -+ MV_STATUS rc = MV_OK; -+ char ivZeroHex[] = "0000"; -+ -+ if(iter == 0) -+ iter = CESA_DEF_ITER_NUM; -+ -+ if(pCmd == NULL) -+ { -+ mvOsPrintf("testCmd failed: pCmd=NULL\n"); -+ return MV_BAD_PARAM; -+ } -+ pCmd->sessionId = sid; -+ -+ cesaCryptoError = 0; -+ cesaReqIdError = 0; -+ cesaError = 0; -+ cesaTestIsrMissCount = 0; -+ cesaIsReady = MV_FALSE; -+ cesaIteration = iter; -+ -+ if(cesaInputHexStr == NULL) -+ cesaInputHexStr = cesaPlainHexEbc; -+ -+ for(i=0; ipSrc = (MV_CESA_MBUF*)(cesaCmdRing[i].pSrc); -+ if(pIV != NULL) -+ { -+ /* If IV from SA - set IV in Source buffer to zeros */ -+ cesaSetMbuf(pCmd->pSrc, ivZeroHex, 0, pCmd->cryptoOffset); -+ cesaSetMbuf(pCmd->pSrc, cesaInputHexStr, pCmd->cryptoOffset, -+ (cesaReqSize - pCmd->cryptoOffset)); -+ } -+ else -+ { -+ cesaSetMbuf(pCmd->pSrc, cesaInputHexStr, 0, cesaReqSize); -+ } -+ pCmd->pDst = (MV_CESA_MBUF*)(cesaCmdRing[i].pDst); -+ cesaSetMbuf(pCmd->pDst, cesaNullPlainHexText, 0, cesaReqSize); -+ -+ memcpy(&cesaCmdRing[i], pCmd, sizeof(*pCmd)); -+ } -+ -+ if(cesaCheckMode == CESA_SW_SHOW_CHECK_MODE) -+ { -+ MV_U8 pDigest[MV_CESA_MAX_DIGEST_SIZE]; -+ -+ if(pTestSession->macAlgorithm == MV_CESA_MAC_MD5) -+ { -+ mvMD5(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, pDigest); -+ mvOsPrintf("SW HASH_MD5: reqSize=%d, macLength=%d\n", -+ cesaReqSize, pCmd->macLength); -+ mvDebugMemDump(pDigest, MV_CESA_MD5_DIGEST_SIZE, 1); -+ return MV_OK; -+ } -+ if(pTestSession->macAlgorithm == MV_CESA_MAC_SHA1) -+ { -+ mvSHA1(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, pDigest); -+ mvOsPrintf("SW HASH_SHA1: reqSize=%d, macLength=%d\n", -+ cesaReqSize, pCmd->macLength); -+ mvDebugMemDump(pDigest, MV_CESA_SHA1_DIGEST_SIZE, 1); -+ return MV_OK; -+ } -+ } -+ -+ cesaBeginTicks = CESA_TEST_TICK_GET(); -+ CESA_TEST_DEBUG_CODE( memset(cesaTestTrace, 0, sizeof(cesaTestTrace)); -+ cesaTestTraceIdx = 0; -+ ); -+ -+ if(cesaCheckMode == CESA_SW_NULL_CHECK_MODE) -+ { -+ volatile MV_U8 pDigest[MV_CESA_MAX_DIGEST_SIZE]; -+ -+ for(i=0; imacAlgorithm == MV_CESA_MAC_MD5) -+ { -+ mvMD5(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, (unsigned char*)pDigest); -+ } -+ if(pTestSession->macAlgorithm == MV_CESA_MAC_SHA1) -+ { -+ mvSHA1(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, (MV_U8 *)pDigest); -+ } -+ } -+ cesaEndTicks = CESA_TEST_TICK_GET(); -+ cesaRate = getRate(&cesaRateAfterDot); -+ cesaIsReady = MV_TRUE; -+ -+ return MV_OK; -+ } -+ -+ /*cesaTestIsrCount = 0;*/ -+ /*mvCesaDebugStatsClear();*/ -+ -+#ifndef MV_NETBSD -+ MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); -+#endif -+ -+ for(i=0; ipReqPrv = (void*)cmdReqId; -+ -+ CESA_TEST_LOCK(flags); -+ -+ rc = mvCesaAction(pCmd); -+ if(rc == MV_NO_RESOURCE) -+ cesaTestFull = 1; -+ -+ CESA_TEST_UNLOCK(flags); -+ -+ if(rc == MV_NO_RESOURCE) -+ { -+ CESA_TEST_LOCK(flags); -+ CESA_TEST_WAIT( (cesaTestFull == 0), 100); -+ CESA_TEST_UNLOCK(flags); -+ if(cesaTestFull == 1) -+ { -+ mvOsPrintf("CESA Test timeout: i=%d, iter=%d, cesaTestFull=%d\n", -+ i, iter, cesaTestFull); -+ cesaTestFull = 0; -+ return MV_TIMEOUT; -+ } -+ -+ CESA_TEST_LOCK(flags); -+ -+ rc = mvCesaAction(pCmd); -+ -+ CESA_TEST_UNLOCK(flags); -+ } -+ if( (rc != MV_OK) && (rc != MV_NO_MORE) ) -+ { -+ mvOsPrintf("mvCesaAction failed: rc=%d\n", rc); -+ return rc; -+ } -+ -+ cmdReqId++; -+ if(cmdReqId >= CESA_DEF_REQ_SIZE) -+ cmdReqId = 0; -+ -+#ifdef MV_LINUX -+ /* Reschedule each 16 requests */ -+ if( (i & 0xF) == 0) -+ schedule(); -+#endif -+ } -+ return MV_OK; -+} -+ -+void cesaTestStart(int bufNum, int bufSize) -+{ -+ int i, j, idx; -+ MV_CESA_MBUF *pMbufSrc, *pMbufDst; -+ MV_BUF_INFO *pFragsSrc, *pFragsDst; -+ char *pBuf; -+#ifndef MV_NETBSD -+ int numOfSessions, queueDepth; -+ char *pSram; -+ MV_STATUS status; -+ MV_CPU_DEC_WIN addrDecWin; -+#endif -+ -+ cesaCmdRing = mvOsMalloc(sizeof(MV_CESA_COMMAND) * CESA_DEF_REQ_SIZE); -+ if(cesaCmdRing == NULL) -+ { -+ mvOsPrintf("testStart: Can't allocate %ld bytes of memory\n", -+ sizeof(MV_CESA_COMMAND) * CESA_DEF_REQ_SIZE); -+ return; -+ } -+ memset(cesaCmdRing, 0, sizeof(MV_CESA_COMMAND) * CESA_DEF_REQ_SIZE); -+ -+ if(bufNum == 0) -+ bufNum = CESA_DEF_BUF_NUM; -+ -+ if(bufSize == 0) -+ bufSize = CESA_DEF_BUF_SIZE; -+ -+ cesaBufNum = bufNum; -+ cesaBufSize = bufSize; -+ mvOsPrintf("CESA test started: bufNum = %d, bufSize = %d\n", -+ bufNum, bufSize); -+ -+ cesaHexBuffer = mvOsMalloc(2*bufNum*bufSize); -+ if(cesaHexBuffer == NULL) -+ { -+ mvOsPrintf("testStart: Can't malloc %d bytes for cesaHexBuffer.\n", -+ 2*bufNum*bufSize); -+ return; -+ } -+ memset(cesaHexBuffer, 0, (2*bufNum*bufSize)); -+ -+ cesaBinBuffer = mvOsMalloc(bufNum*bufSize); -+ if(cesaBinBuffer == NULL) -+ { -+ mvOsPrintf("testStart: Can't malloc %d bytes for cesaBinBuffer\n", -+ bufNum*bufSize); -+ return; -+ } -+ memset(cesaBinBuffer, 0, (bufNum*bufSize)); -+ -+ cesaExpBinBuffer = mvOsMalloc(bufNum*bufSize); -+ if(cesaExpBinBuffer == NULL) -+ { -+ mvOsPrintf("testStart: Can't malloc %d bytes for cesaExpBinBuffer\n", -+ bufNum*bufSize); -+ return; -+ } -+ memset(cesaExpBinBuffer, 0, (bufNum*bufSize)); -+ -+ CESA_TEST_WAIT_INIT(); -+ -+ pMbufSrc = mvOsMalloc(sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); -+ pFragsSrc = mvOsMalloc(sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); -+ -+ pMbufDst = mvOsMalloc(sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); -+ pFragsDst = mvOsMalloc(sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); -+ -+ if( (pMbufSrc == NULL) || (pFragsSrc == NULL) || -+ (pMbufDst == NULL) || (pFragsDst == NULL) ) -+ { -+ mvOsPrintf("testStart: Can't malloc Src and Dst pMbuf and pFrags structures.\n"); -+ /* !!!! Dima cesaTestCleanup();*/ -+ return; -+ } -+ -+ memset(pMbufSrc, 0, sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); -+ memset(pFragsSrc, 0, sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); -+ -+ memset(pMbufDst, 0, sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); -+ memset(pFragsDst, 0, sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); -+ -+ mvOsPrintf("Cesa Test Start: pMbufSrc=%p, pFragsSrc=%p, pMbufDst=%p, pFragsDst=%p\n", -+ pMbufSrc, pFragsSrc, pMbufDst, pFragsDst); -+ -+ idx = 0; -+ for(i=0; ipFrags = &pFragsSrc[idx]; -+ cesaCmdRing[i].pSrc->numFrags = bufNum; -+ cesaCmdRing[i].pSrc->mbufSize = 0; -+ -+ cesaCmdRing[i].pDst = &pMbufDst[i]; -+ cesaCmdRing[i].pDst->pFrags = &pFragsDst[idx]; -+ cesaCmdRing[i].pDst->numFrags = bufNum; -+ cesaCmdRing[i].pDst->mbufSize = 0; -+ -+ for(j=0; jpFrags[j].bufVirtPtr = (MV_U8*)pBuf; -+ cesaCmdRing[i].pSrc->pFrags[j].bufSize = bufSize; -+ pBuf += bufSize; -+ cesaCmdRing[i].pDst->pFrags[j].bufVirtPtr = (MV_U8*)pBuf; -+ cesaCmdRing[i].pDst->pFrags[j].bufSize = bufSize; -+ pBuf += bufSize; -+ } -+ idx += bufNum; -+ } -+ -+#ifndef MV_NETBSD -+ if (mvCpuIfTargetWinGet(CRYPT_ENG, &addrDecWin) == MV_OK) -+ pSram = (char*)addrDecWin.addrWin.baseLow; -+ else -+ { -+ mvOsPrintf("mvCesaInit: ERR. mvCpuIfTargetWinGet failed\n"); -+ return; -+ } -+ -+#ifdef MV_CESA_NO_SRAM -+ pSram = mvOsMalloc(4*1024+8); -+ if(pSram == NULL) -+ { -+ mvOsPrintf("CesaTest: can't allocate %d bytes for SRAM simulation\n", -+ 4*1024+8); -+ /* !!!! Dima cesaTestCleanup();*/ -+ return; -+ } -+ pSram = (MV_U8*)MV_ALIGN_UP((MV_U32)pSram, 8); -+#endif /* MV_CESA_NO_SRAM */ -+ -+ numOfSessions = CESA_DEF_SESSION_NUM; -+ queueDepth = CESA_DEF_REQ_SIZE - MV_CESA_MAX_CHAN; -+ -+ status = mvCesaInit(numOfSessions, queueDepth, pSram, NULL); -+ if(status != MV_OK) -+ { -+ mvOsPrintf("mvCesaInit is Failed: status = 0x%x\n", status); -+ /* !!!! Dima cesaTestCleanup();*/ -+ return; -+ } -+#endif /* !MV_NETBSD */ -+ -+ /* Prepare data for tests */ -+ for(i=0; i<50; i++) -+ strcat((char*)cesaDataHexStr3, "dd"); -+ -+ strcpy((char*)cesaDataAndMd5digest3, cesaDataHexStr3); -+ strcpy((char*)cesaDataAndSha1digest3, cesaDataHexStr3); -+ -+ /* Digest must be 8 byte aligned */ -+ for(; i<56; i++) -+ { -+ strcat((char*)cesaDataAndMd5digest3, "00"); -+ strcat((char*)cesaDataAndSha1digest3, "00"); -+ } -+ strcat((char*)cesaDataAndMd5digest3, cesaHmacMd5digestHex3); -+ strcat((char*)cesaDataAndSha1digest3, cesaHmacSha1digestHex3); -+ -+#ifndef MV_NETBSD -+ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); -+ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, MV_CESA_CAUSE_ACC_DMA_MASK); -+#endif -+ -+#ifdef MV_VXWORKS -+ { -+ MV_STATUS status; -+ -+ status = intConnect((VOIDFUNCPTR *)INT_LVL_CESA, cesaTestReadyIsr, (int)NULL); -+ if (status != OK) -+ { -+ mvOsPrintf("CESA: Can't connect CESA (%d) interrupt, status=0x%x \n", -+ INT_LVL_CESA, status); -+ /* !!!! Dima cesaTestCleanup();*/ -+ return; -+ } -+ cesaSemId = semMCreate(SEM_Q_PRIORITY | SEM_INVERSION_SAFE | SEM_DELETE_SAFE); -+ if(cesaSemId == NULL) -+ { -+ mvOsPrintf("cesaTestStart: Can't create semaphore\n"); -+ return; -+ } -+ intEnable(INT_LVL_CESA); -+ } -+#endif /* MV_VXWORKS */ -+ -+#if !defined(MV_NETBSD) && defined(__KERNEL__) -+ if( request_irq(CESA_IRQ, cesaTestReadyIsr, (SA_INTERRUPT) , "cesa_test", NULL ) ) -+ { -+ mvOsPrintf( "cannot assign irq\n" ); -+ /* !!!! Dima cesaTestCleanup();*/ -+ return; -+ } -+ spin_lock_init( &cesaLock ); -+#endif -+} -+ -+MV_STATUS testRun(int idx, int caseIdx, int iter, -+ int reqSize, int checkMode) -+{ -+ int testIdx, count, sid, digestSize; -+ int blockSize; -+ MV_CESA_TEST_SESSION* pTestSession; -+ MV_CESA_COMMAND cmd; -+ MV_STATUS status; -+ -+ memset(&cmd, 0, sizeof(cmd)); -+ -+ pTestSession = getTestSessionDb(idx, &testIdx); -+ if(pTestSession == NULL) -+ { -+ mvOsPrintf("Test %d is not exist\n", idx); -+ return MV_BAD_PARAM; -+ } -+ pTestSession = &pTestSession[testIdx]; -+ -+ sid = pTestSession->sid; -+ if(sid == -1) -+ { -+ mvOsPrintf("Test %d is not opened\n", idx); -+ return MV_BAD_STATE; -+ } -+ switch(pTestSession->cryptoAlgorithm) -+ { -+ case MV_CESA_CRYPTO_DES: -+ case MV_CESA_CRYPTO_3DES: -+ blockSize = MV_CESA_DES_BLOCK_SIZE; -+ break; -+ -+ case MV_CESA_CRYPTO_AES: -+ blockSize = MV_CESA_AES_BLOCK_SIZE; -+ break; -+ -+ case MV_CESA_CRYPTO_NULL: -+ blockSize = 0; -+ break; -+ -+ default: -+ mvOsPrintf("cesaTestRun: Bad CryptoAlgorithm=%d\n", -+ pTestSession->cryptoAlgorithm); -+ return MV_BAD_PARAM; -+ } -+ switch(pTestSession->macAlgorithm) -+ { -+ case MV_CESA_MAC_MD5: -+ case MV_CESA_MAC_HMAC_MD5: -+ digestSize = MV_CESA_MD5_DIGEST_SIZE; -+ break; -+ -+ case MV_CESA_MAC_SHA1: -+ case MV_CESA_MAC_HMAC_SHA1: -+ digestSize = MV_CESA_SHA1_DIGEST_SIZE; -+ break; -+ default: -+ digestSize = 0; -+ } -+ -+ if(iter == 0) -+ iter = CESA_DEF_ITER_NUM; -+ -+ if(pTestSession->direction == MV_CESA_DIR_ENCODE) -+ { -+ cesaOutputHexStr = cesaTestCases[caseIdx].cipherHexStr; -+ cesaInputHexStr = cesaTestCases[caseIdx].plainHexStr; -+ } -+ else -+ { -+ cesaOutputHexStr = cesaTestCases[caseIdx].plainHexStr; -+ cesaInputHexStr = cesaTestCases[caseIdx].cipherHexStr; -+ } -+ -+ cmd.sessionId = sid; -+ if(checkMode == CESA_FAST_CHECK_MODE) -+ { -+ cmd.cryptoLength = cesaTestCases[caseIdx].cryptoLength; -+ cmd.macLength = cesaTestCases[caseIdx].macLength; -+ } -+ else -+ { -+ cmd.cryptoLength = reqSize; -+ cmd.macLength = reqSize; -+ } -+ cesaRateSize = cmd.cryptoLength; -+ cesaReqSize = cmd.cryptoLength; -+ cmd.cryptoOffset = 0; -+ if(pTestSession->operation != MV_CESA_MAC_ONLY) -+ { -+ if( (pTestSession->cryptoMode == MV_CESA_CRYPTO_CBC) || -+ (pTestSession->cryptoMode == MV_CESA_CRYPTO_CTR) ) -+ { -+ cmd.ivOffset = 0; -+ cmd.cryptoOffset = blockSize; -+ if(cesaTestCases[caseIdx].pCryptoIV == NULL) -+ { -+ cmd.ivFromUser = 1; -+ } -+ else -+ { -+ cmd.ivFromUser = 0; -+ mvCesaCryptoIvSet(cesaTestCases[caseIdx].pCryptoIV, blockSize); -+ } -+ cesaReqSize = cmd.cryptoOffset + cmd.cryptoLength; -+ } -+ } -+ -+/* -+ mvOsPrintf("ivFromUser=%d, cryptoLength=%d, cesaReqSize=%d, cryptoOffset=%d\n", -+ cmd.ivFromUser, cmd.cryptoLength, cesaReqSize, cmd.cryptoOffset); -+*/ -+ if(pTestSession->operation != MV_CESA_CRYPTO_ONLY) -+ { -+ cmd.macOffset = cmd.cryptoOffset; -+ -+ if(cesaTestCases[caseIdx].digestOffset == -1) -+ { -+ cmd.digestOffset = cmd.macOffset + cmd.macLength; -+ cmd.digestOffset = MV_ALIGN_UP(cmd.digestOffset, 8); -+ } -+ else -+ { -+ cmd.digestOffset = cesaTestCases[caseIdx].digestOffset; -+ } -+ if( (cmd.digestOffset + digestSize) > cesaReqSize) -+ cesaReqSize = cmd.digestOffset + digestSize; -+ } -+ -+ cesaCheckMode = checkMode; -+ -+ if(checkMode == CESA_NULL_CHECK_MODE) -+ { -+ cesaCheckSize = 0; -+ cesaCheckOffset = 0; -+ } -+ else -+ { -+ if(pTestSession->operation == MV_CESA_CRYPTO_ONLY) -+ { -+ cesaCheckOffset = 0; -+ cesaCheckSize = cmd.cryptoLength; -+ } -+ else -+ { -+ cesaCheckSize = digestSize; -+ cesaCheckOffset = cmd.digestOffset; -+ } -+ } -+/* -+ mvOsPrintf("reqSize=%d, checkSize=%d, checkOffset=%d, checkMode=%d\n", -+ cesaReqSize, cesaCheckSize, cesaCheckOffset, cesaCheckMode); -+ -+ mvOsPrintf("blockSize=%d, ivOffset=%d, ivFromUser=%d, crOffset=%d, crLength=%d\n", -+ blockSize, cmd.ivOffset, cmd.ivFromUser, -+ cmd.cryptoOffset, cmd.cryptoLength); -+ -+ mvOsPrintf("macOffset=%d, digestOffset=%d, macLength=%d\n", -+ cmd.macOffset, cmd.digestOffset, cmd.macLength); -+*/ -+ status = testCmd(sid, iter, &cmd, pTestSession, -+ cesaTestCases[caseIdx].pCryptoIV, blockSize); -+ -+ if(status != MV_OK) -+ return status; -+ -+ /* Wait when all callbacks is received */ -+ count = 0; -+ while(cesaIsReady == MV_FALSE) -+ { -+ mvOsSleep(10); -+ count++; -+ if(count > 100) -+ { -+ mvOsPrintf("testRun: Timeout occured\n"); -+ return MV_TIMEOUT; -+ } -+ } -+ -+ return MV_OK; -+} -+ -+ -+void cesaTestStop(void) -+{ -+ MV_CESA_MBUF *pMbufSrc, *pMbufDst; -+ MV_BUF_INFO *pFragsSrc, *pFragsDst; -+ int i; -+ -+ /* Release all allocated memories */ -+ pMbufSrc = (MV_CESA_MBUF*)(cesaCmdRing[0].pSrc); -+ pFragsSrc = cesaCmdRing[0].pSrc->pFrags; -+ -+ pMbufDst = (MV_CESA_MBUF*)(cesaCmdRing[0].pDst); -+ pFragsDst = cesaCmdRing[0].pDst->pFrags; -+ -+ mvOsFree(pMbufSrc); -+ mvOsFree(pMbufDst); -+ mvOsFree(pFragsSrc); -+ mvOsFree(pFragsDst); -+ -+ for(i=0; i 0) -+ cryptoError++; -+ if(cesaReqIdError > 0) -+ reqIdError++; -+ -+ testClose(idx); -+ } -+ } -+ if(cryptoError > 0) -+ mvOsPrintf("cryptoError : %d\n", cryptoError); -+ if(reqIdError > 0) -+ mvOsPrintf("reqIdError : %d\n", reqIdError); -+ -+ if(openErrors > 0) -+ { -+ mvOsPrintf("Open Errors = %d\n", openErrors); -+ for(i=0; i<100; i++) -+ { -+ if(openErrDisp[i] != 0) -+ mvOsPrintf("Error %d - occurs %d times\n", i, openErrDisp[i]); -+ } -+ } -+} -+ -+ -+void loopback_test(int idx, int iter, int size, char* pPlainData) -+{ -+} -+ -+ -+#if defined(MV_VXWORKS) -+int testMode = 0; -+unsigned __TASKCONV cesaTask(void* args) -+{ -+ int reqSize = cesaReqSize; -+ -+ if(testMode == 0) -+ { -+ cesaOneTest(cesaTestIdx, cesaCaseIdx, cesaIteration, -+ reqSize, cesaCheckMode); -+ } -+ else -+ { -+ if(testMode == 1) -+ { -+ cesaTest(cesaIteration, reqSize, cesaCheckMode); -+ combiTest(cesaIteration, reqSize, cesaCheckMode); -+ } -+ else -+ { -+ multiSizeTest(cesaIdx, cesaIteration, cesaCheckMode, NULL); -+ } -+ } -+ return 0; -+} -+ -+void oneTest(int testIdx, int caseIdx, -+ int iter, int reqSize, int checkMode) -+{ -+ long rc; -+ -+ cesaIteration = iter; -+ cesaReqSize = cesaRateSize = reqSize; -+ cesaCheckMode = checkMode; -+ testMode = 0; -+ cesaTestIdx = testIdx; -+ cesaCaseIdx = caseIdx; -+ rc = mvOsTaskCreate("CESA_T", 100, 4*1024, cesaTask, NULL, &cesaTaskId); -+ if (rc != MV_OK) -+ { -+ mvOsPrintf("hMW: Can't create CESA multiCmd test task, rc = %ld\n", rc); -+ } -+} -+ -+void multiTest(int iter, int reqSize, int checkMode) -+{ -+ long rc; -+ -+ cesaIteration = iter; -+ cesaCheckMode = checkMode; -+ cesaReqSize = reqSize; -+ testMode = 1; -+ rc = mvOsTaskCreate("CESA_T", 100, 4*1024, cesaTask, NULL, &cesaTaskId); -+ if (rc != MV_OK) -+ { -+ mvOsPrintf("hMW: Can't create CESA multiCmd test task, rc = %ld\n", rc); -+ } -+} -+ -+void sizeTest(int testIdx, int iter, int checkMode) -+{ -+ long rc; -+ -+ cesaIteration = iter; -+ cesaCheckMode = checkMode; -+ testMode = 2; -+ cesaIdx = testIdx; -+ rc = mvOsTaskCreate("CESA_T", 100, 4*1024, cesaTask, NULL, &cesaTaskId); -+ if (rc != MV_OK) -+ { -+ mvOsPrintf("hMW: Can't create CESA test task, rc = %ld\n", rc); -+ } -+} -+ -+#endif /* MV_VXWORKS */ -+ -+extern void mvCesaDebugSA(short sid, int mode); -+void cesaTestPrintSession(int idx) -+{ -+ int testIdx; -+ MV_CESA_TEST_SESSION* pTestSession; -+ -+ pTestSession = getTestSessionDb(idx, &testIdx); -+ if(pTestSession == NULL) -+ { -+ mvOsPrintf("Test %d is not exist\n", idx); -+ return; -+ } -+ pTestSession = &pTestSession[testIdx]; -+ -+ if(pTestSession->sid == -1) -+ { -+ mvOsPrintf("Test session %d is not opened\n", idx); -+ return; -+ } -+ -+ mvCesaDebugSA(pTestSession->sid, 1); -+} -+ -+void cesaTestPrintStatus(void) -+{ -+ mvOsPrintf("\n\t Cesa Test Status\n\n"); -+ -+ mvOsPrintf("isrCount=%d\n", -+ cesaTestIsrCount); -+ -+#ifdef CESA_TEST_DEBUG -+ { -+ int i, j; -+ j = cesaTestTraceIdx; -+ mvOsPrintf("No Type Cause rCause iCause Res Time pReady pProc pEmpty\n"); -+ for(i=0; itable = mvOsMalloc(numOfEntries*sizeof(MV_LRU_ENTRY)); -+ if(pLruCache->table == NULL) -+ { -+ mvOsFree(pLruCache); -+ return NULL; -+ } -+ memset(pLruCache->table, 0, numOfEntries*sizeof(MV_LRU_ENTRY)); -+ pLruCache->tableSize = numOfEntries; -+ -+ for(i=0; itable[i].next = i+1; -+ pLruCache->table[i].prev = i-1; -+ } -+ pLruCache->least = 0; -+ pLruCache->most = numOfEntries-1; -+ -+ return pLruCache; -+} -+ -+void mvLruCacheFinish(MV_LRU_CACHE* pLruCache) -+{ -+ mvOsFree(pLruCache->table); -+ mvOsFree(pLruCache); -+} -+ -+/* Update LRU cache database after using cache Index */ -+void mvLruCacheIdxUpdate(MV_LRU_CACHE* pLruHndl, int cacheIdx) -+{ -+ int prev, next; -+ -+ if(cacheIdx == pLruHndl->most) -+ return; -+ -+ next = pLruHndl->table[cacheIdx].next; -+ if(cacheIdx == pLruHndl->least) -+ { -+ pLruHndl->least = next; -+ } -+ else -+ { -+ prev = pLruHndl->table[cacheIdx].prev; -+ -+ pLruHndl->table[next].prev = prev; -+ pLruHndl->table[prev].next = next; -+ } -+ -+ pLruHndl->table[pLruHndl->most].next = cacheIdx; -+ pLruHndl->table[cacheIdx].prev = pLruHndl->most; -+ pLruHndl->most = cacheIdx; -+} -+ -+/* Delete LRU cache entry */ -+void mvLruCacheIdxDelete(MV_LRU_CACHE* pLruHndl, int cacheIdx) -+{ -+ int prev, next; -+ -+ if(cacheIdx == pLruHndl->least) -+ return; -+ -+ prev = pLruHndl->table[cacheIdx].prev; -+ if(cacheIdx == pLruHndl->most) -+ { -+ pLruHndl->most = prev; -+ } -+ else -+ { -+ next = pLruHndl->table[cacheIdx].next; -+ -+ pLruHndl->table[next].prev = prev; -+ pLruHndl->table[prev].next = next; -+ } -+ pLruHndl->table[pLruHndl->least].prev = cacheIdx; -+ pLruHndl->table[cacheIdx].next = pLruHndl->least; -+ pLruHndl->least = cacheIdx; -+} -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/cesa/mvLru.h linux-2.6.36/crypto/ocf/kirkwood/cesa/mvLru.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/cesa/mvLru.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/cesa/mvLru.h 2010-11-09 20:28:05.861235773 +0100 -@@ -0,0 +1,112 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+/******************************************************************************* -+* mvLru.h - Header File for Least Recently Used Cache algorithm -+* -+* DESCRIPTION: -+* This header file contains macros typedefs and function declaration for -+* the Least Recently Used Cache algorithm. -+* -+*******************************************************************************/ -+ -+#ifndef __mvLru_h__ -+#define __mvLru_h__ -+ -+ -+typedef struct -+{ -+ int next; -+ int prev; -+} MV_LRU_ENTRY; -+ -+typedef struct -+{ -+ int least; -+ int most; -+ MV_LRU_ENTRY* table; -+ int tableSize; -+ -+}MV_LRU_CACHE; -+ -+ -+/* Find Cache index for replacement LRU */ -+static INLINE int mvLruCacheIdxFind(MV_LRU_CACHE* pLruHndl) -+{ -+ return pLruHndl->least; -+} -+ -+/* Init LRU cache module */ -+MV_LRU_CACHE* mvLruCacheInit(int numOfEntries); -+ -+/* Finish LRU cache module */ -+void mvLruCacheFinish(MV_LRU_CACHE* pLruHndl); -+ -+/* Update LRU cache database after using cache Index */ -+void mvLruCacheIdxUpdate(MV_LRU_CACHE* pLruHndl, int cacheIdx); -+ -+/* Delete LRU cache entry */ -+void mvLruCacheIdxDelete(MV_LRU_CACHE* pLruHndl, int cacheIdx); -+ -+ -+#endif /* __mvLru_h__ */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/cesa/mvMD5.c linux-2.6.36/crypto/ocf/kirkwood/cesa/mvMD5.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/cesa/mvMD5.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/cesa/mvMD5.c 2010-11-09 20:28:05.902495799 +0100 -@@ -0,0 +1,349 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "mvOs.h" -+#include "mvMD5.h" -+ -+static void mvMD5Transform(MV_U32 buf[4], MV_U32 const in[MV_MD5_MAC_LEN]); -+ -+#ifdef MV_CPU_LE -+#define mvByteReverse(buf, len) /* Nothing */ -+#else -+static void mvByteReverse(unsigned char *buf, unsigned longs); -+ -+/* -+ * Note: this code is harmless on little-endian machines. -+ */ -+static void mvByteReverse(unsigned char *buf, unsigned longs) -+{ -+ MV_U32 t; -+ -+ do -+ { -+ t = (MV_U32) ((unsigned) buf[3] << 8 | buf[2]) << 16 | -+ ((unsigned) buf[1] << 8 | buf[0]); -+ *(MV_U32 *) buf = t; -+ buf += 4; -+ } while (--longs); -+} -+#endif -+ -+/* -+ * Start MD5 accumulation. Set bit count to 0 and buffer to mysterious -+ * initialization constants. -+ */ -+void mvMD5Init(MV_MD5_CONTEXT *ctx) -+{ -+ ctx->buf[0] = 0x67452301; -+ ctx->buf[1] = 0xefcdab89; -+ ctx->buf[2] = 0x98badcfe; -+ ctx->buf[3] = 0x10325476; -+ -+ ctx->bits[0] = 0; -+ ctx->bits[1] = 0; -+} -+ -+/* -+ * Update context to reflect the concatenation of another buffer full -+ * of bytes. -+ */ -+void mvMD5Update(MV_MD5_CONTEXT *ctx, unsigned char const *buf, unsigned len) -+{ -+ MV_U32 t; -+ -+ /* Update bitcount */ -+ -+ t = ctx->bits[0]; -+ if ((ctx->bits[0] = t + ((MV_U32) len << 3)) < t) -+ ctx->bits[1]++; /* Carry from low to high */ -+ ctx->bits[1] += len >> 29; -+ -+ t = (t >> 3) & 0x3f; /* Bytes already in shsInfo->data */ -+ -+ /* Handle any leading odd-sized chunks */ -+ -+ if (t) -+ { -+ unsigned char *p = (unsigned char *) ctx->in + t; -+ -+ t = 64 - t; -+ if (len < t) -+ { -+ memcpy(p, buf, len); -+ return; -+ } -+ memcpy(p, buf, t); -+ mvByteReverse(ctx->in, MV_MD5_MAC_LEN); -+ mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in); -+ buf += t; -+ len -= t; -+ } -+ /* Process data in 64-byte chunks */ -+ -+ while (len >= 64) -+ { -+ memcpy(ctx->in, buf, 64); -+ mvByteReverse(ctx->in, MV_MD5_MAC_LEN); -+ mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in); -+ buf += 64; -+ len -= 64; -+ } -+ -+ /* Handle any remaining bytes of data. */ -+ -+ memcpy(ctx->in, buf, len); -+} -+ -+/* -+ * Final wrapup - pad to 64-byte boundary with the bit pattern -+ * 1 0* (64-bit count of bits processed, MSB-first) -+ */ -+void mvMD5Final(unsigned char digest[MV_MD5_MAC_LEN], MV_MD5_CONTEXT *ctx) -+{ -+ unsigned count; -+ unsigned char *p; -+ -+ /* Compute number of bytes mod 64 */ -+ count = (ctx->bits[0] >> 3) & 0x3F; -+ -+ /* Set the first char of padding to 0x80. This is safe since there is -+ always at least one byte free */ -+ p = ctx->in + count; -+ *p++ = 0x80; -+ -+ /* Bytes of padding needed to make 64 bytes */ -+ count = 64 - 1 - count; -+ -+ /* Pad out to 56 mod 64 */ -+ if (count < 8) -+ { -+ /* Two lots of padding: Pad the first block to 64 bytes */ -+ memset(p, 0, count); -+ mvByteReverse(ctx->in, MV_MD5_MAC_LEN); -+ mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in); -+ -+ /* Now fill the next block with 56 bytes */ -+ memset(ctx->in, 0, 56); -+ } -+ else -+ { -+ /* Pad block to 56 bytes */ -+ memset(p, 0, count - 8); -+ } -+ mvByteReverse(ctx->in, 14); -+ -+ /* Append length in bits and transform */ -+ ((MV_U32 *) ctx->in)[14] = ctx->bits[0]; -+ ((MV_U32 *) ctx->in)[15] = ctx->bits[1]; -+ -+ mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in); -+ mvByteReverse((unsigned char *) ctx->buf, 4); -+ memcpy(digest, ctx->buf, MV_MD5_MAC_LEN); -+ memset(ctx, 0, sizeof(ctx)); /* In case it's sensitive */ -+} -+ -+/* The four core functions - F1 is optimized somewhat */ -+ -+/* #define F1(x, y, z) (x & y | ~x & z) */ -+#define F1(x, y, z) (z ^ (x & (y ^ z))) -+#define F2(x, y, z) F1(z, x, y) -+#define F3(x, y, z) (x ^ y ^ z) -+#define F4(x, y, z) (y ^ (x | ~z)) -+ -+/* This is the central step in the MD5 algorithm. */ -+#define MD5STEP(f, w, x, y, z, data, s) \ -+ ( w += f(x, y, z) + data, w = w<>(32-s), w += x ) -+ -+/* -+ * The core of the MD5 algorithm, this alters an existing MD5 hash to -+ * reflect the addition of 16 longwords of new data. MD5Update blocks -+ * the data and converts bytes into longwords for this routine. -+ */ -+static void mvMD5Transform(MV_U32 buf[4], MV_U32 const in[MV_MD5_MAC_LEN]) -+{ -+ register MV_U32 a, b, c, d; -+ -+ a = buf[0]; -+ b = buf[1]; -+ c = buf[2]; -+ d = buf[3]; -+ -+ MD5STEP(F1, a, b, c, d, in[0] + 0xd76aa478, 7); -+ MD5STEP(F1, d, a, b, c, in[1] + 0xe8c7b756, 12); -+ MD5STEP(F1, c, d, a, b, in[2] + 0x242070db, 17); -+ MD5STEP(F1, b, c, d, a, in[3] + 0xc1bdceee, 22); -+ MD5STEP(F1, a, b, c, d, in[4] + 0xf57c0faf, 7); -+ MD5STEP(F1, d, a, b, c, in[5] + 0x4787c62a, 12); -+ MD5STEP(F1, c, d, a, b, in[6] + 0xa8304613, 17); -+ MD5STEP(F1, b, c, d, a, in[7] + 0xfd469501, 22); -+ MD5STEP(F1, a, b, c, d, in[8] + 0x698098d8, 7); -+ MD5STEP(F1, d, a, b, c, in[9] + 0x8b44f7af, 12); -+ MD5STEP(F1, c, d, a, b, in[10] + 0xffff5bb1, 17); -+ MD5STEP(F1, b, c, d, a, in[11] + 0x895cd7be, 22); -+ MD5STEP(F1, a, b, c, d, in[12] + 0x6b901122, 7); -+ MD5STEP(F1, d, a, b, c, in[13] + 0xfd987193, 12); -+ MD5STEP(F1, c, d, a, b, in[14] + 0xa679438e, 17); -+ MD5STEP(F1, b, c, d, a, in[15] + 0x49b40821, 22); -+ -+ MD5STEP(F2, a, b, c, d, in[1] + 0xf61e2562, 5); -+ MD5STEP(F2, d, a, b, c, in[6] + 0xc040b340, 9); -+ MD5STEP(F2, c, d, a, b, in[11] + 0x265e5a51, 14); -+ MD5STEP(F2, b, c, d, a, in[0] + 0xe9b6c7aa, 20); -+ MD5STEP(F2, a, b, c, d, in[5] + 0xd62f105d, 5); -+ MD5STEP(F2, d, a, b, c, in[10] + 0x02441453, 9); -+ MD5STEP(F2, c, d, a, b, in[15] + 0xd8a1e681, 14); -+ MD5STEP(F2, b, c, d, a, in[4] + 0xe7d3fbc8, 20); -+ MD5STEP(F2, a, b, c, d, in[9] + 0x21e1cde6, 5); -+ MD5STEP(F2, d, a, b, c, in[14] + 0xc33707d6, 9); -+ MD5STEP(F2, c, d, a, b, in[3] + 0xf4d50d87, 14); -+ MD5STEP(F2, b, c, d, a, in[8] + 0x455a14ed, 20); -+ MD5STEP(F2, a, b, c, d, in[13] + 0xa9e3e905, 5); -+ MD5STEP(F2, d, a, b, c, in[2] + 0xfcefa3f8, 9); -+ MD5STEP(F2, c, d, a, b, in[7] + 0x676f02d9, 14); -+ MD5STEP(F2, b, c, d, a, in[12] + 0x8d2a4c8a, 20); -+ -+ MD5STEP(F3, a, b, c, d, in[5] + 0xfffa3942, 4); -+ MD5STEP(F3, d, a, b, c, in[8] + 0x8771f681, 11); -+ MD5STEP(F3, c, d, a, b, in[11] + 0x6d9d6122, 16); -+ MD5STEP(F3, b, c, d, a, in[14] + 0xfde5380c, 23); -+ MD5STEP(F3, a, b, c, d, in[1] + 0xa4beea44, 4); -+ MD5STEP(F3, d, a, b, c, in[4] + 0x4bdecfa9, 11); -+ MD5STEP(F3, c, d, a, b, in[7] + 0xf6bb4b60, 16); -+ MD5STEP(F3, b, c, d, a, in[10] + 0xbebfbc70, 23); -+ MD5STEP(F3, a, b, c, d, in[13] + 0x289b7ec6, 4); -+ MD5STEP(F3, d, a, b, c, in[0] + 0xeaa127fa, 11); -+ MD5STEP(F3, c, d, a, b, in[3] + 0xd4ef3085, 16); -+ MD5STEP(F3, b, c, d, a, in[6] + 0x04881d05, 23); -+ MD5STEP(F3, a, b, c, d, in[9] + 0xd9d4d039, 4); -+ MD5STEP(F3, d, a, b, c, in[12] + 0xe6db99e5, 11); -+ MD5STEP(F3, c, d, a, b, in[15] + 0x1fa27cf8, 16); -+ MD5STEP(F3, b, c, d, a, in[2] + 0xc4ac5665, 23); -+ -+ MD5STEP(F4, a, b, c, d, in[0] + 0xf4292244, 6); -+ MD5STEP(F4, d, a, b, c, in[7] + 0x432aff97, 10); -+ MD5STEP(F4, c, d, a, b, in[14] + 0xab9423a7, 15); -+ MD5STEP(F4, b, c, d, a, in[5] + 0xfc93a039, 21); -+ MD5STEP(F4, a, b, c, d, in[12] + 0x655b59c3, 6); -+ MD5STEP(F4, d, a, b, c, in[3] + 0x8f0ccc92, 10); -+ MD5STEP(F4, c, d, a, b, in[10] + 0xffeff47d, 15); -+ MD5STEP(F4, b, c, d, a, in[1] + 0x85845dd1, 21); -+ MD5STEP(F4, a, b, c, d, in[8] + 0x6fa87e4f, 6); -+ MD5STEP(F4, d, a, b, c, in[15] + 0xfe2ce6e0, 10); -+ MD5STEP(F4, c, d, a, b, in[6] + 0xa3014314, 15); -+ MD5STEP(F4, b, c, d, a, in[13] + 0x4e0811a1, 21); -+ MD5STEP(F4, a, b, c, d, in[4] + 0xf7537e82, 6); -+ MD5STEP(F4, d, a, b, c, in[11] + 0xbd3af235, 10); -+ MD5STEP(F4, c, d, a, b, in[2] + 0x2ad7d2bb, 15); -+ MD5STEP(F4, b, c, d, a, in[9] + 0xeb86d391, 21); -+ -+ buf[0] += a; -+ buf[1] += b; -+ buf[2] += c; -+ buf[3] += d; -+} -+ -+void mvMD5(unsigned char const *buf, unsigned len, unsigned char* digest) -+{ -+ MV_MD5_CONTEXT ctx; -+ -+ mvMD5Init(&ctx); -+ mvMD5Update(&ctx, buf, len); -+ mvMD5Final(digest, &ctx); -+} -+ -+ -+void mvHmacMd5(unsigned char const* text, int text_len, -+ unsigned char const* key, int key_len, -+ unsigned char* digest) -+{ -+ int i; -+ MV_MD5_CONTEXT ctx; -+ unsigned char k_ipad[64+1]; /* inner padding - key XORd with ipad */ -+ unsigned char k_opad[64+1]; /* outer padding - key XORd with opad */ -+ -+ /* start out by storing key in pads */ -+ memset(k_ipad, 0, 64); -+ memcpy(k_ipad, key, key_len); -+ memset(k_opad, 0, 64); -+ memcpy(k_opad, key, key_len); -+ -+ /* XOR key with ipad and opad values */ -+ for (i=0; i<64; i++) -+ { -+ k_ipad[i] ^= 0x36; -+ k_opad[i] ^= 0x5c; -+ } -+ -+ /* perform inner MD5 */ -+ mvMD5Init(&ctx); /* init ctx for 1st pass */ -+ mvMD5Update(&ctx, k_ipad, 64); /* start with inner pad */ -+ mvMD5Update(&ctx, text, text_len); /* then text of datagram */ -+ mvMD5Final(digest, &ctx); /* finish up 1st pass */ -+ -+ /* perform outer MD5 */ -+ mvMD5Init(&ctx); /* init ctx for 2nd pass */ -+ mvMD5Update(&ctx, k_opad, 64); /* start with outer pad */ -+ mvMD5Update(&ctx, digest, 16); /* then results of 1st hash */ -+ mvMD5Final(digest, &ctx); /* finish up 2nd pass */ -+} -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/cesa/mvMD5.h linux-2.6.36/crypto/ocf/kirkwood/cesa/mvMD5.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/cesa/mvMD5.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/cesa/mvMD5.h 2010-11-09 20:28:05.942495390 +0100 -@@ -0,0 +1,93 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __mvMD5_h__ -+#define __mvMD5_h__ -+ -+#include "mvMD5.h" -+ -+#define MV_MD5_MAC_LEN 16 -+ -+ -+typedef struct -+{ -+ MV_U32 buf[4]; -+ MV_U32 bits[2]; -+ MV_U8 in[64]; -+ -+} MV_MD5_CONTEXT; -+ -+void mvMD5Init(MV_MD5_CONTEXT *context); -+void mvMD5Update(MV_MD5_CONTEXT *context, unsigned char const *buf, -+ unsigned len); -+void mvMD5Final(unsigned char digest[16], MV_MD5_CONTEXT *context); -+ -+void mvMD5(unsigned char const *buf, unsigned len, unsigned char* digest); -+ -+void mvHmacMd5(unsigned char const* text, int text_len, -+ unsigned char const* key, int key_len, -+ unsigned char* digest); -+ -+ -+#endif /* __mvMD5_h__ */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/cesa/mvSHA1.c linux-2.6.36/crypto/ocf/kirkwood/cesa/mvSHA1.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/cesa/mvSHA1.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/cesa/mvSHA1.c 2010-11-09 20:28:05.972495400 +0100 -@@ -0,0 +1,239 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "mvOs.h" -+#include "mvSHA1.h" -+ -+#define SHA1HANDSOFF -+ -+typedef union -+{ -+ MV_U8 c[64]; -+ MV_U32 l[16]; -+ -+} CHAR64LONG16; -+ -+static void mvSHA1Transform(MV_U32 state[5], const MV_U8 *buffer); -+ -+#define rol(value, bits) (((value) << (bits)) | ((value) >> (32 - (bits)))) -+ -+ -+#ifdef MV_CPU_LE -+#define blk0(i) (block->l[i] = (rol(block->l[i], 24) & 0xFF00FF00) | \ -+ (rol(block->l[i], 8) & 0x00FF00FF)) -+#else -+#define blk0(i) block->l[i] -+#endif -+#define blk(i) (block->l[i & 15] = rol(block->l[(i + 13) & 15] ^ \ -+ block->l[(i + 8) & 15] ^ block->l[(i + 2) & 15] ^ block->l[i & 15], 1)) -+ -+/* (R0+R1), R2, R3, R4 are the different operations used in SHA1 */ -+#define R0(v,w,x,y,z,i) \ -+ z += ((w & (x ^ y)) ^ y) + blk0(i) + 0x5A827999 + rol(v, 5); \ -+ w = rol(w, 30); -+#define R1(v,w,x,y,z,i) \ -+ z += ((w & (x ^ y)) ^ y) + blk(i) + 0x5A827999 + rol(v, 5); \ -+ w = rol(w, 30); -+#define R2(v,w,x,y,z,i) \ -+ z += (w ^ x ^ y) + blk(i) + 0x6ED9EBA1 + rol(v, 5); w = rol(w, 30); -+#define R3(v,w,x,y,z,i) \ -+ z += (((w | x) & y) | (w & x)) + blk(i) + 0x8F1BBCDC + rol(v, 5); \ -+ w = rol(w, 30); -+#define R4(v,w,x,y,z,i) \ -+ z += (w ^ x ^ y) + blk(i) + 0xCA62C1D6 + rol(v, 5); \ -+ w=rol(w, 30); -+ -+/* Hash a single 512-bit block. This is the core of the algorithm. */ -+static void mvSHA1Transform(MV_U32 state[5], const MV_U8 *buffer) -+{ -+ MV_U32 a, b, c, d, e; -+ CHAR64LONG16* block; -+ -+#ifdef SHA1HANDSOFF -+ static MV_U32 workspace[16]; -+ -+ block = (CHAR64LONG16 *) workspace; -+ memcpy(block, buffer, 64); -+#else -+ block = (CHAR64LONG16 *) buffer; -+#endif -+ /* Copy context->state[] to working vars */ -+ a = state[0]; -+ b = state[1]; -+ c = state[2]; -+ d = state[3]; -+ e = state[4]; -+ /* 4 rounds of 20 operations each. Loop unrolled. */ -+ R0(a,b,c,d,e, 0); R0(e,a,b,c,d, 1); R0(d,e,a,b,c, 2); R0(c,d,e,a,b, 3); -+ R0(b,c,d,e,a, 4); R0(a,b,c,d,e, 5); R0(e,a,b,c,d, 6); R0(d,e,a,b,c, 7); -+ R0(c,d,e,a,b, 8); R0(b,c,d,e,a, 9); R0(a,b,c,d,e,10); R0(e,a,b,c,d,11); -+ R0(d,e,a,b,c,12); R0(c,d,e,a,b,13); R0(b,c,d,e,a,14); R0(a,b,c,d,e,15); -+ R1(e,a,b,c,d,16); R1(d,e,a,b,c,17); R1(c,d,e,a,b,18); R1(b,c,d,e,a,19); -+ R2(a,b,c,d,e,20); R2(e,a,b,c,d,21); R2(d,e,a,b,c,22); R2(c,d,e,a,b,23); -+ R2(b,c,d,e,a,24); R2(a,b,c,d,e,25); R2(e,a,b,c,d,26); R2(d,e,a,b,c,27); -+ R2(c,d,e,a,b,28); R2(b,c,d,e,a,29); R2(a,b,c,d,e,30); R2(e,a,b,c,d,31); -+ R2(d,e,a,b,c,32); R2(c,d,e,a,b,33); R2(b,c,d,e,a,34); R2(a,b,c,d,e,35); -+ R2(e,a,b,c,d,36); R2(d,e,a,b,c,37); R2(c,d,e,a,b,38); R2(b,c,d,e,a,39); -+ R3(a,b,c,d,e,40); R3(e,a,b,c,d,41); R3(d,e,a,b,c,42); R3(c,d,e,a,b,43); -+ R3(b,c,d,e,a,44); R3(a,b,c,d,e,45); R3(e,a,b,c,d,46); R3(d,e,a,b,c,47); -+ R3(c,d,e,a,b,48); R3(b,c,d,e,a,49); R3(a,b,c,d,e,50); R3(e,a,b,c,d,51); -+ R3(d,e,a,b,c,52); R3(c,d,e,a,b,53); R3(b,c,d,e,a,54); R3(a,b,c,d,e,55); -+ R3(e,a,b,c,d,56); R3(d,e,a,b,c,57); R3(c,d,e,a,b,58); R3(b,c,d,e,a,59); -+ R4(a,b,c,d,e,60); R4(e,a,b,c,d,61); R4(d,e,a,b,c,62); R4(c,d,e,a,b,63); -+ R4(b,c,d,e,a,64); R4(a,b,c,d,e,65); R4(e,a,b,c,d,66); R4(d,e,a,b,c,67); -+ R4(c,d,e,a,b,68); R4(b,c,d,e,a,69); R4(a,b,c,d,e,70); R4(e,a,b,c,d,71); -+ R4(d,e,a,b,c,72); R4(c,d,e,a,b,73); R4(b,c,d,e,a,74); R4(a,b,c,d,e,75); -+ R4(e,a,b,c,d,76); R4(d,e,a,b,c,77); R4(c,d,e,a,b,78); R4(b,c,d,e,a,79); -+ /* Add the working vars back into context.state[] */ -+ state[0] += a; -+ state[1] += b; -+ state[2] += c; -+ state[3] += d; -+ state[4] += e; -+ /* Wipe variables */ -+ a = b = c = d = e = 0; -+} -+ -+void mvSHA1Init(MV_SHA1_CTX* context) -+{ -+ /* SHA1 initialization constants */ -+ context->state[0] = 0x67452301; -+ context->state[1] = 0xEFCDAB89; -+ context->state[2] = 0x98BADCFE; -+ context->state[3] = 0x10325476; -+ context->state[4] = 0xC3D2E1F0; -+ context->count[0] = context->count[1] = 0; -+} -+ -+ -+/* Run your data through this. */ -+void mvSHA1Update(MV_SHA1_CTX *context, MV_U8 const *data, -+ unsigned int len) -+{ -+ MV_U32 i, j; -+ -+ j = (context->count[0] >> 3) & 63; -+ if ((context->count[0] += len << 3) < (len << 3)) -+ context->count[1]++; -+ context->count[1] += (len >> 29); -+ if ((j + len) > 63) -+ { -+ memcpy(&context->buffer[j], data, (i = 64-j)); -+ mvSHA1Transform(context->state, context->buffer); -+ for ( ; i + 63 < len; i += 64) -+ { -+ mvSHA1Transform(context->state, &data[i]); -+ } -+ j = 0; -+ } -+ else -+ { -+ i = 0; -+ } -+ memcpy(&context->buffer[j], &data[i], len - i); -+} -+ -+void mvSHA1Final(MV_U8* digest, MV_SHA1_CTX* context) -+{ -+ MV_U32 i; -+ MV_U8 finalcount[8]; -+ -+ for (i = 0; i < 8; i++) -+ { -+ finalcount[i] = (unsigned char)((context->count[(i >= 4 ? 0 : 1)] >> -+ ((3-(i & 3)) * 8) ) & 255); /* Endian independent */ -+ } -+ mvSHA1Update(context, (const unsigned char *) "\200", 1); -+ while ((context->count[0] & 504) != 448) -+ { -+ mvSHA1Update(context, (const unsigned char *) "\0", 1); -+ } -+ mvSHA1Update(context, finalcount, 8); /* Should cause a mvSHA1Transform() -+ */ -+ for (i = 0; i < 20; i++) -+ { -+ digest[i] = (unsigned char) -+ ((context->state[i >> 2] >> ((3 - (i & 3)) * 8)) & 255); -+ } -+ /* Wipe variables */ -+ i = 0; -+ memset(context->buffer, 0, 64); -+ memset(context->state, 0, 20); -+ memset(context->count, 0, 8); -+ memset(finalcount, 0, 8); -+ -+#ifdef SHA1HANDSOFF /* make SHA1Transform overwrite it's own static vars */ -+ mvSHA1Transform(context->state, context->buffer); -+#endif -+} -+ -+ -+void mvSHA1(MV_U8 const *buf, unsigned int len, MV_U8* digest) -+{ -+ MV_SHA1_CTX ctx; -+ -+ mvSHA1Init(&ctx); -+ mvSHA1Update(&ctx, buf, len); -+ mvSHA1Final(digest, &ctx); -+} -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/cesa/mvSHA1.h linux-2.6.36/crypto/ocf/kirkwood/cesa/mvSHA1.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/cesa/mvSHA1.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/cesa/mvSHA1.h 2010-11-09 20:28:06.012495345 +0100 -@@ -0,0 +1,88 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __mvSHA1_h__ -+#define __mvSHA1_h__ -+ -+#include "mvSHA1.h" -+ -+#define MV_SHA1_MAC_LEN 20 -+ -+ -+typedef struct -+{ -+ MV_U32 state[5]; -+ MV_U32 count[2]; -+ MV_U8 buffer[64]; -+ -+} MV_SHA1_CTX; -+ -+void mvSHA1Init(MV_SHA1_CTX *context); -+void mvSHA1Update(MV_SHA1_CTX *context, MV_U8 const *buf, unsigned int len); -+void mvSHA1Final(MV_U8* digest, MV_SHA1_CTX *context); -+ -+void mvSHA1(MV_U8 const *buf, unsigned int len, MV_U8* digest); -+ -+ -+#endif /* __mvSHA1_h__ */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/cesa_ocf_drv.c linux-2.6.36/crypto/ocf/kirkwood/cesa_ocf_drv.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/cesa_ocf_drv.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/cesa_ocf_drv.c 2010-11-09 20:28:06.052495403 +0100 -@@ -0,0 +1,1296 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+*******************************************************************************/ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "ctrlEnv/sys/mvSysCesa.h" -+#include "cesa/mvCesa.h" /* moved here before cryptodev.h due to include dependencies */ -+#include -+#include -+#include -+#include -+#include "mvDebug.h" -+ -+#include "cesa/mvMD5.h" -+#include "cesa/mvSHA1.h" -+ -+#include "cesa/mvCesaRegs.h" -+#include "cesa/AES/mvAes.h" -+#include "cesa/mvLru.h" -+ -+#undef RT_DEBUG -+#ifdef RT_DEBUG -+static int debug = 1; -+module_param(debug, int, 1); -+MODULE_PARM_DESC(debug, "Enable debug"); -+#undef dprintk -+#define dprintk(a...) if (debug) { printk(a); } else -+#else -+static int debug = 0; -+#undef dprintk -+#define dprintk(a...) -+#endif -+ -+ -+/* TDMA Regs */ -+#define WINDOW_BASE(i) 0xA00 + (i << 3) -+#define WINDOW_CTRL(i) 0xA04 + (i << 3) -+ -+/* interrupt handling */ -+#undef CESA_OCF_POLLING -+#undef CESA_OCF_TASKLET -+ -+#if defined(CESA_OCF_POLLING) && defined(CESA_OCF_TASKLET) -+#error "don't use both tasklet and polling mode" -+#endif -+ -+extern int cesaReqResources; -+/* support for spliting action into 2 actions */ -+#define CESA_OCF_SPLIT -+ -+/* general defines */ -+#define CESA_OCF_MAX_SES 128 -+#define CESA_Q_SIZE 64 -+ -+ -+/* data structures */ -+struct cesa_ocf_data { -+ int cipher_alg; -+ int auth_alg; -+ int encrypt_tn_auth; -+#define auth_tn_decrypt encrypt_tn_auth -+ int ivlen; -+ int digestlen; -+ short sid_encrypt; -+ short sid_decrypt; -+ /* fragment workaround sessions */ -+ short frag_wa_encrypt; -+ short frag_wa_decrypt; -+ short frag_wa_auth; -+}; -+ -+/* CESA device data */ -+struct cesa_dev { -+ void __iomem *sram; -+ void __iomem *reg; -+ struct mv_cesa_platform_data *plat_data; -+ int irq; -+}; -+ -+#define DIGEST_BUF_SIZE 32 -+struct cesa_ocf_process { -+ MV_CESA_COMMAND cesa_cmd; -+ MV_CESA_MBUF cesa_mbuf; -+ MV_BUF_INFO cesa_bufs[MV_CESA_MAX_MBUF_FRAGS]; -+ char digest[DIGEST_BUF_SIZE]; -+ int digest_len; -+ struct cryptop *crp; -+ int need_cb; -+}; -+ -+/* global variables */ -+static int32_t cesa_ocf_id = -1; -+static struct cesa_ocf_data *cesa_ocf_sessions[CESA_OCF_MAX_SES]; -+static spinlock_t cesa_lock; -+static struct cesa_dev cesa_device; -+ -+/* static APIs */ -+static int cesa_ocf_process (device_t, struct cryptop *, int); -+static int cesa_ocf_newsession (device_t, u_int32_t *, struct cryptoini *); -+static int cesa_ocf_freesession (device_t, u_int64_t); -+static void cesa_callback (unsigned long); -+static irqreturn_t cesa_interrupt_handler (int, void *); -+#ifdef CESA_OCF_POLLING -+static void cesa_interrupt_polling(void); -+#endif -+#ifdef CESA_OCF_TASKLET -+static struct tasklet_struct cesa_ocf_tasklet; -+#endif -+ -+static struct timeval tt_start; -+static struct timeval tt_end; -+ -+/* -+ * dummy device structure -+ */ -+ -+static struct { -+ softc_device_decl sc_dev; -+} mv_cesa_dev; -+ -+static device_method_t mv_cesa_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, cesa_ocf_newsession), -+ DEVMETHOD(cryptodev_freesession,cesa_ocf_freesession), -+ DEVMETHOD(cryptodev_process, cesa_ocf_process), -+ DEVMETHOD(cryptodev_kprocess, NULL), -+}; -+ -+ -+ -+/* Add debug Trace */ -+#undef CESA_OCF_TRACE_DEBUG -+#ifdef CESA_OCF_TRACE_DEBUG -+ -+#define MV_CESA_USE_TIMER_ID 0 -+ -+typedef struct -+{ -+ int type; /* 0 - isrEmpty, 1 - cesaReadyGet, 2 - cesaAction */ -+ MV_U32 timeStamp; -+ MV_U32 cause; -+ MV_U32 realCause; -+ MV_U32 dmaCause; -+ int resources; -+ MV_CESA_REQ* pReqReady; -+ MV_CESA_REQ* pReqEmpty; -+ MV_CESA_REQ* pReqProcess; -+} MV_CESA_TEST_TRACE; -+ -+#define MV_CESA_TEST_TRACE_SIZE 50 -+ -+static int cesaTestTraceIdx = 0; -+static MV_CESA_TEST_TRACE cesaTestTrace[MV_CESA_TEST_TRACE_SIZE]; -+ -+static void cesaTestTraceAdd(int type) -+{ -+ cesaTestTrace[cesaTestTraceIdx].type = type; -+ cesaTestTrace[cesaTestTraceIdx].realCause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); -+ //cesaTestTrace[cesaTestTraceIdx].idmaCause = MV_REG_READ(IDMA_CAUSE_REG); -+ cesaTestTrace[cesaTestTraceIdx].resources = cesaReqResources; -+ cesaTestTrace[cesaTestTraceIdx].pReqReady = pCesaReqReady; -+ cesaTestTrace[cesaTestTraceIdx].pReqEmpty = pCesaReqEmpty; -+ cesaTestTrace[cesaTestTraceIdx].pReqProcess = pCesaReqProcess; -+ cesaTestTrace[cesaTestTraceIdx].timeStamp = mvCntmrRead(MV_CESA_USE_TIMER_ID); -+ cesaTestTraceIdx++; -+ if(cesaTestTraceIdx == MV_CESA_TEST_TRACE_SIZE) -+ cesaTestTraceIdx = 0; -+} -+ -+#else /* CESA_OCF_TRACE_DEBUG */ -+ -+#define cesaTestTraceAdd(x) -+ -+#endif /* CESA_OCF_TRACE_DEBUG */ -+ -+unsigned int -+get_usec(unsigned int start) -+{ -+ if(start) { -+ do_gettimeofday (&tt_start); -+ return 0; -+ } -+ else { -+ do_gettimeofday (&tt_end); -+ tt_end.tv_sec -= tt_start.tv_sec; -+ tt_end.tv_usec -= tt_start.tv_usec; -+ if (tt_end.tv_usec < 0) { -+ tt_end.tv_usec += 1000 * 1000; -+ tt_end.tv_sec -= 1; -+ } -+ } -+ printk("time taken is %d\n", (unsigned int)(tt_end.tv_usec + tt_end.tv_sec * 1000000)); -+ return (tt_end.tv_usec + tt_end.tv_sec * 1000000); -+} -+ -+#ifdef RT_DEBUG -+/* -+ * check that the crp action match the current session -+ */ -+static int -+ocf_check_action(struct cryptop *crp, struct cesa_ocf_data *cesa_ocf_cur_ses) { -+ int count = 0; -+ int encrypt = 0, decrypt = 0, auth = 0; -+ struct cryptodesc *crd; -+ -+ /* Go through crypto descriptors, processing as we go */ -+ for (crd = crp->crp_desc; crd; crd = crd->crd_next, count++) { -+ if(count > 2) { -+ printk("%s,%d: session mode is not supported.\n", __FILE__, __LINE__); -+ return 1; -+ } -+ -+ /* Encryption /Decryption */ -+ if(crd->crd_alg == cesa_ocf_cur_ses->cipher_alg) { -+ /* check that the action is compatible with session */ -+ if(encrypt || decrypt) { -+ printk("%s,%d: session mode is not supported.\n", __FILE__, __LINE__); -+ return 1; -+ } -+ -+ if(crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ -+ if( (count == 2) && (cesa_ocf_cur_ses->encrypt_tn_auth) ) { -+ printk("%s,%d: sequence isn't supported by this session.\n", __FILE__, __LINE__); -+ return 1; -+ } -+ encrypt++; -+ } -+ else { /* decrypt */ -+ if( (count == 2) && !(cesa_ocf_cur_ses->auth_tn_decrypt) ) { -+ printk("%s,%d: sequence isn't supported by this session.\n", __FILE__, __LINE__); -+ return 1; -+ } -+ decrypt++; -+ } -+ -+ } -+ /* Authentication */ -+ else if(crd->crd_alg == cesa_ocf_cur_ses->auth_alg) { -+ /* check that the action is compatible with session */ -+ if(auth) { -+ printk("%s,%d: session mode is not supported.\n", __FILE__, __LINE__); -+ return 1; -+ } -+ if( (count == 2) && (decrypt) && (cesa_ocf_cur_ses->auth_tn_decrypt)) { -+ printk("%s,%d: sequence isn't supported by this session.\n", __FILE__, __LINE__); -+ return 1; -+ } -+ if( (count == 2) && (encrypt) && !(cesa_ocf_cur_ses->encrypt_tn_auth)) { -+ printk("%s,%d: sequence isn't supported by this session.\n", __FILE__, __LINE__); -+ return 1; -+ } -+ auth++; -+ } -+ else { -+ printk("%s,%d: Alg isn't supported by this session.\n", __FILE__, __LINE__); -+ return 1; -+ } -+ } -+ return 0; -+ -+} -+#endif -+ -+/* -+ * Process a request. -+ */ -+static int -+cesa_ocf_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ struct cesa_ocf_process *cesa_ocf_cmd = NULL; -+ struct cesa_ocf_process *cesa_ocf_cmd_wa = NULL; -+ MV_CESA_COMMAND *cesa_cmd; -+ struct cryptodesc *crd; -+ struct cesa_ocf_data *cesa_ocf_cur_ses; -+ int sid = 0, temp_len = 0, i; -+ int encrypt = 0, decrypt = 0, auth = 0; -+ int status; -+ struct sk_buff *skb = NULL; -+ struct uio *uiop = NULL; -+ unsigned char *ivp; -+ MV_BUF_INFO *p_buf_info; -+ MV_CESA_MBUF *p_mbuf_info; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if( cesaReqResources <= 1 ) { -+ dprintk("%s,%d: ERESTART\n", __FILE__, __LINE__); -+ return ERESTART; -+ } -+ -+#ifdef RT_DEBUG -+ /* Sanity check */ -+ if (crp == NULL) { -+ printk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ if (crp->crp_desc == NULL || crp->crp_buf == NULL ) { -+ printk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ return EINVAL; -+ } -+ -+ sid = crp->crp_sid & 0xffffffff; -+ if ((sid >= CESA_OCF_MAX_SES) || (cesa_ocf_sessions[sid] == NULL)) { -+ crp->crp_etype = ENOENT; -+ printk("%s,%d: ENOENT session %d \n", __FILE__, __LINE__, sid); -+ return EINVAL; -+ } -+#endif -+ -+ sid = crp->crp_sid & 0xffffffff; -+ crp->crp_etype = 0; -+ cesa_ocf_cur_ses = cesa_ocf_sessions[sid]; -+ -+#ifdef RT_DEBUG -+ if(ocf_check_action(crp, cesa_ocf_cur_ses)){ -+ goto p_error; -+ } -+#endif -+ -+ /* malloc a new cesa process */ -+ cesa_ocf_cmd = kmalloc(sizeof(struct cesa_ocf_process), GFP_ATOMIC); -+ -+ if (cesa_ocf_cmd == NULL) { -+ printk("%s,%d: ENOBUFS \n", __FILE__, __LINE__); -+ goto p_error; -+ } -+ memset(cesa_ocf_cmd, 0, sizeof(struct cesa_ocf_process)); -+ -+ /* init cesa_process */ -+ cesa_ocf_cmd->crp = crp; -+ /* always call callback */ -+ cesa_ocf_cmd->need_cb = 1; -+ -+ /* init cesa_cmd for usage of the HALs */ -+ cesa_cmd = &cesa_ocf_cmd->cesa_cmd; -+ cesa_cmd->pReqPrv = (void *)cesa_ocf_cmd; -+ cesa_cmd->sessionId = cesa_ocf_cur_ses->sid_encrypt; /* defualt use encrypt */ -+ -+ /* prepare src buffer */ -+ /* we send the entire buffer to the HAL, even if only part of it should be encrypt/auth. */ -+ /* if not using seesions for both encrypt and auth, then it will be wiser to to copy only */ -+ /* from skip to crd_len. */ -+ p_buf_info = cesa_ocf_cmd->cesa_bufs; -+ p_mbuf_info = &cesa_ocf_cmd->cesa_mbuf; -+ -+ p_buf_info += 2; /* save 2 first buffers for IV and digest - -+ we won't append them to the end since, they -+ might be places in an unaligned addresses. */ -+ -+ p_mbuf_info->pFrags = p_buf_info; -+ temp_len = 0; -+ -+ /* handle SKB */ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ -+ dprintk("%s,%d: handle SKB.\n", __FILE__, __LINE__); -+ skb = (struct sk_buff *) crp->crp_buf; -+ -+ if (skb_shinfo(skb)->nr_frags >= (MV_CESA_MAX_MBUF_FRAGS - 1)) { -+ printk("%s,%d: %d nr_frags > MV_CESA_MAX_MBUF_FRAGS", __FILE__, __LINE__, skb_shinfo(skb)->nr_frags); -+ goto p_error; -+ } -+ -+ p_mbuf_info->mbufSize = skb->len; -+ temp_len = skb->len; -+ /* first skb fragment */ -+ p_buf_info->bufSize = skb_headlen(skb); -+ p_buf_info->bufVirtPtr = skb->data; -+ p_buf_info++; -+ -+ /* now handle all other skb fragments */ -+ for ( i = 0; i < skb_shinfo(skb)->nr_frags; i++ ) { -+ skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; -+ p_buf_info->bufSize = frag->size; -+ p_buf_info->bufVirtPtr = page_address(frag->page) + frag->page_offset; -+ p_buf_info++; -+ } -+ p_mbuf_info->numFrags = skb_shinfo(skb)->nr_frags + 1; -+ } -+ /* handle UIO */ -+ else if(crp->crp_flags & CRYPTO_F_IOV) { -+ -+ dprintk("%s,%d: handle UIO.\n", __FILE__, __LINE__); -+ uiop = (struct uio *) crp->crp_buf; -+ -+ if (uiop->uio_iovcnt > (MV_CESA_MAX_MBUF_FRAGS - 1)) { -+ printk("%s,%d: %d uio_iovcnt > MV_CESA_MAX_MBUF_FRAGS \n", __FILE__, __LINE__, uiop->uio_iovcnt); -+ goto p_error; -+ } -+ -+ p_mbuf_info->mbufSize = crp->crp_ilen; -+ p_mbuf_info->numFrags = uiop->uio_iovcnt; -+ for(i = 0; i < uiop->uio_iovcnt; i++) { -+ p_buf_info->bufVirtPtr = uiop->uio_iov[i].iov_base; -+ p_buf_info->bufSize = uiop->uio_iov[i].iov_len; -+ temp_len += p_buf_info->bufSize; -+ dprintk("%s,%d: buf %x-> addr %x, size %x \n" -+ , __FILE__, __LINE__, i, (unsigned int)p_buf_info->bufVirtPtr, p_buf_info->bufSize); -+ p_buf_info++; -+ } -+ -+ } -+ /* handle CONTIG */ -+ else { -+ dprintk("%s,%d: handle CONTIG.\n", __FILE__, __LINE__); -+ p_mbuf_info->numFrags = 1; -+ p_mbuf_info->mbufSize = crp->crp_ilen; -+ p_buf_info->bufVirtPtr = crp->crp_buf; -+ p_buf_info->bufSize = crp->crp_ilen; -+ temp_len = crp->crp_ilen; -+ p_buf_info++; -+ } -+ -+ /* Support up to 64K why? cause! */ -+ if(crp->crp_ilen > 64*1024) { -+ printk("%s,%d: buf too big %x \n", __FILE__, __LINE__, crp->crp_ilen); -+ goto p_error; -+ } -+ -+ if( temp_len != crp->crp_ilen ) { -+ printk("%s,%d: warning size don't match.(%x %x) \n", __FILE__, __LINE__, temp_len, crp->crp_ilen); -+ } -+ -+ cesa_cmd->pSrc = p_mbuf_info; -+ cesa_cmd->pDst = p_mbuf_info; -+ -+ /* restore p_buf_info to point to first available buf */ -+ p_buf_info = cesa_ocf_cmd->cesa_bufs; -+ p_buf_info += 1; -+ -+ -+ /* Go through crypto descriptors, processing as we go */ -+ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { -+ -+ /* Encryption /Decryption */ -+ if(crd->crd_alg == cesa_ocf_cur_ses->cipher_alg) { -+ -+ dprintk("%s,%d: cipher", __FILE__, __LINE__); -+ -+ cesa_cmd->cryptoOffset = crd->crd_skip; -+ cesa_cmd->cryptoLength = crd->crd_len; -+ -+ if(crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ -+ dprintk(" encrypt \n"); -+ encrypt++; -+ -+ /* handle IV */ -+ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { /* IV from USER */ -+ dprintk("%s,%d: IV from USER (offset %x) \n", __FILE__, __LINE__, crd->crd_inject); -+ cesa_cmd->ivFromUser = 1; -+ ivp = crd->crd_iv; -+ -+ /* -+ * do we have to copy the IV back to the buffer ? -+ */ -+ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { -+ dprintk("%s,%d: copy the IV back to the buffer\n", __FILE__, __LINE__); -+ cesa_cmd->ivOffset = crd->crd_inject; -+ crypto_copy_bits_back(crp->crp_buf, crd->crd_inject, ivp, cesa_ocf_cur_ses->ivlen); -+ } -+ else { -+ dprintk("%s,%d: don't copy the IV back to the buffer \n", __FILE__, __LINE__); -+ p_mbuf_info->numFrags++; -+ p_mbuf_info->mbufSize += cesa_ocf_cur_ses->ivlen; -+ p_mbuf_info->pFrags = p_buf_info; -+ -+ p_buf_info->bufVirtPtr = ivp; -+ p_buf_info->bufSize = cesa_ocf_cur_ses->ivlen; -+ p_buf_info--; -+ -+ /* offsets */ -+ cesa_cmd->ivOffset = 0; -+ cesa_cmd->cryptoOffset += cesa_ocf_cur_ses->ivlen; -+ if(auth) { -+ cesa_cmd->macOffset += cesa_ocf_cur_ses->ivlen; -+ cesa_cmd->digestOffset += cesa_ocf_cur_ses->ivlen; -+ } -+ } -+ } -+ else { /* random IV */ -+ dprintk("%s,%d: random IV \n", __FILE__, __LINE__); -+ cesa_cmd->ivFromUser = 0; -+ -+ /* -+ * do we have to copy the IV back to the buffer ? -+ */ -+ /* in this mode the HAL will always copy the IV */ -+ /* given by the session to the ivOffset */ -+ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { -+ cesa_cmd->ivOffset = crd->crd_inject; -+ } -+ else { -+ /* if IV isn't copy, then how will the user know which IV did we use??? */ -+ printk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ goto p_error; -+ } -+ } -+ } -+ else { /* decrypt */ -+ dprintk(" decrypt \n"); -+ decrypt++; -+ cesa_cmd->sessionId = cesa_ocf_cur_ses->sid_decrypt; -+ -+ /* handle IV */ -+ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { -+ dprintk("%s,%d: IV from USER \n", __FILE__, __LINE__); -+ /* append the IV buf to the mbuf */ -+ cesa_cmd->ivFromUser = 1; -+ p_mbuf_info->numFrags++; -+ p_mbuf_info->mbufSize += cesa_ocf_cur_ses->ivlen; -+ p_mbuf_info->pFrags = p_buf_info; -+ -+ p_buf_info->bufVirtPtr = crd->crd_iv; -+ p_buf_info->bufSize = cesa_ocf_cur_ses->ivlen; -+ p_buf_info--; -+ -+ /* offsets */ -+ cesa_cmd->ivOffset = 0; -+ cesa_cmd->cryptoOffset += cesa_ocf_cur_ses->ivlen; -+ if(auth) { -+ cesa_cmd->macOffset += cesa_ocf_cur_ses->ivlen; -+ cesa_cmd->digestOffset += cesa_ocf_cur_ses->ivlen; -+ } -+ } -+ else { -+ dprintk("%s,%d: IV inside the buffer \n", __FILE__, __LINE__); -+ cesa_cmd->ivFromUser = 0; -+ cesa_cmd->ivOffset = crd->crd_inject; -+ } -+ } -+ -+ } -+ /* Authentication */ -+ else if(crd->crd_alg == cesa_ocf_cur_ses->auth_alg) { -+ dprintk("%s,%d: Authentication \n", __FILE__, __LINE__); -+ auth++; -+ cesa_cmd->macOffset = crd->crd_skip; -+ cesa_cmd->macLength = crd->crd_len; -+ -+ /* digest + mac */ -+ cesa_cmd->digestOffset = crd->crd_inject; -+ } -+ else { -+ printk("%s,%d: Alg isn't supported by this session.\n", __FILE__, __LINE__); -+ goto p_error; -+ } -+ } -+ -+ dprintk("\n"); -+ dprintk("%s,%d: Sending Action: \n", __FILE__, __LINE__); -+ dprintk("%s,%d: IV from user: %d. IV offset %x \n", __FILE__, __LINE__, cesa_cmd->ivFromUser, cesa_cmd->ivOffset); -+ dprintk("%s,%d: crypt offset %x len %x \n", __FILE__, __LINE__, cesa_cmd->cryptoOffset, cesa_cmd->cryptoLength); -+ dprintk("%s,%d: Auth offset %x len %x \n", __FILE__, __LINE__, cesa_cmd->macOffset, cesa_cmd->macLength); -+ dprintk("%s,%d: set digest in offset %x . \n", __FILE__, __LINE__, cesa_cmd->digestOffset); -+ if(debug) { -+ mvCesaDebugMbuf("SRC BUFFER", cesa_cmd->pSrc, 0, cesa_cmd->pSrc->mbufSize); -+ } -+ -+ -+ /* send action to HAL */ -+ spin_lock_irqsave(&cesa_lock, flags); -+ status = mvCesaAction(cesa_cmd); -+ spin_unlock_irqrestore(&cesa_lock, flags); -+ -+ /* action not allowed */ -+ if(status == MV_NOT_ALLOWED) { -+#ifdef CESA_OCF_SPLIT -+ /* if both encrypt and auth try to split */ -+ if(auth && (encrypt || decrypt)) { -+ MV_CESA_COMMAND *cesa_cmd_wa; -+ -+ /* malloc a new cesa process and init it */ -+ cesa_ocf_cmd_wa = kmalloc(sizeof(struct cesa_ocf_process), GFP_ATOMIC); -+ -+ if (cesa_ocf_cmd_wa == NULL) { -+ printk("%s,%d: ENOBUFS \n", __FILE__, __LINE__); -+ goto p_error; -+ } -+ memcpy(cesa_ocf_cmd_wa, cesa_ocf_cmd, sizeof(struct cesa_ocf_process)); -+ cesa_cmd_wa = &cesa_ocf_cmd_wa->cesa_cmd; -+ cesa_cmd_wa->pReqPrv = (void *)cesa_ocf_cmd_wa; -+ cesa_ocf_cmd_wa->need_cb = 0; -+ -+ /* break requests to two operation, first operation completion won't call callback */ -+ if((decrypt) && (cesa_ocf_cur_ses->auth_tn_decrypt)) { -+ cesa_cmd_wa->sessionId = cesa_ocf_cur_ses->frag_wa_auth; -+ cesa_cmd->sessionId = cesa_ocf_cur_ses->frag_wa_decrypt; -+ } -+ else if((decrypt) && !(cesa_ocf_cur_ses->auth_tn_decrypt)) { -+ cesa_cmd_wa->sessionId = cesa_ocf_cur_ses->frag_wa_decrypt; -+ cesa_cmd->sessionId = cesa_ocf_cur_ses->frag_wa_auth; -+ } -+ else if((encrypt) && (cesa_ocf_cur_ses->encrypt_tn_auth)) { -+ cesa_cmd_wa->sessionId = cesa_ocf_cur_ses->frag_wa_encrypt; -+ cesa_cmd->sessionId = cesa_ocf_cur_ses->frag_wa_auth; -+ } -+ else if((encrypt) && !(cesa_ocf_cur_ses->encrypt_tn_auth)){ -+ cesa_cmd_wa->sessionId = cesa_ocf_cur_ses->frag_wa_auth; -+ cesa_cmd->sessionId = cesa_ocf_cur_ses->frag_wa_encrypt; -+ } -+ else { -+ printk("%s,%d: Unsupporterd fragment wa mode \n", __FILE__, __LINE__); -+ goto p_error; -+ } -+ -+ /* send the 2 actions to the HAL */ -+ spin_lock_irqsave(&cesa_lock, flags); -+ status = mvCesaAction(cesa_cmd_wa); -+ spin_unlock_irqrestore(&cesa_lock, flags); -+ -+ if((status != MV_NO_MORE) && (status != MV_OK)) { -+ printk("%s,%d: cesa action failed, status = 0x%x\n", __FILE__, __LINE__, status); -+ goto p_error; -+ } -+ spin_lock_irqsave(&cesa_lock, flags); -+ status = mvCesaAction(cesa_cmd); -+ spin_unlock_irqrestore(&cesa_lock, flags); -+ -+ } -+ /* action not allowed and can't split */ -+ else -+#endif -+ { -+ goto p_error; -+ } -+ } -+ -+ /* Hal Q is full, send again. This should never happen */ -+ if(status == MV_NO_RESOURCE) { -+ printk("%s,%d: cesa no more resources \n", __FILE__, __LINE__); -+ if(cesa_ocf_cmd) -+ kfree(cesa_ocf_cmd); -+ if(cesa_ocf_cmd_wa) -+ kfree(cesa_ocf_cmd_wa); -+ return ERESTART; -+ } -+ else if((status != MV_NO_MORE) && (status != MV_OK)) { -+ printk("%s,%d: cesa action failed, status = 0x%x\n", __FILE__, __LINE__, status); -+ goto p_error; -+ } -+ -+ -+#ifdef CESA_OCF_POLLING -+ cesa_interrupt_polling(); -+#endif -+ cesaTestTraceAdd(5); -+ -+ return 0; -+p_error: -+ crp->crp_etype = EINVAL; -+ if(cesa_ocf_cmd) -+ kfree(cesa_ocf_cmd); -+ if(cesa_ocf_cmd_wa) -+ kfree(cesa_ocf_cmd_wa); -+ return EINVAL; -+} -+ -+/* -+ * cesa callback. -+ */ -+static void -+cesa_callback(unsigned long dummy) -+{ -+ struct cesa_ocf_process *cesa_ocf_cmd = NULL; -+ struct cryptop *crp = NULL; -+ MV_CESA_RESULT result[MV_CESA_MAX_CHAN]; -+ int res_idx = 0,i; -+ MV_STATUS status; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+#ifdef CESA_OCF_TASKLET -+ disable_irq(cesa_device.irq); -+#endif -+ while(MV_TRUE) { -+ -+ /* Get Ready requests */ -+ spin_lock(&cesa_lock); -+ status = mvCesaReadyGet(&result[res_idx]); -+ spin_unlock(&cesa_lock); -+ -+ cesaTestTraceAdd(2); -+ -+ if(status != MV_OK) { -+#ifdef CESA_OCF_POLLING -+ if(status == MV_BUSY) { /* Fragment */ -+ cesa_interrupt_polling(); -+ return; -+ } -+#endif -+ break; -+ } -+ res_idx++; -+ break; -+ } -+ -+ for(i = 0; i < res_idx; i++) { -+ -+ if(!result[i].pReqPrv) { -+ printk("%s,%d: warning private is NULL\n", __FILE__, __LINE__); -+ break; -+ } -+ -+ cesa_ocf_cmd = result[i].pReqPrv; -+ crp = cesa_ocf_cmd->crp; -+ -+ // ignore HMAC error. -+ //if(result->retCode) -+ // crp->crp_etype = EIO; -+ -+#if defined(CESA_OCF_POLLING) -+ if(!cesa_ocf_cmd->need_cb){ -+ cesa_interrupt_polling(); -+ } -+#endif -+ if(cesa_ocf_cmd->need_cb) { -+ if(debug) { -+ mvCesaDebugMbuf("DST BUFFER", cesa_ocf_cmd->cesa_cmd.pDst, 0, cesa_ocf_cmd->cesa_cmd.pDst->mbufSize); -+ } -+ crypto_done(crp); -+ } -+ kfree(cesa_ocf_cmd); -+ } -+#ifdef CESA_OCF_TASKLET -+ enable_irq(cesa_device.irq); -+#endif -+ -+ cesaTestTraceAdd(3); -+ -+ return; -+} -+ -+#ifdef CESA_OCF_POLLING -+static void -+cesa_interrupt_polling(void) -+{ -+ u32 cause; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ /* Read cause register */ -+ do { -+ cause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); -+ cause &= MV_CESA_CAUSE_ACC_DMA_ALL_MASK; -+ -+ } while (cause == 0); -+ -+ /* clear interrupts */ -+ MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); -+ -+ cesa_callback(0); -+ -+ return; -+} -+ -+#endif -+ -+/* -+ * cesa Interrupt polling routine. -+ */ -+static irqreturn_t -+cesa_interrupt_handler(int irq, void *arg) -+{ -+ u32 cause; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ cesaTestTraceAdd(0); -+ -+ /* Read cause register */ -+ cause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); -+ -+ if( (cause & MV_CESA_CAUSE_ACC_DMA_ALL_MASK) == 0) -+ { -+ /* Empty interrupt */ -+ dprintk("%s,%d: cesaTestReadyIsr: cause=0x%x\n", __FILE__, __LINE__, cause); -+ return IRQ_HANDLED; -+ } -+ -+ /* clear interrupts */ -+ MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); -+ -+ cesaTestTraceAdd(1); -+#ifdef CESA_OCF_TASKLET -+ tasklet_hi_schedule(&cesa_ocf_tasklet); -+#else -+ cesa_callback(0); -+#endif -+ return IRQ_HANDLED; -+} -+ -+/* -+ * Open a session. -+ */ -+static int -+/*cesa_ocf_newsession(void *arg, u_int32_t *sid, struct cryptoini *cri)*/ -+cesa_ocf_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) -+{ -+ u32 status = 0, i; -+ u32 count = 0, auth = 0, encrypt =0; -+ struct cesa_ocf_data *cesa_ocf_cur_ses; -+ MV_CESA_OPEN_SESSION cesa_session; -+ MV_CESA_OPEN_SESSION *cesa_ses = &cesa_session; -+ -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid == NULL || cri == NULL) { -+ printk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ /* leave first empty like in other implementations */ -+ for (i = 1; i < CESA_OCF_MAX_SES; i++) { -+ if (cesa_ocf_sessions[i] == NULL) -+ break; -+ } -+ -+ if(i >= CESA_OCF_MAX_SES) { -+ printk("%s,%d: no more sessions \n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ cesa_ocf_sessions[i] = (struct cesa_ocf_data *) kmalloc(sizeof(struct cesa_ocf_data), GFP_ATOMIC); -+ if (cesa_ocf_sessions[i] == NULL) { -+ cesa_ocf_freesession(NULL, i); -+ printk("%s,%d: ENOBUFS \n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ dprintk("%s,%d: new session %d \n", __FILE__, __LINE__, i); -+ -+ *sid = i; -+ cesa_ocf_cur_ses = cesa_ocf_sessions[i]; -+ memset(cesa_ocf_cur_ses, 0, sizeof(struct cesa_ocf_data)); -+ cesa_ocf_cur_ses->sid_encrypt = -1; -+ cesa_ocf_cur_ses->sid_decrypt = -1; -+ cesa_ocf_cur_ses->frag_wa_encrypt = -1; -+ cesa_ocf_cur_ses->frag_wa_decrypt = -1; -+ cesa_ocf_cur_ses->frag_wa_auth = -1; -+ -+ /* init the session */ -+ memset(cesa_ses, 0, sizeof(MV_CESA_OPEN_SESSION)); -+ count = 1; -+ while (cri) { -+ if(count > 2) { -+ printk("%s,%d: don't support more then 2 operations\n", __FILE__, __LINE__); -+ goto error; -+ } -+ switch (cri->cri_alg) { -+ case CRYPTO_AES_CBC: -+ dprintk("%s,%d: (%d) AES CBC \n", __FILE__, __LINE__, count); -+ cesa_ocf_cur_ses->cipher_alg = cri->cri_alg; -+ cesa_ocf_cur_ses->ivlen = MV_CESA_AES_BLOCK_SIZE; -+ cesa_ses->cryptoAlgorithm = MV_CESA_CRYPTO_AES; -+ cesa_ses->cryptoMode = MV_CESA_CRYPTO_CBC; -+ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { -+ printk("%s,%d: CRYPTO key too long.\n", __FILE__, __LINE__); -+ goto error; -+ } -+ memcpy(cesa_ses->cryptoKey, cri->cri_key, cri->cri_klen/8); -+ dprintk("%s,%d: key length %d \n", __FILE__, __LINE__, cri->cri_klen/8); -+ cesa_ses->cryptoKeyLength = cri->cri_klen/8; -+ encrypt += count; -+ break; -+ case CRYPTO_3DES_CBC: -+ dprintk("%s,%d: (%d) 3DES CBC \n", __FILE__, __LINE__, count); -+ cesa_ocf_cur_ses->cipher_alg = cri->cri_alg; -+ cesa_ocf_cur_ses->ivlen = MV_CESA_3DES_BLOCK_SIZE; -+ cesa_ses->cryptoAlgorithm = MV_CESA_CRYPTO_3DES; -+ cesa_ses->cryptoMode = MV_CESA_CRYPTO_CBC; -+ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { -+ printk("%s,%d: CRYPTO key too long.\n", __FILE__, __LINE__); -+ goto error; -+ } -+ memcpy(cesa_ses->cryptoKey, cri->cri_key, cri->cri_klen/8); -+ cesa_ses->cryptoKeyLength = cri->cri_klen/8; -+ encrypt += count; -+ break; -+ case CRYPTO_DES_CBC: -+ dprintk("%s,%d: (%d) DES CBC \n", __FILE__, __LINE__, count); -+ cesa_ocf_cur_ses->cipher_alg = cri->cri_alg; -+ cesa_ocf_cur_ses->ivlen = MV_CESA_DES_BLOCK_SIZE; -+ cesa_ses->cryptoAlgorithm = MV_CESA_CRYPTO_DES; -+ cesa_ses->cryptoMode = MV_CESA_CRYPTO_CBC; -+ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { -+ printk("%s,%d: CRYPTO key too long.\n", __FILE__, __LINE__); -+ goto error; -+ } -+ memcpy(cesa_ses->cryptoKey, cri->cri_key, cri->cri_klen/8); -+ cesa_ses->cryptoKeyLength = cri->cri_klen/8; -+ encrypt += count; -+ break; -+ case CRYPTO_MD5: -+ case CRYPTO_MD5_HMAC: -+ dprintk("%s,%d: (%d) %sMD5 CBC \n", __FILE__, __LINE__, count, (cri->cri_alg != CRYPTO_MD5)? "H-":" "); -+ cesa_ocf_cur_ses->auth_alg = cri->cri_alg; -+ cesa_ocf_cur_ses->digestlen = (cri->cri_alg == CRYPTO_MD5)? MV_CESA_MD5_DIGEST_SIZE : 12; -+ cesa_ses->macMode = (cri->cri_alg == CRYPTO_MD5)? MV_CESA_MAC_MD5 : MV_CESA_MAC_HMAC_MD5; -+ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { -+ printk("%s,%d: MAC key too long. \n", __FILE__, __LINE__); -+ goto error; -+ } -+ cesa_ses->macKeyLength = cri->cri_klen/8; -+ memcpy(cesa_ses->macKey, cri->cri_key, cri->cri_klen/8); -+ cesa_ses->digestSize = cesa_ocf_cur_ses->digestlen; -+ auth += count; -+ break; -+ case CRYPTO_SHA1: -+ case CRYPTO_SHA1_HMAC: -+ dprintk("%s,%d: (%d) %sSHA1 CBC \n", __FILE__, __LINE__, count, (cri->cri_alg != CRYPTO_SHA1)? "H-":" "); -+ cesa_ocf_cur_ses->auth_alg = cri->cri_alg; -+ cesa_ocf_cur_ses->digestlen = (cri->cri_alg == CRYPTO_SHA1)? MV_CESA_SHA1_DIGEST_SIZE : 12; -+ cesa_ses->macMode = (cri->cri_alg == CRYPTO_SHA1)? MV_CESA_MAC_SHA1 : MV_CESA_MAC_HMAC_SHA1; -+ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { -+ printk("%s,%d: MAC key too long. \n", __FILE__, __LINE__); -+ goto error; -+ } -+ cesa_ses->macKeyLength = cri->cri_klen/8; -+ memcpy(cesa_ses->macKey, cri->cri_key, cri->cri_klen/8); -+ cesa_ses->digestSize = cesa_ocf_cur_ses->digestlen; -+ auth += count; -+ break; -+ default: -+ printk("%s,%d: unknown algo 0x%x\n", __FILE__, __LINE__, cri->cri_alg); -+ goto error; -+ } -+ cri = cri->cri_next; -+ count++; -+ } -+ -+ if((encrypt > 2) || (auth > 2)) { -+ printk("%s,%d: session mode is not supported.\n", __FILE__, __LINE__); -+ goto error; -+ } -+ /* create new sessions in HAL */ -+ if(encrypt) { -+ cesa_ses->operation = MV_CESA_CRYPTO_ONLY; -+ /* encrypt session */ -+ if(auth == 1) { -+ cesa_ses->operation = MV_CESA_MAC_THEN_CRYPTO; -+ } -+ else if(auth == 2) { -+ cesa_ses->operation = MV_CESA_CRYPTO_THEN_MAC; -+ cesa_ocf_cur_ses->encrypt_tn_auth = 1; -+ } -+ else { -+ cesa_ses->operation = MV_CESA_CRYPTO_ONLY; -+ } -+ cesa_ses->direction = MV_CESA_DIR_ENCODE; -+ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->sid_encrypt); -+ if(status != MV_OK) { -+ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); -+ goto error; -+ } -+ /* decrypt session */ -+ if( cesa_ses->operation == MV_CESA_MAC_THEN_CRYPTO ) { -+ cesa_ses->operation = MV_CESA_CRYPTO_THEN_MAC; -+ } -+ else if( cesa_ses->operation == MV_CESA_CRYPTO_THEN_MAC ) { -+ cesa_ses->operation = MV_CESA_MAC_THEN_CRYPTO; -+ } -+ cesa_ses->direction = MV_CESA_DIR_DECODE; -+ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->sid_decrypt); -+ if(status != MV_OK) { -+ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); -+ goto error; -+ } -+ -+ /* preapre one action sessions for case we will need to split an action */ -+#ifdef CESA_OCF_SPLIT -+ if(( cesa_ses->operation == MV_CESA_MAC_THEN_CRYPTO ) || -+ ( cesa_ses->operation == MV_CESA_CRYPTO_THEN_MAC )) { -+ /* open one session for encode and one for decode */ -+ cesa_ses->operation = MV_CESA_CRYPTO_ONLY; -+ cesa_ses->direction = MV_CESA_DIR_ENCODE; -+ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->frag_wa_encrypt); -+ if(status != MV_OK) { -+ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); -+ goto error; -+ } -+ -+ cesa_ses->direction = MV_CESA_DIR_DECODE; -+ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->frag_wa_decrypt); -+ if(status != MV_OK) { -+ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); -+ goto error; -+ } -+ /* open one session for auth */ -+ cesa_ses->operation = MV_CESA_MAC_ONLY; -+ cesa_ses->direction = MV_CESA_DIR_ENCODE; -+ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->frag_wa_auth); -+ if(status != MV_OK) { -+ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); -+ goto error; -+ } -+ } -+#endif -+ } -+ else { /* only auth */ -+ cesa_ses->operation = MV_CESA_MAC_ONLY; -+ cesa_ses->direction = MV_CESA_DIR_ENCODE; -+ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->sid_encrypt); -+ if(status != MV_OK) { -+ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); -+ goto error; -+ } -+ } -+ -+ return 0; -+error: -+ cesa_ocf_freesession(NULL, *sid); -+ return EINVAL; -+ -+} -+ -+ -+/* -+ * Free a session. -+ */ -+static int -+cesa_ocf_freesession(device_t dev, u_int64_t tid) -+{ -+ struct cesa_ocf_data *cesa_ocf_cur_ses; -+ u_int32_t sid = CRYPTO_SESID2LID(tid); -+ //unsigned long flags; -+ -+ dprintk("%s() %d \n", __FUNCTION__, sid); -+ if ( (sid >= CESA_OCF_MAX_SES) || (cesa_ocf_sessions[sid] == NULL) ) { -+ printk("%s,%d: EINVAL can't free session %d \n", __FILE__, __LINE__, sid); -+ return(EINVAL); -+ } -+ -+ /* Silently accept and return */ -+ if (sid == 0) -+ return(0); -+ -+ /* release session from HAL */ -+ cesa_ocf_cur_ses = cesa_ocf_sessions[sid]; -+ if (cesa_ocf_cur_ses->sid_encrypt != -1) { -+ mvCesaSessionClose(cesa_ocf_cur_ses->sid_encrypt); -+ } -+ if (cesa_ocf_cur_ses->sid_decrypt != -1) { -+ mvCesaSessionClose(cesa_ocf_cur_ses->sid_decrypt); -+ } -+ if (cesa_ocf_cur_ses->frag_wa_encrypt != -1) { -+ mvCesaSessionClose(cesa_ocf_cur_ses->frag_wa_encrypt); -+ } -+ if (cesa_ocf_cur_ses->frag_wa_decrypt != -1) { -+ mvCesaSessionClose(cesa_ocf_cur_ses->frag_wa_decrypt); -+ } -+ if (cesa_ocf_cur_ses->frag_wa_auth != -1) { -+ mvCesaSessionClose(cesa_ocf_cur_ses->frag_wa_auth); -+ } -+ -+ kfree(cesa_ocf_cur_ses); -+ cesa_ocf_sessions[sid] = NULL; -+ -+ return 0; -+} -+ -+ -+/* TDMA Window setup */ -+ -+static void __init -+setup_tdma_mbus_windows(struct cesa_dev *dev) -+{ -+ int i; -+ -+ for (i = 0; i < 4; i++) { -+ writel(0, dev->reg + WINDOW_BASE(i)); -+ writel(0, dev->reg + WINDOW_CTRL(i)); -+ } -+ -+ for (i = 0; i < dev->plat_data->dram->num_cs; i++) { -+ struct mbus_dram_window *cs = dev->plat_data->dram->cs + i; -+ writel( -+ ((cs->size - 1) & 0xffff0000) | -+ (cs->mbus_attr << 8) | -+ (dev->plat_data->dram->mbus_dram_target_id << 4) | 1, -+ dev->reg + WINDOW_CTRL(i) -+ ); -+ writel(cs->base, dev->reg + WINDOW_BASE(i)); -+ } -+} -+ -+/* -+ * our driver startup and shutdown routines -+ */ -+static int -+mv_cesa_ocf_init(struct platform_device *pdev) -+{ -+#if defined(CONFIG_MV78200) || defined(CONFIG_MV632X) -+ if (MV_FALSE == mvSocUnitIsMappedToThisCpu(CESA)) -+ { -+ dprintk("CESA is not mapped to this CPU\n"); -+ return -ENODEV; -+ } -+#endif -+ -+ dprintk("%s\n", __FUNCTION__); -+ memset(&mv_cesa_dev, 0, sizeof(mv_cesa_dev)); -+ softc_device_init(&mv_cesa_dev, "MV CESA", 0, mv_cesa_methods); -+ cesa_ocf_id = crypto_get_driverid(softc_get_device(&mv_cesa_dev),CRYPTOCAP_F_HARDWARE); -+ -+ if (cesa_ocf_id < 0) -+ panic("MV CESA crypto device cannot initialize!"); -+ -+ dprintk("%s,%d: cesa ocf device id is %d \n", __FILE__, __LINE__, cesa_ocf_id); -+ -+ /* CESA unit is auto power on off */ -+#if 0 -+ if (MV_FALSE == mvCtrlPwrClckGet(CESA_UNIT_ID,0)) -+ { -+ printk("\nWarning CESA %d is Powered Off\n",0); -+ return EINVAL; -+ } -+#endif -+ -+ memset(&cesa_device, 0, sizeof(struct cesa_dev)); -+ /* Get the IRQ, and crypto memory regions */ -+ { -+ struct resource *res; -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram"); -+ -+ if (!res) -+ return -ENXIO; -+ -+ cesa_device.sram = ioremap(res->start, res->end - res->start + 1); -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); -+ -+ if (!res) { -+ iounmap(cesa_device.sram); -+ return -ENXIO; -+ } -+ cesa_device.reg = ioremap(res->start, res->end - res->start + 1); -+ cesa_device.irq = platform_get_irq(pdev, 0); -+ cesa_device.plat_data = pdev->dev.platform_data; -+ setup_tdma_mbus_windows(&cesa_device); -+ -+ } -+ -+ -+ if( MV_OK != mvCesaInit(CESA_OCF_MAX_SES*5, CESA_Q_SIZE, cesa_device.reg, -+ NULL) ) { -+ printk("%s,%d: mvCesaInit Failed. \n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ /* clear and unmask Int */ -+ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); -+#ifndef CESA_OCF_POLLING -+ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, MV_CESA_CAUSE_ACC_DMA_MASK); -+#endif -+#ifdef CESA_OCF_TASKLET -+ tasklet_init(&cesa_ocf_tasklet, cesa_callback, (unsigned int) 0); -+#endif -+ /* register interrupt */ -+ if( request_irq( cesa_device.irq, cesa_interrupt_handler, -+ (IRQF_DISABLED) , "cesa", &cesa_ocf_id) < 0) { -+ printk("%s,%d: cannot assign irq %x\n", __FILE__, __LINE__, cesa_device.reg); -+ return EINVAL; -+ } -+ -+ -+ memset(cesa_ocf_sessions, 0, sizeof(struct cesa_ocf_data *) * CESA_OCF_MAX_SES); -+ -+#define REGISTER(alg) \ -+ crypto_register(cesa_ocf_id, alg, 0,0) -+ REGISTER(CRYPTO_AES_CBC); -+ REGISTER(CRYPTO_DES_CBC); -+ REGISTER(CRYPTO_3DES_CBC); -+ REGISTER(CRYPTO_MD5); -+ REGISTER(CRYPTO_MD5_HMAC); -+ REGISTER(CRYPTO_SHA1); -+ REGISTER(CRYPTO_SHA1_HMAC); -+#undef REGISTER -+ -+ return 0; -+} -+ -+static void -+mv_cesa_ocf_exit(struct platform_device *pdev) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ crypto_unregister_all(cesa_ocf_id); -+ cesa_ocf_id = -1; -+ iounmap(cesa_device.reg); -+ iounmap(cesa_device.sram); -+ free_irq(cesa_device.irq, NULL); -+ -+ /* mask and clear Int */ -+ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, 0); -+ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); -+ -+ -+ if( MV_OK != mvCesaFinish() ) { -+ printk("%s,%d: mvCesaFinish Failed. \n", __FILE__, __LINE__); -+ return; -+ } -+} -+ -+ -+void cesa_ocf_debug(void) -+{ -+ -+#ifdef CESA_OCF_TRACE_DEBUG -+ { -+ int i, j; -+ j = cesaTestTraceIdx; -+ mvOsPrintf("No Type rCause iCause Proc Isr Res Time pReady pProc pEmpty\n"); -+ for(i=0; i= _1G) -+ { -+ mvOsOutput("%3dGB ", size / _1G); -+ size %= _1G; -+ if(size) -+ mvOsOutput("+"); -+ } -+ if(size >= _1M ) -+ { -+ mvOsOutput("%3dMB ", size / _1M); -+ size %= _1M; -+ if(size) -+ mvOsOutput("+"); -+ } -+ if(size >= _1K) -+ { -+ mvOsOutput("%3dKB ", size / _1K); -+ size %= _1K; -+ if(size) -+ mvOsOutput("+"); -+ } -+ if(size > 0) -+ { -+ mvOsOutput("%3dB ", size); -+ } -+} -+ -+/******************************************************************************* -+* mvHexToBin - Convert hex to binary -+* -+* DESCRIPTION: -+* This function Convert hex to binary. -+* -+* INPUT: -+* pHexStr - hex buffer pointer. -+* size - Size to convert. -+* -+* OUTPUT: -+* pBin - Binary buffer pointer. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvHexToBin(const char* pHexStr, MV_U8* pBin, int size) -+{ -+ int j, i; -+ char tmp[3]; -+ MV_U8 byte; -+ -+ for(j=0, i=0; j> 1; -+ result++; -+ } -+ return result; -+} -+ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/common/mvCommon.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/common/mvCommon.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/common/mvCommon.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/common/mvCommon.h 2010-11-09 20:28:06.212495496 +0100 -@@ -0,0 +1,308 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+ -+#ifndef __INCmvCommonh -+#define __INCmvCommonh -+ -+#include "mvTypes.h" -+ -+/* Swap tool */ -+ -+/* 16bit nibble swap. For example 0x1234 -> 0x2143 */ -+#define MV_NIBBLE_SWAP_16BIT(X) (((X&0xf) << 4) | \ -+ ((X&0xf0) >> 4) | \ -+ ((X&0xf00) << 4) | \ -+ ((X&0xf000) >> 4)) -+ -+/* 32bit nibble swap. For example 0x12345678 -> 0x21436587 */ -+#define MV_NIBBLE_SWAP_32BIT(X) (((X&0xf) << 4) | \ -+ ((X&0xf0) >> 4) | \ -+ ((X&0xf00) << 4) | \ -+ ((X&0xf000) >> 4) | \ -+ ((X&0xf0000) << 4) | \ -+ ((X&0xf00000) >> 4) | \ -+ ((X&0xf000000) << 4) | \ -+ ((X&0xf0000000) >> 4)) -+ -+/* 16bit byte swap. For example 0x1122 -> 0x2211 */ -+#define MV_BYTE_SWAP_16BIT(X) ((((X)&0xff)<<8) | (((X)&0xff00)>>8)) -+ -+/* 32bit byte swap. For example 0x11223344 -> 0x44332211 */ -+#define MV_BYTE_SWAP_32BIT(X) ((((X)&0xff)<<24) | \ -+ (((X)&0xff00)<<8) | \ -+ (((X)&0xff0000)>>8) | \ -+ (((X)&0xff000000)>>24)) -+ -+/* 64bit byte swap. For example 0x11223344.55667788 -> 0x88776655.44332211 */ -+#define MV_BYTE_SWAP_64BIT(X) ((l64) ((((X)&0xffULL)<<56) | \ -+ (((X)&0xff00ULL)<<40) | \ -+ (((X)&0xff0000ULL)<<24) | \ -+ (((X)&0xff000000ULL)<<8) | \ -+ (((X)&0xff00000000ULL)>>8) | \ -+ (((X)&0xff0000000000ULL)>>24) | \ -+ (((X)&0xff000000000000ULL)>>40) | \ -+ (((X)&0xff00000000000000ULL)>>56))) -+ -+/* Endianess macros. */ -+#if defined(MV_CPU_LE) -+ #define MV_16BIT_LE(X) (X) -+ #define MV_32BIT_LE(X) (X) -+ #define MV_64BIT_LE(X) (X) -+ #define MV_16BIT_BE(X) MV_BYTE_SWAP_16BIT(X) -+ #define MV_32BIT_BE(X) MV_BYTE_SWAP_32BIT(X) -+ #define MV_64BIT_BE(X) MV_BYTE_SWAP_64BIT(X) -+#elif defined(MV_CPU_BE) -+ #define MV_16BIT_LE(X) MV_BYTE_SWAP_16BIT(X) -+ #define MV_32BIT_LE(X) MV_BYTE_SWAP_32BIT(X) -+ #define MV_64BIT_LE(X) MV_BYTE_SWAP_64BIT(X) -+ #define MV_16BIT_BE(X) (X) -+ #define MV_32BIT_BE(X) (X) -+ #define MV_64BIT_BE(X) (X) -+#else -+ #error "CPU endianess isn't defined!\n" -+#endif -+ -+ -+/* Bit field definitions */ -+#define NO_BIT 0x00000000 -+#define BIT0 0x00000001 -+#define BIT1 0x00000002 -+#define BIT2 0x00000004 -+#define BIT3 0x00000008 -+#define BIT4 0x00000010 -+#define BIT5 0x00000020 -+#define BIT6 0x00000040 -+#define BIT7 0x00000080 -+#define BIT8 0x00000100 -+#define BIT9 0x00000200 -+#define BIT10 0x00000400 -+#define BIT11 0x00000800 -+#define BIT12 0x00001000 -+#define BIT13 0x00002000 -+#define BIT14 0x00004000 -+#define BIT15 0x00008000 -+#define BIT16 0x00010000 -+#define BIT17 0x00020000 -+#define BIT18 0x00040000 -+#define BIT19 0x00080000 -+#define BIT20 0x00100000 -+#define BIT21 0x00200000 -+#define BIT22 0x00400000 -+#define BIT23 0x00800000 -+#define BIT24 0x01000000 -+#define BIT25 0x02000000 -+#define BIT26 0x04000000 -+#define BIT27 0x08000000 -+#define BIT28 0x10000000 -+#define BIT29 0x20000000 -+#define BIT30 0x40000000 -+#define BIT31 0x80000000 -+ -+/* Handy sizes */ -+#define _1K 0x00000400 -+#define _2K 0x00000800 -+#define _4K 0x00001000 -+#define _8K 0x00002000 -+#define _16K 0x00004000 -+#define _32K 0x00008000 -+#define _64K 0x00010000 -+#define _128K 0x00020000 -+#define _256K 0x00040000 -+#define _512K 0x00080000 -+ -+#define _1M 0x00100000 -+#define _2M 0x00200000 -+#define _4M 0x00400000 -+#define _8M 0x00800000 -+#define _16M 0x01000000 -+#define _32M 0x02000000 -+#define _64M 0x04000000 -+#define _128M 0x08000000 -+#define _256M 0x10000000 -+#define _512M 0x20000000 -+ -+#define _1G 0x40000000 -+#define _2G 0x80000000 -+ -+/* Tclock and Sys clock define */ -+#define _100MHz 100000000 -+#define _125MHz 125000000 -+#define _133MHz 133333334 -+#define _150MHz 150000000 -+#define _160MHz 160000000 -+#define _166MHz 166666667 -+#define _175MHz 175000000 -+#define _178MHz 178000000 -+#define _183MHz 183333334 -+#define _187MHz 187000000 -+#define _192MHz 192000000 -+#define _194MHz 194000000 -+#define _200MHz 200000000 -+#define _233MHz 233333334 -+#define _250MHz 250000000 -+#define _266MHz 266666667 -+#define _300MHz 300000000 -+ -+/* For better address window table readability */ -+#define EN MV_TRUE -+#define DIS MV_FALSE -+#define N_A -1 /* Not applicable */ -+ -+/* Cache configuration options for memory (DRAM, SRAM, ... ) */ -+ -+/* Memory uncached, HW or SW cache coherency is not needed */ -+#define MV_UNCACHED 0 -+/* Memory cached, HW cache coherency supported in WriteThrough mode */ -+#define MV_CACHE_COHER_HW_WT 1 -+/* Memory cached, HW cache coherency supported in WriteBack mode */ -+#define MV_CACHE_COHER_HW_WB 2 -+/* Memory cached, No HW cache coherency, Cache coherency must be in SW */ -+#define MV_CACHE_COHER_SW 3 -+ -+ -+/* Macro for testing aligment. Positive if number is NOT aligned */ -+#define MV_IS_NOT_ALIGN(number, align) ((number) & ((align) - 1)) -+ -+/* Macro for alignment up. For example, MV_ALIGN_UP(0x0330, 0x20) = 0x0340 */ -+#define MV_ALIGN_UP(number, align) \ -+(((number) & ((align) - 1)) ? (((number) + (align)) & ~((align)-1)) : (number)) -+ -+/* Macro for alignment down. For example, MV_ALIGN_UP(0x0330, 0x20) = 0x0320 */ -+#define MV_ALIGN_DOWN(number, align) ((number) & ~((align)-1)) -+ -+/* This macro returns absolute value */ -+#define MV_ABS(number) (((int)(number) < 0) ? -(int)(number) : (int)(number)) -+ -+ -+/* Bit fields manipulation macros */ -+ -+/* An integer word which its 'x' bit is set */ -+#define MV_BIT_MASK(bitNum) (1 << (bitNum) ) -+ -+/* Checks wheter bit 'x' in integer word is set */ -+#define MV_BIT_CHECK(word, bitNum) ( (word) & MV_BIT_MASK(bitNum) ) -+ -+/* Clear (reset) bit 'x' in integer word (RMW - Read-Modify-Write) */ -+#define MV_BIT_CLEAR(word, bitNum) ( (word) &= ~(MV_BIT_MASK(bitNum)) ) -+ -+/* Set bit 'x' in integer word (RMW) */ -+#define MV_BIT_SET(word, bitNum) ( (word) |= MV_BIT_MASK(bitNum) ) -+ -+/* Invert bit 'x' in integer word (RMW) */ -+#define MV_BIT_INV(word, bitNum) ( (word) ^= MV_BIT_MASK(bitNum) ) -+ -+/* Get the min between 'a' or 'b' */ -+#define MV_MIN(a,b) (((a) < (b)) ? (a) : (b)) -+ -+/* Get the max between 'a' or 'b' */ -+#define MV_MAX(a,b) (((a) < (b)) ? (b) : (a)) -+ -+/* Temporary */ -+#define mvOsDivide(num, div) \ -+({ \ -+ int i=0, rem=(num); \ -+ \ -+ while(rem >= (div)) \ -+ { \ -+ rem -= (div); \ -+ i++; \ -+ } \ -+ (i); \ -+}) -+ -+/* Temporary */ -+#define mvOsReminder(num, div) \ -+({ \ -+ int rem = (num); \ -+ \ -+ while(rem >= (div)) \ -+ rem -= (div); \ -+ (rem); \ -+}) -+ -+#define MV_IP_QUAD(ipAddr) ((ipAddr >> 24) & 0xFF), ((ipAddr >> 16) & 0xFF), \ -+ ((ipAddr >> 8) & 0xFF), ((ipAddr >> 0) & 0xFF) -+ -+#define MV_IS_POWER_OF_2(num) ((num != 0) && ((num & (num - 1)) == 0)) -+ -+#ifndef MV_ASMLANGUAGE -+/* mvCommon API list */ -+ -+MV_VOID mvHexToBin(const char* pHexStr, MV_U8* pBin, int size); -+void mvAsciiToHex(const char* asciiStr, char* hexStr); -+void mvBinToHex(const MV_U8* bin, char* hexStr, int size); -+void mvBinToAscii(const MV_U8* bin, char* asciiStr, int size); -+ -+MV_STATUS mvMacStrToHex(const char* macStr, MV_U8* macHex); -+MV_STATUS mvMacHexToStr(MV_U8* macHex, char* macStr); -+void mvSizePrint(MV_U32); -+ -+MV_U32 mvLog2(MV_U32 num); -+ -+#endif /* MV_ASMLANGUAGE */ -+ -+ -+#endif /* __INCmvCommonh */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/common/mvDebug.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/common/mvDebug.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/common/mvDebug.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/common/mvDebug.c 2010-11-09 20:28:06.252495437 +0100 -@@ -0,0 +1,326 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+ -+/* includes */ -+#include "mvOs.h" -+#include "mv802_3.h" -+#include "mvCommon.h" -+#include "mvDebug.h" -+ -+/* Global variables effect on behave MV_DEBUG_PRINT and MV_DEBUG_CODE macros -+ * mvDebug - map of bits (one for each module) bit=1 means enable -+ * debug code and messages for this module -+ * mvModuleDebug - array of 32 bits varables one for each module -+ */ -+MV_U32 mvDebug = 0; -+MV_U32 mvDebugModules[MV_MODULE_MAX]; -+ -+/* Init mvModuleDebug array to default values */ -+void mvDebugInit(void) -+{ -+ int bit; -+ -+ mvDebug = 0; -+ for(bit=0; bit 0) -+ { -+ mvOsPrintf("%08x: ", memAddr); -+ i = 0; -+ /* 32 bytes in the line */ -+ while(i < 32) -+ { -+ if(memAddr >= (MV_U32)addr) -+ { -+ switch(access) -+ { -+ case 1: -+ if( memAddr == CPU_PHY_MEM(memAddr) ) -+ { -+ mvOsPrintf("%02x ", MV_MEMIO8_READ(memAddr)); -+ } -+ else -+ { -+ mvOsPrintf("%02x ", *((MV_U8*)memAddr)); -+ } -+ break; -+ -+ case 2: -+ if( memAddr == CPU_PHY_MEM(memAddr) ) -+ { -+ mvOsPrintf("%04x ", MV_MEMIO16_READ(memAddr)); -+ } -+ else -+ { -+ mvOsPrintf("%04x ", *((MV_U16*)memAddr)); -+ } -+ break; -+ -+ case 4: -+ if( memAddr == CPU_PHY_MEM(memAddr) ) -+ { -+ mvOsPrintf("%08x ", MV_MEMIO32_READ(memAddr)); -+ } -+ else -+ { -+ mvOsPrintf("%08x ", *((MV_U32*)memAddr)); -+ } -+ break; -+ } -+ } -+ else -+ { -+ for(j=0; j<(access*2+1); j++) -+ mvOsPrintf(" "); -+ } -+ i += access; -+ memAddr += access; -+ size -= access; -+ if(size <= 0) -+ break; -+ } -+ mvOsPrintf("\n"); -+ } -+} -+ -+void mvDebugPrintBufInfo(BUF_INFO* pBufInfo, int size, int access) -+{ -+ if(pBufInfo == NULL) -+ { -+ mvOsPrintf("\n!!! pBufInfo = NULL\n"); -+ return; -+ } -+ mvOsPrintf("\n*** pBufInfo=0x%x, cmdSts=0x%08x, pBuf=0x%x, bufSize=%d\n", -+ (unsigned int)pBufInfo, -+ (unsigned int)pBufInfo->cmdSts, -+ (unsigned int)pBufInfo->pBuff, -+ (unsigned int)pBufInfo->bufSize); -+ mvOsPrintf("pData=0x%x, byteCnt=%d, pNext=0x%x, uInfo1=0x%x, uInfo2=0x%x\n", -+ (unsigned int)pBufInfo->pData, -+ (unsigned int)pBufInfo->byteCnt, -+ (unsigned int)pBufInfo->pNextBufInfo, -+ (unsigned int)pBufInfo->userInfo1, -+ (unsigned int)pBufInfo->userInfo2); -+ if(pBufInfo->pData != NULL) -+ { -+ if(size > pBufInfo->byteCnt) -+ size = pBufInfo->byteCnt; -+ mvDebugMemDump(pBufInfo->pData, size, access); -+ } -+} -+ -+void mvDebugPrintPktInfo(MV_PKT_INFO* pPktInfo, int size, int access) -+{ -+ int frag, len; -+ -+ if(pPktInfo == NULL) -+ { -+ mvOsPrintf("\n!!! pPktInfo = NULL\n"); -+ return; -+ } -+ mvOsPrintf("\npPkt=%p, stat=0x%08x, numFr=%d, size=%d, pFr=%p, osInfo=0x%lx\n", -+ pPktInfo, pPktInfo->status, pPktInfo->numFrags, pPktInfo->pktSize, -+ pPktInfo->pFrags, pPktInfo->osInfo); -+ -+ for(frag=0; fragnumFrags; frag++) -+ { -+ mvOsPrintf("#%2d. bufVirt=%p, bufSize=%d\n", -+ frag, pPktInfo->pFrags[frag].bufVirtPtr, -+ pPktInfo->pFrags[frag].bufSize); -+ if(size > 0) -+ { -+ len = MV_MIN((int)pPktInfo->pFrags[frag].bufSize, size); -+ mvDebugMemDump(pPktInfo->pFrags[frag].bufVirtPtr, len, access); -+ size -= len; -+ } -+ } -+ -+} -+ -+void mvDebugPrintIpAddr(MV_U32 ipAddr) -+{ -+ mvOsPrintf("%d.%d.%d.%d", ((ipAddr >> 24) & 0xFF), ((ipAddr >> 16) & 0xFF), -+ ((ipAddr >> 8) & 0xFF), ((ipAddr >> 0) & 0xFF)); -+} -+ -+void mvDebugPrintMacAddr(const MV_U8* pMacAddr) -+{ -+ int i; -+ -+ mvOsPrintf("%02x", (unsigned int)pMacAddr[0]); -+ for(i=1; ibegin = 0; -+ pTimeEntry->count = count; -+ pTimeEntry->end = 0; -+ pTimeEntry->left = pTimeEntry->count; -+ pTimeEntry->total = 0; -+ pTimeEntry->min = 0xFFFFFFFF; -+ pTimeEntry->max = 0x0; -+ strncpy(pTimeEntry->name, pName, sizeof(pTimeEntry->name)-1); -+ pTimeEntry->name[sizeof(pTimeEntry->name)-1] = '\0'; -+} -+ -+/* Print out MV_DEBUG_TIMES entry */ -+void mvDebugPrintTimeEntry(MV_DEBUG_TIMES* pTimeEntry, MV_BOOL isTitle) -+{ -+ int num; -+ -+ if(isTitle == MV_TRUE) -+ mvOsPrintf("Event NumOfEvents TotalTime Average Min Max\n"); -+ -+ num = pTimeEntry->count-pTimeEntry->left; -+ if(num > 0) -+ { -+ mvOsPrintf("%-11s %6u 0x%08lx %6lu %6lu %6lu\n", -+ pTimeEntry->name, num, pTimeEntry->total, pTimeEntry->total/num, -+ pTimeEntry->min, pTimeEntry->max); -+ } -+} -+ -+/* Update MV_DEBUG_TIMES entry */ -+void mvDebugUpdateTimeEntry(MV_DEBUG_TIMES* pTimeEntry) -+{ -+ MV_U32 delta; -+ -+ if(pTimeEntry->left > 0) -+ { -+ if(pTimeEntry->end <= pTimeEntry->begin) -+ { -+ delta = pTimeEntry->begin - pTimeEntry->end; -+ } -+ else -+ { -+ delta = ((MV_U32)0x10000 - pTimeEntry->end) + pTimeEntry->begin; -+ } -+ pTimeEntry->total += delta; -+ -+ if(delta < pTimeEntry->min) -+ pTimeEntry->min = delta; -+ -+ if(delta > pTimeEntry->max) -+ pTimeEntry->max = delta; -+ -+ pTimeEntry->left--; -+ } -+} -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/common/mvDebug.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/common/mvDebug.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/common/mvDebug.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/common/mvDebug.h 2010-11-09 20:28:06.292495404 +0100 -@@ -0,0 +1,178 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+ -+#ifndef __INCmvDebugh -+#define __INCmvDebugh -+ -+/* includes */ -+#include "mvTypes.h" -+ -+typedef enum -+{ -+ MV_MODULE_INVALID = -1, -+ MV_MODULE_ETH = 0, -+ MV_MODULE_IDMA, -+ MV_MODULE_XOR, -+ MV_MODULE_TWASI, -+ MV_MODULE_MGI, -+ MV_MODULE_USB, -+ MV_MODULE_CESA, -+ -+ MV_MODULE_MAX -+}MV_MODULE_ID; -+ -+/* Define generic flags useful for most of modules */ -+#define MV_DEBUG_FLAG_ALL (0) -+#define MV_DEBUG_FLAG_INIT (1 << 0) -+#define MV_DEBUG_FLAG_RX (1 << 1) -+#define MV_DEBUG_FLAG_TX (1 << 2) -+#define MV_DEBUG_FLAG_ERR (1 << 3) -+#define MV_DEBUG_FLAG_TRACE (1 << 4) -+#define MV_DEBUG_FLAG_DUMP (1 << 5) -+#define MV_DEBUG_FLAG_CACHE (1 << 6) -+#define MV_DEBUG_FLAG_IOCTL (1 << 7) -+#define MV_DEBUG_FLAG_STATS (1 << 8) -+ -+extern MV_U32 mvDebug; -+extern MV_U32 mvDebugModules[MV_MODULE_MAX]; -+ -+#ifdef MV_DEBUG -+# define MV_DEBUG_PRINT(module, flags, msg) mvOsPrintf msg -+# define MV_DEBUG_CODE(module, flags, code) code -+#elif defined(MV_RT_DEBUG) -+# define MV_DEBUG_PRINT(module, flags, msg) \ -+ if( (mvDebug & (1<<(module))) && \ -+ ((mvDebugModules[(module)] & (flags)) == (flags)) ) \ -+ mvOsPrintf msg -+# define MV_DEBUG_CODE(module, flags, code) \ -+ if( (mvDebug & (1<<(module))) && \ -+ ((mvDebugModules[(module)] & (flags)) == (flags)) ) \ -+ code -+#else -+# define MV_DEBUG_PRINT(module, flags, msg) -+# define MV_DEBUG_CODE(module, flags, code) -+#endif -+ -+ -+ -+/* typedefs */ -+ -+/* time measurement structure used to check how much time pass between -+ * two points -+ */ -+typedef struct { -+ char name[20]; /* name of the entry */ -+ unsigned long begin; /* time measured on begin point */ -+ unsigned long end; /* time measured on end point */ -+ unsigned long total; /* Accumulated time */ -+ unsigned long left; /* The rest measurement actions */ -+ unsigned long count; /* Maximum measurement actions */ -+ unsigned long min; /* Minimum time from begin to end */ -+ unsigned long max; /* Maximum time from begin to end */ -+} MV_DEBUG_TIMES; -+ -+ -+/* mvDebug.h API list */ -+ -+/****** Error Recording ******/ -+ -+/* Dump memory in specific format: -+ * address: X1X1X1X1 X2X2X2X2 ... X8X8X8X8 -+ */ -+void mvDebugMemDump(void* addr, int size, int access); -+ -+void mvDebugPrintBufInfo(BUF_INFO* pBufInfo, int size, int access); -+ -+void mvDebugPrintPktInfo(MV_PKT_INFO* pPktInfo, int size, int access); -+ -+void mvDebugPrintIpAddr(MV_U32 ipAddr); -+ -+void mvDebugPrintMacAddr(const MV_U8* pMacAddr); -+ -+/**** There are three functions deals with MV_DEBUG_TIMES structure ****/ -+ -+/* Reset MV_DEBUG_TIMES entry */ -+void mvDebugResetTimeEntry(MV_DEBUG_TIMES* pTimeEntry, int count, char* name); -+ -+/* Update MV_DEBUG_TIMES entry */ -+void mvDebugUpdateTimeEntry(MV_DEBUG_TIMES* pTimeEntry); -+ -+/* Print out MV_DEBUG_TIMES entry */ -+void mvDebugPrintTimeEntry(MV_DEBUG_TIMES* pTimeEntry, MV_BOOL isTitle); -+ -+ -+/******** General ***********/ -+ -+/* Change value of mvDebugPrint global variable */ -+ -+void mvDebugInit(void); -+void mvDebugModuleEnable(MV_MODULE_ID module, MV_BOOL isEnable); -+void mvDebugModuleSetFlags(MV_MODULE_ID module, MV_U32 flags); -+void mvDebugModuleClearFlags(MV_MODULE_ID module, MV_U32 flags); -+ -+ -+#endif /* __INCmvDebug.h */ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h 2010-11-09 20:28:06.332495486 +0100 -@@ -0,0 +1,225 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvDeviceIdh -+#define __INCmvDeviceIdh -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* defines */ -+#define MARVELL_VEN_ID 0x11ab -+ -+/* Disco-3 */ -+#define MV64460_DEV_ID 0x6480 -+#define MV64460B_DEV_ID 0x6485 -+#define MV64430_DEV_ID 0x6420 -+ -+/* Disco-5 */ -+#define MV64560_DEV_ID 0x6450 -+ -+/* Disco-6 */ -+#define MV64660_DEV_ID 0x6460 -+ -+/* Orion */ -+#define MV_1181_DEV_ID 0x1181 -+#define MV_5181_DEV_ID 0x5181 -+#define MV_5281_DEV_ID 0x5281 -+#define MV_5182_DEV_ID 0x5182 -+#define MV_8660_DEV_ID 0x8660 -+#define MV_5180_DEV_ID 0x5180 -+#define MV_5082_DEV_ID 0x5082 -+#define MV_1281_DEV_ID 0x1281 -+#define MV_6082_DEV_ID 0x6082 -+#define MV_6183_DEV_ID 0x6183 -+#define MV_6183L_DEV_ID 0x6083 -+ -+#define MV_5281_D0_REV 0x4 -+#define MV_5281_D0_ID ((MV_5281_DEV_ID << 16) | MV_5281_D0_REV) -+#define MV_5281_D0_NAME "88F5281 D0" -+ -+#define MV_5281_D1_REV 0x5 -+#define MV_5281_D1_ID ((MV_5281_DEV_ID << 16) | MV_5281_D1_REV) -+#define MV_5281_D1_NAME "88F5281 D1" -+ -+#define MV_5281_D2_REV 0x6 -+#define MV_5281_D2_ID ((MV_5281_DEV_ID << 16) | MV_5281_D2_REV) -+#define MV_5281_D2_NAME "88F5281 D2" -+ -+ -+#define MV_5181L_A0_REV 0x8 /* need for PCIE Er */ -+#define MV_5181_A1_REV 0x1 /* for USB Er ..*/ -+#define MV_5181_B0_REV 0x2 -+#define MV_5181_B1_REV 0x3 -+#define MV_5182_A1_REV 0x1 -+#define MV_5180N_B1_REV 0x3 -+#define MV_5181L_A0_ID ((MV_5181_DEV_ID << 16) | MV_5181L_A0_REV) -+ -+ -+ -+/* kw */ -+#define MV_6281_DEV_ID 0x6281 -+#define MV_6192_DEV_ID 0x6192 -+#define MV_6190_DEV_ID 0x6190 -+#define MV_6180_DEV_ID 0x6180 -+ -+#define MV_6281_A0_REV 0x2 -+#define MV_6281_A0_ID ((MV_6281_DEV_ID << 16) | MV_6281_A0_REV) -+#define MV_6281_A0_NAME "88F6281 A0" -+ -+#define MV_6192_A0_REV 0x2 -+#define MV_6192_A0_ID ((MV_6192_DEV_ID << 16) | MV_6192_A0_REV) -+#define MV_6192_A0_NAME "88F6192 A0" -+ -+#define MV_6190_A0_REV 0x2 -+#define MV_6190_A0_ID ((MV_6190_DEV_ID << 16) | MV_6190_A0_REV) -+#define MV_6190_A0_NAME "88F6190 A0" -+ -+#define MV_6180_A0_REV 0x2 -+#define MV_6180_A0_ID ((MV_6180_DEV_ID << 16) | MV_6180_A0_REV) -+#define MV_6180_A0_NAME "88F6180 A0" -+ -+#define MV_6281_A1_REV 0x3 -+#define MV_6281_A1_ID ((MV_6281_DEV_ID << 16) | MV_6281_A1_REV) -+#define MV_6281_A1_NAME "88F6281 A1" -+ -+#define MV_6192_A1_REV 0x3 -+#define MV_6192_A1_ID ((MV_6192_DEV_ID << 16) | MV_6192_A1_REV) -+#define MV_6192_A1_NAME "88F6192 A1" -+ -+#define MV_6190_A1_REV 0x3 -+#define MV_6190_A1_ID ((MV_6190_DEV_ID << 16) | MV_6190_A1_REV) -+#define MV_6190_A1_NAME "88F6190 A1" -+ -+#define MV_6180_A1_REV 0x3 -+#define MV_6180_A1_ID ((MV_6180_DEV_ID << 16) | MV_6180_A1_REV) -+#define MV_6180_A1_NAME "88F6180 A1" -+ -+#define MV_88F6XXX_A0_REV 0x2 -+#define MV_88F6XXX_A1_REV 0x3 -+/* Disco-Duo */ -+#define MV_78XX0_ZY_DEV_ID 0x6381 -+#define MV_78XX0_ZY_NAME "MV78X00" -+ -+#define MV_78XX0_Z0_REV 0x1 -+#define MV_78XX0_Z0_ID ((MV_78XX0_ZY_DEV_ID << 16) | MV_78XX0_Z0_REV) -+#define MV_78XX0_Z0_NAME "78X00 Z0" -+ -+#define MV_78XX0_Y0_REV 0x2 -+#define MV_78XX0_Y0_ID ((MV_78XX0_ZY_DEV_ID << 16) | MV_78XX0_Y0_REV) -+#define MV_78XX0_Y0_NAME "78X00 Y0" -+ -+#define MV_78XX0_DEV_ID 0x7800 -+#define MV_78XX0_NAME "MV78X00" -+ -+#define MV_76100_DEV_ID 0x7610 -+#define MV_78200_DEV_ID 0x7820 -+#define MV_78100_DEV_ID 0x7810 -+#define MV_78XX0_A0_REV 0x1 -+#define MV_78XX0_A1_REV 0x2 -+ -+#define MV_76100_NAME "MV76100" -+#define MV_78100_NAME "MV78100" -+#define MV_78200_NAME "MV78200" -+ -+#define MV_76100_A0_ID ((MV_76100_DEV_ID << 16) | MV_78XX0_A0_REV) -+#define MV_78100_A0_ID ((MV_78100_DEV_ID << 16) | MV_78XX0_A0_REV) -+#define MV_78200_A0_ID ((MV_78200_DEV_ID << 16) | MV_78XX0_A0_REV) -+ -+#define MV_76100_A1_ID ((MV_76100_DEV_ID << 16) | MV_78XX0_A1_REV) -+#define MV_78100_A1_ID ((MV_78100_DEV_ID << 16) | MV_78XX0_A1_REV) -+#define MV_78200_A1_ID ((MV_78200_DEV_ID << 16) | MV_78XX0_A1_REV) -+ -+#define MV_76100_A0_NAME "MV76100 A0" -+#define MV_78100_A0_NAME "MV78100 A0" -+#define MV_78200_A0_NAME "MV78200 A0" -+#define MV_78XX0_A0_NAME "MV78XX0 A0" -+ -+#define MV_76100_A1_NAME "MV76100 A1" -+#define MV_78100_A1_NAME "MV78100 A1" -+#define MV_78200_A1_NAME "MV78200 A1" -+#define MV_78XX0_A1_NAME "MV78XX0 A1" -+ -+/*MV88F632X family*/ -+#define MV_6321_DEV_ID 0x6321 -+#define MV_6322_DEV_ID 0x6322 -+#define MV_6323_DEV_ID 0x6323 -+ -+#define MV_6321_NAME "88F6321" -+#define MV_6322_NAME "88F6322" -+#define MV_6323_NAME "88F6323" -+ -+#define MV_632X_A1_REV 0x2 -+ -+#define MV_6321_A1_ID ((MV_6321_DEV_ID << 16) | MV_632X_A1_REV) -+#define MV_6322_A1_ID ((MV_6322_DEV_ID << 16) | MV_632X_A1_REV) -+#define MV_6323_A1_ID ((MV_6323_DEV_ID << 16) | MV_632X_A1_REV) -+ -+#define MV_6321_A1_NAME "88F6321 A1" -+#define MV_6322_A1_NAME "88F6322 A1" -+#define MV_6323_A1_NAME "88F6323 A1" -+ -+ -+#endif /* __INCmvDeviceIdh */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/common/mvHalVer.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/common/mvHalVer.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/common/mvHalVer.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/common/mvHalVer.h 2010-11-09 20:28:07.069296580 +0100 -@@ -0,0 +1,73 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvHalVerh -+#define __INCmvHalVerh -+ -+/* Defines */ -+#define MV_HAL_VERSION "FEROCEON_HAL_3_1_7" -+#define MV_RELEASE_BASELINE "SoCandControllers_FEROCEON_RELEASE_7_9_2009_KW_4_3_4_DD_2_1_4_6183_1_1_4" -+ -+#endif /* __INCmvHalVerh */ -\ No newline at end of file -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/common/mvStack.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/common/mvStack.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/common/mvStack.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/common/mvStack.c 2010-11-09 20:28:07.102606889 +0100 -@@ -0,0 +1,100 @@ -+/******************************************************************************* -+* Copyright 2003, Marvell Semiconductor Israel LTD. * -+* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL. * -+* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT * -+* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE * -+* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL. * -+* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED, * -+* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE. * -+* * -+* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, * -+* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL * -+* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K. * -+* (MJKK), MARVELL SEMICONDUCTOR ISRAEL LTD (MSIL). * -+******************************************************************************** -+* mvQueue.c -+* -+* FILENAME: $Workfile: mvStack.c $ -+* REVISION: $Revision: 1.1 $ -+* LAST UPDATE: $Modtime: $ -+* -+* DESCRIPTION: -+* This file implements simple Stack LIFO functionality. -+*******************************************************************************/ -+ -+/* includes */ -+#include "mvOs.h" -+#include "mvTypes.h" -+#include "mvDebug.h" -+#include "mvStack.h" -+ -+/* defines */ -+ -+ -+/* Public functions */ -+ -+ -+/* Purpose: Create new stack -+ * Inputs: -+ * - MV_U32 noOfElements - maximum number of elements in the stack. -+ * Each element 4 bytes size -+ * Return: void* - pointer to created stack. -+ */ -+void* mvStackCreate(int numOfElements) -+{ -+ MV_STACK* pStack; -+ MV_U32* pStackElements; -+ -+ pStack = (MV_STACK*)mvOsMalloc(sizeof(MV_STACK)); -+ pStackElements = (MV_U32*)mvOsMalloc(numOfElements*sizeof(MV_U32)); -+ if( (pStack == NULL) || (pStackElements == NULL) ) -+ { -+ mvOsPrintf("mvStack: Can't create new stack\n"); -+ return NULL; -+ } -+ memset(pStackElements, 0, numOfElements*sizeof(MV_U32)); -+ pStack->numOfElements = numOfElements; -+ pStack->stackIdx = 0; -+ pStack->stackElements = pStackElements; -+ -+ return pStack; -+} -+ -+/* Purpose: Delete existing stack -+ * Inputs: -+ * - void* stackHndl - Stack handle as returned by "mvStackCreate()" function -+ * -+ * Return: MV_STATUS MV_NOT_FOUND - Failure. StackHandle is not valid. -+ * MV_OK - Success. -+ */ -+MV_STATUS mvStackDelete(void* stackHndl) -+{ -+ MV_STACK* pStack = (MV_STACK*)stackHndl; -+ -+ if( (pStack == NULL) || (pStack->stackElements == NULL) ) -+ return MV_NOT_FOUND; -+ -+ mvOsFree(pStack->stackElements); -+ mvOsFree(pStack); -+ -+ return MV_OK; -+} -+ -+ -+/* PrintOut status of the stack */ -+void mvStackStatus(void* stackHndl, MV_BOOL isPrintElements) -+{ -+ int i; -+ MV_STACK* pStack = (MV_STACK*)stackHndl; -+ -+ mvOsPrintf("StackHandle=%p, pElements=%p, numElements=%d, stackIdx=%d\n", -+ stackHndl, pStack->stackElements, pStack->numOfElements, -+ pStack->stackIdx); -+ if(isPrintElements == MV_TRUE) -+ { -+ for(i=0; istackIdx; i++) -+ { -+ mvOsPrintf("%3d. Value=0x%x\n", i, pStack->stackElements[i]); -+ } -+ } -+} -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/common/mvStack.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/common/mvStack.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/common/mvStack.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/common/mvStack.h 2010-11-09 20:28:07.160842220 +0100 -@@ -0,0 +1,140 @@ -+/******************************************************************************* -+* Copyright 2003, Marvell Semiconductor Israel LTD. * -+* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL. * -+* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT * -+* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE * -+* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL. * -+* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED, * -+* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE. * -+* * -+* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, * -+* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL * -+* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K. * -+* (MJKK), MARVELL SEMICONDUCTOR ISRAEL LTD (MSIL). * -+******************************************************************************** -+* mvStack.h - Header File for : -+* -+* FILENAME: $Workfile: mvStack.h $ -+* REVISION: $Revision: 1.1 $ -+* LAST UPDATE: $Modtime: $ -+* -+* DESCRIPTION: -+* This file defines simple Stack (LIFO) functionality. -+* -+*******************************************************************************/ -+ -+#ifndef __mvStack_h__ -+#define __mvStack_h__ -+ -+ -+/* includes */ -+#include "mvTypes.h" -+ -+ -+/* defines */ -+ -+ -+/* typedefs */ -+/* Data structure describes general purpose Stack */ -+typedef struct -+{ -+ int stackIdx; -+ int numOfElements; -+ MV_U32* stackElements; -+} MV_STACK; -+ -+static INLINE MV_BOOL mvStackIsFull(void* stackHndl) -+{ -+ MV_STACK* pStack = (MV_STACK*)stackHndl; -+ -+ if(pStack->stackIdx == pStack->numOfElements) -+ return MV_TRUE; -+ -+ return MV_FALSE; -+} -+ -+static INLINE MV_BOOL mvStackIsEmpty(void* stackHndl) -+{ -+ MV_STACK* pStack = (MV_STACK*)stackHndl; -+ -+ if(pStack->stackIdx == 0) -+ return MV_TRUE; -+ -+ return MV_FALSE; -+} -+/* Purpose: Push new element to stack -+ * Inputs: -+ * - void* stackHndl - Stack handle as returned by "mvStackCreate()" function. -+ * - MV_U32 value - New element. -+ * -+ * Return: MV_STATUS MV_FULL - Failure. Stack is full. -+ * MV_OK - Success. Element is put to stack. -+ */ -+static INLINE void mvStackPush(void* stackHndl, MV_U32 value) -+{ -+ MV_STACK* pStack = (MV_STACK*)stackHndl; -+ -+#ifdef MV_RT_DEBUG -+ if(pStack->stackIdx == pStack->numOfElements) -+ { -+ mvOsPrintf("mvStackPush: Stack is FULL\n"); -+ return; -+ } -+#endif /* MV_RT_DEBUG */ -+ -+ pStack->stackElements[pStack->stackIdx] = value; -+ pStack->stackIdx++; -+} -+ -+/* Purpose: Pop element from the top of stack and copy it to "pValue" -+ * Inputs: -+ * - void* stackHndl - Stack handle as returned by "mvStackCreate()" function. -+ * - MV_U32 value - Element in the top of stack. -+ * -+ * Return: MV_STATUS MV_EMPTY - Failure. Stack is empty. -+ * MV_OK - Success. Element is removed from the stack and -+ * copied to pValue argument -+ */ -+static INLINE MV_U32 mvStackPop(void* stackHndl) -+{ -+ MV_STACK* pStack = (MV_STACK*)stackHndl; -+ -+#ifdef MV_RT_DEBUG -+ if(pStack->stackIdx == 0) -+ { -+ mvOsPrintf("mvStackPop: Stack is EMPTY\n"); -+ return 0; -+ } -+#endif /* MV_RT_DEBUG */ -+ -+ pStack->stackIdx--; -+ return pStack->stackElements[pStack->stackIdx]; -+} -+ -+static INLINE int mvStackIndex(void* stackHndl) -+{ -+ MV_STACK* pStack = (MV_STACK*)stackHndl; -+ -+ return pStack->stackIdx; -+} -+ -+static INLINE int mvStackFreeElements(void* stackHndl) -+{ -+ MV_STACK* pStack = (MV_STACK*)stackHndl; -+ -+ return (pStack->numOfElements - pStack->stackIdx); -+} -+ -+/* mvStack.h API list */ -+ -+/* Create new Stack */ -+void* mvStackCreate(int numOfElements); -+ -+/* Delete existing stack */ -+MV_STATUS mvStackDelete(void* stackHndl); -+ -+/* Print status of the stack */ -+void mvStackStatus(void* stackHndl, MV_BOOL isPrintElements); -+ -+#endif /* __mvStack_h__ */ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/common/mvTypes.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/common/mvTypes.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/common/mvTypes.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/common/mvTypes.h 2010-11-09 20:28:07.191385803 +0100 -@@ -0,0 +1,245 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvTypesh -+#define __INCmvTypesh -+ -+/* Defines */ -+ -+/* The following is a list of Marvell status */ -+#define MV_ERROR (-1) -+#define MV_OK (0x00) /* Operation succeeded */ -+#define MV_FAIL (0x01) /* Operation failed */ -+#define MV_BAD_VALUE (0x02) /* Illegal value (general) */ -+#define MV_OUT_OF_RANGE (0x03) /* The value is out of range */ -+#define MV_BAD_PARAM (0x04) /* Illegal parameter in function called */ -+#define MV_BAD_PTR (0x05) /* Illegal pointer value */ -+#define MV_BAD_SIZE (0x06) /* Illegal size */ -+#define MV_BAD_STATE (0x07) /* Illegal state of state machine */ -+#define MV_SET_ERROR (0x08) /* Set operation failed */ -+#define MV_GET_ERROR (0x09) /* Get operation failed */ -+#define MV_CREATE_ERROR (0x0A) /* Fail while creating an item */ -+#define MV_NOT_FOUND (0x0B) /* Item not found */ -+#define MV_NO_MORE (0x0C) /* No more items found */ -+#define MV_NO_SUCH (0x0D) /* No such item */ -+#define MV_TIMEOUT (0x0E) /* Time Out */ -+#define MV_NO_CHANGE (0x0F) /* Parameter(s) is already in this value */ -+#define MV_NOT_SUPPORTED (0x10) /* This request is not support */ -+#define MV_NOT_IMPLEMENTED (0x11) /* Request supported but not implemented */ -+#define MV_NOT_INITIALIZED (0x12) /* The item is not initialized */ -+#define MV_NO_RESOURCE (0x13) /* Resource not available (memory ...) */ -+#define MV_FULL (0x14) /* Item is full (Queue or table etc...) */ -+#define MV_EMPTY (0x15) /* Item is empty (Queue or table etc...) */ -+#define MV_INIT_ERROR (0x16) /* Error occured while INIT process */ -+#define MV_HW_ERROR (0x17) /* Hardware error */ -+#define MV_TX_ERROR (0x18) /* Transmit operation not succeeded */ -+#define MV_RX_ERROR (0x19) /* Recieve operation not succeeded */ -+#define MV_NOT_READY (0x1A) /* The other side is not ready yet */ -+#define MV_ALREADY_EXIST (0x1B) /* Tried to create existing item */ -+#define MV_OUT_OF_CPU_MEM (0x1C) /* Cpu memory allocation failed. */ -+#define MV_NOT_STARTED (0x1D) /* Not started yet */ -+#define MV_BUSY (0x1E) /* Item is busy. */ -+#define MV_TERMINATE (0x1F) /* Item terminates it's work. */ -+#define MV_NOT_ALIGNED (0x20) /* Wrong alignment */ -+#define MV_NOT_ALLOWED (0x21) /* Operation NOT allowed */ -+#define MV_WRITE_PROTECT (0x22) /* Write protected */ -+ -+ -+#define MV_INVALID (int)(-1) -+ -+#define MV_FALSE 0 -+#define MV_TRUE (!(MV_FALSE)) -+ -+ -+#ifndef NULL -+#define NULL ((void*)0) -+#endif -+ -+ -+#ifndef MV_ASMLANGUAGE -+/* typedefs */ -+ -+typedef char MV_8; -+typedef unsigned char MV_U8; -+ -+typedef int MV_32; -+typedef unsigned int MV_U32; -+ -+typedef short MV_16; -+typedef unsigned short MV_U16; -+ -+#ifdef MV_PPC64 -+typedef long MV_64; -+typedef unsigned long MV_U64; -+#else -+typedef long long MV_64; -+typedef unsigned long long MV_U64; -+#endif -+ -+typedef long MV_LONG; /* 32/64 */ -+typedef unsigned long MV_ULONG; /* 32/64 */ -+ -+typedef int MV_STATUS; -+typedef int MV_BOOL; -+typedef void MV_VOID; -+typedef float MV_FLOAT; -+ -+typedef int (*MV_FUNCPTR) (void); /* ptr to function returning int */ -+typedef void (*MV_VOIDFUNCPTR) (void); /* ptr to function returning void */ -+typedef double (*MV_DBLFUNCPTR) (void); /* ptr to function returning double*/ -+typedef float (*MV_FLTFUNCPTR) (void); /* ptr to function returning float */ -+ -+typedef MV_U32 MV_KHZ; -+typedef MV_U32 MV_MHZ; -+typedef MV_U32 MV_HZ; -+ -+ -+/* This enumerator describes the set of commands that can be applied on */ -+/* an engine (e.g. IDMA, XOR). Appling a comman depends on the current */ -+/* status (see MV_STATE enumerator) */ -+/* Start can be applied only when status is IDLE */ -+/* Stop can be applied only when status is IDLE, ACTIVE or PAUSED */ -+/* Pause can be applied only when status is ACTIVE */ -+/* Restart can be applied only when status is PAUSED */ -+typedef enum _mvCommand -+{ -+ MV_START, /* Start */ -+ MV_STOP, /* Stop */ -+ MV_PAUSE, /* Pause */ -+ MV_RESTART /* Restart */ -+} MV_COMMAND; -+ -+/* This enumerator describes the set of state conditions. */ -+/* Moving from one state to other is stricted. */ -+typedef enum _mvState -+{ -+ MV_IDLE, -+ MV_ACTIVE, -+ MV_PAUSED, -+ MV_UNDEFINED_STATE -+} MV_STATE; -+ -+ -+/* This structure describes address space window. Window base can be */ -+/* 64 bit, window size up to 4GB */ -+typedef struct _mvAddrWin -+{ -+ MV_U32 baseLow; /* 32bit base low */ -+ MV_U32 baseHigh; /* 32bit base high */ -+ MV_U32 size; /* 32bit size */ -+}MV_ADDR_WIN; -+ -+/* This binary enumerator describes protection attribute status */ -+typedef enum _mvProtRight -+{ -+ ALLOWED, /* Protection attribute allowed */ -+ FORBIDDEN /* Protection attribute forbidden */ -+}MV_PROT_RIGHT; -+ -+/* Unified struct for Rx and Tx packet operations. The user is required to */ -+/* be familier only with Tx/Rx descriptor command status. */ -+typedef struct _bufInfo -+{ -+ MV_U32 cmdSts; /* Tx/Rx command status */ -+ MV_U16 byteCnt; /* Size of valid data in the buffer */ -+ MV_U16 bufSize; /* Total size of the buffer */ -+ MV_U8 *pBuff; /* Pointer to Buffer */ -+ MV_U8 *pData; /* Pointer to data in the Buffer */ -+ MV_U32 userInfo1; /* Tx/Rx attached user information 1 */ -+ MV_U32 userInfo2; /* Tx/Rx attached user information 2 */ -+ struct _bufInfo *pNextBufInfo; /* Next buffer in packet */ -+} BUF_INFO; -+ -+/* This structure contains information describing one of buffers -+ * (fragments) they are built Ethernet packet. -+ */ -+typedef struct -+{ -+ MV_U8* bufVirtPtr; -+ MV_ULONG bufPhysAddr; -+ MV_U32 bufSize; -+ MV_U32 dataSize; -+ MV_U32 memHandle; -+ MV_32 bufAddrShift; -+} MV_BUF_INFO; -+ -+/* This structure contains information describing Ethernet packet. -+ * The packet can be divided for few buffers (fragments) -+ */ -+typedef struct -+{ -+ MV_ULONG osInfo; -+ MV_BUF_INFO *pFrags; -+ MV_U32 status; -+ MV_U16 pktSize; -+ MV_U16 numFrags; -+ MV_U32 ownerId; -+ MV_U32 fragIP; -+} MV_PKT_INFO; -+ -+#endif /* MV_ASMLANGUAGE */ -+ -+#endif /* __INCmvTypesh */ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/dbg-trace.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/dbg-trace.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/dbg-trace.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/dbg-trace.c 2010-11-09 20:28:07.232495685 +0100 -@@ -0,0 +1,110 @@ -+#include -+#include -+#include -+#include "dbg-trace.h" -+ -+#define TRACE_ARR_LEN 800 -+#define STR_LEN 128 -+struct trace { -+ struct timeval tv; -+ char str[STR_LEN]; -+ unsigned int callback_val1; -+ unsigned int callback_val2; -+ char valid; -+}; -+static unsigned int (*trc_callback1) (unsigned char) = NULL; -+static unsigned int (*trc_callback2) (unsigned char) = NULL; -+static unsigned char trc_param1 = 0; -+static unsigned char trc_param2 = 0; -+struct trace *trc_arr; -+static int trc_index; -+static int trc_active = 0; -+ -+void TRC_START() -+{ -+ trc_active = 1; -+} -+ -+void TRC_STOP() -+{ -+ trc_active = 0; -+} -+ -+void TRC_INIT(void *callback1, void *callback2, unsigned char callback1_param, unsigned char callback2_param) -+{ -+ printk("Marvell debug tracing is on\n"); -+ trc_arr = (struct trace *)kmalloc(TRACE_ARR_LEN*sizeof(struct trace),GFP_KERNEL); -+ if(trc_arr == NULL) -+ { -+ printk("Can't allocate Debug Trace buffer\n"); -+ return; -+ } -+ memset(trc_arr,0,TRACE_ARR_LEN*sizeof(struct trace)); -+ trc_index = 0; -+ trc_callback1 = callback1; -+ trc_callback2 = callback2; -+ trc_param1 = callback1_param; -+ trc_param2 = callback2_param; -+} -+void TRC_REC(char *fmt,...) -+{ -+ va_list args; -+ struct trace *trc = &trc_arr[trc_index]; -+ -+ if(trc_active == 0) -+ return; -+ -+ do_gettimeofday(&trc->tv); -+ if(trc_callback1) -+ trc->callback_val1 = trc_callback1(trc_param1); -+ if(trc_callback2) -+ trc->callback_val2 = trc_callback2(trc_param2); -+ va_start(args, fmt); -+ vsprintf(trc->str,fmt,args); -+ va_end(args); -+ trc->valid = 1; -+ if((++trc_index) == TRACE_ARR_LEN) { -+ trc_index = 0; -+ } -+} -+void TRC_OUTPUT(void) -+{ -+ int i,j; -+ struct trace *p; -+ printk("\n\nTrace %d items\n",TRACE_ARR_LEN); -+ for(i=0,j=trc_index; ivalid) { -+ unsigned long uoffs; -+ struct trace *plast; -+ if(p == &trc_arr[0]) -+ plast = &trc_arr[TRACE_ARR_LEN-1]; -+ else -+ plast = p-1; -+ if(p->tv.tv_sec == ((plast)->tv.tv_sec)) -+ uoffs = (p->tv.tv_usec - ((plast)->tv.tv_usec)); -+ else -+ uoffs = (1000000 - ((plast)->tv.tv_usec)) + -+ ((p->tv.tv_sec - ((plast)->tv.tv_sec) - 1) * 1000000) + -+ p->tv.tv_usec; -+ printk("%03d: [+%ld usec]", j, (unsigned long)uoffs); -+ if(trc_callback1) -+ printk("[%u]",p->callback_val1); -+ if(trc_callback2) -+ printk("[%u]",p->callback_val2); -+ printk(": %s",p->str); -+ } -+ p->valid = 0; -+ } -+ memset(trc_arr,0,TRACE_ARR_LEN*sizeof(struct trace)); -+ trc_index = 0; -+} -+void TRC_RELEASE(void) -+{ -+ kfree(trc_arr); -+ trc_index = 0; -+} -+ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/dbg-trace.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/dbg-trace.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/dbg-trace.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/dbg-trace.h 2010-11-09 20:28:07.276291416 +0100 -@@ -0,0 +1,24 @@ -+ -+#ifndef _MV_DBG_TRCE_H_ -+#define _MV_DBG_TRCE_H_ -+ -+#ifdef CONFIG_MV_DBG_TRACE -+void TRC_INIT(void *callback1, void *callback2, -+ unsigned char callback1_param, unsigned char callback2_param); -+void TRC_REC(char *fmt,...); -+void TRC_OUTPUT(void); -+void TRC_RELEASE(void); -+void TRC_START(void); -+void TRC_STOP(void); -+ -+#else -+#define TRC_INIT(x1,x2,x3,x4) -+#define TRC_REC(X...) -+#define TRC_OUTPUT() -+#define TRC_RELEASE() -+#define TRC_START() -+#define TRC_STOP() -+#endif -+ -+ -+#endif -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c 2010-11-09 20:28:07.327371127 +0100 -@@ -0,0 +1,2513 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "boardEnv/mvBoardEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+#include "cpu/mvCpu.h" -+#include "cntmr/mvCntmr.h" -+#include "gpp/mvGpp.h" -+#include "twsi/mvTwsi.h" -+#include "pex/mvPex.h" -+#include "device/mvDevice.h" -+#include "eth/gbe/mvEthRegs.h" -+ -+/* defines */ -+/* #define MV_DEBUG */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+extern MV_CPU_ARM_CLK _cpuARMDDRCLK[]; -+ -+#define CODE_IN_ROM MV_FALSE -+#define CODE_IN_RAM MV_TRUE -+ -+extern MV_BOARD_INFO* boardInfoTbl[]; -+#define BOARD_INFO(boardId) boardInfoTbl[boardId - BOARD_ID_BASE] -+ -+/* Locals */ -+static MV_DEV_CS_INFO* boardGetDevEntry(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); -+ -+MV_U32 tClkRate = -1; -+ -+ -+/******************************************************************************* -+* mvBoardEnvInit - Init board -+* -+* DESCRIPTION: -+* In this function the board environment take care of device bank -+* initialization. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvBoardEnvInit(MV_VOID) -+{ -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardEnvInit:Board unknown.\n"); -+ return; -+ -+ } -+ -+ /* Set GPP Out value */ -+ MV_REG_WRITE(GPP_DATA_OUT_REG(0), BOARD_INFO(boardId)->gppOutValLow); -+ MV_REG_WRITE(GPP_DATA_OUT_REG(1), BOARD_INFO(boardId)->gppOutValHigh); -+ -+ /* set GPP polarity */ -+ mvGppPolaritySet(0, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValLow); -+ mvGppPolaritySet(1, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValHigh); -+ -+ /* Workaround for Erratum FE-MISC-70*/ -+ if(mvCtrlRevGet()==MV_88F6XXX_A0_REV) -+ { -+ BOARD_INFO(boardId)->gppOutEnValLow &= 0xfffffffd; -+ BOARD_INFO(boardId)->gppOutEnValLow |= (BOARD_INFO(boardId)->gppOutEnValHigh) & 0x00000002; -+ } /*End of WA*/ -+ -+ /* Set GPP Out Enable*/ -+ mvGppTypeSet(0, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValLow); -+ mvGppTypeSet(1, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValHigh); -+ -+ /* Nand CE */ -+ MV_REG_BIT_SET(NAND_CTRL_REG, NAND_ACTCEBOOT_BIT); -+} -+ -+/******************************************************************************* -+* mvBoardModelGet - Get Board model -+* -+* DESCRIPTION: -+* This function returns 16bit describing board model. -+* Board model is constructed of one byte major and minor numbers in the -+* following manner: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* String describing board model. -+* -+*******************************************************************************/ -+MV_U16 mvBoardModelGet(MV_VOID) -+{ -+ return (mvBoardIdGet() >> 16); -+} -+ -+/******************************************************************************* -+* mbBoardRevlGet - Get Board revision -+* -+* DESCRIPTION: -+* This function returns a 32bit describing the board revision. -+* Board revision is constructed of 4bytes. 2bytes describes major number -+* and the other 2bytes describes minor munber. -+* For example for board revision 3.4 the function will return -+* 0x00030004. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* String describing board model. -+* -+*******************************************************************************/ -+MV_U16 mvBoardRevGet(MV_VOID) -+{ -+ return (mvBoardIdGet() & 0xFFFF); -+} -+ -+/******************************************************************************* -+* mvBoardNameGet - Get Board name -+* -+* DESCRIPTION: -+* This function returns a string describing the board model and revision. -+* String is extracted from board I2C EEPROM. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* pNameBuff - Buffer to contain board name string. Minimum size 32 chars. -+* -+* RETURN: -+* -+* MV_ERROR if informantion can not be read. -+*******************************************************************************/ -+MV_STATUS mvBoardNameGet(char *pNameBuff) -+{ -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsSPrintf (pNameBuff, "Board unknown.\n"); -+ return MV_ERROR; -+ -+ } -+ -+ mvOsSPrintf (pNameBuff, "%s",BOARD_INFO(boardId)->boardName); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvBoardIsPortInSgmii - -+* -+* DESCRIPTION: -+* This routine returns MV_TRUE for port number works in SGMII or MV_FALSE -+* For all other options. -+* -+* INPUT: -+* ethPortNum - Ethernet port number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE - port in SGMII. -+* MV_FALSE - other. -+* -+*******************************************************************************/ -+MV_BOOL mvBoardIsPortInSgmii(MV_U32 ethPortNum) -+{ -+ MV_BOOL ethPortSgmiiSupport[BOARD_ETH_PORT_NUM] = MV_ETH_PORT_SGMII; -+ -+ if(ethPortNum >= BOARD_ETH_PORT_NUM) -+ { -+ mvOsPrintf ("Invalid portNo=%d\n", ethPortNum); -+ return MV_FALSE; -+ } -+ return ethPortSgmiiSupport[ethPortNum]; -+} -+ -+/******************************************************************************* -+* mvBoardIsPortInGmii - -+* -+* DESCRIPTION: -+* This routine returns MV_TRUE for port number works in GMII or MV_FALSE -+* For all other options. -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE - port in GMII. -+* MV_FALSE - other. -+* -+*******************************************************************************/ -+MV_BOOL mvBoardIsPortInGmii(MV_VOID) -+{ -+ MV_U32 devClassId, devClass = 0; -+ if (mvBoardMppGroupTypeGet(devClass) == MV_BOARD_AUTO) -+ { -+ /* Get MPP module ID */ -+ devClassId = mvBoarModuleTypeGet(devClass); -+ if (MV_BOARD_MODULE_GMII_ID == devClassId) -+ return MV_TRUE; -+ } -+ else if (mvBoardMppGroupTypeGet(devClass) == MV_BOARD_GMII) -+ return MV_TRUE; -+ -+ return MV_FALSE; -+} -+/******************************************************************************* -+* mvBoardPhyAddrGet - Get the phy address -+* -+* DESCRIPTION: -+* This routine returns the Phy address of a given ethernet port. -+* -+* INPUT: -+* ethPortNum - Ethernet port number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit describing Phy address, -1 if the port number is wrong. -+* -+*******************************************************************************/ -+MV_32 mvBoardPhyAddrGet(MV_U32 ethPortNum) -+{ -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardPhyAddrGet: Board unknown.\n"); -+ return MV_ERROR; -+ } -+ -+ return BOARD_INFO(boardId)->pBoardMacInfo[ethPortNum].boardEthSmiAddr; -+} -+ -+/******************************************************************************* -+* mvBoardMacSpeedGet - Get the Mac speed -+* -+* DESCRIPTION: -+* This routine returns the Mac speed if pre define of a given ethernet port. -+* -+* INPUT: -+* ethPortNum - Ethernet port number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BOARD_MAC_SPEED, -1 if the port number is wrong. -+* -+*******************************************************************************/ -+MV_BOARD_MAC_SPEED mvBoardMacSpeedGet(MV_U32 ethPortNum) -+{ -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardMacSpeedGet: Board unknown.\n"); -+ return MV_ERROR; -+ } -+ -+ return BOARD_INFO(boardId)->pBoardMacInfo[ethPortNum].boardMacSpeed; -+} -+ -+/******************************************************************************* -+* mvBoardLinkStatusIrqGet - Get the IRQ number for the link status indication -+* -+* DESCRIPTION: -+* This routine returns the IRQ number for the link status indication. -+* -+* INPUT: -+* ethPortNum - Ethernet port number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* the number of the IRQ for the link status indication, -1 if the port -+* number is wrong or if not relevant. -+* -+*******************************************************************************/ -+MV_32 mvBoardLinkStatusIrqGet(MV_U32 ethPortNum) -+{ -+ MV_U32 boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardLinkStatusIrqGet: Board unknown.\n"); -+ return MV_ERROR; -+ } -+ -+ return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].linkStatusIrq; -+} -+ -+/******************************************************************************* -+* mvBoardSwitchPortGet - Get the mapping between the board connector and the -+* Ethernet Switch port -+* -+* DESCRIPTION: -+* This routine returns the matching Switch port. -+* -+* INPUT: -+* ethPortNum - Ethernet port number. -+* boardPortNum - logical number of the connector on the board -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* the matching Switch port, -1 if the port number is wrong or if not relevant. -+* -+*******************************************************************************/ -+MV_32 mvBoardSwitchPortGet(MV_U32 ethPortNum, MV_U8 boardPortNum) -+{ -+ MV_U32 boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardSwitchPortGet: Board unknown.\n"); -+ return MV_ERROR; -+ } -+ if (boardPortNum >= BOARD_ETH_SWITCH_PORT_NUM) -+ { -+ mvOsPrintf("mvBoardSwitchPortGet: Illegal board port number.\n"); -+ return MV_ERROR; -+ } -+ -+ return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].qdPort[boardPortNum]; -+} -+ -+/******************************************************************************* -+* mvBoardSwitchCpuPortGet - Get the the Ethernet Switch CPU port -+* -+* DESCRIPTION: -+* This routine returns the Switch CPU port. -+* -+* INPUT: -+* ethPortNum - Ethernet port number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* the Switch CPU port, -1 if the port number is wrong or if not relevant. -+* -+*******************************************************************************/ -+MV_32 mvBoardSwitchCpuPortGet(MV_U32 ethPortNum) -+{ -+ MV_U32 boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardSwitchCpuPortGet: Board unknown.\n"); -+ return MV_ERROR; -+ } -+ -+ return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].qdCpuPort; -+} -+ -+/******************************************************************************* -+* mvBoardIsSwitchConnected - Get switch connection status -+* DESCRIPTION: -+* This routine returns port's connection status -+* -+* INPUT: -+* ethPortNum - Ethernet port number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 1 - if ethPortNum is connected to switch, 0 otherwise -+* -+*******************************************************************************/ -+MV_32 mvBoardIsSwitchConnected(MV_U32 ethPortNum) -+{ -+ MV_U32 boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardIsSwitchConnected: Board unknown.\n"); -+ return MV_ERROR; -+ } -+ -+ if(ethPortNum >= BOARD_INFO(boardId)->numBoardMacInfo) -+ { -+ mvOsPrintf("mvBoardIsSwitchConnected: Illegal port number(%u)\n", ethPortNum); -+ return MV_ERROR; -+ } -+ -+ if((MV_32)(BOARD_INFO(boardId)->pSwitchInfo)) -+ return (MV_32)(BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].switchOnPort == ethPortNum); -+ else -+ return 0; -+} -+/******************************************************************************* -+* mvBoardSmiScanModeGet - Get Switch SMI scan mode -+* -+* DESCRIPTION: -+* This routine returns Switch SMI scan mode. -+* -+* INPUT: -+* ethPortNum - Ethernet port number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 1 for SMI_MANUAL_MODE, -1 if the port number is wrong or if not relevant. -+* -+*******************************************************************************/ -+MV_32 mvBoardSmiScanModeGet(MV_U32 ethPortNum) -+{ -+ MV_U32 boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardSmiScanModeGet: Board unknown.\n"); -+ return MV_ERROR; -+ } -+ -+ return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].smiScanMode; -+} -+/******************************************************************************* -+* mvBoardSpecInitGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: Return MV_TRUE and parameters in case board need spesific phy init, -+* otherwise return MV_FALSE. -+* -+* -+*******************************************************************************/ -+ -+MV_BOOL mvBoardSpecInitGet(MV_U32* regOff, MV_U32* data) -+{ -+ return MV_FALSE; -+} -+ -+/******************************************************************************* -+* mvBoardTclkGet - Get the board Tclk (Controller clock) -+* -+* DESCRIPTION: -+* This routine extract the controller core clock. -+* This function uses the controller counters to make identification. -+* Note: In order to avoid interference, make sure task context switch -+* and interrupts will not occure during this function operation -+* -+* INPUT: -+* countNum - Counter number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit clock cycles in Hertz. -+* -+*******************************************************************************/ -+MV_U32 mvBoardTclkGet(MV_VOID) -+{ -+ if(mvCtrlModelGet()==MV_6281_DEV_ID) -+ { -+#if defined(TCLK_AUTO_DETECT) -+ MV_U32 tmpTClkRate = MV_BOARD_TCLK_166MHZ; -+ -+ tmpTClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ tmpTClkRate &= MSAR_TCLCK_MASK; -+ -+ switch (tmpTClkRate) -+ { -+ case MSAR_TCLCK_166: -+ return MV_BOARD_TCLK_166MHZ; -+ break; -+ case MSAR_TCLCK_200: -+ return MV_BOARD_TCLK_200MHZ; -+ break; -+ } -+#else -+ return MV_BOARD_TCLK_200MHZ; -+#endif -+ } -+ -+ return MV_BOARD_TCLK_166MHZ; -+ -+} -+/******************************************************************************* -+* mvBoardSysClkGet - Get the board SysClk (CPU bus clock) -+* -+* DESCRIPTION: -+* This routine extract the CPU bus clock. -+* -+* INPUT: -+* countNum - Counter number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit clock cycles in Hertz. -+* -+*******************************************************************************/ -+static MV_U32 mvBoard6180SysClkGet(MV_VOID) -+{ -+ MV_U32 sysClkRate=0; -+ MV_CPU_ARM_CLK _cpu6180_ddr_l2_CLK[] = MV_CPU6180_DDR_L2_CLCK_TBL; -+ -+ sysClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ sysClkRate = sysClkRate & MSAR_CPUCLCK_MASK_6180; -+ sysClkRate = sysClkRate >> MSAR_CPUCLCK_OFFS_6180; -+ -+ sysClkRate = _cpu6180_ddr_l2_CLK[sysClkRate].ddrClk; -+ -+ return sysClkRate; -+ -+} -+ -+MV_U32 mvBoardSysClkGet(MV_VOID) -+{ -+#ifdef SYSCLK_AUTO_DETECT -+ MV_U32 sysClkRate, tmp, pClkRate, indexDdrRtio; -+ MV_U32 cpuCLK[] = MV_CPU_CLCK_TBL; -+ MV_U32 ddrRtio[][2] = MV_DDR_CLCK_RTIO_TBL; -+ -+ if(mvCtrlModelGet() == MV_6180_DEV_ID) -+ return mvBoard6180SysClkGet(); -+ -+ tmp = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ pClkRate = MSAR_CPUCLCK_EXTRACT(tmp); -+ pClkRate = cpuCLK[pClkRate]; -+ -+ indexDdrRtio = tmp & MSAR_DDRCLCK_RTIO_MASK; -+ indexDdrRtio = indexDdrRtio >> MSAR_DDRCLCK_RTIO_OFFS; -+ if(ddrRtio[indexDdrRtio][0] != 0) -+ sysClkRate = ((pClkRate * ddrRtio[indexDdrRtio][1]) / ddrRtio[indexDdrRtio][0]); -+ else -+ sysClkRate = 0; -+ return sysClkRate; -+#else -+ return MV_BOARD_DEFAULT_SYSCLK; -+#endif -+} -+ -+ -+/******************************************************************************* -+* mvBoardPexBridgeIntPinGet - Get PEX to PCI bridge interrupt pin number -+* -+* DESCRIPTION: -+* Multi-ported PCI Express bridges that is implemented on the board -+* collapse interrupts across multiple conventional PCI/PCI-X buses. -+* A dual-headed PCI Express bridge would map (or "swizzle") the -+* interrupts per the following table (in accordance with the respective -+* logical PCI/PCI-X bridge's Device Number), collapse the INTA#-INTD# -+* signals from its two logical PCI/PCI-X bridges, collapse the -+* INTA#-INTD# signals from any internal sources, and convert the -+* signals to in-band PCI Express messages. 10 -+* This function returns the upstream interrupt as it was converted by -+* the bridge, according to board configuration and the following table: -+* PCI dev num -+* Interrupt pin 7, 8, 9 -+* A -> A D C -+* B -> B A D -+* C -> C B A -+* D -> D C B -+* -+* -+* INPUT: -+* devNum - PCI/PCIX device number. -+* intPin - PCI Int pin -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Int pin connected to the Interrupt controller -+* -+*******************************************************************************/ -+MV_U32 mvBoardPexBridgeIntPinGet(MV_U32 devNum, MV_U32 intPin) -+{ -+ MV_U32 realIntPin = ((intPin + (3 - (devNum % 4))) %4 ); -+ -+ if (realIntPin == 0) return 4; -+ else return realIntPin; -+ -+} -+ -+/******************************************************************************* -+* mvBoardDebugLedNumGet - Get number of debug Leds -+* -+* DESCRIPTION: -+* INPUT: -+* boardId -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_U32 mvBoardDebugLedNumGet(MV_U32 boardId) -+{ -+ return BOARD_INFO(boardId)->activeLedsNumber; -+} -+ -+/******************************************************************************* -+* mvBoardDebugLeg - Set the board debug Leds -+* -+* DESCRIPTION: turn on/off status leds. -+* Note: assume MPP leds are part of group 0 only. -+* -+* INPUT: -+* hexNum - Number to be displied in hex by Leds. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvBoardDebugLed(MV_U32 hexNum) -+{ -+ MV_U32 val = 0,totalMask, currentBitMask = 1,i; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (BOARD_INFO(boardId)->pLedGppPin == NULL) -+ return; -+ -+ totalMask = (1 << BOARD_INFO(boardId)->activeLedsNumber) -1; -+ hexNum &= totalMask; -+ totalMask = 0; -+ -+ for (i = 0 ; i < BOARD_INFO(boardId)->activeLedsNumber ; i++) -+ { -+ if (hexNum & currentBitMask) -+ { -+ val |= (1 << BOARD_INFO(boardId)->pLedGppPin[i]); -+ } -+ -+ totalMask |= (1 << BOARD_INFO(boardId)->pLedGppPin[i]); -+ -+ currentBitMask = (currentBitMask << 1); -+ } -+ -+ if (BOARD_INFO(boardId)->ledsPolarity) -+ { -+ mvGppValueSet(0, totalMask, val); -+ } -+ else -+ { -+ mvGppValueSet(0, totalMask, ~val); -+ } -+} -+ -+ -+/******************************************************************************* -+* mvBoarGpioPinGet - mvBoarGpioPinGet -+* -+* DESCRIPTION: -+* -+* INPUT: -+* class - MV_BOARD_GPP_CLASS enum. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* GPIO pin number. The function return -1 for bad parameters. -+* -+*******************************************************************************/ -+MV_32 mvBoarGpioPinNumGet(MV_BOARD_GPP_CLASS class, MV_U32 index) -+{ -+ MV_U32 boardId, i; -+ MV_U32 indexFound = 0; -+ -+ boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardRTCGpioPinGet:Board unknown.\n"); -+ return MV_ERROR; -+ -+ } -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardGppInfo; i++) -+ if (BOARD_INFO(boardId)->pBoardGppInfo[i].devClass == class) { -+ if (indexFound == index) -+ return (MV_U32)BOARD_INFO(boardId)->pBoardGppInfo[i].gppPinNum; -+ else -+ indexFound++; -+ -+ } -+ -+ return MV_ERROR; -+} -+ -+ -+/******************************************************************************* -+* mvBoardRTCGpioPinGet - mvBoardRTCGpioPinGet -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* GPIO pin number. The function return -1 for bad parameters. -+* -+*******************************************************************************/ -+MV_32 mvBoardRTCGpioPinGet(MV_VOID) -+{ -+ return mvBoarGpioPinNumGet(BOARD_GPP_RTC, 0); -+} -+ -+ -+/******************************************************************************* -+* mvBoardReset - mvBoardReset -+* -+* DESCRIPTION: -+* Reset the board -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None -+* -+*******************************************************************************/ -+MV_VOID mvBoardReset(MV_VOID) -+{ -+ MV_32 resetPin; -+ -+ /* Get gpp reset pin if define */ -+ resetPin = mvBoardResetGpioPinGet(); -+ if (resetPin != MV_ERROR) -+ { -+ MV_REG_BIT_RESET( GPP_DATA_OUT_REG(0) ,(1 << resetPin)); -+ MV_REG_BIT_RESET( GPP_DATA_OUT_EN_REG(0) ,(1 << resetPin)); -+ -+ } -+ else -+ { -+ /* No gpp reset pin was found, try to reset ussing -+ system reset out */ -+ MV_REG_BIT_SET( CPU_RSTOUTN_MASK_REG , BIT2); -+ MV_REG_BIT_SET( CPU_SYS_SOFT_RST_REG , BIT0); -+ } -+} -+ -+/******************************************************************************* -+* mvBoardResetGpioPinGet - mvBoardResetGpioPinGet -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* GPIO pin number. The function return -1 for bad parameters. -+* -+*******************************************************************************/ -+MV_32 mvBoardResetGpioPinGet(MV_VOID) -+{ -+ return mvBoarGpioPinNumGet(BOARD_GPP_RESET, 0); -+} -+/******************************************************************************* -+* mvBoardSDIOGpioPinGet - mvBoardSDIOGpioPinGet -+* -+* DESCRIPTION: -+* used for hotswap detection -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* GPIO pin number. The function return -1 for bad parameters. -+* -+*******************************************************************************/ -+MV_32 mvBoardSDIOGpioPinGet(MV_VOID) -+{ -+ return mvBoarGpioPinNumGet(BOARD_GPP_SDIO_DETECT, 0); -+} -+ -+/******************************************************************************* -+* mvBoardUSBVbusGpioPinGet - return Vbus input GPP -+* -+* DESCRIPTION: -+* -+* INPUT: -+* int devNo. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* GPIO pin number. The function return -1 for bad parameters. -+* -+*******************************************************************************/ -+MV_32 mvBoardUSBVbusGpioPinGet(MV_32 devId) -+{ -+ return mvBoarGpioPinNumGet(BOARD_GPP_USB_VBUS, devId); -+} -+ -+/******************************************************************************* -+* mvBoardUSBVbusEnGpioPinGet - return Vbus Enable output GPP -+* -+* DESCRIPTION: -+* -+* INPUT: -+* int devNo. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* GPIO pin number. The function return -1 for bad parameters. -+* -+*******************************************************************************/ -+MV_32 mvBoardUSBVbusEnGpioPinGet(MV_32 devId) -+{ -+ return mvBoarGpioPinNumGet(BOARD_GPP_USB_VBUS_EN, devId); -+} -+ -+ -+/******************************************************************************* -+* mvBoardGpioIntMaskGet - Get GPIO mask for interrupt pins -+* -+* DESCRIPTION: -+* This function returns a 32-bit mask of GPP pins that connected to -+* interrupt generating sources on board. -+* For example if UART channel A is hardwired to GPP pin 8 and -+* UART channel B is hardwired to GPP pin 4 the fuinction will return -+* the value 0x000000110 -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* See description. The function return -1 if board is not identified. -+* -+*******************************************************************************/ -+MV_32 mvBoardGpioIntMaskLowGet(MV_VOID) -+{ -+ MV_U32 boardId; -+ -+ boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardGpioIntMaskGet:Board unknown.\n"); -+ return MV_ERROR; -+ -+ } -+ -+ return BOARD_INFO(boardId)->intsGppMaskLow; -+} -+MV_32 mvBoardGpioIntMaskHighGet(MV_VOID) -+{ -+ MV_U32 boardId; -+ -+ boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardGpioIntMaskGet:Board unknown.\n"); -+ return MV_ERROR; -+ -+ } -+ -+ return BOARD_INFO(boardId)->intsGppMaskHigh; -+} -+ -+ -+/******************************************************************************* -+* mvBoardMppGet - Get board dependent MPP register value -+* -+* DESCRIPTION: -+* MPP settings are derived from board design. -+* MPP group consist of 8 MPPs. An MPP group represent MPP -+* control register. -+* This function retrieves board dependend MPP register value. -+* -+* INPUT: -+* mppGroupNum - MPP group number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit value describing MPP control register value. -+* -+*******************************************************************************/ -+MV_32 mvBoardMppGet(MV_U32 mppGroupNum) -+{ -+ MV_U32 boardId; -+ -+ boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardMppGet:Board unknown.\n"); -+ return MV_ERROR; -+ -+ } -+ -+ return BOARD_INFO(boardId)->pBoardMppConfigValue[0].mppGroup[mppGroupNum]; -+} -+ -+ -+/******************************************************************************* -+* mvBoardMppGroupId - If MPP group type is AUTO then identify it using twsi -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_VOID mvBoardMppGroupIdUpdate(MV_VOID) -+{ -+ -+ MV_BOARD_MPP_GROUP_CLASS devClass; -+ MV_BOARD_MODULE_ID_CLASS devClassId; -+ MV_BOARD_MPP_TYPE_CLASS mppGroupType; -+ MV_U32 devId; -+ MV_U32 maxMppGrp = 1; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ maxMppGrp = MV_6281_MPP_MAX_MODULE; -+ break; -+ case MV_6192_DEV_ID: -+ maxMppGrp = MV_6192_MPP_MAX_MODULE; -+ break; -+ case MV_6190_DEV_ID: -+ maxMppGrp = MV_6190_MPP_MAX_MODULE; -+ break; -+ case MV_6180_DEV_ID: -+ maxMppGrp = MV_6180_MPP_MAX_MODULE; -+ break; -+ } -+ -+ for (devClass = 0; devClass < maxMppGrp; devClass++) -+ { -+ /* If MPP group can be defined by the module connected to it */ -+ if (mvBoardMppGroupTypeGet(devClass) == MV_BOARD_AUTO) -+ { -+ /* Get MPP module ID */ -+ devClassId = mvBoarModuleTypeGet(devClass); -+ if (MV_ERROR != devClassId) -+ { -+ switch(devClassId) -+ { -+ case MV_BOARD_MODULE_TDM_ID: -+ case MV_BOARD_MODULE_TDM_5CHAN_ID: -+ mppGroupType = MV_BOARD_TDM; -+ break; -+ case MV_BOARD_MODULE_AUDIO_ID: -+ mppGroupType = MV_BOARD_AUDIO; -+ break; -+ case MV_BOARD_MODULE_RGMII_ID: -+ mppGroupType = MV_BOARD_RGMII; -+ break; -+ case MV_BOARD_MODULE_GMII_ID: -+ mppGroupType = MV_BOARD_GMII; -+ break; -+ case MV_BOARD_MODULE_TS_ID: -+ mppGroupType = MV_BOARD_TS; -+ break; -+ case MV_BOARD_MODULE_MII_ID: -+ mppGroupType = MV_BOARD_MII; -+ break; -+ default: -+ mppGroupType = MV_BOARD_OTHER; -+ break; -+ } -+ } -+ else -+ /* The module bay is empty */ -+ mppGroupType = MV_BOARD_OTHER; -+ -+ /* Update MPP group type */ -+ mvBoardMppGroupTypeSet(devClass, mppGroupType); -+ } -+ -+ /* Update MPP output voltage for RGMII 1.8V. Set port to GMII for GMII module */ -+ if ((mvBoardMppGroupTypeGet(devClass) == MV_BOARD_RGMII)) -+ MV_REG_BIT_SET(MPP_OUTPUT_DRIVE_REG,MPP_1_8_RGMII1_OUTPUT_DRIVE | MPP_1_8_RGMII0_OUTPUT_DRIVE); -+ else -+ { -+ if ((mvBoardMppGroupTypeGet(devClass) == MV_BOARD_GMII)) -+ { -+ MV_REG_BIT_RESET(MPP_OUTPUT_DRIVE_REG, BIT7 | BIT15); -+ MV_REG_BIT_RESET(ETH_PORT_SERIAL_CTRL_1_REG(0),BIT3); -+ MV_REG_BIT_RESET(ETH_PORT_SERIAL_CTRL_1_REG(1),BIT3); -+ } -+ else if ((mvBoardMppGroupTypeGet(devClass) == MV_BOARD_MII)) -+ { -+ /* Assumption that the MDC & MDIO should be 3.3V */ -+ MV_REG_BIT_RESET(MPP_OUTPUT_DRIVE_REG, BIT7 | BIT15); -+ /* Assumption that only ETH1 can be MII when using modules on DB */ -+ MV_REG_BIT_RESET(ETH_PORT_SERIAL_CTRL_1_REG(1),BIT3); -+ } -+ } -+ } -+} -+ -+/******************************************************************************* -+* mvBoardMppGroupTypeGet -+* -+* DESCRIPTION: -+* -+* INPUT: -+* mppGroupClass - MPP group number 0 for MPP[35:20] or 1 for MPP[49:36]. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_BOARD_MPP_TYPE_CLASS mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass) -+{ -+ MV_U32 boardId; -+ -+ boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardMppGet:Board unknown.\n"); -+ return MV_ERROR; -+ -+ } -+ -+ if (mppGroupClass == MV_BOARD_MPP_GROUP_1) -+ return BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup1; -+ else -+ return BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup2; -+} -+ -+/******************************************************************************* -+* mvBoardMppGroupTypeSet -+* -+* DESCRIPTION: -+* -+* INPUT: -+* mppGroupClass - MPP group number 0 for MPP[35:20] or 1 for MPP[49:36]. -+* mppGroupType - MPP group type for MPP[35:20] or for MPP[49:36]. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_VOID mvBoardMppGroupTypeSet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass, -+ MV_BOARD_MPP_TYPE_CLASS mppGroupType) -+{ -+ MV_U32 boardId; -+ -+ boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardMppGet:Board unknown.\n"); -+ } -+ -+ if (mppGroupClass == MV_BOARD_MPP_GROUP_1) -+ BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup1 = mppGroupType; -+ else -+ BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup2 = mppGroupType; -+ -+} -+ -+/******************************************************************************* -+* mvBoardMppMuxSet - Update MPP mux -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_VOID mvBoardMppMuxSet(MV_VOID) -+{ -+ -+ MV_BOARD_MPP_GROUP_CLASS devClass; -+ MV_BOARD_MPP_TYPE_CLASS mppGroupType; -+ MV_U32 devId; -+ MV_U8 muxVal = 0xf; -+ MV_U32 maxMppGrp = 1; -+ MV_TWSI_SLAVE twsiSlave; -+ MV_TWSI_ADDR slave; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ maxMppGrp = MV_6281_MPP_MAX_MODULE; -+ break; -+ case MV_6192_DEV_ID: -+ maxMppGrp = MV_6192_MPP_MAX_MODULE; -+ break; -+ case MV_6190_DEV_ID: -+ maxMppGrp = MV_6190_MPP_MAX_MODULE; -+ break; -+ case MV_6180_DEV_ID: -+ maxMppGrp = MV_6180_MPP_MAX_MODULE; -+ break; -+ } -+ -+ for (devClass = 0; devClass < maxMppGrp; devClass++) -+ { -+ mppGroupType = mvBoardMppGroupTypeGet(devClass); -+ -+ switch(mppGroupType) -+ { -+ case MV_BOARD_TDM: -+ muxVal &= ~(devClass ? (0x2 << (devClass * 2)):0x0); -+ break; -+ case MV_BOARD_AUDIO: -+ muxVal &= ~(devClass ? 0x7 : 0x0); /*old Z0 value 0xd:0x0*/ -+ break; -+ case MV_BOARD_TS: -+ muxVal &= ~(devClass ? (0x2 << (devClass * 2)):0x0); -+ break; -+ default: -+ muxVal |= (devClass ? 0xf : 0); -+ break; -+ } -+ } -+ -+ /* TWSI init */ -+ slave.type = ADDR7_BIT; -+ slave.address = 0; -+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); -+ -+ /* Read MPP module ID */ -+ DB(mvOsPrintf("Board: twsi exp set\n")); -+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(MV_BOARD_MUX_I2C_ADDR_ENTRY); -+ twsiSlave.slaveAddr.type = mvBoardTwsiExpAddrTypeGet(MV_BOARD_MUX_I2C_ADDR_ENTRY); -+ twsiSlave.validOffset = MV_TRUE; -+ /* Offset is the first command after the address which indicate the register number to be read -+ in next operation */ -+ twsiSlave.offset = 2; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ -+ -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) -+ { -+ DB(mvOsPrintf("Board: twsi exp out val fail\n")); -+ return; -+ } -+ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); -+ -+ /* Change twsi exp to output */ -+ twsiSlave.offset = 6; -+ muxVal = 0; -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) -+ { -+ DB(mvOsPrintf("Board: twsi exp change to out fail\n")); -+ return; -+ } -+ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); -+ -+} -+ -+/******************************************************************************* -+* mvBoardTdmMppSet - set MPPs in TDM module -+* -+* DESCRIPTION: -+* -+* INPUT: type of second telephony device -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_VOID mvBoardTdmMppSet(MV_32 chType) -+{ -+ -+ MV_BOARD_MPP_GROUP_CLASS devClass; -+ MV_BOARD_MPP_TYPE_CLASS mppGroupType; -+ MV_U32 devId; -+ MV_U8 muxVal = 1; -+ MV_U8 muxValMask = 1; -+ MV_U8 twsiVal; -+ MV_U32 maxMppGrp = 1; -+ MV_TWSI_SLAVE twsiSlave; -+ MV_TWSI_ADDR slave; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ maxMppGrp = MV_6281_MPP_MAX_MODULE; -+ break; -+ case MV_6192_DEV_ID: -+ maxMppGrp = MV_6192_MPP_MAX_MODULE; -+ break; -+ case MV_6190_DEV_ID: -+ maxMppGrp = MV_6190_MPP_MAX_MODULE; -+ break; -+ case MV_6180_DEV_ID: -+ maxMppGrp = MV_6180_MPP_MAX_MODULE; -+ break; -+ } -+ -+ for (devClass = 0; devClass < maxMppGrp; devClass++) -+ { -+ mppGroupType = mvBoardMppGroupTypeGet(devClass); -+ if(mppGroupType == MV_BOARD_TDM) -+ break; -+ } -+ -+ if(devClass == maxMppGrp) -+ return; /* TDM module not found */ -+ -+ /* TWSI init */ -+ slave.type = ADDR7_BIT; -+ slave.address = 0; -+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); -+ -+ /* Read MPP module ID */ -+ DB(mvOsPrintf("Board: twsi exp set\n")); -+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(devClass); -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ /* Offset is the first command after the address which indicate the register number to be read -+ in next operation */ -+ twsiSlave.offset = 3; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ if(mvBoardIdGet() == RD_88F6281A_ID) -+ { -+ muxVal = 0xc; -+ muxValMask = 0xf3; -+ } -+ -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ muxVal = (twsiVal & muxValMask) | muxVal; -+ -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) -+ { -+ mvOsPrintf("Board: twsi exp out val fail\n"); -+ return; -+ } -+ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); -+ -+ /* Change twsi exp to output */ -+ twsiSlave.offset = 7; -+ muxVal = 0xfe; -+ if(mvBoardIdGet() == RD_88F6281A_ID) -+ muxVal = 0xf3; -+ -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ muxVal = (twsiVal & muxVal); -+ -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) -+ { -+ mvOsPrintf("Board: twsi exp change to out fail\n"); -+ return; -+ } -+ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); -+ /* reset the line to 0 */ -+ twsiSlave.offset = 3; -+ muxVal = 0; -+ muxValMask = 1; -+ -+ if(mvBoardIdGet() == RD_88F6281A_ID) { -+ muxVal = 0x0; -+ muxValMask = 0xf3; -+ } -+ -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ muxVal = (twsiVal & muxValMask) | muxVal; -+ -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) -+ { -+ mvOsPrintf("Board: twsi exp out val fail\n"); -+ return; -+ } -+ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); -+ -+ mvOsDelay(20); -+ -+ /* set the line to 1 */ -+ twsiSlave.offset = 3; -+ muxVal = 1; -+ muxValMask = 1; -+ -+ if(mvBoardIdGet() == RD_88F6281A_ID) -+ { -+ muxVal = 0xc; -+ muxValMask = 0xf3; -+ if(chType) /* FXS - issue reset properly */ -+ { -+ MV_REG_BIT_SET(GPP_DATA_OUT_REG(1), MV_GPP12); -+ mvOsDelay(50); -+ MV_REG_BIT_RESET(GPP_DATA_OUT_REG(1), MV_GPP12); -+ } -+ else /* FXO - issue reset via TDM_CODEC_RST*/ -+ { -+ /* change MPP44 type to TDM_CODEC_RST(0x2) */ -+ MV_REG_WRITE(MPP_CONTROL_REG5, ((MV_REG_READ(MPP_CONTROL_REG5) & 0xFFF0FFFF) | BIT17)); -+ } -+ } -+ -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ muxVal = (twsiVal & muxValMask) | muxVal; -+ -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) -+ { -+ mvOsPrintf("Board: twsi exp out val fail\n"); -+ return; -+ } -+ -+ /* TBD - 5 channels */ -+#if defined(MV_TDM_5CHANNELS) -+ /* change MPP38 type to GPIO(0x0) & polarity for TDM_STROBE */ -+ MV_REG_WRITE(MPP_CONTROL_REG4, (MV_REG_READ(MPP_CONTROL_REG4) & 0xF0FFFFFF)); -+ mvGppPolaritySet(1, MV_GPP6, 0); -+ -+ twsiSlave.offset = 6; -+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(2); -+ -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ muxVal = (twsiVal & ~BIT2); -+ -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) -+ { -+ mvOsPrintf("Board: twsi exp change to out fail\n"); -+ return; -+ } -+ -+ -+ twsiSlave.offset = 2; -+ -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ muxVal = (twsiVal & ~BIT2); -+ -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) -+ { -+ mvOsPrintf("Board: twsi exp change to out fail\n"); -+ return; -+ } -+#endif -+ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); -+ -+ -+} -+/******************************************************************************* -+* mvBoardVoiceConnModeGet - return SLIC/DAA connection & interrupt modes -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+ -+MV_VOID mvBoardVoiceConnModeGet(MV_32* connMode, MV_32* irqMode) -+{ -+ switch(mvBoardIdGet()) -+ { -+ case RD_88F6281A_ID: -+ *connMode = DAISY_CHAIN_MODE; -+ *irqMode = INTERRUPT_TO_TDM; -+ break; -+ case DB_88F6281A_BP_ID: -+ *connMode = DUAL_CHIP_SELECT_MODE; -+ *irqMode = INTERRUPT_TO_TDM; -+ break; -+ case RD_88F6192A_ID: -+ *connMode = DUAL_CHIP_SELECT_MODE; -+ *irqMode = INTERRUPT_TO_TDM; -+ break; -+ case DB_88F6192A_BP_ID: -+ *connMode = DUAL_CHIP_SELECT_MODE; -+ *irqMode = INTERRUPT_TO_TDM; -+ break; -+ default: -+ *connMode = *irqMode = -1; -+ mvOsPrintf("mvBoardVoiceAssembleModeGet: TDM not supported(boardId=0x%x)\n",mvBoardIdGet()); -+ } -+ return; -+ -+} -+ -+/******************************************************************************* -+* mvBoardMppModuleTypePrint - print module detect -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_VOID mvBoardMppModuleTypePrint(MV_VOID) -+{ -+ -+ MV_BOARD_MPP_GROUP_CLASS devClass; -+ MV_BOARD_MPP_TYPE_CLASS mppGroupType; -+ MV_U32 devId; -+ MV_U32 maxMppGrp = 1; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ maxMppGrp = MV_6281_MPP_MAX_MODULE; -+ break; -+ case MV_6192_DEV_ID: -+ maxMppGrp = MV_6192_MPP_MAX_MODULE; -+ break; -+ case MV_6190_DEV_ID: -+ maxMppGrp = MV_6190_MPP_MAX_MODULE; -+ break; -+ case MV_6180_DEV_ID: -+ maxMppGrp = MV_6180_MPP_MAX_MODULE; -+ break; -+ } -+ -+ for (devClass = 0; devClass < maxMppGrp; devClass++) -+ { -+ mppGroupType = mvBoardMppGroupTypeGet(devClass); -+ -+ switch(mppGroupType) -+ { -+ case MV_BOARD_TDM: -+ if(devId != MV_6190_DEV_ID) -+ mvOsPrintf("Module %d is TDM\n", devClass); -+ break; -+ case MV_BOARD_AUDIO: -+ if(devId != MV_6190_DEV_ID) -+ mvOsPrintf("Module %d is AUDIO\n", devClass); -+ break; -+ case MV_BOARD_RGMII: -+ if(devId != MV_6190_DEV_ID) -+ mvOsPrintf("Module %d is RGMII\n", devClass); -+ break; -+ case MV_BOARD_GMII: -+ if(devId != MV_6190_DEV_ID) -+ mvOsPrintf("Module %d is GMII\n", devClass); -+ break; -+ case MV_BOARD_TS: -+ if(devId != MV_6190_DEV_ID) -+ mvOsPrintf("Module %d is TS\n", devClass); -+ break; -+ default: -+ break; -+ } -+ } -+} -+ -+/* Board devices API managments */ -+ -+/******************************************************************************* -+* mvBoardGetDeviceNumber - Get number of device of some type on the board -+* -+* DESCRIPTION: -+* -+* INPUT: -+* devType - The device type ( Flash,RTC , etc .. ) -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* If the device is found on the board the then the functions returns the -+* number of those devices else the function returns 0 -+* -+* -+*******************************************************************************/ -+MV_32 mvBoardGetDevicesNumber(MV_BOARD_DEV_CLASS devClass) -+{ -+ MV_U32 foundIndex=0,devNum; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardGetDeviceNumber:Board unknown.\n"); -+ return 0xFFFFFFFF; -+ -+ } -+ -+ for (devNum = START_DEV_CS; devNum < BOARD_INFO(boardId)->numBoardDeviceIf; devNum++) -+ { -+ if (BOARD_INFO(boardId)->pDevCsInfo[devNum].devClass == devClass) -+ { -+ foundIndex++; -+ } -+ } -+ -+ return foundIndex; -+ -+} -+ -+/******************************************************************************* -+* mvBoardGetDeviceBaseAddr - Get base address of a device existing on the board -+* -+* DESCRIPTION: -+* -+* INPUT: -+* devIndex - The device sequential number on the board -+* devType - The device type ( Flash,RTC , etc .. ) -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* If the device is found on the board the then the functions returns the -+* Base address else the function returns 0xffffffff -+* -+* -+*******************************************************************************/ -+MV_32 mvBoardGetDeviceBaseAddr(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) -+{ -+ MV_DEV_CS_INFO* devEntry; -+ devEntry = boardGetDevEntry(devNum,devClass); -+ if (devEntry != NULL) -+ { -+ return mvCpuIfTargetWinBaseLowGet(DEV_TO_TARGET(devEntry->deviceCS)); -+ -+ } -+ -+ return 0xFFFFFFFF; -+} -+ -+/******************************************************************************* -+* mvBoardGetDeviceBusWidth - Get Bus width of a device existing on the board -+* -+* DESCRIPTION: -+* -+* INPUT: -+* devIndex - The device sequential number on the board -+* devType - The device type ( Flash,RTC , etc .. ) -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* If the device is found on the board the then the functions returns the -+* Bus width else the function returns 0xffffffff -+* -+* -+*******************************************************************************/ -+MV_32 mvBoardGetDeviceBusWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) -+{ -+ MV_DEV_CS_INFO* devEntry; -+ -+ devEntry = boardGetDevEntry(devNum,devClass); -+ if (devEntry != NULL) -+ { -+ return 8; -+ } -+ -+ return 0xFFFFFFFF; -+ -+} -+ -+/******************************************************************************* -+* mvBoardGetDeviceWidth - Get dev width of a device existing on the board -+* -+* DESCRIPTION: -+* -+* INPUT: -+* devIndex - The device sequential number on the board -+* devType - The device type ( Flash,RTC , etc .. ) -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* If the device is found on the board the then the functions returns the -+* dev width else the function returns 0xffffffff -+* -+* -+*******************************************************************************/ -+MV_32 mvBoardGetDeviceWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) -+{ -+ MV_DEV_CS_INFO* devEntry; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("Board unknown.\n"); -+ return 0xFFFFFFFF; -+ } -+ -+ devEntry = boardGetDevEntry(devNum,devClass); -+ if (devEntry != NULL) -+ return devEntry->devWidth; -+ -+ return MV_ERROR; -+ -+} -+ -+/******************************************************************************* -+* mvBoardGetDeviceWinSize - Get the window size of a device existing on the board -+* -+* DESCRIPTION: -+* -+* INPUT: -+* devIndex - The device sequential number on the board -+* devType - The device type ( Flash,RTC , etc .. ) -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* If the device is found on the board the then the functions returns the -+* window size else the function returns 0xffffffff -+* -+* -+*******************************************************************************/ -+MV_32 mvBoardGetDeviceWinSize(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) -+{ -+ MV_DEV_CS_INFO* devEntry; -+ MV_U32 boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("Board unknown.\n"); -+ return 0xFFFFFFFF; -+ } -+ -+ devEntry = boardGetDevEntry(devNum,devClass); -+ if (devEntry != NULL) -+ { -+ return mvCpuIfTargetWinSizeGet(DEV_TO_TARGET(devEntry->deviceCS)); -+ } -+ -+ return 0xFFFFFFFF; -+} -+ -+ -+/******************************************************************************* -+* boardGetDevEntry - returns the entry pointer of a device on the board -+* -+* DESCRIPTION: -+* -+* INPUT: -+* devIndex - The device sequential number on the board -+* devType - The device type ( Flash,RTC , etc .. ) -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* If the device is found on the board the then the functions returns the -+* dev number else the function returns 0x0 -+* -+* -+*******************************************************************************/ -+static MV_DEV_CS_INFO* boardGetDevEntry(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) -+{ -+ MV_U32 foundIndex=0,devIndex; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("boardGetDevEntry: Board unknown.\n"); -+ return NULL; -+ -+ } -+ -+ for (devIndex = START_DEV_CS; devIndex < BOARD_INFO(boardId)->numBoardDeviceIf; devIndex++) -+ { -+ /* TBR */ -+ /*if (BOARD_INFO(boardId)->pDevCsInfo[devIndex].deviceCS == MV_BOOTDEVICE_INDEX) -+ continue;*/ -+ -+ if (BOARD_INFO(boardId)->pDevCsInfo[devIndex].devClass == devClass) -+ { -+ if (foundIndex == devNum) -+ { -+ return &(BOARD_INFO(boardId)->pDevCsInfo[devIndex]); -+ } -+ foundIndex++; -+ } -+ } -+ -+ /* device not found */ -+ return NULL; -+} -+ -+/* Get device CS number */ -+ -+MV_U32 boardGetDevCSNum(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) -+{ -+ MV_DEV_CS_INFO* devEntry; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("Board unknown.\n"); -+ return 0xFFFFFFFF; -+ -+ } -+ -+ -+ devEntry = boardGetDevEntry(devNum,devClass); -+ if (devEntry != NULL) -+ return devEntry->deviceCS; -+ -+ return 0xFFFFFFFF; -+ -+} -+ -+/******************************************************************************* -+* mvBoardRtcTwsiAddrTypeGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_U8 mvBoardRtcTwsiAddrTypeGet() -+{ -+ int i; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) -+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_RTC) -+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; -+ return (MV_ERROR); -+} -+ -+/******************************************************************************* -+* mvBoardRtcTwsiAddrGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_U8 mvBoardRtcTwsiAddrGet() -+{ -+ int i; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) -+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_RTC) -+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; -+ return (0xFF); -+} -+ -+/******************************************************************************* -+* mvBoardA2DTwsiAddrTypeGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_U8 mvBoardA2DTwsiAddrTypeGet() -+{ -+ int i; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) -+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_AUDIO_DEC) -+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; -+ return (MV_ERROR); -+} -+ -+/******************************************************************************* -+* mvBoardA2DTwsiAddrGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_U8 mvBoardA2DTwsiAddrGet() -+{ -+ int i; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) -+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_AUDIO_DEC) -+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; -+ return (0xFF); -+} -+ -+/******************************************************************************* -+* mvBoardTwsiExpAddrTypeGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_U8 mvBoardTwsiExpAddrTypeGet(MV_U32 index) -+{ -+ int i; -+ MV_U32 indexFound = 0; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) -+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_EXP) -+ { -+ if (indexFound == index) -+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; -+ else -+ indexFound++; -+ } -+ -+ return (MV_ERROR); -+} -+ -+/******************************************************************************* -+* mvBoardTwsiExpAddrGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_U8 mvBoardTwsiExpAddrGet(MV_U32 index) -+{ -+ int i; -+ MV_U32 indexFound = 0; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) -+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_EXP) -+ { -+ if (indexFound == index) -+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; -+ else -+ indexFound++; -+ } -+ -+ return (0xFF); -+} -+ -+ -+/******************************************************************************* -+* mvBoardTwsiSatRAddrTypeGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_U8 mvBoardTwsiSatRAddrTypeGet(MV_U32 index) -+{ -+ int i; -+ MV_U32 indexFound = 0; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) -+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_SATR) -+ { -+ if (indexFound == index) -+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; -+ else -+ indexFound++; -+ } -+ -+ return (MV_ERROR); -+} -+ -+/******************************************************************************* -+* mvBoardTwsiSatRAddrGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_U8 mvBoardTwsiSatRAddrGet(MV_U32 index) -+{ -+ int i; -+ MV_U32 indexFound = 0; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) -+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_SATR) -+ { -+ if (indexFound == index) -+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; -+ else -+ indexFound++; -+ } -+ -+ return (0xFF); -+} -+ -+/******************************************************************************* -+* mvBoardNandWidthGet - -+* -+* DESCRIPTION: Get the width of the first NAND device in byte. -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: 1, 2, 4 or MV_ERROR -+* -+* -+*******************************************************************************/ -+/* */ -+MV_32 mvBoardNandWidthGet(void) -+{ -+ MV_U32 devNum; -+ MV_U32 devWidth; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (devNum = START_DEV_CS; devNum < BOARD_INFO(boardId)->numBoardDeviceIf; devNum++) -+ { -+ devWidth = mvBoardGetDeviceWidth(devNum, BOARD_DEV_NAND_FLASH); -+ if (devWidth != MV_ERROR) -+ return (devWidth / 8); -+ } -+ -+ /* NAND wasn't found */ -+ return MV_ERROR; -+} -+ -+MV_U32 gBoardId = -1; -+ -+/******************************************************************************* -+* mvBoardIdGet - Get Board model -+* -+* DESCRIPTION: -+* This function returns board ID. -+* Board ID is 32bit word constructed of board model (16bit) and -+* board revision (16bit) in the following way: 0xMMMMRRRR. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit board ID number, '-1' if board is undefined. -+* -+*******************************************************************************/ -+MV_U32 mvBoardIdGet(MV_VOID) -+{ -+ MV_U32 tmpBoardId = -1; -+ -+ if(gBoardId == -1) -+ { -+ #if defined(DB_88F6281A) -+ tmpBoardId = DB_88F6281A_BP_ID; -+ #elif defined(RD_88F6281A) -+ tmpBoardId = RD_88F6281A_ID; -+ #elif defined(DB_88F6192A) -+ tmpBoardId = DB_88F6192A_BP_ID; -+ #elif defined(DB_88F6190A) -+ tmpBoardId = DB_88F6190A_BP_ID; -+ #elif defined(RD_88F6192A) -+ tmpBoardId = RD_88F6192A_ID; -+ #elif defined(RD_88F6190A) -+ tmpBoardId = RD_88F6190A_ID; -+ #elif defined(DB_88F6180A) -+ tmpBoardId = DB_88F6180A_BP_ID; -+ #elif defined(RD_88F6281A_PCAC) -+ tmpBoardId = RD_88F6281A_PCAC_ID; -+ #elif defined(RD_88F6281A_SHEEVA_PLUG) -+ tmpBoardId = SHEEVA_PLUG_ID; -+ #elif defined(DB_CUSTOMER) -+ tmpBoardId = DB_CUSTOMER_ID; -+ #endif -+ gBoardId = tmpBoardId; -+ } -+ -+ return gBoardId; -+} -+ -+ -+/******************************************************************************* -+* mvBoarModuleTypeGet - mvBoarModuleTypeGet -+* -+* DESCRIPTION: -+* -+* INPUT: -+* group num - MV_BOARD_MPP_GROUP_CLASS enum -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* module num - MV_BOARD_MODULE_CLASS enum -+* -+*******************************************************************************/ -+MV_BOARD_MODULE_ID_CLASS mvBoarModuleTypeGet(MV_BOARD_MPP_GROUP_CLASS devClass) -+{ -+ MV_TWSI_SLAVE twsiSlave; -+ MV_TWSI_ADDR slave; -+ MV_U8 data; -+ -+ /* TWSI init */ -+ slave.type = ADDR7_BIT; -+ slave.address = 0; -+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); -+ -+ /* Read MPP module ID */ -+ DB(mvOsPrintf("Board: Read MPP module ID\n")); -+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(devClass); -+ twsiSlave.slaveAddr.type = mvBoardTwsiExpAddrTypeGet(devClass); -+ twsiSlave.validOffset = MV_TRUE; -+ /* Offset is the first command after the address which indicate the register number to be read -+ in next operation */ -+ twsiSlave.offset = 0; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ -+ -+ if( MV_OK != mvTwsiRead (0, &twsiSlave, &data, 1) ) -+ { -+ DB(mvOsPrintf("Board: Read MPP module ID fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: Read MPP module ID succeded\n")); -+ -+ return data; -+} -+ -+/******************************************************************************* -+* mvBoarTwsiSatRGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* device num - one of three devices -+* reg num - 0 or 1 -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* reg value -+* -+*******************************************************************************/ -+MV_U8 mvBoarTwsiSatRGet(MV_U8 devNum, MV_U8 regNum) -+{ -+ MV_TWSI_SLAVE twsiSlave; -+ MV_TWSI_ADDR slave; -+ MV_U8 data; -+ -+ /* TWSI init */ -+ slave.type = ADDR7_BIT; -+ slave.address = 0; -+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); -+ -+ /* Read MPP module ID */ -+ DB(mvOsPrintf("Board: Read S@R device read\n")); -+ twsiSlave.slaveAddr.address = mvBoardTwsiSatRAddrGet(devNum); -+ twsiSlave.slaveAddr.type = mvBoardTwsiSatRAddrTypeGet(devNum); -+ twsiSlave.validOffset = MV_TRUE; -+ /* Use offset as command */ -+ twsiSlave.offset = regNum; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ if( MV_OK != mvTwsiRead (0, &twsiSlave, &data, 1) ) -+ { -+ DB(mvOsPrintf("Board: Read S@R fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: Read S@R succeded\n")); -+ -+ return data; -+} -+ -+/******************************************************************************* -+* mvBoarTwsiSatRSet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* devNum - one of three devices -+* regNum - 0 or 1 -+* regVal - value -+* -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* reg value -+* -+*******************************************************************************/ -+MV_STATUS mvBoarTwsiSatRSet(MV_U8 devNum, MV_U8 regNum, MV_U8 regVal) -+{ -+ MV_TWSI_SLAVE twsiSlave; -+ MV_TWSI_ADDR slave; -+ -+ /* TWSI init */ -+ slave.type = ADDR7_BIT; -+ slave.address = 0; -+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); -+ -+ /* Read MPP module ID */ -+ twsiSlave.slaveAddr.address = mvBoardTwsiSatRAddrGet(devNum); -+ twsiSlave.slaveAddr.type = mvBoardTwsiSatRAddrTypeGet(devNum); -+ twsiSlave.validOffset = MV_TRUE; -+ DB(mvOsPrintf("Board: Write S@R device addr %x, type %x, data %x\n", twsiSlave.slaveAddr.address,\ -+ twsiSlave.slaveAddr.type, regVal)); -+ /* Use offset as command */ -+ twsiSlave.offset = regNum; -+ twsiSlave.moreThen256 = MV_FALSE; -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, ®Val, 1) ) -+ { -+ DB(mvOsPrintf("Board: Write S@R fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: Write S@R succeded\n")); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvBoardSlicGpioPinGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_32 mvBoardSlicGpioPinGet(MV_U32 slicNum) -+{ -+ MV_U32 boardId; -+ boardId = mvBoardIdGet(); -+ -+ switch (boardId) -+ { -+ case DB_88F6281A_BP_ID: -+ case RD_88F6281A_ID: -+ default: -+ return MV_ERROR; -+ break; -+ -+ } -+} -+ -+/******************************************************************************* -+* mvBoardFanPowerControl - Turn on/off the fan power control on the RD-6281A -+* -+* DESCRIPTION: -+* -+* INPUT: -+* mode - MV_TRUE = on ; MV_FALSE = off -+* -+* OUTPUT: -+* MV_STATUS - MV_OK , MV_ERROR. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_STATUS mvBoardFanPowerControl(MV_BOOL mode) -+{ -+ -+ MV_U8 val = 1, twsiVal; -+ MV_TWSI_SLAVE twsiSlave; -+ MV_TWSI_ADDR slave; -+ -+ if(mvBoardIdGet() != RD_88F6281A_ID) -+ return MV_ERROR; -+ -+ /* TWSI init */ -+ slave.type = ADDR7_BIT; -+ slave.address = 0; -+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); -+ -+ /* Read MPP module ID */ -+ DB(mvOsPrintf("Board: twsi exp set\n")); -+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(1); -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ /* Offset is the first command after the address which indicate the register number to be read -+ in next operation */ -+ twsiSlave.offset = 3; -+ twsiSlave.moreThen256 = MV_FALSE; -+ if(mode == MV_TRUE) -+ val = 0x1; -+ else -+ val = 0; -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ val = (twsiVal & 0xfe) | val; -+ -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) -+ { -+ DB(mvOsPrintf("Board: twsi exp out val fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); -+ -+ /* Change twsi exp to output */ -+ twsiSlave.offset = 7; -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ val = (twsiVal & 0xfe); -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) -+ { -+ DB(mvOsPrintf("Board: twsi exp change to out fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvBoardHDDPowerControl - Turn on/off the HDD power control on the RD-6281A -+* -+* DESCRIPTION: -+* -+* INPUT: -+* mode - MV_TRUE = on ; MV_FALSE = off -+* -+* OUTPUT: -+* MV_STATUS - MV_OK , MV_ERROR. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_STATUS mvBoardHDDPowerControl(MV_BOOL mode) -+{ -+ -+ MV_U8 val = 1, twsiVal; -+ MV_TWSI_SLAVE twsiSlave; -+ MV_TWSI_ADDR slave; -+ -+ if(mvBoardIdGet() != RD_88F6281A_ID) -+ return MV_ERROR; -+ -+ /* TWSI init */ -+ slave.type = ADDR7_BIT; -+ slave.address = 0; -+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); -+ -+ /* Read MPP module ID */ -+ DB(mvOsPrintf("Board: twsi exp set\n")); -+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(1); -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ /* Offset is the first command after the address which indicate the register number to be read -+ in next operation */ -+ twsiSlave.offset = 3; -+ twsiSlave.moreThen256 = MV_FALSE; -+ if(mode == MV_TRUE) -+ val = 0x2; -+ else -+ val = 0; -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ val = (twsiVal & 0xfd) | val; -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) -+ { -+ DB(mvOsPrintf("Board: twsi exp out val fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); -+ -+ /* Change twsi exp to output */ -+ twsiSlave.offset = 7; -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ val = (twsiVal & 0xfd); -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) -+ { -+ DB(mvOsPrintf("Board: twsi exp change to out fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvBoardSDioWPControl - Turn on/off the SDIO WP on the RD-6281A -+* -+* DESCRIPTION: -+* -+* INPUT: -+* mode - MV_TRUE = on ; MV_FALSE = off -+* -+* OUTPUT: -+* MV_STATUS - MV_OK , MV_ERROR. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_STATUS mvBoardSDioWPControl(MV_BOOL mode) -+{ -+ -+ MV_U8 val = 1, twsiVal; -+ MV_TWSI_SLAVE twsiSlave; -+ MV_TWSI_ADDR slave; -+ -+ if(mvBoardIdGet() != RD_88F6281A_ID) -+ return MV_ERROR; -+ -+ /* TWSI init */ -+ slave.type = ADDR7_BIT; -+ slave.address = 0; -+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); -+ -+ /* Read MPP module ID */ -+ DB(mvOsPrintf("Board: twsi exp set\n")); -+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(0); -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ /* Offset is the first command after the address which indicate the register number to be read -+ in next operation */ -+ twsiSlave.offset = 3; -+ twsiSlave.moreThen256 = MV_FALSE; -+ if(mode == MV_TRUE) -+ val = 0x10; -+ else -+ val = 0; -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ val = (twsiVal & 0xef) | val; -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) -+ { -+ DB(mvOsPrintf("Board: twsi exp out val fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); -+ -+ /* Change twsi exp to output */ -+ twsiSlave.offset = 7; -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ val = (twsiVal & 0xef); -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) -+ { -+ DB(mvOsPrintf("Board: twsi exp change to out fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); -+ return MV_OK; -+} -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h 2010-11-09 20:28:07.362495449 +0100 -@@ -0,0 +1,376 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#ifndef __INCmvBoardEnvLibh -+#define __INCmvBoardEnvLibh -+ -+/* defines */ -+/* The below constant macros defines the board I2C EEPROM data offsets */ -+ -+ -+ -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "mvSysHwConfig.h" -+#include "boardEnv/mvBoardEnvSpec.h" -+ -+ -+/* DUART stuff for Tclk detection only */ -+#define DUART_BAUD_RATE 115200 -+#define MAX_CLOCK_MARGINE 5000000 /* Maximum detected clock margine */ -+ -+/* Voice devices assembly modes */ -+#define DAISY_CHAIN_MODE 1 -+#define DUAL_CHIP_SELECT_MODE 0 -+#define INTERRUPT_TO_MPP 1 -+#define INTERRUPT_TO_TDM 0 -+ -+ -+#define BOARD_ETH_PORT_NUM MV_ETH_MAX_PORTS -+#define BOARD_ETH_SWITCH_PORT_NUM 5 -+ -+#define MV_BOARD_MAX_USB_IF 1 -+#define MV_BOARD_MAX_MPP 7 -+#define MV_BOARD_NAME_LEN 0x20 -+ -+typedef struct _boardData -+{ -+ MV_U32 magic; -+ MV_U16 boardId; -+ MV_U8 boardVer; -+ MV_U8 boardRev; -+ MV_U32 reserved1; -+ MV_U32 reserved2; -+ -+}BOARD_DATA; -+ -+typedef enum _devBoardMppGroupClass -+{ -+ MV_BOARD_MPP_GROUP_1, -+ MV_BOARD_MPP_GROUP_2, -+ MV_BOARD_MAX_MPP_GROUP -+}MV_BOARD_MPP_GROUP_CLASS; -+ -+typedef enum _devBoardMppTypeClass -+{ -+ MV_BOARD_AUTO, -+ MV_BOARD_TDM, -+ MV_BOARD_AUDIO, -+ MV_BOARD_RGMII, -+ MV_BOARD_GMII, -+ MV_BOARD_TS, -+ MV_BOARD_MII, -+ MV_BOARD_OTHER -+}MV_BOARD_MPP_TYPE_CLASS; -+ -+typedef enum _devBoardModuleIdClass -+{ -+ MV_BOARD_MODULE_TDM_ID = 1, -+ MV_BOARD_MODULE_AUDIO_ID, -+ MV_BOARD_MODULE_RGMII_ID, -+ MV_BOARD_MODULE_GMII_ID, -+ MV_BOARD_MODULE_TS_ID, -+ MV_BOARD_MODULE_MII_ID, -+ MV_BOARD_MODULE_TDM_5CHAN_ID, -+ MV_BOARD_MODULE_OTHER_ID -+}MV_BOARD_MODULE_ID_CLASS; -+ -+typedef struct _boardMppTypeInfo -+{ -+ MV_BOARD_MPP_TYPE_CLASS boardMppGroup1; -+ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2; -+ -+}MV_BOARD_MPP_TYPE_INFO; -+ -+ -+typedef enum _devBoardClass -+{ -+ BOARD_DEV_NOR_FLASH, -+ BOARD_DEV_NAND_FLASH, -+ BOARD_DEV_SEVEN_SEG, -+ BOARD_DEV_FPGA, -+ BOARD_DEV_SRAM, -+ BOARD_DEV_SPI_FLASH, -+ BOARD_DEV_OTHER, -+}MV_BOARD_DEV_CLASS; -+ -+typedef enum _devTwsiBoardClass -+{ -+ BOARD_TWSI_RTC, -+ BOARD_DEV_TWSI_EXP, -+ BOARD_DEV_TWSI_SATR, -+ BOARD_TWSI_AUDIO_DEC, -+ BOARD_TWSI_OTHER -+}MV_BOARD_TWSI_CLASS; -+ -+typedef enum _devGppBoardClass -+{ -+ BOARD_GPP_RTC, -+ BOARD_GPP_MV_SWITCH, -+ BOARD_GPP_USB_VBUS, -+ BOARD_GPP_USB_VBUS_EN, -+ BOARD_GPP_USB_OC, -+ BOARD_GPP_USB_HOST_DEVICE, -+ BOARD_GPP_REF_CLCK, -+ BOARD_GPP_VOIP_SLIC, -+ BOARD_GPP_LIFELINE, -+ BOARD_GPP_BUTTON, -+ BOARD_GPP_TS_BUTTON_C, -+ BOARD_GPP_TS_BUTTON_U, -+ BOARD_GPP_TS_BUTTON_D, -+ BOARD_GPP_TS_BUTTON_L, -+ BOARD_GPP_TS_BUTTON_R, -+ BOARD_GPP_POWER_BUTTON, -+ BOARD_GPP_RESTOR_BUTTON, -+ BOARD_GPP_WPS_BUTTON, -+ BOARD_GPP_HDD0_POWER, -+ BOARD_GPP_HDD1_POWER, -+ BOARD_GPP_FAN_POWER, -+ BOARD_GPP_RESET, -+ BOARD_GPP_POWER_ON_LED, -+ BOARD_GPP_HDD_POWER, -+ BOARD_GPP_SDIO_POWER, -+ BOARD_GPP_SDIO_DETECT, -+ BOARD_GPP_SDIO_WP, -+ BOARD_GPP_SWITCH_PHY_INT, -+ BOARD_GPP_TSU_DIRCTION, -+ BOARD_GPP_OTHER -+}MV_BOARD_GPP_CLASS; -+ -+ -+typedef struct _devCsInfo -+{ -+ MV_U8 deviceCS; -+ MV_U32 params; -+ MV_U32 devClass; /* MV_BOARD_DEV_CLASS */ -+ MV_U8 devWidth; -+ -+}MV_DEV_CS_INFO; -+ -+ -+#define MV_BOARD_PHY_FORCE_10MB 0x0 -+#define MV_BOARD_PHY_FORCE_100MB 0x1 -+#define MV_BOARD_PHY_FORCE_1000MB 0x2 -+#define MV_BOARD_PHY_SPEED_AUTO 0x3 -+ -+typedef struct _boardSwitchInfo -+{ -+ MV_32 linkStatusIrq; -+ MV_32 qdPort[BOARD_ETH_SWITCH_PORT_NUM]; -+ MV_32 qdCpuPort; -+ MV_32 smiScanMode; /* 1 for SMI_MANUAL_MODE, 0 otherwise */ -+ MV_32 switchOnPort; -+ -+}MV_BOARD_SWITCH_INFO; -+ -+typedef struct _boardLedInfo -+{ -+ MV_U8 activeLedsNumber; -+ MV_U8 ledsPolarity; /* '0' or '1' to turn on led */ -+ MV_U8* gppPinNum; /* Pointer to GPP values */ -+ -+}MV_BOARD_LED_INFO; -+ -+typedef struct _boardGppInfo -+{ -+ MV_BOARD_GPP_CLASS devClass; -+ MV_U8 gppPinNum; -+ -+}MV_BOARD_GPP_INFO; -+ -+ -+typedef struct _boardTwsiInfo -+{ -+ MV_BOARD_TWSI_CLASS devClass; -+ MV_U8 twsiDevAddr; -+ MV_U8 twsiDevAddrType; -+ -+}MV_BOARD_TWSI_INFO; -+ -+ -+typedef enum _boardMacSpeed -+{ -+ BOARD_MAC_SPEED_10M, -+ BOARD_MAC_SPEED_100M, -+ BOARD_MAC_SPEED_1000M, -+ BOARD_MAC_SPEED_AUTO, -+ -+}MV_BOARD_MAC_SPEED; -+ -+typedef struct _boardMacInfo -+{ -+ MV_BOARD_MAC_SPEED boardMacSpeed; -+ MV_U8 boardEthSmiAddr; -+ -+}MV_BOARD_MAC_INFO; -+ -+typedef struct _boardMppInfo -+{ -+ MV_U32 mppGroup[MV_BOARD_MAX_MPP]; -+ -+}MV_BOARD_MPP_INFO; -+ -+typedef struct _boardInfo -+{ -+ char boardName[MV_BOARD_NAME_LEN]; -+ MV_U8 numBoardMppTypeValue; -+ MV_BOARD_MPP_TYPE_INFO* pBoardMppTypeValue; -+ MV_U8 numBoardMppConfigValue; -+ MV_BOARD_MPP_INFO* pBoardMppConfigValue; -+ MV_U32 intsGppMaskLow; -+ MV_U32 intsGppMaskHigh; -+ MV_U8 numBoardDeviceIf; -+ MV_DEV_CS_INFO* pDevCsInfo; -+ MV_U8 numBoardTwsiDev; -+ MV_BOARD_TWSI_INFO* pBoardTwsiDev; -+ MV_U8 numBoardMacInfo; -+ MV_BOARD_MAC_INFO* pBoardMacInfo; -+ MV_U8 numBoardGppInfo; -+ MV_BOARD_GPP_INFO* pBoardGppInfo; -+ MV_U8 activeLedsNumber; -+ MV_U8* pLedGppPin; -+ MV_U8 ledsPolarity; /* '0' or '1' to turn on led */ -+ /* GPP values */ -+ MV_U32 gppOutEnValLow; -+ MV_U32 gppOutEnValHigh; -+ MV_U32 gppOutValLow; -+ MV_U32 gppOutValHigh; -+ MV_U32 gppPolarityValLow; -+ MV_U32 gppPolarityValHigh; -+ -+ /* Switch Configuration */ -+ MV_BOARD_SWITCH_INFO* pSwitchInfo; -+}MV_BOARD_INFO; -+ -+ -+ -+MV_VOID mvBoardEnvInit(MV_VOID); -+MV_U32 mvBoardIdGet(MV_VOID); -+MV_U16 mvBoardModelGet(MV_VOID); -+MV_U16 mvBoardRevGet(MV_VOID); -+MV_STATUS mvBoardNameGet(char *pNameBuff); -+MV_32 mvBoardPhyAddrGet(MV_U32 ethPortNum); -+MV_BOARD_MAC_SPEED mvBoardMacSpeedGet(MV_U32 ethPortNum); -+MV_32 mvBoardLinkStatusIrqGet(MV_U32 ethPortNum); -+MV_32 mvBoardSwitchPortGet(MV_U32 ethPortNum, MV_U8 boardPortNum); -+MV_32 mvBoardSwitchCpuPortGet(MV_U32 ethPortNum); -+MV_32 mvBoardIsSwitchConnected(MV_U32 ethPortNum); -+MV_32 mvBoardSmiScanModeGet(MV_U32 ethPortNum); -+MV_BOOL mvBoardIsPortInSgmii(MV_U32 ethPortNum); -+MV_BOOL mvBoardIsPortInGmii(MV_VOID); -+MV_U32 mvBoardTclkGet(MV_VOID); -+MV_U32 mvBoardSysClkGet(MV_VOID); -+MV_U32 mvBoardDebugLedNumGet(MV_U32 boardId); -+MV_VOID mvBoardDebugLed(MV_U32 hexNum); -+MV_32 mvBoardMppGet(MV_U32 mppGroupNum); -+ -+MV_U8 mvBoardRtcTwsiAddrTypeGet(MV_VOID); -+MV_U8 mvBoardRtcTwsiAddrGet(MV_VOID); -+ -+MV_U8 mvBoardA2DTwsiAddrTypeGet(MV_VOID); -+MV_U8 mvBoardA2DTwsiAddrGet(MV_VOID); -+ -+MV_U8 mvBoardTwsiExpAddrGet(MV_U32 index); -+MV_U8 mvBoardTwsiSatRAddrTypeGet(MV_U32 index); -+MV_U8 mvBoardTwsiSatRAddrGet(MV_U32 index); -+MV_U8 mvBoardTwsiExpAddrTypeGet(MV_U32 index); -+MV_BOARD_MODULE_ID_CLASS mvBoarModuleTypeGet(MV_BOARD_MPP_GROUP_CLASS devClass); -+MV_BOARD_MPP_TYPE_CLASS mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass); -+MV_VOID mvBoardMppGroupTypeSet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass, -+ MV_BOARD_MPP_TYPE_CLASS mppGroupType); -+MV_VOID mvBoardMppGroupIdUpdate(MV_VOID); -+MV_VOID mvBoardMppMuxSet(MV_VOID); -+MV_VOID mvBoardTdmMppSet(MV_32 chType); -+MV_VOID mvBoardVoiceConnModeGet(MV_32* connMode, MV_32* irqMode); -+ -+MV_VOID mvBoardMppModuleTypePrint(MV_VOID); -+MV_VOID mvBoardReset(MV_VOID); -+MV_U8 mvBoarTwsiSatRGet(MV_U8 devNum, MV_U8 regNum); -+MV_STATUS mvBoarTwsiSatRSet(MV_U8 devNum, MV_U8 regNum, MV_U8 regVal); -+MV_BOOL mvBoardSpecInitGet(MV_U32* regOff, MV_U32* data); -+/* Board devices API managments */ -+MV_32 mvBoardGetDevicesNumber(MV_BOARD_DEV_CLASS devClass); -+MV_32 mvBoardGetDeviceBaseAddr(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); -+MV_32 mvBoardGetDeviceBusWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); -+MV_32 mvBoardGetDeviceWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); -+MV_32 mvBoardGetDeviceWinSize(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); -+MV_U32 boardGetDevCSNum(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); -+ -+/* Gpio Pin Connections API */ -+MV_32 mvBoardUSBVbusGpioPinGet(int devId); -+MV_32 mvBoardUSBVbusEnGpioPinGet(int devId); -+MV_U32 mvBoardPexBridgeIntPinGet(MV_U32 devNum, MV_U32 intPin); -+ -+MV_32 mvBoardResetGpioPinGet(MV_VOID); -+MV_32 mvBoardRTCGpioPinGet(MV_VOID); -+MV_32 mvBoardGpioIntMaskLowGet(MV_VOID); -+MV_32 mvBoardGpioIntMaskHighGet(MV_VOID); -+MV_32 mvBoardSlicGpioPinGet(MV_U32 slicNum); -+ -+MV_32 mvBoardSDIOGpioPinGet(MV_VOID); -+MV_STATUS mvBoardSDioWPControl(MV_BOOL mode); -+MV_32 mvBoarGpioPinNumGet(MV_BOARD_GPP_CLASS class, MV_U32 index); -+ -+MV_32 mvBoardNandWidthGet(void); -+MV_STATUS mvBoardFanPowerControl(MV_BOOL mode); -+MV_STATUS mvBoardHDDPowerControl(MV_BOOL mode); -+#endif /* __INCmvBoardEnvLibh */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c 2010-11-09 20:28:07.443751783 +0100 -@@ -0,0 +1,848 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#include "mvCommon.h" -+#include "mvBoardEnvLib.h" -+#include "mvBoardEnvSpec.h" -+#include "twsi/mvTwsi.h" -+ -+#define DB_88F6281A_BOARD_PCI_IF_NUM 0x0 -+#define DB_88F6281A_BOARD_TWSI_DEF_NUM 0x7 -+#define DB_88F6281A_BOARD_MAC_INFO_NUM 0x2 -+#define DB_88F6281A_BOARD_GPP_INFO_NUM 0x3 -+#define DB_88F6281A_BOARD_MPP_CONFIG_NUM 0x1 -+#define DB_88F6281A_BOARD_MPP_GROUP_TYPE_NUM 0x1 -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ #define DB_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1 -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ #define DB_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x2 -+#else -+ #define DB_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1 -+#endif -+#define DB_88F6281A_BOARD_DEBUG_LED_NUM 0x0 -+ -+ -+MV_BOARD_TWSI_INFO db88f6281AInfoBoardTwsiDev[] = -+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ -+ { -+ {BOARD_DEV_TWSI_EXP, 0x20, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_EXP, 0x21, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_SATR, 0x4D, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_SATR, 0x4E, ADDR7_BIT}, -+ {BOARD_TWSI_AUDIO_DEC, 0x4A, ADDR7_BIT} -+ }; -+ -+MV_BOARD_MAC_INFO db88f6281AInfoBoardMacInfo[] = -+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ -+ { -+ {BOARD_MAC_SPEED_AUTO, 0x8}, -+ {BOARD_MAC_SPEED_AUTO, 0x9} -+ }; -+ -+MV_BOARD_MPP_TYPE_INFO db88f6281AInfoBoardMppTypeInfo[] = -+ /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, -+ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ -+ {{MV_BOARD_AUTO, MV_BOARD_AUTO} -+ }; -+ -+MV_BOARD_GPP_INFO db88f6281AInfoBoardGppInfo[] = -+ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ -+ { -+ {BOARD_GPP_TSU_DIRCTION, 33} -+ /*muxed with TDM/Audio module via IOexpender -+ {BOARD_GPP_SDIO_DETECT, 38}, -+ {BOARD_GPP_USB_VBUS, 49}*/ -+ }; -+ -+MV_DEV_CS_INFO db88f6281AInfoBoardDeCsInfo[] = -+ /*{deviceCS, params, devType, devWidth}*/ -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ { -+ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ -+ {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ -+ }; -+#else -+ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ -+#endif -+ -+MV_BOARD_MPP_INFO db88f6281AInfoBoardMppConfigValue[] = -+ {{{ -+ DB_88F6281A_MPP0_7, -+ DB_88F6281A_MPP8_15, -+ DB_88F6281A_MPP16_23, -+ DB_88F6281A_MPP24_31, -+ DB_88F6281A_MPP32_39, -+ DB_88F6281A_MPP40_47, -+ DB_88F6281A_MPP48_55 -+ }}}; -+ -+ -+MV_BOARD_INFO db88f6281AInfo = { -+ "DB-88F6281A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ -+ DB_88F6281A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ -+ db88f6281AInfoBoardMppTypeInfo, -+ DB_88F6281A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ db88f6281AInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ 0, /* intsGppMaskHigh */ -+ DB_88F6281A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ db88f6281AInfoBoardDeCsInfo, -+ DB_88F6281A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ db88f6281AInfoBoardTwsiDev, -+ DB_88F6281A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ db88f6281AInfoBoardMacInfo, -+ DB_88F6281A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ db88f6281AInfoBoardGppInfo, -+ DB_88F6281A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ NULL, -+ 0, /* ledsPolarity */ -+ DB_88F6281A_OE_LOW, /* gppOutEnLow */ -+ DB_88F6281A_OE_HIGH, /* gppOutEnHigh */ -+ DB_88F6281A_OE_VAL_LOW, /* gppOutValLow */ -+ DB_88F6281A_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ BIT6, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+ -+#define RD_88F6281A_BOARD_PCI_IF_NUM 0x0 -+#define RD_88F6281A_BOARD_TWSI_DEF_NUM 0x2 -+#define RD_88F6281A_BOARD_MAC_INFO_NUM 0x2 -+#define RD_88F6281A_BOARD_GPP_INFO_NUM 0x5 -+#define RD_88F6281A_BOARD_MPP_GROUP_TYPE_NUM 0x1 -+#define RD_88F6281A_BOARD_MPP_CONFIG_NUM 0x1 -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ #define RD_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1 -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ #define RD_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x2 -+#else -+ #define RD_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1 -+#endif -+#define RD_88F6281A_BOARD_DEBUG_LED_NUM 0x0 -+ -+MV_BOARD_MAC_INFO rd88f6281AInfoBoardMacInfo[] = -+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ -+ {{BOARD_MAC_SPEED_1000M, 0xa}, -+ {BOARD_MAC_SPEED_AUTO, 0xb} -+ }; -+ -+MV_BOARD_SWITCH_INFO rd88f6281AInfoBoardSwitchInfo[] = -+ /* MV_32 linkStatusIrq, {MV_32 qdPort0, MV_32 qdPort1, MV_32 qdPort2, MV_32 qdPort3, MV_32 qdPort4}, -+ MV_32 qdCpuPort, MV_32 smiScanMode, MV_32 switchOnPort} */ -+ {{38, {0, 1, 2, 3, -1}, 5, 2, 0}, -+ {-1, {-1}, -1, -1, -1}}; -+ -+MV_BOARD_TWSI_INFO rd88f6281AInfoBoardTwsiDev[] = -+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ -+ { -+ {BOARD_DEV_TWSI_EXP, 0xFF, ADDR7_BIT}, /* dummy entry to align with modules indexes */ -+ {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT} -+ }; -+ -+MV_BOARD_MPP_TYPE_INFO rd88f6281AInfoBoardMppTypeInfo[] = -+ {{MV_BOARD_RGMII, MV_BOARD_TDM} -+ }; -+ -+MV_DEV_CS_INFO rd88f6281AInfoBoardDeCsInfo[] = -+ /*{deviceCS, params, devType, devWidth}*/ -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ { -+ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ -+ {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ -+ }; -+#else -+ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ -+#endif -+ -+MV_BOARD_GPP_INFO rd88f6281AInfoBoardGppInfo[] = -+ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ -+ {{BOARD_GPP_SDIO_DETECT, 28}, -+ {BOARD_GPP_USB_OC, 29}, -+ {BOARD_GPP_WPS_BUTTON, 35}, -+ {BOARD_GPP_MV_SWITCH, 38}, -+ {BOARD_GPP_USB_VBUS, 49} -+ }; -+ -+MV_BOARD_MPP_INFO rd88f6281AInfoBoardMppConfigValue[] = -+ {{{ -+ RD_88F6281A_MPP0_7, -+ RD_88F6281A_MPP8_15, -+ RD_88F6281A_MPP16_23, -+ RD_88F6281A_MPP24_31, -+ RD_88F6281A_MPP32_39, -+ RD_88F6281A_MPP40_47, -+ RD_88F6281A_MPP48_55 -+ }}}; -+ -+MV_BOARD_INFO rd88f6281AInfo = { -+ "RD-88F6281A", /* boardName[MAX_BOARD_NAME_LEN] */ -+ RD_88F6281A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ -+ rd88f6281AInfoBoardMppTypeInfo, -+ RD_88F6281A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ rd88f6281AInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ (1 << 3), /* intsGppMaskHigh */ -+ RD_88F6281A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ rd88f6281AInfoBoardDeCsInfo, -+ RD_88F6281A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ rd88f6281AInfoBoardTwsiDev, -+ RD_88F6281A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ rd88f6281AInfoBoardMacInfo, -+ RD_88F6281A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ rd88f6281AInfoBoardGppInfo, -+ RD_88F6281A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ NULL, -+ 0, /* ledsPolarity */ -+ RD_88F6281A_OE_LOW, /* gppOutEnLow */ -+ RD_88F6281A_OE_HIGH, /* gppOutEnHigh */ -+ RD_88F6281A_OE_VAL_LOW, /* gppOutValLow */ -+ RD_88F6281A_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ BIT6, /* gppPolarityValHigh */ -+ rd88f6281AInfoBoardSwitchInfo /* pSwitchInfo */ -+}; -+ -+ -+#define DB_88F6192A_BOARD_PCI_IF_NUM 0x0 -+#define DB_88F6192A_BOARD_TWSI_DEF_NUM 0x7 -+#define DB_88F6192A_BOARD_MAC_INFO_NUM 0x2 -+#define DB_88F6192A_BOARD_GPP_INFO_NUM 0x3 -+#define DB_88F6192A_BOARD_MPP_GROUP_TYPE_NUM 0x1 -+#define DB_88F6192A_BOARD_MPP_CONFIG_NUM 0x1 -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ #define DB_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x1 -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ #define DB_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x2 -+#else -+ #define DB_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x1 -+#endif -+#define DB_88F6192A_BOARD_DEBUG_LED_NUM 0x0 -+ -+MV_BOARD_TWSI_INFO db88f6192AInfoBoardTwsiDev[] = -+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ -+ { -+ {BOARD_DEV_TWSI_EXP, 0x20, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_EXP, 0x21, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_SATR, 0x4D, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_SATR, 0x4E, ADDR7_BIT}, -+ {BOARD_TWSI_AUDIO_DEC, 0x4A, ADDR7_BIT} -+ }; -+ -+MV_BOARD_MAC_INFO db88f6192AInfoBoardMacInfo[] = -+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ -+ { -+ {BOARD_MAC_SPEED_AUTO, 0x8}, -+ {BOARD_MAC_SPEED_AUTO, 0x9} -+ }; -+ -+MV_BOARD_MPP_TYPE_INFO db88f6192AInfoBoardMppTypeInfo[] = -+ /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, -+ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ -+ {{MV_BOARD_AUTO, MV_BOARD_OTHER} -+ }; -+ -+MV_DEV_CS_INFO db88f6192AInfoBoardDeCsInfo[] = -+ /*{deviceCS, params, devType, devWidth}*/ -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ { -+ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ -+ {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ -+ }; -+#else -+ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ -+#endif -+ -+MV_BOARD_GPP_INFO db88f6192AInfoBoardGppInfo[] = -+ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ -+ { -+ {BOARD_GPP_SDIO_WP, 20}, -+ {BOARD_GPP_USB_VBUS, 22}, -+ {BOARD_GPP_SDIO_DETECT, 23}, -+ }; -+ -+MV_BOARD_MPP_INFO db88f6192AInfoBoardMppConfigValue[] = -+ {{{ -+ DB_88F6192A_MPP0_7, -+ DB_88F6192A_MPP8_15, -+ DB_88F6192A_MPP16_23, -+ DB_88F6192A_MPP24_31, -+ DB_88F6192A_MPP32_35 -+ }}}; -+ -+MV_BOARD_INFO db88f6192AInfo = { -+ "DB-88F6192A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ -+ DB_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ -+ db88f6192AInfoBoardMppTypeInfo, -+ DB_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ db88f6192AInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ (1 << 3), /* intsGppMaskHigh */ -+ DB_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ db88f6192AInfoBoardDeCsInfo, -+ DB_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ db88f6192AInfoBoardTwsiDev, -+ DB_88F6192A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ db88f6192AInfoBoardMacInfo, -+ DB_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ db88f6192AInfoBoardGppInfo, -+ DB_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ NULL, -+ 0, /* ledsPolarity */ -+ DB_88F6192A_OE_LOW, /* gppOutEnLow */ -+ DB_88F6192A_OE_HIGH, /* gppOutEnHigh */ -+ DB_88F6192A_OE_VAL_LOW, /* gppOutValLow */ -+ DB_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ 0, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+#define DB_88F6190A_BOARD_MAC_INFO_NUM 0x1 -+ -+MV_BOARD_INFO db88f6190AInfo = { -+ "DB-88F6190A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ -+ DB_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ -+ db88f6192AInfoBoardMppTypeInfo, -+ DB_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ db88f6192AInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ (1 << 3), /* intsGppMaskHigh */ -+ DB_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ db88f6192AInfoBoardDeCsInfo, -+ DB_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ db88f6192AInfoBoardTwsiDev, -+ DB_88F6190A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ db88f6192AInfoBoardMacInfo, -+ DB_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ db88f6192AInfoBoardGppInfo, -+ DB_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ NULL, -+ 0, /* ledsPolarity */ -+ DB_88F6192A_OE_LOW, /* gppOutEnLow */ -+ DB_88F6192A_OE_HIGH, /* gppOutEnHigh */ -+ DB_88F6192A_OE_VAL_LOW, /* gppOutValLow */ -+ DB_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ 0, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+#define RD_88F6192A_BOARD_PCI_IF_NUM 0x0 -+#define RD_88F6192A_BOARD_TWSI_DEF_NUM 0x0 -+#define RD_88F6192A_BOARD_MAC_INFO_NUM 0x1 -+#define RD_88F6192A_BOARD_GPP_INFO_NUM 0xE -+#define RD_88F6192A_BOARD_MPP_GROUP_TYPE_NUM 0x1 -+#define RD_88F6192A_BOARD_MPP_CONFIG_NUM 0x1 -+#define RD_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x1 -+#define RD_88F6192A_BOARD_DEBUG_LED_NUM 0x3 -+ -+MV_U8 rd88f6192AInfoBoardDebugLedIf[] = -+ {17, 28, 29}; -+ -+MV_BOARD_MAC_INFO rd88f6192AInfoBoardMacInfo[] = -+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ -+ {{BOARD_MAC_SPEED_AUTO, 0x8} -+ }; -+ -+MV_BOARD_MPP_TYPE_INFO rd88f6192AInfoBoardMppTypeInfo[] = -+ /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, -+ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ -+ {{MV_BOARD_OTHER, MV_BOARD_OTHER} -+ }; -+ -+MV_DEV_CS_INFO rd88f6192AInfoBoardDeCsInfo[] = -+ /*{deviceCS, params, devType, devWidth}*/ -+ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ -+ -+MV_BOARD_GPP_INFO rd88f6192AInfoBoardGppInfo[] = -+ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ -+ { -+ {BOARD_GPP_USB_VBUS_EN, 10}, -+ {BOARD_GPP_USB_HOST_DEVICE, 11}, -+ {BOARD_GPP_RESET, 14}, -+ {BOARD_GPP_POWER_ON_LED, 15}, -+ {BOARD_GPP_HDD_POWER, 16}, -+ {BOARD_GPP_WPS_BUTTON, 24}, -+ {BOARD_GPP_TS_BUTTON_C, 25}, -+ {BOARD_GPP_USB_VBUS, 26}, -+ {BOARD_GPP_USB_OC, 27}, -+ {BOARD_GPP_TS_BUTTON_U, 30}, -+ {BOARD_GPP_TS_BUTTON_R, 31}, -+ {BOARD_GPP_TS_BUTTON_L, 32}, -+ {BOARD_GPP_TS_BUTTON_D, 34}, -+ {BOARD_GPP_FAN_POWER, 35} -+ }; -+ -+MV_BOARD_MPP_INFO rd88f6192AInfoBoardMppConfigValue[] = -+ {{{ -+ RD_88F6192A_MPP0_7, -+ RD_88F6192A_MPP8_15, -+ RD_88F6192A_MPP16_23, -+ RD_88F6192A_MPP24_31, -+ RD_88F6192A_MPP32_35 -+ }}}; -+ -+MV_BOARD_INFO rd88f6192AInfo = { -+ "RD-88F6192A-NAS", /* boardName[MAX_BOARD_NAME_LEN] */ -+ RD_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ -+ rd88f6192AInfoBoardMppTypeInfo, -+ RD_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ rd88f6192AInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ (1 << 3), /* intsGppMaskHigh */ -+ RD_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ rd88f6192AInfoBoardDeCsInfo, -+ RD_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ NULL, -+ RD_88F6192A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ rd88f6192AInfoBoardMacInfo, -+ RD_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ rd88f6192AInfoBoardGppInfo, -+ RD_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ rd88f6192AInfoBoardDebugLedIf, -+ 0, /* ledsPolarity */ -+ RD_88F6192A_OE_LOW, /* gppOutEnLow */ -+ RD_88F6192A_OE_HIGH, /* gppOutEnHigh */ -+ RD_88F6192A_OE_VAL_LOW, /* gppOutValLow */ -+ RD_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ 0, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+MV_BOARD_INFO rd88f6190AInfo = { -+ "RD-88F6190A-NAS", /* boardName[MAX_BOARD_NAME_LEN] */ -+ RD_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ -+ rd88f6192AInfoBoardMppTypeInfo, -+ RD_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ rd88f6192AInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ (1 << 3), /* intsGppMaskHigh */ -+ RD_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ rd88f6192AInfoBoardDeCsInfo, -+ RD_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ NULL, -+ RD_88F6192A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ rd88f6192AInfoBoardMacInfo, -+ RD_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ rd88f6192AInfoBoardGppInfo, -+ RD_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ rd88f6192AInfoBoardDebugLedIf, -+ 0, /* ledsPolarity */ -+ RD_88F6192A_OE_LOW, /* gppOutEnLow */ -+ RD_88F6192A_OE_HIGH, /* gppOutEnHigh */ -+ RD_88F6192A_OE_VAL_LOW, /* gppOutValLow */ -+ RD_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ 0, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+#define DB_88F6180A_BOARD_PCI_IF_NUM 0x0 -+#define DB_88F6180A_BOARD_TWSI_DEF_NUM 0x5 -+#define DB_88F6180A_BOARD_MAC_INFO_NUM 0x1 -+#define DB_88F6180A_BOARD_GPP_INFO_NUM 0x0 -+#define DB_88F6180A_BOARD_MPP_GROUP_TYPE_NUM 0x2 -+#define DB_88F6180A_BOARD_MPP_CONFIG_NUM 0x1 -+#define DB_88F6180A_BOARD_DEVICE_CONFIG_NUM 0x1 -+#define DB_88F6180A_BOARD_DEBUG_LED_NUM 0x0 -+ -+MV_BOARD_TWSI_INFO db88f6180AInfoBoardTwsiDev[] = -+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ -+ { -+ {BOARD_DEV_TWSI_EXP, 0x20, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_EXP, 0x21, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, -+ {BOARD_TWSI_AUDIO_DEC, 0x4A, ADDR7_BIT} -+ }; -+ -+MV_BOARD_MAC_INFO db88f6180AInfoBoardMacInfo[] = -+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ -+ {{BOARD_MAC_SPEED_AUTO, 0x8} -+ }; -+ -+MV_BOARD_GPP_INFO db88f6180AInfoBoardGppInfo[] = -+ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ -+ { -+ /* Muxed with TDM/Audio module via IOexpender -+ {BOARD_GPP_USB_VBUS, 6} */ -+ }; -+ -+MV_BOARD_MPP_TYPE_INFO db88f6180AInfoBoardMppTypeInfo[] = -+ /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, -+ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ -+ {{MV_BOARD_OTHER, MV_BOARD_AUTO} -+ }; -+ -+MV_DEV_CS_INFO db88f6180AInfoBoardDeCsInfo[] = -+ /*{deviceCS, params, devType, devWidth}*/ -+#if defined(MV_NAND_BOOT) -+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ -+#else -+ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ -+#endif -+ -+MV_BOARD_MPP_INFO db88f6180AInfoBoardMppConfigValue[] = -+ {{{ -+ DB_88F6180A_MPP0_7, -+ DB_88F6180A_MPP8_15, -+ DB_88F6180A_MPP16_23, -+ DB_88F6180A_MPP24_31, -+ DB_88F6180A_MPP32_39, -+ DB_88F6180A_MPP40_44 -+ }}}; -+ -+MV_BOARD_INFO db88f6180AInfo = { -+ "DB-88F6180A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ -+ DB_88F6180A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ -+ db88f6180AInfoBoardMppTypeInfo, -+ DB_88F6180A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ db88f6180AInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ 0, /* intsGppMaskHigh */ -+ DB_88F6180A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ db88f6180AInfoBoardDeCsInfo, -+ DB_88F6180A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ db88f6180AInfoBoardTwsiDev, -+ DB_88F6180A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ db88f6180AInfoBoardMacInfo, -+ DB_88F6180A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ NULL, -+ DB_88F6180A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ NULL, -+ 0, /* ledsPolarity */ -+ DB_88F6180A_OE_LOW, /* gppOutEnLow */ -+ DB_88F6180A_OE_HIGH, /* gppOutEnHigh */ -+ DB_88F6180A_OE_VAL_LOW, /* gppOutValLow */ -+ DB_88F6180A_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ 0, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+ -+#define RD_88F6281A_PCAC_BOARD_PCI_IF_NUM 0x0 -+#define RD_88F6281A_PCAC_BOARD_TWSI_DEF_NUM 0x1 -+#define RD_88F6281A_PCAC_BOARD_MAC_INFO_NUM 0x1 -+#define RD_88F6281A_PCAC_BOARD_GPP_INFO_NUM 0x0 -+#define RD_88F6281A_PCAC_BOARD_MPP_GROUP_TYPE_NUM 0x1 -+#define RD_88F6281A_PCAC_BOARD_MPP_CONFIG_NUM 0x1 -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ #define RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM 0x1 -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ #define RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM 0x2 -+#else -+ #define RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM 0x1 -+#endif -+#define RD_88F6281A_PCAC_BOARD_DEBUG_LED_NUM 0x4 -+ -+MV_U8 rd88f6281APcacInfoBoardDebugLedIf[] = -+ {38, 39, 40, 41}; -+ -+MV_BOARD_MAC_INFO rd88f6281APcacInfoBoardMacInfo[] = -+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ -+ {{BOARD_MAC_SPEED_AUTO, 0x8} -+ }; -+ -+MV_BOARD_TWSI_INFO rd88f6281APcacInfoBoardTwsiDev[] = -+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ -+ { -+ {BOARD_TWSI_OTHER, 0xa7, ADDR7_BIT} -+ }; -+ -+MV_BOARD_MPP_TYPE_INFO rd88f6281APcacInfoBoardMppTypeInfo[] = -+ {{MV_BOARD_OTHER, MV_BOARD_OTHER} -+ }; -+ -+MV_DEV_CS_INFO rd88f6281APcacInfoBoardDeCsInfo[] = -+ /*{deviceCS, params, devType, devWidth}*/ -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ { -+ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ -+ {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ -+ }; -+#else -+ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ -+#endif -+ -+MV_BOARD_MPP_INFO rd88f6281APcacInfoBoardMppConfigValue[] = -+ {{{ -+ RD_88F6281A_PCAC_MPP0_7, -+ RD_88F6281A_PCAC_MPP8_15, -+ RD_88F6281A_PCAC_MPP16_23, -+ RD_88F6281A_PCAC_MPP24_31, -+ RD_88F6281A_PCAC_MPP32_39, -+ RD_88F6281A_PCAC_MPP40_47, -+ RD_88F6281A_PCAC_MPP48_55 -+ }}}; -+ -+MV_BOARD_INFO rd88f6281APcacInfo = { -+ "RD-88F6281A-PCAC", /* boardName[MAX_BOARD_NAME_LEN] */ -+ RD_88F6281A_PCAC_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ -+ rd88f6281APcacInfoBoardMppTypeInfo, -+ RD_88F6281A_PCAC_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ rd88f6281APcacInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ (1 << 3), /* intsGppMaskHigh */ -+ RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ rd88f6281APcacInfoBoardDeCsInfo, -+ RD_88F6281A_PCAC_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ rd88f6281APcacInfoBoardTwsiDev, -+ RD_88F6281A_PCAC_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ rd88f6281APcacInfoBoardMacInfo, -+ RD_88F6281A_PCAC_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ 0, -+ RD_88F6281A_PCAC_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ NULL, -+ 0, /* ledsPolarity */ -+ RD_88F6281A_PCAC_OE_LOW, /* gppOutEnLow */ -+ RD_88F6281A_PCAC_OE_HIGH, /* gppOutEnHigh */ -+ RD_88F6281A_PCAC_OE_VAL_LOW, /* gppOutValLow */ -+ RD_88F6281A_PCAC_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ 0, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+ -+/* 6281 Sheeva Plug*/ -+ -+#define SHEEVA_PLUG_BOARD_PCI_IF_NUM 0x0 -+#define SHEEVA_PLUG_BOARD_TWSI_DEF_NUM 0x0 -+#define SHEEVA_PLUG_BOARD_MAC_INFO_NUM 0x1 -+#define SHEEVA_PLUG_BOARD_GPP_INFO_NUM 0x0 -+#define SHEEVA_PLUG_BOARD_MPP_GROUP_TYPE_NUN 0x1 -+#define SHEEVA_PLUG_BOARD_MPP_CONFIG_NUM 0x1 -+#define SHEEVA_PLUG_BOARD_DEVICE_CONFIG_NUM 0x1 -+#define SHEEVA_PLUG_BOARD_DEBUG_LED_NUM 0x1 -+ -+MV_U8 sheevaPlugInfoBoardDebugLedIf[] = -+ {49}; -+ -+MV_BOARD_MAC_INFO sheevaPlugInfoBoardMacInfo[] = -+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ -+ {{BOARD_MAC_SPEED_AUTO, 0x0}}; -+ -+MV_BOARD_TWSI_INFO sheevaPlugInfoBoardTwsiDev[] = -+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ -+ {{BOARD_TWSI_OTHER, 0x0, ADDR7_BIT}}; -+ -+MV_BOARD_MPP_TYPE_INFO sheevaPlugInfoBoardMppTypeInfo[] = -+ {{MV_BOARD_OTHER, MV_BOARD_OTHER} -+ }; -+ -+MV_DEV_CS_INFO sheevaPlugInfoBoardDeCsInfo[] = -+ /*{deviceCS, params, devType, devWidth}*/ -+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ -+ -+MV_BOARD_MPP_INFO sheevaPlugInfoBoardMppConfigValue[] = -+ {{{ -+ RD_SHEEVA_PLUG_MPP0_7, -+ RD_SHEEVA_PLUG_MPP8_15, -+ RD_SHEEVA_PLUG_MPP16_23, -+ RD_SHEEVA_PLUG_MPP24_31, -+ RD_SHEEVA_PLUG_MPP32_39, -+ RD_SHEEVA_PLUG_MPP40_47, -+ RD_SHEEVA_PLUG_MPP48_55 -+ }}}; -+ -+MV_BOARD_INFO sheevaPlugInfo = { -+ "SHEEVA PLUG", /* boardName[MAX_BOARD_NAME_LEN] */ -+ SHEEVA_PLUG_BOARD_MPP_GROUP_TYPE_NUN, /* numBoardMppGroupType */ -+ sheevaPlugInfoBoardMppTypeInfo, -+ SHEEVA_PLUG_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ sheevaPlugInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ 0, /* intsGppMaskHigh */ -+ SHEEVA_PLUG_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ sheevaPlugInfoBoardDeCsInfo, -+ SHEEVA_PLUG_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ sheevaPlugInfoBoardTwsiDev, -+ SHEEVA_PLUG_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ sheevaPlugInfoBoardMacInfo, -+ SHEEVA_PLUG_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ 0, -+ SHEEVA_PLUG_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ sheevaPlugInfoBoardDebugLedIf, -+ 0, /* ledsPolarity */ -+ RD_SHEEVA_PLUG_OE_LOW, /* gppOutEnLow */ -+ RD_SHEEVA_PLUG_OE_HIGH, /* gppOutEnHigh */ -+ RD_SHEEVA_PLUG_OE_VAL_LOW, /* gppOutValLow */ -+ RD_SHEEVA_PLUG_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ 0, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+/* Customer specific board place holder*/ -+ -+#define DB_CUSTOMER_BOARD_PCI_IF_NUM 0x0 -+#define DB_CUSTOMER_BOARD_TWSI_DEF_NUM 0x0 -+#define DB_CUSTOMER_BOARD_MAC_INFO_NUM 0x0 -+#define DB_CUSTOMER_BOARD_GPP_INFO_NUM 0x0 -+#define DB_CUSTOMER_BOARD_MPP_GROUP_TYPE_NUN 0x0 -+#define DB_CUSTOMER_BOARD_MPP_CONFIG_NUM 0x0 -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ #define DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM 0x0 -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ #define DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM 0x0 -+#else -+ #define DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM 0x0 -+#endif -+#define DB_CUSTOMER_BOARD_DEBUG_LED_NUM 0x0 -+ -+MV_U8 dbCustomerInfoBoardDebugLedIf[] = -+ {0}; -+ -+MV_BOARD_MAC_INFO dbCustomerInfoBoardMacInfo[] = -+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ -+ {{BOARD_MAC_SPEED_AUTO, 0x0}}; -+ -+MV_BOARD_TWSI_INFO dbCustomerInfoBoardTwsiDev[] = -+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ -+ {{BOARD_TWSI_OTHER, 0x0, ADDR7_BIT}}; -+ -+MV_BOARD_MPP_TYPE_INFO dbCustomerInfoBoardMppTypeInfo[] = -+ {{MV_BOARD_OTHER, MV_BOARD_OTHER} -+ }; -+ -+MV_DEV_CS_INFO dbCustomerInfoBoardDeCsInfo[] = -+ /*{deviceCS, params, devType, devWidth}*/ -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ { -+ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ -+ {2, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ -+ }; -+#else -+ {{2, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ -+#endif -+ -+MV_BOARD_MPP_INFO dbCustomerInfoBoardMppConfigValue[] = -+ {{{ -+ DB_CUSTOMER_MPP0_7, -+ DB_CUSTOMER_MPP8_15, -+ DB_CUSTOMER_MPP16_23, -+ DB_CUSTOMER_MPP24_31, -+ DB_CUSTOMER_MPP32_39, -+ DB_CUSTOMER_MPP40_47, -+ DB_CUSTOMER_MPP48_55 -+ }}}; -+ -+MV_BOARD_INFO dbCustomerInfo = { -+ "DB-CUSTOMER", /* boardName[MAX_BOARD_NAME_LEN] */ -+ DB_CUSTOMER_BOARD_MPP_GROUP_TYPE_NUN, /* numBoardMppGroupType */ -+ dbCustomerInfoBoardMppTypeInfo, -+ DB_CUSTOMER_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ dbCustomerInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ 0, /* intsGppMaskHigh */ -+ DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ dbCustomerInfoBoardDeCsInfo, -+ DB_CUSTOMER_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ dbCustomerInfoBoardTwsiDev, -+ DB_CUSTOMER_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ dbCustomerInfoBoardMacInfo, -+ DB_CUSTOMER_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ 0, -+ DB_CUSTOMER_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ NULL, -+ 0, /* ledsPolarity */ -+ DB_CUSTOMER_OE_LOW, /* gppOutEnLow */ -+ DB_CUSTOMER_OE_HIGH, /* gppOutEnHigh */ -+ DB_CUSTOMER_OE_VAL_LOW, /* gppOutValLow */ -+ DB_CUSTOMER_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ 0, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+MV_BOARD_INFO* boardInfoTbl[] = { -+ &db88f6281AInfo, -+ &rd88f6281AInfo, -+ &db88f6192AInfo, -+ &rd88f6192AInfo, -+ &db88f6180AInfo, -+ &db88f6190AInfo, -+ &rd88f6190AInfo, -+ &rd88f6281APcacInfo, -+ &dbCustomerInfo, -+ &sheevaPlugInfo -+ }; -+ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.h 2010-11-09 20:28:07.482495476 +0100 -@@ -0,0 +1,262 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvBoardEnvSpech -+#define __INCmvBoardEnvSpech -+ -+#include "mvSysHwConfig.h" -+ -+ -+/* For future use */ -+#define BD_ID_DATA_START_OFFS 0x0 -+#define BD_DETECT_SEQ_OFFS 0x0 -+#define BD_SYS_NUM_OFFS 0x4 -+#define BD_NAME_OFFS 0x8 -+ -+/* I2C bus addresses */ -+#define MV_BOARD_CTRL_I2C_ADDR 0x0 /* Controller slave addr */ -+#define MV_BOARD_CTRL_I2C_ADDR_TYPE ADDR7_BIT -+#define MV_BOARD_DIMM0_I2C_ADDR 0x56 -+#define MV_BOARD_DIMM0_I2C_ADDR_TYPE ADDR7_BIT -+#define MV_BOARD_DIMM1_I2C_ADDR 0x54 -+#define MV_BOARD_DIMM1_I2C_ADDR_TYPE ADDR7_BIT -+#define MV_BOARD_EEPROM_I2C_ADDR 0x51 -+#define MV_BOARD_EEPROM_I2C_ADDR_TYPE ADDR7_BIT -+#define MV_BOARD_MAIN_EEPROM_I2C_ADDR 0x50 -+#define MV_BOARD_MAIN_EEPROM_I2C_ADDR_TYPE ADDR7_BIT -+#define MV_BOARD_MUX_I2C_ADDR_ENTRY 0x2 -+#define MV_BOARD_DIMM_I2C_CHANNEL 0x0 -+ -+#define BOOT_FLASH_INDEX 0 -+#define MAIN_FLASH_INDEX 1 -+ -+#define BOARD_ETH_START_PORT_NUM 0 -+ -+/* Supported clocks */ -+#define MV_BOARD_TCLK_100MHZ 100000000 -+#define MV_BOARD_TCLK_125MHZ 125000000 -+#define MV_BOARD_TCLK_133MHZ 133333333 -+#define MV_BOARD_TCLK_150MHZ 150000000 -+#define MV_BOARD_TCLK_166MHZ 166666667 -+#define MV_BOARD_TCLK_200MHZ 200000000 -+ -+#define MV_BOARD_SYSCLK_100MHZ 100000000 -+#define MV_BOARD_SYSCLK_125MHZ 125000000 -+#define MV_BOARD_SYSCLK_133MHZ 133333333 -+#define MV_BOARD_SYSCLK_150MHZ 150000000 -+#define MV_BOARD_SYSCLK_166MHZ 166666667 -+#define MV_BOARD_SYSCLK_200MHZ 200000000 -+#define MV_BOARD_SYSCLK_233MHZ 233333333 -+#define MV_BOARD_SYSCLK_250MHZ 250000000 -+#define MV_BOARD_SYSCLK_267MHZ 266666667 -+#define MV_BOARD_SYSCLK_300MHZ 300000000 -+#define MV_BOARD_SYSCLK_333MHZ 333333334 -+#define MV_BOARD_SYSCLK_400MHZ 400000000 -+ -+#define MV_BOARD_REFCLK_25MHZ 25000000 -+ -+/* Board specific */ -+/* =============================== */ -+ -+/* boards ID numbers */ -+ -+#define BOARD_ID_BASE 0x0 -+ -+/* New board ID numbers */ -+#define DB_88F6281A_BP_ID (BOARD_ID_BASE) -+#define DB_88F6281_BP_MLL_ID 1680 -+#define RD_88F6281A_ID (BOARD_ID_BASE+0x1) -+#define RD_88F6281_MLL_ID 1682 -+#define DB_88F6192A_BP_ID (BOARD_ID_BASE+0x2) -+#define RD_88F6192A_ID (BOARD_ID_BASE+0x3) -+#define RD_88F6192_MLL_ID 1681 -+#define DB_88F6180A_BP_ID (BOARD_ID_BASE+0x4) -+#define DB_88F6190A_BP_ID (BOARD_ID_BASE+0x5) -+#define RD_88F6190A_ID (BOARD_ID_BASE+0x6) -+#define RD_88F6281A_PCAC_ID (BOARD_ID_BASE+0x7) -+#define DB_CUSTOMER_ID (BOARD_ID_BASE+0x8) -+#define SHEEVA_PLUG_ID (BOARD_ID_BASE+0x9) -+#define MV_MAX_BOARD_ID (SHEEVA_PLUG_ID + 1) -+ -+/* DB-88F6281A-BP */ -+#if defined(MV_NAND) -+ #define DB_88F6281A_MPP0_7 0x21111111 -+#else -+ #define DB_88F6281A_MPP0_7 0x21112220 -+#endif -+#define DB_88F6281A_MPP8_15 0x11113311 -+#define DB_88F6281A_MPP16_23 0x00551111 -+#define DB_88F6281A_MPP24_31 0x00000000 -+#define DB_88F6281A_MPP32_39 0x00000000 -+#define DB_88F6281A_MPP40_47 0x00000000 -+#define DB_88F6281A_MPP48_55 0x00000000 -+#define DB_88F6281A_OE_LOW 0x0 -+#if defined(MV_TDM_5CHANNELS) -+ #define DB_88F6281A_OE_HIGH (BIT6) -+#else -+#define DB_88F6281A_OE_HIGH 0x0 -+#endif -+#define DB_88F6281A_OE_VAL_LOW 0x0 -+#define DB_88F6281A_OE_VAL_HIGH 0x0 -+ -+/* RD-88F6281A */ -+#if defined(MV_NAND) -+ #define RD_88F6281A_MPP0_7 0x21111111 -+#else -+ #define RD_88F6281A_MPP0_7 0x21112220 -+#endif -+#define RD_88F6281A_MPP8_15 0x11113311 -+#define RD_88F6281A_MPP16_23 0x33331111 -+#define RD_88F6281A_MPP24_31 0x33003333 -+#define RD_88F6281A_MPP32_39 0x20440533 -+#define RD_88F6281A_MPP40_47 0x22202222 -+#define RD_88F6281A_MPP48_55 0x00000002 -+#define RD_88F6281A_OE_LOW (BIT28 | BIT29) -+#define RD_88F6281A_OE_HIGH (BIT3 | BIT6 | BIT17) -+#define RD_88F6281A_OE_VAL_LOW 0x0 -+#define RD_88F6281A_OE_VAL_HIGH 0x0 -+ -+/* DB-88F6192A-BP */ -+#if defined(MV_NAND) -+ #define DB_88F6192A_MPP0_7 0x21111111 -+#else -+ #define DB_88F6192A_MPP0_7 0x21112220 -+#endif -+#define DB_88F6192A_MPP8_15 0x11113311 -+#define DB_88F6192A_MPP16_23 0x00501111 -+#define DB_88F6192A_MPP24_31 0x00000000 -+#define DB_88F6192A_MPP32_35 0x00000000 -+#define DB_88F6192A_OE_LOW (BIT22 | BIT23) -+#define DB_88F6192A_OE_HIGH 0x0 -+#define DB_88F6192A_OE_VAL_LOW 0x0 -+#define DB_88F6192A_OE_VAL_HIGH 0x0 -+ -+/* RD-88F6192A */ -+#define RD_88F6192A_MPP0_7 0x01222222 -+#define RD_88F6192A_MPP8_15 0x00000011 -+#define RD_88F6192A_MPP16_23 0x05550000 -+#define RD_88F6192A_MPP24_31 0x0 -+#define RD_88F6192A_MPP32_35 0x0 -+#define RD_88F6192A_OE_LOW (BIT11 | BIT14 | BIT24 | BIT25 | BIT26 | BIT27 | BIT30 | BIT31) -+#define RD_88F6192A_OE_HIGH (BIT0 | BIT2) -+#define RD_88F6192A_OE_VAL_LOW 0x18400 -+#define RD_88F6192A_OE_VAL_HIGH 0x8 -+ -+/* DB-88F6180A-BP */ -+#if defined(MV_NAND) -+ #define DB_88F6180A_MPP0_7 0x21111111 -+#else -+ #define DB_88F6180A_MPP0_7 0x01112222 -+#endif -+#define DB_88F6180A_MPP8_15 0x11113311 -+#define DB_88F6180A_MPP16_23 0x00001111 -+#define DB_88F6180A_MPP24_31 0x0 -+#define DB_88F6180A_MPP32_39 0x4444c000 -+#define DB_88F6180A_MPP40_44 0x00044444 -+#define DB_88F6180A_OE_LOW 0x0 -+#define DB_88F6180A_OE_HIGH 0x0 -+#define DB_88F6180A_OE_VAL_LOW 0x0 -+#define DB_88F6180A_OE_VAL_HIGH 0x0 -+ -+/* RD-88F6281A_PCAC */ -+#define RD_88F6281A_PCAC_MPP0_7 0x21111111 -+#define RD_88F6281A_PCAC_MPP8_15 0x00003311 -+#define RD_88F6281A_PCAC_MPP16_23 0x00001100 -+#define RD_88F6281A_PCAC_MPP24_31 0x00000000 -+#define RD_88F6281A_PCAC_MPP32_39 0x00000000 -+#define RD_88F6281A_PCAC_MPP40_47 0x00000000 -+#define RD_88F6281A_PCAC_MPP48_55 0x00000000 -+#define RD_88F6281A_PCAC_OE_LOW 0x0 -+#define RD_88F6281A_PCAC_OE_HIGH 0x0 -+#define RD_88F6281A_PCAC_OE_VAL_LOW 0x0 -+#define RD_88F6281A_PCAC_OE_VAL_HIGH 0x0 -+ -+/* SHEEVA PLUG */ -+#define RD_SHEEVA_PLUG_MPP0_7 0x01111111 -+#define RD_SHEEVA_PLUG_MPP8_15 0x11113322 -+#define RD_SHEEVA_PLUG_MPP16_23 0x00001111 -+#define RD_SHEEVA_PLUG_MPP24_31 0x00100000 -+#define RD_SHEEVA_PLUG_MPP32_39 0x00000000 -+#define RD_SHEEVA_PLUG_MPP40_47 0x00000000 -+#define RD_SHEEVA_PLUG_MPP48_55 0x00000000 -+#define RD_SHEEVA_PLUG_OE_LOW 0x0 -+#define RD_SHEEVA_PLUG_OE_HIGH 0x0 -+#define RD_SHEEVA_PLUG_OE_VAL_LOW (BIT29) -+#define RD_SHEEVA_PLUG_OE_VAL_HIGH ((~(BIT17 | BIT16 | BIT15)) | BIT14) -+ -+/* DB-CUSTOMER */ -+#define DB_CUSTOMER_MPP0_7 0x21111111 -+#define DB_CUSTOMER_MPP8_15 0x00003311 -+#define DB_CUSTOMER_MPP16_23 0x00001100 -+#define DB_CUSTOMER_MPP24_31 0x00000000 -+#define DB_CUSTOMER_MPP32_39 0x00000000 -+#define DB_CUSTOMER_MPP40_47 0x00000000 -+#define DB_CUSTOMER_MPP48_55 0x00000000 -+#define DB_CUSTOMER_OE_LOW 0x0 -+#define DB_CUSTOMER_OE_HIGH (~((BIT6) | (BIT7) | (BIT8) | (BIT9))) -+#define DB_CUSTOMER_OE_VAL_LOW 0x0 -+#define DB_CUSTOMER_OE_VAL_HIGH 0x0 -+ -+#endif /* __INCmvBoardEnvSpech */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c 2010-11-09 20:28:07.522495500 +0100 -@@ -0,0 +1,320 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#include "cpu/mvCpu.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvRegs.h" -+#include "ctrlEnv/sys/mvCpuIfRegs.h" -+ -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+/* locals */ -+ -+/******************************************************************************* -+* mvCpuPclkGet - Get the CPU pClk (pipe clock) -+* -+* DESCRIPTION: -+* This routine extract the CPU core clock. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit clock cycles in MHertz. -+* -+*******************************************************************************/ -+/* 6180 have different clk reset sampling */ -+ -+static MV_U32 mvCpu6180PclkGet(MV_VOID) -+{ -+ MV_U32 tmpPClkRate=0; -+ MV_CPU_ARM_CLK cpu6180_ddr_l2_CLK[] = MV_CPU6180_DDR_L2_CLCK_TBL; -+ -+ tmpPClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ tmpPClkRate = tmpPClkRate & MSAR_CPUCLCK_MASK_6180; -+ tmpPClkRate = tmpPClkRate >> MSAR_CPUCLCK_OFFS_6180; -+ -+ tmpPClkRate = cpu6180_ddr_l2_CLK[tmpPClkRate].cpuClk; -+ -+ return tmpPClkRate; -+} -+ -+ -+MV_U32 mvCpuPclkGet(MV_VOID) -+{ -+#if defined(PCLCK_AUTO_DETECT) -+ MV_U32 tmpPClkRate=0; -+ MV_U32 cpuCLK[] = MV_CPU_CLCK_TBL; -+ -+ if(mvCtrlModelGet() == MV_6180_DEV_ID) -+ return mvCpu6180PclkGet(); -+ -+ tmpPClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ tmpPClkRate = MSAR_CPUCLCK_EXTRACT(tmpPClkRate); -+ tmpPClkRate = cpuCLK[tmpPClkRate]; -+ -+ return tmpPClkRate; -+#else -+ return MV_DEFAULT_PCLK -+#endif -+} -+ -+/******************************************************************************* -+* mvCpuL2ClkGet - Get the CPU L2 (CPU bus clock) -+* -+* DESCRIPTION: -+* This routine extract the CPU L2 clock. -+* -+* RETURN: -+* 32bit clock cycles in Hertz. -+* -+*******************************************************************************/ -+static MV_U32 mvCpu6180L2ClkGet(MV_VOID) -+{ -+ MV_U32 L2ClkRate=0; -+ MV_CPU_ARM_CLK _cpu6180_ddr_l2_CLK[] = MV_CPU6180_DDR_L2_CLCK_TBL; -+ -+ L2ClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ L2ClkRate = L2ClkRate & MSAR_CPUCLCK_MASK_6180; -+ L2ClkRate = L2ClkRate >> MSAR_CPUCLCK_OFFS_6180; -+ -+ L2ClkRate = _cpu6180_ddr_l2_CLK[L2ClkRate].l2Clk; -+ -+ return L2ClkRate; -+ -+} -+ -+MV_U32 mvCpuL2ClkGet(MV_VOID) -+{ -+#ifdef L2CLK_AUTO_DETECT -+ MV_U32 L2ClkRate, tmp, pClkRate, indexL2Rtio; -+ MV_U32 L2Rtio[][2] = MV_L2_CLCK_RTIO_TBL; -+ -+ if(mvCtrlModelGet() == MV_6180_DEV_ID) -+ return mvCpu6180L2ClkGet(); -+ -+ pClkRate = mvCpuPclkGet(); -+ -+ tmp = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ indexL2Rtio = MSAR_L2CLCK_EXTRACT(tmp); -+ -+ L2ClkRate = ((pClkRate * L2Rtio[indexL2Rtio][1]) / L2Rtio[indexL2Rtio][0]); -+ -+ return L2ClkRate; -+#else -+ return MV_BOARD_DEFAULT_L2CLK; -+#endif -+} -+ -+ -+/******************************************************************************* -+* mvCpuNameGet - Get CPU name -+* -+* DESCRIPTION: -+* This function returns a string describing the CPU model and revision. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* pNameBuff - Buffer to contain board name string. Minimum size 32 chars. -+* -+* RETURN: -+* None. -+*******************************************************************************/ -+MV_VOID mvCpuNameGet(char *pNameBuff) -+{ -+ MV_U32 cpuModel; -+ -+ cpuModel = mvOsCpuPartGet(); -+ -+ /* The CPU module is indicated in the Processor Version Register (PVR) */ -+ switch(cpuModel) -+ { -+ case CPU_PART_MRVL131: -+ mvOsSPrintf(pNameBuff, "%s (Rev %d)", "Marvell Feroceon",mvOsCpuRevGet()); -+ break; -+ case CPU_PART_ARM926: -+ mvOsSPrintf(pNameBuff, "%s (Rev %d)", "ARM926",mvOsCpuRevGet()); -+ break; -+ case CPU_PART_ARM946: -+ mvOsSPrintf(pNameBuff, "%s (Rev %d)", "ARM946",mvOsCpuRevGet()); -+ break; -+ default: -+ mvOsSPrintf(pNameBuff,"??? (0x%04x) (Rev %d)",cpuModel,mvOsCpuRevGet()); -+ break; -+ } /* switch */ -+ -+ return; -+} -+ -+ -+#define MV_PROC_STR_SIZE 50 -+ -+static void mvCpuIfGetL2EccMode(MV_8 *buf) -+{ -+ MV_U32 regVal = MV_REG_READ(CPU_L2_CONFIG_REG); -+ if (regVal & BIT2) -+ mvOsSPrintf(buf, "L2 ECC Enabled"); -+ else -+ mvOsSPrintf(buf, "L2 ECC Disabled"); -+} -+ -+static void mvCpuIfGetL2Mode(MV_8 *buf) -+{ -+ MV_U32 regVal = 0; -+ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ -+ if (regVal & BIT22) -+ mvOsSPrintf(buf, "L2 Enabled"); -+ else -+ mvOsSPrintf(buf, "L2 Disabled"); -+} -+ -+static void mvCpuIfGetL2PrefetchMode(MV_8 *buf) -+{ -+ MV_U32 regVal = 0; -+ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ -+ if (regVal & BIT24) -+ mvOsSPrintf(buf, "L2 Prefetch Disabled"); -+ else -+ mvOsSPrintf(buf, "L2 Prefetch Enabled"); -+} -+ -+static void mvCpuIfGetWriteAllocMode(MV_8 *buf) -+{ -+ MV_U32 regVal = 0; -+ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ -+ if (regVal & BIT28) -+ mvOsSPrintf(buf, "Write Allocate Enabled"); -+ else -+ mvOsSPrintf(buf, "Write Allocate Disabled"); -+} -+ -+static void mvCpuIfGetCpuStreamMode(MV_8 *buf) -+{ -+ MV_U32 regVal = 0; -+ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ -+ if (regVal & BIT29) -+ mvOsSPrintf(buf, "CPU Streaming Enabled"); -+ else -+ mvOsSPrintf(buf, "CPU Streaming Disabled"); -+} -+ -+static void mvCpuIfPrintCpuRegs(void) -+{ -+ MV_U32 regVal = 0; -+ -+ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ -+ mvOsPrintf("Extra Feature Reg = 0x%x\n",regVal); -+ -+ __asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (regVal)); /* Read Control register */ -+ mvOsPrintf("Control Reg = 0x%x\n",regVal); -+ -+ __asm volatile ("mrc p15, 0, %0, c0, c0, 0" : "=r" (regVal)); /* Read ID Code register */ -+ mvOsPrintf("ID Code Reg = 0x%x\n",regVal); -+ -+ __asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=r" (regVal)); /* Read Cache Type register */ -+ mvOsPrintf("Cache Type Reg = 0x%x\n",regVal); -+ -+} -+ -+MV_U32 mvCpuIfPrintSystemConfig(MV_8 *buffer, MV_U32 index) -+{ -+ MV_U32 count = 0; -+ -+ MV_8 L2_ECC_str[MV_PROC_STR_SIZE]; -+ MV_8 L2_En_str[MV_PROC_STR_SIZE]; -+ MV_8 L2_Prefetch_str[MV_PROC_STR_SIZE]; -+ MV_8 Write_Alloc_str[MV_PROC_STR_SIZE]; -+ MV_8 Cpu_Stream_str[MV_PROC_STR_SIZE]; -+ -+ mvCpuIfGetL2Mode(L2_En_str); -+ mvCpuIfGetL2EccMode(L2_ECC_str); -+ mvCpuIfGetL2PrefetchMode(L2_Prefetch_str); -+ mvCpuIfGetWriteAllocMode(Write_Alloc_str); -+ mvCpuIfGetCpuStreamMode(Cpu_Stream_str); -+ mvCpuIfPrintCpuRegs(); -+ -+ count += mvOsSPrintf(buffer + count + index, "%s\n", L2_En_str); -+ count += mvOsSPrintf(buffer + count + index, "%s\n", L2_ECC_str); -+ count += mvOsSPrintf(buffer + count + index, "%s\n", L2_Prefetch_str); -+ count += mvOsSPrintf(buffer + count + index, "%s\n", Write_Alloc_str); -+ count += mvOsSPrintf(buffer + count + index, "%s\n", Cpu_Stream_str); -+ return count; -+} -+ -+MV_U32 whoAmI(MV_VOID) -+{ -+ return 0; -+} -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h 2010-11-09 20:28:07.562495452 +0100 -@@ -0,0 +1,99 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvCpuh -+#define __INCmvCpuh -+ -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+ -+/* defines */ -+#define CPU_PART_MRVL131 0x131 -+#define CPU_PART_ARM926 0x926 -+#define CPU_PART_ARM946 0x946 -+#define MV_CPU_ARM_CLK_ELM_SIZE 12 -+#define MV_CPU_ARM_CLK_RATIO_OFF 8 -+#define MV_CPU_ARM_CLK_DDR_OFF 4 -+ -+#ifndef MV_ASMLANGUAGE -+typedef struct _mvCpuArmClk -+{ -+ MV_U32 cpuClk; /* CPU clock in MHz */ -+ MV_U32 ddrClk; /* DDR clock in MHz */ -+ MV_U32 l2Clk; /* CPU DDR clock ratio */ -+ -+}MV_CPU_ARM_CLK; -+ -+MV_U32 mvCpuPclkGet(MV_VOID); -+MV_VOID mvCpuNameGet(char *pNameBuff); -+MV_U32 mvCpuL2ClkGet(MV_VOID); -+MV_U32 mvCpuIfPrintSystemConfig(MV_8 *buffer, MV_U32 index); -+MV_U32 whoAmI(MV_VOID); -+ -+#endif /* MV_ASMLANGUAGE */ -+ -+ -+#endif /* __INCmvCpuh */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c 2010-11-09 20:28:07.602495466 +0100 -@@ -0,0 +1,296 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+/******************************************************************************* -+* mvCtrlEnvAddrDec.h - Marvell controller address decode library -+* -+* DESCRIPTION: -+* -+* DEPENDENCIES: -+* None. -+* -+*******************************************************************************/ -+ -+/* includes */ -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+#include "ctrlEnv/sys/mvAhbToMbusRegs.h" -+#include "ddr2/mvDramIfRegs.h" -+#include "pex/mvPexRegs.h" -+ -+#define MV_DEBUG -+ -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+/* Default Attributes array */ -+MV_TARGET_ATTRIB mvTargetDefaultsArray[] = TARGETS_DEF_ARRAY; -+extern MV_TARGET *sampleAtResetTargetArray; -+/* Dram\AHBToMbus\PEX share regsiter */ -+ -+#define CTRL_DEC_BASE_OFFS 16 -+#define CTRL_DEC_BASE_MASK (0xffff << CTRL_DEC_BASE_OFFS) -+#define CTRL_DEC_BASE_ALIGNMENT 0x10000 -+ -+#define CTRL_DEC_SIZE_OFFS 16 -+#define CTRL_DEC_SIZE_MASK (0xffff << CTRL_DEC_SIZE_OFFS) -+#define CTRL_DEC_SIZE_ALIGNMENT 0x10000 -+ -+#define CTRL_DEC_WIN_EN BIT0 -+ -+ -+ -+/******************************************************************************* -+* mvCtrlAddrDecToReg - Get address decode register format values -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_STATUS mvCtrlAddrDecToReg(MV_ADDR_WIN *pAddrDecWin, MV_DEC_REGS *pAddrDecRegs) -+{ -+ -+ MV_U32 baseToReg=0 , sizeToReg=0; -+ -+ /* BaseLow[31:16] => base register [31:16] */ -+ baseToReg = pAddrDecWin->baseLow & CTRL_DEC_BASE_MASK; -+ -+ /* Write to address decode Base Address Register */ -+ pAddrDecRegs->baseReg &= ~CTRL_DEC_BASE_MASK; -+ pAddrDecRegs->baseReg |= baseToReg; -+ -+ /* Get size register value according to window size */ -+ sizeToReg = ctrlSizeToReg(pAddrDecWin->size, CTRL_DEC_SIZE_ALIGNMENT); -+ -+ /* Size parameter validity check. */ -+ if (-1 == sizeToReg) -+ { -+ return MV_BAD_PARAM; -+ } -+ -+ /* set size */ -+ pAddrDecRegs->sizeReg &= ~CTRL_DEC_SIZE_MASK; -+ pAddrDecRegs->sizeReg |= (sizeToReg << CTRL_DEC_SIZE_OFFS); -+ -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvCtrlRegToAddrDec - Extract address decode struct from registers. -+* -+* DESCRIPTION: -+* This function extract address decode struct from address decode -+* registers given as parameters. -+* -+* INPUT: -+* pAddrDecRegs - Address decode register struct. -+* -+* OUTPUT: -+* pAddrDecWin - Target window data structure. -+* -+* RETURN: -+* MV_BAD_PARAM if address decode registers data is invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvCtrlRegToAddrDec(MV_DEC_REGS *pAddrDecRegs, MV_ADDR_WIN *pAddrDecWin) -+{ -+ MV_U32 sizeRegVal; -+ -+ sizeRegVal = (pAddrDecRegs->sizeReg & CTRL_DEC_SIZE_MASK) >> -+ CTRL_DEC_SIZE_OFFS; -+ -+ pAddrDecWin->size = ctrlRegToSize(sizeRegVal, CTRL_DEC_SIZE_ALIGNMENT); -+ -+ -+ /* Extract base address */ -+ /* Base register [31:16] ==> baseLow[31:16] */ -+ pAddrDecWin->baseLow = pAddrDecRegs->baseReg & CTRL_DEC_BASE_MASK; -+ -+ pAddrDecWin->baseHigh = 0; -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvCtrlAttribGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+* -+*******************************************************************************/ -+ -+MV_STATUS mvCtrlAttribGet(MV_TARGET target, -+ MV_TARGET_ATTRIB *targetAttrib) -+{ -+ -+ targetAttrib->attrib = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].attrib; -+ targetAttrib->targetId = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId; -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvCtrlGetAttrib - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_TARGET mvCtrlTargetGet(MV_TARGET_ATTRIB *targetAttrib) -+{ -+ MV_TARGET target; -+ MV_TARGET x; -+ for (target = SDRAM_CS0; target < MAX_TARGETS ; target ++) -+ { -+ x = MV_CHANGE_BOOT_CS(target); -+ if ((mvTargetDefaultsArray[x].attrib == targetAttrib->attrib) && -+ (mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId == targetAttrib->targetId)) -+ { -+ /* found it */ -+ break; -+ } -+ } -+ -+ return target; -+} -+ -+MV_STATUS mvCtrlAddrDecToParams(MV_DEC_WIN *pAddrDecWin, -+ MV_DEC_WIN_PARAMS *pWinParam) -+{ -+ MV_U32 baseToReg=0, sizeToReg=0; -+ -+ /* BaseLow[31:16] => base register [31:16] */ -+ baseToReg = pAddrDecWin->addrWin.baseLow & CTRL_DEC_BASE_MASK; -+ -+ /* Write to address decode Base Address Register */ -+ pWinParam->baseAddr &= ~CTRL_DEC_BASE_MASK; -+ pWinParam->baseAddr |= baseToReg; -+ -+ /* Get size register value according to window size */ -+ sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, CTRL_DEC_SIZE_ALIGNMENT); -+ -+ /* Size parameter validity check. */ -+ if (-1 == sizeToReg) -+ { -+ mvOsPrintf("mvCtrlAddrDecToParams: ERR. ctrlSizeToReg failed.\n"); -+ return MV_BAD_PARAM; -+ } -+ pWinParam->size = sizeToReg; -+ -+ pWinParam->attrib = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(pAddrDecWin->target)].attrib; -+ pWinParam->targetId = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(pAddrDecWin->target)].targetId; -+ -+ return MV_OK; -+} -+ -+MV_STATUS mvCtrlParamsToAddrDec(MV_DEC_WIN_PARAMS *pWinParam, -+ MV_DEC_WIN *pAddrDecWin) -+{ -+ MV_TARGET_ATTRIB targetAttrib; -+ -+ pAddrDecWin->addrWin.baseLow = pWinParam->baseAddr; -+ -+ /* Upper 32bit address base is supported under PCI High Address remap */ -+ pAddrDecWin->addrWin.baseHigh = 0; -+ -+ /* Prepare sizeReg to ctrlRegToSize function */ -+ pAddrDecWin->addrWin.size = ctrlRegToSize(pWinParam->size, CTRL_DEC_SIZE_ALIGNMENT); -+ -+ if (-1 == pAddrDecWin->addrWin.size) -+ { -+ DB(mvOsPrintf("mvCtrlParamsToAddrDec: ERR. ctrlRegToSize failed.\n")); -+ return MV_BAD_PARAM; -+ } -+ targetAttrib.targetId = pWinParam->targetId; -+ targetAttrib.attrib = pWinParam->attrib; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ return MV_OK; -+} -+ -+ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h 2010-11-09 20:28:07.642495620 +0100 -@@ -0,0 +1,203 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvCtrlEnvAddrDech -+#define __INCmvCtrlEnvAddrDech -+ -+/* includes */ -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvRegs.h" -+ -+ -+/* defines */ -+/* DUnit attributes */ -+#define ATMWCR_WIN_DUNIT_CS0_OFFS 0 -+#define ATMWCR_WIN_DUNIT_CS0_MASK BIT0 -+#define ATMWCR_WIN_DUNIT_CS0_REQ (0 << ATMWCR_WIN_DUNIT_CS0_OFFS) -+ -+#define ATMWCR_WIN_DUNIT_CS1_OFFS 1 -+#define ATMWCR_WIN_DUNIT_CS1_MASK BIT1 -+#define ATMWCR_WIN_DUNIT_CS1_REQ (0 << ATMWCR_WIN_DUNIT_CS1_OFFS) -+ -+#define ATMWCR_WIN_DUNIT_CS2_OFFS 2 -+#define ATMWCR_WIN_DUNIT_CS2_MASK BIT2 -+#define ATMWCR_WIN_DUNIT_CS2_REQ (0 << ATMWCR_WIN_DUNIT_CS2_OFFS) -+ -+#define ATMWCR_WIN_DUNIT_CS3_OFFS 3 -+#define ATMWCR_WIN_DUNIT_CS3_MASK BIT3 -+#define ATMWCR_WIN_DUNIT_CS3_REQ (0 << ATMWCR_WIN_DUNIT_CS3_OFFS) -+ -+/* RUnit (Device) attributes */ -+#define ATMWCR_WIN_RUNIT_DEVCS0_OFFS 0 -+#define ATMWCR_WIN_RUNIT_DEVCS0_MASK BIT0 -+#define ATMWCR_WIN_RUNIT_DEVCS0_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS0_OFFS) -+ -+#define ATMWCR_WIN_RUNIT_DEVCS1_OFFS 1 -+#define ATMWCR_WIN_RUNIT_DEVCS1_MASK BIT1 -+#define ATMWCR_WIN_RUNIT_DEVCS1_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS1_OFFS) -+ -+#define ATMWCR_WIN_RUNIT_DEVCS2_OFFS 2 -+#define ATMWCR_WIN_RUNIT_DEVCS2_MASK BIT2 -+#define ATMWCR_WIN_RUNIT_DEVCS2_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS2_OFFS) -+ -+#define ATMWCR_WIN_RUNIT_BOOTCS_OFFS 4 -+#define ATMWCR_WIN_RUNIT_BOOTCS_MASK BIT4 -+#define ATMWCR_WIN_RUNIT_BOOTCS_REQ (0 << ATMWCR_WIN_RUNIT_BOOTCS_OFFS) -+ -+/* LMaster (PCI) attributes */ -+#define ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS 0 -+#define ATMWCR_WIN_LUNIT_BYTE_SWP_MASK BIT0 -+#define ATMWCR_WIN_LUNIT_BYTE_SWP (0 << ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS) -+#define ATMWCR_WIN_LUNIT_BYTE_NO_SWP (1 << ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS) -+ -+ -+#define ATMWCR_WIN_LUNIT_WORD_SWP_OFFS 1 -+#define ATMWCR_WIN_LUNIT_WORD_SWP_MASK BIT1 -+#define ATMWCR_WIN_LUNIT_WORD_SWP (0 << ATMWCR_WIN_LUNIT_WORD_SWP_OFFS) -+#define ATMWCR_WIN_LUNIT_WORD_NO_SWP (1 << ATMWCR_WIN_LUNIT_WORD_SWP_OFFS) -+ -+#define ATMWCR_WIN_LUNIT_NO_SNOOP BIT2 -+ -+#define ATMWCR_WIN_LUNIT_TYPE_OFFS 3 -+#define ATMWCR_WIN_LUNIT_TYPE_MASK BIT3 -+#define ATMWCR_WIN_LUNIT_TYPE_IO (0 << ATMWCR_WIN_LUNIT_TYPE_OFFS) -+#define ATMWCR_WIN_LUNIT_TYPE_MEM (1 << ATMWCR_WIN_LUNIT_TYPE_OFFS) -+ -+#define ATMWCR_WIN_LUNIT_FORCE64_OFFS 4 -+#define ATMWCR_WIN_LUNIT_FORCE64_MASK BIT4 -+#define ATMWCR_WIN_LUNIT_FORCE64 (0 << ATMWCR_WIN_LUNIT_FORCE64_OFFS) -+ -+#define ATMWCR_WIN_LUNIT_ORDERING_OFFS 6 -+#define ATMWCR_WIN_LUNIT_ORDERING_MASK BIT6 -+#define ATMWCR_WIN_LUNIT_ORDERING (1 << ATMWCR_WIN_LUNIT_FORCE64_OFFS) -+ -+/* PEX Attributes */ -+#define ATMWCR_WIN_PEX_TYPE_OFFS 3 -+#define ATMWCR_WIN_PEX_TYPE_MASK BIT3 -+#define ATMWCR_WIN_PEX_TYPE_IO (0 << ATMWCR_WIN_PEX_TYPE_OFFS) -+#define ATMWCR_WIN_PEX_TYPE_MEM (1 << ATMWCR_WIN_PEX_TYPE_OFFS) -+ -+/* typedefs */ -+ -+/* Unsupported attributes for address decode: */ -+/* 2) PCI0/1_REQ64n control */ -+ -+typedef struct _mvDecRegs -+{ -+ MV_U32 baseReg; -+ MV_U32 baseRegHigh; -+ MV_U32 sizeReg; -+ -+}MV_DEC_REGS; -+ -+typedef struct _mvTargetAttrib -+{ -+ MV_U8 attrib; /* chip select attributes */ -+ MV_TARGET_ID targetId; /* Target Id of this MV_TARGET */ -+ -+}MV_TARGET_ATTRIB; -+ -+ -+/* This structure describes address decode window */ -+typedef struct _mvDecWin -+{ -+ MV_TARGET target; /* Target for addr decode window */ -+ MV_ADDR_WIN addrWin; /* Address window of target */ -+ MV_BOOL enable; /* Window enable/disable */ -+}MV_DEC_WIN; -+ -+typedef struct _mvDecWinParams -+{ -+ MV_TARGET_ID targetId; /* Target ID field */ -+ MV_U8 attrib; /* Attribute field */ -+ MV_U32 baseAddr; /* Base address in register format */ -+ MV_U32 size; /* Size in register format */ -+}MV_DEC_WIN_PARAMS; -+ -+ -+/* mvCtrlEnvAddrDec API list */ -+ -+MV_STATUS mvCtrlAddrDecToReg(MV_ADDR_WIN *pAddrDecWin, -+ MV_DEC_REGS *pAddrDecRegs); -+ -+MV_STATUS mvCtrlRegToAddrDec(MV_DEC_REGS *pAddrDecRegs, -+ MV_ADDR_WIN *pAddrDecWin); -+ -+MV_STATUS mvCtrlAttribGet(MV_TARGET target, -+ MV_TARGET_ATTRIB *targetAttrib); -+ -+MV_TARGET mvCtrlTargetGet(MV_TARGET_ATTRIB *targetAttrib); -+ -+ -+MV_STATUS mvCtrlAddrDecToParams(MV_DEC_WIN *pAddrDecWin, -+ MV_DEC_WIN_PARAMS *pWinParam); -+ -+MV_STATUS mvCtrlParamsToAddrDec(MV_DEC_WIN_PARAMS *pWinParam, -+ MV_DEC_WIN *pAddrDecWin); -+ -+ -+ -+ -+#endif /* __INCmvCtrlEnvAddrDech */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h 2010-11-09 20:28:07.682495401 +0100 -@@ -0,0 +1,98 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvCtrlEnvAsmh -+#define __INCmvCtrlEnvAsmh -+#include "pex/mvPexRegs.h" -+ -+#define CHIP_BOND_REG 0x10034 -+#define PCKG_OPT_MASK_AS #3 -+#define PXCCARI_REVID_MASK_AS #PXCCARI_REVID_MASK -+ -+/* Read device ID into toReg bits 15:0 from 0xd0000000 */ -+/* defines */ -+#define MV_DV_CTRL_MODEL_GET_ASM(toReg, tmpReg) \ -+ MV_DV_REG_READ_ASM(toReg, tmpReg, CHIP_BOND_REG);\ -+ and toReg, toReg, PCKG_OPT_MASK_AS /* Mask for package ID */ -+ -+/* Read device ID into toReg bits 15:0 from 0xf1000000*/ -+#define MV_CTRL_MODEL_GET_ASM(toReg, tmpReg) \ -+ MV_REG_READ_ASM(toReg, tmpReg, CHIP_BOND_REG);\ -+ and toReg, toReg, PCKG_OPT_MASK_AS /* Mask for package ID */ -+ -+/* Read Revision into toReg bits 7:0 0xd0000000*/ -+#define MV_DV_CTRL_REV_GET_ASM(toReg, tmpReg) \ -+ /* Read device revision */ \ -+ MV_DV_REG_READ_ASM(toReg, tmpReg, PEX_CFG_DIRECT_ACCESS(0,PEX_CLASS_CODE_AND_REVISION_ID));\ -+ and toReg, toReg, PXCCARI_REVID_MASK_AS /* Mask for calss ID */ -+ -+/* Read Revision into toReg bits 7:0 0xf1000000*/ -+#define MV_CTRL_REV_GET_ASM(toReg, tmpReg) \ -+ /* Read device revision */ \ -+ MV_REG_READ_ASM(toReg, tmpReg, PEX_CFG_DIRECT_ACCESS(0,PEX_CLASS_CODE_AND_REVISION_ID));\ -+ and toReg, toReg, PXCCARI_REVID_MASK_AS /* Mask for calss ID */ -+ -+ -+#endif /* __INCmvCtrlEnvAsmh */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c 2010-11-09 20:28:07.712495488 +0100 -@@ -0,0 +1,1825 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+/* includes */ -+#include "mvCommon.h" -+#include "mvCtrlEnvLib.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+ -+#if defined(MV_INCLUDE_PEX) -+#include "pex/mvPex.h" -+#include "ctrlEnv/sys/mvSysPex.h" -+#endif -+ -+#if defined(MV_INCLUDE_GIG_ETH) -+#include "ctrlEnv/sys/mvSysGbe.h" -+#endif -+ -+#if defined(MV_INCLUDE_XOR) -+#include "ctrlEnv/sys/mvSysXor.h" -+#endif -+ -+#if defined(MV_INCLUDE_SATA) -+#include "ctrlEnv/sys/mvSysSata.h" -+#endif -+ -+#if defined(MV_INCLUDE_USB) -+#include "ctrlEnv/sys/mvSysUsb.h" -+#endif -+ -+#if defined(MV_INCLUDE_AUDIO) -+#include "ctrlEnv/sys/mvSysAudio.h" -+#endif -+ -+#if defined(MV_INCLUDE_CESA) -+#include "ctrlEnv/sys/mvSysCesa.h" -+#endif -+ -+#if defined(MV_INCLUDE_TS) -+#include "ctrlEnv/sys/mvSysTs.h" -+#endif -+ -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+/******************************************************************************* -+* mvCtrlEnvInit - Initialize Marvell controller environment. -+* -+* DESCRIPTION: -+* This function get environment information and initialize controller -+* internal/external environment. For example -+* 1) MPP settings according to board MPP macros. -+* NOTE: It is the user responsibility to shut down all DMA channels -+* in device and disable controller sub units interrupts during -+* boot process. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvCtrlEnvInit(MV_VOID) -+{ -+ MV_U32 mppGroup; -+ MV_U32 devId; -+ MV_U32 boardId; -+ MV_U32 i; -+ MV_U32 maxMppGrp = 1; -+ MV_U32 mppVal = 0; -+ MV_U32 bootVal = 0; -+ MV_U32 mppGroupType = 0; -+ MV_U32 mppGroup1[][3] = MPP_GROUP_1_TYPE; -+ MV_U32 mppGroup2[][3] = MPP_GROUP_2_TYPE; -+ -+ devId = mvCtrlModelGet(); -+ boardId= mvBoardIdGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ maxMppGrp = MV_6281_MPP_MAX_GROUP; -+ break; -+ case MV_6192_DEV_ID: -+ maxMppGrp = MV_6192_MPP_MAX_GROUP; -+ break; -+ case MV_6190_DEV_ID: -+ maxMppGrp = MV_6190_MPP_MAX_GROUP; -+ break; -+ case MV_6180_DEV_ID: -+ maxMppGrp = MV_6180_MPP_MAX_GROUP; -+ break; -+ } -+ -+ /* MPP Init */ -+ /* We split mpp init to 3 phases: -+ * 1. We init mpp[19:0] from the board info. mpp[23:20] will be over write -+ * in phase 2. -+ * 2. We detect the mpp group type and according the mpp values [35:20]. -+ * 3. We detect the mpp group type and according the mpp values [49:36]. -+ */ -+ /* Mpp phase 1 mpp[19:0] */ -+ /* Read MPP group from board level and assign to MPP register */ -+ for (mppGroup = 0; mppGroup < 3; mppGroup++) -+ { -+ mppVal = mvBoardMppGet(mppGroup); -+ if (mppGroup == 0) -+ { -+ bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); -+ if (mvCtrlIsBootFromSPI()) -+ { -+ mppVal &= ~0xffff; -+ bootVal &= 0xffff; -+ mppVal |= bootVal; -+ } -+ else if (mvCtrlIsBootFromSPIUseNAND()) -+ { -+ mppVal &= ~0xf0000000; -+ bootVal &= 0xf0000000; -+ mppVal |= bootVal; -+ } -+ else if (mvCtrlIsBootFromNAND()) -+ { -+ mppVal &= ~0xffffff; -+ bootVal &= 0xffffff; -+ mppVal |= bootVal; -+ } -+ } -+ -+ if (mppGroup == 2) -+ { -+ bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); -+ if (mvCtrlIsBootFromNAND()) -+ { -+ mppVal &= ~0xff00; -+ bootVal &= 0xff00; -+ mppVal |= bootVal; -+ } -+ } -+ -+ MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal); -+ } -+ -+ /* Identify MPPs group */ -+ mvBoardMppGroupIdUpdate(); -+ -+ /* Update MPPs mux relevent only on Marvell DB */ -+ if ((boardId == DB_88F6281A_BP_ID) || -+ (boardId == DB_88F6180A_BP_ID)) -+ mvBoardMppMuxSet(); -+ -+ mppGroupType = mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_1); -+ -+ /* Mpp phase 2 */ -+ /* Read MPP group from board level and assign to MPP register */ -+ if (devId != MV_6180_DEV_ID) -+ { -+ i = 0; -+ for (mppGroup = 2; mppGroup < 5; mppGroup++) -+ { -+ if ((mppGroupType == MV_BOARD_OTHER) || -+ (boardId == RD_88F6281A_ID) || -+ (boardId == RD_88F6192A_ID) || -+ (boardId == RD_88F6190A_ID) || -+ (boardId == RD_88F6281A_PCAC_ID) || -+ (boardId == SHEEVA_PLUG_ID)) -+ mppVal = mvBoardMppGet(mppGroup); -+ else -+ { -+ mppVal = mppGroup1[mppGroupType][i]; -+ i++; -+ } -+ -+ /* Group 2 is shared mpp[23:16] */ -+ if (mppGroup == 2) -+ { -+ bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); -+ mppVal &= ~0xffff; -+ bootVal &= 0xffff; -+ mppVal |= bootVal; -+ } -+ -+ MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal); -+ } -+ } -+ -+ if ((devId == MV_6192_DEV_ID) || (devId == MV_6190_DEV_ID)) -+ return MV_OK; -+ -+ /* Mpp phase 3 */ -+ mppGroupType = mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_2); -+ /* Read MPP group from board level and assign to MPP register */ -+ i = 0; -+ for (mppGroup = 4; mppGroup < 7; mppGroup++) -+ { -+ if ((mppGroupType == MV_BOARD_OTHER) || -+ (boardId == RD_88F6281A_ID) || -+ (boardId == RD_88F6281A_PCAC_ID) || -+ (boardId == SHEEVA_PLUG_ID)) -+ mppVal = mvBoardMppGet(mppGroup); -+ else -+ { -+ mppVal = mppGroup2[mppGroupType][i]; -+ i++; -+ } -+ -+ /* Group 4 is shared mpp[35:32] */ -+ if (mppGroup == 4) -+ { -+ bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); -+ mppVal &= ~0xffff; -+ bootVal &= 0xffff; -+ mppVal |= bootVal; -+ } -+ -+ MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal); -+ } -+ /* Update SSCG configuration register*/ -+ if(mvBoardIdGet() == DB_88F6281A_BP_ID || mvBoardIdGet() == DB_88F6192A_BP_ID || -+ mvBoardIdGet() == DB_88F6190A_BP_ID || mvBoardIdGet() == DB_88F6180A_BP_ID) -+ MV_REG_WRITE(0x100d8, 0x53); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCtrlMppRegGet - return reg address of mpp group -+* -+* DESCRIPTION: -+* -+* INPUT: -+* mppGroup - MPP group. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_U32 - Register address. -+* -+*******************************************************************************/ -+MV_U32 mvCtrlMppRegGet(MV_U32 mppGroup) -+{ -+ MV_U32 ret; -+ -+ switch(mppGroup){ -+ case (0): ret = MPP_CONTROL_REG0; -+ break; -+ case (1): ret = MPP_CONTROL_REG1; -+ break; -+ case (2): ret = MPP_CONTROL_REG2; -+ break; -+ case (3): ret = MPP_CONTROL_REG3; -+ break; -+ case (4): ret = MPP_CONTROL_REG4; -+ break; -+ case (5): ret = MPP_CONTROL_REG5; -+ break; -+ case (6): ret = MPP_CONTROL_REG6; -+ break; -+ default: ret = MPP_CONTROL_REG0; -+ break; -+ } -+ return ret; -+} -+#if defined(MV_INCLUDE_PEX) -+/******************************************************************************* -+* mvCtrlPexMaxIfGet - Get Marvell controller number of PEX interfaces. -+* -+* DESCRIPTION: -+* This function returns Marvell controller number of PEX interfaces. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Marvell controller number of PEX interfaces. If controller -+* ID is undefined the function returns '0'. -+* -+*******************************************************************************/ -+MV_U32 mvCtrlPexMaxIfGet(MV_VOID) -+{ -+ -+ return MV_PEX_MAX_IF; -+} -+#endif -+ -+#if defined(MV_INCLUDE_GIG_ETH) -+/******************************************************************************* -+* mvCtrlEthMaxPortGet - Get Marvell controller number of etherent ports. -+* -+* DESCRIPTION: -+* This function returns Marvell controller number of etherent port. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Marvell controller number of etherent port. -+* -+*******************************************************************************/ -+MV_U32 mvCtrlEthMaxPortGet(MV_VOID) -+{ -+ MV_U32 devId; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ return MV_6281_ETH_MAX_PORTS; -+ break; -+ case MV_6192_DEV_ID: -+ return MV_6192_ETH_MAX_PORTS; -+ break; -+ case MV_6190_DEV_ID: -+ return MV_6190_ETH_MAX_PORTS; -+ break; -+ case MV_6180_DEV_ID: -+ return MV_6180_ETH_MAX_PORTS; -+ break; -+ } -+ return 0; -+ -+} -+#endif -+ -+#if defined(MV_INCLUDE_XOR) -+/******************************************************************************* -+* mvCtrlXorMaxChanGet - Get Marvell controller number of XOR channels. -+* -+* DESCRIPTION: -+* This function returns Marvell controller number of XOR channels. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Marvell controller number of XOR channels. -+* -+*******************************************************************************/ -+MV_U32 mvCtrlXorMaxChanGet(MV_VOID) -+{ -+ return MV_XOR_MAX_CHAN; -+} -+#endif -+ -+#if defined(MV_INCLUDE_USB) -+/******************************************************************************* -+* mvCtrlUsbHostMaxGet - Get number of Marvell Usb controllers -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* returns number of Marvell USB controllers. -+* -+*******************************************************************************/ -+MV_U32 mvCtrlUsbMaxGet(void) -+{ -+ return MV_USB_MAX_PORTS; -+} -+#endif -+ -+ -+#if defined(MV_INCLUDE_NAND) -+/******************************************************************************* -+* mvCtrlNandSupport - Return if this controller has integrated NAND flash support -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if NAND is supported and MV_FALSE otherwise -+* -+*******************************************************************************/ -+MV_U32 mvCtrlNandSupport(MV_VOID) -+{ -+ MV_U32 devId; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ return MV_6281_NAND; -+ break; -+ case MV_6192_DEV_ID: -+ return MV_6192_NAND; -+ break; -+ case MV_6190_DEV_ID: -+ return MV_6190_NAND; -+ break; -+ case MV_6180_DEV_ID: -+ return MV_6180_NAND; -+ break; -+ } -+ return 0; -+ -+} -+#endif -+ -+#if defined(MV_INCLUDE_SDIO) -+/******************************************************************************* -+* mvCtrlSdioSupport - Return if this controller has integrated SDIO flash support -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if SDIO is supported and MV_FALSE otherwise -+* -+*******************************************************************************/ -+MV_U32 mvCtrlSdioSupport(MV_VOID) -+{ -+ MV_U32 devId; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ return MV_6281_SDIO; -+ break; -+ case MV_6192_DEV_ID: -+ return MV_6192_SDIO; -+ break; -+ case MV_6190_DEV_ID: -+ return MV_6190_SDIO; -+ break; -+ case MV_6180_DEV_ID: -+ return MV_6180_SDIO; -+ break; -+ } -+ return 0; -+ -+} -+#endif -+ -+#if defined(MV_INCLUDE_TS) -+/******************************************************************************* -+* mvCtrlTsSupport - Return if this controller has integrated TS flash support -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if TS is supported and MV_FALSE otherwise -+* -+*******************************************************************************/ -+MV_U32 mvCtrlTsSupport(MV_VOID) -+{ -+ MV_U32 devId; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ return MV_6281_TS; -+ break; -+ case MV_6192_DEV_ID: -+ return MV_6192_TS; -+ break; -+ case MV_6190_DEV_ID: -+ return MV_6190_TS; -+ break; -+ case MV_6180_DEV_ID: -+ return MV_6180_TS; -+ break; -+ } -+ return 0; -+} -+#endif -+ -+#if defined(MV_INCLUDE_AUDIO) -+/******************************************************************************* -+* mvCtrlAudioSupport - Return if this controller has integrated AUDIO flash support -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if AUDIO is supported and MV_FALSE otherwise -+* -+*******************************************************************************/ -+MV_U32 mvCtrlAudioSupport(MV_VOID) -+{ -+ MV_U32 devId; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ return MV_6281_AUDIO; -+ break; -+ case MV_6192_DEV_ID: -+ return MV_6192_AUDIO; -+ break; -+ case MV_6190_DEV_ID: -+ return MV_6190_AUDIO; -+ break; -+ case MV_6180_DEV_ID: -+ return MV_6180_AUDIO; -+ break; -+ } -+ return 0; -+ -+} -+#endif -+ -+#if defined(MV_INCLUDE_TDM) -+/******************************************************************************* -+* mvCtrlTdmSupport - Return if this controller has integrated TDM flash support -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if TDM is supported and MV_FALSE otherwise -+* -+*******************************************************************************/ -+MV_U32 mvCtrlTdmSupport(MV_VOID) -+{ -+ MV_U32 devId; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ return MV_6281_TDM; -+ break; -+ case MV_6192_DEV_ID: -+ return MV_6192_TDM; -+ break; -+ case MV_6190_DEV_ID: -+ return MV_6190_TDM; -+ break; -+ case MV_6180_DEV_ID: -+ return MV_6180_TDM; -+ break; -+ } -+ return 0; -+ -+} -+#endif -+ -+/******************************************************************************* -+* mvCtrlModelGet - Get Marvell controller device model (Id) -+* -+* DESCRIPTION: -+* This function returns 16bit describing the device model (ID) as defined -+* in PCI Device and Vendor ID configuration register offset 0x0. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 16bit desscribing Marvell controller ID -+* -+*******************************************************************************/ -+MV_U16 mvCtrlModelGet(MV_VOID) -+{ -+ MV_U32 devId; -+ -+ devId = MV_REG_READ(CHIP_BOND_REG); -+ devId &= PCKG_OPT_MASK; -+ -+ switch(devId){ -+ case 2: -+ return MV_6281_DEV_ID; -+ break; -+ case 1: -+ if (((MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0,PEX_DEVICE_AND_VENDOR_ID))& 0xffff0000) >> 16) -+ == MV_6190_DEV_ID) -+ return MV_6190_DEV_ID; -+ else -+ return MV_6192_DEV_ID; -+ break; -+ case 0: -+ return MV_6180_DEV_ID; -+ break; -+ } -+ -+ return 0; -+} -+/******************************************************************************* -+* mvCtrlRevGet - Get Marvell controller device revision number -+* -+* DESCRIPTION: -+* This function returns 8bit describing the device revision as defined -+* in PCI Express Class Code and Revision ID Register. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 8bit desscribing Marvell controller revision number -+* -+*******************************************************************************/ -+MV_U8 mvCtrlRevGet(MV_VOID) -+{ -+ MV_U8 revNum; -+#if defined(MV_INCLUDE_CLK_PWR_CNTRL) -+ /* Check pex power state */ -+ MV_U32 pexPower; -+ pexPower = mvCtrlPwrClckGet(PEX_UNIT_ID,0); -+ if (pexPower == MV_FALSE) -+ mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_TRUE); -+#endif -+ revNum = (MV_U8)MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0,PCI_CLASS_CODE_AND_REVISION_ID)); -+#if defined(MV_INCLUDE_CLK_PWR_CNTRL) -+ /* Return to power off state */ -+ if (pexPower == MV_FALSE) -+ mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_FALSE); -+#endif -+ return ((revNum & PCCRIR_REVID_MASK) >> PCCRIR_REVID_OFFS); -+} -+ -+/******************************************************************************* -+* mvCtrlNameGet - Get Marvell controller name -+* -+* DESCRIPTION: -+* This function returns a string describing the device model and revision. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* pNameBuff - Buffer to contain device name string. Minimum size 30 chars. -+* -+* RETURN: -+* -+* MV_ERROR if informantion can not be read. -+*******************************************************************************/ -+MV_STATUS mvCtrlNameGet(char *pNameBuff) -+{ -+ mvOsSPrintf (pNameBuff, "%s%x Rev %d", SOC_NAME_PREFIX, -+ mvCtrlModelGet(), mvCtrlRevGet()); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCtrlModelRevGet - Get Controller Model (Device ID) and Revision -+* -+* DESCRIPTION: -+* This function returns 32bit value describing both Device ID and Revision -+* as defined in PCI Express Device and Vendor ID Register and device revision -+* as defined in PCI Express Class Code and Revision ID Register. -+ -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit describing both controller device ID and revision number -+* -+*******************************************************************************/ -+MV_U32 mvCtrlModelRevGet(MV_VOID) -+{ -+ return ((mvCtrlModelGet() << 16) | mvCtrlRevGet()); -+} -+ -+/******************************************************************************* -+* mvCtrlModelRevNameGet - Get Marvell controller name -+* -+* DESCRIPTION: -+* This function returns a string describing the device model and revision. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* pNameBuff - Buffer to contain device name string. Minimum size 30 chars. -+* -+* RETURN: -+* -+* MV_ERROR if informantion can not be read. -+*******************************************************************************/ -+ -+MV_STATUS mvCtrlModelRevNameGet(char *pNameBuff) -+{ -+ -+ switch (mvCtrlModelRevGet()) -+ { -+ case MV_6281_A0_ID: -+ mvOsSPrintf (pNameBuff, "%s",MV_6281_A0_NAME); -+ break; -+ case MV_6192_A0_ID: -+ mvOsSPrintf (pNameBuff, "%s",MV_6192_A0_NAME); -+ break; -+ case MV_6180_A0_ID: -+ mvOsSPrintf (pNameBuff, "%s",MV_6180_A0_NAME); -+ break; -+ case MV_6190_A0_ID: -+ mvOsSPrintf (pNameBuff, "%s",MV_6190_A0_NAME); -+ break; -+ case MV_6281_A1_ID: -+ mvOsSPrintf (pNameBuff, "%s",MV_6281_A1_NAME); -+ break; -+ case MV_6192_A1_ID: -+ mvOsSPrintf (pNameBuff, "%s",MV_6192_A1_NAME); -+ break; -+ case MV_6180_A1_ID: -+ mvOsSPrintf (pNameBuff, "%s",MV_6180_A1_NAME); -+ break; -+ case MV_6190_A1_ID: -+ mvOsSPrintf (pNameBuff, "%s",MV_6190_A1_NAME); -+ break; -+ default: -+ mvCtrlNameGet(pNameBuff); -+ break; -+ } -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* ctrlWinOverlapTest - Test address windows for overlaping. -+* -+* DESCRIPTION: -+* This function checks the given two address windows for overlaping. -+* -+* INPUT: -+* pAddrWin1 - Address window 1. -+* pAddrWin2 - Address window 2. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* MV_TRUE if address window overlaps, MV_FALSE otherwise. -+*******************************************************************************/ -+MV_STATUS ctrlWinOverlapTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2) -+{ -+ MV_U32 winBase1, winBase2; -+ MV_U32 winTop1, winTop2; -+ -+ /* check if we have overflow than 4G*/ -+ if (((0xffffffff - pAddrWin1->baseLow) < pAddrWin1->size-1)|| -+ ((0xffffffff - pAddrWin2->baseLow) < pAddrWin2->size-1)) -+ { -+ return MV_TRUE; -+ } -+ -+ winBase1 = pAddrWin1->baseLow; -+ winBase2 = pAddrWin2->baseLow; -+ winTop1 = winBase1 + pAddrWin1->size-1; -+ winTop2 = winBase2 + pAddrWin2->size-1; -+ -+ -+ if (((winBase1 <= winTop2 ) && ( winTop2 <= winTop1)) || -+ ((winBase1 <= winBase2) && (winBase2 <= winTop1))) -+ { -+ return MV_TRUE; -+ } -+ else -+ { -+ return MV_FALSE; -+ } -+} -+ -+/******************************************************************************* -+* ctrlWinWithinWinTest - Test address windows for overlaping. -+* -+* DESCRIPTION: -+* This function checks the given win1 boundries is within -+* win2 boundries. -+* -+* INPUT: -+* pAddrWin1 - Address window 1. -+* pAddrWin2 - Address window 2. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* MV_TRUE if found win1 inside win2, MV_FALSE otherwise. -+*******************************************************************************/ -+MV_STATUS ctrlWinWithinWinTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2) -+{ -+ MV_U32 winBase1, winBase2; -+ MV_U32 winTop1, winTop2; -+ -+ winBase1 = pAddrWin1->baseLow; -+ winBase2 = pAddrWin2->baseLow; -+ winTop1 = winBase1 + pAddrWin1->size -1; -+ winTop2 = winBase2 + pAddrWin2->size -1; -+ -+ if (((winBase1 >= winBase2 ) && ( winBase1 <= winTop2)) || -+ ((winTop1 >= winBase2) && (winTop1 <= winTop2))) -+ { -+ return MV_TRUE; -+ } -+ else -+ { -+ return MV_FALSE; -+ } -+} -+ -+static const char* cntrlName[] = TARGETS_NAME_ARRAY; -+ -+/******************************************************************************* -+* mvCtrlTargetNameGet - Get Marvell controller target name -+* -+* DESCRIPTION: -+* This function convert the trget enumeration to string. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Target name (const MV_8 *) -+*******************************************************************************/ -+const MV_8* mvCtrlTargetNameGet( MV_TARGET target ) -+{ -+ -+ if (target >= MAX_TARGETS) -+ { -+ return "target unknown"; -+ } -+ -+ return cntrlName[target]; -+} -+ -+/******************************************************************************* -+* mvCtrlAddrDecShow - Print the Controller units address decode map. -+* -+* DESCRIPTION: -+* This function the Controller units address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvCtrlAddrDecShow(MV_VOID) -+{ -+ mvCpuIfAddDecShow(); -+ mvAhbToMbusAddDecShow(); -+#if defined(MV_INCLUDE_PEX) -+ mvPexAddrDecShow(); -+#endif -+#if defined(MV_INCLUDE_USB) -+ mvUsbAddrDecShow(); -+#endif -+#if defined(MV_INCLUDE_GIG_ETH) -+ mvEthAddrDecShow(); -+#endif -+#if defined(MV_INCLUDE_XOR) -+ mvXorAddrDecShow(); -+#endif -+#if defined(MV_INCLUDE_SATA) -+ mvSataAddrDecShow(); -+#endif -+#if defined(MV_INCLUDE_AUDIO) -+ mvAudioAddrDecShow(); -+#endif -+#if defined(MV_INCLUDE_TS) -+ mvTsuAddrDecShow(); -+#endif -+} -+ -+/******************************************************************************* -+* ctrlSizeToReg - Extract size value for register assignment. -+* -+* DESCRIPTION: -+* Address decode size parameter must be programed from LSB to MSB as -+* sequence of 1's followed by sequence of 0's. The number of 1's -+* specifies the size of the window in 64 KB granularity (e.g. a -+* value of 0x00ff specifies 256x64k = 16 MB). -+* This function extract the size value from the size parameter according -+* to given aligment paramter. For example for size 0x1000000 (16MB) and -+* aligment 0x10000 (64KB) the function will return 0x00FF. -+* -+* INPUT: -+* size - Size. -+* alignment - Size alignment. Note that alignment must be power of 2! -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit describing size register value correspond to size parameter. -+* If value is '-1' size parameter or aligment are invalid. -+*******************************************************************************/ -+MV_U32 ctrlSizeToReg(MV_U32 size, MV_U32 alignment) -+{ -+ MV_U32 retVal; -+ -+ /* Check size parameter alignment */ -+ if ((0 == size) || (MV_IS_NOT_ALIGN(size, alignment))) -+ { -+ DB(mvOsPrintf("ctrlSizeToReg: ERR. Size is zero or not aligned.\n")); -+ return -1; -+ } -+ -+ /* Take out the "alignment" portion out of the size parameter */ -+ alignment--; /* Now the alignmet is a sequance of '1' (e.g. 0xffff) */ -+ /* and size is 0x1000000 (16MB) for example */ -+ while(alignment & 1) /* Check that alignmet LSB is set */ -+ { -+ size = (size >> 1); /* If LSB is set, move 'size' one bit to right */ -+ alignment = (alignment >> 1); -+ } -+ -+ /* If after the alignment first '0' was met we still have '1' in */ -+ /* it then aligment is invalid (not power of 2) */ -+ if (alignment) -+ { -+ DB(mvOsPrintf("ctrlSizeToReg: ERR. Alignment parameter 0x%x invalid.\n", -+ (MV_U32)alignment)); -+ return -1; -+ } -+ -+ /* Now the size is shifted right according to aligment: 0x0100 */ -+ size--; /* Now the size is a sequance of '1': 0x00ff */ -+ -+ retVal = size ; -+ -+ /* Check that LSB to MSB is sequence of 1's followed by sequence of 0's */ -+ while(size & 1) /* Check that LSB is set */ -+ { -+ size = (size >> 1); /* If LSB is set, move one bit to the right */ -+ } -+ -+ if (size) /* Sequance of 1's is over. Check that we have no other 1's */ -+ { -+ DB(mvOsPrintf("ctrlSizeToReg: ERR. Size parameter 0x%x invalid.\n", -+ size)); -+ return -1; -+ } -+ -+ return retVal; -+ -+} -+ -+/******************************************************************************* -+* ctrlRegToSize - Extract size value from register value. -+* -+* DESCRIPTION: -+* This function extract a size value from the register size parameter -+* according to given aligment paramter. For example for register size -+* value 0xff and aligment 0x10000 the function will return 0x01000000. -+* -+* INPUT: -+* regSize - Size as in register format. See ctrlSizeToReg. -+* alignment - Size alignment. Note that alignment must be power of 2! -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit describing size. -+* If value is '-1' size parameter or aligment are invalid. -+*******************************************************************************/ -+MV_U32 ctrlRegToSize(MV_U32 regSize, MV_U32 alignment) -+{ -+ MV_U32 temp; -+ -+ /* Check that LSB to MSB is sequence of 1's followed by sequence of 0's */ -+ temp = regSize; /* Now the size is a sequance of '1': 0x00ff */ -+ -+ while(temp & 1) /* Check that LSB is set */ -+ { -+ temp = (temp >> 1); /* If LSB is set, move one bit to the right */ -+ } -+ -+ if (temp) /* Sequance of 1's is over. Check that we have no other 1's */ -+ { -+ DB(mvOsPrintf("ctrlRegToSize: ERR. Size parameter 0x%x invalid.\n", -+ regSize)); -+ return -1; -+ } -+ -+ -+ /* Check that aligment is a power of two */ -+ temp = alignment - 1;/* Now the alignmet is a sequance of '1' (0xffff) */ -+ -+ while(temp & 1) /* Check that alignmet LSB is set */ -+ { -+ temp = (temp >> 1); /* If LSB is set, move 'size' one bit to right */ -+ } -+ -+ /* If after the 'temp' first '0' was met we still have '1' in 'temp' */ -+ /* then 'temp' is invalid (not power of 2) */ -+ if (temp) -+ { -+ DB(mvOsPrintf("ctrlSizeToReg: ERR. Alignment parameter 0x%x invalid.\n", -+ alignment)); -+ return -1; -+ } -+ -+ regSize++; /* Now the size is 0x0100 */ -+ -+ /* Add in the "alignment" portion to the register size parameter */ -+ alignment--; /* Now the alignmet is a sequance of '1' (e.g. 0xffff) */ -+ -+ while(alignment & 1) /* Check that alignmet LSB is set */ -+ { -+ regSize = (regSize << 1); /* LSB is set, move 'size' one bit left */ -+ alignment = (alignment >> 1); -+ } -+ -+ return regSize; -+} -+ -+ -+/******************************************************************************* -+* ctrlSizeRegRoundUp - Round up given size -+* -+* DESCRIPTION: -+* This function round up a given size to a size that fits the -+* restrictions of size format given an aligment parameter. -+* to given aligment paramter. For example for size parameter 0xa1000 and -+* aligment 0x1000 the function will return 0xFF000. -+* -+* INPUT: -+* size - Size. -+* alignment - Size alignment. Note that alignment must be power of 2! -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit describing size value correspond to size in register. -+*******************************************************************************/ -+MV_U32 ctrlSizeRegRoundUp(MV_U32 size, MV_U32 alignment) -+{ -+ MV_U32 msbBit = 0; -+ MV_U32 retSize; -+ -+ /* Check if size parameter is already comply with restriction */ -+ if (!(-1 == ctrlSizeToReg(size, alignment))) -+ { -+ return size; -+ } -+ -+ while(size) -+ { -+ size = (size >> 1); -+ msbBit++; -+ } -+ -+ retSize = (1 << msbBit); -+ -+ if (retSize < alignment) -+ { -+ return alignment; -+ } -+ else -+ { -+ return retSize; -+ } -+} -+/******************************************************************************* -+* mvCtrlSysRstLengthCounterGet - Return number of milliseconds the reset button -+* was pressed and clear counter -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: number of milliseconds the reset button was pressed -+*******************************************************************************/ -+MV_U32 mvCtrlSysRstLengthCounterGet(MV_VOID) -+{ -+ static volatile MV_U32 Count = 0; -+ -+ if(!Count) { -+ Count = (MV_REG_READ(SYSRST_LENGTH_COUNTER_REG) & SLCR_COUNT_MASK); -+ Count = (Count / (MV_BOARD_REFCLK_25MHZ / 1000)); -+ /* clear counter for next boot */ -+ MV_REG_BIT_SET(SYSRST_LENGTH_COUNTER_REG, SLCR_CLR_MASK); -+ } -+ -+ DB(mvOsPrintf("mvCtrlSysRstLengthCounterGet: Reset button was pressed for %u milliseconds\n", Count)); -+ -+ return Count; -+} -+ -+MV_BOOL mvCtrlIsBootFromSPI(MV_VOID) -+{ -+ MV_U32 satr = 0; -+ satr = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ if(mvCtrlModelGet() == MV_6180_DEV_ID) -+ { -+ if (MSAR_BOOT_MODE_6180(satr) == MSAR_BOOT_SPI_WITH_BOOTROM_6180) -+ return MV_TRUE; -+ else -+ return MV_FALSE; -+ } -+ satr = satr & MSAR_BOOT_MODE_MASK; -+ if (satr == MSAR_BOOT_SPI_WITH_BOOTROM) -+ return MV_TRUE; -+ else -+ return MV_FALSE; -+} -+ -+MV_BOOL mvCtrlIsBootFromSPIUseNAND(MV_VOID) -+{ -+ MV_U32 satr = 0; -+ if(mvCtrlModelGet() == MV_6180_DEV_ID) -+ return MV_FALSE; -+ satr = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ satr = satr & MSAR_BOOT_MODE_MASK; -+ -+ if (satr == MSAR_BOOT_SPI_USE_NAND_WITH_BOOTROM) -+ return MV_TRUE; -+ else -+ return MV_FALSE; -+} -+ -+MV_BOOL mvCtrlIsBootFromNAND(MV_VOID) -+{ -+ MV_U32 satr = 0; -+ satr = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ if(mvCtrlModelGet() == MV_6180_DEV_ID) -+ { -+ if (MSAR_BOOT_MODE_6180(satr) == MSAR_BOOT_NAND_WITH_BOOTROM_6180) -+ return MV_TRUE; -+ else -+ return MV_FALSE; -+ } -+ satr = satr & MSAR_BOOT_MODE_MASK; -+ if ((satr == MSAR_BOOT_NAND_WITH_BOOTROM)) -+ return MV_TRUE; -+ else -+ return MV_FALSE; -+} -+ -+#if defined(MV_INCLUDE_CLK_PWR_CNTRL) -+/******************************************************************************* -+* mvCtrlPwrSaveOn - Set Power save mode -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+*******************************************************************************/ -+MV_VOID mvCtrlPwrSaveOn(MV_VOID) -+{ -+ unsigned long old,temp; -+ /* Disable int */ -+ __asm__ __volatile__("mrs %0, cpsr\n" -+ "orr %1, %0, #0xc0\n" -+ "msr cpsr_c, %1" -+ : "=r" (old), "=r" (temp) -+ : -+ : "memory"); -+ -+ /* Set SoC in power save */ -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, BIT11); -+ /* Wait for int */ -+ __asm__ __volatile__("mcr p15, 0, r0, c7, c0, 4"); -+ -+ /* Enabled int */ -+ __asm__ __volatile__("msr cpsr_c, %0" -+ : -+ : "r" (old) -+ : "memory"); -+} -+ -+ -+ -+/******************************************************************************* -+* mvCtrlPwrSaveOff - Go out of power save mode -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+*******************************************************************************/ -+MV_VOID mvCtrlPwrSaveOff(MV_VOID) -+{ -+ unsigned long old,temp; -+ /* Disable int */ -+ __asm__ __volatile__("mrs %0, cpsr\n" -+ "orr %1, %0, #0xc0\n" -+ "msr cpsr_c, %1" -+ : "=r" (old), "=r" (temp) -+ : -+ : "memory"); -+ -+ /* Set SoC in power save */ -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, BIT11); -+ /* Wait for int */ -+ __asm__ __volatile__("mcr p15, 0, r0, c7, c0, 4"); -+ -+ /* Enabled int */ -+ __asm__ __volatile__("msr cpsr_c, %0" -+ : -+ : "r" (old) -+ : "memory"); -+} -+ -+/******************************************************************************* -+* mvCtrlPwrClckSet - Set Power State for specific Unit -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+*******************************************************************************/ -+MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) -+{ -+ switch (unitId) -+ { -+#if defined(MV_INCLUDE_PEX) -+ case PEX_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_PEXSTOPCLOCK_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_PEXSTOPCLOCK_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_GIG_ETH) -+ case ETH_GIG_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_GESTOPCLOCK_MASK(index)); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_GESTOPCLOCK_MASK(index)); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_INTEG_SATA) -+ case SATA_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SATASTOPCLOCK_MASK(index)); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SATASTOPCLOCK_MASK(index)); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_CESA) -+ case CESA_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SESTOPCLOCK_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SESTOPCLOCK_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_USB) -+ case USB_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_USBSTOPCLOCK_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_USBSTOPCLOCK_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_AUDIO) -+ case AUDIO_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_AUDIOSTOPCLOCK_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_AUDIOSTOPCLOCK_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_TS) -+ case TS_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_TSSTOPCLOCK_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_TSSTOPCLOCK_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_SDIO) -+ case SDIO_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SDIOSTOPCLOCK_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SDIOSTOPCLOCK_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_TDM) -+ case TDM_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_TDMSTOPCLOCK_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_TDMSTOPCLOCK_MASK); -+ } -+ break; -+#endif -+ -+ default: -+ -+ break; -+ -+ } -+} -+ -+/******************************************************************************* -+* mvCtrlPwrClckGet - Get Power State of specific Unit -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+******************************************************************************/ -+MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index) -+{ -+ MV_U32 reg = MV_REG_READ(POWER_MNG_CTRL_REG); -+ MV_BOOL state = MV_TRUE; -+ -+ switch (unitId) -+ { -+#if defined(MV_INCLUDE_PEX) -+ case PEX_UNIT_ID: -+ if ((reg & PMC_PEXSTOPCLOCK_MASK) == PMC_PEXSTOPCLOCK_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ -+ break; -+#endif -+#if defined(MV_INCLUDE_GIG_ETH) -+ case ETH_GIG_UNIT_ID: -+ if ((reg & PMC_GESTOPCLOCK_MASK(index)) == PMC_GESTOPCLOCK_STOP(index)) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_SATA) -+ case SATA_UNIT_ID: -+ if ((reg & PMC_SATASTOPCLOCK_MASK(index)) == PMC_SATASTOPCLOCK_STOP(index)) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_CESA) -+ case CESA_UNIT_ID: -+ if ((reg & PMC_SESTOPCLOCK_MASK) == PMC_SESTOPCLOCK_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_USB) -+ case USB_UNIT_ID: -+ if ((reg & PMC_USBSTOPCLOCK_MASK) == PMC_USBSTOPCLOCK_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_AUDIO) -+ case AUDIO_UNIT_ID: -+ if ((reg & PMC_AUDIOSTOPCLOCK_MASK) == PMC_AUDIOSTOPCLOCK_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_TS) -+ case TS_UNIT_ID: -+ if ((reg & PMC_TSSTOPCLOCK_MASK) == PMC_TSSTOPCLOCK_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_SDIO) -+ case SDIO_UNIT_ID: -+ if ((reg & PMC_SDIOSTOPCLOCK_MASK)== PMC_SDIOSTOPCLOCK_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_TDM) -+ case TDM_UNIT_ID: -+ if ((reg & PMC_TDMSTOPCLOCK_MASK) == PMC_TDMSTOPCLOCK_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+ -+ default: -+ state = MV_TRUE; -+ break; -+ } -+ -+ -+ return state; -+} -+/******************************************************************************* -+* mvCtrlPwrMemSet - Set Power State for memory on specific Unit -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+*******************************************************************************/ -+MV_VOID mvCtrlPwrMemSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) -+{ -+ switch (unitId) -+ { -+#if defined(MV_INCLUDE_PEX) -+ case PEX_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_PEXSTOPMEM_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_PEXSTOPMEM_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_GIG_ETH) -+ case ETH_GIG_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_GESTOPMEM_MASK(index)); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_GESTOPMEM_MASK(index)); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_INTEG_SATA) -+ case SATA_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_SATASTOPMEM_MASK(index)); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_SATASTOPMEM_MASK(index)); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_CESA) -+ case CESA_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_SESTOPMEM_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_SESTOPMEM_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_USB) -+ case USB_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_USBSTOPMEM_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_USBSTOPMEM_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_AUDIO) -+ case AUDIO_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_AUDIOSTOPMEM_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_AUDIOSTOPMEM_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_XOR) -+ case XOR_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_XORSTOPMEM_MASK(index)); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_XORSTOPMEM_MASK(index)); -+ } -+ break; -+#endif -+ default: -+ -+ break; -+ -+ } -+} -+ -+/******************************************************************************* -+* mvCtrlPwrMemGet - Get Power State of memory on specific Unit -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+******************************************************************************/ -+MV_BOOL mvCtrlPwrMemGet(MV_UNIT_ID unitId, MV_U32 index) -+{ -+ MV_U32 reg = MV_REG_READ(POWER_MNG_MEM_CTRL_REG); -+ MV_BOOL state = MV_TRUE; -+ -+ switch (unitId) -+ { -+#if defined(MV_INCLUDE_PEX) -+ case PEX_UNIT_ID: -+ if ((reg & PMC_PEXSTOPMEM_MASK) == PMC_PEXSTOPMEM_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ -+ break; -+#endif -+#if defined(MV_INCLUDE_GIG_ETH) -+ case ETH_GIG_UNIT_ID: -+ if ((reg & PMC_GESTOPMEM_MASK(index)) == PMC_GESTOPMEM_STOP(index)) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_SATA) -+ case SATA_UNIT_ID: -+ if ((reg & PMC_SATASTOPMEM_MASK(index)) == PMC_SATASTOPMEM_STOP(index)) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_CESA) -+ case CESA_UNIT_ID: -+ if ((reg & PMC_SESTOPMEM_MASK) == PMC_SESTOPMEM_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_USB) -+ case USB_UNIT_ID: -+ if ((reg & PMC_USBSTOPMEM_MASK) == PMC_USBSTOPMEM_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_AUDIO) -+ case AUDIO_UNIT_ID: -+ if ((reg & PMC_AUDIOSTOPMEM_MASK) == PMC_AUDIOSTOPMEM_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_XOR) -+ case XOR_UNIT_ID: -+ if ((reg & PMC_XORSTOPMEM_MASK(index)) == PMC_XORSTOPMEM_STOP(index)) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+ -+ default: -+ state = MV_TRUE; -+ break; -+ } -+ -+ -+ return state; -+} -+#else -+MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) {return;} -+MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index) {return MV_TRUE;} -+#endif /* #if defined(MV_INCLUDE_CLK_PWR_CNTRL) */ -+ -+ -+/******************************************************************************* -+* mvMPPConfigToSPI - Change MPP[3:0] configuration to SPI mode -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+******************************************************************************/ -+MV_VOID mvMPPConfigToSPI(MV_VOID) -+{ -+ MV_U32 mppVal = 0; -+ MV_U32 bootVal = 0; -+ -+ if(!mvCtrlIsBootFromSPIUseNAND()) -+ return; -+ mppVal = 0x00002220; /* Set MPP [3:1] to SPI mode */ -+ bootVal = MV_REG_READ(mvCtrlMppRegGet(0)); -+ bootVal &= 0xffff000f; -+ mppVal |= bootVal; -+ -+ MV_REG_WRITE(mvCtrlMppRegGet(0), mppVal); -+} -+ -+ -+/******************************************************************************* -+* mvMPPConfigToDefault - Change MPP[7:0] configuration to default configuration -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+******************************************************************************/ -+MV_VOID mvMPPConfigToDefault(MV_VOID) -+{ -+ MV_U32 mppVal = 0; -+ MV_U32 bootVal = 0; -+ -+ if(!mvCtrlIsBootFromSPIUseNAND()) -+ return; -+ mppVal = mvBoardMppGet(0); -+ bootVal = MV_REG_READ(mvCtrlMppRegGet(0)); -+ mppVal &= ~0xffff000f; -+ bootVal &= 0xffff000f; -+ mppVal |= bootVal; -+ -+ MV_REG_WRITE(mvCtrlMppRegGet(0), mppVal); -+} -+ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h 2010-11-09 20:28:07.742495476 +0100 -@@ -0,0 +1,185 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvCtrlEnvLibh -+#define __INCmvCtrlEnvLibh -+ -+/* includes */ -+#include "mvSysHwConfig.h" -+#include "mvCommon.h" -+#include "mvTypes.h" -+#include "mvOs.h" -+#include "boardEnv/mvBoardEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+#include "ctrlEnv/mvCtrlEnvRegs.h" -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+ -+ -+/* typedefs */ -+ -+/* This enumerator describes the possible HW cache coherency policies the */ -+/* controllers supports. */ -+typedef enum _mvCachePolicy -+{ -+ NO_COHERENCY, /* No HW cache coherency support */ -+ WT_COHERENCY, /* HW cache coherency supported in Write Through policy */ -+ WB_COHERENCY /* HW cache coherency supported in Write Back policy */ -+}MV_CACHE_POLICY; -+ -+ -+/* The swapping is referred to a 64-bit words (as this is the controller */ -+/* internal data path width). This enumerator describes the possible */ -+/* data swap types. Below is an example of the data 0x0011223344556677 */ -+typedef enum _mvSwapType -+{ -+ MV_BYTE_SWAP, /* Byte Swap 77 66 55 44 33 22 11 00 */ -+ MV_NO_SWAP, /* No swapping 00 11 22 33 44 55 66 77 */ -+ MV_BYTE_WORD_SWAP, /* Both byte and word swap 33 22 11 00 77 66 55 44 */ -+ MV_WORD_SWAP, /* Word swap 44 55 66 77 00 11 22 33 */ -+ SWAP_TYPE_MAX /* Delimiter for this enumerator */ -+}MV_SWAP_TYPE; -+ -+/* This structure describes access rights for Access protection windows */ -+/* that can be found in IDMA, XOR, Ethernet and MPSC units. */ -+/* Note that the permission enumerator coresponds to its register format. */ -+/* For example, Read only premission is presented as "1" in register field. */ -+typedef enum _mvAccessRights -+{ -+ NO_ACCESS_ALLOWED = 0, /* No access allowed */ -+ READ_ONLY = 1, /* Read only permission */ -+ ACC_RESERVED = 2, /* Reserved access right */ -+ FULL_ACCESS = 3, /* Read and Write permission */ -+ MAX_ACC_RIGHTS -+}MV_ACCESS_RIGHTS; -+ -+ -+/* mcspLib.h API list */ -+ -+MV_STATUS mvCtrlEnvInit(MV_VOID); -+MV_U32 mvCtrlMppRegGet(MV_U32 mppGroup); -+ -+#if defined(MV_INCLUDE_PEX) -+MV_U32 mvCtrlPexMaxIfGet(MV_VOID); -+#else -+#define mvCtrlPexMaxIfGet() (0) -+#endif -+ -+#define mvCtrlPciIfMaxIfGet() (0) -+ -+#if defined(MV_INCLUDE_GIG_ETH) -+MV_U32 mvCtrlEthMaxPortGet(MV_VOID); -+#endif -+#if defined(MV_INCLUDE_XOR) -+MV_U32 mvCtrlXorMaxChanGet(MV_VOID); -+#endif -+#if defined(MV_INCLUDE_USB) -+MV_U32 mvCtrlUsbMaxGet(MV_VOID); -+#endif -+#if defined(MV_INCLUDE_NAND) -+MV_U32 mvCtrlNandSupport(MV_VOID); -+#endif -+#if defined(MV_INCLUDE_SDIO) -+MV_U32 mvCtrlSdioSupport(MV_VOID); -+#endif -+#if defined(MV_INCLUDE_TS) -+MV_U32 mvCtrlTsSupport(MV_VOID); -+#endif -+#if defined(MV_INCLUDE_AUDIO) -+MV_U32 mvCtrlAudioSupport(MV_VOID); -+#endif -+#if defined(MV_INCLUDE_TDM) -+MV_U32 mvCtrlTdmSupport(MV_VOID); -+#endif -+ -+MV_U16 mvCtrlModelGet(MV_VOID); -+MV_U8 mvCtrlRevGet(MV_VOID); -+MV_STATUS mvCtrlNameGet(char *pNameBuff); -+MV_U32 mvCtrlModelRevGet(MV_VOID); -+MV_STATUS mvCtrlModelRevNameGet(char *pNameBuff); -+MV_VOID mvCtrlAddrDecShow(MV_VOID); -+const MV_8* mvCtrlTargetNameGet(MV_TARGET target); -+MV_U32 ctrlSizeToReg(MV_U32 size, MV_U32 alignment); -+MV_U32 ctrlRegToSize(MV_U32 regSize, MV_U32 alignment); -+MV_U32 ctrlSizeRegRoundUp(MV_U32 size, MV_U32 alignment); -+MV_U32 mvCtrlSysRstLengthCounterGet(MV_VOID); -+MV_STATUS ctrlWinOverlapTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2); -+MV_STATUS ctrlWinWithinWinTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2); -+ -+MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable); -+MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index); -+MV_VOID mvCtrlPwrMemSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable); -+MV_BOOL mvCtrlIsBootFromSPI(MV_VOID); -+MV_BOOL mvCtrlIsBootFromSPIUseNAND(MV_VOID); -+MV_BOOL mvCtrlIsBootFromNAND(MV_VOID); -+#if defined(MV_INCLUDE_CLK_PWR_CNTRL) -+MV_VOID mvCtrlPwrSaveOn(MV_VOID); -+MV_VOID mvCtrlPwrSaveOff(MV_VOID); -+#endif -+MV_BOOL mvCtrlPwrMemGet(MV_UNIT_ID unitId, MV_U32 index); -+MV_VOID mvMPPConfigToSPI(MV_VOID); -+MV_VOID mvMPPConfigToDefault(MV_VOID); -+ -+ -+#endif /* __INCmvCtrlEnvLibh */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h 2010-11-09 20:28:07.772495664 +0100 -@@ -0,0 +1,419 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvCtrlEnvRegsh -+#define __INCmvCtrlEnvRegsh -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* CV Support */ -+#define PEX0_MEM0 PEX0_MEM -+#define PCI0_MEM0 PEX0_MEM -+ -+/* Controller revision info */ -+#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 -+#define PCCRIR_REVID_OFFS 0 /* Revision ID */ -+#define PCCRIR_REVID_MASK (0xff << PCCRIR_REVID_OFFS) -+ -+/* Controler environment registers offsets */ -+ -+/* Power Managment Control */ -+#define POWER_MNG_MEM_CTRL_REG 0x20118 -+ -+#define PMC_GESTOPMEM_OFFS(port) ((port)? 13 : 0) -+#define PMC_GESTOPMEM_MASK(port) (1 << PMC_GESTOPMEM_OFFS(port)) -+#define PMC_GESTOPMEM_EN(port) (0 << PMC_GESTOPMEM_OFFS(port)) -+#define PMC_GESTOPMEM_STOP(port) (1 << PMC_GESTOPMEM_OFFS(port)) -+ -+#define PMC_PEXSTOPMEM_OFFS 1 -+#define PMC_PEXSTOPMEM_MASK (1 << PMC_PEXSTOPMEM_OFFS) -+#define PMC_PEXSTOPMEM_EN (0 << PMC_PEXSTOPMEM_OFFS) -+#define PMC_PEXSTOPMEM_STOP (1 << PMC_PEXSTOPMEM_OFFS) -+ -+#define PMC_USBSTOPMEM_OFFS 2 -+#define PMC_USBSTOPMEM_MASK (1 << PMC_USBSTOPMEM_OFFS) -+#define PMC_USBSTOPMEM_EN (0 << PMC_USBSTOPMEM_OFFS) -+#define PMC_USBSTOPMEM_STOP (1 << PMC_USBSTOPMEM_OFFS) -+ -+#define PMC_DUNITSTOPMEM_OFFS 3 -+#define PMC_DUNITSTOPMEM_MASK (1 << PMC_DUNITSTOPMEM_OFFS) -+#define PMC_DUNITSTOPMEM_EN (0 << PMC_DUNITSTOPMEM_OFFS) -+#define PMC_DUNITSTOPMEM_STOP (1 << PMC_DUNITSTOPMEM_OFFS) -+ -+#define PMC_RUNITSTOPMEM_OFFS 4 -+#define PMC_RUNITSTOPMEM_MASK (1 << PMC_RUNITSTOPMEM_OFFS) -+#define PMC_RUNITSTOPMEM_EN (0 << PMC_RUNITSTOPMEM_OFFS) -+#define PMC_RUNITSTOPMEM_STOP (1 << PMC_RUNITSTOPMEM_OFFS) -+ -+#define PMC_XORSTOPMEM_OFFS(port) (5+(port*2)) -+#define PMC_XORSTOPMEM_MASK(port) (1 << PMC_XORSTOPMEM_OFFS(port)) -+#define PMC_XORSTOPMEM_EN(port) (0 << PMC_XORSTOPMEM_OFFS(port)) -+#define PMC_XORSTOPMEM_STOP(port) (1 << PMC_XORSTOPMEM_OFFS(port)) -+ -+#define PMC_SATASTOPMEM_OFFS(port) (6+(port*5)) -+#define PMC_SATASTOPMEM_MASK(port) (1 << PMC_SATASTOPMEM_OFFS(port)) -+#define PMC_SATASTOPMEM_EN(port) (0 << PMC_SATASTOPMEM_OFFS(port)) -+#define PMC_SATASTOPMEM_STOP(port) (1 << PMC_SATASTOPMEM_OFFS(port)) -+ -+#define PMC_SESTOPMEM_OFFS 8 -+#define PMC_SESTOPMEM_MASK (1 << PMC_SESTOPMEM_OFFS) -+#define PMC_SESTOPMEM_EN (0 << PMC_SESTOPMEM_OFFS) -+#define PMC_SESTOPMEM_STOP (1 << PMC_SESTOPMEM_OFFS) -+ -+#define PMC_AUDIOSTOPMEM_OFFS 9 -+#define PMC_AUDIOSTOPMEM_MASK (1 << PMC_AUDIOSTOPMEM_OFFS) -+#define PMC_AUDIOSTOPMEM_EN (0 << PMC_AUDIOSTOPMEM_OFFS) -+#define PMC_AUDIOSTOPMEM_STOP (1 << PMC_AUDIOSTOPMEM_OFFS) -+ -+#define POWER_MNG_CTRL_REG 0x2011C -+ -+#define PMC_GESTOPCLOCK_OFFS(port) ((port)? 19 : 0) -+#define PMC_GESTOPCLOCK_MASK(port) (1 << PMC_GESTOPCLOCK_OFFS(port)) -+#define PMC_GESTOPCLOCK_EN(port) (1 << PMC_GESTOPCLOCK_OFFS(port)) -+#define PMC_GESTOPCLOCK_STOP(port) (0 << PMC_GESTOPCLOCK_OFFS(port)) -+ -+#define PMC_PEXPHYSTOPCLOCK_OFFS 1 -+#define PMC_PEXPHYSTOPCLOCK_MASK (1 << PMC_PEXPHYSTOPCLOCK_OFFS) -+#define PMC_PEXPHYSTOPCLOCK_EN (1 << PMC_PEXPHYSTOPCLOCK_OFFS) -+#define PMC_PEXPHYSTOPCLOCK_STOP (0 << PMC_PEXPHYSTOPCLOCK_OFFS) -+ -+#define PMC_PEXSTOPCLOCK_OFFS 2 -+#define PMC_PEXSTOPCLOCK_MASK (1 << PMC_PEXSTOPCLOCK_OFFS) -+#define PMC_PEXSTOPCLOCK_EN (1 << PMC_PEXSTOPCLOCK_OFFS) -+#define PMC_PEXSTOPCLOCK_STOP (0 << PMC_PEXSTOPCLOCK_OFFS) -+ -+#define PMC_USBSTOPCLOCK_OFFS 3 -+#define PMC_USBSTOPCLOCK_MASK (1 << PMC_USBSTOPCLOCK_OFFS) -+#define PMC_USBSTOPCLOCK_EN (1 << PMC_USBSTOPCLOCK_OFFS) -+#define PMC_USBSTOPCLOCK_STOP (0 << PMC_USBSTOPCLOCK_OFFS) -+ -+#define PMC_SDIOSTOPCLOCK_OFFS 4 -+#define PMC_SDIOSTOPCLOCK_MASK (1 << PMC_SDIOSTOPCLOCK_OFFS) -+#define PMC_SDIOSTOPCLOCK_EN (1 << PMC_SDIOSTOPCLOCK_OFFS) -+#define PMC_SDIOSTOPCLOCK_STOP (0 << PMC_SDIOSTOPCLOCK_OFFS) -+ -+#define PMC_TSSTOPCLOCK_OFFS 5 -+#define PMC_TSSTOPCLOCK_MASK (1 << PMC_TSSTOPCLOCK_OFFS) -+#define PMC_TSSTOPCLOCK_EN (1 << PMC_TSSTOPCLOCK_OFFS) -+#define PMC_TSSTOPCLOCK_STOP (0 << PMC_TSSTOPCLOCK_OFFS) -+ -+#define PMC_AUDIOSTOPCLOCK_OFFS 9 -+#define PMC_AUDIOSTOPCLOCK_MASK (1 << PMC_AUDIOSTOPCLOCK_OFFS) -+#define PMC_AUDIOSTOPCLOCK_EN (1 << PMC_AUDIOSTOPCLOCK_OFFS) -+#define PMC_AUDIOSTOPCLOCK_STOP (0 << PMC_AUDIOSTOPCLOCK_OFFS) -+ -+#define PMC_POWERSAVE_OFFS 11 -+#define PMC_POWERSAVE_MASK (1 << PMC_POWERSAVE_OFFS) -+#define PMC_POWERSAVE_EN (1 << PMC_POWERSAVE_OFFS) -+#define PMC_POWERSAVE_STOP (0 << PMC_POWERSAVE_OFFS) -+ -+ -+ -+ -+#define PMC_SATASTOPCLOCK_OFFS(port) (14+(port)) -+#define PMC_SATASTOPCLOCK_MASK(port) (1 << PMC_SATASTOPCLOCK_OFFS(port)) -+#define PMC_SATASTOPCLOCK_EN(port) (1 << PMC_SATASTOPCLOCK_OFFS(port)) -+#define PMC_SATASTOPCLOCK_STOP(port) (0 << PMC_SATASTOPCLOCK_OFFS(port)) -+ -+#define PMC_SESTOPCLOCK_OFFS 17 -+#define PMC_SESTOPCLOCK_MASK (1 << PMC_SESTOPCLOCK_OFFS) -+#define PMC_SESTOPCLOCK_EN (1 << PMC_SESTOPCLOCK_OFFS) -+#define PMC_SESTOPCLOCK_STOP (0 << PMC_SESTOPCLOCK_OFFS) -+ -+#define PMC_TDMSTOPCLOCK_OFFS 20 -+#define PMC_TDMSTOPCLOCK_MASK (1 << PMC_TDMSTOPCLOCK_OFFS) -+#define PMC_TDMSTOPCLOCK_EN (1 << PMC_TDMSTOPCLOCK_OFFS) -+#define PMC_TDMSTOPCLOCK_STOP (0 << PMC_TDMSTOPCLOCK_OFFS) -+ -+ -+/* Controler environment registers offsets */ -+#define MPP_CONTROL_REG0 0x10000 -+#define MPP_CONTROL_REG1 0x10004 -+#define MPP_CONTROL_REG2 0x10008 -+#define MPP_CONTROL_REG3 0x1000C -+#define MPP_CONTROL_REG4 0x10010 -+#define MPP_CONTROL_REG5 0x10014 -+#define MPP_CONTROL_REG6 0x10018 -+#define MPP_SAMPLE_AT_RESET 0x10030 -+#define CHIP_BOND_REG 0x10034 -+#define SYSRST_LENGTH_COUNTER_REG 0x10050 -+#define SLCR_COUNT_OFFS 0 -+#define SLCR_COUNT_MASK (0x1FFFFFFF << SLCR_COUNT_OFFS) -+#define SLCR_CLR_OFFS 31 -+#define SLCR_CLR_MASK (1 << SLCR_CLR_OFFS) -+#define PCKG_OPT_MASK 0x3 -+#define MPP_OUTPUT_DRIVE_REG 0x100E0 -+#define MPP_RGMII0_OUTPUT_DRIVE_OFFS 7 -+#define MPP_3_3_RGMII0_OUTPUT_DRIVE (0x0 << MPP_RGMII0_OUTPUT_DRIVE_OFFS) -+#define MPP_1_8_RGMII0_OUTPUT_DRIVE (0x1 << MPP_RGMII0_OUTPUT_DRIVE_OFFS) -+#define MPP_RGMII1_OUTPUT_DRIVE_OFFS 15 -+#define MPP_3_3_RGMII1_OUTPUT_DRIVE (0x0 << MPP_RGMII1_OUTPUT_DRIVE_OFFS) -+#define MPP_1_8_RGMII1_OUTPUT_DRIVE (0x1 << MPP_RGMII1_OUTPUT_DRIVE_OFFS) -+ -+#define MSAR_BOOT_MODE_OFFS 12 -+#define MSAR_BOOT_MODE_MASK (0x7 << MSAR_BOOT_MODE_OFFS) -+#define MSAR_BOOT_NAND_WITH_BOOTROM (0x5 << MSAR_BOOT_MODE_OFFS) -+#define MSAR_BOOT_SPI_WITH_BOOTROM (0x4 << MSAR_BOOT_MODE_OFFS) -+#define MSAR_BOOT_SPI_USE_NAND_WITH_BOOTROM (0x2 << MSAR_BOOT_MODE_OFFS) -+ -+#define MSAR_BOOT_MODE_6180(X) (((X & 0x3000) >> 12) | \ -+ ((X & 0x2) << 1)) -+#define MSAR_BOOT_SPI_WITH_BOOTROM_6180 0x1 -+#define MSAR_BOOT_NAND_WITH_BOOTROM_6180 0x5 -+ -+#define MSAR_TCLCK_OFFS 21 -+#define MSAR_TCLCK_MASK (0x1 << MSAR_TCLCK_OFFS) -+#define MSAR_TCLCK_166 (0x1 << MSAR_TCLCK_OFFS) -+#define MSAR_TCLCK_200 (0x0 << MSAR_TCLCK_OFFS) -+ -+ -+#define MSAR_CPUCLCK_EXTRACT(X) (((X & 0x2) >> 1) | ((X & 0x400000) >> 21) | \ -+ ((X & 0x18) >> 1)) -+ -+#define MSAR_CPUCLCK_OFFS_6180 2 -+#define MSAR_CPUCLCK_MASK_6180 (0x7 << MSAR_CPUCLCK_OFFS_6180) -+ -+#define MSAR_DDRCLCK_RTIO_OFFS 5 -+#define MSAR_DDRCLCK_RTIO_MASK (0xF << MSAR_DDRCLCK_RTIO_OFFS) -+ -+#define MSAR_L2CLCK_EXTRACT(X) (((X & 0x600) >> 9) | ((X & 0x80000) >> 17)) -+ -+#ifndef MV_ASMLANGUAGE -+/* CPU clock for 6281,6192 0->Resereved */ -+#define MV_CPU_CLCK_TBL { 0, 0, 0, 0, \ -+ 600000000, 0, 800000000, 1000000000, \ -+ 0, 1200000000, 0, 0, \ -+ 1500000000, 0, 0, 0} -+ -+/* DDR clock RATIO for 6281,6192 {0,0}->Reserved */ -+#define MV_DDR_CLCK_RTIO_TBL {\ -+ {0, 0}, {0, 0}, {2, 1}, {0, 0}, \ -+ {3, 1}, {0, 0}, {4, 1}, {9, 2}, \ -+ {5, 1}, {6, 1}, {0, 0}, {0, 0}, \ -+ {0, 0}, {0, 0}, {0, 0}, {0, 0} \ -+} -+ -+/* L2 clock RATIO for 6281,6192 {1,1}->Reserved */ -+#define MV_L2_CLCK_RTIO_TBL {\ -+ {0, 0}, {2, 1}, {0, 0}, {3, 1}, \ -+ {0, 0}, {0, 0}, {0, 0}, {0, 0} \ -+} -+ -+/* 6180 have different clk reset sampling */ -+/* ARM CPU, DDR, L2 clock for 6180 {0,0,0}->Reserved */ -+#define MV_CPU6180_DDR_L2_CLCK_TBL { \ -+ {0, 0, 0 },\ -+ {0, 0, 0 },\ -+ {0, 0, 0 },\ -+ {0, 0, 0 },\ -+ {0, 0, 0 },\ -+ {600000000, 200000000, 300000000 },\ -+ {800000000, 200000000, 400000000 },\ -+ {0, 0, 0 }\ -+} -+ -+ -+ -+/* These macros help units to identify a target Mbus Arbiter group */ -+#define MV_TARGET_IS_DRAM(target) \ -+ ((target >= SDRAM_CS0) && (target <= SDRAM_CS3)) -+ -+#define MV_TARGET_IS_PEX0(target) \ -+ ((target >= PEX0_MEM) && (target <= PEX0_IO)) -+ -+#define MV_TARGET_IS_PEX1(target) 0 -+ -+#define MV_TARGET_IS_PEX(target) (MV_TARGET_IS_PEX0(target) || MV_TARGET_IS_PEX1(target)) -+ -+#define MV_TARGET_IS_DEVICE(target) \ -+ ((target >= DEVICE_CS0) && (target <= DEVICE_CS3)) -+ -+#define MV_PCI_DRAM_BAR_TO_DRAM_TARGET(bar) 0 -+ -+#define MV_TARGET_IS_AS_BOOT(target) ((target) == (sampleAtResetTargetArray[ \ -+ (mvCtrlModelGet() == MV_6180_DEV_ID)? MSAR_BOOT_MODE_6180 \ -+ (MV_REG_READ(MPP_SAMPLE_AT_RESET)):((MV_REG_READ(MPP_SAMPLE_AT_RESET)\ -+ & MSAR_BOOT_MODE_MASK) >> MSAR_BOOT_MODE_OFFS)])) -+ -+ -+#define MV_CHANGE_BOOT_CS(target) (((target) == DEV_BOOCS)?\ -+ sampleAtResetTargetArray[(mvCtrlModelGet() == MV_6180_DEV_ID)? \ -+ MSAR_BOOT_MODE_6180(MV_REG_READ(MPP_SAMPLE_AT_RESET)): \ -+ ((MV_REG_READ(MPP_SAMPLE_AT_RESET) & MSAR_BOOT_MODE_MASK)\ -+ >> MSAR_BOOT_MODE_OFFS)]:(target)) -+ -+#define TCLK_TO_COUNTER_RATIO 1 /* counters running in Tclk */ -+ -+#define BOOT_TARGETS_NAME_ARRAY { \ -+ TBL_TERM, \ -+ TBL_TERM, \ -+ BOOT_ROM_CS, \ -+ TBL_TERM, \ -+ BOOT_ROM_CS, \ -+ BOOT_ROM_CS, \ -+ TBL_TERM, \ -+ TBL_TERM \ -+} -+ -+#define BOOT_TARGETS_NAME_ARRAY_6180 { \ -+ TBL_TERM, \ -+ BOOT_ROM_CS, \ -+ TBL_TERM, \ -+ TBL_TERM, \ -+ TBL_TERM, \ -+ BOOT_ROM_CS, \ -+ TBL_TERM, \ -+ TBL_TERM \ -+} -+ -+ -+/* For old competability */ -+#define DEVICE_CS0 NFLASH_CS -+#define DEVICE_CS1 SPI_CS -+#define DEVICE_CS2 BOOT_ROM_CS -+#define DEVICE_CS3 DEV_BOOCS -+#define MV_BOOTDEVICE_INDEX 0 -+ -+#define START_DEV_CS DEV_CS0 -+#define DEV_TO_TARGET(dev) ((dev) + DEVICE_CS0) -+ -+#define PCI_IF0_MEM0 PEX0_MEM -+#define PCI_IF0_IO PEX0_IO -+ -+ -+/* This enumerator defines the Marvell controller target ID */ -+typedef enum _mvTargetId -+{ -+ DRAM_TARGET_ID = 0 , /* Port 0 -> DRAM interface */ -+ DEV_TARGET_ID = 1, /* Port 1 -> Nand/SPI */ -+ PEX0_TARGET_ID = 4 , /* Port 4 -> PCI Express0 */ -+ CRYPT_TARGET_ID = 3 , /* Port 3 --> Crypto Engine */ -+ SAGE_TARGET_ID = 12 , /* Port 12 -> SAGE Unit */ -+ MAX_TARGETS_ID -+}MV_TARGET_ID; -+ -+ -+/* This enumerator described the possible Controller paripheral targets. */ -+/* Controller peripherals are designated memory/IO address spaces that the */ -+/* controller can access. They are also refered as "targets" */ -+typedef enum _mvTarget -+{ -+ TBL_TERM = -1, /* none valid target, used as targets list terminator*/ -+ SDRAM_CS0, /* SDRAM chip select 0 */ -+ SDRAM_CS1, /* SDRAM chip select 1 */ -+ SDRAM_CS2, /* SDRAM chip select 2 */ -+ SDRAM_CS3, /* SDRAM chip select 3 */ -+ PEX0_MEM, /* PCI Express 0 Memory */ -+ PEX0_IO, /* PCI Express 0 IO */ -+ INTER_REGS, /* Internal registers */ -+ NFLASH_CS, /* NFLASH_CS */ -+ SPI_CS, /* SPI_CS */ -+ BOOT_ROM_CS, /* BOOT_ROM_CS */ -+ DEV_BOOCS, /* DEV_BOOCS */ -+ CRYPT_ENG, /* Crypto Engine */ -+#ifdef MV_INCLUDE_SAGE -+ SAGE_UNIT, /* SAGE Unit */ -+#endif -+ MAX_TARGETS -+ -+}MV_TARGET; -+ -+#define TARGETS_DEF_ARRAY { \ -+ {0x0E, DRAM_TARGET_ID }, /* SDRAM_CS0 */ \ -+ {0x0D, DRAM_TARGET_ID }, /* SDRAM_CS1 */ \ -+ {0x0B, DRAM_TARGET_ID }, /* SDRAM_CS0 */ \ -+ {0x07, DRAM_TARGET_ID }, /* SDRAM_CS1 */ \ -+ {0xE8, PEX0_TARGET_ID }, /* PEX0_MEM */ \ -+ {0xE0, PEX0_TARGET_ID }, /* PEX0_IO */ \ -+ {0xFF, 0xFF }, /* INTER_REGS */ \ -+ {0x2F, DEV_TARGET_ID }, /* NFLASH_CS */ \ -+ {0x1E, DEV_TARGET_ID }, /* SPI_CS */ \ -+ {0x1D, DEV_TARGET_ID }, /* BOOT_ROM_CS */ \ -+ {0x1E, DEV_TARGET_ID }, /* DEV_BOOCS */ \ -+ {0x01, CRYPT_TARGET_ID}, /* CRYPT_ENG */ \ -+ {0x00, SAGE_TARGET_ID } \ -+} -+ -+ -+#define TARGETS_NAME_ARRAY { \ -+ "SDRAM_CS0", /* SDRAM_CS0 */ \ -+ "SDRAM_CS1", /* SDRAM_CS1 */ \ -+ "SDRAM_CS2", /* SDRAM_CS2 */ \ -+ "SDRAM_CS3", /* SDRAM_CS3 */ \ -+ "PEX0_MEM", /* PEX0_MEM */ \ -+ "PEX0_IO", /* PEX0_IO */ \ -+ "INTER_REGS", /* INTER_REGS */ \ -+ "NFLASH_CS", /* NFLASH_CS */ \ -+ "SPI_CS", /* SPI_CS */ \ -+ "BOOT_ROM_CS", /* BOOT_ROM_CS */ \ -+ "DEV_BOOTCS", /* DEV_BOOCS */ \ -+ "CRYPT_ENG", /* CRYPT_ENG */ \ -+ "SAGE_UNIT" /* SAGE_UNIT */ \ -+} -+#endif /* MV_ASMLANGUAGE */ -+ -+ -+#endif -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h 2010-11-09 20:28:07.802495420 +0100 -@@ -0,0 +1,257 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvCtrlEnvSpech -+#define __INCmvCtrlEnvSpech -+ -+#include "mvDeviceId.h" -+#include "mvSysHwConfig.h" -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+#define MV_ARM_SOC -+#define SOC_NAME_PREFIX "MV88F" -+ -+ -+/* units base and port numbers */ -+#ifdef MV_ASMLANGUAGE -+#define XOR_UNIT_BASE(unit) 0x60800 -+#else -+#define MV_XOR_REG_BASE 0x60000 -+#define XOR_UNIT_BASE(unit) ((unit)? 0x60900:0x60800) -+#endif -+ -+#define TDM_REG_BASE 0xD0000 -+#define USB_REG_BASE(dev) 0x50000 -+#define AUDIO_REG_BASE 0xA0000 -+#define SATA_REG_BASE 0x80000 -+#define MV_CESA_REG_BASE 0x3D000 -+#define MV_CESA_TDMA_REG_BASE 0x30000 -+#define MV_SDIO_REG_BASE 0x90000 -+#define MV_ETH_REG_BASE(port) (((port) == 0) ? 0x72000 : 0x76000) -+#define MV_UART_CHAN_BASE(chanNum) (0x12000 + (chanNum * 0x100)) -+#define DRAM_BASE 0x0 -+#define CNTMR_BASE 0x20300 -+#define TWSI_SLAVE_BASE(chanNum) 0x11000 -+#define PEX_IF_BASE(pexIf) 0x40000 -+#define MPP_REG_BASE 0x10000 -+#define TSU_GLOBAL_REG_BASE 0xB4000 -+#define MAX_AHB_TO_MBUS_REG_BASE 0x20000 -+ -+#define INTER_REGS_SIZE _1M -+/* This define describes the TWSI interrupt bit and location */ -+#define TWSI_CPU_MAIN_INT_CAUSE_REG 0x20200 -+#define TWSI0_CPU_MAIN_INT_BIT (1<<29) -+#define TWSI_SPEED 100000 -+ -+#define MV_GPP_MAX_GROUP 2 -+#define MV_CNTMR_MAX_COUNTER 2 -+#define MV_UART_MAX_CHAN 2 -+#define MV_XOR_MAX_UNIT 2 -+#define MV_XOR_MAX_CHAN 4 /* total channels for all units together*/ -+#define MV_XOR_MAX_CHAN_PER_UNIT 2 /* channels for units */ -+#define MV_SATA_MAX_CHAN 2 -+ -+#define MV_6281_MPP_MAX_MODULE 2 -+#define MV_6192_MPP_MAX_MODULE 1 -+#define MV_6190_MPP_MAX_MODULE 1 -+#define MV_6180_MPP_MAX_MODULE 2 -+#define MV_6281_MPP_MAX_GROUP 7 -+#define MV_6192_MPP_MAX_GROUP 4 -+#define MV_6190_MPP_MAX_GROUP 4 -+#define MV_6180_MPP_MAX_GROUP 3 -+ -+#define MV_DRAM_MAX_CS 4 -+ -+/* This define describes the maximum number of supported PCI\PCIX Interfaces*/ -+#define MV_PCI_MAX_IF 0 -+#define MV_PCI_START_IF 0 -+ -+/* This define describes the maximum number of supported PEX Interfaces */ -+#define MV_INCLUDE_PEX0 -+#define MV_DISABLE_PEX_DEVICE_BAR -+#define MV_PEX_MAX_IF 1 -+#define MV_PEX_START_IF MV_PCI_MAX_IF -+ -+/* This define describes the maximum number of supported PCI Interfaces */ -+#define MV_PCI_IF_MAX_IF (MV_PEX_MAX_IF+MV_PCI_MAX_IF) -+ -+#define MV_ETH_MAX_PORTS 2 -+#define MV_6281_ETH_MAX_PORTS 2 -+#define MV_6192_ETH_MAX_PORTS 2 -+#define MV_6190_ETH_MAX_PORTS 1 -+#define MV_6180_ETH_MAX_PORTS 1 -+ -+#define MV_IDMA_MAX_CHAN 0 -+ -+#define MV_USB_MAX_PORTS 1 -+ -+#define MV_USB_VERSION 1 -+ -+ -+#define MV_6281_NAND 1 -+#define MV_6192_NAND 1 -+#define MV_6190_NAND 1 -+#define MV_6180_NAND 0 -+ -+#define MV_6281_SDIO 1 -+#define MV_6192_SDIO 1 -+#define MV_6190_SDIO 1 -+#define MV_6180_SDIO 1 -+ -+#define MV_6281_TS 1 -+#define MV_6192_TS 1 -+#define MV_6190_TS 0 -+#define MV_6180_TS 0 -+ -+#define MV_6281_AUDIO 1 -+#define MV_6192_AUDIO 1 -+#define MV_6190_AUDIO 0 -+#define MV_6180_AUDIO 1 -+ -+#define MV_6281_TDM 1 -+#define MV_6192_TDM 1 -+#define MV_6190_TDM 0 -+#define MV_6180_TDM 0 -+ -+#define MV_DEVICE_MAX_CS 4 -+ -+/* Others */ -+#define PEX_HOST_BUS_NUM(pciIf) (pciIf) -+#define PEX_HOST_DEV_NUM(pciIf) 0 -+ -+#define PCI_IO(pciIf) (PEX0_IO) -+#define PCI_MEM(pciIf, memNum) (PEX0_MEM0) -+/* CESA version #2: One channel, 2KB SRAM, TDMA */ -+#if defined(MV_CESA_CHAIN_MODE_SUPPORT) -+ #define MV_CESA_VERSION 3 -+#else -+#define MV_CESA_VERSION 2 -+#endif -+#define MV_CESA_SRAM_SIZE 2*1024 -+/* This define describes the maximum number of supported Ethernet ports */ -+#define MV_ETH_VERSION 4 -+#define MV_ETH_MAX_RXQ 8 -+#define MV_ETH_MAX_TXQ 8 -+#define MV_ETH_PORT_SGMII { MV_FALSE, MV_FALSE } -+/* This define describes the the support of USB */ -+#define MV_USB_VERSION 1 -+ -+#define MV_INCLUDE_SDRAM_CS0 -+#define MV_INCLUDE_SDRAM_CS1 -+#define MV_INCLUDE_SDRAM_CS2 -+#define MV_INCLUDE_SDRAM_CS3 -+ -+#define MV_INCLUDE_DEVICE_CS0 -+#define MV_INCLUDE_DEVICE_CS1 -+#define MV_INCLUDE_DEVICE_CS2 -+#define MV_INCLUDE_DEVICE_CS3 -+ -+#define MPP_GROUP_1_TYPE {\ -+ {0, 0, 0}, /* Reserved for AUTO */ \ -+ {0x22220000, 0x22222222, 0x2222}, /* TDM */ \ -+ {0x44440000, 0x00044444, 0x0000}, /* AUDIO */ \ -+ {0x33330000, 0x33003333, 0x0033}, /* RGMII */ \ -+ {0x33330000, 0x03333333, 0x0033}, /* GMII */ \ -+ {0x11110000, 0x11111111, 0x0001}, /* TS */ \ -+ {0x33330000, 0x33333333, 0x3333} /* MII */ \ -+} -+ -+#define MPP_GROUP_2_TYPE {\ -+ {0, 0, 0}, /* Reserved for AUTO */ \ -+ {0x22220000, 0x22222222, 0x22}, /* TDM */ \ -+ {0x44440000, 0x00044444, 0x0}, /* AUDIO */ \ -+ {0, 0, 0}, /* N_A */ \ -+ {0, 0, 0}, /* N_A */ \ -+ {0x11110000, 0x11111111, 0x01} /* TS */ \ -+} -+ -+#ifndef MV_ASMLANGUAGE -+ -+/* This enumerator defines the Marvell Units ID */ -+typedef enum _mvUnitId -+{ -+ DRAM_UNIT_ID, -+ PEX_UNIT_ID, -+ ETH_GIG_UNIT_ID, -+ USB_UNIT_ID, -+ IDMA_UNIT_ID, -+ XOR_UNIT_ID, -+ SATA_UNIT_ID, -+ TDM_UNIT_ID, -+ UART_UNIT_ID, -+ CESA_UNIT_ID, -+ SPI_UNIT_ID, -+ AUDIO_UNIT_ID, -+ SDIO_UNIT_ID, -+ TS_UNIT_ID, -+ MAX_UNITS_ID -+ -+}MV_UNIT_ID; -+ -+#endif -+ -+#endif /* __INCmvCtrlEnvSpech */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c 2010-11-09 20:28:07.842495395 +0100 -@@ -0,0 +1,1048 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+/* includes */ -+#include "ctrlEnv/sys/mvAhbToMbus.h" -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+ -+#undef MV_DEBUG -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+/* typedefs */ -+ -+ -+/* CPU address remap registers offsets are inconsecutive. This struct */ -+/* describes address remap register offsets */ -+typedef struct _ahbToMbusRemapRegOffs -+{ -+ MV_U32 lowRegOffs; /* Low 32-bit remap register offset */ -+ MV_U32 highRegOffs; /* High 32 bit remap register offset */ -+}AHB_TO_MBUS_REMAP_REG_OFFS; -+ -+/* locals */ -+static MV_STATUS ahbToMbusRemapRegOffsGet (MV_U32 winNum, -+ AHB_TO_MBUS_REMAP_REG_OFFS *pRemapRegs); -+ -+/******************************************************************************* -+* mvAhbToMbusInit - Initialize Ahb To Mbus Address Map ! -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK laways. -+* -+*******************************************************************************/ -+MV_STATUS mvAhbToMbusInit(void) -+{ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvAhbToMbusWinSet - Set CPU-to-peripheral winNum address window -+* -+* DESCRIPTION: -+* This function sets -+* address window, also known as address decode window. -+* A new address decode window is set for specified winNum address window. -+* If address decode window parameter structure enables the window, -+* the routine will also enable the winNum window, allowing CPU to access -+* the winNum window. -+* -+* INPUT: -+* winNum - Windows number. -+* pAddrDecWin - CPU winNum window data structure. -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_OK if CPU winNum window was set correctly, MV_ERROR in case of -+* address window overlapps with other active CPU winNum window or -+* trying to assign 36bit base address while CPU does not support that. -+* The function returns MV_NOT_SUPPORTED, if the winNum is unsupported. -+* -+*******************************************************************************/ -+MV_STATUS mvAhbToMbusWinSet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin) -+{ -+ MV_TARGET_ATTRIB targetAttribs; -+ MV_DEC_REGS decRegs; -+ -+ /* Parameter checking */ -+ if (winNum >= MAX_AHB_TO_MBUS_WINS) -+ { -+ mvOsPrintf("mvAhbToMbusWinSet: ERR. Invalid winNum %d\n", winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ -+ /* read base register*/ -+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum)); -+ } -+ else -+ { -+ decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_INTEREG_REG); -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvAhbToMbusWinSet:Error setting AHB to MBUS window %d to "\ -+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, -+ mvCtrlTargetNameGet(pAddrDecWin->target), -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ /* read control register*/ -+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ decRegs.sizeReg = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum)); -+ } -+ -+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) -+ { -+ mvOsPrintf("mvAhbToMbusWinSet:mvCtrlAddrDecToReg Failed\n"); -+ return MV_ERROR; -+ } -+ -+ /* enable\Disable */ -+ if (MV_TRUE == pAddrDecWin->enable) -+ { -+ decRegs.sizeReg |= ATMWCR_WIN_ENABLE; -+ } -+ else -+ { -+ decRegs.sizeReg &= ~ATMWCR_WIN_ENABLE; -+ } -+ -+ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); -+ -+ /* set attributes */ -+ decRegs.sizeReg &= ~ATMWCR_WIN_ATTR_MASK; -+ decRegs.sizeReg |= targetAttribs.attrib << ATMWCR_WIN_ATTR_OFFS; -+ /* set target ID */ -+ decRegs.sizeReg &= ~ATMWCR_WIN_TARGET_MASK; -+ decRegs.sizeReg |= targetAttribs.targetId << ATMWCR_WIN_TARGET_OFFS; -+ -+#if !defined(MV_RUN_FROM_FLASH) -+ /* To be on the safe side we disable the window before writing the */ -+ /* new values. */ -+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ mvAhbToMbusWinEnable(winNum,MV_FALSE); -+ } -+#endif -+ -+ /* 3) Write to address decode Base Address Register */ -+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum), decRegs.baseReg); -+ } -+ else -+ { -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_INTEREG_REG, decRegs.baseReg); -+ } -+ -+ -+ /* Internal register space have no size */ -+ /* register. Do not perform size register assigment for those targets */ -+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ /* Write to address decode Size Register */ -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), decRegs.sizeReg); -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvAhbToMbusWinGet - Get CPU-to-peripheral winNum address window -+* -+* DESCRIPTION: -+* Get the CPU peripheral winNum address window. -+* -+* INPUT: -+* winNum - Peripheral winNum enumerator -+* -+* OUTPUT: -+* pAddrDecWin - CPU winNum window information data structure. -+* -+* RETURN: -+* MV_OK if winNum exist, MV_ERROR otherwise. -+* -+*******************************************************************************/ -+MV_STATUS mvAhbToMbusWinGet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin) -+{ -+ MV_DEC_REGS decRegs; -+ MV_TARGET_ATTRIB targetAttrib; -+ -+ -+ /* Parameter checking */ -+ if (winNum >= MAX_AHB_TO_MBUS_WINS) -+ { -+ mvOsPrintf("mvAhbToMbusWinGet: ERR. Invalid winNum %d\n", winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ -+ /* Internal register space size have no size register*/ -+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ decRegs.sizeReg = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum)); -+ } -+ else -+ { -+ decRegs.sizeReg = 0; -+ } -+ -+ -+ /* Read base and size */ -+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum)); -+ } -+ else -+ { -+ decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_INTEREG_REG); -+ } -+ -+ -+ -+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) -+ { -+ mvOsPrintf("mvAhbToMbusWinGet: mvCtrlRegToAddrDec Failed \n"); -+ return MV_ERROR; -+ } -+ -+ if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ pAddrDecWin->addrWin.size = INTER_REGS_SIZE; -+ pAddrDecWin->target = INTER_REGS; -+ pAddrDecWin->enable = MV_TRUE; -+ -+ return MV_OK; -+ } -+ -+ -+ if (decRegs.sizeReg & ATMWCR_WIN_ENABLE) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ -+ } -+ -+ -+ -+ if (-1 == pAddrDecWin->addrWin.size) -+ { -+ return MV_ERROR; -+ } -+ -+ /* attrib and targetId */ -+ targetAttrib.attrib = (decRegs.sizeReg & ATMWCR_WIN_ATTR_MASK) >> -+ ATMWCR_WIN_ATTR_OFFS; -+ targetAttrib.targetId = (decRegs.sizeReg & ATMWCR_WIN_TARGET_MASK) >> -+ ATMWCR_WIN_TARGET_OFFS; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvAhbToMbusWinTargetGet - Get Window number associated with target -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_U32 mvAhbToMbusWinTargetGet(MV_TARGET target) -+{ -+ MV_AHB_TO_MBUS_DEC_WIN decWin; -+ MV_U32 winNum; -+ -+ /* Check parameters */ -+ if (target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetGet: target %d is Illigal\n", target); -+ return 0xffffffff; -+ } -+ -+ if (INTER_REGS == target) -+ { -+ return MV_AHB_TO_MBUS_INTREG_WIN; -+ } -+ -+ for (winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS ; winNum++) -+ { -+ if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) -+ continue; -+ -+ if (mvAhbToMbusWinGet(winNum,&decWin) != MV_OK) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetGet: mvAhbToMbusWinGet fail\n"); -+ return 0xffffffff; -+ -+ } -+ -+ if (decWin.enable == MV_TRUE) -+ { -+ if (decWin.target == target) -+ { -+ return winNum; -+ } -+ -+ } -+ -+ } -+ -+ return 0xFFFFFFFF; -+ -+ -+} -+ -+/******************************************************************************* -+* mvAhbToMbusWinAvailGet - Get First Available window number. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_U32 mvAhbToMbusWinAvailGet(MV_VOID) -+{ -+ MV_AHB_TO_MBUS_DEC_WIN decWin; -+ MV_U32 winNum; -+ -+ for (winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS ; winNum++) -+ { -+ if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) -+ continue; -+ -+ if (mvAhbToMbusWinGet(winNum,&decWin) != MV_OK) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetGet: mvAhbToMbusWinGet fail\n"); -+ return 0xffffffff; -+ -+ } -+ -+ if (decWin.enable == MV_FALSE) -+ { -+ return winNum; -+ } -+ -+ } -+ -+ return 0xFFFFFFFF; -+} -+ -+ -+/******************************************************************************* -+* mvAhbToMbusWinEnable - Enable/disable a CPU address decode window -+* -+* DESCRIPTION: -+* This function enable/disable a CPU address decode window. -+* if parameter 'enable' == MV_TRUE the routine will enable the -+* window, thus enabling CPU accesses (before enabling the window it is -+* tested for overlapping). Otherwise, the window will be disabled. -+* -+* INPUT: -+* winNum - Peripheral winNum enumerator. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_ERROR if protection window number was wrong, or the window -+* overlapps other winNum window. -+* -+*******************************************************************************/ -+MV_STATUS mvAhbToMbusWinEnable(MV_U32 winNum, MV_BOOL enable) -+{ -+ -+ /* Parameter checking */ -+ if (winNum >= MAX_AHB_TO_MBUS_WINS) -+ { -+ mvOsPrintf("mvAhbToMbusWinEnable: ERR. Invalid winNum %d\n", winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ /* Internal registers bar can't be disable or enabled */ -+ if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ return (enable ? MV_OK : MV_ERROR); -+ } -+ -+ if (enable == MV_TRUE) -+ { -+ /* enable the window */ -+ MV_REG_BIT_SET(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ATMWCR_WIN_ENABLE); -+ } -+ else -+ { /* Disable address decode winNum window */ -+ MV_REG_BIT_RESET(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ATMWCR_WIN_ENABLE); -+ } -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvAhbToMbusWinRemap - Set CPU remap register for address windows. -+* -+* DESCRIPTION: -+* After a CPU address hits one of PCI address decode windows there is an -+* option to remap the address to a different one. For example, CPU -+* executes a read from PCI winNum window address 0x1200.0000. This -+* can be modified so the address on the PCI bus would be 0x1400.0000 -+* Using the PCI address remap mechanism. -+* -+* INPUT: -+* winNum - Peripheral winNum enumerator. Must be a PCI winNum. -+* pAddrDecWin - CPU winNum window information data structure. -+* Note that caller has to fill in the base field only. The -+* size field is ignored. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR if winNum is not a PCI one, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_U32 mvAhbToMbusWinRemap(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 baseAddr; -+ AHB_TO_MBUS_REMAP_REG_OFFS remapRegOffs; -+ -+ MV_U32 effectiveBaseAddress=0, -+ baseAddrValue=0,windowSizeValue=0; -+ -+ -+ /* Get registers offsets of given winNum */ -+ if (MV_NO_SUCH == ahbToMbusRemapRegOffsGet(winNum, &remapRegOffs)) -+ { -+ return 0xffffffff; -+ } -+ -+ /* 1) Set address remap low */ -+ baseAddr = pAddrWin->baseLow; -+ -+ /* Check base address aligment */ -+ /* -+ if (MV_IS_NOT_ALIGN(baseAddr, ATMWRLR_REMAP_LOW_ALIGNMENT)) -+ { -+ mvOsPrintf("mvAhbToMbusPciRemap: Warning. Target base 0x%x unaligned\n", -+ baseAddr); -+ return MV_ERROR; -+ } -+ */ -+ -+ /* BaseLow[31:16] => base register [31:16] */ -+ baseAddr = baseAddr & ATMWRLR_REMAP_LOW_MASK; -+ -+ MV_REG_WRITE(remapRegOffs.lowRegOffs, baseAddr); -+ -+ MV_REG_WRITE(remapRegOffs.highRegOffs, pAddrWin->baseHigh); -+ -+ -+ baseAddrValue = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum)); -+ windowSizeValue = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum)); -+ -+ baseAddrValue &= ATMWBR_BASE_MASK; -+ windowSizeValue &=ATMWCR_WIN_SIZE_MASK; -+ -+ /* Start calculating the effective Base Address */ -+ effectiveBaseAddress = baseAddrValue ; -+ -+ /* The effective base address will be combined from the chopped (if any) -+ remap value (according to the size value and remap mechanism) and the -+ window's base address */ -+ effectiveBaseAddress |= (((windowSizeValue) | 0xffff) & pAddrWin->baseLow); -+ /* If the effectiveBaseAddress exceed the window boundaries return an -+ invalid value. */ -+ -+ if (effectiveBaseAddress > (baseAddrValue + (windowSizeValue | 0xffff))) -+ { -+ mvOsPrintf("mvAhbToMbusPciRemap: Error\n"); -+ return 0xffffffff; -+ } -+ -+ return effectiveBaseAddress; -+ -+ -+} -+/******************************************************************************* -+* mvAhbToMbusWinTargetSwap - Swap AhbToMbus windows between targets -+* -+* DESCRIPTION: -+* -+* INPUT: -+* target1 - CPU Interface target 1 -+* target2 - CPU Interface target 2 -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR if targets are illigal, or if one of the targets is not -+* associated to a valid window . -+* MV_OK otherwise. -+* -+*******************************************************************************/ -+ -+ -+MV_STATUS mvAhbToMbusWinTargetSwap(MV_TARGET target1,MV_TARGET target2) -+{ -+ MV_U32 winNum1,winNum2; -+ MV_AHB_TO_MBUS_DEC_WIN winDec1,winDec2,winDecTemp; -+ AHB_TO_MBUS_REMAP_REG_OFFS remapRegs1,remapRegs2; -+ MV_U32 remapBaseLow1=0,remapBaseLow2=0; -+ MV_U32 remapBaseHigh1=0,remapBaseHigh2=0; -+ -+ -+ /* Check parameters */ -+ if (target1 >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d is Illigal\n", target1); -+ return MV_ERROR; -+ } -+ -+ if (target2 >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d is Illigal\n", target1); -+ return MV_ERROR; -+ } -+ -+ -+ /* get window associated with this target */ -+ winNum1 = mvAhbToMbusWinTargetGet(target1); -+ -+ if (winNum1 == 0xffffffff) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d has illigal win %d\n", -+ target1,winNum1); -+ return MV_ERROR; -+ -+ } -+ -+ /* get window associated with this target */ -+ winNum2 = mvAhbToMbusWinTargetGet(target2); -+ -+ if (winNum2 == 0xffffffff) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d has illigal win %d\n", -+ target2,winNum2); -+ return MV_ERROR; -+ -+ } -+ -+ /* now Get original values of both Windows */ -+ if (MV_OK != mvAhbToMbusWinGet(winNum1,&winDec1)) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetSwap: mvAhbToMbusWinGet failed win %d\n", -+ winNum1); -+ return MV_ERROR; -+ -+ } -+ if (MV_OK != mvAhbToMbusWinGet(winNum2,&winDec2)) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetSwap: mvAhbToMbusWinGet failed win %d\n", -+ winNum2); -+ return MV_ERROR; -+ -+ } -+ -+ -+ /* disable both windows */ -+ if (MV_OK != mvAhbToMbusWinEnable(winNum1,MV_FALSE)) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetSwap: failed to enable window %d\n", -+ winNum1); -+ return MV_ERROR; -+ -+ } -+ if (MV_OK != mvAhbToMbusWinEnable(winNum2,MV_FALSE)) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetSwap: failed to enable windo %d\n", -+ winNum2); -+ return MV_ERROR; -+ -+ } -+ -+ -+ /* now swap targets */ -+ -+ /* first save winDec2 values */ -+ winDecTemp.addrWin.baseHigh = winDec2.addrWin.baseHigh; -+ winDecTemp.addrWin.baseLow = winDec2.addrWin.baseLow; -+ winDecTemp.addrWin.size = winDec2.addrWin.size; -+ winDecTemp.enable = winDec2.enable; -+ winDecTemp.target = winDec2.target; -+ -+ /* winDec2 = winDec1 */ -+ winDec2.addrWin.baseHigh = winDec1.addrWin.baseHigh; -+ winDec2.addrWin.baseLow = winDec1.addrWin.baseLow; -+ winDec2.addrWin.size = winDec1.addrWin.size; -+ winDec2.enable = winDec1.enable; -+ winDec2.target = winDec1.target; -+ -+ -+ /* winDec1 = winDecTemp */ -+ winDec1.addrWin.baseHigh = winDecTemp.addrWin.baseHigh; -+ winDec1.addrWin.baseLow = winDecTemp.addrWin.baseLow; -+ winDec1.addrWin.size = winDecTemp.addrWin.size; -+ winDec1.enable = winDecTemp.enable; -+ winDec1.target = winDecTemp.target; -+ -+ -+ /* now set the new values */ -+ -+ -+ mvAhbToMbusWinSet(winNum1,&winDec1); -+ mvAhbToMbusWinSet(winNum2,&winDec2); -+ -+ -+ -+ -+ -+ /* now we will treat the remap windows if exist */ -+ -+ -+ /* now check if one or both windows has a remap window -+ as well after the swap ! */ -+ -+ /* if a window had a remap value differnt than the base value -+ before the swap , then after the swap the remap value will be -+ equal to the base value unless both windows has a remap windows*/ -+ -+ /* first get old values */ -+ if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum1,&remapRegs1)) -+ { -+ remapBaseLow1 = MV_REG_READ(remapRegs1.lowRegOffs); -+ remapBaseHigh1 = MV_REG_READ(remapRegs1.highRegOffs); -+ -+ } -+ if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2,&remapRegs2)) -+ { -+ remapBaseLow2 = MV_REG_READ(remapRegs2.lowRegOffs); -+ remapBaseHigh2 = MV_REG_READ(remapRegs2.highRegOffs); -+ -+ -+ } -+ -+ /* now do the swap */ -+ if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum1,&remapRegs1)) -+ { -+ if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2,&remapRegs2)) -+ { -+ /* Two windows has a remap !!! so swap */ -+ -+ MV_REG_WRITE(remapRegs2.highRegOffs,remapBaseHigh1); -+ MV_REG_WRITE(remapRegs2.lowRegOffs,remapBaseLow1); -+ -+ MV_REG_WRITE(remapRegs1.highRegOffs,remapBaseHigh2); -+ MV_REG_WRITE(remapRegs1.lowRegOffs,remapBaseLow2); -+ -+ -+ -+ } -+ else -+ { -+ /* remap == base */ -+ MV_REG_WRITE(remapRegs1.highRegOffs,winDec1.addrWin.baseHigh); -+ MV_REG_WRITE(remapRegs1.lowRegOffs,winDec1.addrWin.baseLow); -+ -+ } -+ -+ } -+ else if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2,&remapRegs2)) -+ { -+ /* remap == base */ -+ MV_REG_WRITE(remapRegs2.highRegOffs,winDec2.addrWin.baseHigh); -+ MV_REG_WRITE(remapRegs2.lowRegOffs,winDec2.addrWin.baseLow); -+ -+ } -+ -+ -+ -+ return MV_OK; -+ -+ -+} -+ -+ -+ -+#if defined(MV_88F1181) -+ -+/******************************************************************************* -+* mvAhbToMbusXbarCtrlSet - Set The CPU master Xbar arbitration. -+* -+* DESCRIPTION: -+* This function sets CPU Mbus Arbiter -+* -+* INPUT: -+* pPizzaArbArray - A priority Structure describing 16 "pizza slices". At -+* each clock cycle, the crossbar arbiter samples all -+* requests and gives the bus to the next agent according -+* to the "pizza". -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_ERROR if paramers to function invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvMbusArbSet(MV_MBUS_ARB_TARGET *pPizzaArbArray) -+{ -+ MV_U32 sliceNum; -+ MV_U32 xbarCtrl = 0; -+ MV_MBUS_ARB_TARGET xbarTarget; -+ -+ /* 1) Set crossbar control low register */ -+ for (sliceNum = 0; sliceNum < MRLR_SLICE_NUM; sliceNum++) -+ { -+ xbarTarget = pPizzaArbArray[sliceNum]; -+ -+ /* sliceNum parameter check */ -+ if (xbarTarget > MAX_MBUS_ARB_TARGETS) -+ { -+ mvOsPrintf("mvAhbToMbusXbarCtrlSet: ERR. Can't set Target %d\n", -+ xbarTarget); -+ return MV_ERROR; -+ } -+ xbarCtrl |= (xbarTarget << MRLR_LOW_ARB_OFFS(sliceNum)); -+ } -+ /* Write to crossbar control low register */ -+ MV_REG_WRITE(MBUS_ARBITER_LOW_REG, xbarCtrl); -+ -+ xbarCtrl = 0; -+ -+ /* 2) Set crossbar control high register */ -+ for (sliceNum = MRLR_SLICE_NUM; -+ sliceNum < MRLR_SLICE_NUM+MRHR_SLICE_NUM; -+ sliceNum++) -+ { -+ -+ xbarTarget = pPizzaArbArray[sliceNum]; -+ -+ /* sliceNum parameter check */ -+ if (xbarTarget > MAX_MBUS_ARB_TARGETS) -+ { -+ mvOsPrintf("mvAhbToMbusXbarCtrlSet: ERR. Can't set Target %d\n", -+ xbarTarget); -+ return MV_ERROR; -+ } -+ xbarCtrl |= (xbarTarget << MRHR_HIGH_ARB_OFFS(sliceNum)); -+ } -+ /* Write to crossbar control high register */ -+ MV_REG_WRITE(MBUS_ARBITER_HIGH_REG, xbarCtrl); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvMbusArbCtrlSet - Set MBus Arbiter control register -+* -+* DESCRIPTION: -+* -+* INPUT: -+* ctrl - pointer to MV_MBUS_ARB_CTRL register -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_ERROR if paramers to function invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvMbusArbCtrlSet(MV_MBUS_ARB_CTRL *ctrl) -+{ -+ -+ if (ctrl->highPrio == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(MBUS_ARBITER_CTRL_REG, MACR_ARB_ARM_TOP); -+ } -+ else -+ { -+ MV_REG_BIT_SET(MBUS_ARBITER_CTRL_REG, MACR_ARB_ARM_TOP); -+ } -+ -+ if (ctrl->fixedRoundRobin == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(MBUS_ARBITER_CTRL_REG, MACR_ARB_TARGET_FIXED); -+ } -+ else -+ { -+ MV_REG_BIT_SET(MBUS_ARBITER_CTRL_REG, MACR_ARB_TARGET_FIXED); -+ } -+ -+ if (ctrl->starvEn == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(MBUS_ARBITER_CTRL_REG, MACR_ARB_REQ_CTRL_EN); -+ } -+ else -+ { -+ MV_REG_BIT_SET(MBUS_ARBITER_CTRL_REG, MACR_ARB_REQ_CTRL_EN); -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvMbusArbCtrlGet - Get MBus Arbiter control register -+* -+* DESCRIPTION: -+* -+* INPUT: -+* ctrl - pointer to MV_MBUS_ARB_CTRL register -+* -+* OUTPUT: -+* ctrl - pointer to MV_MBUS_ARB_CTRL register -+* -+* RETURN: -+* MV_ERROR if paramers to function invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvMbusArbCtrlGet(MV_MBUS_ARB_CTRL *ctrl) -+{ -+ -+ MV_U32 ctrlReg = MV_REG_READ(MBUS_ARBITER_CTRL_REG); -+ -+ if (ctrlReg & MACR_ARB_ARM_TOP) -+ { -+ ctrl->highPrio = MV_TRUE; -+ } -+ else -+ { -+ ctrl->highPrio = MV_FALSE; -+ } -+ -+ if (ctrlReg & MACR_ARB_TARGET_FIXED) -+ { -+ ctrl->fixedRoundRobin = MV_TRUE; -+ } -+ else -+ { -+ ctrl->fixedRoundRobin = MV_FALSE; -+ } -+ -+ if (ctrlReg & MACR_ARB_REQ_CTRL_EN) -+ { -+ ctrl->starvEn = MV_TRUE; -+ } -+ else -+ { -+ ctrl->starvEn = MV_FALSE; -+ } -+ -+ -+ return MV_OK; -+} -+ -+#endif /* #if defined(MV_88F1181) */ -+ -+ -+ -+/******************************************************************************* -+* ahbToMbusRemapRegOffsGet - Get CPU address remap register offsets -+* -+* DESCRIPTION: -+* CPU to PCI address remap registers offsets are inconsecutive. -+* This function returns PCI address remap registers offsets. -+* -+* INPUT: -+* winNum - Address decode window number. See MV_U32 enumerator. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR if winNum is not a PCI one. -+* -+*******************************************************************************/ -+static MV_STATUS ahbToMbusRemapRegOffsGet(MV_U32 winNum, -+ AHB_TO_MBUS_REMAP_REG_OFFS *pRemapRegs) -+{ -+ switch (winNum) -+ { -+ case 0: -+ case 1: -+ pRemapRegs->lowRegOffs = AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum); -+ pRemapRegs->highRegOffs = AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum); -+ break; -+ case 2: -+ case 3: -+ if((mvCtrlModelGet() == MV_5281_DEV_ID) || -+ (mvCtrlModelGet() == MV_1281_DEV_ID) || -+ (mvCtrlModelGet() == MV_6183_DEV_ID) || -+ (mvCtrlModelGet() == MV_6183L_DEV_ID)) -+ { -+ pRemapRegs->lowRegOffs = AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum); -+ pRemapRegs->highRegOffs = AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum); -+ break; -+ } -+ else -+ { -+ pRemapRegs->lowRegOffs = 0; -+ pRemapRegs->highRegOffs = 0; -+ -+ DB(mvOsPrintf("ahbToMbusRemapRegOffsGet: ERR. Invalid winNum %d\n", -+ winNum)); -+ return MV_NO_SUCH; -+ } -+ default: -+ { -+ pRemapRegs->lowRegOffs = 0; -+ pRemapRegs->highRegOffs = 0; -+ -+ DB(mvOsPrintf("ahbToMbusRemapRegOffsGet: ERR. Invalid winNum %d\n", -+ winNum)); -+ return MV_NO_SUCH; -+ } -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvAhbToMbusAddDecShow - Print the AHB to MBus bridge address decode map. -+* -+* DESCRIPTION: -+* This function print the CPU address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvAhbToMbusAddDecShow(MV_VOID) -+{ -+ MV_AHB_TO_MBUS_DEC_WIN win; -+ MV_U32 winNum; -+ mvOsOutput( "\n" ); -+ mvOsOutput( "AHB To MBUS Bridge:\n" ); -+ mvOsOutput( "-------------------\n" ); -+ -+ for( winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS; winNum++ ) -+ { -+ memset( &win, 0, sizeof(MV_AHB_TO_MBUS_DEC_WIN) ); -+ -+ mvOsOutput( "win%d - ", winNum ); -+ -+ if( mvAhbToMbusWinGet( winNum, &win ) == MV_OK ) -+ { -+ if( win.enable ) -+ { -+ mvOsOutput( "%s base %08x, ", -+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); -+ mvOsOutput( "...." ); -+ mvSizePrint( win.addrWin.size ); -+ -+ mvOsOutput( "\n" ); -+ -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ } -+ } -+ -+} -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h 2010-11-09 20:28:07.872495394 +0100 -@@ -0,0 +1,130 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvAhbToMbush -+#define __INCmvAhbToMbush -+ -+/* includes */ -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/sys/mvAhbToMbusRegs.h" -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+ -+/* defines */ -+ -+#if defined(MV_88F1181) -+/* This enumerator defines the Marvell controller possible MBUS arbiter */ -+/* target ports. It is used to define crossbar priority scheame (pizza) */ -+typedef enum _mvMBusArbTargetId -+{ -+ DRAM_MBUS_ARB_TARGET = 0, /* Port 0 -> DRAM interface */ -+ TWSI_MBUS_ARB_TARGET = 1, /* Port 1 -> TWSI */ -+ ARM_MBUS_ARB_TARGET = 2, /* Port 2 -> ARM */ -+ PEX1_MBUS_ARB_TARGET = 3, /* Port 3 -> PCI Express 1 */ -+ PEX0_MBUS_ARB_TARGET = 4, /* Port 4 -> PCI Express0 */ -+ MAX_MBUS_ARB_TARGETS -+}MV_MBUS_ARB_TARGET; -+ -+typedef struct _mvMBusArbCtrl -+{ -+ MV_BOOL starvEn; -+ MV_BOOL highPrio; -+ MV_BOOL fixedRoundRobin; -+ -+}MV_MBUS_ARB_CTRL; -+ -+#endif /* #if defined(MV_88F1181) */ -+ -+typedef struct _mvAhbtoMbusDecWin -+{ -+ MV_TARGET target; -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+}MV_AHB_TO_MBUS_DEC_WIN; -+ -+/* mvAhbToMbus.h API list */ -+ -+MV_STATUS mvAhbToMbusInit(MV_VOID); -+MV_STATUS mvAhbToMbusWinSet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin); -+MV_STATUS mvAhbToMbusWinGet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin); -+MV_STATUS mvAhbToMbusWinEnable(MV_U32 winNum,MV_BOOL enable); -+MV_U32 mvAhbToMbusWinRemap(MV_U32 winNum, MV_ADDR_WIN *pAddrDecWin); -+MV_U32 mvAhbToMbusWinTargetGet(MV_TARGET target); -+MV_U32 mvAhbToMbusWinAvailGet(MV_VOID); -+MV_STATUS mvAhbToMbusWinTargetSwap(MV_TARGET target1,MV_TARGET target2); -+ -+#if defined(MV_88F1181) -+ -+MV_STATUS mvMbusArbSet(MV_MBUS_ARB_TARGET *pPizzaArbArray); -+MV_STATUS mvMbusArbCtrlSet(MV_MBUS_ARB_CTRL *ctrl); -+MV_STATUS mvMbusArbCtrlGet(MV_MBUS_ARB_CTRL *ctrl); -+ -+#endif /* #if defined(MV_88F1181) */ -+ -+ -+MV_VOID mvAhbToMbusAddDecShow(MV_VOID); -+ -+ -+#endif /* __INCmvAhbToMbush */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h 2010-11-09 20:28:07.902495495 +0100 -@@ -0,0 +1,143 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvAhbToMbusRegsh -+#define __INCmvAhbToMbusRegsh -+ -+/******************************/ -+/* ARM Address Map Registers */ -+/******************************/ -+ -+#define MAX_AHB_TO_MBUS_WINS 9 -+#define MV_AHB_TO_MBUS_INTREG_WIN 8 -+ -+ -+#define AHB_TO_MBUS_WIN_CTRL_REG(winNum) (0x20000 + (winNum)*0x10) -+#define AHB_TO_MBUS_WIN_BASE_REG(winNum) (0x20004 + (winNum)*0x10) -+#define AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum) (0x20008 + (winNum)*0x10) -+#define AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum) (0x2000C + (winNum)*0x10) -+#define AHB_TO_MBUS_WIN_INTEREG_REG 0x20080 -+ -+/* Window Control Register */ -+/* AHB_TO_MBUS_WIN_CTRL_REG (ATMWCR)*/ -+#define ATMWCR_WIN_ENABLE BIT0 /* Window Enable */ -+ -+#define ATMWCR_WIN_TARGET_OFFS 4 /* The target interface associated -+ with this window*/ -+#define ATMWCR_WIN_TARGET_MASK (0xf << ATMWCR_WIN_TARGET_OFFS) -+ -+#define ATMWCR_WIN_ATTR_OFFS 8 /* The target interface attributes -+ Associated with this window */ -+#define ATMWCR_WIN_ATTR_MASK (0xff << ATMWCR_WIN_ATTR_OFFS) -+ -+ -+/* -+Used with the Base register to set the address window size and location -+Must be programed from LSB to MSB as sequence of 1’s followed -+by sequence of 0’s. The number of 1’s specifies the size of the window -+in 64 KB granularity (e.g. a value of 0x00FF specifies 256 = 16 MB). -+ -+NOTE: A value of 0x0 specifies 64KB size. -+*/ -+#define ATMWCR_WIN_SIZE_OFFS 16 /* Window Size */ -+#define ATMWCR_WIN_SIZE_MASK (0xffff << ATMWCR_WIN_SIZE_OFFS) -+#define ATMWCR_WIN_SIZE_ALIGNMENT 0x10000 -+ -+/* Window Base Register */ -+/* AHB_TO_MBUS_WIN_BASE_REG (ATMWBR) */ -+ -+/* -+Used with the size field to set the address window size and location. -+Corresponds to transaction address[31:16] -+*/ -+#define ATMWBR_BASE_OFFS 16 /* Base Address */ -+#define ATMWBR_BASE_MASK (0xffff << ATMWBR_BASE_OFFS) -+#define ATMWBR_BASE_ALIGNMENT 0x10000 -+ -+/* Window Remap Low Register */ -+/* AHB_TO_MBUS_WIN_REMAP_LOW_REG (ATMWRLR) */ -+ -+/* -+Used with the size field to specifies address bits[31:0] to be driven to -+the target interface.: -+target_addr[31:16] = (addr[31:16] & size[15:0]) | (remap[31:16] & ~size[15:0]) -+*/ -+#define ATMWRLR_REMAP_LOW_OFFS 16 /* Remap Address */ -+#define ATMWRLR_REMAP_LOW_MASK (0xffff << ATMWRLR_REMAP_LOW_OFFS) -+#define ATMWRLR_REMAP_LOW_ALIGNMENT 0x10000 -+ -+/* Window Remap High Register */ -+/* AHB_TO_MBUS_WIN_REMAP_HIGH_REG (ATMWRHR) */ -+ -+/* -+Specifies address bits[63:32] to be driven to the target interface. -+target_addr[63:32] = (RemapHigh[31:0] -+*/ -+#define ATMWRHR_REMAP_HIGH_OFFS 0 /* Remap Address */ -+#define ATMWRHR_REMAP_HIGH_MASK (0xffffffff << ATMWRHR_REMAP_HIGH_OFFS) -+ -+ -+#endif /* __INCmvAhbToMbusRegsh */ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c 2010-11-09 20:28:07.942495425 +0100 -@@ -0,0 +1,1036 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+/* includes */ -+#include "ctrlEnv/sys/mvCpuIf.h" -+#include "ctrlEnv/sys/mvAhbToMbusRegs.h" -+#include "cpu/mvCpu.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "mvSysHwConfig.h" -+#include "mvSysDram.h" -+ -+/*#define MV_DEBUG*/ -+/* defines */ -+ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+/* locals */ -+/* static functions */ -+static MV_BOOL cpuTargetWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin); -+ -+MV_TARGET * sampleAtResetTargetArray; -+MV_TARGET sampleAtResetTargetArrayP[] = BOOT_TARGETS_NAME_ARRAY; -+MV_TARGET sampleAtResetTargetArray6180P[] = BOOT_TARGETS_NAME_ARRAY_6180; -+/******************************************************************************* -+* mvCpuIfInit - Initialize Controller CPU interface -+* -+* DESCRIPTION: -+* This function initialize Controller CPU interface: -+* 1. Set CPU interface configuration registers. -+* 2. Set CPU master Pizza arbiter control according to static -+* configuration described in configuration file. -+* 3. Opens CPU address decode windows. DRAM windows are assumed to be -+* already set (auto detection). -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvCpuIfInit(MV_CPU_DEC_WIN *cpuAddrWinMap) -+{ -+ MV_U32 regVal; -+ MV_TARGET target; -+ MV_ADDR_WIN addrWin; -+ -+ if (cpuAddrWinMap == NULL) -+ { -+ DB(mvOsPrintf("mvCpuIfInit:ERR. cpuAddrWinMap == NULL\n")); -+ return MV_ERROR; -+ } -+ -+ /*Initialize the boot target array according to device type*/ -+ if(mvCtrlModelGet() == MV_6180_DEV_ID) -+ sampleAtResetTargetArray = sampleAtResetTargetArray6180P; -+ else -+ sampleAtResetTargetArray = sampleAtResetTargetArrayP; -+ -+ /* Set ARM Configuration register */ -+ regVal = MV_REG_READ(CPU_CONFIG_REG); -+ regVal &= ~CPU_CONFIG_DEFAULT_MASK; -+ regVal |= CPU_CONFIG_DEFAULT; -+ MV_REG_WRITE(CPU_CONFIG_REG,regVal); -+ -+ /* First disable all CPU target windows */ -+ for (target = 0; cpuAddrWinMap[target].enable != TBL_TERM; target++) -+ { -+ if ((MV_TARGET_IS_DRAM(target))||(target == INTER_REGS)) -+ { -+ continue; -+ } -+ -+#if defined(MV_MEM_OVER_PCI_WA) || defined(MV_UART_OVER_PCI_WA) -+ /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ -+ if (MV_TARGET_IS_PCI(target)) -+ { -+ continue; -+ } -+#endif -+ -+#if defined(MV_MEM_OVER_PEX_WA) || defined(MV_UART_OVER_PEX_WA) -+ /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ -+ if (MV_TARGET_IS_PEX(target)) -+ { -+ continue; -+ } -+#endif -+#if defined(MV_RUN_FROM_FLASH) -+ /* Don't disable the boot device. */ -+ if (target == DEV_BOOCS) -+ { -+ continue; -+ } -+#endif /* MV_RUN_FROM_FLASH */ -+ mvCpuIfTargetWinEnable(MV_CHANGE_BOOT_CS(target),MV_FALSE); -+ } -+ -+#if defined(MV_RUN_FROM_FLASH) -+ /* Resize the bootcs windows before other windows, because this */ -+ /* window is enabled and will cause an overlap if not resized. */ -+ target = DEV_BOOCS; -+ -+ if (MV_OK != mvCpuIfTargetWinSet(target, &cpuAddrWinMap[target])) -+ { -+ DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinSet fail\n")); -+ return MV_ERROR; -+ } -+ -+ addrWin.baseLow = cpuAddrWinMap[target].addrWin.baseLow; -+ addrWin.baseHigh = cpuAddrWinMap[target].addrWin.baseHigh; -+ if (0xffffffff == mvAhbToMbusWinRemap(cpuAddrWinMap[target].winNum ,&addrWin)) -+ { -+ DB(mvOsPrintf("mvCpuIfInit:WARN. mvAhbToMbusWinRemap can't remap winNum=%d\n", -+ cpuAddrWinMap[target].winNum)); -+ } -+ -+#endif /* MV_RUN_FROM_FLASH */ -+ -+ /* Go through all targets in user table until table terminator */ -+ for (target = 0; cpuAddrWinMap[target].enable != TBL_TERM; target++) -+ { -+ -+#if defined(MV_RUN_FROM_FLASH) -+ if (target == DEV_BOOCS) -+ { -+ continue; -+ } -+#endif /* MV_RUN_FROM_FLASH */ -+ -+ /* if DRAM auto sizing is used do not initialized DRAM target windows, */ -+ /* assuming this already has been done earlier. */ -+#ifdef MV_DRAM_AUTO_SIZE -+ if (MV_TARGET_IS_DRAM(target)) -+ { -+ continue; -+ } -+#endif -+ -+#if defined(MV_MEM_OVER_PCI_WA) || defined(MV_UART_OVER_PCI_WA) -+ /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ -+ if (MV_TARGET_IS_PCI(target)) -+ { -+ continue; -+ } -+#endif -+ -+#if defined(MV_MEM_OVER_PEX_WA) || defined(MV_UART_OVER_PEX_WA) -+ /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ -+ if (MV_TARGET_IS_PEX(target)) -+ { -+ continue; -+ } -+#endif -+ /* If the target attribute is the same as the boot device attribute */ -+ /* then it's stays disable */ -+ if (MV_TARGET_IS_AS_BOOT(target)) -+ { -+ continue; -+ } -+ -+ if((0 == cpuAddrWinMap[target].addrWin.size) || -+ (DIS == cpuAddrWinMap[target].enable)) -+ -+ { -+ if (MV_OK != mvCpuIfTargetWinEnable(target, MV_FALSE)) -+ { -+ DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinEnable fail\n")); -+ return MV_ERROR; -+ } -+ -+ } -+ else -+ { -+ if (MV_OK != mvCpuIfTargetWinSet(target, &cpuAddrWinMap[target])) -+ { -+ DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinSet fail\n")); -+ return MV_ERROR; -+ } -+ -+ addrWin.baseLow = cpuAddrWinMap[target].addrWin.baseLow; -+ addrWin.baseHigh = cpuAddrWinMap[target].addrWin.baseHigh; -+ if (0xffffffff == mvAhbToMbusWinRemap(cpuAddrWinMap[target].winNum ,&addrWin)) -+ { -+ DB(mvOsPrintf("mvCpuIfInit:WARN. mvAhbToMbusWinRemap can't remap winNum=%d\n", -+ cpuAddrWinMap[target].winNum)); -+ } -+ -+ -+ } -+ } -+ -+ return MV_OK; -+ -+ -+} -+ -+ -+/******************************************************************************* -+* mvCpuIfTargetWinSet - Set CPU-to-peripheral target address window -+* -+* DESCRIPTION: -+* This function sets a peripheral target (e.g. SDRAM bank0, PCI0_MEM0) -+* address window, also known as address decode window. -+* A new address decode window is set for specified target address window. -+* If address decode window parameter structure enables the window, -+* the routine will also enable the target window, allowing CPU to access -+* the target window. -+* -+* INPUT: -+* target - Peripheral target enumerator. -+* pAddrDecWin - CPU target window data structure. -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_OK if CPU target window was set correctly, MV_ERROR in case of -+* address window overlapps with other active CPU target window or -+* trying to assign 36bit base address while CPU does not support that. -+* The function returns MV_NOT_SUPPORTED, if the target is unsupported. -+* -+*******************************************************************************/ -+MV_STATUS mvCpuIfTargetWinSet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin) -+{ -+ MV_AHB_TO_MBUS_DEC_WIN decWin; -+ MV_U32 existingWinNum; -+ MV_DRAM_DEC_WIN addrDecWin; -+ -+ target = MV_CHANGE_BOOT_CS(target); -+ -+ /* Check parameters */ -+ if (target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvCpuIfTargetWinSet: target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ /* 2) Check if the requested window overlaps with current windows */ -+ if (MV_TRUE == cpuTargetWinOverlap(target, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("mvCpuIfTargetWinSet: ERR. Target %d overlap\n", target); -+ return MV_BAD_PARAM; -+ } -+ -+ if (MV_TARGET_IS_DRAM(target)) -+ { -+ /* copy relevant data to MV_DRAM_DEC_WIN structure */ -+ addrDecWin.addrWin.baseHigh = pAddrDecWin->addrWin.baseHigh; -+ addrDecWin.addrWin.baseLow = pAddrDecWin->addrWin.baseLow; -+ addrDecWin.addrWin.size = pAddrDecWin->addrWin.size; -+ addrDecWin.enable = pAddrDecWin->enable; -+ -+ -+ if (mvDramIfWinSet(target,&addrDecWin) != MV_OK); -+ { -+ mvOsPrintf("mvCpuIfTargetWinSet: mvDramIfWinSet Failed\n"); -+ return MV_ERROR; -+ } -+ -+ } -+ else -+ { -+ /* copy relevant data to MV_AHB_TO_MBUS_DEC_WIN structure */ -+ decWin.addrWin.baseLow = pAddrDecWin->addrWin.baseLow; -+ decWin.addrWin.baseHigh = pAddrDecWin->addrWin.baseHigh; -+ decWin.addrWin.size = pAddrDecWin->addrWin.size; -+ decWin.enable = pAddrDecWin->enable; -+ decWin.target = target; -+ -+ existingWinNum = mvAhbToMbusWinTargetGet(target); -+ -+ /* check if there is already another Window configured -+ for this target */ -+ if ((existingWinNum < MAX_AHB_TO_MBUS_WINS )&& -+ (existingWinNum != pAddrDecWin->winNum)) -+ { -+ /* if we want to enable the new winow number -+ passed by the user , then the old one should -+ be disabled */ -+ if (MV_TRUE == pAddrDecWin->enable) -+ { -+ /* be sure it is disabled */ -+ mvAhbToMbusWinEnable(existingWinNum , MV_FALSE); -+ } -+ } -+ -+ if (mvAhbToMbusWinSet(pAddrDecWin->winNum,&decWin) != MV_OK) -+ { -+ mvOsPrintf("mvCpuIfTargetWinSet: mvAhbToMbusWinSet Failed\n"); -+ return MV_ERROR; -+ } -+ -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCpuIfTargetWinGet - Get CPU-to-peripheral target address window -+* -+* DESCRIPTION: -+* Get the CPU peripheral target address window. -+* -+* INPUT: -+* target - Peripheral target enumerator -+* -+* OUTPUT: -+* pAddrDecWin - CPU target window information data structure. -+* -+* RETURN: -+* MV_OK if target exist, MV_ERROR otherwise. -+* -+*******************************************************************************/ -+MV_STATUS mvCpuIfTargetWinGet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin) -+{ -+ -+ MV_U32 winNum=0xffffffff; -+ MV_AHB_TO_MBUS_DEC_WIN decWin; -+ MV_DRAM_DEC_WIN addrDecWin; -+ -+ target = MV_CHANGE_BOOT_CS(target); -+ -+ /* Check parameters */ -+ if (target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvCpuIfTargetWinGet: target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ if (MV_TARGET_IS_DRAM(target)) -+ { -+ if (mvDramIfWinGet(target,&addrDecWin) != MV_OK) -+ { -+ mvOsPrintf("mvCpuIfTargetWinGet: Failed to get window target %d\n", -+ target); -+ return MV_ERROR; -+ } -+ -+ /* copy relevant data to MV_CPU_DEC_WIN structure */ -+ pAddrDecWin->addrWin.baseLow = addrDecWin.addrWin.baseLow; -+ pAddrDecWin->addrWin.baseHigh = addrDecWin.addrWin.baseHigh; -+ pAddrDecWin->addrWin.size = addrDecWin.addrWin.size; -+ pAddrDecWin->enable = addrDecWin.enable; -+ pAddrDecWin->winNum = 0xffffffff; -+ -+ } -+ else -+ { -+ /* get the Window number associated with this target */ -+ -+ winNum = mvAhbToMbusWinTargetGet(target); -+ if (winNum >= MAX_AHB_TO_MBUS_WINS) -+ { -+ return MV_NO_SUCH; -+ -+ } -+ -+ if (mvAhbToMbusWinGet(winNum , &decWin) != MV_OK) -+ { -+ mvOsPrintf("%s: mvAhbToMbusWinGet Failed at winNum = %d\n", -+ __FUNCTION__, winNum); -+ return MV_ERROR; -+ -+ } -+ -+ /* copy relevant data to MV_CPU_DEC_WIN structure */ -+ pAddrDecWin->addrWin.baseLow = decWin.addrWin.baseLow; -+ pAddrDecWin->addrWin.baseHigh = decWin.addrWin.baseHigh; -+ pAddrDecWin->addrWin.size = decWin.addrWin.size; -+ pAddrDecWin->enable = decWin.enable; -+ pAddrDecWin->winNum = winNum; -+ -+ } -+ -+ -+ -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvCpuIfTargetWinEnable - Enable/disable a CPU address decode window -+* -+* DESCRIPTION: -+* This function enable/disable a CPU address decode window. -+* if parameter 'enable' == MV_TRUE the routine will enable the -+* window, thus enabling CPU accesses (before enabling the window it is -+* tested for overlapping). Otherwise, the window will be disabled. -+* -+* INPUT: -+* target - Peripheral target enumerator. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_ERROR if protection window number was wrong, or the window -+* overlapps other target window. -+* -+*******************************************************************************/ -+MV_STATUS mvCpuIfTargetWinEnable(MV_TARGET target,MV_BOOL enable) -+{ -+ MV_U32 winNum, temp; -+ MV_CPU_DEC_WIN addrDecWin; -+ -+ target = MV_CHANGE_BOOT_CS(target); -+ -+ /* Check parameters */ -+ if (target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvCpuIfTargetWinEnable: target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ /* get the window and check if it exist */ -+ temp = mvCpuIfTargetWinGet(target, &addrDecWin); -+ if (MV_NO_SUCH == temp) -+ { -+ return (enable? MV_ERROR: MV_OK); -+ } -+ else if( MV_OK != temp) -+ { -+ mvOsPrintf("%s: ERR. Getting target %d failed.\n",__FUNCTION__, target); -+ return MV_ERROR; -+ } -+ -+ -+ /* check overlap */ -+ -+ if (MV_TRUE == enable) -+ { -+ if (MV_TRUE == cpuTargetWinOverlap(target, &addrDecWin.addrWin)) -+ { -+ DB(mvOsPrintf("%s: ERR. Target %d overlap\n",__FUNCTION__, target)); -+ return MV_ERROR; -+ } -+ -+ } -+ -+ -+ if (MV_TARGET_IS_DRAM(target)) -+ { -+ if (mvDramIfWinEnable(target , enable) != MV_OK) -+ { -+ mvOsPrintf("mvCpuIfTargetWinGet: mvDramIfWinEnable Failed at \n"); -+ return MV_ERROR; -+ -+ } -+ -+ } -+ else -+ { -+ /* get the Window number associated with this target */ -+ -+ winNum = mvAhbToMbusWinTargetGet(target); -+ -+ if (winNum >= MAX_AHB_TO_MBUS_WINS) -+ { -+ return (enable? MV_ERROR: MV_OK); -+ } -+ -+ if (mvAhbToMbusWinEnable(winNum , enable) != MV_OK) -+ { -+ mvOsPrintf("mvCpuIfTargetWinGet: Failed to enable window = %d\n", -+ winNum); -+ return MV_ERROR; -+ -+ } -+ -+ } -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvCpuIfTargetWinSizeGet - Get CPU target address window size -+* -+* DESCRIPTION: -+* Get the size of CPU-to-peripheral target window. -+* -+* INPUT: -+* target - Peripheral target enumerator -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit size. Function also returns '0' if window is closed. -+* Function returns 0xFFFFFFFF in case of an error. -+* -+*******************************************************************************/ -+MV_U32 mvCpuIfTargetWinSizeGet(MV_TARGET target) -+{ -+ MV_CPU_DEC_WIN addrDecWin; -+ -+ target = MV_CHANGE_BOOT_CS(target); -+ -+ /* Check parameters */ -+ if (target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvCpuIfTargetWinSizeGet: target %d is Illigal\n", target); -+ return 0; -+ } -+ -+ /* Get the winNum window */ -+ if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) -+ { -+ mvOsPrintf("mvCpuIfTargetWinSizeGet:ERR. Getting target %d failed.\n", -+ target); -+ return 0; -+ } -+ -+ /* Check if window is enabled */ -+ if (addrDecWin.enable == MV_TRUE) -+ { -+ return (addrDecWin.addrWin.size); -+ } -+ else -+ { -+ return 0; /* Window disabled. return 0 */ -+ } -+} -+ -+/******************************************************************************* -+* mvCpuIfTargetWinBaseLowGet - Get CPU target address window base low -+* -+* DESCRIPTION: -+* CPU-to-peripheral target address window base is constructed of -+* two parts: Low and high. -+* This function gets the CPU peripheral target low base address. -+* -+* INPUT: -+* target - Peripheral target enumerator -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit low base address. -+* -+*******************************************************************************/ -+MV_U32 mvCpuIfTargetWinBaseLowGet(MV_TARGET target) -+{ -+ MV_CPU_DEC_WIN addrDecWin; -+ -+ target = MV_CHANGE_BOOT_CS(target); -+ -+ /* Check parameters */ -+ if (target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvCpuIfTargetWinBaseLowGet: target %d is Illigal\n", target); -+ return 0xffffffff; -+ } -+ -+ /* Get the target window */ -+ if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) -+ { -+ mvOsPrintf("mvCpuIfTargetWinBaseLowGet:ERR. Getting target %d failed.\n", -+ target); -+ return 0xffffffff; -+ } -+ -+ if (MV_FALSE == addrDecWin.enable) -+ { -+ return 0xffffffff; -+ } -+ return (addrDecWin.addrWin.baseLow); -+} -+ -+/******************************************************************************* -+* mvCpuIfTargetWinBaseHighGet - Get CPU target address window base high -+* -+* DESCRIPTION: -+* CPU-to-peripheral target address window base is constructed of -+* two parts: Low and high. -+* This function gets the CPU peripheral target high base address. -+* -+* INPUT: -+* target - Peripheral target enumerator -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit high base address. -+* -+*******************************************************************************/ -+MV_U32 mvCpuIfTargetWinBaseHighGet(MV_TARGET target) -+{ -+ MV_CPU_DEC_WIN addrDecWin; -+ -+ target = MV_CHANGE_BOOT_CS(target); -+ -+ /* Check parameters */ -+ if (target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvCpuIfTargetWinBaseLowGet: target %d is Illigal\n", target); -+ return 0xffffffff; -+ } -+ -+ /* Get the target window */ -+ if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) -+ { -+ mvOsPrintf("mvCpuIfTargetWinBaseHighGet:ERR. Getting target %d failed.\n", -+ target); -+ return 0xffffffff; -+ } -+ -+ if (MV_FALSE == addrDecWin.enable) -+ { -+ return 0; -+ } -+ -+ return (addrDecWin.addrWin.baseHigh); -+} -+ -+#if defined(MV_INCLUDE_PEX) -+/******************************************************************************* -+* mvCpuIfPexRemap - Set CPU remap register for address windows. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* pexTarget - Peripheral target enumerator. Must be a PEX target. -+* pAddrDecWin - CPU target window information data structure. -+* Note that caller has to fill in the base field only. The -+* size field is ignored. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR if target is not a PEX one, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_U32 mvCpuIfPexRemap(MV_TARGET pexTarget, MV_ADDR_WIN *pAddrDecWin) -+{ -+ MV_U32 winNum; -+ -+ /* Check parameters */ -+ -+ if (mvCtrlPexMaxIfGet() > 1) -+ { -+ if ((!MV_TARGET_IS_PEX1(pexTarget))&&(!MV_TARGET_IS_PEX0(pexTarget))) -+ { -+ mvOsPrintf("mvCpuIfPexRemap: target %d is Illigal\n",pexTarget); -+ return 0xffffffff; -+ } -+ -+ } -+ else -+ { -+ if (!MV_TARGET_IS_PEX0(pexTarget)) -+ { -+ mvOsPrintf("mvCpuIfPexRemap: target %d is Illigal\n",pexTarget); -+ return 0xffffffff; -+ } -+ -+ } -+ -+ /* get the Window number associated with this target */ -+ winNum = mvAhbToMbusWinTargetGet(pexTarget); -+ -+ if (winNum >= MAX_AHB_TO_MBUS_WINS) -+ { -+ mvOsPrintf("mvCpuIfPexRemap: mvAhbToMbusWinTargetGet Failed\n"); -+ return 0xffffffff; -+ -+ } -+ -+ return mvAhbToMbusWinRemap(winNum , pAddrDecWin); -+} -+ -+#endif -+ -+#if defined(MV_INCLUDE_PCI) -+/******************************************************************************* -+* mvCpuIfPciRemap - Set CPU remap register for address windows. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* pciTarget - Peripheral target enumerator. Must be a PCI target. -+* pAddrDecWin - CPU target window information data structure. -+* Note that caller has to fill in the base field only. The -+* size field is ignored. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR if target is not a PCI one, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_U32 mvCpuIfPciRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin) -+{ -+ MV_U32 winNum; -+ -+ /* Check parameters */ -+ if (!MV_TARGET_IS_PCI(pciTarget)) -+ { -+ mvOsPrintf("mvCpuIfPciRemap: target %d is Illigal\n",pciTarget); -+ return 0xffffffff; -+ } -+ -+ /* get the Window number associated with this target */ -+ winNum = mvAhbToMbusWinTargetGet(pciTarget); -+ -+ if (winNum >= MAX_AHB_TO_MBUS_WINS) -+ { -+ mvOsPrintf("mvCpuIfPciRemap: mvAhbToMbusWinTargetGet Failed\n"); -+ return 0xffffffff; -+ -+ } -+ -+ return mvAhbToMbusWinRemap(winNum , pAddrDecWin); -+} -+#endif /* MV_INCLUDE_PCI */ -+ -+ -+/******************************************************************************* -+* mvCpuIfPciIfRemap - Set CPU remap register for address windows. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* pciTarget - Peripheral target enumerator. Must be a PCI target. -+* pAddrDecWin - CPU target window information data structure. -+* Note that caller has to fill in the base field only. The -+* size field is ignored. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR if target is not a PCI one, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_U32 mvCpuIfPciIfRemap(MV_TARGET pciIfTarget, MV_ADDR_WIN *pAddrDecWin) -+{ -+#if defined(MV_INCLUDE_PEX) -+ if (MV_TARGET_IS_PEX(pciIfTarget)) -+ { -+ return mvCpuIfPexRemap(pciIfTarget,pAddrDecWin); -+ } -+#endif -+#if defined(MV_INCLUDE_PCI) -+ -+ if (MV_TARGET_IS_PCI(pciIfTarget)) -+ { -+ return mvCpuIfPciRemap(pciIfTarget,pAddrDecWin); -+ } -+#endif -+ return 0; -+} -+ -+ -+ -+/******************************************************************************* -+* mvCpuIfTargetOfBaseAddressGet - Get the target according to base address -+* -+* DESCRIPTION: -+* -+* INPUT: -+* baseAddress - base address to be checked -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* the target number that baseAddress belongs to or MAX_TARGETS is not -+* found -+* -+*******************************************************************************/ -+ -+MV_TARGET mvCpuIfTargetOfBaseAddressGet(MV_U32 baseAddress) -+{ -+ MV_CPU_DEC_WIN win; -+ MV_U32 target; -+ -+ for( target = 0; target < MAX_TARGETS; target++ ) -+ { -+ if( mvCpuIfTargetWinGet( target, &win ) == MV_OK ) -+ { -+ if( win.enable ) -+ { -+ if ((baseAddress >= win.addrWin.baseLow) && -+ (baseAddress < win.addrWin.baseLow + win.addrWin.size)) break; -+ } -+ } -+ else return MAX_TARGETS; -+ -+ } -+ -+ return target; -+} -+/******************************************************************************* -+* cpuTargetWinOverlap - Detect CPU address decode windows overlapping -+* -+* DESCRIPTION: -+* An unpredicted behaviur is expected in case CPU address decode -+* windows overlapps. -+* This function detects CPU address decode windows overlapping of a -+* specified target. The function does not check the target itself for -+* overlapping. The function also skipps disabled address decode windows. -+* -+* INPUT: -+* target - Peripheral target enumerator. -+* pAddrDecWin - An address decode window struct. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlaps current address -+* decode map, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+static MV_BOOL cpuTargetWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 targetNum; -+ MV_CPU_DEC_WIN addrDecWin; -+ MV_STATUS status; -+ -+ -+ for(targetNum = 0; targetNum < MAX_TARGETS; targetNum++) -+ { -+#if defined(MV_RUN_FROM_FLASH) -+ if(MV_TARGET_IS_AS_BOOT(target)) -+ { -+ if (MV_CHANGE_BOOT_CS(targetNum) == target) -+ continue; -+ } -+#endif /* MV_RUN_FROM_FLASH */ -+ -+ /* don't check our target or illegal targets */ -+ if (targetNum == target) -+ { -+ continue; -+ } -+ -+ /* Get window parameters */ -+ status = mvCpuIfTargetWinGet(targetNum, &addrDecWin); -+ if(MV_NO_SUCH == status) -+ { -+ continue; -+ } -+ if(MV_OK != status) -+ { -+ DB(mvOsPrintf("cpuTargetWinOverlap: ERR. TargetWinGet failed\n")); -+ return MV_TRUE; -+ } -+ -+ /* Do not check disabled windows */ -+ if (MV_FALSE == addrDecWin.enable) -+ { -+ continue; -+ } -+ -+ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) -+ { -+ DB(mvOsPrintf( -+ "cpuTargetWinOverlap: Required target %d overlap current %d\n", -+ target, targetNum)); -+ return MV_TRUE; -+ } -+ } -+ -+ return MV_FALSE; -+ -+} -+ -+/******************************************************************************* -+* mvCpuIfAddDecShow - Print the CPU address decode map. -+* -+* DESCRIPTION: -+* This function print the CPU address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvCpuIfAddDecShow(MV_VOID) -+{ -+ MV_CPU_DEC_WIN win; -+ MV_U32 target; -+ mvOsOutput( "\n" ); -+ mvOsOutput( "CPU Interface\n" ); -+ mvOsOutput( "-------------\n" ); -+ -+ for( target = 0; target < MAX_TARGETS; target++ ) -+ { -+ -+ memset( &win, 0, sizeof(MV_CPU_DEC_WIN) ); -+ -+ mvOsOutput( "%s ",mvCtrlTargetNameGet(target)); -+ mvOsOutput( "...." ); -+ -+ if( mvCpuIfTargetWinGet( target, &win ) == MV_OK ) -+ { -+ if( win.enable ) -+ { -+ mvOsOutput( "base %08x, ", win.addrWin.baseLow ); -+ mvSizePrint( win.addrWin.size ); -+ mvOsOutput( "\n" ); -+ -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ } -+ else if( mvCpuIfTargetWinGet( target, &win ) == MV_NO_SUCH ) -+ { -+ mvOsOutput( "no such\n" ); -+ } -+ } -+} -+ -+/******************************************************************************* -+* mvCpuIfEnablePex - Enable PCI Express. -+* -+* DESCRIPTION: -+* This function Enable PCI Express. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* pexType - MV_PEX_ROOT_COMPLEX - root complex device -+* MV_PEX_END_POINT - end point device -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+#if defined(MV_INCLUDE_PEX) -+MV_VOID mvCpuIfEnablePex(MV_U32 pexIf, MV_PEX_TYPE pexType) -+{ -+ /* Set pex mode incase S@R not exist */ -+ if( pexType == MV_PEX_END_POINT) -+ { -+ MV_REG_BIT_RESET(PEX_CTRL_REG(pexIf),PXCR_DEV_TYPE_CTRL_MASK); -+ /* Change pex mode in capability reg */ -+ MV_REG_BIT_RESET(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_CAPABILITY_REG), BIT22); -+ MV_REG_BIT_SET(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_CAPABILITY_REG), BIT20); -+ -+ } -+ else -+ { -+ MV_REG_BIT_SET(PEX_CTRL_REG(pexIf),PXCR_DEV_TYPE_CTRL_MASK); -+ } -+ -+ /* CPU config register Pex enable */ -+ MV_REG_BIT_SET(CPU_CTRL_STAT_REG,CCSR_PCI_ACCESS_MASK); -+} -+#endif -+ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h 2010-11-09 20:28:07.982495689 +0100 -@@ -0,0 +1,120 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvCpuIfh -+#define __INCmvCpuIfh -+ -+/* includes */ -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/sys/mvCpuIfRegs.h" -+#include "ctrlEnv/sys/mvAhbToMbus.h" -+#include "ddr2/mvDramIf.h" -+#include "ctrlEnv/sys/mvSysDram.h" -+#if defined(MV_INCLUDE_PEX) -+#include "pex/mvPex.h" -+#endif -+ -+/* defines */ -+ -+/* typedefs */ -+/* This structure describes CPU interface address decode window */ -+typedef struct _mvCpuIfDecWin -+{ -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_U32 winNum; /* Window Number in the AHB To Mbus bridge */ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+}MV_CPU_DEC_WIN; -+ -+ -+ -+/* mvCpuIfLib.h API list */ -+ -+/* mvCpuIfLib.h API list */ -+ -+MV_STATUS mvCpuIfInit(MV_CPU_DEC_WIN *cpuAddrWinMap); -+MV_STATUS mvCpuIfTargetWinSet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin); -+MV_STATUS mvCpuIfTargetWinGet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin); -+MV_STATUS mvCpuIfTargetWinEnable(MV_TARGET target,MV_BOOL enable); -+MV_U32 mvCpuIfTargetWinSizeGet(MV_TARGET target); -+MV_U32 mvCpuIfTargetWinBaseLowGet(MV_TARGET target); -+MV_U32 mvCpuIfTargetWinBaseHighGet(MV_TARGET target); -+MV_TARGET mvCpuIfTargetOfBaseAddressGet(MV_U32 baseAddress); -+#if defined(MV_INCLUDE_PEX) -+MV_U32 mvCpuIfPexRemap(MV_TARGET pexTarget, MV_ADDR_WIN *pAddrDecWin); -+MV_VOID mvCpuIfEnablePex(MV_U32 pexIf, MV_PEX_TYPE pexType); -+#endif -+#if defined(MV_INCLUDE_PCI) -+MV_U32 mvCpuIfPciRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin); -+#endif -+MV_U32 mvCpuIfPciIfRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin); -+ -+MV_VOID mvCpuIfAddDecShow(MV_VOID); -+ -+#if defined(MV88F6281) -+MV_STATUS mvCpuIfBridgeReorderWAInit(void); -+#endif -+ -+#endif /* __INCmvCpuIfh */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h 2010-11-09 20:28:08.012495399 +0100 -@@ -0,0 +1,304 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvCpuIfRegsh -+#define __INCmvCpuIfRegsh -+ -+/****************************************/ -+/* ARM Control and Status Registers Map */ -+/****************************************/ -+ -+#define CPU_CONFIG_REG 0x20100 -+#define CPU_CTRL_STAT_REG 0x20104 -+#define CPU_RSTOUTN_MASK_REG 0x20108 -+#define CPU_SYS_SOFT_RST_REG 0x2010C -+#define CPU_AHB_MBUS_CAUSE_INT_REG 0x20110 -+#define CPU_AHB_MBUS_MASK_INT_REG 0x20114 -+#define CPU_FTDLL_CONFIG_REG 0x20120 -+#define CPU_L2_CONFIG_REG 0x20128 -+ -+ -+ -+/* ARM Configuration register */ -+/* CPU_CONFIG_REG (CCR) */ -+ -+ -+/* Reset vector location */ -+#define CCR_VEC_INIT_LOC_OFFS 1 -+#define CCR_VEC_INIT_LOC_MASK BIT1 -+/* reset at 0x00000000 */ -+#define CCR_VEC_INIT_LOC_0000 (0 << CCR_VEC_INIT_LOC_OFFS) -+/* reset at 0xFFFF0000 */ -+#define CCR_VEC_INIT_LOC_FF00 (1 << CCR_VEC_INIT_LOC_OFFS) -+ -+ -+#define CCR_AHB_ERROR_PROP_OFFS 2 -+#define CCR_AHB_ERROR_PROP_MASK BIT2 -+/* Erros are not propogated to AHB */ -+#define CCR_AHB_ERROR_PROP_NO_INDICATE (0 << CCR_AHB_ERROR_PROP_OFFS) -+/* Erros are propogated to AHB */ -+#define CCR_AHB_ERROR_PROP_INDICATE (1 << CCR_AHB_ERROR_PROP_OFFS) -+ -+ -+#define CCR_ENDIAN_INIT_OFFS 3 -+#define CCR_ENDIAN_INIT_MASK BIT3 -+#define CCR_ENDIAN_INIT_LITTLE (0 << CCR_ENDIAN_INIT_OFFS) -+#define CCR_ENDIAN_INIT_BIG (1 << CCR_ENDIAN_INIT_OFFS) -+ -+ -+#define CCR_INCR_EN_OFFS 4 -+#define CCR_INCR_EN_MASK BIT4 -+#define CCR_INCR_EN BIT4 -+ -+ -+#define CCR_NCB_BLOCKING_OFFS 5 -+#define CCR_NCB_BLOCKING_MASK (1 << CCR_NCB_BLOCKING_OFFS) -+#define CCR_NCB_BLOCKING_NON (0 << CCR_NCB_BLOCKING_OFFS) -+#define CCR_NCB_BLOCKING_EN (1 << CCR_NCB_BLOCKING_OFFS) -+ -+#define CCR_CPU_2_MBUSL_TICK_DRV_OFFS 8 -+#define CCR_CPU_2_MBUSL_TICK_DRV_MASK (0xF << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) -+#define CCR_CPU_2_MBUSL_TICK_SMPL_OFFS 12 -+#define CCR_CPU_2_MBUSL_TICK_SMPL_MASK (0xF << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS) -+#define CCR_ICACH_PREF_BUF_ENABLE BIT16 -+#define CCR_DCACH_PREF_BUF_ENABLE BIT17 -+ -+/* Ratio options for CPU to DDR for 6281/6192/6190 */ -+#define CPU_2_DDR_CLK_1x3 4 -+#define CPU_2_DDR_CLK_1x4 6 -+ -+/* Ratio options for CPU to DDR for 6281 only */ -+#define CPU_2_DDR_CLK_2x9 7 -+#define CPU_2_DDR_CLK_1x5 8 -+#define CPU_2_DDR_CLK_1x6 9 -+ -+/* Ratio options for CPU to DDR for 6180 only */ -+#define CPU_2_DDR_CLK_1x3_1 0x5 -+#define CPU_2_DDR_CLK_1x4_1 0x6 -+ -+/* Default values for CPU to Mbus-L DDR Interface Tick Driver and */ -+/* CPU to Mbus-L Tick Sample fields in CPU config register */ -+ -+#define TICK_DRV_1x1 0 -+#define TICK_DRV_1x2 0 -+#define TICK_DRV_1x3 1 -+#define TICK_DRV_1x4 2 -+#define TICK_SMPL_1x1 0 -+#define TICK_SMPL_1x2 1 -+#define TICK_SMPL_1x3 0 -+#define TICK_SMPL_1x4 0 -+ -+#define CPU_2_MBUSL_DDR_CLK_1x2 \ -+ ((TICK_DRV_1x2 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \ -+ (TICK_SMPL_1x2 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS)) -+#define CPU_2_MBUSL_DDR_CLK_1x3 \ -+ ((TICK_DRV_1x3 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \ -+ (TICK_SMPL_1x3 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS)) -+#define CPU_2_MBUSL_DDR_CLK_1x4 \ -+ ((TICK_DRV_1x4 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \ -+ (TICK_SMPL_1x4 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS)) -+ -+/* ARM Control and Status register */ -+/* CPU_CTRL_STAT_REG (CCSR) */ -+ -+ -+/* -+This is used to block PCI express\PCI from access Socrates/Feroceon GP -+while ARM boot is still in progress -+*/ -+ -+#define CCSR_PCI_ACCESS_OFFS 0 -+#define CCSR_PCI_ACCESS_MASK BIT0 -+#define CCSR_PCI_ACCESS_ENABLE (0 << CCSR_PCI_ACCESS_OFFS) -+#define CCSR_PCI_ACCESS_DISBALE (1 << CCSR_PCI_ACCESS_OFFS) -+ -+#define CCSR_ARM_RESET BIT1 -+#define CCSR_SELF_INT BIT2 -+#define CCSR_BIG_ENDIAN BIT15 -+ -+ -+/* RSTOUTn Mask Register */ -+/* CPU_RSTOUTN_MASK_REG (CRMR) */ -+ -+#define CRMR_PEX_RST_OUT_OFFS 0 -+#define CRMR_PEX_RST_OUT_MASK BIT0 -+#define CRMR_PEX_RST_OUT_ENABLE (1 << CRMR_PEX_RST_OUT_OFFS) -+#define CRMR_PEX_RST_OUT_DISABLE (0 << CRMR_PEX_RST_OUT_OFFS) -+ -+#define CRMR_WD_RST_OUT_OFFS 1 -+#define CRMR_WD_RST_OUT_MASK BIT1 -+#define CRMR_WD_RST_OUT_ENABLE (1 << CRMR_WD_RST_OUT_OFFS) -+#define CRMR_WD_RST_OUT_DISBALE (0 << CRMR_WD_RST_OUT_OFFS) -+ -+#define CRMR_SOFT_RST_OUT_OFFS 2 -+#define CRMR_SOFT_RST_OUT_MASK BIT2 -+#define CRMR_SOFT_RST_OUT_ENABLE (1 << CRMR_SOFT_RST_OUT_OFFS) -+#define CRMR_SOFT_RST_OUT_DISBALE (0 << CRMR_SOFT_RST_OUT_OFFS) -+ -+/* System Software Reset Register */ -+/* CPU_SYS_SOFT_RST_REG (CSSRR) */ -+ -+#define CSSRR_SYSTEM_SOFT_RST BIT0 -+ -+/* AHB to Mbus Bridge Interrupt Cause Register*/ -+/* CPU_AHB_MBUS_CAUSE_INT_REG (CAMCIR) */ -+ -+#define CAMCIR_ARM_SELF_INT BIT0 -+#define CAMCIR_ARM_TIMER0_INT_REQ BIT1 -+#define CAMCIR_ARM_TIMER1_INT_REQ BIT2 -+#define CAMCIR_ARM_WD_TIMER_INT_REQ BIT3 -+ -+ -+/* AHB to Mbus Bridge Interrupt Mask Register*/ -+/* CPU_AHB_MBUS_MASK_INT_REG (CAMMIR) */ -+ -+#define CAMCIR_ARM_SELF_INT_OFFS 0 -+#define CAMCIR_ARM_SELF_INT_MASK BIT0 -+#define CAMCIR_ARM_SELF_INT_EN (1 << CAMCIR_ARM_SELF_INT_OFFS) -+#define CAMCIR_ARM_SELF_INT_DIS (0 << CAMCIR_ARM_SELF_INT_OFFS) -+ -+ -+#define CAMCIR_ARM_TIMER0_INT_REQ_OFFS 1 -+#define CAMCIR_ARM_TIMER0_INT_REQ_MASK BIT1 -+#define CAMCIR_ARM_TIMER0_INT_REQ_EN (1 << CAMCIR_ARM_TIMER0_INT_REQ_OFFS) -+#define CAMCIR_ARM_TIMER0_INT_REQ_DIS (0 << CAMCIR_ARM_TIMER0_INT_REQ_OFFS) -+ -+#define CAMCIR_ARM_TIMER1_INT_REQ_OFFS 2 -+#define CAMCIR_ARM_TIMER1_INT_REQ_MASK BIT2 -+#define CAMCIR_ARM_TIMER1_INT_REQ_EN (1 << CAMCIR_ARM_TIMER1_INT_REQ_OFFS) -+#define CAMCIR_ARM_TIMER1_INT_REQ_DIS (0 << CAMCIR_ARM_TIMER1_INT_REQ_OFFS) -+ -+#define CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS 3 -+#define CAMCIR_ARM_WD_TIMER_INT_REQ_MASK BIT3 -+#define CAMCIR_ARM_WD_TIMER_INT_REQ_EN (1 << CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS) -+#define CAMCIR_ARM_WD_TIMER_INT_REQ_DIS (0 << CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS) -+ -+/* CPU FTDLL Config register (CFCR) fields */ -+#define CFCR_FTDLL_ICACHE_TAG_OFFS 0 -+#define CFCR_FTDLL_ICACHE_TAG_MASK (0x7F << CFCR_FTDLL_ICACHE_TAG_OFFS) -+#define CFCR_FTDLL_DCACHE_TAG_OFFS 8 -+#define CFCR_FTDLL_DCACHE_TAG_MASK (0x7F << CFCR_FTDLL_DCACHE_TAG_OFFS) -+#define CFCR_FTDLL_OVERWRITE_ENABLE (1 << 15) -+/* For Orion 2 D2 only */ -+#define CFCR_MRVL_CPU_ID_OFFS 16 -+#define CFCR_MRVL_CPU_ID_MASK (0x1 << CFCR_MRVL_CPU_ID_OFFS) -+#define CFCR_ARM_CPU_ID (0x0 << CFCR_MRVL_CPU_ID_OFFS) -+#define CFCR_MRVL_CPU_ID (0x1 << CFCR_MRVL_CPU_ID_OFFS) -+#define CFCR_VFP_SUB_ARC_NUM_OFFS 7 -+#define CFCR_VFP_SUB_ARC_NUM_MASK (0x1 << CFCR_VFP_SUB_ARC_NUM_OFFS) -+#define CFCR_VFP_SUB_ARC_NUM_1 (0x0 << CFCR_VFP_SUB_ARC_NUM_OFFS) -+#define CFCR_VFP_SUB_ARC_NUM_2 (0x1 << CFCR_VFP_SUB_ARC_NUM_OFFS) -+ -+/* CPU_L2_CONFIG_REG fields */ -+#ifdef MV_CPU_LE -+#define CL2CR_L2_ECC_EN_OFFS 2 -+#define CL2CR_L2_WT_MODE_OFFS 4 -+#else -+#define CL2CR_L2_ECC_EN_OFFS 26 -+#define CL2CR_L2_WT_MODE_OFFS 28 -+#endif -+ -+#define CL2CR_L2_ECC_EN_MASK (1 << CL2CR_L2_ECC_EN_OFFS) -+#define CL2CR_L2_WT_MODE_MASK (1 << CL2CR_L2_WT_MODE_OFFS) -+ -+/*******************************************/ -+/* Main Interrupt Controller Registers Map */ -+/*******************************************/ -+ -+#define CPU_MAIN_INT_CAUSE_REG 0x20200 -+#define CPU_MAIN_IRQ_MASK_REG 0x20204 -+#define CPU_MAIN_FIQ_MASK_REG 0x20208 -+#define CPU_ENPOINT_MASK_REG 0x2020C -+#define CPU_MAIN_INT_CAUSE_HIGH_REG 0x20210 -+#define CPU_MAIN_IRQ_MASK_HIGH_REG 0x20214 -+#define CPU_MAIN_FIQ_MASK_HIGH_REG 0x20218 -+#define CPU_ENPOINT_MASK_HIGH_REG 0x2021C -+ -+ -+/*******************************************/ -+/* ARM Doorbell Registers Map */ -+/*******************************************/ -+ -+#define CPU_HOST_TO_ARM_DRBL_REG 0x20400 -+#define CPU_HOST_TO_ARM_MASK_REG 0x20404 -+#define CPU_ARM_TO_HOST_DRBL_REG 0x20408 -+#define CPU_ARM_TO_HOST_MASK_REG 0x2040C -+ -+ -+ -+/* CPU control register map */ -+/* Set bits means value is about to change according to new value */ -+#define CPU_CONFIG_DEFAULT_MASK (CCR_VEC_INIT_LOC_MASK | CCR_AHB_ERROR_PROP_MASK) -+ -+#define CPU_CONFIG_DEFAULT (CCR_VEC_INIT_LOC_FF00) -+ -+/* CPU Control and status defaults */ -+#define CPU_CTRL_STAT_DEFAULT_MASK (CCSR_PCI_ACCESS_MASK) -+ -+ -+#define CPU_CTRL_STAT_DEFAULT (CCSR_PCI_ACCESS_ENABLE) -+ -+#endif /* __INCmvCpuIfRegsh */ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c 2010-11-09 20:28:08.042495347 +0100 -@@ -0,0 +1,324 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#include "mvSysAudio.h" -+ -+/******************************************************************************* -+* mvAudioWinSet - Set AUDIO target address window -+* -+* DESCRIPTION: -+* This function sets a peripheral target (e.g. SDRAM bank0, PCI_MEM0) -+* address window, also known as address decode window. -+* After setting this target window, the AUDIO will be able to access the -+* target within the address window. -+* -+* INPUT: -+* winNum - AUDIO target address decode window number. -+* pAddrDecWin - AUDIO target window data structure. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR if address window overlapps with other address decode windows. -+* MV_BAD_PARAM if base address is invalid parameter or target is -+* unknown. -+* -+*******************************************************************************/ -+MV_STATUS mvAudioWinSet(MV_U32 winNum, MV_AUDIO_DEC_WIN *pAddrDecWin) -+{ -+ MV_TARGET_ATTRIB targetAttribs; -+ MV_DEC_REGS decRegs; -+ -+ /* Parameter checking */ -+ if (winNum >= MV_AUDIO_MAX_ADDR_DECODE_WIN) -+ { -+ mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvAudioWinSet:Error setting AUDIO window %d to "\ -+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, -+ mvCtrlTargetNameGet(pAddrDecWin->target), -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ decRegs.baseReg = 0; -+ decRegs.sizeReg = 0; -+ -+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) -+ { -+ mvOsPrintf("%s: mvCtrlAddrDecToReg Failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); -+ -+ /* set attributes */ -+ decRegs.sizeReg &= ~MV_AUDIO_WIN_ATTR_MASK; -+ decRegs.sizeReg |= (targetAttribs.attrib << MV_AUDIO_WIN_ATTR_OFFSET); -+ -+ /* set target ID */ -+ decRegs.sizeReg &= ~MV_AUDIO_WIN_TARGET_MASK; -+ decRegs.sizeReg |= (targetAttribs.targetId << MV_AUDIO_WIN_TARGET_OFFSET); -+ -+ if (pAddrDecWin->enable == MV_TRUE) -+ { -+ decRegs.sizeReg |= MV_AUDIO_WIN_ENABLE_MASK; -+ } -+ else -+ { -+ decRegs.sizeReg &= ~MV_AUDIO_WIN_ENABLE_MASK; -+ } -+ -+ MV_REG_WRITE( MV_AUDIO_WIN_CTRL_REG(winNum), decRegs.sizeReg); -+ MV_REG_WRITE( MV_AUDIO_WIN_BASE_REG(winNum), decRegs.baseReg); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvAudioWinGet - Get AUDIO peripheral target address window. -+* -+* DESCRIPTION: -+* Get AUDIO peripheral target address window. -+* -+* INPUT: -+* winNum - AUDIO target address decode window number. -+* -+* OUTPUT: -+* pAddrDecWin - AUDIO target window data structure. -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvAudioWinGet(MV_U32 winNum, MV_AUDIO_DEC_WIN *pAddrDecWin) -+{ -+ MV_DEC_REGS decRegs; -+ MV_TARGET_ATTRIB targetAttrib; -+ -+ /* Parameter checking */ -+ if (winNum >= MV_AUDIO_MAX_ADDR_DECODE_WIN) -+ { -+ mvOsPrintf("%s : ERR. Invalid winNum %d\n", -+ __FUNCTION__, winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ decRegs.baseReg = MV_REG_READ( MV_AUDIO_WIN_BASE_REG(winNum) ); -+ decRegs.sizeReg = MV_REG_READ( MV_AUDIO_WIN_CTRL_REG(winNum) ); -+ -+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs, &pAddrDecWin->addrWin) ) -+ { -+ mvOsPrintf("%s: mvCtrlRegToAddrDec Failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ /* attrib and targetId */ -+ targetAttrib.attrib = (decRegs.sizeReg & MV_AUDIO_WIN_ATTR_MASK) >> -+ MV_AUDIO_WIN_ATTR_OFFSET; -+ targetAttrib.targetId = (decRegs.sizeReg & MV_AUDIO_WIN_TARGET_MASK) >> -+ MV_AUDIO_WIN_TARGET_OFFSET; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ /* Check if window is enabled */ -+ if(decRegs.sizeReg & MV_AUDIO_WIN_ENABLE_MASK) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ } -+ return MV_OK; -+} -+/******************************************************************************* -+* mvAudioAddrDecShow - Print the AUDIO address decode map. -+* -+* DESCRIPTION: -+* This function print the AUDIO address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvAudioAddrDecShow(MV_VOID) -+{ -+ -+ MV_AUDIO_DEC_WIN win; -+ int i; -+ -+ if (MV_FALSE == mvCtrlPwrClckGet(AUDIO_UNIT_ID, 0)) -+ return; -+ -+ -+ mvOsOutput( "\n" ); -+ mvOsOutput( "AUDIO:\n" ); -+ mvOsOutput( "----\n" ); -+ -+ for( i = 0; i < MV_AUDIO_MAX_ADDR_DECODE_WIN; i++ ) -+ { -+ memset( &win, 0, sizeof(MV_AUDIO_DEC_WIN) ); -+ -+ mvOsOutput( "win%d - ", i ); -+ -+ if( mvAudioWinGet( i, &win ) == MV_OK ) -+ { -+ if( win.enable ) -+ { -+ mvOsOutput( "%s base %08x, ", -+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); -+ mvOsOutput( "...." ); -+ -+ mvSizePrint( win.addrWin.size ); -+ -+ mvOsOutput( "\n" ); -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ } -+ } -+} -+ -+ -+/******************************************************************************* -+* mvAudioWinInit - Initialize the integrated AUDIO target address window. -+* -+* DESCRIPTION: -+* Initialize the AUDIO peripheral target address window. -+* -+* INPUT: -+* -+* -+* OUTPUT: -+* -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvAudioInit(MV_VOID) -+{ -+ int winNum; -+ MV_AUDIO_DEC_WIN audioWin; -+ MV_CPU_DEC_WIN cpuAddrDecWin; -+ MV_U32 status; -+ -+ mvAudioHalInit(); -+ -+ /* Initiate Audio address decode */ -+ -+ /* First disable all address decode windows */ -+ for(winNum = 0; winNum < MV_AUDIO_MAX_ADDR_DECODE_WIN; winNum++) -+ { -+ MV_U32 regVal = MV_REG_READ(MV_AUDIO_WIN_CTRL_REG(winNum)); -+ regVal &= ~MV_AUDIO_WIN_ENABLE_MASK; -+ MV_REG_WRITE(MV_AUDIO_WIN_CTRL_REG(winNum), regVal); -+ } -+ -+ for(winNum = 0; winNum < MV_AUDIO_MAX_ADDR_DECODE_WIN; winNum++) -+ { -+ -+ /* We will set the Window to DRAM_CS0 in default */ -+ /* first get attributes from CPU If */ -+ status = mvCpuIfTargetWinGet(SDRAM_CS0, -+ &cpuAddrDecWin); -+ -+ if (MV_OK != status) -+ { -+ mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ if (cpuAddrDecWin.enable == MV_TRUE) -+ { -+ audioWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; -+ audioWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; -+ audioWin.addrWin.size = cpuAddrDecWin.addrWin.size; -+ audioWin.enable = MV_TRUE; -+ audioWin.target = SDRAM_CS0; -+ -+ if(MV_OK != mvAudioWinSet(winNum, &audioWin)) -+ { -+ return MV_ERROR; -+ } -+ } -+ } -+ -+ return MV_OK; -+} -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h 2010-11-09 20:28:08.082495466 +0100 -@@ -0,0 +1,123 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#ifndef __INCMVSysAudioH -+#define __INCMVSysAudioH -+ -+#include "mvCommon.h" -+#include "audio/mvAudio.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+ -+/***********************************/ -+/* Audio Address Decoding registers*/ -+/***********************************/ -+ -+#define MV_AUDIO_MAX_ADDR_DECODE_WIN 2 -+#define MV_AUDIO_RECORD_WIN_NUM 0 -+#define MV_AUDIO_PLAYBACK_WIN_NUM 1 -+ -+#define MV_AUDIO_WIN_CTRL_REG(win) (AUDIO_REG_BASE + 0xA04 + ((win)<<3)) -+#define MV_AUDIO_WIN_BASE_REG(win) (AUDIO_REG_BASE + 0xA00 + ((win)<<3)) -+ -+#define MV_AUDIO_RECORD_WIN_CTRL_REG MV_AUDIO_WIN_CTRL_REG(MV_AUDIO_RECORD_WIN_NUM) -+#define MV_AUDIO_RECORD_WIN_BASE_REG MV_AUDIO_WIN_BASE_REG(MV_AUDIO_RECORD_WIN_NUM) -+#define MV_AUDIO_PLAYBACK_WIN_CTRL_REG MV_AUDIO_WIN_CTRL_REG(MV_AUDIO_PLAYBACK_WIN_NUM) -+#define MV_AUDIO_PLAYBACK_WIN_BASE_REG MV_AUDIO_WIN_BASE_REG(MV_AUDIO_PLAYBACK_WIN_NUM) -+ -+ -+/* BITs in Windows 0-3 Control and Base Registers */ -+#define MV_AUDIO_WIN_ENABLE_BIT 0 -+#define MV_AUDIO_WIN_ENABLE_MASK (1<= 2) -+MV_TARGET tdmaAddrDecPrioTable[] = -+{ -+#if defined(MV_INCLUDE_SDRAM_CS0) -+ SDRAM_CS0, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS1) -+ SDRAM_CS1, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS2) -+ SDRAM_CS2, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS3) -+ SDRAM_CS3, -+#endif -+#if defined(MV_INCLUDE_PEX) -+ PEX0_MEM, -+#endif -+ -+ TBL_TERM -+}; -+ -+/******************************************************************************* -+* mvCesaWinGet - Get TDMA target address window. -+* -+* DESCRIPTION: -+* Get TDMA target address window. -+* -+* INPUT: -+* winNum - TDMA target address decode window number. -+* -+* OUTPUT: -+* pDecWin - TDMA target window data structure. -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+static MV_STATUS mvCesaWinGet(MV_U32 winNum, MV_DEC_WIN *pDecWin) -+{ -+ MV_DEC_WIN_PARAMS winParam; -+ MV_U32 sizeReg, baseReg; -+ -+ /* Parameter checking */ -+ if (winNum >= MV_CESA_TDMA_ADDR_DEC_WIN) -+ { -+ mvOsPrintf("%s : ERR. Invalid winNum %d\n", -+ __FUNCTION__, winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ baseReg = MV_REG_READ( MV_CESA_TDMA_BASE_ADDR_REG(winNum) ); -+ sizeReg = MV_REG_READ( MV_CESA_TDMA_WIN_CTRL_REG(winNum) ); -+ -+ /* Check if window is enabled */ -+ if(sizeReg & MV_CESA_TDMA_WIN_ENABLE_MASK) -+ { -+ pDecWin->enable = MV_TRUE; -+ -+ /* Extract window parameters from registers */ -+ winParam.targetId = (sizeReg & MV_CESA_TDMA_WIN_TARGET_MASK) >> MV_CESA_TDMA_WIN_TARGET_OFFSET; -+ winParam.attrib = (sizeReg & MV_CESA_TDMA_WIN_ATTR_MASK) >> MV_CESA_TDMA_WIN_ATTR_OFFSET; -+ winParam.size = (sizeReg & MV_CESA_TDMA_WIN_SIZE_MASK) >> MV_CESA_TDMA_WIN_SIZE_OFFSET; -+ winParam.baseAddr = (baseReg & MV_CESA_TDMA_WIN_BASE_MASK); -+ -+ /* Translate the decode window parameters to address decode struct */ -+ if (MV_OK != mvCtrlParamsToAddrDec(&winParam, pDecWin)) -+ { -+ mvOsPrintf("Failed to translate register parameters to CESA address" \ -+ " decode window structure\n"); -+ return MV_ERROR; -+ } -+ } -+ else -+ { -+ pDecWin->enable = MV_FALSE; -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* cesaWinOverlapDetect - Detect CESA TDMA address windows overlapping -+* -+* DESCRIPTION: -+* An unpredicted behaviur is expected in case TDMA address decode -+* windows overlapps. -+* This function detects TDMA address decode windows overlapping of a -+* specified window. The function does not check the window itself for -+* overlapping. The function also skipps disabled address decode windows. -+* -+* INPUT: -+* winNum - address decode window number. -+* pAddrDecWin - An address decode window struct. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE - if the given address window overlap current address -+* decode map, -+* MV_FALSE - otherwise, MV_ERROR if reading invalid data -+* from registers. -+* -+*******************************************************************************/ -+static MV_STATUS cesaWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 winNumIndex; -+ MV_DEC_WIN addrDecWin; -+ -+ for(winNumIndex=0; winNumIndex= MV_CESA_TDMA_ADDR_DEC_WIN) -+ { -+ mvOsPrintf("mvCesaTdmaWinSet: ERR. Invalid win num %d\n",winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlapps with current windows */ -+ if (MV_TRUE == cesaWinOverlapDetect(winNum, &pDecWin->addrWin)) -+ { -+ mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); -+ return MV_ERROR; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pDecWin->addrWin.baseLow, pDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvCesaTdmaWinSet: Error setting CESA TDMA window %d to "\ -+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, -+ mvCtrlTargetNameGet(pDecWin->target), -+ pDecWin->addrWin.baseLow, -+ pDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ if(MV_OK != mvCtrlAddrDecToParams(pDecWin, &winParams)) -+ { -+ mvOsPrintf("%s: mvCtrlAddrDecToParams Failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ /* set Size, Attributes and TargetID */ -+ sizeReg = (((winParams.targetId << MV_CESA_TDMA_WIN_TARGET_OFFSET) & MV_CESA_TDMA_WIN_TARGET_MASK) | -+ ((winParams.attrib << MV_CESA_TDMA_WIN_ATTR_OFFSET) & MV_CESA_TDMA_WIN_ATTR_MASK) | -+ ((winParams.size << MV_CESA_TDMA_WIN_SIZE_OFFSET) & MV_CESA_TDMA_WIN_SIZE_MASK)); -+ -+ if (pDecWin->enable == MV_TRUE) -+ { -+ sizeReg |= MV_CESA_TDMA_WIN_ENABLE_MASK; -+ } -+ else -+ { -+ sizeReg &= ~MV_CESA_TDMA_WIN_ENABLE_MASK; -+ } -+ -+ /* Update Base value */ -+ baseReg = (winParams.baseAddr & MV_CESA_TDMA_WIN_BASE_MASK); -+ -+ MV_REG_WRITE( MV_CESA_TDMA_WIN_CTRL_REG(winNum), sizeReg); -+ MV_REG_WRITE( MV_CESA_TDMA_BASE_ADDR_REG(winNum), baseReg); -+ -+ return MV_OK; -+} -+ -+ -+static MV_STATUS mvCesaTdmaAddrDecInit (void) -+{ -+ MV_U32 winNum; -+ MV_STATUS status; -+ MV_CPU_DEC_WIN cpuAddrDecWin; -+ MV_DEC_WIN cesaWin; -+ MV_U32 winPrioIndex = 0; -+ -+ /* First disable all address decode windows */ -+ for(winNum=0; winNum= 2 */ -+ -+ -+ -+ -+MV_STATUS mvCesaInit (int numOfSession, int queueDepth, char* pSramBase, void *osHandle) -+{ -+ MV_U32 cesaCryptEngBase; -+ MV_CPU_DEC_WIN addrDecWin; -+ -+ if(sizeof(MV_CESA_SRAM_MAP) > MV_CESA_SRAM_SIZE) -+ { -+ mvOsPrintf("mvCesaInit: Wrong SRAM map - %ld > %d\n", -+ sizeof(MV_CESA_SRAM_MAP), MV_CESA_SRAM_SIZE); -+ return MV_FAIL; -+ } -+#if 0 -+ if (mvCpuIfTargetWinGet(CRYPT_ENG, &addrDecWin) == MV_OK) -+ cesaCryptEngBase = addrDecWin.addrWin.baseLow; -+ else -+ { -+ mvOsPrintf("mvCesaInit: ERR. mvCpuIfTargetWinGet failed\n"); -+ return MV_ERROR; -+ } -+#else -+ cesaCryptEngBase = (MV_U32)pSramBase; -+#endif -+ -+#if 0 /* Already done in the platform init */ -+#if (MV_CESA_VERSION >= 2) -+ mvCesaTdmaAddrDecInit(); -+#endif /* MV_CESA_VERSION >= 2 */ -+#endif -+ return mvCesaHalInit(numOfSession, queueDepth, pSramBase, cesaCryptEngBase, -+ osHandle); -+ -+} -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h 2010-11-09 20:28:08.152495441 +0100 -@@ -0,0 +1,100 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __mvSysCesa_h__ -+#define __mvSysCesa_h__ -+ -+ -+#include "mvCommon.h" -+#include "cesa/mvCesa.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+ -+/***************************** TDMA Registers *************************************/ -+ -+#define MV_CESA_TDMA_ADDR_DEC_WIN 4 -+ -+#define MV_CESA_TDMA_BASE_ADDR_REG(win) (MV_CESA_TDMA_REG_BASE + 0xa00 + (win<<3)) -+ -+#define MV_CESA_TDMA_WIN_CTRL_REG(win) (MV_CESA_TDMA_REG_BASE + 0xa04 + (win<<3)) -+ -+#define MV_CESA_TDMA_WIN_ENABLE_BIT 0 -+#define MV_CESA_TDMA_WIN_ENABLE_MASK (1 << MV_CESA_TDMA_WIN_ENABLE_BIT) -+ -+#define MV_CESA_TDMA_WIN_TARGET_OFFSET 4 -+#define MV_CESA_TDMA_WIN_TARGET_MASK (0xf << MV_CESA_TDMA_WIN_TARGET_OFFSET) -+ -+#define MV_CESA_TDMA_WIN_ATTR_OFFSET 8 -+#define MV_CESA_TDMA_WIN_ATTR_MASK (0xff << MV_CESA_TDMA_WIN_ATTR_OFFSET) -+ -+#define MV_CESA_TDMA_WIN_SIZE_OFFSET 16 -+#define MV_CESA_TDMA_WIN_SIZE_MASK (0xFFFF << MV_CESA_TDMA_WIN_SIZE_OFFSET) -+ -+#define MV_CESA_TDMA_WIN_BASE_OFFSET 16 -+#define MV_CESA_TDMA_WIN_BASE_MASK (0xFFFF << MV_CESA_TDMA_WIN_BASE_OFFSET) -+ -+ -+MV_STATUS mvCesaInit (int numOfSession, int queueDepth, char* pSramBase, void *osHandle); -+ -+#endif -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.c 2010-11-09 20:28:08.192500699 +0100 -@@ -0,0 +1,348 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+/* includes */ -+ -+#include "ddr2/mvDramIf.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+#include "ctrlEnv/sys/mvSysDram.h" -+ -+/* #define MV_DEBUG */ -+#ifdef MV_DEBUG -+#define DB(x) x -+#else -+#define DB(x) -+#endif -+ -+static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin); -+ -+/******************************************************************************* -+* mvDramIfWinSet - Set DRAM interface address decode window -+* -+* DESCRIPTION: -+* This function sets DRAM interface address decode window. -+* -+* INPUT: -+* target - System target. Use only SDRAM targets. -+* pAddrDecWin - SDRAM address window structure. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK -+* otherwise. -+*******************************************************************************/ -+MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) -+{ -+ MV_U32 baseReg=0,sizeReg=0; -+ MV_U32 baseToReg=0 , sizeToReg=0; -+ -+ /* Check parameters */ -+ if (!MV_TARGET_IS_DRAM(target)) -+ { -+ mvOsPrintf("mvDramIfWinSet: target %d is not SDRAM\n", target); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlaps with current enabled windows */ -+ if (MV_TRUE == sdramIfWinOverlap(target, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("mvDramIfWinSet: ERR. Target %d overlaps\n", target); -+ return MV_BAD_PARAM; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvDramIfWinSet:Error setting DRAM interface window %d."\ -+ "\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ target, -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ /* read base register*/ -+ baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(0,target)); -+ -+ /* read size register */ -+ sizeReg = MV_REG_READ(SDRAM_SIZE_REG(0,target)); -+ -+ /* BaseLow[31:16] => base register [31:16] */ -+ baseToReg = pAddrDecWin->addrWin.baseLow & SCBAR_BASE_MASK; -+ -+ /* Write to address decode Base Address Register */ -+ baseReg &= ~SCBAR_BASE_MASK; -+ baseReg |= baseToReg; -+ -+ /* Translate the given window size to register format */ -+ sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, SCSR_SIZE_ALIGNMENT); -+ -+ /* Size parameter validity check. */ -+ if (-1 == sizeToReg) -+ { -+ mvOsPrintf("mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n",target); -+ return MV_BAD_PARAM; -+ } -+ -+ /* set size */ -+ sizeReg &= ~SCSR_SIZE_MASK; -+ /* Size is located at upper 16 bits */ -+ sizeReg |= (sizeToReg << SCSR_SIZE_OFFS); -+ -+ /* enable/Disable */ -+ if (MV_TRUE == pAddrDecWin->enable) -+ { -+ sizeReg |= SCSR_WIN_EN; -+ } -+ else -+ { -+ sizeReg &= ~SCSR_WIN_EN; -+ } -+ -+ /* 3) Write to address decode Base Address Register */ -+ MV_REG_WRITE(SDRAM_BASE_ADDR_REG(0,target), baseReg); -+ -+ /* Write to address decode Size Register */ -+ MV_REG_WRITE(SDRAM_SIZE_REG(0,target), sizeReg); -+ -+ return MV_OK; -+} -+/******************************************************************************* -+* mvDramIfWinGet - Get DRAM interface address decode window -+* -+* DESCRIPTION: -+* This function gets DRAM interface address decode window. -+* -+* INPUT: -+* target - System target. Use only SDRAM targets. -+* -+* OUTPUT: -+* pAddrDecWin - SDRAM address window structure. -+* -+* RETURN: -+* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK -+* otherwise. -+*******************************************************************************/ -+MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) -+{ -+ MV_U32 baseReg,sizeReg; -+ MV_U32 sizeRegVal; -+ /* Check parameters */ -+ if (!MV_TARGET_IS_DRAM(target)) -+ { -+ mvOsPrintf("mvDramIfWinGet: target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ /* Read base and size registers */ -+ sizeReg = MV_REG_READ(SDRAM_SIZE_REG(0,target)); -+ baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(0,target)); -+ -+ sizeRegVal = (sizeReg & SCSR_SIZE_MASK) >> SCSR_SIZE_OFFS; -+ -+ pAddrDecWin->addrWin.size = ctrlRegToSize(sizeRegVal, -+ SCSR_SIZE_ALIGNMENT); -+ -+ /* Check if ctrlRegToSize returned OK */ -+ if (-1 == pAddrDecWin->addrWin.size) -+ { -+ mvOsPrintf("mvDramIfWinGet: size of target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ /* Extract base address */ -+ /* Base register [31:16] ==> baseLow[31:16] */ -+ pAddrDecWin->addrWin.baseLow = baseReg & SCBAR_BASE_MASK; -+ -+ pAddrDecWin->addrWin.baseHigh = 0; -+ -+ -+ if (sizeReg & SCSR_WIN_EN) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ } -+ -+ return MV_OK; -+} -+/******************************************************************************* -+* mvDramIfWinEnable - Enable/Disable SDRAM address decode window -+* -+* DESCRIPTION: -+* This function enable/Disable SDRAM address decode window. -+* -+* INPUT: -+* target - System target. Use only SDRAM targets. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR in case function parameter are invalid, MV_OK otherewise. -+* -+*******************************************************************************/ -+MV_STATUS mvDramIfWinEnable(MV_TARGET target, MV_BOOL enable) -+{ -+ MV_DRAM_DEC_WIN addrDecWin; -+ -+ /* Check parameters */ -+ if (!MV_TARGET_IS_DRAM(target)) -+ { -+ mvOsPrintf("mvDramIfWinEnable: target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ if (enable == MV_TRUE) -+ { /* First check for overlap with other enabled windows */ -+ if (MV_OK != mvDramIfWinGet(target, &addrDecWin)) -+ { -+ mvOsPrintf("mvDramIfWinEnable:ERR. Getting target %d failed.\n", -+ target); -+ return MV_ERROR; -+ } -+ /* Check for overlapping */ -+ if (MV_FALSE == sdramIfWinOverlap(target, &(addrDecWin.addrWin))) -+ { -+ /* No Overlap. Enable address decode winNum window */ -+ MV_REG_BIT_SET(SDRAM_SIZE_REG(0,target), SCSR_WIN_EN); -+ } -+ else -+ { /* Overlap detected */ -+ mvOsPrintf("mvDramIfWinEnable: ERR. Target %d overlap detect\n", -+ target); -+ return MV_ERROR; -+ } -+ } -+ else -+ { /* Disable address decode winNum window */ -+ MV_REG_BIT_RESET(SDRAM_SIZE_REG(0, target), SCSR_WIN_EN); -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* sdramIfWinOverlap - Check if an address window overlap an SDRAM address window -+* -+* DESCRIPTION: -+* This function scan each SDRAM address decode window to test if it -+* overlapps the given address windoow -+* -+* INPUT: -+* target - SDRAM target where the function skips checking. -+* pAddrDecWin - The tested address window for overlapping with -+* SDRAM windows. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlaps any enabled address -+* decode map, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_TARGET targetNum; -+ MV_DRAM_DEC_WIN addrDecWin; -+ -+ for(targetNum = SDRAM_CS0; targetNum < MV_DRAM_MAX_CS ; targetNum++) -+ { -+ /* don't check our winNum or illegal targets */ -+ if (targetNum == target) -+ { -+ continue; -+ } -+ -+ /* Get window parameters */ -+ if (MV_OK != mvDramIfWinGet(targetNum, &addrDecWin)) -+ { -+ mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); -+ return MV_ERROR; -+ } -+ -+ /* Do not check disabled windows */ -+ if (MV_FALSE == addrDecWin.enable) -+ { -+ continue; -+ } -+ -+ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) -+ { -+ mvOsPrintf( -+ "sdramIfWinOverlap: Required target %d overlap winNum %d\n", -+ target, targetNum); -+ return MV_TRUE; -+ } -+ } -+ -+ return MV_FALSE; -+} -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h 2010-11-09 20:28:08.232495451 +0100 -@@ -0,0 +1,80 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __sysDram -+#define __sysDram -+ -+/* This structure describes CPU interface address decode window */ -+typedef struct _mvDramIfDecWin -+{ -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+}MV_DRAM_DEC_WIN; -+ -+MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); -+MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); -+MV_STATUS mvDramIfWinEnable(MV_TARGET target, MV_BOOL enable); -+ -+#endif -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c 2010-11-09 20:28:08.262495451 +0100 -@@ -0,0 +1,658 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#include "ctrlEnv/sys/mvSysGbe.h" -+ -+ -+ -+typedef struct _mvEthDecWin -+{ -+ MV_TARGET target; -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+}MV_ETH_DEC_WIN; -+ -+MV_TARGET ethAddrDecPrioTap[] = -+{ -+#if defined(MV_INCLUDE_SDRAM_CS0) -+ SDRAM_CS0, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS1) -+ SDRAM_CS1, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS2) -+ SDRAM_CS2, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS3) -+ SDRAM_CS3, -+#endif -+#if defined(MV_INCLUDE_DEVICE_CS0) -+ DEVICE_CS0, -+#endif -+#if defined(MV_INCLUDE_DEVICE_CS1) -+ DEVICE_CS1, -+#endif -+#if defined(MV_INCLUDE_DEVICE_CS2) -+ DEVICE_CS2, -+#endif -+#if defined(MV_INCLUDE_DEVICE_CS3) -+ DEVICE_CS3, -+#endif -+#if defined(MV_INCLUDE_PEX) -+ PEX0_IO, -+#endif -+ TBL_TERM -+}; -+ -+static MV_STATUS ethWinOverlapDetect(int port, MV_U32 winNum, MV_ADDR_WIN *pAddrWin); -+static MV_STATUS mvEthWinSet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin); -+static MV_STATUS mvEthWinGet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin); -+ -+ -+/******************************************************************************* -+* mvEthWinInit - Initialize ETH address decode windows -+* -+* DESCRIPTION: -+* This function initialize ETH window decode unit. It set the -+* default address decode windows of the unit. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR if setting fail. -+*******************************************************************************/ -+/* Configure EthDrv memory map registes. */ -+MV_STATUS mvEthWinInit (int port) -+{ -+ MV_U32 winNum, status, winPrioIndex=0, i, regVal=0; -+ MV_ETH_DEC_WIN ethWin; -+ MV_CPU_DEC_WIN cpuAddrDecWin; -+ static MV_U32 accessProtReg = 0; -+ -+#if (MV_ETH_VERSION <= 1) -+ static MV_BOOL isFirst = MV_TRUE; -+ -+ if(isFirst == MV_FALSE) -+ { -+ MV_REG_WRITE(ETH_ACCESS_PROTECT_REG(port), accessProtReg); -+ return MV_OK; -+ } -+ isFirst = MV_FALSE; -+#endif /* MV_GIGA_ETH_VERSION */ -+ -+ /* Initiate Ethernet address decode */ -+ -+ /* First disable all address decode windows */ -+ for(winNum=0; winNum= ETH_MAX_DECODE_WIN) -+ { -+ mvOsPrintf("mvEthWinSet: ERR. Invalid win num %d\n",winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlapps with current windows */ -+ if (MV_TRUE == ethWinOverlapDetect(port, winNum, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("mvEthWinSet: ERR. Window %d overlap\n", winNum); -+ return MV_ERROR; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvEthWinSet: Error setting Ethernet window %d to "\ -+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, -+ mvCtrlTargetNameGet(pAddrDecWin->target), -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ -+ decRegs.baseReg = MV_REG_READ(ETH_WIN_BASE_REG(port, winNum)); -+ decRegs.sizeReg = MV_REG_READ(ETH_WIN_SIZE_REG(port, winNum)); -+ -+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) -+ { -+ mvOsPrintf("mvEthWinSet:mvCtrlAddrDecToReg Failed\n"); -+ return MV_ERROR; -+ } -+ -+ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); -+ -+ /* set attributes */ -+ decRegs.baseReg &= ~ETH_WIN_ATTR_MASK; -+ decRegs.baseReg |= targetAttribs.attrib << ETH_WIN_ATTR_OFFS; -+ /* set target ID */ -+ decRegs.baseReg &= ~ETH_WIN_TARGET_MASK; -+ decRegs.baseReg |= targetAttribs.targetId << ETH_WIN_TARGET_OFFS; -+ -+ /* for the safe side we disable the window before writing the new -+ values */ -+ mvEthWinEnable(port, winNum, MV_FALSE); -+ MV_REG_WRITE(ETH_WIN_BASE_REG(port, winNum), decRegs.baseReg); -+ -+ /* Write to address decode Size Register */ -+ MV_REG_WRITE(ETH_WIN_SIZE_REG(port, winNum), decRegs.sizeReg); -+ -+ /* Enable address decode target window */ -+ if (pAddrDecWin->enable == MV_TRUE) -+ { -+ mvEthWinEnable(port, winNum, MV_TRUE); -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvETHWinGet - Get dma peripheral target address window. -+* -+* DESCRIPTION: -+* Get ETH peripheral target address window. -+* -+* INPUT: -+* winNum - ETH to target address decode window number. -+* -+* OUTPUT: -+* pAddrDecWin - ETH target window data structure. -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvEthWinGet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin) -+{ -+ MV_DEC_REGS decRegs; -+ MV_TARGET_ATTRIB targetAttrib; -+ -+ /* Parameter checking */ -+ if (winNum >= ETH_MAX_DECODE_WIN) -+ { -+ mvOsPrintf("mvEthWinGet: ERR. Invalid winNum %d\n", winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ decRegs.baseReg = MV_REG_READ(ETH_WIN_BASE_REG(port, winNum)); -+ decRegs.sizeReg = MV_REG_READ(ETH_WIN_SIZE_REG(port, winNum)); -+ -+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) -+ { -+ mvOsPrintf("mvAhbToMbusWinGet: mvCtrlRegToAddrDec Failed \n"); -+ return MV_ERROR; -+ } -+ -+ /* attrib and targetId */ -+ targetAttrib.attrib = -+ (decRegs.baseReg & ETH_WIN_ATTR_MASK) >> ETH_WIN_ATTR_OFFS; -+ targetAttrib.targetId = -+ (decRegs.baseReg & ETH_WIN_TARGET_MASK) >> ETH_WIN_TARGET_OFFS; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ /* Check if window is enabled */ -+ if (~(MV_REG_READ(ETH_BASE_ADDR_ENABLE_REG(port))) & (1 << winNum) ) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthWinEnable - Enable/disable a ETH to target address window -+* -+* DESCRIPTION: -+* This function enable/disable a ETH to target address window. -+* According to parameter 'enable' the routine will enable the -+* window, thus enabling ETH accesses (before enabling the window it is -+* tested for overlapping). Otherwise, the window will be disabled. -+* -+* INPUT: -+* winNum - ETH to target address decode window number. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_ERROR if decode window number was wrong or enabled window overlapps. -+* -+*******************************************************************************/ -+MV_STATUS mvEthWinEnable(int port, MV_U32 winNum,MV_BOOL enable) -+{ -+ MV_ETH_DEC_WIN addrDecWin; -+ -+ /* Parameter checking */ -+ if (winNum >= ETH_MAX_DECODE_WIN) -+ { -+ mvOsPrintf("mvEthTargetWinEnable:ERR. Invalid winNum%d\n",winNum); -+ return MV_ERROR; -+ } -+ -+ if (enable == MV_TRUE) -+ { /* First check for overlap with other enabled windows */ -+ /* Get current window */ -+ if (MV_OK != mvEthWinGet(port, winNum, &addrDecWin)) -+ { -+ mvOsPrintf("mvEthTargetWinEnable:ERR. targetWinGet fail\n"); -+ return MV_ERROR; -+ } -+ /* Check for overlapping */ -+ if (MV_FALSE == ethWinOverlapDetect(port, winNum, &(addrDecWin.addrWin))) -+ { -+ /* No Overlap. Enable address decode target window */ -+ MV_REG_BIT_RESET(ETH_BASE_ADDR_ENABLE_REG(port), (1 << winNum)); -+ } -+ else -+ { /* Overlap detected */ -+ mvOsPrintf("mvEthTargetWinEnable:ERR. Overlap detected\n"); -+ return MV_ERROR; -+ } -+ } -+ else -+ { /* Disable address decode target window */ -+ MV_REG_BIT_SET(ETH_BASE_ADDR_ENABLE_REG(port), (1 << winNum)); -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthWinTargetGet - Get Window number associated with target -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+* window number -+* -+*******************************************************************************/ -+MV_U32 mvEthWinTargetGet(int port, MV_TARGET target) -+{ -+ MV_ETH_DEC_WIN decWin; -+ MV_U32 winNum; -+ -+ /* Check parameters */ -+ if (target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetGet: target %d is Illigal\n", target); -+ return 0xffffffff; -+ } -+ -+ for (winNum=0; winNum= mvCtrlEthMaxPortGet()) -+ { -+ mvOsPrintf("mvEthProtWinSet:ERR. Invalid port number %d\n", portNo); -+ return MV_ERROR; -+ } -+ -+ if (winNum >= ETH_MAX_DECODE_WIN) -+ { -+ mvOsPrintf("mvEthProtWinSet:ERR. Invalid winNum%d\n",winNum); -+ return MV_ERROR; -+ } -+ -+ if((access == ACC_RESERVED) || (access >= MAX_ACC_RIGHTS)) -+ { -+ mvOsPrintf("mvEthProtWinSet:ERR. Inv access param %d\n", access); -+ return MV_ERROR; -+ } -+ /* Read current protection register */ -+ protReg = MV_REG_READ(ETH_ACCESS_PROTECT_REG(portNo)); -+ -+ /* Clear protection window field */ -+ protReg &= ~(ETH_PROT_WIN_MASK(winNum)); -+ -+ /* Set new protection field value */ -+ protReg |= (access << (ETH_PROT_WIN_OFFS(winNum))); -+ -+ /* Write protection register back */ -+ MV_REG_WRITE(ETH_ACCESS_PROTECT_REG(portNo), protReg); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* ethWinOverlapDetect - Detect ETH address windows overlapping -+* -+* DESCRIPTION: -+* An unpredicted behaviur is expected in case ETH address decode -+* windows overlapps. -+* This function detects ETH address decode windows overlapping of a -+* specified window. The function does not check the window itself for -+* overlapping. The function also skipps disabled address decode windows. -+* -+* INPUT: -+* winNum - address decode window number. -+* pAddrDecWin - An address decode window struct. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data -+* from registers. -+* -+*******************************************************************************/ -+static MV_STATUS ethWinOverlapDetect(int port, MV_U32 winNum, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 baseAddrEnableReg; -+ MV_U32 winNumIndex; -+ MV_ETH_DEC_WIN addrDecWin; -+ -+ /* Read base address enable register. Do not check disabled windows */ -+ baseAddrEnableReg = MV_REG_READ(ETH_BASE_ADDR_ENABLE_REG(port)); -+ -+ for (winNumIndex=0; winNumIndex= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexInit: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Enabled CPU access to PCI-Express */ -+ mvCpuIfEnablePex(pexIf, pexType); -+ -+ /* Start with bars */ -+ /* First disable all PEX bars*/ -+ for (bar = 0; bar < PEX_MAX_BARS; bar++) -+ { -+ if (PEX_INTER_REGS_BAR != bar) -+ { -+ if (MV_OK != mvPexBarEnable(pexIf, bar, MV_FALSE)) -+ { -+ mvOsPrintf("mvPexInit:mvPexBarEnable bar =%d failed \n",bar); -+ return MV_ERROR; -+ } -+ -+ } -+ -+ } -+ -+ /* and disable all PEX target windows */ -+ for (winNum = 0; winNum < PEX_MAX_TARGET_WIN - 2; winNum++) -+ { -+ if (MV_OK != mvPexTargetWinEnable(pexIf, winNum, MV_FALSE)) -+ { -+ mvOsPrintf("mvPexInit:mvPexTargetWinEnable winNum =%d failed \n", -+ winNum); -+ return MV_ERROR; -+ -+ } -+ } -+ -+ /* Now, go through all bars*/ -+ -+ -+ -+/******************************************************************************/ -+/* Internal registers bar */ -+/******************************************************************************/ -+ bar = PEX_INTER_REGS_BAR; -+ -+ /* we only open the bar , no need to open windows for this bar */ -+ -+ /* first get the CS attribute from the CPU Interface */ -+ if (MV_OK !=mvCpuIfTargetWinGet(INTER_REGS,&addrDecWin)) -+ { -+ mvOsPrintf("mvPexInit: ERR. mvCpuIfTargetWinGet failed target =%d\n",INTER_REGS); -+ return MV_ERROR; -+ } -+ -+ pexBar.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; -+ pexBar.addrWin.baseLow = addrDecWin.addrWin.baseLow; -+ pexBar.addrWin.size = addrDecWin.addrWin.size; -+ pexBar.enable = MV_TRUE; -+ -+ if (MV_OK != mvPexBarSet(pexIf, bar, &pexBar)) -+ { -+ mvOsPrintf("mvPexInit: ERR. mvPexBarSet %d failed\n", bar); -+ return MV_ERROR; -+ } -+ -+/******************************************************************************/ -+/* DRAM bar */ -+/******************************************************************************/ -+ -+ bar = PEX_DRAM_BAR; -+ -+ pexBar.addrWin.size = 0; -+ -+ for (target = SDRAM_CS0;target < MV_DRAM_MAX_CS; target++ ) -+ { -+ -+ status = mvCpuIfTargetWinGet(target,&addrDecWin); -+ -+ if((MV_NO_SUCH == status)&&(target != SDRAM_CS0)) -+ { -+ continue; -+ } -+ -+ /* first get attributes from CPU If */ -+ if (MV_OK != status) -+ { -+ mvOsPrintf("mvPexInit: ERR. mvCpuIfTargetWinGet failed target =%d\n",target); -+ return MV_ERROR; -+ } -+ if (addrDecWin.enable == MV_TRUE) -+ { -+ /* the base is the base of DRAM CS0 always */ -+ if (SDRAM_CS0 == target ) -+ { -+ pexBar.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; -+ pexBar.addrWin.baseLow = addrDecWin.addrWin.baseLow; -+ -+ } -+ -+ /* increment the bar size to be the sum of the size of all -+ DRAM chips selecs */ -+ pexBar.addrWin.size += addrDecWin.addrWin.size; -+ -+ /* set a Pex window for this target ! -+ DRAM CS always will have a Pex Window , and is not a -+ part of the priority table */ -+ pexWin.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; -+ pexWin.addrWin.baseLow = addrDecWin.addrWin.baseLow; -+ pexWin.addrWin.size = addrDecWin.addrWin.size; -+ -+ /* we disable the windows at first because we are not -+ sure that it is witihin bar boundries */ -+ pexWin.enable =MV_FALSE; -+ pexWin.target = target; -+ pexWin.targetBar = bar; -+ -+ if (MV_OK != mvPexTargetWinSet(pexIf,pexCurrWin++,&pexWin)) -+ { -+ mvOsPrintf("mvPexInit: ERR. mvPexTargetWinSet failed\n"); -+ return MV_ERROR; -+ } -+ } -+ } -+ -+ /* check if the size of the bar is illeggal */ -+ if (-1 == ctrlSizeToReg(pexBar.addrWin.size, PXBCR_BAR_SIZE_ALIGNMENT)) -+ { -+ /* try to get a good size */ -+ pexBar.addrWin.size = ctrlSizeRegRoundUp(pexBar.addrWin.size, -+ PXBCR_BAR_SIZE_ALIGNMENT); -+ } -+ -+ /* check if the size and base are valid */ -+ if (MV_TRUE == pexBarOverlapDetect(pexIf,bar,&pexBar.addrWin)) -+ { -+ mvOsPrintf("mvPexInit:Warning :Bar %d size is illigal\n",bar); -+ mvOsPrintf("it will be disabled\n"); -+ mvOsPrintf("please check Pex and CPU windows configuration\n"); -+ } -+ else -+ { -+ pexBar.enable = MV_TRUE; -+ -+ /* configure the bar */ -+ if (MV_OK != mvPexBarSet(pexIf, bar, &pexBar)) -+ { -+ mvOsPrintf("mvPexInit: ERR. mvPexBarSet %d failed\n", bar); -+ return MV_ERROR; -+ } -+ -+ /* after the bar was configured then we enable the Pex windows*/ -+ for (winNum = 0;winNum < pexCurrWin ;winNum++) -+ { -+ if (MV_OK != mvPexTargetWinEnable(pexIf, winNum, MV_TRUE)) -+ { -+ mvOsPrintf("mvPexInit: Can't enable window =%d\n",winNum); -+ return MV_ERROR; -+ } -+ -+ } -+ } -+ -+/******************************************************************************/ -+/* DEVICE bar */ -+/******************************************************************************/ -+ -+/* Open the Device BAR for non linux only */ -+#ifndef MV_DISABLE_PEX_DEVICE_BAR -+ -+ /* then device bar*/ -+ bar = PEX_DEVICE_BAR; -+ -+ /* save the starting window */ -+ pexStartWindow = pexCurrWin; -+ pexBar.addrWin.size = 0; -+ pexBar.addrWin.baseLow = 0xffffffff; -+ pexBar.addrWin.baseHigh = 0; -+ maxBase = 0; -+ -+ for (target = DEV_TO_TARGET(START_DEV_CS);target < DEV_TO_TARGET(MV_DEV_MAX_CS); target++ ) -+ { -+ status = mvCpuIfTargetWinGet(target,&addrDecWin); -+ -+ if (MV_NO_SUCH == status) -+ { -+ continue; -+ } -+ -+ if (MV_OK != status) -+ { -+ mvOsPrintf("mvPexInit: ERR. mvCpuIfTargetWinGet failed target =%d\n",target); -+ return MV_ERROR; -+ } -+ -+ if (addrDecWin.enable == MV_TRUE) -+ { -+ /* get the minimum base */ -+ if (addrDecWin.addrWin.baseLow < pexBar.addrWin.baseLow) -+ { -+ pexBar.addrWin.baseLow = addrDecWin.addrWin.baseLow; -+ } -+ -+ /* get the maximum base */ -+ if (addrDecWin.addrWin.baseLow > maxBase) -+ { -+ maxBase = addrDecWin.addrWin.baseLow; -+ sizeOfMaxBase = addrDecWin.addrWin.size; -+ } -+ -+ /* search in the priority table for this target */ -+ for (winIndex = 0; pexDevBarPrioTable[winIndex] != TBL_TERM; -+ winIndex++) -+ { -+ if (pexDevBarPrioTable[winIndex] != target) -+ { -+ continue; -+ } -+ else if (pexDevBarPrioTable[winIndex] == target) -+ { -+ /*found it */ -+ -+ /* if the index of this target in the prio table is valid -+ then we set the Pex window for this target, a valid index is -+ an index that is lower than the number of the windows that -+ was not configured yet */ -+ -+ /* we subtract 2 always because the default and expantion -+ rom windows are always configured */ -+ if ( pexCurrWin < PEX_MAX_TARGET_WIN - 2) -+ { -+ /* set a Pex window for this target ! */ -+ pexWin.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; -+ pexWin.addrWin.baseLow = addrDecWin.addrWin.baseLow; -+ pexWin.addrWin.size = addrDecWin.addrWin.size; -+ -+ /* we disable the windows at first because we are not -+ sure that it is witihin bar boundries */ -+ pexWin.enable = MV_FALSE; -+ pexWin.target = target; -+ pexWin.targetBar = bar; -+ -+ if (MV_OK != mvPexTargetWinSet(pexIf,pexCurrWin++, -+ &pexWin)) -+ { -+ mvOsPrintf("mvPexInit: ERR. Window Set failed\n"); -+ return MV_ERROR; -+ } -+ } -+ } -+ } -+ } -+ } -+ -+ pexBar.addrWin.size = maxBase - pexBar.addrWin.baseLow + sizeOfMaxBase; -+ pexBar.enable = MV_TRUE; -+ -+ /* check if the size of the bar is illegal */ -+ if (-1 == ctrlSizeToReg(pexBar.addrWin.size, PXBCR_BAR_SIZE_ALIGNMENT)) -+ { -+ /* try to get a good size */ -+ pexBar.addrWin.size = ctrlSizeRegRoundUp(pexBar.addrWin.size, -+ PXBCR_BAR_SIZE_ALIGNMENT); -+ } -+ -+ /* check if the size and base are valid */ -+ if (MV_TRUE == pexBarOverlapDetect(pexIf,bar,&pexBar.addrWin)) -+ { -+ mvOsPrintf("mvPexInit:Warning :Bar %d size is illigal\n",bar); -+ mvOsPrintf("it will be disabled\n"); -+ mvOsPrintf("please check Pex and CPU windows configuration\n"); -+ } -+ else -+ { -+ if (MV_OK != mvPexBarSet(pexIf, bar, &pexBar)) -+ { -+ mvOsPrintf("mvPexInit: ERR. mvPexBarSet %d failed\n", bar); -+ return MV_ERROR; -+ } -+ -+ /* now enable the windows */ -+ for (winNum = pexStartWindow; winNum < pexCurrWin ; winNum++) -+ { -+ if (MV_OK != mvPexTargetWinEnable(pexIf, winNum, MV_TRUE)) -+ { -+ mvOsPrintf("mvPexInit:mvPexTargetWinEnable winNum =%d failed \n", -+ winNum); -+ return MV_ERROR; -+ } -+ } -+ } -+ -+#endif -+ -+ return mvPexHalInit(pexIf, pexType); -+ -+} -+ -+/******************************************************************************* -+* mvPexTargetWinSet - Set PEX to peripheral target address window BAR -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_OK if PEX BAR target window was set correctly, -+* MV_BAD_PARAM on bad params -+* MV_ERROR otherwise -+* (e.g. address window overlapps with other active PEX target window). -+* -+*******************************************************************************/ -+MV_STATUS mvPexTargetWinSet(MV_U32 pexIf, MV_U32 winNum, -+ MV_PEX_DEC_WIN *pAddrDecWin) -+{ -+ -+ MV_DEC_REGS decRegs; -+ PEX_WIN_REG_INFO winRegInfo; -+ MV_TARGET_ATTRIB targetAttribs; -+ -+ /* Parameter checking */ -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexTargetWinSet: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ -+ if (winNum >= PEX_MAX_TARGET_WIN) -+ { -+ mvOsPrintf("mvPexTargetWinSet: ERR. Invalid PEX winNum %d\n", winNum); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ /* get the pex Window registers offsets */ -+ pexWinRegInfoGet(pexIf,winNum,&winRegInfo); -+ -+ -+ if (MV_TRUE == pAddrDecWin->enable) -+ { -+ -+ /* 2) Check if the requested window overlaps with current windows */ -+ if (MV_TRUE == pexWinOverlapDetect(pexIf,winNum, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("mvPexTargetWinSet: ERR. Target %d overlap\n", winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* 2) Check if the requested window overlaps with current windows */ -+ if (MV_FALSE == pexIsWinWithinBar(pexIf,&pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("mvPexTargetWinSet: Win %d should be in bar boundries\n", -+ winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ } -+ -+ -+ -+ /* read base register*/ -+ -+ if (winRegInfo.baseLowRegOffs) -+ { -+ decRegs.baseReg = MV_REG_READ(winRegInfo.baseLowRegOffs); -+ } -+ else -+ { -+ decRegs.baseReg = 0; -+ } -+ -+ if (winRegInfo.sizeRegOffs) -+ { -+ decRegs.sizeReg = MV_REG_READ(winRegInfo.sizeRegOffs); -+ } -+ else -+ { -+ decRegs.sizeReg =0; -+ } -+ -+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) -+ { -+ mvOsPrintf("mvPexTargetWinSet:mvCtrlAddrDecToReg Failed\n"); -+ return MV_ERROR; -+ } -+ -+ /* enable\Disable */ -+ if (MV_TRUE == pAddrDecWin->enable) -+ { -+ decRegs.sizeReg |= PXWCR_WIN_EN; -+ } -+ else -+ { -+ decRegs.sizeReg &= ~PXWCR_WIN_EN; -+ } -+ -+ -+ /* clear bit location */ -+ decRegs.sizeReg &= ~PXWCR_WIN_BAR_MAP_MASK; -+ -+ /* set bar Mapping */ -+ if (pAddrDecWin->targetBar == 1) -+ { -+ decRegs.sizeReg |= PXWCR_WIN_BAR_MAP_BAR1; -+ } -+ else if (pAddrDecWin->targetBar == 2) -+ { -+ decRegs.sizeReg |= PXWCR_WIN_BAR_MAP_BAR2; -+ } -+ -+ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); -+ -+ /* set attributes */ -+ decRegs.sizeReg &= ~PXWCR_ATTRIB_MASK; -+ decRegs.sizeReg |= targetAttribs.attrib << PXWCR_ATTRIB_OFFS; -+ /* set target ID */ -+ decRegs.sizeReg &= ~PXWCR_TARGET_MASK; -+ decRegs.sizeReg |= targetAttribs.targetId << PXWCR_TARGET_OFFS; -+ -+ -+ /* 3) Write to address decode Base Address Register */ -+ -+ if (winRegInfo.baseLowRegOffs) -+ { -+ MV_REG_WRITE(winRegInfo.baseLowRegOffs, decRegs.baseReg); -+ } -+ -+ /* write size reg */ -+ if (winRegInfo.sizeRegOffs) -+ { -+ if ((MV_PEX_WIN_DEFAULT == winNum)|| -+ (MV_PEX_WIN_EXP_ROM == winNum)) -+ { -+ /* clear size because there is no size field*/ -+ decRegs.sizeReg &= ~PXWCR_SIZE_MASK; -+ -+ /* clear enable because there is no enable field*/ -+ decRegs.sizeReg &= ~PXWCR_WIN_EN; -+ -+ } -+ -+ MV_REG_WRITE(winRegInfo.sizeRegOffs, decRegs.sizeReg); -+ } -+ -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvPexTargetWinGet - Get PEX to peripheral target address window -+* -+* DESCRIPTION: -+* Get the PEX to peripheral target address window BAR. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* bar - BAR to be accessed by slave. -+* -+* OUTPUT: -+* pAddrBarWin - PEX target window information data structure. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexTargetWinGet(MV_U32 pexIf, MV_U32 winNum, -+ MV_PEX_DEC_WIN *pAddrDecWin) -+{ -+ MV_TARGET_ATTRIB targetAttrib; -+ MV_DEC_REGS decRegs; -+ -+ PEX_WIN_REG_INFO winRegInfo; -+ -+ /* Parameter checking */ -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexTargetWinGet: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ -+ if (winNum >= PEX_MAX_TARGET_WIN) -+ { -+ mvOsPrintf("mvPexTargetWinGet: ERR. Invalid PEX winNum %d\n", winNum); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ /* get the pex Window registers offsets */ -+ pexWinRegInfoGet(pexIf,winNum,&winRegInfo); -+ -+ /* read base register*/ -+ if (winRegInfo.baseLowRegOffs) -+ { -+ decRegs.baseReg = MV_REG_READ(winRegInfo.baseLowRegOffs); -+ } -+ else -+ { -+ decRegs.baseReg = 0; -+ } -+ -+ /* read size reg */ -+ if (winRegInfo.sizeRegOffs) -+ { -+ decRegs.sizeReg = MV_REG_READ(winRegInfo.sizeRegOffs); -+ } -+ else -+ { -+ decRegs.sizeReg =0; -+ } -+ -+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) -+ { -+ mvOsPrintf("mvPexTargetWinGet: mvCtrlRegToAddrDec Failed \n"); -+ return MV_ERROR; -+ -+ } -+ -+ if (decRegs.sizeReg & PXWCR_WIN_EN) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ -+ } -+ -+ -+ #if 0 -+ if (-1 == pAddrDecWin->addrWin.size) -+ { -+ return MV_ERROR; -+ } -+ #endif -+ -+ -+ /* get target bar */ -+ if ((decRegs.sizeReg & PXWCR_WIN_BAR_MAP_MASK) == PXWCR_WIN_BAR_MAP_BAR1 ) -+ { -+ pAddrDecWin->targetBar = 1; -+ } -+ else if ((decRegs.sizeReg & PXWCR_WIN_BAR_MAP_MASK) == -+ PXWCR_WIN_BAR_MAP_BAR2 ) -+ { -+ pAddrDecWin->targetBar = 2; -+ } -+ -+ /* attrib and targetId */ -+ pAddrDecWin->attrib = (decRegs.sizeReg & PXWCR_ATTRIB_MASK) >> -+ PXWCR_ATTRIB_OFFS; -+ pAddrDecWin->targetId = (decRegs.sizeReg & PXWCR_TARGET_MASK) >> -+ PXWCR_TARGET_OFFS; -+ -+ targetAttrib.attrib = pAddrDecWin->attrib; -+ targetAttrib.targetId = pAddrDecWin->targetId; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ return MV_OK; -+ -+} -+ -+ -+/******************************************************************************* -+* mvPexTargetWinEnable - Enable/disable a PEX BAR window -+* -+* DESCRIPTION: -+* This function enable/disable a PEX BAR window. -+* if parameter 'enable' == MV_TRUE the routine will enable the -+* window, thus enabling PEX accesses for that BAR (before enabling the -+* window it is tested for overlapping). Otherwise, the window will -+* be disabled. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* bar - BAR to be accessed by slave. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexTargetWinEnable(MV_U32 pexIf,MV_U32 winNum, MV_BOOL enable) -+{ -+ PEX_WIN_REG_INFO winRegInfo; -+ MV_PEX_DEC_WIN addrDecWin; -+ -+ /* Parameter checking */ -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexTargetWinEnable: ERR. Invalid PEX If %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ -+ if (winNum >= PEX_MAX_TARGET_WIN) -+ { -+ mvOsPrintf("mvPexTargetWinEnable ERR. Invalid PEX winNum %d\n", winNum); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ -+ /* get the pex Window registers offsets */ -+ pexWinRegInfoGet(pexIf,winNum,&winRegInfo); -+ -+ -+ /* if the address windows is disabled , we only disable the appropriare -+ pex window and ignore other settings */ -+ -+ if (MV_FALSE == enable) -+ { -+ -+ /* this is not relevant to default and expantion rom -+ windows */ -+ if (winRegInfo.sizeRegOffs) -+ { -+ if ((MV_PEX_WIN_DEFAULT != winNum)&& -+ (MV_PEX_WIN_EXP_ROM != winNum)) -+ { -+ MV_REG_BIT_RESET(winRegInfo.sizeRegOffs, PXWCR_WIN_EN); -+ } -+ } -+ -+ } -+ else -+ { -+ if (MV_OK != mvPexTargetWinGet(pexIf,winNum, &addrDecWin)) -+ { -+ mvOsPrintf("mvPexTargetWinEnable: mvPexTargetWinGet Failed\n"); -+ return MV_ERROR; -+ } -+ -+ /* Check if the requested window overlaps with current windows */ -+ if (MV_TRUE == pexWinOverlapDetect(pexIf,winNum, &addrDecWin.addrWin)) -+ { -+ mvOsPrintf("mvPexTargetWinEnable: ERR. Target %d overlap\n", winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ if (MV_FALSE == pexIsWinWithinBar(pexIf,&addrDecWin.addrWin)) -+ { -+ mvOsPrintf("mvPexTargetWinEnable: Win %d should be in bar boundries\n", -+ winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ -+ /* this is not relevant to default and expantion rom -+ windows */ -+ if (winRegInfo.sizeRegOffs) -+ { -+ if ((MV_PEX_WIN_DEFAULT != winNum)&& -+ (MV_PEX_WIN_EXP_ROM != winNum)) -+ { -+ MV_REG_BIT_SET(winRegInfo.sizeRegOffs, PXWCR_WIN_EN); -+ } -+ } -+ -+ -+ } -+ -+ return MV_OK; -+ -+} -+ -+ -+ -+/******************************************************************************* -+* mvPexTargetWinRemap - Set PEX to target address window remap. -+* -+* DESCRIPTION: -+* The PEX interface supports remap of the BAR original address window. -+* For each BAR it is possible to define a remap address. For example -+* an address 0x12345678 that hits BAR 0x10 (SDRAM CS[0]) will be modified -+* according to remap register but will also be targeted to the -+* SDRAM CS[0]. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* bar - Peripheral target enumerator accessed by slave. -+* pAddrWin - Address window to be checked. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexTargetWinRemap(MV_U32 pexIf, MV_U32 winNum, -+ MV_PEX_REMAP_WIN *pAddrWin) -+{ -+ -+ PEX_WIN_REG_INFO winRegInfo; -+ -+ /* Parameter checking */ -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX interface num %d\n", -+ pexIf); -+ return MV_BAD_PARAM; -+ } -+ if (MV_PEX_WIN_DEFAULT == winNum) -+ { -+ mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX win num %d\n", -+ winNum); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ if (MV_IS_NOT_ALIGN(pAddrWin->addrWin.baseLow, PXWRR_REMAP_ALIGNMENT)) -+ { -+ mvOsPrintf("mvPexTargetWinRemap: Error remap PEX interface %d win %d."\ -+ "\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ pexIf, -+ winNum, -+ pAddrWin->addrWin.baseLow, -+ pAddrWin->addrWin.size); -+ -+ return MV_ERROR; -+ } -+ -+ pexWinRegInfoGet(pexIf, winNum, &winRegInfo); -+ -+ /* Set remap low register value */ -+ MV_REG_WRITE(winRegInfo.remapLowRegOffs, pAddrWin->addrWin.baseLow); -+ -+ /* Skip base high settings if the BAR has only base low (32-bit) */ -+ if (0 != winRegInfo.remapHighRegOffs) -+ { -+ MV_REG_WRITE(winRegInfo.remapHighRegOffs, pAddrWin->addrWin.baseHigh); -+ } -+ -+ -+ if (pAddrWin->enable == MV_TRUE) -+ { -+ MV_REG_BIT_SET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvPexTargetWinRemapEnable - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+ -+MV_STATUS mvPexTargetWinRemapEnable(MV_U32 pexIf, MV_U32 winNum, -+ MV_BOOL enable) -+{ -+ PEX_WIN_REG_INFO winRegInfo; -+ -+ /* Parameter checking */ -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX interface num %d\n", -+ pexIf); -+ return MV_BAD_PARAM; -+ } -+ if (MV_PEX_WIN_DEFAULT == winNum) -+ { -+ mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX win num %d\n", -+ winNum); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ -+ pexWinRegInfoGet(pexIf, winNum, &winRegInfo); -+ -+ if (enable == MV_TRUE) -+ { -+ MV_REG_BIT_SET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); -+ } -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvPexBarSet - Set PEX bar address and size -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexBarSet(MV_U32 pexIf, -+ MV_U32 barNum, -+ MV_PEX_BAR *pAddrWin) -+{ -+ MV_U32 regBaseLow; -+ MV_U32 regSize,sizeToReg; -+ -+ -+ /* check parameters */ -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexBarSet: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ -+ if(barNum >= PEX_MAX_BARS) -+ { -+ mvOsPrintf("mvPexBarSet: ERR. Invalid bar number %d\n", barNum); -+ return MV_BAD_PARAM; -+ } -+ -+ -+ if (pAddrWin->addrWin.size == 0) -+ { -+ mvOsPrintf("mvPexBarSet: Size zero is Illigal\n" ); -+ return MV_BAD_PARAM; -+ } -+ -+ -+ /* Check if the window complies with PEX spec */ -+ if (MV_TRUE != pexBarIsValid(pAddrWin->addrWin.baseLow, -+ pAddrWin->addrWin.size)) -+ { -+ mvOsPrintf("mvPexBarSet: ERR. Target %d window invalid\n", barNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* 2) Check if the requested bar overlaps with current bars */ -+ if (MV_TRUE == pexBarOverlapDetect(pexIf,barNum, &pAddrWin->addrWin)) -+ { -+ mvOsPrintf("mvPexBarSet: ERR. Target %d overlap\n", barNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Get size register value according to window size */ -+ sizeToReg = ctrlSizeToReg(pAddrWin->addrWin.size, PXBCR_BAR_SIZE_ALIGNMENT); -+ -+ /* Read bar size */ -+ if (PEX_INTER_REGS_BAR != barNum) /* internal registers have no size */ -+ { -+ regSize = MV_REG_READ(PEX_BAR_CTRL_REG(pexIf,barNum)); -+ -+ /* Size parameter validity check. */ -+ if (-1 == sizeToReg) -+ { -+ mvOsPrintf("mvPexBarSet: ERR. Target BAR %d size invalid.\n",barNum); -+ return MV_BAD_PARAM; -+ } -+ -+ regSize &= ~PXBCR_BAR_SIZE_MASK; -+ regSize |= (sizeToReg << PXBCR_BAR_SIZE_OFFS) ; -+ -+ MV_REG_WRITE(PEX_BAR_CTRL_REG(pexIf,barNum),regSize); -+ -+ } -+ -+ /* set size */ -+ -+ -+ -+ /* Read base address low */ -+ regBaseLow = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, -+ PEX_MV_BAR_BASE(barNum))); -+ -+ /* clear current base */ -+ if (PEX_INTER_REGS_BAR == barNum) -+ { -+ regBaseLow &= ~PXBIR_BASE_MASK; -+ regBaseLow |= (pAddrWin->addrWin.baseLow & PXBIR_BASE_MASK); -+ } -+ else -+ { -+ regBaseLow &= ~PXBR_BASE_MASK; -+ regBaseLow |= (pAddrWin->addrWin.baseLow & PXBR_BASE_MASK); -+ } -+ -+ /* if we had a previous value that contain the bar type (MeM\IO), we want to -+ restore it */ -+ regBaseLow |= PEX_BAR_DEFAULT_ATTRIB; -+ -+ -+ -+ /* write base low */ -+ MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE(barNum)), -+ regBaseLow); -+ -+ if (pAddrWin->addrWin.baseHigh != 0) -+ { -+ /* Read base address high */ -+ MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE_HIGH(barNum)), -+ pAddrWin->addrWin.baseHigh); -+ -+ } -+ -+ /* lastly enable the Bar */ -+ if (pAddrWin->enable == MV_TRUE) -+ { -+ if (PEX_INTER_REGS_BAR != barNum) /* internal registers -+ are enabled always */ -+ { -+ MV_REG_BIT_SET(PEX_BAR_CTRL_REG(pexIf,barNum),PXBCR_BAR_EN); -+ } -+ } -+ else if (MV_FALSE == pAddrWin->enable) -+ { -+ if (PEX_INTER_REGS_BAR != barNum) /* internal registers -+ are enabled always */ -+ { -+ MV_REG_BIT_RESET(PEX_BAR_CTRL_REG(pexIf,barNum),PXBCR_BAR_EN); -+ } -+ -+ } -+ -+ -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPexBarGet - Get PEX bar address and size -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+ -+MV_STATUS mvPexBarGet(MV_U32 pexIf, -+ MV_U32 barNum, -+ MV_PEX_BAR *pAddrWin) -+{ -+ /* check parameters */ -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexBarGet: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ -+ if(barNum >= PEX_MAX_BARS) -+ { -+ mvOsPrintf("mvPexBarGet: ERR. Invalid bar number %d\n", barNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* read base low */ -+ pAddrWin->addrWin.baseLow = -+ MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE(barNum))); -+ -+ -+ if (PEX_INTER_REGS_BAR == barNum) -+ { -+ pAddrWin->addrWin.baseLow &= PXBIR_BASE_MASK; -+ } -+ else -+ { -+ pAddrWin->addrWin.baseLow &= PXBR_BASE_MASK; -+ } -+ -+ -+ /* read base high */ -+ pAddrWin->addrWin.baseHigh = -+ MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE_HIGH(barNum))); -+ -+ -+ /* Read bar size */ -+ if (PEX_INTER_REGS_BAR != barNum) /* internal registers have no size */ -+ { -+ pAddrWin->addrWin.size = MV_REG_READ(PEX_BAR_CTRL_REG(pexIf,barNum)); -+ -+ /* check if enable or not */ -+ if (pAddrWin->addrWin.size & PXBCR_BAR_EN) -+ { -+ pAddrWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrWin->enable = MV_FALSE; -+ } -+ -+ /* now get the size */ -+ pAddrWin->addrWin.size &= PXBCR_BAR_SIZE_MASK; -+ pAddrWin->addrWin.size >>= PXBCR_BAR_SIZE_OFFS; -+ -+ pAddrWin->addrWin.size = ctrlRegToSize(pAddrWin->addrWin.size, -+ PXBCR_BAR_SIZE_ALIGNMENT); -+ -+ } -+ else /* PEX_INTER_REGS_BAR */ -+ { -+ pAddrWin->addrWin.size = INTER_REGS_SIZE; -+ pAddrWin->enable = MV_TRUE; -+ } -+ -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvPexBarEnable - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+ -+ -+MV_STATUS mvPexBarEnable(MV_U32 pexIf, MV_U32 barNum, MV_BOOL enable) -+{ -+ -+ MV_PEX_BAR pexBar; -+ -+ /* check parameters */ -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexBarEnable: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ -+ -+ if(barNum >= PEX_MAX_BARS) -+ { -+ mvOsPrintf("mvPexBarEnable: ERR. Invalid bar number %d\n", barNum); -+ return MV_BAD_PARAM; -+ } -+ -+ if (PEX_INTER_REGS_BAR == barNum) -+ { -+ if (MV_TRUE == enable) -+ { -+ return MV_OK; -+ } -+ else -+ { -+ return MV_ERROR; -+ } -+ } -+ -+ -+ if (MV_FALSE == enable) -+ { -+ /* disable bar and quit */ -+ MV_REG_BIT_RESET(PEX_BAR_CTRL_REG(pexIf,barNum),PXBCR_BAR_EN); -+ return MV_OK; -+ } -+ -+ /* else */ -+ -+ if (mvPexBarGet(pexIf,barNum,&pexBar) != MV_OK) -+ { -+ mvOsPrintf("mvPexBarEnable: mvPexBarGet Failed\n"); -+ return MV_ERROR; -+ -+ } -+ -+ if (MV_TRUE == pexBar.enable) -+ { -+ /* it is already enabled !!! */ -+ return MV_OK; -+ } -+ -+ /* else enable the bar*/ -+ -+ pexBar.enable = MV_TRUE; -+ -+ if (mvPexBarSet(pexIf,barNum,&pexBar) != MV_OK) -+ { -+ mvOsPrintf("mvPexBarEnable: mvPexBarSet Failed\n"); -+ return MV_ERROR; -+ -+ } -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* pexWinOverlapDetect - Detect address windows overlapping -+* -+* DESCRIPTION: -+* This function detects address window overlapping of a given address -+* window in PEX BARs. -+* -+* INPUT: -+* pAddrWin - Address window to be checked. -+* bar - BAR to be accessed by slave. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+static MV_BOOL pexWinOverlapDetect(MV_U32 pexIf, -+ MV_U32 winNum, -+ MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 win; -+ MV_PEX_DEC_WIN addrDecWin; -+ -+ -+ for(win = 0; win < PEX_MAX_TARGET_WIN -2 ; win++) -+ { -+ /* don't check our target or illegal targets */ -+ if (winNum == win) -+ { -+ continue; -+ } -+ -+ /* Get window parameters */ -+ if (MV_OK != mvPexTargetWinGet(pexIf, win, &addrDecWin)) -+ { -+ mvOsPrintf("pexWinOverlapDetect: ERR. TargetWinGet failed win=%x\n", -+ win); -+ return MV_ERROR; -+ } -+ -+ /* Do not check disabled windows */ -+ if (MV_FALSE == addrDecWin.enable) -+ { -+ continue; -+ } -+ -+ -+ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) -+ { -+ mvOsPrintf("pexWinOverlapDetect: winNum %d overlap current %d\n", -+ winNum, win); -+ return MV_TRUE; -+ } -+ } -+ -+ return MV_FALSE; -+} -+ -+/******************************************************************************* -+* pexIsWinWithinBar - Detect if address is within PEX bar boundries -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+static MV_BOOL pexIsWinWithinBar(MV_U32 pexIf, -+ MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 bar; -+ MV_PEX_BAR addrDecWin; -+ -+ for(bar = 0; bar < PEX_MAX_BARS; bar++) -+ { -+ -+ /* Get window parameters */ -+ if (MV_OK != mvPexBarGet(pexIf, bar, &addrDecWin)) -+ { -+ mvOsPrintf("pexIsWinWithinBar: ERR. mvPexBarGet failed\n"); -+ return MV_ERROR; -+ } -+ -+ /* Do not check disabled bars */ -+ if (MV_FALSE == addrDecWin.enable) -+ { -+ continue; -+ } -+ -+ -+ if(MV_TRUE == ctrlWinWithinWinTest(pAddrWin, &addrDecWin.addrWin)) -+ { -+ return MV_TRUE; -+ } -+ } -+ -+ return MV_FALSE; -+ -+} -+ -+/******************************************************************************* -+* pexBarOverlapDetect - Detect address windows overlapping -+* -+* DESCRIPTION: -+* This function detects address window overlapping of a given address -+* window in PEX BARs. -+* -+* INPUT: -+* pAddrWin - Address window to be checked. -+* bar - BAR to be accessed by slave. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+static MV_BOOL pexBarOverlapDetect(MV_U32 pexIf, -+ MV_U32 barNum, -+ MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 bar; -+ MV_PEX_BAR barDecWin; -+ -+ -+ for(bar = 0; bar < PEX_MAX_BARS; bar++) -+ { -+ /* don't check our target or illegal targets */ -+ if (barNum == bar) -+ { -+ continue; -+ } -+ -+ /* Get window parameters */ -+ if (MV_OK != mvPexBarGet(pexIf, bar, &barDecWin)) -+ { -+ mvOsPrintf("pexBarOverlapDetect: ERR. TargetWinGet failed\n"); -+ return MV_ERROR; -+ } -+ -+ /* don'nt check disabled bars */ -+ if (barDecWin.enable == MV_FALSE) -+ { -+ continue; -+ } -+ -+ -+ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &barDecWin.addrWin)) -+ { -+ mvOsPrintf("pexBarOverlapDetect: winNum %d overlap current %d\n", -+ barNum, bar); -+ return MV_TRUE; -+ } -+ } -+ -+ return MV_FALSE; -+} -+ -+/******************************************************************************* -+* pexBarIsValid - Check if the given address window is valid -+* -+* DESCRIPTION: -+* PEX spec restrict BAR base to be aligned to BAR size. -+* This function checks if the given address window is valid. -+* -+* INPUT: -+* baseLow - 32bit low base address. -+* size - Window size. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the address window is valid, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+static MV_STATUS pexBarIsValid(MV_U32 baseLow, MV_U32 size) -+{ -+ -+ /* PCI spec restrict BAR base to be aligned to BAR size */ -+ if(MV_IS_NOT_ALIGN(baseLow, size)) -+ { -+ return MV_ERROR; -+ } -+ else -+ { -+ return MV_TRUE; -+ } -+ -+ return MV_TRUE; -+} -+ -+/******************************************************************************* -+* pexBarRegInfoGet - Get BAR register information -+* -+* DESCRIPTION: -+* PEX BARs registers offsets are inconsecutive. -+* This function gets a PEX BAR register information like register offsets -+* and function location of the BAR. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* bar - The PEX BAR in question. -+* -+* OUTPUT: -+* pBarRegInfo - BAR register info struct. -+* -+* RETURN: -+* MV_BAD_PARAM when bad parameters ,MV_ERROR on error ,othewise MV_OK -+* -+*******************************************************************************/ -+static MV_STATUS pexWinRegInfoGet(MV_U32 pexIf, -+ MV_U32 winNum, -+ PEX_WIN_REG_INFO *pWinRegInfo) -+{ -+ -+ if ((winNum >= 0)&&(winNum <=3)) -+ { -+ pWinRegInfo->baseLowRegOffs = PEX_WIN0_3_BASE_REG(pexIf,winNum); -+ pWinRegInfo->baseHighRegOffs = 0; -+ pWinRegInfo->sizeRegOffs = PEX_WIN0_3_CTRL_REG(pexIf,winNum); -+ pWinRegInfo->remapLowRegOffs = PEX_WIN0_3_REMAP_REG(pexIf,winNum); -+ pWinRegInfo->remapHighRegOffs = 0; -+ } -+ else if ((winNum >= 4)&&(winNum <=5)) -+ { -+ pWinRegInfo->baseLowRegOffs = PEX_WIN4_5_BASE_REG(pexIf,winNum); -+ pWinRegInfo->baseHighRegOffs = 0; -+ pWinRegInfo->sizeRegOffs = PEX_WIN4_5_CTRL_REG(pexIf,winNum); -+ pWinRegInfo->remapLowRegOffs = PEX_WIN4_5_REMAP_REG(pexIf,winNum); -+ pWinRegInfo->remapHighRegOffs = PEX_WIN4_5_REMAP_HIGH_REG(pexIf,winNum); -+ -+ } -+ else if (MV_PEX_WIN_DEFAULT == winNum) -+ { -+ pWinRegInfo->baseLowRegOffs = 0; -+ pWinRegInfo->baseHighRegOffs = 0; -+ pWinRegInfo->sizeRegOffs = PEX_WIN_DEFAULT_CTRL_REG(pexIf); -+ pWinRegInfo->remapLowRegOffs = 0; -+ pWinRegInfo->remapHighRegOffs = 0; -+ } -+ else if (MV_PEX_WIN_EXP_ROM == winNum) -+ { -+ pWinRegInfo->baseLowRegOffs = 0; -+ pWinRegInfo->baseHighRegOffs = 0; -+ pWinRegInfo->sizeRegOffs = PEX_WIN_EXP_ROM_CTRL_REG(pexIf); -+ pWinRegInfo->remapLowRegOffs = PEX_WIN_EXP_ROM_REMAP_REG(pexIf); -+ pWinRegInfo->remapHighRegOffs = 0; -+ -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* pexBarNameGet - Get the string name of PEX BAR. -+* -+* DESCRIPTION: -+* This function get the string name of PEX BAR. -+* -+* INPUT: -+* bar - PEX bar number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* pointer to the string name of PEX BAR. -+* -+*******************************************************************************/ -+const MV_8* pexBarNameGet( MV_U32 bar ) -+{ -+ switch( bar ) -+ { -+ case PEX_INTER_REGS_BAR: -+ return "Internal Regs Bar0...."; -+ case PEX_DRAM_BAR: -+ return "DRAM Bar1............."; -+ case PEX_DEVICE_BAR: -+ return "Devices Bar2.........."; -+ default: -+ return "Bar unknown"; -+ } -+} -+/******************************************************************************* -+* mvPexAddrDecShow - Print the PEX address decode map (BARs and windows). -+* -+* DESCRIPTION: -+* This function print the PEX address decode map (BARs and windows). -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvPexAddrDecShow(MV_VOID) -+{ -+ MV_PEX_BAR pexBar; -+ MV_PEX_DEC_WIN win; -+ MV_U32 pexIf; -+ MV_U32 bar,winNum; -+ -+ for( pexIf = 0; pexIf < mvCtrlPexMaxIfGet(); pexIf++ ) -+ { -+ if (MV_FALSE == mvCtrlPwrClckGet(PEX_UNIT_ID, pexIf)) continue; -+ mvOsOutput( "\n" ); -+ mvOsOutput( "PEX%d:\n", pexIf ); -+ mvOsOutput( "-----\n" ); -+ -+ mvOsOutput( "\nPex Bars \n\n"); -+ -+ for( bar = 0; bar < PEX_MAX_BARS; bar++ ) -+ { -+ memset( &pexBar, 0, sizeof(MV_PEX_BAR) ); -+ -+ mvOsOutput( "%s ", pexBarNameGet(bar) ); -+ -+ if( mvPexBarGet( pexIf, bar, &pexBar ) == MV_OK ) -+ { -+ if( pexBar.enable ) -+ { -+ mvOsOutput( "base %08x, ", pexBar.addrWin.baseLow ); -+ mvSizePrint( pexBar.addrWin.size ); -+ mvOsOutput( "\n" ); -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ } -+ } -+ mvOsOutput( "\nPex Decode Windows\n\n"); -+ -+ for( winNum = 0; winNum < PEX_MAX_TARGET_WIN - 2; winNum++) -+ { -+ memset( &win, 0,sizeof(MV_PEX_DEC_WIN) ); -+ -+ mvOsOutput( "win%d - ", winNum ); -+ -+ if ( mvPexTargetWinGet(pexIf,winNum,&win) == MV_OK) -+ { -+ if (win.enable) -+ { -+ mvOsOutput( "%s base %08x, ", -+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); -+ mvOsOutput( "...." ); -+ mvSizePrint( win.addrWin.size ); -+ -+ mvOsOutput( "\n" ); -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ -+ -+ } -+ } -+ -+ memset( &win, 0,sizeof(MV_PEX_DEC_WIN) ); -+ -+ mvOsOutput( "default win - " ); -+ -+ if ( mvPexTargetWinGet(pexIf, MV_PEX_WIN_DEFAULT, &win) == MV_OK) -+ { -+ mvOsOutput( "%s ", -+ mvCtrlTargetNameGet(win.target) ); -+ mvOsOutput( "\n" ); -+ } -+ memset( &win, 0,sizeof(MV_PEX_DEC_WIN) ); -+ -+ mvOsOutput( "Expansion ROM - " ); -+ -+ if ( mvPexTargetWinGet(pexIf, MV_PEX_WIN_EXP_ROM, &win) == MV_OK) -+ { -+ mvOsOutput( "%s ", -+ mvCtrlTargetNameGet(win.target) ); -+ mvOsOutput( "\n" ); -+ } -+ -+ } -+} -+ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.h 2010-11-09 20:28:08.372495456 +0100 -@@ -0,0 +1,348 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCSysPEXH -+#define __INCSysPEXH -+ -+#include "mvCommon.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+ -+/* 4KB granularity */ -+#define MINIMUM_WINDOW_SIZE 0x1000 -+#define MINIMUM_BAR_SIZE 0x1000 -+#define MINIMUM_BAR_SIZE_MASK 0xFFFFF000 -+#define BAR_SIZE_OFFS 12 -+#define BAR_SIZE_MASK (0xFFFFF << BAR_SIZE_OFFS) -+ -+ -+ -+#define MV_PEX_WIN_DEFAULT 6 -+#define MV_PEX_WIN_EXP_ROM 7 -+#define PEX_MAX_TARGET_WIN 8 -+ -+ -+#define PEX_MAX_BARS 3 -+#define PEX_INTER_REGS_BAR 0 -+#define PEX_DRAM_BAR 1 -+#define PEX_DEVICE_BAR 2 -+ -+/*************************************/ -+/* PCI Express BAR Control Registers */ -+/*************************************/ -+#define PEX_BAR_CTRL_REG(pexIf,bar) (0x41804 + (bar-1)*4- (pexIf)*0x10000) -+#define PEX_EXP_ROM_BAR_CTRL_REG(pexIf) (0x4180C - (pexIf)*0x10000) -+ -+ -+/* PCI Express BAR Control Register */ -+/* PEX_BAR_CTRL_REG (PXBCR) */ -+ -+#define PXBCR_BAR_EN BIT0 -+#define PXBCR_BAR_SIZE_OFFS 16 -+#define PXBCR_BAR_SIZE_MASK (0xffff << PXBCR_BAR_SIZE_OFFS) -+#define PXBCR_BAR_SIZE_ALIGNMENT 0x10000 -+ -+ -+ -+/* PCI Express Expansion ROM BAR Control Register */ -+/* PEX_EXP_ROM_BAR_CTRL_REG (PXERBCR) */ -+ -+#define PXERBCR_EXPROM_EN BIT0 -+#define PXERBCR_EXPROMSZ_OFFS 19 -+#define PXERBCR_EXPROMSZ_MASK (0xf << PXERBCR_EXPROMSZ_OFFS) -+#define PXERBCR_EXPROMSZ_512KB (0x0 << PXERBCR_EXPROMSZ_OFFS) -+#define PXERBCR_EXPROMSZ_1024KB (0x1 << PXERBCR_EXPROMSZ_OFFS) -+#define PXERBCR_EXPROMSZ_2048KB (0x3 << PXERBCR_EXPROMSZ_OFFS) -+#define PXERBCR_EXPROMSZ_4096KB (0x7 << PXERBCR_EXPROMSZ_OFFS) -+ -+/************************************************/ -+/* PCI Express Address Window Control Registers */ -+/************************************************/ -+#define PEX_WIN0_3_CTRL_REG(pexIf,winNum) \ -+ (0x41820 + (winNum) * 0x10 - (pexIf) * 0x10000) -+#define PEX_WIN0_3_BASE_REG(pexIf,winNum) \ -+ (0x41824 + (winNum) * 0x10 - (pexIf) * 0x10000) -+#define PEX_WIN0_3_REMAP_REG(pexIf,winNum) \ -+ (0x4182C + (winNum) * 0x10 - (pexIf) * 0x10000) -+#define PEX_WIN4_5_CTRL_REG(pexIf,winNum) \ -+ (0x41860 + (winNum - 4) * 0x20 - (pexIf) * 0x10000) -+#define PEX_WIN4_5_BASE_REG(pexIf,winNum) \ -+ (0x41864 + (winNum - 4) * 0x20 - (pexIf) * 0x10000) -+#define PEX_WIN4_5_REMAP_REG(pexIf,winNum) \ -+ (0x4186C + (winNum - 4) * 0x20 - (pexIf) * 0x10000) -+#define PEX_WIN4_5_REMAP_HIGH_REG(pexIf,winNum) \ -+ (0x41870 + (winNum - 4) * 0x20 - (pexIf) * 0x10000) -+ -+#define PEX_WIN_DEFAULT_CTRL_REG(pexIf) (0x418B0 - (pexIf) * 0x10000) -+#define PEX_WIN_EXP_ROM_CTRL_REG(pexIf) (0x418C0 - (pexIf) * 0x10000) -+#define PEX_WIN_EXP_ROM_REMAP_REG(pexIf) (0x418C4 - (pexIf) * 0x10000) -+ -+/* PCI Express Window Control Register */ -+/* PEX_WIN_CTRL_REG (PXWCR) */ -+ -+#define PXWCR_WIN_EN BIT0 /* Window Enable.*/ -+ -+#define PXWCR_WIN_BAR_MAP_OFFS 1 /* Mapping to BAR.*/ -+#define PXWCR_WIN_BAR_MAP_MASK BIT1 -+#define PXWCR_WIN_BAR_MAP_BAR1 (0 << PXWCR_WIN_BAR_MAP_OFFS) -+#define PXWCR_WIN_BAR_MAP_BAR2 (1 << PXWCR_WIN_BAR_MAP_OFFS) -+ -+#define PXWCR_TARGET_OFFS 4 /*Unit ID */ -+#define PXWCR_TARGET_MASK (0xf << PXWCR_TARGET_OFFS) -+ -+#define PXWCR_ATTRIB_OFFS 8 /* target attributes */ -+#define PXWCR_ATTRIB_MASK (0xff << PXWCR_ATTRIB_OFFS) -+ -+#define PXWCR_SIZE_OFFS 16 /* size */ -+#define PXWCR_SIZE_MASK (0xffff << PXWCR_SIZE_OFFS) -+#define PXWCR_SIZE_ALIGNMENT 0x10000 -+ -+/* PCI Express Window Base Register */ -+/* PEX_WIN_BASE_REG (PXWBR)*/ -+ -+#define PXWBR_BASE_OFFS 16 /* address[31:16] */ -+#define PXWBR_BASE_MASK (0xffff << PXWBR_BASE_OFFS) -+#define PXWBR_BASE_ALIGNMENT 0x10000 -+ -+/* PCI Express Window Remap Register */ -+/* PEX_WIN_REMAP_REG (PXWRR)*/ -+ -+#define PXWRR_REMAP_EN BIT0 -+#define PXWRR_REMAP_OFFS 16 -+#define PXWRR_REMAP_MASK (0xffff << PXWRR_REMAP_OFFS) -+#define PXWRR_REMAP_ALIGNMENT 0x10000 -+ -+/* PCI Express Window Remap (High) Register */ -+/* PEX_WIN_REMAP_HIGH_REG (PXWRHR)*/ -+ -+#define PXWRHR_REMAP_HIGH_OFFS 0 -+#define PXWRHR_REMAP_HIGH_MASK (0xffffffff << PXWRHR_REMAP_HIGH_OFFS) -+ -+/* PCI Express Default Window Control Register */ -+/* PEX_WIN_DEFAULT_CTRL_REG (PXWDCR) */ -+ -+#define PXWDCR_TARGET_OFFS 4 /*Unit ID */ -+#define PXWDCR_TARGET_MASK (0xf << PXWDCR_TARGET_OFFS) -+#define PXWDCR_ATTRIB_OFFS 8 /* target attributes */ -+#define PXWDCR_ATTRIB_MASK (0xff << PXWDCR_ATTRIB_OFFS) -+ -+/* PCI Express Expansion ROM Window Control Register */ -+/* PEX_WIN_EXP_ROM_CTRL_REG (PXWERCR)*/ -+ -+#define PXWERCR_TARGET_OFFS 4 /*Unit ID */ -+#define PXWERCR_TARGET_MASK (0xf << PXWERCR_TARGET_OFFS) -+#define PXWERCR_ATTRIB_OFFS 8 /* target attributes */ -+#define PXWERCR_ATTRIB_MASK (0xff << PXWERCR_ATTRIB_OFFS) -+ -+/* PCI Express Expansion ROM Window Remap Register */ -+/* PEX_WIN_EXP_ROM_REMAP_REG (PXWERRR)*/ -+ -+#define PXWERRR_REMAP_EN BIT0 -+#define PXWERRR_REMAP_OFFS 16 -+#define PXWERRR_REMAP_MASK (0xffff << PXWERRR_REMAP_OFFS) -+#define PXWERRR_REMAP_ALIGNMENT 0x10000 -+ -+ -+ -+/*PEX_MEMORY_BAR_BASE_ADDR(barNum) (PXMBBA)*/ -+/* PCI Express BAR0 Internal Register*/ -+/*PEX BAR0_INTER_REG (PXBIR)*/ -+ -+#define PXBIR_IOSPACE BIT0 /* Memory Space Indicator */ -+ -+#define PXBIR_TYPE_OFFS 1 /* BAR Type/Init Val. */ -+#define PXBIR_TYPE_MASK (0x3 << PXBIR_TYPE_OFFS) -+#define PXBIR_TYPE_32BIT_ADDR (0x0 << PXBIR_TYPE_OFFS) -+#define PXBIR_TYPE_64BIT_ADDR (0x2 << PXBIR_TYPE_OFFS) -+ -+#define PXBIR_PREFETCH_EN BIT3 /* Prefetch Enable */ -+ -+#define PXBIR_BASE_OFFS 20 /* Base address. Address bits [31:20] */ -+#define PXBIR_BASE_MASK (0xfff << PXBIR_BASE_OFFS) -+#define PXBIR_BASE_ALIGNMET (1 << PXBIR_BASE_OFFS) -+ -+ -+/* PCI Express BAR0 Internal (High) Register*/ -+/*PEX BAR0_INTER_REG_HIGH (PXBIRH)*/ -+ -+#define PXBIRH_BASE_OFFS 0 /* Base address. Bits [63:32] */ -+#define PXBIRH_BASE_MASK (0xffffffff << PBBHR_BASE_OFFS) -+ -+ -+#define PEX_BAR_DEFAULT_ATTRIB 0xc /* Memory - Prefetch - 64 bit address */ -+#define PEX_BAR0_DEFAULT_ATTRIB PEX_BAR_DEFAULT_ATTRIB -+#define PEX_BAR1_DEFAULT_ATTRIB PEX_BAR_DEFAULT_ATTRIB -+#define PEX_BAR2_DEFAULT_ATTRIB PEX_BAR_DEFAULT_ATTRIB -+ -+ -+/* PCI Express BAR1 Register */ -+/* PCI Express BAR2 Register*/ -+/*PEX BAR1_REG (PXBR)*/ -+/*PEX BAR2_REG (PXBR)*/ -+ -+#define PXBR_IOSPACE BIT0 /* Memory Space Indicator */ -+ -+#define PXBR_TYPE_OFFS 1 /* BAR Type/Init Val. */ -+#define PXBR_TYPE_MASK (0x3 << PXBR_TYPE_OFFS) -+#define PXBR_TYPE_32BIT_ADDR (0x0 << PXBR_TYPE_OFFS) -+#define PXBR_TYPE_64BIT_ADDR (0x2 << PXBR_TYPE_OFFS) -+ -+#define PXBR_PREFETCH_EN BIT3 /* Prefetch Enable */ -+ -+#define PXBR_BASE_OFFS 16 /* Base address. Address bits [31:16] */ -+#define PXBR_BASE_MASK (0xffff << PXBR_BASE_OFFS) -+#define PXBR_BASE_ALIGNMET (1 << PXBR_BASE_OFFS) -+ -+ -+/* PCI Express BAR1 (High) Register*/ -+/* PCI Express BAR2 (High) Register*/ -+/*PEX BAR1_REG_HIGH (PXBRH)*/ -+/*PEX BAR2_REG_HIGH (PXBRH)*/ -+ -+#define PXBRH_BASE_OFFS 0 /* Base address. Address bits [63:32] */ -+#define PXBRH_BASE_MASK (0xffffffff << PXBRH_BASE_OFFS) -+ -+/* PCI Express Expansion ROM BAR Register*/ -+/*PEX_EXPANSION_ROM_BASE_ADDR_REG (PXERBAR)*/ -+ -+#define PXERBAR_EXPROMEN BIT0 /* Expansion ROM Enable */ -+ -+#define PXERBAR_BASE_512K_OFFS 19 /* Expansion ROM Base Address */ -+#define PXERBAR_BASE_512K_MASK (0x1fff << PXERBAR_BASE_512K_OFFS) -+ -+#define PXERBAR_BASE_1MB_OFFS 20 /* Expansion ROM Base Address */ -+#define PXERBAR_BASE_1MB_MASK (0xfff << PXERBAR_BASE_1MB_OFFS) -+ -+#define PXERBAR_BASE_2MB_OFFS 21 /* Expansion ROM Base Address */ -+#define PXERBAR_BASE_2MB_MASK (0x7ff << PXERBAR_BASE_2MB_OFFS) -+ -+#define PXERBAR_BASE_4MB_OFFS 22 /* Expansion ROM Base Address */ -+#define PXERBAR_BASE_4MB_MASK (0x3ff << PXERBAR_BASE_4MB_OFFS) -+ -+/* PEX Bar attributes */ -+typedef struct _mvPexBar -+{ -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+}MV_PEX_BAR; -+ -+/* PEX Remap Window attributes */ -+typedef struct _mvPexRemapWin -+{ -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+}MV_PEX_REMAP_WIN; -+ -+/* PEX Remap Window attributes */ -+typedef struct _mvPexDecWin -+{ -+ MV_TARGET target; -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_U32 targetBar; -+ MV_U8 attrib; /* chip select attributes */ -+ MV_TARGET_ID targetId; /* Target Id of this MV_TARGET */ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+}MV_PEX_DEC_WIN; -+ -+/* Global Functions prototypes */ -+/* mvPexHalInit - Initialize PEX interfaces*/ -+MV_STATUS mvPexInit(MV_U32 pexIf, MV_PEX_TYPE pexType); -+ -+ -+/* mvPexTargetWinSet - Set PEX to peripheral target address window BAR*/ -+MV_STATUS mvPexTargetWinSet(MV_U32 pexIf, MV_U32 winNum, -+ MV_PEX_DEC_WIN *pAddrDecWin); -+ -+/* mvPexTargetWinGet - Get PEX to peripheral target address window*/ -+MV_STATUS mvPexTargetWinGet(MV_U32 pexIf, MV_U32 winNum, -+ MV_PEX_DEC_WIN *pAddrDecWin); -+ -+/* mvPexTargetWinEnable - Enable/disable a PEX BAR window*/ -+MV_STATUS mvPexTargetWinEnable(MV_U32 pexIf,MV_U32 winNum, MV_BOOL enable); -+ -+/* mvPexTargetWinRemap - Set PEX to target address window remap.*/ -+MV_STATUS mvPexTargetWinRemap(MV_U32 pexIf, MV_U32 winNum, -+ MV_PEX_REMAP_WIN *pAddrWin); -+ -+/* mvPexTargetWinRemapEnable -enable\disable a PEX Window remap.*/ -+MV_STATUS mvPexTargetWinRemapEnable(MV_U32 pexIf, MV_U32 winNum, -+ MV_BOOL enable); -+ -+/* mvPexBarSet - Set PEX bar address and size */ -+MV_STATUS mvPexBarSet(MV_U32 pexIf, MV_U32 barNum, MV_PEX_BAR *addrWin); -+ -+/* mvPexBarGet - Get PEX bar address and size */ -+MV_STATUS mvPexBarGet(MV_U32 pexIf, MV_U32 barNum, MV_PEX_BAR *addrWin); -+ -+/* mvPexBarEnable - enable\disable a PEX bar*/ -+MV_STATUS mvPexBarEnable(MV_U32 pexIf, MV_U32 barNum, MV_BOOL enable); -+ -+/* mvPexAddrDecShow - Display address decode windows attributes */ -+MV_VOID mvPexAddrDecShow(MV_VOID); -+ -+#endif -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.c 2010-11-09 20:28:08.402495399 +0100 -@@ -0,0 +1,430 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#include "mvTypes.h" -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "cpu/mvCpu.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+#include "sata/CoreDriver/mvRegs.h" -+#include "ctrlEnv/sys/mvSysSata.h" -+ -+MV_TARGET sataAddrDecPrioTab[] = -+{ -+#if defined(MV_INCLUDE_SDRAM_CS0) -+ SDRAM_CS0, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS1) -+ SDRAM_CS1, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS2) -+ SDRAM_CS2, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS3) -+ SDRAM_CS3, -+#endif -+#if defined(MV_INCLUDE_PEX) -+ PEX0_MEM, -+#endif -+ TBL_TERM -+}; -+ -+ -+/******************************************************************************* -+* sataWinOverlapDetect - Detect SATA address windows overlapping -+* -+* DESCRIPTION: -+* An unpredicted behaviur is expected in case SATA address decode -+* windows overlapps. -+* This function detects SATA address decode windows overlapping of a -+* specified window. The function does not check the window itself for -+* overlapping. The function also skipps disabled address decode windows. -+* -+* INPUT: -+* winNum - address decode window number. -+* pAddrDecWin - An address decode window struct. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data -+* from registers. -+* -+*******************************************************************************/ -+static MV_STATUS sataWinOverlapDetect(int dev, MV_U32 winNum, -+ MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 winNumIndex; -+ MV_SATA_DEC_WIN addrDecWin; -+ -+ for(winNumIndex=0; winNumIndex= MV_SATA_MAX_ADDR_DECODE_WIN) -+ { -+ mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlapps with current windows */ -+ if (MV_TRUE == sataWinOverlapDetect(dev, winNum, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); -+ return MV_ERROR; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvSataWinSet:Error setting SATA window %d to "\ -+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, -+ mvCtrlTargetNameGet(pAddrDecWin->target), -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ decRegs.baseReg = 0; -+ decRegs.sizeReg = 0; -+ -+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) -+ { -+ mvOsPrintf("%s: mvCtrlAddrDecToReg Failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); -+ -+ /* set attributes */ -+ decRegs.sizeReg &= ~MV_SATA_WIN_ATTR_MASK; -+ decRegs.sizeReg |= (targetAttribs.attrib << MV_SATA_WIN_ATTR_OFFSET); -+ -+ /* set target ID */ -+ decRegs.sizeReg &= ~MV_SATA_WIN_TARGET_MASK; -+ decRegs.sizeReg |= (targetAttribs.targetId << MV_SATA_WIN_TARGET_OFFSET); -+ -+ if (pAddrDecWin->enable == MV_TRUE) -+ { -+ decRegs.sizeReg |= MV_SATA_WIN_ENABLE_MASK; -+ } -+ else -+ { -+ decRegs.sizeReg &= ~MV_SATA_WIN_ENABLE_MASK; -+ } -+ -+ MV_REG_WRITE( MV_SATA_WIN_CTRL_REG(dev, winNum), decRegs.sizeReg); -+ MV_REG_WRITE( MV_SATA_WIN_BASE_REG(dev, winNum), decRegs.baseReg); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSataWinGet - Get SATA peripheral target address window. -+* -+* DESCRIPTION: -+* Get SATA peripheral target address window. -+* -+* INPUT: -+* winNum - SATA target address decode window number. -+* -+* OUTPUT: -+* pAddrDecWin - SATA target window data structure. -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvSataWinGet(int dev, MV_U32 winNum, MV_SATA_DEC_WIN *pAddrDecWin) -+{ -+ MV_DEC_REGS decRegs; -+ MV_TARGET_ATTRIB targetAttrib; -+ -+ /* Parameter checking */ -+ if (winNum >= MV_SATA_MAX_ADDR_DECODE_WIN) -+ { -+ mvOsPrintf("%s (dev=%d): ERR. Invalid winNum %d\n", -+ __FUNCTION__, dev, winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ decRegs.baseReg = MV_REG_READ( MV_SATA_WIN_BASE_REG(dev, winNum) ); -+ decRegs.sizeReg = MV_REG_READ( MV_SATA_WIN_CTRL_REG(dev, winNum) ); -+ -+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs, &pAddrDecWin->addrWin) ) -+ { -+ mvOsPrintf("%s: mvCtrlRegToAddrDec Failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ /* attrib and targetId */ -+ targetAttrib.attrib = (decRegs.sizeReg & MV_SATA_WIN_ATTR_MASK) >> -+ MV_SATA_WIN_ATTR_OFFSET; -+ targetAttrib.targetId = (decRegs.sizeReg & MV_SATA_WIN_TARGET_MASK) >> -+ MV_SATA_WIN_TARGET_OFFSET; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ /* Check if window is enabled */ -+ if(decRegs.sizeReg & MV_SATA_WIN_ENABLE_MASK) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ } -+ return MV_OK; -+} -+/******************************************************************************* -+* mvSataAddrDecShow - Print the SATA address decode map. -+* -+* DESCRIPTION: -+* This function print the SATA address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvSataAddrDecShow(MV_VOID) -+{ -+ -+ MV_SATA_DEC_WIN win; -+ int i,j; -+ -+ -+ -+ for( j = 0; j < MV_SATA_MAX_CHAN; j++ ) -+ { -+ if (MV_FALSE == mvCtrlPwrClckGet(SATA_UNIT_ID, j)) -+ return; -+ -+ mvOsOutput( "\n" ); -+ mvOsOutput( "SATA %d:\n", j ); -+ mvOsOutput( "----\n" ); -+ -+ for( i = 0; i < MV_SATA_MAX_ADDR_DECODE_WIN; i++ ) -+ { -+ memset( &win, 0, sizeof(MV_SATA_DEC_WIN) ); -+ -+ mvOsOutput( "win%d - ", i ); -+ -+ if( mvSataWinGet(j, i, &win ) == MV_OK ) -+ { -+ if( win.enable ) -+ { -+ mvOsOutput( "%s base %08x, ", -+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); -+ mvOsOutput( "...." ); -+ -+ mvSizePrint( win.addrWin.size ); -+ -+ mvOsOutput( "\n" ); -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ } -+ } -+ } -+} -+ -+ -+/******************************************************************************* -+* mvSataWinInit - Initialize the integrated SATA target address window. -+* -+* DESCRIPTION: -+* Initialize the SATA peripheral target address window. -+* -+* INPUT: -+* -+* -+* OUTPUT: -+* -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvSataWinInit(MV_VOID) -+{ -+ int winNum; -+ MV_SATA_DEC_WIN sataWin; -+ MV_CPU_DEC_WIN cpuAddrDecWin; -+ MV_U32 status, winPrioIndex = 0; -+ -+ /* Initiate Sata address decode */ -+ -+ /* First disable all address decode windows */ -+ for(winNum = 0; winNum < MV_SATA_MAX_ADDR_DECODE_WIN; winNum++) -+ { -+ MV_U32 regVal = MV_REG_READ(MV_SATA_WIN_CTRL_REG(0, winNum)); -+ regVal &= ~MV_SATA_WIN_ENABLE_MASK; -+ MV_REG_WRITE(MV_SATA_WIN_CTRL_REG(0, winNum), regVal); -+ } -+ -+ winNum = 0; -+ while( (sataAddrDecPrioTab[winPrioIndex] != TBL_TERM) && -+ (winNum < MV_SATA_MAX_ADDR_DECODE_WIN) ) -+ { -+ /* first get attributes from CPU If */ -+ status = mvCpuIfTargetWinGet(sataAddrDecPrioTab[winPrioIndex], -+ &cpuAddrDecWin); -+ -+ if(MV_NO_SUCH == status) -+ { -+ winPrioIndex++; -+ continue; -+ } -+ if (MV_OK != status) -+ { -+ mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ if (cpuAddrDecWin.enable == MV_TRUE) -+ { -+ sataWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; -+ sataWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; -+ sataWin.addrWin.size = cpuAddrDecWin.addrWin.size; -+ sataWin.enable = MV_TRUE; -+ sataWin.target = sataAddrDecPrioTab[winPrioIndex]; -+ -+ if(MV_OK != mvSataWinSet(0/*dev*/, winNum, &sataWin)) -+ { -+ return MV_ERROR; -+ } -+ winNum++; -+ } -+ winPrioIndex++; -+ } -+ return MV_OK; -+} -+ -+ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.h 2010-11-09 20:28:08.526524216 +0100 -@@ -0,0 +1,128 @@ -+ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#ifndef __INCMVSysSataAddrDech -+#define __INCMVSysSataAddrDech -+ -+#include "mvCommon.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+ -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+typedef struct _mvSataDecWin -+{ -+ MV_TARGET target; -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+} MV_SATA_DEC_WIN; -+ -+ -+#define MV_SATA_MAX_ADDR_DECODE_WIN 4 -+ -+#define MV_SATA_WIN_CTRL_REG(dev, win) (SATA_REG_BASE + 0x30 + ((win)<<4)) -+#define MV_SATA_WIN_BASE_REG(dev, win) (SATA_REG_BASE + 0x34 + ((win)<<4)) -+ -+/* BITs in Bridge Interrupt Cause and Mask registers */ -+#define MV_SATA_ADDR_DECODE_ERROR_BIT 0 -+#define MV_SATA_ADDR_DECODE_ERROR_MASK (1<= MV_SDMMC_MAX_ADDR_DECODE_WIN) -+ { -+ mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlapps with current windows */ -+ if (MV_TRUE == sdmmcWinOverlapDetect(dev, winNum, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); -+ return MV_ERROR; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvSdmmcWinSet:Error setting SDMMC window %d to "\ -+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, -+ mvCtrlTargetNameGet(pAddrDecWin->target), -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ decRegs.baseReg = 0; -+ decRegs.sizeReg = 0; -+ -+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) -+ { -+ mvOsPrintf("%s: mvCtrlAddrDecToReg Failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); -+ -+ /* set attributes */ -+ decRegs.sizeReg &= ~MV_SDMMC_WIN_ATTR_MASK; -+ decRegs.sizeReg |= (targetAttribs.attrib << MV_SDMMC_WIN_ATTR_OFFSET); -+ -+ /* set target ID */ -+ decRegs.sizeReg &= ~MV_SDMMC_WIN_TARGET_MASK; -+ decRegs.sizeReg |= (targetAttribs.targetId << MV_SDMMC_WIN_TARGET_OFFSET); -+ -+ if (pAddrDecWin->enable == MV_TRUE) -+ { -+ decRegs.sizeReg |= MV_SDMMC_WIN_ENABLE_MASK; -+ } -+ else -+ { -+ decRegs.sizeReg &= ~MV_SDMMC_WIN_ENABLE_MASK; -+ } -+ -+ MV_REG_WRITE( MV_SDMMC_WIN_CTRL_REG(dev, winNum), decRegs.sizeReg); -+ MV_REG_WRITE( MV_SDMMC_WIN_BASE_REG(dev, winNum), decRegs.baseReg); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSdmmcWinGet - Get SDMMC peripheral target address window. -+* -+* DESCRIPTION: -+* Get SDMMC peripheral target address window. -+* -+* INPUT: -+* winNum - SDMMC target address decode window number. -+*d -+* OUTPUT: -+* pAddrDecWin - SDMMC target window data structure. -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvSdmmcWinGet(int dev, MV_U32 winNum, MV_SDMMC_DEC_WIN *pAddrDecWin) -+{ -+ MV_DEC_REGS decRegs; -+ MV_TARGET_ATTRIB targetAttrib; -+ -+ /* Parameter checking */ -+ if (winNum >= MV_SDMMC_MAX_ADDR_DECODE_WIN) -+ { -+ mvOsPrintf("%s (dev=%d): ERR. Invalid winNum %d\n", -+ __FUNCTION__, dev, winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ decRegs.baseReg = MV_REG_READ( MV_SDMMC_WIN_BASE_REG(dev, winNum) ); -+ decRegs.sizeReg = MV_REG_READ( MV_SDMMC_WIN_CTRL_REG(dev, winNum) ); -+ -+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs, &pAddrDecWin->addrWin) ) -+ { -+ mvOsPrintf("%s: mvCtrlRegToAddrDec Failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ /* attrib and targetId */ -+ targetAttrib.attrib = (decRegs.sizeReg & MV_SDMMC_WIN_ATTR_MASK) >> -+ MV_SDMMC_WIN_ATTR_OFFSET; -+ targetAttrib.targetId = (decRegs.sizeReg & MV_SDMMC_WIN_TARGET_MASK) >> -+ MV_SDMMC_WIN_TARGET_OFFSET; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ /* Check if window is enabled */ -+ if(decRegs.sizeReg & MV_SDMMC_WIN_ENABLE_MASK) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ } -+ return MV_OK; -+} -+/******************************************************************************* -+* mvSdmmcAddrDecShow - Print the SDMMC address decode map. -+* -+* DESCRIPTION: -+* This function print the SDMMC address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvSdmmcAddrDecShow(MV_VOID) -+{ -+ -+ MV_SDMMC_DEC_WIN win; -+ int i,j=0; -+ -+ -+ -+ if (MV_FALSE == mvCtrlPwrClckGet(SDIO_UNIT_ID, 0)) -+ return; -+ -+ mvOsOutput( "\n" ); -+ mvOsOutput( "SDMMC %d:\n", j ); -+ mvOsOutput( "----\n" ); -+ -+ for( i = 0; i < MV_SDMMC_MAX_ADDR_DECODE_WIN; i++ ) -+ { -+ memset( &win, 0, sizeof(MV_SDMMC_DEC_WIN) ); -+ -+ mvOsOutput( "win%d - ", i ); -+ -+ if( mvSdmmcWinGet(j, i, &win ) == MV_OK ) -+ { -+ if( win.enable ) -+ { -+ mvOsOutput( "%s base %08x, ", -+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); -+ mvOsOutput( "...." ); -+ -+ mvSizePrint( win.addrWin.size ); -+ -+ mvOsOutput( "\n" ); -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ } -+ } -+} -+ -+ -+/******************************************************************************* -+* mvSdmmcWinInit - Initialize the integrated SDMMC target address window. -+* -+* DESCRIPTION: -+* Initialize the SDMMC peripheral target address window. -+* -+* INPUT: -+* -+* -+* OUTPUT: -+* -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvSdmmcWinInit(MV_VOID) -+{ -+ int winNum; -+ MV_SDMMC_DEC_WIN sdmmcWin; -+ MV_CPU_DEC_WIN cpuAddrDecWin; -+ MV_U32 status, winPrioIndex = 0; -+ -+ /* Initiate Sdmmc address decode */ -+ -+ /* First disable all address decode windows */ -+ for(winNum = 0; winNum < MV_SDMMC_MAX_ADDR_DECODE_WIN; winNum++) -+ { -+ MV_U32 regVal = MV_REG_READ(MV_SDMMC_WIN_CTRL_REG(0, winNum)); -+ regVal &= ~MV_SDMMC_WIN_ENABLE_MASK; -+ MV_REG_WRITE(MV_SDMMC_WIN_CTRL_REG(0, winNum), regVal); -+ } -+ -+ winNum = 0; -+ while( (sdmmcAddrDecPrioTab[winPrioIndex] != TBL_TERM) && -+ (winNum < MV_SDMMC_MAX_ADDR_DECODE_WIN) ) -+ { -+ /* first get attributes from CPU If */ -+ status = mvCpuIfTargetWinGet(sdmmcAddrDecPrioTab[winPrioIndex], -+ &cpuAddrDecWin); -+ -+ if(MV_NO_SUCH == status) -+ { -+ winPrioIndex++; -+ continue; -+ } -+ if (MV_OK != status) -+ { -+ mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ if (cpuAddrDecWin.enable == MV_TRUE) -+ { -+ sdmmcWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; -+ sdmmcWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; -+ sdmmcWin.addrWin.size = cpuAddrDecWin.addrWin.size; -+ sdmmcWin.enable = MV_TRUE; -+ sdmmcWin.target = sdmmcAddrDecPrioTab[winPrioIndex]; -+ -+ if(MV_OK != mvSdmmcWinSet(0/*dev*/, winNum, &sdmmcWin)) -+ { -+ return MV_ERROR; -+ } -+ winNum++; -+ } -+ winPrioIndex++; -+ } -+ return MV_OK; -+} -+ -+ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h 2010-11-09 20:28:08.891243103 +0100 -@@ -0,0 +1,125 @@ -+ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#ifndef __INCMVSysSdmmcAddrDech -+#define __INCMVSysSdmmcAddrDech -+ -+#include "mvCommon.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+ -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+typedef struct _mvSdmmcDecWin -+{ -+ MV_TARGET target; -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+} MV_SDMMC_DEC_WIN; -+ -+ -+#define MV_SDMMC_MAX_ADDR_DECODE_WIN 4 -+ -+#define MV_SDMMC_WIN_CTRL_REG(dev, win) (MV_SDIO_REG_BASE + 0x108 + ((win)<<3)) -+#define MV_SDMMC_WIN_BASE_REG(dev, win) (MV_SDIO_REG_BASE + 0x10c + ((win)<<3)) -+ -+ -+/* BITs in Windows 0-3 Control and Base Registers */ -+#define MV_SDMMC_WIN_ENABLE_BIT 0 -+#define MV_SDMMC_WIN_ENABLE_MASK (1<= TDM_MBUS_MAX_WIN) -+ { -+ mvOsPrintf("mvTdmWinSet: ERR. Invalid win num %d\n",winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlapps with current windows */ -+ if (MV_TRUE == tdmWinOverlapDetect(winNum, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("mvTdmWinSet: ERR. Window %d overlap\n", winNum); -+ return MV_ERROR; -+ } -+ -+ /* check if address is aligned to the size */ -+ if (MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvTdmWinSet: Error setting TDM window %d to "\ -+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, -+ mvCtrlTargetNameGet(pAddrDecWin->target), -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ decRegs.baseReg = MV_REG_READ(TDM_WIN_BASE_REG(winNum)); -+ decRegs.sizeReg = (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_SIZE_MASK) >> TDM_WIN_SIZE_OFFS; -+ -+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) -+ { -+ mvOsPrintf("mvTdmWinSet: mvCtrlAddrDecToReg Failed\n"); -+ return MV_ERROR; -+ } -+ -+ mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); -+ -+ /* for the safe side we disable the window before writing the new -+ values */ -+ mvTdmWinEnable(winNum, MV_FALSE); -+ -+ ctrlReg |= (targetAttribs.attrib << TDM_WIN_ATTRIB_OFFS); -+ ctrlReg |= (targetAttribs.targetId << TDM_WIN_TARGET_OFFS); -+ ctrlReg |= (decRegs.sizeReg & TDM_WIN_SIZE_MASK); -+ -+ /* Write to address base and control registers */ -+ MV_REG_WRITE(TDM_WIN_BASE_REG(winNum), decRegs.baseReg); -+ MV_REG_WRITE(TDM_WIN_CTRL_REG(winNum), ctrlReg); -+ /* Enable address decode target window */ -+ if (pAddrDecWin->enable == MV_TRUE) -+ { -+ mvTdmWinEnable(winNum, MV_TRUE); -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvTdmWinGet - Get peripheral target address window. -+* -+* DESCRIPTION: -+* Get TDM peripheral target address window. -+* -+* INPUT: -+* winNum - TDM to target address decode window number. -+* -+* OUTPUT: -+* pAddrDecWin - TDM target window data structure. -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+ -+MV_STATUS mvTdmWinGet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin) -+{ -+ -+ MV_DEC_REGS decRegs; -+ MV_TARGET_ATTRIB targetAttrib; -+ -+ /* Parameter checking */ -+ if (winNum >= TDM_MBUS_MAX_WIN) -+ { -+ mvOsPrintf("mvTdmWinGet: ERR. Invalid winNum %d\n", winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ decRegs.baseReg = MV_REG_READ(TDM_WIN_BASE_REG(winNum)); -+ decRegs.sizeReg = (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_SIZE_MASK) >> TDM_WIN_SIZE_OFFS; -+ -+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) -+ { -+ mvOsPrintf("mvTdmWinGet: mvCtrlRegToAddrDec Failed \n"); -+ return MV_ERROR; -+ } -+ -+ /* attrib and targetId */ -+ targetAttrib.attrib = -+ (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ATTRIB_MASK) >> TDM_WIN_ATTRIB_OFFS; -+ targetAttrib.targetId = -+ (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_TARGET_MASK) >> TDM_WIN_TARGET_OFFS; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ /* Check if window is enabled */ -+ if (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ENABLE_MASK) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvTdmWinEnable - Enable/disable a TDM to target address window -+* -+* DESCRIPTION: -+* This function enable/disable a TDM to target address window. -+* According to parameter 'enable' the routine will enable the -+* window, thus enabling TDM accesses (before enabling the window it is -+* tested for overlapping). Otherwise, the window will be disabled. -+* -+* INPUT: -+* winNum - TDM to target address decode window number. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_ERROR if decode window number was wrong or enabled window overlapps. -+* -+*******************************************************************************/ -+MV_STATUS mvTdmWinEnable(int winNum, MV_BOOL enable) -+{ -+ MV_TDM_DEC_WIN addrDecWin; -+ -+ if (MV_TRUE == enable) -+ { -+ if (winNum >= TDM_MBUS_MAX_WIN) -+ { -+ mvOsPrintf("mvTdmWinEnable:ERR. Invalid winNum%d\n",winNum); -+ return MV_ERROR; -+ } -+ -+ /* First check for overlap with other enabled windows */ -+ /* Get current window */ -+ if (MV_OK != mvTdmWinGet(winNum, &addrDecWin)) -+ { -+ mvOsPrintf("mvTdmWinEnable:ERR. targetWinGet fail\n"); -+ return MV_ERROR; -+ } -+ /* Check for overlapping */ -+ if (MV_FALSE == tdmWinOverlapDetect(winNum, &(addrDecWin.addrWin))) -+ { -+ /* No Overlap. Enable address decode target window */ -+ MV_REG_BIT_SET(TDM_WIN_CTRL_REG(winNum), TDM_WIN_ENABLE_MASK); -+ } -+ else -+ { /* Overlap detected */ -+ mvOsPrintf("mvTdmWinEnable:ERR. Overlap detected\n"); -+ return MV_ERROR; -+ } -+ } -+ else -+ { -+ MV_REG_BIT_RESET(TDM_WIN_CTRL_REG(winNum), TDM_WIN_ENABLE_MASK); -+ } -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* tdmWinOverlapDetect - Detect TDM address windows overlapping -+* -+* DESCRIPTION: -+* An unpredicted behaviour is expected in case TDM address decode -+* windows overlapps. -+* This function detects TDM address decode windows overlapping of a -+* specified window. The function does not check the window itself for -+* overlapping. The function also skipps disabled address decode windows. -+* -+* INPUT: -+* winNum - address decode window number. -+* pAddrDecWin - An address decode window struct. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data -+* from registers. -+* -+*******************************************************************************/ -+static MV_STATUS tdmWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 winNumIndex; -+ MV_TDM_DEC_WIN addrDecWin; -+ -+ for (winNumIndex = 0; winNumIndex < TDM_MBUS_MAX_WIN; winNumIndex++) -+ { -+ /* Do not check window itself */ -+ if (winNumIndex == winNum) -+ { -+ continue; -+ } -+ /* Do not check disabled windows */ -+ if (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ENABLE_MASK) -+ { -+ /* Get window parameters */ -+ if (MV_OK != mvTdmWinGet(winNumIndex, &addrDecWin)) -+ { -+ DB(mvOsPrintf("dmaWinOverlapDetect: ERR. TargetWinGet failed\n")); -+ return MV_ERROR; -+ } -+ -+ if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin))) -+ { -+ return MV_TRUE; -+ } -+ } -+ } -+ return MV_FALSE; -+} -+ -+/******************************************************************************* -+* mvTdmAddrDecShow - Print the TDM address decode map. -+* -+* DESCRIPTION: -+* This function print the TDM address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvTdmAddrDecShow(MV_VOID) -+{ -+ MV_TDM_DEC_WIN win; -+ int i; -+ -+ mvOsOutput( "\n" ); -+ mvOsOutput( "TDM:\n" ); -+ mvOsOutput( "----\n" ); -+ -+ for( i = 0; i < TDM_MBUS_MAX_WIN; i++ ) -+ { -+ memset( &win, 0, sizeof(MV_TDM_DEC_WIN) ); -+ -+ mvOsOutput( "win%d - ", i ); -+ -+ if (mvTdmWinGet(i, &win ) == MV_OK ) -+ { -+ if( win.enable ) -+ { -+ mvOsOutput( "%s base %08x, ", -+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow); -+ mvOsOutput( "...." ); -+ mvSizePrint( win.addrWin.size ); -+ mvOsOutput( "\n" ); -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ } -+ } -+} -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.h 2010-11-09 20:28:09.471497270 +0100 -@@ -0,0 +1,106 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvSysTdmh -+#define __INCmvSysTdmh -+ -+#include "ctrlEnv/sys/mvCpuIf.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+ -+typedef struct _mvTdmDecWin -+{ -+ MV_TARGET target; -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+} MV_TDM_DEC_WIN; -+ -+MV_STATUS mvTdmWinInit(MV_VOID); -+MV_STATUS mvTdmWinSet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin); -+MV_STATUS mvTdmWinGet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin); -+MV_STATUS mvTdmWinEnable(int winNum, MV_BOOL enable); -+MV_VOID mvTdmAddrDecShow(MV_VOID); -+ -+ -+#define TDM_MBUS_MAX_WIN 4 -+#define TDM_WIN_CTRL_REG(win) ((TDM_REG_BASE + 0x4030) + (win<<4)) -+#define TDM_WIN_BASE_REG(win) ((TDM_REG_BASE +0x4034) + (win<<4)) -+ -+/* TDM_WIN_CTRL_REG bits */ -+#define TDM_WIN_ENABLE_OFFS 0 -+#define TDM_WIN_ENABLE_MASK (1<= TSU_MAX_DECODE_WIN) -+ { -+ mvOsPrintf("mvTsuWinSet: ERR. Invalid win num %d\n",winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlapps with current windows */ -+ if(MV_TRUE == tsuWinOverlapDetect(winNum, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("mvTsuWinSet: ERR. Window %d overlap\n", winNum); -+ return MV_ERROR; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow,pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvTsuWinSet: Error setting TSU window %d to target " -+ "%s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, mvCtrlTargetNameGet(pAddrDecWin->target), -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ decRegs.baseReg = MV_REG_READ(MV_TSU_WIN_BASE_REG(winNum)); -+ decRegs.sizeReg = MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNum)); -+ -+ if(MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) -+ { -+ mvOsPrintf("mvTsuWinSet: mvCtrlAddrDecToReg Failed\n"); -+ return MV_ERROR; -+ } -+ -+ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); -+ -+ /* set attributes */ -+ decRegs.sizeReg &= ~TSU_WIN_CTRL_ATTR_MASK; -+ decRegs.sizeReg |= targetAttribs.attrib << TSU_WIN_CTRL_ATTR_OFFS; -+ /* set target ID */ -+ decRegs.sizeReg &= ~TSU_WIN_CTRL_TARGET_MASK; -+ decRegs.sizeReg |= targetAttribs.targetId << TSU_WIN_CTRL_TARGET_OFFS; -+ -+ /* for the safe side we disable the window before writing the new */ -+ /* values */ -+ mvTsuWinEnable(winNum, MV_FALSE); -+ MV_REG_WRITE(MV_TSU_WIN_CTRL_REG(winNum),decRegs.sizeReg); -+ -+ /* Write to address decode Size Register */ -+ MV_REG_WRITE(MV_TSU_WIN_BASE_REG(winNum), decRegs.baseReg); -+ -+ /* Enable address decode target window */ -+ if(pAddrDecWin->enable == MV_TRUE) -+ { -+ mvTsuWinEnable(winNum,MV_TRUE); -+ } -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvTsuWinGet -+* -+* DESCRIPTION: -+* Get TSU peripheral target address window. -+* -+* INPUT: -+* winNum - TSU to target address decode window number. -+* -+* OUTPUT: -+* pAddrDecWin - TSU target window data structure. -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvTsuWinGet(MV_U32 winNum, MV_TSU_DEC_WIN *pAddrDecWin) -+{ -+ MV_DEC_REGS decRegs; -+ MV_TARGET_ATTRIB targetAttrib; -+ -+ /* Parameter checking */ -+ if(winNum >= TSU_MAX_DECODE_WIN) -+ { -+ mvOsPrintf("mvTsuWinGet: ERR. Invalid winNum %d\n", winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ decRegs.baseReg = MV_REG_READ(MV_TSU_WIN_BASE_REG(winNum)); -+ decRegs.sizeReg = MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNum)); -+ -+ if(MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) -+ { -+ mvOsPrintf("mvTsuWinGet: mvCtrlRegToAddrDec Failed \n"); -+ return MV_ERROR; -+ } -+ -+ /* attrib and targetId */ -+ targetAttrib.attrib = -+ (decRegs.sizeReg & TSU_WIN_CTRL_ATTR_MASK) >> TSU_WIN_CTRL_ATTR_OFFS; -+ targetAttrib.targetId = -+ (decRegs.sizeReg & TSU_WIN_CTRL_TARGET_MASK) >> TSU_WIN_CTRL_TARGET_OFFS; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ /* Check if window is enabled */ -+ if((MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNum)) & TSU_WIN_CTRL_EN_MASK)) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ } -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvTsuWinEnable -+* -+* DESCRIPTION: -+* This function enable/disable a TSU to target address window. -+* According to parameter 'enable' the routine will enable the -+* window, thus enabling TSU accesses (before enabling the window it is -+* tested for overlapping). Otherwise, the window will be disabled. -+* -+* INPUT: -+* winNum - TSU to target address decode window number. -+* enable - Enable / disable parameter. -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_ERROR if decode window number was wrong or enabled window overlapps. -+* -+*******************************************************************************/ -+MV_STATUS mvTsuWinEnable(MV_U32 winNum,MV_BOOL enable) -+{ -+ MV_TSU_DEC_WIN addrDecWin; -+ -+ /* Parameter checking */ -+ if(winNum >= TSU_MAX_DECODE_WIN) -+ { -+ mvOsPrintf("mvTsuWinEnable: ERR. Invalid winNum%d\n",winNum); -+ return MV_ERROR; -+ } -+ -+ if(enable == MV_TRUE) -+ { -+ /* First check for overlap with other enabled windows */ -+ /* Get current window. */ -+ if(MV_OK != mvTsuWinGet(winNum,&addrDecWin)) -+ { -+ mvOsPrintf("mvTsuWinEnable: ERR. targetWinGet fail\n"); -+ return MV_ERROR; -+ } -+ /* Check for overlapping. */ -+ if(MV_FALSE == tsuWinOverlapDetect(winNum,&(addrDecWin.addrWin))) -+ { -+ /* No Overlap. Enable address decode target window */ -+ MV_REG_BIT_SET(MV_TSU_WIN_CTRL_REG(winNum), -+ TSU_WIN_CTRL_EN_MASK); -+ } -+ else -+ { -+ /* Overlap detected */ -+ mvOsPrintf("mvTsuWinEnable: ERR. Overlap detected\n"); -+ return MV_ERROR; -+ } -+ } -+ else -+ { -+ /* Disable address decode target window */ -+ MV_REG_BIT_RESET(MV_TSU_WIN_CTRL_REG(winNum), -+ TSU_WIN_CTRL_EN_MASK); -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvTsuWinTargetGet -+* -+* DESCRIPTION: -+* Get Window number associated with target -+* -+* INPUT: -+* target - Target ID to get the window number for. -+* OUTPUT: -+* -+* RETURN: -+* window number or 0xFFFFFFFF on error. -+* -+*******************************************************************************/ -+MV_U32 mvTsuWinTargetGet(MV_TARGET target) -+{ -+ MV_TSU_DEC_WIN decWin; -+ MV_U32 winNum; -+ -+ /* Check parameters */ -+ if(target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvTsuWinTargetGet: target %d is Illigal\n", target); -+ return 0xffffffff; -+ } -+ -+ for(winNum = 0; winNum < TSU_MAX_DECODE_WIN; winNum++) -+ { -+ if(mvTsuWinGet(winNum,&decWin) != MV_OK) -+ { -+ mvOsPrintf("mvTsuWinGet: window returned error\n"); -+ return 0xffffffff; -+ } -+ -+ if (decWin.enable == MV_TRUE) -+ { -+ if(decWin.target == target) -+ { -+ return winNum; -+ } -+ } -+ } -+ return 0xFFFFFFFF; -+} -+ -+ -+/******************************************************************************* -+* tsuWinOverlapDetect -+* -+* DESCRIPTION: -+* Detect TSU address windows overlapping -+* An unpredicted behaviur is expected in case TSU address decode -+* windows overlapps. -+* This function detects TSU address decode windows overlapping of a -+* specified window. The function does not check the window itself for -+* overlapping. The function also skipps disabled address decode windows. -+* -+* INPUT: -+* winNum - address decode window number. -+* pAddrDecWin - An address decode window struct. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data -+* from registers. -+* -+*******************************************************************************/ -+static MV_STATUS tsuWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 ctrlReg; -+ MV_U32 winNumIndex; -+ MV_TSU_DEC_WIN addrDecWin; -+ -+ for(winNumIndex = 0; winNumIndex < TSU_MAX_DECODE_WIN; winNumIndex++) -+ { -+ /* Do not check window itself */ -+ if(winNumIndex == winNum) -+ { -+ continue; -+ } -+ -+ /* Do not check disabled windows */ -+ ctrlReg = MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNumIndex)); -+ if((ctrlReg & TSU_WIN_CTRL_EN_MASK) == 0) -+ { -+ continue; -+ } -+ -+ /* Get window parameters */ -+ if (MV_OK != mvTsuWinGet(winNumIndex, &addrDecWin)) -+ { -+ mvOsPrintf("tsuWinOverlapDetect: ERR. mvTsuWinGet failed\n"); -+ return MV_ERROR; -+ } -+ -+ if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin))) -+ { -+ return MV_TRUE; -+ } -+ } -+ return MV_FALSE; -+} -+ -+ -+/******************************************************************************* -+* mvTsuAddrDecShow -+* -+* DESCRIPTION: -+* Print the TSU address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+void mvTsuAddrDecShow(void) -+{ -+ MV_TSU_DEC_WIN win; -+ int i; -+ -+ if (MV_FALSE == mvCtrlPwrClckGet(TS_UNIT_ID, 0)) -+ return; -+ -+ mvOsOutput( "\n" ); -+ mvOsOutput( "TSU:\n"); -+ mvOsOutput( "----\n" ); -+ -+ for(i = 0; i < TSU_MAX_DECODE_WIN; i++) -+ { -+ memset(&win, 0, sizeof(TSU_MAX_DECODE_WIN)); -+ mvOsOutput( "win%d - ", i ); -+ -+ if(mvTsuWinGet(i, &win ) == MV_OK ) -+ { -+ if(win.enable == MV_TRUE) -+ { -+ mvOsOutput("%s base %08x, ", -+ mvCtrlTargetNameGet(win.target), -+ win.addrWin.baseLow); -+ mvOsOutput( "...." ); -+ mvSizePrint(win.addrWin.size ); -+ mvOsOutput( "\n" ); -+ } -+ else -+ { -+ mvOsOutput( "disable\n" ); -+ } -+ } -+ } -+ return; -+} -+ -+ -+/******************************************************************************* -+* mvTsuInit -+* -+* DESCRIPTION: -+* Initialize the TSU unit, and get unit out of reset. -+* -+* INPUT: -+* coreClock - The core clock at which the TSU should operate. -+* mode - The mode on configure the unit into (serial/parallel). -+* memHandle - Memory handle used for memory allocations. -+* OUTPUT: -+* None. -+* RETURN: -+* MV_OK - on success, -+* -+*******************************************************************************/ -+MV_STATUS mvTsuInit(MV_TSU_CORE_CLOCK coreClock, MV_TSU_PORTS_MODE mode, -+ void *osHandle) -+{ -+ MV_STATUS status; -+ -+ status = mvTsuWinInit(); -+ if(status == MV_OK) -+ status = mvTsuHalInit(coreClock,mode,osHandle); -+ -+ return status; -+} -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h 2010-11-09 20:28:09.894776606 +0100 -@@ -0,0 +1,110 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvSysTsh -+#define __INCmvSysTsh -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* includes */ -+#include "ts/mvTsu.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+ -+#define TSU_MAX_DECODE_WIN 4 -+ -+ -+/*******************************************/ -+/* TSU Windows Registers */ -+/*******************************************/ -+#define MV_TSU_WIN_CTRL_REG(win) (TSU_GLOBAL_REG_BASE +0x30 + 0x10 * win) -+#define MV_TSU_WIN_BASE_REG(win) (TSU_GLOBAL_REG_BASE +0x34 + 0x10 * win) -+ -+/* TSU windows control register. */ -+#define TSU_WIN_CTRL_EN_MASK (0x1 << 0) -+#define TSU_WIN_CTRL_TARGET_OFFS 4 -+#define TSU_WIN_CTRL_TARGET_MASK (0xF << TSU_WIN_CTRL_TARGET_OFFS) -+#define TSU_WIN_CTRL_ATTR_OFFS 8 -+#define TSU_WIN_CTRL_ATTR_MASK (0xFF << TSU_WIN_CTRL_ATTR_OFFS) -+#define TSU_WIN_CTRL_SIZE_OFFS 16 -+#define TSU_WIN_CTRL_SIZE_MASK (0xFFFF << TSU_WIN_CTRL_SIZE_OFFS) -+ -+/* TSU windows base register. */ -+#define TSU_WIN_BASE_OFFS 16 -+#define TSU_WIN_BASE_MASK (0xFFFF << TSU_WIN_BASE_OFFS) -+ -+MV_STATUS mvTsuWinInit(void); -+ -+void mvTsuAddrDecShow(void); -+MV_STATUS mvTsuInit(MV_TSU_CORE_CLOCK coreClock, MV_TSU_PORTS_MODE mode, -+ void *osHandle); -+ -+#ifdef __cplusplus -+} -+#endif /* __cplusplus */ -+ -+#endif /* __INCmvTsh */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.c 2010-11-09 20:28:09.932495382 +0100 -@@ -0,0 +1,497 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "ctrlEnv/sys/mvSysUsb.h" -+ -+MV_TARGET usbAddrDecPrioTab[] = -+{ -+#if defined(MV_INCLUDE_SDRAM_CS0) -+ SDRAM_CS0, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS1) -+ SDRAM_CS1, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS2) -+ SDRAM_CS2, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS3) -+ SDRAM_CS3, -+#endif -+#if defined(MV_INCLUDE_CESA) && defined(USB_UNDERRUN_WA) -+ CRYPT_ENG, -+#endif -+#if defined(MV_INCLUDE_PEX) -+ PEX0_MEM, -+#endif -+ TBL_TERM -+}; -+ -+ -+ -+MV_STATUS mvUsbInit(int dev, MV_BOOL isHost) -+{ -+ MV_STATUS status; -+ -+ status = mvUsbWinInit(dev); -+ if(status != MV_OK) -+ return status; -+ -+ return mvUsbHalInit(dev, isHost); -+} -+ -+ -+/******************************************************************************* -+* usbWinOverlapDetect - Detect USB address windows overlapping -+* -+* DESCRIPTION: -+* An unpredicted behaviur is expected in case USB address decode -+* windows overlapps. -+* This function detects USB address decode windows overlapping of a -+* specified window. The function does not check the window itself for -+* overlapping. The function also skipps disabled address decode windows. -+* -+* INPUT: -+* winNum - address decode window number. -+* pAddrDecWin - An address decode window struct. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data -+* from registers. -+* -+*******************************************************************************/ -+static MV_STATUS usbWinOverlapDetect(int dev, MV_U32 winNum, -+ MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 winNumIndex; -+ MV_DEC_WIN addrDecWin; -+ -+ for(winNumIndex=0; winNumIndex= MV_USB_MAX_ADDR_DECODE_WIN) -+ { -+ mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlapps with current windows */ -+ if (MV_TRUE == usbWinOverlapDetect(dev, winNum, &pDecWin->addrWin)) -+ { -+ mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); -+ return MV_ERROR; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pDecWin->addrWin.baseLow, pDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvUsbWinSet:Error setting USB window %d to "\ -+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, -+ mvCtrlTargetNameGet(pDecWin->target), -+ pDecWin->addrWin.baseLow, -+ pDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ if(MV_OK != mvCtrlAddrDecToParams(pDecWin, &winParams)) -+ { -+ mvOsPrintf("%s: mvCtrlAddrDecToParams Failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ /* set Size, Attributes and TargetID */ -+ sizeReg = (((winParams.targetId << MV_USB_WIN_TARGET_OFFSET) & MV_USB_WIN_TARGET_MASK) | -+ ((winParams.attrib << MV_USB_WIN_ATTR_OFFSET) & MV_USB_WIN_ATTR_MASK) | -+ ((winParams.size << MV_USB_WIN_SIZE_OFFSET) & MV_USB_WIN_SIZE_MASK)); -+ -+#if defined(MV645xx) || defined(MV646xx) -+ /* If window is DRAM with HW cache coherency, make sure bit2 is set */ -+ sizeReg &= ~MV_USB_WIN_BURST_WR_LIMIT_MASK; -+ -+ if((MV_TARGET_IS_DRAM(pDecWin->target)) && -+ (pDecWin->addrWinAttr.cachePolicy != NO_COHERENCY)) -+ { -+ sizeReg |= MV_USB_WIN_BURST_WR_32BIT_LIMIT; -+ } -+ else -+ { -+ sizeReg |= MV_USB_WIN_BURST_WR_NO_LIMIT; -+ } -+#endif /* MV645xx || MV646xx */ -+ -+ if (pDecWin->enable == MV_TRUE) -+ { -+ sizeReg |= MV_USB_WIN_ENABLE_MASK; -+ } -+ else -+ { -+ sizeReg &= ~MV_USB_WIN_ENABLE_MASK; -+ } -+ -+ /* Update Base value */ -+ baseReg = (winParams.baseAddr & MV_USB_WIN_BASE_MASK); -+ -+ MV_REG_WRITE( MV_USB_WIN_CTRL_REG(dev, winNum), sizeReg); -+ MV_REG_WRITE( MV_USB_WIN_BASE_REG(dev, winNum), baseReg); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvUsbWinGet - Get USB peripheral target address window. -+* -+* DESCRIPTION: -+* Get USB peripheral target address window. -+* -+* INPUT: -+* winNum - USB target address decode window number. -+* -+* OUTPUT: -+* pDecWin - USB target window data structure. -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvUsbWinGet(int dev, MV_U32 winNum, MV_DEC_WIN *pDecWin) -+{ -+ MV_DEC_WIN_PARAMS winParam; -+ MV_U32 sizeReg, baseReg; -+ -+ /* Parameter checking */ -+ if (winNum >= MV_USB_MAX_ADDR_DECODE_WIN) -+ { -+ mvOsPrintf("%s (dev=%d): ERR. Invalid winNum %d\n", -+ __FUNCTION__, dev, winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ baseReg = MV_REG_READ( MV_USB_WIN_BASE_REG(dev, winNum) ); -+ sizeReg = MV_REG_READ( MV_USB_WIN_CTRL_REG(dev, winNum) ); -+ -+ /* Check if window is enabled */ -+ if(sizeReg & MV_USB_WIN_ENABLE_MASK) -+ { -+ pDecWin->enable = MV_TRUE; -+ -+ /* Extract window parameters from registers */ -+ winParam.targetId = (sizeReg & MV_USB_WIN_TARGET_MASK) >> MV_USB_WIN_TARGET_OFFSET; -+ winParam.attrib = (sizeReg & MV_USB_WIN_ATTR_MASK) >> MV_USB_WIN_ATTR_OFFSET; -+ winParam.size = (sizeReg & MV_USB_WIN_SIZE_MASK) >> MV_USB_WIN_SIZE_OFFSET; -+ winParam.baseAddr = (baseReg & MV_USB_WIN_BASE_MASK); -+ -+ /* Translate the decode window parameters to address decode struct */ -+ if (MV_OK != mvCtrlParamsToAddrDec(&winParam, pDecWin)) -+ { -+ mvOsPrintf("Failed to translate register parameters to USB address" \ -+ " decode window structure\n"); -+ return MV_ERROR; -+ } -+ } -+ else -+ { -+ pDecWin->enable = MV_FALSE; -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvUsbWinInit - -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvUsbWinInit(int dev) -+{ -+ MV_STATUS status; -+ MV_DEC_WIN usbWin; -+ MV_CPU_DEC_WIN cpuAddrDecWin; -+ int winNum; -+ MV_U32 winPrioIndex = 0; -+ -+ /* First disable all address decode windows */ -+ for(winNum = 0; winNum < MV_USB_MAX_ADDR_DECODE_WIN; winNum++) -+ { -+ MV_REG_BIT_RESET(MV_USB_WIN_CTRL_REG(dev, winNum), MV_USB_WIN_ENABLE_MASK); -+ } -+ -+ /* Go through all windows in user table until table terminator */ -+ winNum = 0; -+ while( (usbAddrDecPrioTab[winPrioIndex] != TBL_TERM) && -+ (winNum < MV_USB_MAX_ADDR_DECODE_WIN) ) -+ { -+ /* first get attributes from CPU If */ -+ status = mvCpuIfTargetWinGet(usbAddrDecPrioTab[winPrioIndex], -+ &cpuAddrDecWin); -+ -+ if(MV_NO_SUCH == status) -+ { -+ winPrioIndex++; -+ continue; -+ } -+ if (MV_OK != status) -+ { -+ mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ if (cpuAddrDecWin.enable == MV_TRUE) -+ { -+ usbWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; -+ usbWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; -+ usbWin.addrWin.size = cpuAddrDecWin.addrWin.size; -+ usbWin.enable = MV_TRUE; -+ usbWin.target = usbAddrDecPrioTab[winPrioIndex]; -+ -+#if defined(MV645xx) || defined(MV646xx) -+ /* Get the default attributes for that target window */ -+ mvCtrlDefAttribGet(usbWin.target, &usbWin.addrWinAttr); -+#endif /* MV645xx || MV646xx */ -+ -+ if(MV_OK != mvUsbWinSet(dev, winNum, &usbWin)) -+ { -+ return MV_ERROR; -+ } -+ winNum++; -+ } -+ winPrioIndex++; -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvUsbAddrDecShow - Print the USB address decode map. -+* -+* DESCRIPTION: -+* This function print the USB address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvUsbAddrDecShow(MV_VOID) -+{ -+ MV_DEC_WIN addrDecWin; -+ int i, winNum; -+ -+ mvOsOutput( "\n" ); -+ mvOsOutput( "USB:\n" ); -+ mvOsOutput( "----\n" ); -+ -+ for(i=0; i= XOR_MAX_ADDR_DEC_WIN) -+ { -+ DB(mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum)); -+ return MV_BAD_PARAM; -+ } -+ if (pAddrDecWin == NULL) -+ { -+ DB(mvOsPrintf("%s: ERR. pAddrDecWin is NULL pointer\n", __FUNCTION__ )); -+ return MV_BAD_PTR; -+ } -+ /* Check if the requested window overlaps with current windows */ -+ if (MV_TRUE == xorWinOverlapDetect(unit, winNum, &pAddrDecWin->addrWin)) -+ { -+ DB(mvOsPrintf("%s: ERR. Window %d overlap\n",__FUNCTION__,winNum)); -+ return MV_ERROR; -+ } -+ -+ xorDecRegs.baseReg = MV_REG_READ(XOR_BASE_ADDR_REG(unit,winNum)); -+ xorDecRegs.sizeReg = MV_REG_READ(XOR_SIZE_MASK_REG(unit,winNum)); -+ -+ /* Get Base Address and size registers values */ -+ if(MV_OK != mvCtrlAddrDecToReg(&pAddrDecWin->addrWin, &xorDecRegs)) -+ { -+ DB(mvOsPrintf("%s: ERR. Invalid addr dec window\n",__FUNCTION__)); -+ return MV_BAD_PARAM; -+ } -+ -+ -+ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); -+ -+ /* set attributes */ -+ xorDecRegs.baseReg &= ~XEBARX_ATTR_MASK; -+ xorDecRegs.baseReg |= targetAttribs.attrib << XEBARX_ATTR_OFFS; -+ /* set target ID */ -+ xorDecRegs.baseReg &= ~XEBARX_TARGET_MASK; -+ xorDecRegs.baseReg |= targetAttribs.targetId << XEBARX_TARGET_OFFS; -+ -+ -+ /* Write to address decode Base Address Register */ -+ MV_REG_WRITE(XOR_BASE_ADDR_REG(unit,winNum), xorDecRegs.baseReg); -+ -+ /* Write to Size Register */ -+ MV_REG_WRITE(XOR_SIZE_MASK_REG(unit,winNum), xorDecRegs.sizeReg); -+ -+ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) -+ { -+ if (pAddrDecWin->enable) -+ { -+ MV_REG_BIT_SET(XOR_WINDOW_CTRL_REG(unit,chan), -+ XEXWCR_WIN_EN_MASK(winNum)); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(XOR_WINDOW_CTRL_REG(unit,chan), -+ XEXWCR_WIN_EN_MASK(winNum)); -+ } -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvXorTargetWinGet - Get xor peripheral target address window. -+* -+* DESCRIPTION: -+* Get xor peripheral target address window. -+* -+* INPUT: -+* winNum - One of the possible XOR memory decode windows. -+* -+* OUTPUT: -+* base - Window base address. -+* size - Window size. -+* enable - window enable/disable. -+* -+* RETURN: -+* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_STATUS mvXorTargetWinGet(MV_U32 unit,MV_U32 winNum, MV_XOR_DEC_WIN *pAddrDecWin) -+{ -+ MV_DEC_REGS xorDecRegs; -+ MV_TARGET_ATTRIB targetAttrib; -+ MV_U32 chan=0,chanWinEn; -+ -+ /* Parameter checking */ -+ if (winNum >= XOR_MAX_ADDR_DEC_WIN) -+ { -+ DB(mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__ , winNum)); -+ return MV_ERROR; -+ } -+ -+ if (NULL == pAddrDecWin) -+ { -+ DB(mvOsPrintf("%s: ERR. pAddrDecWin is NULL pointer\n", __FUNCTION__ )); -+ return MV_BAD_PTR; -+ } -+ -+ chanWinEn = MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,0)) & XEXWCR_WIN_EN_MASK(winNum); -+ -+ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) /* we should scan here all channels per unit */ -+ { -+ /* Check if enable bit is equal for all channels */ -+ if ((MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,chan)) & -+ XEXWCR_WIN_EN_MASK(winNum)) != chanWinEn) -+ { -+ mvOsPrintf("%s: ERR. Window enable field must be equal in " -+ "all channels(chan=%d)\n",__FUNCTION__, chan); -+ return MV_ERROR; -+ } -+ } -+ -+ -+ -+ xorDecRegs.baseReg = MV_REG_READ(XOR_BASE_ADDR_REG(unit,winNum)); -+ xorDecRegs.sizeReg = MV_REG_READ(XOR_SIZE_MASK_REG(unit,winNum)); -+ -+ if (MV_OK != mvCtrlRegToAddrDec(&xorDecRegs, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("%s: ERR. mvCtrlRegToAddrDec failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ /* attrib and targetId */ -+ targetAttrib.attrib = -+ (xorDecRegs.baseReg & XEBARX_ATTR_MASK) >> XEBARX_ATTR_OFFS; -+ targetAttrib.targetId = -+ (xorDecRegs.baseReg & XEBARX_TARGET_MASK) >> XEBARX_TARGET_OFFS; -+ -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ if(chanWinEn) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else pAddrDecWin->enable = MV_FALSE; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvXorTargetWinEnable - Enable/disable a Xor address decode window -+* -+* DESCRIPTION: -+* This function enable/disable a XOR address decode window. -+* if parameter 'enable' == MV_TRUE the routine will enable the -+* window, thus enabling XOR accesses (before enabling the window it is -+* tested for overlapping). Otherwise, the window will be disabled. -+* -+* INPUT: -+* winNum - Decode window number. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_STATUS mvXorTargetWinEnable(MV_U32 unit,MV_U32 winNum, MV_BOOL enable) -+{ -+ MV_XOR_DEC_WIN addrDecWin; -+ MV_U32 chan; -+ -+ /* Parameter checking */ -+ if (winNum >= XOR_MAX_ADDR_DEC_WIN) -+ { -+ DB(mvOsPrintf("%s: ERR. Invalid winNum%d\n", __FUNCTION__, winNum)); -+ return MV_ERROR; -+ } -+ -+ if (enable == MV_TRUE) -+ { -+ /* Get current window */ -+ if (MV_OK != mvXorTargetWinGet(unit,winNum, &addrDecWin)) -+ { -+ DB(mvOsPrintf("%s: ERR. targetWinGet fail\n", __FUNCTION__)); -+ return MV_ERROR; -+ } -+ -+ /* Check for overlapping */ -+ if (MV_TRUE == xorWinOverlapDetect(unit,winNum, &(addrDecWin.addrWin))) -+ { -+ /* Overlap detected */ -+ DB(mvOsPrintf("%s: ERR. Overlap detected\n", __FUNCTION__)); -+ return MV_ERROR; -+ } -+ -+ /* No Overlap. Enable address decode target window */ -+ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) -+ { -+ MV_REG_BIT_SET(XOR_WINDOW_CTRL_REG(unit,chan), -+ XEXWCR_WIN_EN_MASK(winNum)); -+ } -+ -+ } -+ else -+ { -+ /* Disable address decode target window */ -+ -+ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) -+ { -+ MV_REG_BIT_RESET(XOR_WINDOW_CTRL_REG(unit,chan), -+ XEXWCR_WIN_EN_MASK(winNum)); -+ } -+ -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvXorSetProtWinSet - Configure access attributes of a XOR engine -+* to one of the XOR memory windows. -+* -+* DESCRIPTION: -+* Each engine can be configured with access attributes for each of the -+* memory spaces. This function sets access attributes -+* to a given window for the given engine -+* -+* INPUTS: -+* chan - One of the possible engines. -+* winNum - One of the possible XOR memory spaces. -+* access - Protection access rights. -+* write - Write rights. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_STATUS mvXorProtWinSet (MV_U32 unit,MV_U32 chan, MV_U32 winNum, MV_BOOL access, -+ MV_BOOL write) -+{ -+ MV_U32 temp; -+ -+ /* Parameter checking */ -+ if (chan >= MV_XOR_MAX_CHAN_PER_UNIT) -+ { -+ DB(mvOsPrintf("%s: ERR. Invalid chan num %d\n", __FUNCTION__ , chan)); -+ return MV_BAD_PARAM; -+ } -+ if (winNum >= XOR_MAX_ADDR_DEC_WIN) -+ { -+ DB(mvOsPrintf("%s: ERR. Invalid win num %d\n", __FUNCTION__, winNum)); -+ return MV_BAD_PARAM; -+ } -+ -+ temp = MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,chan)) & -+ (~XEXWCR_WIN_ACC_MASK(winNum)); -+ -+ /* if access is disable */ -+ if (!access) -+ { -+ /* disable access */ -+ temp |= XEXWCR_WIN_ACC_NO_ACC(winNum); -+ } -+ /* if access is enable */ -+ else -+ { -+ /* if write is enable */ -+ if (write) -+ { -+ /* enable write */ -+ temp |= XEXWCR_WIN_ACC_RW(winNum); -+ } -+ /* if write is disable */ -+ else -+ { -+ /* disable write */ -+ temp |= XEXWCR_WIN_ACC_RO(winNum); -+ } -+ } -+ MV_REG_WRITE(XOR_WINDOW_CTRL_REG(unit,chan),temp); -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvXorPciRemap - Set XOR remap register for PCI address windows. -+* -+* DESCRIPTION: -+* only Windows 0-3 can be remapped. -+* -+* INPUT: -+* winNum - window number -+* pAddrDecWin - pointer to address space window structure -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_STATUS mvXorPciRemap(MV_U32 unit,MV_U32 winNum, MV_U32 addrHigh) -+{ -+ /* Parameter checking */ -+ if (winNum >= XOR_MAX_REMAP_WIN) -+ { -+ DB(mvOsPrintf("%s: ERR. Invalid win num %d\n", __FUNCTION__, winNum)); -+ return MV_BAD_PARAM; -+ } -+ -+ MV_REG_WRITE(XOR_HIGH_ADDR_REMAP_REG(unit,winNum), addrHigh); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* xorWinOverlapDetect - Detect XOR address windows overlaping -+* -+* DESCRIPTION: -+* An unpredicted behaviour is expected in case XOR address decode -+* windows overlaps. -+* This function detects XOR address decode windows overlaping of a -+* specified window. The function does not check the window itself for -+* overlaping. The function also skipps disabled address decode windows. -+* -+* INPUT: -+* winNum - address decode window number. -+* pAddrDecWin - An address decode window struct. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data -+* from registers. -+* -+*******************************************************************************/ -+static MV_STATUS xorWinOverlapDetect(MV_U32 unit,MV_U32 winNum, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 baseAddrEnableReg; -+ MV_U32 winNumIndex,chan; -+ MV_XOR_DEC_WIN addrDecWin; -+ -+ if (pAddrWin == NULL) -+ { -+ DB(mvOsPrintf("%s: ERR. pAddrWin is NULL pointer\n", __FUNCTION__ )); -+ return MV_BAD_PTR; -+ } -+ -+ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) -+ { -+ /* Read base address enable register. Do not check disabled windows */ -+ baseAddrEnableReg = MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,chan)); -+ -+ for (winNumIndex = 0; winNumIndex < XOR_MAX_ADDR_DEC_WIN; winNumIndex++) -+ { -+ /* Do not check window itself */ -+ if (winNumIndex == winNum) -+ { -+ continue; -+ } -+ -+ /* Do not check disabled windows */ -+ if ((baseAddrEnableReg & XEXWCR_WIN_EN_MASK(winNumIndex)) == 0) -+ { -+ continue; -+ } -+ -+ /* Get window parameters */ -+ if (MV_OK != mvXorTargetWinGet(unit,winNumIndex, &addrDecWin)) -+ { -+ DB(mvOsPrintf("%s: ERR. TargetWinGet failed\n", __FUNCTION__ )); -+ return MV_ERROR; -+ } -+ -+ if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin))) -+ { -+ return MV_TRUE; -+ } -+ } -+ } -+ -+ return MV_FALSE; -+} -+ -+static MV_VOID mvXorAddrDecShowUnit(MV_U32 unit) -+{ -+ MV_XOR_DEC_WIN win; -+ int i; -+ -+ mvOsOutput( "\n" ); -+ mvOsOutput( "XOR %d:\n", unit ); -+ mvOsOutput( "----\n" ); -+ -+ for( i = 0; i < XOR_MAX_ADDR_DEC_WIN; i++ ) -+ { -+ memset( &win, 0, sizeof(MV_XOR_DEC_WIN) ); -+ -+ mvOsOutput( "win%d - ", i ); -+ -+ if( mvXorTargetWinGet(unit, i, &win ) == MV_OK ) -+ { -+ if( win.enable ) -+ { -+ mvOsOutput( "%s base %x, ", -+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); -+ -+ mvSizePrint( win.addrWin.size ); -+ -+ mvOsOutput( "\n" ); -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ } -+ } -+} -+ -+/******************************************************************************* -+* mvXorAddrDecShow - Print the XOR address decode map. -+* -+* DESCRIPTION: -+* This function print the XOR address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvXorAddrDecShow(MV_VOID) -+{ -+ int i; -+ -+ for( i = 0; i < MV_XOR_MAX_UNIT; i++ ) -+ mvXorAddrDecShowUnit(i); -+ -+} -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.h 2010-11-09 20:28:10.062495382 +0100 -@@ -0,0 +1,140 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCMVSysXorh -+#define __INCMVSysXorh -+ -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+#include "ctrlEnv/sys/mvCpuIf.h" -+ -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+ -+#define XOR_MAX_ADDR_DEC_WIN 8 /* Maximum address decode windows */ -+#define XOR_MAX_REMAP_WIN 4 /* Maximum address arbiter windows */ -+ -+/* XOR Engine Address Decoding Register Map */ -+#define XOR_WINDOW_CTRL_REG(unit,chan) (XOR_UNIT_BASE(unit)+(0x240 + ((chan) * 4))) -+#define XOR_BASE_ADDR_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x250 + ((winNum) * 4))) -+#define XOR_SIZE_MASK_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x270 + ((winNum) * 4))) -+#define XOR_HIGH_ADDR_REMAP_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x290 + ((winNum) * 4))) -+ -+/* XOR Engine [0..1] Window Control Registers (XExWCR) */ -+#define XEXWCR_WIN_EN_OFFS(winNum) (winNum) -+#define XEXWCR_WIN_EN_MASK(winNum) (1 << (XEXWCR_WIN_EN_OFFS(winNum))) -+#define XEXWCR_WIN_EN_ENABLE(winNum) (1 << (XEXWCR_WIN_EN_OFFS(winNum))) -+#define XEXWCR_WIN_EN_DISABLE(winNum) (0 << (XEXWCR_WIN_EN_OFFS(winNum))) -+ -+#define XEXWCR_WIN_ACC_OFFS(winNum) ((2 * winNum) + 16) -+#define XEXWCR_WIN_ACC_MASK(winNum) (3 << (XEXWCR_WIN_ACC_OFFS(winNum))) -+#define XEXWCR_WIN_ACC_NO_ACC(winNum) (0 << (XEXWCR_WIN_ACC_OFFS(winNum))) -+#define XEXWCR_WIN_ACC_RO(winNum) (1 << (XEXWCR_WIN_ACC_OFFS(winNum))) -+#define XEXWCR_WIN_ACC_RW(winNum) (3 << (XEXWCR_WIN_ACC_OFFS(winNum))) -+ -+/* XOR Engine Base Address Registers (XEBARx) */ -+#define XEBARX_TARGET_OFFS (0) -+#define XEBARX_TARGET_MASK (0xF << XEBARX_TARGET_OFFS) -+#define XEBARX_ATTR_OFFS (8) -+#define XEBARX_ATTR_MASK (0xFF << XEBARX_ATTR_OFFS) -+#define XEBARX_BASE_OFFS (16) -+#define XEBARX_BASE_MASK (0xFFFF << XEBARX_BASE_OFFS) -+ -+/* XOR Engine Size Mask Registers (XESMRx) */ -+#define XESMRX_SIZE_MASK_OFFS (16) -+#define XESMRX_SIZE_MASK_MASK (0xFFFF << XESMRX_SIZE_MASK_OFFS) -+ -+/* XOR Engine High Address Remap Register (XEHARRx1) */ -+#define XEHARRX_REMAP_OFFS (0) -+#define XEHARRX_REMAP_MASK (0xFFFFFFFF << XEHARRX_REMAP_OFFS) -+ -+typedef struct _mvXorDecWin -+{ -+ MV_TARGET target; -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+}MV_XOR_DEC_WIN; -+ -+MV_STATUS mvXorInit (MV_VOID); -+MV_STATUS mvXorTargetWinSet(MV_U32 unit, MV_U32 winNum, -+ MV_XOR_DEC_WIN *pAddrDecWin); -+MV_STATUS mvXorTargetWinGet(MV_U32 unit, MV_U32 winNum, -+ MV_XOR_DEC_WIN *pAddrDecWin); -+MV_STATUS mvXorTargetWinEnable(MV_U32 unit, -+ MV_U32 winNum, MV_BOOL enable); -+MV_STATUS mvXorProtWinSet (MV_U32 unit,MV_U32 chan, MV_U32 winNum, MV_BOOL access, -+ MV_BOOL write); -+MV_STATUS mvXorPciRemap(MV_U32 unit, MV_U32 winNum, MV_U32 addrHigh); -+ -+MV_VOID mvXorAddrDecShow(MV_VOID); -+ -+#ifdef __cplusplus -+} -+#endif -+ -+#endif -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.c 2010-11-09 20:28:10.101392611 +0100 -@@ -0,0 +1,75 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "device/mvDevice.h" -+ -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.h 2010-11-09 20:28:10.141918633 +0100 -@@ -0,0 +1,74 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvDeviceH -+#define __INCmvDeviceH -+ -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+#include "device/mvDeviceRegs.h" -+ -+ -+#endif /* #ifndef __INCmvDeviceH */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDeviceRegs.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDeviceRegs.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDeviceRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDeviceRegs.h 2010-11-09 20:28:10.181250318 +0100 -@@ -0,0 +1,101 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvDeviceRegsH -+#define __INCmvDeviceRegsH -+ -+#ifndef MV_ASMLANGUAGE -+#include "ctrlEnv/mvCtrlEnvLib.h" -+/* This enumerator describes the Marvell controller possible devices that */ -+/* can be connected to its device interface. */ -+typedef enum _mvDevice -+{ -+#if defined(MV_INCLUDE_DEVICE_CS0) -+ DEV_CS0 = 0, /* Device connected to dev CS[0] */ -+#endif -+#if defined(MV_INCLUDE_DEVICE_CS1) -+ DEV_CS1 = 1, /* Device connected to dev CS[1] */ -+#endif -+#if defined(MV_INCLUDE_DEVICE_CS2) -+ DEV_CS2 = 2, /* Device connected to dev CS[2] */ -+#endif -+#if defined(MV_INCLUDE_DEVICE_CS3) -+ DEV_CS3 = 3, /* Device connected to dev CS[2] */ -+#endif -+#if defined(MV_INCLUDE_DEVICE_CS4) -+ DEV_CS4 = 4, /* Device connected to BOOT dev */ -+#endif -+ MV_DEV_MAX_CS = MV_DEVICE_MAX_CS -+}MV_DEVICE; -+ -+ -+#endif /* MV_ASMLANGUAGE */ -+ -+ -+#define NAND_CTRL_REG 0x10470 -+ -+#define NAND_ACTCEBOOT_BIT BIT1 -+ -+ -+#endif /* #ifndef __INCmvDeviceRegsH */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.c 2010-11-09 20:28:10.222495542 +0100 -@@ -0,0 +1,211 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+*******************************************************************************/ -+/******************************************************************************* -+* mvOsCpuArchLib.c - Marvell CPU architecture library -+* -+* DESCRIPTION: -+* This library introduce Marvell API for OS dependent CPU architecture -+* APIs. This library introduce single CPU architecture services APKI -+* cross OS. -+* -+* DEPENDENCIES: -+* None. -+* -+*******************************************************************************/ -+ -+/* includes */ -+#include -+#include "mvOs.h" -+ -+static MV_U32 read_p15_c0 (void); -+ -+/* defines */ -+#define ARM_ID_REVISION_OFFS 0 -+#define ARM_ID_REVISION_MASK (0xf << ARM_ID_REVISION_OFFS) -+ -+#define ARM_ID_PART_NUM_OFFS 4 -+#define ARM_ID_PART_NUM_MASK (0xfff << ARM_ID_PART_NUM_OFFS) -+ -+#define ARM_ID_ARCH_OFFS 16 -+#define ARM_ID_ARCH_MASK (0xf << ARM_ID_ARCH_OFFS) -+ -+#define ARM_ID_VAR_OFFS 20 -+#define ARM_ID_VAR_MASK (0xf << ARM_ID_VAR_OFFS) -+ -+#define ARM_ID_ASCII_OFFS 24 -+#define ARM_ID_ASCII_MASK (0xff << ARM_ID_ASCII_OFFS) -+ -+ -+ -+void* mvOsIoCachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, -+ MV_U32 *memHandle) -+{ -+ void *p = kmalloc( size, GFP_KERNEL ); -+ *pPhyAddr = pci_map_single( osHandle, p, 0, PCI_DMA_BIDIRECTIONAL ); -+ return p; -+} -+void* mvOsIoUncachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, -+ MV_U32 *memHandle) -+{ -+ return pci_alloc_consistent( osHandle, size, (dma_addr_t *)pPhyAddr ); -+} -+ -+void mvOsIoUncachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, -+ MV_U32 memHandle) -+{ -+ return pci_free_consistent( osHandle, size, pVirtAddr, (dma_addr_t)phyAddr ); -+} -+ -+void mvOsIoCachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, -+ MV_U32 memHandle ) -+{ -+ return kfree( pVirtAddr ); -+} -+ -+int mvOsRand(void) -+{ -+ int rand; -+ get_random_bytes(&rand, sizeof(rand) ); -+ return rand; -+} -+ -+/******************************************************************************* -+* mvOsCpuVerGet() - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit CPU Revision -+* -+*******************************************************************************/ -+MV_U32 mvOsCpuRevGet( MV_VOID ) -+{ -+ return ((read_p15_c0() & ARM_ID_REVISION_MASK ) >> ARM_ID_REVISION_OFFS); -+} -+/******************************************************************************* -+* mvOsCpuPartGet() - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit CPU Part number -+* -+*******************************************************************************/ -+MV_U32 mvOsCpuPartGet( MV_VOID ) -+{ -+ return ((read_p15_c0() & ARM_ID_PART_NUM_MASK ) >> ARM_ID_PART_NUM_OFFS); -+} -+/******************************************************************************* -+* mvOsCpuArchGet() - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit CPU Architicture number -+* -+*******************************************************************************/ -+MV_U32 mvOsCpuArchGet( MV_VOID ) -+{ -+ return ((read_p15_c0() & ARM_ID_ARCH_MASK ) >> ARM_ID_ARCH_OFFS); -+} -+/******************************************************************************* -+* mvOsCpuVarGet() - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit CPU Variant number -+* -+*******************************************************************************/ -+MV_U32 mvOsCpuVarGet( MV_VOID ) -+{ -+ return ((read_p15_c0() & ARM_ID_VAR_MASK ) >> ARM_ID_VAR_OFFS); -+} -+/******************************************************************************* -+* mvOsCpuAsciiGet() - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit CPU Variant number -+* -+*******************************************************************************/ -+MV_U32 mvOsCpuAsciiGet( MV_VOID ) -+{ -+ return ((read_p15_c0() & ARM_ID_ASCII_MASK ) >> ARM_ID_ASCII_OFFS); -+} -+ -+ -+ -+/* -+static unsigned long read_p15_c0 (void) -+*/ -+/* read co-processor 15, register #0 (ID register) */ -+static MV_U32 read_p15_c0 (void) -+{ -+ MV_U32 value; -+ -+ __asm__ __volatile__( -+ "mrc p15, 0, %0, c0, c0, 0 @ read control reg\n" -+ : "=r" (value) -+ : -+ : "memory"); -+ -+ return value; -+} -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h 2010-11-09 20:28:10.262495482 +0100 -@@ -0,0 +1,423 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+*******************************************************************************/ -+#ifndef _MV_OS_LNX_H_ -+#define _MV_OS_LNX_H_ -+ -+ -+#ifdef __KERNEL__ -+/* for kernel space */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "dbg-trace.h" -+ -+extern void mv_early_printk(char *fmt,...); -+ -+#define MV_ASM __asm__ __volatile__ -+#define INLINE inline -+#define MV_TRC_REC TRC_REC -+#define mvOsPrintf printk -+#define mvOsEarlyPrintf mv_early_printk -+#define mvOsOutput printk -+#define mvOsSPrintf sprintf -+#define mvOsMalloc(_size_) kmalloc(_size_,GFP_ATOMIC) -+#define mvOsFree kfree -+#define mvOsMemcpy memcpy -+#define mvOsSleep(_mils_) mdelay(_mils_) -+#define mvOsTaskLock() -+#define mvOsTaskUnlock() -+#define strtol simple_strtoul -+#define mvOsDelay(x) mdelay(x) -+#define mvOsUDelay(x) udelay(x) -+#define mvCopyFromOs copy_from_user -+#define mvCopyToOs copy_to_user -+ -+ -+#include "mvTypes.h" -+#include "mvCommon.h" -+ -+#ifdef MV_NDEBUG -+#define mvOsAssert(cond) -+#else -+#define mvOsAssert(cond) { do { if(!(cond)) { BUG(); } }while(0); } -+#endif /* MV_NDEBUG */ -+ -+#else /* __KERNEL__ */ -+ -+/* for user space applications */ -+#include -+#include -+#include -+#include -+ -+#define INLINE inline -+#define mvOsPrintf printf -+#define mvOsOutput printf -+#define mvOsMalloc(_size_) malloc(_size_) -+#define mvOsFree free -+#define mvOsAssert(cond) assert(cond) -+ -+#endif /* __KERNEL__ */ -+#define mvOsIoVirtToPhy(pDev, pVirtAddr) \ -+ pci_map_single( (pDev), (pVirtAddr), 0, PCI_DMA_BIDIRECTIONAL ) -+ -+#define mvOsCacheClear(pDev, p, size ) \ -+ pci_map_single( (pDev), (p), (size), PCI_DMA_BIDIRECTIONAL) -+ -+#define mvOsCacheFlush(pDev, p, size ) \ -+ pci_map_single( (pDev), (p), (size), PCI_DMA_TODEVICE) -+ -+#define mvOsCacheInvalidate(pDev, p, size) \ -+ pci_map_single( (pDev), (p), (size), PCI_DMA_FROMDEVICE ) -+ -+#define mvOsCacheUnmap(pDev, phys, size) \ -+ pci_unmap_single( (pDev), (dma_addr_t)(phys), (size), PCI_DMA_FROMDEVICE ) -+ -+ -+#define CPU_PHY_MEM(x) (MV_U32)x -+#define CPU_MEMIO_CACHED_ADDR(x) (void*)x -+#define CPU_MEMIO_UNCACHED_ADDR(x) (void*)x -+ -+ -+/* CPU architecture dependent 32, 16, 8 bit read/write IO addresses */ -+#define MV_MEMIO32_WRITE(addr, data) \ -+ ((*((volatile unsigned int*)(addr))) = ((unsigned int)(data))) -+ -+#define MV_MEMIO32_READ(addr) \ -+ ((*((volatile unsigned int*)(addr)))) -+ -+#define MV_MEMIO16_WRITE(addr, data) \ -+ ((*((volatile unsigned short*)(addr))) = ((unsigned short)(data))) -+ -+#define MV_MEMIO16_READ(addr) \ -+ ((*((volatile unsigned short*)(addr)))) -+ -+#define MV_MEMIO8_WRITE(addr, data) \ -+ ((*((volatile unsigned char*)(addr))) = ((unsigned char)(data))) -+ -+#define MV_MEMIO8_READ(addr) \ -+ ((*((volatile unsigned char*)(addr)))) -+ -+ -+/* No Fast Swap implementation (in assembler) for ARM */ -+#define MV_32BIT_LE_FAST(val) MV_32BIT_LE(val) -+#define MV_16BIT_LE_FAST(val) MV_16BIT_LE(val) -+#define MV_32BIT_BE_FAST(val) MV_32BIT_BE(val) -+#define MV_16BIT_BE_FAST(val) MV_16BIT_BE(val) -+ -+/* 32 and 16 bit read/write in big/little endian mode */ -+ -+/* 16bit write in little endian mode */ -+#define MV_MEMIO_LE16_WRITE(addr, data) \ -+ MV_MEMIO16_WRITE(addr, MV_16BIT_LE_FAST(data)) -+ -+/* 16bit read in little endian mode */ -+static __inline MV_U16 MV_MEMIO_LE16_READ(MV_U32 addr) -+{ -+ MV_U16 data; -+ -+ data= (MV_U16)MV_MEMIO16_READ(addr); -+ -+ return (MV_U16)MV_16BIT_LE_FAST(data); -+} -+ -+/* 32bit write in little endian mode */ -+#define MV_MEMIO_LE32_WRITE(addr, data) \ -+ MV_MEMIO32_WRITE(addr, MV_32BIT_LE_FAST(data)) -+ -+/* 32bit read in little endian mode */ -+static __inline MV_U32 MV_MEMIO_LE32_READ(MV_U32 addr) -+{ -+ MV_U32 data; -+ -+ data= (MV_U32)MV_MEMIO32_READ(addr); -+ -+ return (MV_U32)MV_32BIT_LE_FAST(data); -+} -+ -+static __inline void mvOsBCopy(char* srcAddr, char* dstAddr, int byteCount) -+{ -+ while(byteCount != 0) -+ { -+ *dstAddr = *srcAddr; -+ dstAddr++; -+ srcAddr++; -+ byteCount--; -+ } -+} -+ -+static INLINE MV_U64 mvOsDivMod64(MV_U64 divided, MV_U64 divisor, MV_U64* modulu) -+{ -+ MV_U64 division = 0; -+ -+ if(divisor == 1) -+ return divided; -+ -+ while(divided >= divisor) -+ { -+ division++; -+ divided -= divisor; -+ } -+ if (modulu != NULL) -+ *modulu = divided; -+ -+ return division; -+} -+ -+#if defined(MV_BRIDGE_SYNC_REORDER) -+extern MV_U32 *mvUncachedParam; -+ -+static __inline void mvOsBridgeReorderWA(void) -+{ -+ volatile MV_U32 val = 0; -+ -+ val = mvUncachedParam[0]; -+} -+#endif -+ -+ -+/* Flash APIs */ -+#define MV_FL_8_READ MV_MEMIO8_READ -+#define MV_FL_16_READ MV_MEMIO_LE16_READ -+#define MV_FL_32_READ MV_MEMIO_LE32_READ -+#define MV_FL_8_DATA_READ MV_MEMIO8_READ -+#define MV_FL_16_DATA_READ MV_MEMIO16_READ -+#define MV_FL_32_DATA_READ MV_MEMIO32_READ -+#define MV_FL_8_WRITE MV_MEMIO8_WRITE -+#define MV_FL_16_WRITE MV_MEMIO_LE16_WRITE -+#define MV_FL_32_WRITE MV_MEMIO_LE32_WRITE -+#define MV_FL_8_DATA_WRITE MV_MEMIO8_WRITE -+#define MV_FL_16_DATA_WRITE MV_MEMIO16_WRITE -+#define MV_FL_32_DATA_WRITE MV_MEMIO32_WRITE -+ -+ -+/* CPU cache information */ -+#define CPU_I_CACHE_LINE_SIZE 32 /* 2do: replace 32 with linux core macro */ -+#define CPU_D_CACHE_LINE_SIZE 32 /* 2do: replace 32 with linux core macro */ -+ -+#ifdef CONFIG_L2_CACHE_ENABLE -+/* Data cache flush one line */ -+#define mvOsCacheLineFlushInv(handle, addr) \ -+{ \ -+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c14, 1" : : "r" (addr));\ -+ __asm__ __volatile__ ("mcr p15, 1, %0, c15, c10, 1" : : "r" (addr));\ -+ __asm__ __volatile__ ("mcr p15, 0, r0, c7, c10, 4"); \ -+} -+ -+#else -+ -+/* Data cache flush one line */ -+#define mvOsCacheLineFlushInv(handle, addr) \ -+{ \ -+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c14, 1" : : "r" (addr));\ -+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" : : "r" (addr)); \ -+} -+#endif -+ -+#ifdef CONFIG_L2_CACHE_ENABLE -+#define mvOsCacheLineInv(handle,addr) \ -+{ \ -+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c6, 1" : : "r" (addr)); \ -+ __asm__ __volatile__ ("mcr p15, 1, %0, c15, c11, 1" : : "r" (addr)); \ -+} -+#else -+#define mvOsCacheLineInv(handle,addr) \ -+{ \ -+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c6, 1" : : "r" (addr)); \ -+} -+#endif -+ -+#ifdef CONFIG_L2_CACHE_ENABLE -+/* Data cache flush one line */ -+#define mvOsCacheLineFlush(handle, addr) \ -+{ \ -+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 1" : : "r" (addr));\ -+ __asm__ __volatile__ ("mcr p15, 1, %0, c15, c9, 1" : : "r" (addr));\ -+ __asm__ __volatile__ ("mcr p15, 0, r0, c7, c10, 4"); \ -+} -+ -+#else -+/* Data cache flush one line */ -+#define mvOsCacheLineFlush(handle, addr) \ -+{ \ -+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 1" : : "r" (addr));\ -+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" : : "r" (addr)); \ -+} -+#endif -+ -+static __inline void mvOsPrefetch(const void *ptr) -+{ -+#ifdef CONFIG_USE_DSP -+ __asm__ __volatile__( -+ "pld\t%0" -+ : -+ : "o" (*(char *)ptr) -+ : "cc"); -+#else -+ return; -+#endif -+} -+ -+ -+/* Flush CPU pipe */ -+#define CPU_PIPE_FLUSH -+ -+ -+ -+ -+ -+/* register manipulations */ -+ -+/****************************************************************************** -+* This debug function enable the write of each register that u-boot access to -+* to an array in the DRAM, the function record only MV_REG_WRITE access. -+* The function could not be operate when booting from flash. -+* In order to print the array we use the printreg command. -+******************************************************************************/ -+/* #define REG_DEBUG */ -+#if defined(REG_DEBUG) -+extern int reg_arry[2048][2]; -+extern int reg_arry_index; -+#endif -+ -+/* Marvell controller register read/write macros */ -+#define MV_REG_VALUE(offset) \ -+ (MV_MEMIO32_READ((INTER_REGS_BASE | (offset)))) -+ -+#define MV_REG_READ(offset) \ -+ (MV_MEMIO_LE32_READ(INTER_REGS_BASE | (offset))) -+ -+#if defined(REG_DEBUG) -+#define MV_REG_WRITE(offset, val) \ -+ MV_MEMIO_LE32_WRITE((INTER_REGS_BASE | (offset)), (val)); \ -+ { \ -+ reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\ -+ reg_arry[reg_arry_index][1] = (val);\ -+ reg_arry_index++;\ -+ } -+#else -+#define MV_REG_WRITE(offset, val) \ -+ MV_MEMIO_LE32_WRITE((INTER_REGS_BASE | (offset)), (val)); -+#endif -+ -+#define MV_REG_BYTE_READ(offset) \ -+ (MV_MEMIO8_READ((INTER_REGS_BASE | (offset)))) -+ -+#if defined(REG_DEBUG) -+#define MV_REG_BYTE_WRITE(offset, val) \ -+ MV_MEMIO8_WRITE((INTER_REGS_BASE | (offset)), (val)); \ -+ { \ -+ reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\ -+ reg_arry[reg_arry_index][1] = (val);\ -+ reg_arry_index++;\ -+ } -+#else -+#define MV_REG_BYTE_WRITE(offset, val) \ -+ MV_MEMIO8_WRITE((INTER_REGS_BASE | (offset)), (val)) -+#endif -+ -+#if defined(REG_DEBUG) -+#define MV_REG_BIT_SET(offset, bitMask) \ -+ (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ -+ (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) | \ -+ MV_32BIT_LE_FAST(bitMask)))); \ -+ { \ -+ reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\ -+ reg_arry[reg_arry_index][1] = (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)));\ -+ reg_arry_index++;\ -+ } -+#else -+#define MV_REG_BIT_SET(offset, bitMask) \ -+ (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ -+ (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) | \ -+ MV_32BIT_LE_FAST(bitMask)))) -+#endif -+ -+#if defined(REG_DEBUG) -+#define MV_REG_BIT_RESET(offset,bitMask) \ -+ (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ -+ (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) & \ -+ MV_32BIT_LE_FAST(~bitMask)))); \ -+ { \ -+ reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\ -+ reg_arry[reg_arry_index][1] = (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)));\ -+ reg_arry_index++;\ -+ } -+#else -+#define MV_REG_BIT_RESET(offset,bitMask) \ -+ (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ -+ (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) & \ -+ MV_32BIT_LE_FAST(~bitMask)))) -+#endif -+ -+ -+ -+/* ARM architecture APIs */ -+MV_U32 mvOsCpuRevGet (MV_VOID); -+MV_U32 mvOsCpuPartGet (MV_VOID); -+MV_U32 mvOsCpuArchGet (MV_VOID); -+MV_U32 mvOsCpuVarGet (MV_VOID); -+MV_U32 mvOsCpuAsciiGet (MV_VOID); -+ -+/* Other APIs */ -+void* mvOsIoCachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, MV_U32 *memHandle); -+void* mvOsIoUncachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, MV_U32 *memHandle ); -+void mvOsIoUncachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, MV_U32 memHandle ); -+void mvOsIoCachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, MV_U32 memHandle ); -+int mvOsRand(void); -+ -+#endif /* _MV_OS_LNX_H_ */ -+ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOsSata.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/linux_oss/mvOsSata.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOsSata.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/linux_oss/mvOsSata.h 2010-11-09 20:28:10.302495426 +0100 -@@ -0,0 +1,158 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+*******************************************************************************/ -+/******************************************************************************* -+* mvOsLinux.h - O.S. interface header file for Linux -+* -+* DESCRIPTION: -+* This header file contains OS dependent definition under Linux -+* -+* DEPENDENCIES: -+* Linux kernel header files. -+* -+* FILE REVISION NUMBER: -+* $Revision: 1.1 $ -+*******************************************************************************/ -+ -+#ifndef __INCmvOsLinuxh -+#define __INCmvOsLinuxh -+ -+/* Includes */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include "mvOs.h" -+ -+ -+/* Definitions */ -+#define MV_DEFAULT_QUEUE_DEPTH 2 -+#define MV_SATA_SUPPORT_EDMA_SINGLE_DATA_REGION -+#define MV_SATA_SUPPORT_GEN2E_128_QUEUE_LEN -+ -+#ifdef CONFIG_MV88F6082 -+ #define MV_SATA_OVERRIDE_SW_QUEUE_SIZE -+ #define MV_SATA_REQUESTED_SW_QUEUE_SIZE 2 -+ #undef MV_SATA_SUPPORT_GEN2E_128_QUEUE_LEN -+#endif -+ -+/* System dependent macro for flushing CPU write cache */ -+#if defined (MV_BRIDGE_SYNC_REORDER) -+#define MV_CPU_WRITE_BUFFER_FLUSH() do { \ -+ wmb(); \ -+ mvOsBridgeReorderWA(); \ -+ } while (0) -+#else -+#define MV_CPU_WRITE_BUFFER_FLUSH() wmb() -+#endif /* CONFIG_MV78XX0 */ -+ -+/* System dependent little endian from / to CPU conversions */ -+#define MV_CPU_TO_LE16(x) cpu_to_le16(x) -+#define MV_CPU_TO_LE32(x) cpu_to_le32(x) -+ -+#define MV_LE16_TO_CPU(x) le16_to_cpu(x) -+#define MV_LE32_TO_CPU(x) le32_to_cpu(x) -+ -+#ifdef __BIG_ENDIAN_BITFIELD -+#define MV_BIG_ENDIAN_BITFIELD -+#endif -+ -+/* System dependent register read / write in byte/word/dword variants */ -+#define MV_REG_WRITE_BYTE(base, offset, val) writeb(val, base + offset) -+#define MV_REG_WRITE_WORD(base, offset, val) writew(val, base + offset) -+#define MV_REG_WRITE_DWORD(base, offset, val) writel(val, base + offset) -+#define MV_REG_READ_BYTE(base, offset) readb(base + offset) -+#define MV_REG_READ_WORD(base, offset) readw(base + offset) -+#define MV_REG_READ_DWORD(base, offset) readl(base + offset) -+ -+ -+/* Typedefs */ -+ -+/* System dependant typedefs */ -+typedef void *MV_VOID_PTR; -+typedef u32 *MV_U32_PTR; -+typedef u16 *MV_U16_PTR; -+typedef u8 *MV_U8_PTR; -+typedef char *MV_CHAR_PTR; -+typedef void *MV_BUS_ADDR_T; -+typedef unsigned long MV_CPU_FLAGS; -+ -+ -+/* Structures */ -+/* System dependent structure */ -+typedef struct mvOsSemaphore -+{ -+ int notUsed; -+} MV_OS_SEMAPHORE; -+ -+ -+/* Functions (User implemented)*/ -+ -+/* Semaphore init, take and release */ -+#define mvOsSemInit(x) MV_TRUE -+#define mvOsSemTake(x) -+#define mvOsSemRelease(x) -+ -+/* Interrupt masking and unmasking functions */ -+MV_CPU_FLAGS mvOsSaveFlagsAndMaskCPUInterrupts(MV_VOID); -+MV_VOID mvOsRestoreFlags(MV_CPU_FLAGS); -+ -+/* Delay function in micro seconds resolution */ -+void mvMicroSecondsDelay(MV_VOID_PTR, MV_U32); -+ -+/* Typedefs */ -+typedef enum mvBoolean -+{ -+ MV_SFALSE, MV_STRUE -+} MV_BOOLEAN; -+ -+/* System logging function */ -+#include "mvLog.h" -+/* Enable READ/WRITE Long SCSI command only when driver is compiled for debugging */ -+#ifdef MV_LOGGER -+#define MV_SATA_SUPPORT_READ_WRITE_LONG -+#endif -+ -+#define MV_IAL_LOG_ID 3 -+ -+#endif /* __INCmvOsLinuxh */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.c 2010-11-09 20:28:10.342495568 +0100 -@@ -0,0 +1,376 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "mvCntmr.h" -+#include "cpu/mvCpu.h" -+ -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+extern unsigned int whoAmI(void); -+ -+/******************************************************************************* -+* mvCntmrLoad - -+* -+* DESCRIPTION: -+* Load an init Value to a given counter/timer -+* -+* INPUT: -+* countNum - counter number -+* value - value to be loaded -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess -+*******************************************************************************/ -+MV_STATUS mvCntmrLoad(MV_U32 countNum, MV_U32 value) -+{ -+ if (countNum >= MV_CNTMR_MAX_COUNTER ) -+ { -+ -+ mvOsPrintf(("mvCntmrLoad: Err. Illigal counter number \n")); -+ return MV_BAD_PARAM;; -+ -+ } -+ -+ MV_REG_WRITE(CNTMR_RELOAD_REG(countNum),value); -+ MV_REG_WRITE(CNTMR_VAL_REG(countNum),value); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCntmrRead - -+* -+* DESCRIPTION: -+* Returns the value of the given Counter/Timer -+* -+* INPUT: -+* countNum - counter number -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_U32 counter value -+*******************************************************************************/ -+MV_U32 mvCntmrRead(MV_U32 countNum) -+{ -+ return MV_REG_READ(CNTMR_VAL_REG(countNum)); -+} -+ -+/******************************************************************************* -+* mvCntmrWrite - -+* -+* DESCRIPTION: -+* Returns the value of the given Counter/Timer -+* -+* INPUT: -+* countNum - counter number -+* countVal - value to write -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None -+*******************************************************************************/ -+void mvCntmrWrite(MV_U32 countNum,MV_U32 countVal) -+{ -+ MV_REG_WRITE(CNTMR_VAL_REG(countNum),countVal); -+} -+ -+/******************************************************************************* -+* mvCntmrCtrlSet - -+* -+* DESCRIPTION: -+* Set the Control to a given counter/timer -+* -+* INPUT: -+* countNum - counter number -+* pCtrl - pointer to MV_CNTMR_CTRL structure -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess -+*******************************************************************************/ -+MV_STATUS mvCntmrCtrlSet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl) -+{ -+ MV_U32 cntmrCtrl; -+ -+ if (countNum >= MV_CNTMR_MAX_COUNTER ) -+ { -+ -+ DB(mvOsPrintf(("mvCntmrCtrlSet: Err. Illigal counter number \n"))); -+ return MV_BAD_PARAM;; -+ -+ } -+ -+ /* read control register */ -+ cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG); -+ -+ -+ if (pCtrl->enable) /* enable counter\timer */ -+ { -+ cntmrCtrl |= CTCR_ARM_TIMER_EN(countNum); -+ } -+ else /* disable counter\timer */ -+ { -+ cntmrCtrl &= ~CTCR_ARM_TIMER_EN(countNum); -+ } -+ -+ if ( pCtrl->autoEnable ) /* Auto mode */ -+ { -+ cntmrCtrl |= CTCR_ARM_TIMER_AUTO_EN(countNum); -+ -+ } -+ else /* no auto mode */ -+ { -+ cntmrCtrl &= ~CTCR_ARM_TIMER_AUTO_EN(countNum); -+ } -+ -+ MV_REG_WRITE(CNTMR_CTRL_REG,cntmrCtrl); -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvCntmrCtrlGet - -+* -+* DESCRIPTION: -+* Get the Control value of a given counter/timer -+* -+* INPUT: -+* countNum - counter number -+* pCtrl - pointer to MV_CNTMR_CTRL structure -+* -+* OUTPUT: -+* Counter\Timer control value -+* -+* RETURN: -+* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess -+*******************************************************************************/ -+MV_STATUS mvCntmrCtrlGet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl) -+{ -+ MV_U32 cntmrCtrl; -+ -+ if (countNum >= MV_CNTMR_MAX_COUNTER ) -+ { -+ DB(mvOsPrintf(("mvCntmrCtrlGet: Err. Illigal counter number \n"))); -+ return MV_BAD_PARAM;; -+ } -+ -+ /* read control register */ -+ cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG); -+ -+ /* enable counter\timer */ -+ if (cntmrCtrl & CTCR_ARM_TIMER_EN(countNum)) -+ { -+ pCtrl->enable = MV_TRUE; -+ } -+ else -+ { -+ pCtrl->enable = MV_FALSE; -+ } -+ -+ /* counter mode */ -+ if (cntmrCtrl & CTCR_ARM_TIMER_AUTO_EN(countNum)) -+ { -+ pCtrl->autoEnable = MV_TRUE; -+ } -+ else -+ { -+ pCtrl->autoEnable = MV_FALSE; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCntmrEnable - -+* -+* DESCRIPTION: -+* Set the Enable-Bit to logic '1' ==> starting the counter -+* -+* INPUT: -+* countNum - counter number -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess -+*******************************************************************************/ -+MV_STATUS mvCntmrEnable(MV_U32 countNum) -+{ -+ MV_U32 cntmrCtrl; -+ -+ if (countNum >= MV_CNTMR_MAX_COUNTER ) -+ { -+ -+ DB(mvOsPrintf(("mvCntmrEnable: Err. Illigal counter number \n"))); -+ return MV_BAD_PARAM;; -+ -+ } -+ -+ /* read control register */ -+ cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG); -+ -+ /* enable counter\timer */ -+ cntmrCtrl |= CTCR_ARM_TIMER_EN(countNum); -+ -+ -+ MV_REG_WRITE(CNTMR_CTRL_REG,cntmrCtrl); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCntmrDisable - -+* -+* DESCRIPTION: -+* Stop the counter/timer running, and returns its Value -+* -+* INPUT: -+* countNum - counter number -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_U32 counter\timer value -+*******************************************************************************/ -+MV_STATUS mvCntmrDisable(MV_U32 countNum) -+{ -+ MV_U32 cntmrCtrl; -+ -+ if (countNum >= MV_CNTMR_MAX_COUNTER ) -+ { -+ -+ DB(mvOsPrintf(("mvCntmrDisable: Err. Illigal counter number \n"))); -+ return MV_BAD_PARAM;; -+ -+ } -+ -+ /* read control register */ -+ cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG); -+ -+ /* disable counter\timer */ -+ cntmrCtrl &= ~CTCR_ARM_TIMER_EN(countNum); -+ -+ MV_REG_WRITE(CNTMR_CTRL_REG,cntmrCtrl); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCntmrStart - -+* -+* DESCRIPTION: -+* Combined all the sub-operations above to one function: Load,setMode,Enable -+* -+* INPUT: -+* countNum - counter number -+* value - value of the counter\timer to be set -+* pCtrl - pointer to MV_CNTMR_CTRL structure -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess -+*******************************************************************************/ -+MV_STATUS mvCntmrStart(MV_U32 countNum, MV_U32 value, -+ MV_CNTMR_CTRL *pCtrl) -+{ -+ -+ if (countNum >= MV_CNTMR_MAX_COUNTER ) -+ { -+ -+ mvOsPrintf(("mvCntmrDisable: Err. Illigal counter number \n")); -+ return MV_BAD_PARAM;; -+ -+ } -+ -+ /* load value onto counter\timer */ -+ mvCntmrLoad(countNum,value); -+ -+ /* set the counter to load in the first time */ -+ mvCntmrWrite(countNum,value); -+ -+ /* set control for timer \ cunter and enable */ -+ mvCntmrCtrlSet(countNum,pCtrl); -+ -+ return MV_OK; -+} -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.h 2010-11-09 20:28:10.381238003 +0100 -@@ -0,0 +1,121 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvTmrWtdgh -+#define __INCmvTmrWtdgh -+ -+/* includes */ -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "cntmr/mvCntmrRegs.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+ -+ -+/* This enumerator describe counters\watchdog numbers */ -+typedef enum _mvCntmrID -+{ -+ TIMER0 = 0, -+ TIMER1, -+ WATCHDOG, -+ TIMER2, -+ TIMER3, -+}MV_CNTMR_ID; -+ -+ -+/* Counter / Timer control structure */ -+typedef struct _mvCntmrCtrl -+{ -+ MV_BOOL enable; /* enable */ -+ MV_BOOL autoEnable; /* counter/Timer */ -+}MV_CNTMR_CTRL; -+ -+ -+/* Functions */ -+ -+/* Load an init Value to a given counter/timer */ -+MV_STATUS mvCntmrLoad(MV_U32 countNum, MV_U32 value); -+ -+/* Returns the value of the given Counter/Timer */ -+MV_U32 mvCntmrRead(MV_U32 countNum); -+ -+/* Write a value of the given Counter/Timer */ -+void mvCntmrWrite(MV_U32 countNum,MV_U32 countVal); -+ -+/* Set the Control to a given counter/timer */ -+MV_STATUS mvCntmrCtrlSet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl); -+ -+/* Get the value of a given counter/timer */ -+MV_STATUS mvCntmrCtrlGet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl); -+ -+/* Set the Enable-Bit to logic '1' ==> starting the counter. */ -+MV_STATUS mvCntmrEnable(MV_U32 countNum); -+ -+/* Stop the counter/timer running, and returns its Value. */ -+MV_STATUS mvCntmrDisable(MV_U32 countNum); -+ -+/* Combined all the sub-operations above to one function: Load,setMode,Enable */ -+MV_STATUS mvCntmrStart(MV_U32 countNum, MV_U32 value, -+ MV_CNTMR_CTRL *pCtrl); -+ -+#endif /* __INCmvTmrWtdgh */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmrRegs.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmrRegs.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmrRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmrRegs.h 2010-11-09 20:28:10.422495568 +0100 -@@ -0,0 +1,121 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvTmrwtdgRegsh -+#define __INCmvTmrwtdgRegsh -+ -+/*******************************************/ -+/* ARM Timers Registers Map */ -+/*******************************************/ -+ -+#define CNTMR_RELOAD_REG(tmrNum) (CNTMR_BASE + 0x10 + (tmrNum)*8 + \ -+ (((tmrNum) <= 3)?0:8)) -+#define CNTMR_VAL_REG(tmrNum) (CNTMR_BASE + 0x14 + (tmrNum)*8 + \ -+ (((tmrNum) <= 3)?0:8)) -+#define CNTMR_CTRL_REG (CNTMR_BASE) -+ -+/*For MV78XX0*/ -+#define CNTMR_CAUSE_REG (CPU_AHB_MBUS_CAUSE_INT_REG(whoAmI())) -+#define CNTMR_MASK_REG (CPU_AHB_MBUS_MASK_INT_REG(whoAmI())) -+ -+/* ARM Timers Registers Map */ -+/*******************************************/ -+ -+ -+/* ARM Timers Control Register */ -+/* CPU_TIMERS_CTRL_REG (CTCR) */ -+ -+#define TIMER0_NUM 0 -+#define TIMER1_NUM 1 -+#define WATCHDOG_NUM 2 -+#define TIMER2_NUM 3 -+#define TIMER3_NUM 4 -+ -+#define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2) -+#define CTCR_ARM_TIMER_EN_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS) -+#define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr)) -+#define CTCR_ARM_TIMER_DIS(cntr) (0 << CTCR_ARM_TIMER_EN_OFFS(cntr)) -+ -+#define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1) -+#define CTCR_ARM_TIMER_AUTO_MASK(cntr) BIT1 -+#define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) -+#define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) -+ -+ -+/* ARM Timer\Watchdog Reload Register */ -+/* CNTMR_RELOAD_REG (TRR) */ -+ -+#define TRG_ARM_TIMER_REL_OFFS 0 -+#define TRG_ARM_TIMER_REL_MASK 0xffffffff -+ -+/* ARM Timer\Watchdog Register */ -+/* CNTMR_VAL_REG (TVRG) */ -+ -+#define TVR_ARM_TIMER_OFFS 0 -+#define TVR_ARM_TIMER_MASK 0xffffffff -+#define TVR_ARM_TIMER_MAX 0xffffffff -+ -+ -+ -+#endif /* __INCmvTmrwtdgRegsh */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c 2010-11-09 20:28:10.462495409 +0100 -@@ -0,0 +1,207 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include "mvOs.h" -+#include "mvCpuCntrs.h" -+ -+ -+const static MV_CPU_CNTRS_OPS mvCpuCntrsOpsTbl[MV_CPU_CNTRS_NUM][MV_CPU_CNTRS_OPS_NUM] = -+{ -+ /*0*/ -+ { -+ MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_DCACHE_READ_HIT, MV_CPU_CNTRS_DCACHE_READ_MISS, -+ MV_CPU_CNTRS_DCACHE_WRITE_HIT, MV_CPU_CNTRS_DCACHE_WRITE_MISS, MV_CPU_CNTRS_INSTRUCTIONS, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, -+ MV_CPU_CNTRS_MMU_READ_LATENCY, MV_CPU_CNTRS_ICACHE_READ_LATENCY, MV_CPU_CNTRS_WB_WRITE_LATENCY, -+ MV_CPU_CNTRS_LDM_STM_HOLD, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, -+ MV_CPU_CNTRS_DATA_WRITE_ACCESS, MV_CPU_CNTRS_DATA_READ_ACCESS, MV_CPU_CNTRS_INVALID, -+ MV_CPU_CNTRS_BRANCH_PREDICT_COUNT, -+ }, -+ /*1*/ -+ { -+ MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_ICACHE_READ_MISS, MV_CPU_CNTRS_DCACHE_READ_MISS, -+ MV_CPU_CNTRS_DCACHE_WRITE_MISS, MV_CPU_CNTRS_ITLB_MISS, MV_CPU_CNTRS_SINGLE_ISSUE, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BRANCH_RETIRED, MV_CPU_CNTRS_INVALID, -+ MV_CPU_CNTRS_MMU_READ_BEAT, MV_CPU_CNTRS_ICACHE_READ_LATENCY, MV_CPU_CNTRS_WB_WRITE_BEAT, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_IS_HOLD, MV_CPU_CNTRS_DATA_READ_ACCESS, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, -+ MV_CPU_CNTRS_INVALID, -+ }, -+ /*2*/ -+ { -+ MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DCACHE_ACCESS, -+ MV_CPU_CNTRS_DTLB_MISS, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BRANCH_PREDICT_MISS, MV_CPU_CNTRS_WB_WRITE_BEAT, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DCACHE_READ_LATENCY, MV_CPU_CNTRS_DCACHE_WRITE_LATENCY, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BIU_SIMULT_ACCESS, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, -+ MV_CPU_CNTRS_INVALID, -+ }, -+ /*3*/ -+ { -+ MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_DCACHE_READ_MISS, MV_CPU_CNTRS_DCACHE_WRITE_MISS, -+ MV_CPU_CNTRS_TLB_MISS, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BRANCH_TAKEN, MV_CPU_CNTRS_WB_FULL_CYCLES, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DCACHE_READ_BEAT, MV_CPU_CNTRS_DCACHE_WRITE_BEAT, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BIU_ANY_ACCESS, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DATA_WRITE_ACCESS, -+ MV_CPU_CNTRS_INVALID, -+ } -+}; -+ -+MV_CPU_CNTRS_ENTRY mvCpuCntrsTbl[MV_CPU_CNTRS_NUM]; -+ -+MV_CPU_CNTRS_EVENT* mvCpuCntrsEventTbl[128]; -+ -+void mvCpuCntrsReset(void) -+{ -+ MV_U32 reg = 0; -+ -+ MV_ASM ("mcr p15, 0, %0, c15, c13, 0" : : "r" (reg)); -+ MV_ASM ("mcr p15, 0, %0, c15, c13, 1" : : "r" (reg)); -+ MV_ASM ("mcr p15, 0, %0, c15, c13, 2" : : "r" (reg)); -+ MV_ASM ("mcr p15, 0, %0, c15, c13, 3" : : "r" (reg)); -+ MV_ASM ("mcr p15, 0, %0, c15, c13, 4" : : "r" (reg)); -+ MV_ASM ("mcr p15, 0, %0, c15, c13, 5" : : "r" (reg)); -+ MV_ASM ("mcr p15, 0, %0, c15, c13, 6" : : "r" (reg)); -+ MV_ASM ("mcr p15, 0, %0, c15, c13, 7" : : "r" (reg)); -+} -+ -+void program_counter(int counter, int op) -+{ -+ MV_U32 reg = (1 << op) | 0x1; /*enable*/ -+ -+ switch(counter) -+ { -+ case 0: -+ __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 0" : : "r" (reg)); -+ return; -+ -+ case 1: -+ __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 1" : : "r" (reg)); -+ return; -+ -+ case 2: -+ __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 2" : : "r" (reg)); -+ return; -+ -+ case 3: -+ __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 3" : : "r" (reg)); -+ return; -+ -+ default: -+ mvOsPrintf("error in program_counter: bad counter number (%d)\n", counter); -+ } -+ return; -+} -+ -+void mvCpuCntrsEventClear(MV_CPU_CNTRS_EVENT* pEvent) -+{ -+ int i; -+ -+ for(i=0; icounters_sum[i] = 0; -+ } -+ pEvent->num_of_measurements = 0; -+} -+ -+ -+MV_CPU_CNTRS_EVENT* mvCpuCntrsEventCreate(char* name, MV_U32 print_threshold) -+{ -+ int i; -+ MV_CPU_CNTRS_EVENT* event = mvOsMalloc(sizeof(MV_CPU_CNTRS_EVENT)); -+ -+ if(event) -+ { -+ strncpy(event->name, name, sizeof(event->name)); -+ event->num_of_measurements = 0; -+ event->avg_sample_count = print_threshold; -+ for(i=0; icounters_before[i] = 0; -+ event->counters_after[i] = 0; -+ event->counters_sum[i] = 0; -+ } -+ } -+ return event; -+} -+ -+void mvCpuCntrsEventDelete(MV_CPU_CNTRS_EVENT* event) -+{ -+ if(event != NULL) -+ mvOsFree(event); -+} -+ -+ -+MV_STATUS mvCpuCntrsProgram(int counter, MV_CPU_CNTRS_OPS op, -+ char* name, MV_U32 overhead) -+{ -+ int i; -+ -+ /* Find required operations */ -+ for(i=0; inum_of_measurements < pEvent->avg_sample_count) -+ return; -+ -+ mvOsPrintf("%16s: ", pEvent->name); -+ for(i=0; icounters_sum[i], -+ pEvent->num_of_measurements, NULL); -+ if(counters_avg >= mvCpuCntrsTbl[i].overhead) -+ counters_avg -= mvCpuCntrsTbl[i].overhead; -+ else -+ counters_avg = 0; -+ -+ mvOsPrintf("%s=%5llu, ", mvCpuCntrsTbl[i].name, counters_avg); -+ } -+ mvOsPrintf("\n"); -+ mvCpuCntrsEventClear(pEvent); -+ mvCpuCntrsReset(); -+} -+ -+void mvCpuCntrsStatus(void) -+{ -+ int i; -+ -+ for(i=0; icounters_before[i] = mvCpuCntrsRead(i); -+#else -+ pEvent->counters_before[1] = mvCpuCntrsRead(1); -+ pEvent->counters_before[3] = mvCpuCntrsRead(3); -+ pEvent->counters_before[0] = mvCpuCntrsRead(0); -+ pEvent->counters_before[2] = mvCpuCntrsRead(2); -+#endif -+} -+ -+static INLINE void mvCpuCntrsReadAfter(MV_CPU_CNTRS_EVENT* pEvent) -+{ -+ int i; -+ -+#if 0 -+ /* order is important - we want to measure the cycle count first here! */ -+ for(i=0; icounters_after[i] = mvCpuCntrsRead(i); -+#else -+ pEvent->counters_after[2] = mvCpuCntrsRead(2); -+ pEvent->counters_after[0] = mvCpuCntrsRead(0); -+ pEvent->counters_after[3] = mvCpuCntrsRead(3); -+ pEvent->counters_after[1] = mvCpuCntrsRead(1); -+#endif -+ -+ for(i=0; icounters_sum[i] += (pEvent->counters_after[i] - pEvent->counters_before[i]); -+ } -+ pEvent->num_of_measurements++; -+} -+ -+ -+#ifdef CONFIG_MV_CPU_PERF_CNTRS -+ -+#define MV_CPU_CNTRS_READ(counter) mvCpuCntrsRead(counter) -+ -+#define MV_CPU_CNTRS_START(event) mvCpuCntrsReadBefore(event) -+ -+#define MV_CPU_CNTRS_STOP(event) mvCpuCntrsReadAfter(event) -+ -+#define MV_CPU_CNTRS_SHOW(event) mvCpuCntrsShow(event) -+ -+#else -+ -+#define MV_CPU_CNTRS_READ(counter) -+#define MV_CPU_CNTRS_START(event) -+#define MV_CPU_CNTRS_STOP(event) -+#define MV_CPU_CNTRS_SHOW(event) -+ -+#endif /* CONFIG_MV_CPU_PERF_CNTRS */ -+ -+ -+#endif /* __mvCpuCntrs_h__ */ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c 2010-11-09 20:28:10.522495411 +0100 -@@ -0,0 +1,143 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include "mvOs.h" -+#include "mvCpuL2Cntrs.h" -+ -+ -+ -+MV_CPU_L2_CNTRS_ENTRY mvCpuL2CntrsTbl[MV_CPU_L2_CNTRS_NUM]; -+ -+MV_CPU_L2_CNTRS_EVENT* mvCpuL2CntrsEventTbl[128]; -+ -+void mvCpuL2CntrsReset(void) -+{ -+ MV_U32 reg = 0; -+ -+ MV_ASM ("mcr p15, 6, %0, c15, c13, 0" : : "r" (reg)); -+ MV_ASM ("mcr p15, 6, %0, c15, c13, 1" : : "r" (reg)); -+ MV_ASM ("mcr p15, 6, %0, c15, c13, 2" : : "r" (reg)); -+ MV_ASM ("mcr p15, 6, %0, c15, c13, 3" : : "r" (reg)); -+} -+ -+static void mvCpuL2CntrConfig(int counter, int op) -+{ -+ MV_U32 reg = (1 << op) | 0x1; /*enable*/ -+ -+ switch(counter) -+ { -+ case 0: -+ MV_ASM ("mcr p15, 6, %0, c15, c12, 0" : : "r" (reg)); -+ return; -+ -+ case 1: -+ MV_ASM ("mcr p15, 6, %0, c15, c12, 1" : : "r" (reg)); -+ return; -+ -+ default: -+ mvOsPrintf("mvCpuL2CntrConfig: bad counter number (%d)\n", counter); -+ } -+ return; -+} -+ -+void mvCpuL2CntrsEventClear(MV_CPU_L2_CNTRS_EVENT* pEvent) -+{ -+ int i; -+ -+ for(i=0; icounters_sum[i] = 0; -+ } -+ pEvent->num_of_measurements = 0; -+} -+ -+ -+MV_CPU_L2_CNTRS_EVENT* mvCpuL2CntrsEventCreate(char* name, MV_U32 print_threshold) -+{ -+ int i; -+ MV_CPU_L2_CNTRS_EVENT* event = mvOsMalloc(sizeof(MV_CPU_L2_CNTRS_EVENT)); -+ -+ if(event) -+ { -+ strncpy(event->name, name, sizeof(event->name)); -+ event->num_of_measurements = 0; -+ event->avg_sample_count = print_threshold; -+ for(i=0; icounters_before[i] = 0; -+ event->counters_after[i] = 0; -+ event->counters_sum[i] = 0; -+ } -+ } -+ return event; -+} -+ -+void mvCpuL2CntrsEventDelete(MV_CPU_L2_CNTRS_EVENT* event) -+{ -+ if(event != NULL) -+ mvOsFree(event); -+} -+ -+ -+MV_STATUS mvCpuL2CntrsProgram(int counter, MV_CPU_L2_CNTRS_OPS op, -+ char* name, MV_U32 overhead) -+{ -+ strncpy(mvCpuL2CntrsTbl[counter].name, name, sizeof(mvCpuL2CntrsTbl[counter].name)); -+ mvCpuL2CntrsTbl[counter].operation = op; -+ mvCpuL2CntrsTbl[counter].opIdx = op; -+ mvCpuL2CntrsTbl[counter].overhead = overhead; -+ mvCpuL2CntrConfig(counter, op); -+ mvOsPrintf("CPU L2 Counter %d: operation=%d, overhead=%d\n", -+ counter, op, overhead); -+ return MV_OK; -+} -+ -+void mvCpuL2CntrsShow(MV_CPU_L2_CNTRS_EVENT* pEvent) -+{ -+ int i; -+ MV_U64 counters_avg; -+ -+ if(pEvent->num_of_measurements < pEvent->avg_sample_count) -+ return; -+ -+ mvOsPrintf("%16s: ", pEvent->name); -+ for(i=0; icounters_sum[i], -+ pEvent->num_of_measurements, NULL); -+ -+ if(counters_avg >= mvCpuL2CntrsTbl[i].overhead) -+ counters_avg -= mvCpuL2CntrsTbl[i].overhead; -+ else -+ counters_avg = 0; -+ -+ mvOsPrintf("%s=%5llu, ", mvCpuL2CntrsTbl[i].name, counters_avg); -+ } -+ mvOsPrintf("\n"); -+ mvCpuL2CntrsEventClear(pEvent); -+ mvCpuL2CntrsReset(); -+} -+ -+void mvCpuL2CntrsStatus(void) -+{ -+ int i; -+ -+ for(i=0; icounters_before[i] = mvCpuL2CntrsRead(i); -+} -+ -+static INLINE void mvCpuL2CntrsReadAfter(MV_CPU_L2_CNTRS_EVENT* pEvent) -+{ -+ int i; -+ -+ for(i=0; icounters_after[i] = mvCpuL2CntrsRead(i); -+ pEvent->counters_sum[i] += (pEvent->counters_after[i] - pEvent->counters_before[i]); -+ } -+ pEvent->num_of_measurements++; -+} -+ -+ -+#ifdef CONFIG_MV_CPU_L2_PERF_CNTRS -+ -+#define MV_CPU_L2_CNTRS_READ(counter) mvCpuL2CntrsRead(counter) -+ -+#define MV_CPU_L2_CNTRS_START(event) mvCpuL2CntrsReadBefore(event) -+ -+#define MV_CPU_L2_CNTRS_STOP(event) mvCpuL2CntrsReadAfter(event) -+ -+#define MV_CPU_L2_CNTRS_SHOW(event) mvCpuL2CntrsShow(event) -+ -+#else -+ -+#define MV_CPU_L2_CNTRS_READ(counter) -+#define MV_CPU_L2_CNTRS_START(event) -+#define MV_CPU_L2_CNTRS_STOP(event) -+#define MV_CPU_L2_CNTRS_SHOW(event) -+ -+#endif /* CONFIG_MV_CPU_L2_PERF_CNTRS */ -+ -+ -+#endif /* __mvCpuL2Cntrs_h__ */ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c 2010-11-09 20:28:10.592495381 +0100 -@@ -0,0 +1,1479 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "ddr1_2/mvDram.h" -+#include "boardEnv/mvBoardEnvLib.h" -+ -+#undef MV_DEBUG -+#ifdef MV_DEBUG -+#define DB(x) x -+#else -+#define DB(x) -+#endif -+ -+static MV_VOID cpyDimm2BankInfo(MV_DIMM_INFO *pDimmInfo, -+ MV_DRAM_BANK_INFO *pBankInfo); -+static MV_U32 cas2ps(MV_U8 spd_byte); -+/******************************************************************************* -+* mvDramBankGet - Get the DRAM bank paramters. -+* -+* DESCRIPTION: -+* This function retrieves DRAM bank parameters as described in -+* DRAM_BANK_INFO struct to the controller DRAM unit. In case the board -+* has its DRAM on DIMMs it will use its EEPROM to extract SPD data -+* from it. Otherwise, if the DRAM is soldered on board, the function -+* should insert its bank information into MV_DRAM_BANK_INFO struct. -+* -+* INPUT: -+* bankNum - Board DRAM bank number. -+* -+* OUTPUT: -+* pBankInfo - DRAM bank information struct. -+* -+* RETURN: -+* MV_FAIL - Bank parameters could not be read. -+* -+*******************************************************************************/ -+MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo) -+{ -+ MV_DIMM_INFO dimmInfo; -+ -+ DB(mvOsPrintf("Dram: mvDramBankInfoGet bank %d\n", bankNum)); -+ /* zero pBankInfo structure */ -+ memset(pBankInfo, 0, sizeof(*pBankInfo)); -+ -+ if((NULL == pBankInfo) || (bankNum >= MV_DRAM_MAX_CS )) -+ { -+ DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); -+ return MV_BAD_PARAM; -+ } -+ if( MV_OK != dimmSpdGet((MV_U32)(bankNum/2), &dimmInfo)) -+ { -+ DB(mvOsPrintf("Dram: ERR dimmSpdGet failed to get dimm info \n")); -+ return MV_FAIL; -+ } -+ if((dimmInfo.numOfModuleBanks == 1) && ((bankNum % 2) == 1)) -+ { -+ DB(mvOsPrintf("Dram: ERR dimmSpdGet. Can't find DIMM bank 2 \n")); -+ return MV_FAIL; -+ } -+ -+ /* convert Dimm info to Bank info */ -+ cpyDimm2BankInfo(&dimmInfo, pBankInfo); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* cpyDimm2BankInfo - Convert a Dimm info struct into a bank info struct. -+* -+* DESCRIPTION: -+* Convert a Dimm info struct into a bank info struct. -+* -+* INPUT: -+* pDimmInfo - DIMM information structure. -+* -+* OUTPUT: -+* pBankInfo - DRAM bank information struct. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+static MV_VOID cpyDimm2BankInfo(MV_DIMM_INFO *pDimmInfo, -+ MV_DRAM_BANK_INFO *pBankInfo) -+{ -+ pBankInfo->memoryType = pDimmInfo->memoryType; -+ -+ /* DIMM dimensions */ -+ pBankInfo->numOfRowAddr = pDimmInfo->numOfRowAddr; -+ pBankInfo->numOfColAddr = pDimmInfo->numOfColAddr; -+ pBankInfo->dataWidth = pDimmInfo->dataWidth; -+ pBankInfo->errorCheckType = pDimmInfo->errorCheckType; -+ pBankInfo->sdramWidth = pDimmInfo->sdramWidth; -+ pBankInfo->errorCheckDataWidth = pDimmInfo->errorCheckDataWidth; -+ pBankInfo->numOfBanksOnEachDevice = pDimmInfo->numOfBanksOnEachDevice; -+ pBankInfo->suportedCasLatencies = pDimmInfo->suportedCasLatencies; -+ pBankInfo->refreshInterval = pDimmInfo->refreshInterval; -+ -+ /* DIMM timing parameters */ -+ pBankInfo->minCycleTimeAtMaxCasLatPs = pDimmInfo->minCycleTimeAtMaxCasLatPs; -+ pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps = -+ pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps; -+ pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps = -+ pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps; -+ -+ pBankInfo->minRowPrechargeTime = pDimmInfo->minRowPrechargeTime; -+ pBankInfo->minRowActiveToRowActive = pDimmInfo->minRowActiveToRowActive; -+ pBankInfo->minRasToCasDelay = pDimmInfo->minRasToCasDelay; -+ pBankInfo->minRasPulseWidth = pDimmInfo->minRasPulseWidth; -+ pBankInfo->minWriteRecoveryTime = pDimmInfo->minWriteRecoveryTime; -+ pBankInfo->minWriteToReadCmdDelay = pDimmInfo->minWriteToReadCmdDelay; -+ pBankInfo->minReadToPrechCmdDelay = pDimmInfo->minReadToPrechCmdDelay; -+ pBankInfo->minRefreshToActiveCmd = pDimmInfo->minRefreshToActiveCmd; -+ -+ /* Parameters calculated from the extracted DIMM information */ -+ pBankInfo->size = pDimmInfo->size/pDimmInfo->numOfModuleBanks; -+ pBankInfo->deviceDensity = pDimmInfo->deviceDensity; -+ pBankInfo->numberOfDevices = pDimmInfo->numberOfDevices / -+ pDimmInfo->numOfModuleBanks; -+ -+ /* DIMM attributes (MV_TRUE for yes) */ -+ -+ if ((pDimmInfo->memoryType == MEM_TYPE_SDRAM) || -+ (pDimmInfo->memoryType == MEM_TYPE_DDR1) ) -+ { -+ if (pDimmInfo->dimmAttributes & BIT1) -+ pBankInfo->registeredAddrAndControlInputs = MV_TRUE; -+ else -+ pBankInfo->registeredAddrAndControlInputs = MV_FALSE; -+ } -+ else /* pDimmInfo->memoryType == MEM_TYPE_DDR2 */ -+ { -+ if (pDimmInfo->dimmTypeInfo & (BIT0 | BIT4)) -+ pBankInfo->registeredAddrAndControlInputs = MV_TRUE; -+ else -+ pBankInfo->registeredAddrAndControlInputs = MV_FALSE; -+ } -+ -+ return; -+} -+ -+/******************************************************************************* -+* dimmSpdCpy - Cpy SPD parameters from dimm 0 to dimm 1. -+* -+* DESCRIPTION: -+* Read the DIMM SPD parameters from dimm 0 into dimm 1 SPD. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+MV_STATUS dimmSpdCpy(MV_VOID) -+{ -+ MV_U32 i; -+ MV_U32 spdChecksum; -+ -+ MV_TWSI_SLAVE twsiSlave; -+ MV_U8 data[SPD_SIZE]; -+ -+ /* zero dimmInfo structure */ -+ memset(data, 0, SPD_SIZE); -+ -+ /* read the dimm eeprom */ -+ DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); -+ twsiSlave.slaveAddr.address = MV_BOARD_DIMM0_I2C_ADDR; -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ twsiSlave.offset = 0; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, -+ &twsiSlave, data, SPD_SIZE) ) -+ { -+ DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 0\n")); -+ return MV_FAIL; -+ } -+ DB(puts("DRAM: Reading dimm info succeded.\n")); -+ -+ /* calculate SPD checksum */ -+ spdChecksum = 0; -+ -+ for(i = 0 ; i <= 62 ; i++) -+ { -+ spdChecksum += data[i]; -+ } -+ -+ if ((spdChecksum & 0xff) != data[63]) -+ { -+ DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", -+ (MV_U32)(spdChecksum & 0xff), data[63])); -+ } -+ else -+ { -+ DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); -+ } -+ -+ /* copy the SPD content 1:1 into the DIMM 1 SPD */ -+ twsiSlave.slaveAddr.address = MV_BOARD_DIMM1_I2C_ADDR; -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ twsiSlave.offset = 0; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ for(i = 0 ; i < SPD_SIZE ; i++) -+ { -+ twsiSlave.offset = i; -+ if( MV_OK != mvTwsiWrite (MV_BOARD_DIMM_I2C_CHANNEL, -+ &twsiSlave, &data[i], 1) ) -+ { -+ mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 1 byte %d \n",i); -+ return MV_FAIL; -+ } -+ mvOsDelay(5); -+ } -+ -+ DB(puts("DRAM: Reading dimm info succeded.\n")); -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* dimmSpdGet - Get the SPD parameters. -+* -+* DESCRIPTION: -+* Read the DIMM SPD parameters into given struct parameter. -+* -+* INPUT: -+* dimmNum - DIMM number. See MV_BOARD_DIMM_NUM enumerator. -+* -+* OUTPUT: -+* pDimmInfo - DIMM information structure. -+* -+* RETURN: -+* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo) -+{ -+ MV_U32 i; -+ MV_U32 density = 1; -+ MV_U32 spdChecksum; -+ -+ MV_TWSI_SLAVE twsiSlave; -+ MV_U8 data[SPD_SIZE]; -+ -+ if((NULL == pDimmInfo)|| (dimmNum >= MAX_DIMM_NUM)) -+ { -+ DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); -+ return MV_BAD_PARAM; -+ } -+ -+ /* zero dimmInfo structure */ -+ memset(data, 0, SPD_SIZE); -+ -+ /* read the dimm eeprom */ -+ DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); -+ twsiSlave.slaveAddr.address = (dimmNum == 0) ? -+ MV_BOARD_DIMM0_I2C_ADDR : MV_BOARD_DIMM1_I2C_ADDR; -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ twsiSlave.offset = 0; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, -+ &twsiSlave, data, SPD_SIZE) ) -+ { -+ DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum %d \n", dimmNum)); -+ return MV_FAIL; -+ } -+ DB(puts("DRAM: Reading dimm info succeded.\n")); -+ -+ /* calculate SPD checksum */ -+ spdChecksum = 0; -+ -+ for(i = 0 ; i <= 62 ; i++) -+ { -+ spdChecksum += data[i]; -+ } -+ -+ if ((spdChecksum & 0xff) != data[63]) -+ { -+ DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", -+ (MV_U32)(spdChecksum & 0xff), data[63])); -+ } -+ else -+ { -+ DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); -+ } -+ -+ /* copy the SPD content 1:1 into the dimmInfo structure*/ -+ for(i = 0 ; i < SPD_SIZE ; i++) -+ { -+ pDimmInfo->spdRawData[i] = data[i]; -+ DB(mvOsPrintf("SPD-EEPROM Byte %3d = %3x (%3d)\n",i, data[i], data[i])); -+ } -+ -+ DB(mvOsPrintf("DRAM SPD Information:\n")); -+ -+ /* Memory type (DDR / SDRAM) */ -+ switch (data[DIMM_MEM_TYPE]) -+ { -+ case (DIMM_MEM_TYPE_SDRAM): -+ pDimmInfo->memoryType = MEM_TYPE_SDRAM; -+ DB(mvOsPrintf("DRAM Memeory type SDRAM\n")); -+ break; -+ case (DIMM_MEM_TYPE_DDR1): -+ pDimmInfo->memoryType = MEM_TYPE_DDR1; -+ DB(mvOsPrintf("DRAM Memeory type DDR1\n")); -+ break; -+ case (DIMM_MEM_TYPE_DDR2): -+ pDimmInfo->memoryType = MEM_TYPE_DDR2; -+ DB(mvOsPrintf("DRAM Memeory type DDR2\n")); -+ break; -+ default: -+ mvOsPrintf("ERROR: Undefined memory type!\n"); -+ return MV_ERROR; -+ } -+ -+ -+ /* Number Of Row Addresses */ -+ pDimmInfo->numOfRowAddr = data[DIMM_ROW_NUM]; -+ DB(mvOsPrintf("DRAM numOfRowAddr[3] %d\n",pDimmInfo->numOfRowAddr)); -+ -+ /* Number Of Column Addresses */ -+ pDimmInfo->numOfColAddr = data[DIMM_COL_NUM]; -+ DB(mvOsPrintf("DRAM numOfColAddr[4] %d\n",pDimmInfo->numOfColAddr)); -+ -+ /* Number Of Module Banks */ -+ pDimmInfo->numOfModuleBanks = data[DIMM_MODULE_BANK_NUM]; -+ DB(mvOsPrintf("DRAM numOfModuleBanks[5] 0x%x\n", -+ pDimmInfo->numOfModuleBanks)); -+ -+ /* Number of module banks encoded differently for DDR2 */ -+ if (pDimmInfo->memoryType == MEM_TYPE_DDR2) -+ pDimmInfo->numOfModuleBanks = (pDimmInfo->numOfModuleBanks & 0x7)+1; -+ -+ /* Data Width */ -+ pDimmInfo->dataWidth = data[DIMM_DATA_WIDTH]; -+ DB(mvOsPrintf("DRAM dataWidth[6] 0x%x\n", pDimmInfo->dataWidth)); -+ -+ /* Minimum Cycle Time At Max CasLatancy */ -+ pDimmInfo->minCycleTimeAtMaxCasLatPs = cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS]); -+ -+ /* Error Check Type */ -+ pDimmInfo->errorCheckType = data[DIMM_ERR_CHECK_TYPE]; -+ DB(mvOsPrintf("DRAM errorCheckType[11] 0x%x\n", -+ pDimmInfo->errorCheckType)); -+ -+ /* Refresh Interval */ -+ pDimmInfo->refreshInterval = data[DIMM_REFRESH_INTERVAL]; -+ DB(mvOsPrintf("DRAM refreshInterval[12] 0x%x\n", -+ pDimmInfo->refreshInterval)); -+ -+ /* Sdram Width */ -+ pDimmInfo->sdramWidth = data[DIMM_SDRAM_WIDTH]; -+ DB(mvOsPrintf("DRAM sdramWidth[13] 0x%x\n",pDimmInfo->sdramWidth)); -+ -+ /* Error Check Data Width */ -+ pDimmInfo->errorCheckDataWidth = data[DIMM_ERR_CHECK_DATA_WIDTH]; -+ DB(mvOsPrintf("DRAM errorCheckDataWidth[14] 0x%x\n", -+ pDimmInfo->errorCheckDataWidth)); -+ -+ /* Burst Length Supported */ -+ /* SDRAM/DDR1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * -+ *********************************************************/ -+ /* DDR2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * -+ *********************************************************/ -+ -+ pDimmInfo->burstLengthSupported = data[DIMM_BURST_LEN_SUP]; -+ DB(mvOsPrintf("DRAM burstLengthSupported[16] 0x%x\n", -+ pDimmInfo->burstLengthSupported)); -+ -+ /* Number Of Banks On Each Device */ -+ pDimmInfo->numOfBanksOnEachDevice = data[DIMM_DEV_BANK_NUM]; -+ DB(mvOsPrintf("DRAM numOfBanksOnEachDevice[17] 0x%x\n", -+ pDimmInfo->numOfBanksOnEachDevice)); -+ -+ /* Suported Cas Latencies */ -+ -+ /* SDRAM: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * -+ ********************************************************/ -+ -+ /* DDR 1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * -+ *********************************************************/ -+ -+ /* DDR 2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * -+ *********************************************************/ -+ -+ pDimmInfo->suportedCasLatencies = data[DIMM_SUP_CAL]; -+ DB(mvOsPrintf("DRAM suportedCasLatencies[18] 0x%x\n", -+ pDimmInfo->suportedCasLatencies)); -+ -+ /* For DDR2 only, get the DIMM type information */ -+ if (pDimmInfo->memoryType == MEM_TYPE_DDR2) -+ { -+ pDimmInfo->dimmTypeInfo = data[DIMM_DDR2_TYPE_INFORMATION]; -+ DB(mvOsPrintf("DRAM dimmTypeInfo[20] (DDR2) 0x%x\n", -+ pDimmInfo->dimmTypeInfo)); -+ } -+ -+ /* SDRAM Modules Attributes */ -+ pDimmInfo->dimmAttributes = data[DIMM_BUF_ADDR_CONT_IN]; -+ DB(mvOsPrintf("DRAM dimmAttributes[21] 0x%x\n", -+ pDimmInfo->dimmAttributes)); -+ -+ /* Minimum Cycle Time At Max CasLatancy Minus 1*/ -+ pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps = -+ cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS1]); -+ -+ /* Minimum Cycle Time At Max CasLatancy Minus 2*/ -+ pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps = -+ cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS2]); -+ -+ pDimmInfo->minRowPrechargeTime = data[DIMM_MIN_ROW_PRECHARGE_TIME]; -+ DB(mvOsPrintf("DRAM minRowPrechargeTime[27] 0x%x\n", -+ pDimmInfo->minRowPrechargeTime)); -+ pDimmInfo->minRowActiveToRowActive = data[DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE]; -+ DB(mvOsPrintf("DRAM minRowActiveToRowActive[28] 0x%x\n", -+ pDimmInfo->minRowActiveToRowActive)); -+ pDimmInfo->minRasToCasDelay = data[DIMM_MIN_RAS_TO_CAS_DELAY]; -+ DB(mvOsPrintf("DRAM minRasToCasDelay[29] 0x%x\n", -+ pDimmInfo->minRasToCasDelay)); -+ pDimmInfo->minRasPulseWidth = data[DIMM_MIN_RAS_PULSE_WIDTH]; -+ DB(mvOsPrintf("DRAM minRasPulseWidth[30] 0x%x\n", -+ pDimmInfo->minRasPulseWidth)); -+ -+ /* DIMM Bank Density */ -+ pDimmInfo->dimmBankDensity = data[DIMM_BANK_DENSITY]; -+ DB(mvOsPrintf("DRAM dimmBankDensity[31] 0x%x\n", -+ pDimmInfo->dimmBankDensity)); -+ -+ /* Only DDR2 includes Write Recovery Time field. Other SDRAM ignore */ -+ pDimmInfo->minWriteRecoveryTime = data[DIMM_MIN_WRITE_RECOVERY_TIME]; -+ DB(mvOsPrintf("DRAM minWriteRecoveryTime[36] 0x%x\n", -+ pDimmInfo->minWriteRecoveryTime)); -+ -+ /* Only DDR2 includes Internal Write To Read Command Delay field. */ -+ pDimmInfo->minWriteToReadCmdDelay = data[DIMM_MIN_WRITE_TO_READ_CMD_DELAY]; -+ DB(mvOsPrintf("DRAM minWriteToReadCmdDelay[37] 0x%x\n", -+ pDimmInfo->minWriteToReadCmdDelay)); -+ -+ /* Only DDR2 includes Internal Read To Precharge Command Delay field. */ -+ pDimmInfo->minReadToPrechCmdDelay = data[DIMM_MIN_READ_TO_PRECH_CMD_DELAY]; -+ DB(mvOsPrintf("DRAM minReadToPrechCmdDelay[38] 0x%x\n", -+ pDimmInfo->minReadToPrechCmdDelay)); -+ -+ /* Only DDR2 includes Minimum Refresh to Activate/Refresh Command field */ -+ pDimmInfo->minRefreshToActiveCmd = data[DIMM_MIN_REFRESH_TO_ACTIVATE_CMD]; -+ DB(mvOsPrintf("DRAM minRefreshToActiveCmd[42] 0x%x\n", -+ pDimmInfo->minRefreshToActiveCmd)); -+ -+ /* calculating the sdram density. Representing device density from */ -+ /* bit 20 to allow representation of 4GB and above. */ -+ /* For example, if density is 512Mbit 0x20000000, will be represent in */ -+ /* deviceDensity by 0x20000000 >> 16 --> 0x00000200. Another example */ -+ /* is density 8GB 0x200000000 >> 16 --> 0x00002000. */ -+ density = (1 << ((pDimmInfo->numOfRowAddr + pDimmInfo->numOfColAddr) - 20)); -+ pDimmInfo->deviceDensity = density * -+ pDimmInfo->numOfBanksOnEachDevice * -+ pDimmInfo->sdramWidth; -+ DB(mvOsPrintf("DRAM deviceDensity %d\n",pDimmInfo->deviceDensity)); -+ -+ /* Number of devices includeing Error correction */ -+ pDimmInfo->numberOfDevices = (pDimmInfo->dataWidth/pDimmInfo->sdramWidth) * -+ pDimmInfo->numOfModuleBanks; -+ DB(mvOsPrintf("DRAM numberOfDevices %d\n", -+ pDimmInfo->numberOfDevices)); -+ -+ pDimmInfo->size = 0; -+ -+ /* Note that pDimmInfo->size is in MB units */ -+ if (pDimmInfo->memoryType == MEM_TYPE_SDRAM) -+ { -+ if (pDimmInfo->dimmBankDensity & BIT0) -+ pDimmInfo->size += 1024; /* Equal to 1GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT1) -+ pDimmInfo->size += 8; /* Equal to 8MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT2) -+ pDimmInfo->size += 16; /* Equal to 16MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT3) -+ pDimmInfo->size += 32; /* Equal to 32MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT4) -+ pDimmInfo->size += 64; /* Equal to 64MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT5) -+ pDimmInfo->size += 128; /* Equal to 128MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT6) -+ pDimmInfo->size += 256; /* Equal to 256MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT7) -+ pDimmInfo->size += 512; /* Equal to 512MB */ -+ } -+ else if (pDimmInfo->memoryType == MEM_TYPE_DDR1) -+ { -+ if (pDimmInfo->dimmBankDensity & BIT0) -+ pDimmInfo->size += 1024; /* Equal to 1GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT1) -+ pDimmInfo->size += 2048; /* Equal to 2GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT2) -+ pDimmInfo->size += 16; /* Equal to 16MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT3) -+ pDimmInfo->size += 32; /* Equal to 32MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT4) -+ pDimmInfo->size += 64; /* Equal to 64MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT5) -+ pDimmInfo->size += 128; /* Equal to 128MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT6) -+ pDimmInfo->size += 256; /* Equal to 256MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT7) -+ pDimmInfo->size += 512; /* Equal to 512MB */ -+ } -+ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ -+ { -+ if (pDimmInfo->dimmBankDensity & BIT0) -+ pDimmInfo->size += 1024; /* Equal to 1GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT1) -+ pDimmInfo->size += 2048; /* Equal to 2GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT2) -+ pDimmInfo->size += 4096; /* Equal to 4GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT3) -+ pDimmInfo->size += 8192; /* Equal to 8GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT4) -+ pDimmInfo->size += 16384; /* Equal to 16GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT5) -+ pDimmInfo->size += 128; /* Equal to 128MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT6) -+ pDimmInfo->size += 256; /* Equal to 256MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT7) -+ pDimmInfo->size += 512; /* Equal to 512MB */ -+ } -+ -+ pDimmInfo->size *= pDimmInfo->numOfModuleBanks; -+ -+ DB(mvOsPrintf("Dram: dimm size %dMB \n",pDimmInfo->size)); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* dimmSpdPrint - Print the SPD parameters. -+* -+* DESCRIPTION: -+* Print the Dimm SPD parameters. -+* -+* INPUT: -+* pDimmInfo - DIMM information structure. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID dimmSpdPrint(MV_U32 dimmNum) -+{ -+ MV_DIMM_INFO dimmInfo; -+ MV_U32 i, temp = 0; -+ MV_U32 k, maskLeftOfPoint = 0, maskRightOfPoint = 0; -+ MV_U32 rightOfPoint = 0,leftOfPoint = 0, div, time_tmp, shift; -+ MV_U32 busClkPs; -+ MV_U8 trp_clocks=0, trcd_clocks, tras_clocks, trrd_clocks, -+ temp_buf[40], *spdRawData; -+ -+ busClkPs = 1000000000 / (mvBoardSysClkGet() / 100); /* in 10 ps units */ -+ -+ spdRawData = dimmInfo.spdRawData; -+ -+ if(MV_OK != dimmSpdGet(dimmNum, &dimmInfo)) -+ { -+ mvOsOutput("ERROR: Could not read SPD information!\n"); -+ return; -+ } -+ -+ /* find Manufactura of Dimm Module */ -+ mvOsOutput("\nManufacturer's JEDEC ID Code: "); -+ for(i = 0 ; i < DIMM_MODULE_MANU_SIZE ; i++) -+ { -+ mvOsOutput("%x",spdRawData[DIMM_MODULE_MANU_OFFS + i]); -+ } -+ mvOsOutput("\n"); -+ -+ /* Manufacturer's Specific Data */ -+ for(i = 0 ; i < DIMM_MODULE_ID_SIZE ; i++) -+ { -+ temp_buf[i] = spdRawData[DIMM_MODULE_ID_OFFS + i]; -+ } -+ mvOsOutput("Manufacturer's Specific Data: %s\n", temp_buf); -+ -+ /* Module Part Number */ -+ for(i = 0 ; i < DIMM_MODULE_VEN_SIZE ; i++) -+ { -+ temp_buf[i] = spdRawData[DIMM_MODULE_VEN_OFFS + i]; -+ } -+ mvOsOutput("Module Part Number: %s\n", temp_buf); -+ -+ /* Module Serial Number */ -+ for(i = 0; i < sizeof(MV_U32); i++) -+ { -+ temp |= spdRawData[95+i] << 8*i; -+ } -+ mvOsOutput("DIMM Serial No. %ld (%lx)\n", (long)temp, -+ (long)temp); -+ -+ /* find Manufac-Data of Dimm Module */ -+ mvOsOutput("Manufactoring Date: Year 20%d%d/ ww %d%d\n", -+ ((spdRawData[93] & 0xf0) >> 4), (spdRawData[93] & 0xf), -+ ((spdRawData[94] & 0xf0) >> 4), (spdRawData[94] & 0xf)); -+ /* find modul_revision of Dimm Module */ -+ mvOsOutput("Module Revision: %d.%d\n", -+ spdRawData[91], spdRawData[92]); -+ -+ /* find manufac_place of Dimm Module */ -+ mvOsOutput("manufac_place: %d\n", spdRawData[72]); -+ -+ /* go over the first 35 I2C data bytes */ -+ for(i = 2 ; i <= 35 ; i++) -+ switch(i) -+ { -+ case 2: /* Memory type (DDR1/2 / SDRAM) */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ mvOsOutput("Dram Type is: SDRAM\n"); -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ mvOsOutput("Dram Type is: SDRAM DDR1\n"); -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) -+ mvOsOutput("Dram Type is: SDRAM DDR2\n"); -+ else -+ mvOsOutput("Dram Type unknown\n"); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 3: /* Number Of Row Addresses */ -+ mvOsOutput("Module Number of row addresses: %d\n", -+ dimmInfo.numOfRowAddr); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 4: /* Number Of Column Addresses */ -+ mvOsOutput("Module Number of col addresses: %d\n", -+ dimmInfo.numOfColAddr); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 5: /* Number Of Module Banks */ -+ mvOsOutput("Number of Banks on Mod.: %d\n", -+ dimmInfo.numOfModuleBanks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 6: /* Data Width */ -+ mvOsOutput("Module Data Width: %d bit\n", -+ dimmInfo.dataWidth); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 8: /* Voltage Interface */ -+ switch(spdRawData[i]) -+ { -+ case 0x0: -+ mvOsOutput("Module is TTL_5V_TOLERANT\n"); -+ break; -+ case 0x1: -+ mvOsOutput("Module is LVTTL\n"); -+ break; -+ case 0x2: -+ mvOsOutput("Module is HSTL_1_5V\n"); -+ break; -+ case 0x3: -+ mvOsOutput("Module is SSTL_3_3V\n"); -+ break; -+ case 0x4: -+ mvOsOutput("Module is SSTL_2_5V\n"); -+ break; -+ case 0x5: -+ if (dimmInfo.memoryType != MEM_TYPE_SDRAM) -+ { -+ mvOsOutput("Module is SSTL_1_8V\n"); -+ break; -+ } -+ default: -+ mvOsOutput("Module is VOLTAGE_UNKNOWN\n"); -+ break; -+ } -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 9: /* Minimum Cycle Time At Max CasLatancy */ -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ rightOfPoint = (spdRawData[i] & 0x0f) * 10; -+ -+ /* DDR2 addition of right of point */ -+ if ((spdRawData[i] & 0x0f) == 0xA) -+ { -+ rightOfPoint = 25; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xB) -+ { -+ rightOfPoint = 33; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xC) -+ { -+ rightOfPoint = 66; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xD) -+ { -+ rightOfPoint = 75; -+ } -+ mvOsOutput("Minimum Cycle Time At Max CL: %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 10: /* Clock To Data Out */ -+ div = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 10:100; -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / div; -+ rightOfPoint = time_tmp % div; -+ mvOsOutput("Clock To Data Out: %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 11: /* Error Check Type */ -+ mvOsOutput("Error Check Type (0=NONE): %d\n", -+ dimmInfo.errorCheckType); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 12: /* Refresh Interval */ -+ mvOsOutput("Refresh Rate: %x\n", -+ dimmInfo.refreshInterval); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 13: /* Sdram Width */ -+ mvOsOutput("Sdram Width: %d bits\n", -+ dimmInfo.sdramWidth); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 14: /* Error Check Data Width */ -+ mvOsOutput("Error Check Data Width: %d bits\n", -+ dimmInfo.errorCheckDataWidth); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 15: /* Minimum Clock Delay is unsupported */ -+ if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || -+ (dimmInfo.memoryType == MEM_TYPE_DDR1)) -+ { -+ mvOsOutput("Minimum Clk Delay back to back: %d\n", -+ spdRawData[i]); -+ } -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 16: /* Burst Length Supported */ -+ /* SDRAM/DDR1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * -+ *********************************************************/ -+ /* DDR2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * -+ *********************************************************/ -+ mvOsOutput("Burst Length Supported: "); -+ if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || -+ (dimmInfo.memoryType == MEM_TYPE_DDR1)) -+ { -+ if (dimmInfo.burstLengthSupported & BIT0) -+ mvOsOutput("1, "); -+ if (dimmInfo.burstLengthSupported & BIT1) -+ mvOsOutput("2, "); -+ } -+ if (dimmInfo.burstLengthSupported & BIT2) -+ mvOsOutput("4, "); -+ if (dimmInfo.burstLengthSupported & BIT3) -+ mvOsOutput("8, "); -+ -+ mvOsOutput(" Bit \n"); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 17: /* Number Of Banks On Each Device */ -+ mvOsOutput("Number Of Banks On Each Chip: %d\n", -+ dimmInfo.numOfBanksOnEachDevice); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 18: /* Suported Cas Latencies */ -+ -+ /* SDRAM: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * -+ ********************************************************/ -+ -+ /* DDR 1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * -+ *********************************************************/ -+ -+ /* DDR 2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * -+ *********************************************************/ -+ -+ mvOsOutput("Suported Cas Latencies: (CL) "); -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ for (k = 0; k <=7; k++) -+ { -+ if (dimmInfo.suportedCasLatencies & (1 << k)) -+ mvOsOutput("%d, ", k+1); -+ } -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ { -+ if (dimmInfo.suportedCasLatencies & BIT0) -+ mvOsOutput("1, "); -+ if (dimmInfo.suportedCasLatencies & BIT1) -+ mvOsOutput("1.5, "); -+ if (dimmInfo.suportedCasLatencies & BIT2) -+ mvOsOutput("2, "); -+ if (dimmInfo.suportedCasLatencies & BIT3) -+ mvOsOutput("2.5, "); -+ if (dimmInfo.suportedCasLatencies & BIT4) -+ mvOsOutput("3, "); -+ if (dimmInfo.suportedCasLatencies & BIT5) -+ mvOsOutput("3.5, "); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) -+ { -+ if (dimmInfo.suportedCasLatencies & BIT2) -+ mvOsOutput("2, "); -+ if (dimmInfo.suportedCasLatencies & BIT3) -+ mvOsOutput("3, "); -+ if (dimmInfo.suportedCasLatencies & BIT4) -+ mvOsOutput("4, "); -+ if (dimmInfo.suportedCasLatencies & BIT5) -+ mvOsOutput("5, "); -+ } -+ else -+ mvOsOutput("?.?, "); -+ mvOsOutput("\n"); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 20: /* DDR2 DIMM type info */ -+ if (dimmInfo.memoryType == MEM_TYPE_DDR2) -+ { -+ if (dimmInfo.dimmTypeInfo & (BIT0 | BIT4)) -+ mvOsOutput("Registered DIMM (RDIMM)\n"); -+ else if (dimmInfo.dimmTypeInfo & (BIT1 | BIT5)) -+ mvOsOutput("Unbuffered DIMM (UDIMM)\n"); -+ else -+ mvOsOutput("Unknown DIMM type.\n"); -+ } -+ -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 21: /* SDRAM Modules Attributes */ -+ mvOsOutput("\nModule Attributes (SPD Byte 21): \n"); -+ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ if (dimmInfo.dimmAttributes & BIT0) -+ mvOsOutput(" Buffered Addr/Control Input: Yes\n"); -+ else -+ mvOsOutput(" Buffered Addr/Control Input: No\n"); -+ -+ if (dimmInfo.dimmAttributes & BIT1) -+ mvOsOutput(" Registered Addr/Control Input: Yes\n"); -+ else -+ mvOsOutput(" Registered Addr/Control Input: No\n"); -+ -+ if (dimmInfo.dimmAttributes & BIT2) -+ mvOsOutput(" On-Card PLL (clock): Yes \n"); -+ else -+ mvOsOutput(" On-Card PLL (clock): No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT3) -+ mvOsOutput(" Bufferd DQMB Input: Yes \n"); -+ else -+ mvOsOutput(" Bufferd DQMB Inputs: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT4) -+ mvOsOutput(" Registered DQMB Inputs: Yes \n"); -+ else -+ mvOsOutput(" Registered DQMB Inputs: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT5) -+ mvOsOutput(" Differential Clock Input: Yes \n"); -+ else -+ mvOsOutput(" Differential Clock Input: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT6) -+ mvOsOutput(" redundant Row Addressing: Yes \n"); -+ else -+ mvOsOutput(" redundant Row Addressing: No \n"); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ { -+ if (dimmInfo.dimmAttributes & BIT0) -+ mvOsOutput(" Buffered Addr/Control Input: Yes\n"); -+ else -+ mvOsOutput(" Buffered Addr/Control Input: No\n"); -+ -+ if (dimmInfo.dimmAttributes & BIT1) -+ mvOsOutput(" Registered Addr/Control Input: Yes\n"); -+ else -+ mvOsOutput(" Registered Addr/Control Input: No\n"); -+ -+ if (dimmInfo.dimmAttributes & BIT2) -+ mvOsOutput(" On-Card PLL (clock): Yes \n"); -+ else -+ mvOsOutput(" On-Card PLL (clock): No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT3) -+ mvOsOutput(" FET Switch On-Card Enabled: Yes \n"); -+ else -+ mvOsOutput(" FET Switch On-Card Enabled: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT4) -+ mvOsOutput(" FET Switch External Enabled: Yes \n"); -+ else -+ mvOsOutput(" FET Switch External Enabled: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT5) -+ mvOsOutput(" Differential Clock Input: Yes \n"); -+ else -+ mvOsOutput(" Differential Clock Input: No \n"); -+ } -+ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ -+ { -+ mvOsOutput(" Number of Active Registers on the DIMM: %d\n", -+ (dimmInfo.dimmAttributes & 0x3) + 1); -+ -+ mvOsOutput(" Number of PLLs on the DIMM: %d\n", -+ ((dimmInfo.dimmAttributes) >> 2) & 0x3); -+ -+ if (dimmInfo.dimmAttributes & BIT4) -+ mvOsOutput(" FET Switch External Enabled: Yes \n"); -+ else -+ mvOsOutput(" FET Switch External Enabled: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT6) -+ mvOsOutput(" Analysis probe installed: Yes \n"); -+ else -+ mvOsOutput(" Analysis probe installed: No \n"); -+ } -+ -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 22: /* Suported AutoPreCharge */ -+ mvOsOutput("\nModul Attributes (SPD Byte 22): \n"); -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ if ( spdRawData[i] & BIT0 ) -+ mvOsOutput(" Early Ras Precharge: Yes \n"); -+ else -+ mvOsOutput(" Early Ras Precharge: No \n"); -+ -+ if ( spdRawData[i] & BIT1 ) -+ mvOsOutput(" AutoPreCharge: Yes \n"); -+ else -+ mvOsOutput(" AutoPreCharge: No \n"); -+ -+ if ( spdRawData[i] & BIT2 ) -+ mvOsOutput(" Precharge All: Yes \n"); -+ else -+ mvOsOutput(" Precharge All: No \n"); -+ -+ if ( spdRawData[i] & BIT3 ) -+ mvOsOutput(" Write 1/ReadBurst: Yes \n"); -+ else -+ mvOsOutput(" Write 1/ReadBurst: No \n"); -+ -+ if ( spdRawData[i] & BIT4 ) -+ mvOsOutput(" lower VCC tolerance: 5%%\n"); -+ else -+ mvOsOutput(" lower VCC tolerance: 10%%\n"); -+ -+ if ( spdRawData[i] & BIT5 ) -+ mvOsOutput(" upper VCC tolerance: 5%%\n"); -+ else -+ mvOsOutput(" upper VCC tolerance: 10%%\n"); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ { -+ if ( spdRawData[i] & BIT0 ) -+ mvOsOutput(" Supports Weak Driver: Yes \n"); -+ else -+ mvOsOutput(" Supports Weak Driver: No \n"); -+ -+ if ( !(spdRawData[i] & BIT4) ) -+ mvOsOutput(" lower VCC tolerance: 0.2V\n"); -+ -+ if ( !(spdRawData[i] & BIT5) ) -+ mvOsOutput(" upper VCC tolerance: 0.2V\n"); -+ -+ if ( spdRawData[i] & BIT6 ) -+ mvOsOutput(" Concurrent Auto Preharge: Yes \n"); -+ else -+ mvOsOutput(" Concurrent Auto Preharge: No \n"); -+ -+ if ( spdRawData[i] & BIT7 ) -+ mvOsOutput(" Supports Fast AP: Yes \n"); -+ else -+ mvOsOutput(" Supports Fast AP: No \n"); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) -+ { -+ if ( spdRawData[i] & BIT0 ) -+ mvOsOutput(" Supports Weak Driver: Yes \n"); -+ else -+ mvOsOutput(" Supports Weak Driver: No \n"); -+ } -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 23: -+ /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */ -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ rightOfPoint = (spdRawData[i] & 0x0f) * 10; -+ -+ /* DDR2 addition of right of point */ -+ if ((spdRawData[i] & 0x0f) == 0xA) -+ { -+ rightOfPoint = 25; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xB) -+ { -+ rightOfPoint = 33; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xC) -+ { -+ rightOfPoint = 66; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xD) -+ { -+ rightOfPoint = 75; -+ } -+ -+ mvOsOutput("Minimum Cycle Time At 2nd highest CasLatancy" -+ "(0 = Not supported): %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint ); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 24: /* Clock To Data Out 2nd highest Cas Latency Value*/ -+ div = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? 10:100; -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / div; -+ rightOfPoint = time_tmp % div; -+ mvOsOutput("Clock To Data Out (2nd CL value): %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 25: -+ /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ leftOfPoint = (spdRawData[i] & 0xfc) >> 2; -+ rightOfPoint = (spdRawData[i] & 0x3) * 25; -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ rightOfPoint = (spdRawData[i] & 0x0f) * 10; -+ -+ /* DDR2 addition of right of point */ -+ if ((spdRawData[i] & 0x0f) == 0xA) -+ { -+ rightOfPoint = 25; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xB) -+ { -+ rightOfPoint = 33; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xC) -+ { -+ rightOfPoint = 66; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xD) -+ { -+ rightOfPoint = 75; -+ } -+ } -+ mvOsOutput("Minimum Cycle Time At 3rd highest CasLatancy" -+ "(0 = Not supported): %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint ); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 26: /* Clock To Data Out 3rd highest Cas Latency Value*/ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ leftOfPoint = (spdRawData[i] & 0xfc) >> 2; -+ rightOfPoint = (spdRawData[i] & 0x3) * 25; -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = 0; -+ rightOfPoint = time_tmp; -+ } -+ mvOsOutput("Clock To Data Out (3rd CL value): %d.%2d[ns]\n", -+ leftOfPoint, rightOfPoint ); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 27: /* Minimum Row Precharge Time */ -+ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; -+ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0xff : 0xfc; -+ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0x00 : 0x03; -+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); -+ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; -+ temp = ((leftOfPoint*100) + rightOfPoint);/* in 10ps Intervals*/ -+ trp_clocks = (temp + (busClkPs-1)) / busClkPs; -+ mvOsOutput("Minimum Row Precharge Time [ns]: %d.%d = " -+ "in Clk cycles %d\n", -+ leftOfPoint, rightOfPoint, trp_clocks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 28: /* Minimum Row Active to Row Active Time */ -+ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; -+ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0xff : 0xfc; -+ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0x00 : 0x03; -+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); -+ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; -+ temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ -+ trrd_clocks = (temp + (busClkPs-1)) / busClkPs; -+ mvOsOutput("Minimum Row Active -To- Row Active Delay [ns]: " -+ "%d.%d = in Clk cycles %d\n", -+ leftOfPoint, rightOfPoint, trp_clocks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 29: /* Minimum Ras-To-Cas Delay */ -+ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; -+ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0xff : 0xfc; -+ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0x00 : 0x03; -+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); -+ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; -+ temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ -+ trcd_clocks = (temp + (busClkPs-1) )/ busClkPs; -+ mvOsOutput("Minimum Ras-To-Cas Delay [ns]: %d.%d = " -+ "in Clk cycles %d\n", -+ leftOfPoint, rightOfPoint, trp_clocks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 30: /* Minimum Ras Pulse Width */ -+ tras_clocks = (cas2ps(spdRawData[i])+(busClkPs-1)) / busClkPs; -+ mvOsOutput("Minimum Ras Pulse Width [ns]: %d = " -+ "in Clk cycles %d\n", spdRawData[i], tras_clocks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 31: /* Module Bank Density */ -+ mvOsOutput("Module Bank Density (more than 1= Multisize-Module):"); -+ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ if (dimmInfo.dimmBankDensity & BIT0) -+ mvOsOutput("1GB, "); -+ if (dimmInfo.dimmBankDensity & BIT1) -+ mvOsOutput("8MB, "); -+ if (dimmInfo.dimmBankDensity & BIT2) -+ mvOsOutput("16MB, "); -+ if (dimmInfo.dimmBankDensity & BIT3) -+ mvOsOutput("32MB, "); -+ if (dimmInfo.dimmBankDensity & BIT4) -+ mvOsOutput("64MB, "); -+ if (dimmInfo.dimmBankDensity & BIT5) -+ mvOsOutput("128MB, "); -+ if (dimmInfo.dimmBankDensity & BIT6) -+ mvOsOutput("256MB, "); -+ if (dimmInfo.dimmBankDensity & BIT7) -+ mvOsOutput("512MB, "); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ { -+ if (dimmInfo.dimmBankDensity & BIT0) -+ mvOsOutput("1GB, "); -+ if (dimmInfo.dimmBankDensity & BIT1) -+ mvOsOutput("2GB, "); -+ if (dimmInfo.dimmBankDensity & BIT2) -+ mvOsOutput("16MB, "); -+ if (dimmInfo.dimmBankDensity & BIT3) -+ mvOsOutput("32MB, "); -+ if (dimmInfo.dimmBankDensity & BIT4) -+ mvOsOutput("64MB, "); -+ if (dimmInfo.dimmBankDensity & BIT5) -+ mvOsOutput("128MB, "); -+ if (dimmInfo.dimmBankDensity & BIT6) -+ mvOsOutput("256MB, "); -+ if (dimmInfo.dimmBankDensity & BIT7) -+ mvOsOutput("512MB, "); -+ } -+ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ -+ { -+ if (dimmInfo.dimmBankDensity & BIT0) -+ mvOsOutput("1GB, "); -+ if (dimmInfo.dimmBankDensity & BIT1) -+ mvOsOutput("2GB, "); -+ if (dimmInfo.dimmBankDensity & BIT2) -+ mvOsOutput("4GB, "); -+ if (dimmInfo.dimmBankDensity & BIT3) -+ mvOsOutput("8GB, "); -+ if (dimmInfo.dimmBankDensity & BIT4) -+ mvOsOutput("16GB, "); -+ if (dimmInfo.dimmBankDensity & BIT5) -+ mvOsOutput("128MB, "); -+ if (dimmInfo.dimmBankDensity & BIT6) -+ mvOsOutput("256MB, "); -+ if (dimmInfo.dimmBankDensity & BIT7) -+ mvOsOutput("512MB, "); -+ } -+ mvOsOutput("\n"); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 32: /* Address And Command Setup Time (measured in ns/1000) */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ rightOfPoint = (spdRawData[i] & 0x0f); -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ if(leftOfPoint > 7) -+ { -+ leftOfPoint *= -1; -+ } -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / 100; -+ rightOfPoint = time_tmp % 100; -+ } -+ mvOsOutput("Address And Command Setup Time [ns]: %d.%d\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 33: /* Address And Command Hold Time */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ rightOfPoint = (spdRawData[i] & 0x0f); -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ if(leftOfPoint > 7) -+ { -+ leftOfPoint *= -1; -+ } -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / 100; -+ rightOfPoint = time_tmp % 100; -+ } -+ mvOsOutput("Address And Command Hold Time [ns]: %d.%d\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 34: /* Data Input Setup Time */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ rightOfPoint = (spdRawData[i] & 0x0f); -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ if(leftOfPoint > 7) -+ { -+ leftOfPoint *= -1; -+ } -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / 100; -+ rightOfPoint = time_tmp % 100; -+ } -+ mvOsOutput("Data Input Setup Time [ns]: %d.%d\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 35: /* Data Input Hold Time */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ rightOfPoint = (spdRawData[i] & 0x0f); -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ if(leftOfPoint > 7) -+ { -+ leftOfPoint *= -1; -+ } -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / 100; -+ rightOfPoint = time_tmp % 100; -+ } -+ mvOsOutput("Data Input Hold Time [ns]: %d.%d\n\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 36: /* Relevant for DDR2 only: Write Recovery Time */ -+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> 2); -+ rightOfPoint = (spdRawData[i] & maskRightOfPoint) * 25; -+ mvOsOutput("Write Recovery Time [ns]: %d.%d\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ } -+ -+} -+ -+ -+/* -+ * translate ns.ns/10 coding of SPD timing values -+ * into ps unit values -+ */ -+/******************************************************************************* -+* cas2ps - Translate x.y ns parameter to pico-seconds values -+* -+* DESCRIPTION: -+* This function translates x.y nano seconds to its value in pico seconds. -+* For example 3.75ns will return 3750. -+* -+* INPUT: -+* spd_byte - DIMM SPD byte. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* value in pico seconds. -+* -+*******************************************************************************/ -+static MV_U32 cas2ps(MV_U8 spd_byte) -+{ -+ MV_U32 ns, ns10; -+ -+ /* isolate upper nibble */ -+ ns = (spd_byte >> 4) & 0x0F; -+ /* isolate lower nibble */ -+ ns10 = (spd_byte & 0x0F); -+ -+ if( ns10 < 10 ) { -+ ns10 *= 10; -+ } -+ else if( ns10 == 10 ) -+ ns10 = 25; -+ else if( ns10 == 11 ) -+ ns10 = 33; -+ else if( ns10 == 12 ) -+ ns10 = 66; -+ else if( ns10 == 13 ) -+ ns10 = 75; -+ else -+ { -+ mvOsOutput("cas2ps Err. unsupported cycle time.\n"); -+ } -+ -+ return (ns*1000 + ns10*10); -+} -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h 2010-11-09 20:28:10.622495522 +0100 -@@ -0,0 +1,191 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvDram -+#define __INCmvDram -+ -+#include "ddr1_2/mvDramIf.h" -+#include "twsi/mvTwsi.h" -+ -+#define MAX_DIMM_NUM 2 -+#define SPD_SIZE 128 -+ -+/* Dimm spd offsets */ -+#define DIMM_MEM_TYPE 2 -+#define DIMM_ROW_NUM 3 -+#define DIMM_COL_NUM 4 -+#define DIMM_MODULE_BANK_NUM 5 -+#define DIMM_DATA_WIDTH 6 -+#define DIMM_VOLT_IF 8 -+#define DIMM_MIN_CC_AT_MAX_CAS 9 -+#define DIMM_ERR_CHECK_TYPE 11 -+#define DIMM_REFRESH_INTERVAL 12 -+#define DIMM_SDRAM_WIDTH 13 -+#define DIMM_ERR_CHECK_DATA_WIDTH 14 -+#define DIMM_MIN_CLK_DEL 15 -+#define DIMM_BURST_LEN_SUP 16 -+#define DIMM_DEV_BANK_NUM 17 -+#define DIMM_SUP_CAL 18 -+#define DIMM_DDR2_TYPE_INFORMATION 20 /* DDR2 only */ -+#define DIMM_BUF_ADDR_CONT_IN 21 -+#define DIMM_MIN_CC_AT_MAX_CAS_MINUS1 23 -+#define DIMM_MIN_CC_AT_MAX_CAS_MINUS2 25 -+#define DIMM_MIN_ROW_PRECHARGE_TIME 27 -+#define DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE 28 -+#define DIMM_MIN_RAS_TO_CAS_DELAY 29 -+#define DIMM_MIN_RAS_PULSE_WIDTH 30 -+#define DIMM_BANK_DENSITY 31 -+#define DIMM_MIN_WRITE_RECOVERY_TIME 36 -+#define DIMM_MIN_WRITE_TO_READ_CMD_DELAY 37 -+#define DIMM_MIN_READ_TO_PRECH_CMD_DELAY 38 -+#define DIMM_MIN_REFRESH_TO_ACTIVATE_CMD 42 -+ -+/* Dimm Memory Type values */ -+#define DIMM_MEM_TYPE_SDRAM 0x4 -+#define DIMM_MEM_TYPE_DDR1 0x7 -+#define DIMM_MEM_TYPE_DDR2 0x8 -+ -+#define DIMM_MODULE_MANU_OFFS 64 -+#define DIMM_MODULE_MANU_SIZE 8 -+#define DIMM_MODULE_VEN_OFFS 73 -+#define DIMM_MODULE_VEN_SIZE 25 -+#define DIMM_MODULE_ID_OFFS 99 -+#define DIMM_MODULE_ID_SIZE 18 -+ -+/* enumeration for voltage levels. */ -+typedef enum _mvDimmVoltageIf -+{ -+ TTL_5V_TOLERANT, -+ LVTTL, -+ HSTL_1_5V, -+ SSTL_3_3V, -+ SSTL_2_5V, -+ VOLTAGE_UNKNOWN, -+} MV_DIMM_VOLTAGE_IF; -+ -+ -+/* enumaration for SDRAM CAS Latencies. */ -+typedef enum _mvDimmSdramCas -+{ -+ SD_CL_1 =1, -+ SD_CL_2, -+ SD_CL_3, -+ SD_CL_4, -+ SD_CL_5, -+ SD_CL_6, -+ SD_CL_7, -+ SD_FAULT -+}MV_DIMM_SDRAM_CAS; -+ -+ -+/* DIMM information structure */ -+typedef struct _mvDimmInfo -+{ -+ MV_MEMORY_TYPE memoryType; /* DDR or SDRAM */ -+ -+ MV_U8 spdRawData[SPD_SIZE]; /* Content of SPD-EEPROM copied 1:1 */ -+ -+ /* DIMM dimensions */ -+ MV_U32 numOfRowAddr; -+ MV_U32 numOfColAddr; -+ MV_U32 numOfModuleBanks; -+ MV_U32 dataWidth; -+ MV_U32 errorCheckType; /* ECC , PARITY..*/ -+ MV_U32 sdramWidth; /* 4,8,16 or 32 */ -+ MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ -+ MV_U32 burstLengthSupported; -+ MV_U32 numOfBanksOnEachDevice; -+ MV_U32 suportedCasLatencies; -+ MV_U32 refreshInterval; -+ MV_U32 dimmBankDensity; -+ MV_U32 dimmTypeInfo; /* DDR2 only */ -+ MV_U32 dimmAttributes; -+ -+ /* DIMM timing parameters */ -+ MV_U32 minCycleTimeAtMaxCasLatPs; -+ MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; -+ MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; -+ MV_U32 minRowPrechargeTime; -+ MV_U32 minRowActiveToRowActive; -+ MV_U32 minRasToCasDelay; -+ MV_U32 minRasPulseWidth; -+ MV_U32 minWriteRecoveryTime; /* DDR2 only */ -+ MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ -+ MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ -+ MV_U32 minRefreshToActiveCmd; /* DDR2 only */ -+ -+ /* Parameters calculated from the extracted DIMM information */ -+ MV_U32 size; /* 16,64,128,256 or 512 MByte in MB units */ -+ MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit in MB units */ -+ MV_U32 numberOfDevices; -+ -+} MV_DIMM_INFO; -+ -+ -+MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo); -+MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo); -+MV_VOID dimmSpdPrint(MV_U32 dimmNum); -+MV_STATUS dimmSpdCpy(MV_VOID); -+ -+#endif /* __INCmvDram */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c 2010-11-09 20:28:10.662495471 +0100 -@@ -0,0 +1,1599 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+/* includes */ -+#include "ddr1_2/mvDramIf.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+ -+ -+ -+#ifdef MV_DEBUG -+#define DB(x) x -+#else -+#define DB(x) -+#endif -+ -+/* DRAM bank presence encoding */ -+#define BANK_PRESENT_CS0 0x1 -+#define BANK_PRESENT_CS0_CS1 0x3 -+#define BANK_PRESENT_CS0_CS2 0x5 -+#define BANK_PRESENT_CS0_CS1_CS2 0x7 -+#define BANK_PRESENT_CS0_CS2_CS3 0xd -+#define BANK_PRESENT_CS0_CS2_CS3_CS4 0xf -+ -+/* locals */ -+static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin); -+#if defined(MV_INC_BOARD_DDIM) -+static void sdramDDr2OdtConfig(MV_DRAM_BANK_INFO *pBankInfo); -+static MV_U32 dunitCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas); -+static MV_U32 sdramModeRegCalc(MV_U32 minCas); -+static MV_U32 sdramExtModeRegCalc(MV_DRAM_BANK_INFO *pBankInfo); -+static MV_U32 sdramAddrCtrlRegCalc(MV_DRAM_BANK_INFO *pBankInfo); -+static MV_U32 sdramConfigRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk); -+static MV_U32 minCasCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk, -+ MV_U32 forcedCl); -+static MV_U32 sdramTimeCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, -+ MV_U32 minCas, MV_U32 busClk); -+static MV_U32 sdramTimeCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, -+ MV_U32 busClk); -+ -+/******************************************************************************* -+* mvDramIfDetect - Prepare DRAM interface configuration values. -+* -+* DESCRIPTION: -+* This function implements the full DRAM detection and timing -+* configuration for best system performance. -+* Since this routine runs from a ROM device (Boot Flash), its stack -+* resides on RAM, that might be the system DRAM. Changing DRAM -+* configuration values while keeping vital data in DRAM is risky. That -+* is why the function does not preform the configuration setting but -+* prepare those in predefined 32bit registers (in this case IDMA -+* registers are used) for other routine to perform the settings. -+* The function will call for board DRAM SPD information for each DRAM -+* chip select. The function will then analyze those SPD parameters of -+* all DRAM banks in order to decide on DRAM configuration compatible -+* for all DRAM banks. -+* The function will set the CPU DRAM address decode registers. -+* Note: This routine prepares values that will overide configuration of -+* mvDramBasicAsmInit(). -+* -+* INPUT: -+* forcedCl - Forced CAL Latency. If equal to zero, do not force. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvDramIfDetect(MV_U32 forcedCl) -+{ -+ MV_U32 retVal = MV_OK; /* return value */ -+ MV_DRAM_BANK_INFO bankInfo[MV_DRAM_MAX_CS]; -+ MV_U32 busClk, size, base = 0, i, temp, deviceW, dimmW; -+ MV_U8 minCas; -+ MV_DRAM_DEC_WIN dramDecWin; -+ -+ dramDecWin.addrWin.baseHigh = 0; -+ -+ busClk = mvBoardSysClkGet(); -+ -+ if (0 == busClk) -+ { -+ mvOsPrintf("Dram: ERR. Can't detect system clock! \n"); -+ return MV_ERROR; -+ } -+ -+ /* Close DRAM banks except bank 0 (in case code is excecuting from it...) */ -+#if defined(MV_INCLUDE_SDRAM_CS1) -+ for(i= SDRAM_CS1; i < MV_DRAM_MAX_CS; i++) -+ mvCpuIfTargetWinEnable(i, MV_FALSE); -+#endif -+ -+ /* we will use bank 0 as the representative of the all the DRAM banks, */ -+ /* since bank 0 must exist. */ -+ for(i = 0; i < MV_DRAM_MAX_CS; i++) -+ { -+ /* if Bank exist */ -+ if(MV_OK == mvDramBankInfoGet(i, &bankInfo[i])) -+ { -+ /* check it isn't SDRAM */ -+ if(bankInfo[i].memoryType == MEM_TYPE_SDRAM) -+ { -+ mvOsPrintf("Dram: ERR. SDRAM type not supported !!!\n"); -+ return MV_ERROR; -+ } -+ /* All banks must support registry in order to activate it */ -+ if(bankInfo[i].registeredAddrAndControlInputs != -+ bankInfo[0].registeredAddrAndControlInputs) -+ { -+ mvOsPrintf("Dram: ERR. different Registered settings !!!\n"); -+ return MV_ERROR; -+ } -+ -+ /* Init the CPU window decode */ -+ /* Note that the size in Bank info is in MB units */ -+ /* Note that the Dimm width might be different then the device DRAM width */ -+ temp = MV_REG_READ(SDRAM_CONFIG_REG); -+ -+ deviceW = ((temp & SDRAM_DWIDTH_MASK) == SDRAM_DWIDTH_16BIT )? 16 : 32; -+ dimmW = bankInfo[0].dataWidth - (bankInfo[0].dataWidth % 16); -+ size = ((bankInfo[i].size << 20) / (dimmW/deviceW)); -+ -+ /* We can not change DRAM window settings while excecuting */ -+ /* code from it. That is why we skip the DRAM CS[0], saving */ -+ /* it to the ROM configuration routine */ -+ if(i == SDRAM_CS0) -+ { -+ MV_U32 sizeToReg; -+ -+ /* Translate the given window size to register format */ -+ sizeToReg = ctrlSizeToReg(size, SCSR_SIZE_ALIGNMENT); -+ -+ /* Size parameter validity check. */ -+ if (-1 == sizeToReg) -+ { -+ mvOsPrintf("mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n" -+ ,i); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Size is located at upper 16 bits */ -+ sizeToReg <<= SCSR_SIZE_OFFS; -+ -+ /* enable it */ -+ sizeToReg |= SCSR_WIN_EN; -+ -+ MV_REG_WRITE(DRAM_BUF_REG0, sizeToReg); -+ } -+ else -+ { -+ dramDecWin.addrWin.baseLow = base; -+ dramDecWin.addrWin.size = size; -+ dramDecWin.enable = MV_TRUE; -+ -+ if (MV_OK != mvDramIfWinSet(SDRAM_CS0 + i, &dramDecWin)) -+ { -+ mvOsPrintf("Dram: ERR. Fail to set bank %d!!!\n", -+ SDRAM_CS0 + i); -+ return MV_ERROR; -+ } -+ } -+ -+ base += size; -+ -+ /* update the suportedCasLatencies mask */ -+ bankInfo[0].suportedCasLatencies &= bankInfo[i].suportedCasLatencies; -+ -+ } -+ else -+ { -+ if( i == 0 ) /* bank 0 doesn't exist */ -+ { -+ mvOsPrintf("Dram: ERR. Fail to detect bank 0 !!!\n"); -+ return MV_ERROR; -+ } -+ else -+ { -+ DB(mvOsPrintf("Dram: Could not find bank %d\n", i)); -+ bankInfo[i].size = 0; /* Mark this bank as non exist */ -+ } -+ } -+ } -+ -+ /* calculate minimum CAS */ -+ minCas = minCasCalc(&bankInfo[0], busClk, forcedCl); -+ if (0 == minCas) -+ { -+ mvOsOutput("Dram: Warn: Could not find CAS compatible to SysClk %dMhz\n", -+ (busClk / 1000000)); -+ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ minCas = DDR2_CL_4; /* Continue with this CAS */ -+ mvOsPrintf("Set default CAS latency 4\n"); -+ } -+ else -+ { -+ minCas = DDR1_CL_3; /* Continue with this CAS */ -+ mvOsPrintf("Set default CAS latency 3\n"); -+ } -+ } -+ -+ /* calc SDRAM_CONFIG_REG and save it to temp register */ -+ temp = sdramConfigRegCalc(&bankInfo[0], busClk); -+ if(-1 == temp) -+ { -+ mvOsPrintf("Dram: ERR. sdramConfigRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG1, temp); -+ -+ /* calc SDRAM_MODE_REG and save it to temp register */ -+ temp = sdramModeRegCalc(minCas); -+ if(-1 == temp) -+ { -+ mvOsPrintf("Dram: ERR. sdramModeRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG2, temp); -+ -+ /* calc SDRAM_EXTENDED_MODE_REG and save it to temp register */ -+ temp = sdramExtModeRegCalc(&bankInfo[0]); -+ if(-1 == temp) -+ { -+ mvOsPrintf("Dram: ERR. sdramModeRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG10, temp); -+ -+ /* calc D_UNIT_CONTROL_LOW and save it to temp register */ -+ temp = dunitCtrlLowRegCalc(&bankInfo[0], minCas); -+ if(-1 == temp) -+ { -+ mvOsPrintf("Dram: ERR. dunitCtrlLowRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG3, temp); -+ -+ /* calc SDRAM_ADDR_CTRL_REG and save it to temp register */ -+ temp = sdramAddrCtrlRegCalc(&bankInfo[0]); -+ if(-1 == temp) -+ { -+ mvOsPrintf("Dram: ERR. sdramAddrCtrlRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG4, temp); -+ -+ /* calc SDRAM_TIMING_CTRL_LOW_REG and save it to temp register */ -+ temp = sdramTimeCtrlLowRegCalc(&bankInfo[0], minCas, busClk); -+ if(-1 == temp) -+ { -+ mvOsPrintf("Dram: ERR. sdramTimeCtrlLowRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG5, temp); -+ -+ /* calc SDRAM_TIMING_CTRL_HIGH_REG and save it to temp register */ -+ temp = sdramTimeCtrlHighRegCalc(&bankInfo[0], busClk); -+ if(-1 == temp) -+ { -+ mvOsPrintf("Dram: ERR. sdramTimeCtrlHighRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG6, temp); -+ -+ /* Config DDR2 On Die Termination (ODT) registers */ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ sdramDDr2OdtConfig(bankInfo); -+ } -+ -+ /* Note that DDR SDRAM Address/Control and Data pad calibration */ -+ /* settings is done in mvSdramIfConfig.s */ -+ -+ return retVal; -+} -+ -+/******************************************************************************* -+* minCasCalc - Calculate the Minimum CAS latency which can be used. -+* -+* DESCRIPTION: -+* Calculate the minimum CAS latency that can be used, base on the DRAM -+* parameters and the SDRAM bus Clock freq. -+* -+* INPUT: -+* busClk - the DRAM bus Clock. -+* pBankInfo - bank info parameters. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* The minimum CAS Latency. The function returns 0 if max CAS latency -+* supported by banks is incompatible with system bus clock frequancy. -+* -+*******************************************************************************/ -+static MV_U32 minCasCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk, -+ MV_U32 forcedCl) -+{ -+ MV_U32 count = 1, j; -+ MV_U32 busClkPs = 1000000000 / (busClk / 1000); /* in ps units */ -+ MV_U32 startBit, stopBit; -+ -+ /* DDR 1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * -+ *********************************************************/ -+ -+ /* DDR 2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * -+ *********************************************************/ -+ -+ -+ /* If we are asked to use the forced CAL */ -+ if (forcedCl) -+ { -+ mvOsPrintf("DRAM: Using forced CL %d.%d\n", (forcedCl / 10), -+ (forcedCl % 10)); -+ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ if (forcedCl == 30) -+ pBankInfo->suportedCasLatencies = 0x08; -+ else if (forcedCl == 40) -+ pBankInfo->suportedCasLatencies = 0x10; -+ else -+ { -+ mvOsPrintf("Forced CL %d.%d not supported. Set default CL 4\n", -+ (forcedCl / 10), (forcedCl % 10)); -+ pBankInfo->suportedCasLatencies = 0x10; -+ } -+ } -+ else -+ { -+ if (forcedCl == 15) -+ pBankInfo->suportedCasLatencies = 0x02; -+ else if (forcedCl == 20) -+ pBankInfo->suportedCasLatencies = 0x04; -+ else if (forcedCl == 25) -+ pBankInfo->suportedCasLatencies = 0x08; -+ else if (forcedCl == 30) -+ pBankInfo->suportedCasLatencies = 0x10; -+ else if (forcedCl == 40) -+ pBankInfo->suportedCasLatencies = 0x40; -+ else -+ { -+ mvOsPrintf("Forced CL %d.%d not supported. Set default CL 3\n", -+ (forcedCl / 10), (forcedCl % 10)); -+ pBankInfo->suportedCasLatencies = 0x10; -+ } -+ } -+ -+ return pBankInfo->suportedCasLatencies; -+ } -+ -+ /* go over the supported cas mask from Max Cas down and check if the */ -+ /* SysClk stands in its time requirments. */ -+ -+ -+ DB(mvOsPrintf("Dram: minCasCalc supported mask = %x busClkPs = %x \n", -+ pBankInfo->suportedCasLatencies,busClkPs )); -+ for(j = 7; j > 0; j--) -+ { -+ if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) -+ { -+ /* Reset the bits for CL incompatible for the sysClk */ -+ switch (count) -+ { -+ case 1: -+ if (pBankInfo->minCycleTimeAtMaxCasLatPs > busClkPs) -+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ case 2: -+ if (pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps > busClkPs) -+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ case 3: -+ if (pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps > busClkPs) -+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ default: -+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); -+ break; -+ } -+ } -+ } -+ -+ DB(mvOsPrintf("Dram: minCasCalc support = %x (after SysCC calc)\n", -+ pBankInfo->suportedCasLatencies )); -+ -+ /* SDRAM DDR1 controller supports CL 1.5 to 3.5 */ -+ /* SDRAM DDR2 controller supports CL 3 to 5 */ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ startBit = 3; /* DDR2 support CL start with CL3 (bit 3) */ -+ stopBit = 5; /* DDR2 support CL stops with CL5 (bit 5) */ -+ } -+ else -+ { -+ startBit = 1; /* DDR1 support CL start with CL1.5 (bit 3) */ -+ stopBit = 4; /* DDR1 support CL stops with CL3 (bit 4) */ -+ } -+ -+ for(j = startBit; j <= stopBit ; j++) -+ { -+ if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) -+ { -+ DB(mvOsPrintf("Dram: minCasCalc choose CAS %x \n",(BIT0 << j))); -+ return (BIT0 << j); -+ } -+ } -+ -+ return 0; -+} -+ -+/******************************************************************************* -+* sdramConfigRegCalc - Calculate sdram config register -+* -+* DESCRIPTION: Calculate sdram config register optimized value based -+* on the bank info parameters. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram config reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramConfigRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) -+{ -+ MV_U32 sdramConfig = 0; -+ MV_U32 refreshPeriod; -+ -+ busClk /= 1000000; /* we work with busClk in MHz */ -+ -+ sdramConfig = MV_REG_READ(SDRAM_CONFIG_REG); -+ -+ /* figure out the memory refresh internal */ -+ switch (pBankInfo->refreshInterval & 0xf) -+ { -+ case 0x0: /* refresh period is 15.625 usec */ -+ refreshPeriod = 15625; -+ break; -+ case 0x1: /* refresh period is 3.9 usec */ -+ refreshPeriod = 3900; -+ break; -+ case 0x2: /* refresh period is 7.8 usec */ -+ refreshPeriod = 7800; -+ break; -+ case 0x3: /* refresh period is 31.3 usec */ -+ refreshPeriod = 31300; -+ break; -+ case 0x4: /* refresh period is 62.5 usec */ -+ refreshPeriod = 62500; -+ break; -+ case 0x5: /* refresh period is 125 usec */ -+ refreshPeriod = 125000; -+ break; -+ default: /* refresh period undefined */ -+ mvOsPrintf("Dram: ERR. DRAM refresh period is unknown!\n"); -+ return -1; -+ } -+ -+ /* Now the refreshPeriod is in register format value */ -+ refreshPeriod = (busClk * refreshPeriod) / 1000; -+ -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc calculated refresh interval %0x\n", -+ refreshPeriod)); -+ -+ /* make sure the refresh value is only 14 bits */ -+ if(refreshPeriod > SDRAM_REFRESH_MAX) -+ { -+ refreshPeriod = SDRAM_REFRESH_MAX; -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc adjusted refresh interval %0x\n", -+ refreshPeriod)); -+ } -+ -+ /* Clear the refresh field */ -+ sdramConfig &= ~SDRAM_REFRESH_MASK; -+ -+ /* Set new value to refresh field */ -+ sdramConfig |= (refreshPeriod & SDRAM_REFRESH_MASK); -+ -+ /* registered DRAM ? */ -+ if ( pBankInfo->registeredAddrAndControlInputs ) -+ { -+ /* it's registered DRAM, so set the reg. DRAM bit */ -+ sdramConfig |= SDRAM_REGISTERED; -+ mvOsPrintf("DRAM Attribute: Registered address and control inputs.\n"); -+ } -+ -+ /* set DDR SDRAM devices configuration */ -+ sdramConfig &= ~SDRAM_DCFG_MASK; /* Clear Dcfg field */ -+ -+ switch (pBankInfo->sdramWidth) -+ { -+ case 8: /* memory is x8 */ -+ sdramConfig |= SDRAM_DCFG_X8_DEV; -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc SDRAM device width x8\n")); -+ break; -+ case 16: -+ sdramConfig |= SDRAM_DCFG_X16_DEV; -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc SDRAM device width x16\n")); -+ break; -+ default: /* memory width unsupported */ -+ mvOsPrintf("Dram: ERR. DRAM chip width is unknown!\n"); -+ return -1; -+ } -+ -+ /* Set static default settings */ -+ sdramConfig |= SDRAM_CONFIG_DV; -+ -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc set sdramConfig to 0x%x\n", -+ sdramConfig)); -+ -+ return sdramConfig; -+} -+ -+/******************************************************************************* -+* sdramModeRegCalc - Calculate sdram mode register -+* -+* DESCRIPTION: Calculate sdram mode register optimized value based -+* on the bank info parameters and the minCas. -+* -+* INPUT: -+* minCas - minimum CAS supported. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram mode reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramModeRegCalc(MV_U32 minCas) -+{ -+ MV_U32 sdramMode; -+ -+ sdramMode = MV_REG_READ(SDRAM_MODE_REG); -+ -+ /* Clear CAS Latency field */ -+ sdramMode &= ~SDRAM_CL_MASK; -+ -+ mvOsPrintf("DRAM CAS Latency "); -+ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ switch (minCas) -+ { -+ case DDR2_CL_3: -+ sdramMode |= SDRAM_DDR2_CL_3; -+ mvOsPrintf("3.\n"); -+ break; -+ case DDR2_CL_4: -+ sdramMode |= SDRAM_DDR2_CL_4; -+ mvOsPrintf("4.\n"); -+ break; -+ case DDR2_CL_5: -+ sdramMode |= SDRAM_DDR2_CL_5; -+ mvOsPrintf("5.\n"); -+ break; -+ default: -+ mvOsPrintf("\nsdramModeRegCalc ERROR: Max. CL out of range\n"); -+ return -1; -+ } -+ sdramMode |= DDR2_MODE_REG_DV; -+ } -+ else /* DDR1 */ -+ { -+ switch (minCas) -+ { -+ case DDR1_CL_1_5: -+ sdramMode |= SDRAM_DDR1_CL_1_5; -+ mvOsPrintf("1.5\n"); -+ break; -+ case DDR1_CL_2: -+ sdramMode |= SDRAM_DDR1_CL_2; -+ mvOsPrintf("2\n"); -+ break; -+ case DDR1_CL_2_5: -+ sdramMode |= SDRAM_DDR1_CL_2_5; -+ mvOsPrintf("2.5\n"); -+ break; -+ case DDR1_CL_3: -+ sdramMode |= SDRAM_DDR1_CL_3; -+ mvOsPrintf("3\n"); -+ break; -+ case DDR1_CL_4: -+ sdramMode |= SDRAM_DDR1_CL_4; -+ mvOsPrintf("4\n"); -+ break; -+ default: -+ mvOsPrintf("\nsdramModeRegCalc ERROR: Max. CL out of range\n"); -+ return -1; -+ } -+ sdramMode |= DDR1_MODE_REG_DV; -+ } -+ -+ DB(mvOsPrintf("nsdramModeRegCalc register 0x%x\n", sdramMode )); -+ -+ return sdramMode; -+} -+ -+/******************************************************************************* -+* sdramExtModeRegCalc - Calculate sdram Extended mode register -+* -+* DESCRIPTION: -+* Return sdram Extended mode register value based -+* on the bank info parameters and bank presence. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram Extended mode reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramExtModeRegCalc(MV_DRAM_BANK_INFO *pBankInfo) -+{ -+ MV_U32 populateBanks = 0; -+ int bankNum; -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ /* Represent the populate banks in binary form */ -+ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ if (0 != pBankInfo[bankNum].size) -+ { -+ populateBanks |= (1 << bankNum); -+ } -+ } -+ -+ switch(populateBanks) -+ { -+ case(BANK_PRESENT_CS0): -+ return DDR_SDRAM_EXT_MODE_CS0_DV; -+ -+ case(BANK_PRESENT_CS0_CS1): -+ return DDR_SDRAM_EXT_MODE_CS0_DV; -+ -+ case(BANK_PRESENT_CS0_CS2): -+ return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; -+ -+ case(BANK_PRESENT_CS0_CS1_CS2): -+ return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; -+ -+ case(BANK_PRESENT_CS0_CS2_CS3): -+ return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; -+ -+ case(BANK_PRESENT_CS0_CS2_CS3_CS4): -+ return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; -+ -+ default: -+ mvOsPrintf("sdramExtModeRegCalc: Invalid DRAM bank presence\n"); -+ return -1; -+ } -+ } -+ return 0; -+} -+ -+/******************************************************************************* -+* dunitCtrlLowRegCalc - Calculate sdram dunit control low register -+* -+* DESCRIPTION: Calculate sdram dunit control low register optimized value based -+* on the bank info parameters and the minCas. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* minCas - minimum CAS supported. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram dunit control low reg value. -+* -+*******************************************************************************/ -+static MV_U32 dunitCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas) -+{ -+ MV_U32 dunitCtrlLow; -+ -+ dunitCtrlLow = MV_REG_READ(SDRAM_DUNIT_CTRL_REG); -+ -+ /* Clear StBurstDel field */ -+ dunitCtrlLow &= ~SDRAM_ST_BURST_DEL_MASK; -+ -+#ifdef MV_88W8660 -+ /* Clear address/control output timing field */ -+ dunitCtrlLow &= ~SDRAM_CTRL_POS_RISE; -+#endif /* MV_88W8660 */ -+ -+ DB(mvOsPrintf("Dram: dunitCtrlLowRegCalc\n")); -+ -+ /* For proper sample of read data set the Dunit Control register's */ -+ /* stBurstDel bits [27:24] */ -+ /********-********-********-********-********-********* -+ * CL=1.5 | CL=2 | CL=2.5 | CL=3 | CL=4 | CL=5 * -+ *********-********-********-********-********-********* -+Not Reg. * 0011 | 0011 | 0100 | 0100 | 0101 | TBD * -+ *********-********-********-********-********-********* -+Registered * 0100 | 0100 | 0101 | 0101 | 0110 | TBD * -+ *********-********-********-********-********-*********/ -+ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ switch (minCas) -+ { -+ case DDR2_CL_3: -+ /* registerd DDR SDRAM? */ -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; -+ else -+ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; -+ break; -+ case DDR2_CL_4: -+ /* registerd DDR SDRAM? */ -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ dunitCtrlLow |= 0x6 << SDRAM_ST_BURST_DEL_OFFS; -+ else -+ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; -+ break; -+ default: -+ mvOsPrintf("Dram: dunitCtrlLowRegCalc Max. CL out of range %d\n", -+ minCas); -+ return -1; -+ } -+ } -+ else /* DDR1 */ -+ { -+ switch (minCas) -+ { -+ case DDR1_CL_1_5: -+ /* registerd DDR SDRAM? */ -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; -+ else -+ dunitCtrlLow |= 0x3 << SDRAM_ST_BURST_DEL_OFFS; -+ break; -+ case DDR1_CL_2: -+ /* registerd DDR SDRAM? */ -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; -+ else -+ dunitCtrlLow |= 0x3 << SDRAM_ST_BURST_DEL_OFFS; -+ break; -+ case DDR1_CL_2_5: -+ /* registerd DDR SDRAM? */ -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; -+ else -+ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; -+ break; -+ case DDR1_CL_3: -+ /* registerd DDR SDRAM? */ -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; -+ else -+ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; -+ break; -+ case DDR1_CL_4: -+ /* registerd DDR SDRAM? */ -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ dunitCtrlLow |= 0x6 << SDRAM_ST_BURST_DEL_OFFS; -+ else -+ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; -+ break; -+ default: -+ mvOsPrintf("Dram: dunitCtrlLowRegCalc Max. CL out of range %d\n", -+ minCas); -+ return -1; -+ } -+ -+ } -+ DB(mvOsPrintf("Dram: Reg dunit control low = %x\n", dunitCtrlLow )); -+ -+ return dunitCtrlLow; -+} -+ -+/******************************************************************************* -+* sdramAddrCtrlRegCalc - Calculate sdram address control register -+* -+* DESCRIPTION: Calculate sdram address control register optimized value based -+* on the bank info parameters and the minCas. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram address control reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramAddrCtrlRegCalc(MV_DRAM_BANK_INFO *pBankInfo) -+{ -+ MV_U32 addrCtrl = 0; -+ -+ /* Set Address Control register static configuration bits */ -+ addrCtrl = MV_REG_READ(SDRAM_ADDR_CTRL_REG); -+ -+ /* Set address control default value */ -+ addrCtrl |= SDRAM_ADDR_CTRL_DV; -+ -+ /* Clear DSize field */ -+ addrCtrl &= ~SDRAM_DSIZE_MASK; -+ -+ /* Note that density is in MB units */ -+ switch (pBankInfo->deviceDensity) -+ { -+ case 128: /* 128 Mbit */ -+ DB(mvOsPrintf("DRAM Device Density 128Mbit\n")); -+ addrCtrl |= SDRAM_DSIZE_128Mb; -+ break; -+ case 256: /* 256 Mbit */ -+ DB(mvOsPrintf("DRAM Device Density 256Mbit\n")); -+ addrCtrl |= SDRAM_DSIZE_256Mb; -+ break; -+ case 512: /* 512 Mbit */ -+ DB(mvOsPrintf("DRAM Device Density 512Mbit\n")); -+ addrCtrl |= SDRAM_DSIZE_512Mb; -+ break; -+ default: -+ mvOsPrintf("Dram: sdramAddrCtrl unsupported RAM-Device size %d\n", -+ pBankInfo->deviceDensity); -+ return -1; -+ } -+ -+ /* SDRAM address control */ -+ DB(mvOsPrintf("Dram: setting sdram address control with: %x \n", addrCtrl)); -+ -+ return addrCtrl; -+} -+ -+/******************************************************************************* -+* sdramTimeCtrlLowRegCalc - Calculate sdram timing control low register -+* -+* DESCRIPTION: -+* This function calculates sdram timing control low register -+* optimized value based on the bank info parameters and the minCas. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* busClk - Bus clock -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram timinf control low reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramTimeCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, -+ MV_U32 minCas, MV_U32 busClk) -+{ -+ MV_U32 tRp = 0; -+ MV_U32 tRrd = 0; -+ MV_U32 tRcd = 0; -+ MV_U32 tRas = 0; -+ MV_U32 tWr = 0; -+ MV_U32 tWtr = 0; -+ MV_U32 tRtp = 0; -+ -+ MV_U32 bankNum; -+ -+ busClk = busClk / 1000000; /* In MHz */ -+ -+ /* Scan all DRAM banks to find maximum timing values */ -+ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ tRp = MV_MAX(tRp, pBankInfo[bankNum].minRowPrechargeTime); -+ tRrd = MV_MAX(tRrd, pBankInfo[bankNum].minRowActiveToRowActive); -+ tRcd = MV_MAX(tRcd, pBankInfo[bankNum].minRasToCasDelay); -+ tRas = MV_MAX(tRas, pBankInfo[bankNum].minRasPulseWidth); -+ } -+ -+ /* Extract timing (in ns) from SPD value. We ignore the tenth ns part. */ -+ /* by shifting the data two bits right. */ -+ tRp = tRp >> 2; /* For example 0x50 -> 20ns */ -+ tRrd = tRrd >> 2; -+ tRcd = tRcd >> 2; -+ -+ /* Extract clock cycles from time parameter. We need to round up */ -+ tRp = ((busClk * tRp) / 1000) + (((busClk * tRp) % 1000) ? 1 : 0); -+ /* Micron work around for 133MHz */ -+ if (busClk == 133) -+ tRp += 1; -+ DB(mvOsPrintf("Dram Timing Low: tRp = %d ", tRp)); -+ tRrd = ((busClk * tRrd) / 1000) + (((busClk * tRrd) % 1000) ? 1 : 0); -+ /* JEDEC min reqeirments tRrd = 2 */ -+ if (tRrd < 2) -+ tRrd = 2; -+ DB(mvOsPrintf("tRrd = %d ", tRrd)); -+ tRcd = ((busClk * tRcd) / 1000) + (((busClk * tRcd) % 1000) ? 1 : 0); -+ DB(mvOsPrintf("tRcd = %d ", tRcd)); -+ tRas = ((busClk * tRas) / 1000) + (((busClk * tRas) % 1000) ? 1 : 0); -+ DB(mvOsPrintf("tRas = %d ", tRas)); -+ -+ /* tWr and tWtr is different for DDR1 and DDR2. tRtp is only for DDR2 */ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ /* Scan all DRAM banks to find maximum timing values */ -+ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ tWr = MV_MAX(tWr, pBankInfo[bankNum].minWriteRecoveryTime); -+ tWtr = MV_MAX(tWtr, pBankInfo[bankNum].minWriteToReadCmdDelay); -+ tRtp = MV_MAX(tRtp, pBankInfo[bankNum].minReadToPrechCmdDelay); -+ } -+ -+ /* Extract timing (in ns) from SPD value. We ignore the tenth ns */ -+ /* part by shifting the data two bits right. */ -+ tWr = tWr >> 2; /* For example 0x50 -> 20ns */ -+ tWtr = tWtr >> 2; -+ tRtp = tRtp >> 2; -+ -+ /* Extract clock cycles from time parameter. We need to round up */ -+ tWr = ((busClk * tWr) / 1000) + (((busClk * tWr) % 1000) ? 1 : 0); -+ DB(mvOsPrintf("tWr = %d ", tWr)); -+ tWtr = ((busClk * tWtr) / 1000) + (((busClk * tWtr) % 1000) ? 1 : 0); -+ /* JEDEC min reqeirments tWtr = 2 */ -+ if (tWtr < 2) -+ tWtr = 2; -+ DB(mvOsPrintf("tWtr = %d ", tWtr)); -+ tRtp = ((busClk * tRtp) / 1000) + (((busClk * tRtp) % 1000) ? 1 : 0); -+ /* JEDEC min reqeirments tRtp = 2 */ -+ if (tRtp < 2) -+ tRtp = 2; -+ DB(mvOsPrintf("tRtp = %d ", tRtp)); -+ } -+ else -+ { -+ tWr = ((busClk*SDRAM_TWR) / 1000) + (((busClk*SDRAM_TWR) % 1000)?1:0); -+ -+ if ((200 == busClk) || ((100 == busClk) && (DDR1_CL_1_5 == minCas))) -+ { -+ tWtr = 2; -+ } -+ else -+ { -+ tWtr = 1; -+ } -+ -+ tRtp = 2; /* Must be set to 0x1 (two cycles) when using DDR1 */ -+ } -+ -+ DB(mvOsPrintf("tWtr = %d\n", tWtr)); -+ -+ /* Note: value of 0 in register means one cycle, 1 means two and so on */ -+ return (((tRp - 1) << SDRAM_TRP_OFFS) | -+ ((tRrd - 1) << SDRAM_TRRD_OFFS) | -+ ((tRcd - 1) << SDRAM_TRCD_OFFS) | -+ ((tRas - 1) << SDRAM_TRAS_OFFS) | -+ ((tWr - 1) << SDRAM_TWR_OFFS) | -+ ((tWtr - 1) << SDRAM_TWTR_OFFS) | -+ ((tRtp - 1) << SDRAM_TRTP_OFFS)); -+} -+ -+/******************************************************************************* -+* sdramTimeCtrlHighRegCalc - Calculate sdram timing control high register -+* -+* DESCRIPTION: -+* This function calculates sdram timing control high register -+* optimized value based on the bank info parameters and the bus clock. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* busClk - Bus clock -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram timinf control high reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramTimeCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, -+ MV_U32 busClk) -+{ -+ MV_U32 tRfc; -+ MV_U32 timeNs = 0; -+ int bankNum; -+ MV_U32 sdramTw2wCyc = 0; -+ -+ busClk = busClk / 1000000; /* In MHz */ -+ -+ /* tRfc is different for DDR1 and DDR2. */ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ MV_U32 bankNum; -+ -+ /* Scan all DRAM banks to find maximum timing values */ -+ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ timeNs = MV_MAX(timeNs, pBankInfo[bankNum].minRefreshToActiveCmd); -+ } -+ else -+ { -+ if (pBankInfo[0].deviceDensity == _1G) -+ { -+ timeNs = SDRAM_TRFC_1G; -+ } -+ else -+ { -+ if (200 == busClk) -+ { -+ timeNs = SDRAM_TRFC_64_512M_AT_200MHZ; -+ } -+ else -+ { -+ timeNs = SDRAM_TRFC_64_512M; -+ } -+ } -+ } -+ -+ tRfc = ((busClk * timeNs) / 1000) + (((busClk * timeNs) % 1000) ? 1 : 0); -+ -+ DB(mvOsPrintf("Dram Timing High: tRfc = %d\n", tRfc)); -+ -+ -+ /* Represent the populate banks in binary form */ -+ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ if (0 != pBankInfo[bankNum].size) -+ sdramTw2wCyc++; -+ } -+ -+ /* If we have more the 1 bank then we need the TW2W in 1 for ODT switch */ -+ if (sdramTw2wCyc > 1) -+ sdramTw2wCyc = 1; -+ else -+ sdramTw2wCyc = 0; -+ -+ /* Note: value of 0 in register means one cycle, 1 means two and so on */ -+ return ((((tRfc - 1) & SDRAM_TRFC_MASK) << SDRAM_TRFC_OFFS) | -+ ((SDRAM_TR2R_CYC - 1) << SDRAM_TR2R_OFFS) | -+ ((SDRAM_TR2WW2R_CYC - 1) << SDRAM_TR2W_W2R_OFFS) | -+ (((tRfc - 1) >> 4) << SDRAM_TRFC_EXT_OFFS) | -+ (sdramTw2wCyc << SDRAM_TW2W_OFFS)); -+ -+} -+ -+/******************************************************************************* -+* sdramDDr2OdtConfig - Set DRAM DDR2 On Die Termination registers. -+* -+* DESCRIPTION: -+* This function config DDR2 On Die Termination (ODT) registers. -+* ODT configuration is done according to DIMM presence: -+* -+* Presence Ctrl Low Ctrl High Dunit Ctrl Ext Mode -+* CS0 0x84210000 0x00000000 0x0000780F 0x00000440 -+* CS0+CS1 0x84210000 0x00000000 0x0000780F 0x00000440 -+* CS0+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 -+* CS0+CS1+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 -+* CS0+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 -+* CS0+CS1+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 -+* -+* INPUT: -+* pBankInfo - bank info parameters. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* None -+*******************************************************************************/ -+static void sdramDDr2OdtConfig(MV_DRAM_BANK_INFO *pBankInfo) -+{ -+ MV_U32 populateBanks = 0; -+ MV_U32 odtCtrlLow, odtCtrlHigh, dunitOdtCtrl; -+ int bankNum; -+ -+ /* Represent the populate banks in binary form */ -+ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ if (0 != pBankInfo[bankNum].size) -+ { -+ populateBanks |= (1 << bankNum); -+ } -+ } -+ -+ switch(populateBanks) -+ { -+ case(BANK_PRESENT_CS0): -+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_DV; -+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_DV; -+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_DV; -+ break; -+ case(BANK_PRESENT_CS0_CS1): -+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_DV; -+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_DV; -+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_DV; -+ break; -+ case(BANK_PRESENT_CS0_CS2): -+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; -+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; -+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; -+ break; -+ case(BANK_PRESENT_CS0_CS1_CS2): -+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; -+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; -+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; -+ break; -+ case(BANK_PRESENT_CS0_CS2_CS3): -+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; -+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; -+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; -+ break; -+ case(BANK_PRESENT_CS0_CS2_CS3_CS4): -+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; -+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; -+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; -+ break; -+ default: -+ mvOsPrintf("sdramDDr2OdtConfig: Invalid DRAM bank presence\n"); -+ return; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG7, odtCtrlLow); -+ MV_REG_WRITE(DRAM_BUF_REG8, odtCtrlHigh); -+ MV_REG_WRITE(DRAM_BUF_REG9, dunitOdtCtrl); -+ return; -+} -+#endif /* defined(MV_INC_BOARD_DDIM) */ -+ -+/******************************************************************************* -+* mvDramIfWinSet - Set DRAM interface address decode window -+* -+* DESCRIPTION: -+* This function sets DRAM interface address decode window. -+* -+* INPUT: -+* target - System target. Use only SDRAM targets. -+* pAddrDecWin - SDRAM address window structure. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK -+* otherwise. -+*******************************************************************************/ -+MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) -+{ -+ MV_U32 baseReg=0,sizeReg=0; -+ MV_U32 baseToReg=0 , sizeToReg=0; -+ -+ /* Check parameters */ -+ if (!MV_TARGET_IS_DRAM(target)) -+ { -+ mvOsPrintf("mvDramIfWinSet: target %d is not SDRAM\n", target); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlaps with current enabled windows */ -+ if (MV_TRUE == sdramIfWinOverlap(target, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("mvDramIfWinSet: ERR. Target %d overlaps\n", target); -+ return MV_BAD_PARAM; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvDramIfWinSet:Error setting DRAM interface window %d."\ -+ "\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ target, -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ /* read base register*/ -+ baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(target)); -+ -+ /* read size register */ -+ sizeReg = MV_REG_READ(SDRAM_SIZE_REG(target)); -+ -+ /* BaseLow[31:16] => base register [31:16] */ -+ baseToReg = pAddrDecWin->addrWin.baseLow & SCBAR_BASE_MASK; -+ -+ /* Write to address decode Base Address Register */ -+ baseReg &= ~SCBAR_BASE_MASK; -+ baseReg |= baseToReg; -+ -+ /* Translate the given window size to register format */ -+ sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, SCSR_SIZE_ALIGNMENT); -+ -+ /* Size parameter validity check. */ -+ if (-1 == sizeToReg) -+ { -+ mvOsPrintf("mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n",target); -+ return MV_BAD_PARAM; -+ } -+ -+ /* set size */ -+ sizeReg &= ~SCSR_SIZE_MASK; -+ /* Size is located at upper 16 bits */ -+ sizeReg |= (sizeToReg << SCSR_SIZE_OFFS); -+ -+ /* enable/Disable */ -+ if (MV_TRUE == pAddrDecWin->enable) -+ { -+ sizeReg |= SCSR_WIN_EN; -+ } -+ else -+ { -+ sizeReg &= ~SCSR_WIN_EN; -+ } -+ -+ /* 3) Write to address decode Base Address Register */ -+ MV_REG_WRITE(SDRAM_BASE_ADDR_REG(target), baseReg); -+ -+ /* Write to address decode Size Register */ -+ MV_REG_WRITE(SDRAM_SIZE_REG(target), sizeReg); -+ -+ return MV_OK; -+} -+/******************************************************************************* -+* mvDramIfWinGet - Get DRAM interface address decode window -+* -+* DESCRIPTION: -+* This function gets DRAM interface address decode window. -+* -+* INPUT: -+* target - System target. Use only SDRAM targets. -+* -+* OUTPUT: -+* pAddrDecWin - SDRAM address window structure. -+* -+* RETURN: -+* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK -+* otherwise. -+*******************************************************************************/ -+MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) -+{ -+ MV_U32 baseReg,sizeReg; -+ MV_U32 sizeRegVal; -+ -+ /* Check parameters */ -+ if (!MV_TARGET_IS_DRAM(target)) -+ { -+ mvOsPrintf("mvDramIfWinGet: target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ /* Read base and size registers */ -+ sizeReg = MV_REG_READ(SDRAM_SIZE_REG(target)); -+ baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(target)); -+ -+ sizeRegVal = (sizeReg & SCSR_SIZE_MASK) >> SCSR_SIZE_OFFS; -+ -+ pAddrDecWin->addrWin.size = ctrlRegToSize(sizeRegVal, -+ SCSR_SIZE_ALIGNMENT); -+ -+ /* Check if ctrlRegToSize returned OK */ -+ if (-1 == pAddrDecWin->addrWin.size) -+ { -+ mvOsPrintf("mvDramIfWinGet: size of target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ /* Extract base address */ -+ /* Base register [31:16] ==> baseLow[31:16] */ -+ pAddrDecWin->addrWin.baseLow = baseReg & SCBAR_BASE_MASK; -+ -+ pAddrDecWin->addrWin.baseHigh = 0; -+ -+ -+ if (sizeReg & SCSR_WIN_EN) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ } -+ -+ return MV_OK; -+} -+/******************************************************************************* -+* mvDramIfWinEnable - Enable/Disable SDRAM address decode window -+* -+* DESCRIPTION: -+* This function enable/Disable SDRAM address decode window. -+* -+* INPUT: -+* target - System target. Use only SDRAM targets. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR in case function parameter are invalid, MV_OK otherewise. -+* -+*******************************************************************************/ -+MV_STATUS mvDramIfWinEnable(MV_TARGET target,MV_BOOL enable) -+{ -+ MV_DRAM_DEC_WIN addrDecWin; -+ -+ /* Check parameters */ -+ if (!MV_TARGET_IS_DRAM(target)) -+ { -+ mvOsPrintf("mvDramIfWinEnable: target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ if (enable == MV_TRUE) -+ { /* First check for overlap with other enabled windows */ -+ if (MV_OK != mvDramIfWinGet(target, &addrDecWin)) -+ { -+ mvOsPrintf("mvDramIfWinEnable:ERR. Getting target %d failed.\n", -+ target); -+ return MV_ERROR; -+ } -+ /* Check for overlapping */ -+ if (MV_FALSE == sdramIfWinOverlap(target, &(addrDecWin.addrWin))) -+ { -+ /* No Overlap. Enable address decode winNum window */ -+ MV_REG_BIT_SET(SDRAM_SIZE_REG(target), SCSR_WIN_EN); -+ } -+ else -+ { /* Overlap detected */ -+ mvOsPrintf("mvDramIfWinEnable: ERR. Target %d overlap detect\n", -+ target); -+ return MV_ERROR; -+ } -+ } -+ else -+ { /* Disable address decode winNum window */ -+ MV_REG_BIT_RESET(SDRAM_SIZE_REG(target), SCSR_WIN_EN); -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* sdramIfWinOverlap - Check if an address window overlap an SDRAM address window -+* -+* DESCRIPTION: -+* This function scan each SDRAM address decode window to test if it -+* overlapps the given address windoow -+* -+* INPUT: -+* target - SDRAM target where the function skips checking. -+* pAddrDecWin - The tested address window for overlapping with -+* SDRAM windows. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlaps any enabled address -+* decode map, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_TARGET targetNum; -+ MV_DRAM_DEC_WIN addrDecWin; -+ -+ for(targetNum = SDRAM_CS0; targetNum < MV_DRAM_MAX_CS ; targetNum++) -+ { -+ /* don't check our winNum or illegal targets */ -+ if (targetNum == target) -+ { -+ continue; -+ } -+ -+ /* Get window parameters */ -+ if (MV_OK != mvDramIfWinGet(targetNum, &addrDecWin)) -+ { -+ mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); -+ return MV_ERROR; -+ } -+ -+ /* Do not check disabled windows */ -+ if (MV_FALSE == addrDecWin.enable) -+ { -+ continue; -+ } -+ -+ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) -+ { -+ mvOsPrintf( -+ "sdramIfWinOverlap: Required target %d overlap winNum %d\n", -+ target, targetNum); -+ return MV_TRUE; -+ } -+ } -+ -+ return MV_FALSE; -+} -+ -+/******************************************************************************* -+* mvDramIfBankSizeGet - Get DRAM interface bank size. -+* -+* DESCRIPTION: -+* This function returns the size of a given DRAM bank. -+* -+* INPUT: -+* bankNum - Bank number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* DRAM bank size. If bank is disabled the function return '0'. In case -+* or paramter is invalid, the function returns -1. -+* -+*******************************************************************************/ -+MV_32 mvDramIfBankSizeGet(MV_U32 bankNum) -+{ -+ MV_DRAM_DEC_WIN addrDecWin; -+ -+ /* Check parameters */ -+ if (!MV_TARGET_IS_DRAM(bankNum)) -+ { -+ mvOsPrintf("mvDramIfBankBaseGet: bankNum %d is invalid\n", bankNum); -+ return -1; -+ } -+ /* Get window parameters */ -+ if (MV_OK != mvDramIfWinGet(bankNum, &addrDecWin)) -+ { -+ mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); -+ return -1; -+ } -+ -+ if (MV_TRUE == addrDecWin.enable) -+ { -+ return addrDecWin.addrWin.size; -+ } -+ else -+ { -+ return 0; -+ } -+} -+ -+ -+/******************************************************************************* -+* mvDramIfSizeGet - Get DRAM interface total size. -+* -+* DESCRIPTION: -+* This function get the DRAM total size. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* DRAM total size. In case or paramter is invalid, the function -+* returns -1. -+* -+*******************************************************************************/ -+MV_32 mvDramIfSizeGet(MV_VOID) -+{ -+ MV_U32 totalSize = 0, bankSize = 0, bankNum; -+ -+ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ bankSize = mvDramIfBankSizeGet(bankNum); -+ -+ if (-1 == bankSize) -+ { -+ mvOsPrintf("Dram: mvDramIfSizeGet error with bank %d \n",bankNum); -+ return -1; -+ } -+ else -+ { -+ totalSize += bankSize; -+ } -+ } -+ -+ DB(mvOsPrintf("Dram: Total DRAM size is 0x%x \n",totalSize)); -+ -+ return totalSize; -+} -+ -+/******************************************************************************* -+* mvDramIfBankBaseGet - Get DRAM interface bank base. -+* -+* DESCRIPTION: -+* This function returns the 32 bit base address of a given DRAM bank. -+* -+* INPUT: -+* bankNum - Bank number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* DRAM bank size. If bank is disabled or paramter is invalid, the -+* function returns -1. -+* -+*******************************************************************************/ -+MV_32 mvDramIfBankBaseGet(MV_U32 bankNum) -+{ -+ MV_DRAM_DEC_WIN addrDecWin; -+ -+ /* Check parameters */ -+ if (!MV_TARGET_IS_DRAM(bankNum)) -+ { -+ mvOsPrintf("mvDramIfBankBaseGet: bankNum %d is invalid\n", bankNum); -+ return -1; -+ } -+ /* Get window parameters */ -+ if (MV_OK != mvDramIfWinGet(bankNum, &addrDecWin)) -+ { -+ mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); -+ return -1; -+ } -+ -+ if (MV_TRUE == addrDecWin.enable) -+ { -+ return addrDecWin.addrWin.baseLow; -+ } -+ else -+ { -+ return -1; -+ } -+} -+ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h 2010-11-09 20:28:10.692495407 +0100 -@@ -0,0 +1,192 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvDramIfConfigh -+#define __INCmvDramIfConfigh -+ -+/* includes */ -+ -+/* defines */ -+ -+/* registers defaults values */ -+ -+#define SDRAM_CONFIG_DV \ -+ (SDRAM_PERR_WRITE | \ -+ SDRAM_SRMODE | \ -+ SDRAM_SRCLK_GATED) -+ -+#define SDRAM_DUNIT_CTRL_LOW_DV \ -+ (SDRAM_CTRL_POS_RISE | \ -+ SDRAM_CLK1DRV_NORMAL | \ -+ SDRAM_LOCKEN_ENABLE) -+ -+#define SDRAM_ADDR_CTRL_DV 0 -+ -+#define SDRAM_TIMING_CTRL_LOW_REG_DV \ -+ ((0x2 << SDRAM_TRCD_OFFS) | \ -+ (0x2 << SDRAM_TRP_OFFS) | \ -+ (0x1 << SDRAM_TWR_OFFS) | \ -+ (0x0 << SDRAM_TWTR_OFFS) | \ -+ (0x5 << SDRAM_TRAS_OFFS) | \ -+ (0x1 << SDRAM_TRRD_OFFS)) -+/* TRFC 0x27, TW2W 0x1 */ -+#define SDRAM_TIMING_CTRL_HIGH_REG_DV (( 0x7 << SDRAM_TRFC_OFFS ) |\ -+ ( 0x2 << SDRAM_TRFC_EXT_OFFS) |\ -+ ( 0x1 << SDRAM_TW2W_OFFS)) -+ -+#define SDRAM_OPEN_PAGES_CTRL_REG_DV SDRAM_OPEN_PAGE_EN -+ -+/* DDR2 ODT default register values */ -+ -+/* Presence Ctrl Low Ctrl High Dunit Ctrl Ext Mode */ -+/* CS0 0x84210000 0x00000000 0x0000780F 0x00000440 */ -+/* CS0+CS1 0x84210000 0x00000000 0x0000780F 0x00000440 */ -+/* CS0+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -+/* CS0+CS1+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -+/* CS0+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -+/* CS0+CS1+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -+ -+#define DDR2_ODT_CTRL_LOW_CS0_DV 0x84210000 -+#define DDR2_ODT_CTRL_HIGH_CS0_DV 0x00000000 -+#define DDR2_DUNIT_ODT_CTRL_CS0_DV 0x0000780F -+#define DDR_SDRAM_EXT_MODE_CS0_DV 0x00000440 -+ -+#define DDR2_ODT_CTRL_LOW_CS0_CS2_DV 0x030C030C -+#define DDR2_ODT_CTRL_HIGH_CS0_CS2_DV 0x00000000 -+#define DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV 0x0000740F -+#define DDR_SDRAM_EXT_MODE_CS0_CS2_DV 0x00000404 -+ -+ -+/* DDR SDRAM Adderss/Control and Data Pads Calibration default values */ -+#define DDR1_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \ -+ (1 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) -+#define DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \ -+ (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) -+ -+ -+#define DDR1_DATA_PAD_STRENGTH_TYPICAL_DV \ -+ (1 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) -+#define DDR2_DATA_PAD_STRENGTH_TYPICAL_DV \ -+ (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) -+ -+/* DDR SDRAM Mode Register default value */ -+#define DDR1_MODE_REG_DV 0x00000000 -+#define DDR2_MODE_REG_DV 0x00000400 -+ -+/* DDR SDRAM Timing parameter default values */ -+#define DDR1_TIMING_LOW_DV 0x11602220 -+#define DDR1_TIMING_HIGH_DV 0x0000000d -+ -+#define DDR2_TIMING_LOW_DV 0x11812220 -+#define DDR2_TIMING_HIGH_DV 0x0000030f -+ -+/* For Guideline (GL# MEM-4) DQS Reference Delay Tuning */ -+#define FTDLL_DDR1_166MHZ ((0x1 << 0) | \ -+ (0x7F<< 12) | \ -+ (0x1 << 22)) -+ -+#define FTDLL_DDR1_133MHZ FTDLL_DDR1_166MHZ -+ -+#define FTDLL_DDR1_200MHZ ((0x1 << 0) | \ -+ (0x1 << 12) | \ -+ (0x3 << 14) | \ -+ (0x1 << 18) | \ -+ (0x1 << 22)) -+ -+ -+#define FTDLL_DDR2_166MHZ ((0x1 << 0) | \ -+ (0x1 << 12) | \ -+ (0x1 << 14) | \ -+ (0x1 << 16) | \ -+ (0x1 << 19) | \ -+ (0xF << 20)) -+ -+#define FTDLL_DDR2_133MHZ FTDLL_DDR2_166MHZ -+ -+#define FTDLL_DDR2_200MHZ ((0x1 << 0) | \ -+ (0x1 << 12) | \ -+ (0x1 << 14) | \ -+ (0x1 << 16) | \ -+ (0x1 << 19) | \ -+ (0xF << 20)) -+ -+#define FTDLL_DDR2_250MHZ 0x445001 -+ -+/* Orion 1 B1 and above */ -+#define FTDLL_DDR1_166MHZ_5181_B1 0x45D001 -+ -+/* Orion nas */ -+#define FTDLL_DDR2_166MHZ_5182 0x597001 -+ -+/* Orion 2 D0 and above */ -+#define FTDLL_DDR1_166MHZ_5281_D0 0x8D0001 -+#define FTDLL_DDR1_200MHZ_5281_D0 0x8D0001 -+#define FTDLL_DDR2_166MHZ_5281_D0 0x485001 -+#define FTDLL_DDR2_200MHZ_5281_D0 0x485001 -+#define FTDLL_DDR2_250MHZ_5281_D0 0x445001 -+#define FTDLL_DDR2_200MHZ_5281_D1 0x995001 -+#define FTDLL_DDR2_250MHZ_5281_D1 0x984801 -+ -+#endif /* __INCmvDramIfh */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h 2010-11-09 20:28:10.747105889 +0100 -@@ -0,0 +1,179 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvDramIfh -+#define __INCmvDramIfh -+ -+/* includes */ -+#include "ddr1_2/mvDramIfRegs.h" -+#include "ddr1_2/mvDramIfConfig.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+ -+/* defines */ -+/* DRAM Timing parameters */ -+#define SDRAM_TWR 15 /* ns tWr */ -+#define SDRAM_TRFC_64_512M_AT_200MHZ 70 /* ns tRfc for dens 64-512 @ 200MHz */ -+#define SDRAM_TRFC_64_512M 75 /* ns tRfc for dens 64-512 */ -+#define SDRAM_TRFC_1G 120 /* ns tRfc for dens 1GB */ -+#define SDRAM_TR2R_CYC 1 /* cycle for tR2r */ -+#define SDRAM_TR2WW2R_CYC 1 /* cycle for tR2wW2r */ -+ -+/* typedefs */ -+ -+/* enumeration for memory types */ -+typedef enum _mvMemoryType -+{ -+ MEM_TYPE_SDRAM, -+ MEM_TYPE_DDR1, -+ MEM_TYPE_DDR2 -+}MV_MEMORY_TYPE; -+ -+/* enumeration for DDR1 supported CAS Latencies */ -+typedef enum _mvDimmDdr1Cas -+{ -+ DDR1_CL_1_5 = 0x02, -+ DDR1_CL_2 = 0x04, -+ DDR1_CL_2_5 = 0x08, -+ DDR1_CL_3 = 0x10, -+ DDR1_CL_4 = 0x40, -+ DDR1_CL_FAULT -+} MV_DIMM_DDR1_CAS; -+ -+/* enumeration for DDR2 supported CAS Latencies */ -+typedef enum _mvDimmDdr2Cas -+{ -+ DDR2_CL_3 = 0x08, -+ DDR2_CL_4 = 0x10, -+ DDR2_CL_5 = 0x20, -+ DDR2_CL_FAULT -+} MV_DIMM_DDR2_CAS; -+ -+ -+typedef struct _mvDramBankInfo -+{ -+ MV_MEMORY_TYPE memoryType; /* DDR1, DDR2 or SDRAM */ -+ -+ /* DIMM dimensions */ -+ MV_U32 numOfRowAddr; -+ MV_U32 numOfColAddr; -+ MV_U32 dataWidth; -+ MV_U32 errorCheckType; /* ECC , PARITY..*/ -+ MV_U32 sdramWidth; /* 4,8,16 or 32 */ -+ MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ -+ MV_U32 burstLengthSupported; -+ MV_U32 numOfBanksOnEachDevice; -+ MV_U32 suportedCasLatencies; -+ MV_U32 refreshInterval; -+ -+ /* DIMM timing parameters */ -+ MV_U32 minCycleTimeAtMaxCasLatPs; -+ MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; -+ MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; -+ MV_U32 minRowPrechargeTime; -+ MV_U32 minRowActiveToRowActive; -+ MV_U32 minRasToCasDelay; -+ MV_U32 minRasPulseWidth; -+ MV_U32 minWriteRecoveryTime; /* DDR2 only */ -+ MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ -+ MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ -+ MV_U32 minRefreshToActiveCmd; /* DDR2 only */ -+ -+ /* Parameters calculated from the extracted DIMM information */ -+ MV_U32 size; -+ MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit */ -+ MV_U32 numberOfDevices; -+ -+ /* DIMM attributes (MV_TRUE for yes) */ -+ MV_BOOL registeredAddrAndControlInputs; -+ -+}MV_DRAM_BANK_INFO; -+ -+/* This structure describes CPU interface address decode window */ -+typedef struct _mvDramIfDecWin -+{ -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+}MV_DRAM_DEC_WIN; -+ -+#include "ddr1_2/mvDram.h" -+ -+/* mvDramIf.h API list */ -+MV_VOID mvDramIfBasicAsmInit(MV_VOID); -+MV_STATUS mvDramIfDetect(MV_U32 forcedCl); -+MV_VOID _mvDramIfConfig(MV_VOID); -+ -+MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); -+MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); -+MV_STATUS mvDramIfWinEnable(MV_TARGET target,MV_BOOL enable); -+MV_32 mvDramIfBankSizeGet(MV_U32 bankNum); -+MV_32 mvDramIfBankBaseGet(MV_U32 bankNum); -+MV_32 mvDramIfSizeGet(MV_VOID); -+ -+#if 0 -+MV_STATUS mvDramIfMbusCtrlSet(MV_XBAR_TARGET *pPizzaArbArray); -+MV_STATUS mvDramIfMbusToutSet(MV_U32 timeout, MV_BOOL enable); -+#endif -+ -+#endif /* __INCmvDramIfh */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h 2010-11-09 20:28:10.772495655 +0100 -@@ -0,0 +1,306 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvDramIfRegsh -+#define __INCmvDramIfRegsh -+ -+ -+/* DDR SDRAM Controller Address Decode Registers */ -+/* SDRAM CSn Base Address Register (SCBAR) */ -+#define SDRAM_BASE_ADDR_REG(csNum) (0x1500 + (csNum * 8)) -+#define SCBAR_BASE_OFFS 16 -+#define SCBAR_BASE_MASK (0xffff << SCBAR_BASE_OFFS) -+#define SCBAR_BASE_ALIGNMENT 0x10000 -+ -+/* SDRAM CSn Size Register (SCSR) */ -+#define SDRAM_SIZE_REG(csNum) (0x1504 + (csNum * 8)) -+#define SCSR_WIN_EN BIT0 -+#define SCSR_SIZE_OFFS 16 -+#define SCSR_SIZE_MASK (0xffff << SCSR_SIZE_OFFS) -+#define SCSR_SIZE_ALIGNMENT 0x10000 -+ -+/* configuration register */ -+#define SDRAM_CONFIG_REG 0x1400 -+#define SDRAM_REFRESH_OFFS 0 -+#define SDRAM_REFRESH_MAX 0x3000 -+#define SDRAM_REFRESH_MASK (SDRAM_REFRESH_MAX << SDRAM_REFRESH_OFFS) -+#define SDRAM_DWIDTH_OFFS 14 -+#define SDRAM_DWIDTH_MASK (3 << SDRAM_DWIDTH_OFFS) -+#define SDRAM_DWIDTH_16BIT (1 << SDRAM_DWIDTH_OFFS) -+#define SDRAM_DWIDTH_32BIT (2 << SDRAM_DWIDTH_OFFS) -+#define SDRAM_DTYPE_OFFS 16 -+#define SDRAM_DTYPE_MASK (1 << SDRAM_DTYPE_OFFS) -+#define SDRAM_DTYPE_DDR1 (0 << SDRAM_DTYPE_OFFS) -+#define SDRAM_DTYPE_DDR2 (1 << SDRAM_DTYPE_OFFS) -+#define SDRAM_REGISTERED (1 << 17) -+#define SDRAM_PERR_OFFS 18 -+#define SDRAM_PERR_MASK (1 << SDRAM_PERR_OFFS) -+#define SDRAM_PERR_NO_WRITE (0 << SDRAM_PERR_OFFS) -+#define SDRAM_PERR_WRITE (1 << SDRAM_PERR_OFFS) -+#define SDRAM_DCFG_OFFS 20 -+#define SDRAM_DCFG_MASK (0x3 << SDRAM_DCFG_OFFS) -+#define SDRAM_DCFG_X16_DEV (1 << SDRAM_DCFG_OFFS) -+#define SDRAM_DCFG_X8_DEV (2 << SDRAM_DCFG_OFFS) -+#define SDRAM_SRMODE (1 << 24) -+#define SDRAM_SRCLK_OFFS 25 -+#define SDRAM_SRCLK_MASK (1 << SDRAM_SRCLK_OFFS) -+#define SDRAM_SRCLK_KEPT (0 << SDRAM_SRCLK_OFFS) -+#define SDRAM_SRCLK_GATED (1 << SDRAM_SRCLK_OFFS) -+#define SDRAM_CATTH_OFFS 26 -+#define SDRAM_CATTHR_EN (1 << SDRAM_CATTH_OFFS) -+ -+ -+/* dunit control register */ -+#define SDRAM_DUNIT_CTRL_REG 0x1404 -+#define SDRAM_CTRL_POS_OFFS 6 -+#define SDRAM_CTRL_POS_FALL (0 << SDRAM_CTRL_POS_OFFS) -+#define SDRAM_CTRL_POS_RISE (1 << SDRAM_CTRL_POS_OFFS) -+#define SDRAM_CLK1DRV_OFFS 12 -+#define SDRAM_CLK1DRV_MASK (1 << SDRAM_CLK1DRV_OFFS) -+#define SDRAM_CLK1DRV_HIGH_Z (0 << SDRAM_CLK1DRV_OFFS) -+#define SDRAM_CLK1DRV_NORMAL (1 << SDRAM_CLK1DRV_OFFS) -+#define SDRAM_LOCKEN_OFFS 18 -+#define SDRAM_LOCKEN_MASK (1 << SDRAM_LOCKEN_OFFS) -+#define SDRAM_LOCKEN_DISABLE (0 << SDRAM_LOCKEN_OFFS) -+#define SDRAM_LOCKEN_ENABLE (1 << SDRAM_LOCKEN_OFFS) -+#define SDRAM_ST_BURST_DEL_OFFS 24 -+#define SDRAM_ST_BURST_DEL_MAX 0xf -+#define SDRAM_ST_BURST_DEL_MASK (SDRAM_ST_BURST_DEL_MAX< busClkPs) -+ { -+ mvOsOutput("Dram: ERR. Bank %d doesn't support memory clock!!!\n", i); -+ return MV_ERROR; -+ } -+ -+ /* All banks must support registry in order to activate it */ -+ if(bankInfo[i].registeredAddrAndControlInputs != -+ bankInfo[0].registeredAddrAndControlInputs) -+ { -+ mvOsOutput("Dram: ERR. different Registered settings !!!\n"); -+ return MV_ERROR; -+ } -+ -+ /* All banks must support same ECC mode */ -+ if(bankInfo[i].errorCheckType != -+ bankInfo[0].errorCheckType) -+ { -+ mvOsOutput("Dram: ERR. different ECC settings !!!\n"); -+ return MV_ERROR; -+ } -+ -+ } -+ else -+ { -+ if( i == 0 ) /* bank 0 doesn't exist */ -+ { -+ mvOsOutput("Dram: ERR. Fail to detect bank 0 !!!\n"); -+ return MV_ERROR; -+ } -+ else -+ { -+ DB(mvOsPrintf("Dram: Could not find bank %d\n", i)); -+ bankInfo[i].size = 0; /* Mark this bank as non exist */ -+ } -+ } -+ } -+ -+#ifdef MV_INCLUDE_SDRAM_CS2 -+ if (bankInfo[SDRAM_CS0].size < bankInfo[SDRAM_CS2].size) -+ { -+ MV_DRAM_CS_order[0] = SDRAM_CS2; -+ MV_DRAM_CS_order[1] = SDRAM_CS3; -+ MV_DRAM_CS_order[2] = SDRAM_CS0; -+ MV_DRAM_CS_order[3] = SDRAM_CS1; -+ DRAM_CS_Order[0] = SDRAM_CS2; -+ DRAM_CS_Order[1] = SDRAM_CS3; -+ DRAM_CS_Order[2] = SDRAM_CS0; -+ DRAM_CS_Order[3] = SDRAM_CS1; -+ -+ } -+ else -+#endif -+ { -+ MV_DRAM_CS_order[0] = SDRAM_CS0; -+ MV_DRAM_CS_order[1] = SDRAM_CS1; -+ DRAM_CS_Order[0] = SDRAM_CS0; -+ DRAM_CS_Order[1] = SDRAM_CS1; -+#ifdef MV_INCLUDE_SDRAM_CS2 -+ MV_DRAM_CS_order[2] = SDRAM_CS2; -+ MV_DRAM_CS_order[3] = SDRAM_CS3; -+ DRAM_CS_Order[2] = SDRAM_CS2; -+ DRAM_CS_Order[3] = SDRAM_CS3; -+#endif -+ } -+ -+ for(j = 0; j < MV_DRAM_MAX_CS; j++) -+ { -+ i = MV_DRAM_CS_order[j]; -+ -+ if (0 == bankInfo[i].size) -+ continue; -+ -+ /* Init the CPU window decode */ -+ /* Note that the Dimm width might be different then the device DRAM width */ -+#ifdef MV78XX0 -+ temp = MV_REG_READ(SDRAM_CONFIG_REG); -+ deviceW = ((temp & SDRAM_DWIDTH_MASK) == SDRAM_DWIDTH_32BIT )? 32 : 64; -+#else -+ deviceW = 16 /* KW family */; -+#endif -+ dimmW = bankInfo[0].dataWidth - (bankInfo[0].dataWidth % 16); -+ size = ((bankInfo[i].size << 20) / (dimmW/deviceW)); -+ -+ /* We can not change DRAM window settings while excecuting */ -+ /* code from it. That is why we skip the DRAM CS[0], saving */ -+ /* it to the ROM configuration routine */ -+ -+ numOfAllDevices += bankInfo[i].numberOfDevices; -+ if (i == MV_DRAM_CS_order[0]) -+ { -+ MV_U32 sizeToReg; -+ /* Translate the given window size to register format */ -+ sizeToReg = ctrlSizeToReg(size, SCSR_SIZE_ALIGNMENT); -+ /* Size parameter validity check. */ -+ if (-1 == sizeToReg) -+ { -+ mvOsOutput("DRAM: mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n" -+ ,i); -+ return MV_BAD_PARAM; -+ } -+ -+ DB(mvOsPrintf("Dram: Bank 0 Size - %x\n",sizeToReg);) -+ sizeToReg = (sizeToReg << SCSR_SIZE_OFFS); -+ sizeToReg |= SCSR_WIN_EN; -+ MV_REG_WRITE(DRAM_BUF_REG0, sizeToReg); -+ } -+ else -+ { -+ dramDecWin.addrWin.baseLow = base; -+ dramDecWin.addrWin.size = size; -+ dramDecWin.enable = MV_TRUE; -+ DB(mvOsPrintf("Dram: Enable window %d base 0x%x, size=0x%x\n",i, base, size)); -+ -+ /* Check if the DRAM size is more then 3GByte */ -+ if (base < 0xC0000000) -+ { -+ DB(mvOsPrintf("Dram: Enable window %d base 0x%x, size=0x%x\n",i, base, size)); -+ if (MV_OK != mvCpuIfTargetWinSet(i, &dramDecWin)) -+ { -+ mvOsPrintf("Dram: ERR. Fail to set bank %d!!!\n", SDRAM_CS0 + i); -+ return MV_ERROR; -+ } -+ } -+ } -+ -+ base += size; -+ -+ /* update the suportedCasLatencies mask */ -+ bankInfo[0].suportedCasLatencies &= bankInfo[i].suportedCasLatencies; -+ } -+ -+ /* calculate minimum CAS */ -+ minCas = minCasCalc(&bankInfo[0], &bankInfo[2], busClk, forcedCl); -+ if (0 == minCas) -+ { -+ mvOsOutput("Dram: Warn: Could not find CAS compatible to SysClk %dMhz\n", -+ (busClk / 1000000)); -+ -+ minCas = DDR2_CL_4; /* Continue with this CAS */ -+ mvOsOutput("Set default CAS latency 4\n"); -+ } -+ -+ /* calc SDRAM_CONFIG_REG and save it to temp register */ -+ temp = sdramConfigRegCalc(&bankInfo[0],&bankInfo[2], busClk); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. sdramConfigRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ -+ /* check if ECC is enabled by the user */ -+ if(eccDisable) -+ { -+ /* turn off ECC*/ -+ temp &= ~BIT18; -+ } -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG1, temp); -+ -+ /* calc SDRAM_MODE_REG and save it to temp register */ -+ temp = sdramModeRegCalc(minCas); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. sdramModeRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: sdramModeRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG2, temp); -+ -+ /* calc SDRAM_EXTENDED_MODE_REG and save it to temp register */ -+ temp = sdramExtModeRegCalc(&bankInfo[0], busClk); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. sdramExtModeRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: sdramExtModeRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG10, temp); -+ -+ /* calc D_UNIT_CONTROL_LOW and save it to temp register */ -+ TTMode = MV_FALSE; -+ DB(mvOsPrintf("Dram: numOfAllDevices = %x\n",numOfAllDevices);) -+ if( (numOfAllDevices > 9) && (bankInfo[0].registeredAddrAndControlInputs == MV_FALSE) ) -+ { -+ if ( ( (numOfAllDevices > 9) && (busClk > MV_BOARD_SYSCLK_200MHZ) ) || -+ (numOfAllDevices > 18) ) -+ { -+ mvOsOutput("Enable 2T "); -+ TTMode = MV_TRUE; -+ } -+ } -+ -+ temp = dunitCtrlLowRegCalc(&bankInfo[0], minCas, busClk, TTMode ); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. dunitCtrlLowRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: dunitCtrlLowRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG3, temp); -+ -+ /* calc D_UNIT_CONTROL_HIGH and save it to temp register */ -+ temp = dunitCtrlHighRegCalc(&bankInfo[0], busClk); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. dunitCtrlHighRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: dunitCtrlHighRegCalc - %x\n",temp);) -+ /* check if ECC is enabled by the user */ -+ if(eccDisable) -+ { -+ /* turn off sample stage if no ecc */ -+ temp &= ~SDRAM__D2P_EN;; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG13, temp); -+ -+ /* calc SDRAM_ADDR_CTRL_REG and save it to temp register */ -+ temp = sdramAddrCtrlRegCalc(&bankInfo[0],&bankInfo[2]); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. sdramAddrCtrlRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: sdramAddrCtrlRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG4, temp); -+ -+ /* calc SDRAM_TIMING_CTRL_LOW_REG and save it to temp register */ -+ temp = sdramTimeCtrlLowRegCalc(&bankInfo[0], minCas, busClk); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. sdramTimeCtrlLowRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: sdramTimeCtrlLowRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG5, temp); -+ -+ /* calc SDRAM_TIMING_CTRL_HIGH_REG and save it to temp register */ -+ temp = sdramTimeCtrlHighRegCalc(&bankInfo[0], busClk); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. sdramTimeCtrlHighRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: sdramTimeCtrlHighRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG6, temp); -+ -+ sdramDDr2OdtConfig(bankInfo); -+ -+ /* calc DDR2_SDRAM_TIMING_LOW_REG and save it to temp register */ -+ temp = sdramDdr2TimeLoRegCalc(minCas); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. sdramDdr2TimeLoRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: sdramDdr2TimeLoRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG11, temp); -+ -+ /* calc DDR2_SDRAM_TIMING_HIGH_REG and save it to temp register */ -+ temp = sdramDdr2TimeHiRegCalc(minCas); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. sdramDdr2TimeHiRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: sdramDdr2TimeHiRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG12, temp); -+#endif -+ -+ /* Note that DDR SDRAM Address/Control and Data pad calibration */ -+ /* settings is done in mvSdramIfConfig.s */ -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvDramIfBankBaseGet - Get DRAM interface bank base. -+* -+* DESCRIPTION: -+* This function returns the 32 bit base address of a given DRAM bank. -+* -+* INPUT: -+* bankNum - Bank number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* DRAM bank size. If bank is disabled or paramter is invalid, the -+* function returns -1. -+* -+*******************************************************************************/ -+MV_U32 mvDramIfBankBaseGet(MV_U32 bankNum) -+{ -+ DB(mvOsPrintf("Dram: mvDramIfBankBaseGet Bank %d base addr is %x \n", -+ bankNum, mvCpuIfTargetWinBaseLowGet(SDRAM_CS0 + bankNum))); -+ return mvCpuIfTargetWinBaseLowGet(SDRAM_CS0 + bankNum); -+} -+ -+/******************************************************************************* -+* mvDramIfBankSizeGet - Get DRAM interface bank size. -+* -+* DESCRIPTION: -+* This function returns the size of a given DRAM bank. -+* -+* INPUT: -+* bankNum - Bank number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* DRAM bank size. If bank is disabled the function return '0'. In case -+* or paramter is invalid, the function returns -1. -+* -+*******************************************************************************/ -+MV_U32 mvDramIfBankSizeGet(MV_U32 bankNum) -+{ -+ DB(mvOsPrintf("Dram: mvDramIfBankSizeGet Bank %d size is %x \n", -+ bankNum, mvCpuIfTargetWinSizeGet(SDRAM_CS0 + bankNum))); -+ return mvCpuIfTargetWinSizeGet(SDRAM_CS0 + bankNum); -+} -+ -+ -+/******************************************************************************* -+* mvDramIfSizeGet - Get DRAM interface total size. -+* -+* DESCRIPTION: -+* This function get the DRAM total size. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* DRAM total size. In case or paramter is invalid, the function -+* returns -1. -+* -+*******************************************************************************/ -+MV_U32 mvDramIfSizeGet(MV_VOID) -+{ -+ MV_U32 size = 0, i; -+ -+ for(i = 0; i < MV_DRAM_MAX_CS; i++) -+ size += mvDramIfBankSizeGet(i); -+ -+ DB(mvOsPrintf("Dram: mvDramIfSizeGet size is %x \n",size)); -+ return size; -+} -+ -+/******************************************************************************* -+* mvDramIfSingleBitErrThresholdSet - Set single bit ECC threshold. -+* -+* DESCRIPTION: -+* The ECC single bit error threshold is the number of single bit -+* errors to happen before the Dunit generates an interrupt. -+* This function set single bit ECC threshold. -+* -+* INPUT: -+* threshold - threshold. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM if threshold is to big, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_STATUS mvDramIfSingleBitErrThresholdSet(MV_U32 threshold) -+{ -+ MV_U32 regVal; -+ -+ if (threshold > SECR_THRECC_MAX) -+ { -+ return MV_BAD_PARAM; -+ } -+ -+ regVal = MV_REG_READ(SDRAM_ECC_CONTROL_REG); -+ regVal &= ~SECR_THRECC_MASK; -+ regVal |= ((SECR_THRECC(threshold) & SECR_THRECC_MASK)); -+ MV_REG_WRITE(SDRAM_ECC_CONTROL_REG, regVal); -+ -+ return MV_OK; -+} -+ -+#ifndef MV_STATIC_DRAM_ON_BOARD -+/******************************************************************************* -+* minCasCalc - Calculate the Minimum CAS latency which can be used. -+* -+* DESCRIPTION: -+* Calculate the minimum CAS latency that can be used, base on the DRAM -+* parameters and the SDRAM bus Clock freq. -+* -+* INPUT: -+* busClk - the DRAM bus Clock. -+* pBankInfo - bank info parameters. -+* forcedCl - Forced CAS Latency multiplied by 10. If equal to zero, do not force. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* The minimum CAS Latency. The function returns 0 if max CAS latency -+* supported by banks is incompatible with system bus clock frequancy. -+* -+*******************************************************************************/ -+ -+static MV_U32 minCasCalc(MV_DRAM_BANK_INFO *pBankInfo,MV_DRAM_BANK_INFO *pBankInfo2, MV_U32 busClk, MV_U32 forcedCl) -+{ -+ MV_U32 count = 1, j; -+ MV_U32 busClkPs = 1000000000 / (busClk / 1000); /* in ps units */ -+ MV_U32 startBit, stopBit; -+ MV_U32 minCas0 = 0, minCas2 = 0; -+ -+ -+ /* DDR 2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * -+ Disco VI= * TBD | TBD | 5 | 4 | 3 | TBD | TBD | TBD * -+ Disco Duo= * TBD | 6 | 5 | 4 | 3 | TBD | TBD | TBD * -+ *********************************************************/ -+ -+ -+ /* If we are asked to use the forced CAL we change the suported CAL to be forcedCl only */ -+ if (forcedCl) -+ { -+ mvOsOutput("DRAM: Using forced CL %d.%d\n", (forcedCl / 10), (forcedCl % 10)); -+ -+ if (forcedCl == 30) -+ pBankInfo->suportedCasLatencies = 0x08; -+ else if (forcedCl == 40) -+ pBankInfo->suportedCasLatencies = 0x10; -+ else if (forcedCl == 50) -+ pBankInfo->suportedCasLatencies = 0x20; -+ else if (forcedCl == 60) -+ pBankInfo->suportedCasLatencies = 0x40; -+ else -+ { -+ mvOsPrintf("Forced CL %d.%d not supported. Set default CL 4\n", -+ (forcedCl / 10), (forcedCl % 10)); -+ pBankInfo->suportedCasLatencies = 0x10; -+ } -+ -+ return pBankInfo->suportedCasLatencies; -+ } -+ -+ /* go over the supported cas mask from Max Cas down and check if the */ -+ /* SysClk stands in its time requirments. */ -+ -+ DB(mvOsPrintf("Dram: minCasCalc supported mask = %x busClkPs = %x \n", -+ pBankInfo->suportedCasLatencies,busClkPs )); -+ count = 1; -+ for(j = 7; j > 0; j--) -+ { -+ if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) -+ { -+ /* Reset the bits for CL incompatible for the sysClk */ -+ switch (count) -+ { -+ case 1: -+ if (pBankInfo->minCycleTimeAtMaxCasLatPs > busClkPs) -+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ case 2: -+ if (pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps > busClkPs) -+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ case 3: -+ if (pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps > busClkPs) -+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ default: -+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); -+ break; -+ } -+ } -+ } -+ -+ DB(mvOsPrintf("Dram: minCasCalc support = %x (after SysCC calc)\n", -+ pBankInfo->suportedCasLatencies )); -+ -+ count = 1; -+ DB(mvOsPrintf("Dram2: minCasCalc supported mask = %x busClkPs = %x \n", -+ pBankInfo2->suportedCasLatencies,busClkPs )); -+ for(j = 7; j > 0; j--) -+ { -+ if((pBankInfo2->suportedCasLatencies >> j) & BIT0 ) -+ { -+ /* Reset the bits for CL incompatible for the sysClk */ -+ switch (count) -+ { -+ case 1: -+ if (pBankInfo2->minCycleTimeAtMaxCasLatPs > busClkPs) -+ pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ case 2: -+ if (pBankInfo2->minCycleTimeAtMaxCasLatMinus1Ps > busClkPs) -+ pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ case 3: -+ if (pBankInfo2->minCycleTimeAtMaxCasLatMinus2Ps > busClkPs) -+ pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ default: -+ pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); -+ break; -+ } -+ } -+ } -+ -+ DB(mvOsPrintf("Dram2: minCasCalc support = %x (after SysCC calc)\n", -+ pBankInfo2->suportedCasLatencies )); -+ -+ startBit = 3; /* DDR2 support CL start with CL3 (bit 3) */ -+ stopBit = 6; /* DDR2 support CL stops with CL6 (bit 6) */ -+ -+ for(j = startBit; j <= stopBit ; j++) -+ { -+ if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) -+ { -+ DB(mvOsPrintf("Dram: minCasCalc choose CAS %x \n",(BIT0 << j))); -+ minCas0 = (BIT0 << j); -+ break; -+ } -+ } -+ -+ for(j = startBit; j <= stopBit ; j++) -+ { -+ if((pBankInfo2->suportedCasLatencies >> j) & BIT0 ) -+ { -+ DB(mvOsPrintf("Dram: minCasCalc choose CAS %x \n",(BIT0 << j))); -+ minCas2 = (BIT0 << j); -+ break; -+ } -+ } -+ -+ if (minCas2 > minCas0) -+ return minCas2; -+ else -+ return minCas0; -+ -+ return 0; -+} -+ -+/******************************************************************************* -+* sdramConfigRegCalc - Calculate sdram config register -+* -+* DESCRIPTION: Calculate sdram config register optimized value based -+* on the bank info parameters. -+* -+* INPUT: -+* busClk - the DRAM bus Clock. -+* pBankInfo - sdram bank parameters -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram config reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramConfigRegCalc(MV_DRAM_BANK_INFO *pBankInfo,MV_DRAM_BANK_INFO *pBankInfo2, MV_U32 busClk) -+{ -+ MV_U32 sdramConfig = 0; -+ MV_U32 refreshPeriod; -+ -+ busClk /= 1000000; /* we work with busClk in MHz */ -+ -+ sdramConfig = MV_REG_READ(SDRAM_CONFIG_REG); -+ -+ /* figure out the memory refresh internal */ -+ switch (pBankInfo->refreshInterval & 0xf) -+ { -+ case 0x0: /* refresh period is 15.625 usec */ -+ refreshPeriod = 15625; -+ break; -+ case 0x1: /* refresh period is 3.9 usec */ -+ refreshPeriod = 3900; -+ break; -+ case 0x2: /* refresh period is 7.8 usec */ -+ refreshPeriod = 7800; -+ break; -+ case 0x3: /* refresh period is 31.3 usec */ -+ refreshPeriod = 31300; -+ break; -+ case 0x4: /* refresh period is 62.5 usec */ -+ refreshPeriod = 62500; -+ break; -+ case 0x5: /* refresh period is 125 usec */ -+ refreshPeriod = 125000; -+ break; -+ default: /* refresh period undefined */ -+ mvOsPrintf("Dram: ERR. DRAM refresh period is unknown!\n"); -+ return -1; -+ } -+ -+ /* Now the refreshPeriod is in register format value */ -+ refreshPeriod = (busClk * refreshPeriod) / 1000; -+ -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc calculated refresh interval %0x\n", -+ refreshPeriod)); -+ -+ /* make sure the refresh value is only 14 bits */ -+ if(refreshPeriod > SDRAM_REFRESH_MAX) -+ { -+ refreshPeriod = SDRAM_REFRESH_MAX; -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc adjusted refresh interval %0x\n", -+ refreshPeriod)); -+ } -+ -+ /* Clear the refresh field */ -+ sdramConfig &= ~SDRAM_REFRESH_MASK; -+ -+ /* Set new value to refresh field */ -+ sdramConfig |= (refreshPeriod & SDRAM_REFRESH_MASK); -+ -+ /* registered DRAM ? */ -+ if ( pBankInfo->registeredAddrAndControlInputs ) -+ { -+ /* it's registered DRAM, so set the reg. DRAM bit */ -+ sdramConfig |= SDRAM_REGISTERED; -+ DB(mvOsPrintf("DRAM Attribute: Registered address and control inputs.\n");) -+ } -+ -+ /* ECC and IERR support */ -+ sdramConfig &= ~SDRAM_ECC_MASK; /* Clear ECC field */ -+ sdramConfig &= ~SDRAM_IERR_MASK; /* Clear IErr field */ -+ -+ if ( pBankInfo->errorCheckType ) -+ { -+ sdramConfig |= SDRAM_ECC_EN; -+ sdramConfig |= SDRAM_IERR_REPORTE; -+ DB(mvOsPrintf("Dram: mvDramIfDetect Enabling ECC\n")); -+ } -+ else -+ { -+ sdramConfig |= SDRAM_ECC_DIS; -+ sdramConfig |= SDRAM_IERR_IGNORE; -+ DB(mvOsPrintf("Dram: mvDramIfDetect Disabling ECC!\n")); -+ } -+ /* Set static default settings */ -+ sdramConfig |= SDRAM_CONFIG_DV; -+ -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc set sdramConfig to 0x%x\n", -+ sdramConfig)); -+ -+ return sdramConfig; -+} -+ -+/******************************************************************************* -+* sdramModeRegCalc - Calculate sdram mode register -+* -+* DESCRIPTION: Calculate sdram mode register optimized value based -+* on the bank info parameters and the minCas. -+* -+* INPUT: -+* minCas - minimum CAS supported. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram mode reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramModeRegCalc(MV_U32 minCas) -+{ -+ MV_U32 sdramMode; -+ -+ sdramMode = MV_REG_READ(SDRAM_MODE_REG); -+ -+ /* Clear CAS Latency field */ -+ sdramMode &= ~SDRAM_CL_MASK; -+ -+ DB(mvOsPrintf("DRAM CAS Latency ");) -+ -+ switch (minCas) -+ { -+ case DDR2_CL_3: -+ sdramMode |= SDRAM_DDR2_CL_3; -+ DB(mvOsPrintf("3.\n");) -+ break; -+ case DDR2_CL_4: -+ sdramMode |= SDRAM_DDR2_CL_4; -+ DB(mvOsPrintf("4.\n");) -+ break; -+ case DDR2_CL_5: -+ sdramMode |= SDRAM_DDR2_CL_5; -+ DB(mvOsPrintf("5.\n");) -+ break; -+ case DDR2_CL_6: -+ sdramMode |= SDRAM_DDR2_CL_6; -+ DB(mvOsPrintf("6.\n");) -+ break; -+ default: -+ mvOsOutput("\nsdramModeRegCalc ERROR: Max. CL out of range\n"); -+ return -1; -+ } -+ -+ DB(mvOsPrintf("\nsdramModeRegCalc register 0x%x\n", sdramMode )); -+ -+ return sdramMode; -+} -+/******************************************************************************* -+* sdramExtModeRegCalc - Calculate sdram Extended mode register -+* -+* DESCRIPTION: -+* Return sdram Extended mode register value based -+* on the bank info parameters and bank presence. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* busClk - DRAM frequency -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram Extended mode reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramExtModeRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) -+{ -+ MV_U32 populateBanks = 0; -+ int bankNum; -+ -+ /* Represent the populate banks in binary form */ -+ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ if (0 != pBankInfo[bankNum].size) -+ { -+ populateBanks |= (1 << bankNum); -+ } -+ } -+ -+ switch(populateBanks) -+ { -+ case(BANK_PRESENT_CS0): -+ case(BANK_PRESENT_CS0_CS1): -+ return DDR_SDRAM_EXT_MODE_CS0_CS1_DV; -+ -+ case(BANK_PRESENT_CS0_CS2): -+ case(BANK_PRESENT_CS0_CS1_CS2): -+ case(BANK_PRESENT_CS0_CS2_CS3): -+ case(BANK_PRESENT_CS0_CS2_CS3_CS4): -+ if (busClk >= MV_BOARD_SYSCLK_267MHZ) -+ return DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV; -+ else -+ return DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV; -+ -+ default: -+ mvOsOutput("sdramExtModeRegCalc: Invalid DRAM bank presence\n"); -+ return -1; -+ } -+ return 0; -+} -+ -+/******************************************************************************* -+* dunitCtrlLowRegCalc - Calculate sdram dunit control low register -+* -+* DESCRIPTION: Calculate sdram dunit control low register optimized value based -+* on the bank info parameters and the minCas. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* minCas - minimum CAS supported. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram dunit control low reg value. -+* -+*******************************************************************************/ -+static MV_U32 dunitCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas, MV_U32 busClk, MV_STATUS TTMode) -+{ -+ MV_U32 dunitCtrlLow, cl; -+ MV_U32 sbOutR[4]={3,5,7,9} ; -+ MV_U32 sbOutU[4]={1,3,5,7} ; -+ -+ dunitCtrlLow = MV_REG_READ(SDRAM_DUNIT_CTRL_REG); -+ -+ DB(mvOsPrintf("Dram: dunitCtrlLowRegCalc\n")); -+ -+ /* Clear StBurstOutDel field */ -+ dunitCtrlLow &= ~SDRAM_SB_OUT_MASK; -+ -+ /* Clear StBurstInDel field */ -+ dunitCtrlLow &= ~SDRAM_SB_IN_MASK; -+ -+ /* Clear CtrlPos field */ -+ dunitCtrlLow &= ~SDRAM_CTRL_POS_MASK; -+ -+ /* Clear 2T field */ -+ dunitCtrlLow &= ~SDRAM_2T_MASK; -+ if (TTMode == MV_TRUE) -+ { -+ dunitCtrlLow |= SDRAM_2T_MODE; -+ } -+ -+ /* For proper sample of read data set the Dunit Control register's */ -+ /* stBurstInDel bits [27:24] */ -+ /* 200MHz - 267MHz None reg = CL + 1 */ -+ /* 200MHz - 267MHz reg = CL + 2 */ -+ /* > 267MHz None reg = CL + 2 */ -+ /* > 267MHz reg = CL + 3 */ -+ -+ /* For proper sample of read data set the Dunit Control register's */ -+ /* stBurstOutDel bits [23:20] */ -+ /********-********-********-********- -+ * CL=3 | CL=4 | CL=5 | CL=6 | -+ *********-********-********-********- -+ Not Reg. * 0001 | 0011 | 0101 | 0111 | -+ *********-********-********-********- -+ Registered * 0011 | 0101 | 0111 | 1001 | -+ *********-********-********-********/ -+ -+ /* Set Dunit Control low default value */ -+ dunitCtrlLow |= SDRAM_DUNIT_CTRL_LOW_DDR2_DV; -+ -+ switch (minCas) -+ { -+ case DDR2_CL_3: cl = 3; break; -+ case DDR2_CL_4: cl = 4; break; -+ case DDR2_CL_5: cl = 5; break; -+ case DDR2_CL_6: cl = 6; break; -+ default: -+ mvOsOutput("Dram: dunitCtrlLowRegCalc Max. CL out of range %d\n", minCas); -+ return -1; -+ } -+ -+ /* registerd DDR SDRAM? */ -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ { -+ dunitCtrlLow |= (sbOutR[cl-3]) << SDRAM_SB_OUT_DEL_OFFS; -+ } -+ else -+ { -+ dunitCtrlLow |= (sbOutU[cl-3]) << SDRAM_SB_OUT_DEL_OFFS; -+ } -+ -+ DB(mvOsPrintf("\n\ndunitCtrlLowRegCalc: CL = %d, frequencies=%d\n", cl, busClk)); -+ -+ if (busClk <= MV_BOARD_SYSCLK_267MHZ) -+ { -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ cl = cl + 2; -+ else -+ cl = cl + 1; -+ } -+ else -+ { -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ cl = cl + 3; -+ else -+ cl = cl + 2; -+ } -+ -+ DB(mvOsPrintf("dunitCtrlLowRegCalc: SDRAM_SB_IN_DEL_OFFS = %d \n", cl)); -+ dunitCtrlLow |= cl << SDRAM_SB_IN_DEL_OFFS; -+ -+ DB(mvOsPrintf("Dram: Reg dunit control low = %x\n", dunitCtrlLow )); -+ -+ return dunitCtrlLow; -+} -+ -+/******************************************************************************* -+* dunitCtrlHighRegCalc - Calculate sdram dunit control high register -+* -+* DESCRIPTION: Calculate sdram dunit control high register optimized value based -+* on the bus clock. -+* -+* INPUT: -+* busClk - DRAM frequency. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram dunit control high reg value. -+* -+*******************************************************************************/ -+static MV_U32 dunitCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) -+{ -+ MV_U32 dunitCtrlHigh; -+ dunitCtrlHigh = MV_REG_READ(SDRAM_DUNIT_CTRL_HI_REG); -+ if(busClk > MV_BOARD_SYSCLK_300MHZ) -+ dunitCtrlHigh |= SDRAM__P2D_EN; -+ else -+ dunitCtrlHigh &= ~SDRAM__P2D_EN; -+ -+ if(busClk > MV_BOARD_SYSCLK_267MHZ) -+ dunitCtrlHigh |= (SDRAM__WR_MESH_DELAY_EN | SDRAM__PUP_ZERO_SKEW_EN | SDRAM__ADD_HALF_FCC_EN); -+ -+ /* If ECC support we turn on D2P sample */ -+ dunitCtrlHigh &= ~SDRAM__D2P_EN; /* Clear D2P bit */ -+ if (( pBankInfo->errorCheckType ) && (busClk > MV_BOARD_SYSCLK_267MHZ)) -+ dunitCtrlHigh |= SDRAM__D2P_EN; -+ -+ return dunitCtrlHigh; -+} -+ -+/******************************************************************************* -+* sdramAddrCtrlRegCalc - Calculate sdram address control register -+* -+* DESCRIPTION: Calculate sdram address control register optimized value based -+* on the bank info parameters and the minCas. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram address control reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramAddrCtrlRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_DRAM_BANK_INFO *pBankInfoDIMM1) -+{ -+ MV_U32 addrCtrl = 0; -+ -+ if (pBankInfoDIMM1->size) -+ { -+ switch (pBankInfoDIMM1->sdramWidth) -+ { -+ case 4: /* memory is x4 */ -+ mvOsOutput("sdramAddrCtrlRegCalc: Error - x4 not supported!\n"); -+ return -1; -+ break; -+ case 8: /* memory is x8 */ -+ addrCtrl |= SDRAM_ADDRSEL_X8(2) | SDRAM_ADDRSEL_X8(3); -+ DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device DIMM2 width x8\n")); -+ break; -+ case 16: -+ addrCtrl |= SDRAM_ADDRSEL_X16(2) | SDRAM_ADDRSEL_X16(3); -+ DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device DIMM2 width x16\n")); -+ break; -+ default: /* memory width unsupported */ -+ mvOsOutput("sdramAddrCtrlRegCalc: ERR. DRAM chip width is unknown!\n"); -+ return -1; -+ } -+ } -+ -+ switch (pBankInfo->sdramWidth) -+ { -+ case 4: /* memory is x4 */ -+ mvOsOutput("sdramAddrCtrlRegCalc: Error - x4 not supported!\n"); -+ return -1; -+ break; -+ case 8: /* memory is x8 */ -+ addrCtrl |= SDRAM_ADDRSEL_X8(0) | SDRAM_ADDRSEL_X8(1); -+ DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device width x8\n")); -+ break; -+ case 16: -+ addrCtrl |= SDRAM_ADDRSEL_X16(0) | SDRAM_ADDRSEL_X16(1); -+ DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device width x16\n")); -+ break; -+ default: /* memory width unsupported */ -+ mvOsOutput("sdramAddrCtrlRegCalc: ERR. DRAM chip width is unknown!\n"); -+ return -1; -+ } -+ -+ /* Note that density is in MB units */ -+ switch (pBankInfo->deviceDensity) -+ { -+ case 256: /* 256 Mbit */ -+ DB(mvOsPrintf("DRAM Device Density 256Mbit\n")); -+ addrCtrl |= SDRAM_DSIZE_256Mb(0) | SDRAM_DSIZE_256Mb(1); -+ break; -+ case 512: /* 512 Mbit */ -+ DB(mvOsPrintf("DRAM Device Density 512Mbit\n")); -+ addrCtrl |= SDRAM_DSIZE_512Mb(0) | SDRAM_DSIZE_512Mb(1); -+ break; -+ case 1024: /* 1 Gbit */ -+ DB(mvOsPrintf("DRAM Device Density 1Gbit\n")); -+ addrCtrl |= SDRAM_DSIZE_1Gb(0) | SDRAM_DSIZE_1Gb(1); -+ break; -+ case 2048: /* 2 Gbit */ -+ DB(mvOsPrintf("DRAM Device Density 2Gbit\n")); -+ addrCtrl |= SDRAM_DSIZE_2Gb(0) | SDRAM_DSIZE_2Gb(1); -+ break; -+ default: -+ mvOsOutput("Dram: sdramAddrCtrl unsupported RAM-Device size %d\n", -+ pBankInfo->deviceDensity); -+ return -1; -+ } -+ -+ if (pBankInfoDIMM1->size) -+ { -+ switch (pBankInfoDIMM1->deviceDensity) -+ { -+ case 256: /* 256 Mbit */ -+ DB(mvOsPrintf("DIMM2: DRAM Device Density 256Mbit\n")); -+ addrCtrl |= SDRAM_DSIZE_256Mb(2) | SDRAM_DSIZE_256Mb(3); -+ break; -+ case 512: /* 512 Mbit */ -+ DB(mvOsPrintf("DIMM2: DRAM Device Density 512Mbit\n")); -+ addrCtrl |= SDRAM_DSIZE_512Mb(2) | SDRAM_DSIZE_512Mb(3); -+ break; -+ case 1024: /* 1 Gbit */ -+ DB(mvOsPrintf("DIMM2: DRAM Device Density 1Gbit\n")); -+ addrCtrl |= SDRAM_DSIZE_1Gb(2) | SDRAM_DSIZE_1Gb(3); -+ break; -+ case 2048: /* 2 Gbit */ -+ DB(mvOsPrintf("DIMM2: DRAM Device Density 2Gbit\n")); -+ addrCtrl |= SDRAM_DSIZE_2Gb(2) | SDRAM_DSIZE_2Gb(3); -+ break; -+ default: -+ mvOsOutput("DIMM2: Dram: sdramAddrCtrl unsupported RAM-Device size %d\n", -+ pBankInfoDIMM1->deviceDensity); -+ return -1; -+ } -+ } -+ /* SDRAM address control */ -+ DB(mvOsPrintf("Dram: setting sdram address control with: %x \n", addrCtrl)); -+ -+ return addrCtrl; -+} -+ -+/******************************************************************************* -+* sdramTimeCtrlLowRegCalc - Calculate sdram timing control low register -+* -+* DESCRIPTION: -+* This function calculates sdram timing control low register -+* optimized value based on the bank info parameters and the minCas. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* minCas - minimum CAS supported. -+* busClk - Bus clock -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram timing control low reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramTimeCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas, MV_U32 busClk) -+{ -+ MV_U32 tRp = 0; -+ MV_U32 tRrd = 0; -+ MV_U32 tRcd = 0; -+ MV_U32 tRas = 0; -+ MV_U32 tWr = 0; -+ MV_U32 tWtr = 0; -+ MV_U32 tRtp = 0; -+ MV_U32 timeCtrlLow = 0; -+ -+ MV_U32 bankNum; -+ -+ busClk = busClk / 1000000; /* In MHz */ -+ -+ /* Scan all DRAM banks to find maximum timing values */ -+ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ tRp = MV_MAX(tRp, pBankInfo[bankNum].minRowPrechargeTime); -+ tRrd = MV_MAX(tRrd, pBankInfo[bankNum].minRowActiveToRowActive); -+ tRcd = MV_MAX(tRcd, pBankInfo[bankNum].minRasToCasDelay); -+ tRas = MV_MAX(tRas, pBankInfo[bankNum].minRasPulseWidth); -+ } -+ -+ /* Extract timing (in ns) from SPD value. We ignore the tenth ns part. */ -+ /* by shifting the data two bits right. */ -+ tRp = tRp >> 2; /* For example 0x50 -> 20ns */ -+ tRrd = tRrd >> 2; -+ tRcd = tRcd >> 2; -+ -+ /* Extract clock cycles from time parameter. We need to round up */ -+ tRp = ((busClk * tRp) / 1000) + (((busClk * tRp) % 1000) ? 1 : 0); -+ DB(mvOsPrintf("Dram Timing Low: tRp = %d ", tRp)); -+ tRrd = ((busClk * tRrd) / 1000) + (((busClk * tRrd) % 1000) ? 1 : 0); -+ /* JEDEC min reqeirments tRrd = 2 */ -+ if (tRrd < 2) -+ tRrd = 2; -+ DB(mvOsPrintf("tRrd = %d ", tRrd)); -+ tRcd = ((busClk * tRcd) / 1000) + (((busClk * tRcd) % 1000) ? 1 : 0); -+ DB(mvOsPrintf("tRcd = %d ", tRcd)); -+ tRas = ((busClk * tRas) / 1000) + (((busClk * tRas) % 1000) ? 1 : 0); -+ DB(mvOsPrintf("tRas = %d ", tRas)); -+ -+ /* tWr and tWtr is different for DDR1 and DDR2. tRtp is only for DDR2 */ -+ /* Scan all DRAM banks to find maximum timing values */ -+ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ tWr = MV_MAX(tWr, pBankInfo[bankNum].minWriteRecoveryTime); -+ tWtr = MV_MAX(tWtr, pBankInfo[bankNum].minWriteToReadCmdDelay); -+ tRtp = MV_MAX(tRtp, pBankInfo[bankNum].minReadToPrechCmdDelay); -+ } -+ -+ /* Extract timing (in ns) from SPD value. We ignore the tenth ns */ -+ /* part by shifting the data two bits right. */ -+ tWr = tWr >> 2; /* For example 0x50 -> 20ns */ -+ tWtr = tWtr >> 2; -+ tRtp = tRtp >> 2; -+ /* Extract clock cycles from time parameter. We need to round up */ -+ tWr = ((busClk * tWr) / 1000) + (((busClk * tWr) % 1000) ? 1 : 0); -+ DB(mvOsPrintf("tWr = %d ", tWr)); -+ tWtr = ((busClk * tWtr) / 1000) + (((busClk * tWtr) % 1000) ? 1 : 0); -+ /* JEDEC min reqeirments tWtr = 2 */ -+ if (tWtr < 2) -+ tWtr = 2; -+ DB(mvOsPrintf("tWtr = %d ", tWtr)); -+ tRtp = ((busClk * tRtp) / 1000) + (((busClk * tRtp) % 1000) ? 1 : 0); -+ /* JEDEC min reqeirments tRtp = 2 */ -+ if (tRtp < 2) -+ tRtp = 2; -+ DB(mvOsPrintf("tRtp = %d ", tRtp)); -+ -+ /* Note: value of 0 in register means one cycle, 1 means two and so on */ -+ timeCtrlLow = (((tRp - 1) << SDRAM_TRP_OFFS) | -+ ((tRrd - 1) << SDRAM_TRRD_OFFS) | -+ ((tRcd - 1) << SDRAM_TRCD_OFFS) | -+ (((tRas - 1) << SDRAM_TRAS_OFFS) & SDRAM_TRAS_MASK)| -+ ((tWr - 1) << SDRAM_TWR_OFFS) | -+ ((tWtr - 1) << SDRAM_TWTR_OFFS) | -+ ((tRtp - 1) << SDRAM_TRTP_OFFS)); -+ -+ /* Check extended tRas bit */ -+ if ((tRas - 1) & BIT4) -+ timeCtrlLow |= (1 << SDRAM_EXT_TRAS_OFFS); -+ -+ return timeCtrlLow; -+} -+ -+/******************************************************************************* -+* sdramTimeCtrlHighRegCalc - Calculate sdram timing control high register -+* -+* DESCRIPTION: -+* This function calculates sdram timing control high register -+* optimized value based on the bank info parameters and the bus clock. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* busClk - Bus clock -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram timing control high reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramTimeCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) -+{ -+ MV_U32 tRfc; -+ MV_U32 timingHigh; -+ MV_U32 timeNs = 0; -+ MV_U32 bankNum; -+ -+ busClk = busClk / 1000000; /* In MHz */ -+ -+ /* Set DDR timing high register static configuration bits */ -+ timingHigh = MV_REG_READ(SDRAM_TIMING_CTRL_HIGH_REG); -+ -+ /* Set DDR timing high register default value */ -+ timingHigh |= SDRAM_TIMING_CTRL_HIGH_REG_DV; -+ -+ /* Clear tRfc field */ -+ timingHigh &= ~SDRAM_TRFC_MASK; -+ -+ /* Scan all DRAM banks to find maximum timing values */ -+ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ timeNs = MV_MAX(timeNs, pBankInfo[bankNum].minRefreshToActiveCmd); -+ DB(mvOsPrintf("Dram: Timing High: minRefreshToActiveCmd = %d\n", -+ pBankInfo[bankNum].minRefreshToActiveCmd)); -+ } -+ if(busClk >= 333 && mvCtrlModelGet() == MV_78XX0_A1_REV) -+ { -+ timingHigh |= 0x1 << SDRAM_TR2W_W2R_OFFS; -+ } -+ -+ tRfc = ((busClk * timeNs) / 1000) + (((busClk * timeNs) % 1000) ? 1 : 0); -+ /* Note: value of 0 in register means one cycle, 1 means two and so on */ -+ DB(mvOsPrintf("Dram: Timing High: tRfc = %d\n", tRfc)); -+ timingHigh |= (((tRfc - 1) & SDRAM_TRFC_MASK) << SDRAM_TRFC_OFFS); -+ DB(mvOsPrintf("Dram: Timing High: tRfc = %d\n", tRfc)); -+ -+ /* SDRAM timing high */ -+ DB(mvOsPrintf("Dram: setting timing high with: %x \n", timingHigh)); -+ -+ return timingHigh; -+} -+/******************************************************************************* -+* sdramDDr2OdtConfig - Set DRAM DDR2 On Die Termination registers. -+* -+* DESCRIPTION: -+* This function config DDR2 On Die Termination (ODT) registers. -+* -+* INPUT: -+* pBankInfo - bank info parameters. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* None -+*******************************************************************************/ -+static void sdramDDr2OdtConfig(MV_DRAM_BANK_INFO *pBankInfo) -+{ -+ MV_U32 populateBanks = 0; -+ MV_U32 odtCtrlLow, odtCtrlHigh, dunitOdtCtrl; -+ int bankNum; -+ -+ /* Represent the populate banks in binary form */ -+ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ if (0 != pBankInfo[bankNum].size) -+ { -+ populateBanks |= (1 << bankNum); -+ } -+ } -+ -+ switch(populateBanks) -+ { -+ case(BANK_PRESENT_CS0): -+ case(BANK_PRESENT_CS0_CS1): -+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS1_DV; -+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS1_DV; -+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV; -+ break; -+ case(BANK_PRESENT_CS0_CS2): -+ case(BANK_PRESENT_CS0_CS1_CS2): -+ case(BANK_PRESENT_CS0_CS2_CS3): -+ case(BANK_PRESENT_CS0_CS2_CS3_CS4): -+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV; -+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS1_CS2_CS3_DV; -+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV; -+ break; -+ default: -+ DB(mvOsPrintf("sdramDDr2OdtConfig: Invalid DRAM bank presence\n")); -+ return; -+ } -+ /* DDR2 SDRAM ODT ctrl low */ -+ DB(mvOsPrintf("Dram: DDR2 setting ODT ctrl low with: %x \n", odtCtrlLow)); -+ MV_REG_WRITE(DRAM_BUF_REG7, odtCtrlLow); -+ -+ /* DDR2 SDRAM ODT ctrl high */ -+ DB(mvOsPrintf("Dram: DDR2 setting ODT ctrl high with: %x \n", odtCtrlHigh)); -+ MV_REG_WRITE(DRAM_BUF_REG8, odtCtrlHigh); -+ -+ /* DDR2 DUNIT ODT ctrl */ -+ if ( ((mvCtrlModelGet() == MV_78XX0_DEV_ID) && (mvCtrlRevGet() == MV_78XX0_Y0_REV)) || -+ (mvCtrlModelGet() == MV_76100_DEV_ID) || -+ (mvCtrlModelGet() == MV_78100_DEV_ID) || -+ (mvCtrlModelGet() == MV_78200_DEV_ID) ) -+ dunitOdtCtrl &= ~(BIT9|BIT8); /* Clear ODT always on */ -+ -+ DB(mvOsPrintf("DUNIT: DDR2 setting ODT ctrl with: %x \n", dunitOdtCtrl)); -+ MV_REG_WRITE(DRAM_BUF_REG9, dunitOdtCtrl); -+ return; -+} -+/******************************************************************************* -+* sdramDdr2TimeLoRegCalc - Set DDR2 DRAM Timing Low registers. -+* -+* DESCRIPTION: -+* This function config DDR2 DRAM Timing low registers. -+* -+* INPUT: -+* minCas - minimum CAS supported. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* DDR2 sdram timing low reg value. -+*******************************************************************************/ -+static MV_U32 sdramDdr2TimeLoRegCalc(MV_U32 minCas) -+{ -+ MV_U8 cl = -1; -+ MV_U32 ddr2TimeLoReg; -+ -+ /* read and clear the feilds we are going to set */ -+ ddr2TimeLoReg = MV_REG_READ(SDRAM_DDR2_TIMING_LO_REG); -+ ddr2TimeLoReg &= ~(SD2TLR_TODT_ON_RD_MASK | -+ SD2TLR_TODT_OFF_RD_MASK | -+ SD2TLR_TODT_ON_CTRL_RD_MASK | -+ SD2TLR_TODT_OFF_CTRL_RD_MASK); -+ -+ if( minCas == DDR2_CL_3 ) -+ { -+ cl = 3; -+ } -+ else if( minCas == DDR2_CL_4 ) -+ { -+ cl = 4; -+ } -+ else if( minCas == DDR2_CL_5 ) -+ { -+ cl = 5; -+ } -+ else if( minCas == DDR2_CL_6 ) -+ { -+ cl = 6; -+ } -+ else -+ { -+ DB(mvOsPrintf("sdramDdr2TimeLoRegCalc: CAS latency %d unsupported. using CAS latency 4\n", -+ minCas)); -+ cl = 4; -+ } -+ -+ ddr2TimeLoReg |= ((cl-3) << SD2TLR_TODT_ON_RD_OFFS); -+ ddr2TimeLoReg |= ( cl << SD2TLR_TODT_OFF_RD_OFFS); -+ ddr2TimeLoReg |= ( cl << SD2TLR_TODT_ON_CTRL_RD_OFFS); -+ ddr2TimeLoReg |= ((cl+3) << SD2TLR_TODT_OFF_CTRL_RD_OFFS); -+ -+ /* DDR2 SDRAM timing low */ -+ DB(mvOsPrintf("Dram: DDR2 setting timing low with: %x \n", ddr2TimeLoReg)); -+ -+ return ddr2TimeLoReg; -+} -+ -+/******************************************************************************* -+* sdramDdr2TimeHiRegCalc - Set DDR2 DRAM Timing High registers. -+* -+* DESCRIPTION: -+* This function config DDR2 DRAM Timing high registers. -+* -+* INPUT: -+* minCas - minimum CAS supported. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* DDR2 sdram timing high reg value. -+*******************************************************************************/ -+static MV_U32 sdramDdr2TimeHiRegCalc(MV_U32 minCas) -+{ -+ MV_U8 cl = -1; -+ MV_U32 ddr2TimeHiReg; -+ -+ /* read and clear the feilds we are going to set */ -+ ddr2TimeHiReg = MV_REG_READ(SDRAM_DDR2_TIMING_HI_REG); -+ ddr2TimeHiReg &= ~(SD2THR_TODT_ON_WR_MASK | -+ SD2THR_TODT_OFF_WR_MASK | -+ SD2THR_TODT_ON_CTRL_WR_MASK | -+ SD2THR_TODT_OFF_CTRL_WR_MASK); -+ -+ if( minCas == DDR2_CL_3 ) -+ { -+ cl = 3; -+ } -+ else if( minCas == DDR2_CL_4 ) -+ { -+ cl = 4; -+ } -+ else if( minCas == DDR2_CL_5 ) -+ { -+ cl = 5; -+ } -+ else if( minCas == DDR2_CL_6 ) -+ { -+ cl = 6; -+ } -+ else -+ { -+ mvOsOutput("sdramDdr2TimeHiRegCalc: CAS latency %d unsupported. using CAS latency 4\n", -+ minCas); -+ cl = 4; -+ } -+ -+ ddr2TimeHiReg |= ((cl-3) << SD2THR_TODT_ON_WR_OFFS); -+ ddr2TimeHiReg |= ( cl << SD2THR_TODT_OFF_WR_OFFS); -+ ddr2TimeHiReg |= ( cl << SD2THR_TODT_ON_CTRL_WR_OFFS); -+ ddr2TimeHiReg |= ((cl+3) << SD2THR_TODT_OFF_CTRL_WR_OFFS); -+ -+ /* DDR2 SDRAM timin high */ -+ DB(mvOsPrintf("Dram: DDR2 setting timing high with: %x \n", ddr2TimeHiReg)); -+ -+ return ddr2TimeHiReg; -+} -+#endif -+ -+/******************************************************************************* -+* mvDramIfCalGet - Get CAS Latency -+* -+* DESCRIPTION: -+* This function get the CAS Latency. -+* -+* INPUT: -+* None -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* CAS latency times 10 (to avoid using floating point). -+* -+*******************************************************************************/ -+MV_U32 mvDramIfCalGet(void) -+{ -+ MV_U32 sdramCasLat, casLatMask; -+ -+ casLatMask = (MV_REG_READ(SDRAM_MODE_REG) & SDRAM_CL_MASK); -+ -+ switch (casLatMask) -+ { -+ case SDRAM_DDR2_CL_3: -+ sdramCasLat = 30; -+ break; -+ case SDRAM_DDR2_CL_4: -+ sdramCasLat = 40; -+ break; -+ case SDRAM_DDR2_CL_5: -+ sdramCasLat = 50; -+ break; -+ case SDRAM_DDR2_CL_6: -+ sdramCasLat = 60; -+ break; -+ default: -+ mvOsOutput("mvDramIfCalGet: Err, unknown DDR2 CAL\n"); -+ return -1; -+ } -+ -+ return sdramCasLat; -+} -+ -+ -+/******************************************************************************* -+* mvDramIfSelfRefreshSet - Put the dram in self refresh mode - -+* -+* DESCRIPTION: -+* add support in power management. -+* -+* -+* INPUT: -+* None -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* None -+* -+*******************************************************************************/ -+ -+MV_VOID mvDramIfSelfRefreshSet() -+{ -+ MV_U32 operReg; -+ -+ operReg = MV_REG_READ(SDRAM_OPERATION_REG); -+ MV_REG_WRITE(SDRAM_OPERATION_REG ,operReg |SDRAM_CMD_SLF_RFRSH); -+ /* Read until register is reset to 0 */ -+ while(MV_REG_READ(SDRAM_OPERATION_REG)); -+} -+/******************************************************************************* -+* mvDramIfDimGetSPDversion - return DIMM SPD version. -+* -+* DESCRIPTION: -+* This function prints the DRAM controller information. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+static void mvDramIfDimGetSPDversion(MV_U32 *pMajor, MV_U32 *pMinor, MV_U32 bankNum) -+{ -+ MV_DIMM_INFO dimmInfo; -+ if (bankNum >= MV_DRAM_MAX_CS ) -+ { -+ DB(mvOsPrintf("Dram: mvDramIfDimGetSPDversion bad params \n")); -+ return ; -+ } -+ memset(&dimmInfo,0,sizeof(dimmInfo)); -+ if ( MV_OK != dimmSpdGet((MV_U32)(bankNum/2), &dimmInfo)) -+ { -+ DB(mvOsPrintf("Dram: ERR dimmSpdGet failed to get dimm info \n")); -+ return ; -+ } -+ *pMajor = dimmInfo.spdRawData[DIMM_SPD_VERSION]/10; -+ *pMinor = dimmInfo.spdRawData[DIMM_SPD_VERSION]%10; -+} -+/******************************************************************************* -+* mvDramIfShow - Show DRAM controller information. -+* -+* DESCRIPTION: -+* This function prints the DRAM controller information. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+void mvDramIfShow(void) -+{ -+ int i, sdramCasLat, sdramCsSize; -+ MV_U32 Major=0, Minor=0; -+ -+ mvOsOutput("DRAM Controller info:\n"); -+ -+ mvOsOutput("Total DRAM "); -+ mvSizePrint(mvDramIfSizeGet()); -+ mvOsOutput("\n"); -+ -+ for(i = 0; i < MV_DRAM_MAX_CS; i++) -+ { -+ sdramCsSize = mvDramIfBankSizeGet(i); -+ if (sdramCsSize) -+ { -+ if (0 == (i & 1)) -+ { -+ mvDramIfDimGetSPDversion(&Major, &Minor,i); -+ mvOsOutput("DIMM %d version %d.%d\n", i/2, Major, Minor); -+ } -+ mvOsOutput("\tDRAM CS[%d] ", i); -+ mvSizePrint(sdramCsSize); -+ mvOsOutput("\n"); -+ } -+ } -+ sdramCasLat = mvDramIfCalGet(); -+ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_ECC_EN) -+ { -+ mvOsOutput("ECC enabled, "); -+ } -+ else -+ { -+ mvOsOutput("ECC Disabled, "); -+ } -+ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_REGISTERED) -+ { -+ mvOsOutput("Registered DIMM\n"); -+ } -+ else -+ { -+ mvOsOutput("Non registered DIMM\n"); -+ } -+ -+ mvOsOutput("Configured CAS Latency %d.%d\n", sdramCasLat/10, sdramCasLat%10); -+} -+/******************************************************************************* -+* mvDramIfGetFirstCS - find the DRAM bank on the lower address -+* -+* -+* DESCRIPTION: -+* This function return the fisrt CS on address 0 -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* SDRAM_CS0 or SDRAM_CS2 -+* -+*******************************************************************************/ -+MV_U32 mvDramIfGetFirstCS(void) -+{ -+ MV_DRAM_BANK_INFO bankInfo[MV_DRAM_MAX_CS]; -+ -+ if (DRAM_CS_Order[0] == N_A) -+ { -+ mvDramBankInfoGet(SDRAM_CS0, &bankInfo[SDRAM_CS0]); -+#ifdef MV_INCLUDE_SDRAM_CS2 -+ mvDramBankInfoGet(SDRAM_CS2, &bankInfo[SDRAM_CS2]); -+#endif -+ -+#ifdef MV_INCLUDE_SDRAM_CS2 -+ if (bankInfo[SDRAM_CS0].size < bankInfo[SDRAM_CS2].size) -+ { -+ DRAM_CS_Order[0] = SDRAM_CS2; -+ DRAM_CS_Order[1] = SDRAM_CS3; -+ DRAM_CS_Order[2] = SDRAM_CS0; -+ DRAM_CS_Order[3] = SDRAM_CS1; -+ -+ return SDRAM_CS2; -+ } -+#endif -+ DRAM_CS_Order[0] = SDRAM_CS0; -+ DRAM_CS_Order[1] = SDRAM_CS1; -+#ifdef MV_INCLUDE_SDRAM_CS2 -+ DRAM_CS_Order[2] = SDRAM_CS2; -+ DRAM_CS_Order[3] = SDRAM_CS3; -+#endif -+ return SDRAM_CS0; -+ } -+ return DRAM_CS_Order[0]; -+} -+/******************************************************************************* -+* mvDramIfGetCSorder - -+* -+* -+* DESCRIPTION: -+* This function return the fisrt CS on address 0 -+* -+* INPUT: -+* CS number. -+* -+* OUTPUT: -+* CS order. -+* -+* RETURN: -+* SDRAM_CS0 or SDRAM_CS2 -+* -+* NOTE: mvDramIfGetFirstCS must be caled before this subroutine -+*******************************************************************************/ -+MV_U32 mvDramIfGetCSorder(MV_U32 csOrder ) -+{ -+ return DRAM_CS_Order[csOrder]; -+} -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h 2010-11-09 20:28:10.852495382 +0100 -@@ -0,0 +1,157 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvDramIfConfigh -+#define __INCmvDramIfConfigh -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* includes */ -+ -+/* defines */ -+ -+/* registers defaults values */ -+ -+#define SDRAM_CONFIG_DV (SDRAM_SRMODE_DRAM | BIT25 | BIT30) -+ -+#define SDRAM_DUNIT_CTRL_LOW_DDR2_DV \ -+ (SDRAM_SRCLK_KEPT | \ -+ SDRAM_CLK1DRV_NORMAL | \ -+ (BIT28 | BIT29)) -+ -+#define SDRAM_ADDR_CTRL_DV 2 -+ -+#define SDRAM_TIMING_CTRL_LOW_REG_DV \ -+ ((0x2 << SDRAM_TRCD_OFFS) | \ -+ (0x2 << SDRAM_TRP_OFFS) | \ -+ (0x1 << SDRAM_TWR_OFFS) | \ -+ (0x0 << SDRAM_TWTR_OFFS) | \ -+ (0x5 << SDRAM_TRAS_OFFS) | \ -+ (0x1 << SDRAM_TRRD_OFFS)) -+ -+/* Note: value of 0 in register means one cycle, 1 means two and so on */ -+#define SDRAM_TIMING_CTRL_HIGH_REG_DV \ -+ ((0x0 << SDRAM_TR2R_OFFS) | \ -+ (0x0 << SDRAM_TR2W_W2R_OFFS) | \ -+ (0x1 << SDRAM_TW2W_OFFS)) -+ -+#define SDRAM_OPEN_PAGES_CTRL_REG_DV SDRAM_OPEN_PAGE_EN -+ -+/* Presence Ctrl Low Ctrl High Dunit Ctrl Ext Mode */ -+/* CS0 0x84210000 0x00000000 0x0000780F 0x00000440 */ -+/* CS0+CS1 0x84210000 0x00000000 0x0000780F 0x00000440 */ -+/* CS0+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -+/* CS0+CS1+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -+/* CS0+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -+/* CS0+CS1+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -+ -+#define DDR2_ODT_CTRL_LOW_CS0_CS1_DV 0x84210000 -+#define DDR2_ODT_CTRL_HIGH_CS0_CS1_DV 0x00000000 -+#define DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV 0x0000E80F -+#ifdef MV78XX0 -+#define DDR_SDRAM_EXT_MODE_CS0_CS1_DV 0x00000040 -+#else -+#define DDR_SDRAM_EXT_MODE_CS0_CS1_DV 0x00000440 -+#endif -+ -+#define DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV 0x030C030C -+#define DDR2_ODT_CTRL_HIGH_CS0_CS1_CS2_CS3_DV 0x00000000 -+#define DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV 0x0000F40F -+#ifdef MV78XX0 -+#define DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV 0x00000004 -+#define DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV 0x00000044 -+#else -+#define DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV 0x00000404 -+#define DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV 0x00000444 -+#endif -+ -+/* DDR SDRAM Adderss/Control and Data Pads Calibration default values */ -+#define DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \ -+ (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) -+ -+#define DDR2_DATA_PAD_STRENGTH_TYPICAL_DV \ -+ (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) -+ -+/* DDR SDRAM Mode Register default value */ -+#define DDR2_MODE_REG_DV (SDRAM_BURST_LEN_4 | SDRAM_WR_3_CYC) -+/* DDR SDRAM Timing parameter default values */ -+#define SDRAM_TIMING_CTRL_LOW_REG_DEFAULT 0x33136552 -+#define SDRAM_TRFC_DEFAULT_VALUE 0x34 -+#define SDRAM_TRFC_DEFAULT SDRAM_TRFC_DEFAULT_VALUE -+#define SDRAM_TW2W_DEFALT (0x1 << SDRAM_TW2W_OFFS) -+ -+#define SDRAM_TIMING_CTRL_HIGH_REG_DEFAULT (SDRAM_TRFC_DEFAULT | SDRAM_TW2W_DEFALT) -+ -+#define SDRAM_FTDLL_REG_DEFAULT_LEFT 0x88C800 -+#define SDRAM_FTDLL_REG_DEFAULT_RIGHT 0x88C800 -+#define SDRAM_FTDLL_REG_DEFAULT_UP 0x88C800 -+ -+#ifdef __cplusplus -+} -+#endif /* __cplusplus */ -+ -+#endif /* __INCmvDramIfh */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h 2010-11-09 20:28:10.882495421 +0100 -@@ -0,0 +1,172 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvDramIfh -+#define __INCmvDramIfh -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* includes */ -+#include "ddr2/mvDramIfRegs.h" -+#include "ddr2/mvDramIfConfig.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+ -+/* defines */ -+/* DRAM Timing parameters */ -+#define SDRAM_TWR 15 /* ns tWr */ -+#define SDRAM_TRFC_64_512M_AT_200MHZ 70 /* ns tRfc for dens 64-512 @ 200MHz */ -+#define SDRAM_TRFC_64_512M 75 /* ns tRfc for dens 64-512 */ -+#define SDRAM_TRFC_1G 120 /* ns tRfc for dens 1GB */ -+#define SDRAM_TR2R_CYC 1 /* cycle for tR2r */ -+ -+#define CAL_AUTO_DETECT 0 /* Do not force CAS latancy (mvDramIfDetect) */ -+#define ECC_DISABLE 1 /* Force ECC to Disable */ -+#define ECC_ENABLE 0 /* Force ECC to ENABLE */ -+/* typedefs */ -+ -+/* enumeration for memory types */ -+typedef enum _mvMemoryType -+{ -+ MEM_TYPE_SDRAM, -+ MEM_TYPE_DDR1, -+ MEM_TYPE_DDR2 -+}MV_MEMORY_TYPE; -+ -+/* enumeration for DDR2 supported CAS Latencies */ -+typedef enum _mvDimmDdr2Cas -+{ -+ DDR2_CL_3 = 0x08, -+ DDR2_CL_4 = 0x10, -+ DDR2_CL_5 = 0x20, -+ DDR2_CL_6 = 0x40, -+ DDR2_CL_FAULT -+} MV_DIMM_DDR2_CAS; -+ -+ -+typedef struct _mvDramBankInfo -+{ -+ MV_MEMORY_TYPE memoryType; /* DDR1, DDR2 or SDRAM */ -+ -+ /* DIMM dimensions */ -+ MV_U32 numOfRowAddr; -+ MV_U32 numOfColAddr; -+ MV_U32 dataWidth; -+ MV_U32 errorCheckType; /* ECC , PARITY..*/ -+ MV_U32 sdramWidth; /* 4,8,16 or 32 */ -+ MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ -+ MV_U32 burstLengthSupported; -+ MV_U32 numOfBanksOnEachDevice; -+ MV_U32 suportedCasLatencies; -+ MV_U32 refreshInterval; -+ -+ /* DIMM timing parameters */ -+ MV_U32 minCycleTimeAtMaxCasLatPs; -+ MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; -+ MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; -+ MV_U32 minRowPrechargeTime; -+ MV_U32 minRowActiveToRowActive; -+ MV_U32 minRasToCasDelay; -+ MV_U32 minRasPulseWidth; -+ MV_U32 minWriteRecoveryTime; /* DDR2 only */ -+ MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ -+ MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ -+ MV_U32 minRefreshToActiveCmd; /* DDR2 only */ -+ -+ /* Parameters calculated from the extracted DIMM information */ -+ MV_U32 size; -+ MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit */ -+ MV_U32 numberOfDevices; -+ -+ /* DIMM attributes (MV_TRUE for yes) */ -+ MV_BOOL registeredAddrAndControlInputs; -+ MV_BOOL registeredDQMBinputs; -+ -+}MV_DRAM_BANK_INFO; -+ -+#include "ddr2/spd/mvSpd.h" -+ -+/* mvDramIf.h API list */ -+MV_VOID mvDramIfBasicAsmInit(MV_VOID); -+MV_STATUS mvDramIfDetect(MV_U32 forcedCl, MV_BOOL eccDisable); -+MV_VOID _mvDramIfConfig(int entryNum); -+ -+MV_U32 mvDramIfBankSizeGet(MV_U32 bankNum); -+MV_U32 mvDramIfBankBaseGet(MV_U32 bankNum); -+MV_U32 mvDramIfSizeGet(MV_VOID); -+MV_U32 mvDramIfCalGet(void); -+MV_STATUS mvDramIfSingleBitErrThresholdSet(MV_U32 threshold); -+MV_VOID mvDramIfSelfRefreshSet(void); -+void mvDramIfShow(void); -+MV_U32 mvDramIfGetFirstCS(void); -+MV_U32 mvDramIfGetCSorder(MV_U32 csOrder ); -+MV_U32 mvDramCsSizeGet(MV_U32 csNum); -+ -+#ifdef __cplusplus -+} -+#endif /* __cplusplus */ -+ -+#endif /* __INCmvDramIfh */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h 2010-11-09 20:28:10.921244571 +0100 -@@ -0,0 +1,423 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvDramIfRegsh -+#define __INCmvDramIfRegsh -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* DDR SDRAM Controller Address Decode Registers */ -+ /* SDRAM CSn Base Address Register (SCBAR) */ -+#define SDRAM_BASE_ADDR_REG(cpu,csNum) (0x1500 + ((csNum) * 8) + ((cpu) * 0x70)) -+#define SCBAR_BASE_OFFS 16 -+#define SCBAR_BASE_MASK (0xffff << SCBAR_BASE_OFFS) -+#define SCBAR_BASE_ALIGNMENT 0x10000 -+ -+/* SDRAM CSn Size Register (SCSR) */ -+#define SDRAM_SIZE_REG(cpu,csNum) (0x1504 + ((csNum) * 8) + ((cpu) * 0x70)) -+#define SCSR_SIZE_OFFS 24 -+#define SCSR_SIZE_MASK (0xff << SCSR_SIZE_OFFS) -+#define SCSR_SIZE_ALIGNMENT 0x1000000 -+#define SCSR_WIN_EN BIT0 -+ -+/* configuration register */ -+#define SDRAM_CONFIG_REG (DRAM_BASE + 0x1400) -+#define SDRAM_REFRESH_OFFS 0 -+#define SDRAM_REFRESH_MAX 0x3FFF -+#define SDRAM_REFRESH_MASK (SDRAM_REFRESH_MAX << SDRAM_REFRESH_OFFS) -+#define SDRAM_DWIDTH_OFFS 15 -+#define SDRAM_DWIDTH_MASK (1 << SDRAM_DWIDTH_OFFS) -+#define SDRAM_DWIDTH_32BIT (0 << SDRAM_DWIDTH_OFFS) -+#define SDRAM_DWIDTH_64BIT (1 << SDRAM_DWIDTH_OFFS) -+#define SDRAM_REGISTERED (1 << 17) -+#define SDRAM_ECC_OFFS 18 -+#define SDRAM_ECC_MASK (1 << SDRAM_ECC_OFFS) -+#define SDRAM_ECC_DIS (0 << SDRAM_ECC_OFFS) -+#define SDRAM_ECC_EN (1 << SDRAM_ECC_OFFS) -+#define SDRAM_IERR_OFFS 19 -+#define SDRAM_IERR_MASK (1 << SDRAM_IERR_OFFS) -+#define SDRAM_IERR_REPORTE (0 << SDRAM_IERR_OFFS) -+#define SDRAM_IERR_IGNORE (1 << SDRAM_IERR_OFFS) -+#define SDRAM_SRMODE_OFFS 24 -+#define SDRAM_SRMODE_MASK (1 << SDRAM_SRMODE_OFFS) -+#define SDRAM_SRMODE_POWER (0 << SDRAM_SRMODE_OFFS) -+#define SDRAM_SRMODE_DRAM (1 << SDRAM_SRMODE_OFFS) -+ -+/* dunit control low register */ -+#define SDRAM_DUNIT_CTRL_REG (DRAM_BASE + 0x1404) -+#define SDRAM_2T_OFFS 4 -+#define SDRAM_2T_MASK (1 << SDRAM_2T_OFFS) -+#define SDRAM_2T_MODE (1 << SDRAM_2T_OFFS) -+ -+#define SDRAM_SRCLK_OFFS 5 -+#define SDRAM_SRCLK_MASK (1 << SDRAM_SRCLK_OFFS) -+#define SDRAM_SRCLK_KEPT (0 << SDRAM_SRCLK_OFFS) -+#define SDRAM_SRCLK_GATED (1 << SDRAM_SRCLK_OFFS) -+#define SDRAM_CTRL_POS_OFFS 6 -+#define SDRAM_CTRL_POS_MASK (1 << SDRAM_CTRL_POS_OFFS) -+#define SDRAM_CTRL_POS_FALL (0 << SDRAM_CTRL_POS_OFFS) -+#define SDRAM_CTRL_POS_RISE (1 << SDRAM_CTRL_POS_OFFS) -+#define SDRAM_CLK1DRV_OFFS 12 -+#define SDRAM_CLK1DRV_MASK (1 << SDRAM_CLK1DRV_OFFS) -+#define SDRAM_CLK1DRV_HIGH_Z (0 << SDRAM_CLK1DRV_OFFS) -+#define SDRAM_CLK1DRV_NORMAL (1 << SDRAM_CLK1DRV_OFFS) -+#define SDRAM_CLK2DRV_OFFS 13 -+#define SDRAM_CLK2DRV_MASK (1 << SDRAM_CLK2DRV_OFFS) -+#define SDRAM_CLK2DRV_HIGH_Z (0 << SDRAM_CLK2DRV_OFFS) -+#define SDRAM_CLK2DRV_NORMAL (1 << SDRAM_CLK2DRV_OFFS) -+#define SDRAM_SB_OUT_DEL_OFFS 20 -+#define SDRAM_SB_OUT_DEL_MAX 0xf -+#define SDRAM_SB_OUT_MASK (SDRAM_SB_OUT_DEL_MAX<= MV_DRAM_MAX_CS )) -+ { -+ DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); -+ return MV_BAD_PARAM; -+ } -+ memset(pBankInfo, 0, sizeof(*pBankInfo)); -+ -+ if ( MV_OK != dimmSpdGet((MV_U32)(bankNum/2), &dimmInfo)) -+ { -+ DB(mvOsPrintf("Dram: ERR dimmSpdGet failed to get dimm info \n")); -+ return MV_FAIL; -+ } -+ if ((dimmInfo.numOfModuleBanks == 1) && ((bankNum % 2) == 1)) -+ { -+ DB(mvOsPrintf("Dram: ERR dimmSpdGet. Can't find DIMM bank 2 \n")); -+ return MV_FAIL; -+ } -+ /* convert Dimm info to Bank info */ -+ cpyDimm2BankInfo(&dimmInfo, pBankInfo); -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* cpyDimm2BankInfo - Convert a Dimm info struct into a bank info struct. -+* -+* DESCRIPTION: -+* Convert a Dimm info struct into a bank info struct. -+* -+* INPUT: -+* pDimmInfo - DIMM information structure. -+* -+* OUTPUT: -+* pBankInfo - DRAM bank information struct. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+static MV_VOID cpyDimm2BankInfo(MV_DIMM_INFO *pDimmInfo, -+ MV_DRAM_BANK_INFO *pBankInfo) -+{ -+ pBankInfo->memoryType = pDimmInfo->memoryType; -+ -+ /* DIMM dimensions */ -+ pBankInfo->numOfRowAddr = pDimmInfo->numOfRowAddr; -+ pBankInfo->numOfColAddr = pDimmInfo->numOfColAddr; -+ pBankInfo->dataWidth = pDimmInfo->dataWidth; -+ pBankInfo->errorCheckType = pDimmInfo->errorCheckType; -+ pBankInfo->sdramWidth = pDimmInfo->sdramWidth; -+ pBankInfo->errorCheckDataWidth = pDimmInfo->errorCheckDataWidth; -+ pBankInfo->numOfBanksOnEachDevice = pDimmInfo->numOfBanksOnEachDevice; -+ pBankInfo->suportedCasLatencies = pDimmInfo->suportedCasLatencies; -+ pBankInfo->refreshInterval = pDimmInfo->refreshInterval; -+ -+ /* DIMM timing parameters */ -+ pBankInfo->minCycleTimeAtMaxCasLatPs = pDimmInfo->minCycleTimeAtMaxCasLatPs; -+ pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps = -+ pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps; -+ pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps = -+ pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps; -+ -+ pBankInfo->minRowPrechargeTime = pDimmInfo->minRowPrechargeTime; -+ pBankInfo->minRowActiveToRowActive = pDimmInfo->minRowActiveToRowActive; -+ pBankInfo->minRasToCasDelay = pDimmInfo->minRasToCasDelay; -+ pBankInfo->minRasPulseWidth = pDimmInfo->minRasPulseWidth; -+ pBankInfo->minWriteRecoveryTime = pDimmInfo->minWriteRecoveryTime; -+ pBankInfo->minWriteToReadCmdDelay = pDimmInfo->minWriteToReadCmdDelay; -+ pBankInfo->minReadToPrechCmdDelay = pDimmInfo->minReadToPrechCmdDelay; -+ pBankInfo->minRefreshToActiveCmd = pDimmInfo->minRefreshToActiveCmd; -+ -+ /* Parameters calculated from the extracted DIMM information */ -+ pBankInfo->size = pDimmInfo->size/pDimmInfo->numOfModuleBanks; -+ pBankInfo->deviceDensity = pDimmInfo->deviceDensity; -+ pBankInfo->numberOfDevices = pDimmInfo->numberOfDevices / -+ pDimmInfo->numOfModuleBanks; -+ -+ /* DIMM attributes (MV_TRUE for yes) */ -+ -+ if ((pDimmInfo->memoryType == MEM_TYPE_SDRAM) || -+ (pDimmInfo->memoryType == MEM_TYPE_DDR1) ) -+ { -+ if (pDimmInfo->dimmAttributes & BIT1) -+ pBankInfo->registeredAddrAndControlInputs = MV_TRUE; -+ else -+ pBankInfo->registeredAddrAndControlInputs = MV_FALSE; -+ } -+ else /* pDimmInfo->memoryType == MEM_TYPE_DDR2 */ -+ { -+ if (pDimmInfo->dimmTypeInfo & (BIT0 | BIT4)) -+ pBankInfo->registeredAddrAndControlInputs = MV_TRUE; -+ else -+ pBankInfo->registeredAddrAndControlInputs = MV_FALSE; -+ } -+ -+ return; -+} -+/******************************************************************************* -+* dimmSpdCpy - Cpy SPD parameters from dimm 0 to dimm 1. -+* -+* DESCRIPTION: -+* Read the DIMM SPD parameters from dimm 0 into dimm 1 SPD. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+MV_STATUS dimmSpdCpy(MV_VOID) -+{ -+ MV_U32 i; -+ MV_U32 spdChecksum; -+ -+ MV_TWSI_SLAVE twsiSlave; -+ MV_U8 data[SPD_SIZE]; -+ -+ /* zero dimmInfo structure */ -+ memset(data, 0, SPD_SIZE); -+ -+ /* read the dimm eeprom */ -+ DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); -+ twsiSlave.slaveAddr.address = MV_BOARD_DIMM0_I2C_ADDR; -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ twsiSlave.offset = 0; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, &twsiSlave, data, SPD_SIZE) ) -+ { -+ DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 0\n")); -+ return MV_FAIL; -+ } -+ DB(puts("DRAM: Reading dimm info succeded.\n")); -+ -+ /* calculate SPD checksum */ -+ spdChecksum = 0; -+ -+ for(i = 0 ; i <= 62 ; i++) -+ { -+ spdChecksum += data[i]; -+ } -+ -+ if ((spdChecksum & 0xff) != data[63]) -+ { -+ DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", -+ (MV_U32)(spdChecksum & 0xff), data[63])); -+ } -+ else -+ { -+ DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); -+ } -+ -+ /* copy the SPD content 1:1 into the DIMM 1 SPD */ -+ twsiSlave.slaveAddr.address = MV_BOARD_DIMM1_I2C_ADDR; -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ twsiSlave.offset = 0; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ for(i = 0 ; i < SPD_SIZE ; i++) -+ { -+ twsiSlave.offset = i; -+ if( MV_OK != mvTwsiWrite (MV_BOARD_DIMM_I2C_CHANNEL, &twsiSlave, &data[i], 1) ) -+ { -+ mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 1 byte %d \n",i); -+ return MV_FAIL; -+ } -+ mvOsDelay(5); -+ } -+ -+ DB(puts("DRAM: Reading dimm info succeded.\n")); -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* dimmSpdGet - Get the SPD parameters. -+* -+* DESCRIPTION: -+* Read the DIMM SPD parameters into given struct parameter. -+* -+* INPUT: -+* dimmNum - DIMM number. See MV_BOARD_DIMM_NUM enumerator. -+* -+* OUTPUT: -+* pDimmInfo - DIMM information structure. -+* -+* RETURN: -+* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo) -+{ -+ MV_U32 i; -+ MV_U32 density = 1; -+ MV_U32 spdChecksum; -+ -+ MV_TWSI_SLAVE twsiSlave; -+ MV_U8 data[SPD_SIZE]; -+ -+ if((NULL == pDimmInfo)|| (dimmNum >= MAX_DIMM_NUM)) -+ { -+ DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); -+ return MV_BAD_PARAM; -+ } -+ -+ /* zero dimmInfo structure */ -+ memset(data, 0, SPD_SIZE); -+ -+ /* read the dimm eeprom */ -+ DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); -+ twsiSlave.slaveAddr.address = (dimmNum == 0) ? -+ MV_BOARD_DIMM0_I2C_ADDR : MV_BOARD_DIMM1_I2C_ADDR; -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ twsiSlave.offset = 0; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, &twsiSlave, data, SPD_SIZE) ) -+ { -+ DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum %d \n", dimmNum)); -+ return MV_FAIL; -+ } -+ DB(puts("DRAM: Reading dimm info succeded.\n")); -+ -+ /* calculate SPD checksum */ -+ spdChecksum = 0; -+ -+ for(i = 0 ; i <= 62 ; i++) -+ { -+ spdChecksum += data[i]; -+ } -+ -+ if ((spdChecksum & 0xff) != data[63]) -+ { -+ DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", -+ (MV_U32)(spdChecksum & 0xff), data[63])); -+ } -+ else -+ { -+ DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); -+ } -+ -+ /* copy the SPD content 1:1 into the dimmInfo structure*/ -+ for(i = 0 ; i < SPD_SIZE ; i++) -+ { -+ pDimmInfo->spdRawData[i] = data[i]; -+ DB(mvOsPrintf("SPD-EEPROM Byte %3d = %3x (%3d)\n",i, data[i], data[i])); -+ } -+ -+ DB(mvOsPrintf("DRAM SPD Information:\n")); -+ -+ /* Memory type (DDR / SDRAM) */ -+ switch (data[DIMM_MEM_TYPE]) -+ { -+ case (DIMM_MEM_TYPE_SDRAM): -+ pDimmInfo->memoryType = MEM_TYPE_SDRAM; -+ DB(mvOsPrintf("DRAM Memeory type SDRAM\n")); -+ break; -+ case (DIMM_MEM_TYPE_DDR1): -+ pDimmInfo->memoryType = MEM_TYPE_DDR1; -+ DB(mvOsPrintf("DRAM Memeory type DDR1\n")); -+ break; -+ case (DIMM_MEM_TYPE_DDR2): -+ pDimmInfo->memoryType = MEM_TYPE_DDR2; -+ DB(mvOsPrintf("DRAM Memeory type DDR2\n")); -+ break; -+ default: -+ mvOsPrintf("ERROR: Undefined memory type!\n"); -+ return MV_ERROR; -+ } -+ -+ -+ /* Number Of Row Addresses */ -+ pDimmInfo->numOfRowAddr = data[DIMM_ROW_NUM]; -+ DB(mvOsPrintf("DRAM numOfRowAddr[3] %d\n",pDimmInfo->numOfRowAddr)); -+ -+ /* Number Of Column Addresses */ -+ pDimmInfo->numOfColAddr = data[DIMM_COL_NUM]; -+ DB(mvOsPrintf("DRAM numOfColAddr[4] %d\n",pDimmInfo->numOfColAddr)); -+ -+ /* Number Of Module Banks */ -+ pDimmInfo->numOfModuleBanks = data[DIMM_MODULE_BANK_NUM]; -+ DB(mvOsPrintf("DRAM numOfModuleBanks[5] 0x%x\n", -+ pDimmInfo->numOfModuleBanks)); -+ -+ /* Number of module banks encoded differently for DDR2 */ -+ if (pDimmInfo->memoryType == MEM_TYPE_DDR2) -+ pDimmInfo->numOfModuleBanks = (pDimmInfo->numOfModuleBanks & 0x7)+1; -+ -+ /* Data Width */ -+ pDimmInfo->dataWidth = data[DIMM_DATA_WIDTH]; -+ DB(mvOsPrintf("DRAM dataWidth[6] 0x%x\n", pDimmInfo->dataWidth)); -+ -+ /* Minimum Cycle Time At Max CasLatancy */ -+ pDimmInfo->minCycleTimeAtMaxCasLatPs = cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS]); -+ -+ /* Error Check Type */ -+ pDimmInfo->errorCheckType = data[DIMM_ERR_CHECK_TYPE]; -+ DB(mvOsPrintf("DRAM errorCheckType[11] 0x%x\n", -+ pDimmInfo->errorCheckType)); -+ -+ /* Refresh Interval */ -+ pDimmInfo->refreshInterval = data[DIMM_REFRESH_INTERVAL]; -+ DB(mvOsPrintf("DRAM refreshInterval[12] 0x%x\n", -+ pDimmInfo->refreshInterval)); -+ -+ /* Sdram Width */ -+ pDimmInfo->sdramWidth = data[DIMM_SDRAM_WIDTH]; -+ DB(mvOsPrintf("DRAM sdramWidth[13] 0x%x\n",pDimmInfo->sdramWidth)); -+ -+ /* Error Check Data Width */ -+ pDimmInfo->errorCheckDataWidth = data[DIMM_ERR_CHECK_DATA_WIDTH]; -+ DB(mvOsPrintf("DRAM errorCheckDataWidth[14] 0x%x\n", -+ pDimmInfo->errorCheckDataWidth)); -+ -+ /* Burst Length Supported */ -+ /* SDRAM/DDR1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * -+ *********************************************************/ -+ /* DDR2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * -+ *********************************************************/ -+ -+ pDimmInfo->burstLengthSupported = data[DIMM_BURST_LEN_SUP]; -+ DB(mvOsPrintf("DRAM burstLengthSupported[16] 0x%x\n", -+ pDimmInfo->burstLengthSupported)); -+ -+ /* Number Of Banks On Each Device */ -+ pDimmInfo->numOfBanksOnEachDevice = data[DIMM_DEV_BANK_NUM]; -+ DB(mvOsPrintf("DRAM numOfBanksOnEachDevice[17] 0x%x\n", -+ pDimmInfo->numOfBanksOnEachDevice)); -+ -+ /* Suported Cas Latencies */ -+ -+ /* SDRAM: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * -+ ********************************************************/ -+ -+ /* DDR 1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * -+ *********************************************************/ -+ -+ /* DDR 2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * -+ *********************************************************/ -+ -+ pDimmInfo->suportedCasLatencies = data[DIMM_SUP_CAL]; -+ DB(mvOsPrintf("DRAM suportedCasLatencies[18] 0x%x\n", -+ pDimmInfo->suportedCasLatencies)); -+ -+ /* For DDR2 only, get the DIMM type information */ -+ if (pDimmInfo->memoryType == MEM_TYPE_DDR2) -+ { -+ pDimmInfo->dimmTypeInfo = data[DIMM_DDR2_TYPE_INFORMATION]; -+ DB(mvOsPrintf("DRAM dimmTypeInfo[20] (DDR2) 0x%x\n", -+ pDimmInfo->dimmTypeInfo)); -+ } -+ -+ /* SDRAM Modules Attributes */ -+ pDimmInfo->dimmAttributes = data[DIMM_BUF_ADDR_CONT_IN]; -+ DB(mvOsPrintf("DRAM dimmAttributes[21] 0x%x\n", -+ pDimmInfo->dimmAttributes)); -+ -+ /* Minimum Cycle Time At Max CasLatancy Minus 1*/ -+ pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps = -+ cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS1]); -+ -+ /* Minimum Cycle Time At Max CasLatancy Minus 2*/ -+ pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps = -+ cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS2]); -+ -+ pDimmInfo->minRowPrechargeTime = data[DIMM_MIN_ROW_PRECHARGE_TIME]; -+ DB(mvOsPrintf("DRAM minRowPrechargeTime[27] 0x%x\n", -+ pDimmInfo->minRowPrechargeTime)); -+ pDimmInfo->minRowActiveToRowActive = data[DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE]; -+ DB(mvOsPrintf("DRAM minRowActiveToRowActive[28] 0x%x\n", -+ pDimmInfo->minRowActiveToRowActive)); -+ pDimmInfo->minRasToCasDelay = data[DIMM_MIN_RAS_TO_CAS_DELAY]; -+ DB(mvOsPrintf("DRAM minRasToCasDelay[29] 0x%x\n", -+ pDimmInfo->minRasToCasDelay)); -+ pDimmInfo->minRasPulseWidth = data[DIMM_MIN_RAS_PULSE_WIDTH]; -+ DB(mvOsPrintf("DRAM minRasPulseWidth[30] 0x%x\n", -+ pDimmInfo->minRasPulseWidth)); -+ -+ /* DIMM Bank Density */ -+ pDimmInfo->dimmBankDensity = data[DIMM_BANK_DENSITY]; -+ DB(mvOsPrintf("DRAM dimmBankDensity[31] 0x%x\n", -+ pDimmInfo->dimmBankDensity)); -+ -+ /* Only DDR2 includes Write Recovery Time field. Other SDRAM ignore */ -+ pDimmInfo->minWriteRecoveryTime = data[DIMM_MIN_WRITE_RECOVERY_TIME]; -+ DB(mvOsPrintf("DRAM minWriteRecoveryTime[36] 0x%x\n", -+ pDimmInfo->minWriteRecoveryTime)); -+ -+ /* Only DDR2 includes Internal Write To Read Command Delay field. */ -+ pDimmInfo->minWriteToReadCmdDelay = data[DIMM_MIN_WRITE_TO_READ_CMD_DELAY]; -+ DB(mvOsPrintf("DRAM minWriteToReadCmdDelay[37] 0x%x\n", -+ pDimmInfo->minWriteToReadCmdDelay)); -+ -+ /* Only DDR2 includes Internal Read To Precharge Command Delay field. */ -+ pDimmInfo->minReadToPrechCmdDelay = data[DIMM_MIN_READ_TO_PRECH_CMD_DELAY]; -+ DB(mvOsPrintf("DRAM minReadToPrechCmdDelay[38] 0x%x\n", -+ pDimmInfo->minReadToPrechCmdDelay)); -+ -+ /* Only DDR2 includes Minimum Refresh to Activate/Refresh Command field */ -+ pDimmInfo->minRefreshToActiveCmd = data[DIMM_MIN_REFRESH_TO_ACTIVATE_CMD]; -+ DB(mvOsPrintf("DRAM minRefreshToActiveCmd[42] 0x%x\n", -+ pDimmInfo->minRefreshToActiveCmd)); -+ -+ /* calculating the sdram density. Representing device density from */ -+ /* bit 20 to allow representation of 4GB and above. */ -+ /* For example, if density is 512Mbit 0x20000000, will be represent in */ -+ /* deviceDensity by 0x20000000 >> 16 --> 0x00000200. Another example */ -+ /* is density 8GB 0x200000000 >> 16 --> 0x00002000. */ -+ density = (1 << ((pDimmInfo->numOfRowAddr + pDimmInfo->numOfColAddr) - 20)); -+ pDimmInfo->deviceDensity = density * -+ pDimmInfo->numOfBanksOnEachDevice * -+ pDimmInfo->sdramWidth; -+ DB(mvOsPrintf("DRAM deviceDensity %d\n",pDimmInfo->deviceDensity)); -+ -+ /* Number of devices includeing Error correction */ -+ pDimmInfo->numberOfDevices = (pDimmInfo->dataWidth/pDimmInfo->sdramWidth) * -+ pDimmInfo->numOfModuleBanks; -+ DB(mvOsPrintf("DRAM numberOfDevices %d\n", -+ pDimmInfo->numberOfDevices)); -+ -+ pDimmInfo->size = 0; -+ -+ /* Note that pDimmInfo->size is in MB units */ -+ if (pDimmInfo->memoryType == MEM_TYPE_SDRAM) -+ { -+ if (pDimmInfo->dimmBankDensity & BIT0) -+ pDimmInfo->size += 1024; /* Equal to 1GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT1) -+ pDimmInfo->size += 8; /* Equal to 8MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT2) -+ pDimmInfo->size += 16; /* Equal to 16MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT3) -+ pDimmInfo->size += 32; /* Equal to 32MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT4) -+ pDimmInfo->size += 64; /* Equal to 64MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT5) -+ pDimmInfo->size += 128; /* Equal to 128MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT6) -+ pDimmInfo->size += 256; /* Equal to 256MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT7) -+ pDimmInfo->size += 512; /* Equal to 512MB */ -+ } -+ else if (pDimmInfo->memoryType == MEM_TYPE_DDR1) -+ { -+ if (pDimmInfo->dimmBankDensity & BIT0) -+ pDimmInfo->size += 1024; /* Equal to 1GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT1) -+ pDimmInfo->size += 2048; /* Equal to 2GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT2) -+ pDimmInfo->size += 16; /* Equal to 16MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT3) -+ pDimmInfo->size += 32; /* Equal to 32MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT4) -+ pDimmInfo->size += 64; /* Equal to 64MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT5) -+ pDimmInfo->size += 128; /* Equal to 128MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT6) -+ pDimmInfo->size += 256; /* Equal to 256MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT7) -+ pDimmInfo->size += 512; /* Equal to 512MB */ -+ } -+ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ -+ { -+ if (pDimmInfo->dimmBankDensity & BIT0) -+ pDimmInfo->size += 1024; /* Equal to 1GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT1) -+ pDimmInfo->size += 2048; /* Equal to 2GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT2) -+ pDimmInfo->size += 4096; /* Equal to 4GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT3) -+ pDimmInfo->size += 8192; /* Equal to 8GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT4) -+ pDimmInfo->size += 16384; /* Equal to 16GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT5) -+ pDimmInfo->size += 128; /* Equal to 128MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT6) -+ pDimmInfo->size += 256; /* Equal to 256MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT7) -+ pDimmInfo->size += 512; /* Equal to 512MB */ -+ } -+ -+ pDimmInfo->size *= pDimmInfo->numOfModuleBanks; -+ -+ DB(mvOsPrintf("Dram: dimm size %dMB \n",pDimmInfo->size)); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* dimmSpdPrint - Print the SPD parameters. -+* -+* DESCRIPTION: -+* Print the Dimm SPD parameters. -+* -+* INPUT: -+* pDimmInfo - DIMM information structure. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID dimmSpdPrint(MV_U32 dimmNum) -+{ -+ MV_DIMM_INFO dimmInfo; -+ MV_U32 i, temp = 0; -+ MV_U32 k, maskLeftOfPoint = 0, maskRightOfPoint = 0; -+ MV_U32 rightOfPoint = 0,leftOfPoint = 0, div, time_tmp, shift; -+ MV_U32 busClkPs; -+ MV_U8 trp_clocks=0, trcd_clocks, tras_clocks, trrd_clocks, -+ temp_buf[40], *spdRawData; -+ -+ busClkPs = 1000000000 / (mvBoardSysClkGet() / 100); /* in 10 ps units */ -+ -+ spdRawData = dimmInfo.spdRawData; -+ -+ if(MV_OK != dimmSpdGet(dimmNum, &dimmInfo)) -+ { -+ mvOsOutput("ERROR: Could not read SPD information!\n"); -+ return; -+ } -+ -+ /* find Manufactura of Dimm Module */ -+ mvOsOutput("\nManufacturer's JEDEC ID Code: "); -+ for(i = 0 ; i < DIMM_MODULE_MANU_SIZE ; i++) -+ { -+ mvOsOutput("%x",spdRawData[DIMM_MODULE_MANU_OFFS + i]); -+ } -+ mvOsOutput("\n"); -+ -+ /* Manufacturer's Specific Data */ -+ for(i = 0 ; i < DIMM_MODULE_ID_SIZE ; i++) -+ { -+ temp_buf[i] = spdRawData[DIMM_MODULE_ID_OFFS + i]; -+ } -+ mvOsOutput("Manufacturer's Specific Data: %s\n", temp_buf); -+ -+ /* Module Part Number */ -+ for(i = 0 ; i < DIMM_MODULE_VEN_SIZE ; i++) -+ { -+ temp_buf[i] = spdRawData[DIMM_MODULE_VEN_OFFS + i]; -+ } -+ mvOsOutput("Module Part Number: %s\n", temp_buf); -+ -+ /* Module Serial Number */ -+ for(i = 0; i < sizeof(MV_U32); i++) -+ { -+ temp |= spdRawData[95+i] << 8*i; -+ } -+ mvOsOutput("DIMM Serial No. %ld (%lx)\n", (long)temp, -+ (long)temp); -+ -+ /* find Manufac-Data of Dimm Module */ -+ mvOsOutput("Manufactoring Date: Year 20%d%d/ ww %d%d\n", -+ ((spdRawData[93] & 0xf0) >> 4), (spdRawData[93] & 0xf), -+ ((spdRawData[94] & 0xf0) >> 4), (spdRawData[94] & 0xf)); -+ /* find modul_revision of Dimm Module */ -+ mvOsOutput("Module Revision: %d.%d\n", -+ spdRawData[62]/10, spdRawData[62]%10); -+ -+ /* find manufac_place of Dimm Module */ -+ mvOsOutput("manufac_place: %d\n", spdRawData[72]); -+ -+ /* go over the first 35 I2C data bytes */ -+ for(i = 2 ; i <= 35 ; i++) -+ switch(i) -+ { -+ case 2: /* Memory type (DDR1/2 / SDRAM) */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ mvOsOutput("Dram Type is: SDRAM\n"); -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ mvOsOutput("Dram Type is: SDRAM DDR1\n"); -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) -+ mvOsOutput("Dram Type is: SDRAM DDR2\n"); -+ else -+ mvOsOutput("Dram Type unknown\n"); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 3: /* Number Of Row Addresses */ -+ mvOsOutput("Module Number of row addresses: %d\n", -+ dimmInfo.numOfRowAddr); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 4: /* Number Of Column Addresses */ -+ mvOsOutput("Module Number of col addresses: %d\n", -+ dimmInfo.numOfColAddr); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 5: /* Number Of Module Banks */ -+ mvOsOutput("Number of Banks on Mod.: %d\n", -+ dimmInfo.numOfModuleBanks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 6: /* Data Width */ -+ mvOsOutput("Module Data Width: %d bit\n", -+ dimmInfo.dataWidth); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 8: /* Voltage Interface */ -+ switch(spdRawData[i]) -+ { -+ case 0x0: -+ mvOsOutput("Module is TTL_5V_TOLERANT\n"); -+ break; -+ case 0x1: -+ mvOsOutput("Module is LVTTL\n"); -+ break; -+ case 0x2: -+ mvOsOutput("Module is HSTL_1_5V\n"); -+ break; -+ case 0x3: -+ mvOsOutput("Module is SSTL_3_3V\n"); -+ break; -+ case 0x4: -+ mvOsOutput("Module is SSTL_2_5V\n"); -+ break; -+ case 0x5: -+ if (dimmInfo.memoryType != MEM_TYPE_SDRAM) -+ { -+ mvOsOutput("Module is SSTL_1_8V\n"); -+ break; -+ } -+ default: -+ mvOsOutput("Module is VOLTAGE_UNKNOWN\n"); -+ break; -+ } -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 9: /* Minimum Cycle Time At Max CasLatancy */ -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ rightOfPoint = (spdRawData[i] & 0x0f) * 10; -+ -+ /* DDR2 addition of right of point */ -+ if ((spdRawData[i] & 0x0f) == 0xA) -+ { -+ rightOfPoint = 25; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xB) -+ { -+ rightOfPoint = 33; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xC) -+ { -+ rightOfPoint = 66; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xD) -+ { -+ rightOfPoint = 75; -+ } -+ mvOsOutput("Minimum Cycle Time At Max CL: %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 10: /* Clock To Data Out */ -+ div = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 10:100; -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / div; -+ rightOfPoint = time_tmp % div; -+ mvOsOutput("Clock To Data Out: %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 11: /* Error Check Type */ -+ mvOsOutput("Error Check Type (0=NONE): %d\n", -+ dimmInfo.errorCheckType); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 12: /* Refresh Interval */ -+ mvOsOutput("Refresh Rate: %x\n", -+ dimmInfo.refreshInterval); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 13: /* Sdram Width */ -+ mvOsOutput("Sdram Width: %d bits\n", -+ dimmInfo.sdramWidth); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 14: /* Error Check Data Width */ -+ mvOsOutput("Error Check Data Width: %d bits\n", -+ dimmInfo.errorCheckDataWidth); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 15: /* Minimum Clock Delay is unsupported */ -+ if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || -+ (dimmInfo.memoryType == MEM_TYPE_DDR1)) -+ { -+ mvOsOutput("Minimum Clk Delay back to back: %d\n", -+ spdRawData[i]); -+ } -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 16: /* Burst Length Supported */ -+ /* SDRAM/DDR1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * -+ *********************************************************/ -+ /* DDR2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * -+ *********************************************************/ -+ mvOsOutput("Burst Length Supported: "); -+ if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || -+ (dimmInfo.memoryType == MEM_TYPE_DDR1)) -+ { -+ if (dimmInfo.burstLengthSupported & BIT0) -+ mvOsOutput("1, "); -+ if (dimmInfo.burstLengthSupported & BIT1) -+ mvOsOutput("2, "); -+ } -+ if (dimmInfo.burstLengthSupported & BIT2) -+ mvOsOutput("4, "); -+ if (dimmInfo.burstLengthSupported & BIT3) -+ mvOsOutput("8, "); -+ -+ mvOsOutput(" Bit \n"); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 17: /* Number Of Banks On Each Device */ -+ mvOsOutput("Number Of Banks On Each Chip: %d\n", -+ dimmInfo.numOfBanksOnEachDevice); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 18: /* Suported Cas Latencies */ -+ -+ /* SDRAM: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * -+ ********************************************************/ -+ -+ /* DDR 1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * -+ *********************************************************/ -+ -+ /* DDR 2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * -+ *********************************************************/ -+ -+ mvOsOutput("Suported Cas Latencies: (CL) "); -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ for (k = 0; k <=7; k++) -+ { -+ if (dimmInfo.suportedCasLatencies & (1 << k)) -+ mvOsOutput("%d, ", k+1); -+ } -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ { -+ if (dimmInfo.suportedCasLatencies & BIT0) -+ mvOsOutput("1, "); -+ if (dimmInfo.suportedCasLatencies & BIT1) -+ mvOsOutput("1.5, "); -+ if (dimmInfo.suportedCasLatencies & BIT2) -+ mvOsOutput("2, "); -+ if (dimmInfo.suportedCasLatencies & BIT3) -+ mvOsOutput("2.5, "); -+ if (dimmInfo.suportedCasLatencies & BIT4) -+ mvOsOutput("3, "); -+ if (dimmInfo.suportedCasLatencies & BIT5) -+ mvOsOutput("3.5, "); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) -+ { -+ if (dimmInfo.suportedCasLatencies & BIT2) -+ mvOsOutput("2, "); -+ if (dimmInfo.suportedCasLatencies & BIT3) -+ mvOsOutput("3, "); -+ if (dimmInfo.suportedCasLatencies & BIT4) -+ mvOsOutput("4, "); -+ if (dimmInfo.suportedCasLatencies & BIT5) -+ mvOsOutput("5, "); -+ } -+ else -+ mvOsOutput("?.?, "); -+ mvOsOutput("\n"); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 20: /* DDR2 DIMM type info */ -+ if (dimmInfo.memoryType == MEM_TYPE_DDR2) -+ { -+ if (dimmInfo.dimmTypeInfo & (BIT0 | BIT4)) -+ mvOsOutput("Registered DIMM (RDIMM)\n"); -+ else if (dimmInfo.dimmTypeInfo & (BIT1 | BIT5)) -+ mvOsOutput("Unbuffered DIMM (UDIMM)\n"); -+ else -+ mvOsOutput("Unknown DIMM type.\n"); -+ } -+ -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 21: /* SDRAM Modules Attributes */ -+ mvOsOutput("\nModule Attributes (SPD Byte 21): \n"); -+ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ if (dimmInfo.dimmAttributes & BIT0) -+ mvOsOutput(" Buffered Addr/Control Input: Yes\n"); -+ else -+ mvOsOutput(" Buffered Addr/Control Input: No\n"); -+ -+ if (dimmInfo.dimmAttributes & BIT1) -+ mvOsOutput(" Registered Addr/Control Input: Yes\n"); -+ else -+ mvOsOutput(" Registered Addr/Control Input: No\n"); -+ -+ if (dimmInfo.dimmAttributes & BIT2) -+ mvOsOutput(" On-Card PLL (clock): Yes \n"); -+ else -+ mvOsOutput(" On-Card PLL (clock): No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT3) -+ mvOsOutput(" Bufferd DQMB Input: Yes \n"); -+ else -+ mvOsOutput(" Bufferd DQMB Inputs: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT4) -+ mvOsOutput(" Registered DQMB Inputs: Yes \n"); -+ else -+ mvOsOutput(" Registered DQMB Inputs: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT5) -+ mvOsOutput(" Differential Clock Input: Yes \n"); -+ else -+ mvOsOutput(" Differential Clock Input: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT6) -+ mvOsOutput(" redundant Row Addressing: Yes \n"); -+ else -+ mvOsOutput(" redundant Row Addressing: No \n"); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ { -+ if (dimmInfo.dimmAttributes & BIT0) -+ mvOsOutput(" Buffered Addr/Control Input: Yes\n"); -+ else -+ mvOsOutput(" Buffered Addr/Control Input: No\n"); -+ -+ if (dimmInfo.dimmAttributes & BIT1) -+ mvOsOutput(" Registered Addr/Control Input: Yes\n"); -+ else -+ mvOsOutput(" Registered Addr/Control Input: No\n"); -+ -+ if (dimmInfo.dimmAttributes & BIT2) -+ mvOsOutput(" On-Card PLL (clock): Yes \n"); -+ else -+ mvOsOutput(" On-Card PLL (clock): No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT3) -+ mvOsOutput(" FET Switch On-Card Enabled: Yes \n"); -+ else -+ mvOsOutput(" FET Switch On-Card Enabled: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT4) -+ mvOsOutput(" FET Switch External Enabled: Yes \n"); -+ else -+ mvOsOutput(" FET Switch External Enabled: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT5) -+ mvOsOutput(" Differential Clock Input: Yes \n"); -+ else -+ mvOsOutput(" Differential Clock Input: No \n"); -+ } -+ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ -+ { -+ mvOsOutput(" Number of Active Registers on the DIMM: %d\n", -+ (dimmInfo.dimmAttributes & 0x3) + 1); -+ -+ mvOsOutput(" Number of PLLs on the DIMM: %d\n", -+ ((dimmInfo.dimmAttributes) >> 2) & 0x3); -+ -+ if (dimmInfo.dimmAttributes & BIT4) -+ mvOsOutput(" FET Switch External Enabled: Yes \n"); -+ else -+ mvOsOutput(" FET Switch External Enabled: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT6) -+ mvOsOutput(" Analysis probe installed: Yes \n"); -+ else -+ mvOsOutput(" Analysis probe installed: No \n"); -+ } -+ -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 22: /* Suported AutoPreCharge */ -+ mvOsOutput("\nModul Attributes (SPD Byte 22): \n"); -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ if ( spdRawData[i] & BIT0 ) -+ mvOsOutput(" Early Ras Precharge: Yes \n"); -+ else -+ mvOsOutput(" Early Ras Precharge: No \n"); -+ -+ if ( spdRawData[i] & BIT1 ) -+ mvOsOutput(" AutoPreCharge: Yes \n"); -+ else -+ mvOsOutput(" AutoPreCharge: No \n"); -+ -+ if ( spdRawData[i] & BIT2 ) -+ mvOsOutput(" Precharge All: Yes \n"); -+ else -+ mvOsOutput(" Precharge All: No \n"); -+ -+ if ( spdRawData[i] & BIT3 ) -+ mvOsOutput(" Write 1/ReadBurst: Yes \n"); -+ else -+ mvOsOutput(" Write 1/ReadBurst: No \n"); -+ -+ if ( spdRawData[i] & BIT4 ) -+ mvOsOutput(" lower VCC tolerance: 5%%\n"); -+ else -+ mvOsOutput(" lower VCC tolerance: 10%%\n"); -+ -+ if ( spdRawData[i] & BIT5 ) -+ mvOsOutput(" upper VCC tolerance: 5%%\n"); -+ else -+ mvOsOutput(" upper VCC tolerance: 10%%\n"); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ { -+ if ( spdRawData[i] & BIT0 ) -+ mvOsOutput(" Supports Weak Driver: Yes \n"); -+ else -+ mvOsOutput(" Supports Weak Driver: No \n"); -+ -+ if ( !(spdRawData[i] & BIT4) ) -+ mvOsOutput(" lower VCC tolerance: 0.2V\n"); -+ -+ if ( !(spdRawData[i] & BIT5) ) -+ mvOsOutput(" upper VCC tolerance: 0.2V\n"); -+ -+ if ( spdRawData[i] & BIT6 ) -+ mvOsOutput(" Concurrent Auto Preharge: Yes \n"); -+ else -+ mvOsOutput(" Concurrent Auto Preharge: No \n"); -+ -+ if ( spdRawData[i] & BIT7 ) -+ mvOsOutput(" Supports Fast AP: Yes \n"); -+ else -+ mvOsOutput(" Supports Fast AP: No \n"); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) -+ { -+ if ( spdRawData[i] & BIT0 ) -+ mvOsOutput(" Supports Weak Driver: Yes \n"); -+ else -+ mvOsOutput(" Supports Weak Driver: No \n"); -+ } -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 23: -+ /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */ -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ rightOfPoint = (spdRawData[i] & 0x0f) * 10; -+ -+ /* DDR2 addition of right of point */ -+ if ((spdRawData[i] & 0x0f) == 0xA) -+ { -+ rightOfPoint = 25; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xB) -+ { -+ rightOfPoint = 33; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xC) -+ { -+ rightOfPoint = 66; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xD) -+ { -+ rightOfPoint = 75; -+ } -+ -+ mvOsOutput("Minimum Cycle Time At 2nd highest CasLatancy" -+ "(0 = Not supported): %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint ); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 24: /* Clock To Data Out 2nd highest Cas Latency Value*/ -+ div = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? 10:100; -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / div; -+ rightOfPoint = time_tmp % div; -+ mvOsOutput("Clock To Data Out (2nd CL value): %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 25: -+ /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ leftOfPoint = (spdRawData[i] & 0xfc) >> 2; -+ rightOfPoint = (spdRawData[i] & 0x3) * 25; -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ rightOfPoint = (spdRawData[i] & 0x0f) * 10; -+ -+ /* DDR2 addition of right of point */ -+ if ((spdRawData[i] & 0x0f) == 0xA) -+ { -+ rightOfPoint = 25; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xB) -+ { -+ rightOfPoint = 33; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xC) -+ { -+ rightOfPoint = 66; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xD) -+ { -+ rightOfPoint = 75; -+ } -+ } -+ mvOsOutput("Minimum Cycle Time At 3rd highest CasLatancy" -+ "(0 = Not supported): %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint ); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 26: /* Clock To Data Out 3rd highest Cas Latency Value*/ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ leftOfPoint = (spdRawData[i] & 0xfc) >> 2; -+ rightOfPoint = (spdRawData[i] & 0x3) * 25; -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = 0; -+ rightOfPoint = time_tmp; -+ } -+ mvOsOutput("Clock To Data Out (3rd CL value): %d.%2d[ns]\n", -+ leftOfPoint, rightOfPoint ); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 27: /* Minimum Row Precharge Time */ -+ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; -+ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0xff : 0xfc; -+ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0x00 : 0x03; -+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); -+ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; -+ temp = ((leftOfPoint*100) + rightOfPoint);/* in 10ps Intervals*/ -+ trp_clocks = (temp + (busClkPs-1)) / busClkPs; -+ mvOsOutput("Minimum Row Precharge Time [ns]: %d.%d = " -+ "in Clk cycles %d\n", -+ leftOfPoint, rightOfPoint, trp_clocks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 28: /* Minimum Row Active to Row Active Time */ -+ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; -+ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0xff : 0xfc; -+ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0x00 : 0x03; -+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); -+ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; -+ temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ -+ trrd_clocks = (temp + (busClkPs-1)) / busClkPs; -+ mvOsOutput("Minimum Row Active -To- Row Active Delay [ns]: " -+ "%d.%d = in Clk cycles %d\n", -+ leftOfPoint, rightOfPoint, trp_clocks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 29: /* Minimum Ras-To-Cas Delay */ -+ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; -+ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0xff : 0xfc; -+ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0x00 : 0x03; -+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); -+ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; -+ temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ -+ trcd_clocks = (temp + (busClkPs-1) )/ busClkPs; -+ mvOsOutput("Minimum Ras-To-Cas Delay [ns]: %d.%d = " -+ "in Clk cycles %d\n", -+ leftOfPoint, rightOfPoint, trp_clocks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 30: /* Minimum Ras Pulse Width */ -+ tras_clocks = (cas2ps(spdRawData[i])+(busClkPs-1)) / busClkPs; -+ mvOsOutput("Minimum Ras Pulse Width [ns]: %d = " -+ "in Clk cycles %d\n", spdRawData[i], tras_clocks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 31: /* Module Bank Density */ -+ mvOsOutput("Module Bank Density (more than 1= Multisize-Module):"); -+ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ if (dimmInfo.dimmBankDensity & BIT0) -+ mvOsOutput("1GB, "); -+ if (dimmInfo.dimmBankDensity & BIT1) -+ mvOsOutput("8MB, "); -+ if (dimmInfo.dimmBankDensity & BIT2) -+ mvOsOutput("16MB, "); -+ if (dimmInfo.dimmBankDensity & BIT3) -+ mvOsOutput("32MB, "); -+ if (dimmInfo.dimmBankDensity & BIT4) -+ mvOsOutput("64MB, "); -+ if (dimmInfo.dimmBankDensity & BIT5) -+ mvOsOutput("128MB, "); -+ if (dimmInfo.dimmBankDensity & BIT6) -+ mvOsOutput("256MB, "); -+ if (dimmInfo.dimmBankDensity & BIT7) -+ mvOsOutput("512MB, "); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ { -+ if (dimmInfo.dimmBankDensity & BIT0) -+ mvOsOutput("1GB, "); -+ if (dimmInfo.dimmBankDensity & BIT1) -+ mvOsOutput("2GB, "); -+ if (dimmInfo.dimmBankDensity & BIT2) -+ mvOsOutput("16MB, "); -+ if (dimmInfo.dimmBankDensity & BIT3) -+ mvOsOutput("32MB, "); -+ if (dimmInfo.dimmBankDensity & BIT4) -+ mvOsOutput("64MB, "); -+ if (dimmInfo.dimmBankDensity & BIT5) -+ mvOsOutput("128MB, "); -+ if (dimmInfo.dimmBankDensity & BIT6) -+ mvOsOutput("256MB, "); -+ if (dimmInfo.dimmBankDensity & BIT7) -+ mvOsOutput("512MB, "); -+ } -+ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ -+ { -+ if (dimmInfo.dimmBankDensity & BIT0) -+ mvOsOutput("1GB, "); -+ if (dimmInfo.dimmBankDensity & BIT1) -+ mvOsOutput("2GB, "); -+ if (dimmInfo.dimmBankDensity & BIT2) -+ mvOsOutput("4GB, "); -+ if (dimmInfo.dimmBankDensity & BIT3) -+ mvOsOutput("8GB, "); -+ if (dimmInfo.dimmBankDensity & BIT4) -+ mvOsOutput("16GB, "); -+ if (dimmInfo.dimmBankDensity & BIT5) -+ mvOsOutput("128MB, "); -+ if (dimmInfo.dimmBankDensity & BIT6) -+ mvOsOutput("256MB, "); -+ if (dimmInfo.dimmBankDensity & BIT7) -+ mvOsOutput("512MB, "); -+ } -+ mvOsOutput("\n"); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 32: /* Address And Command Setup Time (measured in ns/1000) */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ rightOfPoint = (spdRawData[i] & 0x0f); -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ if(leftOfPoint > 7) -+ { -+ leftOfPoint *= -1; -+ } -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / 100; -+ rightOfPoint = time_tmp % 100; -+ } -+ mvOsOutput("Address And Command Setup Time [ns]: %d.%d\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 33: /* Address And Command Hold Time */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ rightOfPoint = (spdRawData[i] & 0x0f); -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ if(leftOfPoint > 7) -+ { -+ leftOfPoint *= -1; -+ } -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / 100; -+ rightOfPoint = time_tmp % 100; -+ } -+ mvOsOutput("Address And Command Hold Time [ns]: %d.%d\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 34: /* Data Input Setup Time */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ rightOfPoint = (spdRawData[i] & 0x0f); -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ if(leftOfPoint > 7) -+ { -+ leftOfPoint *= -1; -+ } -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / 100; -+ rightOfPoint = time_tmp % 100; -+ } -+ mvOsOutput("Data Input Setup Time [ns]: %d.%d\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 35: /* Data Input Hold Time */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ rightOfPoint = (spdRawData[i] & 0x0f); -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ if(leftOfPoint > 7) -+ { -+ leftOfPoint *= -1; -+ } -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / 100; -+ rightOfPoint = time_tmp % 100; -+ } -+ mvOsOutput("Data Input Hold Time [ns]: %d.%d\n\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 36: /* Relevant for DDR2 only: Write Recovery Time */ -+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> 2); -+ rightOfPoint = (spdRawData[i] & maskRightOfPoint) * 25; -+ mvOsOutput("Write Recovery Time [ns]: %d.%d\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ } -+ -+} -+ -+ -+/* -+ * translate ns.ns/10 coding of SPD timing values -+ * into ps unit values -+ */ -+/******************************************************************************* -+* cas2ps - Translate x.y ns parameter to pico-seconds values -+* -+* DESCRIPTION: -+* This function translates x.y nano seconds to its value in pico seconds. -+* For example 3.75ns will return 3750. -+* -+* INPUT: -+* spd_byte - DIMM SPD byte. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* value in pico seconds. -+* -+*******************************************************************************/ -+static MV_U32 cas2ps(MV_U8 spd_byte) -+{ -+ MV_U32 ns, ns10; -+ -+ /* isolate upper nibble */ -+ ns = (spd_byte >> 4) & 0x0F; -+ /* isolate lower nibble */ -+ ns10 = (spd_byte & 0x0F); -+ -+ if( ns10 < 10 ) { -+ ns10 *= 10; -+ } -+ else if( ns10 == 10 ) -+ ns10 = 25; -+ else if( ns10 == 11 ) -+ ns10 = 33; -+ else if( ns10 == 12 ) -+ ns10 = 66; -+ else if( ns10 == 13 ) -+ ns10 = 75; -+ else -+ { -+ mvOsOutput("cas2ps Err. unsupported cycle time.\n"); -+ } -+ -+ return (ns*1000 + ns10*10); -+} -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h 2010-11-09 20:28:11.032495447 +0100 -@@ -0,0 +1,192 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvDram -+#define __INCmvDram -+ -+#include "ddr2/mvDramIf.h" -+#include "twsi/mvTwsi.h" -+ -+#define MAX_DIMM_NUM 2 -+#define SPD_SIZE 128 -+ -+/* Dimm spd offsets */ -+#define DIMM_MEM_TYPE 2 -+#define DIMM_ROW_NUM 3 -+#define DIMM_COL_NUM 4 -+#define DIMM_MODULE_BANK_NUM 5 -+#define DIMM_DATA_WIDTH 6 -+#define DIMM_VOLT_IF 8 -+#define DIMM_MIN_CC_AT_MAX_CAS 9 -+#define DIMM_ERR_CHECK_TYPE 11 -+#define DIMM_REFRESH_INTERVAL 12 -+#define DIMM_SDRAM_WIDTH 13 -+#define DIMM_ERR_CHECK_DATA_WIDTH 14 -+#define DIMM_MIN_CLK_DEL 15 -+#define DIMM_BURST_LEN_SUP 16 -+#define DIMM_DEV_BANK_NUM 17 -+#define DIMM_SUP_CAL 18 -+#define DIMM_DDR2_TYPE_INFORMATION 20 /* DDR2 only */ -+#define DIMM_BUF_ADDR_CONT_IN 21 -+#define DIMM_MIN_CC_AT_MAX_CAS_MINUS1 23 -+#define DIMM_MIN_CC_AT_MAX_CAS_MINUS2 25 -+#define DIMM_MIN_ROW_PRECHARGE_TIME 27 -+#define DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE 28 -+#define DIMM_MIN_RAS_TO_CAS_DELAY 29 -+#define DIMM_MIN_RAS_PULSE_WIDTH 30 -+#define DIMM_BANK_DENSITY 31 -+#define DIMM_MIN_WRITE_RECOVERY_TIME 36 -+#define DIMM_MIN_WRITE_TO_READ_CMD_DELAY 37 -+#define DIMM_MIN_READ_TO_PRECH_CMD_DELAY 38 -+#define DIMM_MIN_REFRESH_TO_ACTIVATE_CMD 42 -+#define DIMM_SPD_VERSION 62 -+ -+/* Dimm Memory Type values */ -+#define DIMM_MEM_TYPE_SDRAM 0x4 -+#define DIMM_MEM_TYPE_DDR1 0x7 -+#define DIMM_MEM_TYPE_DDR2 0x8 -+ -+#define DIMM_MODULE_MANU_OFFS 64 -+#define DIMM_MODULE_MANU_SIZE 8 -+#define DIMM_MODULE_VEN_OFFS 73 -+#define DIMM_MODULE_VEN_SIZE 25 -+#define DIMM_MODULE_ID_OFFS 99 -+#define DIMM_MODULE_ID_SIZE 18 -+ -+/* enumeration for voltage levels. */ -+typedef enum _mvDimmVoltageIf -+{ -+ TTL_5V_TOLERANT, -+ LVTTL, -+ HSTL_1_5V, -+ SSTL_3_3V, -+ SSTL_2_5V, -+ VOLTAGE_UNKNOWN, -+} MV_DIMM_VOLTAGE_IF; -+ -+ -+/* enumaration for SDRAM CAS Latencies. */ -+typedef enum _mvDimmSdramCas -+{ -+ SD_CL_1 =1, -+ SD_CL_2, -+ SD_CL_3, -+ SD_CL_4, -+ SD_CL_5, -+ SD_CL_6, -+ SD_CL_7, -+ SD_FAULT -+}MV_DIMM_SDRAM_CAS; -+ -+ -+/* DIMM information structure */ -+typedef struct _mvDimmInfo -+{ -+ MV_MEMORY_TYPE memoryType; /* DDR or SDRAM */ -+ -+ MV_U8 spdRawData[SPD_SIZE]; /* Content of SPD-EEPROM copied 1:1 */ -+ -+ /* DIMM dimensions */ -+ MV_U32 numOfRowAddr; -+ MV_U32 numOfColAddr; -+ MV_U32 numOfModuleBanks; -+ MV_U32 dataWidth; -+ MV_U32 errorCheckType; /* ECC , PARITY..*/ -+ MV_U32 sdramWidth; /* 4,8,16 or 32 */ -+ MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ -+ MV_U32 burstLengthSupported; -+ MV_U32 numOfBanksOnEachDevice; -+ MV_U32 suportedCasLatencies; -+ MV_U32 refreshInterval; -+ MV_U32 dimmBankDensity; -+ MV_U32 dimmTypeInfo; /* DDR2 only */ -+ MV_U32 dimmAttributes; -+ -+ /* DIMM timing parameters */ -+ MV_U32 minCycleTimeAtMaxCasLatPs; -+ MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; -+ MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; -+ MV_U32 minRowPrechargeTime; -+ MV_U32 minRowActiveToRowActive; -+ MV_U32 minRasToCasDelay; -+ MV_U32 minRasPulseWidth; -+ MV_U32 minWriteRecoveryTime; /* DDR2 only */ -+ MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ -+ MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ -+ MV_U32 minRefreshToActiveCmd; /* DDR2 only */ -+ -+ /* Parameters calculated from the extracted DIMM information */ -+ MV_U32 size; /* 16,64,128,256 or 512 MByte in MB units */ -+ MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit in MB units */ -+ MV_U32 numberOfDevices; -+ -+} MV_DIMM_INFO; -+ -+ -+MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo); -+MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo); -+MV_VOID dimmSpdPrint(MV_U32 dimmNum); -+MV_STATUS dimmSpdCpy(MV_VOID); -+ -+#endif /* __INCmvDram */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEth.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEth.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEth.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEth.c 2010-11-09 20:28:11.042495489 +0100 -@@ -0,0 +1,2952 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+/******************************************************************************* -+* mvEth.c - Marvell's Gigabit Ethernet controller low level driver -+* -+* DESCRIPTION: -+* This file introduce OS independent APIs to Marvell's Gigabit Ethernet -+* controller. This Gigabit Ethernet Controller driver API controls -+* 1) Operations (i.e. port Init, Finish, Up, Down, PhyReset etc'). -+* 2) Data flow (i.e. port Send, Receive etc'). -+* 3) MAC Filtering functions (ethSetMcastAddr, ethSetRxFilterMode, etc.) -+* 4) MIB counters support (ethReadMibCounter) -+* 5) Debug functions (ethPortRegs, ethPortCounters, ethPortQueues, etc.) -+* Each Gigabit Ethernet port is controlled via ETH_PORT_CTRL struct. -+* This struct includes configuration information as well as driver -+* internal data needed for its operations. -+* -+* Supported Features: -+* - OS independent. All required OS services are implemented via external -+* OS dependent components (like osLayer or ethOsg) -+* - The user is free from Rx/Tx queue managing. -+* - Simple Gigabit Ethernet port operation API. -+* - Simple Gigabit Ethernet port data flow API. -+* - Data flow and operation API support per queue functionality. -+* - Support cached descriptors for better performance. -+* - PHY access and control API. -+* - Port Configuration API. -+* - Full control over Special and Other Multicast MAC tables. -+* -+*******************************************************************************/ -+/* includes */ -+#include "mvTypes.h" -+#include "mv802_3.h" -+#include "mvDebug.h" -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "eth-phy/mvEthPhy.h" -+#include "eth/mvEth.h" -+#include "eth/gbe/mvEthGbe.h" -+#include "cpu/mvCpu.h" -+ -+#ifdef INCLUDE_SYNC_BARR -+#include "sys/mvCpuIf.h" -+#endif -+ -+#ifdef MV_RT_DEBUG -+# define ETH_DEBUG -+#endif -+ -+ -+/* locals */ -+MV_BOOL ethDescInSram; -+MV_BOOL ethDescSwCoher; -+ -+/* This array holds the control structure of each port */ -+ETH_PORT_CTRL* ethPortCtrl[MV_ETH_MAX_PORTS]; -+ -+/* Ethernet Port Local routines */ -+ -+static void ethInitRxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue); -+ -+static void ethInitTxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue); -+ -+static void ethSetUcastTable(int portNo, int queue); -+ -+static MV_BOOL ethSetUcastAddr (int ethPortNum, MV_U8 lastNibble, int queue); -+static MV_BOOL ethSetSpecialMcastAddr(int ethPortNum, MV_U8 lastByte, int queue); -+static MV_BOOL ethSetOtherMcastAddr(int ethPortNum, MV_U8 crc8, int queue); -+ -+static void ethFreeDescrMemory(ETH_PORT_CTRL* pEthPortCtrl, MV_BUF_INFO* pDescBuf); -+static MV_U8* ethAllocDescrMemory(ETH_PORT_CTRL* pEthPortCtrl, int size, -+ MV_ULONG* pPhysAddr, MV_U32 *memHandle); -+ -+static MV_U32 mvEthMruGet(MV_U32 maxRxPktSize); -+ -+static void mvEthPortSgmiiConfig(int port); -+ -+ -+ -+/******************************************************************************/ -+/* EthDrv Initialization functions */ -+/******************************************************************************/ -+ -+/******************************************************************************* -+* mvEthHalInit - Initialize the Giga Ethernet unit -+* -+* DESCRIPTION: -+* This function initialize the Giga Ethernet unit. -+* 1) Configure Address decode windows of the unit -+* 2) Set registers to HW default values. -+* 3) Clear and Disable interrupts -+* -+* INPUT: NONE -+* -+* RETURN: NONE -+* -+* NOTE: this function is called once in the boot process. -+*******************************************************************************/ -+void mvEthHalInit(void) -+{ -+ int port; -+ -+ /* Init static data structures */ -+ for (port=0; port 0) -+ { -+ isSram = MV_TRUE; -+ #if (INTEG_SRAM_COHER == MV_CACHE_COHER_SW) -+ isSwCoher = MV_TRUE; -+ #else -+ isSwCoher = MV_FALSE; -+ #endif -+ } -+#endif /* ETH_DESCR_IN_SRAM */ -+ -+ if(pIsSram != NULL) -+ *pIsSram = isSram; -+ -+ if(pIsSwCoher != NULL) -+ *pIsSwCoher = isSwCoher; -+} -+ -+ -+ -+/******************************************************************************/ -+/* Port Initialization functions */ -+/******************************************************************************/ -+ -+/******************************************************************************* -+* mvEthPortInit - Initialize the Ethernet port driver -+* -+* DESCRIPTION: -+* This function initialize the ethernet port. -+* 1) Allocate and initialize internal port Control structure. -+* 2) Create RX and TX descriptor rings for default RX and TX queues -+* 3) Disable RX and TX operations, clear cause registers and -+* mask all interrupts. -+* 4) Set all registers to default values and clean all MAC tables. -+* -+* INPUT: -+* int portNo - Ethernet port number -+* ETH_PORT_INIT *pEthPortInit - Ethernet port init structure -+* -+* RETURN: -+* void* - ethernet port handler, that should be passed to the most other -+* functions dealing with this port. -+* -+* NOTE: This function is called once per port when loading the eth module. -+*******************************************************************************/ -+void* mvEthPortInit(int portNo, MV_ETH_PORT_INIT *pEthPortInit) -+{ -+ int queue, descSize; -+ ETH_PORT_CTRL* pPortCtrl; -+ -+ /* Check validity of parameters */ -+ if( (portNo >= (int)mvCtrlEthMaxPortGet()) || -+ (pEthPortInit->rxDefQ >= MV_ETH_RX_Q_NUM) || -+ (pEthPortInit->maxRxPktSize < 1518) ) -+ { -+ mvOsPrintf("EthPort #%d: Bad initialization parameters\n", portNo); -+ return NULL; -+ } -+ if( (pEthPortInit->rxDescrNum[pEthPortInit->rxDefQ]) == 0) -+ { -+ mvOsPrintf("EthPort #%d: rxDefQ (%d) must be created\n", -+ portNo, pEthPortInit->rxDefQ); -+ return NULL; -+ } -+ -+ pPortCtrl = (ETH_PORT_CTRL*)mvOsMalloc( sizeof(ETH_PORT_CTRL) ); -+ if(pPortCtrl == NULL) -+ { -+ mvOsPrintf("EthDrv: Can't allocate %dB for port #%d control structure!\n", -+ (int)sizeof(ETH_PORT_CTRL), portNo); -+ return NULL; -+ } -+ -+ memset(pPortCtrl, 0, sizeof(ETH_PORT_CTRL) ); -+ ethPortCtrl[portNo] = pPortCtrl; -+ -+ pPortCtrl->portState = MV_UNDEFINED_STATE; -+ -+ pPortCtrl->portNo = portNo; -+ -+ pPortCtrl->osHandle = pEthPortInit->osHandle; -+ -+ /* Copy Configuration parameters */ -+ pPortCtrl->portConfig.maxRxPktSize = pEthPortInit->maxRxPktSize; -+ pPortCtrl->portConfig.rxDefQ = pEthPortInit->rxDefQ; -+ pPortCtrl->portConfig.ejpMode = 0; -+ -+ for( queue=0; queuerxQueueConfig[queue].descrNum = pEthPortInit->rxDescrNum[queue]; -+ } -+ for( queue=0; queuetxQueueConfig[queue].descrNum = pEthPortInit->txDescrNum[queue]; -+ } -+ -+ mvEthPortDisable(pPortCtrl); -+ -+ /* Set the board information regarding PHY address */ -+ mvEthPhyAddrSet(pPortCtrl, mvBoardPhyAddrGet(portNo) ); -+ -+ /* Create all requested RX queues */ -+ for(queue=0; queuerxQueueConfig[queue].descrNum == 0) -+ continue; -+ -+ /* Allocate memory for RX descriptors */ -+ descSize = ((pPortCtrl->rxQueueConfig[queue].descrNum * ETH_RX_DESC_ALIGNED_SIZE) + -+ CPU_D_CACHE_LINE_SIZE); -+ -+ pPortCtrl->rxQueue[queue].descBuf.bufVirtPtr = -+ ethAllocDescrMemory(pPortCtrl, descSize, -+ &pPortCtrl->rxQueue[queue].descBuf.bufPhysAddr, -+ &pPortCtrl->rxQueue[queue].descBuf.memHandle); -+ pPortCtrl->rxQueue[queue].descBuf.bufSize = descSize; -+ if(pPortCtrl->rxQueue[queue].descBuf.bufVirtPtr == NULL) -+ { -+ mvOsPrintf("EthPort #%d, rxQ=%d: Can't allocate %d bytes in %s for %d RX descr\n", -+ pPortCtrl->portNo, queue, descSize, -+ ethDescInSram ? "SRAM" : "DRAM", -+ pPortCtrl->rxQueueConfig[queue].descrNum); -+ return NULL; -+ } -+ -+ ethInitRxDescRing(pPortCtrl, queue); -+ } -+ /* Create TX queues */ -+ for(queue=0; queuetxQueueConfig[queue].descrNum == 0) -+ continue; -+ -+ /* Allocate memory for TX descriptors */ -+ descSize = ((pPortCtrl->txQueueConfig[queue].descrNum * ETH_TX_DESC_ALIGNED_SIZE) + -+ CPU_D_CACHE_LINE_SIZE); -+ -+ pPortCtrl->txQueue[queue].descBuf.bufVirtPtr = -+ ethAllocDescrMemory(pPortCtrl, descSize, -+ &pPortCtrl->txQueue[queue].descBuf.bufPhysAddr, -+ &pPortCtrl->txQueue[queue].descBuf.memHandle); -+ pPortCtrl->txQueue[queue].descBuf.bufSize = descSize; -+ if(pPortCtrl->txQueue[queue].descBuf.bufVirtPtr == NULL) -+ { -+ mvOsPrintf("EthPort #%d, txQ=%d: Can't allocate %d bytes in %s for %d TX descr\n", -+ pPortCtrl->portNo, queue, descSize, ethDescInSram ? "SRAM" : "DRAM", -+ pPortCtrl->txQueueConfig[queue].descrNum); -+ return NULL; -+ } -+ -+ ethInitTxDescRing(pPortCtrl, queue); -+ } -+ mvEthDefaultsSet(pPortCtrl); -+ -+ pPortCtrl->portState = MV_IDLE; -+ return pPortCtrl; -+} -+ -+/******************************************************************************* -+* ethPortFinish - Finish the Ethernet port driver -+* -+* DESCRIPTION: -+* This function finish the ethernet port. -+* 1) Down ethernet port if needed. -+* 2) Delete RX and TX descriptor rings for all created RX and TX queues -+* 3) Free internal port Control structure. -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet port handler -+* -+* RETURN: NONE. -+* -+*******************************************************************************/ -+void mvEthPortFinish(void* pPortHndl) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ int queue, portNo = pPortCtrl->portNo; -+ -+ if(pPortCtrl->portState == MV_ACTIVE) -+ { -+ mvOsPrintf("ethPort #%d: Warning !!! Finish port in Active state\n", -+ portNo); -+ mvEthPortDisable(pPortHndl); -+ } -+ -+ /* Free all allocated RX queues */ -+ for(queue=0; queuerxQueue[queue].descBuf); -+ } -+ -+ /* Free all allocated TX queues */ -+ for(queue=0; queuetxQueue[queue].descBuf); -+ } -+ -+ /* Free port control structure */ -+ mvOsFree(pPortCtrl); -+ -+ ethPortCtrl[portNo] = NULL; -+} -+ -+/******************************************************************************* -+* mvEthDefaultsSet - Set defaults to the ethernet port -+* -+* DESCRIPTION: -+* This function set default values to the ethernet port. -+* 1) Clear Cause registers and Mask all interrupts -+* 2) Clear all MAC tables -+* 3) Set defaults to all registers -+* 4) Reset all created RX and TX descriptors ring -+* 5) Reset PHY -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet port handler -+* -+* RETURN: MV_STATUS -+* MV_OK - Success, Others - Failure -+* NOTE: -+* This function update all the port configuration except those set -+* Initialy by the OsGlue by MV_ETH_PORT_INIT. -+* This function can be called after portDown to return the port setting -+* to defaults. -+*******************************************************************************/ -+MV_STATUS mvEthDefaultsSet(void* pPortHndl) -+{ -+ int ethPortNo, queue; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ MV_U32 txPrio; -+ MV_U32 portCfgReg, portCfgExtReg, portSerialCtrlReg, portSerialCtrl1Reg, portSdmaCfgReg; -+ MV_BOARD_MAC_SPEED boardMacCfg; -+ -+ ethPortNo = pPortCtrl->portNo; -+ -+ /* Clear Cause registers */ -+ MV_REG_WRITE(ETH_INTR_CAUSE_REG(ethPortNo),0); -+ MV_REG_WRITE(ETH_INTR_CAUSE_EXT_REG(ethPortNo),0); -+ -+ /* Mask all interrupts */ -+ MV_REG_WRITE(ETH_INTR_MASK_REG(ethPortNo),0); -+ MV_REG_WRITE(ETH_INTR_MASK_EXT_REG(ethPortNo),0); -+ -+ portCfgReg = PORT_CONFIG_VALUE; -+ portCfgExtReg = PORT_CONFIG_EXTEND_VALUE; -+ -+ boardMacCfg = mvBoardMacSpeedGet(ethPortNo); -+ -+ if(boardMacCfg == BOARD_MAC_SPEED_100M) -+ { -+ portSerialCtrlReg = PORT_SERIAL_CONTROL_100MB_FORCE_VALUE; -+ } -+ else if(boardMacCfg == BOARD_MAC_SPEED_1000M) -+ { -+ portSerialCtrlReg = PORT_SERIAL_CONTROL_1000MB_FORCE_VALUE; -+ } -+ else -+ { -+ portSerialCtrlReg = PORT_SERIAL_CONTROL_VALUE; -+ } -+ -+ /* build PORT_SDMA_CONFIG_REG */ -+ portSdmaCfgReg = ETH_TX_INTR_COAL_MASK(0); -+ portSdmaCfgReg |= ETH_TX_BURST_SIZE_MASK(ETH_BURST_SIZE_16_64BIT_VALUE); -+ -+#if ( (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WB) || \ -+ (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WT) ) -+ /* some devices have restricted RX burst size when using HW coherency */ -+ portSdmaCfgReg |= ETH_RX_BURST_SIZE_MASK(ETH_BURST_SIZE_4_64BIT_VALUE); -+#else -+ portSdmaCfgReg |= ETH_RX_BURST_SIZE_MASK(ETH_BURST_SIZE_16_64BIT_VALUE); -+#endif -+ -+#if defined(MV_CPU_BE) -+ /* big endian */ -+# if defined(MV_ARM) -+ portSdmaCfgReg |= (ETH_RX_NO_DATA_SWAP_MASK | -+ ETH_TX_NO_DATA_SWAP_MASK | -+ ETH_DESC_SWAP_MASK); -+# elif defined(MV_PPC) -+ portSdmaCfgReg |= (ETH_RX_DATA_SWAP_MASK | -+ ETH_TX_DATA_SWAP_MASK | -+ ETH_NO_DESC_SWAP_MASK); -+# else -+# error "Giga Ethernet Swap policy is not defined for the CPU_ARCH" -+# endif /* MV_ARM / MV_PPC */ -+ -+#else /* MV_CPU_LE */ -+ /* little endian */ -+ portSdmaCfgReg |= (ETH_RX_NO_DATA_SWAP_MASK | -+ ETH_TX_NO_DATA_SWAP_MASK | -+ ETH_NO_DESC_SWAP_MASK); -+#endif /* MV_CPU_BE / MV_CPU_LE */ -+ -+ pPortCtrl->portRxQueueCmdReg = 0; -+ pPortCtrl->portTxQueueCmdReg = 0; -+ -+#if (MV_ETH_VERSION >= 4) -+ if(pPortCtrl->portConfig.ejpMode == MV_TRUE) -+ { -+ MV_REG_WRITE(ETH_TXQ_CMD_1_REG(ethPortNo), ETH_TX_EJP_ENABLE_MASK); -+ } -+ else -+ { -+ MV_REG_WRITE(ETH_TXQ_CMD_1_REG(ethPortNo), 0) -+ } -+#endif /* (MV_ETH_VERSION >= 4) */ -+ -+ ethSetUcastTable(ethPortNo, -1); -+ mvEthSetSpecialMcastTable(ethPortNo, -1); -+ mvEthSetOtherMcastTable(ethPortNo, -1); -+ -+ portSerialCtrlReg &= ~ETH_MAX_RX_PACKET_SIZE_MASK; -+ -+ portSerialCtrlReg |= mvEthMruGet(pPortCtrl->portConfig.maxRxPktSize); -+ -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNo), portSerialCtrlReg); -+ -+ /* Update value of PortConfig register accordingly with all RxQueue types */ -+ pPortCtrl->portConfig.rxArpQ = pPortCtrl->portConfig.rxDefQ; -+ pPortCtrl->portConfig.rxBpduQ = pPortCtrl->portConfig.rxDefQ; -+ pPortCtrl->portConfig.rxTcpQ = pPortCtrl->portConfig.rxDefQ; -+ pPortCtrl->portConfig.rxUdpQ = pPortCtrl->portConfig.rxDefQ; -+ -+ portCfgReg &= ~ETH_DEF_RX_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_QUEUE_MASK(pPortCtrl->portConfig.rxDefQ); -+ -+ portCfgReg &= ~ETH_DEF_RX_ARP_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_ARP_QUEUE_MASK(pPortCtrl->portConfig.rxArpQ); -+ -+ portCfgReg &= ~ETH_DEF_RX_BPDU_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_BPDU_QUEUE_MASK(pPortCtrl->portConfig.rxBpduQ); -+ -+ portCfgReg &= ~ETH_DEF_RX_TCP_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_TCP_QUEUE_MASK(pPortCtrl->portConfig.rxTcpQ); -+ -+ portCfgReg &= ~ETH_DEF_RX_UDP_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_UDP_QUEUE_MASK(pPortCtrl->portConfig.rxUdpQ); -+ -+ /* Assignment of Tx CTRP of given queue */ -+ txPrio = 0; -+ -+ for(queue=0; queuetxQueue[queue]; -+ -+ if(pQueueCtrl->pFirstDescr != NULL) -+ { -+ ethResetTxDescRing(pPortCtrl, queue); -+ -+ MV_REG_WRITE(ETH_TXQ_TOKEN_COUNT_REG(ethPortNo, queue), -+ 0x3fffffff); -+ MV_REG_WRITE(ETH_TXQ_TOKEN_CFG_REG(ethPortNo, queue), -+ 0x03ffffff); -+ } -+ else -+ { -+ MV_REG_WRITE(ETH_TXQ_TOKEN_COUNT_REG(ethPortNo, queue), 0x0); -+ MV_REG_WRITE(ETH_TXQ_TOKEN_CFG_REG(ethPortNo, queue), 0x0); -+ } -+ } -+ -+ /* Assignment of Rx CRDP of given queue */ -+ for(queue=0; queueportNo; -+ -+ if( (pPortCtrl->portState != MV_ACTIVE) && -+ (pPortCtrl->portState != MV_PAUSED) ) -+ { -+ mvOsPrintf("ethDrv port%d: Unexpected port state %d\n", -+ ethPortNo, pPortCtrl->portState); -+ return MV_BAD_STATE; -+ } -+ -+ ethPortNo = pPortCtrl->portNo; -+ -+ /* Enable port RX. */ -+ MV_REG_WRITE(ETH_RX_QUEUE_COMMAND_REG(ethPortNo), pPortCtrl->portRxQueueCmdReg); -+ -+ /* Enable port TX. */ -+ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(ethPortNo)) = pPortCtrl->portTxQueueCmdReg; -+ -+ pPortCtrl->portState = MV_ACTIVE; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* ethPortDown - Stop the Ethernet port activity. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet port handler -+* -+* RETURN: MV_STATUS -+* MV_OK - Success, Others - Failure. -+* -+* NOTE : used for port link down. -+*******************************************************************************/ -+MV_STATUS mvEthPortDown(void* pEthPortHndl) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ int ethPortNum = pPortCtrl->portNo; -+ unsigned int regData; -+ volatile int uDelay, mDelay; -+ -+ /* Stop Rx port activity. Check port Rx activity. */ -+ regData = (MV_REG_READ(ETH_RX_QUEUE_COMMAND_REG(ethPortNum))) & ETH_RXQ_ENABLE_MASK; -+ if(regData != 0) -+ { -+ /* Issue stop command for active channels only */ -+ MV_REG_WRITE(ETH_RX_QUEUE_COMMAND_REG(ethPortNum), (regData << ETH_RXQ_DISABLE_OFFSET)); -+ } -+ -+ /* Stop Tx port activity. Check port Tx activity. */ -+ regData = (MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(ethPortNum))) & ETH_TXQ_ENABLE_MASK; -+ if(regData != 0) -+ { -+ /* Issue stop command for active channels only */ -+ MV_REG_WRITE(ETH_TX_QUEUE_COMMAND_REG(ethPortNum), -+ (regData << ETH_TXQ_DISABLE_OFFSET) ); -+ } -+ -+ /* Force link down */ -+/* -+ regData = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNum)); -+ regData &= ~(ETH_DO_NOT_FORCE_LINK_FAIL_MASK); -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNum), regData); -+*/ -+ /* Wait for all Rx activity to terminate. */ -+ mDelay = 0; -+ do -+ { -+ if(mDelay >= RX_DISABLE_TIMEOUT_MSEC) -+ { -+ mvOsPrintf("ethPort_%d: TIMEOUT for RX stopped !!! rxQueueCmd - 0x08%x\n", -+ ethPortNum, regData); -+ break; -+ } -+ mvOsDelay(1); -+ mDelay++; -+ -+ /* Check port RX Command register that all Rx queues are stopped */ -+ regData = MV_REG_READ(ETH_RX_QUEUE_COMMAND_REG(ethPortNum)); -+ } -+ while(regData & 0xFF); -+ -+ /* Wait for all Tx activity to terminate. */ -+ mDelay = 0; -+ do -+ { -+ if(mDelay >= TX_DISABLE_TIMEOUT_MSEC) -+ { -+ mvOsPrintf("ethPort_%d: TIMEOUT for TX stoped !!! txQueueCmd - 0x08%x\n", -+ ethPortNum, regData); -+ break; -+ } -+ mvOsDelay(1); -+ mDelay++; -+ -+ /* Check port TX Command register that all Tx queues are stopped */ -+ regData = MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(ethPortNum)); -+ } -+ while(regData & 0xFF); -+ -+ /* Double check to Verify that TX FIFO is Empty */ -+ mDelay = 0; -+ while(MV_TRUE) -+ { -+ do -+ { -+ if(mDelay >= TX_FIFO_EMPTY_TIMEOUT_MSEC) -+ { -+ mvOsPrintf("\n ethPort_%d: TIMEOUT for TX FIFO empty !!! portStatus - 0x08%x\n", -+ ethPortNum, regData); -+ break; -+ } -+ mvOsDelay(1); -+ mDelay++; -+ -+ regData = MV_REG_READ(ETH_PORT_STATUS_REG(ethPortNum)); -+ } -+ while( ((regData & ETH_TX_FIFO_EMPTY_MASK) == 0) || -+ ((regData & ETH_TX_IN_PROGRESS_MASK) != 0) ); -+ -+ if(mDelay >= TX_FIFO_EMPTY_TIMEOUT_MSEC) -+ break; -+ -+ /* Double check */ -+ regData = MV_REG_READ(ETH_PORT_STATUS_REG(ethPortNum)); -+ if( ((regData & ETH_TX_FIFO_EMPTY_MASK) != 0) && -+ ((regData & ETH_TX_IN_PROGRESS_MASK) == 0) ) -+ { -+ break; -+ } -+ else -+ mvOsPrintf("ethPort_%d: TX FIFO Empty double check failed. %d msec, portStatus=0x%x\n", -+ ethPortNum, mDelay, regData); -+ } -+ -+ /* Do NOT force link down */ -+/* -+ regData = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNum)); -+ regData |= (ETH_DO_NOT_FORCE_LINK_FAIL_MASK); -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNum), regData); -+*/ -+ /* Wait about 2500 tclk cycles */ -+ uDelay = (PORT_DISABLE_WAIT_TCLOCKS/(mvBoardTclkGet()/1000000)); -+ mvOsUDelay(uDelay); -+ -+ pPortCtrl->portState = MV_PAUSED; -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* ethPortEnable - Enable the Ethernet port and Start RX and TX. -+* -+* DESCRIPTION: -+* This routine enable the Ethernet port and Rx and Tx activity: -+* -+* Note: Each Rx and Tx queue descriptor's list must be initialized prior -+* to calling this function (use etherInitTxDescRing for Tx queues and -+* etherInitRxDescRing for Rx queues). -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet port handler -+* -+* RETURN: MV_STATUS -+* MV_OK - Success, Others - Failure. -+* -+* NOTE: main usage is to enable the port after ifconfig up. -+*******************************************************************************/ -+MV_STATUS mvEthPortEnable(void* pEthPortHndl) -+{ -+ int ethPortNo; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ MV_U32 portSerialCtrlReg; -+ -+ ethPortNo = pPortCtrl->portNo; -+ -+ /* Enable port */ -+ portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNo)); -+ portSerialCtrlReg |= (ETH_DO_NOT_FORCE_LINK_FAIL_MASK | ETH_PORT_ENABLE_MASK); -+ -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNo), portSerialCtrlReg); -+ -+ mvEthMibCountersClear(pEthPortHndl); -+ -+ pPortCtrl->portState = MV_PAUSED; -+ -+ /* If Link is UP, Start RX and TX traffic */ -+ if( MV_REG_READ( ETH_PORT_STATUS_REG(ethPortNo) ) & ETH_LINK_UP_MASK) -+ return( mvEthPortUp(pEthPortHndl) ); -+ -+ return MV_NOT_READY; -+} -+ -+ -+/******************************************************************************* -+* mvEthPortDisable - Stop RX and TX activities and Disable the Ethernet port. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet port handler -+* -+* RETURN: MV_STATUS -+* MV_OK - Success, Others - Failure. -+* -+* NOTE: main usage is to disable the port after ifconfig down. -+*******************************************************************************/ -+MV_STATUS mvEthPortDisable(void* pEthPortHndl) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ int ethPortNum = pPortCtrl->portNo; -+ unsigned int regData; -+ volatile int mvDelay; -+ -+ if(pPortCtrl->portState == MV_ACTIVE) -+ { -+ /* Stop RX and TX activities */ -+ mvEthPortDown(pEthPortHndl); -+ } -+ -+ /* Reset the Enable bit in the Serial Control Register */ -+ regData = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNum)); -+ regData &= ~(ETH_PORT_ENABLE_MASK); -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNum), regData); -+ -+ /* Wait about 2500 tclk cycles */ -+ mvDelay = (PORT_DISABLE_WAIT_TCLOCKS*(mvCpuPclkGet()/mvBoardTclkGet())); -+ for(mvDelay; mvDelay>0; mvDelay--); -+ -+ pPortCtrl->portState = MV_IDLE; -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthPortForceTxDone - Get next buffer from TX queue in spite of buffer ownership. -+* -+* DESCRIPTION: -+* This routine used to free buffers attached to the Tx ring and should -+* be called only when Giga Ethernet port is Down -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet Port handler. -+* int txQueue - Number of TX queue. -+* -+* OUTPUT: -+* MV_PKT_INFO *pPktInfo - Pointer to packet was sent. -+* -+* RETURN: -+* MV_EMPTY - There is no more buffers in this queue. -+* MV_OK - Buffer detached from the queue and pPktInfo structure -+* filled with relevant information. -+* -+*******************************************************************************/ -+MV_PKT_INFO* mvEthPortForceTxDone(void* pEthPortHndl, int txQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ MV_PKT_INFO* pPktInfo; -+ ETH_TX_DESC* pTxDesc; -+ int port = pPortCtrl->portNo; -+ -+ pQueueCtrl = &pPortCtrl->txQueue[txQueue]; -+ -+ while( (pQueueCtrl->pUsedDescr != pQueueCtrl->pCurrentDescr) || -+ (pQueueCtrl->resource == 0) ) -+ { -+ /* Free next descriptor */ -+ pQueueCtrl->resource++; -+ pTxDesc = (ETH_TX_DESC*)pQueueCtrl->pUsedDescr; -+ -+ /* pPktInfo is available only in descriptors which are last descriptors */ -+ pPktInfo = (MV_PKT_INFO*)pTxDesc->returnInfo; -+ if (pPktInfo) -+ pPktInfo->status = pTxDesc->cmdSts; -+ -+ pTxDesc->cmdSts = 0x0; -+ pTxDesc->returnInfo = 0x0; -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxDesc); -+ -+ pQueueCtrl->pUsedDescr = TX_NEXT_DESC_PTR(pTxDesc, pQueueCtrl); -+ -+ if (pPktInfo) -+ if (pPktInfo->status & ETH_TX_LAST_DESC_MASK) -+ return pPktInfo; -+ } -+ MV_REG_WRITE( ETH_TX_CUR_DESC_PTR_REG(port, txQueue), -+ (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); -+ return NULL; -+} -+ -+ -+ -+/******************************************************************************* -+* mvEthPortForceRx - Get next buffer from RX queue in spite of buffer ownership. -+* -+* DESCRIPTION: -+* This routine used to free buffers attached to the Rx ring and should -+* be called only when Giga Ethernet port is Down -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet Port handler. -+* int rxQueue - Number of Rx queue. -+* -+* OUTPUT: -+* MV_PKT_INFO *pPktInfo - Pointer to received packet. -+* -+* RETURN: -+* MV_EMPTY - There is no more buffers in this queue. -+* MV_OK - Buffer detached from the queue and pBufInfo structure -+* filled with relevant information. -+* -+*******************************************************************************/ -+MV_PKT_INFO* mvEthPortForceRx(void* pEthPortHndl, int rxQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ ETH_RX_DESC* pRxDesc; -+ MV_PKT_INFO* pPktInfo; -+ int port = pPortCtrl->portNo; -+ -+ pQueueCtrl = &pPortCtrl->rxQueue[rxQueue]; -+ -+ if(pQueueCtrl->resource == 0) -+ { -+ MV_REG_WRITE( ETH_RX_CUR_DESC_PTR_REG(port, rxQueue), -+ (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); -+ -+ return NULL; -+ } -+ /* Free next descriptor */ -+ pQueueCtrl->resource--; -+ pRxDesc = (ETH_RX_DESC*)pQueueCtrl->pCurrentDescr; -+ pPktInfo = (MV_PKT_INFO*)pRxDesc->returnInfo; -+ -+ pPktInfo->status = pRxDesc->cmdSts; -+ pRxDesc->cmdSts = 0x0; -+ pRxDesc->returnInfo = 0x0; -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxDesc); -+ -+ pQueueCtrl->pCurrentDescr = RX_NEXT_DESC_PTR(pRxDesc, pQueueCtrl); -+ return pPktInfo; -+} -+ -+ -+/******************************************************************************/ -+/* Port Configuration functions */ -+/******************************************************************************/ -+/******************************************************************************* -+* mvEthMruGet - Get MRU configuration for Max Rx packet size. -+* -+* INPUT: -+* MV_U32 maxRxPktSize - max packet size. -+* -+* RETURN: MV_U32 - MRU configuration. -+* -+*******************************************************************************/ -+static MV_U32 mvEthMruGet(MV_U32 maxRxPktSize) -+{ -+ MV_U32 portSerialCtrlReg = 0; -+ -+ if(maxRxPktSize > 9192) -+ portSerialCtrlReg |= ETH_MAX_RX_PACKET_9700BYTE; -+ else if(maxRxPktSize > 9022) -+ portSerialCtrlReg |= ETH_MAX_RX_PACKET_9192BYTE; -+ else if(maxRxPktSize > 1552) -+ portSerialCtrlReg |= ETH_MAX_RX_PACKET_9022BYTE; -+ else if(maxRxPktSize > 1522) -+ portSerialCtrlReg |= ETH_MAX_RX_PACKET_1552BYTE; -+ else if(maxRxPktSize > 1518) -+ portSerialCtrlReg |= ETH_MAX_RX_PACKET_1522BYTE; -+ else -+ portSerialCtrlReg |= ETH_MAX_RX_PACKET_1518BYTE; -+ -+ return portSerialCtrlReg; -+} -+ -+/******************************************************************************* -+* mvEthRxCoalSet - Sets coalescing interrupt mechanism on RX path -+* -+* DESCRIPTION: -+* This routine sets the RX coalescing interrupt mechanism parameter. -+* This parameter is a timeout counter, that counts in 64 tClk -+* chunks, that when timeout event occurs a maskable interrupt occurs. -+* The parameter is calculated using the tCLK frequency of the -+* MV-64xxx chip, and the required number is in micro seconds. -+* -+* INPUT: -+* void* pPortHndl - Ethernet Port handler. -+* MV_U32 uSec - Number of micro seconds between -+* RX interrupts -+* -+* RETURN: -+* None. -+* -+* COMMENT: -+* 1 sec - TCLK_RATE clocks -+* 1 uSec - TCLK_RATE / 1,000,000 clocks -+* -+* Register Value for N micro seconds - ((N * ( (TCLK_RATE / 1,000,000)) / 64) -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_U32 mvEthRxCoalSet (void* pPortHndl, MV_U32 uSec) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ MV_U32 coal = ((uSec * (mvBoardTclkGet() / 1000000)) / 64); -+ MV_U32 portSdmaCfgReg; -+ -+ portSdmaCfgReg = MV_REG_READ(ETH_SDMA_CONFIG_REG(pPortCtrl->portNo)); -+ portSdmaCfgReg &= ~ETH_RX_INTR_COAL_ALL_MASK; -+ -+ portSdmaCfgReg |= ETH_RX_INTR_COAL_MASK(coal); -+ -+#if (MV_ETH_VERSION >= 2) -+ /* Set additional bit if needed ETH_RX_INTR_COAL_MSB_BIT (25) */ -+ if(ETH_RX_INTR_COAL_MASK(coal) > ETH_RX_INTR_COAL_ALL_MASK) -+ portSdmaCfgReg |= ETH_RX_INTR_COAL_MSB_MASK; -+#endif /* MV_ETH_VERSION >= 2 */ -+ -+ MV_REG_WRITE (ETH_SDMA_CONFIG_REG(pPortCtrl->portNo), portSdmaCfgReg); -+ return coal; -+} -+ -+/******************************************************************************* -+* mvEthTxCoalSet - Sets coalescing interrupt mechanism on TX path -+* -+* DESCRIPTION: -+* This routine sets the TX coalescing interrupt mechanism parameter. -+* This parameter is a timeout counter, that counts in 64 tClk -+* chunks, that when timeout event occurs a maskable interrupt -+* occurs. -+* The parameter is calculated using the tCLK frequency of the -+* MV-64xxx chip, and the required number is in micro seconds. -+* -+* INPUT: -+* void* pPortHndl - Ethernet Port handler. -+* MV_U32 uSec - Number of micro seconds between -+* RX interrupts -+* -+* RETURN: -+* None. -+* -+* COMMENT: -+* 1 sec - TCLK_RATE clocks -+* 1 uSec - TCLK_RATE / 1,000,000 clocks -+* -+* Register Value for N micro seconds - ((N * ( (TCLK_RATE / 1,000,000)) / 64) -+* -+*******************************************************************************/ -+MV_U32 mvEthTxCoalSet(void* pPortHndl, MV_U32 uSec) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ MV_U32 coal = ((uSec * (mvBoardTclkGet() / 1000000)) / 64); -+ MV_U32 regVal; -+ -+ regVal = MV_REG_READ(ETH_TX_FIFO_URGENT_THRESH_REG(pPortCtrl->portNo)); -+ regVal &= ~ETH_TX_INTR_COAL_ALL_MASK; -+ regVal |= ETH_TX_INTR_COAL_MASK(coal); -+ -+ /* Set TX Coalescing mechanism */ -+ MV_REG_WRITE (ETH_TX_FIFO_URGENT_THRESH_REG(pPortCtrl->portNo), regVal); -+ return coal; -+} -+ -+/******************************************************************************* -+* mvEthCoalGet - Gets RX and TX coalescing values in micro seconds -+* -+* DESCRIPTION: -+* This routine gets the RX and TX coalescing interrupt values. -+* The parameter is calculated using the tCLK frequency of the -+* MV-64xxx chip, and the returned numbers are in micro seconds. -+* -+* INPUTs: -+* void* pPortHndl - Ethernet Port handler. -+* -+* OUTPUTs: -+* MV_U32* pRxCoal - Number of micro seconds between RX interrupts -+* MV_U32* pTxCoal - Number of micro seconds between TX interrupts -+* -+* RETURN: -+* MV_STATUS MV_OK - success -+* Others - failure. -+* -+* COMMENT: -+* 1 sec - TCLK_RATE clocks -+* 1 uSec - TCLK_RATE / 1,000,000 clocks -+* -+* Register Value for N micro seconds - ((N * ( (TCLK_RATE / 1,000,000)) / 64) -+* -+*******************************************************************************/ -+MV_STATUS mvEthCoalGet(void* pPortHndl, MV_U32* pRxCoal, MV_U32* pTxCoal) -+{ -+ MV_U32 regVal, coal, usec; -+ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ -+ /* get TX Coalescing */ -+ regVal = MV_REG_READ (ETH_TX_FIFO_URGENT_THRESH_REG(pPortCtrl->portNo)); -+ coal = ((regVal & ETH_TX_INTR_COAL_ALL_MASK) >> ETH_TX_INTR_COAL_OFFSET); -+ -+ usec = (coal * 64) / (mvBoardTclkGet() / 1000000); -+ if(pTxCoal != NULL) -+ *pTxCoal = usec; -+ -+ /* Get RX Coalescing */ -+ regVal = MV_REG_READ(ETH_SDMA_CONFIG_REG(pPortCtrl->portNo)); -+ coal = ((regVal & ETH_RX_INTR_COAL_ALL_MASK) >> ETH_RX_INTR_COAL_OFFSET); -+ -+#if (MV_ETH_VERSION >= 2) -+ if(regVal & ETH_RX_INTR_COAL_MSB_MASK) -+ { -+ /* Add MSB */ -+ coal |= (ETH_RX_INTR_COAL_ALL_MASK + 1); -+ } -+#endif /* MV_ETH_VERSION >= 2 */ -+ -+ usec = (coal * 64) / (mvBoardTclkGet() / 1000000); -+ if(pRxCoal != NULL) -+ *pRxCoal = usec; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthMaxRxSizeSet - -+* -+* DESCRIPTION: -+* Change maximum receive size of the port. This configuration will take place -+* after next call of ethPortSetDefaults() function. -+* -+* INPUT: -+* -+* RETURN: -+*******************************************************************************/ -+MV_STATUS mvEthMaxRxSizeSet(void* pPortHndl, int maxRxSize) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ MV_U32 portSerialCtrlReg; -+ -+ if((maxRxSize < 1518) || (maxRxSize & ~ETH_RX_BUFFER_MASK)) -+ return MV_BAD_PARAM; -+ -+ pPortCtrl->portConfig.maxRxPktSize = maxRxSize; -+ -+ portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(pPortCtrl->portNo)); -+ portSerialCtrlReg &= ~ETH_MAX_RX_PACKET_SIZE_MASK; -+ portSerialCtrlReg |= mvEthMruGet(pPortCtrl->portConfig.maxRxPktSize); -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(pPortCtrl->portNo), portSerialCtrlReg); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************/ -+/* MAC Filtering functions */ -+/******************************************************************************/ -+ -+/******************************************************************************* -+* mvEthRxFilterModeSet - Configure Fitering mode of Ethernet port -+* -+* DESCRIPTION: -+* This routine used to free buffers attached to the Rx ring and should -+* be called only when Giga Ethernet port is Down -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet Port handler. -+* MV_BOOL isPromisc - Promiscous mode -+* MV_TRUE - accept all Broadcast, Multicast -+* and Unicast packets -+* MV_FALSE - accept all Broadcast, -+* specially added Multicast and -+* single Unicast packets -+* -+* RETURN: MV_STATUS MV_OK - Success, Other - Failure -+* -+*******************************************************************************/ -+MV_STATUS mvEthRxFilterModeSet(void* pEthPortHndl, MV_BOOL isPromisc) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ int queue; -+ MV_U32 portCfgReg; -+ -+ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); -+ /* Set / Clear UPM bit in port configuration register */ -+ if(isPromisc) -+ { -+ /* Accept all multicast packets to RX default queue */ -+ queue = pPortCtrl->portConfig.rxDefQ; -+ portCfgReg |= ETH_UNICAST_PROMISCUOUS_MODE_MASK; -+ memset(pPortCtrl->mcastCount, 1, sizeof(pPortCtrl->mcastCount)); -+ MV_REG_WRITE(ETH_MAC_ADDR_LOW_REG(pPortCtrl->portNo),0xFFFF); -+ MV_REG_WRITE(ETH_MAC_ADDR_HIGH_REG(pPortCtrl->portNo),0xFFFFFFFF); -+ } -+ else -+ { -+ /* Reject all Multicast addresses */ -+ queue = -1; -+ portCfgReg &= ~ETH_UNICAST_PROMISCUOUS_MODE_MASK; -+ /* Clear all mcastCount */ -+ memset(pPortCtrl->mcastCount, 0, sizeof(pPortCtrl->mcastCount)); -+ } -+ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); -+ -+ /* Set Special Multicast and Other Multicast tables */ -+ mvEthSetSpecialMcastTable(pPortCtrl->portNo, queue); -+ mvEthSetOtherMcastTable(pPortCtrl->portNo, queue); -+ ethSetUcastTable(pPortCtrl->portNo, queue); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthMacAddrSet - This function Set the port Unicast address. -+* -+* DESCRIPTION: -+* This function Set the port Ethernet MAC address. This address -+* will be used to send Pause frames if enabled. Packets with this -+* address will be accepted and dispatched to default RX queue -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet port handler. -+* char* pAddr - Address to be set -+* -+* RETURN: MV_STATUS -+* MV_OK - Success, Other - Faulure -+* -+*******************************************************************************/ -+MV_STATUS mvEthMacAddrSet(void* pPortHndl, unsigned char *pAddr, int queue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ unsigned int macH; -+ unsigned int macL; -+ -+ if(queue >= MV_ETH_RX_Q_NUM) -+ { -+ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", queue); -+ return MV_BAD_PARAM; -+ } -+ -+ if(queue != -1) -+ { -+ macL = (pAddr[4] << 8) | (pAddr[5]); -+ macH = (pAddr[0] << 24)| (pAddr[1] << 16) | -+ (pAddr[2] << 8) | (pAddr[3] << 0); -+ -+ MV_REG_WRITE(ETH_MAC_ADDR_LOW_REG(pPortCtrl->portNo), macL); -+ MV_REG_WRITE(ETH_MAC_ADDR_HIGH_REG(pPortCtrl->portNo), macH); -+ } -+ -+ /* Accept frames of this address */ -+ ethSetUcastAddr(pPortCtrl->portNo, pAddr[5], queue); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthMacAddrGet - This function returns the port Unicast address. -+* -+* DESCRIPTION: -+* This function returns the port Ethernet MAC address. -+* -+* INPUT: -+* int portNo - Ethernet port number. -+* char* pAddr - Pointer where address will be written to -+* -+* RETURN: MV_STATUS -+* MV_OK - Success, Other - Faulure -+* -+*******************************************************************************/ -+MV_STATUS mvEthMacAddrGet(int portNo, unsigned char *pAddr) -+{ -+ unsigned int macH; -+ unsigned int macL; -+ -+ if(pAddr == NULL) -+ { -+ mvOsPrintf("mvEthMacAddrGet: NULL pointer.\n"); -+ return MV_BAD_PARAM; -+ } -+ -+ macH = MV_REG_READ(ETH_MAC_ADDR_HIGH_REG(portNo)); -+ macL = MV_REG_READ(ETH_MAC_ADDR_LOW_REG(portNo)); -+ pAddr[0] = (macH >> 24) & 0xff; -+ pAddr[1] = (macH >> 16) & 0xff; -+ pAddr[2] = (macH >> 8) & 0xff; -+ pAddr[3] = macH & 0xff; -+ pAddr[4] = (macL >> 8) & 0xff; -+ pAddr[5] = macL & 0xff; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthMcastCrc8Get - Calculate CRC8 of MAC address. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* MV_U8* pAddr - Address to calculate CRC-8 -+* -+* RETURN: MV_U8 - CRC-8 of this MAC address -+* -+*******************************************************************************/ -+MV_U8 mvEthMcastCrc8Get(MV_U8* pAddr) -+{ -+ unsigned int macH; -+ unsigned int macL; -+ int macArray[48]; -+ int crc[8]; -+ int i; -+ unsigned char crcResult = 0; -+ -+ /* Calculate CRC-8 out of the given address */ -+ macH = (pAddr[0] << 8) | (pAddr[1]); -+ macL = (pAddr[2] << 24)| (pAddr[3] << 16) | -+ (pAddr[4] << 8) | (pAddr[5] << 0); -+ -+ for(i=0; i<32; i++) -+ macArray[i] = (macL >> i) & 0x1; -+ -+ for(i=32; i<48; i++) -+ macArray[i] = (macH >> (i - 32)) & 0x1; -+ -+ crc[0] = macArray[45] ^ macArray[43] ^ macArray[40] ^ macArray[39] ^ -+ macArray[35] ^ macArray[34] ^ macArray[31] ^ macArray[30] ^ -+ macArray[28] ^ macArray[23] ^ macArray[21] ^ macArray[19] ^ -+ macArray[18] ^ macArray[16] ^ macArray[14] ^ macArray[12] ^ -+ macArray[8] ^ macArray[7] ^ macArray[6] ^ macArray[0]; -+ -+ crc[1] = macArray[46] ^ macArray[45] ^ macArray[44] ^ macArray[43] ^ -+ macArray[41] ^ macArray[39] ^ macArray[36] ^ macArray[34] ^ -+ macArray[32] ^ macArray[30] ^ macArray[29] ^ macArray[28] ^ -+ macArray[24] ^ macArray[23] ^ macArray[22] ^ macArray[21] ^ -+ macArray[20] ^ macArray[18] ^ macArray[17] ^ macArray[16] ^ -+ macArray[15] ^ macArray[14] ^ macArray[13] ^ macArray[12] ^ -+ macArray[9] ^ macArray[6] ^ macArray[1] ^ macArray[0]; -+ -+ crc[2] = macArray[47] ^ macArray[46] ^ macArray[44] ^ macArray[43] ^ -+ macArray[42] ^ macArray[39] ^ macArray[37] ^ macArray[34] ^ -+ macArray[33] ^ macArray[29] ^ macArray[28] ^ macArray[25] ^ -+ macArray[24] ^ macArray[22] ^ macArray[17] ^ macArray[15] ^ -+ macArray[13] ^ macArray[12] ^ macArray[10] ^ macArray[8] ^ -+ macArray[6] ^ macArray[2] ^ macArray[1] ^ macArray[0]; -+ -+ crc[3] = macArray[47] ^ macArray[45] ^ macArray[44] ^ macArray[43] ^ -+ macArray[40] ^ macArray[38] ^ macArray[35] ^ macArray[34] ^ -+ macArray[30] ^ macArray[29] ^ macArray[26] ^ macArray[25] ^ -+ macArray[23] ^ macArray[18] ^ macArray[16] ^ macArray[14] ^ -+ macArray[13] ^ macArray[11] ^ macArray[9] ^ macArray[7] ^ -+ macArray[3] ^ macArray[2] ^ macArray[1]; -+ -+ crc[4] = macArray[46] ^ macArray[45] ^ macArray[44] ^ macArray[41] ^ -+ macArray[39] ^ macArray[36] ^ macArray[35] ^ macArray[31] ^ -+ macArray[30] ^ macArray[27] ^ macArray[26] ^ macArray[24] ^ -+ macArray[19] ^ macArray[17] ^ macArray[15] ^ macArray[14] ^ -+ macArray[12] ^ macArray[10] ^ macArray[8] ^ macArray[4] ^ -+ macArray[3] ^ macArray[2]; -+ -+ crc[5] = macArray[47] ^ macArray[46] ^ macArray[45] ^ macArray[42] ^ -+ macArray[40] ^ macArray[37] ^ macArray[36] ^ macArray[32] ^ -+ macArray[31] ^ macArray[28] ^ macArray[27] ^ macArray[25] ^ -+ macArray[20] ^ macArray[18] ^ macArray[16] ^ macArray[15] ^ -+ macArray[13] ^ macArray[11] ^ macArray[9] ^ macArray[5] ^ -+ macArray[4] ^ macArray[3]; -+ -+ crc[6] = macArray[47] ^ macArray[46] ^ macArray[43] ^ macArray[41] ^ -+ macArray[38] ^ macArray[37] ^ macArray[33] ^ macArray[32] ^ -+ macArray[29] ^ macArray[28] ^ macArray[26] ^ macArray[21] ^ -+ macArray[19] ^ macArray[17] ^ macArray[16] ^ macArray[14] ^ -+ macArray[12] ^ macArray[10] ^ macArray[6] ^ macArray[5] ^ -+ macArray[4]; -+ -+ crc[7] = macArray[47] ^ macArray[44] ^ macArray[42] ^ macArray[39] ^ -+ macArray[38] ^ macArray[34] ^ macArray[33] ^ macArray[30] ^ -+ macArray[29] ^ macArray[27] ^ macArray[22] ^ macArray[20] ^ -+ macArray[18] ^ macArray[17] ^ macArray[15] ^ macArray[13] ^ -+ macArray[11] ^ macArray[7] ^ macArray[6] ^ macArray[5]; -+ -+ for(i=0; i<8; i++) -+ crcResult = crcResult | (crc[i] << i); -+ -+ return crcResult; -+} -+/******************************************************************************* -+* mvEthMcastAddrSet - Multicast address settings. -+* -+* DESCRIPTION: -+* This API controls the MV device MAC multicast support. -+* The MV device supports multicast using two tables: -+* 1) Special Multicast Table for MAC addresses of the form -+* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). -+* The MAC DA[7:0] bits are used as a pointer to the Special Multicast -+* Table entries in the DA-Filter table. -+* In this case, the function calls ethPortSmcAddr() routine to set the -+* Special Multicast Table. -+* 2) Other Multicast Table for multicast of another type. A CRC-8bit -+* is used as an index to the Other Multicast Table entries in the -+* DA-Filter table. -+* In this case, the function calculates the CRC-8bit value and calls -+* ethPortOmcAddr() routine to set the Other Multicast Table. -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet port handler. -+* MV_U8* pAddr - Address to be set -+* int queue - RX queue to capture all packets with this -+* Multicast MAC address. -+* -1 means delete this Multicast address. -+* -+* RETURN: MV_STATUS -+* MV_TRUE - Success, Other - Failure -+* -+*******************************************************************************/ -+MV_STATUS mvEthMcastAddrSet(void* pPortHndl, MV_U8 *pAddr, int queue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ unsigned char crcResult = 0; -+ -+ if(queue >= MV_ETH_RX_Q_NUM) -+ { -+ mvOsPrintf("ethPort %d: RX queue #%d is out of range\n", -+ pPortCtrl->portNo, queue); -+ return MV_BAD_PARAM; -+ } -+ -+ if((pAddr[0] == 0x01) && -+ (pAddr[1] == 0x00) && -+ (pAddr[2] == 0x5E) && -+ (pAddr[3] == 0x00) && -+ (pAddr[4] == 0x00)) -+ { -+ ethSetSpecialMcastAddr(pPortCtrl->portNo, pAddr[5], queue); -+ } -+ else -+ { -+ crcResult = mvEthMcastCrc8Get(pAddr); -+ -+ /* Check Add counter for this CRC value */ -+ if(queue == -1) -+ { -+ if(pPortCtrl->mcastCount[crcResult] == 0) -+ { -+ mvOsPrintf("ethPort #%d: No valid Mcast for crc8=0x%02x\n", -+ pPortCtrl->portNo, (unsigned)crcResult); -+ return MV_NO_SUCH; -+ } -+ -+ pPortCtrl->mcastCount[crcResult]--; -+ if(pPortCtrl->mcastCount[crcResult] != 0) -+ { -+ mvOsPrintf("ethPort #%d: After delete there are %d valid Mcast for crc8=0x%02x\n", -+ pPortCtrl->portNo, pPortCtrl->mcastCount[crcResult], -+ (unsigned)crcResult); -+ return MV_NO_CHANGE; -+ } -+ } -+ else -+ { -+ pPortCtrl->mcastCount[crcResult]++; -+ if(pPortCtrl->mcastCount[crcResult] > 1) -+ { -+ mvOsPrintf("ethPort #%d: Valid Mcast for crc8=0x%02x already exists\n", -+ pPortCtrl->portNo, (unsigned)crcResult); -+ return MV_NO_CHANGE; -+ } -+ } -+ ethSetOtherMcastAddr(pPortCtrl->portNo, crcResult, queue); -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* ethSetUcastTable - Unicast address settings. -+* -+* DESCRIPTION: -+* Set all entries in the Unicast MAC Table queue==-1 means reject all -+* INPUT: -+* -+* RETURN: -+* -+*******************************************************************************/ -+static void ethSetUcastTable(int portNo, int queue) -+{ -+ int offset; -+ MV_U32 regValue; -+ -+ if(queue == -1) -+ { -+ regValue = 0; -+ } -+ else -+ { -+ regValue = (((0x01 | (queue<<1)) << 0) | -+ ((0x01 | (queue<<1)) << 8) | -+ ((0x01 | (queue<<1)) << 16) | -+ ((0x01 | (queue<<1)) << 24)); -+ } -+ -+ for (offset=0; offset<=0xC; offset+=4) -+ MV_REG_WRITE((ETH_DA_FILTER_UCAST_BASE(portNo) + offset), regValue); -+} -+ -+/******************************************************************************* -+* mvEthSetSpecialMcastTable - Special Multicast address settings. -+* -+* DESCRIPTION: -+* Set all entries to the Special Multicast MAC Table. queue==-1 means reject all -+* INPUT: -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_VOID mvEthSetSpecialMcastTable(int portNo, int queue) -+{ -+ int offset; -+ MV_U32 regValue; -+ -+ if(queue == -1) -+ { -+ regValue = 0; -+ } -+ else -+ { -+ regValue = (((0x01 | (queue<<1)) << 0) | -+ ((0x01 | (queue<<1)) << 8) | -+ ((0x01 | (queue<<1)) << 16) | -+ ((0x01 | (queue<<1)) << 24)); -+ } -+ -+ for (offset=0; offset<=0xFC; offset+=4) -+ { -+ MV_REG_WRITE((ETH_DA_FILTER_SPEC_MCAST_BASE(portNo) + -+ offset), regValue); -+ } -+} -+ -+/******************************************************************************* -+* mvEthSetOtherMcastTable - Other Multicast address settings. -+* -+* DESCRIPTION: -+* Set all entries to the Other Multicast MAC Table. queue==-1 means reject all -+* INPUT: -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_VOID mvEthSetOtherMcastTable(int portNo, int queue) -+{ -+ int offset; -+ MV_U32 regValue; -+ -+ if(queue == -1) -+ { -+ regValue = 0; -+ } -+ else -+ { -+ regValue = (((0x01 | (queue<<1)) << 0) | -+ ((0x01 | (queue<<1)) << 8) | -+ ((0x01 | (queue<<1)) << 16) | -+ ((0x01 | (queue<<1)) << 24)); -+ } -+ -+ for (offset=0; offset<=0xFC; offset+=4) -+ { -+ MV_REG_WRITE((ETH_DA_FILTER_OTH_MCAST_BASE(portNo) + -+ offset), regValue); -+ } -+} -+ -+/******************************************************************************* -+* ethSetUcastAddr - This function Set the port unicast address table -+* -+* DESCRIPTION: -+* This function locates the proper entry in the Unicast table for the -+* specified MAC nibble and sets its properties according to function -+* parameters. -+* -+* INPUT: -+* int ethPortNum - Port number. -+* MV_U8 lastNibble - Unicast MAC Address last nibble. -+* int queue - Rx queue number for this MAC address. -+* value "-1" means remove address -+* -+* OUTPUT: -+* This function add/removes MAC addresses from the port unicast address -+* table. -+* -+* RETURN: -+* MV_TRUE is output succeeded. -+* MV_FALSE if option parameter is invalid. -+* -+*******************************************************************************/ -+static MV_BOOL ethSetUcastAddr(int portNo, MV_U8 lastNibble, int queue) -+{ -+ unsigned int unicastReg; -+ unsigned int tblOffset; -+ unsigned int regOffset; -+ -+ /* Locate the Unicast table entry */ -+ lastNibble = (0xf & lastNibble); -+ tblOffset = (lastNibble / 4) * 4; /* Register offset from unicast table base*/ -+ regOffset = lastNibble % 4; /* Entry offset within the above register */ -+ -+ -+ unicastReg = MV_REG_READ( (ETH_DA_FILTER_UCAST_BASE(portNo) + -+ tblOffset)); -+ -+ -+ if(queue == -1) -+ { -+ /* Clear accepts frame bit at specified unicast DA table entry */ -+ unicastReg &= ~(0xFF << (8*regOffset)); -+ } -+ else -+ { -+ unicastReg &= ~(0xFF << (8*regOffset)); -+ unicastReg |= ((0x01 | (queue<<1)) << (8*regOffset)); -+ } -+ MV_REG_WRITE( (ETH_DA_FILTER_UCAST_BASE(portNo) + tblOffset), -+ unicastReg); -+ -+ return MV_TRUE; -+} -+ -+/******************************************************************************* -+* ethSetSpecialMcastAddr - Special Multicast address settings. -+* -+* DESCRIPTION: -+* This routine controls the MV device special MAC multicast support. -+* The Special Multicast Table for MAC addresses supports MAC of the form -+* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). -+* The MAC DA[7:0] bits are used as a pointer to the Special Multicast -+* Table entries in the DA-Filter table. -+* This function set the Special Multicast Table appropriate entry -+* according to the argument given. -+* -+* INPUT: -+* int ethPortNum Port number. -+* unsigned char mcByte Multicast addr last byte (MAC DA[7:0] bits). -+* int queue Rx queue number for this MAC address. -+* int option 0 = Add, 1 = remove address. -+* -+* OUTPUT: -+* See description. -+* -+* RETURN: -+* MV_TRUE is output succeeded. -+* MV_FALSE if option parameter is invalid. -+* -+*******************************************************************************/ -+static MV_BOOL ethSetSpecialMcastAddr(int ethPortNum, MV_U8 lastByte, int queue) -+{ -+ unsigned int smcTableReg; -+ unsigned int tblOffset; -+ unsigned int regOffset; -+ -+ /* Locate the SMC table entry */ -+ tblOffset = (lastByte / 4); /* Register offset from SMC table base */ -+ regOffset = lastByte % 4; /* Entry offset within the above register */ -+ -+ smcTableReg = MV_REG_READ((ETH_DA_FILTER_SPEC_MCAST_BASE(ethPortNum) + tblOffset*4)); -+ -+ if(queue == -1) -+ { -+ /* Clear accepts frame bit at specified Special DA table entry */ -+ smcTableReg &= ~(0xFF << (8 * regOffset)); -+ } -+ else -+ { -+ smcTableReg &= ~(0xFF << (8 * regOffset)); -+ smcTableReg |= ((0x01 | (queue<<1)) << (8 * regOffset)); -+ } -+ MV_REG_WRITE((ETH_DA_FILTER_SPEC_MCAST_BASE(ethPortNum) + -+ tblOffset*4), smcTableReg); -+ -+ return MV_TRUE; -+} -+ -+/******************************************************************************* -+* ethSetOtherMcastAddr - Multicast address settings. -+* -+* DESCRIPTION: -+* This routine controls the MV device Other MAC multicast support. -+* The Other Multicast Table is used for multicast of another type. -+* A CRC-8bit is used as an index to the Other Multicast Table entries -+* in the DA-Filter table. -+* The function gets the CRC-8bit value from the calling routine and -+* set the Other Multicast Table appropriate entry according to the -+* CRC-8 argument given. -+* -+* INPUT: -+* int ethPortNum Port number. -+* MV_U8 crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1). -+* int queue Rx queue number for this MAC address. -+* -+* OUTPUT: -+* See description. -+* -+* RETURN: -+* MV_TRUE is output succeeded. -+* MV_FALSE if option parameter is invalid. -+* -+*******************************************************************************/ -+static MV_BOOL ethSetOtherMcastAddr(int ethPortNum, MV_U8 crc8, int queue) -+{ -+ unsigned int omcTableReg; -+ unsigned int tblOffset; -+ unsigned int regOffset; -+ -+ /* Locate the OMC table entry */ -+ tblOffset = (crc8 / 4) * 4; /* Register offset from OMC table base */ -+ regOffset = crc8 % 4; /* Entry offset within the above register */ -+ -+ omcTableReg = MV_REG_READ( -+ (ETH_DA_FILTER_OTH_MCAST_BASE(ethPortNum) + tblOffset)); -+ -+ if(queue == -1) -+ { -+ /* Clear accepts frame bit at specified Other DA table entry */ -+ omcTableReg &= ~(0xFF << (8 * regOffset)); -+ } -+ else -+ { -+ omcTableReg &= ~(0xFF << (8 * regOffset)); -+ omcTableReg |= ((0x01 | (queue<<1)) << (8 * regOffset)); -+ } -+ -+ MV_REG_WRITE((ETH_DA_FILTER_OTH_MCAST_BASE(ethPortNum) + tblOffset), -+ omcTableReg); -+ -+ return MV_TRUE; -+} -+ -+ -+/******************************************************************************/ -+/* MIB Counters functions */ -+/******************************************************************************/ -+ -+ -+/******************************************************************************* -+* mvEthMibCounterRead - Read a MIB counter -+* -+* DESCRIPTION: -+* This function reads a MIB counter of a specific ethernet port. -+* NOTE - Read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW or -+* ETH_MIB_GOOD_OCTETS_SENT_LOW counters will return 64 bits value, -+* so pHigh32 pointer should not be NULL in this case. -+* -+* INPUT: -+* int ethPortNum - Ethernet Port number. -+* unsigned int mibOffset - MIB counter offset. -+* -+* OUTPUT: -+* MV_U32* pHigh32 - pointer to place where 32 most significant bits -+* of the counter will be stored. -+* -+* RETURN: -+* 32 low sgnificant bits of MIB counter value. -+* -+*******************************************************************************/ -+MV_U32 mvEthMibCounterRead(void* pPortHandle, unsigned int mibOffset, -+ MV_U32* pHigh32) -+{ -+ int portNo; -+ MV_U32 valLow32, valHigh32; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ -+ portNo = pPortCtrl->portNo; -+ -+ valLow32 = MV_REG_READ(ETH_MIB_COUNTERS_BASE(portNo) + mibOffset); -+ -+ /* Implement FEr ETH. Erroneous Value when Reading the Upper 32-bits */ -+ /* of a 64-bit MIB Counter. */ -+ if( (mibOffset == ETH_MIB_GOOD_OCTETS_RECEIVED_LOW) || -+ (mibOffset == ETH_MIB_GOOD_OCTETS_SENT_LOW) ) -+ { -+ valHigh32 = MV_REG_READ(ETH_MIB_COUNTERS_BASE(portNo) + mibOffset + 4); -+ if(pHigh32 != NULL) -+ *pHigh32 = valHigh32; -+ } -+ return valLow32; -+} -+ -+/******************************************************************************* -+* mvEthMibCountersClear - Clear all MIB counters -+* -+* DESCRIPTION: -+* This function clears all MIB counters -+* -+* INPUT: -+* int ethPortNum - Ethernet Port number. -+* -+* -+* RETURN: void -+* -+*******************************************************************************/ -+void mvEthMibCountersClear(void* pPortHandle) -+{ -+ int i, portNo; -+ unsigned int dummy; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ -+ portNo = pPortCtrl->portNo; -+ -+ /* Perform dummy reads from MIB counters */ -+ for(i=ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i 0xFF) -+ { -+ mvOsPrintf("eth_%d: tos=0x%x is out of range\n", pPortCtrl->portNo, tos); -+ return -1; -+ } -+ regIdx = mvOsDivide(tos>>2, 10); -+ regOffs = mvOsReminder(tos>>2, 10); -+ -+ regValue = MV_REG_READ(ETH_DIFF_SERV_PRIO_REG(pPortCtrl->portNo, regIdx) ); -+ rxq = (regValue >> (regOffs*3)); -+ rxq &= 0x7; -+ -+ return rxq; -+} -+ -+/******************************************************************************* -+* mvEthTosToRxqSet - Map packets with special TOS value to special RX queue -+* -+* DESCRIPTION: -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* int tos - TOS value in the IP header of the packet -+* int rxq - RX Queue for packets with the configured TOS value -+* Negative value (-1) means no special processing for these packets, -+* so they will be processed as regular packets. -+* -+* RETURN: MV_STATUS -+*******************************************************************************/ -+MV_STATUS mvEthTosToRxqSet(void* pPortHandle, int tos, int rxq) -+{ -+ MV_U32 regValue; -+ int regIdx, regOffs; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ -+ if( (rxq < 0) || (rxq >= MV_ETH_RX_Q_NUM) ) -+ { -+ mvOsPrintf("eth_%d: RX queue #%d is out of range\n", pPortCtrl->portNo, rxq); -+ return MV_BAD_PARAM; -+ } -+ if(tos > 0xFF) -+ { -+ mvOsPrintf("eth_%d: tos=0x%x is out of range\n", pPortCtrl->portNo, tos); -+ return MV_BAD_PARAM; -+ } -+ regIdx = mvOsDivide(tos>>2, 10); -+ regOffs = mvOsReminder(tos>>2, 10); -+ -+ regValue = MV_REG_READ(ETH_DIFF_SERV_PRIO_REG(pPortCtrl->portNo, regIdx) ); -+ regValue &= ~(0x7 << (regOffs*3)); -+ regValue |= (rxq << (regOffs*3)); -+ -+ MV_REG_WRITE(ETH_DIFF_SERV_PRIO_REG(pPortCtrl->portNo, regIdx), regValue); -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthVlanPrioRxQueue - Configure RX queue to capture VLAN tagged packets with -+* special priority bits [0-2] -+* -+* DESCRIPTION: -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* int bpduQueue - Special queue to capture VLAN tagged packets with special -+* priority. -+* Negative value (-1) means no special processing for these packets, -+* so they will be processed as regular packets. -+* -+* RETURN: MV_STATUS -+* MV_OK - Success -+* MV_FAIL - Failed. -+* -+*******************************************************************************/ -+MV_STATUS mvEthVlanPrioRxQueue(void* pPortHandle, int vlanPrio, int vlanPrioQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ MV_U32 vlanPrioReg; -+ -+ if(vlanPrioQueue >= MV_ETH_RX_Q_NUM) -+ { -+ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", vlanPrioQueue); -+ return MV_BAD_PARAM; -+ } -+ if(vlanPrio >= 8) -+ { -+ mvOsPrintf("ethDrv: vlanPrio=%d is out of range\n", vlanPrio); -+ return MV_BAD_PARAM; -+ } -+ -+ vlanPrioReg = MV_REG_READ(ETH_VLAN_TAG_TO_PRIO_REG(pPortCtrl->portNo)); -+ vlanPrioReg &= ~(0x7 << (vlanPrio*3)); -+ vlanPrioReg |= (vlanPrioQueue << (vlanPrio*3)); -+ MV_REG_WRITE(ETH_VLAN_TAG_TO_PRIO_REG(pPortCtrl->portNo), vlanPrioReg); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvEthBpduRxQueue - Configure RX queue to capture BPDU packets. -+* -+* DESCRIPTION: -+* This function defines processing of BPDU packets. -+* BPDU packets can be accepted and captured to one of RX queues -+* or can be processing as regular Multicast packets. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* int bpduQueue - Special queue to capture BPDU packets (DA is equal to -+* 01-80-C2-00-00-00 through 01-80-C2-00-00-FF, -+* except for the Flow-Control Pause packets). -+* Negative value (-1) means no special processing for BPDU, -+* packets so they will be processed as regular Multicast packets. -+* -+* RETURN: MV_STATUS -+* MV_OK - Success -+* MV_FAIL - Failed. -+* -+*******************************************************************************/ -+MV_STATUS mvEthBpduRxQueue(void* pPortHandle, int bpduQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ MV_U32 portCfgReg; -+ MV_U32 portCfgExtReg; -+ -+ if(bpduQueue >= MV_ETH_RX_Q_NUM) -+ { -+ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", bpduQueue); -+ return MV_BAD_PARAM; -+ } -+ -+ portCfgExtReg = MV_REG_READ(ETH_PORT_CONFIG_EXTEND_REG(pPortCtrl->portNo)); -+ -+ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); -+ if(bpduQueue >= 0) -+ { -+ pPortCtrl->portConfig.rxBpduQ = bpduQueue; -+ -+ portCfgReg &= ~ETH_DEF_RX_BPDU_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_BPDU_QUEUE_MASK(pPortCtrl->portConfig.rxBpduQ); -+ -+ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); -+ -+ portCfgExtReg |= ETH_CAPTURE_SPAN_BPDU_ENABLE_MASK; -+ } -+ else -+ { -+ pPortCtrl->portConfig.rxBpduQ = -1; -+ /* no special processing for BPDU packets */ -+ portCfgExtReg &= (~ETH_CAPTURE_SPAN_BPDU_ENABLE_MASK); -+ } -+ -+ MV_REG_WRITE(ETH_PORT_CONFIG_EXTEND_REG(pPortCtrl->portNo), portCfgExtReg); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvEthArpRxQueue - Configure RX queue to capture ARP packets. -+* -+* DESCRIPTION: -+* This function defines processing of ARP (type=0x0806) packets. -+* ARP packets can be accepted and captured to one of RX queues -+* or can be processed as other Broadcast packets. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* int arpQueue - Special queue to capture ARP packets (type=0x806). -+* Negative value (-1) means discard ARP packets -+* -+* RETURN: MV_STATUS -+* MV_OK - Success -+* MV_FAIL - Failed. -+* -+*******************************************************************************/ -+MV_STATUS mvEthArpRxQueue(void* pPortHandle, int arpQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ MV_U32 portCfgReg; -+ -+ if(arpQueue >= MV_ETH_RX_Q_NUM) -+ { -+ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", arpQueue); -+ return MV_BAD_PARAM; -+ } -+ -+ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); -+ -+ if(arpQueue >= 0) -+ { -+ pPortCtrl->portConfig.rxArpQ = arpQueue; -+ portCfgReg &= ~ETH_DEF_RX_ARP_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_ARP_QUEUE_MASK(pPortCtrl->portConfig.rxArpQ); -+ -+ portCfgReg &= (~ETH_REJECT_ARP_BCAST_MASK); -+ } -+ else -+ { -+ pPortCtrl->portConfig.rxArpQ = -1; -+ portCfgReg |= ETH_REJECT_ARP_BCAST_MASK; -+ } -+ -+ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvEthTcpRxQueue - Configure RX queue to capture TCP packets. -+* -+* DESCRIPTION: -+* This function defines processing of TCP packets. -+* TCP packets can be accepted and captured to one of RX queues -+* or can be processed as regular Unicast packets. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* int tcpQueue - Special queue to capture TCP packets. Value "-1" -+* means no special processing for TCP packets, -+* so they will be processed as regular -+* -+* RETURN: MV_STATUS -+* MV_OK - Success -+* MV_FAIL - Failed. -+* -+*******************************************************************************/ -+MV_STATUS mvEthTcpRxQueue(void* pPortHandle, int tcpQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ MV_U32 portCfgReg; -+ -+ if(tcpQueue >= MV_ETH_RX_Q_NUM) -+ { -+ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", tcpQueue); -+ return MV_BAD_PARAM; -+ } -+ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); -+ -+ if(tcpQueue >= 0) -+ { -+ pPortCtrl->portConfig.rxTcpQ = tcpQueue; -+ portCfgReg &= ~ETH_DEF_RX_TCP_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_TCP_QUEUE_MASK(pPortCtrl->portConfig.rxTcpQ); -+ -+ portCfgReg |= ETH_CAPTURE_TCP_FRAMES_ENABLE_MASK; -+ } -+ else -+ { -+ pPortCtrl->portConfig.rxTcpQ = -1; -+ portCfgReg &= (~ETH_CAPTURE_TCP_FRAMES_ENABLE_MASK); -+ } -+ -+ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvEthUdpRxQueue - Configure RX queue to capture UDP packets. -+* -+* DESCRIPTION: -+* This function defines processing of UDP packets. -+* TCP packets can be accepted and captured to one of RX queues -+* or can be processed as regular Unicast packets. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* int udpQueue - Special queue to capture UDP packets. Value "-1" -+* means no special processing for UDP packets, -+* so they will be processed as regular -+* -+* RETURN: MV_STATUS -+* MV_OK - Success -+* MV_FAIL - Failed. -+* -+*******************************************************************************/ -+MV_STATUS mvEthUdpRxQueue(void* pPortHandle, int udpQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ MV_U32 portCfgReg; -+ -+ if(udpQueue >= MV_ETH_RX_Q_NUM) -+ { -+ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", udpQueue); -+ return MV_BAD_PARAM; -+ } -+ -+ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); -+ -+ if(udpQueue >= 0) -+ { -+ pPortCtrl->portConfig.rxUdpQ = udpQueue; -+ portCfgReg &= ~ETH_DEF_RX_UDP_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_UDP_QUEUE_MASK(pPortCtrl->portConfig.rxUdpQ); -+ -+ portCfgReg |= ETH_CAPTURE_UDP_FRAMES_ENABLE_MASK; -+ } -+ else -+ { -+ pPortCtrl->portConfig.rxUdpQ = -1; -+ portCfgReg &= ~ETH_CAPTURE_UDP_FRAMES_ENABLE_MASK; -+ } -+ -+ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************/ -+/* Speed, Duplex, FlowControl routines */ -+/******************************************************************************/ -+ -+/******************************************************************************* -+* mvEthSpeedDuplexSet - Set Speed and Duplex of the port. -+* -+* DESCRIPTION: -+* This function configure the port to work with desirable Duplex and Speed. -+* Changing of these parameters are allowed only when port is disabled. -+* This function disable the port if was enabled, change duplex and speed -+* and, enable the port back if needed. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* ETH_PORT_SPEED speed - Speed of the port. -+* ETH_PORT_SPEED duplex - Duplex of the port. -+* -+* RETURN: MV_STATUS -+* MV_OK - Success -+* MV_OUT_OF_RANGE - Failed. Port is out of valid range -+* MV_NOT_FOUND - Failed. Port is not initialized. -+* MV_BAD_PARAM - Input parameters (speed/duplex) in conflict. -+* MV_BAD_VALUE - Value of one of input parameters (speed, duplex) -+* is not valid -+* -+*******************************************************************************/ -+MV_STATUS mvEthSpeedDuplexSet(void* pPortHandle, MV_ETH_PORT_SPEED speed, -+ MV_ETH_PORT_DUPLEX duplex) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ int port = pPortCtrl->portNo; -+ MV_U32 portSerialCtrlReg; -+ -+ if( (port < 0) || (port >= (int)mvCtrlEthMaxPortGet()) ) -+ return MV_OUT_OF_RANGE; -+ -+ pPortCtrl = ethPortCtrl[port]; -+ if(pPortCtrl == NULL) -+ return MV_NOT_FOUND; -+ -+ /* Check validity */ -+ if( (speed == MV_ETH_SPEED_1000) && (duplex == MV_ETH_DUPLEX_HALF) ) -+ return MV_BAD_PARAM; -+ -+ portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port)); -+ /* Set Speed */ -+ switch(speed) -+ { -+ case MV_ETH_SPEED_AN: -+ portSerialCtrlReg &= ~ETH_DISABLE_SPEED_AUTO_NEG_MASK; -+ break; -+ -+ case MV_ETH_SPEED_10: -+ portSerialCtrlReg |= ETH_DISABLE_SPEED_AUTO_NEG_MASK; -+ portSerialCtrlReg &= ~ETH_SET_GMII_SPEED_1000_MASK; -+ portSerialCtrlReg &= ~ETH_SET_MII_SPEED_100_MASK; -+ break; -+ -+ case MV_ETH_SPEED_100: -+ portSerialCtrlReg |= ETH_DISABLE_SPEED_AUTO_NEG_MASK; -+ portSerialCtrlReg &= ~ETH_SET_GMII_SPEED_1000_MASK; -+ portSerialCtrlReg |= ETH_SET_MII_SPEED_100_MASK; -+ break; -+ -+ case MV_ETH_SPEED_1000: -+ portSerialCtrlReg |= ETH_DISABLE_SPEED_AUTO_NEG_MASK; -+ portSerialCtrlReg |= ETH_SET_GMII_SPEED_1000_MASK; -+ break; -+ -+ default: -+ mvOsPrintf("ethDrv: Unexpected Speed value %d\n", speed); -+ return MV_BAD_VALUE; -+ } -+ /* Set duplex */ -+ switch(duplex) -+ { -+ case MV_ETH_DUPLEX_AN: -+ portSerialCtrlReg &= ~ETH_DISABLE_DUPLEX_AUTO_NEG_MASK; -+ break; -+ -+ case MV_ETH_DUPLEX_HALF: -+ portSerialCtrlReg |= ETH_DISABLE_DUPLEX_AUTO_NEG_MASK; -+ portSerialCtrlReg &= ~ETH_SET_FULL_DUPLEX_MASK; -+ break; -+ -+ case MV_ETH_DUPLEX_FULL: -+ portSerialCtrlReg |= ETH_DISABLE_DUPLEX_AUTO_NEG_MASK; -+ portSerialCtrlReg |= ETH_SET_FULL_DUPLEX_MASK; -+ break; -+ -+ default: -+ mvOsPrintf("ethDrv: Unexpected Duplex value %d\n", duplex); -+ return MV_BAD_VALUE; -+ } -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(port), portSerialCtrlReg); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthFlowCtrlSet - Set Flow Control of the port. -+* -+* DESCRIPTION: -+* This function configure the port to work with desirable Duplex and -+* Speed. Changing of these parameters are allowed only when port is -+* disabled. This function disable the port if was enabled, change -+* duplex and speed and, enable the port back if needed. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* MV_ETH_PORT_FC flowControl - Flow control of the port. -+* -+* RETURN: MV_STATUS -+* MV_OK - Success -+* MV_OUT_OF_RANGE - Failed. Port is out of valid range -+* MV_NOT_FOUND - Failed. Port is not initialized. -+* MV_BAD_VALUE - Value flowControl parameters is not valid -+* -+*******************************************************************************/ -+MV_STATUS mvEthFlowCtrlSet(void* pPortHandle, MV_ETH_PORT_FC flowControl) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ int port = pPortCtrl->portNo; -+ MV_U32 portSerialCtrlReg; -+ -+ if( (port < 0) || (port >= (int)mvCtrlEthMaxPortGet() ) ) -+ return MV_OUT_OF_RANGE; -+ -+ pPortCtrl = ethPortCtrl[port]; -+ if(pPortCtrl == NULL) -+ return MV_NOT_FOUND; -+ -+ portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port)); -+ switch(flowControl) -+ { -+ case MV_ETH_FC_AN_ADV_DIS: -+ portSerialCtrlReg &= ~ETH_DISABLE_FC_AUTO_NEG_MASK; -+ portSerialCtrlReg &= ~ETH_ADVERTISE_SYM_FC_MASK; -+ break; -+ -+ case MV_ETH_FC_AN_ADV_SYM: -+ portSerialCtrlReg &= ~ETH_DISABLE_FC_AUTO_NEG_MASK; -+ portSerialCtrlReg |= ETH_ADVERTISE_SYM_FC_MASK; -+ break; -+ -+ case MV_ETH_FC_DISABLE: -+ portSerialCtrlReg |= ETH_DISABLE_FC_AUTO_NEG_MASK; -+ portSerialCtrlReg &= ~ETH_SET_FLOW_CTRL_MASK; -+ break; -+ -+ case MV_ETH_FC_ENABLE: -+ portSerialCtrlReg |= ETH_DISABLE_FC_AUTO_NEG_MASK; -+ portSerialCtrlReg |= ETH_SET_FLOW_CTRL_MASK; -+ break; -+ -+ default: -+ mvOsPrintf("ethDrv: Unexpected FlowControl value %d\n", flowControl); -+ return MV_BAD_VALUE; -+ } -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(port), portSerialCtrlReg); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthHeaderModeSet - Set port header mode. -+* -+* DESCRIPTION: -+* This function configures the port to work in Marvell-Header mode. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* MV_ETH_HEADER_MODE headerMode - The header mode to set the port in. -+* -+* RETURN: MV_STATUS -+* MV_OK - Success -+* MV_NOT_SUPPORTED- Feature not supported. -+* MV_OUT_OF_RANGE - Failed. Port is out of valid range -+* MV_NOT_FOUND - Failed. Port is not initialized. -+* MV_BAD_VALUE - Value of headerMode or numRxQueue parameter is not valid. -+* -+*******************************************************************************/ -+MV_STATUS mvEthHeaderModeSet(void* pPortHandle, MV_ETH_HEADER_MODE headerMode) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ int port = pPortCtrl->portNo; -+ MV_U32 mvHeaderReg; -+ MV_U32 numRxQ = MV_ETH_RX_Q_NUM; -+ -+ if((port < 0) || (port >= mvCtrlEthMaxPortGet())) -+ return MV_OUT_OF_RANGE; -+ -+ pPortCtrl = ethPortCtrl[port]; -+ if(pPortCtrl == NULL) -+ return MV_NOT_FOUND; -+ -+ mvHeaderReg = MV_REG_READ(ETH_PORT_MARVELL_HEADER_REG(port)); -+ /* Disable header mode. */ -+ mvHeaderReg &= ~ETH_MVHDR_EN_MASK; -+ -+ if(headerMode != MV_ETH_DISABLE_HEADER_MODE) -+ { -+ /* Enable Header mode. */ -+ mvHeaderReg |= ETH_MVHDR_EN_MASK; -+ -+ /* Clear DA-Prefix & MHMask fields.*/ -+ mvHeaderReg &= ~(ETH_MVHDR_DAPREFIX_MASK | ETH_MVHDR_MHMASK_MASK); -+ -+ if(numRxQ > 1) -+ { -+ switch (headerMode) -+ { -+ case(MV_ETH_ENABLE_HEADER_MODE_PRI_2_1): -+ mvHeaderReg |= ETH_MVHDR_DAPREFIX_PRI_1_2; -+ break; -+ case(MV_ETH_ENABLE_HEADER_MODE_PRI_DBNUM): -+ mvHeaderReg |= ETH_MVHDR_DAPREFIX_DBNUM_PRI; -+ break; -+ case(MV_ETH_ENABLE_HEADER_MODE_PRI_SPID): -+ mvHeaderReg |= ETH_MVHDR_DAPREFIX_SPID_PRI; -+ break; -+ default: -+ break; -+ } -+ -+ switch (numRxQ) -+ { -+ case (4): -+ mvHeaderReg |= ETH_MVHDR_MHMASK_4_QUEUE; -+ break; -+ case (8): -+ mvHeaderReg |= ETH_MVHDR_MHMASK_8_QUEUE; -+ break; -+ default: -+ break; -+ } -+ } -+ } -+ -+ MV_REG_WRITE(ETH_PORT_MARVELL_HEADER_REG(port), mvHeaderReg); -+ -+ return MV_OK; -+} -+ -+#if (MV_ETH_VERSION >= 4) -+/******************************************************************************* -+* mvEthEjpModeSet - Enable / Disable EJP policy for TX. -+* -+* DESCRIPTION: -+* This function -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* MV_BOOL TRUE - enable EJP mode -+* FALSE - disable EJP mode -+* -+* OUTPUT: MV_STATUS -+* MV_OK - Success -+* Other - Failure -+* -+* RETURN: None. -+* -+*******************************************************************************/ -+MV_STATUS mvEthEjpModeSet(void* pPortHandle, int mode) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ int port = pPortCtrl->portNo; -+ -+ if((port < 0) || (port >= mvCtrlEthMaxPortGet())) -+ return MV_OUT_OF_RANGE; -+ -+ pPortCtrl = ethPortCtrl[port]; -+ if(pPortCtrl == NULL) -+ return MV_NOT_FOUND; -+ -+ pPortCtrl->portConfig.ejpMode = mode; -+ if(mode) -+ { -+ /* EJP enabled */ -+ MV_REG_WRITE(ETH_TXQ_CMD_1_REG(port), ETH_TX_EJP_ENABLE_MASK); -+ } -+ else -+ { -+ /* EJP disabled */ -+ MV_REG_WRITE(ETH_TXQ_CMD_1_REG(port), 0); -+ } -+ mvOsPrintf("eth_%d: EJP %s - ETH_TXQ_CMD_1_REG: 0x%x = 0x%08x\n", -+ port, mode ? "Enabled" : "Disabled", ETH_TXQ_CMD_1_REG(port), -+ MV_REG_READ(ETH_TXQ_CMD_1_REG(port))); -+ -+ return MV_OK; -+} -+#endif /* MV_ETH_VERSION >= 4 */ -+ -+/******************************************************************************* -+* mvEthStatusGet - Get major properties of the port . -+* -+* DESCRIPTION: -+* This function get major properties of the port (link, speed, duplex, -+* flowControl, etc) and return them using the single structure. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* -+* OUTPUT: -+* MV_ETH_PORT_STATUS* pStatus - Pointer to structure, were port status -+* will be placed. -+* -+* RETURN: None. -+* -+*******************************************************************************/ -+void mvEthStatusGet(void* pPortHandle, MV_ETH_PORT_STATUS* pStatus) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ int port = pPortCtrl->portNo; -+ -+ MV_U32 regValue; -+ -+ regValue = MV_REG_READ( ETH_PORT_STATUS_REG(port) ); -+ -+ if(regValue & ETH_GMII_SPEED_1000_MASK) -+ pStatus->speed = MV_ETH_SPEED_1000; -+ else if(regValue & ETH_MII_SPEED_100_MASK) -+ pStatus->speed = MV_ETH_SPEED_100; -+ else -+ pStatus->speed = MV_ETH_SPEED_10; -+ -+ if(regValue & ETH_LINK_UP_MASK) -+ pStatus->isLinkUp = MV_TRUE; -+ else -+ pStatus->isLinkUp = MV_FALSE; -+ -+ if(regValue & ETH_FULL_DUPLEX_MASK) -+ pStatus->duplex = MV_ETH_DUPLEX_FULL; -+ else -+ pStatus->duplex = MV_ETH_DUPLEX_HALF; -+ -+ -+ if(regValue & ETH_ENABLE_RCV_FLOW_CTRL_MASK) -+ pStatus->flowControl = MV_ETH_FC_ENABLE; -+ else -+ pStatus->flowControl = MV_ETH_FC_DISABLE; -+} -+ -+ -+/******************************************************************************/ -+/* PHY Control Functions */ -+/******************************************************************************/ -+ -+ -+/******************************************************************************* -+* mvEthPhyAddrSet - Set the ethernet port PHY address. -+* -+* DESCRIPTION: -+* This routine set the ethernet port PHY address according to given -+* parameter. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* int phyAddr - PHY address -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+void mvEthPhyAddrSet(void* pPortHandle, int phyAddr) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ int port = pPortCtrl->portNo; -+ unsigned int regData; -+ -+ regData = MV_REG_READ(ETH_PHY_ADDR_REG(port)); -+ -+ regData &= ~ETH_PHY_ADDR_MASK; -+ regData |= phyAddr; -+ -+ MV_REG_WRITE(ETH_PHY_ADDR_REG(port), regData); -+ -+ return; -+} -+ -+/******************************************************************************* -+* mvEthPhyAddrGet - Get the ethernet port PHY address. -+* -+* DESCRIPTION: -+* This routine returns the given ethernet port PHY address. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* -+* -+* RETURN: int - PHY address. -+* -+*******************************************************************************/ -+int mvEthPhyAddrGet(void* pPortHandle) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ int port = pPortCtrl->portNo; -+ unsigned int regData; -+ -+ regData = MV_REG_READ(ETH_PHY_ADDR_REG(port)); -+ -+ return ((regData >> (5 * port)) & 0x1f); -+} -+ -+/******************************************************************************/ -+/* Descriptor handling Functions */ -+/******************************************************************************/ -+ -+/******************************************************************************* -+* etherInitRxDescRing - Curve a Rx chain desc list and buffer in memory. -+* -+* DESCRIPTION: -+* This function prepares a Rx chained list of descriptors and packet -+* buffers in a form of a ring. The routine must be called after port -+* initialization routine and before port start routine. -+* The Ethernet SDMA engine uses CPU bus addresses to access the various -+* devices in the system (i.e. DRAM). This function uses the ethernet -+* struct 'virtual to physical' routine (set by the user) to set the ring -+* with physical addresses. -+* -+* INPUT: -+* ETH_QUEUE_CTRL *pEthPortCtrl Ethernet Port Control srtuct. -+* int rxQueue Number of Rx queue. -+* int rxDescNum Number of Rx descriptors -+* MV_U8* rxDescBaseAddr Rx descriptors memory area base addr. -+* -+* OUTPUT: -+* The routine updates the Ethernet port control struct with information -+* regarding the Rx descriptors and buffers. -+* -+* RETURN: None -+* -+*******************************************************************************/ -+static void ethInitRxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue) -+{ -+ ETH_RX_DESC *pRxDescBase, *pRxDesc, *pRxPrevDesc; -+ int ix, rxDescNum = pPortCtrl->rxQueueConfig[queue].descrNum; -+ ETH_QUEUE_CTRL *pQueueCtrl = &pPortCtrl->rxQueue[queue]; -+ -+ /* Make sure descriptor address is cache line size aligned */ -+ pRxDescBase = (ETH_RX_DESC*)MV_ALIGN_UP((MV_ULONG)pQueueCtrl->descBuf.bufVirtPtr, -+ CPU_D_CACHE_LINE_SIZE); -+ -+ pRxDesc = (ETH_RX_DESC*)pRxDescBase; -+ pRxPrevDesc = pRxDesc; -+ -+ /* initialize the Rx descriptors ring */ -+ for (ix=0; ixbufSize = 0x0; -+ pRxDesc->byteCnt = 0x0; -+ pRxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; -+ pRxDesc->bufPtr = 0x0; -+ pRxDesc->returnInfo = 0x0; -+ pRxPrevDesc = pRxDesc; -+ if(ix == (rxDescNum-1)) -+ { -+ /* Closing Rx descriptors ring */ -+ pRxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pRxDescBase); -+ } -+ else -+ { -+ pRxDesc = (ETH_RX_DESC*)((MV_ULONG)pRxDesc + ETH_RX_DESC_ALIGNED_SIZE); -+ pRxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pRxDesc); -+ } -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxPrevDesc); -+ } -+ -+ pQueueCtrl->pCurrentDescr = pRxDescBase; -+ pQueueCtrl->pUsedDescr = pRxDescBase; -+ -+ pQueueCtrl->pFirstDescr = pRxDescBase; -+ pQueueCtrl->pLastDescr = pRxDesc; -+ pQueueCtrl->resource = 0; -+} -+ -+void ethResetRxDescRing(void* pPortHndl, int queue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->rxQueue[queue]; -+ ETH_RX_DESC* pRxDesc = (ETH_RX_DESC*)pQueueCtrl->pFirstDescr; -+ -+ pQueueCtrl->resource = 0; -+ if(pQueueCtrl->pFirstDescr != NULL) -+ { -+ while(MV_TRUE) -+ { -+ pRxDesc->bufSize = 0x0; -+ pRxDesc->byteCnt = 0x0; -+ pRxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; -+ pRxDesc->bufPtr = 0x0; -+ pRxDesc->returnInfo = 0x0; -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxDesc); -+ if( (void*)pRxDesc == pQueueCtrl->pLastDescr) -+ break; -+ pRxDesc = RX_NEXT_DESC_PTR(pRxDesc, pQueueCtrl); -+ } -+ pQueueCtrl->pCurrentDescr = pQueueCtrl->pFirstDescr; -+ pQueueCtrl->pUsedDescr = pQueueCtrl->pFirstDescr; -+ -+ /* Update RX Command register */ -+ pPortCtrl->portRxQueueCmdReg |= (1 << queue); -+ -+ /* update HW */ -+ MV_REG_WRITE( ETH_RX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), -+ (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); -+ } -+ else -+ { -+ /* Update RX Command register */ -+ pPortCtrl->portRxQueueCmdReg &= ~(1 << queue); -+ -+ /* update HW */ -+ MV_REG_WRITE( ETH_RX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), 0); -+ } -+} -+ -+/******************************************************************************* -+* etherInitTxDescRing - Curve a Tx chain desc list and buffer in memory. -+* -+* DESCRIPTION: -+* This function prepares a Tx chained list of descriptors and packet -+* buffers in a form of a ring. The routine must be called after port -+* initialization routine and before port start routine. -+* The Ethernet SDMA engine uses CPU bus addresses to access the various -+* devices in the system (i.e. DRAM). This function uses the ethernet -+* struct 'virtual to physical' routine (set by the user) to set the ring -+* with physical addresses. -+* -+* INPUT: -+* ETH_PORT_CTRL *pEthPortCtrl Ethernet Port Control srtuct. -+* int txQueue Number of Tx queue. -+* int txDescNum Number of Tx descriptors -+* int txBuffSize Size of Tx buffer -+* MV_U8* pTxDescBase Tx descriptors memory area base addr. -+* -+* OUTPUT: -+* The routine updates the Ethernet port control struct with information -+* regarding the Tx descriptors and buffers. -+* -+* RETURN: None. -+* -+*******************************************************************************/ -+static void ethInitTxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue) -+{ -+ ETH_TX_DESC *pTxDescBase, *pTxDesc, *pTxPrevDesc; -+ int ix, txDescNum = pPortCtrl->txQueueConfig[queue].descrNum; -+ ETH_QUEUE_CTRL *pQueueCtrl = &pPortCtrl->txQueue[queue]; -+ -+ /* Make sure descriptor address is cache line size aligned */ -+ pTxDescBase = (ETH_TX_DESC*)MV_ALIGN_UP((MV_ULONG)pQueueCtrl->descBuf.bufVirtPtr, -+ CPU_D_CACHE_LINE_SIZE); -+ -+ pTxDesc = (ETH_TX_DESC*)pTxDescBase; -+ pTxPrevDesc = pTxDesc; -+ -+ /* initialize the Tx descriptors ring */ -+ for (ix=0; ixbyteCnt = 0x0000; -+ pTxDesc->L4iChk = 0x0000; -+ pTxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; -+ pTxDesc->bufPtr = 0x0; -+ pTxDesc->returnInfo = 0x0; -+ -+ pTxPrevDesc = pTxDesc; -+ -+ if(ix == (txDescNum-1)) -+ { -+ /* Closing Tx descriptors ring */ -+ pTxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pTxDescBase); -+ } -+ else -+ { -+ pTxDesc = (ETH_TX_DESC*)((MV_ULONG)pTxDesc + ETH_TX_DESC_ALIGNED_SIZE); -+ pTxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pTxDesc); -+ } -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxPrevDesc); -+ } -+ -+ pQueueCtrl->pCurrentDescr = pTxDescBase; -+ pQueueCtrl->pUsedDescr = pTxDescBase; -+ -+ pQueueCtrl->pFirstDescr = pTxDescBase; -+ pQueueCtrl->pLastDescr = pTxDesc; -+ /* Leave one TX descriptor out of use */ -+ pQueueCtrl->resource = txDescNum - 1; -+} -+ -+void ethResetTxDescRing(void* pPortHndl, int queue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->txQueue[queue]; -+ ETH_TX_DESC* pTxDesc = (ETH_TX_DESC*)pQueueCtrl->pFirstDescr; -+ -+ pQueueCtrl->resource = 0; -+ if(pQueueCtrl->pFirstDescr != NULL) -+ { -+ while(MV_TRUE) -+ { -+ pTxDesc->byteCnt = 0x0000; -+ pTxDesc->L4iChk = 0x0000; -+ pTxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; -+ pTxDesc->bufPtr = 0x0; -+ pTxDesc->returnInfo = 0x0; -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxDesc); -+ pQueueCtrl->resource++; -+ if( (void*)pTxDesc == pQueueCtrl->pLastDescr) -+ break; -+ pTxDesc = TX_NEXT_DESC_PTR(pTxDesc, pQueueCtrl); -+ } -+ /* Leave one TX descriptor out of use */ -+ pQueueCtrl->resource--; -+ pQueueCtrl->pCurrentDescr = pQueueCtrl->pFirstDescr; -+ pQueueCtrl->pUsedDescr = pQueueCtrl->pFirstDescr; -+ -+ /* Update TX Command register */ -+ pPortCtrl->portTxQueueCmdReg |= MV_32BIT_LE_FAST(1 << queue); -+ /* update HW */ -+ MV_REG_WRITE( ETH_TX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), -+ (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); -+ } -+ else -+ { -+ /* Update TX Command register */ -+ pPortCtrl->portTxQueueCmdReg &= MV_32BIT_LE_FAST(~(1 << queue)); -+ /* update HW */ -+ MV_REG_WRITE( ETH_TX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), 0 ); -+ } -+} -+ -+/******************************************************************************* -+* ethAllocDescrMemory - Free memory allocated for RX and TX descriptors. -+* -+* DESCRIPTION: -+* This function allocates memory for RX and TX descriptors. -+* - If ETH_DESCR_IN_SRAM defined, allocate memory from SRAM. -+* - If ETH_DESCR_IN_SDRAM defined, allocate memory in SDRAM. -+* -+* INPUT: -+* int size - size of memory should be allocated. -+* -+* RETURN: None -+* -+*******************************************************************************/ -+static MV_U8* ethAllocDescrMemory(ETH_PORT_CTRL* pPortCtrl, int descSize, -+ MV_ULONG* pPhysAddr, MV_U32 *memHandle) -+{ -+ MV_U8* pVirt; -+ -+#if defined(ETH_DESCR_IN_SRAM) -+ if(ethDescInSram == MV_TRUE) -+ pVirt = (char*)mvSramMalloc(descSize, pPhysAddr); -+ else -+#endif /* ETH_DESCR_IN_SRAM */ -+ { -+#ifdef ETH_DESCR_UNCACHED -+ pVirt = (MV_U8*)mvOsIoUncachedMalloc(pPortCtrl->osHandle, descSize, -+ pPhysAddr,memHandle); -+#else -+ pVirt = (MV_U8*)mvOsIoCachedMalloc(pPortCtrl->osHandle, descSize, -+ pPhysAddr, memHandle); -+#endif /* ETH_DESCR_UNCACHED */ -+ } -+ memset(pVirt, 0, descSize); -+ -+ return pVirt; -+} -+ -+/******************************************************************************* -+* ethFreeDescrMemory - Free memory allocated for RX and TX descriptors. -+* -+* DESCRIPTION: -+* This function frees memory allocated for RX and TX descriptors. -+* - If ETH_DESCR_IN_SRAM defined, free memory using gtSramFree() function. -+* - If ETH_DESCR_IN_SDRAM defined, free memory using mvOsFree() function. -+* -+* INPUT: -+* void* pVirtAddr - virtual pointer to memory allocated for RX and TX -+* desriptors. -+* -+* RETURN: None -+* -+*******************************************************************************/ -+void ethFreeDescrMemory(ETH_PORT_CTRL* pPortCtrl, MV_BUF_INFO* pDescBuf) -+{ -+ if( (pDescBuf == NULL) || (pDescBuf->bufVirtPtr == NULL) ) -+ return; -+ -+#if defined(ETH_DESCR_IN_SRAM) -+ if( ethDescInSram ) -+ { -+ mvSramFree(pDescBuf->bufSize, pDescBuf->bufPhysAddr, pDescBuf->bufVirtPtr); -+ return; -+ } -+#endif /* ETH_DESCR_IN_SRAM */ -+ -+#ifdef ETH_DESCR_UNCACHED -+ mvOsIoUncachedFree(pPortCtrl->osHandle, pDescBuf->bufSize, pDescBuf->bufPhysAddr, -+ pDescBuf->bufVirtPtr,pDescBuf->memHandle); -+#else -+ mvOsIoCachedFree(pPortCtrl->osHandle, pDescBuf->bufSize, pDescBuf->bufPhysAddr, -+ pDescBuf->bufVirtPtr,pDescBuf->memHandle); -+#endif /* ETH_DESCR_UNCACHED */ -+} -+ -+/******************************************************************************/ -+/* Other Functions */ -+/******************************************************************************/ -+ -+void mvEthPortPowerUp(int port) -+{ -+ MV_U32 regVal; -+ -+ /* MAC Cause register should be cleared */ -+ MV_REG_WRITE(ETH_UNIT_INTR_CAUSE_REG(port), 0); -+ -+ if (mvBoardIsPortInSgmii(port)) -+ mvEthPortSgmiiConfig(port); -+ -+ /* Cancel Port Reset */ -+ regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)); -+ regVal &= (~ETH_PORT_RESET_MASK); -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal); -+ while( (MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)) & ETH_PORT_RESET_MASK) != 0); -+} -+ -+void mvEthPortPowerDown(int port) -+{ -+ MV_U32 regVal; -+ -+ /* Port must be DISABLED */ -+ regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port)); -+ if( (regVal & ETH_PORT_ENABLE_MASK) != 0) -+ { -+ mvOsPrintf("ethPort #%d: PowerDown - port must be Disabled (PSC=0x%x)\n", -+ port, regVal); -+ return; -+ } -+ -+ /* Port Reset (Read after write the register as a precaution) */ -+ regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)); -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal | ETH_PORT_RESET_MASK); -+ while((MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)) & ETH_PORT_RESET_MASK) == 0); -+} -+ -+static void mvEthPortSgmiiConfig(int port) -+{ -+ MV_U32 regVal; -+ -+ regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)); -+ -+ regVal |= (ETH_SGMII_MODE_MASK /*| ETH_INBAND_AUTO_NEG_ENABLE_MASK */); -+ regVal &= (~ETH_INBAND_AUTO_NEG_BYPASS_MASK); -+ -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal); -+} -+ -+ -+ -+ -+ -+ -+ -+ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c 2010-11-09 20:28:11.072495491 +0100 -@@ -0,0 +1,748 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+/******************************************************************************* -+* mvEthDebug.c - Source file for user friendly debug functions -+* -+* DESCRIPTION: -+* -+* DEPENDENCIES: -+* None. -+* -+*******************************************************************************/ -+ -+#include "mvOs.h" -+#include "mvCommon.h" -+#include "mvTypes.h" -+#include "mv802_3.h" -+#include "mvDebug.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "eth-phy/mvEthPhy.h" -+#include "eth/mvEth.h" -+#include "eth/gbe/mvEthDebug.h" -+ -+/* #define mvOsPrintf printf */ -+ -+void mvEthPortShow(void* pHndl); -+void mvEthQueuesShow(void* pHndl, int rxQueue, int txQueue, int mode); -+ -+/******************************************************************************/ -+/* Debug functions */ -+/******************************************************************************/ -+void ethRxCoal(int port, int usec) -+{ -+ void* pHndl; -+ -+ pHndl = mvEthPortHndlGet(port); -+ if(pHndl != NULL) -+ { -+ mvEthRxCoalSet(pHndl, usec); -+ } -+} -+ -+void ethTxCoal(int port, int usec) -+{ -+ void* pHndl; -+ -+ pHndl = mvEthPortHndlGet(port); -+ if(pHndl != NULL) -+ { -+ mvEthTxCoalSet(pHndl, usec); -+ } -+} -+ -+#if (MV_ETH_VERSION >= 4) -+void ethEjpModeSet(int port, int mode) -+{ -+ void* pHndl; -+ -+ pHndl = mvEthPortHndlGet(port); -+ if(pHndl != NULL) -+ { -+ mvEthEjpModeSet(pHndl, mode); -+ } -+} -+#endif /* (MV_ETH_VERSION >= 4) */ -+ -+void ethBpduRxQ(int port, int bpduQueue) -+{ -+ void* pHndl; -+ -+ pHndl = mvEthPortHndlGet(port); -+ if(pHndl != NULL) -+ { -+ mvEthBpduRxQueue(pHndl, bpduQueue); -+ } -+} -+ -+void ethArpRxQ(int port, int arpQueue) -+{ -+ void* pHndl; -+ -+ pHndl = mvEthPortHndlGet(port); -+ if(pHndl != NULL) -+ { -+ mvEthArpRxQueue(pHndl, arpQueue); -+ } -+} -+ -+void ethTcpRxQ(int port, int tcpQueue) -+{ -+ void* pHndl; -+ -+ pHndl = mvEthPortHndlGet(port); -+ if(pHndl != NULL) -+ { -+ mvEthTcpRxQueue(pHndl, tcpQueue); -+ } -+} -+ -+void ethUdpRxQ(int port, int udpQueue) -+{ -+ void* pHndl; -+ -+ pHndl = mvEthPortHndlGet(port); -+ if(pHndl != NULL) -+ { -+ mvEthUdpRxQueue(pHndl, udpQueue); -+ } -+} -+ -+void ethTxPolicyRegs(int port) -+{ -+ int queue; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)mvEthPortHndlGet(port); -+ -+ if(pPortCtrl == NULL) -+ { -+ return; -+ } -+ mvOsPrintf("Port #%d TX Policy: EJP=%d, TXQs: ", -+ port, pPortCtrl->portConfig.ejpMode); -+ for(queue=0; queuetxQueueConfig[queue].descrNum > 0) -+ mvOsPrintf("%d, ", queue); -+ } -+ mvOsPrintf("\n"); -+ -+ mvOsPrintf("\n\t TX policy Port #%d configuration registers\n", port); -+ -+ mvOsPrintf("ETH_TX_QUEUE_COMMAND_REG : 0x%X = 0x%08x\n", -+ ETH_TX_QUEUE_COMMAND_REG(port), -+ MV_REG_READ( ETH_TX_QUEUE_COMMAND_REG(port) ) ); -+ -+ mvOsPrintf("ETH_TX_FIXED_PRIO_CFG_REG : 0x%X = 0x%08x\n", -+ ETH_TX_FIXED_PRIO_CFG_REG(port), -+ MV_REG_READ( ETH_TX_FIXED_PRIO_CFG_REG(port) ) ); -+ -+ mvOsPrintf("ETH_TX_TOKEN_RATE_CFG_REG : 0x%X = 0x%08x\n", -+ ETH_TX_TOKEN_RATE_CFG_REG(port), -+ MV_REG_READ( ETH_TX_TOKEN_RATE_CFG_REG(port) ) ); -+ -+ mvOsPrintf("ETH_MAX_TRANSMIT_UNIT_REG : 0x%X = 0x%08x\n", -+ ETH_MAX_TRANSMIT_UNIT_REG(port), -+ MV_REG_READ( ETH_MAX_TRANSMIT_UNIT_REG(port) ) ); -+ -+ mvOsPrintf("ETH_TX_TOKEN_BUCKET_SIZE_REG : 0x%X = 0x%08x\n", -+ ETH_TX_TOKEN_BUCKET_SIZE_REG(port), -+ MV_REG_READ( ETH_TX_TOKEN_BUCKET_SIZE_REG(port) ) ); -+ -+ mvOsPrintf("ETH_TX_TOKEN_BUCKET_COUNT_REG : 0x%X = 0x%08x\n", -+ ETH_TX_TOKEN_BUCKET_COUNT_REG(port), -+ MV_REG_READ( ETH_TX_TOKEN_BUCKET_COUNT_REG(port) ) ); -+ -+ for(queue=0; queue> 24) & 0xff), ((macH >> 16) & 0xff), -+ ((macH >> 8) & 0xff), (macH & 0xff), -+ ((macL >> 8) & 0xff), (macL & 0xff) ); -+ -+ for (i=0; i<4; i++) -+ { -+ unicastReg = MV_REG_READ( (ETH_DA_FILTER_UCAST_BASE(port) + i*4)); -+ for(j=0; j<4; j++) -+ { -+ MV_U8 macEntry = (unicastReg >> (8*j)) & 0xFF; -+ -+ mvOsPrintf("%X: %8s, Q = %d\n", i*4+j, -+ (macEntry & BIT0) ? "Accept" : "Reject", (macEntry >> 1) & 0x7); -+ } -+ } -+} -+ -+void ethMcastAdd(int port, char* macStr, int queue) -+{ -+ void* pHndl; -+ MV_U8 macAddr[MV_MAC_ADDR_SIZE]; -+ -+ pHndl = mvEthPortHndlGet(port); -+ if(pHndl != NULL) -+ { -+ mvMacStrToHex(macStr, macAddr); -+ mvEthMcastAddrSet(pHndl, macAddr, queue); -+ } -+} -+ -+void ethPortMcast(int port) -+{ -+ int tblIdx, regIdx; -+ MV_U32 regVal; -+ -+ mvOsPrintf("\n\t Port #%d Special (IP) Multicast table: 01:00:5E:00:00:XX\n\n", -+ port); -+ -+ for(tblIdx=0; tblIdx<(256/4); tblIdx++) -+ { -+ regVal = MV_REG_READ((ETH_DA_FILTER_SPEC_MCAST_BASE(port) + tblIdx*4)); -+ for(regIdx=0; regIdx<4; regIdx++) -+ { -+ if((regVal & (0x01 << (regIdx*8))) != 0) -+ { -+ mvOsPrintf("0x%02X: Accepted, rxQ = %d\n", -+ tblIdx*4+regIdx, ((regVal >> (regIdx*8+1)) & 0x07)); -+ } -+ } -+ } -+ mvOsPrintf("\n\t Port #%d Other Multicast table\n\n", port); -+ for(tblIdx=0; tblIdx<(256/4); tblIdx++) -+ { -+ regVal = MV_REG_READ((ETH_DA_FILTER_OTH_MCAST_BASE(port) + tblIdx*4)); -+ for(regIdx=0; regIdx<4; regIdx++) -+ { -+ if((regVal & (0x01 << (regIdx*8))) != 0) -+ { -+ mvOsPrintf("Crc8=0x%02X: Accepted, rxQ = %d\n", -+ tblIdx*4+regIdx, ((regVal >> (regIdx*8+1)) & 0x07)); -+ } -+ } -+ } -+} -+ -+ -+/* Print status of Ethernet port */ -+void mvEthPortShow(void* pHndl) -+{ -+ MV_U32 regValue, rxCoal, txCoal; -+ int speed, queue, port; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pHndl; -+ -+ port = pPortCtrl->portNo; -+ -+ regValue = MV_REG_READ( ETH_PORT_STATUS_REG(port) ); -+ -+ mvOsPrintf("\n\t ethGiga #%d port Status: 0x%04x = 0x%08x\n\n", -+ port, ETH_PORT_STATUS_REG(port), regValue); -+ -+ mvOsPrintf("descInSram=%d, descSwCoher=%d\n", -+ ethDescInSram, ethDescSwCoher); -+ -+ if(regValue & ETH_GMII_SPEED_1000_MASK) -+ speed = 1000; -+ else if(regValue & ETH_MII_SPEED_100_MASK) -+ speed = 100; -+ else -+ speed = 10; -+ -+ mvEthCoalGet(pPortCtrl, &rxCoal, &txCoal); -+ -+ /* Link, Speed, Duplex, FlowControl */ -+ mvOsPrintf("Link=%s, Speed=%d, Duplex=%s, RxFlowControl=%s", -+ (regValue & ETH_LINK_UP_MASK) ? "UP" : "DOWN", -+ speed, -+ (regValue & ETH_FULL_DUPLEX_MASK) ? "FULL" : "HALF", -+ (regValue & ETH_ENABLE_RCV_FLOW_CTRL_MASK) ? "ENABLE" : "DISABLE"); -+ -+ mvOsPrintf("\n"); -+ -+ mvOsPrintf("RxCoal = %d usec, TxCoal = %d usec\n", -+ rxCoal, txCoal); -+ -+ mvOsPrintf("rxDefQ=%d, arpQ=%d, bpduQ=%d, tcpQ=%d, udpQ=%d\n\n", -+ pPortCtrl->portConfig.rxDefQ, pPortCtrl->portConfig.rxArpQ, -+ pPortCtrl->portConfig.rxBpduQ, -+ pPortCtrl->portConfig.rxTcpQ, pPortCtrl->portConfig.rxUdpQ); -+ -+ /* Print all RX and TX queues */ -+ for(queue=0; queuerxQueue[queue].pFirstDescr, -+ mvEthRxResourceGet(pPortCtrl, queue) ); -+ } -+ mvOsPrintf("\n"); -+ for(queue=0; queuetxQueue[queue].pFirstDescr, -+ mvEthTxResourceGet(pPortCtrl, queue) ); -+ } -+} -+ -+/* Print RX and TX queue of the Ethernet port */ -+void mvEthQueuesShow(void* pHndl, int rxQueue, int txQueue, int mode) -+{ -+ ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL*)pHndl; -+ ETH_QUEUE_CTRL *pQueueCtrl; -+ MV_U32 regValue; -+ ETH_RX_DESC *pRxDescr; -+ ETH_TX_DESC *pTxDescr; -+ int i, port = pPortCtrl->portNo; -+ -+ if( (rxQueue >=0) && (rxQueue < MV_ETH_RX_Q_NUM) ) -+ { -+ pQueueCtrl = &(pPortCtrl->rxQueue[rxQueue]); -+ mvOsPrintf("Port #%d, RX Queue #%d\n\n", port, rxQueue); -+ -+ mvOsPrintf("CURR_RX_DESC_PTR : 0x%X = 0x%08x\n", -+ ETH_RX_CUR_DESC_PTR_REG(port, rxQueue), -+ MV_REG_READ( ETH_RX_CUR_DESC_PTR_REG(port, rxQueue))); -+ -+ -+ if(pQueueCtrl->pFirstDescr != NULL) -+ { -+ mvOsPrintf("pFirstDescr=0x%lx, pLastDescr=0x%lx, numOfResources=%d\n", -+ (MV_ULONG)pQueueCtrl->pFirstDescr, (MV_ULONG)pQueueCtrl->pLastDescr, -+ pQueueCtrl->resource); -+ mvOsPrintf("pCurrDescr: 0x%lx, pUsedDescr: 0x%lx\n", -+ (MV_ULONG)pQueueCtrl->pCurrentDescr, -+ (MV_ULONG)pQueueCtrl->pUsedDescr); -+ -+ if(mode == 1) -+ { -+ pRxDescr = (ETH_RX_DESC*)pQueueCtrl->pFirstDescr; -+ i = 0; -+ do -+ { -+ mvOsPrintf("%3d. desc=%08x (%08x), cmd=%08x, data=%4d, buf=%4d, buf=%08x, pkt=%lx, os=%lx\n", -+ i, (MV_U32)pRxDescr, (MV_U32)ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pRxDescr), -+ pRxDescr->cmdSts, pRxDescr->byteCnt, (MV_U32)pRxDescr->bufSize, -+ (unsigned int)pRxDescr->bufPtr, (MV_ULONG)pRxDescr->returnInfo, -+ ((MV_PKT_INFO*)pRxDescr->returnInfo)->osInfo); -+ -+ ETH_DESCR_INV(pPortCtrl, pRxDescr); -+ pRxDescr = RX_NEXT_DESC_PTR(pRxDescr, pQueueCtrl); -+ i++; -+ } while (pRxDescr != pQueueCtrl->pFirstDescr); -+ } -+ } -+ else -+ mvOsPrintf("RX Queue #%d is NOT CREATED\n", rxQueue); -+ } -+ -+ if( (txQueue >=0) && (txQueue < MV_ETH_TX_Q_NUM) ) -+ { -+ pQueueCtrl = &(pPortCtrl->txQueue[txQueue]); -+ mvOsPrintf("Port #%d, TX Queue #%d\n\n", port, txQueue); -+ -+ regValue = MV_REG_READ( ETH_TX_CUR_DESC_PTR_REG(port, txQueue)); -+ mvOsPrintf("CURR_TX_DESC_PTR : 0x%X = 0x%08x\n", -+ ETH_TX_CUR_DESC_PTR_REG(port, txQueue), regValue); -+ -+ if(pQueueCtrl->pFirstDescr != NULL) -+ { -+ mvOsPrintf("pFirstDescr=0x%lx, pLastDescr=0x%lx, numOfResources=%d\n", -+ (MV_ULONG)pQueueCtrl->pFirstDescr, -+ (MV_ULONG)pQueueCtrl->pLastDescr, -+ pQueueCtrl->resource); -+ mvOsPrintf("pCurrDescr: 0x%lx, pUsedDescr: 0x%lx\n", -+ (MV_ULONG)pQueueCtrl->pCurrentDescr, -+ (MV_ULONG)pQueueCtrl->pUsedDescr); -+ -+ if(mode == 1) -+ { -+ pTxDescr = (ETH_TX_DESC*)pQueueCtrl->pFirstDescr; -+ i = 0; -+ do -+ { -+ mvOsPrintf("%3d. desc=%08x (%08x), cmd=%08x, data=%4d, buf=%08x, pkt=%lx, os=%lx\n", -+ i, (MV_U32)pTxDescr, (MV_U32)ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pTxDescr), -+ pTxDescr->cmdSts, pTxDescr->byteCnt, -+ (MV_U32)pTxDescr->bufPtr, (MV_ULONG)pTxDescr->returnInfo, -+ pTxDescr->returnInfo ? (((MV_PKT_INFO*)pTxDescr->returnInfo)->osInfo) : 0x0); -+ -+ ETH_DESCR_INV(pPortCtrl, pTxDescr); -+ pTxDescr = TX_NEXT_DESC_PTR(pTxDescr, pQueueCtrl); -+ i++; -+ } while (pTxDescr != pQueueCtrl->pFirstDescr); -+ } -+ } -+ else -+ mvOsPrintf("TX Queue #%d is NOT CREATED\n", txQueue); -+ } -+} -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.h 2010-11-09 20:28:11.112495471 +0100 -@@ -0,0 +1,146 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#ifndef __MV_ETH_DEBUG_H__ -+#define __MV_ETH_DEBUG_H__ -+ -+#if 0 -+/* -+ ** Externs -+ */ -+void ethBpduRxQ(int port, int bpduQueue); -+void ethArpRxQ(int port, int bpduQueue); -+void ethTcpRxQ(int port, int bpduQueue); -+void ethUdpRxQ(int port, int bpduQueue); -+void ethMcastAdd(int port, char* macStr, int queue); -+ -+#ifdef INCLUDE_MULTI_QUEUE -+void ethRxPolicy( int port); -+void ethTxPolicy( int port); -+void ethTxPolDA(int port, char* macStr, int txQ, char* headerHexStr); -+void ethRxPolMode(int port, MV_ETH_PRIO_MODE prioMode); -+void ethRxPolQ(int port, int rxQueue, int rxQuota); -+#endif /* INCLUDE_MULTI_QUEUE */ -+ -+void print_egiga_stat(void *sc, unsigned int port); -+void ethPortStatus (int port); -+void ethPortQueues( int port, int rxQueue, int txQueue, int mode); -+void ethPortMcast(int port); -+void ethPortRegs(int port); -+void ethPortCounters(int port); -+void ethPortRmonCounters(int port); -+void ethRxCoal(int port, int usec); -+void ethTxCoal(int port, int usec); -+ -+void ethRegs(int port); -+void ethClearCounters(int port); -+void ethUcastSet(int port, char* macStr, int queue); -+void ethPortUcastShow(int port); -+ -+#ifdef CONFIG_MV_ETH_HEADER -+void run_com_header(const char *buffer); -+#endif -+ -+#ifdef INCLUDE_MULTI_QUEUE -+void ethRxPolMode(int port, MV_ETH_PRIO_MODE prioMode); -+void ethRxPolQ(int port, int queue, int quota); -+void ethRxPolicy(int port); -+void ethTxPolDef(int port, int txQ, char* headerHexStr); -+void ethTxPolDA(int port, char* macStr, int txQ, char* headerHexStr); -+void ethTxPolicy(int port); -+#endif /* INCLUDE_MULTI_QUEUE */ -+ -+#if (MV_ETH_VERSION >= 4) -+void ethEjpModeSet(int port, int mode) -+#endif -+#endif /* 0 */ -+ -+ -+ -+ -+void ethRxCoal(int port, int usec); -+void ethTxCoal(int port, int usec); -+#if (MV_ETH_VERSION >= 4) -+void ethEjpModeSet(int port, int mode); -+#endif /* (MV_ETH_VERSION >= 4) */ -+ -+void ethBpduRxQ(int port, int bpduQueue); -+void ethArpRxQ(int port, int arpQueue); -+void ethTcpRxQ(int port, int tcpQueue); -+void ethUdpRxQ(int port, int udpQueue); -+void ethTxPolicyRegs(int port); -+void ethPortRegs(int port); -+void ethRegs(int port); -+void ethClearCounters(int port); -+void ethPortCounters(int port); -+void ethPortRmonCounters(int port); -+void ethPortStatus(int port); -+void ethPortQueues(int port, int rxQueue, int txQueue, int mode); -+void ethUcastSet(int port, char* macStr, int queue); -+void ethPortUcastShow(int port); -+void ethMcastAdd(int port, char* macStr, int queue); -+void ethPortMcast(int port); -+void mvEthPortShow(void* pHndl); -+void mvEthQueuesShow(void* pHndl, int rxQueue, int txQueue, int mode); -+ -+#endif -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthGbe.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthGbe.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthGbe.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthGbe.h 2010-11-09 20:28:11.152495442 +0100 -@@ -0,0 +1,751 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+/******************************************************************************* -+* mvEth.h - Header File for : Marvell Gigabit Ethernet Controller -+* -+* DESCRIPTION: -+* This header file contains macros typedefs and function declaration specific to -+* the Marvell Gigabit Ethernet Controller. -+* -+* DEPENDENCIES: -+* None. -+* -+*******************************************************************************/ -+ -+#ifndef __mvEthGbe_h__ -+#define __mvEthGbe_h__ -+ -+extern MV_BOOL ethDescInSram; -+extern MV_BOOL ethDescSwCoher; -+extern ETH_PORT_CTRL* ethPortCtrl[]; -+ -+static INLINE MV_ULONG ethDescVirtToPhy(ETH_QUEUE_CTRL* pQueueCtrl, MV_U8* pDesc) -+{ -+#if defined (ETH_DESCR_IN_SRAM) -+ if( ethDescInSram ) -+ return mvSramVirtToPhy(pDesc); -+ else -+#endif /* ETH_DESCR_IN_SRAM */ -+ return (pQueueCtrl->descBuf.bufPhysAddr + (pDesc - pQueueCtrl->descBuf.bufVirtPtr)); -+} -+/* Return port handler */ -+#define mvEthPortHndlGet(port) ethPortCtrl[port] -+ -+/* Used as WA for HW/SW race on TX */ -+static INLINE int mvEthPortTxEnable(void* pPortHndl, int queue, int max_deep) -+{ -+ int deep = 0; -+ MV_U32 txCurrReg, txEnReg; -+ ETH_TX_DESC* pTxLastDesc; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ -+ txEnReg = MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)); -+ if( (txEnReg & MV_32BIT_LE_FAST(ETH_TXQ_ENABLE_MASK)) == 0) -+ { -+ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) = pPortCtrl->portTxQueueCmdReg; -+ return 0; -+ } -+ -+ pQueueCtrl = &pPortCtrl->txQueue[queue]; -+ pTxLastDesc = pQueueCtrl->pCurrentDescr; -+ txCurrReg = MV_REG_READ(ETH_TX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue)); -+ if(ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pTxLastDesc) == txCurrReg) -+ { -+ /* All descriptors are processed, no chance for race */ -+ return 0; -+ } -+ -+ /* Check distance betwee HW and SW location: */ -+ /* If distance between HW and SW pointers is less than max_deep descriptors */ -+ /* Race condition is possible, so wait end of TX and restart TXQ */ -+ while(deep < max_deep) -+ { -+ pTxLastDesc = TX_PREV_DESC_PTR(pTxLastDesc, pQueueCtrl); -+ if(ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pTxLastDesc) == txCurrReg) -+ { -+ int count = 0; -+ -+ while( (txEnReg & MV_32BIT_LE_FAST(ETH_TXQ_ENABLE_MASK)) != 0) -+ { -+ count++; -+ if(count > 10000) -+ { -+ mvOsPrintf("mvEthPortTxEnable: timeout - TXQ_CMD=0x%08x\n", -+ MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) ); -+ break; -+ } -+ txEnReg = MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)); -+ } -+ -+ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) = pPortCtrl->portTxQueueCmdReg; -+ return count; -+ } -+ deep++; -+ } -+ /* Distance between HW and SW pointers is more than max_deep descriptors, */ -+ /* So NO race condition - do nothing */ -+ return -1; -+} -+ -+ -+/* defines */ -+#define ETH_CSUM_MIN_BYTE_COUNT 72 -+ -+/* Tailgate and Kirwood have only 2K TX FIFO */ -+#if (MV_ETH_VERSION == 2) || (MV_ETH_VERSION == 4) -+#define ETH_CSUM_MAX_BYTE_COUNT 1600 -+#else -+#define ETH_CSUM_MAX_BYTE_COUNT 9*1024 -+#endif /* MV_ETH_VERSION */ -+ -+#define ETH_MV_HEADER_SIZE 2 -+#define ETH_MV_TX_EN -+ -+/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */ -+#define MIN_TX_BUFF_LOAD 8 -+#define TX_BUF_OFFSET_IN_DESC (ETH_TX_DESC_ALIGNED_SIZE - MIN_TX_BUFF_LOAD) -+ -+/* Default port configuration value */ -+#define PORT_CONFIG_VALUE \ -+ ETH_DEF_RX_QUEUE_MASK(0) | \ -+ ETH_DEF_RX_ARP_QUEUE_MASK(0) | \ -+ ETH_DEF_RX_TCP_QUEUE_MASK(0) | \ -+ ETH_DEF_RX_UDP_QUEUE_MASK(0) | \ -+ ETH_DEF_RX_BPDU_QUEUE_MASK(0) | \ -+ ETH_RX_CHECKSUM_WITH_PSEUDO_HDR -+ -+/* Default port extend configuration value */ -+#define PORT_CONFIG_EXTEND_VALUE 0 -+ -+#define PORT_SERIAL_CONTROL_VALUE \ -+ ETH_DISABLE_FC_AUTO_NEG_MASK | \ -+ BIT9 | \ -+ ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ -+ ETH_MAX_RX_PACKET_1552BYTE | \ -+ ETH_SET_FULL_DUPLEX_MASK -+ -+#define PORT_SERIAL_CONTROL_100MB_FORCE_VALUE \ -+ ETH_FORCE_LINK_PASS_MASK | \ -+ ETH_DISABLE_DUPLEX_AUTO_NEG_MASK | \ -+ ETH_DISABLE_FC_AUTO_NEG_MASK | \ -+ BIT9 | \ -+ ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ -+ ETH_DISABLE_SPEED_AUTO_NEG_MASK | \ -+ ETH_SET_FULL_DUPLEX_MASK | \ -+ ETH_SET_MII_SPEED_100_MASK | \ -+ ETH_MAX_RX_PACKET_1552BYTE -+ -+ -+#define PORT_SERIAL_CONTROL_1000MB_FORCE_VALUE \ -+ ETH_FORCE_LINK_PASS_MASK | \ -+ ETH_DISABLE_DUPLEX_AUTO_NEG_MASK | \ -+ ETH_DISABLE_FC_AUTO_NEG_MASK | \ -+ BIT9 | \ -+ ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ -+ ETH_DISABLE_SPEED_AUTO_NEG_MASK | \ -+ ETH_SET_FULL_DUPLEX_MASK | \ -+ ETH_SET_GMII_SPEED_1000_MASK | \ -+ ETH_MAX_RX_PACKET_1552BYTE -+ -+#define PORT_SERIAL_CONTROL_SGMII_IBAN_VALUE \ -+ ETH_DISABLE_FC_AUTO_NEG_MASK | \ -+ BIT9 | \ -+ ETH_IN_BAND_AN_EN_MASK | \ -+ ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ -+ ETH_MAX_RX_PACKET_1552BYTE -+ -+/* Function headers: */ -+MV_VOID mvEthSetSpecialMcastTable(int portNo, int queue); -+MV_STATUS mvEthArpRxQueue(void* pPortHandle, int arpQueue); -+MV_STATUS mvEthUdpRxQueue(void* pPortHandle, int udpQueue); -+MV_STATUS mvEthTcpRxQueue(void* pPortHandle, int tcpQueue); -+MV_STATUS mvEthMacAddrGet(int portNo, unsigned char *pAddr); -+MV_VOID mvEthSetOtherMcastTable(int portNo, int queue); -+MV_STATUS mvEthHeaderModeSet(void* pPortHandle, MV_ETH_HEADER_MODE headerMode); -+/* Interrupt Coalesting functions */ -+MV_U32 mvEthRxCoalSet(void* pPortHndl, MV_U32 uSec); -+MV_U32 mvEthTxCoalSet(void* pPortHndl, MV_U32 uSec); -+MV_STATUS mvEthCoalGet(void* pPortHndl, MV_U32* pRxCoal, MV_U32* pTxCoal); -+ -+/******************************************************************************/ -+/* Data Flow functions */ -+/******************************************************************************/ -+static INLINE void mvEthPortTxRestart(void* pPortHndl) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ -+ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) = pPortCtrl->portTxQueueCmdReg; -+} -+ -+/* Get number of Free resources in specific TX queue */ -+static INLINE int mvEthTxResourceGet(void* pPortHndl, int txQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ -+ return (pPortCtrl->txQueue[txQueue].resource); -+} -+ -+/* Get number of Free resources in specific RX queue */ -+static INLINE int mvEthRxResourceGet(void* pPortHndl, int rxQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ -+ return (pPortCtrl->rxQueue[rxQueue].resource); -+} -+ -+static INLINE int mvEthTxQueueIsFull(void* pPortHndl, int txQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ -+ if(pPortCtrl->txQueue[txQueue].resource == 0) -+ return MV_TRUE; -+ -+ return MV_FALSE; -+} -+ -+/* Get number of Free resources in specific RX queue */ -+static INLINE int mvEthRxQueueIsFull(void* pPortHndl, int rxQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->rxQueue[rxQueue]; -+ -+ if( (pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) && -+ (pQueueCtrl->resource != 0) ) -+ return MV_TRUE; -+ -+ return MV_FALSE; -+} -+ -+static INLINE int mvEthTxQueueIsEmpty(void* pPortHndl, int txQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->txQueue[txQueue]; -+ -+ if( (pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) && -+ (pQueueCtrl->resource != 0) ) -+ { -+ return MV_TRUE; -+ } -+ return MV_FALSE; -+} -+ -+/* Get number of Free resources in specific RX queue */ -+static INLINE int mvEthRxQueueIsEmpty(void* pPortHndl, int rxQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ -+ if(pPortCtrl->rxQueue[rxQueue].resource == 0) -+ return MV_TRUE; -+ -+ return MV_FALSE; -+} -+ -+/******************************************************************************* -+* mvEthPortTx - Send an Ethernet packet -+* -+* DESCRIPTION: -+* This routine send a given packet described by pPktInfo parameter. -+* Single buffer only. -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet Port handler. -+* int txQueue - Number of Tx queue. -+* MV_PKT_INFO *pPktInfo - User packet to send. -+* -+* RETURN: -+* MV_NO_RESOURCE - No enough resources to send this packet. -+* MV_ERROR - Unexpected Fatal error. -+* MV_OK - Packet send successfully. -+* -+*******************************************************************************/ -+static INLINE MV_STATUS mvEthPortTx(void* pEthPortHndl, int txQueue, MV_PKT_INFO* pPktInfo) -+{ -+ ETH_TX_DESC* pTxCurrDesc; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ int portNo; -+ MV_BUF_INFO* pBufInfo = pPktInfo->pFrags; -+ -+#ifdef ETH_DEBUG -+ if(pPortCtrl->portState != MV_ACTIVE) -+ return MV_BAD_STATE; -+#endif /* ETH_DEBUG */ -+ -+ portNo = pPortCtrl->portNo; -+ pQueueCtrl = &pPortCtrl->txQueue[txQueue]; -+ -+ /* Get the Tx Desc ring indexes */ -+ pTxCurrDesc = pQueueCtrl->pCurrentDescr; -+ -+ /* Check if there is enough resources to send the packet */ -+ if(pQueueCtrl->resource == 0) -+ return MV_NO_RESOURCE; -+ -+ pTxCurrDesc->byteCnt = pBufInfo->dataSize; -+ -+ /* Flash Buffer */ -+ if(pPktInfo->pktSize != 0) -+ { -+#ifdef MV_NETBSD -+ pTxCurrDesc->bufPtr = pBufInfo->bufPhysAddr; -+ ETH_PACKET_CACHE_FLUSH(pBufInfo->bufVirtPtr, pPktInfo->pktSize); -+#else -+ pTxCurrDesc->bufPtr = ETH_PACKET_CACHE_FLUSH(pBufInfo->bufVirtPtr, pPktInfo->pktSize); -+#endif -+ pPktInfo->pktSize = 0; -+ } -+ else -+ pTxCurrDesc->bufPtr = pBufInfo->bufPhysAddr; -+ -+ pTxCurrDesc->returnInfo = (MV_ULONG)pPktInfo; -+ -+ /* There is only one buffer in the packet */ -+ /* The OSG might set some bits for checksum offload, so add them to first descriptor */ -+ pTxCurrDesc->cmdSts = pPktInfo->status | -+ ETH_BUFFER_OWNED_BY_DMA | -+ ETH_TX_GENERATE_CRC_MASK | -+ ETH_TX_ENABLE_INTERRUPT_MASK | -+ ETH_TX_ZERO_PADDING_MASK | -+ ETH_TX_FIRST_DESC_MASK | -+ ETH_TX_LAST_DESC_MASK; -+ -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); -+ -+ pQueueCtrl->resource--; -+ pQueueCtrl->pCurrentDescr = TX_NEXT_DESC_PTR(pTxCurrDesc, pQueueCtrl); -+ -+ /* Apply send command */ -+ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(portNo)) = pPortCtrl->portTxQueueCmdReg; -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvEthPortSgTx - Send an Ethernet packet -+* -+* DESCRIPTION: -+* This routine send a given packet described by pBufInfo parameter. It -+* supports transmitting of a packet spaned over multiple buffers. -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet Port handler. -+* int txQueue - Number of Tx queue. -+* MV_PKT_INFO *pPktInfo - User packet to send. -+* -+* RETURN: -+* MV_NO_RESOURCE - No enough resources to send this packet. -+* MV_ERROR - Unexpected Fatal error. -+* MV_OK - Packet send successfully. -+* -+*******************************************************************************/ -+static INLINE MV_STATUS mvEthPortSgTx(void* pEthPortHndl, int txQueue, MV_PKT_INFO* pPktInfo) -+{ -+ ETH_TX_DESC* pTxFirstDesc; -+ ETH_TX_DESC* pTxCurrDesc; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ int portNo, bufCount; -+ MV_BUF_INFO* pBufInfo = pPktInfo->pFrags; -+ MV_U8* pTxBuf; -+ -+#ifdef ETH_DEBUG -+ if(pPortCtrl->portState != MV_ACTIVE) -+ return MV_BAD_STATE; -+#endif /* ETH_DEBUG */ -+ -+ portNo = pPortCtrl->portNo; -+ pQueueCtrl = &pPortCtrl->txQueue[txQueue]; -+ -+ /* Get the Tx Desc ring indexes */ -+ pTxCurrDesc = pQueueCtrl->pCurrentDescr; -+ -+ /* Check if there is enough resources to send the packet */ -+ if(pQueueCtrl->resource < pPktInfo->numFrags) -+ return MV_NO_RESOURCE; -+ -+ /* Remember first desc */ -+ pTxFirstDesc = pTxCurrDesc; -+ -+ bufCount = 0; -+ while(MV_TRUE) -+ { -+ if(pBufInfo[bufCount].dataSize <= MIN_TX_BUFF_LOAD) -+ { -+ /* Buffers with a payload smaller than MIN_TX_BUFF_LOAD (8 bytes) must be aligned */ -+ /* to 64-bit boundary. Two options here: */ -+ /* 1) Usually, copy the payload to the reserved 8 bytes inside descriptor. */ -+ /* 2) In the Half duplex workaround, the reserved 8 bytes inside descriptor are used */ -+ /* as a pointer to the aligned buffer, copy the small payload to this buffer. */ -+ pTxBuf = ((MV_U8*)pTxCurrDesc)+TX_BUF_OFFSET_IN_DESC; -+ mvOsBCopy(pBufInfo[bufCount].bufVirtPtr, pTxBuf, pBufInfo[bufCount].dataSize); -+ pTxCurrDesc->bufPtr = ethDescVirtToPhy(pQueueCtrl, pTxBuf); -+ } -+ else -+ { -+ /* Flash Buffer */ -+#ifdef MV_NETBSD -+ pTxCurrDesc->bufPtr = pBufInfo[bufCount].bufPhysAddr; -+ ETH_PACKET_CACHE_FLUSH(pBufInfo[bufCount].bufVirtPtr, pBufInfo[bufCount].dataSize); -+#else -+ pTxCurrDesc->bufPtr = ETH_PACKET_CACHE_FLUSH(pBufInfo[bufCount].bufVirtPtr, pBufInfo[bufCount].dataSize); -+#endif -+ } -+ -+ pTxCurrDesc->byteCnt = pBufInfo[bufCount].dataSize; -+ bufCount++; -+ -+ if(bufCount >= pPktInfo->numFrags) -+ break; -+ -+ if(bufCount > 1) -+ { -+ /* There is middle buffer of the packet Not First and Not Last */ -+ pTxCurrDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA; -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); -+ } -+ /* Go to next descriptor and next buffer */ -+ pTxCurrDesc = TX_NEXT_DESC_PTR(pTxCurrDesc, pQueueCtrl); -+ } -+ /* Set last desc with DMA ownership and interrupt enable. */ -+ pTxCurrDesc->returnInfo = (MV_ULONG)pPktInfo; -+ if(bufCount == 1) -+ { -+ /* There is only one buffer in the packet */ -+ /* The OSG might set some bits for checksum offload, so add them to first descriptor */ -+ pTxCurrDesc->cmdSts = pPktInfo->status | -+ ETH_BUFFER_OWNED_BY_DMA | -+ ETH_TX_GENERATE_CRC_MASK | -+ ETH_TX_ENABLE_INTERRUPT_MASK | -+ ETH_TX_ZERO_PADDING_MASK | -+ ETH_TX_FIRST_DESC_MASK | -+ ETH_TX_LAST_DESC_MASK; -+ -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); -+ } -+ else -+ { -+ /* Last but not First */ -+ pTxCurrDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA | -+ ETH_TX_ENABLE_INTERRUPT_MASK | -+ ETH_TX_ZERO_PADDING_MASK | -+ ETH_TX_LAST_DESC_MASK; -+ -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); -+ -+ /* Update First when more than one buffer in the packet */ -+ /* The OSG might set some bits for checksum offload, so add them to first descriptor */ -+ pTxFirstDesc->cmdSts = pPktInfo->status | -+ ETH_BUFFER_OWNED_BY_DMA | -+ ETH_TX_GENERATE_CRC_MASK | -+ ETH_TX_FIRST_DESC_MASK; -+ -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxFirstDesc); -+ } -+ /* Update txQueue state */ -+ pQueueCtrl->resource -= bufCount; -+ pQueueCtrl->pCurrentDescr = TX_NEXT_DESC_PTR(pTxCurrDesc, pQueueCtrl); -+ -+ /* Apply send command */ -+ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(portNo)) = pPortCtrl->portTxQueueCmdReg; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthPortTxDone - Free all used Tx descriptors and mBlks. -+* -+* DESCRIPTION: -+* This routine returns the transmitted packet information to the caller. -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet Port handler. -+* int txQueue - Number of Tx queue. -+* -+* OUTPUT: -+* MV_PKT_INFO *pPktInfo - Pointer to packet was sent. -+* -+* RETURN: -+* MV_NOT_FOUND - No transmitted packets to return. Transmit in progress. -+* MV_EMPTY - No transmitted packets to return. TX Queue is empty. -+* MV_ERROR - Unexpected Fatal error. -+* MV_OK - There is transmitted packet in the queue, -+* 'pPktInfo' filled with relevant information. -+* -+*******************************************************************************/ -+static INLINE MV_PKT_INFO* mvEthPortTxDone(void* pEthPortHndl, int txQueue) -+{ -+ ETH_TX_DESC* pTxCurrDesc; -+ ETH_TX_DESC* pTxUsedDesc; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ MV_PKT_INFO* pPktInfo; -+ MV_U32 commandStatus; -+ -+ pQueueCtrl = &pPortCtrl->txQueue[txQueue]; -+ -+ pTxUsedDesc = pQueueCtrl->pUsedDescr; -+ pTxCurrDesc = pQueueCtrl->pCurrentDescr; -+ -+ while(MV_TRUE) -+ { -+ /* No more used descriptors */ -+ commandStatus = pTxUsedDesc->cmdSts; -+ if (commandStatus & (ETH_BUFFER_OWNED_BY_DMA)) -+ { -+ ETH_DESCR_INV(pPortCtrl, pTxUsedDesc); -+ return NULL; -+ } -+ if( (pTxUsedDesc == pTxCurrDesc) && -+ (pQueueCtrl->resource != 0) ) -+ { -+ return NULL; -+ } -+ pQueueCtrl->resource++; -+ pQueueCtrl->pUsedDescr = TX_NEXT_DESC_PTR(pTxUsedDesc, pQueueCtrl); -+ if(commandStatus & (ETH_TX_LAST_DESC_MASK)) -+ { -+ pPktInfo = (MV_PKT_INFO*)pTxUsedDesc->returnInfo; -+ pPktInfo->status = commandStatus; -+ return pPktInfo; -+ } -+ pTxUsedDesc = pQueueCtrl->pUsedDescr; -+ } -+} -+ -+/******************************************************************************* -+* mvEthPortRx - Get new received packets from Rx queue. -+* -+* DESCRIPTION: -+* This routine returns the received data to the caller. There is no -+* data copying during routine operation. All information is returned -+* using pointer to packet information struct passed from the caller. -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet Port handler. -+* int rxQueue - Number of Rx queue. -+* -+* OUTPUT: -+* MV_PKT_INFO *pPktInfo - Pointer to received packet. -+* -+* RETURN: -+* MV_NO_RESOURCE - No free resources in RX queue. -+* MV_ERROR - Unexpected Fatal error. -+* MV_OK - New packet received and 'pBufInfo' structure filled -+* with relevant information. -+* -+*******************************************************************************/ -+static INLINE MV_PKT_INFO* mvEthPortRx(void* pEthPortHndl, int rxQueue) -+{ -+ ETH_RX_DESC *pRxCurrDesc; -+ MV_U32 commandStatus; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ MV_PKT_INFO* pPktInfo; -+ -+ pQueueCtrl = &(pPortCtrl->rxQueue[rxQueue]); -+ -+ /* Check resources */ -+ if(pQueueCtrl->resource == 0) -+ { -+ mvOsPrintf("ethPortRx: no more resources\n"); -+ return NULL; -+ } -+ while(MV_TRUE) -+ { -+ /* Get the Rx Desc ring 'curr and 'used' indexes */ -+ pRxCurrDesc = pQueueCtrl->pCurrentDescr; -+ -+ commandStatus = pRxCurrDesc->cmdSts; -+ if (commandStatus & (ETH_BUFFER_OWNED_BY_DMA)) -+ { -+ /* Nothing to receive... */ -+ ETH_DESCR_INV(pPortCtrl, pRxCurrDesc); -+ return NULL; -+ } -+ -+ /* Valid RX only if FIRST and LAST bits are set */ -+ if( (commandStatus & (ETH_RX_LAST_DESC_MASK | ETH_RX_FIRST_DESC_MASK)) == -+ (ETH_RX_LAST_DESC_MASK | ETH_RX_FIRST_DESC_MASK) ) -+ { -+ pPktInfo = (MV_PKT_INFO*)pRxCurrDesc->returnInfo; -+ pPktInfo->pFrags->dataSize = pRxCurrDesc->byteCnt - 4; -+ pPktInfo->status = commandStatus; -+ pPktInfo->fragIP = pRxCurrDesc->bufSize & ETH_RX_IP_FRAGMENTED_FRAME_MASK; -+ -+ pQueueCtrl->resource--; -+ /* Update 'curr' in data structure */ -+ pQueueCtrl->pCurrentDescr = RX_NEXT_DESC_PTR(pRxCurrDesc, pQueueCtrl); -+ -+#ifdef INCLUDE_SYNC_BARR -+ mvCpuIfSyncBarr(DRAM_TARGET); -+#endif -+ return pPktInfo; -+ } -+ else -+ { -+ ETH_RX_DESC* pRxUsedDesc = pQueueCtrl->pUsedDescr; -+ -+#ifdef ETH_DEBUG -+ mvOsPrintf("ethDrv: Unexpected Jumbo frame: " -+ "status=0x%08x, byteCnt=%d, pData=0x%x\n", -+ commandStatus, pRxCurrDesc->byteCnt, pRxCurrDesc->bufPtr); -+#endif /* ETH_DEBUG */ -+ -+ /* move buffer from pCurrentDescr position to pUsedDescr position */ -+ pRxUsedDesc->bufPtr = pRxCurrDesc->bufPtr; -+ pRxUsedDesc->returnInfo = pRxCurrDesc->returnInfo; -+ pRxUsedDesc->bufSize = pRxCurrDesc->bufSize & ETH_RX_BUFFER_MASK; -+ -+ /* Return the descriptor to DMA ownership */ -+ pRxUsedDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA | -+ ETH_RX_ENABLE_INTERRUPT_MASK; -+ -+ /* Flush descriptor and CPU pipe */ -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxUsedDesc); -+ -+ /* Move the used descriptor pointer to the next descriptor */ -+ pQueueCtrl->pUsedDescr = RX_NEXT_DESC_PTR(pRxUsedDesc, pQueueCtrl); -+ pQueueCtrl->pCurrentDescr = RX_NEXT_DESC_PTR(pRxCurrDesc, pQueueCtrl); -+ } -+ } -+} -+ -+/******************************************************************************* -+* mvEthPortRxDone - Returns a Rx buffer back to the Rx ring. -+* -+* DESCRIPTION: -+* This routine returns a Rx buffer back to the Rx ring. -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet Port handler. -+* int rxQueue - Number of Rx queue. -+* MV_PKT_INFO *pPktInfo - Pointer to received packet. -+* -+* RETURN: -+* MV_ERROR - Unexpected Fatal error. -+* MV_OUT_OF_RANGE - RX queue is already FULL, so this buffer can't be -+* returned to this queue. -+* MV_FULL - Buffer returned successfully and RX queue became full. -+* More buffers should not be returned at the time. -+* MV_OK - Buffer returned successfully and there are more free -+* places in the queue. -+* -+*******************************************************************************/ -+static INLINE MV_STATUS mvEthPortRxDone(void* pEthPortHndl, int rxQueue, MV_PKT_INFO *pPktInfo) -+{ -+ ETH_RX_DESC* pRxUsedDesc; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ -+ pQueueCtrl = &pPortCtrl->rxQueue[rxQueue]; -+ -+ /* Get 'used' Rx descriptor */ -+ pRxUsedDesc = pQueueCtrl->pUsedDescr; -+ -+ /* Check that ring is not FULL */ -+ if( (pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) && -+ (pQueueCtrl->resource != 0) ) -+ { -+ mvOsPrintf("%s %d: out of range Error resource=%d, curr=%p, used=%p\n", -+ __FUNCTION__, pPortCtrl->portNo, pQueueCtrl->resource, -+ pQueueCtrl->pCurrentDescr, pQueueCtrl->pUsedDescr); -+ return MV_OUT_OF_RANGE; -+ } -+ -+ pRxUsedDesc->bufPtr = pPktInfo->pFrags->bufPhysAddr; -+ pRxUsedDesc->returnInfo = (MV_ULONG)pPktInfo; -+ pRxUsedDesc->bufSize = pPktInfo->pFrags->bufSize & ETH_RX_BUFFER_MASK; -+ -+ /* Invalidate data buffer accordingly with pktSize */ -+ if(pPktInfo->pktSize != 0) -+ { -+ ETH_PACKET_CACHE_INVALIDATE(pPktInfo->pFrags->bufVirtPtr, pPktInfo->pktSize); -+ pPktInfo->pktSize = 0; -+ } -+ -+ /* Return the descriptor to DMA ownership */ -+ pRxUsedDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT_MASK; -+ -+ /* Flush descriptor and CPU pipe */ -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxUsedDesc); -+ -+ pQueueCtrl->resource++; -+ -+ /* Move the used descriptor pointer to the next descriptor */ -+ pQueueCtrl->pUsedDescr = RX_NEXT_DESC_PTR(pRxUsedDesc, pQueueCtrl); -+ -+ /* If ring became Full return MV_FULL */ -+ if(pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) -+ return MV_FULL; -+ -+ return MV_OK; -+} -+ -+ -+#endif /* __mvEthGbe_h__ */ -+ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h 2010-11-09 20:28:11.192495435 +0100 -@@ -0,0 +1,700 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvEthRegsh -+#define __INCmvEthRegsh -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+ -+/****************************************/ -+/* Ethernet Unit Registers */ -+/****************************************/ -+#define ETH_REG_BASE MV_ETH_REG_BASE -+ -+#define ETH_PHY_ADDR_REG(port) (ETH_REG_BASE(port) + 0x000) -+#define ETH_SMI_REG(port) (ETH_REG_BASE(port) + 0x004) -+#define ETH_UNIT_DEF_ADDR_REG(port) (ETH_REG_BASE(port) + 0x008) -+#define ETH_UNIT_DEF_ID_REG(port) (ETH_REG_BASE(port) + 0x00c) -+#define ETH_UNIT_RESERVED(port) (ETH_REG_BASE(port) + 0x014) -+#define ETH_UNIT_INTR_CAUSE_REG(port) (ETH_REG_BASE(port) + 0x080) -+#define ETH_UNIT_INTR_MASK_REG(port) (ETH_REG_BASE(port) + 0x084) -+ -+ -+#define ETH_UNIT_ERROR_ADDR_REG(port) (ETH_REG_BASE(port) + 0x094) -+#define ETH_UNIT_INT_ADDR_ERROR_REG(port) (ETH_REG_BASE(port) + 0x098) -+#define ETH_UNIT_CONTROL_REG(port) (ETH_REG_BASE(port) + 0x0B0) -+ -+#define ETH_PORT_CONFIG_REG(port) (ETH_REG_BASE(port) + 0x400) -+#define ETH_PORT_CONFIG_EXTEND_REG(port) (ETH_REG_BASE(port) + 0x404) -+#define ETH_MII_SERIAL_PARAM_REG(port) (ETH_REG_BASE(port) + 0x408) -+#define ETH_GMII_SERIAL_PARAM_REG(port) (ETH_REG_BASE(port) + 0x40c) -+#define ETH_VLAN_ETHER_TYPE_REG(port) (ETH_REG_BASE(port) + 0x410) -+#define ETH_MAC_ADDR_LOW_REG(port) (ETH_REG_BASE(port) + 0x414) -+#define ETH_MAC_ADDR_HIGH_REG(port) (ETH_REG_BASE(port) + 0x418) -+#define ETH_SDMA_CONFIG_REG(port) (ETH_REG_BASE(port) + 0x41c) -+#define ETH_DIFF_SERV_PRIO_REG(port, code) (ETH_REG_BASE(port) + 0x420 + ((code)<<2)) -+#define ETH_PORT_SERIAL_CTRL_REG(port) (ETH_REG_BASE(port) + 0x43c) -+#define ETH_VLAN_TAG_TO_PRIO_REG(port) (ETH_REG_BASE(port) + 0x440) -+#define ETH_PORT_STATUS_REG(port) (ETH_REG_BASE(port) + 0x444) -+ -+#define ETH_RX_QUEUE_COMMAND_REG(port) (ETH_REG_BASE(port) + 0x680) -+#define ETH_TX_QUEUE_COMMAND_REG(port) (ETH_REG_BASE(port) + 0x448) -+ -+#define ETH_PORT_SERIAL_CTRL_1_REG(port) (ETH_REG_BASE(port) + 0x44c) -+#define ETH_PORT_STATUS_1_REG(port) (ETH_REG_BASE(port) + 0x450) -+#define ETH_PORT_MARVELL_HEADER_REG(port) (ETH_REG_BASE(port) + 0x454) -+#define ETH_PORT_FIFO_PARAMS_REG(port) (ETH_REG_BASE(port) + 0x458) -+#define ETH_MAX_TOKEN_BUCKET_SIZE_REG(port) (ETH_REG_BASE(port) + 0x45c) -+#define ETH_INTR_CAUSE_REG(port) (ETH_REG_BASE(port) + 0x460) -+#define ETH_INTR_CAUSE_EXT_REG(port) (ETH_REG_BASE(port) + 0x464) -+#define ETH_INTR_MASK_REG(port) (ETH_REG_BASE(port) + 0x468) -+#define ETH_INTR_MASK_EXT_REG(port) (ETH_REG_BASE(port) + 0x46c) -+#define ETH_TX_FIFO_URGENT_THRESH_REG(port) (ETH_REG_BASE(port) + 0x474) -+#define ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (ETH_REG_BASE(port) + 0x47c) -+#define ETH_RX_DISCARD_PKTS_CNTR_REG(port) (ETH_REG_BASE(port) + 0x484) -+#define ETH_RX_OVERRUN_PKTS_CNTR_REG(port) (ETH_REG_BASE(port) + 0x488) -+#define ETH_INTERNAL_ADDR_ERROR_REG(port) (ETH_REG_BASE(port) + 0x494) -+#define ETH_TX_FIXED_PRIO_CFG_REG(port) (ETH_REG_BASE(port) + 0x4dc) -+#define ETH_TX_TOKEN_RATE_CFG_REG(port) (ETH_REG_BASE(port) + 0x4e0) -+#define ETH_TX_QUEUE_COMMAND1_REG(port) (ETH_REG_BASE(port) + 0x4e4) -+#define ETH_MAX_TRANSMIT_UNIT_REG(port) (ETH_REG_BASE(port) + 0x4e8) -+#define ETH_TX_TOKEN_BUCKET_SIZE_REG(port) (ETH_REG_BASE(port) + 0x4ec) -+#define ETH_TX_TOKEN_BUCKET_COUNT_REG(port) (ETH_REG_BASE(port) + 0x780) -+#define ETH_RX_DESCR_STAT_CMD_REG(port, q) (ETH_REG_BASE(port) + 0x600 + ((q)<<4)) -+#define ETH_RX_BYTE_COUNT_REG(port, q) (ETH_REG_BASE(port) + 0x604 + ((q)<<4)) -+#define ETH_RX_BUF_PTR_REG(port, q) (ETH_REG_BASE(port) + 0x608 + ((q)<<4)) -+#define ETH_RX_CUR_DESC_PTR_REG(port, q) (ETH_REG_BASE(port) + 0x60c + ((q)<<4)) -+#define ETH_TX_CUR_DESC_PTR_REG(port, q) (ETH_REG_BASE(port) + 0x6c0 + ((q)<<2)) -+ -+#define ETH_TXQ_TOKEN_COUNT_REG(port, q) (ETH_REG_BASE(port) + 0x700 + ((q)<<4)) -+#define ETH_TXQ_TOKEN_CFG_REG(port, q) (ETH_REG_BASE(port) + 0x704 + ((q)<<4)) -+#define ETH_TXQ_ARBITER_CFG_REG(port, q) (ETH_REG_BASE(port) + 0x708 + ((q)<<4)) -+ -+#if (MV_ETH_VERSION >= 4) -+#define ETH_TXQ_CMD_1_REG(port) (ETH_REG_BASE(port) + 0x4E4) -+#define ETH_EJP_TX_HI_IPG_REG(port) (ETH_REG_BASE(port) + 0x7A8) -+#define ETH_EJP_TX_LO_IPG_REG(port) (ETH_REG_BASE(port) + 0x7B8) -+#define ETH_EJP_HI_TKN_LO_PKT_REG(port) (ETH_REG_BASE(port) + 0x7C0) -+#define ETH_EJP_HI_TKN_ASYNC_PKT_REG(port) (ETH_REG_BASE(port) + 0x7C4) -+#define ETH_EJP_LO_TKN_ASYNC_PKT_REG(port) (ETH_REG_BASE(port) + 0x7C8) -+#define ETH_EJP_TX_SPEED_REG(port) (ETH_REG_BASE(port) + 0x7D0) -+#endif /* MV_ETH_VERSION >= 4 */ -+ -+#define ETH_MIB_COUNTERS_BASE(port) (ETH_REG_BASE(port) + 0x1000) -+#define ETH_DA_FILTER_SPEC_MCAST_BASE(port) (ETH_REG_BASE(port) + 0x1400) -+#define ETH_DA_FILTER_OTH_MCAST_BASE(port) (ETH_REG_BASE(port) + 0x1500) -+#define ETH_DA_FILTER_UCAST_BASE(port) (ETH_REG_BASE(port) + 0x1600) -+ -+/* Phy address register definitions */ -+#define ETH_PHY_ADDR_OFFS 0 -+#define ETH_PHY_ADDR_MASK (0x1f <= 4) -+#define ETH_TX_EJP_RESET_BIT 0 -+#define ETH_TX_EJP_RESET_MASK (1 << ETH_TX_EJP_RESET_BIT) -+ -+#define ETH_TX_EJP_ENABLE_BIT 2 -+#define ETH_TX_EJP_ENABLE_MASK (1 << ETH_TX_EJP_ENABLE_BIT) -+ -+#define ETH_TX_LEGACY_WRR_BIT 3 -+#define ETH_TX_LEGACY_WRR_MASK (1 << ETH_TX_LEGACY_WRR_BIT) -+#endif /* (MV_ETH_VERSION >= 4) */ -+ -+/***** BITs of Ethernet Port Status reg (PSR) *****/ -+#define ETH_LINK_UP_BIT 1 -+#define ETH_LINK_UP_MASK (1<= 4) -+MV_STATUS mvEthEjpModeSet(void* pPortHandle, int mode); -+#endif /* (MV_ETH_VERSION >= 4) */ -+ -+void mvEthStatusGet(void* pPortHandle, MV_ETH_PORT_STATUS* pStatus); -+ -+/* Marvell Header control */ -+MV_STATUS mvEthHeaderModeSet(void* pPortHandle, MV_ETH_HEADER_MODE headerMode); -+ -+/* PHY routines */ -+void mvEthPhyAddrSet(void* pPortHandle, int phyAddr); -+int mvEthPhyAddrGet(void* pPortHandle); -+ -+/* Power management routines */ -+void mvEthPortPowerDown(int port); -+void mvEthPortPowerUp(int port); -+ -+/******************** ETH PRIVATE ************************/ -+ -+/*#define UNCACHED_TX_BUFFERS*/ -+/*#define UNCACHED_RX_BUFFERS*/ -+ -+ -+/* Port attributes */ -+/* Size of a Tx/Rx descriptor used in chain list data structure */ -+#define ETH_RX_DESC_ALIGNED_SIZE 32 -+#define ETH_TX_DESC_ALIGNED_SIZE 32 -+ -+#define TX_DISABLE_TIMEOUT_MSEC 1000 -+#define RX_DISABLE_TIMEOUT_MSEC 1000 -+#define TX_FIFO_EMPTY_TIMEOUT_MSEC 10000 -+#define PORT_DISABLE_WAIT_TCLOCKS 5000 -+ -+/* Macros that save access to desc in order to find next desc pointer */ -+#define RX_NEXT_DESC_PTR(pRxDescr, pQueueCtrl) \ -+ ((pRxDescr) == (pQueueCtrl)->pLastDescr) ? \ -+ (ETH_RX_DESC*)((pQueueCtrl)->pFirstDescr) : \ -+ (ETH_RX_DESC*)(((MV_ULONG)(pRxDescr)) + ETH_RX_DESC_ALIGNED_SIZE) -+ -+#define TX_NEXT_DESC_PTR(pTxDescr, pQueueCtrl) \ -+ ((pTxDescr) == (pQueueCtrl)->pLastDescr) ? \ -+ (ETH_TX_DESC*)((pQueueCtrl)->pFirstDescr) : \ -+ (ETH_TX_DESC*)(((MV_ULONG)(pTxDescr)) + ETH_TX_DESC_ALIGNED_SIZE) -+ -+#define RX_PREV_DESC_PTR(pRxDescr, pQueueCtrl) \ -+ ((pRxDescr) == (pQueueCtrl)->pFirstDescr) ? \ -+ (ETH_RX_DESC*)((pQueueCtrl)->pLastDescr) : \ -+ (ETH_RX_DESC*)(((MV_ULONG)(pRxDescr)) - ETH_RX_DESC_ALIGNED_SIZE) -+ -+#define TX_PREV_DESC_PTR(pTxDescr, pQueueCtrl) \ -+ ((pTxDescr) == (pQueueCtrl)->pFirstDescr) ? \ -+ (ETH_TX_DESC*)((pQueueCtrl)->pLastDescr) : \ -+ (ETH_TX_DESC*)(((MV_ULONG)(pTxDescr)) - ETH_TX_DESC_ALIGNED_SIZE) -+ -+ -+/* Queue specific information */ -+typedef struct -+{ -+ void* pFirstDescr; -+ void* pLastDescr; -+ void* pCurrentDescr; -+ void* pUsedDescr; -+ int resource; -+ MV_BUF_INFO descBuf; -+} ETH_QUEUE_CTRL; -+ -+ -+/* Ethernet port specific infomation */ -+typedef struct _ethPortCtrl -+{ -+ int portNo; -+ ETH_QUEUE_CTRL rxQueue[MV_ETH_RX_Q_NUM]; /* Rx ring resource */ -+ ETH_QUEUE_CTRL txQueue[MV_ETH_TX_Q_NUM]; /* Tx ring resource */ -+ -+ MV_ETH_PORT_CFG portConfig; -+ MV_ETH_RX_Q_CFG rxQueueConfig[MV_ETH_RX_Q_NUM]; -+ MV_ETH_TX_Q_CFG txQueueConfig[MV_ETH_TX_Q_NUM]; -+ -+ /* Register images - For DP */ -+ MV_U32 portTxQueueCmdReg; /* Port active Tx queues summary */ -+ MV_U32 portRxQueueCmdReg; /* Port active Rx queues summary */ -+ -+ MV_STATE portState; -+ -+ MV_U8 mcastCount[256]; -+ MV_U32* hashPtr; -+ void *osHandle; -+} ETH_PORT_CTRL; -+ -+/************** MACROs ****************/ -+ -+/* MACROs to Flush / Invalidate TX / RX Buffers */ -+#if (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) && !defined(UNCACHED_TX_BUFFERS) -+# define ETH_PACKET_CACHE_FLUSH(pAddr, size) \ -+ mvOsCacheClear(NULL, (pAddr), (size)); \ -+ /*CPU_PIPE_FLUSH;*/ -+#else -+# define ETH_PACKET_CACHE_FLUSH(pAddr, size) \ -+ mvOsIoVirtToPhy(NULL, (pAddr)); -+#endif /* ETHER_DRAM_COHER == MV_CACHE_COHER_SW */ -+ -+#if ( (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) && !defined(UNCACHED_RX_BUFFERS) ) -+# define ETH_PACKET_CACHE_INVALIDATE(pAddr, size) \ -+ mvOsCacheInvalidate (NULL, (pAddr), (size)); \ -+ /*CPU_PIPE_FLUSH;*/ -+#else -+# define ETH_PACKET_CACHE_INVALIDATE(pAddr, size) -+#endif /* ETHER_DRAM_COHER == MV_CACHE_COHER_SW && !UNCACHED_RX_BUFFERS */ -+ -+#ifdef ETH_DESCR_UNCACHED -+ -+#define ETH_DESCR_FLUSH_INV(pPortCtrl, pDescr) -+#define ETH_DESCR_INV(pPortCtrl, pDescr) -+ -+#else -+ -+#define ETH_DESCR_FLUSH_INV(pPortCtrl, pDescr) \ -+ mvOsCacheLineFlushInv(pPortCtrl->osHandle, (MV_ULONG)(pDescr)) -+ -+#define ETH_DESCR_INV(pPortCtrl, pDescr) \ -+ mvOsCacheLineInv(pPortCtrl->osHandle, (MV_ULONG)(pDescr)) -+ -+#endif /* ETH_DESCR_UNCACHED */ -+ -+#include "eth/gbe/mvEthGbe.h" -+ -+#endif /* __mvEth_h__ */ -+ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.c 2010-11-09 20:28:11.262495582 +0100 -@@ -0,0 +1,362 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "gpp/mvGpp.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+static MV_VOID gppRegSet(MV_U32 group, MV_U32 regOffs,MV_U32 mask,MV_U32 value); -+ -+/******************************************************************************* -+* mvGppTypeSet - Enable a GPP (OUT) pin -+* -+* DESCRIPTION: -+* -+* INPUT: -+* group - GPP group number -+* mask - 32bit mask value. Each set bit in the mask means that the type -+* of corresponding GPP will be set. Other GPPs are ignored. -+* value - 32bit value that describes GPP type per pin. -+* -+* OUTPUT: -+* None. -+* -+* EXAMPLE: -+* Set GPP8 to input and GPP15 to output. -+* mvGppTypeSet(0, (GPP8 | GPP15), -+* ((MV_GPP_IN & GPP8) | (MV_GPP_OUT & GPP15)) ); -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvGppTypeSet(MV_U32 group, MV_U32 mask, MV_U32 value) -+{ -+ if (group >= MV_GPP_MAX_GROUP) -+ { -+ DB(mvOsPrintf("mvGppTypeSet: ERR. invalid group number \n")); -+ return MV_BAD_PARAM; -+ } -+ -+ gppRegSet(group, GPP_DATA_OUT_EN_REG(group), mask, value); -+ -+ /* Workaround for Erratum FE-MISC-70*/ -+ if(mvCtrlRevGet()==MV_88F6XXX_A0_REV && (group == 1)) -+ { -+ mask &= 0x2; -+ gppRegSet(0, GPP_DATA_OUT_EN_REG(0), mask, value); -+ } /*End of WA*/ -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvGppBlinkEn - Set a GPP (IN) Pin list to blink every ~100ms -+* -+* DESCRIPTION: -+* -+* INPUT: -+* group - GPP group number -+* mask - 32bit mask value. Each set bit in the mask means that the type -+* of corresponding GPP will be set. Other GPPs are ignored. -+* value - 32bit value that describes GPP blink per pin. -+* -+* OUTPUT: -+* None. -+* -+* EXAMPLE: -+* Set GPP8 to be static and GPP15 to be blinking. -+* mvGppBlinkEn(0, (GPP8 | GPP15), -+* ((MV_GPP_OUT_STATIC & GPP8) | (MV_GPP_OUT_BLINK & GPP15)) ); -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvGppBlinkEn(MV_U32 group, MV_U32 mask, MV_U32 value) -+{ -+ if (group >= MV_GPP_MAX_GROUP) -+ { -+ DB(mvOsPrintf("mvGppBlinkEn: ERR. invalid group number \n")); -+ return MV_BAD_PARAM; -+ } -+ -+ gppRegSet(group, GPP_BLINK_EN_REG(group), mask, value); -+ -+ return MV_OK; -+ -+} -+/******************************************************************************* -+* mvGppPolaritySet - Set a GPP (IN) Pin list Polarity mode -+* -+* DESCRIPTION: -+* -+* INPUT: -+* group - GPP group number -+* mask - 32bit mask value. Each set bit in the mask means that the type -+* of corresponding GPP will be set. Other GPPs are ignored. -+* value - 32bit value that describes GPP polarity per pin. -+* -+* OUTPUT: -+* None. -+* -+* EXAMPLE: -+* Set GPP8 to the actual pin value and GPP15 to be inverted. -+* mvGppPolaritySet(0, (GPP8 | GPP15), -+* ((MV_GPP_IN_ORIGIN & GPP8) | (MV_GPP_IN_INVERT & GPP15)) ); -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvGppPolaritySet(MV_U32 group, MV_U32 mask, MV_U32 value) -+{ -+ if (group >= MV_GPP_MAX_GROUP) -+ { -+ DB(mvOsPrintf("mvGppPolaritySet: ERR. invalid group number \n")); -+ return MV_BAD_PARAM; -+ } -+ -+ gppRegSet(group, GPP_DATA_IN_POL_REG(group), mask, value); -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvGppPolarityGet - Get a value of relevant bits from GPP Polarity register. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* group - GPP group number -+* mask - 32bit mask value. Each set bit in the mask means that the -+* returned value is valid for it. -+* -+* OUTPUT: -+* None. -+* -+* EXAMPLE: -+* Get GPP8 and GPP15 value. -+* mvGppPolarityGet(0, (GPP8 | GPP15)); -+* -+* RETURN: -+* 32bit value that describes GPP polatity mode per pin. -+* -+*******************************************************************************/ -+MV_U32 mvGppPolarityGet(MV_U32 group, MV_U32 mask) -+{ -+ MV_U32 regVal; -+ -+ if (group >= MV_GPP_MAX_GROUP) -+ { -+ DB(mvOsPrintf("mvGppActiveSet: Error invalid group number \n")); -+ return MV_ERROR; -+ } -+ regVal = MV_REG_READ(GPP_DATA_IN_POL_REG(group)); -+ -+ return (regVal & mask); -+} -+ -+/******************************************************************************* -+* mvGppValueGet - Get a GPP Pin list value. -+* -+* DESCRIPTION: -+* This function get GPP value. -+* -+* INPUT: -+* group - GPP group number -+* mask - 32bit mask value. Each set bit in the mask means that the -+* returned value is valid for it. -+* -+* OUTPUT: -+* None. -+* -+* EXAMPLE: -+* Get GPP8 and GPP15 value. -+* mvGppValueGet(0, (GPP8 | GPP15)); -+* -+* RETURN: -+* 32bit value that describes GPP activity mode per pin. -+* -+*******************************************************************************/ -+MV_U32 mvGppValueGet(MV_U32 group, MV_U32 mask) -+{ -+ MV_U32 gppData; -+ -+ gppData = MV_REG_READ(GPP_DATA_IN_REG(group)); -+ -+ gppData &= mask; -+ -+ return gppData; -+ -+} -+ -+/******************************************************************************* -+* mvGppValueSet - Set a GPP Pin list value. -+* -+* DESCRIPTION: -+* This function set value for given GPP pin list. -+* -+* INPUT: -+* group - GPP group number -+* mask - 32bit mask value. Each set bit in the mask means that the -+* value of corresponding GPP will be set accordingly. Other GPP -+* are not affected. -+* value - 32bit value that describes GPP value per pin. -+* -+* OUTPUT: -+* None. -+* -+* EXAMPLE: -+* Set GPP8 value of '0' and GPP15 value of '1'. -+* mvGppActiveSet(0, (GPP8 | GPP15), ((0 & GPP8) | (GPP15)) ); -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvGppValueSet (MV_U32 group, MV_U32 mask, MV_U32 value) -+{ -+ MV_U32 outEnable, tmp; -+ MV_U32 i; -+ -+ if (group >= MV_GPP_MAX_GROUP) -+ { -+ DB(mvOsPrintf("mvGppValueSet: Error invalid group number \n")); -+ return MV_BAD_PARAM; -+ } -+ -+ /* verify that the gpp pin is configured as output */ -+ /* Note that in the register out enabled -> bit = '0'. */ -+ outEnable = ~MV_REG_READ(GPP_DATA_OUT_EN_REG(group)); -+ -+ /* Workaround for Erratum FE-MISC-70*/ -+ if(mvCtrlRevGet()==MV_88F6XXX_A0_REV && (group == 1)) -+ { -+ tmp = ~MV_REG_READ(GPP_DATA_OUT_EN_REG(0)); -+ outEnable &= 0xfffffffd; -+ outEnable |= (tmp & 0x2); -+ } /*End of WA*/ -+ -+ for (i = 0 ; i < 32 ;i++) -+ { -+ if (((mask & (1 << i)) & (outEnable & (1 << i))) != (mask & (1 << i))) -+ { -+ mvOsPrintf("mvGppValueSet: Err. An attempt to set output "\ -+ "value to GPP %d in input mode.\n", i); -+ return MV_ERROR; -+ } -+ } -+ -+ gppRegSet(group, GPP_DATA_OUT_REG(group), mask, value); -+ -+ return MV_OK; -+ -+} -+/******************************************************************************* -+* gppRegSet - Set a specific GPP pin on a specific GPP register -+* -+* DESCRIPTION: -+* This function set a specific GPP pin on a specific GPP register -+* -+* INPUT: -+* regOffs - GPP Register offset -+* group - GPP group number -+* mask - 32bit mask value. Each set bit in the mask means that the -+* value of corresponding GPP will be set accordingly. Other GPP -+* are not affected. -+* value - 32bit value that describes GPP value per pin. -+* -+* OUTPUT: -+* None. -+* -+* EXAMPLE: -+* Set GPP8 value of '0' and GPP15 value of '1'. -+* mvGppActiveSet(0, (GPP8 | GPP15), ((0 & GPP8) | (1 & GPP15)) ); -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+static MV_VOID gppRegSet (MV_U32 group, MV_U32 regOffs,MV_U32 mask,MV_U32 value) -+{ -+ MV_U32 gppData; -+ -+ gppData = MV_REG_READ(regOffs); -+ -+ gppData &= ~mask; -+ -+ gppData |= (value & mask); -+ -+ MV_REG_WRITE(regOffs, gppData); -+} -+ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.h 2010-11-09 20:28:11.302495429 +0100 -@@ -0,0 +1,118 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvGppH -+#define __INCmvGppH -+ -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+#include "gpp/mvGppRegs.h" -+ -+/* These macros describes the GPP type. Each of the GPPs pins can */ -+/* be assigned to act as a general purpose input or output pin. */ -+#define MV_GPP_IN 0xFFFFFFFF /* GPP input */ -+#define MV_GPP_OUT 0 /* GPP output */ -+ -+ -+/* These macros describes the GPP Out Enable. */ -+#define MV_GPP_OUT_DIS 0xFFFFFFFF /* Out pin disabled*/ -+#define MV_GPP_OUT_EN 0 /* Out pin enabled*/ -+ -+/* These macros describes the GPP Out Blinking. */ -+/* When set and the corresponding bit in GPIO Data Out Enable Control */ -+/* Register is enabled, the GPIO pin blinks every ~100 ms (a period of */ -+/* 2^24 TCLK clocks). */ -+#define MV_GPP_OUT_BLINK 0xFFFFFFFF /* Out pin blinking*/ -+#define MV_GPP_OUT_STATIC 0 /* Out pin static*/ -+ -+ -+/* These macros describes the GPP Polarity. */ -+/* When set to 1 GPIO Data In Register reflects the inverted value of the */ -+/* corresponding pin. */ -+ -+#define MV_GPP_IN_INVERT 0xFFFFFFFF /* Inverted value is got*/ -+#define MV_GPP_IN_ORIGIN 0 /* original value is got*/ -+ -+/* mvGppTypeSet - Set PP pin mode (IN or OUT) */ -+MV_STATUS mvGppTypeSet(MV_U32 group, MV_U32 mask, MV_U32 value); -+ -+/* mvGppBlinkEn - Set a GPP (IN) Pin list to blink every ~100ms */ -+MV_STATUS mvGppBlinkEn(MV_U32 group, MV_U32 mask, MV_U32 value); -+ -+/* mvGppPolaritySet - Set a GPP (IN) Pin list Polarity mode. */ -+MV_STATUS mvGppPolaritySet(MV_U32 group, MV_U32 mask, MV_U32 value); -+ -+/* mvGppPolarityGet - Get the Polarity of a GPP Pin */ -+MV_U32 mvGppPolarityGet(MV_U32 group, MV_U32 mask); -+ -+/* mvGppValueGet - Get a GPP Pin list value.*/ -+MV_U32 mvGppValueGet(MV_U32 group, MV_U32 mask); -+ -+ -+/* mvGppValueSet - Set a GPP Pin list value. */ -+MV_STATUS mvGppValueSet (MV_U32 group, MV_U32 mask, MV_U32 value); -+ -+#endif /* #ifndef __INCmvGppH */ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGppRegs.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGppRegs.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGppRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGppRegs.h 2010-11-09 20:28:11.342495467 +0100 -@@ -0,0 +1,116 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvGppRegsH -+#define __INCmvGppRegsH -+ -+#define MV_GPP0 BIT0 -+#define MV_GPP1 BIT1 -+#define MV_GPP2 BIT2 -+#define MV_GPP3 BIT3 -+#define MV_GPP4 BIT4 -+#define MV_GPP5 BIT5 -+#define MV_GPP6 BIT6 -+#define MV_GPP7 BIT7 -+#define MV_GPP8 BIT8 -+#define MV_GPP9 BIT9 -+#define MV_GPP10 BIT10 -+#define MV_GPP11 BIT11 -+#define MV_GPP12 BIT12 -+#define MV_GPP13 BIT13 -+#define MV_GPP14 BIT14 -+#define MV_GPP15 BIT15 -+#define MV_GPP16 BIT16 -+#define MV_GPP17 BIT17 -+#define MV_GPP18 BIT18 -+#define MV_GPP19 BIT19 -+#define MV_GPP20 BIT20 -+#define MV_GPP21 BIT21 -+#define MV_GPP22 BIT22 -+#define MV_GPP23 BIT23 -+#define MV_GPP24 BIT24 -+#define MV_GPP25 BIT25 -+#define MV_GPP26 BIT26 -+#define MV_GPP27 BIT27 -+#define MV_GPP28 BIT28 -+#define MV_GPP29 BIT29 -+#define MV_GPP30 BIT30 -+#define MV_GPP31 BIT31 -+ -+ -+/* registers offsets */ -+ -+#define GPP_DATA_OUT_REG(grp) ((grp == 0) ? 0x10100 : 0x10140) -+#define GPP_DATA_OUT_EN_REG(grp) ((grp == 0) ? 0x10104 : 0x10144) -+#define GPP_BLINK_EN_REG(grp) ((grp == 0) ? 0x10108 : 0x10148) -+#define GPP_DATA_IN_POL_REG(grp) ((grp == 0) ? 0x1010C : 0x1014c) -+#define GPP_DATA_IN_REG(grp) ((grp == 0) ? 0x10110 : 0x10150) -+#define GPP_INT_CAUSE_REG(grp) ((grp == 0) ? 0x10114 : 0x10154) -+#define GPP_INT_MASK_REG(grp) ((grp == 0) ? 0x10118 : 0x10158) -+#define GPP_INT_LVL_REG(grp) ((grp == 0) ? 0x1011c : 0x1015c) -+ -+#define GPP_DATA_OUT_SET_REG 0x10120 -+#define GPP_DATA_OUT_CLEAR_REG 0x10124 -+ -+#endif /* #ifndef __INCmvGppRegsH */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.c 2010-11-09 20:28:11.372495482 +0100 -@@ -0,0 +1,1047 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#include "pci/mvPci.h" -+ -+#include "ctrlEnv/mvCtrlEnvLib.h" -+ -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+ -+ -+MV_VOID mvPciHalInit(MV_U32 pciIf, MV_PCI_MOD pciIfmod) -+{ -+ if (MV_PCI_MOD_HOST == pciIfmod) -+ { -+ -+ mvPciLocalBusNumSet(pciIf, PCI_HOST_BUS_NUM(pciIf)); -+ mvPciLocalDevNumSet(pciIf, PCI_HOST_DEV_NUM(pciIf)); -+ -+ /* Local device master Enable */ -+ mvPciMasterEnable(pciIf, MV_TRUE); -+ -+ /* Local device slave Enable */ -+ mvPciSlaveEnable(pciIf, mvPciLocalBusNumGet(pciIf), -+ mvPciLocalDevNumGet(pciIf), MV_TRUE); -+ } -+ /* enable CPU-2-PCI ordering */ -+ MV_REG_BIT_SET(PCI_CMD_REG(0), PCR_CPU_TO_PCI_ORDER_EN); -+} -+ -+/******************************************************************************* -+* mvPciCommandSet - Set PCI comman register value. -+* -+* DESCRIPTION: -+* This function sets a given PCI interface with its command register -+* value. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* command - 32bit value to be written to comamnd register. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM if pciIf is not in range otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciCommandSet(MV_U32 pciIf, MV_U32 command) -+{ -+ MV_U32 locBusNum, locDevNum, regVal; -+ -+ locBusNum = mvPciLocalBusNumGet(pciIf); -+ locDevNum = mvPciLocalDevNumGet(pciIf); -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciCommandSet: ERR. Invalid PCI IF num %d\n", pciIf); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Set command register */ -+ MV_REG_WRITE(PCI_CMD_REG(pciIf), command); -+ -+ /* Upodate device max outstanding split tarnsaction */ -+ if ((command & PCR_CPU_TO_PCI_ORDER_EN) && -+ (command & PCR_PCI_TO_CPU_ORDER_EN)) -+ { -+ /* Read PCI-X command register */ -+ regVal = mvPciConfigRead (pciIf, locBusNum, locDevNum, 0, PCIX_COMMAND); -+ -+ /* clear bits 22:20 */ -+ regVal &= 0xff8fffff; -+ -+ /* set reset value */ -+ regVal |= (0x3 << 20); -+ -+ /* Write back the value */ -+ mvPciConfigWrite (pciIf, locBusNum, locDevNum, 0, PCIX_COMMAND, regVal); -+ } -+ -+ return MV_OK; -+ -+ -+} -+ -+ -+/******************************************************************************* -+* mvPciModeGet - Get PCI interface mode. -+* -+* DESCRIPTION: -+* This function returns the given PCI interface mode. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* -+* OUTPUT: -+* pPciMode - Pointer to PCI mode structure. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciModeGet(MV_U32 pciIf, MV_PCI_MODE *pPciMode) -+{ -+ MV_U32 pciMode; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciModeGet: ERR. Invalid PCI interface %d\n", pciIf); -+ return MV_BAD_PARAM; -+ } -+ if (NULL == pPciMode) -+ { -+ mvOsPrintf("mvPciModeGet: ERR. pPciMode = NULL \n"); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Read pci mode register */ -+ pciMode = MV_REG_READ(PCI_MODE_REG(pciIf)); -+ -+ switch (pciMode & PMR_PCI_MODE_MASK) -+ { -+ case PMR_PCI_MODE_CONV: -+ pPciMode->pciType = MV_PCI_CONV; -+ -+ if (MV_REG_READ(PCI_DLL_CTRL_REG(pciIf)) & PDC_DLL_EN) -+ { -+ pPciMode->pciSpeed = 66000000; /* 66MHZ */ -+ } -+ else -+ { -+ pPciMode->pciSpeed = 33000000; /* 33MHZ */ -+ } -+ -+ break; -+ -+ case PMR_PCI_MODE_PCIX_66MHZ: -+ pPciMode->pciType = MV_PCIX; -+ pPciMode->pciSpeed = 66000000; /* 66MHZ */ -+ break; -+ -+ case PMR_PCI_MODE_PCIX_100MHZ: -+ pPciMode->pciType = MV_PCIX; -+ pPciMode->pciSpeed = 100000000; /* 100MHZ */ -+ break; -+ -+ case PMR_PCI_MODE_PCIX_133MHZ: -+ pPciMode->pciType = MV_PCIX; -+ pPciMode->pciSpeed = 133000000; /* 133MHZ */ -+ break; -+ -+ default: -+ { -+ mvOsPrintf("mvPciModeGet: ERR. Non existing mode !!\n"); -+ return MV_ERROR; -+ } -+ } -+ -+ switch (pciMode & PMR_PCI_64_MASK) -+ { -+ case PMR_PCI_64_64BIT: -+ pPciMode->pciWidth = MV_PCI_64; -+ break; -+ -+ case PMR_PCI_64_32BIT: -+ pPciMode->pciWidth = MV_PCI_32; -+ break; -+ -+ default: -+ { -+ mvOsPrintf("mvPciModeGet: ERR. Non existing mode !!\n"); -+ return MV_ERROR; -+ } -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvPciRetrySet - Set PCI retry counters -+* -+* DESCRIPTION: -+* This function specifies the number of times the PCI controller -+* retries a transaction before it quits. -+* Applies to the PCI Master when acting as a requester. -+* Applies to the PCI slave when acting as a completer (PCI-X mode). -+* A 0x00 value means a "retry forever". -+* -+* INPUT: -+* pciIf - PCI interface number. -+* counter - Number of times PCI controller retry. Use counter value -+* up to PRR_RETRY_CNTR_MAX. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciRetrySet(MV_U32 pciIf, MV_U32 counter) -+{ -+ MV_U32 pciRetry; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciRetrySet: ERR. Invalid PCI interface %d\n", pciIf); -+ return MV_BAD_PARAM; -+ } -+ -+ if (counter >= PRR_RETRY_CNTR_MAX) -+ { -+ mvOsPrintf("mvPciRetrySet: ERR. Invalid counter: %d\n", counter); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ /* Reading PCI retry register */ -+ pciRetry = MV_REG_READ(PCI_RETRY_REG(pciIf)); -+ -+ pciRetry &= ~PRR_RETRY_CNTR_MASK; -+ -+ pciRetry |= (counter << PRR_RETRY_CNTR_OFFS); -+ -+ /* write new value */ -+ MV_REG_WRITE(PCI_RETRY_REG(pciIf), pciRetry); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPciDiscardTimerSet - Set PCI discard timer -+* -+* DESCRIPTION: -+* This function set PCI discard timer. -+* In conventional PCI mode: -+* Specifies the number of PCLK cycles the PCI slave keeps a non-accessed -+* read buffers (non-completed delayed read) before invalidate the buffer. -+* Set to '0' to disable the timer. The PCI slave waits for delayed -+* read completion forever. -+* In PCI-X mode: -+* Specifies the number of PCLK cycles the PCI master waits for split -+* completion transaction, before it invalidates the pre-allocated read -+* buffer. -+* Set to '0' to disable the timer. The PCI master waits for split -+* completion forever. -+* NOTE: Must be set to a number greater than MV_PCI_MAX_DISCARD_CLK, -+* unless using the "wait for ever" setting 0x0. -+* NOTE: Must not be updated while there are pending read requests. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* pClkCycles - Number of PCI clock cycles. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciDiscardTimerSet(MV_U32 pciIf, MV_U32 pClkCycles) -+{ -+ MV_U32 pciDiscardTimer; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciDiscardTimerSet: ERR. Invalid PCI interface %d\n", -+ pciIf); -+ return MV_BAD_PARAM; -+ } -+ -+ if (pClkCycles >= PDTR_TIMER_MIN) -+ { -+ mvOsPrintf("mvPciDiscardTimerSet: ERR. Invalid Clk value: %d\n", -+ pClkCycles); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ /* Read PCI Discard Timer */ -+ pciDiscardTimer = MV_REG_READ(PCI_DISCARD_TIMER_REG(pciIf)); -+ -+ pciDiscardTimer &= ~PDTR_TIMER_MASK; -+ -+ pciDiscardTimer |= (pClkCycles << PDTR_TIMER_OFFS); -+ -+ /* Write new value */ -+ MV_REG_WRITE(PCI_DISCARD_TIMER_REG(pciIf), pciDiscardTimer); -+ -+ return MV_OK; -+ -+} -+ -+/* PCI Arbiter routines */ -+ -+/******************************************************************************* -+* mvPciArbEnable - PCI arbiter enable/disable -+* -+* DESCRIPTION: -+* This fuction enable/disables a given PCI interface arbiter. -+* NOTE: Arbiter setting can not be changed while in work. It should only -+* be set once. -+* INPUT: -+* pciIf - PCI interface number. -+* enable - Enable/disable parameter. If enable = MV_TRUE then enable. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvPciArbEnable(MV_U32 pciIf, MV_BOOL enable) -+{ -+ MV_U32 regVal; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciArbEnable: ERR. Invalid PCI interface %d\n", pciIf); -+ return MV_ERROR; -+ } -+ -+ /* Set PCI Arbiter Control register according to default configuration */ -+ regVal = MV_REG_READ(PCI_ARBITER_CTRL_REG(pciIf)); -+ -+ /* Make sure arbiter disabled before changing its values */ -+ MV_REG_BIT_RESET(PCI_ARBITER_CTRL_REG(pciIf), PACR_ARB_ENABLE); -+ -+ regVal &= ~PCI_ARBITER_CTRL_DEFAULT_MASK; -+ -+ regVal |= PCI_ARBITER_CTRL_DEFAULT; /* Set default configuration */ -+ -+ if (MV_TRUE == enable) -+ { -+ regVal |= PACR_ARB_ENABLE; -+ } -+ else -+ { -+ regVal &= ~PACR_ARB_ENABLE; -+ } -+ -+ /* Write to register */ -+ MV_REG_WRITE(PCI_ARBITER_CTRL_REG(pciIf), regVal); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPciArbParkDis - Disable arbiter parking on agent -+* -+* DESCRIPTION: -+* This function disables the PCI arbiter from parking on the given agent -+* list. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* pciAgentMask - When a bit in the mask is set to '1', parking on -+* the associated PCI master is disabled. Mask bit -+* refers to bit 0 - 6. For example disable parking on PCI -+* agent 3 set pciAgentMask 0x4 (bit 3 is set). -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvPciArbParkDis(MV_U32 pciIf, MV_U32 pciAgentMask) -+{ -+ MV_U32 pciArbiterCtrl; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciArbParkDis: ERR. Invalid PCI interface %d\n", pciIf); -+ return MV_ERROR; -+ } -+ -+ /* Reading Arbiter Control register */ -+ pciArbiterCtrl = MV_REG_READ(PCI_ARBITER_CTRL_REG(pciIf)); -+ -+ /* Arbiter must be disabled before changing parking */ -+ MV_REG_BIT_RESET(PCI_ARBITER_CTRL_REG(pciIf), PACR_ARB_ENABLE); -+ -+ /* do the change */ -+ pciArbiterCtrl &= ~PACR_PARK_DIS_MASK; -+ pciArbiterCtrl |= (pciAgentMask << PACR_PARK_DIS_OFFS); -+ -+ /* writing new value ( if th earbiter was enabled before the change */ -+ /* here it will be reenabled */ -+ MV_REG_WRITE(PCI_ARBITER_CTRL_REG(pciIf), pciArbiterCtrl); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPciArbBrokDetectSet - Set PCI arbiter broken detection -+* -+* DESCRIPTION: -+* This function sets the maximum number of cycles that the arbiter -+* waits for a PCI master to respond to its grant assertion. If a -+* PCI agent fails to respond within this time, the PCI arbiter aborts -+* the transaction and performs a new arbitration cycle. -+* NOTE: Value must be greater than '1' for conventional PCI and -+* greater than '5' for PCI-X. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* pClkCycles - Number of PCI clock cycles. If equal to '0' the broken -+* master detection is disabled. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciArbBrokDetectSet(MV_U32 pciIf, MV_U32 pClkCycles) -+{ -+ MV_U32 pciArbiterCtrl; -+ MV_U32 pciMode; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciArbBrokDetectSet: ERR. Invalid PCI interface %d\n", -+ pciIf); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Checking PCI mode and if pClkCycles is legal value */ -+ pciMode = MV_REG_READ(PCI_MODE_REG(pciIf)); -+ pciMode &= PMR_PCI_MODE_MASK; -+ -+ if (PMR_PCI_MODE_CONV == pciMode) -+ { -+ if (pClkCycles < PACR_BROKEN_VAL_CONV_MIN) -+ return MV_ERROR; -+ } -+ else -+ { -+ if (pClkCycles < PACR_BROKEN_VAL_PCIX_MIN) -+ return MV_ERROR; -+ } -+ -+ pClkCycles <<= PACR_BROKEN_VAL_OFFS; -+ -+ /* Reading Arbiter Control register */ -+ pciArbiterCtrl = MV_REG_READ(PCI_ARBITER_CTRL_REG(pciIf)); -+ pciArbiterCtrl &= ~PACR_BROKEN_VAL_MASK; -+ pciArbiterCtrl |= pClkCycles; -+ -+ /* Arbiter must be disabled before changing broken detection */ -+ MV_REG_BIT_RESET(PCI_ARBITER_CTRL_REG(pciIf), PACR_ARB_ENABLE); -+ -+ /* writing new value ( if th earbiter was enabled before the change */ -+ /* here it will be reenabled */ -+ -+ MV_REG_WRITE(PCI_ARBITER_CTRL_REG(pciIf), pciArbiterCtrl); -+ -+ return MV_OK; -+} -+ -+/* PCI configuration space read write */ -+ -+/******************************************************************************* -+* mvPciConfigRead - Read from configuration space -+* -+* DESCRIPTION: -+* This function performs a 32 bit read from PCI configuration space. -+* It supports both type 0 and type 1 of Configuration Transactions -+* (local and over bridge). In order to read from local bus segment, use -+* bus number retrieved from mvPciLocalBusNumGet(). Other bus numbers -+* will result configuration transaction of type 1 (over bridge). -+* -+* INPUT: -+* pciIf - PCI interface number. -+* bus - PCI segment bus number. -+* dev - PCI device number. -+* func - Function number. -+* regOffs - Register offset. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit register data, 0xffffffff on error -+* -+*******************************************************************************/ -+MV_U32 mvPciConfigRead (MV_U32 pciIf, MV_U32 bus, MV_U32 dev, MV_U32 func, -+ MV_U32 regOff) -+{ -+ MV_U32 pciData = 0; -+ -+ /* Parameter checking */ -+ if (PCI_DEFAULT_IF != pciIf) -+ { -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciConfigRead: ERR. Invalid PCI interface %d\n",pciIf); -+ return 0xFFFFFFFF; -+ } -+ } -+ -+ if (dev >= MAX_PCI_DEVICES) -+ { -+ DB(mvOsPrintf("mvPciConfigRead: ERR. device number illigal %d\n", dev)); -+ return 0xFFFFFFFF; -+ } -+ -+ if (func >= MAX_PCI_FUNCS) -+ { -+ DB(mvOsPrintf("mvPciConfigRead: ERR. function number illigal %d\n", func)); -+ return 0xFFFFFFFF; -+ } -+ -+ if (bus >= MAX_PCI_BUSSES) -+ { -+ DB(mvOsPrintf("mvPciConfigRead: ERR. bus number illigal %d\n", bus)); -+ return MV_ERROR; -+ } -+ -+ -+ /* Creating PCI address to be passed */ -+ pciData |= (bus << PCAR_BUS_NUM_OFFS); -+ pciData |= (dev << PCAR_DEVICE_NUM_OFFS); -+ pciData |= (func << PCAR_FUNC_NUM_OFFS); -+ pciData |= (regOff & PCAR_REG_NUM_MASK); -+ -+ pciData |= PCAR_CONFIG_EN; -+ -+ /* Write the address to the PCI configuration address register */ -+ MV_REG_WRITE(PCI_CONFIG_ADDR_REG(pciIf), pciData); -+ -+ /* In order to let the PCI controller absorbed the address of the read */ -+ /* transaction we perform a validity check that the address was written */ -+ if(pciData != MV_REG_READ(PCI_CONFIG_ADDR_REG(pciIf))) -+ { -+ return MV_ERROR; -+ } -+ /* Read the Data returned in the PCI Data register */ -+ pciData = MV_REG_READ(PCI_CONFIG_DATA_REG(pciIf)); -+ -+ return pciData; -+} -+ -+/******************************************************************************* -+* mvPciConfigWrite - Write to configuration space -+* -+* DESCRIPTION: -+* This function performs a 32 bit write to PCI configuration space. -+* It supports both type 0 and type 1 of Configuration Transactions -+* (local and over bridge). In order to write to local bus segment, use -+* bus number retrieved from mvPciLocalBusNumGet(). Other bus numbers -+* will result configuration transaction of type 1 (over bridge). -+* -+* INPUT: -+* pciIf - PCI interface number. -+* bus - PCI segment bus number. -+* dev - PCI device number. -+* func - Function number. -+* regOffs - Register offset. -+* data - 32bit data. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciConfigWrite(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data) -+{ -+ MV_U32 pciData = 0; -+ -+ /* Parameter checking */ -+ if (PCI_DEFAULT_IF != pciIf) -+ { -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciConfigWrite: ERR. Invalid PCI interface %d\n", -+ pciIf); -+ return 0xFFFFFFFF; -+ } -+ } -+ -+ if (dev >= MAX_PCI_DEVICES) -+ { -+ mvOsPrintf("mvPciConfigWrite: ERR. device number illigal %d\n",dev); -+ return MV_BAD_PARAM; -+ } -+ -+ if (func >= MAX_PCI_FUNCS) -+ { -+ mvOsPrintf("mvPciConfigWrite: ERR. function number illigal %d\n", func); -+ return MV_ERROR; -+ } -+ -+ if (bus >= MAX_PCI_BUSSES) -+ { -+ mvOsPrintf("mvPciConfigWrite: ERR. bus number illigal %d\n", bus); -+ return MV_ERROR; -+ } -+ -+ /* Creating PCI address to be passed */ -+ pciData |= (bus << PCAR_BUS_NUM_OFFS); -+ pciData |= (dev << PCAR_DEVICE_NUM_OFFS); -+ pciData |= (func << PCAR_FUNC_NUM_OFFS); -+ pciData |= (regOff & PCAR_REG_NUM_MASK); -+ -+ pciData |= PCAR_CONFIG_EN; -+ -+ /* Write the address to the PCI configuration address register */ -+ MV_REG_WRITE(PCI_CONFIG_ADDR_REG(pciIf), pciData); -+ -+ /* In order to let the PCI controller absorbed the address of the read */ -+ /* transaction we perform a validity check that the address was written */ -+ if(pciData != MV_REG_READ(PCI_CONFIG_ADDR_REG(pciIf))) -+ { -+ return MV_ERROR; -+ } -+ -+ /* Write the Data passed to the PCI Data register */ -+ MV_REG_WRITE(PCI_CONFIG_DATA_REG(pciIf), data); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvPciMasterEnable - Enable/disale PCI interface master transactions. -+* -+* DESCRIPTION: -+* This function performs read modified write to PCI command status -+* (offset 0x4) to set/reset bit 2. After this bit is set, the PCI -+* master is allowed to gain ownership on the bus, otherwise it is -+* incapable to do so. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciMasterEnable(MV_U32 pciIf, MV_BOOL enable) -+{ -+ MV_U32 pciCommandStatus; -+ MV_U32 RegOffs; -+ MV_U32 localBus; -+ MV_U32 localDev; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciMasterEnable: ERR. Invalid PCI interface %d\n", pciIf); -+ return MV_ERROR; -+ } -+ -+ localBus = mvPciLocalBusNumGet(pciIf); -+ localDev = mvPciLocalDevNumGet(pciIf); -+ -+ RegOffs = PCI_STATUS_AND_COMMAND; -+ -+ pciCommandStatus = mvPciConfigRead(pciIf, localBus, localDev, 0, RegOffs); -+ -+ if (MV_TRUE == enable) -+ { -+ pciCommandStatus |= PSCR_MASTER_EN; -+ } -+ else -+ { -+ pciCommandStatus &= ~PSCR_MASTER_EN; -+ } -+ -+ mvPciConfigWrite(pciIf, localBus, localDev, 0, RegOffs, pciCommandStatus); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPciSlaveEnable - Enable/disale PCI interface slave transactions. -+* -+* DESCRIPTION: -+* This function performs read modified write to PCI command status -+* (offset 0x4) to set/reset bit 0 and 1. After those bits are set, -+* the PCI slave is allowed to respond to PCI IO space access (bit 0) -+* and PCI memory space access (bit 1). -+* -+* INPUT: -+* pciIf - PCI interface number. -+* dev - PCI device number. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciSlaveEnable(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, MV_BOOL enable) -+{ -+ MV_U32 pciCommandStatus; -+ MV_U32 RegOffs; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciSlaveEnable: ERR. Invalid PCI interface %d\n", pciIf); -+ return MV_BAD_PARAM; -+ } -+ if (dev >= MAX_PCI_DEVICES) -+ { -+ mvOsPrintf("mvPciLocalDevNumSet: ERR. device number illigal %d\n", dev); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ RegOffs = PCI_STATUS_AND_COMMAND; -+ -+ pciCommandStatus=mvPciConfigRead(pciIf, bus, dev, 0, RegOffs); -+ -+ if (MV_TRUE == enable) -+ { -+ pciCommandStatus |= (PSCR_IO_EN | PSCR_MEM_EN); -+ } -+ else -+ { -+ pciCommandStatus &= ~(PSCR_IO_EN | PSCR_MEM_EN); -+ } -+ -+ mvPciConfigWrite(pciIf, bus, dev, 0, RegOffs, pciCommandStatus); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvPciLocalBusNumSet - Set PCI interface local bus number. -+* -+* DESCRIPTION: -+* This function sets given PCI interface its local bus number. -+* Note: In case the PCI interface is PCI-X, the information is read-only. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* busNum - Bus number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_NOT_ALLOWED in case PCI interface is PCI-X. -+* MV_BAD_PARAM on bad parameters , -+* otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciLocalBusNumSet(MV_U32 pciIf, MV_U32 busNum) -+{ -+ MV_U32 pciP2PConfig; -+ MV_PCI_MODE pciMode; -+ MV_U32 localBus; -+ MV_U32 localDev; -+ -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciLocalBusNumSet: ERR. Invalid PCI interface %d\n",pciIf); -+ return MV_BAD_PARAM; -+ } -+ if (busNum >= MAX_PCI_BUSSES) -+ { -+ mvOsPrintf("mvPciLocalBusNumSet: ERR. bus number illigal %d\n", busNum); -+ return MV_ERROR; -+ -+ } -+ -+ localBus = mvPciLocalBusNumGet(pciIf); -+ localDev = mvPciLocalDevNumGet(pciIf); -+ -+ -+ /* PCI interface mode */ -+ mvPciModeGet(pciIf, &pciMode); -+ -+ /* if PCI type is PCI-X then it is not allowed to change the dev number */ -+ if (MV_PCIX == pciMode.pciType) -+ { -+ pciP2PConfig = mvPciConfigRead(pciIf, localBus, localDev, 0, PCIX_STATUS ); -+ -+ pciP2PConfig &= ~PXS_BN_MASK; -+ -+ pciP2PConfig |= (busNum << PXS_BN_OFFS) & PXS_BN_MASK; -+ -+ mvPciConfigWrite(pciIf, localBus, localDev, 0, PCIX_STATUS,pciP2PConfig ); -+ -+ } -+ else -+ { -+ pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); -+ -+ pciP2PConfig &= ~PPCR_BUS_NUM_MASK; -+ -+ pciP2PConfig |= (busNum << PPCR_BUS_NUM_OFFS) & PPCR_BUS_NUM_MASK; -+ -+ MV_REG_WRITE(PCI_P2P_CONFIG_REG(pciIf), pciP2PConfig); -+ -+ } -+ -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPciLocalBusNumGet - Get PCI interface local bus number. -+* -+* DESCRIPTION: -+* This function gets the local bus number of a given PCI interface. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Local bus number.0xffffffff on Error -+* -+*******************************************************************************/ -+MV_U32 mvPciLocalBusNumGet(MV_U32 pciIf) -+{ -+ MV_U32 pciP2PConfig; -+ -+ /* Parameter checking */ -+ if (PCI_DEFAULT_IF != pciIf) -+ { -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciLocalBusNumGet: ERR. Invalid PCI interface %d\n", -+ pciIf); -+ return 0xFFFFFFFF; -+ } -+ } -+ -+ pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); -+ pciP2PConfig &= PPCR_BUS_NUM_MASK; -+ return (pciP2PConfig >> PPCR_BUS_NUM_OFFS); -+} -+ -+ -+/******************************************************************************* -+* mvPciLocalDevNumSet - Set PCI interface local device number. -+* -+* DESCRIPTION: -+* This function sets given PCI interface its local device number. -+* Note: In case the PCI interface is PCI-X, the information is read-only. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* devNum - Device number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_NOT_ALLOWED in case PCI interface is PCI-X. MV_BAD_PARAM on bad parameters , -+* otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciLocalDevNumSet(MV_U32 pciIf, MV_U32 devNum) -+{ -+ MV_U32 pciP2PConfig; -+ MV_PCI_MODE pciMode; -+ MV_U32 localBus; -+ MV_U32 localDev; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciLocalDevNumSet: ERR. Invalid PCI interface %d\n",pciIf); -+ return MV_BAD_PARAM; -+ } -+ if (devNum >= MAX_PCI_DEVICES) -+ { -+ mvOsPrintf("mvPciLocalDevNumSet: ERR. device number illigal %d\n", -+ devNum); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ localBus = mvPciLocalBusNumGet(pciIf); -+ localDev = mvPciLocalDevNumGet(pciIf); -+ -+ /* PCI interface mode */ -+ mvPciModeGet(pciIf, &pciMode); -+ -+ /* if PCI type is PCIX then it is not allowed to change the dev number */ -+ if (MV_PCIX == pciMode.pciType) -+ { -+ pciP2PConfig = mvPciConfigRead(pciIf, localBus, localDev, 0, PCIX_STATUS ); -+ -+ pciP2PConfig &= ~PXS_DN_MASK; -+ -+ pciP2PConfig |= (devNum << PXS_DN_OFFS) & PXS_DN_MASK; -+ -+ mvPciConfigWrite(pciIf,localBus, localDev, 0, PCIX_STATUS,pciP2PConfig ); -+ } -+ else -+ { -+ pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); -+ -+ pciP2PConfig &= ~PPCR_DEV_NUM_MASK; -+ -+ pciP2PConfig |= (devNum << PPCR_DEV_NUM_OFFS) & PPCR_DEV_NUM_MASK; -+ -+ MV_REG_WRITE(PCI_P2P_CONFIG_REG(pciIf), pciP2PConfig); -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvPciLocalDevNumGet - Get PCI interface local device number. -+* -+* DESCRIPTION: -+* This function gets the local device number of a given PCI interface. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Local device number. 0xffffffff on Error -+* -+*******************************************************************************/ -+MV_U32 mvPciLocalDevNumGet(MV_U32 pciIf) -+{ -+ MV_U32 pciP2PConfig; -+ -+ /* Parameter checking */ -+ -+ if (PCI_DEFAULT_IF != pciIf) -+ { -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciLocalDevNumGet: ERR. Invalid PCI interface %d\n", -+ pciIf); -+ return 0xFFFFFFFF; -+ } -+ } -+ -+ pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); -+ -+ pciP2PConfig &= PPCR_DEV_NUM_MASK; -+ -+ return (pciP2PConfig >> PPCR_DEV_NUM_OFFS); -+} -+ -+ -+ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h 2010-11-09 20:28:11.412495457 +0100 -@@ -0,0 +1,185 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCPCIH -+#define __INCPCIH -+ -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+#include "pci/mvPciRegs.h" -+ -+ -+/* NOTE not supported in this driver: -+ -+ Built In Self Test (BIST) -+ Vital Product Data (VPD) -+ Message Signaled Interrupt (MSI) -+ Power Management -+ Compact PCI Hot Swap -+ Header retarget -+ -+Registers not supported: -+1) PCI DLL Status and Control (PCI0 0x1D20, PCI1 0x1DA0) -+2) PCI/MPP Pads Calibration (CI0/MPP[31:16] 0x1D1C, PCI1/MPP[15:0] 0X1D9C) -+*/ -+ -+/* defines */ -+/* The number of supported PCI interfaces depend on Marvell controller */ -+/* device number. This device number ID is located on the PCI unit */ -+/* configuration header. This creates a loop where calling PCI */ -+/* configuration read/write routine results a call to get PCI configuration */ -+/* information etc. This macro defines a default PCI interface. This PCI */ -+/* interface is sure to exist. */ -+#define PCI_DEFAULT_IF 0 -+ -+ -+/* typedefs */ -+/* The Marvell controller supports both conventional PCI and PCI-X. */ -+/* This enumeration describes the PCI type. */ -+typedef enum _mvPciType -+{ -+ MV_PCI_CONV, /* Conventional PCI */ -+ MV_PCIX /* PCI-X */ -+}MV_PCI_TYPE; -+ -+typedef enum _mvPciMod -+{ -+ MV_PCI_MOD_HOST, -+ MV_PCI_MOD_DEVICE -+}MV_PCI_MOD; -+ -+ -+/* The Marvell controller supports both PCI width of 32 and 64 bit. */ -+/* This enumerator describes PCI width */ -+typedef enum _mvPciWidth -+{ -+ MV_PCI_32, /* PCI width 32bit */ -+ MV_PCI_64 /* PCI width 64bit */ -+}MV_PCI_WIDTH; -+ -+/* This structure describes the PCI unit configured type, speed and width. */ -+typedef struct _mvPciMode -+{ -+ MV_PCI_TYPE pciType; /* PCI type */ -+ MV_U32 pciSpeed; /* Assuming PCI base clock on board is 33MHz */ -+ MV_PCI_WIDTH pciWidth; /* PCI bus width */ -+}MV_PCI_MODE; -+ -+/* mvPciInit - Initialize PCI interfaces*/ -+MV_VOID mvPciHalInit(MV_U32 pciIf, MV_PCI_MOD pciIfmod); -+ -+/* mvPciCommandSet - Set PCI comman register value.*/ -+MV_STATUS mvPciCommandSet(MV_U32 pciIf, MV_U32 command); -+ -+/* mvPciModeGet - Get PCI interface mode.*/ -+MV_STATUS mvPciModeGet(MV_U32 pciIf, MV_PCI_MODE *pPciMode); -+ -+/* mvPciRetrySet - Set PCI retry counters*/ -+MV_STATUS mvPciRetrySet(MV_U32 pciIf, MV_U32 counter); -+ -+/* mvPciDiscardTimerSet - Set PCI discard timer*/ -+MV_STATUS mvPciDiscardTimerSet(MV_U32 pciIf, MV_U32 pClkCycles); -+ -+/* mvPciArbEnable - PCI arbiter enable/disable*/ -+MV_STATUS mvPciArbEnable(MV_U32 pciIf, MV_BOOL enable); -+ -+/* mvPciArbParkDis - Disable arbiter parking on agent */ -+MV_STATUS mvPciArbParkDis(MV_U32 pciIf, MV_U32 pciAgentMask); -+ -+/* mvPciArbBrokDetectSet - Set PCI arbiter broken detection */ -+MV_STATUS mvPciArbBrokDetectSet(MV_U32 pciIf, MV_U32 pClkCycles); -+ -+/* mvPciConfigRead - Read from configuration space */ -+MV_U32 mvPciConfigRead (MV_U32 pciIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func,MV_U32 regOff); -+ -+/* mvPciConfigWrite - Write to configuration space */ -+MV_STATUS mvPciConfigWrite(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data); -+ -+/* mvPciMasterEnable - Enable/disale PCI interface master transactions.*/ -+MV_STATUS mvPciMasterEnable(MV_U32 pciIf, MV_BOOL enable); -+ -+/* mvPciSlaveEnable - Enable/disale PCI interface slave transactions.*/ -+MV_STATUS mvPciSlaveEnable(MV_U32 pciIf, MV_U32 bus, MV_U32 dev,MV_BOOL enable); -+ -+/* mvPciLocalBusNumSet - Set PCI interface local bus number.*/ -+MV_STATUS mvPciLocalBusNumSet(MV_U32 pciIf, MV_U32 busNum); -+ -+/* mvPciLocalBusNumGet - Get PCI interface local bus number.*/ -+MV_U32 mvPciLocalBusNumGet(MV_U32 pciIf); -+ -+/* mvPciLocalDevNumSet - Set PCI interface local device number.*/ -+MV_STATUS mvPciLocalDevNumSet(MV_U32 pciIf, MV_U32 devNum); -+ -+/* mvPciLocalDevNumGet - Get PCI interface local device number.*/ -+MV_U32 mvPciLocalDevNumGet(MV_U32 pciIf); -+ -+ -+#endif /* #ifndef __INCPCIH */ -+ -+ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h 2010-11-09 20:28:11.452495500 +0100 -@@ -0,0 +1,411 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCPCIREGSH -+#define __INCPCIREGSH -+ -+ -+#include "pci-if/mvPciIfRegs.h" -+/* defines */ -+#define MAX_PCI_DEVICES 32 -+#define MAX_PCI_FUNCS 8 -+#define MAX_PCI_BUSSES 128 -+ -+/* enumerators */ -+ -+/* This enumerator described the possible PCI slave targets. */ -+/* PCI slave targets are designated memory/IO address spaces that the */ -+/* PCI slave targets can access. They are also refered as "targets" */ -+/* this enumeratoe order is determined by the content of : -+ PCI_BASE_ADDR_ENABLE_REG */ -+ -+ -+/* registers offsetes defines */ -+ -+ -+ -+/*************************/ -+/* PCI control registers */ -+/*************************/ -+/* maen : should add new registers */ -+#define PCI_CMD_REG(pciIf) (0x30c00 + ((pciIf) * 0x80)) -+#define PCI_MODE_REG(pciIf) (0x30d00 + ((pciIf) * 0x80)) -+#define PCI_RETRY_REG(pciIf) (0x30c04 + ((pciIf) * 0x80)) -+#define PCI_DISCARD_TIMER_REG(pciIf) (0x30d04 + ((pciIf) * 0x80)) -+#define PCI_ARBITER_CTRL_REG(pciIf) (0x31d00 + ((pciIf) * 0x80)) -+#define PCI_P2P_CONFIG_REG(pciIf) (0x31d14 + ((pciIf) * 0x80)) -+#define PCI_ACCESS_CTRL_BASEL_REG(pciIf, targetWin) \ -+ (0x31e00 + ((pciIf) * 0x80) + ((targetWin) * 0x10)) -+#define PCI_ACCESS_CTRL_BASEH_REG(pciIf, targetWin) \ -+ (0x31e04 + ((pciIf) * 0x80) + ((targetWin) * 0x10)) -+#define PCI_ACCESS_CTRL_SIZE_REG(pciIf, targetWin) \ -+ (0x31e08 + ((pciIf) * 0x80) + ((targetWin) * 0x10)) -+ -+#define PCI_DLL_CTRL_REG(pciIf) (0x31d20 + ((pciIf) * 0x80)) -+ -+/* PCI Dll Control (PDC)*/ -+#define PDC_DLL_EN BIT0 -+ -+ -+/* PCI Command Register (PCR) */ -+#define PCR_MASTER_BYTE_SWAP_EN BIT0 -+#define PCR_MASTER_WR_COMBINE_EN BIT4 -+#define PCR_MASTER_RD_COMBINE_EN BIT5 -+#define PCR_MASTER_WR_TRIG_WHOLE BIT6 -+#define PCR_MASTER_RD_TRIG_WHOLE BIT7 -+#define PCR_MASTER_MEM_RD_LINE_EN BIT8 -+#define PCR_MASTER_MEM_RD_MULT_EN BIT9 -+#define PCR_MASTER_WORD_SWAP_EN BIT10 -+#define PCR_SLAVE_WORD_SWAP_EN BIT11 -+#define PCR_NS_ACCORDING_RCV_TRANS BIT14 -+#define PCR_MASTER_PCIX_REQ64N_EN BIT15 -+#define PCR_SLAVE_BYTE_SWAP_EN BIT16 -+#define PCR_MASTER_DAC_EN BIT17 -+#define PCR_MASTER_M64_ALLIGN BIT18 -+#define PCR_ERRORS_PROPAGATION_EN BIT19 -+#define PCR_SLAVE_SWAP_ENABLE BIT20 -+#define PCR_MASTER_SWAP_ENABLE BIT21 -+#define PCR_MASTER_INT_SWAP_EN BIT22 -+#define PCR_LOOP_BACK_ENABLE BIT23 -+#define PCR_SLAVE_INTREG_SWAP_OFFS 24 -+#define PCR_SLAVE_INTREG_SWAP_MASK 0x3 -+#define PCR_SLAVE_INTREG_BYTE_SWAP \ -+ (MV_BYTE_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) -+#define PCR_SLAVE_INTREG_NO_SWAP \ -+ (MV_NO_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) -+#define PCR_SLAVE_INTREG_BYTE_WORD \ -+ (MV_BYTE_WORD_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) -+#define PCR_SLAVE_INTREG_WORD_SWAP \ -+ (MV_WORD_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) -+#define PCR_RESET_REASSERTION_EN BIT26 -+#define PCR_PCI_TO_CPU_REG_ORDER_EN BIT28 -+#define PCR_CPU_TO_PCI_ORDER_EN BIT29 -+#define PCR_PCI_TO_CPU_ORDER_EN BIT30 -+ -+/* PCI Mode Register (PMR) */ -+#define PMR_PCI_ID_OFFS 0 /* PCI Interface ID */ -+#define PMR_PCI_ID_MASK (0x1 << PMR_PCI_ID_OFFS) -+#define PMR_PCI_ID_PCI(pciNum) ((pciNum) << PCI_MODE_PCIID_OFFS) -+ -+#define PMR_PCI_64_OFFS 2 /* 64-bit PCI Interface */ -+#define PMR_PCI_64_MASK (0x1 << PMR_PCI_64_OFFS) -+#define PMR_PCI_64_64BIT (0x1 << PMR_PCI_64_OFFS) -+#define PMR_PCI_64_32BIT (0x0 << PMR_PCI_64_OFFS) -+ -+#define PMR_PCI_MODE_OFFS 4 /* PCI interface mode of operation */ -+#define PMR_PCI_MODE_MASK (0x3 << PMR_PCI_MODE_OFFS) -+#define PMR_PCI_MODE_CONV (0x0 << PMR_PCI_MODE_OFFS) -+#define PMR_PCI_MODE_PCIX_66MHZ (0x1 << PMR_PCI_MODE_OFFS) -+#define PMR_PCI_MODE_PCIX_100MHZ (0x2 << PMR_PCI_MODE_OFFS) -+#define PMR_PCI_MODE_PCIX_133MHZ (0x3 << PMR_PCI_MODE_OFFS) -+ -+#define PMR_EXP_ROM_SUPPORT BIT8 /* Expansion ROM Active */ -+ -+#define PMR_PCI_RESET_OFFS 31 /* PCI Interface Reset Indication */ -+#define PMR_PCI_RESET_MASK (0x1 << PMR_PCI_RESET_OFFS) -+#define PMR_PCI_RESET_PCIXRST (0x0 << PMR_PCI_RESET_OFFS) -+ -+ -+/* PCI Retry Register (PRR) */ -+#define PRR_RETRY_CNTR_OFFS 16 /* Retry Counter */ -+#define PRR_RETRY_CNTR_MAX 0xff -+#define PRR_RETRY_CNTR_MASK (PRR_RETRY_CNTR_MAX << PRR_RETRY_CNTR_OFFS) -+ -+ -+/* PCI Discard Timer Register (PDTR) */ -+#define PDTR_TIMER_OFFS 0 /* Timer */ -+#define PDTR_TIMER_MAX 0xffff -+#define PDTR_TIMER_MIN 0x7F -+#define PDTR_TIMER_MASK (PDTR_TIMER_MAX << PDTR_TIMER_OFFS) -+ -+ -+/* PCI Arbiter Control Register (PACR) */ -+#define PACR_BROKEN_DETECT_EN BIT1 /* Broken Detection Enable */ -+ -+#define PACR_BROKEN_VAL_OFFS 3 /* Broken Value */ -+#define PACR_BROKEN_VAL_MASK (0xf << PACR_BROKEN_VAL_OFFS) -+#define PACR_BROKEN_VAL_CONV_MIN 0x2 -+#define PACR_BROKEN_VAL_PCIX_MIN 0x6 -+ -+#define PACR_PARK_DIS_OFFS 14 /* Parking Disable */ -+#define PACR_PARK_DIS_MAX_AGENT 0x3f -+#define PACR_PARK_DIS_MASK (PACR_PARK_DIS_MAX_AGENT<= MV_PCI_START_IF)&&(pciIf < MV_PCI_MAX_IF + MV_PCI_START_IF)) -+ { -+ return PCI_IF_TYPE_CONVEN_PCIX; -+ } -+ else if ((pciIf >= MV_PEX_START_IF) && -+ (pciIf < MV_PEX_MAX_IF + MV_PEX_START_IF)) -+ { -+ return PCI_IF_TYPE_PEX; -+ -+ } -+ else -+ { -+ mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf); -+ } -+ -+ return 0xffffffff; -+ -+} -+ -+/******************************************************************************* -+* mvPciIfTypeGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+ -+MV_U32 mvPciRealIfNumGet(MV_U32 pciIf) -+{ -+ -+ PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf); -+ -+ if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType) -+ { -+ return (pciIf - MV_PCI_START_IF); -+ } -+ else if (PCI_IF_TYPE_PEX == pciIfType) -+ { -+ return (pciIf - MV_PEX_START_IF); -+ -+ } -+ else -+ { -+ mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf); -+ } -+ -+ return 0xffffffff; -+ -+} -+ -+ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.h 2010-11-09 20:28:11.552495455 +0100 -@@ -0,0 +1,134 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCPCIIFH -+#define __INCPCIIFH -+ -+#include "mvSysHwConfig.h" -+#include "pci-if/mvPciIfRegs.h" -+#if defined(MV_INCLUDE_PEX) -+#include "pex/mvPex.h" -+#endif -+#if defined(MV_INCLUDE_PCI) -+#include "pci/mvPci.h" -+#endif -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+ -+typedef enum _mvPCIIfType -+{ -+ PCI_IF_TYPE_CONVEN_PCIX, -+ PCI_IF_TYPE_PEX -+ -+}PCI_IF_TYPE; -+ -+typedef enum _mvPCIIfMode -+{ -+ PCI_IF_MODE_HOST, -+ PCI_IF_MODE_DEVICE -+}PCI_IF_MODE; -+ -+ -+/* Global Functions prototypes */ -+ -+/* mvPciIfInit - Initialize PCI interfaces*/ -+MV_STATUS mvPciIfInit(MV_U32 pciIf, PCI_IF_MODE pciIfmode); -+ -+/* mvPciIfConfigRead - Read from configuration space */ -+MV_U32 mvPciIfConfigRead (MV_U32 pciIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func,MV_U32 regOff); -+ -+/* mvPciIfConfigWrite - Write to configuration space */ -+MV_STATUS mvPciIfConfigWrite(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data); -+ -+/* mvPciIfMasterEnable - Enable/disale PCI interface master transactions.*/ -+MV_STATUS mvPciIfMasterEnable(MV_U32 pciIf, MV_BOOL enable); -+ -+/* mvPciIfSlaveEnable - Enable/disale PCI interface slave transactions.*/ -+MV_STATUS mvPciIfSlaveEnable(MV_U32 pciIf,MV_U32 bus, MV_U32 dev, -+ MV_BOOL enable); -+ -+/* mvPciIfLocalBusNumSet - Set PCI interface local bus number.*/ -+MV_STATUS mvPciIfLocalBusNumSet(MV_U32 pciIf, MV_U32 busNum); -+ -+/* mvPciIfLocalBusNumGet - Get PCI interface local bus number.*/ -+MV_U32 mvPciIfLocalBusNumGet(MV_U32 pciIf); -+ -+/* mvPciIfLocalDevNumSet - Set PCI interface local device number.*/ -+MV_STATUS mvPciIfLocalDevNumSet(MV_U32 pciIf, MV_U32 devNum); -+ -+/* mvPciIfLocalDevNumGet - Get PCI interface local device number.*/ -+MV_U32 mvPciIfLocalDevNumGet(MV_U32 pciIf); -+ -+/* mvPciIfTypeGet - Get PCI If type*/ -+PCI_IF_TYPE mvPciIfTypeGet(MV_U32 pciIf); -+ -+MV_U32 mvPciRealIfNumGet(MV_U32 pciIf); -+ -+/* mvPciIfAddrDecShow - Display address decode windows attributes */ -+MV_VOID mvPciIfAddrDecShow(MV_VOID); -+ -+#endif /* #ifndef __INCPCIIFH */ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h 2010-11-09 20:28:11.592495403 +0100 -@@ -0,0 +1,245 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCPCIIFREGSH -+#define __INCPCIIFREGSH -+ -+ -+/* defines */ -+#define MAX_PCI_DEVICES 32 -+#define MAX_PCI_FUNCS 8 -+#define MAX_PCI_BUSSES 128 -+ -+/***************************************/ -+/* PCI Configuration registers */ -+/***************************************/ -+ -+/*********************************************/ -+/* PCI Configuration, Function 0, Registers */ -+/*********************************************/ -+ -+ -+/* Standard registers */ -+#define PCI_DEVICE_AND_VENDOR_ID 0x000 -+#define PCI_STATUS_AND_COMMAND 0x004 -+#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 -+#define PCI_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE 0x00C -+#define PCI_MEMORY_BAR_BASE_ADDR(barNum) (0x010 + ((barNum) << 2)) -+#define PCI_SUBSYS_ID_AND_SUBSYS_VENDOR_ID 0x02C -+#define PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030 -+#define PCI_CAPABILTY_LIST_POINTER 0x034 -+#define PCI_INTERRUPT_PIN_AND_LINE 0x03C -+ -+ -+/* PCI Device and Vendor ID Register (PDVIR) */ -+#define PDVIR_VEN_ID_OFFS 0 /* Vendor ID */ -+#define PDVIR_VEN_ID_MASK (0xffff << PDVIR_VEN_ID_OFFS) -+ -+#define PDVIR_DEV_ID_OFFS 16 /* Device ID */ -+#define PDVIR_DEV_ID_MASK (0xffff << PDVIR_DEV_ID_OFFS) -+ -+/* PCI Status and Command Register (PSCR) */ -+#define PSCR_IO_EN BIT0 /* IO Enable */ -+#define PSCR_MEM_EN BIT1 /* Memory Enable */ -+#define PSCR_MASTER_EN BIT2 /* Master Enable */ -+#define PSCR_SPECIAL_EN BIT3 /* Special Cycle Enable */ -+#define PSCR_MEM_WRI_INV BIT4 /* Memory Write and Invalidate Enable */ -+#define PSCR_VGA BIT5 /* VGA Palette Snoops */ -+#define PSCR_PERR_EN BIT6 /* Parity Errors Respond Enable */ -+#define PSCR_ADDR_STEP BIT7 /* Address Stepping Enable (Wait Cycle En)*/ -+#define PSCR_SERR_EN BIT8 /* Ability to assert SERR# line */ -+#define PSCR_FAST_BTB_EN BIT9 /* generate fast back-to-back transactions*/ -+#define PSCR_CAP_LIST BIT20 /* Capability List Support */ -+#define PSCR_66MHZ_EN BIT21 /* 66 MHz Capable */ -+#define PSCR_UDF_EN BIT22 /* User definable features */ -+#define PSCR_TAR_FAST_BB BIT23 /* fast back-to-back transactions capable */ -+#define PSCR_DATA_PERR BIT24 /* Data Parity reported */ -+ -+#define PSCR_DEVSEL_TIM_OFFS 25 /* DEVSEL timing */ -+#define PSCR_DEVSEL_TIM_MASK (0x3 << PSCR_DEVSEL_TIM_OFFS) -+#define PSCR_DEVSEL_TIM_FAST (0x0 << PSCR_DEVSEL_TIM_OFFS) -+#define PSCR_DEVSEL_TIM_MED (0x1 << PSCR_DEVSEL_TIM_OFFS) -+#define PSCR_DEVSEL_TIM_SLOW (0x2 << PSCR_DEVSEL_TIM_OFFS) -+ -+#define PSCR_SLAVE_TABORT BIT27 /* Signalled Target Abort */ -+#define PSCR_MASTER_TABORT BIT28 /* Recieved Target Abort */ -+#define PSCR_MABORT BIT29 /* Recieved Master Abort */ -+#define PSCR_SYSERR BIT30 /* Signalled system error */ -+#define PSCR_DET_PARERR BIT31 /* Detect Parity Error */ -+ -+/* PCI configuration register offset=0x08 fields -+ (PCI_CLASS_CODE_AND_REVISION_ID)(PCCRI) */ -+ -+#define PCCRIR_REVID_OFFS 0 /* Revision ID */ -+#define PCCRIR_REVID_MASK (0xff << PCCRIR_REVID_OFFS) -+ -+#define PCCRIR_FULL_CLASS_OFFS 8 /* Full Class Code */ -+#define PCCRIR_FULL_CLASS_MASK (0xffffff << PCCRIR_FULL_CLASS_OFFS) -+ -+#define PCCRIR_PROGIF_OFFS 8 /* Prog .I/F*/ -+#define PCCRIR_PROGIF_MASK (0xff << PCCRIR_PROGIF_OFFS) -+ -+#define PCCRIR_SUB_CLASS_OFFS 16 /* Sub Class*/ -+#define PCCRIR_SUB_CLASS_MASK (0xff << PCCRIR_SUB_CLASS_OFFS) -+ -+#define PCCRIR_BASE_CLASS_OFFS 24 /* Base Class*/ -+#define PCCRIR_BASE_CLASS_MASK (0xff << PCCRIR_BASE_CLASS_OFFS) -+ -+/* PCI configuration register offset=0x0C fields -+ (PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE)(PBHTLTCL) */ -+ -+#define PBHTLTCLR_CACHELINE_OFFS 0 /* Specifies the cache line size */ -+#define PBHTLTCLR_CACHELINE_MASK (0xff << PBHTLTCLR_CACHELINE_OFFS) -+ -+#define PBHTLTCLR_LATTIMER_OFFS 8 /* latency timer */ -+#define PBHTLTCLR_LATTIMER_MASK (0xff << PBHTLTCLR_LATTIMER_OFFS) -+ -+#define PBHTLTCLR_HEADTYPE_FULL_OFFS 16 /* Full Header Type */ -+#define PBHTLTCLR_HEADTYPE_FULL_MASK (0xff << PBHTLTCLR_HEADTYPE_FULL_OFFS) -+ -+#define PBHTLTCLR_MULTI_FUNC BIT23 /* Multi/Single function */ -+ -+#define PBHTLTCLR_HEADER_OFFS 16 /* Header type */ -+#define PBHTLTCLR_HEADER_MASK (0x7f << PBHTLTCLR_HEADER_OFFS) -+#define PBHTLTCLR_HEADER_STANDARD (0x0 << PBHTLTCLR_HEADER_OFFS) -+#define PBHTLTCLR_HEADER_PCI2PCI_BRIDGE (0x1 << PBHTLTCLR_HEADER_OFFS) -+ -+ -+#define PBHTLTCLR_BISTCOMP_OFFS 24 /* BIST Completion Code */ -+#define PBHTLTCLR_BISTCOMP_MASK (0xf << PBHTLTCLR_BISTCOMP_OFFS) -+ -+#define PBHTLTCLR_BISTACT BIT30 /* BIST Activate bit */ -+#define PBHTLTCLR_BISTCAP BIT31 /* BIST Capable Bit */ -+ -+ -+/* PCI Bar Base Low Register (PBBLR) */ -+#define PBBLR_IOSPACE BIT0 /* Memory Space Indicator */ -+ -+#define PBBLR_TYPE_OFFS 1 /* BAR Type/Init Val. */ -+#define PBBLR_TYPE_MASK (0x3 << PBBLR_TYPE_OFFS) -+#define PBBLR_TYPE_32BIT_ADDR (0x0 << PBBLR_TYPE_OFFS) -+#define PBBLR_TYPE_64BIT_ADDR (0x2 << PBBLR_TYPE_OFFS) -+ -+#define PBBLR_PREFETCH_EN BIT3 /* Prefetch Enable */ -+ -+ -+#define PBBLR_MEM_BASE_OFFS 4 /* Memory Bar Base address. Corresponds to -+ address bits [31:4] */ -+#define PBBLR_MEM_BASE_MASK (0xfffffff << PBBLR_MEM_BASE_OFFS) -+ -+#define PBBLR_IO_BASE_OFFS 2 /* IO Bar Base address. Corresponds to -+ address bits [31:2] */ -+#define PBBLR_IO_BASE_MASK (0x3fffffff << PBBLR_IO_BASE_OFFS) -+ -+ -+#define PBBLR_BASE_OFFS 12 /* Base address. Address bits [31:12] */ -+#define PBBLR_BASE_MASK (0xfffff << PBBLR_BASE_OFFS) -+#define PBBLR_BASE_ALIGNMET (1 << PBBLR_BASE_OFFS) -+ -+ -+/* PCI Bar Base High Fegister (PBBHR) */ -+#define PBBHR_BASE_OFFS 0 /* Base address. Address bits [31:12] */ -+#define PBBHR_BASE_MASK (0xffffffff << PBBHR_BASE_OFFS) -+ -+ -+/* PCI configuration register offset=0x2C fields -+ (PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID)(PSISVI) */ -+ -+#define PSISVIR_VENID_OFFS 0 /* Subsystem Manufacturer Vendor ID Number */ -+#define PSISVIR_VENID_MASK (0xffff << PSISVIR_VENID_OFFS) -+ -+#define PSISVIR_DEVID_OFFS 16 /* Subsystem Device ID Number */ -+#define PSISVIR_DEVID_MASK (0xffff << PSISVIR_DEVID_OFFS) -+ -+/* PCI configuration register offset=0x30 fields -+ (PCI_EXPANSION_ROM_BASE_ADDR_REG)(PERBA) */ -+ -+#define PERBAR_EXPROMEN BIT0 /* Expansion ROM Enable */ -+ -+#define PERBAR_BASE_OFFS 12 /* Expansion ROM Base Address */ -+#define PERBAR_BASE_MASK (0xfffff << PERBAR_BASE_OFFS) -+ -+/* PCI configuration register offset=0x34 fields -+ (PCI_CAPABILTY_LIST_POINTER)(PCLP) */ -+ -+#define PCLPR_CAPPTR_OFFS 0 /* Capability List Pointer */ -+#define PCLPR_CAPPTR_MASK (0xff << PCLPR_CAPPTR_OFFS) -+ -+/* PCI configuration register offset=0x3C fields -+ (PCI_INTERRUPT_PIN_AND_LINE)(PIPL) */ -+ -+#define PIPLR_INTLINE_OFFS 0 /* Interrupt line (IRQ) */ -+#define PIPLR_INTLINE_MASK (0xff << PIPLR_INTLINE_OFFS) -+ -+#define PIPLR_INTPIN_OFFS 8 /* interrupt pin (A,B,C,D) */ -+#define PIPLR_INTPIN_MASK (0xff << PIPLR_INTPIN_OFFS) -+ -+#define PIPLR_MINGRANT_OFFS 16 /* Minimum Grant on 250 nano seconds units */ -+#define PIPLR_MINGRANT_MASK (0xff << PIPLR_MINGRANT_OFFS) -+ -+#define PIPLR_MAXLATEN_OFFS 24 /* Maximum latency on 250 nano seconds units */ -+#define PIPLR_MAXLATEN_MASK (0xff << PIPLR_MAXLATEN_OFFS) -+ -+#endif /* #ifndef __INCPCIIFREGSH */ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.c 2010-11-09 20:28:11.632495445 +0100 -@@ -0,0 +1,1006 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+/* includes */ -+#include "mvPciUtils.h" -+ -+#include "ctrlEnv/mvCtrlEnvLib.h" -+ -+/* #define MV_DEBUG */ -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+ #define mvOsPrintf printf -+#else -+ #define DB(x) -+#endif -+ -+/* -+This module only support scanning of Header type 00h of pci devices -+There is no suppotr for Header type 01h of pci devices ( PCI bridges ) -+*/ -+ -+ -+static MV_STATUS pciDetectDevice(MV_U32 pciIf, -+ MV_U32 bus, -+ MV_U32 dev, -+ MV_U32 func, -+ MV_PCI_DEVICE *pPciAgent); -+ -+static MV_U32 pciDetectDeviceBars(MV_U32 pciIf, -+ MV_U32 bus, -+ MV_U32 dev, -+ MV_U32 func, -+ MV_PCI_DEVICE *pPciAgent); -+ -+ -+ -+ -+ -+ -+/******************************************************************************* -+* mvPciScan - Scan a PCI interface bus -+* -+* DESCRIPTION: -+* Performs a full scan on a PCI interface and returns all possible details -+* on the agents found on the bus. -+* -+* INPUT: -+* pciIf - PCI Interface -+* pPciAgents - Pointer to an Array of the pci agents to be detected -+* pPciAgentsNum - pPciAgents array maximum number of elements -+* -+* OUTPUT: -+* pPciAgents - Array of the pci agents detected on the bus -+* pPciAgentsNum - Number of pci agents detected on the bus -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+ -+MV_STATUS mvPciScan(MV_U32 pciIf, -+ MV_PCI_DEVICE *pPciAgents, -+ MV_U32 *pPciAgentsNum) -+{ -+ -+ MV_U32 devIndex,funcIndex=0,busIndex=0,detectedDevNum=0; -+ MV_U32 localBus=mvPciIfLocalBusNumGet(pciIf); -+ MV_PCI_DEVICE *pPciDevice; -+ MV_PCI_DEVICE *pMainDevice; -+ -+ DB(mvOsPrintf("mvPciScan: PCI interface num %d\n", pciIf)); -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPexMaxIfGet()) -+ { -+ DB(mvOsPrintf("mvPciScan: ERR. Invalid PCI interface num %d\n", pciIf)); -+ return MV_BAD_PARAM; -+ } -+ if (NULL == pPciAgents) -+ { -+ DB(mvOsPrintf("mvPciScan: ERR. pPciAgents=NULL \n")); -+ return MV_BAD_PARAM; -+ } -+ if (NULL == pPciAgentsNum) -+ { -+ DB(mvOsPrintf("mvPciScan: ERR. pPciAgentsNum=NULL \n")); -+ return MV_BAD_PARAM; -+ } -+ -+ -+ DB(mvOsPrintf("mvPciScan: PCI interface num %d mvPciMasterEnable\n", pciIf)); -+ /* Master enable the MV PCI master */ -+ if (MV_OK != mvPciIfMasterEnable(pciIf,MV_TRUE)) -+ { -+ DB(mvOsPrintf("mvPciScan: ERR. mvPciMasterEnable failed \n")); -+ return MV_ERROR; -+ -+ } -+ -+ DB(mvOsPrintf("mvPciScan: PCI interface num scan%d\n", pciIf)); -+ -+ /* go through all busses */ -+ for (busIndex=localBus ; busIndex < MAX_PCI_BUSSES ; busIndex++) -+ { -+ /* go through all possible devices on the local bus */ -+ for (devIndex=0 ; devIndex < MAX_PCI_DEVICES ; devIndex++) -+ { -+ /* always start with function equal to zero */ -+ funcIndex=0; -+ -+ pPciDevice=&pPciAgents[detectedDevNum]; -+ DB(mvOsPrintf("mvPciScan: PCI interface num scan%d:%d\n", busIndex, devIndex)); -+ -+ if (MV_ERROR == pciDetectDevice(pciIf, -+ busIndex, -+ devIndex, -+ funcIndex, -+ pPciDevice)) -+ { -+ /* no device detected , try the next address */ -+ continue; -+ } -+ -+ /* We are here ! means we have detected a device*/ -+ /* always we start with only one function per device */ -+ pMainDevice = pPciDevice; -+ pPciDevice->funtionsNum = 1; -+ -+ -+ /* move on */ -+ detectedDevNum++; -+ -+ -+ /* check if we have no more room for a new device */ -+ if (detectedDevNum == *pPciAgentsNum) -+ { -+ DB(mvOsPrintf("mvPciScan: ERR. array passed too small \n")); -+ return MV_ERROR; -+ } -+ -+ /* check the detected device if it is a multi functional device then -+ scan all device functions*/ -+ if (pPciDevice->isMultiFunction == MV_TRUE) -+ { -+ /* start with function number 1 because we have already detected -+ function 0 */ -+ for (funcIndex=1; funcIndexfuntionsNum++; -+ detectedDevNum++; -+ -+ /* check if we have no more room for a new device */ -+ if (detectedDevNum == *pPciAgentsNum) -+ { -+ DB(mvOsPrintf("mvPciScan: ERR. Array too small\n")); -+ return MV_ERROR; -+ } -+ -+ -+ } -+ } -+ -+ } -+ -+ } -+ -+ /* return the number of devices actually detected on the bus ! */ -+ *pPciAgentsNum = detectedDevNum; -+ -+ return MV_OK; -+ -+} -+ -+ -+/******************************************************************************* -+* pciDetectDevice - Detect a pci device parameters -+* -+* DESCRIPTION: -+* This function detect if a pci agent exist on certain address ! -+* and if exists then it fills all possible information on the -+* agent -+* -+* INPUT: -+* pciIf - PCI Interface -+* bus - Bus number -+* dev - Device number -+* func - Function number -+* -+* -+* -+* OUTPUT: -+* pPciAgent - pointer to the pci agent filled with its information -+* -+* RETURN: -+* MV_ERROR if no device , MV_OK otherwise -+* -+*******************************************************************************/ -+ -+static MV_STATUS pciDetectDevice(MV_U32 pciIf, -+ MV_U32 bus, -+ MV_U32 dev, -+ MV_U32 func, -+ MV_PCI_DEVICE *pPciAgent) -+{ -+ MV_U32 pciData; -+ -+ /* no Parameters checking ! because it is static function and it is assumed -+ that all parameters were checked in the calling function */ -+ -+ -+ /* Try read the PCI Vendor ID and Device ID */ -+ -+ /* We will scan only ourselves and the PCI slots that exist on the -+ board, because we may have a case that we have one slot that has -+ a Cardbus connector, and because CardBus answers all IDsels we want -+ to scan only this slot and ourseleves. -+ -+ */ -+ #if defined(MV_INCLUDE_PCI) -+ if ((PCI_IF_TYPE_CONVEN_PCIX == mvPciIfTypeGet(pciIf)) && -+ (DB_88F5181_DDR1_PRPMC != mvBoardIdGet()) && -+ (DB_88F5181_DDR1_PEXPCI != mvBoardIdGet()) && -+ (DB_88F5181_DDR1_MNG != mvBoardIdGet())) -+ { -+ -+ if (mvBoardIsOurPciSlot(bus, dev) == MV_FALSE) -+ { -+ return MV_ERROR; -+ } -+ } -+ #endif /* defined(MV_INCLUDE_PCI) */ -+ -+ pciData = mvPciIfConfigRead(pciIf, bus,dev,func, PCI_DEVICE_AND_VENDOR_ID); -+ -+ if (PCI_ERROR_CODE == pciData) -+ { -+ /* no device exist */ -+ return MV_ERROR; -+ } -+ -+ /* we are here ! means a device is detected */ -+ -+ /* fill basic information */ -+ pPciAgent->busNumber=bus; -+ pPciAgent->deviceNum=dev; -+ pPciAgent->function=func; -+ -+ /* Fill the PCI Vendor ID and Device ID */ -+ -+ pPciAgent->venID = (pciData & PDVIR_VEN_ID_MASK) >> PDVIR_VEN_ID_OFFS; -+ pPciAgent->deviceID = (pciData & PDVIR_DEV_ID_MASK) >> PDVIR_DEV_ID_OFFS; -+ -+ /* Read Status and command */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_STATUS_AND_COMMAND); -+ -+ -+ /* Fill related Status and Command information*/ -+ -+ if (pciData & PSCR_TAR_FAST_BB) -+ { -+ pPciAgent->isFastB2BCapable = MV_TRUE; -+ } -+ else -+ { -+ pPciAgent->isFastB2BCapable = MV_FALSE; -+ } -+ -+ if (pciData & PSCR_CAP_LIST) -+ { -+ pPciAgent->isCapListSupport=MV_TRUE; -+ } -+ else -+ { -+ pPciAgent->isCapListSupport=MV_FALSE; -+ } -+ -+ if (pciData & PSCR_66MHZ_EN) -+ { -+ pPciAgent->is66MHZCapable=MV_TRUE; -+ } -+ else -+ { -+ pPciAgent->is66MHZCapable=MV_FALSE; -+ } -+ -+ /* Read Class Code and Revision */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_CLASS_CODE_AND_REVISION_ID); -+ -+ -+ pPciAgent->baseClassCode = -+ (pciData & PCCRIR_BASE_CLASS_MASK) >> PCCRIR_BASE_CLASS_OFFS; -+ -+ pPciAgent->subClassCode = -+ (pciData & PCCRIR_SUB_CLASS_MASK) >> PCCRIR_SUB_CLASS_OFFS; -+ -+ pPciAgent->progIf = -+ (pciData & PCCRIR_PROGIF_MASK) >> PCCRIR_PROGIF_OFFS; -+ -+ pPciAgent->revisionID = -+ (pciData & PCCRIR_REVID_MASK) >> PCCRIR_REVID_OFFS; -+ -+ /* Read PCI_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE); -+ -+ -+ -+ pPciAgent->pciCacheLine= -+ (pciData & PBHTLTCLR_CACHELINE_MASK ) >> PBHTLTCLR_CACHELINE_OFFS; -+ pPciAgent->pciLatencyTimer= -+ (pciData & PBHTLTCLR_LATTIMER_MASK) >> PBHTLTCLR_LATTIMER_OFFS; -+ -+ switch (pciData & PBHTLTCLR_HEADER_MASK) -+ { -+ case PBHTLTCLR_HEADER_STANDARD: -+ -+ pPciAgent->pciHeader=MV_PCI_STANDARD; -+ break; -+ case PBHTLTCLR_HEADER_PCI2PCI_BRIDGE: -+ -+ pPciAgent->pciHeader=MV_PCI_PCI2PCI_BRIDGE; -+ break; -+ -+ } -+ -+ if (pciData & PBHTLTCLR_MULTI_FUNC) -+ { -+ pPciAgent->isMultiFunction=MV_TRUE; -+ } -+ else -+ { -+ pPciAgent->isMultiFunction=MV_FALSE; -+ } -+ -+ if (pciData & PBHTLTCLR_BISTCAP) -+ { -+ pPciAgent->isBISTCapable=MV_TRUE; -+ } -+ else -+ { -+ pPciAgent->isBISTCapable=MV_FALSE; -+ } -+ -+ -+ /* read this device pci bars */ -+ -+ pciDetectDeviceBars(pciIf, -+ bus,dev,func, -+ pPciAgent); -+ -+ -+ /* check if we are bridge*/ -+ if ((pPciAgent->baseClassCode == PCI_BRIDGE_CLASS)&& -+ (pPciAgent->subClassCode == P2P_BRIDGE_SUB_CLASS_CODE)) -+ { -+ -+ /* Read P2P_BUSSES_NUM */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ P2P_BUSSES_NUM); -+ -+ pPciAgent->p2pPrimBusNum = -+ (pciData & PBM_PRIME_BUS_NUM_MASK) >> PBM_PRIME_BUS_NUM_OFFS; -+ -+ pPciAgent->p2pSecBusNum = -+ (pciData & PBM_SEC_BUS_NUM_MASK) >> PBM_SEC_BUS_NUM_OFFS; -+ -+ pPciAgent->p2pSubBusNum = -+ (pciData & PBM_SUB_BUS_NUM_MASK) >> PBM_SUB_BUS_NUM_OFFS; -+ -+ pPciAgent->p2pSecLatencyTimer = -+ (pciData & PBM_SEC_LAT_TMR_MASK) >> PBM_SEC_LAT_TMR_OFFS; -+ -+ /* Read P2P_IO_BASE_LIMIT_SEC_STATUS */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ P2P_IO_BASE_LIMIT_SEC_STATUS); -+ -+ pPciAgent->p2pSecStatus = -+ (pciData & PIBLSS_SEC_STATUS_MASK) >> PIBLSS_SEC_STATUS_OFFS; -+ -+ -+ pPciAgent->p2pIObase = -+ (pciData & PIBLSS_IO_BASE_MASK) << PIBLSS_IO_LIMIT_OFFS; -+ -+ /* clear low address (should be zero)*/ -+ pPciAgent->p2pIObase &= PIBLSS_HIGH_ADDR_MASK; -+ -+ pPciAgent->p2pIOLimit = -+ (pciData & PIBLSS_IO_LIMIT_MASK); -+ -+ /* fill low address with 0xfff */ -+ pPciAgent->p2pIOLimit |= PIBLSS_LOW_ADDR_MASK; -+ -+ -+ switch ((pciData & PIBLSS_ADD_CAP_MASK) >> PIBLSS_ADD_CAP_OFFS) -+ { -+ case PIBLSS_ADD_CAP_16BIT: -+ -+ pPciAgent->bIO32 = MV_FALSE; -+ -+ break; -+ case PIBLSS_ADD_CAP_32BIT: -+ -+ pPciAgent->bIO32 = MV_TRUE; -+ -+ /* Read P2P_IO_BASE_LIMIT_UPPER_16 */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ P2P_IO_BASE_LIMIT_UPPER_16); -+ -+ pPciAgent->p2pIObase |= -+ (pciData & PRBU_IO_UPP_BASE_MASK) << PRBU_IO_UPP_LIMIT_OFFS; -+ -+ -+ pPciAgent->p2pIOLimit |= -+ (pciData & PRBU_IO_UPP_LIMIT_MASK); -+ -+ break; -+ -+ } -+ -+ -+ /* Read P2P_MEM_BASE_LIMIT */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ P2P_MEM_BASE_LIMIT); -+ -+ pPciAgent->p2pMemBase = -+ (pciData & PMBL_MEM_BASE_MASK) << PMBL_MEM_LIMIT_OFFS; -+ -+ /* clear low address */ -+ pPciAgent->p2pMemBase &= PMBL_HIGH_ADDR_MASK; -+ -+ pPciAgent->p2pMemLimit = -+ (pciData & PMBL_MEM_LIMIT_MASK); -+ -+ /* add 0xfffff */ -+ pPciAgent->p2pMemLimit |= PMBL_LOW_ADDR_MASK; -+ -+ -+ /* Read P2P_PREF_MEM_BASE_LIMIT */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ P2P_PREF_MEM_BASE_LIMIT); -+ -+ -+ pPciAgent->p2pPrefMemBase = -+ (pciData & PRMBL_PREF_MEM_BASE_MASK) << PRMBL_PREF_MEM_LIMIT_OFFS; -+ -+ /* get high address only */ -+ pPciAgent->p2pPrefMemBase &= PRMBL_HIGH_ADDR_MASK; -+ -+ -+ -+ pPciAgent->p2pPrefMemLimit = -+ (pciData & PRMBL_PREF_MEM_LIMIT_MASK); -+ -+ /* add 0xfffff */ -+ pPciAgent->p2pPrefMemLimit |= PRMBL_LOW_ADDR_MASK; -+ -+ switch (pciData & PRMBL_ADD_CAP_MASK) -+ { -+ case PRMBL_ADD_CAP_32BIT: -+ -+ pPciAgent->bPrefMem64 = MV_FALSE; -+ -+ /* Read P2P_PREF_BASE_UPPER_32 */ -+ pPciAgent->p2pPrefBaseUpper32Bits = 0; -+ -+ /* Read P2P_PREF_LIMIT_UPPER_32 */ -+ pPciAgent->p2pPrefLimitUpper32Bits = 0; -+ -+ break; -+ case PRMBL_ADD_CAP_64BIT: -+ -+ pPciAgent->bPrefMem64 = MV_TRUE; -+ -+ /* Read P2P_PREF_BASE_UPPER_32 */ -+ pPciAgent->p2pPrefBaseUpper32Bits = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ P2P_PREF_BASE_UPPER_32); -+ -+ /* Read P2P_PREF_LIMIT_UPPER_32 */ -+ pPciAgent->p2pPrefLimitUpper32Bits = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ P2P_PREF_LIMIT_UPPER_32); -+ -+ break; -+ -+ } -+ -+ } -+ else /* no bridge */ -+ { -+ /* Read PCI_SUBSYS_ID_AND_SUBSYS_VENDOR_ID */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_SUBSYS_ID_AND_SUBSYS_VENDOR_ID); -+ -+ -+ pPciAgent->subSysVenID = -+ (pciData & PSISVIR_VENID_MASK) >> PSISVIR_VENID_OFFS; -+ pPciAgent->subSysID = -+ (pciData & PSISVIR_DEVID_MASK) >> PSISVIR_DEVID_OFFS; -+ -+ -+ /* Read PCI_EXPANSION_ROM_BASE_ADDR_REG */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_EXPANSION_ROM_BASE_ADDR_REG); -+ -+ -+ if (pciData & PERBAR_EXPROMEN) -+ { -+ pPciAgent->isExpRom = MV_TRUE; -+ } -+ else -+ { -+ pPciAgent->isExpRom = MV_FALSE; -+ } -+ -+ pPciAgent->expRomAddr = -+ (pciData & PERBAR_BASE_MASK) >> PERBAR_BASE_OFFS; -+ -+ } -+ -+ -+ if (MV_TRUE == pPciAgent->isCapListSupport) -+ { -+ /* Read PCI_CAPABILTY_LIST_POINTER */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_CAPABILTY_LIST_POINTER); -+ -+ pPciAgent->capListPointer = -+ (pciData & PCLPR_CAPPTR_MASK) >> PCLPR_CAPPTR_OFFS; -+ -+ } -+ -+ /* Read PCI_INTERRUPT_PIN_AND_LINE */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_INTERRUPT_PIN_AND_LINE); -+ -+ -+ pPciAgent->irqLine= -+ (pciData & PIPLR_INTLINE_MASK) >> PIPLR_INTLINE_OFFS; -+ -+ pPciAgent->intPin= -+ (MV_PCI_INT_PIN)(pciData & PIPLR_INTPIN_MASK) >> PIPLR_INTPIN_OFFS; -+ -+ pPciAgent->minGrant= -+ (pciData & PIPLR_MINGRANT_MASK) >> PIPLR_MINGRANT_OFFS; -+ pPciAgent->maxLatency= -+ (pciData & PIPLR_MAXLATEN_MASK) >> PIPLR_MAXLATEN_OFFS; -+ -+ mvPciClassNameGet(pPciAgent->baseClassCode, -+ (MV_8 *)pPciAgent->type); -+ -+ return MV_OK; -+ -+ -+} -+ -+/******************************************************************************* -+* pciDetectDeviceBars - Detect a pci device bars -+* -+* DESCRIPTION: -+* This function detects all pci agent bars -+* -+* INPUT: -+* pciIf - PCI Interface -+* bus - Bus number -+* dev - Device number -+* func - Function number -+* -+* -+* -+* OUTPUT: -+* pPciAgent - pointer to the pci agent filled with its information -+* -+* RETURN: -+* detected bars number -+* -+*******************************************************************************/ -+static MV_U32 pciDetectDeviceBars(MV_U32 pciIf, -+ MV_U32 bus, -+ MV_U32 dev, -+ MV_U32 func, -+ MV_PCI_DEVICE *pPciAgent) -+{ -+ MV_U32 pciData,barIndex,detectedBar=0; -+ MV_U32 tmpBaseHigh=0,tmpBaseLow=0; -+ MV_U32 pciMaxBars=0; -+ -+ pPciAgent->barsNum=0; -+ -+ /* check if we are bridge*/ -+ if ((pPciAgent->baseClassCode == PCI_BRIDGE_CLASS)&& -+ (pPciAgent->subClassCode == P2P_BRIDGE_SUB_CLASS_CODE)) -+ { -+ pciMaxBars = 2; -+ } -+ else /* no bridge */ -+ { -+ pciMaxBars = 6; -+ } -+ -+ /* read this device pci bars */ -+ for (barIndex = 0 ; barIndex < pciMaxBars ; barIndex++ ) -+ { -+ /* Read PCI_MEMORY_BAR_BASE_ADDR */ -+ tmpBaseLow = pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex)); -+ -+ pPciAgent->pciBar[detectedBar].barOffset = -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex); -+ -+ /* check if the bar is 32bit or 64bit bar */ -+ switch (pciData & PBBLR_TYPE_MASK) -+ { -+ case PBBLR_TYPE_32BIT_ADDR: -+ pPciAgent->pciBar[detectedBar].barType = PCI_32BIT_BAR; -+ break; -+ case PBBLR_TYPE_64BIT_ADDR: -+ pPciAgent->pciBar[detectedBar].barType = PCI_64BIT_BAR; -+ break; -+ -+ } -+ -+ /* check if it is memory or IO bar */ -+ if (pciData & PBBLR_IOSPACE) -+ { -+ pPciAgent->pciBar[detectedBar].barMapping=PCI_IO_BAR; -+ } -+ else -+ { -+ pPciAgent->pciBar[detectedBar].barMapping=PCI_MEMORY_BAR; -+ } -+ -+ /* if it is memory bar then check if it is prefetchable */ -+ if (PCI_MEMORY_BAR == pPciAgent->pciBar[detectedBar].barMapping) -+ { -+ if (pciData & PBBLR_PREFETCH_EN) -+ { -+ pPciAgent->pciBar[detectedBar].isPrefetchable = MV_TRUE; -+ } -+ else -+ { -+ pPciAgent->pciBar[detectedBar].isPrefetchable = MV_FALSE; -+ } -+ -+ pPciAgent->pciBar[detectedBar].barBaseLow = -+ pciData & PBBLR_MEM_BASE_MASK; -+ -+ -+ } -+ else /* IO Bar */ -+ { -+ pPciAgent->pciBar[detectedBar].barBaseLow = -+ pciData & PBBLR_IO_BASE_MASK; -+ -+ } -+ -+ pPciAgent->pciBar[detectedBar].barBaseHigh=0; -+ -+ if (PCI_64BIT_BAR == pPciAgent->pciBar[detectedBar].barType) -+ { -+ barIndex++; -+ -+ tmpBaseHigh = pPciAgent->pciBar[detectedBar].barBaseHigh = -+ mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex)); -+ -+ -+ } -+ -+ /* calculating full base address (64bit) */ -+ pPciAgent->pciBar[detectedBar].barBaseAddr = -+ (MV_U64)pPciAgent->pciBar[detectedBar].barBaseHigh; -+ -+ pPciAgent->pciBar[detectedBar].barBaseAddr <<= 32; -+ -+ pPciAgent->pciBar[detectedBar].barBaseAddr |= -+ (MV_U64)pPciAgent->pciBar[detectedBar].barBaseLow; -+ -+ -+ -+ /* get the sizes of the the bar */ -+ -+ pPciAgent->pciBar[detectedBar].barSizeHigh=0; -+ -+ if ((PCI_64BIT_BAR == pPciAgent->pciBar[detectedBar].barType) && -+ (PCI_MEMORY_BAR == pPciAgent->pciBar[detectedBar].barMapping)) -+ -+ { -+ /* write oxffffffff to the bar to get the size */ -+ /* start with sizelow ( original value was saved in tmpBaseLow ) */ -+ mvPciIfConfigWrite(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex-1), -+ 0xffffffff); -+ -+ /* read size */ -+ pPciAgent->pciBar[detectedBar].barSizeLow = -+ mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex-1)); -+ -+ -+ -+ /* restore original value */ -+ mvPciIfConfigWrite(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex-1), -+ tmpBaseLow); -+ -+ -+ /* now do the same for BaseHigh */ -+ -+ /* write oxffffffff to the bar to get the size */ -+ mvPciIfConfigWrite(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex), -+ 0xffffffff); -+ -+ /* read size */ -+ pPciAgent->pciBar[detectedBar].barSizeHigh = -+ mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex)); -+ -+ /* restore original value */ -+ mvPciIfConfigWrite(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex), -+ tmpBaseHigh); -+ -+ if ((0 == pPciAgent->pciBar[detectedBar].barSizeLow)&& -+ (0 == pPciAgent->pciBar[detectedBar].barSizeHigh)) -+ { -+ /* this bar is not applicable for this device, -+ ignore all previous settings and check the next bar*/ -+ -+ /* we though this was a 64bit bar , and it seems this -+ was wrong ! so decrement barIndex */ -+ barIndex--; -+ continue; -+ } -+ -+ /* calculate the full 64 bit size */ -+ -+ if (0 != pPciAgent->pciBar[detectedBar].barSizeHigh) -+ { -+ pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_MEM_BASE_MASK; -+ -+ pPciAgent->pciBar[detectedBar].barSizeLow = -+ ~pPciAgent->pciBar[detectedBar].barSizeLow + 1; -+ -+ pPciAgent->pciBar[detectedBar].barSizeHigh = 0; -+ -+ } -+ else -+ { -+ -+ pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_MEM_BASE_MASK; -+ -+ pPciAgent->pciBar[detectedBar].barSizeLow = -+ ~pPciAgent->pciBar[detectedBar].barSizeLow + 1; -+ -+ pPciAgent->pciBar[detectedBar].barSizeHigh = 0; -+ -+ } -+ -+ -+ -+ } -+ else /* 32bit bar */ -+ { -+ /* write oxffffffff to the bar to get the size */ -+ mvPciIfConfigWrite(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex), -+ 0xffffffff); -+ -+ /* read size */ -+ pPciAgent->pciBar[detectedBar].barSizeLow = -+ mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex)); -+ -+ if (0 == pPciAgent->pciBar[detectedBar].barSizeLow) -+ { -+ /* this bar is not applicable for this device, -+ ignore all previous settings and check the next bar*/ -+ continue; -+ } -+ -+ -+ /* restore original value */ -+ mvPciIfConfigWrite(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex), -+ tmpBaseLow); -+ -+ /* calculate size low */ -+ -+ if (PCI_MEMORY_BAR == pPciAgent->pciBar[detectedBar].barMapping) -+ { -+ pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_MEM_BASE_MASK; -+ } -+ else -+ { -+ pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_IO_BASE_MASK; -+ } -+ -+ pPciAgent->pciBar[detectedBar].barSizeLow = -+ ~pPciAgent->pciBar[detectedBar].barSizeLow + 1; -+ -+ pPciAgent->pciBar[detectedBar].barSizeHigh = 0; -+ pPciAgent->pciBar[detectedBar].barSize = -+ (MV_U64)pPciAgent->pciBar[detectedBar].barSizeLow; -+ -+ -+ } -+ -+ /* we are here ! this means we have already detected a bar for -+ this device , now move on */ -+ -+ detectedBar++; -+ pPciAgent->barsNum++; -+ } -+ -+ return detectedBar; -+} -+ -+ -+/******************************************************************************* -+* mvPciClassNameGet - get PCI class name -+* -+* DESCRIPTION: -+* This function returns the PCI class name -+* -+* INPUT: -+* baseClassCode - Base Class Code. -+* -+* OUTPUT: -+* pType - the class name -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciClassNameGet(MV_U32 baseClassCode, MV_8 *pType) -+{ -+ -+ switch(baseClassCode) -+ { -+ case 0x0: -+ strcpy(pType,"Old generation device"); -+ break; -+ case 0x1: -+ strcpy(pType,"Mass storage controller"); -+ break; -+ case 0x2: -+ strcpy(pType,"Network controller"); -+ break; -+ case 0x3: -+ strcpy(pType,"Display controller"); -+ break; -+ case 0x4: -+ strcpy(pType,"Multimedia device"); -+ break; -+ case 0x5: -+ strcpy(pType,"Memory controller"); -+ break; -+ case 0x6: -+ strcpy(pType,"Bridge Device"); -+ break; -+ case 0x7: -+ strcpy(pType,"Simple Communication controllers"); -+ break; -+ case 0x8: -+ strcpy(pType,"Base system peripherals"); -+ break; -+ case 0x9: -+ strcpy(pType,"Input Devices"); -+ break; -+ case 0xa: -+ strcpy(pType,"Docking stations"); -+ break; -+ case 0xb: -+ strcpy(pType,"Processors"); -+ break; -+ case 0xc: -+ strcpy(pType,"Serial bus controllers"); -+ break; -+ case 0xd: -+ strcpy(pType,"Wireless controllers"); -+ break; -+ case 0xe: -+ strcpy(pType,"Intelligent I/O controllers"); -+ break; -+ case 0xf: -+ strcpy(pType,"Satellite communication controllers"); -+ break; -+ case 0x10: -+ strcpy(pType,"Encryption/Decryption controllers"); -+ break; -+ case 0x11: -+ strcpy(pType,"Data acquisition and signal processing controllers"); -+ break; -+ default: -+ strcpy(pType,"Unknown device"); -+ break; -+ } -+ -+ return MV_OK; -+ -+} -+ -+ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.h 2010-11-09 20:28:11.662495451 +0100 -@@ -0,0 +1,323 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvPciUtilsh -+#define __INCmvPciUtilsh -+ -+/* -+This module only support scanning of Header type 00h of pci devices -+There is no suppotr for Header type 01h of pci devices ( PCI bridges ) -+*/ -+ -+/* includes */ -+#include "mvSysHwConfig.h" -+#include "pci-if/mvPciIf.h" -+#include "pci/mvPciRegs.h" -+ -+ -+ -+/* PCI base address low bar mask */ -+#define PCI_ERROR_CODE 0xffffffff -+ -+#define PCI_BRIDGE_CLASS 0x6 -+#define P2P_BRIDGE_SUB_CLASS_CODE 0x4 -+ -+ -+#define P2P_BUSSES_NUM 0x18 -+#define P2P_IO_BASE_LIMIT_SEC_STATUS 0x1C -+#define P2P_MEM_BASE_LIMIT 0x20 -+#define P2P_PREF_MEM_BASE_LIMIT 0x24 -+#define P2P_PREF_BASE_UPPER_32 0x28 -+#define P2P_PREF_LIMIT_UPPER_32 0x2C -+#define P2P_IO_BASE_LIMIT_UPPER_16 0x30 -+#define P2P_EXP_ROM 0x38 -+ -+/* P2P_BUSSES_NUM (PBM) */ -+ -+#define PBM_PRIME_BUS_NUM_OFFS 0 -+#define PBM_PRIME_BUS_NUM_MASK (0xff << PBM_PRIME_BUS_NUM_OFFS) -+ -+#define PBM_SEC_BUS_NUM_OFFS 8 -+#define PBM_SEC_BUS_NUM_MASK (0xff << PBM_SEC_BUS_NUM_OFFS) -+ -+#define PBM_SUB_BUS_NUM_OFFS 16 -+#define PBM_SUB_BUS_NUM_MASK (0xff << PBM_SUB_BUS_NUM_OFFS) -+ -+#define PBM_SEC_LAT_TMR_OFFS 24 -+#define PBM_SEC_LAT_TMR_MASK (0xff << PBM_SEC_LAT_TMR_OFFS) -+ -+/* P2P_IO_BASE_LIMIT_SEC_STATUS (PIBLSS) */ -+ -+#define PIBLSS_IO_BASE_OFFS 0 -+#define PIBLSS_IO_BASE_MASK (0xff << PIBLSS_IO_BASE_OFFS) -+ -+#define PIBLSS_ADD_CAP_OFFS 0 -+#define PIBLSS_ADD_CAP_MASK (0x3 << PIBLSS_ADD_CAP_OFFS) -+#define PIBLSS_ADD_CAP_16BIT (0x0 << PIBLSS_ADD_CAP_OFFS) -+#define PIBLSS_ADD_CAP_32BIT (0x1 << PIBLSS_ADD_CAP_OFFS) -+ -+#define PIBLSS_LOW_ADDR_OFFS 0 -+#define PIBLSS_LOW_ADDR_MASK (0xFFF << PIBLSS_LOW_ADDR_OFFS) -+ -+#define PIBLSS_HIGH_ADDR_OFFS 12 -+#define PIBLSS_HIGH_ADDR_MASK (0xF << PIBLSS_HIGH_ADDR_OFFS) -+ -+#define PIBLSS_IO_LIMIT_OFFS 8 -+#define PIBLSS_IO_LIMIT_MASK (0xff << PIBLSS_IO_LIMIT_OFFS) -+ -+#define PIBLSS_SEC_STATUS_OFFS 16 -+#define PIBLSS_SEC_STATUS_MASK (0xffff << PIBLSS_SEC_STATUS_OFFS) -+ -+ -+/* P2P_MEM_BASE_LIMIT (PMBL)*/ -+ -+#define PMBL_MEM_BASE_OFFS 0 -+#define PMBL_MEM_BASE_MASK (0xffff << PMBL_MEM_BASE_OFFS) -+ -+#define PMBL_MEM_LIMIT_OFFS 16 -+#define PMBL_MEM_LIMIT_MASK (0xffff << PMBL_MEM_LIMIT_OFFS) -+ -+ -+#define PMBL_LOW_ADDR_OFFS 0 -+#define PMBL_LOW_ADDR_MASK (0xFFFFF << PMBL_LOW_ADDR_OFFS) -+ -+#define PMBL_HIGH_ADDR_OFFS 20 -+#define PMBL_HIGH_ADDR_MASK (0xFFF << PMBL_HIGH_ADDR_OFFS) -+ -+ -+/* P2P_PREF_MEM_BASE_LIMIT (PRMBL) */ -+ -+#define PRMBL_PREF_MEM_BASE_OFFS 0 -+#define PRMBL_PREF_MEM_BASE_MASK (0xffff << PRMBL_PREF_MEM_BASE_OFFS) -+ -+#define PRMBL_PREF_MEM_LIMIT_OFFS 16 -+#define PRMBL_PREF_MEM_LIMIT_MASK (0xffff<= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexModeGet: ERR. Invalid PEX interface %d\n",pexIf); -+ return MV_ERROR; -+ } -+ } -+ -+ pexData = MV_REG_READ(PEX_CTRL_REG(pexIf)); -+ -+ switch (pexData & PXCR_DEV_TYPE_CTRL_MASK) -+ { -+ case PXCR_DEV_TYPE_CTRL_CMPLX: -+ pexMode->pexType = MV_PEX_ROOT_COMPLEX; -+ break; -+ case PXCR_DEV_TYPE_CTRL_POINT: -+ pexMode->pexType = MV_PEX_END_POINT; -+ break; -+ -+ } -+ -+ /* Check if we have link */ -+ if (MV_REG_READ(PEX_STATUS_REG(pexIf)) & PXSR_DL_DOWN) -+ { -+ pexMode->pexLinkUp = MV_FALSE; -+ -+ /* If there is no link, the auto negotiation data is worthless */ -+ pexMode->pexWidth = MV_PEX_WITDH_INVALID; -+ } -+ else -+ { -+ pexMode->pexLinkUp = MV_TRUE; -+ -+ /* We have link. The link width is now valid */ -+ pexData = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG)); -+ pexMode->pexWidth = ((pexData & PXLCSR_NEG_LNK_WDTH_MASK) >> -+ PXLCSR_NEG_LNK_WDTH_OFFS); -+ } -+ -+ return MV_OK; -+} -+ -+ -+/* PEX configuration space read write */ -+ -+/******************************************************************************* -+* mvPexConfigRead - Read from configuration space -+* -+* DESCRIPTION: -+* This function performs a 32 bit read from PEX configuration space. -+* It supports both type 0 and type 1 of Configuration Transactions -+* (local and over bridge). In order to read from local bus segment, use -+* bus number retrieved from mvPexLocalBusNumGet(). Other bus numbers -+* will result configuration transaction of type 1 (over bridge). -+* -+* INPUT: -+* pexIf - PEX interface number. -+* bus - PEX segment bus number. -+* dev - PEX device number. -+* func - Function number. -+* regOffs - Register offset. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit register data, 0xffffffff on error -+* -+*******************************************************************************/ -+MV_U32 mvPexConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, -+ MV_U32 regOff) -+{ -+#if defined(PCIE_VIRTUAL_BRIDGE_SUPPORT) -+ return mvPexVrtBrgConfigRead (pexIf, bus, dev, func, regOff); -+} -+ -+MV_U32 mvPexHwConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, -+ MV_U32 regOff) -+{ -+#endif -+ MV_U32 pexData = 0; -+ MV_U32 localDev,localBus; -+ -+ /* Parameter checking */ -+ if (PEX_DEFAULT_IF != pexIf) -+ { -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexConfigRead: ERR. Invalid PEX interface %d\n",pexIf); -+ return 0xFFFFFFFF; -+ } -+ } -+ -+ if (dev >= MAX_PEX_DEVICES) -+ { -+ DB(mvOsPrintf("mvPexConfigRead: ERR. device number illigal %d\n", dev)); -+ return 0xFFFFFFFF; -+ } -+ -+ if (func >= MAX_PEX_FUNCS) -+ { -+ DB(mvOsPrintf("mvPexConfigRead: ERR. function num illigal %d\n", func)); -+ return 0xFFFFFFFF; -+ } -+ -+ if (bus >= MAX_PEX_BUSSES) -+ { -+ DB(mvOsPrintf("mvPexConfigRead: ERR. bus number illigal %d\n", bus)); -+ return MV_ERROR; -+ } -+ -+ DB(mvOsPrintf("mvPexConfigRead: pexIf %d, bus %d, dev %d, func %d, regOff 0x%x\n", -+ pexIf, bus, dev, func, regOff)); -+ -+ localDev = mvPexLocalDevNumGet(pexIf); -+ localBus = mvPexLocalBusNumGet(pexIf); -+ -+ /* Speed up the process. In case on no link, return MV_ERROR */ -+ if ((dev != localDev) || (bus != localBus)) -+ { -+ pexData = MV_REG_READ(PEX_STATUS_REG(pexIf)); -+ -+ if ((pexData & PXSR_DL_DOWN)) -+ { -+ return MV_ERROR; -+ } -+ } -+ -+ /* in PCI Express we have only one device number */ -+ /* and this number is the first number we encounter -+ else that the localDev*/ -+ /* spec pex define return on config read/write on any device */ -+ if (bus == localBus) -+ { -+ if (localDev == 0) -+ { -+ /* if local dev is 0 then the first number we encounter -+ after 0 is 1 */ -+ if ((dev != 1)&&(dev != localDev)) -+ { -+ return MV_ERROR; -+ } -+ } -+ else -+ { -+ /* if local dev is not 0 then the first number we encounter -+ is 0 */ -+ -+ if ((dev != 0)&&(dev != localDev)) -+ { -+ return MV_ERROR; -+ } -+ } -+ if(func != 0 ) /* i.e bridge */ -+ { -+ return MV_ERROR; -+ } -+ } -+ -+ -+ /* Creating PEX address to be passed */ -+ pexData = (bus << PXCAR_BUS_NUM_OFFS); -+ pexData |= (dev << PXCAR_DEVICE_NUM_OFFS); -+ pexData |= (func << PXCAR_FUNC_NUM_OFFS); -+ pexData |= (regOff & PXCAR_REG_NUM_MASK); /* lgacy register space */ -+ /* extended register space */ -+ pexData |=(((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >> -+ PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS); -+ -+ pexData |= PXCAR_CONFIG_EN; -+ -+ /* Write the address to the PEX configuration address register */ -+ MV_REG_WRITE(PEX_CFG_ADDR_REG(pexIf), pexData); -+ -+ DB(mvOsPrintf("mvPexConfigRead:address pexData=%x ",pexData)); -+ -+ -+ /* In order to let the PEX controller absorbed the address of the read */ -+ /* transaction we perform a validity check that the address was written */ -+ if(pexData != MV_REG_READ(PEX_CFG_ADDR_REG(pexIf))) -+ { -+ return MV_ERROR; -+ } -+ -+ /* cleaning Master Abort */ -+ MV_REG_BIT_SET(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_STATUS_AND_COMMAND), -+ PXSAC_MABORT); -+#if 0 -+ /* Guideline (GL# PCI Express-1) Erroneous Read Data on Configuration */ -+ /* This guideline is relevant for all devices except of the following devices: -+ 88F5281-BO and above, 88F5181L-A0 and above, 88F1281 A0 and above -+ 88F6183 A0 and above, 88F6183L */ -+ if ( ( (dev != localDev) || (bus != localBus) ) && -+ ( -+ !(MV_5281_DEV_ID == mvCtrlModelGet())&& -+ !((MV_5181_DEV_ID == mvCtrlModelGet())&& (mvCtrlRevGet() >= MV_5181L_A0_REV))&& -+ !(MV_1281_DEV_ID == mvCtrlModelGet())&& -+ !(MV_6183_DEV_ID == mvCtrlModelGet())&& -+ !(MV_6183L_DEV_ID == mvCtrlModelGet())&& -+ !(MV_6281_DEV_ID == mvCtrlModelGet())&& -+ !(MV_6192_DEV_ID == mvCtrlModelGet())&& -+ !(MV_6190_DEV_ID == mvCtrlModelGet())&& -+ !(MV_6180_DEV_ID == mvCtrlModelGet())&& -+ !(MV_78XX0_DEV_ID == mvCtrlModelGet()) -+ )) -+ { -+ -+ /* PCI-Express configuration read work-around */ -+ -+ /* we will use one of the Punit (AHBToMbus) windows to access the xbar -+ and read the data from there */ -+ /* -+ Need to configure the 2 free Punit (AHB to MBus bridge) -+ address decoding windows: -+ Configure the flash Window to handle Configuration space requests -+ for PEX0/1: -+ 1. write 0x7931/0x7941 to the flash window and the size, -+ 79-xbar attr (pci cfg), 3/4-xbar target (pex0/1), 1-WinEn -+ 2. write base to flash window -+ -+ Configuration transactions from the CPU should write/read the data -+ to/from address of the form: -+ addr[31:28] = 0x5 (for PEX0) or 0x6 (for PEX1) -+ addr[27:24] = extended register number -+ addr[23:16] = bus number -+ addr[15:11] = device number -+ addr[10:8] = function number -+ addr[7:0] = register number -+ */ -+ -+ #include "ctrlEnv/sys/mvAhbToMbus.h" -+ { -+ MV_U32 winNum; -+ MV_AHB_TO_MBUS_DEC_WIN originWin; -+ MV_U32 pciAddr=0; -+ MV_U32 remapLow=0,remapHigh=0; -+ -+ /* -+ We will use DEV_CS2\Flash window for this workarround -+ */ -+ -+ winNum = mvAhbToMbusWinTargetGet(PEX_CONFIG_RW_WA_TARGET); -+ -+ /* save remap values if exist */ -+ if ((1 == winNum)||(0 == winNum)) -+ { -+ remapLow = MV_REG_READ(AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum)); -+ remapHigh = MV_REG_READ(AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum)); -+ -+ } -+ -+ -+ /* save the original window values */ -+ mvAhbToMbusWinGet(winNum,&originWin); -+ -+ if (PEX_CONFIG_RW_WA_USE_ORIGINAL_WIN_VALUES) -+ { -+ /* set the window as xbar window */ -+ if (pexIf) -+ { -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), -+ (0x7931 | (((originWin.addrWin.size >> 16)-1) ) << 16)); -+ } -+ else -+ { -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), -+ (0x7941 | (((originWin.addrWin.size >> 16)-1) ) << 16)); -+ } -+ -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum), -+ originWin.addrWin.baseLow); -+ -+ /*pciAddr = originWin.addrWin.baseLow;*/ -+ pciAddr = (MV_U32)CPU_MEMIO_UNCACHED_ADDR( -+ (MV_U32)originWin.addrWin.baseLow); -+ -+ } -+ else -+ { -+ /* set the window as xbar window */ -+ if (pexIf) -+ { -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), -+ (0x7931 | (((PEX_CONFIG_RW_WA_SIZE >> 16)-1) ) << 16)); -+ } -+ else -+ { -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), -+ (0x7941 | (((PEX_CONFIG_RW_WA_SIZE >> 16)-1) ) << 16)); -+ } -+ -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum), -+ PEX_CONFIG_RW_WA_BASE); -+ -+ pciAddr = (MV_U32)CPU_MEMIO_UNCACHED_ADDR(PEX_CONFIG_RW_WA_BASE); -+ } -+ -+ -+ /* remap should be as base */ -+ if ((1 == winNum)||(0 == winNum)) -+ { -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum),pciAddr); -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum),0); -+ -+ } -+ -+ /* extended register space */ -+ pciAddr |= (bus << 16); -+ pciAddr |= (dev << 11); -+ pciAddr |= (func << 8); -+ pciAddr |= (regOff & PXCAR_REG_NUM_MASK); /* lgacy register space */ -+ -+ pexData = *(MV_U32*)pciAddr; -+ pexData = MV_32BIT_LE(pexData); /* Data always in LE */ -+ -+ /* restore the original window values */ -+ mvAhbToMbusWinSet(winNum,&originWin); -+ -+ /* restore original remap values*/ -+ if ((1 == winNum)||(0 == winNum)) -+ { -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum),remapLow); -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum),remapHigh); -+ -+ } -+ } -+ } -+ else -+#endif -+ { -+ /* Read the Data returned in the PEX Data register */ -+ pexData = MV_REG_READ(PEX_CFG_DATA_REG(pexIf)); -+ -+ } -+ -+ DB(mvOsPrintf("mvPexConfigRead: got : %x \n",pexData)); -+ -+ return pexData; -+ -+} -+ -+/******************************************************************************* -+* mvPexConfigWrite - Write to configuration space -+* -+* DESCRIPTION: -+* This function performs a 32 bit write to PEX configuration space. -+* It supports both type 0 and type 1 of Configuration Transactions -+* (local and over bridge). In order to write to local bus segment, use -+* bus number retrieved from mvPexLocalBusNumGet(). Other bus numbers -+* will result configuration transaction of type 1 (over bridge). -+* -+* INPUT: -+* pexIf - PEX interface number. -+* bus - PEX segment bus number. -+* dev - PEX device number. -+* func - Function number. -+* regOffs - Register offset. -+* data - 32bit data. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data) -+{ -+#if defined(PCIE_VIRTUAL_BRIDGE_SUPPORT) -+ return mvPexVrtBrgConfigWrite (pexIf, bus, dev, func, regOff, data); -+} -+ -+MV_STATUS mvPexHwConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data) -+{ -+#endif -+ MV_U32 pexData = 0; -+ MV_U32 localDev,localBus; -+ -+ /* Parameter checking */ -+ if (PEX_DEFAULT_IF != pexIf) -+ { -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexConfigWrite: ERR. Invalid PEX interface %d\n", -+ pexIf); -+ return MV_ERROR; -+ } -+ } -+ -+ if (dev >= MAX_PEX_DEVICES) -+ { -+ mvOsPrintf("mvPexConfigWrite: ERR. device number illigal %d\n",dev); -+ return MV_BAD_PARAM; -+ } -+ -+ if (func >= MAX_PEX_FUNCS) -+ { -+ mvOsPrintf("mvPexConfigWrite: ERR. function number illigal %d\n", func); -+ return MV_ERROR; -+ } -+ -+ if (bus >= MAX_PEX_BUSSES) -+ { -+ mvOsPrintf("mvPexConfigWrite: ERR. bus number illigal %d\n", bus); -+ return MV_ERROR; -+ } -+ -+ -+ -+ localDev = mvPexLocalDevNumGet(pexIf); -+ localBus = mvPexLocalBusNumGet(pexIf); -+ -+ -+ /* in PCI Express we have only one device number other than ourselves*/ -+ /* and this number is the first number we encounter -+ else than the localDev that can be any valid dev number*/ -+ /* pex spec define return on config read/write on any device */ -+ if (bus == localBus) -+ { -+ -+ if (localDev == 0) -+ { -+ /* if local dev is 0 then the first number we encounter -+ after 0 is 1 */ -+ if ((dev != 1)&&(dev != localDev)) -+ { -+ return MV_ERROR; -+ } -+ -+ } -+ else -+ { -+ /* if local dev is not 0 then the first number we encounter -+ is 0 */ -+ -+ if ((dev != 0)&&(dev != localDev)) -+ { -+ return MV_ERROR; -+ } -+ } -+ -+ -+ } -+ -+ /* if we are not accessing ourselves , then check the link */ -+ if ((dev != localDev) || (bus != localBus) ) -+ { -+ /* workarround */ -+ /* when no link return MV_ERROR */ -+ -+ pexData = MV_REG_READ(PEX_STATUS_REG(pexIf)); -+ -+ if ((pexData & PXSR_DL_DOWN)) -+ { -+ return MV_ERROR; -+ } -+ -+ } -+ -+ pexData =0; -+ -+ /* Creating PEX address to be passed */ -+ pexData |= (bus << PXCAR_BUS_NUM_OFFS); -+ pexData |= (dev << PXCAR_DEVICE_NUM_OFFS); -+ pexData |= (func << PXCAR_FUNC_NUM_OFFS); -+ pexData |= (regOff & PXCAR_REG_NUM_MASK); /* lgacy register space */ -+ /* extended register space */ -+ pexData |=(((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >> -+ PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS); -+ pexData |= PXCAR_CONFIG_EN; -+ -+ DB(mvOsPrintf("mvPexConfigWrite: If=%x bus=%x func=%x dev=%x regOff=%x data=%x \n", -+ pexIf,bus,func,dev,regOff,data,pexData) ); -+ -+ /* Write the address to the PEX configuration address register */ -+ MV_REG_WRITE(PEX_CFG_ADDR_REG(pexIf), pexData); -+ -+ /* Clear CPU pipe. Important where CPU can perform OOO execution */ -+ CPU_PIPE_FLUSH; -+ -+ /* In order to let the PEX controller absorbed the address of the read */ -+ /* transaction we perform a validity check that the address was written */ -+ if(pexData != MV_REG_READ(PEX_CFG_ADDR_REG(pexIf))) -+ { -+ return MV_ERROR; -+ } -+ -+ /* Write the Data passed to the PEX Data register */ -+ MV_REG_WRITE(PEX_CFG_DATA_REG(pexIf), data); -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvPexMasterEnable - Enable/disale PEX interface master transactions. -+* -+* DESCRIPTION: -+* This function performs read modified write to PEX command status -+* (offset 0x4) to set/reset bit 2. After this bit is set, the PEX -+* master is allowed to gain ownership on the bus, otherwise it is -+* incapable to do so. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexMasterEnable(MV_U32 pexIf, MV_BOOL enable) -+{ -+ MV_U32 pexCommandStatus; -+ MV_U32 localBus; -+ MV_U32 localDev; -+ -+ /* Parameter checking */ -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexMasterEnable: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_ERROR; -+ } -+ -+ localBus = mvPexLocalBusNumGet(pexIf); -+ localDev = mvPexLocalDevNumGet(pexIf); -+ -+ pexCommandStatus = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, -+ PEX_STATUS_AND_COMMAND)); -+ -+ -+ if (MV_TRUE == enable) -+ { -+ pexCommandStatus |= PXSAC_MASTER_EN; -+ } -+ else -+ { -+ pexCommandStatus &= ~PXSAC_MASTER_EN; -+ } -+ -+ -+ MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_STATUS_AND_COMMAND), -+ pexCommandStatus); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPexSlaveEnable - Enable/disale PEX interface slave transactions. -+* -+* DESCRIPTION: -+* This function performs read modified write to PEX command status -+* (offset 0x4) to set/reset bit 0 and 1. After those bits are set, -+* the PEX slave is allowed to respond to PEX IO space access (bit 0) -+* and PEX memory space access (bit 1). -+* -+* INPUT: -+* pexIf - PEX interface number. -+* dev - PEX device number. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexSlaveEnable(MV_U32 pexIf, MV_U32 bus,MV_U32 dev, MV_BOOL enable) -+{ -+ MV_U32 pexCommandStatus; -+ MV_U32 RegOffs; -+ -+ /* Parameter checking */ -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexSlaveEnable: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ if (dev >= MAX_PEX_DEVICES) -+ { -+ mvOsPrintf("mvPexLocalDevNumSet: ERR. device number illigal %d\n", dev); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ -+ RegOffs = PEX_STATUS_AND_COMMAND; -+ -+ pexCommandStatus = mvPexConfigRead(pexIf, bus, dev, 0, RegOffs); -+ -+ if (MV_TRUE == enable) -+ { -+ pexCommandStatus |= (PXSAC_IO_EN | PXSAC_MEM_EN); -+ } -+ else -+ { -+ pexCommandStatus &= ~(PXSAC_IO_EN | PXSAC_MEM_EN); -+ } -+ -+ mvPexConfigWrite(pexIf, bus, dev, 0, RegOffs, pexCommandStatus); -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvPexLocalBusNumSet - Set PEX interface local bus number. -+* -+* DESCRIPTION: -+* This function sets given PEX interface its local bus number. -+* Note: In case the PEX interface is PEX-X, the information is read-only. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* busNum - Bus number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_NOT_ALLOWED in case PEX interface is PEX-X. -+* MV_BAD_PARAM on bad parameters , -+* otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexLocalBusNumSet(MV_U32 pexIf, MV_U32 busNum) -+{ -+ MV_U32 pexStatus; -+ MV_U32 localBus; -+ MV_U32 localDev; -+ -+ -+ /* Parameter checking */ -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexLocalBusNumSet: ERR. Invalid PEX interface %d\n",pexIf); -+ return MV_BAD_PARAM; -+ } -+ if (busNum >= MAX_PEX_BUSSES) -+ { -+ mvOsPrintf("mvPexLocalBusNumSet: ERR. bus number illigal %d\n", busNum); -+ return MV_ERROR; -+ -+ } -+ -+ localBus = mvPexLocalBusNumGet(pexIf); -+ localDev = mvPexLocalDevNumGet(pexIf); -+ -+ -+ -+ pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); -+ -+ pexStatus &= ~PXSR_PEX_BUS_NUM_MASK; -+ -+ pexStatus |= (busNum << PXSR_PEX_BUS_NUM_OFFS) & PXSR_PEX_BUS_NUM_MASK; -+ -+ MV_REG_WRITE(PEX_STATUS_REG(pexIf), pexStatus); -+ -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPexLocalBusNumGet - Get PEX interface local bus number. -+* -+* DESCRIPTION: -+* This function gets the local bus number of a given PEX interface. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Local bus number.0xffffffff on Error -+* -+*******************************************************************************/ -+MV_U32 mvPexLocalBusNumGet(MV_U32 pexIf) -+{ -+ MV_U32 pexStatus; -+ -+ /* Parameter checking */ -+ if (PEX_DEFAULT_IF != pexIf) -+ { -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexLocalBusNumGet: ERR. Invalid PEX interface %d\n",pexIf); -+ return 0xFFFFFFFF; -+ } -+ } -+ -+ -+ pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); -+ -+ pexStatus &= PXSR_PEX_BUS_NUM_MASK; -+ -+ return (pexStatus >> PXSR_PEX_BUS_NUM_OFFS); -+ -+} -+ -+ -+/******************************************************************************* -+* mvPexLocalDevNumSet - Set PEX interface local device number. -+* -+* DESCRIPTION: -+* This function sets given PEX interface its local device number. -+* Note: In case the PEX interface is PEX-X, the information is read-only. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* devNum - Device number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_NOT_ALLOWED in case PEX interface is PEX-X. -+* MV_BAD_PARAM on bad parameters , -+* otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexLocalDevNumSet(MV_U32 pexIf, MV_U32 devNum) -+{ -+ MV_U32 pexStatus; -+ MV_U32 localBus; -+ MV_U32 localDev; -+ -+ /* Parameter checking */ -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexLocalDevNumSet: ERR. Invalid PEX interface %d\n",pexIf); -+ return MV_BAD_PARAM; -+ } -+ if (devNum >= MAX_PEX_DEVICES) -+ { -+ mvOsPrintf("mvPexLocalDevNumSet: ERR. device number illigal %d\n", -+ devNum); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ localBus = mvPexLocalBusNumGet(pexIf); -+ localDev = mvPexLocalDevNumGet(pexIf); -+ -+ -+ pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); -+ -+ pexStatus &= ~PXSR_PEX_DEV_NUM_MASK; -+ -+ pexStatus |= (devNum << PXSR_PEX_DEV_NUM_OFFS) & PXSR_PEX_DEV_NUM_MASK; -+ -+ MV_REG_WRITE(PEX_STATUS_REG(pexIf), pexStatus); -+ -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvPexLocalDevNumGet - Get PEX interface local device number. -+* -+* DESCRIPTION: -+* This function gets the local device number of a given PEX interface. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Local device number. 0xffffffff on Error -+* -+*******************************************************************************/ -+MV_U32 mvPexLocalDevNumGet(MV_U32 pexIf) -+{ -+ MV_U32 pexStatus; -+ -+ /* Parameter checking */ -+ -+ if (PEX_DEFAULT_IF != pexIf) -+ { -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexLocalDevNumGet: ERR. Invalid PEX interface %d\n", -+ pexIf); -+ return 0xFFFFFFFF; -+ } -+ } -+ -+ pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); -+ -+ pexStatus &= PXSR_PEX_DEV_NUM_MASK; -+ -+ return (pexStatus >> PXSR_PEX_DEV_NUM_OFFS); -+} -+ -+MV_VOID mvPexPhyRegRead(MV_U32 pexIf, MV_U32 regOffset, MV_U16 *value) -+{ -+ -+ MV_U32 regAddr; -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexPhyRegRead: ERR. Invalid PEX interface %d\n", pexIf); -+ return; -+ } -+ regAddr = (BIT31 | ((regOffset & 0x3fff) << 16)); -+ MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexIf), regAddr); -+ *value = MV_REG_READ(PEX_PHY_ACCESS_REG(pexIf)); -+} -+ -+ -+MV_VOID mvPexPhyRegWrite(MV_U32 pexIf, MV_U32 regOffset, MV_U16 value) -+{ -+ -+ MV_U32 regAddr; -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexPhyRegWrite: ERR. Invalid PEX interface %d\n", pexIf); -+ return; -+ } -+ regAddr = (((regOffset & 0x3fff) << 16) | value); -+ MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexIf), regAddr); -+} -+ -+/******************************************************************************* -+* mvPexActiveStateLinkPMEnable -+* -+* DESCRIPTION: -+* Enable Active Link State Power Management -+* -+* INPUT: -+* pexIf - PEX interface number. -+* enable - MV_TRUE to enable ASPM, MV_FALSE to disable. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* MV_OK on success , MV_ERROR otherwise -+* -+*******************************************************************************/ -+MV_STATUS mvPexActiveStateLinkPMEnable(MV_U32 pexIf, MV_BOOL enable) -+{ -+ MV_U32 reg; -+ -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexActiveStateLinkPMEnable: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_ERROR; -+ } -+ -+ reg = MV_REG_READ(PEX_PWR_MNG_EXT_REG(pexIf)) & ~PXPMER_L1_ASPM_EN_MASK; -+ if(enable == MV_TRUE) -+ reg |= PXPMER_L1_ASPM_EN_MASK; -+ MV_REG_WRITE(PEX_PWR_MNG_EXT_REG(pexIf), reg); -+ -+ /* Enable / Disable L0/1 entry */ -+ reg = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG)) -+ & ~PXLCSR_ASPM_CNT_MASK; -+ if(enable == MV_TRUE) -+ reg |= PXLCSR_ASPM_CNT_L0S_L1S_ENT_SUPP; -+ MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG), reg); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPexForceX1 -+* -+* DESCRIPTION: -+* shut down lanes 1-3 if recognize that attached to an x1 end-point -+* INPUT: -+* pexIf - PEX interface number. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* MV_OK on success , MV_ERROR otherwise -+* -+*******************************************************************************/ -+MV_U32 mvPexForceX1(MV_U32 pexIf) -+{ -+ MV_U32 regData = 0; -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexForceX1: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ -+ regData = MV_REG_READ(PEX_CTRL_REG(pexIf)) & ~(PXCR_CONF_LINK_MASK) ; -+ regData |= PXCR_CONF_LINK_X1; -+ -+ MV_REG_WRITE(PEX_CTRL_REG(pexIf), regData); -+ return MV_OK; -+} -+ -+MV_BOOL mvPexIsPowerUp(MV_U32 pexIf) -+{ -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexIsPowerUp: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_FALSE; -+ } -+ return mvCtrlPwrClckGet(PEX_UNIT_ID, pexIf); -+} -+ -+ -+MV_VOID mvPexPowerDown(MV_U32 pexIf) -+{ -+ if ( (mvCtrlModelGet() == MV_78XX0_DEV_ID) || -+ (mvCtrlModelGet() == MV_76100_DEV_ID) || -+ (mvCtrlModelGet() == MV_78100_DEV_ID) || -+ (mvCtrlModelGet() == MV_78200_DEV_ID) ) -+ { -+ mvCtrlPwrClckSet(PEX_UNIT_ID, pexIf, MV_FALSE); -+ } -+ else -+ { -+ MV_REG_WRITE((0x41B00 -(pexIf)*0x10000), 0x20800087); -+ } -+} -+ -+ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h 2010-11-09 20:28:11.742495415 +0100 -@@ -0,0 +1,168 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCPEXH -+#define __INCPEXH -+ -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "pex/mvPexRegs.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+ -+ -+ -+/* NOTE not supported in this driver:*/ -+ -+ -+/* defines */ -+/* The number of supported PEX interfaces depend on Marvell controller */ -+/* device number. This device number ID is located on the PEX unit */ -+/* configuration header. This creates a loop where calling PEX */ -+/* configuration read/write routine results a call to get PEX configuration */ -+/* information etc. This macro defines a default PEX interface. This PEX */ -+/* interface is sure to exist. */ -+#define PEX_DEFAULT_IF 0 -+ -+ -+/* typedefs */ -+/* The Marvell controller supports both root complex and end point devices */ -+/* This enumeration describes the PEX type. */ -+typedef enum _mvPexType -+{ -+ MV_PEX_ROOT_COMPLEX, /* root complex device */ -+ MV_PEX_END_POINT /* end point device */ -+}MV_PEX_TYPE; -+ -+typedef enum _mvPexWidth -+{ -+ MV_PEX_WITDH_X1 = 1, -+ MV_PEX_WITDH_X2, -+ MV_PEX_WITDH_X3, -+ MV_PEX_WITDH_X4, -+ MV_PEX_WITDH_INVALID -+}MV_PEX_WIDTH; -+ -+/* PEX Bar attributes */ -+typedef struct _mvPexMode -+{ -+ MV_PEX_TYPE pexType; -+ MV_PEX_WIDTH pexWidth; -+ MV_BOOL pexLinkUp; -+}MV_PEX_MODE; -+ -+ -+ -+/* Global Functions prototypes */ -+/* mvPexInit - Initialize PEX interfaces*/ -+MV_STATUS mvPexHalInit(MV_U32 pexIf, MV_PEX_TYPE pexType); -+ -+/* mvPexModeGet - Get Pex If mode */ -+MV_U32 mvPexModeGet(MV_U32 pexIf,MV_PEX_MODE *pexMode); -+ -+/* mvPexConfigRead - Read from configuration space */ -+MV_U32 mvPexConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func,MV_U32 regOff); -+ -+/* mvPexConfigWrite - Write to configuration space */ -+MV_STATUS mvPexConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data); -+ -+/* mvPexMasterEnable - Enable/disale PEX interface master transactions.*/ -+MV_STATUS mvPexMasterEnable(MV_U32 pexIf, MV_BOOL enable); -+ -+/* mvPexSlaveEnable - Enable/disale PEX interface slave transactions.*/ -+MV_STATUS mvPexSlaveEnable(MV_U32 pexIf, MV_U32 bus,MV_U32 dev, MV_BOOL enable); -+ -+/* mvPexLocalBusNumSet - Set PEX interface local bus number.*/ -+MV_STATUS mvPexLocalBusNumSet(MV_U32 pexIf, MV_U32 busNum); -+ -+/* mvPexLocalBusNumGet - Get PEX interface local bus number.*/ -+MV_U32 mvPexLocalBusNumGet(MV_U32 pexIf); -+ -+/* mvPexLocalDevNumSet - Set PEX interface local device number.*/ -+MV_STATUS mvPexLocalDevNumSet(MV_U32 pexIf, MV_U32 devNum); -+ -+/* mvPexLocalDevNumGet - Get PEX interface local device number.*/ -+MV_U32 mvPexLocalDevNumGet(MV_U32 pexIf); -+/* mvPexForceX1 - Force PEX interface to X1 mode. */ -+MV_U32 mvPexForceX1(MV_U32 pexIf); -+ -+/* mvPexIsPowerUp - Is PEX interface Power up? */ -+MV_BOOL mvPexIsPowerUp(MV_U32 pexIf); -+ -+/* mvPexPowerDown - Power Down */ -+MV_VOID mvPexPowerDown(MV_U32 pexIf); -+ -+/* mvPexPowerUp - Power Up */ -+MV_VOID mvPexPowerUp(MV_U32 pexIf); -+ -+/* mvPexPhyRegRead - Pex phy read */ -+MV_VOID mvPexPhyRegRead(MV_U32 pexIf, MV_U32 regOffset, MV_U16 *value); -+ -+/* mvPexPhyRegWrite - Pex phy write */ -+MV_VOID mvPexPhyRegWrite(MV_U32 pexIf, MV_U32 regOffset, MV_U16 value); -+ -+MV_STATUS mvPexActiveStateLinkPMEnable(MV_U32 pexIf, MV_BOOL enable); -+ -+#endif /* #ifndef __INCPEXH */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h 2010-11-09 20:28:11.782495900 +0100 -@@ -0,0 +1,751 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCPEXREGSH -+#define __INCPEXREGSH -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* defines */ -+#define MAX_PEX_DEVICES 32 -+#define MAX_PEX_FUNCS 8 -+#define MAX_PEX_BUSSES 256 -+ -+ -+ -+/*********************************************************/ -+/* PCI Express Configuration Cycles Generation Registers */ -+/*********************************************************/ -+ -+#define PEX_CFG_ADDR_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x18F8) -+#define PEX_CFG_DATA_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x18FC) -+#define PEX_PHY_ACCESS_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1B00) -+/* PCI Express Configuration Address Register */ -+/* PEX_CFG_ADDR_REG (PXCAR)*/ -+ -+#define PXCAR_REG_NUM_OFFS 2 -+#define PXCAR_REG_NUM_MAX 0x3F -+#define PXCAR_REG_NUM_MASK (PXCAR_REG_NUM_MAX << PXCAR_REG_NUM_OFFS) -+#define PXCAR_FUNC_NUM_OFFS 8 -+#define PXCAR_FUNC_NUM_MAX 0x7 -+#define PXCAR_FUNC_NUM_MASK (PXCAR_FUNC_NUM_MAX << PXCAR_FUNC_NUM_OFFS) -+#define PXCAR_DEVICE_NUM_OFFS 11 -+#define PXCAR_DEVICE_NUM_MAX 0x1F -+#define PXCAR_DEVICE_NUM_MASK (PXCAR_DEVICE_NUM_MAX << PXCAR_DEVICE_NUM_OFFS) -+#define PXCAR_BUS_NUM_OFFS 16 -+#define PXCAR_BUS_NUM_MAX 0xFF -+#define PXCAR_BUS_NUM_MASK (PXCAR_BUS_NUM_MAX << PXCAR_BUS_NUM_OFFS) -+#define PXCAR_EXT_REG_NUM_OFFS 24 -+#define PXCAR_EXT_REG_NUM_MAX 0xF -+ -+/* in pci express register address is now the legacy register address (8 bits) -+with the new extended register address (more 4 bits) , below is the mask of -+the upper 4 bits of the full register address */ -+ -+#define PXCAR_REAL_EXT_REG_NUM_OFFS 8 -+#define PXCAR_EXT_REG_NUM_MASK (PXCAR_EXT_REG_NUM_MAX << PXCAR_EXT_REG_NUM_OFFS) -+#define PXCAR_CONFIG_EN BIT31 -+ -+#define PXCAR_REAL_EXT_REG_NUM_OFFS 8 -+#define PXCAR_REAL_EXT_REG_NUM_MASK (0xF << PXCAR_REAL_EXT_REG_NUM_OFFS) -+ -+/* The traditional PCI spec defined 6-bit field to describe register offset.*/ -+/* The new PCI Express extend the register offset by an extra 4-bits. */ -+/* The below macro assign 10-bit register offset into the apprpreate */ -+/* fields in the CFG_ADDR_REG */ -+#define PXCAR_REG_OFFS_SET(regOffs) \ -+ ( (regOff & PXCAR_REG_NUM_MASK) | \ -+ ( ((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >> PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS) ) -+ -+/***********************************/ -+/* PCI Express Interrupt registers */ -+/***********************************/ -+#define PEX_CAUSE_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1900) -+#define PEX_MASK_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1910) -+ -+#define PXICR_TX_REQ_IN_DLDOWN_ERR BIT0 /* Transmit request while field */ -+ /* of the PCI Express */ -+/* PCI Express Interrupt Cause */ -+/* PEX_INT_CAUSE_REG (PXICR)*/ -+/* PEX_INT_MASK_REG*/ -+/* -+NOTE:All bits except bits[27:24] are Read/Write Clear only. A cause bit sets -+upon an error event occurrence. A write of 0 clears the bit. A write of 1 has -+no affect. Bits[24:27} are set and cleared upon reception of interrupt -+emulation messages. -+ -+Mask bit per cause bit. If a bit is set to 1, the corresponding event is -+enabled. Mask does not affect setting of the Interrupt Cause register bits; -+it only affects the assertion of the interrupt .*/ -+ -+ -+#define PXICR_MDIS_CAUSE BIT1 /* Attempt to generate PCI transaction -+ while master is disabled */ -+#define PXICR_ERR_WRTO_REG_CAUSE BIT3 /* Erroneous write attempt to -+ PCI Express internal register*/ -+#define PXICR_HIT_DFLT_WIN_ERR BIT4 /* Hit Default Window Error */ -+#define PXICR_RX_RAM_PAR_ERR BIT6 /* Rx RAM Parity Error */ -+#define PXICR_TX_RAM_PAR_ERR BIT7 /* Tx RAM Parity Error */ -+#define PXICR_COR_ERR_DET BIT8 /* Correctable Error Detected*/ -+#define PXICR_NF_ERR_DET BIT9 /* Non-Fatal Error Detected*/ -+#define PXICR_FERR_DET BIT10 /* Fatal Error Detected*/ -+#define PXICR_DSTATE_CHANGE BIT11 /* Dstate Change Indication*/ -+#define PXICR_BIST BIT12 /* PCI-Express BIST activated*/ -+#define PXICR_FLW_CTRL_PROT BIT14 /* Flow Control Protocol Error */ -+ -+#define PXICR_RCV_UR_CA_ERR BIT15 /* Received UR or CA status. */ -+#define PXICR_RCV_ERR_FATAL BIT16 /* Received ERR_FATAL message.*/ -+#define PXICR_RCV_ERR_NON_FATAL BIT17 /* Received ERR_NONFATAL message*/ -+#define PXICR_RCV_ERR_COR BIT18 /* Received ERR_COR message.*/ -+#define PXICR_RCV_CRS BIT19 /* Received CRS completion status*/ -+#define PXICR_SLV_HOT_RESET BIT20 /* Received Hot Reset Indication*/ -+#define PXICR_SLV_DIS_LINK BIT21 /* Slave Disable Link Indication*/ -+#define PXICR_SLV_LB BIT22 /* Slave Loopback Indication*/ -+#define PXICR_LINK_FAIL BIT23 /* Link Failure indication.*/ -+#define PXICR_RCV_INTA BIT24 /* IntA status.*/ -+#define PXICR_RCV_INTB BIT25 /* IntB status.*/ -+#define PXICR_RCV_INTC BIT26 /* IntC status.*/ -+#define PXICR_RCV_INTD BIT27 /* IntD status.*/ -+#define PXICR_RCV_PM_PME BIT28 /* Received PM_PME message. */ -+ -+ -+/********************************************/ -+/* PCI Express Control and Status Registers */ -+/********************************************/ -+#define PEX_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A00) -+#define PEX_STATUS_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A04) -+#define PEX_COMPLT_TMEOUT_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A10) -+#define PEX_PWR_MNG_EXT_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A18) -+#define PEX_FLOW_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A20) -+#define PEX_ACK_TMR_4X_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A30) -+#define PEX_ACK_TMR_1X_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A40) -+#define PEX_TL_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1AB0) -+ -+ -+#define PEX_RAM_PARITY_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A50) -+/* PCI Express Control Register */ -+/* PEX_CTRL_REG (PXCR) */ -+ -+#define PXCR_CONF_LINK_OFFS 0 -+#define PXCR_CONF_LINK_MASK (1 << PXCR_CONF_LINK_OFFS) -+#define PXCR_CONF_LINK_X4 (0 << PXCR_CONF_LINK_OFFS) -+#define PXCR_CONF_LINK_X1 (1 << PXCR_CONF_LINK_OFFS) -+#define PXCR_DEV_TYPE_CTRL_OFFS 1 /*PCI ExpressDevice Type Control*/ -+#define PXCR_DEV_TYPE_CTRL_MASK BIT1 -+#define PXCR_DEV_TYPE_CTRL_CMPLX (1 << PXCR_DEV_TYPE_CTRL_OFFS) -+#define PXCR_DEV_TYPE_CTRL_POINT (0 << PXCR_DEV_TYPE_CTRL_OFFS) -+#define PXCR_CFG_MAP_TO_MEM_EN BIT2 /* Configuration Header Mapping -+ to Memory Space Enable */ -+ -+#define PXCR_CFG_MAP_TO_MEM_EN BIT2 /* Configuration Header Mapping -+ to Memory Space Enable*/ -+ -+#define PXCR_RSRV1_OFFS 5 -+#define PXCR_RSRV1_MASK (0x7 << PXCR_RSRV1_OFFS) -+#define PXCR_RSRV1_VAL (0x0 << PXCR_RSRV1_OFFS) -+ -+#define PXCR_CONF_MAX_OUTSTND_OFFS 8 /*Maximum outstanding NP requests as a master*/ -+#define PXCR_CONF_MAX_OUTSTND_MASK (0x3 << PXCR_CONF_MAX_OUTSTND_OFFS) -+ -+ -+#define PXCR_CONF_NFTS_OFFS 16 /*number of FTS Ordered-Sets*/ -+#define PXCR_CONF_NFTS_MASK (0xff << PXCR_CONF_NFTS_OFFS) -+ -+#define PXCR_CONF_MSTR_HOT_RESET BIT24 /*Master Hot-Reset.*/ -+#define PXCR_CONF_MSTR_LB BIT26 /* Master Loopback */ -+#define PXCR_CONF_MSTR_DIS_SCRMB BIT27 /* Master Disable Scrambling*/ -+#define PXCR_CONF_DIRECT_DIS_SCRMB BIT28 /* Direct Disable Scrambling*/ -+ -+/* PCI Express Status Register */ -+/* PEX_STATUS_REG (PXSR) */ -+ -+#define PXSR_DL_DOWN BIT0 /* DL_Down indication.*/ -+ -+#define PXSR_PEX_BUS_NUM_OFFS 8 /* Bus Number Indication */ -+#define PXSR_PEX_BUS_NUM_MASK (0xff << PXSR_PEX_BUS_NUM_OFFS) -+ -+#define PXSR_PEX_DEV_NUM_OFFS 16 /* Device Number Indication */ -+#define PXSR_PEX_DEV_NUM_MASK (0x1f << PXSR_PEX_DEV_NUM_OFFS) -+ -+#define PXSR_PEX_SLV_HOT_RESET BIT24 /* Slave Hot Reset Indication*/ -+#define PXSR_PEX_SLV_DIS_LINK BIT25 /* Slave Disable Link Indication*/ -+#define PXSR_PEX_SLV_LB BIT26 /* Slave Loopback Indication*/ -+#define PXSR_PEX_SLV_DIS_SCRMB BIT27 /* Slave Disable Scrambling Indication*/ -+ -+ -+/* PCI Express Completion Timeout Register */ -+/* PEX_COMPLT_TMEOUT_REG (PXCTR)*/ -+ -+#define PXCTR_CMP_TO_THRSHLD_OFFS 0 /* Completion Timeout Threshold */ -+#define PXCTR_CMP_TO_THRSHLD_MASK (0xffff << PXCTR_CMP_TO_THRSHLD_OFFS) -+ -+/* PCI Express Power Management Extended Register */ -+/* PEX_PWR_MNG_EXT_REG (PXPMER) */ -+ -+#define PXPMER_L1_ASPM_EN_OFFS 1 -+#define PXPMER_L1_ASPM_EN_MASK (0x1 << PXPMER_L1_ASPM_EN_OFFS) -+ -+/* PCI Express Flow Control Register */ -+/* PEX_FLOW_CTRL_REG (PXFCR)*/ -+ -+#define PXFCR_PH_INIT_FC_OFFS 0 /*Posted Headers Flow Control Credit -+ Initial Value.*/ -+#define PXFCR_PH_INIT_FC_MASK (0xff << PXFCR_PH_INIT_FC_OFFS) -+ -+ -+#define PXFCR_NPH_INIT_FC_OFFS 8 /* Classified Non-Posted Headers -+ Flow Control Credit Initial Value*/ -+#define PXFCR_NPH_INIT_FC_MASK (0xff << PXFCR_NPH_INIT_FC_OFFS) -+ -+#define PXFCR_CH_INIT_FC_OFFS 16 /* Completion Headers Flow Control -+ Credit Initial Value Infinite*/ -+ -+#define PXFCR_CH_INIT_FC_MASK (0xff << PXFCR_CH_INIT_FC_OFFS) -+ -+#define PXFCR_FC_UPDATE_TO_OFFS 24 /* Flow Control Update Timeout */ -+#define PXFCR_FC_UPDATE_TO_MASK (0xff << PXFCR_FC_UPDATE_TO_OFFS) -+ -+/* PCI Express Acknowledge Timers (4X) Register */ -+/* PEX_ACK_TMR_4X_REG (PXAT4R) */ -+#define PXAT1R_ACK_LAT_TOX4_OFFS 0 /* Ack Latency Timer Timeout Value */ -+#define PXAT1R_ACK_LAT_TOX4_MASK (0xffff << PXAT4R_ACK_LAT_TOX1_OFFS) -+#define PXAT1R_ACK_RPLY_TOX4_OFFS 16 /* Ack Replay Timer Timeout Value */ -+#define PXAT1R_ACK_RPLY_TOX4_MASK (0xffff << PXAT1R_ACK_RPLY_TOX1_OFFS) -+ -+/* PCI Express Acknowledge Timers (1X) Register */ -+/* PEX_ACK_TMR_1X_REG (PXAT1R) */ -+ -+#define PXAT1R_ACK_LAT_TOX1_OFFS 0 /* Acknowledge Latency Timer Timeout -+ Value for 1X Link*/ -+#define PXAT1R_ACK_LAT_TOX1_MASK (0xffff << PXAT1R_ACK_LAT_TOX1_OFFS) -+ -+#define PXAT1R_ACK_RPLY_TOX1_OFFS 16 /* Acknowledge Replay Timer Timeout -+ Value for 1X*/ -+#define PXAT1R_ACK_RPLY_TOX1_MASK (0xffff << PXAT1R_ACK_RPLY_TOX1_OFFS) -+ -+ -+/* PCI Express TL Control Register */ -+/* PEX_TL_CTRL_REG (PXTCR) */ -+ -+#define PXTCR_TX_CMP_BUFF_NO_OFFS 8 /*Number of completion buffers in Tx*/ -+#define PXTCR_TX_CMP_BUFF_NO_MASK (0xf << PXTCR_TX_CMP_BUFF_NO_OFFS) -+ -+/* PCI Express Debug MAC Control Register */ -+/* PEX_DEBUG_MAC_CTRL_REG (PXDMCR) */ -+ -+#define PXDMCR_LINKUP BIT4 -+ -+ -+ -+/**********************************************/ -+/* PCI Express Configuration Header Registers */ -+/**********************************************/ -+#define PEX_CFG_DIRECT_ACCESS(pexIf,cfgReg) ((PEX_IF_BASE(pexIf)) + (cfgReg)) -+ -+#define PEX_DEVICE_AND_VENDOR_ID 0x000 -+#define PEX_STATUS_AND_COMMAND 0x004 -+#define PEX_CLASS_CODE_AND_REVISION_ID 0x008 -+#define PEX_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE 0x00C -+#define PEX_MEMORY_BAR_BASE_ADDR(barNum) (0x010 + ((barNum) << 2)) -+#define PEX_MV_BAR_BASE(barNum) (0x010 + (barNum) * 8) -+#define PEX_MV_BAR_BASE_HIGH(barNum) (0x014 + (barNum) * 8) -+#define PEX_BAR0_INTER_REG 0x010 -+#define PEX_BAR0_INTER_REG_HIGH 0x014 -+#define PEX_BAR1_REG 0x018 -+#define PEX_BAR1_REG_HIGH 0x01C -+#define PEX_BAR2_REG 0x020 -+#define PEX_BAR2_REG_HIGH 0x024 -+ -+#define PEX_SUBSYS_ID_AND_SUBSYS_VENDOR_ID 0x02C -+#define PEX_EXPANSION_ROM_BASE_ADDR_REG 0x030 -+#define PEX_CAPABILTY_LIST_POINTER 0x034 -+#define PEX_INTERRUPT_PIN_AND_LINE 0x03C -+ -+/* capability list */ -+#define PEX_POWER_MNG_CAPABILITY 0x040 -+#define PEX_POWER_MNG_STATUS_CONTROL 0x044 -+ -+#define PEX_MSI_MESSAGE_CONTROL 0x050 -+#define PEX_MSI_MESSAGE_ADDR 0x054 -+#define PEX_MSI_MESSAGE_HIGH_ADDR 0x058 -+#define PEX_MSI_MESSAGE_DATA 0x05C -+ -+#define PEX_CAPABILITY_REG 0x60 -+#define PEX_DEV_CAPABILITY_REG 0x64 -+#define PEX_DEV_CTRL_STAT_REG 0x68 -+#define PEX_LINK_CAPABILITY_REG 0x6C -+#define PEX_LINK_CTRL_STAT_REG 0x70 -+ -+#define PEX_ADV_ERR_RPRT_HDR_TRGT_REG 0x100 -+#define PEX_UNCORRECT_ERR_STAT_REG 0x104 -+#define PEX_UNCORRECT_ERR_MASK_REG 0x108 -+#define PEX_UNCORRECT_ERR_SERVITY_REG 0x10C -+#define PEX_CORRECT_ERR_STAT_REG 0x110 -+#define PEX_CORRECT_ERR_MASK_REG 0x114 -+#define PEX_ADV_ERR_CAPABILITY_CTRL_REG 0x118 -+#define PEX_HDR_LOG_FIRST_DWORD_REG 0x11C -+#define PEX_HDR_LOG_SECOND_DWORD_REG 0x120 -+#define PEX_HDR_LOG_THIRD_DWORD_REG 0x124 -+#define PEX_HDR_LOG_FOURTH_DWORD_REG 0x128 -+ -+ -+ -+/* PCI Express Device and Vendor ID Register*/ -+/*PEX_DEVICE_AND_VENDOR_ID (PXDAVI)*/ -+ -+#define PXDAVI_VEN_ID_OFFS 0 /* Vendor ID */ -+#define PXDAVI_VEN_ID_MASK (0xffff << PXDAVI_VEN_ID_OFFS) -+ -+#define PXDAVI_DEV_ID_OFFS 16 /* Device ID */ -+#define PXDAVI_DEV_ID_MASK (0xffff << PXDAVI_DEV_ID_OFFS) -+ -+ -+/* PCI Express Command and Status Register*/ -+/*PEX_STATUS_AND_COMMAND (PXSAC)*/ -+ -+#define PXSAC_IO_EN BIT0 /* IO Enable */ -+#define PXSAC_MEM_EN BIT1 /* Memory Enable */ -+#define PXSAC_MASTER_EN BIT2 /* Master Enable */ -+#define PXSAC_PERR_EN BIT6 /* Parity Errors Respond Enable */ -+#define PXSAC_SERR_EN BIT8 /* Ability to assert SERR# line */ -+#define PXSAC_INT_DIS BIT10 /* Interrupt Disable */ -+#define PXSAC_INT_STAT BIT19 /* Interrupt Status */ -+#define PXSAC_CAP_LIST BIT20 /* Capability List Support */ -+#define PXSAC_MAS_DATA_PERR BIT24 /* Master Data Parity Error */ -+#define PXSAC_SLAVE_TABORT BIT27 /* Signalled Target Abort */ -+#define PXSAC_RT_ABORT BIT28 /* Recieved Target Abort */ -+#define PXSAC_MABORT BIT29 /* Recieved Master Abort */ -+#define PXSAC_SYSERR BIT30 /* Signalled system error */ -+#define PXSAC_DET_PARERR BIT31 /* Detect Parity Error */ -+ -+ -+/* PCI Express Class Code and Revision ID Register*/ -+/*PEX_CLASS_CODE_AND_REVISION_ID (PXCCARI)*/ -+ -+#define PXCCARI_REVID_OFFS 0 /* Revision ID */ -+#define PXCCARI_REVID_MASK (0xff << PXCCARI_REVID_OFFS) -+ -+#define PXCCARI_FULL_CLASS_OFFS 8 /* Full Class Code */ -+#define PXCCARI_FULL_CLASS_MASK (0xffffff << PXCCARI_FULL_CLASS_OFFS) -+ -+#define PXCCARI_PROGIF_OFFS 8 /* Prog .I/F*/ -+#define PXCCARI_PROGIF_MASK (0xff << PXCCARI_PROGIF_OFFS) -+ -+#define PXCCARI_SUB_CLASS_OFFS 16 /* Sub Class*/ -+#define PXCCARI_SUB_CLASS_MASK (0xff << PXCCARI_SUB_CLASS_OFFS) -+ -+#define PXCCARI_BASE_CLASS_OFFS 24 /* Base Class*/ -+#define PXCCARI_BASE_CLASS_MASK (0xff << PXCCARI_BASE_CLASS_OFFS) -+ -+ -+/* PCI Express BIST, Header Type and Cache Line Size Register*/ -+/*PEX_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE (PXBHTLTCL)*/ -+ -+#define PXBHTLTCL_CACHELINE_OFFS 0 /* Specifies the cache line size */ -+#define PXBHTLTCL_CACHELINE_MASK (0xff << PXBHTLTCL_CACHELINE_OFFS) -+ -+#define PXBHTLTCL_HEADTYPE_FULL_OFFS 16 /* Full Header Type */ -+#define PXBHTLTCL_HEADTYPE_FULL_MASK (0xff << PXBHTLTCL_HEADTYPE_FULL_OFFS) -+ -+#define PXBHTLTCL_MULTI_FUNC BIT23 /* Multi/Single function */ -+ -+#define PXBHTLTCL_HEADER_OFFS 16 /* Header type */ -+#define PXBHTLTCL_HEADER_MASK (0x7f << PXBHTLTCL_HEADER_OFFS) -+#define PXBHTLTCL_HEADER_STANDARD (0x0 << PXBHTLTCL_HEADER_OFFS) -+#define PXBHTLTCL_HEADER_PCI2PCI_BRIDGE (0x1 << PXBHTLTCL_HEADER_OFFS) -+ -+ -+#define PXBHTLTCL_BISTCOMP_OFFS 24 /* BIST Completion Code */ -+#define PXBHTLTCL_BISTCOMP_MASK (0xf << PXBHTLTCL_BISTCOMP_OFFS) -+ -+#define PXBHTLTCL_BISTACT BIT30 /* BIST Activate bit */ -+#define PXBHTLTCL_BISTCAP BIT31 /* BIST Capable Bit */ -+#define PXBHTLTCL_BISTCAP_OFFS 31 -+#define PXBHTLTCL_BISTCAP_MASK BIT31 -+#define PXBHTLTCL_BISTCAP_VAL 0 -+ -+ -+/* PCI Express Subsystem Device and Vendor ID */ -+/*PEX_SUBSYS_ID_AND_SUBSYS_VENDOR_ID (PXSIASVI)*/ -+ -+#define PXSIASVI_VENID_OFFS 0 /* Subsystem Manufacturer Vendor ID Number */ -+#define PXSIASVI_VENID_MASK (0xffff << PXSIASVI_VENID_OFFS) -+ -+#define PXSIASVI_DEVID_OFFS 16 /* Subsystem Device ID Number */ -+#define PXSIASVI_DEVID_MASK (0xffff << PXSIASVI_DEVID_OFFS) -+ -+ -+/* PCI Express Capability List Pointer Register*/ -+/*PEX_CAPABILTY_LIST_POINTER (PXCLP)*/ -+ -+#define PXCLP_CAPPTR_OFFS 0 /* Capability List Pointer */ -+#define PXCLP_CAPPTR_MASK (0xff << PXCLP_CAPPTR_OFFS) -+ -+/* PCI Express Interrupt Pin and Line Register */ -+/*PEX_INTERRUPT_PIN_AND_LINE (PXIPAL)*/ -+ -+#define PXIPAL_INTLINE_OFFS 0 /* Interrupt line (IRQ) */ -+#define PXIPAL_INTLINE_MASK (0xff << PXIPAL_INTLINE_OFFS) -+ -+#define PXIPAL_INTPIN_OFFS 8 /* interrupt pin (A,B,C,D) */ -+#define PXIPAL_INTPIN_MASK (0xff << PXIPAL_INTPIN_OFFS) -+ -+ -+/* PCI Express Power Management Capability Header Register*/ -+/*PEX_POWER_MNG_CAPABILITY (PXPMC)*/ -+ -+#define PXPMC_CAP_ID_OFFS 0 /* Capability ID */ -+#define PXPMC_CAP_ID_MASK (0xff << PXPMC_CAP_ID_OFFS) -+ -+#define PXPMC_NEXT_PTR_OFFS 8 /* Next Item Pointer */ -+#define PXPMC_NEXT_PTR_MASK (0xff << PXPMC_NEXT_PTR_OFFS) -+ -+#define PXPMC_PMC_VER_OFFS 16 /* PCI Power Management Capability Version*/ -+#define PXPMC_PMC_VER_MASK (0x7 << PXPMC_PMC_VER_OFFS) -+ -+#define PXPMC_DSI BIT21/* Device Specific Initialization */ -+ -+#define PXPMC_AUX_CUR_OFFS 22 /* Auxiliary Current Requirements */ -+#define PXPMC_AUX_CUR_MASK (0x7 << PXPMC_AUX_CUR_OFFS) -+ -+#define PXPMC_D1_SUP BIT25 /* D1 Power Management support*/ -+ -+#define PXPMC_D2_SUP BIT26 /* D2 Power Management support*/ -+ -+#define PXPMC_PME_SUP_OFFS 27 /* PM Event generation support*/ -+#define PXPMC_PME_SUP_MASK (0x1f << PXPMC_PME_SUP_OFFS) -+ -+/* PCI Express Power Management Control and Status Register*/ -+/*PEX_POWER_MNG_STATUS_CONTROL (PXPMSC)*/ -+ -+#define PXPMSC_PM_STATE_OFFS 0 /* Power State */ -+#define PXPMSC_PM_STATE_MASK (0x3 << PXPMSC_PM_STATE_OFFS) -+#define PXPMSC_PM_STATE_D0 (0x0 << PXPMSC_PM_STATE_OFFS) -+#define PXPMSC_PM_STATE_D1 (0x1 << PXPMSC_PM_STATE_OFFS) -+#define PXPMSC_PM_STATE_D2 (0x2 << PXPMSC_PM_STATE_OFFS) -+#define PXPMSC_PM_STATE_D3 (0x3 << PXPMSC_PM_STATE_OFFS) -+ -+#define PXPMSC_PME_EN BIT8/* PM_PME Message Generation Enable */ -+ -+#define PXPMSC_PM_DATA_SEL_OFFS 9 /* Data Select*/ -+#define PXPMSC_PM_DATA_SEL_MASK (0xf << PXPMSC_PM_DATA_SEL_OFFS) -+ -+#define PXPMSC_PM_DATA_SCALE_OFFS 13 /* Data Scale */ -+#define PXPMSC_PM_DATA_SCALE_MASK (0x3 << PXPMSC_PM_DATA_SCALE_OFFS) -+ -+#define PXPMSC_PME_STAT BIT15/* PME Status */ -+ -+#define PXPMSC_PM_DATA_OFFS 24 /* State Data */ -+#define PXPMSC_PM_DATA_MASK (0xff << PXPMSC_PM_DATA_OFFS) -+ -+ -+/* PCI Express MSI Message Control Register*/ -+/*PEX_MSI_MESSAGE_CONTROL (PXMMC)*/ -+ -+#define PXMMC_CAP_ID_OFFS 0 /* Capability ID */ -+#define PXMMC_CAP_ID_MASK (0xff << PXMMC_CAP_ID_OFFS) -+ -+#define PXMMC_NEXT_PTR_OFFS 8 /* Next Item Pointer */ -+#define PXMMC_NEXT_PTR_MASK (0xff << PXMMC_NEXT_PTR_OFFS) -+ -+#define PXMMC_MSI_EN BIT18 /* MSI Enable */ -+ -+#define PXMMC_MULTI_CAP_OFFS 17 /* Multiple Message Capable */ -+#define PXMMC_MULTI_CAP_MASK (0x7 << PXMMC_MULTI_CAP_OFFS) -+ -+#define PXMMC_MULTI_EN_OFFS 20 /* Multiple Messages Enable */ -+#define PXMMC_MULTI_EN_MASK (0x7 << PXMMC_MULTI_EN_OFFS) -+ -+#define PXMMC_ADDR64 BIT23 /* 64-bit Addressing Capable */ -+ -+ -+/* PCI Express MSI Message Address Register*/ -+/*PEX_MSI_MESSAGE_ADDR (PXMMA)*/ -+ -+#define PXMMA_MSI_ADDR_OFFS 2 /* Message Address corresponds to -+ Address[31:2] of the MSI MWr TLP*/ -+#define PXMMA_MSI_ADDR_MASK (0x3fffffff << PXMMA_MSI_ADDR_OFFS) -+ -+ -+/* PCI Express MSI Message Address (High) Register */ -+/*PEX_MSI_MESSAGE_HIGH_ADDR (PXMMHA)*/ -+ -+#define PXMMA_MSI_ADDR_H_OFFS 0 /* Message Upper Address corresponds to -+ Address[63:32] of the MSI MWr TLP*/ -+#define PXMMA_MSI_ADDR_H_MASK (0xffffffff << PXMMA_MSI_ADDR_H_OFFS ) -+ -+ -+/* PCI Express MSI Message Data Register*/ -+/*PEX_MSI_MESSAGE_DATA (PXMMD)*/ -+ -+#define PXMMD_MSI_DATA_OFFS 0 /* Message Data */ -+#define PXMMD_MSI_DATA_MASK (0xffff << PXMMD_MSI_DATA_OFFS ) -+ -+ -+/* PCI Express Capability Register*/ -+/*PEX_CAPABILITY_REG (PXCR)*/ -+ -+#define PXCR_CAP_ID_OFFS 0 /* Capability ID*/ -+#define PXCR_CAP_ID_MASK (0xff << PXCR_CAP_ID_OFFS) -+ -+#define PXCR_NEXT_PTR_OFFS 8 /* Next Item Pointer*/ -+#define PXCR_NEXT_PTR_MASK (0xff << PXCR_NEXT_PTR_OFFS) -+ -+#define PXCR_CAP_VER_OFFS 16 /* Capability Version*/ -+#define PXCR_CAP_VER_MASK (0xf << PXCR_CAP_VER_OFFS) -+ -+#define PXCR_DEV_TYPE_OFFS 20 /* Device/Port Type*/ -+#define PXCR_DEV_TYPE_MASK (0xf << PXCR_DEV_TYPE_OFFS) -+ -+#define PXCR_SLOT_IMP BIT24 /* Slot Implemented*/ -+ -+#define PXCR_INT_MSG_NUM_OFFS 25 /* Interrupt Message Number*/ -+#define PXCR_INT_MSG_NUM_MASK (0x1f << PXCR_INT_MSG_NUM_OFFS) -+ -+ -+/* PCI Express Device Capabilities Register */ -+/*PEX_DEV_CAPABILITY_REG (PXDCR)*/ -+ -+#define PXDCR_MAX_PLD_SIZE_SUP_OFFS 0 /* Maximum Payload Size Supported*/ -+#define PXDCR_MAX_PLD_SIZE_SUP_MASK (0x7 << PXDCR_MAX_PLD_SIZE_SUP_OFFS) -+ -+#define PXDCR_EP_L0S_ACC_LAT_OFFS 6/* Endpoint L0s Acceptable Latency*/ -+#define PXDCR_EP_L0S_ACC_LAT_MASK (0x7 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+#define PXDCR_EP_L0S_ACC_LAT_64NS_LESS (0x0 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+#define PXDCR_EP_L0S_ACC_LAT_64NS_128NS (0x1 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+#define PXDCR_EP_L0S_ACC_LAT_128NS_256NS (0x2 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+#define PXDCR_EP_L0S_ACC_LAT_256NS_512NS (0x3 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+#define PXDCR_EP_L0S_ACC_LAT_512NS_1US (0x4 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+#define PXDCR_EP_L0S_ACC_LAT_1US_2US (0x5 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+#define PXDCR_EP_L0S_ACC_LAT_2US_4US (0x6 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+#define PXDCR_EP_L0S_ACC_LAT_4US_MORE (0x7 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+ -+#define PXDCR_EP_L1_ACC_LAT_OFFS 9 /* Endpoint L1 Acceptable Latency*/ -+#define PXDCR_EP_L1_ACC_LAT_MASK (0x7 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXDCR_EP_L1_ACC_LAT_64NS_LESS (0x0 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXDCR_EP_L1_ACC_LAT_64NS_128NS (0x1 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXDCR_EP_L1_ACC_LAT_128NS_256NS (0x2 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXDCR_EP_L1_ACC_LAT_256NS_512NS (0x3 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXDCR_EP_L1_ACC_LAT_512NS_1US (0x4 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXDCR_EP_L1_ACC_LAT_1US_2US (0x5 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXDCR_EP_L1_ACC_LAT_2US_4US (0x6 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXDCR_EP_L1_ACC_LAT_4US_MORE (0x7 << PXDCR_EP_L1_ACC_LAT_OFFS) -+ -+ -+#define PXDCR_ATT_BUT_PRS_OFFS 12 /* Attention Button Present*/ -+#define PXDCR_ATT_BUT_PRS_MASK BIT12 -+#define PXDCR_ATT_BUT_PRS_IMPLEMENTED BIT12 -+ -+#define PXDCR_ATT_IND_PRS_OFFS 13 /* Attention Indicator Present*/ -+#define PXDCR_ATT_IND_PRS_MASK BIT13 -+#define PXDCR_ATT_IND_PRS_IMPLEMENTED BIT13 -+ -+#define PXDCR_PWR_IND_PRS_OFFS 14/* Power Indicator Present*/ -+#define PXDCR_PWR_IND_PRS_MASK BIT14 -+#define PXDCR_PWR_IND_PRS_IMPLEMENTED BIT14 -+ -+#define PXDCR_CAP_SPL_VAL_OFFS 18 /*Captured Slot Power Limit -+ Value*/ -+#define PXDCR_CAP_SPL_VAL_MASK (0xff << PXDCR_CAP_SPL_VAL_OFFS) -+ -+#define PXDCR_CAP_SP_LSCL_OFFS 26 /* Captured Slot Power Limit -+ Scale */ -+#define PXDCR_CAP_SP_LSCL_MASK (0x3 << PXDCR_CAP_SP_LSCL_OFFS) -+ -+/* PCI Express Device Control Status Register */ -+/*PEX_DEV_CTRL_STAT_REG (PXDCSR)*/ -+ -+#define PXDCSR_COR_ERR_REP_EN BIT0 /* Correctable Error Reporting Enable*/ -+#define PXDCSR_NF_ERR_REP_EN BIT1 /* Non-Fatal Error Reporting Enable*/ -+#define PXDCSR_F_ERR_REP_EN BIT2 /* Fatal Error Reporting Enable*/ -+#define PXDCSR_UR_REP_EN BIT3 /* Unsupported Request (UR) -+ Reporting Enable*/ -+#define PXDCSR_EN_RO BIT4 /* Enable Relaxed Ordering*/ -+ -+#define PXDCSR_MAX_PLD_SZ_OFFS 5 /* Maximum Payload Size*/ -+#define PXDCSR_MAX_PLD_SZ_MASK (0x7 << PXDCSR_MAX_PLD_SZ_OFFS) -+#define PXDCSR_MAX_PLD_SZ_128B (0x0 << PXDCSR_MAX_PLD_SZ_OFFS) -+#define PXDCSR_EN_NS BIT11 /* Enable No Snoop*/ -+ -+#define PXDCSR_MAX_RD_RQ_SZ_OFFS 12 /* Maximum Read Request Size*/ -+#define PXDCSR_MAX_RD_RQ_SZ_MASK (0x7 << PXDCSR_MAX_RD_RQ_SZ_OFFS) -+#define PXDCSR_MAX_RD_RQ_SZ_128B (0x0 << PXDCSR_MAX_RD_RQ_SZ_OFFS) -+#define PXDCSR_MAX_RD_RQ_SZ_256B (0x1 << PXDCSR_MAX_RD_RQ_SZ_OFFS) -+#define PXDCSR_MAX_RD_RQ_SZ_512B (0x2 << PXDCSR_MAX_RD_RQ_SZ_OFFS) -+#define PXDCSR_MAX_RD_RQ_SZ_1KB (0x3 << PXDCSR_MAX_RD_RQ_SZ_OFFS) -+#define PXDCSR_MAX_RD_RQ_SZ_2KB (0x4 << PXDCSR_MAX_RD_RQ_SZ_OFFS) -+#define PXDCSR_MAX_RD_RQ_SZ_4KB (0x5 << PXDCSR_MAX_RD_RQ_SZ_OFFS) -+ -+#define PXDCSR_COR_ERR_DET BIT16 /* Correctable Error Detected*/ -+#define PXDCSR_NF_ERR_DET BIT17 /* Non-Fatal Error Detected.*/ -+#define PXDCSR_F_ERR_DET BIT18 /* Fatal Error Detected.*/ -+#define PXDCSR_UR_DET BIT19 /* Unsupported Request Detected */ -+#define PXDCSR_AUX_PWR_DET BIT20 /* Reserved*/ -+ -+#define PXDCSR_TRANS_PEND_OFFS 21 /* Transactions Pending*/ -+#define PXDCSR_TRANS_PEND_MASK BIT21 -+#define PXDCSR_TRANS_PEND_NOT_COMPLETED (0x1 << PXDCSR_TRANS_PEND_OFFS) -+ -+ -+/* PCI Express Link Capabilities Register*/ -+/*PEX_LINK_CAPABILITY_REG (PXLCR)*/ -+ -+#define PXLCR_MAX_LINK_SPD_OFFS 0 /* Maximum Link Speed*/ -+#define PXLCR_MAX_LINK_SPD_MASK (0xf << PXLCR_MAX_LINK_SPD_OFFS) -+ -+#define PXLCR_MAX_LNK_WDTH_OFFS 3 /* Maximum Link Width*/ -+#define PXLCR_MAX_LNK_WDTH_MASK (0x3f << PXLCR_MAX_LNK_WDTH_OFFS) -+ -+#define PXLCR_ASPM_SUP_OFFS 10 /* Active State Link PM Support*/ -+#define PXLCR_ASPM_SUP_MASK (0x3 << PXLCR_ASPM_SUP_OFFS) -+ -+#define PXLCR_L0S_EXT_LAT_OFFS 12 /* L0s Exit Latency*/ -+#define PXLCR_L0S_EXT_LAT_MASK (0x7 << PXLCR_L0S_EXT_LAT_OFFS) -+#define PXLCR_L0S_EXT_LAT_64NS_LESS (0x0 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXLCR_L0S_EXT_LAT_64NS_128NS (0x1 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXLCR_L0S_EXT_LAT_128NS_256NS (0x2 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXLCR_L0S_EXT_LAT_256NS_512NS (0x3 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXLCR_L0S_EXT_LAT_512NS_1US (0x4 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXLCR_L0S_EXT_LAT_1US_2US (0x5 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXLCR_L0S_EXT_LAT_2US_4US (0x6 << PXDCR_EP_L1_ACC_LAT_OFFS) -+ -+#define PXLCR_POR_TNUM_OFFS 24 /* Port Number */ -+#define PXLCR_POR_TNUM_MASK (0xff << PXLCR_POR_TNUM_OFFS) -+ -+/* PCI Express Link Control Status Register */ -+/*PEX_LINK_CTRL_STAT_REG (PXLCSR)*/ -+ -+#define PXLCSR_ASPM_CNT_OFFS 0 /* Active State Link PM Control */ -+#define PXLCSR_ASPM_CNT_MASK (0x3 << PXLCSR_ASPM_CNT_OFFS) -+#define PXLCSR_ASPM_CNT_DISABLED (0x0 << PXLCSR_ASPM_CNT_OFFS) -+#define PXLCSR_ASPM_CNT_L0S_ENT_SUPP (0x1 << PXLCSR_ASPM_CNT_OFFS) -+#define PXLCSR_ASPM_CNT_L1S_ENT_SUPP (0x2 << PXLCSR_ASPM_CNT_OFFS) -+#define PXLCSR_ASPM_CNT_L0S_L1S_ENT_SUPP (0x3 << PXLCSR_ASPM_CNT_OFFS) -+ -+#define PXLCSR_RCB_OFFS 3 /* Read Completion Boundary */ -+#define PXLCSR_RCB_MASK BIT3 -+#define PXLCSR_RCB_64B (0 << PXLCSR_RCB_OFFS) -+#define PXLCSR_RCB_128B (1 << PXLCSR_RCB_OFFS) -+ -+#define PXLCSR_LNK_DIS BIT4 /* Link Disable */ -+#define PXLCSR_RETRN_LNK BIT5 /* Retrain Link */ -+#define PXLCSR_CMN_CLK_CFG BIT6 /* Common Clock Configuration */ -+#define PXLCSR_EXTD_SNC BIT7 /* Extended Sync */ -+ -+#define PXLCSR_LNK_SPD_OFFS 16 /* Link Speed */ -+#define PXLCSR_LNK_SPD_MASK (0xf << PXLCSR_LNK_SPD_OFFS) -+ -+#define PXLCSR_NEG_LNK_WDTH_OFFS 20 /* Negotiated Link Width */ -+#define PXLCSR_NEG_LNK_WDTH_MASK (0x3f << PXLCSR_NEG_LNK_WDTH_OFFS) -+#define PXLCSR_NEG_LNK_WDTH_X1 (0x1 << PXLCSR_NEG_LNK_WDTH_OFFS) -+ -+#define PXLCSR_LNK_TRN BIT27 /* Link Training */ -+ -+#define PXLCSR_SLT_CLK_CFG_OFFS 28 /* Slot Clock Configuration */ -+#define PXLCSR_SLT_CLK_CFG_MASK BIT28 -+#define PXLCSR_SLT_CLK_CFG_INDPNT (0x0 << PXLCSR_SLT_CLK_CFG_OFFS) -+#define PXLCSR_SLT_CLK_CFG_REF (0x1 << PXLCSR_SLT_CLK_CFG_OFFS) -+ -+/* PCI Express Advanced Error Report Header Register */ -+/*PEX_ADV_ERR_RPRT_HDR_TRGT_REG (PXAERHTR)*/ -+ -+/* PCI Express Uncorrectable Error Status Register*/ -+/*PEX_UNCORRECT_ERR_STAT_REG (PXUESR)*/ -+ -+/* PCI Express Uncorrectable Error Mask Register */ -+/*PEX_UNCORRECT_ERR_MASK_REG (PXUEMR)*/ -+ -+/* PCI Express Uncorrectable Error Severity Register */ -+/*PEX_UNCORRECT_ERR_SERVITY_REG (PXUESR)*/ -+ -+/* PCI Express Correctable Error Status Register */ -+/*PEX_CORRECT_ERR_STAT_REG (PXCESR)*/ -+ -+/* PCI Express Correctable Error Mask Register */ -+/*PEX_CORRECT_ERR_MASK_REG (PXCEMR)*/ -+ -+/* PCI Express Advanced Error Capability and Control Register*/ -+/*PEX_ADV_ERR_CAPABILITY_CTRL_REG (PXAECCR)*/ -+ -+/* PCI Express Header Log First DWORD Register*/ -+/*PEX_HDR_LOG_FIRST_DWORD_REG (PXHLFDR)*/ -+ -+/* PCI Express Header Log Second DWORD Register*/ -+/*PEX_HDR_LOG_SECOND_DWORD_REG (PXHLSDR)*/ -+ -+/* PCI Express Header Log Third DWORD Register*/ -+/*PEX_HDR_LOG_THIRD_DWORD_REG (PXHLTDR)*/ -+ -+/* PCI Express Header Log Fourth DWORD Register*/ -+/*PEX_HDR_LOG_FOURTH_DWORD_REG (PXHLFDR)*/ -+ -+#ifdef __cplusplus -+} -+#endif /* __cplusplus */ -+ -+#endif /* #ifndef __INCPEXREGSH */ -+ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c 2010-11-09 20:28:11.822495468 +0100 -@@ -0,0 +1,313 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "mvPex.h" -+ -+//#define MV_DEBUG -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+/* locals */ -+typedef struct -+{ -+ MV_U32 data; -+ MV_U32 mask; -+}PEX_HEADER_DATA; -+ -+/* local function forwad decleration */ -+MV_U32 mvPexHwConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, -+ MV_U32 regOff); -+MV_STATUS mvPexHwConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data); -+void resetPexConfig(MV_U32 pexIf, MV_U32 bus, MV_U32 dev); -+ -+ -+PEX_HEADER_DATA configHdr[16] = -+{ -+{0x888811ab, 0x00000000}, /*[device ID, vendor ID] */ -+{0x00100007, 0x0000ffff}, /*[status register, command register] */ -+{0x0604000e, 0x00000000}, /*[programming interface, sub class code, class code, revision ID] */ -+{0x00010008, 0x00000000}, /*[BIST, header type, latency time, cache line] */ -+{0x00000000, 0x00000000}, /*[base address 0] */ -+{0x00000000, 0x00000000}, /*[base address 1] */ -+{0x00000000, 0x00ffffff}, /*[secondary latency timersubordinate bus number, secondary bus number, primary bus number] */ -+{0x0000f101, 0x00000000}, /*[secondary status ,IO limit, IO base] */ -+{0x9ff0a000, 0x00000000}, /*[memory limit, memory base] */ -+{0x0001fff1, 0x00000000}, /*[prefetch memory limit, prefetch memory base] */ -+{0xffffffff, 0x00000000}, /*[prefetch memory base upper] */ -+{0x00000000, 0x00000000}, /*[prefetch memory limit upper] */ -+{0xeffff000, 0x00000000}, /*[IO limit upper 16 bits, IO base upper 16 bits] */ -+{0x00000000, 0x00000000}, /*[reserved, capability pointer] */ -+{0x00000000, 0x00000000}, /*[expansion ROM base address] */ -+{0x00000000, 0x000000FF}, /*[bridge control, interrupt pin, interrupt line] */ -+}; -+ -+ -+#define HEADER_WRITE(data, offset) configHdr[offset/4].data = ((configHdr[offset/4].data & ~configHdr[offset/4].mask) | \ -+ (data & configHdr[offset/4].mask)) -+#define HEADER_READ(offset) configHdr[offset/4].data -+ -+/******************************************************************************* -+* mvVrtBrgPexInit - Initialize PEX interfaces -+* -+* DESCRIPTION: -+* -+* This function is responsible of intialization of the Pex Interface , It -+* configure the Pex Bars and Windows in the following manner: -+* -+* Assumptions : -+* Bar0 is always internal registers bar -+* Bar1 is always the DRAM bar -+* Bar2 is always the Device bar -+* -+* 1) Sets the Internal registers bar base by obtaining the base from -+* the CPU Interface -+* 2) Sets the DRAM bar base and size by getting the base and size from -+* the CPU Interface when the size is the sum of all enabled DRAM -+* chip selects and the base is the base of CS0 . -+* 3) Sets the Device bar base and size by getting these values from the -+* CPU Interface when the base is the base of the lowest base of the -+* Device chip selects, and the -+* -+* -+* INPUT: -+* -+* pexIf - PEX interface number. -+* -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK if function success otherwise MV_ERROR or MV_BAD_PARAM -+* -+*******************************************************************************/ -+MV_STATUS mvPexVrtBrgInit(MV_U32 pexIf) -+{ -+ /* reset PEX tree to recover previous U-boot/Boot configurations */ -+ MV_U32 localBus = mvPexLocalBusNumGet(pexIf); -+ -+ -+ resetPexConfig(pexIf, localBus, 1); -+ return MV_OK; -+} -+ -+ -+MV_U32 mvPexVrtBrgConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, -+ MV_U32 regOff) -+{ -+ -+ MV_U32 localBus = mvPexLocalBusNumGet(pexIf); -+ MV_U32 localDev = mvPexLocalDevNumGet(pexIf); -+ MV_U32 val; -+ if(bus == localBus) -+ { -+ if(dev > 1) -+ { -+/* on the local device allow only device #0 & #1 */ -+ return 0xffffffff; -+ } -+ else -+ if (dev == localDev) -+ { -+ /* read the memory controller registers */ -+ return mvPexHwConfigRead (pexIf, bus, dev, func, regOff); -+ } -+ else -+ { -+ /* access the virtual brg header */ -+ return HEADER_READ(regOff); -+ } -+ } -+ else -+ if(bus == (localBus + 1)) -+ { -+ /* access the device behind the virtual bridge */ -+ if((dev == localDev) || (dev > 1)) -+ { -+ return 0xffffffff; -+ } -+ else -+ { -+ /* access the device behind the virtual bridge, in this case -+ * change the bus number to the local bus number in order to -+ * generate type 0 config cycle -+ */ -+ mvPexLocalBusNumSet(pexIf, bus); -+ mvPexLocalDevNumSet(pexIf, 1); -+ val = mvPexHwConfigRead (pexIf, bus, 0, func, regOff); -+ mvPexLocalBusNumSet(pexIf, localBus); -+ mvPexLocalDevNumSet(pexIf, localDev); -+ return val; -+ } -+ } -+ /* for all other devices use the HW function to get the -+ * requested registers -+ */ -+ mvPexLocalDevNumSet(pexIf, 1); -+ val = mvPexHwConfigRead (pexIf, bus, dev, func, regOff); -+ mvPexLocalDevNumSet(pexIf, localDev); -+ return val; -+} -+ -+ -+MV_STATUS mvPexVrtBrgConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data) -+{ -+ MV_U32 localBus = mvPexLocalBusNumGet(pexIf); -+ MV_U32 localDev = mvPexLocalDevNumGet(pexIf); -+ MV_STATUS status; -+ -+ if(bus == localBus) -+ { -+ if(dev > 1) -+ { -+ /* on the local device allow only device #0 & #1 */ -+ return MV_ERROR; -+ } -+ else -+ if (dev == localDev) -+ { -+ /* read the memory controller registers */ -+ return mvPexHwConfigWrite (pexIf, bus, dev, func, regOff, data); -+ } -+ else -+ { -+ /* access the virtual brg header */ -+ HEADER_WRITE(data, regOff); -+ return MV_OK; -+ } -+ } -+ else -+ if(bus == (localBus + 1)) -+ { -+ /* access the device behind the virtual bridge */ -+ if((dev == localDev) || (dev > 1)) -+ { -+ return MV_ERROR; -+ } -+ else -+ { -+ /* access the device behind the virtual bridge, in this case -+ * change the bus number to the local bus number in order to -+ * generate type 0 config cycle -+ */ -+ //return mvPexHwConfigWrite (pexIf, localBus, dev, func, regOff, data); -+ mvPexLocalBusNumSet(pexIf, bus); -+ mvPexLocalDevNumSet(pexIf, 1); -+ status = mvPexHwConfigWrite (pexIf, bus, 0, func, regOff, data); -+ mvPexLocalBusNumSet(pexIf, localBus); -+ mvPexLocalDevNumSet(pexIf, localDev); -+ return status; -+ -+ } -+ } -+ /* for all other devices use the HW function to get the -+ * requested registers -+ */ -+ mvPexLocalDevNumSet(pexIf, 1); -+ status = mvPexHwConfigWrite (pexIf, bus, dev, func, regOff, data); -+ mvPexLocalDevNumSet(pexIf, localDev); -+ return status; -+} -+ -+ -+ -+ -+void resetPexConfig(MV_U32 pexIf, MV_U32 bus, MV_U32 dev) -+{ -+ MV_U32 tData; -+ MV_U32 i; -+ -+ /* restore the PEX configuration to initialization state */ -+ /* in case PEX P2P call recursive and reset config */ -+ tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x0); -+ if(tData != 0xffffffff) -+ { -+ /* agent had been found - check whether P2P */ -+ tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x8); -+ if((tData & 0xffff0000) == 0x06040000) -+ {/* P2P */ -+ /* get the sec bus and the subordinate */ -+ MV_U32 secBus; -+ tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x18); -+ secBus = ((tData >> 8) & 0xff); -+ /* now scan on sec bus */ -+ for(i = 0;i < 0xff;i++) -+ { -+ resetPexConfig(pexIf, secBus, i); -+ } -+ /* now reset this device */ -+ DB(mvOsPrintf("Reset bus %d dev %d\n", bus, dev)); -+ mvPexHwConfigWrite(pexIf, bus, dev, 0x0, 0x18, 0x0); -+ DB(mvOsPrintf("Reset bus %d dev %d\n", bus, dev)); -+ } -+ } -+} -+ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h 2010-11-09 20:28:11.861239834 +0100 -@@ -0,0 +1,82 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCVRTBRGPEXH -+#define __INCVRTBRGPEXH -+ -+ -+/* Global Functions prototypes */ -+/* mvPexInit - Initialize PEX interfaces*/ -+MV_STATUS mvPexVrtBrgInit(MV_U32 pexIf); -+ -+/* mvPexConfigRead - Read from configuration space */ -+MV_U32 mvPexVrtBrgConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func,MV_U32 regOff); -+ -+/* mvPexConfigWrite - Write to configuration space */ -+MV_STATUS mvPexVrtBrgConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data); -+ -+ -+#endif /* #ifndef __INCPEXH */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.c 2010-11-09 20:28:11.901246212 +0100 -@@ -0,0 +1,1522 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#include "mvOs.h" -+#include "sflash/mvSFlash.h" -+#include "sflash/mvSFlashSpec.h" -+#include "spi/mvSpi.h" -+#include "spi/mvSpiCmnd.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+ -+/*#define MV_DEBUG*/ -+#ifdef MV_DEBUG -+#define DB(x) x -+#else -+#define DB(x) -+#endif -+ -+/* Globals */ -+static MV_SFLASH_DEVICE_PARAMS sflash[] = { -+ /* ST M25P32 SPI flash, 4MB, 64 sectors of 64K each */ -+ { -+ MV_M25P_WREN_CMND_OPCD, -+ MV_M25P_WRDI_CMND_OPCD, -+ MV_M25P_RDID_CMND_OPCD, -+ MV_M25P_RDSR_CMND_OPCD, -+ MV_M25P_WRSR_CMND_OPCD, -+ MV_M25P_READ_CMND_OPCD, -+ MV_M25P_FAST_RD_CMND_OPCD, -+ MV_M25P_PP_CMND_OPCD, -+ MV_M25P_SE_CMND_OPCD, -+ MV_M25P_BE_CMND_OPCD, -+ MV_M25P_RES_CMND_OPCD, -+ MV_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */ -+ MV_M25P32_SECTOR_SIZE, -+ MV_M25P32_SECTOR_NUMBER, -+ MV_M25P_PAGE_SIZE, -+ "ST M25P32", -+ MV_M25PXXX_ST_MANF_ID, -+ MV_M25P32_DEVICE_ID, -+ MV_M25P32_MAX_SPI_FREQ, -+ MV_M25P32_MAX_FAST_SPI_FREQ, -+ MV_M25P32_FAST_READ_DUMMY_BYTES -+ }, -+ /* ST M25P64 SPI flash, 8MB, 128 sectors of 64K each */ -+ { -+ MV_M25P_WREN_CMND_OPCD, -+ MV_M25P_WRDI_CMND_OPCD, -+ MV_M25P_RDID_CMND_OPCD, -+ MV_M25P_RDSR_CMND_OPCD, -+ MV_M25P_WRSR_CMND_OPCD, -+ MV_M25P_READ_CMND_OPCD, -+ MV_M25P_FAST_RD_CMND_OPCD, -+ MV_M25P_PP_CMND_OPCD, -+ MV_M25P_SE_CMND_OPCD, -+ MV_M25P_BE_CMND_OPCD, -+ MV_M25P_RES_CMND_OPCD, -+ MV_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */ -+ MV_M25P64_SECTOR_SIZE, -+ MV_M25P64_SECTOR_NUMBER, -+ MV_M25P_PAGE_SIZE, -+ "ST M25P64", -+ MV_M25PXXX_ST_MANF_ID, -+ MV_M25P64_DEVICE_ID, -+ MV_M25P64_MAX_SPI_FREQ, -+ MV_M25P64_MAX_FAST_SPI_FREQ, -+ MV_M25P64_FAST_READ_DUMMY_BYTES -+ }, -+ /* ST M25P128 SPI flash, 16MB, 64 sectors of 256K each */ -+ { -+ MV_M25P_WREN_CMND_OPCD, -+ MV_M25P_WRDI_CMND_OPCD, -+ MV_M25P_RDID_CMND_OPCD, -+ MV_M25P_RDSR_CMND_OPCD, -+ MV_M25P_WRSR_CMND_OPCD, -+ MV_M25P_READ_CMND_OPCD, -+ MV_M25P_FAST_RD_CMND_OPCD, -+ MV_M25P_PP_CMND_OPCD, -+ MV_M25P_SE_CMND_OPCD, -+ MV_M25P_BE_CMND_OPCD, -+ MV_M25P_RES_CMND_OPCD, -+ MV_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */ -+ MV_M25P128_SECTOR_SIZE, -+ MV_M25P128_SECTOR_NUMBER, -+ MV_M25P_PAGE_SIZE, -+ "ST M25P128", -+ MV_M25PXXX_ST_MANF_ID, -+ MV_M25P128_DEVICE_ID, -+ MV_M25P128_MAX_SPI_FREQ, -+ MV_M25P128_MAX_FAST_SPI_FREQ, -+ MV_M25P128_FAST_READ_DUMMY_BYTES -+ }, -+ /* Macronix MXIC MX25L6405 SPI flash, 8MB, 128 sectors of 64K each */ -+ { -+ MV_MX25L_WREN_CMND_OPCD, -+ MV_MX25L_WRDI_CMND_OPCD, -+ MV_MX25L_RDID_CMND_OPCD, -+ MV_MX25L_RDSR_CMND_OPCD, -+ MV_MX25L_WRSR_CMND_OPCD, -+ MV_MX25L_READ_CMND_OPCD, -+ MV_MX25L_FAST_RD_CMND_OPCD, -+ MV_MX25L_PP_CMND_OPCD, -+ MV_MX25L_SE_CMND_OPCD, -+ MV_MX25L_BE_CMND_OPCD, -+ MV_MX25L_RES_CMND_OPCD, -+ MV_MX25L_DP_CMND_OPCD, -+ MV_MX25L6405_SECTOR_SIZE, -+ MV_MX25L6405_SECTOR_NUMBER, -+ MV_MXIC_PAGE_SIZE, -+ "MXIC MX25L6405", -+ MV_MXIC_MANF_ID, -+ MV_MX25L6405_DEVICE_ID, -+ MV_MX25L6405_MAX_SPI_FREQ, -+ MV_MX25L6405_MAX_FAST_SPI_FREQ, -+ MV_MX25L6405_FAST_READ_DUMMY_BYTES -+ }, -+ /* SPANSION S25FL128P SPI flash, 16MB, 64 sectors of 256K each */ -+ { -+ MV_S25FL_WREN_CMND_OPCD, -+ MV_S25FL_WRDI_CMND_OPCD, -+ MV_S25FL_RDID_CMND_OPCD, -+ MV_S25FL_RDSR_CMND_OPCD, -+ MV_S25FL_WRSR_CMND_OPCD, -+ MV_S25FL_READ_CMND_OPCD, -+ MV_S25FL_FAST_RD_CMND_OPCD, -+ MV_S25FL_PP_CMND_OPCD, -+ MV_S25FL_SE_CMND_OPCD, -+ MV_S25FL_BE_CMND_OPCD, -+ MV_S25FL_RES_CMND_OPCD, -+ MV_S25FL_DP_CMND_OPCD, -+ MV_S25FL128_SECTOR_SIZE, -+ MV_S25FL128_SECTOR_NUMBER, -+ MV_S25FL_PAGE_SIZE, -+ "SPANSION S25FL128", -+ MV_SPANSION_MANF_ID, -+ MV_S25FL128_DEVICE_ID, -+ MV_S25FL128_MAX_SPI_FREQ, -+ MV_M25P128_MAX_FAST_SPI_FREQ, -+ MV_M25P128_FAST_READ_DUMMY_BYTES -+ } -+}; -+ -+/* Static Functions */ -+static MV_STATUS mvWriteEnable (MV_SFLASH_INFO * pFlinfo); -+static MV_STATUS mvStatusRegGet (MV_SFLASH_INFO * pFlinfo, MV_U8 * pStatReg); -+static MV_STATUS mvStatusRegSet (MV_SFLASH_INFO * pFlinfo, MV_U8 sr); -+static MV_STATUS mvWaitOnWipClear(MV_SFLASH_INFO * pFlinfo); -+static MV_STATUS mvSFlashPageWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, \ -+ MV_U8* pPageBuff, MV_U32 buffSize); -+static MV_STATUS mvSFlashWithDefaultsIdGet (MV_SFLASH_INFO * pFlinfo, \ -+ MV_U8* manId, MV_U16* devId); -+ -+/******************************************************************************* -+* mvWriteEnable - serialize the write enable sequence -+* -+* DESCRIPTION: -+* transmit the sequence for write enable -+* -+********************************************************************************/ -+static MV_STATUS mvWriteEnable(MV_SFLASH_INFO * pFlinfo) -+{ -+ MV_U8 cmd[MV_SFLASH_WREN_CMND_LENGTH]; -+ -+ -+ cmd[0] = sflash[pFlinfo->index].opcdWREN; -+ -+ return mvSpiWriteThenRead(cmd, MV_SFLASH_WREN_CMND_LENGTH, NULL, 0, 0); -+} -+ -+/******************************************************************************* -+* mvStatusRegGet - Retrieve the value of the status register -+* -+* DESCRIPTION: -+* perform the RDSR sequence to get the 8bit status register -+* -+********************************************************************************/ -+static MV_STATUS mvStatusRegGet(MV_SFLASH_INFO * pFlinfo, MV_U8 * pStatReg) -+{ -+ MV_STATUS ret; -+ MV_U8 cmd[MV_SFLASH_RDSR_CMND_LENGTH]; -+ MV_U8 sr[MV_SFLASH_RDSR_REPLY_LENGTH]; -+ -+ -+ -+ -+ cmd[0] = sflash[pFlinfo->index].opcdRDSR; -+ -+ if ((ret = mvSpiWriteThenRead(cmd, MV_SFLASH_RDSR_CMND_LENGTH, sr, -+ MV_SFLASH_RDSR_REPLY_LENGTH,0)) != MV_OK) -+ return ret; -+ -+ *pStatReg = sr[0]; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvWaitOnWipClear - Block waiting for the WIP (write in progress) to be cleared -+* -+* DESCRIPTION: -+* Block waiting for the WIP (write in progress) to be cleared -+* -+********************************************************************************/ -+static MV_STATUS mvWaitOnWipClear(MV_SFLASH_INFO * pFlinfo) -+{ -+ MV_STATUS ret; -+ MV_U32 i; -+ MV_U8 stat; -+ -+ for (i=0; iindex].opcdWRSR; -+ cmd[1] = sr; -+ -+ if ((ret = mvSpiWriteThenRead(cmd, MV_SFLASH_WRSR_CMND_LENGTH, NULL, 0, 0)) != MV_OK) -+ return ret; -+ -+ if ((ret = mvWaitOnWipClear(pFlinfo)) != MV_OK) -+ return ret; -+ -+ mvOsDelay(1); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSFlashPageWr - Write up to 256 Bytes in the same page -+* -+* DESCRIPTION: -+* Write a buffer up to the page size in length provided that the whole address -+* range is within the same page (alligned to page bounderies) -+* -+*******************************************************************************/ -+static MV_STATUS mvSFlashPageWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, -+ MV_U8* pPageBuff, MV_U32 buffSize) -+{ -+ MV_STATUS ret; -+ MV_U8 cmd[MV_SFLASH_PP_CMND_LENGTH]; -+ -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invalid parameter device index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* check that we do not cross the page bounderies */ -+ if (((offset & (sflash[pFlinfo->index].pageSize - 1)) + buffSize) > -+ sflash[pFlinfo->index].pageSize) -+ { -+ DB(mvOsPrintf("%s WARNING: Page allignment problem!\n", __FUNCTION__);) -+ return MV_OUT_OF_RANGE; -+ } -+ -+ /* Issue the Write enable command prior the page program command */ -+ if ((ret = mvWriteEnable(pFlinfo)) != MV_OK) -+ return ret; -+ -+ cmd[0] = sflash[pFlinfo->index].opcdPP; -+ cmd[1] = ((offset >> 16) & 0xFF); -+ cmd[2] = ((offset >> 8) & 0xFF); -+ cmd[3] = (offset & 0xFF); -+ -+ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_PP_CMND_LENGTH, pPageBuff, buffSize)) != MV_OK) -+ return ret; -+ -+ if ((ret = mvWaitOnWipClear(pFlinfo)) != MV_OK) -+ return ret; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSFlashWithDefaultsIdGet - Try to read the manufacturer and Device IDs from -+* the device using the default RDID opcode and the default WREN opcode. -+* -+* DESCRIPTION: -+* This is used to detect a generic device that uses the default opcodes -+* for the WREN and RDID. -+* -+********************************************************************************/ -+static MV_STATUS mvSFlashWithDefaultsIdGet (MV_SFLASH_INFO * pFlinfo, MV_U8* manId, MV_U16* devId) -+{ -+ MV_STATUS ret; -+ MV_U8 cmdRDID[MV_SFLASH_RDID_CMND_LENGTH]; -+ MV_U8 id[MV_SFLASH_RDID_REPLY_LENGTH]; -+ -+ -+ -+ /* Use the default RDID opcode to read the IDs */ -+ cmdRDID[0] = MV_SFLASH_DEFAULT_RDID_OPCD; /* unknown model try default */ -+ if ((ret = mvSpiWriteThenRead(cmdRDID, MV_SFLASH_RDID_CMND_LENGTH, id, MV_SFLASH_RDID_REPLY_LENGTH, 0)) != MV_OK) -+ return ret; -+ -+ *manId = id[0]; -+ *devId = 0; -+ *devId |= (id[1] << 8); -+ *devId |= id[2]; -+ -+ return MV_OK; -+} -+ -+/* -+##################################################################################### -+##################################################################################### -+*/ -+ -+/******************************************************************************* -+* mvSFlashInit - Initialize the serial flash device -+* -+* DESCRIPTION: -+* Perform the neccessary initialization and configuration -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* pFlinfo->baseAddr: base address in fast mode. -+* pFlinfo->index: Index of the flash in the sflash tabel. If the SPI -+* flash device does not support read Id command with -+* the standard opcode, then the user should supply this -+* as an input to skip the autodetection process!!!! -+* -+* OUTPUT: -+* pFlinfo: pointer to the Flash information structure after detection -+* pFlinfo->manufacturerId: Manufacturer ID -+* pFlinfo->deviceId: Device ID -+* pFlinfo->sectorSize: size of the sector (all sectors are the same). -+* pFlinfo->sectorNumber: number of sectors. -+* pFlinfo->pageSize: size of the page. -+* pFlinfo->index: Index of the detected flash in the sflash tabel -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashInit (MV_SFLASH_INFO * pFlinfo) -+{ -+ MV_STATUS ret; -+ MV_U8 manf; -+ MV_U16 dev; -+ MV_U32 indx; -+ MV_BOOL detectFlag = MV_FALSE; -+ -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Initialize the SPI interface with low frequency to make sure that the read ID succeeds */ -+ if ((ret = mvSpiInit(MV_SFLASH_BASIC_SPI_FREQ)) != MV_OK) -+ { -+ mvOsPrintf("%s ERROR: Failed to initialize the SPI interface!\n", __FUNCTION__); -+ return ret; -+ } -+ -+ /* First try to read the Manufacturer and Device IDs */ -+ if ((ret = mvSFlashIdGet(pFlinfo, &manf, &dev)) != MV_OK) -+ { -+ mvOsPrintf("%s ERROR: Failed to get the SFlash ID!\n", __FUNCTION__); -+ return ret; -+ } -+ -+ /* loop over the whole table and look for the appropriate SFLASH */ -+ for (indx=0; indxmanufacturerId = manf; -+ pFlinfo->deviceId = dev; -+ pFlinfo->index = indx; -+ detectFlag = MV_TRUE; -+ } -+ } -+ -+ if(!detectFlag) -+ { -+ mvOsPrintf("%s ERROR: Unknown SPI flash device!\n", __FUNCTION__); -+ return MV_FAIL; -+ } -+ -+ /* fill the info based on the model detected */ -+ pFlinfo->sectorSize = sflash[pFlinfo->index].sectorSize; -+ pFlinfo->sectorNumber = sflash[pFlinfo->index].sectorNumber; -+ pFlinfo->pageSize = sflash[pFlinfo->index].pageSize; -+ -+ /* Set the SPI frequency to the MAX allowed for the device for best performance */ -+ if ((ret = mvSpiBaudRateSet(sflash[pFlinfo->index].spiMaxFreq)) != MV_OK) -+ { -+ mvOsPrintf("%s ERROR: Failed to set the SPI frequency!\n", __FUNCTION__); -+ return ret; -+ } -+ -+ /* As default lock the SR */ -+ if ((ret = mvSFlashStatRegLock(pFlinfo, MV_TRUE)) != MV_OK) -+ return ret; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSFlashSectorErase - Erasse a single sector of the serial flash -+* -+* DESCRIPTION: -+* Issue the erase sector command and address -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* secNumber: sector Number to erase (0 -> (sectorNumber-1)) -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashSectorErase (MV_SFLASH_INFO * pFlinfo, MV_U32 secNumber) -+{ -+ MV_STATUS ret; -+ MV_U8 cmd[MV_SFLASH_SE_CMND_LENGTH]; -+ -+ MV_U32 secAddr = (secNumber * pFlinfo->sectorSize); -+#if 0 -+ MV_U32 i; -+ MV_U32 * pW = (MV_U32*) (secAddr + pFlinfo->baseAddr); -+ MV_U32 erasedWord = 0xFFFFFFFF; -+ MV_U32 wordsPerSector = (pFlinfo->sectorSize / sizeof(MV_U32)); -+ MV_BOOL eraseNeeded = MV_FALSE; -+#endif -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* check that the sector number is valid */ -+ if (secNumber >= pFlinfo->sectorNumber) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter sector number!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* we don't want to access SPI in direct mode from in-direct API, -+ becasue of timing issue between CS asserts. */ -+#if 0 -+ /* First compare to FF and check if erase is needed */ -+ for (i=0; iindex].opcdSE; -+ cmd[1] = ((secAddr >> 16) & 0xFF); -+ cmd[2] = ((secAddr >> 8) & 0xFF); -+ cmd[3] = (secAddr & 0xFF); -+ -+ /* Issue the Write enable command prior the sector erase command */ -+ if ((ret = mvWriteEnable(pFlinfo)) != MV_OK) -+ return ret; -+ -+ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_SE_CMND_LENGTH, NULL, 0)) != MV_OK) -+ return ret; -+ -+ if ((ret = mvWaitOnWipClear(pFlinfo)) != MV_OK) -+ return ret; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSFlashChipErase - Erasse the whole serial flash -+* -+* DESCRIPTION: -+* Issue the bulk (chip) erase command -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashChipErase (MV_SFLASH_INFO * pFlinfo) -+{ -+ MV_STATUS ret; -+ MV_U8 cmd[MV_SFLASH_BE_CMND_LENGTH]; -+ -+ -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ cmd[0] = sflash[pFlinfo->index].opcdBE; -+ -+ /* Issue the Write enable command prior the Bulk erase command */ -+ if ((ret = mvWriteEnable(pFlinfo)) != MV_OK) -+ return ret; -+ -+ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_BE_CMND_LENGTH, NULL, 0)) != MV_OK) -+ return ret; -+ -+ if ((ret = mvWaitOnChipEraseDone(pFlinfo)) != MV_OK) -+ return ret; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSFlashBlockRd - Read from the serial flash -+* -+* DESCRIPTION: -+* Issue the read command and address then perfom the needed read -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* offset: byte offset with the flash to start reading from -+* pReadBuff: pointer to the buffer to read the data in -+* buffSize: size of the buffer to read. -+* -+* OUTPUT: -+* pReadBuff: pointer to the buffer containing the read data -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, -+ MV_U8* pReadBuff, MV_U32 buffSize) -+{ -+ MV_U8 cmd[MV_SFLASH_READ_CMND_LENGTH]; -+ -+ -+ /* check for NULL pointer */ -+ if ((pFlinfo == NULL) || (pReadBuff == NULL)) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ cmd[0] = sflash[pFlinfo->index].opcdREAD; -+ cmd[1] = ((offset >> 16) & 0xFF); -+ cmd[2] = ((offset >> 8) & 0xFF); -+ cmd[3] = (offset & 0xFF); -+ -+ return mvSpiWriteThenRead(cmd, MV_SFLASH_READ_CMND_LENGTH, pReadBuff, buffSize, 0); -+} -+ -+/******************************************************************************* -+* mvSFlashFastBlockRd - Fast read from the serial flash -+* -+* DESCRIPTION: -+* Issue the fast read command and address then perfom the needed read -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* offset: byte offset with the flash to start reading from -+* pReadBuff: pointer to the buffer to read the data in -+* buffSize: size of the buffer to read. -+* -+* OUTPUT: -+* pReadBuff: pointer to the buffer containing the read data -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashFastBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, -+ MV_U8* pReadBuff, MV_U32 buffSize) -+{ -+ MV_U8 cmd[MV_SFLASH_READ_CMND_LENGTH]; -+ MV_STATUS ret; -+ -+ /* check for NULL pointer */ -+ if ((pFlinfo == NULL) || (pReadBuff == NULL)) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* Set the SPI frequency to the MAX allowed for fast-read operations */ -+ mvOsPrintf("Setting freq to %d.\n",sflash[pFlinfo->index].spiMaxFastFreq); -+ if ((ret = mvSpiBaudRateSet(sflash[pFlinfo->index].spiMaxFastFreq)) != MV_OK) -+ { -+ mvOsPrintf("%s ERROR: Failed to set the SPI fast frequency!\n", __FUNCTION__); -+ return ret; -+ } -+ -+ cmd[0] = sflash[pFlinfo->index].opcdFSTRD; -+ cmd[1] = ((offset >> 16) & 0xFF); -+ cmd[2] = ((offset >> 8) & 0xFF); -+ cmd[3] = (offset & 0xFF); -+ -+ -+ ret = mvSpiWriteThenRead(cmd, MV_SFLASH_READ_CMND_LENGTH, pReadBuff, buffSize, -+ sflash[pFlinfo->index].spiFastRdDummyBytes); -+ -+ /* Reset the SPI frequency to the MAX allowed for the device for best performance */ -+ if ((ret = mvSpiBaudRateSet(sflash[pFlinfo->index].spiMaxFreq)) != MV_OK) -+ { -+ mvOsPrintf("%s ERROR: Failed to set the SPI frequency!\n", __FUNCTION__); -+ return ret; -+ } -+ -+ return ret; -+} -+ -+ -+/******************************************************************************* -+* mvSFlashBlockWr - Write a buffer with any size -+* -+* DESCRIPTION: -+* write regardless of the page boundaries and size limit per Page -+* program command -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* offset: byte offset within the flash region -+* pWriteBuff: pointer to the buffer holding the data to program -+* buffSize: size of the buffer to write -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashBlockWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, -+ MV_U8* pWriteBuff, MV_U32 buffSize) -+{ -+ MV_STATUS ret; -+ MV_U32 data2write = buffSize; -+ MV_U32 preAllOffset = (offset & MV_SFLASH_PAGE_ALLIGN_MASK(MV_M25P_PAGE_SIZE)); -+ MV_U32 preAllSz = (preAllOffset ? (MV_M25P_PAGE_SIZE - preAllOffset) : 0); -+ MV_U32 writeOffset = offset; -+ -+ /* check for NULL pointer */ -+#ifndef CONFIG_MARVELL -+ if(NULL == pWriteBuff) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+#endif -+ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* check that the buffer size does not exceed the flash size */ -+ if ((offset + buffSize) > mvSFlashSizeGet(pFlinfo)) -+ { -+ DB(mvOsPrintf("%s WARNING: Write exceeds flash size!\n", __FUNCTION__);) -+ return MV_OUT_OF_RANGE; -+ } -+ -+ /* check if the total block size is less than the first chunk remainder */ -+ if (data2write < preAllSz) -+ preAllSz = data2write; -+ -+ /* check if programing does not start at a 64byte alligned offset */ -+ if (preAllSz) -+ { -+ if ((ret = mvSFlashPageWr(pFlinfo, writeOffset, pWriteBuff, preAllSz)) != MV_OK) -+ return ret; -+ -+ /* increment pointers and counters */ -+ writeOffset += preAllSz; -+ data2write -= preAllSz; -+ pWriteBuff += preAllSz; -+ } -+ -+ /* program the data that fits in complete page chunks */ -+ while (data2write >= sflash[pFlinfo->index].pageSize) -+ { -+ if ((ret = mvSFlashPageWr(pFlinfo, writeOffset, pWriteBuff, sflash[pFlinfo->index].pageSize)) != MV_OK) -+ return ret; -+ -+ /* increment pointers and counters */ -+ writeOffset += sflash[pFlinfo->index].pageSize; -+ data2write -= sflash[pFlinfo->index].pageSize; -+ pWriteBuff += sflash[pFlinfo->index].pageSize; -+ } -+ -+ /* program the last partial chunk */ -+ if (data2write) -+ { -+ if ((ret = mvSFlashPageWr(pFlinfo, writeOffset, pWriteBuff, data2write)) != MV_OK) -+ return ret; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSFlashIdGet - Get the manufacturer and device IDs. -+* -+* DESCRIPTION: -+* Get the Manufacturer and device IDs from the serial flash through -+* writing the RDID command then reading 3 bytes of data. In case that -+* this command was called for the first time in order to detect the -+* manufacturer and device IDs, then the default RDID opcode will be used -+* unless the device index is indicated by the user (in case the SPI flash -+* does not use the default RDID opcode). -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* pManId: pointer to the 8bit variable to hold the manufacturing ID -+* pDevId: pointer to the 16bit variable to hold the device ID -+* -+* OUTPUT: -+* pManId: pointer to the 8bit variable holding the manufacturing ID -+* pDevId: pointer to the 16bit variable holding the device ID -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashIdGet (MV_SFLASH_INFO * pFlinfo, MV_U8* pManId, MV_U16* pDevId) -+{ -+ MV_STATUS ret; -+ MV_U8 cmd[MV_SFLASH_RDID_CMND_LENGTH]; -+ MV_U8 id[MV_SFLASH_RDID_REPLY_LENGTH]; -+ -+ -+ -+ /* check for NULL pointer */ -+ if ((pFlinfo == NULL) || (pManId == NULL) || (pDevId == NULL)) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ return mvSFlashWithDefaultsIdGet(pFlinfo, pManId, pDevId); -+ else -+ cmd[0] = sflash[pFlinfo->index].opcdRDID; -+ -+ if ((ret = mvSpiWriteThenRead(cmd, MV_SFLASH_RDID_CMND_LENGTH, id, MV_SFLASH_RDID_REPLY_LENGTH, 0)) != MV_OK) -+ return ret; -+ -+ *pManId = id[0]; -+ *pDevId = 0; -+ *pDevId |= (id[1] << 8); -+ *pDevId |= id[2]; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSFlashWpRegionSet - Set the Write-Protected region -+* -+* DESCRIPTION: -+* Set the Write-Protected region -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* wpRegion: which region will be protected -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashWpRegionSet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION wpRegion) -+{ -+ MV_U8 wpMask; -+ -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the chip is an ST flash; then WP supports only 3 bits */ -+ if (pFlinfo->manufacturerId == MV_M25PXXX_ST_MANF_ID) -+ { -+ switch (wpRegion) -+ { -+ case MV_WP_NONE: -+ wpMask = MV_M25P_STATUS_BP_NONE; -+ break; -+ -+ case MV_WP_UPR_1OF128: -+ DB(mvOsPrintf("%s WARNING: Invaild option for this flash chip!\n", __FUNCTION__);) -+ return MV_NOT_SUPPORTED; -+ -+ case MV_WP_UPR_1OF64: -+ wpMask = MV_M25P_STATUS_BP_1_OF_64; -+ break; -+ -+ case MV_WP_UPR_1OF32: -+ wpMask = MV_M25P_STATUS_BP_1_OF_32; -+ break; -+ -+ case MV_WP_UPR_1OF16: -+ wpMask = MV_M25P_STATUS_BP_1_OF_16; -+ break; -+ -+ case MV_WP_UPR_1OF8: -+ wpMask = MV_M25P_STATUS_BP_1_OF_8; -+ break; -+ -+ case MV_WP_UPR_1OF4: -+ wpMask = MV_M25P_STATUS_BP_1_OF_4; -+ break; -+ -+ case MV_WP_UPR_1OF2: -+ wpMask = MV_M25P_STATUS_BP_1_OF_2; -+ break; -+ -+ case MV_WP_ALL: -+ wpMask = MV_M25P_STATUS_BP_ALL; -+ break; -+ -+ default: -+ DB(mvOsPrintf("%s WARNING: Invaild parameter WP region!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ } -+ /* check if the manufacturer is MXIC then the WP is 4bits */ -+ else if (pFlinfo->manufacturerId == MV_MXIC_MANF_ID) -+ { -+ switch (wpRegion) -+ { -+ case MV_WP_NONE: -+ wpMask = MV_MX25L_STATUS_BP_NONE; -+ break; -+ -+ case MV_WP_UPR_1OF128: -+ wpMask = MV_MX25L_STATUS_BP_1_OF_128; -+ break; -+ -+ case MV_WP_UPR_1OF64: -+ wpMask = MV_MX25L_STATUS_BP_1_OF_64; -+ break; -+ -+ case MV_WP_UPR_1OF32: -+ wpMask = MV_MX25L_STATUS_BP_1_OF_32; -+ break; -+ -+ case MV_WP_UPR_1OF16: -+ wpMask = MV_MX25L_STATUS_BP_1_OF_16; -+ break; -+ -+ case MV_WP_UPR_1OF8: -+ wpMask = MV_MX25L_STATUS_BP_1_OF_8; -+ break; -+ -+ case MV_WP_UPR_1OF4: -+ wpMask = MV_MX25L_STATUS_BP_1_OF_4; -+ break; -+ -+ case MV_WP_UPR_1OF2: -+ wpMask = MV_MX25L_STATUS_BP_1_OF_2; -+ break; -+ -+ case MV_WP_ALL: -+ wpMask = MV_MX25L_STATUS_BP_ALL; -+ break; -+ -+ default: -+ DB(mvOsPrintf("%s WARNING: Invaild parameter WP region!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ } -+ /* check if the manufacturer is SPANSION then the WP is 4bits */ -+ else if (pFlinfo->manufacturerId == MV_SPANSION_MANF_ID) -+ { -+ switch (wpRegion) -+ { -+ case MV_WP_NONE: -+ wpMask = MV_S25FL_STATUS_BP_NONE; -+ break; -+ -+ case MV_WP_UPR_1OF128: -+ DB(mvOsPrintf("%s WARNING: Invaild option for this flash chip!\n", __FUNCTION__);) -+ return MV_NOT_SUPPORTED; -+ -+ case MV_WP_UPR_1OF64: -+ wpMask = MV_S25FL_STATUS_BP_1_OF_64; -+ break; -+ -+ case MV_WP_UPR_1OF32: -+ wpMask = MV_S25FL_STATUS_BP_1_OF_32; -+ break; -+ -+ case MV_WP_UPR_1OF16: -+ wpMask = MV_S25FL_STATUS_BP_1_OF_16; -+ break; -+ -+ case MV_WP_UPR_1OF8: -+ wpMask = MV_S25FL_STATUS_BP_1_OF_8; -+ break; -+ -+ case MV_WP_UPR_1OF4: -+ wpMask = MV_S25FL_STATUS_BP_1_OF_4; -+ break; -+ -+ case MV_WP_UPR_1OF2: -+ wpMask = MV_S25FL_STATUS_BP_1_OF_2; -+ break; -+ -+ case MV_WP_ALL: -+ wpMask = MV_S25FL_STATUS_BP_ALL; -+ break; -+ -+ -+ default: -+ DB(mvOsPrintf("%s WARNING: Invaild parameter WP region!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ } -+ else -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter Manufacturer ID!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* Verify that the SRWD bit is always set - register is s/w locked */ -+ wpMask |= MV_SFLASH_STATUS_REG_SRWD_MASK; -+ -+ return mvStatusRegSet(pFlinfo, wpMask); -+} -+ -+/******************************************************************************* -+* mvSFlashWpRegionGet - Get the Write-Protected region configured -+* -+* DESCRIPTION: -+* Get from the chip the Write-Protected region configured -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* pWpRegion: pointer to the variable to return the WP region in -+* -+* OUTPUT: -+* wpRegion: pointer to the variable holding the WP region configured -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashWpRegionGet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION * pWpRegion) -+{ -+ MV_STATUS ret; -+ MV_U8 reg; -+ -+ /* check for NULL pointer */ -+ if ((pFlinfo == NULL) || (pWpRegion == NULL)) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ if ((ret = mvStatusRegGet(pFlinfo, ®)) != MV_OK) -+ return ret; -+ -+ /* Check if the chip is an ST flash; then WP supports only 3 bits */ -+ if (pFlinfo->manufacturerId == MV_M25PXXX_ST_MANF_ID) -+ { -+ switch ((reg & MV_M25P_STATUS_REG_WP_MASK)) -+ { -+ case MV_M25P_STATUS_BP_NONE: -+ *pWpRegion = MV_WP_NONE; -+ break; -+ -+ case MV_M25P_STATUS_BP_1_OF_64: -+ *pWpRegion = MV_WP_UPR_1OF64; -+ break; -+ -+ case MV_M25P_STATUS_BP_1_OF_32: -+ *pWpRegion = MV_WP_UPR_1OF32; -+ break; -+ -+ case MV_M25P_STATUS_BP_1_OF_16: -+ *pWpRegion = MV_WP_UPR_1OF16; -+ break; -+ -+ case MV_M25P_STATUS_BP_1_OF_8: -+ *pWpRegion = MV_WP_UPR_1OF8; -+ break; -+ -+ case MV_M25P_STATUS_BP_1_OF_4: -+ *pWpRegion = MV_WP_UPR_1OF4; -+ break; -+ -+ case MV_M25P_STATUS_BP_1_OF_2: -+ *pWpRegion = MV_WP_UPR_1OF2; -+ break; -+ -+ case MV_M25P_STATUS_BP_ALL: -+ *pWpRegion = MV_WP_ALL; -+ break; -+ -+ default: -+ DB(mvOsPrintf("%s WARNING: Unidentified WP region in h/w!\n", __FUNCTION__);) -+ return MV_BAD_VALUE; -+ } -+ } -+ /* check if the manufacturer is MXIC then the WP is 4bits */ -+ else if (pFlinfo->manufacturerId == MV_MXIC_MANF_ID) -+ { -+ switch ((reg & MV_MX25L_STATUS_REG_WP_MASK)) -+ { -+ case MV_MX25L_STATUS_BP_NONE: -+ *pWpRegion = MV_WP_NONE; -+ break; -+ -+ case MV_MX25L_STATUS_BP_1_OF_128: -+ *pWpRegion = MV_WP_UPR_1OF128; -+ break; -+ -+ case MV_MX25L_STATUS_BP_1_OF_64: -+ *pWpRegion = MV_WP_UPR_1OF64; -+ break; -+ -+ case MV_MX25L_STATUS_BP_1_OF_32: -+ *pWpRegion = MV_WP_UPR_1OF32; -+ break; -+ -+ case MV_MX25L_STATUS_BP_1_OF_16: -+ *pWpRegion = MV_WP_UPR_1OF16; -+ break; -+ -+ case MV_MX25L_STATUS_BP_1_OF_8: -+ *pWpRegion = MV_WP_UPR_1OF8; -+ break; -+ -+ case MV_MX25L_STATUS_BP_1_OF_4: -+ *pWpRegion = MV_WP_UPR_1OF4; -+ break; -+ -+ case MV_MX25L_STATUS_BP_1_OF_2: -+ *pWpRegion = MV_WP_UPR_1OF2; -+ break; -+ -+ case MV_MX25L_STATUS_BP_ALL: -+ *pWpRegion = MV_WP_ALL; -+ break; -+ -+ default: -+ DB(mvOsPrintf("%s WARNING: Unidentified WP region in h/w!\n", __FUNCTION__);) -+ return MV_BAD_VALUE; -+ } -+ } -+ /* Check if the chip is an SPANSION flash; then WP supports only 3 bits */ -+ else if (pFlinfo->manufacturerId == MV_SPANSION_MANF_ID) -+ { -+ switch ((reg & MV_S25FL_STATUS_REG_WP_MASK)) -+ { -+ case MV_S25FL_STATUS_BP_NONE: -+ *pWpRegion = MV_WP_NONE; -+ break; -+ -+ case MV_S25FL_STATUS_BP_1_OF_64: -+ *pWpRegion = MV_WP_UPR_1OF64; -+ break; -+ -+ case MV_S25FL_STATUS_BP_1_OF_32: -+ *pWpRegion = MV_WP_UPR_1OF32; -+ break; -+ -+ case MV_S25FL_STATUS_BP_1_OF_16: -+ *pWpRegion = MV_WP_UPR_1OF16; -+ break; -+ -+ case MV_S25FL_STATUS_BP_1_OF_8: -+ *pWpRegion = MV_WP_UPR_1OF8; -+ break; -+ -+ case MV_S25FL_STATUS_BP_1_OF_4: -+ *pWpRegion = MV_WP_UPR_1OF4; -+ break; -+ -+ case MV_S25FL_STATUS_BP_1_OF_2: -+ *pWpRegion = MV_WP_UPR_1OF2; -+ break; -+ -+ case MV_S25FL_STATUS_BP_ALL: -+ *pWpRegion = MV_WP_ALL; -+ break; -+ -+ default: -+ DB(mvOsPrintf("%s WARNING: Unidentified WP region in h/w!\n", __FUNCTION__);) -+ return MV_BAD_VALUE; -+ } -+ } -+ else -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter Manufacturer ID!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSFlashStatRegLock - Lock the status register for writing - W/Vpp -+* pin should be low to take effect -+* -+* DESCRIPTION: -+* Lock the access to the Status Register for writing. This will -+* cause the flash to enter the hardware protection mode if the W/Vpp -+* is low. If the W/Vpp is hi, the chip will be in soft protection mode, but -+* the register will continue to be writable if WREN sequence was used. -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* srLock: enable/disable (MV_TRUE/MV_FALSE) status registor lock mechanism -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashStatRegLock (MV_SFLASH_INFO * pFlinfo, MV_BOOL srLock) -+{ -+ MV_STATUS ret; -+ MV_U8 reg; -+ -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ if ((ret = mvStatusRegGet(pFlinfo, ®)) != MV_OK) -+ return ret; -+ -+ if (srLock) -+ reg |= MV_SFLASH_STATUS_REG_SRWD_MASK; -+ else -+ reg &= ~MV_SFLASH_STATUS_REG_SRWD_MASK; -+ -+ return mvStatusRegSet(pFlinfo, reg); -+} -+ -+/******************************************************************************* -+* mvSFlashSizeGet - Get the size of the SPI flash -+* -+* DESCRIPTION: -+* based on the sector number and size of each sector calculate the total -+* size of the flash memory. -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Size of the flash in bytes. -+* -+* -+*******************************************************************************/ -+MV_U32 mvSFlashSizeGet (MV_SFLASH_INFO * pFlinfo) -+{ -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return 0; -+ } -+ -+ return (pFlinfo->sectorSize * pFlinfo->sectorNumber); -+} -+ -+/******************************************************************************* -+* mvSFlashPowerSaveEnter - Cause the falsh device to go into power save mode -+* -+* DESCRIPTION: -+* Enter a special power save mode. -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Size of the flash in bytes. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashPowerSaveEnter(MV_SFLASH_INFO * pFlinfo) -+{ -+ MV_STATUS ret; -+ MV_U8 cmd[MV_SFLASH_DP_CMND_LENGTH]; -+ -+ -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return 0; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* check that power save mode is supported in the specific device */ -+ if (sflash[pFlinfo->index].opcdPwrSave == MV_SFLASH_NO_SPECIFIC_OPCD) -+ { -+ DB(mvOsPrintf("%s WARNING: Power save not supported for this device!\n", __FUNCTION__);) -+ return MV_NOT_SUPPORTED; -+ } -+ -+ cmd[0] = sflash[pFlinfo->index].opcdPwrSave; -+ -+ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_DP_CMND_LENGTH, NULL, 0)) != MV_OK) -+ return ret; -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvSFlashPowerSaveExit - Cause the falsh device to exit the power save mode -+* -+* DESCRIPTION: -+* Exit the deep power save mode. -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Size of the flash in bytes. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashPowerSaveExit (MV_SFLASH_INFO * pFlinfo) -+{ -+ MV_STATUS ret; -+ MV_U8 cmd[MV_SFLASH_RES_CMND_LENGTH]; -+ -+ -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return 0; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* check that power save mode is supported in the specific device */ -+ if (sflash[pFlinfo->index].opcdRES == MV_SFLASH_NO_SPECIFIC_OPCD) -+ { -+ DB(mvOsPrintf("%s WARNING: Read Electronic Signature not supported for this device!\n", __FUNCTION__);) -+ return MV_NOT_SUPPORTED; -+ } -+ -+ cmd[0] = sflash[pFlinfo->index].opcdRES; -+ -+ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_RES_CMND_LENGTH, NULL, 0)) != MV_OK) -+ return ret; -+ -+ /* add the delay needed for the device to wake up */ -+ mvOsDelay(MV_MXIC_DP_EXIT_DELAY); /* 30 ms */ -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvSFlashModelGet - Retreive the string with the device manufacturer and model -+* -+* DESCRIPTION: -+* Retreive the string with the device manufacturer and model -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* pointer to the string indicating the device manufacturer and model -+* -+* -+*******************************************************************************/ -+const MV_8 * mvSFlashModelGet (MV_SFLASH_INFO * pFlinfo) -+{ -+ static const MV_8 * unknModel = (const MV_8 *)"Unknown"; -+ -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return 0; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return unknModel; -+ } -+ -+ return sflash[pFlinfo->index].deviceModel; -+} -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.h 2010-11-09 20:28:11.941246441 +0100 -@@ -0,0 +1,166 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvSFlashH -+#define __INCmvSFlashH -+ -+#include "mvTypes.h" -+ -+/* MCAROS */ -+#define MV_SFLASH_PAGE_ALLIGN_MASK(pgSz) (pgSz-1) -+#define MV_ARRAY_SIZE(a) ((sizeof(a)) / (sizeof(a[0]))) -+ -+/* Constants */ -+#define MV_INVALID_DEVICE_NUMBER 0xFFFFFFFF -+/* 10 MHz is the minimum possible SPI frequency when tclk is set 200MHz*/ -+#define MV_SFLASH_BASIC_SPI_FREQ 10000000 -+/* enumerations */ -+typedef enum -+{ -+ MV_WP_NONE, /* Unprotect the whole chip */ -+ MV_WP_UPR_1OF128, /* Write protect the upper 1/128 part */ -+ MV_WP_UPR_1OF64, /* Write protect the upper 1/64 part */ -+ MV_WP_UPR_1OF32, /* Write protect the upper 1/32 part */ -+ MV_WP_UPR_1OF16, /* Write protect the upper 1/16 part */ -+ MV_WP_UPR_1OF8, /* Write protect the upper 1/8 part */ -+ MV_WP_UPR_1OF4, /* Write protect the upper 1/4 part */ -+ MV_WP_UPR_1OF2, /* Write protect the upper 1/2 part */ -+ MV_WP_ALL /* Write protect the whole chip */ -+} MV_SFLASH_WP_REGION; -+ -+/* Type Definitions */ -+typedef struct -+{ -+ MV_U8 opcdWREN; /* Write enable opcode */ -+ MV_U8 opcdWRDI; /* Write disable opcode */ -+ MV_U8 opcdRDID; /* Read ID opcode */ -+ MV_U8 opcdRDSR; /* Read Status Register opcode */ -+ MV_U8 opcdWRSR; /* Write Status register opcode */ -+ MV_U8 opcdREAD; /* Read opcode */ -+ MV_U8 opcdFSTRD; /* Fast Read opcode */ -+ MV_U8 opcdPP; /* Page program opcode */ -+ MV_U8 opcdSE; /* Sector erase opcode */ -+ MV_U8 opcdBE; /* Bulk erase opcode */ -+ MV_U8 opcdRES; /* Read electronic signature */ -+ MV_U8 opcdPwrSave; /* Go into power save mode */ -+ MV_U32 sectorSize; /* Size of each sector */ -+ MV_U32 sectorNumber; /* Number of sectors */ -+ MV_U32 pageSize; /* size of each page */ -+ const char * deviceModel; /* string with the device model */ -+ MV_U32 manufacturerId; /* The manufacturer ID */ -+ MV_U32 deviceId; /* Device ID */ -+ MV_U32 spiMaxFreq; /* The MAX frequency that can be used with the device */ -+ MV_U32 spiMaxFastFreq; /* The MAX frequency that can be used with the device for fast reads */ -+ MV_U32 spiFastRdDummyBytes; /* Number of dumy bytes to read before real data when working in fast read mode. */ -+} MV_SFLASH_DEVICE_PARAMS; -+ -+typedef struct -+{ -+ MV_U32 baseAddr; /* Flash Base Address used in fast mode */ -+ MV_U8 manufacturerId; /* Manufacturer ID */ -+ MV_U16 deviceId; /* Device ID */ -+ MV_U32 sectorSize; /* Size of each sector - all the same */ -+ MV_U32 sectorNumber; /* Number of sectors */ -+ MV_U32 pageSize; /* Page size - affect allignment */ -+ MV_U32 index; /* index of the device in the sflash table (internal parameter) */ -+} MV_SFLASH_INFO; -+ -+/* Function Prototypes */ -+/* Init */ -+MV_STATUS mvSFlashInit (MV_SFLASH_INFO * pFlinfo); -+ -+/* erase */ -+MV_STATUS mvSFlashSectorErase (MV_SFLASH_INFO * pFlinfo, MV_U32 secNumber); -+MV_STATUS mvSFlashChipErase (MV_SFLASH_INFO * pFlinfo); -+ -+/* Read */ -+MV_STATUS mvSFlashBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, -+ MV_U8* pReadBuff, MV_U32 buffSize); -+MV_STATUS mvSFlashFastBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, -+ MV_U8* pReadBuff, MV_U32 buffSize); -+ -+/* write regardless of the page boundaries and size limit per Page program command */ -+MV_STATUS mvSFlashBlockWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, -+ MV_U8* pWriteBuff, MV_U32 buffSize); -+/* Get IDs */ -+MV_STATUS mvSFlashIdGet (MV_SFLASH_INFO * pFlinfo, MV_U8* pManId, MV_U16* pDevId); -+ -+/* Set and Get the Write Protection region - if the Status register is not locked */ -+MV_STATUS mvSFlashWpRegionSet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION wpRegion); -+MV_STATUS mvSFlashWpRegionGet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION * pWpRegion); -+ -+/* Lock the status register for writing - W/Vpp pin should be low to take effect */ -+MV_STATUS mvSFlashStatRegLock (MV_SFLASH_INFO * pFlinfo, MV_BOOL srLock); -+ -+/* Get the regions sizes */ -+MV_U32 mvSFlashSizeGet (MV_SFLASH_INFO * pFlinfo); -+ -+/* Cause the falsh device to go into power save mode */ -+MV_STATUS mvSFlashPowerSaveEnter(MV_SFLASH_INFO * pFlinfo); -+MV_STATUS mvSFlashPowerSaveExit (MV_SFLASH_INFO * pFlinfo); -+ -+/* Retreive the string with the device manufacturer and model */ -+const MV_8 * mvSFlashModelGet (MV_SFLASH_INFO * pFlinfo); -+ -+#endif /* __INCmvSFlashH */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlashSpec.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlashSpec.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlashSpec.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlashSpec.h 2010-11-09 20:28:11.981246772 +0100 -@@ -0,0 +1,233 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvSFlashSpecH -+#define __INCmvSFlashSpecH -+ -+/* Constants */ -+#define MV_SFLASH_READ_CMND_LENGTH 4 /* 1B opcode + 3B address */ -+#define MV_SFLASH_SE_CMND_LENGTH 4 /* 1B opcode + 3B address */ -+#define MV_SFLASH_BE_CMND_LENGTH 1 /* 1B opcode */ -+#define MV_SFLASH_PP_CMND_LENGTH 4 /* 1B opcode + 3B address */ -+#define MV_SFLASH_WREN_CMND_LENGTH 1 /* 1B opcode */ -+#define MV_SFLASH_WRDI_CMND_LENGTH 1 /* 1B opcode */ -+#define MV_SFLASH_RDID_CMND_LENGTH 1 /* 1B opcode */ -+#define MV_SFLASH_RDID_REPLY_LENGTH 3 /* 1B manf ID and 2B device ID */ -+#define MV_SFLASH_RDSR_CMND_LENGTH 1 /* 1B opcode */ -+#define MV_SFLASH_RDSR_REPLY_LENGTH 1 /* 1B status */ -+#define MV_SFLASH_WRSR_CMND_LENGTH 2 /* 1B opcode + 1B status value */ -+#define MV_SFLASH_DP_CMND_LENGTH 1 /* 1B opcode */ -+#define MV_SFLASH_RES_CMND_LENGTH 1 /* 1B opcode */ -+ -+/* Status Register Bit Masks */ -+#define MV_SFLASH_STATUS_REG_WIP_OFFSET 0 /* bit 0; write in progress */ -+#define MV_SFLASH_STATUS_REG_WP_OFFSET 2 /* bit 2-4; write protect option */ -+#define MV_SFLASH_STATUS_REG_SRWD_OFFSET 7 /* bit 7; lock status register write */ -+#define MV_SFLASH_STATUS_REG_WIP_MASK (0x1 << MV_SFLASH_STATUS_REG_WIP_OFFSET) -+#define MV_SFLASH_STATUS_REG_SRWD_MASK (0x1 << MV_SFLASH_STATUS_REG_SRWD_OFFSET) -+ -+#define MV_SFLASH_MAX_WAIT_LOOP 1000000 -+#define MV_SFLASH_CHIP_ERASE_MAX_WAIT_LOOP 0x50000000 -+ -+#define MV_SFLASH_DEFAULT_RDID_OPCD 0x9F /* Default Read ID */ -+#define MV_SFLASH_DEFAULT_WREN_OPCD 0x06 /* Default Write Enable */ -+#define MV_SFLASH_NO_SPECIFIC_OPCD 0x00 -+ -+/********************************/ -+/* ST M25Pxxx Device Specific */ -+/********************************/ -+ -+/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ -+#define MV_M25PXXX_ST_MANF_ID 0x20 -+#define MV_M25P32_DEVICE_ID 0x2016 -+#define MV_M25P32_MAX_SPI_FREQ 20000000 /* 20MHz */ -+#define MV_M25P32_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ -+#define MV_M25P32_FAST_READ_DUMMY_BYTES 1 -+#define MV_M25P64_DEVICE_ID 0x2017 -+#define MV_M25P64_MAX_SPI_FREQ 20000000 /* 20MHz */ -+#define MV_M25P64_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ -+#define MV_M25P64_FAST_READ_DUMMY_BYTES 1 -+#define MV_M25P128_DEVICE_ID 0x2018 -+#define MV_M25P128_MAX_SPI_FREQ 20000000 /* 20MHz */ -+#define MV_M25P128_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ -+#define MV_M25P128_FAST_READ_DUMMY_BYTES 1 -+ -+ -+/* Sector Sizes and population per device model*/ -+#define MV_M25P32_SECTOR_SIZE 0x10000 /* 64K */ -+#define MV_M25P64_SECTOR_SIZE 0x10000 /* 64K */ -+#define MV_M25P128_SECTOR_SIZE 0x40000 /* 256K */ -+#define MV_M25P32_SECTOR_NUMBER 64 -+#define MV_M25P64_SECTOR_NUMBER 128 -+#define MV_M25P128_SECTOR_NUMBER 64 -+#define MV_M25P_PAGE_SIZE 0x100 /* 256 byte */ -+ -+#define MV_M25P_WREN_CMND_OPCD 0x06 /* Write Enable */ -+#define MV_M25P_WRDI_CMND_OPCD 0x04 /* Write Disable */ -+#define MV_M25P_RDID_CMND_OPCD 0x9F /* Read ID */ -+#define MV_M25P_RDSR_CMND_OPCD 0x05 /* Read Status Register */ -+#define MV_M25P_WRSR_CMND_OPCD 0x01 /* Write Status Register */ -+#define MV_M25P_READ_CMND_OPCD 0x03 /* Sequential Read */ -+#define MV_M25P_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ -+#define MV_M25P_PP_CMND_OPCD 0x02 /* Page Program */ -+#define MV_M25P_SE_CMND_OPCD 0xD8 /* Sector Erase */ -+#define MV_M25P_BE_CMND_OPCD 0xC7 /* Bulk Erase */ -+#define MV_M25P_RES_CMND_OPCD 0xAB /* Read Electronic Signature */ -+ -+/* Status Register Write Protect Bit Masks - 3bits */ -+#define MV_M25P_STATUS_REG_WP_MASK (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_M25P_STATUS_BP_NONE (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_M25P_STATUS_BP_1_OF_64 (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_M25P_STATUS_BP_1_OF_32 (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_M25P_STATUS_BP_1_OF_16 (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_M25P_STATUS_BP_1_OF_8 (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_M25P_STATUS_BP_1_OF_4 (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_M25P_STATUS_BP_1_OF_2 (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_M25P_STATUS_BP_ALL (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+ -+/************************************/ -+/* MXIC MX25L6405 Device Specific */ -+/************************************/ -+ -+/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ -+#define MV_MXIC_MANF_ID 0xC2 -+#define MV_MX25L6405_DEVICE_ID 0x2017 -+#define MV_MX25L6405_MAX_SPI_FREQ 20000000 /* 20MHz */ -+#define MV_MX25L6405_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ -+#define MV_MX25L6405_FAST_READ_DUMMY_BYTES 1 -+#define MV_MXIC_DP_EXIT_DELAY 30 /* 30 ms */ -+ -+/* Sector Sizes and population per device model*/ -+#define MV_MX25L6405_SECTOR_SIZE 0x10000 /* 64K */ -+#define MV_MX25L6405_SECTOR_NUMBER 128 -+#define MV_MXIC_PAGE_SIZE 0x100 /* 256 byte */ -+ -+#define MV_MX25L_WREN_CMND_OPCD 0x06 /* Write Enable */ -+#define MV_MX25L_WRDI_CMND_OPCD 0x04 /* Write Disable */ -+#define MV_MX25L_RDID_CMND_OPCD 0x9F /* Read ID */ -+#define MV_MX25L_RDSR_CMND_OPCD 0x05 /* Read Status Register */ -+#define MV_MX25L_WRSR_CMND_OPCD 0x01 /* Write Status Register */ -+#define MV_MX25L_READ_CMND_OPCD 0x03 /* Sequential Read */ -+#define MV_MX25L_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ -+#define MV_MX25L_PP_CMND_OPCD 0x02 /* Page Program */ -+#define MV_MX25L_SE_CMND_OPCD 0xD8 /* Sector Erase */ -+#define MV_MX25L_BE_CMND_OPCD 0xC7 /* Bulk Erase */ -+#define MV_MX25L_DP_CMND_OPCD 0xB9 /* Deep Power Down */ -+#define MV_MX25L_RES_CMND_OPCD 0xAB /* Read Electronic Signature */ -+ -+/* Status Register Write Protect Bit Masks - 4bits */ -+#define MV_MX25L_STATUS_REG_WP_MASK (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_NONE (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_1_OF_128 (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_1_OF_64 (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_1_OF_32 (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_1_OF_16 (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_1_OF_8 (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_1_OF_4 (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_1_OF_2 (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_ALL (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) -+ -+/************************************/ -+/* SPANSION S25FL128P Device Specific */ -+/************************************/ -+ -+/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ -+#define MV_SPANSION_MANF_ID 0x01 -+#define MV_S25FL128_DEVICE_ID 0x2018 -+#define MV_S25FL128_MAX_SPI_FREQ 33000000 /* 33MHz */ -+#define MV_S25FL128_MAX_FAST_SPI_FREQ 104000000 /* 104MHz */ -+#define MV_S25FL128_FAST_READ_DUMMY_BYTES 1 -+ -+/* Sector Sizes and population per device model*/ -+#define MV_S25FL128_SECTOR_SIZE 0x40000 /* 256K */ -+#define MV_S25FL128_SECTOR_NUMBER 64 -+#define MV_S25FL_PAGE_SIZE 0x100 /* 256 byte */ -+ -+#define MV_S25FL_WREN_CMND_OPCD 0x06 /* Write Enable */ -+#define MV_S25FL_WRDI_CMND_OPCD 0x04 /* Write Disable */ -+#define MV_S25FL_RDID_CMND_OPCD 0x9F /* Read ID */ -+#define MV_S25FL_RDSR_CMND_OPCD 0x05 /* Read Status Register */ -+#define MV_S25FL_WRSR_CMND_OPCD 0x01 /* Write Status Register */ -+#define MV_S25FL_READ_CMND_OPCD 0x03 /* Sequential Read */ -+#define MV_S25FL_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ -+#define MV_S25FL_PP_CMND_OPCD 0x02 /* Page Program */ -+#define MV_S25FL_SE_CMND_OPCD 0xD8 /* Sector Erase */ -+#define MV_S25FL_BE_CMND_OPCD 0xC7 /* Bulk Erase */ -+#define MV_S25FL_DP_CMND_OPCD 0xB9 /* Deep Power Down */ -+#define MV_S25FL_RES_CMND_OPCD 0xAB /* Read Electronic Signature */ -+ -+/* Status Register Write Protect Bit Masks - 4bits */ -+#define MV_S25FL_STATUS_REG_WP_MASK (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_NONE (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_1_OF_128 (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_1_OF_64 (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_1_OF_32 (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_1_OF_16 (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_1_OF_8 (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_1_OF_4 (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_1_OF_2 (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_ALL (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) -+ -+#endif /* __INCmvSFlashSpecH */ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.c 2010-11-09 20:28:12.022495595 +0100 -@@ -0,0 +1,576 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "spi/mvSpi.h" -+#include "spi/mvSpiSpec.h" -+ -+#include "ctrlEnv/mvCtrlEnvLib.h" -+ -+/* #define MV_DEBUG */ -+#ifdef MV_DEBUG -+#define DB(x) x -+#define mvOsPrintf printf -+#else -+#define DB(x) -+#endif -+ -+ -+/******************************************************************************* -+* mvSpi16bitDataTxRx - Transmt and receive data -+* -+* DESCRIPTION: -+* Tx data and block waiting for data to be transmitted -+* -+********************************************************************************/ -+static MV_STATUS mvSpi16bitDataTxRx (MV_U16 txData, MV_U16 * pRxData) -+{ -+ MV_U32 i; -+ MV_BOOL ready = MV_FALSE; -+ -+ /* First clear the bit in the interrupt cause register */ -+ MV_REG_WRITE(MV_SPI_INT_CAUSE_REG, 0x0); -+ -+ /* Transmit data */ -+ MV_REG_WRITE(MV_SPI_DATA_OUT_REG, MV_16BIT_LE(txData)); -+ -+ /* wait with timeout for memory ready */ -+ for (i=0; i> 8) & 0xFF); -+ -+#elif defined(MV_CPU_BE) -+ -+ /* perform the data write to the buffer in two stages with 8bit each */ -+ MV_U8 * bptr = (MV_U8 *)pRxData; -+ MV_U16 data = MV_16BIT_LE(MV_REG_READ(MV_SPI_DATA_IN_REG)); -+ *bptr = ((data >> 8) & 0xFF); -+ ++bptr; -+ *bptr = (data & 0xFF); -+ -+#else -+ #error "CPU endianess isn't defined!\n" -+#endif -+ -+ } -+ else -+ *pRxData = MV_16BIT_LE(MV_REG_READ(MV_SPI_DATA_IN_REG)); -+ } -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvSpi8bitDataTxRx - Transmt and receive data (8bits) -+* -+* DESCRIPTION: -+* Tx data and block waiting for data to be transmitted -+* -+********************************************************************************/ -+static MV_STATUS mvSpi8bitDataTxRx (MV_U8 txData, MV_U8 * pRxData) -+{ -+ MV_U32 i; -+ MV_BOOL ready = MV_FALSE; -+ -+ /* First clear the bit in the interrupt cause register */ -+ MV_REG_WRITE(MV_SPI_INT_CAUSE_REG, 0x0); -+ -+ /* Transmit data */ -+ MV_REG_WRITE(MV_SPI_DATA_OUT_REG, txData); -+ -+ /* wait with timeout for memory ready */ -+ for (i=0; i serialBaudRate) -+ continue; -+ -+ /* check for exact fit */ -+ if ((cpuClk / preScale[i]) == serialBaudRate) -+ { -+ bestPrescaleIndx = i; -+ break; -+ } -+ -+ /* check if this is better than the previous one */ -+ if ((serialBaudRate - (cpuClk / preScale[i])) < minBaudOffset) -+ { -+ minBaudOffset = (serialBaudRate - (cpuClk / preScale[i])); -+ bestPrescaleIndx = i; -+ } -+ } -+ -+ if (bestPrescaleIndx > 14) -+ { -+ mvOsPrintf("%s ERROR: SPI baud rate prescale error!\n", __FUNCTION__); -+ return MV_OUT_OF_RANGE; -+ } -+ -+ /* configure the Prescale */ -+ tempReg = MV_REG_READ(MV_SPI_IF_CONFIG_REG); -+ tempReg = ((tempReg & ~MV_SPI_CLK_PRESCALE_MASK) | (bestPrescaleIndx + 0x12)); -+ MV_REG_WRITE(MV_SPI_IF_CONFIG_REG, tempReg); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSpiCsAssert - Assert the Chip Select pin indicating a new transfer -+* -+* DESCRIPTION: -+* Assert The chip select - used to select an external SPI device -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Success or Error code. -+* -+********************************************************************************/ -+MV_VOID mvSpiCsAssert(MV_VOID) -+{ -+ /* For devices in which the SPI is muxed on the MPP with other interfaces*/ -+ mvMPPConfigToSPI(); -+ mvOsUDelay(1); -+ MV_REG_BIT_SET(MV_SPI_IF_CTRL_REG, MV_SPI_CS_ENABLE_MASK); -+} -+ -+/******************************************************************************* -+* mvSpiCsDeassert - DeAssert the Chip Select pin indicating the end of a -+* SPI transfer sequence -+* -+* DESCRIPTION: -+* DeAssert the chip select pin -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Success or Error code. -+* -+********************************************************************************/ -+MV_VOID mvSpiCsDeassert(MV_VOID) -+{ -+ MV_REG_BIT_RESET(MV_SPI_IF_CTRL_REG, MV_SPI_CS_ENABLE_MASK); -+ -+ /* For devices in which the SPI is muxed on the MPP with other interfaces*/ -+ mvMPPConfigToDefault(); -+} -+ -+/******************************************************************************* -+* mvSpiRead - Read a buffer over the SPI interface -+* -+* DESCRIPTION: -+* Receive (read) a buffer over the SPI interface in 16bit chunks. If the -+* buffer size is odd, then the last chunk will be 8bits. Chip select is not -+* handled at this level. -+* -+* INPUT: -+* pRxBuff: Pointer to the buffer to hold the received data -+* buffSize: length of the pRxBuff -+* -+* OUTPUT: -+* pRxBuff: Pointer to the buffer with the received data -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSpiRead (MV_U8* pRxBuff, MV_U32 buffSize) -+{ -+ MV_STATUS ret; -+ MV_U32 bytesLeft = buffSize; -+ MV_U16* rxPtr = (MV_U16*)pRxBuff; -+ -+ /* check for null parameters */ -+ if (pRxBuff == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check that the buffer pointer and the buffer size are 16bit aligned */ -+ if ((((MV_U32)buffSize & 1) == 0) && (((MV_U32)pRxBuff & 1) == 0)) -+ { -+ /* Verify that the SPI mode is in 16bit mode */ -+ MV_REG_BIT_SET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); -+ -+ /* TX/RX as long we have complete 16bit chunks */ -+ while (bytesLeft >= MV_SPI_16_BIT_CHUNK_SIZE) -+ { -+ /* Transmitted and wait for the transfer to be completed */ -+ if ((ret = mvSpi16bitDataTxRx(MV_SPI_DUMMY_WRITE_16BITS, rxPtr)) != MV_OK) -+ return ret; -+ -+ /* increment the pointers */ -+ rxPtr++; -+ bytesLeft -= MV_SPI_16_BIT_CHUNK_SIZE; -+ } -+ -+ } -+ else -+ { -+ /* Verify that the SPI mode is in 8bit mode */ -+ MV_REG_BIT_RESET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); -+ -+ /* TX/RX in 8bit chanks */ -+ while (bytesLeft > 0) -+ { -+ /* Transmitted and wait for the transfer to be completed */ -+ if ((ret = mvSpi8bitDataTxRx(MV_SPI_DUMMY_WRITE_8BITS, pRxBuff)) != MV_OK) -+ return ret; -+ /* increment the pointers */ -+ pRxBuff++; -+ bytesLeft--; -+ } -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSpiWrite - Transmit a buffer over the SPI interface -+* -+* DESCRIPTION: -+* Transmit a buffer over the SPI interface in 16bit chunks. If the -+* buffer size is odd, then the last chunk will be 8bits. No chip select -+* action is taken. -+* -+* INPUT: -+* pTxBuff: Pointer to the buffer holding the TX data -+* buffSize: length of the pTxBuff -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSpiWrite(MV_U8* pTxBuff, MV_U32 buffSize) -+{ -+ MV_STATUS ret; -+ MV_U32 bytesLeft = buffSize; -+ MV_U16* txPtr = (MV_U16*)pTxBuff; -+ -+ /* check for null parameters */ -+ if (pTxBuff == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check that the buffer pointer and the buffer size are 16bit aligned */ -+ if ((((MV_U32)buffSize & 1) == 0) && (((MV_U32)pTxBuff & 1) == 0)) -+ { -+ /* Verify that the SPI mode is in 16bit mode */ -+ MV_REG_BIT_SET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); -+ -+ /* TX/RX as long we have complete 16bit chunks */ -+ while (bytesLeft >= MV_SPI_16_BIT_CHUNK_SIZE) -+ { -+ /* Transmitted and wait for the transfer to be completed */ -+ if ((ret = mvSpi16bitDataTxRx(*txPtr, NULL)) != MV_OK) -+ return ret; -+ -+ /* increment the pointers */ -+ txPtr++; -+ bytesLeft -= MV_SPI_16_BIT_CHUNK_SIZE; -+ } -+ } -+ else -+ { -+ -+ /* Verify that the SPI mode is in 8bit mode */ -+ MV_REG_BIT_RESET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); -+ -+ /* TX/RX in 8bit chanks */ -+ while (bytesLeft > 0) -+ { -+ /* Transmitted and wait for the transfer to be completed */ -+ if ((ret = mvSpi8bitDataTxRx(*pTxBuff, NULL)) != MV_OK) -+ return ret; -+ -+ /* increment the pointers */ -+ pTxBuff++; -+ bytesLeft--; -+ } -+ } -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvSpiReadWrite - Read and Write a buffer simultanuosely -+* -+* DESCRIPTION: -+* Transmit and receive a buffer over the SPI in 16bit chunks. If the -+* buffer size is odd, then the last chunk will be 8bits. The SPI chip -+* select is not handled implicitely. -+* -+* INPUT: -+* pRxBuff: Pointer to the buffer to write the RX info in -+* pTxBuff: Pointer to the buffer holding the TX info -+* buffSize: length of both the pTxBuff and pRxBuff -+* -+* OUTPUT: -+* pRxBuff: Pointer of the buffer holding the RX data -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSpiReadWrite(MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize) -+{ -+ MV_STATUS ret; -+ MV_U32 bytesLeft = buffSize; -+ MV_U16* txPtr = (MV_U16*)pTxBuff; -+ MV_U16* rxPtr = (MV_U16*)pRxBuff; -+ -+ /* check for null parameters */ -+ if ((pRxBuff == NULL) || (pTxBuff == NULL)) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check that the buffer pointer and the buffer size are 16bit aligned */ -+ if ((((MV_U32)buffSize & 1) == 0) && (((MV_U32)pTxBuff & 1) == 0) && (((MV_U32)pRxBuff & 1) == 0)) -+ { -+ /* Verify that the SPI mode is in 16bit mode */ -+ MV_REG_BIT_SET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); -+ -+ /* TX/RX as long we have complete 16bit chunks */ -+ while (bytesLeft >= MV_SPI_16_BIT_CHUNK_SIZE) -+ { -+ /* Transmitted and wait for the transfer to be completed */ -+ if ((ret = mvSpi16bitDataTxRx(*txPtr, rxPtr)) != MV_OK) -+ return ret; -+ -+ /* increment the pointers */ -+ txPtr++; -+ rxPtr++; -+ bytesLeft -= MV_SPI_16_BIT_CHUNK_SIZE; -+ } -+ } -+ else -+ { -+ /* Verify that the SPI mode is in 8bit mode */ -+ MV_REG_BIT_RESET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); -+ -+ /* TX/RX in 8bit chanks */ -+ while (bytesLeft > 0) -+ { -+ /* Transmitted and wait for the transfer to be completed */ -+ if ( (ret = mvSpi8bitDataTxRx(*pTxBuff, pRxBuff) ) != MV_OK) -+ return ret; -+ pRxBuff++; -+ pTxBuff++; -+ bytesLeft--; -+ } -+ } -+ -+ return MV_OK; -+} -+ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.c 2010-11-09 20:28:12.052495353 +0100 -@@ -0,0 +1,249 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "spi/mvSpi.h" -+#include "spi/mvSpiSpec.h" -+ -+/*#define MV_DEBUG*/ -+#ifdef MV_DEBUG -+#define DB(x) x -+#else -+#define DB(x) -+#endif -+ -+ -+/******************************************************************************* -+* mvSpiReadAndWrite - Read and Write a buffer simultanuousely -+* -+* DESCRIPTION: -+* Transmit and receive a buffer over the SPI in 16bit chunks. If the -+* buffer size is odd, then the last chunk will be 8bits. -+* -+* INPUT: -+* pRxBuff: Pointer to the buffer to write the RX info in -+* pTxBuff: Pointer to the buffer holding the TX info -+* buffSize: length of both the pTxBuff and pRxBuff -+* -+* OUTPUT: -+* pRxBuff: Pointer of the buffer holding the RX data -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSpiReadAndWrite(MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize) -+{ -+ MV_STATUS ret; -+ -+ /* check for null parameters */ -+ if ((pRxBuff == NULL) || (pTxBuff == NULL) || (buffSize == 0)) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* First assert the chip select */ -+ mvSpiCsAssert(); -+ -+ ret = mvSpiReadWrite(pRxBuff, pTxBuff, buffSize); -+ -+ /* Finally deassert the chip select */ -+ mvSpiCsDeassert(); -+ -+ return ret; -+} -+ -+/******************************************************************************* -+* mvSpiWriteThenWrite - Serialize a command followed by the data over the TX line -+* -+* DESCRIPTION: -+* Assert the chip select line. Transmit the command buffer followed by -+* the data buffer. Then deassert the CS line. -+* -+* INPUT: -+* pCmndBuff: Pointer to the command buffer to transmit -+* cmndSize: length of the command size -+* pTxDataBuff: Pointer to the data buffer to transmit -+* txDataSize: length of the data buffer -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSpiWriteThenWrite (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pTxDataBuff, -+ MV_U32 txDataSize) -+{ -+ MV_STATUS ret = MV_OK, tempRet; -+ -+ /* check for null parameters */ -+#ifndef CONFIG_MARVELL -+ if(NULL == pTxDataBuff) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+#endif -+ -+ if (pCmndBuff == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* First assert the chip select */ -+ mvSpiCsAssert(); -+ -+ /* first write the command */ -+ if ((cmndSize) && (pCmndBuff != NULL)) -+ { -+ if ((tempRet = mvSpiWrite(pCmndBuff, cmndSize)) != MV_OK) -+ ret = tempRet; -+ } -+ -+ /* Then write the data buffer */ -+#ifndef CONFIG_MARVELL -+ if (txDataSize) -+#else -+ if ((txDataSize) && (pTxDataBuff != NULL)) -+#endif -+ { -+ if ((tempRet = mvSpiWrite(pTxDataBuff, txDataSize)) != MV_OK) -+ ret = tempRet; -+ } -+ -+ /* Finally deassert the chip select */ -+ mvSpiCsDeassert(); -+ -+ return ret; -+} -+ -+/******************************************************************************* -+* mvSpiWriteThenRead - Serialize a command then read a data buffer -+* -+* DESCRIPTION: -+* Assert the chip select line. Transmit the command buffer then read -+* the data buffer. Then deassert the CS line. -+* -+* INPUT: -+* pCmndBuff: Pointer to the command buffer to transmit -+* cmndSize: length of the command size -+* pRxDataBuff: Pointer to the buffer to read the data in -+* txDataSize: length of the data buffer -+* -+* OUTPUT: -+* pRxDataBuff: Pointer to the buffer holding the data -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSpiWriteThenRead (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pRxDataBuff, -+ MV_U32 rxDataSize,MV_U32 dummyBytesToRead) -+{ -+ MV_STATUS ret = MV_OK, tempRet; -+ MV_U8 dummyByte; -+ -+ /* check for null parameters */ -+ if ((pCmndBuff == NULL) && (pRxDataBuff == NULL)) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* First assert the chip select */ -+ mvSpiCsAssert(); -+ -+ /* first write the command */ -+ if ((cmndSize) && (pCmndBuff != NULL)) -+ { -+ if ((tempRet = mvSpiWrite(pCmndBuff, cmndSize)) != MV_OK) -+ ret = tempRet; -+ } -+ -+ /* Read dummy bytes before real data. */ -+ while(dummyBytesToRead) -+ { -+ mvSpiRead(&dummyByte,1); -+ dummyBytesToRead--; -+ } -+ -+ /* Then write the data buffer */ -+ if ((rxDataSize) && (pRxDataBuff != NULL)) -+ { -+ if ((tempRet = mvSpiRead(pRxDataBuff, rxDataSize)) != MV_OK) -+ ret = tempRet; -+ } -+ -+ /* Finally deassert the chip select */ -+ mvSpiCsDeassert(); -+ -+ return ret; -+} -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.h 2010-11-09 20:28:12.082495364 +0100 -@@ -0,0 +1,82 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvSpiCmndhH -+#define __INCmvSpiCmndhH -+ -+#include "mvTypes.h" -+ -+/* Function Prototypes */ -+ -+/* Simultanuous Read and write */ -+MV_STATUS mvSpiReadAndWrite (MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize); -+ -+/* write command - write a command and then write data */ -+MV_STATUS mvSpiWriteThenWrite (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pTxDataBuff, MV_U32 txDataSize); -+ -+/* read command - write a command and then read data by writing dummy data */ -+MV_STATUS mvSpiWriteThenRead (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pRxDataBuff, -+ MV_U32 rxDataSize,MV_U32 dummyBytesToRead); -+ -+#endif /* __INCmvSpiCmndhH */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.h 2010-11-09 20:28:12.121243940 +0100 -@@ -0,0 +1,94 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvSpihH -+#define __INCmvSpihH -+ -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+ -+/* Function Prototypes */ -+/* Init */ -+MV_STATUS mvSpiInit (MV_U32 serialBaudRate); -+ -+/* Set the Frequency of the Spi clock */ -+MV_STATUS mvSpiBaudRateSet(MV_U32 serialBaudRate); -+ -+/* Assert the SPI chip select */ -+MV_VOID mvSpiCsAssert (MV_VOID); -+ -+/* De-assert the SPI chip select */ -+MV_VOID mvSpiCsDeassert (MV_VOID); -+ -+/* Simultanuous Read and write */ -+MV_STATUS mvSpiReadWrite (MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize); -+ -+/* serialize a buffer on the TX line - Rx is ignored */ -+MV_STATUS mvSpiWrite (MV_U8* pTxBuff, MV_U32 buffSize); -+ -+/* read from the RX line by writing dummy values to the TX line */ -+MV_STATUS mvSpiRead (MV_U8* pRxBuff, MV_U32 buffSize); -+ -+#endif /* __INCmvSpihH */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiSpec.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiSpec.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiSpec.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiSpec.h 2010-11-09 20:28:12.162495430 +0100 -@@ -0,0 +1,98 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvSpiSpecH -+#define __INCmvSpiSpecH -+ -+/* Constants */ -+#define MV_SPI_WAIT_RDY_MAX_LOOP 100000 -+#define MV_SPI_16_BIT_CHUNK_SIZE 2 -+#define MV_SPI_DUMMY_WRITE_16BITS 0xFFFF -+#define MV_SPI_DUMMY_WRITE_8BITS 0xFF -+ -+/* Marvell Flash Device Controller Registers */ -+#define MV_SPI_CTRLR_OFST 0x10600 -+#define MV_SPI_IF_CTRL_REG (MV_SPI_CTRLR_OFST + 0x00) -+#define MV_SPI_IF_CONFIG_REG (MV_SPI_CTRLR_OFST + 0x04) -+#define MV_SPI_DATA_OUT_REG (MV_SPI_CTRLR_OFST + 0x08) -+#define MV_SPI_DATA_IN_REG (MV_SPI_CTRLR_OFST + 0x0c) -+#define MV_SPI_INT_CAUSE_REG (MV_SPI_CTRLR_OFST + 0x10) -+#define MV_SPI_INT_CAUSE_MASK_REG (MV_SPI_CTRLR_OFST + 0x14) -+ -+/* Serial Memory Interface Control Register Masks */ -+#define MV_SPI_CS_ENABLE_OFFSET 0 /* bit 0 */ -+#define MV_SPI_MEMORY_READY_OFFSET 1 /* bit 1 */ -+#define MV_SPI_CS_ENABLE_MASK (0x1 << MV_SPI_CS_ENABLE_OFFSET) -+#define MV_SPI_MEMORY_READY_MASK (0x1 << MV_SPI_MEMORY_READY_OFFSET) -+ -+/* Serial Memory Interface Configuration Register Masks */ -+#define MV_SPI_CLK_PRESCALE_OFFSET 0 /* bit 0-4 */ -+#define MV_SPI_BYTE_LENGTH_OFFSET 5 /* bit 5 */ -+#define MV_SPI_ADDRESS_BURST_LENGTH_OFFSET 8 /* bit 8-9 */ -+#define MV_SPI_CLK_PRESCALE_MASK (0x1F << MV_SPI_CLK_PRESCALE_OFFSET) -+#define MV_SPI_BYTE_LENGTH_MASK (0x1 << MV_SPI_BYTE_LENGTH_OFFSET) -+#define MV_SPI_ADDRESS_BURST_LENGTH_MASK (0x3 << MV_SPI_ADDRESS_BURST_LENGTH_OFFSET) -+ -+#endif /* __INCmvSpiSpecH */ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.c linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.c ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.c 2010-11-09 20:28:12.192495512 +0100 -@@ -0,0 +1,1023 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#include "mvTwsi.h" -+#include "mvTwsiSpec.h" -+#include "cpu/mvCpu.h" -+ -+ -+/*#define MV_DEBUG*/ -+#ifdef MV_DEBUG -+#define DB(x) x -+#else -+#define DB(x) -+#endif -+ -+static MV_VOID twsiIntFlgClr(MV_U8 chanNum); -+static MV_BOOL twsiMainIntGet(MV_U8 chanNum); -+static MV_VOID twsiAckBitSet(MV_U8 chanNum); -+static MV_U32 twsiStsGet(MV_U8 chanNum); -+static MV_VOID twsiReset(MV_U8 chanNum); -+static MV_STATUS twsiAddr7BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command); -+static MV_STATUS twsiAddr10BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command); -+static MV_STATUS twsiDataTransmit(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize); -+static MV_STATUS twsiDataReceive(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize); -+static MV_STATUS twsiTargetOffsSet(MV_U8 chanNum, MV_U32 offset,MV_BOOL moreThen256); -+ -+ -+static MV_BOOL twsiTimeoutChk(MV_U32 timeout, const MV_8 *pString) -+{ -+ if(timeout >= TWSI_TIMEOUT_VALUE) -+ { -+ DB(mvOsPrintf("%s",pString)); -+ return MV_TRUE; -+ } -+ return MV_FALSE; -+ -+} -+/******************************************************************************* -+* mvTwsiStartBitSet - Set start bit on the bus -+* -+* DESCRIPTION: -+* This routine sets the start bit on the TWSI bus. -+* The routine first checks for interrupt flag condition, then it sets -+* the start bit in the TWSI Control register. -+* If the interrupt flag condition check previously was set, the function -+* will clear it. -+* The function then wait for the start bit to be cleared by the HW. -+* Then it waits for the interrupt flag to be set and eventually, the -+* TWSI status is checked to be 0x8 or 0x10(repeated start bit). -+* -+* INPUT: -+* chanNum - TWSI channel. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK is start bit was set successfuly on the bus. -+* MV_FAIL if interrupt flag was set before setting start bit. -+* -+*******************************************************************************/ -+MV_STATUS mvTwsiStartBitSet(MV_U8 chanNum) -+{ -+ MV_BOOL isIntFlag = MV_FALSE; -+ MV_U32 timeout, temp; -+ -+ DB(mvOsPrintf("TWSI: mvTwsiStartBitSet \n")); -+ /* check Int flag */ -+ if(twsiMainIntGet(chanNum)) -+ isIntFlag = MV_TRUE; -+ /* set start Bit */ -+ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); -+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp | TWSI_CONTROL_START_BIT); -+ -+ /* in case that the int flag was set before i.e. repeated start bit */ -+ if(isIntFlag){ -+ DB(mvOsPrintf("TWSI: mvTwsiStartBitSet repeated start Bit\n")); -+ twsiIntFlgClr(chanNum); -+ } -+ -+ /* wait for interrupt */ -+ timeout = 0; -+ while(!twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: mvTwsiStartBitSet ERROR - Start Clear bit TimeOut .\n")) -+ return MV_TIMEOUT; -+ -+ -+ /* check that start bit went down */ -+ if((MV_REG_READ(TWSI_CONTROL_REG(chanNum)) & TWSI_CONTROL_START_BIT) != 0) -+ { -+ mvOsPrintf("TWSI: mvTwsiStartBitSet ERROR - start bit didn't went down\n"); -+ return MV_FAIL; -+ } -+ -+ /* check the status */ -+ temp = twsiStsGet(chanNum); -+ if(( temp != TWSI_START_CON_TRA ) && ( temp != TWSI_REPEATED_START_CON_TRA )) -+ { -+ mvOsPrintf("TWSI: mvTwsiStartBitSet ERROR - status %x after Set Start Bit. \n",temp); -+ return MV_FAIL; -+ } -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvTwsiStopBitSet - Set stop bit on the bus -+* -+* DESCRIPTION: -+* This routine set the stop bit on the TWSI bus. -+* The function then wait for the stop bit to be cleared by the HW. -+* Finally the function checks for status of 0xF8. -+* -+* INPUT: -+* chanNum - TWSI channel -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE is stop bit was set successfuly on the bus. -+* -+*******************************************************************************/ -+MV_STATUS mvTwsiStopBitSet(MV_U8 chanNum) -+{ -+ MV_U32 timeout, temp; -+ -+ /* Generate stop bit */ -+ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); -+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp | TWSI_CONTROL_STOP_BIT); -+ -+ twsiIntFlgClr(chanNum); -+ -+ /* wait for stop bit to come down */ -+ timeout = 0; -+ while( ((MV_REG_READ(TWSI_CONTROL_REG(chanNum)) & TWSI_CONTROL_STOP_BIT) != 0) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: mvTwsiStopBitSet ERROR - Stop bit TimeOut .\n")) -+ return MV_TIMEOUT; -+ -+ /* check that the stop bit went down */ -+ if((MV_REG_READ(TWSI_CONTROL_REG(chanNum)) & TWSI_CONTROL_STOP_BIT) != 0) -+ { -+ mvOsPrintf("TWSI: mvTwsiStopBitSet ERROR - stop bit didn't went down. \n"); -+ return MV_FAIL; -+ } -+ -+ /* check the status */ -+ temp = twsiStsGet(chanNum); -+ if( temp != TWSI_NO_REL_STS_INT_FLAG_IS_KEPT_0){ -+ mvOsPrintf("TWSI: mvTwsiStopBitSet ERROR - status %x after Stop Bit. \n", temp); -+ return MV_FAIL; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* twsiMainIntGet - Get twsi bit from main Interrupt cause. -+* -+* DESCRIPTION: -+* This routine returns the twsi interrupt flag value. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE is interrupt flag is set, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+static MV_BOOL twsiMainIntGet(MV_U8 chanNum) -+{ -+ MV_U32 temp; -+ -+ /* get the int flag bit */ -+ -+ temp = MV_REG_READ(TWSI_CPU_MAIN_INT_CAUSE_REG); -+ if (temp & (TWSI0_CPU_MAIN_INT_BIT << chanNum)) -+ return MV_TRUE; -+ -+ return MV_FALSE; -+} -+/******************************************************************************* -+* twsiIntFlgClr - Clear Interrupt flag. -+* -+* DESCRIPTION: -+* This routine clears the interrupt flag. It does NOT poll the interrupt -+* to make sure the clear. After clearing the interrupt, it waits for at -+* least 1 miliseconds. -+* -+* INPUT: -+* chanNum - TWSI channel -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+static MV_VOID twsiIntFlgClr(MV_U8 chanNum) -+{ -+ MV_U32 temp; -+ -+ /* wait for 1 mili to prevent TWSI register write after write problems */ -+ mvOsDelay(1); -+ /* clear the int flag bit */ -+ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); -+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum),temp & ~(TWSI_CONTROL_INT_FLAG_SET)); -+ -+ /* wait for 1 mili sec for the clear to take effect */ -+ mvOsDelay(1); -+ -+ return; -+} -+ -+ -+/******************************************************************************* -+* twsiAckBitSet - Set acknowledge bit on the bus -+* -+* DESCRIPTION: -+* This routine set the acknowledge bit on the TWSI bus. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+static MV_VOID twsiAckBitSet(MV_U8 chanNum) -+{ -+ MV_U32 temp; -+ -+ /*Set the Ack bit */ -+ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); -+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp | TWSI_CONTROL_ACK); -+ -+ /* Add delay of 1ms */ -+ mvOsDelay(1); -+ return; -+} -+ -+ -+/******************************************************************************* -+* twsiInit - Initialize TWSI interface -+* -+* DESCRIPTION: -+* This routine: -+* -Reset the TWSI. -+* -Initialize the TWSI clock baud rate according to given frequancy -+* parameter based on Tclk frequancy and enables TWSI slave. -+* -Set the ack bit. -+* -Assign the TWSI slave address according to the TWSI address Type. -+* -+* -+* INPUT: -+* chanNum - TWSI channel -+* frequancy - TWSI frequancy in KHz. (up to 100KHZ) -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Actual frequancy. -+* -+*******************************************************************************/ -+MV_U32 mvTwsiInit(MV_U8 chanNum, MV_HZ frequancy, MV_U32 Tclk, MV_TWSI_ADDR *pTwsiAddr, MV_BOOL generalCallEnable) -+{ -+ MV_U32 n,m,freq,margin,minMargin = 0xffffffff; -+ MV_U32 power; -+ MV_U32 actualFreq = 0,actualN = 0,actualM = 0,val; -+ -+ if(frequancy > 100000) -+ { -+ mvOsPrintf("Warning TWSI frequancy is too high, please use up tp 100Khz. \n"); -+ } -+ -+ DB(mvOsPrintf("TWSI: mvTwsiInit - Tclk = %d freq = %d\n",Tclk,frequancy)); -+ /* Calucalte N and M for the TWSI clock baud rate */ -+ for(n = 0 ; n < 8 ; n++) -+ { -+ for(m = 0 ; m < 16 ; m++) -+ { -+ power = 2 << n; /* power = 2^(n+1) */ -+ freq = Tclk/(10*(m+1)*power); -+ margin = MV_ABS(frequancy - freq); -+ if(margin < minMargin) -+ { -+ minMargin = margin; -+ actualFreq = freq; -+ actualN = n; -+ actualM = m; -+ } -+ } -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiInit - actN %d actM %d actFreq %d\n",actualN , actualM, actualFreq)); -+ /* Reset the TWSI logic */ -+ twsiReset(chanNum); -+ -+ /* Set the baud rate */ -+ val = ((actualM<< TWSI_BAUD_RATE_M_OFFS) | actualN << TWSI_BAUD_RATE_N_OFFS); -+ MV_REG_WRITE(TWSI_STATUS_BAUDE_RATE_REG(chanNum),val); -+ -+ /* Enable the TWSI and slave */ -+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), TWSI_CONTROL_ENA | TWSI_CONTROL_ACK); -+ -+ /* set the TWSI slave address */ -+ if( pTwsiAddr->type == ADDR10_BIT )/* 10 Bit deviceAddress */ -+ { -+ /* writing the 2 most significant bits of the 10 bit address*/ -+ val = ((pTwsiAddr->address & TWSI_SLAVE_ADDR_10BIT_MASK) >> TWSI_SLAVE_ADDR_10BIT_OFFS ); -+ /* bits 7:3 must be 0x11110 */ -+ val |= TWSI_SLAVE_ADDR_10BIT_CONST; -+ /* set GCE bit */ -+ if(generalCallEnable) -+ val |= TWSI_SLAVE_ADDR_GCE_ENA; -+ /* write slave address */ -+ MV_REG_WRITE(TWSI_SLAVE_ADDR_REG(chanNum),val); -+ -+ /* writing the 8 least significant bits of the 10 bit address*/ -+ val = (pTwsiAddr->address << TWSI_EXTENDED_SLAVE_OFFS) & TWSI_EXTENDED_SLAVE_MASK; -+ MV_REG_WRITE(TWSI_EXTENDED_SLAVE_ADDR_REG(chanNum), val); -+ } -+ else /*7 bit address*/ -+ { -+ /* set the 7 Bits address */ -+ MV_REG_WRITE(TWSI_EXTENDED_SLAVE_ADDR_REG(chanNum),0x0); -+ val = (pTwsiAddr->address << TWSI_SLAVE_ADDR_7BIT_OFFS) & TWSI_SLAVE_ADDR_7BIT_MASK; -+ MV_REG_WRITE(TWSI_SLAVE_ADDR_REG(chanNum), val); -+ } -+ -+ /* unmask twsi int */ -+ val = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); -+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), val | TWSI_CONTROL_INT_ENA); -+ /* Add delay of 1ms */ -+ mvOsDelay(1); -+ -+ return actualFreq; -+} -+ -+ -+/******************************************************************************* -+* twsiStsGet - Get the TWSI status value. -+* -+* DESCRIPTION: -+* This routine returns the TWSI status value. -+* -+* INPUT: -+* chanNum - TWSI channel -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_U32 - the TWSI status. -+* -+*******************************************************************************/ -+static MV_U32 twsiStsGet(MV_U8 chanNum) -+{ -+ return MV_REG_READ(TWSI_STATUS_BAUDE_RATE_REG(chanNum)); -+ -+} -+ -+/******************************************************************************* -+* twsiReset - Reset the TWSI. -+* -+* DESCRIPTION: -+* Resets the TWSI logic and sets all TWSI registers to their reset values. -+* -+* INPUT: -+* chanNum - TWSI channel -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None -+* -+*******************************************************************************/ -+static MV_VOID twsiReset(MV_U8 chanNum) -+{ -+ /* Reset the TWSI logic */ -+ MV_REG_WRITE(TWSI_SOFT_RESET_REG(chanNum),0); -+ -+ /* wait for 2 mili sec */ -+ mvOsDelay(2); -+ -+ return; -+} -+ -+ -+ -+ -+/******************************* POLICY ****************************************/ -+ -+ -+ -+/******************************************************************************* -+* mvTwsiAddrSet - Set address on TWSI bus. -+* -+* DESCRIPTION: -+* This function Set address (7 or 10 Bit address) on the Twsi Bus. -+* -+* INPUT: -+* chanNum - TWSI channel -+* pTwsiAddr - twsi address. -+* command - read / write . -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK - if setting the address completed succesfully. -+* MV_FAIL otherwmise. -+* -+*******************************************************************************/ -+MV_STATUS mvTwsiAddrSet(MV_U8 chanNum, MV_TWSI_ADDR *pTwsiAddr, MV_TWSI_CMD command) -+{ -+ DB(mvOsPrintf("TWSI: mvTwsiAddr7BitSet addr %x , type %d, cmd is %s\n",pTwsiAddr->address,\ -+ pTwsiAddr->type, ((command==MV_TWSI_WRITE)?"Write":"Read") )); -+ /* 10 Bit address */ -+ if(pTwsiAddr->type == ADDR10_BIT) -+ { -+ return twsiAddr10BitSet(chanNum, pTwsiAddr->address,command); -+ } -+ /* 7 Bit address */ -+ else -+ { -+ return twsiAddr7BitSet(chanNum, pTwsiAddr->address,command); -+ } -+ -+} -+ -+/******************************************************************************* -+* twsiAddr10BitSet - Set 10 Bit address on TWSI bus. -+* -+* DESCRIPTION: -+* There are two address phases: -+* 1) Write '11110' to data register bits [7:3] and 10-bit address MSB -+* (bits [9:8]) to data register bits [2:1] plus a write(0) or read(1) bit -+* to the Data register. Then it clears interrupt flag which drive -+* the address on the TWSI bus. The function then waits for interrupt -+* flag to be active and status 0x18 (write) or 0x40 (read) to be set. -+* 2) write the rest of 10-bit address to data register and clears -+* interrupt flag which drive the address on the TWSI bus. The -+* function then waits for interrupt flag to be active and status -+* 0xD0 (write) or 0xE0 (read) to be set. -+* -+* INPUT: -+* chanNum - TWSI channel -+* deviceAddress - twsi address. -+* command - read / write . -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK - if setting the address completed succesfully. -+* MV_FAIL otherwmise. -+* -+*******************************************************************************/ -+static MV_STATUS twsiAddr10BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command) -+{ -+ MV_U32 val,timeout; -+ -+ /* writing the 2 most significant bits of the 10 bit address*/ -+ val = ((deviceAddress & TWSI_DATA_ADDR_10BIT_MASK) >> TWSI_DATA_ADDR_10BIT_OFFS ); -+ /* bits 7:3 must be 0x11110 */ -+ val |= TWSI_DATA_ADDR_10BIT_CONST; -+ /* set command */ -+ val |= command; -+ MV_REG_WRITE(TWSI_DATA_REG(chanNum), val); -+ /* WA add a delay */ -+ mvOsDelay(1); -+ -+ /* clear Int flag */ -+ twsiIntFlgClr(chanNum); -+ -+ /* wait for Int to be Set */ -+ timeout = 0; -+ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiAddr10BitSet ERROR - 1st addr (10Bit) Int TimeOut.\n")) -+ return MV_TIMEOUT; -+ -+ /* check the status */ -+ val = twsiStsGet(chanNum); -+ if(( (val != TWSI_AD_PLS_RD_BIT_TRA_ACK_REC) && (command == MV_TWSI_READ ) ) || -+ ( (val != TWSI_AD_PLS_WR_BIT_TRA_ACK_REC) && (command == MV_TWSI_WRITE) )) -+ { -+ mvOsPrintf("TWSI: twsiAddr10BitSet ERROR - status %x 1st addr (10 Bit) in %s mode.\n"\ -+ ,val, ((command==MV_TWSI_WRITE)?"Write":"Read") ); -+ return MV_FAIL; -+ } -+ -+ /* set 8 LSB of the address */ -+ val = (deviceAddress << TWSI_DATA_ADDR_7BIT_OFFS) & TWSI_DATA_ADDR_7BIT_MASK; -+ MV_REG_WRITE(TWSI_DATA_REG(chanNum), val); -+ -+ /* clear Int flag */ -+ twsiIntFlgClr(chanNum); -+ -+ /* wait for Int to be Set */ -+ timeout = 0; -+ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiAddr10BitSet ERROR - 2nd (10 Bit) Int TimOut.\n")) -+ return MV_TIMEOUT; -+ -+ /* check the status */ -+ val = twsiStsGet(chanNum); -+ if(( (val != TWSI_SEC_AD_PLS_RD_BIT_TRA_ACK_REC) && (command == MV_TWSI_READ ) ) || -+ ( (val != TWSI_SEC_AD_PLS_WR_BIT_TRA_ACK_REC) && (command == MV_TWSI_WRITE) )) -+ { -+ mvOsPrintf("TWSI: twsiAddr10BitSet ERROR - status %x 2nd addr(10 Bit) in %s mode.\n"\ -+ ,val, ((command==MV_TWSI_WRITE)?"Write":"Read") ); -+ return MV_FAIL; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* twsiAddr7BitSet - Set 7 Bit address on TWSI bus. -+* -+* DESCRIPTION: -+* This function writes 7 bit address plus a write or read bit to the -+* Data register. Then it clears interrupt flag which drive the address on -+* the TWSI bus. The function then waits for interrupt flag to be active -+* and status 0x18 (write) or 0x40 (read) to be set. -+* -+* INPUT: -+* chanNum - TWSI channel -+* deviceAddress - twsi address. -+* command - read / write . -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK - if setting the address completed succesfully. -+* MV_FAIL otherwmise. -+* -+*******************************************************************************/ -+static MV_STATUS twsiAddr7BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command) -+{ -+ MV_U32 val,timeout; -+ -+ /* set the address */ -+ val = (deviceAddress << TWSI_DATA_ADDR_7BIT_OFFS) & TWSI_DATA_ADDR_7BIT_MASK; -+ /* set command */ -+ val |= command; -+ MV_REG_WRITE(TWSI_DATA_REG(chanNum), val); -+ /* WA add a delay */ -+ mvOsDelay(1); -+ -+ /* clear Int flag */ -+ twsiIntFlgClr(chanNum); -+ -+ /* wait for Int to be Set */ -+ timeout = 0; -+ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiAddr7BitSet ERROR - Addr (7 Bit) int TimeOut.\n")) -+ return MV_TIMEOUT; -+ -+ /* check the status */ -+ val = twsiStsGet(chanNum); -+ if(( (val != TWSI_AD_PLS_RD_BIT_TRA_ACK_REC) && (command == MV_TWSI_READ ) ) || -+ ( (val != TWSI_AD_PLS_WR_BIT_TRA_ACK_REC) && (command == MV_TWSI_WRITE) )) -+ { -+ /* only in debug, since in boot we try to read the SPD of both DRAM, and we don't -+ want error messeges in case DIMM doesn't exist. */ -+ DB(mvOsPrintf("TWSI: twsiAddr7BitSet ERROR - status %x addr (7 Bit) in %s mode.\n"\ -+ ,val,((command==MV_TWSI_WRITE)?"Write":"Read") )); -+ return MV_FAIL; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* twsiDataWrite - Trnasmit a data block over TWSI bus. -+* -+* DESCRIPTION: -+* This function writes a given data block to TWSI bus in 8 bit granularity. -+* first The function waits for interrupt flag to be active then -+* For each 8-bit data: -+* The function writes data to data register. It then clears -+* interrupt flag which drives the data on the TWSI bus. -+* The function then waits for interrupt flag to be active and status -+* 0x28 to be set. -+* -+* -+* INPUT: -+* chanNum - TWSI channel -+* pBlock - Data block. -+* blockSize - number of chars in pBlock. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK - if transmiting the block completed succesfully, -+* MV_BAD_PARAM - if pBlock is NULL, -+* MV_FAIL otherwmise. -+* -+*******************************************************************************/ -+static MV_STATUS twsiDataTransmit(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize) -+{ -+ MV_U32 timeout, temp, blockSizeWr = blockSize; -+ -+ if(NULL == pBlock) -+ return MV_BAD_PARAM; -+ -+ /* wait for Int to be Set */ -+ timeout = 0; -+ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataTransmit ERROR - Read Data Int TimeOut.\n")) -+ return MV_TIMEOUT; -+ -+ while(blockSizeWr) -+ { -+ /* write the data*/ -+ MV_REG_WRITE(TWSI_DATA_REG(chanNum),(MV_U32)*pBlock); -+ DB(mvOsPrintf("TWSI: twsiDataTransmit place = %d write %x \n",\ -+ blockSize - blockSizeWr, *pBlock)); -+ pBlock++; -+ blockSizeWr--; -+ -+ twsiIntFlgClr(chanNum); -+ -+ /* wait for Int to be Set */ -+ timeout = 0; -+ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataTransmit ERROR - Read Data Int TimeOut.\n")) -+ return MV_TIMEOUT; -+ -+ /* check the status */ -+ temp = twsiStsGet(chanNum); -+ if(temp != TWSI_M_TRAN_DATA_BYTE_ACK_REC) -+ { -+ mvOsPrintf("TWSI: twsiDataTransmit ERROR - status %x in write trans\n",temp); -+ return MV_FAIL; -+ } -+ -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* twsiDataReceive - Receive data block from TWSI bus. -+* -+* DESCRIPTION: -+* This function receive data block from TWSI bus in 8bit granularity -+* into pBlock buffer. -+* first The function waits for interrupt flag to be active then -+* For each 8-bit data: -+* It clears the interrupt flag which allows the next data to be -+* received from TWSI bus. -+* The function waits for interrupt flag to be active, -+* and status reg is 0x50. -+* Then the function reads data from data register, and copies it to -+* the given buffer. -+* -+* INPUT: -+* chanNum - TWSI channel -+* blockSize - number of bytes to read. -+* -+* OUTPUT: -+* pBlock - Data block. -+* -+* RETURN: -+* MV_OK - if receive transaction completed succesfully, -+* MV_BAD_PARAM - if pBlock is NULL, -+* MV_FAIL otherwmise. -+* -+*******************************************************************************/ -+static MV_STATUS twsiDataReceive(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize) -+{ -+ MV_U32 timeout, temp, blockSizeRd = blockSize; -+ if(NULL == pBlock) -+ return MV_BAD_PARAM; -+ -+ /* wait for Int to be Set */ -+ timeout = 0; -+ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataReceive ERROR - Read Data int Time out .\n")) -+ return MV_TIMEOUT; -+ -+ while(blockSizeRd) -+ { -+ if(blockSizeRd == 1) -+ { -+ /* clear ack and Int flag */ -+ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); -+ temp &= ~(TWSI_CONTROL_ACK); -+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp); -+ } -+ twsiIntFlgClr(chanNum); -+ /* wait for Int to be Set */ -+ timeout = 0; -+ while( (!twsiMainIntGet(chanNum)) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataReceive ERROR - Read Data Int Time out .\n")) -+ return MV_TIMEOUT; -+ -+ /* check the status */ -+ temp = twsiStsGet(chanNum); -+ if((temp != TWSI_M_REC_RD_DATA_ACK_TRA) && (blockSizeRd !=1)) -+ { -+ mvOsPrintf("TWSI: twsiDataReceive ERROR - status %x in read trans \n",temp); -+ return MV_FAIL; -+ } -+ else if((temp != TWSI_M_REC_RD_DATA_ACK_NOT_TRA) && (blockSizeRd ==1)) -+ { -+ mvOsPrintf("TWSI: twsiDataReceive ERROR - status %x in Rd Terminate\n",temp); -+ return MV_FAIL; -+ } -+ -+ /* read the data*/ -+ *pBlock = (MV_U8)MV_REG_READ(TWSI_DATA_REG(chanNum)); -+ DB(mvOsPrintf("TWSI: twsiDataReceive place %d read %x \n",\ -+ blockSize - blockSizeRd,*pBlock)); -+ pBlock++; -+ blockSizeRd--; -+ } -+ -+ return MV_OK; -+} -+ -+ -+ -+/******************************************************************************* -+* twsiTargetOffsSet - Set TWST target offset on TWSI bus. -+* -+* DESCRIPTION: -+* The function support TWSI targets that have inside address space (for -+* example EEPROMs). The function: -+* 1) Convert the given offset into pBlock and size. -+* in case the offset should be set to a TWSI slave which support -+* more then 256 bytes offset, the offset setting will be done -+* in 2 transactions. -+* 2) Use twsiDataTransmit to place those on the bus. -+* -+* INPUT: -+* chanNum - TWSI channel -+* offset - offset to be set on the EEPROM device. -+* moreThen256 - whether the EEPROM device support more then 256 byte offset. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK - if setting the offset completed succesfully. -+* MV_FAIL otherwmise. -+* -+*******************************************************************************/ -+static MV_STATUS twsiTargetOffsSet(MV_U8 chanNum, MV_U32 offset, MV_BOOL moreThen256) -+{ -+ MV_U8 offBlock[2]; -+ MV_U32 offSize; -+ -+ if(moreThen256 == MV_TRUE) -+ { -+ offBlock[0] = (offset >> 8) & 0xff; -+ offBlock[1] = offset & 0xff; -+ offSize = 2; -+ } -+ else -+ { -+ offBlock[0] = offset & 0xff; -+ offSize = 1; -+ } -+ DB(mvOsPrintf("TWSI: twsiTargetOffsSet offSize = %x addr1 = %x addr2 = %x\n",\ -+ offSize,offBlock[0],offBlock[1])); -+ return twsiDataTransmit(chanNum, offBlock, offSize); -+ -+} -+ -+/******************************************************************************* -+* mvTwsiRead - Read data block from a TWSI Slave. -+* -+* DESCRIPTION: -+* The function calls the following functions: -+* -) mvTwsiStartBitSet(); -+* if(EEPROM device) -+* -) mvTwsiAddrSet(w); -+* -) twsiTargetOffsSet(); -+* -) mvTwsiStartBitSet(); -+* -) mvTwsiAddrSet(r); -+* -) twsiDataReceive(); -+* -) mvTwsiStopBitSet(); -+* -+* INPUT: -+* chanNum - TWSI channel -+* pTwsiSlave - Twsi Slave structure. -+* blockSize - number of bytes to read. -+* -+* OUTPUT: -+* pBlock - Data block. -+* -+* RETURN: -+* MV_OK - if EEPROM read transaction completed succesfully, -+* MV_BAD_PARAM - if pBlock is NULL, -+* MV_FAIL otherwmise. -+* -+*******************************************************************************/ -+MV_STATUS mvTwsiRead(MV_U8 chanNum, MV_TWSI_SLAVE *pTwsiSlave, MV_U8 *pBlock, MV_U32 blockSize) -+{ -+ if((NULL == pBlock) || (NULL == pTwsiSlave)) -+ return MV_BAD_PARAM; -+ if(MV_OK != mvTwsiStartBitSet(chanNum)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ -+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiStartBitSet\n")); -+ -+ /* in case offset exsist (i.e. eeprom ) */ -+ if(MV_TRUE == pTwsiSlave->validOffset) -+ { -+ if(MV_OK != mvTwsiAddrSet(chanNum, &(pTwsiSlave->slaveAddr), MV_TWSI_WRITE)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiAddrSet\n")); -+ if(MV_OK != twsiTargetOffsSet(chanNum, pTwsiSlave->offset, pTwsiSlave->moreThen256)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after twsiTargetOffsSet\n")); -+ if(MV_OK != mvTwsiStartBitSet(chanNum)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiStartBitSet\n")); -+ } -+ if(MV_OK != mvTwsiAddrSet(chanNum, &(pTwsiSlave->slaveAddr), MV_TWSI_READ)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiAddrSet\n")); -+ if(MV_OK != twsiDataReceive(chanNum, pBlock, blockSize)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after twsiDataReceive\n")); -+ -+ if(MV_OK != mvTwsiStopBitSet(chanNum)) -+ { -+ return MV_FAIL; -+ } -+ -+ twsiAckBitSet(chanNum); -+ -+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiStopBitSet\n")); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvTwsiWrite - Write data block to a TWSI Slave. -+* -+* DESCRIPTION: -+* The function calls the following functions: -+* -) mvTwsiStartBitSet(); -+* -) mvTwsiAddrSet(); -+* -)if(EEPROM device) -+* -) twsiTargetOffsSet(); -+* -) twsiDataTransmit(); -+* -) mvTwsiStopBitSet(); -+* -+* INPUT: -+* chanNum - TWSI channel -+* eepromAddress - eeprom address. -+* blockSize - number of bytes to write. -+* pBlock - Data block. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* MV_OK - if EEPROM read transaction completed succesfully. -+* MV_BAD_PARAM - if pBlock is NULL, -+* MV_FAIL otherwmise. -+* -+* NOTE: Part of the EEPROM, required that the offset will be aligned to the -+* max write burst supported. -+*******************************************************************************/ -+MV_STATUS mvTwsiWrite(MV_U8 chanNum, MV_TWSI_SLAVE *pTwsiSlave, MV_U8 *pBlock, MV_U32 blockSize) -+{ -+ if((NULL == pBlock) || (NULL == pTwsiSlave)) -+ return MV_BAD_PARAM; -+ -+ if(MV_OK != mvTwsiStartBitSet(chanNum)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ -+ DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after mvTwsiStartBitSet\n")); -+ if(MV_OK != mvTwsiAddrSet(chanNum, &(pTwsiSlave->slaveAddr), MV_TWSI_WRITE)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI :mvTwsiEepromWrite after mvTwsiAddrSet\n")); -+ -+ /* in case offset exsist (i.e. eeprom ) */ -+ if(MV_TRUE == pTwsiSlave->validOffset) -+ { -+ if(MV_OK != twsiTargetOffsSet(chanNum, pTwsiSlave->offset, pTwsiSlave->moreThen256)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after twsiTargetOffsSet\n")); -+ } -+ if(MV_OK != twsiDataTransmit(chanNum, pBlock, blockSize)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after twsiDataTransmit\n")); -+ if(MV_OK != mvTwsiStopBitSet(chanNum)) -+ { -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after mvTwsiStopBitSet\n")); -+ -+ return MV_OK; -+} -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.h 2010-11-09 20:28:12.231824496 +0100 -@@ -0,0 +1,121 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#ifndef __INCmvTwsiH -+#define __INCmvTwsiH -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* need to update this includes */ -+#include "twsi/mvTwsiSpec.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+ -+ -+/* The TWSI interface supports both 7-bit and 10-bit addressing. */ -+/* This enumerator describes addressing type. */ -+typedef enum _mvTwsiAddrType -+{ -+ ADDR7_BIT, /* 7 bit address */ -+ ADDR10_BIT /* 10 bit address */ -+}MV_TWSI_ADDR_TYPE; -+ -+/* This structure describes TWSI address. */ -+typedef struct _mvTwsiAddr -+{ -+ MV_U32 address; /* address */ -+ MV_TWSI_ADDR_TYPE type; /* Address type */ -+}MV_TWSI_ADDR; -+ -+/* This structure describes a TWSI slave. */ -+typedef struct _mvTwsiSlave -+{ -+ MV_TWSI_ADDR slaveAddr; -+ MV_BOOL validOffset; /* whether the slave has offset (i.e. Eeprom etc.) */ -+ MV_U32 offset; /* offset in the slave. */ -+ MV_BOOL moreThen256; /* whether the ofset is bigger then 256 */ -+}MV_TWSI_SLAVE; -+ -+/* This enumerator describes TWSI protocol commands. */ -+typedef enum _mvTwsiCmd -+{ -+ MV_TWSI_WRITE, /* TWSI write command - 0 according to spec */ -+ MV_TWSI_READ /* TWSI read command - 1 according to spec */ -+}MV_TWSI_CMD; -+ -+MV_STATUS mvTwsiStartBitSet(MV_U8 chanNum); -+MV_STATUS mvTwsiStopBitSet(MV_U8 chanNum); -+MV_STATUS mvTwsiAddrSet(MV_U8 chanNum, MV_TWSI_ADDR *twsiAddr, MV_TWSI_CMD command); -+ -+MV_U32 mvTwsiInit(MV_U8 chanNum, MV_KHZ frequancy, MV_U32 Tclk, MV_TWSI_ADDR *twsiAddr, MV_BOOL generalCallEnable); -+MV_STATUS mvTwsiRead (MV_U8 chanNum, MV_TWSI_SLAVE *twsiSlave, MV_U8 *pBlock, MV_U32 blockSize); -+MV_STATUS mvTwsiWrite(MV_U8 chanNum, MV_TWSI_SLAVE *twsiSlave, MV_U8 *pBlock, MV_U32 blockSize); -+ -+ -+#ifdef __cplusplus -+} -+#endif /* __cplusplus */ -+ -+#endif /* __INCmvTwsiH */ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiSpec.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiSpec.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiSpec.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiSpec.h 2010-11-09 20:28:12.272374071 +0100 -@@ -0,0 +1,160 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+/****************************************/ -+/* TWSI Registers */ -+/****************************************/ -+#ifndef __INCmvTwsiSpech -+#define __INCmvTwsiSpech -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* defines */ -+#define TWSI_SLAVE_ADDR_REG(chanNum) (TWSI_SLAVE_BASE(chanNum)+ 0x00) -+ -+#define TWSI_SLAVE_ADDR_GCE_ENA BIT0 -+#define TWSI_SLAVE_ADDR_7BIT_OFFS 0x1 -+#define TWSI_SLAVE_ADDR_7BIT_MASK (0xFF << TWSI_SLAVE_ADDR_7BIT_OFFS) -+#define TWSI_SLAVE_ADDR_10BIT_OFFS 0x7 -+#define TWSI_SLAVE_ADDR_10BIT_MASK 0x300 -+#define TWSI_SLAVE_ADDR_10BIT_CONST 0xF0 -+ -+ -+#define TWSI_EXTENDED_SLAVE_ADDR_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x10) -+#define TWSI_EXTENDED_SLAVE_OFFS 0 -+#define TWSI_EXTENDED_SLAVE_MASK (0xFF << TWSI_EXTENDED_SLAVE_OFFS) -+ -+ -+#define TWSI_DATA_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x04) -+#define TWSI_DATA_COMMAND_OFFS 0x0 -+#define TWSI_DATA_COMMAND_MASK (0x1 << TWSI_DATA_COMMAND_OFFS) -+#define TWSI_DATA_COMMAND_WR (0x1 << TWSI_DATA_COMMAND_OFFS) -+#define TWSI_DATA_COMMAND_RD (0x0 << TWSI_DATA_COMMAND_OFFS) -+#define TWSI_DATA_ADDR_7BIT_OFFS 0x1 -+#define TWSI_DATA_ADDR_7BIT_MASK (0xFF << TWSI_DATA_ADDR_7BIT_OFFS) -+#define TWSI_DATA_ADDR_10BIT_OFFS 0x7 -+#define TWSI_DATA_ADDR_10BIT_MASK 0x300 -+#define TWSI_DATA_ADDR_10BIT_CONST 0xF0 -+ -+ -+#define TWSI_CONTROL_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x08) -+#define TWSI_CONTROL_ACK BIT2 -+#define TWSI_CONTROL_INT_FLAG_SET BIT3 -+#define TWSI_CONTROL_STOP_BIT BIT4 -+#define TWSI_CONTROL_START_BIT BIT5 -+#define TWSI_CONTROL_ENA BIT6 -+#define TWSI_CONTROL_INT_ENA BIT7 -+ -+ -+#define TWSI_STATUS_BAUDE_RATE_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x0c) -+#define TWSI_BAUD_RATE_N_OFFS 0 -+#define TWSI_BAUD_RATE_N_MASK (0x7 << TWSI_BAUD_RATE_N_OFFS) -+#define TWSI_BAUD_RATE_M_OFFS 3 -+#define TWSI_BAUD_RATE_M_MASK (0xF << TWSI_BAUD_RATE_M_OFFS) -+ -+#define TWSI_SOFT_RESET_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x1c) -+ -+/* defines */ -+#define TWSI_TIMEOUT_VALUE 0x500 -+ -+/* TWSI status codes */ -+#define TWSI_BUS_ERROR 0x00 -+#define TWSI_START_CON_TRA 0x08 -+#define TWSI_REPEATED_START_CON_TRA 0x10 -+#define TWSI_AD_PLS_WR_BIT_TRA_ACK_REC 0x18 -+#define TWSI_AD_PLS_WR_BIT_TRA_ACK_NOT_REC 0x20 -+#define TWSI_M_TRAN_DATA_BYTE_ACK_REC 0x28 -+#define TWSI_M_TRAN_DATA_BYTE_ACK_NOT_REC 0x30 -+#define TWSI_M_LOST_ARB_DUR_AD_OR_DATA_TRA 0x38 -+#define TWSI_AD_PLS_RD_BIT_TRA_ACK_REC 0x40 -+#define TWSI_AD_PLS_RD_BIT_TRA_ACK_NOT_REC 0x48 -+#define TWSI_M_REC_RD_DATA_ACK_TRA 0x50 -+#define TWSI_M_REC_RD_DATA_ACK_NOT_TRA 0x58 -+#define TWSI_SLA_REC_AD_PLS_WR_BIT_ACK_TRA 0x60 -+#define TWSI_M_LOST_ARB_DUR_AD_TRA_AD_IS_TRGT_TO_SLA_ACK_TRA_W 0x68 -+#define TWSI_GNL_CALL_REC_ACK_TRA 0x70 -+#define TWSI_M_LOST_ARB_DUR_AD_TRA_GNL_CALL_AD_REC_ACK_TRA 0x78 -+#define TWSI_SLA_REC_WR_DATA_AF_REC_SLA_AD_ACK_TRAN 0x80 -+#define TWSI_SLA_REC_WR_DATA_AF_REC_SLA_AD_ACK_NOT_TRAN 0x88 -+#define TWSI_SLA_REC_WR_DATA_AF_REC_GNL_CALL_ACK_TRAN 0x90 -+#define TWSI_SLA_REC_WR_DATA_AF_REC_GNL_CALL_ACK_NOT_TRAN 0x98 -+#define TWSI_SLA_REC_STOP_OR_REPEATED_STRT_CON 0xA0 -+#define TWSI_SLA_REC_AD_PLS_RD_BIT_ACK_TRA 0xA8 -+#define TWSI_M_LOST_ARB_DUR_AD_TRA_AD_IS_TRGT_TO_SLA_ACK_TRA_R 0xB0 -+#define TWSI_SLA_TRA_RD_DATA_ACK_REC 0xB8 -+#define TWSI_SLA_TRA_RD_DATA_ACK_NOT_REC 0xC0 -+#define TWSI_SLA_TRA_LAST_RD_DATA_ACK_REC 0xC8 -+#define TWSI_SEC_AD_PLS_WR_BIT_TRA_ACK_REC 0xD0 -+#define TWSI_SEC_AD_PLS_WR_BIT_TRA_ACK_NOT_REC 0xD8 -+#define TWSI_SEC_AD_PLS_RD_BIT_TRA_ACK_REC 0xE0 -+#define TWSI_SEC_AD_PLS_RD_BIT_TRA_ACK_NOT_REC 0xE8 -+#define TWSI_NO_REL_STS_INT_FLAG_IS_KEPT_0 0xF8 -+ -+ -+#ifdef __cplusplus -+} -+#endif /* __cplusplus */ -+ -+#endif /* __INCmvTwsiSpech */ -diff -Nur linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mvSysHwConfig.h linux-2.6.36/crypto/ocf/kirkwood/mvHal/mvSysHwConfig.h ---- linux-2.6.36.orig/crypto/ocf/kirkwood/mvHal/mvSysHwConfig.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/kirkwood/mvHal/mvSysHwConfig.h 2010-11-09 20:28:12.322486315 +0100 -@@ -0,0 +1,375 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+ -+*******************************************************************************/ -+/******************************************************************************* -+* mvSysHwCfg.h - Marvell system HW configuration file -+* -+* DESCRIPTION: -+* None. -+* -+* DEPENDENCIES: -+* None. -+* -+*******************************************************************************/ -+ -+#ifndef __INCmvSysHwConfigh -+#define __INCmvSysHwConfigh -+ -+#include "../../../../include/linux/autoconf.h" -+ -+#define CONFIG_MARVELL 1 -+ -+/* includes */ -+#define _1K 0x00000400 -+#define _4K 0x00001000 -+#define _8K 0x00002000 -+#define _16K 0x00004000 -+#define _32K 0x00008000 -+#define _64K 0x00010000 -+#define _128K 0x00020000 -+#define _256K 0x00040000 -+#define _512K 0x00080000 -+ -+#define _1M 0x00100000 -+#define _2M 0x00200000 -+#define _4M 0x00400000 -+#define _8M 0x00800000 -+#define _16M 0x01000000 -+#define _32M 0x02000000 -+#define _64M 0x04000000 -+#define _128M 0x08000000 -+#define _256M 0x10000000 -+#define _512M 0x20000000 -+ -+#define _1G 0x40000000 -+#define _2G 0x80000000 -+ -+/****************************************/ -+/* Soc supporeted Units definitions */ -+/****************************************/ -+ -+#ifdef CONFIG_MV_INCLUDE_PEX -+#define MV_INCLUDE_PEX -+#endif -+#ifdef CONFIG_MV_INCLUDE_TWSI -+#define MV_INCLUDE_TWSI -+#endif -+#ifdef CONFIG_MV_INCLUDE_CESA -+#define MV_INCLUDE_CESA -+#endif -+#ifdef CONFIG_MV_INCLUDE_GIG_ETH -+#define MV_INCLUDE_GIG_ETH -+#endif -+#ifdef CONFIG_MV_INCLUDE_INTEG_SATA -+#define MV_INCLUDE_INTEG_SATA -+#define MV_INCLUDE_SATA -+#endif -+#ifdef CONFIG_MV_INCLUDE_USB -+#define MV_INCLUDE_USB -+#define MV_USB_VOLTAGE_FIX -+#endif -+#ifdef CONFIG_MV_INCLUDE_NAND -+#define MV_INCLUDE_NAND -+#endif -+#ifdef CONFIG_MV_INCLUDE_TDM -+#define MV_INCLUDE_TDM -+#endif -+#ifdef CONFIG_MV_INCLUDE_XOR -+#define MV_INCLUDE_XOR -+#endif -+#ifdef CONFIG_MV_INCLUDE_TWSI -+#define MV_INCLUDE_TWSI -+#endif -+#ifdef CONFIG_MV_INCLUDE_UART -+#define MV_INCLUDE_UART -+#endif -+#ifdef CONFIG_MV_INCLUDE_SPI -+#define MV_INCLUDE_SPI -+#endif -+#ifdef CONFIG_MV_INCLUDE_SFLASH_MTD -+#define MV_INCLUDE_SFLASH_MTD -+#endif -+#ifdef CONFIG_MV_INCLUDE_AUDIO -+#define MV_INCLUDE_AUDIO -+#endif -+#ifdef CONFIG_MV_INCLUDE_TS -+#define MV_INCLUDE_TS -+#endif -+#ifdef CONFIG_MV_INCLUDE_SDIO -+#define MV_INCLUDE_SDIO -+#endif -+ -+ -+/* NAND flash stuff */ -+#ifdef CONFIG_MV_NAND_BOOT -+#define MV_NAND_BOOT -+#endif -+#ifdef CONFIG_MV_NAND -+#define MV_NAND -+#endif -+ -+/* SPI flash stuff */ -+#ifdef CONFIG_MV_SPI_BOOT -+#define MV_SPI_BOOT -+#endif -+ -+ -+/****************************************************************/ -+/************* General configuration ********************/ -+/****************************************************************/ -+ -+/* Enable Clock Power Control */ -+#define MV_INCLUDE_CLK_PWR_CNTRL -+ -+/* Disable the DEVICE BAR in the PEX */ -+#define MV_DISABLE_PEX_DEVICE_BAR -+ -+/* Allow the usage of early printings during initialization */ -+#define MV_INCLUDE_EARLY_PRINTK -+ -+/****************************************************************/ -+/************* NFP configuration ********************************/ -+/****************************************************************/ -+#define MV_NFP_SEC_Q_SIZE 64 -+#define MV_NFP_SEC_REQ_Q_SIZE 1000 -+ -+ -+ -+/****************************************************************/ -+/************* CESA configuration ********************/ -+/****************************************************************/ -+ -+#ifdef MV_INCLUDE_CESA -+ -+#define MV_CESA_MAX_CHAN 4 -+ -+/* Use 2K of SRAM */ -+#define MV_CESA_MAX_BUF_SIZE 1600 -+ -+#endif /* MV_INCLUDE_CESA */ -+ -+#if defined(CONFIG_MV_INCLUDE_GIG_ETH) -+ -+#ifdef CONFIG_MV_NFP_STATS -+#define MV_FP_STATISTICS -+#else -+#undef MV_FP_STATISTICS -+#endif -+/* Default configuration for SKB_REUSE: 0 - Disabled, 1 - Enabled */ -+#define MV_ETH_SKB_REUSE_DEFAULT 1 -+/* Default configuration for TX_EN workaround: 0 - Disabled, 1 - Enabled */ -+#define MV_ETH_TX_EN_DEFAULT 0 -+ -+/* un-comment if you want to perform tx_done from within the poll function */ -+/* #define ETH_TX_DONE_ISR */ -+ -+/* put descriptors in uncached memory */ -+/* #define ETH_DESCR_UNCACHED */ -+ -+/* Descriptors location: DRAM/internal-SRAM */ -+#define ETH_DESCR_IN_SDRAM -+#undef ETH_DESCR_IN_SRAM /* No integrated SRAM in 88Fxx81 devices */ -+ -+#if defined(ETH_DESCR_IN_SRAM) -+#if defined(ETH_DESCR_UNCACHED) -+ #define ETH_DESCR_CONFIG_STR "Uncached descriptors in integrated SRAM" -+#else -+ #define ETH_DESCR_CONFIG_STR "Cached descriptors in integrated SRAM" -+#endif -+#elif defined(ETH_DESCR_IN_SDRAM) -+#if defined(ETH_DESCR_UNCACHED) -+ #define ETH_DESCR_CONFIG_STR "Uncached descriptors in DRAM" -+#else -+ #define ETH_DESCR_CONFIG_STR "Cached descriptors in DRAM" -+#endif -+#else -+ #error "Ethernet descriptors location undefined" -+#endif /* ETH_DESCR_IN_SRAM or ETH_DESCR_IN_SDRAM*/ -+ -+/* SW Sync-Barrier: not relevant for 88fxx81*/ -+/* Reasnable to define this macro when descriptors in SRAM and buffers in DRAM */ -+/* In RX the CPU theoretically might see himself as the descriptor owner, */ -+/* although the buffer hadn't been written to DRAM yet. Performance cost. */ -+/* #define INCLUDE_SYNC_BARR */ -+ -+/* Buffers cache coherency method (buffers in DRAM) */ -+#ifndef MV_CACHE_COHER_SW -+/* Taken from mvCommon.h */ -+/* Memory uncached, HW or SW cache coherency is not needed */ -+#define MV_UNCACHED 0 -+/* Memory cached, HW cache coherency supported in WriteThrough mode */ -+#define MV_CACHE_COHER_HW_WT 1 -+/* Memory cached, HW cache coherency supported in WriteBack mode */ -+#define MV_CACHE_COHER_HW_WB 2 -+/* Memory cached, No HW cache coherency, Cache coherency must be in SW */ -+#define MV_CACHE_COHER_SW 3 -+ -+#endif -+ -+/* DRAM cache coherency configuration */ -+#define MV_CACHE_COHERENCY MV_CACHE_COHER_SW -+ -+ -+#define ETHER_DRAM_COHER MV_CACHE_COHER_SW /* No HW coherency in 88Fxx81 devices */ -+ -+#if (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WB) -+ #define ETH_SDRAM_CONFIG_STR "DRAM HW cache coherency (write-back)" -+#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WT) -+ #define ETH_SDRAM_CONFIG_STR "DRAM HW cache coherency (write-through)" -+#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) -+ #define ETH_SDRAM_CONFIG_STR "DRAM SW cache-coherency" -+#elif (ETHER_DRAM_COHER == MV_UNCACHED) -+# define ETH_SDRAM_CONFIG_STR "DRAM uncached" -+#else -+ #error "Ethernet-DRAM undefined" -+#endif /* ETHER_DRAM_COHER */ -+ -+ -+/****************************************************************/ -+/************* Ethernet driver configuration ********************/ -+/****************************************************************/ -+ -+/* port's default queueus */ -+#define ETH_DEF_TXQ 0 -+#define ETH_DEF_RXQ 0 -+ -+#define MV_ETH_RX_Q_NUM CONFIG_MV_ETH_RX_Q_NUM -+#define MV_ETH_TX_Q_NUM CONFIG_MV_ETH_TX_Q_NUM -+ -+/* interrupt coalescing setting */ -+#define ETH_TX_COAL 200 -+#define ETH_RX_COAL 200 -+ -+/* Checksum offloading */ -+#define TX_CSUM_OFFLOAD -+#define RX_CSUM_OFFLOAD -+ -+#endif /* CONFIG_MV_INCLUDE_GIG_ETH */ -+ -+/****************************************************************/ -+/*************** Telephony configuration ************************/ -+/****************************************************************/ -+#if defined(CONFIG_MV_TDM_LINEAR_MODE) -+ #define MV_TDM_LINEAR_MODE -+#elif defined(CONFIG_MV_TDM_ULAW_MODE) -+ #define MV_TDM_ULAW_MODE -+#endif -+ -+#if defined(CONFIG_MV_TDM_5CHANNELS) -+ #define MV_TDM_5CHANNELS -+#endif -+ -+#if defined(CONFIG_MV_TDM_USE_EXTERNAL_PCLK_SOURCE) -+ #define MV_TDM_USE_EXTERNAL_PCLK_SOURCE -+#endif -+ -+/* We use the following registers to store DRAM interface pre configuration */ -+/* auto-detection results */ -+/* IMPORTANT: We are using mask register for that purpose. Before writing */ -+/* to units mask register, make sure main maks register is set to disable */ -+/* all interrupts. */ -+#define DRAM_BUF_REG0 0x30810 /* sdram bank 0 size */ -+#define DRAM_BUF_REG1 0x30820 /* sdram config */ -+#define DRAM_BUF_REG2 0x30830 /* sdram mode */ -+#define DRAM_BUF_REG3 0x308c4 /* dunit control low */ -+#define DRAM_BUF_REG4 0x60a90 /* sdram address control */ -+#define DRAM_BUF_REG5 0x60a94 /* sdram timing control low */ -+#define DRAM_BUF_REG6 0x60a98 /* sdram timing control high */ -+#define DRAM_BUF_REG7 0x60a9c /* sdram ODT control low */ -+#define DRAM_BUF_REG8 0x60b90 /* sdram ODT control high */ -+#define DRAM_BUF_REG9 0x60b94 /* sdram Dunit ODT control */ -+#define DRAM_BUF_REG10 0x60b98 /* sdram Extended Mode */ -+#define DRAM_BUF_REG11 0x60b9c /* sdram Ddr2 Time Low Reg */ -+#define DRAM_BUF_REG12 0x60a00 /* sdram Ddr2 Time High Reg */ -+#define DRAM_BUF_REG13 0x60a04 /* dunit Ctrl High */ -+#define DRAM_BUF_REG14 0x60b00 /* sdram second DIMM exist */ -+ -+/* Following the pre-configuration registers default values restored after */ -+/* auto-detection is done */ -+#define DRAM_BUF_REG_DV 0 -+ -+/* System Mapping */ -+#define SDRAM_CS0_BASE 0x00000000 -+#define SDRAM_CS0_SIZE _256M -+ -+#define SDRAM_CS1_BASE 0x10000000 -+#define SDRAM_CS1_SIZE _256M -+ -+#define SDRAM_CS2_BASE 0x20000000 -+#define SDRAM_CS2_SIZE _256M -+ -+#define SDRAM_CS3_BASE 0x30000000 -+#define SDRAM_CS3_SIZE _256M -+ -+/* PEX */ -+#define PEX0_MEM_BASE 0xe8000000 -+#define PEX0_MEM_SIZE _128M -+ -+#define PEX0_IO_BASE 0xf2000000 -+#define PEX0_IO_SIZE _1M -+ -+/* Device Chip Selects */ -+#define NFLASH_CS_BASE 0xfa000000 -+#define NFLASH_CS_SIZE _2M -+ -+#define SPI_CS_BASE 0xf4000000 -+#define SPI_CS_SIZE _16M -+ -+#define CRYPT_ENG_BASE 0xf0000000 -+#define CRYPT_ENG_SIZE _2M -+ -+#define BOOTDEV_CS_BASE 0xff800000 -+#define BOOTDEV_CS_SIZE _8M -+ -+/* CS2 - BOOTROM */ -+#define DEVICE_CS2_BASE 0xff900000 -+#define DEVICE_CS2_SIZE _1M -+ -+/* PEX Work arround */ -+/* the target we will use for the workarround */ -+#define PEX_CONFIG_RW_WA_TARGET PEX0_MEM -+/*a flag that indicates if we are going to use the -+size and base of the target we using for the workarround -+window */ -+#define PEX_CONFIG_RW_WA_USE_ORIGINAL_WIN_VALUES 1 -+/* if the above flag is 0 then the following values -+will be used for the workarround window base and size, -+otherwise the following defines will be ignored */ -+#define PEX_CONFIG_RW_WA_BASE 0xF3000000 -+#define PEX_CONFIG_RW_WA_SIZE _16M -+ -+/* Internal registers: size is defined in Controllerenvironment */ -+#define INTER_REGS_BASE 0xFEE00000 -+ -+/* DRAM detection stuff */ -+#define MV_DRAM_AUTO_SIZE -+ -+/* Board clock detection */ -+#define TCLK_AUTO_DETECT /* Use Tclk auto detection */ -+#define SYSCLK_AUTO_DETECT /* Use SysClk auto detection */ -+#define PCLCK_AUTO_DETECT /* Use PClk auto detection */ -+#define L2CLK_AUTO_DETECT /* Use L2Clk auto detection */ -+ -+/* PEX-PCI\PCI-PCI Bridge*/ -+#define PCI0_IF_PTP 0 /* Bridge exist on pciIf0*/ -+ -+ -+ -+#endif /* __INCmvSysHwConfigh */ -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/Makefile linux-2.6.36/crypto/ocf/Makefile ---- linux-2.6.36.orig/crypto/ocf/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/Makefile 2010-11-09 20:28:12.342495369 +0100 -@@ -0,0 +1,124 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+OCF_OBJS = crypto.o criov.o -+ -+ifdef CONFIG_OCF_RANDOMHARVEST -+ OCF_OBJS += random.o -+endif -+ -+ifdef CONFIG_OCF_FIPS -+ OCF_OBJS += rndtest.o -+endif -+ -+# Add in autoconf.h to get #defines for CONFIG_xxx -+AUTOCONF_H=$(ROOTDIR)/modules/autoconf.h -+ifeq ($(AUTOCONF_H), $(wildcard $(AUTOCONF_H))) -+ EXTRA_CFLAGS += -include $(AUTOCONF_H) -+ export EXTRA_CFLAGS -+endif -+ -+ifndef obj -+ obj ?= . -+ _obj = subdir -+ mod-subdirs := safe hifn ixp4xx talitos ocfnull -+ export-objs += crypto.o criov.o random.o -+ list-multi += ocf.o -+ _slash := -+else -+ _obj = obj -+ _slash := / -+endif -+ -+EXTRA_CFLAGS += -I$(obj)/. -+ -+obj-$(CONFIG_OCF_OCF) += ocf.o -+obj-$(CONFIG_OCF_CRYPTODEV) += cryptodev.o -+obj-$(CONFIG_OCF_CRYPTOSOFT) += cryptosoft.o -+obj-$(CONFIG_OCF_BENCH) += ocf-bench.o -+ -+$(_obj)-$(CONFIG_OCF_SAFE) += safe$(_slash) -+$(_obj)-$(CONFIG_OCF_HIFN) += hifn$(_slash) -+$(_obj)-$(CONFIG_OCF_IXP4XX) += ixp4xx$(_slash) -+$(_obj)-$(CONFIG_OCF_TALITOS) += talitos$(_slash) -+$(_obj)-$(CONFIG_OCF_PASEMI) += pasemi$(_slash) -+$(_obj)-$(CONFIG_OCF_EP80579) += ep80579$(_slash) -+$(_obj)-$(CONFIG_OCF_CRYPTOCTEON) += cryptocteon$(_slash) -+$(_obj)-$(CONFIG_OCF_KIRKWOOD) += kirkwood$(_slash) -+$(_obj)-$(CONFIG_OCF_OCFNULL) += ocfnull$(_slash) -+$(_obj)-$(CONFIG_OCF_C7108) += c7108$(_slash) -+ -+ocf-objs := $(OCF_OBJS) -+ -+$(list-multi) dummy1: $(ocf-objs) -+ $(LD) -r -o $@ $(ocf-objs) -+ -+.PHONY: -+clean: -+ rm -f *.o *.ko .*.o.flags .*.ko.cmd .*.o.cmd .*.mod.o.cmd *.mod.c -+ rm -f */*.o */*.ko */.*.o.cmd */.*.ko.cmd */.*.mod.o.cmd */*.mod.c */.*.o.flags -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -+# -+# release gen targets -+# -+ -+.PHONY: patch -+patch: -+ REL=`date +%Y%m%d`; \ -+ patch=ocf-linux-$$REL.patch; \ -+ patch24=ocf-linux-24-$$REL.patch; \ -+ patch26=ocf-linux-26-$$REL.patch; \ -+ ( \ -+ find . -name Makefile; \ -+ find . -name Config.in; \ -+ find . -name Kconfig; \ -+ find . -name README; \ -+ find . -name '*.[ch]' | grep -v '.mod.c'; \ -+ ) | while read t; do \ -+ diff -Nau /dev/null $$t | sed 's?^+++ \./?+++ linux/crypto/ocf/?'; \ -+ done > $$patch; \ -+ cat patches/linux-2.4.35-ocf.patch $$patch > $$patch24; \ -+ cat patches/linux-2.6.33-ocf.patch $$patch > $$patch26 -+ -+.PHONY: tarball -+tarball: -+ REL=`date +%Y%m%d`; RELDIR=/tmp/ocf-linux-$$REL; \ -+ CURDIR=`pwd`; \ -+ rm -rf /tmp/ocf-linux-$$REL*; \ -+ mkdir -p $$RELDIR/tools; \ -+ cp README* $$RELDIR; \ -+ cp patches/openss*.patch $$RELDIR; \ -+ cp patches/crypto-tools.patch $$RELDIR; \ -+ cp tools/[!C]* $$RELDIR/tools; \ -+ cd ..; \ -+ tar cvf $$RELDIR/ocf-linux.tar \ -+ --exclude=CVS \ -+ --exclude=.* \ -+ --exclude=*.o \ -+ --exclude=*.ko \ -+ --exclude=*.mod.* \ -+ --exclude=README* \ -+ --exclude=ocf-*.patch \ -+ --exclude=ocf/patches/openss*.patch \ -+ --exclude=ocf/patches/crypto-tools.patch \ -+ --exclude=ocf/tools \ -+ ocf; \ -+ gzip -9 $$RELDIR/ocf-linux.tar; \ -+ cd /tmp; \ -+ tar cvf ocf-linux-$$REL.tar ocf-linux-$$REL; \ -+ gzip -9 ocf-linux-$$REL.tar; \ -+ cd $$CURDIR/../../user; \ -+ rm -rf /tmp/crypto-tools-$$REL*; \ -+ tar cvf /tmp/crypto-tools-$$REL.tar \ -+ --exclude=CVS \ -+ --exclude=.* \ -+ --exclude=*.o \ -+ --exclude=cryptotest \ -+ --exclude=cryptokeytest \ -+ crypto-tools; \ -+ gzip -9 /tmp/crypto-tools-$$REL.tar -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/ocf-bench.c linux-2.6.36/crypto/ocf/ocf-bench.c ---- linux-2.6.36.orig/crypto/ocf/ocf-bench.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/ocf-bench.c 2010-11-09 20:28:12.381251524 +0100 -@@ -0,0 +1,436 @@ -+/* -+ * A loadable module that benchmarks the OCF crypto speed from kernel space. -+ * -+ * Copyright (C) 2004-2010 David McCullough -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * ALTERNATIVELY, provided that this notice is retained in full, this product -+ * may be distributed under the terms of the GNU General Public License (GPL), -+ * in which case the provisions of the GPL apply INSTEAD OF those given above. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ */ -+ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#ifdef I_HAVE_AN_XSCALE_WITH_INTEL_SDK -+#define BENCH_IXP_ACCESS_LIB 1 -+#endif -+#ifdef BENCH_IXP_ACCESS_LIB -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#endif -+ -+/* -+ * support for access lib version 1.4 -+ */ -+#ifndef IX_MBUF_PRIV -+#define IX_MBUF_PRIV(x) ((x)->priv) -+#endif -+ -+/* -+ * the number of simultaneously active requests -+ */ -+static int request_q_len = 20; -+module_param(request_q_len, int, 0); -+MODULE_PARM_DESC(request_q_len, "Number of outstanding requests"); -+/* -+ * how many requests we want to have processed -+ */ -+static int request_num = 1024; -+module_param(request_num, int, 0); -+MODULE_PARM_DESC(request_num, "run for at least this many requests"); -+/* -+ * the size of each request -+ */ -+static int request_size = 1500; -+module_param(request_size, int, 0); -+MODULE_PARM_DESC(request_size, "size of each request"); -+ -+/* -+ * a structure for each request -+ */ -+typedef struct { -+ struct work_struct work; -+#ifdef BENCH_IXP_ACCESS_LIB -+ IX_MBUF mbuf; -+#endif -+ unsigned char *buffer; -+} request_t; -+ -+static request_t *requests; -+ -+static int outstanding; -+static int total; -+ -+/*************************************************************************/ -+/* -+ * OCF benchmark routines -+ */ -+ -+static uint64_t ocf_cryptoid; -+static int ocf_init(void); -+static int ocf_cb(struct cryptop *crp); -+static void ocf_request(void *arg); -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void ocf_request_wq(struct work_struct *work); -+#endif -+ -+static int -+ocf_init(void) -+{ -+ int error; -+ struct cryptoini crie, cria; -+ struct cryptodesc crda, crde; -+ -+ memset(&crie, 0, sizeof(crie)); -+ memset(&cria, 0, sizeof(cria)); -+ memset(&crde, 0, sizeof(crde)); -+ memset(&crda, 0, sizeof(crda)); -+ -+ cria.cri_alg = CRYPTO_SHA1_HMAC; -+ cria.cri_klen = 20 * 8; -+ cria.cri_key = "0123456789abcdefghij"; -+ -+ crie.cri_alg = CRYPTO_3DES_CBC; -+ crie.cri_klen = 24 * 8; -+ crie.cri_key = "0123456789abcdefghijklmn"; -+ -+ crie.cri_next = &cria; -+ -+ error = crypto_newsession(&ocf_cryptoid, &crie, 0); -+ if (error) { -+ printk("crypto_newsession failed %d\n", error); -+ return -1; -+ } -+ return 0; -+} -+ -+static int -+ocf_cb(struct cryptop *crp) -+{ -+ request_t *r = (request_t *) crp->crp_opaque; -+ -+ if (crp->crp_etype) -+ printk("Error in OCF processing: %d\n", crp->crp_etype); -+ total++; -+ crypto_freereq(crp); -+ crp = NULL; -+ -+ if (total > request_num) { -+ outstanding--; -+ return 0; -+ } -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ INIT_WORK(&r->work, ocf_request_wq); -+#else -+ INIT_WORK(&r->work, ocf_request, r); -+#endif -+ schedule_work(&r->work); -+ return 0; -+} -+ -+ -+static void -+ocf_request(void *arg) -+{ -+ request_t *r = arg; -+ struct cryptop *crp = crypto_getreq(2); -+ struct cryptodesc *crde, *crda; -+ -+ if (!crp) { -+ outstanding--; -+ return; -+ } -+ -+ crde = crp->crp_desc; -+ crda = crde->crd_next; -+ -+ crda->crd_skip = 0; -+ crda->crd_flags = 0; -+ crda->crd_len = request_size; -+ crda->crd_inject = request_size; -+ crda->crd_alg = CRYPTO_SHA1_HMAC; -+ crda->crd_key = "0123456789abcdefghij"; -+ crda->crd_klen = 20 * 8; -+ -+ crde->crd_skip = 0; -+ crde->crd_flags = CRD_F_IV_EXPLICIT | CRD_F_ENCRYPT; -+ crde->crd_len = request_size; -+ crde->crd_inject = request_size; -+ crde->crd_alg = CRYPTO_3DES_CBC; -+ crde->crd_key = "0123456789abcdefghijklmn"; -+ crde->crd_klen = 24 * 8; -+ -+ crp->crp_ilen = request_size + 64; -+ crp->crp_flags = CRYPTO_F_CBIMM; -+ crp->crp_buf = (caddr_t) r->buffer; -+ crp->crp_callback = ocf_cb; -+ crp->crp_sid = ocf_cryptoid; -+ crp->crp_opaque = (caddr_t) r; -+ crypto_dispatch(crp); -+} -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void -+ocf_request_wq(struct work_struct *work) -+{ -+ request_t *r = container_of(work, request_t, work); -+ ocf_request(r); -+} -+#endif -+ -+/*************************************************************************/ -+#ifdef BENCH_IXP_ACCESS_LIB -+/*************************************************************************/ -+/* -+ * CryptoAcc benchmark routines -+ */ -+ -+static IxCryptoAccCtx ixp_ctx; -+static UINT32 ixp_ctx_id; -+static IX_MBUF ixp_pri; -+static IX_MBUF ixp_sec; -+static int ixp_registered = 0; -+ -+static void ixp_register_cb(UINT32 ctx_id, IX_MBUF *bufp, -+ IxCryptoAccStatus status); -+static void ixp_perform_cb(UINT32 ctx_id, IX_MBUF *sbufp, IX_MBUF *dbufp, -+ IxCryptoAccStatus status); -+static void ixp_request(void *arg); -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void ixp_request_wq(struct work_struct *work); -+#endif -+ -+static int -+ixp_init(void) -+{ -+ IxCryptoAccStatus status; -+ -+ ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_3DES; -+ ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; -+ ixp_ctx.cipherCtx.cipherKeyLen = 24; -+ ixp_ctx.cipherCtx.cipherBlockLen = IX_CRYPTO_ACC_DES_BLOCK_64; -+ ixp_ctx.cipherCtx.cipherInitialVectorLen = IX_CRYPTO_ACC_DES_IV_64; -+ memcpy(ixp_ctx.cipherCtx.key.cipherKey, "0123456789abcdefghijklmn", 24); -+ -+ ixp_ctx.authCtx.authAlgo = IX_CRYPTO_ACC_AUTH_SHA1; -+ ixp_ctx.authCtx.authDigestLen = 12; -+ ixp_ctx.authCtx.aadLen = 0; -+ ixp_ctx.authCtx.authKeyLen = 20; -+ memcpy(ixp_ctx.authCtx.key.authKey, "0123456789abcdefghij", 20); -+ -+ ixp_ctx.useDifferentSrcAndDestMbufs = 0; -+ ixp_ctx.operation = IX_CRYPTO_ACC_OP_ENCRYPT_AUTH ; -+ -+ IX_MBUF_MLEN(&ixp_pri) = IX_MBUF_PKT_LEN(&ixp_pri) = 128; -+ IX_MBUF_MDATA(&ixp_pri) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); -+ IX_MBUF_MLEN(&ixp_sec) = IX_MBUF_PKT_LEN(&ixp_sec) = 128; -+ IX_MBUF_MDATA(&ixp_sec) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); -+ -+ status = ixCryptoAccCtxRegister(&ixp_ctx, &ixp_pri, &ixp_sec, -+ ixp_register_cb, ixp_perform_cb, &ixp_ctx_id); -+ -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) { -+ while (!ixp_registered) -+ schedule(); -+ return ixp_registered < 0 ? -1 : 0; -+ } -+ -+ printk("ixp: ixCryptoAccCtxRegister failed %d\n", status); -+ return -1; -+} -+ -+static void -+ixp_register_cb(UINT32 ctx_id, IX_MBUF *bufp, IxCryptoAccStatus status) -+{ -+ if (bufp) { -+ IX_MBUF_MLEN(bufp) = IX_MBUF_PKT_LEN(bufp) = 0; -+ kfree(IX_MBUF_MDATA(bufp)); -+ IX_MBUF_MDATA(bufp) = NULL; -+ } -+ -+ if (IX_CRYPTO_ACC_STATUS_WAIT == status) -+ return; -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) -+ ixp_registered = 1; -+ else -+ ixp_registered = -1; -+} -+ -+static void -+ixp_perform_cb( -+ UINT32 ctx_id, -+ IX_MBUF *sbufp, -+ IX_MBUF *dbufp, -+ IxCryptoAccStatus status) -+{ -+ request_t *r = NULL; -+ -+ total++; -+ if (total > request_num) { -+ outstanding--; -+ return; -+ } -+ -+ if (!sbufp || !(r = IX_MBUF_PRIV(sbufp))) { -+ printk("crappo %p %p\n", sbufp, r); -+ outstanding--; -+ return; -+ } -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ INIT_WORK(&r->work, ixp_request_wq); -+#else -+ INIT_WORK(&r->work, ixp_request, r); -+#endif -+ schedule_work(&r->work); -+} -+ -+static void -+ixp_request(void *arg) -+{ -+ request_t *r = arg; -+ IxCryptoAccStatus status; -+ -+ memset(&r->mbuf, 0, sizeof(r->mbuf)); -+ IX_MBUF_MLEN(&r->mbuf) = IX_MBUF_PKT_LEN(&r->mbuf) = request_size + 64; -+ IX_MBUF_MDATA(&r->mbuf) = r->buffer; -+ IX_MBUF_PRIV(&r->mbuf) = r; -+ status = ixCryptoAccAuthCryptPerform(ixp_ctx_id, &r->mbuf, NULL, -+ 0, request_size, 0, request_size, request_size, r->buffer); -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS != status) { -+ printk("status1 = %d\n", status); -+ outstanding--; -+ return; -+ } -+ return; -+} -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void -+ixp_request_wq(struct work_struct *work) -+{ -+ request_t *r = container_of(work, request_t, work); -+ ixp_request(r); -+} -+#endif -+ -+/*************************************************************************/ -+#endif /* BENCH_IXP_ACCESS_LIB */ -+/*************************************************************************/ -+ -+int -+ocfbench_init(void) -+{ -+ int i, jstart, jstop; -+ -+ printk("Crypto Speed tests\n"); -+ -+ requests = kmalloc(sizeof(request_t) * request_q_len, GFP_KERNEL); -+ if (!requests) { -+ printk("malloc failed\n"); -+ return -EINVAL; -+ } -+ -+ for (i = 0; i < request_q_len; i++) { -+ /* +64 for return data */ -+ requests[i].buffer = kmalloc(request_size + 128, GFP_DMA); -+ if (!requests[i].buffer) { -+ printk("malloc failed\n"); -+ return -EINVAL; -+ } -+ memset(requests[i].buffer, '0' + i, request_size + 128); -+ } -+ -+ /* -+ * OCF benchmark -+ */ -+ printk("OCF: testing ...\n"); -+ ocf_init(); -+ total = outstanding = 0; -+ jstart = jiffies; -+ for (i = 0; i < request_q_len; i++) { -+ outstanding++; -+ ocf_request(&requests[i]); -+ } -+ while (outstanding > 0) -+ schedule(); -+ jstop = jiffies; -+ -+ printk("OCF: %d requests of %d bytes in %d jiffies\n", total, request_size, -+ jstop - jstart); -+ -+#ifdef BENCH_IXP_ACCESS_LIB -+ /* -+ * IXP benchmark -+ */ -+ printk("IXP: testing ...\n"); -+ ixp_init(); -+ total = outstanding = 0; -+ jstart = jiffies; -+ for (i = 0; i < request_q_len; i++) { -+ outstanding++; -+ ixp_request(&requests[i]); -+ } -+ while (outstanding > 0) -+ schedule(); -+ jstop = jiffies; -+ -+ printk("IXP: %d requests of %d bytes in %d jiffies\n", total, request_size, -+ jstop - jstart); -+#endif /* BENCH_IXP_ACCESS_LIB */ -+ -+ for (i = 0; i < request_q_len; i++) -+ kfree(requests[i].buffer); -+ kfree(requests); -+ return -EINVAL; /* always fail to load so it can be re-run quickly ;-) */ -+} -+ -+static void __exit ocfbench_exit(void) -+{ -+} -+ -+module_init(ocfbench_init); -+module_exit(ocfbench_exit); -+ -+MODULE_LICENSE("BSD"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("Benchmark various in-kernel crypto speeds"); -diff -Nur linux-2.6.36.orig/crypto/ocf/ocf-compat.h linux-2.6.36/crypto/ocf/ocf-compat.h ---- linux-2.6.36.orig/crypto/ocf/ocf-compat.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/ocf-compat.h 2010-11-09 20:28:12.422358492 +0100 -@@ -0,0 +1,294 @@ -+#ifndef _BSD_COMPAT_H_ -+#define _BSD_COMPAT_H_ 1 -+/****************************************************************************/ -+/* -+ * Provide compat routines for older linux kernels and BSD kernels -+ * -+ * Written by David McCullough -+ * Copyright (C) 2010 David McCullough -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * ALTERNATIVELY, provided that this notice is retained in full, this file -+ * may be distributed under the terms of the GNU General Public License (GPL), -+ * in which case the provisions of the GPL apply INSTEAD OF those given above. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ */ -+/****************************************************************************/ -+#ifdef __KERNEL__ -+/* -+ * fake some BSD driver interface stuff specifically for OCF use -+ */ -+ -+typedef struct ocf_device *device_t; -+ -+typedef struct { -+ int (*cryptodev_newsession)(device_t dev, u_int32_t *sidp, struct cryptoini *cri); -+ int (*cryptodev_freesession)(device_t dev, u_int64_t tid); -+ int (*cryptodev_process)(device_t dev, struct cryptop *crp, int hint); -+ int (*cryptodev_kprocess)(device_t dev, struct cryptkop *krp, int hint); -+} device_method_t; -+#define DEVMETHOD(id, func) id: func -+ -+struct ocf_device { -+ char name[32]; /* the driver name */ -+ char nameunit[32]; /* the driver name + HW instance */ -+ int unit; -+ device_method_t methods; -+ void *softc; -+}; -+ -+#define CRYPTODEV_NEWSESSION(dev, sid, cri) \ -+ ((*(dev)->methods.cryptodev_newsession)(dev,sid,cri)) -+#define CRYPTODEV_FREESESSION(dev, sid) \ -+ ((*(dev)->methods.cryptodev_freesession)(dev, sid)) -+#define CRYPTODEV_PROCESS(dev, crp, hint) \ -+ ((*(dev)->methods.cryptodev_process)(dev, crp, hint)) -+#define CRYPTODEV_KPROCESS(dev, krp, hint) \ -+ ((*(dev)->methods.cryptodev_kprocess)(dev, krp, hint)) -+ -+#define device_get_name(dev) ((dev)->name) -+#define device_get_nameunit(dev) ((dev)->nameunit) -+#define device_get_unit(dev) ((dev)->unit) -+#define device_get_softc(dev) ((dev)->softc) -+ -+#define softc_device_decl \ -+ struct ocf_device _device; \ -+ device_t -+ -+#define softc_device_init(_sc, _name, _unit, _methods) \ -+ if (1) {\ -+ strncpy((_sc)->_device.name, _name, sizeof((_sc)->_device.name) - 1); \ -+ snprintf((_sc)->_device.nameunit, sizeof((_sc)->_device.name), "%s%d", _name, _unit); \ -+ (_sc)->_device.unit = _unit; \ -+ (_sc)->_device.methods = _methods; \ -+ (_sc)->_device.softc = (void *) _sc; \ -+ *(device_t *)((softc_get_device(_sc))+1) = &(_sc)->_device; \ -+ } else -+ -+#define softc_get_device(_sc) (&(_sc)->_device) -+ -+/* -+ * iomem support for 2.4 and 2.6 kernels -+ */ -+#include -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+#define ocf_iomem_t unsigned long -+ -+/* -+ * implement simple workqueue like support for older kernels -+ */ -+ -+#include -+ -+#define work_struct tq_struct -+ -+#define INIT_WORK(wp, fp, ap) \ -+ do { \ -+ (wp)->sync = 0; \ -+ (wp)->routine = (fp); \ -+ (wp)->data = (ap); \ -+ } while (0) -+ -+#define schedule_work(wp) \ -+ do { \ -+ queue_task((wp), &tq_immediate); \ -+ mark_bh(IMMEDIATE_BH); \ -+ } while (0) -+ -+#define flush_scheduled_work() run_task_queue(&tq_immediate) -+ -+#else -+#define ocf_iomem_t void __iomem * -+ -+#include -+ -+#endif -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26) -+#include -+#elif LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) -+#define files_fdtable(files) (files) -+#endif -+ -+#ifdef MODULE_PARM -+#undef module_param /* just in case */ -+#define module_param(a,b,c) MODULE_PARM(a,"i") -+#endif -+ -+#define bzero(s,l) memset(s,0,l) -+#define bcopy(s,d,l) memcpy(d,s,l) -+#define bcmp(x, y, l) memcmp(x,y,l) -+ -+#define MIN(x,y) ((x) < (y) ? (x) : (y)) -+ -+#define device_printf(dev, a...) ({ \ -+ printk("%s: ", device_get_nameunit(dev)); printk(a); \ -+ }) -+ -+#undef printf -+#define printf(fmt...) printk(fmt) -+ -+#define KASSERT(c,p) if (!(c)) { printk p ; } else -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+#define ocf_daemonize(str) \ -+ daemonize(); \ -+ spin_lock_irq(¤t->sigmask_lock); \ -+ sigemptyset(¤t->blocked); \ -+ recalc_sigpending(current); \ -+ spin_unlock_irq(¤t->sigmask_lock); \ -+ sprintf(current->comm, str); -+#else -+#define ocf_daemonize(str) daemonize(str); -+#endif -+ -+#define TAILQ_INSERT_TAIL(q,d,m) list_add_tail(&(d)->m, (q)) -+#define TAILQ_EMPTY(q) list_empty(q) -+#define TAILQ_FOREACH(v, q, m) list_for_each_entry(v, q, m) -+ -+#define read_random(p,l) get_random_bytes(p,l) -+ -+#define DELAY(x) ((x) > 2000 ? mdelay((x)/1000) : udelay(x)) -+#define strtoul simple_strtoul -+ -+#define pci_get_vendor(dev) ((dev)->vendor) -+#define pci_get_device(dev) ((dev)->device) -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+#define pci_set_consistent_dma_mask(dev, mask) (0) -+#endif -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10) -+#define pci_dma_sync_single_for_cpu pci_dma_sync_single -+#endif -+ -+#ifndef DMA_32BIT_MASK -+#define DMA_32BIT_MASK 0x00000000ffffffffULL -+#endif -+ -+#ifndef htole32 -+#define htole32(x) cpu_to_le32(x) -+#endif -+#ifndef htobe32 -+#define htobe32(x) cpu_to_be32(x) -+#endif -+#ifndef htole16 -+#define htole16(x) cpu_to_le16(x) -+#endif -+#ifndef htobe16 -+#define htobe16(x) cpu_to_be16(x) -+#endif -+ -+/* older kernels don't have these */ -+ -+#include -+#if !defined(IRQ_NONE) && !defined(IRQ_RETVAL) -+#define IRQ_NONE -+#define IRQ_HANDLED -+#define IRQ_WAKE_THREAD -+#define IRQ_RETVAL -+#define irqreturn_t void -+typedef irqreturn_t (*irq_handler_t)(int irq, void *arg, struct pt_regs *regs); -+#endif -+#ifndef IRQF_SHARED -+#define IRQF_SHARED SA_SHIRQ -+#endif -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) -+# define strlcpy(dest,src,len) \ -+ ({strncpy(dest,src,(len)-1); ((char *)dest)[(len)-1] = '\0'; }) -+#endif -+ -+#ifndef MAX_ERRNO -+#define MAX_ERRNO 4095 -+#endif -+#ifndef IS_ERR_VALUE -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,5) -+#include -+#endif -+#ifndef IS_ERR_VALUE -+#define IS_ERR_VALUE(x) ((unsigned long)(x) >= (unsigned long)-MAX_ERRNO) -+#endif -+#endif -+ -+/* -+ * common debug for all -+ */ -+#if 1 -+#define dprintk(a...) do { if (debug) printk(a); } while(0) -+#else -+#define dprintk(a...) -+#endif -+ -+#ifndef SLAB_ATOMIC -+/* Changed in 2.6.20, must use GFP_ATOMIC now */ -+#define SLAB_ATOMIC GFP_ATOMIC -+#endif -+ -+/* -+ * need some additional support for older kernels */ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,2) -+#define pci_register_driver_compat(driver, rc) \ -+ do { \ -+ if ((rc) > 0) { \ -+ (rc) = 0; \ -+ } else if (rc == 0) { \ -+ (rc) = -ENODEV; \ -+ } else { \ -+ pci_unregister_driver(driver); \ -+ } \ -+ } while (0) -+#elif LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10) -+#define pci_register_driver_compat(driver,rc) ((rc) = (rc) < 0 ? (rc) : 0) -+#else -+#define pci_register_driver_compat(driver,rc) -+#endif -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) -+ -+#include -+#include -+ -+static inline void sg_set_page(struct scatterlist *sg, struct page *page, -+ unsigned int len, unsigned int offset) -+{ -+ sg->page = page; -+ sg->offset = offset; -+ sg->length = len; -+} -+ -+static inline void *sg_virt(struct scatterlist *sg) -+{ -+ return page_address(sg->page) + sg->offset; -+} -+ -+#define sg_init_table(sg, n) -+ -+#endif -+ -+#ifndef late_initcall -+#define late_initcall(init) module_init(init) -+#endif -+ -+#endif /* __KERNEL__ */ -+ -+/****************************************************************************/ -+#endif /* _BSD_COMPAT_H_ */ -diff -Nur linux-2.6.36.orig/crypto/ocf/ocfnull/Makefile linux-2.6.36/crypto/ocf/ocfnull/Makefile ---- linux-2.6.36.orig/crypto/ocf/ocfnull/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/ocfnull/Makefile 2010-11-09 20:28:12.462495574 +0100 -@@ -0,0 +1,12 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+obj-$(CONFIG_OCF_OCFNULL) += ocfnull.o -+ -+obj ?= . -+EXTRA_CFLAGS += -I$(obj)/.. -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/ocfnull/ocfnull.c linux-2.6.36/crypto/ocf/ocfnull/ocfnull.c ---- linux-2.6.36.orig/crypto/ocf/ocfnull/ocfnull.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/ocfnull/ocfnull.c 2010-11-09 20:28:12.501251038 +0100 -@@ -0,0 +1,203 @@ -+/* -+ * An OCF module for determining the cost of crypto versus the cost of -+ * IPSec processing outside of OCF. This modules gives us the effect of -+ * zero cost encryption, of course you will need to run it at both ends -+ * since it does no crypto at all. -+ * -+ * Written by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * ALTERNATIVELY, provided that this notice is retained in full, this product -+ * may be distributed under the terms of the GNU General Public License (GPL), -+ * in which case the provisions of the GPL apply INSTEAD OF those given above. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ */ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+static int32_t null_id = -1; -+static u_int32_t null_sesnum = 0; -+ -+static int null_process(device_t, struct cryptop *, int); -+static int null_newsession(device_t, u_int32_t *, struct cryptoini *); -+static int null_freesession(device_t, u_int64_t); -+ -+#define debug ocfnull_debug -+int ocfnull_debug = 0; -+module_param(ocfnull_debug, int, 0644); -+MODULE_PARM_DESC(ocfnull_debug, "Enable debug"); -+ -+/* -+ * dummy device structure -+ */ -+ -+static struct { -+ softc_device_decl sc_dev; -+} nulldev; -+ -+static device_method_t null_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, null_newsession), -+ DEVMETHOD(cryptodev_freesession,null_freesession), -+ DEVMETHOD(cryptodev_process, null_process), -+}; -+ -+/* -+ * Generate a new software session. -+ */ -+static int -+null_newsession(device_t arg, u_int32_t *sid, struct cryptoini *cri) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid == NULL || cri == NULL) { -+ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ if (null_sesnum == 0) -+ null_sesnum++; -+ *sid = null_sesnum++; -+ return 0; -+} -+ -+ -+/* -+ * Free a session. -+ */ -+static int -+null_freesession(device_t arg, u_int64_t tid) -+{ -+ u_int32_t sid = CRYPTO_SESID2LID(tid); -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid > null_sesnum) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ /* Silently accept and return */ -+ if (sid == 0) -+ return 0; -+ return 0; -+} -+ -+ -+/* -+ * Process a request. -+ */ -+static int -+null_process(device_t arg, struct cryptop *crp, int hint) -+{ -+ unsigned int lid; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ /* Sanity check */ -+ if (crp == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ crp->crp_etype = 0; -+ -+ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ /* -+ * find the session we are using -+ */ -+ -+ lid = crp->crp_sid & 0xffffffff; -+ if (lid >= null_sesnum || lid == 0) { -+ crp->crp_etype = ENOENT; -+ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); -+ goto done; -+ } -+ -+done: -+ crypto_done(crp); -+ return 0; -+} -+ -+ -+/* -+ * our driver startup and shutdown routines -+ */ -+ -+static int -+null_init(void) -+{ -+ dprintk("%s(%p)\n", __FUNCTION__, null_init); -+ -+ memset(&nulldev, 0, sizeof(nulldev)); -+ softc_device_init(&nulldev, "ocfnull", 0, null_methods); -+ -+ null_id = crypto_get_driverid(softc_get_device(&nulldev), -+ CRYPTOCAP_F_HARDWARE); -+ if (null_id < 0) -+ panic("ocfnull: crypto device cannot initialize!"); -+ -+#define REGISTER(alg) \ -+ crypto_register(null_id,alg,0,0) -+ REGISTER(CRYPTO_DES_CBC); -+ REGISTER(CRYPTO_3DES_CBC); -+ REGISTER(CRYPTO_RIJNDAEL128_CBC); -+ REGISTER(CRYPTO_MD5); -+ REGISTER(CRYPTO_SHA1); -+ REGISTER(CRYPTO_MD5_HMAC); -+ REGISTER(CRYPTO_SHA1_HMAC); -+#undef REGISTER -+ -+ return 0; -+} -+ -+static void -+null_exit(void) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ crypto_unregister_all(null_id); -+ null_id = -1; -+} -+ -+module_init(null_init); -+module_exit(null_exit); -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("ocfnull - claims a lot but does nothing"); -diff -Nur linux-2.6.36.orig/crypto/ocf/pasemi/Makefile linux-2.6.36/crypto/ocf/pasemi/Makefile ---- linux-2.6.36.orig/crypto/ocf/pasemi/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/pasemi/Makefile 2010-11-09 20:28:12.532495480 +0100 -@@ -0,0 +1,12 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+obj-$(CONFIG_OCF_PASEMI) += pasemi.o -+ -+obj ?= . -+EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/pasemi/pasemi.c linux-2.6.36/crypto/ocf/pasemi/pasemi.c ---- linux-2.6.36.orig/crypto/ocf/pasemi/pasemi.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/pasemi/pasemi.c 2010-11-09 20:28:12.572495531 +0100 -@@ -0,0 +1,1009 @@ -+/* -+ * Copyright (C) 2007 PA Semi, Inc -+ * -+ * Driver for the PA Semi PWRficient DMA Crypto Engine -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "pasemi_fnu.h" -+ -+#define DRV_NAME "pasemi" -+ -+#define TIMER_INTERVAL 1000 -+ -+static void __devexit pasemi_dma_remove(struct pci_dev *pdev); -+static struct pasdma_status volatile * dma_status; -+ -+static int debug; -+module_param(debug, int, 0644); -+MODULE_PARM_DESC(debug, "Enable debug"); -+ -+static void pasemi_desc_start(struct pasemi_desc *desc, u64 hdr) -+{ -+ desc->postop = 0; -+ desc->quad[0] = hdr; -+ desc->quad_cnt = 1; -+ desc->size = 1; -+} -+ -+static void pasemi_desc_build(struct pasemi_desc *desc, u64 val) -+{ -+ desc->quad[desc->quad_cnt++] = val; -+ desc->size = (desc->quad_cnt + 1) / 2; -+} -+ -+static void pasemi_desc_hdr(struct pasemi_desc *desc, u64 hdr) -+{ -+ desc->quad[0] |= hdr; -+} -+ -+static int pasemi_desc_size(struct pasemi_desc *desc) -+{ -+ return desc->size; -+} -+ -+static void pasemi_ring_add_desc( -+ struct pasemi_fnu_txring *ring, -+ struct pasemi_desc *desc, -+ struct cryptop *crp) { -+ int i; -+ int ring_index = 2 * (ring->next_to_fill & (TX_RING_SIZE-1)); -+ -+ TX_DESC_INFO(ring, ring->next_to_fill).desc_size = desc->size; -+ TX_DESC_INFO(ring, ring->next_to_fill).desc_postop = desc->postop; -+ TX_DESC_INFO(ring, ring->next_to_fill).cf_crp = crp; -+ -+ for (i = 0; i < desc->quad_cnt; i += 2) { -+ ring_index = 2 * (ring->next_to_fill & (TX_RING_SIZE-1)); -+ ring->desc[ring_index] = desc->quad[i]; -+ ring->desc[ring_index + 1] = desc->quad[i + 1]; -+ ring->next_to_fill++; -+ } -+ -+ if (desc->quad_cnt & 1) -+ ring->desc[ring_index + 1] = 0; -+} -+ -+static void pasemi_ring_incr(struct pasemi_softc *sc, int chan_index, int incr) -+{ -+ out_le32(sc->dma_regs + PAS_DMA_TXCHAN_INCR(sc->base_chan + chan_index), -+ incr); -+} -+ -+/* -+ * Generate a new software session. -+ */ -+static int -+pasemi_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) -+{ -+ struct cryptoini *c, *encini = NULL, *macini = NULL; -+ struct pasemi_softc *sc = device_get_softc(dev); -+ struct pasemi_session *ses = NULL, **sespp; -+ int sesn, blksz = 0; -+ u64 ccmd = 0; -+ unsigned long flags; -+ struct pasemi_desc init_desc; -+ struct pasemi_fnu_txring *txring; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ if (sidp == NULL || cri == NULL || sc == NULL) { -+ DPRINTF("%s,%d - EINVAL\n", __FILE__, __LINE__); -+ return -EINVAL; -+ } -+ for (c = cri; c != NULL; c = c->cri_next) { -+ if (ALG_IS_SIG(c->cri_alg)) { -+ if (macini) -+ return -EINVAL; -+ macini = c; -+ } else if (ALG_IS_CIPHER(c->cri_alg)) { -+ if (encini) -+ return -EINVAL; -+ encini = c; -+ } else { -+ DPRINTF("UNKNOWN c->cri_alg %d\n", c->cri_alg); -+ return -EINVAL; -+ } -+ } -+ if (encini == NULL && macini == NULL) -+ return -EINVAL; -+ if (encini) { -+ /* validate key length */ -+ switch (encini->cri_alg) { -+ case CRYPTO_DES_CBC: -+ if (encini->cri_klen != 64) -+ return -EINVAL; -+ ccmd = DMA_CALGO_DES; -+ break; -+ case CRYPTO_3DES_CBC: -+ if (encini->cri_klen != 192) -+ return -EINVAL; -+ ccmd = DMA_CALGO_3DES; -+ break; -+ case CRYPTO_AES_CBC: -+ if (encini->cri_klen != 128 && -+ encini->cri_klen != 192 && -+ encini->cri_klen != 256) -+ return -EINVAL; -+ ccmd = DMA_CALGO_AES; -+ break; -+ case CRYPTO_ARC4: -+ if (encini->cri_klen != 128) -+ return -EINVAL; -+ ccmd = DMA_CALGO_ARC; -+ break; -+ default: -+ DPRINTF("UNKNOWN encini->cri_alg %d\n", -+ encini->cri_alg); -+ return -EINVAL; -+ } -+ } -+ -+ if (macini) { -+ switch (macini->cri_alg) { -+ case CRYPTO_MD5: -+ case CRYPTO_MD5_HMAC: -+ blksz = 16; -+ break; -+ case CRYPTO_SHA1: -+ case CRYPTO_SHA1_HMAC: -+ blksz = 20; -+ break; -+ default: -+ DPRINTF("UNKNOWN macini->cri_alg %d\n", -+ macini->cri_alg); -+ return -EINVAL; -+ } -+ if (((macini->cri_klen + 7) / 8) > blksz) { -+ DPRINTF("key length %d bigger than blksize %d not supported\n", -+ ((macini->cri_klen + 7) / 8), blksz); -+ return -EINVAL; -+ } -+ } -+ -+ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { -+ if (sc->sc_sessions[sesn] == NULL) { -+ sc->sc_sessions[sesn] = (struct pasemi_session *) -+ kzalloc(sizeof(struct pasemi_session), GFP_ATOMIC); -+ ses = sc->sc_sessions[sesn]; -+ break; -+ } else if (sc->sc_sessions[sesn]->used == 0) { -+ ses = sc->sc_sessions[sesn]; -+ break; -+ } -+ } -+ -+ if (ses == NULL) { -+ sespp = (struct pasemi_session **) -+ kzalloc(sc->sc_nsessions * 2 * -+ sizeof(struct pasemi_session *), GFP_ATOMIC); -+ if (sespp == NULL) -+ return -ENOMEM; -+ memcpy(sespp, sc->sc_sessions, -+ sc->sc_nsessions * sizeof(struct pasemi_session *)); -+ kfree(sc->sc_sessions); -+ sc->sc_sessions = sespp; -+ sesn = sc->sc_nsessions; -+ ses = sc->sc_sessions[sesn] = (struct pasemi_session *) -+ kzalloc(sizeof(struct pasemi_session), GFP_ATOMIC); -+ if (ses == NULL) -+ return -ENOMEM; -+ sc->sc_nsessions *= 2; -+ } -+ -+ ses->used = 1; -+ -+ ses->dma_addr = pci_map_single(sc->dma_pdev, (void *) ses->civ, -+ sizeof(struct pasemi_session), DMA_TO_DEVICE); -+ -+ /* enter the channel scheduler */ -+ spin_lock_irqsave(&sc->sc_chnlock, flags); -+ -+ /* ARC4 has to be processed by the even channel */ -+ if (encini && (encini->cri_alg == CRYPTO_ARC4)) -+ ses->chan = sc->sc_lastchn & ~1; -+ else -+ ses->chan = sc->sc_lastchn; -+ sc->sc_lastchn = (sc->sc_lastchn + 1) % sc->sc_num_channels; -+ -+ spin_unlock_irqrestore(&sc->sc_chnlock, flags); -+ -+ txring = &sc->tx[ses->chan]; -+ -+ if (encini) { -+ ses->ccmd = ccmd; -+ -+ /* get an IV */ -+ /* XXX may read fewer than requested */ -+ get_random_bytes(ses->civ, sizeof(ses->civ)); -+ -+ ses->keysz = (encini->cri_klen - 63) / 64; -+ memcpy(ses->key, encini->cri_key, (ses->keysz + 1) * 8); -+ -+ pasemi_desc_start(&init_desc, -+ XCT_CTRL_HDR(ses->chan, (encini && macini) ? 0x68 : 0x40, DMA_FN_CIV0)); -+ pasemi_desc_build(&init_desc, -+ XCT_FUN_SRC_PTR((encini && macini) ? 0x68 : 0x40, ses->dma_addr)); -+ } -+ if (macini) { -+ if (macini->cri_alg == CRYPTO_MD5_HMAC || -+ macini->cri_alg == CRYPTO_SHA1_HMAC) -+ memcpy(ses->hkey, macini->cri_key, blksz); -+ else { -+ /* Load initialization constants(RFC 1321, 3174) */ -+ ses->hiv[0] = 0x67452301efcdab89ULL; -+ ses->hiv[1] = 0x98badcfe10325476ULL; -+ ses->hiv[2] = 0xc3d2e1f000000000ULL; -+ } -+ ses->hseq = 0ULL; -+ } -+ -+ spin_lock_irqsave(&txring->fill_lock, flags); -+ -+ if (((txring->next_to_fill + pasemi_desc_size(&init_desc)) - -+ txring->next_to_clean) > TX_RING_SIZE) { -+ spin_unlock_irqrestore(&txring->fill_lock, flags); -+ return ERESTART; -+ } -+ -+ if (encini) { -+ pasemi_ring_add_desc(txring, &init_desc, NULL); -+ pasemi_ring_incr(sc, ses->chan, -+ pasemi_desc_size(&init_desc)); -+ } -+ -+ txring->sesn = sesn; -+ spin_unlock_irqrestore(&txring->fill_lock, flags); -+ -+ *sidp = PASEMI_SID(sesn); -+ return 0; -+} -+ -+/* -+ * Deallocate a session. -+ */ -+static int -+pasemi_freesession(device_t dev, u_int64_t tid) -+{ -+ struct pasemi_softc *sc = device_get_softc(dev); -+ int session; -+ u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (sc == NULL) -+ return -EINVAL; -+ session = PASEMI_SESSION(sid); -+ if (session >= sc->sc_nsessions || !sc->sc_sessions[session]) -+ return -EINVAL; -+ -+ pci_unmap_single(sc->dma_pdev, -+ sc->sc_sessions[session]->dma_addr, -+ sizeof(struct pasemi_session), DMA_TO_DEVICE); -+ memset(sc->sc_sessions[session], 0, -+ sizeof(struct pasemi_session)); -+ -+ return 0; -+} -+ -+static int -+pasemi_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ -+ int err = 0, ivsize, srclen = 0, reinit = 0, reinit_size = 0, chsel; -+ struct pasemi_softc *sc = device_get_softc(dev); -+ struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; -+ caddr_t ivp; -+ struct pasemi_desc init_desc, work_desc; -+ struct pasemi_session *ses; -+ struct sk_buff *skb; -+ struct uio *uiop; -+ unsigned long flags; -+ struct pasemi_fnu_txring *txring; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (crp == NULL || crp->crp_callback == NULL || sc == NULL) -+ return -EINVAL; -+ -+ crp->crp_etype = 0; -+ if (PASEMI_SESSION(crp->crp_sid) >= sc->sc_nsessions) -+ return -EINVAL; -+ -+ ses = sc->sc_sessions[PASEMI_SESSION(crp->crp_sid)]; -+ -+ crd1 = crp->crp_desc; -+ if (crd1 == NULL) { -+ err = -EINVAL; -+ goto errout; -+ } -+ crd2 = crd1->crd_next; -+ -+ if (ALG_IS_SIG(crd1->crd_alg)) { -+ maccrd = crd1; -+ if (crd2 == NULL) -+ enccrd = NULL; -+ else if (ALG_IS_CIPHER(crd2->crd_alg) && -+ (crd2->crd_flags & CRD_F_ENCRYPT) == 0) -+ enccrd = crd2; -+ else -+ goto erralg; -+ } else if (ALG_IS_CIPHER(crd1->crd_alg)) { -+ enccrd = crd1; -+ if (crd2 == NULL) -+ maccrd = NULL; -+ else if (ALG_IS_SIG(crd2->crd_alg) && -+ (crd1->crd_flags & CRD_F_ENCRYPT)) -+ maccrd = crd2; -+ else -+ goto erralg; -+ } else -+ goto erralg; -+ -+ chsel = ses->chan; -+ -+ txring = &sc->tx[chsel]; -+ -+ if (enccrd && !maccrd) { -+ if (enccrd->crd_alg == CRYPTO_ARC4) -+ reinit = 1; -+ reinit_size = 0x40; -+ srclen = crp->crp_ilen; -+ -+ pasemi_desc_start(&work_desc, XCT_FUN_O | XCT_FUN_I -+ | XCT_FUN_FUN(chsel)); -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) -+ pasemi_desc_hdr(&work_desc, XCT_FUN_CRM_ENC); -+ else -+ pasemi_desc_hdr(&work_desc, XCT_FUN_CRM_DEC); -+ } else if (enccrd && maccrd) { -+ if (enccrd->crd_alg == CRYPTO_ARC4) -+ reinit = 1; -+ reinit_size = 0x68; -+ -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) { -+ /* Encrypt -> Authenticate */ -+ pasemi_desc_start(&work_desc, XCT_FUN_O | XCT_FUN_I | XCT_FUN_CRM_ENC_SIG -+ | XCT_FUN_A | XCT_FUN_FUN(chsel)); -+ srclen = maccrd->crd_skip + maccrd->crd_len; -+ } else { -+ /* Authenticate -> Decrypt */ -+ pasemi_desc_start(&work_desc, XCT_FUN_O | XCT_FUN_I | XCT_FUN_CRM_SIG_DEC -+ | XCT_FUN_24BRES | XCT_FUN_FUN(chsel)); -+ pasemi_desc_build(&work_desc, 0); -+ pasemi_desc_build(&work_desc, 0); -+ pasemi_desc_build(&work_desc, 0); -+ work_desc.postop = PASEMI_CHECK_SIG; -+ srclen = crp->crp_ilen; -+ } -+ -+ pasemi_desc_hdr(&work_desc, XCT_FUN_SHL(maccrd->crd_skip / 4)); -+ pasemi_desc_hdr(&work_desc, XCT_FUN_CHL(enccrd->crd_skip - maccrd->crd_skip)); -+ } else if (!enccrd && maccrd) { -+ srclen = maccrd->crd_len; -+ -+ pasemi_desc_start(&init_desc, -+ XCT_CTRL_HDR(chsel, 0x58, DMA_FN_HKEY0)); -+ pasemi_desc_build(&init_desc, -+ XCT_FUN_SRC_PTR(0x58, ((struct pasemi_session *)ses->dma_addr)->hkey)); -+ -+ pasemi_desc_start(&work_desc, XCT_FUN_O | XCT_FUN_I | XCT_FUN_CRM_SIG -+ | XCT_FUN_A | XCT_FUN_FUN(chsel)); -+ } -+ -+ if (enccrd) { -+ switch (enccrd->crd_alg) { -+ case CRYPTO_3DES_CBC: -+ pasemi_desc_hdr(&work_desc, XCT_FUN_ALG_3DES | -+ XCT_FUN_BCM_CBC); -+ ivsize = sizeof(u64); -+ break; -+ case CRYPTO_DES_CBC: -+ pasemi_desc_hdr(&work_desc, XCT_FUN_ALG_DES | -+ XCT_FUN_BCM_CBC); -+ ivsize = sizeof(u64); -+ break; -+ case CRYPTO_AES_CBC: -+ pasemi_desc_hdr(&work_desc, XCT_FUN_ALG_AES | -+ XCT_FUN_BCM_CBC); -+ ivsize = 2 * sizeof(u64); -+ break; -+ case CRYPTO_ARC4: -+ pasemi_desc_hdr(&work_desc, XCT_FUN_ALG_ARC); -+ ivsize = 0; -+ break; -+ default: -+ printk(DRV_NAME ": unimplemented enccrd->crd_alg %d\n", -+ enccrd->crd_alg); -+ err = -EINVAL; -+ goto errout; -+ } -+ -+ ivp = (ivsize == sizeof(u64)) ? (caddr_t) &ses->civ[1] : (caddr_t) &ses->civ[0]; -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) { -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) -+ memcpy(ivp, enccrd->crd_iv, ivsize); -+ /* If IV is not present in the buffer already, it has to be copied there */ -+ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ enccrd->crd_inject, ivsize, ivp); -+ } else { -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) -+ /* IV is provided expicitly in descriptor */ -+ memcpy(ivp, enccrd->crd_iv, ivsize); -+ else -+ /* IV is provided in the packet */ -+ crypto_copydata(crp->crp_flags, crp->crp_buf, -+ enccrd->crd_inject, ivsize, -+ ivp); -+ } -+ } -+ -+ if (maccrd) { -+ switch (maccrd->crd_alg) { -+ case CRYPTO_MD5: -+ pasemi_desc_hdr(&work_desc, XCT_FUN_SIG_MD5 | -+ XCT_FUN_HSZ((crp->crp_ilen - maccrd->crd_inject) / 4)); -+ break; -+ case CRYPTO_SHA1: -+ pasemi_desc_hdr(&work_desc, XCT_FUN_SIG_SHA1 | -+ XCT_FUN_HSZ((crp->crp_ilen - maccrd->crd_inject) / 4)); -+ break; -+ case CRYPTO_MD5_HMAC: -+ pasemi_desc_hdr(&work_desc, XCT_FUN_SIG_HMAC_MD5 | -+ XCT_FUN_HSZ((crp->crp_ilen - maccrd->crd_inject) / 4)); -+ break; -+ case CRYPTO_SHA1_HMAC: -+ pasemi_desc_hdr(&work_desc, XCT_FUN_SIG_HMAC_SHA1 | -+ XCT_FUN_HSZ((crp->crp_ilen - maccrd->crd_inject) / 4)); -+ break; -+ default: -+ printk(DRV_NAME ": unimplemented maccrd->crd_alg %d\n", -+ maccrd->crd_alg); -+ err = -EINVAL; -+ goto errout; -+ } -+ } -+ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ /* using SKB buffers */ -+ skb = (struct sk_buff *)crp->crp_buf; -+ if (skb_shinfo(skb)->nr_frags) { -+ printk(DRV_NAME ": skb frags unimplemented\n"); -+ err = -EINVAL; -+ goto errout; -+ } -+ pasemi_desc_build( -+ &work_desc, -+ XCT_FUN_DST_PTR(skb->len, pci_map_single( -+ sc->dma_pdev, skb->data, -+ skb->len, DMA_TO_DEVICE))); -+ pasemi_desc_build( -+ &work_desc, -+ XCT_FUN_SRC_PTR( -+ srclen, pci_map_single( -+ sc->dma_pdev, skb->data, -+ srclen, DMA_TO_DEVICE))); -+ pasemi_desc_hdr(&work_desc, XCT_FUN_LLEN(srclen)); -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ /* using IOV buffers */ -+ uiop = (struct uio *)crp->crp_buf; -+ if (uiop->uio_iovcnt > 1) { -+ printk(DRV_NAME ": iov frags unimplemented\n"); -+ err = -EINVAL; -+ goto errout; -+ } -+ -+ /* crp_olen is never set; always use crp_ilen */ -+ pasemi_desc_build( -+ &work_desc, -+ XCT_FUN_DST_PTR(crp->crp_ilen, pci_map_single( -+ sc->dma_pdev, -+ uiop->uio_iov->iov_base, -+ crp->crp_ilen, DMA_TO_DEVICE))); -+ pasemi_desc_hdr(&work_desc, XCT_FUN_LLEN(srclen)); -+ -+ pasemi_desc_build( -+ &work_desc, -+ XCT_FUN_SRC_PTR(srclen, pci_map_single( -+ sc->dma_pdev, -+ uiop->uio_iov->iov_base, -+ srclen, DMA_TO_DEVICE))); -+ } else { -+ /* using contig buffers */ -+ pasemi_desc_build( -+ &work_desc, -+ XCT_FUN_DST_PTR(crp->crp_ilen, pci_map_single( -+ sc->dma_pdev, -+ crp->crp_buf, -+ crp->crp_ilen, DMA_TO_DEVICE))); -+ pasemi_desc_build( -+ &work_desc, -+ XCT_FUN_SRC_PTR(srclen, pci_map_single( -+ sc->dma_pdev, -+ crp->crp_buf, srclen, -+ DMA_TO_DEVICE))); -+ pasemi_desc_hdr(&work_desc, XCT_FUN_LLEN(srclen)); -+ } -+ -+ spin_lock_irqsave(&txring->fill_lock, flags); -+ -+ if (txring->sesn != PASEMI_SESSION(crp->crp_sid)) { -+ txring->sesn = PASEMI_SESSION(crp->crp_sid); -+ reinit = 1; -+ } -+ -+ if (enccrd) { -+ pasemi_desc_start(&init_desc, -+ XCT_CTRL_HDR(chsel, reinit ? reinit_size : 0x10, DMA_FN_CIV0)); -+ pasemi_desc_build(&init_desc, -+ XCT_FUN_SRC_PTR(reinit ? reinit_size : 0x10, ses->dma_addr)); -+ } -+ -+ if (((txring->next_to_fill + pasemi_desc_size(&init_desc) + -+ pasemi_desc_size(&work_desc)) - -+ txring->next_to_clean) > TX_RING_SIZE) { -+ spin_unlock_irqrestore(&txring->fill_lock, flags); -+ err = ERESTART; -+ goto errout; -+ } -+ -+ pasemi_ring_add_desc(txring, &init_desc, NULL); -+ pasemi_ring_add_desc(txring, &work_desc, crp); -+ -+ pasemi_ring_incr(sc, chsel, -+ pasemi_desc_size(&init_desc) + -+ pasemi_desc_size(&work_desc)); -+ -+ spin_unlock_irqrestore(&txring->fill_lock, flags); -+ -+ mod_timer(&txring->crypto_timer, jiffies + TIMER_INTERVAL); -+ -+ return 0; -+ -+erralg: -+ printk(DRV_NAME ": unsupported algorithm or algorithm order alg1 %d alg2 %d\n", -+ crd1->crd_alg, crd2->crd_alg); -+ err = -EINVAL; -+ -+errout: -+ if (err != ERESTART) { -+ crp->crp_etype = err; -+ crypto_done(crp); -+ } -+ return err; -+} -+ -+static int pasemi_clean_tx(struct pasemi_softc *sc, int chan) -+{ -+ int i, j, ring_idx; -+ struct pasemi_fnu_txring *ring = &sc->tx[chan]; -+ u16 delta_cnt; -+ int flags, loops = 10; -+ int desc_size; -+ struct cryptop *crp; -+ -+ spin_lock_irqsave(&ring->clean_lock, flags); -+ -+ while ((delta_cnt = (dma_status->tx_sta[sc->base_chan + chan] -+ & PAS_STATUS_PCNT_M) - ring->total_pktcnt) -+ && loops--) { -+ -+ for (i = 0; i < delta_cnt; i++) { -+ desc_size = TX_DESC_INFO(ring, ring->next_to_clean).desc_size; -+ crp = TX_DESC_INFO(ring, ring->next_to_clean).cf_crp; -+ if (crp) { -+ ring_idx = 2 * (ring->next_to_clean & (TX_RING_SIZE-1)); -+ if (TX_DESC_INFO(ring, ring->next_to_clean).desc_postop & PASEMI_CHECK_SIG) { -+ /* Need to make sure signature matched, -+ * if not - return error */ -+ if (!(ring->desc[ring_idx + 1] & (1ULL << 63))) -+ crp->crp_etype = -EINVAL; -+ } -+ crypto_done(TX_DESC_INFO(ring, -+ ring->next_to_clean).cf_crp); -+ TX_DESC_INFO(ring, ring->next_to_clean).cf_crp = NULL; -+ pci_unmap_single( -+ sc->dma_pdev, -+ XCT_PTR_ADDR_LEN(ring->desc[ring_idx + 1]), -+ PCI_DMA_TODEVICE); -+ -+ ring->desc[ring_idx] = ring->desc[ring_idx + 1] = 0; -+ -+ ring->next_to_clean++; -+ for (j = 1; j < desc_size; j++) { -+ ring_idx = 2 * -+ (ring->next_to_clean & -+ (TX_RING_SIZE-1)); -+ pci_unmap_single( -+ sc->dma_pdev, -+ XCT_PTR_ADDR_LEN(ring->desc[ring_idx]), -+ PCI_DMA_TODEVICE); -+ if (ring->desc[ring_idx + 1]) -+ pci_unmap_single( -+ sc->dma_pdev, -+ XCT_PTR_ADDR_LEN( -+ ring->desc[ -+ ring_idx + 1]), -+ PCI_DMA_TODEVICE); -+ ring->desc[ring_idx] = -+ ring->desc[ring_idx + 1] = 0; -+ ring->next_to_clean++; -+ } -+ } else { -+ for (j = 0; j < desc_size; j++) { -+ ring_idx = 2 * (ring->next_to_clean & (TX_RING_SIZE-1)); -+ ring->desc[ring_idx] = -+ ring->desc[ring_idx + 1] = 0; -+ ring->next_to_clean++; -+ } -+ } -+ } -+ -+ ring->total_pktcnt += delta_cnt; -+ } -+ spin_unlock_irqrestore(&ring->clean_lock, flags); -+ -+ return 0; -+} -+ -+static void sweepup_tx(struct pasemi_softc *sc) -+{ -+ int i; -+ -+ for (i = 0; i < sc->sc_num_channels; i++) -+ pasemi_clean_tx(sc, i); -+} -+ -+static irqreturn_t pasemi_intr(int irq, void *arg, struct pt_regs *regs) -+{ -+ struct pasemi_softc *sc = arg; -+ unsigned int reg; -+ int chan = irq - sc->base_irq; -+ int chan_index = sc->base_chan + chan; -+ u64 stat = dma_status->tx_sta[chan_index]; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (!(stat & PAS_STATUS_CAUSE_M)) -+ return IRQ_NONE; -+ -+ pasemi_clean_tx(sc, chan); -+ -+ stat = dma_status->tx_sta[chan_index]; -+ -+ reg = PAS_IOB_DMA_TXCH_RESET_PINTC | -+ PAS_IOB_DMA_TXCH_RESET_PCNT(sc->tx[chan].total_pktcnt); -+ -+ if (stat & PAS_STATUS_SOFT) -+ reg |= PAS_IOB_DMA_RXCH_RESET_SINTC; -+ -+ out_le32(sc->iob_regs + PAS_IOB_DMA_TXCH_RESET(chan_index), reg); -+ -+ -+ return IRQ_HANDLED; -+} -+ -+static int pasemi_dma_setup_tx_resources(struct pasemi_softc *sc, int chan) -+{ -+ u32 val; -+ int chan_index = chan + sc->base_chan; -+ int ret; -+ struct pasemi_fnu_txring *ring; -+ -+ ring = &sc->tx[chan]; -+ -+ spin_lock_init(&ring->fill_lock); -+ spin_lock_init(&ring->clean_lock); -+ -+ ring->desc_info = kzalloc(sizeof(struct pasemi_desc_info) * -+ TX_RING_SIZE, GFP_KERNEL); -+ if (!ring->desc_info) -+ return -ENOMEM; -+ -+ /* Allocate descriptors */ -+ ring->desc = dma_alloc_coherent(&sc->dma_pdev->dev, -+ TX_RING_SIZE * -+ 2 * sizeof(u64), -+ &ring->dma, GFP_KERNEL); -+ if (!ring->desc) -+ return -ENOMEM; -+ -+ memset((void *) ring->desc, 0, TX_RING_SIZE * 2 * sizeof(u64)); -+ -+ out_le32(sc->iob_regs + PAS_IOB_DMA_TXCH_RESET(chan_index), 0x30); -+ -+ ring->total_pktcnt = 0; -+ -+ out_le32(sc->dma_regs + PAS_DMA_TXCHAN_BASEL(chan_index), -+ PAS_DMA_TXCHAN_BASEL_BRBL(ring->dma)); -+ -+ val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->dma >> 32); -+ val |= PAS_DMA_TXCHAN_BASEU_SIZ(TX_RING_SIZE >> 2); -+ -+ out_le32(sc->dma_regs + PAS_DMA_TXCHAN_BASEU(chan_index), val); -+ -+ out_le32(sc->dma_regs + PAS_DMA_TXCHAN_CFG(chan_index), -+ PAS_DMA_TXCHAN_CFG_TY_FUNC | -+ PAS_DMA_TXCHAN_CFG_TATTR(chan) | -+ PAS_DMA_TXCHAN_CFG_WT(2)); -+ -+ /* enable tx channel */ -+ out_le32(sc->dma_regs + -+ PAS_DMA_TXCHAN_TCMDSTA(chan_index), -+ PAS_DMA_TXCHAN_TCMDSTA_EN); -+ -+ out_le32(sc->iob_regs + PAS_IOB_DMA_TXCH_CFG(chan_index), -+ PAS_IOB_DMA_TXCH_CFG_CNTTH(1000)); -+ -+ ring->next_to_fill = 0; -+ ring->next_to_clean = 0; -+ -+ snprintf(ring->irq_name, sizeof(ring->irq_name), -+ "%s%d", "crypto", chan); -+ -+ ring->irq = irq_create_mapping(NULL, sc->base_irq + chan); -+ ret = request_irq(ring->irq, (irq_handler_t) -+ pasemi_intr, IRQF_DISABLED, ring->irq_name, sc); -+ if (ret) { -+ printk(KERN_ERR DRV_NAME ": failed to hook irq %d ret %d\n", -+ ring->irq, ret); -+ ring->irq = -1; -+ return ret; -+ } -+ -+ setup_timer(&ring->crypto_timer, (void *) sweepup_tx, (unsigned long) sc); -+ -+ return 0; -+} -+ -+static device_method_t pasemi_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, pasemi_newsession), -+ DEVMETHOD(cryptodev_freesession, pasemi_freesession), -+ DEVMETHOD(cryptodev_process, pasemi_process), -+}; -+ -+/* Set up the crypto device structure, private data, -+ * and anything else we need before we start */ -+ -+static int __devinit -+pasemi_dma_probe(struct pci_dev *pdev, const struct pci_device_id *ent) -+{ -+ struct pasemi_softc *sc; -+ int ret, i; -+ -+ DPRINTF(KERN_ERR "%s()\n", __FUNCTION__); -+ -+ sc = kzalloc(sizeof(*sc), GFP_KERNEL); -+ if (!sc) -+ return -ENOMEM; -+ -+ softc_device_init(sc, DRV_NAME, 1, pasemi_methods); -+ -+ pci_set_drvdata(pdev, sc); -+ -+ spin_lock_init(&sc->sc_chnlock); -+ -+ sc->sc_sessions = (struct pasemi_session **) -+ kzalloc(PASEMI_INITIAL_SESSIONS * -+ sizeof(struct pasemi_session *), GFP_ATOMIC); -+ if (sc->sc_sessions == NULL) { -+ ret = -ENOMEM; -+ goto out; -+ } -+ -+ sc->sc_nsessions = PASEMI_INITIAL_SESSIONS; -+ sc->sc_lastchn = 0; -+ sc->base_irq = pdev->irq + 6; -+ sc->base_chan = 6; -+ sc->sc_cid = -1; -+ sc->dma_pdev = pdev; -+ -+ sc->iob_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL); -+ if (!sc->iob_pdev) { -+ dev_err(&pdev->dev, "Can't find I/O Bridge\n"); -+ ret = -ENODEV; -+ goto out; -+ } -+ -+ /* This is hardcoded and ugly, but we have some firmware versions -+ * who don't provide the register space in the device tree. Luckily -+ * they are at well-known locations so we can just do the math here. -+ */ -+ sc->dma_regs = -+ ioremap(0xe0000000 + (sc->dma_pdev->devfn << 12), 0x2000); -+ sc->iob_regs = -+ ioremap(0xe0000000 + (sc->iob_pdev->devfn << 12), 0x2000); -+ if (!sc->dma_regs || !sc->iob_regs) { -+ dev_err(&pdev->dev, "Can't map registers\n"); -+ ret = -ENODEV; -+ goto out; -+ } -+ -+ dma_status = __ioremap(0xfd800000, 0x1000, 0); -+ if (!dma_status) { -+ ret = -ENODEV; -+ dev_err(&pdev->dev, "Can't map dmastatus space\n"); -+ goto out; -+ } -+ -+ sc->tx = (struct pasemi_fnu_txring *) -+ kzalloc(sizeof(struct pasemi_fnu_txring) -+ * 8, GFP_KERNEL); -+ if (!sc->tx) { -+ ret = -ENOMEM; -+ goto out; -+ } -+ -+ /* Initialize the h/w */ -+ out_le32(sc->dma_regs + PAS_DMA_COM_CFG, -+ (in_le32(sc->dma_regs + PAS_DMA_COM_CFG) | -+ PAS_DMA_COM_CFG_FWF)); -+ out_le32(sc->dma_regs + PAS_DMA_COM_TXCMD, PAS_DMA_COM_TXCMD_EN); -+ -+ for (i = 0; i < PASEMI_FNU_CHANNELS; i++) { -+ sc->sc_num_channels++; -+ ret = pasemi_dma_setup_tx_resources(sc, i); -+ if (ret) -+ goto out; -+ } -+ -+ sc->sc_cid = crypto_get_driverid(softc_get_device(sc), -+ CRYPTOCAP_F_HARDWARE); -+ if (sc->sc_cid < 0) { -+ printk(KERN_ERR DRV_NAME ": could not get crypto driver id\n"); -+ ret = -ENXIO; -+ goto out; -+ } -+ -+ /* register algorithms with the framework */ -+ printk(DRV_NAME ":"); -+ -+ crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); -+ -+ return 0; -+ -+out: -+ pasemi_dma_remove(pdev); -+ return ret; -+} -+ -+#define MAX_RETRIES 5000 -+ -+static void pasemi_free_tx_resources(struct pasemi_softc *sc, int chan) -+{ -+ struct pasemi_fnu_txring *ring = &sc->tx[chan]; -+ int chan_index = chan + sc->base_chan; -+ int retries; -+ u32 stat; -+ -+ /* Stop the channel */ -+ out_le32(sc->dma_regs + -+ PAS_DMA_TXCHAN_TCMDSTA(chan_index), -+ PAS_DMA_TXCHAN_TCMDSTA_ST); -+ -+ for (retries = 0; retries < MAX_RETRIES; retries++) { -+ stat = in_le32(sc->dma_regs + -+ PAS_DMA_TXCHAN_TCMDSTA(chan_index)); -+ if (!(stat & PAS_DMA_TXCHAN_TCMDSTA_ACT)) -+ break; -+ cond_resched(); -+ } -+ -+ if (stat & PAS_DMA_TXCHAN_TCMDSTA_ACT) -+ dev_err(&sc->dma_pdev->dev, "Failed to stop tx channel %d\n", -+ chan_index); -+ -+ /* Disable the channel */ -+ out_le32(sc->dma_regs + -+ PAS_DMA_TXCHAN_TCMDSTA(chan_index), -+ 0); -+ -+ if (ring->desc_info) -+ kfree((void *) ring->desc_info); -+ if (ring->desc) -+ dma_free_coherent(&sc->dma_pdev->dev, -+ TX_RING_SIZE * -+ 2 * sizeof(u64), -+ (void *) ring->desc, ring->dma); -+ if (ring->irq != -1) -+ free_irq(ring->irq, sc); -+ -+ del_timer(&ring->crypto_timer); -+} -+ -+static void __devexit pasemi_dma_remove(struct pci_dev *pdev) -+{ -+ struct pasemi_softc *sc = pci_get_drvdata(pdev); -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (sc->sc_cid >= 0) { -+ crypto_unregister_all(sc->sc_cid); -+ } -+ -+ if (sc->tx) { -+ for (i = 0; i < sc->sc_num_channels; i++) -+ pasemi_free_tx_resources(sc, i); -+ -+ kfree(sc->tx); -+ } -+ if (sc->sc_sessions) { -+ for (i = 0; i < sc->sc_nsessions; i++) -+ kfree(sc->sc_sessions[i]); -+ kfree(sc->sc_sessions); -+ } -+ if (sc->iob_pdev) -+ pci_dev_put(sc->iob_pdev); -+ if (sc->dma_regs) -+ iounmap(sc->dma_regs); -+ if (sc->iob_regs) -+ iounmap(sc->iob_regs); -+ kfree(sc); -+} -+ -+static struct pci_device_id pasemi_dma_pci_tbl[] = { -+ { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa007) }, -+}; -+ -+MODULE_DEVICE_TABLE(pci, pasemi_dma_pci_tbl); -+ -+static struct pci_driver pasemi_dma_driver = { -+ .name = "pasemi_dma", -+ .id_table = pasemi_dma_pci_tbl, -+ .probe = pasemi_dma_probe, -+ .remove = __devexit_p(pasemi_dma_remove), -+}; -+ -+static void __exit pasemi_dma_cleanup_module(void) -+{ -+ pci_unregister_driver(&pasemi_dma_driver); -+ __iounmap(dma_status); -+ dma_status = NULL; -+} -+ -+int pasemi_dma_init_module(void) -+{ -+ return pci_register_driver(&pasemi_dma_driver); -+} -+ -+module_init(pasemi_dma_init_module); -+module_exit(pasemi_dma_cleanup_module); -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_AUTHOR("Egor Martovetsky egor@pasemi.com"); -+MODULE_DESCRIPTION("OCF driver for PA Semi PWRficient DMA Crypto Engine"); -diff -Nur linux-2.6.36.orig/crypto/ocf/pasemi/pasemi_fnu.h linux-2.6.36/crypto/ocf/pasemi/pasemi_fnu.h ---- linux-2.6.36.orig/crypto/ocf/pasemi/pasemi_fnu.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/pasemi/pasemi_fnu.h 2010-11-09 20:28:12.612495424 +0100 -@@ -0,0 +1,410 @@ -+/* -+ * Copyright (C) 2007 PA Semi, Inc -+ * -+ * Driver for the PA Semi PWRficient DMA Crypto Engine, soft state and -+ * hardware register layouts. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef PASEMI_FNU_H -+#define PASEMI_FNU_H -+ -+#include -+ -+#define PASEMI_SESSION(sid) ((sid) & 0xffffffff) -+#define PASEMI_SID(sesn) ((sesn) & 0xffffffff) -+#define DPRINTF(a...) if (debug) { printk(DRV_NAME ": " a); } -+ -+/* Must be a power of two */ -+#define RX_RING_SIZE 512 -+#define TX_RING_SIZE 512 -+#define TX_DESC(ring, num) ((ring)->desc[2 * (num & (TX_RING_SIZE-1))]) -+#define TX_DESC_INFO(ring, num) ((ring)->desc_info[(num) & (TX_RING_SIZE-1)]) -+#define MAX_DESC_SIZE 8 -+#define PASEMI_INITIAL_SESSIONS 10 -+#define PASEMI_FNU_CHANNELS 8 -+ -+/* DMA descriptor */ -+struct pasemi_desc { -+ u64 quad[2*MAX_DESC_SIZE]; -+ int quad_cnt; -+ int size; -+ int postop; -+}; -+ -+/* -+ * Holds per descriptor data -+ */ -+struct pasemi_desc_info { -+ int desc_size; -+ int desc_postop; -+#define PASEMI_CHECK_SIG 0x1 -+ -+ struct cryptop *cf_crp; -+}; -+ -+/* -+ * Holds per channel data -+ */ -+struct pasemi_fnu_txring { -+ volatile u64 *desc; -+ volatile struct -+ pasemi_desc_info *desc_info; -+ dma_addr_t dma; -+ struct timer_list crypto_timer; -+ spinlock_t fill_lock; -+ spinlock_t clean_lock; -+ unsigned int next_to_fill; -+ unsigned int next_to_clean; -+ u16 total_pktcnt; -+ int irq; -+ int sesn; -+ char irq_name[10]; -+}; -+ -+/* -+ * Holds data specific to a single pasemi device. -+ */ -+struct pasemi_softc { -+ softc_device_decl sc_cdev; -+ struct pci_dev *dma_pdev; /* device backpointer */ -+ struct pci_dev *iob_pdev; /* device backpointer */ -+ void __iomem *dma_regs; -+ void __iomem *iob_regs; -+ int base_irq; -+ int base_chan; -+ int32_t sc_cid; /* crypto tag */ -+ int sc_nsessions; -+ struct pasemi_session **sc_sessions; -+ int sc_num_channels;/* number of crypto channels */ -+ -+ /* pointer to the array of txring datastructures, one txring per channel */ -+ struct pasemi_fnu_txring *tx; -+ -+ /* -+ * mutual exclusion for the channel scheduler -+ */ -+ spinlock_t sc_chnlock; -+ /* last channel used, for now use round-robin to allocate channels */ -+ int sc_lastchn; -+}; -+ -+struct pasemi_session { -+ u64 civ[2]; -+ u64 keysz; -+ u64 key[4]; -+ u64 ccmd; -+ u64 hkey[4]; -+ u64 hseq; -+ u64 giv[2]; -+ u64 hiv[4]; -+ -+ int used; -+ dma_addr_t dma_addr; -+ int chan; -+}; -+ -+/* status register layout in IOB region, at 0xfd800000 */ -+struct pasdma_status { -+ u64 rx_sta[64]; -+ u64 tx_sta[20]; -+}; -+ -+#define ALG_IS_CIPHER(alg) ((alg == CRYPTO_DES_CBC) || \ -+ (alg == CRYPTO_3DES_CBC) || \ -+ (alg == CRYPTO_AES_CBC) || \ -+ (alg == CRYPTO_ARC4) || \ -+ (alg == CRYPTO_NULL_CBC)) -+ -+#define ALG_IS_SIG(alg) ((alg == CRYPTO_MD5) || \ -+ (alg == CRYPTO_MD5_HMAC) || \ -+ (alg == CRYPTO_SHA1) || \ -+ (alg == CRYPTO_SHA1_HMAC) || \ -+ (alg == CRYPTO_NULL_HMAC)) -+ -+enum { -+ PAS_DMA_COM_TXCMD = 0x100, /* Transmit Command Register */ -+ PAS_DMA_COM_TXSTA = 0x104, /* Transmit Status Register */ -+ PAS_DMA_COM_RXCMD = 0x108, /* Receive Command Register */ -+ PAS_DMA_COM_RXSTA = 0x10c, /* Receive Status Register */ -+ PAS_DMA_COM_CFG = 0x114, /* DMA Configuration Register */ -+}; -+ -+/* All these registers live in the PCI configuration space for the DMA PCI -+ * device. Use the normal PCI config access functions for them. -+ */ -+ -+#define PAS_DMA_COM_CFG_FWF 0x18000000 -+ -+#define PAS_DMA_COM_TXCMD_EN 0x00000001 /* enable */ -+#define PAS_DMA_COM_TXSTA_ACT 0x00000001 /* active */ -+#define PAS_DMA_COM_RXCMD_EN 0x00000001 /* enable */ -+#define PAS_DMA_COM_RXSTA_ACT 0x00000001 /* active */ -+ -+#define _PAS_DMA_TXCHAN_STRIDE 0x20 /* Size per channel */ -+#define _PAS_DMA_TXCHAN_TCMDSTA 0x300 /* Command / Status */ -+#define _PAS_DMA_TXCHAN_CFG 0x304 /* Configuration */ -+#define _PAS_DMA_TXCHAN_DSCRBU 0x308 /* Descriptor BU Allocation */ -+#define _PAS_DMA_TXCHAN_INCR 0x310 /* Descriptor increment */ -+#define _PAS_DMA_TXCHAN_CNT 0x314 /* Descriptor count/offset */ -+#define _PAS_DMA_TXCHAN_BASEL 0x318 /* Descriptor ring base (low) */ -+#define _PAS_DMA_TXCHAN_BASEU 0x31c /* (high) */ -+#define PAS_DMA_TXCHAN_TCMDSTA(c) (0x300+(c)*_PAS_DMA_TXCHAN_STRIDE) -+#define PAS_DMA_TXCHAN_TCMDSTA_EN 0x00000001 /* Enabled */ -+#define PAS_DMA_TXCHAN_TCMDSTA_ST 0x00000002 /* Stop interface */ -+#define PAS_DMA_TXCHAN_TCMDSTA_ACT 0x00010000 /* Active */ -+#define PAS_DMA_TXCHAN_CFG(c) (0x304+(c)*_PAS_DMA_TXCHAN_STRIDE) -+#define PAS_DMA_TXCHAN_CFG_TY_FUNC 0x00000002 /* Type = interface */ -+#define PAS_DMA_TXCHAN_CFG_TY_IFACE 0x00000000 /* Type = interface */ -+#define PAS_DMA_TXCHAN_CFG_TATTR_M 0x0000003c -+#define PAS_DMA_TXCHAN_CFG_TATTR_S 2 -+#define PAS_DMA_TXCHAN_CFG_TATTR(x) (((x) << PAS_DMA_TXCHAN_CFG_TATTR_S) & \ -+ PAS_DMA_TXCHAN_CFG_TATTR_M) -+#define PAS_DMA_TXCHAN_CFG_WT_M 0x000001c0 -+#define PAS_DMA_TXCHAN_CFG_WT_S 6 -+#define PAS_DMA_TXCHAN_CFG_WT(x) (((x) << PAS_DMA_TXCHAN_CFG_WT_S) & \ -+ PAS_DMA_TXCHAN_CFG_WT_M) -+#define PAS_DMA_TXCHAN_CFG_LPSQ_FAST 0x00000400 -+#define PAS_DMA_TXCHAN_CFG_LPDQ_FAST 0x00000800 -+#define PAS_DMA_TXCHAN_CFG_CF 0x00001000 /* Clean first line */ -+#define PAS_DMA_TXCHAN_CFG_CL 0x00002000 /* Clean last line */ -+#define PAS_DMA_TXCHAN_CFG_UP 0x00004000 /* update tx descr when sent */ -+#define PAS_DMA_TXCHAN_INCR(c) (0x310+(c)*_PAS_DMA_TXCHAN_STRIDE) -+#define PAS_DMA_TXCHAN_BASEL(c) (0x318+(c)*_PAS_DMA_TXCHAN_STRIDE) -+#define PAS_DMA_TXCHAN_BASEL_BRBL_M 0xffffffc0 -+#define PAS_DMA_TXCHAN_BASEL_BRBL_S 0 -+#define PAS_DMA_TXCHAN_BASEL_BRBL(x) (((x) << PAS_DMA_TXCHAN_BASEL_BRBL_S) & \ -+ PAS_DMA_TXCHAN_BASEL_BRBL_M) -+#define PAS_DMA_TXCHAN_BASEU(c) (0x31c+(c)*_PAS_DMA_TXCHAN_STRIDE) -+#define PAS_DMA_TXCHAN_BASEU_BRBH_M 0x00000fff -+#define PAS_DMA_TXCHAN_BASEU_BRBH_S 0 -+#define PAS_DMA_TXCHAN_BASEU_BRBH(x) (((x) << PAS_DMA_TXCHAN_BASEU_BRBH_S) & \ -+ PAS_DMA_TXCHAN_BASEU_BRBH_M) -+/* # of cache lines worth of buffer ring */ -+#define PAS_DMA_TXCHAN_BASEU_SIZ_M 0x3fff0000 -+#define PAS_DMA_TXCHAN_BASEU_SIZ_S 16 /* 0 = 16K */ -+#define PAS_DMA_TXCHAN_BASEU_SIZ(x) (((x) << PAS_DMA_TXCHAN_BASEU_SIZ_S) & \ -+ PAS_DMA_TXCHAN_BASEU_SIZ_M) -+ -+#define PAS_STATUS_PCNT_M 0x000000000000ffffull -+#define PAS_STATUS_PCNT_S 0 -+#define PAS_STATUS_DCNT_M 0x00000000ffff0000ull -+#define PAS_STATUS_DCNT_S 16 -+#define PAS_STATUS_BPCNT_M 0x0000ffff00000000ull -+#define PAS_STATUS_BPCNT_S 32 -+#define PAS_STATUS_CAUSE_M 0xf000000000000000ull -+#define PAS_STATUS_TIMER 0x1000000000000000ull -+#define PAS_STATUS_ERROR 0x2000000000000000ull -+#define PAS_STATUS_SOFT 0x4000000000000000ull -+#define PAS_STATUS_INT 0x8000000000000000ull -+ -+#define PAS_IOB_DMA_RXCH_CFG(i) (0x1100 + (i)*4) -+#define PAS_IOB_DMA_RXCH_CFG_CNTTH_M 0x00000fff -+#define PAS_IOB_DMA_RXCH_CFG_CNTTH_S 0 -+#define PAS_IOB_DMA_RXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_RXCH_CFG_CNTTH_S) & \ -+ PAS_IOB_DMA_RXCH_CFG_CNTTH_M) -+#define PAS_IOB_DMA_TXCH_CFG(i) (0x1200 + (i)*4) -+#define PAS_IOB_DMA_TXCH_CFG_CNTTH_M 0x00000fff -+#define PAS_IOB_DMA_TXCH_CFG_CNTTH_S 0 -+#define PAS_IOB_DMA_TXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_TXCH_CFG_CNTTH_S) & \ -+ PAS_IOB_DMA_TXCH_CFG_CNTTH_M) -+#define PAS_IOB_DMA_RXCH_STAT(i) (0x1300 + (i)*4) -+#define PAS_IOB_DMA_RXCH_STAT_INTGEN 0x00001000 -+#define PAS_IOB_DMA_RXCH_STAT_CNTDEL_M 0x00000fff -+#define PAS_IOB_DMA_RXCH_STAT_CNTDEL_S 0 -+#define PAS_IOB_DMA_RXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_RXCH_STAT_CNTDEL_S) &\ -+ PAS_IOB_DMA_RXCH_STAT_CNTDEL_M) -+#define PAS_IOB_DMA_TXCH_STAT(i) (0x1400 + (i)*4) -+#define PAS_IOB_DMA_TXCH_STAT_INTGEN 0x00001000 -+#define PAS_IOB_DMA_TXCH_STAT_CNTDEL_M 0x00000fff -+#define PAS_IOB_DMA_TXCH_STAT_CNTDEL_S 0 -+#define PAS_IOB_DMA_TXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_TXCH_STAT_CNTDEL_S) &\ -+ PAS_IOB_DMA_TXCH_STAT_CNTDEL_M) -+#define PAS_IOB_DMA_RXCH_RESET(i) (0x1500 + (i)*4) -+#define PAS_IOB_DMA_RXCH_RESET_PCNT_M 0xffff0000 -+#define PAS_IOB_DMA_RXCH_RESET_PCNT_S 16 -+#define PAS_IOB_DMA_RXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_RXCH_RESET_PCNT_S) & \ -+ PAS_IOB_DMA_RXCH_RESET_PCNT_M) -+#define PAS_IOB_DMA_RXCH_RESET_PCNTRST 0x00000020 -+#define PAS_IOB_DMA_RXCH_RESET_DCNTRST 0x00000010 -+#define PAS_IOB_DMA_RXCH_RESET_TINTC 0x00000008 -+#define PAS_IOB_DMA_RXCH_RESET_DINTC 0x00000004 -+#define PAS_IOB_DMA_RXCH_RESET_SINTC 0x00000002 -+#define PAS_IOB_DMA_RXCH_RESET_PINTC 0x00000001 -+#define PAS_IOB_DMA_TXCH_RESET(i) (0x1600 + (i)*4) -+#define PAS_IOB_DMA_TXCH_RESET_PCNT_M 0xffff0000 -+#define PAS_IOB_DMA_TXCH_RESET_PCNT_S 16 -+#define PAS_IOB_DMA_TXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_TXCH_RESET_PCNT_S) & \ -+ PAS_IOB_DMA_TXCH_RESET_PCNT_M) -+#define PAS_IOB_DMA_TXCH_RESET_PCNTRST 0x00000020 -+#define PAS_IOB_DMA_TXCH_RESET_DCNTRST 0x00000010 -+#define PAS_IOB_DMA_TXCH_RESET_TINTC 0x00000008 -+#define PAS_IOB_DMA_TXCH_RESET_DINTC 0x00000004 -+#define PAS_IOB_DMA_TXCH_RESET_SINTC 0x00000002 -+#define PAS_IOB_DMA_TXCH_RESET_PINTC 0x00000001 -+ -+#define PAS_IOB_DMA_COM_TIMEOUTCFG 0x1700 -+#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M 0x00ffffff -+#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S 0 -+#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(x) (((x) << PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S) & \ -+ PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M) -+ -+/* Transmit descriptor fields */ -+#define XCT_MACTX_T 0x8000000000000000ull -+#define XCT_MACTX_ST 0x4000000000000000ull -+#define XCT_MACTX_NORES 0x0000000000000000ull -+#define XCT_MACTX_8BRES 0x1000000000000000ull -+#define XCT_MACTX_24BRES 0x2000000000000000ull -+#define XCT_MACTX_40BRES 0x3000000000000000ull -+#define XCT_MACTX_I 0x0800000000000000ull -+#define XCT_MACTX_O 0x0400000000000000ull -+#define XCT_MACTX_E 0x0200000000000000ull -+#define XCT_MACTX_VLAN_M 0x0180000000000000ull -+#define XCT_MACTX_VLAN_NOP 0x0000000000000000ull -+#define XCT_MACTX_VLAN_REMOVE 0x0080000000000000ull -+#define XCT_MACTX_VLAN_INSERT 0x0100000000000000ull -+#define XCT_MACTX_VLAN_REPLACE 0x0180000000000000ull -+#define XCT_MACTX_CRC_M 0x0060000000000000ull -+#define XCT_MACTX_CRC_NOP 0x0000000000000000ull -+#define XCT_MACTX_CRC_INSERT 0x0020000000000000ull -+#define XCT_MACTX_CRC_PAD 0x0040000000000000ull -+#define XCT_MACTX_CRC_REPLACE 0x0060000000000000ull -+#define XCT_MACTX_SS 0x0010000000000000ull -+#define XCT_MACTX_LLEN_M 0x00007fff00000000ull -+#define XCT_MACTX_LLEN_S 32ull -+#define XCT_MACTX_LLEN(x) ((((long)(x)) << XCT_MACTX_LLEN_S) & \ -+ XCT_MACTX_LLEN_M) -+#define XCT_MACTX_IPH_M 0x00000000f8000000ull -+#define XCT_MACTX_IPH_S 27ull -+#define XCT_MACTX_IPH(x) ((((long)(x)) << XCT_MACTX_IPH_S) & \ -+ XCT_MACTX_IPH_M) -+#define XCT_MACTX_IPO_M 0x0000000007c00000ull -+#define XCT_MACTX_IPO_S 22ull -+#define XCT_MACTX_IPO(x) ((((long)(x)) << XCT_MACTX_IPO_S) & \ -+ XCT_MACTX_IPO_M) -+#define XCT_MACTX_CSUM_M 0x0000000000000060ull -+#define XCT_MACTX_CSUM_NOP 0x0000000000000000ull -+#define XCT_MACTX_CSUM_TCP 0x0000000000000040ull -+#define XCT_MACTX_CSUM_UDP 0x0000000000000060ull -+#define XCT_MACTX_V6 0x0000000000000010ull -+#define XCT_MACTX_C 0x0000000000000004ull -+#define XCT_MACTX_AL2 0x0000000000000002ull -+ -+#define XCT_PTR_T 0x8000000000000000ull -+#define XCT_PTR_LEN_M 0x7ffff00000000000ull -+#define XCT_PTR_LEN_S 44 -+#define XCT_PTR_LEN(x) ((((long)(x)) << XCT_PTR_LEN_S) & \ -+ XCT_PTR_LEN_M) -+#define XCT_PTR_ADDR_M 0x00000fffffffffffull -+#define XCT_PTR_ADDR_S 0 -+#define XCT_PTR_ADDR(x) ((((long)(x)) << XCT_PTR_ADDR_S) & \ -+ XCT_PTR_ADDR_M) -+ -+/* Function descriptor fields */ -+#define XCT_FUN_T 0x8000000000000000ull -+#define XCT_FUN_ST 0x4000000000000000ull -+#define XCT_FUN_NORES 0x0000000000000000ull -+#define XCT_FUN_8BRES 0x1000000000000000ull -+#define XCT_FUN_24BRES 0x2000000000000000ull -+#define XCT_FUN_40BRES 0x3000000000000000ull -+#define XCT_FUN_I 0x0800000000000000ull -+#define XCT_FUN_O 0x0400000000000000ull -+#define XCT_FUN_E 0x0200000000000000ull -+#define XCT_FUN_FUN_S 54 -+#define XCT_FUN_FUN_M 0x01c0000000000000ull -+#define XCT_FUN_FUN(num) ((((long)(num)) << XCT_FUN_FUN_S) & \ -+ XCT_FUN_FUN_M) -+#define XCT_FUN_CRM_NOP 0x0000000000000000ull -+#define XCT_FUN_CRM_SIG 0x0008000000000000ull -+#define XCT_FUN_CRM_ENC 0x0010000000000000ull -+#define XCT_FUN_CRM_DEC 0x0018000000000000ull -+#define XCT_FUN_CRM_SIG_ENC 0x0020000000000000ull -+#define XCT_FUN_CRM_ENC_SIG 0x0028000000000000ull -+#define XCT_FUN_CRM_SIG_DEC 0x0030000000000000ull -+#define XCT_FUN_CRM_DEC_SIG 0x0038000000000000ull -+#define XCT_FUN_LLEN_M 0x0007ffff00000000ull -+#define XCT_FUN_LLEN_S 32ULL -+#define XCT_FUN_LLEN(x) ((((long)(x)) << XCT_FUN_LLEN_S) & \ -+ XCT_FUN_LLEN_M) -+#define XCT_FUN_SHL_M 0x00000000f8000000ull -+#define XCT_FUN_SHL_S 27ull -+#define XCT_FUN_SHL(x) ((((long)(x)) << XCT_FUN_SHL_S) & \ -+ XCT_FUN_SHL_M) -+#define XCT_FUN_CHL_M 0x0000000007c00000ull -+#define XCT_FUN_CHL_S 22ull -+#define XCT_FUN_CHL(x) ((((long)(x)) << XCT_FUN_CHL_S) & \ -+ XCT_FUN_CHL_M) -+#define XCT_FUN_HSZ_M 0x00000000003c0000ull -+#define XCT_FUN_HSZ_S 18ull -+#define XCT_FUN_HSZ(x) ((((long)(x)) << XCT_FUN_HSZ_S) & \ -+ XCT_FUN_HSZ_M) -+#define XCT_FUN_ALG_DES 0x0000000000000000ull -+#define XCT_FUN_ALG_3DES 0x0000000000008000ull -+#define XCT_FUN_ALG_AES 0x0000000000010000ull -+#define XCT_FUN_ALG_ARC 0x0000000000018000ull -+#define XCT_FUN_ALG_KASUMI 0x0000000000020000ull -+#define XCT_FUN_BCM_ECB 0x0000000000000000ull -+#define XCT_FUN_BCM_CBC 0x0000000000001000ull -+#define XCT_FUN_BCM_CFB 0x0000000000002000ull -+#define XCT_FUN_BCM_OFB 0x0000000000003000ull -+#define XCT_FUN_BCM_CNT 0x0000000000003800ull -+#define XCT_FUN_BCM_KAS_F8 0x0000000000002800ull -+#define XCT_FUN_BCM_KAS_F9 0x0000000000001800ull -+#define XCT_FUN_BCP_NO_PAD 0x0000000000000000ull -+#define XCT_FUN_BCP_ZRO 0x0000000000000200ull -+#define XCT_FUN_BCP_PL 0x0000000000000400ull -+#define XCT_FUN_BCP_INCR 0x0000000000000600ull -+#define XCT_FUN_SIG_MD5 (0ull << 4) -+#define XCT_FUN_SIG_SHA1 (2ull << 4) -+#define XCT_FUN_SIG_HMAC_MD5 (8ull << 4) -+#define XCT_FUN_SIG_HMAC_SHA1 (10ull << 4) -+#define XCT_FUN_A 0x0000000000000008ull -+#define XCT_FUN_C 0x0000000000000004ull -+#define XCT_FUN_AL2 0x0000000000000002ull -+#define XCT_FUN_SE 0x0000000000000001ull -+ -+#define XCT_FUN_SRC_PTR(len, addr) (XCT_PTR_LEN(len) | XCT_PTR_ADDR(addr)) -+#define XCT_FUN_DST_PTR(len, addr) (XCT_FUN_SRC_PTR(len, addr) | \ -+ 0x8000000000000000ull) -+ -+#define XCT_CTRL_HDR_FUN_NUM_M 0x01c0000000000000ull -+#define XCT_CTRL_HDR_FUN_NUM_S 54 -+#define XCT_CTRL_HDR_LEN_M 0x0007ffff00000000ull -+#define XCT_CTRL_HDR_LEN_S 32 -+#define XCT_CTRL_HDR_REG_M 0x00000000000000ffull -+#define XCT_CTRL_HDR_REG_S 0 -+ -+#define XCT_CTRL_HDR(funcN,len,reg) (0x9400000000000000ull | \ -+ ((((long)(funcN)) << XCT_CTRL_HDR_FUN_NUM_S) \ -+ & XCT_CTRL_HDR_FUN_NUM_M) | \ -+ ((((long)(len)) << \ -+ XCT_CTRL_HDR_LEN_S) & XCT_CTRL_HDR_LEN_M) | \ -+ ((((long)(reg)) << \ -+ XCT_CTRL_HDR_REG_S) & XCT_CTRL_HDR_REG_M)) -+ -+/* Function config command options */ -+#define DMA_CALGO_DES 0x00 -+#define DMA_CALGO_3DES 0x01 -+#define DMA_CALGO_AES 0x02 -+#define DMA_CALGO_ARC 0x03 -+ -+#define DMA_FN_CIV0 0x02 -+#define DMA_FN_CIV1 0x03 -+#define DMA_FN_HKEY0 0x0a -+ -+#define XCT_PTR_ADDR_LEN(ptr) ((ptr) & XCT_PTR_ADDR_M), \ -+ (((ptr) & XCT_PTR_LEN_M) >> XCT_PTR_LEN_S) -+ -+#endif /* PASEMI_FNU_H */ -diff -Nur linux-2.6.36.orig/crypto/ocf/random.c linux-2.6.36/crypto/ocf/random.c ---- linux-2.6.36.orig/crypto/ocf/random.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/random.c 2010-11-09 20:28:12.652495434 +0100 -@@ -0,0 +1,322 @@ -+/* -+ * A system independant way of adding entropy to the kernels pool -+ * this way the drivers can focus on the real work and we can take -+ * care of pushing it to the appropriate place in the kernel. -+ * -+ * This should be fast and callable from timers/interrupts -+ * -+ * Written by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * ALTERNATIVELY, provided that this notice is retained in full, this product -+ * may be distributed under the terms of the GNU General Public License (GPL), -+ * in which case the provisions of the GPL apply INSTEAD OF those given above. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ */ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#ifdef CONFIG_OCF_FIPS -+#include "rndtest.h" -+#endif -+ -+#ifndef HAS_RANDOM_INPUT_WAIT -+#error "Please do not enable OCF_RANDOMHARVEST unless you have applied patches" -+#endif -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) -+#include -+#define kill_proc(p,s,v) send_sig(s,find_task_by_vpid(p),0) -+#endif -+ -+/* -+ * a hack to access the debug levels from the crypto driver -+ */ -+extern int crypto_debug; -+#define debug crypto_debug -+ -+/* -+ * a list of all registered random providers -+ */ -+static LIST_HEAD(random_ops); -+static int started = 0; -+static int initted = 0; -+ -+struct random_op { -+ struct list_head random_list; -+ u_int32_t driverid; -+ int (*read_random)(void *arg, u_int32_t *buf, int len); -+ void *arg; -+}; -+ -+static int random_proc(void *arg); -+ -+static pid_t randomproc = (pid_t) -1; -+static spinlock_t random_lock; -+ -+/* -+ * just init the spin locks -+ */ -+static int -+crypto_random_init(void) -+{ -+ spin_lock_init(&random_lock); -+ initted = 1; -+ return(0); -+} -+ -+/* -+ * Add the given random reader to our list (if not present) -+ * and start the thread (if not already started) -+ * -+ * we have to assume that driver id is ok for now -+ */ -+int -+crypto_rregister( -+ u_int32_t driverid, -+ int (*read_random)(void *arg, u_int32_t *buf, int len), -+ void *arg) -+{ -+ unsigned long flags; -+ int ret = 0; -+ struct random_op *rops, *tmp; -+ -+ dprintk("%s,%d: %s(0x%x, %p, %p)\n", __FILE__, __LINE__, -+ __FUNCTION__, driverid, read_random, arg); -+ -+ if (!initted) -+ crypto_random_init(); -+ -+#if 0 -+ struct cryptocap *cap; -+ -+ cap = crypto_checkdriver(driverid); -+ if (!cap) -+ return EINVAL; -+#endif -+ -+ list_for_each_entry_safe(rops, tmp, &random_ops, random_list) { -+ if (rops->driverid == driverid && rops->read_random == read_random) -+ return EEXIST; -+ } -+ -+ rops = (struct random_op *) kmalloc(sizeof(*rops), GFP_KERNEL); -+ if (!rops) -+ return ENOMEM; -+ -+ rops->driverid = driverid; -+ rops->read_random = read_random; -+ rops->arg = arg; -+ -+ spin_lock_irqsave(&random_lock, flags); -+ list_add_tail(&rops->random_list, &random_ops); -+ if (!started) { -+ randomproc = kernel_thread(random_proc, NULL, CLONE_FS|CLONE_FILES); -+ if (randomproc < 0) { -+ ret = randomproc; -+ printk("crypto: crypto_rregister cannot start random thread; " -+ "error %d", ret); -+ } else -+ started = 1; -+ } -+ spin_unlock_irqrestore(&random_lock, flags); -+ -+ return ret; -+} -+EXPORT_SYMBOL(crypto_rregister); -+ -+int -+crypto_runregister_all(u_int32_t driverid) -+{ -+ struct random_op *rops, *tmp; -+ unsigned long flags; -+ -+ dprintk("%s,%d: %s(0x%x)\n", __FILE__, __LINE__, __FUNCTION__, driverid); -+ -+ list_for_each_entry_safe(rops, tmp, &random_ops, random_list) { -+ if (rops->driverid == driverid) { -+ list_del(&rops->random_list); -+ kfree(rops); -+ } -+ } -+ -+ spin_lock_irqsave(&random_lock, flags); -+ if (list_empty(&random_ops) && started) -+ kill_proc(randomproc, SIGKILL, 1); -+ spin_unlock_irqrestore(&random_lock, flags); -+ return(0); -+} -+EXPORT_SYMBOL(crypto_runregister_all); -+ -+/* -+ * while we can add entropy to random.c continue to read random data from -+ * the drivers and push it to random. -+ */ -+static int -+random_proc(void *arg) -+{ -+ int n; -+ int wantcnt; -+ int bufcnt = 0; -+ int retval = 0; -+ int *buf = NULL; -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ daemonize(); -+ spin_lock_irq(¤t->sigmask_lock); -+ sigemptyset(¤t->blocked); -+ recalc_sigpending(current); -+ spin_unlock_irq(¤t->sigmask_lock); -+ sprintf(current->comm, "ocf-random"); -+#else -+ daemonize("ocf-random"); -+ allow_signal(SIGKILL); -+#endif -+ -+ (void) get_fs(); -+ set_fs(get_ds()); -+ -+#ifdef CONFIG_OCF_FIPS -+#define NUM_INT (RNDTEST_NBYTES/sizeof(int)) -+#else -+#define NUM_INT 32 -+#endif -+ -+ /* -+ * some devices can transferr their RNG data direct into memory, -+ * so make sure it is device friendly -+ */ -+ buf = kmalloc(NUM_INT * sizeof(int), GFP_DMA); -+ if (NULL == buf) { -+ printk("crypto: RNG could not allocate memory\n"); -+ retval = -ENOMEM; -+ goto bad_alloc; -+ } -+ -+ wantcnt = NUM_INT; /* start by adding some entropy */ -+ -+ /* -+ * its possible due to errors or driver removal that we no longer -+ * have anything to do, if so exit or we will consume all the CPU -+ * doing nothing -+ */ -+ while (!list_empty(&random_ops)) { -+ struct random_op *rops, *tmp; -+ -+#ifdef CONFIG_OCF_FIPS -+ if (wantcnt) -+ wantcnt = NUM_INT; /* FIPs mode can do 20000 bits or none */ -+#endif -+ -+ /* see if we can get enough entropy to make the world -+ * a better place. -+ */ -+ while (bufcnt < wantcnt && bufcnt < NUM_INT) { -+ list_for_each_entry_safe(rops, tmp, &random_ops, random_list) { -+ -+ n = (*rops->read_random)(rops->arg, &buf[bufcnt], -+ NUM_INT - bufcnt); -+ -+ /* on failure remove the random number generator */ -+ if (n == -1) { -+ list_del(&rops->random_list); -+ printk("crypto: RNG (driverid=0x%x) failed, disabling\n", -+ rops->driverid); -+ kfree(rops); -+ } else if (n > 0) -+ bufcnt += n; -+ } -+ /* give up CPU for a bit, just in case as this is a loop */ -+ schedule(); -+ } -+ -+ -+#ifdef CONFIG_OCF_FIPS -+ if (bufcnt > 0 && rndtest_buf((unsigned char *) &buf[0])) { -+ dprintk("crypto: buffer had fips errors, discarding\n"); -+ bufcnt = 0; -+ } -+#endif -+ -+ /* -+ * if we have a certified buffer, we can send some data -+ * to /dev/random and move along -+ */ -+ if (bufcnt > 0) { -+ /* add what we have */ -+ random_input_words(buf, bufcnt, bufcnt*sizeof(int)*8); -+ bufcnt = 0; -+ } -+ -+ /* give up CPU for a bit so we don't hog while filling */ -+ schedule(); -+ -+ /* wait for needing more */ -+ wantcnt = random_input_wait(); -+ -+ if (wantcnt <= 0) -+ wantcnt = 0; /* try to get some info again */ -+ else -+ /* round up to one word or we can loop forever */ -+ wantcnt = (wantcnt + (sizeof(int)*8)) / (sizeof(int)*8); -+ if (wantcnt > NUM_INT) { -+ wantcnt = NUM_INT; -+ } -+ -+ if (signal_pending(current)) { -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ spin_lock_irq(¤t->sigmask_lock); -+#endif -+ flush_signals(current); -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ spin_unlock_irq(¤t->sigmask_lock); -+#endif -+ } -+ } -+ -+ kfree(buf); -+ -+bad_alloc: -+ spin_lock_irq(&random_lock); -+ randomproc = (pid_t) -1; -+ started = 0; -+ spin_unlock_irq(&random_lock); -+ -+ return retval; -+} -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/README linux-2.6.36/crypto/ocf/README ---- linux-2.6.36.orig/crypto/ocf/README 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/README 2010-11-09 20:28:12.681240186 +0100 -@@ -0,0 +1,167 @@ -+README - ocf-linux-20100325 -+--------------------------- -+ -+This README provides instructions for getting ocf-linux compiled and -+operating in a generic linux environment. For other information you -+might like to visit the home page for this project: -+ -+ http://ocf-linux.sourceforge.net/ -+ -+Adding OCF to linux -+------------------- -+ -+ Not much in this file for now, just some notes. I usually build -+ the ocf support as modules but it can be built into the kernel as -+ well. To use it: -+ -+ * mknod /dev/crypto c 10 70 -+ -+ * to add OCF to your kernel source, you have two options. Apply -+ the kernel specific patch: -+ -+ cd linux-2.4*; gunzip < ocf-linux-24-XXXXXXXX.patch.gz | patch -p1 -+ cd linux-2.6*; gunzip < ocf-linux-26-XXXXXXXX.patch.gz | patch -p1 -+ -+ if you do one of the above, then you can proceed to the next step, -+ or you can do the above process by hand with using the patches against -+ linux-2.4.35 and 2.6.33 to include the ocf code under crypto/ocf. -+ Here's how to add it: -+ -+ for 2.4.35 (and later) -+ -+ cd linux-2.4.35/crypto -+ tar xvzf ocf-linux.tar.gz -+ cd .. -+ patch -p1 < crypto/ocf/patches/linux-2.4.35-ocf.patch -+ -+ for 2.6.23 (and later), find the kernel patch specific (or nearest) -+ to your kernel versions and then: -+ -+ cd linux-2.6.NN/crypto -+ tar xvzf ocf-linux.tar.gz -+ cd .. -+ patch -p1 < crypto/ocf/patches/linux-2.6.NN-ocf.patch -+ -+ It should be easy to take this patch and apply it to other more -+ recent versions of the kernels. The same patches should also work -+ relatively easily on kernels as old as 2.6.11 and 2.4.18. -+ -+ * under 2.4 if you are on a non-x86 platform, you may need to: -+ -+ cp linux-2.X.x/include/asm-i386/kmap_types.h linux-2.X.x/include/asm-YYY -+ -+ so that you can build the kernel crypto support needed for the cryptosoft -+ driver. -+ -+ * For simplicity you should enable all the crypto support in your kernel -+ except for the test driver. Likewise for the OCF options. Do not -+ enable OCF crypto drivers for HW that you do not have (for example -+ ixp4xx will not compile on non-Xscale systems). -+ -+ * make sure that cryptodev.h (from ocf-linux.tar.gz) is installed as -+ crypto/cryptodev.h in an include directory that is used for building -+ applications for your platform. For example on a host system that -+ might be: -+ -+ /usr/include/crypto/cryptodev.h -+ -+ * patch your openssl-0.9.8n code with the openssl-0.9.8n.patch. -+ (NOTE: there is no longer a need to patch ssh). The patch is against: -+ openssl-0_9_8e -+ -+ If you need a patch for an older version of openssl, you should look -+ to older OCF releases. This patch is unlikely to work on older -+ openssl versions. -+ -+ openssl-0.9.8n.patch -+ - enables --with-cryptodev for non BSD systems -+ - adds -cpu option to openssl speed for calculating CPU load -+ under linux -+ - fixes null pointer in openssl speed multi thread output. -+ - fixes test keys to work with linux crypto's more stringent -+ key checking. -+ - adds MD5/SHA acceleration (Ronen Shitrit), only enabled -+ with the --with-cryptodev-digests option -+ - fixes bug in engine code caching. -+ -+ * build crypto-tools-XXXXXXXX.tar.gz if you want to try some of the BSD -+ tools for testing OCF (ie., cryptotest). -+ -+How to load the OCF drivers -+--------------------------- -+ -+ First insert the base modules: -+ -+ insmod ocf -+ insmod cryptodev -+ -+ You can then install the software OCF driver with: -+ -+ insmod cryptosoft -+ -+ and one or more of the OCF HW drivers with: -+ -+ insmod safe -+ insmod hifn7751 -+ insmod ixp4xx -+ ... -+ -+ all the drivers take a debug option to enable verbose debug so that -+ you can see what is going on. For debug you load them as: -+ -+ insmod ocf crypto_debug=1 -+ insmod cryptodev cryptodev_debug=1 -+ insmod cryptosoft swcr_debug=1 -+ -+ You may load more than one OCF crypto driver but then there is no guarantee -+ as to which will be used. -+ -+ You can also enable debug at run time on 2.6 systems with the following: -+ -+ echo 1 > /sys/module/ocf/parameters/crypto_debug -+ echo 1 > /sys/module/cryptodev/parameters/cryptodev_debug -+ echo 1 > /sys/module/cryptosoft/parameters/swcr_debug -+ echo 1 > /sys/module/hifn7751/parameters/hifn_debug -+ echo 1 > /sys/module/safe/parameters/safe_debug -+ echo 1 > /sys/module/ixp4xx/parameters/ixp_debug -+ ... -+ -+Testing the OCF support -+----------------------- -+ -+ run "cryptotest", it should do a short test for a couple of -+ des packets. If it does everything is working. -+ -+ If this works, then ssh will use the driver when invoked as: -+ -+ ssh -c 3des username@host -+ -+ to see for sure that it is operating, enable debug as defined above. -+ -+ To get a better idea of performance run: -+ -+ cryptotest 100 4096 -+ -+ There are more options to cryptotest, see the help. -+ -+ It is also possible to use openssl to test the speed of the crypto -+ drivers. -+ -+ openssl speed -evp des -engine cryptodev -elapsed -+ openssl speed -evp des3 -engine cryptodev -elapsed -+ openssl speed -evp aes128 -engine cryptodev -elapsed -+ -+ and multiple threads (10) with: -+ -+ openssl speed -evp des -engine cryptodev -elapsed -multi 10 -+ openssl speed -evp des3 -engine cryptodev -elapsed -multi 10 -+ openssl speed -evp aes128 -engine cryptodev -elapsed -multi 10 -+ -+ for public key testing you can try: -+ -+ cryptokeytest -+ openssl speed -engine cryptodev rsa -elapsed -+ openssl speed -engine cryptodev dsa -elapsed -+ -+David McCullough -+david_mccullough@mcafee.com -diff -Nur linux-2.6.36.orig/crypto/ocf/rndtest.c linux-2.6.36/crypto/ocf/rndtest.c ---- linux-2.6.36.orig/crypto/ocf/rndtest.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/rndtest.c 2010-11-09 20:28:12.722495563 +0100 -@@ -0,0 +1,300 @@ -+/* $OpenBSD$ */ -+ -+/* -+ * OCF/Linux port done by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * The license and original author are listed below. -+ * -+ * Copyright (c) 2002 Jason L. Wright (jason@thought.net) -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. All advertising materials mentioning features or use of this software -+ * must display the following acknowledgement: -+ * This product includes software developed by Jason L. Wright -+ * 4. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "rndtest.h" -+ -+static struct rndtest_stats rndstats; -+ -+static void rndtest_test(struct rndtest_state *); -+ -+/* The tests themselves */ -+static int rndtest_monobit(struct rndtest_state *); -+static int rndtest_runs(struct rndtest_state *); -+static int rndtest_longruns(struct rndtest_state *); -+static int rndtest_chi_4(struct rndtest_state *); -+ -+static int rndtest_runs_check(struct rndtest_state *, int, int *); -+static void rndtest_runs_record(struct rndtest_state *, int, int *); -+ -+static const struct rndtest_testfunc { -+ int (*test)(struct rndtest_state *); -+} rndtest_funcs[] = { -+ { rndtest_monobit }, -+ { rndtest_runs }, -+ { rndtest_chi_4 }, -+ { rndtest_longruns }, -+}; -+ -+#define RNDTEST_NTESTS (sizeof(rndtest_funcs)/sizeof(rndtest_funcs[0])) -+ -+static void -+rndtest_test(struct rndtest_state *rsp) -+{ -+ int i, rv = 0; -+ -+ rndstats.rst_tests++; -+ for (i = 0; i < RNDTEST_NTESTS; i++) -+ rv |= (*rndtest_funcs[i].test)(rsp); -+ rsp->rs_discard = (rv != 0); -+} -+ -+ -+extern int crypto_debug; -+#define rndtest_verbose 2 -+#define rndtest_report(rsp, failure, fmt, a...) \ -+ { if (failure || crypto_debug) { printk("rng_test: " fmt "\n", a); } else; } -+ -+#define RNDTEST_MONOBIT_MINONES 9725 -+#define RNDTEST_MONOBIT_MAXONES 10275 -+ -+static int -+rndtest_monobit(struct rndtest_state *rsp) -+{ -+ int i, ones = 0, j; -+ u_int8_t r; -+ -+ for (i = 0; i < RNDTEST_NBYTES; i++) { -+ r = rsp->rs_buf[i]; -+ for (j = 0; j < 8; j++, r <<= 1) -+ if (r & 0x80) -+ ones++; -+ } -+ if (ones > RNDTEST_MONOBIT_MINONES && -+ ones < RNDTEST_MONOBIT_MAXONES) { -+ if (rndtest_verbose > 1) -+ rndtest_report(rsp, 0, "monobit pass (%d < %d < %d)", -+ RNDTEST_MONOBIT_MINONES, ones, -+ RNDTEST_MONOBIT_MAXONES); -+ return (0); -+ } else { -+ if (rndtest_verbose) -+ rndtest_report(rsp, 1, -+ "monobit failed (%d ones)", ones); -+ rndstats.rst_monobit++; -+ return (-1); -+ } -+} -+ -+#define RNDTEST_RUNS_NINTERVAL 6 -+ -+static const struct rndtest_runs_tabs { -+ u_int16_t min, max; -+} rndtest_runs_tab[] = { -+ { 2343, 2657 }, -+ { 1135, 1365 }, -+ { 542, 708 }, -+ { 251, 373 }, -+ { 111, 201 }, -+ { 111, 201 }, -+}; -+ -+static int -+rndtest_runs(struct rndtest_state *rsp) -+{ -+ int i, j, ones, zeros, rv = 0; -+ int onei[RNDTEST_RUNS_NINTERVAL], zeroi[RNDTEST_RUNS_NINTERVAL]; -+ u_int8_t c; -+ -+ bzero(onei, sizeof(onei)); -+ bzero(zeroi, sizeof(zeroi)); -+ ones = zeros = 0; -+ for (i = 0; i < RNDTEST_NBYTES; i++) { -+ c = rsp->rs_buf[i]; -+ for (j = 0; j < 8; j++, c <<= 1) { -+ if (c & 0x80) { -+ ones++; -+ rndtest_runs_record(rsp, zeros, zeroi); -+ zeros = 0; -+ } else { -+ zeros++; -+ rndtest_runs_record(rsp, ones, onei); -+ ones = 0; -+ } -+ } -+ } -+ rndtest_runs_record(rsp, ones, onei); -+ rndtest_runs_record(rsp, zeros, zeroi); -+ -+ rv |= rndtest_runs_check(rsp, 0, zeroi); -+ rv |= rndtest_runs_check(rsp, 1, onei); -+ -+ if (rv) -+ rndstats.rst_runs++; -+ -+ return (rv); -+} -+ -+static void -+rndtest_runs_record(struct rndtest_state *rsp, int len, int *intrv) -+{ -+ if (len == 0) -+ return; -+ if (len > RNDTEST_RUNS_NINTERVAL) -+ len = RNDTEST_RUNS_NINTERVAL; -+ len -= 1; -+ intrv[len]++; -+} -+ -+static int -+rndtest_runs_check(struct rndtest_state *rsp, int val, int *src) -+{ -+ int i, rv = 0; -+ -+ for (i = 0; i < RNDTEST_RUNS_NINTERVAL; i++) { -+ if (src[i] < rndtest_runs_tab[i].min || -+ src[i] > rndtest_runs_tab[i].max) { -+ rndtest_report(rsp, 1, -+ "%s interval %d failed (%d, %d-%d)", -+ val ? "ones" : "zeros", -+ i + 1, src[i], rndtest_runs_tab[i].min, -+ rndtest_runs_tab[i].max); -+ rv = -1; -+ } else { -+ rndtest_report(rsp, 0, -+ "runs pass %s interval %d (%d < %d < %d)", -+ val ? "ones" : "zeros", -+ i + 1, rndtest_runs_tab[i].min, src[i], -+ rndtest_runs_tab[i].max); -+ } -+ } -+ return (rv); -+} -+ -+static int -+rndtest_longruns(struct rndtest_state *rsp) -+{ -+ int i, j, ones = 0, zeros = 0, maxones = 0, maxzeros = 0; -+ u_int8_t c; -+ -+ for (i = 0; i < RNDTEST_NBYTES; i++) { -+ c = rsp->rs_buf[i]; -+ for (j = 0; j < 8; j++, c <<= 1) { -+ if (c & 0x80) { -+ zeros = 0; -+ ones++; -+ if (ones > maxones) -+ maxones = ones; -+ } else { -+ ones = 0; -+ zeros++; -+ if (zeros > maxzeros) -+ maxzeros = zeros; -+ } -+ } -+ } -+ -+ if (maxones < 26 && maxzeros < 26) { -+ rndtest_report(rsp, 0, "longruns pass (%d ones, %d zeros)", -+ maxones, maxzeros); -+ return (0); -+ } else { -+ rndtest_report(rsp, 1, "longruns fail (%d ones, %d zeros)", -+ maxones, maxzeros); -+ rndstats.rst_longruns++; -+ return (-1); -+ } -+} -+ -+/* -+ * chi^2 test over 4 bits: (this is called the poker test in FIPS 140-2, -+ * but it is really the chi^2 test over 4 bits (the poker test as described -+ * by Knuth vol 2 is something different, and I take him as authoritative -+ * on nomenclature over NIST). -+ */ -+#define RNDTEST_CHI4_K 16 -+#define RNDTEST_CHI4_K_MASK (RNDTEST_CHI4_K - 1) -+ -+/* -+ * The unnormalized values are used so that we don't have to worry about -+ * fractional precision. The "real" value is found by: -+ * (V - 1562500) * (16 / 5000) = Vn (where V is the unnormalized value) -+ */ -+#define RNDTEST_CHI4_VMIN 1563181 /* 2.1792 */ -+#define RNDTEST_CHI4_VMAX 1576929 /* 46.1728 */ -+ -+static int -+rndtest_chi_4(struct rndtest_state *rsp) -+{ -+ unsigned int freq[RNDTEST_CHI4_K], i, sum; -+ -+ for (i = 0; i < RNDTEST_CHI4_K; i++) -+ freq[i] = 0; -+ -+ /* Get number of occurances of each 4 bit pattern */ -+ for (i = 0; i < RNDTEST_NBYTES; i++) { -+ freq[(rsp->rs_buf[i] >> 4) & RNDTEST_CHI4_K_MASK]++; -+ freq[(rsp->rs_buf[i] >> 0) & RNDTEST_CHI4_K_MASK]++; -+ } -+ -+ for (i = 0, sum = 0; i < RNDTEST_CHI4_K; i++) -+ sum += freq[i] * freq[i]; -+ -+ if (sum >= 1563181 && sum <= 1576929) { -+ rndtest_report(rsp, 0, "chi^2(4): pass (sum %u)", sum); -+ return (0); -+ } else { -+ rndtest_report(rsp, 1, "chi^2(4): failed (sum %u)", sum); -+ rndstats.rst_chi++; -+ return (-1); -+ } -+} -+ -+int -+rndtest_buf(unsigned char *buf) -+{ -+ struct rndtest_state rsp; -+ -+ memset(&rsp, 0, sizeof(rsp)); -+ rsp.rs_buf = buf; -+ rndtest_test(&rsp); -+ return(rsp.rs_discard); -+} -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/rndtest.h linux-2.6.36/crypto/ocf/rndtest.h ---- linux-2.6.36.orig/crypto/ocf/rndtest.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/rndtest.h 2010-11-09 20:28:12.762495556 +0100 -@@ -0,0 +1,54 @@ -+/* $FreeBSD: src/sys/dev/rndtest/rndtest.h,v 1.1 2003/03/11 22:54:44 sam Exp $ */ -+/* $OpenBSD$ */ -+ -+/* -+ * Copyright (c) 2002 Jason L. Wright (jason@thought.net) -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. All advertising materials mentioning features or use of this software -+ * must display the following acknowledgement: -+ * This product includes software developed by Jason L. Wright -+ * 4. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/* Some of the tests depend on these values */ -+#define RNDTEST_NBYTES 2500 -+#define RNDTEST_NBITS (8 * RNDTEST_NBYTES) -+ -+struct rndtest_state { -+ int rs_discard; /* discard/accept random data */ -+ u_int8_t *rs_buf; -+}; -+ -+struct rndtest_stats { -+ u_int32_t rst_discard; /* number of bytes discarded */ -+ u_int32_t rst_tests; /* number of test runs */ -+ u_int32_t rst_monobit; /* monobit test failures */ -+ u_int32_t rst_runs; /* 0/1 runs failures */ -+ u_int32_t rst_longruns; /* longruns failures */ -+ u_int32_t rst_chi; /* chi^2 failures */ -+}; -+ -+extern int rndtest_buf(unsigned char *buf); -diff -Nur linux-2.6.36.orig/crypto/ocf/safe/Makefile linux-2.6.36/crypto/ocf/safe/Makefile ---- linux-2.6.36.orig/crypto/ocf/safe/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/safe/Makefile 2010-11-09 20:28:12.805576889 +0100 -@@ -0,0 +1,12 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+obj-$(CONFIG_OCF_SAFE) += safe.o -+ -+obj ?= . -+EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/safe/md5.c linux-2.6.36/crypto/ocf/safe/md5.c ---- linux-2.6.36.orig/crypto/ocf/safe/md5.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/safe/md5.c 2010-11-09 20:28:12.842495449 +0100 -@@ -0,0 +1,308 @@ -+/* $KAME: md5.c,v 1.5 2000/11/08 06:13:08 itojun Exp $ */ -+/* -+ * Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. Neither the name of the project nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ */ -+ -+#if 0 -+#include -+__FBSDID("$FreeBSD: src/sys/crypto/md5.c,v 1.9 2004/01/27 19:49:19 des Exp $"); -+ -+#include -+#include -+#include -+#include -+#include -+#endif -+ -+#define SHIFT(X, s) (((X) << (s)) | ((X) >> (32 - (s)))) -+ -+#define F(X, Y, Z) (((X) & (Y)) | ((~X) & (Z))) -+#define G(X, Y, Z) (((X) & (Z)) | ((Y) & (~Z))) -+#define H(X, Y, Z) ((X) ^ (Y) ^ (Z)) -+#define I(X, Y, Z) ((Y) ^ ((X) | (~Z))) -+ -+#define ROUND1(a, b, c, d, k, s, i) { \ -+ (a) = (a) + F((b), (c), (d)) + X[(k)] + T[(i)]; \ -+ (a) = SHIFT((a), (s)); \ -+ (a) = (b) + (a); \ -+} -+ -+#define ROUND2(a, b, c, d, k, s, i) { \ -+ (a) = (a) + G((b), (c), (d)) + X[(k)] + T[(i)]; \ -+ (a) = SHIFT((a), (s)); \ -+ (a) = (b) + (a); \ -+} -+ -+#define ROUND3(a, b, c, d, k, s, i) { \ -+ (a) = (a) + H((b), (c), (d)) + X[(k)] + T[(i)]; \ -+ (a) = SHIFT((a), (s)); \ -+ (a) = (b) + (a); \ -+} -+ -+#define ROUND4(a, b, c, d, k, s, i) { \ -+ (a) = (a) + I((b), (c), (d)) + X[(k)] + T[(i)]; \ -+ (a) = SHIFT((a), (s)); \ -+ (a) = (b) + (a); \ -+} -+ -+#define Sa 7 -+#define Sb 12 -+#define Sc 17 -+#define Sd 22 -+ -+#define Se 5 -+#define Sf 9 -+#define Sg 14 -+#define Sh 20 -+ -+#define Si 4 -+#define Sj 11 -+#define Sk 16 -+#define Sl 23 -+ -+#define Sm 6 -+#define Sn 10 -+#define So 15 -+#define Sp 21 -+ -+#define MD5_A0 0x67452301 -+#define MD5_B0 0xefcdab89 -+#define MD5_C0 0x98badcfe -+#define MD5_D0 0x10325476 -+ -+/* Integer part of 4294967296 times abs(sin(i)), where i is in radians. */ -+static const u_int32_t T[65] = { -+ 0, -+ 0xd76aa478, 0xe8c7b756, 0x242070db, 0xc1bdceee, -+ 0xf57c0faf, 0x4787c62a, 0xa8304613, 0xfd469501, -+ 0x698098d8, 0x8b44f7af, 0xffff5bb1, 0x895cd7be, -+ 0x6b901122, 0xfd987193, 0xa679438e, 0x49b40821, -+ -+ 0xf61e2562, 0xc040b340, 0x265e5a51, 0xe9b6c7aa, -+ 0xd62f105d, 0x2441453, 0xd8a1e681, 0xe7d3fbc8, -+ 0x21e1cde6, 0xc33707d6, 0xf4d50d87, 0x455a14ed, -+ 0xa9e3e905, 0xfcefa3f8, 0x676f02d9, 0x8d2a4c8a, -+ -+ 0xfffa3942, 0x8771f681, 0x6d9d6122, 0xfde5380c, -+ 0xa4beea44, 0x4bdecfa9, 0xf6bb4b60, 0xbebfbc70, -+ 0x289b7ec6, 0xeaa127fa, 0xd4ef3085, 0x4881d05, -+ 0xd9d4d039, 0xe6db99e5, 0x1fa27cf8, 0xc4ac5665, -+ -+ 0xf4292244, 0x432aff97, 0xab9423a7, 0xfc93a039, -+ 0x655b59c3, 0x8f0ccc92, 0xffeff47d, 0x85845dd1, -+ 0x6fa87e4f, 0xfe2ce6e0, 0xa3014314, 0x4e0811a1, -+ 0xf7537e82, 0xbd3af235, 0x2ad7d2bb, 0xeb86d391, -+}; -+ -+static const u_int8_t md5_paddat[MD5_BUFLEN] = { -+ 0x80, 0, 0, 0, 0, 0, 0, 0, -+ 0, 0, 0, 0, 0, 0, 0, 0, -+ 0, 0, 0, 0, 0, 0, 0, 0, -+ 0, 0, 0, 0, 0, 0, 0, 0, -+ 0, 0, 0, 0, 0, 0, 0, 0, -+ 0, 0, 0, 0, 0, 0, 0, 0, -+ 0, 0, 0, 0, 0, 0, 0, 0, -+ 0, 0, 0, 0, 0, 0, 0, 0, -+}; -+ -+static void md5_calc(u_int8_t *, md5_ctxt *); -+ -+void md5_init(ctxt) -+ md5_ctxt *ctxt; -+{ -+ ctxt->md5_n = 0; -+ ctxt->md5_i = 0; -+ ctxt->md5_sta = MD5_A0; -+ ctxt->md5_stb = MD5_B0; -+ ctxt->md5_stc = MD5_C0; -+ ctxt->md5_std = MD5_D0; -+ bzero(ctxt->md5_buf, sizeof(ctxt->md5_buf)); -+} -+ -+void md5_loop(ctxt, input, len) -+ md5_ctxt *ctxt; -+ u_int8_t *input; -+ u_int len; /* number of bytes */ -+{ -+ u_int gap, i; -+ -+ ctxt->md5_n += len * 8; /* byte to bit */ -+ gap = MD5_BUFLEN - ctxt->md5_i; -+ -+ if (len >= gap) { -+ bcopy((void *)input, (void *)(ctxt->md5_buf + ctxt->md5_i), -+ gap); -+ md5_calc(ctxt->md5_buf, ctxt); -+ -+ for (i = gap; i + MD5_BUFLEN <= len; i += MD5_BUFLEN) { -+ md5_calc((u_int8_t *)(input + i), ctxt); -+ } -+ -+ ctxt->md5_i = len - i; -+ bcopy((void *)(input + i), (void *)ctxt->md5_buf, ctxt->md5_i); -+ } else { -+ bcopy((void *)input, (void *)(ctxt->md5_buf + ctxt->md5_i), -+ len); -+ ctxt->md5_i += len; -+ } -+} -+ -+void md5_pad(ctxt) -+ md5_ctxt *ctxt; -+{ -+ u_int gap; -+ -+ /* Don't count up padding. Keep md5_n. */ -+ gap = MD5_BUFLEN - ctxt->md5_i; -+ if (gap > 8) { -+ bcopy(md5_paddat, -+ (void *)(ctxt->md5_buf + ctxt->md5_i), -+ gap - sizeof(ctxt->md5_n)); -+ } else { -+ /* including gap == 8 */ -+ bcopy(md5_paddat, (void *)(ctxt->md5_buf + ctxt->md5_i), -+ gap); -+ md5_calc(ctxt->md5_buf, ctxt); -+ bcopy((md5_paddat + gap), -+ (void *)ctxt->md5_buf, -+ MD5_BUFLEN - sizeof(ctxt->md5_n)); -+ } -+ -+ /* 8 byte word */ -+#if BYTE_ORDER == LITTLE_ENDIAN -+ bcopy(&ctxt->md5_n8[0], &ctxt->md5_buf[56], 8); -+#endif -+#if BYTE_ORDER == BIG_ENDIAN -+ ctxt->md5_buf[56] = ctxt->md5_n8[7]; -+ ctxt->md5_buf[57] = ctxt->md5_n8[6]; -+ ctxt->md5_buf[58] = ctxt->md5_n8[5]; -+ ctxt->md5_buf[59] = ctxt->md5_n8[4]; -+ ctxt->md5_buf[60] = ctxt->md5_n8[3]; -+ ctxt->md5_buf[61] = ctxt->md5_n8[2]; -+ ctxt->md5_buf[62] = ctxt->md5_n8[1]; -+ ctxt->md5_buf[63] = ctxt->md5_n8[0]; -+#endif -+ -+ md5_calc(ctxt->md5_buf, ctxt); -+} -+ -+void md5_result(digest, ctxt) -+ u_int8_t *digest; -+ md5_ctxt *ctxt; -+{ -+ /* 4 byte words */ -+#if BYTE_ORDER == LITTLE_ENDIAN -+ bcopy(&ctxt->md5_st8[0], digest, 16); -+#endif -+#if BYTE_ORDER == BIG_ENDIAN -+ digest[ 0] = ctxt->md5_st8[ 3]; digest[ 1] = ctxt->md5_st8[ 2]; -+ digest[ 2] = ctxt->md5_st8[ 1]; digest[ 3] = ctxt->md5_st8[ 0]; -+ digest[ 4] = ctxt->md5_st8[ 7]; digest[ 5] = ctxt->md5_st8[ 6]; -+ digest[ 6] = ctxt->md5_st8[ 5]; digest[ 7] = ctxt->md5_st8[ 4]; -+ digest[ 8] = ctxt->md5_st8[11]; digest[ 9] = ctxt->md5_st8[10]; -+ digest[10] = ctxt->md5_st8[ 9]; digest[11] = ctxt->md5_st8[ 8]; -+ digest[12] = ctxt->md5_st8[15]; digest[13] = ctxt->md5_st8[14]; -+ digest[14] = ctxt->md5_st8[13]; digest[15] = ctxt->md5_st8[12]; -+#endif -+} -+ -+static void md5_calc(b64, ctxt) -+ u_int8_t *b64; -+ md5_ctxt *ctxt; -+{ -+ u_int32_t A = ctxt->md5_sta; -+ u_int32_t B = ctxt->md5_stb; -+ u_int32_t C = ctxt->md5_stc; -+ u_int32_t D = ctxt->md5_std; -+#if BYTE_ORDER == LITTLE_ENDIAN -+ u_int32_t *X = (u_int32_t *)b64; -+#endif -+#if BYTE_ORDER == BIG_ENDIAN -+ /* 4 byte words */ -+ /* what a brute force but fast! */ -+ u_int32_t X[16]; -+ u_int8_t *y = (u_int8_t *)X; -+ y[ 0] = b64[ 3]; y[ 1] = b64[ 2]; y[ 2] = b64[ 1]; y[ 3] = b64[ 0]; -+ y[ 4] = b64[ 7]; y[ 5] = b64[ 6]; y[ 6] = b64[ 5]; y[ 7] = b64[ 4]; -+ y[ 8] = b64[11]; y[ 9] = b64[10]; y[10] = b64[ 9]; y[11] = b64[ 8]; -+ y[12] = b64[15]; y[13] = b64[14]; y[14] = b64[13]; y[15] = b64[12]; -+ y[16] = b64[19]; y[17] = b64[18]; y[18] = b64[17]; y[19] = b64[16]; -+ y[20] = b64[23]; y[21] = b64[22]; y[22] = b64[21]; y[23] = b64[20]; -+ y[24] = b64[27]; y[25] = b64[26]; y[26] = b64[25]; y[27] = b64[24]; -+ y[28] = b64[31]; y[29] = b64[30]; y[30] = b64[29]; y[31] = b64[28]; -+ y[32] = b64[35]; y[33] = b64[34]; y[34] = b64[33]; y[35] = b64[32]; -+ y[36] = b64[39]; y[37] = b64[38]; y[38] = b64[37]; y[39] = b64[36]; -+ y[40] = b64[43]; y[41] = b64[42]; y[42] = b64[41]; y[43] = b64[40]; -+ y[44] = b64[47]; y[45] = b64[46]; y[46] = b64[45]; y[47] = b64[44]; -+ y[48] = b64[51]; y[49] = b64[50]; y[50] = b64[49]; y[51] = b64[48]; -+ y[52] = b64[55]; y[53] = b64[54]; y[54] = b64[53]; y[55] = b64[52]; -+ y[56] = b64[59]; y[57] = b64[58]; y[58] = b64[57]; y[59] = b64[56]; -+ y[60] = b64[63]; y[61] = b64[62]; y[62] = b64[61]; y[63] = b64[60]; -+#endif -+ -+ ROUND1(A, B, C, D, 0, Sa, 1); ROUND1(D, A, B, C, 1, Sb, 2); -+ ROUND1(C, D, A, B, 2, Sc, 3); ROUND1(B, C, D, A, 3, Sd, 4); -+ ROUND1(A, B, C, D, 4, Sa, 5); ROUND1(D, A, B, C, 5, Sb, 6); -+ ROUND1(C, D, A, B, 6, Sc, 7); ROUND1(B, C, D, A, 7, Sd, 8); -+ ROUND1(A, B, C, D, 8, Sa, 9); ROUND1(D, A, B, C, 9, Sb, 10); -+ ROUND1(C, D, A, B, 10, Sc, 11); ROUND1(B, C, D, A, 11, Sd, 12); -+ ROUND1(A, B, C, D, 12, Sa, 13); ROUND1(D, A, B, C, 13, Sb, 14); -+ ROUND1(C, D, A, B, 14, Sc, 15); ROUND1(B, C, D, A, 15, Sd, 16); -+ -+ ROUND2(A, B, C, D, 1, Se, 17); ROUND2(D, A, B, C, 6, Sf, 18); -+ ROUND2(C, D, A, B, 11, Sg, 19); ROUND2(B, C, D, A, 0, Sh, 20); -+ ROUND2(A, B, C, D, 5, Se, 21); ROUND2(D, A, B, C, 10, Sf, 22); -+ ROUND2(C, D, A, B, 15, Sg, 23); ROUND2(B, C, D, A, 4, Sh, 24); -+ ROUND2(A, B, C, D, 9, Se, 25); ROUND2(D, A, B, C, 14, Sf, 26); -+ ROUND2(C, D, A, B, 3, Sg, 27); ROUND2(B, C, D, A, 8, Sh, 28); -+ ROUND2(A, B, C, D, 13, Se, 29); ROUND2(D, A, B, C, 2, Sf, 30); -+ ROUND2(C, D, A, B, 7, Sg, 31); ROUND2(B, C, D, A, 12, Sh, 32); -+ -+ ROUND3(A, B, C, D, 5, Si, 33); ROUND3(D, A, B, C, 8, Sj, 34); -+ ROUND3(C, D, A, B, 11, Sk, 35); ROUND3(B, C, D, A, 14, Sl, 36); -+ ROUND3(A, B, C, D, 1, Si, 37); ROUND3(D, A, B, C, 4, Sj, 38); -+ ROUND3(C, D, A, B, 7, Sk, 39); ROUND3(B, C, D, A, 10, Sl, 40); -+ ROUND3(A, B, C, D, 13, Si, 41); ROUND3(D, A, B, C, 0, Sj, 42); -+ ROUND3(C, D, A, B, 3, Sk, 43); ROUND3(B, C, D, A, 6, Sl, 44); -+ ROUND3(A, B, C, D, 9, Si, 45); ROUND3(D, A, B, C, 12, Sj, 46); -+ ROUND3(C, D, A, B, 15, Sk, 47); ROUND3(B, C, D, A, 2, Sl, 48); -+ -+ ROUND4(A, B, C, D, 0, Sm, 49); ROUND4(D, A, B, C, 7, Sn, 50); -+ ROUND4(C, D, A, B, 14, So, 51); ROUND4(B, C, D, A, 5, Sp, 52); -+ ROUND4(A, B, C, D, 12, Sm, 53); ROUND4(D, A, B, C, 3, Sn, 54); -+ ROUND4(C, D, A, B, 10, So, 55); ROUND4(B, C, D, A, 1, Sp, 56); -+ ROUND4(A, B, C, D, 8, Sm, 57); ROUND4(D, A, B, C, 15, Sn, 58); -+ ROUND4(C, D, A, B, 6, So, 59); ROUND4(B, C, D, A, 13, Sp, 60); -+ ROUND4(A, B, C, D, 4, Sm, 61); ROUND4(D, A, B, C, 11, Sn, 62); -+ ROUND4(C, D, A, B, 2, So, 63); ROUND4(B, C, D, A, 9, Sp, 64); -+ -+ ctxt->md5_sta += A; -+ ctxt->md5_stb += B; -+ ctxt->md5_stc += C; -+ ctxt->md5_std += D; -+} -diff -Nur linux-2.6.36.orig/crypto/ocf/safe/md5.h linux-2.6.36/crypto/ocf/safe/md5.h ---- linux-2.6.36.orig/crypto/ocf/safe/md5.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/safe/md5.h 2010-11-09 20:28:12.881683669 +0100 -@@ -0,0 +1,76 @@ -+/* $FreeBSD: src/sys/crypto/md5.h,v 1.4 2002/03/20 05:13:50 alfred Exp $ */ -+/* $KAME: md5.h,v 1.4 2000/03/27 04:36:22 sumikawa Exp $ */ -+ -+/* -+ * Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. Neither the name of the project nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ */ -+ -+#ifndef _NETINET6_MD5_H_ -+#define _NETINET6_MD5_H_ -+ -+#define MD5_BUFLEN 64 -+ -+typedef struct { -+ union { -+ u_int32_t md5_state32[4]; -+ u_int8_t md5_state8[16]; -+ } md5_st; -+ -+#define md5_sta md5_st.md5_state32[0] -+#define md5_stb md5_st.md5_state32[1] -+#define md5_stc md5_st.md5_state32[2] -+#define md5_std md5_st.md5_state32[3] -+#define md5_st8 md5_st.md5_state8 -+ -+ union { -+ u_int64_t md5_count64; -+ u_int8_t md5_count8[8]; -+ } md5_count; -+#define md5_n md5_count.md5_count64 -+#define md5_n8 md5_count.md5_count8 -+ -+ u_int md5_i; -+ u_int8_t md5_buf[MD5_BUFLEN]; -+} md5_ctxt; -+ -+extern void md5_init(md5_ctxt *); -+extern void md5_loop(md5_ctxt *, u_int8_t *, u_int); -+extern void md5_pad(md5_ctxt *); -+extern void md5_result(u_int8_t *, md5_ctxt *); -+ -+/* compatibility */ -+#define MD5_CTX md5_ctxt -+#define MD5Init(x) md5_init((x)) -+#define MD5Update(x, y, z) md5_loop((x), (y), (z)) -+#define MD5Final(x, y) \ -+do { \ -+ md5_pad((y)); \ -+ md5_result((x), (y)); \ -+} while (0) -+ -+#endif /* ! _NETINET6_MD5_H_*/ -diff -Nur linux-2.6.36.orig/crypto/ocf/safe/safe.c linux-2.6.36/crypto/ocf/safe/safe.c ---- linux-2.6.36.orig/crypto/ocf/safe/safe.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/safe/safe.c 2010-11-09 20:28:12.922204086 +0100 -@@ -0,0 +1,2288 @@ -+/*- -+ * Linux port done by David McCullough -+ * Copyright (C) 2004-2010 David McCullough -+ * The license and original author are listed below. -+ * -+ * Copyright (c) 2003 Sam Leffler, Errno Consulting -+ * Copyright (c) 2003 Global Technology Associates, Inc. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ * -+__FBSDID("$FreeBSD: src/sys/dev/safe/safe.c,v 1.18 2007/03/21 03:42:50 sam Exp $"); -+ */ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* -+ * SafeNet SafeXcel-1141 hardware crypto accelerator -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#if 1 -+#define DPRINTF(a) do { \ -+ if (debug) { \ -+ printk("%s: ", sc ? \ -+ device_get_nameunit(sc->sc_dev) : "safe"); \ -+ printk a; \ -+ } \ -+ } while (0) -+#else -+#define DPRINTF(a) -+#endif -+ -+/* -+ * until we find a cleaner way, include the BSD md5/sha1 code -+ * here -+ */ -+#define HMAC_HACK 1 -+#ifdef HMAC_HACK -+#define LITTLE_ENDIAN 1234 -+#define BIG_ENDIAN 4321 -+#ifdef __LITTLE_ENDIAN -+#define BYTE_ORDER LITTLE_ENDIAN -+#endif -+#ifdef __BIG_ENDIAN -+#define BYTE_ORDER BIG_ENDIAN -+#endif -+#include -+#include -+#include -+#include -+ -+u_int8_t hmac_ipad_buffer[64] = { -+ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, -+ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, -+ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, -+ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, -+ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, -+ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, -+ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, -+ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36 -+}; -+ -+u_int8_t hmac_opad_buffer[64] = { -+ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, -+ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, -+ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, -+ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, -+ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, -+ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, -+ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, -+ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C -+}; -+#endif /* HMAC_HACK */ -+ -+/* add proc entry for this */ -+struct safe_stats safestats; -+ -+#define debug safe_debug -+int safe_debug = 0; -+module_param(safe_debug, int, 0644); -+MODULE_PARM_DESC(safe_debug, "Enable debug"); -+ -+static void safe_callback(struct safe_softc *, struct safe_ringentry *); -+static void safe_feed(struct safe_softc *, struct safe_ringentry *); -+#if defined(CONFIG_OCF_RANDOMHARVEST) && !defined(SAFE_NO_RNG) -+static void safe_rng_init(struct safe_softc *); -+int safe_rngbufsize = 8; /* 32 bytes each read */ -+module_param(safe_rngbufsize, int, 0644); -+MODULE_PARM_DESC(safe_rngbufsize, "RNG polling buffer size (32-bit words)"); -+int safe_rngmaxalarm = 8; /* max alarms before reset */ -+module_param(safe_rngmaxalarm, int, 0644); -+MODULE_PARM_DESC(safe_rngmaxalarm, "RNG max alarms before reset"); -+#endif /* SAFE_NO_RNG */ -+ -+static void safe_totalreset(struct safe_softc *sc); -+static int safe_dmamap_aligned(struct safe_softc *sc, const struct safe_operand *op); -+static int safe_dmamap_uniform(struct safe_softc *sc, const struct safe_operand *op); -+static int safe_free_entry(struct safe_softc *sc, struct safe_ringentry *re); -+static int safe_kprocess(device_t dev, struct cryptkop *krp, int hint); -+static int safe_kstart(struct safe_softc *sc); -+static int safe_ksigbits(struct safe_softc *sc, struct crparam *cr); -+static void safe_kfeed(struct safe_softc *sc); -+static void safe_kpoll(unsigned long arg); -+static void safe_kload_reg(struct safe_softc *sc, u_int32_t off, -+ u_int32_t len, struct crparam *n); -+ -+static int safe_newsession(device_t, u_int32_t *, struct cryptoini *); -+static int safe_freesession(device_t, u_int64_t); -+static int safe_process(device_t, struct cryptop *, int); -+ -+static device_method_t safe_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, safe_newsession), -+ DEVMETHOD(cryptodev_freesession,safe_freesession), -+ DEVMETHOD(cryptodev_process, safe_process), -+ DEVMETHOD(cryptodev_kprocess, safe_kprocess), -+}; -+ -+#define READ_REG(sc,r) readl((sc)->sc_base_addr + (r)) -+#define WRITE_REG(sc,r,val) writel((val), (sc)->sc_base_addr + (r)) -+ -+#define SAFE_MAX_CHIPS 8 -+static struct safe_softc *safe_chip_idx[SAFE_MAX_CHIPS]; -+ -+/* -+ * split our buffers up into safe DMAable byte fragments to avoid lockup -+ * bug in 1141 HW on rev 1.0. -+ */ -+ -+static int -+pci_map_linear( -+ struct safe_softc *sc, -+ struct safe_operand *buf, -+ void *addr, -+ int len) -+{ -+ dma_addr_t tmp; -+ int chunk, tlen = len; -+ -+ tmp = pci_map_single(sc->sc_pcidev, addr, len, PCI_DMA_BIDIRECTIONAL); -+ -+ buf->mapsize += len; -+ while (len > 0) { -+ chunk = (len > sc->sc_max_dsize) ? sc->sc_max_dsize : len; -+ buf->segs[buf->nsegs].ds_addr = tmp; -+ buf->segs[buf->nsegs].ds_len = chunk; -+ buf->segs[buf->nsegs].ds_tlen = tlen; -+ buf->nsegs++; -+ tmp += chunk; -+ len -= chunk; -+ tlen = 0; -+ } -+ return 0; -+} -+ -+/* -+ * map in a given uio buffer (great on some arches :-) -+ */ -+ -+static int -+pci_map_uio(struct safe_softc *sc, struct safe_operand *buf, struct uio *uio) -+{ -+ struct iovec *iov = uio->uio_iov; -+ int n; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ buf->mapsize = 0; -+ buf->nsegs = 0; -+ -+ for (n = 0; n < uio->uio_iovcnt; n++) { -+ pci_map_linear(sc, buf, iov->iov_base, iov->iov_len); -+ iov++; -+ } -+ -+ /* identify this buffer by the first segment */ -+ buf->map = (void *) buf->segs[0].ds_addr; -+ return(0); -+} -+ -+/* -+ * map in a given sk_buff -+ */ -+ -+static int -+pci_map_skb(struct safe_softc *sc,struct safe_operand *buf,struct sk_buff *skb) -+{ -+ int i; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ buf->mapsize = 0; -+ buf->nsegs = 0; -+ -+ pci_map_linear(sc, buf, skb->data, skb_headlen(skb)); -+ -+ for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { -+ pci_map_linear(sc, buf, -+ page_address(skb_shinfo(skb)->frags[i].page) + -+ skb_shinfo(skb)->frags[i].page_offset, -+ skb_shinfo(skb)->frags[i].size); -+ } -+ -+ /* identify this buffer by the first segment */ -+ buf->map = (void *) buf->segs[0].ds_addr; -+ return(0); -+} -+ -+ -+#if 0 /* not needed at this time */ -+static void -+pci_sync_operand(struct safe_softc *sc, struct safe_operand *buf) -+{ -+ int i; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ for (i = 0; i < buf->nsegs; i++) -+ pci_dma_sync_single_for_cpu(sc->sc_pcidev, buf->segs[i].ds_addr, -+ buf->segs[i].ds_len, PCI_DMA_BIDIRECTIONAL); -+} -+#endif -+ -+static void -+pci_unmap_operand(struct safe_softc *sc, struct safe_operand *buf) -+{ -+ int i; -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ for (i = 0; i < buf->nsegs; i++) { -+ if (buf->segs[i].ds_tlen) { -+ DPRINTF(("%s - unmap %d 0x%x %d\n", __FUNCTION__, i, buf->segs[i].ds_addr, buf->segs[i].ds_tlen)); -+ pci_unmap_single(sc->sc_pcidev, buf->segs[i].ds_addr, -+ buf->segs[i].ds_tlen, PCI_DMA_BIDIRECTIONAL); -+ DPRINTF(("%s - unmap %d 0x%x %d done\n", __FUNCTION__, i, buf->segs[i].ds_addr, buf->segs[i].ds_tlen)); -+ } -+ buf->segs[i].ds_addr = 0; -+ buf->segs[i].ds_len = 0; -+ buf->segs[i].ds_tlen = 0; -+ } -+ buf->nsegs = 0; -+ buf->mapsize = 0; -+ buf->map = 0; -+} -+ -+ -+/* -+ * SafeXcel Interrupt routine -+ */ -+static irqreturn_t -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) -+safe_intr(int irq, void *arg) -+#else -+safe_intr(int irq, void *arg, struct pt_regs *regs) -+#endif -+{ -+ struct safe_softc *sc = arg; -+ int stat; -+ unsigned long flags; -+ -+ stat = READ_REG(sc, SAFE_HM_STAT); -+ -+ DPRINTF(("%s(stat=0x%x)\n", __FUNCTION__, stat)); -+ -+ if (stat == 0) /* shared irq, not for us */ -+ return IRQ_NONE; -+ -+ WRITE_REG(sc, SAFE_HI_CLR, stat); /* IACK */ -+ -+ if ((stat & SAFE_INT_PE_DDONE)) { -+ /* -+ * Descriptor(s) done; scan the ring and -+ * process completed operations. -+ */ -+ spin_lock_irqsave(&sc->sc_ringmtx, flags); -+ while (sc->sc_back != sc->sc_front) { -+ struct safe_ringentry *re = sc->sc_back; -+ -+#ifdef SAFE_DEBUG -+ if (debug) { -+ safe_dump_ringstate(sc, __func__); -+ safe_dump_request(sc, __func__, re); -+ } -+#endif -+ /* -+ * safe_process marks ring entries that were allocated -+ * but not used with a csr of zero. This insures the -+ * ring front pointer never needs to be set backwards -+ * in the event that an entry is allocated but not used -+ * because of a setup error. -+ */ -+ DPRINTF(("%s re->re_desc.d_csr=0x%x\n", __FUNCTION__, re->re_desc.d_csr)); -+ if (re->re_desc.d_csr != 0) { -+ if (!SAFE_PE_CSR_IS_DONE(re->re_desc.d_csr)) { -+ DPRINTF(("%s !CSR_IS_DONE\n", __FUNCTION__)); -+ break; -+ } -+ if (!SAFE_PE_LEN_IS_DONE(re->re_desc.d_len)) { -+ DPRINTF(("%s !LEN_IS_DONE\n", __FUNCTION__)); -+ break; -+ } -+ sc->sc_nqchip--; -+ safe_callback(sc, re); -+ } -+ if (++(sc->sc_back) == sc->sc_ringtop) -+ sc->sc_back = sc->sc_ring; -+ } -+ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); -+ } -+ -+ /* -+ * Check to see if we got any DMA Error -+ */ -+ if (stat & SAFE_INT_PE_ERROR) { -+ printk("%s: dmaerr dmastat %08x\n", device_get_nameunit(sc->sc_dev), -+ (int)READ_REG(sc, SAFE_PE_DMASTAT)); -+ safestats.st_dmaerr++; -+ safe_totalreset(sc); -+#if 0 -+ safe_feed(sc); -+#endif -+ } -+ -+ if (sc->sc_needwakeup) { /* XXX check high watermark */ -+ int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); -+ DPRINTF(("%s: wakeup crypto %x\n", __func__, -+ sc->sc_needwakeup)); -+ sc->sc_needwakeup &= ~wakeup; -+ crypto_unblock(sc->sc_cid, wakeup); -+ } -+ -+ return IRQ_HANDLED; -+} -+ -+/* -+ * safe_feed() - post a request to chip -+ */ -+static void -+safe_feed(struct safe_softc *sc, struct safe_ringentry *re) -+{ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+#ifdef SAFE_DEBUG -+ if (debug) { -+ safe_dump_ringstate(sc, __func__); -+ safe_dump_request(sc, __func__, re); -+ } -+#endif -+ sc->sc_nqchip++; -+ if (sc->sc_nqchip > safestats.st_maxqchip) -+ safestats.st_maxqchip = sc->sc_nqchip; -+ /* poke h/w to check descriptor ring, any value can be written */ -+ WRITE_REG(sc, SAFE_HI_RD_DESCR, 0); -+} -+ -+#define N(a) (sizeof(a) / sizeof (a[0])) -+static void -+safe_setup_enckey(struct safe_session *ses, caddr_t key) -+{ -+ int i; -+ -+ bcopy(key, ses->ses_key, ses->ses_klen / 8); -+ -+ /* PE is little-endian, insure proper byte order */ -+ for (i = 0; i < N(ses->ses_key); i++) -+ ses->ses_key[i] = htole32(ses->ses_key[i]); -+} -+ -+static void -+safe_setup_mackey(struct safe_session *ses, int algo, caddr_t key, int klen) -+{ -+#ifdef HMAC_HACK -+ MD5_CTX md5ctx; -+ SHA1_CTX sha1ctx; -+ int i; -+ -+ -+ for (i = 0; i < klen; i++) -+ key[i] ^= HMAC_IPAD_VAL; -+ -+ if (algo == CRYPTO_MD5_HMAC) { -+ MD5Init(&md5ctx); -+ MD5Update(&md5ctx, key, klen); -+ MD5Update(&md5ctx, hmac_ipad_buffer, MD5_HMAC_BLOCK_LEN - klen); -+ bcopy(md5ctx.md5_st8, ses->ses_hminner, sizeof(md5ctx.md5_st8)); -+ } else { -+ SHA1Init(&sha1ctx); -+ SHA1Update(&sha1ctx, key, klen); -+ SHA1Update(&sha1ctx, hmac_ipad_buffer, -+ SHA1_HMAC_BLOCK_LEN - klen); -+ bcopy(sha1ctx.h.b32, ses->ses_hminner, sizeof(sha1ctx.h.b32)); -+ } -+ -+ for (i = 0; i < klen; i++) -+ key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); -+ -+ if (algo == CRYPTO_MD5_HMAC) { -+ MD5Init(&md5ctx); -+ MD5Update(&md5ctx, key, klen); -+ MD5Update(&md5ctx, hmac_opad_buffer, MD5_HMAC_BLOCK_LEN - klen); -+ bcopy(md5ctx.md5_st8, ses->ses_hmouter, sizeof(md5ctx.md5_st8)); -+ } else { -+ SHA1Init(&sha1ctx); -+ SHA1Update(&sha1ctx, key, klen); -+ SHA1Update(&sha1ctx, hmac_opad_buffer, -+ SHA1_HMAC_BLOCK_LEN - klen); -+ bcopy(sha1ctx.h.b32, ses->ses_hmouter, sizeof(sha1ctx.h.b32)); -+ } -+ -+ for (i = 0; i < klen; i++) -+ key[i] ^= HMAC_OPAD_VAL; -+ -+#if 0 -+ /* -+ * this code prevents SHA working on a BE host, -+ * so it is obviously wrong. I think the byte -+ * swap setup we do with the chip fixes this for us -+ */ -+ -+ /* PE is little-endian, insure proper byte order */ -+ for (i = 0; i < N(ses->ses_hminner); i++) { -+ ses->ses_hminner[i] = htole32(ses->ses_hminner[i]); -+ ses->ses_hmouter[i] = htole32(ses->ses_hmouter[i]); -+ } -+#endif -+#else /* HMAC_HACK */ -+ printk("safe: md5/sha not implemented\n"); -+#endif /* HMAC_HACK */ -+} -+#undef N -+ -+/* -+ * Allocate a new 'session' and return an encoded session id. 'sidp' -+ * contains our registration id, and should contain an encoded session -+ * id on successful allocation. -+ */ -+static int -+safe_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) -+{ -+ struct safe_softc *sc = device_get_softc(dev); -+ struct cryptoini *c, *encini = NULL, *macini = NULL; -+ struct safe_session *ses = NULL; -+ int sesn; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (sidp == NULL || cri == NULL || sc == NULL) -+ return (EINVAL); -+ -+ for (c = cri; c != NULL; c = c->cri_next) { -+ if (c->cri_alg == CRYPTO_MD5_HMAC || -+ c->cri_alg == CRYPTO_SHA1_HMAC || -+ c->cri_alg == CRYPTO_NULL_HMAC) { -+ if (macini) -+ return (EINVAL); -+ macini = c; -+ } else if (c->cri_alg == CRYPTO_DES_CBC || -+ c->cri_alg == CRYPTO_3DES_CBC || -+ c->cri_alg == CRYPTO_AES_CBC || -+ c->cri_alg == CRYPTO_NULL_CBC) { -+ if (encini) -+ return (EINVAL); -+ encini = c; -+ } else -+ return (EINVAL); -+ } -+ if (encini == NULL && macini == NULL) -+ return (EINVAL); -+ if (encini) { /* validate key length */ -+ switch (encini->cri_alg) { -+ case CRYPTO_DES_CBC: -+ if (encini->cri_klen != 64) -+ return (EINVAL); -+ break; -+ case CRYPTO_3DES_CBC: -+ if (encini->cri_klen != 192) -+ return (EINVAL); -+ break; -+ case CRYPTO_AES_CBC: -+ if (encini->cri_klen != 128 && -+ encini->cri_klen != 192 && -+ encini->cri_klen != 256) -+ return (EINVAL); -+ break; -+ } -+ } -+ -+ if (sc->sc_sessions == NULL) { -+ ses = sc->sc_sessions = (struct safe_session *) -+ kmalloc(sizeof(struct safe_session), SLAB_ATOMIC); -+ if (ses == NULL) -+ return (ENOMEM); -+ memset(ses, 0, sizeof(struct safe_session)); -+ sesn = 0; -+ sc->sc_nsessions = 1; -+ } else { -+ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { -+ if (sc->sc_sessions[sesn].ses_used == 0) { -+ ses = &sc->sc_sessions[sesn]; -+ break; -+ } -+ } -+ -+ if (ses == NULL) { -+ sesn = sc->sc_nsessions; -+ ses = (struct safe_session *) -+ kmalloc((sesn + 1) * sizeof(struct safe_session), SLAB_ATOMIC); -+ if (ses == NULL) -+ return (ENOMEM); -+ memset(ses, 0, (sesn + 1) * sizeof(struct safe_session)); -+ bcopy(sc->sc_sessions, ses, sesn * -+ sizeof(struct safe_session)); -+ bzero(sc->sc_sessions, sesn * -+ sizeof(struct safe_session)); -+ kfree(sc->sc_sessions); -+ sc->sc_sessions = ses; -+ ses = &sc->sc_sessions[sesn]; -+ sc->sc_nsessions++; -+ } -+ } -+ -+ bzero(ses, sizeof(struct safe_session)); -+ ses->ses_used = 1; -+ -+ if (encini) { -+ /* get an IV */ -+ /* XXX may read fewer than requested */ -+ read_random(ses->ses_iv, sizeof(ses->ses_iv)); -+ -+ ses->ses_klen = encini->cri_klen; -+ if (encini->cri_key != NULL) -+ safe_setup_enckey(ses, encini->cri_key); -+ } -+ -+ if (macini) { -+ ses->ses_mlen = macini->cri_mlen; -+ if (ses->ses_mlen == 0) { -+ if (macini->cri_alg == CRYPTO_MD5_HMAC) -+ ses->ses_mlen = MD5_HASH_LEN; -+ else -+ ses->ses_mlen = SHA1_HASH_LEN; -+ } -+ -+ if (macini->cri_key != NULL) { -+ safe_setup_mackey(ses, macini->cri_alg, macini->cri_key, -+ macini->cri_klen / 8); -+ } -+ } -+ -+ *sidp = SAFE_SID(device_get_unit(sc->sc_dev), sesn); -+ return (0); -+} -+ -+/* -+ * Deallocate a session. -+ */ -+static int -+safe_freesession(device_t dev, u_int64_t tid) -+{ -+ struct safe_softc *sc = device_get_softc(dev); -+ int session, ret; -+ u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (sc == NULL) -+ return (EINVAL); -+ -+ session = SAFE_SESSION(sid); -+ if (session < sc->sc_nsessions) { -+ bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session])); -+ ret = 0; -+ } else -+ ret = EINVAL; -+ return (ret); -+} -+ -+ -+static int -+safe_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ struct safe_softc *sc = device_get_softc(dev); -+ int err = 0, i, nicealign, uniform; -+ struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; -+ int bypass, oplen, ivsize; -+ caddr_t iv; -+ int16_t coffset; -+ struct safe_session *ses; -+ struct safe_ringentry *re; -+ struct safe_sarec *sa; -+ struct safe_pdesc *pd; -+ u_int32_t cmd0, cmd1, staterec; -+ unsigned long flags; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { -+ safestats.st_invalid++; -+ return (EINVAL); -+ } -+ if (SAFE_SESSION(crp->crp_sid) >= sc->sc_nsessions) { -+ safestats.st_badsession++; -+ return (EINVAL); -+ } -+ -+ spin_lock_irqsave(&sc->sc_ringmtx, flags); -+ if (sc->sc_front == sc->sc_back && sc->sc_nqchip != 0) { -+ safestats.st_ringfull++; -+ sc->sc_needwakeup |= CRYPTO_SYMQ; -+ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); -+ return (ERESTART); -+ } -+ re = sc->sc_front; -+ -+ staterec = re->re_sa.sa_staterec; /* save */ -+ /* NB: zero everything but the PE descriptor */ -+ bzero(&re->re_sa, sizeof(struct safe_ringentry) - sizeof(re->re_desc)); -+ re->re_sa.sa_staterec = staterec; /* restore */ -+ -+ re->re_crp = crp; -+ re->re_sesn = SAFE_SESSION(crp->crp_sid); -+ -+ re->re_src.nsegs = 0; -+ re->re_dst.nsegs = 0; -+ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ re->re_src_skb = (struct sk_buff *)crp->crp_buf; -+ re->re_dst_skb = (struct sk_buff *)crp->crp_buf; -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ re->re_src_io = (struct uio *)crp->crp_buf; -+ re->re_dst_io = (struct uio *)crp->crp_buf; -+ } else { -+ safestats.st_badflags++; -+ err = EINVAL; -+ goto errout; /* XXX we don't handle contiguous blocks! */ -+ } -+ -+ sa = &re->re_sa; -+ ses = &sc->sc_sessions[re->re_sesn]; -+ -+ crd1 = crp->crp_desc; -+ if (crd1 == NULL) { -+ safestats.st_nodesc++; -+ err = EINVAL; -+ goto errout; -+ } -+ crd2 = crd1->crd_next; -+ -+ cmd0 = SAFE_SA_CMD0_BASIC; /* basic group operation */ -+ cmd1 = 0; -+ if (crd2 == NULL) { -+ if (crd1->crd_alg == CRYPTO_MD5_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1_HMAC || -+ crd1->crd_alg == CRYPTO_NULL_HMAC) { -+ maccrd = crd1; -+ enccrd = NULL; -+ cmd0 |= SAFE_SA_CMD0_OP_HASH; -+ } else if (crd1->crd_alg == CRYPTO_DES_CBC || -+ crd1->crd_alg == CRYPTO_3DES_CBC || -+ crd1->crd_alg == CRYPTO_AES_CBC || -+ crd1->crd_alg == CRYPTO_NULL_CBC) { -+ maccrd = NULL; -+ enccrd = crd1; -+ cmd0 |= SAFE_SA_CMD0_OP_CRYPT; -+ } else { -+ safestats.st_badalg++; -+ err = EINVAL; -+ goto errout; -+ } -+ } else { -+ if ((crd1->crd_alg == CRYPTO_MD5_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1_HMAC || -+ crd1->crd_alg == CRYPTO_NULL_HMAC) && -+ (crd2->crd_alg == CRYPTO_DES_CBC || -+ crd2->crd_alg == CRYPTO_3DES_CBC || -+ crd2->crd_alg == CRYPTO_AES_CBC || -+ crd2->crd_alg == CRYPTO_NULL_CBC) && -+ ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { -+ maccrd = crd1; -+ enccrd = crd2; -+ } else if ((crd1->crd_alg == CRYPTO_DES_CBC || -+ crd1->crd_alg == CRYPTO_3DES_CBC || -+ crd1->crd_alg == CRYPTO_AES_CBC || -+ crd1->crd_alg == CRYPTO_NULL_CBC) && -+ (crd2->crd_alg == CRYPTO_MD5_HMAC || -+ crd2->crd_alg == CRYPTO_SHA1_HMAC || -+ crd2->crd_alg == CRYPTO_NULL_HMAC) && -+ (crd1->crd_flags & CRD_F_ENCRYPT)) { -+ enccrd = crd1; -+ maccrd = crd2; -+ } else { -+ safestats.st_badalg++; -+ err = EINVAL; -+ goto errout; -+ } -+ cmd0 |= SAFE_SA_CMD0_OP_BOTH; -+ } -+ -+ if (enccrd) { -+ if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) -+ safe_setup_enckey(ses, enccrd->crd_key); -+ -+ if (enccrd->crd_alg == CRYPTO_DES_CBC) { -+ cmd0 |= SAFE_SA_CMD0_DES; -+ cmd1 |= SAFE_SA_CMD1_CBC; -+ ivsize = 2*sizeof(u_int32_t); -+ } else if (enccrd->crd_alg == CRYPTO_3DES_CBC) { -+ cmd0 |= SAFE_SA_CMD0_3DES; -+ cmd1 |= SAFE_SA_CMD1_CBC; -+ ivsize = 2*sizeof(u_int32_t); -+ } else if (enccrd->crd_alg == CRYPTO_AES_CBC) { -+ cmd0 |= SAFE_SA_CMD0_AES; -+ cmd1 |= SAFE_SA_CMD1_CBC; -+ if (ses->ses_klen == 128) -+ cmd1 |= SAFE_SA_CMD1_AES128; -+ else if (ses->ses_klen == 192) -+ cmd1 |= SAFE_SA_CMD1_AES192; -+ else -+ cmd1 |= SAFE_SA_CMD1_AES256; -+ ivsize = 4*sizeof(u_int32_t); -+ } else { -+ cmd0 |= SAFE_SA_CMD0_CRYPT_NULL; -+ ivsize = 0; -+ } -+ -+ /* -+ * Setup encrypt/decrypt state. When using basic ops -+ * we can't use an inline IV because hash/crypt offset -+ * must be from the end of the IV to the start of the -+ * crypt data and this leaves out the preceding header -+ * from the hash calculation. Instead we place the IV -+ * in the state record and set the hash/crypt offset to -+ * copy both the header+IV. -+ */ -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) { -+ cmd0 |= SAFE_SA_CMD0_OUTBOUND; -+ -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) -+ iv = enccrd->crd_iv; -+ else -+ iv = (caddr_t) ses->ses_iv; -+ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ enccrd->crd_inject, ivsize, iv); -+ } -+ bcopy(iv, re->re_sastate.sa_saved_iv, ivsize); -+ /* make iv LE */ -+ for (i = 0; i < ivsize/sizeof(re->re_sastate.sa_saved_iv[0]); i++) -+ re->re_sastate.sa_saved_iv[i] = -+ cpu_to_le32(re->re_sastate.sa_saved_iv[i]); -+ cmd0 |= SAFE_SA_CMD0_IVLD_STATE | SAFE_SA_CMD0_SAVEIV; -+ re->re_flags |= SAFE_QFLAGS_COPYOUTIV; -+ } else { -+ cmd0 |= SAFE_SA_CMD0_INBOUND; -+ -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) { -+ bcopy(enccrd->crd_iv, -+ re->re_sastate.sa_saved_iv, ivsize); -+ } else { -+ crypto_copydata(crp->crp_flags, crp->crp_buf, -+ enccrd->crd_inject, ivsize, -+ (caddr_t)re->re_sastate.sa_saved_iv); -+ } -+ /* make iv LE */ -+ for (i = 0; i < ivsize/sizeof(re->re_sastate.sa_saved_iv[0]); i++) -+ re->re_sastate.sa_saved_iv[i] = -+ cpu_to_le32(re->re_sastate.sa_saved_iv[i]); -+ cmd0 |= SAFE_SA_CMD0_IVLD_STATE; -+ } -+ /* -+ * For basic encryption use the zero pad algorithm. -+ * This pads results to an 8-byte boundary and -+ * suppresses padding verification for inbound (i.e. -+ * decrypt) operations. -+ * -+ * NB: Not sure if the 8-byte pad boundary is a problem. -+ */ -+ cmd0 |= SAFE_SA_CMD0_PAD_ZERO; -+ -+ /* XXX assert key bufs have the same size */ -+ bcopy(ses->ses_key, sa->sa_key, sizeof(sa->sa_key)); -+ } -+ -+ if (maccrd) { -+ if (maccrd->crd_flags & CRD_F_KEY_EXPLICIT) { -+ safe_setup_mackey(ses, maccrd->crd_alg, -+ maccrd->crd_key, maccrd->crd_klen / 8); -+ } -+ -+ if (maccrd->crd_alg == CRYPTO_MD5_HMAC) { -+ cmd0 |= SAFE_SA_CMD0_MD5; -+ cmd1 |= SAFE_SA_CMD1_HMAC; /* NB: enable HMAC */ -+ } else if (maccrd->crd_alg == CRYPTO_SHA1_HMAC) { -+ cmd0 |= SAFE_SA_CMD0_SHA1; -+ cmd1 |= SAFE_SA_CMD1_HMAC; /* NB: enable HMAC */ -+ } else { -+ cmd0 |= SAFE_SA_CMD0_HASH_NULL; -+ } -+ /* -+ * Digest data is loaded from the SA and the hash -+ * result is saved to the state block where we -+ * retrieve it for return to the caller. -+ */ -+ /* XXX assert digest bufs have the same size */ -+ bcopy(ses->ses_hminner, sa->sa_indigest, -+ sizeof(sa->sa_indigest)); -+ bcopy(ses->ses_hmouter, sa->sa_outdigest, -+ sizeof(sa->sa_outdigest)); -+ -+ cmd0 |= SAFE_SA_CMD0_HSLD_SA | SAFE_SA_CMD0_SAVEHASH; -+ re->re_flags |= SAFE_QFLAGS_COPYOUTICV; -+ } -+ -+ if (enccrd && maccrd) { -+ /* -+ * The offset from hash data to the start of -+ * crypt data is the difference in the skips. -+ */ -+ bypass = maccrd->crd_skip; -+ coffset = enccrd->crd_skip - maccrd->crd_skip; -+ if (coffset < 0) { -+ DPRINTF(("%s: hash does not precede crypt; " -+ "mac skip %u enc skip %u\n", -+ __func__, maccrd->crd_skip, enccrd->crd_skip)); -+ safestats.st_skipmismatch++; -+ err = EINVAL; -+ goto errout; -+ } -+ oplen = enccrd->crd_skip + enccrd->crd_len; -+ if (maccrd->crd_skip + maccrd->crd_len != oplen) { -+ DPRINTF(("%s: hash amount %u != crypt amount %u\n", -+ __func__, maccrd->crd_skip + maccrd->crd_len, -+ oplen)); -+ safestats.st_lenmismatch++; -+ err = EINVAL; -+ goto errout; -+ } -+#ifdef SAFE_DEBUG -+ if (debug) { -+ printf("mac: skip %d, len %d, inject %d\n", -+ maccrd->crd_skip, maccrd->crd_len, -+ maccrd->crd_inject); -+ printf("enc: skip %d, len %d, inject %d\n", -+ enccrd->crd_skip, enccrd->crd_len, -+ enccrd->crd_inject); -+ printf("bypass %d coffset %d oplen %d\n", -+ bypass, coffset, oplen); -+ } -+#endif -+ if (coffset & 3) { /* offset must be 32-bit aligned */ -+ DPRINTF(("%s: coffset %u misaligned\n", -+ __func__, coffset)); -+ safestats.st_coffmisaligned++; -+ err = EINVAL; -+ goto errout; -+ } -+ coffset >>= 2; -+ if (coffset > 255) { /* offset must be <256 dwords */ -+ DPRINTF(("%s: coffset %u too big\n", -+ __func__, coffset)); -+ safestats.st_cofftoobig++; -+ err = EINVAL; -+ goto errout; -+ } -+ /* -+ * Tell the hardware to copy the header to the output. -+ * The header is defined as the data from the end of -+ * the bypass to the start of data to be encrypted. -+ * Typically this is the inline IV. Note that you need -+ * to do this even if src+dst are the same; it appears -+ * that w/o this bit the crypted data is written -+ * immediately after the bypass data. -+ */ -+ cmd1 |= SAFE_SA_CMD1_HDRCOPY; -+ /* -+ * Disable IP header mutable bit handling. This is -+ * needed to get correct HMAC calculations. -+ */ -+ cmd1 |= SAFE_SA_CMD1_MUTABLE; -+ } else { -+ if (enccrd) { -+ bypass = enccrd->crd_skip; -+ oplen = bypass + enccrd->crd_len; -+ } else { -+ bypass = maccrd->crd_skip; -+ oplen = bypass + maccrd->crd_len; -+ } -+ coffset = 0; -+ } -+ /* XXX verify multiple of 4 when using s/g */ -+ if (bypass > 96) { /* bypass offset must be <= 96 bytes */ -+ DPRINTF(("%s: bypass %u too big\n", __func__, bypass)); -+ safestats.st_bypasstoobig++; -+ err = EINVAL; -+ goto errout; -+ } -+ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ if (pci_map_skb(sc, &re->re_src, re->re_src_skb)) { -+ safestats.st_noload++; -+ err = ENOMEM; -+ goto errout; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ if (pci_map_uio(sc, &re->re_src, re->re_src_io)) { -+ safestats.st_noload++; -+ err = ENOMEM; -+ goto errout; -+ } -+ } -+ nicealign = safe_dmamap_aligned(sc, &re->re_src); -+ uniform = safe_dmamap_uniform(sc, &re->re_src); -+ -+ DPRINTF(("src nicealign %u uniform %u nsegs %u\n", -+ nicealign, uniform, re->re_src.nsegs)); -+ if (re->re_src.nsegs > 1) { -+ re->re_desc.d_src = sc->sc_spalloc.dma_paddr + -+ ((caddr_t) sc->sc_spfree - (caddr_t) sc->sc_spring); -+ for (i = 0; i < re->re_src_nsegs; i++) { -+ /* NB: no need to check if there's space */ -+ pd = sc->sc_spfree; -+ if (++(sc->sc_spfree) == sc->sc_springtop) -+ sc->sc_spfree = sc->sc_spring; -+ -+ KASSERT((pd->pd_flags&3) == 0 || -+ (pd->pd_flags&3) == SAFE_PD_DONE, -+ ("bogus source particle descriptor; flags %x", -+ pd->pd_flags)); -+ pd->pd_addr = re->re_src_segs[i].ds_addr; -+ pd->pd_size = re->re_src_segs[i].ds_len; -+ pd->pd_flags = SAFE_PD_READY; -+ } -+ cmd0 |= SAFE_SA_CMD0_IGATHER; -+ } else { -+ /* -+ * No need for gather, reference the operand directly. -+ */ -+ re->re_desc.d_src = re->re_src_segs[0].ds_addr; -+ } -+ -+ if (enccrd == NULL && maccrd != NULL) { -+ /* -+ * Hash op; no destination needed. -+ */ -+ } else { -+ if (crp->crp_flags & (CRYPTO_F_IOV|CRYPTO_F_SKBUF)) { -+ if (!nicealign) { -+ safestats.st_iovmisaligned++; -+ err = EINVAL; -+ goto errout; -+ } -+ if (uniform != 1) { -+ device_printf(sc->sc_dev, "!uniform source\n"); -+ if (!uniform) { -+ /* -+ * There's no way to handle the DMA -+ * requirements with this uio. We -+ * could create a separate DMA area for -+ * the result and then copy it back, -+ * but for now we just bail and return -+ * an error. Note that uio requests -+ * > SAFE_MAX_DSIZE are handled because -+ * the DMA map and segment list for the -+ * destination wil result in a -+ * destination particle list that does -+ * the necessary scatter DMA. -+ */ -+ safestats.st_iovnotuniform++; -+ err = EINVAL; -+ goto errout; -+ } -+ } else -+ re->re_dst = re->re_src; -+ } else { -+ safestats.st_badflags++; -+ err = EINVAL; -+ goto errout; -+ } -+ -+ if (re->re_dst.nsegs > 1) { -+ re->re_desc.d_dst = sc->sc_dpalloc.dma_paddr + -+ ((caddr_t) sc->sc_dpfree - (caddr_t) sc->sc_dpring); -+ for (i = 0; i < re->re_dst_nsegs; i++) { -+ pd = sc->sc_dpfree; -+ KASSERT((pd->pd_flags&3) == 0 || -+ (pd->pd_flags&3) == SAFE_PD_DONE, -+ ("bogus dest particle descriptor; flags %x", -+ pd->pd_flags)); -+ if (++(sc->sc_dpfree) == sc->sc_dpringtop) -+ sc->sc_dpfree = sc->sc_dpring; -+ pd->pd_addr = re->re_dst_segs[i].ds_addr; -+ pd->pd_flags = SAFE_PD_READY; -+ } -+ cmd0 |= SAFE_SA_CMD0_OSCATTER; -+ } else { -+ /* -+ * No need for scatter, reference the operand directly. -+ */ -+ re->re_desc.d_dst = re->re_dst_segs[0].ds_addr; -+ } -+ } -+ -+ /* -+ * All done with setup; fillin the SA command words -+ * and the packet engine descriptor. The operation -+ * is now ready for submission to the hardware. -+ */ -+ sa->sa_cmd0 = cmd0 | SAFE_SA_CMD0_IPCI | SAFE_SA_CMD0_OPCI; -+ sa->sa_cmd1 = cmd1 -+ | (coffset << SAFE_SA_CMD1_OFFSET_S) -+ | SAFE_SA_CMD1_SAREV1 /* Rev 1 SA data structure */ -+ | SAFE_SA_CMD1_SRPCI -+ ; -+ /* -+ * NB: the order of writes is important here. In case the -+ * chip is scanning the ring because of an outstanding request -+ * it might nab this one too. In that case we need to make -+ * sure the setup is complete before we write the length -+ * field of the descriptor as it signals the descriptor is -+ * ready for processing. -+ */ -+ re->re_desc.d_csr = SAFE_PE_CSR_READY | SAFE_PE_CSR_SAPCI; -+ if (maccrd) -+ re->re_desc.d_csr |= SAFE_PE_CSR_LOADSA | SAFE_PE_CSR_HASHFINAL; -+ wmb(); -+ re->re_desc.d_len = oplen -+ | SAFE_PE_LEN_READY -+ | (bypass << SAFE_PE_LEN_BYPASS_S) -+ ; -+ -+ safestats.st_ipackets++; -+ safestats.st_ibytes += oplen; -+ -+ if (++(sc->sc_front) == sc->sc_ringtop) -+ sc->sc_front = sc->sc_ring; -+ -+ /* XXX honor batching */ -+ safe_feed(sc, re); -+ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); -+ return (0); -+ -+errout: -+ if (re->re_src.map != re->re_dst.map) -+ pci_unmap_operand(sc, &re->re_dst); -+ if (re->re_src.map) -+ pci_unmap_operand(sc, &re->re_src); -+ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); -+ if (err != ERESTART) { -+ crp->crp_etype = err; -+ crypto_done(crp); -+ } else { -+ sc->sc_needwakeup |= CRYPTO_SYMQ; -+ } -+ return (err); -+} -+ -+static void -+safe_callback(struct safe_softc *sc, struct safe_ringentry *re) -+{ -+ struct cryptop *crp = (struct cryptop *)re->re_crp; -+ struct cryptodesc *crd; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ safestats.st_opackets++; -+ safestats.st_obytes += re->re_dst.mapsize; -+ -+ if (re->re_desc.d_csr & SAFE_PE_CSR_STATUS) { -+ device_printf(sc->sc_dev, "csr 0x%x cmd0 0x%x cmd1 0x%x\n", -+ re->re_desc.d_csr, -+ re->re_sa.sa_cmd0, re->re_sa.sa_cmd1); -+ safestats.st_peoperr++; -+ crp->crp_etype = EIO; /* something more meaningful? */ -+ } -+ -+ if (re->re_dst.map != NULL && re->re_dst.map != re->re_src.map) -+ pci_unmap_operand(sc, &re->re_dst); -+ pci_unmap_operand(sc, &re->re_src); -+ -+ /* -+ * If result was written to a differet mbuf chain, swap -+ * it in as the return value and reclaim the original. -+ */ -+ if ((crp->crp_flags & CRYPTO_F_SKBUF) && re->re_src_skb != re->re_dst_skb) { -+ device_printf(sc->sc_dev, "no CRYPTO_F_SKBUF swapping support\n"); -+ /* kfree_skb(skb) */ -+ /* crp->crp_buf = (caddr_t)re->re_dst_skb */ -+ return; -+ } -+ -+ if (re->re_flags & SAFE_QFLAGS_COPYOUTIV) { -+ /* copy out IV for future use */ -+ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { -+ int i; -+ int ivsize; -+ -+ if (crd->crd_alg == CRYPTO_DES_CBC || -+ crd->crd_alg == CRYPTO_3DES_CBC) { -+ ivsize = 2*sizeof(u_int32_t); -+ } else if (crd->crd_alg == CRYPTO_AES_CBC) { -+ ivsize = 4*sizeof(u_int32_t); -+ } else -+ continue; -+ crypto_copydata(crp->crp_flags, crp->crp_buf, -+ crd->crd_skip + crd->crd_len - ivsize, ivsize, -+ (caddr_t)sc->sc_sessions[re->re_sesn].ses_iv); -+ for (i = 0; -+ i < ivsize/sizeof(sc->sc_sessions[re->re_sesn].ses_iv[0]); -+ i++) -+ sc->sc_sessions[re->re_sesn].ses_iv[i] = -+ cpu_to_le32(sc->sc_sessions[re->re_sesn].ses_iv[i]); -+ break; -+ } -+ } -+ -+ if (re->re_flags & SAFE_QFLAGS_COPYOUTICV) { -+ /* copy out ICV result */ -+ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { -+ if (!(crd->crd_alg == CRYPTO_MD5_HMAC || -+ crd->crd_alg == CRYPTO_SHA1_HMAC || -+ crd->crd_alg == CRYPTO_NULL_HMAC)) -+ continue; -+ if (crd->crd_alg == CRYPTO_SHA1_HMAC) { -+ /* -+ * SHA-1 ICV's are byte-swapped; fix 'em up -+ * before copy them to their destination. -+ */ -+ re->re_sastate.sa_saved_indigest[0] = -+ cpu_to_be32(re->re_sastate.sa_saved_indigest[0]); -+ re->re_sastate.sa_saved_indigest[1] = -+ cpu_to_be32(re->re_sastate.sa_saved_indigest[1]); -+ re->re_sastate.sa_saved_indigest[2] = -+ cpu_to_be32(re->re_sastate.sa_saved_indigest[2]); -+ } else { -+ re->re_sastate.sa_saved_indigest[0] = -+ cpu_to_le32(re->re_sastate.sa_saved_indigest[0]); -+ re->re_sastate.sa_saved_indigest[1] = -+ cpu_to_le32(re->re_sastate.sa_saved_indigest[1]); -+ re->re_sastate.sa_saved_indigest[2] = -+ cpu_to_le32(re->re_sastate.sa_saved_indigest[2]); -+ } -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, -+ sc->sc_sessions[re->re_sesn].ses_mlen, -+ (caddr_t)re->re_sastate.sa_saved_indigest); -+ break; -+ } -+ } -+ crypto_done(crp); -+} -+ -+ -+#if defined(CONFIG_OCF_RANDOMHARVEST) && !defined(SAFE_NO_RNG) -+#define SAFE_RNG_MAXWAIT 1000 -+ -+static void -+safe_rng_init(struct safe_softc *sc) -+{ -+ u_int32_t w, v; -+ int i; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ WRITE_REG(sc, SAFE_RNG_CTRL, 0); -+ /* use default value according to the manual */ -+ WRITE_REG(sc, SAFE_RNG_CNFG, 0x834); /* magic from SafeNet */ -+ WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); -+ -+ /* -+ * There is a bug in rev 1.0 of the 1140 that when the RNG -+ * is brought out of reset the ready status flag does not -+ * work until the RNG has finished its internal initialization. -+ * -+ * So in order to determine the device is through its -+ * initialization we must read the data register, using the -+ * status reg in the read in case it is initialized. Then read -+ * the data register until it changes from the first read. -+ * Once it changes read the data register until it changes -+ * again. At this time the RNG is considered initialized. -+ * This could take between 750ms - 1000ms in time. -+ */ -+ i = 0; -+ w = READ_REG(sc, SAFE_RNG_OUT); -+ do { -+ v = READ_REG(sc, SAFE_RNG_OUT); -+ if (v != w) { -+ w = v; -+ break; -+ } -+ DELAY(10); -+ } while (++i < SAFE_RNG_MAXWAIT); -+ -+ /* Wait Until data changes again */ -+ i = 0; -+ do { -+ v = READ_REG(sc, SAFE_RNG_OUT); -+ if (v != w) -+ break; -+ DELAY(10); -+ } while (++i < SAFE_RNG_MAXWAIT); -+} -+ -+static __inline void -+safe_rng_disable_short_cycle(struct safe_softc *sc) -+{ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ WRITE_REG(sc, SAFE_RNG_CTRL, -+ READ_REG(sc, SAFE_RNG_CTRL) &~ SAFE_RNG_CTRL_SHORTEN); -+} -+ -+static __inline void -+safe_rng_enable_short_cycle(struct safe_softc *sc) -+{ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ WRITE_REG(sc, SAFE_RNG_CTRL, -+ READ_REG(sc, SAFE_RNG_CTRL) | SAFE_RNG_CTRL_SHORTEN); -+} -+ -+static __inline u_int32_t -+safe_rng_read(struct safe_softc *sc) -+{ -+ int i; -+ -+ i = 0; -+ while (READ_REG(sc, SAFE_RNG_STAT) != 0 && ++i < SAFE_RNG_MAXWAIT) -+ ; -+ return READ_REG(sc, SAFE_RNG_OUT); -+} -+ -+static int -+safe_read_random(void *arg, u_int32_t *buf, int maxwords) -+{ -+ struct safe_softc *sc = (struct safe_softc *) arg; -+ int i, rc; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ safestats.st_rng++; -+ /* -+ * Fetch the next block of data. -+ */ -+ if (maxwords > safe_rngbufsize) -+ maxwords = safe_rngbufsize; -+ if (maxwords > SAFE_RNG_MAXBUFSIZ) -+ maxwords = SAFE_RNG_MAXBUFSIZ; -+retry: -+ /* read as much as we can */ -+ for (rc = 0; rc < maxwords; rc++) { -+ if (READ_REG(sc, SAFE_RNG_STAT) != 0) -+ break; -+ buf[rc] = READ_REG(sc, SAFE_RNG_OUT); -+ } -+ if (rc == 0) -+ return 0; -+ /* -+ * Check the comparator alarm count and reset the h/w if -+ * it exceeds our threshold. This guards against the -+ * hardware oscillators resonating with external signals. -+ */ -+ if (READ_REG(sc, SAFE_RNG_ALM_CNT) > safe_rngmaxalarm) { -+ u_int32_t freq_inc, w; -+ -+ DPRINTF(("%s: alarm count %u exceeds threshold %u\n", __func__, -+ (unsigned)READ_REG(sc, SAFE_RNG_ALM_CNT), safe_rngmaxalarm)); -+ safestats.st_rngalarm++; -+ safe_rng_enable_short_cycle(sc); -+ freq_inc = 18; -+ for (i = 0; i < 64; i++) { -+ w = READ_REG(sc, SAFE_RNG_CNFG); -+ freq_inc = ((w + freq_inc) & 0x3fL); -+ w = ((w & ~0x3fL) | freq_inc); -+ WRITE_REG(sc, SAFE_RNG_CNFG, w); -+ -+ WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); -+ -+ (void) safe_rng_read(sc); -+ DELAY(25); -+ -+ if (READ_REG(sc, SAFE_RNG_ALM_CNT) == 0) { -+ safe_rng_disable_short_cycle(sc); -+ goto retry; -+ } -+ freq_inc = 1; -+ } -+ safe_rng_disable_short_cycle(sc); -+ } else -+ WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); -+ -+ return(rc); -+} -+#endif /* defined(CONFIG_OCF_RANDOMHARVEST) && !defined(SAFE_NO_RNG) */ -+ -+ -+/* -+ * Resets the board. Values in the regesters are left as is -+ * from the reset (i.e. initial values are assigned elsewhere). -+ */ -+static void -+safe_reset_board(struct safe_softc *sc) -+{ -+ u_int32_t v; -+ /* -+ * Reset the device. The manual says no delay -+ * is needed between marking and clearing reset. -+ */ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ v = READ_REG(sc, SAFE_PE_DMACFG) &~ -+ (SAFE_PE_DMACFG_PERESET | SAFE_PE_DMACFG_PDRRESET | -+ SAFE_PE_DMACFG_SGRESET); -+ WRITE_REG(sc, SAFE_PE_DMACFG, v -+ | SAFE_PE_DMACFG_PERESET -+ | SAFE_PE_DMACFG_PDRRESET -+ | SAFE_PE_DMACFG_SGRESET); -+ WRITE_REG(sc, SAFE_PE_DMACFG, v); -+} -+ -+/* -+ * Initialize registers we need to touch only once. -+ */ -+static void -+safe_init_board(struct safe_softc *sc) -+{ -+ u_int32_t v, dwords; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ v = READ_REG(sc, SAFE_PE_DMACFG); -+ v &=~ ( SAFE_PE_DMACFG_PEMODE -+ | SAFE_PE_DMACFG_FSENA /* failsafe enable */ -+ | SAFE_PE_DMACFG_GPRPCI /* gather ring on PCI */ -+ | SAFE_PE_DMACFG_SPRPCI /* scatter ring on PCI */ -+ | SAFE_PE_DMACFG_ESDESC /* endian-swap descriptors */ -+ | SAFE_PE_DMACFG_ESPDESC /* endian-swap part. desc's */ -+ | SAFE_PE_DMACFG_ESSA /* endian-swap SA's */ -+ | SAFE_PE_DMACFG_ESPACKET /* swap the packet data */ -+ ); -+ v |= SAFE_PE_DMACFG_FSENA /* failsafe enable */ -+ | SAFE_PE_DMACFG_GPRPCI /* gather ring on PCI */ -+ | SAFE_PE_DMACFG_SPRPCI /* scatter ring on PCI */ -+ | SAFE_PE_DMACFG_ESDESC /* endian-swap descriptors */ -+ | SAFE_PE_DMACFG_ESPDESC /* endian-swap part. desc's */ -+ | SAFE_PE_DMACFG_ESSA /* endian-swap SA's */ -+#if 0 -+ | SAFE_PE_DMACFG_ESPACKET /* swap the packet data */ -+#endif -+ ; -+ WRITE_REG(sc, SAFE_PE_DMACFG, v); -+ -+#ifdef __BIG_ENDIAN -+ /* tell the safenet that we are 4321 and not 1234 */ -+ WRITE_REG(sc, SAFE_ENDIAN, 0xe4e41b1b); -+#endif -+ -+ if (sc->sc_chiprev == SAFE_REV(1,0)) { -+ /* -+ * Avoid large PCI DMA transfers. Rev 1.0 has a bug where -+ * "target mode transfers" done while the chip is DMA'ing -+ * >1020 bytes cause the hardware to lockup. To avoid this -+ * we reduce the max PCI transfer size and use small source -+ * particle descriptors (<= 256 bytes). -+ */ -+ WRITE_REG(sc, SAFE_DMA_CFG, 256); -+ device_printf(sc->sc_dev, -+ "Reduce max DMA size to %u words for rev %u.%u WAR\n", -+ (unsigned) ((READ_REG(sc, SAFE_DMA_CFG)>>2) & 0xff), -+ (unsigned) SAFE_REV_MAJ(sc->sc_chiprev), -+ (unsigned) SAFE_REV_MIN(sc->sc_chiprev)); -+ sc->sc_max_dsize = 256; -+ } else { -+ sc->sc_max_dsize = SAFE_MAX_DSIZE; -+ } -+ -+ /* NB: operands+results are overlaid */ -+ WRITE_REG(sc, SAFE_PE_PDRBASE, sc->sc_ringalloc.dma_paddr); -+ WRITE_REG(sc, SAFE_PE_RDRBASE, sc->sc_ringalloc.dma_paddr); -+ /* -+ * Configure ring entry size and number of items in the ring. -+ */ -+ KASSERT((sizeof(struct safe_ringentry) % sizeof(u_int32_t)) == 0, -+ ("PE ring entry not 32-bit aligned!")); -+ dwords = sizeof(struct safe_ringentry) / sizeof(u_int32_t); -+ WRITE_REG(sc, SAFE_PE_RINGCFG, -+ (dwords << SAFE_PE_RINGCFG_OFFSET_S) | SAFE_MAX_NQUEUE); -+ WRITE_REG(sc, SAFE_PE_RINGPOLL, 0); /* disable polling */ -+ -+ WRITE_REG(sc, SAFE_PE_GRNGBASE, sc->sc_spalloc.dma_paddr); -+ WRITE_REG(sc, SAFE_PE_SRNGBASE, sc->sc_dpalloc.dma_paddr); -+ WRITE_REG(sc, SAFE_PE_PARTSIZE, -+ (SAFE_TOTAL_DPART<<16) | SAFE_TOTAL_SPART); -+ /* -+ * NB: destination particles are fixed size. We use -+ * an mbuf cluster and require all results go to -+ * clusters or smaller. -+ */ -+ WRITE_REG(sc, SAFE_PE_PARTCFG, sc->sc_max_dsize); -+ -+ /* it's now safe to enable PE mode, do it */ -+ WRITE_REG(sc, SAFE_PE_DMACFG, v | SAFE_PE_DMACFG_PEMODE); -+ -+ /* -+ * Configure hardware to use level-triggered interrupts and -+ * to interrupt after each descriptor is processed. -+ */ -+ WRITE_REG(sc, SAFE_HI_CFG, SAFE_HI_CFG_LEVEL); -+ WRITE_REG(sc, SAFE_HI_CLR, 0xffffffff); -+ WRITE_REG(sc, SAFE_HI_DESC_CNT, 1); -+ WRITE_REG(sc, SAFE_HI_MASK, SAFE_INT_PE_DDONE | SAFE_INT_PE_ERROR); -+} -+ -+ -+/* -+ * Clean up after a chip crash. -+ * It is assumed that the caller in splimp() -+ */ -+static void -+safe_cleanchip(struct safe_softc *sc) -+{ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (sc->sc_nqchip != 0) { -+ struct safe_ringentry *re = sc->sc_back; -+ -+ while (re != sc->sc_front) { -+ if (re->re_desc.d_csr != 0) -+ safe_free_entry(sc, re); -+ if (++re == sc->sc_ringtop) -+ re = sc->sc_ring; -+ } -+ sc->sc_back = re; -+ sc->sc_nqchip = 0; -+ } -+} -+ -+/* -+ * free a safe_q -+ * It is assumed that the caller is within splimp(). -+ */ -+static int -+safe_free_entry(struct safe_softc *sc, struct safe_ringentry *re) -+{ -+ struct cryptop *crp; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ /* -+ * Free header MCR -+ */ -+ if ((re->re_dst_skb != NULL) && (re->re_src_skb != re->re_dst_skb)) -+#ifdef NOTYET -+ m_freem(re->re_dst_m); -+#else -+ printk("%s,%d: SKB not supported\n", __FILE__, __LINE__); -+#endif -+ -+ crp = (struct cryptop *)re->re_crp; -+ -+ re->re_desc.d_csr = 0; -+ -+ crp->crp_etype = EFAULT; -+ crypto_done(crp); -+ return(0); -+} -+ -+/* -+ * Routine to reset the chip and clean up. -+ * It is assumed that the caller is in splimp() -+ */ -+static void -+safe_totalreset(struct safe_softc *sc) -+{ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ safe_reset_board(sc); -+ safe_init_board(sc); -+ safe_cleanchip(sc); -+} -+ -+/* -+ * Is the operand suitable aligned for direct DMA. Each -+ * segment must be aligned on a 32-bit boundary and all -+ * but the last segment must be a multiple of 4 bytes. -+ */ -+static int -+safe_dmamap_aligned(struct safe_softc *sc, const struct safe_operand *op) -+{ -+ int i; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ for (i = 0; i < op->nsegs; i++) { -+ if (op->segs[i].ds_addr & 3) -+ return (0); -+ if (i != (op->nsegs - 1) && (op->segs[i].ds_len & 3)) -+ return (0); -+ } -+ return (1); -+} -+ -+/* -+ * Is the operand suitable for direct DMA as the destination -+ * of an operation. The hardware requires that each ``particle'' -+ * but the last in an operation result have the same size. We -+ * fix that size at SAFE_MAX_DSIZE bytes. This routine returns -+ * 0 if some segment is not a multiple of of this size, 1 if all -+ * segments are exactly this size, or 2 if segments are at worst -+ * a multple of this size. -+ */ -+static int -+safe_dmamap_uniform(struct safe_softc *sc, const struct safe_operand *op) -+{ -+ int result = 1; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (op->nsegs > 0) { -+ int i; -+ -+ for (i = 0; i < op->nsegs-1; i++) { -+ if (op->segs[i].ds_len % sc->sc_max_dsize) -+ return (0); -+ if (op->segs[i].ds_len != sc->sc_max_dsize) -+ result = 2; -+ } -+ } -+ return (result); -+} -+ -+static int -+safe_kprocess(device_t dev, struct cryptkop *krp, int hint) -+{ -+ struct safe_softc *sc = device_get_softc(dev); -+ struct safe_pkq *q; -+ unsigned long flags; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (sc == NULL) { -+ krp->krp_status = EINVAL; -+ goto err; -+ } -+ -+ if (krp->krp_op != CRK_MOD_EXP) { -+ krp->krp_status = EOPNOTSUPP; -+ goto err; -+ } -+ -+ q = (struct safe_pkq *) kmalloc(sizeof(*q), GFP_KERNEL); -+ if (q == NULL) { -+ krp->krp_status = ENOMEM; -+ goto err; -+ } -+ memset(q, 0, sizeof(*q)); -+ q->pkq_krp = krp; -+ INIT_LIST_HEAD(&q->pkq_list); -+ -+ spin_lock_irqsave(&sc->sc_pkmtx, flags); -+ list_add_tail(&q->pkq_list, &sc->sc_pkq); -+ safe_kfeed(sc); -+ spin_unlock_irqrestore(&sc->sc_pkmtx, flags); -+ return (0); -+ -+err: -+ crypto_kdone(krp); -+ return (0); -+} -+ -+#define SAFE_CRK_PARAM_BASE 0 -+#define SAFE_CRK_PARAM_EXP 1 -+#define SAFE_CRK_PARAM_MOD 2 -+ -+static int -+safe_kstart(struct safe_softc *sc) -+{ -+ struct cryptkop *krp = sc->sc_pkq_cur->pkq_krp; -+ int exp_bits, mod_bits, base_bits; -+ u_int32_t op, a_off, b_off, c_off, d_off; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (krp->krp_iparams < 3 || krp->krp_oparams != 1) { -+ krp->krp_status = EINVAL; -+ return (1); -+ } -+ -+ base_bits = safe_ksigbits(sc, &krp->krp_param[SAFE_CRK_PARAM_BASE]); -+ if (base_bits > 2048) -+ goto too_big; -+ if (base_bits <= 0) /* 5. base not zero */ -+ goto too_small; -+ -+ exp_bits = safe_ksigbits(sc, &krp->krp_param[SAFE_CRK_PARAM_EXP]); -+ if (exp_bits > 2048) -+ goto too_big; -+ if (exp_bits <= 0) /* 1. exponent word length > 0 */ -+ goto too_small; /* 4. exponent not zero */ -+ -+ mod_bits = safe_ksigbits(sc, &krp->krp_param[SAFE_CRK_PARAM_MOD]); -+ if (mod_bits > 2048) -+ goto too_big; -+ if (mod_bits <= 32) /* 2. modulus word length > 1 */ -+ goto too_small; /* 8. MSW of modulus != zero */ -+ if (mod_bits < exp_bits) /* 3 modulus len >= exponent len */ -+ goto too_small; -+ if ((krp->krp_param[SAFE_CRK_PARAM_MOD].crp_p[0] & 1) == 0) -+ goto bad_domain; /* 6. modulus is odd */ -+ if (mod_bits > krp->krp_param[krp->krp_iparams].crp_nbits) -+ goto too_small; /* make sure result will fit */ -+ -+ /* 7. modulus > base */ -+ if (mod_bits < base_bits) -+ goto too_small; -+ if (mod_bits == base_bits) { -+ u_int8_t *basep, *modp; -+ int i; -+ -+ basep = krp->krp_param[SAFE_CRK_PARAM_BASE].crp_p + -+ ((base_bits + 7) / 8) - 1; -+ modp = krp->krp_param[SAFE_CRK_PARAM_MOD].crp_p + -+ ((mod_bits + 7) / 8) - 1; -+ -+ for (i = 0; i < (mod_bits + 7) / 8; i++, basep--, modp--) { -+ if (*modp < *basep) -+ goto too_small; -+ if (*modp > *basep) -+ break; -+ } -+ } -+ -+ /* And on the 9th step, he rested. */ -+ -+ WRITE_REG(sc, SAFE_PK_A_LEN, (exp_bits + 31) / 32); -+ WRITE_REG(sc, SAFE_PK_B_LEN, (mod_bits + 31) / 32); -+ if (mod_bits > 1024) { -+ op = SAFE_PK_FUNC_EXP4; -+ a_off = 0x000; -+ b_off = 0x100; -+ c_off = 0x200; -+ d_off = 0x300; -+ } else { -+ op = SAFE_PK_FUNC_EXP16; -+ a_off = 0x000; -+ b_off = 0x080; -+ c_off = 0x100; -+ d_off = 0x180; -+ } -+ sc->sc_pk_reslen = b_off - a_off; -+ sc->sc_pk_resoff = d_off; -+ -+ /* A is exponent, B is modulus, C is base, D is result */ -+ safe_kload_reg(sc, a_off, b_off - a_off, -+ &krp->krp_param[SAFE_CRK_PARAM_EXP]); -+ WRITE_REG(sc, SAFE_PK_A_ADDR, a_off >> 2); -+ safe_kload_reg(sc, b_off, b_off - a_off, -+ &krp->krp_param[SAFE_CRK_PARAM_MOD]); -+ WRITE_REG(sc, SAFE_PK_B_ADDR, b_off >> 2); -+ safe_kload_reg(sc, c_off, b_off - a_off, -+ &krp->krp_param[SAFE_CRK_PARAM_BASE]); -+ WRITE_REG(sc, SAFE_PK_C_ADDR, c_off >> 2); -+ WRITE_REG(sc, SAFE_PK_D_ADDR, d_off >> 2); -+ -+ WRITE_REG(sc, SAFE_PK_FUNC, op | SAFE_PK_FUNC_RUN); -+ -+ return (0); -+ -+too_big: -+ krp->krp_status = E2BIG; -+ return (1); -+too_small: -+ krp->krp_status = ERANGE; -+ return (1); -+bad_domain: -+ krp->krp_status = EDOM; -+ return (1); -+} -+ -+static int -+safe_ksigbits(struct safe_softc *sc, struct crparam *cr) -+{ -+ u_int plen = (cr->crp_nbits + 7) / 8; -+ int i, sig = plen * 8; -+ u_int8_t c, *p = cr->crp_p; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ for (i = plen - 1; i >= 0; i--) { -+ c = p[i]; -+ if (c != 0) { -+ while ((c & 0x80) == 0) { -+ sig--; -+ c <<= 1; -+ } -+ break; -+ } -+ sig -= 8; -+ } -+ return (sig); -+} -+ -+static void -+safe_kfeed(struct safe_softc *sc) -+{ -+ struct safe_pkq *q, *tmp; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (list_empty(&sc->sc_pkq) && sc->sc_pkq_cur == NULL) -+ return; -+ if (sc->sc_pkq_cur != NULL) -+ return; -+ list_for_each_entry_safe(q, tmp, &sc->sc_pkq, pkq_list) { -+ sc->sc_pkq_cur = q; -+ list_del(&q->pkq_list); -+ if (safe_kstart(sc) != 0) { -+ crypto_kdone(q->pkq_krp); -+ kfree(q); -+ sc->sc_pkq_cur = NULL; -+ } else { -+ /* op started, start polling */ -+ mod_timer(&sc->sc_pkto, jiffies + 1); -+ break; -+ } -+ } -+} -+ -+static void -+safe_kpoll(unsigned long arg) -+{ -+ struct safe_softc *sc = NULL; -+ struct safe_pkq *q; -+ struct crparam *res; -+ int i; -+ u_int32_t buf[64]; -+ unsigned long flags; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (arg >= SAFE_MAX_CHIPS) -+ return; -+ sc = safe_chip_idx[arg]; -+ if (!sc) { -+ DPRINTF(("%s() - bad callback\n", __FUNCTION__)); -+ return; -+ } -+ -+ spin_lock_irqsave(&sc->sc_pkmtx, flags); -+ if (sc->sc_pkq_cur == NULL) -+ goto out; -+ if (READ_REG(sc, SAFE_PK_FUNC) & SAFE_PK_FUNC_RUN) { -+ /* still running, check back later */ -+ mod_timer(&sc->sc_pkto, jiffies + 1); -+ goto out; -+ } -+ -+ q = sc->sc_pkq_cur; -+ res = &q->pkq_krp->krp_param[q->pkq_krp->krp_iparams]; -+ bzero(buf, sizeof(buf)); -+ bzero(res->crp_p, (res->crp_nbits + 7) / 8); -+ for (i = 0; i < sc->sc_pk_reslen >> 2; i++) -+ buf[i] = le32_to_cpu(READ_REG(sc, SAFE_PK_RAM_START + -+ sc->sc_pk_resoff + (i << 2))); -+ bcopy(buf, res->crp_p, (res->crp_nbits + 7) / 8); -+ /* -+ * reduce the bits that need copying if possible -+ */ -+ res->crp_nbits = min(res->crp_nbits,sc->sc_pk_reslen * 8); -+ res->crp_nbits = safe_ksigbits(sc, res); -+ -+ for (i = SAFE_PK_RAM_START; i < SAFE_PK_RAM_END; i += 4) -+ WRITE_REG(sc, i, 0); -+ -+ crypto_kdone(q->pkq_krp); -+ kfree(q); -+ sc->sc_pkq_cur = NULL; -+ -+ safe_kfeed(sc); -+out: -+ spin_unlock_irqrestore(&sc->sc_pkmtx, flags); -+} -+ -+static void -+safe_kload_reg(struct safe_softc *sc, u_int32_t off, u_int32_t len, -+ struct crparam *n) -+{ -+ u_int32_t buf[64], i; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ bzero(buf, sizeof(buf)); -+ bcopy(n->crp_p, buf, (n->crp_nbits + 7) / 8); -+ -+ for (i = 0; i < len >> 2; i++) -+ WRITE_REG(sc, SAFE_PK_RAM_START + off + (i << 2), -+ cpu_to_le32(buf[i])); -+} -+ -+#ifdef SAFE_DEBUG -+static void -+safe_dump_dmastatus(struct safe_softc *sc, const char *tag) -+{ -+ printf("%s: ENDIAN 0x%x SRC 0x%x DST 0x%x STAT 0x%x\n" -+ , tag -+ , READ_REG(sc, SAFE_DMA_ENDIAN) -+ , READ_REG(sc, SAFE_DMA_SRCADDR) -+ , READ_REG(sc, SAFE_DMA_DSTADDR) -+ , READ_REG(sc, SAFE_DMA_STAT) -+ ); -+} -+ -+static void -+safe_dump_intrstate(struct safe_softc *sc, const char *tag) -+{ -+ printf("%s: HI_CFG 0x%x HI_MASK 0x%x HI_DESC_CNT 0x%x HU_STAT 0x%x HM_STAT 0x%x\n" -+ , tag -+ , READ_REG(sc, SAFE_HI_CFG) -+ , READ_REG(sc, SAFE_HI_MASK) -+ , READ_REG(sc, SAFE_HI_DESC_CNT) -+ , READ_REG(sc, SAFE_HU_STAT) -+ , READ_REG(sc, SAFE_HM_STAT) -+ ); -+} -+ -+static void -+safe_dump_ringstate(struct safe_softc *sc, const char *tag) -+{ -+ u_int32_t estat = READ_REG(sc, SAFE_PE_ERNGSTAT); -+ -+ /* NB: assume caller has lock on ring */ -+ printf("%s: ERNGSTAT %x (next %u) back %lu front %lu\n", -+ tag, -+ estat, (estat >> SAFE_PE_ERNGSTAT_NEXT_S), -+ (unsigned long)(sc->sc_back - sc->sc_ring), -+ (unsigned long)(sc->sc_front - sc->sc_ring)); -+} -+ -+static void -+safe_dump_request(struct safe_softc *sc, const char* tag, struct safe_ringentry *re) -+{ -+ int ix, nsegs; -+ -+ ix = re - sc->sc_ring; -+ printf("%s: %p (%u): csr %x src %x dst %x sa %x len %x\n" -+ , tag -+ , re, ix -+ , re->re_desc.d_csr -+ , re->re_desc.d_src -+ , re->re_desc.d_dst -+ , re->re_desc.d_sa -+ , re->re_desc.d_len -+ ); -+ if (re->re_src.nsegs > 1) { -+ ix = (re->re_desc.d_src - sc->sc_spalloc.dma_paddr) / -+ sizeof(struct safe_pdesc); -+ for (nsegs = re->re_src.nsegs; nsegs; nsegs--) { -+ printf(" spd[%u] %p: %p size %u flags %x" -+ , ix, &sc->sc_spring[ix] -+ , (caddr_t)(uintptr_t) sc->sc_spring[ix].pd_addr -+ , sc->sc_spring[ix].pd_size -+ , sc->sc_spring[ix].pd_flags -+ ); -+ if (sc->sc_spring[ix].pd_size == 0) -+ printf(" (zero!)"); -+ printf("\n"); -+ if (++ix == SAFE_TOTAL_SPART) -+ ix = 0; -+ } -+ } -+ if (re->re_dst.nsegs > 1) { -+ ix = (re->re_desc.d_dst - sc->sc_dpalloc.dma_paddr) / -+ sizeof(struct safe_pdesc); -+ for (nsegs = re->re_dst.nsegs; nsegs; nsegs--) { -+ printf(" dpd[%u] %p: %p flags %x\n" -+ , ix, &sc->sc_dpring[ix] -+ , (caddr_t)(uintptr_t) sc->sc_dpring[ix].pd_addr -+ , sc->sc_dpring[ix].pd_flags -+ ); -+ if (++ix == SAFE_TOTAL_DPART) -+ ix = 0; -+ } -+ } -+ printf("sa: cmd0 %08x cmd1 %08x staterec %x\n", -+ re->re_sa.sa_cmd0, re->re_sa.sa_cmd1, re->re_sa.sa_staterec); -+ printf("sa: key %x %x %x %x %x %x %x %x\n" -+ , re->re_sa.sa_key[0] -+ , re->re_sa.sa_key[1] -+ , re->re_sa.sa_key[2] -+ , re->re_sa.sa_key[3] -+ , re->re_sa.sa_key[4] -+ , re->re_sa.sa_key[5] -+ , re->re_sa.sa_key[6] -+ , re->re_sa.sa_key[7] -+ ); -+ printf("sa: indigest %x %x %x %x %x\n" -+ , re->re_sa.sa_indigest[0] -+ , re->re_sa.sa_indigest[1] -+ , re->re_sa.sa_indigest[2] -+ , re->re_sa.sa_indigest[3] -+ , re->re_sa.sa_indigest[4] -+ ); -+ printf("sa: outdigest %x %x %x %x %x\n" -+ , re->re_sa.sa_outdigest[0] -+ , re->re_sa.sa_outdigest[1] -+ , re->re_sa.sa_outdigest[2] -+ , re->re_sa.sa_outdigest[3] -+ , re->re_sa.sa_outdigest[4] -+ ); -+ printf("sr: iv %x %x %x %x\n" -+ , re->re_sastate.sa_saved_iv[0] -+ , re->re_sastate.sa_saved_iv[1] -+ , re->re_sastate.sa_saved_iv[2] -+ , re->re_sastate.sa_saved_iv[3] -+ ); -+ printf("sr: hashbc %u indigest %x %x %x %x %x\n" -+ , re->re_sastate.sa_saved_hashbc -+ , re->re_sastate.sa_saved_indigest[0] -+ , re->re_sastate.sa_saved_indigest[1] -+ , re->re_sastate.sa_saved_indigest[2] -+ , re->re_sastate.sa_saved_indigest[3] -+ , re->re_sastate.sa_saved_indigest[4] -+ ); -+} -+ -+static void -+safe_dump_ring(struct safe_softc *sc, const char *tag) -+{ -+ unsigned long flags; -+ -+ spin_lock_irqsave(&sc->sc_ringmtx, flags); -+ printf("\nSafeNet Ring State:\n"); -+ safe_dump_intrstate(sc, tag); -+ safe_dump_dmastatus(sc, tag); -+ safe_dump_ringstate(sc, tag); -+ if (sc->sc_nqchip) { -+ struct safe_ringentry *re = sc->sc_back; -+ do { -+ safe_dump_request(sc, tag, re); -+ if (++re == sc->sc_ringtop) -+ re = sc->sc_ring; -+ } while (re != sc->sc_front); -+ } -+ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); -+} -+#endif /* SAFE_DEBUG */ -+ -+ -+static int safe_probe(struct pci_dev *dev, const struct pci_device_id *ent) -+{ -+ struct safe_softc *sc = NULL; -+ u32 mem_start, mem_len, cmd; -+ int i, rc, devinfo; -+ dma_addr_t raddr; -+ static int num_chips = 0; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (pci_enable_device(dev) < 0) -+ return(-ENODEV); -+ -+ if (!dev->irq) { -+ printk("safe: found device with no IRQ assigned. check BIOS settings!"); -+ pci_disable_device(dev); -+ return(-ENODEV); -+ } -+ -+ if (pci_set_mwi(dev)) { -+ printk("safe: pci_set_mwi failed!"); -+ return(-ENODEV); -+ } -+ -+ sc = (struct safe_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); -+ if (!sc) -+ return(-ENOMEM); -+ memset(sc, 0, sizeof(*sc)); -+ -+ softc_device_init(sc, "safe", num_chips, safe_methods); -+ -+ sc->sc_irq = -1; -+ sc->sc_cid = -1; -+ sc->sc_pcidev = dev; -+ if (num_chips < SAFE_MAX_CHIPS) { -+ safe_chip_idx[device_get_unit(sc->sc_dev)] = sc; -+ num_chips++; -+ } -+ -+ INIT_LIST_HEAD(&sc->sc_pkq); -+ spin_lock_init(&sc->sc_pkmtx); -+ -+ pci_set_drvdata(sc->sc_pcidev, sc); -+ -+ /* we read its hardware registers as memory */ -+ mem_start = pci_resource_start(sc->sc_pcidev, 0); -+ mem_len = pci_resource_len(sc->sc_pcidev, 0); -+ -+ sc->sc_base_addr = (ocf_iomem_t) ioremap(mem_start, mem_len); -+ if (!sc->sc_base_addr) { -+ device_printf(sc->sc_dev, "failed to ioremap 0x%x-0x%x\n", -+ mem_start, mem_start + mem_len - 1); -+ goto out; -+ } -+ -+ /* fix up the bus size */ -+ if (pci_set_dma_mask(sc->sc_pcidev, DMA_32BIT_MASK)) { -+ device_printf(sc->sc_dev, "No usable DMA configuration, aborting.\n"); -+ goto out; -+ } -+ if (pci_set_consistent_dma_mask(sc->sc_pcidev, DMA_32BIT_MASK)) { -+ device_printf(sc->sc_dev, "No usable consistent DMA configuration, aborting.\n"); -+ goto out; -+ } -+ -+ pci_set_master(sc->sc_pcidev); -+ -+ pci_read_config_dword(sc->sc_pcidev, PCI_COMMAND, &cmd); -+ -+ if (!(cmd & PCI_COMMAND_MEMORY)) { -+ device_printf(sc->sc_dev, "failed to enable memory mapping\n"); -+ goto out; -+ } -+ -+ if (!(cmd & PCI_COMMAND_MASTER)) { -+ device_printf(sc->sc_dev, "failed to enable bus mastering\n"); -+ goto out; -+ } -+ -+ rc = request_irq(dev->irq, safe_intr, IRQF_SHARED, "safe", sc); -+ if (rc) { -+ device_printf(sc->sc_dev, "failed to hook irq %d\n", sc->sc_irq); -+ goto out; -+ } -+ sc->sc_irq = dev->irq; -+ -+ sc->sc_chiprev = READ_REG(sc, SAFE_DEVINFO) & -+ (SAFE_DEVINFO_REV_MAJ | SAFE_DEVINFO_REV_MIN); -+ -+ /* -+ * Allocate packet engine descriptors. -+ */ -+ sc->sc_ringalloc.dma_vaddr = pci_alloc_consistent(sc->sc_pcidev, -+ SAFE_MAX_NQUEUE * sizeof (struct safe_ringentry), -+ &sc->sc_ringalloc.dma_paddr); -+ if (!sc->sc_ringalloc.dma_vaddr) { -+ device_printf(sc->sc_dev, "cannot allocate PE descriptor ring\n"); -+ goto out; -+ } -+ -+ /* -+ * Hookup the static portion of all our data structures. -+ */ -+ sc->sc_ring = (struct safe_ringentry *) sc->sc_ringalloc.dma_vaddr; -+ sc->sc_ringtop = sc->sc_ring + SAFE_MAX_NQUEUE; -+ sc->sc_front = sc->sc_ring; -+ sc->sc_back = sc->sc_ring; -+ raddr = sc->sc_ringalloc.dma_paddr; -+ bzero(sc->sc_ring, SAFE_MAX_NQUEUE * sizeof(struct safe_ringentry)); -+ for (i = 0; i < SAFE_MAX_NQUEUE; i++) { -+ struct safe_ringentry *re = &sc->sc_ring[i]; -+ -+ re->re_desc.d_sa = raddr + -+ offsetof(struct safe_ringentry, re_sa); -+ re->re_sa.sa_staterec = raddr + -+ offsetof(struct safe_ringentry, re_sastate); -+ -+ raddr += sizeof (struct safe_ringentry); -+ } -+ spin_lock_init(&sc->sc_ringmtx); -+ -+ /* -+ * Allocate scatter and gather particle descriptors. -+ */ -+ sc->sc_spalloc.dma_vaddr = pci_alloc_consistent(sc->sc_pcidev, -+ SAFE_TOTAL_SPART * sizeof (struct safe_pdesc), -+ &sc->sc_spalloc.dma_paddr); -+ if (!sc->sc_spalloc.dma_vaddr) { -+ device_printf(sc->sc_dev, "cannot allocate source particle descriptor ring\n"); -+ goto out; -+ } -+ sc->sc_spring = (struct safe_pdesc *) sc->sc_spalloc.dma_vaddr; -+ sc->sc_springtop = sc->sc_spring + SAFE_TOTAL_SPART; -+ sc->sc_spfree = sc->sc_spring; -+ bzero(sc->sc_spring, SAFE_TOTAL_SPART * sizeof(struct safe_pdesc)); -+ -+ sc->sc_dpalloc.dma_vaddr = pci_alloc_consistent(sc->sc_pcidev, -+ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), -+ &sc->sc_dpalloc.dma_paddr); -+ if (!sc->sc_dpalloc.dma_vaddr) { -+ device_printf(sc->sc_dev, "cannot allocate destination particle descriptor ring\n"); -+ goto out; -+ } -+ sc->sc_dpring = (struct safe_pdesc *) sc->sc_dpalloc.dma_vaddr; -+ sc->sc_dpringtop = sc->sc_dpring + SAFE_TOTAL_DPART; -+ sc->sc_dpfree = sc->sc_dpring; -+ bzero(sc->sc_dpring, SAFE_TOTAL_DPART * sizeof(struct safe_pdesc)); -+ -+ sc->sc_cid = crypto_get_driverid(softc_get_device(sc), CRYPTOCAP_F_HARDWARE); -+ if (sc->sc_cid < 0) { -+ device_printf(sc->sc_dev, "could not get crypto driver id\n"); -+ goto out; -+ } -+ -+ printf("%s:", device_get_nameunit(sc->sc_dev)); -+ -+ devinfo = READ_REG(sc, SAFE_DEVINFO); -+ if (devinfo & SAFE_DEVINFO_RNG) { -+ sc->sc_flags |= SAFE_FLAGS_RNG; -+ printf(" rng"); -+ } -+ if (devinfo & SAFE_DEVINFO_PKEY) { -+ printf(" key"); -+ sc->sc_flags |= SAFE_FLAGS_KEY; -+ crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0); -+#if 0 -+ crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0); -+#endif -+ init_timer(&sc->sc_pkto); -+ sc->sc_pkto.function = safe_kpoll; -+ sc->sc_pkto.data = (unsigned long) device_get_unit(sc->sc_dev); -+ } -+ if (devinfo & SAFE_DEVINFO_DES) { -+ printf(" des/3des"); -+ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); -+ } -+ if (devinfo & SAFE_DEVINFO_AES) { -+ printf(" aes"); -+ crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); -+ } -+ if (devinfo & SAFE_DEVINFO_MD5) { -+ printf(" md5"); -+ crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); -+ } -+ if (devinfo & SAFE_DEVINFO_SHA1) { -+ printf(" sha1"); -+ crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); -+ } -+ printf(" null"); -+ crypto_register(sc->sc_cid, CRYPTO_NULL_CBC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_NULL_HMAC, 0, 0); -+ /* XXX other supported algorithms */ -+ printf("\n"); -+ -+ safe_reset_board(sc); /* reset h/w */ -+ safe_init_board(sc); /* init h/w */ -+ -+#if defined(CONFIG_OCF_RANDOMHARVEST) && !defined(SAFE_NO_RNG) -+ if (sc->sc_flags & SAFE_FLAGS_RNG) { -+ safe_rng_init(sc); -+ crypto_rregister(sc->sc_cid, safe_read_random, sc); -+ } -+#endif /* SAFE_NO_RNG */ -+ -+ return (0); -+ -+out: -+ if (sc->sc_cid >= 0) -+ crypto_unregister_all(sc->sc_cid); -+ if (sc->sc_irq != -1) -+ free_irq(sc->sc_irq, sc); -+ if (sc->sc_ringalloc.dma_vaddr) -+ pci_free_consistent(sc->sc_pcidev, -+ SAFE_MAX_NQUEUE * sizeof (struct safe_ringentry), -+ sc->sc_ringalloc.dma_vaddr, sc->sc_ringalloc.dma_paddr); -+ if (sc->sc_spalloc.dma_vaddr) -+ pci_free_consistent(sc->sc_pcidev, -+ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), -+ sc->sc_spalloc.dma_vaddr, sc->sc_spalloc.dma_paddr); -+ if (sc->sc_dpalloc.dma_vaddr) -+ pci_free_consistent(sc->sc_pcidev, -+ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), -+ sc->sc_dpalloc.dma_vaddr, sc->sc_dpalloc.dma_paddr); -+ kfree(sc); -+ return(-ENODEV); -+} -+ -+static void safe_remove(struct pci_dev *dev) -+{ -+ struct safe_softc *sc = pci_get_drvdata(dev); -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ /* XXX wait/abort active ops */ -+ -+ WRITE_REG(sc, SAFE_HI_MASK, 0); /* disable interrupts */ -+ -+ del_timer_sync(&sc->sc_pkto); -+ -+ crypto_unregister_all(sc->sc_cid); -+ -+ safe_cleanchip(sc); -+ -+ if (sc->sc_irq != -1) -+ free_irq(sc->sc_irq, sc); -+ if (sc->sc_ringalloc.dma_vaddr) -+ pci_free_consistent(sc->sc_pcidev, -+ SAFE_MAX_NQUEUE * sizeof (struct safe_ringentry), -+ sc->sc_ringalloc.dma_vaddr, sc->sc_ringalloc.dma_paddr); -+ if (sc->sc_spalloc.dma_vaddr) -+ pci_free_consistent(sc->sc_pcidev, -+ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), -+ sc->sc_spalloc.dma_vaddr, sc->sc_spalloc.dma_paddr); -+ if (sc->sc_dpalloc.dma_vaddr) -+ pci_free_consistent(sc->sc_pcidev, -+ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), -+ sc->sc_dpalloc.dma_vaddr, sc->sc_dpalloc.dma_paddr); -+ sc->sc_irq = -1; -+ sc->sc_ringalloc.dma_vaddr = NULL; -+ sc->sc_spalloc.dma_vaddr = NULL; -+ sc->sc_dpalloc.dma_vaddr = NULL; -+} -+ -+static struct pci_device_id safe_pci_tbl[] = { -+ { PCI_VENDOR_SAFENET, PCI_PRODUCT_SAFEXCEL, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ { }, -+}; -+MODULE_DEVICE_TABLE(pci, safe_pci_tbl); -+ -+static struct pci_driver safe_driver = { -+ .name = "safe", -+ .id_table = safe_pci_tbl, -+ .probe = safe_probe, -+ .remove = safe_remove, -+ /* add PM stuff here one day */ -+}; -+ -+static int __init safe_init (void) -+{ -+ struct safe_softc *sc = NULL; -+ int rc; -+ -+ DPRINTF(("%s(%p)\n", __FUNCTION__, safe_init)); -+ -+ rc = pci_register_driver(&safe_driver); -+ pci_register_driver_compat(&safe_driver, rc); -+ -+ return rc; -+} -+ -+static void __exit safe_exit (void) -+{ -+ pci_unregister_driver(&safe_driver); -+} -+ -+module_init(safe_init); -+module_exit(safe_exit); -+ -+MODULE_LICENSE("BSD"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("OCF driver for safenet PCI crypto devices"); -diff -Nur linux-2.6.36.orig/crypto/ocf/safe/safereg.h linux-2.6.36/crypto/ocf/safe/safereg.h ---- linux-2.6.36.orig/crypto/ocf/safe/safereg.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/safe/safereg.h 2010-11-09 20:28:12.962495464 +0100 -@@ -0,0 +1,421 @@ -+/*- -+ * Copyright (c) 2003 Sam Leffler, Errno Consulting -+ * Copyright (c) 2003 Global Technology Associates, Inc. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ * -+ * $FreeBSD: src/sys/dev/safe/safereg.h,v 1.1 2003/07/21 21:46:07 sam Exp $ -+ */ -+#ifndef _SAFE_SAFEREG_H_ -+#define _SAFE_SAFEREG_H_ -+ -+/* -+ * Register definitions for SafeNet SafeXcel-1141 crypto device. -+ * Definitions from revision 1.3 (Nov 6 2002) of the User's Manual. -+ */ -+ -+#define BS_BAR 0x10 /* DMA base address register */ -+#define BS_TRDY_TIMEOUT 0x40 /* TRDY timeout */ -+#define BS_RETRY_TIMEOUT 0x41 /* DMA retry timeout */ -+ -+#define PCI_VENDOR_SAFENET 0x16ae /* SafeNet, Inc. */ -+ -+/* SafeNet */ -+#define PCI_PRODUCT_SAFEXCEL 0x1141 /* 1141 */ -+ -+#define SAFE_PE_CSR 0x0000 /* Packet Enginge Ctrl/Status */ -+#define SAFE_PE_SRC 0x0004 /* Packet Engine Source */ -+#define SAFE_PE_DST 0x0008 /* Packet Engine Destination */ -+#define SAFE_PE_SA 0x000c /* Packet Engine SA */ -+#define SAFE_PE_LEN 0x0010 /* Packet Engine Length */ -+#define SAFE_PE_DMACFG 0x0040 /* Packet Engine DMA Configuration */ -+#define SAFE_PE_DMASTAT 0x0044 /* Packet Engine DMA Status */ -+#define SAFE_PE_PDRBASE 0x0048 /* Packet Engine Descriptor Ring Base */ -+#define SAFE_PE_RDRBASE 0x004c /* Packet Engine Result Ring Base */ -+#define SAFE_PE_RINGCFG 0x0050 /* Packet Engine Ring Configuration */ -+#define SAFE_PE_RINGPOLL 0x0054 /* Packet Engine Ring Poll */ -+#define SAFE_PE_IRNGSTAT 0x0058 /* Packet Engine Internal Ring Status */ -+#define SAFE_PE_ERNGSTAT 0x005c /* Packet Engine External Ring Status */ -+#define SAFE_PE_IOTHRESH 0x0060 /* Packet Engine I/O Threshold */ -+#define SAFE_PE_GRNGBASE 0x0064 /* Packet Engine Gather Ring Base */ -+#define SAFE_PE_SRNGBASE 0x0068 /* Packet Engine Scatter Ring Base */ -+#define SAFE_PE_PARTSIZE 0x006c /* Packet Engine Particlar Ring Size */ -+#define SAFE_PE_PARTCFG 0x0070 /* Packet Engine Particle Ring Config */ -+#define SAFE_CRYPTO_CTRL 0x0080 /* Crypto Control */ -+#define SAFE_DEVID 0x0084 /* Device ID */ -+#define SAFE_DEVINFO 0x0088 /* Device Info */ -+#define SAFE_HU_STAT 0x00a0 /* Host Unmasked Status */ -+#define SAFE_HM_STAT 0x00a4 /* Host Masked Status (read-only) */ -+#define SAFE_HI_CLR 0x00a4 /* Host Clear Interrupt (write-only) */ -+#define SAFE_HI_MASK 0x00a8 /* Host Mask Control */ -+#define SAFE_HI_CFG 0x00ac /* Interrupt Configuration */ -+#define SAFE_HI_RD_DESCR 0x00b4 /* Force Descriptor Read */ -+#define SAFE_HI_DESC_CNT 0x00b8 /* Host Descriptor Done Count */ -+#define SAFE_DMA_ENDIAN 0x00c0 /* Master Endian Status */ -+#define SAFE_DMA_SRCADDR 0x00c4 /* DMA Source Address Status */ -+#define SAFE_DMA_DSTADDR 0x00c8 /* DMA Destination Address Status */ -+#define SAFE_DMA_STAT 0x00cc /* DMA Current Status */ -+#define SAFE_DMA_CFG 0x00d4 /* DMA Configuration/Status */ -+#define SAFE_ENDIAN 0x00e0 /* Endian Configuration */ -+#define SAFE_PK_A_ADDR 0x0800 /* Public Key A Address */ -+#define SAFE_PK_B_ADDR 0x0804 /* Public Key B Address */ -+#define SAFE_PK_C_ADDR 0x0808 /* Public Key C Address */ -+#define SAFE_PK_D_ADDR 0x080c /* Public Key D Address */ -+#define SAFE_PK_A_LEN 0x0810 /* Public Key A Length */ -+#define SAFE_PK_B_LEN 0x0814 /* Public Key B Length */ -+#define SAFE_PK_SHIFT 0x0818 /* Public Key Shift */ -+#define SAFE_PK_FUNC 0x081c /* Public Key Function */ -+#define SAFE_PK_RAM_START 0x1000 /* Public Key RAM start address */ -+#define SAFE_PK_RAM_END 0x1fff /* Public Key RAM end address */ -+ -+#define SAFE_RNG_OUT 0x0100 /* RNG Output */ -+#define SAFE_RNG_STAT 0x0104 /* RNG Status */ -+#define SAFE_RNG_CTRL 0x0108 /* RNG Control */ -+#define SAFE_RNG_A 0x010c /* RNG A */ -+#define SAFE_RNG_B 0x0110 /* RNG B */ -+#define SAFE_RNG_X_LO 0x0114 /* RNG X [31:0] */ -+#define SAFE_RNG_X_MID 0x0118 /* RNG X [63:32] */ -+#define SAFE_RNG_X_HI 0x011c /* RNG X [80:64] */ -+#define SAFE_RNG_X_CNTR 0x0120 /* RNG Counter */ -+#define SAFE_RNG_ALM_CNT 0x0124 /* RNG Alarm Count */ -+#define SAFE_RNG_CNFG 0x0128 /* RNG Configuration */ -+#define SAFE_RNG_LFSR1_LO 0x012c /* RNG LFSR1 [31:0] */ -+#define SAFE_RNG_LFSR1_HI 0x0130 /* RNG LFSR1 [47:32] */ -+#define SAFE_RNG_LFSR2_LO 0x0134 /* RNG LFSR1 [31:0] */ -+#define SAFE_RNG_LFSR2_HI 0x0138 /* RNG LFSR1 [47:32] */ -+ -+#define SAFE_PE_CSR_READY 0x00000001 /* ready for processing */ -+#define SAFE_PE_CSR_DONE 0x00000002 /* h/w completed processing */ -+#define SAFE_PE_CSR_LOADSA 0x00000004 /* load SA digests */ -+#define SAFE_PE_CSR_HASHFINAL 0x00000010 /* do hash pad & write result */ -+#define SAFE_PE_CSR_SABUSID 0x000000c0 /* bus id for SA */ -+#define SAFE_PE_CSR_SAPCI 0x00000040 /* PCI bus id for SA */ -+#define SAFE_PE_CSR_NXTHDR 0x0000ff00 /* next hdr value for IPsec */ -+#define SAFE_PE_CSR_FPAD 0x0000ff00 /* fixed pad for basic ops */ -+#define SAFE_PE_CSR_STATUS 0x00ff0000 /* operation result status */ -+#define SAFE_PE_CSR_AUTH_FAIL 0x00010000 /* ICV mismatch (inbound) */ -+#define SAFE_PE_CSR_PAD_FAIL 0x00020000 /* pad verify fail (inbound) */ -+#define SAFE_PE_CSR_SEQ_FAIL 0x00040000 /* sequence number (inbound) */ -+#define SAFE_PE_CSR_XERROR 0x00080000 /* extended error follows */ -+#define SAFE_PE_CSR_XECODE 0x00f00000 /* extended error code */ -+#define SAFE_PE_CSR_XECODE_S 20 -+#define SAFE_PE_CSR_XECODE_BADCMD 0 /* invalid command */ -+#define SAFE_PE_CSR_XECODE_BADALG 1 /* invalid algorithm */ -+#define SAFE_PE_CSR_XECODE_ALGDIS 2 /* algorithm disabled */ -+#define SAFE_PE_CSR_XECODE_ZEROLEN 3 /* zero packet length */ -+#define SAFE_PE_CSR_XECODE_DMAERR 4 /* bus DMA error */ -+#define SAFE_PE_CSR_XECODE_PIPEABORT 5 /* secondary bus DMA error */ -+#define SAFE_PE_CSR_XECODE_BADSPI 6 /* IPsec SPI mismatch */ -+#define SAFE_PE_CSR_XECODE_TIMEOUT 10 /* failsafe timeout */ -+#define SAFE_PE_CSR_PAD 0xff000000 /* ESP padding control/status */ -+#define SAFE_PE_CSR_PAD_MIN 0x00000000 /* minimum IPsec padding */ -+#define SAFE_PE_CSR_PAD_16 0x08000000 /* pad to 16-byte boundary */ -+#define SAFE_PE_CSR_PAD_32 0x10000000 /* pad to 32-byte boundary */ -+#define SAFE_PE_CSR_PAD_64 0x20000000 /* pad to 64-byte boundary */ -+#define SAFE_PE_CSR_PAD_128 0x40000000 /* pad to 128-byte boundary */ -+#define SAFE_PE_CSR_PAD_256 0x80000000 /* pad to 256-byte boundary */ -+ -+/* -+ * Check the CSR to see if the PE has returned ownership to -+ * the host. Note that before processing a descriptor this -+ * must be done followed by a check of the SAFE_PE_LEN register -+ * status bits to avoid premature processing of a descriptor -+ * on its way back to the host. -+ */ -+#define SAFE_PE_CSR_IS_DONE(_csr) \ -+ (((_csr) & (SAFE_PE_CSR_READY | SAFE_PE_CSR_DONE)) == SAFE_PE_CSR_DONE) -+ -+#define SAFE_PE_LEN_LENGTH 0x000fffff /* total length (bytes) */ -+#define SAFE_PE_LEN_READY 0x00400000 /* ready for processing */ -+#define SAFE_PE_LEN_DONE 0x00800000 /* h/w completed processing */ -+#define SAFE_PE_LEN_BYPASS 0xff000000 /* bypass offset (bytes) */ -+#define SAFE_PE_LEN_BYPASS_S 24 -+ -+#define SAFE_PE_LEN_IS_DONE(_len) \ -+ (((_len) & (SAFE_PE_LEN_READY | SAFE_PE_LEN_DONE)) == SAFE_PE_LEN_DONE) -+ -+/* NB: these apply to HU_STAT, HM_STAT, HI_CLR, and HI_MASK */ -+#define SAFE_INT_PE_CDONE 0x00000002 /* PE context done */ -+#define SAFE_INT_PE_DDONE 0x00000008 /* PE descriptor done */ -+#define SAFE_INT_PE_ERROR 0x00000010 /* PE error */ -+#define SAFE_INT_PE_ODONE 0x00000020 /* PE operation done */ -+ -+#define SAFE_HI_CFG_PULSE 0x00000001 /* use pulse interrupt */ -+#define SAFE_HI_CFG_LEVEL 0x00000000 /* use level interrupt */ -+#define SAFE_HI_CFG_AUTOCLR 0x00000002 /* auto-clear pulse interrupt */ -+ -+#define SAFE_ENDIAN_PASS 0x000000e4 /* straight pass-thru */ -+#define SAFE_ENDIAN_SWAB 0x0000001b /* swap bytes in 32-bit word */ -+ -+#define SAFE_PE_DMACFG_PERESET 0x00000001 /* reset packet engine */ -+#define SAFE_PE_DMACFG_PDRRESET 0x00000002 /* reset PDR counters/ptrs */ -+#define SAFE_PE_DMACFG_SGRESET 0x00000004 /* reset scatter/gather cache */ -+#define SAFE_PE_DMACFG_FSENA 0x00000008 /* enable failsafe reset */ -+#define SAFE_PE_DMACFG_PEMODE 0x00000100 /* packet engine mode */ -+#define SAFE_PE_DMACFG_SAPREC 0x00000200 /* SA precedes packet */ -+#define SAFE_PE_DMACFG_PKFOLL 0x00000400 /* packet follows descriptor */ -+#define SAFE_PE_DMACFG_GPRBID 0x00003000 /* gather particle ring busid */ -+#define SAFE_PE_DMACFG_GPRPCI 0x00001000 /* PCI gather particle ring */ -+#define SAFE_PE_DMACFG_SPRBID 0x0000c000 /* scatter part. ring busid */ -+#define SAFE_PE_DMACFG_SPRPCI 0x00004000 /* PCI scatter part. ring */ -+#define SAFE_PE_DMACFG_ESDESC 0x00010000 /* endian swap descriptors */ -+#define SAFE_PE_DMACFG_ESSA 0x00020000 /* endian swap SA data */ -+#define SAFE_PE_DMACFG_ESPACKET 0x00040000 /* endian swap packet data */ -+#define SAFE_PE_DMACFG_ESPDESC 0x00080000 /* endian swap particle desc. */ -+#define SAFE_PE_DMACFG_NOPDRUP 0x00100000 /* supp. PDR ownership update */ -+#define SAFE_PD_EDMACFG_PCIMODE 0x01000000 /* PCI target mode */ -+ -+#define SAFE_PE_DMASTAT_PEIDONE 0x00000001 /* PE core input done */ -+#define SAFE_PE_DMASTAT_PEODONE 0x00000002 /* PE core output done */ -+#define SAFE_PE_DMASTAT_ENCDONE 0x00000004 /* encryption done */ -+#define SAFE_PE_DMASTAT_IHDONE 0x00000008 /* inner hash done */ -+#define SAFE_PE_DMASTAT_OHDONE 0x00000010 /* outer hash (HMAC) done */ -+#define SAFE_PE_DMASTAT_PADFLT 0x00000020 /* crypto pad fault */ -+#define SAFE_PE_DMASTAT_ICVFLT 0x00000040 /* ICV fault */ -+#define SAFE_PE_DMASTAT_SPIMIS 0x00000080 /* SPI mismatch */ -+#define SAFE_PE_DMASTAT_CRYPTO 0x00000100 /* crypto engine timeout */ -+#define SAFE_PE_DMASTAT_CQACT 0x00000200 /* command queue active */ -+#define SAFE_PE_DMASTAT_IRACT 0x00000400 /* input request active */ -+#define SAFE_PE_DMASTAT_ORACT 0x00000800 /* output request active */ -+#define SAFE_PE_DMASTAT_PEISIZE 0x003ff000 /* PE input size:32-bit words */ -+#define SAFE_PE_DMASTAT_PEOSIZE 0xffc00000 /* PE out. size:32-bit words */ -+ -+#define SAFE_PE_RINGCFG_SIZE 0x000003ff /* ring size (descriptors) */ -+#define SAFE_PE_RINGCFG_OFFSET 0xffff0000 /* offset btw desc's (dwords) */ -+#define SAFE_PE_RINGCFG_OFFSET_S 16 -+ -+#define SAFE_PE_RINGPOLL_POLL 0x00000fff /* polling frequency/divisor */ -+#define SAFE_PE_RINGPOLL_RETRY 0x03ff0000 /* polling frequency/divisor */ -+#define SAFE_PE_RINGPOLL_CONT 0x80000000 /* continuously poll */ -+ -+#define SAFE_PE_IRNGSTAT_CQAVAIL 0x00000001 /* command queue available */ -+ -+#define SAFE_PE_ERNGSTAT_NEXT 0x03ff0000 /* index of next packet desc. */ -+#define SAFE_PE_ERNGSTAT_NEXT_S 16 -+ -+#define SAFE_PE_IOTHRESH_INPUT 0x000003ff /* input threshold (dwords) */ -+#define SAFE_PE_IOTHRESH_OUTPUT 0x03ff0000 /* output threshold (dwords) */ -+ -+#define SAFE_PE_PARTCFG_SIZE 0x0000ffff /* scatter particle size */ -+#define SAFE_PE_PARTCFG_GBURST 0x00030000 /* gather particle burst */ -+#define SAFE_PE_PARTCFG_GBURST_2 0x00000000 -+#define SAFE_PE_PARTCFG_GBURST_4 0x00010000 -+#define SAFE_PE_PARTCFG_GBURST_8 0x00020000 -+#define SAFE_PE_PARTCFG_GBURST_16 0x00030000 -+#define SAFE_PE_PARTCFG_SBURST 0x000c0000 /* scatter particle burst */ -+#define SAFE_PE_PARTCFG_SBURST_2 0x00000000 -+#define SAFE_PE_PARTCFG_SBURST_4 0x00040000 -+#define SAFE_PE_PARTCFG_SBURST_8 0x00080000 -+#define SAFE_PE_PARTCFG_SBURST_16 0x000c0000 -+ -+#define SAFE_PE_PARTSIZE_SCAT 0xffff0000 /* scatter particle ring size */ -+#define SAFE_PE_PARTSIZE_GATH 0x0000ffff /* gather particle ring size */ -+ -+#define SAFE_CRYPTO_CTRL_3DES 0x00000001 /* enable 3DES support */ -+#define SAFE_CRYPTO_CTRL_PKEY 0x00010000 /* enable public key support */ -+#define SAFE_CRYPTO_CTRL_RNG 0x00020000 /* enable RNG support */ -+ -+#define SAFE_DEVINFO_REV_MIN 0x0000000f /* minor rev for chip */ -+#define SAFE_DEVINFO_REV_MAJ 0x000000f0 /* major rev for chip */ -+#define SAFE_DEVINFO_REV_MAJ_S 4 -+#define SAFE_DEVINFO_DES 0x00000100 /* DES/3DES support present */ -+#define SAFE_DEVINFO_ARC4 0x00000200 /* ARC4 support present */ -+#define SAFE_DEVINFO_AES 0x00000400 /* AES support present */ -+#define SAFE_DEVINFO_MD5 0x00001000 /* MD5 support present */ -+#define SAFE_DEVINFO_SHA1 0x00002000 /* SHA-1 support present */ -+#define SAFE_DEVINFO_RIPEMD 0x00004000 /* RIPEMD support present */ -+#define SAFE_DEVINFO_DEFLATE 0x00010000 /* Deflate support present */ -+#define SAFE_DEVINFO_SARAM 0x00100000 /* on-chip SA RAM present */ -+#define SAFE_DEVINFO_EMIBUS 0x00200000 /* EMI bus present */ -+#define SAFE_DEVINFO_PKEY 0x00400000 /* public key support present */ -+#define SAFE_DEVINFO_RNG 0x00800000 /* RNG present */ -+ -+#define SAFE_REV(_maj, _min) (((_maj) << SAFE_DEVINFO_REV_MAJ_S) | (_min)) -+#define SAFE_REV_MAJ(_chiprev) \ -+ (((_chiprev) & SAFE_DEVINFO_REV_MAJ) >> SAFE_DEVINFO_REV_MAJ_S) -+#define SAFE_REV_MIN(_chiprev) ((_chiprev) & SAFE_DEVINFO_REV_MIN) -+ -+#define SAFE_PK_FUNC_MULT 0x00000001 /* Multiply function */ -+#define SAFE_PK_FUNC_SQUARE 0x00000004 /* Square function */ -+#define SAFE_PK_FUNC_ADD 0x00000010 /* Add function */ -+#define SAFE_PK_FUNC_SUB 0x00000020 /* Subtract function */ -+#define SAFE_PK_FUNC_LSHIFT 0x00000040 /* Left-shift function */ -+#define SAFE_PK_FUNC_RSHIFT 0x00000080 /* Right-shift function */ -+#define SAFE_PK_FUNC_DIV 0x00000100 /* Divide function */ -+#define SAFE_PK_FUNC_CMP 0x00000400 /* Compare function */ -+#define SAFE_PK_FUNC_COPY 0x00000800 /* Copy function */ -+#define SAFE_PK_FUNC_EXP16 0x00002000 /* Exponentiate (4-bit ACT) */ -+#define SAFE_PK_FUNC_EXP4 0x00004000 /* Exponentiate (2-bit ACT) */ -+#define SAFE_PK_FUNC_RUN 0x00008000 /* start/status */ -+ -+#define SAFE_RNG_STAT_BUSY 0x00000001 /* busy, data not valid */ -+ -+#define SAFE_RNG_CTRL_PRE_LFSR 0x00000001 /* enable output pre-LFSR */ -+#define SAFE_RNG_CTRL_TST_MODE 0x00000002 /* enable test mode */ -+#define SAFE_RNG_CTRL_TST_RUN 0x00000004 /* start test state machine */ -+#define SAFE_RNG_CTRL_ENA_RING1 0x00000008 /* test entropy oscillator #1 */ -+#define SAFE_RNG_CTRL_ENA_RING2 0x00000010 /* test entropy oscillator #2 */ -+#define SAFE_RNG_CTRL_DIS_ALARM 0x00000020 /* disable RNG alarm reports */ -+#define SAFE_RNG_CTRL_TST_CLOCK 0x00000040 /* enable test clock */ -+#define SAFE_RNG_CTRL_SHORTEN 0x00000080 /* shorten state timers */ -+#define SAFE_RNG_CTRL_TST_ALARM 0x00000100 /* simulate alarm state */ -+#define SAFE_RNG_CTRL_RST_LFSR 0x00000200 /* reset LFSR */ -+ -+/* -+ * Packet engine descriptor. Note that d_csr is a copy of the -+ * SAFE_PE_CSR register and all definitions apply, and d_len -+ * is a copy of the SAFE_PE_LEN register and all definitions apply. -+ * d_src and d_len may point directly to contiguous data or to a -+ * list of ``particle descriptors'' when using scatter/gather i/o. -+ */ -+struct safe_desc { -+ u_int32_t d_csr; /* per-packet control/status */ -+ u_int32_t d_src; /* source address */ -+ u_int32_t d_dst; /* destination address */ -+ u_int32_t d_sa; /* SA address */ -+ u_int32_t d_len; /* length, bypass, status */ -+}; -+ -+/* -+ * Scatter/Gather particle descriptor. -+ * -+ * NB: scatter descriptors do not specify a size; this is fixed -+ * by the setting of the SAFE_PE_PARTCFG register. -+ */ -+struct safe_pdesc { -+ u_int32_t pd_addr; /* particle address */ -+#ifdef __BIG_ENDIAN -+ u_int16_t pd_flags; /* control word */ -+ u_int16_t pd_size; /* particle size (bytes) */ -+#else -+ u_int16_t pd_flags; /* control word */ -+ u_int16_t pd_size; /* particle size (bytes) */ -+#endif -+}; -+ -+#define SAFE_PD_READY 0x0001 /* ready for processing */ -+#define SAFE_PD_DONE 0x0002 /* h/w completed processing */ -+ -+/* -+ * Security Association (SA) Record (Rev 1). One of these is -+ * required for each operation processed by the packet engine. -+ */ -+struct safe_sarec { -+ u_int32_t sa_cmd0; -+ u_int32_t sa_cmd1; -+ u_int32_t sa_resv0; -+ u_int32_t sa_resv1; -+ u_int32_t sa_key[8]; /* DES/3DES/AES key */ -+ u_int32_t sa_indigest[5]; /* inner digest */ -+ u_int32_t sa_outdigest[5]; /* outer digest */ -+ u_int32_t sa_spi; /* SPI */ -+ u_int32_t sa_seqnum; /* sequence number */ -+ u_int32_t sa_seqmask[2]; /* sequence number mask */ -+ u_int32_t sa_resv2; -+ u_int32_t sa_staterec; /* address of state record */ -+ u_int32_t sa_resv3[2]; -+ u_int32_t sa_samgmt0; /* SA management field 0 */ -+ u_int32_t sa_samgmt1; /* SA management field 0 */ -+}; -+ -+#define SAFE_SA_CMD0_OP 0x00000007 /* operation code */ -+#define SAFE_SA_CMD0_OP_CRYPT 0x00000000 /* encrypt/decrypt (basic) */ -+#define SAFE_SA_CMD0_OP_BOTH 0x00000001 /* encrypt-hash/hash-decrypto */ -+#define SAFE_SA_CMD0_OP_HASH 0x00000003 /* hash (outbound-only) */ -+#define SAFE_SA_CMD0_OP_ESP 0x00000000 /* ESP in/out (proto) */ -+#define SAFE_SA_CMD0_OP_AH 0x00000001 /* AH in/out (proto) */ -+#define SAFE_SA_CMD0_INBOUND 0x00000008 /* inbound operation */ -+#define SAFE_SA_CMD0_OUTBOUND 0x00000000 /* outbound operation */ -+#define SAFE_SA_CMD0_GROUP 0x00000030 /* operation group */ -+#define SAFE_SA_CMD0_BASIC 0x00000000 /* basic operation */ -+#define SAFE_SA_CMD0_PROTO 0x00000010 /* protocol/packet operation */ -+#define SAFE_SA_CMD0_BUNDLE 0x00000020 /* bundled operation (resvd) */ -+#define SAFE_SA_CMD0_PAD 0x000000c0 /* crypto pad method */ -+#define SAFE_SA_CMD0_PAD_IPSEC 0x00000000 /* IPsec padding */ -+#define SAFE_SA_CMD0_PAD_PKCS7 0x00000040 /* PKCS#7 padding */ -+#define SAFE_SA_CMD0_PAD_CONS 0x00000080 /* constant padding */ -+#define SAFE_SA_CMD0_PAD_ZERO 0x000000c0 /* zero padding */ -+#define SAFE_SA_CMD0_CRYPT_ALG 0x00000f00 /* symmetric crypto algorithm */ -+#define SAFE_SA_CMD0_DES 0x00000000 /* DES crypto algorithm */ -+#define SAFE_SA_CMD0_3DES 0x00000100 /* 3DES crypto algorithm */ -+#define SAFE_SA_CMD0_AES 0x00000300 /* AES crypto algorithm */ -+#define SAFE_SA_CMD0_CRYPT_NULL 0x00000f00 /* null crypto algorithm */ -+#define SAFE_SA_CMD0_HASH_ALG 0x0000f000 /* hash algorithm */ -+#define SAFE_SA_CMD0_MD5 0x00000000 /* MD5 hash algorithm */ -+#define SAFE_SA_CMD0_SHA1 0x00001000 /* SHA-1 hash algorithm */ -+#define SAFE_SA_CMD0_HASH_NULL 0x0000f000 /* null hash algorithm */ -+#define SAFE_SA_CMD0_HDR_PROC 0x00080000 /* header processing */ -+#define SAFE_SA_CMD0_IBUSID 0x00300000 /* input bus id */ -+#define SAFE_SA_CMD0_IPCI 0x00100000 /* PCI input bus id */ -+#define SAFE_SA_CMD0_OBUSID 0x00c00000 /* output bus id */ -+#define SAFE_SA_CMD0_OPCI 0x00400000 /* PCI output bus id */ -+#define SAFE_SA_CMD0_IVLD 0x03000000 /* IV loading */ -+#define SAFE_SA_CMD0_IVLD_NONE 0x00000000 /* IV no load (reuse) */ -+#define SAFE_SA_CMD0_IVLD_IBUF 0x01000000 /* IV load from input buffer */ -+#define SAFE_SA_CMD0_IVLD_STATE 0x02000000 /* IV load from state */ -+#define SAFE_SA_CMD0_HSLD 0x0c000000 /* hash state loading */ -+#define SAFE_SA_CMD0_HSLD_SA 0x00000000 /* hash state load from SA */ -+#define SAFE_SA_CMD0_HSLD_STATE 0x08000000 /* hash state load from state */ -+#define SAFE_SA_CMD0_HSLD_NONE 0x0c000000 /* hash state no load */ -+#define SAFE_SA_CMD0_SAVEIV 0x10000000 /* save IV */ -+#define SAFE_SA_CMD0_SAVEHASH 0x20000000 /* save hash state */ -+#define SAFE_SA_CMD0_IGATHER 0x40000000 /* input gather */ -+#define SAFE_SA_CMD0_OSCATTER 0x80000000 /* output scatter */ -+ -+#define SAFE_SA_CMD1_HDRCOPY 0x00000002 /* copy header to output */ -+#define SAFE_SA_CMD1_PAYCOPY 0x00000004 /* copy payload to output */ -+#define SAFE_SA_CMD1_PADCOPY 0x00000008 /* copy pad to output */ -+#define SAFE_SA_CMD1_IPV4 0x00000000 /* IPv4 protocol */ -+#define SAFE_SA_CMD1_IPV6 0x00000010 /* IPv6 protocol */ -+#define SAFE_SA_CMD1_MUTABLE 0x00000020 /* mutable bit processing */ -+#define SAFE_SA_CMD1_SRBUSID 0x000000c0 /* state record bus id */ -+#define SAFE_SA_CMD1_SRPCI 0x00000040 /* state record from PCI */ -+#define SAFE_SA_CMD1_CRMODE 0x00000300 /* crypto mode */ -+#define SAFE_SA_CMD1_ECB 0x00000000 /* ECB crypto mode */ -+#define SAFE_SA_CMD1_CBC 0x00000100 /* CBC crypto mode */ -+#define SAFE_SA_CMD1_OFB 0x00000200 /* OFB crypto mode */ -+#define SAFE_SA_CMD1_CFB 0x00000300 /* CFB crypto mode */ -+#define SAFE_SA_CMD1_CRFEEDBACK 0x00000c00 /* crypto feedback mode */ -+#define SAFE_SA_CMD1_64BIT 0x00000000 /* 64-bit crypto feedback */ -+#define SAFE_SA_CMD1_8BIT 0x00000400 /* 8-bit crypto feedback */ -+#define SAFE_SA_CMD1_1BIT 0x00000800 /* 1-bit crypto feedback */ -+#define SAFE_SA_CMD1_128BIT 0x00000c00 /* 128-bit crypto feedback */ -+#define SAFE_SA_CMD1_OPTIONS 0x00001000 /* HMAC/options mutable bit */ -+#define SAFE_SA_CMD1_HMAC SAFE_SA_CMD1_OPTIONS -+#define SAFE_SA_CMD1_SAREV1 0x00008000 /* SA Revision 1 */ -+#define SAFE_SA_CMD1_OFFSET 0x00ff0000 /* hash/crypto offset(dwords) */ -+#define SAFE_SA_CMD1_OFFSET_S 16 -+#define SAFE_SA_CMD1_AESKEYLEN 0x0f000000 /* AES key length */ -+#define SAFE_SA_CMD1_AES128 0x02000000 /* 128-bit AES key */ -+#define SAFE_SA_CMD1_AES192 0x03000000 /* 192-bit AES key */ -+#define SAFE_SA_CMD1_AES256 0x04000000 /* 256-bit AES key */ -+ -+/* -+ * Security Associate State Record (Rev 1). -+ */ -+struct safe_sastate { -+ u_int32_t sa_saved_iv[4]; /* saved IV (DES/3DES/AES) */ -+ u_int32_t sa_saved_hashbc; /* saved hash byte count */ -+ u_int32_t sa_saved_indigest[5]; /* saved inner digest */ -+}; -+#endif /* _SAFE_SAFEREG_H_ */ -diff -Nur linux-2.6.36.orig/crypto/ocf/safe/safevar.h linux-2.6.36/crypto/ocf/safe/safevar.h ---- linux-2.6.36.orig/crypto/ocf/safe/safevar.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/safe/safevar.h 2010-11-09 20:28:13.022495375 +0100 -@@ -0,0 +1,230 @@ -+/*- -+ * The linux port of this code done by David McCullough -+ * Copyright (C) 2004-2010 David McCullough -+ * The license and original author are listed below. -+ * -+ * Copyright (c) 2003 Sam Leffler, Errno Consulting -+ * Copyright (c) 2003 Global Technology Associates, Inc. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ * -+ * $FreeBSD: src/sys/dev/safe/safevar.h,v 1.2 2006/05/17 18:34:26 pjd Exp $ -+ */ -+#ifndef _SAFE_SAFEVAR_H_ -+#define _SAFE_SAFEVAR_H_ -+ -+/* Maximum queue length */ -+#ifndef SAFE_MAX_NQUEUE -+#define SAFE_MAX_NQUEUE 60 -+#endif -+ -+#define SAFE_MAX_PART 64 /* Maximum scatter/gather depth */ -+#define SAFE_DMA_BOUNDARY 0 /* No boundary for source DMA ops */ -+#define SAFE_MAX_DSIZE 2048 /* MCLBYTES Fixed scatter particle size */ -+#define SAFE_MAX_SSIZE 0x0ffff /* Maximum gather particle size */ -+#define SAFE_MAX_DMA 0xfffff /* Maximum PE operand size (20 bits) */ -+/* total src+dst particle descriptors */ -+#define SAFE_TOTAL_DPART (SAFE_MAX_NQUEUE * SAFE_MAX_PART) -+#define SAFE_TOTAL_SPART (SAFE_MAX_NQUEUE * SAFE_MAX_PART) -+ -+#define SAFE_RNG_MAXBUFSIZ 128 /* 32-bit words */ -+ -+#define SAFE_CARD(sid) (((sid) & 0xf0000000) >> 28) -+#define SAFE_SESSION(sid) ( (sid) & 0x0fffffff) -+#define SAFE_SID(crd, sesn) (((crd) << 28) | ((sesn) & 0x0fffffff)) -+ -+#define SAFE_DEF_RTY 0xff /* PCI Retry Timeout */ -+#define SAFE_DEF_TOUT 0xff /* PCI TRDY Timeout */ -+#define SAFE_DEF_CACHELINE 0x01 /* Cache Line setting */ -+ -+#ifdef __KERNEL__ -+/* -+ * State associated with the allocation of each chunk -+ * of memory setup for DMA. -+ */ -+struct safe_dma_alloc { -+ dma_addr_t dma_paddr; -+ void *dma_vaddr; -+}; -+ -+/* -+ * Cryptographic operand state. One of these exists for each -+ * source and destination operand passed in from the crypto -+ * subsystem. When possible source and destination operands -+ * refer to the same memory. More often they are distinct. -+ * We track the virtual address of each operand as well as -+ * where each is mapped for DMA. -+ */ -+struct safe_operand { -+ union { -+ struct sk_buff *skb; -+ struct uio *io; -+ } u; -+ void *map; -+ int mapsize; /* total number of bytes in segs */ -+ struct { -+ dma_addr_t ds_addr; -+ int ds_len; -+ int ds_tlen; -+ } segs[SAFE_MAX_PART]; -+ int nsegs; -+}; -+ -+/* -+ * Packet engine ring entry and cryptographic operation state. -+ * The packet engine requires a ring of descriptors that contain -+ * pointers to various cryptographic state. However the ring -+ * configuration register allows you to specify an arbitrary size -+ * for ring entries. We use this feature to collect most of the -+ * state for each cryptographic request into one spot. Other than -+ * ring entries only the ``particle descriptors'' (scatter/gather -+ * lists) and the actual operand data are kept separate. The -+ * particle descriptors must also be organized in rings. The -+ * operand data can be located aribtrarily (modulo alignment constraints). -+ * -+ * Note that the descriptor ring is mapped onto the PCI bus so -+ * the hardware can DMA data. This means the entire ring must be -+ * contiguous. -+ */ -+struct safe_ringentry { -+ struct safe_desc re_desc; /* command descriptor */ -+ struct safe_sarec re_sa; /* SA record */ -+ struct safe_sastate re_sastate; /* SA state record */ -+ -+ struct cryptop *re_crp; /* crypto operation */ -+ -+ struct safe_operand re_src; /* source operand */ -+ struct safe_operand re_dst; /* destination operand */ -+ -+ int re_sesn; /* crypto session ID */ -+ int re_flags; -+#define SAFE_QFLAGS_COPYOUTIV 0x1 /* copy back on completion */ -+#define SAFE_QFLAGS_COPYOUTICV 0x2 /* copy back on completion */ -+}; -+ -+#define re_src_skb re_src.u.skb -+#define re_src_io re_src.u.io -+#define re_src_map re_src.map -+#define re_src_nsegs re_src.nsegs -+#define re_src_segs re_src.segs -+#define re_src_mapsize re_src.mapsize -+ -+#define re_dst_skb re_dst.u.skb -+#define re_dst_io re_dst.u.io -+#define re_dst_map re_dst.map -+#define re_dst_nsegs re_dst.nsegs -+#define re_dst_segs re_dst.segs -+#define re_dst_mapsize re_dst.mapsize -+ -+struct rndstate_test; -+ -+struct safe_session { -+ u_int32_t ses_used; -+ u_int32_t ses_klen; /* key length in bits */ -+ u_int32_t ses_key[8]; /* DES/3DES/AES key */ -+ u_int32_t ses_mlen; /* hmac length in bytes */ -+ u_int32_t ses_hminner[5]; /* hmac inner state */ -+ u_int32_t ses_hmouter[5]; /* hmac outer state */ -+ u_int32_t ses_iv[4]; /* DES/3DES/AES iv */ -+}; -+ -+struct safe_pkq { -+ struct list_head pkq_list; -+ struct cryptkop *pkq_krp; -+}; -+ -+struct safe_softc { -+ softc_device_decl sc_dev; -+ u32 sc_irq; -+ -+ struct pci_dev *sc_pcidev; -+ ocf_iomem_t sc_base_addr; -+ -+ u_int sc_chiprev; /* major/minor chip revision */ -+ int sc_flags; /* device specific flags */ -+#define SAFE_FLAGS_KEY 0x01 /* has key accelerator */ -+#define SAFE_FLAGS_RNG 0x02 /* hardware rng */ -+ int sc_suspended; -+ int sc_needwakeup; /* notify crypto layer */ -+ int32_t sc_cid; /* crypto tag */ -+ -+ struct safe_dma_alloc sc_ringalloc; /* PE ring allocation state */ -+ struct safe_ringentry *sc_ring; /* PE ring */ -+ struct safe_ringentry *sc_ringtop; /* PE ring top */ -+ struct safe_ringentry *sc_front; /* next free entry */ -+ struct safe_ringentry *sc_back; /* next pending entry */ -+ int sc_nqchip; /* # passed to chip */ -+ spinlock_t sc_ringmtx; /* PE ring lock */ -+ struct safe_pdesc *sc_spring; /* src particle ring */ -+ struct safe_pdesc *sc_springtop; /* src particle ring top */ -+ struct safe_pdesc *sc_spfree; /* next free src particle */ -+ struct safe_dma_alloc sc_spalloc; /* src particle ring state */ -+ struct safe_pdesc *sc_dpring; /* dest particle ring */ -+ struct safe_pdesc *sc_dpringtop; /* dest particle ring top */ -+ struct safe_pdesc *sc_dpfree; /* next free dest particle */ -+ struct safe_dma_alloc sc_dpalloc; /* dst particle ring state */ -+ int sc_nsessions; /* # of sessions */ -+ struct safe_session *sc_sessions; /* sessions */ -+ -+ struct timer_list sc_pkto; /* PK polling */ -+ spinlock_t sc_pkmtx; /* PK lock */ -+ struct list_head sc_pkq; /* queue of PK requests */ -+ struct safe_pkq *sc_pkq_cur; /* current processing request */ -+ u_int32_t sc_pk_reslen, sc_pk_resoff; -+ -+ int sc_max_dsize; /* maximum safe DMA size */ -+}; -+#endif /* __KERNEL__ */ -+ -+struct safe_stats { -+ u_int64_t st_ibytes; -+ u_int64_t st_obytes; -+ u_int32_t st_ipackets; -+ u_int32_t st_opackets; -+ u_int32_t st_invalid; /* invalid argument */ -+ u_int32_t st_badsession; /* invalid session id */ -+ u_int32_t st_badflags; /* flags indicate !(mbuf | uio) */ -+ u_int32_t st_nodesc; /* op submitted w/o descriptors */ -+ u_int32_t st_badalg; /* unsupported algorithm */ -+ u_int32_t st_ringfull; /* PE descriptor ring full */ -+ u_int32_t st_peoperr; /* PE marked error */ -+ u_int32_t st_dmaerr; /* PE DMA error */ -+ u_int32_t st_bypasstoobig; /* bypass > 96 bytes */ -+ u_int32_t st_skipmismatch; /* enc part begins before auth part */ -+ u_int32_t st_lenmismatch; /* enc length different auth length */ -+ u_int32_t st_coffmisaligned; /* crypto offset not 32-bit aligned */ -+ u_int32_t st_cofftoobig; /* crypto offset > 255 words */ -+ u_int32_t st_iovmisaligned; /* iov op not aligned */ -+ u_int32_t st_iovnotuniform; /* iov op not suitable */ -+ u_int32_t st_unaligned; /* unaligned src caused copy */ -+ u_int32_t st_notuniform; /* non-uniform src caused copy */ -+ u_int32_t st_nomap; /* bus_dmamap_create failed */ -+ u_int32_t st_noload; /* bus_dmamap_load_* failed */ -+ u_int32_t st_nombuf; /* MGET* failed */ -+ u_int32_t st_nomcl; /* MCLGET* failed */ -+ u_int32_t st_maxqchip; /* max mcr1 ops out for processing */ -+ u_int32_t st_rng; /* RNG requests */ -+ u_int32_t st_rngalarm; /* RNG alarm requests */ -+ u_int32_t st_noicvcopy; /* ICV data copies suppressed */ -+}; -+#endif /* _SAFE_SAFEVAR_H_ */ -diff -Nur linux-2.6.36.orig/crypto/ocf/safe/sha1.c linux-2.6.36/crypto/ocf/safe/sha1.c ---- linux-2.6.36.orig/crypto/ocf/safe/sha1.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/safe/sha1.c 2010-11-09 20:28:13.072495484 +0100 -@@ -0,0 +1,279 @@ -+/* $KAME: sha1.c,v 1.5 2000/11/08 06:13:08 itojun Exp $ */ -+/* -+ * Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. Neither the name of the project nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ */ -+ -+/* -+ * FIPS pub 180-1: Secure Hash Algorithm (SHA-1) -+ * based on: http://csrc.nist.gov/fips/fip180-1.txt -+ * implemented by Jun-ichiro itojun Itoh -+ */ -+ -+#if 0 -+#include -+__FBSDID("$FreeBSD: src/sys/crypto/sha1.c,v 1.9 2003/06/10 21:36:57 obrien Exp $"); -+ -+#include -+#include -+#include -+#include -+ -+#include -+#endif -+ -+/* sanity check */ -+#if BYTE_ORDER != BIG_ENDIAN -+# if BYTE_ORDER != LITTLE_ENDIAN -+# define unsupported 1 -+# endif -+#endif -+ -+#ifndef unsupported -+ -+/* constant table */ -+static u_int32_t _K[] = { 0x5a827999, 0x6ed9eba1, 0x8f1bbcdc, 0xca62c1d6 }; -+#define K(t) _K[(t) / 20] -+ -+#define F0(b, c, d) (((b) & (c)) | ((~(b)) & (d))) -+#define F1(b, c, d) (((b) ^ (c)) ^ (d)) -+#define F2(b, c, d) (((b) & (c)) | ((b) & (d)) | ((c) & (d))) -+#define F3(b, c, d) (((b) ^ (c)) ^ (d)) -+ -+#define S(n, x) (((x) << (n)) | ((x) >> (32 - n))) -+ -+#undef H -+#define H(n) (ctxt->h.b32[(n)]) -+#define COUNT (ctxt->count) -+#define BCOUNT (ctxt->c.b64[0] / 8) -+#define W(n) (ctxt->m.b32[(n)]) -+ -+#define PUTBYTE(x) { \ -+ ctxt->m.b8[(COUNT % 64)] = (x); \ -+ COUNT++; \ -+ COUNT %= 64; \ -+ ctxt->c.b64[0] += 8; \ -+ if (COUNT % 64 == 0) \ -+ sha1_step(ctxt); \ -+ } -+ -+#define PUTPAD(x) { \ -+ ctxt->m.b8[(COUNT % 64)] = (x); \ -+ COUNT++; \ -+ COUNT %= 64; \ -+ if (COUNT % 64 == 0) \ -+ sha1_step(ctxt); \ -+ } -+ -+static void sha1_step(struct sha1_ctxt *); -+ -+static void -+sha1_step(ctxt) -+ struct sha1_ctxt *ctxt; -+{ -+ u_int32_t a, b, c, d, e; -+ size_t t, s; -+ u_int32_t tmp; -+ -+#if BYTE_ORDER == LITTLE_ENDIAN -+ struct sha1_ctxt tctxt; -+ bcopy(&ctxt->m.b8[0], &tctxt.m.b8[0], 64); -+ ctxt->m.b8[0] = tctxt.m.b8[3]; ctxt->m.b8[1] = tctxt.m.b8[2]; -+ ctxt->m.b8[2] = tctxt.m.b8[1]; ctxt->m.b8[3] = tctxt.m.b8[0]; -+ ctxt->m.b8[4] = tctxt.m.b8[7]; ctxt->m.b8[5] = tctxt.m.b8[6]; -+ ctxt->m.b8[6] = tctxt.m.b8[5]; ctxt->m.b8[7] = tctxt.m.b8[4]; -+ ctxt->m.b8[8] = tctxt.m.b8[11]; ctxt->m.b8[9] = tctxt.m.b8[10]; -+ ctxt->m.b8[10] = tctxt.m.b8[9]; ctxt->m.b8[11] = tctxt.m.b8[8]; -+ ctxt->m.b8[12] = tctxt.m.b8[15]; ctxt->m.b8[13] = tctxt.m.b8[14]; -+ ctxt->m.b8[14] = tctxt.m.b8[13]; ctxt->m.b8[15] = tctxt.m.b8[12]; -+ ctxt->m.b8[16] = tctxt.m.b8[19]; ctxt->m.b8[17] = tctxt.m.b8[18]; -+ ctxt->m.b8[18] = tctxt.m.b8[17]; ctxt->m.b8[19] = tctxt.m.b8[16]; -+ ctxt->m.b8[20] = tctxt.m.b8[23]; ctxt->m.b8[21] = tctxt.m.b8[22]; -+ ctxt->m.b8[22] = tctxt.m.b8[21]; ctxt->m.b8[23] = tctxt.m.b8[20]; -+ ctxt->m.b8[24] = tctxt.m.b8[27]; ctxt->m.b8[25] = tctxt.m.b8[26]; -+ ctxt->m.b8[26] = tctxt.m.b8[25]; ctxt->m.b8[27] = tctxt.m.b8[24]; -+ ctxt->m.b8[28] = tctxt.m.b8[31]; ctxt->m.b8[29] = tctxt.m.b8[30]; -+ ctxt->m.b8[30] = tctxt.m.b8[29]; ctxt->m.b8[31] = tctxt.m.b8[28]; -+ ctxt->m.b8[32] = tctxt.m.b8[35]; ctxt->m.b8[33] = tctxt.m.b8[34]; -+ ctxt->m.b8[34] = tctxt.m.b8[33]; ctxt->m.b8[35] = tctxt.m.b8[32]; -+ ctxt->m.b8[36] = tctxt.m.b8[39]; ctxt->m.b8[37] = tctxt.m.b8[38]; -+ ctxt->m.b8[38] = tctxt.m.b8[37]; ctxt->m.b8[39] = tctxt.m.b8[36]; -+ ctxt->m.b8[40] = tctxt.m.b8[43]; ctxt->m.b8[41] = tctxt.m.b8[42]; -+ ctxt->m.b8[42] = tctxt.m.b8[41]; ctxt->m.b8[43] = tctxt.m.b8[40]; -+ ctxt->m.b8[44] = tctxt.m.b8[47]; ctxt->m.b8[45] = tctxt.m.b8[46]; -+ ctxt->m.b8[46] = tctxt.m.b8[45]; ctxt->m.b8[47] = tctxt.m.b8[44]; -+ ctxt->m.b8[48] = tctxt.m.b8[51]; ctxt->m.b8[49] = tctxt.m.b8[50]; -+ ctxt->m.b8[50] = tctxt.m.b8[49]; ctxt->m.b8[51] = tctxt.m.b8[48]; -+ ctxt->m.b8[52] = tctxt.m.b8[55]; ctxt->m.b8[53] = tctxt.m.b8[54]; -+ ctxt->m.b8[54] = tctxt.m.b8[53]; ctxt->m.b8[55] = tctxt.m.b8[52]; -+ ctxt->m.b8[56] = tctxt.m.b8[59]; ctxt->m.b8[57] = tctxt.m.b8[58]; -+ ctxt->m.b8[58] = tctxt.m.b8[57]; ctxt->m.b8[59] = tctxt.m.b8[56]; -+ ctxt->m.b8[60] = tctxt.m.b8[63]; ctxt->m.b8[61] = tctxt.m.b8[62]; -+ ctxt->m.b8[62] = tctxt.m.b8[61]; ctxt->m.b8[63] = tctxt.m.b8[60]; -+#endif -+ -+ a = H(0); b = H(1); c = H(2); d = H(3); e = H(4); -+ -+ for (t = 0; t < 20; t++) { -+ s = t & 0x0f; -+ if (t >= 16) { -+ W(s) = S(1, W((s+13) & 0x0f) ^ W((s+8) & 0x0f) ^ W((s+2) & 0x0f) ^ W(s)); -+ } -+ tmp = S(5, a) + F0(b, c, d) + e + W(s) + K(t); -+ e = d; d = c; c = S(30, b); b = a; a = tmp; -+ } -+ for (t = 20; t < 40; t++) { -+ s = t & 0x0f; -+ W(s) = S(1, W((s+13) & 0x0f) ^ W((s+8) & 0x0f) ^ W((s+2) & 0x0f) ^ W(s)); -+ tmp = S(5, a) + F1(b, c, d) + e + W(s) + K(t); -+ e = d; d = c; c = S(30, b); b = a; a = tmp; -+ } -+ for (t = 40; t < 60; t++) { -+ s = t & 0x0f; -+ W(s) = S(1, W((s+13) & 0x0f) ^ W((s+8) & 0x0f) ^ W((s+2) & 0x0f) ^ W(s)); -+ tmp = S(5, a) + F2(b, c, d) + e + W(s) + K(t); -+ e = d; d = c; c = S(30, b); b = a; a = tmp; -+ } -+ for (t = 60; t < 80; t++) { -+ s = t & 0x0f; -+ W(s) = S(1, W((s+13) & 0x0f) ^ W((s+8) & 0x0f) ^ W((s+2) & 0x0f) ^ W(s)); -+ tmp = S(5, a) + F3(b, c, d) + e + W(s) + K(t); -+ e = d; d = c; c = S(30, b); b = a; a = tmp; -+ } -+ -+ H(0) = H(0) + a; -+ H(1) = H(1) + b; -+ H(2) = H(2) + c; -+ H(3) = H(3) + d; -+ H(4) = H(4) + e; -+ -+ bzero(&ctxt->m.b8[0], 64); -+} -+ -+/*------------------------------------------------------------*/ -+ -+void -+sha1_init(ctxt) -+ struct sha1_ctxt *ctxt; -+{ -+ bzero(ctxt, sizeof(struct sha1_ctxt)); -+ H(0) = 0x67452301; -+ H(1) = 0xefcdab89; -+ H(2) = 0x98badcfe; -+ H(3) = 0x10325476; -+ H(4) = 0xc3d2e1f0; -+} -+ -+void -+sha1_pad(ctxt) -+ struct sha1_ctxt *ctxt; -+{ -+ size_t padlen; /*pad length in bytes*/ -+ size_t padstart; -+ -+ PUTPAD(0x80); -+ -+ padstart = COUNT % 64; -+ padlen = 64 - padstart; -+ if (padlen < 8) { -+ bzero(&ctxt->m.b8[padstart], padlen); -+ COUNT += padlen; -+ COUNT %= 64; -+ sha1_step(ctxt); -+ padstart = COUNT % 64; /* should be 0 */ -+ padlen = 64 - padstart; /* should be 64 */ -+ } -+ bzero(&ctxt->m.b8[padstart], padlen - 8); -+ COUNT += (padlen - 8); -+ COUNT %= 64; -+#if BYTE_ORDER == BIG_ENDIAN -+ PUTPAD(ctxt->c.b8[0]); PUTPAD(ctxt->c.b8[1]); -+ PUTPAD(ctxt->c.b8[2]); PUTPAD(ctxt->c.b8[3]); -+ PUTPAD(ctxt->c.b8[4]); PUTPAD(ctxt->c.b8[5]); -+ PUTPAD(ctxt->c.b8[6]); PUTPAD(ctxt->c.b8[7]); -+#else -+ PUTPAD(ctxt->c.b8[7]); PUTPAD(ctxt->c.b8[6]); -+ PUTPAD(ctxt->c.b8[5]); PUTPAD(ctxt->c.b8[4]); -+ PUTPAD(ctxt->c.b8[3]); PUTPAD(ctxt->c.b8[2]); -+ PUTPAD(ctxt->c.b8[1]); PUTPAD(ctxt->c.b8[0]); -+#endif -+} -+ -+void -+sha1_loop(ctxt, input, len) -+ struct sha1_ctxt *ctxt; -+ const u_int8_t *input; -+ size_t len; -+{ -+ size_t gaplen; -+ size_t gapstart; -+ size_t off; -+ size_t copysiz; -+ -+ off = 0; -+ -+ while (off < len) { -+ gapstart = COUNT % 64; -+ gaplen = 64 - gapstart; -+ -+ copysiz = (gaplen < len - off) ? gaplen : len - off; -+ bcopy(&input[off], &ctxt->m.b8[gapstart], copysiz); -+ COUNT += copysiz; -+ COUNT %= 64; -+ ctxt->c.b64[0] += copysiz * 8; -+ if (COUNT % 64 == 0) -+ sha1_step(ctxt); -+ off += copysiz; -+ } -+} -+ -+void -+sha1_result(ctxt, digest0) -+ struct sha1_ctxt *ctxt; -+ caddr_t digest0; -+{ -+ u_int8_t *digest; -+ -+ digest = (u_int8_t *)digest0; -+ sha1_pad(ctxt); -+#if BYTE_ORDER == BIG_ENDIAN -+ bcopy(&ctxt->h.b8[0], digest, 20); -+#else -+ digest[0] = ctxt->h.b8[3]; digest[1] = ctxt->h.b8[2]; -+ digest[2] = ctxt->h.b8[1]; digest[3] = ctxt->h.b8[0]; -+ digest[4] = ctxt->h.b8[7]; digest[5] = ctxt->h.b8[6]; -+ digest[6] = ctxt->h.b8[5]; digest[7] = ctxt->h.b8[4]; -+ digest[8] = ctxt->h.b8[11]; digest[9] = ctxt->h.b8[10]; -+ digest[10] = ctxt->h.b8[9]; digest[11] = ctxt->h.b8[8]; -+ digest[12] = ctxt->h.b8[15]; digest[13] = ctxt->h.b8[14]; -+ digest[14] = ctxt->h.b8[13]; digest[15] = ctxt->h.b8[12]; -+ digest[16] = ctxt->h.b8[19]; digest[17] = ctxt->h.b8[18]; -+ digest[18] = ctxt->h.b8[17]; digest[19] = ctxt->h.b8[16]; -+#endif -+} -+ -+#endif /*unsupported*/ -diff -Nur linux-2.6.36.orig/crypto/ocf/safe/sha1.h linux-2.6.36/crypto/ocf/safe/sha1.h ---- linux-2.6.36.orig/crypto/ocf/safe/sha1.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/safe/sha1.h 2010-11-09 20:28:13.112495423 +0100 -@@ -0,0 +1,72 @@ -+/* $FreeBSD: src/sys/crypto/sha1.h,v 1.8 2002/03/20 05:13:50 alfred Exp $ */ -+/* $KAME: sha1.h,v 1.5 2000/03/27 04:36:23 sumikawa Exp $ */ -+ -+/* -+ * Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. Neither the name of the project nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ */ -+/* -+ * FIPS pub 180-1: Secure Hash Algorithm (SHA-1) -+ * based on: http://csrc.nist.gov/fips/fip180-1.txt -+ * implemented by Jun-ichiro itojun Itoh -+ */ -+ -+#ifndef _NETINET6_SHA1_H_ -+#define _NETINET6_SHA1_H_ -+ -+struct sha1_ctxt { -+ union { -+ u_int8_t b8[20]; -+ u_int32_t b32[5]; -+ } h; -+ union { -+ u_int8_t b8[8]; -+ u_int64_t b64[1]; -+ } c; -+ union { -+ u_int8_t b8[64]; -+ u_int32_t b32[16]; -+ } m; -+ u_int8_t count; -+}; -+ -+#ifdef __KERNEL__ -+extern void sha1_init(struct sha1_ctxt *); -+extern void sha1_pad(struct sha1_ctxt *); -+extern void sha1_loop(struct sha1_ctxt *, const u_int8_t *, size_t); -+extern void sha1_result(struct sha1_ctxt *, caddr_t); -+ -+/* compatibilty with other SHA1 source codes */ -+typedef struct sha1_ctxt SHA1_CTX; -+#define SHA1Init(x) sha1_init((x)) -+#define SHA1Update(x, y, z) sha1_loop((x), (y), (z)) -+#define SHA1Final(x, y) sha1_result((y), (x)) -+#endif /* __KERNEL__ */ -+ -+#define SHA1_RESULTLEN (160/8) -+ -+#endif /*_NETINET6_SHA1_H_*/ -diff -Nur linux-2.6.36.orig/crypto/ocf/talitos/Makefile linux-2.6.36/crypto/ocf/talitos/Makefile ---- linux-2.6.36.orig/crypto/ocf/talitos/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/talitos/Makefile 2010-11-09 20:28:13.155214387 +0100 -@@ -0,0 +1,12 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+obj-$(CONFIG_OCF_TALITOS) += talitos.o -+ -+obj ?= . -+EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff -Nur linux-2.6.36.orig/crypto/ocf/talitos/talitos.c linux-2.6.36/crypto/ocf/talitos/talitos.c ---- linux-2.6.36.orig/crypto/ocf/talitos/talitos.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/talitos/talitos.c 2010-11-09 20:28:13.192104548 +0100 -@@ -0,0 +1,1359 @@ -+/* -+ * crypto/ocf/talitos/talitos.c -+ * -+ * An OCF-Linux module that uses Freescale's SEC to do the crypto. -+ * Based on crypto/ocf/hifn and crypto/ocf/safe OCF drivers -+ * -+ * Copyright (c) 2006 Freescale Semiconductor, Inc. -+ * -+ * This code written by Kim A. B. Phillips -+ * some code copied from files with the following: -+ * Copyright (C) 2004-2007 David McCullough -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * --------------------------------------------------------------------------- -+ * -+ * NOTES: -+ * -+ * The Freescale SEC (also known as 'talitos') resides on the -+ * internal bus, and runs asynchronous to the processor core. It has -+ * a wide gamut of cryptographic acceleration features, including single- -+ * pass IPsec (also known as algorithm chaining). To properly utilize -+ * all of the SEC's performance enhancing features, further reworking -+ * of higher level code (framework, applications) will be necessary. -+ * -+ * The following table shows which SEC version is present in which devices: -+ * -+ * Devices SEC version -+ * -+ * 8272, 8248 SEC 1.0 -+ * 885, 875 SEC 1.2 -+ * 8555E, 8541E SEC 2.0 -+ * 8349E SEC 2.01 -+ * 8548E SEC 2.1 -+ * -+ * The following table shows the features offered by each SEC version: -+ * -+ * Max. chan- -+ * version Bus I/F Clock nels DEU AESU AFEU MDEU PKEU RNG KEU -+ * -+ * SEC 1.0 internal 64b 100MHz 4 1 1 1 1 1 1 0 -+ * SEC 1.2 internal 32b 66MHz 1 1 1 0 1 0 0 0 -+ * SEC 2.0 internal 64b 166MHz 4 1 1 1 1 1 1 0 -+ * SEC 2.01 internal 64b 166MHz 4 1 1 1 1 1 1 0 -+ * SEC 2.1 internal 64b 333MHz 4 1 1 1 1 1 1 1 -+ * -+ * Each execution unit in the SEC has two modes of execution; channel and -+ * slave/debug. This driver employs the channel infrastructure in the -+ * device for convenience. Only the RNG is directly accessed due to the -+ * convenience of its random fifo pool. The relationship between the -+ * channels and execution units is depicted in the following diagram: -+ * -+ * ------- ------------ -+ * ---| ch0 |---| | -+ * ------- | | -+ * | |------+-------+-------+-------+------------ -+ * ------- | | | | | | | -+ * ---| ch1 |---| | | | | | | -+ * ------- | | ------ ------ ------ ------ ------ -+ * |controller| |DEU | |AESU| |MDEU| |PKEU| ... |RNG | -+ * ------- | | ------ ------ ------ ------ ------ -+ * ---| ch2 |---| | | | | | | -+ * ------- | | | | | | | -+ * | |------+-------+-------+-------+------------ -+ * ------- | | -+ * ---| ch3 |---| | -+ * ------- ------------ -+ * -+ * Channel ch0 may drive an aes operation to the aes unit (AESU), -+ * and, at the same time, ch1 may drive a message digest operation -+ * to the mdeu. Each channel has an input descriptor FIFO, and the -+ * FIFO can contain, e.g. on the 8541E, up to 24 entries, before a -+ * a buffer overrun error is triggered. The controller is responsible -+ * for fetching the data from descriptor pointers, and passing the -+ * data to the appropriate EUs. The controller also writes the -+ * cryptographic operation's result to memory. The SEC notifies -+ * completion by triggering an interrupt and/or setting the 1st byte -+ * of the hdr field to 0xff. -+ * -+ * TODO: -+ * o support more algorithms -+ * o support more versions of the SEC -+ * o add support for linux 2.4 -+ * o scatter-gather (sg) support -+ * o add support for public key ops (PKEU) -+ * o add statistics -+ */ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include /* dma_map_single() */ -+#include -+ -+#include -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,15) -+#include -+#endif -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) -+#include -+#endif -+ -+#include -+#include -+ -+#define DRV_NAME "talitos" -+ -+#include "talitos_dev.h" -+#include "talitos_soft.h" -+ -+#define read_random(p,l) get_random_bytes(p,l) -+ -+const char talitos_driver_name[] = "Talitos OCF"; -+const char talitos_driver_version[] = "0.2"; -+ -+static int talitos_newsession(device_t dev, u_int32_t *sidp, -+ struct cryptoini *cri); -+static int talitos_freesession(device_t dev, u_int64_t tid); -+static int talitos_process(device_t dev, struct cryptop *crp, int hint); -+static void dump_talitos_status(struct talitos_softc *sc); -+static int talitos_submit(struct talitos_softc *sc, struct talitos_desc *td, -+ int chsel); -+static void talitos_doneprocessing(struct talitos_softc *sc); -+static void talitos_init_device(struct talitos_softc *sc); -+static void talitos_reset_device_master(struct talitos_softc *sc); -+static void talitos_reset_device(struct talitos_softc *sc); -+static void talitos_errorprocessing(struct talitos_softc *sc); -+#ifdef CONFIG_PPC_MERGE -+static int talitos_probe(struct of_device *ofdev, const struct of_device_id *match); -+static int talitos_remove(struct of_device *ofdev); -+#else -+static int talitos_probe(struct platform_device *pdev); -+static int talitos_remove(struct platform_device *pdev); -+#endif -+#ifdef CONFIG_OCF_RANDOMHARVEST -+static int talitos_read_random(void *arg, u_int32_t *buf, int maxwords); -+static void talitos_rng_init(struct talitos_softc *sc); -+#endif -+ -+static device_method_t talitos_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, talitos_newsession), -+ DEVMETHOD(cryptodev_freesession,talitos_freesession), -+ DEVMETHOD(cryptodev_process, talitos_process), -+}; -+ -+#define debug talitos_debug -+int talitos_debug = 0; -+module_param(talitos_debug, int, 0644); -+MODULE_PARM_DESC(talitos_debug, "Enable debug"); -+ -+static inline void talitos_write(volatile unsigned *addr, u32 val) -+{ -+ out_be32(addr, val); -+} -+ -+static inline u32 talitos_read(volatile unsigned *addr) -+{ -+ u32 val; -+ val = in_be32(addr); -+ return val; -+} -+ -+static void dump_talitos_status(struct talitos_softc *sc) -+{ -+ unsigned int v, v_hi, i, *ptr; -+ v = talitos_read(sc->sc_base_addr + TALITOS_MCR); -+ v_hi = talitos_read(sc->sc_base_addr + TALITOS_MCR_HI); -+ printk(KERN_INFO "%s: MCR 0x%08x_%08x\n", -+ device_get_nameunit(sc->sc_cdev), v, v_hi); -+ v = talitos_read(sc->sc_base_addr + TALITOS_IMR); -+ v_hi = talitos_read(sc->sc_base_addr + TALITOS_IMR_HI); -+ printk(KERN_INFO "%s: IMR 0x%08x_%08x\n", -+ device_get_nameunit(sc->sc_cdev), v, v_hi); -+ v = talitos_read(sc->sc_base_addr + TALITOS_ISR); -+ v_hi = talitos_read(sc->sc_base_addr + TALITOS_ISR_HI); -+ printk(KERN_INFO "%s: ISR 0x%08x_%08x\n", -+ device_get_nameunit(sc->sc_cdev), v, v_hi); -+ for (i = 0; i < sc->sc_num_channels; i++) { -+ v = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + -+ TALITOS_CH_CDPR); -+ v_hi = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + -+ TALITOS_CH_CDPR_HI); -+ printk(KERN_INFO "%s: CDPR ch%d 0x%08x_%08x\n", -+ device_get_nameunit(sc->sc_cdev), i, v, v_hi); -+ } -+ for (i = 0; i < sc->sc_num_channels; i++) { -+ v = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + -+ TALITOS_CH_CCPSR); -+ v_hi = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + -+ TALITOS_CH_CCPSR_HI); -+ printk(KERN_INFO "%s: CCPSR ch%d 0x%08x_%08x\n", -+ device_get_nameunit(sc->sc_cdev), i, v, v_hi); -+ } -+ ptr = sc->sc_base_addr + TALITOS_CH_DESCBUF; -+ for (i = 0; i < 16; i++) { -+ v = talitos_read(ptr++); v_hi = talitos_read(ptr++); -+ printk(KERN_INFO "%s: DESCBUF ch0 0x%08x_%08x (tdp%02d)\n", -+ device_get_nameunit(sc->sc_cdev), v, v_hi, i); -+ } -+ return; -+} -+ -+ -+#ifdef CONFIG_OCF_RANDOMHARVEST -+/* -+ * pull random numbers off the RNG FIFO, not exceeding amount available -+ */ -+static int -+talitos_read_random(void *arg, u_int32_t *buf, int maxwords) -+{ -+ struct talitos_softc *sc = (struct talitos_softc *) arg; -+ int rc; -+ u_int32_t v; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ /* check for things like FIFO underflow */ -+ v = talitos_read(sc->sc_base_addr + TALITOS_RNGISR_HI); -+ if (unlikely(v)) { -+ printk(KERN_ERR "%s: RNGISR_HI error %08x\n", -+ device_get_nameunit(sc->sc_cdev), v); -+ return 0; -+ } -+ /* -+ * OFL is number of available 64-bit words, -+ * shift and convert to a 32-bit word count -+ */ -+ v = talitos_read(sc->sc_base_addr + TALITOS_RNGSR_HI); -+ v = (v & TALITOS_RNGSR_HI_OFL) >> (16 - 1); -+ if (maxwords > v) -+ maxwords = v; -+ for (rc = 0; rc < maxwords; rc++) { -+ buf[rc] = talitos_read(sc->sc_base_addr + -+ TALITOS_RNG_FIFO + rc*sizeof(u_int32_t)); -+ } -+ if (maxwords & 1) { -+ /* -+ * RNG will complain with an AE in the RNGISR -+ * if we don't complete the pairs of 32-bit reads -+ * to its 64-bit register based FIFO -+ */ -+ v = talitos_read(sc->sc_base_addr + -+ TALITOS_RNG_FIFO + rc*sizeof(u_int32_t)); -+ } -+ -+ return rc; -+} -+ -+static void -+talitos_rng_init(struct talitos_softc *sc) -+{ -+ u_int32_t v; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ /* reset RNG EU */ -+ v = talitos_read(sc->sc_base_addr + TALITOS_RNGRCR_HI); -+ v |= TALITOS_RNGRCR_HI_SR; -+ talitos_write(sc->sc_base_addr + TALITOS_RNGRCR_HI, v); -+ while ((talitos_read(sc->sc_base_addr + TALITOS_RNGSR_HI) -+ & TALITOS_RNGSR_HI_RD) == 0) -+ cpu_relax(); -+ /* -+ * we tell the RNG to start filling the RNG FIFO -+ * by writing the RNGDSR -+ */ -+ v = talitos_read(sc->sc_base_addr + TALITOS_RNGDSR_HI); -+ talitos_write(sc->sc_base_addr + TALITOS_RNGDSR_HI, v); -+ /* -+ * 64 bits of data will be pushed onto the FIFO every -+ * 256 SEC cycles until the FIFO is full. The RNG then -+ * attempts to keep the FIFO full. -+ */ -+ v = talitos_read(sc->sc_base_addr + TALITOS_RNGISR_HI); -+ if (v) { -+ printk(KERN_ERR "%s: RNGISR_HI error %08x\n", -+ device_get_nameunit(sc->sc_cdev), v); -+ return; -+ } -+ /* -+ * n.b. we need to add a FIPS test here - if the RNG is going -+ * to fail, it's going to fail at reset time -+ */ -+ return; -+} -+#endif /* CONFIG_OCF_RANDOMHARVEST */ -+ -+/* -+ * Generate a new software session. -+ */ -+static int -+talitos_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) -+{ -+ struct cryptoini *c, *encini = NULL, *macini = NULL; -+ struct talitos_softc *sc = device_get_softc(dev); -+ struct talitos_session *ses = NULL; -+ int sesn; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ if (sidp == NULL || cri == NULL || sc == NULL) { -+ DPRINTF("%s,%d - EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ for (c = cri; c != NULL; c = c->cri_next) { -+ if (c->cri_alg == CRYPTO_MD5 || -+ c->cri_alg == CRYPTO_MD5_HMAC || -+ c->cri_alg == CRYPTO_SHA1 || -+ c->cri_alg == CRYPTO_SHA1_HMAC || -+ c->cri_alg == CRYPTO_NULL_HMAC) { -+ if (macini) -+ return EINVAL; -+ macini = c; -+ } else if (c->cri_alg == CRYPTO_DES_CBC || -+ c->cri_alg == CRYPTO_3DES_CBC || -+ c->cri_alg == CRYPTO_AES_CBC || -+ c->cri_alg == CRYPTO_NULL_CBC) { -+ if (encini) -+ return EINVAL; -+ encini = c; -+ } else { -+ DPRINTF("UNKNOWN c->cri_alg %d\n", encini->cri_alg); -+ return EINVAL; -+ } -+ } -+ if (encini == NULL && macini == NULL) -+ return EINVAL; -+ if (encini) { -+ /* validate key length */ -+ switch (encini->cri_alg) { -+ case CRYPTO_DES_CBC: -+ if (encini->cri_klen != 64) -+ return EINVAL; -+ break; -+ case CRYPTO_3DES_CBC: -+ if (encini->cri_klen != 192) { -+ return EINVAL; -+ } -+ break; -+ case CRYPTO_AES_CBC: -+ if (encini->cri_klen != 128 && -+ encini->cri_klen != 192 && -+ encini->cri_klen != 256) -+ return EINVAL; -+ break; -+ default: -+ DPRINTF("UNKNOWN encini->cri_alg %d\n", -+ encini->cri_alg); -+ return EINVAL; -+ } -+ } -+ -+ if (sc->sc_sessions == NULL) { -+ ses = sc->sc_sessions = (struct talitos_session *) -+ kmalloc(sizeof(struct talitos_session), SLAB_ATOMIC); -+ if (ses == NULL) -+ return ENOMEM; -+ memset(ses, 0, sizeof(struct talitos_session)); -+ sesn = 0; -+ sc->sc_nsessions = 1; -+ } else { -+ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { -+ if (sc->sc_sessions[sesn].ses_used == 0) { -+ ses = &sc->sc_sessions[sesn]; -+ break; -+ } -+ } -+ -+ if (ses == NULL) { -+ /* allocating session */ -+ sesn = sc->sc_nsessions; -+ ses = (struct talitos_session *) kmalloc( -+ (sesn + 1) * sizeof(struct talitos_session), -+ SLAB_ATOMIC); -+ if (ses == NULL) -+ return ENOMEM; -+ memset(ses, 0, -+ (sesn + 1) * sizeof(struct talitos_session)); -+ memcpy(ses, sc->sc_sessions, -+ sesn * sizeof(struct talitos_session)); -+ memset(sc->sc_sessions, 0, -+ sesn * sizeof(struct talitos_session)); -+ kfree(sc->sc_sessions); -+ sc->sc_sessions = ses; -+ ses = &sc->sc_sessions[sesn]; -+ sc->sc_nsessions++; -+ } -+ } -+ -+ ses->ses_used = 1; -+ -+ if (encini) { -+ /* get an IV */ -+ /* XXX may read fewer than requested */ -+ read_random(ses->ses_iv, sizeof(ses->ses_iv)); -+ -+ ses->ses_klen = (encini->cri_klen + 7) / 8; -+ memcpy(ses->ses_key, encini->cri_key, ses->ses_klen); -+ if (macini) { -+ /* doing hash on top of cipher */ -+ ses->ses_hmac_len = (macini->cri_klen + 7) / 8; -+ memcpy(ses->ses_hmac, macini->cri_key, -+ ses->ses_hmac_len); -+ } -+ } else if (macini) { -+ /* doing hash */ -+ ses->ses_klen = (macini->cri_klen + 7) / 8; -+ memcpy(ses->ses_key, macini->cri_key, ses->ses_klen); -+ } -+ -+ /* back compat way of determining MSC result len */ -+ if (macini) { -+ ses->ses_mlen = macini->cri_mlen; -+ if (ses->ses_mlen == 0) { -+ if (macini->cri_alg == CRYPTO_MD5_HMAC) -+ ses->ses_mlen = MD5_HASH_LEN; -+ else -+ ses->ses_mlen = SHA1_HASH_LEN; -+ } -+ } -+ -+ /* really should make up a template td here, -+ * and only fill things like i/o and direction in process() */ -+ -+ /* assign session ID */ -+ *sidp = TALITOS_SID(sc->sc_num, sesn); -+ return 0; -+} -+ -+/* -+ * Deallocate a session. -+ */ -+static int -+talitos_freesession(device_t dev, u_int64_t tid) -+{ -+ struct talitos_softc *sc = device_get_softc(dev); -+ int session, ret; -+ u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; -+ -+ if (sc == NULL) -+ return EINVAL; -+ session = TALITOS_SESSION(sid); -+ if (session < sc->sc_nsessions) { -+ memset(&sc->sc_sessions[session], 0, -+ sizeof(sc->sc_sessions[session])); -+ ret = 0; -+ } else -+ ret = EINVAL; -+ return ret; -+} -+ -+/* -+ * launch device processing - it will come back with done notification -+ * in the form of an interrupt and/or HDR_DONE_BITS in header -+ */ -+static int -+talitos_submit( -+ struct talitos_softc *sc, -+ struct talitos_desc *td, -+ int chsel) -+{ -+ u_int32_t v; -+ -+ v = dma_map_single(NULL, td, sizeof(*td), DMA_TO_DEVICE); -+ talitos_write(sc->sc_base_addr + -+ chsel*TALITOS_CH_OFFSET + TALITOS_CH_FF, 0); -+ talitos_write(sc->sc_base_addr + -+ chsel*TALITOS_CH_OFFSET + TALITOS_CH_FF_HI, v); -+ return 0; -+} -+ -+static int -+talitos_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ int i, err = 0, ivsize; -+ struct talitos_softc *sc = device_get_softc(dev); -+ struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; -+ caddr_t iv; -+ struct talitos_session *ses; -+ struct talitos_desc *td; -+ unsigned long flags; -+ /* descriptor mappings */ -+ int hmac_key, hmac_data, cipher_iv, cipher_key, -+ in_fifo, out_fifo, cipher_iv_out; -+ static int chsel = -1; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { -+ return EINVAL; -+ } -+ crp->crp_etype = 0; -+ if (TALITOS_SESSION(crp->crp_sid) >= sc->sc_nsessions) { -+ return EINVAL; -+ } -+ -+ ses = &sc->sc_sessions[TALITOS_SESSION(crp->crp_sid)]; -+ -+ /* enter the channel scheduler */ -+ spin_lock_irqsave(&sc->sc_chnfifolock[sc->sc_num_channels], flags); -+ -+ /* reuse channel that already had/has requests for the required EU */ -+ for (i = 0; i < sc->sc_num_channels; i++) { -+ if (sc->sc_chnlastalg[i] == crp->crp_desc->crd_alg) -+ break; -+ } -+ if (i == sc->sc_num_channels) { -+ /* -+ * haven't seen this algo the last sc_num_channels or more -+ * use round robin in this case -+ * nb: sc->sc_num_channels must be power of 2 -+ */ -+ chsel = (chsel + 1) & (sc->sc_num_channels - 1); -+ } else { -+ /* -+ * matches channel with same target execution unit; -+ * use same channel in this case -+ */ -+ chsel = i; -+ } -+ sc->sc_chnlastalg[chsel] = crp->crp_desc->crd_alg; -+ -+ /* release the channel scheduler lock */ -+ spin_unlock_irqrestore(&sc->sc_chnfifolock[sc->sc_num_channels], flags); -+ -+ /* acquire the selected channel fifo lock */ -+ spin_lock_irqsave(&sc->sc_chnfifolock[chsel], flags); -+ -+ /* find and reserve next available descriptor-cryptop pair */ -+ for (i = 0; i < sc->sc_chfifo_len; i++) { -+ if (sc->sc_chnfifo[chsel][i].cf_desc.hdr == 0) { -+ /* -+ * ensure correct descriptor formation by -+ * avoiding inadvertently setting "optional" entries -+ * e.g. not using "optional" dptr2 for MD/HMAC descs -+ */ -+ memset(&sc->sc_chnfifo[chsel][i].cf_desc, -+ 0, sizeof(*td)); -+ /* reserve it with done notification request bit */ -+ sc->sc_chnfifo[chsel][i].cf_desc.hdr |= -+ TALITOS_DONE_NOTIFY; -+ break; -+ } -+ } -+ spin_unlock_irqrestore(&sc->sc_chnfifolock[chsel], flags); -+ -+ if (i == sc->sc_chfifo_len) { -+ /* fifo full */ -+ err = ERESTART; -+ goto errout; -+ } -+ -+ td = &sc->sc_chnfifo[chsel][i].cf_desc; -+ sc->sc_chnfifo[chsel][i].cf_crp = crp; -+ -+ crd1 = crp->crp_desc; -+ if (crd1 == NULL) { -+ err = EINVAL; -+ goto errout; -+ } -+ crd2 = crd1->crd_next; -+ /* prevent compiler warning */ -+ hmac_key = 0; -+ hmac_data = 0; -+ if (crd2 == NULL) { -+ td->hdr |= TD_TYPE_COMMON_NONSNOOP_NO_AFEU; -+ /* assign descriptor dword ptr mappings for this desc. type */ -+ cipher_iv = 1; -+ cipher_key = 2; -+ in_fifo = 3; -+ cipher_iv_out = 5; -+ if (crd1->crd_alg == CRYPTO_MD5_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1 || -+ crd1->crd_alg == CRYPTO_MD5) { -+ out_fifo = 5; -+ maccrd = crd1; -+ enccrd = NULL; -+ } else if (crd1->crd_alg == CRYPTO_DES_CBC || -+ crd1->crd_alg == CRYPTO_3DES_CBC || -+ crd1->crd_alg == CRYPTO_AES_CBC || -+ crd1->crd_alg == CRYPTO_ARC4) { -+ out_fifo = 4; -+ maccrd = NULL; -+ enccrd = crd1; -+ } else { -+ DPRINTF("UNKNOWN crd1->crd_alg %d\n", crd1->crd_alg); -+ err = EINVAL; -+ goto errout; -+ } -+ } else { -+ if (sc->sc_desc_types & TALITOS_HAS_DT_IPSEC_ESP) { -+ td->hdr |= TD_TYPE_IPSEC_ESP; -+ } else { -+ DPRINTF("unimplemented: multiple descriptor ipsec\n"); -+ err = EINVAL; -+ goto errout; -+ } -+ /* assign descriptor dword ptr mappings for this desc. type */ -+ hmac_key = 0; -+ hmac_data = 1; -+ cipher_iv = 2; -+ cipher_key = 3; -+ in_fifo = 4; -+ out_fifo = 5; -+ cipher_iv_out = 6; -+ if ((crd1->crd_alg == CRYPTO_MD5_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1_HMAC || -+ crd1->crd_alg == CRYPTO_MD5 || -+ crd1->crd_alg == CRYPTO_SHA1) && -+ (crd2->crd_alg == CRYPTO_DES_CBC || -+ crd2->crd_alg == CRYPTO_3DES_CBC || -+ crd2->crd_alg == CRYPTO_AES_CBC || -+ crd2->crd_alg == CRYPTO_ARC4) && -+ ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { -+ maccrd = crd1; -+ enccrd = crd2; -+ } else if ((crd1->crd_alg == CRYPTO_DES_CBC || -+ crd1->crd_alg == CRYPTO_ARC4 || -+ crd1->crd_alg == CRYPTO_3DES_CBC || -+ crd1->crd_alg == CRYPTO_AES_CBC) && -+ (crd2->crd_alg == CRYPTO_MD5_HMAC || -+ crd2->crd_alg == CRYPTO_SHA1_HMAC || -+ crd2->crd_alg == CRYPTO_MD5 || -+ crd2->crd_alg == CRYPTO_SHA1) && -+ (crd1->crd_flags & CRD_F_ENCRYPT)) { -+ enccrd = crd1; -+ maccrd = crd2; -+ } else { -+ /* We cannot order the SEC as requested */ -+ printk("%s: cannot do the order\n", -+ device_get_nameunit(sc->sc_cdev)); -+ err = EINVAL; -+ goto errout; -+ } -+ } -+ /* assign in_fifo and out_fifo based on input/output struct type */ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ /* using SKB buffers */ -+ struct sk_buff *skb = (struct sk_buff *)crp->crp_buf; -+ if (skb_shinfo(skb)->nr_frags) { -+ printk("%s: skb frags unimplemented\n", -+ device_get_nameunit(sc->sc_cdev)); -+ err = EINVAL; -+ goto errout; -+ } -+ td->ptr[in_fifo].ptr = dma_map_single(NULL, skb->data, -+ skb->len, DMA_TO_DEVICE); -+ td->ptr[in_fifo].len = skb->len; -+ td->ptr[out_fifo].ptr = dma_map_single(NULL, skb->data, -+ skb->len, DMA_TO_DEVICE); -+ td->ptr[out_fifo].len = skb->len; -+ td->ptr[hmac_data].ptr = dma_map_single(NULL, skb->data, -+ skb->len, DMA_TO_DEVICE); -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ /* using IOV buffers */ -+ struct uio *uiop = (struct uio *)crp->crp_buf; -+ if (uiop->uio_iovcnt > 1) { -+ printk("%s: iov frags unimplemented\n", -+ device_get_nameunit(sc->sc_cdev)); -+ err = EINVAL; -+ goto errout; -+ } -+ td->ptr[in_fifo].ptr = dma_map_single(NULL, -+ uiop->uio_iov->iov_base, crp->crp_ilen, DMA_TO_DEVICE); -+ td->ptr[in_fifo].len = crp->crp_ilen; -+ /* crp_olen is never set; always use crp_ilen */ -+ td->ptr[out_fifo].ptr = dma_map_single(NULL, -+ uiop->uio_iov->iov_base, -+ crp->crp_ilen, DMA_TO_DEVICE); -+ td->ptr[out_fifo].len = crp->crp_ilen; -+ } else { -+ /* using contig buffers */ -+ td->ptr[in_fifo].ptr = dma_map_single(NULL, -+ crp->crp_buf, crp->crp_ilen, DMA_TO_DEVICE); -+ td->ptr[in_fifo].len = crp->crp_ilen; -+ td->ptr[out_fifo].ptr = dma_map_single(NULL, -+ crp->crp_buf, crp->crp_ilen, DMA_TO_DEVICE); -+ td->ptr[out_fifo].len = crp->crp_ilen; -+ } -+ if (enccrd) { -+ switch (enccrd->crd_alg) { -+ case CRYPTO_3DES_CBC: -+ td->hdr |= TALITOS_MODE0_DEU_3DES; -+ /* FALLTHROUGH */ -+ case CRYPTO_DES_CBC: -+ td->hdr |= TALITOS_SEL0_DEU -+ | TALITOS_MODE0_DEU_CBC; -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) -+ td->hdr |= TALITOS_MODE0_DEU_ENC; -+ ivsize = 2*sizeof(u_int32_t); -+ DPRINTF("%cDES ses %d ch %d len %d\n", -+ (td->hdr & TALITOS_MODE0_DEU_3DES)?'3':'1', -+ (u32)TALITOS_SESSION(crp->crp_sid), -+ chsel, td->ptr[in_fifo].len); -+ break; -+ case CRYPTO_AES_CBC: -+ td->hdr |= TALITOS_SEL0_AESU -+ | TALITOS_MODE0_AESU_CBC; -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) -+ td->hdr |= TALITOS_MODE0_AESU_ENC; -+ ivsize = 4*sizeof(u_int32_t); -+ DPRINTF("AES ses %d ch %d len %d\n", -+ (u32)TALITOS_SESSION(crp->crp_sid), -+ chsel, td->ptr[in_fifo].len); -+ break; -+ default: -+ printk("%s: unimplemented enccrd->crd_alg %d\n", -+ device_get_nameunit(sc->sc_cdev), enccrd->crd_alg); -+ err = EINVAL; -+ goto errout; -+ } -+ /* -+ * Setup encrypt/decrypt state. When using basic ops -+ * we can't use an inline IV because hash/crypt offset -+ * must be from the end of the IV to the start of the -+ * crypt data and this leaves out the preceding header -+ * from the hash calculation. Instead we place the IV -+ * in the state record and set the hash/crypt offset to -+ * copy both the header+IV. -+ */ -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) { -+ td->hdr |= TALITOS_DIR_OUTBOUND; -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) -+ iv = enccrd->crd_iv; -+ else -+ iv = (caddr_t) ses->ses_iv; -+ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ enccrd->crd_inject, ivsize, iv); -+ } -+ } else { -+ td->hdr |= TALITOS_DIR_INBOUND; -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) { -+ iv = enccrd->crd_iv; -+ bcopy(enccrd->crd_iv, iv, ivsize); -+ } else { -+ iv = (caddr_t) ses->ses_iv; -+ crypto_copydata(crp->crp_flags, crp->crp_buf, -+ enccrd->crd_inject, ivsize, iv); -+ } -+ } -+ td->ptr[cipher_iv].ptr = dma_map_single(NULL, iv, ivsize, -+ DMA_TO_DEVICE); -+ td->ptr[cipher_iv].len = ivsize; -+ /* -+ * we don't need the cipher iv out length/pointer -+ * field to do ESP IPsec. Therefore we set the len field as 0, -+ * which tells the SEC not to do anything with this len/ptr -+ * field. Previously, when length/pointer as pointing to iv, -+ * it gave us corruption of packets. -+ */ -+ td->ptr[cipher_iv_out].len = 0; -+ } -+ if (enccrd && maccrd) { -+ /* this is ipsec only for now */ -+ td->hdr |= TALITOS_SEL1_MDEU -+ | TALITOS_MODE1_MDEU_INIT -+ | TALITOS_MODE1_MDEU_PAD; -+ switch (maccrd->crd_alg) { -+ case CRYPTO_MD5: -+ td->hdr |= TALITOS_MODE1_MDEU_MD5; -+ break; -+ case CRYPTO_MD5_HMAC: -+ td->hdr |= TALITOS_MODE1_MDEU_MD5_HMAC; -+ break; -+ case CRYPTO_SHA1: -+ td->hdr |= TALITOS_MODE1_MDEU_SHA1; -+ break; -+ case CRYPTO_SHA1_HMAC: -+ td->hdr |= TALITOS_MODE1_MDEU_SHA1_HMAC; -+ break; -+ default: -+ /* We cannot order the SEC as requested */ -+ printk("%s: cannot do the order\n", -+ device_get_nameunit(sc->sc_cdev)); -+ err = EINVAL; -+ goto errout; -+ } -+ if ((maccrd->crd_alg == CRYPTO_MD5_HMAC) || -+ (maccrd->crd_alg == CRYPTO_SHA1_HMAC)) { -+ /* -+ * The offset from hash data to the start of -+ * crypt data is the difference in the skips. -+ */ -+ /* ipsec only for now */ -+ td->ptr[hmac_key].ptr = dma_map_single(NULL, -+ ses->ses_hmac, ses->ses_hmac_len, DMA_TO_DEVICE); -+ td->ptr[hmac_key].len = ses->ses_hmac_len; -+ td->ptr[in_fifo].ptr += enccrd->crd_skip; -+ td->ptr[in_fifo].len = enccrd->crd_len; -+ td->ptr[out_fifo].ptr += enccrd->crd_skip; -+ td->ptr[out_fifo].len = enccrd->crd_len; -+ /* bytes of HMAC to postpend to ciphertext */ -+ td->ptr[out_fifo].extent = ses->ses_mlen; -+ td->ptr[hmac_data].ptr += maccrd->crd_skip; -+ td->ptr[hmac_data].len = enccrd->crd_skip - maccrd->crd_skip; -+ } -+ if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) { -+ printk("%s: CRD_F_KEY_EXPLICIT unimplemented\n", -+ device_get_nameunit(sc->sc_cdev)); -+ } -+ } -+ if (!enccrd && maccrd) { -+ /* single MD5 or SHA */ -+ td->hdr |= TALITOS_SEL0_MDEU -+ | TALITOS_MODE0_MDEU_INIT -+ | TALITOS_MODE0_MDEU_PAD; -+ switch (maccrd->crd_alg) { -+ case CRYPTO_MD5: -+ td->hdr |= TALITOS_MODE0_MDEU_MD5; -+ DPRINTF("MD5 ses %d ch %d len %d\n", -+ (u32)TALITOS_SESSION(crp->crp_sid), -+ chsel, td->ptr[in_fifo].len); -+ break; -+ case CRYPTO_MD5_HMAC: -+ td->hdr |= TALITOS_MODE0_MDEU_MD5_HMAC; -+ break; -+ case CRYPTO_SHA1: -+ td->hdr |= TALITOS_MODE0_MDEU_SHA1; -+ DPRINTF("SHA1 ses %d ch %d len %d\n", -+ (u32)TALITOS_SESSION(crp->crp_sid), -+ chsel, td->ptr[in_fifo].len); -+ break; -+ case CRYPTO_SHA1_HMAC: -+ td->hdr |= TALITOS_MODE0_MDEU_SHA1_HMAC; -+ break; -+ default: -+ /* We cannot order the SEC as requested */ -+ DPRINTF("cannot do the order\n"); -+ err = EINVAL; -+ goto errout; -+ } -+ -+ if (crp->crp_flags & CRYPTO_F_IOV) -+ td->ptr[out_fifo].ptr += maccrd->crd_inject; -+ -+ if ((maccrd->crd_alg == CRYPTO_MD5_HMAC) || -+ (maccrd->crd_alg == CRYPTO_SHA1_HMAC)) { -+ td->ptr[hmac_key].ptr = dma_map_single(NULL, -+ ses->ses_hmac, ses->ses_hmac_len, -+ DMA_TO_DEVICE); -+ td->ptr[hmac_key].len = ses->ses_hmac_len; -+ } -+ } -+ else { -+ /* using process key (session data has duplicate) */ -+ td->ptr[cipher_key].ptr = dma_map_single(NULL, -+ enccrd->crd_key, (enccrd->crd_klen + 7) / 8, -+ DMA_TO_DEVICE); -+ td->ptr[cipher_key].len = (enccrd->crd_klen + 7) / 8; -+ } -+ /* descriptor complete - GO! */ -+ return talitos_submit(sc, td, chsel); -+ -+errout: -+ if (err != ERESTART) { -+ crp->crp_etype = err; -+ crypto_done(crp); -+ } -+ return err; -+} -+ -+/* go through all channels descriptors, notifying OCF what has -+ * _and_hasn't_ successfully completed and reset the device -+ * (otherwise it's up to decoding desc hdrs!) -+ */ -+static void talitos_errorprocessing(struct talitos_softc *sc) -+{ -+ unsigned long flags; -+ int i, j; -+ -+ /* disable further scheduling until under control */ -+ spin_lock_irqsave(&sc->sc_chnfifolock[sc->sc_num_channels], flags); -+ -+ if (debug) dump_talitos_status(sc); -+ /* go through descriptors, try and salvage those successfully done, -+ * and EIO those that weren't -+ */ -+ for (i = 0; i < sc->sc_num_channels; i++) { -+ spin_lock_irqsave(&sc->sc_chnfifolock[i], flags); -+ for (j = 0; j < sc->sc_chfifo_len; j++) { -+ if (sc->sc_chnfifo[i][j].cf_desc.hdr) { -+ if ((sc->sc_chnfifo[i][j].cf_desc.hdr -+ & TALITOS_HDR_DONE_BITS) -+ != TALITOS_HDR_DONE_BITS) { -+ /* this one didn't finish */ -+ /* signify in crp->etype */ -+ sc->sc_chnfifo[i][j].cf_crp->crp_etype -+ = EIO; -+ } -+ } else -+ continue; /* free entry */ -+ /* either way, notify ocf */ -+ crypto_done(sc->sc_chnfifo[i][j].cf_crp); -+ /* and tag it available again -+ * -+ * memset to ensure correct descriptor formation by -+ * avoiding inadvertently setting "optional" entries -+ * e.g. not using "optional" dptr2 MD/HMAC processing -+ */ -+ memset(&sc->sc_chnfifo[i][j].cf_desc, -+ 0, sizeof(struct talitos_desc)); -+ } -+ spin_unlock_irqrestore(&sc->sc_chnfifolock[i], flags); -+ } -+ /* reset and initialize the SEC h/w device */ -+ talitos_reset_device(sc); -+ talitos_init_device(sc); -+#ifdef CONFIG_OCF_RANDOMHARVEST -+ if (sc->sc_exec_units & TALITOS_HAS_EU_RNG) -+ talitos_rng_init(sc); -+#endif -+ -+ /* Okay. Stand by. */ -+ spin_unlock_irqrestore(&sc->sc_chnfifolock[sc->sc_num_channels], flags); -+ -+ return; -+} -+ -+/* go through all channels descriptors, notifying OCF what's been done */ -+static void talitos_doneprocessing(struct talitos_softc *sc) -+{ -+ unsigned long flags; -+ int i, j; -+ -+ /* go through descriptors looking for done bits */ -+ for (i = 0; i < sc->sc_num_channels; i++) { -+ spin_lock_irqsave(&sc->sc_chnfifolock[i], flags); -+ for (j = 0; j < sc->sc_chfifo_len; j++) { -+ /* descriptor has done bits set? */ -+ if ((sc->sc_chnfifo[i][j].cf_desc.hdr -+ & TALITOS_HDR_DONE_BITS) -+ == TALITOS_HDR_DONE_BITS) { -+ /* notify ocf */ -+ crypto_done(sc->sc_chnfifo[i][j].cf_crp); -+ /* and tag it available again -+ * -+ * memset to ensure correct descriptor formation by -+ * avoiding inadvertently setting "optional" entries -+ * e.g. not using "optional" dptr2 MD/HMAC processing -+ */ -+ memset(&sc->sc_chnfifo[i][j].cf_desc, -+ 0, sizeof(struct talitos_desc)); -+ } -+ } -+ spin_unlock_irqrestore(&sc->sc_chnfifolock[i], flags); -+ } -+ return; -+} -+ -+static irqreturn_t -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) -+talitos_intr(int irq, void *arg) -+#else -+talitos_intr(int irq, void *arg, struct pt_regs *regs) -+#endif -+{ -+ struct talitos_softc *sc = arg; -+ u_int32_t v, v_hi; -+ -+ /* ack */ -+ v = talitos_read(sc->sc_base_addr + TALITOS_ISR); -+ v_hi = talitos_read(sc->sc_base_addr + TALITOS_ISR_HI); -+ talitos_write(sc->sc_base_addr + TALITOS_ICR, v); -+ talitos_write(sc->sc_base_addr + TALITOS_ICR_HI, v_hi); -+ -+ if (unlikely(v & TALITOS_ISR_ERROR)) { -+ /* Okay, Houston, we've had a problem here. */ -+ printk(KERN_DEBUG "%s: got error interrupt - ISR 0x%08x_%08x\n", -+ device_get_nameunit(sc->sc_cdev), v, v_hi); -+ talitos_errorprocessing(sc); -+ } else -+ if (likely(v & TALITOS_ISR_DONE)) { -+ talitos_doneprocessing(sc); -+ } -+ return IRQ_HANDLED; -+} -+ -+/* -+ * Initialize registers we need to touch only once. -+ */ -+static void -+talitos_init_device(struct talitos_softc *sc) -+{ -+ u_int32_t v; -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ /* init all channels */ -+ for (i = 0; i < sc->sc_num_channels; i++) { -+ v = talitos_read(sc->sc_base_addr + -+ i*TALITOS_CH_OFFSET + TALITOS_CH_CCCR_HI); -+ v |= TALITOS_CH_CCCR_HI_CDWE -+ | TALITOS_CH_CCCR_HI_CDIE; /* invoke interrupt if done */ -+ talitos_write(sc->sc_base_addr + -+ i*TALITOS_CH_OFFSET + TALITOS_CH_CCCR_HI, v); -+ } -+ /* enable all interrupts */ -+ v = talitos_read(sc->sc_base_addr + TALITOS_IMR); -+ v |= TALITOS_IMR_ALL; -+ talitos_write(sc->sc_base_addr + TALITOS_IMR, v); -+ v = talitos_read(sc->sc_base_addr + TALITOS_IMR_HI); -+ v |= TALITOS_IMR_HI_ERRONLY; -+ talitos_write(sc->sc_base_addr + TALITOS_IMR_HI, v); -+ return; -+} -+ -+/* -+ * set the master reset bit on the device. -+ */ -+static void -+talitos_reset_device_master(struct talitos_softc *sc) -+{ -+ u_int32_t v; -+ -+ /* Reset the device by writing 1 to MCR:SWR and waiting 'til cleared */ -+ v = talitos_read(sc->sc_base_addr + TALITOS_MCR); -+ talitos_write(sc->sc_base_addr + TALITOS_MCR, v | TALITOS_MCR_SWR); -+ -+ while (talitos_read(sc->sc_base_addr + TALITOS_MCR) & TALITOS_MCR_SWR) -+ cpu_relax(); -+ -+ return; -+} -+ -+/* -+ * Resets the device. Values in the registers are left as is -+ * from the reset (i.e. initial values are assigned elsewhere). -+ */ -+static void -+talitos_reset_device(struct talitos_softc *sc) -+{ -+ u_int32_t v; -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ /* -+ * Master reset -+ * errata documentation: warning: certain SEC interrupts -+ * are not fully cleared by writing the MCR:SWR bit, -+ * set bit twice to completely reset -+ */ -+ talitos_reset_device_master(sc); /* once */ -+ talitos_reset_device_master(sc); /* and once again */ -+ -+ /* reset all channels */ -+ for (i = 0; i < sc->sc_num_channels; i++) { -+ v = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + -+ TALITOS_CH_CCCR); -+ talitos_write(sc->sc_base_addr + i*TALITOS_CH_OFFSET + -+ TALITOS_CH_CCCR, v | TALITOS_CH_CCCR_RESET); -+ } -+} -+ -+/* Set up the crypto device structure, private data, -+ * and anything else we need before we start */ -+#ifdef CONFIG_PPC_MERGE -+static int talitos_probe(struct of_device *ofdev, const struct of_device_id *match) -+#else -+static int talitos_probe(struct platform_device *pdev) -+#endif -+{ -+ struct talitos_softc *sc = NULL; -+ struct resource *r; -+#ifdef CONFIG_PPC_MERGE -+ struct device *device = &ofdev->dev; -+ struct device_node *np = ofdev->node; -+ const unsigned int *prop; -+ int err; -+ struct resource res; -+#endif -+ static int num_chips = 0; -+ int rc; -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ sc = (struct talitos_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); -+ if (!sc) -+ return -ENOMEM; -+ memset(sc, 0, sizeof(*sc)); -+ -+ softc_device_init(sc, DRV_NAME, num_chips, talitos_methods); -+ -+ sc->sc_irq = -1; -+ sc->sc_cid = -1; -+#ifndef CONFIG_PPC_MERGE -+ sc->sc_dev = pdev; -+#endif -+ sc->sc_num = num_chips++; -+ -+#ifdef CONFIG_PPC_MERGE -+ dev_set_drvdata(device, sc); -+#else -+ platform_set_drvdata(sc->sc_dev, sc); -+#endif -+ -+ /* get the irq line */ -+#ifdef CONFIG_PPC_MERGE -+ err = of_address_to_resource(np, 0, &res); -+ if (err) -+ return -EINVAL; -+ r = &res; -+ -+ sc->sc_irq = irq_of_parse_and_map(np, 0); -+#else -+ /* get a pointer to the register memory */ -+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ -+ sc->sc_irq = platform_get_irq(pdev, 0); -+#endif -+ rc = request_irq(sc->sc_irq, talitos_intr, 0, -+ device_get_nameunit(sc->sc_cdev), sc); -+ if (rc) { -+ printk(KERN_ERR "%s: failed to hook irq %d\n", -+ device_get_nameunit(sc->sc_cdev), sc->sc_irq); -+ sc->sc_irq = -1; -+ goto out; -+ } -+ -+ sc->sc_base_addr = (ocf_iomem_t) ioremap(r->start, (r->end - r->start)); -+ if (!sc->sc_base_addr) { -+ printk(KERN_ERR "%s: failed to ioremap\n", -+ device_get_nameunit(sc->sc_cdev)); -+ goto out; -+ } -+ -+ /* figure out our SEC's properties and capabilities */ -+ sc->sc_chiprev = (u64)talitos_read(sc->sc_base_addr + TALITOS_ID) << 32 -+ | talitos_read(sc->sc_base_addr + TALITOS_ID_HI); -+ DPRINTF("sec id 0x%llx\n", sc->sc_chiprev); -+ -+#ifdef CONFIG_PPC_MERGE -+ /* get SEC properties from device tree, defaulting to SEC 2.0 */ -+ -+ prop = of_get_property(np, "num-channels", NULL); -+ sc->sc_num_channels = prop ? *prop : TALITOS_NCHANNELS_SEC_2_0; -+ -+ prop = of_get_property(np, "channel-fifo-len", NULL); -+ sc->sc_chfifo_len = prop ? *prop : TALITOS_CHFIFOLEN_SEC_2_0; -+ -+ prop = of_get_property(np, "exec-units-mask", NULL); -+ sc->sc_exec_units = prop ? *prop : TALITOS_HAS_EUS_SEC_2_0; -+ -+ prop = of_get_property(np, "descriptor-types-mask", NULL); -+ sc->sc_desc_types = prop ? *prop : TALITOS_HAS_DESCTYPES_SEC_2_0; -+#else -+ /* bulk should go away with openfirmware flat device tree support */ -+ if (sc->sc_chiprev & TALITOS_ID_SEC_2_0) { -+ sc->sc_num_channels = TALITOS_NCHANNELS_SEC_2_0; -+ sc->sc_chfifo_len = TALITOS_CHFIFOLEN_SEC_2_0; -+ sc->sc_exec_units = TALITOS_HAS_EUS_SEC_2_0; -+ sc->sc_desc_types = TALITOS_HAS_DESCTYPES_SEC_2_0; -+ } else { -+ printk(KERN_ERR "%s: failed to id device\n", -+ device_get_nameunit(sc->sc_cdev)); -+ goto out; -+ } -+#endif -+ -+ /* + 1 is for the meta-channel lock used by the channel scheduler */ -+ sc->sc_chnfifolock = (spinlock_t *) kmalloc( -+ (sc->sc_num_channels + 1) * sizeof(spinlock_t), GFP_KERNEL); -+ if (!sc->sc_chnfifolock) -+ goto out; -+ for (i = 0; i < sc->sc_num_channels + 1; i++) { -+ spin_lock_init(&sc->sc_chnfifolock[i]); -+ } -+ -+ sc->sc_chnlastalg = (int *) kmalloc( -+ sc->sc_num_channels * sizeof(int), GFP_KERNEL); -+ if (!sc->sc_chnlastalg) -+ goto out; -+ memset(sc->sc_chnlastalg, 0, sc->sc_num_channels * sizeof(int)); -+ -+ sc->sc_chnfifo = (struct desc_cryptop_pair **) kmalloc( -+ sc->sc_num_channels * sizeof(struct desc_cryptop_pair *), -+ GFP_KERNEL); -+ if (!sc->sc_chnfifo) -+ goto out; -+ for (i = 0; i < sc->sc_num_channels; i++) { -+ sc->sc_chnfifo[i] = (struct desc_cryptop_pair *) kmalloc( -+ sc->sc_chfifo_len * sizeof(struct desc_cryptop_pair), -+ GFP_KERNEL); -+ if (!sc->sc_chnfifo[i]) -+ goto out; -+ memset(sc->sc_chnfifo[i], 0, -+ sc->sc_chfifo_len * sizeof(struct desc_cryptop_pair)); -+ } -+ -+ /* reset and initialize the SEC h/w device */ -+ talitos_reset_device(sc); -+ talitos_init_device(sc); -+ -+ sc->sc_cid = crypto_get_driverid(softc_get_device(sc),CRYPTOCAP_F_HARDWARE); -+ if (sc->sc_cid < 0) { -+ printk(KERN_ERR "%s: could not get crypto driver id\n", -+ device_get_nameunit(sc->sc_cdev)); -+ goto out; -+ } -+ -+ /* register algorithms with the framework */ -+ printk("%s:", device_get_nameunit(sc->sc_cdev)); -+ -+ if (sc->sc_exec_units & TALITOS_HAS_EU_RNG) { -+ printk(" rng"); -+#ifdef CONFIG_OCF_RANDOMHARVEST -+ talitos_rng_init(sc); -+ crypto_rregister(sc->sc_cid, talitos_read_random, sc); -+#endif -+ } -+ if (sc->sc_exec_units & TALITOS_HAS_EU_DEU) { -+ printk(" des/3des"); -+ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); -+ } -+ if (sc->sc_exec_units & TALITOS_HAS_EU_AESU) { -+ printk(" aes"); -+ crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); -+ } -+ if (sc->sc_exec_units & TALITOS_HAS_EU_MDEU) { -+ printk(" md5"); -+ crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0); -+ /* HMAC support only with IPsec for now */ -+ crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); -+ printk(" sha1"); -+ crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0); -+ /* HMAC support only with IPsec for now */ -+ crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); -+ } -+ printk("\n"); -+ return 0; -+ -+out: -+#ifndef CONFIG_PPC_MERGE -+ talitos_remove(pdev); -+#endif -+ return -ENOMEM; -+} -+ -+#ifdef CONFIG_PPC_MERGE -+static int talitos_remove(struct of_device *ofdev) -+#else -+static int talitos_remove(struct platform_device *pdev) -+#endif -+{ -+#ifdef CONFIG_PPC_MERGE -+ struct talitos_softc *sc = dev_get_drvdata(&ofdev->dev); -+#else -+ struct talitos_softc *sc = platform_get_drvdata(pdev); -+#endif -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ if (sc->sc_cid >= 0) -+ crypto_unregister_all(sc->sc_cid); -+ if (sc->sc_chnfifo) { -+ for (i = 0; i < sc->sc_num_channels; i++) -+ if (sc->sc_chnfifo[i]) -+ kfree(sc->sc_chnfifo[i]); -+ kfree(sc->sc_chnfifo); -+ } -+ if (sc->sc_chnlastalg) -+ kfree(sc->sc_chnlastalg); -+ if (sc->sc_chnfifolock) -+ kfree(sc->sc_chnfifolock); -+ if (sc->sc_irq != -1) -+ free_irq(sc->sc_irq, sc); -+ if (sc->sc_base_addr) -+ iounmap((void *) sc->sc_base_addr); -+ kfree(sc); -+ return 0; -+} -+ -+#ifdef CONFIG_PPC_MERGE -+static struct of_device_id talitos_match[] = { -+ { -+ .type = "crypto", -+ .compatible = "talitos", -+ }, -+ {}, -+}; -+ -+MODULE_DEVICE_TABLE(of, talitos_match); -+ -+static struct of_platform_driver talitos_driver = { -+ .name = DRV_NAME, -+ .match_table = talitos_match, -+ .probe = talitos_probe, -+ .remove = talitos_remove, -+}; -+ -+static int __init talitos_init(void) -+{ -+ return of_register_platform_driver(&talitos_driver); -+} -+ -+static void __exit talitos_exit(void) -+{ -+ of_unregister_platform_driver(&talitos_driver); -+} -+#else -+/* Structure for a platform device driver */ -+static struct platform_driver talitos_driver = { -+ .probe = talitos_probe, -+ .remove = talitos_remove, -+ .driver = { -+ .name = "fsl-sec2", -+ } -+}; -+ -+static int __init talitos_init(void) -+{ -+ return platform_driver_register(&talitos_driver); -+} -+ -+static void __exit talitos_exit(void) -+{ -+ platform_driver_unregister(&talitos_driver); -+} -+#endif -+ -+module_init(talitos_init); -+module_exit(talitos_exit); -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_AUTHOR("kim.phillips@freescale.com"); -+MODULE_DESCRIPTION("OCF driver for Freescale SEC (talitos)"); -diff -Nur linux-2.6.36.orig/crypto/ocf/talitos/talitos_dev.h linux-2.6.36/crypto/ocf/talitos/talitos_dev.h ---- linux-2.6.36.orig/crypto/ocf/talitos/talitos_dev.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/talitos/talitos_dev.h 2010-11-09 20:28:13.232495491 +0100 -@@ -0,0 +1,277 @@ -+/* -+ * Freescale SEC (talitos) device dependent data structures -+ * -+ * Copyright (c) 2006 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ */ -+ -+/* device ID register values */ -+#define TALITOS_ID_SEC_2_0 0x40 -+#define TALITOS_ID_SEC_2_1 0x40 /* cross ref with IP block revision reg */ -+ -+/* -+ * following num_channels, channel-fifo-depth, exec-unit-mask, and -+ * descriptor-types-mask are for forward-compatibility with openfirmware -+ * flat device trees -+ */ -+ -+/* -+ * num_channels : the number of channels available in each SEC version. -+ */ -+ -+/* n.b. this driver requires these values be a power of 2 */ -+#define TALITOS_NCHANNELS_SEC_1_0 4 -+#define TALITOS_NCHANNELS_SEC_1_2 1 -+#define TALITOS_NCHANNELS_SEC_2_0 4 -+#define TALITOS_NCHANNELS_SEC_2_01 4 -+#define TALITOS_NCHANNELS_SEC_2_1 4 -+#define TALITOS_NCHANNELS_SEC_2_4 4 -+ -+/* -+ * channel-fifo-depth : The number of descriptor -+ * pointers a channel fetch fifo can hold. -+ */ -+#define TALITOS_CHFIFOLEN_SEC_1_0 1 -+#define TALITOS_CHFIFOLEN_SEC_1_2 1 -+#define TALITOS_CHFIFOLEN_SEC_2_0 24 -+#define TALITOS_CHFIFOLEN_SEC_2_01 24 -+#define TALITOS_CHFIFOLEN_SEC_2_1 24 -+#define TALITOS_CHFIFOLEN_SEC_2_4 24 -+ -+/* -+ * exec-unit-mask : The bitmask representing what Execution Units (EUs) -+ * are available. EU information should be encoded following the SEC's -+ * EU_SEL0 bitfield documentation, i.e. as follows: -+ * -+ * bit 31 = set if SEC permits no-EU selection (should be always set) -+ * bit 30 = set if SEC has the ARC4 EU (AFEU) -+ * bit 29 = set if SEC has the des/3des EU (DEU) -+ * bit 28 = set if SEC has the message digest EU (MDEU) -+ * bit 27 = set if SEC has the random number generator EU (RNG) -+ * bit 26 = set if SEC has the public key EU (PKEU) -+ * bit 25 = set if SEC has the aes EU (AESU) -+ * bit 24 = set if SEC has the Kasumi EU (KEU) -+ * -+ */ -+#define TALITOS_HAS_EU_NONE (1<<0) -+#define TALITOS_HAS_EU_AFEU (1<<1) -+#define TALITOS_HAS_EU_DEU (1<<2) -+#define TALITOS_HAS_EU_MDEU (1<<3) -+#define TALITOS_HAS_EU_RNG (1<<4) -+#define TALITOS_HAS_EU_PKEU (1<<5) -+#define TALITOS_HAS_EU_AESU (1<<6) -+#define TALITOS_HAS_EU_KEU (1<<7) -+ -+/* the corresponding masks for each SEC version */ -+#define TALITOS_HAS_EUS_SEC_1_0 0x7f -+#define TALITOS_HAS_EUS_SEC_1_2 0x4d -+#define TALITOS_HAS_EUS_SEC_2_0 0x7f -+#define TALITOS_HAS_EUS_SEC_2_01 0x7f -+#define TALITOS_HAS_EUS_SEC_2_1 0xff -+#define TALITOS_HAS_EUS_SEC_2_4 0x7f -+ -+/* -+ * descriptor-types-mask : The bitmask representing what descriptors -+ * are available. Descriptor type information should be encoded -+ * following the SEC's Descriptor Header Dword DESC_TYPE field -+ * documentation, i.e. as follows: -+ * -+ * bit 0 = set if SEC supports the aesu_ctr_nonsnoop desc. type -+ * bit 1 = set if SEC supports the ipsec_esp descriptor type -+ * bit 2 = set if SEC supports the common_nonsnoop desc. type -+ * bit 3 = set if SEC supports the 802.11i AES ccmp desc. type -+ * bit 4 = set if SEC supports the hmac_snoop_no_afeu desc. type -+ * bit 5 = set if SEC supports the srtp descriptor type -+ * bit 6 = set if SEC supports the non_hmac_snoop_no_afeu desc.type -+ * bit 7 = set if SEC supports the pkeu_assemble descriptor type -+ * bit 8 = set if SEC supports the aesu_key_expand_output desc.type -+ * bit 9 = set if SEC supports the pkeu_ptmul descriptor type -+ * bit 10 = set if SEC supports the common_nonsnoop_afeu desc. type -+ * bit 11 = set if SEC supports the pkeu_ptadd_dbl descriptor type -+ * -+ * ..and so on and so forth. -+ */ -+#define TALITOS_HAS_DT_AESU_CTR_NONSNOOP (1<<0) -+#define TALITOS_HAS_DT_IPSEC_ESP (1<<1) -+#define TALITOS_HAS_DT_COMMON_NONSNOOP (1<<2) -+ -+/* the corresponding masks for each SEC version */ -+#define TALITOS_HAS_DESCTYPES_SEC_2_0 0x01010ebf -+#define TALITOS_HAS_DESCTYPES_SEC_2_1 0x012b0ebf -+ -+/* -+ * a TALITOS_xxx_HI address points to the low data bits (32-63) of the register -+ */ -+ -+/* global register offset addresses */ -+#define TALITOS_ID 0x1020 -+#define TALITOS_ID_HI 0x1024 -+#define TALITOS_MCR 0x1030 /* master control register */ -+#define TALITOS_MCR_HI 0x1038 /* master control register */ -+#define TALITOS_MCR_SWR 0x1 -+#define TALITOS_IMR 0x1008 /* interrupt mask register */ -+#define TALITOS_IMR_ALL 0x00010fff /* enable all interrupts mask */ -+#define TALITOS_IMR_ERRONLY 0x00010aaa /* enable error interrupts */ -+#define TALITOS_IMR_HI 0x100C /* interrupt mask register */ -+#define TALITOS_IMR_HI_ALL 0x00323333 /* enable all interrupts mask */ -+#define TALITOS_IMR_HI_ERRONLY 0x00222222 /* enable error interrupts */ -+#define TALITOS_ISR 0x1010 /* interrupt status register */ -+#define TALITOS_ISR_ERROR 0x00010faa /* errors mask */ -+#define TALITOS_ISR_DONE 0x00000055 /* channel(s) done mask */ -+#define TALITOS_ISR_HI 0x1014 /* interrupt status register */ -+#define TALITOS_ICR 0x1018 /* interrupt clear register */ -+#define TALITOS_ICR_HI 0x101C /* interrupt clear register */ -+ -+/* channel register address stride */ -+#define TALITOS_CH_OFFSET 0x100 -+ -+/* channel register offset addresses and bits */ -+#define TALITOS_CH_CCCR 0x1108 /* Crypto-Channel Config Register */ -+#define TALITOS_CH_CCCR_RESET 0x1 /* Channel Reset bit */ -+#define TALITOS_CH_CCCR_HI 0x110c /* Crypto-Channel Config Register */ -+#define TALITOS_CH_CCCR_HI_CDWE 0x10 /* Channel done writeback enable bit */ -+#define TALITOS_CH_CCCR_HI_NT 0x4 /* Notification type bit */ -+#define TALITOS_CH_CCCR_HI_CDIE 0x2 /* Channel Done Interrupt Enable bit */ -+#define TALITOS_CH_CCPSR 0x1110 /* Crypto-Channel Pointer Status Reg */ -+#define TALITOS_CH_CCPSR_HI 0x1114 /* Crypto-Channel Pointer Status Reg */ -+#define TALITOS_CH_FF 0x1148 /* Fetch FIFO */ -+#define TALITOS_CH_FF_HI 0x114c /* Fetch FIFO's FETCH_ADRS */ -+#define TALITOS_CH_CDPR 0x1140 /* Crypto-Channel Pointer Status Reg */ -+#define TALITOS_CH_CDPR_HI 0x1144 /* Crypto-Channel Pointer Status Reg */ -+#define TALITOS_CH_DESCBUF 0x1180 /* (thru 11bf) Crypto-Channel -+ * Descriptor Buffer (debug) */ -+ -+/* execution unit register offset addresses and bits */ -+#define TALITOS_DEUSR 0x2028 /* DEU status register */ -+#define TALITOS_DEUSR_HI 0x202c /* DEU status register */ -+#define TALITOS_DEUISR 0x2030 /* DEU interrupt status register */ -+#define TALITOS_DEUISR_HI 0x2034 /* DEU interrupt status register */ -+#define TALITOS_DEUICR 0x2038 /* DEU interrupt control register */ -+#define TALITOS_DEUICR_HI 0x203c /* DEU interrupt control register */ -+#define TALITOS_AESUISR 0x4030 /* AESU interrupt status register */ -+#define TALITOS_AESUISR_HI 0x4034 /* AESU interrupt status register */ -+#define TALITOS_AESUICR 0x4038 /* AESU interrupt control register */ -+#define TALITOS_AESUICR_HI 0x403c /* AESU interrupt control register */ -+#define TALITOS_MDEUISR 0x6030 /* MDEU interrupt status register */ -+#define TALITOS_MDEUISR_HI 0x6034 /* MDEU interrupt status register */ -+#define TALITOS_RNGSR 0xa028 /* RNG status register */ -+#define TALITOS_RNGSR_HI 0xa02c /* RNG status register */ -+#define TALITOS_RNGSR_HI_RD 0x1 /* RNG Reset done */ -+#define TALITOS_RNGSR_HI_OFL 0xff0000/* number of dwords in RNG output FIFO*/ -+#define TALITOS_RNGDSR 0xa010 /* RNG data size register */ -+#define TALITOS_RNGDSR_HI 0xa014 /* RNG data size register */ -+#define TALITOS_RNG_FIFO 0xa800 /* RNG FIFO - pool of random numbers */ -+#define TALITOS_RNGISR 0xa030 /* RNG Interrupt status register */ -+#define TALITOS_RNGISR_HI 0xa034 /* RNG Interrupt status register */ -+#define TALITOS_RNGRCR 0xa018 /* RNG Reset control register */ -+#define TALITOS_RNGRCR_HI 0xa01c /* RNG Reset control register */ -+#define TALITOS_RNGRCR_HI_SR 0x1 /* RNG RNGRCR:Software Reset */ -+ -+/* descriptor pointer entry */ -+struct talitos_desc_ptr { -+ u16 len; /* length */ -+ u8 extent; /* jump (to s/g link table) and extent */ -+ u8 res; /* reserved */ -+ u32 ptr; /* pointer */ -+}; -+ -+/* descriptor */ -+struct talitos_desc { -+ u32 hdr; /* header */ -+ u32 res; /* reserved */ -+ struct talitos_desc_ptr ptr[7]; /* ptr/len pair array */ -+}; -+ -+/* talitos descriptor header (hdr) bits */ -+ -+/* primary execution unit select */ -+#define TALITOS_SEL0_AFEU 0x10000000 -+#define TALITOS_SEL0_DEU 0x20000000 -+#define TALITOS_SEL0_MDEU 0x30000000 -+#define TALITOS_SEL0_RNG 0x40000000 -+#define TALITOS_SEL0_PKEU 0x50000000 -+#define TALITOS_SEL0_AESU 0x60000000 -+ -+/* primary execution unit mode (MODE0) and derivatives */ -+#define TALITOS_MODE0_AESU_CBC 0x00200000 -+#define TALITOS_MODE0_AESU_ENC 0x00100000 -+#define TALITOS_MODE0_DEU_CBC 0x00400000 -+#define TALITOS_MODE0_DEU_3DES 0x00200000 -+#define TALITOS_MODE0_DEU_ENC 0x00100000 -+#define TALITOS_MODE0_MDEU_INIT 0x01000000 /* init starting regs */ -+#define TALITOS_MODE0_MDEU_HMAC 0x00800000 -+#define TALITOS_MODE0_MDEU_PAD 0x00400000 /* PD */ -+#define TALITOS_MODE0_MDEU_MD5 0x00200000 -+#define TALITOS_MODE0_MDEU_SHA256 0x00100000 -+#define TALITOS_MODE0_MDEU_SHA1 0x00000000 /* SHA-160 */ -+#define TALITOS_MODE0_MDEU_MD5_HMAC \ -+ (TALITOS_MODE0_MDEU_MD5 | TALITOS_MODE0_MDEU_HMAC) -+#define TALITOS_MODE0_MDEU_SHA256_HMAC \ -+ (TALITOS_MODE0_MDEU_SHA256 | TALITOS_MODE0_MDEU_HMAC) -+#define TALITOS_MODE0_MDEU_SHA1_HMAC \ -+ (TALITOS_MODE0_MDEU_SHA1 | TALITOS_MODE0_MDEU_HMAC) -+ -+/* secondary execution unit select (SEL1) */ -+/* it's MDEU or nothing */ -+#define TALITOS_SEL1_MDEU 0x00030000 -+ -+/* secondary execution unit mode (MODE1) and derivatives */ -+#define TALITOS_MODE1_MDEU_INIT 0x00001000 /* init starting regs */ -+#define TALITOS_MODE1_MDEU_HMAC 0x00000800 -+#define TALITOS_MODE1_MDEU_PAD 0x00000400 /* PD */ -+#define TALITOS_MODE1_MDEU_MD5 0x00000200 -+#define TALITOS_MODE1_MDEU_SHA256 0x00000100 -+#define TALITOS_MODE1_MDEU_SHA1 0x00000000 /* SHA-160 */ -+#define TALITOS_MODE1_MDEU_MD5_HMAC \ -+ (TALITOS_MODE1_MDEU_MD5 | TALITOS_MODE1_MDEU_HMAC) -+#define TALITOS_MODE1_MDEU_SHA256_HMAC \ -+ (TALITOS_MODE1_MDEU_SHA256 | TALITOS_MODE1_MDEU_HMAC) -+#define TALITOS_MODE1_MDEU_SHA1_HMAC \ -+ (TALITOS_MODE1_MDEU_SHA1 | TALITOS_MODE1_MDEU_HMAC) -+ -+/* direction of overall data flow (DIR) */ -+#define TALITOS_DIR_OUTBOUND 0x00000000 -+#define TALITOS_DIR_INBOUND 0x00000002 -+ -+/* done notification (DN) */ -+#define TALITOS_DONE_NOTIFY 0x00000001 -+ -+/* descriptor types */ -+/* odd numbers here are valid on SEC2 and greater only (e.g. ipsec_esp) */ -+#define TD_TYPE_AESU_CTR_NONSNOOP (0 << 3) -+#define TD_TYPE_IPSEC_ESP (1 << 3) -+#define TD_TYPE_COMMON_NONSNOOP_NO_AFEU (2 << 3) -+#define TD_TYPE_HMAC_SNOOP_NO_AFEU (4 << 3) -+ -+#define TALITOS_HDR_DONE_BITS 0xff000000 -+ -+#define DPRINTF(a...) do { \ -+ if (debug) { \ -+ printk("%s: ", sc ? \ -+ device_get_nameunit(sc->sc_cdev) : "talitos"); \ -+ printk(a); \ -+ } \ -+ } while (0) -diff -Nur linux-2.6.36.orig/crypto/ocf/talitos/talitos_soft.h linux-2.6.36/crypto/ocf/talitos/talitos_soft.h ---- linux-2.6.36.orig/crypto/ocf/talitos/talitos_soft.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/talitos/talitos_soft.h 2010-11-09 20:28:13.272495451 +0100 -@@ -0,0 +1,77 @@ -+/* -+ * Freescale SEC data structures for integration with ocf-linux -+ * -+ * Copyright (c) 2006 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/* -+ * paired descriptor and associated crypto operation -+ */ -+struct desc_cryptop_pair { -+ struct talitos_desc cf_desc; /* descriptor ptr */ -+ struct cryptop *cf_crp; /* cryptop ptr */ -+}; -+ -+/* -+ * Holds data specific to a single talitos device. -+ */ -+struct talitos_softc { -+ softc_device_decl sc_cdev; -+ struct platform_device *sc_dev; /* device backpointer */ -+ ocf_iomem_t sc_base_addr; -+ int sc_irq; -+ int sc_num; /* if we have multiple chips */ -+ int32_t sc_cid; /* crypto tag */ -+ u64 sc_chiprev; /* major/minor chip revision */ -+ int sc_nsessions; -+ struct talitos_session *sc_sessions; -+ int sc_num_channels;/* number of crypto channels */ -+ int sc_chfifo_len; /* channel fetch fifo len */ -+ int sc_exec_units; /* execution units mask */ -+ int sc_desc_types; /* descriptor types mask */ -+ /* -+ * mutual exclusion for intra-channel resources, e.g. fetch fifos -+ * the last entry is a meta-channel lock used by the channel scheduler -+ */ -+ spinlock_t *sc_chnfifolock; -+ /* sc_chnlastalgo contains last algorithm for that channel */ -+ int *sc_chnlastalg; -+ /* sc_chnfifo holds pending descriptor--crypto operation pairs */ -+ struct desc_cryptop_pair **sc_chnfifo; -+}; -+ -+struct talitos_session { -+ u_int32_t ses_used; -+ u_int32_t ses_klen; /* key length in bits */ -+ u_int32_t ses_key[8]; /* DES/3DES/AES key */ -+ u_int32_t ses_hmac[5]; /* hmac inner state */ -+ u_int32_t ses_hmac_len; /* hmac length */ -+ u_int32_t ses_iv[4]; /* DES/3DES/AES iv */ -+ u_int32_t ses_mlen; /* desired hash result len (12=ipsec or 16) */ -+}; -+ -+#define TALITOS_SESSION(sid) ((sid) & 0x0fffffff) -+#define TALITOS_SID(crd, sesn) (((crd) << 28) | ((sesn) & 0x0fffffff)) -diff -Nur linux-2.6.36.orig/crypto/ocf/uio.h linux-2.6.36/crypto/ocf/uio.h ---- linux-2.6.36.orig/crypto/ocf/uio.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/crypto/ocf/uio.h 2010-11-09 20:28:13.313482727 +0100 -@@ -0,0 +1,54 @@ -+#ifndef _OCF_UIO_H_ -+#define _OCF_UIO_H_ -+ -+#include -+ -+/* -+ * The linux uio.h doesn't have all we need. To be fully api compatible -+ * with the BSD cryptodev, we need to keep this around. Perhaps this can -+ * be moved back into the linux/uio.h -+ * -+ * Linux port done by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * ALTERNATIVELY, provided that this notice is retained in full, this product -+ * may be distributed under the terms of the GNU General Public License (GPL), -+ * in which case the provisions of the GPL apply INSTEAD OF those given above. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ * --------------------------------------------------------------------------- -+ */ -+ -+struct uio { -+ struct iovec *uio_iov; -+ int uio_iovcnt; -+ off_t uio_offset; -+ int uio_resid; -+#if 0 -+ enum uio_seg uio_segflg; -+ enum uio_rw uio_rw; -+ struct thread *uio_td; -+#endif -+}; -+ -+#endif -diff -Nur linux-2.6.36.orig/drivers/char/random.c linux-2.6.36/drivers/char/random.c ---- linux-2.6.36.orig/drivers/char/random.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/drivers/char/random.c 2010-11-09 20:28:13.352495461 +0100 -@@ -129,6 +129,9 @@ - * unsigned int value); - * void add_interrupt_randomness(int irq); - * -+ * void random_input_words(__u32 *buf, size_t wordcount, int ent_count) -+ * int random_input_wait(void); -+ * - * add_input_randomness() uses the input layer interrupt timing, as well as - * the event type information from the hardware. - * -@@ -140,6 +143,13 @@ - * a better measure, since the timing of the disk interrupts are more - * unpredictable. - * -+ * random_input_words() just provides a raw block of entropy to the input -+ * pool, such as from a hardware entropy generator. -+ * -+ * random_input_wait() suspends the caller until such time as the -+ * entropy pool falls below the write threshold, and returns a count of how -+ * much entropy (in bits) is needed to sustain the pool. -+ * - * All of these routines try to estimate how many bits of randomness a - * particular randomness source. They do this by keeping track of the - * first and second order deltas of the event timings. -@@ -259,6 +269,7 @@ - #define SEC_XFER_SIZE 512 - #define EXTRACT_SIZE 10 - -+ - /* - * The minimum number of bits of entropy before we wake up a read on - * /dev/random. Should be enough to do a significant reseed. -@@ -552,6 +563,60 @@ - spin_unlock_irqrestore(&r->lock, flags); - } - -+/* -+ * random_input_words - add bulk entropy to pool -+ * -+ * @buf: buffer to add -+ * @wordcount: number of __u32 words to add -+ * @ent_count: total amount of entropy (in bits) to credit -+ * -+ * this provides bulk input of entropy to the input pool -+ * -+ */ -+void random_input_words(__u32 *buf, size_t wordcount, int ent_count) -+{ -+ mix_pool_bytes(&input_pool, buf, wordcount*4); -+ -+ credit_entropy_bits(&input_pool, ent_count); -+ -+ DEBUG_ENT("crediting %d bits => %d\n", -+ ent_count, input_pool.entropy_count); -+ /* -+ * Wake up waiting processes if we have enough -+ * entropy. -+ */ -+ if (input_pool.entropy_count >= random_read_wakeup_thresh) -+ wake_up_interruptible(&random_read_wait); -+} -+EXPORT_SYMBOL(random_input_words); -+ -+/* -+ * random_input_wait - wait until random needs entropy -+ * -+ * this function sleeps until the /dev/random subsystem actually -+ * needs more entropy, and then return the amount of entropy -+ * that it would be nice to have added to the system. -+ */ -+int random_input_wait(void) -+{ -+ int count; -+ -+ wait_event_interruptible(random_write_wait, -+ input_pool.entropy_count < random_write_wakeup_thresh); -+ -+ count = random_write_wakeup_thresh - input_pool.entropy_count; -+ -+ /* likely we got woken up due to a signal */ -+ if (count <= 0) count = random_read_wakeup_thresh; -+ -+ DEBUG_ENT("requesting %d bits from input_wait()er %d<%d\n", -+ count, -+ input_pool.entropy_count, random_write_wakeup_thresh); -+ -+ return count; -+} -+EXPORT_SYMBOL(random_input_wait); -+ - /********************************************************************* - * - * Entropy input management -diff -Nur linux-2.6.36.orig/fs/fcntl.c linux-2.6.36/fs/fcntl.c ---- linux-2.6.36.orig/fs/fcntl.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/fs/fcntl.c 2010-11-09 20:28:13.392495458 +0100 -@@ -142,6 +142,7 @@ - } - return ret; - } -+EXPORT_SYMBOL(sys_dup); - - #define SETFL_MASK (O_APPEND | O_NONBLOCK | O_NDELAY | O_DIRECT | O_NOATIME) - -diff -Nur linux-2.6.36.orig/include/linux/miscdevice.h linux-2.6.36/include/linux/miscdevice.h ---- linux-2.6.36.orig/include/linux/miscdevice.h 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/include/linux/miscdevice.h 2010-11-09 20:28:13.432495492 +0100 -@@ -18,6 +18,7 @@ - #define APOLLO_MOUSE_MINOR 7 - #define PC110PAD_MINOR 9 - /*#define ADB_MOUSE_MINOR 10 FIXME OBSOLETE */ -+#define CRYPTODEV_MINOR 70 /* /dev/crypto */ - #define WATCHDOG_MINOR 130 /* Watchdog timer */ - #define TEMP_MINOR 131 /* Temperature Sensor */ - #define RTC_MINOR 135 -diff -Nur linux-2.6.36.orig/include/linux/random.h linux-2.6.36/include/linux/random.h ---- linux-2.6.36.orig/include/linux/random.h 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/include/linux/random.h 2010-11-09 20:28:13.597270121 +0100 -@@ -9,6 +9,7 @@ - - #include - #include -+#include /* for __u32 in user space */ - #include - - /* ioctl()'s for the random number generator */ -@@ -34,6 +35,30 @@ - /* Clear the entropy pool and associated counters. (Superuser only.) */ - #define RNDCLEARPOOL _IO( 'R', 0x06 ) - -+#ifdef CONFIG_FIPS_RNG -+ -+/* Size of seed value - equal to AES blocksize */ -+#define AES_BLOCK_SIZE_BYTES 16 -+#define SEED_SIZE_BYTES AES_BLOCK_SIZE_BYTES -+/* Size of AES key */ -+#define KEY_SIZE_BYTES 16 -+ -+/* ioctl() structure used by FIPS 140-2 Tests */ -+struct rand_fips_test { -+ unsigned char key[KEY_SIZE_BYTES]; /* Input */ -+ unsigned char datetime[SEED_SIZE_BYTES]; /* Input */ -+ unsigned char seed[SEED_SIZE_BYTES]; /* Input */ -+ unsigned char result[SEED_SIZE_BYTES]; /* Output */ -+}; -+ -+/* FIPS 140-2 RNG Variable Seed Test. (Superuser only.) */ -+#define RNDFIPSVST _IOWR('R', 0x10, struct rand_fips_test) -+ -+/* FIPS 140-2 RNG Monte Carlo Test. (Superuser only.) */ -+#define RNDFIPSMCT _IOWR('R', 0x11, struct rand_fips_test) -+ -+#endif /* #ifdef CONFIG_FIPS_RNG */ -+ - struct rand_pool_info { - int entropy_count; - int buf_size; -@@ -54,6 +79,10 @@ - unsigned int value); - extern void add_interrupt_randomness(int irq); - -+extern void random_input_words(__u32 *buf, size_t wordcount, int ent_count); -+extern int random_input_wait(void); -+#define HAS_RANDOM_INPUT_WAIT 1 -+ - extern void get_random_bytes(void *buf, int nbytes); - void generate_random_uuid(unsigned char uuid_out[16]); - diff --git a/target/linux/patches/2.6.37/rb532.patch b/target/linux/patches/2.6.37/rb532.patch deleted file mode 100644 index be68c65f0..000000000 --- a/target/linux/patches/2.6.37/rb532.patch +++ /dev/null @@ -1,18 +0,0 @@ -diff -Nur linux-2.6.36.orig/arch/mips/rb532/devices.c linux-2.6.36/arch/mips/rb532/devices.c ---- linux-2.6.36.orig/arch/mips/rb532/devices.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/arch/mips/rb532/devices.c 2010-12-21 20:26:05.000000000 +0100 -@@ -190,8 +190,12 @@ - }, { - .name = "rootfs", - .offset = MTDPART_OFS_NXTBLK, -- .size = MTDPART_SIZ_FULL, -- } -+ .size = 0x8000000 - 0x400000 - 0x400000, -+ }, { -+ .name = "cfgfs", -+ .offset = 0x8000000 - 0x400000, -+ .size = 0x400000, -+ }, - }; - - static struct platform_device rb532_led = { diff --git a/target/linux/patches/2.6.37/startup.patch b/target/linux/patches/2.6.37/startup.patch deleted file mode 100644 index 68e8987b0..000000000 --- a/target/linux/patches/2.6.37/startup.patch +++ /dev/null @@ -1,20 +0,0 @@ -diff -Nur linux-2.6.34.orig/init/main.c linux-2.6.34/init/main.c ---- linux-2.6.34.orig/init/main.c 2010-05-16 23:17:36.000000000 +0200 -+++ linux-2.6.34/init/main.c 2010-05-20 20:13:26.321613615 +0200 -@@ -842,6 +842,7 @@ - printk(KERN_WARNING "Failed to execute %s. Attempting " - "defaults...\n", execute_command); - } -+ run_init_process("/init"); - run_init_process("/sbin/init"); - run_init_process("/etc/init"); - run_init_process("/bin/init"); -@@ -889,6 +890,8 @@ - if (sys_open((const char __user *) "/dev/console", O_RDWR, 0) < 0) - printk(KERN_WARNING "Warning: unable to open an initial console.\n"); - -+ printk(KERN_WARNING "Starting Linux (built with OpenADK).\n"); -+ - (void) sys_dup(0); - (void) sys_dup(0); - /* diff --git a/target/linux/patches/2.6.37/usb-defaults-off.patch b/target/linux/patches/2.6.37/usb-defaults-off.patch deleted file mode 100644 index 31367108a..000000000 --- a/target/linux/patches/2.6.37/usb-defaults-off.patch +++ /dev/null @@ -1,32 +0,0 @@ -diff -Nur linux-2.6.37.orig//drivers/usb/core/Kconfig linux-2.6.37/drivers/usb/core/Kconfig ---- linux-2.6.37.orig//drivers/usb/core/Kconfig 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/usb/core/Kconfig 2011-04-12 19:04:23.000000000 +0200 -@@ -59,7 +59,7 @@ - config USB_DEVICE_CLASS - bool "USB device class-devices (DEPRECATED)" - depends on USB -- default y -+ default n - ---help--- - Userspace access to USB devices is granted by device-nodes exported - directly from the usbdev in sysfs. Old versions of the driver -diff -Nur linux-2.6.37.orig//drivers/usb/host/Kconfig linux-2.6.37/drivers/usb/host/Kconfig ---- linux-2.6.37.orig//drivers/usb/host/Kconfig 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/usb/host/Kconfig 2011-04-12 19:04:48.000000000 +0200 -@@ -62,6 +62,7 @@ - config USB_EHCI_ROOT_HUB_TT - bool "Root Hub Transaction Translators" - depends on USB_EHCI_HCD -+ default n - ---help--- - Some EHCI chips have vendor-specific extensions to integrate - transaction translators, so that no OHCI or UHCI companion -@@ -74,7 +75,7 @@ - config USB_EHCI_TT_NEWSCHED - bool "Improved Transaction Translator scheduling" - depends on USB_EHCI_HCD -- default y -+ default n - ---help--- - This changes the periodic scheduling code to fill more of the low - and full speed bandwidth available from the Transaction Translator diff --git a/target/linux/patches/2.6.37/uuid.patch b/target/linux/patches/2.6.37/uuid.patch deleted file mode 100644 index cf2869ed2..000000000 --- a/target/linux/patches/2.6.37/uuid.patch +++ /dev/null @@ -1,261 +0,0 @@ -# DP: Add support for specifying the root device using UUIDs on the -# DP: kernel command line like this without the need for an initrd: -# DP: linux ... root=UUID=ce40d6b2-18eb-4a75-aefe-7ddb0995ce63 -# DP: Note: debugging code is kept in, commented out “//†style. -# DP: -# DP: Written © 2010 by Thorsten Glaser -# DP: Idea from 1999 by David Balazic - ---- linux-2.6.36/block/genhd.c~ Wed Oct 20 22:30:22 2010 -+++ linux-2.6.36/block/genhd.c Sat Nov 20 23:14:03 2010 -@@ -35,7 +35,7 @@ struct kobject *block_depr; - static DEFINE_MUTEX(ext_devt_mutex); - static DEFINE_IDR(ext_devt_idr); - --static struct device_type disk_type; -+struct device_type disk_type; - - /** - * disk_get_part - get partition -@@ -1019,7 +1019,7 @@ static char *block_devnode(struct device *dev, mode_t - return NULL; - } - --static struct device_type disk_type = { -+struct device_type disk_type = { - .name = "disk", - .groups = disk_attr_groups, - .release = disk_release, ---- linux-2.6.36/init/do_mounts.c~ Wed Oct 20 20:29:58 2010 -+++ linux-2.6.36/init/do_mounts.c Sun Nov 21 18:37:36 2010 -@@ -32,6 +32,132 @@ static int __initdata root_wait; - - dev_t ROOT_DEV; - -+#ifdef CONFIG_EXT2_FS -+/* support for root=UUID=ce40d6b2-18eb-4a75-aefe-7ddb0995ce63 bootargs */ -+ -+#include -+ -+__u8 root_dev_uuid[16]; -+int root_dev_type; /* 0 = normal (/dev/hda1, 0301); 1 = UUID; 3 = bad */ -+ -+/* imported from block/genhd.c after removing its static qualifier */ -+extern struct device_type disk_type; -+ -+/* helper function */ -+static __u8 __init fromhex(char c) -+{ -+ if (c >= '0' && c <= '9') -+ return (c - '0'); -+ c &= ~32; -+ if (c >= 'A' && c <= 'F') -+ return (c - 'A' + 10); -+ return (0xFF); -+} -+ -+static void __init parse_uuid(const char *s) -+{ -+ int i; -+ __u8 j, k; -+ -+ if (strlen(s) != 36 || s[8] != '-' || s[13] != '-' || -+ s[18] != '-' || s[23] != '-') -+ goto bad_uuid; -+ for (i = 0; i < 16; i++) { -+ if (*s == '-') -+ ++s; -+ j = fromhex(*s++); -+ k = fromhex(*s++); -+ if (j == 0xFF || k == 0xFF) -+ goto bad_uuid; -+ root_dev_uuid[i] = (j << 4) | k; -+ } -+ return; -+ bad_uuid: -+ /* we cannot panic here, defer */ -+ root_dev_type = 3; -+} -+ -+/* from drivers/md/md.c */ -+static void __init initcode_bi_complete(struct bio *bio, int error) -+{ -+ complete((struct completion*)bio->bi_private); -+} -+ -+static int __init initcode_sync_page_read(struct block_device *bdev, -+ sector_t sector, int size, struct page *page) -+{ -+ struct bio *bio = bio_alloc(GFP_NOIO, 1); -+ struct completion event; -+ int ret, rw = READ; -+ -+ rw |= REQ_SYNC | REQ_UNPLUG; -+ -+ bio->bi_bdev = bdev; -+ bio->bi_sector = sector; -+ bio_add_page(bio, page, size, 0); -+ init_completion(&event); -+ bio->bi_private = &event; -+ bio->bi_end_io = initcode_bi_complete; -+ submit_bio(rw, bio); -+ wait_for_completion(&event); -+ -+ ret = test_bit(BIO_UPTODATE, &bio->bi_flags); -+ bio_put(bio); -+ /* 0 = failure */ -+ return ret; -+} -+ -+/* most of this taken from fs/ext2/super.c */ -+static int __init check_dev(struct gendisk *thedisk, dev_t devt, -+ int blocksize, struct page *page) -+{ -+ struct ext2_super_block * es; -+ struct block_device *bdev; -+ unsigned long sb_block = 1; -+ unsigned long logic_sb_block; -+ unsigned long offset = 0; -+ int rv = /* not found */ 0; -+ char bff[22]; -+ -+ bdev = bdget(devt); -+ if (blkdev_get(bdev, FMODE_READ)) { -+ printk(KERN_ERR "VFS: opening block device %s failed!\n", -+ format_dev_t(bff, devt)); -+ return (0); -+ } -+ -+ if (blocksize != BLOCK_SIZE) { -+ logic_sb_block = (sb_block*BLOCK_SIZE) / blocksize; -+ offset = (sb_block*BLOCK_SIZE) % blocksize; -+ } else { -+ logic_sb_block = sb_block; -+ } -+ -+// printk(KERN_ERR "D: attempting to read %d @%lu from " -+// "bdev %p devt %08X %s\n", blocksize, logic_sb_block, -+// bdev, devt, format_dev_t(bff, devt)); -+ if (!initcode_sync_page_read(bdev, logic_sb_block, blocksize, page)) { -+// printk(KERN_ERR "D: failed!\n"); -+ goto out; -+ } -+ es = (struct ext2_super_block *)(((char *)page_address(page)) + offset); -+ if (le16_to_cpu(es->s_magic) == EXT2_SUPER_MAGIC) { -+// printk(KERN_ERR "D: has uuid " -+// "%02X%02X%02X%02X-%02X%02X-%02X%02X-%02X%02X-%02X%02X%02X%02X%02X%02X\n", -+// es->s_uuid[0], es->s_uuid[1], es->s_uuid[2], es->s_uuid[3], -+// es->s_uuid[4], es->s_uuid[5], es->s_uuid[6], es->s_uuid[7], -+// es->s_uuid[8], es->s_uuid[9], es->s_uuid[10], es->s_uuid[11], -+// es->s_uuid[12], es->s_uuid[13], es->s_uuid[14], es->s_uuid[15]); -+ if (!memcmp(es->s_uuid, root_dev_uuid, 16)) -+ rv = /* found */ 1; -+ } -+// else printk(KERN_ERR "D: bad ext2fs magic\n"); -+ out: -+ blkdev_put(bdev, FMODE_READ); -+ return (rv); -+} -+#endif /* CONFIG_EXT2_FS for UUID support */ -+ - static int __init load_ramdisk(char *str) - { - rd_doload = simple_strtol(str,NULL,0) & 3; -@@ -148,6 +274,13 @@ done: - static int __init root_dev_setup(char *line) - { - strlcpy(saved_root_name, line, sizeof(saved_root_name)); -+#ifdef CONFIG_EXT2_FS -+ root_dev_type = 0; -+ if (!strncmp(line, "UUID=", 5)) { -+ root_dev_type = 1; -+ parse_uuid(line + 5); -+ } -+#endif /* CONFIG_EXT2_FS for UUID support */ - return 1; - } - -@@ -333,6 +466,83 @@ void __init change_floppy(char *fmt, ... - - void __init mount_root(void) - { -+#ifdef CONFIG_EXT2_FS -+ /* UUID support */ -+// printk_all_partitions(); -+ if (root_dev_type == 1) { -+ int blocksize; -+ -+ /* from block/genhd.c printk_all_partitions */ -+ struct class_dev_iter iter; -+ struct device *dev; -+ -+ /* from drivers/md/md.c */ -+ struct page *sb_page; -+ -+ if (!(sb_page = alloc_page(GFP_KERNEL))) { -+ printk(KERN_ERR "VFS: no memory for bio page\n"); -+ goto nomemforbio; -+ } -+ -+// printk(KERN_ERR "D: root is: " -+// "%02X%02X%02X%02X-%02X%02X-%02X%02X-%02X%02X-%02X%02X%02X%02X%02X%02X\n", -+// root_dev_uuid[0], root_dev_uuid[1], root_dev_uuid[2], root_dev_uuid[3], -+// root_dev_uuid[4], root_dev_uuid[5], root_dev_uuid[6], root_dev_uuid[7], -+// root_dev_uuid[8], root_dev_uuid[9], root_dev_uuid[10], root_dev_uuid[11], -+// root_dev_uuid[12], root_dev_uuid[13], root_dev_uuid[14], root_dev_uuid[15]); -+ /* from block/genhd.c printk_all_partitions */ -+// printk(KERN_ERR "D: begin iter\n"); -+ class_dev_iter_init(&iter, &block_class, NULL, &disk_type); -+ while (root_dev_type && (dev = class_dev_iter_next(&iter))) { -+// char bff[22]; -+ struct gendisk *disk = dev_to_disk(dev); -+ struct disk_part_iter piter; -+ struct hd_struct *part; -+ if (get_capacity(disk) == 0 || -+ (disk->flags & GENHD_FL_SUPPRESS_PARTITION_INFO)) { -+// printk(KERN_ERR "D: ignoring\n"); -+ continue; -+ } -+ blocksize = queue_logical_block_size(disk->queue); -+// printk(KERN_ERR "D: gendisk, blocksize %d " -+// "name '%s' devt %08X %s #part %d\n", blocksize, -+// disk->disk_name, dev->devt, -+// format_dev_t(bff, dev->devt), -+// disk_max_parts(disk)); -+ disk_part_iter_init(&piter, disk, DISK_PITER_INCL_PART0); -+ while (root_dev_type && (part = disk_part_iter_next(&piter))) { -+ /* avoid empty or too small partitions */ -+// printk(KERN_ERR "D: part #%d start %llu " -+// "nr %llu\n", part->partno, -+// (__u64)part->start_sect, -+// (__u64)part->nr_sects); -+ if (part->nr_sects < 8) -+ continue; -+ if (check_dev(disk, MKDEV(MAJOR(dev->devt), -+ MINOR(dev->devt) + part->partno), -+ blocksize, sb_page)) { -+ ROOT_DEV = part_devt(part); -+// printk(KERN_ERR "D: got match!\n"); -+ // comment out below for debugging -+ root_dev_type = 0; -+ } -+ } -+ disk_part_iter_exit(&piter); -+ } -+// printk(KERN_ERR "D: end iter\n"); -+ class_dev_iter_exit(&iter); -+ put_page(sb_page); -+ } -+ nomemforbio: -+ if (root_dev_type == 1) -+ printk(KERN_ERR "VFS: Unable to find root by UUID %s.\n", -+ saved_root_name + 5); -+ else if (root_dev_type == 3) -+ /* execute deferred panic from parse_uuid */ -+ panic("Badly formatted UUID %s was supplied as kernel " -+ "parameter root", saved_root_name + 5); -+#endif /* CONFIG_EXT2_FS for UUID support */ -+ - #ifdef CONFIG_ROOT_NFS - if (MAJOR(ROOT_DEV) == UNNAMED_MAJOR) { - if (mount_nfs_root()) diff --git a/target/linux/patches/2.6.37/vga-cons-default-off.patch b/target/linux/patches/2.6.37/vga-cons-default-off.patch deleted file mode 100644 index 178aeeeb9..000000000 --- a/target/linux/patches/2.6.37/vga-cons-default-off.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff -Nur linux-2.6.37.orig//drivers/video/console/Kconfig linux-2.6.37/drivers/video/console/Kconfig ---- linux-2.6.37.orig//drivers/video/console/Kconfig 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/video/console/Kconfig 2011-04-12 16:29:34.000000000 +0200 -@@ -7,7 +7,7 @@ - config VGA_CONSOLE - bool "VGA text console" if EMBEDDED || !X86 - depends on !4xx && !8xx && !SPARC && !M68K && !PARISC && !FRV && !SUPERH && !BLACKFIN && !AVR32 && !MN10300 && (!ARM || ARCH_FOOTBRIDGE || ARCH_INTEGRATOR || ARCH_NETWINDER) -- default y -+ default n - help - Saying Y here will allow you to use Linux in text mode through a - display that complies with the generic VGA standard. Virtually diff --git a/target/linux/patches/2.6.37/yaffs2.patch b/target/linux/patches/2.6.37/yaffs2.patch deleted file mode 100644 index 4a52d3f10..000000000 --- a/target/linux/patches/2.6.37/yaffs2.patch +++ /dev/null @@ -1,16912 +0,0 @@ -diff -Nur linux-2.6.36.orig/fs/Kconfig linux-2.6.36/fs/Kconfig ---- linux-2.6.36.orig/fs/Kconfig 2011-01-10 19:28:45.000000000 +0100 -+++ linux-2.6.36/fs/Kconfig 2011-01-10 19:29:29.000000000 +0100 -@@ -174,6 +174,7 @@ - source "fs/befs/Kconfig" - source "fs/bfs/Kconfig" - source "fs/efs/Kconfig" -+source "fs/yaffs2/Kconfig" - source "fs/jffs2/Kconfig" - # UBIFS File system configuration - source "fs/ubifs/Kconfig" -diff -Nur linux-2.6.36.orig/fs/Makefile linux-2.6.36/fs/Makefile ---- linux-2.6.36.orig/fs/Makefile 2011-01-10 19:28:45.000000000 +0100 -+++ linux-2.6.36/fs/Makefile 2011-01-10 19:30:04.000000000 +0100 -@@ -124,6 +124,7 @@ - obj-$(CONFIG_OCFS2_FS) += ocfs2/ - obj-$(CONFIG_BTRFS_FS) += btrfs/ - obj-$(CONFIG_GFS2_FS) += gfs2/ -+obj-$(CONFIG_YAFFS_FS) += yaffs2/ - obj-$(CONFIG_EXOFS_FS) += exofs/ - obj-$(CONFIG_CEPH_FS) += ceph/ - obj-$(CONFIG_AUFS_FS) += aufs/ -diff -Nur linux-2.6.36.orig/fs/yaffs2/Kconfig linux-2.6.36/fs/yaffs2/Kconfig ---- linux-2.6.36.orig/fs/yaffs2/Kconfig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/Kconfig 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,161 @@ -+# -+# YAFFS file system configurations -+# -+ -+config YAFFS_FS -+ tristate "YAFFS2 file system support" -+ default n -+ depends on MTD_BLOCK -+ select YAFFS_YAFFS1 -+ select YAFFS_YAFFS2 -+ help -+ YAFFS2, or Yet Another Flash Filing System, is a filing system -+ optimised for NAND Flash chips. -+ -+ To compile the YAFFS2 file system support as a module, choose M -+ here: the module will be called yaffs2. -+ -+ If unsure, say N. -+ -+ Further information on YAFFS2 is available at -+ . -+ -+config YAFFS_YAFFS1 -+ bool "512 byte / page devices" -+ depends on YAFFS_FS -+ default y -+ help -+ Enable YAFFS1 support -- yaffs for 512 byte / page devices -+ -+ Not needed for 2K-page devices. -+ -+ If unsure, say Y. -+ -+config YAFFS_9BYTE_TAGS -+ bool "Use older-style on-NAND data format with pageStatus byte" -+ depends on YAFFS_YAFFS1 -+ default n -+ help -+ -+ Older-style on-NAND data format has a "pageStatus" byte to record -+ chunk/page state. This byte is zero when the page is discarded. -+ Choose this option if you have existing on-NAND data using this -+ format that you need to continue to support. New data written -+ also uses the older-style format. Note: Use of this option -+ generally requires that MTD's oob layout be adjusted to use the -+ older-style format. See notes on tags formats and MTD versions -+ in yaffs_mtdif1.c. -+ -+ If unsure, say N. -+ -+config YAFFS_DOES_ECC -+ bool "Lets Yaffs do its own ECC" -+ depends on YAFFS_FS && YAFFS_YAFFS1 && !YAFFS_9BYTE_TAGS -+ default n -+ help -+ This enables Yaffs to use its own ECC functions instead of using -+ the ones from the generic MTD-NAND driver. -+ -+ If unsure, say N. -+ -+config YAFFS_ECC_WRONG_ORDER -+ bool "Use the same ecc byte order as Steven Hill's nand_ecc.c" -+ depends on YAFFS_FS && YAFFS_DOES_ECC && !YAFFS_9BYTE_TAGS -+ default n -+ help -+ This makes yaffs_ecc.c use the same ecc byte order as Steven -+ Hill's nand_ecc.c. If not set, then you get the same ecc byte -+ order as SmartMedia. -+ -+ If unsure, say N. -+ -+config YAFFS_YAFFS2 -+ bool "2048 byte (or larger) / page devices" -+ depends on YAFFS_FS -+ default y -+ help -+ Enable YAFFS2 support -- yaffs for >= 2K bytes per page devices -+ -+ If unsure, say Y. -+ -+config YAFFS_AUTO_YAFFS2 -+ bool "Autoselect yaffs2 format" -+ depends on YAFFS_YAFFS2 -+ default y -+ help -+ Without this, you need to explicitely use yaffs2 as the file -+ system type. With this, you can say "yaffs" and yaffs or yaffs2 -+ will be used depending on the device page size (yaffs on -+ 512-byte page devices, yaffs2 on 2K page devices). -+ -+ If unsure, say Y. -+ -+config YAFFS_DISABLE_TAGS_ECC -+ bool "Disable YAFFS from doing ECC on tags by default" -+ depends on YAFFS_FS && YAFFS_YAFFS2 -+ default n -+ help -+ This defaults Yaffs to using its own ECC calculations on tags instead of -+ just relying on the MTD. -+ This behavior can also be overridden with tags_ecc_on and -+ tags_ecc_off mount options. -+ -+ If unsure, say N. -+ -+config YAFFS_ALWAYS_CHECK_CHUNK_ERASED -+ bool "Force chunk erase check" -+ depends on YAFFS_FS -+ default n -+ help -+ Normally YAFFS only checks chunks before writing until an erased -+ chunk is found. This helps to detect any partially written -+ chunks that might have happened due to power loss. -+ -+ Enabling this forces on the test that chunks are erased in flash -+ before writing to them. This takes more time but is potentially -+ a bit more secure. -+ -+ Suggest setting Y during development and ironing out driver -+ issues etc. Suggest setting to N if you want faster writing. -+ -+ If unsure, say Y. -+ -+config YAFFS_EMPTY_LOST_AND_FOUND -+ bool "Empty lost and found on boot" -+ depends on YAFFS_FS -+ default n -+ help -+ If this is enabled then the contents of lost and found is -+ automatically dumped at mount. -+ -+ If unsure, say N. -+ -+config YAFFS_DISABLE_BLOCK_REFRESHING -+ bool "Disable yaffs2 block refreshing" -+ depends on YAFFS_FS -+ default n -+ help -+ If this is set, then block refreshing is disabled. -+ Block refreshing infrequently refreshes the oldest block in -+ a yaffs2 file system. This mechanism helps to refresh flash to -+ mitigate against data loss. This is particularly useful for MLC. -+ -+ If unsure, say N. -+ -+config YAFFS_DISABLE_BACKGROUND -+ bool "Disable yaffs2 background processing" -+ depends on YAFFS_FS -+ default n -+ help -+ If this is set, then background processing is disabled. -+ Background processing makes many foreground activities faster. -+ -+ If unsure, say N. -+ -+config YAFFS_XATTR -+ bool "Enable yaffs2 xattr support" -+ depends on YAFFS_FS -+ default y -+ help -+ If this is set then yaffs2 will provide xattr support. -+ If unsure, say Y. -diff -Nur linux-2.6.36.orig/fs/yaffs2/Makefile linux-2.6.36/fs/yaffs2/Makefile ---- linux-2.6.36.orig/fs/yaffs2/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/Makefile 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,17 @@ -+# -+# Makefile for the linux YAFFS filesystem routines. -+# -+ -+obj-$(CONFIG_YAFFS_FS) += yaffs.o -+ -+yaffs-y := yaffs_ecc.o yaffs_vfs.o yaffs_guts.o yaffs_checkptrw.o -+yaffs-y += yaffs_packedtags1.o yaffs_packedtags2.o yaffs_nand.o -+yaffs-y += yaffs_tagscompat.o yaffs_tagsvalidity.o -+yaffs-y += yaffs_mtdif.o yaffs_mtdif1.o yaffs_mtdif2.o -+yaffs-y += yaffs_nameval.o yaffs_attribs.o -+yaffs-y += yaffs_allocator.o -+yaffs-y += yaffs_yaffs1.o -+yaffs-y += yaffs_yaffs2.o -+yaffs-y += yaffs_bitmap.o -+yaffs-y += yaffs_verify.o -+ -diff -Nur linux-2.6.36.orig/fs/yaffs2/moduleconfig.h linux-2.6.36/fs/yaffs2/moduleconfig.h ---- linux-2.6.36.orig/fs/yaffs2/moduleconfig.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/moduleconfig.h 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,81 @@ -+/* -+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Martin Fouts -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU Lesser General Public License version 2.1 as -+ * published by the Free Software Foundation. -+ * -+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. -+ */ -+ -+#ifndef __YAFFS_CONFIG_H__ -+#define __YAFFS_CONFIG_H__ -+ -+#ifdef YAFFS_OUT_OF_TREE -+ -+/* DO NOT UNSET THESE THREE. YAFFS2 will not compile if you do. */ -+#define CONFIG_YAFFS_FS -+#define CONFIG_YAFFS_YAFFS1 -+#define CONFIG_YAFFS_YAFFS2 -+ -+/* These options are independent of each other. Select those that matter. */ -+ -+/* Default: Not selected */ -+/* Meaning: Yaffs does its own ECC, rather than using MTD ECC */ -+/* #define CONFIG_YAFFS_DOES_ECC */ -+ -+/* Default: Selected */ -+/* Meaning: Yaffs does its own ECC on tags for packed tags rather than use mtd */ -+#define CONFIG_YAFFS_DOES_TAGS_ECC -+ -+/* Default: Not selected */ -+/* Meaning: ECC byte order is 'wrong'. Only meaningful if */ -+/* CONFIG_YAFFS_DOES_ECC is set */ -+/* #define CONFIG_YAFFS_ECC_WRONG_ORDER */ -+ -+/* Default: Not selected */ -+/* Meaning: Always test whether chunks are erased before writing to them. -+ Use during mtd debugging and init. */ -+/* #define CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED */ -+ -+/* Default: Not Selected */ -+/* Meaning: At mount automatically empty all files from lost and found. */ -+/* This is done to fix an old problem where rmdir was not checking for an */ -+/* empty directory. This can also be achieved with a mount option. */ -+#define CONFIG_YAFFS_EMPTY_LOST_AND_FOUND -+ -+/* Default: Unselected */ -+/* Meaning: Select to disable block refreshing. */ -+/* Block Refreshing periodically rewrites the oldest block. */ -+/* #define CONFIG_DISABLE_BLOCK_REFRESHING */ -+ -+/* Default: Unselected */ -+/* Meaning: Select to disable background processing */ -+/* #define CONFIG_DISABLE_BACKGROUND */ -+ -+/* Default: Selected */ -+/* Meaning: Enable XATTR support */ -+#define CONFIG_YAFFS_XATTR -+ -+/* -+Older-style on-NAND data format has a "page_status" byte to record -+chunk/page state. This byte is zeroed when the page is discarded. -+Choose this option if you have existing on-NAND data in this format -+that you need to continue to support. New data written also uses the -+older-style format. -+Note: Use of this option generally requires that MTD's oob layout be -+adjusted to use the older-style format. See notes on tags formats and -+MTD versions in yaffs_mtdif1.c. -+*/ -+/* Default: Not selected */ -+/* Meaning: Use older-style on-NAND data format with page_status byte */ -+/* #define CONFIG_YAFFS_9BYTE_TAGS */ -+ -+#endif /* YAFFS_OUT_OF_TREE */ -+ -+#endif /* __YAFFS_CONFIG_H__ */ -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_allocator.c linux-2.6.36/fs/yaffs2/yaffs_allocator.c ---- linux-2.6.36.orig/fs/yaffs2/yaffs_allocator.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_allocator.c 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,397 @@ -+/* -+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include "yaffs_allocator.h" -+#include "yaffs_guts.h" -+#include "yaffs_trace.h" -+#include "yportenv.h" -+ -+#ifdef CONFIG_YAFFS_YMALLOC_ALLOCATOR -+ -+void yaffs_deinit_raw_tnodes_and_objs(struct yaffs_dev *dev) -+{ -+ dev = dev; -+} -+ -+void yaffs_init_raw_tnodes_and_objs(struct yaffs_dev *dev) -+{ -+ dev = dev; -+} -+ -+struct yaffs_tnode *yaffs_alloc_raw_tnode(struct yaffs_dev *dev) -+{ -+ return (struct yaffs_tnode *)YMALLOC(dev->tnode_size); -+} -+ -+void yaffs_free_raw_tnode(struct yaffs_dev *dev, struct yaffs_tnode *tn) -+{ -+ dev = dev; -+ YFREE(tn); -+} -+ -+void yaffs_init_raw_objs(struct yaffs_dev *dev) -+{ -+ dev = dev; -+} -+ -+void yaffs_deinit_raw_objs(struct yaffs_dev *dev) -+{ -+ dev = dev; -+} -+ -+struct yaffs_obj *yaffs_alloc_raw_obj(struct yaffs_dev *dev) -+{ -+ dev = dev; -+ return (struct yaffs_obj *)YMALLOC(sizeof(struct yaffs_obj)); -+} -+ -+void yaffs_free_raw_obj(struct yaffs_dev *dev, struct yaffs_obj *obj) -+{ -+ -+ dev = dev; -+ YFREE(obj); -+} -+ -+#else -+ -+struct yaffs_tnode_list { -+ struct yaffs_tnode_list *next; -+ struct yaffs_tnode *tnodes; -+}; -+ -+struct yaffs_obj_list { -+ struct yaffs_obj_list *next; -+ struct yaffs_obj *objects; -+}; -+ -+struct yaffs_allocator { -+ int n_tnodes_created; -+ struct yaffs_tnode *free_tnodes; -+ int n_free_tnodes; -+ struct yaffs_tnode_list *alloc_tnode_list; -+ -+ int n_obj_created; -+ struct yaffs_obj *free_objs; -+ int n_free_objects; -+ -+ struct yaffs_obj_list *allocated_obj_list; -+}; -+ -+static void yaffs_deinit_raw_tnodes(struct yaffs_dev *dev) -+{ -+ -+ struct yaffs_allocator *allocator = -+ (struct yaffs_allocator *)dev->allocator; -+ -+ struct yaffs_tnode_list *tmp; -+ -+ if (!allocator) { -+ YBUG(); -+ return; -+ } -+ -+ while (allocator->alloc_tnode_list) { -+ tmp = allocator->alloc_tnode_list->next; -+ -+ YFREE(allocator->alloc_tnode_list->tnodes); -+ YFREE(allocator->alloc_tnode_list); -+ allocator->alloc_tnode_list = tmp; -+ -+ } -+ -+ allocator->free_tnodes = NULL; -+ allocator->n_free_tnodes = 0; -+ allocator->n_tnodes_created = 0; -+} -+ -+static void yaffs_init_raw_tnodes(struct yaffs_dev *dev) -+{ -+ struct yaffs_allocator *allocator = dev->allocator; -+ -+ if (allocator) { -+ allocator->alloc_tnode_list = NULL; -+ allocator->free_tnodes = NULL; -+ allocator->n_free_tnodes = 0; -+ allocator->n_tnodes_created = 0; -+ } else { -+ YBUG(); -+ } -+} -+ -+static int yaffs_create_tnodes(struct yaffs_dev *dev, int n_tnodes) -+{ -+ struct yaffs_allocator *allocator = -+ (struct yaffs_allocator *)dev->allocator; -+ int i; -+ struct yaffs_tnode *new_tnodes; -+ u8 *mem; -+ struct yaffs_tnode *curr; -+ struct yaffs_tnode *next; -+ struct yaffs_tnode_list *tnl; -+ -+ if (!allocator) { -+ YBUG(); -+ return YAFFS_FAIL; -+ } -+ -+ if (n_tnodes < 1) -+ return YAFFS_OK; -+ -+ /* make these things */ -+ -+ new_tnodes = YMALLOC(n_tnodes * dev->tnode_size); -+ mem = (u8 *) new_tnodes; -+ -+ if (!new_tnodes) { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR("yaffs: Could not allocate Tnodes" TENDSTR))); -+ return YAFFS_FAIL; -+ } -+ -+ /* New hookup for wide tnodes */ -+ for (i = 0; i < n_tnodes - 1; i++) { -+ curr = (struct yaffs_tnode *)&mem[i * dev->tnode_size]; -+ next = (struct yaffs_tnode *)&mem[(i + 1) * dev->tnode_size]; -+ curr->internal[0] = next; -+ } -+ -+ curr = (struct yaffs_tnode *)&mem[(n_tnodes - 1) * dev->tnode_size]; -+ curr->internal[0] = allocator->free_tnodes; -+ allocator->free_tnodes = (struct yaffs_tnode *)mem; -+ -+ allocator->n_free_tnodes += n_tnodes; -+ allocator->n_tnodes_created += n_tnodes; -+ -+ /* Now add this bunch of tnodes to a list for freeing up. -+ * NB If we can't add this to the management list it isn't fatal -+ * but it just means we can't free this bunch of tnodes later. -+ */ -+ -+ tnl = YMALLOC(sizeof(struct yaffs_tnode_list)); -+ if (!tnl) { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR -+ ("yaffs: Could not add tnodes to management list" TENDSTR))); -+ return YAFFS_FAIL; -+ } else { -+ tnl->tnodes = new_tnodes; -+ tnl->next = allocator->alloc_tnode_list; -+ allocator->alloc_tnode_list = tnl; -+ } -+ -+ T(YAFFS_TRACE_ALLOCATE, (TSTR("yaffs: Tnodes added" TENDSTR))); -+ -+ return YAFFS_OK; -+} -+ -+struct yaffs_tnode *yaffs_alloc_raw_tnode(struct yaffs_dev *dev) -+{ -+ struct yaffs_allocator *allocator = -+ (struct yaffs_allocator *)dev->allocator; -+ struct yaffs_tnode *tn = NULL; -+ -+ if (!allocator) { -+ YBUG(); -+ return NULL; -+ } -+ -+ /* If there are none left make more */ -+ if (!allocator->free_tnodes) -+ yaffs_create_tnodes(dev, YAFFS_ALLOCATION_NTNODES); -+ -+ if (allocator->free_tnodes) { -+ tn = allocator->free_tnodes; -+ allocator->free_tnodes = allocator->free_tnodes->internal[0]; -+ allocator->n_free_tnodes--; -+ } -+ -+ return tn; -+} -+ -+/* FreeTnode frees up a tnode and puts it back on the free list */ -+void yaffs_free_raw_tnode(struct yaffs_dev *dev, struct yaffs_tnode *tn) -+{ -+ struct yaffs_allocator *allocator = dev->allocator; -+ -+ if (!allocator) { -+ YBUG(); -+ return; -+ } -+ -+ if (tn) { -+ tn->internal[0] = allocator->free_tnodes; -+ allocator->free_tnodes = tn; -+ allocator->n_free_tnodes++; -+ } -+ dev->checkpoint_blocks_required = 0; /* force recalculation */ -+} -+ -+static void yaffs_init_raw_objs(struct yaffs_dev *dev) -+{ -+ struct yaffs_allocator *allocator = dev->allocator; -+ -+ if (allocator) { -+ allocator->allocated_obj_list = NULL; -+ allocator->free_objs = NULL; -+ allocator->n_free_objects = 0; -+ } else { -+ YBUG(); -+ } -+} -+ -+static void yaffs_deinit_raw_objs(struct yaffs_dev *dev) -+{ -+ struct yaffs_allocator *allocator = dev->allocator; -+ struct yaffs_obj_list *tmp; -+ -+ if (!allocator) { -+ YBUG(); -+ return; -+ } -+ -+ while (allocator->allocated_obj_list) { -+ tmp = allocator->allocated_obj_list->next; -+ YFREE(allocator->allocated_obj_list->objects); -+ YFREE(allocator->allocated_obj_list); -+ -+ allocator->allocated_obj_list = tmp; -+ } -+ -+ allocator->free_objs = NULL; -+ allocator->n_free_objects = 0; -+ allocator->n_obj_created = 0; -+} -+ -+static int yaffs_create_free_objs(struct yaffs_dev *dev, int n_obj) -+{ -+ struct yaffs_allocator *allocator = dev->allocator; -+ -+ int i; -+ struct yaffs_obj *new_objs; -+ struct yaffs_obj_list *list; -+ -+ if (!allocator) { -+ YBUG(); -+ return YAFFS_FAIL; -+ } -+ -+ if (n_obj < 1) -+ return YAFFS_OK; -+ -+ /* make these things */ -+ new_objs = YMALLOC(n_obj * sizeof(struct yaffs_obj)); -+ list = YMALLOC(sizeof(struct yaffs_obj_list)); -+ -+ if (!new_objs || !list) { -+ if (new_objs) { -+ YFREE(new_objs); -+ new_objs = NULL; -+ } -+ if (list) { -+ YFREE(list); -+ list = NULL; -+ } -+ T(YAFFS_TRACE_ALLOCATE, -+ (TSTR("yaffs: Could not allocate more objects" TENDSTR))); -+ return YAFFS_FAIL; -+ } -+ -+ /* Hook them into the free list */ -+ for (i = 0; i < n_obj - 1; i++) { -+ new_objs[i].siblings.next = -+ (struct list_head *)(&new_objs[i + 1]); -+ } -+ -+ new_objs[n_obj - 1].siblings.next = (void *)allocator->free_objs; -+ allocator->free_objs = new_objs; -+ allocator->n_free_objects += n_obj; -+ allocator->n_obj_created += n_obj; -+ -+ /* Now add this bunch of Objects to a list for freeing up. */ -+ -+ list->objects = new_objs; -+ list->next = allocator->allocated_obj_list; -+ allocator->allocated_obj_list = list; -+ -+ return YAFFS_OK; -+} -+ -+struct yaffs_obj *yaffs_alloc_raw_obj(struct yaffs_dev *dev) -+{ -+ struct yaffs_obj *obj = NULL; -+ struct yaffs_allocator *allocator = dev->allocator; -+ -+ if (!allocator) { -+ YBUG(); -+ return obj; -+ } -+ -+ /* If there are none left make more */ -+ if (!allocator->free_objs) -+ yaffs_create_free_objs(dev, YAFFS_ALLOCATION_NOBJECTS); -+ -+ if (allocator->free_objs) { -+ obj = allocator->free_objs; -+ allocator->free_objs = -+ (struct yaffs_obj *)(allocator->free_objs->siblings.next); -+ allocator->n_free_objects--; -+ } -+ -+ return obj; -+} -+ -+void yaffs_free_raw_obj(struct yaffs_dev *dev, struct yaffs_obj *obj) -+{ -+ -+ struct yaffs_allocator *allocator = dev->allocator; -+ -+ if (!allocator) -+ YBUG(); -+ else { -+ /* Link into the free list. */ -+ obj->siblings.next = (struct list_head *)(allocator->free_objs); -+ allocator->free_objs = obj; -+ allocator->n_free_objects++; -+ } -+} -+ -+void yaffs_deinit_raw_tnodes_and_objs(struct yaffs_dev *dev) -+{ -+ if (dev->allocator) { -+ yaffs_deinit_raw_tnodes(dev); -+ yaffs_deinit_raw_objs(dev); -+ -+ YFREE(dev->allocator); -+ dev->allocator = NULL; -+ } else { -+ YBUG(); -+ } -+} -+ -+void yaffs_init_raw_tnodes_and_objs(struct yaffs_dev *dev) -+{ -+ struct yaffs_allocator *allocator; -+ -+ if (!dev->allocator) { -+ allocator = YMALLOC(sizeof(struct yaffs_allocator)); -+ if (allocator) { -+ dev->allocator = allocator; -+ yaffs_init_raw_tnodes(dev); -+ yaffs_init_raw_objs(dev); -+ } -+ } else { -+ YBUG(); -+ } -+} -+ -+#endif -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_allocator.h linux-2.6.36/fs/yaffs2/yaffs_allocator.h ---- linux-2.6.36.orig/fs/yaffs2/yaffs_allocator.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_allocator.h 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,30 @@ -+/* -+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU Lesser General Public License version 2.1 as -+ * published by the Free Software Foundation. -+ * -+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. -+ */ -+ -+#ifndef __YAFFS_ALLOCATOR_H__ -+#define __YAFFS_ALLOCATOR_H__ -+ -+#include "yaffs_guts.h" -+ -+void yaffs_init_raw_tnodes_and_objs(struct yaffs_dev *dev); -+void yaffs_deinit_raw_tnodes_and_objs(struct yaffs_dev *dev); -+ -+struct yaffs_tnode *yaffs_alloc_raw_tnode(struct yaffs_dev *dev); -+void yaffs_free_raw_tnode(struct yaffs_dev *dev, struct yaffs_tnode *tn); -+ -+struct yaffs_obj *yaffs_alloc_raw_obj(struct yaffs_dev *dev); -+void yaffs_free_raw_obj(struct yaffs_dev *dev, struct yaffs_obj *obj); -+ -+#endif -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_attribs.c linux-2.6.36/fs/yaffs2/yaffs_attribs.c ---- linux-2.6.36.orig/fs/yaffs2/yaffs_attribs.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_attribs.c 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,124 @@ -+/* -+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include "yaffs_guts.h" -+#include "yaffs_attribs.h" -+ -+void yaffs_load_attribs(struct yaffs_obj *obj, struct yaffs_obj_hdr *oh) -+{ -+ obj->yst_uid = oh->yst_uid; -+ obj->yst_gid = oh->yst_gid; -+ obj->yst_atime = oh->yst_atime; -+ obj->yst_mtime = oh->yst_mtime; -+ obj->yst_ctime = oh->yst_ctime; -+ obj->yst_rdev = oh->yst_rdev; -+} -+ -+void yaffs_load_attribs_oh(struct yaffs_obj_hdr *oh, struct yaffs_obj *obj) -+{ -+ oh->yst_uid = obj->yst_uid; -+ oh->yst_gid = obj->yst_gid; -+ oh->yst_atime = obj->yst_atime; -+ oh->yst_mtime = obj->yst_mtime; -+ oh->yst_ctime = obj->yst_ctime; -+ oh->yst_rdev = obj->yst_rdev; -+ -+} -+ -+void yaffs_load_current_time(struct yaffs_obj *obj, int do_a, int do_c) -+{ -+ obj->yst_mtime = Y_CURRENT_TIME; -+ if (do_a) -+ obj->yst_atime = obj->yst_atime; -+ if (do_c) -+ obj->yst_ctime = obj->yst_atime; -+} -+ -+void yaffs_attribs_init(struct yaffs_obj *obj, u32 gid, u32 uid, u32 rdev) -+{ -+ yaffs_load_current_time(obj, 1, 1); -+ obj->yst_rdev = rdev; -+ obj->yst_uid = uid; -+ obj->yst_gid = gid; -+} -+ -+loff_t yaffs_get_file_size(struct yaffs_obj *obj) -+{ -+ YCHAR *alias = NULL; -+ obj = yaffs_get_equivalent_obj(obj); -+ -+ switch (obj->variant_type) { -+ case YAFFS_OBJECT_TYPE_FILE: -+ return obj->variant.file_variant.file_size; -+ case YAFFS_OBJECT_TYPE_SYMLINK: -+ alias = obj->variant.symlink_variant.alias; -+ if (!alias) -+ return 0; -+ return yaffs_strnlen(alias, YAFFS_MAX_ALIAS_LENGTH); -+ default: -+ return 0; -+ } -+} -+ -+int yaffs_set_attribs(struct yaffs_obj *obj, struct iattr *attr) -+{ -+ unsigned int valid = attr->ia_valid; -+ -+ if (valid & ATTR_MODE) -+ obj->yst_mode = attr->ia_mode; -+ if (valid & ATTR_UID) -+ obj->yst_uid = attr->ia_uid; -+ if (valid & ATTR_GID) -+ obj->yst_gid = attr->ia_gid; -+ -+ if (valid & ATTR_ATIME) -+ obj->yst_atime = Y_TIME_CONVERT(attr->ia_atime); -+ if (valid & ATTR_CTIME) -+ obj->yst_ctime = Y_TIME_CONVERT(attr->ia_ctime); -+ if (valid & ATTR_MTIME) -+ obj->yst_mtime = Y_TIME_CONVERT(attr->ia_mtime); -+ -+ if (valid & ATTR_SIZE) -+ yaffs_resize_file(obj, attr->ia_size); -+ -+ yaffs_update_oh(obj, NULL, 1, 0, 0, NULL); -+ -+ return YAFFS_OK; -+ -+} -+ -+int yaffs_get_attribs(struct yaffs_obj *obj, struct iattr *attr) -+{ -+ unsigned int valid = 0; -+ -+ attr->ia_mode = obj->yst_mode; -+ valid |= ATTR_MODE; -+ attr->ia_uid = obj->yst_uid; -+ valid |= ATTR_UID; -+ attr->ia_gid = obj->yst_gid; -+ valid |= ATTR_GID; -+ -+ Y_TIME_CONVERT(attr->ia_atime) = obj->yst_atime; -+ valid |= ATTR_ATIME; -+ Y_TIME_CONVERT(attr->ia_ctime) = obj->yst_ctime; -+ valid |= ATTR_CTIME; -+ Y_TIME_CONVERT(attr->ia_mtime) = obj->yst_mtime; -+ valid |= ATTR_MTIME; -+ -+ attr->ia_size = yaffs_get_file_size(obj); -+ valid |= ATTR_SIZE; -+ -+ attr->ia_valid = valid; -+ -+ return YAFFS_OK; -+} -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_attribs.h linux-2.6.36/fs/yaffs2/yaffs_attribs.h ---- linux-2.6.36.orig/fs/yaffs2/yaffs_attribs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_attribs.h 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,28 @@ -+/* -+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU Lesser General Public License version 2.1 as -+ * published by the Free Software Foundation. -+ * -+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. -+ */ -+ -+#ifndef __YAFFS_ATTRIBS_H__ -+#define __YAFFS_ATTRIBS_H__ -+ -+#include "yaffs_guts.h" -+ -+void yaffs_load_attribs(struct yaffs_obj *obj, struct yaffs_obj_hdr *oh); -+void yaffs_load_attribs_oh(struct yaffs_obj_hdr *oh, struct yaffs_obj *obj); -+void yaffs_attribs_init(struct yaffs_obj *obj, u32 gid, u32 uid, u32 rdev); -+void yaffs_load_current_time(struct yaffs_obj *obj, int do_a, int do_c); -+int yaffs_set_attribs(struct yaffs_obj *obj, struct iattr *attr); -+int yaffs_get_attribs(struct yaffs_obj *obj, struct iattr *attr); -+ -+#endif -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_bitmap.c linux-2.6.36/fs/yaffs2/yaffs_bitmap.c ---- linux-2.6.36.orig/fs/yaffs2/yaffs_bitmap.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_bitmap.c 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,104 @@ -+/* -+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include "yaffs_bitmap.h" -+#include "yaffs_trace.h" -+/* -+ * Chunk bitmap manipulations -+ */ -+ -+static Y_INLINE u8 *yaffs_block_bits(struct yaffs_dev *dev, int blk) -+{ -+ if (blk < dev->internal_start_block || blk > dev->internal_end_block) { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR("**>> yaffs: BlockBits block %d is not valid" TENDSTR), -+ blk)); -+ YBUG(); -+ } -+ return dev->chunk_bits + -+ (dev->chunk_bit_stride * (blk - dev->internal_start_block)); -+} -+ -+void yaffs_verify_chunk_bit_id(struct yaffs_dev *dev, int blk, int chunk) -+{ -+ if (blk < dev->internal_start_block || blk > dev->internal_end_block || -+ chunk < 0 || chunk >= dev->param.chunks_per_block) { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR("**>> yaffs: Chunk Id (%d:%d) invalid" TENDSTR), -+ blk, chunk)); -+ YBUG(); -+ } -+} -+ -+void yaffs_clear_chunk_bits(struct yaffs_dev *dev, int blk) -+{ -+ u8 *blk_bits = yaffs_block_bits(dev, blk); -+ -+ memset(blk_bits, 0, dev->chunk_bit_stride); -+} -+ -+void yaffs_clear_chunk_bit(struct yaffs_dev *dev, int blk, int chunk) -+{ -+ u8 *blk_bits = yaffs_block_bits(dev, blk); -+ -+ yaffs_verify_chunk_bit_id(dev, blk, chunk); -+ -+ blk_bits[chunk / 8] &= ~(1 << (chunk & 7)); -+} -+ -+void yaffs_set_chunk_bit(struct yaffs_dev *dev, int blk, int chunk) -+{ -+ u8 *blk_bits = yaffs_block_bits(dev, blk); -+ -+ yaffs_verify_chunk_bit_id(dev, blk, chunk); -+ -+ blk_bits[chunk / 8] |= (1 << (chunk & 7)); -+} -+ -+int yaffs_check_chunk_bit(struct yaffs_dev *dev, int blk, int chunk) -+{ -+ u8 *blk_bits = yaffs_block_bits(dev, blk); -+ yaffs_verify_chunk_bit_id(dev, blk, chunk); -+ -+ return (blk_bits[chunk / 8] & (1 << (chunk & 7))) ? 1 : 0; -+} -+ -+int yaffs_still_some_chunks(struct yaffs_dev *dev, int blk) -+{ -+ u8 *blk_bits = yaffs_block_bits(dev, blk); -+ int i; -+ for (i = 0; i < dev->chunk_bit_stride; i++) { -+ if (*blk_bits) -+ return 1; -+ blk_bits++; -+ } -+ return 0; -+} -+ -+int yaffs_count_chunk_bits(struct yaffs_dev *dev, int blk) -+{ -+ u8 *blk_bits = yaffs_block_bits(dev, blk); -+ int i; -+ int n = 0; -+ for (i = 0; i < dev->chunk_bit_stride; i++) { -+ u8 x = *blk_bits; -+ while (x) { -+ if (x & 1) -+ n++; -+ x >>= 1; -+ } -+ -+ blk_bits++; -+ } -+ return n; -+} -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_bitmap.h linux-2.6.36/fs/yaffs2/yaffs_bitmap.h ---- linux-2.6.36.orig/fs/yaffs2/yaffs_bitmap.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_bitmap.h 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,33 @@ -+/* -+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU Lesser General Public License version 2.1 as -+ * published by the Free Software Foundation. -+ * -+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. -+ */ -+ -+/* -+ * Chunk bitmap manipulations -+ */ -+ -+#ifndef __YAFFS_BITMAP_H__ -+#define __YAFFS_BITMAP_H__ -+ -+#include "yaffs_guts.h" -+ -+void yaffs_verify_chunk_bit_id(struct yaffs_dev *dev, int blk, int chunk); -+void yaffs_clear_chunk_bits(struct yaffs_dev *dev, int blk); -+void yaffs_clear_chunk_bit(struct yaffs_dev *dev, int blk, int chunk); -+void yaffs_set_chunk_bit(struct yaffs_dev *dev, int blk, int chunk); -+int yaffs_check_chunk_bit(struct yaffs_dev *dev, int blk, int chunk); -+int yaffs_still_some_chunks(struct yaffs_dev *dev, int blk); -+int yaffs_count_chunk_bits(struct yaffs_dev *dev, int blk); -+ -+#endif -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_checkptrw.c linux-2.6.36/fs/yaffs2/yaffs_checkptrw.c ---- linux-2.6.36.orig/fs/yaffs2/yaffs_checkptrw.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_checkptrw.c 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,420 @@ -+/* -+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include "yaffs_checkptrw.h" -+#include "yaffs_getblockinfo.h" -+ -+static int yaffs2_checkpt_space_ok(struct yaffs_dev *dev) -+{ -+ int blocks_avail = dev->n_erased_blocks - dev->param.n_reserved_blocks; -+ -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR("checkpt blocks available = %d" TENDSTR), blocks_avail)); -+ -+ return (blocks_avail <= 0) ? 0 : 1; -+} -+ -+static int yaffs_checkpt_erase(struct yaffs_dev *dev) -+{ -+ int i; -+ -+ if (!dev->param.erase_fn) -+ return 0; -+ T(YAFFS_TRACE_CHECKPOINT, (TSTR("checking blocks %d to %d" TENDSTR), -+ dev->internal_start_block, -+ dev->internal_end_block)); -+ -+ for (i = dev->internal_start_block; i <= dev->internal_end_block; i++) { -+ struct yaffs_block_info *bi = yaffs_get_block_info(dev, i); -+ if (bi->block_state == YAFFS_BLOCK_STATE_CHECKPOINT) { -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR("erasing checkpt block %d" TENDSTR), i)); -+ -+ dev->n_erasures++; -+ -+ if (dev->param. -+ erase_fn(dev, -+ i - dev->block_offset /* realign */ )) { -+ bi->block_state = YAFFS_BLOCK_STATE_EMPTY; -+ dev->n_erased_blocks++; -+ dev->n_free_chunks += -+ dev->param.chunks_per_block; -+ } else { -+ dev->param.bad_block_fn(dev, i); -+ bi->block_state = YAFFS_BLOCK_STATE_DEAD; -+ } -+ } -+ } -+ -+ dev->blocks_in_checkpt = 0; -+ -+ return 1; -+} -+ -+static void yaffs2_checkpt_find_erased_block(struct yaffs_dev *dev) -+{ -+ int i; -+ int blocks_avail = dev->n_erased_blocks - dev->param.n_reserved_blocks; -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR -+ ("allocating checkpt block: erased %d reserved %d avail %d next %d " -+ TENDSTR), dev->n_erased_blocks, dev->param.n_reserved_blocks, -+ blocks_avail, dev->checkpt_next_block)); -+ -+ if (dev->checkpt_next_block >= 0 && -+ dev->checkpt_next_block <= dev->internal_end_block && -+ blocks_avail > 0) { -+ -+ for (i = dev->checkpt_next_block; i <= dev->internal_end_block; -+ i++) { -+ struct yaffs_block_info *bi = -+ yaffs_get_block_info(dev, i); -+ if (bi->block_state == YAFFS_BLOCK_STATE_EMPTY) { -+ dev->checkpt_next_block = i + 1; -+ dev->checkpt_cur_block = i; -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR("allocating checkpt block %d" TENDSTR), -+ i)); -+ return; -+ } -+ } -+ } -+ T(YAFFS_TRACE_CHECKPOINT, (TSTR("out of checkpt blocks" TENDSTR))); -+ -+ dev->checkpt_next_block = -1; -+ dev->checkpt_cur_block = -1; -+} -+ -+static void yaffs2_checkpt_find_block(struct yaffs_dev *dev) -+{ -+ int i; -+ struct yaffs_ext_tags tags; -+ -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR("find next checkpt block: start: blocks %d next %d" TENDSTR), -+ dev->blocks_in_checkpt, dev->checkpt_next_block)); -+ -+ if (dev->blocks_in_checkpt < dev->checkpt_max_blocks) -+ for (i = dev->checkpt_next_block; i <= dev->internal_end_block; -+ i++) { -+ int chunk = i * dev->param.chunks_per_block; -+ int realigned_chunk = chunk - dev->chunk_offset; -+ -+ dev->param.read_chunk_tags_fn(dev, realigned_chunk, -+ NULL, &tags); -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR -+ ("find next checkpt block: search: block %d oid %d seq %d eccr %d" -+ TENDSTR), i, tags.obj_id, tags.seq_number, -+ tags.ecc_result)); -+ -+ if (tags.seq_number == YAFFS_SEQUENCE_CHECKPOINT_DATA) { -+ /* Right kind of block */ -+ dev->checkpt_next_block = tags.obj_id; -+ dev->checkpt_cur_block = i; -+ dev->checkpt_block_list[dev-> -+ blocks_in_checkpt] = i; -+ dev->blocks_in_checkpt++; -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR("found checkpt block %d" TENDSTR), i)); -+ return; -+ } -+ } -+ -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR("found no more checkpt blocks" TENDSTR))); -+ -+ dev->checkpt_next_block = -1; -+ dev->checkpt_cur_block = -1; -+} -+ -+int yaffs2_checkpt_open(struct yaffs_dev *dev, int writing) -+{ -+ -+ dev->checkpt_open_write = writing; -+ -+ /* Got the functions we need? */ -+ if (!dev->param.write_chunk_tags_fn || -+ !dev->param.read_chunk_tags_fn || -+ !dev->param.erase_fn || !dev->param.bad_block_fn) -+ return 0; -+ -+ if (writing && !yaffs2_checkpt_space_ok(dev)) -+ return 0; -+ -+ if (!dev->checkpt_buffer) -+ dev->checkpt_buffer = -+ YMALLOC_DMA(dev->param.total_bytes_per_chunk); -+ if (!dev->checkpt_buffer) -+ return 0; -+ -+ dev->checkpt_page_seq = 0; -+ dev->checkpt_byte_count = 0; -+ dev->checkpt_sum = 0; -+ dev->checkpt_xor = 0; -+ dev->checkpt_cur_block = -1; -+ dev->checkpt_cur_chunk = -1; -+ dev->checkpt_next_block = dev->internal_start_block; -+ -+ /* Erase all the blocks in the checkpoint area */ -+ if (writing) { -+ memset(dev->checkpt_buffer, 0, dev->data_bytes_per_chunk); -+ dev->checkpt_byte_offs = 0; -+ return yaffs_checkpt_erase(dev); -+ } else { -+ int i; -+ /* Set to a value that will kick off a read */ -+ dev->checkpt_byte_offs = dev->data_bytes_per_chunk; -+ /* A checkpoint block list of 1 checkpoint block per 16 block is (hopefully) -+ * going to be way more than we need */ -+ dev->blocks_in_checkpt = 0; -+ dev->checkpt_max_blocks = -+ (dev->internal_end_block - dev->internal_start_block) / 16 + -+ 2; -+ dev->checkpt_block_list = -+ YMALLOC(sizeof(int) * dev->checkpt_max_blocks); -+ if (!dev->checkpt_block_list) -+ return 0; -+ -+ for (i = 0; i < dev->checkpt_max_blocks; i++) -+ dev->checkpt_block_list[i] = -1; -+ } -+ -+ return 1; -+} -+ -+int yaffs2_get_checkpt_sum(struct yaffs_dev *dev, u32 * sum) -+{ -+ u32 composite_sum; -+ composite_sum = (dev->checkpt_sum << 8) | (dev->checkpt_xor & 0xFF); -+ *sum = composite_sum; -+ return 1; -+} -+ -+static int yaffs2_checkpt_flush_buffer(struct yaffs_dev *dev) -+{ -+ int chunk; -+ int realigned_chunk; -+ -+ struct yaffs_ext_tags tags; -+ -+ if (dev->checkpt_cur_block < 0) { -+ yaffs2_checkpt_find_erased_block(dev); -+ dev->checkpt_cur_chunk = 0; -+ } -+ -+ if (dev->checkpt_cur_block < 0) -+ return 0; -+ -+ tags.is_deleted = 0; -+ tags.obj_id = dev->checkpt_next_block; /* Hint to next place to look */ -+ tags.chunk_id = dev->checkpt_page_seq + 1; -+ tags.seq_number = YAFFS_SEQUENCE_CHECKPOINT_DATA; -+ tags.n_bytes = dev->data_bytes_per_chunk; -+ if (dev->checkpt_cur_chunk == 0) { -+ /* First chunk we write for the block? Set block state to -+ checkpoint */ -+ struct yaffs_block_info *bi = -+ yaffs_get_block_info(dev, dev->checkpt_cur_block); -+ bi->block_state = YAFFS_BLOCK_STATE_CHECKPOINT; -+ dev->blocks_in_checkpt++; -+ } -+ -+ chunk = -+ dev->checkpt_cur_block * dev->param.chunks_per_block + -+ dev->checkpt_cur_chunk; -+ -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR -+ ("checkpoint wite buffer nand %d(%d:%d) objid %d chId %d" TENDSTR), -+ chunk, dev->checkpt_cur_block, dev->checkpt_cur_chunk, tags.obj_id, -+ tags.chunk_id)); -+ -+ realigned_chunk = chunk - dev->chunk_offset; -+ -+ dev->n_page_writes++; -+ -+ dev->param.write_chunk_tags_fn(dev, realigned_chunk, -+ dev->checkpt_buffer, &tags); -+ dev->checkpt_byte_offs = 0; -+ dev->checkpt_page_seq++; -+ dev->checkpt_cur_chunk++; -+ if (dev->checkpt_cur_chunk >= dev->param.chunks_per_block) { -+ dev->checkpt_cur_chunk = 0; -+ dev->checkpt_cur_block = -1; -+ } -+ memset(dev->checkpt_buffer, 0, dev->data_bytes_per_chunk); -+ -+ return 1; -+} -+ -+int yaffs2_checkpt_wr(struct yaffs_dev *dev, const void *data, int n_bytes) -+{ -+ int i = 0; -+ int ok = 1; -+ -+ u8 *data_bytes = (u8 *) data; -+ -+ if (!dev->checkpt_buffer) -+ return 0; -+ -+ if (!dev->checkpt_open_write) -+ return -1; -+ -+ while (i < n_bytes && ok) { -+ dev->checkpt_buffer[dev->checkpt_byte_offs] = *data_bytes; -+ dev->checkpt_sum += *data_bytes; -+ dev->checkpt_xor ^= *data_bytes; -+ -+ dev->checkpt_byte_offs++; -+ i++; -+ data_bytes++; -+ dev->checkpt_byte_count++; -+ -+ if (dev->checkpt_byte_offs < 0 || -+ dev->checkpt_byte_offs >= dev->data_bytes_per_chunk) -+ ok = yaffs2_checkpt_flush_buffer(dev); -+ } -+ -+ return i; -+} -+ -+int yaffs2_checkpt_rd(struct yaffs_dev *dev, void *data, int n_bytes) -+{ -+ int i = 0; -+ int ok = 1; -+ struct yaffs_ext_tags tags; -+ -+ int chunk; -+ int realigned_chunk; -+ -+ u8 *data_bytes = (u8 *) data; -+ -+ if (!dev->checkpt_buffer) -+ return 0; -+ -+ if (dev->checkpt_open_write) -+ return -1; -+ -+ while (i < n_bytes && ok) { -+ -+ if (dev->checkpt_byte_offs < 0 || -+ dev->checkpt_byte_offs >= dev->data_bytes_per_chunk) { -+ -+ if (dev->checkpt_cur_block < 0) { -+ yaffs2_checkpt_find_block(dev); -+ dev->checkpt_cur_chunk = 0; -+ } -+ -+ if (dev->checkpt_cur_block < 0) -+ ok = 0; -+ else { -+ chunk = dev->checkpt_cur_block * -+ dev->param.chunks_per_block + -+ dev->checkpt_cur_chunk; -+ -+ realigned_chunk = chunk - dev->chunk_offset; -+ -+ dev->n_page_reads++; -+ -+ /* read in the next chunk */ -+ dev->param.read_chunk_tags_fn(dev, -+ realigned_chunk, -+ dev-> -+ checkpt_buffer, -+ &tags); -+ -+ if (tags.chunk_id != (dev->checkpt_page_seq + 1) -+ || tags.ecc_result > YAFFS_ECC_RESULT_FIXED -+ || tags.seq_number != -+ YAFFS_SEQUENCE_CHECKPOINT_DATA) -+ ok = 0; -+ -+ dev->checkpt_byte_offs = 0; -+ dev->checkpt_page_seq++; -+ dev->checkpt_cur_chunk++; -+ -+ if (dev->checkpt_cur_chunk >= -+ dev->param.chunks_per_block) -+ dev->checkpt_cur_block = -1; -+ } -+ } -+ -+ if (ok) { -+ *data_bytes = -+ dev->checkpt_buffer[dev->checkpt_byte_offs]; -+ dev->checkpt_sum += *data_bytes; -+ dev->checkpt_xor ^= *data_bytes; -+ dev->checkpt_byte_offs++; -+ i++; -+ data_bytes++; -+ dev->checkpt_byte_count++; -+ } -+ } -+ -+ return i; -+} -+ -+int yaffs_checkpt_close(struct yaffs_dev *dev) -+{ -+ -+ if (dev->checkpt_open_write) { -+ if (dev->checkpt_byte_offs != 0) -+ yaffs2_checkpt_flush_buffer(dev); -+ } else if (dev->checkpt_block_list) { -+ int i; -+ for (i = 0; -+ i < dev->blocks_in_checkpt -+ && dev->checkpt_block_list[i] >= 0; i++) { -+ int blk = dev->checkpt_block_list[i]; -+ struct yaffs_block_info *bi = NULL; -+ if (dev->internal_start_block <= blk -+ && blk <= dev->internal_end_block) -+ bi = yaffs_get_block_info(dev, blk); -+ if (bi && bi->block_state == YAFFS_BLOCK_STATE_EMPTY) -+ bi->block_state = YAFFS_BLOCK_STATE_CHECKPOINT; -+ else { -+ /* Todo this looks odd... */ -+ } -+ } -+ YFREE(dev->checkpt_block_list); -+ dev->checkpt_block_list = NULL; -+ } -+ -+ dev->n_free_chunks -= -+ dev->blocks_in_checkpt * dev->param.chunks_per_block; -+ dev->n_erased_blocks -= dev->blocks_in_checkpt; -+ -+ T(YAFFS_TRACE_CHECKPOINT, (TSTR("checkpoint byte count %d" TENDSTR), -+ dev->checkpt_byte_count)); -+ -+ if (dev->checkpt_buffer) { -+ /* free the buffer */ -+ YFREE(dev->checkpt_buffer); -+ dev->checkpt_buffer = NULL; -+ return 1; -+ } else { -+ return 0; -+ } -+} -+ -+int yaffs2_checkpt_invalidate_stream(struct yaffs_dev *dev) -+{ -+ /* Erase the checkpoint data */ -+ -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR("checkpoint invalidate of %d blocks" TENDSTR), -+ dev->blocks_in_checkpt)); -+ -+ return yaffs_checkpt_erase(dev); -+} -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_checkptrw.h linux-2.6.36/fs/yaffs2/yaffs_checkptrw.h ---- linux-2.6.36.orig/fs/yaffs2/yaffs_checkptrw.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_checkptrw.h 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,33 @@ -+/* -+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU Lesser General Public License version 2.1 as -+ * published by the Free Software Foundation. -+ * -+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. -+ */ -+ -+#ifndef __YAFFS_CHECKPTRW_H__ -+#define __YAFFS_CHECKPTRW_H__ -+ -+#include "yaffs_guts.h" -+ -+int yaffs2_checkpt_open(struct yaffs_dev *dev, int writing); -+ -+int yaffs2_checkpt_wr(struct yaffs_dev *dev, const void *data, int n_bytes); -+ -+int yaffs2_checkpt_rd(struct yaffs_dev *dev, void *data, int n_bytes); -+ -+int yaffs2_get_checkpt_sum(struct yaffs_dev *dev, u32 * sum); -+ -+int yaffs_checkpt_close(struct yaffs_dev *dev); -+ -+int yaffs2_checkpt_invalidate_stream(struct yaffs_dev *dev); -+ -+#endif -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_ecc.c linux-2.6.36/fs/yaffs2/yaffs_ecc.c ---- linux-2.6.36.orig/fs/yaffs2/yaffs_ecc.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_ecc.c 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,322 @@ -+/* -+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+/* -+ * This code implements the ECC algorithm used in SmartMedia. -+ * -+ * The ECC comprises 22 bits of parity information and is stuffed into 3 bytes. -+ * The two unused bit are set to 1. -+ * The ECC can correct single bit errors in a 256-byte page of data. Thus, two such ECC -+ * blocks are used on a 512-byte NAND page. -+ * -+ */ -+ -+/* Table generated by gen-ecc.c -+ * Using a table means we do not have to calculate p1..p4 and p1'..p4' -+ * for each byte of data. These are instead provided in a table in bits7..2. -+ * Bit 0 of each entry indicates whether the entry has an odd or even parity, and therefore -+ * this bytes influence on the line parity. -+ */ -+ -+#include "yportenv.h" -+ -+#include "yaffs_ecc.h" -+ -+static const unsigned char column_parity_table[] = { -+ 0x00, 0x55, 0x59, 0x0c, 0x65, 0x30, 0x3c, 0x69, -+ 0x69, 0x3c, 0x30, 0x65, 0x0c, 0x59, 0x55, 0x00, -+ 0x95, 0xc0, 0xcc, 0x99, 0xf0, 0xa5, 0xa9, 0xfc, -+ 0xfc, 0xa9, 0xa5, 0xf0, 0x99, 0xcc, 0xc0, 0x95, -+ 0x99, 0xcc, 0xc0, 0x95, 0xfc, 0xa9, 0xa5, 0xf0, -+ 0xf0, 0xa5, 0xa9, 0xfc, 0x95, 0xc0, 0xcc, 0x99, -+ 0x0c, 0x59, 0x55, 0x00, 0x69, 0x3c, 0x30, 0x65, -+ 0x65, 0x30, 0x3c, 0x69, 0x00, 0x55, 0x59, 0x0c, -+ 0xa5, 0xf0, 0xfc, 0xa9, 0xc0, 0x95, 0x99, 0xcc, -+ 0xcc, 0x99, 0x95, 0xc0, 0xa9, 0xfc, 0xf0, 0xa5, -+ 0x30, 0x65, 0x69, 0x3c, 0x55, 0x00, 0x0c, 0x59, -+ 0x59, 0x0c, 0x00, 0x55, 0x3c, 0x69, 0x65, 0x30, -+ 0x3c, 0x69, 0x65, 0x30, 0x59, 0x0c, 0x00, 0x55, -+ 0x55, 0x00, 0x0c, 0x59, 0x30, 0x65, 0x69, 0x3c, -+ 0xa9, 0xfc, 0xf0, 0xa5, 0xcc, 0x99, 0x95, 0xc0, -+ 0xc0, 0x95, 0x99, 0xcc, 0xa5, 0xf0, 0xfc, 0xa9, -+ 0xa9, 0xfc, 0xf0, 0xa5, 0xcc, 0x99, 0x95, 0xc0, -+ 0xc0, 0x95, 0x99, 0xcc, 0xa5, 0xf0, 0xfc, 0xa9, -+ 0x3c, 0x69, 0x65, 0x30, 0x59, 0x0c, 0x00, 0x55, -+ 0x55, 0x00, 0x0c, 0x59, 0x30, 0x65, 0x69, 0x3c, -+ 0x30, 0x65, 0x69, 0x3c, 0x55, 0x00, 0x0c, 0x59, -+ 0x59, 0x0c, 0x00, 0x55, 0x3c, 0x69, 0x65, 0x30, -+ 0xa5, 0xf0, 0xfc, 0xa9, 0xc0, 0x95, 0x99, 0xcc, -+ 0xcc, 0x99, 0x95, 0xc0, 0xa9, 0xfc, 0xf0, 0xa5, -+ 0x0c, 0x59, 0x55, 0x00, 0x69, 0x3c, 0x30, 0x65, -+ 0x65, 0x30, 0x3c, 0x69, 0x00, 0x55, 0x59, 0x0c, -+ 0x99, 0xcc, 0xc0, 0x95, 0xfc, 0xa9, 0xa5, 0xf0, -+ 0xf0, 0xa5, 0xa9, 0xfc, 0x95, 0xc0, 0xcc, 0x99, -+ 0x95, 0xc0, 0xcc, 0x99, 0xf0, 0xa5, 0xa9, 0xfc, -+ 0xfc, 0xa9, 0xa5, 0xf0, 0x99, 0xcc, 0xc0, 0x95, -+ 0x00, 0x55, 0x59, 0x0c, 0x65, 0x30, 0x3c, 0x69, -+ 0x69, 0x3c, 0x30, 0x65, 0x0c, 0x59, 0x55, 0x00, -+}; -+ -+/* Count the bits in an unsigned char or a U32 */ -+ -+static int yaffs_count_bits(unsigned char x) -+{ -+ int r = 0; -+ while (x) { -+ if (x & 1) -+ r++; -+ x >>= 1; -+ } -+ return r; -+} -+ -+static int yaffs_count_bits32(unsigned x) -+{ -+ int r = 0; -+ while (x) { -+ if (x & 1) -+ r++; -+ x >>= 1; -+ } -+ return r; -+} -+ -+/* Calculate the ECC for a 256-byte block of data */ -+void yaffs_ecc_cacl(const unsigned char *data, unsigned char *ecc) -+{ -+ unsigned int i; -+ -+ unsigned char col_parity = 0; -+ unsigned char line_parity = 0; -+ unsigned char line_parity_prime = 0; -+ unsigned char t; -+ unsigned char b; -+ -+ for (i = 0; i < 256; i++) { -+ b = column_parity_table[*data++]; -+ col_parity ^= b; -+ -+ if (b & 0x01) { /* odd number of bits in the byte */ -+ line_parity ^= i; -+ line_parity_prime ^= ~i; -+ } -+ } -+ -+ ecc[2] = (~col_parity) | 0x03; -+ -+ t = 0; -+ if (line_parity & 0x80) -+ t |= 0x80; -+ if (line_parity_prime & 0x80) -+ t |= 0x40; -+ if (line_parity & 0x40) -+ t |= 0x20; -+ if (line_parity_prime & 0x40) -+ t |= 0x10; -+ if (line_parity & 0x20) -+ t |= 0x08; -+ if (line_parity_prime & 0x20) -+ t |= 0x04; -+ if (line_parity & 0x10) -+ t |= 0x02; -+ if (line_parity_prime & 0x10) -+ t |= 0x01; -+ ecc[1] = ~t; -+ -+ t = 0; -+ if (line_parity & 0x08) -+ t |= 0x80; -+ if (line_parity_prime & 0x08) -+ t |= 0x40; -+ if (line_parity & 0x04) -+ t |= 0x20; -+ if (line_parity_prime & 0x04) -+ t |= 0x10; -+ if (line_parity & 0x02) -+ t |= 0x08; -+ if (line_parity_prime & 0x02) -+ t |= 0x04; -+ if (line_parity & 0x01) -+ t |= 0x02; -+ if (line_parity_prime & 0x01) -+ t |= 0x01; -+ ecc[0] = ~t; -+ -+#ifdef CONFIG_YAFFS_ECC_WRONG_ORDER -+ /* Swap the bytes into the wrong order */ -+ t = ecc[0]; -+ ecc[0] = ecc[1]; -+ ecc[1] = t; -+#endif -+} -+ -+/* Correct the ECC on a 256 byte block of data */ -+ -+int yaffs_ecc_correct(unsigned char *data, unsigned char *read_ecc, -+ const unsigned char *test_ecc) -+{ -+ unsigned char d0, d1, d2; /* deltas */ -+ -+ d0 = read_ecc[0] ^ test_ecc[0]; -+ d1 = read_ecc[1] ^ test_ecc[1]; -+ d2 = read_ecc[2] ^ test_ecc[2]; -+ -+ if ((d0 | d1 | d2) == 0) -+ return 0; /* no error */ -+ -+ if (((d0 ^ (d0 >> 1)) & 0x55) == 0x55 && -+ ((d1 ^ (d1 >> 1)) & 0x55) == 0x55 && -+ ((d2 ^ (d2 >> 1)) & 0x54) == 0x54) { -+ /* Single bit (recoverable) error in data */ -+ -+ unsigned byte; -+ unsigned bit; -+ -+#ifdef CONFIG_YAFFS_ECC_WRONG_ORDER -+ /* swap the bytes to correct for the wrong order */ -+ unsigned char t; -+ -+ t = d0; -+ d0 = d1; -+ d1 = t; -+#endif -+ -+ bit = byte = 0; -+ -+ if (d1 & 0x80) -+ byte |= 0x80; -+ if (d1 & 0x20) -+ byte |= 0x40; -+ if (d1 & 0x08) -+ byte |= 0x20; -+ if (d1 & 0x02) -+ byte |= 0x10; -+ if (d0 & 0x80) -+ byte |= 0x08; -+ if (d0 & 0x20) -+ byte |= 0x04; -+ if (d0 & 0x08) -+ byte |= 0x02; -+ if (d0 & 0x02) -+ byte |= 0x01; -+ -+ if (d2 & 0x80) -+ bit |= 0x04; -+ if (d2 & 0x20) -+ bit |= 0x02; -+ if (d2 & 0x08) -+ bit |= 0x01; -+ -+ data[byte] ^= (1 << bit); -+ -+ return 1; /* Corrected the error */ -+ } -+ -+ if ((yaffs_count_bits(d0) + -+ yaffs_count_bits(d1) + yaffs_count_bits(d2)) == 1) { -+ /* Reccoverable error in ecc */ -+ -+ read_ecc[0] = test_ecc[0]; -+ read_ecc[1] = test_ecc[1]; -+ read_ecc[2] = test_ecc[2]; -+ -+ return 1; /* Corrected the error */ -+ } -+ -+ /* Unrecoverable error */ -+ -+ return -1; -+ -+} -+ -+/* -+ * ECCxxxOther does ECC calcs on arbitrary n bytes of data -+ */ -+void yaffs_ecc_calc_other(const unsigned char *data, unsigned n_bytes, -+ struct yaffs_ecc_other *ecc_other) -+{ -+ unsigned int i; -+ -+ unsigned char col_parity = 0; -+ unsigned line_parity = 0; -+ unsigned line_parity_prime = 0; -+ unsigned char b; -+ -+ for (i = 0; i < n_bytes; i++) { -+ b = column_parity_table[*data++]; -+ col_parity ^= b; -+ -+ if (b & 0x01) { -+ /* odd number of bits in the byte */ -+ line_parity ^= i; -+ line_parity_prime ^= ~i; -+ } -+ -+ } -+ -+ ecc_other->col_parity = (col_parity >> 2) & 0x3f; -+ ecc_other->line_parity = line_parity; -+ ecc_other->line_parity_prime = line_parity_prime; -+} -+ -+int yaffs_ecc_correct_other(unsigned char *data, unsigned n_bytes, -+ struct yaffs_ecc_other *read_ecc, -+ const struct yaffs_ecc_other *test_ecc) -+{ -+ unsigned char delta_col; /* column parity delta */ -+ unsigned delta_line; /* line parity delta */ -+ unsigned delta_line_prime; /* line parity delta */ -+ unsigned bit; -+ -+ delta_col = read_ecc->col_parity ^ test_ecc->col_parity; -+ delta_line = read_ecc->line_parity ^ test_ecc->line_parity; -+ delta_line_prime = -+ read_ecc->line_parity_prime ^ test_ecc->line_parity_prime; -+ -+ if ((delta_col | delta_line | delta_line_prime) == 0) -+ return 0; /* no error */ -+ -+ if (delta_line == ~delta_line_prime && -+ (((delta_col ^ (delta_col >> 1)) & 0x15) == 0x15)) { -+ /* Single bit (recoverable) error in data */ -+ -+ bit = 0; -+ -+ if (delta_col & 0x20) -+ bit |= 0x04; -+ if (delta_col & 0x08) -+ bit |= 0x02; -+ if (delta_col & 0x02) -+ bit |= 0x01; -+ -+ if (delta_line >= n_bytes) -+ return -1; -+ -+ data[delta_line] ^= (1 << bit); -+ -+ return 1; /* corrected */ -+ } -+ -+ if ((yaffs_count_bits32(delta_line) + -+ yaffs_count_bits32(delta_line_prime) + -+ yaffs_count_bits(delta_col)) == 1) { -+ /* Reccoverable error in ecc */ -+ -+ *read_ecc = *test_ecc; -+ return 1; /* corrected */ -+ } -+ -+ /* Unrecoverable error */ -+ -+ return -1; -+} -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_ecc.h linux-2.6.36/fs/yaffs2/yaffs_ecc.h ---- linux-2.6.36.orig/fs/yaffs2/yaffs_ecc.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_ecc.h 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,44 @@ -+/* -+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU Lesser General Public License version 2.1 as -+ * published by the Free Software Foundation. -+ * -+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. -+ */ -+ -+/* -+ * This code implements the ECC algorithm used in SmartMedia. -+ * -+ * The ECC comprises 22 bits of parity information and is stuffed into 3 bytes. -+ * The two unused bit are set to 1. -+ * The ECC can correct single bit errors in a 256-byte page of data. Thus, two such ECC -+ * blocks are used on a 512-byte NAND page. -+ * -+ */ -+ -+#ifndef __YAFFS_ECC_H__ -+#define __YAFFS_ECC_H__ -+ -+struct yaffs_ecc_other { -+ unsigned char col_parity; -+ unsigned line_parity; -+ unsigned line_parity_prime; -+}; -+ -+void yaffs_ecc_cacl(const unsigned char *data, unsigned char *ecc); -+int yaffs_ecc_correct(unsigned char *data, unsigned char *read_ecc, -+ const unsigned char *test_ecc); -+ -+void yaffs_ecc_calc_other(const unsigned char *data, unsigned n_bytes, -+ struct yaffs_ecc_other *ecc); -+int yaffs_ecc_correct_other(unsigned char *data, unsigned n_bytes, -+ struct yaffs_ecc_other *read_ecc, -+ const struct yaffs_ecc_other *test_ecc); -+#endif -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_getblockinfo.h linux-2.6.36/fs/yaffs2/yaffs_getblockinfo.h ---- linux-2.6.36.orig/fs/yaffs2/yaffs_getblockinfo.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_getblockinfo.h 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,36 @@ -+/* -+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU Lesser General Public License version 2.1 as -+ * published by the Free Software Foundation. -+ * -+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. -+ */ -+ -+#ifndef __YAFFS_GETBLOCKINFO_H__ -+#define __YAFFS_GETBLOCKINFO_H__ -+ -+#include "yaffs_guts.h" -+#include "yaffs_trace.h" -+ -+/* Function to manipulate block info */ -+static Y_INLINE struct yaffs_block_info *yaffs_get_block_info(struct yaffs_dev -+ *dev, int blk) -+{ -+ if (blk < dev->internal_start_block || blk > dev->internal_end_block) { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR -+ ("**>> yaffs: get_block_info block %d is not valid" TENDSTR), -+ blk)); -+ YBUG(); -+ } -+ return &dev->block_info[blk - dev->internal_start_block]; -+} -+ -+#endif -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_guts.c linux-2.6.36/fs/yaffs2/yaffs_guts.c ---- linux-2.6.36.orig/fs/yaffs2/yaffs_guts.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_guts.c 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,5227 @@ -+/* -+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include "yportenv.h" -+#include "yaffs_trace.h" -+ -+#include "yaffs_guts.h" -+#include "yaffs_tagsvalidity.h" -+#include "yaffs_getblockinfo.h" -+ -+#include "yaffs_tagscompat.h" -+ -+#include "yaffs_nand.h" -+ -+#include "yaffs_yaffs1.h" -+#include "yaffs_yaffs2.h" -+#include "yaffs_bitmap.h" -+#include "yaffs_verify.h" -+ -+#include "yaffs_nand.h" -+#include "yaffs_packedtags2.h" -+ -+#include "yaffs_nameval.h" -+#include "yaffs_allocator.h" -+ -+#include "yaffs_attribs.h" -+ -+/* Note YAFFS_GC_GOOD_ENOUGH must be <= YAFFS_GC_PASSIVE_THRESHOLD */ -+#define YAFFS_GC_GOOD_ENOUGH 2 -+#define YAFFS_GC_PASSIVE_THRESHOLD 4 -+ -+#include "yaffs_ecc.h" -+ -+/* Robustification (if it ever comes about...) */ -+static void yaffs_retire_block(struct yaffs_dev *dev, int flash_block); -+static void yaffs_handle_chunk_wr_error(struct yaffs_dev *dev, int nand_chunk, -+ int erased_ok); -+static void yaffs_handle_chunk_wr_ok(struct yaffs_dev *dev, int nand_chunk, -+ const u8 * data, -+ const struct yaffs_ext_tags *tags); -+static void yaffs_handle_chunk_update(struct yaffs_dev *dev, int nand_chunk, -+ const struct yaffs_ext_tags *tags); -+ -+/* Other local prototypes */ -+static void yaffs_update_parent(struct yaffs_obj *obj); -+static int yaffs_unlink_obj(struct yaffs_obj *obj); -+static int yaffs_obj_cache_dirty(struct yaffs_obj *obj); -+ -+static int yaffs_write_new_chunk(struct yaffs_dev *dev, -+ const u8 * buffer, -+ struct yaffs_ext_tags *tags, int use_reserver); -+ -+static struct yaffs_obj *yaffs_new_obj(struct yaffs_dev *dev, int number, -+ enum yaffs_obj_type type); -+ -+static int yaffs_apply_xattrib_mod(struct yaffs_obj *obj, char *buffer, -+ struct yaffs_xattr_mod *xmod); -+ -+static void yaffs_remove_obj_from_dir(struct yaffs_obj *obj); -+static int yaffs_generic_obj_del(struct yaffs_obj *in); -+ -+static int yaffs_check_chunk_erased(struct yaffs_dev *dev, int nand_chunk); -+ -+static int yaffs_unlink_worker(struct yaffs_obj *obj); -+ -+static int yaffs_tags_match(const struct yaffs_ext_tags *tags, int obj_id, -+ int chunk_obj); -+ -+static int yaffs_alloc_chunk(struct yaffs_dev *dev, int use_reserver, -+ struct yaffs_block_info **block_ptr); -+ -+static void yaffs_check_obj_details_loaded(struct yaffs_obj *in); -+ -+static void yaffs_invalidate_whole_cache(struct yaffs_obj *in); -+static void yaffs_invalidate_chunk_cache(struct yaffs_obj *object, -+ int chunk_id); -+ -+static int yaffs_find_chunk_in_file(struct yaffs_obj *in, int inode_chunk, -+ struct yaffs_ext_tags *tags); -+ -+static int yaffs_verify_chunk_written(struct yaffs_dev *dev, -+ int nand_chunk, -+ const u8 * data, -+ struct yaffs_ext_tags *tags); -+ -+static void yaffs_load_name_from_oh(struct yaffs_dev *dev, YCHAR * name, -+ const YCHAR * oh_name, int buff_size); -+static void yaffs_load_oh_from_name(struct yaffs_dev *dev, YCHAR * oh_name, -+ const YCHAR * name); -+ -+/* Function to calculate chunk and offset */ -+ -+static void yaffs_addr_to_chunk(struct yaffs_dev *dev, loff_t addr, -+ int *chunk_out, u32 * offset_out) -+{ -+ int chunk; -+ u32 offset; -+ -+ chunk = (u32) (addr >> dev->chunk_shift); -+ -+ if (dev->chunk_div == 1) { -+ /* easy power of 2 case */ -+ offset = (u32) (addr & dev->chunk_mask); -+ } else { -+ /* Non power-of-2 case */ -+ -+ loff_t chunk_base; -+ -+ chunk /= dev->chunk_div; -+ -+ chunk_base = ((loff_t) chunk) * dev->data_bytes_per_chunk; -+ offset = (u32) (addr - chunk_base); -+ } -+ -+ *chunk_out = chunk; -+ *offset_out = offset; -+} -+ -+/* Function to return the number of shifts for a power of 2 greater than or -+ * equal to the given number -+ * Note we don't try to cater for all possible numbers and this does not have to -+ * be hellishly efficient. -+ */ -+ -+static u32 calc_shifts_ceiling(u32 x) -+{ -+ int extra_bits; -+ int shifts; -+ -+ shifts = extra_bits = 0; -+ -+ while (x > 1) { -+ if (x & 1) -+ extra_bits++; -+ x >>= 1; -+ shifts++; -+ } -+ -+ if (extra_bits) -+ shifts++; -+ -+ return shifts; -+} -+ -+/* Function to return the number of shifts to get a 1 in bit 0 -+ */ -+ -+static u32 calc_shifts(u32 x) -+{ -+ u32 shifts; -+ -+ shifts = 0; -+ -+ if (!x) -+ return 0; -+ -+ while (!(x & 1)) { -+ x >>= 1; -+ shifts++; -+ } -+ -+ return shifts; -+} -+ -+/* -+ * Temporary buffer manipulations. -+ */ -+ -+static int yaffs_init_tmp_buffers(struct yaffs_dev *dev) -+{ -+ int i; -+ u8 *buf = (u8 *) 1; -+ -+ memset(dev->temp_buffer, 0, sizeof(dev->temp_buffer)); -+ -+ for (i = 0; buf && i < YAFFS_N_TEMP_BUFFERS; i++) { -+ dev->temp_buffer[i].line = 0; /* not in use */ -+ dev->temp_buffer[i].buffer = buf = -+ YMALLOC_DMA(dev->param.total_bytes_per_chunk); -+ } -+ -+ return buf ? YAFFS_OK : YAFFS_FAIL; -+} -+ -+u8 *yaffs_get_temp_buffer(struct yaffs_dev * dev, int line_no) -+{ -+ int i, j; -+ -+ dev->temp_in_use++; -+ if (dev->temp_in_use > dev->max_temp) -+ dev->max_temp = dev->temp_in_use; -+ -+ for (i = 0; i < YAFFS_N_TEMP_BUFFERS; i++) { -+ if (dev->temp_buffer[i].line == 0) { -+ dev->temp_buffer[i].line = line_no; -+ if ((i + 1) > dev->max_temp) { -+ dev->max_temp = i + 1; -+ for (j = 0; j <= i; j++) -+ dev->temp_buffer[j].max_line = -+ dev->temp_buffer[j].line; -+ } -+ -+ return dev->temp_buffer[i].buffer; -+ } -+ } -+ -+ T(YAFFS_TRACE_BUFFERS, -+ (TSTR("Out of temp buffers at line %d, other held by lines:"), -+ line_no)); -+ for (i = 0; i < YAFFS_N_TEMP_BUFFERS; i++) -+ T(YAFFS_TRACE_BUFFERS, -+ (TSTR(" %d "), dev->temp_buffer[i].line)); -+ -+ T(YAFFS_TRACE_BUFFERS, (TSTR(" " TENDSTR))); -+ -+ /* -+ * If we got here then we have to allocate an unmanaged one -+ * This is not good. -+ */ -+ -+ dev->unmanaged_buffer_allocs++; -+ return YMALLOC(dev->data_bytes_per_chunk); -+ -+} -+ -+void yaffs_release_temp_buffer(struct yaffs_dev *dev, u8 * buffer, int line_no) -+{ -+ int i; -+ -+ dev->temp_in_use--; -+ -+ for (i = 0; i < YAFFS_N_TEMP_BUFFERS; i++) { -+ if (dev->temp_buffer[i].buffer == buffer) { -+ dev->temp_buffer[i].line = 0; -+ return; -+ } -+ } -+ -+ if (buffer) { -+ /* assume it is an unmanaged one. */ -+ T(YAFFS_TRACE_BUFFERS, -+ (TSTR("Releasing unmanaged temp buffer in line %d" TENDSTR), -+ line_no)); -+ YFREE(buffer); -+ dev->unmanaged_buffer_deallocs++; -+ } -+ -+} -+ -+/* -+ * Determine if we have a managed buffer. -+ */ -+int yaffs_is_managed_tmp_buffer(struct yaffs_dev *dev, const u8 * buffer) -+{ -+ int i; -+ -+ for (i = 0; i < YAFFS_N_TEMP_BUFFERS; i++) { -+ if (dev->temp_buffer[i].buffer == buffer) -+ return 1; -+ } -+ -+ for (i = 0; i < dev->param.n_caches; i++) { -+ if (dev->cache[i].data == buffer) -+ return 1; -+ } -+ -+ if (buffer == dev->checkpt_buffer) -+ return 1; -+ -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR("yaffs: unmaged buffer detected.\n" TENDSTR))); -+ return 0; -+} -+ -+/* -+ * Verification code -+ */ -+ -+/* -+ * Simple hash function. Needs to have a reasonable spread -+ */ -+ -+static Y_INLINE int yaffs_hash_fn(int n) -+{ -+ n = abs(n); -+ return n % YAFFS_NOBJECT_BUCKETS; -+} -+ -+/* -+ * Access functions to useful fake objects. -+ * Note that root might have a presence in NAND if permissions are set. -+ */ -+ -+struct yaffs_obj *yaffs_root(struct yaffs_dev *dev) -+{ -+ return dev->root_dir; -+} -+ -+struct yaffs_obj *yaffs_lost_n_found(struct yaffs_dev *dev) -+{ -+ return dev->lost_n_found; -+} -+ -+/* -+ * Erased NAND checking functions -+ */ -+ -+int yaffs_check_ff(u8 * buffer, int n_bytes) -+{ -+ /* Horrible, slow implementation */ -+ while (n_bytes--) { -+ if (*buffer != 0xFF) -+ return 0; -+ buffer++; -+ } -+ return 1; -+} -+ -+static int yaffs_check_chunk_erased(struct yaffs_dev *dev, int nand_chunk) -+{ -+ int retval = YAFFS_OK; -+ u8 *data = yaffs_get_temp_buffer(dev, __LINE__); -+ struct yaffs_ext_tags tags; -+ int result; -+ -+ result = yaffs_rd_chunk_tags_nand(dev, nand_chunk, data, &tags); -+ -+ if (tags.ecc_result > YAFFS_ECC_RESULT_NO_ERROR) -+ retval = YAFFS_FAIL; -+ -+ if (!yaffs_check_ff(data, dev->data_bytes_per_chunk) || tags.chunk_used) { -+ T(YAFFS_TRACE_NANDACCESS, -+ (TSTR("Chunk %d not erased" TENDSTR), nand_chunk)); -+ retval = YAFFS_FAIL; -+ } -+ -+ yaffs_release_temp_buffer(dev, data, __LINE__); -+ -+ return retval; -+ -+} -+ -+static int yaffs_verify_chunk_written(struct yaffs_dev *dev, -+ int nand_chunk, -+ const u8 * data, -+ struct yaffs_ext_tags *tags) -+{ -+ int retval = YAFFS_OK; -+ struct yaffs_ext_tags temp_tags; -+ u8 *buffer = yaffs_get_temp_buffer(dev, __LINE__); -+ int result; -+ -+ result = yaffs_rd_chunk_tags_nand(dev, nand_chunk, buffer, &temp_tags); -+ if (memcmp(buffer, data, dev->data_bytes_per_chunk) || -+ temp_tags.obj_id != tags->obj_id || -+ temp_tags.chunk_id != tags->chunk_id || -+ temp_tags.n_bytes != tags->n_bytes) -+ retval = YAFFS_FAIL; -+ -+ yaffs_release_temp_buffer(dev, buffer, __LINE__); -+ -+ return retval; -+} -+ -+static int yaffs_write_new_chunk(struct yaffs_dev *dev, -+ const u8 * data, -+ struct yaffs_ext_tags *tags, int use_reserver) -+{ -+ int attempts = 0; -+ int write_ok = 0; -+ int chunk; -+ -+ yaffs2_checkpt_invalidate(dev); -+ -+ do { -+ struct yaffs_block_info *bi = 0; -+ int erased_ok = 0; -+ -+ chunk = yaffs_alloc_chunk(dev, use_reserver, &bi); -+ if (chunk < 0) { -+ /* no space */ -+ break; -+ } -+ -+ /* First check this chunk is erased, if it needs -+ * checking. The checking policy (unless forced -+ * always on) is as follows: -+ * -+ * Check the first page we try to write in a block. -+ * If the check passes then we don't need to check any -+ * more. If the check fails, we check again... -+ * If the block has been erased, we don't need to check. -+ * -+ * However, if the block has been prioritised for gc, -+ * then we think there might be something odd about -+ * this block and stop using it. -+ * -+ * Rationale: We should only ever see chunks that have -+ * not been erased if there was a partially written -+ * chunk due to power loss. This checking policy should -+ * catch that case with very few checks and thus save a -+ * lot of checks that are most likely not needed. -+ * -+ * Mods to the above -+ * If an erase check fails or the write fails we skip the -+ * rest of the block. -+ */ -+ -+ /* let's give it a try */ -+ attempts++; -+ -+ if (dev->param.always_check_erased) -+ bi->skip_erased_check = 0; -+ -+ if (!bi->skip_erased_check) { -+ erased_ok = yaffs_check_chunk_erased(dev, chunk); -+ if (erased_ok != YAFFS_OK) { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR("**>> yaffs chunk %d was not erased" -+ TENDSTR), chunk)); -+ -+ /* If not erased, delete this one, -+ * skip rest of block and -+ * try another chunk */ -+ yaffs_chunk_del(dev, chunk, 1, __LINE__); -+ yaffs_skip_rest_of_block(dev); -+ continue; -+ } -+ } -+ -+ write_ok = yaffs_wr_chunk_tags_nand(dev, chunk, data, tags); -+ -+ if (!bi->skip_erased_check) -+ write_ok = -+ yaffs_verify_chunk_written(dev, chunk, data, tags); -+ -+ if (write_ok != YAFFS_OK) { -+ /* Clean up aborted write, skip to next block and -+ * try another chunk */ -+ yaffs_handle_chunk_wr_error(dev, chunk, erased_ok); -+ continue; -+ } -+ -+ bi->skip_erased_check = 1; -+ -+ /* Copy the data into the robustification buffer */ -+ yaffs_handle_chunk_wr_ok(dev, chunk, data, tags); -+ -+ } while (write_ok != YAFFS_OK && -+ (yaffs_wr_attempts <= 0 || attempts <= yaffs_wr_attempts)); -+ -+ if (!write_ok) -+ chunk = -1; -+ -+ if (attempts > 1) { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR("**>> yaffs write required %d attempts" TENDSTR), -+ attempts)); -+ -+ dev->n_retired_writes += (attempts - 1); -+ } -+ -+ return chunk; -+} -+ -+/* -+ * Block retiring for handling a broken block. -+ */ -+ -+static void yaffs_retire_block(struct yaffs_dev *dev, int flash_block) -+{ -+ struct yaffs_block_info *bi = yaffs_get_block_info(dev, flash_block); -+ -+ yaffs2_checkpt_invalidate(dev); -+ -+ yaffs2_clear_oldest_dirty_seq(dev, bi); -+ -+ if (yaffs_mark_bad(dev, flash_block) != YAFFS_OK) { -+ if (yaffs_erase_block(dev, flash_block) != YAFFS_OK) { -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR -+ ("yaffs: Failed to mark bad and erase block %d" -+ TENDSTR), flash_block)); -+ } else { -+ struct yaffs_ext_tags tags; -+ int chunk_id = -+ flash_block * dev->param.chunks_per_block; -+ -+ u8 *buffer = yaffs_get_temp_buffer(dev, __LINE__); -+ -+ memset(buffer, 0xff, dev->data_bytes_per_chunk); -+ yaffs_init_tags(&tags); -+ tags.seq_number = YAFFS_SEQUENCE_BAD_BLOCK; -+ if (dev->param.write_chunk_tags_fn(dev, chunk_id - -+ dev->chunk_offset, -+ buffer, -+ &tags) != YAFFS_OK) -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR -+ ("yaffs: Failed to " -+ TCONT("write bad block marker to block %d") -+ TENDSTR), flash_block)); -+ -+ yaffs_release_temp_buffer(dev, buffer, __LINE__); -+ } -+ } -+ -+ bi->block_state = YAFFS_BLOCK_STATE_DEAD; -+ bi->gc_prioritise = 0; -+ bi->needs_retiring = 0; -+ -+ dev->n_retired_blocks++; -+} -+ -+/* -+ * Functions for robustisizing TODO -+ * -+ */ -+ -+static void yaffs_handle_chunk_wr_ok(struct yaffs_dev *dev, int nand_chunk, -+ const u8 * data, -+ const struct yaffs_ext_tags *tags) -+{ -+ dev = dev; -+ nand_chunk = nand_chunk; -+ data = data; -+ tags = tags; -+} -+ -+static void yaffs_handle_chunk_update(struct yaffs_dev *dev, int nand_chunk, -+ const struct yaffs_ext_tags *tags) -+{ -+ dev = dev; -+ nand_chunk = nand_chunk; -+ tags = tags; -+} -+ -+void yaffs_handle_chunk_error(struct yaffs_dev *dev, -+ struct yaffs_block_info *bi) -+{ -+ if (!bi->gc_prioritise) { -+ bi->gc_prioritise = 1; -+ dev->has_pending_prioritised_gc = 1; -+ bi->chunk_error_strikes++; -+ -+ if (bi->chunk_error_strikes > 3) { -+ bi->needs_retiring = 1; /* Too many stikes, so retire this */ -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR("yaffs: Block struck out" TENDSTR))); -+ -+ } -+ } -+} -+ -+static void yaffs_handle_chunk_wr_error(struct yaffs_dev *dev, int nand_chunk, -+ int erased_ok) -+{ -+ int flash_block = nand_chunk / dev->param.chunks_per_block; -+ struct yaffs_block_info *bi = yaffs_get_block_info(dev, flash_block); -+ -+ yaffs_handle_chunk_error(dev, bi); -+ -+ if (erased_ok) { -+ /* Was an actual write failure, so mark the block for retirement */ -+ bi->needs_retiring = 1; -+ T(YAFFS_TRACE_ERROR | YAFFS_TRACE_BAD_BLOCKS, -+ (TSTR("**>> Block %d needs retiring" TENDSTR), flash_block)); -+ } -+ -+ /* Delete the chunk */ -+ yaffs_chunk_del(dev, nand_chunk, 1, __LINE__); -+ yaffs_skip_rest_of_block(dev); -+} -+ -+/*---------------- Name handling functions ------------*/ -+ -+static u16 yaffs_calc_name_sum(const YCHAR * name) -+{ -+ u16 sum = 0; -+ u16 i = 1; -+ -+ const YUCHAR *bname = (const YUCHAR *)name; -+ if (bname) { -+ while ((*bname) && (i < (YAFFS_MAX_NAME_LENGTH / 2))) { -+ -+ /* 0x1f mask is case insensitive */ -+ sum += ((*bname) & 0x1f) * i; -+ i++; -+ bname++; -+ } -+ } -+ return sum; -+} -+ -+void yaffs_set_obj_name(struct yaffs_obj *obj, const YCHAR * name) -+{ -+#ifndef CONFIG_YAFFS_NO_SHORT_NAMES -+ memset(obj->short_name, 0, sizeof(obj->short_name)); -+ if (name && -+ yaffs_strnlen(name, YAFFS_SHORT_NAME_LENGTH + 1) <= -+ YAFFS_SHORT_NAME_LENGTH) -+ yaffs_strcpy(obj->short_name, name); -+ else -+ obj->short_name[0] = _Y('\0'); -+#endif -+ obj->sum = yaffs_calc_name_sum(name); -+} -+ -+void yaffs_set_obj_name_from_oh(struct yaffs_obj *obj, -+ const struct yaffs_obj_hdr *oh) -+{ -+#ifdef CONFIG_YAFFS_AUTO_UNICODE -+ YCHAR tmp_name[YAFFS_MAX_NAME_LENGTH + 1]; -+ memset(tmp_name, 0, sizeof(tmp_name)); -+ yaffs_load_name_from_oh(obj->my_dev, tmp_name, oh->name, -+ YAFFS_MAX_NAME_LENGTH + 1); -+ yaffs_set_obj_name(obj, tmp_name); -+#else -+ yaffs_set_obj_name(obj, oh->name); -+#endif -+} -+ -+/*-------------------- TNODES ------------------- -+ -+ * List of spare tnodes -+ * The list is hooked together using the first pointer -+ * in the tnode. -+ */ -+ -+struct yaffs_tnode *yaffs_get_tnode(struct yaffs_dev *dev) -+{ -+ struct yaffs_tnode *tn = yaffs_alloc_raw_tnode(dev); -+ if (tn) { -+ memset(tn, 0, dev->tnode_size); -+ dev->n_tnodes++; -+ } -+ -+ dev->checkpoint_blocks_required = 0; /* force recalculation */ -+ -+ return tn; -+} -+ -+/* FreeTnode frees up a tnode and puts it back on the free list */ -+static void yaffs_free_tnode(struct yaffs_dev *dev, struct yaffs_tnode *tn) -+{ -+ yaffs_free_raw_tnode(dev, tn); -+ dev->n_tnodes--; -+ dev->checkpoint_blocks_required = 0; /* force recalculation */ -+} -+ -+static void yaffs_deinit_tnodes_and_objs(struct yaffs_dev *dev) -+{ -+ yaffs_deinit_raw_tnodes_and_objs(dev); -+ dev->n_obj = 0; -+ dev->n_tnodes = 0; -+} -+ -+void yaffs_load_tnode_0(struct yaffs_dev *dev, struct yaffs_tnode *tn, -+ unsigned pos, unsigned val) -+{ -+ u32 *map = (u32 *) tn; -+ u32 bit_in_map; -+ u32 bit_in_word; -+ u32 word_in_map; -+ u32 mask; -+ -+ pos &= YAFFS_TNODES_LEVEL0_MASK; -+ val >>= dev->chunk_grp_bits; -+ -+ bit_in_map = pos * dev->tnode_width; -+ word_in_map = bit_in_map / 32; -+ bit_in_word = bit_in_map & (32 - 1); -+ -+ mask = dev->tnode_mask << bit_in_word; -+ -+ map[word_in_map] &= ~mask; -+ map[word_in_map] |= (mask & (val << bit_in_word)); -+ -+ if (dev->tnode_width > (32 - bit_in_word)) { -+ bit_in_word = (32 - bit_in_word); -+ word_in_map++;; -+ mask = -+ dev->tnode_mask >> ( /*dev->tnode_width - */ bit_in_word); -+ map[word_in_map] &= ~mask; -+ map[word_in_map] |= (mask & (val >> bit_in_word)); -+ } -+} -+ -+u32 yaffs_get_group_base(struct yaffs_dev *dev, struct yaffs_tnode *tn, -+ unsigned pos) -+{ -+ u32 *map = (u32 *) tn; -+ u32 bit_in_map; -+ u32 bit_in_word; -+ u32 word_in_map; -+ u32 val; -+ -+ pos &= YAFFS_TNODES_LEVEL0_MASK; -+ -+ bit_in_map = pos * dev->tnode_width; -+ word_in_map = bit_in_map / 32; -+ bit_in_word = bit_in_map & (32 - 1); -+ -+ val = map[word_in_map] >> bit_in_word; -+ -+ if (dev->tnode_width > (32 - bit_in_word)) { -+ bit_in_word = (32 - bit_in_word); -+ word_in_map++;; -+ val |= (map[word_in_map] << bit_in_word); -+ } -+ -+ val &= dev->tnode_mask; -+ val <<= dev->chunk_grp_bits; -+ -+ return val; -+} -+ -+/* ------------------- End of individual tnode manipulation -----------------*/ -+ -+/* ---------Functions to manipulate the look-up tree (made up of tnodes) ------ -+ * The look up tree is represented by the top tnode and the number of top_level -+ * in the tree. 0 means only the level 0 tnode is in the tree. -+ */ -+ -+/* FindLevel0Tnode finds the level 0 tnode, if one exists. */ -+struct yaffs_tnode *yaffs_find_tnode_0(struct yaffs_dev *dev, -+ struct yaffs_file_var *file_struct, -+ u32 chunk_id) -+{ -+ struct yaffs_tnode *tn = file_struct->top; -+ u32 i; -+ int required_depth; -+ int level = file_struct->top_level; -+ -+ dev = dev; -+ -+ /* Check sane level and chunk Id */ -+ if (level < 0 || level > YAFFS_TNODES_MAX_LEVEL) -+ return NULL; -+ -+ if (chunk_id > YAFFS_MAX_CHUNK_ID) -+ return NULL; -+ -+ /* First check we're tall enough (ie enough top_level) */ -+ -+ i = chunk_id >> YAFFS_TNODES_LEVEL0_BITS; -+ required_depth = 0; -+ while (i) { -+ i >>= YAFFS_TNODES_INTERNAL_BITS; -+ required_depth++; -+ } -+ -+ if (required_depth > file_struct->top_level) -+ return NULL; /* Not tall enough, so we can't find it */ -+ -+ /* Traverse down to level 0 */ -+ while (level > 0 && tn) { -+ tn = tn->internal[(chunk_id >> -+ (YAFFS_TNODES_LEVEL0_BITS + -+ (level - 1) * -+ YAFFS_TNODES_INTERNAL_BITS)) & -+ YAFFS_TNODES_INTERNAL_MASK]; -+ level--; -+ } -+ -+ return tn; -+} -+ -+/* AddOrFindLevel0Tnode finds the level 0 tnode if it exists, otherwise first expands the tree. -+ * This happens in two steps: -+ * 1. If the tree isn't tall enough, then make it taller. -+ * 2. Scan down the tree towards the level 0 tnode adding tnodes if required. -+ * -+ * Used when modifying the tree. -+ * -+ * If the tn argument is NULL, then a fresh tnode will be added otherwise the specified tn will -+ * be plugged into the ttree. -+ */ -+ -+struct yaffs_tnode *yaffs_add_find_tnode_0(struct yaffs_dev *dev, -+ struct yaffs_file_var *file_struct, -+ u32 chunk_id, -+ struct yaffs_tnode *passed_tn) -+{ -+ int required_depth; -+ int i; -+ int l; -+ struct yaffs_tnode *tn; -+ -+ u32 x; -+ -+ /* Check sane level and page Id */ -+ if (file_struct->top_level < 0 -+ || file_struct->top_level > YAFFS_TNODES_MAX_LEVEL) -+ return NULL; -+ -+ if (chunk_id > YAFFS_MAX_CHUNK_ID) -+ return NULL; -+ -+ /* First check we're tall enough (ie enough top_level) */ -+ -+ x = chunk_id >> YAFFS_TNODES_LEVEL0_BITS; -+ required_depth = 0; -+ while (x) { -+ x >>= YAFFS_TNODES_INTERNAL_BITS; -+ required_depth++; -+ } -+ -+ if (required_depth > file_struct->top_level) { -+ /* Not tall enough, gotta make the tree taller */ -+ for (i = file_struct->top_level; i < required_depth; i++) { -+ -+ tn = yaffs_get_tnode(dev); -+ -+ if (tn) { -+ tn->internal[0] = file_struct->top; -+ file_struct->top = tn; -+ file_struct->top_level++; -+ } else { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR("yaffs: no more tnodes" TENDSTR))); -+ return NULL; -+ } -+ } -+ } -+ -+ /* Traverse down to level 0, adding anything we need */ -+ -+ l = file_struct->top_level; -+ tn = file_struct->top; -+ -+ if (l > 0) { -+ while (l > 0 && tn) { -+ x = (chunk_id >> -+ (YAFFS_TNODES_LEVEL0_BITS + -+ (l - 1) * YAFFS_TNODES_INTERNAL_BITS)) & -+ YAFFS_TNODES_INTERNAL_MASK; -+ -+ if ((l > 1) && !tn->internal[x]) { -+ /* Add missing non-level-zero tnode */ -+ tn->internal[x] = yaffs_get_tnode(dev); -+ if (!tn->internal[x]) -+ return NULL; -+ } else if (l == 1) { -+ /* Looking from level 1 at level 0 */ -+ if (passed_tn) { -+ /* If we already have one, then release it. */ -+ if (tn->internal[x]) -+ yaffs_free_tnode(dev, -+ tn-> -+ internal[x]); -+ tn->internal[x] = passed_tn; -+ -+ } else if (!tn->internal[x]) { -+ /* Don't have one, none passed in */ -+ tn->internal[x] = yaffs_get_tnode(dev); -+ if (!tn->internal[x]) -+ return NULL; -+ } -+ } -+ -+ tn = tn->internal[x]; -+ l--; -+ } -+ } else { -+ /* top is level 0 */ -+ if (passed_tn) { -+ memcpy(tn, passed_tn, -+ (dev->tnode_width * YAFFS_NTNODES_LEVEL0) / 8); -+ yaffs_free_tnode(dev, passed_tn); -+ } -+ } -+ -+ return tn; -+} -+ -+static int yaffs_find_chunk_in_group(struct yaffs_dev *dev, int the_chunk, -+ struct yaffs_ext_tags *tags, int obj_id, -+ int inode_chunk) -+{ -+ int j; -+ -+ for (j = 0; the_chunk && j < dev->chunk_grp_size; j++) { -+ if (yaffs_check_chunk_bit -+ (dev, the_chunk / dev->param.chunks_per_block, -+ the_chunk % dev->param.chunks_per_block)) { -+ -+ if (dev->chunk_grp_size == 1) -+ return the_chunk; -+ else { -+ yaffs_rd_chunk_tags_nand(dev, the_chunk, NULL, -+ tags); -+ if (yaffs_tags_match(tags, obj_id, inode_chunk)) { -+ /* found it; */ -+ return the_chunk; -+ } -+ } -+ } -+ the_chunk++; -+ } -+ return -1; -+} -+ -+static void yaffs_soft_del_chunk(struct yaffs_dev *dev, int chunk) -+{ -+ struct yaffs_block_info *the_block; -+ unsigned block_no; -+ -+ T(YAFFS_TRACE_DELETION, (TSTR("soft delete chunk %d" TENDSTR), chunk)); -+ -+ block_no = chunk / dev->param.chunks_per_block; -+ the_block = yaffs_get_block_info(dev, block_no); -+ if (the_block) { -+ the_block->soft_del_pages++; -+ dev->n_free_chunks++; -+ yaffs2_update_oldest_dirty_seq(dev, block_no, the_block); -+ } -+} -+ -+/* SoftDeleteWorker scans backwards through the tnode tree and soft deletes all the chunks in the file. -+ * All soft deleting does is increment the block's softdelete count and pulls the chunk out -+ * of the tnode. -+ * Thus, essentially this is the same as DeleteWorker except that the chunks are soft deleted. -+ */ -+ -+static int yaffs_soft_del_worker(struct yaffs_obj *in, struct yaffs_tnode *tn, -+ u32 level, int chunk_offset) -+{ -+ int i; -+ int the_chunk; -+ int all_done = 1; -+ struct yaffs_dev *dev = in->my_dev; -+ -+ if (tn) { -+ if (level > 0) { -+ -+ for (i = YAFFS_NTNODES_INTERNAL - 1; all_done && i >= 0; -+ i--) { -+ if (tn->internal[i]) { -+ all_done = -+ yaffs_soft_del_worker(in, -+ tn->internal -+ [i], -+ level - 1, -+ (chunk_offset -+ << -+ YAFFS_TNODES_INTERNAL_BITS) -+ + i); -+ if (all_done) { -+ yaffs_free_tnode(dev, -+ tn->internal -+ [i]); -+ tn->internal[i] = NULL; -+ } else { -+ /* Hoosterman... how could this happen? */ -+ } -+ } -+ } -+ return (all_done) ? 1 : 0; -+ } else if (level == 0) { -+ -+ for (i = YAFFS_NTNODES_LEVEL0 - 1; i >= 0; i--) { -+ the_chunk = yaffs_get_group_base(dev, tn, i); -+ if (the_chunk) { -+ /* Note this does not find the real chunk, only the chunk group. -+ * We make an assumption that a chunk group is not larger than -+ * a block. -+ */ -+ yaffs_soft_del_chunk(dev, the_chunk); -+ yaffs_load_tnode_0(dev, tn, i, 0); -+ } -+ -+ } -+ return 1; -+ -+ } -+ -+ } -+ -+ return 1; -+ -+} -+ -+static void yaffs_soft_del_file(struct yaffs_obj *obj) -+{ -+ if (obj->deleted && -+ obj->variant_type == YAFFS_OBJECT_TYPE_FILE && !obj->soft_del) { -+ if (obj->n_data_chunks <= 0) { -+ /* Empty file with no duplicate object headers, just delete it immediately */ -+ yaffs_free_tnode(obj->my_dev, -+ obj->variant.file_variant.top); -+ obj->variant.file_variant.top = NULL; -+ T(YAFFS_TRACE_TRACING, -+ (TSTR("yaffs: Deleting empty file %d" TENDSTR), -+ obj->obj_id)); -+ yaffs_generic_obj_del(obj); -+ } else { -+ yaffs_soft_del_worker(obj, -+ obj->variant.file_variant.top, -+ obj->variant. -+ file_variant.top_level, 0); -+ obj->soft_del = 1; -+ } -+ } -+} -+ -+/* Pruning removes any part of the file structure tree that is beyond the -+ * bounds of the file (ie that does not point to chunks). -+ * -+ * A file should only get pruned when its size is reduced. -+ * -+ * Before pruning, the chunks must be pulled from the tree and the -+ * level 0 tnode entries must be zeroed out. -+ * Could also use this for file deletion, but that's probably better handled -+ * by a special case. -+ * -+ * This function is recursive. For levels > 0 the function is called again on -+ * any sub-tree. For level == 0 we just check if the sub-tree has data. -+ * If there is no data in a subtree then it is pruned. -+ */ -+ -+static struct yaffs_tnode *yaffs_prune_worker(struct yaffs_dev *dev, -+ struct yaffs_tnode *tn, u32 level, -+ int del0) -+{ -+ int i; -+ int has_data; -+ -+ if (tn) { -+ has_data = 0; -+ -+ if (level > 0) { -+ for (i = 0; i < YAFFS_NTNODES_INTERNAL; i++) { -+ if (tn->internal[i]) { -+ tn->internal[i] = -+ yaffs_prune_worker(dev, -+ tn->internal[i], -+ level - 1, -+ (i == -+ 0) ? del0 : 1); -+ } -+ -+ if (tn->internal[i]) -+ has_data++; -+ } -+ } else { -+ int tnode_size_u32 = dev->tnode_size / sizeof(u32); -+ u32 *map = (u32 *) tn; -+ -+ for (i = 0; !has_data && i < tnode_size_u32; i++) { -+ if (map[i]) -+ has_data++; -+ } -+ } -+ -+ if (has_data == 0 && del0) { -+ /* Free and return NULL */ -+ -+ yaffs_free_tnode(dev, tn); -+ tn = NULL; -+ } -+ -+ } -+ -+ return tn; -+ -+} -+ -+static int yaffs_prune_tree(struct yaffs_dev *dev, -+ struct yaffs_file_var *file_struct) -+{ -+ int i; -+ int has_data; -+ int done = 0; -+ struct yaffs_tnode *tn; -+ -+ if (file_struct->top_level > 0) { -+ file_struct->top = -+ yaffs_prune_worker(dev, file_struct->top, -+ file_struct->top_level, 0); -+ -+ /* Now we have a tree with all the non-zero branches NULL but the height -+ * is the same as it was. -+ * Let's see if we can trim internal tnodes to shorten the tree. -+ * We can do this if only the 0th element in the tnode is in use -+ * (ie all the non-zero are NULL) -+ */ -+ -+ while (file_struct->top_level && !done) { -+ tn = file_struct->top; -+ -+ has_data = 0; -+ for (i = 1; i < YAFFS_NTNODES_INTERNAL; i++) { -+ if (tn->internal[i]) -+ has_data++; -+ } -+ -+ if (!has_data) { -+ file_struct->top = tn->internal[0]; -+ file_struct->top_level--; -+ yaffs_free_tnode(dev, tn); -+ } else { -+ done = 1; -+ } -+ } -+ } -+ -+ return YAFFS_OK; -+} -+ -+/*-------------------- End of File Structure functions.-------------------*/ -+ -+/* AllocateEmptyObject gets us a clean Object. Tries to make allocate more if we run out */ -+static struct yaffs_obj *yaffs_alloc_empty_obj(struct yaffs_dev *dev) -+{ -+ struct yaffs_obj *obj = yaffs_alloc_raw_obj(dev); -+ -+ if (obj) { -+ dev->n_obj++; -+ -+ /* Now sweeten it up... */ -+ -+ memset(obj, 0, sizeof(struct yaffs_obj)); -+ obj->being_created = 1; -+ -+ obj->my_dev = dev; -+ obj->hdr_chunk = 0; -+ obj->variant_type = YAFFS_OBJECT_TYPE_UNKNOWN; -+ INIT_LIST_HEAD(&(obj->hard_links)); -+ INIT_LIST_HEAD(&(obj->hash_link)); -+ INIT_LIST_HEAD(&obj->siblings); -+ -+ /* Now make the directory sane */ -+ if (dev->root_dir) { -+ obj->parent = dev->root_dir; -+ list_add(&(obj->siblings), -+ &dev->root_dir->variant.dir_variant.children); -+ } -+ -+ /* Add it to the lost and found directory. -+ * NB Can't put root or lost-n-found in lost-n-found so -+ * check if lost-n-found exists first -+ */ -+ if (dev->lost_n_found) -+ yaffs_add_obj_to_dir(dev->lost_n_found, obj); -+ -+ obj->being_created = 0; -+ } -+ -+ dev->checkpoint_blocks_required = 0; /* force recalculation */ -+ -+ return obj; -+} -+ -+static struct yaffs_obj *yaffs_create_fake_dir(struct yaffs_dev *dev, -+ int number, u32 mode) -+{ -+ -+ struct yaffs_obj *obj = -+ yaffs_new_obj(dev, number, YAFFS_OBJECT_TYPE_DIRECTORY); -+ if (obj) { -+ obj->fake = 1; /* it is fake so it might have no NAND presence... */ -+ obj->rename_allowed = 0; /* ... and we're not allowed to rename it... */ -+ obj->unlink_allowed = 0; /* ... or unlink it */ -+ obj->deleted = 0; -+ obj->unlinked = 0; -+ obj->yst_mode = mode; -+ obj->my_dev = dev; -+ obj->hdr_chunk = 0; /* Not a valid chunk. */ -+ } -+ -+ return obj; -+ -+} -+ -+static void yaffs_unhash_obj(struct yaffs_obj *obj) -+{ -+ int bucket; -+ struct yaffs_dev *dev = obj->my_dev; -+ -+ /* If it is still linked into the bucket list, free from the list */ -+ if (!list_empty(&obj->hash_link)) { -+ list_del_init(&obj->hash_link); -+ bucket = yaffs_hash_fn(obj->obj_id); -+ dev->obj_bucket[bucket].count--; -+ } -+} -+ -+/* FreeObject frees up a Object and puts it back on the free list */ -+static void yaffs_free_obj(struct yaffs_obj *obj) -+{ -+ struct yaffs_dev *dev = obj->my_dev; -+ -+ T(YAFFS_TRACE_OS, -+ (TSTR("FreeObject %p inode %p" TENDSTR), obj, obj->my_inode)); -+ -+ if (!obj) -+ YBUG(); -+ if (obj->parent) -+ YBUG(); -+ if (!list_empty(&obj->siblings)) -+ YBUG(); -+ -+ if (obj->my_inode) { -+ /* We're still hooked up to a cached inode. -+ * Don't delete now, but mark for later deletion -+ */ -+ obj->defered_free = 1; -+ return; -+ } -+ -+ yaffs_unhash_obj(obj); -+ -+ yaffs_free_raw_obj(dev, obj); -+ dev->n_obj--; -+ dev->checkpoint_blocks_required = 0; /* force recalculation */ -+} -+ -+void yaffs_handle_defered_free(struct yaffs_obj *obj) -+{ -+ if (obj->defered_free) -+ yaffs_free_obj(obj); -+} -+ -+static void yaffs_init_tnodes_and_objs(struct yaffs_dev *dev) -+{ -+ int i; -+ -+ dev->n_obj = 0; -+ dev->n_tnodes = 0; -+ -+ yaffs_init_raw_tnodes_and_objs(dev); -+ -+ for (i = 0; i < YAFFS_NOBJECT_BUCKETS; i++) { -+ INIT_LIST_HEAD(&dev->obj_bucket[i].list); -+ dev->obj_bucket[i].count = 0; -+ } -+} -+ -+static int yaffs_find_nice_bucket(struct yaffs_dev *dev) -+{ -+ int i; -+ int l = 999; -+ int lowest = 999999; -+ -+ /* Search for the shortest list or one that -+ * isn't too long. -+ */ -+ -+ for (i = 0; i < 10 && lowest > 4; i++) { -+ dev->bucket_finder++; -+ dev->bucket_finder %= YAFFS_NOBJECT_BUCKETS; -+ if (dev->obj_bucket[dev->bucket_finder].count < lowest) { -+ lowest = dev->obj_bucket[dev->bucket_finder].count; -+ l = dev->bucket_finder; -+ } -+ -+ } -+ -+ return l; -+} -+ -+static int yaffs_new_obj_id(struct yaffs_dev *dev) -+{ -+ int bucket = yaffs_find_nice_bucket(dev); -+ -+ /* Now find an object value that has not already been taken -+ * by scanning the list. -+ */ -+ -+ int found = 0; -+ struct list_head *i; -+ -+ u32 n = (u32) bucket; -+ -+ /* yaffs_check_obj_hash_sane(); */ -+ -+ while (!found) { -+ found = 1; -+ n += YAFFS_NOBJECT_BUCKETS; -+ if (1 || dev->obj_bucket[bucket].count > 0) { -+ list_for_each(i, &dev->obj_bucket[bucket].list) { -+ /* If there is already one in the list */ -+ if (i && list_entry(i, struct yaffs_obj, -+ hash_link)->obj_id == n) { -+ found = 0; -+ } -+ } -+ } -+ } -+ -+ return n; -+} -+ -+static void yaffs_hash_obj(struct yaffs_obj *in) -+{ -+ int bucket = yaffs_hash_fn(in->obj_id); -+ struct yaffs_dev *dev = in->my_dev; -+ -+ list_add(&in->hash_link, &dev->obj_bucket[bucket].list); -+ dev->obj_bucket[bucket].count++; -+} -+ -+struct yaffs_obj *yaffs_find_by_number(struct yaffs_dev *dev, u32 number) -+{ -+ int bucket = yaffs_hash_fn(number); -+ struct list_head *i; -+ struct yaffs_obj *in; -+ -+ list_for_each(i, &dev->obj_bucket[bucket].list) { -+ /* Look if it is in the list */ -+ if (i) { -+ in = list_entry(i, struct yaffs_obj, hash_link); -+ if (in->obj_id == number) { -+ -+ /* Don't tell the VFS about this one if it is defered free */ -+ if (in->defered_free) -+ return NULL; -+ -+ return in; -+ } -+ } -+ } -+ -+ return NULL; -+} -+ -+struct yaffs_obj *yaffs_new_obj(struct yaffs_dev *dev, int number, -+ enum yaffs_obj_type type) -+{ -+ struct yaffs_obj *the_obj = NULL; -+ struct yaffs_tnode *tn = NULL; -+ -+ if (number < 0) -+ number = yaffs_new_obj_id(dev); -+ -+ if (type == YAFFS_OBJECT_TYPE_FILE) { -+ tn = yaffs_get_tnode(dev); -+ if (!tn) -+ return NULL; -+ } -+ -+ the_obj = yaffs_alloc_empty_obj(dev); -+ if (!the_obj) { -+ if (tn) -+ yaffs_free_tnode(dev, tn); -+ return NULL; -+ } -+ -+ if (the_obj) { -+ the_obj->fake = 0; -+ the_obj->rename_allowed = 1; -+ the_obj->unlink_allowed = 1; -+ the_obj->obj_id = number; -+ yaffs_hash_obj(the_obj); -+ the_obj->variant_type = type; -+ yaffs_load_current_time(the_obj, 1, 1); -+ -+ switch (type) { -+ case YAFFS_OBJECT_TYPE_FILE: -+ the_obj->variant.file_variant.file_size = 0; -+ the_obj->variant.file_variant.scanned_size = 0; -+ the_obj->variant.file_variant.shrink_size = ~0; /* max */ -+ the_obj->variant.file_variant.top_level = 0; -+ the_obj->variant.file_variant.top = tn; -+ break; -+ case YAFFS_OBJECT_TYPE_DIRECTORY: -+ INIT_LIST_HEAD(&the_obj->variant.dir_variant.children); -+ INIT_LIST_HEAD(&the_obj->variant.dir_variant.dirty); -+ break; -+ case YAFFS_OBJECT_TYPE_SYMLINK: -+ case YAFFS_OBJECT_TYPE_HARDLINK: -+ case YAFFS_OBJECT_TYPE_SPECIAL: -+ /* No action required */ -+ break; -+ case YAFFS_OBJECT_TYPE_UNKNOWN: -+ /* todo this should not happen */ -+ break; -+ } -+ } -+ -+ return the_obj; -+} -+ -+struct yaffs_obj *yaffs_find_or_create_by_number(struct yaffs_dev *dev, -+ int number, -+ enum yaffs_obj_type type) -+{ -+ struct yaffs_obj *the_obj = NULL; -+ -+ if (number > 0) -+ the_obj = yaffs_find_by_number(dev, number); -+ -+ if (!the_obj) -+ the_obj = yaffs_new_obj(dev, number, type); -+ -+ return the_obj; -+ -+} -+ -+YCHAR *yaffs_clone_str(const YCHAR * str) -+{ -+ YCHAR *new_str = NULL; -+ int len; -+ -+ if (!str) -+ str = _Y(""); -+ -+ len = yaffs_strnlen(str, YAFFS_MAX_ALIAS_LENGTH); -+ new_str = YMALLOC((len + 1) * sizeof(YCHAR)); -+ if (new_str) { -+ yaffs_strncpy(new_str, str, len); -+ new_str[len] = 0; -+ } -+ return new_str; -+ -+} -+ -+/* -+ * Mknod (create) a new object. -+ * equiv_obj only has meaning for a hard link; -+ * alias_str only has meaning for a symlink. -+ * rdev only has meaning for devices (a subset of special objects) -+ */ -+ -+static struct yaffs_obj *yaffs_create_obj(enum yaffs_obj_type type, -+ struct yaffs_obj *parent, -+ const YCHAR * name, -+ u32 mode, -+ u32 uid, -+ u32 gid, -+ struct yaffs_obj *equiv_obj, -+ const YCHAR * alias_str, u32 rdev) -+{ -+ struct yaffs_obj *in; -+ YCHAR *str = NULL; -+ -+ struct yaffs_dev *dev = parent->my_dev; -+ -+ /* Check if the entry exists. If it does then fail the call since we don't want a dup. */ -+ if (yaffs_find_by_name(parent, name)) -+ return NULL; -+ -+ if (type == YAFFS_OBJECT_TYPE_SYMLINK) { -+ str = yaffs_clone_str(alias_str); -+ if (!str) -+ return NULL; -+ } -+ -+ in = yaffs_new_obj(dev, -1, type); -+ -+ if (!in) { -+ if (str) -+ YFREE(str); -+ return NULL; -+ } -+ -+ if (in) { -+ in->hdr_chunk = 0; -+ in->valid = 1; -+ in->variant_type = type; -+ -+ in->yst_mode = mode; -+ -+ yaffs_attribs_init(in, gid, uid, rdev); -+ -+ in->n_data_chunks = 0; -+ -+ yaffs_set_obj_name(in, name); -+ in->dirty = 1; -+ -+ yaffs_add_obj_to_dir(parent, in); -+ -+ in->my_dev = parent->my_dev; -+ -+ switch (type) { -+ case YAFFS_OBJECT_TYPE_SYMLINK: -+ in->variant.symlink_variant.alias = str; -+ break; -+ case YAFFS_OBJECT_TYPE_HARDLINK: -+ in->variant.hardlink_variant.equiv_obj = equiv_obj; -+ in->variant.hardlink_variant.equiv_id = -+ equiv_obj->obj_id; -+ list_add(&in->hard_links, &equiv_obj->hard_links); -+ break; -+ case YAFFS_OBJECT_TYPE_FILE: -+ case YAFFS_OBJECT_TYPE_DIRECTORY: -+ case YAFFS_OBJECT_TYPE_SPECIAL: -+ case YAFFS_OBJECT_TYPE_UNKNOWN: -+ /* do nothing */ -+ break; -+ } -+ -+ if (yaffs_update_oh(in, name, 0, 0, 0, NULL) < 0) { -+ /* Could not create the object header, fail the creation */ -+ yaffs_del_obj(in); -+ in = NULL; -+ } -+ -+ yaffs_update_parent(parent); -+ } -+ -+ return in; -+} -+ -+struct yaffs_obj *yaffs_create_file(struct yaffs_obj *parent, -+ const YCHAR * name, u32 mode, u32 uid, -+ u32 gid) -+{ -+ return yaffs_create_obj(YAFFS_OBJECT_TYPE_FILE, parent, name, mode, -+ uid, gid, NULL, NULL, 0); -+} -+ -+struct yaffs_obj *yaffs_create_dir(struct yaffs_obj *parent, const YCHAR * name, -+ u32 mode, u32 uid, u32 gid) -+{ -+ return yaffs_create_obj(YAFFS_OBJECT_TYPE_DIRECTORY, parent, name, -+ mode, uid, gid, NULL, NULL, 0); -+} -+ -+struct yaffs_obj *yaffs_create_special(struct yaffs_obj *parent, -+ const YCHAR * name, u32 mode, u32 uid, -+ u32 gid, u32 rdev) -+{ -+ return yaffs_create_obj(YAFFS_OBJECT_TYPE_SPECIAL, parent, name, mode, -+ uid, gid, NULL, NULL, rdev); -+} -+ -+struct yaffs_obj *yaffs_create_symlink(struct yaffs_obj *parent, -+ const YCHAR * name, u32 mode, u32 uid, -+ u32 gid, const YCHAR * alias) -+{ -+ return yaffs_create_obj(YAFFS_OBJECT_TYPE_SYMLINK, parent, name, mode, -+ uid, gid, NULL, alias, 0); -+} -+ -+/* yaffs_link_obj returns the object id of the equivalent object.*/ -+struct yaffs_obj *yaffs_link_obj(struct yaffs_obj *parent, const YCHAR * name, -+ struct yaffs_obj *equiv_obj) -+{ -+ /* Get the real object in case we were fed a hard link as an equivalent object */ -+ equiv_obj = yaffs_get_equivalent_obj(equiv_obj); -+ -+ if (yaffs_create_obj -+ (YAFFS_OBJECT_TYPE_HARDLINK, parent, name, 0, 0, 0, -+ equiv_obj, NULL, 0)) { -+ return equiv_obj; -+ } else { -+ return NULL; -+ } -+ -+} -+ -+static int yaffs_change_obj_name(struct yaffs_obj *obj, -+ struct yaffs_obj *new_dir, -+ const YCHAR * new_name, int force, int shadows) -+{ -+ int unlink_op; -+ int del_op; -+ -+ struct yaffs_obj *existing_target; -+ -+ if (new_dir == NULL) -+ new_dir = obj->parent; /* use the old directory */ -+ -+ if (new_dir->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) { -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR -+ ("tragedy: yaffs_change_obj_name: new_dir is not a directory" -+ TENDSTR))); -+ YBUG(); -+ } -+ -+ /* TODO: Do we need this different handling for YAFFS2 and YAFFS1?? */ -+ if (obj->my_dev->param.is_yaffs2) -+ unlink_op = (new_dir == obj->my_dev->unlinked_dir); -+ else -+ unlink_op = (new_dir == obj->my_dev->unlinked_dir -+ && obj->variant_type == YAFFS_OBJECT_TYPE_FILE); -+ -+ del_op = (new_dir == obj->my_dev->del_dir); -+ -+ existing_target = yaffs_find_by_name(new_dir, new_name); -+ -+ /* If the object is a file going into the unlinked directory, -+ * then it is OK to just stuff it in since duplicate names are allowed. -+ * else only proceed if the new name does not exist and if we're putting -+ * it into a directory. -+ */ -+ if ((unlink_op || -+ del_op || -+ force || -+ (shadows > 0) || -+ !existing_target) && -+ new_dir->variant_type == YAFFS_OBJECT_TYPE_DIRECTORY) { -+ yaffs_set_obj_name(obj, new_name); -+ obj->dirty = 1; -+ -+ yaffs_add_obj_to_dir(new_dir, obj); -+ -+ if (unlink_op) -+ obj->unlinked = 1; -+ -+ /* If it is a deletion then we mark it as a shrink for gc purposes. */ -+ if (yaffs_update_oh(obj, new_name, 0, del_op, shadows, NULL) >= -+ 0) -+ return YAFFS_OK; -+ } -+ -+ return YAFFS_FAIL; -+} -+ -+int yaffs_rename_obj(struct yaffs_obj *old_dir, const YCHAR * old_name, -+ struct yaffs_obj *new_dir, const YCHAR * new_name) -+{ -+ struct yaffs_obj *obj = NULL; -+ struct yaffs_obj *existing_target = NULL; -+ int force = 0; -+ int result; -+ struct yaffs_dev *dev; -+ -+ if (!old_dir || old_dir->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) -+ YBUG(); -+ if (!new_dir || new_dir->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) -+ YBUG(); -+ -+ dev = old_dir->my_dev; -+ -+#ifdef CONFIG_YAFFS_CASE_INSENSITIVE -+ /* Special case for case insemsitive systems. -+ * While look-up is case insensitive, the name isn't. -+ * Therefore we might want to change x.txt to X.txt -+ */ -+ if (old_dir == new_dir && yaffs_strcmp(old_name, new_name) == 0) -+ force = 1; -+#endif -+ -+ if (yaffs_strnlen(new_name, YAFFS_MAX_NAME_LENGTH + 1) > -+ YAFFS_MAX_NAME_LENGTH) -+ /* ENAMETOOLONG */ -+ return YAFFS_FAIL; -+ -+ obj = yaffs_find_by_name(old_dir, old_name); -+ -+ if (obj && obj->rename_allowed) { -+ -+ /* Now do the handling for an existing target, if there is one */ -+ -+ existing_target = yaffs_find_by_name(new_dir, new_name); -+ if (existing_target && -+ existing_target->variant_type == YAFFS_OBJECT_TYPE_DIRECTORY -+ && !list_empty(&existing_target->variant.dir_variant. -+ children)) { -+ /* There is a target that is a non-empty directory, so we fail */ -+ return YAFFS_FAIL; /* EEXIST or ENOTEMPTY */ -+ } else if (existing_target && existing_target != obj) { -+ /* Nuke the target first, using shadowing, -+ * but only if it isn't the same object. -+ * -+ * Note we must disable gc otherwise it can mess up the shadowing. -+ * -+ */ -+ dev->gc_disable = 1; -+ yaffs_change_obj_name(obj, new_dir, new_name, force, -+ existing_target->obj_id); -+ existing_target->is_shadowed = 1; -+ yaffs_unlink_obj(existing_target); -+ dev->gc_disable = 0; -+ } -+ -+ result = yaffs_change_obj_name(obj, new_dir, new_name, 1, 0); -+ -+ yaffs_update_parent(old_dir); -+ if (new_dir != old_dir) -+ yaffs_update_parent(new_dir); -+ -+ return result; -+ } -+ return YAFFS_FAIL; -+} -+ -+/*------------------------- Block Management and Page Allocation ----------------*/ -+ -+static int yaffs_init_blocks(struct yaffs_dev *dev) -+{ -+ int n_blocks = dev->internal_end_block - dev->internal_start_block + 1; -+ -+ dev->block_info = NULL; -+ dev->chunk_bits = NULL; -+ -+ dev->alloc_block = -1; /* force it to get a new one */ -+ -+ /* If the first allocation strategy fails, thry the alternate one */ -+ dev->block_info = YMALLOC(n_blocks * sizeof(struct yaffs_block_info)); -+ if (!dev->block_info) { -+ dev->block_info = -+ YMALLOC_ALT(n_blocks * sizeof(struct yaffs_block_info)); -+ dev->block_info_alt = 1; -+ } else { -+ dev->block_info_alt = 0; -+ } -+ -+ if (dev->block_info) { -+ /* Set up dynamic blockinfo stuff. */ -+ dev->chunk_bit_stride = (dev->param.chunks_per_block + 7) / 8; /* round up bytes */ -+ dev->chunk_bits = YMALLOC(dev->chunk_bit_stride * n_blocks); -+ if (!dev->chunk_bits) { -+ dev->chunk_bits = -+ YMALLOC_ALT(dev->chunk_bit_stride * n_blocks); -+ dev->chunk_bits_alt = 1; -+ } else { -+ dev->chunk_bits_alt = 0; -+ } -+ } -+ -+ if (dev->block_info && dev->chunk_bits) { -+ memset(dev->block_info, 0, -+ n_blocks * sizeof(struct yaffs_block_info)); -+ memset(dev->chunk_bits, 0, dev->chunk_bit_stride * n_blocks); -+ return YAFFS_OK; -+ } -+ -+ return YAFFS_FAIL; -+} -+ -+static void yaffs_deinit_blocks(struct yaffs_dev *dev) -+{ -+ if (dev->block_info_alt && dev->block_info) -+ YFREE_ALT(dev->block_info); -+ else if (dev->block_info) -+ YFREE(dev->block_info); -+ -+ dev->block_info_alt = 0; -+ -+ dev->block_info = NULL; -+ -+ if (dev->chunk_bits_alt && dev->chunk_bits) -+ YFREE_ALT(dev->chunk_bits); -+ else if (dev->chunk_bits) -+ YFREE(dev->chunk_bits); -+ dev->chunk_bits_alt = 0; -+ dev->chunk_bits = NULL; -+} -+ -+void yaffs_block_became_dirty(struct yaffs_dev *dev, int block_no) -+{ -+ struct yaffs_block_info *bi = yaffs_get_block_info(dev, block_no); -+ -+ int erased_ok = 0; -+ -+ /* If the block is still healthy erase it and mark as clean. -+ * If the block has had a data failure, then retire it. -+ */ -+ -+ T(YAFFS_TRACE_GC | YAFFS_TRACE_ERASE, -+ (TSTR("yaffs_block_became_dirty block %d state %d %s" TENDSTR), -+ block_no, bi->block_state, -+ (bi->needs_retiring) ? "needs retiring" : "")); -+ -+ yaffs2_clear_oldest_dirty_seq(dev, bi); -+ -+ bi->block_state = YAFFS_BLOCK_STATE_DIRTY; -+ -+ /* If this is the block being garbage collected then stop gc'ing this block */ -+ if (block_no == dev->gc_block) -+ dev->gc_block = 0; -+ -+ /* If this block is currently the best candidate for gc then drop as a candidate */ -+ if (block_no == dev->gc_dirtiest) { -+ dev->gc_dirtiest = 0; -+ dev->gc_pages_in_use = 0; -+ } -+ -+ if (!bi->needs_retiring) { -+ yaffs2_checkpt_invalidate(dev); -+ erased_ok = yaffs_erase_block(dev, block_no); -+ if (!erased_ok) { -+ dev->n_erase_failures++; -+ T(YAFFS_TRACE_ERROR | YAFFS_TRACE_BAD_BLOCKS, -+ (TSTR("**>> Erasure failed %d" TENDSTR), block_no)); -+ } -+ } -+ -+ if (erased_ok && -+ ((yaffs_trace_mask & YAFFS_TRACE_ERASE) -+ || !yaffs_skip_verification(dev))) { -+ int i; -+ for (i = 0; i < dev->param.chunks_per_block; i++) { -+ if (!yaffs_check_chunk_erased -+ (dev, block_no * dev->param.chunks_per_block + i)) { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR -+ (">>Block %d erasure supposedly OK, but chunk %d not erased" -+ TENDSTR), block_no, i)); -+ } -+ } -+ } -+ -+ if (erased_ok) { -+ /* Clean it up... */ -+ bi->block_state = YAFFS_BLOCK_STATE_EMPTY; -+ bi->seq_number = 0; -+ dev->n_erased_blocks++; -+ bi->pages_in_use = 0; -+ bi->soft_del_pages = 0; -+ bi->has_shrink_hdr = 0; -+ bi->skip_erased_check = 1; /* This is clean, so no need to check */ -+ bi->gc_prioritise = 0; -+ yaffs_clear_chunk_bits(dev, block_no); -+ -+ T(YAFFS_TRACE_ERASE, -+ (TSTR("Erased block %d" TENDSTR), block_no)); -+ } else { -+ dev->n_free_chunks -= dev->param.chunks_per_block; /* We lost a block of free space */ -+ -+ yaffs_retire_block(dev, block_no); -+ T(YAFFS_TRACE_ERROR | YAFFS_TRACE_BAD_BLOCKS, -+ (TSTR("**>> Block %d retired" TENDSTR), block_no)); -+ } -+} -+ -+static int yaffs_find_alloc_block(struct yaffs_dev *dev) -+{ -+ int i; -+ -+ struct yaffs_block_info *bi; -+ -+ if (dev->n_erased_blocks < 1) { -+ /* Hoosterman we've got a problem. -+ * Can't get space to gc -+ */ -+ T(YAFFS_TRACE_ERROR, -+ (TSTR("yaffs tragedy: no more erased blocks" TENDSTR))); -+ -+ return -1; -+ } -+ -+ /* Find an empty block. */ -+ -+ for (i = dev->internal_start_block; i <= dev->internal_end_block; i++) { -+ dev->alloc_block_finder++; -+ if (dev->alloc_block_finder < dev->internal_start_block -+ || dev->alloc_block_finder > dev->internal_end_block) { -+ dev->alloc_block_finder = dev->internal_start_block; -+ } -+ -+ bi = yaffs_get_block_info(dev, dev->alloc_block_finder); -+ -+ if (bi->block_state == YAFFS_BLOCK_STATE_EMPTY) { -+ bi->block_state = YAFFS_BLOCK_STATE_ALLOCATING; -+ dev->seq_number++; -+ bi->seq_number = dev->seq_number; -+ dev->n_erased_blocks--; -+ T(YAFFS_TRACE_ALLOCATE, -+ (TSTR("Allocated block %d, seq %d, %d left" TENDSTR), -+ dev->alloc_block_finder, dev->seq_number, -+ dev->n_erased_blocks)); -+ return dev->alloc_block_finder; -+ } -+ } -+ -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR -+ ("yaffs tragedy: no more erased blocks, but there should have been %d" -+ TENDSTR), dev->n_erased_blocks)); -+ -+ return -1; -+} -+ -+/* -+ * Check if there's space to allocate... -+ * Thinks.... do we need top make this ths same as yaffs_get_free_chunks()? -+ */ -+int yaffs_check_alloc_available(struct yaffs_dev *dev, int n_chunks) -+{ -+ int reserved_chunks; -+ int reserved_blocks = dev->param.n_reserved_blocks; -+ int checkpt_blocks; -+ -+ checkpt_blocks = yaffs_calc_checkpt_blocks_required(dev); -+ -+ reserved_chunks = -+ ((reserved_blocks + checkpt_blocks) * dev->param.chunks_per_block); -+ -+ return (dev->n_free_chunks > (reserved_chunks + n_chunks)); -+} -+ -+static int yaffs_alloc_chunk(struct yaffs_dev *dev, int use_reserver, -+ struct yaffs_block_info **block_ptr) -+{ -+ int ret_val; -+ struct yaffs_block_info *bi; -+ -+ if (dev->alloc_block < 0) { -+ /* Get next block to allocate off */ -+ dev->alloc_block = yaffs_find_alloc_block(dev); -+ dev->alloc_page = 0; -+ } -+ -+ if (!use_reserver && !yaffs_check_alloc_available(dev, 1)) { -+ /* Not enough space to allocate unless we're allowed to use the reserve. */ -+ return -1; -+ } -+ -+ if (dev->n_erased_blocks < dev->param.n_reserved_blocks -+ && dev->alloc_page == 0) { -+ T(YAFFS_TRACE_ALLOCATE, (TSTR("Allocating reserve" TENDSTR))); -+ } -+ -+ /* Next page please.... */ -+ if (dev->alloc_block >= 0) { -+ bi = yaffs_get_block_info(dev, dev->alloc_block); -+ -+ ret_val = (dev->alloc_block * dev->param.chunks_per_block) + -+ dev->alloc_page; -+ bi->pages_in_use++; -+ yaffs_set_chunk_bit(dev, dev->alloc_block, dev->alloc_page); -+ -+ dev->alloc_page++; -+ -+ dev->n_free_chunks--; -+ -+ /* If the block is full set the state to full */ -+ if (dev->alloc_page >= dev->param.chunks_per_block) { -+ bi->block_state = YAFFS_BLOCK_STATE_FULL; -+ dev->alloc_block = -1; -+ } -+ -+ if (block_ptr) -+ *block_ptr = bi; -+ -+ return ret_val; -+ } -+ -+ T(YAFFS_TRACE_ERROR, -+ (TSTR("!!!!!!!!! Allocator out !!!!!!!!!!!!!!!!!" TENDSTR))); -+ -+ return -1; -+} -+ -+static int yaffs_get_erased_chunks(struct yaffs_dev *dev) -+{ -+ int n; -+ -+ n = dev->n_erased_blocks * dev->param.chunks_per_block; -+ -+ if (dev->alloc_block > 0) -+ n += (dev->param.chunks_per_block - dev->alloc_page); -+ -+ return n; -+ -+} -+ -+/* -+ * yaffs_skip_rest_of_block() skips over the rest of the allocation block -+ * if we don't want to write to it. -+ */ -+void yaffs_skip_rest_of_block(struct yaffs_dev *dev) -+{ -+ if (dev->alloc_block > 0) { -+ struct yaffs_block_info *bi = -+ yaffs_get_block_info(dev, dev->alloc_block); -+ if (bi->block_state == YAFFS_BLOCK_STATE_ALLOCATING) { -+ bi->block_state = YAFFS_BLOCK_STATE_FULL; -+ dev->alloc_block = -1; -+ } -+ } -+} -+ -+static int yaffs_gc_block(struct yaffs_dev *dev, int block, int whole_block) -+{ -+ int old_chunk; -+ int new_chunk; -+ int mark_flash; -+ int ret_val = YAFFS_OK; -+ int i; -+ int is_checkpt_block; -+ int matching_chunk; -+ int max_copies; -+ -+ int chunks_before = yaffs_get_erased_chunks(dev); -+ int chunks_after; -+ -+ struct yaffs_ext_tags tags; -+ -+ struct yaffs_block_info *bi = yaffs_get_block_info(dev, block); -+ -+ struct yaffs_obj *object; -+ -+ is_checkpt_block = (bi->block_state == YAFFS_BLOCK_STATE_CHECKPOINT); -+ -+ T(YAFFS_TRACE_TRACING, -+ (TSTR -+ ("Collecting block %d, in use %d, shrink %d, whole_block %d" -+ TENDSTR), block, bi->pages_in_use, bi->has_shrink_hdr, -+ whole_block)); -+ -+ /*yaffs_verify_free_chunks(dev); */ -+ -+ if (bi->block_state == YAFFS_BLOCK_STATE_FULL) -+ bi->block_state = YAFFS_BLOCK_STATE_COLLECTING; -+ -+ bi->has_shrink_hdr = 0; /* clear the flag so that the block can erase */ -+ -+ dev->gc_disable = 1; -+ -+ if (is_checkpt_block || !yaffs_still_some_chunks(dev, block)) { -+ T(YAFFS_TRACE_TRACING, -+ (TSTR -+ ("Collecting block %d that has no chunks in use" TENDSTR), -+ block)); -+ yaffs_block_became_dirty(dev, block); -+ } else { -+ -+ u8 *buffer = yaffs_get_temp_buffer(dev, __LINE__); -+ -+ yaffs_verify_blk(dev, bi, block); -+ -+ max_copies = (whole_block) ? dev->param.chunks_per_block : 5; -+ old_chunk = block * dev->param.chunks_per_block + dev->gc_chunk; -+ -+ for ( /* init already done */ ; -+ ret_val == YAFFS_OK && -+ dev->gc_chunk < dev->param.chunks_per_block && -+ (bi->block_state == YAFFS_BLOCK_STATE_COLLECTING) && -+ max_copies > 0; dev->gc_chunk++, old_chunk++) { -+ if (yaffs_check_chunk_bit(dev, block, dev->gc_chunk)) { -+ -+ /* This page is in use and might need to be copied off */ -+ -+ max_copies--; -+ -+ mark_flash = 1; -+ -+ yaffs_init_tags(&tags); -+ -+ yaffs_rd_chunk_tags_nand(dev, old_chunk, -+ buffer, &tags); -+ -+ object = yaffs_find_by_number(dev, tags.obj_id); -+ -+ T(YAFFS_TRACE_GC_DETAIL, -+ (TSTR -+ ("Collecting chunk in block %d, %d %d %d " -+ TENDSTR), dev->gc_chunk, tags.obj_id, -+ tags.chunk_id, tags.n_bytes)); -+ -+ if (object && !yaffs_skip_verification(dev)) { -+ if (tags.chunk_id == 0) -+ matching_chunk = -+ object->hdr_chunk; -+ else if (object->soft_del) -+ matching_chunk = old_chunk; /* Defeat the test */ -+ else -+ matching_chunk = -+ yaffs_find_chunk_in_file -+ (object, tags.chunk_id, -+ NULL); -+ -+ if (old_chunk != matching_chunk) -+ T(YAFFS_TRACE_ERROR, -+ (TSTR -+ ("gc: page in gc mismatch: %d %d %d %d" -+ TENDSTR), old_chunk, -+ matching_chunk, tags.obj_id, -+ tags.chunk_id)); -+ -+ } -+ -+ if (!object) { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR -+ ("page %d in gc has no object: %d %d %d " -+ TENDSTR), old_chunk, -+ tags.obj_id, tags.chunk_id, -+ tags.n_bytes)); -+ } -+ -+ if (object && -+ object->deleted && -+ object->soft_del && tags.chunk_id != 0) { -+ /* Data chunk in a soft deleted file, throw it away -+ * It's a soft deleted data chunk, -+ * No need to copy this, just forget about it and -+ * fix up the object. -+ */ -+ -+ /* Free chunks already includes softdeleted chunks. -+ * How ever this chunk is going to soon be really deleted -+ * which will increment free chunks. -+ * We have to decrement free chunks so this works out properly. -+ */ -+ dev->n_free_chunks--; -+ bi->soft_del_pages--; -+ -+ object->n_data_chunks--; -+ -+ if (object->n_data_chunks <= 0) { -+ /* remeber to clean up the object */ -+ dev->gc_cleanup_list[dev-> -+ n_clean_ups] -+ = tags.obj_id; -+ dev->n_clean_ups++; -+ } -+ mark_flash = 0; -+ } else if (0) { -+ /* Todo object && object->deleted && object->n_data_chunks == 0 */ -+ /* Deleted object header with no data chunks. -+ * Can be discarded and the file deleted. -+ */ -+ object->hdr_chunk = 0; -+ yaffs_free_tnode(object->my_dev, -+ object-> -+ variant.file_variant. -+ top); -+ object->variant.file_variant.top = NULL; -+ yaffs_generic_obj_del(object); -+ -+ } else if (object) { -+ /* It's either a data chunk in a live file or -+ * an ObjectHeader, so we're interested in it. -+ * NB Need to keep the ObjectHeaders of deleted files -+ * until the whole file has been deleted off -+ */ -+ tags.serial_number++; -+ -+ dev->n_gc_copies++; -+ -+ if (tags.chunk_id == 0) { -+ /* It is an object Id, -+ * We need to nuke the shrinkheader flags first -+ * Also need to clean up shadowing. -+ * We no longer want the shrink_header flag since its work is done -+ * and if it is left in place it will mess up scanning. -+ */ -+ -+ struct yaffs_obj_hdr *oh; -+ oh = (struct yaffs_obj_hdr *) -+ buffer; -+ -+ oh->is_shrink = 0; -+ tags.extra_is_shrink = 0; -+ -+ oh->shadows_obj = 0; -+ oh->inband_shadowed_obj_id = 0; -+ tags.extra_shadows = 0; -+ -+ /* Update file size */ -+ if (object->variant_type == -+ YAFFS_OBJECT_TYPE_FILE) { -+ oh->file_size = -+ object->variant. -+ file_variant. -+ file_size; -+ tags.extra_length = -+ oh->file_size; -+ } -+ -+ yaffs_verify_oh(object, oh, -+ &tags, 1); -+ new_chunk = -+ yaffs_write_new_chunk(dev, -+ (u8 *) -+ oh, -+ &tags, -+ 1); -+ } else { -+ new_chunk = -+ yaffs_write_new_chunk(dev, -+ buffer, -+ &tags, -+ 1); -+ } -+ -+ if (new_chunk < 0) { -+ ret_val = YAFFS_FAIL; -+ } else { -+ -+ /* Ok, now fix up the Tnodes etc. */ -+ -+ if (tags.chunk_id == 0) { -+ /* It's a header */ -+ object->hdr_chunk = -+ new_chunk; -+ object->serial = -+ tags.serial_number; -+ } else { -+ /* It's a data chunk */ -+ int ok; -+ ok = yaffs_put_chunk_in_file(object, tags.chunk_id, new_chunk, 0); -+ } -+ } -+ } -+ -+ if (ret_val == YAFFS_OK) -+ yaffs_chunk_del(dev, old_chunk, -+ mark_flash, __LINE__); -+ -+ } -+ } -+ -+ yaffs_release_temp_buffer(dev, buffer, __LINE__); -+ -+ } -+ -+ yaffs_verify_collected_blk(dev, bi, block); -+ -+ if (bi->block_state == YAFFS_BLOCK_STATE_COLLECTING) { -+ /* -+ * The gc did not complete. Set block state back to FULL -+ * because checkpointing does not restore gc. -+ */ -+ bi->block_state = YAFFS_BLOCK_STATE_FULL; -+ } else { -+ /* The gc completed. */ -+ /* Do any required cleanups */ -+ for (i = 0; i < dev->n_clean_ups; i++) { -+ /* Time to delete the file too */ -+ object = -+ yaffs_find_by_number(dev, dev->gc_cleanup_list[i]); -+ if (object) { -+ yaffs_free_tnode(dev, -+ object->variant. -+ file_variant.top); -+ object->variant.file_variant.top = NULL; -+ T(YAFFS_TRACE_GC, -+ (TSTR -+ ("yaffs: About to finally delete object %d" -+ TENDSTR), object->obj_id)); -+ yaffs_generic_obj_del(object); -+ object->my_dev->n_deleted_files--; -+ } -+ -+ } -+ -+ chunks_after = yaffs_get_erased_chunks(dev); -+ if (chunks_before >= chunks_after) { -+ T(YAFFS_TRACE_GC, -+ (TSTR -+ ("gc did not increase free chunks before %d after %d" -+ TENDSTR), chunks_before, chunks_after)); -+ } -+ dev->gc_block = 0; -+ dev->gc_chunk = 0; -+ dev->n_clean_ups = 0; -+ } -+ -+ dev->gc_disable = 0; -+ -+ return ret_val; -+} -+ -+/* -+ * FindBlockForgarbageCollection is used to select the dirtiest block (or close enough) -+ * for garbage collection. -+ */ -+ -+static unsigned yaffs_find_gc_block(struct yaffs_dev *dev, -+ int aggressive, int background) -+{ -+ int i; -+ int iterations; -+ unsigned selected = 0; -+ int prioritised = 0; -+ int prioritised_exist = 0; -+ struct yaffs_block_info *bi; -+ int threshold; -+ -+ /* First let's see if we need to grab a prioritised block */ -+ if (dev->has_pending_prioritised_gc && !aggressive) { -+ dev->gc_dirtiest = 0; -+ bi = dev->block_info; -+ for (i = dev->internal_start_block; -+ i <= dev->internal_end_block && !selected; i++) { -+ -+ if (bi->gc_prioritise) { -+ prioritised_exist = 1; -+ if (bi->block_state == YAFFS_BLOCK_STATE_FULL && -+ yaffs_block_ok_for_gc(dev, bi)) { -+ selected = i; -+ prioritised = 1; -+ } -+ } -+ bi++; -+ } -+ -+ /* -+ * If there is a prioritised block and none was selected then -+ * this happened because there is at least one old dirty block gumming -+ * up the works. Let's gc the oldest dirty block. -+ */ -+ -+ if (prioritised_exist && -+ !selected && dev->oldest_dirty_block > 0) -+ selected = dev->oldest_dirty_block; -+ -+ if (!prioritised_exist) /* None found, so we can clear this */ -+ dev->has_pending_prioritised_gc = 0; -+ } -+ -+ /* If we're doing aggressive GC then we are happy to take a less-dirty block, and -+ * search harder. -+ * else (we're doing a leasurely gc), then we only bother to do this if the -+ * block has only a few pages in use. -+ */ -+ -+ if (!selected) { -+ int pages_used; -+ int n_blocks = -+ dev->internal_end_block - dev->internal_start_block + 1; -+ if (aggressive) { -+ threshold = dev->param.chunks_per_block; -+ iterations = n_blocks; -+ } else { -+ int max_threshold; -+ -+ if (background) -+ max_threshold = dev->param.chunks_per_block / 2; -+ else -+ max_threshold = dev->param.chunks_per_block / 8; -+ -+ if (max_threshold < YAFFS_GC_PASSIVE_THRESHOLD) -+ max_threshold = YAFFS_GC_PASSIVE_THRESHOLD; -+ -+ threshold = background ? (dev->gc_not_done + 2) * 2 : 0; -+ if (threshold < YAFFS_GC_PASSIVE_THRESHOLD) -+ threshold = YAFFS_GC_PASSIVE_THRESHOLD; -+ if (threshold > max_threshold) -+ threshold = max_threshold; -+ -+ iterations = n_blocks / 16 + 1; -+ if (iterations > 100) -+ iterations = 100; -+ } -+ -+ for (i = 0; -+ i < iterations && -+ (dev->gc_dirtiest < 1 || -+ dev->gc_pages_in_use > YAFFS_GC_GOOD_ENOUGH); i++) { -+ dev->gc_block_finder++; -+ if (dev->gc_block_finder < dev->internal_start_block || -+ dev->gc_block_finder > dev->internal_end_block) -+ dev->gc_block_finder = -+ dev->internal_start_block; -+ -+ bi = yaffs_get_block_info(dev, dev->gc_block_finder); -+ -+ pages_used = bi->pages_in_use - bi->soft_del_pages; -+ -+ if (bi->block_state == YAFFS_BLOCK_STATE_FULL && -+ pages_used < dev->param.chunks_per_block && -+ (dev->gc_dirtiest < 1 -+ || pages_used < dev->gc_pages_in_use) -+ && yaffs_block_ok_for_gc(dev, bi)) { -+ dev->gc_dirtiest = dev->gc_block_finder; -+ dev->gc_pages_in_use = pages_used; -+ } -+ } -+ -+ if (dev->gc_dirtiest > 0 && dev->gc_pages_in_use <= threshold) -+ selected = dev->gc_dirtiest; -+ } -+ -+ /* -+ * If nothing has been selected for a while, try selecting the oldest dirty -+ * because that's gumming up the works. -+ */ -+ -+ if (!selected && dev->param.is_yaffs2 && -+ dev->gc_not_done >= (background ? 10 : 20)) { -+ yaffs2_find_oldest_dirty_seq(dev); -+ if (dev->oldest_dirty_block > 0) { -+ selected = dev->oldest_dirty_block; -+ dev->gc_dirtiest = selected; -+ dev->oldest_dirty_gc_count++; -+ bi = yaffs_get_block_info(dev, selected); -+ dev->gc_pages_in_use = -+ bi->pages_in_use - bi->soft_del_pages; -+ } else { -+ dev->gc_not_done = 0; -+ } -+ } -+ -+ if (selected) { -+ T(YAFFS_TRACE_GC, -+ (TSTR -+ ("GC Selected block %d with %d free, prioritised:%d" -+ TENDSTR), selected, -+ dev->param.chunks_per_block - dev->gc_pages_in_use, -+ prioritised)); -+ -+ dev->n_gc_blocks++; -+ if (background) -+ dev->bg_gcs++; -+ -+ dev->gc_dirtiest = 0; -+ dev->gc_pages_in_use = 0; -+ dev->gc_not_done = 0; -+ if (dev->refresh_skip > 0) -+ dev->refresh_skip--; -+ } else { -+ dev->gc_not_done++; -+ T(YAFFS_TRACE_GC, -+ (TSTR -+ ("GC none: finder %d skip %d threshold %d dirtiest %d using %d oldest %d%s" -+ TENDSTR), dev->gc_block_finder, dev->gc_not_done, threshold, -+ dev->gc_dirtiest, dev->gc_pages_in_use, -+ dev->oldest_dirty_block, background ? " bg" : "")); -+ } -+ -+ return selected; -+} -+ -+/* New garbage collector -+ * If we're very low on erased blocks then we do aggressive garbage collection -+ * otherwise we do "leasurely" garbage collection. -+ * Aggressive gc looks further (whole array) and will accept less dirty blocks. -+ * Passive gc only inspects smaller areas and will only accept more dirty blocks. -+ * -+ * The idea is to help clear out space in a more spread-out manner. -+ * Dunno if it really does anything useful. -+ */ -+static int yaffs_check_gc(struct yaffs_dev *dev, int background) -+{ -+ int aggressive = 0; -+ int gc_ok = YAFFS_OK; -+ int max_tries = 0; -+ int min_erased; -+ int erased_chunks; -+ int checkpt_block_adjust; -+ -+ if (dev->param.gc_control && (dev->param.gc_control(dev) & 1) == 0) -+ return YAFFS_OK; -+ -+ if (dev->gc_disable) { -+ /* Bail out so we don't get recursive gc */ -+ return YAFFS_OK; -+ } -+ -+ /* This loop should pass the first time. -+ * We'll only see looping here if the collection does not increase space. -+ */ -+ -+ do { -+ max_tries++; -+ -+ checkpt_block_adjust = yaffs_calc_checkpt_blocks_required(dev); -+ -+ min_erased = -+ dev->param.n_reserved_blocks + checkpt_block_adjust + 1; -+ erased_chunks = -+ dev->n_erased_blocks * dev->param.chunks_per_block; -+ -+ /* If we need a block soon then do aggressive gc. */ -+ if (dev->n_erased_blocks < min_erased) -+ aggressive = 1; -+ else { -+ if (!background -+ && erased_chunks > (dev->n_free_chunks / 4)) -+ break; -+ -+ if (dev->gc_skip > 20) -+ dev->gc_skip = 20; -+ if (erased_chunks < dev->n_free_chunks / 2 || -+ dev->gc_skip < 1 || background) -+ aggressive = 0; -+ else { -+ dev->gc_skip--; -+ break; -+ } -+ } -+ -+ dev->gc_skip = 5; -+ -+ /* If we don't already have a block being gc'd then see if we should start another */ -+ -+ if (dev->gc_block < 1 && !aggressive) { -+ dev->gc_block = yaffs2_find_refresh_block(dev); -+ dev->gc_chunk = 0; -+ dev->n_clean_ups = 0; -+ } -+ if (dev->gc_block < 1) { -+ dev->gc_block = -+ yaffs_find_gc_block(dev, aggressive, background); -+ dev->gc_chunk = 0; -+ dev->n_clean_ups = 0; -+ } -+ -+ if (dev->gc_block > 0) { -+ dev->all_gcs++; -+ if (!aggressive) -+ dev->passive_gc_count++; -+ -+ T(YAFFS_TRACE_GC, -+ (TSTR -+ ("yaffs: GC n_erased_blocks %d aggressive %d" -+ TENDSTR), dev->n_erased_blocks, aggressive)); -+ -+ gc_ok = yaffs_gc_block(dev, dev->gc_block, aggressive); -+ } -+ -+ if (dev->n_erased_blocks < (dev->param.n_reserved_blocks) -+ && dev->gc_block > 0) { -+ T(YAFFS_TRACE_GC, -+ (TSTR -+ ("yaffs: GC !!!no reclaim!!! n_erased_blocks %d after try %d block %d" -+ TENDSTR), dev->n_erased_blocks, max_tries, -+ dev->gc_block)); -+ } -+ } while ((dev->n_erased_blocks < dev->param.n_reserved_blocks) && -+ (dev->gc_block > 0) && (max_tries < 2)); -+ -+ return aggressive ? gc_ok : YAFFS_OK; -+} -+ -+/* -+ * yaffs_bg_gc() -+ * Garbage collects. Intended to be called from a background thread. -+ * Returns non-zero if at least half the free chunks are erased. -+ */ -+int yaffs_bg_gc(struct yaffs_dev *dev, unsigned urgency) -+{ -+ int erased_chunks = dev->n_erased_blocks * dev->param.chunks_per_block; -+ -+ T(YAFFS_TRACE_BACKGROUND, (TSTR("Background gc %u" TENDSTR), urgency)); -+ -+ yaffs_check_gc(dev, 1); -+ return erased_chunks > dev->n_free_chunks / 2; -+} -+ -+/*------------------------- TAGS --------------------------------*/ -+ -+static int yaffs_tags_match(const struct yaffs_ext_tags *tags, int obj_id, -+ int chunk_obj) -+{ -+ return (tags->chunk_id == chunk_obj && -+ tags->obj_id == obj_id && !tags->is_deleted) ? 1 : 0; -+ -+} -+ -+/*-------------------- Data file manipulation -----------------*/ -+ -+static int yaffs_find_chunk_in_file(struct yaffs_obj *in, int inode_chunk, -+ struct yaffs_ext_tags *tags) -+{ -+ /*Get the Tnode, then get the level 0 offset chunk offset */ -+ struct yaffs_tnode *tn; -+ int the_chunk = -1; -+ struct yaffs_ext_tags local_tags; -+ int ret_val = -1; -+ -+ struct yaffs_dev *dev = in->my_dev; -+ -+ if (!tags) { -+ /* Passed a NULL, so use our own tags space */ -+ tags = &local_tags; -+ } -+ -+ tn = yaffs_find_tnode_0(dev, &in->variant.file_variant, inode_chunk); -+ -+ if (tn) { -+ the_chunk = yaffs_get_group_base(dev, tn, inode_chunk); -+ -+ ret_val = -+ yaffs_find_chunk_in_group(dev, the_chunk, tags, in->obj_id, -+ inode_chunk); -+ } -+ return ret_val; -+} -+ -+static int yaffs_find_del_file_chunk(struct yaffs_obj *in, int inode_chunk, -+ struct yaffs_ext_tags *tags) -+{ -+ /* Get the Tnode, then get the level 0 offset chunk offset */ -+ struct yaffs_tnode *tn; -+ int the_chunk = -1; -+ struct yaffs_ext_tags local_tags; -+ -+ struct yaffs_dev *dev = in->my_dev; -+ int ret_val = -1; -+ -+ if (!tags) { -+ /* Passed a NULL, so use our own tags space */ -+ tags = &local_tags; -+ } -+ -+ tn = yaffs_find_tnode_0(dev, &in->variant.file_variant, inode_chunk); -+ -+ if (tn) { -+ -+ the_chunk = yaffs_get_group_base(dev, tn, inode_chunk); -+ -+ ret_val = -+ yaffs_find_chunk_in_group(dev, the_chunk, tags, in->obj_id, -+ inode_chunk); -+ -+ /* Delete the entry in the filestructure (if found) */ -+ if (ret_val != -1) -+ yaffs_load_tnode_0(dev, tn, inode_chunk, 0); -+ } -+ -+ return ret_val; -+} -+ -+int yaffs_put_chunk_in_file(struct yaffs_obj *in, int inode_chunk, -+ int nand_chunk, int in_scan) -+{ -+ /* NB in_scan is zero unless scanning. -+ * For forward scanning, in_scan is > 0; -+ * for backward scanning in_scan is < 0 -+ * -+ * nand_chunk = 0 is a dummy insert to make sure the tnodes are there. -+ */ -+ -+ struct yaffs_tnode *tn; -+ struct yaffs_dev *dev = in->my_dev; -+ int existing_cunk; -+ struct yaffs_ext_tags existing_tags; -+ struct yaffs_ext_tags new_tags; -+ unsigned existing_serial, new_serial; -+ -+ if (in->variant_type != YAFFS_OBJECT_TYPE_FILE) { -+ /* Just ignore an attempt at putting a chunk into a non-file during scanning -+ * If it is not during Scanning then something went wrong! -+ */ -+ if (!in_scan) { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR -+ ("yaffs tragedy:attempt to put data chunk into a non-file" -+ TENDSTR))); -+ YBUG(); -+ } -+ -+ yaffs_chunk_del(dev, nand_chunk, 1, __LINE__); -+ return YAFFS_OK; -+ } -+ -+ tn = yaffs_add_find_tnode_0(dev, -+ &in->variant.file_variant, -+ inode_chunk, NULL); -+ if (!tn) -+ return YAFFS_FAIL; -+ -+ if (!nand_chunk) -+ /* Dummy insert, bail now */ -+ return YAFFS_OK; -+ -+ existing_cunk = yaffs_get_group_base(dev, tn, inode_chunk); -+ -+ if (in_scan != 0) { -+ /* If we're scanning then we need to test for duplicates -+ * NB This does not need to be efficient since it should only ever -+ * happen when the power fails during a write, then only one -+ * chunk should ever be affected. -+ * -+ * Correction for YAFFS2: This could happen quite a lot and we need to think about efficiency! TODO -+ * Update: For backward scanning we don't need to re-read tags so this is quite cheap. -+ */ -+ -+ if (existing_cunk > 0) { -+ /* NB Right now existing chunk will not be real chunk_id if the chunk group size > 1 -+ * thus we have to do a FindChunkInFile to get the real chunk id. -+ * -+ * We have a duplicate now we need to decide which one to use: -+ * -+ * Backwards scanning YAFFS2: The old one is what we use, dump the new one. -+ * Forward scanning YAFFS2: The new one is what we use, dump the old one. -+ * YAFFS1: Get both sets of tags and compare serial numbers. -+ */ -+ -+ if (in_scan > 0) { -+ /* Only do this for forward scanning */ -+ yaffs_rd_chunk_tags_nand(dev, -+ nand_chunk, -+ NULL, &new_tags); -+ -+ /* Do a proper find */ -+ existing_cunk = -+ yaffs_find_chunk_in_file(in, inode_chunk, -+ &existing_tags); -+ } -+ -+ if (existing_cunk <= 0) { -+ /*Hoosterman - how did this happen? */ -+ -+ T(YAFFS_TRACE_ERROR, -+ (TSTR -+ ("yaffs tragedy: existing chunk < 0 in scan" -+ TENDSTR))); -+ -+ } -+ -+ /* NB The deleted flags should be false, otherwise the chunks will -+ * not be loaded during a scan -+ */ -+ -+ if (in_scan > 0) { -+ new_serial = new_tags.serial_number; -+ existing_serial = existing_tags.serial_number; -+ } -+ -+ if ((in_scan > 0) && -+ (existing_cunk <= 0 || -+ ((existing_serial + 1) & 3) == new_serial)) { -+ /* Forward scanning. -+ * Use new -+ * Delete the old one and drop through to update the tnode -+ */ -+ yaffs_chunk_del(dev, existing_cunk, 1, -+ __LINE__); -+ } else { -+ /* Backward scanning or we want to use the existing one -+ * Use existing. -+ * Delete the new one and return early so that the tnode isn't changed -+ */ -+ yaffs_chunk_del(dev, nand_chunk, 1, __LINE__); -+ return YAFFS_OK; -+ } -+ } -+ -+ } -+ -+ if (existing_cunk == 0) -+ in->n_data_chunks++; -+ -+ yaffs_load_tnode_0(dev, tn, inode_chunk, nand_chunk); -+ -+ return YAFFS_OK; -+} -+ -+static int yaffs_rd_data_obj(struct yaffs_obj *in, int inode_chunk, u8 * buffer) -+{ -+ int nand_chunk = yaffs_find_chunk_in_file(in, inode_chunk, NULL); -+ -+ if (nand_chunk >= 0) -+ return yaffs_rd_chunk_tags_nand(in->my_dev, nand_chunk, -+ buffer, NULL); -+ else { -+ T(YAFFS_TRACE_NANDACCESS, -+ (TSTR("Chunk %d not found zero instead" TENDSTR), -+ nand_chunk)); -+ /* get sane (zero) data if you read a hole */ -+ memset(buffer, 0, in->my_dev->data_bytes_per_chunk); -+ return 0; -+ } -+ -+} -+ -+void yaffs_chunk_del(struct yaffs_dev *dev, int chunk_id, int mark_flash, -+ int lyn) -+{ -+ int block; -+ int page; -+ struct yaffs_ext_tags tags; -+ struct yaffs_block_info *bi; -+ -+ if (chunk_id <= 0) -+ return; -+ -+ dev->n_deletions++; -+ block = chunk_id / dev->param.chunks_per_block; -+ page = chunk_id % dev->param.chunks_per_block; -+ -+ if (!yaffs_check_chunk_bit(dev, block, page)) -+ T(YAFFS_TRACE_VERIFY, -+ (TSTR("Deleting invalid chunk %d" TENDSTR), chunk_id)); -+ -+ bi = yaffs_get_block_info(dev, block); -+ -+ yaffs2_update_oldest_dirty_seq(dev, block, bi); -+ -+ T(YAFFS_TRACE_DELETION, -+ (TSTR("line %d delete of chunk %d" TENDSTR), lyn, chunk_id)); -+ -+ if (!dev->param.is_yaffs2 && mark_flash && -+ bi->block_state != YAFFS_BLOCK_STATE_COLLECTING) { -+ -+ yaffs_init_tags(&tags); -+ -+ tags.is_deleted = 1; -+ -+ yaffs_wr_chunk_tags_nand(dev, chunk_id, NULL, &tags); -+ yaffs_handle_chunk_update(dev, chunk_id, &tags); -+ } else { -+ dev->n_unmarked_deletions++; -+ } -+ -+ /* Pull out of the management area. -+ * If the whole block became dirty, this will kick off an erasure. -+ */ -+ if (bi->block_state == YAFFS_BLOCK_STATE_ALLOCATING || -+ bi->block_state == YAFFS_BLOCK_STATE_FULL || -+ bi->block_state == YAFFS_BLOCK_STATE_NEEDS_SCANNING || -+ bi->block_state == YAFFS_BLOCK_STATE_COLLECTING) { -+ dev->n_free_chunks++; -+ -+ yaffs_clear_chunk_bit(dev, block, page); -+ -+ bi->pages_in_use--; -+ -+ if (bi->pages_in_use == 0 && -+ !bi->has_shrink_hdr && -+ bi->block_state != YAFFS_BLOCK_STATE_ALLOCATING && -+ bi->block_state != YAFFS_BLOCK_STATE_NEEDS_SCANNING) { -+ yaffs_block_became_dirty(dev, block); -+ } -+ -+ } -+ -+} -+ -+static int yaffs_wr_data_obj(struct yaffs_obj *in, int inode_chunk, -+ const u8 * buffer, int n_bytes, int use_reserve) -+{ -+ /* Find old chunk Need to do this to get serial number -+ * Write new one and patch into tree. -+ * Invalidate old tags. -+ */ -+ -+ int prev_chunk_id; -+ struct yaffs_ext_tags prev_tags; -+ -+ int new_chunk_id; -+ struct yaffs_ext_tags new_tags; -+ -+ struct yaffs_dev *dev = in->my_dev; -+ -+ yaffs_check_gc(dev, 0); -+ -+ /* Get the previous chunk at this location in the file if it exists. -+ * If it does not exist then put a zero into the tree. This creates -+ * the tnode now, rather than later when it is harder to clean up. -+ */ -+ prev_chunk_id = yaffs_find_chunk_in_file(in, inode_chunk, &prev_tags); -+ if (prev_chunk_id < 1 && -+ !yaffs_put_chunk_in_file(in, inode_chunk, 0, 0)) -+ return 0; -+ -+ /* Set up new tags */ -+ yaffs_init_tags(&new_tags); -+ -+ new_tags.chunk_id = inode_chunk; -+ new_tags.obj_id = in->obj_id; -+ new_tags.serial_number = -+ (prev_chunk_id > 0) ? prev_tags.serial_number + 1 : 1; -+ new_tags.n_bytes = n_bytes; -+ -+ if (n_bytes < 1 || n_bytes > dev->param.total_bytes_per_chunk) { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR("Writing %d bytes to chunk!!!!!!!!!" TENDSTR), -+ n_bytes)); -+ YBUG(); -+ } -+ -+ new_chunk_id = -+ yaffs_write_new_chunk(dev, buffer, &new_tags, use_reserve); -+ -+ if (new_chunk_id > 0) { -+ yaffs_put_chunk_in_file(in, inode_chunk, new_chunk_id, 0); -+ -+ if (prev_chunk_id > 0) -+ yaffs_chunk_del(dev, prev_chunk_id, 1, __LINE__); -+ -+ yaffs_verify_file_sane(in); -+ } -+ return new_chunk_id; -+ -+} -+ -+/* UpdateObjectHeader updates the header on NAND for an object. -+ * If name is not NULL, then that new name is used. -+ */ -+int yaffs_update_oh(struct yaffs_obj *in, const YCHAR * name, int force, -+ int is_shrink, int shadows, struct yaffs_xattr_mod *xmod) -+{ -+ -+ struct yaffs_block_info *bi; -+ -+ struct yaffs_dev *dev = in->my_dev; -+ -+ int prev_chunk_id; -+ int ret_val = 0; -+ int result = 0; -+ -+ int new_chunk_id; -+ struct yaffs_ext_tags new_tags; -+ struct yaffs_ext_tags old_tags; -+ const YCHAR *alias = NULL; -+ -+ u8 *buffer = NULL; -+ YCHAR old_name[YAFFS_MAX_NAME_LENGTH + 1]; -+ -+ struct yaffs_obj_hdr *oh = NULL; -+ -+ yaffs_strcpy(old_name, _Y("silly old name")); -+ -+ if (!in->fake || in == dev->root_dir || /* The root_dir should also be saved */ -+ force || xmod) { -+ -+ yaffs_check_gc(dev, 0); -+ yaffs_check_obj_details_loaded(in); -+ -+ buffer = yaffs_get_temp_buffer(in->my_dev, __LINE__); -+ oh = (struct yaffs_obj_hdr *)buffer; -+ -+ prev_chunk_id = in->hdr_chunk; -+ -+ if (prev_chunk_id > 0) { -+ result = yaffs_rd_chunk_tags_nand(dev, prev_chunk_id, -+ buffer, &old_tags); -+ -+ yaffs_verify_oh(in, oh, &old_tags, 0); -+ -+ memcpy(old_name, oh->name, sizeof(oh->name)); -+ memset(buffer, 0xFF, sizeof(struct yaffs_obj_hdr)); -+ } else { -+ memset(buffer, 0xFF, dev->data_bytes_per_chunk); -+ } -+ -+ oh->type = in->variant_type; -+ oh->yst_mode = in->yst_mode; -+ oh->shadows_obj = oh->inband_shadowed_obj_id = shadows; -+ -+ yaffs_load_attribs_oh(oh, in); -+ -+ if (in->parent) -+ oh->parent_obj_id = in->parent->obj_id; -+ else -+ oh->parent_obj_id = 0; -+ -+ if (name && *name) { -+ memset(oh->name, 0, sizeof(oh->name)); -+ yaffs_load_oh_from_name(dev, oh->name, name); -+ } else if (prev_chunk_id > 0) { -+ memcpy(oh->name, old_name, sizeof(oh->name)); -+ } else { -+ memset(oh->name, 0, sizeof(oh->name)); -+ } -+ -+ oh->is_shrink = is_shrink; -+ -+ switch (in->variant_type) { -+ case YAFFS_OBJECT_TYPE_UNKNOWN: -+ /* Should not happen */ -+ break; -+ case YAFFS_OBJECT_TYPE_FILE: -+ oh->file_size = -+ (oh->parent_obj_id == YAFFS_OBJECTID_DELETED -+ || oh->parent_obj_id == -+ YAFFS_OBJECTID_UNLINKED) ? 0 : in-> -+ variant.file_variant.file_size; -+ break; -+ case YAFFS_OBJECT_TYPE_HARDLINK: -+ oh->equiv_id = in->variant.hardlink_variant.equiv_id; -+ break; -+ case YAFFS_OBJECT_TYPE_SPECIAL: -+ /* Do nothing */ -+ break; -+ case YAFFS_OBJECT_TYPE_DIRECTORY: -+ /* Do nothing */ -+ break; -+ case YAFFS_OBJECT_TYPE_SYMLINK: -+ alias = in->variant.symlink_variant.alias; -+ if (!alias) -+ alias = _Y("no alias"); -+ yaffs_strncpy(oh->alias, alias, YAFFS_MAX_ALIAS_LENGTH); -+ oh->alias[YAFFS_MAX_ALIAS_LENGTH] = 0; -+ break; -+ } -+ -+ /* process any xattrib modifications */ -+ if (xmod) -+ yaffs_apply_xattrib_mod(in, (char *)buffer, xmod); -+ -+ /* Tags */ -+ yaffs_init_tags(&new_tags); -+ in->serial++; -+ new_tags.chunk_id = 0; -+ new_tags.obj_id = in->obj_id; -+ new_tags.serial_number = in->serial; -+ -+ /* Add extra info for file header */ -+ -+ new_tags.extra_available = 1; -+ new_tags.extra_parent_id = oh->parent_obj_id; -+ new_tags.extra_length = oh->file_size; -+ new_tags.extra_is_shrink = oh->is_shrink; -+ new_tags.extra_equiv_id = oh->equiv_id; -+ new_tags.extra_shadows = (oh->shadows_obj > 0) ? 1 : 0; -+ new_tags.extra_obj_type = in->variant_type; -+ -+ yaffs_verify_oh(in, oh, &new_tags, 1); -+ -+ /* Create new chunk in NAND */ -+ new_chunk_id = -+ yaffs_write_new_chunk(dev, buffer, &new_tags, -+ (prev_chunk_id > 0) ? 1 : 0); -+ -+ if (new_chunk_id >= 0) { -+ -+ in->hdr_chunk = new_chunk_id; -+ -+ if (prev_chunk_id > 0) { -+ yaffs_chunk_del(dev, prev_chunk_id, 1, -+ __LINE__); -+ } -+ -+ if (!yaffs_obj_cache_dirty(in)) -+ in->dirty = 0; -+ -+ /* If this was a shrink, then mark the block that the chunk lives on */ -+ if (is_shrink) { -+ bi = yaffs_get_block_info(in->my_dev, -+ new_chunk_id / -+ in->my_dev->param. -+ chunks_per_block); -+ bi->has_shrink_hdr = 1; -+ } -+ -+ } -+ -+ ret_val = new_chunk_id; -+ -+ } -+ -+ if (buffer) -+ yaffs_release_temp_buffer(dev, buffer, __LINE__); -+ -+ return ret_val; -+} -+ -+/*------------------------ Short Operations Cache ---------------------------------------- -+ * In many situations where there is no high level buffering a lot of -+ * reads might be short sequential reads, and a lot of writes may be short -+ * sequential writes. eg. scanning/writing a jpeg file. -+ * In these cases, a short read/write cache can provide a huge perfomance -+ * benefit with dumb-as-a-rock code. -+ * In Linux, the page cache provides read buffering and the short op cache -+ * provides write buffering. -+ * -+ * There are a limited number (~10) of cache chunks per device so that we don't -+ * need a very intelligent search. -+ */ -+ -+static int yaffs_obj_cache_dirty(struct yaffs_obj *obj) -+{ -+ struct yaffs_dev *dev = obj->my_dev; -+ int i; -+ struct yaffs_cache *cache; -+ int n_caches = obj->my_dev->param.n_caches; -+ -+ for (i = 0; i < n_caches; i++) { -+ cache = &dev->cache[i]; -+ if (cache->object == obj && cache->dirty) -+ return 1; -+ } -+ -+ return 0; -+} -+ -+static void yaffs_flush_file_cache(struct yaffs_obj *obj) -+{ -+ struct yaffs_dev *dev = obj->my_dev; -+ int lowest = -99; /* Stop compiler whining. */ -+ int i; -+ struct yaffs_cache *cache; -+ int chunk_written = 0; -+ int n_caches = obj->my_dev->param.n_caches; -+ -+ if (n_caches > 0) { -+ do { -+ cache = NULL; -+ -+ /* Find the dirty cache for this object with the lowest chunk id. */ -+ for (i = 0; i < n_caches; i++) { -+ if (dev->cache[i].object == obj && -+ dev->cache[i].dirty) { -+ if (!cache -+ || dev->cache[i].chunk_id < -+ lowest) { -+ cache = &dev->cache[i]; -+ lowest = cache->chunk_id; -+ } -+ } -+ } -+ -+ if (cache && !cache->locked) { -+ /* Write it out and free it up */ -+ -+ chunk_written = -+ yaffs_wr_data_obj(cache->object, -+ cache->chunk_id, -+ cache->data, -+ cache->n_bytes, 1); -+ cache->dirty = 0; -+ cache->object = NULL; -+ } -+ -+ } while (cache && chunk_written > 0); -+ -+ if (cache) { -+ /* Hoosterman, disk full while writing cache out. */ -+ T(YAFFS_TRACE_ERROR, -+ (TSTR -+ ("yaffs tragedy: no space during cache write" -+ TENDSTR))); -+ -+ } -+ } -+ -+} -+ -+/*yaffs_flush_whole_cache(dev) -+ * -+ * -+ */ -+ -+void yaffs_flush_whole_cache(struct yaffs_dev *dev) -+{ -+ struct yaffs_obj *obj; -+ int n_caches = dev->param.n_caches; -+ int i; -+ -+ /* Find a dirty object in the cache and flush it... -+ * until there are no further dirty objects. -+ */ -+ do { -+ obj = NULL; -+ for (i = 0; i < n_caches && !obj; i++) { -+ if (dev->cache[i].object && dev->cache[i].dirty) -+ obj = dev->cache[i].object; -+ -+ } -+ if (obj) -+ yaffs_flush_file_cache(obj); -+ -+ } while (obj); -+ -+} -+ -+/* Grab us a cache chunk for use. -+ * First look for an empty one. -+ * Then look for the least recently used non-dirty one. -+ * Then look for the least recently used dirty one...., flush and look again. -+ */ -+static struct yaffs_cache *yaffs_grab_chunk_worker(struct yaffs_dev *dev) -+{ -+ int i; -+ -+ if (dev->param.n_caches > 0) { -+ for (i = 0; i < dev->param.n_caches; i++) { -+ if (!dev->cache[i].object) -+ return &dev->cache[i]; -+ } -+ } -+ -+ return NULL; -+} -+ -+static struct yaffs_cache *yaffs_grab_chunk_cache(struct yaffs_dev *dev) -+{ -+ struct yaffs_cache *cache; -+ struct yaffs_obj *the_obj; -+ int usage; -+ int i; -+ int pushout; -+ -+ if (dev->param.n_caches > 0) { -+ /* Try find a non-dirty one... */ -+ -+ cache = yaffs_grab_chunk_worker(dev); -+ -+ if (!cache) { -+ /* They were all dirty, find the last recently used object and flush -+ * its cache, then find again. -+ * NB what's here is not very accurate, we actually flush the object -+ * the last recently used page. -+ */ -+ -+ /* With locking we can't assume we can use entry zero */ -+ -+ the_obj = NULL; -+ usage = -1; -+ cache = NULL; -+ pushout = -1; -+ -+ for (i = 0; i < dev->param.n_caches; i++) { -+ if (dev->cache[i].object && -+ !dev->cache[i].locked && -+ (dev->cache[i].last_use < usage -+ || !cache)) { -+ usage = dev->cache[i].last_use; -+ the_obj = dev->cache[i].object; -+ cache = &dev->cache[i]; -+ pushout = i; -+ } -+ } -+ -+ if (!cache || cache->dirty) { -+ /* Flush and try again */ -+ yaffs_flush_file_cache(the_obj); -+ cache = yaffs_grab_chunk_worker(dev); -+ } -+ -+ } -+ return cache; -+ } else { -+ return NULL; -+ } -+} -+ -+/* Find a cached chunk */ -+static struct yaffs_cache *yaffs_find_chunk_cache(const struct yaffs_obj *obj, -+ int chunk_id) -+{ -+ struct yaffs_dev *dev = obj->my_dev; -+ int i; -+ if (dev->param.n_caches > 0) { -+ for (i = 0; i < dev->param.n_caches; i++) { -+ if (dev->cache[i].object == obj && -+ dev->cache[i].chunk_id == chunk_id) { -+ dev->cache_hits++; -+ -+ return &dev->cache[i]; -+ } -+ } -+ } -+ return NULL; -+} -+ -+/* Mark the chunk for the least recently used algorithym */ -+static void yaffs_use_cache(struct yaffs_dev *dev, struct yaffs_cache *cache, -+ int is_write) -+{ -+ -+ if (dev->param.n_caches > 0) { -+ if (dev->cache_last_use < 0 || dev->cache_last_use > 100000000) { -+ /* Reset the cache usages */ -+ int i; -+ for (i = 1; i < dev->param.n_caches; i++) -+ dev->cache[i].last_use = 0; -+ -+ dev->cache_last_use = 0; -+ } -+ -+ dev->cache_last_use++; -+ -+ cache->last_use = dev->cache_last_use; -+ -+ if (is_write) -+ cache->dirty = 1; -+ } -+} -+ -+/* Invalidate a single cache page. -+ * Do this when a whole page gets written, -+ * ie the short cache for this page is no longer valid. -+ */ -+static void yaffs_invalidate_chunk_cache(struct yaffs_obj *object, int chunk_id) -+{ -+ if (object->my_dev->param.n_caches > 0) { -+ struct yaffs_cache *cache = -+ yaffs_find_chunk_cache(object, chunk_id); -+ -+ if (cache) -+ cache->object = NULL; -+ } -+} -+ -+/* Invalidate all the cache pages associated with this object -+ * Do this whenever ther file is deleted or resized. -+ */ -+static void yaffs_invalidate_whole_cache(struct yaffs_obj *in) -+{ -+ int i; -+ struct yaffs_dev *dev = in->my_dev; -+ -+ if (dev->param.n_caches > 0) { -+ /* Invalidate it. */ -+ for (i = 0; i < dev->param.n_caches; i++) { -+ if (dev->cache[i].object == in) -+ dev->cache[i].object = NULL; -+ } -+ } -+} -+ -+/*--------------------- File read/write ------------------------ -+ * Read and write have very similar structures. -+ * In general the read/write has three parts to it -+ * An incomplete chunk to start with (if the read/write is not chunk-aligned) -+ * Some complete chunks -+ * An incomplete chunk to end off with -+ * -+ * Curve-balls: the first chunk might also be the last chunk. -+ */ -+ -+int yaffs_file_rd(struct yaffs_obj *in, u8 * buffer, loff_t offset, int n_bytes) -+{ -+ -+ int chunk; -+ u32 start; -+ int n_copy; -+ int n = n_bytes; -+ int n_done = 0; -+ struct yaffs_cache *cache; -+ -+ struct yaffs_dev *dev; -+ -+ dev = in->my_dev; -+ -+ while (n > 0) { -+ /* chunk = offset / dev->data_bytes_per_chunk + 1; */ -+ /* start = offset % dev->data_bytes_per_chunk; */ -+ yaffs_addr_to_chunk(dev, offset, &chunk, &start); -+ chunk++; -+ -+ /* OK now check for the curveball where the start and end are in -+ * the same chunk. -+ */ -+ if ((start + n) < dev->data_bytes_per_chunk) -+ n_copy = n; -+ else -+ n_copy = dev->data_bytes_per_chunk - start; -+ -+ cache = yaffs_find_chunk_cache(in, chunk); -+ -+ /* If the chunk is already in the cache or it is less than a whole chunk -+ * or we're using inband tags then use the cache (if there is caching) -+ * else bypass the cache. -+ */ -+ if (cache || n_copy != dev->data_bytes_per_chunk -+ || dev->param.inband_tags) { -+ if (dev->param.n_caches > 0) { -+ -+ /* If we can't find the data in the cache, then load it up. */ -+ -+ if (!cache) { -+ cache = -+ yaffs_grab_chunk_cache(in->my_dev); -+ cache->object = in; -+ cache->chunk_id = chunk; -+ cache->dirty = 0; -+ cache->locked = 0; -+ yaffs_rd_data_obj(in, chunk, -+ cache->data); -+ cache->n_bytes = 0; -+ } -+ -+ yaffs_use_cache(dev, cache, 0); -+ -+ cache->locked = 1; -+ -+ memcpy(buffer, &cache->data[start], n_copy); -+ -+ cache->locked = 0; -+ } else { -+ /* Read into the local buffer then copy.. */ -+ -+ u8 *local_buffer = -+ yaffs_get_temp_buffer(dev, __LINE__); -+ yaffs_rd_data_obj(in, chunk, local_buffer); -+ -+ memcpy(buffer, &local_buffer[start], n_copy); -+ -+ yaffs_release_temp_buffer(dev, local_buffer, -+ __LINE__); -+ } -+ -+ } else { -+ -+ /* A full chunk. Read directly into the supplied buffer. */ -+ yaffs_rd_data_obj(in, chunk, buffer); -+ -+ } -+ -+ n -= n_copy; -+ offset += n_copy; -+ buffer += n_copy; -+ n_done += n_copy; -+ -+ } -+ -+ return n_done; -+} -+ -+int yaffs_do_file_wr(struct yaffs_obj *in, const u8 * buffer, loff_t offset, -+ int n_bytes, int write_trhrough) -+{ -+ -+ int chunk; -+ u32 start; -+ int n_copy; -+ int n = n_bytes; -+ int n_done = 0; -+ int n_writeback; -+ int start_write = offset; -+ int chunk_written = 0; -+ u32 n_bytes_read; -+ u32 chunk_start; -+ -+ struct yaffs_dev *dev; -+ -+ dev = in->my_dev; -+ -+ while (n > 0 && chunk_written >= 0) { -+ yaffs_addr_to_chunk(dev, offset, &chunk, &start); -+ -+ if (chunk * dev->data_bytes_per_chunk + start != offset || -+ start >= dev->data_bytes_per_chunk) { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR -+ ("AddrToChunk of offset %d gives chunk %d start %d" -+ TENDSTR), (int)offset, chunk, start)); -+ } -+ chunk++; /* File pos to chunk in file offset */ -+ -+ /* OK now check for the curveball where the start and end are in -+ * the same chunk. -+ */ -+ -+ if ((start + n) < dev->data_bytes_per_chunk) { -+ n_copy = n; -+ -+ /* Now folks, to calculate how many bytes to write back.... -+ * If we're overwriting and not writing to then end of file then -+ * we need to write back as much as was there before. -+ */ -+ -+ chunk_start = ((chunk - 1) * dev->data_bytes_per_chunk); -+ -+ if (chunk_start > in->variant.file_variant.file_size) -+ n_bytes_read = 0; /* Past end of file */ -+ else -+ n_bytes_read = -+ in->variant.file_variant.file_size - -+ chunk_start; -+ -+ if (n_bytes_read > dev->data_bytes_per_chunk) -+ n_bytes_read = dev->data_bytes_per_chunk; -+ -+ n_writeback = -+ (n_bytes_read > -+ (start + n)) ? n_bytes_read : (start + n); -+ -+ if (n_writeback < 0 -+ || n_writeback > dev->data_bytes_per_chunk) -+ YBUG(); -+ -+ } else { -+ n_copy = dev->data_bytes_per_chunk - start; -+ n_writeback = dev->data_bytes_per_chunk; -+ } -+ -+ if (n_copy != dev->data_bytes_per_chunk -+ || dev->param.inband_tags) { -+ /* An incomplete start or end chunk (or maybe both start and end chunk), -+ * or we're using inband tags, so we want to use the cache buffers. -+ */ -+ if (dev->param.n_caches > 0) { -+ struct yaffs_cache *cache; -+ /* If we can't find the data in the cache, then load the cache */ -+ cache = yaffs_find_chunk_cache(in, chunk); -+ -+ if (!cache -+ && yaffs_check_alloc_available(dev, 1)) { -+ cache = yaffs_grab_chunk_cache(dev); -+ cache->object = in; -+ cache->chunk_id = chunk; -+ cache->dirty = 0; -+ cache->locked = 0; -+ yaffs_rd_data_obj(in, chunk, -+ cache->data); -+ } else if (cache && -+ !cache->dirty && -+ !yaffs_check_alloc_available(dev, -+ 1)) { -+ /* Drop the cache if it was a read cache item and -+ * no space check has been made for it. -+ */ -+ cache = NULL; -+ } -+ -+ if (cache) { -+ yaffs_use_cache(dev, cache, 1); -+ cache->locked = 1; -+ -+ memcpy(&cache->data[start], buffer, -+ n_copy); -+ -+ cache->locked = 0; -+ cache->n_bytes = n_writeback; -+ -+ if (write_trhrough) { -+ chunk_written = -+ yaffs_wr_data_obj -+ (cache->object, -+ cache->chunk_id, -+ cache->data, -+ cache->n_bytes, 1); -+ cache->dirty = 0; -+ } -+ -+ } else { -+ chunk_written = -1; /* fail the write */ -+ } -+ } else { -+ /* An incomplete start or end chunk (or maybe both start and end chunk) -+ * Read into the local buffer then copy, then copy over and write back. -+ */ -+ -+ u8 *local_buffer = -+ yaffs_get_temp_buffer(dev, __LINE__); -+ -+ yaffs_rd_data_obj(in, chunk, local_buffer); -+ -+ memcpy(&local_buffer[start], buffer, n_copy); -+ -+ chunk_written = -+ yaffs_wr_data_obj(in, chunk, -+ local_buffer, -+ n_writeback, 0); -+ -+ yaffs_release_temp_buffer(dev, local_buffer, -+ __LINE__); -+ -+ } -+ -+ } else { -+ /* A full chunk. Write directly from the supplied buffer. */ -+ -+ chunk_written = -+ yaffs_wr_data_obj(in, chunk, buffer, -+ dev->data_bytes_per_chunk, 0); -+ -+ /* Since we've overwritten the cached data, we better invalidate it. */ -+ yaffs_invalidate_chunk_cache(in, chunk); -+ } -+ -+ if (chunk_written >= 0) { -+ n -= n_copy; -+ offset += n_copy; -+ buffer += n_copy; -+ n_done += n_copy; -+ } -+ -+ } -+ -+ /* Update file object */ -+ -+ if ((start_write + n_done) > in->variant.file_variant.file_size) -+ in->variant.file_variant.file_size = (start_write + n_done); -+ -+ in->dirty = 1; -+ -+ return n_done; -+} -+ -+int yaffs_wr_file(struct yaffs_obj *in, const u8 * buffer, loff_t offset, -+ int n_bytes, int write_trhrough) -+{ -+ yaffs2_handle_hole(in, offset); -+ return yaffs_do_file_wr(in, buffer, offset, n_bytes, write_trhrough); -+} -+ -+/* ---------------------- File resizing stuff ------------------ */ -+ -+static void yaffs_prune_chunks(struct yaffs_obj *in, int new_size) -+{ -+ -+ struct yaffs_dev *dev = in->my_dev; -+ int old_size = in->variant.file_variant.file_size; -+ -+ int last_del = 1 + (old_size - 1) / dev->data_bytes_per_chunk; -+ -+ int start_del = 1 + (new_size + dev->data_bytes_per_chunk - 1) / -+ dev->data_bytes_per_chunk; -+ int i; -+ int chunk_id; -+ -+ /* Delete backwards so that we don't end up with holes if -+ * power is lost part-way through the operation. -+ */ -+ for (i = last_del; i >= start_del; i--) { -+ /* NB this could be optimised somewhat, -+ * eg. could retrieve the tags and write them without -+ * using yaffs_chunk_del -+ */ -+ -+ chunk_id = yaffs_find_del_file_chunk(in, i, NULL); -+ if (chunk_id > 0) { -+ if (chunk_id < -+ (dev->internal_start_block * -+ dev->param.chunks_per_block) -+ || chunk_id >= -+ ((dev->internal_end_block + -+ 1) * dev->param.chunks_per_block)) { -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR -+ ("Found daft chunk_id %d for %d" TENDSTR), -+ chunk_id, i)); -+ } else { -+ in->n_data_chunks--; -+ yaffs_chunk_del(dev, chunk_id, 1, __LINE__); -+ } -+ } -+ } -+ -+} -+ -+void yaffs_resize_file_down(struct yaffs_obj *obj, loff_t new_size) -+{ -+ int new_full; -+ u32 new_partial; -+ struct yaffs_dev *dev = obj->my_dev; -+ -+ yaffs_addr_to_chunk(dev, new_size, &new_full, &new_partial); -+ -+ yaffs_prune_chunks(obj, new_size); -+ -+ if (new_partial != 0) { -+ int last_chunk = 1 + new_full; -+ u8 *local_buffer = yaffs_get_temp_buffer(dev, __LINE__); -+ -+ /* Got to read and rewrite the last chunk with its new size and zero pad */ -+ yaffs_rd_data_obj(obj, last_chunk, local_buffer); -+ memset(local_buffer + new_partial, 0, -+ dev->data_bytes_per_chunk - new_partial); -+ -+ yaffs_wr_data_obj(obj, last_chunk, local_buffer, -+ new_partial, 1); -+ -+ yaffs_release_temp_buffer(dev, local_buffer, __LINE__); -+ } -+ -+ obj->variant.file_variant.file_size = new_size; -+ -+ yaffs_prune_tree(dev, &obj->variant.file_variant); -+} -+ -+int yaffs_resize_file(struct yaffs_obj *in, loff_t new_size) -+{ -+ struct yaffs_dev *dev = in->my_dev; -+ int old_size = in->variant.file_variant.file_size; -+ -+ yaffs_flush_file_cache(in); -+ yaffs_invalidate_whole_cache(in); -+ -+ yaffs_check_gc(dev, 0); -+ -+ if (in->variant_type != YAFFS_OBJECT_TYPE_FILE) -+ return YAFFS_FAIL; -+ -+ if (new_size == old_size) -+ return YAFFS_OK; -+ -+ if (new_size > old_size) { -+ yaffs2_handle_hole(in, new_size); -+ in->variant.file_variant.file_size = new_size; -+ } else { -+ /* new_size < old_size */ -+ yaffs_resize_file_down(in, new_size); -+ } -+ -+ /* Write a new object header to reflect the resize. -+ * show we've shrunk the file, if need be -+ * Do this only if the file is not in the deleted directories -+ * and is not shadowed. -+ */ -+ if (in->parent && -+ !in->is_shadowed && -+ in->parent->obj_id != YAFFS_OBJECTID_UNLINKED && -+ in->parent->obj_id != YAFFS_OBJECTID_DELETED) -+ yaffs_update_oh(in, NULL, 0, 0, 0, NULL); -+ -+ return YAFFS_OK; -+} -+ -+int yaffs_flush_file(struct yaffs_obj *in, int update_time, int data_sync) -+{ -+ int ret_val; -+ if (in->dirty) { -+ yaffs_flush_file_cache(in); -+ if (data_sync) /* Only sync data */ -+ ret_val = YAFFS_OK; -+ else { -+ if (update_time) -+ yaffs_load_current_time(in, 0, 0); -+ -+ ret_val = (yaffs_update_oh(in, NULL, 0, 0, 0, NULL) >= -+ 0) ? YAFFS_OK : YAFFS_FAIL; -+ } -+ } else { -+ ret_val = YAFFS_OK; -+ } -+ -+ return ret_val; -+ -+} -+ -+static int yaffs_generic_obj_del(struct yaffs_obj *in) -+{ -+ -+ /* First off, invalidate the file's data in the cache, without flushing. */ -+ yaffs_invalidate_whole_cache(in); -+ -+ if (in->my_dev->param.is_yaffs2 && (in->parent != in->my_dev->del_dir)) { -+ /* Move to the unlinked directory so we have a record that it was deleted. */ -+ yaffs_change_obj_name(in, in->my_dev->del_dir, _Y("deleted"), 0, -+ 0); -+ -+ } -+ -+ yaffs_remove_obj_from_dir(in); -+ yaffs_chunk_del(in->my_dev, in->hdr_chunk, 1, __LINE__); -+ in->hdr_chunk = 0; -+ -+ yaffs_free_obj(in); -+ return YAFFS_OK; -+ -+} -+ -+/* yaffs_del_file deletes the whole file data -+ * and the inode associated with the file. -+ * It does not delete the links associated with the file. -+ */ -+static int yaffs_unlink_file_if_needed(struct yaffs_obj *in) -+{ -+ -+ int ret_val; -+ int del_now = 0; -+ struct yaffs_dev *dev = in->my_dev; -+ -+ if (!in->my_inode) -+ del_now = 1; -+ -+ if (del_now) { -+ ret_val = -+ yaffs_change_obj_name(in, in->my_dev->del_dir, -+ _Y("deleted"), 0, 0); -+ T(YAFFS_TRACE_TRACING, -+ (TSTR("yaffs: immediate deletion of file %d" TENDSTR), -+ in->obj_id)); -+ in->deleted = 1; -+ in->my_dev->n_deleted_files++; -+ if (dev->param.disable_soft_del || dev->param.is_yaffs2) -+ yaffs_resize_file(in, 0); -+ yaffs_soft_del_file(in); -+ } else { -+ ret_val = -+ yaffs_change_obj_name(in, in->my_dev->unlinked_dir, -+ _Y("unlinked"), 0, 0); -+ } -+ -+ return ret_val; -+} -+ -+int yaffs_del_file(struct yaffs_obj *in) -+{ -+ int ret_val = YAFFS_OK; -+ int deleted; /* Need to cache value on stack if in is freed */ -+ struct yaffs_dev *dev = in->my_dev; -+ -+ if (dev->param.disable_soft_del || dev->param.is_yaffs2) -+ yaffs_resize_file(in, 0); -+ -+ if (in->n_data_chunks > 0) { -+ /* Use soft deletion if there is data in the file. -+ * That won't be the case if it has been resized to zero. -+ */ -+ if (!in->unlinked) -+ ret_val = yaffs_unlink_file_if_needed(in); -+ -+ deleted = in->deleted; -+ -+ if (ret_val == YAFFS_OK && in->unlinked && !in->deleted) { -+ in->deleted = 1; -+ deleted = 1; -+ in->my_dev->n_deleted_files++; -+ yaffs_soft_del_file(in); -+ } -+ return deleted ? YAFFS_OK : YAFFS_FAIL; -+ } else { -+ /* The file has no data chunks so we toss it immediately */ -+ yaffs_free_tnode(in->my_dev, in->variant.file_variant.top); -+ in->variant.file_variant.top = NULL; -+ yaffs_generic_obj_del(in); -+ -+ return YAFFS_OK; -+ } -+} -+ -+static int yaffs_is_non_empty_dir(struct yaffs_obj *obj) -+{ -+ return (obj->variant_type == YAFFS_OBJECT_TYPE_DIRECTORY) && -+ !(list_empty(&obj->variant.dir_variant.children)); -+} -+ -+static int yaffs_del_dir(struct yaffs_obj *obj) -+{ -+ /* First check that the directory is empty. */ -+ if (yaffs_is_non_empty_dir(obj)) -+ return YAFFS_FAIL; -+ -+ return yaffs_generic_obj_del(obj); -+} -+ -+static int yaffs_del_symlink(struct yaffs_obj *in) -+{ -+ if (in->variant.symlink_variant.alias) -+ YFREE(in->variant.symlink_variant.alias); -+ in->variant.symlink_variant.alias = NULL; -+ -+ return yaffs_generic_obj_del(in); -+} -+ -+static int yaffs_del_link(struct yaffs_obj *in) -+{ -+ /* remove this hardlink from the list assocaited with the equivalent -+ * object -+ */ -+ list_del_init(&in->hard_links); -+ return yaffs_generic_obj_del(in); -+} -+ -+int yaffs_del_obj(struct yaffs_obj *obj) -+{ -+ int ret_val = -1; -+ switch (obj->variant_type) { -+ case YAFFS_OBJECT_TYPE_FILE: -+ ret_val = yaffs_del_file(obj); -+ break; -+ case YAFFS_OBJECT_TYPE_DIRECTORY: -+ if (!list_empty(&obj->variant.dir_variant.dirty)) { -+ T(YAFFS_TRACE_BACKGROUND, -+ (TSTR -+ ("Remove object %d from dirty directories" TENDSTR), -+ obj->obj_id)); -+ list_del_init(&obj->variant.dir_variant.dirty); -+ } -+ return yaffs_del_dir(obj); -+ break; -+ case YAFFS_OBJECT_TYPE_SYMLINK: -+ ret_val = yaffs_del_symlink(obj); -+ break; -+ case YAFFS_OBJECT_TYPE_HARDLINK: -+ ret_val = yaffs_del_link(obj); -+ break; -+ case YAFFS_OBJECT_TYPE_SPECIAL: -+ ret_val = yaffs_generic_obj_del(obj); -+ break; -+ case YAFFS_OBJECT_TYPE_UNKNOWN: -+ ret_val = 0; -+ break; /* should not happen. */ -+ } -+ -+ return ret_val; -+} -+ -+static int yaffs_unlink_worker(struct yaffs_obj *obj) -+{ -+ -+ int del_now = 0; -+ -+ if (!obj->my_inode) -+ del_now = 1; -+ -+ if (obj) -+ yaffs_update_parent(obj->parent); -+ -+ if (obj->variant_type == YAFFS_OBJECT_TYPE_HARDLINK) { -+ return yaffs_del_link(obj); -+ } else if (!list_empty(&obj->hard_links)) { -+ /* Curve ball: We're unlinking an object that has a hardlink. -+ * -+ * This problem arises because we are not strictly following -+ * The Linux link/inode model. -+ * -+ * We can't really delete the object. -+ * Instead, we do the following: -+ * - Select a hardlink. -+ * - Unhook it from the hard links -+ * - Move it from its parent directory (so that the rename can work) -+ * - Rename the object to the hardlink's name. -+ * - Delete the hardlink -+ */ -+ -+ struct yaffs_obj *hl; -+ struct yaffs_obj *parent; -+ int ret_val; -+ YCHAR name[YAFFS_MAX_NAME_LENGTH + 1]; -+ -+ hl = list_entry(obj->hard_links.next, struct yaffs_obj, -+ hard_links); -+ -+ yaffs_get_obj_name(hl, name, YAFFS_MAX_NAME_LENGTH + 1); -+ parent = hl->parent; -+ -+ list_del_init(&hl->hard_links); -+ -+ yaffs_add_obj_to_dir(obj->my_dev->unlinked_dir, hl); -+ -+ ret_val = yaffs_change_obj_name(obj, parent, name, 0, 0); -+ -+ if (ret_val == YAFFS_OK) -+ ret_val = yaffs_generic_obj_del(hl); -+ -+ return ret_val; -+ -+ } else if (del_now) { -+ switch (obj->variant_type) { -+ case YAFFS_OBJECT_TYPE_FILE: -+ return yaffs_del_file(obj); -+ break; -+ case YAFFS_OBJECT_TYPE_DIRECTORY: -+ list_del_init(&obj->variant.dir_variant.dirty); -+ return yaffs_del_dir(obj); -+ break; -+ case YAFFS_OBJECT_TYPE_SYMLINK: -+ return yaffs_del_symlink(obj); -+ break; -+ case YAFFS_OBJECT_TYPE_SPECIAL: -+ return yaffs_generic_obj_del(obj); -+ break; -+ case YAFFS_OBJECT_TYPE_HARDLINK: -+ case YAFFS_OBJECT_TYPE_UNKNOWN: -+ default: -+ return YAFFS_FAIL; -+ } -+ } else if (yaffs_is_non_empty_dir(obj)) { -+ return YAFFS_FAIL; -+ } else { -+ return yaffs_change_obj_name(obj, obj->my_dev->unlinked_dir, -+ _Y("unlinked"), 0, 0); -+ } -+} -+ -+static int yaffs_unlink_obj(struct yaffs_obj *obj) -+{ -+ -+ if (obj && obj->unlink_allowed) -+ return yaffs_unlink_worker(obj); -+ -+ return YAFFS_FAIL; -+ -+} -+ -+int yaffs_unlinker(struct yaffs_obj *dir, const YCHAR * name) -+{ -+ struct yaffs_obj *obj; -+ -+ obj = yaffs_find_by_name(dir, name); -+ return yaffs_unlink_obj(obj); -+} -+ -+/*----------------------- Initialisation Scanning ---------------------- */ -+ -+void yaffs_handle_shadowed_obj(struct yaffs_dev *dev, int obj_id, -+ int backward_scanning) -+{ -+ struct yaffs_obj *obj; -+ -+ if (!backward_scanning) { -+ /* Handle YAFFS1 forward scanning case -+ * For YAFFS1 we always do the deletion -+ */ -+ -+ } else { -+ /* Handle YAFFS2 case (backward scanning) -+ * If the shadowed object exists then ignore. -+ */ -+ obj = yaffs_find_by_number(dev, obj_id); -+ if (obj) -+ return; -+ } -+ -+ /* Let's create it (if it does not exist) assuming it is a file so that it can do shrinking etc. -+ * We put it in unlinked dir to be cleaned up after the scanning -+ */ -+ obj = -+ yaffs_find_or_create_by_number(dev, obj_id, YAFFS_OBJECT_TYPE_FILE); -+ if (!obj) -+ return; -+ obj->is_shadowed = 1; -+ yaffs_add_obj_to_dir(dev->unlinked_dir, obj); -+ obj->variant.file_variant.shrink_size = 0; -+ obj->valid = 1; /* So that we don't read any other info for this file */ -+ -+} -+ -+void yaffs_link_fixup(struct yaffs_dev *dev, struct yaffs_obj *hard_list) -+{ -+ struct yaffs_obj *hl; -+ struct yaffs_obj *in; -+ -+ while (hard_list) { -+ hl = hard_list; -+ hard_list = (struct yaffs_obj *)(hard_list->hard_links.next); -+ -+ in = yaffs_find_by_number(dev, -+ hl->variant. -+ hardlink_variant.equiv_id); -+ -+ if (in) { -+ /* Add the hardlink pointers */ -+ hl->variant.hardlink_variant.equiv_obj = in; -+ list_add(&hl->hard_links, &in->hard_links); -+ } else { -+ /* Todo Need to report/handle this better. -+ * Got a problem... hardlink to a non-existant object -+ */ -+ hl->variant.hardlink_variant.equiv_obj = NULL; -+ INIT_LIST_HEAD(&hl->hard_links); -+ -+ } -+ } -+} -+ -+static void yaffs_strip_deleted_objs(struct yaffs_dev *dev) -+{ -+ /* -+ * Sort out state of unlinked and deleted objects after scanning. -+ */ -+ struct list_head *i; -+ struct list_head *n; -+ struct yaffs_obj *l; -+ -+ if (dev->read_only) -+ return; -+ -+ /* Soft delete all the unlinked files */ -+ list_for_each_safe(i, n, -+ &dev->unlinked_dir->variant.dir_variant.children) { -+ if (i) { -+ l = list_entry(i, struct yaffs_obj, siblings); -+ yaffs_del_obj(l); -+ } -+ } -+ -+ list_for_each_safe(i, n, &dev->del_dir->variant.dir_variant.children) { -+ if (i) { -+ l = list_entry(i, struct yaffs_obj, siblings); -+ yaffs_del_obj(l); -+ } -+ } -+ -+} -+ -+/* -+ * This code iterates through all the objects making sure that they are rooted. -+ * Any unrooted objects are re-rooted in lost+found. -+ * An object needs to be in one of: -+ * - Directly under deleted, unlinked -+ * - Directly or indirectly under root. -+ * -+ * Note: -+ * This code assumes that we don't ever change the current relationships between -+ * directories: -+ * root_dir->parent == unlinked_dir->parent == del_dir->parent == NULL -+ * lost-n-found->parent == root_dir -+ * -+ * This fixes the problem where directories might have inadvertently been deleted -+ * leaving the object "hanging" without being rooted in the directory tree. -+ */ -+ -+static int yaffs_has_null_parent(struct yaffs_dev *dev, struct yaffs_obj *obj) -+{ -+ return (obj == dev->del_dir || -+ obj == dev->unlinked_dir || obj == dev->root_dir); -+} -+ -+static void yaffs_fix_hanging_objs(struct yaffs_dev *dev) -+{ -+ struct yaffs_obj *obj; -+ struct yaffs_obj *parent; -+ int i; -+ struct list_head *lh; -+ struct list_head *n; -+ int depth_limit; -+ int hanging; -+ -+ if (dev->read_only) -+ return; -+ -+ /* Iterate through the objects in each hash entry, -+ * looking at each object. -+ * Make sure it is rooted. -+ */ -+ -+ for (i = 0; i < YAFFS_NOBJECT_BUCKETS; i++) { -+ list_for_each_safe(lh, n, &dev->obj_bucket[i].list) { -+ if (lh) { -+ obj = -+ list_entry(lh, struct yaffs_obj, hash_link); -+ parent = obj->parent; -+ -+ if (yaffs_has_null_parent(dev, obj)) { -+ /* These directories are not hanging */ -+ hanging = 0; -+ } else if (!parent -+ || parent->variant_type != -+ YAFFS_OBJECT_TYPE_DIRECTORY) { -+ hanging = 1; -+ } else if (yaffs_has_null_parent(dev, parent)) { -+ hanging = 0; -+ } else { -+ /* -+ * Need to follow the parent chain to see if it is hanging. -+ */ -+ hanging = 0; -+ depth_limit = 100; -+ -+ while (parent != dev->root_dir && -+ parent->parent && -+ parent->parent->variant_type == -+ YAFFS_OBJECT_TYPE_DIRECTORY -+ && depth_limit > 0) { -+ parent = parent->parent; -+ depth_limit--; -+ } -+ if (parent != dev->root_dir) -+ hanging = 1; -+ } -+ if (hanging) { -+ T(YAFFS_TRACE_SCAN, -+ (TSTR -+ ("Hanging object %d moved to lost and found" -+ TENDSTR), obj->obj_id)); -+ yaffs_add_obj_to_dir(dev->lost_n_found, -+ obj); -+ } -+ } -+ } -+ } -+} -+ -+/* -+ * Delete directory contents for cleaning up lost and found. -+ */ -+static void yaffs_del_dir_contents(struct yaffs_obj *dir) -+{ -+ struct yaffs_obj *obj; -+ struct list_head *lh; -+ struct list_head *n; -+ -+ if (dir->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) -+ YBUG(); -+ -+ list_for_each_safe(lh, n, &dir->variant.dir_variant.children) { -+ if (lh) { -+ obj = list_entry(lh, struct yaffs_obj, siblings); -+ if (obj->variant_type == YAFFS_OBJECT_TYPE_DIRECTORY) -+ yaffs_del_dir_contents(obj); -+ -+ T(YAFFS_TRACE_SCAN, -+ (TSTR("Deleting lost_found object %d" TENDSTR), -+ obj->obj_id)); -+ -+ /* Need to use UnlinkObject since Delete would not handle -+ * hardlinked objects correctly. -+ */ -+ yaffs_unlink_obj(obj); -+ } -+ } -+ -+} -+ -+static void yaffs_empty_l_n_f(struct yaffs_dev *dev) -+{ -+ yaffs_del_dir_contents(dev->lost_n_found); -+} -+ -+static void yaffs_check_obj_details_loaded(struct yaffs_obj *in) -+{ -+ u8 *chunk_data; -+ struct yaffs_obj_hdr *oh; -+ struct yaffs_dev *dev; -+ struct yaffs_ext_tags tags; -+ int result; -+ int alloc_failed = 0; -+ -+ if (!in) -+ return; -+ -+ dev = in->my_dev; -+ -+ if (in->lazy_loaded && in->hdr_chunk > 0) { -+ in->lazy_loaded = 0; -+ chunk_data = yaffs_get_temp_buffer(dev, __LINE__); -+ -+ result = -+ yaffs_rd_chunk_tags_nand(dev, in->hdr_chunk, chunk_data, -+ &tags); -+ oh = (struct yaffs_obj_hdr *)chunk_data; -+ -+ in->yst_mode = oh->yst_mode; -+ yaffs_load_attribs(in, oh); -+ yaffs_set_obj_name_from_oh(in, oh); -+ -+ if (in->variant_type == YAFFS_OBJECT_TYPE_SYMLINK) { -+ in->variant.symlink_variant.alias = -+ yaffs_clone_str(oh->alias); -+ if (!in->variant.symlink_variant.alias) -+ alloc_failed = 1; /* Not returned to caller */ -+ } -+ -+ yaffs_release_temp_buffer(dev, chunk_data, __LINE__); -+ } -+} -+ -+/*------------------------------ Directory Functions ----------------------------- */ -+ -+/* -+ *yaffs_update_parent() handles fixing a directories mtime and ctime when a new -+ * link (ie. name) is created or deleted in the directory. -+ * -+ * ie. -+ * create dir/a : update dir's mtime/ctime -+ * rm dir/a: update dir's mtime/ctime -+ * modify dir/a: don't update dir's mtimme/ctime -+ * -+ * This can be handled immediately or defered. Defering helps reduce the number -+ * of updates when many files in a directory are changed within a brief period. -+ * -+ * If the directory updating is defered then yaffs_update_dirty_dirs must be -+ * called periodically. -+ */ -+ -+static void yaffs_update_parent(struct yaffs_obj *obj) -+{ -+ struct yaffs_dev *dev; -+ if (!obj) -+ return; -+ dev = obj->my_dev; -+ obj->dirty = 1; -+ yaffs_load_current_time(obj, 0, 1); -+ if (dev->param.defered_dir_update) { -+ struct list_head *link = &obj->variant.dir_variant.dirty; -+ -+ if (list_empty(link)) { -+ list_add(link, &dev->dirty_dirs); -+ T(YAFFS_TRACE_BACKGROUND, -+ (TSTR("Added object %d to dirty directories" TENDSTR), -+ obj->obj_id)); -+ } -+ -+ } else { -+ yaffs_update_oh(obj, NULL, 0, 0, 0, NULL); -+ } -+} -+ -+void yaffs_update_dirty_dirs(struct yaffs_dev *dev) -+{ -+ struct list_head *link; -+ struct yaffs_obj *obj; -+ struct yaffs_dir_var *d_s; -+ union yaffs_obj_var *o_v; -+ -+ T(YAFFS_TRACE_BACKGROUND, (TSTR("Update dirty directories" TENDSTR))); -+ -+ while (!list_empty(&dev->dirty_dirs)) { -+ link = dev->dirty_dirs.next; -+ list_del_init(link); -+ -+ d_s = list_entry(link, struct yaffs_dir_var, dirty); -+ o_v = list_entry(d_s, union yaffs_obj_var, dir_variant); -+ obj = list_entry(o_v, struct yaffs_obj, variant); -+ -+ T(YAFFS_TRACE_BACKGROUND, -+ (TSTR("Update directory %d" TENDSTR), obj->obj_id)); -+ -+ if (obj->dirty) -+ yaffs_update_oh(obj, NULL, 0, 0, 0, NULL); -+ } -+} -+ -+static void yaffs_remove_obj_from_dir(struct yaffs_obj *obj) -+{ -+ struct yaffs_dev *dev = obj->my_dev; -+ struct yaffs_obj *parent; -+ -+ yaffs_verify_obj_in_dir(obj); -+ parent = obj->parent; -+ -+ yaffs_verify_dir(parent); -+ -+ if (dev && dev->param.remove_obj_fn) -+ dev->param.remove_obj_fn(obj); -+ -+ list_del_init(&obj->siblings); -+ obj->parent = NULL; -+ -+ yaffs_verify_dir(parent); -+} -+ -+void yaffs_add_obj_to_dir(struct yaffs_obj *directory, struct yaffs_obj *obj) -+{ -+ if (!directory) { -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR -+ ("tragedy: Trying to add an object to a null pointer directory" -+ TENDSTR))); -+ YBUG(); -+ return; -+ } -+ if (directory->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) { -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR -+ ("tragedy: Trying to add an object to a non-directory" -+ TENDSTR))); -+ YBUG(); -+ } -+ -+ if (obj->siblings.prev == NULL) { -+ /* Not initialised */ -+ YBUG(); -+ } -+ -+ yaffs_verify_dir(directory); -+ -+ yaffs_remove_obj_from_dir(obj); -+ -+ /* Now add it */ -+ list_add(&obj->siblings, &directory->variant.dir_variant.children); -+ obj->parent = directory; -+ -+ if (directory == obj->my_dev->unlinked_dir -+ || directory == obj->my_dev->del_dir) { -+ obj->unlinked = 1; -+ obj->my_dev->n_unlinked_files++; -+ obj->rename_allowed = 0; -+ } -+ -+ yaffs_verify_dir(directory); -+ yaffs_verify_obj_in_dir(obj); -+} -+ -+struct yaffs_obj *yaffs_find_by_name(struct yaffs_obj *directory, -+ const YCHAR * name) -+{ -+ int sum; -+ -+ struct list_head *i; -+ YCHAR buffer[YAFFS_MAX_NAME_LENGTH + 1]; -+ -+ struct yaffs_obj *l; -+ -+ if (!name) -+ return NULL; -+ -+ if (!directory) { -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR -+ ("tragedy: yaffs_find_by_name: null pointer directory" -+ TENDSTR))); -+ YBUG(); -+ return NULL; -+ } -+ if (directory->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) { -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR("tragedy: yaffs_find_by_name: non-directory" TENDSTR))); -+ YBUG(); -+ } -+ -+ sum = yaffs_calc_name_sum(name); -+ -+ list_for_each(i, &directory->variant.dir_variant.children) { -+ if (i) { -+ l = list_entry(i, struct yaffs_obj, siblings); -+ -+ if (l->parent != directory) -+ YBUG(); -+ -+ yaffs_check_obj_details_loaded(l); -+ -+ /* Special case for lost-n-found */ -+ if (l->obj_id == YAFFS_OBJECTID_LOSTNFOUND) { -+ if (!yaffs_strcmp(name, YAFFS_LOSTNFOUND_NAME)) -+ return l; -+ } else if (yaffs_sum_cmp(l->sum, sum) -+ || l->hdr_chunk <= 0) { -+ /* LostnFound chunk called Objxxx -+ * Do a real check -+ */ -+ yaffs_get_obj_name(l, buffer, -+ YAFFS_MAX_NAME_LENGTH + 1); -+ if (yaffs_strncmp -+ (name, buffer, YAFFS_MAX_NAME_LENGTH) == 0) -+ return l; -+ } -+ } -+ } -+ -+ return NULL; -+} -+ -+/* GetEquivalentObject dereferences any hard links to get to the -+ * actual object. -+ */ -+ -+struct yaffs_obj *yaffs_get_equivalent_obj(struct yaffs_obj *obj) -+{ -+ if (obj && obj->variant_type == YAFFS_OBJECT_TYPE_HARDLINK) { -+ /* We want the object id of the equivalent object, not this one */ -+ obj = obj->variant.hardlink_variant.equiv_obj; -+ yaffs_check_obj_details_loaded(obj); -+ } -+ return obj; -+} -+ -+/* -+ * A note or two on object names. -+ * * If the object name is missing, we then make one up in the form objnnn -+ * -+ * * ASCII names are stored in the object header's name field from byte zero -+ * * Unicode names are historically stored starting from byte zero. -+ * -+ * Then there are automatic Unicode names... -+ * The purpose of these is to save names in a way that can be read as -+ * ASCII or Unicode names as appropriate, thus allowing a Unicode and ASCII -+ * system to share files. -+ * -+ * These automatic unicode are stored slightly differently... -+ * - If the name can fit in the ASCII character space then they are saved as -+ * ascii names as per above. -+ * - If the name needs Unicode then the name is saved in Unicode -+ * starting at oh->name[1]. -+ -+ */ -+static void yaffs_fix_null_name(struct yaffs_obj *obj, YCHAR * name, -+ int buffer_size) -+{ -+ /* Create an object name if we could not find one. */ -+ if (yaffs_strnlen(name, YAFFS_MAX_NAME_LENGTH) == 0) { -+ YCHAR local_name[20]; -+ YCHAR num_string[20]; -+ YCHAR *x = &num_string[19]; -+ unsigned v = obj->obj_id; -+ num_string[19] = 0; -+ while (v > 0) { -+ x--; -+ *x = '0' + (v % 10); -+ v /= 10; -+ } -+ /* make up a name */ -+ yaffs_strcpy(local_name, YAFFS_LOSTNFOUND_PREFIX); -+ yaffs_strcat(local_name, x); -+ yaffs_strncpy(name, local_name, buffer_size - 1); -+ } -+} -+ -+static void yaffs_load_name_from_oh(struct yaffs_dev *dev, YCHAR * name, -+ const YCHAR * oh_name, int buff_size) -+{ -+#ifdef CONFIG_YAFFS_AUTO_UNICODE -+ if (dev->param.auto_unicode) { -+ if (*oh_name) { -+ /* It is an ASCII name, so do an ASCII to unicode conversion */ -+ const char *ascii_oh_name = (const char *)oh_name; -+ int n = buff_size - 1; -+ while (n > 0 && *ascii_oh_name) { -+ *name = *ascii_oh_name; -+ name++; -+ ascii_oh_name++; -+ n--; -+ } -+ } else { -+ yaffs_strncpy(name, oh_name + 1, buff_size - 1); -+ } -+ } else { -+#else -+ { -+#endif -+ yaffs_strncpy(name, oh_name, buff_size - 1); -+ } -+} -+ -+static void yaffs_load_oh_from_name(struct yaffs_dev *dev, YCHAR * oh_name, -+ const YCHAR * name) -+{ -+#ifdef CONFIG_YAFFS_AUTO_UNICODE -+ -+ int is_ascii; -+ YCHAR *w; -+ -+ if (dev->param.auto_unicode) { -+ -+ is_ascii = 1; -+ w = name; -+ -+ /* Figure out if the name will fit in ascii character set */ -+ while (is_ascii && *w) { -+ if ((*w) & 0xff00) -+ is_ascii = 0; -+ w++; -+ } -+ -+ if (is_ascii) { -+ /* It is an ASCII name, so do a unicode to ascii conversion */ -+ char *ascii_oh_name = (char *)oh_name; -+ int n = YAFFS_MAX_NAME_LENGTH - 1; -+ while (n > 0 && *name) { -+ *ascii_oh_name = *name; -+ name++; -+ ascii_oh_name++; -+ n--; -+ } -+ } else { -+ /* It is a unicode name, so save starting at the second YCHAR */ -+ *oh_name = 0; -+ yaffs_strncpy(oh_name + 1, name, -+ YAFFS_MAX_NAME_LENGTH - 2); -+ } -+ } else { -+#else -+ { -+#endif -+ yaffs_strncpy(oh_name, name, YAFFS_MAX_NAME_LENGTH - 1); -+ } -+ -+} -+ -+int yaffs_get_obj_name(struct yaffs_obj *obj, YCHAR * name, int buffer_size) -+{ -+ memset(name, 0, buffer_size * sizeof(YCHAR)); -+ -+ yaffs_check_obj_details_loaded(obj); -+ -+ if (obj->obj_id == YAFFS_OBJECTID_LOSTNFOUND) { -+ yaffs_strncpy(name, YAFFS_LOSTNFOUND_NAME, buffer_size - 1); -+ } -+#ifndef CONFIG_YAFFS_NO_SHORT_NAMES -+ else if (obj->short_name[0]) { -+ yaffs_strcpy(name, obj->short_name); -+ } -+#endif -+ else if (obj->hdr_chunk > 0) { -+ int result; -+ u8 *buffer = yaffs_get_temp_buffer(obj->my_dev, __LINE__); -+ -+ struct yaffs_obj_hdr *oh = (struct yaffs_obj_hdr *)buffer; -+ -+ memset(buffer, 0, obj->my_dev->data_bytes_per_chunk); -+ -+ if (obj->hdr_chunk > 0) { -+ result = yaffs_rd_chunk_tags_nand(obj->my_dev, -+ obj->hdr_chunk, -+ buffer, NULL); -+ } -+ yaffs_load_name_from_oh(obj->my_dev, name, oh->name, -+ buffer_size); -+ -+ yaffs_release_temp_buffer(obj->my_dev, buffer, __LINE__); -+ } -+ -+ yaffs_fix_null_name(obj, name, buffer_size); -+ -+ return yaffs_strnlen(name, YAFFS_MAX_NAME_LENGTH); -+} -+ -+int yaffs_get_obj_length(struct yaffs_obj *obj) -+{ -+ /* Dereference any hard linking */ -+ obj = yaffs_get_equivalent_obj(obj); -+ -+ if (obj->variant_type == YAFFS_OBJECT_TYPE_FILE) -+ return obj->variant.file_variant.file_size; -+ if (obj->variant_type == YAFFS_OBJECT_TYPE_SYMLINK) { -+ if (!obj->variant.symlink_variant.alias) -+ return 0; -+ return yaffs_strnlen(obj->variant.symlink_variant.alias, -+ YAFFS_MAX_ALIAS_LENGTH); -+ } else { -+ /* Only a directory should drop through to here */ -+ return obj->my_dev->data_bytes_per_chunk; -+ } -+} -+ -+int yaffs_get_obj_link_count(struct yaffs_obj *obj) -+{ -+ int count = 0; -+ struct list_head *i; -+ -+ if (!obj->unlinked) -+ count++; /* the object itself */ -+ -+ list_for_each(i, &obj->hard_links) -+ count++; /* add the hard links; */ -+ -+ return count; -+} -+ -+int yaffs_get_obj_inode(struct yaffs_obj *obj) -+{ -+ obj = yaffs_get_equivalent_obj(obj); -+ -+ return obj->obj_id; -+} -+ -+unsigned yaffs_get_obj_type(struct yaffs_obj *obj) -+{ -+ obj = yaffs_get_equivalent_obj(obj); -+ -+ switch (obj->variant_type) { -+ case YAFFS_OBJECT_TYPE_FILE: -+ return DT_REG; -+ break; -+ case YAFFS_OBJECT_TYPE_DIRECTORY: -+ return DT_DIR; -+ break; -+ case YAFFS_OBJECT_TYPE_SYMLINK: -+ return DT_LNK; -+ break; -+ case YAFFS_OBJECT_TYPE_HARDLINK: -+ return DT_REG; -+ break; -+ case YAFFS_OBJECT_TYPE_SPECIAL: -+ if (S_ISFIFO(obj->yst_mode)) -+ return DT_FIFO; -+ if (S_ISCHR(obj->yst_mode)) -+ return DT_CHR; -+ if (S_ISBLK(obj->yst_mode)) -+ return DT_BLK; -+ if (S_ISSOCK(obj->yst_mode)) -+ return DT_SOCK; -+ default: -+ return DT_REG; -+ break; -+ } -+} -+ -+YCHAR *yaffs_get_symlink_alias(struct yaffs_obj *obj) -+{ -+ obj = yaffs_get_equivalent_obj(obj); -+ if (obj->variant_type == YAFFS_OBJECT_TYPE_SYMLINK) -+ return yaffs_clone_str(obj->variant.symlink_variant.alias); -+ else -+ return yaffs_clone_str(_Y("")); -+} -+ -+static int yaffs_do_xattrib_mod(struct yaffs_obj *obj, int set, -+ const YCHAR * name, const void *value, int size, -+ int flags) -+{ -+ struct yaffs_xattr_mod xmod; -+ -+ int result; -+ -+ xmod.set = set; -+ xmod.name = name; -+ xmod.data = value; -+ xmod.size = size; -+ xmod.flags = flags; -+ xmod.result = -ENOSPC; -+ -+ result = yaffs_update_oh(obj, NULL, 0, 0, 0, &xmod); -+ -+ if (result > 0) -+ return xmod.result; -+ else -+ return -ENOSPC; -+} -+ -+static int yaffs_apply_xattrib_mod(struct yaffs_obj *obj, char *buffer, -+ struct yaffs_xattr_mod *xmod) -+{ -+ int retval = 0; -+ int x_offs = sizeof(struct yaffs_obj_hdr); -+ struct yaffs_dev *dev = obj->my_dev; -+ int x_size = dev->data_bytes_per_chunk - sizeof(struct yaffs_obj_hdr); -+ -+ char *x_buffer = buffer + x_offs; -+ -+ if (xmod->set) -+ retval = -+ nval_set(x_buffer, x_size, xmod->name, xmod->data, -+ xmod->size, xmod->flags); -+ else -+ retval = nval_del(x_buffer, x_size, xmod->name); -+ -+ obj->has_xattr = nval_hasvalues(x_buffer, x_size); -+ obj->xattr_known = 1; -+ -+ xmod->result = retval; -+ -+ return retval; -+} -+ -+static int yaffs_do_xattrib_fetch(struct yaffs_obj *obj, const YCHAR * name, -+ void *value, int size) -+{ -+ char *buffer = NULL; -+ int result; -+ struct yaffs_ext_tags tags; -+ struct yaffs_dev *dev = obj->my_dev; -+ int x_offs = sizeof(struct yaffs_obj_hdr); -+ int x_size = dev->data_bytes_per_chunk - sizeof(struct yaffs_obj_hdr); -+ -+ char *x_buffer; -+ -+ int retval = 0; -+ -+ if (obj->hdr_chunk < 1) -+ return -ENODATA; -+ -+ /* If we know that the object has no xattribs then don't do all the -+ * reading and parsing. -+ */ -+ if (obj->xattr_known && !obj->has_xattr) { -+ if (name) -+ return -ENODATA; -+ else -+ return 0; -+ } -+ -+ buffer = (char *)yaffs_get_temp_buffer(dev, __LINE__); -+ if (!buffer) -+ return -ENOMEM; -+ -+ result = -+ yaffs_rd_chunk_tags_nand(dev, obj->hdr_chunk, (u8 *) buffer, &tags); -+ -+ if (result != YAFFS_OK) -+ retval = -ENOENT; -+ else { -+ x_buffer = buffer + x_offs; -+ -+ if (!obj->xattr_known) { -+ obj->has_xattr = nval_hasvalues(x_buffer, x_size); -+ obj->xattr_known = 1; -+ } -+ -+ if (name) -+ retval = nval_get(x_buffer, x_size, name, value, size); -+ else -+ retval = nval_list(x_buffer, x_size, value, size); -+ } -+ yaffs_release_temp_buffer(dev, (u8 *) buffer, __LINE__); -+ return retval; -+} -+ -+int yaffs_set_xattrib(struct yaffs_obj *obj, const YCHAR * name, -+ const void *value, int size, int flags) -+{ -+ return yaffs_do_xattrib_mod(obj, 1, name, value, size, flags); -+} -+ -+int yaffs_remove_xattrib(struct yaffs_obj *obj, const YCHAR * name) -+{ -+ return yaffs_do_xattrib_mod(obj, 0, name, NULL, 0, 0); -+} -+ -+int yaffs_get_xattrib(struct yaffs_obj *obj, const YCHAR * name, void *value, -+ int size) -+{ -+ return yaffs_do_xattrib_fetch(obj, name, value, size); -+} -+ -+int yaffs_list_xattrib(struct yaffs_obj *obj, char *buffer, int size) -+{ -+ return yaffs_do_xattrib_fetch(obj, NULL, buffer, size); -+} -+ -+/*---------------------------- Initialisation code -------------------------------------- */ -+ -+static int yaffs_check_dev_fns(const struct yaffs_dev *dev) -+{ -+ -+ /* Common functions, gotta have */ -+ if (!dev->param.erase_fn || !dev->param.initialise_flash_fn) -+ return 0; -+ -+#ifdef CONFIG_YAFFS_YAFFS2 -+ -+ /* Can use the "with tags" style interface for yaffs1 or yaffs2 */ -+ if (dev->param.write_chunk_tags_fn && -+ dev->param.read_chunk_tags_fn && -+ !dev->param.write_chunk_fn && -+ !dev->param.read_chunk_fn && -+ dev->param.bad_block_fn && dev->param.query_block_fn) -+ return 1; -+#endif -+ -+ /* Can use the "spare" style interface for yaffs1 */ -+ if (!dev->param.is_yaffs2 && -+ !dev->param.write_chunk_tags_fn && -+ !dev->param.read_chunk_tags_fn && -+ dev->param.write_chunk_fn && -+ dev->param.read_chunk_fn && -+ !dev->param.bad_block_fn && !dev->param.query_block_fn) -+ return 1; -+ -+ return 0; /* bad */ -+} -+ -+static int yaffs_create_initial_dir(struct yaffs_dev *dev) -+{ -+ /* Initialise the unlinked, deleted, root and lost and found directories */ -+ -+ dev->lost_n_found = dev->root_dir = NULL; -+ dev->unlinked_dir = dev->del_dir = NULL; -+ -+ dev->unlinked_dir = -+ yaffs_create_fake_dir(dev, YAFFS_OBJECTID_UNLINKED, S_IFDIR); -+ -+ dev->del_dir = -+ yaffs_create_fake_dir(dev, YAFFS_OBJECTID_DELETED, S_IFDIR); -+ -+ dev->root_dir = -+ yaffs_create_fake_dir(dev, YAFFS_OBJECTID_ROOT, -+ YAFFS_ROOT_MODE | S_IFDIR); -+ dev->lost_n_found = -+ yaffs_create_fake_dir(dev, YAFFS_OBJECTID_LOSTNFOUND, -+ YAFFS_LOSTNFOUND_MODE | S_IFDIR); -+ -+ if (dev->lost_n_found && dev->root_dir && dev->unlinked_dir -+ && dev->del_dir) { -+ yaffs_add_obj_to_dir(dev->root_dir, dev->lost_n_found); -+ return YAFFS_OK; -+ } -+ -+ return YAFFS_FAIL; -+} -+ -+int yaffs_guts_initialise(struct yaffs_dev *dev) -+{ -+ int init_failed = 0; -+ unsigned x; -+ int bits; -+ -+ T(YAFFS_TRACE_TRACING, -+ (TSTR("yaffs: yaffs_guts_initialise()" TENDSTR))); -+ -+ /* Check stuff that must be set */ -+ -+ if (!dev) { -+ T(YAFFS_TRACE_ALWAYS, (TSTR("yaffs: Need a device" TENDSTR))); -+ return YAFFS_FAIL; -+ } -+ -+ dev->internal_start_block = dev->param.start_block; -+ dev->internal_end_block = dev->param.end_block; -+ dev->block_offset = 0; -+ dev->chunk_offset = 0; -+ dev->n_free_chunks = 0; -+ -+ dev->gc_block = 0; -+ -+ if (dev->param.start_block == 0) { -+ dev->internal_start_block = dev->param.start_block + 1; -+ dev->internal_end_block = dev->param.end_block + 1; -+ dev->block_offset = 1; -+ dev->chunk_offset = dev->param.chunks_per_block; -+ } -+ -+ /* Check geometry parameters. */ -+ -+ if ((!dev->param.inband_tags && dev->param.is_yaffs2 && dev->param.total_bytes_per_chunk < 1024) || (!dev->param.is_yaffs2 && dev->param.total_bytes_per_chunk < 512) || (dev->param.inband_tags && !dev->param.is_yaffs2) || dev->param.chunks_per_block < 2 || dev->param.n_reserved_blocks < 2 || dev->internal_start_block <= 0 || dev->internal_end_block <= 0 || dev->internal_end_block <= (dev->internal_start_block + dev->param.n_reserved_blocks + 2)) { /* otherwise it is too small */ -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR -+ ("yaffs: NAND geometry problems: chunk size %d, type is yaffs%s, inband_tags %d " -+ TENDSTR), dev->param.total_bytes_per_chunk, -+ dev->param.is_yaffs2 ? "2" : "", dev->param.inband_tags)); -+ return YAFFS_FAIL; -+ } -+ -+ if (yaffs_init_nand(dev) != YAFFS_OK) { -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR("yaffs: InitialiseNAND failed" TENDSTR))); -+ return YAFFS_FAIL; -+ } -+ -+ /* Sort out space for inband tags, if required */ -+ if (dev->param.inband_tags) -+ dev->data_bytes_per_chunk = -+ dev->param.total_bytes_per_chunk - -+ sizeof(struct yaffs_packed_tags2_tags_only); -+ else -+ dev->data_bytes_per_chunk = dev->param.total_bytes_per_chunk; -+ -+ /* Got the right mix of functions? */ -+ if (!yaffs_check_dev_fns(dev)) { -+ /* Function missing */ -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR -+ ("yaffs: device function(s) missing or wrong\n" TENDSTR))); -+ -+ return YAFFS_FAIL; -+ } -+ -+ if (dev->is_mounted) { -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR("yaffs: device already mounted\n" TENDSTR))); -+ return YAFFS_FAIL; -+ } -+ -+ /* Finished with most checks. One or two more checks happen later on too. */ -+ -+ dev->is_mounted = 1; -+ -+ /* OK now calculate a few things for the device */ -+ -+ /* -+ * Calculate all the chunk size manipulation numbers: -+ */ -+ x = dev->data_bytes_per_chunk; -+ /* We always use dev->chunk_shift and dev->chunk_div */ -+ dev->chunk_shift = calc_shifts(x); -+ x >>= dev->chunk_shift; -+ dev->chunk_div = x; -+ /* We only use chunk mask if chunk_div is 1 */ -+ dev->chunk_mask = (1 << dev->chunk_shift) - 1; -+ -+ /* -+ * Calculate chunk_grp_bits. -+ * We need to find the next power of 2 > than internal_end_block -+ */ -+ -+ x = dev->param.chunks_per_block * (dev->internal_end_block + 1); -+ -+ bits = calc_shifts_ceiling(x); -+ -+ /* Set up tnode width if wide tnodes are enabled. */ -+ if (!dev->param.wide_tnodes_disabled) { -+ /* bits must be even so that we end up with 32-bit words */ -+ if (bits & 1) -+ bits++; -+ if (bits < 16) -+ dev->tnode_width = 16; -+ else -+ dev->tnode_width = bits; -+ } else { -+ dev->tnode_width = 16; -+ } -+ -+ dev->tnode_mask = (1 << dev->tnode_width) - 1; -+ -+ /* Level0 Tnodes are 16 bits or wider (if wide tnodes are enabled), -+ * so if the bitwidth of the -+ * chunk range we're using is greater than 16 we need -+ * to figure out chunk shift and chunk_grp_size -+ */ -+ -+ if (bits <= dev->tnode_width) -+ dev->chunk_grp_bits = 0; -+ else -+ dev->chunk_grp_bits = bits - dev->tnode_width; -+ -+ dev->tnode_size = (dev->tnode_width * YAFFS_NTNODES_LEVEL0) / 8; -+ if (dev->tnode_size < sizeof(struct yaffs_tnode)) -+ dev->tnode_size = sizeof(struct yaffs_tnode); -+ -+ dev->chunk_grp_size = 1 << dev->chunk_grp_bits; -+ -+ if (dev->param.chunks_per_block < dev->chunk_grp_size) { -+ /* We have a problem because the soft delete won't work if -+ * the chunk group size > chunks per block. -+ * This can be remedied by using larger "virtual blocks". -+ */ -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR("yaffs: chunk group too large\n" TENDSTR))); -+ -+ return YAFFS_FAIL; -+ } -+ -+ /* OK, we've finished verifying the device, lets continue with initialisation */ -+ -+ /* More device initialisation */ -+ dev->all_gcs = 0; -+ dev->passive_gc_count = 0; -+ dev->oldest_dirty_gc_count = 0; -+ dev->bg_gcs = 0; -+ dev->gc_block_finder = 0; -+ dev->buffered_block = -1; -+ dev->doing_buffered_block_rewrite = 0; -+ dev->n_deleted_files = 0; -+ dev->n_bg_deletions = 0; -+ dev->n_unlinked_files = 0; -+ dev->n_ecc_fixed = 0; -+ dev->n_ecc_unfixed = 0; -+ dev->n_tags_ecc_fixed = 0; -+ dev->n_tags_ecc_unfixed = 0; -+ dev->n_erase_failures = 0; -+ dev->n_erased_blocks = 0; -+ dev->gc_disable = 0; -+ dev->has_pending_prioritised_gc = 1; /* Assume the worst for now, will get fixed on first GC */ -+ INIT_LIST_HEAD(&dev->dirty_dirs); -+ dev->oldest_dirty_seq = 0; -+ dev->oldest_dirty_block = 0; -+ -+ /* Initialise temporary buffers and caches. */ -+ if (!yaffs_init_tmp_buffers(dev)) -+ init_failed = 1; -+ -+ dev->cache = NULL; -+ dev->gc_cleanup_list = NULL; -+ -+ if (!init_failed && dev->param.n_caches > 0) { -+ int i; -+ void *buf; -+ int cache_bytes = -+ dev->param.n_caches * sizeof(struct yaffs_cache); -+ -+ if (dev->param.n_caches > YAFFS_MAX_SHORT_OP_CACHES) -+ dev->param.n_caches = YAFFS_MAX_SHORT_OP_CACHES; -+ -+ dev->cache = YMALLOC(cache_bytes); -+ -+ buf = (u8 *) dev->cache; -+ -+ if (dev->cache) -+ memset(dev->cache, 0, cache_bytes); -+ -+ for (i = 0; i < dev->param.n_caches && buf; i++) { -+ dev->cache[i].object = NULL; -+ dev->cache[i].last_use = 0; -+ dev->cache[i].dirty = 0; -+ dev->cache[i].data = buf = -+ YMALLOC_DMA(dev->param.total_bytes_per_chunk); -+ } -+ if (!buf) -+ init_failed = 1; -+ -+ dev->cache_last_use = 0; -+ } -+ -+ dev->cache_hits = 0; -+ -+ if (!init_failed) { -+ dev->gc_cleanup_list = -+ YMALLOC(dev->param.chunks_per_block * sizeof(u32)); -+ if (!dev->gc_cleanup_list) -+ init_failed = 1; -+ } -+ -+ if (dev->param.is_yaffs2) -+ dev->param.use_header_file_size = 1; -+ -+ if (!init_failed && !yaffs_init_blocks(dev)) -+ init_failed = 1; -+ -+ yaffs_init_tnodes_and_objs(dev); -+ -+ if (!init_failed && !yaffs_create_initial_dir(dev)) -+ init_failed = 1; -+ -+ if (!init_failed) { -+ /* Now scan the flash. */ -+ if (dev->param.is_yaffs2) { -+ if (yaffs2_checkpt_restore(dev)) { -+ yaffs_check_obj_details_loaded(dev->root_dir); -+ T(YAFFS_TRACE_CHECKPOINT | YAFFS_TRACE_MOUNT, -+ (TSTR -+ ("yaffs: restored from checkpoint" -+ TENDSTR))); -+ } else { -+ -+ /* Clean up the mess caused by an aborted checkpoint load -+ * and scan backwards. -+ */ -+ yaffs_deinit_blocks(dev); -+ -+ yaffs_deinit_tnodes_and_objs(dev); -+ -+ dev->n_erased_blocks = 0; -+ dev->n_free_chunks = 0; -+ dev->alloc_block = -1; -+ dev->alloc_page = -1; -+ dev->n_deleted_files = 0; -+ dev->n_unlinked_files = 0; -+ dev->n_bg_deletions = 0; -+ -+ if (!init_failed && !yaffs_init_blocks(dev)) -+ init_failed = 1; -+ -+ yaffs_init_tnodes_and_objs(dev); -+ -+ if (!init_failed -+ && !yaffs_create_initial_dir(dev)) -+ init_failed = 1; -+ -+ if (!init_failed && !yaffs2_scan_backwards(dev)) -+ init_failed = 1; -+ } -+ } else if (!yaffs1_scan(dev)) { -+ init_failed = 1; -+ } -+ -+ yaffs_strip_deleted_objs(dev); -+ yaffs_fix_hanging_objs(dev); -+ if (dev->param.empty_lost_n_found) -+ yaffs_empty_l_n_f(dev); -+ } -+ -+ if (init_failed) { -+ /* Clean up the mess */ -+ T(YAFFS_TRACE_TRACING, -+ (TSTR("yaffs: yaffs_guts_initialise() aborted.\n" TENDSTR))); -+ -+ yaffs_deinitialise(dev); -+ return YAFFS_FAIL; -+ } -+ -+ /* Zero out stats */ -+ dev->n_page_reads = 0; -+ dev->n_page_writes = 0; -+ dev->n_erasures = 0; -+ dev->n_gc_copies = 0; -+ dev->n_retired_writes = 0; -+ -+ dev->n_retired_blocks = 0; -+ -+ yaffs_verify_free_chunks(dev); -+ yaffs_verify_blocks(dev); -+ -+ /* Clean up any aborted checkpoint data */ -+ if (!dev->is_checkpointed && dev->blocks_in_checkpt > 0) -+ yaffs2_checkpt_invalidate(dev); -+ -+ T(YAFFS_TRACE_TRACING, -+ (TSTR("yaffs: yaffs_guts_initialise() done.\n" TENDSTR))); -+ return YAFFS_OK; -+ -+} -+ -+void yaffs_deinitialise(struct yaffs_dev *dev) -+{ -+ if (dev->is_mounted) { -+ int i; -+ -+ yaffs_deinit_blocks(dev); -+ yaffs_deinit_tnodes_and_objs(dev); -+ if (dev->param.n_caches > 0 && dev->cache) { -+ -+ for (i = 0; i < dev->param.n_caches; i++) { -+ if (dev->cache[i].data) -+ YFREE(dev->cache[i].data); -+ dev->cache[i].data = NULL; -+ } -+ -+ YFREE(dev->cache); -+ dev->cache = NULL; -+ } -+ -+ YFREE(dev->gc_cleanup_list); -+ -+ for (i = 0; i < YAFFS_N_TEMP_BUFFERS; i++) -+ YFREE(dev->temp_buffer[i].buffer); -+ -+ dev->is_mounted = 0; -+ -+ if (dev->param.deinitialise_flash_fn) -+ dev->param.deinitialise_flash_fn(dev); -+ } -+} -+ -+int yaffs_count_free_chunks(struct yaffs_dev *dev) -+{ -+ int n_free = 0; -+ int b; -+ -+ struct yaffs_block_info *blk; -+ -+ blk = dev->block_info; -+ for (b = dev->internal_start_block; b <= dev->internal_end_block; b++) { -+ switch (blk->block_state) { -+ case YAFFS_BLOCK_STATE_EMPTY: -+ case YAFFS_BLOCK_STATE_ALLOCATING: -+ case YAFFS_BLOCK_STATE_COLLECTING: -+ case YAFFS_BLOCK_STATE_FULL: -+ n_free += -+ (dev->param.chunks_per_block - blk->pages_in_use + -+ blk->soft_del_pages); -+ break; -+ default: -+ break; -+ } -+ blk++; -+ } -+ -+ return n_free; -+} -+ -+int yaffs_get_n_free_chunks(struct yaffs_dev *dev) -+{ -+ /* This is what we report to the outside world */ -+ -+ int n_free; -+ int n_dirty_caches; -+ int blocks_for_checkpt; -+ int i; -+ -+ n_free = dev->n_free_chunks; -+ n_free += dev->n_deleted_files; -+ -+ /* Now count the number of dirty chunks in the cache and subtract those */ -+ -+ for (n_dirty_caches = 0, i = 0; i < dev->param.n_caches; i++) { -+ if (dev->cache[i].dirty) -+ n_dirty_caches++; -+ } -+ -+ n_free -= n_dirty_caches; -+ -+ n_free -= -+ ((dev->param.n_reserved_blocks + 1) * dev->param.chunks_per_block); -+ -+ /* Now we figure out how much to reserve for the checkpoint and report that... */ -+ blocks_for_checkpt = yaffs_calc_checkpt_blocks_required(dev); -+ -+ n_free -= (blocks_for_checkpt * dev->param.chunks_per_block); -+ -+ if (n_free < 0) -+ n_free = 0; -+ -+ return n_free; -+ -+} -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_guts.h linux-2.6.36/fs/yaffs2/yaffs_guts.h ---- linux-2.6.36.orig/fs/yaffs2/yaffs_guts.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_guts.h 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,914 @@ -+/* -+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU Lesser General Public License version 2.1 as -+ * published by the Free Software Foundation. -+ * -+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. -+ */ -+ -+#ifndef __YAFFS_GUTS_H__ -+#define __YAFFS_GUTS_H__ -+ -+#include "yportenv.h" -+ -+#define YAFFS_OK 1 -+#define YAFFS_FAIL 0 -+ -+/* Give us a Y=0x59, -+ * Give us an A=0x41, -+ * Give us an FF=0xFF -+ * Give us an S=0x53 -+ * And what have we got... -+ */ -+#define YAFFS_MAGIC 0x5941FF53 -+ -+#define YAFFS_NTNODES_LEVEL0 16 -+#define YAFFS_TNODES_LEVEL0_BITS 4 -+#define YAFFS_TNODES_LEVEL0_MASK 0xf -+ -+#define YAFFS_NTNODES_INTERNAL (YAFFS_NTNODES_LEVEL0 / 2) -+#define YAFFS_TNODES_INTERNAL_BITS (YAFFS_TNODES_LEVEL0_BITS - 1) -+#define YAFFS_TNODES_INTERNAL_MASK 0x7 -+#define YAFFS_TNODES_MAX_LEVEL 6 -+ -+#ifndef CONFIG_YAFFS_NO_YAFFS1 -+#define YAFFS_BYTES_PER_SPARE 16 -+#define YAFFS_BYTES_PER_CHUNK 512 -+#define YAFFS_CHUNK_SIZE_SHIFT 9 -+#define YAFFS_CHUNKS_PER_BLOCK 32 -+#define YAFFS_BYTES_PER_BLOCK (YAFFS_CHUNKS_PER_BLOCK*YAFFS_BYTES_PER_CHUNK) -+#endif -+ -+#define YAFFS_MIN_YAFFS2_CHUNK_SIZE 1024 -+#define YAFFS_MIN_YAFFS2_SPARE_SIZE 32 -+ -+#define YAFFS_MAX_CHUNK_ID 0x000FFFFF -+ -+#define YAFFS_ALLOCATION_NOBJECTS 100 -+#define YAFFS_ALLOCATION_NTNODES 100 -+#define YAFFS_ALLOCATION_NLINKS 100 -+ -+#define YAFFS_NOBJECT_BUCKETS 256 -+ -+#define YAFFS_OBJECT_SPACE 0x40000 -+#define YAFFS_MAX_OBJECT_ID (YAFFS_OBJECT_SPACE -1) -+ -+#define YAFFS_CHECKPOINT_VERSION 4 -+ -+#ifdef CONFIG_YAFFS_UNICODE -+#define YAFFS_MAX_NAME_LENGTH 127 -+#define YAFFS_MAX_ALIAS_LENGTH 79 -+#else -+#define YAFFS_MAX_NAME_LENGTH 255 -+#define YAFFS_MAX_ALIAS_LENGTH 159 -+#endif -+ -+#define YAFFS_SHORT_NAME_LENGTH 15 -+ -+/* Some special object ids for pseudo objects */ -+#define YAFFS_OBJECTID_ROOT 1 -+#define YAFFS_OBJECTID_LOSTNFOUND 2 -+#define YAFFS_OBJECTID_UNLINKED 3 -+#define YAFFS_OBJECTID_DELETED 4 -+ -+/* Pseudo object ids for checkpointing */ -+#define YAFFS_OBJECTID_SB_HEADER 0x10 -+#define YAFFS_OBJECTID_CHECKPOINT_DATA 0x20 -+#define YAFFS_SEQUENCE_CHECKPOINT_DATA 0x21 -+ -+#define YAFFS_MAX_SHORT_OP_CACHES 20 -+ -+#define YAFFS_N_TEMP_BUFFERS 6 -+ -+/* We limit the number attempts at sucessfully saving a chunk of data. -+ * Small-page devices have 32 pages per block; large-page devices have 64. -+ * Default to something in the order of 5 to 10 blocks worth of chunks. -+ */ -+#define YAFFS_WR_ATTEMPTS (5*64) -+ -+/* Sequence numbers are used in YAFFS2 to determine block allocation order. -+ * The range is limited slightly to help distinguish bad numbers from good. -+ * This also allows us to perhaps in the future use special numbers for -+ * special purposes. -+ * EFFFFF00 allows the allocation of 8 blocks per second (~1Mbytes) for 15 years, -+ * and is a larger number than the lifetime of a 2GB device. -+ */ -+#define YAFFS_LOWEST_SEQUENCE_NUMBER 0x00001000 -+#define YAFFS_HIGHEST_SEQUENCE_NUMBER 0xEFFFFF00 -+ -+/* Special sequence number for bad block that failed to be marked bad */ -+#define YAFFS_SEQUENCE_BAD_BLOCK 0xFFFF0000 -+ -+/* ChunkCache is used for short read/write operations.*/ -+struct yaffs_cache { -+ struct yaffs_obj *object; -+ int chunk_id; -+ int last_use; -+ int dirty; -+ int n_bytes; /* Only valid if the cache is dirty */ -+ int locked; /* Can't push out or flush while locked. */ -+ u8 *data; -+}; -+ -+/* Tags structures in RAM -+ * NB This uses bitfield. Bitfields should not straddle a u32 boundary otherwise -+ * the structure size will get blown out. -+ */ -+ -+#ifndef CONFIG_YAFFS_NO_YAFFS1 -+struct yaffs_tags { -+ unsigned chunk_id:20; -+ unsigned serial_number:2; -+ unsigned n_bytes_lsb:10; -+ unsigned obj_id:18; -+ unsigned ecc:12; -+ unsigned n_bytes_msb:2; -+}; -+ -+union yaffs_tags_union { -+ struct yaffs_tags as_tags; -+ u8 as_bytes[8]; -+}; -+ -+#endif -+ -+/* Stuff used for extended tags in YAFFS2 */ -+ -+enum yaffs_ecc_result { -+ YAFFS_ECC_RESULT_UNKNOWN, -+ YAFFS_ECC_RESULT_NO_ERROR, -+ YAFFS_ECC_RESULT_FIXED, -+ YAFFS_ECC_RESULT_UNFIXED -+}; -+ -+enum yaffs_obj_type { -+ YAFFS_OBJECT_TYPE_UNKNOWN, -+ YAFFS_OBJECT_TYPE_FILE, -+ YAFFS_OBJECT_TYPE_SYMLINK, -+ YAFFS_OBJECT_TYPE_DIRECTORY, -+ YAFFS_OBJECT_TYPE_HARDLINK, -+ YAFFS_OBJECT_TYPE_SPECIAL -+}; -+ -+#define YAFFS_OBJECT_TYPE_MAX YAFFS_OBJECT_TYPE_SPECIAL -+ -+struct yaffs_ext_tags { -+ -+ unsigned validity0; -+ unsigned chunk_used; /* Status of the chunk: used or unused */ -+ unsigned obj_id; /* If 0 then this is not part of an object (unused) */ -+ unsigned chunk_id; /* If 0 then this is a header, else a data chunk */ -+ unsigned n_bytes; /* Only valid for data chunks */ -+ -+ /* The following stuff only has meaning when we read */ -+ enum yaffs_ecc_result ecc_result; -+ unsigned block_bad; -+ -+ /* YAFFS 1 stuff */ -+ unsigned is_deleted; /* The chunk is marked deleted */ -+ unsigned serial_number; /* Yaffs1 2-bit serial number */ -+ -+ /* YAFFS2 stuff */ -+ unsigned seq_number; /* The sequence number of this block */ -+ -+ /* Extra info if this is an object header (YAFFS2 only) */ -+ -+ unsigned extra_available; /* There is extra info available if this is not zero */ -+ unsigned extra_parent_id; /* The parent object */ -+ unsigned extra_is_shrink; /* Is it a shrink header? */ -+ unsigned extra_shadows; /* Does this shadow another object? */ -+ -+ enum yaffs_obj_type extra_obj_type; /* What object type? */ -+ -+ unsigned extra_length; /* Length if it is a file */ -+ unsigned extra_equiv_id; /* Equivalent object Id if it is a hard link */ -+ -+ unsigned validity1; -+ -+}; -+ -+/* Spare structure for YAFFS1 */ -+struct yaffs_spare { -+ u8 tb0; -+ u8 tb1; -+ u8 tb2; -+ u8 tb3; -+ u8 page_status; /* set to 0 to delete the chunk */ -+ u8 block_status; -+ u8 tb4; -+ u8 tb5; -+ u8 ecc1[3]; -+ u8 tb6; -+ u8 tb7; -+ u8 ecc2[3]; -+}; -+ -+/*Special structure for passing through to mtd */ -+struct yaffs_nand_spare { -+ struct yaffs_spare spare; -+ int eccres1; -+ int eccres2; -+}; -+ -+/* Block data in RAM */ -+ -+enum yaffs_block_state { -+ YAFFS_BLOCK_STATE_UNKNOWN = 0, -+ -+ YAFFS_BLOCK_STATE_SCANNING, -+ /* Being scanned */ -+ -+ YAFFS_BLOCK_STATE_NEEDS_SCANNING, -+ /* The block might have something on it (ie it is allocating or full, perhaps empty) -+ * but it needs to be scanned to determine its true state. -+ * This state is only valid during scanning. -+ * NB We tolerate empty because the pre-scanner might be incapable of deciding -+ * However, if this state is returned on a YAFFS2 device, then we expect a sequence number -+ */ -+ -+ YAFFS_BLOCK_STATE_EMPTY, -+ /* This block is empty */ -+ -+ YAFFS_BLOCK_STATE_ALLOCATING, -+ /* This block is partially allocated. -+ * At least one page holds valid data. -+ * This is the one currently being used for page -+ * allocation. Should never be more than one of these. -+ * If a block is only partially allocated at mount it is treated as full. -+ */ -+ -+ YAFFS_BLOCK_STATE_FULL, -+ /* All the pages in this block have been allocated. -+ * If a block was only partially allocated when mounted we treat -+ * it as fully allocated. -+ */ -+ -+ YAFFS_BLOCK_STATE_DIRTY, -+ /* The block was full and now all chunks have been deleted. -+ * Erase me, reuse me. -+ */ -+ -+ YAFFS_BLOCK_STATE_CHECKPOINT, -+ /* This block is assigned to holding checkpoint data. */ -+ -+ YAFFS_BLOCK_STATE_COLLECTING, -+ /* This block is being garbage collected */ -+ -+ YAFFS_BLOCK_STATE_DEAD -+ /* This block has failed and is not in use */ -+}; -+ -+#define YAFFS_NUMBER_OF_BLOCK_STATES (YAFFS_BLOCK_STATE_DEAD + 1) -+ -+struct yaffs_block_info { -+ -+ int soft_del_pages:10; /* number of soft deleted pages */ -+ int pages_in_use:10; /* number of pages in use */ -+ unsigned block_state:4; /* One of the above block states. NB use unsigned because enum is sometimes an int */ -+ u32 needs_retiring:1; /* Data has failed on this block, need to get valid data off */ -+ /* and retire the block. */ -+ u32 skip_erased_check:1; /* If this is set we can skip the erased check on this block */ -+ u32 gc_prioritise:1; /* An ECC check or blank check has failed on this block. -+ It should be prioritised for GC */ -+ u32 chunk_error_strikes:3; /* How many times we've had ecc etc failures on this block and tried to reuse it */ -+ -+#ifdef CONFIG_YAFFS_YAFFS2 -+ u32 has_shrink_hdr:1; /* This block has at least one shrink object header */ -+ u32 seq_number; /* block sequence number for yaffs2 */ -+#endif -+ -+}; -+ -+/* -------------------------- Object structure -------------------------------*/ -+/* This is the object structure as stored on NAND */ -+ -+struct yaffs_obj_hdr { -+ enum yaffs_obj_type type; -+ -+ /* Apply to everything */ -+ int parent_obj_id; -+ u16 sum_no_longer_used; /* checksum of name. No longer used */ -+ YCHAR name[YAFFS_MAX_NAME_LENGTH + 1]; -+ -+ /* The following apply to directories, files, symlinks - not hard links */ -+ u32 yst_mode; /* protection */ -+ -+ u32 yst_uid; -+ u32 yst_gid; -+ u32 yst_atime; -+ u32 yst_mtime; -+ u32 yst_ctime; -+ -+ /* File size applies to files only */ -+ int file_size; -+ -+ /* Equivalent object id applies to hard links only. */ -+ int equiv_id; -+ -+ /* Alias is for symlinks only. */ -+ YCHAR alias[YAFFS_MAX_ALIAS_LENGTH + 1]; -+ -+ u32 yst_rdev; /* device stuff for block and char devices (major/min) */ -+ -+ u32 win_ctime[2]; -+ u32 win_atime[2]; -+ u32 win_mtime[2]; -+ -+ u32 inband_shadowed_obj_id; -+ u32 inband_is_shrink; -+ -+ u32 reserved[2]; -+ int shadows_obj; /* This object header shadows the specified object if > 0 */ -+ -+ /* is_shrink applies to object headers written when we shrink the file (ie resize) */ -+ u32 is_shrink; -+ -+}; -+ -+/*--------------------------- Tnode -------------------------- */ -+ -+struct yaffs_tnode { -+ struct yaffs_tnode *internal[YAFFS_NTNODES_INTERNAL]; -+}; -+ -+/*------------------------ Object -----------------------------*/ -+/* An object can be one of: -+ * - a directory (no data, has children links -+ * - a regular file (data.... not prunes :->). -+ * - a symlink [symbolic link] (the alias). -+ * - a hard link -+ */ -+ -+struct yaffs_file_var { -+ u32 file_size; -+ u32 scanned_size; -+ u32 shrink_size; -+ int top_level; -+ struct yaffs_tnode *top; -+}; -+ -+struct yaffs_dir_var { -+ struct list_head children; /* list of child links */ -+ struct list_head dirty; /* Entry for list of dirty directories */ -+}; -+ -+struct yaffs_symlink_var { -+ YCHAR *alias; -+}; -+ -+struct yaffs_hardlink_var { -+ struct yaffs_obj *equiv_obj; -+ u32 equiv_id; -+}; -+ -+union yaffs_obj_var { -+ struct yaffs_file_var file_variant; -+ struct yaffs_dir_var dir_variant; -+ struct yaffs_symlink_var symlink_variant; -+ struct yaffs_hardlink_var hardlink_variant; -+}; -+ -+struct yaffs_obj { -+ u8 deleted:1; /* This should only apply to unlinked files. */ -+ u8 soft_del:1; /* it has also been soft deleted */ -+ u8 unlinked:1; /* An unlinked file. The file should be in the unlinked directory. */ -+ u8 fake:1; /* A fake object has no presence on NAND. */ -+ u8 rename_allowed:1; /* Some objects are not allowed to be renamed. */ -+ u8 unlink_allowed:1; -+ u8 dirty:1; /* the object needs to be written to flash */ -+ u8 valid:1; /* When the file system is being loaded up, this -+ * object might be created before the data -+ * is available (ie. file data records appear before the header). -+ */ -+ u8 lazy_loaded:1; /* This object has been lazy loaded and is missing some detail */ -+ -+ u8 defered_free:1; /* For Linux kernel. Object is removed from NAND, but is -+ * still in the inode cache. Free of object is defered. -+ * until the inode is released. -+ */ -+ u8 being_created:1; /* This object is still being created so skip some checks. */ -+ u8 is_shadowed:1; /* This object is shadowed on the way to being renamed. */ -+ -+ u8 xattr_known:1; /* We know if this has object has xattribs or not. */ -+ u8 has_xattr:1; /* This object has xattribs. Valid if xattr_known. */ -+ -+ u8 serial; /* serial number of chunk in NAND. Cached here */ -+ u16 sum; /* sum of the name to speed searching */ -+ -+ struct yaffs_dev *my_dev; /* The device I'm on */ -+ -+ struct list_head hash_link; /* list of objects in this hash bucket */ -+ -+ struct list_head hard_links; /* all the equivalent hard linked objects */ -+ -+ /* directory structure stuff */ -+ /* also used for linking up the free list */ -+ struct yaffs_obj *parent; -+ struct list_head siblings; -+ -+ /* Where's my object header in NAND? */ -+ int hdr_chunk; -+ -+ int n_data_chunks; /* Number of data chunks attached to the file. */ -+ -+ u32 obj_id; /* the object id value */ -+ -+ u32 yst_mode; -+ -+#ifndef CONFIG_YAFFS_NO_SHORT_NAMES -+ YCHAR short_name[YAFFS_SHORT_NAME_LENGTH + 1]; -+#endif -+ -+#ifdef CONFIG_YAFFS_WINCE -+ u32 win_ctime[2]; -+ u32 win_mtime[2]; -+ u32 win_atime[2]; -+#else -+ u32 yst_uid; -+ u32 yst_gid; -+ u32 yst_atime; -+ u32 yst_mtime; -+ u32 yst_ctime; -+#endif -+ -+ u32 yst_rdev; -+ -+ void *my_inode; -+ -+ enum yaffs_obj_type variant_type; -+ -+ union yaffs_obj_var variant; -+ -+}; -+ -+struct yaffs_obj_bucket { -+ struct list_head list; -+ int count; -+}; -+ -+/* yaffs_checkpt_obj holds the definition of an object as dumped -+ * by checkpointing. -+ */ -+ -+struct yaffs_checkpt_obj { -+ int struct_type; -+ u32 obj_id; -+ u32 parent_id; -+ int hdr_chunk; -+ enum yaffs_obj_type variant_type:3; -+ u8 deleted:1; -+ u8 soft_del:1; -+ u8 unlinked:1; -+ u8 fake:1; -+ u8 rename_allowed:1; -+ u8 unlink_allowed:1; -+ u8 serial; -+ int n_data_chunks; -+ u32 size_or_equiv_obj; -+}; -+ -+/*--------------------- Temporary buffers ---------------- -+ * -+ * These are chunk-sized working buffers. Each device has a few -+ */ -+ -+struct yaffs_buffer { -+ u8 *buffer; -+ int line; /* track from whence this buffer was allocated */ -+ int max_line; -+}; -+ -+/*----------------- Device ---------------------------------*/ -+ -+struct yaffs_param { -+ const YCHAR *name; -+ -+ /* -+ * Entry parameters set up way early. Yaffs sets up the rest. -+ * The structure should be zeroed out before use so that unused -+ * and defualt values are zero. -+ */ -+ -+ int inband_tags; /* Use unband tags */ -+ u32 total_bytes_per_chunk; /* Should be >= 512, does not need to be a power of 2 */ -+ int chunks_per_block; /* does not need to be a power of 2 */ -+ int spare_bytes_per_chunk; /* spare area size */ -+ int start_block; /* Start block we're allowed to use */ -+ int end_block; /* End block we're allowed to use */ -+ int n_reserved_blocks; /* We want this tuneable so that we can reduce */ -+ /* reserved blocks on NOR and RAM. */ -+ -+ int n_caches; /* If <= 0, then short op caching is disabled, else -+ * the number of short op caches (don't use too many). -+ * 10 to 20 is a good bet. -+ */ -+ int use_nand_ecc; /* Flag to decide whether or not to use NANDECC on data (yaffs1) */ -+ int no_tags_ecc; /* Flag to decide whether or not to do ECC on packed tags (yaffs2) */ -+ -+ int is_yaffs2; /* Use yaffs2 mode on this device */ -+ -+ int empty_lost_n_found; /* Auto-empty lost+found directory on mount */ -+ -+ int refresh_period; /* How often we should check to do a block refresh */ -+ -+ /* Checkpoint control. Can be set before or after initialisation */ -+ u8 skip_checkpt_rd; -+ u8 skip_checkpt_wr; -+ -+ int enable_xattr; /* Enable xattribs */ -+ -+ /* NAND access functions (Must be set before calling YAFFS) */ -+ -+ int (*write_chunk_fn) (struct yaffs_dev * dev, -+ int nand_chunk, const u8 * data, -+ const struct yaffs_spare * spare); -+ int (*read_chunk_fn) (struct yaffs_dev * dev, -+ int nand_chunk, u8 * data, -+ struct yaffs_spare * spare); -+ int (*erase_fn) (struct yaffs_dev * dev, int flash_block); -+ int (*initialise_flash_fn) (struct yaffs_dev * dev); -+ int (*deinitialise_flash_fn) (struct yaffs_dev * dev); -+ -+#ifdef CONFIG_YAFFS_YAFFS2 -+ int (*write_chunk_tags_fn) (struct yaffs_dev * dev, -+ int nand_chunk, const u8 * data, -+ const struct yaffs_ext_tags * tags); -+ int (*read_chunk_tags_fn) (struct yaffs_dev * dev, -+ int nand_chunk, u8 * data, -+ struct yaffs_ext_tags * tags); -+ int (*bad_block_fn) (struct yaffs_dev * dev, int block_no); -+ int (*query_block_fn) (struct yaffs_dev * dev, int block_no, -+ enum yaffs_block_state * state, -+ u32 * seq_number); -+#endif -+ -+ /* The remove_obj_fn function must be supplied by OS flavours that -+ * need it. -+ * yaffs direct uses it to implement the faster readdir. -+ * Linux uses it to protect the directory during unlocking. -+ */ -+ void (*remove_obj_fn) (struct yaffs_obj * obj); -+ -+ /* Callback to mark the superblock dirty */ -+ void (*sb_dirty_fn) (struct yaffs_dev * dev); -+ -+ /* Callback to control garbage collection. */ -+ unsigned (*gc_control) (struct yaffs_dev * dev); -+ -+ /* Debug control flags. Don't use unless you know what you're doing */ -+ int use_header_file_size; /* Flag to determine if we should use file sizes from the header */ -+ int disable_lazy_load; /* Disable lazy loading on this device */ -+ int wide_tnodes_disabled; /* Set to disable wide tnodes */ -+ int disable_soft_del; /* yaffs 1 only: Set to disable the use of softdeletion. */ -+ -+ int defered_dir_update; /* Set to defer directory updates */ -+ -+#ifdef CONFIG_YAFFS_AUTO_UNICODE -+ int auto_unicode; -+#endif -+ int always_check_erased; /* Force chunk erased check always on */ -+}; -+ -+struct yaffs_dev { -+ struct yaffs_param param; -+ -+ /* Context storage. Holds extra OS specific data for this device */ -+ -+ void *os_context; -+ void *driver_context; -+ -+ struct list_head dev_list; -+ -+ /* Runtime parameters. Set up by YAFFS. */ -+ int data_bytes_per_chunk; -+ -+ /* Non-wide tnode stuff */ -+ u16 chunk_grp_bits; /* Number of bits that need to be resolved if -+ * the tnodes are not wide enough. -+ */ -+ u16 chunk_grp_size; /* == 2^^chunk_grp_bits */ -+ -+ /* Stuff to support wide tnodes */ -+ u32 tnode_width; -+ u32 tnode_mask; -+ u32 tnode_size; -+ -+ /* Stuff for figuring out file offset to chunk conversions */ -+ u32 chunk_shift; /* Shift value */ -+ u32 chunk_div; /* Divisor after shifting: 1 for power-of-2 sizes */ -+ u32 chunk_mask; /* Mask to use for power-of-2 case */ -+ -+ int is_mounted; -+ int read_only; -+ int is_checkpointed; -+ -+ /* Stuff to support block offsetting to support start block zero */ -+ int internal_start_block; -+ int internal_end_block; -+ int block_offset; -+ int chunk_offset; -+ -+ /* Runtime checkpointing stuff */ -+ int checkpt_page_seq; /* running sequence number of checkpoint pages */ -+ int checkpt_byte_count; -+ int checkpt_byte_offs; -+ u8 *checkpt_buffer; -+ int checkpt_open_write; -+ int blocks_in_checkpt; -+ int checkpt_cur_chunk; -+ int checkpt_cur_block; -+ int checkpt_next_block; -+ int *checkpt_block_list; -+ int checkpt_max_blocks; -+ u32 checkpt_sum; -+ u32 checkpt_xor; -+ -+ int checkpoint_blocks_required; /* Number of blocks needed to store current checkpoint set */ -+ -+ /* Block Info */ -+ struct yaffs_block_info *block_info; -+ u8 *chunk_bits; /* bitmap of chunks in use */ -+ unsigned block_info_alt:1; /* was allocated using alternative strategy */ -+ unsigned chunk_bits_alt:1; /* was allocated using alternative strategy */ -+ int chunk_bit_stride; /* Number of bytes of chunk_bits per block. -+ * Must be consistent with chunks_per_block. -+ */ -+ -+ int n_erased_blocks; -+ int alloc_block; /* Current block being allocated off */ -+ u32 alloc_page; -+ int alloc_block_finder; /* Used to search for next allocation block */ -+ -+ /* Object and Tnode memory management */ -+ void *allocator; -+ int n_obj; -+ int n_tnodes; -+ -+ int n_hardlinks; -+ -+ struct yaffs_obj_bucket obj_bucket[YAFFS_NOBJECT_BUCKETS]; -+ u32 bucket_finder; -+ -+ int n_free_chunks; -+ -+ /* Garbage collection control */ -+ u32 *gc_cleanup_list; /* objects to delete at the end of a GC. */ -+ u32 n_clean_ups; -+ -+ unsigned has_pending_prioritised_gc; /* We think this device might have pending prioritised gcs */ -+ unsigned gc_disable; -+ unsigned gc_block_finder; -+ unsigned gc_dirtiest; -+ unsigned gc_pages_in_use; -+ unsigned gc_not_done; -+ unsigned gc_block; -+ unsigned gc_chunk; -+ unsigned gc_skip; -+ -+ /* Special directories */ -+ struct yaffs_obj *root_dir; -+ struct yaffs_obj *lost_n_found; -+ -+ /* Buffer areas for storing data to recover from write failures TODO -+ * u8 buffered_data[YAFFS_CHUNKS_PER_BLOCK][YAFFS_BYTES_PER_CHUNK]; -+ * struct yaffs_spare buffered_spare[YAFFS_CHUNKS_PER_BLOCK]; -+ */ -+ -+ int buffered_block; /* Which block is buffered here? */ -+ int doing_buffered_block_rewrite; -+ -+ struct yaffs_cache *cache; -+ int cache_last_use; -+ -+ /* Stuff for background deletion and unlinked files. */ -+ struct yaffs_obj *unlinked_dir; /* Directory where unlinked and deleted files live. */ -+ struct yaffs_obj *del_dir; /* Directory where deleted objects are sent to disappear. */ -+ struct yaffs_obj *unlinked_deletion; /* Current file being background deleted. */ -+ int n_deleted_files; /* Count of files awaiting deletion; */ -+ int n_unlinked_files; /* Count of unlinked files. */ -+ int n_bg_deletions; /* Count of background deletions. */ -+ -+ /* Temporary buffer management */ -+ struct yaffs_buffer temp_buffer[YAFFS_N_TEMP_BUFFERS]; -+ int max_temp; -+ int temp_in_use; -+ int unmanaged_buffer_allocs; -+ int unmanaged_buffer_deallocs; -+ -+ /* yaffs2 runtime stuff */ -+ unsigned seq_number; /* Sequence number of currently allocating block */ -+ unsigned oldest_dirty_seq; -+ unsigned oldest_dirty_block; -+ -+ /* Block refreshing */ -+ int refresh_skip; /* A skip down counter. Refresh happens when this gets to zero. */ -+ -+ /* Dirty directory handling */ -+ struct list_head dirty_dirs; /* List of dirty directories */ -+ -+ /* Statistcs */ -+ u32 n_page_writes; -+ u32 n_page_reads; -+ u32 n_erasures; -+ u32 n_erase_failures; -+ u32 n_gc_copies; -+ u32 all_gcs; -+ u32 passive_gc_count; -+ u32 oldest_dirty_gc_count; -+ u32 n_gc_blocks; -+ u32 bg_gcs; -+ u32 n_retired_writes; -+ u32 n_retired_blocks; -+ u32 n_ecc_fixed; -+ u32 n_ecc_unfixed; -+ u32 n_tags_ecc_fixed; -+ u32 n_tags_ecc_unfixed; -+ u32 n_deletions; -+ u32 n_unmarked_deletions; -+ u32 refresh_count; -+ u32 cache_hits; -+ -+}; -+ -+/* The CheckpointDevice structure holds the device information that changes at runtime and -+ * must be preserved over unmount/mount cycles. -+ */ -+struct yaffs_checkpt_dev { -+ int struct_type; -+ int n_erased_blocks; -+ int alloc_block; /* Current block being allocated off */ -+ u32 alloc_page; -+ int n_free_chunks; -+ -+ int n_deleted_files; /* Count of files awaiting deletion; */ -+ int n_unlinked_files; /* Count of unlinked files. */ -+ int n_bg_deletions; /* Count of background deletions. */ -+ -+ /* yaffs2 runtime stuff */ -+ unsigned seq_number; /* Sequence number of currently allocating block */ -+ -+}; -+ -+struct yaffs_checkpt_validity { -+ int struct_type; -+ u32 magic; -+ u32 version; -+ u32 head; -+}; -+ -+struct yaffs_shadow_fixer { -+ int obj_id; -+ int shadowed_id; -+ struct yaffs_shadow_fixer *next; -+}; -+ -+/* Structure for doing xattr modifications */ -+struct yaffs_xattr_mod { -+ int set; /* If 0 then this is a deletion */ -+ const YCHAR *name; -+ const void *data; -+ int size; -+ int flags; -+ int result; -+}; -+ -+/*----------------------- YAFFS Functions -----------------------*/ -+ -+int yaffs_guts_initialise(struct yaffs_dev *dev); -+void yaffs_deinitialise(struct yaffs_dev *dev); -+ -+int yaffs_get_n_free_chunks(struct yaffs_dev *dev); -+ -+int yaffs_rename_obj(struct yaffs_obj *old_dir, const YCHAR * old_name, -+ struct yaffs_obj *new_dir, const YCHAR * new_name); -+ -+int yaffs_unlinker(struct yaffs_obj *dir, const YCHAR * name); -+int yaffs_del_obj(struct yaffs_obj *obj); -+ -+int yaffs_get_obj_name(struct yaffs_obj *obj, YCHAR * name, int buffer_size); -+int yaffs_get_obj_length(struct yaffs_obj *obj); -+int yaffs_get_obj_inode(struct yaffs_obj *obj); -+unsigned yaffs_get_obj_type(struct yaffs_obj *obj); -+int yaffs_get_obj_link_count(struct yaffs_obj *obj); -+ -+/* File operations */ -+int yaffs_file_rd(struct yaffs_obj *obj, u8 * buffer, loff_t offset, -+ int n_bytes); -+int yaffs_wr_file(struct yaffs_obj *obj, const u8 * buffer, loff_t offset, -+ int n_bytes, int write_trhrough); -+int yaffs_resize_file(struct yaffs_obj *obj, loff_t new_size); -+ -+struct yaffs_obj *yaffs_create_file(struct yaffs_obj *parent, -+ const YCHAR * name, u32 mode, u32 uid, -+ u32 gid); -+ -+int yaffs_flush_file(struct yaffs_obj *obj, int update_time, int data_sync); -+ -+/* Flushing and checkpointing */ -+void yaffs_flush_whole_cache(struct yaffs_dev *dev); -+ -+int yaffs_checkpoint_save(struct yaffs_dev *dev); -+int yaffs_checkpoint_restore(struct yaffs_dev *dev); -+ -+/* Directory operations */ -+struct yaffs_obj *yaffs_create_dir(struct yaffs_obj *parent, const YCHAR * name, -+ u32 mode, u32 uid, u32 gid); -+struct yaffs_obj *yaffs_find_by_name(struct yaffs_obj *the_dir, -+ const YCHAR * name); -+struct yaffs_obj *yaffs_find_by_number(struct yaffs_dev *dev, u32 number); -+ -+/* Link operations */ -+struct yaffs_obj *yaffs_link_obj(struct yaffs_obj *parent, const YCHAR * name, -+ struct yaffs_obj *equiv_obj); -+ -+struct yaffs_obj *yaffs_get_equivalent_obj(struct yaffs_obj *obj); -+ -+/* Symlink operations */ -+struct yaffs_obj *yaffs_create_symlink(struct yaffs_obj *parent, -+ const YCHAR * name, u32 mode, u32 uid, -+ u32 gid, const YCHAR * alias); -+YCHAR *yaffs_get_symlink_alias(struct yaffs_obj *obj); -+ -+/* Special inodes (fifos, sockets and devices) */ -+struct yaffs_obj *yaffs_create_special(struct yaffs_obj *parent, -+ const YCHAR * name, u32 mode, u32 uid, -+ u32 gid, u32 rdev); -+ -+int yaffs_set_xattrib(struct yaffs_obj *obj, const YCHAR * name, -+ const void *value, int size, int flags); -+int yaffs_get_xattrib(struct yaffs_obj *obj, const YCHAR * name, void *value, -+ int size); -+int yaffs_list_xattrib(struct yaffs_obj *obj, char *buffer, int size); -+int yaffs_remove_xattrib(struct yaffs_obj *obj, const YCHAR * name); -+ -+/* Special directories */ -+struct yaffs_obj *yaffs_root(struct yaffs_dev *dev); -+struct yaffs_obj *yaffs_lost_n_found(struct yaffs_dev *dev); -+ -+void yaffs_handle_defered_free(struct yaffs_obj *obj); -+ -+void yaffs_update_dirty_dirs(struct yaffs_dev *dev); -+ -+int yaffs_bg_gc(struct yaffs_dev *dev, unsigned urgency); -+ -+/* Debug dump */ -+int yaffs_dump_obj(struct yaffs_obj *obj); -+ -+void yaffs_guts_test(struct yaffs_dev *dev); -+ -+/* A few useful functions to be used within the core files*/ -+void yaffs_chunk_del(struct yaffs_dev *dev, int chunk_id, int mark_flash, -+ int lyn); -+int yaffs_check_ff(u8 * buffer, int n_bytes); -+void yaffs_handle_chunk_error(struct yaffs_dev *dev, -+ struct yaffs_block_info *bi); -+ -+u8 *yaffs_get_temp_buffer(struct yaffs_dev *dev, int line_no); -+void yaffs_release_temp_buffer(struct yaffs_dev *dev, u8 * buffer, int line_no); -+ -+struct yaffs_obj *yaffs_find_or_create_by_number(struct yaffs_dev *dev, -+ int number, -+ enum yaffs_obj_type type); -+int yaffs_put_chunk_in_file(struct yaffs_obj *in, int inode_chunk, -+ int nand_chunk, int in_scan); -+void yaffs_set_obj_name(struct yaffs_obj *obj, const YCHAR * name); -+void yaffs_set_obj_name_from_oh(struct yaffs_obj *obj, -+ const struct yaffs_obj_hdr *oh); -+void yaffs_add_obj_to_dir(struct yaffs_obj *directory, struct yaffs_obj *obj); -+YCHAR *yaffs_clone_str(const YCHAR * str); -+void yaffs_link_fixup(struct yaffs_dev *dev, struct yaffs_obj *hard_list); -+void yaffs_block_became_dirty(struct yaffs_dev *dev, int block_no); -+int yaffs_update_oh(struct yaffs_obj *in, const YCHAR * name, -+ int force, int is_shrink, int shadows, -+ struct yaffs_xattr_mod *xop); -+void yaffs_handle_shadowed_obj(struct yaffs_dev *dev, int obj_id, -+ int backward_scanning); -+int yaffs_check_alloc_available(struct yaffs_dev *dev, int n_chunks); -+struct yaffs_tnode *yaffs_get_tnode(struct yaffs_dev *dev); -+struct yaffs_tnode *yaffs_add_find_tnode_0(struct yaffs_dev *dev, -+ struct yaffs_file_var *file_struct, -+ u32 chunk_id, -+ struct yaffs_tnode *passed_tn); -+ -+int yaffs_do_file_wr(struct yaffs_obj *in, const u8 * buffer, loff_t offset, -+ int n_bytes, int write_trhrough); -+void yaffs_resize_file_down(struct yaffs_obj *obj, loff_t new_size); -+void yaffs_skip_rest_of_block(struct yaffs_dev *dev); -+ -+int yaffs_count_free_chunks(struct yaffs_dev *dev); -+ -+struct yaffs_tnode *yaffs_find_tnode_0(struct yaffs_dev *dev, -+ struct yaffs_file_var *file_struct, -+ u32 chunk_id); -+ -+u32 yaffs_get_group_base(struct yaffs_dev *dev, struct yaffs_tnode *tn, -+ unsigned pos); -+ -+#endif -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_linux.h linux-2.6.36/fs/yaffs2/yaffs_linux.h ---- linux-2.6.36.orig/fs/yaffs2/yaffs_linux.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_linux.h 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,41 @@ -+/* -+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU Lesser General Public License version 2.1 as -+ * published by the Free Software Foundation. -+ * -+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. -+ */ -+ -+#ifndef __YAFFS_LINUX_H__ -+#define __YAFFS_LINUX_H__ -+ -+#include "yportenv.h" -+ -+struct yaffs_linux_context { -+ struct list_head context_list; /* List of these we have mounted */ -+ struct yaffs_dev *dev; -+ struct super_block *super; -+ struct task_struct *bg_thread; /* Background thread for this device */ -+ int bg_running; -+ struct mutex gross_lock; /* Gross locking mutex*/ -+ u8 *spare_buffer; /* For mtdif2 use. Don't know the size of the buffer -+ * at compile time so we have to allocate it. -+ */ -+ struct list_head search_contexts; -+ void (*put_super_fn) (struct super_block * sb); -+ -+ struct task_struct *readdir_process; -+ unsigned mount_id; -+}; -+ -+#define yaffs_dev_to_lc(dev) ((struct yaffs_linux_context *)((dev)->os_context)) -+#define yaffs_dev_to_mtd(dev) ((struct mtd_info *)((dev)->driver_context)) -+ -+#endif -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_mtdif.c linux-2.6.36/fs/yaffs2/yaffs_mtdif.c ---- linux-2.6.36.orig/fs/yaffs2/yaffs_mtdif.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_mtdif.c 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,54 @@ -+/* -+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include "yportenv.h" -+ -+#include "yaffs_mtdif.h" -+ -+#include "linux/mtd/mtd.h" -+#include "linux/types.h" -+#include "linux/time.h" -+#include "linux/mtd/nand.h" -+ -+#include "yaffs_linux.h" -+ -+int nandmtd_erase_block(struct yaffs_dev *dev, int block_no) -+{ -+ struct mtd_info *mtd = yaffs_dev_to_mtd(dev); -+ u32 addr = -+ ((loff_t) block_no) * dev->param.total_bytes_per_chunk -+ * dev->param.chunks_per_block; -+ struct erase_info ei; -+ -+ int retval = 0; -+ -+ ei.mtd = mtd; -+ ei.addr = addr; -+ ei.len = dev->param.total_bytes_per_chunk * dev->param.chunks_per_block; -+ ei.time = 1000; -+ ei.retries = 2; -+ ei.callback = NULL; -+ ei.priv = (u_long) dev; -+ -+ retval = mtd->erase(mtd, &ei); -+ -+ if (retval == 0) -+ return YAFFS_OK; -+ else -+ return YAFFS_FAIL; -+} -+ -+int nandmtd_initialise(struct yaffs_dev *dev) -+{ -+ return YAFFS_OK; -+} -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_mtdif.h linux-2.6.36/fs/yaffs2/yaffs_mtdif.h ---- linux-2.6.36.orig/fs/yaffs2/yaffs_mtdif.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_mtdif.h 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,23 @@ -+/* -+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU Lesser General Public License version 2.1 as -+ * published by the Free Software Foundation. -+ * -+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. -+ */ -+ -+#ifndef __YAFFS_MTDIF_H__ -+#define __YAFFS_MTDIF_H__ -+ -+#include "yaffs_guts.h" -+ -+int nandmtd_erase_block(struct yaffs_dev *dev, int block_no); -+int nandmtd_initialise(struct yaffs_dev *dev); -+#endif -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_mtdif1.c linux-2.6.36/fs/yaffs2/yaffs_mtdif1.c ---- linux-2.6.36.orig/fs/yaffs2/yaffs_mtdif1.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_mtdif1.c 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,365 @@ -+/* -+ * YAFFS: Yet another FFS. A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+/* -+ * This module provides the interface between yaffs_nand.c and the -+ * MTD API. This version is used when the MTD interface supports the -+ * 'mtd_oob_ops' style calls to read_oob and write_oob, circa 2.6.17, -+ * and we have small-page NAND device. -+ * -+ * These functions are invoked via function pointers in yaffs_nand.c. -+ * This replaces functionality provided by functions in yaffs_mtdif.c -+ * and the yaffs_tags compatability functions in yaffs_tagscompat.c that are -+ * called in yaffs_mtdif.c when the function pointers are NULL. -+ * We assume the MTD layer is performing ECC (use_nand_ecc is true). -+ */ -+ -+#include "yportenv.h" -+#include "yaffs_trace.h" -+#include "yaffs_guts.h" -+#include "yaffs_packedtags1.h" -+#include "yaffs_tagscompat.h" /* for yaffs_calc_tags_ecc */ -+#include "yaffs_linux.h" -+ -+#include "linux/kernel.h" -+#include "linux/version.h" -+#include "linux/types.h" -+#include "linux/mtd/mtd.h" -+ -+/* Don't compile this module if we don't have MTD's mtd_oob_ops interface */ -+#if (MTD_VERSION_CODE > MTD_VERSION(2, 6, 17)) -+ -+#ifndef CONFIG_YAFFS_9BYTE_TAGS -+# define YTAG1_SIZE 8 -+#else -+# define YTAG1_SIZE 9 -+#endif -+ -+#if 0 -+/* Use the following nand_ecclayout with MTD when using -+ * CONFIG_YAFFS_9BYTE_TAGS and the older on-NAND tags layout. -+ * If you have existing Yaffs images and the byte order differs from this, -+ * adjust 'oobfree' to match your existing Yaffs data. -+ * -+ * This nand_ecclayout scatters/gathers to/from the old-yaffs layout with the -+ * page_status byte (at NAND spare offset 4) scattered/gathered from/to -+ * the 9th byte. -+ * -+ * Old-style on-NAND format: T0,T1,T2,T3,P,B,T4,T5,E0,E1,E2,T6,T7,E3,E4,E5 -+ * We have/need packed_tags1 plus page_status: T0,T1,T2,T3,T4,T5,T6,T7,P -+ * where Tn are the tag bytes, En are MTD's ECC bytes, P is the page_status -+ * byte and B is the small-page bad-block indicator byte. -+ */ -+static struct nand_ecclayout nand_oob_16 = { -+ .eccbytes = 6, -+ .eccpos = {8, 9, 10, 13, 14, 15}, -+ .oobavail = 9, -+ .oobfree = {{0, 4}, {6, 2}, {11, 2}, {4, 1}} -+}; -+#endif -+ -+/* Write a chunk (page) of data to NAND. -+ * -+ * Caller always provides ExtendedTags data which are converted to a more -+ * compact (packed) form for storage in NAND. A mini-ECC runs over the -+ * contents of the tags meta-data; used to valid the tags when read. -+ * -+ * - Pack ExtendedTags to packed_tags1 form -+ * - Compute mini-ECC for packed_tags1 -+ * - Write data and packed tags to NAND. -+ * -+ * Note: Due to the use of the packed_tags1 meta-data which does not include -+ * a full sequence number (as found in the larger packed_tags2 form) it is -+ * necessary for Yaffs to re-write a chunk/page (just once) to mark it as -+ * discarded and dirty. This is not ideal: newer NAND parts are supposed -+ * to be written just once. When Yaffs performs this operation, this -+ * function is called with a NULL data pointer -- calling MTD write_oob -+ * without data is valid usage (2.6.17). -+ * -+ * Any underlying MTD error results in YAFFS_FAIL. -+ * Returns YAFFS_OK or YAFFS_FAIL. -+ */ -+int nandmtd1_write_chunk_tags(struct yaffs_dev *dev, -+ int nand_chunk, const u8 * data, -+ const struct yaffs_ext_tags *etags) -+{ -+ struct mtd_info *mtd = yaffs_dev_to_mtd(dev); -+ int chunk_bytes = dev->data_bytes_per_chunk; -+ loff_t addr = ((loff_t) nand_chunk) * chunk_bytes; -+ struct mtd_oob_ops ops; -+ struct yaffs_packed_tags1 pt1; -+ int retval; -+ -+ /* we assume that packed_tags1 and struct yaffs_tags are compatible */ -+ compile_time_assertion(sizeof(struct yaffs_packed_tags1) == 12); -+ compile_time_assertion(sizeof(struct yaffs_tags) == 8); -+ -+ yaffs_pack_tags1(&pt1, etags); -+ yaffs_calc_tags_ecc((struct yaffs_tags *)&pt1); -+ -+ /* When deleting a chunk, the upper layer provides only skeletal -+ * etags, one with is_deleted set. However, we need to update the -+ * tags, not erase them completely. So we use the NAND write property -+ * that only zeroed-bits stick and set tag bytes to all-ones and -+ * zero just the (not) deleted bit. -+ */ -+#ifndef CONFIG_YAFFS_9BYTE_TAGS -+ if (etags->is_deleted) { -+ memset(&pt1, 0xff, 8); -+ /* clear delete status bit to indicate deleted */ -+ pt1.deleted = 0; -+ } -+#else -+ ((u8 *) & pt1)[8] = 0xff; -+ if (etags->is_deleted) { -+ memset(&pt1, 0xff, 8); -+ /* zero page_status byte to indicate deleted */ -+ ((u8 *) & pt1)[8] = 0; -+ } -+#endif -+ -+ memset(&ops, 0, sizeof(ops)); -+ ops.mode = MTD_OOB_AUTO; -+ ops.len = (data) ? chunk_bytes : 0; -+ ops.ooblen = YTAG1_SIZE; -+ ops.datbuf = (u8 *) data; -+ ops.oobbuf = (u8 *) & pt1; -+ -+ retval = mtd->write_oob(mtd, addr, &ops); -+ if (retval) { -+ T(YAFFS_TRACE_MTD, -+ (TSTR("write_oob failed, chunk %d, mtd error %d" TENDSTR), -+ nand_chunk, retval)); -+ } -+ return retval ? YAFFS_FAIL : YAFFS_OK; -+} -+ -+/* Return with empty ExtendedTags but add ecc_result. -+ */ -+static int rettags(struct yaffs_ext_tags *etags, int ecc_result, int retval) -+{ -+ if (etags) { -+ memset(etags, 0, sizeof(*etags)); -+ etags->ecc_result = ecc_result; -+ } -+ return retval; -+} -+ -+/* Read a chunk (page) from NAND. -+ * -+ * Caller expects ExtendedTags data to be usable even on error; that is, -+ * all members except ecc_result and block_bad are zeroed. -+ * -+ * - Check ECC results for data (if applicable) -+ * - Check for blank/erased block (return empty ExtendedTags if blank) -+ * - Check the packed_tags1 mini-ECC (correct if necessary/possible) -+ * - Convert packed_tags1 to ExtendedTags -+ * - Update ecc_result and block_bad members to refect state. -+ * -+ * Returns YAFFS_OK or YAFFS_FAIL. -+ */ -+int nandmtd1_read_chunk_tags(struct yaffs_dev *dev, -+ int nand_chunk, u8 * data, -+ struct yaffs_ext_tags *etags) -+{ -+ struct mtd_info *mtd = yaffs_dev_to_mtd(dev); -+ int chunk_bytes = dev->data_bytes_per_chunk; -+ loff_t addr = ((loff_t) nand_chunk) * chunk_bytes; -+ int eccres = YAFFS_ECC_RESULT_NO_ERROR; -+ struct mtd_oob_ops ops; -+ struct yaffs_packed_tags1 pt1; -+ int retval; -+ int deleted; -+ -+ memset(&ops, 0, sizeof(ops)); -+ ops.mode = MTD_OOB_AUTO; -+ ops.len = (data) ? chunk_bytes : 0; -+ ops.ooblen = YTAG1_SIZE; -+ ops.datbuf = data; -+ ops.oobbuf = (u8 *) & pt1; -+ -+#if (MTD_VERSION_CODE < MTD_VERSION(2, 6, 20)) -+ /* In MTD 2.6.18 to 2.6.19 nand_base.c:nand_do_read_oob() has a bug; -+ * help it out with ops.len = ops.ooblen when ops.datbuf == NULL. -+ */ -+ ops.len = (ops.datbuf) ? ops.len : ops.ooblen; -+#endif -+ /* Read page and oob using MTD. -+ * Check status and determine ECC result. -+ */ -+ retval = mtd->read_oob(mtd, addr, &ops); -+ if (retval) { -+ T(YAFFS_TRACE_MTD, -+ (TSTR("read_oob failed, chunk %d, mtd error %d" TENDSTR), -+ nand_chunk, retval)); -+ } -+ -+ switch (retval) { -+ case 0: -+ /* no error */ -+ break; -+ -+ case -EUCLEAN: -+ /* MTD's ECC fixed the data */ -+ eccres = YAFFS_ECC_RESULT_FIXED; -+ dev->n_ecc_fixed++; -+ break; -+ -+ case -EBADMSG: -+ /* MTD's ECC could not fix the data */ -+ dev->n_ecc_unfixed++; -+ /* fall into... */ -+ default: -+ rettags(etags, YAFFS_ECC_RESULT_UNFIXED, 0); -+ etags->block_bad = (mtd->block_isbad) (mtd, addr); -+ return YAFFS_FAIL; -+ } -+ -+ /* Check for a blank/erased chunk. -+ */ -+ if (yaffs_check_ff((u8 *) & pt1, 8)) { -+ /* when blank, upper layers want ecc_result to be <= NO_ERROR */ -+ return rettags(etags, YAFFS_ECC_RESULT_NO_ERROR, YAFFS_OK); -+ } -+#ifndef CONFIG_YAFFS_9BYTE_TAGS -+ /* Read deleted status (bit) then return it to it's non-deleted -+ * state before performing tags mini-ECC check. pt1.deleted is -+ * inverted. -+ */ -+ deleted = !pt1.deleted; -+ pt1.deleted = 1; -+#else -+ deleted = (yaffs_count_bits(((u8 *) & pt1)[8]) < 7); -+#endif -+ -+ /* Check the packed tags mini-ECC and correct if necessary/possible. -+ */ -+ retval = yaffs_check_tags_ecc((struct yaffs_tags *)&pt1); -+ switch (retval) { -+ case 0: -+ /* no tags error, use MTD result */ -+ break; -+ case 1: -+ /* recovered tags-ECC error */ -+ dev->n_tags_ecc_fixed++; -+ if (eccres == YAFFS_ECC_RESULT_NO_ERROR) -+ eccres = YAFFS_ECC_RESULT_FIXED; -+ break; -+ default: -+ /* unrecovered tags-ECC error */ -+ dev->n_tags_ecc_unfixed++; -+ return rettags(etags, YAFFS_ECC_RESULT_UNFIXED, YAFFS_FAIL); -+ } -+ -+ /* Unpack the tags to extended form and set ECC result. -+ * [set should_be_ff just to keep yaffs_unpack_tags1 happy] -+ */ -+ pt1.should_be_ff = 0xFFFFFFFF; -+ yaffs_unpack_tags1(etags, &pt1); -+ etags->ecc_result = eccres; -+ -+ /* Set deleted state */ -+ etags->is_deleted = deleted; -+ return YAFFS_OK; -+} -+ -+/* Mark a block bad. -+ * -+ * This is a persistant state. -+ * Use of this function should be rare. -+ * -+ * Returns YAFFS_OK or YAFFS_FAIL. -+ */ -+int nandmtd1_mark_block_bad(struct yaffs_dev *dev, int block_no) -+{ -+ struct mtd_info *mtd = yaffs_dev_to_mtd(dev); -+ int blocksize = dev->param.chunks_per_block * dev->data_bytes_per_chunk; -+ int retval; -+ -+ T(YAFFS_TRACE_BAD_BLOCKS, -+ (TSTR("marking block %d bad" TENDSTR), block_no)); -+ -+ retval = mtd->block_markbad(mtd, (loff_t) blocksize * block_no); -+ return (retval) ? YAFFS_FAIL : YAFFS_OK; -+} -+ -+/* Check any MTD prerequists. -+ * -+ * Returns YAFFS_OK or YAFFS_FAIL. -+ */ -+static int nandmtd1_test_prerequists(struct mtd_info *mtd) -+{ -+ /* 2.6.18 has mtd->ecclayout->oobavail */ -+ /* 2.6.21 has mtd->ecclayout->oobavail and mtd->oobavail */ -+ int oobavail = mtd->ecclayout->oobavail; -+ -+ if (oobavail < YTAG1_SIZE) { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR -+ ("mtd device has only %d bytes for tags, need %d" TENDSTR), -+ oobavail, YTAG1_SIZE)); -+ return YAFFS_FAIL; -+ } -+ return YAFFS_OK; -+} -+ -+/* Query for the current state of a specific block. -+ * -+ * Examine the tags of the first chunk of the block and return the state: -+ * - YAFFS_BLOCK_STATE_DEAD, the block is marked bad -+ * - YAFFS_BLOCK_STATE_NEEDS_SCANNING, the block is in use -+ * - YAFFS_BLOCK_STATE_EMPTY, the block is clean -+ * -+ * Always returns YAFFS_OK. -+ */ -+int nandmtd1_query_block(struct yaffs_dev *dev, int block_no, -+ enum yaffs_block_state *state_ptr, u32 * seq_ptr) -+{ -+ struct mtd_info *mtd = yaffs_dev_to_mtd(dev); -+ int chunk_num = block_no * dev->param.chunks_per_block; -+ loff_t addr = (loff_t) chunk_num * dev->data_bytes_per_chunk; -+ struct yaffs_ext_tags etags; -+ int state = YAFFS_BLOCK_STATE_DEAD; -+ int seqnum = 0; -+ int retval; -+ -+ /* We don't yet have a good place to test for MTD config prerequists. -+ * Do it here as we are called during the initial scan. -+ */ -+ if (nandmtd1_test_prerequists(mtd) != YAFFS_OK) -+ return YAFFS_FAIL; -+ -+ retval = nandmtd1_read_chunk_tags(dev, chunk_num, NULL, &etags); -+ etags.block_bad = (mtd->block_isbad) (mtd, addr); -+ if (etags.block_bad) { -+ T(YAFFS_TRACE_BAD_BLOCKS, -+ (TSTR("block %d is marked bad" TENDSTR), block_no)); -+ state = YAFFS_BLOCK_STATE_DEAD; -+ } else if (etags.ecc_result != YAFFS_ECC_RESULT_NO_ERROR) { -+ /* bad tags, need to look more closely */ -+ state = YAFFS_BLOCK_STATE_NEEDS_SCANNING; -+ } else if (etags.chunk_used) { -+ state = YAFFS_BLOCK_STATE_NEEDS_SCANNING; -+ seqnum = etags.seq_number; -+ } else { -+ state = YAFFS_BLOCK_STATE_EMPTY; -+ } -+ -+ *state_ptr = state; -+ *seq_ptr = seqnum; -+ -+ /* query always succeeds */ -+ return YAFFS_OK; -+} -+ -+#endif /*MTD_VERSION */ -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_mtdif1.h linux-2.6.36/fs/yaffs2/yaffs_mtdif1.h ---- linux-2.6.36.orig/fs/yaffs2/yaffs_mtdif1.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_mtdif1.h 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,29 @@ -+/* -+ * YAFFS: Yet another Flash File System. A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU Lesser General Public License version 2.1 as -+ * published by the Free Software Foundation. -+ * -+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. -+ */ -+ -+#ifndef __YAFFS_MTDIF1_H__ -+#define __YAFFS_MTDIF1_H__ -+ -+int nandmtd1_write_chunk_tags(struct yaffs_dev *dev, int nand_chunk, -+ const u8 * data, -+ const struct yaffs_ext_tags *tags); -+ -+int nandmtd1_read_chunk_tags(struct yaffs_dev *dev, int nand_chunk, -+ u8 * data, struct yaffs_ext_tags *tags); -+ -+int nandmtd1_mark_block_bad(struct yaffs_dev *dev, int block_no); -+ -+int nandmtd1_query_block(struct yaffs_dev *dev, int block_no, -+ enum yaffs_block_state *state, u32 * seq_number); -+ -+#endif -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_mtdif2.c linux-2.6.36/fs/yaffs2/yaffs_mtdif2.c ---- linux-2.6.36.orig/fs/yaffs2/yaffs_mtdif2.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_mtdif2.c 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,261 @@ -+/* -+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+/* mtd interface for YAFFS2 */ -+ -+#include "yportenv.h" -+#include "yaffs_trace.h" -+ -+#include "yaffs_mtdif2.h" -+ -+#include "linux/mtd/mtd.h" -+#include "linux/types.h" -+#include "linux/time.h" -+ -+#include "yaffs_packedtags2.h" -+ -+#include "yaffs_linux.h" -+ -+/* NB For use with inband tags.... -+ * We assume that the data buffer is of size total_bytes_per_chunk so that we can also -+ * use it to load the tags. -+ */ -+int nandmtd2_write_chunk_tags(struct yaffs_dev *dev, int nand_chunk, -+ const u8 * data, -+ const struct yaffs_ext_tags *tags) -+{ -+ struct mtd_info *mtd = yaffs_dev_to_mtd(dev); -+#if (MTD_VERSION_CODE > MTD_VERSION(2, 6, 17)) -+ struct mtd_oob_ops ops; -+#else -+ size_t dummy; -+#endif -+ int retval = 0; -+ -+ loff_t addr; -+ -+ struct yaffs_packed_tags2 pt; -+ -+ int packed_tags_size = -+ dev->param.no_tags_ecc ? sizeof(pt.t) : sizeof(pt); -+ void *packed_tags_ptr = -+ dev->param.no_tags_ecc ? (void *)&pt.t : (void *)&pt; -+ -+ T(YAFFS_TRACE_MTD, -+ (TSTR -+ ("nandmtd2_write_chunk_tags chunk %d data %p tags %p" -+ TENDSTR), nand_chunk, data, tags)); -+ -+ addr = ((loff_t) nand_chunk) * dev->param.total_bytes_per_chunk; -+ -+ /* For yaffs2 writing there must be both data and tags. -+ * If we're using inband tags, then the tags are stuffed into -+ * the end of the data buffer. -+ */ -+ if (!data || !tags) -+ BUG(); -+ else if (dev->param.inband_tags) { -+ struct yaffs_packed_tags2_tags_only *pt2tp; -+ pt2tp = -+ (struct yaffs_packed_tags2_tags_only *)(data + -+ dev-> -+ data_bytes_per_chunk); -+ yaffs_pack_tags2_tags_only(pt2tp, tags); -+ } else { -+ yaffs_pack_tags2(&pt, tags, !dev->param.no_tags_ecc); -+ } -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17)) -+ ops.mode = MTD_OOB_AUTO; -+ ops.ooblen = (dev->param.inband_tags) ? 0 : packed_tags_size; -+ ops.len = dev->param.total_bytes_per_chunk; -+ ops.ooboffs = 0; -+ ops.datbuf = (u8 *) data; -+ ops.oobbuf = (dev->param.inband_tags) ? NULL : packed_tags_ptr; -+ retval = mtd->write_oob(mtd, addr, &ops); -+ -+#else -+ if (!dev->param.inband_tags) { -+ retval = -+ mtd->write_ecc(mtd, addr, dev->data_bytes_per_chunk, -+ &dummy, data, (u8 *) packed_tags_ptr, NULL); -+ } else { -+ retval = -+ mtd->write(mtd, addr, dev->param.total_bytes_per_chunk, -+ &dummy, data); -+ } -+#endif -+ -+ if (retval == 0) -+ return YAFFS_OK; -+ else -+ return YAFFS_FAIL; -+} -+ -+int nandmtd2_read_chunk_tags(struct yaffs_dev *dev, int nand_chunk, -+ u8 * data, struct yaffs_ext_tags *tags) -+{ -+ struct mtd_info *mtd = yaffs_dev_to_mtd(dev); -+#if (MTD_VERSION_CODE > MTD_VERSION(2, 6, 17)) -+ struct mtd_oob_ops ops; -+#endif -+ size_t dummy; -+ int retval = 0; -+ int local_data = 0; -+ -+ loff_t addr = ((loff_t) nand_chunk) * dev->param.total_bytes_per_chunk; -+ -+ struct yaffs_packed_tags2 pt; -+ -+ int packed_tags_size = -+ dev->param.no_tags_ecc ? sizeof(pt.t) : sizeof(pt); -+ void *packed_tags_ptr = -+ dev->param.no_tags_ecc ? (void *)&pt.t : (void *)&pt; -+ -+ T(YAFFS_TRACE_MTD, -+ (TSTR -+ ("nandmtd2_read_chunk_tags chunk %d data %p tags %p" -+ TENDSTR), nand_chunk, data, tags)); -+ -+ if (dev->param.inband_tags) { -+ -+ if (!data) { -+ local_data = 1; -+ data = yaffs_get_temp_buffer(dev, __LINE__); -+ } -+ -+ } -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17)) -+ if (dev->param.inband_tags || (data && !tags)) -+ retval = mtd->read(mtd, addr, dev->param.total_bytes_per_chunk, -+ &dummy, data); -+ else if (tags) { -+ ops.mode = MTD_OOB_AUTO; -+ ops.ooblen = packed_tags_size; -+ ops.len = data ? dev->data_bytes_per_chunk : packed_tags_size; -+ ops.ooboffs = 0; -+ ops.datbuf = data; -+ ops.oobbuf = yaffs_dev_to_lc(dev)->spare_buffer; -+ retval = mtd->read_oob(mtd, addr, &ops); -+ } -+#else -+ if (!dev->param.inband_tags && data && tags) { -+ -+ retval = mtd->read_ecc(mtd, addr, dev->data_bytes_per_chunk, -+ &dummy, data, dev->spare_buffer, NULL); -+ } else { -+ if (data) -+ retval = -+ mtd->read(mtd, addr, dev->data_bytes_per_chunk, -+ &dummy, data); -+ if (!dev->param.inband_tags && tags) -+ retval = -+ mtd->read_oob(mtd, addr, mtd->oobsize, &dummy, -+ dev->spare_buffer); -+ } -+#endif -+ -+ if (dev->param.inband_tags) { -+ if (tags) { -+ struct yaffs_packed_tags2_tags_only *pt2tp; -+ pt2tp = -+ (struct yaffs_packed_tags2_tags_only *)&data[dev-> -+ data_bytes_per_chunk]; -+ yaffs_unpack_tags2_tags_only(tags, pt2tp); -+ } -+ } else { -+ if (tags) { -+ memcpy(packed_tags_ptr, -+ yaffs_dev_to_lc(dev)->spare_buffer, -+ packed_tags_size); -+ yaffs_unpack_tags2(tags, &pt, !dev->param.no_tags_ecc); -+ } -+ } -+ -+ if (local_data) -+ yaffs_release_temp_buffer(dev, data, __LINE__); -+ -+ if (tags && retval == -EBADMSG -+ && tags->ecc_result == YAFFS_ECC_RESULT_NO_ERROR) { -+ tags->ecc_result = YAFFS_ECC_RESULT_UNFIXED; -+ dev->n_ecc_unfixed++; -+ } -+ if (tags && retval == -EUCLEAN -+ && tags->ecc_result == YAFFS_ECC_RESULT_NO_ERROR) { -+ tags->ecc_result = YAFFS_ECC_RESULT_FIXED; -+ dev->n_ecc_fixed++; -+ } -+ if (retval == 0) -+ return YAFFS_OK; -+ else -+ return YAFFS_FAIL; -+} -+ -+int nandmtd2_mark_block_bad(struct yaffs_dev *dev, int block_no) -+{ -+ struct mtd_info *mtd = yaffs_dev_to_mtd(dev); -+ int retval; -+ T(YAFFS_TRACE_MTD, -+ (TSTR("nandmtd2_mark_block_bad %d" TENDSTR), block_no)); -+ -+ retval = -+ mtd->block_markbad(mtd, -+ block_no * dev->param.chunks_per_block * -+ dev->param.total_bytes_per_chunk); -+ -+ if (retval == 0) -+ return YAFFS_OK; -+ else -+ return YAFFS_FAIL; -+ -+} -+ -+int nandmtd2_query_block(struct yaffs_dev *dev, int block_no, -+ enum yaffs_block_state *state, u32 * seq_number) -+{ -+ struct mtd_info *mtd = yaffs_dev_to_mtd(dev); -+ int retval; -+ -+ T(YAFFS_TRACE_MTD, (TSTR("nandmtd2_query_block %d" TENDSTR), block_no)); -+ retval = -+ mtd->block_isbad(mtd, -+ block_no * dev->param.chunks_per_block * -+ dev->param.total_bytes_per_chunk); -+ -+ if (retval) { -+ T(YAFFS_TRACE_MTD, (TSTR("block is bad" TENDSTR))); -+ -+ *state = YAFFS_BLOCK_STATE_DEAD; -+ *seq_number = 0; -+ } else { -+ struct yaffs_ext_tags t; -+ nandmtd2_read_chunk_tags(dev, block_no * -+ dev->param.chunks_per_block, NULL, &t); -+ -+ if (t.chunk_used) { -+ *seq_number = t.seq_number; -+ *state = YAFFS_BLOCK_STATE_NEEDS_SCANNING; -+ } else { -+ *seq_number = 0; -+ *state = YAFFS_BLOCK_STATE_EMPTY; -+ } -+ } -+ T(YAFFS_TRACE_MTD, -+ (TSTR("block is bad seq %d state %d" TENDSTR), *seq_number, *state)); -+ -+ if (retval == 0) -+ return YAFFS_OK; -+ else -+ return YAFFS_FAIL; -+} -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_mtdif2.h linux-2.6.36/fs/yaffs2/yaffs_mtdif2.h ---- linux-2.6.36.orig/fs/yaffs2/yaffs_mtdif2.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_mtdif2.h 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,29 @@ -+/* -+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU Lesser General Public License version 2.1 as -+ * published by the Free Software Foundation. -+ * -+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. -+ */ -+ -+#ifndef __YAFFS_MTDIF2_H__ -+#define __YAFFS_MTDIF2_H__ -+ -+#include "yaffs_guts.h" -+int nandmtd2_write_chunk_tags(struct yaffs_dev *dev, int nand_chunk, -+ const u8 * data, -+ const struct yaffs_ext_tags *tags); -+int nandmtd2_read_chunk_tags(struct yaffs_dev *dev, int nand_chunk, -+ u8 * data, struct yaffs_ext_tags *tags); -+int nandmtd2_mark_block_bad(struct yaffs_dev *dev, int block_no); -+int nandmtd2_query_block(struct yaffs_dev *dev, int block_no, -+ enum yaffs_block_state *state, u32 * seq_number); -+ -+#endif -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_nameval.c linux-2.6.36/fs/yaffs2/yaffs_nameval.c ---- linux-2.6.36.orig/fs/yaffs2/yaffs_nameval.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_nameval.c 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,201 @@ -+/* -+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+/* -+ * This simple implementation of a name-value store assumes a small number of values and fits -+ * into a small finite buffer. -+ * -+ * Each attribute is stored as a record: -+ * sizeof(int) bytes record size. -+ * strnlen+1 bytes name null terminated. -+ * nbytes value. -+ * ---------- -+ * total size stored in record size -+ * -+ * This code has not been tested with unicode yet. -+ */ -+ -+#include "yaffs_nameval.h" -+ -+#include "yportenv.h" -+ -+static int nval_find(const char *xb, int xb_size, const YCHAR * name, -+ int *exist_size) -+{ -+ int pos = 0; -+ int size; -+ -+ memcpy(&size, xb, sizeof(int)); -+ while (size > 0 && (size < xb_size) && (pos + size < xb_size)) { -+ if (yaffs_strncmp -+ ((YCHAR *) (xb + pos + sizeof(int)), name, size) == 0) { -+ if (exist_size) -+ *exist_size = size; -+ return pos; -+ } -+ pos += size; -+ if (pos < xb_size - sizeof(int)) -+ memcpy(&size, xb + pos, sizeof(int)); -+ else -+ size = 0; -+ } -+ if (exist_size) -+ *exist_size = 0; -+ return -1; -+} -+ -+static int nval_used(const char *xb, int xb_size) -+{ -+ int pos = 0; -+ int size; -+ -+ memcpy(&size, xb + pos, sizeof(int)); -+ while (size > 0 && (size < xb_size) && (pos + size < xb_size)) { -+ pos += size; -+ if (pos < xb_size - sizeof(int)) -+ memcpy(&size, xb + pos, sizeof(int)); -+ else -+ size = 0; -+ } -+ return pos; -+} -+ -+int nval_del(char *xb, int xb_size, const YCHAR * name) -+{ -+ int pos = nval_find(xb, xb_size, name, NULL); -+ int size; -+ -+ if (pos >= 0 && pos < xb_size) { -+ /* Find size, shift rest over this record, then zero out the rest of buffer */ -+ memcpy(&size, xb + pos, sizeof(int)); -+ memcpy(xb + pos, xb + pos + size, xb_size - (pos + size)); -+ memset(xb + (xb_size - size), 0, size); -+ return 0; -+ } else { -+ return -ENODATA; -+ } -+} -+ -+int nval_set(char *xb, int xb_size, const YCHAR * name, const char *buf, -+ int bsize, int flags) -+{ -+ int pos; -+ int namelen = yaffs_strnlen(name, xb_size); -+ int reclen; -+ int size_exist = 0; -+ int space; -+ int start; -+ -+ pos = nval_find(xb, xb_size, name, &size_exist); -+ -+ if (flags & XATTR_CREATE && pos >= 0) -+ return -EEXIST; -+ if (flags & XATTR_REPLACE && pos < 0) -+ return -ENODATA; -+ -+ start = nval_used(xb, xb_size); -+ space = xb_size - start + size_exist; -+ -+ reclen = (sizeof(int) + namelen + 1 + bsize); -+ -+ if (reclen > space) -+ return -ENOSPC; -+ -+ if (pos >= 0) { -+ nval_del(xb, xb_size, name); -+ start = nval_used(xb, xb_size); -+ } -+ -+ pos = start; -+ -+ memcpy(xb + pos, &reclen, sizeof(int)); -+ pos += sizeof(int); -+ yaffs_strncpy((YCHAR *) (xb + pos), name, reclen); -+ pos += (namelen + 1); -+ memcpy(xb + pos, buf, bsize); -+ return 0; -+} -+ -+int nval_get(const char *xb, int xb_size, const YCHAR * name, char *buf, -+ int bsize) -+{ -+ int pos = nval_find(xb, xb_size, name, NULL); -+ int size; -+ -+ if (pos >= 0 && pos < xb_size) { -+ -+ memcpy(&size, xb + pos, sizeof(int)); -+ pos += sizeof(int); /* advance past record length */ -+ size -= sizeof(int); -+ -+ /* Advance over name string */ -+ while (xb[pos] && size > 0 && pos < xb_size) { -+ pos++; -+ size--; -+ } -+ /*Advance over NUL */ -+ pos++; -+ size--; -+ -+ if (size <= bsize) { -+ memcpy(buf, xb + pos, size); -+ return size; -+ } -+ -+ } -+ if (pos >= 0) -+ return -ERANGE; -+ else -+ return -ENODATA; -+} -+ -+int nval_list(const char *xb, int xb_size, char *buf, int bsize) -+{ -+ int pos = 0; -+ int size; -+ int name_len; -+ int ncopied = 0; -+ int filled = 0; -+ -+ memcpy(&size, xb + pos, sizeof(int)); -+ while (size > sizeof(int) && size <= xb_size && (pos + size) < xb_size -+ && !filled) { -+ pos += sizeof(int); -+ size -= sizeof(int); -+ name_len = yaffs_strnlen((YCHAR *) (xb + pos), size); -+ if (ncopied + name_len + 1 < bsize) { -+ memcpy(buf, xb + pos, name_len * sizeof(YCHAR)); -+ buf += name_len; -+ *buf = '\0'; -+ buf++; -+ if (sizeof(YCHAR) > 1) { -+ *buf = '\0'; -+ buf++; -+ } -+ ncopied += (name_len + 1); -+ } else { -+ filled = 1; -+ } -+ pos += size; -+ if (pos < xb_size - sizeof(int)) -+ memcpy(&size, xb + pos, sizeof(int)); -+ else -+ size = 0; -+ } -+ return ncopied; -+} -+ -+int nval_hasvalues(const char *xb, int xb_size) -+{ -+ return nval_used(xb, xb_size) > 0; -+} -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_nameval.h linux-2.6.36/fs/yaffs2/yaffs_nameval.h ---- linux-2.6.36.orig/fs/yaffs2/yaffs_nameval.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_nameval.h 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,28 @@ -+/* -+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU Lesser General Public License version 2.1 as -+ * published by the Free Software Foundation. -+ * -+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. -+ */ -+ -+#ifndef __NAMEVAL_H__ -+#define __NAMEVAL_H__ -+ -+#include "yportenv.h" -+ -+int nval_del(char *xb, int xb_size, const YCHAR * name); -+int nval_set(char *xb, int xb_size, const YCHAR * name, const char *buf, -+ int bsize, int flags); -+int nval_get(const char *xb, int xb_size, const YCHAR * name, char *buf, -+ int bsize); -+int nval_list(const char *xb, int xb_size, char *buf, int bsize); -+int nval_hasvalues(const char *xb, int xb_size); -+#endif -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_nand.c linux-2.6.36/fs/yaffs2/yaffs_nand.c ---- linux-2.6.36.orig/fs/yaffs2/yaffs_nand.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_nand.c 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,128 @@ -+/* -+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include "yaffs_nand.h" -+#include "yaffs_tagscompat.h" -+#include "yaffs_tagsvalidity.h" -+ -+#include "yaffs_getblockinfo.h" -+ -+int yaffs_rd_chunk_tags_nand(struct yaffs_dev *dev, int nand_chunk, -+ u8 * buffer, struct yaffs_ext_tags *tags) -+{ -+ int result; -+ struct yaffs_ext_tags local_tags; -+ -+ int realigned_chunk = nand_chunk - dev->chunk_offset; -+ -+ dev->n_page_reads++; -+ -+ /* If there are no tags provided, use local tags to get prioritised gc working */ -+ if (!tags) -+ tags = &local_tags; -+ -+ if (dev->param.read_chunk_tags_fn) -+ result = -+ dev->param.read_chunk_tags_fn(dev, realigned_chunk, buffer, -+ tags); -+ else -+ result = yaffs_tags_compat_rd(dev, -+ realigned_chunk, buffer, tags); -+ if (tags && tags->ecc_result > YAFFS_ECC_RESULT_NO_ERROR) { -+ -+ struct yaffs_block_info *bi; -+ bi = yaffs_get_block_info(dev, -+ nand_chunk / -+ dev->param.chunks_per_block); -+ yaffs_handle_chunk_error(dev, bi); -+ } -+ -+ return result; -+} -+ -+int yaffs_wr_chunk_tags_nand(struct yaffs_dev *dev, -+ int nand_chunk, -+ const u8 * buffer, struct yaffs_ext_tags *tags) -+{ -+ -+ dev->n_page_writes++; -+ -+ nand_chunk -= dev->chunk_offset; -+ -+ if (tags) { -+ tags->seq_number = dev->seq_number; -+ tags->chunk_used = 1; -+ if (!yaffs_validate_tags(tags)) { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR("Writing uninitialised tags" TENDSTR))); -+ YBUG(); -+ } -+ T(YAFFS_TRACE_WRITE, -+ (TSTR("Writing chunk %d tags %d %d" TENDSTR), nand_chunk, -+ tags->obj_id, tags->chunk_id)); -+ } else { -+ T(YAFFS_TRACE_ERROR, (TSTR("Writing with no tags" TENDSTR))); -+ YBUG(); -+ } -+ -+ if (dev->param.write_chunk_tags_fn) -+ return dev->param.write_chunk_tags_fn(dev, nand_chunk, buffer, -+ tags); -+ else -+ return yaffs_tags_compat_wr(dev, nand_chunk, buffer, tags); -+} -+ -+int yaffs_mark_bad(struct yaffs_dev *dev, int block_no) -+{ -+ block_no -= dev->block_offset; -+ -+ if (dev->param.bad_block_fn) -+ return dev->param.bad_block_fn(dev, block_no); -+ else -+ return yaffs_tags_compat_mark_bad(dev, block_no); -+} -+ -+int yaffs_query_init_block_state(struct yaffs_dev *dev, -+ int block_no, -+ enum yaffs_block_state *state, -+ u32 * seq_number) -+{ -+ block_no -= dev->block_offset; -+ -+ if (dev->param.query_block_fn) -+ return dev->param.query_block_fn(dev, block_no, state, -+ seq_number); -+ else -+ return yaffs_tags_compat_query_block(dev, block_no, -+ state, seq_number); -+} -+ -+int yaffs_erase_block(struct yaffs_dev *dev, int flash_block) -+{ -+ int result; -+ -+ flash_block -= dev->block_offset; -+ -+ dev->n_erasures++; -+ -+ result = dev->param.erase_fn(dev, flash_block); -+ -+ return result; -+} -+ -+int yaffs_init_nand(struct yaffs_dev *dev) -+{ -+ if (dev->param.initialise_flash_fn) -+ return dev->param.initialise_flash_fn(dev); -+ return YAFFS_OK; -+} -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_nand.h linux-2.6.36/fs/yaffs2/yaffs_nand.h ---- linux-2.6.36.orig/fs/yaffs2/yaffs_nand.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_nand.h 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,38 @@ -+/* -+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU Lesser General Public License version 2.1 as -+ * published by the Free Software Foundation. -+ * -+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. -+ */ -+ -+#ifndef __YAFFS_NAND_H__ -+#define __YAFFS_NAND_H__ -+#include "yaffs_guts.h" -+ -+int yaffs_rd_chunk_tags_nand(struct yaffs_dev *dev, int nand_chunk, -+ u8 * buffer, struct yaffs_ext_tags *tags); -+ -+int yaffs_wr_chunk_tags_nand(struct yaffs_dev *dev, -+ int nand_chunk, -+ const u8 * buffer, struct yaffs_ext_tags *tags); -+ -+int yaffs_mark_bad(struct yaffs_dev *dev, int block_no); -+ -+int yaffs_query_init_block_state(struct yaffs_dev *dev, -+ int block_no, -+ enum yaffs_block_state *state, -+ unsigned *seq_number); -+ -+int yaffs_erase_block(struct yaffs_dev *dev, int flash_block); -+ -+int yaffs_init_nand(struct yaffs_dev *dev); -+ -+#endif -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_packedtags1.c linux-2.6.36/fs/yaffs2/yaffs_packedtags1.c ---- linux-2.6.36.orig/fs/yaffs2/yaffs_packedtags1.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_packedtags1.c 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,53 @@ -+/* -+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include "yaffs_packedtags1.h" -+#include "yportenv.h" -+ -+void yaffs_pack_tags1(struct yaffs_packed_tags1 *pt, -+ const struct yaffs_ext_tags *t) -+{ -+ pt->chunk_id = t->chunk_id; -+ pt->serial_number = t->serial_number; -+ pt->n_bytes = t->n_bytes; -+ pt->obj_id = t->obj_id; -+ pt->ecc = 0; -+ pt->deleted = (t->is_deleted) ? 0 : 1; -+ pt->unused_stuff = 0; -+ pt->should_be_ff = 0xFFFFFFFF; -+ -+} -+ -+void yaffs_unpack_tags1(struct yaffs_ext_tags *t, -+ const struct yaffs_packed_tags1 *pt) -+{ -+ static const u8 all_ff[] = -+ { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -+ 0xff -+ }; -+ -+ if (memcmp(all_ff, pt, sizeof(struct yaffs_packed_tags1))) { -+ t->block_bad = 0; -+ if (pt->should_be_ff != 0xFFFFFFFF) -+ t->block_bad = 1; -+ t->chunk_used = 1; -+ t->obj_id = pt->obj_id; -+ t->chunk_id = pt->chunk_id; -+ t->n_bytes = pt->n_bytes; -+ t->ecc_result = YAFFS_ECC_RESULT_NO_ERROR; -+ t->is_deleted = (pt->deleted) ? 0 : 1; -+ t->serial_number = pt->serial_number; -+ } else { -+ memset(t, 0, sizeof(struct yaffs_ext_tags)); -+ } -+} -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_packedtags1.h linux-2.6.36/fs/yaffs2/yaffs_packedtags1.h ---- linux-2.6.36.orig/fs/yaffs2/yaffs_packedtags1.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_packedtags1.h 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,39 @@ -+/* -+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU Lesser General Public License version 2.1 as -+ * published by the Free Software Foundation. -+ * -+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. -+ */ -+ -+/* This is used to pack YAFFS1 tags, not YAFFS2 tags. */ -+ -+#ifndef __YAFFS_PACKEDTAGS1_H__ -+#define __YAFFS_PACKEDTAGS1_H__ -+ -+#include "yaffs_guts.h" -+ -+struct yaffs_packed_tags1 { -+ unsigned chunk_id:20; -+ unsigned serial_number:2; -+ unsigned n_bytes:10; -+ unsigned obj_id:18; -+ unsigned ecc:12; -+ unsigned deleted:1; -+ unsigned unused_stuff:1; -+ unsigned should_be_ff; -+ -+}; -+ -+void yaffs_pack_tags1(struct yaffs_packed_tags1 *pt, -+ const struct yaffs_ext_tags *t); -+void yaffs_unpack_tags1(struct yaffs_ext_tags *t, -+ const struct yaffs_packed_tags1 *pt); -+#endif -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_packedtags2.c linux-2.6.36/fs/yaffs2/yaffs_packedtags2.c ---- linux-2.6.36.orig/fs/yaffs2/yaffs_packedtags2.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_packedtags2.c 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,197 @@ -+/* -+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include "yaffs_packedtags2.h" -+#include "yportenv.h" -+#include "yaffs_trace.h" -+#include "yaffs_tagsvalidity.h" -+ -+/* This code packs a set of extended tags into a binary structure for -+ * NAND storage -+ */ -+ -+/* Some of the information is "extra" struff which can be packed in to -+ * speed scanning -+ * This is defined by having the EXTRA_HEADER_INFO_FLAG set. -+ */ -+ -+/* Extra flags applied to chunk_id */ -+ -+#define EXTRA_HEADER_INFO_FLAG 0x80000000 -+#define EXTRA_SHRINK_FLAG 0x40000000 -+#define EXTRA_SHADOWS_FLAG 0x20000000 -+#define EXTRA_SPARE_FLAGS 0x10000000 -+ -+#define ALL_EXTRA_FLAGS 0xF0000000 -+ -+/* Also, the top 4 bits of the object Id are set to the object type. */ -+#define EXTRA_OBJECT_TYPE_SHIFT (28) -+#define EXTRA_OBJECT_TYPE_MASK ((0x0F) << EXTRA_OBJECT_TYPE_SHIFT) -+ -+static void yaffs_dump_packed_tags2_tags_only(const struct -+ yaffs_packed_tags2_tags_only *ptt) -+{ -+ T(YAFFS_TRACE_MTD, -+ (TSTR("packed tags obj %d chunk %d byte %d seq %d" TENDSTR), -+ ptt->obj_id, ptt->chunk_id, ptt->n_bytes, ptt->seq_number)); -+} -+ -+static void yaffs_dump_packed_tags2(const struct yaffs_packed_tags2 *pt) -+{ -+ yaffs_dump_packed_tags2_tags_only(&pt->t); -+} -+ -+static void yaffs_dump_tags2(const struct yaffs_ext_tags *t) -+{ -+ T(YAFFS_TRACE_MTD, -+ (TSTR -+ ("ext.tags eccres %d blkbad %d chused %d obj %d chunk%d byte %d del %d ser %d seq %d" -+ TENDSTR), t->ecc_result, t->block_bad, t->chunk_used, t->obj_id, -+ t->chunk_id, t->n_bytes, t->is_deleted, t->serial_number, -+ t->seq_number)); -+ -+} -+ -+void yaffs_pack_tags2_tags_only(struct yaffs_packed_tags2_tags_only *ptt, -+ const struct yaffs_ext_tags *t) -+{ -+ ptt->chunk_id = t->chunk_id; -+ ptt->seq_number = t->seq_number; -+ ptt->n_bytes = t->n_bytes; -+ ptt->obj_id = t->obj_id; -+ -+ if (t->chunk_id == 0 && t->extra_available) { -+ /* Store the extra header info instead */ -+ /* We save the parent object in the chunk_id */ -+ ptt->chunk_id = EXTRA_HEADER_INFO_FLAG | t->extra_parent_id; -+ if (t->extra_is_shrink) -+ ptt->chunk_id |= EXTRA_SHRINK_FLAG; -+ if (t->extra_shadows) -+ ptt->chunk_id |= EXTRA_SHADOWS_FLAG; -+ -+ ptt->obj_id &= ~EXTRA_OBJECT_TYPE_MASK; -+ ptt->obj_id |= (t->extra_obj_type << EXTRA_OBJECT_TYPE_SHIFT); -+ -+ if (t->extra_obj_type == YAFFS_OBJECT_TYPE_HARDLINK) -+ ptt->n_bytes = t->extra_equiv_id; -+ else if (t->extra_obj_type == YAFFS_OBJECT_TYPE_FILE) -+ ptt->n_bytes = t->extra_length; -+ else -+ ptt->n_bytes = 0; -+ } -+ -+ yaffs_dump_packed_tags2_tags_only(ptt); -+ yaffs_dump_tags2(t); -+} -+ -+void yaffs_pack_tags2(struct yaffs_packed_tags2 *pt, -+ const struct yaffs_ext_tags *t, int tags_ecc) -+{ -+ yaffs_pack_tags2_tags_only(&pt->t, t); -+ -+ if (tags_ecc) -+ yaffs_ecc_calc_other((unsigned char *)&pt->t, -+ sizeof(struct -+ yaffs_packed_tags2_tags_only), -+ &pt->ecc); -+} -+ -+void yaffs_unpack_tags2_tags_only(struct yaffs_ext_tags *t, -+ struct yaffs_packed_tags2_tags_only *ptt) -+{ -+ -+ memset(t, 0, sizeof(struct yaffs_ext_tags)); -+ -+ yaffs_init_tags(t); -+ -+ if (ptt->seq_number != 0xFFFFFFFF) { -+ t->block_bad = 0; -+ t->chunk_used = 1; -+ t->obj_id = ptt->obj_id; -+ t->chunk_id = ptt->chunk_id; -+ t->n_bytes = ptt->n_bytes; -+ t->is_deleted = 0; -+ t->serial_number = 0; -+ t->seq_number = ptt->seq_number; -+ -+ /* Do extra header info stuff */ -+ -+ if (ptt->chunk_id & EXTRA_HEADER_INFO_FLAG) { -+ t->chunk_id = 0; -+ t->n_bytes = 0; -+ -+ t->extra_available = 1; -+ t->extra_parent_id = -+ ptt->chunk_id & (~(ALL_EXTRA_FLAGS)); -+ t->extra_is_shrink = -+ (ptt->chunk_id & EXTRA_SHRINK_FLAG) ? 1 : 0; -+ t->extra_shadows = -+ (ptt->chunk_id & EXTRA_SHADOWS_FLAG) ? 1 : 0; -+ t->extra_obj_type = -+ ptt->obj_id >> EXTRA_OBJECT_TYPE_SHIFT; -+ t->obj_id &= ~EXTRA_OBJECT_TYPE_MASK; -+ -+ if (t->extra_obj_type == YAFFS_OBJECT_TYPE_HARDLINK) -+ t->extra_equiv_id = ptt->n_bytes; -+ else -+ t->extra_length = ptt->n_bytes; -+ } -+ } -+ -+ yaffs_dump_packed_tags2_tags_only(ptt); -+ yaffs_dump_tags2(t); -+ -+} -+ -+void yaffs_unpack_tags2(struct yaffs_ext_tags *t, struct yaffs_packed_tags2 *pt, -+ int tags_ecc) -+{ -+ -+ enum yaffs_ecc_result ecc_result = YAFFS_ECC_RESULT_NO_ERROR; -+ -+ if (pt->t.seq_number != 0xFFFFFFFF && tags_ecc) { -+ /* Chunk is in use and we need to do ECC */ -+ -+ struct yaffs_ecc_other ecc; -+ int result; -+ yaffs_ecc_calc_other((unsigned char *)&pt->t, -+ sizeof(struct -+ yaffs_packed_tags2_tags_only), -+ &ecc); -+ result = -+ yaffs_ecc_correct_other((unsigned char *)&pt->t, -+ sizeof(struct -+ yaffs_packed_tags2_tags_only), -+ &pt->ecc, &ecc); -+ switch (result) { -+ case 0: -+ ecc_result = YAFFS_ECC_RESULT_NO_ERROR; -+ break; -+ case 1: -+ ecc_result = YAFFS_ECC_RESULT_FIXED; -+ break; -+ case -1: -+ ecc_result = YAFFS_ECC_RESULT_UNFIXED; -+ break; -+ default: -+ ecc_result = YAFFS_ECC_RESULT_UNKNOWN; -+ } -+ } -+ -+ yaffs_unpack_tags2_tags_only(t, &pt->t); -+ -+ t->ecc_result = ecc_result; -+ -+ yaffs_dump_packed_tags2(pt); -+ yaffs_dump_tags2(t); -+} -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_packedtags2.h linux-2.6.36/fs/yaffs2/yaffs_packedtags2.h ---- linux-2.6.36.orig/fs/yaffs2/yaffs_packedtags2.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_packedtags2.h 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,47 @@ -+/* -+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU Lesser General Public License version 2.1 as -+ * published by the Free Software Foundation. -+ * -+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. -+ */ -+ -+/* This is used to pack YAFFS2 tags, not YAFFS1tags. */ -+ -+#ifndef __YAFFS_PACKEDTAGS2_H__ -+#define __YAFFS_PACKEDTAGS2_H__ -+ -+#include "yaffs_guts.h" -+#include "yaffs_ecc.h" -+ -+struct yaffs_packed_tags2_tags_only { -+ unsigned seq_number; -+ unsigned obj_id; -+ unsigned chunk_id; -+ unsigned n_bytes; -+}; -+ -+struct yaffs_packed_tags2 { -+ struct yaffs_packed_tags2_tags_only t; -+ struct yaffs_ecc_other ecc; -+}; -+ -+/* Full packed tags with ECC, used for oob tags */ -+void yaffs_pack_tags2(struct yaffs_packed_tags2 *pt, -+ const struct yaffs_ext_tags *t, int tags_ecc); -+void yaffs_unpack_tags2(struct yaffs_ext_tags *t, struct yaffs_packed_tags2 *pt, -+ int tags_ecc); -+ -+/* Only the tags part (no ECC for use with inband tags */ -+void yaffs_pack_tags2_tags_only(struct yaffs_packed_tags2_tags_only *pt, -+ const struct yaffs_ext_tags *t); -+void yaffs_unpack_tags2_tags_only(struct yaffs_ext_tags *t, -+ struct yaffs_packed_tags2_tags_only *pt); -+#endif -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_tagscompat.c linux-2.6.36/fs/yaffs2/yaffs_tagscompat.c ---- linux-2.6.36.orig/fs/yaffs2/yaffs_tagscompat.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_tagscompat.c 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,454 @@ -+/* -+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include "yaffs_guts.h" -+#include "yaffs_tagscompat.h" -+#include "yaffs_ecc.h" -+#include "yaffs_getblockinfo.h" -+#include "yaffs_trace.h" -+ -+static void yaffs_handle_rd_data_error(struct yaffs_dev *dev, int nand_chunk); -+ -+static const char yaffs_count_bits_table[256] = { -+ 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4, -+ 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, -+ 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, -+ 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, -+ 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, -+ 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, -+ 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, -+ 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, -+ 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, -+ 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, -+ 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, -+ 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, -+ 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, -+ 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, -+ 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, -+ 4, 5, 5, 6, 5, 6, 6, 7, 5, 6, 6, 7, 6, 7, 7, 8 -+}; -+ -+int yaffs_count_bits(u8 x) -+{ -+ int ret_val; -+ ret_val = yaffs_count_bits_table[x]; -+ return ret_val; -+} -+ -+/********** Tags ECC calculations *********/ -+ -+void yaffs_calc_ecc(const u8 * data, struct yaffs_spare *spare) -+{ -+ yaffs_ecc_cacl(data, spare->ecc1); -+ yaffs_ecc_cacl(&data[256], spare->ecc2); -+} -+ -+void yaffs_calc_tags_ecc(struct yaffs_tags *tags) -+{ -+ /* Calculate an ecc */ -+ -+ unsigned char *b = ((union yaffs_tags_union *)tags)->as_bytes; -+ unsigned i, j; -+ unsigned ecc = 0; -+ unsigned bit = 0; -+ -+ tags->ecc = 0; -+ -+ for (i = 0; i < 8; i++) { -+ for (j = 1; j & 0xff; j <<= 1) { -+ bit++; -+ if (b[i] & j) -+ ecc ^= bit; -+ } -+ } -+ -+ tags->ecc = ecc; -+ -+} -+ -+int yaffs_check_tags_ecc(struct yaffs_tags *tags) -+{ -+ unsigned ecc = tags->ecc; -+ -+ yaffs_calc_tags_ecc(tags); -+ -+ ecc ^= tags->ecc; -+ -+ if (ecc && ecc <= 64) { -+ /* TODO: Handle the failure better. Retire? */ -+ unsigned char *b = ((union yaffs_tags_union *)tags)->as_bytes; -+ -+ ecc--; -+ -+ b[ecc / 8] ^= (1 << (ecc & 7)); -+ -+ /* Now recvalc the ecc */ -+ yaffs_calc_tags_ecc(tags); -+ -+ return 1; /* recovered error */ -+ } else if (ecc) { -+ /* Wierd ecc failure value */ -+ /* TODO Need to do somethiong here */ -+ return -1; /* unrecovered error */ -+ } -+ -+ return 0; -+} -+ -+/********** Tags **********/ -+ -+static void yaffs_load_tags_to_spare(struct yaffs_spare *spare_ptr, -+ struct yaffs_tags *tags_ptr) -+{ -+ union yaffs_tags_union *tu = (union yaffs_tags_union *)tags_ptr; -+ -+ yaffs_calc_tags_ecc(tags_ptr); -+ -+ spare_ptr->tb0 = tu->as_bytes[0]; -+ spare_ptr->tb1 = tu->as_bytes[1]; -+ spare_ptr->tb2 = tu->as_bytes[2]; -+ spare_ptr->tb3 = tu->as_bytes[3]; -+ spare_ptr->tb4 = tu->as_bytes[4]; -+ spare_ptr->tb5 = tu->as_bytes[5]; -+ spare_ptr->tb6 = tu->as_bytes[6]; -+ spare_ptr->tb7 = tu->as_bytes[7]; -+} -+ -+static void yaffs_get_tags_from_spare(struct yaffs_dev *dev, -+ struct yaffs_spare *spare_ptr, -+ struct yaffs_tags *tags_ptr) -+{ -+ union yaffs_tags_union *tu = (union yaffs_tags_union *)tags_ptr; -+ int result; -+ -+ tu->as_bytes[0] = spare_ptr->tb0; -+ tu->as_bytes[1] = spare_ptr->tb1; -+ tu->as_bytes[2] = spare_ptr->tb2; -+ tu->as_bytes[3] = spare_ptr->tb3; -+ tu->as_bytes[4] = spare_ptr->tb4; -+ tu->as_bytes[5] = spare_ptr->tb5; -+ tu->as_bytes[6] = spare_ptr->tb6; -+ tu->as_bytes[7] = spare_ptr->tb7; -+ -+ result = yaffs_check_tags_ecc(tags_ptr); -+ if (result > 0) -+ dev->n_tags_ecc_fixed++; -+ else if (result < 0) -+ dev->n_tags_ecc_unfixed++; -+} -+ -+static void yaffs_spare_init(struct yaffs_spare *spare) -+{ -+ memset(spare, 0xFF, sizeof(struct yaffs_spare)); -+} -+ -+static int yaffs_wr_nand(struct yaffs_dev *dev, -+ int nand_chunk, const u8 * data, -+ struct yaffs_spare *spare) -+{ -+ if (nand_chunk < dev->param.start_block * dev->param.chunks_per_block) { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR("**>> yaffs chunk %d is not valid" TENDSTR), -+ nand_chunk)); -+ return YAFFS_FAIL; -+ } -+ -+ return dev->param.write_chunk_fn(dev, nand_chunk, data, spare); -+} -+ -+static int yaffs_rd_chunk_nand(struct yaffs_dev *dev, -+ int nand_chunk, -+ u8 * data, -+ struct yaffs_spare *spare, -+ enum yaffs_ecc_result *ecc_result, -+ int correct_errors) -+{ -+ int ret_val; -+ struct yaffs_spare local_spare; -+ -+ if (!spare && data) { -+ /* If we don't have a real spare, then we use a local one. */ -+ /* Need this for the calculation of the ecc */ -+ spare = &local_spare; -+ } -+ -+ if (!dev->param.use_nand_ecc) { -+ ret_val = -+ dev->param.read_chunk_fn(dev, nand_chunk, data, spare); -+ if (data && correct_errors) { -+ /* Do ECC correction */ -+ /* Todo handle any errors */ -+ int ecc_result1, ecc_result2; -+ u8 calc_ecc[3]; -+ -+ yaffs_ecc_cacl(data, calc_ecc); -+ ecc_result1 = -+ yaffs_ecc_correct(data, spare->ecc1, calc_ecc); -+ yaffs_ecc_cacl(&data[256], calc_ecc); -+ ecc_result2 = -+ yaffs_ecc_correct(&data[256], spare->ecc2, -+ calc_ecc); -+ -+ if (ecc_result1 > 0) { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR -+ ("**>>yaffs ecc error fix performed on chunk %d:0" -+ TENDSTR), nand_chunk)); -+ dev->n_ecc_fixed++; -+ } else if (ecc_result1 < 0) { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR -+ ("**>>yaffs ecc error unfixed on chunk %d:0" -+ TENDSTR), nand_chunk)); -+ dev->n_ecc_unfixed++; -+ } -+ -+ if (ecc_result2 > 0) { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR -+ ("**>>yaffs ecc error fix performed on chunk %d:1" -+ TENDSTR), nand_chunk)); -+ dev->n_ecc_fixed++; -+ } else if (ecc_result2 < 0) { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR -+ ("**>>yaffs ecc error unfixed on chunk %d:1" -+ TENDSTR), nand_chunk)); -+ dev->n_ecc_unfixed++; -+ } -+ -+ if (ecc_result1 || ecc_result2) { -+ /* We had a data problem on this page */ -+ yaffs_handle_rd_data_error(dev, nand_chunk); -+ } -+ -+ if (ecc_result1 < 0 || ecc_result2 < 0) -+ *ecc_result = YAFFS_ECC_RESULT_UNFIXED; -+ else if (ecc_result1 > 0 || ecc_result2 > 0) -+ *ecc_result = YAFFS_ECC_RESULT_FIXED; -+ else -+ *ecc_result = YAFFS_ECC_RESULT_NO_ERROR; -+ } -+ } else { -+ /* Must allocate enough memory for spare+2*sizeof(int) */ -+ /* for ecc results from device. */ -+ struct yaffs_nand_spare nspare; -+ -+ memset(&nspare, 0, sizeof(nspare)); -+ -+ ret_val = dev->param.read_chunk_fn(dev, nand_chunk, data, -+ (struct yaffs_spare *) -+ &nspare); -+ memcpy(spare, &nspare, sizeof(struct yaffs_spare)); -+ if (data && correct_errors) { -+ if (nspare.eccres1 > 0) { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR -+ ("**>>mtd ecc error fix performed on chunk %d:0" -+ TENDSTR), nand_chunk)); -+ } else if (nspare.eccres1 < 0) { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR -+ ("**>>mtd ecc error unfixed on chunk %d:0" -+ TENDSTR), nand_chunk)); -+ } -+ -+ if (nspare.eccres2 > 0) { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR -+ ("**>>mtd ecc error fix performed on chunk %d:1" -+ TENDSTR), nand_chunk)); -+ } else if (nspare.eccres2 < 0) { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR -+ ("**>>mtd ecc error unfixed on chunk %d:1" -+ TENDSTR), nand_chunk)); -+ } -+ -+ if (nspare.eccres1 || nspare.eccres2) { -+ /* We had a data problem on this page */ -+ yaffs_handle_rd_data_error(dev, nand_chunk); -+ } -+ -+ if (nspare.eccres1 < 0 || nspare.eccres2 < 0) -+ *ecc_result = YAFFS_ECC_RESULT_UNFIXED; -+ else if (nspare.eccres1 > 0 || nspare.eccres2 > 0) -+ *ecc_result = YAFFS_ECC_RESULT_FIXED; -+ else -+ *ecc_result = YAFFS_ECC_RESULT_NO_ERROR; -+ -+ } -+ } -+ return ret_val; -+} -+ -+/* -+ * Functions for robustisizing -+ */ -+ -+static void yaffs_handle_rd_data_error(struct yaffs_dev *dev, int nand_chunk) -+{ -+ int flash_block = nand_chunk / dev->param.chunks_per_block; -+ -+ /* Mark the block for retirement */ -+ yaffs_get_block_info(dev, -+ flash_block + dev->block_offset)->needs_retiring = -+ 1; -+ T(YAFFS_TRACE_ERROR | YAFFS_TRACE_BAD_BLOCKS, -+ (TSTR("**>>Block %d marked for retirement" TENDSTR), flash_block)); -+ -+ /* TODO: -+ * Just do a garbage collection on the affected block -+ * then retire the block -+ * NB recursion -+ */ -+} -+ -+int yaffs_tags_compat_wr(struct yaffs_dev *dev, -+ int nand_chunk, -+ const u8 * data, const struct yaffs_ext_tags *ext_tags) -+{ -+ struct yaffs_spare spare; -+ struct yaffs_tags tags; -+ -+ yaffs_spare_init(&spare); -+ -+ if (ext_tags->is_deleted) -+ spare.page_status = 0; -+ else { -+ tags.obj_id = ext_tags->obj_id; -+ tags.chunk_id = ext_tags->chunk_id; -+ -+ tags.n_bytes_lsb = ext_tags->n_bytes & 0x3ff; -+ -+ if (dev->data_bytes_per_chunk >= 1024) -+ tags.n_bytes_msb = (ext_tags->n_bytes >> 10) & 3; -+ else -+ tags.n_bytes_msb = 3; -+ -+ tags.serial_number = ext_tags->serial_number; -+ -+ if (!dev->param.use_nand_ecc && data) -+ yaffs_calc_ecc(data, &spare); -+ -+ yaffs_load_tags_to_spare(&spare, &tags); -+ -+ } -+ -+ return yaffs_wr_nand(dev, nand_chunk, data, &spare); -+} -+ -+int yaffs_tags_compat_rd(struct yaffs_dev *dev, -+ int nand_chunk, -+ u8 * data, struct yaffs_ext_tags *ext_tags) -+{ -+ -+ struct yaffs_spare spare; -+ struct yaffs_tags tags; -+ enum yaffs_ecc_result ecc_result = YAFFS_ECC_RESULT_UNKNOWN; -+ -+ static struct yaffs_spare spare_ff; -+ static int init; -+ -+ if (!init) { -+ memset(&spare_ff, 0xFF, sizeof(spare_ff)); -+ init = 1; -+ } -+ -+ if (yaffs_rd_chunk_nand(dev, nand_chunk, data, &spare, &ecc_result, 1)) { -+ /* ext_tags may be NULL */ -+ if (ext_tags) { -+ -+ int deleted = -+ (yaffs_count_bits(spare.page_status) < 7) ? 1 : 0; -+ -+ ext_tags->is_deleted = deleted; -+ ext_tags->ecc_result = ecc_result; -+ ext_tags->block_bad = 0; /* We're reading it */ -+ /* therefore it is not a bad block */ -+ ext_tags->chunk_used = -+ (memcmp(&spare_ff, &spare, sizeof(spare_ff)) != -+ 0) ? 1 : 0; -+ -+ if (ext_tags->chunk_used) { -+ yaffs_get_tags_from_spare(dev, &spare, &tags); -+ -+ ext_tags->obj_id = tags.obj_id; -+ ext_tags->chunk_id = tags.chunk_id; -+ ext_tags->n_bytes = tags.n_bytes_lsb; -+ -+ if (dev->data_bytes_per_chunk >= 1024) -+ ext_tags->n_bytes |= -+ (((unsigned)tags. -+ n_bytes_msb) << 10); -+ -+ ext_tags->serial_number = tags.serial_number; -+ } -+ } -+ -+ return YAFFS_OK; -+ } else { -+ return YAFFS_FAIL; -+ } -+} -+ -+int yaffs_tags_compat_mark_bad(struct yaffs_dev *dev, int flash_block) -+{ -+ -+ struct yaffs_spare spare; -+ -+ memset(&spare, 0xff, sizeof(struct yaffs_spare)); -+ -+ spare.block_status = 'Y'; -+ -+ yaffs_wr_nand(dev, flash_block * dev->param.chunks_per_block, NULL, -+ &spare); -+ yaffs_wr_nand(dev, flash_block * dev->param.chunks_per_block + 1, -+ NULL, &spare); -+ -+ return YAFFS_OK; -+ -+} -+ -+int yaffs_tags_compat_query_block(struct yaffs_dev *dev, -+ int block_no, -+ enum yaffs_block_state *state, -+ u32 * seq_number) -+{ -+ -+ struct yaffs_spare spare0, spare1; -+ static struct yaffs_spare spare_ff; -+ static int init; -+ enum yaffs_ecc_result dummy; -+ -+ if (!init) { -+ memset(&spare_ff, 0xFF, sizeof(spare_ff)); -+ init = 1; -+ } -+ -+ *seq_number = 0; -+ -+ yaffs_rd_chunk_nand(dev, block_no * dev->param.chunks_per_block, NULL, -+ &spare0, &dummy, 1); -+ yaffs_rd_chunk_nand(dev, block_no * dev->param.chunks_per_block + 1, -+ NULL, &spare1, &dummy, 1); -+ -+ if (yaffs_count_bits(spare0.block_status & spare1.block_status) < 7) -+ *state = YAFFS_BLOCK_STATE_DEAD; -+ else if (memcmp(&spare_ff, &spare0, sizeof(spare_ff)) == 0) -+ *state = YAFFS_BLOCK_STATE_EMPTY; -+ else -+ *state = YAFFS_BLOCK_STATE_NEEDS_SCANNING; -+ -+ return YAFFS_OK; -+} -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_tagscompat.h linux-2.6.36/fs/yaffs2/yaffs_tagscompat.h ---- linux-2.6.36.orig/fs/yaffs2/yaffs_tagscompat.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_tagscompat.h 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,36 @@ -+/* -+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU Lesser General Public License version 2.1 as -+ * published by the Free Software Foundation. -+ * -+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. -+ */ -+ -+#ifndef __YAFFS_TAGSCOMPAT_H__ -+#define __YAFFS_TAGSCOMPAT_H__ -+ -+#include "yaffs_guts.h" -+int yaffs_tags_compat_wr(struct yaffs_dev *dev, -+ int nand_chunk, -+ const u8 * data, const struct yaffs_ext_tags *tags); -+int yaffs_tags_compat_rd(struct yaffs_dev *dev, -+ int nand_chunk, -+ u8 * data, struct yaffs_ext_tags *tags); -+int yaffs_tags_compat_mark_bad(struct yaffs_dev *dev, int block_no); -+int yaffs_tags_compat_query_block(struct yaffs_dev *dev, -+ int block_no, -+ enum yaffs_block_state *state, -+ u32 * seq_number); -+ -+void yaffs_calc_tags_ecc(struct yaffs_tags *tags); -+int yaffs_check_tags_ecc(struct yaffs_tags *tags); -+int yaffs_count_bits(u8 byte); -+ -+#endif -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_tagsvalidity.c linux-2.6.36/fs/yaffs2/yaffs_tagsvalidity.c ---- linux-2.6.36.orig/fs/yaffs2/yaffs_tagsvalidity.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_tagsvalidity.c 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,27 @@ -+/* -+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include "yaffs_tagsvalidity.h" -+ -+void yaffs_init_tags(struct yaffs_ext_tags *tags) -+{ -+ memset(tags, 0, sizeof(struct yaffs_ext_tags)); -+ tags->validity0 = 0xAAAAAAAA; -+ tags->validity1 = 0x55555555; -+} -+ -+int yaffs_validate_tags(struct yaffs_ext_tags *tags) -+{ -+ return (tags->validity0 == 0xAAAAAAAA && tags->validity1 == 0x55555555); -+ -+} -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_tagsvalidity.h linux-2.6.36/fs/yaffs2/yaffs_tagsvalidity.h ---- linux-2.6.36.orig/fs/yaffs2/yaffs_tagsvalidity.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_tagsvalidity.h 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,23 @@ -+/* -+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU Lesser General Public License version 2.1 as -+ * published by the Free Software Foundation. -+ * -+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. -+ */ -+ -+#ifndef __YAFFS_TAGS_VALIDITY_H__ -+#define __YAFFS_TAGS_VALIDITY_H__ -+ -+#include "yaffs_guts.h" -+ -+void yaffs_init_tags(struct yaffs_ext_tags *tags); -+int yaffs_validate_tags(struct yaffs_ext_tags *tags); -+#endif -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_trace.h linux-2.6.36/fs/yaffs2/yaffs_trace.h ---- linux-2.6.36.orig/fs/yaffs2/yaffs_trace.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_trace.h 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,59 @@ -+/* -+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU Lesser General Public License version 2.1 as -+ * published by the Free Software Foundation. -+ * -+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. -+ */ -+ -+#ifndef __YTRACE_H__ -+#define __YTRACE_H__ -+ -+extern unsigned int yaffs_trace_mask; -+extern unsigned int yaffs_wr_attempts; -+ -+/* -+ * Tracing flags. -+ * The flags masked in YAFFS_TRACE_ALWAYS are always traced. -+ */ -+ -+#define YAFFS_TRACE_OS 0x00000002 -+#define YAFFS_TRACE_ALLOCATE 0x00000004 -+#define YAFFS_TRACE_SCAN 0x00000008 -+#define YAFFS_TRACE_BAD_BLOCKS 0x00000010 -+#define YAFFS_TRACE_ERASE 0x00000020 -+#define YAFFS_TRACE_GC 0x00000040 -+#define YAFFS_TRACE_WRITE 0x00000080 -+#define YAFFS_TRACE_TRACING 0x00000100 -+#define YAFFS_TRACE_DELETION 0x00000200 -+#define YAFFS_TRACE_BUFFERS 0x00000400 -+#define YAFFS_TRACE_NANDACCESS 0x00000800 -+#define YAFFS_TRACE_GC_DETAIL 0x00001000 -+#define YAFFS_TRACE_SCAN_DEBUG 0x00002000 -+#define YAFFS_TRACE_MTD 0x00004000 -+#define YAFFS_TRACE_CHECKPOINT 0x00008000 -+ -+#define YAFFS_TRACE_VERIFY 0x00010000 -+#define YAFFS_TRACE_VERIFY_NAND 0x00020000 -+#define YAFFS_TRACE_VERIFY_FULL 0x00040000 -+#define YAFFS_TRACE_VERIFY_ALL 0x000F0000 -+ -+#define YAFFS_TRACE_SYNC 0x00100000 -+#define YAFFS_TRACE_BACKGROUND 0x00200000 -+#define YAFFS_TRACE_LOCK 0x00400000 -+#define YAFFS_TRACE_MOUNT 0x00800000 -+ -+#define YAFFS_TRACE_ERROR 0x40000000 -+#define YAFFS_TRACE_BUG 0x80000000 -+#define YAFFS_TRACE_ALWAYS 0xF0000000 -+ -+#define T(mask, p) do { if ((mask) & (yaffs_trace_mask | YAFFS_TRACE_ALWAYS)) TOUT(p); } while (0) -+ -+#endif -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_verify.c linux-2.6.36/fs/yaffs2/yaffs_verify.c ---- linux-2.6.36.orig/fs/yaffs2/yaffs_verify.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_verify.c 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,546 @@ -+/* -+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include "yaffs_verify.h" -+#include "yaffs_trace.h" -+#include "yaffs_bitmap.h" -+#include "yaffs_getblockinfo.h" -+#include "yaffs_nand.h" -+ -+int yaffs_skip_verification(struct yaffs_dev *dev) -+{ -+ dev = dev; -+ return !(yaffs_trace_mask & -+ (YAFFS_TRACE_VERIFY | YAFFS_TRACE_VERIFY_FULL)); -+} -+ -+static int yaffs_skip_full_verification(struct yaffs_dev *dev) -+{ -+ dev = dev; -+ return !(yaffs_trace_mask & (YAFFS_TRACE_VERIFY_FULL)); -+} -+ -+static int yaffs_skip_nand_verification(struct yaffs_dev *dev) -+{ -+ dev = dev; -+ return !(yaffs_trace_mask & (YAFFS_TRACE_VERIFY_NAND)); -+} -+ -+static const char *block_state_name[] = { -+ "Unknown", -+ "Needs scanning", -+ "Scanning", -+ "Empty", -+ "Allocating", -+ "Full", -+ "Dirty", -+ "Checkpoint", -+ "Collecting", -+ "Dead" -+}; -+ -+void yaffs_verify_blk(struct yaffs_dev *dev, struct yaffs_block_info *bi, int n) -+{ -+ int actually_used; -+ int in_use; -+ -+ if (yaffs_skip_verification(dev)) -+ return; -+ -+ /* Report illegal runtime states */ -+ if (bi->block_state >= YAFFS_NUMBER_OF_BLOCK_STATES) -+ T(YAFFS_TRACE_VERIFY, -+ (TSTR("Block %d has undefined state %d" TENDSTR), n, -+ bi->block_state)); -+ -+ switch (bi->block_state) { -+ case YAFFS_BLOCK_STATE_UNKNOWN: -+ case YAFFS_BLOCK_STATE_SCANNING: -+ case YAFFS_BLOCK_STATE_NEEDS_SCANNING: -+ T(YAFFS_TRACE_VERIFY, -+ (TSTR("Block %d has bad run-state %s" TENDSTR), n, -+ block_state_name[bi->block_state])); -+ } -+ -+ /* Check pages in use and soft deletions are legal */ -+ -+ actually_used = bi->pages_in_use - bi->soft_del_pages; -+ -+ if (bi->pages_in_use < 0 -+ || bi->pages_in_use > dev->param.chunks_per_block -+ || bi->soft_del_pages < 0 -+ || bi->soft_del_pages > dev->param.chunks_per_block -+ || actually_used < 0 || actually_used > dev->param.chunks_per_block) -+ T(YAFFS_TRACE_VERIFY, -+ (TSTR -+ ("Block %d has illegal values pages_in_used %d soft_del_pages %d" -+ TENDSTR), n, bi->pages_in_use, bi->soft_del_pages)); -+ -+ /* Check chunk bitmap legal */ -+ in_use = yaffs_count_chunk_bits(dev, n); -+ if (in_use != bi->pages_in_use) -+ T(YAFFS_TRACE_VERIFY, -+ (TSTR -+ ("Block %d has inconsistent values pages_in_use %d counted chunk bits %d" -+ TENDSTR), n, bi->pages_in_use, in_use)); -+ -+} -+ -+void yaffs_verify_collected_blk(struct yaffs_dev *dev, -+ struct yaffs_block_info *bi, int n) -+{ -+ yaffs_verify_blk(dev, bi, n); -+ -+ /* After collection the block should be in the erased state */ -+ -+ if (bi->block_state != YAFFS_BLOCK_STATE_COLLECTING && -+ bi->block_state != YAFFS_BLOCK_STATE_EMPTY) { -+ T(YAFFS_TRACE_ERROR, -+ (TSTR -+ ("Block %d is in state %d after gc, should be erased" -+ TENDSTR), n, bi->block_state)); -+ } -+} -+ -+void yaffs_verify_blocks(struct yaffs_dev *dev) -+{ -+ int i; -+ int state_count[YAFFS_NUMBER_OF_BLOCK_STATES]; -+ int illegal_states = 0; -+ -+ if (yaffs_skip_verification(dev)) -+ return; -+ -+ memset(state_count, 0, sizeof(state_count)); -+ -+ for (i = dev->internal_start_block; i <= dev->internal_end_block; i++) { -+ struct yaffs_block_info *bi = yaffs_get_block_info(dev, i); -+ yaffs_verify_blk(dev, bi, i); -+ -+ if (bi->block_state < YAFFS_NUMBER_OF_BLOCK_STATES) -+ state_count[bi->block_state]++; -+ else -+ illegal_states++; -+ } -+ -+ T(YAFFS_TRACE_VERIFY, (TSTR("" TENDSTR))); -+ T(YAFFS_TRACE_VERIFY, (TSTR("Block summary" TENDSTR))); -+ -+ T(YAFFS_TRACE_VERIFY, -+ (TSTR("%d blocks have illegal states" TENDSTR), illegal_states)); -+ if (state_count[YAFFS_BLOCK_STATE_ALLOCATING] > 1) -+ T(YAFFS_TRACE_VERIFY, -+ (TSTR("Too many allocating blocks" TENDSTR))); -+ -+ for (i = 0; i < YAFFS_NUMBER_OF_BLOCK_STATES; i++) -+ T(YAFFS_TRACE_VERIFY, -+ (TSTR("%s %d blocks" TENDSTR), -+ block_state_name[i], state_count[i])); -+ -+ if (dev->blocks_in_checkpt != state_count[YAFFS_BLOCK_STATE_CHECKPOINT]) -+ T(YAFFS_TRACE_VERIFY, -+ (TSTR("Checkpoint block count wrong dev %d count %d" TENDSTR), -+ dev->blocks_in_checkpt, -+ state_count[YAFFS_BLOCK_STATE_CHECKPOINT])); -+ -+ if (dev->n_erased_blocks != state_count[YAFFS_BLOCK_STATE_EMPTY]) -+ T(YAFFS_TRACE_VERIFY, -+ (TSTR("Erased block count wrong dev %d count %d" TENDSTR), -+ dev->n_erased_blocks, state_count[YAFFS_BLOCK_STATE_EMPTY])); -+ -+ if (state_count[YAFFS_BLOCK_STATE_COLLECTING] > 1) -+ T(YAFFS_TRACE_VERIFY, -+ (TSTR("Too many collecting blocks %d (max is 1)" TENDSTR), -+ state_count[YAFFS_BLOCK_STATE_COLLECTING])); -+ -+ T(YAFFS_TRACE_VERIFY, (TSTR("" TENDSTR))); -+ -+} -+ -+/* -+ * Verify the object header. oh must be valid, but obj and tags may be NULL in which -+ * case those tests will not be performed. -+ */ -+void yaffs_verify_oh(struct yaffs_obj *obj, struct yaffs_obj_hdr *oh, -+ struct yaffs_ext_tags *tags, int parent_check) -+{ -+ if (obj && yaffs_skip_verification(obj->my_dev)) -+ return; -+ -+ if (!(tags && obj && oh)) { -+ T(YAFFS_TRACE_VERIFY, -+ (TSTR("Verifying object header tags %p obj %p oh %p" TENDSTR), -+ tags, obj, oh)); -+ return; -+ } -+ -+ if (oh->type <= YAFFS_OBJECT_TYPE_UNKNOWN || -+ oh->type > YAFFS_OBJECT_TYPE_MAX) -+ T(YAFFS_TRACE_VERIFY, -+ (TSTR("Obj %d header type is illegal value 0x%x" TENDSTR), -+ tags->obj_id, oh->type)); -+ -+ if (tags->obj_id != obj->obj_id) -+ T(YAFFS_TRACE_VERIFY, -+ (TSTR("Obj %d header mismatch obj_id %d" TENDSTR), -+ tags->obj_id, obj->obj_id)); -+ -+ /* -+ * Check that the object's parent ids match if parent_check requested. -+ * -+ * Tests do not apply to the root object. -+ */ -+ -+ if (parent_check && tags->obj_id > 1 && !obj->parent) -+ T(YAFFS_TRACE_VERIFY, -+ (TSTR -+ ("Obj %d header mismatch parent_id %d obj->parent is NULL" -+ TENDSTR), tags->obj_id, oh->parent_obj_id)); -+ -+ if (parent_check && obj->parent && -+ oh->parent_obj_id != obj->parent->obj_id && -+ (oh->parent_obj_id != YAFFS_OBJECTID_UNLINKED || -+ obj->parent->obj_id != YAFFS_OBJECTID_DELETED)) -+ T(YAFFS_TRACE_VERIFY, -+ (TSTR -+ ("Obj %d header mismatch parent_id %d parent_obj_id %d" -+ TENDSTR), tags->obj_id, oh->parent_obj_id, -+ obj->parent->obj_id)); -+ -+ if (tags->obj_id > 1 && oh->name[0] == 0) /* Null name */ -+ T(YAFFS_TRACE_VERIFY, -+ (TSTR("Obj %d header name is NULL" TENDSTR), obj->obj_id)); -+ -+ if (tags->obj_id > 1 && ((u8) (oh->name[0])) == 0xff) /* Trashed name */ -+ T(YAFFS_TRACE_VERIFY, -+ (TSTR("Obj %d header name is 0xFF" TENDSTR), obj->obj_id)); -+} -+ -+void yaffs_verify_file(struct yaffs_obj *obj) -+{ -+ int required_depth; -+ int actual_depth; -+ u32 last_chunk; -+ u32 x; -+ u32 i; -+ struct yaffs_dev *dev; -+ struct yaffs_ext_tags tags; -+ struct yaffs_tnode *tn; -+ u32 obj_id; -+ -+ if (!obj) -+ return; -+ -+ if (yaffs_skip_verification(obj->my_dev)) -+ return; -+ -+ dev = obj->my_dev; -+ obj_id = obj->obj_id; -+ -+ /* Check file size is consistent with tnode depth */ -+ last_chunk = -+ obj->variant.file_variant.file_size / dev->data_bytes_per_chunk + 1; -+ x = last_chunk >> YAFFS_TNODES_LEVEL0_BITS; -+ required_depth = 0; -+ while (x > 0) { -+ x >>= YAFFS_TNODES_INTERNAL_BITS; -+ required_depth++; -+ } -+ -+ actual_depth = obj->variant.file_variant.top_level; -+ -+ /* Check that the chunks in the tnode tree are all correct. -+ * We do this by scanning through the tnode tree and -+ * checking the tags for every chunk match. -+ */ -+ -+ if (yaffs_skip_nand_verification(dev)) -+ return; -+ -+ for (i = 1; i <= last_chunk; i++) { -+ tn = yaffs_find_tnode_0(dev, &obj->variant.file_variant, i); -+ -+ if (tn) { -+ u32 the_chunk = yaffs_get_group_base(dev, tn, i); -+ if (the_chunk > 0) { -+ /* T(~0,(TSTR("verifying (%d:%d) %d"TENDSTR),obj_id,i,the_chunk)); */ -+ yaffs_rd_chunk_tags_nand(dev, the_chunk, NULL, -+ &tags); -+ if (tags.obj_id != obj_id || tags.chunk_id != i) { -+ T(~0, -+ (TSTR -+ ("Object %d chunk_id %d NAND mismatch chunk %d tags (%d:%d)" -+ TENDSTR), obj_id, i, the_chunk, -+ tags.obj_id, tags.chunk_id)); -+ } -+ } -+ } -+ } -+} -+ -+void yaffs_verify_link(struct yaffs_obj *obj) -+{ -+ if (obj && yaffs_skip_verification(obj->my_dev)) -+ return; -+ -+ /* Verify sane equivalent object */ -+} -+ -+void yaffs_verify_symlink(struct yaffs_obj *obj) -+{ -+ if (obj && yaffs_skip_verification(obj->my_dev)) -+ return; -+ -+ /* Verify symlink string */ -+} -+ -+void yaffs_verify_special(struct yaffs_obj *obj) -+{ -+ if (obj && yaffs_skip_verification(obj->my_dev)) -+ return; -+} -+ -+void yaffs_verify_obj(struct yaffs_obj *obj) -+{ -+ struct yaffs_dev *dev; -+ -+ u32 chunk_min; -+ u32 chunk_max; -+ -+ u32 chunk_id_ok; -+ u32 chunk_in_range; -+ u32 chunk_wrongly_deleted; -+ u32 chunk_valid; -+ -+ if (!obj) -+ return; -+ -+ if (obj->being_created) -+ return; -+ -+ dev = obj->my_dev; -+ -+ if (yaffs_skip_verification(dev)) -+ return; -+ -+ /* Check sane object header chunk */ -+ -+ chunk_min = dev->internal_start_block * dev->param.chunks_per_block; -+ chunk_max = -+ (dev->internal_end_block + 1) * dev->param.chunks_per_block - 1; -+ -+ chunk_in_range = (((unsigned)(obj->hdr_chunk)) >= chunk_min && -+ ((unsigned)(obj->hdr_chunk)) <= chunk_max); -+ chunk_id_ok = chunk_in_range || (obj->hdr_chunk == 0); -+ chunk_valid = chunk_in_range && -+ yaffs_check_chunk_bit(dev, -+ obj->hdr_chunk / dev->param.chunks_per_block, -+ obj->hdr_chunk % dev->param.chunks_per_block); -+ chunk_wrongly_deleted = chunk_in_range && !chunk_valid; -+ -+ if (!obj->fake && (!chunk_id_ok || chunk_wrongly_deleted)) { -+ T(YAFFS_TRACE_VERIFY, -+ (TSTR("Obj %d has chunk_id %d %s %s" TENDSTR), -+ obj->obj_id, obj->hdr_chunk, -+ chunk_id_ok ? "" : ",out of range", -+ chunk_wrongly_deleted ? ",marked as deleted" : "")); -+ } -+ -+ if (chunk_valid && !yaffs_skip_nand_verification(dev)) { -+ struct yaffs_ext_tags tags; -+ struct yaffs_obj_hdr *oh; -+ u8 *buffer = yaffs_get_temp_buffer(dev, __LINE__); -+ -+ oh = (struct yaffs_obj_hdr *)buffer; -+ -+ yaffs_rd_chunk_tags_nand(dev, obj->hdr_chunk, buffer, &tags); -+ -+ yaffs_verify_oh(obj, oh, &tags, 1); -+ -+ yaffs_release_temp_buffer(dev, buffer, __LINE__); -+ } -+ -+ /* Verify it has a parent */ -+ if (obj && !obj->fake && (!obj->parent || obj->parent->my_dev != dev)) { -+ T(YAFFS_TRACE_VERIFY, -+ (TSTR -+ ("Obj %d has parent pointer %p which does not look like an object" -+ TENDSTR), obj->obj_id, obj->parent)); -+ } -+ -+ /* Verify parent is a directory */ -+ if (obj->parent -+ && obj->parent->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) { -+ T(YAFFS_TRACE_VERIFY, -+ (TSTR("Obj %d's parent is not a directory (type %d)" TENDSTR), -+ obj->obj_id, obj->parent->variant_type)); -+ } -+ -+ switch (obj->variant_type) { -+ case YAFFS_OBJECT_TYPE_FILE: -+ yaffs_verify_file(obj); -+ break; -+ case YAFFS_OBJECT_TYPE_SYMLINK: -+ yaffs_verify_symlink(obj); -+ break; -+ case YAFFS_OBJECT_TYPE_DIRECTORY: -+ yaffs_verify_dir(obj); -+ break; -+ case YAFFS_OBJECT_TYPE_HARDLINK: -+ yaffs_verify_link(obj); -+ break; -+ case YAFFS_OBJECT_TYPE_SPECIAL: -+ yaffs_verify_special(obj); -+ break; -+ case YAFFS_OBJECT_TYPE_UNKNOWN: -+ default: -+ T(YAFFS_TRACE_VERIFY, -+ (TSTR("Obj %d has illegaltype %d" TENDSTR), -+ obj->obj_id, obj->variant_type)); -+ break; -+ } -+} -+ -+void yaffs_verify_objects(struct yaffs_dev *dev) -+{ -+ struct yaffs_obj *obj; -+ int i; -+ struct list_head *lh; -+ -+ if (yaffs_skip_verification(dev)) -+ return; -+ -+ /* Iterate through the objects in each hash entry */ -+ -+ for (i = 0; i < YAFFS_NOBJECT_BUCKETS; i++) { -+ list_for_each(lh, &dev->obj_bucket[i].list) { -+ if (lh) { -+ obj = -+ list_entry(lh, struct yaffs_obj, hash_link); -+ yaffs_verify_obj(obj); -+ } -+ } -+ } -+} -+ -+void yaffs_verify_obj_in_dir(struct yaffs_obj *obj) -+{ -+ struct list_head *lh; -+ struct yaffs_obj *list_obj; -+ -+ int count = 0; -+ -+ if (!obj) { -+ T(YAFFS_TRACE_ALWAYS, (TSTR("No object to verify" TENDSTR))); -+ YBUG(); -+ return; -+ } -+ -+ if (yaffs_skip_verification(obj->my_dev)) -+ return; -+ -+ if (!obj->parent) { -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR("Object does not have parent" TENDSTR))); -+ YBUG(); -+ return; -+ } -+ -+ if (obj->parent->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) { -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR("Parent is not directory" TENDSTR))); -+ YBUG(); -+ } -+ -+ /* Iterate through the objects in each hash entry */ -+ -+ list_for_each(lh, &obj->parent->variant.dir_variant.children) { -+ if (lh) { -+ list_obj = list_entry(lh, struct yaffs_obj, siblings); -+ yaffs_verify_obj(list_obj); -+ if (obj == list_obj) -+ count++; -+ } -+ } -+ -+ if (count != 1) { -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR("Object in directory %d times" TENDSTR), count)); -+ YBUG(); -+ } -+} -+ -+void yaffs_verify_dir(struct yaffs_obj *directory) -+{ -+ struct list_head *lh; -+ struct yaffs_obj *list_obj; -+ -+ if (!directory) { -+ YBUG(); -+ return; -+ } -+ -+ if (yaffs_skip_full_verification(directory->my_dev)) -+ return; -+ -+ if (directory->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) { -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR("Directory has wrong type: %d" TENDSTR), -+ directory->variant_type)); -+ YBUG(); -+ } -+ -+ /* Iterate through the objects in each hash entry */ -+ -+ list_for_each(lh, &directory->variant.dir_variant.children) { -+ if (lh) { -+ list_obj = list_entry(lh, struct yaffs_obj, siblings); -+ if (list_obj->parent != directory) { -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR -+ ("Object in directory list has wrong parent %p" -+ TENDSTR), list_obj->parent)); -+ YBUG(); -+ } -+ yaffs_verify_obj_in_dir(list_obj); -+ } -+ } -+} -+ -+static int yaffs_free_verification_failures; -+ -+void yaffs_verify_free_chunks(struct yaffs_dev *dev) -+{ -+ int counted; -+ int difference; -+ -+ if (yaffs_skip_verification(dev)) -+ return; -+ -+ counted = yaffs_count_free_chunks(dev); -+ -+ difference = dev->n_free_chunks - counted; -+ -+ if (difference) { -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR("Freechunks verification failure %d %d %d" TENDSTR), -+ dev->n_free_chunks, counted, difference)); -+ yaffs_free_verification_failures++; -+ } -+} -+ -+int yaffs_verify_file_sane(struct yaffs_obj *in) -+{ -+ in = in; -+ return YAFFS_OK; -+} -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_verify.h linux-2.6.36/fs/yaffs2/yaffs_verify.h ---- linux-2.6.36.orig/fs/yaffs2/yaffs_verify.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_verify.h 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,43 @@ -+/* -+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU Lesser General Public License version 2.1 as -+ * published by the Free Software Foundation. -+ * -+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. -+ */ -+ -+#ifndef __YAFFS_VERIFY_H__ -+#define __YAFFS_VERIFY_H__ -+ -+#include "yaffs_guts.h" -+ -+void yaffs_verify_blk(struct yaffs_dev *dev, struct yaffs_block_info *bi, -+ int n); -+void yaffs_verify_collected_blk(struct yaffs_dev *dev, -+ struct yaffs_block_info *bi, int n); -+void yaffs_verify_blocks(struct yaffs_dev *dev); -+ -+void yaffs_verify_oh(struct yaffs_obj *obj, struct yaffs_obj_hdr *oh, -+ struct yaffs_ext_tags *tags, int parent_check); -+void yaffs_verify_file(struct yaffs_obj *obj); -+void yaffs_verify_link(struct yaffs_obj *obj); -+void yaffs_verify_symlink(struct yaffs_obj *obj); -+void yaffs_verify_special(struct yaffs_obj *obj); -+void yaffs_verify_obj(struct yaffs_obj *obj); -+void yaffs_verify_objects(struct yaffs_dev *dev); -+void yaffs_verify_obj_in_dir(struct yaffs_obj *obj); -+void yaffs_verify_dir(struct yaffs_obj *directory); -+void yaffs_verify_free_chunks(struct yaffs_dev *dev); -+ -+int yaffs_verify_file_sane(struct yaffs_obj *obj); -+ -+int yaffs_skip_verification(struct yaffs_dev *dev); -+ -+#endif -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_vfs.c linux-2.6.36/fs/yaffs2/yaffs_vfs.c ---- linux-2.6.36.orig/fs/yaffs2/yaffs_vfs.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_vfs.c 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,3565 @@ -+/* -+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * Acknowledgements: -+ * Luc van OostenRyck for numerous patches. -+ * Nick Bane for numerous patches. -+ * Nick Bane for 2.5/2.6 integration. -+ * Andras Toth for mknod rdev issue. -+ * Michael Fischer for finding the problem with inode inconsistency. -+ * Some code bodily lifted from JFFS -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+/* -+ * -+ * This is the file system front-end to YAFFS that hooks it up to -+ * the VFS. -+ * -+ * Special notes: -+ * >> 2.4: sb->u.generic_sbp points to the struct yaffs_dev associated with -+ * this superblock -+ * >> 2.6: sb->s_fs_info points to the struct yaffs_dev associated with this -+ * superblock -+ * >> inode->u.generic_ip points to the associated struct yaffs_obj. -+ */ -+ -+/* -+ * There are two variants of the VFS glue code. This variant should compile -+ * for any version of Linux. -+ */ -+#include -+ -+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 10)) -+#define YAFFS_COMPILE_BACKGROUND -+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6, 23)) -+#define YAFFS_COMPILE_FREEZER -+#endif -+#endif -+ -+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)) -+#define YAFFS_COMPILE_EXPORTFS -+#endif -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)) -+#define YAFFS_USE_SETATTR_COPY -+#define YAFFS_USE_TRUNCATE_SETSIZE -+#endif -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)) -+#define YAFFS_HAS_EVICT_INODE -+#endif -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,13)) -+#define YAFFS_NEW_FOLLOW_LINK 1 -+#else -+#define YAFFS_NEW_FOLLOW_LINK 0 -+#endif -+ -+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19)) -+#include -+#endif -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#if (YAFFS_NEW_FOLLOW_LINK == 1) -+#include -+#endif -+ -+#ifdef YAFFS_COMPILE_EXPORTFS -+#include -+#endif -+ -+#ifdef YAFFS_COMPILE_BACKGROUND -+#include -+#include -+#endif -+#ifdef YAFFS_COMPILE_FREEZER -+#include -+#endif -+ -+#include -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) -+ -+#include -+ -+#define UnlockPage(p) unlock_page(p) -+#define Page_Uptodate(page) test_bit(PG_uptodate, &(page)->flags) -+ -+/* FIXME: use sb->s_id instead ? */ -+#define yaffs_devname(sb, buf) bdevname(sb->s_bdev, buf) -+ -+#else -+ -+#include -+#define BDEVNAME_SIZE 0 -+#define yaffs_devname(sb, buf) kdevname(sb->s_dev) -+ -+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 0)) -+/* added NCB 26/5/2006 for 2.4.25-vrs2-tcl1 kernel */ -+#define __user -+#endif -+ -+#endif -+ -+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 26)) -+#define YPROC_ROOT (&proc_root) -+#else -+#define YPROC_ROOT NULL -+#endif -+ -+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) -+#define Y_INIT_TIMER(a) init_timer(a) -+#else -+#define Y_INIT_TIMER(a) init_timer_on_stack(a) -+#endif -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17)) -+#define WRITE_SIZE_STR "writesize" -+#define WRITE_SIZE(mtd) ((mtd)->writesize) -+#else -+#define WRITE_SIZE_STR "oobblock" -+#define WRITE_SIZE(mtd) ((mtd)->oobblock) -+#endif -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 27)) -+#define YAFFS_USE_WRITE_BEGIN_END 1 -+#else -+#define YAFFS_USE_WRITE_BEGIN_END 0 -+#endif -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 28)) -+static uint32_t YCALCBLOCKS(uint64_t partition_size, uint32_t block_size) -+{ -+ uint64_t result = partition_size; -+ do_div(result, block_size); -+ return (uint32_t) result; -+} -+#else -+#define YCALCBLOCKS(s, b) ((s)/(b)) -+#endif -+ -+#include -+#include -+ -+#include "yportenv.h" -+#include "yaffs_trace.h" -+#include "yaffs_guts.h" -+#include "yaffs_attribs.h" -+ -+#include "yaffs_linux.h" -+ -+#include "yaffs_mtdif.h" -+#include "yaffs_mtdif1.h" -+#include "yaffs_mtdif2.h" -+ -+unsigned int yaffs_trace_mask = YAFFS_TRACE_BAD_BLOCKS | YAFFS_TRACE_ALWAYS; -+unsigned int yaffs_wr_attempts = YAFFS_WR_ATTEMPTS; -+unsigned int yaffs_auto_checkpoint = 1; -+unsigned int yaffs_gc_control = 1; -+unsigned int yaffs_bg_enable = 1; -+ -+/* Module Parameters */ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) -+module_param(yaffs_trace_mask, uint, 0644); -+module_param(yaffs_wr_attempts, uint, 0644); -+module_param(yaffs_auto_checkpoint, uint, 0644); -+module_param(yaffs_gc_control, uint, 0644); -+module_param(yaffs_bg_enable, uint, 0644); -+#else -+MODULE_PARM(yaffs_trace_mask, "i"); -+MODULE_PARM(yaffs_wr_attempts, "i"); -+MODULE_PARM(yaffs_auto_checkpoint, "i"); -+MODULE_PARM(yaffs_gc_control, "i"); -+#endif -+ -+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 25)) -+/* use iget and read_inode */ -+#define Y_IGET(sb, inum) iget((sb), (inum)) -+static void yaffs_read_inode(struct inode *inode); -+ -+#else -+/* Call local equivalent */ -+#define YAFFS_USE_OWN_IGET -+#define Y_IGET(sb, inum) yaffs_iget((sb), (inum)) -+ -+static struct inode *yaffs_iget(struct super_block *sb, unsigned long ino); -+#endif -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 18)) -+#define yaffs_inode_to_obj_lv(iptr) ((iptr)->i_private) -+#else -+#define yaffs_inode_to_obj_lv(iptr) ((iptr)->u.generic_ip) -+#endif -+ -+#define yaffs_inode_to_obj(iptr) ((struct yaffs_obj *)(yaffs_inode_to_obj_lv(iptr))) -+#define yaffs_dentry_to_obj(dptr) yaffs_inode_to_obj((dptr)->d_inode) -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) -+#define yaffs_super_to_dev(sb) ((struct yaffs_dev *)sb->s_fs_info) -+#else -+#define yaffs_super_to_dev(sb) ((struct yaffs_dev *)sb->u.generic_sbp) -+#endif -+ -+#define update_dir_time(dir) do {\ -+ (dir)->i_ctime = (dir)->i_mtime = CURRENT_TIME; \ -+ } while(0) -+ -+static void yaffs_put_super(struct super_block *sb); -+ -+static ssize_t yaffs_file_write(struct file *f, const char *buf, size_t n, -+ loff_t * pos); -+static ssize_t yaffs_hold_space(struct file *f); -+static void yaffs_release_space(struct file *f); -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17)) -+static int yaffs_file_flush(struct file *file, fl_owner_t id); -+#else -+static int yaffs_file_flush(struct file *file); -+#endif -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 34)) -+static int yaffs_sync_object(struct file *file, int datasync); -+#else -+static int yaffs_sync_object(struct file *file, struct dentry *dentry, -+ int datasync); -+#endif -+ -+static int yaffs_readdir(struct file *f, void *dirent, filldir_t filldir); -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) -+static int yaffs_create(struct inode *dir, struct dentry *dentry, int mode, -+ struct nameidata *n); -+static struct dentry *yaffs_lookup(struct inode *dir, struct dentry *dentry, -+ struct nameidata *n); -+#else -+static int yaffs_create(struct inode *dir, struct dentry *dentry, int mode); -+static struct dentry *yaffs_lookup(struct inode *dir, struct dentry *dentry); -+#endif -+static int yaffs_link(struct dentry *old_dentry, struct inode *dir, -+ struct dentry *dentry); -+static int yaffs_unlink(struct inode *dir, struct dentry *dentry); -+static int yaffs_symlink(struct inode *dir, struct dentry *dentry, -+ const char *symname); -+static int yaffs_mkdir(struct inode *dir, struct dentry *dentry, int mode); -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) -+static int yaffs_mknod(struct inode *dir, struct dentry *dentry, int mode, -+ dev_t dev); -+#else -+static int yaffs_mknod(struct inode *dir, struct dentry *dentry, int mode, -+ int dev); -+#endif -+static int yaffs_rename(struct inode *old_dir, struct dentry *old_dentry, -+ struct inode *new_dir, struct dentry *new_dentry); -+static int yaffs_setattr(struct dentry *dentry, struct iattr *attr); -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17)) -+static int yaffs_sync_fs(struct super_block *sb, int wait); -+static void yaffs_write_super(struct super_block *sb); -+#else -+static int yaffs_sync_fs(struct super_block *sb); -+static int yaffs_write_super(struct super_block *sb); -+#endif -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17)) -+static int yaffs_statfs(struct dentry *dentry, struct kstatfs *buf); -+#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) -+static int yaffs_statfs(struct super_block *sb, struct kstatfs *buf); -+#else -+static int yaffs_statfs(struct super_block *sb, struct statfs *buf); -+#endif -+ -+#ifdef YAFFS_HAS_PUT_INODE -+static void yaffs_put_inode(struct inode *inode); -+#endif -+ -+#ifdef YAFFS_HAS_EVICT_INODE -+static void yaffs_evict_inode(struct inode *); -+#else -+static void yaffs_delete_inode(struct inode *); -+static void yaffs_clear_inode(struct inode *); -+#endif -+ -+static int yaffs_readpage(struct file *file, struct page *page); -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) -+static int yaffs_writepage(struct page *page, struct writeback_control *wbc); -+#else -+static int yaffs_writepage(struct page *page); -+#endif -+ -+#ifdef CONFIG_YAFFS_XATTR -+int yaffs_setxattr(struct dentry *dentry, const char *name, -+ const void *value, size_t size, int flags); -+ssize_t yaffs_getxattr(struct dentry *dentry, const char *name, void *buff, -+ size_t size); -+int yaffs_removexattr(struct dentry *dentry, const char *name); -+ssize_t yaffs_listxattr(struct dentry *dentry, char *buff, size_t size); -+#endif -+ -+#if (YAFFS_USE_WRITE_BEGIN_END != 0) -+static int yaffs_write_begin(struct file *filp, struct address_space *mapping, -+ loff_t pos, unsigned len, unsigned flags, -+ struct page **pagep, void **fsdata); -+static int yaffs_write_end(struct file *filp, struct address_space *mapping, -+ loff_t pos, unsigned len, unsigned copied, -+ struct page *pg, void *fsdadata); -+#else -+static int yaffs_prepare_write(struct file *f, struct page *pg, -+ unsigned offset, unsigned to); -+static int yaffs_commit_write(struct file *f, struct page *pg, unsigned offset, -+ unsigned to); -+ -+#endif -+ -+static int yaffs_readlink(struct dentry *dentry, char __user * buffer, -+ int buflen); -+#if (YAFFS_NEW_FOLLOW_LINK == 1) -+void yaffs_put_link(struct dentry *dentry, struct nameidata *nd, void *alias); -+static void *yaffs_follow_link(struct dentry *dentry, struct nameidata *nd); -+#else -+static int yaffs_follow_link(struct dentry *dentry, struct nameidata *nd); -+#endif -+ -+static void yaffs_touch_super(struct yaffs_dev *dev); -+ -+static loff_t yaffs_dir_llseek(struct file *file, loff_t offset, int origin); -+ -+static int yaffs_vfs_setattr(struct inode *, struct iattr *); -+ -+static struct address_space_operations yaffs_file_address_operations = { -+ .readpage = yaffs_readpage, -+ .writepage = yaffs_writepage, -+#if (YAFFS_USE_WRITE_BEGIN_END > 0) -+ .write_begin = yaffs_write_begin, -+ .write_end = yaffs_write_end, -+#else -+ .prepare_write = yaffs_prepare_write, -+ .commit_write = yaffs_commit_write, -+#endif -+}; -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 22)) -+static const struct file_operations yaffs_file_operations = { -+ .read = do_sync_read, -+ .write = do_sync_write, -+ .aio_read = generic_file_aio_read, -+ .aio_write = generic_file_aio_write, -+ .mmap = generic_file_mmap, -+ .flush = yaffs_file_flush, -+ .fsync = yaffs_sync_object, -+ .splice_read = generic_file_splice_read, -+ .splice_write = generic_file_splice_write, -+ .llseek = generic_file_llseek, -+}; -+ -+#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 18)) -+ -+static const struct file_operations yaffs_file_operations = { -+ .read = do_sync_read, -+ .write = do_sync_write, -+ .aio_read = generic_file_aio_read, -+ .aio_write = generic_file_aio_write, -+ .mmap = generic_file_mmap, -+ .flush = yaffs_file_flush, -+ .fsync = yaffs_sync_object, -+ .sendfile = generic_file_sendfile, -+}; -+ -+#else -+ -+static const struct file_operations yaffs_file_operations = { -+ .read = generic_file_read, -+ .write = generic_file_write, -+ .mmap = generic_file_mmap, -+ .flush = yaffs_file_flush, -+ .fsync = yaffs_sync_object, -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) -+ .sendfile = generic_file_sendfile, -+#endif -+}; -+#endif -+ -+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)) -+static void zero_user_segment(struct page *page, unsigned start, unsigned end) -+{ -+ void *kaddr = kmap_atomic(page, KM_USER0); -+ memset(kaddr + start, 0, end - start); -+ kunmap_atomic(kaddr, KM_USER0); -+ flush_dcache_page(page); -+} -+#endif -+ -+static const struct inode_operations yaffs_file_inode_operations = { -+ .setattr = yaffs_setattr, -+#ifdef CONFIG_YAFFS_XATTR -+ .setxattr = yaffs_setxattr, -+ .getxattr = yaffs_getxattr, -+ .listxattr = yaffs_listxattr, -+ .removexattr = yaffs_removexattr, -+#endif -+}; -+ -+static const struct inode_operations yaffs_symlink_inode_operations = { -+ .readlink = yaffs_readlink, -+ .follow_link = yaffs_follow_link, -+#if (YAFFS_NEW_FOLLOW_LINK == 1) -+ .put_link = yaffs_put_link, -+#endif -+ .setattr = yaffs_setattr, -+#ifdef CONFIG_YAFFS_XATTR -+ .setxattr = yaffs_setxattr, -+ .getxattr = yaffs_getxattr, -+ .listxattr = yaffs_listxattr, -+ .removexattr = yaffs_removexattr, -+#endif -+}; -+ -+static const struct inode_operations yaffs_dir_inode_operations = { -+ .create = yaffs_create, -+ .lookup = yaffs_lookup, -+ .link = yaffs_link, -+ .unlink = yaffs_unlink, -+ .symlink = yaffs_symlink, -+ .mkdir = yaffs_mkdir, -+ .rmdir = yaffs_unlink, -+ .mknod = yaffs_mknod, -+ .rename = yaffs_rename, -+ .setattr = yaffs_setattr, -+#ifdef CONFIG_YAFFS_XATTR -+ .setxattr = yaffs_setxattr, -+ .getxattr = yaffs_getxattr, -+ .listxattr = yaffs_listxattr, -+ .removexattr = yaffs_removexattr, -+#endif -+}; -+ -+static const struct file_operations yaffs_dir_operations = { -+ .read = generic_read_dir, -+ .readdir = yaffs_readdir, -+ .fsync = yaffs_sync_object, -+ .llseek = yaffs_dir_llseek, -+}; -+ -+static const struct super_operations yaffs_super_ops = { -+ .statfs = yaffs_statfs, -+ -+#ifndef YAFFS_USE_OWN_IGET -+ .read_inode = yaffs_read_inode, -+#endif -+#ifdef YAFFS_HAS_PUT_INODE -+ .put_inode = yaffs_put_inode, -+#endif -+ .put_super = yaffs_put_super, -+#ifdef YAFFS_HAS_EVICT_INODE -+ .evict_inode = yaffs_evict_inode, -+#else -+ .delete_inode = yaffs_delete_inode, -+ .clear_inode = yaffs_clear_inode, -+#endif -+ .sync_fs = yaffs_sync_fs, -+ .write_super = yaffs_write_super, -+}; -+ -+static int yaffs_vfs_setattr(struct inode *inode, struct iattr *attr) -+{ -+#ifdef YAFFS_USE_SETATTR_COPY -+ setattr_copy(inode, attr); -+ return 0; -+#else -+ return inode_setattr(inode, attr); -+#endif -+ -+} -+ -+static int yaffs_vfs_setsize(struct inode *inode, loff_t newsize) -+{ -+#ifdef YAFFS_USE_TRUNCATE_SETSIZE -+ truncate_setsize(inode, newsize); -+ return 0; -+#else -+ truncate_inode_pages(&inode->i_data, newsize); -+ return 0; -+#endif -+ -+} -+ -+static unsigned yaffs_gc_control_callback(struct yaffs_dev *dev) -+{ -+ return yaffs_gc_control; -+} -+ -+static void yaffs_gross_lock(struct yaffs_dev *dev) -+{ -+ T(YAFFS_TRACE_LOCK, (TSTR("yaffs locking %p\n"), current)); -+ mutex_lock(&(yaffs_dev_to_lc(dev)->gross_lock)); -+ T(YAFFS_TRACE_LOCK, (TSTR("yaffs locked %p\n"), current)); -+} -+ -+static void yaffs_gross_unlock(struct yaffs_dev *dev) -+{ -+ T(YAFFS_TRACE_LOCK, (TSTR("yaffs unlocking %p\n"), current)); -+ mutex_unlock(&(yaffs_dev_to_lc(dev)->gross_lock)); -+} -+ -+#ifdef YAFFS_COMPILE_EXPORTFS -+ -+static struct inode *yaffs2_nfs_get_inode(struct super_block *sb, uint64_t ino, -+ uint32_t generation) -+{ -+ return Y_IGET(sb, ino); -+} -+ -+static struct dentry *yaffs2_fh_to_dentry(struct super_block *sb, -+ struct fid *fid, int fh_len, -+ int fh_type) -+{ -+ return generic_fh_to_dentry(sb, fid, fh_len, fh_type, -+ yaffs2_nfs_get_inode); -+} -+ -+static struct dentry *yaffs2_fh_to_parent(struct super_block *sb, -+ struct fid *fid, int fh_len, -+ int fh_type) -+{ -+ return generic_fh_to_parent(sb, fid, fh_len, fh_type, -+ yaffs2_nfs_get_inode); -+} -+ -+struct dentry *yaffs2_get_parent(struct dentry *dentry) -+{ -+ -+ struct super_block *sb = dentry->d_inode->i_sb; -+ struct dentry *parent = ERR_PTR(-ENOENT); -+ struct inode *inode; -+ unsigned long parent_ino; -+ struct yaffs_obj *d_obj; -+ struct yaffs_obj *parent_obj; -+ -+ d_obj = yaffs_inode_to_obj(dentry->d_inode); -+ -+ if (d_obj) { -+ parent_obj = d_obj->parent; -+ if (parent_obj) { -+ parent_ino = yaffs_get_obj_inode(parent_obj); -+ inode = Y_IGET(sb, parent_ino); -+ -+ if (IS_ERR(inode)) { -+ parent = ERR_CAST(inode); -+ } else { -+ parent = d_obtain_alias(inode); -+ if (!IS_ERR(parent)) { -+ parent = ERR_PTR(-ENOMEM); -+ iput(inode); -+ } -+ } -+ } -+ } -+ -+ return parent; -+} -+ -+/* Just declare a zero structure as a NULL value implies -+ * using the default functions of exportfs. -+ */ -+ -+static struct export_operations yaffs_export_ops = { -+ .fh_to_dentry = yaffs2_fh_to_dentry, -+ .fh_to_parent = yaffs2_fh_to_parent, -+ .get_parent = yaffs2_get_parent, -+}; -+ -+#endif -+ -+/*-----------------------------------------------------------------*/ -+/* Directory search context allows us to unlock access to yaffs during -+ * filldir without causing problems with the directory being modified. -+ * This is similar to the tried and tested mechanism used in yaffs direct. -+ * -+ * A search context iterates along a doubly linked list of siblings in the -+ * directory. If the iterating object is deleted then this would corrupt -+ * the list iteration, likely causing a crash. The search context avoids -+ * this by using the remove_obj_fn to move the search context to the -+ * next object before the object is deleted. -+ * -+ * Many readdirs (and thus seach conexts) may be alive simulateously so -+ * each struct yaffs_dev has a list of these. -+ * -+ * A seach context lives for the duration of a readdir. -+ * -+ * All these functions must be called while yaffs is locked. -+ */ -+ -+struct yaffs_search_context { -+ struct yaffs_dev *dev; -+ struct yaffs_obj *dir_obj; -+ struct yaffs_obj *next_return; -+ struct list_head others; -+}; -+ -+/* -+ * yaffs_new_search() creates a new search context, initialises it and -+ * adds it to the device's search context list. -+ * -+ * Called at start of readdir. -+ */ -+static struct yaffs_search_context *yaffs_new_search(struct yaffs_obj *dir) -+{ -+ struct yaffs_dev *dev = dir->my_dev; -+ struct yaffs_search_context *sc = -+ YMALLOC(sizeof(struct yaffs_search_context)); -+ if (sc) { -+ sc->dir_obj = dir; -+ sc->dev = dev; -+ if (list_empty(&sc->dir_obj->variant.dir_variant.children)) -+ sc->next_return = NULL; -+ else -+ sc->next_return = -+ list_entry(dir->variant.dir_variant.children.next, -+ struct yaffs_obj, siblings); -+ INIT_LIST_HEAD(&sc->others); -+ list_add(&sc->others, &(yaffs_dev_to_lc(dev)->search_contexts)); -+ } -+ return sc; -+} -+ -+/* -+ * yaffs_search_end() disposes of a search context and cleans up. -+ */ -+static void yaffs_search_end(struct yaffs_search_context *sc) -+{ -+ if (sc) { -+ list_del(&sc->others); -+ YFREE(sc); -+ } -+} -+ -+/* -+ * yaffs_search_advance() moves a search context to the next object. -+ * Called when the search iterates or when an object removal causes -+ * the search context to be moved to the next object. -+ */ -+static void yaffs_search_advance(struct yaffs_search_context *sc) -+{ -+ if (!sc) -+ return; -+ -+ if (sc->next_return == NULL || -+ list_empty(&sc->dir_obj->variant.dir_variant.children)) -+ sc->next_return = NULL; -+ else { -+ struct list_head *next = sc->next_return->siblings.next; -+ -+ if (next == &sc->dir_obj->variant.dir_variant.children) -+ sc->next_return = NULL; /* end of list */ -+ else -+ sc->next_return = -+ list_entry(next, struct yaffs_obj, siblings); -+ } -+} -+ -+/* -+ * yaffs_remove_obj_callback() is called when an object is unlinked. -+ * We check open search contexts and advance any which are currently -+ * on the object being iterated. -+ */ -+static void yaffs_remove_obj_callback(struct yaffs_obj *obj) -+{ -+ -+ struct list_head *i; -+ struct yaffs_search_context *sc; -+ struct list_head *search_contexts = -+ &(yaffs_dev_to_lc(obj->my_dev)->search_contexts); -+ -+ /* Iterate through the directory search contexts. -+ * If any are currently on the object being removed, then advance -+ * the search context to the next object to prevent a hanging pointer. -+ */ -+ list_for_each(i, search_contexts) { -+ if (i) { -+ sc = list_entry(i, struct yaffs_search_context, others); -+ if (sc->next_return == obj) -+ yaffs_search_advance(sc); -+ } -+ } -+ -+} -+ -+/*-----------------------------------------------------------------*/ -+ -+static int yaffs_readlink(struct dentry *dentry, char __user * buffer, -+ int buflen) -+{ -+ unsigned char *alias; -+ int ret; -+ -+ struct yaffs_dev *dev = yaffs_dentry_to_obj(dentry)->my_dev; -+ -+ yaffs_gross_lock(dev); -+ -+ alias = yaffs_get_symlink_alias(yaffs_dentry_to_obj(dentry)); -+ -+ yaffs_gross_unlock(dev); -+ -+ if (!alias) -+ return -ENOMEM; -+ -+ ret = vfs_readlink(dentry, buffer, buflen, alias); -+ kfree(alias); -+ return ret; -+} -+ -+#if (YAFFS_NEW_FOLLOW_LINK == 1) -+static void *yaffs_follow_link(struct dentry *dentry, struct nameidata *nd) -+{ -+ void *ret; -+#else -+static int yaffs_follow_link(struct dentry *dentry, struct nameidata *nd) -+{ -+ int ret -+#endif -+ unsigned char *alias; -+ int ret_int = 0; -+ struct yaffs_dev *dev = yaffs_dentry_to_obj(dentry)->my_dev; -+ -+ yaffs_gross_lock(dev); -+ -+ alias = yaffs_get_symlink_alias(yaffs_dentry_to_obj(dentry)); -+ yaffs_gross_unlock(dev); -+ -+ if (!alias) { -+ ret_int = -ENOMEM; -+ goto out; -+ } -+#if (YAFFS_NEW_FOLLOW_LINK == 1) -+ nd_set_link(nd, alias); -+ ret = alias; -+out: -+ if (ret_int) -+ ret = ERR_PTR(ret_int); -+ return ret; -+#else -+ ret = vfs_follow_link(nd, alias); -+ kfree(alias); -+out: -+ if (ret_int) -+ ret = ret_int; -+ return ret; -+#endif -+} -+ -+#if (YAFFS_NEW_FOLLOW_LINK == 1) -+void yaffs_put_link(struct dentry *dentry, struct nameidata *nd, void *alias) -+{ -+ kfree(alias); -+} -+#endif -+ -+struct inode *yaffs_get_inode(struct super_block *sb, int mode, int dev, -+ struct yaffs_obj *obj); -+ -+/* -+ * Lookup is used to find objects in the fs -+ */ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) -+ -+static struct dentry *yaffs_lookup(struct inode *dir, struct dentry *dentry, -+ struct nameidata *n) -+#else -+static struct dentry *yaffs_lookup(struct inode *dir, struct dentry *dentry) -+#endif -+{ -+ struct yaffs_obj *obj; -+ struct inode *inode = NULL; /* NCB 2.5/2.6 needs NULL here */ -+ -+ struct yaffs_dev *dev = yaffs_inode_to_obj(dir)->my_dev; -+ -+ if (current != yaffs_dev_to_lc(dev)->readdir_process) -+ yaffs_gross_lock(dev); -+ -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_lookup for %d:%s\n"), -+ yaffs_inode_to_obj(dir)->obj_id, dentry->d_name.name)); -+ -+ obj = yaffs_find_by_name(yaffs_inode_to_obj(dir), dentry->d_name.name); -+ -+ obj = yaffs_get_equivalent_obj(obj); /* in case it was a hardlink */ -+ -+ /* Can't hold gross lock when calling yaffs_get_inode() */ -+ if (current != yaffs_dev_to_lc(dev)->readdir_process) -+ yaffs_gross_unlock(dev); -+ -+ if (obj) { -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_lookup found %d\n"), obj->obj_id)); -+ -+ inode = yaffs_get_inode(dir->i_sb, obj->yst_mode, 0, obj); -+ -+ if (inode) { -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_loookup dentry \n"))); -+/* #if 0 asserted by NCB for 2.5/6 compatability - falls through to -+ * d_add even if NULL inode */ -+#if 0 -+ /*dget(dentry); // try to solve directory bug */ -+ d_add(dentry, inode); -+ -+ /* return dentry; */ -+ return NULL; -+#endif -+ } -+ -+ } else { -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_lookup not found\n"))); -+ -+ } -+ -+/* added NCB for 2.5/6 compatability - forces add even if inode is -+ * NULL which creates dentry hash */ -+ d_add(dentry, inode); -+ -+ return NULL; -+} -+ -+#ifdef YAFFS_HAS_PUT_INODE -+ -+/* For now put inode is just for debugging -+ * Put inode is called when the inode **structure** is put. -+ */ -+static void yaffs_put_inode(struct inode *inode) -+{ -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_put_inode: ino %d, count %d\n"), (int)inode->i_ino, -+ atomic_read(&inode->i_count))); -+ -+} -+#endif -+ -+static void yaffs_unstitch_obj(struct inode *inode, struct yaffs_obj *obj) -+{ -+ /* Clear the association between the inode and -+ * the struct yaffs_obj. -+ */ -+ obj->my_inode = NULL; -+ yaffs_inode_to_obj_lv(inode) = NULL; -+ -+ /* If the object freeing was deferred, then the real -+ * free happens now. -+ * This should fix the inode inconsistency problem. -+ */ -+ yaffs_handle_defered_free(obj); -+} -+ -+#ifdef YAFFS_HAS_EVICT_INODE -+/* yaffs_evict_inode combines into one operation what was previously done in -+ * yaffs_clear_inode() and yaffs_delete_inode() -+ * -+ */ -+static void yaffs_evict_inode(struct inode *inode) -+{ -+ struct yaffs_obj *obj; -+ struct yaffs_dev *dev; -+ int deleteme = 0; -+ -+ obj = yaffs_inode_to_obj(inode); -+ -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_evict_inode: ino %d, count %d %s\n"), (int)inode->i_ino, -+ atomic_read(&inode->i_count), -+ obj ? "object exists" : "null object")); -+ -+ if (!inode->i_nlink && !is_bad_inode(inode)) -+ deleteme = 1; -+ truncate_inode_pages(&inode->i_data, 0); -+ end_writeback(inode); -+ -+ if (deleteme && obj) { -+ dev = obj->my_dev; -+ yaffs_gross_lock(dev); -+ yaffs_del_obj(obj); -+ yaffs_gross_unlock(dev); -+ } -+ if (obj) { -+ dev = obj->my_dev; -+ yaffs_gross_lock(dev); -+ yaffs_unstitch_obj(inode, obj); -+ yaffs_gross_unlock(dev); -+ } -+ -+} -+#else -+ -+/* clear is called to tell the fs to release any per-inode data it holds. -+ * The object might still exist on disk and is just being thrown out of the cache -+ * or else the object has actually been deleted and we're being called via -+ * the chain -+ * yaffs_delete_inode() -> clear_inode()->yaffs_clear_inode() -+ */ -+ -+static void yaffs_clear_inode(struct inode *inode) -+{ -+ struct yaffs_obj *obj; -+ struct yaffs_dev *dev; -+ -+ obj = yaffs_inode_to_obj(inode); -+ -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_clear_inode: ino %d, count %d %s\n"), (int)inode->i_ino, -+ atomic_read(&inode->i_count), -+ obj ? "object exists" : "null object")); -+ -+ if (obj) { -+ dev = obj->my_dev; -+ yaffs_gross_lock(dev); -+ yaffs_unstitch_obj(inode, obj); -+ yaffs_gross_unlock(dev); -+ } -+ -+} -+ -+/* delete is called when the link count is zero and the inode -+ * is put (ie. nobody wants to know about it anymore, time to -+ * delete the file). -+ * NB Must call clear_inode() -+ */ -+static void yaffs_delete_inode(struct inode *inode) -+{ -+ struct yaffs_obj *obj = yaffs_inode_to_obj(inode); -+ struct yaffs_dev *dev; -+ -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_delete_inode: ino %d, count %d %s\n"), (int)inode->i_ino, -+ atomic_read(&inode->i_count), -+ obj ? "object exists" : "null object")); -+ -+ if (obj) { -+ dev = obj->my_dev; -+ yaffs_gross_lock(dev); -+ yaffs_del_obj(obj); -+ yaffs_gross_unlock(dev); -+ } -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 13)) -+ truncate_inode_pages(&inode->i_data, 0); -+#endif -+ clear_inode(inode); -+} -+#endif -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17)) -+static int yaffs_file_flush(struct file *file, fl_owner_t id) -+#else -+static int yaffs_file_flush(struct file *file) -+#endif -+{ -+ struct yaffs_obj *obj = yaffs_dentry_to_obj(file->f_dentry); -+ -+ struct yaffs_dev *dev = obj->my_dev; -+ -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_file_flush object %d (%s)\n"), obj->obj_id, -+ obj->dirty ? "dirty" : "clean")); -+ -+ yaffs_gross_lock(dev); -+ -+ yaffs_flush_file(obj, 1, 0); -+ -+ yaffs_gross_unlock(dev); -+ -+ return 0; -+} -+ -+static int yaffs_readpage_nolock(struct file *f, struct page *pg) -+{ -+ /* Lifted from jffs2 */ -+ -+ struct yaffs_obj *obj; -+ unsigned char *pg_buf; -+ int ret; -+ -+ struct yaffs_dev *dev; -+ -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_readpage_nolock at %08x, size %08x\n"), -+ (unsigned)(pg->index << PAGE_CACHE_SHIFT), -+ (unsigned)PAGE_CACHE_SIZE)); -+ -+ obj = yaffs_dentry_to_obj(f->f_dentry); -+ -+ dev = obj->my_dev; -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) -+ BUG_ON(!PageLocked(pg)); -+#else -+ if (!PageLocked(pg)) -+ PAGE_BUG(pg); -+#endif -+ -+ pg_buf = kmap(pg); -+ /* FIXME: Can kmap fail? */ -+ -+ yaffs_gross_lock(dev); -+ -+ ret = yaffs_file_rd(obj, pg_buf, -+ pg->index << PAGE_CACHE_SHIFT, PAGE_CACHE_SIZE); -+ -+ yaffs_gross_unlock(dev); -+ -+ if (ret >= 0) -+ ret = 0; -+ -+ if (ret) { -+ ClearPageUptodate(pg); -+ SetPageError(pg); -+ } else { -+ SetPageUptodate(pg); -+ ClearPageError(pg); -+ } -+ -+ flush_dcache_page(pg); -+ kunmap(pg); -+ -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_readpage_nolock done\n"))); -+ return ret; -+} -+ -+static int yaffs_readpage_unlock(struct file *f, struct page *pg) -+{ -+ int ret = yaffs_readpage_nolock(f, pg); -+ UnlockPage(pg); -+ return ret; -+} -+ -+static int yaffs_readpage(struct file *f, struct page *pg) -+{ -+ int ret; -+ -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_readpage\n"))); -+ ret = yaffs_readpage_unlock(f, pg); -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_readpage done\n"))); -+ return ret; -+} -+ -+/* writepage inspired by/stolen from smbfs */ -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) -+static int yaffs_writepage(struct page *page, struct writeback_control *wbc) -+#else -+static int yaffs_writepage(struct page *page) -+#endif -+{ -+ struct yaffs_dev *dev; -+ struct address_space *mapping = page->mapping; -+ struct inode *inode; -+ unsigned long end_index; -+ char *buffer; -+ struct yaffs_obj *obj; -+ int n_written = 0; -+ unsigned n_bytes; -+ loff_t i_size; -+ -+ if (!mapping) -+ BUG(); -+ inode = mapping->host; -+ if (!inode) -+ BUG(); -+ i_size = i_size_read(inode); -+ -+ end_index = i_size >> PAGE_CACHE_SHIFT; -+ -+ if (page->index < end_index) -+ n_bytes = PAGE_CACHE_SIZE; -+ else { -+ n_bytes = i_size & (PAGE_CACHE_SIZE - 1); -+ -+ if (page->index > end_index || !n_bytes) { -+ T(YAFFS_TRACE_OS, -+ (TSTR -+ ("yaffs_writepage at %08x, inode size = %08x!!!\n"), -+ (unsigned)(page->index << PAGE_CACHE_SHIFT), -+ (unsigned)inode->i_size)); -+ T(YAFFS_TRACE_OS, -+ (TSTR(" -> don't care!!\n"))); -+ -+ zero_user_segment(page, 0, PAGE_CACHE_SIZE); -+ set_page_writeback(page); -+ unlock_page(page); -+ end_page_writeback(page); -+ return 0; -+ } -+ } -+ -+ if (n_bytes != PAGE_CACHE_SIZE) -+ zero_user_segment(page, n_bytes, PAGE_CACHE_SIZE); -+ -+ get_page(page); -+ -+ buffer = kmap(page); -+ -+ obj = yaffs_inode_to_obj(inode); -+ dev = obj->my_dev; -+ yaffs_gross_lock(dev); -+ -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_writepage at %08x, size %08x\n"), -+ (unsigned)(page->index << PAGE_CACHE_SHIFT), n_bytes)); -+ T(YAFFS_TRACE_OS, -+ (TSTR("writepag0: obj = %05x, ino = %05x\n"), -+ (int)obj->variant.file_variant.file_size, (int)inode->i_size)); -+ -+ n_written = yaffs_wr_file(obj, buffer, -+ page->index << PAGE_CACHE_SHIFT, n_bytes, 0); -+ -+ yaffs_touch_super(dev); -+ -+ T(YAFFS_TRACE_OS, -+ (TSTR("writepag1: obj = %05x, ino = %05x\n"), -+ (int)obj->variant.file_variant.file_size, (int)inode->i_size)); -+ -+ yaffs_gross_unlock(dev); -+ -+ kunmap(page); -+ set_page_writeback(page); -+ unlock_page(page); -+ end_page_writeback(page); -+ put_page(page); -+ -+ return (n_written == n_bytes) ? 0 : -ENOSPC; -+} -+ -+#if (YAFFS_USE_WRITE_BEGIN_END > 0) -+static int yaffs_write_begin(struct file *filp, struct address_space *mapping, -+ loff_t pos, unsigned len, unsigned flags, -+ struct page **pagep, void **fsdata) -+{ -+ struct page *pg = NULL; -+ pgoff_t index = pos >> PAGE_CACHE_SHIFT; -+ -+ int ret = 0; -+ int space_held = 0; -+ -+ /* Get a page */ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 28) -+ pg = grab_cache_page_write_begin(mapping, index, flags); -+#else -+ pg = __grab_cache_page(mapping, index); -+#endif -+ -+ *pagep = pg; -+ if (!pg) { -+ ret = -ENOMEM; -+ goto out; -+ } -+ T(YAFFS_TRACE_OS, -+ (TSTR("start yaffs_write_begin index %d(%x) uptodate %d\n"), -+ (int)index, (int)index, Page_Uptodate(pg) ? 1 : 0)); -+ -+ /* Get fs space */ -+ space_held = yaffs_hold_space(filp); -+ -+ if (!space_held) { -+ ret = -ENOSPC; -+ goto out; -+ } -+ -+ /* Update page if required */ -+ -+ if (!Page_Uptodate(pg)) -+ ret = yaffs_readpage_nolock(filp, pg); -+ -+ if (ret) -+ goto out; -+ -+ /* Happy path return */ -+ T(YAFFS_TRACE_OS, (TSTR("end yaffs_write_begin - ok\n"))); -+ -+ return 0; -+ -+out: -+ T(YAFFS_TRACE_OS, -+ (TSTR("end yaffs_write_begin fail returning %d\n"), ret)); -+ if (space_held) -+ yaffs_release_space(filp); -+ if (pg) { -+ unlock_page(pg); -+ page_cache_release(pg); -+ } -+ return ret; -+} -+ -+#else -+ -+static int yaffs_prepare_write(struct file *f, struct page *pg, -+ unsigned offset, unsigned to) -+{ -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_prepair_write\n"))); -+ -+ if (!Page_Uptodate(pg)) -+ return yaffs_readpage_nolock(f, pg); -+ return 0; -+} -+#endif -+ -+#if (YAFFS_USE_WRITE_BEGIN_END > 0) -+static int yaffs_write_end(struct file *filp, struct address_space *mapping, -+ loff_t pos, unsigned len, unsigned copied, -+ struct page *pg, void *fsdadata) -+{ -+ int ret = 0; -+ void *addr, *kva; -+ uint32_t offset_into_page = pos & (PAGE_CACHE_SIZE - 1); -+ -+ kva = kmap(pg); -+ addr = kva + offset_into_page; -+ -+ T(YAFFS_TRACE_OS, -+ ("yaffs_write_end addr %p pos %x n_bytes %d\n", -+ addr, (unsigned)pos, copied)); -+ -+ ret = yaffs_file_write(filp, addr, copied, &pos); -+ -+ if (ret != copied) { -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_write_end not same size ret %d copied %d\n"), -+ ret, copied)); -+ SetPageError(pg); -+ } else { -+ /* Nothing */ -+ } -+ -+ kunmap(pg); -+ -+ yaffs_release_space(filp); -+ unlock_page(pg); -+ page_cache_release(pg); -+ return ret; -+} -+#else -+ -+static int yaffs_commit_write(struct file *f, struct page *pg, unsigned offset, -+ unsigned to) -+{ -+ void *addr, *kva; -+ -+ loff_t pos = (((loff_t) pg->index) << PAGE_CACHE_SHIFT) + offset; -+ int n_bytes = to - offset; -+ int n_written; -+ -+ unsigned spos = pos; -+ unsigned saddr; -+ -+ kva = kmap(pg); -+ addr = kva + offset; -+ -+ saddr = (unsigned)addr; -+ -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_commit_write addr %x pos %x n_bytes %d\n"), -+ saddr, spos, n_bytes)); -+ -+ n_written = yaffs_file_write(f, addr, n_bytes, &pos); -+ -+ if (n_written != n_bytes) { -+ T(YAFFS_TRACE_OS, -+ (TSTR -+ ("yaffs_commit_write not same size n_written %d n_bytes %d\n"), -+ n_written, n_bytes)); -+ SetPageError(pg); -+ } else { -+ /* Nothing */ -+ } -+ -+ kunmap(pg); -+ -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_commit_write returning %d\n"), -+ n_written == n_bytes ? 0 : n_written)); -+ -+ return n_written == n_bytes ? 0 : n_written; -+} -+#endif -+ -+static void yaffs_fill_inode_from_obj(struct inode *inode, -+ struct yaffs_obj *obj) -+{ -+ if (inode && obj) { -+ -+ /* Check mode against the variant type and attempt to repair if broken. */ -+ u32 mode = obj->yst_mode; -+ switch (obj->variant_type) { -+ case YAFFS_OBJECT_TYPE_FILE: -+ if (!S_ISREG(mode)) { -+ obj->yst_mode &= ~S_IFMT; -+ obj->yst_mode |= S_IFREG; -+ } -+ -+ break; -+ case YAFFS_OBJECT_TYPE_SYMLINK: -+ if (!S_ISLNK(mode)) { -+ obj->yst_mode &= ~S_IFMT; -+ obj->yst_mode |= S_IFLNK; -+ } -+ -+ break; -+ case YAFFS_OBJECT_TYPE_DIRECTORY: -+ if (!S_ISDIR(mode)) { -+ obj->yst_mode &= ~S_IFMT; -+ obj->yst_mode |= S_IFDIR; -+ } -+ -+ break; -+ case YAFFS_OBJECT_TYPE_UNKNOWN: -+ case YAFFS_OBJECT_TYPE_HARDLINK: -+ case YAFFS_OBJECT_TYPE_SPECIAL: -+ default: -+ /* TODO? */ -+ break; -+ } -+ -+ inode->i_flags |= S_NOATIME; -+ -+ inode->i_ino = obj->obj_id; -+ inode->i_mode = obj->yst_mode; -+ inode->i_uid = obj->yst_uid; -+ inode->i_gid = obj->yst_gid; -+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19)) -+ inode->i_blksize = inode->i_sb->s_blocksize; -+#endif -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) -+ -+ inode->i_rdev = old_decode_dev(obj->yst_rdev); -+ inode->i_atime.tv_sec = (time_t) (obj->yst_atime); -+ inode->i_atime.tv_nsec = 0; -+ inode->i_mtime.tv_sec = (time_t) obj->yst_mtime; -+ inode->i_mtime.tv_nsec = 0; -+ inode->i_ctime.tv_sec = (time_t) obj->yst_ctime; -+ inode->i_ctime.tv_nsec = 0; -+#else -+ inode->i_rdev = obj->yst_rdev; -+ inode->i_atime = obj->yst_atime; -+ inode->i_mtime = obj->yst_mtime; -+ inode->i_ctime = obj->yst_ctime; -+#endif -+ inode->i_size = yaffs_get_obj_length(obj); -+ inode->i_blocks = (inode->i_size + 511) >> 9; -+ -+ inode->i_nlink = yaffs_get_obj_link_count(obj); -+ -+ T(YAFFS_TRACE_OS, -+ (TSTR -+ ("yaffs_fill_inode mode %x uid %d gid %d size %d count %d\n"), -+ inode->i_mode, inode->i_uid, inode->i_gid, -+ (int)inode->i_size, atomic_read(&inode->i_count))); -+ -+ switch (obj->yst_mode & S_IFMT) { -+ default: /* fifo, device or socket */ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) -+ init_special_inode(inode, obj->yst_mode, -+ old_decode_dev(obj->yst_rdev)); -+#else -+ init_special_inode(inode, obj->yst_mode, -+ (dev_t) (obj->yst_rdev)); -+#endif -+ break; -+ case S_IFREG: /* file */ -+ inode->i_op = &yaffs_file_inode_operations; -+ inode->i_fop = &yaffs_file_operations; -+ inode->i_mapping->a_ops = -+ &yaffs_file_address_operations; -+ break; -+ case S_IFDIR: /* directory */ -+ inode->i_op = &yaffs_dir_inode_operations; -+ inode->i_fop = &yaffs_dir_operations; -+ break; -+ case S_IFLNK: /* symlink */ -+ inode->i_op = &yaffs_symlink_inode_operations; -+ break; -+ } -+ -+ yaffs_inode_to_obj_lv(inode) = obj; -+ -+ obj->my_inode = inode; -+ -+ } else { -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_fill_inode invalid parameters\n"))); -+ } -+ -+} -+ -+struct inode *yaffs_get_inode(struct super_block *sb, int mode, int dev, -+ struct yaffs_obj *obj) -+{ -+ struct inode *inode; -+ -+ if (!sb) { -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_get_inode for NULL super_block!!\n"))); -+ return NULL; -+ -+ } -+ -+ if (!obj) { -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_get_inode for NULL object!!\n"))); -+ return NULL; -+ -+ } -+ -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_get_inode for object %d\n"), obj->obj_id)); -+ -+ inode = Y_IGET(sb, obj->obj_id); -+ if (IS_ERR(inode)) -+ return NULL; -+ -+ /* NB Side effect: iget calls back to yaffs_read_inode(). */ -+ /* iget also increments the inode's i_count */ -+ /* NB You can't be holding gross_lock or deadlock will happen! */ -+ -+ return inode; -+} -+ -+static ssize_t yaffs_file_write(struct file *f, const char *buf, size_t n, -+ loff_t * pos) -+{ -+ struct yaffs_obj *obj; -+ int n_written, ipos; -+ struct inode *inode; -+ struct yaffs_dev *dev; -+ -+ obj = yaffs_dentry_to_obj(f->f_dentry); -+ -+ dev = obj->my_dev; -+ -+ yaffs_gross_lock(dev); -+ -+ inode = f->f_dentry->d_inode; -+ -+ if (!S_ISBLK(inode->i_mode) && f->f_flags & O_APPEND) -+ ipos = inode->i_size; -+ else -+ ipos = *pos; -+ -+ if (!obj) -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_file_write: hey obj is null!\n"))); -+ else -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_file_write about to write writing %u(%x) bytes" -+ "to object %d at %d(%x)\n"), -+ (unsigned)n, (unsigned)n, obj->obj_id, ipos, ipos)); -+ -+ n_written = yaffs_wr_file(obj, buf, ipos, n, 0); -+ -+ yaffs_touch_super(dev); -+ -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_file_write: %d(%x) bytes written\n"), -+ (unsigned)n, (unsigned)n)); -+ -+ if (n_written > 0) { -+ ipos += n_written; -+ *pos = ipos; -+ if (ipos > inode->i_size) { -+ inode->i_size = ipos; -+ inode->i_blocks = (ipos + 511) >> 9; -+ -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_file_write size updated to %d bytes, " -+ "%d blocks\n"), ipos, (int)(inode->i_blocks))); -+ } -+ -+ } -+ yaffs_gross_unlock(dev); -+ return (n_written == 0) && (n > 0) ? -ENOSPC : n_written; -+} -+ -+/* Space holding and freeing is done to ensure we have space available for write_begin/end */ -+/* For now we just assume few parallel writes and check against a small number. */ -+/* Todo: need to do this with a counter to handle parallel reads better */ -+ -+static ssize_t yaffs_hold_space(struct file *f) -+{ -+ struct yaffs_obj *obj; -+ struct yaffs_dev *dev; -+ -+ int n_free_chunks; -+ -+ obj = yaffs_dentry_to_obj(f->f_dentry); -+ -+ dev = obj->my_dev; -+ -+ yaffs_gross_lock(dev); -+ -+ n_free_chunks = yaffs_get_n_free_chunks(dev); -+ -+ yaffs_gross_unlock(dev); -+ -+ return (n_free_chunks > 20) ? 1 : 0; -+} -+ -+static void yaffs_release_space(struct file *f) -+{ -+ struct yaffs_obj *obj; -+ struct yaffs_dev *dev; -+ -+ obj = yaffs_dentry_to_obj(f->f_dentry); -+ -+ dev = obj->my_dev; -+ -+ yaffs_gross_lock(dev); -+ -+ yaffs_gross_unlock(dev); -+} -+ -+static loff_t yaffs_dir_llseek(struct file *file, loff_t offset, int origin) -+{ -+ long long retval; -+ -+ lock_kernel(); -+ -+ switch (origin) { -+ case 2: -+ offset += i_size_read(file->f_path.dentry->d_inode); -+ break; -+ case 1: -+ offset += file->f_pos; -+ } -+ retval = -EINVAL; -+ -+ if (offset >= 0) { -+ if (offset != file->f_pos) -+ file->f_pos = offset; -+ -+ retval = offset; -+ } -+ unlock_kernel(); -+ return retval; -+} -+ -+static int yaffs_readdir(struct file *f, void *dirent, filldir_t filldir) -+{ -+ struct yaffs_obj *obj; -+ struct yaffs_dev *dev; -+ struct yaffs_search_context *sc; -+ struct inode *inode = f->f_dentry->d_inode; -+ unsigned long offset, curoffs; -+ struct yaffs_obj *l; -+ int ret_val = 0; -+ -+ char name[YAFFS_MAX_NAME_LENGTH + 1]; -+ -+ obj = yaffs_dentry_to_obj(f->f_dentry); -+ dev = obj->my_dev; -+ -+ yaffs_gross_lock(dev); -+ -+ yaffs_dev_to_lc(dev)->readdir_process = current; -+ -+ offset = f->f_pos; -+ -+ sc = yaffs_new_search(obj); -+ if (!sc) { -+ ret_val = -ENOMEM; -+ goto out; -+ } -+ -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_readdir: starting at %d\n"), (int)offset)); -+ -+ if (offset == 0) { -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_readdir: entry . ino %d \n"), -+ (int)inode->i_ino)); -+ yaffs_gross_unlock(dev); -+ if (filldir(dirent, ".", 1, offset, inode->i_ino, DT_DIR) < 0) { -+ yaffs_gross_lock(dev); -+ goto out; -+ } -+ yaffs_gross_lock(dev); -+ offset++; -+ f->f_pos++; -+ } -+ if (offset == 1) { -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_readdir: entry .. ino %d \n"), -+ (int)f->f_dentry->d_parent->d_inode->i_ino)); -+ yaffs_gross_unlock(dev); -+ if (filldir(dirent, "..", 2, offset, -+ f->f_dentry->d_parent->d_inode->i_ino, -+ DT_DIR) < 0) { -+ yaffs_gross_lock(dev); -+ goto out; -+ } -+ yaffs_gross_lock(dev); -+ offset++; -+ f->f_pos++; -+ } -+ -+ curoffs = 1; -+ -+ /* If the directory has changed since the open or last call to -+ readdir, rewind to after the 2 canned entries. */ -+ if (f->f_version != inode->i_version) { -+ offset = 2; -+ f->f_pos = offset; -+ f->f_version = inode->i_version; -+ } -+ -+ while (sc->next_return) { -+ curoffs++; -+ l = sc->next_return; -+ if (curoffs >= offset) { -+ int this_inode = yaffs_get_obj_inode(l); -+ int this_type = yaffs_get_obj_type(l); -+ -+ yaffs_get_obj_name(l, name, YAFFS_MAX_NAME_LENGTH + 1); -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_readdir: %s inode %d\n"), -+ name, yaffs_get_obj_inode(l))); -+ -+ yaffs_gross_unlock(dev); -+ -+ if (filldir(dirent, -+ name, -+ strlen(name), -+ offset, this_inode, this_type) < 0) { -+ yaffs_gross_lock(dev); -+ goto out; -+ } -+ -+ yaffs_gross_lock(dev); -+ -+ offset++; -+ f->f_pos++; -+ } -+ yaffs_search_advance(sc); -+ } -+ -+out: -+ yaffs_search_end(sc); -+ yaffs_dev_to_lc(dev)->readdir_process = NULL; -+ yaffs_gross_unlock(dev); -+ -+ return ret_val; -+} -+ -+/* -+ * File creation. Allocate an inode, and we're done.. -+ */ -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 29) -+#define YCRED(x) x -+#else -+#define YCRED(x) (x->cred) -+#endif -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) -+static int yaffs_mknod(struct inode *dir, struct dentry *dentry, int mode, -+ dev_t rdev) -+#else -+static int yaffs_mknod(struct inode *dir, struct dentry *dentry, int mode, -+ int rdev) -+#endif -+{ -+ struct inode *inode; -+ -+ struct yaffs_obj *obj = NULL; -+ struct yaffs_dev *dev; -+ -+ struct yaffs_obj *parent = yaffs_inode_to_obj(dir); -+ -+ int error = -ENOSPC; -+ uid_t uid = YCRED(current)->fsuid; -+ gid_t gid = -+ (dir->i_mode & S_ISGID) ? dir->i_gid : YCRED(current)->fsgid; -+ -+ if ((dir->i_mode & S_ISGID) && S_ISDIR(mode)) -+ mode |= S_ISGID; -+ -+ if (parent) { -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_mknod: parent object %d type %d\n"), -+ parent->obj_id, parent->variant_type)); -+ } else { -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_mknod: could not get parent object\n"))); -+ return -EPERM; -+ } -+ -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_mknod: making oject for %s, " -+ "mode %x dev %x\n"), -+ dentry->d_name.name, mode, rdev)); -+ -+ dev = parent->my_dev; -+ -+ yaffs_gross_lock(dev); -+ -+ switch (mode & S_IFMT) { -+ default: -+ /* Special (socket, fifo, device...) */ -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_mknod: making special\n"))); -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) -+ obj = -+ yaffs_create_special(parent, dentry->d_name.name, mode, uid, -+ gid, old_encode_dev(rdev)); -+#else -+ obj = -+ yaffs_create_special(parent, dentry->d_name.name, mode, uid, -+ gid, rdev); -+#endif -+ break; -+ case S_IFREG: /* file */ -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_mknod: making file\n"))); -+ obj = yaffs_create_file(parent, dentry->d_name.name, mode, uid, -+ gid); -+ break; -+ case S_IFDIR: /* directory */ -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_mknod: making directory\n"))); -+ obj = yaffs_create_dir(parent, dentry->d_name.name, mode, -+ uid, gid); -+ break; -+ case S_IFLNK: /* symlink */ -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_mknod: making symlink\n"))); -+ obj = NULL; /* Do we ever get here? */ -+ break; -+ } -+ -+ /* Can not call yaffs_get_inode() with gross lock held */ -+ yaffs_gross_unlock(dev); -+ -+ if (obj) { -+ inode = yaffs_get_inode(dir->i_sb, mode, rdev, obj); -+ d_instantiate(dentry, inode); -+ update_dir_time(dir); -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_mknod created object %d count = %d\n"), -+ obj->obj_id, atomic_read(&inode->i_count))); -+ error = 0; -+ yaffs_fill_inode_from_obj(dir, parent); -+ } else { -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_mknod failed making object\n"))); -+ error = -ENOMEM; -+ } -+ -+ return error; -+} -+ -+static int yaffs_mkdir(struct inode *dir, struct dentry *dentry, int mode) -+{ -+ int ret_val; -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_mkdir\n"))); -+ ret_val = yaffs_mknod(dir, dentry, mode | S_IFDIR, 0); -+ return ret_val; -+} -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) -+static int yaffs_create(struct inode *dir, struct dentry *dentry, int mode, -+ struct nameidata *n) -+#else -+static int yaffs_create(struct inode *dir, struct dentry *dentry, int mode) -+#endif -+{ -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_create\n"))); -+ return yaffs_mknod(dir, dentry, mode | S_IFREG, 0); -+} -+ -+static int yaffs_unlink(struct inode *dir, struct dentry *dentry) -+{ -+ int ret_val; -+ -+ struct yaffs_dev *dev; -+ struct yaffs_obj *obj; -+ -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_unlink %d:%s\n"), -+ (int)(dir->i_ino), dentry->d_name.name)); -+ obj = yaffs_inode_to_obj(dir); -+ dev = obj->my_dev; -+ -+ yaffs_gross_lock(dev); -+ -+ ret_val = yaffs_unlinker(obj, dentry->d_name.name); -+ -+ if (ret_val == YAFFS_OK) { -+ dentry->d_inode->i_nlink--; -+ dir->i_version++; -+ yaffs_gross_unlock(dev); -+ mark_inode_dirty(dentry->d_inode); -+ update_dir_time(dir); -+ return 0; -+ } -+ yaffs_gross_unlock(dev); -+ return -ENOTEMPTY; -+} -+ -+/* -+ * Create a link... -+ */ -+static int yaffs_link(struct dentry *old_dentry, struct inode *dir, -+ struct dentry *dentry) -+{ -+ struct inode *inode = old_dentry->d_inode; -+ struct yaffs_obj *obj = NULL; -+ struct yaffs_obj *link = NULL; -+ struct yaffs_dev *dev; -+ -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_link\n"))); -+ -+ obj = yaffs_inode_to_obj(inode); -+ dev = obj->my_dev; -+ -+ yaffs_gross_lock(dev); -+ -+ if (!S_ISDIR(inode->i_mode)) /* Don't link directories */ -+ link = -+ yaffs_link_obj(yaffs_inode_to_obj(dir), dentry->d_name.name, -+ obj); -+ -+ if (link) { -+ old_dentry->d_inode->i_nlink = yaffs_get_obj_link_count(obj); -+ d_instantiate(dentry, old_dentry->d_inode); -+ atomic_inc(&old_dentry->d_inode->i_count); -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_link link count %d i_count %d\n"), -+ old_dentry->d_inode->i_nlink, -+ atomic_read(&old_dentry->d_inode->i_count))); -+ } -+ -+ yaffs_gross_unlock(dev); -+ -+ if (link) { -+ update_dir_time(dir); -+ return 0; -+ } -+ -+ return -EPERM; -+} -+ -+static int yaffs_symlink(struct inode *dir, struct dentry *dentry, -+ const char *symname) -+{ -+ struct yaffs_obj *obj; -+ struct yaffs_dev *dev; -+ uid_t uid = YCRED(current)->fsuid; -+ gid_t gid = -+ (dir->i_mode & S_ISGID) ? dir->i_gid : YCRED(current)->fsgid; -+ -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_symlink\n"))); -+ -+ dev = yaffs_inode_to_obj(dir)->my_dev; -+ yaffs_gross_lock(dev); -+ obj = yaffs_create_symlink(yaffs_inode_to_obj(dir), dentry->d_name.name, -+ S_IFLNK | S_IRWXUGO, uid, gid, symname); -+ yaffs_gross_unlock(dev); -+ -+ if (obj) { -+ struct inode *inode; -+ -+ inode = yaffs_get_inode(dir->i_sb, obj->yst_mode, 0, obj); -+ d_instantiate(dentry, inode); -+ update_dir_time(dir); -+ T(YAFFS_TRACE_OS, (TSTR("symlink created OK\n"))); -+ return 0; -+ } else { -+ T(YAFFS_TRACE_OS, (TSTR("symlink not created\n"))); -+ } -+ -+ return -ENOMEM; -+} -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 34)) -+static int yaffs_sync_object(struct file *file, int datasync) -+#else -+static int yaffs_sync_object(struct file *file, struct dentry *dentry, -+ int datasync) -+#endif -+{ -+ -+ struct yaffs_obj *obj; -+ struct yaffs_dev *dev; -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 34)) -+ struct dentry *dentry = file->f_path.dentry; -+#endif -+ -+ obj = yaffs_dentry_to_obj(dentry); -+ -+ dev = obj->my_dev; -+ -+ T(YAFFS_TRACE_OS | YAFFS_TRACE_SYNC, (TSTR("yaffs_sync_object\n"))); -+ yaffs_gross_lock(dev); -+ yaffs_flush_file(obj, 1, datasync); -+ yaffs_gross_unlock(dev); -+ return 0; -+} -+ -+/* -+ * The VFS layer already does all the dentry stuff for rename. -+ * -+ * NB: POSIX says you can rename an object over an old object of the same name -+ */ -+static int yaffs_rename(struct inode *old_dir, struct dentry *old_dentry, -+ struct inode *new_dir, struct dentry *new_dentry) -+{ -+ struct yaffs_dev *dev; -+ int ret_val = YAFFS_FAIL; -+ struct yaffs_obj *target; -+ -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_rename\n"))); -+ dev = yaffs_inode_to_obj(old_dir)->my_dev; -+ -+ yaffs_gross_lock(dev); -+ -+ /* Check if the target is an existing directory that is not empty. */ -+ target = yaffs_find_by_name(yaffs_inode_to_obj(new_dir), -+ new_dentry->d_name.name); -+ -+ if (target && target->variant_type == YAFFS_OBJECT_TYPE_DIRECTORY && -+ !list_empty(&target->variant.dir_variant.children)) { -+ -+ T(YAFFS_TRACE_OS, (TSTR("target is non-empty dir\n"))); -+ -+ ret_val = YAFFS_FAIL; -+ } else { -+ /* Now does unlinking internally using shadowing mechanism */ -+ T(YAFFS_TRACE_OS, (TSTR("calling yaffs_rename_obj\n"))); -+ -+ ret_val = yaffs_rename_obj(yaffs_inode_to_obj(old_dir), -+ old_dentry->d_name.name, -+ yaffs_inode_to_obj(new_dir), -+ new_dentry->d_name.name); -+ } -+ yaffs_gross_unlock(dev); -+ -+ if (ret_val == YAFFS_OK) { -+ if (target) { -+ new_dentry->d_inode->i_nlink--; -+ mark_inode_dirty(new_dentry->d_inode); -+ } -+ -+ update_dir_time(old_dir); -+ if (old_dir != new_dir) -+ update_dir_time(new_dir); -+ return 0; -+ } else { -+ return -ENOTEMPTY; -+ } -+} -+ -+static int yaffs_setattr(struct dentry *dentry, struct iattr *attr) -+{ -+ struct inode *inode = dentry->d_inode; -+ int error = 0; -+ struct yaffs_dev *dev; -+ -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_setattr of object %d\n"), -+ yaffs_inode_to_obj(inode)->obj_id)); -+ -+ /* Fail if a requested resize >= 2GB */ -+ if (attr->ia_valid & ATTR_SIZE && (attr->ia_size >> 31)) -+ error = -EINVAL; -+ -+ if (error == 0) -+ error = inode_change_ok(inode, attr); -+ if (error == 0) { -+ int result; -+ if (!error) { -+ error = yaffs_vfs_setattr(inode, attr); -+ T(YAFFS_TRACE_OS, (TSTR("inode_setattr called\n"))); -+ if (attr->ia_valid & ATTR_SIZE) { -+ yaffs_vfs_setsize(inode, attr->ia_size); -+ inode->i_blocks = (inode->i_size + 511) >> 9; -+ } -+ } -+ dev = yaffs_inode_to_obj(inode)->my_dev; -+ if (attr->ia_valid & ATTR_SIZE) { -+ T(YAFFS_TRACE_OS, (TSTR("resize to %d(%x)\n"), -+ (int)(attr->ia_size), -+ (int)(attr->ia_size))); -+ } -+ yaffs_gross_lock(dev); -+ result = yaffs_set_attribs(yaffs_inode_to_obj(inode), attr); -+ if (result == YAFFS_OK) { -+ error = 0; -+ } else { -+ error = -EPERM; -+ } -+ yaffs_gross_unlock(dev); -+ -+ } -+ -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_setattr done returning %d\n"), error)); -+ -+ return error; -+} -+ -+#ifdef CONFIG_YAFFS_XATTR -+int yaffs_setxattr(struct dentry *dentry, const char *name, -+ const void *value, size_t size, int flags) -+{ -+ struct inode *inode = dentry->d_inode; -+ int error = 0; -+ struct yaffs_dev *dev; -+ struct yaffs_obj *obj = yaffs_inode_to_obj(inode); -+ -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_setxattr of object %d\n"), obj->obj_id)); -+ -+ if (error == 0) { -+ int result; -+ dev = obj->my_dev; -+ yaffs_gross_lock(dev); -+ result = yaffs_set_xattrib(obj, name, value, size, flags); -+ if (result == YAFFS_OK) -+ error = 0; -+ else if (result < 0) -+ error = result; -+ yaffs_gross_unlock(dev); -+ -+ } -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_setxattr done returning %d\n"), error)); -+ -+ return error; -+} -+ -+ssize_t yaffs_getxattr(struct dentry * dentry, const char *name, void *buff, -+ size_t size) -+{ -+ struct inode *inode = dentry->d_inode; -+ int error = 0; -+ struct yaffs_dev *dev; -+ struct yaffs_obj *obj = yaffs_inode_to_obj(inode); -+ -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_getxattr \"%s\" from object %d\n"), name, obj->obj_id)); -+ -+ if (error == 0) { -+ dev = obj->my_dev; -+ yaffs_gross_lock(dev); -+ error = yaffs_get_xattrib(obj, name, buff, size); -+ yaffs_gross_unlock(dev); -+ -+ } -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_getxattr done returning %d\n"), error)); -+ -+ return error; -+} -+ -+int yaffs_removexattr(struct dentry *dentry, const char *name) -+{ -+ struct inode *inode = dentry->d_inode; -+ int error = 0; -+ struct yaffs_dev *dev; -+ struct yaffs_obj *obj = yaffs_inode_to_obj(inode); -+ -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_removexattr of object %d\n"), obj->obj_id)); -+ -+ if (error == 0) { -+ int result; -+ dev = obj->my_dev; -+ yaffs_gross_lock(dev); -+ result = yaffs_remove_xattrib(obj, name); -+ if (result == YAFFS_OK) -+ error = 0; -+ else if (result < 0) -+ error = result; -+ yaffs_gross_unlock(dev); -+ -+ } -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_removexattr done returning %d\n"), error)); -+ -+ return error; -+} -+ -+ssize_t yaffs_listxattr(struct dentry * dentry, char *buff, size_t size) -+{ -+ struct inode *inode = dentry->d_inode; -+ int error = 0; -+ struct yaffs_dev *dev; -+ struct yaffs_obj *obj = yaffs_inode_to_obj(inode); -+ -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_listxattr of object %d\n"), obj->obj_id)); -+ -+ if (error == 0) { -+ dev = obj->my_dev; -+ yaffs_gross_lock(dev); -+ error = yaffs_list_xattrib(obj, buff, size); -+ yaffs_gross_unlock(dev); -+ -+ } -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_listxattr done returning %d\n"), error)); -+ -+ return error; -+} -+ -+#endif -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17)) -+static int yaffs_statfs(struct dentry *dentry, struct kstatfs *buf) -+{ -+ struct yaffs_dev *dev = yaffs_dentry_to_obj(dentry)->my_dev; -+ struct super_block *sb = dentry->d_sb; -+#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) -+static int yaffs_statfs(struct super_block *sb, struct kstatfs *buf) -+{ -+ struct yaffs_dev *dev = yaffs_super_to_dev(sb); -+#else -+static int yaffs_statfs(struct super_block *sb, struct statfs *buf) -+{ -+ struct yaffs_dev *dev = yaffs_super_to_dev(sb); -+#endif -+ -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_statfs\n"))); -+ -+ yaffs_gross_lock(dev); -+ -+ buf->f_type = YAFFS_MAGIC; -+ buf->f_bsize = sb->s_blocksize; -+ buf->f_namelen = 255; -+ -+ if (dev->data_bytes_per_chunk & (dev->data_bytes_per_chunk - 1)) { -+ /* Do this if chunk size is not a power of 2 */ -+ -+ uint64_t bytes_in_dev; -+ uint64_t bytes_free; -+ -+ bytes_in_dev = -+ ((uint64_t) -+ ((dev->param.end_block - dev->param.start_block + -+ 1))) * ((uint64_t) (dev->param.chunks_per_block * -+ dev->data_bytes_per_chunk)); -+ -+ do_div(bytes_in_dev, sb->s_blocksize); /* bytes_in_dev becomes the number of blocks */ -+ buf->f_blocks = bytes_in_dev; -+ -+ bytes_free = ((uint64_t) (yaffs_get_n_free_chunks(dev))) * -+ ((uint64_t) (dev->data_bytes_per_chunk)); -+ -+ do_div(bytes_free, sb->s_blocksize); -+ -+ buf->f_bfree = bytes_free; -+ -+ } else if (sb->s_blocksize > dev->data_bytes_per_chunk) { -+ -+ buf->f_blocks = -+ (dev->param.end_block - dev->param.start_block + 1) * -+ dev->param.chunks_per_block / -+ (sb->s_blocksize / dev->data_bytes_per_chunk); -+ buf->f_bfree = -+ yaffs_get_n_free_chunks(dev) / -+ (sb->s_blocksize / dev->data_bytes_per_chunk); -+ } else { -+ buf->f_blocks = -+ (dev->param.end_block - dev->param.start_block + 1) * -+ dev->param.chunks_per_block * -+ (dev->data_bytes_per_chunk / sb->s_blocksize); -+ -+ buf->f_bfree = -+ yaffs_get_n_free_chunks(dev) * -+ (dev->data_bytes_per_chunk / sb->s_blocksize); -+ } -+ -+ buf->f_files = 0; -+ buf->f_ffree = 0; -+ buf->f_bavail = buf->f_bfree; -+ -+ yaffs_gross_unlock(dev); -+ return 0; -+} -+ -+static void yaffs_flush_inodes(struct super_block *sb) -+{ -+ struct inode *iptr; -+ struct yaffs_obj *obj; -+ -+ list_for_each_entry(iptr, &sb->s_inodes, i_sb_list) { -+ obj = yaffs_inode_to_obj(iptr); -+ if (obj) { -+ T(YAFFS_TRACE_OS, (TSTR("flushing obj %d\n"), -+ obj->obj_id)); -+ yaffs_flush_file(obj, 1, 0); -+ } -+ } -+} -+ -+static void yaffs_flush_super(struct super_block *sb, int do_checkpoint) -+{ -+ struct yaffs_dev *dev = yaffs_super_to_dev(sb); -+ if (!dev) -+ return; -+ -+ yaffs_flush_inodes(sb); -+ yaffs_update_dirty_dirs(dev); -+ yaffs_flush_whole_cache(dev); -+ if (do_checkpoint) -+ yaffs_checkpoint_save(dev); -+} -+ -+static unsigned yaffs_bg_gc_urgency(struct yaffs_dev *dev) -+{ -+ unsigned erased_chunks = -+ dev->n_erased_blocks * dev->param.chunks_per_block; -+ struct yaffs_linux_context *context = yaffs_dev_to_lc(dev); -+ unsigned scattered = 0; /* Free chunks not in an erased block */ -+ -+ if (erased_chunks < dev->n_free_chunks) -+ scattered = (dev->n_free_chunks - erased_chunks); -+ -+ if (!context->bg_running) -+ return 0; -+ else if (scattered < (dev->param.chunks_per_block * 2)) -+ return 0; -+ else if (erased_chunks > dev->n_free_chunks / 2) -+ return 0; -+ else if (erased_chunks > dev->n_free_chunks / 4) -+ return 1; -+ else -+ return 2; -+} -+ -+static int yaffs_do_sync_fs(struct super_block *sb, int request_checkpoint) -+{ -+ -+ struct yaffs_dev *dev = yaffs_super_to_dev(sb); -+ unsigned int oneshot_checkpoint = (yaffs_auto_checkpoint & 4); -+ unsigned gc_urgent = yaffs_bg_gc_urgency(dev); -+ int do_checkpoint; -+ -+ T(YAFFS_TRACE_OS | YAFFS_TRACE_SYNC | YAFFS_TRACE_BACKGROUND, -+ (TSTR("yaffs_do_sync_fs: gc-urgency %d %s %s%s\n"), -+ gc_urgent, -+ sb->s_dirt ? "dirty" : "clean", -+ request_checkpoint ? "checkpoint requested" : "no checkpoint", -+ oneshot_checkpoint ? " one-shot" : "")); -+ -+ yaffs_gross_lock(dev); -+ do_checkpoint = ((request_checkpoint && !gc_urgent) || -+ oneshot_checkpoint) && !dev->is_checkpointed; -+ -+ if (sb->s_dirt || do_checkpoint) { -+ yaffs_flush_super(sb, !dev->is_checkpointed && do_checkpoint); -+ sb->s_dirt = 0; -+ if (oneshot_checkpoint) -+ yaffs_auto_checkpoint &= ~4; -+ } -+ yaffs_gross_unlock(dev); -+ -+ return 0; -+} -+ -+/* -+ * yaffs background thread functions . -+ * yaffs_bg_thread_fn() the thread function -+ * yaffs_bg_start() launches the background thread. -+ * yaffs_bg_stop() cleans up the background thread. -+ * -+ * NB: -+ * The thread should only run after the yaffs is initialised -+ * The thread should be stopped before yaffs is unmounted. -+ * The thread should not do any writing while the fs is in read only. -+ */ -+ -+#ifdef YAFFS_COMPILE_BACKGROUND -+ -+void yaffs_background_waker(unsigned long data) -+{ -+ wake_up_process((struct task_struct *)data); -+} -+ -+static int yaffs_bg_thread_fn(void *data) -+{ -+ struct yaffs_dev *dev = (struct yaffs_dev *)data; -+ struct yaffs_linux_context *context = yaffs_dev_to_lc(dev); -+ unsigned long now = jiffies; -+ unsigned long next_dir_update = now; -+ unsigned long next_gc = now; -+ unsigned long expires; -+ unsigned int urgency; -+ -+ int gc_result; -+ struct timer_list timer; -+ -+ T(YAFFS_TRACE_BACKGROUND, -+ (TSTR("yaffs_background starting for dev %p\n"), (void *)dev)); -+ -+#ifdef YAFFS_COMPILE_FREEZER -+ set_freezable(); -+#endif -+ while (context->bg_running) { -+ T(YAFFS_TRACE_BACKGROUND, (TSTR("yaffs_background\n"))); -+ -+ if (kthread_should_stop()) -+ break; -+ -+#ifdef YAFFS_COMPILE_FREEZER -+ if (try_to_freeze()) -+ continue; -+#endif -+ yaffs_gross_lock(dev); -+ -+ now = jiffies; -+ -+ if (time_after(now, next_dir_update) && yaffs_bg_enable) { -+ yaffs_update_dirty_dirs(dev); -+ next_dir_update = now + HZ; -+ } -+ -+ if (time_after(now, next_gc) && yaffs_bg_enable) { -+ if (!dev->is_checkpointed) { -+ urgency = yaffs_bg_gc_urgency(dev); -+ gc_result = yaffs_bg_gc(dev, urgency); -+ if (urgency > 1) -+ next_gc = now + HZ / 20 + 1; -+ else if (urgency > 0) -+ next_gc = now + HZ / 10 + 1; -+ else -+ next_gc = now + HZ * 2; -+ } else { -+ /* -+ * gc not running so set to next_dir_update -+ * to cut down on wake ups -+ */ -+ next_gc = next_dir_update; -+ } -+ } -+ yaffs_gross_unlock(dev); -+#if 1 -+ expires = next_dir_update; -+ if (time_before(next_gc, expires)) -+ expires = next_gc; -+ if (time_before(expires, now)) -+ expires = now + HZ; -+ -+ Y_INIT_TIMER(&timer); -+ timer.expires = expires + 1; -+ timer.data = (unsigned long)current; -+ timer.function = yaffs_background_waker; -+ -+ set_current_state(TASK_INTERRUPTIBLE); -+ add_timer(&timer); -+ schedule(); -+ del_timer_sync(&timer); -+#else -+ msleep(10); -+#endif -+ } -+ -+ return 0; -+} -+ -+static int yaffs_bg_start(struct yaffs_dev *dev) -+{ -+ int retval = 0; -+ struct yaffs_linux_context *context = yaffs_dev_to_lc(dev); -+ -+ if (dev->read_only) -+ return -1; -+ -+ context->bg_running = 1; -+ -+ context->bg_thread = kthread_run(yaffs_bg_thread_fn, -+ (void *)dev, "yaffs-bg-%d", -+ context->mount_id); -+ -+ if (IS_ERR(context->bg_thread)) { -+ retval = PTR_ERR(context->bg_thread); -+ context->bg_thread = NULL; -+ context->bg_running = 0; -+ } -+ return retval; -+} -+ -+static void yaffs_bg_stop(struct yaffs_dev *dev) -+{ -+ struct yaffs_linux_context *ctxt = yaffs_dev_to_lc(dev); -+ -+ ctxt->bg_running = 0; -+ -+ if (ctxt->bg_thread) { -+ kthread_stop(ctxt->bg_thread); -+ ctxt->bg_thread = NULL; -+ } -+} -+#else -+static int yaffs_bg_thread_fn(void *data) -+{ -+ return 0; -+} -+ -+static int yaffs_bg_start(struct yaffs_dev *dev) -+{ -+ return 0; -+} -+ -+static void yaffs_bg_stop(struct yaffs_dev *dev) -+{ -+} -+#endif -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17)) -+static void yaffs_write_super(struct super_block *sb) -+#else -+static int yaffs_write_super(struct super_block *sb) -+#endif -+{ -+ unsigned request_checkpoint = (yaffs_auto_checkpoint >= 2); -+ -+ T(YAFFS_TRACE_OS | YAFFS_TRACE_SYNC | YAFFS_TRACE_BACKGROUND, -+ (TSTR("yaffs_write_super%s\n"), -+ request_checkpoint ? " checkpt" : "")); -+ -+ yaffs_do_sync_fs(sb, request_checkpoint); -+ -+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)) -+ return 0; -+#endif -+} -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17)) -+static int yaffs_sync_fs(struct super_block *sb, int wait) -+#else -+static int yaffs_sync_fs(struct super_block *sb) -+#endif -+{ -+ unsigned request_checkpoint = (yaffs_auto_checkpoint >= 1); -+ -+ T(YAFFS_TRACE_OS | YAFFS_TRACE_SYNC, -+ (TSTR("yaffs_sync_fs%s\n"), request_checkpoint ? " checkpt" : "")); -+ -+ yaffs_do_sync_fs(sb, request_checkpoint); -+ -+ return 0; -+} -+ -+#ifdef YAFFS_USE_OWN_IGET -+ -+static struct inode *yaffs_iget(struct super_block *sb, unsigned long ino) -+{ -+ struct inode *inode; -+ struct yaffs_obj *obj; -+ struct yaffs_dev *dev = yaffs_super_to_dev(sb); -+ -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_iget for %lu\n"), ino)); -+ -+ inode = iget_locked(sb, ino); -+ if (!inode) -+ return ERR_PTR(-ENOMEM); -+ if (!(inode->i_state & I_NEW)) -+ return inode; -+ -+ /* NB This is called as a side effect of other functions, but -+ * we had to release the lock to prevent deadlocks, so -+ * need to lock again. -+ */ -+ -+ yaffs_gross_lock(dev); -+ -+ obj = yaffs_find_by_number(dev, inode->i_ino); -+ -+ yaffs_fill_inode_from_obj(inode, obj); -+ -+ yaffs_gross_unlock(dev); -+ -+ unlock_new_inode(inode); -+ return inode; -+} -+ -+#else -+ -+static void yaffs_read_inode(struct inode *inode) -+{ -+ /* NB This is called as a side effect of other functions, but -+ * we had to release the lock to prevent deadlocks, so -+ * need to lock again. -+ */ -+ -+ struct yaffs_obj *obj; -+ struct yaffs_dev *dev = yaffs_super_to_dev(inode->i_sb); -+ -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_read_inode for %d\n"), (int)inode->i_ino)); -+ -+ if (current != yaffs_dev_to_lc(dev)->readdir_process) -+ yaffs_gross_lock(dev); -+ -+ obj = yaffs_find_by_number(dev, inode->i_ino); -+ -+ yaffs_fill_inode_from_obj(inode, obj); -+ -+ if (current != yaffs_dev_to_lc(dev)->readdir_process) -+ yaffs_gross_unlock(dev); -+} -+ -+#endif -+ -+static LIST_HEAD(yaffs_context_list); -+struct mutex yaffs_context_lock; -+ -+static void yaffs_put_super(struct super_block *sb) -+{ -+ struct yaffs_dev *dev = yaffs_super_to_dev(sb); -+ -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_put_super\n"))); -+ -+ T(YAFFS_TRACE_OS | YAFFS_TRACE_BACKGROUND, -+ (TSTR("Shutting down yaffs background thread\n"))); -+ yaffs_bg_stop(dev); -+ T(YAFFS_TRACE_OS | YAFFS_TRACE_BACKGROUND, -+ (TSTR("yaffs background thread shut down\n"))); -+ -+ yaffs_gross_lock(dev); -+ -+ yaffs_flush_super(sb, 1); -+ -+ if (yaffs_dev_to_lc(dev)->put_super_fn) -+ yaffs_dev_to_lc(dev)->put_super_fn(sb); -+ -+ yaffs_deinitialise(dev); -+ -+ yaffs_gross_unlock(dev); -+ -+ mutex_lock(&yaffs_context_lock); -+ list_del_init(&(yaffs_dev_to_lc(dev)->context_list)); -+ mutex_unlock(&yaffs_context_lock); -+ -+ if (yaffs_dev_to_lc(dev)->spare_buffer) { -+ YFREE(yaffs_dev_to_lc(dev)->spare_buffer); -+ yaffs_dev_to_lc(dev)->spare_buffer = NULL; -+ } -+ -+ kfree(dev); -+} -+ -+static void yaffs_mtd_put_super(struct super_block *sb) -+{ -+ struct mtd_info *mtd = yaffs_dev_to_mtd(yaffs_super_to_dev(sb)); -+ -+ if (mtd->sync) -+ mtd->sync(mtd); -+ -+ put_mtd_device(mtd); -+} -+ -+static void yaffs_touch_super(struct yaffs_dev *dev) -+{ -+ struct super_block *sb = yaffs_dev_to_lc(dev)->super; -+ -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_touch_super() sb = %p\n"), sb)); -+ if (sb) -+ sb->s_dirt = 1; -+} -+ -+struct yaffs_options { -+ int inband_tags; -+ int skip_checkpoint_read; -+ int skip_checkpoint_write; -+ int no_cache; -+ int tags_ecc_on; -+ int tags_ecc_overridden; -+ int lazy_loading_enabled; -+ int lazy_loading_overridden; -+ int empty_lost_and_found; -+ int empty_lost_and_found_overridden; -+}; -+ -+#define MAX_OPT_LEN 30 -+static int yaffs_parse_options(struct yaffs_options *options, -+ const char *options_str) -+{ -+ char cur_opt[MAX_OPT_LEN + 1]; -+ int p; -+ int error = 0; -+ -+ /* Parse through the options which is a comma seperated list */ -+ -+ while (options_str && *options_str && !error) { -+ memset(cur_opt, 0, MAX_OPT_LEN + 1); -+ p = 0; -+ -+ while (*options_str == ',') -+ options_str++; -+ -+ while (*options_str && *options_str != ',') { -+ if (p < MAX_OPT_LEN) { -+ cur_opt[p] = *options_str; -+ p++; -+ } -+ options_str++; -+ } -+ -+ if (!strcmp(cur_opt, "inband-tags")) { -+ options->inband_tags = 1; -+ } else if (!strcmp(cur_opt, "tags-ecc-off")) { -+ options->tags_ecc_on = 0; -+ options->tags_ecc_overridden = 1; -+ } else if (!strcmp(cur_opt, "tags-ecc-on")) { -+ options->tags_ecc_on = 1; -+ options->tags_ecc_overridden = 1; -+ } else if (!strcmp(cur_opt, "lazy-loading-off")) { -+ options->lazy_loading_enabled = 0; -+ options->lazy_loading_overridden = 1; -+ } else if (!strcmp(cur_opt, "lazy-loading-on")) { -+ options->lazy_loading_enabled = 1; -+ options->lazy_loading_overridden = 1; -+ } else if (!strcmp(cur_opt, "empty-lost-and-found-off")) { -+ options->empty_lost_and_found = 0; -+ options->empty_lost_and_found_overridden = 1; -+ } else if (!strcmp(cur_opt, "empty-lost-and-found-on")) { -+ options->empty_lost_and_found = 1; -+ options->empty_lost_and_found_overridden = 1; -+ } else if (!strcmp(cur_opt, "no-cache")) { -+ options->no_cache = 1; -+ } else if (!strcmp(cur_opt, "no-checkpoint-read")) { -+ options->skip_checkpoint_read = 1; -+ } else if (!strcmp(cur_opt, "no-checkpoint-write")) { -+ options->skip_checkpoint_write = 1; -+ } else if (!strcmp(cur_opt, "no-checkpoint")) { -+ options->skip_checkpoint_read = 1; -+ options->skip_checkpoint_write = 1; -+ } else { -+ printk(KERN_INFO "yaffs: Bad mount option \"%s\"\n", -+ cur_opt); -+ error = 1; -+ } -+ } -+ -+ return error; -+} -+ -+static struct super_block *yaffs_internal_read_super(int yaffs_version, -+ struct super_block *sb, -+ void *data, int silent) -+{ -+ int n_blocks; -+ struct inode *inode = NULL; -+ struct dentry *root; -+ struct yaffs_dev *dev = 0; -+ char devname_buf[BDEVNAME_SIZE + 1]; -+ struct mtd_info *mtd; -+ int err; -+ char *data_str = (char *)data; -+ struct yaffs_linux_context *context = NULL; -+ struct yaffs_param *param; -+ -+ int read_only = 0; -+ -+ struct yaffs_options options; -+ -+ unsigned mount_id; -+ int found; -+ struct yaffs_linux_context *context_iterator; -+ struct list_head *l; -+ -+ sb->s_magic = YAFFS_MAGIC; -+ sb->s_op = &yaffs_super_ops; -+ sb->s_flags |= MS_NOATIME; -+ -+ read_only = ((sb->s_flags & MS_RDONLY) != 0); -+ -+#ifdef YAFFS_COMPILE_EXPORTFS -+ sb->s_export_op = &yaffs_export_ops; -+#endif -+ -+ if (!sb) -+ printk(KERN_INFO "yaffs: sb is NULL\n"); -+ else if (!sb->s_dev) -+ printk(KERN_INFO "yaffs: sb->s_dev is NULL\n"); -+ else if (!yaffs_devname(sb, devname_buf)) -+ printk(KERN_INFO "yaffs: devname is NULL\n"); -+ else -+ printk(KERN_INFO "yaffs: dev is %d name is \"%s\" %s\n", -+ sb->s_dev, -+ yaffs_devname(sb, devname_buf), read_only ? "ro" : "rw"); -+ -+ if (!data_str) -+ data_str = ""; -+ -+ printk(KERN_INFO "yaffs: passed flags \"%s\"\n", data_str); -+ -+ memset(&options, 0, sizeof(options)); -+ -+ if (yaffs_parse_options(&options, data_str)) { -+ /* Option parsing failed */ -+ return NULL; -+ } -+ -+ sb->s_blocksize = PAGE_CACHE_SIZE; -+ sb->s_blocksize_bits = PAGE_CACHE_SHIFT; -+ -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_read_super: Using yaffs%d\n"), yaffs_version)); -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_read_super: block size %d\n"), (int)(sb->s_blocksize))); -+ -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR("yaffs: Attempting MTD mount of %u.%u,\"%s\"\n"), -+ MAJOR(sb->s_dev), MINOR(sb->s_dev), yaffs_devname(sb, devname_buf))); -+ -+ /* Check it's an mtd device..... */ -+ if (MAJOR(sb->s_dev) != MTD_BLOCK_MAJOR) -+ return NULL; /* This isn't an mtd device */ -+ -+ /* Get the device */ -+ mtd = get_mtd_device(NULL, MINOR(sb->s_dev)); -+ if (!mtd) { -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR("yaffs: MTD device #%u doesn't appear to exist\n"), -+ MINOR(sb->s_dev))); -+ return NULL; -+ } -+ /* Check it's NAND */ -+ if (mtd->type != MTD_NANDFLASH) { -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR("yaffs: MTD device is not NAND it's type %d\n"), -+ mtd->type)); -+ return NULL; -+ } -+ -+ T(YAFFS_TRACE_OS, (TSTR(" erase %p\n"), mtd->erase)); -+ T(YAFFS_TRACE_OS, (TSTR(" read %p\n"), mtd->read)); -+ T(YAFFS_TRACE_OS, (TSTR(" write %p\n"), mtd->write)); -+ T(YAFFS_TRACE_OS, (TSTR(" readoob %p\n"), mtd->read_oob)); -+ T(YAFFS_TRACE_OS, (TSTR(" writeoob %p\n"), mtd->write_oob)); -+ T(YAFFS_TRACE_OS, (TSTR(" block_isbad %p\n"), mtd->block_isbad)); -+ T(YAFFS_TRACE_OS, (TSTR(" block_markbad %p\n"), mtd->block_markbad)); -+ T(YAFFS_TRACE_OS, (TSTR(" %s %d\n"), WRITE_SIZE_STR, WRITE_SIZE(mtd))); -+ T(YAFFS_TRACE_OS, (TSTR(" oobsize %d\n"), mtd->oobsize)); -+ T(YAFFS_TRACE_OS, (TSTR(" erasesize %d\n"), mtd->erasesize)); -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 29) -+ T(YAFFS_TRACE_OS, (TSTR(" size %u\n"), mtd->size)); -+#else -+ T(YAFFS_TRACE_OS, (TSTR(" size %lld\n"), mtd->size)); -+#endif -+ -+#ifdef CONFIG_YAFFS_AUTO_YAFFS2 -+ -+ if (yaffs_version == 1 && WRITE_SIZE(mtd) >= 2048) { -+ T(YAFFS_TRACE_ALWAYS, (TSTR("yaffs: auto selecting yaffs2\n"))); -+ yaffs_version = 2; -+ } -+ -+ /* Added NCB 26/5/2006 for completeness */ -+ if (yaffs_version == 2 && !options.inband_tags -+ && WRITE_SIZE(mtd) == 512) { -+ T(YAFFS_TRACE_ALWAYS, (TSTR("yaffs: auto selecting yaffs1\n"))); -+ yaffs_version = 1; -+ } -+#endif -+ -+ if (yaffs_version == 2) { -+ /* Check for version 2 style functions */ -+ if (!mtd->erase || -+ !mtd->block_isbad || -+ !mtd->block_markbad || !mtd->read || !mtd->write || -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17)) -+ !mtd->read_oob || !mtd->write_oob) { -+#else -+ !mtd->write_ecc || -+ !mtd->read_ecc || !mtd->read_oob || !mtd->write_oob) { -+#endif -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR("yaffs: MTD device does not support required " -+ "functions\n"))); -+ return NULL; -+ } -+ -+ if ((WRITE_SIZE(mtd) < YAFFS_MIN_YAFFS2_CHUNK_SIZE || -+ mtd->oobsize < YAFFS_MIN_YAFFS2_SPARE_SIZE) && -+ !options.inband_tags) { -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR("yaffs: MTD device does not have the " -+ "right page sizes\n"))); -+ return NULL; -+ } -+ } else { -+ /* Check for V1 style functions */ -+ if (!mtd->erase || !mtd->read || !mtd->write || -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17)) -+ !mtd->read_oob || !mtd->write_oob) { -+#else -+ !mtd->write_ecc || -+ !mtd->read_ecc || !mtd->read_oob || !mtd->write_oob) { -+#endif -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR("yaffs: MTD device does not support required " -+ "functions\n"))); -+ return NULL; -+ } -+ -+ if (WRITE_SIZE(mtd) < YAFFS_BYTES_PER_CHUNK || -+ mtd->oobsize != YAFFS_BYTES_PER_SPARE) { -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR("yaffs: MTD device does not support have the " -+ "right page sizes\n"))); -+ return NULL; -+ } -+ } -+ -+ /* OK, so if we got here, we have an MTD that's NAND and looks -+ * like it has the right capabilities -+ * Set the struct yaffs_dev up for mtd -+ */ -+ -+ if (!read_only && !(mtd->flags & MTD_WRITEABLE)) { -+ read_only = 1; -+ printk(KERN_INFO -+ "yaffs: mtd is read only, setting superblock read only"); -+ sb->s_flags |= MS_RDONLY; -+ } -+ -+ dev = kmalloc(sizeof(struct yaffs_dev), GFP_KERNEL); -+ context = kmalloc(sizeof(struct yaffs_linux_context), GFP_KERNEL); -+ -+ if (!dev || !context) { -+ if (dev) -+ kfree(dev); -+ if (context) -+ kfree(context); -+ dev = NULL; -+ context = NULL; -+ } -+ -+ if (!dev) { -+ /* Deep shit could not allocate device structure */ -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR("yaffs_read_super: Failed trying to allocate " -+ "struct yaffs_dev. \n"))); -+ return NULL; -+ } -+ memset(dev, 0, sizeof(struct yaffs_dev)); -+ param = &(dev->param); -+ -+ memset(context, 0, sizeof(struct yaffs_linux_context)); -+ dev->os_context = context; -+ INIT_LIST_HEAD(&(context->context_list)); -+ context->dev = dev; -+ context->super = sb; -+ -+ dev->read_only = read_only; -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) -+ sb->s_fs_info = dev; -+#else -+ sb->u.generic_sbp = dev; -+#endif -+ -+ dev->driver_context = mtd; -+ param->name = mtd->name; -+ -+ /* Set up the memory size parameters.... */ -+ -+ n_blocks = -+ YCALCBLOCKS(mtd->size, -+ (YAFFS_CHUNKS_PER_BLOCK * YAFFS_BYTES_PER_CHUNK)); -+ -+ param->start_block = 0; -+ param->end_block = n_blocks - 1; -+ param->chunks_per_block = YAFFS_CHUNKS_PER_BLOCK; -+ param->total_bytes_per_chunk = YAFFS_BYTES_PER_CHUNK; -+ param->n_reserved_blocks = 5; -+ param->n_caches = (options.no_cache) ? 0 : 10; -+ param->inband_tags = options.inband_tags; -+ -+#ifdef CONFIG_YAFFS_DISABLE_LAZY_LOAD -+ param->disable_lazy_load = 1; -+#endif -+#ifdef CONFIG_YAFFS_XATTR -+ param->enable_xattr = 1; -+#endif -+ if (options.lazy_loading_overridden) -+ param->disable_lazy_load = !options.lazy_loading_enabled; -+ -+#ifdef CONFIG_YAFFS_DISABLE_TAGS_ECC -+ param->no_tags_ecc = 1; -+#endif -+ -+#ifdef CONFIG_YAFFS_DISABLE_BACKGROUND -+#else -+ param->defered_dir_update = 1; -+#endif -+ -+ if (options.tags_ecc_overridden) -+ param->no_tags_ecc = !options.tags_ecc_on; -+ -+#ifdef CONFIG_YAFFS_EMPTY_LOST_AND_FOUND -+ param->empty_lost_n_found = 1; -+#endif -+ -+#ifdef CONFIG_YAFFS_DISABLE_BLOCK_REFRESHING -+ param->refresh_period = 0; -+#else -+ param->refresh_period = 500; -+#endif -+ -+#ifdef CONFIG_YAFFS__ALWAYS_CHECK_CHUNK_ERASED -+ param->always_check_erased = 1; -+#endif -+ -+ if (options.empty_lost_and_found_overridden) -+ param->empty_lost_n_found = options.empty_lost_and_found; -+ -+ /* ... and the functions. */ -+ if (yaffs_version == 2) { -+ param->write_chunk_tags_fn = nandmtd2_write_chunk_tags; -+ param->read_chunk_tags_fn = nandmtd2_read_chunk_tags; -+ param->bad_block_fn = nandmtd2_mark_block_bad; -+ param->query_block_fn = nandmtd2_query_block; -+ yaffs_dev_to_lc(dev)->spare_buffer = YMALLOC(mtd->oobsize); -+ param->is_yaffs2 = 1; -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17)) -+ param->total_bytes_per_chunk = mtd->writesize; -+ param->chunks_per_block = mtd->erasesize / mtd->writesize; -+#else -+ param->total_bytes_per_chunk = mtd->oobblock; -+ param->chunks_per_block = mtd->erasesize / mtd->oobblock; -+#endif -+ n_blocks = YCALCBLOCKS(mtd->size, mtd->erasesize); -+ -+ param->start_block = 0; -+ param->end_block = n_blocks - 1; -+ } else { -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17)) -+ /* use the MTD interface in yaffs_mtdif1.c */ -+ param->write_chunk_tags_fn = nandmtd1_write_chunk_tags; -+ param->read_chunk_tags_fn = nandmtd1_read_chunk_tags; -+ param->bad_block_fn = nandmtd1_mark_block_bad; -+ param->query_block_fn = nandmtd1_query_block; -+#else -+ param->write_chunk_fn = nandmtd_write_chunk; -+ param->read_chunk_fn = nandmtd_read_chunk; -+#endif -+ param->is_yaffs2 = 0; -+ } -+ /* ... and common functions */ -+ param->erase_fn = nandmtd_erase_block; -+ param->initialise_flash_fn = nandmtd_initialise; -+ -+ yaffs_dev_to_lc(dev)->put_super_fn = yaffs_mtd_put_super; -+ -+ param->sb_dirty_fn = yaffs_touch_super; -+ param->gc_control = yaffs_gc_control_callback; -+ -+ yaffs_dev_to_lc(dev)->super = sb; -+ -+#ifndef CONFIG_YAFFS_DOES_ECC -+ param->use_nand_ecc = 1; -+#endif -+ -+#ifdef CONFIG_YAFFS_DISABLE_WIDE_TNODES -+ param->wide_tnodes_disabled = 1; -+#endif -+ -+ param->skip_checkpt_rd = options.skip_checkpoint_read; -+ param->skip_checkpt_wr = options.skip_checkpoint_write; -+ -+ mutex_lock(&yaffs_context_lock); -+ /* Get a mount id */ -+ found = 0; -+ for (mount_id = 0; !found; mount_id++) { -+ found = 1; -+ list_for_each(l, &yaffs_context_list) { -+ context_iterator = -+ list_entry(l, struct yaffs_linux_context, -+ context_list); -+ if (context_iterator->mount_id == mount_id) -+ found = 0; -+ } -+ } -+ context->mount_id = mount_id; -+ -+ list_add_tail(&(yaffs_dev_to_lc(dev)->context_list), -+ &yaffs_context_list); -+ mutex_unlock(&yaffs_context_lock); -+ -+ /* Directory search handling... */ -+ INIT_LIST_HEAD(&(yaffs_dev_to_lc(dev)->search_contexts)); -+ param->remove_obj_fn = yaffs_remove_obj_callback; -+ -+ mutex_init(&(yaffs_dev_to_lc(dev)->gross_lock)); -+ -+ yaffs_gross_lock(dev); -+ -+ err = yaffs_guts_initialise(dev); -+ -+ T(YAFFS_TRACE_OS, -+ (TSTR("yaffs_read_super: guts initialised %s\n"), -+ (err == YAFFS_OK) ? "OK" : "FAILED")); -+ -+ if (err == YAFFS_OK) -+ yaffs_bg_start(dev); -+ -+ if (!context->bg_thread) -+ param->defered_dir_update = 0; -+ -+ /* Release lock before yaffs_get_inode() */ -+ yaffs_gross_unlock(dev); -+ -+ /* Create root inode */ -+ if (err == YAFFS_OK) -+ inode = yaffs_get_inode(sb, S_IFDIR | 0755, 0, yaffs_root(dev)); -+ -+ if (!inode) -+ return NULL; -+ -+ inode->i_op = &yaffs_dir_inode_operations; -+ inode->i_fop = &yaffs_dir_operations; -+ -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_read_super: got root inode\n"))); -+ -+ root = d_alloc_root(inode); -+ -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_read_super: d_alloc_root done\n"))); -+ -+ if (!root) { -+ iput(inode); -+ return NULL; -+ } -+ sb->s_root = root; -+ sb->s_dirt = !dev->is_checkpointed; -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR("yaffs_read_super: is_checkpointed %d\n"), -+ dev->is_checkpointed)); -+ -+ T(YAFFS_TRACE_OS, (TSTR("yaffs_read_super: done\n"))); -+ return sb; -+} -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) -+static int yaffs_internal_read_super_mtd(struct super_block *sb, void *data, -+ int silent) -+{ -+ return yaffs_internal_read_super(1, sb, data, silent) ? 0 : -EINVAL; -+} -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17)) -+static int yaffs_read_super(struct file_system_type *fs, -+ int flags, const char *dev_name, -+ void *data, struct vfsmount *mnt) -+{ -+ -+ return get_sb_bdev(fs, flags, dev_name, data, -+ yaffs_internal_read_super_mtd, mnt); -+} -+#else -+static struct super_block *yaffs_read_super(struct file_system_type *fs, -+ int flags, const char *dev_name, -+ void *data) -+{ -+ -+ return get_sb_bdev(fs, flags, dev_name, data, -+ yaffs_internal_read_super_mtd); -+} -+#endif -+ -+static struct file_system_type yaffs_fs_type = { -+ .owner = THIS_MODULE, -+ .name = "yaffs", -+ .get_sb = yaffs_read_super, -+ .kill_sb = kill_block_super, -+ .fs_flags = FS_REQUIRES_DEV, -+}; -+#else -+static struct super_block *yaffs_read_super(struct super_block *sb, void *data, -+ int silent) -+{ -+ return yaffs_internal_read_super(1, sb, data, silent); -+} -+ -+static DECLARE_FSTYPE(yaffs_fs_type, "yaffs", yaffs_read_super, -+ FS_REQUIRES_DEV); -+#endif -+ -+#ifdef CONFIG_YAFFS_YAFFS2 -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) -+static int yaffs2_internal_read_super_mtd(struct super_block *sb, void *data, -+ int silent) -+{ -+ return yaffs_internal_read_super(2, sb, data, silent) ? 0 : -EINVAL; -+} -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 17)) -+static int yaffs2_read_super(struct file_system_type *fs, -+ int flags, const char *dev_name, void *data, -+ struct vfsmount *mnt) -+{ -+ return get_sb_bdev(fs, flags, dev_name, data, -+ yaffs2_internal_read_super_mtd, mnt); -+} -+#else -+static struct super_block *yaffs2_read_super(struct file_system_type *fs, -+ int flags, const char *dev_name, -+ void *data) -+{ -+ -+ return get_sb_bdev(fs, flags, dev_name, data, -+ yaffs2_internal_read_super_mtd); -+} -+#endif -+ -+static struct file_system_type yaffs2_fs_type = { -+ .owner = THIS_MODULE, -+ .name = "yaffs2", -+ .get_sb = yaffs2_read_super, -+ .kill_sb = kill_block_super, -+ .fs_flags = FS_REQUIRES_DEV, -+}; -+#else -+static struct super_block *yaffs2_read_super(struct super_block *sb, -+ void *data, int silent) -+{ -+ return yaffs_internal_read_super(2, sb, data, silent); -+} -+ -+static DECLARE_FSTYPE(yaffs2_fs_type, "yaffs2", yaffs2_read_super, -+ FS_REQUIRES_DEV); -+#endif -+ -+#endif /* CONFIG_YAFFS_YAFFS2 */ -+ -+static struct proc_dir_entry *my_proc_entry; -+static struct proc_dir_entry *debug_proc_entry; -+ -+static char *yaffs_dump_dev_part0(char *buf, struct yaffs_dev *dev) -+{ -+ buf += -+ sprintf(buf, "start_block.......... %d\n", dev->param.start_block); -+ buf += sprintf(buf, "end_block............ %d\n", dev->param.end_block); -+ buf += -+ sprintf(buf, "total_bytes_per_chunk %d\n", -+ dev->param.total_bytes_per_chunk); -+ buf += -+ sprintf(buf, "use_nand_ecc......... %d\n", dev->param.use_nand_ecc); -+ buf += -+ sprintf(buf, "no_tags_ecc.......... %d\n", dev->param.no_tags_ecc); -+ buf += sprintf(buf, "is_yaffs2............ %d\n", dev->param.is_yaffs2); -+ buf += -+ sprintf(buf, "inband_tags.......... %d\n", dev->param.inband_tags); -+ buf += -+ sprintf(buf, "empty_lost_n_found... %d\n", -+ dev->param.empty_lost_n_found); -+ buf += -+ sprintf(buf, "disable_lazy_load.... %d\n", -+ dev->param.disable_lazy_load); -+ buf += -+ sprintf(buf, "refresh_period....... %d\n", -+ dev->param.refresh_period); -+ buf += sprintf(buf, "n_caches............. %d\n", dev->param.n_caches); -+ buf += -+ sprintf(buf, "n_reserved_blocks.... %d\n", -+ dev->param.n_reserved_blocks); -+ buf += -+ sprintf(buf, "always_check_erased.. %d\n", -+ dev->param.always_check_erased); -+ -+ buf += sprintf(buf, "\n"); -+ -+ return buf; -+} -+ -+static char *yaffs_dump_dev_part1(char *buf, struct yaffs_dev *dev) -+{ -+ buf += -+ sprintf(buf, "data_bytes_per_chunk. %d\n", -+ dev->data_bytes_per_chunk); -+ buf += sprintf(buf, "chunk_grp_bits....... %d\n", dev->chunk_grp_bits); -+ buf += sprintf(buf, "chunk_grp_size....... %d\n", dev->chunk_grp_size); -+ buf += sprintf(buf, "n_erased_blocks...... %d\n", dev->n_erased_blocks); -+ buf += -+ sprintf(buf, "blocks_in_checkpt.... %d\n", dev->blocks_in_checkpt); -+ buf += sprintf(buf, "\n"); -+ buf += sprintf(buf, "n_tnodes............. %d\n", dev->n_tnodes); -+ buf += sprintf(buf, "n_obj................ %d\n", dev->n_obj); -+ buf += sprintf(buf, "n_free_chunks........ %d\n", dev->n_free_chunks); -+ buf += sprintf(buf, "\n"); -+ buf += sprintf(buf, "n_page_writes........ %u\n", dev->n_page_writes); -+ buf += sprintf(buf, "n_page_reads......... %u\n", dev->n_page_reads); -+ buf += sprintf(buf, "n_erasures........... %u\n", dev->n_erasures); -+ buf += sprintf(buf, "n_gc_copies.......... %u\n", dev->n_gc_copies); -+ buf += sprintf(buf, "all_gcs.............. %u\n", dev->all_gcs); -+ buf += -+ sprintf(buf, "passive_gc_count..... %u\n", dev->passive_gc_count); -+ buf += -+ sprintf(buf, "oldest_dirty_gc_count %u\n", -+ dev->oldest_dirty_gc_count); -+ buf += sprintf(buf, "n_gc_blocks.......... %u\n", dev->n_gc_blocks); -+ buf += sprintf(buf, "bg_gcs............... %u\n", dev->bg_gcs); -+ buf += -+ sprintf(buf, "n_retired_writes..... %u\n", dev->n_retired_writes); -+ buf += -+ sprintf(buf, "n_retired_blocks..... %u\n", dev->n_retired_blocks); -+ buf += sprintf(buf, "n_ecc_fixed.......... %u\n", dev->n_ecc_fixed); -+ buf += sprintf(buf, "n_ecc_unfixed........ %u\n", dev->n_ecc_unfixed); -+ buf += -+ sprintf(buf, "n_tags_ecc_fixed..... %u\n", dev->n_tags_ecc_fixed); -+ buf += -+ sprintf(buf, "n_tags_ecc_unfixed... %u\n", dev->n_tags_ecc_unfixed); -+ buf += sprintf(buf, "cache_hits........... %u\n", dev->cache_hits); -+ buf += sprintf(buf, "n_deleted_files...... %u\n", dev->n_deleted_files); -+ buf += -+ sprintf(buf, "n_unlinked_files..... %u\n", dev->n_unlinked_files); -+ buf += sprintf(buf, "refresh_count........ %u\n", dev->refresh_count); -+ buf += sprintf(buf, "n_bg_deletions....... %u\n", dev->n_bg_deletions); -+ -+ return buf; -+} -+ -+static int yaffs_proc_read(char *page, -+ char **start, -+ off_t offset, int count, int *eof, void *data) -+{ -+ struct list_head *item; -+ char *buf = page; -+ int step = offset; -+ int n = 0; -+ -+ /* Get proc_file_read() to step 'offset' by one on each sucessive call. -+ * We use 'offset' (*ppos) to indicate where we are in dev_list. -+ * This also assumes the user has posted a read buffer large -+ * enough to hold the complete output; but that's life in /proc. -+ */ -+ -+ *(int *)start = 1; -+ -+ /* Print header first */ -+ if (step == 0) -+ buf += -+ sprintf(buf, -+ "Multi-version YAFFS built:" __DATE__ " " __TIME__ -+ "\n"); -+ else if (step == 1) -+ buf += sprintf(buf, "\n"); -+ else { -+ step -= 2; -+ -+ mutex_lock(&yaffs_context_lock); -+ -+ /* Locate and print the Nth entry. Order N-squared but N is small. */ -+ list_for_each(item, &yaffs_context_list) { -+ struct yaffs_linux_context *dc = -+ list_entry(item, struct yaffs_linux_context, -+ context_list); -+ struct yaffs_dev *dev = dc->dev; -+ -+ if (n < (step & ~1)) { -+ n += 2; -+ continue; -+ } -+ if ((step & 1) == 0) { -+ buf += -+ sprintf(buf, "\nDevice %d \"%s\"\n", n, -+ dev->param.name); -+ buf = yaffs_dump_dev_part0(buf, dev); -+ } else { -+ buf = yaffs_dump_dev_part1(buf, dev); -+ } -+ -+ break; -+ } -+ mutex_unlock(&yaffs_context_lock); -+ } -+ -+ return buf - page < count ? buf - page : count; -+} -+ -+static int yaffs_stats_proc_read(char *page, -+ char **start, -+ off_t offset, int count, int *eof, void *data) -+{ -+ struct list_head *item; -+ char *buf = page; -+ int n = 0; -+ -+ mutex_lock(&yaffs_context_lock); -+ -+ /* Locate and print the Nth entry. Order N-squared but N is small. */ -+ list_for_each(item, &yaffs_context_list) { -+ struct yaffs_linux_context *dc = -+ list_entry(item, struct yaffs_linux_context, context_list); -+ struct yaffs_dev *dev = dc->dev; -+ -+ int erased_chunks; -+ -+ erased_chunks = -+ dev->n_erased_blocks * dev->param.chunks_per_block; -+ -+ buf += sprintf(buf, "%d, %d, %d, %u, %u, %u, %u\n", -+ n, dev->n_free_chunks, erased_chunks, -+ dev->bg_gcs, dev->oldest_dirty_gc_count, -+ dev->n_obj, dev->n_tnodes); -+ } -+ mutex_unlock(&yaffs_context_lock); -+ -+ return buf - page < count ? buf - page : count; -+} -+ -+/** -+ * Set the verbosity of the warnings and error messages. -+ * -+ * Note that the names can only be a..z or _ with the current code. -+ */ -+ -+static struct { -+ char *mask_name; -+ unsigned mask_bitfield; -+} mask_flags[] = { -+ {"allocate", YAFFS_TRACE_ALLOCATE}, -+ {"always", YAFFS_TRACE_ALWAYS}, -+ {"background", YAFFS_TRACE_BACKGROUND}, -+ {"bad_blocks", YAFFS_TRACE_BAD_BLOCKS}, -+ {"buffers", YAFFS_TRACE_BUFFERS}, -+ {"bug", YAFFS_TRACE_BUG}, -+ {"checkpt", YAFFS_TRACE_CHECKPOINT}, -+ {"deletion", YAFFS_TRACE_DELETION}, -+ {"erase", YAFFS_TRACE_ERASE}, -+ {"error", YAFFS_TRACE_ERROR}, -+ {"gc_detail", YAFFS_TRACE_GC_DETAIL}, -+ {"gc", YAFFS_TRACE_GC}, -+ {"lock", YAFFS_TRACE_LOCK}, -+ {"mtd", YAFFS_TRACE_MTD}, -+ {"nandaccess", YAFFS_TRACE_NANDACCESS}, -+ {"os", YAFFS_TRACE_OS}, -+ {"scan_debug", YAFFS_TRACE_SCAN_DEBUG}, -+ {"scan", YAFFS_TRACE_SCAN}, -+ {"mount", YAFFS_TRACE_MOUNT}, -+ {"tracing", YAFFS_TRACE_TRACING}, -+ {"sync", YAFFS_TRACE_SYNC}, -+ {"write", YAFFS_TRACE_WRITE}, -+ {"verify", YAFFS_TRACE_VERIFY}, -+ {"verify_nand", YAFFS_TRACE_VERIFY_NAND}, -+ {"verify_full", YAFFS_TRACE_VERIFY_FULL}, -+ {"verify_all", YAFFS_TRACE_VERIFY_ALL}, -+ {"all", 0xffffffff}, -+ {"none", 0}, -+ {NULL, 0}, -+}; -+ -+#define MAX_MASK_NAME_LENGTH 40 -+static int yaffs_proc_write_trace_options(struct file *file, const char *buf, -+ unsigned long count, void *data) -+{ -+ unsigned rg = 0, mask_bitfield; -+ char *end; -+ char *mask_name; -+ const char *x; -+ char substring[MAX_MASK_NAME_LENGTH + 1]; -+ int i; -+ int done = 0; -+ int add, len = 0; -+ int pos = 0; -+ -+ rg = yaffs_trace_mask; -+ -+ while (!done && (pos < count)) { -+ done = 1; -+ while ((pos < count) && isspace(buf[pos])) -+ pos++; -+ -+ switch (buf[pos]) { -+ case '+': -+ case '-': -+ case '=': -+ add = buf[pos]; -+ pos++; -+ break; -+ -+ default: -+ add = ' '; -+ break; -+ } -+ mask_name = NULL; -+ -+ mask_bitfield = simple_strtoul(buf + pos, &end, 0); -+ -+ if (end > buf + pos) { -+ mask_name = "numeral"; -+ len = end - (buf + pos); -+ pos += len; -+ done = 0; -+ } else { -+ for (x = buf + pos, i = 0; -+ (*x == '_' || (*x >= 'a' && *x <= 'z')) && -+ i < MAX_MASK_NAME_LENGTH; x++, i++, pos++) -+ substring[i] = *x; -+ substring[i] = '\0'; -+ -+ for (i = 0; mask_flags[i].mask_name != NULL; i++) { -+ if (strcmp(substring, mask_flags[i].mask_name) -+ == 0) { -+ mask_name = mask_flags[i].mask_name; -+ mask_bitfield = -+ mask_flags[i].mask_bitfield; -+ done = 0; -+ break; -+ } -+ } -+ } -+ -+ if (mask_name != NULL) { -+ done = 0; -+ switch (add) { -+ case '-': -+ rg &= ~mask_bitfield; -+ break; -+ case '+': -+ rg |= mask_bitfield; -+ break; -+ case '=': -+ rg = mask_bitfield; -+ break; -+ default: -+ rg |= mask_bitfield; -+ break; -+ } -+ } -+ } -+ -+ yaffs_trace_mask = rg | YAFFS_TRACE_ALWAYS; -+ -+ printk(KERN_DEBUG "new trace = 0x%08X\n", yaffs_trace_mask); -+ -+ if (rg & YAFFS_TRACE_ALWAYS) { -+ for (i = 0; mask_flags[i].mask_name != NULL; i++) { -+ char flag; -+ flag = ((rg & mask_flags[i].mask_bitfield) == -+ mask_flags[i].mask_bitfield) ? '+' : '-'; -+ printk(KERN_DEBUG "%c%s\n", flag, -+ mask_flags[i].mask_name); -+ } -+ } -+ -+ return count; -+} -+ -+static int yaffs_proc_write(struct file *file, const char *buf, -+ unsigned long count, void *data) -+{ -+ return yaffs_proc_write_trace_options(file, buf, count, data); -+} -+ -+/* Stuff to handle installation of file systems */ -+struct file_system_to_install { -+ struct file_system_type *fst; -+ int installed; -+}; -+ -+static struct file_system_to_install fs_to_install[] = { -+ {&yaffs_fs_type, 0}, -+ {&yaffs2_fs_type, 0}, -+ {NULL, 0} -+}; -+ -+static int __init init_yaffs_fs(void) -+{ -+ int error = 0; -+ struct file_system_to_install *fsinst; -+ -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR("yaffs built " __DATE__ " " __TIME__ " Installing. \n"))); -+ -+#ifdef CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR -+ (" \n\n\n\nYAFFS-WARNING CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED selected.\n\n\n\n"))); -+#endif -+ -+ mutex_init(&yaffs_context_lock); -+ -+ /* Install the proc_fs entries */ -+ my_proc_entry = create_proc_entry("yaffs", -+ S_IRUGO | S_IFREG, YPROC_ROOT); -+ -+ if (my_proc_entry) { -+ my_proc_entry->write_proc = yaffs_proc_write; -+ my_proc_entry->read_proc = yaffs_proc_read; -+ my_proc_entry->data = NULL; -+ } else { -+ return -ENOMEM; -+ } -+ -+ debug_proc_entry = create_proc_entry("yaffs_stats", -+ S_IRUGO | S_IFREG, YPROC_ROOT); -+ -+ if (debug_proc_entry) { -+ debug_proc_entry->write_proc = NULL; -+ debug_proc_entry->read_proc = yaffs_stats_proc_read; -+ debug_proc_entry->data = NULL; -+ } else { -+ return -ENOMEM; -+ } -+ -+ /* Now add the file system entries */ -+ -+ fsinst = fs_to_install; -+ -+ while (fsinst->fst && !error) { -+ error = register_filesystem(fsinst->fst); -+ if (!error) -+ fsinst->installed = 1; -+ fsinst++; -+ } -+ -+ /* Any errors? uninstall */ -+ if (error) { -+ fsinst = fs_to_install; -+ -+ while (fsinst->fst) { -+ if (fsinst->installed) { -+ unregister_filesystem(fsinst->fst); -+ fsinst->installed = 0; -+ } -+ fsinst++; -+ } -+ } -+ -+ return error; -+} -+ -+static void __exit exit_yaffs_fs(void) -+{ -+ -+ struct file_system_to_install *fsinst; -+ -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR("yaffs built " __DATE__ " " __TIME__ " removing. \n"))); -+ -+ remove_proc_entry("yaffs", YPROC_ROOT); -+ remove_proc_entry("yaffs_stats", YPROC_ROOT); -+ -+ fsinst = fs_to_install; -+ -+ while (fsinst->fst) { -+ if (fsinst->installed) { -+ unregister_filesystem(fsinst->fst); -+ fsinst->installed = 0; -+ } -+ fsinst++; -+ } -+} -+ -+module_init(init_yaffs_fs) -+ module_exit(exit_yaffs_fs) -+ -+ MODULE_DESCRIPTION("YAFFS2 - a NAND specific flash file system"); -+MODULE_AUTHOR("Charles Manning, Aleph One Ltd., 2002-2010"); -+MODULE_LICENSE("GPL"); -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_yaffs1.c linux-2.6.36/fs/yaffs2/yaffs_yaffs1.c ---- linux-2.6.36.orig/fs/yaffs2/yaffs_yaffs1.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_yaffs1.c 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,437 @@ -+/* -+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include "yaffs_yaffs1.h" -+#include "yportenv.h" -+#include "yaffs_trace.h" -+#include "yaffs_bitmap.h" -+#include "yaffs_getblockinfo.h" -+#include "yaffs_nand.h" -+#include "yaffs_attribs.h" -+ -+int yaffs1_scan(struct yaffs_dev *dev) -+{ -+ struct yaffs_ext_tags tags; -+ int blk; -+ int result; -+ -+ int chunk; -+ int c; -+ int deleted; -+ enum yaffs_block_state state; -+ struct yaffs_obj *hard_list = NULL; -+ struct yaffs_block_info *bi; -+ u32 seq_number; -+ struct yaffs_obj_hdr *oh; -+ struct yaffs_obj *in; -+ struct yaffs_obj *parent; -+ -+ int alloc_failed = 0; -+ -+ struct yaffs_shadow_fixer *shadow_fixers = NULL; -+ -+ u8 *chunk_data; -+ -+ T(YAFFS_TRACE_SCAN, -+ (TSTR("yaffs1_scan starts intstartblk %d intendblk %d..." TENDSTR), -+ dev->internal_start_block, dev->internal_end_block)); -+ -+ chunk_data = yaffs_get_temp_buffer(dev, __LINE__); -+ -+ dev->seq_number = YAFFS_LOWEST_SEQUENCE_NUMBER; -+ -+ /* Scan all the blocks to determine their state */ -+ bi = dev->block_info; -+ for (blk = dev->internal_start_block; blk <= dev->internal_end_block; -+ blk++) { -+ yaffs_clear_chunk_bits(dev, blk); -+ bi->pages_in_use = 0; -+ bi->soft_del_pages = 0; -+ -+ yaffs_query_init_block_state(dev, blk, &state, &seq_number); -+ -+ bi->block_state = state; -+ bi->seq_number = seq_number; -+ -+ if (bi->seq_number == YAFFS_SEQUENCE_BAD_BLOCK) -+ bi->block_state = state = YAFFS_BLOCK_STATE_DEAD; -+ -+ T(YAFFS_TRACE_SCAN_DEBUG, -+ (TSTR("Block scanning block %d state %d seq %d" TENDSTR), blk, -+ state, seq_number)); -+ -+ if (state == YAFFS_BLOCK_STATE_DEAD) { -+ T(YAFFS_TRACE_BAD_BLOCKS, -+ (TSTR("block %d is bad" TENDSTR), blk)); -+ } else if (state == YAFFS_BLOCK_STATE_EMPTY) { -+ T(YAFFS_TRACE_SCAN_DEBUG, -+ (TSTR("Block empty " TENDSTR))); -+ dev->n_erased_blocks++; -+ dev->n_free_chunks += dev->param.chunks_per_block; -+ } -+ bi++; -+ } -+ -+ /* For each block.... */ -+ for (blk = dev->internal_start_block; -+ !alloc_failed && blk <= dev->internal_end_block; blk++) { -+ -+ YYIELD(); -+ -+ bi = yaffs_get_block_info(dev, blk); -+ state = bi->block_state; -+ -+ deleted = 0; -+ -+ /* For each chunk in each block that needs scanning.... */ -+ for (c = 0; !alloc_failed && c < dev->param.chunks_per_block && -+ state == YAFFS_BLOCK_STATE_NEEDS_SCANNING; c++) { -+ /* Read the tags and decide what to do */ -+ chunk = blk * dev->param.chunks_per_block + c; -+ -+ result = yaffs_rd_chunk_tags_nand(dev, chunk, NULL, -+ &tags); -+ -+ /* Let's have a good look at this chunk... */ -+ -+ if (tags.ecc_result == YAFFS_ECC_RESULT_UNFIXED -+ || tags.is_deleted) { -+ /* YAFFS1 only... -+ * A deleted chunk -+ */ -+ deleted++; -+ dev->n_free_chunks++; -+ /*T((" %d %d deleted\n",blk,c)); */ -+ } else if (!tags.chunk_used) { -+ /* An unassigned chunk in the block -+ * This means that either the block is empty or -+ * this is the one being allocated from -+ */ -+ -+ if (c == 0) { -+ /* We're looking at the first chunk in the block so the block is unused */ -+ state = YAFFS_BLOCK_STATE_EMPTY; -+ dev->n_erased_blocks++; -+ } else { -+ /* this is the block being allocated from */ -+ T(YAFFS_TRACE_SCAN, -+ (TSTR -+ (" Allocating from %d %d" TENDSTR), -+ blk, c)); -+ state = YAFFS_BLOCK_STATE_ALLOCATING; -+ dev->alloc_block = blk; -+ dev->alloc_page = c; -+ dev->alloc_block_finder = blk; -+ /* Set block finder here to encourage the allocator to go forth from here. */ -+ -+ } -+ -+ dev->n_free_chunks += -+ (dev->param.chunks_per_block - c); -+ } else if (tags.chunk_id > 0) { -+ /* chunk_id > 0 so it is a data chunk... */ -+ unsigned int endpos; -+ -+ yaffs_set_chunk_bit(dev, blk, c); -+ bi->pages_in_use++; -+ -+ in = yaffs_find_or_create_by_number(dev, -+ tags.obj_id, -+ YAFFS_OBJECT_TYPE_FILE); -+ /* PutChunkIntoFile checks for a clash (two data chunks with -+ * the same chunk_id). -+ */ -+ -+ if (!in) -+ alloc_failed = 1; -+ -+ if (in) { -+ if (!yaffs_put_chunk_in_file -+ (in, tags.chunk_id, chunk, 1)) -+ alloc_failed = 1; -+ } -+ -+ endpos = -+ (tags.chunk_id - -+ 1) * dev->data_bytes_per_chunk + -+ tags.n_bytes; -+ if (in -+ && in->variant_type == -+ YAFFS_OBJECT_TYPE_FILE -+ && in->variant.file_variant.scanned_size < -+ endpos) { -+ in->variant.file_variant.scanned_size = -+ endpos; -+ if (!dev->param.use_header_file_size) { -+ in->variant. -+ file_variant.file_size = -+ in->variant. -+ file_variant.scanned_size; -+ } -+ -+ } -+ /* T((" %d %d data %d %d\n",blk,c,tags.obj_id,tags.chunk_id)); */ -+ } else { -+ /* chunk_id == 0, so it is an ObjectHeader. -+ * Thus, we read in the object header and make the object -+ */ -+ yaffs_set_chunk_bit(dev, blk, c); -+ bi->pages_in_use++; -+ -+ result = yaffs_rd_chunk_tags_nand(dev, chunk, -+ chunk_data, -+ NULL); -+ -+ oh = (struct yaffs_obj_hdr *)chunk_data; -+ -+ in = yaffs_find_by_number(dev, tags.obj_id); -+ if (in && in->variant_type != oh->type) { -+ /* This should not happen, but somehow -+ * Wev'e ended up with an obj_id that has been reused but not yet -+ * deleted, and worse still it has changed type. Delete the old object. -+ */ -+ -+ yaffs_del_obj(in); -+ -+ in = 0; -+ } -+ -+ in = yaffs_find_or_create_by_number(dev, -+ tags.obj_id, -+ oh->type); -+ -+ if (!in) -+ alloc_failed = 1; -+ -+ if (in && oh->shadows_obj > 0) { -+ -+ struct yaffs_shadow_fixer *fixer; -+ fixer = -+ YMALLOC(sizeof -+ (struct -+ yaffs_shadow_fixer)); -+ if (fixer) { -+ fixer->next = shadow_fixers; -+ shadow_fixers = fixer; -+ fixer->obj_id = tags.obj_id; -+ fixer->shadowed_id = -+ oh->shadows_obj; -+ T(YAFFS_TRACE_SCAN, -+ (TSTR -+ (" Shadow fixer: %d shadows %d" -+ TENDSTR), fixer->obj_id, -+ fixer->shadowed_id)); -+ -+ } -+ -+ } -+ -+ if (in && in->valid) { -+ /* We have already filled this one. We have a duplicate and need to resolve it. */ -+ -+ unsigned existing_serial = in->serial; -+ unsigned new_serial = -+ tags.serial_number; -+ -+ if (((existing_serial + 1) & 3) == -+ new_serial) { -+ /* Use new one - destroy the exisiting one */ -+ yaffs_chunk_del(dev, -+ in->hdr_chunk, -+ 1, __LINE__); -+ in->valid = 0; -+ } else { -+ /* Use existing - destroy this one. */ -+ yaffs_chunk_del(dev, chunk, 1, -+ __LINE__); -+ } -+ } -+ -+ if (in && !in->valid && -+ (tags.obj_id == YAFFS_OBJECTID_ROOT || -+ tags.obj_id == -+ YAFFS_OBJECTID_LOSTNFOUND)) { -+ /* We only load some info, don't fiddle with directory structure */ -+ in->valid = 1; -+ in->variant_type = oh->type; -+ -+ in->yst_mode = oh->yst_mode; -+ yaffs_load_attribs(in, oh); -+ in->hdr_chunk = chunk; -+ in->serial = tags.serial_number; -+ -+ } else if (in && !in->valid) { -+ /* we need to load this info */ -+ -+ in->valid = 1; -+ in->variant_type = oh->type; -+ -+ in->yst_mode = oh->yst_mode; -+ yaffs_load_attribs(in, oh); -+ in->hdr_chunk = chunk; -+ in->serial = tags.serial_number; -+ -+ yaffs_set_obj_name_from_oh(in, oh); -+ in->dirty = 0; -+ -+ /* directory stuff... -+ * hook up to parent -+ */ -+ -+ parent = -+ yaffs_find_or_create_by_number -+ (dev, oh->parent_obj_id, -+ YAFFS_OBJECT_TYPE_DIRECTORY); -+ if (!parent) -+ alloc_failed = 1; -+ if (parent && parent->variant_type == -+ YAFFS_OBJECT_TYPE_UNKNOWN) { -+ /* Set up as a directory */ -+ parent->variant_type = -+ YAFFS_OBJECT_TYPE_DIRECTORY; -+ INIT_LIST_HEAD(&parent-> -+ variant.dir_variant.children); -+ } else if (!parent -+ || parent->variant_type != -+ YAFFS_OBJECT_TYPE_DIRECTORY) { -+ /* Hoosterman, another problem.... -+ * We're trying to use a non-directory as a directory -+ */ -+ -+ T(YAFFS_TRACE_ERROR, -+ (TSTR -+ ("yaffs tragedy: attempting to use non-directory as a directory in scan. Put in lost+found." -+ TENDSTR))); -+ parent = dev->lost_n_found; -+ } -+ -+ yaffs_add_obj_to_dir(parent, in); -+ -+ if (0 && (parent == dev->del_dir || -+ parent == -+ dev->unlinked_dir)) { -+ in->deleted = 1; /* If it is unlinked at start up then it wants deleting */ -+ dev->n_deleted_files++; -+ } -+ /* Note re hardlinks. -+ * Since we might scan a hardlink before its equivalent object is scanned -+ * we put them all in a list. -+ * After scanning is complete, we should have all the objects, so we run through this -+ * list and fix up all the chains. -+ */ -+ -+ switch (in->variant_type) { -+ case YAFFS_OBJECT_TYPE_UNKNOWN: -+ /* Todo got a problem */ -+ break; -+ case YAFFS_OBJECT_TYPE_FILE: -+ if (dev->param. -+ use_header_file_size) -+ -+ in->variant. -+ file_variant.file_size -+ = oh->file_size; -+ -+ break; -+ case YAFFS_OBJECT_TYPE_HARDLINK: -+ in->variant. -+ hardlink_variant.equiv_id = -+ oh->equiv_id; -+ in->hard_links.next = -+ (struct list_head *) -+ hard_list; -+ hard_list = in; -+ break; -+ case YAFFS_OBJECT_TYPE_DIRECTORY: -+ /* Do nothing */ -+ break; -+ case YAFFS_OBJECT_TYPE_SPECIAL: -+ /* Do nothing */ -+ break; -+ case YAFFS_OBJECT_TYPE_SYMLINK: -+ in->variant.symlink_variant. -+ alias = -+ yaffs_clone_str(oh->alias); -+ if (!in->variant. -+ symlink_variant.alias) -+ alloc_failed = 1; -+ break; -+ } -+ -+ } -+ } -+ } -+ -+ if (state == YAFFS_BLOCK_STATE_NEEDS_SCANNING) { -+ /* If we got this far while scanning, then the block is fully allocated. */ -+ state = YAFFS_BLOCK_STATE_FULL; -+ } -+ -+ if (state == YAFFS_BLOCK_STATE_ALLOCATING) { -+ /* If the block was partially allocated then treat it as fully allocated. */ -+ state = YAFFS_BLOCK_STATE_FULL; -+ dev->alloc_block = -1; -+ } -+ -+ bi->block_state = state; -+ -+ /* Now let's see if it was dirty */ -+ if (bi->pages_in_use == 0 && -+ !bi->has_shrink_hdr && -+ bi->block_state == YAFFS_BLOCK_STATE_FULL) { -+ yaffs_block_became_dirty(dev, blk); -+ } -+ -+ } -+ -+ /* Ok, we've done all the scanning. -+ * Fix up the hard link chains. -+ * We should now have scanned all the objects, now it's time to add these -+ * hardlinks. -+ */ -+ -+ yaffs_link_fixup(dev, hard_list); -+ -+ /* Fix up any shadowed objects */ -+ { -+ struct yaffs_shadow_fixer *fixer; -+ struct yaffs_obj *obj; -+ -+ while (shadow_fixers) { -+ fixer = shadow_fixers; -+ shadow_fixers = fixer->next; -+ /* Complete the rename transaction by deleting the shadowed object -+ * then setting the object header to unshadowed. -+ */ -+ obj = yaffs_find_by_number(dev, fixer->shadowed_id); -+ if (obj) -+ yaffs_del_obj(obj); -+ -+ obj = yaffs_find_by_number(dev, fixer->obj_id); -+ -+ if (obj) -+ yaffs_update_oh(obj, NULL, 1, 0, 0, NULL); -+ -+ YFREE(fixer); -+ } -+ } -+ -+ yaffs_release_temp_buffer(dev, chunk_data, __LINE__); -+ -+ if (alloc_failed) -+ return YAFFS_FAIL; -+ -+ T(YAFFS_TRACE_SCAN, (TSTR("yaffs1_scan ends" TENDSTR))); -+ -+ return YAFFS_OK; -+} -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_yaffs1.h linux-2.6.36/fs/yaffs2/yaffs_yaffs1.h ---- linux-2.6.36.orig/fs/yaffs2/yaffs_yaffs1.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_yaffs1.h 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,22 @@ -+/* -+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU Lesser General Public License version 2.1 as -+ * published by the Free Software Foundation. -+ * -+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. -+ */ -+ -+#ifndef __YAFFS_YAFFS1_H__ -+#define __YAFFS_YAFFS1_H__ -+ -+#include "yaffs_guts.h" -+int yaffs1_scan(struct yaffs_dev *dev); -+ -+#endif -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_yaffs2.c linux-2.6.36/fs/yaffs2/yaffs_yaffs2.c ---- linux-2.6.36.orig/fs/yaffs2/yaffs_yaffs2.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_yaffs2.c 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,1620 @@ -+/* -+ * YAFFS: Yet Another Flash File System. A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include "yaffs_guts.h" -+#include "yaffs_trace.h" -+#include "yaffs_yaffs2.h" -+#include "yaffs_checkptrw.h" -+#include "yaffs_bitmap.h" -+#include "yaffs_nand.h" -+#include "yaffs_getblockinfo.h" -+#include "yaffs_verify.h" -+#include "yaffs_attribs.h" -+ -+/* -+ * Checkpoints are really no benefit on very small partitions. -+ * -+ * To save space on small partitions don't bother with checkpoints unless -+ * the partition is at least this big. -+ */ -+#define YAFFS_CHECKPOINT_MIN_BLOCKS 60 -+ -+#define YAFFS_SMALL_HOLE_THRESHOLD 4 -+ -+/* -+ * Oldest Dirty Sequence Number handling. -+ */ -+ -+/* yaffs_calc_oldest_dirty_seq() -+ * yaffs2_find_oldest_dirty_seq() -+ * Calculate the oldest dirty sequence number if we don't know it. -+ */ -+void yaffs_calc_oldest_dirty_seq(struct yaffs_dev *dev) -+{ -+ int i; -+ unsigned seq; -+ unsigned block_no = 0; -+ struct yaffs_block_info *b; -+ -+ if (!dev->param.is_yaffs2) -+ return; -+ -+ /* Find the oldest dirty sequence number. */ -+ seq = dev->seq_number + 1; -+ b = dev->block_info; -+ for (i = dev->internal_start_block; i <= dev->internal_end_block; i++) { -+ if (b->block_state == YAFFS_BLOCK_STATE_FULL && -+ (b->pages_in_use - b->soft_del_pages) < -+ dev->param.chunks_per_block && b->seq_number < seq) { -+ seq = b->seq_number; -+ block_no = i; -+ } -+ b++; -+ } -+ -+ if (block_no) { -+ dev->oldest_dirty_seq = seq; -+ dev->oldest_dirty_block = block_no; -+ } -+ -+} -+ -+void yaffs2_find_oldest_dirty_seq(struct yaffs_dev *dev) -+{ -+ if (!dev->param.is_yaffs2) -+ return; -+ -+ if (!dev->oldest_dirty_seq) -+ yaffs_calc_oldest_dirty_seq(dev); -+} -+ -+/* -+ * yaffs_clear_oldest_dirty_seq() -+ * Called when a block is erased or marked bad. (ie. when its seq_number -+ * becomes invalid). If the value matches the oldest then we clear -+ * dev->oldest_dirty_seq to force its recomputation. -+ */ -+void yaffs2_clear_oldest_dirty_seq(struct yaffs_dev *dev, -+ struct yaffs_block_info *bi) -+{ -+ -+ if (!dev->param.is_yaffs2) -+ return; -+ -+ if (!bi || bi->seq_number == dev->oldest_dirty_seq) { -+ dev->oldest_dirty_seq = 0; -+ dev->oldest_dirty_block = 0; -+ } -+} -+ -+/* -+ * yaffs2_update_oldest_dirty_seq() -+ * Update the oldest dirty sequence number whenever we dirty a block. -+ * Only do this if the oldest_dirty_seq is actually being tracked. -+ */ -+void yaffs2_update_oldest_dirty_seq(struct yaffs_dev *dev, unsigned block_no, -+ struct yaffs_block_info *bi) -+{ -+ if (!dev->param.is_yaffs2) -+ return; -+ -+ if (dev->oldest_dirty_seq) { -+ if (dev->oldest_dirty_seq > bi->seq_number) { -+ dev->oldest_dirty_seq = bi->seq_number; -+ dev->oldest_dirty_block = block_no; -+ } -+ } -+} -+ -+int yaffs_block_ok_for_gc(struct yaffs_dev *dev, struct yaffs_block_info *bi) -+{ -+ -+ if (!dev->param.is_yaffs2) -+ return 1; /* disqualification only applies to yaffs2. */ -+ -+ if (!bi->has_shrink_hdr) -+ return 1; /* can gc */ -+ -+ yaffs2_find_oldest_dirty_seq(dev); -+ -+ /* Can't do gc of this block if there are any blocks older than this one that have -+ * discarded pages. -+ */ -+ return (bi->seq_number <= dev->oldest_dirty_seq); -+} -+ -+/* -+ * yaffs2_find_refresh_block() -+ * periodically finds the oldest full block by sequence number for refreshing. -+ * Only for yaffs2. -+ */ -+u32 yaffs2_find_refresh_block(struct yaffs_dev * dev) -+{ -+ u32 b; -+ -+ u32 oldest = 0; -+ u32 oldest_seq = 0; -+ -+ struct yaffs_block_info *bi; -+ -+ if (!dev->param.is_yaffs2) -+ return oldest; -+ -+ /* -+ * If refresh period < 10 then refreshing is disabled. -+ */ -+ if (dev->param.refresh_period < 10) -+ return oldest; -+ -+ /* -+ * Fix broken values. -+ */ -+ if (dev->refresh_skip > dev->param.refresh_period) -+ dev->refresh_skip = dev->param.refresh_period; -+ -+ if (dev->refresh_skip > 0) -+ return oldest; -+ -+ /* -+ * Refresh skip is now zero. -+ * We'll do a refresh this time around.... -+ * Update the refresh skip and find the oldest block. -+ */ -+ dev->refresh_skip = dev->param.refresh_period; -+ dev->refresh_count++; -+ bi = dev->block_info; -+ for (b = dev->internal_start_block; b <= dev->internal_end_block; b++) { -+ -+ if (bi->block_state == YAFFS_BLOCK_STATE_FULL) { -+ -+ if (oldest < 1 || bi->seq_number < oldest_seq) { -+ oldest = b; -+ oldest_seq = bi->seq_number; -+ } -+ } -+ bi++; -+ } -+ -+ if (oldest > 0) { -+ T(YAFFS_TRACE_GC, -+ (TSTR -+ ("GC refresh count %d selected block %d with seq_number %d" -+ TENDSTR), dev->refresh_count, oldest, oldest_seq)); -+ } -+ -+ return oldest; -+} -+ -+int yaffs2_checkpt_required(struct yaffs_dev *dev) -+{ -+ int nblocks; -+ -+ if (!dev->param.is_yaffs2) -+ return 0; -+ -+ nblocks = dev->internal_end_block - dev->internal_start_block + 1; -+ -+ return !dev->param.skip_checkpt_wr && -+ !dev->read_only && (nblocks >= YAFFS_CHECKPOINT_MIN_BLOCKS); -+} -+ -+int yaffs_calc_checkpt_blocks_required(struct yaffs_dev *dev) -+{ -+ int retval; -+ -+ if (!dev->param.is_yaffs2) -+ return 0; -+ -+ if (!dev->checkpoint_blocks_required && yaffs2_checkpt_required(dev)) { -+ /* Not a valid value so recalculate */ -+ int n_bytes = 0; -+ int n_blocks; -+ int dev_blocks = -+ (dev->param.end_block - dev->param.start_block + 1); -+ -+ n_bytes += sizeof(struct yaffs_checkpt_validity); -+ n_bytes += sizeof(struct yaffs_checkpt_dev); -+ n_bytes += dev_blocks * sizeof(struct yaffs_block_info); -+ n_bytes += dev_blocks * dev->chunk_bit_stride; -+ n_bytes += -+ (sizeof(struct yaffs_checkpt_obj) + -+ sizeof(u32)) * (dev->n_obj); -+ n_bytes += (dev->tnode_size + sizeof(u32)) * (dev->n_tnodes); -+ n_bytes += sizeof(struct yaffs_checkpt_validity); -+ n_bytes += sizeof(u32); /* checksum */ -+ -+ /* Round up and add 2 blocks to allow for some bad blocks, so add 3 */ -+ -+ n_blocks = -+ (n_bytes / -+ (dev->data_bytes_per_chunk * -+ dev->param.chunks_per_block)) + 3; -+ -+ dev->checkpoint_blocks_required = n_blocks; -+ } -+ -+ retval = dev->checkpoint_blocks_required - dev->blocks_in_checkpt; -+ if (retval < 0) -+ retval = 0; -+ return retval; -+} -+ -+/*--------------------- Checkpointing --------------------*/ -+ -+static int yaffs2_wr_checkpt_validity_marker(struct yaffs_dev *dev, int head) -+{ -+ struct yaffs_checkpt_validity cp; -+ -+ memset(&cp, 0, sizeof(cp)); -+ -+ cp.struct_type = sizeof(cp); -+ cp.magic = YAFFS_MAGIC; -+ cp.version = YAFFS_CHECKPOINT_VERSION; -+ cp.head = (head) ? 1 : 0; -+ -+ return (yaffs2_checkpt_wr(dev, &cp, sizeof(cp)) == sizeof(cp)) ? 1 : 0; -+} -+ -+static int yaffs2_rd_checkpt_validity_marker(struct yaffs_dev *dev, int head) -+{ -+ struct yaffs_checkpt_validity cp; -+ int ok; -+ -+ ok = (yaffs2_checkpt_rd(dev, &cp, sizeof(cp)) == sizeof(cp)); -+ -+ if (ok) -+ ok = (cp.struct_type == sizeof(cp)) && -+ (cp.magic == YAFFS_MAGIC) && -+ (cp.version == YAFFS_CHECKPOINT_VERSION) && -+ (cp.head == ((head) ? 1 : 0)); -+ return ok ? 1 : 0; -+} -+ -+static void yaffs2_dev_to_checkpt_dev(struct yaffs_checkpt_dev *cp, -+ struct yaffs_dev *dev) -+{ -+ cp->n_erased_blocks = dev->n_erased_blocks; -+ cp->alloc_block = dev->alloc_block; -+ cp->alloc_page = dev->alloc_page; -+ cp->n_free_chunks = dev->n_free_chunks; -+ -+ cp->n_deleted_files = dev->n_deleted_files; -+ cp->n_unlinked_files = dev->n_unlinked_files; -+ cp->n_bg_deletions = dev->n_bg_deletions; -+ cp->seq_number = dev->seq_number; -+ -+} -+ -+static void yaffs_checkpt_dev_to_dev(struct yaffs_dev *dev, -+ struct yaffs_checkpt_dev *cp) -+{ -+ dev->n_erased_blocks = cp->n_erased_blocks; -+ dev->alloc_block = cp->alloc_block; -+ dev->alloc_page = cp->alloc_page; -+ dev->n_free_chunks = cp->n_free_chunks; -+ -+ dev->n_deleted_files = cp->n_deleted_files; -+ dev->n_unlinked_files = cp->n_unlinked_files; -+ dev->n_bg_deletions = cp->n_bg_deletions; -+ dev->seq_number = cp->seq_number; -+} -+ -+static int yaffs2_wr_checkpt_dev(struct yaffs_dev *dev) -+{ -+ struct yaffs_checkpt_dev cp; -+ u32 n_bytes; -+ u32 n_blocks = -+ (dev->internal_end_block - dev->internal_start_block + 1); -+ -+ int ok; -+ -+ /* Write device runtime values */ -+ yaffs2_dev_to_checkpt_dev(&cp, dev); -+ cp.struct_type = sizeof(cp); -+ -+ ok = (yaffs2_checkpt_wr(dev, &cp, sizeof(cp)) == sizeof(cp)); -+ -+ /* Write block info */ -+ if (ok) { -+ n_bytes = n_blocks * sizeof(struct yaffs_block_info); -+ ok = (yaffs2_checkpt_wr(dev, dev->block_info, n_bytes) == -+ n_bytes); -+ } -+ -+ /* Write chunk bits */ -+ if (ok) { -+ n_bytes = n_blocks * dev->chunk_bit_stride; -+ ok = (yaffs2_checkpt_wr(dev, dev->chunk_bits, n_bytes) == -+ n_bytes); -+ } -+ return ok ? 1 : 0; -+ -+} -+ -+static int yaffs2_rd_checkpt_dev(struct yaffs_dev *dev) -+{ -+ struct yaffs_checkpt_dev cp; -+ u32 n_bytes; -+ u32 n_blocks = -+ (dev->internal_end_block - dev->internal_start_block + 1); -+ -+ int ok; -+ -+ ok = (yaffs2_checkpt_rd(dev, &cp, sizeof(cp)) == sizeof(cp)); -+ if (!ok) -+ return 0; -+ -+ if (cp.struct_type != sizeof(cp)) -+ return 0; -+ -+ yaffs_checkpt_dev_to_dev(dev, &cp); -+ -+ n_bytes = n_blocks * sizeof(struct yaffs_block_info); -+ -+ ok = (yaffs2_checkpt_rd(dev, dev->block_info, n_bytes) == n_bytes); -+ -+ if (!ok) -+ return 0; -+ n_bytes = n_blocks * dev->chunk_bit_stride; -+ -+ ok = (yaffs2_checkpt_rd(dev, dev->chunk_bits, n_bytes) == n_bytes); -+ -+ return ok ? 1 : 0; -+} -+ -+static void yaffs2_obj_checkpt_obj(struct yaffs_checkpt_obj *cp, -+ struct yaffs_obj *obj) -+{ -+ -+ cp->obj_id = obj->obj_id; -+ cp->parent_id = (obj->parent) ? obj->parent->obj_id : 0; -+ cp->hdr_chunk = obj->hdr_chunk; -+ cp->variant_type = obj->variant_type; -+ cp->deleted = obj->deleted; -+ cp->soft_del = obj->soft_del; -+ cp->unlinked = obj->unlinked; -+ cp->fake = obj->fake; -+ cp->rename_allowed = obj->rename_allowed; -+ cp->unlink_allowed = obj->unlink_allowed; -+ cp->serial = obj->serial; -+ cp->n_data_chunks = obj->n_data_chunks; -+ -+ if (obj->variant_type == YAFFS_OBJECT_TYPE_FILE) -+ cp->size_or_equiv_obj = obj->variant.file_variant.file_size; -+ else if (obj->variant_type == YAFFS_OBJECT_TYPE_HARDLINK) -+ cp->size_or_equiv_obj = obj->variant.hardlink_variant.equiv_id; -+} -+ -+static int taffs2_checkpt_obj_to_obj(struct yaffs_obj *obj, -+ struct yaffs_checkpt_obj *cp) -+{ -+ -+ struct yaffs_obj *parent; -+ -+ if (obj->variant_type != cp->variant_type) { -+ T(YAFFS_TRACE_ERROR, (TSTR("Checkpoint read object %d type %d " -+ TCONT -+ ("chunk %d does not match existing object type %d") -+ TENDSTR), cp->obj_id, -+ cp->variant_type, cp->hdr_chunk, -+ obj->variant_type)); -+ return 0; -+ } -+ -+ obj->obj_id = cp->obj_id; -+ -+ if (cp->parent_id) -+ parent = yaffs_find_or_create_by_number(obj->my_dev, -+ cp->parent_id, -+ YAFFS_OBJECT_TYPE_DIRECTORY); -+ else -+ parent = NULL; -+ -+ if (parent) { -+ if (parent->variant_type != YAFFS_OBJECT_TYPE_DIRECTORY) { -+ T(YAFFS_TRACE_ALWAYS, -+ (TSTR -+ ("Checkpoint read object %d parent %d type %d" -+ TCONT(" chunk %d Parent type, %d, not directory") -+ TENDSTR), cp->obj_id, cp->parent_id, -+ cp->variant_type, cp->hdr_chunk, -+ parent->variant_type)); -+ return 0; -+ } -+ yaffs_add_obj_to_dir(parent, obj); -+ } -+ -+ obj->hdr_chunk = cp->hdr_chunk; -+ obj->variant_type = cp->variant_type; -+ obj->deleted = cp->deleted; -+ obj->soft_del = cp->soft_del; -+ obj->unlinked = cp->unlinked; -+ obj->fake = cp->fake; -+ obj->rename_allowed = cp->rename_allowed; -+ obj->unlink_allowed = cp->unlink_allowed; -+ obj->serial = cp->serial; -+ obj->n_data_chunks = cp->n_data_chunks; -+ -+ if (obj->variant_type == YAFFS_OBJECT_TYPE_FILE) -+ obj->variant.file_variant.file_size = cp->size_or_equiv_obj; -+ else if (obj->variant_type == YAFFS_OBJECT_TYPE_HARDLINK) -+ obj->variant.hardlink_variant.equiv_id = cp->size_or_equiv_obj; -+ -+ if (obj->hdr_chunk > 0) -+ obj->lazy_loaded = 1; -+ return 1; -+} -+ -+static int yaffs2_checkpt_tnode_worker(struct yaffs_obj *in, -+ struct yaffs_tnode *tn, u32 level, -+ int chunk_offset) -+{ -+ int i; -+ struct yaffs_dev *dev = in->my_dev; -+ int ok = 1; -+ -+ if (tn) { -+ if (level > 0) { -+ -+ for (i = 0; i < YAFFS_NTNODES_INTERNAL && ok; i++) { -+ if (tn->internal[i]) { -+ ok = yaffs2_checkpt_tnode_worker(in, -+ tn-> -+ internal -+ [i], -+ level - -+ 1, -+ (chunk_offset -+ << -+ YAFFS_TNODES_INTERNAL_BITS) -+ + i); -+ } -+ } -+ } else if (level == 0) { -+ u32 base_offset = -+ chunk_offset << YAFFS_TNODES_LEVEL0_BITS; -+ ok = (yaffs2_checkpt_wr -+ (dev, &base_offset, -+ sizeof(base_offset)) == sizeof(base_offset)); -+ if (ok) -+ ok = (yaffs2_checkpt_wr -+ (dev, tn, -+ dev->tnode_size) == dev->tnode_size); -+ } -+ } -+ -+ return ok; -+ -+} -+ -+static int yaffs2_wr_checkpt_tnodes(struct yaffs_obj *obj) -+{ -+ u32 end_marker = ~0; -+ int ok = 1; -+ -+ if (obj->variant_type == YAFFS_OBJECT_TYPE_FILE) { -+ ok = yaffs2_checkpt_tnode_worker(obj, -+ obj->variant.file_variant.top, -+ obj->variant.file_variant. -+ top_level, 0); -+ if (ok) -+ ok = (yaffs2_checkpt_wr -+ (obj->my_dev, &end_marker, -+ sizeof(end_marker)) == sizeof(end_marker)); -+ } -+ -+ return ok ? 1 : 0; -+} -+ -+static int yaffs2_rd_checkpt_tnodes(struct yaffs_obj *obj) -+{ -+ u32 base_chunk; -+ int ok = 1; -+ struct yaffs_dev *dev = obj->my_dev; -+ struct yaffs_file_var *file_stuct_ptr = &obj->variant.file_variant; -+ struct yaffs_tnode *tn; -+ int nread = 0; -+ -+ ok = (yaffs2_checkpt_rd(dev, &base_chunk, sizeof(base_chunk)) == -+ sizeof(base_chunk)); -+ -+ while (ok && (~base_chunk)) { -+ nread++; -+ /* Read level 0 tnode */ -+ -+ tn = yaffs_get_tnode(dev); -+ if (tn) { -+ ok = (yaffs2_checkpt_rd(dev, tn, dev->tnode_size) == -+ dev->tnode_size); -+ } else { -+ ok = 0; -+ } -+ -+ if (tn && ok) -+ ok = yaffs_add_find_tnode_0(dev, -+ file_stuct_ptr, -+ base_chunk, tn) ? 1 : 0; -+ -+ if (ok) -+ ok = (yaffs2_checkpt_rd -+ (dev, &base_chunk, -+ sizeof(base_chunk)) == sizeof(base_chunk)); -+ -+ } -+ -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR("Checkpoint read tnodes %d records, last %d. ok %d" TENDSTR), -+ nread, base_chunk, ok)); -+ -+ return ok ? 1 : 0; -+} -+ -+static int yaffs2_wr_checkpt_objs(struct yaffs_dev *dev) -+{ -+ struct yaffs_obj *obj; -+ struct yaffs_checkpt_obj cp; -+ int i; -+ int ok = 1; -+ struct list_head *lh; -+ -+ /* Iterate through the objects in each hash entry, -+ * dumping them to the checkpointing stream. -+ */ -+ -+ for (i = 0; ok && i < YAFFS_NOBJECT_BUCKETS; i++) { -+ list_for_each(lh, &dev->obj_bucket[i].list) { -+ if (lh) { -+ obj = -+ list_entry(lh, struct yaffs_obj, hash_link); -+ if (!obj->defered_free) { -+ yaffs2_obj_checkpt_obj(&cp, obj); -+ cp.struct_type = sizeof(cp); -+ -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR -+ ("Checkpoint write object %d parent %d type %d chunk %d obj addr %p" -+ TENDSTR), cp.obj_id, cp.parent_id, -+ cp.variant_type, cp.hdr_chunk, obj)); -+ -+ ok = (yaffs2_checkpt_wr -+ (dev, &cp, -+ sizeof(cp)) == sizeof(cp)); -+ -+ if (ok -+ && obj->variant_type == -+ YAFFS_OBJECT_TYPE_FILE) -+ ok = yaffs2_wr_checkpt_tnodes -+ (obj); -+ } -+ } -+ } -+ } -+ -+ /* Dump end of list */ -+ memset(&cp, 0xFF, sizeof(struct yaffs_checkpt_obj)); -+ cp.struct_type = sizeof(cp); -+ -+ if (ok) -+ ok = (yaffs2_checkpt_wr(dev, &cp, sizeof(cp)) == sizeof(cp)); -+ -+ return ok ? 1 : 0; -+} -+ -+static int yaffs2_rd_checkpt_objs(struct yaffs_dev *dev) -+{ -+ struct yaffs_obj *obj; -+ struct yaffs_checkpt_obj cp; -+ int ok = 1; -+ int done = 0; -+ struct yaffs_obj *hard_list = NULL; -+ -+ while (ok && !done) { -+ ok = (yaffs2_checkpt_rd(dev, &cp, sizeof(cp)) == sizeof(cp)); -+ if (cp.struct_type != sizeof(cp)) { -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR("struct size %d instead of %d ok %d" TENDSTR), -+ cp.struct_type, (int)sizeof(cp), ok)); -+ ok = 0; -+ } -+ -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR -+ ("Checkpoint read object %d parent %d type %d chunk %d " -+ TENDSTR), cp.obj_id, cp.parent_id, cp.variant_type, -+ cp.hdr_chunk)); -+ -+ if (ok && cp.obj_id == ~0) { -+ done = 1; -+ } else if (ok) { -+ obj = -+ yaffs_find_or_create_by_number(dev, cp.obj_id, -+ cp.variant_type); -+ if (obj) { -+ ok = taffs2_checkpt_obj_to_obj(obj, &cp); -+ if (!ok) -+ break; -+ if (obj->variant_type == YAFFS_OBJECT_TYPE_FILE) { -+ ok = yaffs2_rd_checkpt_tnodes(obj); -+ } else if (obj->variant_type == -+ YAFFS_OBJECT_TYPE_HARDLINK) { -+ obj->hard_links.next = -+ (struct list_head *)hard_list; -+ hard_list = obj; -+ } -+ } else { -+ ok = 0; -+ } -+ } -+ } -+ -+ if (ok) -+ yaffs_link_fixup(dev, hard_list); -+ -+ return ok ? 1 : 0; -+} -+ -+static int yaffs2_wr_checkpt_sum(struct yaffs_dev *dev) -+{ -+ u32 checkpt_sum; -+ int ok; -+ -+ yaffs2_get_checkpt_sum(dev, &checkpt_sum); -+ -+ ok = (yaffs2_checkpt_wr(dev, &checkpt_sum, sizeof(checkpt_sum)) == -+ sizeof(checkpt_sum)); -+ -+ if (!ok) -+ return 0; -+ -+ return 1; -+} -+ -+static int yaffs2_rd_checkpt_sum(struct yaffs_dev *dev) -+{ -+ u32 checkpt_sum0; -+ u32 checkpt_sum1; -+ int ok; -+ -+ yaffs2_get_checkpt_sum(dev, &checkpt_sum0); -+ -+ ok = (yaffs2_checkpt_rd(dev, &checkpt_sum1, sizeof(checkpt_sum1)) == -+ sizeof(checkpt_sum1)); -+ -+ if (!ok) -+ return 0; -+ -+ if (checkpt_sum0 != checkpt_sum1) -+ return 0; -+ -+ return 1; -+} -+ -+static int yaffs2_wr_checkpt_data(struct yaffs_dev *dev) -+{ -+ int ok = 1; -+ -+ if (!yaffs2_checkpt_required(dev)) { -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR("skipping checkpoint write" TENDSTR))); -+ ok = 0; -+ } -+ -+ if (ok) -+ ok = yaffs2_checkpt_open(dev, 1); -+ -+ if (ok) { -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR("write checkpoint validity" TENDSTR))); -+ ok = yaffs2_wr_checkpt_validity_marker(dev, 1); -+ } -+ if (ok) { -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR("write checkpoint device" TENDSTR))); -+ ok = yaffs2_wr_checkpt_dev(dev); -+ } -+ if (ok) { -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR("write checkpoint objects" TENDSTR))); -+ ok = yaffs2_wr_checkpt_objs(dev); -+ } -+ if (ok) { -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR("write checkpoint validity" TENDSTR))); -+ ok = yaffs2_wr_checkpt_validity_marker(dev, 0); -+ } -+ -+ if (ok) -+ ok = yaffs2_wr_checkpt_sum(dev); -+ -+ if (!yaffs_checkpt_close(dev)) -+ ok = 0; -+ -+ if (ok) -+ dev->is_checkpointed = 1; -+ else -+ dev->is_checkpointed = 0; -+ -+ return dev->is_checkpointed; -+} -+ -+static int yaffs2_rd_checkpt_data(struct yaffs_dev *dev) -+{ -+ int ok = 1; -+ -+ if (!dev->param.is_yaffs2) -+ ok = 0; -+ -+ if (ok && dev->param.skip_checkpt_rd) { -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR("skipping checkpoint read" TENDSTR))); -+ ok = 0; -+ } -+ -+ if (ok) -+ ok = yaffs2_checkpt_open(dev, 0); /* open for read */ -+ -+ if (ok) { -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR("read checkpoint validity" TENDSTR))); -+ ok = yaffs2_rd_checkpt_validity_marker(dev, 1); -+ } -+ if (ok) { -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR("read checkpoint device" TENDSTR))); -+ ok = yaffs2_rd_checkpt_dev(dev); -+ } -+ if (ok) { -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR("read checkpoint objects" TENDSTR))); -+ ok = yaffs2_rd_checkpt_objs(dev); -+ } -+ if (ok) { -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR("read checkpoint validity" TENDSTR))); -+ ok = yaffs2_rd_checkpt_validity_marker(dev, 0); -+ } -+ -+ if (ok) { -+ ok = yaffs2_rd_checkpt_sum(dev); -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR("read checkpoint checksum %d" TENDSTR), ok)); -+ } -+ -+ if (!yaffs_checkpt_close(dev)) -+ ok = 0; -+ -+ if (ok) -+ dev->is_checkpointed = 1; -+ else -+ dev->is_checkpointed = 0; -+ -+ return ok ? 1 : 0; -+ -+} -+ -+void yaffs2_checkpt_invalidate(struct yaffs_dev *dev) -+{ -+ if (dev->is_checkpointed || dev->blocks_in_checkpt > 0) { -+ dev->is_checkpointed = 0; -+ yaffs2_checkpt_invalidate_stream(dev); -+ } -+ if (dev->param.sb_dirty_fn) -+ dev->param.sb_dirty_fn(dev); -+} -+ -+int yaffs_checkpoint_save(struct yaffs_dev *dev) -+{ -+ -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR("save entry: is_checkpointed %d" TENDSTR), -+ dev->is_checkpointed)); -+ -+ yaffs_verify_objects(dev); -+ yaffs_verify_blocks(dev); -+ yaffs_verify_free_chunks(dev); -+ -+ if (!dev->is_checkpointed) { -+ yaffs2_checkpt_invalidate(dev); -+ yaffs2_wr_checkpt_data(dev); -+ } -+ -+ T(YAFFS_TRACE_CHECKPOINT | YAFFS_TRACE_MOUNT, -+ (TSTR("save exit: is_checkpointed %d" TENDSTR), -+ dev->is_checkpointed)); -+ -+ return dev->is_checkpointed; -+} -+ -+int yaffs2_checkpt_restore(struct yaffs_dev *dev) -+{ -+ int retval; -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR("restore entry: is_checkpointed %d" TENDSTR), -+ dev->is_checkpointed)); -+ -+ retval = yaffs2_rd_checkpt_data(dev); -+ -+ if (dev->is_checkpointed) { -+ yaffs_verify_objects(dev); -+ yaffs_verify_blocks(dev); -+ yaffs_verify_free_chunks(dev); -+ } -+ -+ T(YAFFS_TRACE_CHECKPOINT, -+ (TSTR("restore exit: is_checkpointed %d" TENDSTR), -+ dev->is_checkpointed)); -+ -+ return retval; -+} -+ -+int yaffs2_handle_hole(struct yaffs_obj *obj, loff_t new_size) -+{ -+ /* if new_size > old_file_size. -+ * We're going to be writing a hole. -+ * If the hole is small then write zeros otherwise write a start of hole marker. -+ */ -+ -+ loff_t old_file_size; -+ int increase; -+ int small_hole; -+ int result = YAFFS_OK; -+ struct yaffs_dev *dev = NULL; -+ -+ u8 *local_buffer = NULL; -+ -+ int small_increase_ok = 0; -+ -+ if (!obj) -+ return YAFFS_FAIL; -+ -+ if (obj->variant_type != YAFFS_OBJECT_TYPE_FILE) -+ return YAFFS_FAIL; -+ -+ dev = obj->my_dev; -+ -+ /* Bail out if not yaffs2 mode */ -+ if (!dev->param.is_yaffs2) -+ return YAFFS_OK; -+ -+ old_file_size = obj->variant.file_variant.file_size; -+ -+ if (new_size <= old_file_size) -+ return YAFFS_OK; -+ -+ increase = new_size - old_file_size; -+ -+ if (increase < YAFFS_SMALL_HOLE_THRESHOLD * dev->data_bytes_per_chunk && -+ yaffs_check_alloc_available(dev, YAFFS_SMALL_HOLE_THRESHOLD + 1)) -+ small_hole = 1; -+ else -+ small_hole = 0; -+ -+ if (small_hole) -+ local_buffer = yaffs_get_temp_buffer(dev, __LINE__); -+ -+ if (local_buffer) { -+ /* fill hole with zero bytes */ -+ int pos = old_file_size; -+ int this_write; -+ int written; -+ memset(local_buffer, 0, dev->data_bytes_per_chunk); -+ small_increase_ok = 1; -+ -+ while (increase > 0 && small_increase_ok) { -+ this_write = increase; -+ if (this_write > dev->data_bytes_per_chunk) -+ this_write = dev->data_bytes_per_chunk; -+ written = -+ yaffs_do_file_wr(obj, local_buffer, pos, this_write, -+ 0); -+ if (written == this_write) { -+ pos += this_write; -+ increase -= this_write; -+ } else { -+ small_increase_ok = 0; -+ } -+ } -+ -+ yaffs_release_temp_buffer(dev, local_buffer, __LINE__); -+ -+ /* If we were out of space then reverse any chunks we've added */ -+ if (!small_increase_ok) -+ yaffs_resize_file_down(obj, old_file_size); -+ } -+ -+ if (!small_increase_ok && -+ obj->parent && -+ obj->parent->obj_id != YAFFS_OBJECTID_UNLINKED && -+ obj->parent->obj_id != YAFFS_OBJECTID_DELETED) { -+ /* Write a hole start header with the old file size */ -+ yaffs_update_oh(obj, NULL, 0, 1, 0, NULL); -+ } -+ -+ return result; -+ -+} -+ -+struct yaffs_block_index { -+ int seq; -+ int block; -+}; -+ -+static int yaffs2_ybicmp(const void *a, const void *b) -+{ -+ int aseq = ((struct yaffs_block_index *)a)->seq; -+ int bseq = ((struct yaffs_block_index *)b)->seq; -+ int ablock = ((struct yaffs_block_index *)a)->block; -+ int bblock = ((struct yaffs_block_index *)b)->block; -+ if (aseq == bseq) -+ return ablock - bblock; -+ else -+ return aseq - bseq; -+} -+ -+int yaffs2_scan_backwards(struct yaffs_dev *dev) -+{ -+ struct yaffs_ext_tags tags; -+ int blk; -+ int block_iter; -+ int start_iter; -+ int end_iter; -+ int n_to_scan = 0; -+ -+ int chunk; -+ int result; -+ int c; -+ int deleted; -+ enum yaffs_block_state state; -+ struct yaffs_obj *hard_list = NULL; -+ struct yaffs_block_info *bi; -+ u32 seq_number; -+ struct yaffs_obj_hdr *oh; -+ struct yaffs_obj *in; -+ struct yaffs_obj *parent; -+ int n_blocks = dev->internal_end_block - dev->internal_start_block + 1; -+ int is_unlinked; -+ u8 *chunk_data; -+ -+ int file_size; -+ int is_shrink; -+ int found_chunks; -+ int equiv_id; -+ int alloc_failed = 0; -+ -+ struct yaffs_block_index *block_index = NULL; -+ int alt_block_index = 0; -+ -+ T(YAFFS_TRACE_SCAN, -+ (TSTR -+ ("yaffs2_scan_backwards starts intstartblk %d intendblk %d..." -+ TENDSTR), dev->internal_start_block, dev->internal_end_block)); -+ -+ dev->seq_number = YAFFS_LOWEST_SEQUENCE_NUMBER; -+ -+ block_index = YMALLOC(n_blocks * sizeof(struct yaffs_block_index)); -+ -+ if (!block_index) { -+ block_index = -+ YMALLOC_ALT(n_blocks * sizeof(struct yaffs_block_index)); -+ alt_block_index = 1; -+ } -+ -+ if (!block_index) { -+ T(YAFFS_TRACE_SCAN, -+ (TSTR -+ ("yaffs2_scan_backwards() could not allocate block index!" -+ TENDSTR))); -+ return YAFFS_FAIL; -+ } -+ -+ dev->blocks_in_checkpt = 0; -+ -+ chunk_data = yaffs_get_temp_buffer(dev, __LINE__); -+ -+ /* Scan all the blocks to determine their state */ -+ bi = dev->block_info; -+ for (blk = dev->internal_start_block; blk <= dev->internal_end_block; -+ blk++) { -+ yaffs_clear_chunk_bits(dev, blk); -+ bi->pages_in_use = 0; -+ bi->soft_del_pages = 0; -+ -+ yaffs_query_init_block_state(dev, blk, &state, &seq_number); -+ -+ bi->block_state = state; -+ bi->seq_number = seq_number; -+ -+ if (bi->seq_number == YAFFS_SEQUENCE_CHECKPOINT_DATA) -+ bi->block_state = state = YAFFS_BLOCK_STATE_CHECKPOINT; -+ if (bi->seq_number == YAFFS_SEQUENCE_BAD_BLOCK) -+ bi->block_state = state = YAFFS_BLOCK_STATE_DEAD; -+ -+ T(YAFFS_TRACE_SCAN_DEBUG, -+ (TSTR("Block scanning block %d state %d seq %d" TENDSTR), blk, -+ state, seq_number)); -+ -+ if (state == YAFFS_BLOCK_STATE_CHECKPOINT) { -+ dev->blocks_in_checkpt++; -+ -+ } else if (state == YAFFS_BLOCK_STATE_DEAD) { -+ T(YAFFS_TRACE_BAD_BLOCKS, -+ (TSTR("block %d is bad" TENDSTR), blk)); -+ } else if (state == YAFFS_BLOCK_STATE_EMPTY) { -+ T(YAFFS_TRACE_SCAN_DEBUG, -+ (TSTR("Block empty " TENDSTR))); -+ dev->n_erased_blocks++; -+ dev->n_free_chunks += dev->param.chunks_per_block; -+ } else if (state == YAFFS_BLOCK_STATE_NEEDS_SCANNING) { -+ -+ /* Determine the highest sequence number */ -+ if (seq_number >= YAFFS_LOWEST_SEQUENCE_NUMBER && -+ seq_number < YAFFS_HIGHEST_SEQUENCE_NUMBER) { -+ -+ block_index[n_to_scan].seq = seq_number; -+ block_index[n_to_scan].block = blk; -+ -+ n_to_scan++; -+ -+ if (seq_number >= dev->seq_number) -+ dev->seq_number = seq_number; -+ } else { -+ /* TODO: Nasty sequence number! */ -+ T(YAFFS_TRACE_SCAN, -+ (TSTR -+ ("Block scanning block %d has bad sequence number %d" -+ TENDSTR), blk, seq_number)); -+ -+ } -+ } -+ bi++; -+ } -+ -+ T(YAFFS_TRACE_SCAN, -+ (TSTR("%d blocks to be sorted..." TENDSTR), n_to_scan)); -+ -+ YYIELD(); -+ -+ /* Sort the blocks by sequence number */ -+ yaffs_sort(block_index, n_to_scan, sizeof(struct yaffs_block_index), -+ yaffs2_ybicmp); -+ -+ YYIELD(); -+ -+ T(YAFFS_TRACE_SCAN, (TSTR("...done" TENDSTR))); -+ -+ /* Now scan the blocks looking at the data. */ -+ start_iter = 0; -+ end_iter = n_to_scan - 1; -+ T(YAFFS_TRACE_SCAN_DEBUG, -+ (TSTR("%d blocks to be scanned" TENDSTR), n_to_scan)); -+ -+ /* For each block.... backwards */ -+ for (block_iter = end_iter; !alloc_failed && block_iter >= start_iter; -+ block_iter--) { -+ /* Cooperative multitasking! This loop can run for so -+ long that watchdog timers expire. */ -+ YYIELD(); -+ -+ /* get the block to scan in the correct order */ -+ blk = block_index[block_iter].block; -+ -+ bi = yaffs_get_block_info(dev, blk); -+ -+ state = bi->block_state; -+ -+ deleted = 0; -+ -+ /* For each chunk in each block that needs scanning.... */ -+ found_chunks = 0; -+ for (c = dev->param.chunks_per_block - 1; -+ !alloc_failed && c >= 0 && -+ (state == YAFFS_BLOCK_STATE_NEEDS_SCANNING || -+ state == YAFFS_BLOCK_STATE_ALLOCATING); c--) { -+ /* Scan backwards... -+ * Read the tags and decide what to do -+ */ -+ -+ chunk = blk * dev->param.chunks_per_block + c; -+ -+ result = yaffs_rd_chunk_tags_nand(dev, chunk, NULL, -+ &tags); -+ -+ /* Let's have a good look at this chunk... */ -+ -+ if (!tags.chunk_used) { -+ /* An unassigned chunk in the block. -+ * If there are used chunks after this one, then -+ * it is a chunk that was skipped due to failing the erased -+ * check. Just skip it so that it can be deleted. -+ * But, more typically, We get here when this is an unallocated -+ * chunk and his means that either the block is empty or -+ * this is the one being allocated from -+ */ -+ -+ if (found_chunks) { -+ /* This is a chunk that was skipped due to failing the erased check */ -+ } else if (c == 0) { -+ /* We're looking at the first chunk in the block so the block is unused */ -+ state = YAFFS_BLOCK_STATE_EMPTY; -+ dev->n_erased_blocks++; -+ } else { -+ if (state == -+ YAFFS_BLOCK_STATE_NEEDS_SCANNING -+ || state == -+ YAFFS_BLOCK_STATE_ALLOCATING) { -+ if (dev->seq_number == -+ bi->seq_number) { -+ /* this is the block being allocated from */ -+ -+ T(YAFFS_TRACE_SCAN, -+ (TSTR -+ (" Allocating from %d %d" -+ TENDSTR), blk, c)); -+ -+ state = -+ YAFFS_BLOCK_STATE_ALLOCATING; -+ dev->alloc_block = blk; -+ dev->alloc_page = c; -+ dev-> -+ alloc_block_finder = -+ blk; -+ } else { -+ /* This is a partially written block that is not -+ * the current allocation block. -+ */ -+ -+ T(YAFFS_TRACE_SCAN, -+ (TSTR -+ ("Partially written block %d detected" -+ TENDSTR), blk)); -+ } -+ } -+ } -+ -+ dev->n_free_chunks++; -+ -+ } else if (tags.ecc_result == YAFFS_ECC_RESULT_UNFIXED) { -+ T(YAFFS_TRACE_SCAN, -+ (TSTR -+ (" Unfixed ECC in chunk(%d:%d), chunk ignored" -+ TENDSTR), blk, c)); -+ -+ dev->n_free_chunks++; -+ -+ } else if (tags.obj_id > YAFFS_MAX_OBJECT_ID || -+ tags.chunk_id > YAFFS_MAX_CHUNK_ID || -+ (tags.chunk_id > 0 -+ && tags.n_bytes > dev->data_bytes_per_chunk) -+ || tags.seq_number != bi->seq_number) { -+ T(YAFFS_TRACE_SCAN, -+ (TSTR -+ ("Chunk (%d:%d) with bad tags:obj = %d, chunk_id = %d, n_bytes = %d, ignored" -+ TENDSTR), blk, c, tags.obj_id, -+ tags.chunk_id, tags.n_bytes)); -+ -+ dev->n_free_chunks++; -+ -+ } else if (tags.chunk_id > 0) { -+ /* chunk_id > 0 so it is a data chunk... */ -+ unsigned int endpos; -+ u32 chunk_base = -+ (tags.chunk_id - -+ 1) * dev->data_bytes_per_chunk; -+ -+ found_chunks = 1; -+ -+ yaffs_set_chunk_bit(dev, blk, c); -+ bi->pages_in_use++; -+ -+ in = yaffs_find_or_create_by_number(dev, -+ tags.obj_id, -+ YAFFS_OBJECT_TYPE_FILE); -+ if (!in) { -+ /* Out of memory */ -+ alloc_failed = 1; -+ } -+ -+ if (in && -+ in->variant_type == YAFFS_OBJECT_TYPE_FILE -+ && chunk_base < -+ in->variant.file_variant.shrink_size) { -+ /* This has not been invalidated by a resize */ -+ if (!yaffs_put_chunk_in_file -+ (in, tags.chunk_id, chunk, -1)) { -+ alloc_failed = 1; -+ } -+ -+ /* File size is calculated by looking at the data chunks if we have not -+ * seen an object header yet. Stop this practice once we find an object header. -+ */ -+ endpos = chunk_base + tags.n_bytes; -+ -+ if (!in->valid && /* have not got an object header yet */ -+ in->variant.file_variant. -+ scanned_size < endpos) { -+ in->variant.file_variant. -+ scanned_size = endpos; -+ in->variant.file_variant. -+ file_size = endpos; -+ } -+ -+ } else if (in) { -+ /* This chunk has been invalidated by a resize, or a past file deletion -+ * so delete the chunk*/ -+ yaffs_chunk_del(dev, chunk, 1, -+ __LINE__); -+ -+ } -+ } else { -+ /* chunk_id == 0, so it is an ObjectHeader. -+ * Thus, we read in the object header and make the object -+ */ -+ found_chunks = 1; -+ -+ yaffs_set_chunk_bit(dev, blk, c); -+ bi->pages_in_use++; -+ -+ oh = NULL; -+ in = NULL; -+ -+ if (tags.extra_available) { -+ in = yaffs_find_or_create_by_number(dev, -+ tags. -+ obj_id, -+ tags. -+ extra_obj_type); -+ if (!in) -+ alloc_failed = 1; -+ } -+ -+ if (!in || -+ (!in->valid && dev->param.disable_lazy_load) -+ || tags.extra_shadows || (!in->valid -+ && (tags.obj_id == -+ YAFFS_OBJECTID_ROOT -+ || tags. -+ obj_id == -+ YAFFS_OBJECTID_LOSTNFOUND))) -+ { -+ -+ /* If we don't have valid info then we need to read the chunk -+ * TODO In future we can probably defer reading the chunk and -+ * living with invalid data until needed. -+ */ -+ -+ result = yaffs_rd_chunk_tags_nand(dev, -+ chunk, -+ chunk_data, -+ NULL); -+ -+ oh = (struct yaffs_obj_hdr *)chunk_data; -+ -+ if (dev->param.inband_tags) { -+ /* Fix up the header if they got corrupted by inband tags */ -+ oh->shadows_obj = -+ oh->inband_shadowed_obj_id; -+ oh->is_shrink = -+ oh->inband_is_shrink; -+ } -+ -+ if (!in) { -+ in = yaffs_find_or_create_by_number(dev, tags.obj_id, oh->type); -+ if (!in) -+ alloc_failed = 1; -+ } -+ -+ } -+ -+ if (!in) { -+ /* TODO Hoosterman we have a problem! */ -+ T(YAFFS_TRACE_ERROR, -+ (TSTR -+ ("yaffs tragedy: Could not make object for object %d at chunk %d during scan" -+ TENDSTR), tags.obj_id, chunk)); -+ continue; -+ } -+ -+ if (in->valid) { -+ /* We have already filled this one. -+ * We have a duplicate that will be discarded, but -+ * we first have to suck out resize info if it is a file. -+ */ -+ -+ if ((in->variant_type == -+ YAFFS_OBJECT_TYPE_FILE) && ((oh -+ && -+ oh-> -+ type -+ == -+ YAFFS_OBJECT_TYPE_FILE) -+ || -+ (tags. -+ extra_available -+ && -+ tags. -+ extra_obj_type -+ == -+ YAFFS_OBJECT_TYPE_FILE))) -+ { -+ u32 this_size = -+ (oh) ? oh-> -+ file_size : -+ tags.extra_length; -+ u32 parent_obj_id = -+ (oh) ? oh->parent_obj_id : -+ tags.extra_parent_id; -+ -+ is_shrink = -+ (oh) ? oh-> -+ is_shrink : -+ tags.extra_is_shrink; -+ -+ /* If it is deleted (unlinked at start also means deleted) -+ * we treat the file size as being zeroed at this point. -+ */ -+ if (parent_obj_id == -+ YAFFS_OBJECTID_DELETED -+ || parent_obj_id == -+ YAFFS_OBJECTID_UNLINKED) { -+ this_size = 0; -+ is_shrink = 1; -+ } -+ -+ if (is_shrink -+ && in->variant.file_variant. -+ shrink_size > this_size) -+ in->variant. -+ file_variant. -+ shrink_size = -+ this_size; -+ -+ if (is_shrink) -+ bi->has_shrink_hdr = 1; -+ -+ } -+ /* Use existing - destroy this one. */ -+ yaffs_chunk_del(dev, chunk, 1, -+ __LINE__); -+ -+ } -+ -+ if (!in->valid && in->variant_type != -+ (oh ? oh->type : tags.extra_obj_type)) -+ T(YAFFS_TRACE_ERROR, -+ (TSTR -+ ("yaffs tragedy: Bad object type, " -+ TCONT -+ ("%d != %d, for object %d at chunk ") -+ TCONT("%d during scan") -+ TENDSTR), oh ? -+ oh->type : tags.extra_obj_type, -+ in->variant_type, tags.obj_id, -+ chunk)); -+ -+ if (!in->valid && -+ (tags.obj_id == YAFFS_OBJECTID_ROOT || -+ tags.obj_id == -+ YAFFS_OBJECTID_LOSTNFOUND)) { -+ /* We only load some info, don't fiddle with directory structure */ -+ in->valid = 1; -+ -+ if (oh) { -+ -+ in->yst_mode = oh->yst_mode; -+ yaffs_load_attribs(in, oh); -+ in->lazy_loaded = 0; -+ } else { -+ in->lazy_loaded = 1; -+ } -+ in->hdr_chunk = chunk; -+ -+ } else if (!in->valid) { -+ /* we need to load this info */ -+ -+ in->valid = 1; -+ in->hdr_chunk = chunk; -+ -+ if (oh) { -+ in->variant_type = oh->type; -+ -+ in->yst_mode = oh->yst_mode; -+ yaffs_load_attribs(in, oh); -+ -+ if (oh->shadows_obj > 0) -+ yaffs_handle_shadowed_obj -+ (dev, -+ oh->shadows_obj, -+ 1); -+ -+ yaffs_set_obj_name_from_oh(in, -+ oh); -+ parent = -+ yaffs_find_or_create_by_number -+ (dev, oh->parent_obj_id, -+ YAFFS_OBJECT_TYPE_DIRECTORY); -+ -+ file_size = oh->file_size; -+ is_shrink = oh->is_shrink; -+ equiv_id = oh->equiv_id; -+ -+ } else { -+ in->variant_type = -+ tags.extra_obj_type; -+ parent = -+ yaffs_find_or_create_by_number -+ (dev, tags.extra_parent_id, -+ YAFFS_OBJECT_TYPE_DIRECTORY); -+ file_size = tags.extra_length; -+ is_shrink = -+ tags.extra_is_shrink; -+ equiv_id = tags.extra_equiv_id; -+ in->lazy_loaded = 1; -+ -+ } -+ in->dirty = 0; -+ -+ if (!parent) -+ alloc_failed = 1; -+ -+ /* directory stuff... -+ * hook up to parent -+ */ -+ -+ if (parent && parent->variant_type == -+ YAFFS_OBJECT_TYPE_UNKNOWN) { -+ /* Set up as a directory */ -+ parent->variant_type = -+ YAFFS_OBJECT_TYPE_DIRECTORY; -+ INIT_LIST_HEAD(&parent-> -+ variant.dir_variant.children); -+ } else if (!parent -+ || parent->variant_type != -+ YAFFS_OBJECT_TYPE_DIRECTORY) { -+ /* Hoosterman, another problem.... -+ * We're trying to use a non-directory as a directory -+ */ -+ -+ T(YAFFS_TRACE_ERROR, -+ (TSTR -+ ("yaffs tragedy: attempting to use non-directory as a directory in scan. Put in lost+found." -+ TENDSTR))); -+ parent = dev->lost_n_found; -+ } -+ -+ yaffs_add_obj_to_dir(parent, in); -+ -+ is_unlinked = (parent == dev->del_dir) -+ || (parent == dev->unlinked_dir); -+ -+ if (is_shrink) { -+ /* Mark the block as having a shrink header */ -+ bi->has_shrink_hdr = 1; -+ } -+ -+ /* Note re hardlinks. -+ * Since we might scan a hardlink before its equivalent object is scanned -+ * we put them all in a list. -+ * After scanning is complete, we should have all the objects, so we run -+ * through this list and fix up all the chains. -+ */ -+ -+ switch (in->variant_type) { -+ case YAFFS_OBJECT_TYPE_UNKNOWN: -+ /* Todo got a problem */ -+ break; -+ case YAFFS_OBJECT_TYPE_FILE: -+ -+ if (in->variant. -+ file_variant.scanned_size < -+ file_size) { -+ /* This covers the case where the file size is greater -+ * than where the data is -+ * This will happen if the file is resized to be larger -+ * than its current data extents. -+ */ -+ in->variant. -+ file_variant. -+ file_size = -+ file_size; -+ in->variant. -+ file_variant. -+ scanned_size = -+ file_size; -+ } -+ -+ if (in->variant.file_variant. -+ shrink_size > file_size) -+ in->variant. -+ file_variant. -+ shrink_size = -+ file_size; -+ -+ break; -+ case YAFFS_OBJECT_TYPE_HARDLINK: -+ if (!is_unlinked) { -+ in->variant. -+ hardlink_variant. -+ equiv_id = equiv_id; -+ in->hard_links.next = -+ (struct list_head *) -+ hard_list; -+ hard_list = in; -+ } -+ break; -+ case YAFFS_OBJECT_TYPE_DIRECTORY: -+ /* Do nothing */ -+ break; -+ case YAFFS_OBJECT_TYPE_SPECIAL: -+ /* Do nothing */ -+ break; -+ case YAFFS_OBJECT_TYPE_SYMLINK: -+ if (oh) { -+ in->variant. -+ symlink_variant. -+ alias = -+ yaffs_clone_str(oh-> -+ alias); -+ if (!in->variant. -+ symlink_variant. -+ alias) -+ alloc_failed = -+ 1; -+ } -+ break; -+ } -+ -+ } -+ -+ } -+ -+ } /* End of scanning for each chunk */ -+ -+ if (state == YAFFS_BLOCK_STATE_NEEDS_SCANNING) { -+ /* If we got this far while scanning, then the block is fully allocated. */ -+ state = YAFFS_BLOCK_STATE_FULL; -+ } -+ -+ bi->block_state = state; -+ -+ /* Now let's see if it was dirty */ -+ if (bi->pages_in_use == 0 && -+ !bi->has_shrink_hdr && -+ bi->block_state == YAFFS_BLOCK_STATE_FULL) { -+ yaffs_block_became_dirty(dev, blk); -+ } -+ -+ } -+ -+ yaffs_skip_rest_of_block(dev); -+ -+ if (alt_block_index) -+ YFREE_ALT(block_index); -+ else -+ YFREE(block_index); -+ -+ /* Ok, we've done all the scanning. -+ * Fix up the hard link chains. -+ * We should now have scanned all the objects, now it's time to add these -+ * hardlinks. -+ */ -+ yaffs_link_fixup(dev, hard_list); -+ -+ yaffs_release_temp_buffer(dev, chunk_data, __LINE__); -+ -+ if (alloc_failed) -+ return YAFFS_FAIL; -+ -+ T(YAFFS_TRACE_SCAN, (TSTR("yaffs2_scan_backwards ends" TENDSTR))); -+ -+ return YAFFS_OK; -+} -diff -Nur linux-2.6.36.orig/fs/yaffs2/yaffs_yaffs2.h linux-2.6.36/fs/yaffs2/yaffs_yaffs2.h ---- linux-2.6.36.orig/fs/yaffs2/yaffs_yaffs2.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yaffs_yaffs2.h 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,39 @@ -+/* -+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU Lesser General Public License version 2.1 as -+ * published by the Free Software Foundation. -+ * -+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. -+ */ -+ -+#ifndef __YAFFS_YAFFS2_H__ -+#define __YAFFS_YAFFS2_H__ -+ -+#include "yaffs_guts.h" -+ -+void yaffs_calc_oldest_dirty_seq(struct yaffs_dev *dev); -+void yaffs2_find_oldest_dirty_seq(struct yaffs_dev *dev); -+void yaffs2_clear_oldest_dirty_seq(struct yaffs_dev *dev, -+ struct yaffs_block_info *bi); -+void yaffs2_update_oldest_dirty_seq(struct yaffs_dev *dev, unsigned block_no, -+ struct yaffs_block_info *bi); -+int yaffs_block_ok_for_gc(struct yaffs_dev *dev, struct yaffs_block_info *bi); -+u32 yaffs2_find_refresh_block(struct yaffs_dev *dev); -+int yaffs2_checkpt_required(struct yaffs_dev *dev); -+int yaffs_calc_checkpt_blocks_required(struct yaffs_dev *dev); -+ -+void yaffs2_checkpt_invalidate(struct yaffs_dev *dev); -+int yaffs2_checkpt_save(struct yaffs_dev *dev); -+int yaffs2_checkpt_restore(struct yaffs_dev *dev); -+ -+int yaffs2_handle_hole(struct yaffs_obj *obj, loff_t new_size); -+int yaffs2_scan_backwards(struct yaffs_dev *dev); -+ -+#endif -diff -Nur linux-2.6.36.orig/fs/yaffs2/yportenv.h linux-2.6.36/fs/yaffs2/yportenv.h ---- linux-2.6.36.orig/fs/yaffs2/yportenv.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.36/fs/yaffs2/yportenv.h 2011-01-10 19:29:29.000000000 +0100 -@@ -0,0 +1,339 @@ -+/* -+ * YAFFS: Yet another Flash File System . A NAND-flash specific file system. -+ * -+ * Copyright (C) 2002-2010 Aleph One Ltd. -+ * for Toby Churchill Ltd and Brightstar Engineering -+ * -+ * Created by Charles Manning -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU Lesser General Public License version 2.1 as -+ * published by the Free Software Foundation. -+ * -+ * Note: Only YAFFS headers are LGPL, YAFFS C code is covered by GPL. -+ */ -+ -+#ifndef __YPORTENV_H__ -+#define __YPORTENV_H__ -+ -+/* -+ * Define the MTD version in terms of Linux Kernel versions -+ * This allows yaffs to be used independantly of the kernel -+ * as well as with it. -+ */ -+ -+#define MTD_VERSION(a, b, c) (((a) << 16) + ((b) << 8) + (c)) -+ -+#if defined CONFIG_YAFFS_WINCE -+ -+#include "ywinceenv.h" -+ -+#elif defined __KERNEL__ -+ -+#include "moduleconfig.h" -+ -+/* Linux kernel */ -+ -+#include -+#define MTD_VERSION_CODE LINUX_VERSION_CODE -+ -+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19)) -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define YCHAR char -+#define YUCHAR unsigned char -+#define _Y(x) x -+#define yaffs_strcat(a, b) strcat(a, b) -+#define yaffs_strcpy(a, b) strcpy(a, b) -+#define yaffs_strncpy(a, b, c) strncpy(a, b, c) -+#define yaffs_strncmp(a, b, c) strncmp(a, b, c) -+#define yaffs_strnlen(s,m) strnlen(s,m) -+#define yaffs_sprintf sprintf -+#define yaffs_toupper(a) toupper(a) -+#define yaffs_sort(base, n, sz, cmp_fn) sort(base, n, sz, cmp_fn, NULL) -+ -+#define Y_INLINE __inline__ -+ -+#define YAFFS_LOSTNFOUND_NAME "lost+found" -+#define YAFFS_LOSTNFOUND_PREFIX "obj" -+ -+/* #define YPRINTF(x) printk x */ -+#define YMALLOC(x) kmalloc(x, GFP_NOFS) -+#define YFREE(x) kfree(x) -+#define YMALLOC_ALT(x) vmalloc(x) -+#define YFREE_ALT(x) vfree(x) -+#define YMALLOC_DMA(x) YMALLOC(x) -+ -+#define YYIELD() schedule() -+#define Y_DUMP_STACK() dump_stack() -+ -+#define YAFFS_ROOT_MODE 0755 -+#define YAFFS_LOSTNFOUND_MODE 0700 -+ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0)) -+#define Y_CURRENT_TIME CURRENT_TIME.tv_sec -+#define Y_TIME_CONVERT(x) (x).tv_sec -+#else -+#define Y_CURRENT_TIME CURRENT_TIME -+#define Y_TIME_CONVERT(x) (x) -+#endif -+ -+#define yaffs_sum_cmp(x, y) ((x) == (y)) -+#define yaffs_strcmp(a, b) strcmp(a, b) -+ -+#define TENDSTR "\n" -+#define TSTR(x) KERN_DEBUG x -+#define TCONT(x) x -+#define TOUT(p) printk p -+ -+#define compile_time_assertion(assertion) \ -+ ({ int x = __builtin_choose_expr(assertion, 0, (void)0); (void) x; }) -+ -+#elif defined CONFIG_YAFFS_DIRECT -+ -+#define MTD_VERSION_CODE MTD_VERSION(2, 6, 22) -+ -+/* Direct interface */ -+#include "ydirectenv.h" -+ -+#elif defined CONFIG_YAFFS_UTIL -+ -+/* Stuff for YAFFS utilities */ -+ -+#include "stdlib.h" -+#include "stdio.h" -+#include "string.h" -+ -+#define YMALLOC(x) malloc(x) -+#define YFREE(x) free(x) -+#define YMALLOC_ALT(x) malloc(x) -+#define YFREE_ALT(x) free(x) -+ -+#define YCHAR char -+#define YUCHAR unsigned char -+#define _Y(x) x -+#define yaffs_strcat(a, b) strcat(a, b) -+#define yaffs_strcpy(a, b) strcpy(a, b) -+#define yaffs_strncpy(a, b, c) strncpy(a, b, c) -+#define yaffs_strnlen(s,m) strnlen(s,m) -+#define yaffs_sprintf sprintf -+#define yaffs_toupper(a) toupper(a) -+ -+#define Y_INLINE inline -+ -+/* #define YINFO(s) YPRINTF(( __FILE__ " %d %s\n",__LINE__,s)) */ -+/* #define YALERT(s) YINFO(s) */ -+ -+#define TENDSTR "\n" -+#define TSTR(x) x -+#define TOUT(p) printf p -+ -+#define YAFFS_LOSTNFOUND_NAME "lost+found" -+#define YAFFS_LOSTNFOUND_PREFIX "obj" -+/* #define YPRINTF(x) printf x */ -+ -+#define YAFFS_ROOT_MODE 0755 -+#define YAFFS_LOSTNFOUND_MODE 0700 -+ -+#define yaffs_sum_cmp(x, y) ((x) == (y)) -+#define yaffs_strcmp(a, b) strcmp(a, b) -+ -+#else -+/* Should have specified a configuration type */ -+#error Unknown configuration -+ -+#endif -+ -+#if defined(CONFIG_YAFFS_DIRECT) || defined(CONFIG_YAFFS_WINCE) -+ -+#ifdef CONFIG_YAFFSFS_PROVIDE_VALUES -+ -+#ifndef O_RDONLY -+#define O_RDONLY 00 -+#endif -+ -+#ifndef O_WRONLY -+#define O_WRONLY 01 -+#endif -+ -+#ifndef O_RDWR -+#define O_RDWR 02 -+#endif -+ -+#ifndef O_CREAT -+#define O_CREAT 0100 -+#endif -+ -+#ifndef O_EXCL -+#define O_EXCL 0200 -+#endif -+ -+#ifndef O_TRUNC -+#define O_TRUNC 01000 -+#endif -+ -+#ifndef O_APPEND -+#define O_APPEND 02000 -+#endif -+ -+#ifndef SEEK_SET -+#define SEEK_SET 0 -+#endif -+ -+#ifndef SEEK_CUR -+#define SEEK_CUR 1 -+#endif -+ -+#ifndef SEEK_END -+#define SEEK_END 2 -+#endif -+ -+#ifndef EBUSY -+#define EBUSY 16 -+#endif -+ -+#ifndef ENODEV -+#define ENODEV 19 -+#endif -+ -+#ifndef EINVAL -+#define EINVAL 22 -+#endif -+ -+#ifndef ENFILE -+#define ENFILE 23 -+#endif -+ -+#ifndef EBADF -+#define EBADF 9 -+#endif -+ -+#ifndef EACCES -+#define EACCES 13 -+#endif -+ -+#ifndef EXDEV -+#define EXDEV 18 -+#endif -+ -+#ifndef ENOENT -+#define ENOENT 2 -+#endif -+ -+#ifndef ENOSPC -+#define ENOSPC 28 -+#endif -+ -+#ifndef ERANGE -+#define ERANGE 34 -+#endif -+ -+#ifndef ENODATA -+#define ENODATA 61 -+#endif -+ -+#ifndef ENOTEMPTY -+#define ENOTEMPTY 39 -+#endif -+ -+#ifndef ENAMETOOLONG -+#define ENAMETOOLONG 36 -+#endif -+ -+#ifndef ENOMEM -+#define ENOMEM 12 -+#endif -+ -+#ifndef EEXIST -+#define EEXIST 17 -+#endif -+ -+#ifndef ENOTDIR -+#define ENOTDIR 20 -+#endif -+ -+#ifndef EISDIR -+#define EISDIR 21 -+#endif -+ -+// Mode flags -+ -+#ifndef S_IFMT -+#define S_IFMT 0170000 -+#endif -+ -+#ifndef S_IFLNK -+#define S_IFLNK 0120000 -+#endif -+ -+#ifndef S_IFDIR -+#define S_IFDIR 0040000 -+#endif -+ -+#ifndef S_IFREG -+#define S_IFREG 0100000 -+#endif -+ -+#ifndef S_IREAD -+#define S_IREAD 0000400 -+#endif -+ -+#ifndef S_IWRITE -+#define S_IWRITE 0000200 -+#endif -+ -+#ifndef S_IEXEC -+#define S_IEXEC 0000100 -+#endif -+ -+#ifndef XATTR_CREATE -+#define XATTR_CREATE 1 -+#endif -+ -+#ifndef XATTR_REPLACE -+#define XATTR_REPLACE 2 -+#endif -+ -+#ifndef R_OK -+#define R_OK 4 -+#define W_OK 2 -+#define X_OK 1 -+#define F_OK 0 -+#endif -+ -+#else -+#include -+#include -+#include -+#endif -+ -+#endif -+ -+#ifndef Y_DUMP_STACK -+#define Y_DUMP_STACK() do { } while (0) -+#endif -+ -+#ifndef YBUG -+#define YBUG() do {\ -+ T(YAFFS_TRACE_BUG,\ -+ (TSTR("==>> yaffs bug: " __FILE__ " %d" TENDSTR),\ -+ __LINE__));\ -+ Y_DUMP_STACK();\ -+} while (0) -+#endif -+ -+#endif diff --git a/target/linux/patches/2.6.37/zlib-inflate.patch b/target/linux/patches/2.6.37/zlib-inflate.patch deleted file mode 100644 index 58e1f6d21..000000000 --- a/target/linux/patches/2.6.37/zlib-inflate.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff -Nur linux-2.6.37.orig/lib/Kconfig linux-2.6.37/lib/Kconfig ---- linux-2.6.37.orig/lib/Kconfig 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/lib/Kconfig 2011-03-01 20:10:29.833370667 +0100 -@@ -95,7 +95,7 @@ - # compression support is select'ed if needed - # - config ZLIB_INFLATE -- tristate -+ boolean - - config ZLIB_DEFLATE - tristate diff --git a/target/linux/patches/2.6.39/arm-statcmd.patch b/target/linux/patches/2.6.39/arm-statcmd.patch deleted file mode 100644 index 3aed60cbc..000000000 --- a/target/linux/patches/2.6.39/arm-statcmd.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff -Nur linux-2.6.39-rc6.orig/arch/arm/boot/compressed/Makefile linux-2.6.39-rc6/arch/arm/boot/compressed/Makefile ---- linux-2.6.39-rc6.orig/arch/arm/boot/compressed/Makefile 2011-05-04 04:59:13.000000000 +0200 -+++ linux-2.6.39-rc6/arch/arm/boot/compressed/Makefile 2011-05-10 10:35:34.000000000 +0200 -@@ -99,7 +99,7 @@ - asflags-y := -Wa,-march=all - - # Provide size of uncompressed kernel to the decompressor via a linker symbol. --LDFLAGS_vmlinux = --defsym _image_size=$(shell stat -c "%s" $(obj)/../Image) -+LDFLAGS_vmlinux = --defsym _image_size=$(shell if stat -qs .>/dev/null 2>&1;then statcmd='stat -f %z';else statcmd='stat -c %s';fi; $$statcmd "%s" $(obj)/../Image) - # Supply ZRELADDR to the decompressor via a linker symbol. - ifneq ($(CONFIG_AUTO_ZRELADDR),y) - LDFLAGS_vmlinux += --defsym zreladdr=$(ZRELADDR) diff --git a/target/linux/patches/2.6.39/bsd-compatibility.patch b/target/linux/patches/2.6.39/bsd-compatibility.patch deleted file mode 100644 index 9e91a62de..000000000 --- a/target/linux/patches/2.6.39/bsd-compatibility.patch +++ /dev/null @@ -1,2512 +0,0 @@ -diff -Nur linux-2.6.36.orig/scripts/Makefile.lib linux-2.6.36/scripts/Makefile.lib ---- linux-2.6.36.orig/scripts/Makefile.lib 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/scripts/Makefile.lib 2010-11-28 18:34:22.000000000 +0100 -@@ -216,7 +216,12 @@ - size_append = printf $(shell \ - dec_size=0; \ - for F in $1; do \ -- fsize=$$(stat -c "%s" $$F); \ -+ if stat -qs .>/dev/null 2>&1; then \ -+ statcmd='stat -f %z'; \ -+ else \ -+ statcmd='stat -c %s'; \ -+ fi; \ -+ fsize=$$($$statcmd $$F); \ - dec_size=$$(expr $$dec_size + $$fsize); \ - done; \ - printf "%08x\n" $$dec_size | \ -diff -Nur linux-2.6.36.orig/scripts/mod/mk_elfconfig.c linux-2.6.36/scripts/mod/mk_elfconfig.c ---- linux-2.6.36.orig/scripts/mod/mk_elfconfig.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/scripts/mod/mk_elfconfig.c 2010-11-28 18:33:24.000000000 +0100 -@@ -1,7 +1,18 @@ - #include - #include - #include --#include -+ -+#define EI_NIDENT (16) -+#define ELFMAG "\177ELF" -+ -+#define SELFMAG 4 -+#define EI_CLASS 4 -+#define ELFCLASS32 1 /* 32-bit objects */ -+#define ELFCLASS64 2 /* 64-bit objects */ -+ -+#define EI_DATA 5 /* Data encoding byte index */ -+#define ELFDATA2LSB 1 /* 2's complement, little endian */ -+#define ELFDATA2MSB 2 /* 2's complement, big endian */ - - int - main(int argc, char **argv) -diff -Nur linux-2.6.36.orig/scripts/mod/modpost.h linux-2.6.36/scripts/mod/modpost.h ---- linux-2.6.36.orig/scripts/mod/modpost.h 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/scripts/mod/modpost.h 2010-11-28 18:33:24.000000000 +0100 -@@ -7,7 +7,2453 @@ - #include - #include - #include --#include -+ -+ -+/* This file defines standard ELF types, structures, and macros. -+ Copyright (C) 1995-1999,2000,2001,2002,2003 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#ifndef _ELF_H -+#define _ELF_H 1 -+ -+__BEGIN_DECLS -+ -+/* Standard ELF types. */ -+ -+#include -+ -+/* Type for a 16-bit quantity. */ -+typedef uint16_t Elf32_Half; -+typedef uint16_t Elf64_Half; -+ -+/* Types for signed and unsigned 32-bit quantities. */ -+typedef uint32_t Elf32_Word; -+typedef int32_t Elf32_Sword; -+typedef uint32_t Elf64_Word; -+typedef int32_t Elf64_Sword; -+ -+/* Types for signed and unsigned 64-bit quantities. */ -+typedef uint64_t Elf32_Xword; -+typedef int64_t Elf32_Sxword; -+typedef uint64_t Elf64_Xword; -+typedef int64_t Elf64_Sxword; -+ -+/* Type of addresses. */ -+typedef uint32_t Elf32_Addr; -+typedef uint64_t Elf64_Addr; -+ -+/* Type of file offsets. */ -+typedef uint32_t Elf32_Off; -+typedef uint64_t Elf64_Off; -+ -+/* Type for section indices, which are 16-bit quantities. */ -+typedef uint16_t Elf32_Section; -+typedef uint16_t Elf64_Section; -+ -+/* Type for version symbol information. */ -+typedef Elf32_Half Elf32_Versym; -+typedef Elf64_Half Elf64_Versym; -+ -+ -+/* The ELF file header. This appears at the start of every ELF file. */ -+ -+#define EI_NIDENT (16) -+ -+typedef struct -+{ -+ unsigned char e_ident[EI_NIDENT]; /* Magic number and other info */ -+ Elf32_Half e_type; /* Object file type */ -+ Elf32_Half e_machine; /* Architecture */ -+ Elf32_Word e_version; /* Object file version */ -+ Elf32_Addr e_entry; /* Entry point virtual address */ -+ Elf32_Off e_phoff; /* Program header table file offset */ -+ Elf32_Off e_shoff; /* Section header table file offset */ -+ Elf32_Word e_flags; /* Processor-specific flags */ -+ Elf32_Half e_ehsize; /* ELF header size in bytes */ -+ Elf32_Half e_phentsize; /* Program header table entry size */ -+ Elf32_Half e_phnum; /* Program header table entry count */ -+ Elf32_Half e_shentsize; /* Section header table entry size */ -+ Elf32_Half e_shnum; /* Section header table entry count */ -+ Elf32_Half e_shstrndx; /* Section header string table index */ -+} Elf32_Ehdr; -+ -+typedef struct -+{ -+ unsigned char e_ident[EI_NIDENT]; /* Magic number and other info */ -+ Elf64_Half e_type; /* Object file type */ -+ Elf64_Half e_machine; /* Architecture */ -+ Elf64_Word e_version; /* Object file version */ -+ Elf64_Addr e_entry; /* Entry point virtual address */ -+ Elf64_Off e_phoff; /* Program header table file offset */ -+ Elf64_Off e_shoff; /* Section header table file offset */ -+ Elf64_Word e_flags; /* Processor-specific flags */ -+ Elf64_Half e_ehsize; /* ELF header size in bytes */ -+ Elf64_Half e_phentsize; /* Program header table entry size */ -+ Elf64_Half e_phnum; /* Program header table entry count */ -+ Elf64_Half e_shentsize; /* Section header table entry size */ -+ Elf64_Half e_shnum; /* Section header table entry count */ -+ Elf64_Half e_shstrndx; /* Section header string table index */ -+} Elf64_Ehdr; -+ -+/* Fields in the e_ident array. The EI_* macros are indices into the -+ array. The macros under each EI_* macro are the values the byte -+ may have. */ -+ -+#define EI_MAG0 0 /* File identification byte 0 index */ -+#define ELFMAG0 0x7f /* Magic number byte 0 */ -+ -+#define EI_MAG1 1 /* File identification byte 1 index */ -+#define ELFMAG1 'E' /* Magic number byte 1 */ -+ -+#define EI_MAG2 2 /* File identification byte 2 index */ -+#define ELFMAG2 'L' /* Magic number byte 2 */ -+ -+#define EI_MAG3 3 /* File identification byte 3 index */ -+#define ELFMAG3 'F' /* Magic number byte 3 */ -+ -+/* Conglomeration of the identification bytes, for easy testing as a word. */ -+#define ELFMAG "\177ELF" -+#define SELFMAG 4 -+ -+#define EI_CLASS 4 /* File class byte index */ -+#define ELFCLASSNONE 0 /* Invalid class */ -+#define ELFCLASS32 1 /* 32-bit objects */ -+#define ELFCLASS64 2 /* 64-bit objects */ -+#define ELFCLASSNUM 3 -+ -+#define EI_DATA 5 /* Data encoding byte index */ -+#define ELFDATANONE 0 /* Invalid data encoding */ -+#define ELFDATA2LSB 1 /* 2's complement, little endian */ -+#define ELFDATA2MSB 2 /* 2's complement, big endian */ -+#define ELFDATANUM 3 -+ -+#define EI_VERSION 6 /* File version byte index */ -+ /* Value must be EV_CURRENT */ -+ -+#define EI_OSABI 7 /* OS ABI identification */ -+#define ELFOSABI_NONE 0 /* UNIX System V ABI */ -+#define ELFOSABI_SYSV 0 /* Alias. */ -+#define ELFOSABI_HPUX 1 /* HP-UX */ -+#define ELFOSABI_NETBSD 2 /* NetBSD. */ -+#define ELFOSABI_LINUX 3 /* Linux. */ -+#define ELFOSABI_SOLARIS 6 /* Sun Solaris. */ -+#define ELFOSABI_AIX 7 /* IBM AIX. */ -+#define ELFOSABI_IRIX 8 /* SGI Irix. */ -+#define ELFOSABI_FREEBSD 9 /* FreeBSD. */ -+#define ELFOSABI_TRU64 10 /* Compaq TRU64 UNIX. */ -+#define ELFOSABI_MODESTO 11 /* Novell Modesto. */ -+#define ELFOSABI_OPENBSD 12 /* OpenBSD. */ -+#define ELFOSABI_ARM 97 /* ARM */ -+#define ELFOSABI_STANDALONE 255 /* Standalone (embedded) application */ -+ -+#define EI_ABIVERSION 8 /* ABI version */ -+ -+#define EI_PAD 9 /* Byte index of padding bytes */ -+ -+/* Legal values for e_type (object file type). */ -+ -+#define ET_NONE 0 /* No file type */ -+#define ET_REL 1 /* Relocatable file */ -+#define ET_EXEC 2 /* Executable file */ -+#define ET_DYN 3 /* Shared object file */ -+#define ET_CORE 4 /* Core file */ -+#define ET_NUM 5 /* Number of defined types */ -+#define ET_LOOS 0xfe00 /* OS-specific range start */ -+#define ET_HIOS 0xfeff /* OS-specific range end */ -+#define ET_LOPROC 0xff00 /* Processor-specific range start */ -+#define ET_HIPROC 0xffff /* Processor-specific range end */ -+ -+/* Legal values for e_machine (architecture). */ -+ -+#define EM_NONE 0 /* No machine */ -+#define EM_M32 1 /* AT&T WE 32100 */ -+#define EM_SPARC 2 /* SUN SPARC */ -+#define EM_386 3 /* Intel 80386 */ -+#define EM_68K 4 /* Motorola m68k family */ -+#define EM_88K 5 /* Motorola m88k family */ -+#define EM_860 7 /* Intel 80860 */ -+#define EM_MIPS 8 /* MIPS R3000 big-endian */ -+#define EM_S370 9 /* IBM System/370 */ -+#define EM_MIPS_RS3_LE 10 /* MIPS R3000 little-endian */ -+ -+#define EM_PARISC 15 /* HPPA */ -+#define EM_VPP500 17 /* Fujitsu VPP500 */ -+#define EM_SPARC32PLUS 18 /* Sun's "v8plus" */ -+#define EM_960 19 /* Intel 80960 */ -+#define EM_PPC 20 /* PowerPC */ -+#define EM_PPC64 21 /* PowerPC 64-bit */ -+#define EM_S390 22 /* IBM S390 */ -+ -+#define EM_V800 36 /* NEC V800 series */ -+#define EM_FR20 37 /* Fujitsu FR20 */ -+#define EM_RH32 38 /* TRW RH-32 */ -+#define EM_RCE 39 /* Motorola RCE */ -+#define EM_ARM 40 /* ARM */ -+#define EM_FAKE_ALPHA 41 /* Digital Alpha */ -+#define EM_SH 42 /* Hitachi SH */ -+#define EM_SPARCV9 43 /* SPARC v9 64-bit */ -+#define EM_TRICORE 44 /* Siemens Tricore */ -+#define EM_ARC 45 /* Argonaut RISC Core */ -+#define EM_H8_300 46 /* Hitachi H8/300 */ -+#define EM_H8_300H 47 /* Hitachi H8/300H */ -+#define EM_H8S 48 /* Hitachi H8S */ -+#define EM_H8_500 49 /* Hitachi H8/500 */ -+#define EM_IA_64 50 /* Intel Merced */ -+#define EM_MIPS_X 51 /* Stanford MIPS-X */ -+#define EM_COLDFIRE 52 /* Motorola Coldfire */ -+#define EM_68HC12 53 /* Motorola M68HC12 */ -+#define EM_MMA 54 /* Fujitsu MMA Multimedia Accelerator*/ -+#define EM_PCP 55 /* Siemens PCP */ -+#define EM_NCPU 56 /* Sony nCPU embeeded RISC */ -+#define EM_NDR1 57 /* Denso NDR1 microprocessor */ -+#define EM_STARCORE 58 /* Motorola Start*Core processor */ -+#define EM_ME16 59 /* Toyota ME16 processor */ -+#define EM_ST100 60 /* STMicroelectronic ST100 processor */ -+#define EM_TINYJ 61 /* Advanced Logic Corp. Tinyj emb.fam*/ -+#define EM_X86_64 62 /* AMD x86-64 architecture */ -+#define EM_PDSP 63 /* Sony DSP Processor */ -+ -+#define EM_FX66 66 /* Siemens FX66 microcontroller */ -+#define EM_ST9PLUS 67 /* STMicroelectronics ST9+ 8/16 mc */ -+#define EM_ST7 68 /* STmicroelectronics ST7 8 bit mc */ -+#define EM_68HC16 69 /* Motorola MC68HC16 microcontroller */ -+#define EM_68HC11 70 /* Motorola MC68HC11 microcontroller */ -+#define EM_68HC08 71 /* Motorola MC68HC08 microcontroller */ -+#define EM_68HC05 72 /* Motorola MC68HC05 microcontroller */ -+#define EM_SVX 73 /* Silicon Graphics SVx */ -+#define EM_ST19 74 /* STMicroelectronics ST19 8 bit mc */ -+#define EM_VAX 75 /* Digital VAX */ -+#define EM_CRIS 76 /* Axis Communications 32-bit embedded processor */ -+#define EM_JAVELIN 77 /* Infineon Technologies 32-bit embedded processor */ -+#define EM_FIREPATH 78 /* Element 14 64-bit DSP Processor */ -+#define EM_ZSP 79 /* LSI Logic 16-bit DSP Processor */ -+#define EM_MMIX 80 /* Donald Knuth's educational 64-bit processor */ -+#define EM_HUANY 81 /* Harvard University machine-independent object files */ -+#define EM_PRISM 82 /* SiTera Prism */ -+#define EM_AVR 83 /* Atmel AVR 8-bit microcontroller */ -+#define EM_FR30 84 /* Fujitsu FR30 */ -+#define EM_D10V 85 /* Mitsubishi D10V */ -+#define EM_D30V 86 /* Mitsubishi D30V */ -+#define EM_V850 87 /* NEC v850 */ -+#define EM_M32R 88 /* Mitsubishi M32R */ -+#define EM_MN10300 89 /* Matsushita MN10300 */ -+#define EM_MN10200 90 /* Matsushita MN10200 */ -+#define EM_PJ 91 /* picoJava */ -+#define EM_OPENRISC 92 /* OpenRISC 32-bit embedded processor */ -+#define EM_ARC_A5 93 /* ARC Cores Tangent-A5 */ -+#define EM_XTENSA 94 /* Tensilica Xtensa Architecture */ -+#define EM_NUM 95 -+ -+/* If it is necessary to assign new unofficial EM_* values, please -+ pick large random numbers (0x8523, 0xa7f2, etc.) to minimize the -+ chances of collision with official or non-GNU unofficial values. */ -+ -+#define EM_ALPHA 0x9026 -+ -+/* Legal values for e_version (version). */ -+ -+#define EV_NONE 0 /* Invalid ELF version */ -+#define EV_CURRENT 1 /* Current version */ -+#define EV_NUM 2 -+ -+/* Section header. */ -+ -+typedef struct -+{ -+ Elf32_Word sh_name; /* Section name (string tbl index) */ -+ Elf32_Word sh_type; /* Section type */ -+ Elf32_Word sh_flags; /* Section flags */ -+ Elf32_Addr sh_addr; /* Section virtual addr at execution */ -+ Elf32_Off sh_offset; /* Section file offset */ -+ Elf32_Word sh_size; /* Section size in bytes */ -+ Elf32_Word sh_link; /* Link to another section */ -+ Elf32_Word sh_info; /* Additional section information */ -+ Elf32_Word sh_addralign; /* Section alignment */ -+ Elf32_Word sh_entsize; /* Entry size if section holds table */ -+} Elf32_Shdr; -+ -+typedef struct -+{ -+ Elf64_Word sh_name; /* Section name (string tbl index) */ -+ Elf64_Word sh_type; /* Section type */ -+ Elf64_Xword sh_flags; /* Section flags */ -+ Elf64_Addr sh_addr; /* Section virtual addr at execution */ -+ Elf64_Off sh_offset; /* Section file offset */ -+ Elf64_Xword sh_size; /* Section size in bytes */ -+ Elf64_Word sh_link; /* Link to another section */ -+ Elf64_Word sh_info; /* Additional section information */ -+ Elf64_Xword sh_addralign; /* Section alignment */ -+ Elf64_Xword sh_entsize; /* Entry size if section holds table */ -+} Elf64_Shdr; -+ -+/* Special section indices. */ -+ -+#define SHN_UNDEF 0 /* Undefined section */ -+#define SHN_LORESERVE 0xff00 /* Start of reserved indices */ -+#define SHN_LOPROC 0xff00 /* Start of processor-specific */ -+#define SHN_HIPROC 0xff1f /* End of processor-specific */ -+#define SHN_LOOS 0xff20 /* Start of OS-specific */ -+#define SHN_HIOS 0xff3f /* End of OS-specific */ -+#define SHN_ABS 0xfff1 /* Associated symbol is absolute */ -+#define SHN_COMMON 0xfff2 /* Associated symbol is common */ -+#define SHN_XINDEX 0xffff /* Index is in extra table. */ -+#define SHN_HIRESERVE 0xffff /* End of reserved indices */ -+ -+/* Legal values for sh_type (section type). */ -+ -+#define SHT_NULL 0 /* Section header table entry unused */ -+#define SHT_PROGBITS 1 /* Program data */ -+#define SHT_SYMTAB 2 /* Symbol table */ -+#define SHT_STRTAB 3 /* String table */ -+#define SHT_RELA 4 /* Relocation entries with addends */ -+#define SHT_HASH 5 /* Symbol hash table */ -+#define SHT_DYNAMIC 6 /* Dynamic linking information */ -+#define SHT_NOTE 7 /* Notes */ -+#define SHT_NOBITS 8 /* Program space with no data (bss) */ -+#define SHT_REL 9 /* Relocation entries, no addends */ -+#define SHT_SHLIB 10 /* Reserved */ -+#define SHT_DYNSYM 11 /* Dynamic linker symbol table */ -+#define SHT_INIT_ARRAY 14 /* Array of constructors */ -+#define SHT_FINI_ARRAY 15 /* Array of destructors */ -+#define SHT_PREINIT_ARRAY 16 /* Array of pre-constructors */ -+#define SHT_GROUP 17 /* Section group */ -+#define SHT_SYMTAB_SHNDX 18 /* Extended section indeces */ -+#define SHT_NUM 19 /* Number of defined types. */ -+#define SHT_LOOS 0x60000000 /* Start OS-specific */ -+#define SHT_GNU_LIBLIST 0x6ffffff7 /* Prelink library list */ -+#define SHT_CHECKSUM 0x6ffffff8 /* Checksum for DSO content. */ -+#define SHT_LOSUNW 0x6ffffffa /* Sun-specific low bound. */ -+#define SHT_SUNW_move 0x6ffffffa -+#define SHT_SUNW_COMDAT 0x6ffffffb -+#define SHT_SUNW_syminfo 0x6ffffffc -+#define SHT_GNU_verdef 0x6ffffffd /* Version definition section. */ -+#define SHT_GNU_verneed 0x6ffffffe /* Version needs section. */ -+#define SHT_GNU_versym 0x6fffffff /* Version symbol table. */ -+#define SHT_HISUNW 0x6fffffff /* Sun-specific high bound. */ -+#define SHT_HIOS 0x6fffffff /* End OS-specific type */ -+#define SHT_LOPROC 0x70000000 /* Start of processor-specific */ -+#define SHT_HIPROC 0x7fffffff /* End of processor-specific */ -+#define SHT_LOUSER 0x80000000 /* Start of application-specific */ -+#define SHT_HIUSER 0x8fffffff /* End of application-specific */ -+ -+/* Legal values for sh_flags (section flags). */ -+ -+#define SHF_WRITE (1 << 0) /* Writable */ -+#define SHF_ALLOC (1 << 1) /* Occupies memory during execution */ -+#define SHF_EXECINSTR (1 << 2) /* Executable */ -+#define SHF_MERGE (1 << 4) /* Might be merged */ -+#define SHF_STRINGS (1 << 5) /* Contains nul-terminated strings */ -+#define SHF_INFO_LINK (1 << 6) /* `sh_info' contains SHT index */ -+#define SHF_LINK_ORDER (1 << 7) /* Preserve order after combining */ -+#define SHF_OS_NONCONFORMING (1 << 8) /* Non-standard OS specific handling -+ required */ -+#define SHF_GROUP (1 << 9) /* Section is member of a group. */ -+#define SHF_TLS (1 << 10) /* Section hold thread-local data. */ -+#define SHF_MASKOS 0x0ff00000 /* OS-specific. */ -+#define SHF_MASKPROC 0xf0000000 /* Processor-specific */ -+ -+/* Section group handling. */ -+#define GRP_COMDAT 0x1 /* Mark group as COMDAT. */ -+ -+/* Symbol table entry. */ -+ -+typedef struct -+{ -+ Elf32_Word st_name; /* Symbol name (string tbl index) */ -+ Elf32_Addr st_value; /* Symbol value */ -+ Elf32_Word st_size; /* Symbol size */ -+ unsigned char st_info; /* Symbol type and binding */ -+ unsigned char st_other; /* Symbol visibility */ -+ Elf32_Section st_shndx; /* Section index */ -+} Elf32_Sym; -+ -+typedef struct -+{ -+ Elf64_Word st_name; /* Symbol name (string tbl index) */ -+ unsigned char st_info; /* Symbol type and binding */ -+ unsigned char st_other; /* Symbol visibility */ -+ Elf64_Section st_shndx; /* Section index */ -+ Elf64_Addr st_value; /* Symbol value */ -+ Elf64_Xword st_size; /* Symbol size */ -+} Elf64_Sym; -+ -+/* The syminfo section if available contains additional information about -+ every dynamic symbol. */ -+ -+typedef struct -+{ -+ Elf32_Half si_boundto; /* Direct bindings, symbol bound to */ -+ Elf32_Half si_flags; /* Per symbol flags */ -+} Elf32_Syminfo; -+ -+typedef struct -+{ -+ Elf64_Half si_boundto; /* Direct bindings, symbol bound to */ -+ Elf64_Half si_flags; /* Per symbol flags */ -+} Elf64_Syminfo; -+ -+/* Possible values for si_boundto. */ -+#define SYMINFO_BT_SELF 0xffff /* Symbol bound to self */ -+#define SYMINFO_BT_PARENT 0xfffe /* Symbol bound to parent */ -+#define SYMINFO_BT_LOWRESERVE 0xff00 /* Beginning of reserved entries */ -+ -+/* Possible bitmasks for si_flags. */ -+#define SYMINFO_FLG_DIRECT 0x0001 /* Direct bound symbol */ -+#define SYMINFO_FLG_PASSTHRU 0x0002 /* Pass-thru symbol for translator */ -+#define SYMINFO_FLG_COPY 0x0004 /* Symbol is a copy-reloc */ -+#define SYMINFO_FLG_LAZYLOAD 0x0008 /* Symbol bound to object to be lazy -+ loaded */ -+/* Syminfo version values. */ -+#define SYMINFO_NONE 0 -+#define SYMINFO_CURRENT 1 -+#define SYMINFO_NUM 2 -+ -+ -+/* How to extract and insert information held in the st_info field. */ -+ -+#define ELF32_ST_BIND(val) (((unsigned char) (val)) >> 4) -+#define ELF32_ST_TYPE(val) ((val) & 0xf) -+#define ELF32_ST_INFO(bind, type) (((bind) << 4) + ((type) & 0xf)) -+ -+/* Both Elf32_Sym and Elf64_Sym use the same one-byte st_info field. */ -+#define ELF64_ST_BIND(val) ELF32_ST_BIND (val) -+#define ELF64_ST_TYPE(val) ELF32_ST_TYPE (val) -+#define ELF64_ST_INFO(bind, type) ELF32_ST_INFO ((bind), (type)) -+ -+/* Legal values for ST_BIND subfield of st_info (symbol binding). */ -+ -+#define STB_LOCAL 0 /* Local symbol */ -+#define STB_GLOBAL 1 /* Global symbol */ -+#define STB_WEAK 2 /* Weak symbol */ -+#define STB_NUM 3 /* Number of defined types. */ -+#define STB_LOOS 10 /* Start of OS-specific */ -+#define STB_HIOS 12 /* End of OS-specific */ -+#define STB_LOPROC 13 /* Start of processor-specific */ -+#define STB_HIPROC 15 /* End of processor-specific */ -+ -+/* Legal values for ST_TYPE subfield of st_info (symbol type). */ -+ -+#define STT_NOTYPE 0 /* Symbol type is unspecified */ -+#define STT_OBJECT 1 /* Symbol is a data object */ -+#define STT_FUNC 2 /* Symbol is a code object */ -+#define STT_SECTION 3 /* Symbol associated with a section */ -+#define STT_FILE 4 /* Symbol's name is file name */ -+#define STT_COMMON 5 /* Symbol is a common data object */ -+#define STT_TLS 6 /* Symbol is thread-local data object*/ -+#define STT_NUM 7 /* Number of defined types. */ -+#define STT_LOOS 10 /* Start of OS-specific */ -+#define STT_HIOS 12 /* End of OS-specific */ -+#define STT_LOPROC 13 /* Start of processor-specific */ -+#define STT_HIPROC 15 /* End of processor-specific */ -+ -+ -+/* Symbol table indices are found in the hash buckets and chain table -+ of a symbol hash table section. This special index value indicates -+ the end of a chain, meaning no further symbols are found in that bucket. */ -+ -+#define STN_UNDEF 0 /* End of a chain. */ -+ -+ -+/* How to extract and insert information held in the st_other field. */ -+ -+#define ELF32_ST_VISIBILITY(o) ((o) & 0x03) -+ -+/* For ELF64 the definitions are the same. */ -+#define ELF64_ST_VISIBILITY(o) ELF32_ST_VISIBILITY (o) -+ -+/* Symbol visibility specification encoded in the st_other field. */ -+#define STV_DEFAULT 0 /* Default symbol visibility rules */ -+#define STV_INTERNAL 1 /* Processor specific hidden class */ -+#define STV_HIDDEN 2 /* Sym unavailable in other modules */ -+#define STV_PROTECTED 3 /* Not preemptible, not exported */ -+ -+ -+/* Relocation table entry without addend (in section of type SHT_REL). */ -+ -+typedef struct -+{ -+ Elf32_Addr r_offset; /* Address */ -+ Elf32_Word r_info; /* Relocation type and symbol index */ -+} Elf32_Rel; -+ -+/* I have seen two different definitions of the Elf64_Rel and -+ Elf64_Rela structures, so we'll leave them out until Novell (or -+ whoever) gets their act together. */ -+/* The following, at least, is used on Sparc v9, MIPS, and Alpha. */ -+ -+typedef struct -+{ -+ Elf64_Addr r_offset; /* Address */ -+ Elf64_Xword r_info; /* Relocation type and symbol index */ -+} Elf64_Rel; -+ -+/* Relocation table entry with addend (in section of type SHT_RELA). */ -+ -+typedef struct -+{ -+ Elf32_Addr r_offset; /* Address */ -+ Elf32_Word r_info; /* Relocation type and symbol index */ -+ Elf32_Sword r_addend; /* Addend */ -+} Elf32_Rela; -+ -+typedef struct -+{ -+ Elf64_Addr r_offset; /* Address */ -+ Elf64_Xword r_info; /* Relocation type and symbol index */ -+ Elf64_Sxword r_addend; /* Addend */ -+} Elf64_Rela; -+ -+/* How to extract and insert information held in the r_info field. */ -+ -+#define ELF32_R_SYM(val) ((val) >> 8) -+#define ELF32_R_TYPE(val) ((val) & 0xff) -+#define ELF32_R_INFO(sym, type) (((sym) << 8) + ((type) & 0xff)) -+ -+#define ELF64_R_SYM(i) ((i) >> 32) -+#define ELF64_R_TYPE(i) ((i) & 0xffffffff) -+#define ELF64_R_INFO(sym,type) ((((Elf64_Xword) (sym)) << 32) + (type)) -+ -+/* Program segment header. */ -+ -+typedef struct -+{ -+ Elf32_Word p_type; /* Segment type */ -+ Elf32_Off p_offset; /* Segment file offset */ -+ Elf32_Addr p_vaddr; /* Segment virtual address */ -+ Elf32_Addr p_paddr; /* Segment physical address */ -+ Elf32_Word p_filesz; /* Segment size in file */ -+ Elf32_Word p_memsz; /* Segment size in memory */ -+ Elf32_Word p_flags; /* Segment flags */ -+ Elf32_Word p_align; /* Segment alignment */ -+} Elf32_Phdr; -+ -+typedef struct -+{ -+ Elf64_Word p_type; /* Segment type */ -+ Elf64_Word p_flags; /* Segment flags */ -+ Elf64_Off p_offset; /* Segment file offset */ -+ Elf64_Addr p_vaddr; /* Segment virtual address */ -+ Elf64_Addr p_paddr; /* Segment physical address */ -+ Elf64_Xword p_filesz; /* Segment size in file */ -+ Elf64_Xword p_memsz; /* Segment size in memory */ -+ Elf64_Xword p_align; /* Segment alignment */ -+} Elf64_Phdr; -+ -+/* Legal values for p_type (segment type). */ -+ -+#define PT_NULL 0 /* Program header table entry unused */ -+#define PT_LOAD 1 /* Loadable program segment */ -+#define PT_DYNAMIC 2 /* Dynamic linking information */ -+#define PT_INTERP 3 /* Program interpreter */ -+#define PT_NOTE 4 /* Auxiliary information */ -+#define PT_SHLIB 5 /* Reserved */ -+#define PT_PHDR 6 /* Entry for header table itself */ -+#define PT_TLS 7 /* Thread-local storage segment */ -+#define PT_NUM 8 /* Number of defined types */ -+#define PT_LOOS 0x60000000 /* Start of OS-specific */ -+#define PT_GNU_EH_FRAME 0x6474e550 /* GCC .eh_frame_hdr segment */ -+#define PT_GNU_STACK 0x6474e551 /* Indicates stack executability */ -+#define PT_LOSUNW 0x6ffffffa -+#define PT_SUNWBSS 0x6ffffffa /* Sun Specific segment */ -+#define PT_SUNWSTACK 0x6ffffffb /* Stack segment */ -+#define PT_HISUNW 0x6fffffff -+#define PT_HIOS 0x6fffffff /* End of OS-specific */ -+#define PT_LOPROC 0x70000000 /* Start of processor-specific */ -+#define PT_HIPROC 0x7fffffff /* End of processor-specific */ -+ -+/* Legal values for p_flags (segment flags). */ -+ -+#define PF_X (1 << 0) /* Segment is executable */ -+#define PF_W (1 << 1) /* Segment is writable */ -+#define PF_R (1 << 2) /* Segment is readable */ -+#define PF_MASKOS 0x0ff00000 /* OS-specific */ -+#define PF_MASKPROC 0xf0000000 /* Processor-specific */ -+ -+/* Legal values for note segment descriptor types for core files. */ -+ -+#define NT_PRSTATUS 1 /* Contains copy of prstatus struct */ -+#define NT_FPREGSET 2 /* Contains copy of fpregset struct */ -+#define NT_PRPSINFO 3 /* Contains copy of prpsinfo struct */ -+#define NT_PRXREG 4 /* Contains copy of prxregset struct */ -+#define NT_TASKSTRUCT 4 /* Contains copy of task structure */ -+#define NT_PLATFORM 5 /* String from sysinfo(SI_PLATFORM) */ -+#define NT_AUXV 6 /* Contains copy of auxv array */ -+#define NT_GWINDOWS 7 /* Contains copy of gwindows struct */ -+#define NT_ASRS 8 /* Contains copy of asrset struct */ -+#define NT_PSTATUS 10 /* Contains copy of pstatus struct */ -+#define NT_PSINFO 13 /* Contains copy of psinfo struct */ -+#define NT_PRCRED 14 /* Contains copy of prcred struct */ -+#define NT_UTSNAME 15 /* Contains copy of utsname struct */ -+#define NT_LWPSTATUS 16 /* Contains copy of lwpstatus struct */ -+#define NT_LWPSINFO 17 /* Contains copy of lwpinfo struct */ -+#define NT_PRFPXREG 20 /* Contains copy of fprxregset struct*/ -+ -+/* Legal values for the note segment descriptor types for object files. */ -+ -+#define NT_VERSION 1 /* Contains a version string. */ -+ -+ -+/* Dynamic section entry. */ -+ -+typedef struct -+{ -+ Elf32_Sword d_tag; /* Dynamic entry type */ -+ union -+ { -+ Elf32_Word d_val; /* Integer value */ -+ Elf32_Addr d_ptr; /* Address value */ -+ } d_un; -+} Elf32_Dyn; -+ -+typedef struct -+{ -+ Elf64_Sxword d_tag; /* Dynamic entry type */ -+ union -+ { -+ Elf64_Xword d_val; /* Integer value */ -+ Elf64_Addr d_ptr; /* Address value */ -+ } d_un; -+} Elf64_Dyn; -+ -+/* Legal values for d_tag (dynamic entry type). */ -+ -+#define DT_NULL 0 /* Marks end of dynamic section */ -+#define DT_NEEDED 1 /* Name of needed library */ -+#define DT_PLTRELSZ 2 /* Size in bytes of PLT relocs */ -+#define DT_PLTGOT 3 /* Processor defined value */ -+#define DT_HASH 4 /* Address of symbol hash table */ -+#define DT_STRTAB 5 /* Address of string table */ -+#define DT_SYMTAB 6 /* Address of symbol table */ -+#define DT_RELA 7 /* Address of Rela relocs */ -+#define DT_RELASZ 8 /* Total size of Rela relocs */ -+#define DT_RELAENT 9 /* Size of one Rela reloc */ -+#define DT_STRSZ 10 /* Size of string table */ -+#define DT_SYMENT 11 /* Size of one symbol table entry */ -+#define DT_INIT 12 /* Address of init function */ -+#define DT_FINI 13 /* Address of termination function */ -+#define DT_SONAME 14 /* Name of shared object */ -+#define DT_RPATH 15 /* Library search path (deprecated) */ -+#define DT_SYMBOLIC 16 /* Start symbol search here */ -+#define DT_REL 17 /* Address of Rel relocs */ -+#define DT_RELSZ 18 /* Total size of Rel relocs */ -+#define DT_RELENT 19 /* Size of one Rel reloc */ -+#define DT_PLTREL 20 /* Type of reloc in PLT */ -+#define DT_DEBUG 21 /* For debugging; unspecified */ -+#define DT_TEXTREL 22 /* Reloc might modify .text */ -+#define DT_JMPREL 23 /* Address of PLT relocs */ -+#define DT_BIND_NOW 24 /* Process relocations of object */ -+#define DT_INIT_ARRAY 25 /* Array with addresses of init fct */ -+#define DT_FINI_ARRAY 26 /* Array with addresses of fini fct */ -+#define DT_INIT_ARRAYSZ 27 /* Size in bytes of DT_INIT_ARRAY */ -+#define DT_FINI_ARRAYSZ 28 /* Size in bytes of DT_FINI_ARRAY */ -+#define DT_RUNPATH 29 /* Library search path */ -+#define DT_FLAGS 30 /* Flags for the object being loaded */ -+#define DT_ENCODING 32 /* Start of encoded range */ -+#define DT_PREINIT_ARRAY 32 /* Array with addresses of preinit fct*/ -+#define DT_PREINIT_ARRAYSZ 33 /* size in bytes of DT_PREINIT_ARRAY */ -+#define DT_NUM 34 /* Number used */ -+#define DT_LOOS 0x6000000d /* Start of OS-specific */ -+#define DT_HIOS 0x6ffff000 /* End of OS-specific */ -+#define DT_LOPROC 0x70000000 /* Start of processor-specific */ -+#define DT_HIPROC 0x7fffffff /* End of processor-specific */ -+#define DT_PROCNUM DT_MIPS_NUM /* Most used by any processor */ -+ -+/* DT_* entries which fall between DT_VALRNGHI & DT_VALRNGLO use the -+ Dyn.d_un.d_val field of the Elf*_Dyn structure. This follows Sun's -+ approach. */ -+#define DT_VALRNGLO 0x6ffffd00 -+#define DT_GNU_PRELINKED 0x6ffffdf5 /* Prelinking timestamp */ -+#define DT_GNU_CONFLICTSZ 0x6ffffdf6 /* Size of conflict section */ -+#define DT_GNU_LIBLISTSZ 0x6ffffdf7 /* Size of library list */ -+#define DT_CHECKSUM 0x6ffffdf8 -+#define DT_PLTPADSZ 0x6ffffdf9 -+#define DT_MOVEENT 0x6ffffdfa -+#define DT_MOVESZ 0x6ffffdfb -+#define DT_FEATURE_1 0x6ffffdfc /* Feature selection (DTF_*). */ -+#define DT_POSFLAG_1 0x6ffffdfd /* Flags for DT_* entries, effecting -+ the following DT_* entry. */ -+#define DT_SYMINSZ 0x6ffffdfe /* Size of syminfo table (in bytes) */ -+#define DT_SYMINENT 0x6ffffdff /* Entry size of syminfo */ -+#define DT_VALRNGHI 0x6ffffdff -+#define DT_VALTAGIDX(tag) (DT_VALRNGHI - (tag)) /* Reverse order! */ -+#define DT_VALNUM 12 -+ -+/* DT_* entries which fall between DT_ADDRRNGHI & DT_ADDRRNGLO use the -+ Dyn.d_un.d_ptr field of the Elf*_Dyn structure. -+ -+ If any adjustment is made to the ELF object after it has been -+ built these entries will need to be adjusted. */ -+#define DT_ADDRRNGLO 0x6ffffe00 -+#define DT_GNU_CONFLICT 0x6ffffef8 /* Start of conflict section */ -+#define DT_GNU_LIBLIST 0x6ffffef9 /* Library list */ -+#define DT_CONFIG 0x6ffffefa /* Configuration information. */ -+#define DT_DEPAUDIT 0x6ffffefb /* Dependency auditing. */ -+#define DT_AUDIT 0x6ffffefc /* Object auditing. */ -+#define DT_PLTPAD 0x6ffffefd /* PLT padding. */ -+#define DT_MOVETAB 0x6ffffefe /* Move table. */ -+#define DT_SYMINFO 0x6ffffeff /* Syminfo table. */ -+#define DT_ADDRRNGHI 0x6ffffeff -+#define DT_ADDRTAGIDX(tag) (DT_ADDRRNGHI - (tag)) /* Reverse order! */ -+#define DT_ADDRNUM 10 -+ -+/* The versioning entry types. The next are defined as part of the -+ GNU extension. */ -+#define DT_VERSYM 0x6ffffff0 -+ -+#define DT_RELACOUNT 0x6ffffff9 -+#define DT_RELCOUNT 0x6ffffffa -+ -+/* These were chosen by Sun. */ -+#define DT_FLAGS_1 0x6ffffffb /* State flags, see DF_1_* below. */ -+#define DT_VERDEF 0x6ffffffc /* Address of version definition -+ table */ -+#define DT_VERDEFNUM 0x6ffffffd /* Number of version definitions */ -+#define DT_VERNEED 0x6ffffffe /* Address of table with needed -+ versions */ -+#define DT_VERNEEDNUM 0x6fffffff /* Number of needed versions */ -+#define DT_VERSIONTAGIDX(tag) (DT_VERNEEDNUM - (tag)) /* Reverse order! */ -+#define DT_VERSIONTAGNUM 16 -+ -+/* Sun added these machine-independent extensions in the "processor-specific" -+ range. Be compatible. */ -+#define DT_AUXILIARY 0x7ffffffd /* Shared object to load before self */ -+#define DT_FILTER 0x7fffffff /* Shared object to get values from */ -+#define DT_EXTRATAGIDX(tag) ((Elf32_Word)-((Elf32_Sword) (tag) <<1>>1)-1) -+#define DT_EXTRANUM 3 -+ -+/* Values of `d_un.d_val' in the DT_FLAGS entry. */ -+#define DF_ORIGIN 0x00000001 /* Object may use DF_ORIGIN */ -+#define DF_SYMBOLIC 0x00000002 /* Symbol resolutions starts here */ -+#define DF_TEXTREL 0x00000004 /* Object contains text relocations */ -+#define DF_BIND_NOW 0x00000008 /* No lazy binding for this object */ -+#define DF_STATIC_TLS 0x00000010 /* Module uses the static TLS model */ -+ -+/* State flags selectable in the `d_un.d_val' element of the DT_FLAGS_1 -+ entry in the dynamic section. */ -+#define DF_1_NOW 0x00000001 /* Set RTLD_NOW for this object. */ -+#define DF_1_GLOBAL 0x00000002 /* Set RTLD_GLOBAL for this object. */ -+#define DF_1_GROUP 0x00000004 /* Set RTLD_GROUP for this object. */ -+#define DF_1_NODELETE 0x00000008 /* Set RTLD_NODELETE for this object.*/ -+#define DF_1_LOADFLTR 0x00000010 /* Trigger filtee loading at runtime.*/ -+#define DF_1_INITFIRST 0x00000020 /* Set RTLD_INITFIRST for this object*/ -+#define DF_1_NOOPEN 0x00000040 /* Set RTLD_NOOPEN for this object. */ -+#define DF_1_ORIGIN 0x00000080 /* $ORIGIN must be handled. */ -+#define DF_1_DIRECT 0x00000100 /* Direct binding enabled. */ -+#define DF_1_TRANS 0x00000200 -+#define DF_1_INTERPOSE 0x00000400 /* Object is used to interpose. */ -+#define DF_1_NODEFLIB 0x00000800 /* Ignore default lib search path. */ -+#define DF_1_NODUMP 0x00001000 /* Object can't be dldump'ed. */ -+#define DF_1_CONFALT 0x00002000 /* Configuration alternative created.*/ -+#define DF_1_ENDFILTEE 0x00004000 /* Filtee terminates filters search. */ -+#define DF_1_DISPRELDNE 0x00008000 /* Disp reloc applied at build time. */ -+#define DF_1_DISPRELPND 0x00010000 /* Disp reloc applied at run-time. */ -+ -+/* Flags for the feature selection in DT_FEATURE_1. */ -+#define DTF_1_PARINIT 0x00000001 -+#define DTF_1_CONFEXP 0x00000002 -+ -+/* Flags in the DT_POSFLAG_1 entry effecting only the next DT_* entry. */ -+#define DF_P1_LAZYLOAD 0x00000001 /* Lazyload following object. */ -+#define DF_P1_GROUPPERM 0x00000002 /* Symbols from next object are not -+ generally available. */ -+ -+/* Version definition sections. */ -+ -+typedef struct -+{ -+ Elf32_Half vd_version; /* Version revision */ -+ Elf32_Half vd_flags; /* Version information */ -+ Elf32_Half vd_ndx; /* Version Index */ -+ Elf32_Half vd_cnt; /* Number of associated aux entries */ -+ Elf32_Word vd_hash; /* Version name hash value */ -+ Elf32_Word vd_aux; /* Offset in bytes to verdaux array */ -+ Elf32_Word vd_next; /* Offset in bytes to next verdef -+ entry */ -+} Elf32_Verdef; -+ -+typedef struct -+{ -+ Elf64_Half vd_version; /* Version revision */ -+ Elf64_Half vd_flags; /* Version information */ -+ Elf64_Half vd_ndx; /* Version Index */ -+ Elf64_Half vd_cnt; /* Number of associated aux entries */ -+ Elf64_Word vd_hash; /* Version name hash value */ -+ Elf64_Word vd_aux; /* Offset in bytes to verdaux array */ -+ Elf64_Word vd_next; /* Offset in bytes to next verdef -+ entry */ -+} Elf64_Verdef; -+ -+ -+/* Legal values for vd_version (version revision). */ -+#define VER_DEF_NONE 0 /* No version */ -+#define VER_DEF_CURRENT 1 /* Current version */ -+#define VER_DEF_NUM 2 /* Given version number */ -+ -+/* Legal values for vd_flags (version information flags). */ -+#define VER_FLG_BASE 0x1 /* Version definition of file itself */ -+#define VER_FLG_WEAK 0x2 /* Weak version identifier */ -+ -+/* Versym symbol index values. */ -+#define VER_NDX_LOCAL 0 /* Symbol is local. */ -+#define VER_NDX_GLOBAL 1 /* Symbol is global. */ -+#define VER_NDX_LORESERVE 0xff00 /* Beginning of reserved entries. */ -+#define VER_NDX_ELIMINATE 0xff01 /* Symbol is to be eliminated. */ -+ -+/* Auxialiary version information. */ -+ -+typedef struct -+{ -+ Elf32_Word vda_name; /* Version or dependency names */ -+ Elf32_Word vda_next; /* Offset in bytes to next verdaux -+ entry */ -+} Elf32_Verdaux; -+ -+typedef struct -+{ -+ Elf64_Word vda_name; /* Version or dependency names */ -+ Elf64_Word vda_next; /* Offset in bytes to next verdaux -+ entry */ -+} Elf64_Verdaux; -+ -+ -+/* Version dependency section. */ -+ -+typedef struct -+{ -+ Elf32_Half vn_version; /* Version of structure */ -+ Elf32_Half vn_cnt; /* Number of associated aux entries */ -+ Elf32_Word vn_file; /* Offset of filename for this -+ dependency */ -+ Elf32_Word vn_aux; /* Offset in bytes to vernaux array */ -+ Elf32_Word vn_next; /* Offset in bytes to next verneed -+ entry */ -+} Elf32_Verneed; -+ -+typedef struct -+{ -+ Elf64_Half vn_version; /* Version of structure */ -+ Elf64_Half vn_cnt; /* Number of associated aux entries */ -+ Elf64_Word vn_file; /* Offset of filename for this -+ dependency */ -+ Elf64_Word vn_aux; /* Offset in bytes to vernaux array */ -+ Elf64_Word vn_next; /* Offset in bytes to next verneed -+ entry */ -+} Elf64_Verneed; -+ -+ -+/* Legal values for vn_version (version revision). */ -+#define VER_NEED_NONE 0 /* No version */ -+#define VER_NEED_CURRENT 1 /* Current version */ -+#define VER_NEED_NUM 2 /* Given version number */ -+ -+/* Auxiliary needed version information. */ -+ -+typedef struct -+{ -+ Elf32_Word vna_hash; /* Hash value of dependency name */ -+ Elf32_Half vna_flags; /* Dependency specific information */ -+ Elf32_Half vna_other; /* Unused */ -+ Elf32_Word vna_name; /* Dependency name string offset */ -+ Elf32_Word vna_next; /* Offset in bytes to next vernaux -+ entry */ -+} Elf32_Vernaux; -+ -+typedef struct -+{ -+ Elf64_Word vna_hash; /* Hash value of dependency name */ -+ Elf64_Half vna_flags; /* Dependency specific information */ -+ Elf64_Half vna_other; /* Unused */ -+ Elf64_Word vna_name; /* Dependency name string offset */ -+ Elf64_Word vna_next; /* Offset in bytes to next vernaux -+ entry */ -+} Elf64_Vernaux; -+ -+ -+/* Legal values for vna_flags. */ -+#define VER_FLG_WEAK 0x2 /* Weak version identifier */ -+ -+ -+/* Auxiliary vector. */ -+ -+/* This vector is normally only used by the program interpreter. The -+ usual definition in an ABI supplement uses the name auxv_t. The -+ vector is not usually defined in a standard file, but it -+ can't hurt. We rename it to avoid conflicts. The sizes of these -+ types are an arrangement between the exec server and the program -+ interpreter, so we don't fully specify them here. */ -+ -+typedef struct -+{ -+ int a_type; /* Entry type */ -+ union -+ { -+ long int a_val; /* Integer value */ -+ void *a_ptr; /* Pointer value */ -+ void (*a_fcn) (void); /* Function pointer value */ -+ } a_un; -+} Elf32_auxv_t; -+ -+typedef struct -+{ -+ long int a_type; /* Entry type */ -+ union -+ { -+ long int a_val; /* Integer value */ -+ void *a_ptr; /* Pointer value */ -+ void (*a_fcn) (void); /* Function pointer value */ -+ } a_un; -+} Elf64_auxv_t; -+ -+/* Legal values for a_type (entry type). */ -+ -+#define AT_NULL 0 /* End of vector */ -+#define AT_IGNORE 1 /* Entry should be ignored */ -+#define AT_EXECFD 2 /* File descriptor of program */ -+#define AT_PHDR 3 /* Program headers for program */ -+#define AT_PHENT 4 /* Size of program header entry */ -+#define AT_PHNUM 5 /* Number of program headers */ -+#define AT_PAGESZ 6 /* System page size */ -+#define AT_BASE 7 /* Base address of interpreter */ -+#define AT_FLAGS 8 /* Flags */ -+#define AT_ENTRY 9 /* Entry point of program */ -+#define AT_NOTELF 10 /* Program is not ELF */ -+#define AT_UID 11 /* Real uid */ -+#define AT_EUID 12 /* Effective uid */ -+#define AT_GID 13 /* Real gid */ -+#define AT_EGID 14 /* Effective gid */ -+#define AT_CLKTCK 17 /* Frequency of times() */ -+ -+/* Some more special a_type values describing the hardware. */ -+#define AT_PLATFORM 15 /* String identifying platform. */ -+#define AT_HWCAP 16 /* Machine dependent hints about -+ processor capabilities. */ -+ -+/* This entry gives some information about the FPU initialization -+ performed by the kernel. */ -+#define AT_FPUCW 18 /* Used FPU control word. */ -+ -+/* Cache block sizes. */ -+#define AT_DCACHEBSIZE 19 /* Data cache block size. */ -+#define AT_ICACHEBSIZE 20 /* Instruction cache block size. */ -+#define AT_UCACHEBSIZE 21 /* Unified cache block size. */ -+ -+/* A special ignored value for PPC, used by the kernel to control the -+ interpretation of the AUXV. Must be > 16. */ -+#define AT_IGNOREPPC 22 /* Entry should be ignored. */ -+ -+#define AT_SECURE 23 /* Boolean, was exec setuid-like? */ -+ -+/* Pointer to the global system page used for system calls and other -+ nice things. */ -+#define AT_SYSINFO 32 -+#define AT_SYSINFO_EHDR 33 -+ -+ -+/* Note section contents. Each entry in the note section begins with -+ a header of a fixed form. */ -+ -+typedef struct -+{ -+ Elf32_Word n_namesz; /* Length of the note's name. */ -+ Elf32_Word n_descsz; /* Length of the note's descriptor. */ -+ Elf32_Word n_type; /* Type of the note. */ -+} Elf32_Nhdr; -+ -+typedef struct -+{ -+ Elf64_Word n_namesz; /* Length of the note's name. */ -+ Elf64_Word n_descsz; /* Length of the note's descriptor. */ -+ Elf64_Word n_type; /* Type of the note. */ -+} Elf64_Nhdr; -+ -+/* Known names of notes. */ -+ -+/* Solaris entries in the note section have this name. */ -+#define ELF_NOTE_SOLARIS "SUNW Solaris" -+ -+/* Note entries for GNU systems have this name. */ -+#define ELF_NOTE_GNU "GNU" -+ -+ -+/* Defined types of notes for Solaris. */ -+ -+/* Value of descriptor (one word) is desired pagesize for the binary. */ -+#define ELF_NOTE_PAGESIZE_HINT 1 -+ -+ -+/* Defined note types for GNU systems. */ -+ -+/* ABI information. The descriptor consists of words: -+ word 0: OS descriptor -+ word 1: major version of the ABI -+ word 2: minor version of the ABI -+ word 3: subminor version of the ABI -+*/ -+#define ELF_NOTE_ABI 1 -+ -+/* Known OSes. These value can appear in word 0 of an ELF_NOTE_ABI -+ note section entry. */ -+#define ELF_NOTE_OS_LINUX 0 -+#define ELF_NOTE_OS_GNU 1 -+#define ELF_NOTE_OS_SOLARIS2 2 -+#define ELF_NOTE_OS_FREEBSD 3 -+ -+ -+/* Move records. */ -+typedef struct -+{ -+ Elf32_Xword m_value; /* Symbol value. */ -+ Elf32_Word m_info; /* Size and index. */ -+ Elf32_Word m_poffset; /* Symbol offset. */ -+ Elf32_Half m_repeat; /* Repeat count. */ -+ Elf32_Half m_stride; /* Stride info. */ -+} Elf32_Move; -+ -+typedef struct -+{ -+ Elf64_Xword m_value; /* Symbol value. */ -+ Elf64_Xword m_info; /* Size and index. */ -+ Elf64_Xword m_poffset; /* Symbol offset. */ -+ Elf64_Half m_repeat; /* Repeat count. */ -+ Elf64_Half m_stride; /* Stride info. */ -+} Elf64_Move; -+ -+/* Macro to construct move records. */ -+#define ELF32_M_SYM(info) ((info) >> 8) -+#define ELF32_M_SIZE(info) ((unsigned char) (info)) -+#define ELF32_M_INFO(sym, size) (((sym) << 8) + (unsigned char) (size)) -+ -+#define ELF64_M_SYM(info) ELF32_M_SYM (info) -+#define ELF64_M_SIZE(info) ELF32_M_SIZE (info) -+#define ELF64_M_INFO(sym, size) ELF32_M_INFO (sym, size) -+ -+ -+/* Motorola 68k specific definitions. */ -+ -+/* Values for Elf32_Ehdr.e_flags. */ -+#define EF_CPU32 0x00810000 -+ -+/* m68k relocs. */ -+ -+#define R_68K_NONE 0 /* No reloc */ -+#define R_68K_32 1 /* Direct 32 bit */ -+#define R_68K_16 2 /* Direct 16 bit */ -+#define R_68K_8 3 /* Direct 8 bit */ -+#define R_68K_PC32 4 /* PC relative 32 bit */ -+#define R_68K_PC16 5 /* PC relative 16 bit */ -+#define R_68K_PC8 6 /* PC relative 8 bit */ -+#define R_68K_GOT32 7 /* 32 bit PC relative GOT entry */ -+#define R_68K_GOT16 8 /* 16 bit PC relative GOT entry */ -+#define R_68K_GOT8 9 /* 8 bit PC relative GOT entry */ -+#define R_68K_GOT32O 10 /* 32 bit GOT offset */ -+#define R_68K_GOT16O 11 /* 16 bit GOT offset */ -+#define R_68K_GOT8O 12 /* 8 bit GOT offset */ -+#define R_68K_PLT32 13 /* 32 bit PC relative PLT address */ -+#define R_68K_PLT16 14 /* 16 bit PC relative PLT address */ -+#define R_68K_PLT8 15 /* 8 bit PC relative PLT address */ -+#define R_68K_PLT32O 16 /* 32 bit PLT offset */ -+#define R_68K_PLT16O 17 /* 16 bit PLT offset */ -+#define R_68K_PLT8O 18 /* 8 bit PLT offset */ -+#define R_68K_COPY 19 /* Copy symbol at runtime */ -+#define R_68K_GLOB_DAT 20 /* Create GOT entry */ -+#define R_68K_JMP_SLOT 21 /* Create PLT entry */ -+#define R_68K_RELATIVE 22 /* Adjust by program base */ -+/* Keep this the last entry. */ -+#define R_68K_NUM 23 -+ -+/* Intel 80386 specific definitions. */ -+ -+/* i386 relocs. */ -+ -+#define R_386_NONE 0 /* No reloc */ -+#define R_386_32 1 /* Direct 32 bit */ -+#define R_386_PC32 2 /* PC relative 32 bit */ -+#define R_386_GOT32 3 /* 32 bit GOT entry */ -+#define R_386_PLT32 4 /* 32 bit PLT address */ -+#define R_386_COPY 5 /* Copy symbol at runtime */ -+#define R_386_GLOB_DAT 6 /* Create GOT entry */ -+#define R_386_JMP_SLOT 7 /* Create PLT entry */ -+#define R_386_RELATIVE 8 /* Adjust by program base */ -+#define R_386_GOTOFF 9 /* 32 bit offset to GOT */ -+#define R_386_GOTPC 10 /* 32 bit PC relative offset to GOT */ -+#define R_386_32PLT 11 -+#define R_386_TLS_TPOFF 14 /* Offset in static TLS block */ -+#define R_386_TLS_IE 15 /* Address of GOT entry for static TLS -+ block offset */ -+#define R_386_TLS_GOTIE 16 /* GOT entry for static TLS block -+ offset */ -+#define R_386_TLS_LE 17 /* Offset relative to static TLS -+ block */ -+#define R_386_TLS_GD 18 /* Direct 32 bit for GNU version of -+ general dynamic thread local data */ -+#define R_386_TLS_LDM 19 /* Direct 32 bit for GNU version of -+ local dynamic thread local data -+ in LE code */ -+#define R_386_16 20 -+#define R_386_PC16 21 -+#define R_386_8 22 -+#define R_386_PC8 23 -+#define R_386_TLS_GD_32 24 /* Direct 32 bit for general dynamic -+ thread local data */ -+#define R_386_TLS_GD_PUSH 25 /* Tag for pushl in GD TLS code */ -+#define R_386_TLS_GD_CALL 26 /* Relocation for call to -+ __tls_get_addr() */ -+#define R_386_TLS_GD_POP 27 /* Tag for popl in GD TLS code */ -+#define R_386_TLS_LDM_32 28 /* Direct 32 bit for local dynamic -+ thread local data in LE code */ -+#define R_386_TLS_LDM_PUSH 29 /* Tag for pushl in LDM TLS code */ -+#define R_386_TLS_LDM_CALL 30 /* Relocation for call to -+ __tls_get_addr() in LDM code */ -+#define R_386_TLS_LDM_POP 31 /* Tag for popl in LDM TLS code */ -+#define R_386_TLS_LDO_32 32 /* Offset relative to TLS block */ -+#define R_386_TLS_IE_32 33 /* GOT entry for negated static TLS -+ block offset */ -+#define R_386_TLS_LE_32 34 /* Negated offset relative to static -+ TLS block */ -+#define R_386_TLS_DTPMOD32 35 /* ID of module containing symbol */ -+#define R_386_TLS_DTPOFF32 36 /* Offset in TLS block */ -+#define R_386_TLS_TPOFF32 37 /* Negated offset in static TLS block */ -+/* Keep this the last entry. */ -+#define R_386_NUM 38 -+ -+/* SUN SPARC specific definitions. */ -+ -+/* Legal values for ST_TYPE subfield of st_info (symbol type). */ -+ -+#define STT_REGISTER 13 /* Global register reserved to app. */ -+ -+/* Values for Elf64_Ehdr.e_flags. */ -+ -+#define EF_SPARCV9_MM 3 -+#define EF_SPARCV9_TSO 0 -+#define EF_SPARCV9_PSO 1 -+#define EF_SPARCV9_RMO 2 -+#define EF_SPARC_LEDATA 0x800000 /* little endian data */ -+#define EF_SPARC_EXT_MASK 0xFFFF00 -+#define EF_SPARC_32PLUS 0x000100 /* generic V8+ features */ -+#define EF_SPARC_SUN_US1 0x000200 /* Sun UltraSPARC1 extensions */ -+#define EF_SPARC_HAL_R1 0x000400 /* HAL R1 extensions */ -+#define EF_SPARC_SUN_US3 0x000800 /* Sun UltraSPARCIII extensions */ -+ -+/* SPARC relocs. */ -+ -+#define R_SPARC_NONE 0 /* No reloc */ -+#define R_SPARC_8 1 /* Direct 8 bit */ -+#define R_SPARC_16 2 /* Direct 16 bit */ -+#define R_SPARC_32 3 /* Direct 32 bit */ -+#define R_SPARC_DISP8 4 /* PC relative 8 bit */ -+#define R_SPARC_DISP16 5 /* PC relative 16 bit */ -+#define R_SPARC_DISP32 6 /* PC relative 32 bit */ -+#define R_SPARC_WDISP30 7 /* PC relative 30 bit shifted */ -+#define R_SPARC_WDISP22 8 /* PC relative 22 bit shifted */ -+#define R_SPARC_HI22 9 /* High 22 bit */ -+#define R_SPARC_22 10 /* Direct 22 bit */ -+#define R_SPARC_13 11 /* Direct 13 bit */ -+#define R_SPARC_LO10 12 /* Truncated 10 bit */ -+#define R_SPARC_GOT10 13 /* Truncated 10 bit GOT entry */ -+#define R_SPARC_GOT13 14 /* 13 bit GOT entry */ -+#define R_SPARC_GOT22 15 /* 22 bit GOT entry shifted */ -+#define R_SPARC_PC10 16 /* PC relative 10 bit truncated */ -+#define R_SPARC_PC22 17 /* PC relative 22 bit shifted */ -+#define R_SPARC_WPLT30 18 /* 30 bit PC relative PLT address */ -+#define R_SPARC_COPY 19 /* Copy symbol at runtime */ -+#define R_SPARC_GLOB_DAT 20 /* Create GOT entry */ -+#define R_SPARC_JMP_SLOT 21 /* Create PLT entry */ -+#define R_SPARC_RELATIVE 22 /* Adjust by program base */ -+#define R_SPARC_UA32 23 /* Direct 32 bit unaligned */ -+ -+/* Additional Sparc64 relocs. */ -+ -+#define R_SPARC_PLT32 24 /* Direct 32 bit ref to PLT entry */ -+#define R_SPARC_HIPLT22 25 /* High 22 bit PLT entry */ -+#define R_SPARC_LOPLT10 26 /* Truncated 10 bit PLT entry */ -+#define R_SPARC_PCPLT32 27 /* PC rel 32 bit ref to PLT entry */ -+#define R_SPARC_PCPLT22 28 /* PC rel high 22 bit PLT entry */ -+#define R_SPARC_PCPLT10 29 /* PC rel trunc 10 bit PLT entry */ -+#define R_SPARC_10 30 /* Direct 10 bit */ -+#define R_SPARC_11 31 /* Direct 11 bit */ -+#define R_SPARC_64 32 /* Direct 64 bit */ -+#define R_SPARC_OLO10 33 /* 10bit with secondary 13bit addend */ -+#define R_SPARC_HH22 34 /* Top 22 bits of direct 64 bit */ -+#define R_SPARC_HM10 35 /* High middle 10 bits of ... */ -+#define R_SPARC_LM22 36 /* Low middle 22 bits of ... */ -+#define R_SPARC_PC_HH22 37 /* Top 22 bits of pc rel 64 bit */ -+#define R_SPARC_PC_HM10 38 /* High middle 10 bit of ... */ -+#define R_SPARC_PC_LM22 39 /* Low miggle 22 bits of ... */ -+#define R_SPARC_WDISP16 40 /* PC relative 16 bit shifted */ -+#define R_SPARC_WDISP19 41 /* PC relative 19 bit shifted */ -+#define R_SPARC_7 43 /* Direct 7 bit */ -+#define R_SPARC_5 44 /* Direct 5 bit */ -+#define R_SPARC_6 45 /* Direct 6 bit */ -+#define R_SPARC_DISP64 46 /* PC relative 64 bit */ -+#define R_SPARC_PLT64 47 /* Direct 64 bit ref to PLT entry */ -+#define R_SPARC_HIX22 48 /* High 22 bit complemented */ -+#define R_SPARC_LOX10 49 /* Truncated 11 bit complemented */ -+#define R_SPARC_H44 50 /* Direct high 12 of 44 bit */ -+#define R_SPARC_M44 51 /* Direct mid 22 of 44 bit */ -+#define R_SPARC_L44 52 /* Direct low 10 of 44 bit */ -+#define R_SPARC_REGISTER 53 /* Global register usage */ -+#define R_SPARC_UA64 54 /* Direct 64 bit unaligned */ -+#define R_SPARC_UA16 55 /* Direct 16 bit unaligned */ -+#define R_SPARC_TLS_GD_HI22 56 -+#define R_SPARC_TLS_GD_LO10 57 -+#define R_SPARC_TLS_GD_ADD 58 -+#define R_SPARC_TLS_GD_CALL 59 -+#define R_SPARC_TLS_LDM_HI22 60 -+#define R_SPARC_TLS_LDM_LO10 61 -+#define R_SPARC_TLS_LDM_ADD 62 -+#define R_SPARC_TLS_LDM_CALL 63 -+#define R_SPARC_TLS_LDO_HIX22 64 -+#define R_SPARC_TLS_LDO_LOX10 65 -+#define R_SPARC_TLS_LDO_ADD 66 -+#define R_SPARC_TLS_IE_HI22 67 -+#define R_SPARC_TLS_IE_LO10 68 -+#define R_SPARC_TLS_IE_LD 69 -+#define R_SPARC_TLS_IE_LDX 70 -+#define R_SPARC_TLS_IE_ADD 71 -+#define R_SPARC_TLS_LE_HIX22 72 -+#define R_SPARC_TLS_LE_LOX10 73 -+#define R_SPARC_TLS_DTPMOD32 74 -+#define R_SPARC_TLS_DTPMOD64 75 -+#define R_SPARC_TLS_DTPOFF32 76 -+#define R_SPARC_TLS_DTPOFF64 77 -+#define R_SPARC_TLS_TPOFF32 78 -+#define R_SPARC_TLS_TPOFF64 79 -+/* Keep this the last entry. */ -+#define R_SPARC_NUM 80 -+ -+/* For Sparc64, legal values for d_tag of Elf64_Dyn. */ -+ -+#define DT_SPARC_REGISTER 0x70000001 -+#define DT_SPARC_NUM 2 -+ -+/* Bits present in AT_HWCAP, primarily for Sparc32. */ -+ -+#define HWCAP_SPARC_FLUSH 1 /* The cpu supports flush insn. */ -+#define HWCAP_SPARC_STBAR 2 -+#define HWCAP_SPARC_SWAP 4 -+#define HWCAP_SPARC_MULDIV 8 -+#define HWCAP_SPARC_V9 16 /* The cpu is v9, so v8plus is ok. */ -+#define HWCAP_SPARC_ULTRA3 32 -+ -+/* MIPS R3000 specific definitions. */ -+ -+/* Legal values for e_flags field of Elf32_Ehdr. */ -+ -+#define EF_MIPS_NOREORDER 1 /* A .noreorder directive was used */ -+#define EF_MIPS_PIC 2 /* Contains PIC code */ -+#define EF_MIPS_CPIC 4 /* Uses PIC calling sequence */ -+#define EF_MIPS_XGOT 8 -+#define EF_MIPS_64BIT_WHIRL 16 -+#define EF_MIPS_ABI2 32 -+#define EF_MIPS_ABI_ON32 64 -+#define EF_MIPS_ARCH 0xf0000000 /* MIPS architecture level */ -+ -+/* Legal values for MIPS architecture level. */ -+ -+#define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ -+#define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ -+#define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ -+#define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ -+#define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ -+#define EF_MIPS_ARCH_32 0x60000000 /* MIPS32 code. */ -+#define EF_MIPS_ARCH_64 0x70000000 /* MIPS64 code. */ -+ -+/* The following are non-official names and should not be used. */ -+ -+#define E_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ -+#define E_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ -+#define E_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ -+#define E_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ -+#define E_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ -+#define E_MIPS_ARCH_32 0x60000000 /* MIPS32 code. */ -+#define E_MIPS_ARCH_64 0x70000000 /* MIPS64 code. */ -+ -+/* Special section indices. */ -+ -+#define SHN_MIPS_ACOMMON 0xff00 /* Allocated common symbols */ -+#define SHN_MIPS_TEXT 0xff01 /* Allocated test symbols. */ -+#define SHN_MIPS_DATA 0xff02 /* Allocated data symbols. */ -+#define SHN_MIPS_SCOMMON 0xff03 /* Small common symbols */ -+#define SHN_MIPS_SUNDEFINED 0xff04 /* Small undefined symbols */ -+ -+/* Legal values for sh_type field of Elf32_Shdr. */ -+ -+#define SHT_MIPS_LIBLIST 0x70000000 /* Shared objects used in link */ -+#define SHT_MIPS_MSYM 0x70000001 -+#define SHT_MIPS_CONFLICT 0x70000002 /* Conflicting symbols */ -+#define SHT_MIPS_GPTAB 0x70000003 /* Global data area sizes */ -+#define SHT_MIPS_UCODE 0x70000004 /* Reserved for SGI/MIPS compilers */ -+#define SHT_MIPS_DEBUG 0x70000005 /* MIPS ECOFF debugging information*/ -+#define SHT_MIPS_REGINFO 0x70000006 /* Register usage information */ -+#define SHT_MIPS_PACKAGE 0x70000007 -+#define SHT_MIPS_PACKSYM 0x70000008 -+#define SHT_MIPS_RELD 0x70000009 -+#define SHT_MIPS_IFACE 0x7000000b -+#define SHT_MIPS_CONTENT 0x7000000c -+#define SHT_MIPS_OPTIONS 0x7000000d /* Miscellaneous options. */ -+#define SHT_MIPS_SHDR 0x70000010 -+#define SHT_MIPS_FDESC 0x70000011 -+#define SHT_MIPS_EXTSYM 0x70000012 -+#define SHT_MIPS_DENSE 0x70000013 -+#define SHT_MIPS_PDESC 0x70000014 -+#define SHT_MIPS_LOCSYM 0x70000015 -+#define SHT_MIPS_AUXSYM 0x70000016 -+#define SHT_MIPS_OPTSYM 0x70000017 -+#define SHT_MIPS_LOCSTR 0x70000018 -+#define SHT_MIPS_LINE 0x70000019 -+#define SHT_MIPS_RFDESC 0x7000001a -+#define SHT_MIPS_DELTASYM 0x7000001b -+#define SHT_MIPS_DELTAINST 0x7000001c -+#define SHT_MIPS_DELTACLASS 0x7000001d -+#define SHT_MIPS_DWARF 0x7000001e /* DWARF debugging information. */ -+#define SHT_MIPS_DELTADECL 0x7000001f -+#define SHT_MIPS_SYMBOL_LIB 0x70000020 -+#define SHT_MIPS_EVENTS 0x70000021 /* Event section. */ -+#define SHT_MIPS_TRANSLATE 0x70000022 -+#define SHT_MIPS_PIXIE 0x70000023 -+#define SHT_MIPS_XLATE 0x70000024 -+#define SHT_MIPS_XLATE_DEBUG 0x70000025 -+#define SHT_MIPS_WHIRL 0x70000026 -+#define SHT_MIPS_EH_REGION 0x70000027 -+#define SHT_MIPS_XLATE_OLD 0x70000028 -+#define SHT_MIPS_PDR_EXCEPTION 0x70000029 -+ -+/* Legal values for sh_flags field of Elf32_Shdr. */ -+ -+#define SHF_MIPS_GPREL 0x10000000 /* Must be part of global data area */ -+#define SHF_MIPS_MERGE 0x20000000 -+#define SHF_MIPS_ADDR 0x40000000 -+#define SHF_MIPS_STRINGS 0x80000000 -+#define SHF_MIPS_NOSTRIP 0x08000000 -+#define SHF_MIPS_LOCAL 0x04000000 -+#define SHF_MIPS_NAMES 0x02000000 -+#define SHF_MIPS_NODUPE 0x01000000 -+ -+ -+/* Symbol tables. */ -+ -+/* MIPS specific values for `st_other'. */ -+#define STO_MIPS_DEFAULT 0x0 -+#define STO_MIPS_INTERNAL 0x1 -+#define STO_MIPS_HIDDEN 0x2 -+#define STO_MIPS_PROTECTED 0x3 -+#define STO_MIPS_SC_ALIGN_UNUSED 0xff -+ -+/* MIPS specific values for `st_info'. */ -+#define STB_MIPS_SPLIT_COMMON 13 -+ -+/* Entries found in sections of type SHT_MIPS_GPTAB. */ -+ -+typedef union -+{ -+ struct -+ { -+ Elf32_Word gt_current_g_value; /* -G value used for compilation */ -+ Elf32_Word gt_unused; /* Not used */ -+ } gt_header; /* First entry in section */ -+ struct -+ { -+ Elf32_Word gt_g_value; /* If this value were used for -G */ -+ Elf32_Word gt_bytes; /* This many bytes would be used */ -+ } gt_entry; /* Subsequent entries in section */ -+} Elf32_gptab; -+ -+/* Entry found in sections of type SHT_MIPS_REGINFO. */ -+ -+typedef struct -+{ -+ Elf32_Word ri_gprmask; /* General registers used */ -+ Elf32_Word ri_cprmask[4]; /* Coprocessor registers used */ -+ Elf32_Sword ri_gp_value; /* $gp register value */ -+} Elf32_RegInfo; -+ -+/* Entries found in sections of type SHT_MIPS_OPTIONS. */ -+ -+typedef struct -+{ -+ unsigned char kind; /* Determines interpretation of the -+ variable part of descriptor. */ -+ unsigned char size; /* Size of descriptor, including header. */ -+ Elf32_Section section; /* Section header index of section affected, -+ 0 for global options. */ -+ Elf32_Word info; /* Kind-specific information. */ -+} Elf_Options; -+ -+/* Values for `kind' field in Elf_Options. */ -+ -+#define ODK_NULL 0 /* Undefined. */ -+#define ODK_REGINFO 1 /* Register usage information. */ -+#define ODK_EXCEPTIONS 2 /* Exception processing options. */ -+#define ODK_PAD 3 /* Section padding options. */ -+#define ODK_HWPATCH 4 /* Hardware workarounds performed */ -+#define ODK_FILL 5 /* record the fill value used by the linker. */ -+#define ODK_TAGS 6 /* reserve space for desktop tools to write. */ -+#define ODK_HWAND 7 /* HW workarounds. 'AND' bits when merging. */ -+#define ODK_HWOR 8 /* HW workarounds. 'OR' bits when merging. */ -+ -+/* Values for `info' in Elf_Options for ODK_EXCEPTIONS entries. */ -+ -+#define OEX_FPU_MIN 0x1f /* FPE's which MUST be enabled. */ -+#define OEX_FPU_MAX 0x1f00 /* FPE's which MAY be enabled. */ -+#define OEX_PAGE0 0x10000 /* page zero must be mapped. */ -+#define OEX_SMM 0x20000 /* Force sequential memory mode? */ -+#define OEX_FPDBUG 0x40000 /* Force floating point debug mode? */ -+#define OEX_PRECISEFP OEX_FPDBUG -+#define OEX_DISMISS 0x80000 /* Dismiss invalid address faults? */ -+ -+#define OEX_FPU_INVAL 0x10 -+#define OEX_FPU_DIV0 0x08 -+#define OEX_FPU_OFLO 0x04 -+#define OEX_FPU_UFLO 0x02 -+#define OEX_FPU_INEX 0x01 -+ -+/* Masks for `info' in Elf_Options for an ODK_HWPATCH entry. */ -+ -+#define OHW_R4KEOP 0x1 /* R4000 end-of-page patch. */ -+#define OHW_R8KPFETCH 0x2 /* may need R8000 prefetch patch. */ -+#define OHW_R5KEOP 0x4 /* R5000 end-of-page patch. */ -+#define OHW_R5KCVTL 0x8 /* R5000 cvt.[ds].l bug. clean=1. */ -+ -+#define OPAD_PREFIX 0x1 -+#define OPAD_POSTFIX 0x2 -+#define OPAD_SYMBOL 0x4 -+ -+/* Entry found in `.options' section. */ -+ -+typedef struct -+{ -+ Elf32_Word hwp_flags1; /* Extra flags. */ -+ Elf32_Word hwp_flags2; /* Extra flags. */ -+} Elf_Options_Hw; -+ -+/* Masks for `info' in ElfOptions for ODK_HWAND and ODK_HWOR entries. */ -+ -+#define OHWA0_R4KEOP_CHECKED 0x00000001 -+#define OHWA1_R4KEOP_CLEAN 0x00000002 -+ -+/* MIPS relocs. */ -+ -+#define R_MIPS_NONE 0 /* No reloc */ -+#define R_MIPS_16 1 /* Direct 16 bit */ -+#define R_MIPS_32 2 /* Direct 32 bit */ -+#define R_MIPS_REL32 3 /* PC relative 32 bit */ -+#define R_MIPS_26 4 /* Direct 26 bit shifted */ -+#define R_MIPS_HI16 5 /* High 16 bit */ -+#define R_MIPS_LO16 6 /* Low 16 bit */ -+#define R_MIPS_GPREL16 7 /* GP relative 16 bit */ -+#define R_MIPS_LITERAL 8 /* 16 bit literal entry */ -+#define R_MIPS_GOT16 9 /* 16 bit GOT entry */ -+#define R_MIPS_PC16 10 /* PC relative 16 bit */ -+#define R_MIPS_CALL16 11 /* 16 bit GOT entry for function */ -+#define R_MIPS_GPREL32 12 /* GP relative 32 bit */ -+ -+#define R_MIPS_SHIFT5 16 -+#define R_MIPS_SHIFT6 17 -+#define R_MIPS_64 18 -+#define R_MIPS_GOT_DISP 19 -+#define R_MIPS_GOT_PAGE 20 -+#define R_MIPS_GOT_OFST 21 -+#define R_MIPS_GOT_HI16 22 -+#define R_MIPS_GOT_LO16 23 -+#define R_MIPS_SUB 24 -+#define R_MIPS_INSERT_A 25 -+#define R_MIPS_INSERT_B 26 -+#define R_MIPS_DELETE 27 -+#define R_MIPS_HIGHER 28 -+#define R_MIPS_HIGHEST 29 -+#define R_MIPS_CALL_HI16 30 -+#define R_MIPS_CALL_LO16 31 -+#define R_MIPS_SCN_DISP 32 -+#define R_MIPS_REL16 33 -+#define R_MIPS_ADD_IMMEDIATE 34 -+#define R_MIPS_PJUMP 35 -+#define R_MIPS_RELGOT 36 -+#define R_MIPS_JALR 37 -+/* Keep this the last entry. */ -+#define R_MIPS_NUM 38 -+ -+/* Legal values for p_type field of Elf32_Phdr. */ -+ -+#define PT_MIPS_REGINFO 0x70000000 /* Register usage information */ -+#define PT_MIPS_RTPROC 0x70000001 /* Runtime procedure table. */ -+#define PT_MIPS_OPTIONS 0x70000002 -+ -+/* Special program header types. */ -+ -+#define PF_MIPS_LOCAL 0x10000000 -+ -+/* Legal values for d_tag field of Elf32_Dyn. */ -+ -+#define DT_MIPS_RLD_VERSION 0x70000001 /* Runtime linker interface version */ -+#define DT_MIPS_TIME_STAMP 0x70000002 /* Timestamp */ -+#define DT_MIPS_ICHECKSUM 0x70000003 /* Checksum */ -+#define DT_MIPS_IVERSION 0x70000004 /* Version string (string tbl index) */ -+#define DT_MIPS_FLAGS 0x70000005 /* Flags */ -+#define DT_MIPS_BASE_ADDRESS 0x70000006 /* Base address */ -+#define DT_MIPS_MSYM 0x70000007 -+#define DT_MIPS_CONFLICT 0x70000008 /* Address of CONFLICT section */ -+#define DT_MIPS_LIBLIST 0x70000009 /* Address of LIBLIST section */ -+#define DT_MIPS_LOCAL_GOTNO 0x7000000a /* Number of local GOT entries */ -+#define DT_MIPS_CONFLICTNO 0x7000000b /* Number of CONFLICT entries */ -+#define DT_MIPS_LIBLISTNO 0x70000010 /* Number of LIBLIST entries */ -+#define DT_MIPS_SYMTABNO 0x70000011 /* Number of DYNSYM entries */ -+#define DT_MIPS_UNREFEXTNO 0x70000012 /* First external DYNSYM */ -+#define DT_MIPS_GOTSYM 0x70000013 /* First GOT entry in DYNSYM */ -+#define DT_MIPS_HIPAGENO 0x70000014 /* Number of GOT page table entries */ -+#define DT_MIPS_RLD_MAP 0x70000016 /* Address of run time loader map. */ -+#define DT_MIPS_DELTA_CLASS 0x70000017 /* Delta C++ class definition. */ -+#define DT_MIPS_DELTA_CLASS_NO 0x70000018 /* Number of entries in -+ DT_MIPS_DELTA_CLASS. */ -+#define DT_MIPS_DELTA_INSTANCE 0x70000019 /* Delta C++ class instances. */ -+#define DT_MIPS_DELTA_INSTANCE_NO 0x7000001a /* Number of entries in -+ DT_MIPS_DELTA_INSTANCE. */ -+#define DT_MIPS_DELTA_RELOC 0x7000001b /* Delta relocations. */ -+#define DT_MIPS_DELTA_RELOC_NO 0x7000001c /* Number of entries in -+ DT_MIPS_DELTA_RELOC. */ -+#define DT_MIPS_DELTA_SYM 0x7000001d /* Delta symbols that Delta -+ relocations refer to. */ -+#define DT_MIPS_DELTA_SYM_NO 0x7000001e /* Number of entries in -+ DT_MIPS_DELTA_SYM. */ -+#define DT_MIPS_DELTA_CLASSSYM 0x70000020 /* Delta symbols that hold the -+ class declaration. */ -+#define DT_MIPS_DELTA_CLASSSYM_NO 0x70000021 /* Number of entries in -+ DT_MIPS_DELTA_CLASSSYM. */ -+#define DT_MIPS_CXX_FLAGS 0x70000022 /* Flags indicating for C++ flavor. */ -+#define DT_MIPS_PIXIE_INIT 0x70000023 -+#define DT_MIPS_SYMBOL_LIB 0x70000024 -+#define DT_MIPS_LOCALPAGE_GOTIDX 0x70000025 -+#define DT_MIPS_LOCAL_GOTIDX 0x70000026 -+#define DT_MIPS_HIDDEN_GOTIDX 0x70000027 -+#define DT_MIPS_PROTECTED_GOTIDX 0x70000028 -+#define DT_MIPS_OPTIONS 0x70000029 /* Address of .options. */ -+#define DT_MIPS_INTERFACE 0x7000002a /* Address of .interface. */ -+#define DT_MIPS_DYNSTR_ALIGN 0x7000002b -+#define DT_MIPS_INTERFACE_SIZE 0x7000002c /* Size of the .interface section. */ -+#define DT_MIPS_RLD_TEXT_RESOLVE_ADDR 0x7000002d /* Address of rld_text_rsolve -+ function stored in GOT. */ -+#define DT_MIPS_PERF_SUFFIX 0x7000002e /* Default suffix of dso to be added -+ by rld on dlopen() calls. */ -+#define DT_MIPS_COMPACT_SIZE 0x7000002f /* (O32)Size of compact rel section. */ -+#define DT_MIPS_GP_VALUE 0x70000030 /* GP value for aux GOTs. */ -+#define DT_MIPS_AUX_DYNAMIC 0x70000031 /* Address of aux .dynamic. */ -+#define DT_MIPS_NUM 0x32 -+ -+/* Legal values for DT_MIPS_FLAGS Elf32_Dyn entry. */ -+ -+#define RHF_NONE 0 /* No flags */ -+#define RHF_QUICKSTART (1 << 0) /* Use quickstart */ -+#define RHF_NOTPOT (1 << 1) /* Hash size not power of 2 */ -+#define RHF_NO_LIBRARY_REPLACEMENT (1 << 2) /* Ignore LD_LIBRARY_PATH */ -+#define RHF_NO_MOVE (1 << 3) -+#define RHF_SGI_ONLY (1 << 4) -+#define RHF_GUARANTEE_INIT (1 << 5) -+#define RHF_DELTA_C_PLUS_PLUS (1 << 6) -+#define RHF_GUARANTEE_START_INIT (1 << 7) -+#define RHF_PIXIE (1 << 8) -+#define RHF_DEFAULT_DELAY_LOAD (1 << 9) -+#define RHF_REQUICKSTART (1 << 10) -+#define RHF_REQUICKSTARTED (1 << 11) -+#define RHF_CORD (1 << 12) -+#define RHF_NO_UNRES_UNDEF (1 << 13) -+#define RHF_RLD_ORDER_SAFE (1 << 14) -+ -+/* Entries found in sections of type SHT_MIPS_LIBLIST. */ -+ -+typedef struct -+{ -+ Elf32_Word l_name; /* Name (string table index) */ -+ Elf32_Word l_time_stamp; /* Timestamp */ -+ Elf32_Word l_checksum; /* Checksum */ -+ Elf32_Word l_version; /* Interface version */ -+ Elf32_Word l_flags; /* Flags */ -+} Elf32_Lib; -+ -+typedef struct -+{ -+ Elf64_Word l_name; /* Name (string table index) */ -+ Elf64_Word l_time_stamp; /* Timestamp */ -+ Elf64_Word l_checksum; /* Checksum */ -+ Elf64_Word l_version; /* Interface version */ -+ Elf64_Word l_flags; /* Flags */ -+} Elf64_Lib; -+ -+ -+/* Legal values for l_flags. */ -+ -+#define LL_NONE 0 -+#define LL_EXACT_MATCH (1 << 0) /* Require exact match */ -+#define LL_IGNORE_INT_VER (1 << 1) /* Ignore interface version */ -+#define LL_REQUIRE_MINOR (1 << 2) -+#define LL_EXPORTS (1 << 3) -+#define LL_DELAY_LOAD (1 << 4) -+#define LL_DELTA (1 << 5) -+ -+/* Entries found in sections of type SHT_MIPS_CONFLICT. */ -+ -+typedef Elf32_Addr Elf32_Conflict; -+ -+ -+/* HPPA specific definitions. */ -+ -+/* Legal values for e_flags field of Elf32_Ehdr. */ -+ -+#define EF_PARISC_TRAPNIL 0x00010000 /* Trap nil pointer dereference. */ -+#define EF_PARISC_EXT 0x00020000 /* Program uses arch. extensions. */ -+#define EF_PARISC_LSB 0x00040000 /* Program expects little endian. */ -+#define EF_PARISC_WIDE 0x00080000 /* Program expects wide mode. */ -+#define EF_PARISC_NO_KABP 0x00100000 /* No kernel assisted branch -+ prediction. */ -+#define EF_PARISC_LAZYSWAP 0x00400000 /* Allow lazy swapping. */ -+#define EF_PARISC_ARCH 0x0000ffff /* Architecture version. */ -+ -+/* Defined values for `e_flags & EF_PARISC_ARCH' are: */ -+ -+#define EFA_PARISC_1_0 0x020b /* PA-RISC 1.0 big-endian. */ -+#define EFA_PARISC_1_1 0x0210 /* PA-RISC 1.1 big-endian. */ -+#define EFA_PARISC_2_0 0x0214 /* PA-RISC 2.0 big-endian. */ -+ -+/* Additional section indeces. */ -+ -+#define SHN_PARISC_ANSI_COMMON 0xff00 /* Section for tenatively declared -+ symbols in ANSI C. */ -+#define SHN_PARISC_HUGE_COMMON 0xff01 /* Common blocks in huge model. */ -+ -+/* Legal values for sh_type field of Elf32_Shdr. */ -+ -+#define SHT_PARISC_EXT 0x70000000 /* Contains product specific ext. */ -+#define SHT_PARISC_UNWIND 0x70000001 /* Unwind information. */ -+#define SHT_PARISC_DOC 0x70000002 /* Debug info for optimized code. */ -+ -+/* Legal values for sh_flags field of Elf32_Shdr. */ -+ -+#define SHF_PARISC_SHORT 0x20000000 /* Section with short addressing. */ -+#define SHF_PARISC_HUGE 0x40000000 /* Section far from gp. */ -+#define SHF_PARISC_SBP 0x80000000 /* Static branch prediction code. */ -+ -+/* Legal values for ST_TYPE subfield of st_info (symbol type). */ -+ -+#define STT_PARISC_MILLICODE 13 /* Millicode function entry point. */ -+ -+#define STT_HP_OPAQUE (STT_LOOS + 0x1) -+#define STT_HP_STUB (STT_LOOS + 0x2) -+ -+/* HPPA relocs. */ -+ -+#define R_PARISC_NONE 0 /* No reloc. */ -+#define R_PARISC_DIR32 1 /* Direct 32-bit reference. */ -+#define R_PARISC_DIR21L 2 /* Left 21 bits of eff. address. */ -+#define R_PARISC_DIR17R 3 /* Right 17 bits of eff. address. */ -+#define R_PARISC_DIR17F 4 /* 17 bits of eff. address. */ -+#define R_PARISC_DIR14R 6 /* Right 14 bits of eff. address. */ -+#define R_PARISC_PCREL32 9 /* 32-bit rel. address. */ -+#define R_PARISC_PCREL21L 10 /* Left 21 bits of rel. address. */ -+#define R_PARISC_PCREL17R 11 /* Right 17 bits of rel. address. */ -+#define R_PARISC_PCREL17F 12 /* 17 bits of rel. address. */ -+#define R_PARISC_PCREL14R 14 /* Right 14 bits of rel. address. */ -+#define R_PARISC_DPREL21L 18 /* Left 21 bits of rel. address. */ -+#define R_PARISC_DPREL14R 22 /* Right 14 bits of rel. address. */ -+#define R_PARISC_GPREL21L 26 /* GP-relative, left 21 bits. */ -+#define R_PARISC_GPREL14R 30 /* GP-relative, right 14 bits. */ -+#define R_PARISC_LTOFF21L 34 /* LT-relative, left 21 bits. */ -+#define R_PARISC_LTOFF14R 38 /* LT-relative, right 14 bits. */ -+#define R_PARISC_SECREL32 41 /* 32 bits section rel. address. */ -+#define R_PARISC_SEGBASE 48 /* No relocation, set segment base. */ -+#define R_PARISC_SEGREL32 49 /* 32 bits segment rel. address. */ -+#define R_PARISC_PLTOFF21L 50 /* PLT rel. address, left 21 bits. */ -+#define R_PARISC_PLTOFF14R 54 /* PLT rel. address, right 14 bits. */ -+#define R_PARISC_LTOFF_FPTR32 57 /* 32 bits LT-rel. function pointer. */ -+#define R_PARISC_LTOFF_FPTR21L 58 /* LT-rel. fct ptr, left 21 bits. */ -+#define R_PARISC_LTOFF_FPTR14R 62 /* LT-rel. fct ptr, right 14 bits. */ -+#define R_PARISC_FPTR64 64 /* 64 bits function address. */ -+#define R_PARISC_PLABEL32 65 /* 32 bits function address. */ -+#define R_PARISC_PCREL64 72 /* 64 bits PC-rel. address. */ -+#define R_PARISC_PCREL22F 74 /* 22 bits PC-rel. address. */ -+#define R_PARISC_PCREL14WR 75 /* PC-rel. address, right 14 bits. */ -+#define R_PARISC_PCREL14DR 76 /* PC rel. address, right 14 bits. */ -+#define R_PARISC_PCREL16F 77 /* 16 bits PC-rel. address. */ -+#define R_PARISC_PCREL16WF 78 /* 16 bits PC-rel. address. */ -+#define R_PARISC_PCREL16DF 79 /* 16 bits PC-rel. address. */ -+#define R_PARISC_DIR64 80 /* 64 bits of eff. address. */ -+#define R_PARISC_DIR14WR 83 /* 14 bits of eff. address. */ -+#define R_PARISC_DIR14DR 84 /* 14 bits of eff. address. */ -+#define R_PARISC_DIR16F 85 /* 16 bits of eff. address. */ -+#define R_PARISC_DIR16WF 86 /* 16 bits of eff. address. */ -+#define R_PARISC_DIR16DF 87 /* 16 bits of eff. address. */ -+#define R_PARISC_GPREL64 88 /* 64 bits of GP-rel. address. */ -+#define R_PARISC_GPREL14WR 91 /* GP-rel. address, right 14 bits. */ -+#define R_PARISC_GPREL14DR 92 /* GP-rel. address, right 14 bits. */ -+#define R_PARISC_GPREL16F 93 /* 16 bits GP-rel. address. */ -+#define R_PARISC_GPREL16WF 94 /* 16 bits GP-rel. address. */ -+#define R_PARISC_GPREL16DF 95 /* 16 bits GP-rel. address. */ -+#define R_PARISC_LTOFF64 96 /* 64 bits LT-rel. address. */ -+#define R_PARISC_LTOFF14WR 99 /* LT-rel. address, right 14 bits. */ -+#define R_PARISC_LTOFF14DR 100 /* LT-rel. address, right 14 bits. */ -+#define R_PARISC_LTOFF16F 101 /* 16 bits LT-rel. address. */ -+#define R_PARISC_LTOFF16WF 102 /* 16 bits LT-rel. address. */ -+#define R_PARISC_LTOFF16DF 103 /* 16 bits LT-rel. address. */ -+#define R_PARISC_SECREL64 104 /* 64 bits section rel. address. */ -+#define R_PARISC_SEGREL64 112 /* 64 bits segment rel. address. */ -+#define R_PARISC_PLTOFF14WR 115 /* PLT-rel. address, right 14 bits. */ -+#define R_PARISC_PLTOFF14DR 116 /* PLT-rel. address, right 14 bits. */ -+#define R_PARISC_PLTOFF16F 117 /* 16 bits LT-rel. address. */ -+#define R_PARISC_PLTOFF16WF 118 /* 16 bits PLT-rel. address. */ -+#define R_PARISC_PLTOFF16DF 119 /* 16 bits PLT-rel. address. */ -+#define R_PARISC_LTOFF_FPTR64 120 /* 64 bits LT-rel. function ptr. */ -+#define R_PARISC_LTOFF_FPTR14WR 123 /* LT-rel. fct. ptr., right 14 bits. */ -+#define R_PARISC_LTOFF_FPTR14DR 124 /* LT-rel. fct. ptr., right 14 bits. */ -+#define R_PARISC_LTOFF_FPTR16F 125 /* 16 bits LT-rel. function ptr. */ -+#define R_PARISC_LTOFF_FPTR16WF 126 /* 16 bits LT-rel. function ptr. */ -+#define R_PARISC_LTOFF_FPTR16DF 127 /* 16 bits LT-rel. function ptr. */ -+#define R_PARISC_LORESERVE 128 -+#define R_PARISC_COPY 128 /* Copy relocation. */ -+#define R_PARISC_IPLT 129 /* Dynamic reloc, imported PLT */ -+#define R_PARISC_EPLT 130 /* Dynamic reloc, exported PLT */ -+#define R_PARISC_TPREL32 153 /* 32 bits TP-rel. address. */ -+#define R_PARISC_TPREL21L 154 /* TP-rel. address, left 21 bits. */ -+#define R_PARISC_TPREL14R 158 /* TP-rel. address, right 14 bits. */ -+#define R_PARISC_LTOFF_TP21L 162 /* LT-TP-rel. address, left 21 bits. */ -+#define R_PARISC_LTOFF_TP14R 166 /* LT-TP-rel. address, right 14 bits.*/ -+#define R_PARISC_LTOFF_TP14F 167 /* 14 bits LT-TP-rel. address. */ -+#define R_PARISC_TPREL64 216 /* 64 bits TP-rel. address. */ -+#define R_PARISC_TPREL14WR 219 /* TP-rel. address, right 14 bits. */ -+#define R_PARISC_TPREL14DR 220 /* TP-rel. address, right 14 bits. */ -+#define R_PARISC_TPREL16F 221 /* 16 bits TP-rel. address. */ -+#define R_PARISC_TPREL16WF 222 /* 16 bits TP-rel. address. */ -+#define R_PARISC_TPREL16DF 223 /* 16 bits TP-rel. address. */ -+#define R_PARISC_LTOFF_TP64 224 /* 64 bits LT-TP-rel. address. */ -+#define R_PARISC_LTOFF_TP14WR 227 /* LT-TP-rel. address, right 14 bits.*/ -+#define R_PARISC_LTOFF_TP14DR 228 /* LT-TP-rel. address, right 14 bits.*/ -+#define R_PARISC_LTOFF_TP16F 229 /* 16 bits LT-TP-rel. address. */ -+#define R_PARISC_LTOFF_TP16WF 230 /* 16 bits LT-TP-rel. address. */ -+#define R_PARISC_LTOFF_TP16DF 231 /* 16 bits LT-TP-rel. address. */ -+#define R_PARISC_HIRESERVE 255 -+ -+/* Legal values for p_type field of Elf32_Phdr/Elf64_Phdr. */ -+ -+#define PT_HP_TLS (PT_LOOS + 0x0) -+#define PT_HP_CORE_NONE (PT_LOOS + 0x1) -+#define PT_HP_CORE_VERSION (PT_LOOS + 0x2) -+#define PT_HP_CORE_KERNEL (PT_LOOS + 0x3) -+#define PT_HP_CORE_COMM (PT_LOOS + 0x4) -+#define PT_HP_CORE_PROC (PT_LOOS + 0x5) -+#define PT_HP_CORE_LOADABLE (PT_LOOS + 0x6) -+#define PT_HP_CORE_STACK (PT_LOOS + 0x7) -+#define PT_HP_CORE_SHM (PT_LOOS + 0x8) -+#define PT_HP_CORE_MMF (PT_LOOS + 0x9) -+#define PT_HP_PARALLEL (PT_LOOS + 0x10) -+#define PT_HP_FASTBIND (PT_LOOS + 0x11) -+#define PT_HP_OPT_ANNOT (PT_LOOS + 0x12) -+#define PT_HP_HSL_ANNOT (PT_LOOS + 0x13) -+#define PT_HP_STACK (PT_LOOS + 0x14) -+ -+#define PT_PARISC_ARCHEXT 0x70000000 -+#define PT_PARISC_UNWIND 0x70000001 -+ -+/* Legal values for p_flags field of Elf32_Phdr/Elf64_Phdr. */ -+ -+#define PF_PARISC_SBP 0x08000000 -+ -+#define PF_HP_PAGE_SIZE 0x00100000 -+#define PF_HP_FAR_SHARED 0x00200000 -+#define PF_HP_NEAR_SHARED 0x00400000 -+#define PF_HP_CODE 0x01000000 -+#define PF_HP_MODIFY 0x02000000 -+#define PF_HP_LAZYSWAP 0x04000000 -+#define PF_HP_SBP 0x08000000 -+ -+ -+/* Alpha specific definitions. */ -+ -+/* Legal values for e_flags field of Elf64_Ehdr. */ -+ -+#define EF_ALPHA_32BIT 1 /* All addresses must be < 2GB. */ -+#define EF_ALPHA_CANRELAX 2 /* Relocations for relaxing exist. */ -+ -+/* Legal values for sh_type field of Elf64_Shdr. */ -+ -+/* These two are primerily concerned with ECOFF debugging info. */ -+#define SHT_ALPHA_DEBUG 0x70000001 -+#define SHT_ALPHA_REGINFO 0x70000002 -+ -+/* Legal values for sh_flags field of Elf64_Shdr. */ -+ -+#define SHF_ALPHA_GPREL 0x10000000 -+ -+/* Legal values for st_other field of Elf64_Sym. */ -+#define STO_ALPHA_NOPV 0x80 /* No PV required. */ -+#define STO_ALPHA_STD_GPLOAD 0x88 /* PV only used for initial ldgp. */ -+ -+/* Alpha relocs. */ -+ -+#define R_ALPHA_NONE 0 /* No reloc */ -+#define R_ALPHA_REFLONG 1 /* Direct 32 bit */ -+#define R_ALPHA_REFQUAD 2 /* Direct 64 bit */ -+#define R_ALPHA_GPREL32 3 /* GP relative 32 bit */ -+#define R_ALPHA_LITERAL 4 /* GP relative 16 bit w/optimization */ -+#define R_ALPHA_LITUSE 5 /* Optimization hint for LITERAL */ -+#define R_ALPHA_GPDISP 6 /* Add displacement to GP */ -+#define R_ALPHA_BRADDR 7 /* PC+4 relative 23 bit shifted */ -+#define R_ALPHA_HINT 8 /* PC+4 relative 16 bit shifted */ -+#define R_ALPHA_SREL16 9 /* PC relative 16 bit */ -+#define R_ALPHA_SREL32 10 /* PC relative 32 bit */ -+#define R_ALPHA_SREL64 11 /* PC relative 64 bit */ -+#define R_ALPHA_GPRELHIGH 17 /* GP relative 32 bit, high 16 bits */ -+#define R_ALPHA_GPRELLOW 18 /* GP relative 32 bit, low 16 bits */ -+#define R_ALPHA_GPREL16 19 /* GP relative 16 bit */ -+#define R_ALPHA_COPY 24 /* Copy symbol at runtime */ -+#define R_ALPHA_GLOB_DAT 25 /* Create GOT entry */ -+#define R_ALPHA_JMP_SLOT 26 /* Create PLT entry */ -+#define R_ALPHA_RELATIVE 27 /* Adjust by program base */ -+#define R_ALPHA_TLS_GD_HI 28 -+#define R_ALPHA_TLSGD 29 -+#define R_ALPHA_TLS_LDM 30 -+#define R_ALPHA_DTPMOD64 31 -+#define R_ALPHA_GOTDTPREL 32 -+#define R_ALPHA_DTPREL64 33 -+#define R_ALPHA_DTPRELHI 34 -+#define R_ALPHA_DTPRELLO 35 -+#define R_ALPHA_DTPREL16 36 -+#define R_ALPHA_GOTTPREL 37 -+#define R_ALPHA_TPREL64 38 -+#define R_ALPHA_TPRELHI 39 -+#define R_ALPHA_TPRELLO 40 -+#define R_ALPHA_TPREL16 41 -+/* Keep this the last entry. */ -+#define R_ALPHA_NUM 46 -+ -+/* Magic values of the LITUSE relocation addend. */ -+#define LITUSE_ALPHA_ADDR 0 -+#define LITUSE_ALPHA_BASE 1 -+#define LITUSE_ALPHA_BYTOFF 2 -+#define LITUSE_ALPHA_JSR 3 -+#define LITUSE_ALPHA_TLS_GD 4 -+#define LITUSE_ALPHA_TLS_LDM 5 -+ -+ -+/* PowerPC specific declarations */ -+ -+/* Values for Elf32/64_Ehdr.e_flags. */ -+#define EF_PPC_EMB 0x80000000 /* PowerPC embedded flag */ -+ -+/* Cygnus local bits below */ -+#define EF_PPC_RELOCATABLE 0x00010000 /* PowerPC -mrelocatable flag*/ -+#define EF_PPC_RELOCATABLE_LIB 0x00008000 /* PowerPC -mrelocatable-lib -+ flag */ -+ -+/* PowerPC relocations defined by the ABIs */ -+#define R_PPC_NONE 0 -+#define R_PPC_ADDR32 1 /* 32bit absolute address */ -+#define R_PPC_ADDR24 2 /* 26bit address, 2 bits ignored. */ -+#define R_PPC_ADDR16 3 /* 16bit absolute address */ -+#define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */ -+#define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */ -+#define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */ -+#define R_PPC_ADDR14 7 /* 16bit address, 2 bits ignored */ -+#define R_PPC_ADDR14_BRTAKEN 8 -+#define R_PPC_ADDR14_BRNTAKEN 9 -+#define R_PPC_REL24 10 /* PC relative 26 bit */ -+#define R_PPC_REL14 11 /* PC relative 16 bit */ -+#define R_PPC_REL14_BRTAKEN 12 -+#define R_PPC_REL14_BRNTAKEN 13 -+#define R_PPC_GOT16 14 -+#define R_PPC_GOT16_LO 15 -+#define R_PPC_GOT16_HI 16 -+#define R_PPC_GOT16_HA 17 -+#define R_PPC_PLTREL24 18 -+#define R_PPC_COPY 19 -+#define R_PPC_GLOB_DAT 20 -+#define R_PPC_JMP_SLOT 21 -+#define R_PPC_RELATIVE 22 -+#define R_PPC_LOCAL24PC 23 -+#define R_PPC_UADDR32 24 -+#define R_PPC_UADDR16 25 -+#define R_PPC_REL32 26 -+#define R_PPC_PLT32 27 -+#define R_PPC_PLTREL32 28 -+#define R_PPC_PLT16_LO 29 -+#define R_PPC_PLT16_HI 30 -+#define R_PPC_PLT16_HA 31 -+#define R_PPC_SDAREL16 32 -+#define R_PPC_SECTOFF 33 -+#define R_PPC_SECTOFF_LO 34 -+#define R_PPC_SECTOFF_HI 35 -+#define R_PPC_SECTOFF_HA 36 -+ -+/* PowerPC relocations defined for the TLS access ABI. */ -+#define R_PPC_TLS 67 /* none (sym+add)@tls */ -+#define R_PPC_DTPMOD32 68 /* word32 (sym+add)@dtpmod */ -+#define R_PPC_TPREL16 69 /* half16* (sym+add)@tprel */ -+#define R_PPC_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */ -+#define R_PPC_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */ -+#define R_PPC_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */ -+#define R_PPC_TPREL32 73 /* word32 (sym+add)@tprel */ -+#define R_PPC_DTPREL16 74 /* half16* (sym+add)@dtprel */ -+#define R_PPC_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */ -+#define R_PPC_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */ -+#define R_PPC_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */ -+#define R_PPC_DTPREL32 78 /* word32 (sym+add)@dtprel */ -+#define R_PPC_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */ -+#define R_PPC_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */ -+#define R_PPC_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */ -+#define R_PPC_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */ -+#define R_PPC_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */ -+#define R_PPC_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */ -+#define R_PPC_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */ -+#define R_PPC_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */ -+#define R_PPC_GOT_TPREL16 87 /* half16* (sym+add)@got@tprel */ -+#define R_PPC_GOT_TPREL16_LO 88 /* half16 (sym+add)@got@tprel@l */ -+#define R_PPC_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */ -+#define R_PPC_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */ -+#define R_PPC_GOT_DTPREL16 91 /* half16* (sym+add)@got@dtprel */ -+#define R_PPC_GOT_DTPREL16_LO 92 /* half16* (sym+add)@got@dtprel@l */ -+#define R_PPC_GOT_DTPREL16_HI 93 /* half16* (sym+add)@got@dtprel@h */ -+#define R_PPC_GOT_DTPREL16_HA 94 /* half16* (sym+add)@got@dtprel@ha */ -+ -+/* Keep this the last entry. */ -+#define R_PPC_NUM 95 -+ -+/* The remaining relocs are from the Embedded ELF ABI, and are not -+ in the SVR4 ELF ABI. */ -+#define R_PPC_EMB_NADDR32 101 -+#define R_PPC_EMB_NADDR16 102 -+#define R_PPC_EMB_NADDR16_LO 103 -+#define R_PPC_EMB_NADDR16_HI 104 -+#define R_PPC_EMB_NADDR16_HA 105 -+#define R_PPC_EMB_SDAI16 106 -+#define R_PPC_EMB_SDA2I16 107 -+#define R_PPC_EMB_SDA2REL 108 -+#define R_PPC_EMB_SDA21 109 /* 16 bit offset in SDA */ -+#define R_PPC_EMB_MRKREF 110 -+#define R_PPC_EMB_RELSEC16 111 -+#define R_PPC_EMB_RELST_LO 112 -+#define R_PPC_EMB_RELST_HI 113 -+#define R_PPC_EMB_RELST_HA 114 -+#define R_PPC_EMB_BIT_FLD 115 -+#define R_PPC_EMB_RELSDA 116 /* 16 bit relative offset in SDA */ -+ -+/* Diab tool relocations. */ -+#define R_PPC_DIAB_SDA21_LO 180 /* like EMB_SDA21, but lower 16 bit */ -+#define R_PPC_DIAB_SDA21_HI 181 /* like EMB_SDA21, but high 16 bit */ -+#define R_PPC_DIAB_SDA21_HA 182 /* like EMB_SDA21, adjusted high 16 */ -+#define R_PPC_DIAB_RELSDA_LO 183 /* like EMB_RELSDA, but lower 16 bit */ -+#define R_PPC_DIAB_RELSDA_HI 184 /* like EMB_RELSDA, but high 16 bit */ -+#define R_PPC_DIAB_RELSDA_HA 185 /* like EMB_RELSDA, adjusted high 16 */ -+ -+/* This is a phony reloc to handle any old fashioned TOC16 references -+ that may still be in object files. */ -+#define R_PPC_TOC16 255 -+ -+ -+/* PowerPC64 relocations defined by the ABIs */ -+#define R_PPC64_NONE R_PPC_NONE -+#define R_PPC64_ADDR32 R_PPC_ADDR32 /* 32bit absolute address */ -+#define R_PPC64_ADDR24 R_PPC_ADDR24 /* 26bit address, word aligned */ -+#define R_PPC64_ADDR16 R_PPC_ADDR16 /* 16bit absolute address */ -+#define R_PPC64_ADDR16_LO R_PPC_ADDR16_LO /* lower 16bits of address */ -+#define R_PPC64_ADDR16_HI R_PPC_ADDR16_HI /* high 16bits of address. */ -+#define R_PPC64_ADDR16_HA R_PPC_ADDR16_HA /* adjusted high 16bits. */ -+#define R_PPC64_ADDR14 R_PPC_ADDR14 /* 16bit address, word aligned */ -+#define R_PPC64_ADDR14_BRTAKEN R_PPC_ADDR14_BRTAKEN -+#define R_PPC64_ADDR14_BRNTAKEN R_PPC_ADDR14_BRNTAKEN -+#define R_PPC64_REL24 R_PPC_REL24 /* PC-rel. 26 bit, word aligned */ -+#define R_PPC64_REL14 R_PPC_REL14 /* PC relative 16 bit */ -+#define R_PPC64_REL14_BRTAKEN R_PPC_REL14_BRTAKEN -+#define R_PPC64_REL14_BRNTAKEN R_PPC_REL14_BRNTAKEN -+#define R_PPC64_GOT16 R_PPC_GOT16 -+#define R_PPC64_GOT16_LO R_PPC_GOT16_LO -+#define R_PPC64_GOT16_HI R_PPC_GOT16_HI -+#define R_PPC64_GOT16_HA R_PPC_GOT16_HA -+ -+#define R_PPC64_COPY R_PPC_COPY -+#define R_PPC64_GLOB_DAT R_PPC_GLOB_DAT -+#define R_PPC64_JMP_SLOT R_PPC_JMP_SLOT -+#define R_PPC64_RELATIVE R_PPC_RELATIVE -+ -+#define R_PPC64_UADDR32 R_PPC_UADDR32 -+#define R_PPC64_UADDR16 R_PPC_UADDR16 -+#define R_PPC64_REL32 R_PPC_REL32 -+#define R_PPC64_PLT32 R_PPC_PLT32 -+#define R_PPC64_PLTREL32 R_PPC_PLTREL32 -+#define R_PPC64_PLT16_LO R_PPC_PLT16_LO -+#define R_PPC64_PLT16_HI R_PPC_PLT16_HI -+#define R_PPC64_PLT16_HA R_PPC_PLT16_HA -+ -+#define R_PPC64_SECTOFF R_PPC_SECTOFF -+#define R_PPC64_SECTOFF_LO R_PPC_SECTOFF_LO -+#define R_PPC64_SECTOFF_HI R_PPC_SECTOFF_HI -+#define R_PPC64_SECTOFF_HA R_PPC_SECTOFF_HA -+#define R_PPC64_ADDR30 37 /* word30 (S + A - P) >> 2 */ -+#define R_PPC64_ADDR64 38 /* doubleword64 S + A */ -+#define R_PPC64_ADDR16_HIGHER 39 /* half16 #higher(S + A) */ -+#define R_PPC64_ADDR16_HIGHERA 40 /* half16 #highera(S + A) */ -+#define R_PPC64_ADDR16_HIGHEST 41 /* half16 #highest(S + A) */ -+#define R_PPC64_ADDR16_HIGHESTA 42 /* half16 #highesta(S + A) */ -+#define R_PPC64_UADDR64 43 /* doubleword64 S + A */ -+#define R_PPC64_REL64 44 /* doubleword64 S + A - P */ -+#define R_PPC64_PLT64 45 /* doubleword64 L + A */ -+#define R_PPC64_PLTREL64 46 /* doubleword64 L + A - P */ -+#define R_PPC64_TOC16 47 /* half16* S + A - .TOC */ -+#define R_PPC64_TOC16_LO 48 /* half16 #lo(S + A - .TOC.) */ -+#define R_PPC64_TOC16_HI 49 /* half16 #hi(S + A - .TOC.) */ -+#define R_PPC64_TOC16_HA 50 /* half16 #ha(S + A - .TOC.) */ -+#define R_PPC64_TOC 51 /* doubleword64 .TOC */ -+#define R_PPC64_PLTGOT16 52 /* half16* M + A */ -+#define R_PPC64_PLTGOT16_LO 53 /* half16 #lo(M + A) */ -+#define R_PPC64_PLTGOT16_HI 54 /* half16 #hi(M + A) */ -+#define R_PPC64_PLTGOT16_HA 55 /* half16 #ha(M + A) */ -+ -+#define R_PPC64_ADDR16_DS 56 /* half16ds* (S + A) >> 2 */ -+#define R_PPC64_ADDR16_LO_DS 57 /* half16ds #lo(S + A) >> 2 */ -+#define R_PPC64_GOT16_DS 58 /* half16ds* (G + A) >> 2 */ -+#define R_PPC64_GOT16_LO_DS 59 /* half16ds #lo(G + A) >> 2 */ -+#define R_PPC64_PLT16_LO_DS 60 /* half16ds #lo(L + A) >> 2 */ -+#define R_PPC64_SECTOFF_DS 61 /* half16ds* (R + A) >> 2 */ -+#define R_PPC64_SECTOFF_LO_DS 62 /* half16ds #lo(R + A) >> 2 */ -+#define R_PPC64_TOC16_DS 63 /* half16ds* (S + A - .TOC.) >> 2 */ -+#define R_PPC64_TOC16_LO_DS 64 /* half16ds #lo(S + A - .TOC.) >> 2 */ -+#define R_PPC64_PLTGOT16_DS 65 /* half16ds* (M + A) >> 2 */ -+#define R_PPC64_PLTGOT16_LO_DS 66 /* half16ds #lo(M + A) >> 2 */ -+ -+/* PowerPC64 relocations defined for the TLS access ABI. */ -+#define R_PPC64_TLS 67 /* none (sym+add)@tls */ -+#define R_PPC64_DTPMOD64 68 /* doubleword64 (sym+add)@dtpmod */ -+#define R_PPC64_TPREL16 69 /* half16* (sym+add)@tprel */ -+#define R_PPC64_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */ -+#define R_PPC64_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */ -+#define R_PPC64_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */ -+#define R_PPC64_TPREL64 73 /* doubleword64 (sym+add)@tprel */ -+#define R_PPC64_DTPREL16 74 /* half16* (sym+add)@dtprel */ -+#define R_PPC64_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */ -+#define R_PPC64_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */ -+#define R_PPC64_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */ -+#define R_PPC64_DTPREL64 78 /* doubleword64 (sym+add)@dtprel */ -+#define R_PPC64_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */ -+#define R_PPC64_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */ -+#define R_PPC64_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */ -+#define R_PPC64_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */ -+#define R_PPC64_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */ -+#define R_PPC64_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */ -+#define R_PPC64_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */ -+#define R_PPC64_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */ -+#define R_PPC64_GOT_TPREL16_DS 87 /* half16ds* (sym+add)@got@tprel */ -+#define R_PPC64_GOT_TPREL16_LO_DS 88 /* half16ds (sym+add)@got@tprel@l */ -+#define R_PPC64_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */ -+#define R_PPC64_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */ -+#define R_PPC64_GOT_DTPREL16_DS 91 /* half16ds* (sym+add)@got@dtprel */ -+#define R_PPC64_GOT_DTPREL16_LO_DS 92 /* half16ds (sym+add)@got@dtprel@l */ -+#define R_PPC64_GOT_DTPREL16_HI 93 /* half16 (sym+add)@got@dtprel@h */ -+#define R_PPC64_GOT_DTPREL16_HA 94 /* half16 (sym+add)@got@dtprel@ha */ -+#define R_PPC64_TPREL16_DS 95 /* half16ds* (sym+add)@tprel */ -+#define R_PPC64_TPREL16_LO_DS 96 /* half16ds (sym+add)@tprel@l */ -+#define R_PPC64_TPREL16_HIGHER 97 /* half16 (sym+add)@tprel@higher */ -+#define R_PPC64_TPREL16_HIGHERA 98 /* half16 (sym+add)@tprel@highera */ -+#define R_PPC64_TPREL16_HIGHEST 99 /* half16 (sym+add)@tprel@highest */ -+#define R_PPC64_TPREL16_HIGHESTA 100 /* half16 (sym+add)@tprel@highesta */ -+#define R_PPC64_DTPREL16_DS 101 /* half16ds* (sym+add)@dtprel */ -+#define R_PPC64_DTPREL16_LO_DS 102 /* half16ds (sym+add)@dtprel@l */ -+#define R_PPC64_DTPREL16_HIGHER 103 /* half16 (sym+add)@dtprel@higher */ -+#define R_PPC64_DTPREL16_HIGHERA 104 /* half16 (sym+add)@dtprel@highera */ -+#define R_PPC64_DTPREL16_HIGHEST 105 /* half16 (sym+add)@dtprel@highest */ -+#define R_PPC64_DTPREL16_HIGHESTA 106 /* half16 (sym+add)@dtprel@highesta */ -+ -+/* Keep this the last entry. */ -+#define R_PPC64_NUM 107 -+ -+/* PowerPC64 specific values for the Dyn d_tag field. */ -+#define DT_PPC64_GLINK (DT_LOPROC + 0) -+#define DT_PPC64_NUM 1 -+ -+ -+/* ARM specific declarations */ -+ -+/* Processor specific flags for the ELF header e_flags field. */ -+#define EF_ARM_RELEXEC 0x01 -+#define EF_ARM_HASENTRY 0x02 -+#define EF_ARM_INTERWORK 0x04 -+#define EF_ARM_APCS_26 0x08 -+#define EF_ARM_APCS_FLOAT 0x10 -+#define EF_ARM_PIC 0x20 -+#define EF_ARM_ALIGN8 0x40 /* 8-bit structure alignment is in use */ -+#define EF_ARM_NEW_ABI 0x80 -+#define EF_ARM_OLD_ABI 0x100 -+ -+/* Other constants defined in the ARM ELF spec. version B-01. */ -+/* NB. These conflict with values defined above. */ -+#define EF_ARM_SYMSARESORTED 0x04 -+#define EF_ARM_DYNSYMSUSESEGIDX 0x08 -+#define EF_ARM_MAPSYMSFIRST 0x10 -+#define EF_ARM_EABIMASK 0XFF000000 -+ -+#define EF_ARM_EABI_VERSION(flags) ((flags) & EF_ARM_EABIMASK) -+#define EF_ARM_EABI_UNKNOWN 0x00000000 -+#define EF_ARM_EABI_VER1 0x01000000 -+#define EF_ARM_EABI_VER2 0x02000000 -+ -+/* Additional symbol types for Thumb */ -+#define STT_ARM_TFUNC 0xd -+ -+/* ARM-specific values for sh_flags */ -+#define SHF_ARM_ENTRYSECT 0x10000000 /* Section contains an entry point */ -+#define SHF_ARM_COMDEF 0x80000000 /* Section may be multiply defined -+ in the input to a link step */ -+ -+/* ARM-specific program header flags */ -+#define PF_ARM_SB 0x10000000 /* Segment contains the location -+ addressed by the static base */ -+ -+/* ARM relocs. */ -+#define R_ARM_NONE 0 /* No reloc */ -+#define R_ARM_PC24 1 /* PC relative 26 bit branch */ -+#define R_ARM_ABS32 2 /* Direct 32 bit */ -+#define R_ARM_REL32 3 /* PC relative 32 bit */ -+#define R_ARM_PC13 4 -+#define R_ARM_ABS16 5 /* Direct 16 bit */ -+#define R_ARM_ABS12 6 /* Direct 12 bit */ -+#define R_ARM_THM_ABS5 7 -+#define R_ARM_ABS8 8 /* Direct 8 bit */ -+#define R_ARM_SBREL32 9 -+#define R_ARM_THM_PC22 10 -+#define R_ARM_THM_PC8 11 -+#define R_ARM_AMP_VCALL9 12 -+#define R_ARM_SWI24 13 -+#define R_ARM_THM_SWI8 14 -+#define R_ARM_XPC25 15 -+#define R_ARM_THM_XPC22 16 -+#define R_ARM_COPY 20 /* Copy symbol at runtime */ -+#define R_ARM_GLOB_DAT 21 /* Create GOT entry */ -+#define R_ARM_JUMP_SLOT 22 /* Create PLT entry */ -+#define R_ARM_RELATIVE 23 /* Adjust by program base */ -+#define R_ARM_GOTOFF 24 /* 32 bit offset to GOT */ -+#define R_ARM_GOTPC 25 /* 32 bit PC relative offset to GOT */ -+#define R_ARM_GOT32 26 /* 32 bit GOT entry */ -+#define R_ARM_PLT32 27 /* 32 bit PLT address */ -+#define R_ARM_ALU_PCREL_7_0 32 -+#define R_ARM_ALU_PCREL_15_8 33 -+#define R_ARM_ALU_PCREL_23_15 34 -+#define R_ARM_LDR_SBREL_11_0 35 -+#define R_ARM_ALU_SBREL_19_12 36 -+#define R_ARM_ALU_SBREL_27_20 37 -+#define R_ARM_GNU_VTENTRY 100 -+#define R_ARM_GNU_VTINHERIT 101 -+#define R_ARM_THM_PC11 102 /* thumb unconditional branch */ -+#define R_ARM_THM_PC9 103 /* thumb conditional branch */ -+#define R_ARM_RXPC25 249 -+#define R_ARM_RSBREL32 250 -+#define R_ARM_THM_RPC22 251 -+#define R_ARM_RREL32 252 -+#define R_ARM_RABS22 253 -+#define R_ARM_RPC24 254 -+#define R_ARM_RBASE 255 -+/* Keep this the last entry. */ -+#define R_ARM_NUM 256 -+ -+/* IA-64 specific declarations. */ -+ -+/* Processor specific flags for the Ehdr e_flags field. */ -+#define EF_IA_64_MASKOS 0x0000000f /* os-specific flags */ -+#define EF_IA_64_ABI64 0x00000010 /* 64-bit ABI */ -+#define EF_IA_64_ARCH 0xff000000 /* arch. version mask */ -+ -+/* Processor specific values for the Phdr p_type field. */ -+#define PT_IA_64_ARCHEXT (PT_LOPROC + 0) /* arch extension bits */ -+#define PT_IA_64_UNWIND (PT_LOPROC + 1) /* ia64 unwind bits */ -+ -+/* Processor specific flags for the Phdr p_flags field. */ -+#define PF_IA_64_NORECOV 0x80000000 /* spec insns w/o recovery */ -+ -+/* Processor specific values for the Shdr sh_type field. */ -+#define SHT_IA_64_EXT (SHT_LOPROC + 0) /* extension bits */ -+#define SHT_IA_64_UNWIND (SHT_LOPROC + 1) /* unwind bits */ -+ -+/* Processor specific flags for the Shdr sh_flags field. */ -+#define SHF_IA_64_SHORT 0x10000000 /* section near gp */ -+#define SHF_IA_64_NORECOV 0x20000000 /* spec insns w/o recovery */ -+ -+/* Processor specific values for the Dyn d_tag field. */ -+#define DT_IA_64_PLT_RESERVE (DT_LOPROC + 0) -+#define DT_IA_64_NUM 1 -+ -+/* IA-64 relocations. */ -+#define R_IA64_NONE 0x00 /* none */ -+#define R_IA64_IMM14 0x21 /* symbol + addend, add imm14 */ -+#define R_IA64_IMM22 0x22 /* symbol + addend, add imm22 */ -+#define R_IA64_IMM64 0x23 /* symbol + addend, mov imm64 */ -+#define R_IA64_DIR32MSB 0x24 /* symbol + addend, data4 MSB */ -+#define R_IA64_DIR32LSB 0x25 /* symbol + addend, data4 LSB */ -+#define R_IA64_DIR64MSB 0x26 /* symbol + addend, data8 MSB */ -+#define R_IA64_DIR64LSB 0x27 /* symbol + addend, data8 LSB */ -+#define R_IA64_GPREL22 0x2a /* @gprel(sym + add), add imm22 */ -+#define R_IA64_GPREL64I 0x2b /* @gprel(sym + add), mov imm64 */ -+#define R_IA64_GPREL32MSB 0x2c /* @gprel(sym + add), data4 MSB */ -+#define R_IA64_GPREL32LSB 0x2d /* @gprel(sym + add), data4 LSB */ -+#define R_IA64_GPREL64MSB 0x2e /* @gprel(sym + add), data8 MSB */ -+#define R_IA64_GPREL64LSB 0x2f /* @gprel(sym + add), data8 LSB */ -+#define R_IA64_LTOFF22 0x32 /* @ltoff(sym + add), add imm22 */ -+#define R_IA64_LTOFF64I 0x33 /* @ltoff(sym + add), mov imm64 */ -+#define R_IA64_PLTOFF22 0x3a /* @pltoff(sym + add), add imm22 */ -+#define R_IA64_PLTOFF64I 0x3b /* @pltoff(sym + add), mov imm64 */ -+#define R_IA64_PLTOFF64MSB 0x3e /* @pltoff(sym + add), data8 MSB */ -+#define R_IA64_PLTOFF64LSB 0x3f /* @pltoff(sym + add), data8 LSB */ -+#define R_IA64_FPTR64I 0x43 /* @fptr(sym + add), mov imm64 */ -+#define R_IA64_FPTR32MSB 0x44 /* @fptr(sym + add), data4 MSB */ -+#define R_IA64_FPTR32LSB 0x45 /* @fptr(sym + add), data4 LSB */ -+#define R_IA64_FPTR64MSB 0x46 /* @fptr(sym + add), data8 MSB */ -+#define R_IA64_FPTR64LSB 0x47 /* @fptr(sym + add), data8 LSB */ -+#define R_IA64_PCREL60B 0x48 /* @pcrel(sym + add), brl */ -+#define R_IA64_PCREL21B 0x49 /* @pcrel(sym + add), ptb, call */ -+#define R_IA64_PCREL21M 0x4a /* @pcrel(sym + add), chk.s */ -+#define R_IA64_PCREL21F 0x4b /* @pcrel(sym + add), fchkf */ -+#define R_IA64_PCREL32MSB 0x4c /* @pcrel(sym + add), data4 MSB */ -+#define R_IA64_PCREL32LSB 0x4d /* @pcrel(sym + add), data4 LSB */ -+#define R_IA64_PCREL64MSB 0x4e /* @pcrel(sym + add), data8 MSB */ -+#define R_IA64_PCREL64LSB 0x4f /* @pcrel(sym + add), data8 LSB */ -+#define R_IA64_LTOFF_FPTR22 0x52 /* @ltoff(@fptr(s+a)), imm22 */ -+#define R_IA64_LTOFF_FPTR64I 0x53 /* @ltoff(@fptr(s+a)), imm64 */ -+#define R_IA64_LTOFF_FPTR32MSB 0x54 /* @ltoff(@fptr(s+a)), data4 MSB */ -+#define R_IA64_LTOFF_FPTR32LSB 0x55 /* @ltoff(@fptr(s+a)), data4 LSB */ -+#define R_IA64_LTOFF_FPTR64MSB 0x56 /* @ltoff(@fptr(s+a)), data8 MSB */ -+#define R_IA64_LTOFF_FPTR64LSB 0x57 /* @ltoff(@fptr(s+a)), data8 LSB */ -+#define R_IA64_SEGREL32MSB 0x5c /* @segrel(sym + add), data4 MSB */ -+#define R_IA64_SEGREL32LSB 0x5d /* @segrel(sym + add), data4 LSB */ -+#define R_IA64_SEGREL64MSB 0x5e /* @segrel(sym + add), data8 MSB */ -+#define R_IA64_SEGREL64LSB 0x5f /* @segrel(sym + add), data8 LSB */ -+#define R_IA64_SECREL32MSB 0x64 /* @secrel(sym + add), data4 MSB */ -+#define R_IA64_SECREL32LSB 0x65 /* @secrel(sym + add), data4 LSB */ -+#define R_IA64_SECREL64MSB 0x66 /* @secrel(sym + add), data8 MSB */ -+#define R_IA64_SECREL64LSB 0x67 /* @secrel(sym + add), data8 LSB */ -+#define R_IA64_REL32MSB 0x6c /* data 4 + REL */ -+#define R_IA64_REL32LSB 0x6d /* data 4 + REL */ -+#define R_IA64_REL64MSB 0x6e /* data 8 + REL */ -+#define R_IA64_REL64LSB 0x6f /* data 8 + REL */ -+#define R_IA64_LTV32MSB 0x74 /* symbol + addend, data4 MSB */ -+#define R_IA64_LTV32LSB 0x75 /* symbol + addend, data4 LSB */ -+#define R_IA64_LTV64MSB 0x76 /* symbol + addend, data8 MSB */ -+#define R_IA64_LTV64LSB 0x77 /* symbol + addend, data8 LSB */ -+#define R_IA64_PCREL21BI 0x79 /* @pcrel(sym + add), 21bit inst */ -+#define R_IA64_PCREL22 0x7a /* @pcrel(sym + add), 22bit inst */ -+#define R_IA64_PCREL64I 0x7b /* @pcrel(sym + add), 64bit inst */ -+#define R_IA64_IPLTMSB 0x80 /* dynamic reloc, imported PLT, MSB */ -+#define R_IA64_IPLTLSB 0x81 /* dynamic reloc, imported PLT, LSB */ -+#define R_IA64_COPY 0x84 /* copy relocation */ -+#define R_IA64_SUB 0x85 /* Addend and symbol difference */ -+#define R_IA64_LTOFF22X 0x86 /* LTOFF22, relaxable. */ -+#define R_IA64_LDXMOV 0x87 /* Use of LTOFF22X. */ -+#define R_IA64_TPREL14 0x91 /* @tprel(sym + add), imm14 */ -+#define R_IA64_TPREL22 0x92 /* @tprel(sym + add), imm22 */ -+#define R_IA64_TPREL64I 0x93 /* @tprel(sym + add), imm64 */ -+#define R_IA64_TPREL64MSB 0x96 /* @tprel(sym + add), data8 MSB */ -+#define R_IA64_TPREL64LSB 0x97 /* @tprel(sym + add), data8 LSB */ -+#define R_IA64_LTOFF_TPREL22 0x9a /* @ltoff(@tprel(s+a)), imm2 */ -+#define R_IA64_DTPMOD64MSB 0xa6 /* @dtpmod(sym + add), data8 MSB */ -+#define R_IA64_DTPMOD64LSB 0xa7 /* @dtpmod(sym + add), data8 LSB */ -+#define R_IA64_LTOFF_DTPMOD22 0xaa /* @ltoff(@dtpmod(sym + add)), imm22 */ -+#define R_IA64_DTPREL14 0xb1 /* @dtprel(sym + add), imm14 */ -+#define R_IA64_DTPREL22 0xb2 /* @dtprel(sym + add), imm22 */ -+#define R_IA64_DTPREL64I 0xb3 /* @dtprel(sym + add), imm64 */ -+#define R_IA64_DTPREL32MSB 0xb4 /* @dtprel(sym + add), data4 MSB */ -+#define R_IA64_DTPREL32LSB 0xb5 /* @dtprel(sym + add), data4 LSB */ -+#define R_IA64_DTPREL64MSB 0xb6 /* @dtprel(sym + add), data8 MSB */ -+#define R_IA64_DTPREL64LSB 0xb7 /* @dtprel(sym + add), data8 LSB */ -+#define R_IA64_LTOFF_DTPREL22 0xba /* @ltoff(@dtprel(s+a)), imm22 */ -+ -+/* SH specific declarations */ -+ -+/* SH relocs. */ -+#define R_SH_NONE 0 -+#define R_SH_DIR32 1 -+#define R_SH_REL32 2 -+#define R_SH_DIR8WPN 3 -+#define R_SH_IND12W 4 -+#define R_SH_DIR8WPL 5 -+#define R_SH_DIR8WPZ 6 -+#define R_SH_DIR8BP 7 -+#define R_SH_DIR8W 8 -+#define R_SH_DIR8L 9 -+#define R_SH_SWITCH16 25 -+#define R_SH_SWITCH32 26 -+#define R_SH_USES 27 -+#define R_SH_COUNT 28 -+#define R_SH_ALIGN 29 -+#define R_SH_CODE 30 -+#define R_SH_DATA 31 -+#define R_SH_LABEL 32 -+#define R_SH_SWITCH8 33 -+#define R_SH_GNU_VTINHERIT 34 -+#define R_SH_GNU_VTENTRY 35 -+#define R_SH_TLS_GD_32 144 -+#define R_SH_TLS_LD_32 145 -+#define R_SH_TLS_LDO_32 146 -+#define R_SH_TLS_IE_32 147 -+#define R_SH_TLS_LE_32 148 -+#define R_SH_TLS_DTPMOD32 149 -+#define R_SH_TLS_DTPOFF32 150 -+#define R_SH_TLS_TPOFF32 151 -+#define R_SH_GOT32 160 -+#define R_SH_PLT32 161 -+#define R_SH_COPY 162 -+#define R_SH_GLOB_DAT 163 -+#define R_SH_JMP_SLOT 164 -+#define R_SH_RELATIVE 165 -+#define R_SH_GOTOFF 166 -+#define R_SH_GOTPC 167 -+/* Keep this the last entry. */ -+#define R_SH_NUM 256 -+ -+/* Additional s390 relocs */ -+ -+#define R_390_NONE 0 /* No reloc. */ -+#define R_390_8 1 /* Direct 8 bit. */ -+#define R_390_12 2 /* Direct 12 bit. */ -+#define R_390_16 3 /* Direct 16 bit. */ -+#define R_390_32 4 /* Direct 32 bit. */ -+#define R_390_PC32 5 /* PC relative 32 bit. */ -+#define R_390_GOT12 6 /* 12 bit GOT offset. */ -+#define R_390_GOT32 7 /* 32 bit GOT offset. */ -+#define R_390_PLT32 8 /* 32 bit PC relative PLT address. */ -+#define R_390_COPY 9 /* Copy symbol at runtime. */ -+#define R_390_GLOB_DAT 10 /* Create GOT entry. */ -+#define R_390_JMP_SLOT 11 /* Create PLT entry. */ -+#define R_390_RELATIVE 12 /* Adjust by program base. */ -+#define R_390_GOTOFF32 13 /* 32 bit offset to GOT. */ -+#define R_390_GOTPC 14 /* 32 bit PC relative offset to GOT. */ -+#define R_390_GOT16 15 /* 16 bit GOT offset. */ -+#define R_390_PC16 16 /* PC relative 16 bit. */ -+#define R_390_PC16DBL 17 /* PC relative 16 bit shifted by 1. */ -+#define R_390_PLT16DBL 18 /* 16 bit PC rel. PLT shifted by 1. */ -+#define R_390_PC32DBL 19 /* PC relative 32 bit shifted by 1. */ -+#define R_390_PLT32DBL 20 /* 32 bit PC rel. PLT shifted by 1. */ -+#define R_390_GOTPCDBL 21 /* 32 bit PC rel. GOT shifted by 1. */ -+#define R_390_64 22 /* Direct 64 bit. */ -+#define R_390_PC64 23 /* PC relative 64 bit. */ -+#define R_390_GOT64 24 /* 64 bit GOT offset. */ -+#define R_390_PLT64 25 /* 64 bit PC relative PLT address. */ -+#define R_390_GOTENT 26 /* 32 bit PC rel. to GOT entry >> 1. */ -+#define R_390_GOTOFF16 27 /* 16 bit offset to GOT. */ -+#define R_390_GOTOFF64 28 /* 64 bit offset to GOT. */ -+#define R_390_GOTPLT12 29 /* 12 bit offset to jump slot. */ -+#define R_390_GOTPLT16 30 /* 16 bit offset to jump slot. */ -+#define R_390_GOTPLT32 31 /* 32 bit offset to jump slot. */ -+#define R_390_GOTPLT64 32 /* 64 bit offset to jump slot. */ -+#define R_390_GOTPLTENT 33 /* 32 bit rel. offset to jump slot. */ -+#define R_390_PLTOFF16 34 /* 16 bit offset from GOT to PLT. */ -+#define R_390_PLTOFF32 35 /* 32 bit offset from GOT to PLT. */ -+#define R_390_PLTOFF64 36 /* 16 bit offset from GOT to PLT. */ -+#define R_390_TLS_LOAD 37 /* Tag for load insn in TLS code. */ -+#define R_390_TLS_GDCALL 38 /* Tag for function call in general -+ dynamic TLS code. */ -+#define R_390_TLS_LDCALL 39 /* Tag for function call in local -+ dynamic TLS code. */ -+#define R_390_TLS_GD32 40 /* Direct 32 bit for general dynamic -+ thread local data. */ -+#define R_390_TLS_GD64 41 /* Direct 64 bit for general dynamic -+ thread local data. */ -+#define R_390_TLS_GOTIE12 42 /* 12 bit GOT offset for static TLS -+ block offset. */ -+#define R_390_TLS_GOTIE32 43 /* 32 bit GOT offset for static TLS -+ block offset. */ -+#define R_390_TLS_GOTIE64 44 /* 64 bit GOT offset for static TLS -+ block offset. */ -+#define R_390_TLS_LDM32 45 /* Direct 32 bit for local dynamic -+ thread local data in LE code. */ -+#define R_390_TLS_LDM64 46 /* Direct 64 bit for local dynamic -+ thread local data in LE code. */ -+#define R_390_TLS_IE32 47 /* 32 bit address of GOT entry for -+ negated static TLS block offset. */ -+#define R_390_TLS_IE64 48 /* 64 bit address of GOT entry for -+ negated static TLS block offset. */ -+#define R_390_TLS_IEENT 49 /* 32 bit rel. offset to GOT entry for -+ negated static TLS block offset. */ -+#define R_390_TLS_LE32 50 /* 32 bit negated offset relative to -+ static TLS block. */ -+#define R_390_TLS_LE64 51 /* 64 bit negated offset relative to -+ static TLS block. */ -+#define R_390_TLS_LDO32 52 /* 32 bit offset relative to TLS -+ block. */ -+#define R_390_TLS_LDO64 53 /* 64 bit offset relative to TLS -+ block. */ -+#define R_390_TLS_DTPMOD 54 /* ID of module containing symbol. */ -+#define R_390_TLS_DTPOFF 55 /* Offset in TLS block. */ -+#define R_390_TLS_TPOFF 56 /* Negated offset in static TLS -+ block. */ -+ -+/* Keep this the last entry. */ -+#define R_390_NUM 57 -+ -+/* CRIS relocations. */ -+#define R_CRIS_NONE 0 -+#define R_CRIS_8 1 -+#define R_CRIS_16 2 -+#define R_CRIS_32 3 -+#define R_CRIS_8_PCREL 4 -+#define R_CRIS_16_PCREL 5 -+#define R_CRIS_32_PCREL 6 -+#define R_CRIS_GNU_VTINHERIT 7 -+#define R_CRIS_GNU_VTENTRY 8 -+#define R_CRIS_COPY 9 -+#define R_CRIS_GLOB_DAT 10 -+#define R_CRIS_JUMP_SLOT 11 -+#define R_CRIS_RELATIVE 12 -+#define R_CRIS_16_GOT 13 -+#define R_CRIS_32_GOT 14 -+#define R_CRIS_16_GOTPLT 15 -+#define R_CRIS_32_GOTPLT 16 -+#define R_CRIS_32_GOTREL 17 -+#define R_CRIS_32_PLT_GOTREL 18 -+#define R_CRIS_32_PLT_PCREL 19 -+ -+#define R_CRIS_NUM 20 -+ -+/* AMD x86-64 relocations. */ -+#define R_X86_64_NONE 0 /* No reloc */ -+#define R_X86_64_64 1 /* Direct 64 bit */ -+#define R_X86_64_PC32 2 /* PC relative 32 bit signed */ -+#define R_X86_64_GOT32 3 /* 32 bit GOT entry */ -+#define R_X86_64_PLT32 4 /* 32 bit PLT address */ -+#define R_X86_64_COPY 5 /* Copy symbol at runtime */ -+#define R_X86_64_GLOB_DAT 6 /* Create GOT entry */ -+#define R_X86_64_JUMP_SLOT 7 /* Create PLT entry */ -+#define R_X86_64_RELATIVE 8 /* Adjust by program base */ -+#define R_X86_64_GOTPCREL 9 /* 32 bit signed PC relative -+ offset to GOT */ -+#define R_X86_64_32 10 /* Direct 32 bit zero extended */ -+#define R_X86_64_32S 11 /* Direct 32 bit sign extended */ -+#define R_X86_64_16 12 /* Direct 16 bit zero extended */ -+#define R_X86_64_PC16 13 /* 16 bit sign extended pc relative */ -+#define R_X86_64_8 14 /* Direct 8 bit sign extended */ -+#define R_X86_64_PC8 15 /* 8 bit sign extended pc relative */ -+#define R_X86_64_DTPMOD64 16 /* ID of module containing symbol */ -+#define R_X86_64_DTPOFF64 17 /* Offset in module's TLS block */ -+#define R_X86_64_TPOFF64 18 /* Offset in initial TLS block */ -+#define R_X86_64_TLSGD 19 /* 32 bit signed PC relative offset -+ to two GOT entries for GD symbol */ -+#define R_X86_64_TLSLD 20 /* 32 bit signed PC relative offset -+ to two GOT entries for LD symbol */ -+#define R_X86_64_DTPOFF32 21 /* Offset in TLS block */ -+#define R_X86_64_GOTTPOFF 22 /* 32 bit signed PC relative offset -+ to GOT entry for IE symbol */ -+#define R_X86_64_TPOFF32 23 /* Offset in initial TLS block */ -+ -+#define R_X86_64_NUM 24 -+ -+__END_DECLS -+ -+#endif /* elf.h */ - - #include "elfconfig.h" - -@@ -195,3 +2641,4 @@ - void fatal(const char *fmt, ...); - void warn(const char *fmt, ...); - void merror(const char *fmt, ...); -+ -diff -Nur linux-2.6.36.orig/scripts/mod/sumversion.c linux-2.6.36/scripts/mod/sumversion.c ---- linux-2.6.36.orig/scripts/mod/sumversion.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/scripts/mod/sumversion.c 2010-11-28 18:33:24.000000000 +0100 -@@ -1,4 +1,4 @@ --#include -+/* #include */ - #ifdef __sun__ - #include - #else diff --git a/target/linux/patches/2.6.39/cris-etrax.patch b/target/linux/patches/2.6.39/cris-etrax.patch deleted file mode 100644 index a80d9a8b8..000000000 --- a/target/linux/patches/2.6.39/cris-etrax.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff -Nur linux-2.6.39.orig/arch/cris/arch-v32/drivers/i2c.h linux-2.6.39/arch/cris/arch-v32/drivers/i2c.h ---- linux-2.6.39.orig/arch/cris/arch-v32/drivers/i2c.h 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/arch/cris/arch-v32/drivers/i2c.h 2011-08-24 19:15:05.000000000 +0200 -@@ -2,7 +2,7 @@ - #include - - /* High level I2C actions */ --int __init i2c_init(void); -+static int __init i2c_init(void); - int i2c_write(unsigned char theSlave, void *data, size_t nbytes); - int i2c_read(unsigned char theSlave, void *data, size_t nbytes); - int i2c_writereg(unsigned char theSlave, unsigned char theReg, unsigned char theValue); diff --git a/target/linux/patches/2.6.39/cris-thread-macro.patch b/target/linux/patches/2.6.39/cris-thread-macro.patch deleted file mode 100644 index 717b31636..000000000 --- a/target/linux/patches/2.6.39/cris-thread-macro.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff -Nur linux-2.6.39.orig/arch/cris/include/asm/thread_info.h linux-2.6.39/arch/cris/include/asm/thread_info.h ---- linux-2.6.39.orig/arch/cris/include/asm/thread_info.h 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/arch/cris/include/asm/thread_info.h 2011-06-28 13:07:09.712682140 +0200 -@@ -68,7 +68,7 @@ - #define init_thread_info (init_thread_union.thread_info) - - /* thread information allocation */ --#define alloc_thread_info(tsk, node) ((struct thread_info *) __get_free_pages(GFP_KERNEL,1)) -+#define alloc_thread_info_node(tsk, node) ((struct thread_info *) __get_free_pages(GFP_KERNEL,1)) - #define free_thread_info(ti) free_pages((unsigned long) (ti), 1) - - #endif /* !__ASSEMBLY__ */ diff --git a/target/linux/patches/2.6.39/cris.patch b/target/linux/patches/2.6.39/cris.patch deleted file mode 100644 index 2d56de399..000000000 --- a/target/linux/patches/2.6.39/cris.patch +++ /dev/null @@ -1,5739 +0,0 @@ -diff -Nur linux-2.6.39.orig/arch/cris/arch-v10/drivers/axisflashmap.c linux-2.6.39/arch/cris/arch-v10/drivers/axisflashmap.c ---- linux-2.6.39.orig/arch/cris/arch-v10/drivers/axisflashmap.c 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/arch/cris/arch-v10/drivers/axisflashmap.c 2011-08-25 07:43:00.179230147 +0200 -@@ -113,7 +113,7 @@ - - /* If no partition-table was found, we use this default-set. */ - #define MAX_PARTITIONS 7 --#define NUM_DEFAULT_PARTITIONS 3 -+#define NUM_DEFAULT_PARTITIONS 4 - - /* - * Default flash size is 2MB. CONFIG_ETRAX_PTABLE_SECTOR is most likely the -@@ -122,19 +122,24 @@ - */ - static struct mtd_partition axis_default_partitions[NUM_DEFAULT_PARTITIONS] = { - { -- .name = "boot firmware", -- .size = CONFIG_ETRAX_PTABLE_SECTOR, -+ .name = "kernel", -+ .size = 0x00, - .offset = 0 - }, - { -- .name = "kernel", -- .size = 0x200000 - (6 * CONFIG_ETRAX_PTABLE_SECTOR), -- .offset = CONFIG_ETRAX_PTABLE_SECTOR -+ .name = "rootfs", -+ .size = 0x200000 , -+ .offset = 0x200000 -+ }, -+ { -+ .name = "cfgfs", -+ .size = 0x20000 , -+ .offset = CONFIG_ETRAX_MTD_SIZE - 0x20000 - }, - { -- .name = "filesystem", -- .size = 5 * CONFIG_ETRAX_PTABLE_SECTOR, -- .offset = 0x200000 - (5 * CONFIG_ETRAX_PTABLE_SECTOR) -+ .name = "linux", -+ .size = CONFIG_ETRAX_MTD_SIZE - 0x20000, -+ .offset = 0 - } - }; - -@@ -275,6 +280,11 @@ - struct partitiontable_entry *ptable; - int use_default_ptable = 1; /* Until proven otherwise. */ - const char pmsg[] = " /dev/flash%d at 0x%08x, size 0x%08x\n"; -+ unsigned int kernel_part_size = 0; -+ unsigned char *flash_mem = (unsigned char*)(FLASH_CACHED_ADDR); -+ unsigned int flash_scan_count = 0; -+ const char *part_magic = "ACME_PART_MAGIC"; -+ unsigned int magic_len = strlen(part_magic); - - if (!(mymtd = flash_probe())) { - /* There's no reason to use this module if no flash chip can -@@ -286,6 +296,31 @@ - mymtd->name, mymtd->size); - axisflash_mtd = mymtd; - } -+ /* scan flash to findout where out partition starts */ -+ -+ printk(KERN_INFO "Scanning flash for end of kernel magic\n"); -+ for(flash_scan_count = 0; flash_scan_count < 100000; flash_scan_count++){ -+ if(strncmp(&flash_mem[flash_scan_count], part_magic, magic_len - 1) == 0) -+ { -+ kernel_part_size = flash_mem[flash_scan_count + magic_len ]; -+ kernel_part_size <<= 8; -+ kernel_part_size += flash_mem[flash_scan_count + magic_len + 2]; -+ kernel_part_size <<= 8; -+ kernel_part_size += flash_mem[flash_scan_count + magic_len + 1]; -+ kernel_part_size <<= 8; -+ kernel_part_size += flash_mem[flash_scan_count + magic_len + 3]; -+ printk(KERN_INFO "Kernel ends at 0x%.08X\n", kernel_part_size); -+ flash_scan_count = 1100000; -+ } -+ } -+ -+ -+ if(kernel_part_size){ -+ kernel_part_size = (kernel_part_size & 0xffff0000); -+ axis_default_partitions[0].size = kernel_part_size; -+ axis_default_partitions[1].size = mymtd->size - axis_default_partitions[0].size - axis_default_partitions[2].size; -+ axis_default_partitions[1].offset = axis_default_partitions[0].size; -+ } - - if (mymtd) { - mymtd->owner = THIS_MODULE; -@@ -354,21 +389,6 @@ - use_default_ptable = !ptable_ok; - } - -- if (romfs_in_flash) { -- /* Add an overlapping device for the root partition (romfs). */ -- -- axis_partitions[pidx].name = "romfs"; -- axis_partitions[pidx].size = romfs_length; -- axis_partitions[pidx].offset = romfs_start - FLASH_CACHED_ADDR; -- axis_partitions[pidx].mask_flags |= MTD_WRITEABLE; -- -- printk(KERN_INFO -- " Adding readonly flash partition for romfs image:\n"); -- printk(pmsg, pidx, axis_partitions[pidx].offset, -- axis_partitions[pidx].size); -- pidx++; -- } -- - #ifdef CONFIG_ETRAX_AXISFLASHMAP_MTD0WHOLE - if (mymtd) { - main_partition.size = mymtd->size; -@@ -391,36 +411,6 @@ - if (err) - panic("axisflashmap could not add MTD partitions!\n"); - } -- -- if (!romfs_in_flash) { -- /* Create an RAM device for the root partition (romfs). */ -- --#if !defined(CONFIG_MTD_MTDRAM) || (CONFIG_MTDRAM_TOTAL_SIZE != 0) || (CONFIG_MTDRAM_ABS_POS != 0) -- /* No use trying to boot this kernel from RAM. Panic! */ -- printk(KERN_EMERG "axisflashmap: Cannot create an MTD RAM " -- "device due to kernel (mis)configuration!\n"); -- panic("This kernel cannot boot from RAM!\n"); --#else -- struct mtd_info *mtd_ram; -- -- mtd_ram = kmalloc(sizeof(struct mtd_info), GFP_KERNEL); -- if (!mtd_ram) -- panic("axisflashmap couldn't allocate memory for " -- "mtd_info!\n"); -- -- printk(KERN_INFO " Adding RAM partition for romfs image:\n"); -- printk(pmsg, pidx, (unsigned)romfs_start, -- (unsigned)romfs_length); -- -- err = mtdram_init_device(mtd_ram, -- (void *)romfs_start, -- romfs_length, -- "romfs"); -- if (err) -- panic("axisflashmap could not initialize MTD RAM " -- "device!\n"); --#endif -- } - return err; - } - -diff -Nur linux-2.6.39.orig/arch/cris/arch-v10/drivers/ds1302.c linux-2.6.39/arch/cris/arch-v10/drivers/ds1302.c ---- linux-2.6.39.orig/arch/cris/arch-v10/drivers/ds1302.c 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/arch/cris/arch-v10/drivers/ds1302.c 2011-08-25 07:43:00.339229517 +0200 -@@ -22,6 +22,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -501,6 +502,10 @@ - return 0; - } - -+#ifdef CONFIG_SYSFS -+static struct class *rtc_class; -+#endif -+ - static int __init ds1302_register(void) - { - ds1302_init(); -@@ -509,6 +514,12 @@ - ds1302_name, RTC_MAJOR_NR); - return -1; - } -+ #ifdef CONFIG_SYSFS -+ rtc_class = class_create(THIS_MODULE, "rtc"); -+ class_device_create(rtc_class, NULL, MKDEV(RTC_MAJOR_NR, 0), -+ NULL, "rtc"); -+ #endif -+ - return 0; - - } -diff -Nur linux-2.6.39.orig/arch/cris/arch-v10/drivers/gpio.c linux-2.6.39/arch/cris/arch-v10/drivers/gpio.c ---- linux-2.6.39.orig/arch/cris/arch-v10/drivers/gpio.c 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/arch/cris/arch-v10/drivers/gpio.c 2011-08-25 07:43:00.588029746 +0200 -@@ -20,6 +20,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -798,6 +799,10 @@ - - /* main driver initialization routine, called from mem.c */ - -+#ifdef CONFIG_SYSFS -+static struct class *gpio_class; -+#endif -+ - static int __init gpio_init(void) - { - int res; -@@ -811,6 +816,13 @@ - return res; - } - -+#ifdef CONFIG_SYSFS -+ gpio_class = class_create(THIS_MODULE, "gpio"); -+ device_create(gpio_class, NULL, MKDEV(GPIO_MAJOR, 0), NULL, "gpioa"); -+ device_create(gpio_class, NULL, MKDEV(GPIO_MAJOR, 1), NULL, "gpiob"); -+ device_create(gpio_class, NULL, MKDEV(GPIO_MAJOR, 2), NULL, "leds"); -+ device_create(gpio_class, NULL, MKDEV(GPIO_MAJOR, 3), NULL, "gpiog"); -+#endif - /* Clear all leds */ - #if defined (CONFIG_ETRAX_CSP0_LEDS) || defined (CONFIG_ETRAX_PA_LEDS) || defined (CONFIG_ETRAX_PB_LEDS) - CRIS_LED_NETWORK_SET(0); -diff -Nur linux-2.6.39.orig/arch/cris/arch-v10/lib/hw_settings.S linux-2.6.39/arch/cris/arch-v10/lib/hw_settings.S ---- linux-2.6.39.orig/arch/cris/arch-v10/lib/hw_settings.S 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/arch/cris/arch-v10/lib/hw_settings.S 2011-08-25 07:43:00.799228984 +0200 -@@ -58,3 +58,5 @@ - .dword R_PORT_PB_SET - .dword PB_SET_VALUE - .dword 0 ; No more register values -+ .ascii "ACME_PART_MAGIC" -+ .dword 0xdeadc0de -diff -Nur linux-2.6.39.orig/arch/cris/arch-v10/mm/init.c linux-2.6.39/arch/cris/arch-v10/mm/init.c ---- linux-2.6.39.orig/arch/cris/arch-v10/mm/init.c 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/arch/cris/arch-v10/mm/init.c 2011-08-25 07:43:01.069229695 +0200 -@@ -184,6 +184,9 @@ - - free_area_init_node(0, zones_size, PAGE_OFFSET >> PAGE_SHIFT, 0); - } -+void free_initrd_mem(unsigned long start, unsigned long end) -+{ -+} - - /* Initialize remaps of some I/O-ports. It is important that this - * is called before any driver is initialized. -diff -Nur linux-2.6.39.orig/arch/cris/boot/compressed/Makefile linux-2.6.39/arch/cris/boot/compressed/Makefile ---- linux-2.6.39.orig/arch/cris/boot/compressed/Makefile 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/arch/cris/boot/compressed/Makefile 2011-08-25 07:43:01.847994855 +0200 -@@ -18,7 +18,7 @@ - OBJECTS-$(CONFIG_ETRAX_ARCH_V32) = $(obj)/head_v32.o - OBJECTS-$(CONFIG_ETRAX_ARCH_V10) = $(obj)/head_v10.o - OBJECTS= $(OBJECTS-y) $(obj)/misc.o --OBJCOPYFLAGS = -O binary --remove-section=.bss -+#OBJCOPYFLAGS = -O binary --remove-section=.bss - - quiet_cmd_image = BUILD $@ - cmd_image = cat $(obj)/decompress.bin $(obj)/piggy.gz > $@ -diff -Nur linux-2.6.39.orig/arch/cris/boot/Makefile linux-2.6.39/arch/cris/boot/Makefile ---- linux-2.6.39.orig/arch/cris/boot/Makefile 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/arch/cris/boot/Makefile 2011-08-25 07:43:01.989240448 +0200 -@@ -5,7 +5,7 @@ - objcopyflags-$(CONFIG_ETRAX_ARCH_V10) += -R .note -R .comment - objcopyflags-$(CONFIG_ETRAX_ARCH_V32) += --remove-section=.bss --remove-section=.note.gnu.build-id - --OBJCOPYFLAGS = -O binary $(objcopyflags-y) -+#OBJCOPYFLAGS = -O binary $(objcopyflags-y) - - - subdir- := compressed rescue -@@ -17,7 +17,6 @@ - - $(obj)/compressed/vmlinux: $(obj)/Image FORCE - $(Q)$(MAKE) $(build)=$(obj)/compressed $@ -- $(Q)$(MAKE) $(build)=$(obj)/rescue $(obj)/rescue/rescue.bin - - $(obj)/zImage: $(obj)/compressed/vmlinux - @cp $< $@ -diff -Nur linux-2.6.39.orig/arch/cris/Kconfig linux-2.6.39/arch/cris/Kconfig ---- linux-2.6.39.orig/arch/cris/Kconfig 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/arch/cris/Kconfig 2011-08-25 07:43:57.197980003 +0200 -@@ -168,6 +168,12 @@ - help - Size of DRAM (decimal in MB) typically 2, 8 or 16. - -+config ETRAX_MTD_SIZE -+ hex "MTD size (hex)" -+ default "0x00800000" -+ help -+ Size of MTD device typically 4 or 8 MB. -+ - config ETRAX_VMEM_SIZE - int "Video memory size (dec, in MB)" - depends on ETRAX_ARCH_V32 && !ETRAXFS -@@ -273,7 +279,7 @@ - select MTD_CFI_AMDSTD - select MTD_JEDECPROBE if ETRAX_ARCH_V32 - select MTD_CHAR -- select MTD_BLOCK -+ select MTD_BLOCK_RO - select MTD_PARTITIONS - select MTD_COMPLEX_MAPPINGS - help -@@ -660,6 +666,13 @@ - - source "drivers/ide/Kconfig" - -+#mysteriously part of this standard linux driver was removed from cris build! - info@crisos.org -+source "drivers/scsi/Kconfig" -+ -+source "drivers/media/Kconfig" -+ -+source "drivers/misc/Kconfig" -+ - source "drivers/net/Kconfig" - - source "drivers/i2c/Kconfig" -@@ -675,6 +688,8 @@ - - source "fs/Kconfig" - -+source "sound/Kconfig" -+ - source "drivers/usb/Kconfig" - - source "drivers/uwb/Kconfig" -diff -Nur linux-2.6.39.orig/arch/cris/Makefile linux-2.6.39/arch/cris/Makefile ---- linux-2.6.39.orig/arch/cris/Makefile 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/arch/cris/Makefile 2011-08-25 07:43:02.329230084 +0200 -@@ -40,10 +40,10 @@ - - LD = $(CROSS_COMPILE)ld -mcrislinux - --OBJCOPYFLAGS := -O binary -R .note -R .comment -S -+OBJCOPYFLAGS := -O binary -R .bss -R .note -R .note.gnu.build-id -R .comment -S - - KBUILD_AFLAGS += -mlinux -march=$(arch-y) $(inc) --KBUILD_CFLAGS += -mlinux -march=$(arch-y) -pipe $(inc) -+KBUILD_CFLAGS += -mlinux -march=$(arch-y) -pipe -fno-peephole2 $(inc) - KBUILD_CPPFLAGS += $(inc) - - ifdef CONFIG_FRAME_POINTER -diff -Nur linux-2.6.39.orig/arch/cris/mm/init.c linux-2.6.39/arch/cris/mm/init.c ---- linux-2.6.39.orig/arch/cris/mm/init.c 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/arch/cris/mm/init.c 2011-08-25 07:43:02.489240456 +0200 -@@ -16,6 +16,7 @@ - DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); - - unsigned long empty_zero_page; -+EXPORT_SYMBOL(empty_zero_page); - - extern char _stext, _edata, _etext; /* From linkerscript */ - extern char __init_begin, __init_end; -@@ -81,3 +82,10 @@ - printk (KERN_INFO "Freeing unused kernel memory: %luk freed\n", - (unsigned long)((&__init_end - &__init_begin) >> 10)); - } -+ -+#ifdef CONFIG_BLK_DEV_INITRD -+void free_initrd_mem(unsigned long start, unsigned long end) -+{ -+ return 0; -+} -+#endif -diff -Nur linux-2.6.39.orig/drivers/net/cris/eth_v10.c linux-2.6.39/drivers/net/cris/eth_v10.c ---- linux-2.6.39.orig/drivers/net/cris/eth_v10.c 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/drivers/net/cris/eth_v10.c 2011-08-25 07:43:02.627979938 +0200 -@@ -1714,7 +1714,7 @@ - static void - e100_netpoll(struct net_device* netdev) - { -- e100rxtx_interrupt(NETWORK_DMA_TX_IRQ_NBR, netdev, NULL); -+ e100rxtx_interrupt(NETWORK_DMA_TX_IRQ_NBR, netdev); - } - #endif - -diff -Nur linux-2.6.39.orig/drivers/tty/serial/crisv10.c linux-2.6.39/drivers/tty/serial/crisv10.c ---- linux-2.6.39.orig/drivers/tty/serial/crisv10.c 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/drivers/tty/serial/crisv10.c 2011-08-25 07:43:02.637980323 +0200 -@@ -26,6 +26,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -4430,6 +4431,7 @@ - #endif - }; - -+static struct class *rs_class; - static int __init rs_init(void) - { - int i; -@@ -4564,6 +4566,24 @@ - #endif - #endif /* CONFIG_SVINTO_SIM */ - -+ rs_class = class_create(THIS_MODULE, "rs_tty"); -+#ifdef CONFIG_ETRAX_SERIAL_PORT0 -+ device_create(rs_class, NULL, -+ MKDEV(TTY_MAJOR, 64), NULL, "ttyS0"); -+#endif -+#ifdef CONFIG_ETRAX_SERIAL_PORT1 -+ device_create(rs_class, NULL, -+ MKDEV(TTY_MAJOR, 65), NULL, "ttyS1"); -+#endif -+#ifdef CONFIG_ETRAX_SERIAL_PORT2 -+ device_create(rs_class, NULL, -+ MKDEV(TTY_MAJOR, 66), NULL, "ttyS2"); -+#endif -+#ifdef CONFIG_ETRAX_SERIAL_PORT3 -+ device_create(rs_class, NULL, -+ MKDEV(TTY_MAJOR, 67), NULL, "ttyS3"); -+#endif -+ - return 0; - } - -diff -Nur linux-2.6.39.orig/drivers/usb/host/hc-cris-dbg.h linux-2.6.39/drivers/usb/host/hc-cris-dbg.h ---- linux-2.6.39.orig/drivers/usb/host/hc-cris-dbg.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/drivers/usb/host/hc-cris-dbg.h 2011-08-25 07:43:02.837990398 +0200 -@@ -0,0 +1,146 @@ -+ -+/* macros for debug output */ -+ -+#define warn(fmt, args...) \ -+ printk(KERN_INFO "crisv10 warn: ");printk(fmt, ## args) -+ -+#define hcd_dbg(hcd, fmt, args...) \ -+ dev_info(hcd->self.controller, fmt, ## args) -+#define hcd_err(hcd, fmt, args...) \ -+ dev_err(hcd->self.controller, fmt, ## args) -+#define hcd_info(hcd, fmt, args...) \ -+ dev_info(hcd->self.controller, fmt, ## args) -+#define hcd_warn(hcd, fmt, args...) \ -+ dev_warn(hcd->self.controller, fmt, ## args) -+ -+/* -+#define devdrv_dbg(fmt, args...) \ -+ printk(KERN_INFO "usb_devdrv dbg: ");printk(fmt, ## args) -+*/ -+#define devdrv_dbg(fmt, args...) {} -+ -+#define devdrv_err(fmt, args...) \ -+ printk(KERN_ERR "usb_devdrv error: ");printk(fmt, ## args) -+#define devdrv_info(fmt, args...) \ -+ printk(KERN_INFO "usb_devdrv: ");printk(fmt, ## args) -+ -+#define irq_dbg(fmt, args...) \ -+ printk(KERN_INFO "crisv10_irq dbg: ");printk(fmt, ## args) -+#define irq_err(fmt, args...) \ -+ printk(KERN_ERR "crisv10_irq error: ");printk(fmt, ## args) -+#define irq_warn(fmt, args...) \ -+ printk(KERN_INFO "crisv10_irq warn: ");printk(fmt, ## args) -+#define irq_info(fmt, args...) \ -+ printk(KERN_INFO "crisv10_hcd: ");printk(fmt, ## args) -+ -+/* -+#define rh_dbg(fmt, args...) \ -+ printk(KERN_DEBUG "crisv10_rh dbg: ");printk(fmt, ## args) -+*/ -+#define rh_dbg(fmt, args...) {} -+ -+#define rh_err(fmt, args...) \ -+ printk(KERN_ERR "crisv10_rh error: ");printk(fmt, ## args) -+#define rh_warn(fmt, args...) \ -+ printk(KERN_INFO "crisv10_rh warning: ");printk(fmt, ## args) -+#define rh_info(fmt, args...) \ -+ printk(KERN_INFO "crisv10_rh: ");printk(fmt, ## args) -+ -+/* -+#define tc_dbg(fmt, args...) \ -+ printk(KERN_INFO "crisv10_tc dbg: ");printk(fmt, ## args) -+*/ -+#define tc_dbg(fmt, args...) {while(0){}} -+ -+#define tc_err(fmt, args...) \ -+ printk(KERN_ERR "crisv10_tc error: ");printk(fmt, ## args) -+/* -+#define tc_warn(fmt, args...) \ -+ printk(KERN_INFO "crisv10_tc warning: ");printk(fmt, ## args) -+*/ -+#define tc_warn(fmt, args...) {while(0){}} -+ -+#define tc_info(fmt, args...) \ -+ printk(KERN_INFO "crisv10_tc: ");printk(fmt, ## args) -+ -+ -+/* Debug print-outs for various traffic types */ -+ -+#define intr_warn(fmt, args...) \ -+ printk(KERN_INFO "crisv10_intr warning: ");printk(fmt, ## args) -+ -+#define intr_dbg(fmt, args...) \ -+ printk(KERN_DEBUG "crisv10_intr dbg: ");printk(fmt, ## args) -+/* -+#define intr_dbg(fmt, args...) {while(0){}} -+*/ -+ -+ -+#define isoc_err(fmt, args...) \ -+ printk(KERN_ERR "crisv10_isoc error: ");printk(fmt, ## args) -+/* -+#define isoc_warn(fmt, args...) \ -+ printk(KERN_INFO "crisv10_isoc warning: ");printk(fmt, ## args) -+*/ -+#define isoc_warn(fmt, args...) {while(0){}} -+ -+/* -+#define isoc_dbg(fmt, args...) \ -+ printk(KERN_INFO "crisv10_isoc dbg: ");printk(fmt, ## args) -+*/ -+#define isoc_dbg(fmt, args...) {while(0){}} -+ -+/* -+#define timer_warn(fmt, args...) \ -+ printk(KERN_INFO "crisv10_timer warning: ");printk(fmt, ## args) -+*/ -+#define timer_warn(fmt, args...) {while(0){}} -+ -+/* -+#define timer_dbg(fmt, args...) \ -+ printk(KERN_INFO "crisv10_timer dbg: ");printk(fmt, ## args) -+*/ -+#define timer_dbg(fmt, args...) {while(0){}} -+ -+ -+/* Debug printouts for events related to late finishing of URBs */ -+ -+#define late_dbg(fmt, args...) \ -+ printk(KERN_INFO "crisv10_late dbg: ");printk(fmt, ## args) -+/* -+#define late_dbg(fmt, args...) {while(0){}} -+*/ -+ -+#define late_warn(fmt, args...) \ -+ printk(KERN_INFO "crisv10_late warning: ");printk(fmt, ## args) -+/* -+#define errno_dbg(fmt, args...) \ -+ printk(KERN_INFO "crisv10_errno dbg: ");printk(fmt, ## args) -+*/ -+#define errno_dbg(fmt, args...) {while(0){}} -+ -+ -+#define dma_dbg(fmt, args...) \ -+ printk(KERN_INFO "crisv10_dma dbg: ");printk(fmt, ## args) -+#define dma_err(fmt, args...) \ -+ printk(KERN_ERR "crisv10_dma error: ");printk(fmt, ## args) -+#define dma_warn(fmt, args...) \ -+ printk(KERN_INFO "crisv10_dma warning: ");printk(fmt, ## args) -+#define dma_info(fmt, args...) \ -+ printk(KERN_INFO "crisv10_dma: ");printk(fmt, ## args) -+ -+ -+ -+#define str_dir(pipe) \ -+ (usb_pipeout(pipe) ? "out" : "in") -+#define str_type(pipe) \ -+ ({ \ -+ char *s = "?"; \ -+ switch (usb_pipetype(pipe)) { \ -+ case PIPE_ISOCHRONOUS: s = "iso"; break; \ -+ case PIPE_INTERRUPT: s = "intr"; break; \ -+ case PIPE_CONTROL: s = "ctrl"; break; \ -+ case PIPE_BULK: s = "bulk"; break; \ -+ }; \ -+ s; \ -+ }) -diff -Nur linux-2.6.39.orig/drivers/usb/host/hc-crisv10.c linux-2.6.39/drivers/usb/host/hc-crisv10.c ---- linux-2.6.39.orig/drivers/usb/host/hc-crisv10.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/drivers/usb/host/hc-crisv10.c 2011-08-25 07:43:02.897981683 +0200 -@@ -0,0 +1,4801 @@ -+/* -+ * -+ * ETRAX 100LX USB Host Controller Driver -+ * -+ * Copyright (C) 2005, 2006 Axis Communications AB -+ * -+ * Author: Konrad Eriksson -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+ -+#include "hc-crisv10.h" -+#include "hc-cris-dbg.h" -+ -+ -+/***************************************************************************/ -+/***************************************************************************/ -+/* Host Controller settings */ -+/***************************************************************************/ -+/***************************************************************************/ -+ -+#define VERSION "1.00 hinko.4" -+#define COPYRIGHT "(c) 2005, 2006 Axis Communications AB" -+#define DESCRIPTION "ETRAX 100LX USB Host Controller" -+ -+#define ETRAX_USB_HC_IRQ USB_HC_IRQ_NBR -+#define ETRAX_USB_RX_IRQ USB_DMA_RX_IRQ_NBR -+#define ETRAX_USB_TX_IRQ USB_DMA_TX_IRQ_NBR -+ -+/* Number of physical ports in Etrax 100LX */ -+#define USB_ROOT_HUB_PORTS 2 -+ -+const char hc_name[] = "hc-crisv10"; -+const char product_desc[] = DESCRIPTION; -+ -+/* The number of epids is, among other things, used for pre-allocating -+ ctrl, bulk and isoc EP descriptors (one for each epid). -+ Assumed to be > 1 when initiating the DMA lists. */ -+#define NBR_OF_EPIDS 32 -+ -+/* Support interrupt traffic intervals up to 128 ms. */ -+#define MAX_INTR_INTERVAL 128 -+ -+/* If periodic traffic (intr or isoc) is to be used, then one entry in the EP -+ table must be "invalid". By this we mean that we shouldn't care about epid -+ attentions for this epid, or at least handle them differently from epid -+ attentions for "valid" epids. This define determines which one to use -+ (don't change it). */ -+#define INVALID_EPID 31 -+/* A special epid for the bulk dummys. */ -+#define DUMMY_EPID 30 -+ -+/* Module settings */ -+ -+MODULE_DESCRIPTION(DESCRIPTION); -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Konrad Eriksson "); -+ -+ -+/* Module parameters */ -+ -+/* 0 = No ports enabled -+ 1 = Only port 1 enabled (on board ethernet on devboard) -+ 2 = Only port 2 enabled (external connector on devboard) -+ 3 = Both ports enabled -+*/ -+static unsigned int ports = 3; -+module_param(ports, uint, S_IRUGO); -+MODULE_PARM_DESC(ports, "Bitmask indicating USB ports to use"); -+ -+ -+/***************************************************************************/ -+/***************************************************************************/ -+/* Shared global variables for this module */ -+/***************************************************************************/ -+/***************************************************************************/ -+ -+/* EP descriptor lists for non period transfers. Must be 32-bit aligned. */ -+static volatile struct USB_EP_Desc TxBulkEPList[NBR_OF_EPIDS] __attribute__ ((aligned (4))); -+ -+static volatile struct USB_EP_Desc TxCtrlEPList[NBR_OF_EPIDS] __attribute__ ((aligned (4))); -+ -+/* EP descriptor lists for period transfers. Must be 32-bit aligned. */ -+static volatile struct USB_EP_Desc TxIntrEPList[MAX_INTR_INTERVAL] __attribute__ ((aligned (4))); -+static volatile struct USB_SB_Desc TxIntrSB_zout __attribute__ ((aligned (4))); -+ -+static volatile struct USB_EP_Desc TxIsocEPList[NBR_OF_EPIDS] __attribute__ ((aligned (4))); -+static volatile struct USB_SB_Desc TxIsocSB_zout __attribute__ ((aligned (4))); -+ -+//static volatile struct USB_SB_Desc TxIsocSBList[NBR_OF_EPIDS] __attribute__ ((aligned (4))); -+ -+/* After each enabled bulk EP IN we put two disabled EP descriptors with the eol flag set, -+ causing the DMA to stop the DMA channel. The first of these two has the intr flag set, which -+ gives us a dma8_sub0_descr interrupt. When we receive this, we advance the DMA one step in the -+ EP list and then restart the bulk channel, thus forcing a switch between bulk EP descriptors -+ in each frame. */ -+static volatile struct USB_EP_Desc TxBulkDummyEPList[NBR_OF_EPIDS][2] __attribute__ ((aligned (4))); -+ -+/* List of URB pointers, where each points to the active URB for a epid. -+ For Bulk, Ctrl and Intr this means which URB that currently is added to -+ DMA lists (Isoc URBs are all directly added to DMA lists). As soon as -+ URB has completed is the queue examined and the first URB in queue is -+ removed and moved to the activeUrbList while its state change to STARTED and -+ its transfer(s) gets added to DMA list (exception Isoc where URBs enter -+ state STARTED directly and added transfers added to DMA lists). */ -+static struct urb *activeUrbList[NBR_OF_EPIDS]; -+ -+/* Additional software state info for each epid */ -+static struct etrax_epid epid_state[NBR_OF_EPIDS]; -+ -+/* Timer handles for bulk traffic timer used to avoid DMA bug where DMA stops -+ even if there is new data waiting to be processed */ -+static struct timer_list bulk_start_timer = TIMER_INITIALIZER(NULL, 0, 0); -+static struct timer_list bulk_eot_timer = TIMER_INITIALIZER(NULL, 0, 0); -+ -+/* We want the start timer to expire before the eot timer, because the former -+ might start traffic, thus making it unnecessary for the latter to time -+ out. */ -+#define BULK_START_TIMER_INTERVAL (HZ/50) /* 20 ms */ -+#define BULK_EOT_TIMER_INTERVAL (HZ/16) /* 60 ms */ -+ -+/* Delay before a URB completion happen when it's scheduled to be delayed */ -+#define LATER_TIMER_DELAY (HZ/50) /* 20 ms */ -+ -+/* Simplifying macros for checking software state info of a epid */ -+/* ----------------------------------------------------------------------- */ -+#define epid_inuse(epid) epid_state[epid].inuse -+#define epid_out_traffic(epid) epid_state[epid].out_traffic -+#define epid_isoc(epid) (epid_state[epid].type == PIPE_ISOCHRONOUS ? 1 : 0) -+#define epid_intr(epid) (epid_state[epid].type == PIPE_INTERRUPT ? 1 : 0) -+ -+ -+/***************************************************************************/ -+/***************************************************************************/ -+/* DEBUG FUNCTIONS */ -+/***************************************************************************/ -+/***************************************************************************/ -+/* Note that these functions are always available in their "__" variants, -+ for use in error situations. The "__" missing variants are controlled by -+ the USB_DEBUG_DESC/USB_DEBUG_URB macros. */ -+static void __dump_urb(struct urb* purb) -+{ -+ struct crisv10_urb_priv *urb_priv = purb->hcpriv; -+ int urb_num = -1; -+ if(urb_priv) { -+ urb_num = urb_priv->urb_num; -+ } -+ printk("\nURB:0x%x[%d]\n", (unsigned int)purb, urb_num); -+ printk("dev :0x%08lx\n", (unsigned long)purb->dev); -+ printk("pipe :0x%08x\n", purb->pipe); -+ printk("status :%d\n", purb->status); -+ printk("transfer_flags :0x%08x\n", purb->transfer_flags); -+ printk("transfer_buffer :0x%08lx\n", (unsigned long)purb->transfer_buffer); -+ printk("transfer_buffer_length:%d\n", purb->transfer_buffer_length); -+ printk("actual_length :%d\n", purb->actual_length); -+ printk("setup_packet :0x%08lx\n", (unsigned long)purb->setup_packet); -+ printk("start_frame :%d\n", purb->start_frame); -+ printk("number_of_packets :%d\n", purb->number_of_packets); -+ printk("interval :%d\n", purb->interval); -+ printk("error_count :%d\n", purb->error_count); -+ printk("context :0x%08lx\n", (unsigned long)purb->context); -+ printk("complete :0x%08lx\n\n", (unsigned long)purb->complete); -+} -+ -+static void __dump_in_desc(volatile struct USB_IN_Desc *in) -+{ -+ printk("\nUSB_IN_Desc at 0x%08lx\n", (unsigned long)in); -+ printk(" sw_len : 0x%04x (%d)\n", in->sw_len, in->sw_len); -+ printk(" command : 0x%04x\n", in->command); -+ printk(" next : 0x%08lx\n", in->next); -+ printk(" buf : 0x%08lx\n", in->buf); -+ printk(" hw_len : 0x%04x (%d)\n", in->hw_len, in->hw_len); -+ printk(" status : 0x%04x\n\n", in->status); -+} -+ -+static void __dump_sb_desc(volatile struct USB_SB_Desc *sb) -+{ -+ char tt = (sb->command & 0x30) >> 4; -+ char *tt_string; -+ -+ switch (tt) { -+ case 0: -+ tt_string = "zout"; -+ break; -+ case 1: -+ tt_string = "in"; -+ break; -+ case 2: -+ tt_string = "out"; -+ break; -+ case 3: -+ tt_string = "setup"; -+ break; -+ default: -+ tt_string = "unknown (weird)"; -+ } -+ -+ printk(" USB_SB_Desc at 0x%08lx ", (unsigned long)sb); -+ printk(" command:0x%04x (", sb->command); -+ printk("rem:%d ", (sb->command & 0x3f00) >> 8); -+ printk("full:%d ", (sb->command & 0x40) >> 6); -+ printk("tt:%d(%s) ", tt, tt_string); -+ printk("intr:%d ", (sb->command & 0x8) >> 3); -+ printk("eot:%d ", (sb->command & 0x2) >> 1); -+ printk("eol:%d)", sb->command & 0x1); -+ printk(" sw_len:0x%04x(%d)", sb->sw_len, sb->sw_len); -+ printk(" next:0x%08lx", sb->next); -+ printk(" buf:0x%08lx\n", sb->buf); -+} -+ -+ -+static void __dump_ep_desc(volatile struct USB_EP_Desc *ep) -+{ -+ printk("USB_EP_Desc at 0x%08lx ", (unsigned long)ep); -+ printk(" command:0x%04x (", ep->command); -+ printk("ep_id:%d ", (ep->command & 0x1f00) >> 8); -+ printk("enable:%d ", (ep->command & 0x10) >> 4); -+ printk("intr:%d ", (ep->command & 0x8) >> 3); -+ printk("eof:%d ", (ep->command & 0x2) >> 1); -+ printk("eol:%d)", ep->command & 0x1); -+ printk(" hw_len:0x%04x(%d)", ep->hw_len, ep->hw_len); -+ printk(" next:0x%08lx", ep->next); -+ printk(" sub:0x%08lx\n", ep->sub); -+} -+ -+static inline void __dump_ep_list(int pipe_type) -+{ -+ volatile struct USB_EP_Desc *ep; -+ volatile struct USB_EP_Desc *first_ep; -+ volatile struct USB_SB_Desc *sb; -+ -+ switch (pipe_type) -+ { -+ case PIPE_BULK: -+ first_ep = &TxBulkEPList[0]; -+ break; -+ case PIPE_CONTROL: -+ first_ep = &TxCtrlEPList[0]; -+ break; -+ case PIPE_INTERRUPT: -+ first_ep = &TxIntrEPList[0]; -+ break; -+ case PIPE_ISOCHRONOUS: -+ first_ep = &TxIsocEPList[0]; -+ break; -+ default: -+ warn("Cannot dump unknown traffic type"); -+ return; -+ } -+ ep = first_ep; -+ -+ printk("\n\nDumping EP list...\n\n"); -+ -+ do { -+ __dump_ep_desc(ep); -+ /* Cannot phys_to_virt on 0 as it turns into 80000000, which is != 0. */ -+ sb = ep->sub ? phys_to_virt(ep->sub) : 0; -+ while (sb) { -+ __dump_sb_desc(sb); -+ sb = sb->next ? phys_to_virt(sb->next) : 0; -+ } -+ ep = (volatile struct USB_EP_Desc *)(phys_to_virt(ep->next)); -+ -+ } while (ep != first_ep); -+} -+ -+static inline void __dump_ept_data(int epid) -+{ -+ unsigned long flags; -+ __u32 r_usb_ept_data; -+ -+ if (epid < 0 || epid > 31) { -+ printk("Cannot dump ept data for invalid epid %d\n", epid); -+ return; -+ } -+ -+ local_irq_save(flags); -+ *R_USB_EPT_INDEX = IO_FIELD(R_USB_EPT_INDEX, value, epid); -+ nop(); -+ r_usb_ept_data = *R_USB_EPT_DATA; -+ local_irq_restore(flags); -+ -+ printk(" R_USB_EPT_DATA = 0x%x for epid %d :\n", r_usb_ept_data, epid); -+ if (r_usb_ept_data == 0) { -+ /* No need for more detailed printing. */ -+ return; -+ } -+ printk(" valid : %d\n", (r_usb_ept_data & 0x80000000) >> 31); -+ printk(" hold : %d\n", (r_usb_ept_data & 0x40000000) >> 30); -+ printk(" error_count_in : %d\n", (r_usb_ept_data & 0x30000000) >> 28); -+ printk(" t_in : %d\n", (r_usb_ept_data & 0x08000000) >> 27); -+ printk(" low_speed : %d\n", (r_usb_ept_data & 0x04000000) >> 26); -+ printk(" port : %d\n", (r_usb_ept_data & 0x03000000) >> 24); -+ printk(" error_code : %d\n", (r_usb_ept_data & 0x00c00000) >> 22); -+ printk(" t_out : %d\n", (r_usb_ept_data & 0x00200000) >> 21); -+ printk(" error_count_out : %d\n", (r_usb_ept_data & 0x00180000) >> 19); -+ printk(" max_len : %d\n", (r_usb_ept_data & 0x0003f800) >> 11); -+ printk(" ep : %d\n", (r_usb_ept_data & 0x00000780) >> 7); -+ printk(" dev : %d\n", (r_usb_ept_data & 0x0000003f)); -+} -+ -+static inline void __dump_ept_data_iso(int epid) -+{ -+ unsigned long flags; -+ __u32 ept_data; -+ -+ if (epid < 0 || epid > 31) { -+ printk("Cannot dump ept data for invalid epid %d\n", epid); -+ return; -+ } -+ -+ local_irq_save(flags); -+ *R_USB_EPT_INDEX = IO_FIELD(R_USB_EPT_INDEX, value, epid); -+ nop(); -+ ept_data = *R_USB_EPT_DATA_ISO; -+ local_irq_restore(flags); -+ -+ printk(" R_USB_EPT_DATA = 0x%x for epid %d :\n", ept_data, epid); -+ if (ept_data == 0) { -+ /* No need for more detailed printing. */ -+ return; -+ } -+ printk(" valid : %d\n", IO_EXTRACT(R_USB_EPT_DATA_ISO, valid, -+ ept_data)); -+ printk(" port : %d\n", IO_EXTRACT(R_USB_EPT_DATA_ISO, port, -+ ept_data)); -+ printk(" error_code : %d\n", IO_EXTRACT(R_USB_EPT_DATA_ISO, error_code, -+ ept_data)); -+ printk(" max_len : %d\n", IO_EXTRACT(R_USB_EPT_DATA_ISO, max_len, -+ ept_data)); -+ printk(" ep : %d\n", IO_EXTRACT(R_USB_EPT_DATA_ISO, ep, -+ ept_data)); -+ printk(" dev : %d\n", IO_EXTRACT(R_USB_EPT_DATA_ISO, dev, -+ ept_data)); -+} -+ -+static inline void __dump_ept_data_list(void) -+{ -+ int i; -+ -+ printk("Dumping the whole R_USB_EPT_DATA list\n"); -+ -+ for (i = 0; i < 32; i++) { -+ __dump_ept_data(i); -+ } -+} -+ -+static void debug_epid(int epid) { -+ int i; -+ -+ if(epid_isoc(epid)) { -+ __dump_ept_data_iso(epid); -+ } else { -+ __dump_ept_data(epid); -+ } -+ -+ printk("Bulk:\n"); -+ for(i = 0; i < 32; i++) { -+ if(IO_EXTRACT(USB_EP_command, epid, TxBulkEPList[i].command) == -+ epid) { -+ printk("%d: ", i); __dump_ep_desc(&(TxBulkEPList[i])); -+ } -+ } -+ -+ printk("Ctrl:\n"); -+ for(i = 0; i < 32; i++) { -+ if(IO_EXTRACT(USB_EP_command, epid, TxCtrlEPList[i].command) == -+ epid) { -+ printk("%d: ", i); __dump_ep_desc(&(TxCtrlEPList[i])); -+ } -+ } -+ -+ printk("Intr:\n"); -+ for(i = 0; i < MAX_INTR_INTERVAL; i++) { -+ if(IO_EXTRACT(USB_EP_command, epid, TxIntrEPList[i].command) == -+ epid) { -+ printk("%d: ", i); __dump_ep_desc(&(TxIntrEPList[i])); -+ } -+ } -+ -+ printk("Isoc:\n"); -+ for(i = 0; i < 32; i++) { -+ if(IO_EXTRACT(USB_EP_command, epid, TxIsocEPList[i].command) == -+ epid) { -+ printk("%d: ", i); __dump_ep_desc(&(TxIsocEPList[i])); -+ } -+ } -+ -+ __dump_ept_data_list(); -+ __dump_ep_list(PIPE_INTERRUPT); -+ printk("\n\n"); -+} -+ -+ -+ -+char* hcd_status_to_str(__u8 bUsbStatus) { -+ static char hcd_status_str[128]; -+ hcd_status_str[0] = '\0'; -+ if(bUsbStatus & IO_STATE(R_USB_STATUS, ourun, yes)) { -+ strcat(hcd_status_str, "ourun "); -+ } -+ if(bUsbStatus & IO_STATE(R_USB_STATUS, perror, yes)) { -+ strcat(hcd_status_str, "perror "); -+ } -+ if(bUsbStatus & IO_STATE(R_USB_STATUS, device_mode, yes)) { -+ strcat(hcd_status_str, "device_mode "); -+ } -+ if(bUsbStatus & IO_STATE(R_USB_STATUS, host_mode, yes)) { -+ strcat(hcd_status_str, "host_mode "); -+ } -+ if(bUsbStatus & IO_STATE(R_USB_STATUS, started, yes)) { -+ strcat(hcd_status_str, "started "); -+ } -+ if(bUsbStatus & IO_STATE(R_USB_STATUS, running, yes)) { -+ strcat(hcd_status_str, "running "); -+ } -+ return hcd_status_str; -+} -+ -+ -+char* sblist_to_str(struct USB_SB_Desc* sb_desc) { -+ static char sblist_to_str_buff[128]; -+ char tmp[32], tmp2[32]; -+ sblist_to_str_buff[0] = '\0'; -+ while(sb_desc != NULL) { -+ switch(IO_EXTRACT(USB_SB_command, tt, sb_desc->command)) { -+ case 0: sprintf(tmp, "zout"); break; -+ case 1: sprintf(tmp, "in"); break; -+ case 2: sprintf(tmp, "out"); break; -+ case 3: sprintf(tmp, "setup"); break; -+ } -+ sprintf(tmp2, "(%s %d)", tmp, sb_desc->sw_len); -+ strcat(sblist_to_str_buff, tmp2); -+ if(sb_desc->next != 0) { -+ sb_desc = phys_to_virt(sb_desc->next); -+ } else { -+ sb_desc = NULL; -+ } -+ } -+ return sblist_to_str_buff; -+} -+ -+char* port_status_to_str(__u16 wPortStatus) { -+ static char port_status_str[128]; -+ port_status_str[0] = '\0'; -+ if(wPortStatus & IO_STATE(R_USB_RH_PORT_STATUS_1, connected, yes)) { -+ strcat(port_status_str, "connected "); -+ } -+ if(wPortStatus & IO_STATE(R_USB_RH_PORT_STATUS_1, enabled, yes)) { -+ strcat(port_status_str, "enabled "); -+ } -+ if(wPortStatus & IO_STATE(R_USB_RH_PORT_STATUS_1, suspended, yes)) { -+ strcat(port_status_str, "suspended "); -+ } -+ if(wPortStatus & IO_STATE(R_USB_RH_PORT_STATUS_1, reset, yes)) { -+ strcat(port_status_str, "reset "); -+ } -+ if(wPortStatus & IO_STATE(R_USB_RH_PORT_STATUS_1, speed, full)) { -+ strcat(port_status_str, "full-speed "); -+ } else { -+ strcat(port_status_str, "low-speed "); -+ } -+ return port_status_str; -+} -+ -+ -+char* endpoint_to_str(struct usb_endpoint_descriptor *ed) { -+ static char endpoint_to_str_buff[128]; -+ char tmp[32]; -+ int epnum = ed->bEndpointAddress & 0x0F; -+ int dir = ed->bEndpointAddress & 0x80; -+ int type = ed->bmAttributes & 0x03; -+ endpoint_to_str_buff[0] = '\0'; -+ sprintf(endpoint_to_str_buff, "ep:%d ", epnum); -+ switch(type) { -+ case 0: -+ sprintf(tmp, " ctrl"); -+ break; -+ case 1: -+ sprintf(tmp, " isoc"); -+ break; -+ case 2: -+ sprintf(tmp, " bulk"); -+ break; -+ case 3: -+ sprintf(tmp, " intr"); -+ break; -+ } -+ strcat(endpoint_to_str_buff, tmp); -+ if(dir) { -+ sprintf(tmp, " in"); -+ } else { -+ sprintf(tmp, " out"); -+ } -+ strcat(endpoint_to_str_buff, tmp); -+ -+ return endpoint_to_str_buff; -+} -+ -+/* Debug helper functions for Transfer Controller */ -+char* pipe_to_str(unsigned int pipe) { -+ static char pipe_to_str_buff[128]; -+ char tmp[64]; -+ sprintf(pipe_to_str_buff, "dir:%s", str_dir(pipe)); -+ sprintf(tmp, " type:%s", str_type(pipe)); -+ strcat(pipe_to_str_buff, tmp); -+ -+ sprintf(tmp, " dev:%d", usb_pipedevice(pipe)); -+ strcat(pipe_to_str_buff, tmp); -+ sprintf(tmp, " ep:%d", usb_pipeendpoint(pipe)); -+ strcat(pipe_to_str_buff, tmp); -+ return pipe_to_str_buff; -+} -+ -+ -+#define USB_DEBUG_DESC 1 -+ -+#ifdef USB_DEBUG_DESC -+#define dump_in_desc(x) __dump_in_desc(x) -+#define dump_sb_desc(...) __dump_sb_desc(...) -+#define dump_ep_desc(x) __dump_ep_desc(x) -+#define dump_ept_data(x) __dump_ept_data(x) -+#else -+#define dump_in_desc(...) do {} while (0) -+#define dump_sb_desc(...) do {} while (0) -+#define dump_ep_desc(...) do {} while (0) -+#endif -+ -+ -+/* Uncomment this to enable massive function call trace -+ #define USB_DEBUG_TRACE */ -+//#define USB_DEBUG_TRACE 1 -+ -+#ifdef USB_DEBUG_TRACE -+#define DBFENTER (printk(": Entering: %s\n", __FUNCTION__)) -+#define DBFEXIT (printk(": Exiting: %s\n", __FUNCTION__)) -+#else -+#define DBFENTER do {} while (0) -+#define DBFEXIT do {} while (0) -+#endif -+ -+#define CHECK_ALIGN(x) if (((__u32)(x)) & 0x00000003) \ -+{panic("Alignment check (DWORD) failed at %s:%s:%d\n", __FILE__, __FUNCTION__, __LINE__);} -+ -+/* Most helpful debugging aid */ -+#define ASSERT(expr) ((void) ((expr) ? 0 : (err("assert failed at: %s %d",__FUNCTION__, __LINE__)))) -+ -+ -+/***************************************************************************/ -+/***************************************************************************/ -+/* Forward declarations */ -+/***************************************************************************/ -+/***************************************************************************/ -+void crisv10_hcd_epid_attn_irq(struct crisv10_irq_reg *reg); -+void crisv10_hcd_port_status_irq(struct crisv10_irq_reg *reg); -+void crisv10_hcd_ctl_status_irq(struct crisv10_irq_reg *reg); -+void crisv10_hcd_isoc_eof_irq(struct crisv10_irq_reg *reg); -+ -+void rh_port_status_change(__u16[]); -+int rh_clear_port_feature(__u8, __u16); -+int rh_set_port_feature(__u8, __u16); -+static void rh_disable_port(unsigned int port); -+ -+static void check_finished_bulk_tx_epids(struct usb_hcd *hcd, -+ int timer); -+ -+//static int tc_setup_epid(struct usb_host_endpoint *ep, struct urb *urb, -+// int mem_flags); -+static int tc_setup_epid(struct urb *urb, int mem_flags); -+static void tc_free_epid(struct usb_host_endpoint *ep); -+static int tc_allocate_epid(void); -+static void tc_finish_urb(struct usb_hcd *hcd, struct urb *urb, int status); -+static void tc_finish_urb_later(struct usb_hcd *hcd, struct urb *urb, -+ int status); -+ -+static int urb_priv_create(struct usb_hcd *hcd, struct urb *urb, int epid, -+ int mem_flags); -+static void urb_priv_free(struct usb_hcd *hcd, struct urb *urb); -+ -+static inline struct urb *urb_list_first(int epid); -+static inline void urb_list_add(struct urb *urb, int epid, -+ int mem_flags); -+static inline urb_entry_t *urb_list_entry(struct urb *urb, int epid); -+static inline void urb_list_del(struct urb *urb, int epid); -+static inline void urb_list_move_last(struct urb *urb, int epid); -+static inline struct urb *urb_list_next(struct urb *urb, int epid); -+ -+int create_sb_for_urb(struct urb *urb, int mem_flags); -+int init_intr_urb(struct urb *urb, int mem_flags); -+ -+static inline void etrax_epid_set(__u8 index, __u32 data); -+static inline void etrax_epid_clear_error(__u8 index); -+static inline void etrax_epid_set_toggle(__u8 index, __u8 dirout, -+ __u8 toggle); -+static inline __u8 etrax_epid_get_toggle(__u8 index, __u8 dirout); -+static inline __u32 etrax_epid_get(__u8 index); -+ -+/* We're accessing the same register position in Etrax so -+ when we do full access the internal difference doesn't matter */ -+#define etrax_epid_iso_set(index, data) etrax_epid_set(index, data) -+#define etrax_epid_iso_get(index) etrax_epid_get(index) -+ -+ -+//static void tc_dma_process_isoc_urb(struct urb *urb); -+static void tc_dma_process_queue(int epid); -+static void tc_dma_unlink_intr_urb(struct urb *urb); -+static irqreturn_t tc_dma_tx_interrupt(int irq, void *vhc); -+static irqreturn_t tc_dma_rx_interrupt(int irq, void *vhc); -+ -+static void tc_bulk_start_timer_func(unsigned long dummy); -+static void tc_bulk_eot_timer_func(unsigned long dummy); -+ -+ -+/*************************************************************/ -+/*************************************************************/ -+/* Host Controler Driver block */ -+/*************************************************************/ -+/*************************************************************/ -+ -+/* HCD operations */ -+static irqreturn_t crisv10_hcd_top_irq(int irq, void*); -+static int crisv10_hcd_reset(struct usb_hcd *); -+static int crisv10_hcd_start(struct usb_hcd *); -+static void crisv10_hcd_stop(struct usb_hcd *); -+#ifdef CONFIG_PM -+static int crisv10_hcd_suspend(struct device *, u32, u32); -+static int crisv10_hcd_resume(struct device *, u32); -+#endif /* CONFIG_PM */ -+static int crisv10_hcd_get_frame(struct usb_hcd *); -+ -+//static int tc_urb_enqueue(struct usb_hcd *, struct usb_host_endpoint *ep, struct urb *, gfp_t mem_flags); -+static int tc_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags); -+//static int tc_urb_dequeue(struct usb_hcd *, struct urb *); -+static int tc_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status); -+static void tc_endpoint_disable(struct usb_hcd *, struct usb_host_endpoint *ep); -+ -+static int rh_status_data_request(struct usb_hcd *, char *); -+static int rh_control_request(struct usb_hcd *, u16, u16, u16, char*, u16); -+ -+#ifdef CONFIG_PM -+static int crisv10_hcd_hub_suspend(struct usb_hcd *); -+static int crisv10_hcd_hub_resume(struct usb_hcd *); -+#endif /* CONFIG_PM */ -+#ifdef CONFIG_USB_OTG -+static int crisv10_hcd_start_port_reset(struct usb_hcd *, unsigned); -+#endif /* CONFIG_USB_OTG */ -+ -+/* host controller driver interface */ -+static const struct hc_driver crisv10_hc_driver = -+ { -+ .description = hc_name, -+ .product_desc = product_desc, -+ .hcd_priv_size = sizeof(struct crisv10_hcd), -+ -+ /* Attaching IRQ handler manualy in probe() */ -+ /* .irq = crisv10_hcd_irq, */ -+ -+ .flags = HCD_USB11, -+ -+ /* called to init HCD and root hub */ -+ .reset = crisv10_hcd_reset, -+ .start = crisv10_hcd_start, -+ -+ /* cleanly make HCD stop writing memory and doing I/O */ -+ .stop = crisv10_hcd_stop, -+ -+ /* return current frame number */ -+ .get_frame_number = crisv10_hcd_get_frame, -+ -+ -+ /* Manage i/o requests via the Transfer Controller */ -+ .urb_enqueue = tc_urb_enqueue, -+ .urb_dequeue = tc_urb_dequeue, -+ -+ /* hw synch, freeing endpoint resources that urb_dequeue can't */ -+ .endpoint_disable = tc_endpoint_disable, -+ -+ -+ /* Root Hub support */ -+ .hub_status_data = rh_status_data_request, -+ .hub_control = rh_control_request, -+#ifdef CONFIG_PM -+ .hub_suspend = rh_suspend_request, -+ .hub_resume = rh_resume_request, -+#endif /* CONFIG_PM */ -+#ifdef CONFIG_USB_OTG -+ .start_port_reset = crisv10_hcd_start_port_reset, -+#endif /* CONFIG_USB_OTG */ -+ }; -+ -+ -+/* -+ * conversion between pointers to a hcd and the corresponding -+ * crisv10_hcd -+ */ -+ -+static inline struct crisv10_hcd *hcd_to_crisv10_hcd(struct usb_hcd *hcd) -+{ -+ return (struct crisv10_hcd *) hcd->hcd_priv; -+} -+ -+static inline struct usb_hcd *crisv10_hcd_to_hcd(struct crisv10_hcd *hcd) -+{ -+ return container_of((void *) hcd, struct usb_hcd, hcd_priv); -+} -+ -+/* check if specified port is in use */ -+static inline int port_in_use(unsigned int port) -+{ -+ return ports & (1 << port); -+} -+ -+/* number of ports in use */ -+static inline unsigned int num_ports(void) -+{ -+ unsigned int i, num = 0; -+ for (i = 0; i < USB_ROOT_HUB_PORTS; i++) -+ if (port_in_use(i)) -+ num++; -+ return num; -+} -+ -+/* map hub port number to the port number used internally by the HC */ -+static inline unsigned int map_port(unsigned int port) -+{ -+ unsigned int i, num = 0; -+ for (i = 0; i < USB_ROOT_HUB_PORTS; i++) -+ if (port_in_use(i)) -+ if (++num == port) -+ return i; -+ return -1; -+} -+ -+/* size of descriptors in slab cache */ -+#ifndef MAX -+#define MAX(x, y) ((x) > (y) ? (x) : (y)) -+#endif -+ -+ -+/******************************************************************/ -+/* Hardware Interrupt functions */ -+/******************************************************************/ -+ -+/* Fast interrupt handler for HC */ -+static irqreturn_t crisv10_hcd_top_irq(int irq, void *vcd) -+{ -+ struct usb_hcd *hcd = vcd; -+ struct crisv10_irq_reg reg; -+ __u32 irq_mask; -+ unsigned long flags; -+ -+ DBFENTER; -+ -+ ASSERT(hcd != NULL); -+ reg.hcd = hcd; -+ -+ /* Turn of other interrupts while handling these sensitive cases */ -+ local_irq_save(flags); -+ -+ /* Read out which interrupts that are flaged */ -+ irq_mask = *R_USB_IRQ_MASK_READ; -+ reg.r_usb_irq_mask_read = irq_mask; -+ -+ /* Reading R_USB_STATUS clears the ctl_status interrupt. Note that -+ R_USB_STATUS must be read before R_USB_EPID_ATTN since reading the latter -+ clears the ourun and perror fields of R_USB_STATUS. */ -+ reg.r_usb_status = *R_USB_STATUS; -+ -+ /* Reading R_USB_EPID_ATTN clears the iso_eof, bulk_eot and epid_attn -+ interrupts. */ -+ reg.r_usb_epid_attn = *R_USB_EPID_ATTN; -+ -+ /* Reading R_USB_RH_PORT_STATUS_1 and R_USB_RH_PORT_STATUS_2 clears the -+ port_status interrupt. */ -+ reg.r_usb_rh_port_status_1 = *R_USB_RH_PORT_STATUS_1; -+ reg.r_usb_rh_port_status_2 = *R_USB_RH_PORT_STATUS_2; -+ -+ /* Reading R_USB_FM_NUMBER clears the sof interrupt. */ -+ /* Note: the lower 11 bits contain the actual frame number, sent with each -+ sof. */ -+ reg.r_usb_fm_number = *R_USB_FM_NUMBER; -+ -+ /* Interrupts are handled in order of priority. */ -+ if (irq_mask & IO_MASK(R_USB_IRQ_MASK_READ, port_status)) { -+ crisv10_hcd_port_status_irq(®); -+ } -+ if (irq_mask & IO_MASK(R_USB_IRQ_MASK_READ, epid_attn)) { -+ crisv10_hcd_epid_attn_irq(®); -+ } -+ if (irq_mask & IO_MASK(R_USB_IRQ_MASK_READ, ctl_status)) { -+ crisv10_hcd_ctl_status_irq(®); -+ } -+ if (irq_mask & IO_MASK(R_USB_IRQ_MASK_READ, iso_eof)) { -+ crisv10_hcd_isoc_eof_irq(®); -+ } -+ if (irq_mask & IO_MASK(R_USB_IRQ_MASK_READ, bulk_eot)) { -+ /* Update/restart the bulk start timer since obviously the channel is -+ running. */ -+ mod_timer(&bulk_start_timer, jiffies + BULK_START_TIMER_INTERVAL); -+ /* Update/restart the bulk eot timer since we just received an bulk eot -+ interrupt. */ -+ mod_timer(&bulk_eot_timer, jiffies + BULK_EOT_TIMER_INTERVAL); -+ -+ /* Check for finished bulk transfers on epids */ -+ check_finished_bulk_tx_epids(hcd, 0); -+ } -+ local_irq_restore(flags); -+ -+ DBFEXIT; -+ return IRQ_HANDLED; -+} -+ -+ -+void crisv10_hcd_epid_attn_irq(struct crisv10_irq_reg *reg) { -+ struct usb_hcd *hcd = reg->hcd; -+ struct crisv10_urb_priv *urb_priv; -+ int epid; -+ DBFENTER; -+ -+ for (epid = 0; epid < NBR_OF_EPIDS; epid++) { -+ if (test_bit(epid, (void *)®->r_usb_epid_attn)) { -+ struct urb *urb; -+ __u32 ept_data; -+ int error_code; -+ -+ if (epid == DUMMY_EPID || epid == INVALID_EPID) { -+ /* We definitely don't care about these ones. Besides, they are -+ always disabled, so any possible disabling caused by the -+ epid attention interrupt is irrelevant. */ -+ warn("Got epid_attn for INVALID_EPID or DUMMY_EPID (%d).", epid); -+ continue; -+ } -+ -+ if(!epid_inuse(epid)) { -+ irq_err("Epid attention on epid:%d that isn't in use\n", epid); -+ printk("R_USB_STATUS: 0x%x\n", reg->r_usb_status); -+ debug_epid(epid); -+ continue; -+ } -+ -+ /* Note that although there are separate R_USB_EPT_DATA and -+ R_USB_EPT_DATA_ISO registers, they are located at the same address and -+ are of the same size. In other words, this read should be ok for isoc -+ also. */ -+ ept_data = etrax_epid_get(epid); -+ error_code = IO_EXTRACT(R_USB_EPT_DATA, error_code, ept_data); -+ -+ /* Get the active URB for this epid. We blatantly assume -+ that only this URB could have caused the epid attention. */ -+ urb = activeUrbList[epid]; -+ if (urb == NULL) { -+ irq_err("Attention on epid:%d error:%d with no active URB.\n", -+ epid, error_code); -+ printk("R_USB_STATUS: 0x%x\n", reg->r_usb_status); -+ debug_epid(epid); -+ continue; -+ } -+ -+ urb_priv = (struct crisv10_urb_priv *)urb->hcpriv; -+ ASSERT(urb_priv); -+ -+ /* Using IO_STATE_VALUE on R_USB_EPT_DATA should be ok for isoc also. */ -+ if (error_code == IO_STATE_VALUE(R_USB_EPT_DATA, error_code, no_error)) { -+ -+ /* Isoc traffic doesn't have error_count_in/error_count_out. */ -+ if ((usb_pipetype(urb->pipe) != PIPE_ISOCHRONOUS) && -+ (IO_EXTRACT(R_USB_EPT_DATA, error_count_in, ept_data) == 3 || -+ IO_EXTRACT(R_USB_EPT_DATA, error_count_out, ept_data) == 3)) { -+ /* Check if URB allready is marked for late-finish, we can get -+ several 3rd error for Intr traffic when a device is unplugged */ -+ if(urb_priv->later_data == NULL) { -+ /* 3rd error. */ -+ irq_warn("3rd error for epid:%d (%s %s) URB:0x%x[%d]\n", epid, -+ str_dir(urb->pipe), str_type(urb->pipe), -+ (unsigned int)urb, urb_priv->urb_num); -+ -+ tc_finish_urb_later(hcd, urb, -EPROTO); -+ } -+ -+ } else if (reg->r_usb_status & IO_MASK(R_USB_STATUS, perror)) { -+ irq_warn("Perror for epid:%d\n", epid); -+ printk("FM_NUMBER: %d\n", reg->r_usb_fm_number & 0x7ff); -+ printk("R_USB_STATUS: 0x%x\n", reg->r_usb_status); -+ __dump_urb(urb); -+ debug_epid(epid); -+ -+ if (!(ept_data & IO_MASK(R_USB_EPT_DATA, valid))) { -+ /* invalid ep_id */ -+ panic("Perror because of invalid epid." -+ " Deconfigured too early?"); -+ } else { -+ /* past eof1, near eof, zout transfer, setup transfer */ -+ /* Dump the urb and the relevant EP descriptor. */ -+ panic("Something wrong with DMA descriptor contents." -+ " Too much traffic inserted?"); -+ } -+ } else if (reg->r_usb_status & IO_MASK(R_USB_STATUS, ourun)) { -+ /* buffer ourun */ -+ printk("FM_NUMBER: %d\n", reg->r_usb_fm_number & 0x7ff); -+ printk("R_USB_STATUS: 0x%x\n", reg->r_usb_status); -+ __dump_urb(urb); -+ debug_epid(epid); -+ -+ panic("Buffer overrun/underrun for epid:%d. DMA too busy?", epid); -+ } else { -+ irq_warn("Attention on epid:%d (%s %s) with no error code\n", epid, -+ str_dir(urb->pipe), str_type(urb->pipe)); -+ printk("R_USB_STATUS: 0x%x\n", reg->r_usb_status); -+ __dump_urb(urb); -+ debug_epid(epid); -+ } -+ -+ } else if (error_code == IO_STATE_VALUE(R_USB_EPT_DATA, error_code, -+ stall)) { -+ /* Not really a protocol error, just says that the endpoint gave -+ a stall response. Note that error_code cannot be stall for isoc. */ -+ if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { -+ panic("Isoc traffic cannot stall"); -+ } -+ -+ tc_dbg("Stall for epid:%d (%s %s) URB:0x%x\n", epid, -+ str_dir(urb->pipe), str_type(urb->pipe), (unsigned int)urb); -+ tc_finish_urb(hcd, urb, -EPIPE); -+ -+ } else if (error_code == IO_STATE_VALUE(R_USB_EPT_DATA, error_code, -+ bus_error)) { -+ /* Two devices responded to a transaction request. Must be resolved -+ by software. FIXME: Reset ports? */ -+ panic("Bus error for epid %d." -+ " Two devices responded to transaction request\n", -+ epid); -+ -+ } else if (error_code == IO_STATE_VALUE(R_USB_EPT_DATA, error_code, -+ buffer_error)) { -+ /* DMA overrun or underrun. */ -+ irq_warn("Buffer overrun/underrun for epid:%d (%s %s)\n", epid, -+ str_dir(urb->pipe), str_type(urb->pipe)); -+ -+ /* It seems that error_code = buffer_error in -+ R_USB_EPT_DATA/R_USB_EPT_DATA_ISO and ourun = yes in R_USB_STATUS -+ are the same error. */ -+ tc_finish_urb(hcd, urb, -EPROTO); -+ } else { -+ irq_warn("Unknown attention on epid:%d (%s %s)\n", epid, -+ str_dir(urb->pipe), str_type(urb->pipe)); -+ dump_ept_data(epid); -+ } -+ } -+ } -+ DBFEXIT; -+} -+ -+void crisv10_hcd_port_status_irq(struct crisv10_irq_reg *reg) -+{ -+ __u16 port_reg[USB_ROOT_HUB_PORTS]; -+ DBFENTER; -+ port_reg[0] = reg->r_usb_rh_port_status_1; -+ port_reg[1] = reg->r_usb_rh_port_status_2; -+ rh_port_status_change(port_reg); -+ DBFEXIT; -+} -+ -+void crisv10_hcd_isoc_eof_irq(struct crisv10_irq_reg *reg) -+{ -+ int epid; -+ struct urb *urb; -+ struct crisv10_urb_priv *urb_priv; -+ -+ DBFENTER; -+ -+ for (epid = 0; epid < NBR_OF_EPIDS - 1; epid++) { -+ -+ /* Only check epids that are in use, is valid and has SB list */ -+ if (!epid_inuse(epid) || epid == INVALID_EPID || -+ TxIsocEPList[epid].sub == 0 || epid == DUMMY_EPID) { -+ /* Nothing here to see. */ -+ continue; -+ } -+ ASSERT(epid_isoc(epid)); -+ -+ /* Get the active URB for this epid (if any). */ -+ urb = activeUrbList[epid]; -+ if (urb == 0) { -+ isoc_warn("Ignoring NULL urb for epid:%d\n", epid); -+ continue; -+ } -+ if(!epid_out_traffic(epid)) { -+ /* Sanity check. */ -+ ASSERT(usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS); -+ -+ urb_priv = (struct crisv10_urb_priv *)urb->hcpriv; -+ ASSERT(urb_priv); -+ -+ if (urb_priv->urb_state == NOT_STARTED) { -+ /* If ASAP is not set and urb->start_frame is the current frame, -+ start the transfer. */ -+ if (!(urb->transfer_flags & URB_ISO_ASAP) && -+ (urb->start_frame == (*R_USB_FM_NUMBER & 0x7ff))) { -+ /* EP should not be enabled if we're waiting for start_frame */ -+ ASSERT((TxIsocEPList[epid].command & -+ IO_STATE(USB_EP_command, enable, yes)) == 0); -+ -+ isoc_warn("Enabling isoc IN EP descr for epid %d\n", epid); -+ TxIsocEPList[epid].command |= IO_STATE(USB_EP_command, enable, yes); -+ -+ /* This urb is now active. */ -+ urb_priv->urb_state = STARTED; -+ continue; -+ } -+ } -+ } -+ } -+ -+ DBFEXIT; -+} -+ -+void crisv10_hcd_ctl_status_irq(struct crisv10_irq_reg *reg) -+{ -+ struct crisv10_hcd* crisv10_hcd = hcd_to_crisv10_hcd(reg->hcd); -+ -+ DBFENTER; -+ ASSERT(crisv10_hcd); -+ -+ irq_dbg("ctr_status_irq, controller status: %s\n", -+ hcd_status_to_str(reg->r_usb_status)); -+ -+ /* FIXME: What should we do if we get ourun or perror? Dump the EP and SB -+ list for the corresponding epid? */ -+ if (reg->r_usb_status & IO_MASK(R_USB_STATUS, ourun)) { -+ panic("USB controller got ourun."); -+ } -+ if (reg->r_usb_status & IO_MASK(R_USB_STATUS, perror)) { -+ -+ /* Before, etrax_usb_do_intr_recover was called on this epid if it was -+ an interrupt pipe. I don't see how re-enabling all EP descriptors -+ will help if there was a programming error. */ -+ panic("USB controller got perror."); -+ } -+ -+ /* Keep track of USB Controller, if it's running or not */ -+ if(reg->r_usb_status & IO_STATE(R_USB_STATUS, running, yes)) { -+ crisv10_hcd->running = 1; -+ } else { -+ crisv10_hcd->running = 0; -+ } -+ -+ if (reg->r_usb_status & IO_MASK(R_USB_STATUS, device_mode)) { -+ /* We should never operate in device mode. */ -+ panic("USB controller in device mode."); -+ } -+ -+ /* Set the flag to avoid getting "Unlink after no-IRQ? Controller is probably -+ using the wrong IRQ" from hcd_unlink_urb() in drivers/usb/core/hcd.c */ -+ set_bit(HCD_FLAG_SAW_IRQ, ®->hcd->flags); -+ -+ DBFEXIT; -+} -+ -+ -+/******************************************************************/ -+/* Host Controller interface functions */ -+/******************************************************************/ -+ -+static inline void crisv10_ready_wait(void) { -+ volatile int timeout = 10000; -+ /* Check the busy bit of USB controller in Etrax */ -+ while((*R_USB_COMMAND & IO_MASK(R_USB_COMMAND, busy)) && -+ (timeout-- > 0)); -+ if(timeout == 0) { -+ warn("Timeout while waiting for USB controller to be idle\n"); -+ } -+} -+ -+/* reset host controller */ -+static int crisv10_hcd_reset(struct usb_hcd *hcd) -+{ -+ DBFENTER; -+ hcd_dbg(hcd, "reset\n"); -+ -+ -+ /* Reset the USB interface. */ -+ /* -+ *R_USB_COMMAND = -+ IO_STATE(R_USB_COMMAND, port_sel, nop) | -+ IO_STATE(R_USB_COMMAND, port_cmd, reset) | -+ IO_STATE(R_USB_COMMAND, ctrl_cmd, reset); -+ nop(); -+ */ -+ DBFEXIT; -+ return 0; -+} -+ -+/* start host controller */ -+static int crisv10_hcd_start(struct usb_hcd *hcd) -+{ -+ DBFENTER; -+ hcd_dbg(hcd, "start\n"); -+ -+ crisv10_ready_wait(); -+ -+ /* Start processing of USB traffic. */ -+ *R_USB_COMMAND = -+ IO_STATE(R_USB_COMMAND, port_sel, nop) | -+ IO_STATE(R_USB_COMMAND, port_cmd, reset) | -+ IO_STATE(R_USB_COMMAND, ctrl_cmd, host_run); -+ -+ nop(); -+ -+ hcd->state = HC_STATE_RUNNING; -+ -+ DBFEXIT; -+ return 0; -+} -+ -+/* stop host controller */ -+static void crisv10_hcd_stop(struct usb_hcd *hcd) -+{ -+ DBFENTER; -+ hcd_dbg(hcd, "stop\n"); -+ crisv10_hcd_reset(hcd); -+ DBFEXIT; -+} -+ -+/* return the current frame number */ -+static int crisv10_hcd_get_frame(struct usb_hcd *hcd) -+{ -+ DBFENTER; -+ DBFEXIT; -+ return (*R_USB_FM_NUMBER & 0x7ff); -+} -+ -+#ifdef CONFIG_USB_OTG -+ -+static int crisv10_hcd_start_port_reset(struct usb_hcd *hcd, unsigned port) -+{ -+ return 0; /* no-op for now */ -+} -+ -+#endif /* CONFIG_USB_OTG */ -+ -+ -+/******************************************************************/ -+/* Root Hub functions */ -+/******************************************************************/ -+ -+/* root hub status */ -+static const struct usb_hub_status rh_hub_status = -+ { -+ .wHubStatus = 0, -+ .wHubChange = 0, -+ }; -+ -+/* root hub descriptor */ -+static const u8 rh_hub_descr[] = -+ { -+ 0x09, /* bDescLength */ -+ 0x29, /* bDescriptorType */ -+ USB_ROOT_HUB_PORTS, /* bNbrPorts */ -+ 0x00, /* wHubCharacteristics */ -+ 0x00, -+ 0x01, /* bPwrOn2pwrGood */ -+ 0x00, /* bHubContrCurrent */ -+ 0x00, /* DeviceRemovable */ -+ 0xff /* PortPwrCtrlMask */ -+ }; -+ -+/* Actual holder of root hub status*/ -+struct crisv10_rh rh; -+ -+/* Initialize root hub data structures (called from dvdrv_hcd_probe()) */ -+int rh_init(void) { -+ int i; -+ /* Reset port status flags */ -+ for (i = 0; i < USB_ROOT_HUB_PORTS; i++) { -+ rh.wPortChange[i] = 0; -+ rh.wPortStatusPrev[i] = 0; -+ } -+ return 0; -+} -+ -+#define RH_FEAT_MASK ((1<lock); -+ for (i = 1; i <= crisv10_hcd->num_ports; i++) { -+ if (rh.wPortChange[map_port(i)]) { -+ *buf |= (1 << i); -+ rh_dbg("rh_status_data_request, change on port %d: %s Current Status: %s\n", i, -+ port_status_to_str(rh.wPortChange[map_port(i)]), -+ port_status_to_str(rh.wPortStatusPrev[map_port(i)])); -+ } -+ } -+ spin_unlock(&crisv10_hcd->lock); -+ -+// DBFEXIT; -+ -+ return *buf == 0 ? 0 : 1; -+} -+ -+/* Handle a control request for the root hub (called from hcd_driver) */ -+static int rh_control_request(struct usb_hcd *hcd, -+ u16 typeReq, -+ u16 wValue, -+ u16 wIndex, -+ char *buf, -+ u16 wLength) { -+ -+ struct crisv10_hcd *crisv10_hcd = hcd_to_crisv10_hcd(hcd); -+ int retval = 0; -+ int len; -+ DBFENTER; -+ -+ switch (typeReq) { -+ case GetHubDescriptor: -+ rh_dbg("GetHubDescriptor\n"); -+ len = min_t(unsigned int, sizeof rh_hub_descr, wLength); -+ memcpy(buf, rh_hub_descr, len); -+ buf[2] = crisv10_hcd->num_ports; -+ break; -+ case GetHubStatus: -+ rh_dbg("GetHubStatus\n"); -+ len = min_t(unsigned int, sizeof rh_hub_status, wLength); -+ memcpy(buf, &rh_hub_status, len); -+ break; -+ case GetPortStatus: -+ if (!wIndex || wIndex > crisv10_hcd->num_ports) -+ goto error; -+ rh_dbg("GetportStatus, port:%d change:%s status:%s\n", wIndex, -+ port_status_to_str(rh.wPortChange[map_port(wIndex)]), -+ port_status_to_str(rh.wPortStatusPrev[map_port(wIndex)])); -+ *(u16 *) buf = cpu_to_le16(rh.wPortStatusPrev[map_port(wIndex)]); -+ *(u16 *) (buf + 2) = cpu_to_le16(rh.wPortChange[map_port(wIndex)]); -+ break; -+ case SetHubFeature: -+ rh_dbg("SetHubFeature\n"); -+ case ClearHubFeature: -+ rh_dbg("ClearHubFeature\n"); -+ switch (wValue) { -+ case C_HUB_OVER_CURRENT: -+ case C_HUB_LOCAL_POWER: -+ rh_warn("Not implemented hub request:%d \n", typeReq); -+ /* not implemented */ -+ break; -+ default: -+ goto error; -+ } -+ break; -+ case SetPortFeature: -+ if (!wIndex || wIndex > crisv10_hcd->num_ports) -+ goto error; -+ if(rh_set_port_feature(map_port(wIndex), wValue)) -+ goto error; -+ break; -+ case ClearPortFeature: -+ if (!wIndex || wIndex > crisv10_hcd->num_ports) -+ goto error; -+ if(rh_clear_port_feature(map_port(wIndex), wValue)) -+ goto error; -+ break; -+ default: -+ rh_warn("Unknown hub request: %d\n", typeReq); -+ error: -+ retval = -EPIPE; -+ } -+ DBFEXIT; -+ return retval; -+} -+ -+int rh_set_port_feature(__u8 bPort, __u16 wFeature) { -+ __u8 bUsbCommand = 0; -+ switch(wFeature) { -+ case USB_PORT_FEAT_RESET: -+ rh_dbg("SetPortFeature: reset\n"); -+ bUsbCommand |= IO_STATE(R_USB_COMMAND, port_cmd, reset); -+ goto set; -+ break; -+ case USB_PORT_FEAT_SUSPEND: -+ rh_dbg("SetPortFeature: suspend\n"); -+ bUsbCommand |= IO_STATE(R_USB_COMMAND, port_cmd, suspend); -+ goto set; -+ break; -+ case USB_PORT_FEAT_POWER: -+ rh_dbg("SetPortFeature: power\n"); -+ break; -+ case USB_PORT_FEAT_C_CONNECTION: -+ rh_dbg("SetPortFeature: c_connection\n"); -+ break; -+ case USB_PORT_FEAT_C_RESET: -+ rh_dbg("SetPortFeature: c_reset\n"); -+ break; -+ case USB_PORT_FEAT_C_OVER_CURRENT: -+ rh_dbg("SetPortFeature: c_over_current\n"); -+ break; -+ -+ set: -+ /* Select which port via the port_sel field */ -+ bUsbCommand |= IO_FIELD(R_USB_COMMAND, port_sel, bPort+1); -+ -+ /* Make sure the controller isn't busy. */ -+ crisv10_ready_wait(); -+ /* Send out the actual command to the USB controller */ -+ *R_USB_COMMAND = bUsbCommand; -+ -+ /* If port reset then also bring USB controller into running state */ -+ if(wFeature == USB_PORT_FEAT_RESET) { -+ /* Wait a while for controller to first become started after port reset */ -+ udelay(12000); /* 12ms blocking wait */ -+ -+ /* Make sure the controller isn't busy. */ -+ crisv10_ready_wait(); -+ -+ /* If all enabled ports were disabled the host controller goes down into -+ started mode, so we need to bring it back into the running state. -+ (This is safe even if it's already in the running state.) */ -+ *R_USB_COMMAND = -+ IO_STATE(R_USB_COMMAND, port_sel, nop) | -+ IO_STATE(R_USB_COMMAND, port_cmd, reset) | -+ IO_STATE(R_USB_COMMAND, ctrl_cmd, host_run); -+ } -+ -+ break; -+ default: -+ rh_dbg("SetPortFeature: unknown feature\n"); -+ return -1; -+ } -+ return 0; -+} -+ -+int rh_clear_port_feature(__u8 bPort, __u16 wFeature) { -+ switch(wFeature) { -+ case USB_PORT_FEAT_ENABLE: -+ rh_dbg("ClearPortFeature: enable\n"); -+ rh_disable_port(bPort); -+ break; -+ case USB_PORT_FEAT_SUSPEND: -+ rh_dbg("ClearPortFeature: suspend\n"); -+ break; -+ case USB_PORT_FEAT_POWER: -+ rh_dbg("ClearPortFeature: power\n"); -+ break; -+ -+ case USB_PORT_FEAT_C_ENABLE: -+ rh_dbg("ClearPortFeature: c_enable\n"); -+ goto clear; -+ case USB_PORT_FEAT_C_SUSPEND: -+ rh_dbg("ClearPortFeature: c_suspend\n"); -+ goto clear; -+ case USB_PORT_FEAT_C_CONNECTION: -+ rh_dbg("ClearPortFeature: c_connection\n"); -+ goto clear; -+ case USB_PORT_FEAT_C_OVER_CURRENT: -+ rh_dbg("ClearPortFeature: c_over_current\n"); -+ goto clear; -+ case USB_PORT_FEAT_C_RESET: -+ rh_dbg("ClearPortFeature: c_reset\n"); -+ goto clear; -+ clear: -+ rh.wPortChange[bPort] &= ~(1 << (wFeature - 16)); -+ break; -+ default: -+ rh_dbg("ClearPortFeature: unknown feature\n"); -+ return -1; -+ } -+ return 0; -+} -+ -+ -+#ifdef CONFIG_PM -+/* Handle a suspend request for the root hub (called from hcd_driver) */ -+static int rh_suspend_request(struct usb_hcd *hcd) -+{ -+ return 0; /* no-op for now */ -+} -+ -+/* Handle a resume request for the root hub (called from hcd_driver) */ -+static int rh_resume_request(struct usb_hcd *hcd) -+{ -+ return 0; /* no-op for now */ -+} -+#endif /* CONFIG_PM */ -+ -+ -+ -+/* Wrapper function for workaround port disable registers in USB controller */ -+static void rh_disable_port(unsigned int port) { -+ volatile int timeout = 10000; -+ volatile char* usb_portx_disable; -+ switch(port) { -+ case 0: -+ usb_portx_disable = R_USB_PORT1_DISABLE; -+ break; -+ case 1: -+ usb_portx_disable = R_USB_PORT2_DISABLE; -+ break; -+ default: -+ /* Invalid port index */ -+ return; -+ } -+ /* Set disable flag in special register */ -+ *usb_portx_disable = IO_STATE(R_USB_PORT1_DISABLE, disable, yes); -+ /* Wait until not enabled anymore */ -+ while((rh.wPortStatusPrev[port] & -+ IO_STATE(R_USB_RH_PORT_STATUS_1, enabled, yes)) && -+ (timeout-- > 0)); -+ if(timeout == 0) { -+ warn("Timeout while waiting for port %d to become disabled\n", port); -+ } -+ /* clear disable flag in special register */ -+ *usb_portx_disable = IO_STATE(R_USB_PORT1_DISABLE, disable, no); -+ rh_info("Physical port %d disabled\n", port+1); -+} -+ -+ -+/******************************************************************/ -+/* Transfer Controller (TC) functions */ -+/******************************************************************/ -+ -+/* FIXME: Should RX_BUF_SIZE be a config option, or maybe we should adjust it -+ dynamically? -+ To adjust it dynamically we would have to get an interrupt when we reach -+ the end of the rx descriptor list, or when we get close to the end, and -+ then allocate more descriptors. */ -+#define NBR_OF_RX_DESC 512 -+#define RX_DESC_BUF_SIZE 1024 -+#define RX_BUF_SIZE (NBR_OF_RX_DESC * RX_DESC_BUF_SIZE) -+ -+ -+/* Local variables for Transfer Controller */ -+/* --------------------------------------- */ -+ -+/* This is a circular (double-linked) list of the active urbs for each epid. -+ The head is never removed, and new urbs are linked onto the list as -+ urb_entry_t elements. Don't reference urb_list directly; use the wrapper -+ functions instead (which includes spin_locks) */ -+static struct list_head urb_list[NBR_OF_EPIDS]; -+ -+/* Read about the need and usage of this lock in submit_ctrl_urb. */ -+/* Lock for URB lists for each EPID */ -+static spinlock_t urb_list_lock; -+ -+/* Lock for EPID array register (R_USB_EPT_x) in Etrax */ -+static spinlock_t etrax_epid_lock; -+ -+/* Lock for dma8 sub0 handling */ -+static spinlock_t etrax_dma8_sub0_lock; -+ -+/* DMA IN cache bug. Align the DMA IN buffers to 32 bytes, i.e. a cache line. -+ Since RX_DESC_BUF_SIZE is 1024 is a multiple of 32, all rx buffers will be -+ cache aligned. */ -+static volatile unsigned char RxBuf[RX_BUF_SIZE] __attribute__ ((aligned (32))); -+static volatile struct USB_IN_Desc RxDescList[NBR_OF_RX_DESC] __attribute__ ((aligned (4))); -+ -+/* Pointers into RxDescList. */ -+static volatile struct USB_IN_Desc *myNextRxDesc; -+static volatile struct USB_IN_Desc *myLastRxDesc; -+ -+/* A zout transfer makes a memory access at the address of its buf pointer, -+ which means that setting this buf pointer to 0 will cause an access to the -+ flash. In addition to this, setting sw_len to 0 results in a 16/32 bytes -+ (depending on DMA burst size) transfer. -+ Instead, we set it to 1, and point it to this buffer. */ -+static int zout_buffer[4] __attribute__ ((aligned (4))); -+ -+/* Cache for allocating new EP and SB descriptors. */ -+//static kmem_cache_t *usb_desc_cache; -+static struct kmem_cache *usb_desc_cache; -+ -+/* Cache for the data allocated in the isoc descr top half. */ -+//static kmem_cache_t *isoc_compl_cache; -+static struct kmem_cache *isoc_compl_cache; -+ -+/* Cache for the data allocated when delayed finishing of URBs */ -+//static kmem_cache_t *later_data_cache; -+static struct kmem_cache *later_data_cache; -+ -+/* Counter to keep track of how many Isoc EP we have sat up. Used to enable -+ and disable iso_eof interrupt. We only need these interrupts when we have -+ Isoc data endpoints (consumes CPU cycles). -+ FIXME: This could be more fine granular, so this interrupt is only enabled -+ when we have a In Isoc URB not URB_ISO_ASAP flaged queued. */ -+static int isoc_epid_counter; -+ -+/* Protecting wrapper functions for R_USB_EPT_x */ -+/* -------------------------------------------- */ -+static inline void etrax_epid_set(__u8 index, __u32 data) { -+ unsigned long flags; -+ spin_lock_irqsave(&etrax_epid_lock, flags); -+ *R_USB_EPT_INDEX = IO_FIELD(R_USB_EPT_INDEX, value, index); -+ nop(); -+ *R_USB_EPT_DATA = data; -+ spin_unlock_irqrestore(&etrax_epid_lock, flags); -+} -+ -+static inline void etrax_epid_clear_error(__u8 index) { -+ unsigned long flags; -+ spin_lock_irqsave(&etrax_epid_lock, flags); -+ *R_USB_EPT_INDEX = IO_FIELD(R_USB_EPT_INDEX, value, index); -+ nop(); -+ *R_USB_EPT_DATA &= -+ ~(IO_MASK(R_USB_EPT_DATA, error_count_in) | -+ IO_MASK(R_USB_EPT_DATA, error_count_out) | -+ IO_MASK(R_USB_EPT_DATA, error_code)); -+ spin_unlock_irqrestore(&etrax_epid_lock, flags); -+} -+ -+static inline void etrax_epid_set_toggle(__u8 index, __u8 dirout, -+ __u8 toggle) { -+ unsigned long flags; -+ spin_lock_irqsave(&etrax_epid_lock, flags); -+ *R_USB_EPT_INDEX = IO_FIELD(R_USB_EPT_INDEX, value, index); -+ nop(); -+ if(dirout) { -+ *R_USB_EPT_DATA &= ~IO_MASK(R_USB_EPT_DATA, t_out); -+ *R_USB_EPT_DATA |= IO_FIELD(R_USB_EPT_DATA, t_out, toggle); -+ } else { -+ *R_USB_EPT_DATA &= ~IO_MASK(R_USB_EPT_DATA, t_in); -+ *R_USB_EPT_DATA |= IO_FIELD(R_USB_EPT_DATA, t_in, toggle); -+ } -+ spin_unlock_irqrestore(&etrax_epid_lock, flags); -+} -+ -+static inline __u8 etrax_epid_get_toggle(__u8 index, __u8 dirout) { -+ unsigned long flags; -+ __u8 toggle; -+ spin_lock_irqsave(&etrax_epid_lock, flags); -+ *R_USB_EPT_INDEX = IO_FIELD(R_USB_EPT_INDEX, value, index); -+ nop(); -+ if (dirout) { -+ toggle = IO_EXTRACT(R_USB_EPT_DATA, t_out, *R_USB_EPT_DATA); -+ } else { -+ toggle = IO_EXTRACT(R_USB_EPT_DATA, t_in, *R_USB_EPT_DATA); -+ } -+ spin_unlock_irqrestore(&etrax_epid_lock, flags); -+ return toggle; -+} -+ -+ -+static inline __u32 etrax_epid_get(__u8 index) { -+ unsigned long flags; -+ __u32 data; -+ spin_lock_irqsave(&etrax_epid_lock, flags); -+ *R_USB_EPT_INDEX = IO_FIELD(R_USB_EPT_INDEX, value, index); -+ nop(); -+ data = *R_USB_EPT_DATA; -+ spin_unlock_irqrestore(&etrax_epid_lock, flags); -+ return data; -+} -+ -+ -+ -+ -+/* Main functions for Transfer Controller */ -+/* -------------------------------------- */ -+ -+/* Init structs, memories and lists used by Transfer Controller */ -+int tc_init(struct usb_hcd *hcd) { -+ int i; -+ /* Clear software state info for all epids */ -+ memset(epid_state, 0, sizeof(struct etrax_epid) * NBR_OF_EPIDS); -+ -+ /* Set Invalid and Dummy as being in use and disabled */ -+ epid_state[INVALID_EPID].inuse = 1; -+ epid_state[DUMMY_EPID].inuse = 1; -+ epid_state[INVALID_EPID].disabled = 1; -+ epid_state[DUMMY_EPID].disabled = 1; -+ -+ /* Clear counter for how many Isoc epids we have sat up */ -+ isoc_epid_counter = 0; -+ -+ /* Initialize the urb list by initiating a head for each list. -+ Also reset list hodling active URB for each epid */ -+ for (i = 0; i < NBR_OF_EPIDS; i++) { -+ INIT_LIST_HEAD(&urb_list[i]); -+ activeUrbList[i] = NULL; -+ } -+ -+ /* Init lock for URB lists */ -+ spin_lock_init(&urb_list_lock); -+ /* Init lock for Etrax R_USB_EPT register */ -+ spin_lock_init(&etrax_epid_lock); -+ /* Init lock for Etrax dma8 sub0 handling */ -+ spin_lock_init(&etrax_dma8_sub0_lock); -+ -+ /* We use kmem_cache_* to make sure that all DMA desc. are dword aligned */ -+ -+ /* Note that we specify sizeof(struct USB_EP_Desc) as the size, but also -+ allocate SB descriptors from this cache. This is ok since -+ sizeof(struct USB_EP_Desc) == sizeof(struct USB_SB_Desc). */ -+// usb_desc_cache = kmem_cache_create("usb_desc_cache", -+// sizeof(struct USB_EP_Desc), 0, -+// SLAB_HWCACHE_ALIGN, 0, 0); -+ usb_desc_cache = kmem_cache_create( -+ "usb_desc_cache", -+ sizeof(struct USB_EP_Desc), -+ 0, -+ SLAB_HWCACHE_ALIGN, -+ NULL); -+ if(usb_desc_cache == NULL) { -+ return -ENOMEM; -+ } -+ -+ /* Create slab cache for speedy allocation of memory for isoc bottom-half -+ interrupt handling */ -+// isoc_compl_cache = -+// kmem_cache_create("isoc_compl_cache", -+// sizeof(struct crisv10_isoc_complete_data), -+// 0, SLAB_HWCACHE_ALIGN, 0, 0); -+ isoc_compl_cache = kmem_cache_create( -+ "isoc_compl_cache", -+ sizeof(struct crisv10_isoc_complete_data), -+ 0, -+ SLAB_HWCACHE_ALIGN, -+ NULL -+ ); -+ -+ if(isoc_compl_cache == NULL) { -+ return -ENOMEM; -+ } -+ -+ /* Create slab cache for speedy allocation of memory for later URB finish -+ struct */ -+// later_data_cache = -+// kmem_cache_create("later_data_cache", -+// sizeof(struct urb_later_data), -+// 0, SLAB_HWCACHE_ALIGN, 0, 0); -+ -+ later_data_cache = kmem_cache_create( -+ "later_data_cache", -+ sizeof(struct urb_later_data), -+ 0, -+ SLAB_HWCACHE_ALIGN, -+ NULL -+ ); -+ -+ if(later_data_cache == NULL) { -+ return -ENOMEM; -+ } -+ -+ -+ /* Initiate the bulk start timer. */ -+ init_timer(&bulk_start_timer); -+ bulk_start_timer.expires = jiffies + BULK_START_TIMER_INTERVAL; -+ bulk_start_timer.function = tc_bulk_start_timer_func; -+ add_timer(&bulk_start_timer); -+ -+ -+ /* Initiate the bulk eot timer. */ -+ init_timer(&bulk_eot_timer); -+ bulk_eot_timer.expires = jiffies + BULK_EOT_TIMER_INTERVAL; -+ bulk_eot_timer.function = tc_bulk_eot_timer_func; -+ bulk_eot_timer.data = (unsigned long)hcd; -+ add_timer(&bulk_eot_timer); -+ -+ return 0; -+} -+ -+/* Uninitialize all resources used by Transfer Controller */ -+void tc_destroy(void) { -+ -+ /* Destroy all slab cache */ -+ kmem_cache_destroy(usb_desc_cache); -+ kmem_cache_destroy(isoc_compl_cache); -+ kmem_cache_destroy(later_data_cache); -+ -+ /* Remove timers */ -+ del_timer(&bulk_start_timer); -+ del_timer(&bulk_eot_timer); -+} -+ -+static void restart_dma8_sub0(void) { -+ unsigned long flags; -+ spin_lock_irqsave(&etrax_dma8_sub0_lock, flags); -+ /* Verify that the dma is not running */ -+ if ((*R_DMA_CH8_SUB0_CMD & IO_MASK(R_DMA_CH8_SUB0_CMD, cmd)) == 0) { -+ struct USB_EP_Desc *ep = (struct USB_EP_Desc *)phys_to_virt(*R_DMA_CH8_SUB0_EP); -+ while (DUMMY_EPID == IO_EXTRACT(USB_EP_command, epid, ep->command)) { -+ ep = (struct USB_EP_Desc *)phys_to_virt(ep->next); -+ } -+ /* Advance the DMA to the next EP descriptor that is not a DUMMY_EPID. -+ * ep->next is already a physical address. virt_to_phys is needed, see -+ * http://mhonarc.axis.se/dev-etrax/msg08630.html -+ */ -+ //*R_DMA_CH8_SUB0_EP = ep->next; -+ *R_DMA_CH8_SUB0_EP = virt_to_phys(ep); -+ /* Restart the DMA */ -+ *R_DMA_CH8_SUB0_CMD = IO_STATE(R_DMA_CH8_SUB0_CMD, cmd, start); -+ } -+ spin_unlock_irqrestore(&etrax_dma8_sub0_lock, flags); -+} -+ -+/* queue an URB with the transfer controller (called from hcd_driver) */ -+//static int tc_urb_enqueue(struct usb_hcd *hcd, -+// struct usb_host_endpoint *ep, -+// struct urb *urb, -+// gfp_t mem_flags) { -+static int tc_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags) -+{ -+ int epid; -+ int retval; -+// int bustime = 0; -+ int maxpacket; -+ unsigned long flags; -+ struct crisv10_urb_priv *urb_priv; -+ struct crisv10_hcd* crisv10_hcd = hcd_to_crisv10_hcd(hcd); -+ DBFENTER; -+ -+ if(!(crisv10_hcd->running)) { -+ /* The USB Controller is not running, probably because no device is -+ attached. No idea to enqueue URBs then */ -+ tc_warn("Rejected enqueueing of URB:0x%x because no dev attached\n", -+ (unsigned int)urb); -+ return -ENOENT; -+ } -+ -+ maxpacket = usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)); -+ -+ /* hinko ignore usb_pipeisoc */ -+#if 0 -+ /* Special case check for In Isoc transfers. Specification states that each -+ In Isoc transfer consists of one packet and therefore it should fit into -+ the transfer-buffer of an URB. -+ We do the check here to be sure (an invalid scenario can be produced with -+ parameters to the usbtest suite) */ -+ if(usb_pipeisoc(urb->pipe) && usb_pipein(urb->pipe) && -+ (urb->transfer_buffer_length < maxpacket)) { -+ tc_err("Submit In Isoc URB with buffer length:%d to pipe with maxpacketlen: %d\n", urb->transfer_buffer_length, maxpacket); -+ return -EMSGSIZE; -+ } -+ -+ /* Check if there is enough bandwidth for periodic transfer */ -+ if(usb_pipeint(urb->pipe) || usb_pipeisoc(urb->pipe)) { -+ /* only check (and later claim) if not already claimed */ -+ if (urb->bandwidth == 0) { -+ bustime = usb_check_bandwidth(urb->dev, urb); -+ if (bustime < 0) { -+ tc_err("Not enough periodic bandwidth\n"); -+ return -ENOSPC; -+ } -+ } -+ } -+#endif -+ -+ /* Check if there is a epid for URBs destination, if not this function -+ set up one. */ -+ //epid = tc_setup_epid(ep, urb, mem_flags); -+ epid = tc_setup_epid(urb, mem_flags); -+ if (epid < 0) { -+ tc_err("Failed setup epid:%d for URB:0x%x\n", epid, (unsigned int)urb); -+ DBFEXIT; -+ return -ENOMEM; -+ } -+ -+ if(urb == activeUrbList[epid]) { -+ tc_err("Resubmition of allready active URB:0x%x\n", (unsigned int)urb); -+ return -ENXIO; -+ } -+ -+ if(urb_list_entry(urb, epid)) { -+ tc_err("Resubmition of allready queued URB:0x%x\n", (unsigned int)urb); -+ return -ENXIO; -+ } -+ -+ /* If we actively have flaged endpoint as disabled then refuse submition */ -+ if(epid_state[epid].disabled) { -+ return -ENOENT; -+ } -+ -+ /* Allocate and init HC-private data for URB */ -+ if(urb_priv_create(hcd, urb, epid, mem_flags) != 0) { -+ DBFEXIT; -+ return -ENOMEM; -+ } -+ urb_priv = urb->hcpriv; -+ -+ tc_dbg("Enqueue URB:0x%x[%d] epid:%d (%s) bufflen:%d\n", -+ (unsigned int)urb, urb_priv->urb_num, epid, -+ pipe_to_str(urb->pipe), urb->transfer_buffer_length); -+ -+ /* Create and link SBs required for this URB */ -+ retval = create_sb_for_urb(urb, mem_flags); -+ if(retval != 0) { -+ tc_err("Failed to create SBs for URB:0x%x[%d]\n", (unsigned int)urb, -+ urb_priv->urb_num); -+ urb_priv_free(hcd, urb); -+ DBFEXIT; -+ return retval; -+ } -+ -+ /* Init intr EP pool if this URB is a INTR transfer. This pool is later -+ used when inserting EPs in the TxIntrEPList. We do the alloc here -+ so we can't run out of memory later */ -+ if(usb_pipeint(urb->pipe)) { -+ retval = init_intr_urb(urb, mem_flags); -+ if(retval != 0) { -+ tc_warn("Failed to init Intr URB\n"); -+ urb_priv_free(hcd, urb); -+ DBFEXIT; -+ return retval; -+ } -+ } -+ -+ /* Disable other access when inserting USB */ -+ -+ /* BUG on sleeping inside int disabled if using local_irq_save/local_irq_restore -+ * her - because urb_list_add() and tc_dma_process_queue() save irqs again !??! -+ */ -+// local_irq_save(flags); -+ -+ /* hinko ignore usb_pipeisoc */ -+#if 0 -+ /* Claim bandwidth, if needed */ -+ if(bustime) { -+ usb_claim_bandwidth(urb->dev, urb, bustime, 0); -+ } -+ -+ /* Add URB to EP queue */ -+ urb_list_add(urb, epid, mem_flags); -+ -+ if(usb_pipeisoc(urb->pipe)) { -+ /* Special processing of Isoc URBs. */ -+ tc_dma_process_isoc_urb(urb); -+ } else { -+ /* Process EP queue for rest of the URB types (Bulk, Ctrl, Intr) */ -+ tc_dma_process_queue(epid); -+ } -+#endif -+ /* Add URB to EP queue */ -+ urb_list_add(urb, epid, mem_flags); -+ -+ /*hinko link/unlink urb -> ep */ -+ spin_lock_irqsave(&crisv10_hcd->lock, flags); -+ //spin_lock(&crisv10_hcd->lock); -+ retval = usb_hcd_link_urb_to_ep(hcd, urb); -+ if (retval) { -+ spin_unlock_irqrestore(&crisv10_hcd->lock, flags); -+ tc_warn("Failed to link urb to ep\n"); -+ urb_priv_free(hcd, urb); -+ DBFEXIT; -+ return retval; -+ } -+ spin_unlock_irqrestore(&crisv10_hcd->lock, flags); -+ //spin_unlock(&crisv10_hcd->lock); -+ -+ /* Process EP queue for rest of the URB types (Bulk, Ctrl, Intr) */ -+ tc_dma_process_queue(epid); -+ -+// local_irq_restore(flags); -+ -+ DBFEXIT; -+ return 0; -+} -+ -+/* remove an URB from the transfer controller queues (called from hcd_driver)*/ -+//static int tc_urb_dequeue(struct usb_hcd *hcd, struct urb *urb) -+static int tc_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) -+{ -+ struct crisv10_urb_priv *urb_priv; -+ unsigned long flags; -+ int epid; -+ -+ DBFENTER; -+ /* Disable interrupts here since a descriptor interrupt for the isoc epid -+ will modify the sb list. This could possibly be done more granular, but -+ urb_dequeue should not be used frequently anyway. -+ */ -+ local_irq_save(flags); -+ -+ urb_priv = urb->hcpriv; -+ -+ if (!urb_priv) { -+ /* This happens if a device driver calls unlink on an urb that -+ was never submitted (lazy driver) or if the urb was completed -+ while dequeue was being called. */ -+ tc_warn("Dequeing of not enqueued URB:0x%x\n", (unsigned int)urb); -+ local_irq_restore(flags); -+ return 0; -+ } -+ epid = urb_priv->epid; -+ -+ tc_warn("Dequeing %s URB:0x%x[%d] (%s %s epid:%d) status:%d %s\n", -+ (urb == activeUrbList[epid]) ? "active" : "queued", -+ (unsigned int)urb, urb_priv->urb_num, str_dir(urb->pipe), -+ str_type(urb->pipe), epid, urb->status, -+ (urb_priv->later_data) ? "later-sched" : ""); -+ -+ /* For Bulk, Ctrl and Intr are only one URB active at a time. So any URB -+ that isn't active can be dequeued by just removing it from the queue */ -+ if(usb_pipebulk(urb->pipe) || usb_pipecontrol(urb->pipe) || -+ usb_pipeint(urb->pipe)) { -+ -+ /* Check if URB haven't gone further than the queue */ -+ if(urb != activeUrbList[epid]) { -+ ASSERT(urb_priv->later_data == NULL); -+ tc_warn("Dequeing URB:0x%x[%d] (%s %s epid:%d) from queue" -+ " (not active)\n", (unsigned int)urb, urb_priv->urb_num, -+ str_dir(urb->pipe), str_type(urb->pipe), epid); -+ -+ /* Finish the URB with error status from USB core */ -+ tc_finish_urb(hcd, urb, urb->status); -+ local_irq_restore(flags); -+ return 0; -+ } -+ } -+ -+ /* Set URB status to Unlink for handling when interrupt comes. */ -+ urb_priv->urb_state = UNLINK; -+ -+ /* Differentiate dequeing of Bulk and Ctrl from Isoc and Intr */ -+ switch(usb_pipetype(urb->pipe)) { -+ case PIPE_BULK: -+ /* Check if EP still is enabled */ -+ if (TxBulkEPList[epid].command & IO_MASK(USB_EP_command, enable)) { -+ /* The EP was enabled, disable it. */ -+ TxBulkEPList[epid].command &= ~IO_MASK(USB_EP_command, enable); -+ } -+ /* Kicking dummy list out of the party. */ -+ TxBulkEPList[epid].next = virt_to_phys(&TxBulkEPList[(epid + 1) % NBR_OF_EPIDS]); -+ break; -+ case PIPE_CONTROL: -+ /* Check if EP still is enabled */ -+ if (TxCtrlEPList[epid].command & IO_MASK(USB_EP_command, enable)) { -+ /* The EP was enabled, disable it. */ -+ TxCtrlEPList[epid].command &= ~IO_MASK(USB_EP_command, enable); -+ } -+ break; -+ case PIPE_ISOCHRONOUS: -+ /* Disabling, busy-wait and unlinking of Isoc SBs will be done in -+ finish_isoc_urb(). Because there might the case when URB is dequeued -+ but there are other valid URBs waiting */ -+ -+ /* Check if In Isoc EP still is enabled */ -+ if (TxIsocEPList[epid].command & IO_MASK(USB_EP_command, enable)) { -+ /* The EP was enabled, disable it. */ -+ TxIsocEPList[epid].command &= ~IO_MASK(USB_EP_command, enable); -+ } -+ break; -+ case PIPE_INTERRUPT: -+ /* Special care is taken for interrupt URBs. EPs are unlinked in -+ tc_finish_urb */ -+ break; -+ default: -+ break; -+ } -+ -+ /* Asynchronous unlink, finish the URB later from scheduled or other -+ event (data finished, error) */ -+ tc_finish_urb_later(hcd, urb, urb->status); -+ -+ local_irq_restore(flags); -+ DBFEXIT; -+ return 0; -+} -+ -+ -+static void tc_sync_finish_epid(struct usb_hcd *hcd, int epid) { -+ volatile int timeout = 10000; -+ struct urb* urb; -+ struct crisv10_urb_priv* urb_priv; -+ unsigned long flags; -+ -+ volatile struct USB_EP_Desc *first_ep; /* First EP in the list. */ -+ volatile struct USB_EP_Desc *curr_ep; /* Current EP, the iterator. */ -+ volatile struct USB_EP_Desc *next_ep; /* The EP after current. */ -+ -+ int type = epid_state[epid].type; -+ -+ /* Setting this flag will cause enqueue() to return -ENOENT for new -+ submitions on this endpoint and finish_urb() wont process queue further */ -+ epid_state[epid].disabled = 1; -+ -+ switch(type) { -+ case PIPE_BULK: -+ /* Check if EP still is enabled */ -+ if (TxBulkEPList[epid].command & IO_MASK(USB_EP_command, enable)) { -+ /* The EP was enabled, disable it. */ -+ TxBulkEPList[epid].command &= ~IO_MASK(USB_EP_command, enable); -+ tc_warn("sync_finish: Disabling EP for epid:%d\n", epid); -+ -+ /* Do busy-wait until DMA not using this EP descriptor anymore */ -+ while((*R_DMA_CH8_SUB0_EP == -+ virt_to_phys(&TxBulkEPList[epid])) && -+ (timeout-- > 0)); -+ if(timeout == 0) { -+ warn("Timeout while waiting for DMA-TX-Bulk to leave EP for" -+ " epid:%d\n", epid); -+ } -+ } -+ break; -+ -+ case PIPE_CONTROL: -+ /* Check if EP still is enabled */ -+ if (TxCtrlEPList[epid].command & IO_MASK(USB_EP_command, enable)) { -+ /* The EP was enabled, disable it. */ -+ TxCtrlEPList[epid].command &= ~IO_MASK(USB_EP_command, enable); -+ tc_warn("sync_finish: Disabling EP for epid:%d\n", epid); -+ -+ /* Do busy-wait until DMA not using this EP descriptor anymore */ -+ while((*R_DMA_CH8_SUB1_EP == -+ virt_to_phys(&TxCtrlEPList[epid])) && -+ (timeout-- > 0)); -+ if(timeout == 0) { -+ warn("Timeout while waiting for DMA-TX-Ctrl to leave EP for" -+ " epid:%d\n", epid); -+ } -+ } -+ break; -+ -+ case PIPE_INTERRUPT: -+ local_irq_save(flags); -+ /* Disable all Intr EPs belonging to epid */ -+ first_ep = &TxIntrEPList[0]; -+ curr_ep = first_ep; -+ do { -+ next_ep = (struct USB_EP_Desc *)phys_to_virt(curr_ep->next); -+ if (IO_EXTRACT(USB_EP_command, epid, next_ep->command) == epid) { -+ /* Disable EP */ -+ next_ep->command &= ~IO_MASK(USB_EP_command, enable); -+ } -+ curr_ep = phys_to_virt(curr_ep->next); -+ } while (curr_ep != first_ep); -+ -+ local_irq_restore(flags); -+ break; -+ -+ case PIPE_ISOCHRONOUS: -+ /* Check if EP still is enabled */ -+ if (TxIsocEPList[epid].command & IO_MASK(USB_EP_command, enable)) { -+ tc_warn("sync_finish: Disabling Isoc EP for epid:%d\n", epid); -+ /* The EP was enabled, disable it. */ -+ TxIsocEPList[epid].command &= ~IO_MASK(USB_EP_command, enable); -+ -+ while((*R_DMA_CH8_SUB3_EP == virt_to_phys(&TxIsocEPList[epid])) && -+ (timeout-- > 0)); -+ if(timeout == 0) { -+ warn("Timeout while waiting for DMA-TX-Isoc to leave EP for" -+ " epid:%d\n", epid); -+ } -+ } -+ break; -+ } -+ -+ local_irq_save(flags); -+ -+ /* Finish if there is active URB for this endpoint */ -+ if(activeUrbList[epid] != NULL) { -+ urb = activeUrbList[epid]; -+ urb_priv = urb->hcpriv; -+ ASSERT(urb_priv); -+ tc_warn("Sync finish %s URB:0x%x[%d] (%s %s epid:%d) status:%d %s\n", -+ (urb == activeUrbList[epid]) ? "active" : "queued", -+ (unsigned int)urb, urb_priv->urb_num, str_dir(urb->pipe), -+ str_type(urb->pipe), epid, urb->status, -+ (urb_priv->later_data) ? "later-sched" : ""); -+ -+ tc_finish_urb(hcd, activeUrbList[epid], -ENOENT); -+ ASSERT(activeUrbList[epid] == NULL); -+ } -+ -+ /* Finish any queued URBs for this endpoint. There won't be any resubmitions -+ because epid_disabled causes enqueue() to fail for this endpoint */ -+ while((urb = urb_list_first(epid)) != NULL) { -+ urb_priv = urb->hcpriv; -+ ASSERT(urb_priv); -+ -+ tc_warn("Sync finish %s URB:0x%x[%d] (%s %s epid:%d) status:%d %s\n", -+ (urb == activeUrbList[epid]) ? "active" : "queued", -+ (unsigned int)urb, urb_priv->urb_num, str_dir(urb->pipe), -+ str_type(urb->pipe), epid, urb->status, -+ (urb_priv->later_data) ? "later-sched" : ""); -+ -+ tc_finish_urb(hcd, urb, -ENOENT); -+ } -+ epid_state[epid].disabled = 0; -+ local_irq_restore(flags); -+} -+ -+/* free resources associated with an endpoint (called from hcd_driver) */ -+static void tc_endpoint_disable(struct usb_hcd *hcd, -+ struct usb_host_endpoint *ep) { -+ DBFENTER; -+ /* Only free epid if it has been allocated. We get two endpoint_disable -+ requests for ctrl endpoints so ignore the second one */ -+ if(ep->hcpriv != NULL) { -+ struct crisv10_ep_priv *ep_priv = ep->hcpriv; -+ int epid = ep_priv->epid; -+ tc_warn("endpoint_disable ep:0x%x ep-priv:0x%x (%s) (epid:%d freed)\n", -+ (unsigned int)ep, (unsigned int)ep->hcpriv, -+ endpoint_to_str(&(ep->desc)), epid); -+ -+ tc_sync_finish_epid(hcd, epid); -+ -+ ASSERT(activeUrbList[epid] == NULL); -+ ASSERT(list_empty(&urb_list[epid])); -+ -+ tc_free_epid(ep); -+ } else { -+ tc_dbg("endpoint_disable ep:0x%x ep-priv:0x%x (%s)\n", (unsigned int)ep, -+ (unsigned int)ep->hcpriv, endpoint_to_str(&(ep->desc))); -+ } -+ DBFEXIT; -+} -+ -+//static void tc_finish_urb_later_proc(void *data) { -+static void tc_finish_urb_later_proc(struct work_struct *work) { -+ unsigned long flags; -+ //struct urb_later_data* uld = (struct urb_later_data*)data; -+ struct urb_later_data* uld = container_of(work, struct urb_later_data, ws.work); -+ local_irq_save(flags); -+ if(uld->urb == NULL) { -+ late_dbg("Later finish of URB = NULL (allready finished)\n"); -+ } else { -+ struct crisv10_urb_priv* urb_priv = uld->urb->hcpriv; -+ ASSERT(urb_priv); -+ if(urb_priv->urb_num == uld->urb_num) { -+ late_dbg("Later finish of URB:0x%x[%d]\n", (unsigned int)(uld->urb), -+ urb_priv->urb_num); -+ if(uld->status != uld->urb->status) { -+ errno_dbg("Later-finish URB with status:%d, later-status:%d\n", -+ uld->urb->status, uld->status); -+ } -+ if(uld != urb_priv->later_data) { -+ panic("Scheduled uld not same as URBs uld\n"); -+ } -+ tc_finish_urb(uld->hcd, uld->urb, uld->status); -+ } else { -+ late_warn("Ignoring later finish of URB:0x%x[%d]" -+ ", urb_num doesn't match current URB:0x%x[%d]", -+ (unsigned int)(uld->urb), uld->urb_num, -+ (unsigned int)(uld->urb), urb_priv->urb_num); -+ } -+ } -+ local_irq_restore(flags); -+ kmem_cache_free(later_data_cache, uld); -+} -+ -+static void tc_finish_urb_later(struct usb_hcd *hcd, struct urb *urb, -+ int status) { -+ struct crisv10_urb_priv *urb_priv = urb->hcpriv; -+ struct urb_later_data* uld; -+ -+ ASSERT(urb_priv); -+ -+ if(urb_priv->later_data != NULL) { -+ /* Later-finish allready scheduled for this URB, just update status to -+ return when finishing later */ -+ errno_dbg("Later-finish schedule change URB status:%d with new" -+ " status:%d\n", urb_priv->later_data->status, status); -+ -+ urb_priv->later_data->status = status; -+ return; -+ } -+ -+ uld = kmem_cache_alloc(later_data_cache, GFP_ATOMIC); -+ ASSERT(uld); -+ -+ uld->hcd = hcd; -+ uld->urb = urb; -+ uld->urb_num = urb_priv->urb_num; -+ uld->status = status; -+ -+ //INIT_WORK(&uld->ws, tc_finish_urb_later_proc, uld); -+ INIT_DELAYED_WORK(&uld->ws, tc_finish_urb_later_proc); -+ urb_priv->later_data = uld; -+ -+ /* Schedule the finishing of the URB to happen later */ -+ schedule_delayed_work(&uld->ws, LATER_TIMER_DELAY); -+} -+ -+ /* hinko ignore usb_pipeisoc */ -+#if 0 -+static void tc_finish_isoc_urb(struct usb_hcd *hcd, struct urb *urb, -+ int status); -+#endif -+ -+static void tc_finish_urb(struct usb_hcd *hcd, struct urb *urb, int status) { -+ struct crisv10_hcd* crisv10_hcd = hcd_to_crisv10_hcd(hcd); -+ struct crisv10_urb_priv *urb_priv = urb->hcpriv; -+ int epid; -+ char toggle; -+ int urb_num; -+ unsigned long flags; -+ -+ DBFENTER; -+ ASSERT(urb_priv != NULL); -+ epid = urb_priv->epid; -+ urb_num = urb_priv->urb_num; -+ -+ if(urb != activeUrbList[epid]) { -+ if(urb_list_entry(urb, epid)) { -+ /* Remove this URB from the list. Only happens when URB are finished -+ before having been processed (dequeing) */ -+ urb_list_del(urb, epid); -+ } else { -+ tc_warn("Finishing of URB:0x%x[%d] neither active or in queue for" -+ " epid:%d\n", (unsigned int)urb, urb_num, epid); -+ } -+ } -+ -+ /* Cancel any pending later-finish of this URB */ -+ if(urb_priv->later_data) { -+ urb_priv->later_data->urb = NULL; -+ } -+ -+ /* For an IN pipe, we always set the actual length, regardless of whether -+ there was an error or not (which means the device driver can use the data -+ if it wants to). */ -+ if(usb_pipein(urb->pipe)) { -+ urb->actual_length = urb_priv->rx_offset; -+ } else { -+ /* Set actual_length for OUT urbs also; the USB mass storage driver seems -+ to want that. */ -+ if (status == 0 && urb->status == -EINPROGRESS) { -+ urb->actual_length = urb->transfer_buffer_length; -+ } else { -+ /* We wouldn't know of any partial writes if there was an error. */ -+ urb->actual_length = 0; -+ } -+ } -+ -+ -+ /* URB status mangling */ -+ if(urb->status == -EINPROGRESS) { -+ /* The USB core hasn't changed the status, let's set our finish status */ -+ urb->status = status; -+ -+ if ((status == 0) && (urb->transfer_flags & URB_SHORT_NOT_OK) && -+ usb_pipein(urb->pipe) && -+ (urb->actual_length != urb->transfer_buffer_length)) { -+ /* URB_SHORT_NOT_OK means that short reads (shorter than the endpoint's -+ max length) is to be treated as an error. */ -+ errno_dbg("Finishing URB:0x%x[%d] with SHORT_NOT_OK flag and short" -+ " data:%d\n", (unsigned int)urb, urb_num, -+ urb->actual_length); -+ urb->status = -EREMOTEIO; -+ } -+ -+ if(urb_priv->urb_state == UNLINK) { -+ /* URB has been requested to be unlinked asynchronously */ -+ urb->status = -ECONNRESET; -+ errno_dbg("Fixing unlink status of URB:0x%x[%d] to:%d\n", -+ (unsigned int)urb, urb_num, urb->status); -+ } -+ } else { -+ /* The USB Core wants to signal some error via the URB, pass it through */ -+ } -+ -+ /* hinko ignore usb_pipeisoc */ -+#if 0 -+ /* use completely different finish function for Isoc URBs */ -+ if(usb_pipeisoc(urb->pipe)) { -+ tc_finish_isoc_urb(hcd, urb, status); -+ return; -+ } -+#endif -+ -+ /* Do special unlinking of EPs for Intr traffic */ -+ if(usb_pipeint(urb->pipe)) { -+ tc_dma_unlink_intr_urb(urb); -+ } -+ -+ /* hinko ignore usb_pipeisoc */ -+#if 0 -+ /* Release allocated bandwidth for periodic transfers */ -+ if(usb_pipeint(urb->pipe) || usb_pipeisoc(urb->pipe)) -+ usb_release_bandwidth(urb->dev, urb, 0); -+#endif -+ -+ /* This URB is active on EP */ -+ if(urb == activeUrbList[epid]) { -+ /* We need to fiddle with the toggle bits because the hardware doesn't do -+ it for us. */ -+ toggle = etrax_epid_get_toggle(epid, usb_pipeout(urb->pipe)); -+ usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), -+ usb_pipeout(urb->pipe), toggle); -+ -+ /* Checks for Ctrl and Bulk EPs */ -+ switch(usb_pipetype(urb->pipe)) { -+ case PIPE_BULK: -+ /* Check so Bulk EP realy is disabled before finishing active URB */ -+ ASSERT((TxBulkEPList[epid].command & IO_MASK(USB_EP_command, enable)) == -+ IO_STATE(USB_EP_command, enable, no)); -+ /* Disable sub-pointer for EP to avoid next tx_interrupt() to -+ process Bulk EP. */ -+ TxBulkEPList[epid].sub = 0; -+ /* No need to wait for the DMA before changing the next pointer. -+ The modulo NBR_OF_EPIDS isn't actually necessary, since we will never use -+ the last one (INVALID_EPID) for actual traffic. */ -+ TxBulkEPList[epid].next = -+ virt_to_phys(&TxBulkEPList[(epid + 1) % NBR_OF_EPIDS]); -+ break; -+ case PIPE_CONTROL: -+ /* Check so Ctrl EP realy is disabled before finishing active URB */ -+ ASSERT((TxCtrlEPList[epid].command & IO_MASK(USB_EP_command, enable)) == -+ IO_STATE(USB_EP_command, enable, no)); -+ /* Disable sub-pointer for EP to avoid next tx_interrupt() to -+ process Ctrl EP. */ -+ TxCtrlEPList[epid].sub = 0; -+ break; -+ } -+ } -+ -+ /* Free HC-private URB data*/ -+ urb_priv_free(hcd, urb); -+ -+ if(urb->status) { -+ errno_dbg("finish_urb (URB:0x%x[%d] %s %s) (data:%d) status:%d\n", -+ (unsigned int)urb, urb_num, str_dir(urb->pipe), -+ str_type(urb->pipe), urb->actual_length, urb->status); -+ } else { -+ tc_dbg("finish_urb (URB:0x%x[%d] %s %s) (data:%d) status:%d\n", -+ (unsigned int)urb, urb_num, str_dir(urb->pipe), -+ str_type(urb->pipe), urb->actual_length, urb->status); -+ } -+ -+ /* If we just finished an active URB, clear active pointer. */ -+ if (urb == activeUrbList[epid]) { -+ /* Make URB not active on EP anymore */ -+ activeUrbList[epid] = NULL; -+ -+ if(urb->status == 0) { -+ /* URB finished sucessfully, process queue to see if there are any more -+ URBs waiting before we call completion function.*/ -+ if(crisv10_hcd->running) { -+ /* Only process queue if USB controller is running */ -+ tc_dma_process_queue(epid); -+ } else { -+ tc_warn("No processing of queue for epid:%d, USB Controller not" -+ " running\n", epid); -+ } -+ } -+ } -+ -+ /* Hand the URB from HCD to its USB device driver, using its completion -+ functions */ -+// usb_hcd_giveback_urb (hcd, urb); -+ /** -+ * usb_hcd_unlink_urb_from_ep - remove an URB from its endpoint queue -+ * @hcd: host controller to which @urb was submitted -+ * @urb: URB being unlinked -+ * -+ * Host controller drivers should call this routine before calling -+ * usb_hcd_giveback_urb(). The HCD's private spinlock must be held and -+ * interrupts must be disabled. The actions carried out here are required -+ * for URB completion. -+ */ -+ -+ /*hinko link/unlink urb -> ep */ -+ //spin_lock(&crisv10_hcd->lock); -+ spin_lock_irqsave(&crisv10_hcd->lock, flags); -+ usb_hcd_unlink_urb_from_ep(hcd, urb); -+ usb_hcd_giveback_urb(hcd, urb, status); -+ //spin_unlock(&crisv10_hcd->lock); -+ spin_unlock_irqrestore(&crisv10_hcd->lock, flags); -+ -+ /* Check the queue once more if the URB returned with error, because we -+ didn't do it before the completion function because the specification -+ states that the queue should not restart until all it's unlinked -+ URBs have been fully retired, with the completion functions run */ -+ if(crisv10_hcd->running) { -+ /* Only process queue if USB controller is running */ -+ tc_dma_process_queue(epid); -+ } else { -+ tc_warn("No processing of queue for epid:%d, USB Controller not running\n", -+ epid); -+ } -+ -+ DBFEXIT; -+} -+ -+ /* hinko ignore usb_pipeisoc */ -+#if 0 -+static void tc_finish_isoc_urb(struct usb_hcd *hcd, struct urb *urb, -+ int status) { -+ struct crisv10_urb_priv *urb_priv = urb->hcpriv; -+ int epid, i; -+ volatile int timeout = 10000; -+ -+ ASSERT(urb_priv); -+ epid = urb_priv->epid; -+ -+ ASSERT(usb_pipeisoc(urb->pipe)); -+ -+ /* Set that all isoc packets have status and length set before -+ completing the urb. */ -+ for (i = urb_priv->isoc_packet_counter; i < urb->number_of_packets; i++){ -+ urb->iso_frame_desc[i].actual_length = 0; -+ urb->iso_frame_desc[i].status = -EPROTO; -+ } -+ -+ /* Check if the URB is currently active (done or error) */ -+ if(urb == activeUrbList[epid]) { -+ /* Check if there are another In Isoc URB queued for this epid */ -+ if (!list_empty(&urb_list[epid])&& !epid_state[epid].disabled) { -+ /* Move it from queue to active and mark it started so Isoc transfers -+ won't be interrupted. -+ All Isoc URBs data transfers are already added to DMA lists so we -+ don't have to insert anything in DMA lists here. */ -+ activeUrbList[epid] = urb_list_first(epid); -+ ((struct crisv10_urb_priv *)(activeUrbList[epid]->hcpriv))->urb_state = -+ STARTED; -+ urb_list_del(activeUrbList[epid], epid); -+ -+ if(urb->status) { -+ errno_dbg("finish_isoc_urb (URB:0x%x[%d] %s %s) (%d of %d packets)" -+ " status:%d, new waiting URB:0x%x[%d]\n", -+ (unsigned int)urb, urb_priv->urb_num, str_dir(urb->pipe), -+ str_type(urb->pipe), urb_priv->isoc_packet_counter, -+ urb->number_of_packets, urb->status, -+ (unsigned int)activeUrbList[epid], -+ ((struct crisv10_urb_priv *)(activeUrbList[epid]->hcpriv))->urb_num); -+ } -+ -+ } else { /* No other URB queued for this epid */ -+ if(urb->status) { -+ errno_dbg("finish_isoc_urb (URB:0x%x[%d] %s %s) (%d of %d packets)" -+ " status:%d, no new URB waiting\n", -+ (unsigned int)urb, urb_priv->urb_num, str_dir(urb->pipe), -+ str_type(urb->pipe), urb_priv->isoc_packet_counter, -+ urb->number_of_packets, urb->status); -+ } -+ -+ /* Check if EP is still enabled, then shut it down. */ -+ if (TxIsocEPList[epid].command & IO_MASK(USB_EP_command, enable)) { -+ isoc_dbg("Isoc EP enabled for epid:%d, disabling it\n", epid); -+ -+ /* Should only occur for In Isoc EPs where SB isn't consumed. */ -+ ASSERT(usb_pipein(urb->pipe)); -+ -+ /* Disable it and wait for it to stop */ -+ TxIsocEPList[epid].command &= ~IO_MASK(USB_EP_command, enable); -+ -+ /* Ah, the luxury of busy-wait. */ -+ while((*R_DMA_CH8_SUB3_EP == virt_to_phys(&TxIsocEPList[epid])) && -+ (timeout-- > 0)); -+ if(timeout == 0) { -+ warn("Timeout while waiting for DMA-TX-Isoc to leave EP for epid:%d\n", epid); -+ } -+ } -+ -+ /* Unlink SB to say that epid is finished. */ -+ TxIsocEPList[epid].sub = 0; -+ TxIsocEPList[epid].hw_len = 0; -+ -+ /* No URB active for EP anymore */ -+ activeUrbList[epid] = NULL; -+ } -+ } else { /* Finishing of not active URB (queued up with SBs thought) */ -+ isoc_warn("finish_isoc_urb (URB:0x%x %s) (%d of %d packets) status:%d," -+ " SB queued but not active\n", -+ (unsigned int)urb, str_dir(urb->pipe), -+ urb_priv->isoc_packet_counter, urb->number_of_packets, -+ urb->status); -+ if(usb_pipeout(urb->pipe)) { -+ /* Finishing of not yet active Out Isoc URB needs unlinking of SBs. */ -+ struct USB_SB_Desc *iter_sb, *prev_sb, *next_sb; -+ -+ iter_sb = TxIsocEPList[epid].sub ? -+ phys_to_virt(TxIsocEPList[epid].sub) : 0; -+ prev_sb = 0; -+ -+ /* SB that is linked before this URBs first SB */ -+ while (iter_sb && (iter_sb != urb_priv->first_sb)) { -+ prev_sb = iter_sb; -+ iter_sb = iter_sb->next ? phys_to_virt(iter_sb->next) : 0; -+ } -+ -+ if (iter_sb == 0) { -+ /* Unlink of the URB currently being transmitted. */ -+ prev_sb = 0; -+ iter_sb = TxIsocEPList[epid].sub ? phys_to_virt(TxIsocEPList[epid].sub) : 0; -+ } -+ -+ while (iter_sb && (iter_sb != urb_priv->last_sb)) { -+ iter_sb = iter_sb->next ? phys_to_virt(iter_sb->next) : 0; -+ } -+ -+ if (iter_sb) { -+ next_sb = iter_sb->next ? phys_to_virt(iter_sb->next) : 0; -+ } else { -+ /* This should only happen if the DMA has completed -+ processing the SB list for this EP while interrupts -+ are disabled. */ -+ isoc_dbg("Isoc urb not found, already sent?\n"); -+ next_sb = 0; -+ } -+ if (prev_sb) { -+ prev_sb->next = next_sb ? virt_to_phys(next_sb) : 0; -+ } else { -+ TxIsocEPList[epid].sub = next_sb ? virt_to_phys(next_sb) : 0; -+ } -+ } -+ } -+ -+ /* Free HC-private URB data*/ -+ urb_priv_free(hcd, urb); -+ -+ usb_release_bandwidth(urb->dev, urb, 0); -+ -+ /* Hand the URB from HCD to its USB device driver, using its completion -+ functions */ -+ usb_hcd_giveback_urb (hcd, urb); -+} -+#endif -+ -+static __u32 urb_num = 0; -+ -+/* allocate and initialize URB private data */ -+static int urb_priv_create(struct usb_hcd *hcd, struct urb *urb, int epid, -+ int mem_flags) { -+ struct crisv10_urb_priv *urb_priv; -+ -+ urb_priv = kmalloc(sizeof *urb_priv, mem_flags); -+ if (!urb_priv) -+ return -ENOMEM; -+ memset(urb_priv, 0, sizeof *urb_priv); -+ -+ urb_priv->epid = epid; -+ urb_priv->urb_state = NOT_STARTED; -+ -+ urb->hcpriv = urb_priv; -+ /* Assign URB a sequence number, and increment counter */ -+ urb_priv->urb_num = urb_num; -+ urb_num++; -+ return 0; -+} -+ -+/* free URB private data */ -+static void urb_priv_free(struct usb_hcd *hcd, struct urb *urb) { -+ int i; -+ struct crisv10_urb_priv *urb_priv = urb->hcpriv; -+ ASSERT(urb_priv != 0); -+ -+ /* Check it has any SBs linked that needs to be freed*/ -+ if(urb_priv->first_sb != NULL) { -+ struct USB_SB_Desc *next_sb, *first_sb, *last_sb; -+ int i = 0; -+ first_sb = urb_priv->first_sb; -+ last_sb = urb_priv->last_sb; -+ ASSERT(last_sb); -+ while(first_sb != last_sb) { -+ next_sb = (struct USB_SB_Desc *)phys_to_virt(first_sb->next); -+ kmem_cache_free(usb_desc_cache, first_sb); -+ first_sb = next_sb; -+ i++; -+ } -+ kmem_cache_free(usb_desc_cache, last_sb); -+ i++; -+ } -+ -+ /* Check if it has any EPs in its Intr pool that also needs to be freed */ -+ if(urb_priv->intr_ep_pool_length > 0) { -+ for(i = 0; i < urb_priv->intr_ep_pool_length; i++) { -+ kfree(urb_priv->intr_ep_pool[i]); -+ } -+ /* -+ tc_dbg("Freed %d EPs from URB:0x%x EP pool\n", -+ urb_priv->intr_ep_pool_length, (unsigned int)urb); -+ */ -+ } -+ -+ kfree(urb_priv); -+ urb->hcpriv = NULL; -+} -+ -+static int ep_priv_create(struct usb_host_endpoint *ep, int mem_flags) { -+ struct crisv10_ep_priv *ep_priv; -+ -+ ep_priv = kmalloc(sizeof *ep_priv, mem_flags); -+ if (!ep_priv) -+ return -ENOMEM; -+ memset(ep_priv, 0, sizeof *ep_priv); -+ -+ ep->hcpriv = ep_priv; -+ return 0; -+} -+ -+static void ep_priv_free(struct usb_host_endpoint *ep) { -+ struct crisv10_ep_priv *ep_priv = ep->hcpriv; -+ ASSERT(ep_priv); -+ kfree(ep_priv); -+ ep->hcpriv = NULL; -+} -+ -+/* EPID handling functions, managing EP-list in Etrax through wrappers */ -+/* ------------------------------------------------------------------- */ -+ -+/* Sets up a new EPID for an endpoint or returns existing if found */ -+//static int tc_setup_epid(struct usb_host_endpoint *ep, struct urb *urb, -+// int mem_flags) { -+static int tc_setup_epid(struct urb *urb, int mem_flags) -+{ -+ int epid; -+ char devnum, endpoint, out_traffic, slow; -+ int maxlen; -+ __u32 epid_data; -+ struct usb_host_endpoint *ep = urb->ep; -+ struct crisv10_ep_priv *ep_priv = ep->hcpriv; -+ -+ DBFENTER; -+ -+ /* Check if a valid epid already is setup for this endpoint */ -+ if(ep_priv != NULL) { -+ return ep_priv->epid; -+ } -+ -+ /* We must find and initiate a new epid for this urb. */ -+ epid = tc_allocate_epid(); -+ -+ if (epid == -1) { -+ /* Failed to allocate a new epid. */ -+ DBFEXIT; -+ return epid; -+ } -+ -+ /* We now have a new epid to use. Claim it. */ -+ epid_state[epid].inuse = 1; -+ -+ /* Init private data for new endpoint */ -+ if(ep_priv_create(ep, mem_flags) != 0) { -+ return -ENOMEM; -+ } -+ ep_priv = ep->hcpriv; -+ ep_priv->epid = epid; -+ -+ devnum = usb_pipedevice(urb->pipe); -+ endpoint = usb_pipeendpoint(urb->pipe); -+ slow = (urb->dev->speed == USB_SPEED_LOW); -+ maxlen = usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)); -+ -+ if (usb_pipetype(urb->pipe) == PIPE_CONTROL) { -+ /* We want both IN and OUT control traffic to be put on the same -+ EP/SB list. */ -+ out_traffic = 1; -+ } else { -+ out_traffic = usb_pipeout(urb->pipe); -+ } -+ -+ if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { -+ epid_data = IO_STATE(R_USB_EPT_DATA_ISO, valid, yes) | -+ /* FIXME: Change any to the actual port? */ -+ IO_STATE(R_USB_EPT_DATA_ISO, port, any) | -+ IO_FIELD(R_USB_EPT_DATA_ISO, max_len, maxlen) | -+ IO_FIELD(R_USB_EPT_DATA_ISO, ep, endpoint) | -+ IO_FIELD(R_USB_EPT_DATA_ISO, dev, devnum); -+ etrax_epid_iso_set(epid, epid_data); -+ } else { -+ epid_data = IO_STATE(R_USB_EPT_DATA, valid, yes) | -+ IO_FIELD(R_USB_EPT_DATA, low_speed, slow) | -+ /* FIXME: Change any to the actual port? */ -+ IO_STATE(R_USB_EPT_DATA, port, any) | -+ IO_FIELD(R_USB_EPT_DATA, max_len, maxlen) | -+ IO_FIELD(R_USB_EPT_DATA, ep, endpoint) | -+ IO_FIELD(R_USB_EPT_DATA, dev, devnum); -+ etrax_epid_set(epid, epid_data); -+ } -+ -+ epid_state[epid].out_traffic = out_traffic; -+ epid_state[epid].type = usb_pipetype(urb->pipe); -+ -+ tc_warn("Setting up ep:0x%x epid:%d (addr:%d endp:%d max_len:%d %s %s %s)\n", -+ (unsigned int)ep, epid, devnum, endpoint, maxlen, -+ str_type(urb->pipe), out_traffic ? "out" : "in", -+ slow ? "low" : "full"); -+ -+ /* Enable Isoc eof interrupt if we set up the first Isoc epid */ -+ if(usb_pipeisoc(urb->pipe)) { -+ isoc_epid_counter++; -+ if(isoc_epid_counter == 1) { -+ isoc_warn("Enabled Isoc eof interrupt\n"); -+ *R_USB_IRQ_MASK_SET |= IO_STATE(R_USB_IRQ_MASK_SET, iso_eof, set); -+ } -+ } -+ -+ DBFEXIT; -+ return epid; -+} -+ -+static void tc_free_epid(struct usb_host_endpoint *ep) { -+ unsigned long flags; -+ struct crisv10_ep_priv *ep_priv = ep->hcpriv; -+ int epid; -+ volatile int timeout = 10000; -+ -+ DBFENTER; -+ -+ if (ep_priv == NULL) { -+ tc_warn("Trying to free unused epid on ep:0x%x\n", (unsigned int)ep); -+ DBFEXIT; -+ return; -+ } -+ -+ epid = ep_priv->epid; -+ -+ /* Disable Isoc eof interrupt if we free the last Isoc epid */ -+ if(epid_isoc(epid)) { -+ ASSERT(isoc_epid_counter > 0); -+ isoc_epid_counter--; -+ if(isoc_epid_counter == 0) { -+ *R_USB_IRQ_MASK_SET &= ~IO_STATE(R_USB_IRQ_MASK_SET, iso_eof, set); -+ isoc_warn("Disabled Isoc eof interrupt\n"); -+ } -+ } -+ -+ /* Take lock manualy instead of in epid_x_x wrappers, -+ because we need to be polling here */ -+ spin_lock_irqsave(&etrax_epid_lock, flags); -+ -+ *R_USB_EPT_INDEX = IO_FIELD(R_USB_EPT_INDEX, value, epid); -+ nop(); -+ while((*R_USB_EPT_DATA & IO_MASK(R_USB_EPT_DATA, hold)) && -+ (timeout-- > 0)); -+ if(timeout == 0) { -+ warn("Timeout while waiting for epid:%d to drop hold\n", epid); -+ } -+ /* This will, among other things, set the valid field to 0. */ -+ *R_USB_EPT_DATA = 0; -+ spin_unlock_irqrestore(&etrax_epid_lock, flags); -+ -+ /* Free resource in software state info list */ -+ epid_state[epid].inuse = 0; -+ -+ /* Free private endpoint data */ -+ ep_priv_free(ep); -+ -+ DBFEXIT; -+} -+ -+static int tc_allocate_epid(void) { -+ int i; -+ DBFENTER; -+ for (i = 0; i < NBR_OF_EPIDS; i++) { -+ if (!epid_inuse(i)) { -+ DBFEXIT; -+ return i; -+ } -+ } -+ -+ tc_warn("Found no free epids\n"); -+ DBFEXIT; -+ return -1; -+} -+ -+ -+/* Wrappers around the list functions (include/linux/list.h). */ -+/* ---------------------------------------------------------- */ -+static inline int __urb_list_empty(int epid) { -+ int retval; -+ retval = list_empty(&urb_list[epid]); -+ return retval; -+} -+ -+/* Returns first urb for this epid, or NULL if list is empty. */ -+static inline struct urb *urb_list_first(int epid) { -+ unsigned long flags; -+ struct urb *first_urb = 0; -+ spin_lock_irqsave(&urb_list_lock, flags); -+ if (!__urb_list_empty(epid)) { -+ /* Get the first urb (i.e. head->next). */ -+ urb_entry_t *urb_entry = list_entry((&urb_list[epid])->next, urb_entry_t, list); -+ first_urb = urb_entry->urb; -+ } -+ spin_unlock_irqrestore(&urb_list_lock, flags); -+ return first_urb; -+} -+ -+/* Adds an urb_entry last in the list for this epid. */ -+static inline void urb_list_add(struct urb *urb, int epid, int mem_flags) { -+ unsigned long flags; -+ urb_entry_t *urb_entry = (urb_entry_t *)kmalloc(sizeof(urb_entry_t), mem_flags); -+ ASSERT(urb_entry); -+ -+ urb_entry->urb = urb; -+ spin_lock_irqsave(&urb_list_lock, flags); -+ list_add_tail(&urb_entry->list, &urb_list[epid]); -+ spin_unlock_irqrestore(&urb_list_lock, flags); -+} -+ -+/* Search through the list for an element that contains this urb. (The list -+ is expected to be short and the one we are about to delete will often be -+ the first in the list.) -+ Should be protected by spin_locks in calling function */ -+static inline urb_entry_t *__urb_list_entry(struct urb *urb, int epid) { -+ struct list_head *entry; -+ struct list_head *tmp; -+ urb_entry_t *urb_entry; -+ -+ list_for_each_safe(entry, tmp, &urb_list[epid]) { -+ urb_entry = list_entry(entry, urb_entry_t, list); -+ ASSERT(urb_entry); -+ ASSERT(urb_entry->urb); -+ -+ if (urb_entry->urb == urb) { -+ return urb_entry; -+ } -+ } -+ return 0; -+} -+ -+/* Same function as above but for global use. Protects list by spinlock */ -+static inline urb_entry_t *urb_list_entry(struct urb *urb, int epid) { -+ unsigned long flags; -+ urb_entry_t *urb_entry; -+ spin_lock_irqsave(&urb_list_lock, flags); -+ urb_entry = __urb_list_entry(urb, epid); -+ spin_unlock_irqrestore(&urb_list_lock, flags); -+ return (urb_entry); -+} -+ -+/* Delete an urb from the list. */ -+static inline void urb_list_del(struct urb *urb, int epid) { -+ unsigned long flags; -+ urb_entry_t *urb_entry; -+ -+ /* Delete entry and free. */ -+ spin_lock_irqsave(&urb_list_lock, flags); -+ urb_entry = __urb_list_entry(urb, epid); -+ ASSERT(urb_entry); -+ -+ list_del(&urb_entry->list); -+ spin_unlock_irqrestore(&urb_list_lock, flags); -+ kfree(urb_entry); -+} -+ -+/* Move an urb to the end of the list. */ -+static inline void urb_list_move_last(struct urb *urb, int epid) { -+ unsigned long flags; -+ urb_entry_t *urb_entry; -+ -+ spin_lock_irqsave(&urb_list_lock, flags); -+ urb_entry = __urb_list_entry(urb, epid); -+ ASSERT(urb_entry); -+ -+ list_del(&urb_entry->list); -+ list_add_tail(&urb_entry->list, &urb_list[epid]); -+ spin_unlock_irqrestore(&urb_list_lock, flags); -+} -+ -+/* Get the next urb in the list. */ -+static inline struct urb *urb_list_next(struct urb *urb, int epid) { -+ unsigned long flags; -+ urb_entry_t *urb_entry; -+ -+ spin_lock_irqsave(&urb_list_lock, flags); -+ urb_entry = __urb_list_entry(urb, epid); -+ ASSERT(urb_entry); -+ -+ if (urb_entry->list.next != &urb_list[epid]) { -+ struct list_head *elem = urb_entry->list.next; -+ urb_entry = list_entry(elem, urb_entry_t, list); -+ spin_unlock_irqrestore(&urb_list_lock, flags); -+ return urb_entry->urb; -+ } else { -+ spin_unlock_irqrestore(&urb_list_lock, flags); -+ return NULL; -+ } -+} -+ -+struct USB_EP_Desc* create_ep(int epid, struct USB_SB_Desc* sb_desc, -+ int mem_flags) { -+ struct USB_EP_Desc *ep_desc; -+ ep_desc = (struct USB_EP_Desc *) kmem_cache_alloc(usb_desc_cache, mem_flags); -+ if(ep_desc == NULL) -+ return NULL; -+ memset(ep_desc, 0, sizeof(struct USB_EP_Desc)); -+ -+ ep_desc->hw_len = 0; -+ ep_desc->command = (IO_FIELD(USB_EP_command, epid, epid) | -+ IO_STATE(USB_EP_command, enable, yes)); -+ if(sb_desc == NULL) { -+ ep_desc->sub = 0; -+ } else { -+ ep_desc->sub = virt_to_phys(sb_desc); -+ } -+ return ep_desc; -+} -+ -+#define TT_ZOUT 0 -+#define TT_IN 1 -+#define TT_OUT 2 -+#define TT_SETUP 3 -+ -+#define CMD_EOL IO_STATE(USB_SB_command, eol, yes) -+#define CMD_INTR IO_STATE(USB_SB_command, intr, yes) -+#define CMD_FULL IO_STATE(USB_SB_command, full, yes) -+ -+/* Allocation and setup of a generic SB. Used to create SETUP, OUT and ZOUT -+ SBs. Also used by create_sb_in() to avoid same allocation procedure at two -+ places */ -+struct USB_SB_Desc* create_sb(struct USB_SB_Desc* sb_prev, int tt, void* data, -+ int datalen, int mem_flags) { -+ struct USB_SB_Desc *sb_desc; -+ sb_desc = (struct USB_SB_Desc*)kmem_cache_alloc(usb_desc_cache, mem_flags); -+ if(sb_desc == NULL) -+ return NULL; -+ memset(sb_desc, 0, sizeof(struct USB_SB_Desc)); -+ -+ sb_desc->command = IO_FIELD(USB_SB_command, tt, tt) | -+ IO_STATE(USB_SB_command, eot, yes); -+ -+ sb_desc->sw_len = datalen; -+ if(data != NULL) { -+ sb_desc->buf = virt_to_phys(data); -+ } else { -+ sb_desc->buf = 0; -+ } -+ if(sb_prev != NULL) { -+ sb_prev->next = virt_to_phys(sb_desc); -+ } -+ return sb_desc; -+} -+ -+/* Creates a copy of an existing SB by allocation space for it and copy -+ settings */ -+struct USB_SB_Desc* create_sb_copy(struct USB_SB_Desc* sb_orig, int mem_flags) { -+ struct USB_SB_Desc *sb_desc; -+ sb_desc = (struct USB_SB_Desc*)kmem_cache_alloc(usb_desc_cache, mem_flags); -+ if(sb_desc == NULL) -+ return NULL; -+ -+ memcpy(sb_desc, sb_orig, sizeof(struct USB_SB_Desc)); -+ return sb_desc; -+} -+ -+/* A specific create_sb function for creation of in SBs. This is due to -+ that datalen in In SBs shows how many packets we are expecting. It also -+ sets up the rem field to show if how many bytes we expect in last packet -+ if it's not a full one */ -+struct USB_SB_Desc* create_sb_in(struct USB_SB_Desc* sb_prev, int datalen, -+ int maxlen, int mem_flags) { -+ struct USB_SB_Desc *sb_desc; -+ sb_desc = create_sb(sb_prev, TT_IN, NULL, -+ datalen ? (datalen - 1) / maxlen + 1 : 0, mem_flags); -+ if(sb_desc == NULL) -+ return NULL; -+ sb_desc->command |= IO_FIELD(USB_SB_command, rem, datalen % maxlen); -+ return sb_desc; -+} -+ -+void set_sb_cmds(struct USB_SB_Desc *sb_desc, __u16 flags) { -+ sb_desc->command |= flags; -+} -+ -+int create_sb_for_urb(struct urb *urb, int mem_flags) { -+ int is_out = !usb_pipein(urb->pipe); -+ int type = usb_pipetype(urb->pipe); -+ int maxlen = usb_maxpacket(urb->dev, urb->pipe, is_out); -+ int buf_len = urb->transfer_buffer_length; -+ void *buf = buf_len > 0 ? urb->transfer_buffer : NULL; -+ struct USB_SB_Desc *sb_desc = NULL; -+ -+ struct crisv10_urb_priv *urb_priv = (struct crisv10_urb_priv *)urb->hcpriv; -+ ASSERT(urb_priv != NULL); -+ -+ switch(type) { -+ case PIPE_CONTROL: -+ /* Setup stage */ -+ sb_desc = create_sb(NULL, TT_SETUP, urb->setup_packet, 8, mem_flags); -+ if(sb_desc == NULL) -+ return -ENOMEM; -+ set_sb_cmds(sb_desc, CMD_FULL); -+ -+ /* Attach first SB to URB */ -+ urb_priv->first_sb = sb_desc; -+ -+ if (is_out) { /* Out Control URB */ -+ /* If this Control OUT transfer has an optional data stage we add -+ an OUT token before the mandatory IN (status) token */ -+ if ((buf_len > 0) && buf) { -+ sb_desc = create_sb(sb_desc, TT_OUT, buf, buf_len, mem_flags); -+ if(sb_desc == NULL) -+ return -ENOMEM; -+ set_sb_cmds(sb_desc, CMD_FULL); -+ } -+ -+ /* Status stage */ -+ /* The data length has to be exactly 1. This is due to a requirement -+ of the USB specification that a host must be prepared to receive -+ data in the status phase */ -+ sb_desc = create_sb(sb_desc, TT_IN, NULL, 1, mem_flags); -+ if(sb_desc == NULL) -+ return -ENOMEM; -+ } else { /* In control URB */ -+ /* Data stage */ -+ sb_desc = create_sb_in(sb_desc, buf_len, maxlen, mem_flags); -+ if(sb_desc == NULL) -+ return -ENOMEM; -+ -+ /* Status stage */ -+ /* Read comment at zout_buffer declaration for an explanation to this. */ -+ sb_desc = create_sb(sb_desc, TT_ZOUT, &zout_buffer[0], 1, mem_flags); -+ if(sb_desc == NULL) -+ return -ENOMEM; -+ /* Set descriptor interrupt flag for in URBs so we can finish URB after -+ zout-packet has been sent */ -+ set_sb_cmds(sb_desc, CMD_INTR | CMD_FULL); -+ } -+ /* Set end-of-list flag in last SB */ -+ set_sb_cmds(sb_desc, CMD_EOL); -+ /* Attach last SB to URB */ -+ urb_priv->last_sb = sb_desc; -+ break; -+ -+ case PIPE_BULK: -+ if (is_out) { /* Out Bulk URB */ -+ sb_desc = create_sb(NULL, TT_OUT, buf, buf_len, mem_flags); -+ if(sb_desc == NULL) -+ return -ENOMEM; -+ /* The full field is set to yes, even if we don't actually check that -+ this is a full-length transfer (i.e., that transfer_buffer_length % -+ maxlen = 0). -+ Setting full prevents the USB controller from sending an empty packet -+ in that case. However, if URB_ZERO_PACKET was set we want that. */ -+ if (!(urb->transfer_flags & URB_ZERO_PACKET)) { -+ set_sb_cmds(sb_desc, CMD_FULL); -+ } -+ } else { /* In Bulk URB */ -+ sb_desc = create_sb_in(NULL, buf_len, maxlen, mem_flags); -+ if(sb_desc == NULL) -+ return -ENOMEM; -+ } -+ /* Set end-of-list flag for last SB */ -+ set_sb_cmds(sb_desc, CMD_EOL); -+ -+ /* Attach SB to URB */ -+ urb_priv->first_sb = sb_desc; -+ urb_priv->last_sb = sb_desc; -+ break; -+ -+ case PIPE_INTERRUPT: -+ if(is_out) { /* Out Intr URB */ -+ sb_desc = create_sb(NULL, TT_OUT, buf, buf_len, mem_flags); -+ if(sb_desc == NULL) -+ return -ENOMEM; -+ -+ /* The full field is set to yes, even if we don't actually check that -+ this is a full-length transfer (i.e., that transfer_buffer_length % -+ maxlen = 0). -+ Setting full prevents the USB controller from sending an empty packet -+ in that case. However, if URB_ZERO_PACKET was set we want that. */ -+ if (!(urb->transfer_flags & URB_ZERO_PACKET)) { -+ set_sb_cmds(sb_desc, CMD_FULL); -+ } -+ /* Only generate TX interrupt if it's a Out URB*/ -+ set_sb_cmds(sb_desc, CMD_INTR); -+ -+ } else { /* In Intr URB */ -+ sb_desc = create_sb_in(NULL, buf_len, maxlen, mem_flags); -+ if(sb_desc == NULL) -+ return -ENOMEM; -+ } -+ /* Set end-of-list flag for last SB */ -+ set_sb_cmds(sb_desc, CMD_EOL); -+ -+ /* Attach SB to URB */ -+ urb_priv->first_sb = sb_desc; -+ urb_priv->last_sb = sb_desc; -+ -+ break; -+ case PIPE_ISOCHRONOUS: -+ if(is_out) { /* Out Isoc URB */ -+ int i; -+ if(urb->number_of_packets == 0) { -+ tc_err("Can't create SBs for Isoc URB with zero packets\n"); -+ return -EPIPE; -+ } -+ /* Create one SB descriptor for each packet and link them together. */ -+ for(i = 0; i < urb->number_of_packets; i++) { -+ if (urb->iso_frame_desc[i].length > 0) { -+ -+ sb_desc = create_sb(sb_desc, TT_OUT, urb->transfer_buffer + -+ urb->iso_frame_desc[i].offset, -+ urb->iso_frame_desc[i].length, mem_flags); -+ if(sb_desc == NULL) -+ return -ENOMEM; -+ -+ /* Check if it's a full length packet */ -+ if (urb->iso_frame_desc[i].length == -+ usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe))) { -+ set_sb_cmds(sb_desc, CMD_FULL); -+ } -+ -+ } else { /* zero length packet */ -+ sb_desc = create_sb(sb_desc, TT_ZOUT, &zout_buffer[0], 1, mem_flags); -+ if(sb_desc == NULL) -+ return -ENOMEM; -+ set_sb_cmds(sb_desc, CMD_FULL); -+ } -+ /* Attach first SB descriptor to URB */ -+ if (i == 0) { -+ urb_priv->first_sb = sb_desc; -+ } -+ } -+ /* Set interrupt and end-of-list flags in last SB */ -+ set_sb_cmds(sb_desc, CMD_INTR | CMD_EOL); -+ /* Attach last SB descriptor to URB */ -+ urb_priv->last_sb = sb_desc; -+ tc_dbg("Created %d out SBs for Isoc URB:0x%x\n", -+ urb->number_of_packets, (unsigned int)urb); -+ } else { /* In Isoc URB */ -+ /* Actual number of packets is not relevant for periodic in traffic as -+ long as it is more than zero. Set to 1 always. */ -+ sb_desc = create_sb(sb_desc, TT_IN, NULL, 1, mem_flags); -+ if(sb_desc == NULL) -+ return -ENOMEM; -+ /* Set end-of-list flags for SB */ -+ set_sb_cmds(sb_desc, CMD_EOL); -+ -+ /* Attach SB to URB */ -+ urb_priv->first_sb = sb_desc; -+ urb_priv->last_sb = sb_desc; -+ } -+ break; -+ default: -+ tc_err("Unknown pipe-type\n"); -+ return -EPIPE; -+ break; -+ } -+ return 0; -+} -+ -+int init_intr_urb(struct urb *urb, int mem_flags) { -+ struct crisv10_urb_priv *urb_priv = (struct crisv10_urb_priv *)urb->hcpriv; -+ struct USB_EP_Desc* ep_desc; -+ int interval; -+ int i; -+ int ep_count; -+ -+ ASSERT(urb_priv != NULL); -+ ASSERT(usb_pipeint(urb->pipe)); -+ /* We can't support interval longer than amount of eof descriptors in -+ TxIntrEPList */ -+ if(urb->interval > MAX_INTR_INTERVAL) { -+ tc_err("Interrupt interval %dms too big (max: %dms)\n", urb->interval, -+ MAX_INTR_INTERVAL); -+ return -EINVAL; -+ } -+ -+ /* We assume that the SB descriptors already have been setup */ -+ ASSERT(urb_priv->first_sb != NULL); -+ -+ /* Round of the interval to 2^n, it is obvious that this code favours -+ smaller numbers, but that is actually a good thing */ -+ /* FIXME: The "rounding error" for larger intervals will be quite -+ large. For in traffic this shouldn't be a problem since it will only -+ mean that we "poll" more often. */ -+ interval = urb->interval; -+ for (i = 0; interval; i++) { -+ interval = interval >> 1; -+ } -+ urb_priv->interval = 1 << (i - 1); -+ -+ /* We can only have max interval for Out Interrupt due to that we can only -+ handle one linked in EP for a certain epid in the Intr descr array at the -+ time. The USB Controller in the Etrax 100LX continues to process Intr EPs -+ so we have no way of knowing which one that caused the actual transfer if -+ we have several linked in. */ -+ if(usb_pipeout(urb->pipe)) { -+ urb_priv->interval = MAX_INTR_INTERVAL; -+ } -+ -+ /* Calculate amount of EPs needed */ -+ ep_count = MAX_INTR_INTERVAL / urb_priv->interval; -+ -+ for(i = 0; i < ep_count; i++) { -+ ep_desc = create_ep(urb_priv->epid, urb_priv->first_sb, mem_flags); -+ if(ep_desc == NULL) { -+ /* Free any descriptors that we may have allocated before failure */ -+ while(i > 0) { -+ i--; -+ kfree(urb_priv->intr_ep_pool[i]); -+ } -+ return -ENOMEM; -+ } -+ urb_priv->intr_ep_pool[i] = ep_desc; -+ } -+ urb_priv->intr_ep_pool_length = ep_count; -+ return 0; -+} -+ -+/* DMA RX/TX functions */ -+/* ----------------------- */ -+ -+static void tc_dma_init_rx_list(void) { -+ int i; -+ -+ /* Setup descriptor list except last one */ -+ for (i = 0; i < (NBR_OF_RX_DESC - 1); i++) { -+ RxDescList[i].sw_len = RX_DESC_BUF_SIZE; -+ RxDescList[i].command = 0; -+ RxDescList[i].next = virt_to_phys(&RxDescList[i + 1]); -+ RxDescList[i].buf = virt_to_phys(RxBuf + (i * RX_DESC_BUF_SIZE)); -+ RxDescList[i].hw_len = 0; -+ RxDescList[i].status = 0; -+ -+ /* DMA IN cache bug. (struct etrax_dma_descr has the same layout as -+ USB_IN_Desc for the relevant fields.) */ -+ prepare_rx_descriptor((struct etrax_dma_descr*)&RxDescList[i]); -+ -+ } -+ /* Special handling of last descriptor */ -+ RxDescList[i].sw_len = RX_DESC_BUF_SIZE; -+ RxDescList[i].command = IO_STATE(USB_IN_command, eol, yes); -+ RxDescList[i].next = virt_to_phys(&RxDescList[0]); -+ RxDescList[i].buf = virt_to_phys(RxBuf + (i * RX_DESC_BUF_SIZE)); -+ RxDescList[i].hw_len = 0; -+ RxDescList[i].status = 0; -+ -+ /* Setup list pointers that show progress in list */ -+ myNextRxDesc = &RxDescList[0]; -+ myLastRxDesc = &RxDescList[NBR_OF_RX_DESC - 1]; -+ -+ flush_etrax_cache(); -+ /* Point DMA to first descriptor in list and start it */ -+ *R_DMA_CH9_FIRST = virt_to_phys(myNextRxDesc); -+ *R_DMA_CH9_CMD = IO_STATE(R_DMA_CH9_CMD, cmd, start); -+} -+ -+ -+static void tc_dma_init_tx_bulk_list(void) { -+ int i; -+ volatile struct USB_EP_Desc *epDescr; -+ -+ for (i = 0; i < (NBR_OF_EPIDS - 1); i++) { -+ epDescr = &(TxBulkEPList[i]); -+ CHECK_ALIGN(epDescr); -+ epDescr->hw_len = 0; -+ epDescr->command = IO_FIELD(USB_EP_command, epid, i); -+ epDescr->sub = 0; -+ epDescr->next = virt_to_phys(&TxBulkEPList[i + 1]); -+ -+ /* Initiate two EPs, disabled and with the eol flag set. No need for any -+ preserved epid. */ -+ -+ /* The first one has the intr flag set so we get an interrupt when the DMA -+ channel is about to become disabled. */ -+ CHECK_ALIGN(&TxBulkDummyEPList[i][0]); -+ TxBulkDummyEPList[i][0].hw_len = 0; -+ TxBulkDummyEPList[i][0].command = (IO_FIELD(USB_EP_command, epid, DUMMY_EPID) | -+ IO_STATE(USB_EP_command, eol, yes) | -+ IO_STATE(USB_EP_command, intr, yes)); -+ TxBulkDummyEPList[i][0].sub = 0; -+ TxBulkDummyEPList[i][0].next = virt_to_phys(&TxBulkDummyEPList[i][1]); -+ -+ /* The second one. */ -+ CHECK_ALIGN(&TxBulkDummyEPList[i][1]); -+ TxBulkDummyEPList[i][1].hw_len = 0; -+ TxBulkDummyEPList[i][1].command = (IO_FIELD(USB_EP_command, epid, DUMMY_EPID) | -+ IO_STATE(USB_EP_command, eol, yes)); -+ TxBulkDummyEPList[i][1].sub = 0; -+ /* The last dummy's next pointer is the same as the current EP's next pointer. */ -+ TxBulkDummyEPList[i][1].next = virt_to_phys(&TxBulkEPList[i + 1]); -+ } -+ -+ /* Special handling of last descr in list, make list circular */ -+ epDescr = &TxBulkEPList[i]; -+ CHECK_ALIGN(epDescr); -+ epDescr->hw_len = 0; -+ epDescr->command = IO_STATE(USB_EP_command, eol, yes) | -+ IO_FIELD(USB_EP_command, epid, i); -+ epDescr->sub = 0; -+ epDescr->next = virt_to_phys(&TxBulkEPList[0]); -+ -+ /* Init DMA sub-channel pointers to last item in each list */ -+ *R_DMA_CH8_SUB0_EP = virt_to_phys(&TxBulkEPList[i]); -+ /* No point in starting the bulk channel yet. -+ *R_DMA_CH8_SUB0_CMD = IO_STATE(R_DMA_CH8_SUB0_CMD, cmd, start); */ -+} -+ -+static void tc_dma_init_tx_ctrl_list(void) { -+ int i; -+ volatile struct USB_EP_Desc *epDescr; -+ -+ for (i = 0; i < (NBR_OF_EPIDS - 1); i++) { -+ epDescr = &(TxCtrlEPList[i]); -+ CHECK_ALIGN(epDescr); -+ epDescr->hw_len = 0; -+ epDescr->command = IO_FIELD(USB_EP_command, epid, i); -+ epDescr->sub = 0; -+ epDescr->next = virt_to_phys(&TxCtrlEPList[i + 1]); -+ } -+ /* Special handling of last descr in list, make list circular */ -+ epDescr = &TxCtrlEPList[i]; -+ CHECK_ALIGN(epDescr); -+ epDescr->hw_len = 0; -+ epDescr->command = IO_STATE(USB_EP_command, eol, yes) | -+ IO_FIELD(USB_EP_command, epid, i); -+ epDescr->sub = 0; -+ epDescr->next = virt_to_phys(&TxCtrlEPList[0]); -+ -+ /* Init DMA sub-channel pointers to last item in each list */ -+ *R_DMA_CH8_SUB1_EP = virt_to_phys(&TxCtrlEPList[i]); -+ /* No point in starting the ctrl channel yet. -+ *R_DMA_CH8_SUB1_CMD = IO_STATE(R_DMA_CH8_SUB0_CMD, cmd, start); */ -+} -+ -+ -+static void tc_dma_init_tx_intr_list(void) { -+ int i; -+ -+ TxIntrSB_zout.sw_len = 1; -+ TxIntrSB_zout.next = 0; -+ TxIntrSB_zout.buf = virt_to_phys(&zout_buffer[0]); -+ TxIntrSB_zout.command = (IO_FIELD(USB_SB_command, rem, 0) | -+ IO_STATE(USB_SB_command, tt, zout) | -+ IO_STATE(USB_SB_command, full, yes) | -+ IO_STATE(USB_SB_command, eot, yes) | -+ IO_STATE(USB_SB_command, eol, yes)); -+ -+ for (i = 0; i < (MAX_INTR_INTERVAL - 1); i++) { -+ CHECK_ALIGN(&TxIntrEPList[i]); -+ TxIntrEPList[i].hw_len = 0; -+ TxIntrEPList[i].command = -+ (IO_STATE(USB_EP_command, eof, yes) | -+ IO_STATE(USB_EP_command, enable, yes) | -+ IO_FIELD(USB_EP_command, epid, INVALID_EPID)); -+ TxIntrEPList[i].sub = virt_to_phys(&TxIntrSB_zout); -+ TxIntrEPList[i].next = virt_to_phys(&TxIntrEPList[i + 1]); -+ } -+ -+ /* Special handling of last descr in list, make list circular */ -+ CHECK_ALIGN(&TxIntrEPList[i]); -+ TxIntrEPList[i].hw_len = 0; -+ TxIntrEPList[i].command = -+ (IO_STATE(USB_EP_command, eof, yes) | -+ IO_STATE(USB_EP_command, eol, yes) | -+ IO_STATE(USB_EP_command, enable, yes) | -+ IO_FIELD(USB_EP_command, epid, INVALID_EPID)); -+ TxIntrEPList[i].sub = virt_to_phys(&TxIntrSB_zout); -+ TxIntrEPList[i].next = virt_to_phys(&TxIntrEPList[0]); -+ -+ intr_dbg("Initiated Intr EP descriptor list\n"); -+ -+ -+ /* Connect DMA 8 sub-channel 2 to first in list */ -+ *R_DMA_CH8_SUB2_EP = virt_to_phys(&TxIntrEPList[0]); -+} -+ -+static void tc_dma_init_tx_isoc_list(void) { -+ int i; -+ -+ DBFENTER; -+ -+ /* Read comment at zout_buffer declaration for an explanation to this. */ -+ TxIsocSB_zout.sw_len = 1; -+ TxIsocSB_zout.next = 0; -+ TxIsocSB_zout.buf = virt_to_phys(&zout_buffer[0]); -+ TxIsocSB_zout.command = (IO_FIELD(USB_SB_command, rem, 0) | -+ IO_STATE(USB_SB_command, tt, zout) | -+ IO_STATE(USB_SB_command, full, yes) | -+ IO_STATE(USB_SB_command, eot, yes) | -+ IO_STATE(USB_SB_command, eol, yes)); -+ -+ /* The last isochronous EP descriptor is a dummy. */ -+ for (i = 0; i < (NBR_OF_EPIDS - 1); i++) { -+ CHECK_ALIGN(&TxIsocEPList[i]); -+ TxIsocEPList[i].hw_len = 0; -+ TxIsocEPList[i].command = IO_FIELD(USB_EP_command, epid, i); -+ TxIsocEPList[i].sub = 0; -+ TxIsocEPList[i].next = virt_to_phys(&TxIsocEPList[i + 1]); -+ } -+ -+ CHECK_ALIGN(&TxIsocEPList[i]); -+ TxIsocEPList[i].hw_len = 0; -+ -+ /* Must enable the last EP descr to get eof interrupt. */ -+ TxIsocEPList[i].command = (IO_STATE(USB_EP_command, enable, yes) | -+ IO_STATE(USB_EP_command, eof, yes) | -+ IO_STATE(USB_EP_command, eol, yes) | -+ IO_FIELD(USB_EP_command, epid, INVALID_EPID)); -+ TxIsocEPList[i].sub = virt_to_phys(&TxIsocSB_zout); -+ TxIsocEPList[i].next = virt_to_phys(&TxIsocEPList[0]); -+ -+ *R_DMA_CH8_SUB3_EP = virt_to_phys(&TxIsocEPList[0]); -+ *R_DMA_CH8_SUB3_CMD = IO_STATE(R_DMA_CH8_SUB3_CMD, cmd, start); -+} -+ -+static int tc_dma_init(struct usb_hcd *hcd) { -+ tc_dma_init_rx_list(); -+ tc_dma_init_tx_bulk_list(); -+ tc_dma_init_tx_ctrl_list(); -+ tc_dma_init_tx_intr_list(); -+ tc_dma_init_tx_isoc_list(); -+ -+ if (cris_request_dma(USB_TX_DMA_NBR, -+ "ETRAX 100LX built-in USB (Tx)", -+ DMA_VERBOSE_ON_ERROR, -+ dma_usb)) { -+ err("Could not allocate DMA ch 8 for USB"); -+ return -EBUSY; -+ } -+ -+ if (cris_request_dma(USB_RX_DMA_NBR, -+ "ETRAX 100LX built-in USB (Rx)", -+ DMA_VERBOSE_ON_ERROR, -+ dma_usb)) { -+ err("Could not allocate DMA ch 9 for USB"); -+ return -EBUSY; -+ } -+ -+ *R_IRQ_MASK2_SET = -+ /* Note that these interrupts are not used. */ -+ IO_STATE(R_IRQ_MASK2_SET, dma8_sub0_descr, set) | -+ /* Sub channel 1 (ctrl) descr. interrupts are used. */ -+ IO_STATE(R_IRQ_MASK2_SET, dma8_sub1_descr, set) | -+ IO_STATE(R_IRQ_MASK2_SET, dma8_sub2_descr, set) | -+ /* Sub channel 3 (isoc) descr. interrupts are used. */ -+ IO_STATE(R_IRQ_MASK2_SET, dma8_sub3_descr, set); -+ -+ /* Note that the dma9_descr interrupt is not used. */ -+ *R_IRQ_MASK2_SET = -+ IO_STATE(R_IRQ_MASK2_SET, dma9_eop, set) | -+ IO_STATE(R_IRQ_MASK2_SET, dma9_descr, set); -+ -+ if (request_irq(ETRAX_USB_RX_IRQ, tc_dma_rx_interrupt, 0, -+ "ETRAX 100LX built-in USB (Rx)", hcd)) { -+ err("Could not allocate IRQ %d for USB", ETRAX_USB_RX_IRQ); -+ return -EBUSY; -+ } -+ -+ if (request_irq(ETRAX_USB_TX_IRQ, tc_dma_tx_interrupt, 0, -+ "ETRAX 100LX built-in USB (Tx)", hcd)) { -+ err("Could not allocate IRQ %d for USB", ETRAX_USB_TX_IRQ); -+ return -EBUSY; -+ } -+ -+ return 0; -+} -+ -+static void tc_dma_destroy(void) { -+ free_irq(ETRAX_USB_RX_IRQ, NULL); -+ free_irq(ETRAX_USB_TX_IRQ, NULL); -+ -+ cris_free_dma(USB_TX_DMA_NBR, "ETRAX 100LX built-in USB (Tx)"); -+ cris_free_dma(USB_RX_DMA_NBR, "ETRAX 100LX built-in USB (Rx)"); -+ -+} -+ -+static void tc_dma_link_intr_urb(struct urb *urb); -+ -+/* Handle processing of Bulk, Ctrl and Intr queues */ -+static void tc_dma_process_queue(int epid) { -+ struct urb *urb; -+ struct crisv10_urb_priv *urb_priv = urb->hcpriv; -+ unsigned long flags; -+ char toggle; -+ -+ if(epid_state[epid].disabled) { -+ /* Don't process any URBs on a disabled endpoint */ -+ return; -+ } -+ -+ /* Do not disturb us while fiddling with EPs and epids */ -+ local_irq_save(flags); -+ -+ /* For bulk, Ctrl and Intr can we only have one URB active at a time for -+ a specific EP. */ -+ if(activeUrbList[epid] != NULL) { -+ /* An URB is already active on EP, skip checking queue */ -+ local_irq_restore(flags); -+ return; -+ } -+ -+ urb = urb_list_first(epid); -+ if(urb == NULL) { -+ /* No URB waiting in EP queue. Nothing do to */ -+ local_irq_restore(flags); -+ return; -+ } -+ -+ urb_priv = urb->hcpriv; -+ ASSERT(urb_priv != NULL); -+ ASSERT(urb_priv->urb_state == NOT_STARTED); -+ ASSERT(!usb_pipeisoc(urb->pipe)); -+ -+ /* Remove this URB from the queue and move it to active */ -+ activeUrbList[epid] = urb; -+ urb_list_del(urb, epid); -+ -+ urb_priv->urb_state = STARTED; -+ -+ /* Reset error counters (regardless of which direction this traffic is). */ -+ etrax_epid_clear_error(epid); -+ -+ /* Special handling of Intr EP lists */ -+ if(usb_pipeint(urb->pipe)) { -+ tc_dma_link_intr_urb(urb); -+ local_irq_restore(flags); -+ return; -+ } -+ -+ /* Software must preset the toggle bits for Bulk and Ctrl */ -+ if(usb_pipecontrol(urb->pipe)) { -+ /* Toggle bits are initialized only during setup transaction in a -+ CTRL transfer */ -+ etrax_epid_set_toggle(epid, 0, 0); -+ etrax_epid_set_toggle(epid, 1, 0); -+ } else { -+ toggle = usb_gettoggle(urb->dev, usb_pipeendpoint(urb->pipe), -+ usb_pipeout(urb->pipe)); -+ etrax_epid_set_toggle(epid, usb_pipeout(urb->pipe), toggle); -+ } -+ -+ tc_dbg("Added SBs from (URB:0x%x %s %s) to epid %d: %s\n", -+ (unsigned int)urb, str_dir(urb->pipe), str_type(urb->pipe), epid, -+ sblist_to_str(urb_priv->first_sb)); -+ -+ /* We start the DMA sub channel without checking if it's running or not, -+ because: -+ 1) If it's already running, issuing the start command is a nop. -+ 2) We avoid a test-and-set race condition. */ -+ switch(usb_pipetype(urb->pipe)) { -+ case PIPE_BULK: -+ /* Assert that the EP descriptor is disabled. */ -+ ASSERT(!(TxBulkEPList[epid].command & IO_MASK(USB_EP_command, enable))); -+ -+ /* Set up and enable the EP descriptor. */ -+ TxBulkEPList[epid].sub = virt_to_phys(urb_priv->first_sb); -+ TxBulkEPList[epid].hw_len = 0; -+ TxBulkEPList[epid].command |= IO_STATE(USB_EP_command, enable, yes); -+ -+ /* Check if the dummy list is already with us (if several urbs were queued). */ -+ if (usb_pipein(urb->pipe) && (TxBulkEPList[epid].next != virt_to_phys(&TxBulkDummyEPList[epid][0]))) { -+ tc_dbg("Inviting dummy list to the party for urb 0x%lx, epid %d", -+ (unsigned long)urb, epid); -+ -+ /* We don't need to check if the DMA is at this EP or not before changing the -+ next pointer, since we will do it in one 32-bit write (EP descriptors are -+ 32-bit aligned). */ -+ TxBulkEPList[epid].next = virt_to_phys(&TxBulkDummyEPList[epid][0]); -+ } -+ -+ restart_dma8_sub0(); -+ -+ /* Update/restart the bulk start timer since we just started the channel.*/ -+ mod_timer(&bulk_start_timer, jiffies + BULK_START_TIMER_INTERVAL); -+ /* Update/restart the bulk eot timer since we just inserted traffic. */ -+ mod_timer(&bulk_eot_timer, jiffies + BULK_EOT_TIMER_INTERVAL); -+ break; -+ case PIPE_CONTROL: -+ /* Assert that the EP descriptor is disabled. */ -+ ASSERT(!(TxCtrlEPList[epid].command & IO_MASK(USB_EP_command, enable))); -+ -+ /* Set up and enable the EP descriptor. */ -+ TxCtrlEPList[epid].sub = virt_to_phys(urb_priv->first_sb); -+ TxCtrlEPList[epid].hw_len = 0; -+ TxCtrlEPList[epid].command |= IO_STATE(USB_EP_command, enable, yes); -+ -+ *R_DMA_CH8_SUB1_CMD = IO_STATE(R_DMA_CH8_SUB1_CMD, cmd, start); -+ break; -+ } -+ local_irq_restore(flags); -+} -+ -+static void tc_dma_link_intr_urb(struct urb *urb) { -+ struct crisv10_urb_priv *urb_priv = urb->hcpriv; -+ volatile struct USB_EP_Desc *tmp_ep; -+ struct USB_EP_Desc *ep_desc; -+ int i = 0, epid; -+ int pool_idx = 0; -+ -+ ASSERT(urb_priv != NULL); -+ epid = urb_priv->epid; -+ ASSERT(urb_priv->interval > 0); -+ ASSERT(urb_priv->intr_ep_pool_length > 0); -+ -+ tmp_ep = &TxIntrEPList[0]; -+ -+ /* Only insert one EP descriptor in list for Out Intr URBs. -+ We can only handle Out Intr with interval of 128ms because -+ it's not possible to insert several Out Intr EPs because they -+ are not consumed by the DMA. */ -+ if(usb_pipeout(urb->pipe)) { -+ ep_desc = urb_priv->intr_ep_pool[0]; -+ ASSERT(ep_desc); -+ ep_desc->next = tmp_ep->next; -+ tmp_ep->next = virt_to_phys(ep_desc); -+ i++; -+ } else { -+ /* Loop through Intr EP descriptor list and insert EP for URB at -+ specified interval */ -+ do { -+ /* Each EP descriptor with eof flag sat signals a new frame */ -+ if (tmp_ep->command & IO_MASK(USB_EP_command, eof)) { -+ /* Insert a EP from URBs EP pool at correct interval */ -+ if ((i % urb_priv->interval) == 0) { -+ ep_desc = urb_priv->intr_ep_pool[pool_idx]; -+ ASSERT(ep_desc); -+ ep_desc->next = tmp_ep->next; -+ tmp_ep->next = virt_to_phys(ep_desc); -+ pool_idx++; -+ ASSERT(pool_idx <= urb_priv->intr_ep_pool_length); -+ } -+ i++; -+ } -+ tmp_ep = (struct USB_EP_Desc *)phys_to_virt(tmp_ep->next); -+ } while(tmp_ep != &TxIntrEPList[0]); -+ } -+ -+ intr_dbg("Added SBs to intr epid %d: %s interval:%d (%d EP)\n", epid, -+ sblist_to_str(urb_priv->first_sb), urb_priv->interval, pool_idx); -+ -+ /* We start the DMA sub channel without checking if it's running or not, -+ because: -+ 1) If it's already running, issuing the start command is a nop. -+ 2) We avoid a test-and-set race condition. */ -+ *R_DMA_CH8_SUB2_CMD = IO_STATE(R_DMA_CH8_SUB2_CMD, cmd, start); -+} -+ -+ /* hinko ignore usb_pipeisoc */ -+#if 0 -+static void tc_dma_process_isoc_urb(struct urb *urb) { -+ unsigned long flags; -+ struct crisv10_urb_priv *urb_priv = urb->hcpriv; -+ int epid; -+ -+ /* Do not disturb us while fiddling with EPs and epids */ -+ local_irq_save(flags); -+ -+ ASSERT(urb_priv); -+ ASSERT(urb_priv->first_sb); -+ epid = urb_priv->epid; -+ -+ if(activeUrbList[epid] == NULL) { -+ /* EP is idle, so make this URB active */ -+ activeUrbList[epid] = urb; -+ urb_list_del(urb, epid); -+ ASSERT(TxIsocEPList[epid].sub == 0); -+ ASSERT(!(TxIsocEPList[epid].command & -+ IO_STATE(USB_EP_command, enable, yes))); -+ -+ /* Differentiate between In and Out Isoc. Because In SBs are not consumed*/ -+ if(usb_pipein(urb->pipe)) { -+ /* Each EP for In Isoc will have only one SB descriptor, setup when -+ submitting the first active urb. We do it here by copying from URBs -+ pre-allocated SB. */ -+ memcpy((void *)&(TxIsocSBList[epid]), urb_priv->first_sb, -+ sizeof(TxIsocSBList[epid])); -+ TxIsocEPList[epid].hw_len = 0; -+ TxIsocEPList[epid].sub = virt_to_phys(&(TxIsocSBList[epid])); -+ } else { -+ /* For Out Isoc we attach the pre-allocated list of SBs for the URB */ -+ TxIsocEPList[epid].hw_len = 0; -+ TxIsocEPList[epid].sub = virt_to_phys(urb_priv->first_sb); -+ -+ isoc_dbg("Attached first URB:0x%x[%d] to epid:%d first_sb:0x%x" -+ " last_sb::0x%x\n", -+ (unsigned int)urb, urb_priv->urb_num, epid, -+ (unsigned int)(urb_priv->first_sb), -+ (unsigned int)(urb_priv->last_sb)); -+ } -+ -+ if (urb->transfer_flags & URB_ISO_ASAP) { -+ /* The isoc transfer should be started as soon as possible. The -+ start_frame field is a return value if URB_ISO_ASAP was set. Comparing -+ R_USB_FM_NUMBER with a USB Chief trace shows that the first isoc IN -+ token is sent 2 frames later. I'm not sure how this affects usage of -+ the start_frame field by the device driver, or how it affects things -+ when USB_ISO_ASAP is not set, so therefore there's no compensation for -+ the 2 frame "lag" here. */ -+ urb->start_frame = (*R_USB_FM_NUMBER & 0x7ff); -+ TxIsocEPList[epid].command |= IO_STATE(USB_EP_command, enable, yes); -+ urb_priv->urb_state = STARTED; -+ isoc_dbg("URB_ISO_ASAP set, urb->start_frame set to %d\n", -+ urb->start_frame); -+ } else { -+ /* Not started yet. */ -+ urb_priv->urb_state = NOT_STARTED; -+ isoc_warn("urb_priv->urb_state set to NOT_STARTED for URB:0x%x\n", -+ (unsigned int)urb); -+ } -+ -+ } else { -+ /* An URB is already active on the EP. Leave URB in queue and let -+ finish_isoc_urb process it after current active URB */ -+ ASSERT(TxIsocEPList[epid].sub != 0); -+ -+ if(usb_pipein(urb->pipe)) { -+ /* Because there already is a active In URB on this epid we do nothing -+ and the finish_isoc_urb() function will handle switching to next URB*/ -+ -+ } else { /* For Out Isoc, insert new URBs traffic last in SB-list. */ -+ struct USB_SB_Desc *temp_sb_desc; -+ -+ /* Set state STARTED to all Out Isoc URBs added to SB list because we -+ don't know how many of them that are finished before descr interrupt*/ -+ urb_priv->urb_state = STARTED; -+ -+ /* Find end of current SB list by looking for SB with eol flag sat */ -+ temp_sb_desc = phys_to_virt(TxIsocEPList[epid].sub); -+ while ((temp_sb_desc->command & IO_MASK(USB_SB_command, eol)) != -+ IO_STATE(USB_SB_command, eol, yes)) { -+ ASSERT(temp_sb_desc->next); -+ temp_sb_desc = phys_to_virt(temp_sb_desc->next); -+ } -+ -+ isoc_dbg("Appended URB:0x%x[%d] (first:0x%x last:0x%x) to epid:%d" -+ " sub:0x%x eol:0x%x\n", -+ (unsigned int)urb, urb_priv->urb_num, -+ (unsigned int)(urb_priv->first_sb), -+ (unsigned int)(urb_priv->last_sb), epid, -+ (unsigned int)phys_to_virt(TxIsocEPList[epid].sub), -+ (unsigned int)temp_sb_desc); -+ -+ /* Next pointer must be set before eol is removed. */ -+ temp_sb_desc->next = virt_to_phys(urb_priv->first_sb); -+ /* Clear the previous end of list flag since there is a new in the -+ added SB descriptor list. */ -+ temp_sb_desc->command &= ~IO_MASK(USB_SB_command, eol); -+ -+ if (!(TxIsocEPList[epid].command & IO_MASK(USB_EP_command, enable))) { -+ __u32 epid_data; -+ /* 8.8.5 in Designer's Reference says we should check for and correct -+ any errors in the EP here. That should not be necessary if -+ epid_attn is handled correctly, so we assume all is ok. */ -+ epid_data = etrax_epid_iso_get(epid); -+ if (IO_EXTRACT(R_USB_EPT_DATA, error_code, epid_data) != -+ IO_STATE_VALUE(R_USB_EPT_DATA, error_code, no_error)) { -+ isoc_err("Disabled Isoc EP with error:%d on epid:%d when appending" -+ " URB:0x%x[%d]\n", -+ IO_EXTRACT(R_USB_EPT_DATA, error_code, epid_data), epid, -+ (unsigned int)urb, urb_priv->urb_num); -+ } -+ -+ /* The SB list was exhausted. */ -+ if (virt_to_phys(urb_priv->last_sb) != TxIsocEPList[epid].sub) { -+ /* The new sublist did not get processed before the EP was -+ disabled. Setup the EP again. */ -+ -+ if(virt_to_phys(temp_sb_desc) == TxIsocEPList[epid].sub) { -+ isoc_dbg("EP for epid:%d stoped at SB:0x%x before newly inserted" -+ ", restarting from this URBs SB:0x%x\n", -+ epid, (unsigned int)temp_sb_desc, -+ (unsigned int)(urb_priv->first_sb)); -+ TxIsocEPList[epid].hw_len = 0; -+ TxIsocEPList[epid].sub = virt_to_phys(urb_priv->first_sb); -+ urb->start_frame = (*R_USB_FM_NUMBER & 0x7ff); -+ /* Enable the EP again so data gets processed this time */ -+ TxIsocEPList[epid].command |= -+ IO_STATE(USB_EP_command, enable, yes); -+ -+ } else { -+ /* The EP has been disabled but not at end this URB (god knows -+ where). This should generate an epid_attn so we should not be -+ here */ -+ isoc_warn("EP was disabled on sb:0x%x before SB list for" -+ " URB:0x%x[%d] got processed\n", -+ (unsigned int)phys_to_virt(TxIsocEPList[epid].sub), -+ (unsigned int)urb, urb_priv->urb_num); -+ } -+ } else { -+ /* This might happend if we are slow on this function and isn't -+ an error. */ -+ isoc_dbg("EP was disabled and finished with SBs from appended" -+ " URB:0x%x[%d]\n", (unsigned int)urb, urb_priv->urb_num); -+ } -+ } -+ } -+ } -+ -+ /* Start the DMA sub channel */ -+ *R_DMA_CH8_SUB3_CMD = IO_STATE(R_DMA_CH8_SUB3_CMD, cmd, start); -+ -+ local_irq_restore(flags); -+} -+#endif -+ -+static void tc_dma_unlink_intr_urb(struct urb *urb) { -+ struct crisv10_urb_priv *urb_priv = urb->hcpriv; -+ volatile struct USB_EP_Desc *first_ep; /* First EP in the list. */ -+ volatile struct USB_EP_Desc *curr_ep; /* Current EP, the iterator. */ -+ volatile struct USB_EP_Desc *next_ep; /* The EP after current. */ -+ volatile struct USB_EP_Desc *unlink_ep; /* The one we should remove from -+ the list. */ -+ int count = 0; -+ volatile int timeout = 10000; -+ int epid; -+ -+ /* Read 8.8.4 in Designer's Reference, "Removing an EP Descriptor from the -+ List". */ -+ ASSERT(urb_priv); -+ ASSERT(urb_priv->intr_ep_pool_length > 0); -+ epid = urb_priv->epid; -+ -+ /* First disable all Intr EPs belonging to epid for this URB */ -+ first_ep = &TxIntrEPList[0]; -+ curr_ep = first_ep; -+ do { -+ next_ep = (struct USB_EP_Desc *)phys_to_virt(curr_ep->next); -+ if (IO_EXTRACT(USB_EP_command, epid, next_ep->command) == epid) { -+ /* Disable EP */ -+ next_ep->command &= ~IO_MASK(USB_EP_command, enable); -+ } -+ curr_ep = phys_to_virt(curr_ep->next); -+ } while (curr_ep != first_ep); -+ -+ -+ /* Now unlink all EPs belonging to this epid from Descr list */ -+ first_ep = &TxIntrEPList[0]; -+ curr_ep = first_ep; -+ do { -+ next_ep = (struct USB_EP_Desc *)phys_to_virt(curr_ep->next); -+ if (IO_EXTRACT(USB_EP_command, epid, next_ep->command) == epid) { -+ /* This is the one we should unlink. */ -+ unlink_ep = next_ep; -+ -+ /* Actually unlink the EP from the DMA list. */ -+ curr_ep->next = unlink_ep->next; -+ -+ /* Wait until the DMA is no longer at this descriptor. */ -+ while((*R_DMA_CH8_SUB2_EP == virt_to_phys(unlink_ep)) && -+ (timeout-- > 0)); -+ if(timeout == 0) { -+ warn("Timeout while waiting for DMA-TX-Intr to leave unlink EP\n"); -+ } -+ -+ count++; -+ } -+ curr_ep = phys_to_virt(curr_ep->next); -+ } while (curr_ep != first_ep); -+ -+ if(count != urb_priv->intr_ep_pool_length) { -+ intr_warn("Unlinked %d of %d Intr EPs for URB:0x%x[%d]\n", count, -+ urb_priv->intr_ep_pool_length, (unsigned int)urb, -+ urb_priv->urb_num); -+ } else { -+ intr_dbg("Unlinked %d of %d interrupt EPs for URB:0x%x\n", count, -+ urb_priv->intr_ep_pool_length, (unsigned int)urb); -+ } -+} -+ -+static void check_finished_bulk_tx_epids(struct usb_hcd *hcd, -+ int timer) { -+ unsigned long flags; -+ int epid; -+ struct urb *urb; -+ struct crisv10_urb_priv * urb_priv; -+ __u32 epid_data; -+ -+ /* Protect TxEPList */ -+ local_irq_save(flags); -+ -+ for (epid = 0; epid < NBR_OF_EPIDS; epid++) { -+ /* A finished EP descriptor is disabled and has a valid sub pointer */ -+ if (!(TxBulkEPList[epid].command & IO_MASK(USB_EP_command, enable)) && -+ (TxBulkEPList[epid].sub != 0)) { -+ -+ /* Get the active URB for this epid */ -+ urb = activeUrbList[epid]; -+ /* Sanity checks */ -+ ASSERT(urb); -+ urb_priv = (struct crisv10_urb_priv *)urb->hcpriv; -+ ASSERT(urb_priv); -+ -+ /* Only handle finished out Bulk EPs here, -+ and let RX interrupt take care of the rest */ -+ if(!epid_out_traffic(epid)) { -+ continue; -+ } -+ -+ if(timer) { -+ tc_warn("Found finished %s Bulk epid:%d URB:0x%x[%d] from timeout\n", -+ epid_out_traffic(epid) ? "Out" : "In", epid, (unsigned int)urb, -+ urb_priv->urb_num); -+ } else { -+ tc_dbg("Found finished %s Bulk epid:%d URB:0x%x[%d] from interrupt\n", -+ epid_out_traffic(epid) ? "Out" : "In", epid, (unsigned int)urb, -+ urb_priv->urb_num); -+ } -+ -+ if(urb_priv->urb_state == UNLINK) { -+ /* This Bulk URB is requested to be unlinked, that means that the EP -+ has been disabled and we might not have sent all data */ -+ tc_finish_urb(hcd, urb, urb->status); -+ continue; -+ } -+ -+ ASSERT(urb_priv->urb_state == STARTED); -+ if (phys_to_virt(TxBulkEPList[epid].sub) != urb_priv->last_sb) { -+ tc_err("Endpoint got disabled before reaching last sb\n"); -+ } -+ -+ epid_data = etrax_epid_get(epid); -+ if (IO_EXTRACT(R_USB_EPT_DATA, error_code, epid_data) == -+ IO_STATE_VALUE(R_USB_EPT_DATA, error_code, no_error)) { -+ /* This means that the endpoint has no error, is disabled -+ and had inserted traffic, i.e. transfer successfully completed. */ -+ tc_finish_urb(hcd, urb, 0); -+ } else { -+ /* Shouldn't happen. We expect errors to be caught by epid -+ attention. */ -+ tc_err("Found disabled bulk EP desc (epid:%d error:%d)\n", -+ epid, IO_EXTRACT(R_USB_EPT_DATA, error_code, epid_data)); -+ } -+ } else { -+ tc_dbg("Ignoring In Bulk epid:%d, let RX interrupt handle it\n", epid); -+ } -+ } -+ -+ local_irq_restore(flags); -+} -+ -+static void check_finished_ctrl_tx_epids(struct usb_hcd *hcd) { -+ unsigned long flags; -+ int epid; -+ struct urb *urb; -+ struct crisv10_urb_priv * urb_priv; -+ __u32 epid_data; -+ -+ /* Protect TxEPList */ -+ local_irq_save(flags); -+ -+ for (epid = 0; epid < NBR_OF_EPIDS; epid++) { -+ if(epid == DUMMY_EPID) -+ continue; -+ -+ /* A finished EP descriptor is disabled and has a valid sub pointer */ -+ if (!(TxCtrlEPList[epid].command & IO_MASK(USB_EP_command, enable)) && -+ (TxCtrlEPList[epid].sub != 0)) { -+ -+ /* Get the active URB for this epid */ -+ urb = activeUrbList[epid]; -+ -+ if(urb == NULL) { -+ tc_warn("Found finished Ctrl epid:%d with no active URB\n", epid); -+ continue; -+ } -+ -+ /* Sanity checks */ -+ ASSERT(usb_pipein(urb->pipe)); -+ urb_priv = (struct crisv10_urb_priv *)urb->hcpriv; -+ ASSERT(urb_priv); -+ if (phys_to_virt(TxCtrlEPList[epid].sub) != urb_priv->last_sb) { -+ tc_err("Endpoint got disabled before reaching last sb\n"); -+ } -+ -+ epid_data = etrax_epid_get(epid); -+ if (IO_EXTRACT(R_USB_EPT_DATA, error_code, epid_data) == -+ IO_STATE_VALUE(R_USB_EPT_DATA, error_code, no_error)) { -+ /* This means that the endpoint has no error, is disabled -+ and had inserted traffic, i.e. transfer successfully completed. */ -+ -+ /* Check if RX-interrupt for In Ctrl has been processed before -+ finishing the URB */ -+ if(urb_priv->ctrl_rx_done) { -+ tc_dbg("Finishing In Ctrl URB:0x%x[%d] in tx_interrupt\n", -+ (unsigned int)urb, urb_priv->urb_num); -+ tc_finish_urb(hcd, urb, 0); -+ } else { -+ /* If we get zout descriptor interrupt before RX was done for a -+ In Ctrl transfer, then we flag that and it will be finished -+ in the RX-Interrupt */ -+ urb_priv->ctrl_zout_done = 1; -+ tc_dbg("Got zout descr interrupt before RX interrupt\n"); -+ } -+ } else { -+ /* Shouldn't happen. We expect errors to be caught by epid -+ attention. */ -+ tc_err("Found disabled Ctrl EP desc (epid:%d URB:0x%x[%d]) error_code:%d\n", epid, (unsigned int)urb, urb_priv->urb_num, IO_EXTRACT(R_USB_EPT_DATA, error_code, epid_data)); -+ __dump_ep_desc(&(TxCtrlEPList[epid])); -+ __dump_ept_data(epid); -+ } -+ } -+ } -+ local_irq_restore(flags); -+} -+ -+ /* hinko ignore usb_pipeisoc */ -+#if 0 -+/* This function goes through all epids that are setup for Out Isoc transfers -+ and marks (isoc_out_done) all queued URBs that the DMA has finished -+ transfer for. -+ No URB completetion is done here to make interrupt routine return quickly. -+ URBs are completed later with help of complete_isoc_bottom_half() that -+ becomes schedules when this functions is finished. */ -+static void check_finished_isoc_tx_epids(void) { -+ unsigned long flags; -+ int epid; -+ struct urb *urb; -+ struct crisv10_urb_priv * urb_priv; -+ struct USB_SB_Desc* sb_desc; -+ int epid_done; -+ -+ /* Protect TxIsocEPList */ -+ local_irq_save(flags); -+ -+ for (epid = 0; epid < NBR_OF_EPIDS; epid++) { -+ if (TxIsocEPList[epid].sub == 0 || epid == INVALID_EPID || -+ !epid_out_traffic(epid)) { -+ /* Nothing here to see. */ -+ continue; -+ } -+ ASSERT(epid_inuse(epid)); -+ ASSERT(epid_isoc(epid)); -+ -+ sb_desc = phys_to_virt(TxIsocEPList[epid].sub); -+ /* Find the last descriptor of the currently active URB for this ep. -+ This is the first descriptor in the sub list marked for a descriptor -+ interrupt. */ -+ while (sb_desc && !IO_EXTRACT(USB_SB_command, intr, sb_desc->command)) { -+ sb_desc = sb_desc->next ? phys_to_virt(sb_desc->next) : 0; -+ } -+ ASSERT(sb_desc); -+ -+ isoc_dbg("Descr IRQ checking epid:%d sub:0x%x intr:0x%x\n", -+ epid, (unsigned int)phys_to_virt(TxIsocEPList[epid].sub), -+ (unsigned int)sb_desc); -+ -+ urb = activeUrbList[epid]; -+ if(urb == NULL) { -+ isoc_err("Isoc Descr irq on epid:%d with no active URB\n", epid); -+ continue; -+ } -+ -+ epid_done = 0; -+ while(urb && !epid_done) { -+ /* Sanity check. */ -+ ASSERT(usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS); -+ ASSERT(usb_pipeout(urb->pipe)); -+ -+ urb_priv = (struct crisv10_urb_priv *)urb->hcpriv; -+ ASSERT(urb_priv); -+ ASSERT(urb_priv->urb_state == STARTED || -+ urb_priv->urb_state == UNLINK); -+ -+ if (sb_desc != urb_priv->last_sb) { -+ /* This urb has been sent. */ -+ urb_priv->isoc_out_done = 1; -+ -+ } else { /* Found URB that has last_sb as the interrupt reason */ -+ -+ /* Check if EP has been disabled, meaning that all transfers are done*/ -+ if(!(TxIsocEPList[epid].command & IO_MASK(USB_EP_command, enable))) { -+ ASSERT((sb_desc->command & IO_MASK(USB_SB_command, eol)) == -+ IO_STATE(USB_SB_command, eol, yes)); -+ ASSERT(sb_desc->next == 0); -+ urb_priv->isoc_out_done = 1; -+ } else { -+ isoc_dbg("Skipping URB:0x%x[%d] because EP not disabled yet\n", -+ (unsigned int)urb, urb_priv->urb_num); -+ } -+ /* Stop looking any further in queue */ -+ epid_done = 1; -+ } -+ -+ if (!epid_done) { -+ if(urb == activeUrbList[epid]) { -+ urb = urb_list_first(epid); -+ } else { -+ urb = urb_list_next(urb, epid); -+ } -+ } -+ } /* END: while(urb && !epid_done) */ -+ } -+ -+ local_irq_restore(flags); -+} -+ -+ -+/* This is where the Out Isoc URBs are realy completed. This function is -+ scheduled from tc_dma_tx_interrupt() when one or more Out Isoc transfers -+ are done. This functions completes all URBs earlier marked with -+ isoc_out_done by fast interrupt routine check_finished_isoc_tx_epids() */ -+ -+static void complete_isoc_bottom_half(void *data) { -+ struct crisv10_isoc_complete_data *comp_data; -+ struct usb_iso_packet_descriptor *packet; -+ struct crisv10_urb_priv * urb_priv; -+ unsigned long flags; -+ struct urb* urb; -+ int epid_done; -+ int epid; -+ int i; -+ -+ comp_data = (struct crisv10_isoc_complete_data*)data; -+ -+ local_irq_save(flags); -+ -+ for (epid = 0; epid < NBR_OF_EPIDS - 1; epid++) { -+ if(!epid_inuse(epid) || !epid_isoc(epid) || !epid_out_traffic(epid) || epid == DUMMY_EPID) { -+ /* Only check valid Out Isoc epids */ -+ continue; -+ } -+ -+ isoc_dbg("Isoc bottom-half checking epid:%d, sub:0x%x\n", epid, -+ (unsigned int)phys_to_virt(TxIsocEPList[epid].sub)); -+ -+ /* The descriptor interrupt handler has marked all transmitted Out Isoc -+ URBs with isoc_out_done. Now we traverse all epids and for all that -+ have out Isoc traffic we traverse its URB list and complete the -+ transmitted URBs. */ -+ epid_done = 0; -+ while (!epid_done) { -+ -+ /* Get the active urb (if any) */ -+ urb = activeUrbList[epid]; -+ if (urb == 0) { -+ isoc_dbg("No active URB on epid:%d anymore\n", epid); -+ epid_done = 1; -+ continue; -+ } -+ -+ /* Sanity check. */ -+ ASSERT(usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS); -+ ASSERT(usb_pipeout(urb->pipe)); -+ -+ urb_priv = (struct crisv10_urb_priv *)urb->hcpriv; -+ ASSERT(urb_priv); -+ -+ if (!(urb_priv->isoc_out_done)) { -+ /* We have reached URB that isn't flaged done yet, stop traversing. */ -+ isoc_dbg("Stoped traversing Out Isoc URBs on epid:%d" -+ " before not yet flaged URB:0x%x[%d]\n", -+ epid, (unsigned int)urb, urb_priv->urb_num); -+ epid_done = 1; -+ continue; -+ } -+ -+ /* This urb has been sent. */ -+ isoc_dbg("Found URB:0x%x[%d] that is flaged isoc_out_done\n", -+ (unsigned int)urb, urb_priv->urb_num); -+ -+ /* Set ok on transfered packets for this URB and finish it */ -+ for (i = 0; i < urb->number_of_packets; i++) { -+ packet = &urb->iso_frame_desc[i]; -+ packet->status = 0; -+ packet->actual_length = packet->length; -+ } -+ urb_priv->isoc_packet_counter = urb->number_of_packets; -+ tc_finish_urb(comp_data->hcd, urb, 0); -+ -+ } /* END: while(!epid_done) */ -+ } /* END: for(epid...) */ -+ -+ local_irq_restore(flags); -+ kmem_cache_free(isoc_compl_cache, comp_data); -+} -+#endif -+ -+static void check_finished_intr_tx_epids(struct usb_hcd *hcd) { -+ unsigned long flags; -+ int epid; -+ struct urb *urb; -+ struct crisv10_urb_priv * urb_priv; -+ volatile struct USB_EP_Desc *curr_ep; /* Current EP, the iterator. */ -+ volatile struct USB_EP_Desc *next_ep; /* The EP after current. */ -+ -+ /* Protect TxintrEPList */ -+ local_irq_save(flags); -+ -+ for (epid = 0; epid < NBR_OF_EPIDS; epid++) { -+ if(!epid_inuse(epid) || !epid_intr(epid) || !epid_out_traffic(epid)) { -+ /* Nothing to see on this epid. Only check valid Out Intr epids */ -+ continue; -+ } -+ -+ urb = activeUrbList[epid]; -+ if(urb == 0) { -+ intr_warn("Found Out Intr epid:%d with no active URB\n", epid); -+ continue; -+ } -+ -+ /* Sanity check. */ -+ ASSERT(usb_pipetype(urb->pipe) == PIPE_INTERRUPT); -+ ASSERT(usb_pipeout(urb->pipe)); -+ -+ urb_priv = (struct crisv10_urb_priv *)urb->hcpriv; -+ ASSERT(urb_priv); -+ -+ /* Go through EPs between first and second sof-EP. It's here Out Intr EPs -+ are inserted.*/ -+ curr_ep = &TxIntrEPList[0]; -+ do { -+ next_ep = (struct USB_EP_Desc *)phys_to_virt(curr_ep->next); -+ if(next_ep == urb_priv->intr_ep_pool[0]) { -+ /* We found the Out Intr EP for this epid */ -+ -+ /* Disable it so it doesn't get processed again */ -+ next_ep->command &= ~IO_MASK(USB_EP_command, enable); -+ -+ /* Finish the active Out Intr URB with status OK */ -+ tc_finish_urb(hcd, urb, 0); -+ } -+ curr_ep = phys_to_virt(curr_ep->next); -+ } while (curr_ep != &TxIntrEPList[1]); -+ -+ } -+ local_irq_restore(flags); -+} -+ -+/* Interrupt handler for DMA8/IRQ24 with subchannels (called from hardware intr) */ -+static irqreturn_t tc_dma_tx_interrupt(int irq, void *vhc) { -+ struct usb_hcd *hcd = (struct usb_hcd*)vhc; -+ ASSERT(hcd); -+ -+ if (*R_IRQ_READ2 & IO_MASK(R_IRQ_READ2, dma8_sub0_descr)) { -+ /* Clear this interrupt */ -+ *R_DMA_CH8_SUB0_CLR_INTR = IO_STATE(R_DMA_CH8_SUB0_CLR_INTR, clr_descr, do); -+ restart_dma8_sub0(); -+ } -+ -+ if (*R_IRQ_READ2 & IO_MASK(R_IRQ_READ2, dma8_sub1_descr)) { -+ /* Clear this interrupt */ -+ *R_DMA_CH8_SUB1_CLR_INTR = IO_STATE(R_DMA_CH8_SUB1_CLR_INTR, clr_descr, do); -+ check_finished_ctrl_tx_epids(hcd); -+ } -+ -+ if (*R_IRQ_READ2 & IO_MASK(R_IRQ_READ2, dma8_sub2_descr)) { -+ /* Clear this interrupt */ -+ *R_DMA_CH8_SUB2_CLR_INTR = IO_STATE(R_DMA_CH8_SUB2_CLR_INTR, clr_descr, do); -+ check_finished_intr_tx_epids(hcd); -+ } -+ -+ /* hinko ignore usb_pipeisoc */ -+#if 0 -+ if (*R_IRQ_READ2 & IO_MASK(R_IRQ_READ2, dma8_sub3_descr)) { -+ struct crisv10_isoc_complete_data* comp_data; -+ -+ /* Flag done Out Isoc for later completion */ -+ check_finished_isoc_tx_epids(); -+ -+ /* Clear this interrupt */ -+ *R_DMA_CH8_SUB3_CLR_INTR = IO_STATE(R_DMA_CH8_SUB3_CLR_INTR, clr_descr, do); -+ /* Schedule bottom half of Out Isoc completion function. This function -+ finishes the URBs marked with isoc_out_done */ -+ comp_data = (struct crisv10_isoc_complete_data*) -+ kmem_cache_alloc(isoc_compl_cache, GFP_ATOMIC); -+ ASSERT(comp_data != NULL); -+ comp_data ->hcd = hcd; -+ -+ //INIT_WORK(&comp_data->usb_bh, complete_isoc_bottom_half, comp_data); -+ INIT_WORK(&comp_data->usb_bh, complete_isoc_bottom_half); -+ schedule_work(&comp_data->usb_bh); -+ } -+#endif -+ -+ return IRQ_HANDLED; -+} -+ -+/* Interrupt handler for DMA9/IRQ25 (called from hardware intr) */ -+static irqreturn_t tc_dma_rx_interrupt(int irq, void *vhc) { -+ unsigned long flags; -+ struct urb *urb; -+ struct usb_hcd *hcd = (struct usb_hcd*)vhc; -+ struct crisv10_urb_priv *urb_priv; -+ int epid = 0; -+ int real_error; -+ -+ ASSERT(hcd); -+ -+ /* Clear this interrupt. */ -+ *R_DMA_CH9_CLR_INTR = IO_STATE(R_DMA_CH9_CLR_INTR, clr_eop, do); -+ -+ /* Custom clear interrupt for this interrupt */ -+ /* The reason we cli here is that we call the driver's callback functions. */ -+ local_irq_save(flags); -+ -+ /* Note that this while loop assumes that all packets span only -+ one rx descriptor. */ -+ while(myNextRxDesc->status & IO_MASK(USB_IN_status, eop)) { -+ epid = IO_EXTRACT(USB_IN_status, epid, myNextRxDesc->status); -+ /* Get the active URB for this epid */ -+ urb = activeUrbList[epid]; -+ -+ ASSERT(epid_inuse(epid)); -+ if (!urb) { -+ dma_err("No urb for epid %d in rx interrupt\n", epid); -+ goto skip_out; -+ } -+ -+ /* Check if any errors on epid */ -+ real_error = 0; -+ if (myNextRxDesc->status & IO_MASK(USB_IN_status, error)) { -+ __u32 r_usb_ept_data; -+ -+ if (usb_pipeisoc(urb->pipe)) { -+ r_usb_ept_data = etrax_epid_iso_get(epid); -+ if((r_usb_ept_data & IO_MASK(R_USB_EPT_DATA_ISO, valid)) && -+ (IO_EXTRACT(R_USB_EPT_DATA_ISO, error_code, r_usb_ept_data) == 0) && -+ (myNextRxDesc->status & IO_MASK(USB_IN_status, nodata))) { -+ /* Not an error, just a failure to receive an expected iso -+ in packet in this frame. This is not documented -+ in the designers reference. Continue processing. -+ */ -+ } else real_error = 1; -+ } else real_error = 1; -+ } -+ -+ if(real_error) { -+ dma_err("Error in RX descr on epid:%d for URB 0x%x", -+ epid, (unsigned int)urb); -+ dump_ept_data(epid); -+ dump_in_desc(myNextRxDesc); -+ goto skip_out; -+ } -+ -+ urb_priv = (struct crisv10_urb_priv *)urb->hcpriv; -+ ASSERT(urb_priv); -+ ASSERT(urb_priv->urb_state == STARTED || -+ urb_priv->urb_state == UNLINK); -+ -+ if ((usb_pipetype(urb->pipe) == PIPE_BULK) || -+ (usb_pipetype(urb->pipe) == PIPE_CONTROL) || -+ (usb_pipetype(urb->pipe) == PIPE_INTERRUPT)) { -+ -+ /* We get nodata for empty data transactions, and the rx descriptor's -+ hw_len field is not valid in that case. No data to copy in other -+ words. */ -+ if (myNextRxDesc->status & IO_MASK(USB_IN_status, nodata)) { -+ /* No data to copy */ -+ } else { -+ /* -+ dma_dbg("Processing RX for URB:0x%x epid:%d (data:%d ofs:%d)\n", -+ (unsigned int)urb, epid, myNextRxDesc->hw_len, -+ urb_priv->rx_offset); -+ */ -+ /* Only copy data if URB isn't flaged to be unlinked*/ -+ if(urb_priv->urb_state != UNLINK) { -+ /* Make sure the data fits in the buffer. */ -+ if(urb_priv->rx_offset + myNextRxDesc->hw_len -+ <= urb->transfer_buffer_length) { -+ -+ /* Copy the data to URBs buffer */ -+ memcpy(urb->transfer_buffer + urb_priv->rx_offset, -+ phys_to_virt(myNextRxDesc->buf), myNextRxDesc->hw_len); -+ urb_priv->rx_offset += myNextRxDesc->hw_len; -+ } else { -+ /* Signal overflow when returning URB */ -+ urb->status = -EOVERFLOW; -+ tc_finish_urb_later(hcd, urb, urb->status); -+ } -+ } -+ } -+ -+ /* Check if it was the last packet in the transfer */ -+ if (myNextRxDesc->status & IO_MASK(USB_IN_status, eot)) { -+ /* Special handling for In Ctrl URBs. */ -+ if(usb_pipecontrol(urb->pipe) && usb_pipein(urb->pipe) && -+ !(urb_priv->ctrl_zout_done)) { -+ /* Flag that RX part of Ctrl transfer is done. Because zout descr -+ interrupt hasn't happend yet will the URB be finished in the -+ TX-Interrupt. */ -+ urb_priv->ctrl_rx_done = 1; -+ tc_dbg("Not finishing In Ctrl URB:0x%x from rx_interrupt, waiting" -+ " for zout\n", (unsigned int)urb); -+ } else { -+ tc_finish_urb(hcd, urb, 0); -+ } -+ } -+ } else { /* ISOC RX */ -+ /* -+ isoc_dbg("Processing RX for epid:%d (URB:0x%x) ISOC pipe\n", -+ epid, (unsigned int)urb); -+ */ -+ -+ struct usb_iso_packet_descriptor *packet; -+ -+ if (urb_priv->urb_state == UNLINK) { -+ isoc_warn("Ignoring Isoc Rx data for urb being unlinked.\n"); -+ goto skip_out; -+ } else if (urb_priv->urb_state == NOT_STARTED) { -+ isoc_err("What? Got Rx data for Isoc urb that isn't started?\n"); -+ goto skip_out; -+ } -+ -+ packet = &urb->iso_frame_desc[urb_priv->isoc_packet_counter]; -+ ASSERT(packet); -+ packet->status = 0; -+ -+ if (myNextRxDesc->status & IO_MASK(USB_IN_status, nodata)) { -+ /* We get nodata for empty data transactions, and the rx descriptor's -+ hw_len field is not valid in that case. We copy 0 bytes however to -+ stay in synch. */ -+ packet->actual_length = 0; -+ } else { -+ packet->actual_length = myNextRxDesc->hw_len; -+ /* Make sure the data fits in the buffer. */ -+ ASSERT(packet->actual_length <= packet->length); -+ memcpy(urb->transfer_buffer + packet->offset, -+ phys_to_virt(myNextRxDesc->buf), packet->actual_length); -+ if(packet->actual_length > 0) -+ isoc_dbg("Copied %d bytes, packet %d for URB:0x%x[%d]\n", -+ packet->actual_length, urb_priv->isoc_packet_counter, -+ (unsigned int)urb, urb_priv->urb_num); -+ } -+ -+ /* Increment the packet counter. */ -+ urb_priv->isoc_packet_counter++; -+ -+ /* Note that we don't care about the eot field in the rx descriptor's -+ status. It will always be set for isoc traffic. */ -+ if (urb->number_of_packets == urb_priv->isoc_packet_counter) { -+ /* Complete the urb with status OK. */ -+ tc_finish_urb(hcd, urb, 0); -+ } -+ } -+ -+ skip_out: -+ myNextRxDesc->status = 0; -+ myNextRxDesc->command |= IO_MASK(USB_IN_command, eol); -+ myLastRxDesc->command &= ~IO_MASK(USB_IN_command, eol); -+ myLastRxDesc = myNextRxDesc; -+ myNextRxDesc = phys_to_virt(myNextRxDesc->next); -+ flush_etrax_cache(); -+ *R_DMA_CH9_CMD = IO_STATE(R_DMA_CH9_CMD, cmd, restart); -+ } -+ -+ local_irq_restore(flags); -+ -+ return IRQ_HANDLED; -+} -+ -+static void tc_bulk_start_timer_func(unsigned long dummy) { -+ /* We might enable an EP descriptor behind the current DMA position when -+ it's about to decide that there are no more bulk traffic and it should -+ stop the bulk channel. -+ Therefore we periodically check if the bulk channel is stopped and there -+ is an enabled bulk EP descriptor, in which case we start the bulk -+ channel. */ -+ -+ if (!(*R_DMA_CH8_SUB0_CMD & IO_MASK(R_DMA_CH8_SUB0_CMD, cmd))) { -+ int epid; -+ -+ timer_dbg("bulk_start_timer: Bulk DMA channel not running.\n"); -+ -+ for (epid = 0; epid < NBR_OF_EPIDS; epid++) { -+ if (TxBulkEPList[epid].command & IO_MASK(USB_EP_command, enable)) { -+ timer_warn("Found enabled EP for epid %d, starting bulk channel.\n", -+ epid); -+ restart_dma8_sub0(); -+ -+ /* Restart the bulk eot timer since we just started the bulk channel.*/ -+ mod_timer(&bulk_eot_timer, jiffies + BULK_EOT_TIMER_INTERVAL); -+ -+ /* No need to search any further. */ -+ break; -+ } -+ } -+ } else { -+ timer_dbg("bulk_start_timer: Bulk DMA channel running.\n"); -+ } -+} -+ -+static void tc_bulk_eot_timer_func(unsigned long dummy) { -+ struct usb_hcd *hcd = (struct usb_hcd*)dummy; -+ ASSERT(hcd); -+ /* Because of a race condition in the top half, we might miss a bulk eot. -+ This timer "simulates" a bulk eot if we don't get one for a while, -+ hopefully correcting the situation. */ -+ timer_dbg("bulk_eot_timer timed out.\n"); -+ check_finished_bulk_tx_epids(hcd, 1); -+} -+ -+ -+/*************************************************************/ -+/*************************************************************/ -+/* Device driver block */ -+/*************************************************************/ -+/*************************************************************/ -+ -+/* Forward declarations for device driver functions */ -+static int devdrv_hcd_probe(struct device *); -+static int devdrv_hcd_remove(struct device *); -+#ifdef CONFIG_PM -+static int devdrv_hcd_suspend(struct device *, u32, u32); -+static int devdrv_hcd_resume(struct device *, u32); -+#endif /* CONFIG_PM */ -+ -+/* the device */ -+static struct platform_device *devdrv_hc_platform_device; -+ -+/* device driver interface */ -+static struct device_driver devdrv_hc_device_driver = { -+ .name = (char *) hc_name, -+ .bus = &platform_bus_type, -+ -+ .probe = devdrv_hcd_probe, -+ .remove = devdrv_hcd_remove, -+ -+#ifdef CONFIG_PM -+ .suspend = devdrv_hcd_suspend, -+ .resume = devdrv_hcd_resume, -+#endif /* CONFIG_PM */ -+}; -+ -+/* initialize the host controller and driver */ -+static int __init_or_module devdrv_hcd_probe(struct device *dev) -+{ -+ struct usb_hcd *hcd; -+ struct crisv10_hcd *crisv10_hcd; -+ int retval; -+ int rev_maj, rev_min; -+ -+ /* Check DMA burst length */ -+ if(IO_EXTRACT(R_BUS_CONFIG, dma_burst, *R_BUS_CONFIG) != -+ IO_STATE(R_BUS_CONFIG, dma_burst, burst32)) { -+ devdrv_err("Invalid DMA burst length in Etrax 100LX," -+ " needs to be 32\n"); -+ return -EPERM; -+ } -+ -+ hcd = usb_create_hcd(&crisv10_hc_driver, dev, dev_name(dev)); -+ if (!hcd) -+ return -ENOMEM; -+ -+ crisv10_hcd = hcd_to_crisv10_hcd(hcd); -+ spin_lock_init(&crisv10_hcd->lock); -+ crisv10_hcd->num_ports = num_ports(); -+ crisv10_hcd->running = 0; -+ -+ dev_set_drvdata(dev, crisv10_hcd); -+ -+ devdrv_dbg("ETRAX USB IRQs HC:%d RX:%d TX:%d\n", ETRAX_USB_HC_IRQ, -+ ETRAX_USB_RX_IRQ, ETRAX_USB_TX_IRQ); -+ -+ /* Print out chip version read from registers */ -+ rev_maj = *R_USB_REVISION & IO_MASK(R_USB_REVISION, major); -+ rev_min = *R_USB_REVISION & IO_MASK(R_USB_REVISION, minor); -+ if(rev_min == 0) { -+ devdrv_info("Etrax 100LX USB Revision %d v1,2\n", rev_maj); -+ } else { -+ devdrv_info("Etrax 100LX USB Revision %d v%d\n", rev_maj, rev_min); -+ } -+ -+ devdrv_info("Bulk timer interval, start:%d eot:%d\n", -+ BULK_START_TIMER_INTERVAL, -+ BULK_EOT_TIMER_INTERVAL); -+ -+ -+ /* Init root hub data structures */ -+ if(rh_init()) { -+ devdrv_err("Failed init data for Root Hub\n"); -+ retval = -ENOMEM; -+ } -+ -+ if(port_in_use(0)) { -+ if (cris_request_io_interface(if_usb_1, "ETRAX100LX USB-HCD")) { -+ printk(KERN_CRIT "usb-host: request IO interface usb1 failed"); -+ retval = -EBUSY; -+ goto out; -+ } -+ devdrv_info("Claimed interface for USB physical port 1\n"); -+ } -+ if(port_in_use(1)) { -+ if (cris_request_io_interface(if_usb_2, "ETRAX100LX USB-HCD")) { -+ /* Free first interface if second failed to be claimed */ -+ if(port_in_use(0)) { -+ cris_free_io_interface(if_usb_1); -+ } -+ printk(KERN_CRIT "usb-host: request IO interface usb2 failed"); -+ retval = -EBUSY; -+ goto out; -+ } -+ devdrv_info("Claimed interface for USB physical port 2\n"); -+ } -+ -+ /* Init transfer controller structs and locks */ -+ if((retval = tc_init(hcd)) != 0) { -+ goto out; -+ } -+ -+ /* Attach interrupt functions for DMA and init DMA controller */ -+ if((retval = tc_dma_init(hcd)) != 0) { -+ goto out; -+ } -+ -+ /* Attach the top IRQ handler for USB controller interrupts */ -+ if (request_irq(ETRAX_USB_HC_IRQ, crisv10_hcd_top_irq, 0, -+ "ETRAX 100LX built-in USB (HC)", hcd)) { -+ err("Could not allocate IRQ %d for USB", ETRAX_USB_HC_IRQ); -+ retval = -EBUSY; -+ goto out; -+ } -+ -+ /* iso_eof is only enabled when isoc traffic is running. */ -+ *R_USB_IRQ_MASK_SET = -+ /* IO_STATE(R_USB_IRQ_MASK_SET, iso_eof, set) | */ -+ IO_STATE(R_USB_IRQ_MASK_SET, bulk_eot, set) | -+ IO_STATE(R_USB_IRQ_MASK_SET, epid_attn, set) | -+ IO_STATE(R_USB_IRQ_MASK_SET, port_status, set) | -+ IO_STATE(R_USB_IRQ_MASK_SET, ctl_status, set); -+ -+ -+ crisv10_ready_wait(); -+ /* Reset the USB interface. */ -+ *R_USB_COMMAND = -+ IO_STATE(R_USB_COMMAND, port_sel, nop) | -+ IO_STATE(R_USB_COMMAND, port_cmd, reset) | -+ IO_STATE(R_USB_COMMAND, ctrl_cmd, reset); -+ -+ /* Designer's Reference, p. 8 - 10 says we should Initate R_USB_FM_PSTART to -+ 0x2A30 (10800), to guarantee that control traffic gets 10% of the -+ bandwidth, and periodic transfer may allocate the rest (90%). -+ This doesn't work though. -+ The value 11960 is chosen to be just after the SOF token, with a couple -+ of bit times extra for possible bit stuffing. */ -+ *R_USB_FM_PSTART = IO_FIELD(R_USB_FM_PSTART, value, 11960); -+ -+ crisv10_ready_wait(); -+ /* Configure the USB interface as a host controller. */ -+ *R_USB_COMMAND = -+ IO_STATE(R_USB_COMMAND, port_sel, nop) | -+ IO_STATE(R_USB_COMMAND, port_cmd, reset) | -+ IO_STATE(R_USB_COMMAND, ctrl_cmd, host_config); -+ -+ -+ /* Check so controller not busy before enabling ports */ -+ crisv10_ready_wait(); -+ -+ /* Enable selected USB ports */ -+ if(port_in_use(0)) { -+ *R_USB_PORT1_DISABLE = IO_STATE(R_USB_PORT1_DISABLE, disable, no); -+ } else { -+ *R_USB_PORT1_DISABLE = IO_STATE(R_USB_PORT1_DISABLE, disable, yes); -+ } -+ if(port_in_use(1)) { -+ *R_USB_PORT2_DISABLE = IO_STATE(R_USB_PORT2_DISABLE, disable, no); -+ } else { -+ *R_USB_PORT2_DISABLE = IO_STATE(R_USB_PORT2_DISABLE, disable, yes); -+ } -+ -+ crisv10_ready_wait(); -+ /* Start processing of USB traffic. */ -+ *R_USB_COMMAND = -+ IO_STATE(R_USB_COMMAND, port_sel, nop) | -+ IO_STATE(R_USB_COMMAND, port_cmd, reset) | -+ IO_STATE(R_USB_COMMAND, ctrl_cmd, host_run); -+ -+ /* Do not continue probing initialization before USB interface is done */ -+ crisv10_ready_wait(); -+ -+ /* Register our Host Controller to USB Core -+ * Finish the remaining parts of generic HCD initialization: allocate the -+ * buffers of consistent memory, register the bus -+ * and call the driver's reset() and start() routines. */ -+ retval = usb_add_hcd(hcd, ETRAX_USB_HC_IRQ, IRQF_DISABLED); -+ if (retval != 0) { -+ devdrv_err("Failed registering HCD driver\n"); -+ goto out; -+ } -+ -+ return 0; -+ -+ out: -+ devdrv_hcd_remove(dev); -+ return retval; -+} -+ -+ -+/* cleanup after the host controller and driver */ -+static int __init_or_module devdrv_hcd_remove(struct device *dev) -+{ -+ struct crisv10_hcd *crisv10_hcd = dev_get_drvdata(dev); -+ struct usb_hcd *hcd; -+ -+ if (!crisv10_hcd) -+ return 0; -+ hcd = crisv10_hcd_to_hcd(crisv10_hcd); -+ -+ -+ /* Stop USB Controller in Etrax 100LX */ -+ crisv10_hcd_reset(hcd); -+ -+ usb_remove_hcd(hcd); -+ devdrv_dbg("Removed HCD from USB Core\n"); -+ -+ /* Free USB Controller IRQ */ -+ free_irq(ETRAX_USB_HC_IRQ, NULL); -+ -+ /* Free resources */ -+ tc_dma_destroy(); -+ tc_destroy(); -+ -+ -+ if(port_in_use(0)) { -+ cris_free_io_interface(if_usb_1); -+ } -+ if(port_in_use(1)) { -+ cris_free_io_interface(if_usb_2); -+ } -+ -+ devdrv_dbg("Freed all claimed resources\n"); -+ -+ return 0; -+} -+ -+ -+#ifdef CONFIG_PM -+ -+static int devdrv_hcd_suspend(struct usb_hcd *hcd, u32 state, u32 level) -+{ -+ return 0; /* no-op for now */ -+} -+ -+static int devdrv_hcd_resume(struct usb_hcd *hcd, u32 level) -+{ -+ return 0; /* no-op for now */ -+} -+ -+#endif /* CONFIG_PM */ -+ -+ -+ -+/*************************************************************/ -+/*************************************************************/ -+/* Module block */ -+/*************************************************************/ -+/*************************************************************/ -+ -+/* register driver */ -+static int __init module_hcd_init(void) -+{ -+ -+ if (usb_disabled()) -+ return -ENODEV; -+ -+ /* Here we select enabled ports by following defines created from -+ menuconfig */ -+#ifndef CONFIG_ETRAX_USB_HOST_PORT1 -+ ports &= ~(1<<0); -+#endif -+#ifndef CONFIG_ETRAX_USB_HOST_PORT2 -+ ports &= ~(1<<1); -+#endif -+ -+ printk(KERN_INFO "%s version "VERSION" "COPYRIGHT"\n", product_desc); -+ -+ devdrv_hc_platform_device = -+ platform_device_register_simple((char *) hc_name, 0, NULL, 0); -+ -+ if (IS_ERR(devdrv_hc_platform_device)) -+ return PTR_ERR(devdrv_hc_platform_device); -+ return driver_register(&devdrv_hc_device_driver); -+ /* -+ * Note that we do not set the DMA mask for the device, -+ * i.e. we pretend that we will use PIO, since no specific -+ * allocation routines are needed for DMA buffers. This will -+ * cause the HCD buffer allocation routines to fall back to -+ * kmalloc(). -+ */ -+} -+ -+/* unregister driver */ -+static void __exit module_hcd_exit(void) -+{ -+ driver_unregister(&devdrv_hc_device_driver); -+} -+ -+ -+/* Module hooks */ -+module_init(module_hcd_init); -+module_exit(module_hcd_exit); -diff -Nur linux-2.6.39.orig/drivers/usb/host/hc-crisv10.h linux-2.6.39/drivers/usb/host/hc-crisv10.h ---- linux-2.6.39.orig/drivers/usb/host/hc-crisv10.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/drivers/usb/host/hc-crisv10.h 2011-08-25 07:43:03.100480030 +0200 -@@ -0,0 +1,331 @@ -+#ifndef __LINUX_ETRAX_USB_H -+#define __LINUX_ETRAX_USB_H -+ -+#include -+#include -+ -+struct USB_IN_Desc { -+ volatile __u16 sw_len; -+ volatile __u16 command; -+ volatile unsigned long next; -+ volatile unsigned long buf; -+ volatile __u16 hw_len; -+ volatile __u16 status; -+}; -+ -+struct USB_SB_Desc { -+ volatile __u16 sw_len; -+ volatile __u16 command; -+ volatile unsigned long next; -+ volatile unsigned long buf; -+}; -+ -+struct USB_EP_Desc { -+ volatile __u16 hw_len; -+ volatile __u16 command; -+ volatile unsigned long sub; -+ volatile unsigned long next; -+}; -+ -+ -+/* Root Hub port status struct */ -+struct crisv10_rh { -+ volatile __u16 wPortChange[2]; -+ volatile __u16 wPortStatusPrev[2]; -+}; -+ -+/* HCD description */ -+struct crisv10_hcd { -+ spinlock_t lock; -+ __u8 num_ports; -+ __u8 running; -+}; -+ -+ -+/* Endpoint HC private data description */ -+struct crisv10_ep_priv { -+ int epid; -+}; -+ -+/* Additional software state info for a USB Controller epid */ -+struct etrax_epid { -+ __u8 inuse; /* !0 = setup in Etrax and used for a endpoint */ -+ __u8 disabled; /* !0 = Temporarly disabled to avoid resubmission */ -+ __u8 type; /* Setup as: PIPE_BULK, PIPE_CONTROL ... */ -+ __u8 out_traffic; /* !0 = This epid is for out traffic */ -+}; -+ -+/* Struct to hold information of scheduled later URB completion */ -+struct urb_later_data { -+// struct work_struct ws; -+ struct delayed_work ws; -+ struct usb_hcd *hcd; -+ struct urb *urb; -+ int urb_num; -+ int status; -+}; -+ -+ -+typedef enum { -+ STARTED, -+ NOT_STARTED, -+ UNLINK, -+} crisv10_urb_state_t; -+ -+ -+struct crisv10_urb_priv { -+ /* Sequence number for this URB. Every new submited URB gets this from -+ a incrementing counter. Used when a URB is scheduled for later finish to -+ be sure that the intended URB hasn't already been completed (device -+ drivers has a tendency to reuse URBs once they are completed, causing us -+ to not be able to single old ones out only based on the URB pointer.) */ -+ __u32 urb_num; -+ -+ /* The first_sb field is used for freeing all SB descriptors belonging -+ to an urb. The corresponding ep descriptor's sub pointer cannot be -+ used for this since the DMA advances the sub pointer as it processes -+ the sb list. */ -+ struct USB_SB_Desc *first_sb; -+ -+ /* The last_sb field referes to the last SB descriptor that belongs to -+ this urb. This is important to know so we can free the SB descriptors -+ that ranges between first_sb and last_sb. */ -+ struct USB_SB_Desc *last_sb; -+ -+ /* The rx_offset field is used in ctrl and bulk traffic to keep track -+ of the offset in the urb's transfer_buffer where incoming data should be -+ copied to. */ -+ __u32 rx_offset; -+ -+ /* Counter used in isochronous transfers to keep track of the -+ number of packets received/transmitted. */ -+ __u32 isoc_packet_counter; -+ -+ /* Flag that marks if this Isoc Out URB has finished it's transfer. Used -+ because several URBs can be finished before list is processed */ -+ __u8 isoc_out_done; -+ -+ /* This field is used to pass information about the urb's current state -+ between the various interrupt handlers (thus marked volatile). */ -+ volatile crisv10_urb_state_t urb_state; -+ -+ /* In Ctrl transfers consist of (at least) 3 packets: SETUP, IN and ZOUT. -+ When DMA8 sub-channel 2 has processed the SB list for this sequence we -+ get a interrupt. We also get a interrupt for In transfers and which -+ one of these interrupts that comes first depends of data size and device. -+ To be sure that we have got both interrupts before we complete the URB -+ we have these to flags that shows which part that has completed. -+ We can then check when we get one of the interrupts that if the other has -+ occured it's safe for us to complete the URB, otherwise we set appropriate -+ flag and do the completion when we get the other interrupt. */ -+ volatile unsigned char ctrl_zout_done; -+ volatile unsigned char ctrl_rx_done; -+ -+ /* Connection between the submitted urb and ETRAX epid number */ -+ __u8 epid; -+ -+ /* The rx_data_list field is used for periodic traffic, to hold -+ received data for later processing in the the complete_urb functions, -+ where the data us copied to the urb's transfer_buffer. Basically, we -+ use this intermediate storage because we don't know when it's safe to -+ reuse the transfer_buffer (FIXME?). */ -+ struct list_head rx_data_list; -+ -+ -+ /* The interval time rounded up to closest 2^N */ -+ int interval; -+ -+ /* Pool of EP descriptors needed if it's a INTR transfer. -+ Amount of EPs in pool correspons to how many INTR that should -+ be inserted in TxIntrEPList (max 128, defined by MAX_INTR_INTERVAL) */ -+ struct USB_EP_Desc* intr_ep_pool[128]; -+ -+ /* The mount of EPs allocated for this INTR URB */ -+ int intr_ep_pool_length; -+ -+ /* Pointer to info struct if URB is scheduled to be finished later */ -+ struct urb_later_data* later_data; -+}; -+ -+ -+/* This struct is for passing data from the top half to the bottom half irq -+ handlers */ -+struct crisv10_irq_reg { -+ struct usb_hcd* hcd; -+ __u32 r_usb_epid_attn; -+ __u8 r_usb_status; -+ __u16 r_usb_rh_port_status_1; -+ __u16 r_usb_rh_port_status_2; -+ __u32 r_usb_irq_mask_read; -+ __u32 r_usb_fm_number; -+ struct work_struct usb_bh; -+}; -+ -+ -+/* This struct is for passing data from the isoc top half to the isoc bottom -+ half. */ -+struct crisv10_isoc_complete_data { -+ struct usb_hcd *hcd; -+ struct urb *urb; -+ struct work_struct usb_bh; -+}; -+ -+/* Entry item for URB lists for each endpint */ -+typedef struct urb_entry -+{ -+ struct urb *urb; -+ struct list_head list; -+} urb_entry_t; -+ -+/* --------------------------------------------------------------------------- -+ Virtual Root HUB -+ ------------------------------------------------------------------------- */ -+/* destination of request */ -+#define RH_INTERFACE 0x01 -+#define RH_ENDPOINT 0x02 -+#define RH_OTHER 0x03 -+ -+#define RH_CLASS 0x20 -+#define RH_VENDOR 0x40 -+ -+/* Requests: bRequest << 8 | bmRequestType */ -+#define RH_GET_STATUS 0x0080 -+#define RH_CLEAR_FEATURE 0x0100 -+#define RH_SET_FEATURE 0x0300 -+#define RH_SET_ADDRESS 0x0500 -+#define RH_GET_DESCRIPTOR 0x0680 -+#define RH_SET_DESCRIPTOR 0x0700 -+#define RH_GET_CONFIGURATION 0x0880 -+#define RH_SET_CONFIGURATION 0x0900 -+#define RH_GET_STATE 0x0280 -+#define RH_GET_INTERFACE 0x0A80 -+#define RH_SET_INTERFACE 0x0B00 -+#define RH_SYNC_FRAME 0x0C80 -+/* Our Vendor Specific Request */ -+#define RH_SET_EP 0x2000 -+ -+ -+/* Hub port features */ -+#define RH_PORT_CONNECTION 0x00 -+#define RH_PORT_ENABLE 0x01 -+#define RH_PORT_SUSPEND 0x02 -+#define RH_PORT_OVER_CURRENT 0x03 -+#define RH_PORT_RESET 0x04 -+#define RH_PORT_POWER 0x08 -+#define RH_PORT_LOW_SPEED 0x09 -+#define RH_C_PORT_CONNECTION 0x10 -+#define RH_C_PORT_ENABLE 0x11 -+#define RH_C_PORT_SUSPEND 0x12 -+#define RH_C_PORT_OVER_CURRENT 0x13 -+#define RH_C_PORT_RESET 0x14 -+ -+/* Hub features */ -+#define RH_C_HUB_LOCAL_POWER 0x00 -+#define RH_C_HUB_OVER_CURRENT 0x01 -+ -+#define RH_DEVICE_REMOTE_WAKEUP 0x00 -+#define RH_ENDPOINT_STALL 0x01 -+ -+/* Our Vendor Specific feature */ -+#define RH_REMOVE_EP 0x00 -+ -+ -+#define RH_ACK 0x01 -+#define RH_REQ_ERR -1 -+#define RH_NACK 0x00 -+ -+/* Field definitions for */ -+ -+#define USB_IN_command__eol__BITNR 0 /* command macros */ -+#define USB_IN_command__eol__WIDTH 1 -+#define USB_IN_command__eol__no 0 -+#define USB_IN_command__eol__yes 1 -+ -+#define USB_IN_command__intr__BITNR 3 -+#define USB_IN_command__intr__WIDTH 1 -+#define USB_IN_command__intr__no 0 -+#define USB_IN_command__intr__yes 1 -+ -+#define USB_IN_status__eop__BITNR 1 /* status macros. */ -+#define USB_IN_status__eop__WIDTH 1 -+#define USB_IN_status__eop__no 0 -+#define USB_IN_status__eop__yes 1 -+ -+#define USB_IN_status__eot__BITNR 5 -+#define USB_IN_status__eot__WIDTH 1 -+#define USB_IN_status__eot__no 0 -+#define USB_IN_status__eot__yes 1 -+ -+#define USB_IN_status__error__BITNR 6 -+#define USB_IN_status__error__WIDTH 1 -+#define USB_IN_status__error__no 0 -+#define USB_IN_status__error__yes 1 -+ -+#define USB_IN_status__nodata__BITNR 7 -+#define USB_IN_status__nodata__WIDTH 1 -+#define USB_IN_status__nodata__no 0 -+#define USB_IN_status__nodata__yes 1 -+ -+#define USB_IN_status__epid__BITNR 8 -+#define USB_IN_status__epid__WIDTH 5 -+ -+#define USB_EP_command__eol__BITNR 0 -+#define USB_EP_command__eol__WIDTH 1 -+#define USB_EP_command__eol__no 0 -+#define USB_EP_command__eol__yes 1 -+ -+#define USB_EP_command__eof__BITNR 1 -+#define USB_EP_command__eof__WIDTH 1 -+#define USB_EP_command__eof__no 0 -+#define USB_EP_command__eof__yes 1 -+ -+#define USB_EP_command__intr__BITNR 3 -+#define USB_EP_command__intr__WIDTH 1 -+#define USB_EP_command__intr__no 0 -+#define USB_EP_command__intr__yes 1 -+ -+#define USB_EP_command__enable__BITNR 4 -+#define USB_EP_command__enable__WIDTH 1 -+#define USB_EP_command__enable__no 0 -+#define USB_EP_command__enable__yes 1 -+ -+#define USB_EP_command__hw_valid__BITNR 5 -+#define USB_EP_command__hw_valid__WIDTH 1 -+#define USB_EP_command__hw_valid__no 0 -+#define USB_EP_command__hw_valid__yes 1 -+ -+#define USB_EP_command__epid__BITNR 8 -+#define USB_EP_command__epid__WIDTH 5 -+ -+#define USB_SB_command__eol__BITNR 0 /* command macros. */ -+#define USB_SB_command__eol__WIDTH 1 -+#define USB_SB_command__eol__no 0 -+#define USB_SB_command__eol__yes 1 -+ -+#define USB_SB_command__eot__BITNR 1 -+#define USB_SB_command__eot__WIDTH 1 -+#define USB_SB_command__eot__no 0 -+#define USB_SB_command__eot__yes 1 -+ -+#define USB_SB_command__intr__BITNR 3 -+#define USB_SB_command__intr__WIDTH 1 -+#define USB_SB_command__intr__no 0 -+#define USB_SB_command__intr__yes 1 -+ -+#define USB_SB_command__tt__BITNR 4 -+#define USB_SB_command__tt__WIDTH 2 -+#define USB_SB_command__tt__zout 0 -+#define USB_SB_command__tt__in 1 -+#define USB_SB_command__tt__out 2 -+#define USB_SB_command__tt__setup 3 -+ -+ -+#define USB_SB_command__rem__BITNR 8 -+#define USB_SB_command__rem__WIDTH 6 -+ -+#define USB_SB_command__full__BITNR 6 -+#define USB_SB_command__full__WIDTH 1 -+#define USB_SB_command__full__no 0 -+#define USB_SB_command__full__yes 1 -+ -+#endif -diff -Nur linux-2.6.39.orig/drivers/usb/host/Makefile linux-2.6.39/drivers/usb/host/Makefile ---- linux-2.6.39.orig/drivers/usb/host/Makefile 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/drivers/usb/host/Makefile 2011-08-25 07:43:03.209057611 +0200 -@@ -32,6 +32,7 @@ - obj-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o - obj-$(CONFIG_USB_ISP1760_HCD) += isp1760.o - obj-$(CONFIG_USB_HWA_HCD) += hwa-hc.o -+obj-$(CONFIG_ETRAX_USB_HOST) += hc-crisv10.o - obj-$(CONFIG_USB_IMX21_HCD) += imx21-hcd.o - obj-$(CONFIG_USB_FSL_MPH_DR_OF) += fsl-mph-dr-of.o - obj-$(CONFIG_USB_OCTEON2_COMMON) += octeon2-common.o -diff -Nur linux-2.6.39.orig/drivers/usb/Makefile linux-2.6.39/drivers/usb/Makefile ---- linux-2.6.39.orig/drivers/usb/Makefile 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/drivers/usb/Makefile 2011-08-25 07:43:03.380490677 +0200 -@@ -21,6 +21,7 @@ - obj-$(CONFIG_USB_R8A66597_HCD) += host/ - obj-$(CONFIG_USB_HWA_HCD) += host/ - obj-$(CONFIG_USB_ISP1760_HCD) += host/ -+obj-$(CONFIG_ETRAX_USB_HOST) += host/ - obj-$(CONFIG_USB_IMX21_HCD) += host/ - - obj-$(CONFIG_USB_C67X00_HCD) += c67x00/ -diff -Nur linux-2.6.39.orig/lib/klist.c linux-2.6.39/lib/klist.c ---- linux-2.6.39.orig/lib/klist.c 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/lib/klist.c 2011-08-25 07:43:03.558483154 +0200 -@@ -60,7 +60,7 @@ - { - knode->n_klist = klist; - /* no knode deserves to start its life dead */ -- WARN_ON(knode_dead(knode)); -+ //WARN_ON(knode_dead(knode)); - } - - static void knode_kill(struct klist_node *knode) diff --git a/target/linux/patches/2.6.39/defaults.patch b/target/linux/patches/2.6.39/defaults.patch deleted file mode 100644 index d24c1c367..000000000 --- a/target/linux/patches/2.6.39/defaults.patch +++ /dev/null @@ -1,26 +0,0 @@ -diff -Nur linux-2.6.39.orig/fs/Kconfig linux-2.6.39/fs/Kconfig ---- linux-2.6.39.orig/fs/Kconfig 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/fs/Kconfig 2011-08-08 20:33:22.618014757 +0200 -@@ -44,10 +44,10 @@ - # this symbol for ifdefs in core code. - # - config FS_POSIX_ACL -- def_bool n -+ def_bool y - - config EXPORTFS -- bool -+ def_bool y - - config FILE_LOCKING - bool "Enable POSIX file locking API" if EXPERT -diff -Nur linux-2.6.39.orig/fs/notify/Kconfig linux-2.6.39/fs/notify/Kconfig ---- linux-2.6.39.orig/fs/notify/Kconfig 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/fs/notify/Kconfig 2011-08-08 20:33:38.328017344 +0200 -@@ -1,5 +1,5 @@ - config FSNOTIFY -- def_bool n -+ def_bool y - - source "fs/notify/dnotify/Kconfig" - source "fs/notify/inotify/Kconfig" diff --git a/target/linux/patches/2.6.39/fon2100.patch b/target/linux/patches/2.6.39/fon2100.patch deleted file mode 100644 index 038ff7020..000000000 --- a/target/linux/patches/2.6.39/fon2100.patch +++ /dev/null @@ -1,6279 +0,0 @@ -diff -Nur linux-2.6.39-rc7.orig/arch/mips/Kbuild.platforms linux-2.6.39-rc7/arch/mips/Kbuild.platforms ---- linux-2.6.39-rc7.orig/arch/mips/Kbuild.platforms 2011-05-10 04:33:54.000000000 +0200 -+++ linux-2.6.39-rc7/arch/mips/Kbuild.platforms 2011-05-15 21:34:57.000000000 +0200 -@@ -6,6 +6,7 @@ - platforms += bcm47xx - platforms += bcm63xx - platforms += cavium-octeon -+platforms += ar231x - platforms += cobalt - platforms += dec - platforms += emma -diff -Nur linux-2.6.39-rc7.orig/arch/mips/Kconfig linux-2.6.39-rc7/arch/mips/Kconfig ---- linux-2.6.39-rc7.orig/arch/mips/Kconfig 2011-05-10 04:33:54.000000000 +0200 -+++ linux-2.6.39-rc7/arch/mips/Kconfig 2011-05-16 12:11:11.000000000 +0200 -@@ -121,6 +121,21 @@ - help - Support for BCM63XX based boards - -+config ATHEROS_AR231X -+ bool "Atheros 231x/531x SoC support" -+ select CEVT_R4K -+ select CSRC_R4K -+ select DMA_NONCOHERENT -+ select IRQ_CPU -+ select SYS_HAS_CPU_MIPS32_R1 -+ select SYS_SUPPORTS_BIG_ENDIAN -+ select SYS_SUPPORTS_32BIT_KERNEL -+ select GENERIC_GPIO -+ select SYS_HAS_EARLY_PRINTK -+ select SYS_SUPPORTS_ZBOOT -+ help -+ Support for AR231x and AR531x based boards -+ - config MIPS_COBALT - bool "Cobalt Server" - select CEVT_R4K -@@ -738,6 +753,7 @@ - - endchoice - -+source "arch/mips/ar231x/Kconfig" - source "arch/mips/alchemy/Kconfig" - source "arch/mips/ath79/Kconfig" - source "arch/mips/bcm63xx/Kconfig" -diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/Kconfig linux-2.6.39-rc7/arch/mips/ar231x/Kconfig ---- linux-2.6.39-rc7.orig/arch/mips/ar231x/Kconfig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/ar231x/Kconfig 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,27 @@ -+config ATHEROS_AR5312 -+ bool "Atheros 5312/2312+ support" -+ depends on ATHEROS_AR231X -+ default y -+ -+config ATHEROS_AR2315 -+ bool "Atheros 2315+ support" -+ depends on ATHEROS_AR231X -+ select DMA_NONCOHERENT -+ select CEVT_R4K -+ select CSRC_R4K -+ select IRQ_CPU -+ select SYS_HAS_CPU_MIPS32_R1 -+ select SYS_SUPPORTS_32BIT_KERNEL -+ select SYS_SUPPORTS_BIG_ENDIAN -+ select GENERIC_GPIO -+ default y -+ -+config ATHEROS_AR2315_PCI -+ bool "PCI support" -+ depends on ATHEROS_AR2315 -+ select HW_HAS_PCI -+ select PCI -+ select USB_ARCH_HAS_HCD -+ select USB_ARCH_HAS_OHCI -+ select USB_ARCH_HAS_EHCI -+ default n -diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/Makefile linux-2.6.39-rc7/arch/mips/ar231x/Makefile ---- linux-2.6.39-rc7.orig/arch/mips/ar231x/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/ar231x/Makefile 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,17 @@ -+# -+# This file is subject to the terms and conditions of the GNU General Public -+# License. See the file "COPYING" in the main directory of this archive -+# for more details. -+# -+# Copyright (C) 2006 FON Technology, SL. -+# Copyright (C) 2006 Imre Kaloz -+# Copyright (C) 2006-2009 Felix Fietkau -+# -+ -+obj-y += board.o prom.o devices.o -+ -+obj-$(CONFIG_EARLY_PRINTK) += early_printk.o -+ -+obj-$(CONFIG_ATHEROS_AR5312) += ar5312.o -+obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o -+obj-$(CONFIG_ATHEROS_AR2315_PCI) += pci.o -diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/Platform linux-2.6.39-rc7/arch/mips/ar231x/Platform ---- linux-2.6.39-rc7.orig/arch/mips/ar231x/Platform 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/ar231x/Platform 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,6 @@ -+# -+# Atheros AR5312/AR2312 WiSoC -+# -+platform-$(CONFIG_ATHEROS_AR231X) += ar231x/ -+cflags-$(CONFIG_ATHEROS_AR231X) += -I$(srctree)/arch/mips/include/asm/mach-ar231x -+load-$(CONFIG_ATHEROS_AR231X) += 0xffffffff80041000 -diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/ar2315.c linux-2.6.39-rc7/arch/mips/ar231x/ar2315.c ---- linux-2.6.39-rc7.orig/arch/mips/ar231x/ar2315.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/ar231x/ar2315.c 2011-05-15 21:47:07.000000000 +0200 -@@ -0,0 +1,654 @@ -+/* -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. -+ * Copyright (C) 2006 FON Technology, SL. -+ * Copyright (C) 2006 Imre Kaloz -+ * Copyright (C) 2006 Felix Fietkau -+ */ -+ -+/* -+ * Platform devices for Atheros SoCs -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include "devices.h" -+#include "ar2315.h" -+ -+static u32 gpiointmask = 0, gpiointval = 0; -+ -+static inline void ar2315_gpio_irq(void) -+{ -+ u32 pend; -+ int bit = -1; -+ -+ /* only do one gpio interrupt at a time */ -+ pend = (ar231x_read_reg(AR2315_GPIO_DI) ^ gpiointval) & gpiointmask; -+ -+ if (pend) { -+ bit = fls(pend) - 1; -+ pend &= ~(1 << bit); -+ gpiointval ^= (1 << bit); -+ } -+ -+ if (!pend) -+ ar231x_write_reg(AR2315_ISR, AR2315_ISR_GPIO); -+ -+ /* Enable interrupt with edge detection */ -+ if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(bit)) != AR2315_GPIO_CR_I(bit)) -+ return; -+ -+ if (bit >= 0) -+ do_IRQ(AR531X_GPIO_IRQ_BASE + bit); -+} -+ -+#ifdef CONFIG_ATHEROS_AR2315_PCI -+static inline void pci_abort_irq(void) -+{ -+ ar231x_write_reg(AR2315_PCI_INT_STATUS, AR2315_PCI_ABORT_INT); -+} -+ -+static inline void pci_ack_irq(void) -+{ -+ ar231x_write_reg(AR2315_PCI_INT_STATUS, AR2315_PCI_EXT_INT); -+} -+ -+void ar2315_pci_irq(int irq) -+{ -+ if (ar231x_read_reg(AR2315_PCI_INT_STATUS) == AR2315_PCI_ABORT_INT) -+ pci_abort_irq(); -+ else { -+ do_IRQ(irq); -+ pci_ack_irq(); -+ } -+} -+#endif /* CONFIG_ATHEROS_AR2315_PCI */ -+ -+/* -+ * Called when an interrupt is received, this function -+ * determines exactly which interrupt it was, and it -+ * invokes the appropriate handler. -+ * -+ * Implicitly, we also define interrupt priority by -+ * choosing which to dispatch first. -+ */ -+static asmlinkage void -+ar2315_irq_dispatch(void) -+{ -+ int pending = read_c0_status() & read_c0_cause(); -+ -+ if (pending & CAUSEF_IP3) -+ do_IRQ(AR2315_IRQ_WLAN0_INTRS); -+ else if (pending & CAUSEF_IP4) -+ do_IRQ(AR2315_IRQ_ENET0_INTRS); -+#ifdef CONFIG_ATHEROS_AR2315_PCI -+ else if (pending & CAUSEF_IP5) -+ ar2315_pci_irq(AR2315_IRQ_LCBUS_PCI); -+#endif -+ else if (pending & CAUSEF_IP2) { -+ unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) & ar231x_read_reg(AR2315_IMR); -+ -+ if (misc_intr & AR2315_ISR_SPI) -+ do_IRQ(AR531X_MISC_IRQ_SPI); -+ else if (misc_intr & AR2315_ISR_TIMER) -+ do_IRQ(AR531X_MISC_IRQ_TIMER); -+ else if (misc_intr & AR2315_ISR_AHB) -+ do_IRQ(AR531X_MISC_IRQ_AHB_PROC); -+ else if (misc_intr & AR2315_ISR_GPIO) -+ ar2315_gpio_irq(); -+ else if (misc_intr & AR2315_ISR_UART0) -+ do_IRQ(AR531X_MISC_IRQ_UART0); -+ else if (misc_intr & AR2315_ISR_WD) -+ do_IRQ(AR531X_MISC_IRQ_WATCHDOG); -+ else -+ do_IRQ(AR531X_MISC_IRQ_NONE); -+ } else if (pending & CAUSEF_IP7) -+ do_IRQ(AR531X_IRQ_CPU_CLOCK); -+} -+ -+static void ar2315_set_gpiointmask(int gpio, int level) -+{ -+ u32 reg; -+ -+ reg = ar231x_read_reg(AR2315_GPIO_INT); -+ reg &= ~(AR2315_GPIO_INT_M | AR2315_GPIO_INT_LVL_M); -+ reg |= gpio | AR2315_GPIO_INT_LVL(level); -+ ar231x_write_reg(AR2315_GPIO_INT, reg); -+} -+ -+static void ar2315_gpio_intr_enable(struct irq_data *d) -+{ -+ unsigned int gpio = d->irq - AR531X_GPIO_IRQ_BASE; -+ -+ /* Enable interrupt with edge detection */ -+ if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(gpio)) != AR2315_GPIO_CR_I(gpio)) -+ return; -+ -+ gpiointmask |= (1 << gpio); -+ ar2315_set_gpiointmask(gpio, 3); -+} -+ -+static void ar2315_gpio_intr_disable(struct irq_data *d) -+{ -+ unsigned int gpio = d->irq - AR531X_GPIO_IRQ_BASE; -+ -+ /* Disable interrupt */ -+ gpiointmask &= ~(1 << gpio); -+ ar2315_set_gpiointmask(gpio, 0); -+} -+ -+static struct irq_chip ar2315_gpio_intr_controller = { -+ .name = "AR2315-GPIO", -+ .irq_ack = ar2315_gpio_intr_disable, -+ .irq_mask_ack = ar2315_gpio_intr_disable, -+ .irq_mask = ar2315_gpio_intr_disable, -+ .irq_unmask = ar2315_gpio_intr_enable, -+}; -+ -+static void -+ar2315_misc_intr_enable(struct irq_data *d) -+{ -+ unsigned int imr; -+ -+ imr = ar231x_read_reg(AR2315_IMR); -+ switch(d->irq) { -+ case AR531X_MISC_IRQ_SPI: -+ imr |= AR2315_ISR_SPI; -+ break; -+ case AR531X_MISC_IRQ_TIMER: -+ imr |= AR2315_ISR_TIMER; -+ break; -+ case AR531X_MISC_IRQ_AHB_PROC: -+ imr |= AR2315_ISR_AHB; -+ break; -+ case AR531X_MISC_IRQ_GPIO: -+ imr |= AR2315_ISR_GPIO; -+ break; -+ case AR531X_MISC_IRQ_UART0: -+ imr |= AR2315_ISR_UART0; -+ break; -+ case AR531X_MISC_IRQ_WATCHDOG: -+ imr |= AR2315_ISR_WD; -+ break; -+ default: -+ break; -+ } -+ ar231x_write_reg(AR2315_IMR, imr); -+} -+ -+static void -+ar2315_misc_intr_disable(struct irq_data *d) -+{ -+ unsigned int imr; -+ -+ imr = ar231x_read_reg(AR2315_IMR); -+ switch(d->irq) { -+ case AR531X_MISC_IRQ_SPI: -+ imr &= ~AR2315_ISR_SPI; -+ break; -+ case AR531X_MISC_IRQ_TIMER: -+ imr &= ~AR2315_ISR_TIMER; -+ break; -+ case AR531X_MISC_IRQ_AHB_PROC: -+ imr &= ~AR2315_ISR_AHB; -+ break; -+ case AR531X_MISC_IRQ_GPIO: -+ imr &= ~AR2315_ISR_GPIO; -+ break; -+ case AR531X_MISC_IRQ_UART0: -+ imr &= ~AR2315_ISR_UART0; -+ break; -+ case AR531X_MISC_IRQ_WATCHDOG: -+ imr &= ~AR2315_ISR_WD; -+ break; -+ default: -+ break; -+ } -+ ar231x_write_reg(AR2315_IMR, imr); -+} -+ -+ -+static struct irq_chip ar2315_misc_intr_controller = { -+ .name = "AR2315-MISC", -+ .irq_mask = ar2315_misc_intr_disable, -+ .irq_unmask = ar2315_misc_intr_enable, -+}; -+ -+static irqreturn_t ar2315_ahb_proc_handler(int cpl, void *dev_id) -+{ -+ ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET); -+ ar231x_read_reg(AR2315_AHB_ERR1); -+ -+ printk(KERN_ERR "AHB fatal error\n"); -+ machine_restart("AHB error"); /* Catastrophic failure */ -+ -+ return IRQ_HANDLED; -+} -+ -+static struct irqaction ar2315_ahb_proc_interrupt = { -+ .handler = ar2315_ahb_proc_handler, -+ .flags = IRQF_DISABLED, -+ .name = "ar2315_ahb_proc_interrupt", -+}; -+ -+static struct irqaction cascade = { -+ .handler = no_action, -+ .flags = IRQF_DISABLED, -+ .name = "cascade", -+}; -+ -+void -+ar2315_irq_init(void) -+{ -+ int i; -+ -+ if (!is_2315()) -+ return; -+ -+ ar231x_irq_dispatch = ar2315_irq_dispatch; -+ gpiointval = ar231x_read_reg(AR2315_GPIO_DI); -+ for (i = 0; i < AR531X_MISC_IRQ_COUNT; i++) { -+ int irq = AR531X_MISC_IRQ_BASE + i; -+ irq_set_chip_and_handler(irq, &ar2315_misc_intr_controller, -+ handle_level_irq); -+ } -+ for (i = 0; i < AR531X_GPIO_IRQ_COUNT; i++) { -+ int irq = AR531X_GPIO_IRQ_BASE + i; -+ irq_set_chip_and_handler(irq, &ar2315_gpio_intr_controller, -+ handle_level_irq); -+ } -+ setup_irq(AR531X_MISC_IRQ_GPIO, &cascade); -+ setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar2315_ahb_proc_interrupt); -+ setup_irq(AR2315_IRQ_MISC_INTRS, &cascade); -+} -+ -+const struct ar231x_gpiodev ar2315_gpiodev; -+ -+static u32 -+ar2315_gpio_get_output(void) -+{ -+ u32 reg; -+ reg = ar231x_read_reg(AR2315_GPIO_CR); -+ reg &= ar2315_gpiodev.valid_mask; -+ return reg; -+} -+ -+static u32 -+ar2315_gpio_set_output(u32 mask, u32 val) -+{ -+ u32 reg; -+ -+ reg = ar231x_read_reg(AR2315_GPIO_CR); -+ reg &= ~mask; -+ reg |= val; -+ ar231x_write_reg(AR2315_GPIO_CR, reg); -+ return reg; -+} -+ -+static u32 -+ar2315_gpio_get(void) -+{ -+ u32 reg; -+ reg = ar231x_read_reg(AR2315_GPIO_DI); -+ reg &= ar2315_gpiodev.valid_mask; -+ return reg; -+} -+ -+static u32 -+ar2315_gpio_set(u32 mask, u32 value) -+{ -+ u32 reg; -+ reg = ar231x_read_reg(AR2315_GPIO_DO); -+ reg &= ~mask; -+ reg |= value; -+ ar231x_write_reg(AR2315_GPIO_DO, reg); -+ return reg; -+} -+ -+const struct ar231x_gpiodev ar2315_gpiodev = { -+ .valid_mask = (1 << 22) - 1, -+ .get_output = ar2315_gpio_get_output, -+ .set_output = ar2315_gpio_set_output, -+ .get = ar2315_gpio_get, -+ .set = ar2315_gpio_set, -+}; -+ -+static struct ar231x_eth ar2315_eth_data = { -+ .reset_base = AR2315_RESET, -+ .reset_mac = AR2315_RESET_ENET0, -+ .reset_phy = AR2315_RESET_EPHY0, -+ .phy_base = KSEG1ADDR(AR2315_ENET0), -+ .config = &ar231x_board, -+}; -+ -+static struct resource ar2315_spiflash_res[] = { -+ { -+ .name = "flash_base", -+ .flags = IORESOURCE_MEM, -+ .start = KSEG1ADDR(AR2315_SPI_READ), -+ .end = KSEG1ADDR(AR2315_SPI_READ) + 0x1000000 - 1, -+ }, -+ { -+ .name = "flash_regs", -+ .flags = IORESOURCE_MEM, -+ .start = 0x11300000, -+ .end = 0x11300012, -+ }, -+}; -+ -+static struct platform_device ar2315_spiflash = { -+ .id = 0, -+ .name = "spiflash", -+ .resource = ar2315_spiflash_res, -+ .num_resources = ARRAY_SIZE(ar2315_spiflash_res) -+}; -+ -+static struct platform_device ar2315_wdt = { -+ .id = 0, -+ .name = "ar2315_wdt", -+}; -+ -+#define SPI_FLASH_CTL 0x00 -+#define SPI_FLASH_OPCODE 0x04 -+#define SPI_FLASH_DATA 0x08 -+ -+static inline u32 -+spiflash_read_reg(int reg) -+{ -+ return ar231x_read_reg(AR2315_SPI + reg); -+} -+ -+static inline void -+spiflash_write_reg(int reg, u32 data) -+{ -+ ar231x_write_reg(AR2315_SPI + reg, data); -+} -+ -+static u32 -+spiflash_wait_status(void) -+{ -+ u32 reg; -+ -+ do { -+ reg = spiflash_read_reg(SPI_FLASH_CTL); -+ } while (reg & SPI_CTL_BUSY); -+ -+ return reg; -+} -+ -+static u8 -+spiflash_probe(void) -+{ -+ u32 reg; -+ -+ reg = spiflash_wait_status(); -+ reg &= ~SPI_CTL_TX_RX_CNT_MASK; -+ reg |= (1 << 4) | 4 | SPI_CTL_START; -+ -+ spiflash_write_reg(SPI_FLASH_OPCODE, 0xab); -+ spiflash_write_reg(SPI_FLASH_CTL, reg); -+ -+ reg = spiflash_wait_status(); -+ reg = spiflash_read_reg(SPI_FLASH_DATA); -+ reg &= 0xff; -+ -+ return (u8) reg; -+} -+ -+ -+#define STM_8MBIT_SIGNATURE 0x13 -+#define STM_16MBIT_SIGNATURE 0x14 -+#define STM_32MBIT_SIGNATURE 0x15 -+#define STM_64MBIT_SIGNATURE 0x16 -+#define STM_128MBIT_SIGNATURE 0x17 -+ -+static u8 __init * -+ar2315_flash_limit(void) -+{ -+ u32 flash_size = 0; -+ -+ /* probe the flash chip size */ -+ switch(spiflash_probe()) { -+ case STM_8MBIT_SIGNATURE: -+ flash_size = 0x00100000; -+ break; -+ case STM_16MBIT_SIGNATURE: -+ flash_size = 0x00200000; -+ break; -+ case STM_32MBIT_SIGNATURE: -+ flash_size = 0x00400000; -+ break; -+ case STM_64MBIT_SIGNATURE: -+ flash_size = 0x00800000; -+ break; -+ case STM_128MBIT_SIGNATURE: -+ flash_size = 0x01000000; -+ break; -+ } -+ -+ ar2315_spiflash_res[0].end = ar2315_spiflash_res[0].start + -+ flash_size - 1; -+ return (u8 *) ar2315_spiflash_res[0].end + 1; -+} -+ -+#ifdef CONFIG_LEDS_GPIO -+static struct gpio_led ar2315_leds[6]; -+static struct gpio_led_platform_data ar2315_led_data = { -+ .leds = (void *) ar2315_leds, -+}; -+ -+static struct platform_device ar2315_gpio_leds = { -+ .name = "leds-gpio", -+ .id = -1, -+ .dev = { -+ .platform_data = (void *) &ar2315_led_data, -+ } -+}; -+ -+static void __init -+ar2315_init_gpio(void) -+{ -+ static char led_names[6][6]; -+ int i, led = 0; -+ -+ ar2315_led_data.num_leds = 0; -+ for(i = 1; i < 8; i++) -+ { -+ if((i == AR2315_RESET_GPIO) || -+ (i == ar231x_board.config->resetConfigGpio)) -+ continue; -+ -+ if(i == ar231x_board.config->sysLedGpio) -+ strcpy(led_names[led], "wlan"); -+ else -+ sprintf(led_names[led], "gpio%d", i); -+ -+ ar2315_leds[led].name = led_names[led]; -+ ar2315_leds[led].gpio = i; -+ ar2315_leds[led].active_low = 0; -+ led++; -+ } -+ ar2315_led_data.num_leds = led; -+ platform_device_register(&ar2315_gpio_leds); -+} -+#else -+static inline void ar2315_init_gpio(void) -+{ -+} -+#endif -+ -+int __init -+ar2315_init_devices(void) -+{ -+ if (!is_2315()) -+ return 0; -+ -+ /* Find board configuration */ -+ ar231x_find_config(ar2315_flash_limit()); -+ ar2315_eth_data.macaddr = ar231x_board.config->enet0_mac; -+ -+ ar2315_init_gpio(); -+ platform_device_register(&ar2315_wdt); -+ platform_device_register(&ar2315_spiflash); -+ ar231x_add_ethernet(0, KSEG1ADDR(AR2315_ENET0), AR2315_IRQ_ENET0_INTRS, -+ &ar2315_eth_data); -+ ar231x_add_wmac(0, AR2315_WLAN0, AR2315_IRQ_WLAN0_INTRS); -+ -+ return 0; -+} -+ -+static void -+ar2315_restart(char *command) -+{ -+ void (*mips_reset_vec)(void) = (void *) 0xbfc00000; -+ -+ local_irq_disable(); -+ -+ /* try reset the system via reset control */ -+ ar231x_write_reg(AR2315_COLD_RESET,AR2317_RESET_SYSTEM); -+ -+ /* Cold reset does not work on the AR2315/6, use the GPIO reset bits a workaround. -+ * give it some time to attempt a gpio based hardware reset -+ * (atheros reference design workaround) */ -+ gpio_direction_output(AR2315_RESET_GPIO, 0); -+ mdelay(100); -+ -+ /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic -+ * workaround. Attempt to jump to the mips reset location - -+ * the boot loader itself might be able to recover the system */ -+ mips_reset_vec(); -+} -+ -+ -+/* -+ * This table is indexed by bits 5..4 of the CLOCKCTL1 register -+ * to determine the predevisor value. -+ */ -+static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = { 1, 2, 4, 5 }; -+static int __initdata PLLC_DIVIDE_TABLE[5] = { 2, 3, 4, 6, 3 }; -+ -+static unsigned int __init -+ar2315_sys_clk(unsigned int clockCtl) -+{ -+ unsigned int pllcCtrl,cpuDiv; -+ unsigned int pllcOut,refdiv,fdiv,divby2; -+ unsigned int clkDiv; -+ -+ pllcCtrl = ar231x_read_reg(AR2315_PLLC_CTL); -+ refdiv = (pllcCtrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S; -+ refdiv = CLOCKCTL1_PREDIVIDE_TABLE[refdiv]; -+ fdiv = (pllcCtrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S; -+ divby2 = (pllcCtrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S; -+ divby2 += 1; -+ pllcOut = (40000000/refdiv)*(2*divby2)*fdiv; -+ -+ -+ /* clkm input selected */ -+ switch(clockCtl & CPUCLK_CLK_SEL_M) { -+ case 0: -+ case 1: -+ clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKM_DIV_M) >> PLLC_CLKM_DIV_S]; -+ break; -+ case 2: -+ clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKC_DIV_M) >> PLLC_CLKC_DIV_S]; -+ break; -+ default: -+ pllcOut = 40000000; -+ clkDiv = 1; -+ break; -+ } -+ cpuDiv = (clockCtl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S; -+ cpuDiv = cpuDiv * 2 ?: 1; -+ return (pllcOut/(clkDiv * cpuDiv)); -+} -+ -+static inline unsigned int -+ar2315_cpu_frequency(void) -+{ -+ return ar2315_sys_clk(ar231x_read_reg(AR2315_CPUCLK)); -+} -+ -+static inline unsigned int -+ar2315_apb_frequency(void) -+{ -+ return ar2315_sys_clk(ar231x_read_reg(AR2315_AMBACLK)); -+} -+ -+void __init -+ar2315_time_init(void) -+{ -+ if (!is_2315()) -+ return; -+ -+ mips_hpt_frequency = ar2315_cpu_frequency() / 2; -+} -+ -+void __init -+ar2315_prom_init(void) -+{ -+ u32 memsize, memcfg, devid; -+ -+ if (!is_2315()) -+ return; -+ -+ memcfg = ar231x_read_reg(AR2315_MEM_CFG); -+ memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S); -+ memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S); -+ memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S); -+ memsize <<= 3; -+ add_memory_region(0, memsize, BOOT_MEM_RAM); -+ -+ /* Detect the hardware based on the device ID */ -+ devid = ar231x_read_reg(AR2315_SREV) & AR2315_REV_CHIP; -+ switch(devid) { -+ case 0x90: -+ case 0x91: -+ ar231x_devtype = DEV_TYPE_AR2317; -+ break; -+ default: -+ ar231x_devtype = DEV_TYPE_AR2315; -+ break; -+ } -+ ar231x_gpiodev = &ar2315_gpiodev; -+ ar231x_board.devid = devid; -+} -+ -+void __init -+ar2315_plat_setup(void) -+{ -+ u32 config; -+ -+ if (!is_2315()) -+ return; -+ -+ /* Clear any lingering AHB errors */ -+ config = read_c0_config(); -+ write_c0_config(config & ~0x3); -+ ar231x_write_reg(AR2315_AHB_ERR0,AHB_ERROR_DET); -+ ar231x_read_reg(AR2315_AHB_ERR1); -+ ar231x_write_reg(AR2315_WDC, AR2315_WDC_IGNORE_EXPIRATION); -+ -+ _machine_restart = ar2315_restart; -+ ar231x_serial_setup(KSEG1ADDR(AR2315_UART0), ar2315_apb_frequency()); -+} -diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/ar2315.h linux-2.6.39-rc7/arch/mips/ar231x/ar2315.h ---- linux-2.6.39-rc7.orig/arch/mips/ar231x/ar2315.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/ar231x/ar2315.h 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,37 @@ -+#ifndef __AR2315_H -+#define __AR2315_H -+ -+#ifdef CONFIG_ATHEROS_AR2315 -+ -+extern void ar2315_irq_init(void); -+extern int ar2315_init_devices(void); -+extern void ar2315_prom_init(void); -+extern void ar2315_plat_setup(void); -+extern void ar2315_time_init(void); -+ -+#else -+ -+static inline void ar2315_irq_init(void) -+{ -+} -+ -+static inline int ar2315_init_devices(void) -+{ -+ return 0; -+} -+ -+static inline void ar2315_prom_init(void) -+{ -+} -+ -+static inline void ar2315_plat_setup(void) -+{ -+} -+ -+static inline void ar2315_time_init(void) -+{ -+} -+ -+#endif -+ -+#endif -diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/ar5312.c linux-2.6.39-rc7/arch/mips/ar231x/ar5312.c ---- linux-2.6.39-rc7.orig/arch/mips/ar231x/ar5312.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/ar231x/ar5312.c 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,538 @@ -+/* -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. -+ * Copyright (C) 2006 FON Technology, SL. -+ * Copyright (C) 2006 Imre Kaloz -+ * Copyright (C) 2006-2009 Felix Fietkau -+ */ -+ -+/* -+ * Platform devices for Atheros SoCs -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include "devices.h" -+#include "ar5312.h" -+ -+static void -+ar5312_misc_irq_dispatch(void) -+{ -+ unsigned int ar231x_misc_intrs = ar231x_read_reg(AR531X_ISR) & ar231x_read_reg(AR531X_IMR); -+ -+ if (ar231x_misc_intrs & AR531X_ISR_TIMER) { -+ do_IRQ(AR531X_MISC_IRQ_TIMER); -+ (void)ar231x_read_reg(AR531X_TIMER); -+ } else if (ar231x_misc_intrs & AR531X_ISR_AHBPROC) -+ do_IRQ(AR531X_MISC_IRQ_AHB_PROC); -+ else if ((ar231x_misc_intrs & AR531X_ISR_UART0)) -+ do_IRQ(AR531X_MISC_IRQ_UART0); -+ else if (ar231x_misc_intrs & AR531X_ISR_WD) -+ do_IRQ(AR531X_MISC_IRQ_WATCHDOG); -+ else -+ do_IRQ(AR531X_MISC_IRQ_NONE); -+} -+ -+static asmlinkage void -+ar5312_irq_dispatch(void) -+{ -+ int pending = read_c0_status() & read_c0_cause(); -+ -+ if (pending & CAUSEF_IP2) -+ do_IRQ(AR5312_IRQ_WLAN0_INTRS); -+ else if (pending & CAUSEF_IP3) -+ do_IRQ(AR5312_IRQ_ENET0_INTRS); -+ else if (pending & CAUSEF_IP4) -+ do_IRQ(AR5312_IRQ_ENET1_INTRS); -+ else if (pending & CAUSEF_IP5) -+ do_IRQ(AR5312_IRQ_WLAN1_INTRS); -+ else if (pending & CAUSEF_IP6) -+ ar5312_misc_irq_dispatch(); -+ else if (pending & CAUSEF_IP7) -+ do_IRQ(AR531X_IRQ_CPU_CLOCK); -+} -+ -+ -+/* Enable the specified AR531X_MISC_IRQ interrupt */ -+static void -+ar5312_misc_intr_enable(struct irq_data *d) -+{ -+ unsigned int imr; -+ -+ imr = ar231x_read_reg(AR531X_IMR); -+ imr |= (1 << (d->irq - AR531X_MISC_IRQ_BASE - 1)); -+ ar231x_write_reg(AR531X_IMR, imr); -+} -+ -+/* Disable the specified AR531X_MISC_IRQ interrupt */ -+static void -+ar5312_misc_intr_disable(struct irq_data *d) -+{ -+ unsigned int imr; -+ -+ imr = ar231x_read_reg(AR531X_IMR); -+ imr &= ~(1 << (d->irq - AR531X_MISC_IRQ_BASE - 1)); -+ ar231x_write_reg(AR531X_IMR, imr); -+ ar231x_read_reg(AR531X_IMR); /* flush write buffer */ -+} -+ -+static struct irq_chip ar5312_misc_intr_controller = { -+ .name = "AR5312-MISC", -+ .irq_mask = ar5312_misc_intr_disable, -+ .irq_unmask = ar5312_misc_intr_enable, -+}; -+ -+ -+static irqreturn_t ar5312_ahb_proc_handler(int cpl, void *dev_id) -+{ -+ u32 proc1 = ar231x_read_reg(AR531X_PROC1); -+ u32 procAddr = ar231x_read_reg(AR531X_PROCADDR); /* clears error state */ -+ u32 dma1 = ar231x_read_reg(AR531X_DMA1); -+ u32 dmaAddr = ar231x_read_reg(AR531X_DMAADDR); /* clears error state */ -+ -+ printk("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n", -+ procAddr, proc1, dmaAddr, dma1); -+ -+ machine_restart("AHB error"); /* Catastrophic failure */ -+ return IRQ_HANDLED; -+} -+ -+ -+static struct irqaction ar5312_ahb_proc_interrupt = { -+ .handler = ar5312_ahb_proc_handler, -+ .flags = IRQF_DISABLED, -+ .name = "ar5312_ahb_proc_interrupt", -+}; -+ -+ -+static struct irqaction cascade = { -+ .handler = no_action, -+ .flags = IRQF_DISABLED, -+ .name = "cascade", -+}; -+ -+void __init ar5312_irq_init(void) -+{ -+ int i; -+ -+ if (!is_5312()) -+ return; -+ -+ ar231x_irq_dispatch = ar5312_irq_dispatch; -+ for (i = 0; i < AR531X_MISC_IRQ_COUNT; i++) { -+ int irq = AR531X_MISC_IRQ_BASE + i; -+ irq_set_chip_and_handler(irq, &ar5312_misc_intr_controller, -+ handle_level_irq); -+ } -+ setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt); -+ setup_irq(AR5312_IRQ_MISC_INTRS, &cascade); -+} -+ -+const struct ar231x_gpiodev ar5312_gpiodev; -+ -+static u32 -+ar5312_gpio_get_output(void) -+{ -+ u32 reg; -+ reg = ~(ar231x_read_reg(AR531X_GPIO_CR)); -+ reg &= ar5312_gpiodev.valid_mask; -+ return reg; -+} -+ -+static u32 -+ar5312_gpio_set_output(u32 mask, u32 val) -+{ -+ u32 reg; -+ -+ reg = ar231x_read_reg(AR531X_GPIO_CR); -+ reg |= mask; -+ reg &= ~val; -+ ar231x_write_reg(AR531X_GPIO_CR, reg); -+ return reg; -+} -+ -+static u32 -+ar5312_gpio_get(void) -+{ -+ u32 reg; -+ reg = ar231x_read_reg(AR531X_GPIO_DI); -+ reg &= ar5312_gpiodev.valid_mask; -+ return reg; -+} -+ -+static u32 -+ar5312_gpio_set(u32 mask, u32 value) -+{ -+ u32 reg; -+ reg = ar231x_read_reg(AR531X_GPIO_DO); -+ reg &= ~mask; -+ reg |= value; -+ ar231x_write_reg(AR531X_GPIO_DO, reg); -+ return reg; -+} -+ -+const struct ar231x_gpiodev ar5312_gpiodev = { -+ .valid_mask = (1 << 8) - 1, -+ .get_output = ar5312_gpio_get_output, -+ .set_output = ar5312_gpio_set_output, -+ .get = ar5312_gpio_get, -+ .set = ar5312_gpio_set, -+}; -+ -+static struct physmap_flash_data ar5312_flash_data = { -+ .width = 2, -+}; -+ -+static struct resource ar5312_flash_resource = { -+ .start = AR531X_FLASH, -+ .end = AR531X_FLASH + 0x800000 - 1, -+ .flags = IORESOURCE_MEM, -+}; -+ -+static struct ar231x_eth ar5312_eth0_data = { -+ .reset_base = AR531X_RESET, -+ .reset_mac = AR531X_RESET_ENET0, -+ .reset_phy = AR531X_RESET_EPHY0, -+ .phy_base = KSEG1ADDR(AR531X_ENET0), -+ .config = &ar231x_board, -+}; -+ -+static struct ar231x_eth ar5312_eth1_data = { -+ .reset_base = AR531X_RESET, -+ .reset_mac = AR531X_RESET_ENET1, -+ .reset_phy = AR531X_RESET_EPHY1, -+ .phy_base = KSEG1ADDR(AR531X_ENET1), -+ .config = &ar231x_board, -+}; -+ -+static struct platform_device ar5312_physmap_flash = { -+ .name = "physmap-flash", -+ .id = 0, -+ .dev.platform_data = &ar5312_flash_data, -+ .resource = &ar5312_flash_resource, -+ .num_resources = 1, -+}; -+ -+#ifdef CONFIG_LEDS_GPIO -+static struct gpio_led ar5312_leds[] = { -+ { .name = "wlan", .gpio = 0, .active_low = 1, }, -+}; -+ -+static const struct gpio_led_platform_data ar5312_led_data = { -+ .num_leds = ARRAY_SIZE(ar5312_leds), -+ .leds = (void *) ar5312_leds, -+}; -+ -+static struct platform_device ar5312_gpio_leds = { -+ .name = "leds-gpio", -+ .id = -1, -+ .dev.platform_data = (void *) &ar5312_led_data, -+}; -+#endif -+ -+/* -+ * NB: This mapping size is larger than the actual flash size, -+ * but this shouldn't be a problem here, because the flash -+ * will simply be mapped multiple times. -+ */ -+static char __init *ar5312_flash_limit(void) -+{ -+ u32 ctl; -+ /* -+ * Configure flash bank 0. -+ * Assume 8M window size. Flash will be aliased if it's smaller -+ */ -+ ctl = FLASHCTL_E | -+ FLASHCTL_AC_8M | -+ FLASHCTL_RBLE | -+ (0x01 << FLASHCTL_IDCY_S) | -+ (0x07 << FLASHCTL_WST1_S) | -+ (0x07 << FLASHCTL_WST2_S) | -+ (ar231x_read_reg(AR531X_FLASHCTL0) & FLASHCTL_MW); -+ -+ ar231x_write_reg(AR531X_FLASHCTL0, ctl); -+ -+ /* Disable other flash banks */ -+ ar231x_write_reg(AR531X_FLASHCTL1, -+ ar231x_read_reg(AR531X_FLASHCTL1) & ~(FLASHCTL_E | FLASHCTL_AC)); -+ -+ ar231x_write_reg(AR531X_FLASHCTL2, -+ ar231x_read_reg(AR531X_FLASHCTL2) & ~(FLASHCTL_E | FLASHCTL_AC)); -+ -+ return (char *) KSEG1ADDR(AR531X_FLASH + 0x800000); -+} -+ -+int __init ar5312_init_devices(void) -+{ -+ struct ar231x_boarddata *config; -+ u32 fctl = 0; -+ const u8 *radio; -+ u8 *c; -+ -+ if (!is_5312()) -+ return 0; -+ -+ /* Locate board/radio config data */ -+ ar231x_find_config(ar5312_flash_limit()); -+ config = ar231x_board.config; -+ -+ -+ /* -+ * Chip IDs and hardware detection for some Atheros -+ * models are really broken! -+ * -+ * Atheros uses a disabled WMAC0 and Silicon ID of AR5312 -+ * as indication for AR2312, which is otherwise -+ * indistinguishable from the real AR5312. -+ */ -+ if (ar231x_board.radio) { -+ radio = ar231x_board.radio + AR531X_RADIO_MASK_OFF; -+ if ((*((const u32 *) radio) & AR531X_RADIO0_MASK) == 0) -+ config->flags |= BD_ISCASPER; -+ } else -+ radio = NULL; -+ -+ /* AR2313 has CPU minor rev. 10 */ -+ if ((current_cpu_data.processor_id & 0xff) == 0x0a) -+ ar231x_devtype = DEV_TYPE_AR2313; -+ -+ /* AR2312 shares the same Silicon ID as AR5312 */ -+ else if (config->flags & BD_ISCASPER) -+ ar231x_devtype = DEV_TYPE_AR2312; -+ -+ /* Everything else is probably AR5312 or compatible */ -+ else -+ ar231x_devtype = DEV_TYPE_AR5312; -+ -+ /* fixup flash width */ -+ fctl = ar231x_read_reg(AR531X_FLASHCTL) & FLASHCTL_MW; -+ switch (fctl) { -+ case FLASHCTL_MWx16: -+ ar5312_flash_data.width = 2; -+ break; -+ case FLASHCTL_MWx8: -+ default: -+ ar5312_flash_data.width = 1; -+ break; -+ } -+ -+ platform_device_register(&ar5312_physmap_flash); -+ -+#ifdef CONFIG_LEDS_GPIO -+ ar5312_leds[0].gpio = config->sysLedGpio; -+ platform_device_register(&ar5312_gpio_leds); -+#endif -+ -+ /* Fix up MAC addresses if necessary */ -+ if (!memcmp(config->enet0_mac, "\xff\xff\xff\xff\xff\xff", 6)) -+ memcpy(config->enet0_mac, config->enet1_mac, 6); -+ -+ /* If ENET0 and ENET1 have the same mac address, -+ * increment the one from ENET1 */ -+ if (memcmp(config->enet0_mac, config->enet1_mac, 6) == 0) { -+ c = config->enet1_mac + 5; -+ while ((c >= config->enet1_mac) && !(++(*c))) -+ c--; -+ } -+ -+ switch(ar231x_devtype) { -+ case DEV_TYPE_AR5312: -+ ar5312_eth0_data.macaddr = config->enet0_mac; -+ ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET0), -+ AR5312_IRQ_ENET0_INTRS, &ar5312_eth0_data); -+ -+ ar5312_eth1_data.macaddr = config->enet1_mac; -+ ar231x_add_ethernet(1, KSEG1ADDR(AR531X_ENET1), -+ AR5312_IRQ_ENET1_INTRS, &ar5312_eth1_data); -+ -+ if (!ar231x_board.radio) -+ return 0; -+ -+ if ((*((u32 *) radio) & AR531X_RADIO0_MASK) && -+ (config->flags & BD_WLAN0)) -+ ar231x_add_wmac(0, AR531X_WLAN0, -+ AR5312_IRQ_WLAN0_INTRS); -+ -+ break; -+ /* -+ * AR2312/3 ethernet uses the PHY of ENET0, but the MAC -+ * of ENET1. Atheros calls it 'twisted' for a reason :) -+ */ -+ case DEV_TYPE_AR2312: -+ case DEV_TYPE_AR2313: -+ ar5312_eth1_data.phy_base = ar5312_eth0_data.phy_base; -+ ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy; -+ ar5312_eth1_data.macaddr = config->enet0_mac; -+ ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET1), -+ AR5312_IRQ_ENET1_INTRS, &ar5312_eth1_data); -+ -+ if (!ar231x_board.radio) -+ return 0; -+ break; -+ default: -+ break; -+ } -+ -+ if ((*((u32 *) radio) & AR531X_RADIO1_MASK) && -+ (config->flags & BD_WLAN1)) -+ ar231x_add_wmac(1, AR531X_WLAN1, -+ AR5312_IRQ_WLAN1_INTRS); -+ -+ return 0; -+} -+ -+ -+static void ar5312_restart(char *command) -+{ -+ /* reset the system */ -+ local_irq_disable(); -+ while(1) { -+ ar231x_write_reg(AR531X_RESET, AR531X_RESET_SYSTEM); -+ } -+} -+ -+ -+/* -+ * This table is indexed by bits 5..4 of the CLOCKCTL1 register -+ * to determine the predevisor value. -+ */ -+static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = { 1, 2, 4, 5 }; -+ -+ -+static int __init -+ar5312_cpu_frequency(void) -+{ -+ unsigned int result; -+ unsigned int predivide_mask, predivide_shift; -+ unsigned int multiplier_mask, multiplier_shift; -+ unsigned int clockCtl1, preDivideSelect, preDivisor, multiplier; -+ unsigned int doubler_mask; -+ u16 devid; -+ -+ /* Trust the bootrom's idea of cpu frequency. */ -+ if ((result = ar231x_read_reg(AR5312_SCRATCH))) -+ return result; -+ -+ devid = ar231x_read_reg(AR531X_REV); -+ devid &= AR531X_REV_MAJ; -+ devid >>= AR531X_REV_MAJ_S; -+ if (devid == AR531X_REV_MAJ_AR2313) { -+ predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK; -+ predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT; -+ multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK; -+ multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT; -+ doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK; -+ } else { /* AR5312 and AR2312 */ -+ predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK; -+ predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT; -+ multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK; -+ multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT; -+ doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK; -+ } -+ -+ /* -+ * Clocking is derived from a fixed 40MHz input clock. -+ * -+ * cpuFreq = InputClock * MULT (where MULT is PLL multiplier) -+ * sysFreq = cpuFreq / 4 (used for APB clock, serial, -+ * flash, Timer, Watchdog Timer) -+ * -+ * cntFreq = cpuFreq / 2 (use for CPU count/compare) -+ * -+ * So, for example, with a PLL multiplier of 5, we have -+ * -+ * cpuFreq = 200MHz -+ * sysFreq = 50MHz -+ * cntFreq = 100MHz -+ * -+ * We compute the CPU frequency, based on PLL settings. -+ */ -+ -+ clockCtl1 = ar231x_read_reg(AR5312_CLOCKCTL1); -+ preDivideSelect = (clockCtl1 & predivide_mask) >> predivide_shift; -+ preDivisor = CLOCKCTL1_PREDIVIDE_TABLE[preDivideSelect]; -+ multiplier = (clockCtl1 & multiplier_mask) >> multiplier_shift; -+ -+ if (clockCtl1 & doubler_mask) { -+ multiplier = multiplier << 1; -+ } -+ return (40000000 / preDivisor) * multiplier; -+} -+ -+static inline int -+ar5312_sys_frequency(void) -+{ -+ return ar5312_cpu_frequency() / 4; -+} -+ -+void __init -+ar5312_time_init(void) -+{ -+ if (!is_5312()) -+ return; -+ -+ mips_hpt_frequency = ar5312_cpu_frequency() / 2; -+} -+ -+ -+void __init -+ar5312_prom_init(void) -+{ -+ u32 memsize, memcfg, bank0AC, bank1AC; -+ u32 devid; -+ -+ if (!is_5312()) -+ return; -+ -+ /* Detect memory size */ -+ memcfg = ar231x_read_reg(AR531X_MEM_CFG1); -+ bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S; -+ bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S; -+ memsize = (bank0AC ? (1 << (bank0AC+1)) : 0) -+ + (bank1AC ? (1 << (bank1AC+1)) : 0); -+ memsize <<= 20; -+ add_memory_region(0, memsize, BOOT_MEM_RAM); -+ -+ devid = ar231x_read_reg(AR531X_REV); -+ devid >>= AR531X_REV_WMAC_MIN_S; -+ devid &= AR531X_REV_CHIP; -+ ar231x_board.devid = (u16) devid; -+ ar231x_gpiodev = &ar5312_gpiodev; -+} -+ -+void __init -+ar5312_plat_setup(void) -+{ -+ if (!is_5312()) -+ return; -+ -+ /* Clear any lingering AHB errors */ -+ ar231x_read_reg(AR531X_PROCADDR); -+ ar231x_read_reg(AR531X_DMAADDR); -+ ar231x_write_reg(AR531X_WD_CTRL, AR531X_WD_CTRL_IGNORE_EXPIRATION); -+ -+ _machine_restart = ar5312_restart; -+ ar231x_serial_setup(KSEG1ADDR(AR531X_UART0), ar5312_sys_frequency()); -+} -+ -diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/ar5312.h linux-2.6.39-rc7/arch/mips/ar231x/ar5312.h ---- linux-2.6.39-rc7.orig/arch/mips/ar231x/ar5312.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/ar231x/ar5312.h 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,38 @@ -+#ifndef __AR5312_H -+#define __AR5312_H -+ -+#ifdef CONFIG_ATHEROS_AR5312 -+ -+extern void ar5312_irq_init(void); -+extern int ar5312_init_devices(void); -+extern void ar5312_prom_init(void); -+extern void ar5312_plat_setup(void); -+extern void ar5312_time_init(void); -+extern void ar5312_time_init(void); -+ -+#else -+ -+static inline void ar5312_irq_init(void) -+{ -+} -+ -+static inline int ar5312_init_devices(void) -+{ -+ return 0; -+} -+ -+static inline void ar5312_prom_init(void) -+{ -+} -+ -+static inline void ar5312_plat_setup(void) -+{ -+} -+ -+static inline void ar5312_time_init(void) -+{ -+} -+ -+#endif -+ -+#endif -diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/board.c linux-2.6.39-rc7/arch/mips/ar231x/board.c ---- linux-2.6.39-rc7.orig/arch/mips/ar231x/board.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/ar231x/board.c 2011-05-15 22:16:11.000000000 +0200 -@@ -0,0 +1,261 @@ -+/* -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. -+ * Copyright (C) 2006 FON Technology, SL. -+ * Copyright (C) 2006 Imre Kaloz -+ * Copyright (C) 2006-2009 Felix Fietkau -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include "devices.h" -+#include "ar5312.h" -+#include "ar2315.h" -+ -+void (*ar231x_irq_dispatch)(void); -+ -+static inline bool -+check_radio_magic(u8 *addr) -+{ -+ addr += 0x7a; /* offset for flash magic */ -+ if ((addr[0] == 0x5a) && (addr[1] == 0xa5)) { -+ return 1; -+ } -+ return 0; -+} -+ -+static inline bool -+check_board_data(u8 *flash_limit, u8 *addr, bool broken) -+{ -+ /* config magic found */ -+ if (*((u32 *)addr) == AR531X_BD_MAGIC) -+ return 1; -+ -+ if (!broken) -+ return 0; -+ -+ if (check_radio_magic(addr + 0xf8)) -+ ar231x_board.radio = addr + 0xf8; -+ if ((addr < flash_limit + 0x10000) && -+ check_radio_magic(addr + 0x10000)) -+ ar231x_board.radio = addr + 0x10000; -+ -+ if (ar231x_board.radio) { -+ /* broken board data detected, use radio data to find the offset, -+ * user will fix this */ -+ return 1; -+ } -+ return 0; -+} -+ -+static u8 * -+find_board_config(u8 *flash_limit, bool broken) -+{ -+ u8 *addr; -+ int found = 0; -+ -+ for (addr = flash_limit - 0x1000; -+ addr >= flash_limit - 0x30000; -+ addr -= 0x1000) { -+ -+ if (check_board_data(flash_limit, addr, broken)) { -+ found = 1; -+ break; -+ } -+ } -+ -+ if (!found) -+ addr = NULL; -+ -+ return addr; -+} -+ -+static u8 * -+find_radio_config(u8 *flash_limit, u8 *board_config) -+{ -+ int found; -+ u8 *radio_config; -+ -+ /* -+ * Now find the start of Radio Configuration data, using heuristics: -+ * Search forward from Board Configuration data by 0x1000 bytes -+ * at a time until we find non-0xffffffff. -+ */ -+ found = 0; -+ for (radio_config = board_config + 0x1000; -+ (radio_config < flash_limit); -+ radio_config += 0x1000) { -+ if ((*(u32 *)radio_config != 0xffffffff) && -+ check_radio_magic(radio_config)) { -+ found = 1; -+ break; -+ } -+ } -+ -+ /* AR2316 relocates radio config to new location */ -+ if (!found) { -+ for (radio_config = board_config + 0xf8; -+ (radio_config < flash_limit - 0x1000 + 0xf8); -+ radio_config += 0x1000) { -+ if ((*(u32 *)radio_config != 0xffffffff) && -+ check_radio_magic(radio_config)) { -+ found = 1; -+ break; -+ } -+ } -+ } -+ -+ if (!found) { -+ printk("Could not find Radio Configuration data\n"); -+ radio_config = 0; -+ } -+ -+ return (u8 *) radio_config; -+} -+ -+int __init -+ar231x_find_config(u8 *flash_limit) -+{ -+ struct ar231x_boarddata *config; -+ unsigned int rcfg_size; -+ int broken_boarddata = 0, i, tmp; -+ u8 *bcfg, *rcfg; -+ u8 *board_data; -+ u8 *radio_data; -+ u32 offset; -+ -+ ar231x_board.config = NULL; -+ ar231x_board.radio = NULL; -+ /* Copy the board and radio data to RAM, because accessing the mapped -+ * memory of the flash directly after booting is not safe */ -+ -+ /* Try to find valid board and radio data */ -+ bcfg = find_board_config(flash_limit, false); -+ -+ /* If that fails, try to at least find valid radio data */ -+ if (!bcfg) { -+ bcfg = find_board_config(flash_limit, true); -+ broken_boarddata = 1; -+ } -+ -+ if (!bcfg) { -+ printk(KERN_WARNING "WARNING: No board configuration data found!\n"); -+ return -ENODEV; -+ } -+ -+ board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL); -+ ar231x_board.config = (struct ar231x_boarddata *) board_data; -+ memcpy(board_data, bcfg, 0x100); -+ if (broken_boarddata) { -+ printk(KERN_WARNING "WARNING: broken board data detected\n"); -+ config = ar231x_board.config; -+ if (!memcmp(config->enet0_mac, "\x00\x00\x00\x00\x00\x00", 6)) { -+ printk(KERN_INFO "Fixing up empty mac addresses\n"); -+ config->resetConfigGpio = 0xffff; -+ config->sysLedGpio = 0xffff; -+ random_ether_addr(config->wlan0_mac); -+ config->wlan0_mac[0] &= ~0x06; -+ random_ether_addr(config->enet0_mac); -+ random_ether_addr(config->enet1_mac); -+ } -+ } -+ -+ -+ /* Radio config starts 0x100 bytes after board config, regardless -+ * of what the physical layout on the flash chip looks like */ -+ -+ if (ar231x_board.radio) -+ rcfg = (u8 *) ar231x_board.radio; -+ else -+ rcfg = find_radio_config(flash_limit, bcfg); -+ -+ if (!rcfg) -+ return -ENODEV; -+ -+ radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff); -+ ar231x_board.radio = radio_data; -+ offset = radio_data - board_data; -+ printk(KERN_INFO "Radio config found at offset 0x%x(0x%x)\n", rcfg - bcfg, offset); -+ rcfg_size = BOARD_CONFIG_BUFSZ - offset; -+ memcpy(radio_data, rcfg, rcfg_size); -+ -+ for (tmp = 0xff, i = 0; i < ETH_ALEN; i++) -+ tmp &= radio_data[i + 0x1d * 2]; -+ if (tmp == 0xff) { -+ u16 *eep = (u16 *)radio_data, *bcfgs = (u16 *)bcfg; -+ printk(KERN_INFO "Radio MAC is blank; using board-data\n"); -+ eep[0x1f] = bcfgs[0x30]; -+ eep[0x1e] = bcfgs[0x34]; -+ eep[0x1d] = bcfgs[0x32]; -+ } -+ -+ return 0; -+} -+ -+static void -+ar231x_halt(void) -+{ -+ local_irq_disable(); -+ while (1); -+} -+ -+void __init -+plat_mem_setup(void) -+{ -+ _machine_halt = ar231x_halt; -+ pm_power_off = ar231x_halt; -+ -+ ar5312_plat_setup(); -+ ar2315_plat_setup(); -+ -+ /* Disable data watchpoints */ -+ write_c0_watchlo0(0); -+} -+ -+ -+asmlinkage void -+plat_irq_dispatch(void) -+{ -+ ar231x_irq_dispatch(); -+} -+ -+void __init -+plat_time_init(void) -+{ -+ ar5312_time_init(); -+ ar2315_time_init(); -+} -+ -+unsigned int __cpuinit -+get_c0_compare_int(void) -+{ -+ return CP0_LEGACY_COMPARE_IRQ; -+} -+ -+void __init -+arch_init_irq(void) -+{ -+ clear_c0_status(ST0_IM); -+ mips_cpu_irq_init(); -+ -+ /* Initialize interrupt controllers */ -+ ar5312_irq_init(); -+ ar2315_irq_init(); -+} -+ -+ -diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/devices.c linux-2.6.39-rc7/arch/mips/ar231x/devices.c ---- linux-2.6.39-rc7.orig/arch/mips/ar231x/devices.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/ar231x/devices.c 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,175 @@ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "devices.h" -+#include "ar5312.h" -+#include "ar2315.h" -+ -+struct ar231x_board_config ar231x_board; -+int ar231x_devtype = DEV_TYPE_UNKNOWN; -+const struct ar231x_gpiodev *ar231x_gpiodev; -+EXPORT_SYMBOL(ar231x_gpiodev); -+ -+static struct resource ar231x_eth0_res[] = { -+ { -+ .name = "eth0_membase", -+ .flags = IORESOURCE_MEM, -+ }, -+ { -+ .name = "eth0_irq", -+ .flags = IORESOURCE_IRQ, -+ } -+}; -+ -+static struct resource ar231x_eth1_res[] = { -+ { -+ .name = "eth1_membase", -+ .flags = IORESOURCE_MEM, -+ }, -+ { -+ .name = "eth1_irq", -+ .flags = IORESOURCE_IRQ, -+ } -+}; -+ -+static struct platform_device ar231x_eth[] = { -+ { -+ .id = 0, -+ .name = "ar231x-eth", -+ .resource = ar231x_eth0_res, -+ .num_resources = ARRAY_SIZE(ar231x_eth0_res) -+ }, -+ { -+ .id = 1, -+ .name = "ar231x-eth", -+ .resource = ar231x_eth1_res, -+ .num_resources = ARRAY_SIZE(ar231x_eth1_res) -+ } -+}; -+ -+static struct resource ar231x_wmac0_res[] = { -+ { -+ .name = "wmac0_membase", -+ .flags = IORESOURCE_MEM, -+ }, -+ { -+ .name = "wmac0_irq", -+ .flags = IORESOURCE_IRQ, -+ } -+}; -+ -+static struct resource ar231x_wmac1_res[] = { -+ { -+ .name = "wmac1_membase", -+ .flags = IORESOURCE_MEM, -+ }, -+ { -+ .name = "wmac1_irq", -+ .flags = IORESOURCE_IRQ, -+ } -+}; -+ -+ -+static struct platform_device ar231x_wmac[] = { -+ { -+ .id = 0, -+ .name = "ar231x-wmac", -+ .resource = ar231x_wmac0_res, -+ .num_resources = ARRAY_SIZE(ar231x_wmac0_res), -+ .dev.platform_data = &ar231x_board, -+ }, -+ { -+ .id = 1, -+ .name = "ar231x-wmac", -+ .resource = ar231x_wmac1_res, -+ .num_resources = ARRAY_SIZE(ar231x_wmac1_res), -+ .dev.platform_data = &ar231x_board, -+ }, -+}; -+ -+static const char *devtype_strings[] = { -+ [DEV_TYPE_AR5312] = "Atheros AR5312", -+ [DEV_TYPE_AR2312] = "Atheros AR2312", -+ [DEV_TYPE_AR2313] = "Atheros AR2313", -+ [DEV_TYPE_AR2315] = "Atheros AR2315", -+ [DEV_TYPE_AR2316] = "Atheros AR2316", -+ [DEV_TYPE_AR2317] = "Atheros AR2317", -+ [DEV_TYPE_UNKNOWN] = "Atheros (unknown)", -+}; -+ -+const char *get_system_type(void) -+{ -+ if ((ar231x_devtype >= ARRAY_SIZE(devtype_strings)) || -+ !devtype_strings[ar231x_devtype]) -+ return devtype_strings[DEV_TYPE_UNKNOWN]; -+ return devtype_strings[ar231x_devtype]; -+} -+ -+ -+int __init -+ar231x_add_ethernet(int nr, u32 base, int irq, void *pdata) -+{ -+ struct resource *res; -+ -+ ar231x_eth[nr].dev.platform_data = pdata; -+ res = &ar231x_eth[nr].resource[0]; -+ res->start = base; -+ res->end = base + 0x2000 - 1; -+ res++; -+ res->start = irq; -+ res->end = irq; -+ return platform_device_register(&ar231x_eth[nr]); -+} -+ -+void __init -+ar231x_serial_setup(u32 mapbase, unsigned int uartclk) -+{ -+ struct uart_port s; -+ -+ memset(&s, 0, sizeof(s)); -+ -+ s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST; -+ s.iotype = UPIO_MEM; -+ s.irq = AR531X_MISC_IRQ_UART0; -+ s.regshift = 2; -+ s.mapbase = mapbase; -+ s.uartclk = uartclk; -+ s.membase = (void __iomem *)s.mapbase; -+ -+ early_serial_setup(&s); -+} -+ -+int __init -+ar231x_add_wmac(int nr, u32 base, int irq) -+{ -+ struct resource *res; -+ -+ ar231x_wmac[nr].dev.platform_data = &ar231x_board; -+ res = &ar231x_wmac[nr].resource[0]; -+ res->start = base; -+ res->end = base + 0x10000 - 1; -+ res++; -+ res->start = irq; -+ res->end = irq; -+ return platform_device_register(&ar231x_wmac[nr]); -+} -+ -+static int __init ar231x_register_devices(void) -+{ -+ static struct resource res = { -+ .start = 0xFFFFFFFF, -+ }; -+ -+ platform_device_register_simple("GPIODEV", 0, &res, 1); -+ ar5312_init_devices(); -+ ar2315_init_devices(); -+ -+ return 0; -+} -+ -+device_initcall(ar231x_register_devices); -diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/devices.h linux-2.6.39-rc7/arch/mips/ar231x/devices.h ---- linux-2.6.39-rc7.orig/arch/mips/ar231x/devices.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/ar231x/devices.h 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,37 @@ -+#ifndef __AR231X_DEVICES_H -+#define __AR231X_DEVICES_H -+ -+enum { -+ /* handled by ar5312.c */ -+ DEV_TYPE_AR2312, -+ DEV_TYPE_AR2313, -+ DEV_TYPE_AR5312, -+ -+ /* handled by ar2315.c */ -+ DEV_TYPE_AR2315, -+ DEV_TYPE_AR2316, -+ DEV_TYPE_AR2317, -+ -+ DEV_TYPE_UNKNOWN -+}; -+ -+extern int ar231x_devtype; -+extern struct ar231x_board_config ar231x_board; -+extern asmlinkage void (*ar231x_irq_dispatch)(void); -+ -+extern int ar231x_find_config(u8 *flash_limit); -+extern void ar231x_serial_setup(u32 mapbase, unsigned int uartclk); -+extern int ar231x_add_wmac(int nr, u32 base, int irq); -+extern int ar231x_add_ethernet(int nr, u32 base, int irq, void *pdata); -+ -+static inline bool is_2315(void) -+{ -+ return (current_cpu_data.cputype == CPU_4KEC); -+} -+ -+static inline bool is_5312(void) -+{ -+ return !is_2315(); -+} -+ -+#endif -diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/early_printk.c linux-2.6.39-rc7/arch/mips/ar231x/early_printk.c ---- linux-2.6.39-rc7.orig/arch/mips/ar231x/early_printk.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/ar231x/early_printk.c 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,44 @@ -+/* -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 2010 Gabor Juhos -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include "devices.h" -+ -+static inline void prom_uart_wr(void __iomem *base, unsigned reg, -+ unsigned char ch) -+{ -+ __raw_writeb(ch, base + 4 * reg); -+} -+ -+static inline unsigned char prom_uart_rr(void __iomem *base, unsigned reg) -+{ -+ return __raw_readb(base + 4 * reg); -+} -+ -+void prom_putchar(unsigned char ch) -+{ -+ static void __iomem *base; -+ -+ if (unlikely(base == NULL)) { -+ if (is_2315()) -+ base = (void __iomem *)(KSEG1ADDR(AR2315_UART0)); -+ else -+ base = (void __iomem *)(KSEG1ADDR(AR531X_UART0)); -+ } -+ -+ while ((prom_uart_rr(base, UART_LSR) & UART_LSR_THRE) == 0); -+ prom_uart_wr(base, UART_TX, ch); -+ while ((prom_uart_rr(base, UART_LSR) & UART_LSR_THRE) == 0); -+} -+ -diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/pci.c linux-2.6.39-rc7/arch/mips/ar231x/pci.c ---- linux-2.6.39-rc7.orig/arch/mips/ar231x/pci.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/ar231x/pci.c 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,230 @@ -+/* -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "devices.h" -+ -+#define AR531X_MEM_BASE 0x80800000UL -+#define AR531X_MEM_SIZE 0x00ffffffUL -+#define AR531X_IO_SIZE 0x00007fffUL -+ -+static unsigned long configspace; -+ -+static int config_access(int devfn, int where, int size, u32 *ptr, bool write) -+{ -+ unsigned long flags; -+ int func = PCI_FUNC(devfn); -+ int dev = PCI_SLOT(devfn); -+ u32 value = 0; -+ int err = 0; -+ u32 addr; -+ -+ if (((dev != 0) && (dev != 3)) || (func > 2)) -+ return PCIBIOS_DEVICE_NOT_FOUND; -+ -+ /* Select Configuration access */ -+ local_irq_save(flags); -+ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, 0, AR2315_PCIMISC_CFG_SEL); -+ mb(); -+ -+ addr = (u32) configspace + (1 << (13 + dev)) + (func << 8) + where; -+ if (size == 1) -+ addr ^= 0x3; -+ else if (size == 2) -+ addr ^= 0x2; -+ -+ if (write) { -+ value = *ptr; -+ if (size == 1) -+ err = put_dbe(value, (u8 *) addr); -+ else if (size == 2) -+ err = put_dbe(value, (u16 *) addr); -+ else if (size == 4) -+ err = put_dbe(value, (u32 *) addr); -+ } else { -+ if (size == 1) -+ err = get_dbe(value, (u8 *) addr); -+ else if (size == 2) -+ err = get_dbe(value, (u16 *) addr); -+ else if (size == 4) -+ err = get_dbe(value, (u32 *) addr); -+ if (err) -+ *ptr = 0xffffffff; -+ else -+ *ptr = value; -+ } -+ -+ /* Select Memory access */ -+ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_CFG_SEL, 0); -+ local_irq_restore(flags); -+ -+ return (err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL); -+} -+ -+static int ar231x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * value) -+{ -+ return config_access(devfn, where, size, value, 0); -+} -+ -+static int ar231x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value) -+{ -+ return config_access(devfn, where, size, &value, 1); -+} -+ -+struct pci_ops ar231x_pci_ops = { -+ .read = ar231x_pci_read, -+ .write = ar231x_pci_write, -+}; -+ -+static struct resource ar231x_mem_resource = { -+ .name = "AR531x PCI MEM", -+ .start = AR531X_MEM_BASE, -+ .end = AR531X_MEM_BASE + AR531X_MEM_SIZE - AR531X_IO_SIZE - 1 + 0x4000000, -+ .flags = IORESOURCE_MEM, -+}; -+ -+static struct resource ar231x_io_resource = { -+ .name = "AR531x PCI I/O", -+ .start = AR531X_MEM_BASE + AR531X_MEM_SIZE - AR531X_IO_SIZE, -+ .end = AR531X_MEM_BASE + AR531X_MEM_SIZE - 1, -+ .flags = IORESOURCE_IO, -+}; -+ -+struct pci_controller ar231x_pci_controller = { -+ .pci_ops = &ar231x_pci_ops, -+ .mem_resource = &ar231x_mem_resource, -+ .io_resource = &ar231x_io_resource, -+ .mem_offset = 0x00000000UL, -+ .io_offset = 0x00000000UL, -+}; -+ -+int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -+{ -+ return AR2315_IRQ_LCBUS_PCI; -+} -+ -+int pcibios_plat_dev_init(struct pci_dev *dev) -+{ -+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 5); -+ pci_write_config_word(dev, 0x40, 0); -+ -+ /* Clear any pending Abort or external Interrupts -+ * and enable interrupt processing */ -+ ar231x_mask_reg(AR2315_PCI_INTEN_REG, AR2315_PCI_INT_ENABLE, 0); -+ ar231x_write_reg(AR2315_PCI_INT_STATUS, (AR2315_PCI_ABORT_INT | AR2315_PCI_EXT_INT)); -+ ar231x_write_reg(AR2315_PCI_INT_MASK, (AR2315_PCI_ABORT_INT | AR2315_PCI_EXT_INT)); -+ ar231x_mask_reg(AR2315_PCI_INTEN_REG, 0, AR2315_PCI_INT_ENABLE); -+ -+ return 0; -+} -+ -+static void -+ar2315_pci_fixup(struct pci_dev *dev) -+{ -+ unsigned int devfn = dev->devfn; -+ -+ if (dev->bus->number != 0) -+ return; -+ -+ /* Only fix up the PCI host settings */ -+ if ((PCI_SLOT(devfn) != 3) || (PCI_FUNC(devfn) != 0)) -+ return; -+ -+ /* Fix up MBARs */ -+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, HOST_PCI_MBAR0); -+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, HOST_PCI_MBAR1); -+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, HOST_PCI_MBAR2); -+ pci_write_config_dword(dev, PCI_COMMAND, -+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL | -+ PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | -+ PCI_COMMAND_FAST_BACK); -+} -+DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, ar2315_pci_fixup); -+ -+static int __init -+ar2315_pci_init(void) -+{ -+ u32 reg; -+ -+ if (ar231x_devtype != DEV_TYPE_AR2315) -+ return -ENODEV; -+ -+ configspace = (unsigned long) ioremap_nocache(0x80000000, 1*1024*1024); /* Remap PCI config space */ -+ ar231x_pci_controller.io_map_base = -+ (unsigned long) ioremap_nocache(AR531X_MEM_BASE + AR531X_MEM_SIZE, AR531X_IO_SIZE); -+ set_io_port_base(ar231x_pci_controller.io_map_base); /* PCI I/O space */ -+ -+ reg = ar231x_mask_reg(AR2315_RESET, 0, AR2315_RESET_PCIDMA); -+ msleep(10); -+ -+ reg &= ~AR2315_RESET_PCIDMA; -+ ar231x_write_reg(AR2315_RESET, reg); -+ msleep(10); -+ -+ ar231x_mask_reg(AR2315_ENDIAN_CTL, 0, -+ AR2315_CONFIG_PCIAHB | AR2315_CONFIG_PCIAHB_BRIDGE); -+ -+ ar231x_write_reg(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM | -+ (AR2315_PCICLK_IN_FREQ_DIV_6 << AR2315_PCICLK_DIV_S)); -+ ar231x_mask_reg(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI); -+ ar231x_mask_reg(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK | AR2315_IF_MASK, -+ AR2315_IF_PCI | AR2315_IF_PCI_HOST | AR2315_IF_PCI_INTR | -+ (AR2315_IF_PCI_CLK_OUTPUT_CLK << AR2315_IF_PCI_CLK_SHIFT)); -+ -+ /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */ -+ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE, -+ AR2315_PCIRST_LOW); -+ msleep(100); -+ -+ /* Bring the PCI out of reset */ -+ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE, -+ AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8); -+ -+ ar231x_write_reg(AR2315_PCI_UNCACHE_CFG, -+ 0x1E | /* 1GB uncached */ -+ (1 << 5) | /* Enable uncached */ -+ (0x2 << 30) /* Base: 0x80000000 */ -+ ); -+ ar231x_read_reg(AR2315_PCI_UNCACHE_CFG); -+ -+ msleep(500); -+ -+ /* dirty hack - anyone with a datasheet that knows the memory map ? */ -+ ioport_resource.start = 0x10000000; -+ ioport_resource.end = 0xffffffff; -+ iomem_resource.start = 0x10000000; -+ iomem_resource.end = 0xffffffff; -+ -+ register_pci_controller(&ar231x_pci_controller); -+ -+ return 0; -+} -+ -+arch_initcall(ar2315_pci_init); -diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/prom.c linux-2.6.39-rc7/arch/mips/ar231x/prom.c ---- linux-2.6.39-rc7.orig/arch/mips/ar231x/prom.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/ar231x/prom.c 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,37 @@ -+/* -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright MontaVista Software Inc -+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. -+ * Copyright (C) 2006 FON Technology, SL. -+ * Copyright (C) 2006 Imre Kaloz -+ * Copyright (C) 2006 Felix Fietkau -+ */ -+ -+/* -+ * Prom setup file for ar531x -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include "ar5312.h" -+#include "ar2315.h" -+ -+void __init prom_init(void) -+{ -+ ar5312_prom_init(); -+ ar2315_prom_init(); -+} -+ -+void __init prom_free_prom_memory(void) -+{ -+} -diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/reset.c linux-2.6.39-rc7/arch/mips/ar231x/reset.c ---- linux-2.6.39-rc7.orig/arch/mips/ar231x/reset.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/ar231x/reset.c 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,161 @@ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "devices.h" -+ -+#define AR531X_RESET_GPIO_IRQ (AR531X_GPIO_IRQ(ar231x_board.config->resetConfigGpio)) -+ -+struct event_t { -+ struct work_struct wq; -+ int set; -+ unsigned long jiffies; -+}; -+ -+static struct timer_list rst_button_timer; -+static unsigned long seen; -+ -+struct sock *uevent_sock = NULL; -+EXPORT_SYMBOL_GPL(uevent_sock); -+extern u64 uevent_next_seqnum(void); -+ -+static int no_release_workaround = 1; -+module_param(no_release_workaround, int, 0); -+ -+static inline void -+add_msg(struct sk_buff *skb, char *msg) -+{ -+ char *scratch; -+ scratch = skb_put(skb, strlen(msg) + 1); -+ sprintf(scratch, msg); -+} -+ -+static void -+hotplug_button(struct work_struct *wq) -+{ -+ struct sk_buff *skb; -+ struct event_t *event; -+ size_t len; -+ char *scratch, *s; -+ char buf[128]; -+ -+ event = container_of(wq, struct event_t, wq); -+ if (!uevent_sock) -+ goto done; -+ -+ /* allocate message with the maximum possible size */ -+ s = event->set ? "pressed" : "released"; -+ len = strlen(s) + 2; -+ skb = alloc_skb(NLMSG_GOODSIZE, GFP_KERNEL); -+ if (!skb) -+ goto done; -+ -+ /* add header */ -+ scratch = skb_put(skb, len); -+ sprintf(scratch, "%s@",s); -+ -+ /* copy keys to our continuous event payload buffer */ -+ add_msg(skb, "HOME=/"); -+ add_msg(skb, "PATH=/sbin:/bin:/usr/sbin:/usr/bin"); -+ add_msg(skb, "SUBSYSTEM=button"); -+ add_msg(skb, "BUTTON=reset"); -+ add_msg(skb, (event->set ? "ACTION=pressed" : "ACTION=released")); -+ sprintf(buf, "SEEN=%ld", (event->jiffies - seen)/HZ); -+ add_msg(skb, buf); -+ snprintf(buf, 128, "SEQNUM=%llu", uevent_next_seqnum()); -+ add_msg(skb, buf); -+ -+ NETLINK_CB(skb).dst_group = 1; -+ netlink_broadcast(uevent_sock, skb, 0, 1, GFP_KERNEL); -+ -+done: -+ kfree(event); -+} -+ -+static void -+reset_button_poll(unsigned long unused) -+{ -+ struct event_t *event; -+ int gpio = ~0; -+ -+ if(!no_release_workaround) -+ return; -+ -+ gpio = ar231x_gpiodev->get(); -+ gpio &= (1 << (AR531X_RESET_GPIO_IRQ - AR531X_GPIO_IRQ_BASE)); -+ if(gpio) { -+ rst_button_timer.expires = jiffies + (HZ / 4); -+ add_timer(&rst_button_timer); -+ return; -+ } -+ -+ event = (struct event_t *) kzalloc(sizeof(struct event_t), GFP_ATOMIC); -+ if (!event) -+ return; -+ -+ event->set = 0; -+ event->jiffies = jiffies; -+ INIT_WORK(&event->wq, hotplug_button); -+ schedule_work(&event->wq); -+} -+ -+static irqreturn_t -+button_handler(int irq, void *dev_id) -+{ -+ static int pressed = 0; -+ struct event_t *event; -+ u32 gpio = ~0; -+ -+ event = (struct event_t *) kzalloc(sizeof(struct event_t), GFP_ATOMIC); -+ if (!event) -+ return IRQ_NONE; -+ -+ pressed = !pressed; -+ -+ gpio = ar231x_gpiodev->get() & (1 << (irq - AR531X_GPIO_IRQ_BASE)); -+ -+ event->set = gpio; -+ if(!event->set) -+ no_release_workaround = 0; -+ -+ event->jiffies = jiffies; -+ -+ INIT_WORK(&event->wq, hotplug_button); -+ schedule_work(&event->wq); -+ -+ seen = jiffies; -+ if(event->set && no_release_workaround) -+ mod_timer(&rst_button_timer, jiffies + (HZ / 4)); -+ -+ return IRQ_HANDLED; -+} -+ -+ -+static int __init -+ar231x_init_reset(void) -+{ -+ seen = jiffies; -+ -+ if (ar231x_board.config->resetConfigGpio == 0xffff) -+ return -ENODEV; -+ -+ init_timer(&rst_button_timer); -+ rst_button_timer.function = reset_button_poll; -+ rst_button_timer.expires = jiffies + HZ / 50; -+ add_timer(&rst_button_timer); -+ -+ request_irq(AR531X_RESET_GPIO_IRQ, &button_handler, IRQF_SAMPLE_RANDOM, "ar231x_reset", NULL); -+ -+ return 0; -+} -+ -+module_init(ar231x_init_reset); -diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar2315_regs.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar2315_regs.h ---- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar2315_regs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar2315_regs.h 2011-05-15 21:44:12.000000000 +0200 -@@ -0,0 +1,580 @@ -+/* -+ * Register definitions for AR2315+ -+ * -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. -+ * Copyright (C) 2006 FON Technology, SL. -+ * Copyright (C) 2006 Imre Kaloz -+ * Copyright (C) 2006-2008 Felix Fietkau -+ */ -+ -+#ifndef __AR2315_REG_H -+#define __AR2315_REG_H -+ -+/* -+ * IRQs -+ */ -+#define AR2315_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */ -+#define AR2315_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */ -+#define AR2315_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */ -+#define AR2315_IRQ_LCBUS_PCI MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */ -+#define AR2315_IRQ_WLAN0_POLL MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */ -+ -+/* -+ * Address map -+ */ -+#define AR2315_SPI_READ 0x08000000 /* SPI FLASH */ -+#define AR2315_WLAN0 0x10000000 /* Wireless MMR */ -+#define AR2315_PCI 0x10100000 /* PCI MMR */ -+#define AR2315_SDRAMCTL 0x10300000 /* SDRAM MMR */ -+#define AR2315_LOCAL 0x10400000 /* LOCAL BUS MMR */ -+#define AR2315_ENET0 0x10500000 /* ETHERNET MMR */ -+#define AR2315_DSLBASE 0x11000000 /* RESET CONTROL MMR */ -+#define AR2315_UART0 0x11100003 /* UART MMR */ -+#define AR2315_SPI 0x11300000 /* SPI FLASH MMR */ -+#define AR2315_PCIEXT 0x80000000 /* pci external */ -+ -+/* -+ * Reset Register -+ */ -+#define AR2315_COLD_RESET (AR2315_DSLBASE + 0x0000) -+ -+#define AR2315_RESET_COLD_AHB 0x00000001 -+#define AR2315_RESET_COLD_APB 0x00000002 -+#define AR2315_RESET_COLD_CPU 0x00000004 -+#define AR2315_RESET_COLD_CPUWARM 0x00000008 -+#define AR2315_RESET_SYSTEM (RESET_COLD_CPU | RESET_COLD_APB | RESET_COLD_AHB) /* full system */ -+#define AR2317_RESET_SYSTEM 0x00000010 -+ -+ -+#define AR2315_RESET (AR2315_DSLBASE + 0x0004) -+ -+#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001 /* warm reset WLAN0 MAC */ -+#define AR2315_RESET_WARM_WLAN0_BB 0x00000002 /* warm reset WLAN0 BaseBand */ -+#define AR2315_RESET_MPEGTS_RSVD 0x00000004 /* warm reset MPEG-TS */ -+#define AR2315_RESET_PCIDMA 0x00000008 /* warm reset PCI ahb/dma */ -+#define AR2315_RESET_MEMCTL 0x00000010 /* warm reset memory controller */ -+#define AR2315_RESET_LOCAL 0x00000020 /* warm reset local bus */ -+#define AR2315_RESET_I2C_RSVD 0x00000040 /* warm reset I2C bus */ -+#define AR2315_RESET_SPI 0x00000080 /* warm reset SPI interface */ -+#define AR2315_RESET_UART0 0x00000100 /* warm reset UART0 */ -+#define AR2315_RESET_IR_RSVD 0x00000200 /* warm reset IR interface */ -+#define AR2315_RESET_EPHY0 0x00000400 /* cold reset ENET0 phy */ -+#define AR2315_RESET_ENET0 0x00000800 /* cold reset ENET0 mac */ -+ -+/* -+ * AHB master arbitration control -+ */ -+#define AR2315_AHB_ARB_CTL (AR2315_DSLBASE + 0x0008) -+ -+#define AR2315_ARB_CPU 0x00000001 /* CPU, default */ -+#define AR2315_ARB_WLAN 0x00000002 /* WLAN */ -+#define AR2315_ARB_MPEGTS_RSVD 0x00000004 /* MPEG-TS */ -+#define AR2315_ARB_LOCAL 0x00000008 /* LOCAL */ -+#define AR2315_ARB_PCI 0x00000010 /* PCI */ -+#define AR2315_ARB_ETHERNET 0x00000020 /* Ethernet */ -+#define AR2315_ARB_RETRY 0x00000100 /* retry policy, debug only */ -+ -+/* -+ * Config Register -+ */ -+#define AR2315_ENDIAN_CTL (AR2315_DSLBASE + 0x000c) -+ -+#define AR2315_CONFIG_AHB 0x00000001 /* EC - AHB bridge endianess */ -+#define AR2315_CONFIG_WLAN 0x00000002 /* WLAN byteswap */ -+#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004 /* MPEG-TS byteswap */ -+#define AR2315_CONFIG_PCI 0x00000008 /* PCI byteswap */ -+#define AR2315_CONFIG_MEMCTL 0x00000010 /* Memory controller endianess */ -+#define AR2315_CONFIG_LOCAL 0x00000020 /* Local bus byteswap */ -+#define AR2315_CONFIG_ETHERNET 0x00000040 /* Ethernet byteswap */ -+ -+#define AR2315_CONFIG_MERGE 0x00000200 /* CPU write buffer merge */ -+#define AR2315_CONFIG_CPU 0x00000400 /* CPU big endian */ -+#define AR2315_CONFIG_PCIAHB 0x00000800 -+#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000 -+#define AR2315_CONFIG_SPI 0x00008000 /* SPI byteswap */ -+#define AR2315_CONFIG_CPU_DRAM 0x00010000 -+#define AR2315_CONFIG_CPU_PCI 0x00020000 -+#define AR2315_CONFIG_CPU_MMR 0x00040000 -+#define AR2315_CONFIG_BIG 0x00000400 -+ -+ -+/* -+ * NMI control -+ */ -+#define AR2315_NMI_CTL (AR2315_DSLBASE + 0x0010) -+ -+#define AR2315_NMI_EN 1 -+ -+/* -+ * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR531X 1.0). -+ */ -+#define AR2315_SREV (AR2315_DSLBASE + 0x0014) -+ -+#define AR2315_REV_MAJ 0x00f0 -+#define AR2315_REV_MAJ_S 4 -+#define AR2315_REV_MIN 0x000f -+#define AR2315_REV_MIN_S 0 -+#define AR2315_REV_CHIP (AR2315_REV_MAJ|AR2315_REV_MIN) -+ -+/* -+ * Interface Enable -+ */ -+#define AR2315_IF_CTL (AR2315_DSLBASE + 0x0018) -+ -+#define AR2315_IF_MASK 0x00000007 -+#define AR2315_IF_DISABLED 0 -+#define AR2315_IF_PCI 1 -+#define AR2315_IF_TS_LOCAL 2 -+#define AR2315_IF_ALL 3 /* only for emulation with separate pins */ -+#define AR2315_IF_LOCAL_HOST 0x00000008 -+#define AR2315_IF_PCI_HOST 0x00000010 -+#define AR2315_IF_PCI_INTR 0x00000020 -+#define AR2315_IF_PCI_CLK_MASK 0x00030000 -+#define AR2315_IF_PCI_CLK_INPUT 0 -+#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1 -+#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2 -+#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3 -+#define AR2315_IF_PCI_CLK_SHIFT 16 -+ -+/* -+ * APB Interrupt control -+ */ -+ -+#define AR2315_ISR (AR2315_DSLBASE + 0x0020) -+#define AR2315_IMR (AR2315_DSLBASE + 0x0024) -+#define AR2315_GISR (AR2315_DSLBASE + 0x0028) -+ -+#define AR2315_ISR_UART0 0x0001 /* high speed UART */ -+#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */ -+#define AR2315_ISR_SPI 0x0004 /* SPI bus */ -+#define AR2315_ISR_AHB 0x0008 /* AHB error */ -+#define AR2315_ISR_APB 0x0010 /* APB error */ -+#define AR2315_ISR_TIMER 0x0020 /* timer */ -+#define AR2315_ISR_GPIO 0x0040 /* GPIO */ -+#define AR2315_ISR_WD 0x0080 /* watchdog */ -+#define AR2315_ISR_IR_RSVD 0x0100 /* IR */ -+ -+#define AR2315_GISR_MISC 0x0001 -+#define AR2315_GISR_WLAN0 0x0002 -+#define AR2315_GISR_MPEGTS_RSVD 0x0004 -+#define AR2315_GISR_LOCALPCI 0x0008 -+#define AR2315_GISR_WMACPOLL 0x0010 -+#define AR2315_GISR_TIMER 0x0020 -+#define AR2315_GISR_ETHERNET 0x0040 -+ -+/* -+ * Interrupt routing from IO to the processor IP bits -+ * Define our inter mask and level -+ */ -+#define AR2315_INTR_MISCIO SR_IBIT3 -+#define AR2315_INTR_WLAN0 SR_IBIT4 -+#define AR2315_INTR_ENET0 SR_IBIT5 -+#define AR2315_INTR_LOCALPCI SR_IBIT6 -+#define AR2315_INTR_WMACPOLL SR_IBIT7 -+#define AR2315_INTR_COMPARE SR_IBIT8 -+ -+/* -+ * Timers -+ */ -+#define AR2315_TIMER (AR2315_DSLBASE + 0x0030) -+#define AR2315_RELOAD (AR2315_DSLBASE + 0x0034) -+#define AR2315_WD (AR2315_DSLBASE + 0x0038) -+#define AR2315_WDC (AR2315_DSLBASE + 0x003c) -+ -+#define AR2315_WDC_IGNORE_EXPIRATION 0x00000000 -+#define AR2315_WDC_NMI 0x00000001 /* NMI on watchdog */ -+#define AR2315_WDC_RESET 0x00000002 /* reset on watchdog */ -+ -+/* -+ * CPU Performance Counters -+ */ -+#define AR2315_PERFCNT0 (AR2315_DSLBASE + 0x0048) -+#define AR2315_PERFCNT1 (AR2315_DSLBASE + 0x004c) -+ -+#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */ -+#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */ -+#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */ -+#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */ -+#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */ -+#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */ -+#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */ -+ -+#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */ -+#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */ -+#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */ -+#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */ -+#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */ -+#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */ -+#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */ -+ -+/* -+ * AHB Error Reporting. -+ */ -+#define AR2315_AHB_ERR0 (AR2315_DSLBASE + 0x0050) /* error */ -+#define AR2315_AHB_ERR1 (AR2315_DSLBASE + 0x0054) /* haddr */ -+#define AR2315_AHB_ERR2 (AR2315_DSLBASE + 0x0058) /* hwdata */ -+#define AR2315_AHB_ERR3 (AR2315_DSLBASE + 0x005c) /* hrdata */ -+#define AR2315_AHB_ERR4 (AR2315_DSLBASE + 0x0060) /* status */ -+ -+#define AHB_ERROR_DET 1 /* AHB Error has been detected, */ -+ /* write 1 to clear all bits in ERR0 */ -+#define AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */ -+#define AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */ -+ -+#define AR2315_PROCERR_HMAST 0x0000000f -+#define AR2315_PROCERR_HMAST_DFLT 0 -+#define AR2315_PROCERR_HMAST_WMAC 1 -+#define AR2315_PROCERR_HMAST_ENET 2 -+#define AR2315_PROCERR_HMAST_PCIENDPT 3 -+#define AR2315_PROCERR_HMAST_LOCAL 4 -+#define AR2315_PROCERR_HMAST_CPU 5 -+#define AR2315_PROCERR_HMAST_PCITGT 6 -+ -+#define AR2315_PROCERR_HMAST_S 0 -+#define AR2315_PROCERR_HWRITE 0x00000010 -+#define AR2315_PROCERR_HSIZE 0x00000060 -+#define AR2315_PROCERR_HSIZE_S 5 -+#define AR2315_PROCERR_HTRANS 0x00000180 -+#define AR2315_PROCERR_HTRANS_S 7 -+#define AR2315_PROCERR_HBURST 0x00000e00 -+#define AR2315_PROCERR_HBURST_S 9 -+ -+/* -+ * Clock Control -+ */ -+#define AR2315_PLLC_CTL (AR2315_DSLBASE + 0x0064) -+#define AR2315_PLLV_CTL (AR2315_DSLBASE + 0x0068) -+#define AR2315_CPUCLK (AR2315_DSLBASE + 0x006c) -+#define AR2315_AMBACLK (AR2315_DSLBASE + 0x0070) -+#define AR2315_SYNCCLK (AR2315_DSLBASE + 0x0074) -+#define AR2315_DSL_SLEEP_CTL (AR2315_DSLBASE + 0x0080) -+#define AR2315_DSL_SLEEP_DUR (AR2315_DSLBASE + 0x0084) -+ -+/* PLLc Control fields */ -+#define PLLC_REF_DIV_M 0x00000003 -+#define PLLC_REF_DIV_S 0 -+#define PLLC_FDBACK_DIV_M 0x0000007C -+#define PLLC_FDBACK_DIV_S 2 -+#define PLLC_ADD_FDBACK_DIV_M 0x00000080 -+#define PLLC_ADD_FDBACK_DIV_S 7 -+#define PLLC_CLKC_DIV_M 0x0001c000 -+#define PLLC_CLKC_DIV_S 14 -+#define PLLC_CLKM_DIV_M 0x00700000 -+#define PLLC_CLKM_DIV_S 20 -+ -+/* CPU CLK Control fields */ -+#define CPUCLK_CLK_SEL_M 0x00000003 -+#define CPUCLK_CLK_SEL_S 0 -+#define CPUCLK_CLK_DIV_M 0x0000000c -+#define CPUCLK_CLK_DIV_S 2 -+ -+/* AMBA CLK Control fields */ -+#define AMBACLK_CLK_SEL_M 0x00000003 -+#define AMBACLK_CLK_SEL_S 0 -+#define AMBACLK_CLK_DIV_M 0x0000000c -+#define AMBACLK_CLK_DIV_S 2 -+ -+/* -+ * GPIO -+ */ -+#define AR2315_GPIO_DI (AR2315_DSLBASE + 0x0088) -+#define AR2315_GPIO_DO (AR2315_DSLBASE + 0x0090) -+#define AR2315_GPIO_CR (AR2315_DSLBASE + 0x0098) -+#define AR2315_GPIO_INT (AR2315_DSLBASE + 0x00a0) -+ -+#define AR2315_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */ -+#define AR2315_GPIO_CR_O(x) (1 << (x)) /* output */ -+#define AR2315_GPIO_CR_I(x) (0) /* input */ -+ -+#define AR2315_GPIO_INT_S(x) (x) /* interrupt enable */ -+#define AR2315_GPIO_INT_M (0x3F) /* mask for int */ -+#define AR2315_GPIO_INT_LVL(x) ((x) << 6) /* interrupt level */ -+#define AR2315_GPIO_INT_LVL_M ((0x3) << 6) /* mask for int level */ -+ -+#define AR2315_GPIO_INT_MAX_Y 1 /* Maximum value of Y for AR5313_GPIO_INT_* macros */ -+#define AR2315_GPIO_INT_LVL_OFF 0 /* Triggerring off */ -+#define AR2315_GPIO_INT_LVL_LOW 1 /* Low Level Triggered */ -+#define AR2315_GPIO_INT_LVL_HIGH 2 /* High Level Triggered */ -+#define AR2315_GPIO_INT_LVL_EDGE 3 /* Edge Triggered */ -+ -+#define AR2315_RESET_GPIO 5 -+#define AR2315_NUM_GPIO 22 -+ -+/* -+ * PCI Clock Control -+ */ -+#define AR2315_PCICLK (AR2315_DSLBASE + 0x00a4) -+ -+#define AR2315_PCICLK_INPUT_M 0x3 -+#define AR2315_PCICLK_INPUT_S 0 -+ -+#define AR2315_PCICLK_PLLC_CLKM 0 -+#define AR2315_PCICLK_PLLC_CLKM1 1 -+#define AR2315_PCICLK_PLLC_CLKC 2 -+#define AR2315_PCICLK_REF_CLK 3 -+ -+#define AR2315_PCICLK_DIV_M 0xc -+#define AR2315_PCICLK_DIV_S 2 -+ -+#define AR2315_PCICLK_IN_FREQ 0 -+#define AR2315_PCICLK_IN_FREQ_DIV_6 1 -+#define AR2315_PCICLK_IN_FREQ_DIV_8 2 -+#define AR2315_PCICLK_IN_FREQ_DIV_10 3 -+ -+/* -+ * Observation Control Register -+ */ -+#define AR2315_OCR (AR2315_DSLBASE + 0x00b0) -+#define OCR_GPIO0_IRIN 0x0040 -+#define OCR_GPIO1_IROUT 0x0080 -+#define OCR_GPIO3_RXCLR 0x0200 -+ -+/* -+ * General Clock Control -+ */ -+ -+#define AR2315_MISCCLK (AR2315_DSLBASE + 0x00b4) -+#define MISCCLK_PLLBYPASS_EN 0x00000001 -+#define MISCCLK_PROCREFCLK 0x00000002 -+ -+/* -+ * SDRAM Controller -+ * - No read or write buffers are included. -+ */ -+#define AR2315_MEM_CFG (AR2315_SDRAMCTL + 0x00) -+#define AR2315_MEM_CTRL (AR2315_SDRAMCTL + 0x0c) -+#define AR2315_MEM_REF (AR2315_SDRAMCTL + 0x10) -+ -+#define SDRAM_DATA_WIDTH_M 0x00006000 -+#define SDRAM_DATA_WIDTH_S 13 -+ -+#define SDRAM_COL_WIDTH_M 0x00001E00 -+#define SDRAM_COL_WIDTH_S 9 -+ -+#define SDRAM_ROW_WIDTH_M 0x000001E0 -+#define SDRAM_ROW_WIDTH_S 5 -+ -+#define SDRAM_BANKADDR_BITS_M 0x00000018 -+#define SDRAM_BANKADDR_BITS_S 3 -+ -+/* -+ * SPI Flash Interface Registers -+ */ -+ -+#define AR2315_SPI_CTL (AR2315_SPI + 0x00) -+#define AR2315_SPI_OPCODE (AR2315_SPI + 0x04) -+#define AR2315_SPI_DATA (AR2315_SPI + 0x08) -+ -+#define SPI_CTL_START 0x00000100 -+#define SPI_CTL_BUSY 0x00010000 -+#define SPI_CTL_TXCNT_MASK 0x0000000f -+#define SPI_CTL_RXCNT_MASK 0x000000f0 -+#define SPI_CTL_TX_RX_CNT_MASK 0x000000ff -+#define SPI_CTL_SIZE_MASK 0x00060000 -+ -+#define SPI_CTL_CLK_SEL_MASK 0x03000000 -+#define SPI_OPCODE_MASK 0x000000ff -+ -+/* -+ * PCI Bus Interface Registers -+ */ -+#define AR2315_PCI_1MS_REG (AR2315_PCI + 0x0008) -+#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */ -+ -+#define AR2315_PCI_MISC_CONFIG (AR2315_PCI + 0x000c) -+#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */ -+#define AR2315_PCIMISC_CFG_SEL 0x00000002 /* mem or config cycles */ -+#define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */ -+#define AR2315_PCIMISC_RST_MODE 0x00000030 -+#define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */ -+#define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */ -+#define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */ -+#define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */ -+#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */ -+#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */ -+#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */ -+#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache disable */ -+ -+#define AR2315_PCI_OUT_TSTAMP (AR2315_PCI + 0x0010) -+ -+#define AR2315_PCI_UNCACHE_CFG (AR2315_PCI + 0x0014) -+ -+#define AR2315_PCI_IN_EN (AR2315_PCI + 0x0100) -+#define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */ -+#define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */ -+#define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */ -+#define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */ -+ -+#define AR2315_PCI_IN_DIS (AR2315_PCI + 0x0104) -+#define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */ -+#define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */ -+#define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */ -+#define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */ -+ -+#define AR2315_PCI_IN_PTR (AR2315_PCI + 0x0200) -+ -+#define AR2315_PCI_OUT_EN (AR2315_PCI + 0x0400) -+#define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */ -+ -+#define AR2315_PCI_OUT_DIS (AR2315_PCI + 0x0404) -+#define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */ -+ -+#define AR2315_PCI_OUT_PTR (AR2315_PCI + 0x0408) -+ -+#define AR2315_PCI_INT_STATUS (AR2315_PCI + 0x0500) /* write one to clr */ -+#define AR2315_PCI_TXINT 0x00000001 /* Desc In Completed */ -+#define AR2315_PCI_TXOK 0x00000002 /* Desc In OK */ -+#define AR2315_PCI_TXERR 0x00000004 /* Desc In ERR */ -+#define AR2315_PCI_TXEOL 0x00000008 /* Desc In End-of-List */ -+#define AR2315_PCI_RXINT 0x00000010 /* Desc Out Completed */ -+#define AR2315_PCI_RXOK 0x00000020 /* Desc Out OK */ -+#define AR2315_PCI_RXERR 0x00000040 /* Desc Out ERR */ -+#define AR2315_PCI_RXEOL 0x00000080 /* Desc Out EOL */ -+#define AR2315_PCI_TXOOD 0x00000200 /* Desc In Out-of-Desc */ -+#define AR2315_PCI_MASK 0x0000FFFF /* Desc Mask */ -+#define AR2315_PCI_EXT_INT 0x02000000 -+#define AR2315_PCI_ABORT_INT 0x04000000 -+ -+#define AR2315_PCI_INT_MASK (AR2315_PCI + 0x0504) /* same as INT_STATUS */ -+ -+#define AR2315_PCI_INTEN_REG (AR2315_PCI + 0x0508) -+#define AR2315_PCI_INT_DISABLE 0x00 /* disable pci interrupts */ -+#define AR2315_PCI_INT_ENABLE 0x01 /* enable pci interrupts */ -+ -+#define AR2315_PCI_HOST_IN_EN (AR2315_PCI + 0x0800) -+#define AR2315_PCI_HOST_IN_DIS (AR2315_PCI + 0x0804) -+#define AR2315_PCI_HOST_IN_PTR (AR2315_PCI + 0x0810) -+#define AR2315_PCI_HOST_OUT_EN (AR2315_PCI + 0x0900) -+#define AR2315_PCI_HOST_OUT_DIS (AR2315_PCI + 0x0904) -+#define AR2315_PCI_HOST_OUT_PTR (AR2315_PCI + 0x0908) -+ -+ -+/* -+ * Local Bus Interface Registers -+ */ -+#define AR2315_LB_CONFIG (AR2315_LOCAL + 0x0000) -+#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */ -+#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */ -+#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */ -+#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */ -+#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */ -+#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */ -+#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */ -+#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */ -+#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */ -+#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */ -+#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */ -+#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */ -+#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */ -+#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */ -+#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */ -+#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */ -+#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */ -+#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */ -+#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */ -+#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */ -+#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */ -+#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */ -+#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */ -+#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */ -+#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */ -+ -+#define AR2315_LB_CLKSEL (AR2315_LOCAL + 0x0004) -+#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */ -+ -+#define AR2315_LB_1MS (AR2315_LOCAL + 0x0008) -+#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */ -+ -+#define AR2315_LB_MISCCFG (AR2315_LOCAL + 0x000C) -+#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */ -+#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */ -+#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */ -+#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */ -+#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */ -+#define AR2315_LBM_TIMEOUT_MASK 0x00FFFF80 -+#define AR2315_LBM_TIMEOUT_SHFT 7 -+#define AR2315_LBM_PORTMUX 0x07000000 -+ -+ -+#define AR2315_LB_RXTSOFF (AR2315_LOCAL + 0x0010) -+ -+#define AR2315_LB_TX_CHAIN_EN (AR2315_LOCAL + 0x0100) -+#define AR2315_LB_TXEN_0 0x01 -+#define AR2315_LB_TXEN_1 0x02 -+#define AR2315_LB_TXEN_2 0x04 -+#define AR2315_LB_TXEN_3 0x08 -+ -+#define AR2315_LB_TX_CHAIN_DIS (AR2315_LOCAL + 0x0104) -+#define AR2315_LB_TX_DESC_PTR (AR2315_LOCAL + 0x0200) -+ -+#define AR2315_LB_RX_CHAIN_EN (AR2315_LOCAL + 0x0400) -+#define AR2315_LB_RXEN 0x01 -+ -+#define AR2315_LB_RX_CHAIN_DIS (AR2315_LOCAL + 0x0404) -+#define AR2315_LB_RX_DESC_PTR (AR2315_LOCAL + 0x0408) -+ -+#define AR2315_LB_INT_STATUS (AR2315_LOCAL + 0x0500) -+#define AR2315_INT_TX_DESC 0x0001 -+#define AR2315_INT_TX_OK 0x0002 -+#define AR2315_INT_TX_ERR 0x0004 -+#define AR2315_INT_TX_EOF 0x0008 -+#define AR2315_INT_RX_DESC 0x0010 -+#define AR2315_INT_RX_OK 0x0020 -+#define AR2315_INT_RX_ERR 0x0040 -+#define AR2315_INT_RX_EOF 0x0080 -+#define AR2315_INT_TX_TRUNC 0x0100 -+#define AR2315_INT_TX_STARVE 0x0200 -+#define AR2315_INT_LB_TIMEOUT 0x0400 -+#define AR2315_INT_LB_ERR 0x0800 -+#define AR2315_INT_MBOX_WR 0x1000 -+#define AR2315_INT_MBOX_RD 0x2000 -+ -+/* Bit definitions for INT MASK are the same as INT_STATUS */ -+#define AR2315_LB_INT_MASK (AR2315_LOCAL + 0x0504) -+ -+#define AR2315_LB_INT_EN (AR2315_LOCAL + 0x0508) -+#define AR2315_LB_MBOX (AR2315_LOCAL + 0x0600) -+ -+/* -+ * IR Interface Registers -+ */ -+#define AR2315_IR_PKTDATA (AR2315_IR + 0x0000) -+ -+#define AR2315_IR_PKTLEN (AR2315_IR + 0x07fc) /* 0 - 63 */ -+ -+#define AR2315_IR_CONTROL (AR2315_IR + 0x0800) -+#define AR2315_IRCTL_TX 0x00000000 /* use as tranmitter */ -+#define AR2315_IRCTL_RX 0x00000001 /* use as receiver */ -+#define AR2315_IRCTL_SAMPLECLK_MASK 0x00003ffe /* Sample clk divisor mask */ -+#define AR2315_IRCTL_SAMPLECLK_SHFT 1 -+#define AR2315_IRCTL_OUTPUTCLK_MASK 0x03ffc000 /* Output clk divisor mask */ -+#define AR2315_IRCTL_OUTPUTCLK_SHFT 14 -+ -+#define AR2315_IR_STATUS (AR2315_IR + 0x0804) -+#define AR2315_IRSTS_RX 0x00000001 /* receive in progress */ -+#define AR2315_IRSTS_TX 0x00000002 /* transmit in progress */ -+ -+#define AR2315_IR_CONFIG (AR2315_IR + 0x0808) -+#define AR2315_IRCFG_INVIN 0x00000001 /* invert input polarity */ -+#define AR2315_IRCFG_INVOUT 0x00000002 /* invert output polarity */ -+#define AR2315_IRCFG_SEQ_START_WIN_SEL 0x00000004 /* 1 => 28, 0 => 7 */ -+#define AR2315_IRCFG_SEQ_START_THRESH 0x000000f0 /* */ -+#define AR2315_IRCFG_SEQ_END_UNIT_SEL 0x00000100 /* */ -+#define AR2315_IRCFG_SEQ_END_UNIT_THRESH 0x00007e00 /* */ -+#define AR2315_IRCFG_SEQ_END_WIN_SEL 0x00008000 /* */ -+#define AR2315_IRCFG_SEQ_END_WIN_THRESH 0x001f0000 /* */ -+#define AR2315_IRCFG_NUM_BACKOFF_WORDS 0x01e00000 /* */ -+ -+#define HOST_PCI_DEV_ID 3 -+#define HOST_PCI_MBAR0 0x10000000 -+#define HOST_PCI_MBAR1 0x20000000 -+#define HOST_PCI_MBAR2 0x30000000 -+ -+#define HOST_PCI_SDRAM_BASEADDR HOST_PCI_MBAR1 -+#define PCI_DEVICE_MEM_SPACE 0x800000 -+ -+#endif /* __AR2315_REG_H */ -diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar2315_spiflash.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar2315_spiflash.h ---- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar2315_spiflash.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar2315_spiflash.h 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,116 @@ -+/* -+ * SPI Flash Memory support header file. -+ * -+ * Copyright (c) 2005, Atheros Communications Inc. -+ * Copyright (C) 2006 FON Technology, SL. -+ * Copyright (C) 2006 Imre Kaloz -+ * Copyright (C) 2006-2009 Felix Fietkau -+ * -+ * This code is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ */ -+#ifndef __AR2315_SPIFLASH_H -+#define __AR2315_SPIFLASH_H -+ -+#define STM_PAGE_SIZE 256 -+ -+#define SFI_WRITE_BUFFER_SIZE 4 -+#define SFI_FLASH_ADDR_MASK 0x00ffffff -+ -+#define STM_8MBIT_SIGNATURE 0x13 -+#define STM_M25P80_BYTE_COUNT 1048576 -+#define STM_M25P80_SECTOR_COUNT 16 -+#define STM_M25P80_SECTOR_SIZE 0x10000 -+ -+#define STM_16MBIT_SIGNATURE 0x14 -+#define STM_M25P16_BYTE_COUNT 2097152 -+#define STM_M25P16_SECTOR_COUNT 32 -+#define STM_M25P16_SECTOR_SIZE 0x10000 -+ -+#define STM_32MBIT_SIGNATURE 0x15 -+#define STM_M25P32_BYTE_COUNT 4194304 -+#define STM_M25P32_SECTOR_COUNT 64 -+#define STM_M25P32_SECTOR_SIZE 0x10000 -+ -+#define STM_64MBIT_SIGNATURE 0x16 -+#define STM_M25P64_BYTE_COUNT 8388608 -+#define STM_M25P64_SECTOR_COUNT 128 -+#define STM_M25P64_SECTOR_SIZE 0x10000 -+ -+#define STM_128MBIT_SIGNATURE 0x17 -+#define STM_M25P128_BYTE_COUNT 16777216 -+#define STM_M25P128_SECTOR_COUNT 256 -+#define STM_M25P128_SECTOR_SIZE 0x10000 -+ -+#define STM_1MB_BYTE_COUNT STM_M25P80_BYTE_COUNT -+#define STM_1MB_SECTOR_COUNT STM_M25P80_SECTOR_COUNT -+#define STM_1MB_SECTOR_SIZE STM_M25P80_SECTOR_SIZE -+#define STM_2MB_BYTE_COUNT STM_M25P16_BYTE_COUNT -+#define STM_2MB_SECTOR_COUNT STM_M25P16_SECTOR_COUNT -+#define STM_2MB_SECTOR_SIZE STM_M25P16_SECTOR_SIZE -+#define STM_4MB_BYTE_COUNT STM_M25P32_BYTE_COUNT -+#define STM_4MB_SECTOR_COUNT STM_M25P32_SECTOR_COUNT -+#define STM_4MB_SECTOR_SIZE STM_M25P32_SECTOR_SIZE -+#define STM_8MB_BYTE_COUNT STM_M25P64_BYTE_COUNT -+#define STM_8MB_SECTOR_COUNT STM_M25P64_SECTOR_COUNT -+#define STM_8MB_SECTOR_SIZE STM_M25P64_SECTOR_SIZE -+#define STM_16MB_BYTE_COUNT STM_M25P128_BYTE_COUNT -+#define STM_16MB_SECTOR_COUNT STM_M25P128_SECTOR_COUNT -+#define STM_16MB_SECTOR_SIZE STM_M25P128_SECTOR_SIZE -+ -+/* -+ * ST Microelectronics Opcodes for Serial Flash -+ */ -+ -+#define STM_OP_WR_ENABLE 0x06 /* Write Enable */ -+#define STM_OP_WR_DISABLE 0x04 /* Write Disable */ -+#define STM_OP_RD_STATUS 0x05 /* Read Status */ -+#define STM_OP_WR_STATUS 0x01 /* Write Status */ -+#define STM_OP_RD_DATA 0x03 /* Read Data */ -+#define STM_OP_FAST_RD_DATA 0x0b /* Fast Read Data */ -+#define STM_OP_PAGE_PGRM 0x02 /* Page Program */ -+#define STM_OP_SECTOR_ERASE 0xd8 /* Sector Erase */ -+#define STM_OP_BULK_ERASE 0xc7 /* Bulk Erase */ -+#define STM_OP_DEEP_PWRDOWN 0xb9 /* Deep Power-Down Mode */ -+#define STM_OP_RD_SIG 0xab /* Read Electronic Signature */ -+ -+#define STM_STATUS_WIP 0x01 /* Write-In-Progress */ -+#define STM_STATUS_WEL 0x02 /* Write Enable Latch */ -+#define STM_STATUS_BP0 0x04 /* Block Protect 0 */ -+#define STM_STATUS_BP1 0x08 /* Block Protect 1 */ -+#define STM_STATUS_BP2 0x10 /* Block Protect 2 */ -+#define STM_STATUS_SRWD 0x80 /* Status Register Write Disable */ -+ -+/* -+ * SPI Flash Interface Registers -+ */ -+#define AR531XPLUS_SPI_READ 0x08000000 -+#define AR531XPLUS_SPI_MMR 0x11300000 -+#define AR531XPLUS_SPI_MMR_SIZE 12 -+ -+#define AR531XPLUS_SPI_CTL 0x00 -+#define AR531XPLUS_SPI_OPCODE 0x04 -+#define AR531XPLUS_SPI_DATA 0x08 -+ -+#define SPI_FLASH_READ AR531XPLUS_SPI_READ -+#define SPI_FLASH_MMR AR531XPLUS_SPI_MMR -+#define SPI_FLASH_MMR_SIZE AR531XPLUS_SPI_MMR_SIZE -+#define SPI_FLASH_CTL AR531XPLUS_SPI_CTL -+#define SPI_FLASH_OPCODE AR531XPLUS_SPI_OPCODE -+#define SPI_FLASH_DATA AR531XPLUS_SPI_DATA -+ -+#define SPI_CTL_START 0x00000100 -+#define SPI_CTL_BUSY 0x00010000 -+#define SPI_CTL_TXCNT_MASK 0x0000000f -+#define SPI_CTL_RXCNT_MASK 0x000000f0 -+#define SPI_CTL_TX_RX_CNT_MASK 0x000000ff -+#define SPI_CTL_SIZE_MASK 0x00060000 -+ -+#define SPI_CTL_CLK_SEL_MASK 0x03000000 -+#define SPI_OPCODE_MASK 0x000000ff -+ -+#define SPI_STATUS_WIP STM_STATUS_WIP -+ -+#endif -diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar231x.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar231x.h ---- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar231x.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar231x.h 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,54 @@ -+#ifndef __AR531X_H -+#define __AR531X_H -+ -+#define AR531X_MISC_IRQ_BASE 0x20 -+#define AR531X_GPIO_IRQ_BASE 0x30 -+ -+/* Software's idea of interrupts handled by "CPU Interrupt Controller" */ -+#define AR531X_IRQ_NONE MIPS_CPU_IRQ_BASE+0 -+#define AR531X_IRQ_CPU_CLOCK MIPS_CPU_IRQ_BASE+7 /* C0_CAUSE: 0x8000 */ -+ -+/* Miscellaneous interrupts, which share IP6 */ -+#define AR531X_MISC_IRQ_NONE AR531X_MISC_IRQ_BASE+0 -+#define AR531X_MISC_IRQ_TIMER AR531X_MISC_IRQ_BASE+1 -+#define AR531X_MISC_IRQ_AHB_PROC AR531X_MISC_IRQ_BASE+2 -+#define AR531X_MISC_IRQ_AHB_DMA AR531X_MISC_IRQ_BASE+3 -+#define AR531X_MISC_IRQ_GPIO AR531X_MISC_IRQ_BASE+4 -+#define AR531X_MISC_IRQ_UART0 AR531X_MISC_IRQ_BASE+5 -+#define AR531X_MISC_IRQ_UART0_DMA AR531X_MISC_IRQ_BASE+6 -+#define AR531X_MISC_IRQ_WATCHDOG AR531X_MISC_IRQ_BASE+7 -+#define AR531X_MISC_IRQ_LOCAL AR531X_MISC_IRQ_BASE+8 -+#define AR531X_MISC_IRQ_SPI AR531X_MISC_IRQ_BASE+9 -+#define AR531X_MISC_IRQ_COUNT 10 -+ -+/* GPIO Interrupts [0..7], share AR531X_MISC_IRQ_GPIO */ -+#define AR531X_GPIO_IRQ_NONE AR531X_GPIO_IRQ_BASE+0 -+#define AR531X_GPIO_IRQ(n) AR531X_GPIO_IRQ_BASE+n -+#define AR531X_GPIO_IRQ_COUNT 22 -+ -+static inline u32 -+ar231x_read_reg(u32 reg) -+{ -+ return __raw_readl((u32 *) KSEG1ADDR(reg)); -+} -+ -+static inline void -+ar231x_write_reg(u32 reg, u32 val) -+{ -+ __raw_writel(val, (u32 *) KSEG1ADDR(reg)); -+} -+ -+static inline u32 -+ar231x_mask_reg(u32 reg, u32 mask, u32 val) -+{ -+ u32 ret; -+ -+ ret = ar231x_read_reg(reg); -+ ret &= ~mask; -+ ret |= val; -+ ar231x_write_reg(reg, ret); -+ -+ return ret; -+} -+ -+#endif -diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar231x_platform.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar231x_platform.h ---- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar231x_platform.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar231x_platform.h 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,83 @@ -+#ifndef __AR531X_PLATFORM_H -+#define __AR531X_PLATFORM_H -+ -+/* -+ * This is board-specific data that is stored in a "fixed" location in flash. -+ * It is shared across operating systems, so it should not be changed lightly. -+ * The main reason we need it is in order to extract the ethernet MAC -+ * address(es). -+ */ -+struct ar231x_boarddata { -+ u32 magic; /* board data is valid */ -+#define AR531X_BD_MAGIC 0x35333131 /* "5311", for all 531x platforms */ -+ u16 cksum; /* checksum (starting with BD_REV 2) */ -+ u16 rev; /* revision of this struct */ -+#define BD_REV 4 -+ char boardName[64]; /* Name of board */ -+ u16 major; /* Board major number */ -+ u16 minor; /* Board minor number */ -+ u32 flags; /* Board configuration */ -+#define BD_ENET0 0x00000001 /* ENET0 is stuffed */ -+#define BD_ENET1 0x00000002 /* ENET1 is stuffed */ -+#define BD_UART1 0x00000004 /* UART1 is stuffed */ -+#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */ -+#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */ -+#define BD_SYSLED 0x00000020 /* System LED stuffed */ -+#define BD_EXTUARTCLK 0x00000040 /* External UART clock */ -+#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */ -+#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */ -+#define BD_WLAN0 0x00000200 /* Enable WLAN0 */ -+#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ memCap for testing */ -+#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */ -+#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */ -+#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */ -+#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */ -+#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */ -+#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */ -+#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */ -+ u16 resetConfigGpio; /* Reset factory GPIO pin */ -+ u16 sysLedGpio; /* System LED GPIO pin */ -+ -+ u32 cpuFreq; /* CPU core frequency in Hz */ -+ u32 sysFreq; /* System frequency in Hz */ -+ u32 cntFreq; /* Calculated C0_COUNT frequency */ -+ -+ u8 wlan0_mac[6]; -+ u8 enet0_mac[6]; -+ u8 enet1_mac[6]; -+ -+ u16 pciId; /* Pseudo PCIID for common code */ -+ u16 memCap; /* cap bank1 in MB */ -+ -+ /* version 3 */ -+ u8 wlan1_mac[6]; /* (ar5212) */ -+}; -+ -+#define BOARD_CONFIG_BUFSZ 0x1000 -+ -+/* -+ * Platform device information for the Wireless MAC -+ */ -+struct ar231x_board_config { -+ u16 devid; -+ -+ /* board config data */ -+ struct ar231x_boarddata *config; -+ -+ /* radio calibration data */ -+ const char *radio; -+}; -+ -+/* -+ * Platform device information for the Ethernet MAC -+ */ -+struct ar231x_eth { -+ u32 reset_base; -+ u32 reset_mac; -+ u32 reset_phy; -+ u32 phy_base; -+ struct ar231x_board_config *config; -+ char *macaddr; -+}; -+ -+#endif /* __AR531X_PLATFORM_H */ -diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar5312_regs.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar5312_regs.h ---- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar5312_regs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar5312_regs.h 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,236 @@ -+/* -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. -+ * Copyright (C) 2006 Imre Kaloz -+ * Copyright (C) 2006 Felix Fietkau -+ */ -+ -+#ifndef AR5312_H -+#define AR5312_H -+ -+#include -+ -+/* -+ * IRQs -+ */ -+ -+#define AR5312_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */ -+#define AR5312_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */ -+#define AR5312_IRQ_ENET1_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */ -+#define AR5312_IRQ_WLAN1_INTRS MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */ -+#define AR5312_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */ -+ -+ -+/* Address Map */ -+#define AR531X_WLAN0 0x18000000 -+#define AR531X_WLAN1 0x18500000 -+#define AR531X_ENET0 0x18100000 -+#define AR531X_ENET1 0x18200000 -+#define AR531X_SDRAMCTL 0x18300000 -+#define AR531X_FLASHCTL 0x18400000 -+#define AR531X_APBBASE 0x1c000000 -+#define AR531X_FLASH 0x1e000000 -+#define AR531X_UART0 0xbc000003 /* UART MMR */ -+ -+/* -+ * AR531X_NUM_ENET_MAC defines the number of ethernet MACs that -+ * should be considered available. The AR5312 supports 2 enet MACS, -+ * even though many reference boards only actually use 1 of them -+ * (i.e. Only MAC 0 is actually connected to an enet PHY or PHY switch. -+ * The AR2312 supports 1 enet MAC. -+ */ -+#define AR531X_NUM_ENET_MAC 2 -+ -+/* -+ * Need these defines to determine true number of ethernet MACs -+ */ -+#define AR5212_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */ -+#define AR5212_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */ -+#define AR5212_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */ -+#define AR531X_RADIO_MASK_OFF 0xc8 -+#define AR531X_RADIO0_MASK 0x0003 -+#define AR531X_RADIO1_MASK 0x000c -+#define AR531X_RADIO1_S 2 -+ -+/* -+ * AR531X_NUM_WMAC defines the number of Wireless MACs that\ -+ * should be considered available. -+ */ -+#define AR531X_NUM_WMAC 2 -+ -+/* Reset/Timer Block Address Map */ -+#define AR531X_RESETTMR (AR531X_APBBASE + 0x3000) -+#define AR531X_TIMER (AR531X_RESETTMR + 0x0000) /* countdown timer */ -+#define AR531X_WD_CTRL (AR531X_RESETTMR + 0x0008) /* watchdog cntrl */ -+#define AR531X_WD_TIMER (AR531X_RESETTMR + 0x000c) /* watchdog timer */ -+#define AR531X_ISR (AR531X_RESETTMR + 0x0010) /* Intr Status Reg */ -+#define AR531X_IMR (AR531X_RESETTMR + 0x0014) /* Intr Mask Reg */ -+#define AR531X_RESET (AR531X_RESETTMR + 0x0020) -+#define AR5312_CLOCKCTL1 (AR531X_RESETTMR + 0x0064) -+#define AR5312_SCRATCH (AR531X_RESETTMR + 0x006c) -+#define AR531X_PROCADDR (AR531X_RESETTMR + 0x0070) -+#define AR531X_PROC1 (AR531X_RESETTMR + 0x0074) -+#define AR531X_DMAADDR (AR531X_RESETTMR + 0x0078) -+#define AR531X_DMA1 (AR531X_RESETTMR + 0x007c) -+#define AR531X_ENABLE (AR531X_RESETTMR + 0x0080) /* interface enb */ -+#define AR531X_REV (AR531X_RESETTMR + 0x0090) /* revision */ -+ -+/* AR531X_WD_CTRL register bit field definitions */ -+#define AR531X_WD_CTRL_IGNORE_EXPIRATION 0x0000 -+#define AR531X_WD_CTRL_NMI 0x0001 -+#define AR531X_WD_CTRL_RESET 0x0002 -+ -+/* AR531X_ISR register bit field definitions */ -+#define AR531X_ISR_NONE 0x0000 -+#define AR531X_ISR_TIMER 0x0001 -+#define AR531X_ISR_AHBPROC 0x0002 -+#define AR531X_ISR_AHBDMA 0x0004 -+#define AR531X_ISR_GPIO 0x0008 -+#define AR531X_ISR_UART0 0x0010 -+#define AR531X_ISR_UART0DMA 0x0020 -+#define AR531X_ISR_WD 0x0040 -+#define AR531X_ISR_LOCAL 0x0080 -+ -+/* AR531X_RESET register bit field definitions */ -+#define AR531X_RESET_SYSTEM 0x00000001 /* cold reset full system */ -+#define AR531X_RESET_PROC 0x00000002 /* cold reset MIPS core */ -+#define AR531X_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */ -+#define AR531X_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */ -+#define AR531X_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */ -+#define AR531X_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */ -+#define AR531X_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */ -+#define AR531X_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */ -+#define AR531X_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */ -+#define AR531X_RESET_APB 0x00000400 /* cold reset APB (ar5312) */ -+#define AR531X_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */ -+#define AR531X_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */ -+#define AR531X_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */ -+#define AR531X_RESET_NMI 0x00010000 /* send an NMI to the processor */ -+#define AR531X_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */ -+#define AR531X_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */ -+#define AR531X_RESET_LOCAL_BUS 0x00080000 /* reset local bus */ -+#define AR531X_RESET_WDOG 0x00100000 /* last reset was a watchdog */ -+ -+#define AR531X_RESET_WMAC0_BITS \ -+ AR531X_RESET_WLAN0 |\ -+ AR531X_RESET_WARM_WLAN0_MAC |\ -+ AR531X_RESET_WARM_WLAN0_BB -+ -+#define AR531X_RESERT_WMAC1_BITS \ -+ AR531X_RESET_WLAN1 |\ -+ AR531X_RESET_WARM_WLAN1_MAC |\ -+ AR531X_RESET_WARM_WLAN1_BB -+ -+/* AR5312_CLOCKCTL1 register bit field definitions */ -+#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030 -+#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4 -+#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00 -+#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8 -+#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000 -+ -+/* Valid for AR5312 and AR2312 */ -+#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030 -+#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4 -+#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00 -+#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8 -+#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000 -+ -+/* Valid for AR2313 */ -+#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000 -+#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12 -+#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000 -+#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16 -+#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000 -+ -+ -+/* AR531X_ENABLE register bit field definitions */ -+#define AR531X_ENABLE_WLAN0 0x0001 -+#define AR531X_ENABLE_ENET0 0x0002 -+#define AR531X_ENABLE_ENET1 0x0004 -+#define AR531X_ENABLE_UART_AND_WLAN1_PIO 0x0008 /* UART, and WLAN1 PIOs */ -+#define AR531X_ENABLE_WLAN1_DMA 0x0010 /* WLAN1 DMAs */ -+#define AR531X_ENABLE_WLAN1 \ -+ (AR531X_ENABLE_UART_AND_WLAN1_PIO | AR531X_ENABLE_WLAN1_DMA) -+ -+/* AR531X_REV register bit field definitions */ -+#define AR531X_REV_WMAC_MAJ 0xf000 -+#define AR531X_REV_WMAC_MAJ_S 12 -+#define AR531X_REV_WMAC_MIN 0x0f00 -+#define AR531X_REV_WMAC_MIN_S 8 -+#define AR531X_REV_MAJ 0x00f0 -+#define AR531X_REV_MAJ_S 4 -+#define AR531X_REV_MIN 0x000f -+#define AR531X_REV_MIN_S 0 -+#define AR531X_REV_CHIP (AR531X_REV_MAJ|AR531X_REV_MIN) -+ -+/* Major revision numbers, bits 7..4 of Revision ID register */ -+#define AR531X_REV_MAJ_AR5312 0x4 -+#define AR531X_REV_MAJ_AR2313 0x5 -+ -+/* Minor revision numbers, bits 3..0 of Revision ID register */ -+#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */ -+#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */ -+ -+/* AR531X_FLASHCTL register bit field definitions */ -+#define FLASHCTL_IDCY 0x0000000f /* Idle cycle turn around time */ -+#define FLASHCTL_IDCY_S 0 -+#define FLASHCTL_WST1 0x000003e0 /* Wait state 1 */ -+#define FLASHCTL_WST1_S 5 -+#define FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */ -+#define FLASHCTL_WST2 0x0000f800 /* Wait state 2 */ -+#define FLASHCTL_WST2_S 11 -+#define FLASHCTL_AC 0x00070000 /* Flash address check (added) */ -+#define FLASHCTL_AC_S 16 -+#define FLASHCTL_AC_128K 0x00000000 -+#define FLASHCTL_AC_256K 0x00010000 -+#define FLASHCTL_AC_512K 0x00020000 -+#define FLASHCTL_AC_1M 0x00030000 -+#define FLASHCTL_AC_2M 0x00040000 -+#define FLASHCTL_AC_4M 0x00050000 -+#define FLASHCTL_AC_8M 0x00060000 -+#define FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */ -+#define FLASHCTL_E 0x00080000 /* Flash bank enable (added) */ -+#define FLASHCTL_BUSERR 0x01000000 /* Bus transfer error status flag */ -+#define FLASHCTL_WPERR 0x02000000 /* Write protect error status flag */ -+#define FLASHCTL_WP 0x04000000 /* Write protect */ -+#define FLASHCTL_BM 0x08000000 /* Burst mode */ -+#define FLASHCTL_MW 0x30000000 /* Memory width */ -+#define FLASHCTL_MWx8 0x00000000 /* Memory width x8 */ -+#define FLASHCTL_MWx16 0x10000000 /* Memory width x16 */ -+#define FLASHCTL_MWx32 0x20000000 /* Memory width x32 (not supported) */ -+#define FLASHCTL_ATNR 0x00000000 /* Access type == no retry */ -+#define FLASHCTL_ATR 0x80000000 /* Access type == retry every */ -+#define FLASHCTL_ATR4 0xc0000000 /* Access type == retry every 4 */ -+ -+/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */ -+#define AR531X_FLASHCTL0 (AR531X_FLASHCTL + 0x00) -+#define AR531X_FLASHCTL1 (AR531X_FLASHCTL + 0x04) -+#define AR531X_FLASHCTL2 (AR531X_FLASHCTL + 0x08) -+ -+/* ARM SDRAM Controller -- just enough to determine memory size */ -+#define AR531X_MEM_CFG1 (AR531X_SDRAMCTL + 0x04) -+#define MEM_CFG1_AC0 0x00000700 /* bank 0: SDRAM addr check (added) */ -+#define MEM_CFG1_AC0_S 8 -+#define MEM_CFG1_AC1 0x00007000 /* bank 1: SDRAM addr check (added) */ -+#define MEM_CFG1_AC1_S 12 -+ -+/* GPIO Address Map */ -+#define AR531X_GPIO (AR531X_APBBASE + 0x2000) -+#define AR531X_GPIO_DO (AR531X_GPIO + 0x00) /* output register */ -+#define AR531X_GPIO_DI (AR531X_GPIO + 0x04) /* intput register */ -+#define AR531X_GPIO_CR (AR531X_GPIO + 0x08) /* control register */ -+ -+/* GPIO Control Register bit field definitions */ -+#define AR531X_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */ -+#define AR531X_GPIO_CR_O(x) (0 << (x)) /* mask for output */ -+#define AR531X_GPIO_CR_I(x) (1 << (x)) /* mask for input */ -+#define AR531X_GPIO_CR_INT(x) (1 << ((x)+8)) /* mask for interrupt */ -+#define AR531X_GPIO_CR_UART(x) (1 << ((x)+16)) /* uart multiplex */ -+#define AR531X_NUM_GPIO 8 -+ -+ -+#endif -+ -diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h ---- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,84 @@ -+/* -+ * Atheros SoC specific CPU feature overrides -+ * -+ * Copyright (C) 2008 Gabor Juhos -+ * -+ * This file was derived from: include/asm-mips/cpu-features.h -+ * Copyright (C) 2003, 2004 Ralf Baechle -+ * Copyright (C) 2004 Maciej W. Rozycki -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ */ -+#ifndef __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H -+#define __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H -+ -+/* -+ * The ATHEROS SoCs have MIPS 4Kc/4KEc core. -+ */ -+#define cpu_has_tlb 1 -+#define cpu_has_4kex 1 -+#define cpu_has_3k_cache 0 -+#define cpu_has_4k_cache 1 -+#define cpu_has_tx39_cache 0 -+#define cpu_has_sb1_cache 0 -+#define cpu_has_fpu 0 -+#define cpu_has_32fpr 0 -+#define cpu_has_counter 1 -+/* #define cpu_has_watch ? */ -+/* #define cpu_has_divec ? */ -+/* #define cpu_has_vce ? */ -+/* #define cpu_has_cache_cdex_p ? */ -+/* #define cpu_has_cache_cdex_s ? */ -+/* #define cpu_has_prefetch ? */ -+/* #define cpu_has_mcheck ? */ -+#define cpu_has_ejtag 1 -+ -+#if !defined(CONFIG_ATHEROS_AR5312) -+# define cpu_has_llsc 1 -+#else -+/* -+ * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the -+ * ll/sc instructions. -+ */ -+# define cpu_has_llsc 0 -+#endif -+ -+#define cpu_has_mips16 0 -+#define cpu_has_mdmx 0 -+#define cpu_has_mips3d 0 -+#define cpu_has_smartmips 0 -+ -+/* #define cpu_has_vtag_icache ? */ -+/* #define cpu_has_dc_aliases ? */ -+/* #define cpu_has_ic_fills_f_dc ? */ -+/* #define cpu_has_pindexed_dcache ? */ -+ -+/* #define cpu_icache_snoops_remote_store ? */ -+ -+#define cpu_has_mips32r1 1 -+ -+#if !defined(CONFIG_ATHEROS_AR5312) -+# define cpu_has_mips32r2 1 -+#endif -+ -+#define cpu_has_mips64r1 0 -+#define cpu_has_mips64r2 0 -+ -+#define cpu_has_dsp 0 -+#define cpu_has_mipsmt 0 -+ -+/* #define cpu_has_nofpuex ? */ -+#define cpu_has_64bits 0 -+#define cpu_has_64bit_zero_reg 0 -+#define cpu_has_64bit_gp_regs 0 -+#define cpu_has_64bit_addresses 0 -+ -+/* #define cpu_has_inclusive_pcaches ? */ -+ -+/* #define cpu_dcache_line_size() ? */ -+/* #define cpu_icache_line_size() ? */ -+ -+#endif /* __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H */ -diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/dma-coherence.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/dma-coherence.h ---- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/dma-coherence.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/dma-coherence.h 2011-05-15 21:41:19.000000000 +0200 -@@ -0,0 +1,76 @@ -+/* -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 2006 Ralf Baechle -+ * Copyright (C) 2007 Felix Fietkau -+ * -+ */ -+#ifndef __ASM_MACH_GENERIC_DMA_COHERENCE_H -+#define __ASM_MACH_GENERIC_DMA_COHERENCE_H -+ -+#define PCI_DMA_OFFSET 0x20000000 -+ -+#include -+ -+static inline dma_addr_t ar231x_dev_offset(struct device *dev) -+{ -+#ifdef CONFIG_PCI -+ extern struct bus_type pci_bus_type; -+ -+ if (dev && dev->bus == &pci_bus_type) -+ return PCI_DMA_OFFSET; -+ else -+#endif -+ return 0; -+} -+ -+static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size) -+{ -+ return virt_to_phys(addr) + ar231x_dev_offset(dev); -+} -+ -+static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page) -+{ -+ return page_to_phys(page) + ar231x_dev_offset(dev); -+} -+ -+static inline unsigned long plat_dma_addr_to_phys(struct device *dev, -+ dma_addr_t dma_addr) -+{ -+ return dma_addr - ar231x_dev_offset(dev); -+} -+ -+static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, -+ size_t size, enum dma_data_direction direction) -+{ -+} -+ -+static inline int plat_dma_supported(struct device *dev, u64 mask) -+{ -+ return 1; -+} -+ -+static inline void plat_extra_sync_for_device(struct device *dev) -+{ -+ return; -+} -+ -+static inline int plat_dma_mapping_error(struct device *dev, -+ dma_addr_t dma_addr) -+{ -+ return 0; -+} -+ -+static inline int plat_device_is_coherent(struct device *dev) -+{ -+#ifdef CONFIG_DMA_COHERENT -+ return 1; -+#endif -+#ifdef CONFIG_DMA_NONCOHERENT -+ return 0; -+#endif -+} -+ -+#endif /* __ASM_MACH_GENERIC_DMA_COHERENCE_H */ -diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/gpio.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/gpio.h ---- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/gpio.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/gpio.h 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,84 @@ -+#ifndef _ATHEROS_GPIO_H_ -+#define _ATHEROS_GPIO_H_ -+ -+#include -+ -+struct ar231x_gpiodev { -+ u32 valid_mask; -+ u32 (*get_output)(void); -+ u32 (*set_output)(u32 mask, u32 val); -+ u32 (*get)(void); -+ u32 (*set)(u32 mask, u32 val); -+}; -+ -+extern const struct ar231x_gpiodev *ar231x_gpiodev; -+ -+/* -+ * Wrappers for the generic GPIO layer -+ */ -+ -+static inline int gpio_direction_input(unsigned gpio) { -+ u32 mask = 1 << gpio; -+ -+ if (!(ar231x_gpiodev->valid_mask & mask)) -+ return -ENXIO; -+ -+ ar231x_gpiodev->set_output(mask, 0); -+ return 0; -+} -+ -+static inline void gpio_set_value(unsigned gpio, int value) { -+ u32 mask = 1 << gpio; -+ -+ if (!(ar231x_gpiodev->valid_mask & mask)) -+ return; -+ -+ ar231x_gpiodev->set(mask, (!!value) * mask); -+} -+ -+static inline int gpio_direction_output(unsigned gpio, int value) { -+ u32 mask = 1 << gpio; -+ -+ if (!(ar231x_gpiodev->valid_mask & mask)) -+ return -ENXIO; -+ -+ ar231x_gpiodev->set_output(mask, mask); -+ ar231x_gpiodev->set(mask, (!!value) * mask); -+ return 0; -+} -+ -+/* Reads the gpio pin. Unchecked function */ -+static inline int gpio_get_value(unsigned gpio) { -+ u32 mask = 1 << gpio; -+ -+ if (!(ar231x_gpiodev->valid_mask & mask)) -+ return 0; -+ -+ return !!(ar231x_gpiodev->get() & mask); -+} -+ -+static inline int gpio_request(unsigned gpio, const char *label) { -+ return 0; -+} -+ -+static inline void gpio_free(unsigned gpio) { -+} -+ -+/* Returns IRQ to attach for gpio. Unchecked function */ -+static inline int gpio_to_irq(unsigned gpio) { -+ return AR531X_GPIO_IRQ(gpio); -+} -+ -+/* Returns gpio for IRQ attached. Unchecked function */ -+static inline int irq_to_gpio(unsigned irq) { -+ return (irq - (AR531X_GPIO_IRQ(0))); -+} -+ -+static inline int gpio_set_debounce(unsigned gpio, unsigned debounce) -+{ -+ return -ENOSYS; -+} -+ -+#include /* cansleep wrappers */ -+ -+#endif -diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/reset.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/reset.h ---- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/reset.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/reset.h 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,6 @@ -+#ifndef __AR531X_RESET_H -+#define __AR531X_RESET_H -+ -+void ar531x_disable_reset_button(void); -+ -+#endif /* __AR531X_RESET_H */ -diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/war.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/war.h ---- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/war.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/war.h 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,25 @@ -+/* -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 2008 Felix Fietkau -+ */ -+#ifndef __ASM_MIPS_MACH_ATHEROS_WAR_H -+#define __ASM_MIPS_MACH_ATHEROS_WAR_H -+ -+#define R4600_V1_INDEX_ICACHEOP_WAR 0 -+#define R4600_V1_HIT_CACHEOP_WAR 0 -+#define R4600_V2_HIT_CACHEOP_WAR 0 -+#define R5432_CP0_INTERRUPT_WAR 0 -+#define BCM1250_M3_WAR 0 -+#define SIBYTE_1956_WAR 0 -+#define MIPS4K_ICACHE_REFILL_WAR 0 -+#define MIPS_CACHE_SYNC_WAR 0 -+#define TX49XX_ICACHE_INDEX_INV_WAR 0 -+#define RM9000_CDEX_SMP_WAR 0 -+#define ICACHE_REFILLS_WORKAROUND_WAR 0 -+#define R10000_LLSC_WAR 0 -+#define MIPS34K_MISSED_ITLB_WAR 0 -+ -+#endif /* __ASM_MIPS_MACH_ATHEROS_WAR_H */ -diff -Nur linux-2.6.39-rc7.orig/arch/mips/kernel/cevt-r4k.c linux-2.6.39-rc7/arch/mips/kernel/cevt-r4k.c ---- linux-2.6.39-rc7.orig/arch/mips/kernel/cevt-r4k.c 2011-05-10 04:33:54.000000000 +0200 -+++ linux-2.6.39-rc7/arch/mips/kernel/cevt-r4k.c 2011-05-15 21:34:57.000000000 +0200 -@@ -168,20 +168,23 @@ - struct clock_event_device *cd; - unsigned int irq; - -- if (!cpu_has_counter || !mips_hpt_frequency) -- return -ENXIO; -- -- if (!c0_compare_int_usable()) -- return -ENXIO; -- - /* - * With vectored interrupts things are getting platform specific. - * get_c0_compare_int is a hook to allow a platform to return the - * interrupt number of it's liking. - */ - irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; -- if (get_c0_compare_int) -+ if (get_c0_compare_int) { - irq = get_c0_compare_int(); -+ if ((irq >= MIPS_CPU_IRQ_BASE) && (irq < MIPS_CPU_IRQ_BASE + 8)) -+ cp0_compare_irq = irq - MIPS_CPU_IRQ_BASE; -+ } -+ -+ if (!cpu_has_counter || !mips_hpt_frequency) -+ return -ENXIO; -+ -+ if (!c0_compare_int_usable()) -+ return -ENXIO; - - cd = &per_cpu(mips_clockevent_device, cpu); - -diff -Nur linux-2.6.39-rc7.orig/drivers/mtd/devices/Kconfig linux-2.6.39-rc7/drivers/mtd/devices/Kconfig ---- linux-2.6.39-rc7.orig/drivers/mtd/devices/Kconfig 2011-05-10 04:33:54.000000000 +0200 -+++ linux-2.6.39-rc7/drivers/mtd/devices/Kconfig 2011-05-15 21:34:57.000000000 +0200 -@@ -112,6 +112,10 @@ - Set up your spi devices with the right board-specific platform data, - if you want to specify device partitioning. - -+config MTD_AR2315 -+ tristate "Atheros AR2315+ SPI Flash support" -+ depends on ATHEROS_AR2315 -+ - config MTD_SLRAM - tristate "Uncached system RAM" - help -diff -Nur linux-2.6.39-rc7.orig/drivers/mtd/devices/Makefile linux-2.6.39-rc7/drivers/mtd/devices/Makefile ---- linux-2.6.39-rc7.orig/drivers/mtd/devices/Makefile 2011-05-10 04:33:54.000000000 +0200 -+++ linux-2.6.39-rc7/drivers/mtd/devices/Makefile 2011-05-15 21:34:57.000000000 +0200 -@@ -17,3 +17,4 @@ - obj-$(CONFIG_MTD_DATAFLASH) += mtd_dataflash.o - obj-$(CONFIG_MTD_M25P80) += m25p80.o - obj-$(CONFIG_MTD_SST25L) += sst25l.o -+obj-$(CONFIG_MTD_AR2315) += ar2315.o -diff -Nur linux-2.6.39-rc7.orig/drivers/mtd/devices/ar2315.c linux-2.6.39-rc7/drivers/mtd/devices/ar2315.c ---- linux-2.6.39-rc7.orig/drivers/mtd/devices/ar2315.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/drivers/mtd/devices/ar2315.c 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,517 @@ -+ -+/* -+ * MTD driver for the SPI Flash Memory support on Atheros AR2315 -+ * -+ * Copyright (c) 2005-2006 Atheros Communications Inc. -+ * Copyright (C) 2006-2007 FON Technology, SL. -+ * Copyright (C) 2006-2007 Imre Kaloz -+ * Copyright (C) 2006-2009 Felix Fietkau -+ * -+ * This code is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+ -+#define SPIFLASH "spiflash: " -+#define busy_wait(_priv, _condition, _wait) do { \ -+ while (_condition) { \ -+ spin_unlock_bh(&_priv->lock); \ -+ if (_wait > 1) \ -+ msleep(_wait); \ -+ else if ((_wait == 1) && need_resched()) \ -+ schedule(); \ -+ else \ -+ udelay(1); \ -+ spin_lock_bh(&_priv->lock); \ -+ } \ -+} while (0) -+ -+enum { -+ FLASH_NONE, -+ FLASH_1MB, -+ FLASH_2MB, -+ FLASH_4MB, -+ FLASH_8MB, -+ FLASH_16MB, -+}; -+ -+/* Flash configuration table */ -+struct flashconfig { -+ u32 byte_cnt; -+ u32 sector_cnt; -+ u32 sector_size; -+}; -+ -+const struct flashconfig flashconfig_tbl[] = { -+ [FLASH_NONE] = { 0, 0, 0}, -+ [FLASH_1MB] = { STM_1MB_BYTE_COUNT, STM_1MB_SECTOR_COUNT, STM_1MB_SECTOR_SIZE}, -+ [FLASH_2MB] = { STM_2MB_BYTE_COUNT, STM_2MB_SECTOR_COUNT, STM_2MB_SECTOR_SIZE}, -+ [FLASH_4MB] = { STM_4MB_BYTE_COUNT, STM_4MB_SECTOR_COUNT, STM_4MB_SECTOR_SIZE}, -+ [FLASH_8MB] = { STM_8MB_BYTE_COUNT, STM_8MB_SECTOR_COUNT, STM_8MB_SECTOR_SIZE}, -+ [FLASH_16MB] = { STM_16MB_BYTE_COUNT, STM_16MB_SECTOR_COUNT, STM_16MB_SECTOR_SIZE} -+}; -+ -+/* Mapping of generic opcodes to STM serial flash opcodes */ -+enum { -+ SPI_WRITE_ENABLE, -+ SPI_WRITE_DISABLE, -+ SPI_RD_STATUS, -+ SPI_WR_STATUS, -+ SPI_RD_DATA, -+ SPI_FAST_RD_DATA, -+ SPI_PAGE_PROGRAM, -+ SPI_SECTOR_ERASE, -+ SPI_BULK_ERASE, -+ SPI_DEEP_PWRDOWN, -+ SPI_RD_SIG, -+}; -+ -+struct opcodes { -+ __u16 code; -+ __s8 tx_cnt; -+ __s8 rx_cnt; -+}; -+const struct opcodes stm_opcodes[] = { -+ [SPI_WRITE_ENABLE] = {STM_OP_WR_ENABLE, 1, 0}, -+ [SPI_WRITE_DISABLE] = {STM_OP_WR_DISABLE, 1, 0}, -+ [SPI_RD_STATUS] = {STM_OP_RD_STATUS, 1, 1}, -+ [SPI_WR_STATUS] = {STM_OP_WR_STATUS, 1, 0}, -+ [SPI_RD_DATA] = {STM_OP_RD_DATA, 4, 4}, -+ [SPI_FAST_RD_DATA] = {STM_OP_FAST_RD_DATA, 5, 0}, -+ [SPI_PAGE_PROGRAM] = {STM_OP_PAGE_PGRM, 8, 0}, -+ [SPI_SECTOR_ERASE] = {STM_OP_SECTOR_ERASE, 4, 0}, -+ [SPI_BULK_ERASE] = {STM_OP_BULK_ERASE, 1, 0}, -+ [SPI_DEEP_PWRDOWN] = {STM_OP_DEEP_PWRDOWN, 1, 0}, -+ [SPI_RD_SIG] = {STM_OP_RD_SIG, 4, 1}, -+}; -+ -+/* Driver private data structure */ -+struct spiflash_priv { -+ struct mtd_info mtd; -+ void *readaddr; /* memory mapped data for read */ -+ void *mmraddr; /* memory mapped register space */ -+ wait_queue_head_t wq; -+ spinlock_t lock; -+ int state; -+}; -+ -+#define to_spiflash(_mtd) container_of(_mtd, struct spiflash_priv, mtd) -+ -+enum { -+ FL_READY, -+ FL_READING, -+ FL_ERASING, -+ FL_WRITING -+}; -+ -+/***************************************************************************************************/ -+ -+static u32 -+spiflash_read_reg(struct spiflash_priv *priv, int reg) -+{ -+ return ar231x_read_reg((u32) priv->mmraddr + reg); -+} -+ -+static void -+spiflash_write_reg(struct spiflash_priv *priv, int reg, u32 data) -+{ -+ ar231x_write_reg((u32) priv->mmraddr + reg, data); -+} -+ -+static u32 -+spiflash_wait_busy(struct spiflash_priv *priv) -+{ -+ u32 reg; -+ -+ busy_wait(priv, (reg = spiflash_read_reg(priv, SPI_FLASH_CTL)) & -+ SPI_CTL_BUSY, 0); -+ return reg; -+} -+ -+static u32 -+spiflash_sendcmd (struct spiflash_priv *priv, int opcode, u32 addr) -+{ -+ const struct opcodes *op; -+ u32 reg, mask; -+ -+ op = &stm_opcodes[opcode]; -+ reg = spiflash_wait_busy(priv); -+ spiflash_write_reg(priv, SPI_FLASH_OPCODE, -+ ((u32) op->code) | (addr << 8)); -+ -+ reg &= ~SPI_CTL_TX_RX_CNT_MASK; -+ reg |= SPI_CTL_START | op->tx_cnt | (op->rx_cnt << 4); -+ -+ spiflash_write_reg(priv, SPI_FLASH_CTL, reg); -+ spiflash_wait_busy(priv); -+ -+ if (!op->rx_cnt) -+ return 0; -+ -+ reg = spiflash_read_reg(priv, SPI_FLASH_DATA); -+ -+ switch (op->rx_cnt) { -+ case 1: -+ mask = 0x000000ff; -+ break; -+ case 2: -+ mask = 0x0000ffff; -+ break; -+ case 3: -+ mask = 0x00ffffff; -+ break; -+ default: -+ mask = 0xffffffff; -+ break; -+ } -+ reg &= mask; -+ -+ return reg; -+} -+ -+ -+/* -+ * Probe SPI flash device -+ * Function returns 0 for failure. -+ * and flashconfig_tbl array index for success. -+ */ -+static int -+spiflash_probe_chip (struct spiflash_priv *priv) -+{ -+ u32 sig; -+ int flash_size; -+ -+ /* Read the signature on the flash device */ -+ spin_lock_bh(&priv->lock); -+ sig = spiflash_sendcmd(priv, SPI_RD_SIG, 0); -+ spin_unlock_bh(&priv->lock); -+ -+ switch (sig) { -+ case STM_8MBIT_SIGNATURE: -+ flash_size = FLASH_1MB; -+ break; -+ case STM_16MBIT_SIGNATURE: -+ flash_size = FLASH_2MB; -+ break; -+ case STM_32MBIT_SIGNATURE: -+ flash_size = FLASH_4MB; -+ break; -+ case STM_64MBIT_SIGNATURE: -+ flash_size = FLASH_8MB; -+ break; -+ case STM_128MBIT_SIGNATURE: -+ flash_size = FLASH_16MB; -+ break; -+ default: -+ printk (KERN_WARNING SPIFLASH "Read of flash device signature failed!\n"); -+ return 0; -+ } -+ -+ return flash_size; -+} -+ -+ -+/* wait until the flash chip is ready and grab a lock */ -+static int spiflash_wait_ready(struct spiflash_priv *priv, int state) -+{ -+ DECLARE_WAITQUEUE(wait, current); -+ -+retry: -+ spin_lock_bh(&priv->lock); -+ if (priv->state != FL_READY) { -+ set_current_state(TASK_UNINTERRUPTIBLE); -+ add_wait_queue(&priv->wq, &wait); -+ spin_unlock_bh(&priv->lock); -+ schedule(); -+ remove_wait_queue(&priv->wq, &wait); -+ -+ if(signal_pending(current)) -+ return 0; -+ -+ goto retry; -+ } -+ priv->state = state; -+ -+ return 1; -+} -+ -+static inline void spiflash_done(struct spiflash_priv *priv) -+{ -+ priv->state = FL_READY; -+ spin_unlock_bh(&priv->lock); -+ wake_up(&priv->wq); -+} -+ -+static void -+spiflash_wait_complete(struct spiflash_priv *priv, unsigned int timeout) -+{ -+ busy_wait(priv, spiflash_sendcmd(priv, SPI_RD_STATUS, 0) & -+ SPI_STATUS_WIP, timeout); -+ spiflash_done(priv); -+} -+ -+ -+ -+static int -+spiflash_erase (struct mtd_info *mtd, struct erase_info *instr) -+{ -+ struct spiflash_priv *priv = to_spiflash(mtd); -+ const struct opcodes *op; -+ u32 temp, reg; -+ -+ if (instr->addr + instr->len > mtd->size) -+ return -EINVAL; -+ -+ if (!spiflash_wait_ready(priv, FL_ERASING)) -+ return -EINTR; -+ -+ spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0); -+ reg = spiflash_wait_busy(priv); -+ -+ op = &stm_opcodes[SPI_SECTOR_ERASE]; -+ temp = ((u32)instr->addr << 8) | (u32)(op->code); -+ spiflash_write_reg(priv, SPI_FLASH_OPCODE, temp); -+ -+ reg &= ~SPI_CTL_TX_RX_CNT_MASK; -+ reg |= op->tx_cnt | SPI_CTL_START; -+ spiflash_write_reg(priv, SPI_FLASH_CTL, reg); -+ -+ spiflash_wait_complete(priv, 20); -+ -+ instr->state = MTD_ERASE_DONE; -+ mtd_erase_callback(instr); -+ -+ return 0; -+} -+ -+static int -+spiflash_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf) -+{ -+ struct spiflash_priv *priv = to_spiflash(mtd); -+ u8 *read_addr; -+ -+ if (!len) -+ return 0; -+ -+ if (from + len > mtd->size) -+ return -EINVAL; -+ -+ *retlen = len; -+ -+ if (!spiflash_wait_ready(priv, FL_READING)) -+ return -EINTR; -+ -+ read_addr = (u8 *)(priv->readaddr + from); -+ memcpy_fromio(buf, read_addr, len); -+ spiflash_done(priv); -+ -+ return 0; -+} -+ -+static int -+spiflash_write (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u8 *buf) -+{ -+ struct spiflash_priv *priv = to_spiflash(mtd); -+ u32 opcode, bytes_left; -+ -+ *retlen = 0; -+ -+ if (!len) -+ return 0; -+ -+ if (to + len > mtd->size) -+ return -EINVAL; -+ -+ bytes_left = len; -+ -+ do { -+ u32 read_len, reg, page_offset, spi_data = 0; -+ -+ read_len = min(bytes_left, sizeof(u32)); -+ -+ /* 32-bit writes cannot span across a page boundary -+ * (256 bytes). This types of writes require two page -+ * program operations to handle it correctly. The STM part -+ * will write the overflow data to the beginning of the -+ * current page as opposed to the subsequent page. -+ */ -+ page_offset = (to & (STM_PAGE_SIZE - 1)) + read_len; -+ -+ if (page_offset > STM_PAGE_SIZE) -+ read_len -= (page_offset - STM_PAGE_SIZE); -+ -+ if (!spiflash_wait_ready(priv, FL_WRITING)) -+ return -EINTR; -+ -+ spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0); -+ spi_data = 0; -+ switch (read_len) { -+ case 4: -+ spi_data |= buf[3] << 24; -+ /* fall through */ -+ case 3: -+ spi_data |= buf[2] << 16; -+ /* fall through */ -+ case 2: -+ spi_data |= buf[1] << 8; -+ /* fall through */ -+ case 1: -+ spi_data |= buf[0] & 0xff; -+ break; -+ default: -+ break; -+ } -+ -+ spiflash_write_reg(priv, SPI_FLASH_DATA, spi_data); -+ opcode = stm_opcodes[SPI_PAGE_PROGRAM].code | -+ (to & 0x00ffffff) << 8; -+ spiflash_write_reg(priv, SPI_FLASH_OPCODE, opcode); -+ -+ reg = spiflash_read_reg(priv, SPI_FLASH_CTL); -+ reg &= ~SPI_CTL_TX_RX_CNT_MASK; -+ reg |= (read_len + 4) | SPI_CTL_START; -+ spiflash_write_reg(priv, SPI_FLASH_CTL, reg); -+ -+ spiflash_wait_complete(priv, 1); -+ -+ bytes_left -= read_len; -+ to += read_len; -+ buf += read_len; -+ -+ *retlen += read_len; -+ } while (bytes_left != 0); -+ -+ return 0; -+} -+ -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static const char *part_probe_types[] = { "cmdlinepart", "RedBoot", "MyLoader", NULL }; -+#endif -+ -+ -+static int -+spiflash_probe(struct platform_device *pdev) -+{ -+ struct spiflash_priv *priv; -+ struct mtd_partition *parts; -+ struct mtd_info *mtd; -+ int index, num_parts; -+ int result = 0; -+ -+ priv = kzalloc(sizeof(struct spiflash_priv), GFP_KERNEL); -+ spin_lock_init(&priv->lock); -+ init_waitqueue_head(&priv->wq); -+ priv->state = FL_READY; -+ mtd = &priv->mtd; -+ -+ priv->mmraddr = ioremap_nocache(SPI_FLASH_MMR, SPI_FLASH_MMR_SIZE); -+ if (!priv->mmraddr) { -+ printk(KERN_WARNING SPIFLASH "Failed to map flash device\n"); -+ goto error; -+ } -+ -+ index = spiflash_probe_chip(priv); -+ if (!index) { -+ printk (KERN_WARNING SPIFLASH "Found no serial flash device\n"); -+ goto error; -+ } -+ -+ priv->readaddr = ioremap_nocache(SPI_FLASH_READ, flashconfig_tbl[index].byte_cnt); -+ if (!priv->readaddr) { -+ printk (KERN_WARNING SPIFLASH "Failed to map flash device\n"); -+ goto error; -+ } -+ -+ platform_set_drvdata(pdev, priv); -+ mtd->name = "spiflash"; -+ mtd->type = MTD_NORFLASH; -+ mtd->flags = (MTD_CAP_NORFLASH|MTD_WRITEABLE); -+ mtd->size = flashconfig_tbl[index].byte_cnt; -+ mtd->erasesize = flashconfig_tbl[index].sector_size; -+ mtd->writesize = 1; -+ mtd->numeraseregions = 0; -+ mtd->eraseregions = NULL; -+ mtd->erase = spiflash_erase; -+ mtd->read = spiflash_read; -+ mtd->write = spiflash_write; -+ mtd->owner = THIS_MODULE; -+ -+#ifdef CONFIG_MTD_PARTITIONS -+ /* parse redboot partitions */ -+ num_parts = parse_mtd_partitions(mtd, part_probe_types, &parts, 0); -+ if (!num_parts) -+ goto error; -+ -+ result = add_mtd_partitions(mtd, parts, num_parts); -+#endif -+ -+ return result; -+ -+error: -+ if (priv->mmraddr) -+ iounmap(priv->mmraddr); -+ kfree(priv); -+ return -ENXIO; -+} -+ -+static int -+spiflash_remove (struct platform_device *pdev) -+{ -+ struct spiflash_priv *priv = platform_get_drvdata(pdev); -+ struct mtd_info *mtd = &priv->mtd; -+ -+ del_mtd_partitions(mtd); -+ iounmap(priv->mmraddr); -+ iounmap(priv->readaddr); -+ kfree(priv); -+ -+ return 0; -+} -+ -+struct platform_driver spiflash_driver = { -+ .driver.name = "spiflash", -+ .probe = spiflash_probe, -+ .remove = spiflash_remove, -+}; -+ -+int __init -+spiflash_init (void) -+{ -+ return platform_driver_register(&spiflash_driver); -+} -+ -+void __exit -+spiflash_exit (void) -+{ -+ return platform_driver_unregister(&spiflash_driver); -+} -+ -+module_init (spiflash_init); -+module_exit (spiflash_exit); -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("OpenWrt.org, Atheros Communications Inc"); -+MODULE_DESCRIPTION("MTD driver for SPI Flash on Atheros SOC"); -+ -diff -Nur linux-2.6.39-rc7.orig/drivers/mtd/redboot.c linux-2.6.39-rc7/drivers/mtd/redboot.c ---- linux-2.6.39-rc7.orig/drivers/mtd/redboot.c 2011-05-10 04:33:54.000000000 +0200 -+++ linux-2.6.39-rc7/drivers/mtd/redboot.c 2011-05-15 21:34:57.000000000 +0200 -@@ -55,6 +55,22 @@ - return 1; - } - -+static uint32_t mtd_get_offset_erasesize(struct mtd_info *mtd, uint64_t offset) -+{ -+ struct mtd_erase_region_info *regions = mtd->eraseregions; -+ int i; -+ -+ for (i = 0; i < mtd->numeraseregions; i++) { -+ if (regions[i].offset + -+ regions[i].numblocks * regions[i].erasesize <= offset) -+ continue; -+ -+ return regions[i].erasesize; -+ } -+ -+ return mtd->erasesize; -+} -+ - static int parse_redboot_partitions(struct mtd_info *master, - struct mtd_partition **pparts, - unsigned long fis_origin) -@@ -70,36 +86,38 @@ - int namelen = 0; - int nulllen = 0; - int numslots; -+ int first_slot; - unsigned long offset; - #ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED - static char nullstring[] = "unallocated"; - #endif - -+ buf = vmalloc(master->erasesize); -+ if (!buf) -+ return -ENOMEM; -+ -+ restart: - if ( directory < 0 ) { - offset = master->size + directory * master->erasesize; -- while (master->block_isbad && -+ while (master->block_isbad && - master->block_isbad(master, offset)) { - if (!offset) { - nogood: - printk(KERN_NOTICE "Failed to find a non-bad block to check for RedBoot partition table\n"); -+ vfree(buf); - return -EIO; - } - offset -= master->erasesize; - } - } else { - offset = directory * master->erasesize; -- while (master->block_isbad && -+ while (master->block_isbad && - master->block_isbad(master, offset)) { - offset += master->erasesize; - if (offset == master->size) - goto nogood; - } - } -- buf = vmalloc(master->erasesize); -- -- if (!buf) -- return -ENOMEM; -- - printk(KERN_NOTICE "Searching for RedBoot partition table in %s at offset 0x%lx\n", - master->name, offset); - -@@ -171,13 +189,21 @@ - } - if (i == numslots) { - /* Didn't find it */ -+ if (offset + master->erasesize < master->size) { -+ /* not at the end of the flash yet, maybe next block :) */ -+ directory++; -+ goto restart; -+ } - printk(KERN_NOTICE "No RedBoot partition table detected in %s\n", - master->name); - ret = 0; - goto out; - } - -- for (i = 0; i < numslots; i++) { -+ first_slot = (buf[i].flash_base & (master->erasesize - 1)) / -+ sizeof(struct fis_image_desc); -+ -+ for (i = first_slot; i < first_slot + numslots; i++) { - struct fis_list *new_fl, **prev; - - if (buf[i].name[0] == 0xff) { -diff -Nur linux-2.6.39-rc7.orig/drivers/net/Kconfig linux-2.6.39-rc7/drivers/net/Kconfig ---- linux-2.6.39-rc7.orig/drivers/net/Kconfig 2011-05-10 04:33:54.000000000 +0200 -+++ linux-2.6.39-rc7/drivers/net/Kconfig 2011-05-15 21:34:57.000000000 +0200 -@@ -251,6 +251,12 @@ - help - Select this if your platform comes with an external 93CX6 eeprom. - -+config AR231X_ETHERNET -+ tristate "AR231x Ethernet support" -+ depends on ATHEROS_AR231X -+ help -+ Support for the AR231x/531x ethernet controller -+ - config MACE - tristate "MACE (Power Mac ethernet) support" - depends on PPC_PMAC && PPC32 -diff -Nur linux-2.6.39-rc7.orig/drivers/net/Makefile linux-2.6.39-rc7/drivers/net/Makefile ---- linux-2.6.39-rc7.orig/drivers/net/Makefile 2011-05-10 04:33:54.000000000 +0200 -+++ linux-2.6.39-rc7/drivers/net/Makefile 2011-05-15 21:34:57.000000000 +0200 -@@ -226,6 +226,7 @@ - obj-$(CONFIG_KORINA) += korina.o - obj-$(CONFIG_MIPS_JAZZ_SONIC) += jazzsonic.o - obj-$(CONFIG_MIPS_AU1X00_ENET) += au1000_eth.o -+obj-$(CONFIG_AR231X_ETHERNET) += ar231x.o - obj-$(CONFIG_MIPS_SIM_NET) += mipsnet.o - obj-$(CONFIG_SGI_IOC3_ETH) += ioc3-eth.o - obj-$(CONFIG_DECLANCE) += declance.o -diff -Nur linux-2.6.39-rc7.orig/drivers/net/ar231x.c linux-2.6.39-rc7/drivers/net/ar231x.c ---- linux-2.6.39-rc7.orig/drivers/net/ar231x.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/drivers/net/ar231x.c 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,1293 @@ -+/* -+ * ar231x.c: Linux driver for the Atheros AR231x Ethernet device. -+ * -+ * Copyright (C) 2004 by Sameer Dekate -+ * Copyright (C) 2006 Imre Kaloz -+ * Copyright (C) 2006-2009 Felix Fietkau -+ * -+ * Thanks to Atheros for providing hardware and documentation -+ * enabling me to write this driver. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * Additional credits: -+ * This code is taken from John Taylor's Sibyte driver and then -+ * modified for the AR2313. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define AR2313_MTU 1692 -+#define AR2313_PRIOS 1 -+#define AR2313_QUEUES (2*AR2313_PRIOS) -+#define AR2313_DESCR_ENTRIES 64 -+ -+ -+#ifndef min -+#define min(a,b) (((a)<(b))?(a):(b)) -+#endif -+ -+#ifndef SMP_CACHE_BYTES -+#define SMP_CACHE_BYTES L1_CACHE_BYTES -+#endif -+ -+#define AR2313_MBOX_SET_BIT 0x8 -+ -+#include "ar231x.h" -+ -+/* -+ * New interrupt handler strategy: -+ * -+ * An old interrupt handler worked using the traditional method of -+ * replacing an skbuff with a new one when a packet arrives. However -+ * the rx rings do not need to contain a static number of buffer -+ * descriptors, thus it makes sense to move the memory allocation out -+ * of the main interrupt handler and do it in a bottom half handler -+ * and only allocate new buffers when the number of buffers in the -+ * ring is below a certain threshold. In order to avoid starving the -+ * NIC under heavy load it is however necessary to force allocation -+ * when hitting a minimum threshold. The strategy for alloction is as -+ * follows: -+ * -+ * RX_LOW_BUF_THRES - allocate buffers in the bottom half -+ * RX_PANIC_LOW_THRES - we are very low on buffers, allocate -+ * the buffers in the interrupt handler -+ * RX_RING_THRES - maximum number of buffers in the rx ring -+ * -+ * One advantagous side effect of this allocation approach is that the -+ * entire rx processing can be done without holding any spin lock -+ * since the rx rings and registers are totally independent of the tx -+ * ring and its registers. This of course includes the kmalloc's of -+ * new skb's. Thus start_xmit can run in parallel with rx processing -+ * and the memory allocation on SMP systems. -+ * -+ * Note that running the skb reallocation in a bottom half opens up -+ * another can of races which needs to be handled properly. In -+ * particular it can happen that the interrupt handler tries to run -+ * the reallocation while the bottom half is either running on another -+ * CPU or was interrupted on the same CPU. To get around this the -+ * driver uses bitops to prevent the reallocation routines from being -+ * reentered. -+ * -+ * TX handling can also be done without holding any spin lock, wheee -+ * this is fun! since tx_csm is only written to by the interrupt -+ * handler. -+ */ -+ -+/* -+ * Threshold values for RX buffer allocation - the low water marks for -+ * when to start refilling the rings are set to 75% of the ring -+ * sizes. It seems to make sense to refill the rings entirely from the -+ * intrrupt handler once it gets below the panic threshold, that way -+ * we don't risk that the refilling is moved to another CPU when the -+ * one running the interrupt handler just got the slab code hot in its -+ * cache. -+ */ -+#define RX_RING_SIZE AR2313_DESCR_ENTRIES -+#define RX_PANIC_THRES (RX_RING_SIZE/4) -+#define RX_LOW_THRES ((3*RX_RING_SIZE)/4) -+#define CRC_LEN 4 -+#define RX_OFFSET 2 -+ -+#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) -+#define VLAN_HDR 4 -+#else -+#define VLAN_HDR 0 -+#endif -+ -+#define AR2313_BUFSIZE (AR2313_MTU + VLAN_HDR + ETH_HLEN + CRC_LEN + RX_OFFSET) -+ -+#ifdef MODULE -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Sameer Dekate , Imre Kaloz , Felix Fietkau "); -+MODULE_DESCRIPTION("AR231x Ethernet driver"); -+#endif -+ -+#define virt_to_phys(x) ((u32)(x) & 0x1fffffff) -+ -+// prototypes -+static void ar231x_halt(struct net_device *dev); -+static void rx_tasklet_func(unsigned long data); -+static void rx_tasklet_cleanup(struct net_device *dev); -+static void ar231x_multicast_list(struct net_device *dev); -+static void ar231x_tx_timeout(struct net_device *dev); -+ -+static int ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum); -+static int ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, u16 value); -+static int ar231x_mdiobus_reset(struct mii_bus *bus); -+static int ar231x_mdiobus_probe (struct net_device *dev); -+static void ar231x_adjust_link(struct net_device *dev); -+ -+#ifndef ERR -+#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args) -+#endif -+ -+#ifdef CONFIG_NET_POLL_CONTROLLER -+static void -+ar231x_netpoll(struct net_device *dev) -+{ -+ unsigned long flags; -+ -+ local_irq_save(flags); -+ ar231x_interrupt(dev->irq, dev); -+ local_irq_restore(flags); -+} -+#endif -+ -+static const struct net_device_ops ar231x_ops = { -+ .ndo_open = ar231x_open, -+ .ndo_stop = ar231x_close, -+ .ndo_start_xmit = ar231x_start_xmit, -+ .ndo_set_multicast_list = ar231x_multicast_list, -+ .ndo_do_ioctl = ar231x_ioctl, -+ .ndo_change_mtu = eth_change_mtu, -+ .ndo_validate_addr = eth_validate_addr, -+ .ndo_set_mac_address = eth_mac_addr, -+ .ndo_tx_timeout = ar231x_tx_timeout, -+#ifdef CONFIG_NET_POLL_CONTROLLER -+ .ndo_poll_controller = ar231x_netpoll, -+#endif -+}; -+ -+int __init ar231x_probe(struct platform_device *pdev) -+{ -+ struct net_device *dev; -+ struct ar231x_private *sp; -+ struct resource *res; -+ unsigned long ar_eth_base; -+ char buf[64]; -+ -+ dev = alloc_etherdev(sizeof(struct ar231x_private)); -+ -+ if (dev == NULL) { -+ printk(KERN_ERR -+ "ar231x: Unable to allocate net_device structure!\n"); -+ return -ENOMEM; -+ } -+ -+ platform_set_drvdata(pdev, dev); -+ -+ sp = netdev_priv(dev); -+ sp->dev = dev; -+ sp->cfg = pdev->dev.platform_data; -+ -+ sprintf(buf, "eth%d_membase", pdev->id); -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, buf); -+ if (!res) -+ return -ENODEV; -+ -+ sp->link = 0; -+ ar_eth_base = res->start; -+ -+ sprintf(buf, "eth%d_irq", pdev->id); -+ dev->irq = platform_get_irq_byname(pdev, buf); -+ -+ spin_lock_init(&sp->lock); -+ -+ dev->features |= NETIF_F_HIGHDMA; -+ dev->netdev_ops = &ar231x_ops; -+ -+ tasklet_init(&sp->rx_tasklet, rx_tasklet_func, (unsigned long) dev); -+ tasklet_disable(&sp->rx_tasklet); -+ -+ sp->eth_regs = -+ ioremap_nocache(virt_to_phys(ar_eth_base), sizeof(*sp->eth_regs)); -+ if (!sp->eth_regs) { -+ printk("Can't remap eth registers\n"); -+ return (-ENXIO); -+ } -+ -+ /* -+ * When there's only one MAC, PHY regs are typically on ENET0, -+ * even though the MAC might be on ENET1. -+ * Needto remap PHY regs separately in this case -+ */ -+ if (virt_to_phys(ar_eth_base) == virt_to_phys(sp->phy_regs)) -+ sp->phy_regs = sp->eth_regs; -+ else { -+ sp->phy_regs = -+ ioremap_nocache(virt_to_phys(sp->cfg->phy_base), -+ sizeof(*sp->phy_regs)); -+ if (!sp->phy_regs) { -+ printk("Can't remap phy registers\n"); -+ return (-ENXIO); -+ } -+ } -+ -+ sp->dma_regs = -+ ioremap_nocache(virt_to_phys(ar_eth_base + 0x1000), -+ sizeof(*sp->dma_regs)); -+ dev->base_addr = (unsigned int) sp->dma_regs; -+ if (!sp->dma_regs) { -+ printk("Can't remap DMA registers\n"); -+ return (-ENXIO); -+ } -+ -+ sp->int_regs = ioremap_nocache(virt_to_phys(sp->cfg->reset_base), 4); -+ if (!sp->int_regs) { -+ printk("Can't remap INTERRUPT registers\n"); -+ return (-ENXIO); -+ } -+ -+ strncpy(sp->name, "Atheros AR231x", sizeof(sp->name) - 1); -+ sp->name[sizeof(sp->name) - 1] = '\0'; -+ memcpy(dev->dev_addr, sp->cfg->macaddr, 6); -+ -+ if (ar231x_init(dev)) { -+ /* -+ * ar231x_init() calls ar231x_init_cleanup() on error. -+ */ -+ kfree(dev); -+ return -ENODEV; -+ } -+ -+ if (register_netdev(dev)) { -+ printk("%s: register_netdev failed\n", __func__); -+ return -1; -+ } -+ -+ printk("%s: %s: %02x:%02x:%02x:%02x:%02x:%02x, irq %d\n", -+ dev->name, sp->name, -+ dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], -+ dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5], dev->irq); -+ -+ sp->mii_bus = mdiobus_alloc(); -+ if (sp->mii_bus == NULL) -+ return -1; -+ -+ sp->mii_bus->priv = dev; -+ sp->mii_bus->read = ar231x_mdiobus_read; -+ sp->mii_bus->write = ar231x_mdiobus_write; -+ sp->mii_bus->reset = ar231x_mdiobus_reset; -+ sp->mii_bus->name = "ar231x_eth_mii"; -+ snprintf(sp->mii_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id); -+ sp->mii_bus->irq = kmalloc(sizeof(int), GFP_KERNEL); -+ *sp->mii_bus->irq = PHY_POLL; -+ -+ mdiobus_register(sp->mii_bus); -+ -+ if (ar231x_mdiobus_probe(dev) != 0) { -+ printk(KERN_ERR "%s: mdiobus_probe failed\n", dev->name); -+ rx_tasklet_cleanup(dev); -+ ar231x_init_cleanup(dev); -+ unregister_netdev(dev); -+ kfree(dev); -+ return -ENODEV; -+ } -+ -+ /* start link poll timer */ -+ ar231x_setup_timer(dev); -+ -+ return 0; -+} -+ -+ -+static void ar231x_multicast_list(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ unsigned int filter; -+ -+ filter = sp->eth_regs->mac_control; -+ -+ if (dev->flags & IFF_PROMISC) -+ filter |= MAC_CONTROL_PR; -+ else -+ filter &= ~MAC_CONTROL_PR; -+ if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 0)) -+ filter |= MAC_CONTROL_PM; -+ else -+ filter &= ~MAC_CONTROL_PM; -+ -+ sp->eth_regs->mac_control = filter; -+} -+ -+static void rx_tasklet_cleanup(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ -+ /* -+ * Tasklet may be scheduled. Need to get it removed from the list -+ * since we're about to free the struct. -+ */ -+ -+ sp->unloading = 1; -+ tasklet_enable(&sp->rx_tasklet); -+ tasklet_kill(&sp->rx_tasklet); -+} -+ -+static int __devexit ar231x_remove(struct platform_device *pdev) -+{ -+ struct net_device *dev = platform_get_drvdata(pdev); -+ struct ar231x_private *sp = netdev_priv(dev); -+ rx_tasklet_cleanup(dev); -+ ar231x_init_cleanup(dev); -+ unregister_netdev(dev); -+ mdiobus_unregister(sp->mii_bus); -+ mdiobus_free(sp->mii_bus); -+ kfree(dev); -+ return 0; -+} -+ -+ -+/* -+ * Restart the AR2313 ethernet controller. -+ */ -+static int ar231x_restart(struct net_device *dev) -+{ -+ /* disable interrupts */ -+ disable_irq(dev->irq); -+ -+ /* stop mac */ -+ ar231x_halt(dev); -+ -+ /* initialize */ -+ ar231x_init(dev); -+ -+ /* enable interrupts */ -+ enable_irq(dev->irq); -+ -+ return 0; -+} -+ -+static struct platform_driver ar231x_driver = { -+ .driver.name = "ar231x-eth", -+ .probe = ar231x_probe, -+ .remove = __devexit_p(ar231x_remove), -+}; -+ -+int __init ar231x_module_init(void) -+{ -+ return platform_driver_register(&ar231x_driver); -+} -+ -+void __exit ar231x_module_cleanup(void) -+{ -+ platform_driver_unregister(&ar231x_driver); -+} -+ -+module_init(ar231x_module_init); -+module_exit(ar231x_module_cleanup); -+ -+ -+static void ar231x_free_descriptors(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ if (sp->rx_ring != NULL) { -+ kfree((void *) KSEG0ADDR(sp->rx_ring)); -+ sp->rx_ring = NULL; -+ sp->tx_ring = NULL; -+ } -+} -+ -+ -+static int ar231x_allocate_descriptors(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ int size; -+ int j; -+ ar231x_descr_t *space; -+ -+ if (sp->rx_ring != NULL) { -+ printk("%s: already done.\n", __FUNCTION__); -+ return 0; -+ } -+ -+ size = -+ (sizeof(ar231x_descr_t) * (AR2313_DESCR_ENTRIES * AR2313_QUEUES)); -+ space = kmalloc(size, GFP_KERNEL); -+ if (space == NULL) -+ return 1; -+ -+ /* invalidate caches */ -+ dma_cache_inv((unsigned int) space, size); -+ -+ /* now convert pointer to KSEG1 */ -+ space = (ar231x_descr_t *) KSEG1ADDR(space); -+ -+ memset((void *) space, 0, size); -+ -+ sp->rx_ring = space; -+ space += AR2313_DESCR_ENTRIES; -+ -+ sp->tx_ring = space; -+ space += AR2313_DESCR_ENTRIES; -+ -+ /* Initialize the transmit Descriptors */ -+ for (j = 0; j < AR2313_DESCR_ENTRIES; j++) { -+ ar231x_descr_t *td = &sp->tx_ring[j]; -+ td->status = 0; -+ td->devcs = DMA_TX1_CHAINED; -+ td->addr = 0; -+ td->descr = -+ virt_to_phys(&sp-> -+ tx_ring[(j + 1) & (AR2313_DESCR_ENTRIES - 1)]); -+ } -+ -+ return 0; -+} -+ -+ -+/* -+ * Generic cleanup handling data allocated during init. Used when the -+ * module is unloaded or if an error occurs during initialization -+ */ -+static void ar231x_init_cleanup(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ struct sk_buff *skb; -+ int j; -+ -+ ar231x_free_descriptors(dev); -+ -+ if (sp->eth_regs) -+ iounmap((void *) sp->eth_regs); -+ if (sp->dma_regs) -+ iounmap((void *) sp->dma_regs); -+ -+ if (sp->rx_skb) { -+ for (j = 0; j < AR2313_DESCR_ENTRIES; j++) { -+ skb = sp->rx_skb[j]; -+ if (skb) { -+ sp->rx_skb[j] = NULL; -+ dev_kfree_skb(skb); -+ } -+ } -+ kfree(sp->rx_skb); -+ sp->rx_skb = NULL; -+ } -+ -+ if (sp->tx_skb) { -+ for (j = 0; j < AR2313_DESCR_ENTRIES; j++) { -+ skb = sp->tx_skb[j]; -+ if (skb) { -+ sp->tx_skb[j] = NULL; -+ dev_kfree_skb(skb); -+ } -+ } -+ kfree(sp->tx_skb); -+ sp->tx_skb = NULL; -+ } -+} -+ -+static int ar231x_setup_timer(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ -+ init_timer(&sp->link_timer); -+ -+ sp->link_timer.function = ar231x_link_timer_fn; -+ sp->link_timer.data = (int) dev; -+ sp->link_timer.expires = jiffies + HZ; -+ -+ add_timer(&sp->link_timer); -+ return 0; -+ -+} -+ -+static void ar231x_link_timer_fn(unsigned long data) -+{ -+ struct net_device *dev = (struct net_device *) data; -+ struct ar231x_private *sp = netdev_priv(dev); -+ -+ // see if the link status changed -+ // This was needed to make sure we set the PHY to the -+ // autonegotiated value of half or full duplex. -+ ar231x_check_link(dev); -+ -+ // Loop faster when we don't have link. -+ // This was needed to speed up the AP bootstrap time. -+ if (sp->link == 0) { -+ mod_timer(&sp->link_timer, jiffies + HZ / 2); -+ } else { -+ mod_timer(&sp->link_timer, jiffies + LINK_TIMER); -+ } -+} -+ -+static void ar231x_check_link(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ u16 phyData; -+ -+ phyData = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_BMSR); -+ if (sp->phyData != phyData) { -+ if (phyData & BMSR_LSTATUS) { -+ /* link is present, ready link partner ability to deterine -+ duplexity */ -+ int duplex = 0; -+ u16 reg; -+ -+ sp->link = 1; -+ reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_BMCR); -+ if (reg & BMCR_ANENABLE) { -+ /* auto neg enabled */ -+ reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_LPA); -+ duplex = (reg & (LPA_100FULL | LPA_10FULL)) ? 1 : 0; -+ } else { -+ /* no auto neg, just read duplex config */ -+ duplex = (reg & BMCR_FULLDPLX) ? 1 : 0; -+ } -+ -+ printk(KERN_INFO "%s: Configuring MAC for %s duplex\n", -+ dev->name, (duplex) ? "full" : "half"); -+ -+ if (duplex) { -+ /* full duplex */ -+ sp->eth_regs->mac_control = -+ ((sp->eth_regs-> -+ mac_control | MAC_CONTROL_F) & ~MAC_CONTROL_DRO); -+ } else { -+ /* half duplex */ -+ sp->eth_regs->mac_control = -+ ((sp->eth_regs-> -+ mac_control | MAC_CONTROL_DRO) & ~MAC_CONTROL_F); -+ } -+ } else { -+ /* no link */ -+ sp->link = 0; -+ } -+ sp->phyData = phyData; -+ } -+} -+ -+static int ar231x_reset_reg(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ unsigned int ethsal, ethsah; -+ unsigned int flags; -+ -+ *sp->int_regs |= sp->cfg->reset_mac; -+ mdelay(10); -+ *sp->int_regs &= ~sp->cfg->reset_mac; -+ mdelay(10); -+ *sp->int_regs |= sp->cfg->reset_phy; -+ mdelay(10); -+ *sp->int_regs &= ~sp->cfg->reset_phy; -+ mdelay(10); -+ -+ sp->dma_regs->bus_mode = (DMA_BUS_MODE_SWR); -+ mdelay(10); -+ sp->dma_regs->bus_mode = -+ ((32 << DMA_BUS_MODE_PBL_SHIFT) | DMA_BUS_MODE_BLE); -+ -+ /* enable interrupts */ -+ sp->dma_regs->intr_ena = (DMA_STATUS_AIS | -+ DMA_STATUS_NIS | -+ DMA_STATUS_RI | -+ DMA_STATUS_TI | DMA_STATUS_FBE); -+ sp->dma_regs->xmt_base = virt_to_phys(sp->tx_ring); -+ sp->dma_regs->rcv_base = virt_to_phys(sp->rx_ring); -+ sp->dma_regs->control = -+ (DMA_CONTROL_SR | DMA_CONTROL_ST | DMA_CONTROL_SF); -+ -+ sp->eth_regs->flow_control = (FLOW_CONTROL_FCE); -+ sp->eth_regs->vlan_tag = (0x8100); -+ -+ /* Enable Ethernet Interface */ -+ flags = (MAC_CONTROL_TE | /* transmit enable */ -+ MAC_CONTROL_PM | /* pass mcast */ -+ MAC_CONTROL_F | /* full duplex */ -+ MAC_CONTROL_HBD); /* heart beat disabled */ -+ -+ if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */ -+ flags |= MAC_CONTROL_PR; -+ } -+ sp->eth_regs->mac_control = flags; -+ -+ /* Set all Ethernet station address registers to their initial values */ -+ ethsah = ((((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) | -+ (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF)); -+ -+ ethsal = ((((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) | -+ (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) | -+ (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) | -+ (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF)); -+ -+ sp->eth_regs->mac_addr[0] = ethsah; -+ sp->eth_regs->mac_addr[1] = ethsal; -+ -+ mdelay(10); -+ -+ return (0); -+} -+ -+ -+static int ar231x_init(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ int ecode = 0; -+ -+ /* -+ * Allocate descriptors -+ */ -+ if (ar231x_allocate_descriptors(dev)) { -+ printk("%s: %s: ar231x_allocate_descriptors failed\n", -+ dev->name, __FUNCTION__); -+ ecode = -EAGAIN; -+ goto init_error; -+ } -+ -+ /* -+ * Get the memory for the skb rings. -+ */ -+ if (sp->rx_skb == NULL) { -+ sp->rx_skb = -+ kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES, -+ GFP_KERNEL); -+ if (!(sp->rx_skb)) { -+ printk("%s: %s: rx_skb kmalloc failed\n", -+ dev->name, __FUNCTION__); -+ ecode = -EAGAIN; -+ goto init_error; -+ } -+ } -+ memset(sp->rx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES); -+ -+ if (sp->tx_skb == NULL) { -+ sp->tx_skb = -+ kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES, -+ GFP_KERNEL); -+ if (!(sp->tx_skb)) { -+ printk("%s: %s: tx_skb kmalloc failed\n", -+ dev->name, __FUNCTION__); -+ ecode = -EAGAIN; -+ goto init_error; -+ } -+ } -+ memset(sp->tx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES); -+ -+ /* -+ * Set tx_csm before we start receiving interrupts, otherwise -+ * the interrupt handler might think it is supposed to process -+ * tx ints before we are up and running, which may cause a null -+ * pointer access in the int handler. -+ */ -+ sp->rx_skbprd = 0; -+ sp->cur_rx = 0; -+ sp->tx_prd = 0; -+ sp->tx_csm = 0; -+ -+ /* -+ * Zero the stats before starting the interface -+ */ -+ memset(&dev->stats, 0, sizeof(dev->stats)); -+ -+ /* -+ * We load the ring here as there seem to be no way to tell the -+ * firmware to wipe the ring without re-initializing it. -+ */ -+ ar231x_load_rx_ring(dev, RX_RING_SIZE); -+ -+ /* -+ * Init hardware -+ */ -+ ar231x_reset_reg(dev); -+ -+ /* -+ * Get the IRQ -+ */ -+ ecode = -+ request_irq(dev->irq, &ar231x_interrupt, -+ IRQF_DISABLED | IRQF_SAMPLE_RANDOM, -+ dev->name, dev); -+ if (ecode) { -+ printk(KERN_WARNING "%s: %s: Requested IRQ %d is busy\n", -+ dev->name, __FUNCTION__, dev->irq); -+ goto init_error; -+ } -+ -+ -+ tasklet_enable(&sp->rx_tasklet); -+ -+ return 0; -+ -+ init_error: -+ ar231x_init_cleanup(dev); -+ return ecode; -+} -+ -+/* -+ * Load the rx ring. -+ * -+ * Loading rings is safe without holding the spin lock since this is -+ * done only before the device is enabled, thus no interrupts are -+ * generated and by the interrupt handler/tasklet handler. -+ */ -+static void ar231x_load_rx_ring(struct net_device *dev, int nr_bufs) -+{ -+ -+ struct ar231x_private *sp = netdev_priv(dev); -+ short i, idx; -+ -+ idx = sp->rx_skbprd; -+ -+ for (i = 0; i < nr_bufs; i++) { -+ struct sk_buff *skb; -+ ar231x_descr_t *rd; -+ -+ if (sp->rx_skb[idx]) -+ break; -+ -+ skb = netdev_alloc_skb(dev, AR2313_BUFSIZE); -+ if (!skb) { -+ printk("\n\n\n\n %s: No memory in system\n\n\n\n", -+ __FUNCTION__); -+ break; -+ } -+ -+ /* -+ * Make sure IP header starts on a fresh cache line. -+ */ -+ skb->dev = dev; -+ skb_reserve(skb, RX_OFFSET); -+ sp->rx_skb[idx] = skb; -+ -+ rd = (ar231x_descr_t *) & sp->rx_ring[idx]; -+ -+ /* initialize dma descriptor */ -+ rd->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) | -+ DMA_RX1_CHAINED); -+ rd->addr = virt_to_phys(skb->data); -+ rd->descr = -+ virt_to_phys(&sp-> -+ rx_ring[(idx + 1) & (AR2313_DESCR_ENTRIES - 1)]); -+ rd->status = DMA_RX_OWN; -+ -+ idx = DSC_NEXT(idx); -+ } -+ -+ if (i) -+ sp->rx_skbprd = idx; -+ -+ return; -+} -+ -+#define AR2313_MAX_PKTS_PER_CALL 64 -+ -+static int ar231x_rx_int(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ struct sk_buff *skb, *skb_new; -+ ar231x_descr_t *rxdesc; -+ unsigned int status; -+ u32 idx; -+ int pkts = 0; -+ int rval; -+ -+ idx = sp->cur_rx; -+ -+ /* process at most the entire ring and then wait for another interrupt -+ */ -+ while (1) { -+ -+ rxdesc = &sp->rx_ring[idx]; -+ status = rxdesc->status; -+ if (status & DMA_RX_OWN) { -+ /* SiByte owns descriptor or descr not yet filled in */ -+ rval = 0; -+ break; -+ } -+ -+ if (++pkts > AR2313_MAX_PKTS_PER_CALL) { -+ rval = 1; -+ break; -+ } -+ -+ if ((status & DMA_RX_ERROR) && !(status & DMA_RX_LONG)) { -+ dev->stats.rx_errors++; -+ dev->stats.rx_dropped++; -+ -+ /* add statistics counters */ -+ if (status & DMA_RX_ERR_CRC) -+ dev->stats.rx_crc_errors++; -+ if (status & DMA_RX_ERR_COL) -+ dev->stats.rx_over_errors++; -+ if (status & DMA_RX_ERR_LENGTH) -+ dev->stats.rx_length_errors++; -+ if (status & DMA_RX_ERR_RUNT) -+ dev->stats.rx_over_errors++; -+ if (status & DMA_RX_ERR_DESC) -+ dev->stats.rx_over_errors++; -+ -+ } else { -+ /* alloc new buffer. */ -+ skb_new = netdev_alloc_skb(dev, AR2313_BUFSIZE + RX_OFFSET); -+ if (skb_new != NULL) { -+ -+ skb = sp->rx_skb[idx]; -+ /* set skb */ -+ skb_put(skb, -+ ((status >> DMA_RX_LEN_SHIFT) & 0x3fff) - CRC_LEN); -+ -+ dev->stats.rx_bytes += skb->len; -+ skb->protocol = eth_type_trans(skb, dev); -+ /* pass the packet to upper layers */ -+ netif_rx(skb); -+ -+ skb_new->dev = dev; -+ /* 16 bit align */ -+ skb_reserve(skb_new, RX_OFFSET); -+ /* reset descriptor's curr_addr */ -+ rxdesc->addr = virt_to_phys(skb_new->data); -+ -+ dev->stats.rx_packets++; -+ sp->rx_skb[idx] = skb_new; -+ } else { -+ dev->stats.rx_dropped++; -+ } -+ } -+ -+ rxdesc->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) | -+ DMA_RX1_CHAINED); -+ rxdesc->status = DMA_RX_OWN; -+ -+ idx = DSC_NEXT(idx); -+ } -+ -+ sp->cur_rx = idx; -+ -+ return rval; -+} -+ -+ -+static void ar231x_tx_int(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ u32 idx; -+ struct sk_buff *skb; -+ ar231x_descr_t *txdesc; -+ unsigned int status = 0; -+ -+ idx = sp->tx_csm; -+ -+ while (idx != sp->tx_prd) { -+ txdesc = &sp->tx_ring[idx]; -+ -+ if ((status = txdesc->status) & DMA_TX_OWN) { -+ /* ar231x dma still owns descr */ -+ break; -+ } -+ /* done with this descriptor */ -+ dma_unmap_single(NULL, txdesc->addr, -+ txdesc->devcs & DMA_TX1_BSIZE_MASK, -+ DMA_TO_DEVICE); -+ txdesc->status = 0; -+ -+ if (status & DMA_TX_ERROR) { -+ dev->stats.tx_errors++; -+ dev->stats.tx_dropped++; -+ if (status & DMA_TX_ERR_UNDER) -+ dev->stats.tx_fifo_errors++; -+ if (status & DMA_TX_ERR_HB) -+ dev->stats.tx_heartbeat_errors++; -+ if (status & (DMA_TX_ERR_LOSS | DMA_TX_ERR_LINK)) -+ dev->stats.tx_carrier_errors++; -+ if (status & (DMA_TX_ERR_LATE | -+ DMA_TX_ERR_COL | -+ DMA_TX_ERR_JABBER | DMA_TX_ERR_DEFER)) -+ dev->stats.tx_aborted_errors++; -+ } else { -+ /* transmit OK */ -+ dev->stats.tx_packets++; -+ } -+ -+ skb = sp->tx_skb[idx]; -+ sp->tx_skb[idx] = NULL; -+ idx = DSC_NEXT(idx); -+ dev->stats.tx_bytes += skb->len; -+ dev_kfree_skb_irq(skb); -+ } -+ -+ sp->tx_csm = idx; -+ -+ return; -+} -+ -+ -+static void rx_tasklet_func(unsigned long data) -+{ -+ struct net_device *dev = (struct net_device *) data; -+ struct ar231x_private *sp = netdev_priv(dev); -+ -+ if (sp->unloading) { -+ return; -+ } -+ -+ if (ar231x_rx_int(dev)) { -+ tasklet_hi_schedule(&sp->rx_tasklet); -+ } else { -+ unsigned long flags; -+ spin_lock_irqsave(&sp->lock, flags); -+ sp->dma_regs->intr_ena |= DMA_STATUS_RI; -+ spin_unlock_irqrestore(&sp->lock, flags); -+ } -+} -+ -+static void rx_schedule(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ -+ sp->dma_regs->intr_ena &= ~DMA_STATUS_RI; -+ -+ tasklet_hi_schedule(&sp->rx_tasklet); -+} -+ -+static irqreturn_t ar231x_interrupt(int irq, void *dev_id) -+{ -+ struct net_device *dev = (struct net_device *) dev_id; -+ struct ar231x_private *sp = netdev_priv(dev); -+ unsigned int status, enabled; -+ -+ /* clear interrupt */ -+ /* -+ * Don't clear RI bit if currently disabled. -+ */ -+ status = sp->dma_regs->status; -+ enabled = sp->dma_regs->intr_ena; -+ sp->dma_regs->status = status & enabled; -+ -+ if (status & DMA_STATUS_NIS) { -+ /* normal status */ -+ /* -+ * Don't schedule rx processing if interrupt -+ * is already disabled. -+ */ -+ if (status & enabled & DMA_STATUS_RI) { -+ /* receive interrupt */ -+ rx_schedule(dev); -+ } -+ if (status & DMA_STATUS_TI) { -+ /* transmit interrupt */ -+ ar231x_tx_int(dev); -+ } -+ } -+ -+ /* abnormal status */ -+ if (status & (DMA_STATUS_FBE | DMA_STATUS_TPS)) { -+ ar231x_restart(dev); -+ } -+ return IRQ_HANDLED; -+} -+ -+ -+static int ar231x_open(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ unsigned int ethsal, ethsah; -+ -+ /* reset the hardware, in case the MAC address changed */ -+ ethsah = ((((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) | -+ (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF)); -+ -+ ethsal = ((((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) | -+ (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) | -+ (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) | -+ (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF)); -+ -+ sp->eth_regs->mac_addr[0] = ethsah; -+ sp->eth_regs->mac_addr[1] = ethsal; -+ -+ mdelay(10); -+ -+ dev->mtu = 1500; -+ netif_start_queue(dev); -+ -+ sp->eth_regs->mac_control |= MAC_CONTROL_RE; -+ -+ return 0; -+} -+ -+static void ar231x_tx_timeout(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ unsigned long flags; -+ -+ spin_lock_irqsave(&sp->lock, flags); -+ ar231x_restart(dev); -+ spin_unlock_irqrestore(&sp->lock, flags); -+} -+ -+static void ar231x_halt(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ int j; -+ -+ tasklet_disable(&sp->rx_tasklet); -+ -+ /* kill the MAC */ -+ sp->eth_regs->mac_control &= ~(MAC_CONTROL_RE | /* disable Receives */ -+ MAC_CONTROL_TE); /* disable Transmits */ -+ /* stop dma */ -+ sp->dma_regs->control = 0; -+ sp->dma_regs->bus_mode = DMA_BUS_MODE_SWR; -+ -+ /* place phy and MAC in reset */ -+ *sp->int_regs |= (sp->cfg->reset_mac | sp->cfg->reset_phy); -+ -+ /* free buffers on tx ring */ -+ for (j = 0; j < AR2313_DESCR_ENTRIES; j++) { -+ struct sk_buff *skb; -+ ar231x_descr_t *txdesc; -+ -+ txdesc = &sp->tx_ring[j]; -+ txdesc->descr = 0; -+ -+ skb = sp->tx_skb[j]; -+ if (skb) { -+ dev_kfree_skb(skb); -+ sp->tx_skb[j] = NULL; -+ } -+ } -+} -+ -+/* -+ * close should do nothing. Here's why. It's called when -+ * 'ifconfig bond0 down' is run. If it calls free_irq then -+ * the irq is gone forever ! When bond0 is made 'up' again, -+ * the ar231x_open () does not call request_irq (). Worse, -+ * the call to ar231x_halt() generates a WDOG reset due to -+ * the write to 'sp->int_regs' and the box reboots. -+ * Commenting this out is good since it allows the -+ * system to resume when bond0 is made up again. -+ */ -+static int ar231x_close(struct net_device *dev) -+{ -+#if 0 -+ /* -+ * Disable interrupts -+ */ -+ disable_irq(dev->irq); -+ -+ /* -+ * Without (or before) releasing irq and stopping hardware, this -+ * is an absolute non-sense, by the way. It will be reset instantly -+ * by the first irq. -+ */ -+ netif_stop_queue(dev); -+ -+ /* stop the MAC and DMA engines */ -+ ar231x_halt(dev); -+ -+ /* release the interrupt */ -+ free_irq(dev->irq, dev); -+ -+#endif -+ return 0; -+} -+ -+static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ ar231x_descr_t *td; -+ u32 idx; -+ -+ idx = sp->tx_prd; -+ td = &sp->tx_ring[idx]; -+ -+ if (td->status & DMA_TX_OWN) { -+ /* free skbuf and lie to the caller that we sent it out */ -+ dev->stats.tx_dropped++; -+ dev_kfree_skb(skb); -+ -+ /* restart transmitter in case locked */ -+ sp->dma_regs->xmt_poll = 0; -+ return 0; -+ } -+ -+ /* Setup the transmit descriptor. */ -+ td->devcs = ((skb->len << DMA_TX1_BSIZE_SHIFT) | -+ (DMA_TX1_LS | DMA_TX1_IC | DMA_TX1_CHAINED)); -+ td->addr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE); -+ td->status = DMA_TX_OWN; -+ -+ /* kick transmitter last */ -+ sp->dma_regs->xmt_poll = 0; -+ -+ sp->tx_skb[idx] = skb; -+ idx = DSC_NEXT(idx); -+ sp->tx_prd = idx; -+ -+ return 0; -+} -+ -+static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) -+{ -+ struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_data; -+ struct ar231x_private *sp = netdev_priv(dev); -+ int ret; -+ -+ switch (cmd) { -+ -+ case SIOCETHTOOL: -+ spin_lock_irq(&sp->lock); -+ ret = phy_ethtool_ioctl(sp->phy_dev, (void *) ifr->ifr_data); -+ spin_unlock_irq(&sp->lock); -+ return ret; -+ -+ case SIOCSIFHWADDR: -+ if (copy_from_user -+ (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr))) -+ return -EFAULT; -+ return 0; -+ -+ case SIOCGIFHWADDR: -+ if (copy_to_user -+ (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr))) -+ return -EFAULT; -+ return 0; -+ -+ case SIOCGMIIPHY: -+ case SIOCGMIIREG: -+ case SIOCSMIIREG: -+ return phy_mii_ioctl(sp->phy_dev, data, cmd); -+ -+ default: -+ break; -+ } -+ -+ return -EOPNOTSUPP; -+} -+ -+static void ar231x_adjust_link(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ unsigned int mc; -+ -+ if (!sp->phy_dev->link) -+ return; -+ -+ if (sp->phy_dev->duplex != sp->oldduplex) { -+ mc = readl(&sp->eth_regs->mac_control); -+ mc &= ~(MAC_CONTROL_F | MAC_CONTROL_DRO); -+ if (sp->phy_dev->duplex) -+ mc |= MAC_CONTROL_F; -+ else -+ mc |= MAC_CONTROL_DRO; -+ writel(mc, &sp->eth_regs->mac_control); -+ sp->oldduplex = sp->phy_dev->duplex; -+ } -+} -+ -+#define MII_ADDR(phy, reg) \ -+ ((reg << MII_ADDR_REG_SHIFT) | (phy << MII_ADDR_PHY_SHIFT)) -+ -+static int -+ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum) -+{ -+ struct net_device *const dev = bus->priv; -+ struct ar231x_private *sp = netdev_priv(dev); -+ volatile ETHERNET_STRUCT *ethernet = sp->phy_regs; -+ -+ ethernet->mii_addr = MII_ADDR(phy_addr, regnum); -+ while (ethernet->mii_addr & MII_ADDR_BUSY); -+ return (ethernet->mii_data >> MII_DATA_SHIFT); -+} -+ -+static int -+ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, -+ u16 value) -+{ -+ struct net_device *const dev = bus->priv; -+ struct ar231x_private *sp = netdev_priv(dev); -+ volatile ETHERNET_STRUCT *ethernet = sp->phy_regs; -+ -+ while (ethernet->mii_addr & MII_ADDR_BUSY); -+ ethernet->mii_data = value << MII_DATA_SHIFT; -+ ethernet->mii_addr = MII_ADDR(phy_addr, regnum) | MII_ADDR_WRITE; -+ -+ return 0; -+} -+ -+static int ar231x_mdiobus_reset(struct mii_bus *bus) -+{ -+ struct net_device *const dev = bus->priv; -+ -+ ar231x_reset_reg(dev); -+ -+ return 0; -+} -+ -+static int ar231x_mdiobus_probe (struct net_device *dev) -+{ -+ struct ar231x_private *const sp = netdev_priv(dev); -+ struct phy_device *phydev = NULL; -+ int phy_addr; -+ -+ /* find the first (lowest address) PHY on the current MAC's MII bus */ -+ for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) -+ if (sp->mii_bus->phy_map[phy_addr]) { -+ phydev = sp->mii_bus->phy_map[phy_addr]; -+ sp->phy = phy_addr; -+ break; /* break out with first one found */ -+ } -+ -+ if (!phydev) { -+ printk (KERN_ERR "ar231x: %s: no PHY found\n", dev->name); -+ return -1; -+ } -+ -+ /* now we are supposed to have a proper phydev, to attach to... */ -+ BUG_ON(!phydev); -+ BUG_ON(phydev->attached_dev); -+ -+ phydev = phy_connect(dev, dev_name(&phydev->dev), &ar231x_adjust_link, 0, -+ PHY_INTERFACE_MODE_MII); -+ -+ if (IS_ERR(phydev)) { -+ printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name); -+ return PTR_ERR(phydev); -+ } -+ -+ /* mask with MAC supported features */ -+ phydev->supported &= (SUPPORTED_10baseT_Half -+ | SUPPORTED_10baseT_Full -+ | SUPPORTED_100baseT_Half -+ | SUPPORTED_100baseT_Full -+ | SUPPORTED_Autoneg -+ /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */ -+ | SUPPORTED_MII -+ | SUPPORTED_TP); -+ -+ phydev->advertising = phydev->supported; -+ -+ sp->oldduplex = -1; -+ sp->phy_dev = phydev; -+ -+ printk(KERN_INFO "%s: attached PHY driver [%s] " -+ "(mii_bus:phy_addr=%s)\n", -+ dev->name, phydev->drv->name, dev_name(&phydev->dev)); -+ -+ return 0; -+} -+ -diff -Nur linux-2.6.39-rc7.orig/drivers/net/ar231x.h linux-2.6.39-rc7/drivers/net/ar231x.h ---- linux-2.6.39-rc7.orig/drivers/net/ar231x.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/drivers/net/ar231x.h 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,302 @@ -+/* -+ * ar231x.h: Linux driver for the Atheros AR231x Ethernet device. -+ * -+ * Copyright (C) 2004 by Sameer Dekate -+ * Copyright (C) 2006 Imre Kaloz -+ * Copyright (C) 2006-2009 Felix Fietkau -+ * -+ * Thanks to Atheros for providing hardware and documentation -+ * enabling me to write this driver. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ */ -+ -+#ifndef _AR2313_H_ -+#define _AR2313_H_ -+ -+#include -+#include -+#include -+#include -+ -+/* -+ * probe link timer - 5 secs -+ */ -+#define LINK_TIMER (5*HZ) -+ -+#define IS_DMA_TX_INT(X) (((X) & (DMA_STATUS_TI)) != 0) -+#define IS_DMA_RX_INT(X) (((X) & (DMA_STATUS_RI)) != 0) -+#define IS_DRIVER_OWNED(X) (((X) & (DMA_TX_OWN)) == 0) -+ -+#define AR2313_TX_TIMEOUT (HZ/4) -+ -+/* -+ * Rings -+ */ -+#define DSC_RING_ENTRIES_SIZE (AR2313_DESCR_ENTRIES * sizeof(struct desc)) -+#define DSC_NEXT(idx) ((idx + 1) & (AR2313_DESCR_ENTRIES - 1)) -+ -+#define AR2313_MBGET 2 -+#define AR2313_MBSET 3 -+#define AR2313_PCI_RECONFIG 4 -+#define AR2313_PCI_DUMP 5 -+#define AR2313_TEST_PANIC 6 -+#define AR2313_TEST_NULLPTR 7 -+#define AR2313_READ_DATA 8 -+#define AR2313_WRITE_DATA 9 -+#define AR2313_GET_VERSION 10 -+#define AR2313_TEST_HANG 11 -+#define AR2313_SYNC 12 -+ -+#define DMA_RX_ERR_CRC BIT(1) -+#define DMA_RX_ERR_DRIB BIT(2) -+#define DMA_RX_ERR_MII BIT(3) -+#define DMA_RX_EV2 BIT(5) -+#define DMA_RX_ERR_COL BIT(6) -+#define DMA_RX_LONG BIT(7) -+#define DMA_RX_LS BIT(8) /* last descriptor */ -+#define DMA_RX_FS BIT(9) /* first descriptor */ -+#define DMA_RX_MF BIT(10) /* multicast frame */ -+#define DMA_RX_ERR_RUNT BIT(11) /* runt frame */ -+#define DMA_RX_ERR_LENGTH BIT(12) /* length error */ -+#define DMA_RX_ERR_DESC BIT(14) /* descriptor error */ -+#define DMA_RX_ERROR BIT(15) /* error summary */ -+#define DMA_RX_LEN_MASK 0x3fff0000 -+#define DMA_RX_LEN_SHIFT 16 -+#define DMA_RX_FILT BIT(30) -+#define DMA_RX_OWN BIT(31) /* desc owned by DMA controller */ -+ -+#define DMA_RX1_BSIZE_MASK 0x000007ff -+#define DMA_RX1_BSIZE_SHIFT 0 -+#define DMA_RX1_CHAINED BIT(24) -+#define DMA_RX1_RER BIT(25) -+ -+#define DMA_TX_ERR_UNDER BIT(1) /* underflow error */ -+#define DMA_TX_ERR_DEFER BIT(2) /* excessive deferral */ -+#define DMA_TX_COL_MASK 0x78 -+#define DMA_TX_COL_SHIFT 3 -+#define DMA_TX_ERR_HB BIT(7) /* hearbeat failure */ -+#define DMA_TX_ERR_COL BIT(8) /* excessive collisions */ -+#define DMA_TX_ERR_LATE BIT(9) /* late collision */ -+#define DMA_TX_ERR_LINK BIT(10) /* no carrier */ -+#define DMA_TX_ERR_LOSS BIT(11) /* loss of carrier */ -+#define DMA_TX_ERR_JABBER BIT(14) /* transmit jabber timeout */ -+#define DMA_TX_ERROR BIT(15) /* frame aborted */ -+#define DMA_TX_OWN BIT(31) /* descr owned by DMA controller */ -+ -+#define DMA_TX1_BSIZE_MASK 0x000007ff -+#define DMA_TX1_BSIZE_SHIFT 0 -+#define DMA_TX1_CHAINED BIT(24) /* chained descriptors */ -+#define DMA_TX1_TER BIT(25) /* transmit end of ring */ -+#define DMA_TX1_FS BIT(29) /* first segment */ -+#define DMA_TX1_LS BIT(30) /* last segment */ -+#define DMA_TX1_IC BIT(31) /* interrupt on completion */ -+ -+#define RCVPKT_LENGTH(X) (X >> 16) /* Received pkt Length */ -+ -+#define MAC_CONTROL_RE BIT(2) /* receive enable */ -+#define MAC_CONTROL_TE BIT(3) /* transmit enable */ -+#define MAC_CONTROL_DC BIT(5) /* Deferral check */ -+#define MAC_CONTROL_ASTP BIT(8) /* Auto pad strip */ -+#define MAC_CONTROL_DRTY BIT(10) /* Disable retry */ -+#define MAC_CONTROL_DBF BIT(11) /* Disable bcast frames */ -+#define MAC_CONTROL_LCC BIT(12) /* late collision ctrl */ -+#define MAC_CONTROL_HP BIT(13) /* Hash Perfect filtering */ -+#define MAC_CONTROL_HASH BIT(14) /* Unicast hash filtering */ -+#define MAC_CONTROL_HO BIT(15) /* Hash only filtering */ -+#define MAC_CONTROL_PB BIT(16) /* Pass Bad frames */ -+#define MAC_CONTROL_IF BIT(17) /* Inverse filtering */ -+#define MAC_CONTROL_PR BIT(18) /* promiscuous mode (valid frames only) */ -+#define MAC_CONTROL_PM BIT(19) /* pass multicast */ -+#define MAC_CONTROL_F BIT(20) /* full-duplex */ -+#define MAC_CONTROL_DRO BIT(23) /* Disable Receive Own */ -+#define MAC_CONTROL_HBD BIT(28) /* heart-beat disabled (MUST BE SET) */ -+#define MAC_CONTROL_BLE BIT(30) /* big endian mode */ -+#define MAC_CONTROL_RA BIT(31) /* receive all (valid and invalid frames) */ -+ -+#define MII_ADDR_BUSY BIT(0) -+#define MII_ADDR_WRITE BIT(1) -+#define MII_ADDR_REG_SHIFT 6 -+#define MII_ADDR_PHY_SHIFT 11 -+#define MII_DATA_SHIFT 0 -+ -+#define FLOW_CONTROL_FCE BIT(1) -+ -+#define DMA_BUS_MODE_SWR BIT(0) /* software reset */ -+#define DMA_BUS_MODE_BLE BIT(7) /* big endian mode */ -+#define DMA_BUS_MODE_PBL_SHIFT 8 /* programmable burst length 32 */ -+#define DMA_BUS_MODE_DBO BIT(20) /* big-endian descriptors */ -+ -+#define DMA_STATUS_TI BIT(0) /* transmit interrupt */ -+#define DMA_STATUS_TPS BIT(1) /* transmit process stopped */ -+#define DMA_STATUS_TU BIT(2) /* transmit buffer unavailable */ -+#define DMA_STATUS_TJT BIT(3) /* transmit buffer timeout */ -+#define DMA_STATUS_UNF BIT(5) /* transmit underflow */ -+#define DMA_STATUS_RI BIT(6) /* receive interrupt */ -+#define DMA_STATUS_RU BIT(7) /* receive buffer unavailable */ -+#define DMA_STATUS_RPS BIT(8) /* receive process stopped */ -+#define DMA_STATUS_ETI BIT(10) /* early transmit interrupt */ -+#define DMA_STATUS_FBE BIT(13) /* fatal bus interrupt */ -+#define DMA_STATUS_ERI BIT(14) /* early receive interrupt */ -+#define DMA_STATUS_AIS BIT(15) /* abnormal interrupt summary */ -+#define DMA_STATUS_NIS BIT(16) /* normal interrupt summary */ -+#define DMA_STATUS_RS_SHIFT 17 /* receive process state */ -+#define DMA_STATUS_TS_SHIFT 20 /* transmit process state */ -+#define DMA_STATUS_EB_SHIFT 23 /* error bits */ -+ -+#define DMA_CONTROL_SR BIT(1) /* start receive */ -+#define DMA_CONTROL_ST BIT(13) /* start transmit */ -+#define DMA_CONTROL_SF BIT(21) /* store and forward */ -+ -+ -+typedef struct { -+ volatile unsigned int status; // OWN, Device control and status. -+ volatile unsigned int devcs; // pkt Control bits + Length -+ volatile unsigned int addr; // Current Address. -+ volatile unsigned int descr; // Next descriptor in chain. -+} ar231x_descr_t; -+ -+ -+ -+// -+// New Combo structure for Both Eth0 AND eth1 -+// -+typedef struct { -+ volatile unsigned int mac_control; /* 0x00 */ -+ volatile unsigned int mac_addr[2]; /* 0x04 - 0x08 */ -+ volatile unsigned int mcast_table[2]; /* 0x0c - 0x10 */ -+ volatile unsigned int mii_addr; /* 0x14 */ -+ volatile unsigned int mii_data; /* 0x18 */ -+ volatile unsigned int flow_control; /* 0x1c */ -+ volatile unsigned int vlan_tag; /* 0x20 */ -+ volatile unsigned int pad[7]; /* 0x24 - 0x3c */ -+ volatile unsigned int ucast_table[8]; /* 0x40-0x5c */ -+ -+} ETHERNET_STRUCT; -+ -+/******************************************************************** -+ * Interrupt controller -+ ********************************************************************/ -+ -+typedef struct { -+ volatile unsigned int wdog_control; /* 0x08 */ -+ volatile unsigned int wdog_timer; /* 0x0c */ -+ volatile unsigned int misc_status; /* 0x10 */ -+ volatile unsigned int misc_mask; /* 0x14 */ -+ volatile unsigned int global_status; /* 0x18 */ -+ volatile unsigned int reserved; /* 0x1c */ -+ volatile unsigned int reset_control; /* 0x20 */ -+} INTERRUPT; -+ -+/******************************************************************** -+ * DMA controller -+ ********************************************************************/ -+typedef struct { -+ volatile unsigned int bus_mode; /* 0x00 (CSR0) */ -+ volatile unsigned int xmt_poll; /* 0x04 (CSR1) */ -+ volatile unsigned int rcv_poll; /* 0x08 (CSR2) */ -+ volatile unsigned int rcv_base; /* 0x0c (CSR3) */ -+ volatile unsigned int xmt_base; /* 0x10 (CSR4) */ -+ volatile unsigned int status; /* 0x14 (CSR5) */ -+ volatile unsigned int control; /* 0x18 (CSR6) */ -+ volatile unsigned int intr_ena; /* 0x1c (CSR7) */ -+ volatile unsigned int rcv_missed; /* 0x20 (CSR8) */ -+ volatile unsigned int reserved[11]; /* 0x24-0x4c (CSR9-19) */ -+ volatile unsigned int cur_tx_buf_addr; /* 0x50 (CSR20) */ -+ volatile unsigned int cur_rx_buf_addr; /* 0x50 (CSR21) */ -+} DMA; -+ -+/* -+ * Struct private for the Sibyte. -+ * -+ * Elements are grouped so variables used by the tx handling goes -+ * together, and will go into the same cache lines etc. in order to -+ * avoid cache line contention between the rx and tx handling on SMP. -+ * -+ * Frequently accessed variables are put at the beginning of the -+ * struct to help the compiler generate better/shorter code. -+ */ -+struct ar231x_private { -+ struct net_device *dev; -+ int version; -+ u32 mb[2]; -+ -+ volatile ETHERNET_STRUCT *phy_regs; -+ volatile ETHERNET_STRUCT *eth_regs; -+ volatile DMA *dma_regs; -+ volatile u32 *int_regs; -+ struct ar231x_eth *cfg; -+ -+ spinlock_t lock; /* Serialise access to device */ -+ -+ /* -+ * RX and TX descriptors, must be adjacent -+ */ -+ ar231x_descr_t *rx_ring; -+ ar231x_descr_t *tx_ring; -+ -+ -+ struct sk_buff **rx_skb; -+ struct sk_buff **tx_skb; -+ -+ /* -+ * RX elements -+ */ -+ u32 rx_skbprd; -+ u32 cur_rx; -+ -+ /* -+ * TX elements -+ */ -+ u32 tx_prd; -+ u32 tx_csm; -+ -+ /* -+ * Misc elements -+ */ -+ char name[48]; -+ struct { -+ u32 address; -+ u32 length; -+ char *mapping; -+ } desc; -+ -+ -+ struct timer_list link_timer; -+ unsigned short phy; /* merlot phy = 1, samsung phy = 0x1f */ -+ unsigned short mac; -+ unsigned short link; /* 0 - link down, 1 - link up */ -+ u16 phyData; -+ -+ struct tasklet_struct rx_tasklet; -+ int unloading; -+ -+ struct phy_device *phy_dev; -+ struct mii_bus *mii_bus; -+ int oldduplex; -+}; -+ -+ -+/* -+ * Prototypes -+ */ -+static int ar231x_init(struct net_device *dev); -+#ifdef TX_TIMEOUT -+static void ar231x_tx_timeout(struct net_device *dev); -+#endif -+static int ar231x_restart(struct net_device *dev); -+static void ar231x_load_rx_ring(struct net_device *dev, int bufs); -+static irqreturn_t ar231x_interrupt(int irq, void *dev_id); -+static int ar231x_open(struct net_device *dev); -+static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev); -+static int ar231x_close(struct net_device *dev); -+static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr, -+ int cmd); -+static void ar231x_init_cleanup(struct net_device *dev); -+static int ar231x_setup_timer(struct net_device *dev); -+static void ar231x_link_timer_fn(unsigned long data); -+static void ar231x_check_link(struct net_device *dev); -+#endif /* _AR2313_H_ */ -diff -Nur linux-2.6.39-rc7.orig/drivers/watchdog/Kconfig linux-2.6.39-rc7/drivers/watchdog/Kconfig ---- linux-2.6.39-rc7.orig/drivers/watchdog/Kconfig 2011-05-10 04:33:54.000000000 +0200 -+++ linux-2.6.39-rc7/drivers/watchdog/Kconfig 2011-05-15 21:34:57.000000000 +0200 -@@ -990,6 +990,12 @@ - To compile this driver as a loadable module, choose M here. - The module will be called bcm63xx_wdt. - -+config ATHEROS_WDT -+ tristate "Atheros wisoc Watchdog Timer" -+ depends on ATHEROS_AR231X -+ help -+ Hardware driver for the Atheros wisoc Watchdog Timer. -+ - # PARISC Architecture - - # POWERPC Architecture -diff -Nur linux-2.6.39-rc7.orig/drivers/watchdog/Makefile linux-2.6.39-rc7/drivers/watchdog/Makefile ---- linux-2.6.39-rc7.orig/drivers/watchdog/Makefile 2011-05-10 04:33:54.000000000 +0200 -+++ linux-2.6.39-rc7/drivers/watchdog/Makefile 2011-05-15 21:34:57.000000000 +0200 -@@ -120,6 +120,7 @@ - obj-$(CONFIG_PNX833X_WDT) += pnx833x_wdt.o - obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o - obj-$(CONFIG_AR7_WDT) += ar7_wdt.o -+obj-$(CONFIG_ATHEROS_WDT) += ar2315-wtd.o - obj-$(CONFIG_TXX9_WDT) += txx9wdt.o - obj-$(CONFIG_OCTEON_WDT) += octeon-wdt.o - octeon-wdt-y := octeon-wdt-main.o octeon-wdt-nmi.o -diff -Nur linux-2.6.39-rc7.orig/drivers/watchdog/ar2315-wtd.c linux-2.6.39-rc7/drivers/watchdog/ar2315-wtd.c ---- linux-2.6.39-rc7.orig/drivers/watchdog/ar2315-wtd.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/drivers/watchdog/ar2315-wtd.c 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,200 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ * -+ * Copyright (C) 2008 John Crispin -+ * Based on EP93xx and ifxmips wdt driver -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define CLOCK_RATE 40000000 -+#define HEARTBEAT(x) (x < 1 || x > 90)?(20):(x) -+ -+static int wdt_timeout = 20; -+static int started = 0; -+static int in_use = 0; -+ -+static void -+ar2315_wdt_enable(void) -+{ -+ ar231x_write_reg(AR2315_WD, wdt_timeout * CLOCK_RATE); -+ ar231x_write_reg(AR2315_ISR, 0x80); -+} -+ -+static ssize_t -+ar2315_wdt_write(struct file *file, const char __user *data, size_t len, loff_t *ppos) -+{ -+ if(len) -+ ar2315_wdt_enable(); -+ return len; -+} -+ -+static int -+ar2315_wdt_open(struct inode *inode, struct file *file) -+{ -+ if(in_use) -+ return -EBUSY; -+ ar2315_wdt_enable(); -+ in_use = started = 1; -+ return nonseekable_open(inode, file); -+} -+ -+static int -+ar2315_wdt_release(struct inode *inode, struct file *file) -+{ -+ in_use = 0; -+ return 0; -+} -+ -+static irqreturn_t -+ar2315_wdt_interrupt(int irq, void *dev_id) -+{ -+ if(started) -+ { -+ printk(KERN_CRIT "watchdog expired, rebooting system\n"); -+ emergency_restart(); -+ } else { -+ ar231x_write_reg(AR2315_WDC, 0); -+ ar231x_write_reg(AR2315_WD, 0); -+ ar231x_write_reg(AR2315_ISR, 0x80); -+ } -+ return IRQ_HANDLED; -+} -+ -+static struct watchdog_info ident = { -+ .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, -+ .identity = "ar2315 Watchdog", -+}; -+ -+static int -+ar2315_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) -+{ -+ int new_wdt_timeout; -+ int ret = -ENOIOCTLCMD; -+ -+ switch(cmd) -+ { -+ case WDIOC_GETSUPPORT: -+ ret = copy_to_user((struct watchdog_info __user *)arg, &ident, sizeof(ident)) ? -EFAULT : 0; -+ break; -+ -+ case WDIOC_KEEPALIVE: -+ ar2315_wdt_enable(); -+ ret = 0; -+ break; -+ -+ case WDIOC_SETTIMEOUT: -+ if((ret = get_user(new_wdt_timeout, (int __user *)arg))) -+ break; -+ wdt_timeout = HEARTBEAT(new_wdt_timeout); -+ ar2315_wdt_enable(); -+ break; -+ -+ case WDIOC_GETTIMEOUT: -+ ret = put_user(wdt_timeout, (int __user *)arg); -+ break; -+ } -+ return ret; -+} -+ -+static struct file_operations ar2315_wdt_fops = { -+ .owner = THIS_MODULE, -+ .llseek = no_llseek, -+ .write = ar2315_wdt_write, -+ .unlocked_ioctl = ar2315_wdt_ioctl, -+ .open = ar2315_wdt_open, -+ .release = ar2315_wdt_release, -+}; -+ -+static struct miscdevice ar2315_wdt_miscdev = { -+ .minor = WATCHDOG_MINOR, -+ .name = "watchdog", -+ .fops = &ar2315_wdt_fops, -+}; -+ -+static int -+ar2315_wdt_probe(struct platform_device *dev) -+{ -+ int ret = 0; -+ -+ ar2315_wdt_enable(); -+ ret = request_irq(AR531X_MISC_IRQ_WATCHDOG, ar2315_wdt_interrupt, IRQF_DISABLED, "ar2315_wdt", NULL); -+ if(ret) -+ { -+ printk(KERN_ERR "ar2315wdt: failed to register inetrrupt\n"); -+ goto out; -+ } -+ -+ ret = misc_register(&ar2315_wdt_miscdev); -+ if(ret) -+ printk(KERN_ERR "ar2315wdt: failed to register miscdev\n"); -+ -+out: -+ return ret; -+} -+ -+static int -+ar2315_wdt_remove(struct platform_device *dev) -+{ -+ misc_deregister(&ar2315_wdt_miscdev); -+ free_irq(AR531X_MISC_IRQ_WATCHDOG, NULL); -+ return 0; -+} -+ -+static struct platform_driver ar2315_wdt_driver = { -+ .probe = ar2315_wdt_probe, -+ .remove = ar2315_wdt_remove, -+ .driver = { -+ .name = "ar2315_wdt", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init -+init_ar2315_wdt(void) -+{ -+ int ret = platform_driver_register(&ar2315_wdt_driver); -+ if(ret) -+ printk(KERN_INFO "ar2315_wdt: error registering platfom driver!"); -+ return ret; -+} -+ -+static void __exit -+exit_ar2315_wdt(void) -+{ -+ platform_driver_unregister(&ar2315_wdt_driver); -+} -+ -+module_init(init_ar2315_wdt); -+module_exit(exit_ar2315_wdt); diff --git a/target/linux/patches/2.6.39/gemalto.patch b/target/linux/patches/2.6.39/gemalto.patch deleted file mode 100644 index f3c223b5e..000000000 --- a/target/linux/patches/2.6.39/gemalto.patch +++ /dev/null @@ -1,11 +0,0 @@ -diff -Nur linux-2.6.36.orig/drivers/tty/serial/serial_cs.c linux-2.6.36/drivers/serial/serial_cs.c ---- linux-2.6.36.orig/drivers/tty/serial/serial_cs.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/drivers/tty/serial/serial_cs.c 2010-12-13 23:03:40.000000000 +0100 -@@ -794,6 +794,7 @@ - PCMCIA_DEVICE_MANF_CARD(0x0137, 0x0025), - PCMCIA_DEVICE_MANF_CARD(0x0137, 0x0045), - PCMCIA_DEVICE_MANF_CARD(0x0137, 0x0052), -+ PCMCIA_DEVICE_MANF_CARD(0x0157, 0x0100), /* Gemalto SCR */ - PCMCIA_DEVICE_MANF_CARD(0x016c, 0x0006), /* Psion 56K+Fax */ - PCMCIA_DEVICE_MANF_CARD(0x0200, 0x0001), /* MultiMobile */ - PCMCIA_DEVICE_PROD_ID134("ADV", "TECH", "COMpad-32/85", 0x67459937, 0x916d02ba, 0x8fbe92ae), diff --git a/target/linux/patches/2.6.39/mips-malta.patch b/target/linux/patches/2.6.39/mips-malta.patch deleted file mode 100644 index cc8789dca..000000000 --- a/target/linux/patches/2.6.39/mips-malta.patch +++ /dev/null @@ -1,135 +0,0 @@ -http://lkml.indiana.edu/hypermail/linux/kernel/1105.3/02199.html - -diff -Nur linux-2.6.39.orig/arch/mips/include/asm/smp-ops.h linux-2.6.39/arch/mips/include/asm/smp-ops.h ---- linux-2.6.39.orig/arch/mips/include/asm/smp-ops.h 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/arch/mips/include/asm/smp-ops.h 2011-08-29 04:39:03.360480881 +0200 -@@ -56,8 +56,43 @@ - - #endif /* !CONFIG_SMP */ - --extern struct plat_smp_ops up_smp_ops; --extern struct plat_smp_ops cmp_smp_ops; --extern struct plat_smp_ops vsmp_smp_ops; -+static inline int register_up_smp_ops(void) -+{ -+#ifdef CONFIG_SMP_UP -+ extern struct plat_smp_ops up_smp_ops; -+ -+ register_smp_ops(&up_smp_ops); -+ -+ return 0; -+#else -+ return -ENODEV; -+#endif -+} -+ -+static inline int register_cmp_smp_ops(void) -+{ -+#ifdef CONFIG_MIPS_CMP -+ extern struct plat_smp_ops cmp_smp_ops; -+ -+ register_smp_ops(&cmp_smp_ops); -+ -+ return 0; -+#else -+ return -ENODEV; -+#endif -+} -+ -+static inline int register_vsmp_smp_ops(void) -+{ -+#ifdef CONFIG_MIPS_MT_SMP -+ extern struct plat_smp_ops vsmp_smp_ops; -+ -+ register_smp_ops(&vsmp_smp_ops); -+ -+ return 0; -+#else -+ return -ENODEV; -+#endif -+} - - #endif /* __ASM_SMP_OPS_H */ -diff -Nur linux-2.6.39.orig/arch/mips/mipssim/sim_setup.c linux-2.6.39/arch/mips/mipssim/sim_setup.c ---- linux-2.6.39.orig/arch/mips/mipssim/sim_setup.c 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/arch/mips/mipssim/sim_setup.c 2011-08-29 04:39:03.390480572 +0200 -@@ -59,18 +59,17 @@ - - prom_meminit(); - --#ifdef CONFIG_MIPS_MT_SMP -- if (cpu_has_mipsmt) -- register_smp_ops(&vsmp_smp_ops); -- else -- register_smp_ops(&up_smp_ops); --#endif -+ if (cpu_has_mipsmt) { -+ if (!register_vsmp_smp_ops()) -+ return; -+ - #ifdef CONFIG_MIPS_MT_SMTC -- if (cpu_has_mipsmt) - register_smp_ops(&ssmtc_smp_ops); -- else -- register_smp_ops(&up_smp_ops); -+ return; - #endif -+ } -+ -+ register_up_smp_ops(); - } - - static void __init serial_init(void) -diff -Nur linux-2.6.39.orig/arch/mips/mti-malta/malta-init.c linux-2.6.39/arch/mips/mti-malta/malta-init.c ---- linux-2.6.39.orig/arch/mips/mti-malta/malta-init.c 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/arch/mips/mti-malta/malta-init.c 2011-08-29 04:39:03.700480601 +0200 -@@ -29,6 +29,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -358,15 +359,14 @@ - #ifdef CONFIG_SERIAL_8250_CONSOLE - console_config(); - #endif --#ifdef CONFIG_MIPS_CMP - /* Early detection of CMP support */ - if (gcmp_probe(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ)) -- register_smp_ops(&cmp_smp_ops); -- else --#endif --#ifdef CONFIG_MIPS_MT_SMP -- register_smp_ops(&vsmp_smp_ops); --#endif -+ if (!register_cmp_smp_ops()) -+ return; -+ -+ if (!register_vsmp_smp_ops()) -+ return; -+ - #ifdef CONFIG_MIPS_MT_SMTC - register_smp_ops(&msmtc_smp_ops); - #endif -diff -Nur linux-2.6.39.orig/arch/mips/pmc-sierra/msp71xx/msp_setup.c linux-2.6.39/arch/mips/pmc-sierra/msp71xx/msp_setup.c ---- linux-2.6.39.orig/arch/mips/pmc-sierra/msp71xx/msp_setup.c 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/arch/mips/pmc-sierra/msp71xx/msp_setup.c 2011-08-29 04:39:03.790480302 +0200 -@@ -228,13 +228,11 @@ - */ - msp_serial_setup(); - --#ifdef CONFIG_MIPS_MT_SMP -- register_smp_ops(&vsmp_smp_ops); --#endif -- -+ if (register_vsmp_smp_ops()) { - #ifdef CONFIG_MIPS_MT_SMTC -- register_smp_ops(&msp_smtc_smp_ops); -+ register_smp_ops(&msp_smtc_smp_ops); - #endif -+ } - - #ifdef CONFIG_PMCTWILED - /* diff --git a/target/linux/patches/2.6.39/mmc-host.patch b/target/linux/patches/2.6.39/mmc-host.patch deleted file mode 100644 index 3d0e37add..000000000 --- a/target/linux/patches/2.6.39/mmc-host.patch +++ /dev/null @@ -1,36 +0,0 @@ -diff -Nur linux-2.6.39-rc6.orig/drivers/mmc/host/Kconfig linux-2.6.39-rc6/drivers/mmc/host/Kconfig ---- linux-2.6.39-rc6.orig/drivers/mmc/host/Kconfig 2011-05-04 04:59:13.000000000 +0200 -+++ linux-2.6.39-rc6/drivers/mmc/host/Kconfig 2011-05-10 23:39:01.000000000 +0200 -@@ -253,13 +253,6 @@ - - If unsure, say N. - --choice -- prompt "Atmel SD/MMC Driver" -- depends on AVR32 || ARCH_AT91 -- default MMC_ATMELMCI if AVR32 -- help -- Choose which driver to use for the Atmel MCI Silicon -- - config MMC_AT91 - tristate "AT91 SD/MMC Card Interface support" - depends on ARCH_AT91 -@@ -268,18 +261,6 @@ - - If unsure, say N. - --config MMC_ATMELMCI -- tristate "Atmel Multimedia Card Interface support" -- depends on AVR32 || ARCH_AT91 -- help -- This selects the Atmel Multimedia Card Interface driver. If -- you have an AT32 (AVR32) or AT91 platform with a Multimedia -- Card slot, say Y or M here. -- -- If unsure, say N. -- --endchoice -- - config MMC_ATMELMCI_DMA - bool "Atmel MCI DMA support (EXPERIMENTAL)" - depends on MMC_ATMELMCI && (AVR32 || ARCH_AT91SAM9G45) && DMA_ENGINE && EXPERIMENTAL diff --git a/target/linux/patches/2.6.39/non-static.patch b/target/linux/patches/2.6.39/non-static.patch deleted file mode 100644 index a967703d0..000000000 --- a/target/linux/patches/2.6.39/non-static.patch +++ /dev/null @@ -1,33 +0,0 @@ -diff -Nur linux-2.6.39-rc6.orig/fs/namei.c linux-2.6.39-rc6/fs/namei.c ---- linux-2.6.39-rc6.orig/fs/namei.c 2011-05-04 04:59:13.000000000 +0200 -+++ linux-2.6.39-rc6/fs/namei.c 2011-05-05 11:30:14.000000000 +0200 -@@ -1769,7 +1769,7 @@ - * needs parent already locked. Doesn't follow mounts. - * SMP-safe. - */ --static struct dentry *lookup_hash(struct nameidata *nd) -+struct dentry *lookup_hash(struct nameidata *nd) - { - return __lookup_hash(&nd->last, nd->path.dentry, nd); - } -diff -Nur linux-2.6.39-rc6.orig/fs/splice.c linux-2.6.39-rc6/fs/splice.c ---- linux-2.6.39-rc6.orig/fs/splice.c 2011-05-04 04:59:13.000000000 +0200 -+++ linux-2.6.39-rc6/fs/splice.c 2011-05-05 11:31:04.000000000 +0200 -@@ -1081,7 +1081,7 @@ - /* - * Attempt to initiate a splice from pipe to file. - */ --static long do_splice_from(struct pipe_inode_info *pipe, struct file *out, -+long do_splice_from(struct pipe_inode_info *pipe, struct file *out, - loff_t *ppos, size_t len, unsigned int flags) - { - ssize_t (*splice_write)(struct pipe_inode_info *, struct file *, -@@ -1109,7 +1109,7 @@ - /* - * Attempt to initiate a splice from a file to a pipe. - */ --static long do_splice_to(struct file *in, loff_t *ppos, -+long do_splice_to(struct file *in, loff_t *ppos, - struct pipe_inode_info *pipe, size_t len, - unsigned int flags) - { diff --git a/target/linux/patches/2.6.39/ocf-20100325.patch b/target/linux/patches/2.6.39/ocf-20100325.patch deleted file mode 100644 index b26a65bc1..000000000 --- a/target/linux/patches/2.6.39/ocf-20100325.patch +++ /dev/null @@ -1,90176 +0,0 @@ -diff -Nur linux-2.6.39.orig/crypto/Kconfig linux-2.6.39/crypto/Kconfig ---- linux-2.6.39.orig/crypto/Kconfig 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/crypto/Kconfig 2011-08-01 14:38:18.000000000 +0200 -@@ -866,3 +866,6 @@ - source "drivers/crypto/Kconfig" - - endif # if CRYPTO -+ -+source "crypto/ocf/Kconfig" -+ -diff -Nur linux-2.6.39.orig/crypto/Kconfig.orig linux-2.6.39/crypto/Kconfig.orig ---- linux-2.6.39.orig/crypto/Kconfig.orig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/Kconfig.orig 2011-08-01 14:38:18.000000000 +0200 -@@ -0,0 +1,868 @@ -+# -+# Generic algorithms support -+# -+config XOR_BLOCKS -+ tristate -+ -+# -+# async_tx api: hardware offloaded memory transfer/transform support -+# -+source "crypto/async_tx/Kconfig" -+ -+# -+# Cryptographic API Configuration -+# -+menuconfig CRYPTO -+ tristate "Cryptographic API" -+ help -+ This option provides the core Cryptographic API. -+ -+if CRYPTO -+ -+comment "Crypto core or helper" -+ -+config CRYPTO_FIPS -+ bool "FIPS 200 compliance" -+ depends on CRYPTO_ANSI_CPRNG && !CRYPTO_MANAGER_DISABLE_TESTS -+ help -+ This options enables the fips boot option which is -+ required if you want to system to operate in a FIPS 200 -+ certification. You should say no unless you know what -+ this is. -+ -+config CRYPTO_ALGAPI -+ tristate -+ select CRYPTO_ALGAPI2 -+ help -+ This option provides the API for cryptographic algorithms. -+ -+config CRYPTO_ALGAPI2 -+ tristate -+ -+config CRYPTO_AEAD -+ tristate -+ select CRYPTO_AEAD2 -+ select CRYPTO_ALGAPI -+ -+config CRYPTO_AEAD2 -+ tristate -+ select CRYPTO_ALGAPI2 -+ -+config CRYPTO_BLKCIPHER -+ tristate -+ select CRYPTO_BLKCIPHER2 -+ select CRYPTO_ALGAPI -+ -+config CRYPTO_BLKCIPHER2 -+ tristate -+ select CRYPTO_ALGAPI2 -+ select CRYPTO_RNG2 -+ select CRYPTO_WORKQUEUE -+ -+config CRYPTO_HASH -+ tristate -+ select CRYPTO_HASH2 -+ select CRYPTO_ALGAPI -+ -+config CRYPTO_HASH2 -+ tristate -+ select CRYPTO_ALGAPI2 -+ -+config CRYPTO_RNG -+ tristate -+ select CRYPTO_RNG2 -+ select CRYPTO_ALGAPI -+ -+config CRYPTO_RNG2 -+ tristate -+ select CRYPTO_ALGAPI2 -+ -+config CRYPTO_PCOMP -+ tristate -+ select CRYPTO_PCOMP2 -+ select CRYPTO_ALGAPI -+ -+config CRYPTO_PCOMP2 -+ tristate -+ select CRYPTO_ALGAPI2 -+ -+config CRYPTO_MANAGER -+ tristate "Cryptographic algorithm manager" -+ select CRYPTO_MANAGER2 -+ help -+ Create default cryptographic template instantiations such as -+ cbc(aes). -+ -+config CRYPTO_MANAGER2 -+ def_tristate CRYPTO_MANAGER || (CRYPTO_MANAGER!=n && CRYPTO_ALGAPI=y) -+ select CRYPTO_AEAD2 -+ select CRYPTO_HASH2 -+ select CRYPTO_BLKCIPHER2 -+ select CRYPTO_PCOMP2 -+ -+config CRYPTO_MANAGER_DISABLE_TESTS -+ bool "Disable run-time self tests" -+ default y -+ depends on CRYPTO_MANAGER2 -+ help -+ Disable run-time self tests that normally take place at -+ algorithm registration. -+ -+config CRYPTO_GF128MUL -+ tristate "GF(2^128) multiplication functions (EXPERIMENTAL)" -+ help -+ Efficient table driven implementation of multiplications in the -+ field GF(2^128). This is needed by some cypher modes. This -+ option will be selected automatically if you select such a -+ cipher mode. Only select this option by hand if you expect to load -+ an external module that requires these functions. -+ -+config CRYPTO_NULL -+ tristate "Null algorithms" -+ select CRYPTO_ALGAPI -+ select CRYPTO_BLKCIPHER -+ select CRYPTO_HASH -+ help -+ These are 'Null' algorithms, used by IPsec, which do nothing. -+ -+config CRYPTO_PCRYPT -+ tristate "Parallel crypto engine (EXPERIMENTAL)" -+ depends on SMP && EXPERIMENTAL -+ select PADATA -+ select CRYPTO_MANAGER -+ select CRYPTO_AEAD -+ help -+ This converts an arbitrary crypto algorithm into a parallel -+ algorithm that executes in kernel threads. -+ -+config CRYPTO_WORKQUEUE -+ tristate -+ -+config CRYPTO_CRYPTD -+ tristate "Software async crypto daemon" -+ select CRYPTO_BLKCIPHER -+ select CRYPTO_HASH -+ select CRYPTO_MANAGER -+ select CRYPTO_WORKQUEUE -+ help -+ This is a generic software asynchronous crypto daemon that -+ converts an arbitrary synchronous software crypto algorithm -+ into an asynchronous algorithm that executes in a kernel thread. -+ -+config CRYPTO_AUTHENC -+ tristate "Authenc support" -+ select CRYPTO_AEAD -+ select CRYPTO_BLKCIPHER -+ select CRYPTO_MANAGER -+ select CRYPTO_HASH -+ help -+ Authenc: Combined mode wrapper for IPsec. -+ This is required for IPSec. -+ -+config CRYPTO_TEST -+ tristate "Testing module" -+ depends on m -+ select CRYPTO_MANAGER -+ help -+ Quick & dirty crypto test module. -+ -+comment "Authenticated Encryption with Associated Data" -+ -+config CRYPTO_CCM -+ tristate "CCM support" -+ select CRYPTO_CTR -+ select CRYPTO_AEAD -+ help -+ Support for Counter with CBC MAC. Required for IPsec. -+ -+config CRYPTO_GCM -+ tristate "GCM/GMAC support" -+ select CRYPTO_CTR -+ select CRYPTO_AEAD -+ select CRYPTO_GHASH -+ help -+ Support for Galois/Counter Mode (GCM) and Galois Message -+ Authentication Code (GMAC). Required for IPSec. -+ -+config CRYPTO_SEQIV -+ tristate "Sequence Number IV Generator" -+ select CRYPTO_AEAD -+ select CRYPTO_BLKCIPHER -+ select CRYPTO_RNG -+ help -+ This IV generator generates an IV based on a sequence number by -+ xoring it with a salt. This algorithm is mainly useful for CTR -+ -+comment "Block modes" -+ -+config CRYPTO_CBC -+ tristate "CBC support" -+ select CRYPTO_BLKCIPHER -+ select CRYPTO_MANAGER -+ help -+ CBC: Cipher Block Chaining mode -+ This block cipher algorithm is required for IPSec. -+ -+config CRYPTO_CTR -+ tristate "CTR support" -+ select CRYPTO_BLKCIPHER -+ select CRYPTO_SEQIV -+ select CRYPTO_MANAGER -+ help -+ CTR: Counter mode -+ This block cipher algorithm is required for IPSec. -+ -+config CRYPTO_CTS -+ tristate "CTS support" -+ select CRYPTO_BLKCIPHER -+ help -+ CTS: Cipher Text Stealing -+ This is the Cipher Text Stealing mode as described by -+ Section 8 of rfc2040 and referenced by rfc3962. -+ (rfc3962 includes errata information in its Appendix A) -+ This mode is required for Kerberos gss mechanism support -+ for AES encryption. -+ -+config CRYPTO_ECB -+ tristate "ECB support" -+ select CRYPTO_BLKCIPHER -+ select CRYPTO_MANAGER -+ help -+ ECB: Electronic CodeBook mode -+ This is the simplest block cipher algorithm. It simply encrypts -+ the input block by block. -+ -+config CRYPTO_LRW -+ tristate "LRW support (EXPERIMENTAL)" -+ depends on EXPERIMENTAL -+ select CRYPTO_BLKCIPHER -+ select CRYPTO_MANAGER -+ select CRYPTO_GF128MUL -+ help -+ LRW: Liskov Rivest Wagner, a tweakable, non malleable, non movable -+ narrow block cipher mode for dm-crypt. Use it with cipher -+ specification string aes-lrw-benbi, the key must be 256, 320 or 384. -+ The first 128, 192 or 256 bits in the key are used for AES and the -+ rest is used to tie each cipher block to its logical position. -+ -+config CRYPTO_PCBC -+ tristate "PCBC support" -+ select CRYPTO_BLKCIPHER -+ select CRYPTO_MANAGER -+ help -+ PCBC: Propagating Cipher Block Chaining mode -+ This block cipher algorithm is required for RxRPC. -+ -+config CRYPTO_XTS -+ tristate "XTS support (EXPERIMENTAL)" -+ depends on EXPERIMENTAL -+ select CRYPTO_BLKCIPHER -+ select CRYPTO_MANAGER -+ select CRYPTO_GF128MUL -+ help -+ XTS: IEEE1619/D16 narrow block cipher use with aes-xts-plain, -+ key size 256, 384 or 512 bits. This implementation currently -+ can't handle a sectorsize which is not a multiple of 16 bytes. -+ -+config CRYPTO_FPU -+ tristate -+ select CRYPTO_BLKCIPHER -+ select CRYPTO_MANAGER -+ -+comment "Hash modes" -+ -+config CRYPTO_HMAC -+ tristate "HMAC support" -+ select CRYPTO_HASH -+ select CRYPTO_MANAGER -+ help -+ HMAC: Keyed-Hashing for Message Authentication (RFC2104). -+ This is required for IPSec. -+ -+config CRYPTO_XCBC -+ tristate "XCBC support" -+ depends on EXPERIMENTAL -+ select CRYPTO_HASH -+ select CRYPTO_MANAGER -+ help -+ XCBC: Keyed-Hashing with encryption algorithm -+ http://www.ietf.org/rfc/rfc3566.txt -+ http://csrc.nist.gov/encryption/modes/proposedmodes/ -+ xcbc-mac/xcbc-mac-spec.pdf -+ -+config CRYPTO_VMAC -+ tristate "VMAC support" -+ depends on EXPERIMENTAL -+ select CRYPTO_HASH -+ select CRYPTO_MANAGER -+ help -+ VMAC is a message authentication algorithm designed for -+ very high speed on 64-bit architectures. -+ -+ See also: -+ -+ -+comment "Digest" -+ -+config CRYPTO_CRC32C -+ tristate "CRC32c CRC algorithm" -+ select CRYPTO_HASH -+ help -+ Castagnoli, et al Cyclic Redundancy-Check Algorithm. Used -+ by iSCSI for header and data digests and by others. -+ See Castagnoli93. Module will be crc32c. -+ -+config CRYPTO_CRC32C_INTEL -+ tristate "CRC32c INTEL hardware acceleration" -+ depends on X86 -+ select CRYPTO_HASH -+ help -+ In Intel processor with SSE4.2 supported, the processor will -+ support CRC32C implementation using hardware accelerated CRC32 -+ instruction. This option will create 'crc32c-intel' module, -+ which will enable any routine to use the CRC32 instruction to -+ gain performance compared with software implementation. -+ Module will be crc32c-intel. -+ -+config CRYPTO_GHASH -+ tristate "GHASH digest algorithm" -+ select CRYPTO_SHASH -+ select CRYPTO_GF128MUL -+ help -+ GHASH is message digest algorithm for GCM (Galois/Counter Mode). -+ -+config CRYPTO_MD4 -+ tristate "MD4 digest algorithm" -+ select CRYPTO_HASH -+ help -+ MD4 message digest algorithm (RFC1320). -+ -+config CRYPTO_MD5 -+ tristate "MD5 digest algorithm" -+ select CRYPTO_HASH -+ help -+ MD5 message digest algorithm (RFC1321). -+ -+config CRYPTO_MICHAEL_MIC -+ tristate "Michael MIC keyed digest algorithm" -+ select CRYPTO_HASH -+ help -+ Michael MIC is used for message integrity protection in TKIP -+ (IEEE 802.11i). This algorithm is required for TKIP, but it -+ should not be used for other purposes because of the weakness -+ of the algorithm. -+ -+config CRYPTO_RMD128 -+ tristate "RIPEMD-128 digest algorithm" -+ select CRYPTO_HASH -+ help -+ RIPEMD-128 (ISO/IEC 10118-3:2004). -+ -+ RIPEMD-128 is a 128-bit cryptographic hash function. It should only -+ to be used as a secure replacement for RIPEMD. For other use cases -+ RIPEMD-160 should be used. -+ -+ Developed by Hans Dobbertin, Antoon Bosselaers and Bart Preneel. -+ See -+ -+config CRYPTO_RMD160 -+ tristate "RIPEMD-160 digest algorithm" -+ select CRYPTO_HASH -+ help -+ RIPEMD-160 (ISO/IEC 10118-3:2004). -+ -+ RIPEMD-160 is a 160-bit cryptographic hash function. It is intended -+ to be used as a secure replacement for the 128-bit hash functions -+ MD4, MD5 and it's predecessor RIPEMD -+ (not to be confused with RIPEMD-128). -+ -+ It's speed is comparable to SHA1 and there are no known attacks -+ against RIPEMD-160. -+ -+ Developed by Hans Dobbertin, Antoon Bosselaers and Bart Preneel. -+ See -+ -+config CRYPTO_RMD256 -+ tristate "RIPEMD-256 digest algorithm" -+ select CRYPTO_HASH -+ help -+ RIPEMD-256 is an optional extension of RIPEMD-128 with a -+ 256 bit hash. It is intended for applications that require -+ longer hash-results, without needing a larger security level -+ (than RIPEMD-128). -+ -+ Developed by Hans Dobbertin, Antoon Bosselaers and Bart Preneel. -+ See -+ -+config CRYPTO_RMD320 -+ tristate "RIPEMD-320 digest algorithm" -+ select CRYPTO_HASH -+ help -+ RIPEMD-320 is an optional extension of RIPEMD-160 with a -+ 320 bit hash. It is intended for applications that require -+ longer hash-results, without needing a larger security level -+ (than RIPEMD-160). -+ -+ Developed by Hans Dobbertin, Antoon Bosselaers and Bart Preneel. -+ See -+ -+config CRYPTO_SHA1 -+ tristate "SHA1 digest algorithm" -+ select CRYPTO_HASH -+ help -+ SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2). -+ -+config CRYPTO_SHA256 -+ tristate "SHA224 and SHA256 digest algorithm" -+ select CRYPTO_HASH -+ help -+ SHA256 secure hash standard (DFIPS 180-2). -+ -+ This version of SHA implements a 256 bit hash with 128 bits of -+ security against collision attacks. -+ -+ This code also includes SHA-224, a 224 bit hash with 112 bits -+ of security against collision attacks. -+ -+config CRYPTO_SHA512 -+ tristate "SHA384 and SHA512 digest algorithms" -+ select CRYPTO_HASH -+ help -+ SHA512 secure hash standard (DFIPS 180-2). -+ -+ This version of SHA implements a 512 bit hash with 256 bits of -+ security against collision attacks. -+ -+ This code also includes SHA-384, a 384 bit hash with 192 bits -+ of security against collision attacks. -+ -+config CRYPTO_TGR192 -+ tristate "Tiger digest algorithms" -+ select CRYPTO_HASH -+ help -+ Tiger hash algorithm 192, 160 and 128-bit hashes -+ -+ Tiger is a hash function optimized for 64-bit processors while -+ still having decent performance on 32-bit processors. -+ Tiger was developed by Ross Anderson and Eli Biham. -+ -+ See also: -+ . -+ -+config CRYPTO_WP512 -+ tristate "Whirlpool digest algorithms" -+ select CRYPTO_HASH -+ help -+ Whirlpool hash algorithm 512, 384 and 256-bit hashes -+ -+ Whirlpool-512 is part of the NESSIE cryptographic primitives. -+ Whirlpool will be part of the ISO/IEC 10118-3:2003(E) standard -+ -+ See also: -+ -+ -+config CRYPTO_GHASH_CLMUL_NI_INTEL -+ tristate "GHASH digest algorithm (CLMUL-NI accelerated)" -+ depends on (X86 || UML_X86) && 64BIT -+ select CRYPTO_SHASH -+ select CRYPTO_CRYPTD -+ help -+ GHASH is message digest algorithm for GCM (Galois/Counter Mode). -+ The implementation is accelerated by CLMUL-NI of Intel. -+ -+comment "Ciphers" -+ -+config CRYPTO_AES -+ tristate "AES cipher algorithms" -+ select CRYPTO_ALGAPI -+ help -+ AES cipher algorithms (FIPS-197). AES uses the Rijndael -+ algorithm. -+ -+ Rijndael appears to be consistently a very good performer in -+ both hardware and software across a wide range of computing -+ environments regardless of its use in feedback or non-feedback -+ modes. Its key setup time is excellent, and its key agility is -+ good. Rijndael's very low memory requirements make it very well -+ suited for restricted-space environments, in which it also -+ demonstrates excellent performance. Rijndael's operations are -+ among the easiest to defend against power and timing attacks. -+ -+ The AES specifies three key sizes: 128, 192 and 256 bits -+ -+ See for more information. -+ -+config CRYPTO_AES_586 -+ tristate "AES cipher algorithms (i586)" -+ depends on (X86 || UML_X86) && !64BIT -+ select CRYPTO_ALGAPI -+ select CRYPTO_AES -+ help -+ AES cipher algorithms (FIPS-197). AES uses the Rijndael -+ algorithm. -+ -+ Rijndael appears to be consistently a very good performer in -+ both hardware and software across a wide range of computing -+ environments regardless of its use in feedback or non-feedback -+ modes. Its key setup time is excellent, and its key agility is -+ good. Rijndael's very low memory requirements make it very well -+ suited for restricted-space environments, in which it also -+ demonstrates excellent performance. Rijndael's operations are -+ among the easiest to defend against power and timing attacks. -+ -+ The AES specifies three key sizes: 128, 192 and 256 bits -+ -+ See for more information. -+ -+config CRYPTO_AES_X86_64 -+ tristate "AES cipher algorithms (x86_64)" -+ depends on (X86 || UML_X86) && 64BIT -+ select CRYPTO_ALGAPI -+ select CRYPTO_AES -+ help -+ AES cipher algorithms (FIPS-197). AES uses the Rijndael -+ algorithm. -+ -+ Rijndael appears to be consistently a very good performer in -+ both hardware and software across a wide range of computing -+ environments regardless of its use in feedback or non-feedback -+ modes. Its key setup time is excellent, and its key agility is -+ good. Rijndael's very low memory requirements make it very well -+ suited for restricted-space environments, in which it also -+ demonstrates excellent performance. Rijndael's operations are -+ among the easiest to defend against power and timing attacks. -+ -+ The AES specifies three key sizes: 128, 192 and 256 bits -+ -+ See for more information. -+ -+config CRYPTO_AES_NI_INTEL -+ tristate "AES cipher algorithms (AES-NI)" -+ depends on (X86 || UML_X86) -+ select CRYPTO_AES_X86_64 if 64BIT -+ select CRYPTO_AES_586 if !64BIT -+ select CRYPTO_CRYPTD -+ select CRYPTO_ALGAPI -+ select CRYPTO_FPU -+ help -+ Use Intel AES-NI instructions for AES algorithm. -+ -+ AES cipher algorithms (FIPS-197). AES uses the Rijndael -+ algorithm. -+ -+ Rijndael appears to be consistently a very good performer in -+ both hardware and software across a wide range of computing -+ environments regardless of its use in feedback or non-feedback -+ modes. Its key setup time is excellent, and its key agility is -+ good. Rijndael's very low memory requirements make it very well -+ suited for restricted-space environments, in which it also -+ demonstrates excellent performance. Rijndael's operations are -+ among the easiest to defend against power and timing attacks. -+ -+ The AES specifies three key sizes: 128, 192 and 256 bits -+ -+ See for more information. -+ -+ In addition to AES cipher algorithm support, the acceleration -+ for some popular block cipher mode is supported too, including -+ ECB, CBC, LRW, PCBC, XTS. The 64 bit version has additional -+ acceleration for CTR. -+ -+config CRYPTO_ANUBIS -+ tristate "Anubis cipher algorithm" -+ select CRYPTO_ALGAPI -+ help -+ Anubis cipher algorithm. -+ -+ Anubis is a variable key length cipher which can use keys from -+ 128 bits to 320 bits in length. It was evaluated as a entrant -+ in the NESSIE competition. -+ -+ See also: -+ -+ -+ -+config CRYPTO_ARC4 -+ tristate "ARC4 cipher algorithm" -+ select CRYPTO_ALGAPI -+ help -+ ARC4 cipher algorithm. -+ -+ ARC4 is a stream cipher using keys ranging from 8 bits to 2048 -+ bits in length. This algorithm is required for driver-based -+ WEP, but it should not be for other purposes because of the -+ weakness of the algorithm. -+ -+config CRYPTO_BLOWFISH -+ tristate "Blowfish cipher algorithm" -+ select CRYPTO_ALGAPI -+ help -+ Blowfish cipher algorithm, by Bruce Schneier. -+ -+ This is a variable key length cipher which can use keys from 32 -+ bits to 448 bits in length. It's fast, simple and specifically -+ designed for use on "large microprocessors". -+ -+ See also: -+ -+ -+config CRYPTO_CAMELLIA -+ tristate "Camellia cipher algorithms" -+ depends on CRYPTO -+ select CRYPTO_ALGAPI -+ help -+ Camellia cipher algorithms module. -+ -+ Camellia is a symmetric key block cipher developed jointly -+ at NTT and Mitsubishi Electric Corporation. -+ -+ The Camellia specifies three key sizes: 128, 192 and 256 bits. -+ -+ See also: -+ -+ -+config CRYPTO_CAST5 -+ tristate "CAST5 (CAST-128) cipher algorithm" -+ select CRYPTO_ALGAPI -+ help -+ The CAST5 encryption algorithm (synonymous with CAST-128) is -+ described in RFC2144. -+ -+config CRYPTO_CAST6 -+ tristate "CAST6 (CAST-256) cipher algorithm" -+ select CRYPTO_ALGAPI -+ help -+ The CAST6 encryption algorithm (synonymous with CAST-256) is -+ described in RFC2612. -+ -+config CRYPTO_DES -+ tristate "DES and Triple DES EDE cipher algorithms" -+ select CRYPTO_ALGAPI -+ help -+ DES cipher algorithm (FIPS 46-2), and Triple DES EDE (FIPS 46-3). -+ -+config CRYPTO_FCRYPT -+ tristate "FCrypt cipher algorithm" -+ select CRYPTO_ALGAPI -+ select CRYPTO_BLKCIPHER -+ help -+ FCrypt algorithm used by RxRPC. -+ -+config CRYPTO_KHAZAD -+ tristate "Khazad cipher algorithm" -+ select CRYPTO_ALGAPI -+ help -+ Khazad cipher algorithm. -+ -+ Khazad was a finalist in the initial NESSIE competition. It is -+ an algorithm optimized for 64-bit processors with good performance -+ on 32-bit processors. Khazad uses an 128 bit key size. -+ -+ See also: -+ -+ -+config CRYPTO_SALSA20 -+ tristate "Salsa20 stream cipher algorithm (EXPERIMENTAL)" -+ depends on EXPERIMENTAL -+ select CRYPTO_BLKCIPHER -+ help -+ Salsa20 stream cipher algorithm. -+ -+ Salsa20 is a stream cipher submitted to eSTREAM, the ECRYPT -+ Stream Cipher Project. See -+ -+ The Salsa20 stream cipher algorithm is designed by Daniel J. -+ Bernstein . See -+ -+config CRYPTO_SALSA20_586 -+ tristate "Salsa20 stream cipher algorithm (i586) (EXPERIMENTAL)" -+ depends on (X86 || UML_X86) && !64BIT -+ depends on EXPERIMENTAL -+ select CRYPTO_BLKCIPHER -+ help -+ Salsa20 stream cipher algorithm. -+ -+ Salsa20 is a stream cipher submitted to eSTREAM, the ECRYPT -+ Stream Cipher Project. See -+ -+ The Salsa20 stream cipher algorithm is designed by Daniel J. -+ Bernstein . See -+ -+config CRYPTO_SALSA20_X86_64 -+ tristate "Salsa20 stream cipher algorithm (x86_64) (EXPERIMENTAL)" -+ depends on (X86 || UML_X86) && 64BIT -+ depends on EXPERIMENTAL -+ select CRYPTO_BLKCIPHER -+ help -+ Salsa20 stream cipher algorithm. -+ -+ Salsa20 is a stream cipher submitted to eSTREAM, the ECRYPT -+ Stream Cipher Project. See -+ -+ The Salsa20 stream cipher algorithm is designed by Daniel J. -+ Bernstein . See -+ -+config CRYPTO_SEED -+ tristate "SEED cipher algorithm" -+ select CRYPTO_ALGAPI -+ help -+ SEED cipher algorithm (RFC4269). -+ -+ SEED is a 128-bit symmetric key block cipher that has been -+ developed by KISA (Korea Information Security Agency) as a -+ national standard encryption algorithm of the Republic of Korea. -+ It is a 16 round block cipher with the key size of 128 bit. -+ -+ See also: -+ -+ -+config CRYPTO_SERPENT -+ tristate "Serpent cipher algorithm" -+ select CRYPTO_ALGAPI -+ help -+ Serpent cipher algorithm, by Anderson, Biham & Knudsen. -+ -+ Keys are allowed to be from 0 to 256 bits in length, in steps -+ of 8 bits. Also includes the 'Tnepres' algorithm, a reversed -+ variant of Serpent for compatibility with old kerneli.org code. -+ -+ See also: -+ -+ -+config CRYPTO_TEA -+ tristate "TEA, XTEA and XETA cipher algorithms" -+ select CRYPTO_ALGAPI -+ help -+ TEA cipher algorithm. -+ -+ Tiny Encryption Algorithm is a simple cipher that uses -+ many rounds for security. It is very fast and uses -+ little memory. -+ -+ Xtendend Tiny Encryption Algorithm is a modification to -+ the TEA algorithm to address a potential key weakness -+ in the TEA algorithm. -+ -+ Xtendend Encryption Tiny Algorithm is a mis-implementation -+ of the XTEA algorithm for compatibility purposes. -+ -+config CRYPTO_TWOFISH -+ tristate "Twofish cipher algorithm" -+ select CRYPTO_ALGAPI -+ select CRYPTO_TWOFISH_COMMON -+ help -+ Twofish cipher algorithm. -+ -+ Twofish was submitted as an AES (Advanced Encryption Standard) -+ candidate cipher by researchers at CounterPane Systems. It is a -+ 16 round block cipher supporting key sizes of 128, 192, and 256 -+ bits. -+ -+ See also: -+ -+ -+config CRYPTO_TWOFISH_COMMON -+ tristate -+ help -+ Common parts of the Twofish cipher algorithm shared by the -+ generic c and the assembler implementations. -+ -+config CRYPTO_TWOFISH_586 -+ tristate "Twofish cipher algorithms (i586)" -+ depends on (X86 || UML_X86) && !64BIT -+ select CRYPTO_ALGAPI -+ select CRYPTO_TWOFISH_COMMON -+ help -+ Twofish cipher algorithm. -+ -+ Twofish was submitted as an AES (Advanced Encryption Standard) -+ candidate cipher by researchers at CounterPane Systems. It is a -+ 16 round block cipher supporting key sizes of 128, 192, and 256 -+ bits. -+ -+ See also: -+ -+ -+config CRYPTO_TWOFISH_X86_64 -+ tristate "Twofish cipher algorithm (x86_64)" -+ depends on (X86 || UML_X86) && 64BIT -+ select CRYPTO_ALGAPI -+ select CRYPTO_TWOFISH_COMMON -+ help -+ Twofish cipher algorithm (x86_64). -+ -+ Twofish was submitted as an AES (Advanced Encryption Standard) -+ candidate cipher by researchers at CounterPane Systems. It is a -+ 16 round block cipher supporting key sizes of 128, 192, and 256 -+ bits. -+ -+ See also: -+ -+ -+comment "Compression" -+ -+config CRYPTO_DEFLATE -+ tristate "Deflate compression algorithm" -+ select CRYPTO_ALGAPI -+ select ZLIB_INFLATE -+ select ZLIB_DEFLATE -+ help -+ This is the Deflate algorithm (RFC1951), specified for use in -+ IPSec with the IPCOMP protocol (RFC3173, RFC2394). -+ -+ You will most probably want this if using IPSec. -+ -+config CRYPTO_ZLIB -+ tristate "Zlib compression algorithm" -+ select CRYPTO_PCOMP -+ select ZLIB_INFLATE -+ select ZLIB_DEFLATE -+ select NLATTR -+ help -+ This is the zlib algorithm. -+ -+config CRYPTO_LZO -+ tristate "LZO compression algorithm" -+ select CRYPTO_ALGAPI -+ select LZO_COMPRESS -+ select LZO_DECOMPRESS -+ help -+ This is the LZO algorithm. -+ -+comment "Random Number Generation" -+ -+config CRYPTO_ANSI_CPRNG -+ tristate "Pseudo Random Number Generation for Cryptographic modules" -+ default m -+ select CRYPTO_AES -+ select CRYPTO_RNG -+ help -+ This option enables the generic pseudo random number generator -+ for cryptographic modules. Uses the Algorithm specified in -+ ANSI X9.31 A.2.4. Note that this option must be enabled if -+ CRYPTO_FIPS is selected -+ -+config CRYPTO_USER_API -+ tristate -+ -+config CRYPTO_USER_API_HASH -+ tristate "User-space interface for hash algorithms" -+ depends on NET -+ select CRYPTO_HASH -+ select CRYPTO_USER_API -+ help -+ This option enables the user-spaces interface for hash -+ algorithms. -+ -+config CRYPTO_USER_API_SKCIPHER -+ tristate "User-space interface for symmetric key cipher algorithms" -+ depends on NET -+ select CRYPTO_BLKCIPHER -+ select CRYPTO_USER_API -+ help -+ This option enables the user-spaces interface for symmetric -+ key cipher algorithms. -+ -+source "drivers/crypto/Kconfig" -+ -+endif # if CRYPTO -diff -Nur linux-2.6.39.orig/crypto/Makefile linux-2.6.39/crypto/Makefile ---- linux-2.6.39.orig/crypto/Makefile 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/crypto/Makefile 2011-08-01 14:38:18.000000000 +0200 -@@ -89,6 +89,8 @@ - obj-$(CONFIG_CRYPTO_USER_API_HASH) += algif_hash.o - obj-$(CONFIG_CRYPTO_USER_API_SKCIPHER) += algif_skcipher.o - -+obj-$(CONFIG_OCF_OCF) += ocf/ -+ - # - # generic algorithms and the async_tx api - # -diff -Nur linux-2.6.39.orig/crypto/Makefile.orig linux-2.6.39/crypto/Makefile.orig ---- linux-2.6.39.orig/crypto/Makefile.orig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/Makefile.orig 2011-08-01 14:38:18.000000000 +0200 -@@ -0,0 +1,96 @@ -+# -+# Cryptographic API -+# -+ -+obj-$(CONFIG_CRYPTO) += crypto.o -+crypto-y := api.o cipher.o compress.o -+ -+obj-$(CONFIG_CRYPTO_WORKQUEUE) += crypto_wq.o -+ -+obj-$(CONFIG_CRYPTO_FIPS) += fips.o -+ -+crypto_algapi-$(CONFIG_PROC_FS) += proc.o -+crypto_algapi-y := algapi.o scatterwalk.o $(crypto_algapi-y) -+obj-$(CONFIG_CRYPTO_ALGAPI2) += crypto_algapi.o -+ -+obj-$(CONFIG_CRYPTO_AEAD2) += aead.o -+ -+crypto_blkcipher-y := ablkcipher.o -+crypto_blkcipher-y += blkcipher.o -+obj-$(CONFIG_CRYPTO_BLKCIPHER2) += crypto_blkcipher.o -+obj-$(CONFIG_CRYPTO_BLKCIPHER2) += chainiv.o -+obj-$(CONFIG_CRYPTO_BLKCIPHER2) += eseqiv.o -+obj-$(CONFIG_CRYPTO_SEQIV) += seqiv.o -+ -+crypto_hash-y += ahash.o -+crypto_hash-y += shash.o -+obj-$(CONFIG_CRYPTO_HASH2) += crypto_hash.o -+ -+obj-$(CONFIG_CRYPTO_PCOMP2) += pcompress.o -+ -+cryptomgr-y := algboss.o testmgr.o -+ -+obj-$(CONFIG_CRYPTO_MANAGER2) += cryptomgr.o -+obj-$(CONFIG_CRYPTO_HMAC) += hmac.o -+obj-$(CONFIG_CRYPTO_VMAC) += vmac.o -+obj-$(CONFIG_CRYPTO_XCBC) += xcbc.o -+obj-$(CONFIG_CRYPTO_NULL) += crypto_null.o -+obj-$(CONFIG_CRYPTO_MD4) += md4.o -+obj-$(CONFIG_CRYPTO_MD5) += md5.o -+obj-$(CONFIG_CRYPTO_RMD128) += rmd128.o -+obj-$(CONFIG_CRYPTO_RMD160) += rmd160.o -+obj-$(CONFIG_CRYPTO_RMD256) += rmd256.o -+obj-$(CONFIG_CRYPTO_RMD320) += rmd320.o -+obj-$(CONFIG_CRYPTO_SHA1) += sha1_generic.o -+obj-$(CONFIG_CRYPTO_SHA256) += sha256_generic.o -+obj-$(CONFIG_CRYPTO_SHA512) += sha512_generic.o -+obj-$(CONFIG_CRYPTO_WP512) += wp512.o -+obj-$(CONFIG_CRYPTO_TGR192) += tgr192.o -+obj-$(CONFIG_CRYPTO_GF128MUL) += gf128mul.o -+obj-$(CONFIG_CRYPTO_ECB) += ecb.o -+obj-$(CONFIG_CRYPTO_CBC) += cbc.o -+obj-$(CONFIG_CRYPTO_PCBC) += pcbc.o -+obj-$(CONFIG_CRYPTO_CTS) += cts.o -+obj-$(CONFIG_CRYPTO_LRW) += lrw.o -+obj-$(CONFIG_CRYPTO_XTS) += xts.o -+obj-$(CONFIG_CRYPTO_CTR) += ctr.o -+obj-$(CONFIG_CRYPTO_GCM) += gcm.o -+obj-$(CONFIG_CRYPTO_CCM) += ccm.o -+obj-$(CONFIG_CRYPTO_PCRYPT) += pcrypt.o -+obj-$(CONFIG_CRYPTO_CRYPTD) += cryptd.o -+obj-$(CONFIG_CRYPTO_DES) += des_generic.o -+obj-$(CONFIG_CRYPTO_FCRYPT) += fcrypt.o -+obj-$(CONFIG_CRYPTO_BLOWFISH) += blowfish.o -+obj-$(CONFIG_CRYPTO_TWOFISH) += twofish_generic.o -+obj-$(CONFIG_CRYPTO_TWOFISH_COMMON) += twofish_common.o -+obj-$(CONFIG_CRYPTO_SERPENT) += serpent.o -+obj-$(CONFIG_CRYPTO_AES) += aes_generic.o -+obj-$(CONFIG_CRYPTO_CAMELLIA) += camellia.o -+obj-$(CONFIG_CRYPTO_CAST5) += cast5.o -+obj-$(CONFIG_CRYPTO_CAST6) += cast6.o -+obj-$(CONFIG_CRYPTO_ARC4) += arc4.o -+obj-$(CONFIG_CRYPTO_TEA) += tea.o -+obj-$(CONFIG_CRYPTO_KHAZAD) += khazad.o -+obj-$(CONFIG_CRYPTO_ANUBIS) += anubis.o -+obj-$(CONFIG_CRYPTO_SEED) += seed.o -+obj-$(CONFIG_CRYPTO_SALSA20) += salsa20_generic.o -+obj-$(CONFIG_CRYPTO_DEFLATE) += deflate.o -+obj-$(CONFIG_CRYPTO_ZLIB) += zlib.o -+obj-$(CONFIG_CRYPTO_MICHAEL_MIC) += michael_mic.o -+obj-$(CONFIG_CRYPTO_CRC32C) += crc32c.o -+obj-$(CONFIG_CRYPTO_AUTHENC) += authenc.o authencesn.o -+obj-$(CONFIG_CRYPTO_LZO) += lzo.o -+obj-$(CONFIG_CRYPTO_RNG2) += rng.o -+obj-$(CONFIG_CRYPTO_RNG2) += krng.o -+obj-$(CONFIG_CRYPTO_ANSI_CPRNG) += ansi_cprng.o -+obj-$(CONFIG_CRYPTO_TEST) += tcrypt.o -+obj-$(CONFIG_CRYPTO_GHASH) += ghash-generic.o -+obj-$(CONFIG_CRYPTO_USER_API) += af_alg.o -+obj-$(CONFIG_CRYPTO_USER_API_HASH) += algif_hash.o -+obj-$(CONFIG_CRYPTO_USER_API_SKCIPHER) += algif_skcipher.o -+ -+# -+# generic algorithms and the async_tx api -+# -+obj-$(CONFIG_XOR_BLOCKS) += xor.o -+obj-$(CONFIG_ASYNC_CORE) += async_tx/ -diff -Nur linux-2.6.39.orig/crypto/ocf/Config.in linux-2.6.39/crypto/ocf/Config.in ---- linux-2.6.39.orig/crypto/ocf/Config.in 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/Config.in 2011-08-01 14:38:18.000000000 +0200 -@@ -0,0 +1,36 @@ -+############################################################################# -+ -+mainmenu_option next_comment -+comment 'OCF Configuration' -+tristate 'OCF (Open Cryptograhic Framework)' CONFIG_OCF_OCF -+dep_mbool ' enable fips RNG checks (fips check on RNG data before use)' \ -+ CONFIG_OCF_FIPS $CONFIG_OCF_OCF -+dep_mbool ' enable harvesting entropy for /dev/random' \ -+ CONFIG_OCF_RANDOMHARVEST $CONFIG_OCF_OCF -+dep_tristate ' cryptodev (user space support)' \ -+ CONFIG_OCF_CRYPTODEV $CONFIG_OCF_OCF -+dep_tristate ' cryptosoft (software crypto engine)' \ -+ CONFIG_OCF_CRYPTOSOFT $CONFIG_OCF_OCF -+dep_tristate ' safenet (HW crypto engine)' \ -+ CONFIG_OCF_SAFE $CONFIG_OCF_OCF -+dep_tristate ' IXP4xx (HW crypto engine)' \ -+ CONFIG_OCF_IXP4XX $CONFIG_OCF_OCF -+dep_mbool ' Enable IXP4xx HW to perform SHA1 and MD5 hashing (very slow)' \ -+ CONFIG_OCF_IXP4XX_SHA1_MD5 $CONFIG_OCF_IXP4XX -+dep_tristate ' hifn (HW crypto engine)' \ -+ CONFIG_OCF_HIFN $CONFIG_OCF_OCF -+dep_tristate ' talitos (HW crypto engine)' \ -+ CONFIG_OCF_TALITOS $CONFIG_OCF_OCF -+dep_tristate ' pasemi (HW crypto engine)' \ -+ CONFIG_OCF_PASEMI $CONFIG_OCF_OCF -+dep_tristate ' ep80579 (HW crypto engine)' \ -+ CONFIG_OCF_EP80579 $CONFIG_OCF_OCF -+dep_tristate ' Micronas c7108 (HW crypto engine)' \ -+ CONFIG_OCF_C7108 $CONFIG_OCF_OCF -+dep_tristate ' ocfnull (does no crypto)' \ -+ CONFIG_OCF_OCFNULL $CONFIG_OCF_OCF -+dep_tristate ' ocf-bench (HW crypto in-kernel benchmark)' \ -+ CONFIG_OCF_BENCH $CONFIG_OCF_OCF -+endmenu -+ -+############################################################################# -diff -Nur linux-2.6.39.orig/crypto/ocf/Kconfig linux-2.6.39/crypto/ocf/Kconfig ---- linux-2.6.39.orig/crypto/ocf/Kconfig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/Kconfig 2011-08-01 14:38:18.000000000 +0200 -@@ -0,0 +1,119 @@ -+menu "OCF Configuration" -+ -+config OCF_OCF -+ tristate "OCF (Open Cryptograhic Framework)" -+ help -+ A linux port of the OpenBSD/FreeBSD crypto framework. -+ -+config OCF_RANDOMHARVEST -+ bool "crypto random --- harvest entropy for /dev/random" -+ depends on OCF_OCF -+ help -+ Includes code to harvest random numbers from devices that support it. -+ -+config OCF_FIPS -+ bool "enable fips RNG checks" -+ depends on OCF_OCF && OCF_RANDOMHARVEST -+ help -+ Run all RNG provided data through a fips check before -+ adding it /dev/random's entropy pool. -+ -+config OCF_CRYPTODEV -+ tristate "cryptodev (user space support)" -+ depends on OCF_OCF -+ help -+ The user space API to access crypto hardware. -+ -+config OCF_CRYPTOSOFT -+ tristate "cryptosoft (software crypto engine)" -+ depends on OCF_OCF -+ help -+ A software driver for the OCF framework that uses -+ the kernel CryptoAPI. -+ -+config OCF_SAFE -+ tristate "safenet (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ A driver for a number of the safenet Excel crypto accelerators. -+ Currently tested and working on the 1141 and 1741. -+ -+config OCF_IXP4XX -+ tristate "IXP4xx (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ XScale IXP4xx crypto accelerator driver. Requires the -+ Intel Access library. -+ -+config OCF_IXP4XX_SHA1_MD5 -+ bool "IXP4xx SHA1 and MD5 Hashing" -+ depends on OCF_IXP4XX -+ help -+ Allows the IXP4xx crypto accelerator to perform SHA1 and MD5 hashing. -+ Note: this is MUCH slower than using cryptosoft (software crypto engine). -+ -+config OCF_HIFN -+ tristate "hifn (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for various HIFN based crypto accelerators. -+ (7951, 7955, 7956, 7751, 7811) -+ -+config OCF_HIFNHIPP -+ tristate "Hifn HIPP (HW packet crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for various HIFN (HIPP) based crypto accelerators -+ (7855) -+ -+config OCF_TALITOS -+ tristate "talitos (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for Freescale's security engine (SEC/talitos). -+ -+config OCF_PASEMI -+ tristate "pasemi (HW crypto engine)" -+ depends on OCF_OCF && PPC_PASEMI -+ help -+ OCF driver for the PA Semi PWRficient DMA Engine -+ -+config OCF_EP80579 -+ tristate "ep80579 (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for the Intel EP80579 Integrated Processor Product Line. -+ -+config OCF_CRYPTOCTEON -+ tristate "cryptocteon (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for the Cavium OCTEON Processors. -+ -+config OCF_KIRKWOOD -+ tristate "kirkwood (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for the Marvell Kirkwood (88F6xxx) Processors. -+ -+config OCF_C7108 -+ tristate "Micronas 7108 (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for the Microna 7108 Cipher processors. -+ -+config OCF_OCFNULL -+ tristate "ocfnull (fake crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for measuring ipsec overheads (does no crypto) -+ -+config OCF_BENCH -+ tristate "ocf-bench (HW crypto in-kernel benchmark)" -+ depends on OCF_OCF -+ help -+ A very simple encryption test for the in-kernel interface -+ of OCF. Also includes code to benchmark the IXP Access library -+ for comparison. -+ -+endmenu -diff -Nur linux-2.6.39.orig/crypto/ocf/Makefile linux-2.6.39/crypto/ocf/Makefile ---- linux-2.6.39.orig/crypto/ocf/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/Makefile 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,124 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+OCF_OBJS = crypto.o criov.o -+ -+ifdef CONFIG_OCF_RANDOMHARVEST -+ OCF_OBJS += random.o -+endif -+ -+ifdef CONFIG_OCF_FIPS -+ OCF_OBJS += rndtest.o -+endif -+ -+# Add in autoconf.h to get #defines for CONFIG_xxx -+AUTOCONF_H=$(ROOTDIR)/modules/autoconf.h -+ifeq ($(AUTOCONF_H), $(wildcard $(AUTOCONF_H))) -+ EXTRA_CFLAGS += -include $(AUTOCONF_H) -+ export EXTRA_CFLAGS -+endif -+ -+ifndef obj -+ obj ?= . -+ _obj = subdir -+ mod-subdirs := safe hifn ixp4xx talitos ocfnull -+ export-objs += crypto.o criov.o random.o -+ list-multi += ocf.o -+ _slash := -+else -+ _obj = obj -+ _slash := / -+endif -+ -+EXTRA_CFLAGS += -I$(obj)/. -+ -+obj-$(CONFIG_OCF_OCF) += ocf.o -+obj-$(CONFIG_OCF_CRYPTODEV) += cryptodev.o -+obj-$(CONFIG_OCF_CRYPTOSOFT) += cryptosoft.o -+obj-$(CONFIG_OCF_BENCH) += ocf-bench.o -+ -+$(_obj)-$(CONFIG_OCF_SAFE) += safe$(_slash) -+$(_obj)-$(CONFIG_OCF_HIFN) += hifn$(_slash) -+$(_obj)-$(CONFIG_OCF_IXP4XX) += ixp4xx$(_slash) -+$(_obj)-$(CONFIG_OCF_TALITOS) += talitos$(_slash) -+$(_obj)-$(CONFIG_OCF_PASEMI) += pasemi$(_slash) -+$(_obj)-$(CONFIG_OCF_EP80579) += ep80579$(_slash) -+$(_obj)-$(CONFIG_OCF_CRYPTOCTEON) += cryptocteon$(_slash) -+$(_obj)-$(CONFIG_OCF_KIRKWOOD) += kirkwood$(_slash) -+$(_obj)-$(CONFIG_OCF_OCFNULL) += ocfnull$(_slash) -+$(_obj)-$(CONFIG_OCF_C7108) += c7108$(_slash) -+ -+ocf-objs := $(OCF_OBJS) -+ -+$(list-multi) dummy1: $(ocf-objs) -+ $(LD) -r -o $@ $(ocf-objs) -+ -+.PHONY: -+clean: -+ rm -f *.o *.ko .*.o.flags .*.ko.cmd .*.o.cmd .*.mod.o.cmd *.mod.c -+ rm -f */*.o */*.ko */.*.o.cmd */.*.ko.cmd */.*.mod.o.cmd */*.mod.c */.*.o.flags -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -+# -+# release gen targets -+# -+ -+.PHONY: patch -+patch: -+ REL=`date +%Y%m%d`; \ -+ patch=ocf-linux-$$REL.patch; \ -+ patch24=ocf-linux-24-$$REL.patch; \ -+ patch26=ocf-linux-26-$$REL.patch; \ -+ ( \ -+ find . -name Makefile; \ -+ find . -name Config.in; \ -+ find . -name Kconfig; \ -+ find . -name README; \ -+ find . -name '*.[ch]' | grep -v '.mod.c'; \ -+ ) | while read t; do \ -+ diff -Nau /dev/null $$t | sed 's?^+++ \./?+++ linux/crypto/ocf/?'; \ -+ done > $$patch; \ -+ cat patches/linux-2.4.35-ocf.patch $$patch > $$patch24; \ -+ cat patches/linux-2.6.33-ocf.patch $$patch > $$patch26 -+ -+.PHONY: tarball -+tarball: -+ REL=`date +%Y%m%d`; RELDIR=/tmp/ocf-linux-$$REL; \ -+ CURDIR=`pwd`; \ -+ rm -rf /tmp/ocf-linux-$$REL*; \ -+ mkdir -p $$RELDIR/tools; \ -+ cp README* $$RELDIR; \ -+ cp patches/openss*.patch $$RELDIR; \ -+ cp patches/crypto-tools.patch $$RELDIR; \ -+ cp tools/[!C]* $$RELDIR/tools; \ -+ cd ..; \ -+ tar cvf $$RELDIR/ocf-linux.tar \ -+ --exclude=CVS \ -+ --exclude=.* \ -+ --exclude=*.o \ -+ --exclude=*.ko \ -+ --exclude=*.mod.* \ -+ --exclude=README* \ -+ --exclude=ocf-*.patch \ -+ --exclude=ocf/patches/openss*.patch \ -+ --exclude=ocf/patches/crypto-tools.patch \ -+ --exclude=ocf/tools \ -+ ocf; \ -+ gzip -9 $$RELDIR/ocf-linux.tar; \ -+ cd /tmp; \ -+ tar cvf ocf-linux-$$REL.tar ocf-linux-$$REL; \ -+ gzip -9 ocf-linux-$$REL.tar; \ -+ cd $$CURDIR/../../user; \ -+ rm -rf /tmp/crypto-tools-$$REL*; \ -+ tar cvf /tmp/crypto-tools-$$REL.tar \ -+ --exclude=CVS \ -+ --exclude=.* \ -+ --exclude=*.o \ -+ --exclude=cryptotest \ -+ --exclude=cryptokeytest \ -+ crypto-tools; \ -+ gzip -9 /tmp/crypto-tools-$$REL.tar -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/README linux-2.6.39/crypto/ocf/README ---- linux-2.6.39.orig/crypto/ocf/README 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/README 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,167 @@ -+README - ocf-linux-20100325 -+--------------------------- -+ -+This README provides instructions for getting ocf-linux compiled and -+operating in a generic linux environment. For other information you -+might like to visit the home page for this project: -+ -+ http://ocf-linux.sourceforge.net/ -+ -+Adding OCF to linux -+------------------- -+ -+ Not much in this file for now, just some notes. I usually build -+ the ocf support as modules but it can be built into the kernel as -+ well. To use it: -+ -+ * mknod /dev/crypto c 10 70 -+ -+ * to add OCF to your kernel source, you have two options. Apply -+ the kernel specific patch: -+ -+ cd linux-2.4*; gunzip < ocf-linux-24-XXXXXXXX.patch.gz | patch -p1 -+ cd linux-2.6*; gunzip < ocf-linux-26-XXXXXXXX.patch.gz | patch -p1 -+ -+ if you do one of the above, then you can proceed to the next step, -+ or you can do the above process by hand with using the patches against -+ linux-2.4.35 and 2.6.33 to include the ocf code under crypto/ocf. -+ Here's how to add it: -+ -+ for 2.4.35 (and later) -+ -+ cd linux-2.4.35/crypto -+ tar xvzf ocf-linux.tar.gz -+ cd .. -+ patch -p1 < crypto/ocf/patches/linux-2.4.35-ocf.patch -+ -+ for 2.6.23 (and later), find the kernel patch specific (or nearest) -+ to your kernel versions and then: -+ -+ cd linux-2.6.NN/crypto -+ tar xvzf ocf-linux.tar.gz -+ cd .. -+ patch -p1 < crypto/ocf/patches/linux-2.6.NN-ocf.patch -+ -+ It should be easy to take this patch and apply it to other more -+ recent versions of the kernels. The same patches should also work -+ relatively easily on kernels as old as 2.6.11 and 2.4.18. -+ -+ * under 2.4 if you are on a non-x86 platform, you may need to: -+ -+ cp linux-2.X.x/include/asm-i386/kmap_types.h linux-2.X.x/include/asm-YYY -+ -+ so that you can build the kernel crypto support needed for the cryptosoft -+ driver. -+ -+ * For simplicity you should enable all the crypto support in your kernel -+ except for the test driver. Likewise for the OCF options. Do not -+ enable OCF crypto drivers for HW that you do not have (for example -+ ixp4xx will not compile on non-Xscale systems). -+ -+ * make sure that cryptodev.h (from ocf-linux.tar.gz) is installed as -+ crypto/cryptodev.h in an include directory that is used for building -+ applications for your platform. For example on a host system that -+ might be: -+ -+ /usr/include/crypto/cryptodev.h -+ -+ * patch your openssl-0.9.8n code with the openssl-0.9.8n.patch. -+ (NOTE: there is no longer a need to patch ssh). The patch is against: -+ openssl-0_9_8e -+ -+ If you need a patch for an older version of openssl, you should look -+ to older OCF releases. This patch is unlikely to work on older -+ openssl versions. -+ -+ openssl-0.9.8n.patch -+ - enables --with-cryptodev for non BSD systems -+ - adds -cpu option to openssl speed for calculating CPU load -+ under linux -+ - fixes null pointer in openssl speed multi thread output. -+ - fixes test keys to work with linux crypto's more stringent -+ key checking. -+ - adds MD5/SHA acceleration (Ronen Shitrit), only enabled -+ with the --with-cryptodev-digests option -+ - fixes bug in engine code caching. -+ -+ * build crypto-tools-XXXXXXXX.tar.gz if you want to try some of the BSD -+ tools for testing OCF (ie., cryptotest). -+ -+How to load the OCF drivers -+--------------------------- -+ -+ First insert the base modules: -+ -+ insmod ocf -+ insmod cryptodev -+ -+ You can then install the software OCF driver with: -+ -+ insmod cryptosoft -+ -+ and one or more of the OCF HW drivers with: -+ -+ insmod safe -+ insmod hifn7751 -+ insmod ixp4xx -+ ... -+ -+ all the drivers take a debug option to enable verbose debug so that -+ you can see what is going on. For debug you load them as: -+ -+ insmod ocf crypto_debug=1 -+ insmod cryptodev cryptodev_debug=1 -+ insmod cryptosoft swcr_debug=1 -+ -+ You may load more than one OCF crypto driver but then there is no guarantee -+ as to which will be used. -+ -+ You can also enable debug at run time on 2.6 systems with the following: -+ -+ echo 1 > /sys/module/ocf/parameters/crypto_debug -+ echo 1 > /sys/module/cryptodev/parameters/cryptodev_debug -+ echo 1 > /sys/module/cryptosoft/parameters/swcr_debug -+ echo 1 > /sys/module/hifn7751/parameters/hifn_debug -+ echo 1 > /sys/module/safe/parameters/safe_debug -+ echo 1 > /sys/module/ixp4xx/parameters/ixp_debug -+ ... -+ -+Testing the OCF support -+----------------------- -+ -+ run "cryptotest", it should do a short test for a couple of -+ des packets. If it does everything is working. -+ -+ If this works, then ssh will use the driver when invoked as: -+ -+ ssh -c 3des username@host -+ -+ to see for sure that it is operating, enable debug as defined above. -+ -+ To get a better idea of performance run: -+ -+ cryptotest 100 4096 -+ -+ There are more options to cryptotest, see the help. -+ -+ It is also possible to use openssl to test the speed of the crypto -+ drivers. -+ -+ openssl speed -evp des -engine cryptodev -elapsed -+ openssl speed -evp des3 -engine cryptodev -elapsed -+ openssl speed -evp aes128 -engine cryptodev -elapsed -+ -+ and multiple threads (10) with: -+ -+ openssl speed -evp des -engine cryptodev -elapsed -multi 10 -+ openssl speed -evp des3 -engine cryptodev -elapsed -multi 10 -+ openssl speed -evp aes128 -engine cryptodev -elapsed -multi 10 -+ -+ for public key testing you can try: -+ -+ cryptokeytest -+ openssl speed -engine cryptodev rsa -elapsed -+ openssl speed -engine cryptodev dsa -elapsed -+ -+David McCullough -+david_mccullough@mcafee.com -diff -Nur linux-2.6.39.orig/crypto/ocf/c7108/Makefile linux-2.6.39/crypto/ocf/c7108/Makefile ---- linux-2.6.39.orig/crypto/ocf/c7108/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/c7108/Makefile 2011-08-01 14:38:18.000000000 +0200 -@@ -0,0 +1,12 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+obj-$(CONFIG_OCF_C7108) += aes-7108.o -+ -+obj ?= . -+EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/c7108/aes-7108.c linux-2.6.39/crypto/ocf/c7108/aes-7108.c ---- linux-2.6.39.orig/crypto/ocf/c7108/aes-7108.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/c7108/aes-7108.c 2011-08-01 14:38:18.000000000 +0200 -@@ -0,0 +1,839 @@ -+/* -+ * Copyright (C) 2006 Micronas USA -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored in part by the Defense Advanced Research Projects -+ * Agency (DARPA) and Air Force Research Laboratory, Air Force -+ * Materiel Command, USAF, under agreement number F30602-01-2-0537. -+ * -+ */ -+ -+//#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+//#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* Runtime mode */ -+static int c7108_crypto_mode = C7108_AES_CTRL_MODE_CTR; -+//static int c7108_crypto_mode = C7108_AES_CTRL_MODE_CBC; -+ -+static int32_t c7108_id = -1; -+static struct cipher_7108 **c7108_sessions = NULL; -+static u_int32_t c7108_sesnum = 0; -+static unsigned long iobar; -+ -+/* Crypto entry points */ -+static int c7108_process(void *, struct cryptop *, int); -+static int c7108_newsession(void *, u_int32_t *, struct cryptoini *); -+static int c7108_freesession(void *, u_int64_t); -+ -+/* Globals */ -+static int debug = 0; -+static spinlock_t csr_mutex; -+ -+/* Generic controller-based lock */ -+#define AES_LOCK()\ -+ spin_lock(&csr_mutex) -+#define AES_UNLOCK()\ -+ spin_unlock(&csr_mutex) -+ -+/* 7108 AES register access */ -+#define c7108_reg_wr8(a,d) iowrite8(d, (void*)(iobar+(a))) -+#define c7108_reg_wr16(a,d) iowrite16(d, (void*)(iobar+(a))) -+#define c7108_reg_wr32(a,d) iowrite32(d, (void*)(iobar+(a))) -+#define c7108_reg_rd8(a) ioread8((void*)(iobar+(a))) -+#define c7108_reg_rd16(a) ioread16((void*)(iobar+(a))) -+#define c7108_reg_rd32(a) ioread32((void*)(iobar+(a))) -+ -+static int -+c7108_xlate_key(int klen, u8* k8ptr, u32* k32ptr) -+{ -+ int i, nw=0; -+ nw = ((klen >= 256) ? 8 : (klen >= 192) ? 6 : 4); -+ for ( i = 0; i < nw; i++) { -+ k32ptr[i] = (k8ptr[i+3] << 24) | (k8ptr[i+2] << 16) | -+ (k8ptr[i+1] << 8) | k8ptr[i]; -+ -+ } -+ return 0; -+} -+ -+static int -+c7108_cache_key(int klen, u32* k32ptr, u8* k8ptr) -+{ -+ int i, nb=0; -+ u8* ptr = (u8*)k32ptr; -+ nb = ((klen >= 256) ? 32 : (klen >= 192) ? 24 : 16); -+ for ( i = 0; i < nb; i++) -+ k8ptr[i] = ptr[i]; -+ return 0; -+} -+ -+static int -+c7108_aes_setup_dma(u32 src, u32 dst, u32 len) -+{ -+ if (len < 16) { -+ printk("len < 16\n"); -+ return -10; -+ } -+ if (len % 16) { -+ printk("len not multiple of 16\n"); -+ return -11; -+ } -+ c7108_reg_wr16(C7108_AES_DMA_SRC0_LO, (u16) src); -+ c7108_reg_wr16(C7108_AES_DMA_SRC0_HI, (u16)((src & 0xffff0000) >> 16)); -+ c7108_reg_wr16(C7108_AES_DMA_DST0_LO, (u16) dst); -+ c7108_reg_wr16(C7108_AES_DMA_DST0_HI, (u16)((dst & 0xffff0000) >> 16)); -+ c7108_reg_wr16(C7108_AES_DMA_LEN, (u16) ((len / 16) - 1)); -+ -+ return 0; -+} -+ -+static int -+c7108_aes_set_hw_iv(u8 iv[16]) -+{ -+ c7108_reg_wr16(C7108_AES_IV0_LO, (u16) ((iv[1] << 8) | iv[0])); -+ c7108_reg_wr16(C7108_AES_IV0_HI, (u16) ((iv[3] << 8) | iv[2])); -+ c7108_reg_wr16(C7108_AES_IV1_LO, (u16) ((iv[5] << 8) | iv[4])); -+ c7108_reg_wr16(C7108_AES_IV1_HI, (u16) ((iv[7] << 8) | iv[6])); -+ c7108_reg_wr16(C7108_AES_IV2_LO, (u16) ((iv[9] << 8) | iv[8])); -+ c7108_reg_wr16(C7108_AES_IV2_HI, (u16) ((iv[11] << 8) | iv[10])); -+ c7108_reg_wr16(C7108_AES_IV3_LO, (u16) ((iv[13] << 8) | iv[12])); -+ c7108_reg_wr16(C7108_AES_IV3_HI, (u16) ((iv[15] << 8) | iv[14])); -+ -+ return 0; -+} -+ -+static void -+c7108_aes_read_dkey(u32 * dkey) -+{ -+ dkey[0] = (c7108_reg_rd16(C7108_AES_EKEY0_HI) << 16) | -+ c7108_reg_rd16(C7108_AES_EKEY0_LO); -+ dkey[1] = (c7108_reg_rd16(C7108_AES_EKEY1_HI) << 16) | -+ c7108_reg_rd16(C7108_AES_EKEY1_LO); -+ dkey[2] = (c7108_reg_rd16(C7108_AES_EKEY2_HI) << 16) | -+ c7108_reg_rd16(C7108_AES_EKEY2_LO); -+ dkey[3] = (c7108_reg_rd16(C7108_AES_EKEY3_HI) << 16) | -+ c7108_reg_rd16(C7108_AES_EKEY3_LO); -+ dkey[4] = (c7108_reg_rd16(C7108_AES_EKEY4_HI) << 16) | -+ c7108_reg_rd16(C7108_AES_EKEY4_LO); -+ dkey[5] = (c7108_reg_rd16(C7108_AES_EKEY5_HI) << 16) | -+ c7108_reg_rd16(C7108_AES_EKEY5_LO); -+ dkey[6] = (c7108_reg_rd16(C7108_AES_EKEY6_HI) << 16) | -+ c7108_reg_rd16(C7108_AES_EKEY6_LO); -+ dkey[7] = (c7108_reg_rd16(C7108_AES_EKEY7_HI) << 16) | -+ c7108_reg_rd16(C7108_AES_EKEY7_LO); -+} -+ -+static int -+c7108_aes_cipher(int op, -+ u32 dst, -+ u32 src, -+ u32 len, -+ int klen, -+ u16 mode, -+ u32 key[8], -+ u8 iv[16]) -+{ -+ int rv = 0, cnt=0; -+ u16 ctrl = 0, stat = 0; -+ -+ AES_LOCK(); -+ -+ /* Setup key length */ -+ if (klen == 128) { -+ ctrl |= C7108_AES_KEY_LEN_128; -+ } else if (klen == 192) { -+ ctrl |= C7108_AES_KEY_LEN_192; -+ } else if (klen == 256) { -+ ctrl |= C7108_AES_KEY_LEN_256; -+ } else { -+ AES_UNLOCK(); -+ return -3; -+ } -+ -+ /* Check opcode */ -+ if (C7108_AES_ENCRYPT == op) { -+ ctrl |= C7108_AES_ENCRYPT; -+ } else if (C7108_AES_DECRYPT == op) { -+ ctrl |= C7108_AES_DECRYPT; -+ } else { -+ AES_UNLOCK(); -+ return -4; -+ } -+ -+ /* check mode */ -+ if ( (mode != C7108_AES_CTRL_MODE_CBC) && -+ (mode != C7108_AES_CTRL_MODE_CFB) && -+ (mode != C7108_AES_CTRL_MODE_OFB) && -+ (mode != C7108_AES_CTRL_MODE_CTR) && -+ (mode != C7108_AES_CTRL_MODE_ECB) ) { -+ AES_UNLOCK(); -+ return -5; -+ } -+ -+ /* Now set mode */ -+ ctrl |= mode; -+ -+ /* For CFB, OFB, and CTR, neither backward key -+ * expansion nor key inversion is required. -+ */ -+ if ( (C7108_AES_DECRYPT == op) && -+ (C7108_AES_CTRL_MODE_CBC == mode || -+ C7108_AES_CTRL_MODE_ECB == mode ) ){ -+ -+ /* Program Key */ -+ c7108_reg_wr16(C7108_AES_KEY0_LO, (u16) key[4]); -+ c7108_reg_wr16(C7108_AES_KEY0_HI, (u16) (key[4] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY1_LO, (u16) key[5]); -+ c7108_reg_wr16(C7108_AES_KEY1_HI, (u16) (key[5] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY2_LO, (u16) key[6]); -+ c7108_reg_wr16(C7108_AES_KEY2_HI, (u16) (key[6] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY3_LO, (u16) key[7]); -+ c7108_reg_wr16(C7108_AES_KEY3_HI, (u16) (key[7] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY6_LO, (u16) key[2]); -+ c7108_reg_wr16(C7108_AES_KEY6_HI, (u16) (key[2] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY7_LO, (u16) key[3]); -+ c7108_reg_wr16(C7108_AES_KEY7_HI, (u16) (key[3] >> 16)); -+ -+ -+ if (192 == klen) { -+ c7108_reg_wr16(C7108_AES_KEY4_LO, (u16) key[7]); -+ c7108_reg_wr16(C7108_AES_KEY4_HI, (u16) (key[7] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY5_LO, (u16) key[7]); -+ c7108_reg_wr16(C7108_AES_KEY5_HI, (u16) (key[7] >> 16)); -+ -+ } else if (256 == klen) { -+ /* 256 */ -+ c7108_reg_wr16(C7108_AES_KEY4_LO, (u16) key[0]); -+ c7108_reg_wr16(C7108_AES_KEY4_HI, (u16) (key[0] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY5_LO, (u16) key[1]); -+ c7108_reg_wr16(C7108_AES_KEY5_HI, (u16) (key[1] >> 16)); -+ -+ } -+ -+ } else { -+ /* Program Key */ -+ c7108_reg_wr16(C7108_AES_KEY0_LO, (u16) key[0]); -+ c7108_reg_wr16(C7108_AES_KEY0_HI, (u16) (key[0] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY1_LO, (u16) key[1]); -+ c7108_reg_wr16(C7108_AES_KEY1_HI, (u16) (key[1] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY2_LO, (u16) key[2]); -+ c7108_reg_wr16(C7108_AES_KEY2_HI, (u16) (key[2] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY3_LO, (u16) key[3]); -+ c7108_reg_wr16(C7108_AES_KEY3_HI, (u16) (key[3] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY4_LO, (u16) key[4]); -+ c7108_reg_wr16(C7108_AES_KEY4_HI, (u16) (key[4] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY5_LO, (u16) key[5]); -+ c7108_reg_wr16(C7108_AES_KEY5_HI, (u16) (key[5] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY6_LO, (u16) key[6]); -+ c7108_reg_wr16(C7108_AES_KEY6_HI, (u16) (key[6] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY7_LO, (u16) key[7]); -+ c7108_reg_wr16(C7108_AES_KEY7_HI, (u16) (key[7] >> 16)); -+ -+ } -+ -+ /* Set IV always */ -+ c7108_aes_set_hw_iv(iv); -+ -+ /* Program DMA addresses */ -+ if ((rv = c7108_aes_setup_dma(src, dst, len)) < 0) { -+ AES_UNLOCK(); -+ return rv; -+ } -+ -+ -+ /* Start AES cipher */ -+ c7108_reg_wr16(C7108_AES_CTRL, ctrl | C7108_AES_GO); -+ -+ //printk("Ctrl: 0x%x\n", ctrl | C7108_AES_GO); -+ do { -+ /* TODO: interrupt mode */ -+ // printk("aes_stat=0x%x\n", stat); -+ //udelay(100); -+ } while ((cnt++ < 1000000) && -+ !((stat=c7108_reg_rd16(C7108_AES_CTRL))&C7108_AES_OP_DONE)); -+ -+ -+ if ((mode == C7108_AES_CTRL_MODE_ECB)|| -+ (mode == C7108_AES_CTRL_MODE_CBC)) { -+ /* Save out key when the lock is held ... */ -+ c7108_aes_read_dkey(key); -+ } -+ -+ AES_UNLOCK(); -+ return 0; -+ -+} -+ -+/* -+ * Generate a new crypto device session. -+ */ -+static int -+c7108_newsession(void *arg, u_int32_t *sid, struct cryptoini *cri) -+{ -+ struct cipher_7108 **swd; -+ u_int32_t i; -+ char *algo; -+ int mode, xfm_type; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid == NULL || cri == NULL) { -+ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ if (c7108_sessions) { -+ for (i = 1; i < c7108_sesnum; i++) -+ if (c7108_sessions[i] == NULL) -+ break; -+ } else -+ i = 1; /* NB: to silence compiler warning */ -+ -+ if (c7108_sessions == NULL || i == c7108_sesnum) { -+ if (c7108_sessions == NULL) { -+ i = 1; /* We leave c7108_sessions[0] empty */ -+ c7108_sesnum = CRYPTO_SW_SESSIONS; -+ } else -+ c7108_sesnum *= 2; -+ -+ swd = kmalloc(c7108_sesnum * sizeof(struct cipher_7108 *), -+ GFP_ATOMIC); -+ if (swd == NULL) { -+ /* Reset session number */ -+ if (c7108_sesnum == CRYPTO_SW_SESSIONS) -+ c7108_sesnum = 0; -+ else -+ c7108_sesnum /= 2; -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memset(swd, 0, c7108_sesnum * sizeof(struct cipher_7108 *)); -+ -+ /* Copy existing sessions */ -+ if (c7108_sessions) { -+ memcpy(swd, c7108_sessions, -+ (c7108_sesnum / 2) * sizeof(struct cipher_7108 *)); -+ kfree(c7108_sessions); -+ } -+ -+ c7108_sessions = swd; -+ -+ } -+ -+ swd = &c7108_sessions[i]; -+ *sid = i; -+ -+ while (cri) { -+ *swd = (struct cipher_7108 *) -+ kmalloc(sizeof(struct cipher_7108), GFP_ATOMIC); -+ if (*swd == NULL) { -+ c7108_freesession(NULL, i); -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memset(*swd, 0, sizeof(struct cipher_7108)); -+ -+ algo = NULL; -+ mode = 0; -+ xfm_type = HW_TYPE_CIPHER; -+ -+ switch (cri->cri_alg) { -+ -+ case CRYPTO_AES_CBC: -+ algo = "aes"; -+ mode = CRYPTO_TFM_MODE_CBC; -+ c7108_crypto_mode = C7108_AES_CTRL_MODE_CBC; -+ break; -+#if 0 -+ case CRYPTO_AES_CTR: -+ algo = "aes_ctr"; -+ mode = CRYPTO_TFM_MODE_CBC; -+ c7108_crypto_mode = C7108_AES_CTRL_MODE_CTR; -+ break; -+ case CRYPTO_AES_ECB: -+ algo = "aes_ecb"; -+ mode = CRYPTO_TFM_MODE_CBC; -+ c7108_crypto_mode = C7108_AES_CTRL_MODE_ECB; -+ break; -+ case CRYPTO_AES_OFB: -+ algo = "aes_ofb"; -+ mode = CRYPTO_TFM_MODE_CBC; -+ c7108_crypto_mode = C7108_AES_CTRL_MODE_OFB; -+ break; -+ case CRYPTO_AES_CFB: -+ algo = "aes_cfb"; -+ mode = CRYPTO_TFM_MODE_CBC; -+ c7108_crypto_mode = C7108_AES_CTRL_MODE_CFB; -+ break; -+#endif -+ default: -+ printk("unsupported crypto algorithm: %d\n", -+ cri->cri_alg); -+ return -EINVAL; -+ break; -+ } -+ -+ -+ if (!algo || !*algo) { -+ printk("cypher_7108_crypto: Unknown algo 0x%x\n", -+ cri->cri_alg); -+ c7108_freesession(NULL, i); -+ return EINVAL; -+ } -+ -+ if (xfm_type == HW_TYPE_CIPHER) { -+ if (debug) { -+ dprintk("%s key:", __FUNCTION__); -+ for (i = 0; i < (cri->cri_klen + 7) / 8; i++) -+ dprintk("%s0x%02x", (i % 8) ? " " : "\n ", -+ cri->cri_key[i]); -+ dprintk("\n"); -+ } -+ -+ } else if (xfm_type == SW_TYPE_HMAC || -+ xfm_type == SW_TYPE_HASH) { -+ printk("cypher_7108_crypto: HMAC unsupported!\n"); -+ return -EINVAL; -+ c7108_freesession(NULL, i); -+ } else { -+ printk("cypher_7108_crypto: " -+ "Unhandled xfm_type %d\n", xfm_type); -+ c7108_freesession(NULL, i); -+ return EINVAL; -+ } -+ -+ (*swd)->cri_alg = cri->cri_alg; -+ (*swd)->xfm_type = xfm_type; -+ -+ cri = cri->cri_next; -+ swd = &((*swd)->next); -+ } -+ return 0; -+} -+ -+/* -+ * Free a session. -+ */ -+static int -+c7108_freesession(void *arg, u_int64_t tid) -+{ -+ struct cipher_7108 *swd; -+ u_int32_t sid = CRYPTO_SESID2LID(tid); -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid > c7108_sesnum || c7108_sessions == NULL || -+ c7108_sessions[sid] == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return(EINVAL); -+ } -+ -+ /* Silently accept and return */ -+ if (sid == 0) -+ return(0); -+ -+ while ((swd = c7108_sessions[sid]) != NULL) { -+ c7108_sessions[sid] = swd->next; -+ kfree(swd); -+ } -+ return 0; -+} -+ -+/* -+ * Process a hardware request. -+ */ -+static int -+c7108_process(void *arg, struct cryptop *crp, int hint) -+{ -+ struct cryptodesc *crd; -+ struct cipher_7108 *sw; -+ u_int32_t lid; -+ int type; -+ u32 hwkey[8]; -+ -+#define SCATTERLIST_MAX 16 -+ struct scatterlist sg[SCATTERLIST_MAX]; -+ int sg_num, sg_len, skip; -+ struct sk_buff *skb = NULL; -+ struct uio *uiop = NULL; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ /* Sanity check */ -+ if (crp == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ crp->crp_etype = 0; -+ -+ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ lid = crp->crp_sid & 0xffffffff; -+ if (lid >= c7108_sesnum || lid == 0 || c7108_sessions == NULL || -+ c7108_sessions[lid] == NULL) { -+ crp->crp_etype = ENOENT; -+ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); -+ goto done; -+ } -+ -+ /* -+ * do some error checking outside of the loop for SKB and IOV -+ * processing this leaves us with valid skb or uiop pointers -+ * for later -+ */ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ skb = (struct sk_buff *) crp->crp_buf; -+ if (skb_shinfo(skb)->nr_frags >= SCATTERLIST_MAX) { -+ printk("%s,%d: %d nr_frags > SCATTERLIST_MAX", -+ __FILE__, __LINE__, -+ skb_shinfo(skb)->nr_frags); -+ goto done; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ uiop = (struct uio *) crp->crp_buf; -+ if (uiop->uio_iovcnt > SCATTERLIST_MAX) { -+ printk("%s,%d: %d uio_iovcnt > SCATTERLIST_MAX", -+ __FILE__, __LINE__, -+ uiop->uio_iovcnt); -+ goto done; -+ } -+ } -+ -+ /* Go through crypto descriptors, processing as we go */ -+ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { -+ /* -+ * Find the crypto context. -+ * -+ * XXX Note that the logic here prevents us from having -+ * XXX the same algorithm multiple times in a session -+ * XXX (or rather, we can but it won't give us the right -+ * XXX results). To do that, we'd need some way of differentiating -+ * XXX between the various instances of an algorithm (so we can -+ * XXX locate the correct crypto context). -+ */ -+ for (sw = c7108_sessions[lid]; -+ sw && sw->cri_alg != crd->crd_alg; -+ sw = sw->next) -+ ; -+ -+ /* No such context ? */ -+ if (sw == NULL) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ goto done; -+ } -+ -+ skip = crd->crd_skip; -+ -+ /* -+ * setup the SG list skip from the start of the buffer -+ */ -+ memset(sg, 0, sizeof(sg)); -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ int i, len; -+ type = CRYPTO_BUF_SKBUF; -+ -+ sg_num = 0; -+ sg_len = 0; -+ -+ if (skip < skb_headlen(skb)) { -+ //sg[sg_num].page = virt_to_page(skb->data + skip); -+ //sg[sg_num].offset = offset_in_page(skb->data + skip); -+ len = skb_headlen(skb) - skip; -+ if (len + sg_len > crd->crd_len) -+ len = crd->crd_len - sg_len; -+ //sg[sg_num].length = len; -+ sg_set_page(&sg[sg_num], virt_to_page(skb->data + skip), len, offset_in_page(skb->data + skip)); -+ sg_len += sg[sg_num].length; -+ sg_num++; -+ skip = 0; -+ } else -+ skip -= skb_headlen(skb); -+ -+ for (i = 0; sg_len < crd->crd_len && -+ i < skb_shinfo(skb)->nr_frags && -+ sg_num < SCATTERLIST_MAX; i++) { -+ if (skip < skb_shinfo(skb)->frags[i].size) { -+ //sg[sg_num].page = skb_shinfo(skb)->frags[i].page; -+ //sg[sg_num].offset = skb_shinfo(skb)->frags[i].page_offset + skip; -+ len = skb_shinfo(skb)->frags[i].size - skip; -+ if (len + sg_len > crd->crd_len) -+ len = crd->crd_len - sg_len; -+ //sg[sg_num].length = len; -+ sg_set_page(&sg[sg_num], skb_shinfo(skb)->frags[i].page, len, skb_shinfo(skb)->frags[i].page_offset + skip); -+ sg_len += sg[sg_num].length; -+ sg_num++; -+ skip = 0; -+ } else -+ skip -= skb_shinfo(skb)->frags[i].size; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ int len; -+ type = CRYPTO_BUF_IOV; -+ sg_len = 0; -+ for (sg_num = 0; sg_len < crd->crd_len && -+ sg_num < uiop->uio_iovcnt && -+ sg_num < SCATTERLIST_MAX; sg_num++) { -+ if (skip < uiop->uio_iov[sg_num].iov_len) { -+ //sg[sg_num].page = virt_to_page(uiop->uio_iov[sg_num].iov_base+skip); -+ //sg[sg_num].offset = offset_in_page(uiop->uio_iov[sg_num].iov_base+skip); -+ len = uiop->uio_iov[sg_num].iov_len - skip; -+ if (len + sg_len > crd->crd_len) -+ len = crd->crd_len - sg_len; -+ //sg[sg_num].length = len; -+ sg_set_page(&sg[sg_num], virt_to_page(uiop->uio_iov[sg_num].iov_base+skip), len, offset_in_page(uiop->uio_iov[sg_num].iov_base+skip)); -+ sg_len += sg[sg_num].length; -+ skip = 0; -+ } else -+ skip -= uiop->uio_iov[sg_num].iov_len; -+ } -+ } else { -+ type = CRYPTO_BUF_CONTIG; -+ //sg[0].page = virt_to_page(crp->crp_buf + skip); -+ //sg[0].offset = offset_in_page(crp->crp_buf + skip); -+ sg_len = (crp->crp_ilen - skip); -+ if (sg_len > crd->crd_len) -+ sg_len = crd->crd_len; -+ //sg[0].length = sg_len; -+ sg_set_page(&sg[0], virt_to_page(crp->crp_buf + skip), sg_len, offset_in_page(crp->crp_buf + skip)); -+ sg_num = 1; -+ } -+ -+ -+ switch (sw->xfm_type) { -+ -+ case HW_TYPE_CIPHER: { -+ -+ unsigned char iv[64]; -+ unsigned char *ivp = iv; -+ int i; -+ int ivsize = 16; /* fixed for AES */ -+ int blocksize = 16; /* fixed for AES */ -+ -+ if (sg_len < blocksize) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: EINVAL len %d < %d\n", -+ __FILE__, __LINE__, -+ sg_len, -+ blocksize); -+ goto done; -+ } -+ -+ if (ivsize > sizeof(iv)) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ goto done; -+ } -+ -+ if (crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ -+ -+ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { -+ ivp = crd->crd_iv; -+ } else { -+ get_random_bytes(ivp, ivsize); -+ } -+ /* -+ * do we have to copy the IV back to the buffer ? -+ */ -+ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { -+ crypto_copyback(crp->crp_buf, -+ crd->crd_inject, -+ ivsize, -+ (caddr_t)ivp); -+ } -+ -+ c7108_xlate_key(crd->crd_klen, -+ (u8*)crd->crd_key, (u32*)hwkey); -+ -+ /* Encrypt SG list */ -+ for (i = 0; i < sg_num; i++) { -+ sg[i].dma_address = -+ dma_map_single(NULL, -+ kmap(sg_page(&sg[i])) + sg[i].offset, sg_len, DMA_BIDIRECTIONAL); -+#if 0 -+ printk("sg[%d]:0x%08x, off 0x%08x " -+ "kmap 0x%08x phys 0x%08x\n", -+ i, sg[i].page, sg[i].offset, -+ kmap(sg[i].page) + sg[i].offset, -+ sg[i].dma_address); -+#endif -+ c7108_aes_cipher(C7108_AES_ENCRYPT, -+ sg[i].dma_address, -+ sg[i].dma_address, -+ sg_len, -+ crd->crd_klen, -+ c7108_crypto_mode, -+ hwkey, -+ ivp); -+ -+ if ((c7108_crypto_mode == C7108_AES_CTRL_MODE_CBC)|| -+ (c7108_crypto_mode == C7108_AES_CTRL_MODE_ECB)) { -+ /* Read back expanded key and cache it in key -+ * context. -+ * NOTE: for ECB/CBC modes only (not CTR, CFB, OFB) -+ * where you set the key once. -+ */ -+ c7108_cache_key(crd->crd_klen, -+ (u32*)hwkey, (u8*)crd->crd_key); -+#if 0 -+ printk("%s expanded key:", __FUNCTION__); -+ for (i = 0; i < (crd->crd_klen + 7) / 8; i++) -+ printk("%s0x%02x", (i % 8) ? " " : "\n ", -+ crd->crd_key[i]); -+ printk("\n"); -+#endif -+ } -+ } -+ } -+ else { /*decrypt */ -+ -+ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { -+ ivp = crd->crd_iv; -+ } else { -+ crypto_copydata(crp->crp_buf, crd->crd_inject, -+ ivsize, (caddr_t)ivp); -+ } -+ -+ c7108_xlate_key(crd->crd_klen, -+ (u8*)crd->crd_key, (u32*)hwkey); -+ -+ /* Decrypt SG list */ -+ for (i = 0; i < sg_num; i++) { -+ sg[i].dma_address = -+ dma_map_single(NULL, -+ kmap(sg_page(&sg[i])) + sg[i].offset, -+ sg_len, DMA_BIDIRECTIONAL); -+ -+#if 0 -+ printk("sg[%d]:0x%08x, off 0x%08x " -+ "kmap 0x%08x phys 0x%08x\n", -+ i, sg[i].page, sg[i].offset, -+ kmap(sg[i].page) + sg[i].offset, -+ sg[i].dma_address); -+#endif -+ c7108_aes_cipher(C7108_AES_DECRYPT, -+ sg[i].dma_address, -+ sg[i].dma_address, -+ sg_len, -+ crd->crd_klen, -+ c7108_crypto_mode, -+ hwkey, -+ ivp); -+ } -+ } -+ } break; -+ case SW_TYPE_HMAC: -+ case SW_TYPE_HASH: -+ crp->crp_etype = EINVAL; -+ goto done; -+ break; -+ -+ case SW_TYPE_COMP: -+ crp->crp_etype = EINVAL; -+ goto done; -+ break; -+ -+ default: -+ /* Unknown/unsupported algorithm */ -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ } -+ -+done: -+ crypto_done(crp); -+ return 0; -+} -+ -+static struct { -+ softc_device_decl sc_dev; -+} a7108dev; -+ -+static device_method_t a7108_methods = { -+/* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, c7108_newsession), -+ DEVMETHOD(cryptodev_freesession, c7108_freesession), -+ DEVMETHOD(cryptodev_process, c7108_process), -+ DEVMETHOD(cryptodev_kprocess, NULL) -+}; -+ -+static int -+cypher_7108_crypto_init(void) -+{ -+ dprintk("%s(%p)\n", __FUNCTION__, cypher_7108_crypto_init); -+ -+ iobar = (unsigned long)ioremap(CCU_AES_REG_BASE, 0x4000); -+ printk("7108: AES @ 0x%08x (0x%08x phys) %s mode\n", -+ iobar, CCU_AES_REG_BASE, -+ c7108_crypto_mode & C7108_AES_CTRL_MODE_CBC ? "CBC" : -+ c7108_crypto_mode & C7108_AES_CTRL_MODE_ECB ? "ECB" : -+ c7108_crypto_mode & C7108_AES_CTRL_MODE_CTR ? "CTR" : -+ c7108_crypto_mode & C7108_AES_CTRL_MODE_CFB ? "CFB" : -+ c7108_crypto_mode & C7108_AES_CTRL_MODE_OFB ? "OFB" : "???"); -+ csr_mutex = SPIN_LOCK_UNLOCKED; -+ -+ memset(&a7108dev, 0, sizeof(a7108dev)); -+ softc_device_init(&a7108dev, "aes7108", 0, a7108_methods); -+ -+ c7108_id = crypto_get_driverid(softc_get_device(&a7108dev), CRYPTOCAP_F_HARDWARE); -+ if (c7108_id < 0) -+ panic("7108: crypto device cannot initialize!"); -+ -+// crypto_register(c7108_id, CRYPTO_AES_CBC, 0, 0, c7108_newsession, c7108_freesession, c7108_process, NULL); -+ crypto_register(c7108_id, CRYPTO_AES_CBC, 0, 0); -+ -+ return(0); -+} -+ -+static void -+cypher_7108_crypto_exit(void) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ crypto_unregister_all(c7108_id); -+ c7108_id = -1; -+} -+ -+module_init(cypher_7108_crypto_init); -+module_exit(cypher_7108_crypto_exit); -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_DESCRIPTION("Cypher 7108 Crypto (OCF module for kernel crypto)"); -diff -Nur linux-2.6.39.orig/crypto/ocf/c7108/aes-7108.h linux-2.6.39/crypto/ocf/c7108/aes-7108.h ---- linux-2.6.39.orig/crypto/ocf/c7108/aes-7108.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/c7108/aes-7108.h 2011-08-01 14:38:18.000000000 +0200 -@@ -0,0 +1,134 @@ -+/* -+ * Copyright (C) 2006 Micronas USA -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored in part by the Defense Advanced Research Projects -+ * Agency (DARPA) and Air Force Research Laboratory, Air Force -+ * Materiel Command, USAF, under agreement number F30602-01-2-0537. -+ * -+ */ -+ -+#ifndef __AES_7108_H__ -+#define __AES_7108_H__ -+ -+/* Cypher 7108 AES Controller Hardware */ -+#define CCU_REG_BASE 0x1b500000 -+#define CCU_AES_REG_BASE (CCU_REG_BASE + 0x100) -+#define C7108_AES_KEY0_LO (0x0000) -+#define C7108_AES_KEY0_HI (0x0004) -+#define C7108_AES_KEY1_LO (0x0008) -+#define C7108_AES_KEY1_HI (0x000c) -+#define C7108_AES_KEY2_LO (0x0010) -+#define C7108_AES_KEY2_HI (0x0014) -+#define C7108_AES_KEY3_LO (0x0018) -+#define C7108_AES_KEY3_HI (0x001c) -+#define C7108_AES_KEY4_LO (0x0020) -+#define C7108_AES_KEY4_HI (0x0024) -+#define C7108_AES_KEY5_LO (0x0028) -+#define C7108_AES_KEY5_HI (0x002c) -+#define C7108_AES_KEY6_LO (0x0030) -+#define C7108_AES_KEY6_HI (0x0034) -+#define C7108_AES_KEY7_LO (0x0038) -+#define C7108_AES_KEY7_HI (0x003c) -+#define C7108_AES_IV0_LO (0x0040) -+#define C7108_AES_IV0_HI (0x0044) -+#define C7108_AES_IV1_LO (0x0048) -+#define C7108_AES_IV1_HI (0x004c) -+#define C7108_AES_IV2_LO (0x0050) -+#define C7108_AES_IV2_HI (0x0054) -+#define C7108_AES_IV3_LO (0x0058) -+#define C7108_AES_IV3_HI (0x005c) -+ -+#define C7108_AES_DMA_SRC0_LO (0x0068) /* Bits 0:15 */ -+#define C7108_AES_DMA_SRC0_HI (0x006c) /* Bits 27:16 */ -+#define C7108_AES_DMA_DST0_LO (0x0070) /* Bits 0:15 */ -+#define C7108_AES_DMA_DST0_HI (0x0074) /* Bits 27:16 */ -+#define C7108_AES_DMA_LEN (0x0078) /*Bytes:(Count+1)x16 */ -+ -+/* AES/Copy engine control register */ -+#define C7108_AES_CTRL (0x007c) /* AES control */ -+#define C7108_AES_CTRL_RS (1<<0) /* Which set of src/dst to use */ -+ -+/* AES Cipher mode, controlled by setting Bits 2:0 */ -+#define C7108_AES_CTRL_MODE_CBC 0 -+#define C7108_AES_CTRL_MODE_CFB (1<<0) -+#define C7108_AES_CTRL_MODE_OFB (1<<1) -+#define C7108_AES_CTRL_MODE_CTR ((1<<0)|(1<<1)) -+#define C7108_AES_CTRL_MODE_ECB (1<<2) -+ -+/* AES Key length , Bits 5:4 */ -+#define C7108_AES_KEY_LEN_128 0 /* 00 */ -+#define C7108_AES_KEY_LEN_192 (1<<4) /* 01 */ -+#define C7108_AES_KEY_LEN_256 (1<<5) /* 10 */ -+ -+/* AES Operation (crypt/decrypt), Bit 3 */ -+#define C7108_AES_DECRYPT (1<<3) /* Clear for encrypt */ -+#define C7108_AES_ENCRYPT 0 -+#define C7108_AES_INTR (1<<13) /* Set on done trans from 0->1*/ -+#define C7108_AES_GO (1<<14) /* Run */ -+#define C7108_AES_OP_DONE (1<<15) /* Set when complete */ -+ -+ -+/* Expanded key registers */ -+#define C7108_AES_EKEY0_LO (0x0080) -+#define C7108_AES_EKEY0_HI (0x0084) -+#define C7108_AES_EKEY1_LO (0x0088) -+#define C7108_AES_EKEY1_HI (0x008c) -+#define C7108_AES_EKEY2_LO (0x0090) -+#define C7108_AES_EKEY2_HI (0x0094) -+#define C7108_AES_EKEY3_LO (0x0098) -+#define C7108_AES_EKEY3_HI (0x009c) -+#define C7108_AES_EKEY4_LO (0x00a0) -+#define C7108_AES_EKEY4_HI (0x00a4) -+#define C7108_AES_EKEY5_LO (0x00a8) -+#define C7108_AES_EKEY5_HI (0x00ac) -+#define C7108_AES_EKEY6_LO (0x00b0) -+#define C7108_AES_EKEY6_HI (0x00b4) -+#define C7108_AES_EKEY7_LO (0x00b8) -+#define C7108_AES_EKEY7_HI (0x00bc) -+#define C7108_AES_OK (0x00fc) /* Reset: "OK" */ -+ -+#define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK) -+ -+/* Software session entry */ -+ -+#define HW_TYPE_CIPHER 0 -+#define SW_TYPE_HMAC 1 -+#define SW_TYPE_AUTH2 2 -+#define SW_TYPE_HASH 3 -+#define SW_TYPE_COMP 4 -+ -+struct cipher_7108 { -+ int xfm_type; -+ int cri_alg; -+ union { -+ struct { -+ char sw_key[HMAC_BLOCK_LEN]; -+ int sw_klen; -+ int sw_authlen; -+ } hmac; -+ } u; -+ struct cipher_7108 *next; -+}; -+ -+ -+ -+#endif /* __C7108_AES_7108_H__ */ -diff -Nur linux-2.6.39.orig/crypto/ocf/criov.c linux-2.6.39/crypto/ocf/criov.c ---- linux-2.6.39.orig/crypto/ocf/criov.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/criov.c 2011-08-01 14:39:10.000000000 +0200 -@@ -0,0 +1,212 @@ -+/* $OpenBSD: criov.c,v 1.9 2002/01/29 15:48:29 jason Exp $ */ -+ -+/* -+ * Linux port done by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * The license and original author are listed below. -+ * -+ * Copyright (c) 1999 Theo de Raadt -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+__FBSDID("$FreeBSD: src/sys/opencrypto/criov.c,v 1.5 2006/06/04 22:15:13 pjd Exp $"); -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+/* -+ * This macro is only for avoiding code duplication, as we need to skip -+ * given number of bytes in the same way in three functions below. -+ */ -+#define CUIO_SKIP() do { \ -+ KASSERT(off >= 0, ("%s: off %d < 0", __func__, off)); \ -+ KASSERT(len >= 0, ("%s: len %d < 0", __func__, len)); \ -+ while (off > 0) { \ -+ KASSERT(iol >= 0, ("%s: empty in skip", __func__)); \ -+ if (off < iov->iov_len) \ -+ break; \ -+ off -= iov->iov_len; \ -+ iol--; \ -+ iov++; \ -+ } \ -+} while (0) -+ -+void -+cuio_copydata(struct uio* uio, int off, int len, caddr_t cp) -+{ -+ struct iovec *iov = uio->uio_iov; -+ int iol = uio->uio_iovcnt; -+ unsigned count; -+ -+ CUIO_SKIP(); -+ while (len > 0) { -+ KASSERT(iol >= 0, ("%s: empty", __func__)); -+ count = min((int)(iov->iov_len - off), len); -+ memcpy(cp, ((caddr_t)iov->iov_base) + off, count); -+ len -= count; -+ cp += count; -+ off = 0; -+ iol--; -+ iov++; -+ } -+} -+ -+void -+cuio_copyback(struct uio* uio, int off, int len, caddr_t cp) -+{ -+ struct iovec *iov = uio->uio_iov; -+ int iol = uio->uio_iovcnt; -+ unsigned count; -+ -+ CUIO_SKIP(); -+ while (len > 0) { -+ KASSERT(iol >= 0, ("%s: empty", __func__)); -+ count = min((int)(iov->iov_len - off), len); -+ memcpy(((caddr_t)iov->iov_base) + off, cp, count); -+ len -= count; -+ cp += count; -+ off = 0; -+ iol--; -+ iov++; -+ } -+} -+ -+/* -+ * Return a pointer to iov/offset of location in iovec list. -+ */ -+struct iovec * -+cuio_getptr(struct uio *uio, int loc, int *off) -+{ -+ struct iovec *iov = uio->uio_iov; -+ int iol = uio->uio_iovcnt; -+ -+ while (loc >= 0) { -+ /* Normal end of search */ -+ if (loc < iov->iov_len) { -+ *off = loc; -+ return (iov); -+ } -+ -+ loc -= iov->iov_len; -+ if (iol == 0) { -+ if (loc == 0) { -+ /* Point at the end of valid data */ -+ *off = iov->iov_len; -+ return (iov); -+ } else -+ return (NULL); -+ } else { -+ iov++, iol--; -+ } -+ } -+ -+ return (NULL); -+} -+ -+EXPORT_SYMBOL(cuio_copyback); -+EXPORT_SYMBOL(cuio_copydata); -+EXPORT_SYMBOL(cuio_getptr); -+ -+ -+static void -+skb_copy_bits_back(struct sk_buff *skb, int offset, caddr_t cp, int len) -+{ -+ int i; -+ if (offset < skb_headlen(skb)) { -+ memcpy(skb->data + offset, cp, min_t(int, skb_headlen(skb), len)); -+ len -= skb_headlen(skb); -+ cp += skb_headlen(skb); -+ } -+ offset -= skb_headlen(skb); -+ for (i = 0; len > 0 && i < skb_shinfo(skb)->nr_frags; i++) { -+ if (offset < skb_shinfo(skb)->frags[i].size) { -+ memcpy(page_address(skb_shinfo(skb)->frags[i].page) + -+ skb_shinfo(skb)->frags[i].page_offset, -+ cp, min_t(int, skb_shinfo(skb)->frags[i].size, len)); -+ len -= skb_shinfo(skb)->frags[i].size; -+ cp += skb_shinfo(skb)->frags[i].size; -+ } -+ offset -= skb_shinfo(skb)->frags[i].size; -+ } -+} -+ -+void -+crypto_copyback(int flags, caddr_t buf, int off, int size, caddr_t in) -+{ -+ -+ if ((flags & CRYPTO_F_SKBUF) != 0) -+ skb_copy_bits_back((struct sk_buff *)buf, off, in, size); -+ else if ((flags & CRYPTO_F_IOV) != 0) -+ cuio_copyback((struct uio *)buf, off, size, in); -+ else -+ bcopy(in, buf + off, size); -+} -+ -+void -+crypto_copydata(int flags, caddr_t buf, int off, int size, caddr_t out) -+{ -+ -+ if ((flags & CRYPTO_F_SKBUF) != 0) -+ skb_copy_bits((struct sk_buff *)buf, off, out, size); -+ else if ((flags & CRYPTO_F_IOV) != 0) -+ cuio_copydata((struct uio *)buf, off, size, out); -+ else -+ bcopy(buf + off, out, size); -+} -+ -+int -+crypto_apply(int flags, caddr_t buf, int off, int len, -+ int (*f)(void *, void *, u_int), void *arg) -+{ -+#if 0 -+ int error; -+ -+ if ((flags & CRYPTO_F_SKBUF) != 0) -+ error = XXXXXX((struct mbuf *)buf, off, len, f, arg); -+ else if ((flags & CRYPTO_F_IOV) != 0) -+ error = cuio_apply((struct uio *)buf, off, len, f, arg); -+ else -+ error = (*f)(arg, buf + off, len); -+ return (error); -+#else -+ KASSERT(0, ("crypto_apply not implemented!\n")); -+#endif -+ return 0; -+} -+ -+EXPORT_SYMBOL(crypto_copyback); -+EXPORT_SYMBOL(crypto_copydata); -+EXPORT_SYMBOL(crypto_apply); -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/crypto.c linux-2.6.39/crypto/ocf/crypto.c ---- linux-2.6.39.orig/crypto/ocf/crypto.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/crypto.c 2011-08-01 14:38:42.000000000 +0200 -@@ -0,0 +1,1781 @@ -+/*- -+ * Linux port done by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * The license and original author are listed below. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * Copyright (c) 2002-2006 Sam Leffler. All rights reserved. -+ * -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#if 0 -+#include -+__FBSDID("$FreeBSD: src/sys/opencrypto/crypto.c,v 1.27 2007/03/21 03:42:51 sam Exp $"); -+#endif -+ -+/* -+ * Cryptographic Subsystem. -+ * -+ * This code is derived from the Openbsd Cryptographic Framework (OCF) -+ * that has the copyright shown below. Very little of the original -+ * code remains. -+ */ -+/*- -+ * The author of this code is Angelos D. Keromytis (angelos@cis.upenn.edu) -+ * -+ * This code was written by Angelos D. Keromytis in Athens, Greece, in -+ * February 2000. Network Security Technologies Inc. (NSTI) kindly -+ * supported the development of this code. -+ * -+ * Copyright (c) 2000, 2001 Angelos D. Keromytis -+ * -+ * Permission to use, copy, and modify this software with or without fee -+ * is hereby granted, provided that this entire notice is included in -+ * all source code copies of any software which is or includes a copy or -+ * modification of this software. -+ * -+ * THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR -+ * IMPLIED WARRANTY. IN PARTICULAR, NONE OF THE AUTHORS MAKES ANY -+ * REPRESENTATION OR WARRANTY OF ANY KIND CONCERNING THE -+ * MERCHANTABILITY OF THIS SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR -+ * PURPOSE. -+ * -+__FBSDID("$FreeBSD: src/sys/opencrypto/crypto.c,v 1.16 2005/01/07 02:29:16 imp Exp $"); -+ */ -+ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* -+ * keep track of whether or not we have been initialised, a big -+ * issue if we are linked into the kernel and a driver gets started before -+ * us -+ */ -+static int crypto_initted = 0; -+ -+/* -+ * Crypto drivers register themselves by allocating a slot in the -+ * crypto_drivers table with crypto_get_driverid() and then registering -+ * each algorithm they support with crypto_register() and crypto_kregister(). -+ */ -+ -+/* -+ * lock on driver table -+ * we track its state as spin_is_locked does not do anything on non-SMP boxes -+ */ -+static spinlock_t crypto_drivers_lock; -+static int crypto_drivers_locked; /* for non-SMP boxes */ -+ -+#define CRYPTO_DRIVER_LOCK() \ -+ ({ \ -+ spin_lock_irqsave(&crypto_drivers_lock, d_flags); \ -+ crypto_drivers_locked = 1; \ -+ dprintk("%s,%d: DRIVER_LOCK()\n", __FILE__, __LINE__); \ -+ }) -+#define CRYPTO_DRIVER_UNLOCK() \ -+ ({ \ -+ dprintk("%s,%d: DRIVER_UNLOCK()\n", __FILE__, __LINE__); \ -+ crypto_drivers_locked = 0; \ -+ spin_unlock_irqrestore(&crypto_drivers_lock, d_flags); \ -+ }) -+#define CRYPTO_DRIVER_ASSERT() \ -+ ({ \ -+ if (!crypto_drivers_locked) { \ -+ dprintk("%s,%d: DRIVER_ASSERT!\n", __FILE__, __LINE__); \ -+ } \ -+ }) -+ -+/* -+ * Crypto device/driver capabilities structure. -+ * -+ * Synchronization: -+ * (d) - protected by CRYPTO_DRIVER_LOCK() -+ * (q) - protected by CRYPTO_Q_LOCK() -+ * Not tagged fields are read-only. -+ */ -+struct cryptocap { -+ device_t cc_dev; /* (d) device/driver */ -+ u_int32_t cc_sessions; /* (d) # of sessions */ -+ u_int32_t cc_koperations; /* (d) # os asym operations */ -+ /* -+ * Largest possible operator length (in bits) for each type of -+ * encryption algorithm. XXX not used -+ */ -+ u_int16_t cc_max_op_len[CRYPTO_ALGORITHM_MAX + 1]; -+ u_int8_t cc_alg[CRYPTO_ALGORITHM_MAX + 1]; -+ u_int8_t cc_kalg[CRK_ALGORITHM_MAX + 1]; -+ -+ int cc_flags; /* (d) flags */ -+#define CRYPTOCAP_F_CLEANUP 0x80000000 /* needs resource cleanup */ -+ int cc_qblocked; /* (q) symmetric q blocked */ -+ int cc_kqblocked; /* (q) asymmetric q blocked */ -+ -+ int cc_unqblocked; /* (q) symmetric q blocked */ -+ int cc_unkqblocked; /* (q) asymmetric q blocked */ -+}; -+static struct cryptocap *crypto_drivers = NULL; -+static int crypto_drivers_num = 0; -+ -+/* -+ * There are two queues for crypto requests; one for symmetric (e.g. -+ * cipher) operations and one for asymmetric (e.g. MOD)operations. -+ * A single mutex is used to lock access to both queues. We could -+ * have one per-queue but having one simplifies handling of block/unblock -+ * operations. -+ */ -+static int crp_sleep = 0; -+static LIST_HEAD(crp_q); /* request queues */ -+static LIST_HEAD(crp_kq); -+ -+static spinlock_t crypto_q_lock; -+ -+int crypto_all_qblocked = 0; /* protect with Q_LOCK */ -+module_param(crypto_all_qblocked, int, 0444); -+MODULE_PARM_DESC(crypto_all_qblocked, "Are all crypto queues blocked"); -+ -+int crypto_all_kqblocked = 0; /* protect with Q_LOCK */ -+module_param(crypto_all_kqblocked, int, 0444); -+MODULE_PARM_DESC(crypto_all_kqblocked, "Are all asym crypto queues blocked"); -+ -+#define CRYPTO_Q_LOCK() \ -+ ({ \ -+ spin_lock_irqsave(&crypto_q_lock, q_flags); \ -+ dprintk("%s,%d: Q_LOCK()\n", __FILE__, __LINE__); \ -+ }) -+#define CRYPTO_Q_UNLOCK() \ -+ ({ \ -+ dprintk("%s,%d: Q_UNLOCK()\n", __FILE__, __LINE__); \ -+ spin_unlock_irqrestore(&crypto_q_lock, q_flags); \ -+ }) -+ -+/* -+ * There are two queues for processing completed crypto requests; one -+ * for the symmetric and one for the asymmetric ops. We only need one -+ * but have two to avoid type futzing (cryptop vs. cryptkop). A single -+ * mutex is used to lock access to both queues. Note that this lock -+ * must be separate from the lock on request queues to insure driver -+ * callbacks don't generate lock order reversals. -+ */ -+static LIST_HEAD(crp_ret_q); /* callback queues */ -+static LIST_HEAD(crp_ret_kq); -+ -+static spinlock_t crypto_ret_q_lock; -+#define CRYPTO_RETQ_LOCK() \ -+ ({ \ -+ spin_lock_irqsave(&crypto_ret_q_lock, r_flags); \ -+ dprintk("%s,%d: RETQ_LOCK\n", __FILE__, __LINE__); \ -+ }) -+#define CRYPTO_RETQ_UNLOCK() \ -+ ({ \ -+ dprintk("%s,%d: RETQ_UNLOCK\n", __FILE__, __LINE__); \ -+ spin_unlock_irqrestore(&crypto_ret_q_lock, r_flags); \ -+ }) -+#define CRYPTO_RETQ_EMPTY() (list_empty(&crp_ret_q) && list_empty(&crp_ret_kq)) -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) -+static kmem_cache_t *cryptop_zone; -+static kmem_cache_t *cryptodesc_zone; -+#else -+static struct kmem_cache *cryptop_zone; -+static struct kmem_cache *cryptodesc_zone; -+#endif -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) -+#include -+#define kill_proc(p,s,v) send_sig(s,find_task_by_vpid(p),0) -+#endif -+ -+#define debug crypto_debug -+int crypto_debug = 0; -+module_param(crypto_debug, int, 0644); -+MODULE_PARM_DESC(crypto_debug, "Enable debug"); -+EXPORT_SYMBOL(crypto_debug); -+ -+/* -+ * Maximum number of outstanding crypto requests before we start -+ * failing requests. We need this to prevent DOS when too many -+ * requests are arriving for us to keep up. Otherwise we will -+ * run the system out of memory. Since crypto is slow, we are -+ * usually the bottleneck that needs to say, enough is enough. -+ * -+ * We cannot print errors when this condition occurs, we are already too -+ * slow, printing anything will just kill us -+ */ -+ -+static int crypto_q_cnt = 0; -+module_param(crypto_q_cnt, int, 0444); -+MODULE_PARM_DESC(crypto_q_cnt, -+ "Current number of outstanding crypto requests"); -+ -+static int crypto_q_max = 1000; -+module_param(crypto_q_max, int, 0644); -+MODULE_PARM_DESC(crypto_q_max, -+ "Maximum number of outstanding crypto requests"); -+ -+#define bootverbose crypto_verbose -+static int crypto_verbose = 0; -+module_param(crypto_verbose, int, 0644); -+MODULE_PARM_DESC(crypto_verbose, -+ "Enable verbose crypto startup"); -+ -+int crypto_usercrypto = 1; /* userland may do crypto reqs */ -+module_param(crypto_usercrypto, int, 0644); -+MODULE_PARM_DESC(crypto_usercrypto, -+ "Enable/disable user-mode access to crypto support"); -+ -+int crypto_userasymcrypto = 1; /* userland may do asym crypto reqs */ -+module_param(crypto_userasymcrypto, int, 0644); -+MODULE_PARM_DESC(crypto_userasymcrypto, -+ "Enable/disable user-mode access to asymmetric crypto support"); -+ -+int crypto_devallowsoft = 0; /* only use hardware crypto */ -+module_param(crypto_devallowsoft, int, 0644); -+MODULE_PARM_DESC(crypto_devallowsoft, -+ "Enable/disable use of software crypto support"); -+ -+/* -+ * This parameter controls the maximum number of crypto operations to -+ * do consecutively in the crypto kernel thread before scheduling to allow -+ * other processes to run. Without it, it is possible to get into a -+ * situation where the crypto thread never allows any other processes to run. -+ * Default to 1000 which should be less than one second. -+ */ -+static int crypto_max_loopcount = 1000; -+module_param(crypto_max_loopcount, int, 0644); -+MODULE_PARM_DESC(crypto_max_loopcount, -+ "Maximum number of crypto ops to do before yielding to other processes"); -+ -+static pid_t cryptoproc = (pid_t) -1; -+static struct completion cryptoproc_exited; -+static DECLARE_WAIT_QUEUE_HEAD(cryptoproc_wait); -+static pid_t cryptoretproc = (pid_t) -1; -+static struct completion cryptoretproc_exited; -+static DECLARE_WAIT_QUEUE_HEAD(cryptoretproc_wait); -+ -+static int crypto_proc(void *arg); -+static int crypto_ret_proc(void *arg); -+static int crypto_invoke(struct cryptocap *cap, struct cryptop *crp, int hint); -+static int crypto_kinvoke(struct cryptkop *krp, int flags); -+static void crypto_exit(void); -+static int crypto_init(void); -+ -+static struct cryptostats cryptostats; -+ -+static struct cryptocap * -+crypto_checkdriver(u_int32_t hid) -+{ -+ if (crypto_drivers == NULL) -+ return NULL; -+ return (hid >= crypto_drivers_num ? NULL : &crypto_drivers[hid]); -+} -+ -+/* -+ * Compare a driver's list of supported algorithms against another -+ * list; return non-zero if all algorithms are supported. -+ */ -+static int -+driver_suitable(const struct cryptocap *cap, const struct cryptoini *cri) -+{ -+ const struct cryptoini *cr; -+ -+ /* See if all the algorithms are supported. */ -+ for (cr = cri; cr; cr = cr->cri_next) -+ if (cap->cc_alg[cr->cri_alg] == 0) -+ return 0; -+ return 1; -+} -+ -+/* -+ * Select a driver for a new session that supports the specified -+ * algorithms and, optionally, is constrained according to the flags. -+ * The algorithm we use here is pretty stupid; just use the -+ * first driver that supports all the algorithms we need. If there -+ * are multiple drivers we choose the driver with the fewest active -+ * sessions. We prefer hardware-backed drivers to software ones. -+ * -+ * XXX We need more smarts here (in real life too, but that's -+ * XXX another story altogether). -+ */ -+static struct cryptocap * -+crypto_select_driver(const struct cryptoini *cri, int flags) -+{ -+ struct cryptocap *cap, *best; -+ int match, hid; -+ -+ CRYPTO_DRIVER_ASSERT(); -+ -+ /* -+ * Look first for hardware crypto devices if permitted. -+ */ -+ if (flags & CRYPTOCAP_F_HARDWARE) -+ match = CRYPTOCAP_F_HARDWARE; -+ else -+ match = CRYPTOCAP_F_SOFTWARE; -+ best = NULL; -+again: -+ for (hid = 0; hid < crypto_drivers_num; hid++) { -+ cap = &crypto_drivers[hid]; -+ /* -+ * If it's not initialized, is in the process of -+ * going away, or is not appropriate (hardware -+ * or software based on match), then skip. -+ */ -+ if (cap->cc_dev == NULL || -+ (cap->cc_flags & CRYPTOCAP_F_CLEANUP) || -+ (cap->cc_flags & match) == 0) -+ continue; -+ -+ /* verify all the algorithms are supported. */ -+ if (driver_suitable(cap, cri)) { -+ if (best == NULL || -+ cap->cc_sessions < best->cc_sessions) -+ best = cap; -+ } -+ } -+ if (best != NULL) -+ return best; -+ if (match == CRYPTOCAP_F_HARDWARE && (flags & CRYPTOCAP_F_SOFTWARE)) { -+ /* sort of an Algol 68-style for loop */ -+ match = CRYPTOCAP_F_SOFTWARE; -+ goto again; -+ } -+ return best; -+} -+ -+/* -+ * Create a new session. The crid argument specifies a crypto -+ * driver to use or constraints on a driver to select (hardware -+ * only, software only, either). Whatever driver is selected -+ * must be capable of the requested crypto algorithms. -+ */ -+int -+crypto_newsession(u_int64_t *sid, struct cryptoini *cri, int crid) -+{ -+ struct cryptocap *cap; -+ u_int32_t hid, lid; -+ int err; -+ unsigned long d_flags; -+ -+ CRYPTO_DRIVER_LOCK(); -+ if ((crid & (CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE)) == 0) { -+ /* -+ * Use specified driver; verify it is capable. -+ */ -+ cap = crypto_checkdriver(crid); -+ if (cap != NULL && !driver_suitable(cap, cri)) -+ cap = NULL; -+ } else { -+ /* -+ * No requested driver; select based on crid flags. -+ */ -+ cap = crypto_select_driver(cri, crid); -+ /* -+ * if NULL then can't do everything in one session. -+ * XXX Fix this. We need to inject a "virtual" session -+ * XXX layer right about here. -+ */ -+ } -+ if (cap != NULL) { -+ /* Call the driver initialization routine. */ -+ hid = cap - crypto_drivers; -+ lid = hid; /* Pass the driver ID. */ -+ cap->cc_sessions++; -+ CRYPTO_DRIVER_UNLOCK(); -+ err = CRYPTODEV_NEWSESSION(cap->cc_dev, &lid, cri); -+ CRYPTO_DRIVER_LOCK(); -+ if (err == 0) { -+ (*sid) = (cap->cc_flags & 0xff000000) -+ | (hid & 0x00ffffff); -+ (*sid) <<= 32; -+ (*sid) |= (lid & 0xffffffff); -+ } else -+ cap->cc_sessions--; -+ } else -+ err = EINVAL; -+ CRYPTO_DRIVER_UNLOCK(); -+ return err; -+} -+ -+static void -+crypto_remove(struct cryptocap *cap) -+{ -+ CRYPTO_DRIVER_ASSERT(); -+ if (cap->cc_sessions == 0 && cap->cc_koperations == 0) -+ bzero(cap, sizeof(*cap)); -+} -+ -+/* -+ * Delete an existing session (or a reserved session on an unregistered -+ * driver). -+ */ -+int -+crypto_freesession(u_int64_t sid) -+{ -+ struct cryptocap *cap; -+ u_int32_t hid; -+ int err = 0; -+ unsigned long d_flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ CRYPTO_DRIVER_LOCK(); -+ -+ if (crypto_drivers == NULL) { -+ err = EINVAL; -+ goto done; -+ } -+ -+ /* Determine two IDs. */ -+ hid = CRYPTO_SESID2HID(sid); -+ -+ if (hid >= crypto_drivers_num) { -+ dprintk("%s - INVALID DRIVER NUM %d\n", __FUNCTION__, hid); -+ err = ENOENT; -+ goto done; -+ } -+ cap = &crypto_drivers[hid]; -+ -+ if (cap->cc_dev) { -+ CRYPTO_DRIVER_UNLOCK(); -+ /* Call the driver cleanup routine, if available, unlocked. */ -+ err = CRYPTODEV_FREESESSION(cap->cc_dev, sid); -+ CRYPTO_DRIVER_LOCK(); -+ } -+ -+ if (cap->cc_sessions) -+ cap->cc_sessions--; -+ -+ if (cap->cc_flags & CRYPTOCAP_F_CLEANUP) -+ crypto_remove(cap); -+ -+done: -+ CRYPTO_DRIVER_UNLOCK(); -+ return err; -+} -+ -+/* -+ * Return an unused driver id. Used by drivers prior to registering -+ * support for the algorithms they handle. -+ */ -+int32_t -+crypto_get_driverid(device_t dev, int flags) -+{ -+ struct cryptocap *newdrv; -+ int i; -+ unsigned long d_flags; -+ -+ if ((flags & (CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE)) == 0) { -+ printf("%s: no flags specified when registering driver\n", -+ device_get_nameunit(dev)); -+ return -1; -+ } -+ -+ CRYPTO_DRIVER_LOCK(); -+ -+ for (i = 0; i < crypto_drivers_num; i++) { -+ if (crypto_drivers[i].cc_dev == NULL && -+ (crypto_drivers[i].cc_flags & CRYPTOCAP_F_CLEANUP) == 0) { -+ break; -+ } -+ } -+ -+ /* Out of entries, allocate some more. */ -+ if (i == crypto_drivers_num) { -+ /* Be careful about wrap-around. */ -+ if (2 * crypto_drivers_num <= crypto_drivers_num) { -+ CRYPTO_DRIVER_UNLOCK(); -+ printk("crypto: driver count wraparound!\n"); -+ return -1; -+ } -+ -+ newdrv = kmalloc(2 * crypto_drivers_num * sizeof(struct cryptocap), -+ GFP_KERNEL); -+ if (newdrv == NULL) { -+ CRYPTO_DRIVER_UNLOCK(); -+ printk("crypto: no space to expand driver table!\n"); -+ return -1; -+ } -+ -+ memcpy(newdrv, crypto_drivers, -+ crypto_drivers_num * sizeof(struct cryptocap)); -+ memset(&newdrv[crypto_drivers_num], 0, -+ crypto_drivers_num * sizeof(struct cryptocap)); -+ -+ crypto_drivers_num *= 2; -+ -+ kfree(crypto_drivers); -+ crypto_drivers = newdrv; -+ } -+ -+ /* NB: state is zero'd on free */ -+ crypto_drivers[i].cc_sessions = 1; /* Mark */ -+ crypto_drivers[i].cc_dev = dev; -+ crypto_drivers[i].cc_flags = flags; -+ if (bootverbose) -+ printf("crypto: assign %s driver id %u, flags %u\n", -+ device_get_nameunit(dev), i, flags); -+ -+ CRYPTO_DRIVER_UNLOCK(); -+ -+ return i; -+} -+ -+/* -+ * Lookup a driver by name. We match against the full device -+ * name and unit, and against just the name. The latter gives -+ * us a simple widlcarding by device name. On success return the -+ * driver/hardware identifier; otherwise return -1. -+ */ -+int -+crypto_find_driver(const char *match) -+{ -+ int i, len = strlen(match); -+ unsigned long d_flags; -+ -+ CRYPTO_DRIVER_LOCK(); -+ for (i = 0; i < crypto_drivers_num; i++) { -+ device_t dev = crypto_drivers[i].cc_dev; -+ if (dev == NULL || -+ (crypto_drivers[i].cc_flags & CRYPTOCAP_F_CLEANUP)) -+ continue; -+ if (strncmp(match, device_get_nameunit(dev), len) == 0 || -+ strncmp(match, device_get_name(dev), len) == 0) -+ break; -+ } -+ CRYPTO_DRIVER_UNLOCK(); -+ return i < crypto_drivers_num ? i : -1; -+} -+ -+/* -+ * Return the device_t for the specified driver or NULL -+ * if the driver identifier is invalid. -+ */ -+device_t -+crypto_find_device_byhid(int hid) -+{ -+ struct cryptocap *cap = crypto_checkdriver(hid); -+ return cap != NULL ? cap->cc_dev : NULL; -+} -+ -+/* -+ * Return the device/driver capabilities. -+ */ -+int -+crypto_getcaps(int hid) -+{ -+ struct cryptocap *cap = crypto_checkdriver(hid); -+ return cap != NULL ? cap->cc_flags : 0; -+} -+ -+/* -+ * Register support for a key-related algorithm. This routine -+ * is called once for each algorithm supported a driver. -+ */ -+int -+crypto_kregister(u_int32_t driverid, int kalg, u_int32_t flags) -+{ -+ struct cryptocap *cap; -+ int err; -+ unsigned long d_flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ CRYPTO_DRIVER_LOCK(); -+ -+ cap = crypto_checkdriver(driverid); -+ if (cap != NULL && -+ (CRK_ALGORITM_MIN <= kalg && kalg <= CRK_ALGORITHM_MAX)) { -+ /* -+ * XXX Do some performance testing to determine placing. -+ * XXX We probably need an auxiliary data structure that -+ * XXX describes relative performances. -+ */ -+ -+ cap->cc_kalg[kalg] = flags | CRYPTO_ALG_FLAG_SUPPORTED; -+ if (bootverbose) -+ printf("crypto: %s registers key alg %u flags %u\n" -+ , device_get_nameunit(cap->cc_dev) -+ , kalg -+ , flags -+ ); -+ err = 0; -+ } else -+ err = EINVAL; -+ -+ CRYPTO_DRIVER_UNLOCK(); -+ return err; -+} -+ -+/* -+ * Register support for a non-key-related algorithm. This routine -+ * is called once for each such algorithm supported by a driver. -+ */ -+int -+crypto_register(u_int32_t driverid, int alg, u_int16_t maxoplen, -+ u_int32_t flags) -+{ -+ struct cryptocap *cap; -+ int err; -+ unsigned long d_flags; -+ -+ dprintk("%s(id=0x%x, alg=%d, maxoplen=%d, flags=0x%x)\n", __FUNCTION__, -+ driverid, alg, maxoplen, flags); -+ -+ CRYPTO_DRIVER_LOCK(); -+ -+ cap = crypto_checkdriver(driverid); -+ /* NB: algorithms are in the range [1..max] */ -+ if (cap != NULL && -+ (CRYPTO_ALGORITHM_MIN <= alg && alg <= CRYPTO_ALGORITHM_MAX)) { -+ /* -+ * XXX Do some performance testing to determine placing. -+ * XXX We probably need an auxiliary data structure that -+ * XXX describes relative performances. -+ */ -+ -+ cap->cc_alg[alg] = flags | CRYPTO_ALG_FLAG_SUPPORTED; -+ cap->cc_max_op_len[alg] = maxoplen; -+ if (bootverbose) -+ printf("crypto: %s registers alg %u flags %u maxoplen %u\n" -+ , device_get_nameunit(cap->cc_dev) -+ , alg -+ , flags -+ , maxoplen -+ ); -+ cap->cc_sessions = 0; /* Unmark */ -+ err = 0; -+ } else -+ err = EINVAL; -+ -+ CRYPTO_DRIVER_UNLOCK(); -+ return err; -+} -+ -+static void -+driver_finis(struct cryptocap *cap) -+{ -+ u_int32_t ses, kops; -+ -+ CRYPTO_DRIVER_ASSERT(); -+ -+ ses = cap->cc_sessions; -+ kops = cap->cc_koperations; -+ bzero(cap, sizeof(*cap)); -+ if (ses != 0 || kops != 0) { -+ /* -+ * If there are pending sessions, -+ * just mark as invalid. -+ */ -+ cap->cc_flags |= CRYPTOCAP_F_CLEANUP; -+ cap->cc_sessions = ses; -+ cap->cc_koperations = kops; -+ } -+} -+ -+/* -+ * Unregister a crypto driver. If there are pending sessions using it, -+ * leave enough information around so that subsequent calls using those -+ * sessions will correctly detect the driver has been unregistered and -+ * reroute requests. -+ */ -+int -+crypto_unregister(u_int32_t driverid, int alg) -+{ -+ struct cryptocap *cap; -+ int i, err; -+ unsigned long d_flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ CRYPTO_DRIVER_LOCK(); -+ -+ cap = crypto_checkdriver(driverid); -+ if (cap != NULL && -+ (CRYPTO_ALGORITHM_MIN <= alg && alg <= CRYPTO_ALGORITHM_MAX) && -+ cap->cc_alg[alg] != 0) { -+ cap->cc_alg[alg] = 0; -+ cap->cc_max_op_len[alg] = 0; -+ -+ /* Was this the last algorithm ? */ -+ for (i = 1; i <= CRYPTO_ALGORITHM_MAX; i++) -+ if (cap->cc_alg[i] != 0) -+ break; -+ -+ if (i == CRYPTO_ALGORITHM_MAX + 1) -+ driver_finis(cap); -+ err = 0; -+ } else -+ err = EINVAL; -+ CRYPTO_DRIVER_UNLOCK(); -+ return err; -+} -+ -+/* -+ * Unregister all algorithms associated with a crypto driver. -+ * If there are pending sessions using it, leave enough information -+ * around so that subsequent calls using those sessions will -+ * correctly detect the driver has been unregistered and reroute -+ * requests. -+ */ -+int -+crypto_unregister_all(u_int32_t driverid) -+{ -+ struct cryptocap *cap; -+ int err; -+ unsigned long d_flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ CRYPTO_DRIVER_LOCK(); -+ cap = crypto_checkdriver(driverid); -+ if (cap != NULL) { -+ driver_finis(cap); -+ err = 0; -+ } else -+ err = EINVAL; -+ CRYPTO_DRIVER_UNLOCK(); -+ -+ return err; -+} -+ -+/* -+ * Clear blockage on a driver. The what parameter indicates whether -+ * the driver is now ready for cryptop's and/or cryptokop's. -+ */ -+int -+crypto_unblock(u_int32_t driverid, int what) -+{ -+ struct cryptocap *cap; -+ int err; -+ unsigned long q_flags; -+ -+ CRYPTO_Q_LOCK(); -+ cap = crypto_checkdriver(driverid); -+ if (cap != NULL) { -+ if (what & CRYPTO_SYMQ) { -+ cap->cc_qblocked = 0; -+ cap->cc_unqblocked = 0; -+ crypto_all_qblocked = 0; -+ } -+ if (what & CRYPTO_ASYMQ) { -+ cap->cc_kqblocked = 0; -+ cap->cc_unkqblocked = 0; -+ crypto_all_kqblocked = 0; -+ } -+ if (crp_sleep) -+ wake_up_interruptible(&cryptoproc_wait); -+ err = 0; -+ } else -+ err = EINVAL; -+ CRYPTO_Q_UNLOCK(); //DAVIDM should this be a driver lock -+ -+ return err; -+} -+ -+/* -+ * Add a crypto request to a queue, to be processed by the kernel thread. -+ */ -+int -+crypto_dispatch(struct cryptop *crp) -+{ -+ struct cryptocap *cap; -+ int result = -1; -+ unsigned long q_flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ cryptostats.cs_ops++; -+ -+ CRYPTO_Q_LOCK(); -+ if (crypto_q_cnt >= crypto_q_max) { -+ CRYPTO_Q_UNLOCK(); -+ cryptostats.cs_drops++; -+ return ENOMEM; -+ } -+ crypto_q_cnt++; -+ -+ /* make sure we are starting a fresh run on this crp. */ -+ crp->crp_flags &= ~CRYPTO_F_DONE; -+ crp->crp_etype = 0; -+ -+ /* -+ * Caller marked the request to be processed immediately; dispatch -+ * it directly to the driver unless the driver is currently blocked. -+ */ -+ if ((crp->crp_flags & CRYPTO_F_BATCH) == 0) { -+ int hid = CRYPTO_SESID2HID(crp->crp_sid); -+ cap = crypto_checkdriver(hid); -+ /* Driver cannot disappear when there is an active session. */ -+ KASSERT(cap != NULL, ("%s: Driver disappeared.", __func__)); -+ if (!cap->cc_qblocked) { -+ crypto_all_qblocked = 0; -+ crypto_drivers[hid].cc_unqblocked = 1; -+ CRYPTO_Q_UNLOCK(); -+ result = crypto_invoke(cap, crp, 0); -+ CRYPTO_Q_LOCK(); -+ if (result == ERESTART) -+ if (crypto_drivers[hid].cc_unqblocked) -+ crypto_drivers[hid].cc_qblocked = 1; -+ crypto_drivers[hid].cc_unqblocked = 0; -+ } -+ } -+ if (result == ERESTART) { -+ /* -+ * The driver ran out of resources, mark the -+ * driver ``blocked'' for cryptop's and put -+ * the request back in the queue. It would -+ * best to put the request back where we got -+ * it but that's hard so for now we put it -+ * at the front. This should be ok; putting -+ * it at the end does not work. -+ */ -+ list_add(&crp->crp_next, &crp_q); -+ cryptostats.cs_blocks++; -+ result = 0; -+ } else if (result == -1) { -+ TAILQ_INSERT_TAIL(&crp_q, crp, crp_next); -+ result = 0; -+ } -+ if (crp_sleep) -+ wake_up_interruptible(&cryptoproc_wait); -+ CRYPTO_Q_UNLOCK(); -+ return result; -+} -+ -+/* -+ * Add an asymetric crypto request to a queue, -+ * to be processed by the kernel thread. -+ */ -+int -+crypto_kdispatch(struct cryptkop *krp) -+{ -+ int error; -+ unsigned long q_flags; -+ -+ cryptostats.cs_kops++; -+ -+ error = crypto_kinvoke(krp, krp->krp_crid); -+ if (error == ERESTART) { -+ CRYPTO_Q_LOCK(); -+ TAILQ_INSERT_TAIL(&crp_kq, krp, krp_next); -+ if (crp_sleep) -+ wake_up_interruptible(&cryptoproc_wait); -+ CRYPTO_Q_UNLOCK(); -+ error = 0; -+ } -+ return error; -+} -+ -+/* -+ * Verify a driver is suitable for the specified operation. -+ */ -+static __inline int -+kdriver_suitable(const struct cryptocap *cap, const struct cryptkop *krp) -+{ -+ return (cap->cc_kalg[krp->krp_op] & CRYPTO_ALG_FLAG_SUPPORTED) != 0; -+} -+ -+/* -+ * Select a driver for an asym operation. The driver must -+ * support the necessary algorithm. The caller can constrain -+ * which device is selected with the flags parameter. The -+ * algorithm we use here is pretty stupid; just use the first -+ * driver that supports the algorithms we need. If there are -+ * multiple suitable drivers we choose the driver with the -+ * fewest active operations. We prefer hardware-backed -+ * drivers to software ones when either may be used. -+ */ -+static struct cryptocap * -+crypto_select_kdriver(const struct cryptkop *krp, int flags) -+{ -+ struct cryptocap *cap, *best, *blocked; -+ int match, hid; -+ -+ CRYPTO_DRIVER_ASSERT(); -+ -+ /* -+ * Look first for hardware crypto devices if permitted. -+ */ -+ if (flags & CRYPTOCAP_F_HARDWARE) -+ match = CRYPTOCAP_F_HARDWARE; -+ else -+ match = CRYPTOCAP_F_SOFTWARE; -+ best = NULL; -+ blocked = NULL; -+again: -+ for (hid = 0; hid < crypto_drivers_num; hid++) { -+ cap = &crypto_drivers[hid]; -+ /* -+ * If it's not initialized, is in the process of -+ * going away, or is not appropriate (hardware -+ * or software based on match), then skip. -+ */ -+ if (cap->cc_dev == NULL || -+ (cap->cc_flags & CRYPTOCAP_F_CLEANUP) || -+ (cap->cc_flags & match) == 0) -+ continue; -+ -+ /* verify all the algorithms are supported. */ -+ if (kdriver_suitable(cap, krp)) { -+ if (best == NULL || -+ cap->cc_koperations < best->cc_koperations) -+ best = cap; -+ } -+ } -+ if (best != NULL) -+ return best; -+ if (match == CRYPTOCAP_F_HARDWARE && (flags & CRYPTOCAP_F_SOFTWARE)) { -+ /* sort of an Algol 68-style for loop */ -+ match = CRYPTOCAP_F_SOFTWARE; -+ goto again; -+ } -+ return best; -+} -+ -+/* -+ * Dispatch an assymetric crypto request. -+ */ -+static int -+crypto_kinvoke(struct cryptkop *krp, int crid) -+{ -+ struct cryptocap *cap = NULL; -+ int error; -+ unsigned long d_flags; -+ -+ KASSERT(krp != NULL, ("%s: krp == NULL", __func__)); -+ KASSERT(krp->krp_callback != NULL, -+ ("%s: krp->crp_callback == NULL", __func__)); -+ -+ CRYPTO_DRIVER_LOCK(); -+ if ((crid & (CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE)) == 0) { -+ cap = crypto_checkdriver(crid); -+ if (cap != NULL) { -+ /* -+ * Driver present, it must support the necessary -+ * algorithm and, if s/w drivers are excluded, -+ * it must be registered as hardware-backed. -+ */ -+ if (!kdriver_suitable(cap, krp) || -+ (!crypto_devallowsoft && -+ (cap->cc_flags & CRYPTOCAP_F_HARDWARE) == 0)) -+ cap = NULL; -+ } -+ } else { -+ /* -+ * No requested driver; select based on crid flags. -+ */ -+ if (!crypto_devallowsoft) /* NB: disallow s/w drivers */ -+ crid &= ~CRYPTOCAP_F_SOFTWARE; -+ cap = crypto_select_kdriver(krp, crid); -+ } -+ if (cap != NULL && !cap->cc_kqblocked) { -+ krp->krp_hid = cap - crypto_drivers; -+ cap->cc_koperations++; -+ CRYPTO_DRIVER_UNLOCK(); -+ error = CRYPTODEV_KPROCESS(cap->cc_dev, krp, 0); -+ CRYPTO_DRIVER_LOCK(); -+ if (error == ERESTART) { -+ cap->cc_koperations--; -+ CRYPTO_DRIVER_UNLOCK(); -+ return (error); -+ } -+ /* return the actual device used */ -+ krp->krp_crid = krp->krp_hid; -+ } else { -+ /* -+ * NB: cap is !NULL if device is blocked; in -+ * that case return ERESTART so the operation -+ * is resubmitted if possible. -+ */ -+ error = (cap == NULL) ? ENODEV : ERESTART; -+ } -+ CRYPTO_DRIVER_UNLOCK(); -+ -+ if (error) { -+ krp->krp_status = error; -+ crypto_kdone(krp); -+ } -+ return 0; -+} -+ -+ -+/* -+ * Dispatch a crypto request to the appropriate crypto devices. -+ */ -+static int -+crypto_invoke(struct cryptocap *cap, struct cryptop *crp, int hint) -+{ -+ KASSERT(crp != NULL, ("%s: crp == NULL", __func__)); -+ KASSERT(crp->crp_callback != NULL, -+ ("%s: crp->crp_callback == NULL", __func__)); -+ KASSERT(crp->crp_desc != NULL, ("%s: crp->crp_desc == NULL", __func__)); -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+#ifdef CRYPTO_TIMING -+ if (crypto_timing) -+ crypto_tstat(&cryptostats.cs_invoke, &crp->crp_tstamp); -+#endif -+ if (cap->cc_flags & CRYPTOCAP_F_CLEANUP) { -+ struct cryptodesc *crd; -+ u_int64_t nid; -+ -+ /* -+ * Driver has unregistered; migrate the session and return -+ * an error to the caller so they'll resubmit the op. -+ * -+ * XXX: What if there are more already queued requests for this -+ * session? -+ */ -+ crypto_freesession(crp->crp_sid); -+ -+ for (crd = crp->crp_desc; crd->crd_next; crd = crd->crd_next) -+ crd->CRD_INI.cri_next = &(crd->crd_next->CRD_INI); -+ -+ /* XXX propagate flags from initial session? */ -+ if (crypto_newsession(&nid, &(crp->crp_desc->CRD_INI), -+ CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE) == 0) -+ crp->crp_sid = nid; -+ -+ crp->crp_etype = EAGAIN; -+ crypto_done(crp); -+ return 0; -+ } else { -+ /* -+ * Invoke the driver to process the request. -+ */ -+ return CRYPTODEV_PROCESS(cap->cc_dev, crp, hint); -+ } -+} -+ -+/* -+ * Release a set of crypto descriptors. -+ */ -+void -+crypto_freereq(struct cryptop *crp) -+{ -+ struct cryptodesc *crd; -+ -+ if (crp == NULL) -+ return; -+ -+#ifdef DIAGNOSTIC -+ { -+ struct cryptop *crp2; -+ unsigned long q_flags; -+ -+ CRYPTO_Q_LOCK(); -+ TAILQ_FOREACH(crp2, &crp_q, crp_next) { -+ KASSERT(crp2 != crp, -+ ("Freeing cryptop from the crypto queue (%p).", -+ crp)); -+ } -+ CRYPTO_Q_UNLOCK(); -+ CRYPTO_RETQ_LOCK(); -+ TAILQ_FOREACH(crp2, &crp_ret_q, crp_next) { -+ KASSERT(crp2 != crp, -+ ("Freeing cryptop from the return queue (%p).", -+ crp)); -+ } -+ CRYPTO_RETQ_UNLOCK(); -+ } -+#endif -+ -+ while ((crd = crp->crp_desc) != NULL) { -+ crp->crp_desc = crd->crd_next; -+ kmem_cache_free(cryptodesc_zone, crd); -+ } -+ kmem_cache_free(cryptop_zone, crp); -+} -+ -+/* -+ * Acquire a set of crypto descriptors. -+ */ -+struct cryptop * -+crypto_getreq(int num) -+{ -+ struct cryptodesc *crd; -+ struct cryptop *crp; -+ -+ crp = kmem_cache_alloc(cryptop_zone, SLAB_ATOMIC); -+ if (crp != NULL) { -+ memset(crp, 0, sizeof(*crp)); -+ INIT_LIST_HEAD(&crp->crp_next); -+ init_waitqueue_head(&crp->crp_waitq); -+ while (num--) { -+ crd = kmem_cache_alloc(cryptodesc_zone, SLAB_ATOMIC); -+ if (crd == NULL) { -+ crypto_freereq(crp); -+ return NULL; -+ } -+ memset(crd, 0, sizeof(*crd)); -+ crd->crd_next = crp->crp_desc; -+ crp->crp_desc = crd; -+ } -+ } -+ return crp; -+} -+ -+/* -+ * Invoke the callback on behalf of the driver. -+ */ -+void -+crypto_done(struct cryptop *crp) -+{ -+ unsigned long q_flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if ((crp->crp_flags & CRYPTO_F_DONE) == 0) { -+ crp->crp_flags |= CRYPTO_F_DONE; -+ CRYPTO_Q_LOCK(); -+ crypto_q_cnt--; -+ CRYPTO_Q_UNLOCK(); -+ } else -+ printk("crypto: crypto_done op already done, flags 0x%x", -+ crp->crp_flags); -+ if (crp->crp_etype != 0) -+ cryptostats.cs_errs++; -+ /* -+ * CBIMM means unconditionally do the callback immediately; -+ * CBIFSYNC means do the callback immediately only if the -+ * operation was done synchronously. Both are used to avoid -+ * doing extraneous context switches; the latter is mostly -+ * used with the software crypto driver. -+ */ -+ if ((crp->crp_flags & CRYPTO_F_CBIMM) || -+ ((crp->crp_flags & CRYPTO_F_CBIFSYNC) && -+ (CRYPTO_SESID2CAPS(crp->crp_sid) & CRYPTOCAP_F_SYNC))) { -+ /* -+ * Do the callback directly. This is ok when the -+ * callback routine does very little (e.g. the -+ * /dev/crypto callback method just does a wakeup). -+ */ -+ crp->crp_callback(crp); -+ } else { -+ unsigned long r_flags; -+ /* -+ * Normal case; queue the callback for the thread. -+ */ -+ CRYPTO_RETQ_LOCK(); -+ if (CRYPTO_RETQ_EMPTY()) -+ wake_up_interruptible(&cryptoretproc_wait);/* shared wait channel */ -+ TAILQ_INSERT_TAIL(&crp_ret_q, crp, crp_next); -+ CRYPTO_RETQ_UNLOCK(); -+ } -+} -+ -+/* -+ * Invoke the callback on behalf of the driver. -+ */ -+void -+crypto_kdone(struct cryptkop *krp) -+{ -+ struct cryptocap *cap; -+ unsigned long d_flags; -+ -+ if ((krp->krp_flags & CRYPTO_KF_DONE) != 0) -+ printk("crypto: crypto_kdone op already done, flags 0x%x", -+ krp->krp_flags); -+ krp->krp_flags |= CRYPTO_KF_DONE; -+ if (krp->krp_status != 0) -+ cryptostats.cs_kerrs++; -+ -+ CRYPTO_DRIVER_LOCK(); -+ /* XXX: What if driver is loaded in the meantime? */ -+ if (krp->krp_hid < crypto_drivers_num) { -+ cap = &crypto_drivers[krp->krp_hid]; -+ cap->cc_koperations--; -+ KASSERT(cap->cc_koperations >= 0, ("cc_koperations < 0")); -+ if (cap->cc_flags & CRYPTOCAP_F_CLEANUP) -+ crypto_remove(cap); -+ } -+ CRYPTO_DRIVER_UNLOCK(); -+ -+ /* -+ * CBIMM means unconditionally do the callback immediately; -+ * This is used to avoid doing extraneous context switches -+ */ -+ if ((krp->krp_flags & CRYPTO_KF_CBIMM)) { -+ /* -+ * Do the callback directly. This is ok when the -+ * callback routine does very little (e.g. the -+ * /dev/crypto callback method just does a wakeup). -+ */ -+ krp->krp_callback(krp); -+ } else { -+ unsigned long r_flags; -+ /* -+ * Normal case; queue the callback for the thread. -+ */ -+ CRYPTO_RETQ_LOCK(); -+ if (CRYPTO_RETQ_EMPTY()) -+ wake_up_interruptible(&cryptoretproc_wait);/* shared wait channel */ -+ TAILQ_INSERT_TAIL(&crp_ret_kq, krp, krp_next); -+ CRYPTO_RETQ_UNLOCK(); -+ } -+} -+ -+int -+crypto_getfeat(int *featp) -+{ -+ int hid, kalg, feat = 0; -+ unsigned long d_flags; -+ -+ CRYPTO_DRIVER_LOCK(); -+ for (hid = 0; hid < crypto_drivers_num; hid++) { -+ const struct cryptocap *cap = &crypto_drivers[hid]; -+ -+ if ((cap->cc_flags & CRYPTOCAP_F_SOFTWARE) && -+ !crypto_devallowsoft) { -+ continue; -+ } -+ for (kalg = 0; kalg < CRK_ALGORITHM_MAX; kalg++) -+ if (cap->cc_kalg[kalg] & CRYPTO_ALG_FLAG_SUPPORTED) -+ feat |= 1 << kalg; -+ } -+ CRYPTO_DRIVER_UNLOCK(); -+ *featp = feat; -+ return (0); -+} -+ -+/* -+ * Crypto thread, dispatches crypto requests. -+ */ -+static int -+crypto_proc(void *arg) -+{ -+ struct cryptop *crp, *submit; -+ struct cryptkop *krp, *krpp; -+ struct cryptocap *cap; -+ u_int32_t hid; -+ int result, hint; -+ unsigned long q_flags; -+ int loopcount = 0; -+ -+ ocf_daemonize("crypto"); -+ -+ CRYPTO_Q_LOCK(); -+ for (;;) { -+ /* -+ * we need to make sure we don't get into a busy loop with nothing -+ * to do, the two crypto_all_*blocked vars help us find out when -+ * we are all full and can do nothing on any driver or Q. If so we -+ * wait for an unblock. -+ */ -+ crypto_all_qblocked = !list_empty(&crp_q); -+ -+ /* -+ * Find the first element in the queue that can be -+ * processed and look-ahead to see if multiple ops -+ * are ready for the same driver. -+ */ -+ submit = NULL; -+ hint = 0; -+ list_for_each_entry(crp, &crp_q, crp_next) { -+ hid = CRYPTO_SESID2HID(crp->crp_sid); -+ cap = crypto_checkdriver(hid); -+ /* -+ * Driver cannot disappear when there is an active -+ * session. -+ */ -+ KASSERT(cap != NULL, ("%s:%u Driver disappeared.", -+ __func__, __LINE__)); -+ if (cap == NULL || cap->cc_dev == NULL) { -+ /* Op needs to be migrated, process it. */ -+ if (submit == NULL) -+ submit = crp; -+ break; -+ } -+ if (!cap->cc_qblocked) { -+ if (submit != NULL) { -+ /* -+ * We stop on finding another op, -+ * regardless whether its for the same -+ * driver or not. We could keep -+ * searching the queue but it might be -+ * better to just use a per-driver -+ * queue instead. -+ */ -+ if (CRYPTO_SESID2HID(submit->crp_sid) == hid) -+ hint = CRYPTO_HINT_MORE; -+ break; -+ } else { -+ submit = crp; -+ if ((submit->crp_flags & CRYPTO_F_BATCH) == 0) -+ break; -+ /* keep scanning for more are q'd */ -+ } -+ } -+ } -+ if (submit != NULL) { -+ hid = CRYPTO_SESID2HID(submit->crp_sid); -+ crypto_all_qblocked = 0; -+ list_del(&submit->crp_next); -+ crypto_drivers[hid].cc_unqblocked = 1; -+ cap = crypto_checkdriver(hid); -+ CRYPTO_Q_UNLOCK(); -+ KASSERT(cap != NULL, ("%s:%u Driver disappeared.", -+ __func__, __LINE__)); -+ result = crypto_invoke(cap, submit, hint); -+ CRYPTO_Q_LOCK(); -+ if (result == ERESTART) { -+ /* -+ * The driver ran out of resources, mark the -+ * driver ``blocked'' for cryptop's and put -+ * the request back in the queue. It would -+ * best to put the request back where we got -+ * it but that's hard so for now we put it -+ * at the front. This should be ok; putting -+ * it at the end does not work. -+ */ -+ /* XXX validate sid again? */ -+ list_add(&submit->crp_next, &crp_q); -+ cryptostats.cs_blocks++; -+ if (crypto_drivers[hid].cc_unqblocked) -+ crypto_drivers[hid].cc_qblocked=0; -+ crypto_drivers[hid].cc_unqblocked=0; -+ } -+ crypto_drivers[hid].cc_unqblocked = 0; -+ } -+ -+ crypto_all_kqblocked = !list_empty(&crp_kq); -+ -+ /* As above, but for key ops */ -+ krp = NULL; -+ list_for_each_entry(krpp, &crp_kq, krp_next) { -+ cap = crypto_checkdriver(krpp->krp_hid); -+ if (cap == NULL || cap->cc_dev == NULL) { -+ /* -+ * Operation needs to be migrated, invalidate -+ * the assigned device so it will reselect a -+ * new one below. Propagate the original -+ * crid selection flags if supplied. -+ */ -+ krp->krp_hid = krp->krp_crid & -+ (CRYPTOCAP_F_SOFTWARE|CRYPTOCAP_F_HARDWARE); -+ if (krp->krp_hid == 0) -+ krp->krp_hid = -+ CRYPTOCAP_F_SOFTWARE|CRYPTOCAP_F_HARDWARE; -+ break; -+ } -+ if (!cap->cc_kqblocked) { -+ krp = krpp; -+ break; -+ } -+ } -+ if (krp != NULL) { -+ crypto_all_kqblocked = 0; -+ list_del(&krp->krp_next); -+ crypto_drivers[krp->krp_hid].cc_kqblocked = 1; -+ CRYPTO_Q_UNLOCK(); -+ result = crypto_kinvoke(krp, krp->krp_hid); -+ CRYPTO_Q_LOCK(); -+ if (result == ERESTART) { -+ /* -+ * The driver ran out of resources, mark the -+ * driver ``blocked'' for cryptkop's and put -+ * the request back in the queue. It would -+ * best to put the request back where we got -+ * it but that's hard so for now we put it -+ * at the front. This should be ok; putting -+ * it at the end does not work. -+ */ -+ /* XXX validate sid again? */ -+ list_add(&krp->krp_next, &crp_kq); -+ cryptostats.cs_kblocks++; -+ } else -+ crypto_drivers[krp->krp_hid].cc_kqblocked = 0; -+ } -+ -+ if (submit == NULL && krp == NULL) { -+ /* -+ * Nothing more to be processed. Sleep until we're -+ * woken because there are more ops to process. -+ * This happens either by submission or by a driver -+ * becoming unblocked and notifying us through -+ * crypto_unblock. Note that when we wakeup we -+ * start processing each queue again from the -+ * front. It's not clear that it's important to -+ * preserve this ordering since ops may finish -+ * out of order if dispatched to different devices -+ * and some become blocked while others do not. -+ */ -+ dprintk("%s - sleeping (qe=%d qb=%d kqe=%d kqb=%d)\n", -+ __FUNCTION__, -+ list_empty(&crp_q), crypto_all_qblocked, -+ list_empty(&crp_kq), crypto_all_kqblocked); -+ loopcount = 0; -+ CRYPTO_Q_UNLOCK(); -+ crp_sleep = 1; -+ wait_event_interruptible(cryptoproc_wait, -+ !(list_empty(&crp_q) || crypto_all_qblocked) || -+ !(list_empty(&crp_kq) || crypto_all_kqblocked) || -+ cryptoproc == (pid_t) -1); -+ crp_sleep = 0; -+ if (signal_pending (current)) { -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ spin_lock_irq(¤t->sigmask_lock); -+#endif -+ flush_signals(current); -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ spin_unlock_irq(¤t->sigmask_lock); -+#endif -+ } -+ CRYPTO_Q_LOCK(); -+ dprintk("%s - awake\n", __FUNCTION__); -+ if (cryptoproc == (pid_t) -1) -+ break; -+ cryptostats.cs_intrs++; -+ } else if (loopcount > crypto_max_loopcount) { -+ /* -+ * Give other processes a chance to run if we've -+ * been using the CPU exclusively for a while. -+ */ -+ loopcount = 0; -+ schedule(); -+ } -+ loopcount++; -+ } -+ CRYPTO_Q_UNLOCK(); -+ complete_and_exit(&cryptoproc_exited, 0); -+} -+ -+/* -+ * Crypto returns thread, does callbacks for processed crypto requests. -+ * Callbacks are done here, rather than in the crypto drivers, because -+ * callbacks typically are expensive and would slow interrupt handling. -+ */ -+static int -+crypto_ret_proc(void *arg) -+{ -+ struct cryptop *crpt; -+ struct cryptkop *krpt; -+ unsigned long r_flags; -+ -+ ocf_daemonize("crypto_ret"); -+ -+ CRYPTO_RETQ_LOCK(); -+ for (;;) { -+ /* Harvest return q's for completed ops */ -+ crpt = NULL; -+ if (!list_empty(&crp_ret_q)) -+ crpt = list_entry(crp_ret_q.next, typeof(*crpt), crp_next); -+ if (crpt != NULL) -+ list_del(&crpt->crp_next); -+ -+ krpt = NULL; -+ if (!list_empty(&crp_ret_kq)) -+ krpt = list_entry(crp_ret_kq.next, typeof(*krpt), krp_next); -+ if (krpt != NULL) -+ list_del(&krpt->krp_next); -+ -+ if (crpt != NULL || krpt != NULL) { -+ CRYPTO_RETQ_UNLOCK(); -+ /* -+ * Run callbacks unlocked. -+ */ -+ if (crpt != NULL) -+ crpt->crp_callback(crpt); -+ if (krpt != NULL) -+ krpt->krp_callback(krpt); -+ CRYPTO_RETQ_LOCK(); -+ } else { -+ /* -+ * Nothing more to be processed. Sleep until we're -+ * woken because there are more returns to process. -+ */ -+ dprintk("%s - sleeping\n", __FUNCTION__); -+ CRYPTO_RETQ_UNLOCK(); -+ wait_event_interruptible(cryptoretproc_wait, -+ cryptoretproc == (pid_t) -1 || -+ !list_empty(&crp_ret_q) || -+ !list_empty(&crp_ret_kq)); -+ if (signal_pending (current)) { -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ spin_lock_irq(¤t->sigmask_lock); -+#endif -+ flush_signals(current); -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ spin_unlock_irq(¤t->sigmask_lock); -+#endif -+ } -+ CRYPTO_RETQ_LOCK(); -+ dprintk("%s - awake\n", __FUNCTION__); -+ if (cryptoretproc == (pid_t) -1) { -+ dprintk("%s - EXITING!\n", __FUNCTION__); -+ break; -+ } -+ cryptostats.cs_rets++; -+ } -+ } -+ CRYPTO_RETQ_UNLOCK(); -+ complete_and_exit(&cryptoretproc_exited, 0); -+} -+ -+ -+#if 0 /* should put this into /proc or something */ -+static void -+db_show_drivers(void) -+{ -+ int hid; -+ -+ db_printf("%12s %4s %4s %8s %2s %2s\n" -+ , "Device" -+ , "Ses" -+ , "Kops" -+ , "Flags" -+ , "QB" -+ , "KB" -+ ); -+ for (hid = 0; hid < crypto_drivers_num; hid++) { -+ const struct cryptocap *cap = &crypto_drivers[hid]; -+ if (cap->cc_dev == NULL) -+ continue; -+ db_printf("%-12s %4u %4u %08x %2u %2u\n" -+ , device_get_nameunit(cap->cc_dev) -+ , cap->cc_sessions -+ , cap->cc_koperations -+ , cap->cc_flags -+ , cap->cc_qblocked -+ , cap->cc_kqblocked -+ ); -+ } -+} -+ -+DB_SHOW_COMMAND(crypto, db_show_crypto) -+{ -+ struct cryptop *crp; -+ -+ db_show_drivers(); -+ db_printf("\n"); -+ -+ db_printf("%4s %8s %4s %4s %4s %4s %8s %8s\n", -+ "HID", "Caps", "Ilen", "Olen", "Etype", "Flags", -+ "Desc", "Callback"); -+ TAILQ_FOREACH(crp, &crp_q, crp_next) { -+ db_printf("%4u %08x %4u %4u %4u %04x %8p %8p\n" -+ , (int) CRYPTO_SESID2HID(crp->crp_sid) -+ , (int) CRYPTO_SESID2CAPS(crp->crp_sid) -+ , crp->crp_ilen, crp->crp_olen -+ , crp->crp_etype -+ , crp->crp_flags -+ , crp->crp_desc -+ , crp->crp_callback -+ ); -+ } -+ if (!TAILQ_EMPTY(&crp_ret_q)) { -+ db_printf("\n%4s %4s %4s %8s\n", -+ "HID", "Etype", "Flags", "Callback"); -+ TAILQ_FOREACH(crp, &crp_ret_q, crp_next) { -+ db_printf("%4u %4u %04x %8p\n" -+ , (int) CRYPTO_SESID2HID(crp->crp_sid) -+ , crp->crp_etype -+ , crp->crp_flags -+ , crp->crp_callback -+ ); -+ } -+ } -+} -+ -+DB_SHOW_COMMAND(kcrypto, db_show_kcrypto) -+{ -+ struct cryptkop *krp; -+ -+ db_show_drivers(); -+ db_printf("\n"); -+ -+ db_printf("%4s %5s %4s %4s %8s %4s %8s\n", -+ "Op", "Status", "#IP", "#OP", "CRID", "HID", "Callback"); -+ TAILQ_FOREACH(krp, &crp_kq, krp_next) { -+ db_printf("%4u %5u %4u %4u %08x %4u %8p\n" -+ , krp->krp_op -+ , krp->krp_status -+ , krp->krp_iparams, krp->krp_oparams -+ , krp->krp_crid, krp->krp_hid -+ , krp->krp_callback -+ ); -+ } -+ if (!TAILQ_EMPTY(&crp_ret_q)) { -+ db_printf("%4s %5s %8s %4s %8s\n", -+ "Op", "Status", "CRID", "HID", "Callback"); -+ TAILQ_FOREACH(krp, &crp_ret_kq, krp_next) { -+ db_printf("%4u %5u %08x %4u %8p\n" -+ , krp->krp_op -+ , krp->krp_status -+ , krp->krp_crid, krp->krp_hid -+ , krp->krp_callback -+ ); -+ } -+ } -+} -+#endif -+ -+ -+static int -+crypto_init(void) -+{ -+ int error; -+ -+ dprintk("%s(%p)\n", __FUNCTION__, (void *) crypto_init); -+ -+ if (crypto_initted) -+ return 0; -+ crypto_initted = 1; -+ -+ spin_lock_init(&crypto_drivers_lock); -+ spin_lock_init(&crypto_q_lock); -+ spin_lock_init(&crypto_ret_q_lock); -+ -+ cryptop_zone = kmem_cache_create("cryptop", sizeof(struct cryptop), -+ 0, SLAB_HWCACHE_ALIGN, NULL -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) -+ , NULL -+#endif -+ ); -+ -+ cryptodesc_zone = kmem_cache_create("cryptodesc", sizeof(struct cryptodesc), -+ 0, SLAB_HWCACHE_ALIGN, NULL -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) -+ , NULL -+#endif -+ ); -+ -+ if (cryptodesc_zone == NULL || cryptop_zone == NULL) { -+ printk("crypto: crypto_init cannot setup crypto zones\n"); -+ error = ENOMEM; -+ goto bad; -+ } -+ -+ crypto_drivers_num = CRYPTO_DRIVERS_INITIAL; -+ crypto_drivers = kmalloc(crypto_drivers_num * sizeof(struct cryptocap), -+ GFP_KERNEL); -+ if (crypto_drivers == NULL) { -+ printk("crypto: crypto_init cannot setup crypto drivers\n"); -+ error = ENOMEM; -+ goto bad; -+ } -+ -+ memset(crypto_drivers, 0, crypto_drivers_num * sizeof(struct cryptocap)); -+ -+ init_completion(&cryptoproc_exited); -+ init_completion(&cryptoretproc_exited); -+ -+ cryptoproc = 0; /* to avoid race condition where proc runs first */ -+ cryptoproc = kernel_thread(crypto_proc, NULL, CLONE_FS|CLONE_FILES); -+ if (cryptoproc < 0) { -+ error = cryptoproc; -+ printk("crypto: crypto_init cannot start crypto thread; error %d", -+ error); -+ goto bad; -+ } -+ -+ cryptoretproc = 0; /* to avoid race condition where proc runs first */ -+ cryptoretproc = kernel_thread(crypto_ret_proc, NULL, CLONE_FS|CLONE_FILES); -+ if (cryptoretproc < 0) { -+ error = cryptoretproc; -+ printk("crypto: crypto_init cannot start cryptoret thread; error %d", -+ error); -+ goto bad; -+ } -+ -+ return 0; -+bad: -+ crypto_exit(); -+ return error; -+} -+ -+ -+static void -+crypto_exit(void) -+{ -+ pid_t p; -+ unsigned long d_flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ /* -+ * Terminate any crypto threads. -+ */ -+ -+ CRYPTO_DRIVER_LOCK(); -+ p = cryptoproc; -+ cryptoproc = (pid_t) -1; -+ kill_proc(p, SIGTERM, 1); -+ wake_up_interruptible(&cryptoproc_wait); -+ CRYPTO_DRIVER_UNLOCK(); -+ -+ wait_for_completion(&cryptoproc_exited); -+ -+ CRYPTO_DRIVER_LOCK(); -+ p = cryptoretproc; -+ cryptoretproc = (pid_t) -1; -+ kill_proc(p, SIGTERM, 1); -+ wake_up_interruptible(&cryptoretproc_wait); -+ CRYPTO_DRIVER_UNLOCK(); -+ -+ wait_for_completion(&cryptoretproc_exited); -+ -+ /* XXX flush queues??? */ -+ -+ /* -+ * Reclaim dynamically allocated resources. -+ */ -+ if (crypto_drivers != NULL) -+ kfree(crypto_drivers); -+ -+ if (cryptodesc_zone != NULL) -+ kmem_cache_destroy(cryptodesc_zone); -+ if (cryptop_zone != NULL) -+ kmem_cache_destroy(cryptop_zone); -+} -+ -+ -+EXPORT_SYMBOL(crypto_newsession); -+EXPORT_SYMBOL(crypto_freesession); -+EXPORT_SYMBOL(crypto_get_driverid); -+EXPORT_SYMBOL(crypto_kregister); -+EXPORT_SYMBOL(crypto_register); -+EXPORT_SYMBOL(crypto_unregister); -+EXPORT_SYMBOL(crypto_unregister_all); -+EXPORT_SYMBOL(crypto_unblock); -+EXPORT_SYMBOL(crypto_dispatch); -+EXPORT_SYMBOL(crypto_kdispatch); -+EXPORT_SYMBOL(crypto_freereq); -+EXPORT_SYMBOL(crypto_getreq); -+EXPORT_SYMBOL(crypto_done); -+EXPORT_SYMBOL(crypto_kdone); -+EXPORT_SYMBOL(crypto_getfeat); -+EXPORT_SYMBOL(crypto_userasymcrypto); -+EXPORT_SYMBOL(crypto_getcaps); -+EXPORT_SYMBOL(crypto_find_driver); -+EXPORT_SYMBOL(crypto_find_device_byhid); -+ -+module_init(crypto_init); -+module_exit(crypto_exit); -+ -+MODULE_LICENSE("BSD"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("OCF (OpenBSD Cryptographic Framework)"); -diff -Nur linux-2.6.39.orig/crypto/ocf/cryptocteon/Makefile linux-2.6.39/crypto/ocf/cryptocteon/Makefile ---- linux-2.6.39.orig/crypto/ocf/cryptocteon/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/cryptocteon/Makefile 2011-08-01 14:38:18.000000000 +0200 -@@ -0,0 +1,17 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+obj-$(CONFIG_OCF_CRYPTOCTEON) += cryptocteon.o -+ -+obj ?= . -+EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ -+ -+ifdef CONFIG_OCF_CRYPTOCTEON -+# you need the cavium crypto component installed -+EXTRA_CFLAGS += -I$(ROOTDIR)/prop/include -+endif -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/cryptocteon/cavium_crypto.c linux-2.6.39/crypto/ocf/cryptocteon/cavium_crypto.c ---- linux-2.6.39.orig/crypto/ocf/cryptocteon/cavium_crypto.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/cryptocteon/cavium_crypto.c 2011-08-01 14:38:18.000000000 +0200 -@@ -0,0 +1,2283 @@ -+/* -+ * Copyright (c) 2009 David McCullough -+ * -+ * Copyright (c) 2003-2007 Cavium Networks (support@cavium.com). All rights -+ * reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * 1. Redistributions of source code must retain the above copyright notice, -+ * this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright notice, -+ * this list of conditions and the following disclaimer in the documentation -+ * and/or other materials provided with the distribution. -+ * 3. All advertising materials mentioning features or use of this software -+ * must display the following acknowledgement: -+ * This product includes software developed by Cavium Networks -+ * 4. Cavium Networks' name may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * This Software, including technical data, may be subject to U.S. export -+ * control laws, including the U.S. Export Administration Act and its -+ * associated regulations, and may be subject to export or import regulations -+ * in other countries. You warrant that You will comply strictly in all -+ * respects with all such regulations and acknowledge that you have the -+ * responsibility to obtain licenses to export, re-export or import the -+ * Software. -+ * -+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" AND -+ * WITH ALL FAULTS AND CAVIUM MAKES NO PROMISES, REPRESENTATIONS OR WARRANTIES, -+ * EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO THE -+ * SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR -+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM -+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, -+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF -+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR -+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR -+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. -+*/ -+/****************************************************************************/ -+ -+#include -+#include -+#include "octeon-asm.h" -+ -+/****************************************************************************/ -+ -+extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *); -+extern void octeon_crypto_disable(struct octeon_cop2_state *, unsigned long); -+ -+#define SG_INIT(s, p, i, l) \ -+ { \ -+ (i) = 0; \ -+ (l) = (s)[0].length; \ -+ (p) = (typeof(p)) sg_virt((s)); \ -+ CVMX_PREFETCH0((p)); \ -+ } -+ -+#define SG_CONSUME(s, p, i, l) \ -+ { \ -+ (p)++; \ -+ (l) -= sizeof(*(p)); \ -+ if ((l) < 0) { \ -+ dprintk("%s, %d: l = %d\n", __FILE__, __LINE__, l); \ -+ } else if ((l) == 0) { \ -+ (i)++; \ -+ (l) = (s)[0].length; \ -+ (p) = (typeof(p)) sg_virt(s); \ -+ CVMX_PREFETCH0((p)); \ -+ } \ -+ } -+ -+#define ESP_HEADER_LENGTH 8 -+#define DES_CBC_IV_LENGTH 8 -+#define AES_CBC_IV_LENGTH 16 -+#define ESP_HMAC_LEN 12 -+ -+#define ESP_HEADER_LENGTH 8 -+#define DES_CBC_IV_LENGTH 8 -+ -+/****************************************************************************/ -+ -+#define CVM_LOAD_SHA_UNIT(dat, next) { \ -+ if (next == 0) { \ -+ next = 1; \ -+ CVMX_MT_HSH_DAT (dat, 0); \ -+ } else if (next == 1) { \ -+ next = 2; \ -+ CVMX_MT_HSH_DAT (dat, 1); \ -+ } else if (next == 2) { \ -+ next = 3; \ -+ CVMX_MT_HSH_DAT (dat, 2); \ -+ } else if (next == 3) { \ -+ next = 4; \ -+ CVMX_MT_HSH_DAT (dat, 3); \ -+ } else if (next == 4) { \ -+ next = 5; \ -+ CVMX_MT_HSH_DAT (dat, 4); \ -+ } else if (next == 5) { \ -+ next = 6; \ -+ CVMX_MT_HSH_DAT (dat, 5); \ -+ } else if (next == 6) { \ -+ next = 7; \ -+ CVMX_MT_HSH_DAT (dat, 6); \ -+ } else { \ -+ CVMX_MT_HSH_STARTSHA (dat); \ -+ next = 0; \ -+ } \ -+} -+ -+#define CVM_LOAD2_SHA_UNIT(dat1, dat2, next) { \ -+ if (next == 0) { \ -+ CVMX_MT_HSH_DAT (dat1, 0); \ -+ CVMX_MT_HSH_DAT (dat2, 1); \ -+ next = 2; \ -+ } else if (next == 1) { \ -+ CVMX_MT_HSH_DAT (dat1, 1); \ -+ CVMX_MT_HSH_DAT (dat2, 2); \ -+ next = 3; \ -+ } else if (next == 2) { \ -+ CVMX_MT_HSH_DAT (dat1, 2); \ -+ CVMX_MT_HSH_DAT (dat2, 3); \ -+ next = 4; \ -+ } else if (next == 3) { \ -+ CVMX_MT_HSH_DAT (dat1, 3); \ -+ CVMX_MT_HSH_DAT (dat2, 4); \ -+ next = 5; \ -+ } else if (next == 4) { \ -+ CVMX_MT_HSH_DAT (dat1, 4); \ -+ CVMX_MT_HSH_DAT (dat2, 5); \ -+ next = 6; \ -+ } else if (next == 5) { \ -+ CVMX_MT_HSH_DAT (dat1, 5); \ -+ CVMX_MT_HSH_DAT (dat2, 6); \ -+ next = 7; \ -+ } else if (next == 6) { \ -+ CVMX_MT_HSH_DAT (dat1, 6); \ -+ CVMX_MT_HSH_STARTSHA (dat2); \ -+ next = 0; \ -+ } else { \ -+ CVMX_MT_HSH_STARTSHA (dat1); \ -+ CVMX_MT_HSH_DAT (dat2, 0); \ -+ next = 1; \ -+ } \ -+} -+ -+/****************************************************************************/ -+ -+#define CVM_LOAD_MD5_UNIT(dat, next) { \ -+ if (next == 0) { \ -+ next = 1; \ -+ CVMX_MT_HSH_DAT (dat, 0); \ -+ } else if (next == 1) { \ -+ next = 2; \ -+ CVMX_MT_HSH_DAT (dat, 1); \ -+ } else if (next == 2) { \ -+ next = 3; \ -+ CVMX_MT_HSH_DAT (dat, 2); \ -+ } else if (next == 3) { \ -+ next = 4; \ -+ CVMX_MT_HSH_DAT (dat, 3); \ -+ } else if (next == 4) { \ -+ next = 5; \ -+ CVMX_MT_HSH_DAT (dat, 4); \ -+ } else if (next == 5) { \ -+ next = 6; \ -+ CVMX_MT_HSH_DAT (dat, 5); \ -+ } else if (next == 6) { \ -+ next = 7; \ -+ CVMX_MT_HSH_DAT (dat, 6); \ -+ } else { \ -+ CVMX_MT_HSH_STARTMD5 (dat); \ -+ next = 0; \ -+ } \ -+} -+ -+#define CVM_LOAD2_MD5_UNIT(dat1, dat2, next) { \ -+ if (next == 0) { \ -+ CVMX_MT_HSH_DAT (dat1, 0); \ -+ CVMX_MT_HSH_DAT (dat2, 1); \ -+ next = 2; \ -+ } else if (next == 1) { \ -+ CVMX_MT_HSH_DAT (dat1, 1); \ -+ CVMX_MT_HSH_DAT (dat2, 2); \ -+ next = 3; \ -+ } else if (next == 2) { \ -+ CVMX_MT_HSH_DAT (dat1, 2); \ -+ CVMX_MT_HSH_DAT (dat2, 3); \ -+ next = 4; \ -+ } else if (next == 3) { \ -+ CVMX_MT_HSH_DAT (dat1, 3); \ -+ CVMX_MT_HSH_DAT (dat2, 4); \ -+ next = 5; \ -+ } else if (next == 4) { \ -+ CVMX_MT_HSH_DAT (dat1, 4); \ -+ CVMX_MT_HSH_DAT (dat2, 5); \ -+ next = 6; \ -+ } else if (next == 5) { \ -+ CVMX_MT_HSH_DAT (dat1, 5); \ -+ CVMX_MT_HSH_DAT (dat2, 6); \ -+ next = 7; \ -+ } else if (next == 6) { \ -+ CVMX_MT_HSH_DAT (dat1, 6); \ -+ CVMX_MT_HSH_STARTMD5 (dat2); \ -+ next = 0; \ -+ } else { \ -+ CVMX_MT_HSH_STARTMD5 (dat1); \ -+ CVMX_MT_HSH_DAT (dat2, 0); \ -+ next = 1; \ -+ } \ -+} -+ -+/****************************************************************************/ -+ -+static inline uint64_t -+swap64(uint64_t a) -+{ -+ return ((a >> 56) | -+ (((a >> 48) & 0xfful) << 8) | -+ (((a >> 40) & 0xfful) << 16) | -+ (((a >> 32) & 0xfful) << 24) | -+ (((a >> 24) & 0xfful) << 32) | -+ (((a >> 16) & 0xfful) << 40) | -+ (((a >> 8) & 0xfful) << 48) | (((a >> 0) & 0xfful) << 56)); -+} -+ -+/****************************************************************************/ -+ -+void -+octo_calc_hash(__u8 auth, unsigned char *key, uint64_t *inner, uint64_t *outer) -+{ -+ uint8_t hash_key[64]; -+ uint64_t *key1; -+ register uint64_t xor1 = 0x3636363636363636ULL; -+ register uint64_t xor2 = 0x5c5c5c5c5c5c5c5cULL; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ memset(hash_key, 0, sizeof(hash_key)); -+ memcpy(hash_key, (uint8_t *) key, (auth ? 20 : 16)); -+ key1 = (uint64_t *) hash_key; -+ flags = octeon_crypto_enable(&state); -+ if (auth) { -+ CVMX_MT_HSH_IV(0x67452301EFCDAB89ULL, 0); -+ CVMX_MT_HSH_IV(0x98BADCFE10325476ULL, 1); -+ CVMX_MT_HSH_IV(0xC3D2E1F000000000ULL, 2); -+ } else { -+ CVMX_MT_HSH_IV(0x0123456789ABCDEFULL, 0); -+ CVMX_MT_HSH_IV(0xFEDCBA9876543210ULL, 1); -+ } -+ -+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 0); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 1); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 2); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 3); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 4); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 5); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 6); -+ key1++; -+ if (auth) -+ CVMX_MT_HSH_STARTSHA((*key1 ^ xor1)); -+ else -+ CVMX_MT_HSH_STARTMD5((*key1 ^ xor1)); -+ -+ CVMX_MF_HSH_IV(inner[0], 0); -+ CVMX_MF_HSH_IV(inner[1], 1); -+ if (auth) { -+ inner[2] = 0; -+ CVMX_MF_HSH_IV(((uint64_t *) inner)[2], 2); -+ } -+ -+ memset(hash_key, 0, sizeof(hash_key)); -+ memcpy(hash_key, (uint8_t *) key, (auth ? 20 : 16)); -+ key1 = (uint64_t *) hash_key; -+ if (auth) { -+ CVMX_MT_HSH_IV(0x67452301EFCDAB89ULL, 0); -+ CVMX_MT_HSH_IV(0x98BADCFE10325476ULL, 1); -+ CVMX_MT_HSH_IV(0xC3D2E1F000000000ULL, 2); -+ } else { -+ CVMX_MT_HSH_IV(0x0123456789ABCDEFULL, 0); -+ CVMX_MT_HSH_IV(0xFEDCBA9876543210ULL, 1); -+ } -+ -+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 0); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 1); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 2); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 3); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 4); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 5); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 6); -+ key1++; -+ if (auth) -+ CVMX_MT_HSH_STARTSHA((*key1 ^ xor2)); -+ else -+ CVMX_MT_HSH_STARTMD5((*key1 ^ xor2)); -+ -+ CVMX_MF_HSH_IV(outer[0], 0); -+ CVMX_MF_HSH_IV(outer[1], 1); -+ if (auth) { -+ outer[2] = 0; -+ CVMX_MF_HSH_IV(outer[2], 2); -+ } -+ octeon_crypto_disable(&state, flags); -+ return; -+} -+ -+/****************************************************************************/ -+/* DES functions */ -+ -+int -+octo_des_cbc_encrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ uint64_t *data; -+ int data_i, data_l; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x7) || (crypt_off + crypt_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load 3DES Key */ -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ if (od->octo_encklen == 24) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ } else if (od->octo_encklen == 8) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ -+ CVMX_MT_3DES_IV(* (uint64_t *) ivp); -+ -+ while (crypt_off > 0) { -+ SG_CONSUME(sg, data, data_i, data_l); -+ crypt_off -= 8; -+ } -+ -+ while (crypt_len > 0) { -+ CVMX_MT_3DES_ENC_CBC(*data); -+ CVMX_MF_3DES_RESULT(*data); -+ SG_CONSUME(sg, data, data_i, data_l); -+ crypt_len -= 8; -+ } -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+ -+int -+octo_des_cbc_decrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ uint64_t *data; -+ int data_i, data_l; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x7) || (crypt_off + crypt_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load 3DES Key */ -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ if (od->octo_encklen == 24) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ } else if (od->octo_encklen == 8) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ -+ CVMX_MT_3DES_IV(* (uint64_t *) ivp); -+ -+ while (crypt_off > 0) { -+ SG_CONSUME(sg, data, data_i, data_l); -+ crypt_off -= 8; -+ } -+ -+ while (crypt_len > 0) { -+ CVMX_MT_3DES_DEC_CBC(*data); -+ CVMX_MF_3DES_RESULT(*data); -+ SG_CONSUME(sg, data, data_i, data_l); -+ crypt_len -= 8; -+ } -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+/****************************************************************************/ -+/* AES functions */ -+ -+int -+octo_aes_cbc_encrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ uint64_t *data, *pdata; -+ int data_i, data_l; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x7) || (crypt_off + crypt_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load AES Key */ -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ -+ if (od->octo_encklen == 16) { -+ CVMX_MT_AES_KEY(0x0, 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 24) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 32) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); -+ -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); -+ -+ while (crypt_off > 0) { -+ SG_CONSUME(sg, data, data_i, data_l); -+ crypt_off -= 8; -+ } -+ -+ while (crypt_len > 0) { -+ pdata = data; -+ CVMX_MT_AES_ENC_CBC0(*data); -+ SG_CONSUME(sg, data, data_i, data_l); -+ CVMX_MT_AES_ENC_CBC1(*data); -+ CVMX_MF_AES_RESULT(*pdata, 0); -+ CVMX_MF_AES_RESULT(*data, 1); -+ SG_CONSUME(sg, data, data_i, data_l); -+ crypt_len -= 16; -+ } -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+ -+int -+octo_aes_cbc_decrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ uint64_t *data, *pdata; -+ int data_i, data_l; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x7) || (crypt_off + crypt_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load AES Key */ -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ -+ if (od->octo_encklen == 16) { -+ CVMX_MT_AES_KEY(0x0, 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 24) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 32) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); -+ -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); -+ -+ while (crypt_off > 0) { -+ SG_CONSUME(sg, data, data_i, data_l); -+ crypt_off -= 8; -+ } -+ -+ while (crypt_len > 0) { -+ pdata = data; -+ CVMX_MT_AES_DEC_CBC0(*data); -+ SG_CONSUME(sg, data, data_i, data_l); -+ CVMX_MT_AES_DEC_CBC1(*data); -+ CVMX_MF_AES_RESULT(*pdata, 0); -+ CVMX_MF_AES_RESULT(*data, 1); -+ SG_CONSUME(sg, data, data_i, data_l); -+ crypt_len -= 16; -+ } -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+/****************************************************************************/ -+/* MD5 */ -+ -+int -+octo_null_md5_encrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ uint64_t *data; -+ uint64_t tmp1, tmp2; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || -+ (auth_off & 0x7) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data, data_i, data_l); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* Load MD5 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ -+ while (auth_off > 0) { -+ SG_CONSUME(sg, data, data_i, data_l); -+ auth_off -= 8; -+ } -+ -+ while (auth_len > 0) { -+ CVM_LOAD_MD5_UNIT(*data, next); -+ auth_len -= 8; -+ SG_CONSUME(sg, data, data_i, data_l); -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_MD5_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVMX_ES64(tmp1, ((alen + 64) << 3)); -+ CVM_LOAD_MD5_UNIT(tmp1, next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_ES64(tmp1, ((64 + 16) << 3)); -+ CVMX_MT_HSH_STARTMD5(tmp1); -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data, data_i, data_l); -+ icv_off -= 8; -+ } -+ CVMX_MF_HSH_IV(*data, 0); -+ SG_CONSUME(sg, data, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *(uint32_t *)data = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+/****************************************************************************/ -+/* SHA1 */ -+ -+int -+octo_null_sha1_encrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ uint64_t *data; -+ uint64_t tmp1, tmp2, tmp3; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || -+ (auth_off & 0x7) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data, data_i, data_l); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* Load SHA1 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); -+ -+ while (auth_off > 0) { -+ SG_CONSUME(sg, data, data_i, data_l); -+ auth_off -= 8; -+ } -+ -+ while (auth_len > 0) { -+ CVM_LOAD_SHA_UNIT(*data, next); -+ auth_len -= 8; -+ SG_CONSUME(sg, data, data_i, data_l); -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_MD5_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ tmp3 = 0; -+ CVMX_MF_HSH_IV(tmp3, 2); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ tmp3 |= 0x0000000080000000; -+ CVMX_MT_HSH_DAT(tmp3, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data, data_i, data_l); -+ icv_off -= 8; -+ } -+ CVMX_MF_HSH_IV(*data, 0); -+ SG_CONSUME(sg, data, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *(uint32_t *)data = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+/****************************************************************************/ -+/* DES MD5 */ -+ -+int -+octo_des_cbc_md5_encrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ union { -+ uint32_t data32[2]; -+ uint64_t data64[1]; -+ } mydata; -+ uint64_t *data = &mydata.data64[0]; -+ uint32_t *data32; -+ uint64_t tmp1, tmp2; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || -+ (crypt_len & 0x7) || -+ (auth_len & 0x7) || -+ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data32, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load 3DES Key */ -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ if (od->octo_encklen == 24) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ } else if (od->octo_encklen == 8) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ -+ CVMX_MT_3DES_IV(* (uint64_t *) ivp); -+ -+ /* Load MD5 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ -+ while (crypt_off > 0 && auth_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ crypt_off -= 4; -+ auth_off -= 4; -+ } -+ -+ while (crypt_len > 0 || auth_len > 0) { -+ uint32_t *first = data32; -+ mydata.data32[0] = *first; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata.data32[1] = *data32; -+ if (crypt_off <= 0) { -+ if (crypt_len > 0) { -+ CVMX_MT_3DES_ENC_CBC(*data); -+ CVMX_MF_3DES_RESULT(*data); -+ crypt_len -= 8; -+ } -+ } else -+ crypt_off -= 8; -+ if (auth_off <= 0) { -+ if (auth_len > 0) { -+ CVM_LOAD_MD5_UNIT(*data, next); -+ auth_len -= 8; -+ } -+ } else -+ auth_off -= 8; -+ *first = mydata.data32[0]; -+ *data32 = mydata.data32[1]; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_MD5_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVMX_ES64(tmp1, ((alen + 64) << 3)); -+ CVM_LOAD_MD5_UNIT(tmp1, next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_ES64(tmp1, ((64 + 16) << 3)); -+ CVMX_MT_HSH_STARTMD5(tmp1); -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data32, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ icv_off -= 4; -+ } -+ CVMX_MF_HSH_IV(tmp1, 0); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ SG_CONSUME(sg, data32, data_i, data_l); -+ *data32 = (uint32_t) tmp1; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+int -+octo_des_cbc_md5_decrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ union { -+ uint32_t data32[2]; -+ uint64_t data64[1]; -+ } mydata; -+ uint64_t *data = &mydata.data64[0]; -+ uint32_t *data32; -+ uint64_t tmp1, tmp2; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || -+ (crypt_len & 0x7) || -+ (auth_len & 0x7) || -+ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data32, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load 3DES Key */ -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ if (od->octo_encklen == 24) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ } else if (od->octo_encklen == 8) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ -+ CVMX_MT_3DES_IV(* (uint64_t *) ivp); -+ -+ /* Load MD5 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ -+ while (crypt_off > 0 && auth_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ crypt_off -= 4; -+ auth_off -= 4; -+ } -+ -+ while (crypt_len > 0 || auth_len > 0) { -+ uint32_t *first = data32; -+ mydata.data32[0] = *first; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata.data32[1] = *data32; -+ if (auth_off <= 0) { -+ if (auth_len > 0) { -+ CVM_LOAD_MD5_UNIT(*data, next); -+ auth_len -= 8; -+ } -+ } else -+ auth_off -= 8; -+ if (crypt_off <= 0) { -+ if (crypt_len > 0) { -+ CVMX_MT_3DES_DEC_CBC(*data); -+ CVMX_MF_3DES_RESULT(*data); -+ crypt_len -= 8; -+ } -+ } else -+ crypt_off -= 8; -+ *first = mydata.data32[0]; -+ *data32 = mydata.data32[1]; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_MD5_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVMX_ES64(tmp1, ((alen + 64) << 3)); -+ CVM_LOAD_MD5_UNIT(tmp1, next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_ES64(tmp1, ((64 + 16) << 3)); -+ CVMX_MT_HSH_STARTMD5(tmp1); -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data32, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ icv_off -= 4; -+ } -+ CVMX_MF_HSH_IV(tmp1, 0); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ SG_CONSUME(sg, data32, data_i, data_l); -+ *data32 = (uint32_t) tmp1; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+/****************************************************************************/ -+/* DES SHA */ -+ -+int -+octo_des_cbc_sha1_encrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ union { -+ uint32_t data32[2]; -+ uint64_t data64[1]; -+ } mydata; -+ uint64_t *data = &mydata.data64[0]; -+ uint32_t *data32; -+ uint64_t tmp1, tmp2, tmp3; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || -+ (crypt_len & 0x7) || -+ (auth_len & 0x7) || -+ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data32, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load 3DES Key */ -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ if (od->octo_encklen == 24) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ } else if (od->octo_encklen == 8) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ -+ CVMX_MT_3DES_IV(* (uint64_t *) ivp); -+ -+ /* Load SHA1 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); -+ -+ while (crypt_off > 0 && auth_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ crypt_off -= 4; -+ auth_off -= 4; -+ } -+ -+ while (crypt_len > 0 || auth_len > 0) { -+ uint32_t *first = data32; -+ mydata.data32[0] = *first; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata.data32[1] = *data32; -+ if (crypt_off <= 0) { -+ if (crypt_len > 0) { -+ CVMX_MT_3DES_ENC_CBC(*data); -+ CVMX_MF_3DES_RESULT(*data); -+ crypt_len -= 8; -+ } -+ } else -+ crypt_off -= 8; -+ if (auth_off <= 0) { -+ if (auth_len > 0) { -+ CVM_LOAD_SHA_UNIT(*data, next); -+ auth_len -= 8; -+ } -+ } else -+ auth_off -= 8; -+ *first = mydata.data32[0]; -+ *data32 = mydata.data32[1]; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_SHA_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ tmp3 = 0; -+ CVMX_MF_HSH_IV(tmp3, 2); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ tmp3 |= 0x0000000080000000; -+ CVMX_MT_HSH_DAT(tmp3, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data32, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ icv_off -= 4; -+ } -+ CVMX_MF_HSH_IV(tmp1, 0); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ SG_CONSUME(sg, data32, data_i, data_l); -+ *data32 = (uint32_t) tmp1; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+int -+octo_des_cbc_sha1_decrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ union { -+ uint32_t data32[2]; -+ uint64_t data64[1]; -+ } mydata; -+ uint64_t *data = &mydata.data64[0]; -+ uint32_t *data32; -+ uint64_t tmp1, tmp2, tmp3; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || -+ (crypt_len & 0x7) || -+ (auth_len & 0x7) || -+ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data32, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load 3DES Key */ -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ if (od->octo_encklen == 24) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ } else if (od->octo_encklen == 8) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ -+ CVMX_MT_3DES_IV(* (uint64_t *) ivp); -+ -+ /* Load SHA1 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); -+ -+ while (crypt_off > 0 && auth_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ crypt_off -= 4; -+ auth_off -= 4; -+ } -+ -+ while (crypt_len > 0 || auth_len > 0) { -+ uint32_t *first = data32; -+ mydata.data32[0] = *first; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata.data32[1] = *data32; -+ if (auth_off <= 0) { -+ if (auth_len > 0) { -+ CVM_LOAD_SHA_UNIT(*data, next); -+ auth_len -= 8; -+ } -+ } else -+ auth_off -= 8; -+ if (crypt_off <= 0) { -+ if (crypt_len > 0) { -+ CVMX_MT_3DES_DEC_CBC(*data); -+ CVMX_MF_3DES_RESULT(*data); -+ crypt_len -= 8; -+ } -+ } else -+ crypt_off -= 8; -+ *first = mydata.data32[0]; -+ *data32 = mydata.data32[1]; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_SHA_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ tmp3 = 0; -+ CVMX_MF_HSH_IV(tmp3, 2); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ tmp3 |= 0x0000000080000000; -+ CVMX_MT_HSH_DAT(tmp3, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); -+ /* save the HMAC */ -+ SG_INIT(sg, data32, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ icv_off -= 4; -+ } -+ CVMX_MF_HSH_IV(tmp1, 0); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ SG_CONSUME(sg, data32, data_i, data_l); -+ *data32 = (uint32_t) tmp1; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+/****************************************************************************/ -+/* AES MD5 */ -+ -+int -+octo_aes_cbc_md5_encrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ union { -+ uint32_t data32[2]; -+ uint64_t data64[1]; -+ } mydata[2]; -+ uint64_t *pdata = &mydata[0].data64[0]; -+ uint64_t *data = &mydata[1].data64[0]; -+ uint32_t *data32; -+ uint64_t tmp1, tmp2; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || -+ (crypt_len & 0x7) || -+ (auth_len & 0x7) || -+ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data32, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load AES Key */ -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ -+ if (od->octo_encklen == 16) { -+ CVMX_MT_AES_KEY(0x0, 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 24) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 32) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); -+ -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); -+ -+ /* Load MD5 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ -+ while (crypt_off > 0 && auth_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ crypt_off -= 4; -+ auth_off -= 4; -+ } -+ -+ /* align auth and crypt */ -+ while (crypt_off > 0 && auth_len > 0) { -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVM_LOAD_MD5_UNIT(*pdata, next); -+ crypt_off -= 8; -+ auth_len -= 8; -+ } -+ -+ while (crypt_len > 0) { -+ uint32_t *pdata32[3]; -+ -+ pdata32[0] = data32; -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ -+ pdata32[1] = data32; -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ -+ pdata32[2] = data32; -+ mydata[1].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ -+ mydata[1].data32[1] = *data32; -+ -+ CVMX_MT_AES_ENC_CBC0(*pdata); -+ CVMX_MT_AES_ENC_CBC1(*data); -+ CVMX_MF_AES_RESULT(*pdata, 0); -+ CVMX_MF_AES_RESULT(*data, 1); -+ crypt_len -= 16; -+ -+ if (auth_len > 0) { -+ CVM_LOAD_MD5_UNIT(*pdata, next); -+ auth_len -= 8; -+ } -+ if (auth_len > 0) { -+ CVM_LOAD_MD5_UNIT(*data, next); -+ auth_len -= 8; -+ } -+ -+ *pdata32[0] = mydata[0].data32[0]; -+ *pdata32[1] = mydata[0].data32[1]; -+ *pdata32[2] = mydata[1].data32[0]; -+ *data32 = mydata[1].data32[1]; -+ -+ SG_CONSUME(sg, data32, data_i, data_l); -+ } -+ -+ /* finish any left over hashing */ -+ while (auth_len > 0) { -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVM_LOAD_MD5_UNIT(*pdata, next); -+ auth_len -= 8; -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_MD5_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVMX_ES64(tmp1, ((alen + 64) << 3)); -+ CVM_LOAD_MD5_UNIT(tmp1, next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_ES64(tmp1, ((64 + 16) << 3)); -+ CVMX_MT_HSH_STARTMD5(tmp1); -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data32, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ icv_off -= 4; -+ } -+ CVMX_MF_HSH_IV(tmp1, 0); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ SG_CONSUME(sg, data32, data_i, data_l); -+ *data32 = (uint32_t) tmp1; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+int -+octo_aes_cbc_md5_decrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ union { -+ uint32_t data32[2]; -+ uint64_t data64[1]; -+ } mydata[2]; -+ uint64_t *pdata = &mydata[0].data64[0]; -+ uint64_t *data = &mydata[1].data64[0]; -+ uint32_t *data32; -+ uint64_t tmp1, tmp2; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || -+ (crypt_len & 0x7) || -+ (auth_len & 0x7) || -+ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data32, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load AES Key */ -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ -+ if (od->octo_encklen == 16) { -+ CVMX_MT_AES_KEY(0x0, 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 24) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 32) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); -+ -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); -+ -+ /* Load MD5 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ -+ while (crypt_off > 0 && auth_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ crypt_off -= 4; -+ auth_off -= 4; -+ } -+ -+ /* align auth and crypt */ -+ while (crypt_off > 0 && auth_len > 0) { -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVM_LOAD_MD5_UNIT(*pdata, next); -+ crypt_off -= 8; -+ auth_len -= 8; -+ } -+ -+ while (crypt_len > 0) { -+ uint32_t *pdata32[3]; -+ -+ pdata32[0] = data32; -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ pdata32[1] = data32; -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ pdata32[2] = data32; -+ mydata[1].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[1].data32[1] = *data32; -+ -+ if (auth_len > 0) { -+ CVM_LOAD_MD5_UNIT(*pdata, next); -+ auth_len -= 8; -+ } -+ -+ if (auth_len > 0) { -+ CVM_LOAD_MD5_UNIT(*data, next); -+ auth_len -= 8; -+ } -+ -+ CVMX_MT_AES_DEC_CBC0(*pdata); -+ CVMX_MT_AES_DEC_CBC1(*data); -+ CVMX_MF_AES_RESULT(*pdata, 0); -+ CVMX_MF_AES_RESULT(*data, 1); -+ crypt_len -= 16; -+ -+ *pdata32[0] = mydata[0].data32[0]; -+ *pdata32[1] = mydata[0].data32[1]; -+ *pdata32[2] = mydata[1].data32[0]; -+ *data32 = mydata[1].data32[1]; -+ -+ SG_CONSUME(sg, data32, data_i, data_l); -+ } -+ -+ /* finish left over hash if any */ -+ while (auth_len > 0) { -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVM_LOAD_MD5_UNIT(*pdata, next); -+ auth_len -= 8; -+ } -+ -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_MD5_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVMX_ES64(tmp1, ((alen + 64) << 3)); -+ CVM_LOAD_MD5_UNIT(tmp1, next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_ES64(tmp1, ((64 + 16) << 3)); -+ CVMX_MT_HSH_STARTMD5(tmp1); -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data32, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ icv_off -= 4; -+ } -+ CVMX_MF_HSH_IV(tmp1, 0); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ SG_CONSUME(sg, data32, data_i, data_l); -+ *data32 = (uint32_t) tmp1; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+/****************************************************************************/ -+/* AES SHA1 */ -+ -+int -+octo_aes_cbc_sha1_encrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ union { -+ uint32_t data32[2]; -+ uint64_t data64[1]; -+ } mydata[2]; -+ uint64_t *pdata = &mydata[0].data64[0]; -+ uint64_t *data = &mydata[1].data64[0]; -+ uint32_t *data32; -+ uint64_t tmp1, tmp2, tmp3; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s(a_off=%d a_len=%d c_off=%d c_len=%d icv_off=%d)\n", -+ __FUNCTION__, auth_off, auth_len, crypt_off, crypt_len, icv_off); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || -+ (crypt_len & 0x7) || -+ (auth_len & 0x7) || -+ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data32, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load AES Key */ -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ -+ if (od->octo_encklen == 16) { -+ CVMX_MT_AES_KEY(0x0, 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 24) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 32) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); -+ -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); -+ -+ /* Load SHA IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); -+ -+ while (crypt_off > 0 && auth_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ crypt_off -= 4; -+ auth_off -= 4; -+ } -+ -+ /* align auth and crypt */ -+ while (crypt_off > 0 && auth_len > 0) { -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVM_LOAD_SHA_UNIT(*pdata, next); -+ crypt_off -= 8; -+ auth_len -= 8; -+ } -+ -+ while (crypt_len > 0) { -+ uint32_t *pdata32[3]; -+ -+ pdata32[0] = data32; -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ pdata32[1] = data32; -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ pdata32[2] = data32; -+ mydata[1].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[1].data32[1] = *data32; -+ -+ CVMX_MT_AES_ENC_CBC0(*pdata); -+ CVMX_MT_AES_ENC_CBC1(*data); -+ CVMX_MF_AES_RESULT(*pdata, 0); -+ CVMX_MF_AES_RESULT(*data, 1); -+ crypt_len -= 16; -+ -+ if (auth_len > 0) { -+ CVM_LOAD_SHA_UNIT(*pdata, next); -+ auth_len -= 8; -+ } -+ if (auth_len > 0) { -+ CVM_LOAD_SHA_UNIT(*data, next); -+ auth_len -= 8; -+ } -+ -+ *pdata32[0] = mydata[0].data32[0]; -+ *pdata32[1] = mydata[0].data32[1]; -+ *pdata32[2] = mydata[1].data32[0]; -+ *data32 = mydata[1].data32[1]; -+ -+ SG_CONSUME(sg, data32, data_i, data_l); -+ } -+ -+ /* finish and hashing */ -+ while (auth_len > 0) { -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVM_LOAD_SHA_UNIT(*pdata, next); -+ auth_len -= 8; -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_SHA_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ tmp3 = 0; -+ CVMX_MF_HSH_IV(tmp3, 2); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ tmp3 |= 0x0000000080000000; -+ CVMX_MT_HSH_DAT(tmp3, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_MD5_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data32, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ icv_off -= 4; -+ } -+ CVMX_MF_HSH_IV(tmp1, 0); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ SG_CONSUME(sg, data32, data_i, data_l); -+ *data32 = (uint32_t) tmp1; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+int -+octo_aes_cbc_sha1_decrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ union { -+ uint32_t data32[2]; -+ uint64_t data64[1]; -+ } mydata[2]; -+ uint64_t *pdata = &mydata[0].data64[0]; -+ uint64_t *data = &mydata[1].data64[0]; -+ uint32_t *data32; -+ uint64_t tmp1, tmp2, tmp3; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s(a_off=%d a_len=%d c_off=%d c_len=%d icv_off=%d)\n", -+ __FUNCTION__, auth_off, auth_len, crypt_off, crypt_len, icv_off); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || -+ (crypt_len & 0x7) || -+ (auth_len & 0x7) || -+ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data32, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load AES Key */ -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ -+ if (od->octo_encklen == 16) { -+ CVMX_MT_AES_KEY(0x0, 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 24) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 32) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); -+ -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); -+ -+ /* Load SHA1 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); -+ -+ while (crypt_off > 0 && auth_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ crypt_off -= 4; -+ auth_off -= 4; -+ } -+ -+ /* align auth and crypt */ -+ while (crypt_off > 0 && auth_len > 0) { -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVM_LOAD_SHA_UNIT(*pdata, next); -+ crypt_off -= 8; -+ auth_len -= 8; -+ } -+ -+ while (crypt_len > 0) { -+ uint32_t *pdata32[3]; -+ -+ pdata32[0] = data32; -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ pdata32[1] = data32; -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ pdata32[2] = data32; -+ mydata[1].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[1].data32[1] = *data32; -+ -+ if (auth_len > 0) { -+ CVM_LOAD_SHA_UNIT(*pdata, next); -+ auth_len -= 8; -+ } -+ if (auth_len > 0) { -+ CVM_LOAD_SHA_UNIT(*data, next); -+ auth_len -= 8; -+ } -+ -+ CVMX_MT_AES_DEC_CBC0(*pdata); -+ CVMX_MT_AES_DEC_CBC1(*data); -+ CVMX_MF_AES_RESULT(*pdata, 0); -+ CVMX_MF_AES_RESULT(*data, 1); -+ crypt_len -= 16; -+ -+ *pdata32[0] = mydata[0].data32[0]; -+ *pdata32[1] = mydata[0].data32[1]; -+ *pdata32[2] = mydata[1].data32[0]; -+ *data32 = mydata[1].data32[1]; -+ -+ SG_CONSUME(sg, data32, data_i, data_l); -+ } -+ -+ /* finish and leftover hashing */ -+ while (auth_len > 0) { -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVM_LOAD_SHA_UNIT(*pdata, next); -+ auth_len -= 8; -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_SHA_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ tmp3 = 0; -+ CVMX_MF_HSH_IV(tmp3, 2); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ tmp3 |= 0x0000000080000000; -+ CVMX_MT_HSH_DAT(tmp3, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_MD5_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data32, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ icv_off -= 4; -+ } -+ CVMX_MF_HSH_IV(tmp1, 0); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ SG_CONSUME(sg, data32, data_i, data_l); -+ *data32 = (uint32_t) tmp1; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+/****************************************************************************/ -diff -Nur linux-2.6.39.orig/crypto/ocf/cryptocteon/cryptocteon.c linux-2.6.39/crypto/ocf/cryptocteon/cryptocteon.c ---- linux-2.6.39.orig/crypto/ocf/cryptocteon/cryptocteon.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/cryptocteon/cryptocteon.c 2011-08-01 14:38:18.000000000 +0200 -@@ -0,0 +1,574 @@ -+/* -+ * Octeon Crypto for OCF -+ * -+ * Written by David McCullough -+ * Copyright (C) 2009-2010 David McCullough -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ * --------------------------------------------------------------------------- -+ */ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+struct { -+ softc_device_decl sc_dev; -+} octo_softc; -+ -+#define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK) -+ -+struct octo_sess { -+ int octo_encalg; -+ #define MAX_CIPHER_KEYLEN 64 -+ char octo_enckey[MAX_CIPHER_KEYLEN]; -+ int octo_encklen; -+ -+ int octo_macalg; -+ #define MAX_HASH_KEYLEN 64 -+ char octo_mackey[MAX_HASH_KEYLEN]; -+ int octo_macklen; -+ int octo_mackey_set; -+ -+ int octo_mlen; -+ int octo_ivsize; -+ -+#if 0 -+ int (*octo_decrypt)(struct scatterlist *sg, int sg_len, -+ uint8_t *key, int key_len, uint8_t * iv, -+ uint64_t *hminner, uint64_t *hmouter); -+ -+ int (*octo_encrypt)(struct scatterlist *sg, int sg_len, -+ uint8_t *key, int key_len, uint8_t * iv, -+ uint64_t *hminner, uint64_t *hmouter); -+#else -+ int (*octo_encrypt)(struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp); -+ int (*octo_decrypt)(struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp); -+#endif -+ -+ uint64_t octo_hminner[3]; -+ uint64_t octo_hmouter[3]; -+}; -+ -+int32_t octo_id = -1; -+module_param(octo_id, int, 0444); -+MODULE_PARM_DESC(octo_id, "Read-Only OCF ID for cryptocteon driver"); -+ -+static struct octo_sess **octo_sessions = NULL; -+static u_int32_t octo_sesnum = 0; -+ -+static int octo_process(device_t, struct cryptop *, int); -+static int octo_newsession(device_t, u_int32_t *, struct cryptoini *); -+static int octo_freesession(device_t, u_int64_t); -+ -+static device_method_t octo_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, octo_newsession), -+ DEVMETHOD(cryptodev_freesession,octo_freesession), -+ DEVMETHOD(cryptodev_process, octo_process), -+}; -+ -+#define debug octo_debug -+int octo_debug = 0; -+module_param(octo_debug, int, 0644); -+MODULE_PARM_DESC(octo_debug, "Enable debug"); -+ -+ -+#include "cavium_crypto.c" -+ -+ -+/* -+ * Generate a new octo session. We artifically limit it to a single -+ * hash/cipher or hash-cipher combo just to make it easier, most callers -+ * do not expect more than this anyway. -+ */ -+static int -+octo_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) -+{ -+ struct cryptoini *c, *encini = NULL, *macini = NULL; -+ struct octo_sess **ocd; -+ int i; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid == NULL || cri == NULL) { -+ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ /* -+ * To keep it simple, we only handle hash, cipher or hash/cipher in a -+ * session, you cannot currently do multiple ciphers/hashes in one -+ * session even though it would be possibel to code this driver to -+ * handle it. -+ */ -+ for (i = 0, c = cri; c && i < 2; i++) { -+ if (c->cri_alg == CRYPTO_MD5_HMAC || -+ c->cri_alg == CRYPTO_SHA1_HMAC || -+ c->cri_alg == CRYPTO_NULL_HMAC) { -+ if (macini) { -+ break; -+ } -+ macini = c; -+ } -+ if (c->cri_alg == CRYPTO_DES_CBC || -+ c->cri_alg == CRYPTO_3DES_CBC || -+ c->cri_alg == CRYPTO_AES_CBC || -+ c->cri_alg == CRYPTO_NULL_CBC) { -+ if (encini) { -+ break; -+ } -+ encini = c; -+ } -+ c = c->cri_next; -+ } -+ if (!macini && !encini) { -+ dprintk("%s,%d - EINVAL bad cipher/hash or combination\n", -+ __FILE__, __LINE__); -+ return EINVAL; -+ } -+ if (c) { -+ dprintk("%s,%d - EINVAL cannot handle chained cipher/hash combos\n", -+ __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ /* -+ * So we have something we can do, lets setup the session -+ */ -+ -+ if (octo_sessions) { -+ for (i = 1; i < octo_sesnum; i++) -+ if (octo_sessions[i] == NULL) -+ break; -+ } else -+ i = 1; /* NB: to silence compiler warning */ -+ -+ if (octo_sessions == NULL || i == octo_sesnum) { -+ if (octo_sessions == NULL) { -+ i = 1; /* We leave octo_sessions[0] empty */ -+ octo_sesnum = CRYPTO_SW_SESSIONS; -+ } else -+ octo_sesnum *= 2; -+ -+ ocd = kmalloc(octo_sesnum * sizeof(struct octo_sess *), SLAB_ATOMIC); -+ if (ocd == NULL) { -+ /* Reset session number */ -+ if (octo_sesnum == CRYPTO_SW_SESSIONS) -+ octo_sesnum = 0; -+ else -+ octo_sesnum /= 2; -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memset(ocd, 0, octo_sesnum * sizeof(struct octo_sess *)); -+ -+ /* Copy existing sessions */ -+ if (octo_sessions) { -+ memcpy(ocd, octo_sessions, -+ (octo_sesnum / 2) * sizeof(struct octo_sess *)); -+ kfree(octo_sessions); -+ } -+ -+ octo_sessions = ocd; -+ } -+ -+ ocd = &octo_sessions[i]; -+ *sid = i; -+ -+ -+ *ocd = (struct octo_sess *) kmalloc(sizeof(struct octo_sess), SLAB_ATOMIC); -+ if (*ocd == NULL) { -+ octo_freesession(NULL, i); -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memset(*ocd, 0, sizeof(struct octo_sess)); -+ -+ if (encini && encini->cri_key) { -+ (*ocd)->octo_encklen = (encini->cri_klen + 7) / 8; -+ memcpy((*ocd)->octo_enckey, encini->cri_key, (*ocd)->octo_encklen); -+ } -+ -+ if (macini && macini->cri_key) { -+ (*ocd)->octo_macklen = (macini->cri_klen + 7) / 8; -+ memcpy((*ocd)->octo_mackey, macini->cri_key, (*ocd)->octo_macklen); -+ } -+ -+ (*ocd)->octo_mlen = 0; -+ if (encini && encini->cri_mlen) -+ (*ocd)->octo_mlen = encini->cri_mlen; -+ else if (macini && macini->cri_mlen) -+ (*ocd)->octo_mlen = macini->cri_mlen; -+ else -+ (*ocd)->octo_mlen = 12; -+ -+ /* -+ * point c at the enc if it exists, otherwise the mac -+ */ -+ c = encini ? encini : macini; -+ -+ switch (c->cri_alg) { -+ case CRYPTO_DES_CBC: -+ case CRYPTO_3DES_CBC: -+ (*ocd)->octo_ivsize = 8; -+ switch (macini ? macini->cri_alg : -1) { -+ case CRYPTO_MD5_HMAC: -+ (*ocd)->octo_encrypt = octo_des_cbc_md5_encrypt; -+ (*ocd)->octo_decrypt = octo_des_cbc_md5_decrypt; -+ octo_calc_hash(0, macini->cri_key, (*ocd)->octo_hminner, -+ (*ocd)->octo_hmouter); -+ break; -+ case CRYPTO_SHA1_HMAC: -+ (*ocd)->octo_encrypt = octo_des_cbc_sha1_encrypt; -+ (*ocd)->octo_decrypt = octo_des_cbc_sha1_encrypt; -+ octo_calc_hash(1, macini->cri_key, (*ocd)->octo_hminner, -+ (*ocd)->octo_hmouter); -+ break; -+ case -1: -+ (*ocd)->octo_encrypt = octo_des_cbc_encrypt; -+ (*ocd)->octo_decrypt = octo_des_cbc_decrypt; -+ break; -+ default: -+ octo_freesession(NULL, i); -+ dprintk("%s,%d: EINVALn", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ break; -+ case CRYPTO_AES_CBC: -+ (*ocd)->octo_ivsize = 16; -+ switch (macini ? macini->cri_alg : -1) { -+ case CRYPTO_MD5_HMAC: -+ (*ocd)->octo_encrypt = octo_aes_cbc_md5_encrypt; -+ (*ocd)->octo_decrypt = octo_aes_cbc_md5_decrypt; -+ octo_calc_hash(0, macini->cri_key, (*ocd)->octo_hminner, -+ (*ocd)->octo_hmouter); -+ break; -+ case CRYPTO_SHA1_HMAC: -+ (*ocd)->octo_encrypt = octo_aes_cbc_sha1_encrypt; -+ (*ocd)->octo_decrypt = octo_aes_cbc_sha1_decrypt; -+ octo_calc_hash(1, macini->cri_key, (*ocd)->octo_hminner, -+ (*ocd)->octo_hmouter); -+ break; -+ case -1: -+ (*ocd)->octo_encrypt = octo_aes_cbc_encrypt; -+ (*ocd)->octo_decrypt = octo_aes_cbc_decrypt; -+ break; -+ default: -+ octo_freesession(NULL, i); -+ dprintk("%s,%d: EINVALn", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ break; -+ case CRYPTO_MD5_HMAC: -+ (*ocd)->octo_encrypt = octo_null_md5_encrypt; -+ (*ocd)->octo_decrypt = octo_null_md5_encrypt; -+ octo_calc_hash(0, macini->cri_key, (*ocd)->octo_hminner, -+ (*ocd)->octo_hmouter); -+ break; -+ case CRYPTO_SHA1_HMAC: -+ (*ocd)->octo_encrypt = octo_null_sha1_encrypt; -+ (*ocd)->octo_decrypt = octo_null_sha1_encrypt; -+ octo_calc_hash(1, macini->cri_key, (*ocd)->octo_hminner, -+ (*ocd)->octo_hmouter); -+ break; -+ default: -+ octo_freesession(NULL, i); -+ dprintk("%s,%d: EINVALn", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ (*ocd)->octo_encalg = encini ? encini->cri_alg : -1; -+ (*ocd)->octo_macalg = macini ? macini->cri_alg : -1; -+ -+ return 0; -+} -+ -+/* -+ * Free a session. -+ */ -+static int -+octo_freesession(device_t dev, u_int64_t tid) -+{ -+ u_int32_t sid = CRYPTO_SESID2LID(tid); -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid > octo_sesnum || octo_sessions == NULL || -+ octo_sessions[sid] == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return(EINVAL); -+ } -+ -+ /* Silently accept and return */ -+ if (sid == 0) -+ return(0); -+ -+ if (octo_sessions[sid]) -+ kfree(octo_sessions[sid]); -+ octo_sessions[sid] = NULL; -+ return 0; -+} -+ -+/* -+ * Process a request. -+ */ -+static int -+octo_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ struct cryptodesc *crd; -+ struct octo_sess *od; -+ u_int32_t lid; -+#define SCATTERLIST_MAX 16 -+ struct scatterlist sg[SCATTERLIST_MAX]; -+ int sg_num, sg_len; -+ struct sk_buff *skb = NULL; -+ struct uio *uiop = NULL; -+ struct cryptodesc *enccrd = NULL, *maccrd = NULL; -+ unsigned char *ivp = NULL; -+ unsigned char iv_data[HASH_MAX_LEN]; -+ int auth_off = 0, auth_len = 0, crypt_off = 0, crypt_len = 0, icv_off = 0; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ /* Sanity check */ -+ if (crp == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ crp->crp_etype = 0; -+ -+ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ lid = crp->crp_sid & 0xffffffff; -+ if (lid >= octo_sesnum || lid == 0 || octo_sessions == NULL || -+ octo_sessions[lid] == NULL) { -+ crp->crp_etype = ENOENT; -+ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); -+ goto done; -+ } -+ od = octo_sessions[lid]; -+ -+ /* -+ * do some error checking outside of the loop for SKB and IOV processing -+ * this leaves us with valid skb or uiop pointers for later -+ */ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ skb = (struct sk_buff *) crp->crp_buf; -+ if (skb_shinfo(skb)->nr_frags >= SCATTERLIST_MAX) { -+ printk("%s,%d: %d nr_frags > SCATTERLIST_MAX", __FILE__, __LINE__, -+ skb_shinfo(skb)->nr_frags); -+ goto done; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ uiop = (struct uio *) crp->crp_buf; -+ if (uiop->uio_iovcnt > SCATTERLIST_MAX) { -+ printk("%s,%d: %d uio_iovcnt > SCATTERLIST_MAX", __FILE__, __LINE__, -+ uiop->uio_iovcnt); -+ goto done; -+ } -+ } -+ -+ /* point our enccrd and maccrd appropriately */ -+ crd = crp->crp_desc; -+ if (crd->crd_alg == od->octo_encalg) enccrd = crd; -+ if (crd->crd_alg == od->octo_macalg) maccrd = crd; -+ crd = crd->crd_next; -+ if (crd) { -+ if (crd->crd_alg == od->octo_encalg) enccrd = crd; -+ if (crd->crd_alg == od->octo_macalg) maccrd = crd; -+ crd = crd->crd_next; -+ } -+ if (crd) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: ENOENT - descriptors do not match session\n", -+ __FILE__, __LINE__); -+ goto done; -+ } -+ -+ if (enccrd) { -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) { -+ ivp = enccrd->crd_iv; -+ } else { -+ ivp = iv_data; -+ crypto_copydata(crp->crp_flags, crp->crp_buf, -+ enccrd->crd_inject, od->octo_ivsize, (caddr_t) ivp); -+ } -+ -+ if (maccrd) { -+ auth_off = maccrd->crd_skip; -+ auth_len = maccrd->crd_len; -+ icv_off = maccrd->crd_inject; -+ } -+ -+ crypt_off = enccrd->crd_skip; -+ crypt_len = enccrd->crd_len; -+ } else { /* if (maccrd) */ -+ auth_off = maccrd->crd_skip; -+ auth_len = maccrd->crd_len; -+ icv_off = maccrd->crd_inject; -+ } -+ -+ -+ /* -+ * setup the SG list to cover the buffer -+ */ -+ memset(sg, 0, sizeof(sg)); -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ int i, len; -+ -+ sg_num = 0; -+ sg_len = 0; -+ -+ len = skb_headlen(skb); -+ sg_set_page(&sg[sg_num], virt_to_page(skb->data), len, -+ offset_in_page(skb->data)); -+ sg_len += len; -+ sg_num++; -+ -+ for (i = 0; i < skb_shinfo(skb)->nr_frags && sg_num < SCATTERLIST_MAX; -+ i++) { -+ len = skb_shinfo(skb)->frags[i].size; -+ sg_set_page(&sg[sg_num], skb_shinfo(skb)->frags[i].page, -+ len, skb_shinfo(skb)->frags[i].page_offset); -+ sg_len += len; -+ sg_num++; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ int len; -+ -+ sg_len = 0; -+ for (sg_num = 0; sg_len < crp->crp_ilen && -+ sg_num < uiop->uio_iovcnt && -+ sg_num < SCATTERLIST_MAX; sg_num++) { -+ len = uiop->uio_iov[sg_num].iov_len; -+ sg_set_page(&sg[sg_num], -+ virt_to_page(uiop->uio_iov[sg_num].iov_base), len, -+ offset_in_page(uiop->uio_iov[sg_num].iov_base)); -+ sg_len += len; -+ } -+ } else { -+ sg_len = crp->crp_ilen; -+ sg_set_page(&sg[0], virt_to_page(crp->crp_buf), sg_len, -+ offset_in_page(crp->crp_buf)); -+ sg_num = 1; -+ } -+ -+ -+ /* -+ * setup a new explicit key -+ */ -+ if (enccrd) { -+ if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) { -+ od->octo_encklen = (enccrd->crd_klen + 7) / 8; -+ memcpy(od->octo_enckey, enccrd->crd_key, od->octo_encklen); -+ } -+ } -+ if (maccrd) { -+ if (maccrd->crd_flags & CRD_F_KEY_EXPLICIT) { -+ od->octo_macklen = (maccrd->crd_klen + 7) / 8; -+ memcpy(od->octo_mackey, maccrd->crd_key, od->octo_macklen); -+ od->octo_mackey_set = 0; -+ } -+ if (!od->octo_mackey_set) { -+ octo_calc_hash(maccrd->crd_alg == CRYPTO_MD5_HMAC ? 0 : 1, -+ maccrd->crd_key, od->octo_hminner, od->octo_hmouter); -+ od->octo_mackey_set = 1; -+ } -+ } -+ -+ -+ if (!enccrd || (enccrd->crd_flags & CRD_F_ENCRYPT)) -+ (*od->octo_encrypt)(od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ else -+ (*od->octo_decrypt)(od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ -+done: -+ crypto_done(crp); -+ return 0; -+} -+ -+static int -+cryptocteon_init(void) -+{ -+ dprintk("%s(%p)\n", __FUNCTION__, cryptocteon_init); -+ -+ softc_device_init(&octo_softc, "cryptocteon", 0, octo_methods); -+ -+ octo_id = crypto_get_driverid(softc_get_device(&octo_softc), -+ CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SYNC); -+ if (octo_id < 0) { -+ printk("Cryptocteon device cannot initialize!"); -+ return -ENODEV; -+ } -+ -+ crypto_register(octo_id, CRYPTO_MD5_HMAC, 0,0); -+ crypto_register(octo_id, CRYPTO_SHA1_HMAC, 0,0); -+ //crypto_register(octo_id, CRYPTO_MD5, 0,0); -+ //crypto_register(octo_id, CRYPTO_SHA1, 0,0); -+ crypto_register(octo_id, CRYPTO_DES_CBC, 0,0); -+ crypto_register(octo_id, CRYPTO_3DES_CBC, 0,0); -+ crypto_register(octo_id, CRYPTO_AES_CBC, 0,0); -+ -+ return(0); -+} -+ -+static void -+cryptocteon_exit(void) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ crypto_unregister_all(octo_id); -+ octo_id = -1; -+} -+ -+module_init(cryptocteon_init); -+module_exit(cryptocteon_exit); -+ -+MODULE_LICENSE("BSD"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("Cryptocteon (OCF module for Cavium OCTEON crypto)"); -diff -Nur linux-2.6.39.orig/crypto/ocf/cryptodev.c linux-2.6.39/crypto/ocf/cryptodev.c ---- linux-2.6.39.orig/crypto/ocf/cryptodev.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/cryptodev.c 2011-08-01 14:38:54.000000000 +0200 -@@ -0,0 +1,1057 @@ -+/* $OpenBSD: cryptodev.c,v 1.52 2002/06/19 07:22:46 deraadt Exp $ */ -+ -+/*- -+ * Linux port done by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * The license and original author are listed below. -+ * -+ * Copyright (c) 2001 Theo de Raadt -+ * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored in part by the Defense Advanced Research Projects -+ * Agency (DARPA) and Air Force Research Laboratory, Air Force -+ * Materiel Command, USAF, under agreement number F30602-01-2-0537. -+ * -+__FBSDID("$FreeBSD: src/sys/opencrypto/cryptodev.c,v 1.34 2007/05/09 19:37:02 gnn Exp $"); -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+extern asmlinkage long sys_dup(unsigned int fildes); -+ -+#define debug cryptodev_debug -+int cryptodev_debug = 0; -+module_param(cryptodev_debug, int, 0644); -+MODULE_PARM_DESC(cryptodev_debug, "Enable cryptodev debug"); -+ -+struct csession_info { -+ u_int16_t blocksize; -+ u_int16_t minkey, maxkey; -+ -+ u_int16_t keysize; -+ /* u_int16_t hashsize; */ -+ u_int16_t authsize; -+ u_int16_t authkey; -+ /* u_int16_t ctxsize; */ -+}; -+ -+struct csession { -+ struct list_head list; -+ u_int64_t sid; -+ u_int32_t ses; -+ -+ wait_queue_head_t waitq; -+ -+ u_int32_t cipher; -+ -+ u_int32_t mac; -+ -+ caddr_t key; -+ int keylen; -+ u_char tmp_iv[EALG_MAX_BLOCK_LEN]; -+ -+ caddr_t mackey; -+ int mackeylen; -+ -+ struct csession_info info; -+ -+ struct iovec iovec; -+ struct uio uio; -+ int error; -+}; -+ -+struct fcrypt { -+ struct list_head csessions; -+ int sesn; -+}; -+ -+static struct csession *csefind(struct fcrypt *, u_int); -+static int csedelete(struct fcrypt *, struct csession *); -+static struct csession *cseadd(struct fcrypt *, struct csession *); -+static struct csession *csecreate(struct fcrypt *, u_int64_t, -+ struct cryptoini *crie, struct cryptoini *cria, struct csession_info *); -+static int csefree(struct csession *); -+ -+static int cryptodev_op(struct csession *, struct crypt_op *); -+static int cryptodev_key(struct crypt_kop *); -+static int cryptodev_find(struct crypt_find_op *); -+ -+static int cryptodev_cb(void *); -+static int cryptodev_open(struct inode *inode, struct file *filp); -+ -+/* -+ * Check a crypto identifier to see if it requested -+ * a valid crid and it's capabilities match. -+ */ -+static int -+checkcrid(int crid) -+{ -+ int hid = crid & ~(CRYPTOCAP_F_SOFTWARE | CRYPTOCAP_F_HARDWARE); -+ int typ = crid & (CRYPTOCAP_F_SOFTWARE | CRYPTOCAP_F_HARDWARE); -+ int caps = 0; -+ -+ /* if the user hasn't selected a driver, then just call newsession */ -+ if (hid == 0 && typ != 0) -+ return 0; -+ -+ caps = crypto_getcaps(hid); -+ -+ /* didn't find anything with capabilities */ -+ if (caps == 0) { -+ dprintk("%s: hid=%x typ=%x not matched\n", __FUNCTION__, hid, typ); -+ return EINVAL; -+ } -+ -+ /* the user didn't specify SW or HW, so the driver is ok */ -+ if (typ == 0) -+ return 0; -+ -+ /* if the type specified didn't match */ -+ if (typ != (caps & (CRYPTOCAP_F_SOFTWARE | CRYPTOCAP_F_HARDWARE))) { -+ dprintk("%s: hid=%x typ=%x caps=%x not matched\n", __FUNCTION__, -+ hid, typ, caps); -+ return EINVAL; -+ } -+ -+ return 0; -+} -+ -+static int -+cryptodev_op(struct csession *cse, struct crypt_op *cop) -+{ -+ struct cryptop *crp = NULL; -+ struct cryptodesc *crde = NULL, *crda = NULL; -+ int error = 0; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (cop->len > CRYPTO_MAX_DATA_LEN) { -+ dprintk("%s: %d > %d\n", __FUNCTION__, cop->len, CRYPTO_MAX_DATA_LEN); -+ return (E2BIG); -+ } -+ -+ if (cse->info.blocksize && (cop->len % cse->info.blocksize) != 0) { -+ dprintk("%s: blocksize=%d len=%d\n", __FUNCTION__, cse->info.blocksize, -+ cop->len); -+ return (EINVAL); -+ } -+ -+ cse->uio.uio_iov = &cse->iovec; -+ cse->uio.uio_iovcnt = 1; -+ cse->uio.uio_offset = 0; -+#if 0 -+ cse->uio.uio_resid = cop->len; -+ cse->uio.uio_segflg = UIO_SYSSPACE; -+ cse->uio.uio_rw = UIO_WRITE; -+ cse->uio.uio_td = td; -+#endif -+ cse->uio.uio_iov[0].iov_len = cop->len; -+ if (cse->info.authsize) -+ cse->uio.uio_iov[0].iov_len += cse->info.authsize; -+ cse->uio.uio_iov[0].iov_base = kmalloc(cse->uio.uio_iov[0].iov_len, -+ GFP_KERNEL); -+ -+ if (cse->uio.uio_iov[0].iov_base == NULL) { -+ dprintk("%s: iov_base kmalloc(%d) failed\n", __FUNCTION__, -+ (int)cse->uio.uio_iov[0].iov_len); -+ return (ENOMEM); -+ } -+ -+ crp = crypto_getreq((cse->info.blocksize != 0) + (cse->info.authsize != 0)); -+ if (crp == NULL) { -+ dprintk("%s: ENOMEM\n", __FUNCTION__); -+ error = ENOMEM; -+ goto bail; -+ } -+ -+ if (cse->info.authsize && cse->info.blocksize) { -+ if (cop->op == COP_ENCRYPT) { -+ crde = crp->crp_desc; -+ crda = crde->crd_next; -+ } else { -+ crda = crp->crp_desc; -+ crde = crda->crd_next; -+ } -+ } else if (cse->info.authsize) { -+ crda = crp->crp_desc; -+ } else if (cse->info.blocksize) { -+ crde = crp->crp_desc; -+ } else { -+ dprintk("%s: bad request\n", __FUNCTION__); -+ error = EINVAL; -+ goto bail; -+ } -+ -+ if ((error = copy_from_user(cse->uio.uio_iov[0].iov_base, cop->src, -+ cop->len))) { -+ dprintk("%s: bad copy\n", __FUNCTION__); -+ goto bail; -+ } -+ -+ if (crda) { -+ crda->crd_skip = 0; -+ crda->crd_len = cop->len; -+ crda->crd_inject = cop->len; -+ -+ crda->crd_alg = cse->mac; -+ crda->crd_key = cse->mackey; -+ crda->crd_klen = cse->mackeylen * 8; -+ } -+ -+ if (crde) { -+ if (cop->op == COP_ENCRYPT) -+ crde->crd_flags |= CRD_F_ENCRYPT; -+ else -+ crde->crd_flags &= ~CRD_F_ENCRYPT; -+ crde->crd_len = cop->len; -+ crde->crd_inject = 0; -+ -+ crde->crd_alg = cse->cipher; -+ crde->crd_key = cse->key; -+ crde->crd_klen = cse->keylen * 8; -+ } -+ -+ crp->crp_ilen = cse->uio.uio_iov[0].iov_len; -+ crp->crp_flags = CRYPTO_F_IOV | CRYPTO_F_CBIMM -+ | (cop->flags & COP_F_BATCH); -+ crp->crp_buf = (caddr_t)&cse->uio; -+ crp->crp_callback = (int (*) (struct cryptop *)) cryptodev_cb; -+ crp->crp_sid = cse->sid; -+ crp->crp_opaque = (void *)cse; -+ -+ if (cop->iv) { -+ if (crde == NULL) { -+ error = EINVAL; -+ dprintk("%s no crde\n", __FUNCTION__); -+ goto bail; -+ } -+ if (cse->cipher == CRYPTO_ARC4) { /* XXX use flag? */ -+ error = EINVAL; -+ dprintk("%s arc4 with IV\n", __FUNCTION__); -+ goto bail; -+ } -+ if ((error = copy_from_user(cse->tmp_iv, cop->iv, -+ cse->info.blocksize))) { -+ dprintk("%s bad iv copy\n", __FUNCTION__); -+ goto bail; -+ } -+ memcpy(crde->crd_iv, cse->tmp_iv, cse->info.blocksize); -+ crde->crd_flags |= CRD_F_IV_EXPLICIT | CRD_F_IV_PRESENT; -+ crde->crd_skip = 0; -+ } else if (cse->cipher == CRYPTO_ARC4) { /* XXX use flag? */ -+ crde->crd_skip = 0; -+ } else if (crde) { -+ crde->crd_flags |= CRD_F_IV_PRESENT; -+ crde->crd_skip = cse->info.blocksize; -+ crde->crd_len -= cse->info.blocksize; -+ } -+ -+ if (cop->mac && crda == NULL) { -+ error = EINVAL; -+ dprintk("%s no crda\n", __FUNCTION__); -+ goto bail; -+ } -+ -+ /* -+ * Let the dispatch run unlocked, then, interlock against the -+ * callback before checking if the operation completed and going -+ * to sleep. This insures drivers don't inherit our lock which -+ * results in a lock order reversal between crypto_dispatch forced -+ * entry and the crypto_done callback into us. -+ */ -+ error = crypto_dispatch(crp); -+ if (error) { -+ dprintk("%s error in crypto_dispatch\n", __FUNCTION__); -+ goto bail; -+ } -+ -+ dprintk("%s about to WAIT\n", __FUNCTION__); -+ /* -+ * we really need to wait for driver to complete to maintain -+ * state, luckily interrupts will be remembered -+ */ -+ do { -+ error = wait_event_interruptible(crp->crp_waitq, -+ ((crp->crp_flags & CRYPTO_F_DONE) != 0)); -+ /* -+ * we can't break out of this loop or we will leave behind -+ * a huge mess, however, staying here means if your driver -+ * is broken user applications can hang and not be killed. -+ * The solution, fix your driver :-) -+ */ -+ if (error) { -+ schedule(); -+ error = 0; -+ } -+ } while ((crp->crp_flags & CRYPTO_F_DONE) == 0); -+ dprintk("%s finished WAITING error=%d\n", __FUNCTION__, error); -+ -+ if (crp->crp_etype != 0) { -+ error = crp->crp_etype; -+ dprintk("%s error in crp processing\n", __FUNCTION__); -+ goto bail; -+ } -+ -+ if (cse->error) { -+ error = cse->error; -+ dprintk("%s error in cse processing\n", __FUNCTION__); -+ goto bail; -+ } -+ -+ if (cop->dst && (error = copy_to_user(cop->dst, -+ cse->uio.uio_iov[0].iov_base, cop->len))) { -+ dprintk("%s bad dst copy\n", __FUNCTION__); -+ goto bail; -+ } -+ -+ if (cop->mac && -+ (error=copy_to_user(cop->mac, -+ (caddr_t)cse->uio.uio_iov[0].iov_base + cop->len, -+ cse->info.authsize))) { -+ dprintk("%s bad mac copy\n", __FUNCTION__); -+ goto bail; -+ } -+ -+bail: -+ if (crp) -+ crypto_freereq(crp); -+ if (cse->uio.uio_iov[0].iov_base) -+ kfree(cse->uio.uio_iov[0].iov_base); -+ -+ return (error); -+} -+ -+static int -+cryptodev_cb(void *op) -+{ -+ struct cryptop *crp = (struct cryptop *) op; -+ struct csession *cse = (struct csession *)crp->crp_opaque; -+ int error; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ error = crp->crp_etype; -+ if (error == EAGAIN) { -+ crp->crp_flags &= ~CRYPTO_F_DONE; -+#ifdef NOTYET -+ /* -+ * DAVIDM I am fairly sure that we should turn this into a batch -+ * request to stop bad karma/lockup, revisit -+ */ -+ crp->crp_flags |= CRYPTO_F_BATCH; -+#endif -+ return crypto_dispatch(crp); -+ } -+ if (error != 0 || (crp->crp_flags & CRYPTO_F_DONE)) { -+ cse->error = error; -+ wake_up_interruptible(&crp->crp_waitq); -+ } -+ return (0); -+} -+ -+static int -+cryptodevkey_cb(void *op) -+{ -+ struct cryptkop *krp = (struct cryptkop *) op; -+ dprintk("%s()\n", __FUNCTION__); -+ wake_up_interruptible(&krp->krp_waitq); -+ return (0); -+} -+ -+static int -+cryptodev_key(struct crypt_kop *kop) -+{ -+ struct cryptkop *krp = NULL; -+ int error = EINVAL; -+ int in, out, size, i; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (kop->crk_iparams + kop->crk_oparams > CRK_MAXPARAM) { -+ dprintk("%s params too big\n", __FUNCTION__); -+ return (EFBIG); -+ } -+ -+ in = kop->crk_iparams; -+ out = kop->crk_oparams; -+ switch (kop->crk_op) { -+ case CRK_MOD_EXP: -+ if (in == 3 && out == 1) -+ break; -+ return (EINVAL); -+ case CRK_MOD_EXP_CRT: -+ if (in == 6 && out == 1) -+ break; -+ return (EINVAL); -+ case CRK_DSA_SIGN: -+ if (in == 5 && out == 2) -+ break; -+ return (EINVAL); -+ case CRK_DSA_VERIFY: -+ if (in == 7 && out == 0) -+ break; -+ return (EINVAL); -+ case CRK_DH_COMPUTE_KEY: -+ if (in == 3 && out == 1) -+ break; -+ return (EINVAL); -+ default: -+ return (EINVAL); -+ } -+ -+ krp = (struct cryptkop *)kmalloc(sizeof *krp, GFP_KERNEL); -+ if (!krp) -+ return (ENOMEM); -+ bzero(krp, sizeof *krp); -+ krp->krp_op = kop->crk_op; -+ krp->krp_status = kop->crk_status; -+ krp->krp_iparams = kop->crk_iparams; -+ krp->krp_oparams = kop->crk_oparams; -+ krp->krp_crid = kop->crk_crid; -+ krp->krp_status = 0; -+ krp->krp_flags = CRYPTO_KF_CBIMM; -+ krp->krp_callback = (int (*) (struct cryptkop *)) cryptodevkey_cb; -+ init_waitqueue_head(&krp->krp_waitq); -+ -+ for (i = 0; i < CRK_MAXPARAM; i++) -+ krp->krp_param[i].crp_nbits = kop->crk_param[i].crp_nbits; -+ for (i = 0; i < krp->krp_iparams + krp->krp_oparams; i++) { -+ size = (krp->krp_param[i].crp_nbits + 7) / 8; -+ if (size == 0) -+ continue; -+ krp->krp_param[i].crp_p = (caddr_t) kmalloc(size, GFP_KERNEL); -+ if (i >= krp->krp_iparams) -+ continue; -+ error = copy_from_user(krp->krp_param[i].crp_p, -+ kop->crk_param[i].crp_p, size); -+ if (error) -+ goto fail; -+ } -+ -+ error = crypto_kdispatch(krp); -+ if (error) -+ goto fail; -+ -+ do { -+ error = wait_event_interruptible(krp->krp_waitq, -+ ((krp->krp_flags & CRYPTO_KF_DONE) != 0)); -+ /* -+ * we can't break out of this loop or we will leave behind -+ * a huge mess, however, staying here means if your driver -+ * is broken user applications can hang and not be killed. -+ * The solution, fix your driver :-) -+ */ -+ if (error) { -+ schedule(); -+ error = 0; -+ } -+ } while ((krp->krp_flags & CRYPTO_KF_DONE) == 0); -+ -+ dprintk("%s finished WAITING error=%d\n", __FUNCTION__, error); -+ -+ kop->crk_crid = krp->krp_crid; /* device that did the work */ -+ if (krp->krp_status != 0) { -+ error = krp->krp_status; -+ goto fail; -+ } -+ -+ for (i = krp->krp_iparams; i < krp->krp_iparams + krp->krp_oparams; i++) { -+ size = (krp->krp_param[i].crp_nbits + 7) / 8; -+ if (size == 0) -+ continue; -+ error = copy_to_user(kop->crk_param[i].crp_p, krp->krp_param[i].crp_p, -+ size); -+ if (error) -+ goto fail; -+ } -+ -+fail: -+ if (krp) { -+ kop->crk_status = krp->krp_status; -+ for (i = 0; i < CRK_MAXPARAM; i++) { -+ if (krp->krp_param[i].crp_p) -+ kfree(krp->krp_param[i].crp_p); -+ } -+ kfree(krp); -+ } -+ return (error); -+} -+ -+static int -+cryptodev_find(struct crypt_find_op *find) -+{ -+ device_t dev; -+ -+ if (find->crid != -1) { -+ dev = crypto_find_device_byhid(find->crid); -+ if (dev == NULL) -+ return (ENOENT); -+ strlcpy(find->name, device_get_nameunit(dev), -+ sizeof(find->name)); -+ } else { -+ find->crid = crypto_find_driver(find->name); -+ if (find->crid == -1) -+ return (ENOENT); -+ } -+ return (0); -+} -+ -+static struct csession * -+csefind(struct fcrypt *fcr, u_int ses) -+{ -+ struct csession *cse; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ list_for_each_entry(cse, &fcr->csessions, list) -+ if (cse->ses == ses) -+ return (cse); -+ return (NULL); -+} -+ -+static int -+csedelete(struct fcrypt *fcr, struct csession *cse_del) -+{ -+ struct csession *cse; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ list_for_each_entry(cse, &fcr->csessions, list) { -+ if (cse == cse_del) { -+ list_del(&cse->list); -+ return (1); -+ } -+ } -+ return (0); -+} -+ -+static struct csession * -+cseadd(struct fcrypt *fcr, struct csession *cse) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ list_add_tail(&cse->list, &fcr->csessions); -+ cse->ses = fcr->sesn++; -+ return (cse); -+} -+ -+static struct csession * -+csecreate(struct fcrypt *fcr, u_int64_t sid, struct cryptoini *crie, -+ struct cryptoini *cria, struct csession_info *info) -+{ -+ struct csession *cse; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ cse = (struct csession *) kmalloc(sizeof(struct csession), GFP_KERNEL); -+ if (cse == NULL) -+ return NULL; -+ memset(cse, 0, sizeof(struct csession)); -+ -+ INIT_LIST_HEAD(&cse->list); -+ init_waitqueue_head(&cse->waitq); -+ -+ cse->key = crie->cri_key; -+ cse->keylen = crie->cri_klen/8; -+ cse->mackey = cria->cri_key; -+ cse->mackeylen = cria->cri_klen/8; -+ cse->sid = sid; -+ cse->cipher = crie->cri_alg; -+ cse->mac = cria->cri_alg; -+ cse->info = *info; -+ cseadd(fcr, cse); -+ return (cse); -+} -+ -+static int -+csefree(struct csession *cse) -+{ -+ int error; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ error = crypto_freesession(cse->sid); -+ if (cse->key) -+ kfree(cse->key); -+ if (cse->mackey) -+ kfree(cse->mackey); -+ kfree(cse); -+ return(error); -+} -+ -+static int -+cryptodev_ioctl( -+ struct inode *inode, -+ struct file *filp, -+ unsigned int cmd, -+ unsigned long arg) -+{ -+ struct cryptoini cria, crie; -+ struct fcrypt *fcr = filp->private_data; -+ struct csession *cse; -+ struct csession_info info; -+ struct session2_op sop; -+ struct crypt_op cop; -+ struct crypt_kop kop; -+ struct crypt_find_op fop; -+ u_int64_t sid; -+ u_int32_t ses = 0; -+ int feat, fd, error = 0, crid; -+ mm_segment_t fs; -+ -+ dprintk("%s(cmd=%x arg=%lx)\n", __FUNCTION__, cmd, arg); -+ -+ switch (cmd) { -+ -+ case CRIOGET: { -+ dprintk("%s(CRIOGET)\n", __FUNCTION__); -+ fs = get_fs(); -+ set_fs(get_ds()); -+ for (fd = 0; fd < files_fdtable(current->files)->max_fds; fd++) -+ if (files_fdtable(current->files)->fd[fd] == filp) -+ break; -+ fd = sys_dup(fd); -+ set_fs(fs); -+ put_user(fd, (int *) arg); -+ return IS_ERR_VALUE(fd) ? fd : 0; -+ } -+ -+#define CIOCGSESSSTR (cmd == CIOCGSESSION ? "CIOCGSESSION" : "CIOCGSESSION2") -+ case CIOCGSESSION: -+ case CIOCGSESSION2: -+ dprintk("%s(%s)\n", __FUNCTION__, CIOCGSESSSTR); -+ memset(&crie, 0, sizeof(crie)); -+ memset(&cria, 0, sizeof(cria)); -+ memset(&info, 0, sizeof(info)); -+ memset(&sop, 0, sizeof(sop)); -+ -+ if (copy_from_user(&sop, (void*)arg, (cmd == CIOCGSESSION) ? -+ sizeof(struct session_op) : sizeof(sop))) { -+ dprintk("%s(%s) - bad copy\n", __FUNCTION__, CIOCGSESSSTR); -+ error = EFAULT; -+ goto bail; -+ } -+ -+ switch (sop.cipher) { -+ case 0: -+ dprintk("%s(%s) - no cipher\n", __FUNCTION__, CIOCGSESSSTR); -+ break; -+ case CRYPTO_NULL_CBC: -+ info.blocksize = NULL_BLOCK_LEN; -+ info.minkey = NULL_MIN_KEY_LEN; -+ info.maxkey = NULL_MAX_KEY_LEN; -+ break; -+ case CRYPTO_DES_CBC: -+ info.blocksize = DES_BLOCK_LEN; -+ info.minkey = DES_MIN_KEY_LEN; -+ info.maxkey = DES_MAX_KEY_LEN; -+ break; -+ case CRYPTO_3DES_CBC: -+ info.blocksize = DES3_BLOCK_LEN; -+ info.minkey = DES3_MIN_KEY_LEN; -+ info.maxkey = DES3_MAX_KEY_LEN; -+ break; -+ case CRYPTO_BLF_CBC: -+ info.blocksize = BLOWFISH_BLOCK_LEN; -+ info.minkey = BLOWFISH_MIN_KEY_LEN; -+ info.maxkey = BLOWFISH_MAX_KEY_LEN; -+ break; -+ case CRYPTO_CAST_CBC: -+ info.blocksize = CAST128_BLOCK_LEN; -+ info.minkey = CAST128_MIN_KEY_LEN; -+ info.maxkey = CAST128_MAX_KEY_LEN; -+ break; -+ case CRYPTO_SKIPJACK_CBC: -+ info.blocksize = SKIPJACK_BLOCK_LEN; -+ info.minkey = SKIPJACK_MIN_KEY_LEN; -+ info.maxkey = SKIPJACK_MAX_KEY_LEN; -+ break; -+ case CRYPTO_AES_CBC: -+ info.blocksize = AES_BLOCK_LEN; -+ info.minkey = AES_MIN_KEY_LEN; -+ info.maxkey = AES_MAX_KEY_LEN; -+ break; -+ case CRYPTO_ARC4: -+ info.blocksize = ARC4_BLOCK_LEN; -+ info.minkey = ARC4_MIN_KEY_LEN; -+ info.maxkey = ARC4_MAX_KEY_LEN; -+ break; -+ case CRYPTO_CAMELLIA_CBC: -+ info.blocksize = CAMELLIA_BLOCK_LEN; -+ info.minkey = CAMELLIA_MIN_KEY_LEN; -+ info.maxkey = CAMELLIA_MAX_KEY_LEN; -+ break; -+ default: -+ dprintk("%s(%s) - bad cipher\n", __FUNCTION__, CIOCGSESSSTR); -+ error = EINVAL; -+ goto bail; -+ } -+ -+ switch (sop.mac) { -+ case 0: -+ dprintk("%s(%s) - no mac\n", __FUNCTION__, CIOCGSESSSTR); -+ break; -+ case CRYPTO_NULL_HMAC: -+ info.authsize = NULL_HASH_LEN; -+ break; -+ case CRYPTO_MD5: -+ info.authsize = MD5_HASH_LEN; -+ break; -+ case CRYPTO_SHA1: -+ info.authsize = SHA1_HASH_LEN; -+ break; -+ case CRYPTO_SHA2_256: -+ info.authsize = SHA2_256_HASH_LEN; -+ break; -+ case CRYPTO_SHA2_384: -+ info.authsize = SHA2_384_HASH_LEN; -+ break; -+ case CRYPTO_SHA2_512: -+ info.authsize = SHA2_512_HASH_LEN; -+ break; -+ case CRYPTO_RIPEMD160: -+ info.authsize = RIPEMD160_HASH_LEN; -+ break; -+ case CRYPTO_MD5_HMAC: -+ info.authsize = MD5_HASH_LEN; -+ info.authkey = 16; -+ break; -+ case CRYPTO_SHA1_HMAC: -+ info.authsize = SHA1_HASH_LEN; -+ info.authkey = 20; -+ break; -+ case CRYPTO_SHA2_256_HMAC: -+ info.authsize = SHA2_256_HASH_LEN; -+ info.authkey = 32; -+ break; -+ case CRYPTO_SHA2_384_HMAC: -+ info.authsize = SHA2_384_HASH_LEN; -+ info.authkey = 48; -+ break; -+ case CRYPTO_SHA2_512_HMAC: -+ info.authsize = SHA2_512_HASH_LEN; -+ info.authkey = 64; -+ break; -+ case CRYPTO_RIPEMD160_HMAC: -+ info.authsize = RIPEMD160_HASH_LEN; -+ info.authkey = 20; -+ break; -+ default: -+ dprintk("%s(%s) - bad mac\n", __FUNCTION__, CIOCGSESSSTR); -+ error = EINVAL; -+ goto bail; -+ } -+ -+ if (info.blocksize) { -+ crie.cri_alg = sop.cipher; -+ crie.cri_klen = sop.keylen * 8; -+ if ((info.maxkey && sop.keylen > info.maxkey) || -+ sop.keylen < info.minkey) { -+ dprintk("%s(%s) - bad key\n", __FUNCTION__, CIOCGSESSSTR); -+ error = EINVAL; -+ goto bail; -+ } -+ -+ crie.cri_key = (u_int8_t *) kmalloc(crie.cri_klen/8+1, GFP_KERNEL); -+ if (copy_from_user(crie.cri_key, sop.key, -+ crie.cri_klen/8)) { -+ dprintk("%s(%s) - bad copy\n", __FUNCTION__, CIOCGSESSSTR); -+ error = EFAULT; -+ goto bail; -+ } -+ if (info.authsize) -+ crie.cri_next = &cria; -+ } -+ -+ if (info.authsize) { -+ cria.cri_alg = sop.mac; -+ cria.cri_klen = sop.mackeylen * 8; -+ if (info.authkey && sop.mackeylen != info.authkey) { -+ dprintk("%s(%s) - mackeylen %d != %d\n", __FUNCTION__, -+ CIOCGSESSSTR, sop.mackeylen, info.authkey); -+ error = EINVAL; -+ goto bail; -+ } -+ -+ if (cria.cri_klen) { -+ cria.cri_key = (u_int8_t *) kmalloc(cria.cri_klen/8,GFP_KERNEL); -+ if (copy_from_user(cria.cri_key, sop.mackey, -+ cria.cri_klen / 8)) { -+ dprintk("%s(%s) - bad copy\n", __FUNCTION__, CIOCGSESSSTR); -+ error = EFAULT; -+ goto bail; -+ } -+ } -+ } -+ -+ /* NB: CIOGSESSION2 has the crid */ -+ if (cmd == CIOCGSESSION2) { -+ crid = sop.crid; -+ error = checkcrid(crid); -+ if (error) { -+ dprintk("%s(%s) - checkcrid %x\n", __FUNCTION__, -+ CIOCGSESSSTR, error); -+ goto bail; -+ } -+ } else { -+ /* allow either HW or SW to be used */ -+ crid = CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE; -+ } -+ error = crypto_newsession(&sid, (info.blocksize ? &crie : &cria), crid); -+ if (error) { -+ dprintk("%s(%s) - newsession %d\n",__FUNCTION__,CIOCGSESSSTR,error); -+ goto bail; -+ } -+ -+ cse = csecreate(fcr, sid, &crie, &cria, &info); -+ if (cse == NULL) { -+ crypto_freesession(sid); -+ error = EINVAL; -+ dprintk("%s(%s) - csecreate failed\n", __FUNCTION__, CIOCGSESSSTR); -+ goto bail; -+ } -+ sop.ses = cse->ses; -+ -+ if (cmd == CIOCGSESSION2) { -+ /* return hardware/driver id */ -+ sop.crid = CRYPTO_SESID2HID(cse->sid); -+ } -+ -+ if (copy_to_user((void*)arg, &sop, (cmd == CIOCGSESSION) ? -+ sizeof(struct session_op) : sizeof(sop))) { -+ dprintk("%s(%s) - bad copy\n", __FUNCTION__, CIOCGSESSSTR); -+ error = EFAULT; -+ } -+bail: -+ if (error) { -+ dprintk("%s(%s) - bail %d\n", __FUNCTION__, CIOCGSESSSTR, error); -+ if (crie.cri_key) -+ kfree(crie.cri_key); -+ if (cria.cri_key) -+ kfree(cria.cri_key); -+ } -+ break; -+ case CIOCFSESSION: -+ dprintk("%s(CIOCFSESSION)\n", __FUNCTION__); -+ get_user(ses, (uint32_t*)arg); -+ cse = csefind(fcr, ses); -+ if (cse == NULL) { -+ error = EINVAL; -+ dprintk("%s(CIOCFSESSION) - Fail %d\n", __FUNCTION__, error); -+ break; -+ } -+ csedelete(fcr, cse); -+ error = csefree(cse); -+ break; -+ case CIOCCRYPT: -+ dprintk("%s(CIOCCRYPT)\n", __FUNCTION__); -+ if(copy_from_user(&cop, (void*)arg, sizeof(cop))) { -+ dprintk("%s(CIOCCRYPT) - bad copy\n", __FUNCTION__); -+ error = EFAULT; -+ goto bail; -+ } -+ cse = csefind(fcr, cop.ses); -+ if (cse == NULL) { -+ error = EINVAL; -+ dprintk("%s(CIOCCRYPT) - Fail %d\n", __FUNCTION__, error); -+ break; -+ } -+ error = cryptodev_op(cse, &cop); -+ if(copy_to_user((void*)arg, &cop, sizeof(cop))) { -+ dprintk("%s(CIOCCRYPT) - bad return copy\n", __FUNCTION__); -+ error = EFAULT; -+ goto bail; -+ } -+ break; -+ case CIOCKEY: -+ case CIOCKEY2: -+ dprintk("%s(CIOCKEY)\n", __FUNCTION__); -+ if (!crypto_userasymcrypto) -+ return (EPERM); /* XXX compat? */ -+ if(copy_from_user(&kop, (void*)arg, sizeof(kop))) { -+ dprintk("%s(CIOCKEY) - bad copy\n", __FUNCTION__); -+ error = EFAULT; -+ goto bail; -+ } -+ if (cmd == CIOCKEY) { -+ /* NB: crypto core enforces s/w driver use */ -+ kop.crk_crid = -+ CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE; -+ } -+ error = cryptodev_key(&kop); -+ if(copy_to_user((void*)arg, &kop, sizeof(kop))) { -+ dprintk("%s(CIOCGKEY) - bad return copy\n", __FUNCTION__); -+ error = EFAULT; -+ goto bail; -+ } -+ break; -+ case CIOCASYMFEAT: -+ dprintk("%s(CIOCASYMFEAT)\n", __FUNCTION__); -+ if (!crypto_userasymcrypto) { -+ /* -+ * NB: if user asym crypto operations are -+ * not permitted return "no algorithms" -+ * so well-behaved applications will just -+ * fallback to doing them in software. -+ */ -+ feat = 0; -+ } else -+ error = crypto_getfeat(&feat); -+ if (!error) { -+ error = copy_to_user((void*)arg, &feat, sizeof(feat)); -+ } -+ break; -+ case CIOCFINDDEV: -+ if (copy_from_user(&fop, (void*)arg, sizeof(fop))) { -+ dprintk("%s(CIOCFINDDEV) - bad copy\n", __FUNCTION__); -+ error = EFAULT; -+ goto bail; -+ } -+ error = cryptodev_find(&fop); -+ if (copy_to_user((void*)arg, &fop, sizeof(fop))) { -+ dprintk("%s(CIOCFINDDEV) - bad return copy\n", __FUNCTION__); -+ error = EFAULT; -+ goto bail; -+ } -+ break; -+ default: -+ dprintk("%s(unknown ioctl 0x%x)\n", __FUNCTION__, cmd); -+ error = EINVAL; -+ break; -+ } -+ return(-error); -+} -+ -+#ifdef HAVE_UNLOCKED_IOCTL -+static long -+cryptodev_unlocked_ioctl( -+ struct file *filp, -+ unsigned int cmd, -+ unsigned long arg) -+{ -+ return cryptodev_ioctl(NULL, filp, cmd, arg); -+} -+#endif -+ -+static int -+cryptodev_open(struct inode *inode, struct file *filp) -+{ -+ struct fcrypt *fcr; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (filp->private_data) { -+ printk("cryptodev: Private data already exists !\n"); -+ return(0); -+ } -+ -+ fcr = kmalloc(sizeof(*fcr), GFP_KERNEL); -+ if (!fcr) { -+ dprintk("%s() - malloc failed\n", __FUNCTION__); -+ return(-ENOMEM); -+ } -+ memset(fcr, 0, sizeof(*fcr)); -+ -+ INIT_LIST_HEAD(&fcr->csessions); -+ filp->private_data = fcr; -+ return(0); -+} -+ -+static int -+cryptodev_release(struct inode *inode, struct file *filp) -+{ -+ struct fcrypt *fcr = filp->private_data; -+ struct csession *cse, *tmp; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (!filp) { -+ printk("cryptodev: No private data on release\n"); -+ return(0); -+ } -+ -+ list_for_each_entry_safe(cse, tmp, &fcr->csessions, list) { -+ list_del(&cse->list); -+ (void)csefree(cse); -+ } -+ filp->private_data = NULL; -+ kfree(fcr); -+ return(0); -+} -+ -+static struct file_operations cryptodev_fops = { -+ .owner = THIS_MODULE, -+ .open = cryptodev_open, -+ .release = cryptodev_release, -+#ifdef HAVE_UNLOCKED_IOCTL -+ .unlocked_ioctl = cryptodev_unlocked_ioctl, -+#endif -+}; -+ -+static struct miscdevice cryptodev = { -+ .minor = CRYPTODEV_MINOR, -+ .name = "crypto", -+ .fops = &cryptodev_fops, -+}; -+ -+static int __init -+cryptodev_init(void) -+{ -+ int rc; -+ -+ dprintk("%s(%p)\n", __FUNCTION__, cryptodev_init); -+ rc = misc_register(&cryptodev); -+ if (rc) { -+ printk(KERN_ERR "cryptodev: registration of /dev/crypto failed\n"); -+ return(rc); -+ } -+ -+ return(0); -+} -+ -+static void __exit -+cryptodev_exit(void) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ misc_deregister(&cryptodev); -+} -+ -+module_init(cryptodev_init); -+module_exit(cryptodev_exit); -+ -+MODULE_LICENSE("BSD"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("Cryptodev (user interface to OCF)"); -diff -Nur linux-2.6.39.orig/crypto/ocf/cryptodev.h linux-2.6.39/crypto/ocf/cryptodev.h ---- linux-2.6.39.orig/crypto/ocf/cryptodev.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/cryptodev.h 2011-08-01 14:38:18.000000000 +0200 -@@ -0,0 +1,479 @@ -+/* $FreeBSD: src/sys/opencrypto/cryptodev.h,v 1.25 2007/05/09 19:37:02 gnn Exp $ */ -+/* $OpenBSD: cryptodev.h,v 1.31 2002/06/11 11:14:29 beck Exp $ */ -+ -+/*- -+ * Linux port done by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * The license and original author are listed below. -+ * -+ * The author of this code is Angelos D. Keromytis (angelos@cis.upenn.edu) -+ * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting -+ * -+ * This code was written by Angelos D. Keromytis in Athens, Greece, in -+ * February 2000. Network Security Technologies Inc. (NSTI) kindly -+ * supported the development of this code. -+ * -+ * Copyright (c) 2000 Angelos D. Keromytis -+ * -+ * Permission to use, copy, and modify this software with or without fee -+ * is hereby granted, provided that this entire notice is included in -+ * all source code copies of any software which is or includes a copy or -+ * modification of this software. -+ * -+ * THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR -+ * IMPLIED WARRANTY. IN PARTICULAR, NONE OF THE AUTHORS MAKES ANY -+ * REPRESENTATION OR WARRANTY OF ANY KIND CONCERNING THE -+ * MERCHANTABILITY OF THIS SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR -+ * PURPOSE. -+ * -+ * Copyright (c) 2001 Theo de Raadt -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored in part by the Defense Advanced Research Projects -+ * Agency (DARPA) and Air Force Research Laboratory, Air Force -+ * Materiel Command, USAF, under agreement number F30602-01-2-0537. -+ * -+ */ -+ -+#ifndef _CRYPTO_CRYPTO_H_ -+#define _CRYPTO_CRYPTO_H_ -+ -+/* Some initial values */ -+#define CRYPTO_DRIVERS_INITIAL 4 -+#define CRYPTO_SW_SESSIONS 32 -+ -+/* Hash values */ -+#define NULL_HASH_LEN 0 -+#define MD5_HASH_LEN 16 -+#define SHA1_HASH_LEN 20 -+#define RIPEMD160_HASH_LEN 20 -+#define SHA2_256_HASH_LEN 32 -+#define SHA2_384_HASH_LEN 48 -+#define SHA2_512_HASH_LEN 64 -+#define MD5_KPDK_HASH_LEN 16 -+#define SHA1_KPDK_HASH_LEN 20 -+/* Maximum hash algorithm result length */ -+#define HASH_MAX_LEN SHA2_512_HASH_LEN /* Keep this updated */ -+ -+/* HMAC values */ -+#define NULL_HMAC_BLOCK_LEN 1 -+#define MD5_HMAC_BLOCK_LEN 64 -+#define SHA1_HMAC_BLOCK_LEN 64 -+#define RIPEMD160_HMAC_BLOCK_LEN 64 -+#define SHA2_256_HMAC_BLOCK_LEN 64 -+#define SHA2_384_HMAC_BLOCK_LEN 128 -+#define SHA2_512_HMAC_BLOCK_LEN 128 -+/* Maximum HMAC block length */ -+#define HMAC_MAX_BLOCK_LEN SHA2_512_HMAC_BLOCK_LEN /* Keep this updated */ -+#define HMAC_IPAD_VAL 0x36 -+#define HMAC_OPAD_VAL 0x5C -+ -+/* Encryption algorithm block sizes */ -+#define NULL_BLOCK_LEN 1 -+#define DES_BLOCK_LEN 8 -+#define DES3_BLOCK_LEN 8 -+#define BLOWFISH_BLOCK_LEN 8 -+#define SKIPJACK_BLOCK_LEN 8 -+#define CAST128_BLOCK_LEN 8 -+#define RIJNDAEL128_BLOCK_LEN 16 -+#define AES_BLOCK_LEN RIJNDAEL128_BLOCK_LEN -+#define CAMELLIA_BLOCK_LEN 16 -+#define ARC4_BLOCK_LEN 1 -+#define EALG_MAX_BLOCK_LEN AES_BLOCK_LEN /* Keep this updated */ -+ -+/* Encryption algorithm min and max key sizes */ -+#define NULL_MIN_KEY_LEN 0 -+#define NULL_MAX_KEY_LEN 0 -+#define DES_MIN_KEY_LEN 8 -+#define DES_MAX_KEY_LEN 8 -+#define DES3_MIN_KEY_LEN 24 -+#define DES3_MAX_KEY_LEN 24 -+#define BLOWFISH_MIN_KEY_LEN 4 -+#define BLOWFISH_MAX_KEY_LEN 56 -+#define SKIPJACK_MIN_KEY_LEN 10 -+#define SKIPJACK_MAX_KEY_LEN 10 -+#define CAST128_MIN_KEY_LEN 5 -+#define CAST128_MAX_KEY_LEN 16 -+#define RIJNDAEL128_MIN_KEY_LEN 16 -+#define RIJNDAEL128_MAX_KEY_LEN 32 -+#define AES_MIN_KEY_LEN RIJNDAEL128_MIN_KEY_LEN -+#define AES_MAX_KEY_LEN RIJNDAEL128_MAX_KEY_LEN -+#define CAMELLIA_MIN_KEY_LEN 16 -+#define CAMELLIA_MAX_KEY_LEN 32 -+#define ARC4_MIN_KEY_LEN 1 -+#define ARC4_MAX_KEY_LEN 256 -+ -+/* Max size of data that can be processed */ -+#define CRYPTO_MAX_DATA_LEN 64*1024 - 1 -+ -+#define CRYPTO_ALGORITHM_MIN 1 -+#define CRYPTO_DES_CBC 1 -+#define CRYPTO_3DES_CBC 2 -+#define CRYPTO_BLF_CBC 3 -+#define CRYPTO_CAST_CBC 4 -+#define CRYPTO_SKIPJACK_CBC 5 -+#define CRYPTO_MD5_HMAC 6 -+#define CRYPTO_SHA1_HMAC 7 -+#define CRYPTO_RIPEMD160_HMAC 8 -+#define CRYPTO_MD5_KPDK 9 -+#define CRYPTO_SHA1_KPDK 10 -+#define CRYPTO_RIJNDAEL128_CBC 11 /* 128 bit blocksize */ -+#define CRYPTO_AES_CBC 11 /* 128 bit blocksize -- the same as above */ -+#define CRYPTO_ARC4 12 -+#define CRYPTO_MD5 13 -+#define CRYPTO_SHA1 14 -+#define CRYPTO_NULL_HMAC 15 -+#define CRYPTO_NULL_CBC 16 -+#define CRYPTO_DEFLATE_COMP 17 /* Deflate compression algorithm */ -+#define CRYPTO_SHA2_256_HMAC 18 -+#define CRYPTO_SHA2_384_HMAC 19 -+#define CRYPTO_SHA2_512_HMAC 20 -+#define CRYPTO_CAMELLIA_CBC 21 -+#define CRYPTO_SHA2_256 22 -+#define CRYPTO_SHA2_384 23 -+#define CRYPTO_SHA2_512 24 -+#define CRYPTO_RIPEMD160 25 -+#define CRYPTO_ALGORITHM_MAX 25 /* Keep updated - see below */ -+ -+/* Algorithm flags */ -+#define CRYPTO_ALG_FLAG_SUPPORTED 0x01 /* Algorithm is supported */ -+#define CRYPTO_ALG_FLAG_RNG_ENABLE 0x02 /* Has HW RNG for DH/DSA */ -+#define CRYPTO_ALG_FLAG_DSA_SHA 0x04 /* Can do SHA on msg */ -+ -+/* -+ * Crypto driver/device flags. They can set in the crid -+ * parameter when creating a session or submitting a key -+ * op to affect the device/driver assigned. If neither -+ * of these are specified then the crid is assumed to hold -+ * the driver id of an existing (and suitable) device that -+ * must be used to satisfy the request. -+ */ -+#define CRYPTO_FLAG_HARDWARE 0x01000000 /* hardware accelerated */ -+#define CRYPTO_FLAG_SOFTWARE 0x02000000 /* software implementation */ -+ -+/* NB: deprecated */ -+struct session_op { -+ u_int32_t cipher; /* ie. CRYPTO_DES_CBC */ -+ u_int32_t mac; /* ie. CRYPTO_MD5_HMAC */ -+ -+ u_int32_t keylen; /* cipher key */ -+ caddr_t key; -+ int mackeylen; /* mac key */ -+ caddr_t mackey; -+ -+ u_int32_t ses; /* returns: session # */ -+}; -+ -+struct session2_op { -+ u_int32_t cipher; /* ie. CRYPTO_DES_CBC */ -+ u_int32_t mac; /* ie. CRYPTO_MD5_HMAC */ -+ -+ u_int32_t keylen; /* cipher key */ -+ caddr_t key; -+ int mackeylen; /* mac key */ -+ caddr_t mackey; -+ -+ u_int32_t ses; /* returns: session # */ -+ int crid; /* driver id + flags (rw) */ -+ int pad[4]; /* for future expansion */ -+}; -+ -+struct crypt_op { -+ u_int32_t ses; -+ u_int16_t op; /* i.e. COP_ENCRYPT */ -+#define COP_NONE 0 -+#define COP_ENCRYPT 1 -+#define COP_DECRYPT 2 -+ u_int16_t flags; -+#define COP_F_BATCH 0x0008 /* Batch op if possible */ -+ u_int len; -+ caddr_t src, dst; /* become iov[] inside kernel */ -+ caddr_t mac; /* must be big enough for chosen MAC */ -+ caddr_t iv; -+}; -+ -+/* -+ * Parameters for looking up a crypto driver/device by -+ * device name or by id. The latter are returned for -+ * created sessions (crid) and completed key operations. -+ */ -+struct crypt_find_op { -+ int crid; /* driver id + flags */ -+ char name[32]; /* device/driver name */ -+}; -+ -+/* bignum parameter, in packed bytes, ... */ -+struct crparam { -+ caddr_t crp_p; -+ u_int crp_nbits; -+}; -+ -+#define CRK_MAXPARAM 8 -+ -+struct crypt_kop { -+ u_int crk_op; /* ie. CRK_MOD_EXP or other */ -+ u_int crk_status; /* return status */ -+ u_short crk_iparams; /* # of input parameters */ -+ u_short crk_oparams; /* # of output parameters */ -+ u_int crk_crid; /* NB: only used by CIOCKEY2 (rw) */ -+ struct crparam crk_param[CRK_MAXPARAM]; -+}; -+#define CRK_ALGORITM_MIN 0 -+#define CRK_MOD_EXP 0 -+#define CRK_MOD_EXP_CRT 1 -+#define CRK_DSA_SIGN 2 -+#define CRK_DSA_VERIFY 3 -+#define CRK_DH_COMPUTE_KEY 4 -+#define CRK_ALGORITHM_MAX 4 /* Keep updated - see below */ -+ -+#define CRF_MOD_EXP (1 << CRK_MOD_EXP) -+#define CRF_MOD_EXP_CRT (1 << CRK_MOD_EXP_CRT) -+#define CRF_DSA_SIGN (1 << CRK_DSA_SIGN) -+#define CRF_DSA_VERIFY (1 << CRK_DSA_VERIFY) -+#define CRF_DH_COMPUTE_KEY (1 << CRK_DH_COMPUTE_KEY) -+ -+/* -+ * done against open of /dev/crypto, to get a cloned descriptor. -+ * Please use F_SETFD against the cloned descriptor. -+ */ -+#define CRIOGET _IOWR('c', 100, u_int32_t) -+#define CRIOASYMFEAT CIOCASYMFEAT -+#define CRIOFINDDEV CIOCFINDDEV -+ -+/* the following are done against the cloned descriptor */ -+#define CIOCGSESSION _IOWR('c', 101, struct session_op) -+#define CIOCFSESSION _IOW('c', 102, u_int32_t) -+#define CIOCCRYPT _IOWR('c', 103, struct crypt_op) -+#define CIOCKEY _IOWR('c', 104, struct crypt_kop) -+#define CIOCASYMFEAT _IOR('c', 105, u_int32_t) -+#define CIOCGSESSION2 _IOWR('c', 106, struct session2_op) -+#define CIOCKEY2 _IOWR('c', 107, struct crypt_kop) -+#define CIOCFINDDEV _IOWR('c', 108, struct crypt_find_op) -+ -+struct cryptotstat { -+ struct timespec acc; /* total accumulated time */ -+ struct timespec min; /* min time */ -+ struct timespec max; /* max time */ -+ u_int32_t count; /* number of observations */ -+}; -+ -+struct cryptostats { -+ u_int32_t cs_ops; /* symmetric crypto ops submitted */ -+ u_int32_t cs_errs; /* symmetric crypto ops that failed */ -+ u_int32_t cs_kops; /* asymetric/key ops submitted */ -+ u_int32_t cs_kerrs; /* asymetric/key ops that failed */ -+ u_int32_t cs_intrs; /* crypto swi thread activations */ -+ u_int32_t cs_rets; /* crypto return thread activations */ -+ u_int32_t cs_blocks; /* symmetric op driver block */ -+ u_int32_t cs_kblocks; /* symmetric op driver block */ -+ /* -+ * When CRYPTO_TIMING is defined at compile time and the -+ * sysctl debug.crypto is set to 1, the crypto system will -+ * accumulate statistics about how long it takes to process -+ * crypto requests at various points during processing. -+ */ -+ struct cryptotstat cs_invoke; /* crypto_dipsatch -> crypto_invoke */ -+ struct cryptotstat cs_done; /* crypto_invoke -> crypto_done */ -+ struct cryptotstat cs_cb; /* crypto_done -> callback */ -+ struct cryptotstat cs_finis; /* callback -> callback return */ -+ -+ u_int32_t cs_drops; /* crypto ops dropped due to congestion */ -+}; -+ -+#ifdef __KERNEL__ -+ -+/* Standard initialization structure beginning */ -+struct cryptoini { -+ int cri_alg; /* Algorithm to use */ -+ int cri_klen; /* Key length, in bits */ -+ int cri_mlen; /* Number of bytes we want from the -+ entire hash. 0 means all. */ -+ caddr_t cri_key; /* key to use */ -+ u_int8_t cri_iv[EALG_MAX_BLOCK_LEN]; /* IV to use */ -+ struct cryptoini *cri_next; -+}; -+ -+/* Describe boundaries of a single crypto operation */ -+struct cryptodesc { -+ int crd_skip; /* How many bytes to ignore from start */ -+ int crd_len; /* How many bytes to process */ -+ int crd_inject; /* Where to inject results, if applicable */ -+ int crd_flags; -+ -+#define CRD_F_ENCRYPT 0x01 /* Set when doing encryption */ -+#define CRD_F_IV_PRESENT 0x02 /* When encrypting, IV is already in -+ place, so don't copy. */ -+#define CRD_F_IV_EXPLICIT 0x04 /* IV explicitly provided */ -+#define CRD_F_DSA_SHA_NEEDED 0x08 /* Compute SHA-1 of buffer for DSA */ -+#define CRD_F_KEY_EXPLICIT 0x10 /* Key explicitly provided */ -+#define CRD_F_COMP 0x0f /* Set when doing compression */ -+ -+ struct cryptoini CRD_INI; /* Initialization/context data */ -+#define crd_iv CRD_INI.cri_iv -+#define crd_key CRD_INI.cri_key -+#define crd_alg CRD_INI.cri_alg -+#define crd_klen CRD_INI.cri_klen -+#define crd_mlen CRD_INI.cri_mlen -+ -+ struct cryptodesc *crd_next; -+}; -+ -+/* Structure describing complete operation */ -+struct cryptop { -+ struct list_head crp_next; -+ wait_queue_head_t crp_waitq; -+ -+ u_int64_t crp_sid; /* Session ID */ -+ int crp_ilen; /* Input data total length */ -+ int crp_olen; /* Result total length */ -+ -+ int crp_etype; /* -+ * Error type (zero means no error). -+ * All error codes except EAGAIN -+ * indicate possible data corruption (as in, -+ * the data have been touched). On all -+ * errors, the crp_sid may have changed -+ * (reset to a new one), so the caller -+ * should always check and use the new -+ * value on future requests. -+ */ -+ int crp_flags; -+ -+#define CRYPTO_F_SKBUF 0x0001 /* Input/output are skbuf chains */ -+#define CRYPTO_F_IOV 0x0002 /* Input/output are uio */ -+#define CRYPTO_F_REL 0x0004 /* Must return data in same place */ -+#define CRYPTO_F_BATCH 0x0008 /* Batch op if possible */ -+#define CRYPTO_F_CBIMM 0x0010 /* Do callback immediately */ -+#define CRYPTO_F_DONE 0x0020 /* Operation completed */ -+#define CRYPTO_F_CBIFSYNC 0x0040 /* Do CBIMM if op is synchronous */ -+ -+ caddr_t crp_buf; /* Data to be processed */ -+ caddr_t crp_opaque; /* Opaque pointer, passed along */ -+ struct cryptodesc *crp_desc; /* Linked list of processing descriptors */ -+ -+ int (*crp_callback)(struct cryptop *); /* Callback function */ -+}; -+ -+#define CRYPTO_BUF_CONTIG 0x0 -+#define CRYPTO_BUF_IOV 0x1 -+#define CRYPTO_BUF_SKBUF 0x2 -+ -+#define CRYPTO_OP_DECRYPT 0x0 -+#define CRYPTO_OP_ENCRYPT 0x1 -+ -+/* -+ * Hints passed to process methods. -+ */ -+#define CRYPTO_HINT_MORE 0x1 /* more ops coming shortly */ -+ -+struct cryptkop { -+ struct list_head krp_next; -+ wait_queue_head_t krp_waitq; -+ -+ int krp_flags; -+#define CRYPTO_KF_DONE 0x0001 /* Operation completed */ -+#define CRYPTO_KF_CBIMM 0x0002 /* Do callback immediately */ -+ -+ u_int krp_op; /* ie. CRK_MOD_EXP or other */ -+ u_int krp_status; /* return status */ -+ u_short krp_iparams; /* # of input parameters */ -+ u_short krp_oparams; /* # of output parameters */ -+ u_int krp_crid; /* desired device, etc. */ -+ u_int32_t krp_hid; -+ struct crparam krp_param[CRK_MAXPARAM]; /* kvm */ -+ int (*krp_callback)(struct cryptkop *); -+}; -+ -+#include -+ -+/* -+ * Session ids are 64 bits. The lower 32 bits contain a "local id" which -+ * is a driver-private session identifier. The upper 32 bits contain a -+ * "hardware id" used by the core crypto code to identify the driver and -+ * a copy of the driver's capabilities that can be used by client code to -+ * optimize operation. -+ */ -+#define CRYPTO_SESID2HID(_sid) (((_sid) >> 32) & 0x00ffffff) -+#define CRYPTO_SESID2CAPS(_sid) (((_sid) >> 32) & 0xff000000) -+#define CRYPTO_SESID2LID(_sid) (((u_int32_t) (_sid)) & 0xffffffff) -+ -+extern int crypto_newsession(u_int64_t *sid, struct cryptoini *cri, int hard); -+extern int crypto_freesession(u_int64_t sid); -+#define CRYPTOCAP_F_HARDWARE CRYPTO_FLAG_HARDWARE -+#define CRYPTOCAP_F_SOFTWARE CRYPTO_FLAG_SOFTWARE -+#define CRYPTOCAP_F_SYNC 0x04000000 /* operates synchronously */ -+extern int32_t crypto_get_driverid(device_t dev, int flags); -+extern int crypto_find_driver(const char *); -+extern device_t crypto_find_device_byhid(int hid); -+extern int crypto_getcaps(int hid); -+extern int crypto_register(u_int32_t driverid, int alg, u_int16_t maxoplen, -+ u_int32_t flags); -+extern int crypto_kregister(u_int32_t, int, u_int32_t); -+extern int crypto_unregister(u_int32_t driverid, int alg); -+extern int crypto_unregister_all(u_int32_t driverid); -+extern int crypto_dispatch(struct cryptop *crp); -+extern int crypto_kdispatch(struct cryptkop *); -+#define CRYPTO_SYMQ 0x1 -+#define CRYPTO_ASYMQ 0x2 -+extern int crypto_unblock(u_int32_t, int); -+extern void crypto_done(struct cryptop *crp); -+extern void crypto_kdone(struct cryptkop *); -+extern int crypto_getfeat(int *); -+ -+extern void crypto_freereq(struct cryptop *crp); -+extern struct cryptop *crypto_getreq(int num); -+ -+extern int crypto_usercrypto; /* userland may do crypto requests */ -+extern int crypto_userasymcrypto; /* userland may do asym crypto reqs */ -+extern int crypto_devallowsoft; /* only use hardware crypto */ -+ -+/* -+ * random number support, crypto_unregister_all will unregister -+ */ -+extern int crypto_rregister(u_int32_t driverid, -+ int (*read_random)(void *arg, u_int32_t *buf, int len), void *arg); -+extern int crypto_runregister_all(u_int32_t driverid); -+ -+/* -+ * Crypto-related utility routines used mainly by drivers. -+ * -+ * XXX these don't really belong here; but for now they're -+ * kept apart from the rest of the system. -+ */ -+struct uio; -+extern void cuio_copydata(struct uio* uio, int off, int len, caddr_t cp); -+extern void cuio_copyback(struct uio* uio, int off, int len, caddr_t cp); -+extern struct iovec *cuio_getptr(struct uio *uio, int loc, int *off); -+ -+extern void crypto_copyback(int flags, caddr_t buf, int off, int size, -+ caddr_t in); -+extern void crypto_copydata(int flags, caddr_t buf, int off, int size, -+ caddr_t out); -+extern int crypto_apply(int flags, caddr_t buf, int off, int len, -+ int (*f)(void *, void *, u_int), void *arg); -+ -+#endif /* __KERNEL__ */ -+#endif /* _CRYPTO_CRYPTO_H_ */ -diff -Nur linux-2.6.39.orig/crypto/ocf/cryptosoft.c linux-2.6.39/crypto/ocf/cryptosoft.c ---- linux-2.6.39.orig/crypto/ocf/cryptosoft.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/cryptosoft.c 2011-08-01 14:38:18.000000000 +0200 -@@ -0,0 +1,1210 @@ -+/* -+ * An OCF module that uses the linux kernel cryptoapi, based on the -+ * original cryptosoft for BSD by Angelos D. Keromytis (angelos@cis.upenn.edu) -+ * but is mostly unrecognisable, -+ * -+ * Written by David McCullough -+ * Copyright (C) 2004-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * ALTERNATIVELY, provided that this notice is retained in full, this product -+ * may be distributed under the terms of the GNU General Public License (GPL), -+ * in which case the provisions of the GPL apply INSTEAD OF those given above. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ * --------------------------------------------------------------------------- -+ */ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,10) -+#include -+#endif -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29) -+#include -+#endif -+ -+#include -+#include -+ -+struct { -+ softc_device_decl sc_dev; -+} swcr_softc; -+ -+#define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK) -+ -+#define SW_TYPE_CIPHER 0x01 -+#define SW_TYPE_HMAC 0x02 -+#define SW_TYPE_HASH 0x04 -+#define SW_TYPE_COMP 0x08 -+#define SW_TYPE_BLKCIPHER 0x10 -+#define SW_TYPE_ALG_MASK 0x1f -+ -+#define SW_TYPE_ASYNC 0x8000 -+ -+/* We change some of the above if we have an async interface */ -+ -+#define SW_TYPE_ALG_AMASK (SW_TYPE_ALG_MASK | SW_TYPE_ASYNC) -+ -+#define SW_TYPE_ABLKCIPHER (SW_TYPE_BLKCIPHER | SW_TYPE_ASYNC) -+#define SW_TYPE_AHASH (SW_TYPE_HASH | SW_TYPE_ASYNC) -+#define SW_TYPE_AHMAC (SW_TYPE_HMAC | SW_TYPE_ASYNC) -+ -+#define SCATTERLIST_MAX 16 -+ -+struct swcr_data { -+ int sw_type; -+ int sw_alg; -+ struct crypto_tfm *sw_tfm; -+ union { -+ struct { -+ char *sw_key; -+ int sw_klen; -+ int sw_mlen; -+ } hmac; -+ void *sw_comp_buf; -+ } u; -+ struct swcr_data *sw_next; -+}; -+ -+struct swcr_req { -+ struct swcr_data *sw_head; -+ struct swcr_data *sw; -+ struct cryptop *crp; -+ struct cryptodesc *crd; -+ struct scatterlist sg[SCATTERLIST_MAX]; -+ unsigned char iv[EALG_MAX_BLOCK_LEN]; -+ char result[HASH_MAX_LEN]; -+ void *crypto_req; -+}; -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) -+static kmem_cache_t *swcr_req_cache; -+#else -+static struct kmem_cache *swcr_req_cache; -+#endif -+ -+#ifndef CRYPTO_TFM_MODE_CBC -+/* -+ * As of linux-2.6.21 this is no longer defined, and presumably no longer -+ * needed to be passed into the crypto core code. -+ */ -+#define CRYPTO_TFM_MODE_CBC 0 -+#define CRYPTO_TFM_MODE_ECB 0 -+#endif -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) -+ /* -+ * Linux 2.6.19 introduced a new Crypto API, setup macro's to convert new -+ * API into old API. -+ */ -+ -+ /* Symmetric/Block Cipher */ -+ struct blkcipher_desc -+ { -+ struct crypto_tfm *tfm; -+ void *info; -+ }; -+ #define ecb(X) #X , CRYPTO_TFM_MODE_ECB -+ #define cbc(X) #X , CRYPTO_TFM_MODE_CBC -+ #define crypto_has_blkcipher(X, Y, Z) crypto_alg_available(X, 0) -+ #define crypto_blkcipher_cast(X) X -+ #define crypto_blkcipher_tfm(X) X -+ #define crypto_alloc_blkcipher(X, Y, Z) crypto_alloc_tfm(X, mode) -+ #define crypto_blkcipher_ivsize(X) crypto_tfm_alg_ivsize(X) -+ #define crypto_blkcipher_blocksize(X) crypto_tfm_alg_blocksize(X) -+ #define crypto_blkcipher_setkey(X, Y, Z) crypto_cipher_setkey(X, Y, Z) -+ #define crypto_blkcipher_encrypt_iv(W, X, Y, Z) \ -+ crypto_cipher_encrypt_iv((W)->tfm, X, Y, Z, (u8 *)((W)->info)) -+ #define crypto_blkcipher_decrypt_iv(W, X, Y, Z) \ -+ crypto_cipher_decrypt_iv((W)->tfm, X, Y, Z, (u8 *)((W)->info)) -+ #define crypto_blkcipher_set_flags(x, y) /* nop */ -+ -+ /* Hash/HMAC/Digest */ -+ struct hash_desc -+ { -+ struct crypto_tfm *tfm; -+ }; -+ #define hmac(X) #X , 0 -+ #define crypto_has_hash(X, Y, Z) crypto_alg_available(X, 0) -+ #define crypto_hash_cast(X) X -+ #define crypto_hash_tfm(X) X -+ #define crypto_alloc_hash(X, Y, Z) crypto_alloc_tfm(X, mode) -+ #define crypto_hash_digestsize(X) crypto_tfm_alg_digestsize(X) -+ #define crypto_hash_digest(W, X, Y, Z) \ -+ crypto_digest_digest((W)->tfm, X, sg_num, Z) -+ -+ /* Asymmetric Cipher */ -+ #define crypto_has_cipher(X, Y, Z) crypto_alg_available(X, 0) -+ -+ /* Compression */ -+ #define crypto_has_comp(X, Y, Z) crypto_alg_available(X, 0) -+ #define crypto_comp_tfm(X) X -+ #define crypto_comp_cast(X) X -+ #define crypto_alloc_comp(X, Y, Z) crypto_alloc_tfm(X, mode) -+ #define plain(X) #X , 0 -+#else -+ #define ecb(X) "ecb(" #X ")" , 0 -+ #define cbc(X) "cbc(" #X ")" , 0 -+ #define hmac(X) "hmac(" #X ")" , 0 -+ #define plain(X) #X , 0 -+#endif /* if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) */ -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22) -+/* no ablkcipher in older kernels */ -+#define crypto_alloc_ablkcipher(a,b,c) (NULL) -+#define crypto_ablkcipher_tfm(x) ((struct crypto_tfm *)(x)) -+#define crypto_ablkcipher_set_flags(a, b) /* nop */ -+#define crypto_ablkcipher_setkey(x, y, z) (-EINVAL) -+#define crypto_has_ablkcipher(a,b,c) (0) -+#else -+#define HAVE_ABLKCIPHER -+#endif -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,32) -+/* no ahash in older kernels */ -+#define crypto_ahash_tfm(x) ((struct crypto_tfm *)(x)) -+#define crypto_alloc_ahash(a,b,c) (NULL) -+#define crypto_ahash_digestsize(x) 0 -+#else -+#define HAVE_AHASH -+#endif -+ -+struct crypto_details { -+ char *alg_name; -+ int mode; -+ int sw_type; -+}; -+ -+static struct crypto_details crypto_details[] = { -+ [CRYPTO_DES_CBC] = { cbc(des), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_3DES_CBC] = { cbc(des3_ede), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_BLF_CBC] = { cbc(blowfish), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_CAST_CBC] = { cbc(cast5), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_SKIPJACK_CBC] = { cbc(skipjack), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_MD5_HMAC] = { hmac(md5), SW_TYPE_HMAC, }, -+ [CRYPTO_SHA1_HMAC] = { hmac(sha1), SW_TYPE_HMAC, }, -+ [CRYPTO_RIPEMD160_HMAC] = { hmac(ripemd160), SW_TYPE_HMAC, }, -+ [CRYPTO_MD5_KPDK] = { plain(md5-kpdk), SW_TYPE_HASH, }, -+ [CRYPTO_SHA1_KPDK] = { plain(sha1-kpdk), SW_TYPE_HASH, }, -+ [CRYPTO_AES_CBC] = { cbc(aes), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_ARC4] = { ecb(arc4), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_MD5] = { plain(md5), SW_TYPE_HASH, }, -+ [CRYPTO_SHA1] = { plain(sha1), SW_TYPE_HASH, }, -+ [CRYPTO_NULL_HMAC] = { hmac(digest_null), SW_TYPE_HMAC, }, -+ [CRYPTO_NULL_CBC] = { cbc(cipher_null), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_DEFLATE_COMP] = { plain(deflate), SW_TYPE_COMP, }, -+ [CRYPTO_SHA2_256_HMAC] = { hmac(sha256), SW_TYPE_HMAC, }, -+ [CRYPTO_SHA2_384_HMAC] = { hmac(sha384), SW_TYPE_HMAC, }, -+ [CRYPTO_SHA2_512_HMAC] = { hmac(sha512), SW_TYPE_HMAC, }, -+ [CRYPTO_CAMELLIA_CBC] = { cbc(camellia), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_SHA2_256] = { plain(sha256), SW_TYPE_HASH, }, -+ [CRYPTO_SHA2_384] = { plain(sha384), SW_TYPE_HASH, }, -+ [CRYPTO_SHA2_512] = { plain(sha512), SW_TYPE_HASH, }, -+ [CRYPTO_RIPEMD160] = { plain(ripemd160), SW_TYPE_HASH, }, -+}; -+ -+int32_t swcr_id = -1; -+module_param(swcr_id, int, 0444); -+MODULE_PARM_DESC(swcr_id, "Read-Only OCF ID for cryptosoft driver"); -+ -+int swcr_fail_if_compression_grows = 1; -+module_param(swcr_fail_if_compression_grows, int, 0644); -+MODULE_PARM_DESC(swcr_fail_if_compression_grows, -+ "Treat compression that results in more data as a failure"); -+ -+int swcr_no_ahash = 0; -+module_param(swcr_no_ahash, int, 0644); -+MODULE_PARM_DESC(swcr_no_ahash, -+ "Do not use async hash/hmac even if available"); -+ -+int swcr_no_ablk = 0; -+module_param(swcr_no_ablk, int, 0644); -+MODULE_PARM_DESC(swcr_no_ablk, -+ "Do not use async blk ciphers even if available"); -+ -+static struct swcr_data **swcr_sessions = NULL; -+static u_int32_t swcr_sesnum = 0; -+ -+static int swcr_process(device_t, struct cryptop *, int); -+static int swcr_newsession(device_t, u_int32_t *, struct cryptoini *); -+static int swcr_freesession(device_t, u_int64_t); -+ -+static device_method_t swcr_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, swcr_newsession), -+ DEVMETHOD(cryptodev_freesession,swcr_freesession), -+ DEVMETHOD(cryptodev_process, swcr_process), -+}; -+ -+#define debug swcr_debug -+int swcr_debug = 0; -+module_param(swcr_debug, int, 0644); -+MODULE_PARM_DESC(swcr_debug, "Enable debug"); -+ -+static void swcr_process_req(struct swcr_req *req); -+ -+/* -+ * Generate a new software session. -+ */ -+static int -+swcr_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) -+{ -+ struct swcr_data **swd; -+ u_int32_t i; -+ int error; -+ char *algo; -+ int mode; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid == NULL || cri == NULL) { -+ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ if (swcr_sessions) { -+ for (i = 1; i < swcr_sesnum; i++) -+ if (swcr_sessions[i] == NULL) -+ break; -+ } else -+ i = 1; /* NB: to silence compiler warning */ -+ -+ if (swcr_sessions == NULL || i == swcr_sesnum) { -+ if (swcr_sessions == NULL) { -+ i = 1; /* We leave swcr_sessions[0] empty */ -+ swcr_sesnum = CRYPTO_SW_SESSIONS; -+ } else -+ swcr_sesnum *= 2; -+ -+ swd = kmalloc(swcr_sesnum * sizeof(struct swcr_data *), SLAB_ATOMIC); -+ if (swd == NULL) { -+ /* Reset session number */ -+ if (swcr_sesnum == CRYPTO_SW_SESSIONS) -+ swcr_sesnum = 0; -+ else -+ swcr_sesnum /= 2; -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memset(swd, 0, swcr_sesnum * sizeof(struct swcr_data *)); -+ -+ /* Copy existing sessions */ -+ if (swcr_sessions) { -+ memcpy(swd, swcr_sessions, -+ (swcr_sesnum / 2) * sizeof(struct swcr_data *)); -+ kfree(swcr_sessions); -+ } -+ -+ swcr_sessions = swd; -+ } -+ -+ swd = &swcr_sessions[i]; -+ *sid = i; -+ -+ while (cri) { -+ *swd = (struct swcr_data *) kmalloc(sizeof(struct swcr_data), -+ SLAB_ATOMIC); -+ if (*swd == NULL) { -+ swcr_freesession(NULL, i); -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memset(*swd, 0, sizeof(struct swcr_data)); -+ -+ if (cri->cri_alg < 0 || -+ cri->cri_alg>=sizeof(crypto_details)/sizeof(crypto_details[0])){ -+ printk("cryptosoft: Unknown algorithm 0x%x\n", cri->cri_alg); -+ swcr_freesession(NULL, i); -+ return EINVAL; -+ } -+ -+ algo = crypto_details[cri->cri_alg].alg_name; -+ if (!algo || !*algo) { -+ printk("cryptosoft: Unsupported algorithm 0x%x\n", cri->cri_alg); -+ swcr_freesession(NULL, i); -+ return EINVAL; -+ } -+ -+ mode = crypto_details[cri->cri_alg].mode; -+ (*swd)->sw_type = crypto_details[cri->cri_alg].sw_type; -+ (*swd)->sw_alg = cri->cri_alg; -+ -+ /* Algorithm specific configuration */ -+ switch (cri->cri_alg) { -+ case CRYPTO_NULL_CBC: -+ cri->cri_klen = 0; /* make it work with crypto API */ -+ break; -+ default: -+ break; -+ } -+ -+ if ((*swd)->sw_type & SW_TYPE_BLKCIPHER) { -+ dprintk("%s crypto_alloc_*blkcipher(%s, 0x%x)\n", __FUNCTION__, -+ algo, mode); -+ -+ /* try async first */ -+ (*swd)->sw_tfm = swcr_no_ablk ? NULL : -+ crypto_ablkcipher_tfm(crypto_alloc_ablkcipher(algo, 0, 0)); -+ if ((*swd)->sw_tfm) { -+ dprintk("%s %s cipher is async\n", __FUNCTION__, algo); -+ (*swd)->sw_type |= SW_TYPE_ASYNC; -+ } else { -+ dprintk("%s %s cipher is sync\n", __FUNCTION__, algo); -+ (*swd)->sw_tfm = crypto_blkcipher_tfm( -+ crypto_alloc_blkcipher(algo, 0, CRYPTO_ALG_ASYNC)); -+ } -+ if (!(*swd)->sw_tfm) { -+ dprintk("cryptosoft: crypto_alloc_blkcipher failed(%s, 0x%x)\n", -+ algo,mode); -+ swcr_freesession(NULL, i); -+ return EINVAL; -+ } -+ -+ if (debug) { -+ dprintk("%s key:cri->cri_klen=%d,(cri->cri_klen + 7)/8=%d", -+ __FUNCTION__, cri->cri_klen, (cri->cri_klen + 7) / 8); -+ for (i = 0; i < (cri->cri_klen + 7) / 8; i++) -+ dprintk("%s0x%x", (i % 8) ? " " : "\n ", -+ cri->cri_key[i] & 0xff); -+ dprintk("\n"); -+ } -+ if ((*swd)->sw_type & SW_TYPE_ASYNC) { -+ /* OCF doesn't enforce keys */ -+ crypto_ablkcipher_set_flags( -+ __crypto_ablkcipher_cast((*swd)->sw_tfm), -+ CRYPTO_TFM_REQ_WEAK_KEY); -+ error = crypto_ablkcipher_setkey( -+ __crypto_ablkcipher_cast((*swd)->sw_tfm), -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ } else { -+ /* OCF doesn't enforce keys */ -+ crypto_blkcipher_set_flags( -+ crypto_blkcipher_cast((*swd)->sw_tfm), -+ CRYPTO_TFM_REQ_WEAK_KEY); -+ error = crypto_blkcipher_setkey( -+ crypto_blkcipher_cast((*swd)->sw_tfm), -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ } -+ if (error) { -+ printk("cryptosoft: setkey failed %d (crt_flags=0x%x)\n", error, -+ (*swd)->sw_tfm->crt_flags); -+ swcr_freesession(NULL, i); -+ return error; -+ } -+ } else if ((*swd)->sw_type & (SW_TYPE_HMAC | SW_TYPE_HASH)) { -+ dprintk("%s crypto_alloc_*hash(%s, 0x%x)\n", __FUNCTION__, -+ algo, mode); -+ -+ /* try async first */ -+ (*swd)->sw_tfm = swcr_no_ahash ? NULL : -+ crypto_ahash_tfm(crypto_alloc_ahash(algo, 0, 0)); -+ if ((*swd)->sw_tfm) { -+ dprintk("%s %s hash is async\n", __FUNCTION__, algo); -+ (*swd)->sw_type |= SW_TYPE_ASYNC; -+ } else { -+ dprintk("%s %s hash is sync\n", __FUNCTION__, algo); -+ (*swd)->sw_tfm = crypto_hash_tfm( -+ crypto_alloc_hash(algo, 0, CRYPTO_ALG_ASYNC)); -+ } -+ -+ if (!(*swd)->sw_tfm) { -+ dprintk("cryptosoft: crypto_alloc_hash failed(%s,0x%x)\n", -+ algo, mode); -+ swcr_freesession(NULL, i); -+ return EINVAL; -+ } -+ -+ (*swd)->u.hmac.sw_klen = (cri->cri_klen + 7) / 8; -+ (*swd)->u.hmac.sw_key = (char *)kmalloc((*swd)->u.hmac.sw_klen, -+ SLAB_ATOMIC); -+ if ((*swd)->u.hmac.sw_key == NULL) { -+ swcr_freesession(NULL, i); -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memcpy((*swd)->u.hmac.sw_key, cri->cri_key, (*swd)->u.hmac.sw_klen); -+ if (cri->cri_mlen) { -+ (*swd)->u.hmac.sw_mlen = cri->cri_mlen; -+ } else if ((*swd)->sw_type & SW_TYPE_ASYNC) { -+ (*swd)->u.hmac.sw_mlen = crypto_ahash_digestsize( -+ __crypto_ahash_cast((*swd)->sw_tfm)); -+ } else { -+ (*swd)->u.hmac.sw_mlen = crypto_hash_digestsize( -+ crypto_hash_cast((*swd)->sw_tfm)); -+ } -+ } else if ((*swd)->sw_type & SW_TYPE_COMP) { -+ (*swd)->sw_tfm = crypto_comp_tfm( -+ crypto_alloc_comp(algo, 0, CRYPTO_ALG_ASYNC)); -+ if (!(*swd)->sw_tfm) { -+ dprintk("cryptosoft: crypto_alloc_comp failed(%s,0x%x)\n", -+ algo, mode); -+ swcr_freesession(NULL, i); -+ return EINVAL; -+ } -+ (*swd)->u.sw_comp_buf = kmalloc(CRYPTO_MAX_DATA_LEN, SLAB_ATOMIC); -+ if ((*swd)->u.sw_comp_buf == NULL) { -+ swcr_freesession(NULL, i); -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ } else { -+ printk("cryptosoft: Unhandled sw_type %d\n", (*swd)->sw_type); -+ swcr_freesession(NULL, i); -+ return EINVAL; -+ } -+ -+ cri = cri->cri_next; -+ swd = &((*swd)->sw_next); -+ } -+ return 0; -+} -+ -+/* -+ * Free a session. -+ */ -+static int -+swcr_freesession(device_t dev, u_int64_t tid) -+{ -+ struct swcr_data *swd; -+ u_int32_t sid = CRYPTO_SESID2LID(tid); -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid > swcr_sesnum || swcr_sessions == NULL || -+ swcr_sessions[sid] == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return(EINVAL); -+ } -+ -+ /* Silently accept and return */ -+ if (sid == 0) -+ return(0); -+ -+ while ((swd = swcr_sessions[sid]) != NULL) { -+ swcr_sessions[sid] = swd->sw_next; -+ if (swd->sw_tfm) { -+ switch (swd->sw_type & SW_TYPE_ALG_AMASK) { -+#ifdef HAVE_AHASH -+ case SW_TYPE_AHMAC: -+ case SW_TYPE_AHASH: -+ crypto_free_ahash(__crypto_ahash_cast(swd->sw_tfm)); -+ break; -+#endif -+#ifdef HAVE_ABLKCIPHER -+ case SW_TYPE_ABLKCIPHER: -+ crypto_free_ablkcipher(__crypto_ablkcipher_cast(swd->sw_tfm)); -+ break; -+#endif -+ case SW_TYPE_BLKCIPHER: -+ crypto_free_blkcipher(crypto_blkcipher_cast(swd->sw_tfm)); -+ break; -+ case SW_TYPE_HMAC: -+ case SW_TYPE_HASH: -+ crypto_free_hash(crypto_hash_cast(swd->sw_tfm)); -+ break; -+ case SW_TYPE_COMP: -+ crypto_free_comp(crypto_comp_cast(swd->sw_tfm)); -+ default: -+ crypto_free_tfm(swd->sw_tfm); -+ break; -+ } -+ swd->sw_tfm = NULL; -+ } -+ if (swd->sw_type & SW_TYPE_COMP) { -+ if (swd->u.sw_comp_buf) -+ kfree(swd->u.sw_comp_buf); -+ } else { -+ if (swd->u.hmac.sw_key) -+ kfree(swd->u.hmac.sw_key); -+ } -+ kfree(swd); -+ } -+ return 0; -+} -+ -+#if defined(HAVE_ABLKCIPHER) || defined(HAVE_AHASH) -+/* older kernels had no async interface */ -+ -+static void swcr_process_callback(struct crypto_async_request *creq, int err) -+{ -+ struct swcr_req *req = creq->data; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (err) { -+ if (err == -EINPROGRESS) -+ return; -+ dprintk("%s() fail %d\n", __FUNCTION__, -err); -+ req->crp->crp_etype = -err; -+ goto done; -+ } -+ -+ switch (req->sw->sw_type & SW_TYPE_ALG_AMASK) { -+ case SW_TYPE_AHMAC: -+ case SW_TYPE_AHASH: -+ crypto_copyback(req->crp->crp_flags, req->crp->crp_buf, -+ req->crd->crd_inject, req->sw->u.hmac.sw_mlen, req->result); -+ ahash_request_free(req->crypto_req); -+ break; -+ case SW_TYPE_ABLKCIPHER: -+ ablkcipher_request_free(req->crypto_req); -+ break; -+ default: -+ req->crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ req->crd = req->crd->crd_next; -+ if (req->crd) { -+ swcr_process_req(req); -+ return; -+ } -+ -+done: -+ dprintk("%s crypto_done %p\n", __FUNCTION__, req); -+ crypto_done(req->crp); -+ kmem_cache_free(swcr_req_cache, req); -+} -+#endif /* defined(HAVE_ABLKCIPHER) || defined(HAVE_AHASH) */ -+ -+ -+static void swcr_process_req(struct swcr_req *req) -+{ -+ struct swcr_data *sw; -+ struct cryptop *crp = req->crp; -+ struct cryptodesc *crd = req->crd; -+ struct sk_buff *skb = (struct sk_buff *) crp->crp_buf; -+ struct uio *uiop = (struct uio *) crp->crp_buf; -+ int sg_num, sg_len, skip; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ /* -+ * Find the crypto context. -+ * -+ * XXX Note that the logic here prevents us from having -+ * XXX the same algorithm multiple times in a session -+ * XXX (or rather, we can but it won't give us the right -+ * XXX results). To do that, we'd need some way of differentiating -+ * XXX between the various instances of an algorithm (so we can -+ * XXX locate the correct crypto context). -+ */ -+ for (sw = req->sw_head; sw && sw->sw_alg != crd->crd_alg; sw = sw->sw_next) -+ ; -+ -+ /* No such context ? */ -+ if (sw == NULL) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ goto done; -+ } -+ -+ req->sw = sw; -+ skip = crd->crd_skip; -+ -+ /* -+ * setup the SG list skip from the start of the buffer -+ */ -+ memset(req->sg, 0, sizeof(req->sg)); -+ sg_init_table(req->sg, SCATTERLIST_MAX); -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ int i, len; -+ -+ sg_num = 0; -+ sg_len = 0; -+ -+ if (skip < skb_headlen(skb)) { -+ len = skb_headlen(skb) - skip; -+ if (len + sg_len > crd->crd_len) -+ len = crd->crd_len - sg_len; -+ sg_set_page(&req->sg[sg_num], -+ virt_to_page(skb->data + skip), len, -+ offset_in_page(skb->data + skip)); -+ sg_len += len; -+ sg_num++; -+ skip = 0; -+ } else -+ skip -= skb_headlen(skb); -+ -+ for (i = 0; sg_len < crd->crd_len && -+ i < skb_shinfo(skb)->nr_frags && -+ sg_num < SCATTERLIST_MAX; i++) { -+ if (skip < skb_shinfo(skb)->frags[i].size) { -+ len = skb_shinfo(skb)->frags[i].size - skip; -+ if (len + sg_len > crd->crd_len) -+ len = crd->crd_len - sg_len; -+ sg_set_page(&req->sg[sg_num], -+ skb_shinfo(skb)->frags[i].page, -+ len, -+ skb_shinfo(skb)->frags[i].page_offset + skip); -+ sg_len += len; -+ sg_num++; -+ skip = 0; -+ } else -+ skip -= skb_shinfo(skb)->frags[i].size; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ int len; -+ -+ sg_len = 0; -+ for (sg_num = 0; sg_len < crd->crd_len && -+ sg_num < uiop->uio_iovcnt && -+ sg_num < SCATTERLIST_MAX; sg_num++) { -+ if (skip <= uiop->uio_iov[sg_num].iov_len) { -+ len = uiop->uio_iov[sg_num].iov_len - skip; -+ if (len + sg_len > crd->crd_len) -+ len = crd->crd_len - sg_len; -+ sg_set_page(&req->sg[sg_num], -+ virt_to_page(uiop->uio_iov[sg_num].iov_base+skip), -+ len, -+ offset_in_page(uiop->uio_iov[sg_num].iov_base+skip)); -+ sg_len += len; -+ skip = 0; -+ } else -+ skip -= uiop->uio_iov[sg_num].iov_len; -+ } -+ } else { -+ sg_len = (crp->crp_ilen - skip); -+ if (sg_len > crd->crd_len) -+ sg_len = crd->crd_len; -+ sg_set_page(&req->sg[0], virt_to_page(crp->crp_buf + skip), -+ sg_len, offset_in_page(crp->crp_buf + skip)); -+ sg_num = 1; -+ } -+ -+ switch (sw->sw_type & SW_TYPE_ALG_AMASK) { -+ -+#ifdef HAVE_AHASH -+ case SW_TYPE_AHMAC: -+ case SW_TYPE_AHASH: -+ { -+ int ret; -+ -+ /* check we have room for the result */ -+ if (crp->crp_ilen - crd->crd_inject < sw->u.hmac.sw_mlen) { -+ dprintk("cryptosoft: EINVAL crp_ilen=%d, len=%d, inject=%d " -+ "digestsize=%d\n", crp->crp_ilen, crd->crd_skip + sg_len, -+ crd->crd_inject, sw->u.hmac.sw_mlen); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ req->crypto_req = -+ ahash_request_alloc(__crypto_ahash_cast(sw->sw_tfm),GFP_KERNEL); -+ if (!req->crypto_req) { -+ crp->crp_etype = ENOMEM; -+ dprintk("%s,%d: ENOMEM ahash_request_alloc", __FILE__, __LINE__); -+ goto done; -+ } -+ -+ ahash_request_set_callback(req->crypto_req, -+ CRYPTO_TFM_REQ_MAY_BACKLOG, swcr_process_callback, req); -+ -+ memset(req->result, 0, sizeof(req->result)); -+ -+ if (sw->sw_type & SW_TYPE_AHMAC) -+ crypto_ahash_setkey(__crypto_ahash_cast(sw->sw_tfm), -+ sw->u.hmac.sw_key, sw->u.hmac.sw_klen); -+ ahash_request_set_crypt(req->crypto_req, req->sg, req->result, sg_len); -+ ret = crypto_ahash_digest(req->crypto_req); -+ switch (ret) { -+ case -EINPROGRESS: -+ case -EBUSY: -+ return; -+ default: -+ case 0: -+ dprintk("hash OP %s %d\n", ret ? "failed" : "success", ret); -+ crp->crp_etype = ret; -+ ahash_request_free(req->crypto_req); -+ goto done; -+ } -+ } break; -+#endif /* HAVE_AHASH */ -+ -+#ifdef HAVE_ABLKCIPHER -+ case SW_TYPE_ABLKCIPHER: { -+ int ret; -+ unsigned char *ivp = req->iv; -+ int ivsize = -+ crypto_ablkcipher_ivsize(__crypto_ablkcipher_cast(sw->sw_tfm)); -+ -+ if (sg_len < crypto_ablkcipher_blocksize( -+ __crypto_ablkcipher_cast(sw->sw_tfm))) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: EINVAL len %d < %d\n", __FILE__, __LINE__, -+ sg_len, crypto_ablkcipher_blocksize( -+ __crypto_ablkcipher_cast(sw->sw_tfm))); -+ goto done; -+ } -+ -+ if (ivsize > sizeof(req->iv)) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ goto done; -+ } -+ -+ req->crypto_req = ablkcipher_request_alloc( -+ __crypto_ablkcipher_cast(sw->sw_tfm), GFP_KERNEL); -+ if (!req->crypto_req) { -+ crp->crp_etype = ENOMEM; -+ dprintk("%s,%d: ENOMEM ablkcipher_request_alloc", -+ __FILE__, __LINE__); -+ goto done; -+ } -+ -+ ablkcipher_request_set_callback(req->crypto_req, -+ CRYPTO_TFM_REQ_MAY_BACKLOG, swcr_process_callback, req); -+ -+ if (crd->crd_flags & CRD_F_KEY_EXPLICIT) { -+ int i, error; -+ -+ if (debug) { -+ dprintk("%s key:", __FUNCTION__); -+ for (i = 0; i < (crd->crd_klen + 7) / 8; i++) -+ dprintk("%s0x%x", (i % 8) ? " " : "\n ", -+ crd->crd_key[i] & 0xff); -+ dprintk("\n"); -+ } -+ /* OCF doesn't enforce keys */ -+ crypto_ablkcipher_set_flags(__crypto_ablkcipher_cast(sw->sw_tfm), -+ CRYPTO_TFM_REQ_WEAK_KEY); -+ error = crypto_ablkcipher_setkey( -+ __crypto_ablkcipher_cast(sw->sw_tfm), crd->crd_key, -+ (crd->crd_klen + 7) / 8); -+ if (error) { -+ dprintk("cryptosoft: setkey failed %d (crt_flags=0x%x)\n", -+ error, sw->sw_tfm->crt_flags); -+ crp->crp_etype = -error; -+ } -+ } -+ -+ if (crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ -+ -+ if (crd->crd_flags & CRD_F_IV_EXPLICIT) -+ ivp = crd->crd_iv; -+ else -+ get_random_bytes(ivp, ivsize); -+ /* -+ * do we have to copy the IV back to the buffer ? -+ */ -+ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, ivsize, (caddr_t)ivp); -+ } -+ ablkcipher_request_set_crypt(req->crypto_req, req->sg, req->sg, -+ sg_len, ivp); -+ ret = crypto_ablkcipher_encrypt(req->crypto_req); -+ -+ } else { /*decrypt */ -+ -+ if (crd->crd_flags & CRD_F_IV_EXPLICIT) -+ ivp = crd->crd_iv; -+ else -+ crypto_copydata(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, ivsize, (caddr_t)ivp); -+ ablkcipher_request_set_crypt(req->crypto_req, req->sg, req->sg, -+ sg_len, ivp); -+ ret = crypto_ablkcipher_decrypt(req->crypto_req); -+ } -+ -+ switch (ret) { -+ case -EINPROGRESS: -+ case -EBUSY: -+ return; -+ default: -+ case 0: -+ dprintk("crypto OP %s %d\n", ret ? "failed" : "success", ret); -+ crp->crp_etype = ret; -+ goto done; -+ } -+ } break; -+#endif /* HAVE_ABLKCIPHER */ -+ -+ case SW_TYPE_BLKCIPHER: { -+ unsigned char iv[EALG_MAX_BLOCK_LEN]; -+ unsigned char *ivp = iv; -+ struct blkcipher_desc desc; -+ int ivsize = crypto_blkcipher_ivsize(crypto_blkcipher_cast(sw->sw_tfm)); -+ -+ if (sg_len < crypto_blkcipher_blocksize( -+ crypto_blkcipher_cast(sw->sw_tfm))) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: EINVAL len %d < %d\n", __FILE__, __LINE__, -+ sg_len, crypto_blkcipher_blocksize( -+ crypto_blkcipher_cast(sw->sw_tfm))); -+ goto done; -+ } -+ -+ if (ivsize > sizeof(iv)) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ goto done; -+ } -+ -+ if (crd->crd_flags & CRD_F_KEY_EXPLICIT) { -+ int i, error; -+ -+ if (debug) { -+ dprintk("%s key:", __FUNCTION__); -+ for (i = 0; i < (crd->crd_klen + 7) / 8; i++) -+ dprintk("%s0x%x", (i % 8) ? " " : "\n ", -+ crd->crd_key[i] & 0xff); -+ dprintk("\n"); -+ } -+ /* OCF doesn't enforce keys */ -+ crypto_blkcipher_set_flags(crypto_blkcipher_cast(sw->sw_tfm), -+ CRYPTO_TFM_REQ_WEAK_KEY); -+ error = crypto_blkcipher_setkey( -+ crypto_blkcipher_cast(sw->sw_tfm), crd->crd_key, -+ (crd->crd_klen + 7) / 8); -+ if (error) { -+ dprintk("cryptosoft: setkey failed %d (crt_flags=0x%x)\n", -+ error, sw->sw_tfm->crt_flags); -+ crp->crp_etype = -error; -+ } -+ } -+ -+ memset(&desc, 0, sizeof(desc)); -+ desc.tfm = crypto_blkcipher_cast(sw->sw_tfm); -+ -+ if (crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ -+ -+ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { -+ ivp = crd->crd_iv; -+ } else { -+ get_random_bytes(ivp, ivsize); -+ } -+ /* -+ * do we have to copy the IV back to the buffer ? -+ */ -+ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, ivsize, (caddr_t)ivp); -+ } -+ desc.info = ivp; -+ crypto_blkcipher_encrypt_iv(&desc, req->sg, req->sg, sg_len); -+ -+ } else { /*decrypt */ -+ -+ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { -+ ivp = crd->crd_iv; -+ } else { -+ crypto_copydata(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, ivsize, (caddr_t)ivp); -+ } -+ desc.info = ivp; -+ crypto_blkcipher_decrypt_iv(&desc, req->sg, req->sg, sg_len); -+ } -+ } break; -+ -+ case SW_TYPE_HMAC: -+ case SW_TYPE_HASH: -+ { -+ char result[HASH_MAX_LEN]; -+ struct hash_desc desc; -+ -+ /* check we have room for the result */ -+ if (crp->crp_ilen - crd->crd_inject < sw->u.hmac.sw_mlen) { -+ dprintk("cryptosoft: EINVAL crp_ilen=%d, len=%d, inject=%d " -+ "digestsize=%d\n", crp->crp_ilen, crd->crd_skip + sg_len, -+ crd->crd_inject, sw->u.hmac.sw_mlen); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ memset(&desc, 0, sizeof(desc)); -+ desc.tfm = crypto_hash_cast(sw->sw_tfm); -+ -+ memset(result, 0, sizeof(result)); -+ -+ if (sw->sw_type & SW_TYPE_HMAC) { -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) -+ crypto_hmac(sw->sw_tfm, sw->u.hmac.sw_key, &sw->u.hmac.sw_klen, -+ req->sg, sg_num, result); -+#else -+ crypto_hash_setkey(desc.tfm, sw->u.hmac.sw_key, -+ sw->u.hmac.sw_klen); -+ crypto_hash_digest(&desc, req->sg, sg_len, result); -+#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) */ -+ -+ } else { /* SW_TYPE_HASH */ -+ crypto_hash_digest(&desc, req->sg, sg_len, result); -+ } -+ -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, sw->u.hmac.sw_mlen, result); -+ } -+ break; -+ -+ case SW_TYPE_COMP: { -+ void *ibuf = NULL; -+ void *obuf = sw->u.sw_comp_buf; -+ int ilen = sg_len, olen = CRYPTO_MAX_DATA_LEN; -+ int ret = 0; -+ -+ /* -+ * we need to use an additional copy if there is more than one -+ * input chunk since the kernel comp routines do not handle -+ * SG yet. Otherwise we just use the input buffer as is. -+ * Rather than allocate another buffer we just split the tmp -+ * buffer we already have. -+ * Perhaps we should just use zlib directly ? -+ */ -+ if (sg_num > 1) { -+ int blk; -+ -+ ibuf = obuf; -+ for (blk = 0; blk < sg_num; blk++) { -+ memcpy(obuf, sg_virt(&req->sg[blk]), -+ req->sg[blk].length); -+ obuf += req->sg[blk].length; -+ } -+ olen -= sg_len; -+ } else -+ ibuf = sg_virt(&req->sg[0]); -+ -+ if (crd->crd_flags & CRD_F_ENCRYPT) { /* compress */ -+ ret = crypto_comp_compress(crypto_comp_cast(sw->sw_tfm), -+ ibuf, ilen, obuf, &olen); -+ if (!ret && olen > crd->crd_len) { -+ dprintk("cryptosoft: ERANGE compress %d into %d\n", -+ crd->crd_len, olen); -+ if (swcr_fail_if_compression_grows) -+ ret = ERANGE; -+ } -+ } else { /* decompress */ -+ ret = crypto_comp_decompress(crypto_comp_cast(sw->sw_tfm), -+ ibuf, ilen, obuf, &olen); -+ if (!ret && (olen + crd->crd_inject) > crp->crp_olen) { -+ dprintk("cryptosoft: ETOOSMALL decompress %d into %d, " -+ "space for %d,at offset %d\n", -+ crd->crd_len, olen, crp->crp_olen, crd->crd_inject); -+ ret = ETOOSMALL; -+ } -+ } -+ if (ret) -+ dprintk("%s,%d: ret = %d\n", __FILE__, __LINE__, ret); -+ -+ /* -+ * on success copy result back, -+ * linux crpyto API returns -errno, we need to fix that -+ */ -+ crp->crp_etype = ret < 0 ? -ret : ret; -+ if (ret == 0) { -+ /* copy back the result and return it's size */ -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, olen, obuf); -+ crp->crp_olen = olen; -+ } -+ -+ -+ } break; -+ -+ default: -+ /* Unknown/unsupported algorithm */ -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+done: -+ crypto_done(crp); -+ kmem_cache_free(swcr_req_cache, req); -+} -+ -+ -+/* -+ * Process a crypto request. -+ */ -+static int -+swcr_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ struct swcr_req *req = NULL; -+ u_int32_t lid; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ /* Sanity check */ -+ if (crp == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ crp->crp_etype = 0; -+ -+ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ lid = crp->crp_sid & 0xffffffff; -+ if (lid >= swcr_sesnum || lid == 0 || swcr_sessions == NULL || -+ swcr_sessions[lid] == NULL) { -+ crp->crp_etype = ENOENT; -+ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); -+ goto done; -+ } -+ -+ /* -+ * do some error checking outside of the loop for SKB and IOV processing -+ * this leaves us with valid skb or uiop pointers for later -+ */ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ struct sk_buff *skb = (struct sk_buff *) crp->crp_buf; -+ if (skb_shinfo(skb)->nr_frags >= SCATTERLIST_MAX) { -+ printk("%s,%d: %d nr_frags > SCATTERLIST_MAX", __FILE__, __LINE__, -+ skb_shinfo(skb)->nr_frags); -+ goto done; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ struct uio *uiop = (struct uio *) crp->crp_buf; -+ if (uiop->uio_iovcnt > SCATTERLIST_MAX) { -+ printk("%s,%d: %d uio_iovcnt > SCATTERLIST_MAX", __FILE__, __LINE__, -+ uiop->uio_iovcnt); -+ goto done; -+ } -+ } -+ -+ /* -+ * setup a new request ready for queuing -+ */ -+ req = kmem_cache_alloc(swcr_req_cache, SLAB_ATOMIC); -+ if (req == NULL) { -+ dprintk("%s,%d: ENOMEM\n", __FILE__, __LINE__); -+ crp->crp_etype = ENOMEM; -+ goto done; -+ } -+ memset(req, 0, sizeof(*req)); -+ -+ req->sw_head = swcr_sessions[lid]; -+ req->crp = crp; -+ req->crd = crp->crp_desc; -+ -+ swcr_process_req(req); -+ return 0; -+ -+done: -+ crypto_done(crp); -+ if (req) -+ kmem_cache_free(swcr_req_cache, req); -+ return 0; -+} -+ -+ -+static int -+cryptosoft_init(void) -+{ -+ int i, sw_type, mode; -+ char *algo; -+ -+ dprintk("%s(%p)\n", __FUNCTION__, cryptosoft_init); -+ -+ swcr_req_cache = kmem_cache_create("cryptosoft_req", -+ sizeof(struct swcr_req), 0, SLAB_HWCACHE_ALIGN, NULL -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) -+ , NULL -+#endif -+ ); -+ if (!swcr_req_cache) { -+ printk("cryptosoft: failed to create request cache\n"); -+ return -ENOENT; -+ } -+ -+ softc_device_init(&swcr_softc, "cryptosoft", 0, swcr_methods); -+ -+ swcr_id = crypto_get_driverid(softc_get_device(&swcr_softc), -+ CRYPTOCAP_F_SOFTWARE | CRYPTOCAP_F_SYNC); -+ if (swcr_id < 0) { -+ printk("cryptosoft: Software crypto device cannot initialize!"); -+ return -ENODEV; -+ } -+ -+#define REGISTER(alg) \ -+ crypto_register(swcr_id, alg, 0,0) -+ -+ for (i = 0; i < sizeof(crypto_details)/sizeof(crypto_details[0]); i++) { -+ int found; -+ -+ algo = crypto_details[i].alg_name; -+ if (!algo || !*algo) { -+ dprintk("%s:Algorithm %d not supported\n", __FUNCTION__, i); -+ continue; -+ } -+ -+ mode = crypto_details[i].mode; -+ sw_type = crypto_details[i].sw_type; -+ -+ found = 0; -+ switch (sw_type & SW_TYPE_ALG_MASK) { -+ case SW_TYPE_CIPHER: -+ found = crypto_has_cipher(algo, 0, CRYPTO_ALG_ASYNC); -+ break; -+ case SW_TYPE_HMAC: -+ found = crypto_has_hash(algo, 0, swcr_no_ahash?CRYPTO_ALG_ASYNC:0); -+ break; -+ case SW_TYPE_HASH: -+ found = crypto_has_hash(algo, 0, swcr_no_ahash?CRYPTO_ALG_ASYNC:0); -+ break; -+ case SW_TYPE_COMP: -+ found = crypto_has_comp(algo, 0, CRYPTO_ALG_ASYNC); -+ break; -+ case SW_TYPE_BLKCIPHER: -+ found = crypto_has_blkcipher(algo, 0, CRYPTO_ALG_ASYNC); -+ if (!found && !swcr_no_ablk) -+ found = crypto_has_ablkcipher(algo, 0, 0); -+ break; -+ } -+ if (found) { -+ REGISTER(i); -+ } else { -+ dprintk("%s:Algorithm Type %d not supported (algorithm %d:'%s')\n", -+ __FUNCTION__, sw_type, i, algo); -+ } -+ } -+ return 0; -+} -+ -+static void -+cryptosoft_exit(void) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ crypto_unregister_all(swcr_id); -+ swcr_id = -1; -+ kmem_cache_destroy(swcr_req_cache); -+} -+ -+late_initcall(cryptosoft_init); -+module_exit(cryptosoft_exit); -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("Cryptosoft (OCF module for kernel crypto)"); -diff -Nur linux-2.6.39.orig/crypto/ocf/ep80579/Makefile linux-2.6.39/crypto/ocf/ep80579/Makefile ---- linux-2.6.39.orig/crypto/ocf/ep80579/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/ep80579/Makefile 2011-08-01 14:38:18.000000000 +0200 -@@ -0,0 +1,119 @@ -+######################################################################### -+# -+# Targets supported -+# all - builds everything and installs -+# install - identical to all -+# depend - build dependencies -+# clean - clears derived objects except the .depend files -+# distclean- clears all derived objects and the .depend file -+# -+# @par -+# This file is provided under a dual BSD/GPLv2 license. When using or -+# redistributing this file, you may do so under either license. -+# -+# GPL LICENSE SUMMARY -+# -+# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+# -+# This program is free software; you can redistribute it and/or modify -+# it under the terms of version 2 of the GNU General Public License as -+# published by the Free Software Foundation. -+# -+# This program is distributed in the hope that it will be useful, but -+# WITHOUT ANY WARRANTY; without even the implied warranty of -+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+# General Public License for more details. -+# -+# You should have received a copy of the GNU General Public License -+# along with this program; if not, write to the Free Software -+# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. -+# The full GNU General Public License is included in this distribution -+# in the file called LICENSE.GPL. -+# -+# Contact Information: -+# Intel Corporation -+# -+# BSD LICENSE -+# -+# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+# All rights reserved. -+# -+# Redistribution and use in source and binary forms, with or without -+# modification, are permitted provided that the following conditions -+# are met: -+# -+# * Redistributions of source code must retain the above copyright -+# notice, this list of conditions and the following disclaimer. -+# * Redistributions in binary form must reproduce the above copyright -+# notice, this list of conditions and the following disclaimer in -+# the documentation and/or other materials provided with the -+# distribution. -+# * Neither the name of Intel Corporation nor the names of its -+# contributors may be used to endorse or promote products derived -+# from this software without specific prior written permission. -+# -+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+# -+# -+# version: Security.L.1.0.2-229 -+############################################################################ -+ -+ -+####################Common variables and definitions######################## -+ -+ifndef ICP_ROOT -+$(warning ICP_ROOT is undefined. Please set the path to EP80579 release package directory \ -+ "-> setenv ICP_ROOT ") -+all fastdep: -+ : -+else -+ -+ifndef KERNEL_SOURCE_ROOT -+$(error KERNEL_SOURCE_ROOT is undefined. Please set the path to the kernel source directory \ -+ "-> setenv KERNEL_SOURCE_ROOT ") -+endif -+ -+# Ensure The ENV_DIR environmental var is defined. -+ifndef ICP_ENV_DIR -+$(error ICP_ENV_DIR is undefined. Please set the path to EP80579 driver environment.mk file \ -+ "-> setenv ICP_ENV_DIR ") -+endif -+ -+#Add your project environment Makefile -+include ${ICP_ENV_DIR}/environment.mk -+ -+#include the makefile with all the default and common Make variable definitions -+include ${ICP_BUILDSYSTEM_PATH}/build_files/common.mk -+ -+#Add the name for the executable, Library or Module output definitions -+OUTPUT_NAME= icp_ocf -+ -+# List of Source Files to be compiled -+SOURCES= icp_common.c icp_sym.c icp_asym.c icp_ocf_linux.c -+ -+#common includes between all supported OSes -+INCLUDES= -I ${ICP_API_DIR} -I${ICP_LAC_API} \ -+-I${ICP_OCF_SRC_DIR} -+ -+# The location of the os level makefile needs to be changed. -+include ${ICP_ENV_DIR}/${ICP_OS}_${ICP_OS_LEVEL}.mk -+ -+# On the line directly below list the outputs you wish to build for, -+# e.g "lib_static lib_shared exe module" as shown below -+install: module -+ -+###################Include rules makefiles######################## -+include ${ICP_BUILDSYSTEM_PATH}/build_files/rules.mk -+###################End of Rules inclusion######################### -+ -+endif -diff -Nur linux-2.6.39.orig/crypto/ocf/ep80579/icp_asym.c linux-2.6.39/crypto/ocf/ep80579/icp_asym.c ---- linux-2.6.39.orig/crypto/ocf/ep80579/icp_asym.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/ep80579/icp_asym.c 2011-08-01 14:38:18.000000000 +0200 -@@ -0,0 +1,1334 @@ -+/*************************************************************************** -+ * -+ * This file is provided under a dual BSD/GPLv2 license. When using or -+ * redistributing this file, you may do so under either license. -+ * -+ * GPL LICENSE SUMMARY -+ * -+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of version 2 of the GNU General Public License as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. -+ * The full GNU General Public License is included in this distribution -+ * in the file called LICENSE.GPL. -+ * -+ * Contact Information: -+ * Intel Corporation -+ * -+ * BSD LICENSE -+ * -+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * * Neither the name of Intel Corporation nor the names of its -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * -+ * version: Security.L.1.0.2-229 -+ * -+ ***************************************************************************/ -+ -+#include "icp_ocf.h" -+ -+/*The following define values (containing the word 'INDEX') are used to find -+the index of each input buffer of the crypto_kop struct (see OCF cryptodev.h). -+These values were found through analysis of the OCF OpenSSL patch. If the -+calling program uses different input buffer positions, these defines will have -+to be changed.*/ -+ -+/*DIFFIE HELLMAN buffer index values*/ -+#define ICP_DH_KRP_PARAM_PRIME_INDEX (0) -+#define ICP_DH_KRP_PARAM_BASE_INDEX (1) -+#define ICP_DH_KRP_PARAM_PRIVATE_VALUE_INDEX (2) -+#define ICP_DH_KRP_PARAM_RESULT_INDEX (3) -+ -+/*MOD EXP buffer index values*/ -+#define ICP_MOD_EXP_KRP_PARAM_BASE_INDEX (0) -+#define ICP_MOD_EXP_KRP_PARAM_EXPONENT_INDEX (1) -+#define ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX (2) -+#define ICP_MOD_EXP_KRP_PARAM_RESULT_INDEX (3) -+ -+/*MOD EXP CRT buffer index values*/ -+#define ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_P_INDEX (0) -+#define ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_Q_INDEX (1) -+#define ICP_MOD_EXP_CRT_KRP_PARAM_I_INDEX (2) -+#define ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DP_INDEX (3) -+#define ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DQ_INDEX (4) -+#define ICP_MOD_EXP_CRT_KRP_PARAM_COEFF_QINV_INDEX (5) -+#define ICP_MOD_EXP_CRT_KRP_PARAM_RESULT_INDEX (6) -+ -+/*DSA sign buffer index values*/ -+#define ICP_DSA_SIGN_KRP_PARAM_DGST_INDEX (0) -+#define ICP_DSA_SIGN_KRP_PARAM_PRIME_P_INDEX (1) -+#define ICP_DSA_SIGN_KRP_PARAM_PRIME_Q_INDEX (2) -+#define ICP_DSA_SIGN_KRP_PARAM_G_INDEX (3) -+#define ICP_DSA_SIGN_KRP_PARAM_X_INDEX (4) -+#define ICP_DSA_SIGN_KRP_PARAM_R_RESULT_INDEX (5) -+#define ICP_DSA_SIGN_KRP_PARAM_S_RESULT_INDEX (6) -+ -+/*DSA verify buffer index values*/ -+#define ICP_DSA_VERIFY_KRP_PARAM_DGST_INDEX (0) -+#define ICP_DSA_VERIFY_KRP_PARAM_PRIME_P_INDEX (1) -+#define ICP_DSA_VERIFY_KRP_PARAM_PRIME_Q_INDEX (2) -+#define ICP_DSA_VERIFY_KRP_PARAM_G_INDEX (3) -+#define ICP_DSA_VERIFY_KRP_PARAM_PUBKEY_INDEX (4) -+#define ICP_DSA_VERIFY_KRP_PARAM_SIG_R_INDEX (5) -+#define ICP_DSA_VERIFY_KRP_PARAM_SIG_S_INDEX (6) -+ -+/*DSA sign prime Q vs random number K size check values*/ -+#define DONT_RUN_LESS_THAN_CHECK (0) -+#define FAIL_A_IS_GREATER_THAN_B (1) -+#define FAIL_A_IS_EQUAL_TO_B (1) -+#define SUCCESS_A_IS_LESS_THAN_B (0) -+#define DSA_SIGN_RAND_GEN_VAL_CHECK_MAX_ITERATIONS (500) -+ -+/* We need to set a cryptokp success value just in case it is set or allocated -+ and not set to zero outside of this module */ -+#define CRYPTO_OP_SUCCESS (0) -+ -+/*Function to compute Diffie Hellman (DH) phase 1 or phase 2 key values*/ -+static int icp_ocfDrvDHComputeKey(struct cryptkop *krp); -+ -+/*Function to compute a Modular Exponentiation (Mod Exp)*/ -+static int icp_ocfDrvModExp(struct cryptkop *krp); -+ -+/*Function to compute a Mod Exp using the Chinease Remainder Theorem*/ -+static int icp_ocfDrvModExpCRT(struct cryptkop *krp); -+ -+/*Helper function to compute whether the first big number argument is less than -+ the second big number argument */ -+static int -+icp_ocfDrvCheckALessThanB(CpaFlatBuffer * pK, CpaFlatBuffer * pQ, int *doCheck); -+ -+/*Function to sign an input with DSA R and S keys*/ -+static int icp_ocfDrvDsaSign(struct cryptkop *krp); -+ -+/*Function to Verify a DSA buffer signature*/ -+static int icp_ocfDrvDsaVerify(struct cryptkop *krp); -+ -+/*Callback function for DH operation*/ -+static void -+icp_ocfDrvDhP1CallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, CpaFlatBuffer * pLocalOctetStringPV); -+ -+/*Callback function for ME operation*/ -+static void -+icp_ocfDrvModExpCallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, CpaFlatBuffer * pResult); -+ -+/*Callback function for ME CRT operation*/ -+static void -+icp_ocfDrvModExpCRTCallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, CpaFlatBuffer * pOutputData); -+ -+/*Callback function for DSA sign operation*/ -+static void -+icp_ocfDrvDsaRSSignCallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, -+ CpaBoolean protocolStatus, -+ CpaFlatBuffer * pR, CpaFlatBuffer * pS); -+ -+/*Callback function for DSA Verify operation*/ -+static void -+icp_ocfDrvDsaVerifyCallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, CpaBoolean verifyStatus); -+ -+/* Name : icp_ocfDrvPkeProcess -+ * -+ * Description : This function will choose which PKE process to follow -+ * based on the input arguments -+ */ -+int icp_ocfDrvPkeProcess(icp_device_t dev, struct cryptkop *krp, int hint) -+{ -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ -+ if (NULL == krp) { -+ DPRINTK("%s(): Invalid input parameters, cryptkop = %p\n", -+ __FUNCTION__, krp); -+ return EINVAL; -+ } -+ -+ if (CPA_TRUE == icp_atomic_read(&icp_ocfDrvIsExiting)) { -+ krp->krp_status = ECANCELED; -+ return ECANCELED; -+ } -+ -+ switch (krp->krp_op) { -+ case CRK_DH_COMPUTE_KEY: -+ DPRINTK("%s() doing DH_COMPUTE_KEY\n", __FUNCTION__); -+ lacStatus = icp_ocfDrvDHComputeKey(krp); -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): icp_ocfDrvDHComputeKey failed " -+ "(%d).\n", __FUNCTION__, lacStatus); -+ krp->krp_status = ECANCELED; -+ return ECANCELED; -+ } -+ -+ break; -+ -+ case CRK_MOD_EXP: -+ DPRINTK("%s() doing MOD_EXP \n", __FUNCTION__); -+ lacStatus = icp_ocfDrvModExp(krp); -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): icp_ocfDrvModExp failed (%d).\n", -+ __FUNCTION__, lacStatus); -+ krp->krp_status = ECANCELED; -+ return ECANCELED; -+ } -+ -+ break; -+ -+ case CRK_MOD_EXP_CRT: -+ DPRINTK("%s() doing MOD_EXP_CRT \n", __FUNCTION__); -+ lacStatus = icp_ocfDrvModExpCRT(krp); -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): icp_ocfDrvModExpCRT " -+ "failed (%d).\n", __FUNCTION__, lacStatus); -+ krp->krp_status = ECANCELED; -+ return ECANCELED; -+ } -+ -+ break; -+ -+ case CRK_DSA_SIGN: -+ DPRINTK("%s() doing DSA_SIGN \n", __FUNCTION__); -+ lacStatus = icp_ocfDrvDsaSign(krp); -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): icp_ocfDrvDsaSign " -+ "failed (%d).\n", __FUNCTION__, lacStatus); -+ krp->krp_status = ECANCELED; -+ return ECANCELED; -+ } -+ -+ break; -+ -+ case CRK_DSA_VERIFY: -+ DPRINTK("%s() doing DSA_VERIFY \n", __FUNCTION__); -+ lacStatus = icp_ocfDrvDsaVerify(krp); -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): icp_ocfDrvDsaVerify " -+ "failed (%d).\n", __FUNCTION__, lacStatus); -+ krp->krp_status = ECANCELED; -+ return ECANCELED; -+ } -+ -+ break; -+ -+ default: -+ EPRINTK("%s(): Asymettric function not " -+ "supported (%d).\n", __FUNCTION__, krp->krp_op); -+ krp->krp_status = EOPNOTSUPP; -+ return EOPNOTSUPP; -+ } -+ -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+} -+ -+/* Name : icp_ocfDrvSwapBytes -+ * -+ * Description : This function is used to swap the byte order of a buffer. -+ * It has been seen that in general we are passed little endian byte order -+ * buffers, but LAC only accepts big endian byte order buffers. -+ */ -+static void inline icp_ocfDrvSwapBytes(u_int8_t * num, u_int32_t buff_len_bytes) -+{ -+ -+ int i; -+ u_int8_t *end_ptr; -+ u_int8_t hold_val; -+ -+ end_ptr = num + (buff_len_bytes - 1); -+ buff_len_bytes = buff_len_bytes >> 1; -+ for (i = 0; i < buff_len_bytes; i++) { -+ hold_val = *num; -+ *num = *end_ptr; -+ num++; -+ *end_ptr = hold_val; -+ end_ptr--; -+ } -+} -+ -+/* Name : icp_ocfDrvDHComputeKey -+ * -+ * Description : This function will map Diffie Hellman calls from OCF -+ * to the LAC API. OCF uses this function for Diffie Hellman Phase1 and -+ * Phase2. LAC has a separate Diffie Hellman Phase2 call, however both phases -+ * break down to a modular exponentiation. -+ */ -+static int icp_ocfDrvDHComputeKey(struct cryptkop *krp) -+{ -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ void *callbackTag = NULL; -+ CpaCyDhPhase1KeyGenOpData *pPhase1OpData = NULL; -+ CpaFlatBuffer *pLocalOctetStringPV = NULL; -+ uint32_t dh_prime_len_bytes = 0, dh_prime_len_bits = 0; -+ -+ /* Input checks - check prime is a multiple of 8 bits to allow for -+ allocation later */ -+ dh_prime_len_bits = -+ (krp->krp_param[ICP_DH_KRP_PARAM_PRIME_INDEX].crp_nbits); -+ -+ /* LAC can reject prime lengths based on prime key sizes, we just -+ need to make sure we can allocate space for the base and -+ exponent buffers correctly */ -+ if ((dh_prime_len_bits % NUM_BITS_IN_BYTE) != 0) { -+ APRINTK("%s(): Warning Prime number buffer size is not a " -+ "multiple of 8 bits\n", __FUNCTION__); -+ } -+ -+ /* Result storage space should be the same size as the prime as this -+ value can take up the same amount of storage space */ -+ if (dh_prime_len_bits != -+ krp->krp_param[ICP_DH_KRP_PARAM_RESULT_INDEX].crp_nbits) { -+ DPRINTK("%s(): Return Buffer must be the same size " -+ "as the Prime buffer\n", __FUNCTION__); -+ krp->krp_status = EINVAL; -+ return EINVAL; -+ } -+ /* Switch to size in bytes */ -+ BITS_TO_BYTES(dh_prime_len_bytes, dh_prime_len_bits); -+ -+ callbackTag = krp; -+ -+/*All allocations are set to ICP_M_NOWAIT due to the possibility of getting -+called in interrupt context*/ -+ pPhase1OpData = icp_kmem_cache_zalloc(drvDH_zone, ICP_M_NOWAIT); -+ if (NULL == pPhase1OpData) { -+ APRINTK("%s():Failed to get memory for key gen data\n", -+ __FUNCTION__); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ pLocalOctetStringPV = -+ icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); -+ if (NULL == pLocalOctetStringPV) { -+ APRINTK("%s():Failed to get memory for pLocalOctetStringPV\n", -+ __FUNCTION__); -+ ICP_CACHE_FREE(drvDH_zone, pPhase1OpData); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ /* Link parameters */ -+ pPhase1OpData->primeP.pData = -+ krp->krp_param[ICP_DH_KRP_PARAM_PRIME_INDEX].crp_p; -+ -+ pPhase1OpData->primeP.dataLenInBytes = dh_prime_len_bytes; -+ -+ icp_ocfDrvSwapBytes(pPhase1OpData->primeP.pData, dh_prime_len_bytes); -+ -+ pPhase1OpData->baseG.pData = -+ krp->krp_param[ICP_DH_KRP_PARAM_BASE_INDEX].crp_p; -+ -+ BITS_TO_BYTES(pPhase1OpData->baseG.dataLenInBytes, -+ krp->krp_param[ICP_DH_KRP_PARAM_BASE_INDEX].crp_nbits); -+ -+ icp_ocfDrvSwapBytes(pPhase1OpData->baseG.pData, -+ pPhase1OpData->baseG.dataLenInBytes); -+ -+ pPhase1OpData->privateValueX.pData = -+ krp->krp_param[ICP_DH_KRP_PARAM_PRIVATE_VALUE_INDEX].crp_p; -+ -+ BITS_TO_BYTES(pPhase1OpData->privateValueX.dataLenInBytes, -+ krp->krp_param[ICP_DH_KRP_PARAM_PRIVATE_VALUE_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(pPhase1OpData->privateValueX.pData, -+ pPhase1OpData->privateValueX.dataLenInBytes); -+ -+ /* Output parameters */ -+ pLocalOctetStringPV->pData = -+ krp->krp_param[ICP_DH_KRP_PARAM_RESULT_INDEX].crp_p; -+ -+ BITS_TO_BYTES(pLocalOctetStringPV->dataLenInBytes, -+ krp->krp_param[ICP_DH_KRP_PARAM_RESULT_INDEX].crp_nbits); -+ -+ lacStatus = cpaCyDhKeyGenPhase1(CPA_INSTANCE_HANDLE_SINGLE, -+ icp_ocfDrvDhP1CallBack, -+ callbackTag, pPhase1OpData, -+ pLocalOctetStringPV); -+ -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): DH Phase 1 Key Gen failed (%d).\n", -+ __FUNCTION__, lacStatus); -+ icp_ocfDrvFreeFlatBuffer(pLocalOctetStringPV); -+ ICP_CACHE_FREE(drvDH_zone, pPhase1OpData); -+ } -+ -+ return lacStatus; -+} -+ -+/* Name : icp_ocfDrvModExp -+ * -+ * Description : This function will map ordinary Modular Exponentiation calls -+ * from OCF to the LAC API. -+ * -+ */ -+static int icp_ocfDrvModExp(struct cryptkop *krp) -+{ -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ void *callbackTag = NULL; -+ CpaCyLnModExpOpData *pModExpOpData = NULL; -+ CpaFlatBuffer *pResult = NULL; -+ -+ if ((krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX].crp_nbits % -+ NUM_BITS_IN_BYTE) != 0) { -+ DPRINTK("%s(): Warning - modulus buffer size (%d) is not a " -+ "multiple of 8 bits\n", __FUNCTION__, -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX]. -+ crp_nbits); -+ } -+ -+ /* Result storage space should be the same size as the prime as this -+ value can take up the same amount of storage space */ -+ if (krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX].crp_nbits > -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_RESULT_INDEX].crp_nbits) { -+ APRINTK("%s(): Return Buffer size must be the same or" -+ " greater than the Modulus buffer\n", __FUNCTION__); -+ krp->krp_status = EINVAL; -+ return EINVAL; -+ } -+ -+ callbackTag = krp; -+ -+ pModExpOpData = icp_kmem_cache_zalloc(drvLnModExp_zone, ICP_M_NOWAIT); -+ if (NULL == pModExpOpData) { -+ APRINTK("%s():Failed to get memory for key gen data\n", -+ __FUNCTION__); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ pResult = icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); -+ if (NULL == pResult) { -+ APRINTK("%s():Failed to get memory for ModExp result\n", -+ __FUNCTION__); -+ ICP_CACHE_FREE(drvLnModExp_zone, pModExpOpData); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ /* Link parameters */ -+ pModExpOpData->modulus.pData = -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX].crp_p; -+ BITS_TO_BYTES(pModExpOpData->modulus.dataLenInBytes, -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(pModExpOpData->modulus.pData, -+ pModExpOpData->modulus.dataLenInBytes); -+ -+ DPRINTK("%s : base (%d)\n", __FUNCTION__, krp-> -+ krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX].crp_nbits); -+ pModExpOpData->base.pData = -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX].crp_p; -+ BITS_TO_BYTES(pModExpOpData->base.dataLenInBytes, -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX]. -+ crp_nbits); -+ icp_ocfDrvSwapBytes(pModExpOpData->base.pData, -+ pModExpOpData->base.dataLenInBytes); -+ -+ pModExpOpData->exponent.pData = -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_EXPONENT_INDEX].crp_p; -+ BITS_TO_BYTES(pModExpOpData->exponent.dataLenInBytes, -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_EXPONENT_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(pModExpOpData->exponent.pData, -+ pModExpOpData->exponent.dataLenInBytes); -+ /* Output parameters */ -+ pResult->pData = -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_RESULT_INDEX].crp_p, -+ BITS_TO_BYTES(pResult->dataLenInBytes, -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_RESULT_INDEX]. -+ crp_nbits); -+ -+ lacStatus = cpaCyLnModExp(CPA_INSTANCE_HANDLE_SINGLE, -+ icp_ocfDrvModExpCallBack, -+ callbackTag, pModExpOpData, pResult); -+ -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): Mod Exp Operation failed (%d).\n", -+ __FUNCTION__, lacStatus); -+ krp->krp_status = ECANCELED; -+ icp_ocfDrvFreeFlatBuffer(pResult); -+ ICP_CACHE_FREE(drvLnModExp_zone, pModExpOpData); -+ } -+ -+ return lacStatus; -+} -+ -+/* Name : icp_ocfDrvModExpCRT -+ * -+ * Description : This function will map ordinary Modular Exponentiation Chinese -+ * Remainder Theorem implementaion calls from OCF to the LAC API. -+ * -+ * Note : Mod Exp CRT for this driver is accelerated through LAC RSA type 2 -+ * decrypt operation. Therefore P and Q input values must always be prime -+ * numbers. Although basic primality checks are done in LAC, it is up to the -+ * user to do any correct prime number checking before passing the inputs. -+ */ -+static int icp_ocfDrvModExpCRT(struct cryptkop *krp) -+{ -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ CpaCyRsaDecryptOpData *rsaDecryptOpData = NULL; -+ void *callbackTag = NULL; -+ CpaFlatBuffer *pOutputData = NULL; -+ -+ /*Parameter input checks are all done by LAC, no need to repeat -+ them here. */ -+ callbackTag = krp; -+ -+ rsaDecryptOpData = -+ icp_kmem_cache_zalloc(drvRSADecrypt_zone, ICP_M_NOWAIT); -+ if (NULL == rsaDecryptOpData) { -+ APRINTK("%s():Failed to get memory" -+ " for MOD EXP CRT Op data struct\n", __FUNCTION__); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ rsaDecryptOpData->pRecipientPrivateKey -+ = icp_kmem_cache_zalloc(drvRSAPrivateKey_zone, ICP_M_NOWAIT); -+ if (NULL == rsaDecryptOpData->pRecipientPrivateKey) { -+ APRINTK("%s():Failed to get memory for MOD EXP CRT" -+ " private key values struct\n", __FUNCTION__); -+ ICP_CACHE_FREE(drvRSADecrypt_zone, rsaDecryptOpData); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ version = CPA_CY_RSA_VERSION_TWO_PRIME; -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRepType = CPA_CY_RSA_PRIVATE_KEY_REP_TYPE_2; -+ -+ pOutputData = icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); -+ if (NULL == pOutputData) { -+ APRINTK("%s():Failed to get memory" -+ " for MOD EXP CRT output data\n", __FUNCTION__); -+ ICP_CACHE_FREE(drvRSAPrivateKey_zone, -+ rsaDecryptOpData->pRecipientPrivateKey); -+ ICP_CACHE_FREE(drvRSADecrypt_zone, rsaDecryptOpData); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ version = CPA_CY_RSA_VERSION_TWO_PRIME; -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRepType = CPA_CY_RSA_PRIVATE_KEY_REP_TYPE_2; -+ -+ /* Link parameters */ -+ rsaDecryptOpData->inputData.pData = -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_I_INDEX].crp_p; -+ BITS_TO_BYTES(rsaDecryptOpData->inputData.dataLenInBytes, -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_I_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(rsaDecryptOpData->inputData.pData, -+ rsaDecryptOpData->inputData.dataLenInBytes); -+ -+ rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2.prime1P.pData = -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_P_INDEX].crp_p; -+ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2. -+ prime1P.dataLenInBytes, -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_P_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.prime1P.pData, -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.prime1P.dataLenInBytes); -+ -+ rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2.prime2Q.pData = -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_Q_INDEX].crp_p; -+ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2. -+ prime2Q.dataLenInBytes, -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_Q_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.prime2Q.pData, -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.prime2Q.dataLenInBytes); -+ -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.exponent1Dp.pData = -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DP_INDEX].crp_p; -+ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2. -+ exponent1Dp.dataLenInBytes, -+ krp-> -+ krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DP_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.exponent1Dp.pData, -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.exponent1Dp.dataLenInBytes); -+ -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.exponent2Dq.pData = -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DQ_INDEX].crp_p; -+ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.exponent2Dq.dataLenInBytes, -+ krp-> -+ krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DQ_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.exponent2Dq.pData, -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.exponent2Dq.dataLenInBytes); -+ -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.coefficientQInv.pData = -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_COEFF_QINV_INDEX].crp_p; -+ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.coefficientQInv.dataLenInBytes, -+ krp-> -+ krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_COEFF_QINV_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.coefficientQInv.pData, -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.coefficientQInv.dataLenInBytes); -+ -+ /* Output Parameter */ -+ pOutputData->pData = -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_RESULT_INDEX].crp_p; -+ BITS_TO_BYTES(pOutputData->dataLenInBytes, -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_RESULT_INDEX]. -+ crp_nbits); -+ -+ lacStatus = cpaCyRsaDecrypt(CPA_INSTANCE_HANDLE_SINGLE, -+ icp_ocfDrvModExpCRTCallBack, -+ callbackTag, rsaDecryptOpData, pOutputData); -+ -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): Mod Exp CRT Operation failed (%d).\n", -+ __FUNCTION__, lacStatus); -+ krp->krp_status = ECANCELED; -+ icp_ocfDrvFreeFlatBuffer(pOutputData); -+ ICP_CACHE_FREE(drvRSAPrivateKey_zone, -+ rsaDecryptOpData->pRecipientPrivateKey); -+ ICP_CACHE_FREE(drvRSADecrypt_zone, rsaDecryptOpData); -+ } -+ -+ return lacStatus; -+} -+ -+/* Name : icp_ocfDrvCheckALessThanB -+ * -+ * Description : This function will check whether the first argument is less -+ * than the second. It is used to check whether the DSA RS sign Random K -+ * value is less than the Prime Q value (as defined in the specification) -+ * -+ */ -+static int -+icp_ocfDrvCheckALessThanB(CpaFlatBuffer * pK, CpaFlatBuffer * pQ, int *doCheck) -+{ -+ -+ uint8_t *MSB_K = pK->pData; -+ uint8_t *MSB_Q = pQ->pData; -+ uint32_t buffer_lengths_in_bytes = pQ->dataLenInBytes; -+ -+ if (DONT_RUN_LESS_THAN_CHECK == *doCheck) { -+ return FAIL_A_IS_GREATER_THAN_B; -+ } -+ -+/*Check MSBs -+if A == B, check next MSB -+if A > B, return A_IS_GREATER_THAN_B -+if A < B, return A_IS_LESS_THAN_B (success) -+*/ -+ while (*MSB_K == *MSB_Q) { -+ MSB_K++; -+ MSB_Q++; -+ -+ buffer_lengths_in_bytes--; -+ if (0 == buffer_lengths_in_bytes) { -+ DPRINTK("%s() Buffers have equal value!!\n", -+ __FUNCTION__); -+ return FAIL_A_IS_EQUAL_TO_B; -+ } -+ -+ } -+ -+ if (*MSB_K < *MSB_Q) { -+ return SUCCESS_A_IS_LESS_THAN_B; -+ } else { -+ return FAIL_A_IS_GREATER_THAN_B; -+ } -+ -+} -+ -+/* Name : icp_ocfDrvDsaSign -+ * -+ * Description : This function will map DSA RS Sign from OCF to the LAC API. -+ * -+ * NOTE: From looking at OCF patch to OpenSSL and even the number of input -+ * parameters, OCF expects us to generate the random seed value. This value -+ * is generated and passed to LAC, however the number is discared in the -+ * callback and not returned to the user. -+ */ -+static int icp_ocfDrvDsaSign(struct cryptkop *krp) -+{ -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ CpaCyDsaRSSignOpData *dsaRsSignOpData = NULL; -+ void *callbackTag = NULL; -+ CpaCyRandGenOpData randGenOpData; -+ int primeQSizeInBytes = 0; -+ int doCheck = 0; -+ CpaFlatBuffer randData; -+ CpaBoolean protocolStatus = CPA_FALSE; -+ CpaFlatBuffer *pR = NULL; -+ CpaFlatBuffer *pS = NULL; -+ -+ callbackTag = krp; -+ -+ BITS_TO_BYTES(primeQSizeInBytes, -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_Q_INDEX]. -+ crp_nbits); -+ -+ if (DSA_RS_SIGN_PRIMEQ_SIZE_IN_BYTES != primeQSizeInBytes) { -+ APRINTK("%s(): DSA PRIME Q size not equal to the " -+ "FIPS defined 20bytes, = %d\n", -+ __FUNCTION__, primeQSizeInBytes); -+ krp->krp_status = EDOM; -+ return EDOM; -+ } -+ -+ dsaRsSignOpData = -+ icp_kmem_cache_zalloc(drvDSARSSign_zone, ICP_M_NOWAIT); -+ if (NULL == dsaRsSignOpData) { -+ APRINTK("%s():Failed to get memory" -+ " for DSA RS Sign Op data struct\n", __FUNCTION__); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ dsaRsSignOpData->K.pData = -+ icp_kmem_cache_alloc(drvDSARSSignKValue_zone, ICP_M_NOWAIT); -+ -+ if (NULL == dsaRsSignOpData->K.pData) { -+ APRINTK("%s():Failed to get memory" -+ " for DSA RS Sign Op Random value\n", __FUNCTION__); -+ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ pR = icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); -+ if (NULL == pR) { -+ APRINTK("%s():Failed to get memory" -+ " for DSA signature R\n", __FUNCTION__); -+ ICP_CACHE_FREE(drvDSARSSignKValue_zone, -+ dsaRsSignOpData->K.pData); -+ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ pS = icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); -+ if (NULL == pS) { -+ APRINTK("%s():Failed to get memory" -+ " for DSA signature S\n", __FUNCTION__); -+ icp_ocfDrvFreeFlatBuffer(pR); -+ ICP_CACHE_FREE(drvDSARSSignKValue_zone, -+ dsaRsSignOpData->K.pData); -+ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ /*link prime number parameter for ease of processing */ -+ dsaRsSignOpData->P.pData = -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_P_INDEX].crp_p; -+ BITS_TO_BYTES(dsaRsSignOpData->P.dataLenInBytes, -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_P_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(dsaRsSignOpData->P.pData, -+ dsaRsSignOpData->P.dataLenInBytes); -+ -+ dsaRsSignOpData->Q.pData = -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_Q_INDEX].crp_p; -+ BITS_TO_BYTES(dsaRsSignOpData->Q.dataLenInBytes, -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_Q_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(dsaRsSignOpData->Q.pData, -+ dsaRsSignOpData->Q.dataLenInBytes); -+ -+ /*generate random number with equal buffer size to Prime value Q, -+ but value less than Q */ -+ dsaRsSignOpData->K.dataLenInBytes = dsaRsSignOpData->Q.dataLenInBytes; -+ -+ randGenOpData.generateBits = CPA_TRUE; -+ randGenOpData.lenInBytes = dsaRsSignOpData->K.dataLenInBytes; -+ -+ icp_ocfDrvPtrAndLenToFlatBuffer(dsaRsSignOpData->K.pData, -+ dsaRsSignOpData->K.dataLenInBytes, -+ &randData); -+ -+ doCheck = 0; -+ while (icp_ocfDrvCheckALessThanB(&(dsaRsSignOpData->K), -+ &(dsaRsSignOpData->Q), &doCheck)) { -+ -+ if (CPA_STATUS_SUCCESS -+ != cpaCyRandGen(CPA_INSTANCE_HANDLE_SINGLE, -+ NULL, NULL, &randGenOpData, &randData)) { -+ APRINTK("%s(): ERROR - Failed to generate DSA RS Sign K" -+ "value\n", __FUNCTION__); -+ icp_ocfDrvFreeFlatBuffer(pS); -+ icp_ocfDrvFreeFlatBuffer(pR); -+ ICP_CACHE_FREE(drvDSARSSignKValue_zone, -+ dsaRsSignOpData->K.pData); -+ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); -+ krp->krp_status = EAGAIN; -+ return EAGAIN; -+ } -+ -+ doCheck++; -+ if (DSA_SIGN_RAND_GEN_VAL_CHECK_MAX_ITERATIONS == doCheck) { -+ APRINTK("%s(): ERROR - Failed to find DSA RS Sign K " -+ "value less than Q value\n", __FUNCTION__); -+ icp_ocfDrvFreeFlatBuffer(pS); -+ icp_ocfDrvFreeFlatBuffer(pR); -+ ICP_CACHE_FREE(drvDSARSSignKValue_zone, -+ dsaRsSignOpData->K.pData); -+ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); -+ krp->krp_status = EAGAIN; -+ return EAGAIN; -+ } -+ -+ } -+ /*Rand Data - no need to swap bytes for pK */ -+ -+ /* Link parameters */ -+ dsaRsSignOpData->G.pData = -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_G_INDEX].crp_p; -+ BITS_TO_BYTES(dsaRsSignOpData->G.dataLenInBytes, -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_G_INDEX].crp_nbits); -+ -+ icp_ocfDrvSwapBytes(dsaRsSignOpData->G.pData, -+ dsaRsSignOpData->G.dataLenInBytes); -+ -+ dsaRsSignOpData->X.pData = -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_X_INDEX].crp_p; -+ BITS_TO_BYTES(dsaRsSignOpData->X.dataLenInBytes, -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_X_INDEX].crp_nbits); -+ icp_ocfDrvSwapBytes(dsaRsSignOpData->X.pData, -+ dsaRsSignOpData->X.dataLenInBytes); -+ -+ /*OpenSSL dgst parameter is left in big endian byte order, -+ therefore no byte swap is required */ -+ dsaRsSignOpData->M.pData = -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_DGST_INDEX].crp_p; -+ BITS_TO_BYTES(dsaRsSignOpData->M.dataLenInBytes, -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_DGST_INDEX]. -+ crp_nbits); -+ -+ /* Output Parameters */ -+ pS->pData = krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_S_RESULT_INDEX].crp_p; -+ BITS_TO_BYTES(pS->dataLenInBytes, -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_S_RESULT_INDEX]. -+ crp_nbits); -+ -+ pR->pData = krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_R_RESULT_INDEX].crp_p; -+ BITS_TO_BYTES(pR->dataLenInBytes, -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_R_RESULT_INDEX]. -+ crp_nbits); -+ -+ lacStatus = cpaCyDsaSignRS(CPA_INSTANCE_HANDLE_SINGLE, -+ icp_ocfDrvDsaRSSignCallBack, -+ callbackTag, dsaRsSignOpData, -+ &protocolStatus, pR, pS); -+ -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): DSA RS Sign Operation failed (%d).\n", -+ __FUNCTION__, lacStatus); -+ krp->krp_status = ECANCELED; -+ icp_ocfDrvFreeFlatBuffer(pS); -+ icp_ocfDrvFreeFlatBuffer(pR); -+ ICP_CACHE_FREE(drvDSARSSignKValue_zone, -+ dsaRsSignOpData->K.pData); -+ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); -+ } -+ -+ return lacStatus; -+} -+ -+/* Name : icp_ocfDrvDsaVerify -+ * -+ * Description : This function will map DSA RS Verify from OCF to the LAC API. -+ * -+ */ -+static int icp_ocfDrvDsaVerify(struct cryptkop *krp) -+{ -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ CpaCyDsaVerifyOpData *dsaVerifyOpData = NULL; -+ void *callbackTag = NULL; -+ CpaBoolean verifyStatus = CPA_FALSE; -+ -+ callbackTag = krp; -+ -+ dsaVerifyOpData = -+ icp_kmem_cache_zalloc(drvDSAVerify_zone, ICP_M_NOWAIT); -+ if (NULL == dsaVerifyOpData) { -+ APRINTK("%s():Failed to get memory" -+ " for DSA Verify Op data struct\n", __FUNCTION__); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ /* Link parameters */ -+ dsaVerifyOpData->P.pData = -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PRIME_P_INDEX].crp_p; -+ BITS_TO_BYTES(dsaVerifyOpData->P.dataLenInBytes, -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PRIME_P_INDEX]. -+ crp_nbits); -+ icp_ocfDrvSwapBytes(dsaVerifyOpData->P.pData, -+ dsaVerifyOpData->P.dataLenInBytes); -+ -+ dsaVerifyOpData->Q.pData = -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PRIME_Q_INDEX].crp_p; -+ BITS_TO_BYTES(dsaVerifyOpData->Q.dataLenInBytes, -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PRIME_Q_INDEX]. -+ crp_nbits); -+ icp_ocfDrvSwapBytes(dsaVerifyOpData->Q.pData, -+ dsaVerifyOpData->Q.dataLenInBytes); -+ -+ dsaVerifyOpData->G.pData = -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_G_INDEX].crp_p; -+ BITS_TO_BYTES(dsaVerifyOpData->G.dataLenInBytes, -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_G_INDEX]. -+ crp_nbits); -+ icp_ocfDrvSwapBytes(dsaVerifyOpData->G.pData, -+ dsaVerifyOpData->G.dataLenInBytes); -+ -+ dsaVerifyOpData->Y.pData = -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PUBKEY_INDEX].crp_p; -+ BITS_TO_BYTES(dsaVerifyOpData->Y.dataLenInBytes, -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PUBKEY_INDEX]. -+ crp_nbits); -+ icp_ocfDrvSwapBytes(dsaVerifyOpData->Y.pData, -+ dsaVerifyOpData->Y.dataLenInBytes); -+ -+ /*OpenSSL dgst parameter is left in big endian byte order, -+ therefore no byte swap is required */ -+ dsaVerifyOpData->M.pData = -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_DGST_INDEX].crp_p; -+ BITS_TO_BYTES(dsaVerifyOpData->M.dataLenInBytes, -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_DGST_INDEX]. -+ crp_nbits); -+ -+ dsaVerifyOpData->R.pData = -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_SIG_R_INDEX].crp_p; -+ BITS_TO_BYTES(dsaVerifyOpData->R.dataLenInBytes, -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_SIG_R_INDEX]. -+ crp_nbits); -+ icp_ocfDrvSwapBytes(dsaVerifyOpData->R.pData, -+ dsaVerifyOpData->R.dataLenInBytes); -+ -+ dsaVerifyOpData->S.pData = -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_SIG_S_INDEX].crp_p; -+ BITS_TO_BYTES(dsaVerifyOpData->S.dataLenInBytes, -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_SIG_S_INDEX]. -+ crp_nbits); -+ icp_ocfDrvSwapBytes(dsaVerifyOpData->S.pData, -+ dsaVerifyOpData->S.dataLenInBytes); -+ -+ lacStatus = cpaCyDsaVerify(CPA_INSTANCE_HANDLE_SINGLE, -+ icp_ocfDrvDsaVerifyCallBack, -+ callbackTag, dsaVerifyOpData, &verifyStatus); -+ -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): DSA Verify Operation failed (%d).\n", -+ __FUNCTION__, lacStatus); -+ ICP_CACHE_FREE(drvDSAVerify_zone, dsaVerifyOpData); -+ krp->krp_status = ECANCELED; -+ } -+ -+ return lacStatus; -+} -+ -+/* Name : icp_ocfDrvDhP1Callback -+ * -+ * Description : When this function returns it signifies that the LAC -+ * component has completed the DH operation. -+ */ -+static void -+icp_ocfDrvDhP1CallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, CpaFlatBuffer * pLocalOctetStringPV) -+{ -+ struct cryptkop *krp = NULL; -+ CpaCyDhPhase1KeyGenOpData *pPhase1OpData = NULL; -+ -+ if (NULL == callbackTag) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "callbackTag data is NULL\n", __FUNCTION__); -+ return; -+ } -+ krp = (struct cryptkop *)callbackTag; -+ -+ if (NULL == pOpData) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "Operation Data is NULL\n", __FUNCTION__); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ pPhase1OpData = (CpaCyDhPhase1KeyGenOpData *) pOpData; -+ -+ if (NULL == pLocalOctetStringPV) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "pLocalOctetStringPV Data is NULL\n", __FUNCTION__); -+ memset(pPhase1OpData, 0, sizeof(CpaCyDhPhase1KeyGenOpData)); -+ ICP_CACHE_FREE(drvDH_zone, pPhase1OpData); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ -+ if (CPA_STATUS_SUCCESS == status) { -+ krp->krp_status = CRYPTO_OP_SUCCESS; -+ } else { -+ APRINTK("%s(): Diffie Hellman Phase1 Key Gen failed - " -+ "Operation Status = %d\n", __FUNCTION__, status); -+ krp->krp_status = ECANCELED; -+ } -+ -+ icp_ocfDrvSwapBytes(pLocalOctetStringPV->pData, -+ pLocalOctetStringPV->dataLenInBytes); -+ -+ icp_ocfDrvFreeFlatBuffer(pLocalOctetStringPV); -+ memset(pPhase1OpData, 0, sizeof(CpaCyDhPhase1KeyGenOpData)); -+ ICP_CACHE_FREE(drvDH_zone, pPhase1OpData); -+ -+ crypto_kdone(krp); -+ -+ return; -+} -+ -+/* Name : icp_ocfDrvModExpCallBack -+ * -+ * Description : When this function returns it signifies that the LAC -+ * component has completed the Mod Exp operation. -+ */ -+static void -+icp_ocfDrvModExpCallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpdata, CpaFlatBuffer * pResult) -+{ -+ struct cryptkop *krp = NULL; -+ CpaCyLnModExpOpData *pLnModExpOpData = NULL; -+ -+ if (NULL == callbackTag) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "callbackTag data is NULL\n", __FUNCTION__); -+ return; -+ } -+ krp = (struct cryptkop *)callbackTag; -+ -+ if (NULL == pOpdata) { -+ DPRINTK("%s(): Invalid Mod Exp input parameters - " -+ "Operation Data is NULL\n", __FUNCTION__); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ pLnModExpOpData = (CpaCyLnModExpOpData *) pOpdata; -+ -+ if (NULL == pResult) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "pResult data is NULL\n", __FUNCTION__); -+ krp->krp_status = ECANCELED; -+ memset(pLnModExpOpData, 0, sizeof(CpaCyLnModExpOpData)); -+ ICP_CACHE_FREE(drvLnModExp_zone, pLnModExpOpData); -+ crypto_kdone(krp); -+ return; -+ } -+ -+ if (CPA_STATUS_SUCCESS == status) { -+ krp->krp_status = CRYPTO_OP_SUCCESS; -+ } else { -+ APRINTK("%s(): LAC Mod Exp Operation failed - " -+ "Operation Status = %d\n", __FUNCTION__, status); -+ krp->krp_status = ECANCELED; -+ } -+ -+ icp_ocfDrvSwapBytes(pResult->pData, pResult->dataLenInBytes); -+ -+ /*switch base size value back to original */ -+ if (pLnModExpOpData->base.pData == -+ (uint8_t *) & (krp-> -+ krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX]. -+ crp_nbits)) { -+ *((uint32_t *) pLnModExpOpData->base.pData) = -+ ntohl(*((uint32_t *) pLnModExpOpData->base.pData)); -+ } -+ icp_ocfDrvFreeFlatBuffer(pResult); -+ memset(pLnModExpOpData, 0, sizeof(CpaCyLnModExpOpData)); -+ ICP_CACHE_FREE(drvLnModExp_zone, pLnModExpOpData); -+ -+ crypto_kdone(krp); -+ -+ return; -+ -+} -+ -+/* Name : icp_ocfDrvModExpCRTCallBack -+ * -+ * Description : When this function returns it signifies that the LAC -+ * component has completed the Mod Exp CRT operation. -+ */ -+static void -+icp_ocfDrvModExpCRTCallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, CpaFlatBuffer * pOutputData) -+{ -+ struct cryptkop *krp = NULL; -+ CpaCyRsaDecryptOpData *pDecryptData = NULL; -+ -+ if (NULL == callbackTag) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "callbackTag data is NULL\n", __FUNCTION__); -+ return; -+ } -+ -+ krp = (struct cryptkop *)callbackTag; -+ -+ if (NULL == pOpData) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "Operation Data is NULL\n", __FUNCTION__); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ pDecryptData = (CpaCyRsaDecryptOpData *) pOpData; -+ -+ if (NULL == pOutputData) { -+ DPRINTK("%s(): Invalid input parameter - " -+ "pOutputData is NULL\n", __FUNCTION__); -+ memset(pDecryptData->pRecipientPrivateKey, 0, -+ sizeof(CpaCyRsaPrivateKey)); -+ ICP_CACHE_FREE(drvRSAPrivateKey_zone, -+ pDecryptData->pRecipientPrivateKey); -+ memset(pDecryptData, 0, sizeof(CpaCyRsaDecryptOpData)); -+ ICP_CACHE_FREE(drvRSADecrypt_zone, pDecryptData); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ -+ if (CPA_STATUS_SUCCESS == status) { -+ krp->krp_status = CRYPTO_OP_SUCCESS; -+ } else { -+ APRINTK("%s(): LAC Mod Exp CRT operation failed - " -+ "Operation Status = %d\n", __FUNCTION__, status); -+ krp->krp_status = ECANCELED; -+ } -+ -+ icp_ocfDrvSwapBytes(pOutputData->pData, pOutputData->dataLenInBytes); -+ -+ icp_ocfDrvFreeFlatBuffer(pOutputData); -+ memset(pDecryptData->pRecipientPrivateKey, 0, -+ sizeof(CpaCyRsaPrivateKey)); -+ ICP_CACHE_FREE(drvRSAPrivateKey_zone, -+ pDecryptData->pRecipientPrivateKey); -+ memset(pDecryptData, 0, sizeof(CpaCyRsaDecryptOpData)); -+ ICP_CACHE_FREE(drvRSADecrypt_zone, pDecryptData); -+ -+ crypto_kdone(krp); -+ -+ return; -+} -+ -+/* Name : icp_ocfDrvDsaRSSignCallBack -+ * -+ * Description : When this function returns it signifies that the LAC -+ * component has completed the DSA RS sign operation. -+ */ -+static void -+icp_ocfDrvDsaRSSignCallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, -+ CpaBoolean protocolStatus, -+ CpaFlatBuffer * pR, CpaFlatBuffer * pS) -+{ -+ struct cryptkop *krp = NULL; -+ CpaCyDsaRSSignOpData *pSignData = NULL; -+ -+ if (NULL == callbackTag) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "callbackTag data is NULL\n", __FUNCTION__); -+ return; -+ } -+ -+ krp = (struct cryptkop *)callbackTag; -+ -+ if (NULL == pOpData) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "Operation Data is NULL\n", __FUNCTION__); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ pSignData = (CpaCyDsaRSSignOpData *) pOpData; -+ -+ if (NULL == pR) { -+ DPRINTK("%s(): Invalid input parameter - " -+ "pR sign is NULL\n", __FUNCTION__); -+ icp_ocfDrvFreeFlatBuffer(pS); -+ ICP_CACHE_FREE(drvDSARSSign_zone, pSignData); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ -+ if (NULL == pS) { -+ DPRINTK("%s(): Invalid input parameter - " -+ "pS sign is NULL\n", __FUNCTION__); -+ icp_ocfDrvFreeFlatBuffer(pR); -+ ICP_CACHE_FREE(drvDSARSSign_zone, pSignData); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ -+ if (CPA_STATUS_SUCCESS != status) { -+ APRINTK("%s(): LAC DSA RS Sign operation failed - " -+ "Operation Status = %d\n", __FUNCTION__, status); -+ krp->krp_status = ECANCELED; -+ } else { -+ krp->krp_status = CRYPTO_OP_SUCCESS; -+ -+ if (CPA_TRUE != protocolStatus) { -+ DPRINTK("%s(): LAC DSA RS Sign operation failed due " -+ "to protocol error\n", __FUNCTION__); -+ krp->krp_status = EIO; -+ } -+ } -+ -+ /* Swap bytes only when the callback status is successful and -+ protocolStatus is set to true */ -+ if (CPA_STATUS_SUCCESS == status && CPA_TRUE == protocolStatus) { -+ icp_ocfDrvSwapBytes(pR->pData, pR->dataLenInBytes); -+ icp_ocfDrvSwapBytes(pS->pData, pS->dataLenInBytes); -+ } -+ -+ icp_ocfDrvFreeFlatBuffer(pR); -+ icp_ocfDrvFreeFlatBuffer(pS); -+ memset(pSignData->K.pData, 0, pSignData->K.dataLenInBytes); -+ ICP_CACHE_FREE(drvDSARSSignKValue_zone, pSignData->K.pData); -+ memset(pSignData, 0, sizeof(CpaCyDsaRSSignOpData)); -+ ICP_CACHE_FREE(drvDSARSSign_zone, pSignData); -+ crypto_kdone(krp); -+ -+ return; -+} -+ -+/* Name : icp_ocfDrvDsaVerifyCallback -+ * -+ * Description : When this function returns it signifies that the LAC -+ * component has completed the DSA Verify operation. -+ */ -+static void -+icp_ocfDrvDsaVerifyCallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, CpaBoolean verifyStatus) -+{ -+ -+ struct cryptkop *krp = NULL; -+ CpaCyDsaVerifyOpData *pVerData = NULL; -+ -+ if (NULL == callbackTag) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "callbackTag data is NULL\n", __FUNCTION__); -+ return; -+ } -+ -+ krp = (struct cryptkop *)callbackTag; -+ -+ if (NULL == pOpData) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "Operation Data is NULL\n", __FUNCTION__); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ pVerData = (CpaCyDsaVerifyOpData *) pOpData; -+ -+ if (CPA_STATUS_SUCCESS != status) { -+ APRINTK("%s(): LAC DSA Verify operation failed - " -+ "Operation Status = %d\n", __FUNCTION__, status); -+ krp->krp_status = ECANCELED; -+ } else { -+ krp->krp_status = CRYPTO_OP_SUCCESS; -+ -+ if (CPA_TRUE != verifyStatus) { -+ DPRINTK("%s(): DSA signature invalid\n", __FUNCTION__); -+ krp->krp_status = EIO; -+ } -+ } -+ -+ /* Swap bytes only when the callback status is successful and -+ verifyStatus is set to true */ -+ /*Just swapping back the key values for now. Possibly all -+ swapped buffers need to be reverted */ -+ if (CPA_STATUS_SUCCESS == status && CPA_TRUE == verifyStatus) { -+ icp_ocfDrvSwapBytes(pVerData->R.pData, -+ pVerData->R.dataLenInBytes); -+ icp_ocfDrvSwapBytes(pVerData->S.pData, -+ pVerData->S.dataLenInBytes); -+ } -+ -+ memset(pVerData, 0, sizeof(CpaCyDsaVerifyOpData)); -+ ICP_CACHE_FREE(drvDSAVerify_zone, pVerData); -+ crypto_kdone(krp); -+ -+ return; -+} -diff -Nur linux-2.6.39.orig/crypto/ocf/ep80579/icp_common.c linux-2.6.39/crypto/ocf/ep80579/icp_common.c ---- linux-2.6.39.orig/crypto/ocf/ep80579/icp_common.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/ep80579/icp_common.c 2011-08-01 14:38:18.000000000 +0200 -@@ -0,0 +1,773 @@ -+/************************************************************************* -+ * -+ * This file is provided under a dual BSD/GPLv2 license. When using or -+ * redistributing this file, you may do so under either license. -+ * -+ * GPL LICENSE SUMMARY -+ * -+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of version 2 of the GNU General Public License as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. -+ * The full GNU General Public License is included in this distribution -+ * in the file called LICENSE.GPL. -+ * -+ * Contact Information: -+ * Intel Corporation -+ * -+ * BSD LICENSE -+ * -+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * * Neither the name of Intel Corporation nor the names of its -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * -+ * version: Security.L.1.0.2-229 -+ * -+ ***************************************************************************/ -+ -+/* -+ * An OCF module that uses Intel® QuickAssist Integrated Accelerator to do the -+ * crypto. -+ * -+ * This driver requires the ICP Access Library that is available from Intel in -+ * order to operate. -+ */ -+ -+#include "icp_ocf.h" -+ -+#define ICP_OCF_COMP_NAME "ICP_OCF" -+#define ICP_OCF_VER_MAIN (2) -+#define ICP_OCF_VER_MJR (1) -+#define ICP_OCF_VER_MNR (0) -+ -+#define MAX_DEREG_RETRIES (100) -+#define DEFAULT_DEREG_RETRIES (10) -+#define DEFAULT_DEREG_DELAY_IN_JIFFIES (10) -+ -+/* This defines the maximum number of sessions possible between OCF -+ and the OCF EP80579 Driver. If set to zero, there is no limit. */ -+#define DEFAULT_OCF_TO_DRV_MAX_SESSION_COUNT (0) -+#define NUM_SUPPORTED_CAPABILITIES (21) -+ -+/*Slab zone names*/ -+#define ICP_SESSION_DATA_NAME "icp_ocf.SesDat" -+#define ICP_OP_DATA_NAME "icp_ocf.OpDat" -+#define ICP_DH_NAME "icp_ocf.DH" -+#define ICP_MODEXP_NAME "icp_ocf.ModExp" -+#define ICP_RSA_DECRYPT_NAME "icp_ocf.RSAdec" -+#define ICP_RSA_PKEY_NAME "icp_ocf.RSApk" -+#define ICP_DSA_SIGN_NAME "icp_ocf.DSAsg" -+#define ICP_DSA_VER_NAME "icp_ocf.DSAver" -+#define ICP_RAND_VAL_NAME "icp_ocf.DSArnd" -+#define ICP_FLAT_BUFF_NAME "icp_ocf.FB" -+ -+/*Slabs zones*/ -+icp_kmem_cache drvSessionData_zone = NULL; -+icp_kmem_cache drvOpData_zone = NULL; -+icp_kmem_cache drvDH_zone = NULL; -+icp_kmem_cache drvLnModExp_zone = NULL; -+icp_kmem_cache drvRSADecrypt_zone = NULL; -+icp_kmem_cache drvRSAPrivateKey_zone = NULL; -+icp_kmem_cache drvDSARSSign_zone = NULL; -+icp_kmem_cache drvDSARSSignKValue_zone = NULL; -+icp_kmem_cache drvDSAVerify_zone = NULL; -+ -+/*Slab zones for flatbuffers and bufferlist*/ -+icp_kmem_cache drvFlatBuffer_zone = NULL; -+ -+static inline int icp_cache_null_check(void) -+{ -+ return (drvSessionData_zone && drvOpData_zone -+ && drvDH_zone && drvLnModExp_zone && drvRSADecrypt_zone -+ && drvRSAPrivateKey_zone && drvDSARSSign_zone -+ && drvDSARSSign_zone && drvDSARSSignKValue_zone -+ && drvDSAVerify_zone && drvFlatBuffer_zone); -+} -+ -+/*Function to free all allocated slab caches before exiting the module*/ -+static void icp_ocfDrvFreeCaches(void); -+ -+int32_t icp_ocfDrvDriverId = INVALID_DRIVER_ID; -+ -+/* Module parameter - gives the number of times LAC deregistration shall be -+ re-tried */ -+int num_dereg_retries = DEFAULT_DEREG_RETRIES; -+ -+/* Module parameter - gives the delay time in jiffies before a LAC session -+ shall be attempted to be deregistered again */ -+int dereg_retry_delay_in_jiffies = DEFAULT_DEREG_DELAY_IN_JIFFIES; -+ -+/* Module parameter - gives the maximum number of sessions possible between -+ OCF and the OCF EP80579 Driver. If set to zero, there is no limit.*/ -+int max_sessions = DEFAULT_OCF_TO_DRV_MAX_SESSION_COUNT; -+ -+/* This is set when the module is removed from the system, no further -+ processing can take place if this is set */ -+icp_atomic_t icp_ocfDrvIsExiting = ICP_ATOMIC_INIT(0); -+ -+/* This is used to show how many lac sessions were not deregistered*/ -+icp_atomic_t lac_session_failed_dereg_count = ICP_ATOMIC_INIT(0); -+ -+/* This is used to track the number of registered sessions between OCF and -+ * and the OCF EP80579 driver, when max_session is set to value other than -+ * zero. This ensures that the max_session set for the OCF and the driver -+ * is equal to the LAC registered sessions */ -+icp_atomic_t num_ocf_to_drv_registered_sessions = ICP_ATOMIC_INIT(0); -+ -+/* Head of linked list used to store session data */ -+icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead; -+icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead_FreeMemList; -+ -+icp_spinlock_t icp_ocfDrvSymSessInfoListSpinlock; -+ -+/*Below pointer is only used in linux, FreeBSD uses the name to -+create its own variable name*/ -+icp_workqueue *icp_ocfDrvFreeLacSessionWorkQ = NULL; -+ICP_WORKQUEUE_DEFINE_THREAD(icp_ocfDrvFreeLacSessionWorkQ); -+ -+struct icp_drvBuffListInfo defBuffListInfo; -+ -+/* Name : icp_ocfDrvInit -+ * -+ * Description : This function will register all the symmetric and asymmetric -+ * functionality that will be accelerated by the hardware. It will also -+ * get a unique driver ID from the OCF and initialise all slab caches -+ */ -+ICP_MODULE_INIT_FUNC(icp_ocfDrvInit) -+{ -+ int ocfStatus = 0; -+ -+ IPRINTK("=== %s ver %d.%d.%d ===\n", ICP_OCF_COMP_NAME, -+ ICP_OCF_VER_MAIN, ICP_OCF_VER_MJR, ICP_OCF_VER_MNR); -+ -+ if (MAX_DEREG_RETRIES < num_dereg_retries) { -+ EPRINTK("Session deregistration retry count set to greater " -+ "than %d", MAX_DEREG_RETRIES); -+ icp_module_return_code(EINVAL); -+ } -+ -+ /* Initialize and Start the Cryptographic component */ -+ if (CPA_STATUS_SUCCESS != -+ cpaCyStartInstance(CPA_INSTANCE_HANDLE_SINGLE)) { -+ EPRINTK("Failed to initialize and start the instance " -+ "of the Cryptographic component.\n"); -+ return icp_module_return_code(EINVAL); -+ } -+ -+ icp_spin_lock_init(&icp_ocfDrvSymSessInfoListSpinlock); -+ -+ /* Set the default size of BufferList to allocate */ -+ memset(&defBuffListInfo, 0, sizeof(struct icp_drvBuffListInfo)); -+ if (ICP_OCF_DRV_STATUS_SUCCESS != -+ icp_ocfDrvBufferListMemInfo(ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS, -+ &defBuffListInfo)) { -+ EPRINTK("Failed to get bufferlist memory info.\n"); -+ return icp_module_return_code(ENOMEM); -+ } -+ -+ /*Register OCF EP80579 Driver with OCF */ -+ icp_ocfDrvDriverId = ICP_CRYPTO_GET_DRIVERID(); -+ -+ if (icp_ocfDrvDriverId < 0) { -+ EPRINTK("%s : ICP driver failed to register with OCF!\n", -+ __FUNCTION__); -+ return icp_module_return_code(ENODEV); -+ } -+ -+ /*Create all the slab caches used by the OCF EP80579 Driver */ -+ drvSessionData_zone = -+ ICP_CACHE_CREATE(ICP_SESSION_DATA_NAME, struct icp_drvSessionData); -+ -+ /* -+ * Allocation of the OpData includes the allocation space for meta data. -+ * The memory after the opData structure is reserved for this meta data. -+ */ -+ drvOpData_zone = -+ icp_kmem_cache_create(ICP_OP_DATA_NAME, -+ sizeof(struct icp_drvOpData) + -+ defBuffListInfo.metaSize, -+ ICP_KERNEL_CACHE_ALIGN, -+ ICP_KERNEL_CACHE_NOINIT); -+ -+ drvDH_zone = ICP_CACHE_CREATE(ICP_DH_NAME, CpaCyDhPhase1KeyGenOpData); -+ -+ drvLnModExp_zone = -+ ICP_CACHE_CREATE(ICP_MODEXP_NAME, CpaCyLnModExpOpData); -+ -+ drvRSADecrypt_zone = -+ ICP_CACHE_CREATE(ICP_RSA_DECRYPT_NAME, CpaCyRsaDecryptOpData); -+ -+ drvRSAPrivateKey_zone = -+ ICP_CACHE_CREATE(ICP_RSA_PKEY_NAME, CpaCyRsaPrivateKey); -+ -+ drvDSARSSign_zone = -+ ICP_CACHE_CREATE(ICP_DSA_SIGN_NAME, CpaCyDsaRSSignOpData); -+ -+ /*too awkward to use a macro here */ -+ drvDSARSSignKValue_zone = -+ ICP_CACHE_CREATE(ICP_RAND_VAL_NAME, -+ DSA_RS_SIGN_PRIMEQ_SIZE_IN_BYTES); -+ -+ drvDSAVerify_zone = -+ ICP_CACHE_CREATE(ICP_DSA_VER_NAME, CpaCyDsaVerifyOpData); -+ -+ drvFlatBuffer_zone = -+ ICP_CACHE_CREATE(ICP_FLAT_BUFF_NAME, CpaFlatBuffer); -+ -+ if (0 == icp_cache_null_check()) { -+ icp_ocfDrvFreeCaches(); -+ EPRINTK("%s() line %d: Not enough memory!\n", -+ __FUNCTION__, __LINE__); -+ return ENOMEM; -+ } -+ -+ /* Register the ICP symmetric crypto support. */ -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_NULL_CBC, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_DES_CBC, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_3DES_CBC, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_AES_CBC, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_ARC4, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_MD5, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_MD5_HMAC, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA1, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA1_HMAC, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_256, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_256_HMAC, -+ ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_384, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_384_HMAC, -+ ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_512, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_512_HMAC, -+ ocfStatus); -+ -+ /* Register the ICP asymmetric algorithm support */ -+ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_DH_COMPUTE_KEY, -+ ocfStatus); -+ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_MOD_EXP, ocfStatus); -+ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_MOD_EXP_CRT, ocfStatus); -+ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_DSA_SIGN, ocfStatus); -+ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_DSA_VERIFY, ocfStatus); -+ -+ /* Register the ICP random number generator support */ -+ ICP_REG_RAND_WITH_OCF(icp_ocfDrvDriverId, -+ icp_ocfDrvReadRandom, NULL, ocfStatus); -+ -+ if (OCF_ZERO_FUNCTIONALITY_REGISTERED == ocfStatus) { -+ DPRINTK("%s: Failed to register any device capabilities\n", -+ __FUNCTION__); -+ icp_ocfDrvFreeCaches(); -+ icp_ocfDrvDriverId = INVALID_DRIVER_ID; -+ return icp_module_return_code(ECANCELED); -+ } -+ -+ DPRINTK("%s: Registered %d of %d device capabilities\n", -+ __FUNCTION__, ocfStatus, NUM_SUPPORTED_CAPABILITIES); -+ -+ /*Session data linked list used during module exit */ -+ ICP_INIT_LIST_HEAD(&icp_ocfDrvGlobalSymListHead); -+ ICP_INIT_LIST_HEAD(&icp_ocfDrvGlobalSymListHead_FreeMemList); -+ -+ ICP_WORKQUEUE_CREATE(icp_ocfDrvFreeLacSessionWorkQ, "icpwq"); -+ if (ICP_WORKQUEUE_NULL_CHECK(icp_ocfDrvFreeLacSessionWorkQ)) { -+ EPRINTK("%s: Failed to create single " -+ "thread workqueue\n", __FUNCTION__); -+ icp_ocfDrvFreeCaches(); -+ icp_ocfDrvDriverId = INVALID_DRIVER_ID; -+ return icp_module_return_code(ENOMEM); -+ } -+ -+ return icp_module_return_code(0); -+} -+ -+/* Name : icp_ocfDrvExit -+ * -+ * Description : This function will deregister all the symmetric sessions -+ * registered with the LAC component. It will also deregister all symmetric -+ * and asymmetric functionality that can be accelerated by the hardware via OCF -+ * and random number generation if it is enabled. -+ */ -+ICP_MODULE_EXIT_FUNC(icp_ocfDrvExit) -+{ -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ struct icp_drvSessionData *sessionData = NULL; -+ struct icp_drvSessionData *tempSessionData = NULL; -+ int i, remaining_delay_time_in_jiffies = 0; -+ -+ /* For FreeBSD the invariant macro below makes function to return */ -+ /* with EBUSY value in the case of any session which has been regi- */ -+ /* stered with LAC not being deregistered. */ -+ /* The Linux implementation is empty since it is purely to compensate */ -+ /* for a limitation of the FreeBSD 7.1 Opencrypto framework. */ -+ -+ ICP_MODULE_EXIT_INV(); -+ -+ /* There is a possibility of a process or new session command being */ -+ /* sent before this variable is incremented. The aim of this variable */ -+ /* is to stop a loop of calls creating a deadlock situation which */ -+ /* would prevent the driver from exiting. */ -+ icp_atomic_set(&icp_ocfDrvIsExiting, 1); -+ -+ /*Existing sessions will be routed to another driver after these calls */ -+ crypto_unregister_all(icp_ocfDrvDriverId); -+ crypto_runregister_all(icp_ocfDrvDriverId); -+ -+ if (ICP_WORKQUEUE_NULL_CHECK(icp_ocfDrvFreeLacSessionWorkQ)) { -+ DPRINTK("%s: workqueue already " -+ "destroyed, therefore module exit " -+ " function already called. Exiting.\n", __FUNCTION__); -+ return ICP_MODULE_EXIT_FUNC_RETURN_VAL; -+ } -+ /*If any sessions are waiting to be deregistered, do that. This also -+ flushes the work queue */ -+ ICP_WORKQUEUE_DESTROY(icp_ocfDrvFreeLacSessionWorkQ); -+ -+ /*ENTER CRITICAL SECTION */ -+ icp_spin_lockbh_lock(&icp_ocfDrvSymSessInfoListSpinlock); -+ -+ ICP_LIST_FOR_EACH_ENTRY_SAFE(tempSessionData, sessionData, -+ &icp_ocfDrvGlobalSymListHead, listNode) { -+ for (i = 0; i < num_dereg_retries; i++) { -+ /*No harm if bad input - LAC will handle error cases */ -+ if (ICP_SESSION_RUNNING == tempSessionData->inUse) { -+ lacStatus = -+ cpaCySymRemoveSession -+ (CPA_INSTANCE_HANDLE_SINGLE, -+ tempSessionData->sessHandle); -+ if (CPA_STATUS_SUCCESS == lacStatus) { -+ /* Succesfully deregistered */ -+ break; -+ } else if (CPA_STATUS_RETRY != lacStatus) { -+ icp_atomic_inc -+ (&lac_session_failed_dereg_count); -+ break; -+ } -+ -+ /*schedule_timout returns the time left for completion if -+ * this task is set to TASK_INTERRUPTIBLE */ -+ remaining_delay_time_in_jiffies = -+ dereg_retry_delay_in_jiffies; -+ while (0 > remaining_delay_time_in_jiffies) { -+ remaining_delay_time_in_jiffies = -+ icp_schedule_timeout -+ (&icp_ocfDrvSymSessInfoListSpinlock, -+ remaining_delay_time_in_jiffies); -+ } -+ -+ DPRINTK -+ ("%s(): Retry %d to deregistrate the session\n", -+ __FUNCTION__, i); -+ } -+ } -+ -+ /*remove from current list */ -+ ICP_LIST_DEL(tempSessionData, listNode); -+ /*add to free mem linked list */ -+ ICP_LIST_ADD(tempSessionData, -+ &icp_ocfDrvGlobalSymListHead_FreeMemList, -+ listNode); -+ -+ } -+ -+ /*EXIT CRITICAL SECTION */ -+ icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock); -+ -+ /*set back to initial values */ -+ sessionData = NULL; -+ /*still have a reference in our list! */ -+ tempSessionData = NULL; -+ /*free memory */ -+ -+ ICP_LIST_FOR_EACH_ENTRY_SAFE(tempSessionData, sessionData, -+ &icp_ocfDrvGlobalSymListHead_FreeMemList, -+ listNode) { -+ -+ ICP_LIST_DEL(tempSessionData, listNode); -+ /* Free allocated CpaCySymSessionCtx */ -+ if (NULL != tempSessionData->sessHandle) { -+ icp_kfree(tempSessionData->sessHandle); -+ } -+ memset(tempSessionData, 0, sizeof(struct icp_drvSessionData)); -+ ICP_CACHE_FREE(drvSessionData_zone, tempSessionData); -+ } -+ -+ if (0 != icp_atomic_read(&lac_session_failed_dereg_count)) { -+ DPRINTK("%s(): %d LAC sessions were not deregistered " -+ "correctly. This is not a clean exit! \n", -+ __FUNCTION__, -+ icp_atomic_read(&lac_session_failed_dereg_count)); -+ } -+ -+ icp_ocfDrvFreeCaches(); -+ icp_ocfDrvDriverId = INVALID_DRIVER_ID; -+ -+ icp_spin_lock_destroy(&icp_ocfDrvSymSessInfoListSpinlock); -+ -+ /* Shutdown the Cryptographic component */ -+ lacStatus = cpaCyStopInstance(CPA_INSTANCE_HANDLE_SINGLE); -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ DPRINTK("%s(): Failed to stop instance of the " -+ "Cryptographic component.(status == %d)\n", -+ __FUNCTION__, lacStatus); -+ } -+ -+ return ICP_MODULE_EXIT_FUNC_RETURN_VAL; -+} -+ -+/* Name : icp_ocfDrvFreeCaches -+ * -+ * Description : This function deregisters all slab caches -+ */ -+static void icp_ocfDrvFreeCaches(void) -+{ -+ icp_atomic_set(&icp_ocfDrvIsExiting, 1); -+ -+ /*Sym Zones */ -+ ICP_CACHE_DESTROY(drvSessionData_zone); -+ ICP_CACHE_DESTROY(drvOpData_zone); -+ -+ /*Asym zones */ -+ ICP_CACHE_DESTROY(drvDH_zone); -+ ICP_CACHE_DESTROY(drvLnModExp_zone); -+ ICP_CACHE_DESTROY(drvRSADecrypt_zone); -+ ICP_CACHE_DESTROY(drvRSAPrivateKey_zone); -+ ICP_CACHE_DESTROY(drvDSARSSignKValue_zone); -+ ICP_CACHE_DESTROY(drvDSARSSign_zone); -+ ICP_CACHE_DESTROY(drvDSAVerify_zone); -+ -+ /*FlatBuffer and BufferList Zones */ -+ ICP_CACHE_DESTROY(drvFlatBuffer_zone); -+ -+} -+ -+/* Name : icp_ocfDrvDeregRetry -+ * -+ * Description : This function will try to farm the session deregistration -+ * off to a work queue. If it fails, nothing more can be done and it -+ * returns an error -+ */ -+int icp_ocfDrvDeregRetry(CpaCySymSessionCtx sessionToDeregister) -+{ -+ struct icp_ocfDrvFreeLacSession *workstore = NULL; -+ -+ DPRINTK("%s(): Retry - Deregistering session (%p)\n", -+ __FUNCTION__, sessionToDeregister); -+ -+ /*make sure the session is not available to be allocated during this -+ process */ -+ icp_atomic_inc(&lac_session_failed_dereg_count); -+ -+ /*Farm off to work queue */ -+ workstore = -+ icp_kmalloc(sizeof(struct icp_ocfDrvFreeLacSession), ICP_M_NOWAIT); -+ if (NULL == workstore) { -+ DPRINTK("%s(): unable to free session - no memory available " -+ "for work queue\n", __FUNCTION__); -+ return ENOMEM; -+ } -+ -+ workstore->sessionToDeregister = sessionToDeregister; -+ -+ icp_init_work(&(workstore->work), -+ icp_ocfDrvDeferedFreeLacSessionTaskFn, workstore); -+ -+ ICP_WORKQUEUE_ENQUEUE(icp_ocfDrvFreeLacSessionWorkQ, -+ &(workstore->work)); -+ -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+ -+} -+ -+/* Name : icp_ocfDrvDeferedFreeLacSessionProcess -+ * -+ * Description : This function will retry (module input parameter) -+ * 'num_dereg_retries' times to deregister any symmetric session that recieves a -+ * CPA_STATUS_RETRY message from the LAC component. This function is run in -+ * Thread context because it is called from a worker thread -+ */ -+void icp_ocfDrvDeferedFreeLacSessionProcess(void *arg) -+{ -+ struct icp_ocfDrvFreeLacSession *workstore = NULL; -+ CpaCySymSessionCtx sessionToDeregister = NULL; -+ int i = 0; -+ int remaining_delay_time_in_jiffies = 0; -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ -+ workstore = (struct icp_ocfDrvFreeLacSession *)arg; -+ if (NULL == workstore) { -+ DPRINTK("%s() function called with null parameter \n", -+ __FUNCTION__); -+ return; -+ } -+ -+ sessionToDeregister = workstore->sessionToDeregister; -+ icp_kfree(workstore); -+ -+ /*if exiting, give deregistration one more blast only */ -+ if (icp_atomic_read(&icp_ocfDrvIsExiting) == CPA_TRUE) { -+ lacStatus = cpaCySymRemoveSession(CPA_INSTANCE_HANDLE_SINGLE, -+ sessionToDeregister); -+ -+ if (lacStatus != CPA_STATUS_SUCCESS) { -+ DPRINTK("%s() Failed to Dereg LAC session %p " -+ "during module exit\n", __FUNCTION__, -+ sessionToDeregister); -+ return; -+ } -+ -+ icp_atomic_dec(&lac_session_failed_dereg_count); -+ return; -+ } -+ -+ for (i = 0; i <= num_dereg_retries; i++) { -+ lacStatus = cpaCySymRemoveSession(CPA_INSTANCE_HANDLE_SINGLE, -+ sessionToDeregister); -+ -+ if (lacStatus == CPA_STATUS_SUCCESS) { -+ icp_atomic_dec(&lac_session_failed_dereg_count); -+ return; -+ } -+ if (lacStatus != CPA_STATUS_RETRY) { -+ DPRINTK("%s() Failed to deregister session - lacStatus " -+ " = %d", __FUNCTION__, lacStatus); -+ break; -+ } -+ -+ /*schedule_timout returns the time left for completion if this -+ task is set to TASK_INTERRUPTIBLE */ -+ remaining_delay_time_in_jiffies = dereg_retry_delay_in_jiffies; -+ while (0 < remaining_delay_time_in_jiffies) { -+ remaining_delay_time_in_jiffies = -+ icp_schedule_timeout(NULL, -+ remaining_delay_time_in_jiffies); -+ } -+ -+ } -+ -+ DPRINTK("%s(): Unable to deregister session\n", __FUNCTION__); -+ DPRINTK("%s(): Number of unavailable LAC sessions = %d\n", __FUNCTION__, -+ icp_atomic_read(&lac_session_failed_dereg_count)); -+} -+ -+/* Name : icp_ocfDrvPtrAndLenToFlatBuffer -+ * -+ * Description : This function converts a "pointer and length" buffer -+ * structure to Fredericksburg Flat Buffer (CpaFlatBuffer) format. -+ * -+ * This function assumes that the data passed in are valid. -+ */ -+inline void -+icp_ocfDrvPtrAndLenToFlatBuffer(void *pData, uint32_t len, -+ CpaFlatBuffer * pFlatBuffer) -+{ -+ pFlatBuffer->pData = pData; -+ pFlatBuffer->dataLenInBytes = len; -+} -+ -+/* Name : icp_ocfDrvPtrAndLenToBufferList -+ * -+ * Description : This function converts a "pointer and length" buffer -+ * structure to Fredericksburg Scatter/Gather Buffer (CpaBufferList) format. -+ * -+ * This function assumes that the data passed in are valid. -+ */ -+inline void -+icp_ocfDrvPtrAndLenToBufferList(void *pDataIn, uint32_t length, -+ CpaBufferList * pBufferList) -+{ -+ pBufferList->numBuffers = 1; -+ pBufferList->pBuffers->pData = pDataIn; -+ pBufferList->pBuffers->dataLenInBytes = length; -+} -+ -+/* Name : icp_ocfDrvBufferListToPtrAndLen -+ * -+ * Description : This function converts Fredericksburg Scatter/Gather Buffer -+ * (CpaBufferList) format to a "pointer and length" buffer structure. -+ * -+ * This function assumes that the data passed in are valid. -+ */ -+inline void -+icp_ocfDrvBufferListToPtrAndLen(CpaBufferList * pBufferList, -+ void **ppDataOut, uint32_t * pLength) -+{ -+ *ppDataOut = pBufferList->pBuffers->pData; -+ *pLength = pBufferList->pBuffers->dataLenInBytes; -+} -+ -+/* Name : icp_ocfDrvBufferListMemInfo -+ * -+ * Description : This function will set the number of flat buffers in -+ * bufferlist, the size of memory to allocate for the pPrivateMetaData -+ * member of the CpaBufferList. -+ */ -+int -+icp_ocfDrvBufferListMemInfo(uint16_t numBuffers, -+ struct icp_drvBuffListInfo *buffListInfo) -+{ -+ buffListInfo->numBuffers = numBuffers; -+ -+ if (CPA_STATUS_SUCCESS != -+ cpaCyBufferListGetMetaSize(CPA_INSTANCE_HANDLE_SINGLE, -+ buffListInfo->numBuffers, -+ &(buffListInfo->metaSize))) { -+ EPRINTK("%s() Failed to get buffer list meta size.\n", -+ __FUNCTION__); -+ return ICP_OCF_DRV_STATUS_FAIL; -+ } -+ -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+} -+ -+/* Name : icp_ocfDrvFreeFlatBuffer -+ * -+ * Description : This function will deallocate flat buffer. -+ */ -+inline void icp_ocfDrvFreeFlatBuffer(CpaFlatBuffer * pFlatBuffer) -+{ -+ if (pFlatBuffer != NULL) { -+ memset(pFlatBuffer, 0, sizeof(CpaFlatBuffer)); -+ ICP_CACHE_FREE(drvFlatBuffer_zone, pFlatBuffer); -+ } -+} -+ -+/* Name : icp_ocfDrvAllocMetaData -+ * -+ * Description : This function will allocate memory for the -+ * pPrivateMetaData member of CpaBufferList. -+ */ -+inline int -+icp_ocfDrvAllocMetaData(CpaBufferList * pBufferList, -+ struct icp_drvOpData *pOpData) -+{ -+ Cpa32U metaSize = 0; -+ -+ if (pBufferList->numBuffers <= ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) { -+ uint8_t *pOpDataStartAddr = (uint8_t *) pOpData; -+ -+ if (0 == defBuffListInfo.metaSize) { -+ pBufferList->pPrivateMetaData = NULL; -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+ } -+ /* -+ * The meta data allocation has been included as part of the -+ * op data. It has been pre-allocated in memory just after the -+ * icp_drvOpData structure. -+ */ -+ pBufferList->pPrivateMetaData = (void *)(pOpDataStartAddr + -+ sizeof(struct -+ icp_drvOpData)); -+ } else { -+ if (CPA_STATUS_SUCCESS != -+ cpaCyBufferListGetMetaSize(CPA_INSTANCE_HANDLE_SINGLE, -+ pBufferList->numBuffers, -+ &metaSize)) { -+ EPRINTK("%s() Failed to get buffer list meta size.\n", -+ __FUNCTION__); -+ return ICP_OCF_DRV_STATUS_FAIL; -+ } -+ -+ if (0 == metaSize) { -+ pBufferList->pPrivateMetaData = NULL; -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+ } -+ -+ pBufferList->pPrivateMetaData = -+ icp_kmalloc(metaSize, ICP_M_NOWAIT); -+ } -+ if (NULL == pBufferList->pPrivateMetaData) { -+ EPRINTK("%s() Failed to allocate pPrivateMetaData.\n", -+ __FUNCTION__); -+ return ICP_OCF_DRV_STATUS_FAIL; -+ } -+ -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+} -+ -+/* Name : icp_ocfDrvFreeMetaData -+ * -+ * Description : This function will deallocate pPrivateMetaData memory. -+ */ -+inline void icp_ocfDrvFreeMetaData(CpaBufferList * pBufferList) -+{ -+ if (NULL == pBufferList->pPrivateMetaData) { -+ return; -+ } -+ -+ /* -+ * Only free the meta data if the BufferList has more than -+ * ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS number of buffers. -+ * Otherwise, the meta data shall be freed when the icp_drvOpData is -+ * freed. -+ */ -+ if (ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS < pBufferList->numBuffers) { -+ icp_kfree(pBufferList->pPrivateMetaData); -+ } -+} -+ -+/* Module declaration, init and exit functions */ -+ICP_DECLARE_MODULE(icp_ocf, icp_ocfDrvInit, icp_ocfDrvExit); -+ICP_MODULE_DESCRIPTION("OCF Driver for Intel Quick Assist crypto acceleration"); -+ICP_MODULE_VERSION(icp_ocf, ICP_OCF_VER_MJR); -+ICP_MODULE_LICENSE("Dual BSD/GPL"); -+ICP_MODULE_AUTHOR("Intel"); -+ -+/* Module parameters */ -+ICP_MODULE_PARAM_INT(icp_ocf, num_dereg_retries, -+ "Number of times to retry LAC Sym Session Deregistration. " -+ "Default 10, Max 100"); -+ICP_MODULE_PARAM_INT(icp_ocf, dereg_retry_delay_in_jiffies, "Delay in jiffies " -+ "(added to a schedule() function call) before a LAC Sym " -+ "Session Dereg is retried. Default 10"); -+ICP_MODULE_PARAM_INT(icp_ocf, max_sessions, -+ "This sets the maximum number of sessions " -+ "between OCF and this driver. If this value is set to zero," -+ "max session count checking is disabled. Default is zero(0)"); -+ -+/* Module dependencies */ -+#define MODULE_MIN_VER 1 -+#define CRYPTO_MAX_VER 3 -+#define LAC_MAX_VER 2 -+ -+ICP_MODULE_DEPEND(icp_ocf, crypto, MODULE_MIN_VER, MODULE_MIN_VER, -+ CRYPTO_MAX_VER); -+ICP_MODULE_DEPEND(icp_ocf, cryptodev, MODULE_MIN_VER, MODULE_MIN_VER, -+ CRYPTO_MAX_VER); -+ICP_MODULE_DEPEND(icp_ocf, icp_crypto, MODULE_MIN_VER, MODULE_MIN_VER, -+ LAC_MAX_VER); -diff -Nur linux-2.6.39.orig/crypto/ocf/ep80579/icp_ocf.h linux-2.6.39/crypto/ocf/ep80579/icp_ocf.h ---- linux-2.6.39.orig/crypto/ocf/ep80579/icp_ocf.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/ep80579/icp_ocf.h 2011-08-01 14:38:18.000000000 +0200 -@@ -0,0 +1,376 @@ -+/*************************************************************************** -+ * -+ * This file is provided under a dual BSD/GPLv2 license. When using or -+ * redistributing this file, you may do so under either license. -+ * -+ * GPL LICENSE SUMMARY -+ * -+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of version 2 of the GNU General Public License as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. -+ * The full GNU General Public License is included in this distribution -+ * in the file called LICENSE.GPL. -+ * -+ * Contact Information: -+ * Intel Corporation -+ * -+ * BSD LICENSE -+ * -+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * * Neither the name of Intel Corporation nor the names of its -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * -+ * version: Security.L.1.0.2-229 -+ * -+ ***************************************************************************/ -+ -+/* -+ * OCF driver header file for the Intel ICP processor. -+ */ -+ -+#ifndef ICP_OCF_H_ -+#define ICP_OCF_H_ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "icp_os.h" -+ -+#define NUM_BITS_IN_BYTE (8) -+#define NUM_BITS_IN_BYTE_MINUS_ONE (NUM_BITS_IN_BYTE -1) -+#define INVALID_DRIVER_ID (-1) -+#define RETURN_RAND_NUM_GEN_FAILED (-1) -+ -+/*This is the max block cipher initialisation vector*/ -+#define MAX_IV_LEN_IN_BYTES (20) -+/*This is used to check whether the OCF to this driver session limit has -+ been disabled*/ -+#define NO_OCF_TO_DRV_MAX_SESSIONS (0) -+ -+/*OCF values mapped here*/ -+#define ICP_SHA1_DIGEST_SIZE_IN_BYTES (SHA1_HASH_LEN) -+#define ICP_SHA256_DIGEST_SIZE_IN_BYTES (SHA2_256_HASH_LEN) -+#define ICP_SHA384_DIGEST_SIZE_IN_BYTES (SHA2_384_HASH_LEN) -+#define ICP_SHA512_DIGEST_SIZE_IN_BYTES (SHA2_512_HASH_LEN) -+#define ICP_MD5_DIGEST_SIZE_IN_BYTES (MD5_HASH_LEN) -+#define ARC4_COUNTER_LEN (ARC4_BLOCK_LEN) -+ -+#define OCF_REGISTRATION_STATUS_SUCCESS (0) -+#define OCF_ZERO_FUNCTIONALITY_REGISTERED (0) -+#define ICP_OCF_DRV_NO_CRYPTO_PROCESS_ERROR (0) -+#define ICP_OCF_DRV_STATUS_SUCCESS (0) -+#define ICP_OCF_DRV_STATUS_FAIL (1) -+ -+/*Turn on/off debug options*/ -+#define ICP_OCF_PRINT_DEBUG_MESSAGES (0) -+#define ICP_OCF_PRINT_KERN_ALERT (1) -+#define ICP_OCF_PRINT_KERN_ERRS (1) -+ -+#if ICP_OCF_PRINT_DEBUG_MESSAGES == 1 -+#define DPRINTK(args...) \ -+{ \ -+ ICP_IPRINTK(args); \ -+} -+ -+#else //ICP_OCF_PRINT_DEBUG_MESSAGES == 1 -+ -+#define DPRINTK(args...) -+ -+#endif //ICP_OCF_PRINT_DEBUG_MESSAGES == 1 -+ -+#if ICP_OCF_PRINT_KERN_ALERT == 1 -+#define APRINTK(args...) \ -+{ \ -+ ICP_APRINTK(args); \ -+} -+ -+#else //ICP_OCF_PRINT_KERN_ALERT == 1 -+ -+#define APRINTK(args...) -+ -+#endif //ICP_OCF_PRINT_KERN_ALERT == 1 -+ -+#if ICP_OCF_PRINT_KERN_ERRS == 1 -+#define EPRINTK(args...) \ -+{ \ -+ ICP_EPRINTK(args); \ -+} -+ -+#else //ICP_OCF_PRINT_KERN_ERRS == 1 -+ -+#define EPRINTK(args...) -+ -+#endif //ICP_OCF_PRINT_KERN_ERRS == 1 -+ -+#define IPRINTK(args...) \ -+{ \ -+ ICP_IPRINTK(args); \ -+} -+ -+/*DSA Prime Q size in bytes (as defined in the standard) */ -+#define DSA_RS_SIGN_PRIMEQ_SIZE_IN_BYTES (20) -+ -+#define BITS_TO_BYTES(bytes, bits) \ -+ bytes = (bits + NUM_BITS_IN_BYTE_MINUS_ONE) / NUM_BITS_IN_BYTE -+ -+typedef enum { -+ ICP_OCF_DRV_ALG_CIPHER = 0, -+ ICP_OCF_DRV_ALG_HASH -+} icp_ocf_drv_alg_type_t; -+ -+typedef ICP_LIST_HEAD(icp_drvSessionListHead_s, -+ icp_drvSessionData) icp_drvSessionListHead_t; -+ -+/*Values used to derisk chances of performs being called against -+deregistered sessions (for which the slab page has been reclaimed) -+This is not a fix - since page frames are reclaimed from a slab, one cannot -+rely on that memory not being re-used by another app.*/ -+typedef enum { -+ ICP_SESSION_INITIALISED = 0x5C5C5C, -+ ICP_SESSION_RUNNING = 0x005C00, -+ ICP_SESSION_DEREGISTERED = 0xC5C5C5 -+} usage_derisk; -+ -+/* This struct is required for deferred session -+ deregistration as a work queue function can -+ only have one argument*/ -+struct icp_ocfDrvFreeLacSession { -+ CpaCySymSessionCtx sessionToDeregister; -+ icp_workstruct work; -+}; -+ -+/* -+This is the OCF<->OCF_DRV session object: -+ -+1.listNode -+ The first member is a listNode. These session objects are added to a linked -+ list in order to make it easier to remove them all at session exit time. -+ -+2.inUse -+ The second member is used to give the session object state and derisk the -+ possibility of OCF batch calls executing against a deregistered session (as -+ described above). -+ -+3.sessHandle -+ The third member is a LAC<->OCF_DRV session handle (initialised with the first -+ perform request for that session). -+ -+4.lacSessCtx -+ The fourth is the LAC session context. All the parameters for this structure -+ are only known when the first perform request for this session occurs. That is -+ why the OCF EP80579 Driver only registers a new LAC session at perform time -+*/ -+struct icp_drvSessionData { -+ ICP_LIST_ENTRY(icp_drvSessionData) listNode; -+ usage_derisk inUse; -+ CpaCySymSessionCtx sessHandle; -+ CpaCySymSessionSetupData lacSessCtx; -+}; -+ -+/* These are all defined in icp_common.c */ -+extern icp_atomic_t lac_session_failed_dereg_count; -+extern icp_atomic_t icp_ocfDrvIsExiting; -+extern icp_atomic_t num_ocf_to_drv_registered_sessions; -+ -+extern int32_t icp_ocfDrvDriverId; -+ -+extern icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead; -+extern icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead_FreeMemList; -+extern icp_workqueue *icp_ocfDrvFreeLacSessionWorkQ; -+extern icp_spinlock_t icp_ocfDrvSymSessInfoListSpinlock; -+ -+/*Slab zones for symettric functionality, instantiated in icp_common.c*/ -+extern icp_kmem_cache drvSessionData_zone; -+extern icp_kmem_cache drvOpData_zone; -+ -+/*Slabs zones for asymettric functionality, instantiated in icp_common.c*/ -+extern icp_kmem_cache drvDH_zone; -+extern icp_kmem_cache drvLnModExp_zone; -+extern icp_kmem_cache drvRSADecrypt_zone; -+extern icp_kmem_cache drvRSAPrivateKey_zone; -+extern icp_kmem_cache drvDSARSSign_zone; -+extern icp_kmem_cache drvDSARSSignKValue_zone; -+extern icp_kmem_cache drvDSAVerify_zone; -+ -+/* Module parameters defined in icp_cpmmon.c*/ -+ -+/* Module parameters - gives the number of times LAC deregistration shall be -+ re-tried */ -+extern int num_dereg_retries; -+ -+/* Module parameter - gives the delay time in jiffies before a LAC session -+ shall be attempted to be deregistered again */ -+extern int dereg_retry_delay_in_jiffies; -+ -+/* Module parameter - gives the maximum number of sessions possible between -+ OCF and the OCF EP80579 Driver. If set to zero, there is no limit.*/ -+extern int max_sessions; -+ -+/*Slab zones for flatbuffers and bufferlist*/ -+extern icp_kmem_cache drvFlatBuffer_zone; -+ -+#define ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS (16) -+ -+struct icp_drvBuffListInfo { -+ Cpa16U numBuffers; -+ Cpa32U metaSize; -+ Cpa32U metaOffset; -+ Cpa32U buffListSize; -+}; -+ -+extern struct icp_drvBuffListInfo defBuffListInfo; -+ -+/* This struct is used to keep a reference to the relevant node in the list -+ of sessionData structs, to the buffer type required by OCF and to the OCF -+ provided crp struct that needs to be returned. All this info is needed in -+ the callback function.*/ -+struct icp_drvOpData { -+ CpaCySymOpData lacOpData; -+ uint32_t digestSizeInBytes; -+ struct cryptop *crp; -+ uint8_t bufferType; -+ uint8_t ivData[MAX_IV_LEN_IN_BYTES]; -+ uint16_t numBufferListArray; -+ CpaBufferList srcBuffer; -+ CpaFlatBuffer bufferListArray[ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS]; -+ CpaBoolean verifyResult; -+}; -+ -+/* Create a new session between OCF and this driver*/ -+int icp_ocfDrvNewSession(icp_device_t dev, uint32_t * sild, -+ struct cryptoini *cri); -+ -+/* Free a session between this driver and the Quick Assist Framework*/ -+int icp_ocfDrvFreeLACSession(icp_device_t dev, uint64_t sid); -+ -+/* Defer freeing a Quick Assist session*/ -+void icp_ocfDrvDeferedFreeLacSessionProcess(void *arg); -+ -+/* Process OCF cryptographic request for a symmetric algorithm*/ -+int icp_ocfDrvSymProcess(icp_device_t dev, struct cryptop *crp, int hint); -+ -+/* Process OCF cryptographic request for an asymmetric algorithm*/ -+int icp_ocfDrvPkeProcess(icp_device_t dev, struct cryptkop *krp, int hint); -+ -+/* Populate a buffer with random data*/ -+int icp_ocfDrvReadRandom(void *arg, uint32_t * buf, int maxwords); -+ -+/* Retry Quick Assist session deregistration*/ -+int icp_ocfDrvDeregRetry(CpaCySymSessionCtx sessionToDeregister); -+ -+/* Convert an OS scatter gather list to a CPA buffer list*/ -+int icp_ocfDrvPacketBuffToBufferList(icp_packet_buffer_t * pPacketBuffer, -+ CpaBufferList * bufferList); -+ -+/* Convert a CPA buffer list to an OS scatter gather list*/ -+int icp_ocfDrvBufferListToPacketBuff(CpaBufferList * bufferList, -+ icp_packet_buffer_t ** pPacketBuffer); -+ -+/* Get the number of buffers in an OS scatter gather list*/ -+uint16_t icp_ocfDrvGetPacketBuffFrags(icp_packet_buffer_t * pPacketBuffer); -+ -+/* Convert a single OS buffer to a CPA Flat Buffer*/ -+void icp_ocfDrvSinglePacketBuffToFlatBuffer(icp_packet_buffer_t * pPacketBuffer, -+ CpaFlatBuffer * pFlatBuffer); -+ -+/* Add pointer and length to a CPA Flat Buffer structure*/ -+void icp_ocfDrvPtrAndLenToFlatBuffer(void *pData, uint32_t len, -+ CpaFlatBuffer * pFlatBuffer); -+ -+/* Convert pointer and length values to a CPA buffer list*/ -+void icp_ocfDrvPtrAndLenToBufferList(void *pDataIn, uint32_t length, -+ CpaBufferList * pBufferList); -+ -+/* Convert a CPA buffer list to pointer and length values*/ -+void icp_ocfDrvBufferListToPtrAndLen(CpaBufferList * pBufferList, -+ void **ppDataOut, uint32_t * pLength); -+ -+/* Set the number of flat buffers in bufferlist and the size of memory -+ to allocate for the pPrivateMetaData member of the CpaBufferList.*/ -+int icp_ocfDrvBufferListMemInfo(uint16_t numBuffers, -+ struct icp_drvBuffListInfo *buffListInfo); -+ -+/* Find pointer position of the digest within an OS scatter gather list*/ -+uint8_t *icp_ocfDrvPacketBufferDigestPointerFind(struct icp_drvOpData -+ *drvOpData, -+ int offsetInBytes, -+ uint32_t digestSizeInBytes); -+ -+/*This top level function is used to find a pointer to where a digest is -+ stored/needs to be inserted. */ -+uint8_t *icp_ocfDrvDigestPointerFind(struct icp_drvOpData *drvOpData, -+ struct cryptodesc *crp_desc); -+ -+/* Free a CPA flat buffer*/ -+void icp_ocfDrvFreeFlatBuffer(CpaFlatBuffer * pFlatBuffer); -+ -+/* This function will allocate memory for the pPrivateMetaData -+ member of CpaBufferList. */ -+int icp_ocfDrvAllocMetaData(CpaBufferList * pBufferList, -+ struct icp_drvOpData *pOpData); -+ -+/* Free data allocated for the pPrivateMetaData -+ member of CpaBufferList.*/ -+void icp_ocfDrvFreeMetaData(CpaBufferList * pBufferList); -+ -+#define ICP_CACHE_CREATE(cache_ID, cache_name) \ -+ icp_kmem_cache_create(cache_ID, sizeof(cache_name),ICP_KERNEL_CACHE_ALIGN,\ -+ ICP_KERNEL_CACHE_NOINIT) -+ -+#define ICP_CACHE_FREE(args...) \ -+ icp_kmem_cache_free (args) -+ -+#define ICP_CACHE_DESTROY(slab_zone)\ -+{\ -+ if(NULL != slab_zone){\ -+ icp_kmem_cache_destroy(slab_zone);\ -+ slab_zone = NULL;\ -+ }\ -+} -+ -+#endif -+/* ICP_OCF_H_ */ -diff -Nur linux-2.6.39.orig/crypto/ocf/ep80579/icp_sym.c linux-2.6.39/crypto/ocf/ep80579/icp_sym.c ---- linux-2.6.39.orig/crypto/ocf/ep80579/icp_sym.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/ep80579/icp_sym.c 2011-08-01 14:38:18.000000000 +0200 -@@ -0,0 +1,1153 @@ -+/*************************************************************************** -+ * -+ * This file is provided under a dual BSD/GPLv2 license. When using or -+ * redistributing this file, you may do so under either license. -+ * -+ * GPL LICENSE SUMMARY -+ * -+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of version 2 of the GNU General Public License as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. -+ * The full GNU General Public License is included in this distribution -+ * in the file called LICENSE.GPL. -+ * -+ * Contact Information: -+ * Intel Corporation -+ * -+ * BSD LICENSE -+ * -+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * * Neither the name of Intel Corporation nor the names of its -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * -+ * version: Security.L.1.0.2-229 -+ * -+ ***************************************************************************/ -+/* -+ * An OCF module that uses the API for Intel® QuickAssist Technology to do the -+ * cryptography. -+ * -+ * This driver requires the ICP Access Library that is available from Intel in -+ * order to operate. -+ */ -+ -+#include "icp_ocf.h" -+ -+/*This is the call back function for all symmetric cryptographic processes. -+ Its main functionality is to free driver crypto operation structure and to -+ call back to OCF*/ -+static void -+icp_ocfDrvSymCallBack(void *callbackTag, -+ CpaStatus status, -+ const CpaCySymOp operationType, -+ void *pOpData, -+ CpaBufferList * pDstBuffer, CpaBoolean verifyResult); -+ -+/*This function is used to extract crypto processing information from the OCF -+ inputs, so as that it may be passed onto LAC*/ -+static int -+icp_ocfDrvProcessDataSetup(struct icp_drvOpData *drvOpData, -+ struct cryptodesc *crp_desc); -+ -+/*This function checks whether the crp_desc argument pertains to a digest or a -+ cipher operation*/ -+static int icp_ocfDrvAlgCheck(struct cryptodesc *crp_desc); -+ -+/*This function copies all the passed in session context information and stores -+ it in a LAC context structure*/ -+static int -+icp_ocfDrvAlgorithmSetup(struct cryptoini *cri, -+ CpaCySymSessionSetupData * lacSessCtx); -+ -+/*This function is used to free an OCF->OCF_DRV session object*/ -+static void icp_ocfDrvFreeOCFSession(struct icp_drvSessionData *sessionData); -+ -+/*max IOV buffs supported in a UIO structure*/ -+#define NUM_IOV_SUPPORTED (1) -+ -+/* Name : icp_ocfDrvSymCallBack -+ * -+ * Description : When this function returns it signifies that the LAC -+ * component has completed the relevant symmetric operation. -+ * -+ * Notes : The callbackTag is a pointer to an icp_drvOpData. This memory -+ * object was passed to LAC for the cryptographic processing and contains all -+ * the relevant information for cleaning up buffer handles etc. so that the -+ * OCF EP80579 Driver portion of this crypto operation can be fully completed. -+ */ -+static void -+icp_ocfDrvSymCallBack(void *callbackTag, -+ CpaStatus status, -+ const CpaCySymOp operationType, -+ void *pOpData, -+ CpaBufferList * pDstBuffer, CpaBoolean verifyResult) -+{ -+ struct cryptop *crp = NULL; -+ struct icp_drvOpData *temp_drvOpData = -+ (struct icp_drvOpData *)callbackTag; -+ uint64_t *tempBasePtr = NULL; -+ uint32_t tempLen = 0; -+ -+ if (NULL == temp_drvOpData) { -+ DPRINTK("%s(): The callback from the LAC component" -+ " has failed due to Null userOpaque data" -+ "(status == %d).\n", __FUNCTION__, status); -+ DPRINTK("%s(): Unable to call OCF back! \n", __FUNCTION__); -+ return; -+ } -+ -+ crp = temp_drvOpData->crp; -+ crp->crp_etype = ICP_OCF_DRV_NO_CRYPTO_PROCESS_ERROR; -+ -+ if (NULL == pOpData) { -+ DPRINTK("%s(): The callback from the LAC component" -+ " has failed due to Null Symmetric Op data" -+ "(status == %d).\n", __FUNCTION__, status); -+ crp->crp_etype = ECANCELED; -+ crypto_done(crp); -+ return; -+ } -+ -+ if (NULL == pDstBuffer) { -+ DPRINTK("%s(): The callback from the LAC component" -+ " has failed due to Null Dst Bufferlist data" -+ "(status == %d).\n", __FUNCTION__, status); -+ crp->crp_etype = ECANCELED; -+ crypto_done(crp); -+ return; -+ } -+ -+ if (CPA_STATUS_SUCCESS == status) { -+ -+ if (temp_drvOpData->bufferType == ICP_CRYPTO_F_PACKET_BUF) { -+ if (ICP_OCF_DRV_STATUS_SUCCESS != -+ icp_ocfDrvBufferListToPacketBuff(pDstBuffer, -+ (icp_packet_buffer_t -+ **) -+ & (crp->crp_buf))) { -+ EPRINTK("%s(): BufferList to SkBuff " -+ "conversion error.\n", __FUNCTION__); -+ crp->crp_etype = EPERM; -+ } -+ } else { -+ icp_ocfDrvBufferListToPtrAndLen(pDstBuffer, -+ (void **)&tempBasePtr, -+ &tempLen); -+ crp->crp_olen = (int)tempLen; -+ } -+ -+ } else { -+ DPRINTK("%s(): The callback from the LAC component has failed" -+ "(status == %d).\n", __FUNCTION__, status); -+ -+ crp->crp_etype = ECANCELED; -+ } -+ -+ if (temp_drvOpData->numBufferListArray > -+ ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) { -+ icp_kfree(pDstBuffer->pBuffers); -+ } -+ icp_ocfDrvFreeMetaData(pDstBuffer); -+ ICP_CACHE_FREE(drvOpData_zone, temp_drvOpData); -+ -+ /* Invoke the OCF callback function */ -+ crypto_done(crp); -+ -+ return; -+} -+ -+/* Name : icp_ocfDrvNewSession -+ * -+ * Description : This function will create a new Driver<->OCF session -+ * -+ * Notes : LAC session registration happens during the first perform call. -+ * That is the first time we know all information about a given session. -+ */ -+int icp_ocfDrvNewSession(icp_device_t dev, uint32_t * sid, -+ struct cryptoini *cri) -+{ -+ struct icp_drvSessionData *sessionData = NULL; -+ uint32_t delete_session = 0; -+ -+ /* The SID passed in should be our driver ID. We can return the */ -+ /* local ID (LID) which is a unique identifier which we can use */ -+ /* to differentiate between the encrypt/decrypt LAC session handles */ -+ if (NULL == sid) { -+ EPRINTK("%s(): Invalid input parameters - NULL sid.\n", -+ __FUNCTION__); -+ return EINVAL; -+ } -+ -+ if (NULL == cri) { -+ EPRINTK("%s(): Invalid input parameters - NULL cryptoini.\n", -+ __FUNCTION__); -+ return EINVAL; -+ } -+ -+ if (icp_ocfDrvDriverId != *sid) { -+ EPRINTK("%s(): Invalid input parameters - bad driver ID\n", -+ __FUNCTION__); -+ EPRINTK("\t sid = 0x08%p \n \t cri = 0x08%p \n", sid, cri); -+ return EINVAL; -+ } -+ -+ sessionData = icp_kmem_cache_zalloc(drvSessionData_zone, ICP_M_NOWAIT); -+ if (NULL == sessionData) { -+ DPRINTK("%s():No memory for Session Data\n", __FUNCTION__); -+ return ENOMEM; -+ } -+ -+ /*ENTER CRITICAL SECTION */ -+ icp_spin_lockbh_lock(&icp_ocfDrvSymSessInfoListSpinlock); -+ /*put this check in the spinlock so no new sessions can be added to the -+ linked list when we are exiting */ -+ if (CPA_TRUE == icp_atomic_read(&icp_ocfDrvIsExiting)) { -+ delete_session++; -+ -+ } else if (NO_OCF_TO_DRV_MAX_SESSIONS != max_sessions) { -+ if (icp_atomic_read(&num_ocf_to_drv_registered_sessions) >= -+ (max_sessions - -+ icp_atomic_read(&lac_session_failed_dereg_count))) { -+ delete_session++; -+ } else { -+ icp_atomic_inc(&num_ocf_to_drv_registered_sessions); -+ /* Add to session data linked list */ -+ ICP_LIST_ADD(sessionData, &icp_ocfDrvGlobalSymListHead, -+ listNode); -+ } -+ -+ } else if (NO_OCF_TO_DRV_MAX_SESSIONS == max_sessions) { -+ ICP_LIST_ADD(sessionData, &icp_ocfDrvGlobalSymListHead, -+ listNode); -+ } -+ -+ sessionData->inUse = ICP_SESSION_INITIALISED; -+ -+ /*EXIT CRITICAL SECTION */ -+ icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock); -+ -+ if (delete_session) { -+ DPRINTK("%s():No Session handles available\n", __FUNCTION__); -+ ICP_CACHE_FREE(drvSessionData_zone, sessionData); -+ return EPERM; -+ } -+ -+ if (ICP_OCF_DRV_STATUS_SUCCESS != -+ icp_ocfDrvAlgorithmSetup(cri, &(sessionData->lacSessCtx))) { -+ DPRINTK("%s():algorithm not supported\n", __FUNCTION__); -+ icp_ocfDrvFreeOCFSession(sessionData); -+ return EINVAL; -+ } -+ -+ if (cri->cri_next) { -+ if (cri->cri_next->cri_next != NULL) { -+ DPRINTK("%s():only two chained algorithms supported\n", -+ __FUNCTION__); -+ icp_ocfDrvFreeOCFSession(sessionData); -+ return EPERM; -+ } -+ -+ if (ICP_OCF_DRV_STATUS_SUCCESS != -+ icp_ocfDrvAlgorithmSetup(cri->cri_next, -+ &(sessionData->lacSessCtx))) { -+ DPRINTK("%s():second algorithm not supported\n", -+ __FUNCTION__); -+ icp_ocfDrvFreeOCFSession(sessionData); -+ return EINVAL; -+ } -+ -+ sessionData->lacSessCtx.symOperation = -+ CPA_CY_SYM_OP_ALGORITHM_CHAINING; -+ } -+ -+ *sid = (uint32_t) sessionData; -+ -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+} -+ -+/* Name : icp_ocfDrvAlgorithmSetup -+ * -+ * Description : This function builds the session context data from the -+ * information supplied through OCF. Algorithm chain order and whether the -+ * session is Encrypt/Decrypt can only be found out at perform time however, so -+ * the session is registered with LAC at that time. -+ */ -+static int -+icp_ocfDrvAlgorithmSetup(struct cryptoini *cri, -+ CpaCySymSessionSetupData * lacSessCtx) -+{ -+ -+ lacSessCtx->sessionPriority = CPA_CY_PRIORITY_NORMAL; -+ -+ switch (cri->cri_alg) { -+ -+ case CRYPTO_NULL_CBC: -+ DPRINTK("%s(): NULL CBC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; -+ lacSessCtx->cipherSetupData.cipherAlgorithm = -+ CPA_CY_SYM_CIPHER_NULL; -+ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; -+ break; -+ -+ case CRYPTO_DES_CBC: -+ DPRINTK("%s(): DES CBC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; -+ lacSessCtx->cipherSetupData.cipherAlgorithm = -+ CPA_CY_SYM_CIPHER_DES_CBC; -+ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; -+ break; -+ -+ case CRYPTO_3DES_CBC: -+ DPRINTK("%s(): 3DES CBC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; -+ lacSessCtx->cipherSetupData.cipherAlgorithm = -+ CPA_CY_SYM_CIPHER_3DES_CBC; -+ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; -+ break; -+ -+ case CRYPTO_AES_CBC: -+ DPRINTK("%s(): AES CBC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; -+ lacSessCtx->cipherSetupData.cipherAlgorithm = -+ CPA_CY_SYM_CIPHER_AES_CBC; -+ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; -+ break; -+ -+ case CRYPTO_ARC4: -+ DPRINTK("%s(): ARC4\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; -+ lacSessCtx->cipherSetupData.cipherAlgorithm = -+ CPA_CY_SYM_CIPHER_ARC4; -+ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; -+ break; -+ -+ case CRYPTO_SHA1: -+ DPRINTK("%s(): SHA1\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_SHA1; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_SHA1_DIGEST_SIZE_IN_BYTES); -+ -+ break; -+ -+ case CRYPTO_SHA1_HMAC: -+ DPRINTK("%s(): SHA1_HMAC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_SHA1; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_SHA1_DIGEST_SIZE_IN_BYTES); -+ lacSessCtx->hashSetupData.authModeSetupData.authKey = -+ cri->cri_key; -+ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; -+ -+ break; -+ -+ case CRYPTO_SHA2_256: -+ DPRINTK("%s(): SHA256\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = -+ CPA_CY_SYM_HASH_SHA256; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_SHA256_DIGEST_SIZE_IN_BYTES); -+ -+ break; -+ -+ case CRYPTO_SHA2_256_HMAC: -+ DPRINTK("%s(): SHA256_HMAC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = -+ CPA_CY_SYM_HASH_SHA256; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_SHA256_DIGEST_SIZE_IN_BYTES); -+ lacSessCtx->hashSetupData.authModeSetupData.authKey = -+ cri->cri_key; -+ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; -+ -+ break; -+ -+ case CRYPTO_SHA2_384: -+ DPRINTK("%s(): SHA384\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = -+ CPA_CY_SYM_HASH_SHA384; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_SHA384_DIGEST_SIZE_IN_BYTES); -+ -+ break; -+ -+ case CRYPTO_SHA2_384_HMAC: -+ DPRINTK("%s(): SHA384_HMAC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = -+ CPA_CY_SYM_HASH_SHA384; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_SHA384_DIGEST_SIZE_IN_BYTES); -+ lacSessCtx->hashSetupData.authModeSetupData.authKey = -+ cri->cri_key; -+ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; -+ -+ break; -+ -+ case CRYPTO_SHA2_512: -+ DPRINTK("%s(): SHA512\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = -+ CPA_CY_SYM_HASH_SHA512; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_SHA512_DIGEST_SIZE_IN_BYTES); -+ -+ break; -+ -+ case CRYPTO_SHA2_512_HMAC: -+ DPRINTK("%s(): SHA512_HMAC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = -+ CPA_CY_SYM_HASH_SHA512; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_SHA512_DIGEST_SIZE_IN_BYTES); -+ lacSessCtx->hashSetupData.authModeSetupData.authKey = -+ cri->cri_key; -+ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; -+ -+ break; -+ -+ case CRYPTO_MD5: -+ DPRINTK("%s(): MD5\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_MD5; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_MD5_DIGEST_SIZE_IN_BYTES); -+ -+ break; -+ -+ case CRYPTO_MD5_HMAC: -+ DPRINTK("%s(): MD5_HMAC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_MD5; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_MD5_DIGEST_SIZE_IN_BYTES); -+ lacSessCtx->hashSetupData.authModeSetupData.authKey = -+ cri->cri_key; -+ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; -+ -+ break; -+ -+ default: -+ DPRINTK("%s(): ALG Setup FAIL\n", __FUNCTION__); -+ return ICP_OCF_DRV_STATUS_FAIL; -+ } -+ -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+} -+ -+/* Name : icp_ocfDrvFreeOCFSession -+ * -+ * Description : This function deletes all existing Session data representing -+ * the Cryptographic session established between OCF and this driver. This -+ * also includes freeing the memory allocated for the session context. The -+ * session object is also removed from the session linked list. -+ */ -+static void icp_ocfDrvFreeOCFSession(struct icp_drvSessionData *sessionData) -+{ -+ -+ sessionData->inUse = ICP_SESSION_DEREGISTERED; -+ -+ /*ENTER CRITICAL SECTION */ -+ icp_spin_lockbh_lock(&icp_ocfDrvSymSessInfoListSpinlock); -+ -+ if (CPA_TRUE == icp_atomic_read(&icp_ocfDrvIsExiting)) { -+ /*If the Driver is exiting, allow that process to -+ handle any deletions */ -+ /*EXIT CRITICAL SECTION */ -+ icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock); -+ return; -+ } -+ -+ icp_atomic_dec(&num_ocf_to_drv_registered_sessions); -+ -+ ICP_LIST_DEL(sessionData, listNode); -+ -+ /*EXIT CRITICAL SECTION */ -+ icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock); -+ -+ if (NULL != sessionData->sessHandle) { -+ icp_kfree(sessionData->sessHandle); -+ } -+ ICP_CACHE_FREE(drvSessionData_zone, sessionData); -+} -+ -+/* Name : icp_ocfDrvFreeLACSession -+ * -+ * Description : This attempts to deregister a LAC session. If it fails, the -+ * deregistation retry function is called. -+ */ -+int icp_ocfDrvFreeLACSession(icp_device_t dev, uint64_t sid) -+{ -+ CpaCySymSessionCtx sessionToDeregister = NULL; -+ struct icp_drvSessionData *sessionData = NULL; -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ int retval = 0; -+ -+ sessionData = (struct icp_drvSessionData *)CRYPTO_SESID2LID(sid); -+ if (NULL == sessionData) { -+ EPRINTK("%s(): OCF Free session called with Null Session ID.\n", -+ __FUNCTION__); -+ return EINVAL; -+ } -+ -+ sessionToDeregister = sessionData->sessHandle; -+ -+ if ((ICP_SESSION_INITIALISED != sessionData->inUse) && -+ (ICP_SESSION_RUNNING != sessionData->inUse) && -+ (ICP_SESSION_DEREGISTERED != sessionData->inUse)) { -+ DPRINTK("%s() Session not initialised.\n", __FUNCTION__); -+ return EINVAL; -+ } -+ -+ if (ICP_SESSION_RUNNING == sessionData->inUse) { -+ lacStatus = cpaCySymRemoveSession(CPA_INSTANCE_HANDLE_SINGLE, -+ sessionToDeregister); -+ if (CPA_STATUS_RETRY == lacStatus) { -+ if (ICP_OCF_DRV_STATUS_SUCCESS != -+ icp_ocfDrvDeregRetry(&sessionToDeregister)) { -+ /* the retry function increments the -+ dereg failed count */ -+ DPRINTK("%s(): LAC failed to deregister the " -+ "session. (localSessionId= %p)\n", -+ __FUNCTION__, sessionToDeregister); -+ retval = EPERM; -+ } -+ -+ } else if (CPA_STATUS_SUCCESS != lacStatus) { -+ DPRINTK("%s(): LAC failed to deregister the session. " -+ "localSessionId= %p, lacStatus = %d\n", -+ __FUNCTION__, sessionToDeregister, lacStatus); -+ icp_atomic_inc(&lac_session_failed_dereg_count); -+ retval = EPERM; -+ } -+ } else { -+ DPRINTK("%s() Session not registered with LAC.\n", -+ __FUNCTION__); -+ } -+ -+ icp_ocfDrvFreeOCFSession(sessionData); -+ return retval; -+ -+} -+ -+/* Name : icp_ocfDrvAlgCheck -+ * -+ * Description : This function checks whether the cryptodesc argument pertains -+ * to a sym or hash function -+ */ -+static int icp_ocfDrvAlgCheck(struct cryptodesc *crp_desc) -+{ -+ -+ if (crp_desc->crd_alg == CRYPTO_3DES_CBC || -+ crp_desc->crd_alg == CRYPTO_AES_CBC || -+ crp_desc->crd_alg == CRYPTO_DES_CBC || -+ crp_desc->crd_alg == CRYPTO_NULL_CBC || -+ crp_desc->crd_alg == CRYPTO_ARC4) { -+ return ICP_OCF_DRV_ALG_CIPHER; -+ } -+ -+ return ICP_OCF_DRV_ALG_HASH; -+} -+ -+/* Name : icp_ocfDrvSymProcess -+ * -+ * Description : This function will map symmetric functionality calls from OCF -+ * to the LAC API. It will also allocate memory to store the session context. -+ * -+ * Notes: If it is the first perform call for a given session, then a LAC -+ * session is registered. After the session is registered, no checks as -+ * to whether session paramaters have changed (e.g. alg chain order) are -+ * done. -+ */ -+int icp_ocfDrvSymProcess(icp_device_t dev, struct cryptop *crp, int hint) -+{ -+ struct icp_drvSessionData *sessionData = NULL; -+ struct icp_drvOpData *drvOpData = NULL; -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ Cpa32U sessionCtxSizeInBytes = 0; -+ -+ if (NULL == crp) { -+ DPRINTK("%s(): Invalid input parameters, cryptop is NULL\n", -+ __FUNCTION__); -+ return EINVAL; -+ } -+ -+ if (NULL == crp->crp_desc) { -+ DPRINTK("%s(): Invalid input parameters, no crp_desc attached " -+ "to crp\n", __FUNCTION__); -+ crp->crp_etype = EINVAL; -+ return EINVAL; -+ } -+ -+ if (NULL == crp->crp_buf) { -+ DPRINTK("%s(): Invalid input parameters, no buffer attached " -+ "to crp\n", __FUNCTION__); -+ crp->crp_etype = EINVAL; -+ return EINVAL; -+ } -+ -+ if (CPA_TRUE == icp_atomic_read(&icp_ocfDrvIsExiting)) { -+ crp->crp_etype = EFAULT; -+ return EFAULT; -+ } -+ -+ sessionData = (struct icp_drvSessionData *) -+ (CRYPTO_SESID2LID(crp->crp_sid)); -+ if (NULL == sessionData) { -+ DPRINTK("%s(): Invalid input parameters, Null Session ID \n", -+ __FUNCTION__); -+ crp->crp_etype = EINVAL; -+ return EINVAL; -+ } -+ -+/*If we get a request against a deregisted session, cancel operation*/ -+ if (ICP_SESSION_DEREGISTERED == sessionData->inUse) { -+ DPRINTK("%s(): Session ID %d was deregistered \n", -+ __FUNCTION__, (int)(CRYPTO_SESID2LID(crp->crp_sid))); -+ crp->crp_etype = EFAULT; -+ return EFAULT; -+ } -+ -+/*If none of the session states are set, then the session structure was either -+ not initialised properly or we are reading from a freed memory area (possible -+ due to OCF batch mode not removing queued requests against deregistered -+ sessions*/ -+ if (ICP_SESSION_INITIALISED != sessionData->inUse && -+ ICP_SESSION_RUNNING != sessionData->inUse) { -+ DPRINTK("%s(): Session - ID %d - not properly initialised or " -+ "memory freed back to the kernel \n", -+ __FUNCTION__, (int)(CRYPTO_SESID2LID(crp->crp_sid))); -+ crp->crp_etype = EINVAL; -+ return EINVAL; -+ } -+ -+ /*For the below checks, remember error checking is already done in LAC. -+ We're not validating inputs subsequent to registration */ -+ if (sessionData->inUse == ICP_SESSION_INITIALISED) { -+ DPRINTK("%s(): Initialising session\n", __FUNCTION__); -+ -+ if (NULL != crp->crp_desc->crd_next) { -+ if (ICP_OCF_DRV_ALG_CIPHER == -+ icp_ocfDrvAlgCheck(crp->crp_desc)) { -+ -+ sessionData->lacSessCtx.algChainOrder = -+ CPA_CY_SYM_ALG_CHAIN_ORDER_CIPHER_THEN_HASH; -+ -+ if (crp->crp_desc->crd_flags & CRD_F_ENCRYPT) { -+ sessionData->lacSessCtx.cipherSetupData. -+ cipherDirection = -+ CPA_CY_SYM_CIPHER_DIRECTION_ENCRYPT; -+ } else { -+ sessionData->lacSessCtx.cipherSetupData. -+ cipherDirection = -+ CPA_CY_SYM_CIPHER_DIRECTION_DECRYPT; -+ } -+ } else { -+ sessionData->lacSessCtx.algChainOrder = -+ CPA_CY_SYM_ALG_CHAIN_ORDER_HASH_THEN_CIPHER; -+ -+ if (crp->crp_desc->crd_next->crd_flags & -+ CRD_F_ENCRYPT) { -+ sessionData->lacSessCtx.cipherSetupData. -+ cipherDirection = -+ CPA_CY_SYM_CIPHER_DIRECTION_ENCRYPT; -+ } else { -+ sessionData->lacSessCtx.cipherSetupData. -+ cipherDirection = -+ CPA_CY_SYM_CIPHER_DIRECTION_DECRYPT; -+ } -+ -+ } -+ -+ } else if (ICP_OCF_DRV_ALG_CIPHER == -+ icp_ocfDrvAlgCheck(crp->crp_desc)) { -+ if (crp->crp_desc->crd_flags & CRD_F_ENCRYPT) { -+ sessionData->lacSessCtx.cipherSetupData. -+ cipherDirection = -+ CPA_CY_SYM_CIPHER_DIRECTION_ENCRYPT; -+ } else { -+ sessionData->lacSessCtx.cipherSetupData. -+ cipherDirection = -+ CPA_CY_SYM_CIPHER_DIRECTION_DECRYPT; -+ } -+ -+ } -+ -+ /*No action required for standalone Auth here */ -+ -+ /* Allocate memory for SymSessionCtx before the Session Registration */ -+ lacStatus = -+ cpaCySymSessionCtxGetSize(CPA_INSTANCE_HANDLE_SINGLE, -+ &(sessionData->lacSessCtx), -+ &sessionCtxSizeInBytes); -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): cpaCySymSessionCtxGetSize failed - %d\n", -+ __FUNCTION__, lacStatus); -+ crp->crp_etype = EINVAL; -+ return EINVAL; -+ } -+ sessionData->sessHandle = -+ icp_kmalloc(sessionCtxSizeInBytes, ICP_M_NOWAIT); -+ if (NULL == sessionData->sessHandle) { -+ EPRINTK -+ ("%s(): Failed to get memory for SymSessionCtx\n", -+ __FUNCTION__); -+ crp->crp_etype = ENOMEM; -+ return ENOMEM; -+ } -+ -+ lacStatus = cpaCySymInitSession(CPA_INSTANCE_HANDLE_SINGLE, -+ icp_ocfDrvSymCallBack, -+ &(sessionData->lacSessCtx), -+ sessionData->sessHandle); -+ -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): cpaCySymInitSession failed -%d \n", -+ __FUNCTION__, lacStatus); -+ crp->crp_etype = EFAULT; -+ return EFAULT; -+ } -+ -+ sessionData->inUse = ICP_SESSION_RUNNING; -+ } -+ -+ drvOpData = icp_kmem_cache_zalloc(drvOpData_zone, ICP_M_NOWAIT); -+ if (NULL == drvOpData) { -+ EPRINTK("%s():Failed to get memory for drvOpData\n", -+ __FUNCTION__); -+ crp->crp_etype = ENOMEM; -+ return ENOMEM; -+ } -+ -+ drvOpData->lacOpData.pSessionCtx = sessionData->sessHandle; -+ drvOpData->digestSizeInBytes = sessionData->lacSessCtx.hashSetupData. -+ digestResultLenInBytes; -+ drvOpData->crp = crp; -+ -+ /* Set the default buffer list array memory allocation */ -+ drvOpData->srcBuffer.pBuffers = drvOpData->bufferListArray; -+ drvOpData->numBufferListArray = ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS; -+ -+ if (ICP_OCF_DRV_STATUS_SUCCESS != -+ icp_ocfDrvProcessDataSetup(drvOpData, drvOpData->crp->crp_desc)) { -+ crp->crp_etype = EINVAL; -+ goto err; -+ } -+ -+ if (drvOpData->crp->crp_desc->crd_next != NULL) { -+ if (icp_ocfDrvProcessDataSetup(drvOpData, drvOpData->crp-> -+ crp_desc->crd_next)) { -+ crp->crp_etype = EINVAL; -+ goto err; -+ } -+ -+ } -+ -+ /* -+ * Allocate buffer list array memory if the data fragment is more than -+ * the default number (ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) and not -+ * calculated already -+ */ -+ if (crp->crp_flags & ICP_CRYPTO_F_PACKET_BUF) { -+ if (NULL == drvOpData->lacOpData.pDigestResult) { -+ drvOpData->numBufferListArray = -+ icp_ocfDrvGetPacketBuffFrags((icp_packet_buffer_t *) -+ crp->crp_buf); -+ } -+ -+ if (ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS < -+ drvOpData->numBufferListArray) { -+ DPRINTK("%s() numBufferListArray more than default\n", -+ __FUNCTION__); -+ drvOpData->srcBuffer.pBuffers = NULL; -+ drvOpData->srcBuffer.pBuffers = -+ icp_kmalloc(drvOpData->numBufferListArray * -+ sizeof(CpaFlatBuffer), ICP_M_NOWAIT); -+ if (NULL == drvOpData->srcBuffer.pBuffers) { -+ EPRINTK("%s() Failed to get memory for " -+ "pBuffers\n", __FUNCTION__); -+ ICP_CACHE_FREE(drvOpData_zone, drvOpData); -+ crp->crp_etype = ENOMEM; -+ return ENOMEM; -+ } -+ } -+ } -+ -+ /* -+ * Check the type of buffer structure we got and convert it into -+ * CpaBufferList format. -+ */ -+ if (crp->crp_flags & ICP_CRYPTO_F_PACKET_BUF) { -+ if (ICP_OCF_DRV_STATUS_SUCCESS != -+ icp_ocfDrvPacketBuffToBufferList((icp_packet_buffer_t *) -+ crp->crp_buf, -+ &(drvOpData->srcBuffer))) { -+ EPRINTK("%s():Failed to translate from packet buffer " -+ "to bufferlist\n", __FUNCTION__); -+ crp->crp_etype = EINVAL; -+ goto err; -+ } -+ -+ drvOpData->bufferType = ICP_CRYPTO_F_PACKET_BUF; -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ /* OCF only supports IOV of one entry. */ -+ if (NUM_IOV_SUPPORTED == -+ ((struct uio *)(crp->crp_buf))->uio_iovcnt) { -+ -+ icp_ocfDrvPtrAndLenToBufferList(((struct uio *)(crp-> -+ crp_buf))-> -+ uio_iov[0].iov_base, -+ ((struct uio *)(crp-> -+ crp_buf))-> -+ uio_iov[0].iov_len, -+ &(drvOpData-> -+ srcBuffer)); -+ -+ drvOpData->bufferType = CRYPTO_F_IOV; -+ -+ } else { -+ DPRINTK("%s():Unable to handle IOVs with lengths of " -+ "greater than one!\n", __FUNCTION__); -+ crp->crp_etype = EINVAL; -+ goto err; -+ } -+ -+ } else { -+ icp_ocfDrvPtrAndLenToBufferList(crp->crp_buf, -+ crp->crp_ilen, -+ &(drvOpData->srcBuffer)); -+ -+ drvOpData->bufferType = CRYPTO_BUF_CONTIG; -+ } -+ -+ /* Allocate srcBuffer's private meta data */ -+ if (ICP_OCF_DRV_STATUS_SUCCESS != -+ icp_ocfDrvAllocMetaData(&(drvOpData->srcBuffer), drvOpData)) { -+ EPRINTK("%s() icp_ocfDrvAllocMetaData failed\n", __FUNCTION__); -+ memset(&(drvOpData->lacOpData), 0, sizeof(CpaCySymOpData)); -+ crp->crp_etype = EINVAL; -+ goto err; -+ } -+ -+ /* Perform "in-place" crypto operation */ -+ lacStatus = cpaCySymPerformOp(CPA_INSTANCE_HANDLE_SINGLE, -+ (void *)drvOpData, -+ &(drvOpData->lacOpData), -+ &(drvOpData->srcBuffer), -+ &(drvOpData->srcBuffer), -+ &(drvOpData->verifyResult)); -+ if (CPA_STATUS_RETRY == lacStatus) { -+ DPRINTK("%s(): cpaCySymPerformOp retry, lacStatus = %d\n", -+ __FUNCTION__, lacStatus); -+ memset(&(drvOpData->lacOpData), 0, sizeof(CpaCySymOpData)); -+ crp->crp_etype = ERESTART; -+ goto err; -+ } -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): cpaCySymPerformOp failed, lacStatus = %d\n", -+ __FUNCTION__, lacStatus); -+ memset(&(drvOpData->lacOpData), 0, sizeof(CpaCySymOpData)); -+ crp->crp_etype = EINVAL; -+ goto err; -+ } -+ -+ return 0; //OCF success status value -+ -+ err: -+ if (drvOpData->numBufferListArray > ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) { -+ icp_kfree(drvOpData->srcBuffer.pBuffers); -+ } -+ icp_ocfDrvFreeMetaData(&(drvOpData->srcBuffer)); -+ ICP_CACHE_FREE(drvOpData_zone, drvOpData); -+ -+ return crp->crp_etype; -+} -+ -+/* Name : icp_ocfDrvProcessDataSetup -+ * -+ * Description : This function will setup all the cryptographic operation data -+ * that is required by LAC to execute the operation. -+ */ -+static int icp_ocfDrvProcessDataSetup(struct icp_drvOpData *drvOpData, -+ struct cryptodesc *crp_desc) -+{ -+ CpaCyRandGenOpData randGenOpData; -+ CpaFlatBuffer randData; -+ -+ drvOpData->lacOpData.packetType = CPA_CY_SYM_PACKET_TYPE_FULL; -+ -+ /* Convert from the cryptop to the ICP LAC crypto parameters */ -+ switch (crp_desc->crd_alg) { -+ case CRYPTO_NULL_CBC: -+ drvOpData->lacOpData. -+ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; -+ drvOpData->lacOpData. -+ messageLenToCipherInBytes = crp_desc->crd_len; -+ drvOpData->verifyResult = CPA_FALSE; -+ drvOpData->lacOpData.ivLenInBytes = NULL_BLOCK_LEN; -+ break; -+ case CRYPTO_DES_CBC: -+ drvOpData->lacOpData. -+ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; -+ drvOpData->lacOpData. -+ messageLenToCipherInBytes = crp_desc->crd_len; -+ drvOpData->verifyResult = CPA_FALSE; -+ drvOpData->lacOpData.ivLenInBytes = DES_BLOCK_LEN; -+ break; -+ case CRYPTO_3DES_CBC: -+ drvOpData->lacOpData. -+ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; -+ drvOpData->lacOpData. -+ messageLenToCipherInBytes = crp_desc->crd_len; -+ drvOpData->verifyResult = CPA_FALSE; -+ drvOpData->lacOpData.ivLenInBytes = DES3_BLOCK_LEN; -+ break; -+ case CRYPTO_ARC4: -+ drvOpData->lacOpData. -+ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; -+ drvOpData->lacOpData. -+ messageLenToCipherInBytes = crp_desc->crd_len; -+ drvOpData->verifyResult = CPA_FALSE; -+ drvOpData->lacOpData.ivLenInBytes = ARC4_COUNTER_LEN; -+ break; -+ case CRYPTO_AES_CBC: -+ drvOpData->lacOpData. -+ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; -+ drvOpData->lacOpData. -+ messageLenToCipherInBytes = crp_desc->crd_len; -+ drvOpData->verifyResult = CPA_FALSE; -+ drvOpData->lacOpData.ivLenInBytes = RIJNDAEL128_BLOCK_LEN; -+ break; -+ case CRYPTO_SHA1: -+ case CRYPTO_SHA1_HMAC: -+ case CRYPTO_SHA2_256: -+ case CRYPTO_SHA2_256_HMAC: -+ case CRYPTO_SHA2_384: -+ case CRYPTO_SHA2_384_HMAC: -+ case CRYPTO_SHA2_512: -+ case CRYPTO_SHA2_512_HMAC: -+ case CRYPTO_MD5: -+ case CRYPTO_MD5_HMAC: -+ drvOpData->lacOpData. -+ hashStartSrcOffsetInBytes = crp_desc->crd_skip; -+ drvOpData->lacOpData. -+ messageLenToHashInBytes = crp_desc->crd_len; -+ drvOpData->lacOpData. -+ pDigestResult = -+ icp_ocfDrvDigestPointerFind(drvOpData, crp_desc); -+ -+ if (NULL == drvOpData->lacOpData.pDigestResult) { -+ DPRINTK("%s(): ERROR - could not calculate " -+ "Digest Result memory address\n", __FUNCTION__); -+ return ICP_OCF_DRV_STATUS_FAIL; -+ } -+ -+ drvOpData->lacOpData.digestVerify = CPA_FALSE; -+ break; -+ default: -+ DPRINTK("%s(): Crypto process error - algorithm not " -+ "found \n", __FUNCTION__); -+ return ICP_OCF_DRV_STATUS_FAIL; -+ } -+ -+ /* Figure out what the IV is supposed to be */ -+ if ((crp_desc->crd_alg == CRYPTO_DES_CBC) || -+ (crp_desc->crd_alg == CRYPTO_3DES_CBC) || -+ (crp_desc->crd_alg == CRYPTO_AES_CBC)) { -+ /*ARC4 doesn't use an IV */ -+ if (crp_desc->crd_flags & CRD_F_IV_EXPLICIT) { -+ /* Explicit IV provided to OCF */ -+ drvOpData->lacOpData.pIv = crp_desc->crd_iv; -+ } else { -+ /* IV is not explicitly provided to OCF */ -+ -+ /* Point the LAC OP Data IV pointer to our allocated -+ storage location for this session. */ -+ drvOpData->lacOpData.pIv = drvOpData->ivData; -+ -+ if ((crp_desc->crd_flags & CRD_F_ENCRYPT) && -+ ((crp_desc->crd_flags & CRD_F_IV_PRESENT) == 0)) { -+ -+ /* Encrypting - need to create IV */ -+ randGenOpData.generateBits = CPA_TRUE; -+ randGenOpData.lenInBytes = MAX_IV_LEN_IN_BYTES; -+ -+ icp_ocfDrvPtrAndLenToFlatBuffer((Cpa8U *) -+ drvOpData-> -+ ivData, -+ MAX_IV_LEN_IN_BYTES, -+ &randData); -+ -+ if (CPA_STATUS_SUCCESS != -+ cpaCyRandGen(CPA_INSTANCE_HANDLE_SINGLE, -+ NULL, NULL, -+ &randGenOpData, &randData)) { -+ DPRINTK("%s(): ERROR - Failed to" -+ " generate" -+ " Initialisation Vector\n", -+ __FUNCTION__); -+ return ICP_OCF_DRV_STATUS_FAIL; -+ } -+ -+ crypto_copyback(drvOpData->crp-> -+ crp_flags, -+ drvOpData->crp->crp_buf, -+ crp_desc->crd_inject, -+ drvOpData->lacOpData. -+ ivLenInBytes, -+ (caddr_t) (drvOpData->lacOpData. -+ pIv)); -+ } else { -+ /* Reading IV from buffer */ -+ crypto_copydata(drvOpData->crp-> -+ crp_flags, -+ drvOpData->crp->crp_buf, -+ crp_desc->crd_inject, -+ drvOpData->lacOpData. -+ ivLenInBytes, -+ (caddr_t) (drvOpData->lacOpData. -+ pIv)); -+ } -+ -+ } -+ -+ } -+ -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+} -+ -+/* Name : icp_ocfDrvDigestPointerFind -+ * -+ * Description : This function is used to find the memory address of where the -+ * digest information shall be stored in. Input buffer types are an skbuff, iov -+ * or flat buffer. The address is found using the buffer data start address and -+ * an offset. -+ * -+ * Note: In the case of a linux skbuff, the digest address may exist within -+ * a memory space linked to from the start buffer. These linked memory spaces -+ * must be traversed by the data length offset in order to find the digest start -+ * address. Whether there is enough space for the digest must also be checked. -+ */ -+uint8_t *icp_ocfDrvDigestPointerFind(struct icp_drvOpData * drvOpData, -+ struct cryptodesc * crp_desc) -+{ -+ -+ int offsetInBytes = crp_desc->crd_inject; -+ uint32_t digestSizeInBytes = drvOpData->digestSizeInBytes; -+ uint8_t *flat_buffer_base = NULL; -+ int flat_buffer_length = 0; -+ -+ if (drvOpData->crp->crp_flags & ICP_CRYPTO_F_PACKET_BUF) { -+ -+ return icp_ocfDrvPacketBufferDigestPointerFind(drvOpData, -+ offsetInBytes, -+ digestSizeInBytes); -+ -+ } else { -+ /* IOV or flat buffer */ -+ if (drvOpData->crp->crp_flags & CRYPTO_F_IOV) { -+ /*single IOV check has already been done */ -+ flat_buffer_base = ((struct uio *) -+ (drvOpData->crp->crp_buf))-> -+ uio_iov[0].iov_base; -+ flat_buffer_length = ((struct uio *) -+ (drvOpData->crp->crp_buf))-> -+ uio_iov[0].iov_len; -+ } else { -+ flat_buffer_base = (uint8_t *) drvOpData->crp->crp_buf; -+ flat_buffer_length = drvOpData->crp->crp_ilen; -+ } -+ -+ if (flat_buffer_length < (offsetInBytes + digestSizeInBytes)) { -+ DPRINTK("%s() Not enough space for Digest " -+ "(IOV/Flat Buffer) \n", __FUNCTION__); -+ return NULL; -+ } else { -+ return (uint8_t *) (flat_buffer_base + offsetInBytes); -+ } -+ } -+ DPRINTK("%s() Should not reach this point\n", __FUNCTION__); -+ return NULL; -+} -diff -Nur linux-2.6.39.orig/crypto/ocf/hifn/Makefile linux-2.6.39/crypto/ocf/hifn/Makefile ---- linux-2.6.39.orig/crypto/ocf/hifn/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/hifn/Makefile 2011-08-01 14:38:18.000000000 +0200 -@@ -0,0 +1,13 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+obj-$(CONFIG_OCF_HIFN) += hifn7751.o -+obj-$(CONFIG_OCF_HIFNHIPP) += hifnHIPP.o -+ -+obj ?= . -+EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/hifn/hifn7751.c linux-2.6.39/crypto/ocf/hifn/hifn7751.c ---- linux-2.6.39.orig/crypto/ocf/hifn/hifn7751.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/hifn/hifn7751.c 2011-08-01 14:39:27.000000000 +0200 -@@ -0,0 +1,2973 @@ -+/* $OpenBSD: hifn7751.c,v 1.120 2002/05/17 00:33:34 deraadt Exp $ */ -+ -+/*- -+ * Invertex AEON / Hifn 7751 driver -+ * Copyright (c) 1999 Invertex Inc. All rights reserved. -+ * Copyright (c) 1999 Theo de Raadt -+ * Copyright (c) 2000-2001 Network Security Technologies, Inc. -+ * http://www.netsec.net -+ * Copyright (c) 2003 Hifn Inc. -+ * -+ * This driver is based on a previous driver by Invertex, for which they -+ * requested: Please send any comments, feedback, bug-fixes, or feature -+ * requests to software@invertex.com. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored in part by the Defense Advanced Research Projects -+ * Agency (DARPA) and Air Force Research Laboratory, Air Force -+ * Materiel Command, USAF, under agreement number F30602-01-2-0537. -+ * -+ * -+__FBSDID("$FreeBSD: src/sys/dev/hifn/hifn7751.c,v 1.40 2007/03/21 03:42:49 sam Exp $"); -+ */ -+ -+/* -+ * Driver for various Hifn encryption processors. -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+ -+#if 1 -+#define DPRINTF(a...) if (hifn_debug) { \ -+ printk("%s: ", sc ? \ -+ device_get_nameunit(sc->sc_dev) : "hifn"); \ -+ printk(a); \ -+ } else -+#else -+#define DPRINTF(a...) -+#endif -+ -+static inline int -+pci_get_revid(struct pci_dev *dev) -+{ -+ u8 rid = 0; -+ pci_read_config_byte(dev, PCI_REVISION_ID, &rid); -+ return rid; -+} -+ -+static struct hifn_stats hifnstats; -+ -+#define debug hifn_debug -+int hifn_debug = 0; -+module_param(hifn_debug, int, 0644); -+MODULE_PARM_DESC(hifn_debug, "Enable debug"); -+ -+int hifn_maxbatch = 1; -+module_param(hifn_maxbatch, int, 0644); -+MODULE_PARM_DESC(hifn_maxbatch, "max ops to batch w/o interrupt"); -+ -+int hifn_cache_linesize = 0x10; -+module_param(hifn_cache_linesize, int, 0444); -+MODULE_PARM_DESC(hifn_cache_linesize, "PCI config cache line size"); -+ -+#ifdef MODULE_PARM -+char *hifn_pllconfig = NULL; -+MODULE_PARM(hifn_pllconfig, "s"); -+#else -+char hifn_pllconfig[32]; /* This setting is RO after loading */ -+module_param_string(hifn_pllconfig, hifn_pllconfig, 32, 0444); -+#endif -+MODULE_PARM_DESC(hifn_pllconfig, "PLL config, ie., pci66, ext33, ..."); -+ -+#ifdef HIFN_VULCANDEV -+#include -+#include -+ -+static struct cdevsw vulcanpk_cdevsw; /* forward declaration */ -+#endif -+ -+/* -+ * Prototypes and count for the pci_device structure -+ */ -+static int hifn_probe(struct pci_dev *dev, const struct pci_device_id *ent); -+static void hifn_remove(struct pci_dev *dev); -+ -+static int hifn_newsession(device_t, u_int32_t *, struct cryptoini *); -+static int hifn_freesession(device_t, u_int64_t); -+static int hifn_process(device_t, struct cryptop *, int); -+ -+static device_method_t hifn_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, hifn_newsession), -+ DEVMETHOD(cryptodev_freesession,hifn_freesession), -+ DEVMETHOD(cryptodev_process, hifn_process), -+}; -+ -+static void hifn_reset_board(struct hifn_softc *, int); -+static void hifn_reset_puc(struct hifn_softc *); -+static void hifn_puc_wait(struct hifn_softc *); -+static int hifn_enable_crypto(struct hifn_softc *); -+static void hifn_set_retry(struct hifn_softc *sc); -+static void hifn_init_dma(struct hifn_softc *); -+static void hifn_init_pci_registers(struct hifn_softc *); -+static int hifn_sramsize(struct hifn_softc *); -+static int hifn_dramsize(struct hifn_softc *); -+static int hifn_ramtype(struct hifn_softc *); -+static void hifn_sessions(struct hifn_softc *); -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) -+static irqreturn_t hifn_intr(int irq, void *arg); -+#else -+static irqreturn_t hifn_intr(int irq, void *arg, struct pt_regs *regs); -+#endif -+static u_int hifn_write_command(struct hifn_command *, u_int8_t *); -+static u_int32_t hifn_next_signature(u_int32_t a, u_int cnt); -+static void hifn_callback(struct hifn_softc *, struct hifn_command *, u_int8_t *); -+static int hifn_crypto(struct hifn_softc *, struct hifn_command *, struct cryptop *, int); -+static int hifn_readramaddr(struct hifn_softc *, int, u_int8_t *); -+static int hifn_writeramaddr(struct hifn_softc *, int, u_int8_t *); -+static int hifn_dmamap_load_src(struct hifn_softc *, struct hifn_command *); -+static int hifn_dmamap_load_dst(struct hifn_softc *, struct hifn_command *); -+static int hifn_init_pubrng(struct hifn_softc *); -+static void hifn_tick(unsigned long arg); -+static void hifn_abort(struct hifn_softc *); -+static void hifn_alloc_slot(struct hifn_softc *, int *, int *, int *, int *); -+ -+static void hifn_write_reg_0(struct hifn_softc *, bus_size_t, u_int32_t); -+static void hifn_write_reg_1(struct hifn_softc *, bus_size_t, u_int32_t); -+ -+#ifdef CONFIG_OCF_RANDOMHARVEST -+static int hifn_read_random(void *arg, u_int32_t *buf, int len); -+#endif -+ -+#define HIFN_MAX_CHIPS 8 -+static struct hifn_softc *hifn_chip_idx[HIFN_MAX_CHIPS]; -+ -+static __inline u_int32_t -+READ_REG_0(struct hifn_softc *sc, bus_size_t reg) -+{ -+ u_int32_t v = readl(sc->sc_bar0 + reg); -+ sc->sc_bar0_lastreg = (bus_size_t) -1; -+ return (v); -+} -+#define WRITE_REG_0(sc, reg, val) hifn_write_reg_0(sc, reg, val) -+ -+static __inline u_int32_t -+READ_REG_1(struct hifn_softc *sc, bus_size_t reg) -+{ -+ u_int32_t v = readl(sc->sc_bar1 + reg); -+ sc->sc_bar1_lastreg = (bus_size_t) -1; -+ return (v); -+} -+#define WRITE_REG_1(sc, reg, val) hifn_write_reg_1(sc, reg, val) -+ -+/* -+ * map in a given buffer (great on some arches :-) -+ */ -+ -+static int -+pci_map_uio(struct hifn_softc *sc, struct hifn_operand *buf, struct uio *uio) -+{ -+ struct iovec *iov = uio->uio_iov; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ buf->mapsize = 0; -+ for (buf->nsegs = 0; buf->nsegs < uio->uio_iovcnt; ) { -+ buf->segs[buf->nsegs].ds_addr = pci_map_single(sc->sc_pcidev, -+ iov->iov_base, iov->iov_len, -+ PCI_DMA_BIDIRECTIONAL); -+ buf->segs[buf->nsegs].ds_len = iov->iov_len; -+ buf->mapsize += iov->iov_len; -+ iov++; -+ buf->nsegs++; -+ } -+ /* identify this buffer by the first segment */ -+ buf->map = (void *) buf->segs[0].ds_addr; -+ return(0); -+} -+ -+/* -+ * map in a given sk_buff -+ */ -+ -+static int -+pci_map_skb(struct hifn_softc *sc,struct hifn_operand *buf,struct sk_buff *skb) -+{ -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ buf->mapsize = 0; -+ -+ buf->segs[0].ds_addr = pci_map_single(sc->sc_pcidev, -+ skb->data, skb_headlen(skb), PCI_DMA_BIDIRECTIONAL); -+ buf->segs[0].ds_len = skb_headlen(skb); -+ buf->mapsize += buf->segs[0].ds_len; -+ -+ buf->nsegs = 1; -+ -+ for (i = 0; i < skb_shinfo(skb)->nr_frags; ) { -+ buf->segs[buf->nsegs].ds_len = skb_shinfo(skb)->frags[i].size; -+ buf->segs[buf->nsegs].ds_addr = pci_map_single(sc->sc_pcidev, -+ page_address(skb_shinfo(skb)->frags[i].page) + -+ skb_shinfo(skb)->frags[i].page_offset, -+ buf->segs[buf->nsegs].ds_len, PCI_DMA_BIDIRECTIONAL); -+ buf->mapsize += buf->segs[buf->nsegs].ds_len; -+ buf->nsegs++; -+ } -+ -+ /* identify this buffer by the first segment */ -+ buf->map = (void *) buf->segs[0].ds_addr; -+ return(0); -+} -+ -+/* -+ * map in a given contiguous buffer -+ */ -+ -+static int -+pci_map_buf(struct hifn_softc *sc,struct hifn_operand *buf, void *b, int len) -+{ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ buf->mapsize = 0; -+ buf->segs[0].ds_addr = pci_map_single(sc->sc_pcidev, -+ b, len, PCI_DMA_BIDIRECTIONAL); -+ buf->segs[0].ds_len = len; -+ buf->mapsize += buf->segs[0].ds_len; -+ buf->nsegs = 1; -+ -+ /* identify this buffer by the first segment */ -+ buf->map = (void *) buf->segs[0].ds_addr; -+ return(0); -+} -+ -+#if 0 /* not needed at this time */ -+static void -+pci_sync_iov(struct hifn_softc *sc, struct hifn_operand *buf) -+{ -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ for (i = 0; i < buf->nsegs; i++) -+ pci_dma_sync_single_for_cpu(sc->sc_pcidev, buf->segs[i].ds_addr, -+ buf->segs[i].ds_len, PCI_DMA_BIDIRECTIONAL); -+} -+#endif -+ -+static void -+pci_unmap_buf(struct hifn_softc *sc, struct hifn_operand *buf) -+{ -+ int i; -+ DPRINTF("%s()\n", __FUNCTION__); -+ for (i = 0; i < buf->nsegs; i++) { -+ pci_unmap_single(sc->sc_pcidev, buf->segs[i].ds_addr, -+ buf->segs[i].ds_len, PCI_DMA_BIDIRECTIONAL); -+ buf->segs[i].ds_addr = 0; -+ buf->segs[i].ds_len = 0; -+ } -+ buf->nsegs = 0; -+ buf->mapsize = 0; -+ buf->map = 0; -+} -+ -+static const char* -+hifn_partname(struct hifn_softc *sc) -+{ -+ /* XXX sprintf numbers when not decoded */ -+ switch (pci_get_vendor(sc->sc_pcidev)) { -+ case PCI_VENDOR_HIFN: -+ switch (pci_get_device(sc->sc_pcidev)) { -+ case PCI_PRODUCT_HIFN_6500: return "Hifn 6500"; -+ case PCI_PRODUCT_HIFN_7751: return "Hifn 7751"; -+ case PCI_PRODUCT_HIFN_7811: return "Hifn 7811"; -+ case PCI_PRODUCT_HIFN_7951: return "Hifn 7951"; -+ case PCI_PRODUCT_HIFN_7955: return "Hifn 7955"; -+ case PCI_PRODUCT_HIFN_7956: return "Hifn 7956"; -+ } -+ return "Hifn unknown-part"; -+ case PCI_VENDOR_INVERTEX: -+ switch (pci_get_device(sc->sc_pcidev)) { -+ case PCI_PRODUCT_INVERTEX_AEON: return "Invertex AEON"; -+ } -+ return "Invertex unknown-part"; -+ case PCI_VENDOR_NETSEC: -+ switch (pci_get_device(sc->sc_pcidev)) { -+ case PCI_PRODUCT_NETSEC_7751: return "NetSec 7751"; -+ } -+ return "NetSec unknown-part"; -+ } -+ return "Unknown-vendor unknown-part"; -+} -+ -+static u_int -+checkmaxmin(struct pci_dev *dev, const char *what, u_int v, u_int min, u_int max) -+{ -+ struct hifn_softc *sc = pci_get_drvdata(dev); -+ if (v > max) { -+ device_printf(sc->sc_dev, "Warning, %s %u out of range, " -+ "using max %u\n", what, v, max); -+ v = max; -+ } else if (v < min) { -+ device_printf(sc->sc_dev, "Warning, %s %u out of range, " -+ "using min %u\n", what, v, min); -+ v = min; -+ } -+ return v; -+} -+ -+/* -+ * Select PLL configuration for 795x parts. This is complicated in -+ * that we cannot determine the optimal parameters without user input. -+ * The reference clock is derived from an external clock through a -+ * multiplier. The external clock is either the host bus (i.e. PCI) -+ * or an external clock generator. When using the PCI bus we assume -+ * the clock is either 33 or 66 MHz; for an external source we cannot -+ * tell the speed. -+ * -+ * PLL configuration is done with a string: "pci" for PCI bus, or "ext" -+ * for an external source, followed by the frequency. We calculate -+ * the appropriate multiplier and PLL register contents accordingly. -+ * When no configuration is given we default to "pci66" since that -+ * always will allow the card to work. If a card is using the PCI -+ * bus clock and in a 33MHz slot then it will be operating at half -+ * speed until the correct information is provided. -+ * -+ * We use a default setting of "ext66" because according to Mike Ham -+ * of HiFn, almost every board in existence has an external crystal -+ * populated at 66Mhz. Using PCI can be a problem on modern motherboards, -+ * because PCI33 can have clocks from 0 to 33Mhz, and some have -+ * non-PCI-compliant spread-spectrum clocks, which can confuse the pll. -+ */ -+static void -+hifn_getpllconfig(struct pci_dev *dev, u_int *pll) -+{ -+ const char *pllspec = hifn_pllconfig; -+ u_int freq, mul, fl, fh; -+ u_int32_t pllconfig; -+ char *nxt; -+ -+ if (pllspec == NULL) -+ pllspec = "ext66"; -+ fl = 33, fh = 66; -+ pllconfig = 0; -+ if (strncmp(pllspec, "ext", 3) == 0) { -+ pllspec += 3; -+ pllconfig |= HIFN_PLL_REF_SEL; -+ switch (pci_get_device(dev)) { -+ case PCI_PRODUCT_HIFN_7955: -+ case PCI_PRODUCT_HIFN_7956: -+ fl = 20, fh = 100; -+ break; -+#ifdef notyet -+ case PCI_PRODUCT_HIFN_7954: -+ fl = 20, fh = 66; -+ break; -+#endif -+ } -+ } else if (strncmp(pllspec, "pci", 3) == 0) -+ pllspec += 3; -+ freq = strtoul(pllspec, &nxt, 10); -+ if (nxt == pllspec) -+ freq = 66; -+ else -+ freq = checkmaxmin(dev, "frequency", freq, fl, fh); -+ /* -+ * Calculate multiplier. We target a Fck of 266 MHz, -+ * allowing only even values, possibly rounded down. -+ * Multipliers > 8 must set the charge pump current. -+ */ -+ mul = checkmaxmin(dev, "PLL divisor", (266 / freq) &~ 1, 2, 12); -+ pllconfig |= (mul / 2 - 1) << HIFN_PLL_ND_SHIFT; -+ if (mul > 8) -+ pllconfig |= HIFN_PLL_IS; -+ *pll = pllconfig; -+} -+ -+/* -+ * Attach an interface that successfully probed. -+ */ -+static int -+hifn_probe(struct pci_dev *dev, const struct pci_device_id *ent) -+{ -+ struct hifn_softc *sc = NULL; -+ char rbase; -+ u_int16_t ena, rev; -+ int rseg, rc; -+ unsigned long mem_start, mem_len; -+ static int num_chips = 0; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (pci_enable_device(dev) < 0) -+ return(-ENODEV); -+ -+ if (pci_set_mwi(dev)) -+ return(-ENODEV); -+ -+ if (!dev->irq) { -+ printk("hifn: found device with no IRQ assigned. check BIOS settings!"); -+ pci_disable_device(dev); -+ return(-ENODEV); -+ } -+ -+ sc = (struct hifn_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); -+ if (!sc) -+ return(-ENOMEM); -+ memset(sc, 0, sizeof(*sc)); -+ -+ softc_device_init(sc, "hifn", num_chips, hifn_methods); -+ -+ sc->sc_pcidev = dev; -+ sc->sc_irq = -1; -+ sc->sc_cid = -1; -+ sc->sc_num = num_chips++; -+ if (sc->sc_num < HIFN_MAX_CHIPS) -+ hifn_chip_idx[sc->sc_num] = sc; -+ -+ pci_set_drvdata(sc->sc_pcidev, sc); -+ -+ spin_lock_init(&sc->sc_mtx); -+ -+ /* XXX handle power management */ -+ -+ /* -+ * The 7951 and 795x have a random number generator and -+ * public key support; note this. -+ */ -+ if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && -+ (pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 || -+ pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 || -+ pci_get_device(dev) == PCI_PRODUCT_HIFN_7956)) -+ sc->sc_flags = HIFN_HAS_RNG | HIFN_HAS_PUBLIC; -+ /* -+ * The 7811 has a random number generator and -+ * we also note it's identity 'cuz of some quirks. -+ */ -+ if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && -+ pci_get_device(dev) == PCI_PRODUCT_HIFN_7811) -+ sc->sc_flags |= HIFN_IS_7811 | HIFN_HAS_RNG; -+ -+ /* -+ * The 795x parts support AES. -+ */ -+ if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && -+ (pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 || -+ pci_get_device(dev) == PCI_PRODUCT_HIFN_7956)) { -+ sc->sc_flags |= HIFN_IS_7956 | HIFN_HAS_AES; -+ /* -+ * Select PLL configuration. This depends on the -+ * bus and board design and must be manually configured -+ * if the default setting is unacceptable. -+ */ -+ hifn_getpllconfig(dev, &sc->sc_pllconfig); -+ } -+ -+ /* -+ * Setup PCI resources. Note that we record the bus -+ * tag and handle for each register mapping, this is -+ * used by the READ_REG_0, WRITE_REG_0, READ_REG_1, -+ * and WRITE_REG_1 macros throughout the driver. -+ */ -+ mem_start = pci_resource_start(sc->sc_pcidev, 0); -+ mem_len = pci_resource_len(sc->sc_pcidev, 0); -+ sc->sc_bar0 = (ocf_iomem_t) ioremap(mem_start, mem_len); -+ if (!sc->sc_bar0) { -+ device_printf(sc->sc_dev, "cannot map bar%d register space\n", 0); -+ goto fail; -+ } -+ sc->sc_bar0_lastreg = (bus_size_t) -1; -+ -+ mem_start = pci_resource_start(sc->sc_pcidev, 1); -+ mem_len = pci_resource_len(sc->sc_pcidev, 1); -+ sc->sc_bar1 = (ocf_iomem_t) ioremap(mem_start, mem_len); -+ if (!sc->sc_bar1) { -+ device_printf(sc->sc_dev, "cannot map bar%d register space\n", 1); -+ goto fail; -+ } -+ sc->sc_bar1_lastreg = (bus_size_t) -1; -+ -+ /* fix up the bus size */ -+ if (pci_set_dma_mask(dev, DMA_32BIT_MASK)) { -+ device_printf(sc->sc_dev, "No usable DMA configuration, aborting.\n"); -+ goto fail; -+ } -+ if (pci_set_consistent_dma_mask(dev, DMA_32BIT_MASK)) { -+ device_printf(sc->sc_dev, -+ "No usable consistent DMA configuration, aborting.\n"); -+ goto fail; -+ } -+ -+ hifn_set_retry(sc); -+ -+ /* -+ * Setup the area where the Hifn DMA's descriptors -+ * and associated data structures. -+ */ -+ sc->sc_dma = (struct hifn_dma *) pci_alloc_consistent(dev, -+ sizeof(*sc->sc_dma), -+ &sc->sc_dma_physaddr); -+ if (!sc->sc_dma) { -+ device_printf(sc->sc_dev, "cannot alloc sc_dma\n"); -+ goto fail; -+ } -+ bzero(sc->sc_dma, sizeof(*sc->sc_dma)); -+ -+ /* -+ * Reset the board and do the ``secret handshake'' -+ * to enable the crypto support. Then complete the -+ * initialization procedure by setting up the interrupt -+ * and hooking in to the system crypto support so we'll -+ * get used for system services like the crypto device, -+ * IPsec, RNG device, etc. -+ */ -+ hifn_reset_board(sc, 0); -+ -+ if (hifn_enable_crypto(sc) != 0) { -+ device_printf(sc->sc_dev, "crypto enabling failed\n"); -+ goto fail; -+ } -+ hifn_reset_puc(sc); -+ -+ hifn_init_dma(sc); -+ hifn_init_pci_registers(sc); -+ -+ pci_set_master(sc->sc_pcidev); -+ -+ /* XXX can't dynamically determine ram type for 795x; force dram */ -+ if (sc->sc_flags & HIFN_IS_7956) -+ sc->sc_drammodel = 1; -+ else if (hifn_ramtype(sc)) -+ goto fail; -+ -+ if (sc->sc_drammodel == 0) -+ hifn_sramsize(sc); -+ else -+ hifn_dramsize(sc); -+ -+ /* -+ * Workaround for NetSec 7751 rev A: half ram size because two -+ * of the address lines were left floating -+ */ -+ if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC && -+ pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751 && -+ pci_get_revid(dev) == 0x61) /*XXX???*/ -+ sc->sc_ramsize >>= 1; -+ -+ /* -+ * Arrange the interrupt line. -+ */ -+ rc = request_irq(dev->irq, hifn_intr, IRQF_SHARED, "hifn", sc); -+ if (rc) { -+ device_printf(sc->sc_dev, "could not map interrupt: %d\n", rc); -+ goto fail; -+ } -+ sc->sc_irq = dev->irq; -+ -+ hifn_sessions(sc); -+ -+ /* -+ * NB: Keep only the low 16 bits; this masks the chip id -+ * from the 7951. -+ */ -+ rev = READ_REG_1(sc, HIFN_1_REVID) & 0xffff; -+ -+ rseg = sc->sc_ramsize / 1024; -+ rbase = 'K'; -+ if (sc->sc_ramsize >= (1024 * 1024)) { -+ rbase = 'M'; -+ rseg /= 1024; -+ } -+ device_printf(sc->sc_dev, "%s, rev %u, %d%cB %cram", -+ hifn_partname(sc), rev, -+ rseg, rbase, sc->sc_drammodel ? 'd' : 's'); -+ if (sc->sc_flags & HIFN_IS_7956) -+ printf(", pll=0x%x<%s clk, %ux mult>", -+ sc->sc_pllconfig, -+ sc->sc_pllconfig & HIFN_PLL_REF_SEL ? "ext" : "pci", -+ 2 + 2*((sc->sc_pllconfig & HIFN_PLL_ND) >> 11)); -+ printf("\n"); -+ -+ sc->sc_cid = crypto_get_driverid(softc_get_device(sc),CRYPTOCAP_F_HARDWARE); -+ if (sc->sc_cid < 0) { -+ device_printf(sc->sc_dev, "could not get crypto driver id\n"); -+ goto fail; -+ } -+ -+ WRITE_REG_0(sc, HIFN_0_PUCNFG, -+ READ_REG_0(sc, HIFN_0_PUCNFG) | HIFN_PUCNFG_CHIPID); -+ ena = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; -+ -+ switch (ena) { -+ case HIFN_PUSTAT_ENA_2: -+ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0); -+ if (sc->sc_flags & HIFN_HAS_AES) -+ crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); -+ /*FALLTHROUGH*/ -+ case HIFN_PUSTAT_ENA_1: -+ crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); -+ break; -+ } -+ -+ if (sc->sc_flags & (HIFN_HAS_PUBLIC | HIFN_HAS_RNG)) -+ hifn_init_pubrng(sc); -+ -+ init_timer(&sc->sc_tickto); -+ sc->sc_tickto.function = hifn_tick; -+ sc->sc_tickto.data = (unsigned long) sc->sc_num; -+ mod_timer(&sc->sc_tickto, jiffies + HZ); -+ -+ return (0); -+ -+fail: -+ if (sc->sc_cid >= 0) -+ crypto_unregister_all(sc->sc_cid); -+ if (sc->sc_irq != -1) -+ free_irq(sc->sc_irq, sc); -+ if (sc->sc_dma) { -+ /* Turn off DMA polling */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | -+ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); -+ -+ pci_free_consistent(sc->sc_pcidev, -+ sizeof(*sc->sc_dma), -+ sc->sc_dma, sc->sc_dma_physaddr); -+ } -+ kfree(sc); -+ return (-ENXIO); -+} -+ -+/* -+ * Detach an interface that successfully probed. -+ */ -+static void -+hifn_remove(struct pci_dev *dev) -+{ -+ struct hifn_softc *sc = pci_get_drvdata(dev); -+ unsigned long l_flags; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ KASSERT(sc != NULL, ("hifn_detach: null software carrier!")); -+ -+ /* disable interrupts */ -+ HIFN_LOCK(sc); -+ WRITE_REG_1(sc, HIFN_1_DMA_IER, 0); -+ HIFN_UNLOCK(sc); -+ -+ /*XXX other resources */ -+ del_timer_sync(&sc->sc_tickto); -+ -+ /* Turn off DMA polling */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | -+ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); -+ -+ crypto_unregister_all(sc->sc_cid); -+ -+ free_irq(sc->sc_irq, sc); -+ -+ pci_free_consistent(sc->sc_pcidev, sizeof(*sc->sc_dma), -+ sc->sc_dma, sc->sc_dma_physaddr); -+} -+ -+ -+static int -+hifn_init_pubrng(struct hifn_softc *sc) -+{ -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if ((sc->sc_flags & HIFN_IS_7811) == 0) { -+ /* Reset 7951 public key/rng engine */ -+ WRITE_REG_1(sc, HIFN_1_PUB_RESET, -+ READ_REG_1(sc, HIFN_1_PUB_RESET) | HIFN_PUBRST_RESET); -+ -+ for (i = 0; i < 100; i++) { -+ DELAY(1000); -+ if ((READ_REG_1(sc, HIFN_1_PUB_RESET) & -+ HIFN_PUBRST_RESET) == 0) -+ break; -+ } -+ -+ if (i == 100) { -+ device_printf(sc->sc_dev, "public key init failed\n"); -+ return (1); -+ } -+ } -+ -+ /* Enable the rng, if available */ -+#ifdef CONFIG_OCF_RANDOMHARVEST -+ if (sc->sc_flags & HIFN_HAS_RNG) { -+ if (sc->sc_flags & HIFN_IS_7811) { -+ u_int32_t r; -+ r = READ_REG_1(sc, HIFN_1_7811_RNGENA); -+ if (r & HIFN_7811_RNGENA_ENA) { -+ r &= ~HIFN_7811_RNGENA_ENA; -+ WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); -+ } -+ WRITE_REG_1(sc, HIFN_1_7811_RNGCFG, -+ HIFN_7811_RNGCFG_DEFL); -+ r |= HIFN_7811_RNGENA_ENA; -+ WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); -+ } else -+ WRITE_REG_1(sc, HIFN_1_RNG_CONFIG, -+ READ_REG_1(sc, HIFN_1_RNG_CONFIG) | -+ HIFN_RNGCFG_ENA); -+ -+ sc->sc_rngfirst = 1; -+ crypto_rregister(sc->sc_cid, hifn_read_random, sc); -+ } -+#endif -+ -+ /* Enable public key engine, if available */ -+ if (sc->sc_flags & HIFN_HAS_PUBLIC) { -+ WRITE_REG_1(sc, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE); -+ sc->sc_dmaier |= HIFN_DMAIER_PUBDONE; -+ WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); -+#ifdef HIFN_VULCANDEV -+ sc->sc_pkdev = make_dev(&vulcanpk_cdevsw, 0, -+ UID_ROOT, GID_WHEEL, 0666, -+ "vulcanpk"); -+ sc->sc_pkdev->si_drv1 = sc; -+#endif -+ } -+ -+ return (0); -+} -+ -+#ifdef CONFIG_OCF_RANDOMHARVEST -+static int -+hifn_read_random(void *arg, u_int32_t *buf, int len) -+{ -+ struct hifn_softc *sc = (struct hifn_softc *) arg; -+ u_int32_t sts; -+ int i, rc = 0; -+ -+ if (len <= 0) -+ return rc; -+ -+ if (sc->sc_flags & HIFN_IS_7811) { -+ /* ONLY VALID ON 7811!!!! */ -+ for (i = 0; i < 5; i++) { -+ sts = READ_REG_1(sc, HIFN_1_7811_RNGSTS); -+ if (sts & HIFN_7811_RNGSTS_UFL) { -+ device_printf(sc->sc_dev, -+ "RNG underflow: disabling\n"); -+ /* DAVIDM perhaps return -1 */ -+ break; -+ } -+ if ((sts & HIFN_7811_RNGSTS_RDY) == 0) -+ break; -+ -+ /* -+ * There are at least two words in the RNG FIFO -+ * at this point. -+ */ -+ if (rc < len) -+ buf[rc++] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); -+ if (rc < len) -+ buf[rc++] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); -+ } -+ } else -+ buf[rc++] = READ_REG_1(sc, HIFN_1_RNG_DATA); -+ -+ /* NB: discard first data read */ -+ if (sc->sc_rngfirst) { -+ sc->sc_rngfirst = 0; -+ rc = 0; -+ } -+ -+ return(rc); -+} -+#endif /* CONFIG_OCF_RANDOMHARVEST */ -+ -+static void -+hifn_puc_wait(struct hifn_softc *sc) -+{ -+ int i; -+ int reg = HIFN_0_PUCTRL; -+ -+ if (sc->sc_flags & HIFN_IS_7956) { -+ reg = HIFN_0_PUCTRL2; -+ } -+ -+ for (i = 5000; i > 0; i--) { -+ DELAY(1); -+ if (!(READ_REG_0(sc, reg) & HIFN_PUCTRL_RESET)) -+ break; -+ } -+ if (!i) -+ device_printf(sc->sc_dev, "proc unit did not reset(0x%x)\n", -+ READ_REG_0(sc, HIFN_0_PUCTRL)); -+} -+ -+/* -+ * Reset the processing unit. -+ */ -+static void -+hifn_reset_puc(struct hifn_softc *sc) -+{ -+ /* Reset processing unit */ -+ int reg = HIFN_0_PUCTRL; -+ -+ if (sc->sc_flags & HIFN_IS_7956) { -+ reg = HIFN_0_PUCTRL2; -+ } -+ WRITE_REG_0(sc, reg, HIFN_PUCTRL_DMAENA); -+ -+ hifn_puc_wait(sc); -+} -+ -+/* -+ * Set the Retry and TRDY registers; note that we set them to -+ * zero because the 7811 locks up when forced to retry (section -+ * 3.6 of "Specification Update SU-0014-04". Not clear if we -+ * should do this for all Hifn parts, but it doesn't seem to hurt. -+ */ -+static void -+hifn_set_retry(struct hifn_softc *sc) -+{ -+ DPRINTF("%s()\n", __FUNCTION__); -+ /* NB: RETRY only responds to 8-bit reads/writes */ -+ pci_write_config_byte(sc->sc_pcidev, HIFN_RETRY_TIMEOUT, 0); -+ pci_write_config_dword(sc->sc_pcidev, HIFN_TRDY_TIMEOUT, 0); -+ /* piggy back the cache line setting here */ -+ pci_write_config_byte(sc->sc_pcidev, PCI_CACHE_LINE_SIZE, hifn_cache_linesize); -+} -+ -+/* -+ * Resets the board. Values in the regesters are left as is -+ * from the reset (i.e. initial values are assigned elsewhere). -+ */ -+static void -+hifn_reset_board(struct hifn_softc *sc, int full) -+{ -+ u_int32_t reg; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ /* -+ * Set polling in the DMA configuration register to zero. 0x7 avoids -+ * resetting the board and zeros out the other fields. -+ */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | -+ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); -+ -+ /* -+ * Now that polling has been disabled, we have to wait 1 ms -+ * before resetting the board. -+ */ -+ DELAY(1000); -+ -+ /* Reset the DMA unit */ -+ if (full) { -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE); -+ DELAY(1000); -+ } else { -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, -+ HIFN_DMACNFG_MODE | HIFN_DMACNFG_MSTRESET); -+ hifn_reset_puc(sc); -+ } -+ -+ KASSERT(sc->sc_dma != NULL, ("hifn_reset_board: null DMA tag!")); -+ bzero(sc->sc_dma, sizeof(*sc->sc_dma)); -+ -+ /* Bring dma unit out of reset */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | -+ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); -+ -+ hifn_puc_wait(sc); -+ hifn_set_retry(sc); -+ -+ if (sc->sc_flags & HIFN_IS_7811) { -+ for (reg = 0; reg < 1000; reg++) { -+ if (READ_REG_1(sc, HIFN_1_7811_MIPSRST) & -+ HIFN_MIPSRST_CRAMINIT) -+ break; -+ DELAY(1000); -+ } -+ if (reg == 1000) -+ device_printf(sc->sc_dev, ": cram init timeout\n"); -+ } else { -+ /* set up DMA configuration register #2 */ -+ /* turn off all PK and BAR0 swaps */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG2, -+ (3 << HIFN_DMACNFG2_INIT_WRITE_BURST_SHIFT)| -+ (3 << HIFN_DMACNFG2_INIT_READ_BURST_SHIFT)| -+ (2 << HIFN_DMACNFG2_TGT_WRITE_BURST_SHIFT)| -+ (2 << HIFN_DMACNFG2_TGT_READ_BURST_SHIFT)); -+ } -+} -+ -+static u_int32_t -+hifn_next_signature(u_int32_t a, u_int cnt) -+{ -+ int i; -+ u_int32_t v; -+ -+ for (i = 0; i < cnt; i++) { -+ -+ /* get the parity */ -+ v = a & 0x80080125; -+ v ^= v >> 16; -+ v ^= v >> 8; -+ v ^= v >> 4; -+ v ^= v >> 2; -+ v ^= v >> 1; -+ -+ a = (v & 1) ^ (a << 1); -+ } -+ -+ return a; -+} -+ -+ -+/* -+ * Checks to see if crypto is already enabled. If crypto isn't enable, -+ * "hifn_enable_crypto" is called to enable it. The check is important, -+ * as enabling crypto twice will lock the board. -+ */ -+static int -+hifn_enable_crypto(struct hifn_softc *sc) -+{ -+ u_int32_t dmacfg, ramcfg, encl, addr, i; -+ char offtbl[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00 }; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ ramcfg = READ_REG_0(sc, HIFN_0_PUCNFG); -+ dmacfg = READ_REG_1(sc, HIFN_1_DMA_CNFG); -+ -+ /* -+ * The RAM config register's encrypt level bit needs to be set before -+ * every read performed on the encryption level register. -+ */ -+ WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); -+ -+ encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; -+ -+ /* -+ * Make sure we don't re-unlock. Two unlocks kills chip until the -+ * next reboot. -+ */ -+ if (encl == HIFN_PUSTAT_ENA_1 || encl == HIFN_PUSTAT_ENA_2) { -+#ifdef HIFN_DEBUG -+ if (hifn_debug) -+ device_printf(sc->sc_dev, -+ "Strong crypto already enabled!\n"); -+#endif -+ goto report; -+ } -+ -+ if (encl != 0 && encl != HIFN_PUSTAT_ENA_0) { -+#ifdef HIFN_DEBUG -+ if (hifn_debug) -+ device_printf(sc->sc_dev, -+ "Unknown encryption level 0x%x\n", encl); -+#endif -+ return 1; -+ } -+ -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_UNLOCK | -+ HIFN_DMACNFG_MSTRESET | HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); -+ DELAY(1000); -+ addr = READ_REG_1(sc, HIFN_UNLOCK_SECRET1); -+ DELAY(1000); -+ WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, 0); -+ DELAY(1000); -+ -+ for (i = 0; i <= 12; i++) { -+ addr = hifn_next_signature(addr, offtbl[i] + 0x101); -+ WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, addr); -+ -+ DELAY(1000); -+ } -+ -+ WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); -+ encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; -+ -+#ifdef HIFN_DEBUG -+ if (hifn_debug) { -+ if (encl != HIFN_PUSTAT_ENA_1 && encl != HIFN_PUSTAT_ENA_2) -+ device_printf(sc->sc_dev, "Engine is permanently " -+ "locked until next system reset!\n"); -+ else -+ device_printf(sc->sc_dev, "Engine enabled " -+ "successfully!\n"); -+ } -+#endif -+ -+report: -+ WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg); -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, dmacfg); -+ -+ switch (encl) { -+ case HIFN_PUSTAT_ENA_1: -+ case HIFN_PUSTAT_ENA_2: -+ break; -+ case HIFN_PUSTAT_ENA_0: -+ default: -+ device_printf(sc->sc_dev, "disabled\n"); -+ break; -+ } -+ -+ return 0; -+} -+ -+/* -+ * Give initial values to the registers listed in the "Register Space" -+ * section of the HIFN Software Development reference manual. -+ */ -+static void -+hifn_init_pci_registers(struct hifn_softc *sc) -+{ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ /* write fixed values needed by the Initialization registers */ -+ WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA); -+ WRITE_REG_0(sc, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD); -+ WRITE_REG_0(sc, HIFN_0_PUIER, HIFN_PUIER_DSTOVER); -+ -+ /* write all 4 ring address registers */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CRAR, sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, cmdr[0])); -+ WRITE_REG_1(sc, HIFN_1_DMA_SRAR, sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, srcr[0])); -+ WRITE_REG_1(sc, HIFN_1_DMA_DRAR, sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, dstr[0])); -+ WRITE_REG_1(sc, HIFN_1_DMA_RRAR, sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, resr[0])); -+ -+ DELAY(2000); -+ -+ /* write status register */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CSR, -+ HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS | -+ HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS | -+ HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST | -+ HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER | -+ HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST | -+ HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER | -+ HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST | -+ HIFN_DMACSR_S_WAIT | -+ HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST | -+ HIFN_DMACSR_C_WAIT | -+ HIFN_DMACSR_ENGINE | -+ ((sc->sc_flags & HIFN_HAS_PUBLIC) ? -+ HIFN_DMACSR_PUBDONE : 0) | -+ ((sc->sc_flags & HIFN_IS_7811) ? -+ HIFN_DMACSR_ILLW | HIFN_DMACSR_ILLR : 0)); -+ -+ sc->sc_d_busy = sc->sc_r_busy = sc->sc_s_busy = sc->sc_c_busy = 0; -+ sc->sc_dmaier |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT | -+ HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER | -+ HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT | -+ ((sc->sc_flags & HIFN_IS_7811) ? -+ HIFN_DMAIER_ILLW | HIFN_DMAIER_ILLR : 0); -+ sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; -+ WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); -+ -+ -+ if (sc->sc_flags & HIFN_IS_7956) { -+ u_int32_t pll; -+ -+ WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING | -+ HIFN_PUCNFG_TCALLPHASES | -+ HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32); -+ -+ /* turn off the clocks and insure bypass is set */ -+ pll = READ_REG_1(sc, HIFN_1_PLL); -+ pll = (pll &~ (HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL)) -+ | HIFN_PLL_BP | HIFN_PLL_MBSET; -+ WRITE_REG_1(sc, HIFN_1_PLL, pll); -+ DELAY(10*1000); /* 10ms */ -+ -+ /* change configuration */ -+ pll = (pll &~ HIFN_PLL_CONFIG) | sc->sc_pllconfig; -+ WRITE_REG_1(sc, HIFN_1_PLL, pll); -+ DELAY(10*1000); /* 10ms */ -+ -+ /* disable bypass */ -+ pll &= ~HIFN_PLL_BP; -+ WRITE_REG_1(sc, HIFN_1_PLL, pll); -+ /* enable clocks with new configuration */ -+ pll |= HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL; -+ WRITE_REG_1(sc, HIFN_1_PLL, pll); -+ } else { -+ WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING | -+ HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES | -+ HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 | -+ (sc->sc_drammodel ? HIFN_PUCNFG_DRAM : HIFN_PUCNFG_SRAM)); -+ } -+ -+ WRITE_REG_0(sc, HIFN_0_PUISR, HIFN_PUISR_DSTOVER); -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | -+ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST | -+ ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) | -+ ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL)); -+} -+ -+/* -+ * The maximum number of sessions supported by the card -+ * is dependent on the amount of context ram, which -+ * encryption algorithms are enabled, and how compression -+ * is configured. This should be configured before this -+ * routine is called. -+ */ -+static void -+hifn_sessions(struct hifn_softc *sc) -+{ -+ u_int32_t pucnfg; -+ int ctxsize; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ pucnfg = READ_REG_0(sc, HIFN_0_PUCNFG); -+ -+ if (pucnfg & HIFN_PUCNFG_COMPSING) { -+ if (pucnfg & HIFN_PUCNFG_ENCCNFG) -+ ctxsize = 128; -+ else -+ ctxsize = 512; -+ /* -+ * 7955/7956 has internal context memory of 32K -+ */ -+ if (sc->sc_flags & HIFN_IS_7956) -+ sc->sc_maxses = 32768 / ctxsize; -+ else -+ sc->sc_maxses = 1 + -+ ((sc->sc_ramsize - 32768) / ctxsize); -+ } else -+ sc->sc_maxses = sc->sc_ramsize / 16384; -+ -+ if (sc->sc_maxses > 2048) -+ sc->sc_maxses = 2048; -+} -+ -+/* -+ * Determine ram type (sram or dram). Board should be just out of a reset -+ * state when this is called. -+ */ -+static int -+hifn_ramtype(struct hifn_softc *sc) -+{ -+ u_int8_t data[8], dataexpect[8]; -+ int i; -+ -+ for (i = 0; i < sizeof(data); i++) -+ data[i] = dataexpect[i] = 0x55; -+ if (hifn_writeramaddr(sc, 0, data)) -+ return (-1); -+ if (hifn_readramaddr(sc, 0, data)) -+ return (-1); -+ if (bcmp(data, dataexpect, sizeof(data)) != 0) { -+ sc->sc_drammodel = 1; -+ return (0); -+ } -+ -+ for (i = 0; i < sizeof(data); i++) -+ data[i] = dataexpect[i] = 0xaa; -+ if (hifn_writeramaddr(sc, 0, data)) -+ return (-1); -+ if (hifn_readramaddr(sc, 0, data)) -+ return (-1); -+ if (bcmp(data, dataexpect, sizeof(data)) != 0) { -+ sc->sc_drammodel = 1; -+ return (0); -+ } -+ -+ return (0); -+} -+ -+#define HIFN_SRAM_MAX (32 << 20) -+#define HIFN_SRAM_STEP_SIZE 16384 -+#define HIFN_SRAM_GRANULARITY (HIFN_SRAM_MAX / HIFN_SRAM_STEP_SIZE) -+ -+static int -+hifn_sramsize(struct hifn_softc *sc) -+{ -+ u_int32_t a; -+ u_int8_t data[8]; -+ u_int8_t dataexpect[sizeof(data)]; -+ int32_t i; -+ -+ for (i = 0; i < sizeof(data); i++) -+ data[i] = dataexpect[i] = i ^ 0x5a; -+ -+ for (i = HIFN_SRAM_GRANULARITY - 1; i >= 0; i--) { -+ a = i * HIFN_SRAM_STEP_SIZE; -+ bcopy(&i, data, sizeof(i)); -+ hifn_writeramaddr(sc, a, data); -+ } -+ -+ for (i = 0; i < HIFN_SRAM_GRANULARITY; i++) { -+ a = i * HIFN_SRAM_STEP_SIZE; -+ bcopy(&i, dataexpect, sizeof(i)); -+ if (hifn_readramaddr(sc, a, data) < 0) -+ return (0); -+ if (bcmp(data, dataexpect, sizeof(data)) != 0) -+ return (0); -+ sc->sc_ramsize = a + HIFN_SRAM_STEP_SIZE; -+ } -+ -+ return (0); -+} -+ -+/* -+ * XXX For dram boards, one should really try all of the -+ * HIFN_PUCNFG_DSZ_*'s. This just assumes that PUCNFG -+ * is already set up correctly. -+ */ -+static int -+hifn_dramsize(struct hifn_softc *sc) -+{ -+ u_int32_t cnfg; -+ -+ if (sc->sc_flags & HIFN_IS_7956) { -+ /* -+ * 7955/7956 have a fixed internal ram of only 32K. -+ */ -+ sc->sc_ramsize = 32768; -+ } else { -+ cnfg = READ_REG_0(sc, HIFN_0_PUCNFG) & -+ HIFN_PUCNFG_DRAMMASK; -+ sc->sc_ramsize = 1 << ((cnfg >> 13) + 18); -+ } -+ return (0); -+} -+ -+static void -+hifn_alloc_slot(struct hifn_softc *sc, int *cmdp, int *srcp, int *dstp, int *resp) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (dma->cmdi == HIFN_D_CMD_RSIZE) { -+ dma->cmdi = 0; -+ dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); -+ wmb(); -+ dma->cmdr[HIFN_D_CMD_RSIZE].l |= htole32(HIFN_D_VALID); -+ HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, -+ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); -+ } -+ *cmdp = dma->cmdi++; -+ dma->cmdk = dma->cmdi; -+ -+ if (dma->srci == HIFN_D_SRC_RSIZE) { -+ dma->srci = 0; -+ dma->srcr[HIFN_D_SRC_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); -+ wmb(); -+ dma->srcr[HIFN_D_SRC_RSIZE].l |= htole32(HIFN_D_VALID); -+ HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, -+ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); -+ } -+ *srcp = dma->srci++; -+ dma->srck = dma->srci; -+ -+ if (dma->dsti == HIFN_D_DST_RSIZE) { -+ dma->dsti = 0; -+ dma->dstr[HIFN_D_DST_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); -+ wmb(); -+ dma->dstr[HIFN_D_DST_RSIZE].l |= htole32(HIFN_D_VALID); -+ HIFN_DSTR_SYNC(sc, HIFN_D_DST_RSIZE, -+ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); -+ } -+ *dstp = dma->dsti++; -+ dma->dstk = dma->dsti; -+ -+ if (dma->resi == HIFN_D_RES_RSIZE) { -+ dma->resi = 0; -+ dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); -+ wmb(); -+ dma->resr[HIFN_D_RES_RSIZE].l |= htole32(HIFN_D_VALID); -+ HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, -+ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); -+ } -+ *resp = dma->resi++; -+ dma->resk = dma->resi; -+} -+ -+static int -+hifn_writeramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ hifn_base_command_t wc; -+ const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; -+ int r, cmdi, resi, srci, dsti; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ wc.masks = htole16(3 << 13); -+ wc.session_num = htole16(addr >> 14); -+ wc.total_source_count = htole16(8); -+ wc.total_dest_count = htole16(addr & 0x3fff); -+ -+ hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); -+ -+ WRITE_REG_1(sc, HIFN_1_DMA_CSR, -+ HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | -+ HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); -+ -+ /* build write command */ -+ bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); -+ *(hifn_base_command_t *)dma->command_bufs[cmdi] = wc; -+ bcopy(data, &dma->test_src, sizeof(dma->test_src)); -+ -+ dma->srcr[srci].p = htole32(sc->sc_dma_physaddr -+ + offsetof(struct hifn_dma, test_src)); -+ dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr -+ + offsetof(struct hifn_dma, test_dst)); -+ -+ dma->cmdr[cmdi].l = htole32(16 | masks); -+ dma->srcr[srci].l = htole32(8 | masks); -+ dma->dstr[dsti].l = htole32(4 | masks); -+ dma->resr[resi].l = htole32(4 | masks); -+ -+ for (r = 10000; r >= 0; r--) { -+ DELAY(10); -+ if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) -+ break; -+ } -+ if (r == 0) { -+ device_printf(sc->sc_dev, "writeramaddr -- " -+ "result[%d](addr %d) still valid\n", resi, addr); -+ r = -1; -+ return (-1); -+ } else -+ r = 0; -+ -+ WRITE_REG_1(sc, HIFN_1_DMA_CSR, -+ HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | -+ HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); -+ -+ return (r); -+} -+ -+static int -+hifn_readramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ hifn_base_command_t rc; -+ const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; -+ int r, cmdi, srci, dsti, resi; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ rc.masks = htole16(2 << 13); -+ rc.session_num = htole16(addr >> 14); -+ rc.total_source_count = htole16(addr & 0x3fff); -+ rc.total_dest_count = htole16(8); -+ -+ hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); -+ -+ WRITE_REG_1(sc, HIFN_1_DMA_CSR, -+ HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | -+ HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); -+ -+ bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); -+ *(hifn_base_command_t *)dma->command_bufs[cmdi] = rc; -+ -+ dma->srcr[srci].p = htole32(sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, test_src)); -+ dma->test_src = 0; -+ dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, test_dst)); -+ dma->test_dst = 0; -+ dma->cmdr[cmdi].l = htole32(8 | masks); -+ dma->srcr[srci].l = htole32(8 | masks); -+ dma->dstr[dsti].l = htole32(8 | masks); -+ dma->resr[resi].l = htole32(HIFN_MAX_RESULT | masks); -+ -+ for (r = 10000; r >= 0; r--) { -+ DELAY(10); -+ if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) -+ break; -+ } -+ if (r == 0) { -+ device_printf(sc->sc_dev, "readramaddr -- " -+ "result[%d](addr %d) still valid\n", resi, addr); -+ r = -1; -+ } else { -+ r = 0; -+ bcopy(&dma->test_dst, data, sizeof(dma->test_dst)); -+ } -+ -+ WRITE_REG_1(sc, HIFN_1_DMA_CSR, -+ HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | -+ HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); -+ -+ return (r); -+} -+ -+/* -+ * Initialize the descriptor rings. -+ */ -+static void -+hifn_init_dma(struct hifn_softc *sc) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ hifn_set_retry(sc); -+ -+ /* initialize static pointer values */ -+ for (i = 0; i < HIFN_D_CMD_RSIZE; i++) -+ dma->cmdr[i].p = htole32(sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, command_bufs[i][0])); -+ for (i = 0; i < HIFN_D_RES_RSIZE; i++) -+ dma->resr[i].p = htole32(sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, result_bufs[i][0])); -+ -+ dma->cmdr[HIFN_D_CMD_RSIZE].p = -+ htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, cmdr[0])); -+ dma->srcr[HIFN_D_SRC_RSIZE].p = -+ htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, srcr[0])); -+ dma->dstr[HIFN_D_DST_RSIZE].p = -+ htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, dstr[0])); -+ dma->resr[HIFN_D_RES_RSIZE].p = -+ htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, resr[0])); -+ -+ dma->cmdu = dma->srcu = dma->dstu = dma->resu = 0; -+ dma->cmdi = dma->srci = dma->dsti = dma->resi = 0; -+ dma->cmdk = dma->srck = dma->dstk = dma->resk = 0; -+} -+ -+/* -+ * Writes out the raw command buffer space. Returns the -+ * command buffer size. -+ */ -+static u_int -+hifn_write_command(struct hifn_command *cmd, u_int8_t *buf) -+{ -+ struct hifn_softc *sc = NULL; -+ u_int8_t *buf_pos; -+ hifn_base_command_t *base_cmd; -+ hifn_mac_command_t *mac_cmd; -+ hifn_crypt_command_t *cry_cmd; -+ int using_mac, using_crypt, len, ivlen; -+ u_int32_t dlen, slen; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ buf_pos = buf; -+ using_mac = cmd->base_masks & HIFN_BASE_CMD_MAC; -+ using_crypt = cmd->base_masks & HIFN_BASE_CMD_CRYPT; -+ -+ base_cmd = (hifn_base_command_t *)buf_pos; -+ base_cmd->masks = htole16(cmd->base_masks); -+ slen = cmd->src_mapsize; -+ if (cmd->sloplen) -+ dlen = cmd->dst_mapsize - cmd->sloplen + sizeof(u_int32_t); -+ else -+ dlen = cmd->dst_mapsize; -+ base_cmd->total_source_count = htole16(slen & HIFN_BASE_CMD_LENMASK_LO); -+ base_cmd->total_dest_count = htole16(dlen & HIFN_BASE_CMD_LENMASK_LO); -+ dlen >>= 16; -+ slen >>= 16; -+ base_cmd->session_num = htole16( -+ ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) | -+ ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M)); -+ buf_pos += sizeof(hifn_base_command_t); -+ -+ if (using_mac) { -+ mac_cmd = (hifn_mac_command_t *)buf_pos; -+ dlen = cmd->maccrd->crd_len; -+ mac_cmd->source_count = htole16(dlen & 0xffff); -+ dlen >>= 16; -+ mac_cmd->masks = htole16(cmd->mac_masks | -+ ((dlen << HIFN_MAC_CMD_SRCLEN_S) & HIFN_MAC_CMD_SRCLEN_M)); -+ mac_cmd->header_skip = htole16(cmd->maccrd->crd_skip); -+ mac_cmd->reserved = 0; -+ buf_pos += sizeof(hifn_mac_command_t); -+ } -+ -+ if (using_crypt) { -+ cry_cmd = (hifn_crypt_command_t *)buf_pos; -+ dlen = cmd->enccrd->crd_len; -+ cry_cmd->source_count = htole16(dlen & 0xffff); -+ dlen >>= 16; -+ cry_cmd->masks = htole16(cmd->cry_masks | -+ ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) & HIFN_CRYPT_CMD_SRCLEN_M)); -+ cry_cmd->header_skip = htole16(cmd->enccrd->crd_skip); -+ cry_cmd->reserved = 0; -+ buf_pos += sizeof(hifn_crypt_command_t); -+ } -+ -+ if (using_mac && cmd->mac_masks & HIFN_MAC_CMD_NEW_KEY) { -+ bcopy(cmd->mac, buf_pos, HIFN_MAC_KEY_LENGTH); -+ buf_pos += HIFN_MAC_KEY_LENGTH; -+ } -+ -+ if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_KEY) { -+ switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) { -+ case HIFN_CRYPT_CMD_ALG_3DES: -+ bcopy(cmd->ck, buf_pos, HIFN_3DES_KEY_LENGTH); -+ buf_pos += HIFN_3DES_KEY_LENGTH; -+ break; -+ case HIFN_CRYPT_CMD_ALG_DES: -+ bcopy(cmd->ck, buf_pos, HIFN_DES_KEY_LENGTH); -+ buf_pos += HIFN_DES_KEY_LENGTH; -+ break; -+ case HIFN_CRYPT_CMD_ALG_RC4: -+ len = 256; -+ do { -+ int clen; -+ -+ clen = MIN(cmd->cklen, len); -+ bcopy(cmd->ck, buf_pos, clen); -+ len -= clen; -+ buf_pos += clen; -+ } while (len > 0); -+ bzero(buf_pos, 4); -+ buf_pos += 4; -+ break; -+ case HIFN_CRYPT_CMD_ALG_AES: -+ /* -+ * AES keys are variable 128, 192 and -+ * 256 bits (16, 24 and 32 bytes). -+ */ -+ bcopy(cmd->ck, buf_pos, cmd->cklen); -+ buf_pos += cmd->cklen; -+ break; -+ } -+ } -+ -+ if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_IV) { -+ switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) { -+ case HIFN_CRYPT_CMD_ALG_AES: -+ ivlen = HIFN_AES_IV_LENGTH; -+ break; -+ default: -+ ivlen = HIFN_IV_LENGTH; -+ break; -+ } -+ bcopy(cmd->iv, buf_pos, ivlen); -+ buf_pos += ivlen; -+ } -+ -+ if ((cmd->base_masks & (HIFN_BASE_CMD_MAC|HIFN_BASE_CMD_CRYPT)) == 0) { -+ bzero(buf_pos, 8); -+ buf_pos += 8; -+ } -+ -+ return (buf_pos - buf); -+} -+ -+static int -+hifn_dmamap_aligned(struct hifn_operand *op) -+{ -+ struct hifn_softc *sc = NULL; -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ for (i = 0; i < op->nsegs; i++) { -+ if (op->segs[i].ds_addr & 3) -+ return (0); -+ if ((i != (op->nsegs - 1)) && (op->segs[i].ds_len & 3)) -+ return (0); -+ } -+ return (1); -+} -+ -+static __inline int -+hifn_dmamap_dstwrap(struct hifn_softc *sc, int idx) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ -+ if (++idx == HIFN_D_DST_RSIZE) { -+ dma->dstr[idx].l = htole32(HIFN_D_VALID | HIFN_D_JUMP | -+ HIFN_D_MASKDONEIRQ); -+ HIFN_DSTR_SYNC(sc, idx, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ idx = 0; -+ } -+ return (idx); -+} -+ -+static int -+hifn_dmamap_load_dst(struct hifn_softc *sc, struct hifn_command *cmd) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ struct hifn_operand *dst = &cmd->dst; -+ u_int32_t p, l; -+ int idx, used = 0, i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ idx = dma->dsti; -+ for (i = 0; i < dst->nsegs - 1; i++) { -+ dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); -+ dma->dstr[idx].l = htole32(HIFN_D_MASKDONEIRQ | dst->segs[i].ds_len); -+ wmb(); -+ dma->dstr[idx].l |= htole32(HIFN_D_VALID); -+ HIFN_DSTR_SYNC(sc, idx, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ used++; -+ -+ idx = hifn_dmamap_dstwrap(sc, idx); -+ } -+ -+ if (cmd->sloplen == 0) { -+ p = dst->segs[i].ds_addr; -+ l = HIFN_D_MASKDONEIRQ | HIFN_D_LAST | -+ dst->segs[i].ds_len; -+ } else { -+ p = sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, slop[cmd->slopidx]); -+ l = HIFN_D_MASKDONEIRQ | HIFN_D_LAST | -+ sizeof(u_int32_t); -+ -+ if ((dst->segs[i].ds_len - cmd->sloplen) != 0) { -+ dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); -+ dma->dstr[idx].l = htole32(HIFN_D_MASKDONEIRQ | -+ (dst->segs[i].ds_len - cmd->sloplen)); -+ wmb(); -+ dma->dstr[idx].l |= htole32(HIFN_D_VALID); -+ HIFN_DSTR_SYNC(sc, idx, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ used++; -+ -+ idx = hifn_dmamap_dstwrap(sc, idx); -+ } -+ } -+ dma->dstr[idx].p = htole32(p); -+ dma->dstr[idx].l = htole32(l); -+ wmb(); -+ dma->dstr[idx].l |= htole32(HIFN_D_VALID); -+ HIFN_DSTR_SYNC(sc, idx, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ used++; -+ -+ idx = hifn_dmamap_dstwrap(sc, idx); -+ -+ dma->dsti = idx; -+ dma->dstu += used; -+ return (idx); -+} -+ -+static __inline int -+hifn_dmamap_srcwrap(struct hifn_softc *sc, int idx) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ -+ if (++idx == HIFN_D_SRC_RSIZE) { -+ dma->srcr[idx].l = htole32(HIFN_D_VALID | -+ HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); -+ HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, -+ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); -+ idx = 0; -+ } -+ return (idx); -+} -+ -+static int -+hifn_dmamap_load_src(struct hifn_softc *sc, struct hifn_command *cmd) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ struct hifn_operand *src = &cmd->src; -+ int idx, i; -+ u_int32_t last = 0; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ idx = dma->srci; -+ for (i = 0; i < src->nsegs; i++) { -+ if (i == src->nsegs - 1) -+ last = HIFN_D_LAST; -+ -+ dma->srcr[idx].p = htole32(src->segs[i].ds_addr); -+ dma->srcr[idx].l = htole32(src->segs[i].ds_len | -+ HIFN_D_MASKDONEIRQ | last); -+ wmb(); -+ dma->srcr[idx].l |= htole32(HIFN_D_VALID); -+ HIFN_SRCR_SYNC(sc, idx, -+ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); -+ -+ idx = hifn_dmamap_srcwrap(sc, idx); -+ } -+ dma->srci = idx; -+ dma->srcu += src->nsegs; -+ return (idx); -+} -+ -+ -+static int -+hifn_crypto( -+ struct hifn_softc *sc, -+ struct hifn_command *cmd, -+ struct cryptop *crp, -+ int hint) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ u_int32_t cmdlen, csr; -+ int cmdi, resi, err = 0; -+ unsigned long l_flags; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ /* -+ * need 1 cmd, and 1 res -+ * -+ * NB: check this first since it's easy. -+ */ -+ HIFN_LOCK(sc); -+ if ((dma->cmdu + 1) > HIFN_D_CMD_RSIZE || -+ (dma->resu + 1) > HIFN_D_RES_RSIZE) { -+#ifdef HIFN_DEBUG -+ if (hifn_debug) { -+ device_printf(sc->sc_dev, -+ "cmd/result exhaustion, cmdu %u resu %u\n", -+ dma->cmdu, dma->resu); -+ } -+#endif -+ hifnstats.hst_nomem_cr++; -+ sc->sc_needwakeup |= CRYPTO_SYMQ; -+ HIFN_UNLOCK(sc); -+ return (ERESTART); -+ } -+ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ if (pci_map_skb(sc, &cmd->src, cmd->src_skb)) { -+ hifnstats.hst_nomem_load++; -+ err = ENOMEM; -+ goto err_srcmap1; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ if (pci_map_uio(sc, &cmd->src, cmd->src_io)) { -+ hifnstats.hst_nomem_load++; -+ err = ENOMEM; -+ goto err_srcmap1; -+ } -+ } else { -+ if (pci_map_buf(sc, &cmd->src, cmd->src_buf, crp->crp_ilen)) { -+ hifnstats.hst_nomem_load++; -+ err = ENOMEM; -+ goto err_srcmap1; -+ } -+ } -+ -+ if (hifn_dmamap_aligned(&cmd->src)) { -+ cmd->sloplen = cmd->src_mapsize & 3; -+ cmd->dst = cmd->src; -+ } else { -+ if (crp->crp_flags & CRYPTO_F_IOV) { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ err = EINVAL; -+ goto err_srcmap; -+ } else if (crp->crp_flags & CRYPTO_F_SKBUF) { -+#ifdef NOTYET -+ int totlen, len; -+ struct mbuf *m, *m0, *mlast; -+ -+ KASSERT(cmd->dst_m == cmd->src_m, -+ ("hifn_crypto: dst_m initialized improperly")); -+ hifnstats.hst_unaligned++; -+ /* -+ * Source is not aligned on a longword boundary. -+ * Copy the data to insure alignment. If we fail -+ * to allocate mbufs or clusters while doing this -+ * we return ERESTART so the operation is requeued -+ * at the crypto later, but only if there are -+ * ops already posted to the hardware; otherwise we -+ * have no guarantee that we'll be re-entered. -+ */ -+ totlen = cmd->src_mapsize; -+ if (cmd->src_m->m_flags & M_PKTHDR) { -+ len = MHLEN; -+ MGETHDR(m0, M_DONTWAIT, MT_DATA); -+ if (m0 && !m_dup_pkthdr(m0, cmd->src_m, M_DONTWAIT)) { -+ m_free(m0); -+ m0 = NULL; -+ } -+ } else { -+ len = MLEN; -+ MGET(m0, M_DONTWAIT, MT_DATA); -+ } -+ if (m0 == NULL) { -+ hifnstats.hst_nomem_mbuf++; -+ err = dma->cmdu ? ERESTART : ENOMEM; -+ goto err_srcmap; -+ } -+ if (totlen >= MINCLSIZE) { -+ MCLGET(m0, M_DONTWAIT); -+ if ((m0->m_flags & M_EXT) == 0) { -+ hifnstats.hst_nomem_mcl++; -+ err = dma->cmdu ? ERESTART : ENOMEM; -+ m_freem(m0); -+ goto err_srcmap; -+ } -+ len = MCLBYTES; -+ } -+ totlen -= len; -+ m0->m_pkthdr.len = m0->m_len = len; -+ mlast = m0; -+ -+ while (totlen > 0) { -+ MGET(m, M_DONTWAIT, MT_DATA); -+ if (m == NULL) { -+ hifnstats.hst_nomem_mbuf++; -+ err = dma->cmdu ? ERESTART : ENOMEM; -+ m_freem(m0); -+ goto err_srcmap; -+ } -+ len = MLEN; -+ if (totlen >= MINCLSIZE) { -+ MCLGET(m, M_DONTWAIT); -+ if ((m->m_flags & M_EXT) == 0) { -+ hifnstats.hst_nomem_mcl++; -+ err = dma->cmdu ? ERESTART : ENOMEM; -+ mlast->m_next = m; -+ m_freem(m0); -+ goto err_srcmap; -+ } -+ len = MCLBYTES; -+ } -+ -+ m->m_len = len; -+ m0->m_pkthdr.len += len; -+ totlen -= len; -+ -+ mlast->m_next = m; -+ mlast = m; -+ } -+ cmd->dst_m = m0; -+#else -+ device_printf(sc->sc_dev, -+ "%s,%d: CRYPTO_F_SKBUF unaligned not implemented\n", -+ __FILE__, __LINE__); -+ err = EINVAL; -+ goto err_srcmap; -+#endif -+ } else { -+ device_printf(sc->sc_dev, -+ "%s,%d: unaligned contig buffers not implemented\n", -+ __FILE__, __LINE__); -+ err = EINVAL; -+ goto err_srcmap; -+ } -+ } -+ -+ if (cmd->dst_map == NULL) { -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ if (pci_map_skb(sc, &cmd->dst, cmd->dst_skb)) { -+ hifnstats.hst_nomem_map++; -+ err = ENOMEM; -+ goto err_dstmap1; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ if (pci_map_uio(sc, &cmd->dst, cmd->dst_io)) { -+ hifnstats.hst_nomem_load++; -+ err = ENOMEM; -+ goto err_dstmap1; -+ } -+ } else { -+ if (pci_map_buf(sc, &cmd->dst, cmd->dst_buf, crp->crp_ilen)) { -+ hifnstats.hst_nomem_load++; -+ err = ENOMEM; -+ goto err_dstmap1; -+ } -+ } -+ } -+ -+#ifdef HIFN_DEBUG -+ if (hifn_debug) { -+ device_printf(sc->sc_dev, -+ "Entering cmd: stat %8x ien %8x u %d/%d/%d/%d n %d/%d\n", -+ READ_REG_1(sc, HIFN_1_DMA_CSR), -+ READ_REG_1(sc, HIFN_1_DMA_IER), -+ dma->cmdu, dma->srcu, dma->dstu, dma->resu, -+ cmd->src_nsegs, cmd->dst_nsegs); -+ } -+#endif -+ -+#if 0 -+ if (cmd->src_map == cmd->dst_map) { -+ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, -+ BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); -+ } else { -+ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, -+ BUS_DMASYNC_PREWRITE); -+ bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, -+ BUS_DMASYNC_PREREAD); -+ } -+#endif -+ -+ /* -+ * need N src, and N dst -+ */ -+ if ((dma->srcu + cmd->src_nsegs) > HIFN_D_SRC_RSIZE || -+ (dma->dstu + cmd->dst_nsegs + 1) > HIFN_D_DST_RSIZE) { -+#ifdef HIFN_DEBUG -+ if (hifn_debug) { -+ device_printf(sc->sc_dev, -+ "src/dst exhaustion, srcu %u+%u dstu %u+%u\n", -+ dma->srcu, cmd->src_nsegs, -+ dma->dstu, cmd->dst_nsegs); -+ } -+#endif -+ hifnstats.hst_nomem_sd++; -+ err = ERESTART; -+ goto err_dstmap; -+ } -+ -+ if (dma->cmdi == HIFN_D_CMD_RSIZE) { -+ dma->cmdi = 0; -+ dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); -+ wmb(); -+ dma->cmdr[HIFN_D_CMD_RSIZE].l |= htole32(HIFN_D_VALID); -+ HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, -+ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); -+ } -+ cmdi = dma->cmdi++; -+ cmdlen = hifn_write_command(cmd, dma->command_bufs[cmdi]); -+ HIFN_CMD_SYNC(sc, cmdi, BUS_DMASYNC_PREWRITE); -+ -+ /* .p for command/result already set */ -+ dma->cmdr[cmdi].l = htole32(cmdlen | HIFN_D_LAST | -+ HIFN_D_MASKDONEIRQ); -+ wmb(); -+ dma->cmdr[cmdi].l |= htole32(HIFN_D_VALID); -+ HIFN_CMDR_SYNC(sc, cmdi, -+ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); -+ dma->cmdu++; -+ -+ /* -+ * We don't worry about missing an interrupt (which a "command wait" -+ * interrupt salvages us from), unless there is more than one command -+ * in the queue. -+ */ -+ if (dma->cmdu > 1) { -+ sc->sc_dmaier |= HIFN_DMAIER_C_WAIT; -+ WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); -+ } -+ -+ hifnstats.hst_ipackets++; -+ hifnstats.hst_ibytes += cmd->src_mapsize; -+ -+ hifn_dmamap_load_src(sc, cmd); -+ -+ /* -+ * Unlike other descriptors, we don't mask done interrupt from -+ * result descriptor. -+ */ -+#ifdef HIFN_DEBUG -+ if (hifn_debug) -+ device_printf(sc->sc_dev, "load res\n"); -+#endif -+ if (dma->resi == HIFN_D_RES_RSIZE) { -+ dma->resi = 0; -+ dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); -+ wmb(); -+ dma->resr[HIFN_D_RES_RSIZE].l |= htole32(HIFN_D_VALID); -+ HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ } -+ resi = dma->resi++; -+ KASSERT(dma->hifn_commands[resi] == NULL, -+ ("hifn_crypto: command slot %u busy", resi)); -+ dma->hifn_commands[resi] = cmd; -+ HIFN_RES_SYNC(sc, resi, BUS_DMASYNC_PREREAD); -+ if ((hint & CRYPTO_HINT_MORE) && sc->sc_curbatch < hifn_maxbatch) { -+ dma->resr[resi].l = htole32(HIFN_MAX_RESULT | -+ HIFN_D_LAST | HIFN_D_MASKDONEIRQ); -+ wmb(); -+ dma->resr[resi].l |= htole32(HIFN_D_VALID); -+ sc->sc_curbatch++; -+ if (sc->sc_curbatch > hifnstats.hst_maxbatch) -+ hifnstats.hst_maxbatch = sc->sc_curbatch; -+ hifnstats.hst_totbatch++; -+ } else { -+ dma->resr[resi].l = htole32(HIFN_MAX_RESULT | HIFN_D_LAST); -+ wmb(); -+ dma->resr[resi].l |= htole32(HIFN_D_VALID); -+ sc->sc_curbatch = 0; -+ } -+ HIFN_RESR_SYNC(sc, resi, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ dma->resu++; -+ -+ if (cmd->sloplen) -+ cmd->slopidx = resi; -+ -+ hifn_dmamap_load_dst(sc, cmd); -+ -+ csr = 0; -+ if (sc->sc_c_busy == 0) { -+ csr |= HIFN_DMACSR_C_CTRL_ENA; -+ sc->sc_c_busy = 1; -+ } -+ if (sc->sc_s_busy == 0) { -+ csr |= HIFN_DMACSR_S_CTRL_ENA; -+ sc->sc_s_busy = 1; -+ } -+ if (sc->sc_r_busy == 0) { -+ csr |= HIFN_DMACSR_R_CTRL_ENA; -+ sc->sc_r_busy = 1; -+ } -+ if (sc->sc_d_busy == 0) { -+ csr |= HIFN_DMACSR_D_CTRL_ENA; -+ sc->sc_d_busy = 1; -+ } -+ if (csr) -+ WRITE_REG_1(sc, HIFN_1_DMA_CSR, csr); -+ -+#ifdef HIFN_DEBUG -+ if (hifn_debug) { -+ device_printf(sc->sc_dev, "command: stat %8x ier %8x\n", -+ READ_REG_1(sc, HIFN_1_DMA_CSR), -+ READ_REG_1(sc, HIFN_1_DMA_IER)); -+ } -+#endif -+ -+ sc->sc_active = 5; -+ HIFN_UNLOCK(sc); -+ KASSERT(err == 0, ("hifn_crypto: success with error %u", err)); -+ return (err); /* success */ -+ -+err_dstmap: -+ if (cmd->src_map != cmd->dst_map) -+ pci_unmap_buf(sc, &cmd->dst); -+err_dstmap1: -+err_srcmap: -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ if (cmd->src_skb != cmd->dst_skb) -+#ifdef NOTYET -+ m_freem(cmd->dst_m); -+#else -+ device_printf(sc->sc_dev, -+ "%s,%d: CRYPTO_F_SKBUF src != dst not implemented\n", -+ __FILE__, __LINE__); -+#endif -+ } -+ pci_unmap_buf(sc, &cmd->src); -+err_srcmap1: -+ HIFN_UNLOCK(sc); -+ return (err); -+} -+ -+static void -+hifn_tick(unsigned long arg) -+{ -+ struct hifn_softc *sc; -+ unsigned long l_flags; -+ -+ if (arg >= HIFN_MAX_CHIPS) -+ return; -+ sc = hifn_chip_idx[arg]; -+ if (!sc) -+ return; -+ -+ HIFN_LOCK(sc); -+ if (sc->sc_active == 0) { -+ struct hifn_dma *dma = sc->sc_dma; -+ u_int32_t r = 0; -+ -+ if (dma->cmdu == 0 && sc->sc_c_busy) { -+ sc->sc_c_busy = 0; -+ r |= HIFN_DMACSR_C_CTRL_DIS; -+ } -+ if (dma->srcu == 0 && sc->sc_s_busy) { -+ sc->sc_s_busy = 0; -+ r |= HIFN_DMACSR_S_CTRL_DIS; -+ } -+ if (dma->dstu == 0 && sc->sc_d_busy) { -+ sc->sc_d_busy = 0; -+ r |= HIFN_DMACSR_D_CTRL_DIS; -+ } -+ if (dma->resu == 0 && sc->sc_r_busy) { -+ sc->sc_r_busy = 0; -+ r |= HIFN_DMACSR_R_CTRL_DIS; -+ } -+ if (r) -+ WRITE_REG_1(sc, HIFN_1_DMA_CSR, r); -+ } else -+ sc->sc_active--; -+ HIFN_UNLOCK(sc); -+ mod_timer(&sc->sc_tickto, jiffies + HZ); -+} -+ -+static irqreturn_t -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) -+hifn_intr(int irq, void *arg) -+#else -+hifn_intr(int irq, void *arg, struct pt_regs *regs) -+#endif -+{ -+ struct hifn_softc *sc = arg; -+ struct hifn_dma *dma; -+ u_int32_t dmacsr, restart; -+ int i, u; -+ unsigned long l_flags; -+ -+ dmacsr = READ_REG_1(sc, HIFN_1_DMA_CSR); -+ -+ /* Nothing in the DMA unit interrupted */ -+ if ((dmacsr & sc->sc_dmaier) == 0) -+ return IRQ_NONE; -+ -+ HIFN_LOCK(sc); -+ -+ dma = sc->sc_dma; -+ -+#ifdef HIFN_DEBUG -+ if (hifn_debug) { -+ device_printf(sc->sc_dev, -+ "irq: stat %08x ien %08x damier %08x i %d/%d/%d/%d k %d/%d/%d/%d u %d/%d/%d/%d\n", -+ dmacsr, READ_REG_1(sc, HIFN_1_DMA_IER), sc->sc_dmaier, -+ dma->cmdi, dma->srci, dma->dsti, dma->resi, -+ dma->cmdk, dma->srck, dma->dstk, dma->resk, -+ dma->cmdu, dma->srcu, dma->dstu, dma->resu); -+ } -+#endif -+ -+ WRITE_REG_1(sc, HIFN_1_DMA_CSR, dmacsr & sc->sc_dmaier); -+ -+ if ((sc->sc_flags & HIFN_HAS_PUBLIC) && -+ (dmacsr & HIFN_DMACSR_PUBDONE)) -+ WRITE_REG_1(sc, HIFN_1_PUB_STATUS, -+ READ_REG_1(sc, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE); -+ -+ restart = dmacsr & (HIFN_DMACSR_D_OVER | HIFN_DMACSR_R_OVER); -+ if (restart) -+ device_printf(sc->sc_dev, "overrun %x\n", dmacsr); -+ -+ if (sc->sc_flags & HIFN_IS_7811) { -+ if (dmacsr & HIFN_DMACSR_ILLR) -+ device_printf(sc->sc_dev, "illegal read\n"); -+ if (dmacsr & HIFN_DMACSR_ILLW) -+ device_printf(sc->sc_dev, "illegal write\n"); -+ } -+ -+ restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT | -+ HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT); -+ if (restart) { -+ device_printf(sc->sc_dev, "abort, resetting.\n"); -+ hifnstats.hst_abort++; -+ hifn_abort(sc); -+ HIFN_UNLOCK(sc); -+ return IRQ_HANDLED; -+ } -+ -+ if ((dmacsr & HIFN_DMACSR_C_WAIT) && (dma->cmdu == 0)) { -+ /* -+ * If no slots to process and we receive a "waiting on -+ * command" interrupt, we disable the "waiting on command" -+ * (by clearing it). -+ */ -+ sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; -+ WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); -+ } -+ -+ /* clear the rings */ -+ i = dma->resk; u = dma->resu; -+ while (u != 0) { -+ HIFN_RESR_SYNC(sc, i, -+ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); -+ if (dma->resr[i].l & htole32(HIFN_D_VALID)) { -+ HIFN_RESR_SYNC(sc, i, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ break; -+ } -+ -+ if (i != HIFN_D_RES_RSIZE) { -+ struct hifn_command *cmd; -+ u_int8_t *macbuf = NULL; -+ -+ HIFN_RES_SYNC(sc, i, BUS_DMASYNC_POSTREAD); -+ cmd = dma->hifn_commands[i]; -+ KASSERT(cmd != NULL, -+ ("hifn_intr: null command slot %u", i)); -+ dma->hifn_commands[i] = NULL; -+ -+ if (cmd->base_masks & HIFN_BASE_CMD_MAC) { -+ macbuf = dma->result_bufs[i]; -+ macbuf += 12; -+ } -+ -+ hifn_callback(sc, cmd, macbuf); -+ hifnstats.hst_opackets++; -+ u--; -+ } -+ -+ if (++i == (HIFN_D_RES_RSIZE + 1)) -+ i = 0; -+ } -+ dma->resk = i; dma->resu = u; -+ -+ i = dma->srck; u = dma->srcu; -+ while (u != 0) { -+ if (i == HIFN_D_SRC_RSIZE) -+ i = 0; -+ HIFN_SRCR_SYNC(sc, i, -+ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); -+ if (dma->srcr[i].l & htole32(HIFN_D_VALID)) { -+ HIFN_SRCR_SYNC(sc, i, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ break; -+ } -+ i++, u--; -+ } -+ dma->srck = i; dma->srcu = u; -+ -+ i = dma->cmdk; u = dma->cmdu; -+ while (u != 0) { -+ HIFN_CMDR_SYNC(sc, i, -+ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); -+ if (dma->cmdr[i].l & htole32(HIFN_D_VALID)) { -+ HIFN_CMDR_SYNC(sc, i, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ break; -+ } -+ if (i != HIFN_D_CMD_RSIZE) { -+ u--; -+ HIFN_CMD_SYNC(sc, i, BUS_DMASYNC_POSTWRITE); -+ } -+ if (++i == (HIFN_D_CMD_RSIZE + 1)) -+ i = 0; -+ } -+ dma->cmdk = i; dma->cmdu = u; -+ -+ HIFN_UNLOCK(sc); -+ -+ if (sc->sc_needwakeup) { /* XXX check high watermark */ -+ int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); -+#ifdef HIFN_DEBUG -+ if (hifn_debug) -+ device_printf(sc->sc_dev, -+ "wakeup crypto (%x) u %d/%d/%d/%d\n", -+ sc->sc_needwakeup, -+ dma->cmdu, dma->srcu, dma->dstu, dma->resu); -+#endif -+ sc->sc_needwakeup &= ~wakeup; -+ crypto_unblock(sc->sc_cid, wakeup); -+ } -+ -+ return IRQ_HANDLED; -+} -+ -+/* -+ * Allocate a new 'session' and return an encoded session id. 'sidp' -+ * contains our registration id, and should contain an encoded session -+ * id on successful allocation. -+ */ -+static int -+hifn_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) -+{ -+ struct hifn_softc *sc = device_get_softc(dev); -+ struct cryptoini *c; -+ int mac = 0, cry = 0, sesn; -+ struct hifn_session *ses = NULL; -+ unsigned long l_flags; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ KASSERT(sc != NULL, ("hifn_newsession: null softc")); -+ if (sidp == NULL || cri == NULL || sc == NULL) { -+ DPRINTF("%s,%d: %s - EINVAL\n", __FILE__, __LINE__, __FUNCTION__); -+ return (EINVAL); -+ } -+ -+ HIFN_LOCK(sc); -+ if (sc->sc_sessions == NULL) { -+ ses = sc->sc_sessions = (struct hifn_session *)kmalloc(sizeof(*ses), -+ SLAB_ATOMIC); -+ if (ses == NULL) { -+ HIFN_UNLOCK(sc); -+ return (ENOMEM); -+ } -+ sesn = 0; -+ sc->sc_nsessions = 1; -+ } else { -+ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { -+ if (!sc->sc_sessions[sesn].hs_used) { -+ ses = &sc->sc_sessions[sesn]; -+ break; -+ } -+ } -+ -+ if (ses == NULL) { -+ sesn = sc->sc_nsessions; -+ ses = (struct hifn_session *)kmalloc((sesn + 1) * sizeof(*ses), -+ SLAB_ATOMIC); -+ if (ses == NULL) { -+ HIFN_UNLOCK(sc); -+ return (ENOMEM); -+ } -+ bcopy(sc->sc_sessions, ses, sesn * sizeof(*ses)); -+ bzero(sc->sc_sessions, sesn * sizeof(*ses)); -+ kfree(sc->sc_sessions); -+ sc->sc_sessions = ses; -+ ses = &sc->sc_sessions[sesn]; -+ sc->sc_nsessions++; -+ } -+ } -+ HIFN_UNLOCK(sc); -+ -+ bzero(ses, sizeof(*ses)); -+ ses->hs_used = 1; -+ -+ for (c = cri; c != NULL; c = c->cri_next) { -+ switch (c->cri_alg) { -+ case CRYPTO_MD5: -+ case CRYPTO_SHA1: -+ case CRYPTO_MD5_HMAC: -+ case CRYPTO_SHA1_HMAC: -+ if (mac) { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ return (EINVAL); -+ } -+ mac = 1; -+ ses->hs_mlen = c->cri_mlen; -+ if (ses->hs_mlen == 0) { -+ switch (c->cri_alg) { -+ case CRYPTO_MD5: -+ case CRYPTO_MD5_HMAC: -+ ses->hs_mlen = 16; -+ break; -+ case CRYPTO_SHA1: -+ case CRYPTO_SHA1_HMAC: -+ ses->hs_mlen = 20; -+ break; -+ } -+ } -+ break; -+ case CRYPTO_DES_CBC: -+ case CRYPTO_3DES_CBC: -+ case CRYPTO_AES_CBC: -+ /* XXX this may read fewer, does it matter? */ -+ read_random(ses->hs_iv, -+ c->cri_alg == CRYPTO_AES_CBC ? -+ HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH); -+ /*FALLTHROUGH*/ -+ case CRYPTO_ARC4: -+ if (cry) { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ return (EINVAL); -+ } -+ cry = 1; -+ break; -+ default: -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ return (EINVAL); -+ } -+ } -+ if (mac == 0 && cry == 0) { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ return (EINVAL); -+ } -+ -+ *sidp = HIFN_SID(device_get_unit(sc->sc_dev), sesn); -+ -+ return (0); -+} -+ -+/* -+ * Deallocate a session. -+ * XXX this routine should run a zero'd mac/encrypt key into context ram. -+ * XXX to blow away any keys already stored there. -+ */ -+static int -+hifn_freesession(device_t dev, u_int64_t tid) -+{ -+ struct hifn_softc *sc = device_get_softc(dev); -+ int session, error; -+ u_int32_t sid = CRYPTO_SESID2LID(tid); -+ unsigned long l_flags; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ KASSERT(sc != NULL, ("hifn_freesession: null softc")); -+ if (sc == NULL) { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ return (EINVAL); -+ } -+ -+ HIFN_LOCK(sc); -+ session = HIFN_SESSION(sid); -+ if (session < sc->sc_nsessions) { -+ bzero(&sc->sc_sessions[session], sizeof(struct hifn_session)); -+ error = 0; -+ } else { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ error = EINVAL; -+ } -+ HIFN_UNLOCK(sc); -+ -+ return (error); -+} -+ -+static int -+hifn_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ struct hifn_softc *sc = device_get_softc(dev); -+ struct hifn_command *cmd = NULL; -+ int session, err, ivlen; -+ struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (crp == NULL || crp->crp_callback == NULL) { -+ hifnstats.hst_invalid++; -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ return (EINVAL); -+ } -+ session = HIFN_SESSION(crp->crp_sid); -+ -+ if (sc == NULL || session >= sc->sc_nsessions) { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ err = EINVAL; -+ goto errout; -+ } -+ -+ cmd = kmalloc(sizeof(struct hifn_command), SLAB_ATOMIC); -+ if (cmd == NULL) { -+ hifnstats.hst_nomem++; -+ err = ENOMEM; -+ goto errout; -+ } -+ memset(cmd, 0, sizeof(*cmd)); -+ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ cmd->src_skb = (struct sk_buff *)crp->crp_buf; -+ cmd->dst_skb = (struct sk_buff *)crp->crp_buf; -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ cmd->src_io = (struct uio *)crp->crp_buf; -+ cmd->dst_io = (struct uio *)crp->crp_buf; -+ } else { -+ cmd->src_buf = crp->crp_buf; -+ cmd->dst_buf = crp->crp_buf; -+ } -+ -+ crd1 = crp->crp_desc; -+ if (crd1 == NULL) { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ err = EINVAL; -+ goto errout; -+ } -+ crd2 = crd1->crd_next; -+ -+ if (crd2 == NULL) { -+ if (crd1->crd_alg == CRYPTO_MD5_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1 || -+ crd1->crd_alg == CRYPTO_MD5) { -+ maccrd = crd1; -+ enccrd = NULL; -+ } else if (crd1->crd_alg == CRYPTO_DES_CBC || -+ crd1->crd_alg == CRYPTO_3DES_CBC || -+ crd1->crd_alg == CRYPTO_AES_CBC || -+ crd1->crd_alg == CRYPTO_ARC4) { -+ if ((crd1->crd_flags & CRD_F_ENCRYPT) == 0) -+ cmd->base_masks |= HIFN_BASE_CMD_DECODE; -+ maccrd = NULL; -+ enccrd = crd1; -+ } else { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ err = EINVAL; -+ goto errout; -+ } -+ } else { -+ if ((crd1->crd_alg == CRYPTO_MD5_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1_HMAC || -+ crd1->crd_alg == CRYPTO_MD5 || -+ crd1->crd_alg == CRYPTO_SHA1) && -+ (crd2->crd_alg == CRYPTO_DES_CBC || -+ crd2->crd_alg == CRYPTO_3DES_CBC || -+ crd2->crd_alg == CRYPTO_AES_CBC || -+ crd2->crd_alg == CRYPTO_ARC4) && -+ ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { -+ cmd->base_masks = HIFN_BASE_CMD_DECODE; -+ maccrd = crd1; -+ enccrd = crd2; -+ } else if ((crd1->crd_alg == CRYPTO_DES_CBC || -+ crd1->crd_alg == CRYPTO_ARC4 || -+ crd1->crd_alg == CRYPTO_3DES_CBC || -+ crd1->crd_alg == CRYPTO_AES_CBC) && -+ (crd2->crd_alg == CRYPTO_MD5_HMAC || -+ crd2->crd_alg == CRYPTO_SHA1_HMAC || -+ crd2->crd_alg == CRYPTO_MD5 || -+ crd2->crd_alg == CRYPTO_SHA1) && -+ (crd1->crd_flags & CRD_F_ENCRYPT)) { -+ enccrd = crd1; -+ maccrd = crd2; -+ } else { -+ /* -+ * We cannot order the 7751 as requested -+ */ -+ DPRINTF("%s,%d: %s %d,%d,%d - EINVAL\n",__FILE__,__LINE__,__FUNCTION__, crd1->crd_alg, crd2->crd_alg, crd1->crd_flags & CRD_F_ENCRYPT); -+ err = EINVAL; -+ goto errout; -+ } -+ } -+ -+ if (enccrd) { -+ cmd->enccrd = enccrd; -+ cmd->base_masks |= HIFN_BASE_CMD_CRYPT; -+ switch (enccrd->crd_alg) { -+ case CRYPTO_ARC4: -+ cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_RC4; -+ break; -+ case CRYPTO_DES_CBC: -+ cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_DES | -+ HIFN_CRYPT_CMD_MODE_CBC | -+ HIFN_CRYPT_CMD_NEW_IV; -+ break; -+ case CRYPTO_3DES_CBC: -+ cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_3DES | -+ HIFN_CRYPT_CMD_MODE_CBC | -+ HIFN_CRYPT_CMD_NEW_IV; -+ break; -+ case CRYPTO_AES_CBC: -+ cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_AES | -+ HIFN_CRYPT_CMD_MODE_CBC | -+ HIFN_CRYPT_CMD_NEW_IV; -+ break; -+ default: -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ err = EINVAL; -+ goto errout; -+ } -+ if (enccrd->crd_alg != CRYPTO_ARC4) { -+ ivlen = ((enccrd->crd_alg == CRYPTO_AES_CBC) ? -+ HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH); -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) { -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) -+ bcopy(enccrd->crd_iv, cmd->iv, ivlen); -+ else -+ bcopy(sc->sc_sessions[session].hs_iv, -+ cmd->iv, ivlen); -+ -+ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) -+ == 0) { -+ crypto_copyback(crp->crp_flags, -+ crp->crp_buf, enccrd->crd_inject, -+ ivlen, cmd->iv); -+ } -+ } else { -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) -+ bcopy(enccrd->crd_iv, cmd->iv, ivlen); -+ else { -+ crypto_copydata(crp->crp_flags, -+ crp->crp_buf, enccrd->crd_inject, -+ ivlen, cmd->iv); -+ } -+ } -+ } -+ -+ if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) -+ cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY; -+ cmd->ck = enccrd->crd_key; -+ cmd->cklen = enccrd->crd_klen >> 3; -+ cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY; -+ -+ /* -+ * Need to specify the size for the AES key in the masks. -+ */ -+ if ((cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) == -+ HIFN_CRYPT_CMD_ALG_AES) { -+ switch (cmd->cklen) { -+ case 16: -+ cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_128; -+ break; -+ case 24: -+ cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_192; -+ break; -+ case 32: -+ cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_256; -+ break; -+ default: -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ err = EINVAL; -+ goto errout; -+ } -+ } -+ } -+ -+ if (maccrd) { -+ cmd->maccrd = maccrd; -+ cmd->base_masks |= HIFN_BASE_CMD_MAC; -+ -+ switch (maccrd->crd_alg) { -+ case CRYPTO_MD5: -+ cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | -+ HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | -+ HIFN_MAC_CMD_POS_IPSEC; -+ break; -+ case CRYPTO_MD5_HMAC: -+ cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | -+ HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | -+ HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; -+ break; -+ case CRYPTO_SHA1: -+ cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | -+ HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | -+ HIFN_MAC_CMD_POS_IPSEC; -+ break; -+ case CRYPTO_SHA1_HMAC: -+ cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | -+ HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | -+ HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; -+ break; -+ } -+ -+ if (maccrd->crd_alg == CRYPTO_SHA1_HMAC || -+ maccrd->crd_alg == CRYPTO_MD5_HMAC) { -+ cmd->mac_masks |= HIFN_MAC_CMD_NEW_KEY; -+ bcopy(maccrd->crd_key, cmd->mac, maccrd->crd_klen >> 3); -+ bzero(cmd->mac + (maccrd->crd_klen >> 3), -+ HIFN_MAC_KEY_LENGTH - (maccrd->crd_klen >> 3)); -+ } -+ } -+ -+ cmd->crp = crp; -+ cmd->session_num = session; -+ cmd->softc = sc; -+ -+ err = hifn_crypto(sc, cmd, crp, hint); -+ if (!err) { -+ return 0; -+ } else if (err == ERESTART) { -+ /* -+ * There weren't enough resources to dispatch the request -+ * to the part. Notify the caller so they'll requeue this -+ * request and resubmit it again soon. -+ */ -+#ifdef HIFN_DEBUG -+ if (hifn_debug) -+ device_printf(sc->sc_dev, "requeue request\n"); -+#endif -+ kfree(cmd); -+ sc->sc_needwakeup |= CRYPTO_SYMQ; -+ return (err); -+ } -+ -+errout: -+ if (cmd != NULL) -+ kfree(cmd); -+ if (err == EINVAL) -+ hifnstats.hst_invalid++; -+ else -+ hifnstats.hst_nomem++; -+ crp->crp_etype = err; -+ crypto_done(crp); -+ return (err); -+} -+ -+static void -+hifn_abort(struct hifn_softc *sc) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ struct hifn_command *cmd; -+ struct cryptop *crp; -+ int i, u; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ i = dma->resk; u = dma->resu; -+ while (u != 0) { -+ cmd = dma->hifn_commands[i]; -+ KASSERT(cmd != NULL, ("hifn_abort: null command slot %u", i)); -+ dma->hifn_commands[i] = NULL; -+ crp = cmd->crp; -+ -+ if ((dma->resr[i].l & htole32(HIFN_D_VALID)) == 0) { -+ /* Salvage what we can. */ -+ u_int8_t *macbuf; -+ -+ if (cmd->base_masks & HIFN_BASE_CMD_MAC) { -+ macbuf = dma->result_bufs[i]; -+ macbuf += 12; -+ } else -+ macbuf = NULL; -+ hifnstats.hst_opackets++; -+ hifn_callback(sc, cmd, macbuf); -+ } else { -+#if 0 -+ if (cmd->src_map == cmd->dst_map) { -+ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, -+ BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); -+ } else { -+ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, -+ BUS_DMASYNC_POSTWRITE); -+ bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, -+ BUS_DMASYNC_POSTREAD); -+ } -+#endif -+ -+ if (cmd->src_skb != cmd->dst_skb) { -+#ifdef NOTYET -+ m_freem(cmd->src_m); -+ crp->crp_buf = (caddr_t)cmd->dst_m; -+#else -+ device_printf(sc->sc_dev, -+ "%s,%d: CRYPTO_F_SKBUF src != dst not implemented\n", -+ __FILE__, __LINE__); -+#endif -+ } -+ -+ /* non-shared buffers cannot be restarted */ -+ if (cmd->src_map != cmd->dst_map) { -+ /* -+ * XXX should be EAGAIN, delayed until -+ * after the reset. -+ */ -+ crp->crp_etype = ENOMEM; -+ pci_unmap_buf(sc, &cmd->dst); -+ } else -+ crp->crp_etype = ENOMEM; -+ -+ pci_unmap_buf(sc, &cmd->src); -+ -+ kfree(cmd); -+ if (crp->crp_etype != EAGAIN) -+ crypto_done(crp); -+ } -+ -+ if (++i == HIFN_D_RES_RSIZE) -+ i = 0; -+ u--; -+ } -+ dma->resk = i; dma->resu = u; -+ -+ hifn_reset_board(sc, 1); -+ hifn_init_dma(sc); -+ hifn_init_pci_registers(sc); -+} -+ -+static void -+hifn_callback(struct hifn_softc *sc, struct hifn_command *cmd, u_int8_t *macbuf) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ struct cryptop *crp = cmd->crp; -+ struct cryptodesc *crd; -+ int i, u, ivlen; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+#if 0 -+ if (cmd->src_map == cmd->dst_map) { -+ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, -+ BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); -+ } else { -+ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, -+ BUS_DMASYNC_POSTWRITE); -+ bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, -+ BUS_DMASYNC_POSTREAD); -+ } -+#endif -+ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ if (cmd->src_skb != cmd->dst_skb) { -+#ifdef NOTYET -+ crp->crp_buf = (caddr_t)cmd->dst_m; -+ totlen = cmd->src_mapsize; -+ for (m = cmd->dst_m; m != NULL; m = m->m_next) { -+ if (totlen < m->m_len) { -+ m->m_len = totlen; -+ totlen = 0; -+ } else -+ totlen -= m->m_len; -+ } -+ cmd->dst_m->m_pkthdr.len = cmd->src_m->m_pkthdr.len; -+ m_freem(cmd->src_m); -+#else -+ device_printf(sc->sc_dev, -+ "%s,%d: CRYPTO_F_SKBUF src != dst not implemented\n", -+ __FILE__, __LINE__); -+#endif -+ } -+ } -+ -+ if (cmd->sloplen != 0) { -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ cmd->src_mapsize - cmd->sloplen, cmd->sloplen, -+ (caddr_t)&dma->slop[cmd->slopidx]); -+ } -+ -+ i = dma->dstk; u = dma->dstu; -+ while (u != 0) { -+ if (i == HIFN_D_DST_RSIZE) -+ i = 0; -+#if 0 -+ bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, -+ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); -+#endif -+ if (dma->dstr[i].l & htole32(HIFN_D_VALID)) { -+#if 0 -+ bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+#endif -+ break; -+ } -+ i++, u--; -+ } -+ dma->dstk = i; dma->dstu = u; -+ -+ hifnstats.hst_obytes += cmd->dst_mapsize; -+ -+ if ((cmd->base_masks & (HIFN_BASE_CMD_CRYPT | HIFN_BASE_CMD_DECODE)) == -+ HIFN_BASE_CMD_CRYPT) { -+ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { -+ if (crd->crd_alg != CRYPTO_DES_CBC && -+ crd->crd_alg != CRYPTO_3DES_CBC && -+ crd->crd_alg != CRYPTO_AES_CBC) -+ continue; -+ ivlen = ((crd->crd_alg == CRYPTO_AES_CBC) ? -+ HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH); -+ crypto_copydata(crp->crp_flags, crp->crp_buf, -+ crd->crd_skip + crd->crd_len - ivlen, ivlen, -+ cmd->softc->sc_sessions[cmd->session_num].hs_iv); -+ break; -+ } -+ } -+ -+ if (macbuf != NULL) { -+ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { -+ int len; -+ -+ if (crd->crd_alg != CRYPTO_MD5 && -+ crd->crd_alg != CRYPTO_SHA1 && -+ crd->crd_alg != CRYPTO_MD5_HMAC && -+ crd->crd_alg != CRYPTO_SHA1_HMAC) { -+ continue; -+ } -+ len = cmd->softc->sc_sessions[cmd->session_num].hs_mlen; -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, len, macbuf); -+ break; -+ } -+ } -+ -+ if (cmd->src_map != cmd->dst_map) -+ pci_unmap_buf(sc, &cmd->dst); -+ pci_unmap_buf(sc, &cmd->src); -+ kfree(cmd); -+ crypto_done(crp); -+} -+ -+/* -+ * 7811 PB3 rev/2 parts lock-up on burst writes to Group 0 -+ * and Group 1 registers; avoid conditions that could create -+ * burst writes by doing a read in between the writes. -+ * -+ * NB: The read we interpose is always to the same register; -+ * we do this because reading from an arbitrary (e.g. last) -+ * register may not always work. -+ */ -+static void -+hifn_write_reg_0(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) -+{ -+ if (sc->sc_flags & HIFN_IS_7811) { -+ if (sc->sc_bar0_lastreg == reg - 4) -+ readl(sc->sc_bar0 + HIFN_0_PUCNFG); -+ sc->sc_bar0_lastreg = reg; -+ } -+ writel(val, sc->sc_bar0 + reg); -+} -+ -+static void -+hifn_write_reg_1(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) -+{ -+ if (sc->sc_flags & HIFN_IS_7811) { -+ if (sc->sc_bar1_lastreg == reg - 4) -+ readl(sc->sc_bar1 + HIFN_1_REVID); -+ sc->sc_bar1_lastreg = reg; -+ } -+ writel(val, sc->sc_bar1 + reg); -+} -+ -+ -+static struct pci_device_id hifn_pci_tbl[] = { -+ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7951, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7955, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7956, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ { PCI_VENDOR_NETSEC, PCI_PRODUCT_NETSEC_7751, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ { PCI_VENDOR_INVERTEX, PCI_PRODUCT_INVERTEX_AEON, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7811, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ /* -+ * Other vendors share this PCI ID as well, such as -+ * http://www.powercrypt.com, and obviously they also -+ * use the same key. -+ */ -+ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7751, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ { 0, 0, 0, 0, 0, 0, } -+}; -+MODULE_DEVICE_TABLE(pci, hifn_pci_tbl); -+ -+static struct pci_driver hifn_driver = { -+ .name = "hifn", -+ .id_table = hifn_pci_tbl, -+ .probe = hifn_probe, -+ .remove = hifn_remove, -+ /* add PM stuff here one day */ -+}; -+ -+static int __init hifn_init (void) -+{ -+ struct hifn_softc *sc = NULL; -+ int rc; -+ -+ DPRINTF("%s(%p)\n", __FUNCTION__, hifn_init); -+ -+ rc = pci_register_driver(&hifn_driver); -+ pci_register_driver_compat(&hifn_driver, rc); -+ -+ return rc; -+} -+ -+static void __exit hifn_exit (void) -+{ -+ pci_unregister_driver(&hifn_driver); -+} -+ -+module_init(hifn_init); -+module_exit(hifn_exit); -+ -+MODULE_LICENSE("BSD"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("OCF driver for hifn PCI crypto devices"); -diff -Nur linux-2.6.39.orig/crypto/ocf/hifn/hifn7751reg.h linux-2.6.39/crypto/ocf/hifn/hifn7751reg.h ---- linux-2.6.39.orig/crypto/ocf/hifn/hifn7751reg.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/hifn/hifn7751reg.h 2011-08-01 14:38:18.000000000 +0200 -@@ -0,0 +1,540 @@ -+/* $FreeBSD: src/sys/dev/hifn/hifn7751reg.h,v 1.7 2007/03/21 03:42:49 sam Exp $ */ -+/* $OpenBSD: hifn7751reg.h,v 1.35 2002/04/08 17:49:42 jason Exp $ */ -+ -+/*- -+ * Invertex AEON / Hifn 7751 driver -+ * Copyright (c) 1999 Invertex Inc. All rights reserved. -+ * Copyright (c) 1999 Theo de Raadt -+ * Copyright (c) 2000-2001 Network Security Technologies, Inc. -+ * http://www.netsec.net -+ * -+ * Please send any comments, feedback, bug-fixes, or feature requests to -+ * software@invertex.com. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored in part by the Defense Advanced Research Projects -+ * Agency (DARPA) and Air Force Research Laboratory, Air Force -+ * Materiel Command, USAF, under agreement number F30602-01-2-0537. -+ * -+ */ -+#ifndef __HIFN_H__ -+#define __HIFN_H__ -+ -+/* -+ * Some PCI configuration space offset defines. The names were made -+ * identical to the names used by the Linux kernel. -+ */ -+#define HIFN_BAR0 PCIR_BAR(0) /* PUC register map */ -+#define HIFN_BAR1 PCIR_BAR(1) /* DMA register map */ -+#define HIFN_TRDY_TIMEOUT 0x40 -+#define HIFN_RETRY_TIMEOUT 0x41 -+ -+/* -+ * PCI vendor and device identifiers -+ * (the names are preserved from their OpenBSD source). -+ */ -+#define PCI_VENDOR_HIFN 0x13a3 /* Hifn */ -+#define PCI_PRODUCT_HIFN_7751 0x0005 /* 7751 */ -+#define PCI_PRODUCT_HIFN_6500 0x0006 /* 6500 */ -+#define PCI_PRODUCT_HIFN_7811 0x0007 /* 7811 */ -+#define PCI_PRODUCT_HIFN_7855 0x001f /* 7855 */ -+#define PCI_PRODUCT_HIFN_7951 0x0012 /* 7951 */ -+#define PCI_PRODUCT_HIFN_7955 0x0020 /* 7954/7955 */ -+#define PCI_PRODUCT_HIFN_7956 0x001d /* 7956 */ -+ -+#define PCI_VENDOR_INVERTEX 0x14e1 /* Invertex */ -+#define PCI_PRODUCT_INVERTEX_AEON 0x0005 /* AEON */ -+ -+#define PCI_VENDOR_NETSEC 0x1660 /* NetSec */ -+#define PCI_PRODUCT_NETSEC_7751 0x7751 /* 7751 */ -+ -+/* -+ * The values below should multiple of 4 -- and be large enough to handle -+ * any command the driver implements. -+ * -+ * MAX_COMMAND = base command + mac command + encrypt command + -+ * mac-key + rc4-key -+ * MAX_RESULT = base result + mac result + mac + encrypt result -+ * -+ * -+ */ -+#define HIFN_MAX_COMMAND (8 + 8 + 8 + 64 + 260) -+#define HIFN_MAX_RESULT (8 + 4 + 20 + 4) -+ -+/* -+ * hifn_desc_t -+ * -+ * Holds an individual descriptor for any of the rings. -+ */ -+typedef struct hifn_desc { -+ volatile u_int32_t l; /* length and status bits */ -+ volatile u_int32_t p; -+} hifn_desc_t; -+ -+/* -+ * Masks for the "length" field of struct hifn_desc. -+ */ -+#define HIFN_D_LENGTH 0x0000ffff /* length bit mask */ -+#define HIFN_D_MASKDONEIRQ 0x02000000 /* mask the done interrupt */ -+#define HIFN_D_DESTOVER 0x04000000 /* destination overflow */ -+#define HIFN_D_OVER 0x08000000 /* overflow */ -+#define HIFN_D_LAST 0x20000000 /* last descriptor in chain */ -+#define HIFN_D_JUMP 0x40000000 /* jump descriptor */ -+#define HIFN_D_VALID 0x80000000 /* valid bit */ -+ -+ -+/* -+ * Processing Unit Registers (offset from BASEREG0) -+ */ -+#define HIFN_0_PUDATA 0x00 /* Processing Unit Data */ -+#define HIFN_0_PUCTRL 0x04 /* Processing Unit Control */ -+#define HIFN_0_PUISR 0x08 /* Processing Unit Interrupt Status */ -+#define HIFN_0_PUCNFG 0x0c /* Processing Unit Configuration */ -+#define HIFN_0_PUIER 0x10 /* Processing Unit Interrupt Enable */ -+#define HIFN_0_PUSTAT 0x14 /* Processing Unit Status/Chip ID */ -+#define HIFN_0_FIFOSTAT 0x18 /* FIFO Status */ -+#define HIFN_0_FIFOCNFG 0x1c /* FIFO Configuration */ -+#define HIFN_0_PUCTRL2 0x28 /* Processing Unit Control (2nd map) */ -+#define HIFN_0_MUTE1 0x80 -+#define HIFN_0_MUTE2 0x90 -+#define HIFN_0_SPACESIZE 0x100 /* Register space size */ -+ -+/* Processing Unit Control Register (HIFN_0_PUCTRL) */ -+#define HIFN_PUCTRL_CLRSRCFIFO 0x0010 /* clear source fifo */ -+#define HIFN_PUCTRL_STOP 0x0008 /* stop pu */ -+#define HIFN_PUCTRL_LOCKRAM 0x0004 /* lock ram */ -+#define HIFN_PUCTRL_DMAENA 0x0002 /* enable dma */ -+#define HIFN_PUCTRL_RESET 0x0001 /* Reset processing unit */ -+ -+/* Processing Unit Interrupt Status Register (HIFN_0_PUISR) */ -+#define HIFN_PUISR_CMDINVAL 0x8000 /* Invalid command interrupt */ -+#define HIFN_PUISR_DATAERR 0x4000 /* Data error interrupt */ -+#define HIFN_PUISR_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ -+#define HIFN_PUISR_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ -+#define HIFN_PUISR_DSTOVER 0x0200 /* Destination overrun interrupt */ -+#define HIFN_PUISR_SRCCMD 0x0080 /* Source command interrupt */ -+#define HIFN_PUISR_SRCCTX 0x0040 /* Source context interrupt */ -+#define HIFN_PUISR_SRCDATA 0x0020 /* Source data interrupt */ -+#define HIFN_PUISR_DSTDATA 0x0010 /* Destination data interrupt */ -+#define HIFN_PUISR_DSTRESULT 0x0004 /* Destination result interrupt */ -+ -+/* Processing Unit Configuration Register (HIFN_0_PUCNFG) */ -+#define HIFN_PUCNFG_DRAMMASK 0xe000 /* DRAM size mask */ -+#define HIFN_PUCNFG_DSZ_256K 0x0000 /* 256k dram */ -+#define HIFN_PUCNFG_DSZ_512K 0x2000 /* 512k dram */ -+#define HIFN_PUCNFG_DSZ_1M 0x4000 /* 1m dram */ -+#define HIFN_PUCNFG_DSZ_2M 0x6000 /* 2m dram */ -+#define HIFN_PUCNFG_DSZ_4M 0x8000 /* 4m dram */ -+#define HIFN_PUCNFG_DSZ_8M 0xa000 /* 8m dram */ -+#define HIFN_PUNCFG_DSZ_16M 0xc000 /* 16m dram */ -+#define HIFN_PUCNFG_DSZ_32M 0xe000 /* 32m dram */ -+#define HIFN_PUCNFG_DRAMREFRESH 0x1800 /* DRAM refresh rate mask */ -+#define HIFN_PUCNFG_DRFR_512 0x0000 /* 512 divisor of ECLK */ -+#define HIFN_PUCNFG_DRFR_256 0x0800 /* 256 divisor of ECLK */ -+#define HIFN_PUCNFG_DRFR_128 0x1000 /* 128 divisor of ECLK */ -+#define HIFN_PUCNFG_TCALLPHASES 0x0200 /* your guess is as good as mine... */ -+#define HIFN_PUCNFG_TCDRVTOTEM 0x0100 /* your guess is as good as mine... */ -+#define HIFN_PUCNFG_BIGENDIAN 0x0080 /* DMA big endian mode */ -+#define HIFN_PUCNFG_BUS32 0x0040 /* Bus width 32bits */ -+#define HIFN_PUCNFG_BUS16 0x0000 /* Bus width 16 bits */ -+#define HIFN_PUCNFG_CHIPID 0x0020 /* Allow chipid from PUSTAT */ -+#define HIFN_PUCNFG_DRAM 0x0010 /* Context RAM is DRAM */ -+#define HIFN_PUCNFG_SRAM 0x0000 /* Context RAM is SRAM */ -+#define HIFN_PUCNFG_COMPSING 0x0004 /* Enable single compression context */ -+#define HIFN_PUCNFG_ENCCNFG 0x0002 /* Encryption configuration */ -+ -+/* Processing Unit Interrupt Enable Register (HIFN_0_PUIER) */ -+#define HIFN_PUIER_CMDINVAL 0x8000 /* Invalid command interrupt */ -+#define HIFN_PUIER_DATAERR 0x4000 /* Data error interrupt */ -+#define HIFN_PUIER_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ -+#define HIFN_PUIER_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ -+#define HIFN_PUIER_DSTOVER 0x0200 /* Destination overrun interrupt */ -+#define HIFN_PUIER_SRCCMD 0x0080 /* Source command interrupt */ -+#define HIFN_PUIER_SRCCTX 0x0040 /* Source context interrupt */ -+#define HIFN_PUIER_SRCDATA 0x0020 /* Source data interrupt */ -+#define HIFN_PUIER_DSTDATA 0x0010 /* Destination data interrupt */ -+#define HIFN_PUIER_DSTRESULT 0x0004 /* Destination result interrupt */ -+ -+/* Processing Unit Status Register/Chip ID (HIFN_0_PUSTAT) */ -+#define HIFN_PUSTAT_CMDINVAL 0x8000 /* Invalid command interrupt */ -+#define HIFN_PUSTAT_DATAERR 0x4000 /* Data error interrupt */ -+#define HIFN_PUSTAT_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ -+#define HIFN_PUSTAT_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ -+#define HIFN_PUSTAT_DSTOVER 0x0200 /* Destination overrun interrupt */ -+#define HIFN_PUSTAT_SRCCMD 0x0080 /* Source command interrupt */ -+#define HIFN_PUSTAT_SRCCTX 0x0040 /* Source context interrupt */ -+#define HIFN_PUSTAT_SRCDATA 0x0020 /* Source data interrupt */ -+#define HIFN_PUSTAT_DSTDATA 0x0010 /* Destination data interrupt */ -+#define HIFN_PUSTAT_DSTRESULT 0x0004 /* Destination result interrupt */ -+#define HIFN_PUSTAT_CHIPREV 0x00ff /* Chip revision mask */ -+#define HIFN_PUSTAT_CHIPENA 0xff00 /* Chip enabled mask */ -+#define HIFN_PUSTAT_ENA_2 0x1100 /* Level 2 enabled */ -+#define HIFN_PUSTAT_ENA_1 0x1000 /* Level 1 enabled */ -+#define HIFN_PUSTAT_ENA_0 0x3000 /* Level 0 enabled */ -+#define HIFN_PUSTAT_REV_2 0x0020 /* 7751 PT6/2 */ -+#define HIFN_PUSTAT_REV_3 0x0030 /* 7751 PT6/3 */ -+ -+/* FIFO Status Register (HIFN_0_FIFOSTAT) */ -+#define HIFN_FIFOSTAT_SRC 0x7f00 /* Source FIFO available */ -+#define HIFN_FIFOSTAT_DST 0x007f /* Destination FIFO available */ -+ -+/* FIFO Configuration Register (HIFN_0_FIFOCNFG) */ -+#define HIFN_FIFOCNFG_THRESHOLD 0x0400 /* must be written as this value */ -+ -+/* -+ * DMA Interface Registers (offset from BASEREG1) -+ */ -+#define HIFN_1_DMA_CRAR 0x0c /* DMA Command Ring Address */ -+#define HIFN_1_DMA_SRAR 0x1c /* DMA Source Ring Address */ -+#define HIFN_1_DMA_RRAR 0x2c /* DMA Result Ring Address */ -+#define HIFN_1_DMA_DRAR 0x3c /* DMA Destination Ring Address */ -+#define HIFN_1_DMA_CSR 0x40 /* DMA Status and Control */ -+#define HIFN_1_DMA_IER 0x44 /* DMA Interrupt Enable */ -+#define HIFN_1_DMA_CNFG 0x48 /* DMA Configuration */ -+#define HIFN_1_PLL 0x4c /* 7955/7956: PLL config */ -+#define HIFN_1_7811_RNGENA 0x60 /* 7811: rng enable */ -+#define HIFN_1_7811_RNGCFG 0x64 /* 7811: rng config */ -+#define HIFN_1_7811_RNGDAT 0x68 /* 7811: rng data */ -+#define HIFN_1_7811_RNGSTS 0x6c /* 7811: rng status */ -+#define HIFN_1_DMA_CNFG2 0x6c /* 7955/7956: dma config #2 */ -+#define HIFN_1_7811_MIPSRST 0x94 /* 7811: MIPS reset */ -+#define HIFN_1_REVID 0x98 /* Revision ID */ -+ -+#define HIFN_1_PUB_RESET 0x204 /* Public/RNG Reset */ -+#define HIFN_1_PUB_BASE 0x300 /* Public Base Address */ -+#define HIFN_1_PUB_OPLEN 0x304 /* 7951-compat Public Operand Length */ -+#define HIFN_1_PUB_OP 0x308 /* 7951-compat Public Operand */ -+#define HIFN_1_PUB_STATUS 0x30c /* 7951-compat Public Status */ -+#define HIFN_1_PUB_IEN 0x310 /* Public Interrupt enable */ -+#define HIFN_1_RNG_CONFIG 0x314 /* RNG config */ -+#define HIFN_1_RNG_DATA 0x318 /* RNG data */ -+#define HIFN_1_PUB_MODE 0x320 /* PK mode */ -+#define HIFN_1_PUB_FIFO_OPLEN 0x380 /* first element of oplen fifo */ -+#define HIFN_1_PUB_FIFO_OP 0x384 /* first element of op fifo */ -+#define HIFN_1_PUB_MEM 0x400 /* start of Public key memory */ -+#define HIFN_1_PUB_MEMEND 0xbff /* end of Public key memory */ -+ -+/* DMA Status and Control Register (HIFN_1_DMA_CSR) */ -+#define HIFN_DMACSR_D_CTRLMASK 0xc0000000 /* Destinition Ring Control */ -+#define HIFN_DMACSR_D_CTRL_NOP 0x00000000 /* Dest. Control: no-op */ -+#define HIFN_DMACSR_D_CTRL_DIS 0x40000000 /* Dest. Control: disable */ -+#define HIFN_DMACSR_D_CTRL_ENA 0x80000000 /* Dest. Control: enable */ -+#define HIFN_DMACSR_D_ABORT 0x20000000 /* Destinition Ring PCIAbort */ -+#define HIFN_DMACSR_D_DONE 0x10000000 /* Destinition Ring Done */ -+#define HIFN_DMACSR_D_LAST 0x08000000 /* Destinition Ring Last */ -+#define HIFN_DMACSR_D_WAIT 0x04000000 /* Destinition Ring Waiting */ -+#define HIFN_DMACSR_D_OVER 0x02000000 /* Destinition Ring Overflow */ -+#define HIFN_DMACSR_R_CTRL 0x00c00000 /* Result Ring Control */ -+#define HIFN_DMACSR_R_CTRL_NOP 0x00000000 /* Result Control: no-op */ -+#define HIFN_DMACSR_R_CTRL_DIS 0x00400000 /* Result Control: disable */ -+#define HIFN_DMACSR_R_CTRL_ENA 0x00800000 /* Result Control: enable */ -+#define HIFN_DMACSR_R_ABORT 0x00200000 /* Result Ring PCI Abort */ -+#define HIFN_DMACSR_R_DONE 0x00100000 /* Result Ring Done */ -+#define HIFN_DMACSR_R_LAST 0x00080000 /* Result Ring Last */ -+#define HIFN_DMACSR_R_WAIT 0x00040000 /* Result Ring Waiting */ -+#define HIFN_DMACSR_R_OVER 0x00020000 /* Result Ring Overflow */ -+#define HIFN_DMACSR_S_CTRL 0x0000c000 /* Source Ring Control */ -+#define HIFN_DMACSR_S_CTRL_NOP 0x00000000 /* Source Control: no-op */ -+#define HIFN_DMACSR_S_CTRL_DIS 0x00004000 /* Source Control: disable */ -+#define HIFN_DMACSR_S_CTRL_ENA 0x00008000 /* Source Control: enable */ -+#define HIFN_DMACSR_S_ABORT 0x00002000 /* Source Ring PCI Abort */ -+#define HIFN_DMACSR_S_DONE 0x00001000 /* Source Ring Done */ -+#define HIFN_DMACSR_S_LAST 0x00000800 /* Source Ring Last */ -+#define HIFN_DMACSR_S_WAIT 0x00000400 /* Source Ring Waiting */ -+#define HIFN_DMACSR_ILLW 0x00000200 /* Illegal write (7811 only) */ -+#define HIFN_DMACSR_ILLR 0x00000100 /* Illegal read (7811 only) */ -+#define HIFN_DMACSR_C_CTRL 0x000000c0 /* Command Ring Control */ -+#define HIFN_DMACSR_C_CTRL_NOP 0x00000000 /* Command Control: no-op */ -+#define HIFN_DMACSR_C_CTRL_DIS 0x00000040 /* Command Control: disable */ -+#define HIFN_DMACSR_C_CTRL_ENA 0x00000080 /* Command Control: enable */ -+#define HIFN_DMACSR_C_ABORT 0x00000020 /* Command Ring PCI Abort */ -+#define HIFN_DMACSR_C_DONE 0x00000010 /* Command Ring Done */ -+#define HIFN_DMACSR_C_LAST 0x00000008 /* Command Ring Last */ -+#define HIFN_DMACSR_C_WAIT 0x00000004 /* Command Ring Waiting */ -+#define HIFN_DMACSR_PUBDONE 0x00000002 /* Public op done (7951 only) */ -+#define HIFN_DMACSR_ENGINE 0x00000001 /* Command Ring Engine IRQ */ -+ -+/* DMA Interrupt Enable Register (HIFN_1_DMA_IER) */ -+#define HIFN_DMAIER_D_ABORT 0x20000000 /* Destination Ring PCIAbort */ -+#define HIFN_DMAIER_D_DONE 0x10000000 /* Destination Ring Done */ -+#define HIFN_DMAIER_D_LAST 0x08000000 /* Destination Ring Last */ -+#define HIFN_DMAIER_D_WAIT 0x04000000 /* Destination Ring Waiting */ -+#define HIFN_DMAIER_D_OVER 0x02000000 /* Destination Ring Overflow */ -+#define HIFN_DMAIER_R_ABORT 0x00200000 /* Result Ring PCI Abort */ -+#define HIFN_DMAIER_R_DONE 0x00100000 /* Result Ring Done */ -+#define HIFN_DMAIER_R_LAST 0x00080000 /* Result Ring Last */ -+#define HIFN_DMAIER_R_WAIT 0x00040000 /* Result Ring Waiting */ -+#define HIFN_DMAIER_R_OVER 0x00020000 /* Result Ring Overflow */ -+#define HIFN_DMAIER_S_ABORT 0x00002000 /* Source Ring PCI Abort */ -+#define HIFN_DMAIER_S_DONE 0x00001000 /* Source Ring Done */ -+#define HIFN_DMAIER_S_LAST 0x00000800 /* Source Ring Last */ -+#define HIFN_DMAIER_S_WAIT 0x00000400 /* Source Ring Waiting */ -+#define HIFN_DMAIER_ILLW 0x00000200 /* Illegal write (7811 only) */ -+#define HIFN_DMAIER_ILLR 0x00000100 /* Illegal read (7811 only) */ -+#define HIFN_DMAIER_C_ABORT 0x00000020 /* Command Ring PCI Abort */ -+#define HIFN_DMAIER_C_DONE 0x00000010 /* Command Ring Done */ -+#define HIFN_DMAIER_C_LAST 0x00000008 /* Command Ring Last */ -+#define HIFN_DMAIER_C_WAIT 0x00000004 /* Command Ring Waiting */ -+#define HIFN_DMAIER_PUBDONE 0x00000002 /* public op done (7951 only) */ -+#define HIFN_DMAIER_ENGINE 0x00000001 /* Engine IRQ */ -+ -+/* DMA Configuration Register (HIFN_1_DMA_CNFG) */ -+#define HIFN_DMACNFG_BIGENDIAN 0x10000000 /* big endian mode */ -+#define HIFN_DMACNFG_POLLFREQ 0x00ff0000 /* Poll frequency mask */ -+#define HIFN_DMACNFG_UNLOCK 0x00000800 -+#define HIFN_DMACNFG_POLLINVAL 0x00000700 /* Invalid Poll Scalar */ -+#define HIFN_DMACNFG_LAST 0x00000010 /* Host control LAST bit */ -+#define HIFN_DMACNFG_MODE 0x00000004 /* DMA mode */ -+#define HIFN_DMACNFG_DMARESET 0x00000002 /* DMA Reset # */ -+#define HIFN_DMACNFG_MSTRESET 0x00000001 /* Master Reset # */ -+ -+/* DMA Configuration Register (HIFN_1_DMA_CNFG2) */ -+#define HIFN_DMACNFG2_PKSWAP32 (1 << 19) /* swap the OPLEN/OP reg */ -+#define HIFN_DMACNFG2_PKSWAP8 (1 << 18) /* swap the bits of OPLEN/OP */ -+#define HIFN_DMACNFG2_BAR0_SWAP32 (1<<17) /* swap the bytes of BAR0 */ -+#define HIFN_DMACNFG2_BAR1_SWAP8 (1<<16) /* swap the bits of BAR0 */ -+#define HIFN_DMACNFG2_INIT_WRITE_BURST_SHIFT 12 -+#define HIFN_DMACNFG2_INIT_READ_BURST_SHIFT 8 -+#define HIFN_DMACNFG2_TGT_WRITE_BURST_SHIFT 4 -+#define HIFN_DMACNFG2_TGT_READ_BURST_SHIFT 0 -+ -+/* 7811 RNG Enable Register (HIFN_1_7811_RNGENA) */ -+#define HIFN_7811_RNGENA_ENA 0x00000001 /* enable RNG */ -+ -+/* 7811 RNG Config Register (HIFN_1_7811_RNGCFG) */ -+#define HIFN_7811_RNGCFG_PRE1 0x00000f00 /* first prescalar */ -+#define HIFN_7811_RNGCFG_OPRE 0x00000080 /* output prescalar */ -+#define HIFN_7811_RNGCFG_DEFL 0x00000f80 /* 2 words/ 1/100 sec */ -+ -+/* 7811 RNG Status Register (HIFN_1_7811_RNGSTS) */ -+#define HIFN_7811_RNGSTS_RDY 0x00004000 /* two numbers in FIFO */ -+#define HIFN_7811_RNGSTS_UFL 0x00001000 /* rng underflow */ -+ -+/* 7811 MIPS Reset Register (HIFN_1_7811_MIPSRST) */ -+#define HIFN_MIPSRST_BAR2SIZE 0xffff0000 /* sdram size */ -+#define HIFN_MIPSRST_GPRAMINIT 0x00008000 /* gpram can be accessed */ -+#define HIFN_MIPSRST_CRAMINIT 0x00004000 /* ctxram can be accessed */ -+#define HIFN_MIPSRST_LED2 0x00000400 /* external LED2 */ -+#define HIFN_MIPSRST_LED1 0x00000200 /* external LED1 */ -+#define HIFN_MIPSRST_LED0 0x00000100 /* external LED0 */ -+#define HIFN_MIPSRST_MIPSDIS 0x00000004 /* disable MIPS */ -+#define HIFN_MIPSRST_MIPSRST 0x00000002 /* warm reset MIPS */ -+#define HIFN_MIPSRST_MIPSCOLD 0x00000001 /* cold reset MIPS */ -+ -+/* Public key reset register (HIFN_1_PUB_RESET) */ -+#define HIFN_PUBRST_RESET 0x00000001 /* reset public/rng unit */ -+ -+/* Public operation register (HIFN_1_PUB_OP) */ -+#define HIFN_PUBOP_AOFFSET 0x0000003e /* A offset */ -+#define HIFN_PUBOP_BOFFSET 0x00000fc0 /* B offset */ -+#define HIFN_PUBOP_MOFFSET 0x0003f000 /* M offset */ -+#define HIFN_PUBOP_OP_MASK 0x003c0000 /* Opcode: */ -+#define HIFN_PUBOP_OP_NOP 0x00000000 /* NOP */ -+#define HIFN_PUBOP_OP_ADD 0x00040000 /* ADD */ -+#define HIFN_PUBOP_OP_ADDC 0x00080000 /* ADD w/carry */ -+#define HIFN_PUBOP_OP_SUB 0x000c0000 /* SUB */ -+#define HIFN_PUBOP_OP_SUBC 0x00100000 /* SUB w/carry */ -+#define HIFN_PUBOP_OP_MODADD 0x00140000 /* Modular ADD */ -+#define HIFN_PUBOP_OP_MODSUB 0x00180000 /* Modular SUB */ -+#define HIFN_PUBOP_OP_INCA 0x001c0000 /* INC A */ -+#define HIFN_PUBOP_OP_DECA 0x00200000 /* DEC A */ -+#define HIFN_PUBOP_OP_MULT 0x00240000 /* MULT */ -+#define HIFN_PUBOP_OP_MODMULT 0x00280000 /* Modular MULT */ -+#define HIFN_PUBOP_OP_MODRED 0x002c0000 /* Modular Red */ -+#define HIFN_PUBOP_OP_MODEXP 0x00300000 /* Modular Exp */ -+ -+/* Public operand length register (HIFN_1_PUB_OPLEN) */ -+#define HIFN_PUBOPLEN_MODLEN 0x0000007f -+#define HIFN_PUBOPLEN_EXPLEN 0x0003ff80 -+#define HIFN_PUBOPLEN_REDLEN 0x003c0000 -+ -+/* Public status register (HIFN_1_PUB_STATUS) */ -+#define HIFN_PUBSTS_DONE 0x00000001 /* operation done */ -+#define HIFN_PUBSTS_CARRY 0x00000002 /* carry */ -+#define HIFN_PUBSTS_FIFO_EMPTY 0x00000100 /* fifo empty */ -+#define HIFN_PUBSTS_FIFO_FULL 0x00000200 /* fifo full */ -+#define HIFN_PUBSTS_FIFO_OVFL 0x00000400 /* fifo overflow */ -+#define HIFN_PUBSTS_FIFO_WRITE 0x000f0000 /* fifo write */ -+#define HIFN_PUBSTS_FIFO_READ 0x0f000000 /* fifo read */ -+ -+/* Public interrupt enable register (HIFN_1_PUB_IEN) */ -+#define HIFN_PUBIEN_DONE 0x00000001 /* operation done interrupt */ -+ -+/* Random number generator config register (HIFN_1_RNG_CONFIG) */ -+#define HIFN_RNGCFG_ENA 0x00000001 /* enable rng */ -+ -+/* -+ * Register offsets in register set 1 -+ */ -+ -+#define HIFN_UNLOCK_SECRET1 0xf4 -+#define HIFN_UNLOCK_SECRET2 0xfc -+ -+/* -+ * PLL config register -+ * -+ * This register is present only on 7954/7955/7956 parts. It must be -+ * programmed according to the bus interface method used by the h/w. -+ * Note that the parts require a stable clock. Since the PCI clock -+ * may vary the reference clock must usually be used. To avoid -+ * overclocking the core logic, setup must be done carefully, refer -+ * to the driver for details. The exact multiplier required varies -+ * by part and system configuration; refer to the Hifn documentation. -+ */ -+#define HIFN_PLL_REF_SEL 0x00000001 /* REF/HBI clk selection */ -+#define HIFN_PLL_BP 0x00000002 /* bypass (used during setup) */ -+/* bit 2 reserved */ -+#define HIFN_PLL_PK_CLK_SEL 0x00000008 /* public key clk select */ -+#define HIFN_PLL_PE_CLK_SEL 0x00000010 /* packet engine clk select */ -+/* bits 5-9 reserved */ -+#define HIFN_PLL_MBSET 0x00000400 /* must be set to 1 */ -+#define HIFN_PLL_ND 0x00003800 /* Fpll_ref multiplier select */ -+#define HIFN_PLL_ND_SHIFT 11 -+#define HIFN_PLL_ND_2 0x00000000 /* 2x */ -+#define HIFN_PLL_ND_4 0x00000800 /* 4x */ -+#define HIFN_PLL_ND_6 0x00001000 /* 6x */ -+#define HIFN_PLL_ND_8 0x00001800 /* 8x */ -+#define HIFN_PLL_ND_10 0x00002000 /* 10x */ -+#define HIFN_PLL_ND_12 0x00002800 /* 12x */ -+/* bits 14-15 reserved */ -+#define HIFN_PLL_IS 0x00010000 /* charge pump current select */ -+/* bits 17-31 reserved */ -+ -+/* -+ * Board configuration specifies only these bits. -+ */ -+#define HIFN_PLL_CONFIG (HIFN_PLL_IS|HIFN_PLL_ND|HIFN_PLL_REF_SEL) -+ -+/* -+ * Public Key Engine Mode Register -+ */ -+#define HIFN_PKMODE_HOSTINVERT (1 << 0) /* HOST INVERT */ -+#define HIFN_PKMODE_ENHANCED (1 << 1) /* Enable enhanced mode */ -+ -+ -+/********************************************************************* -+ * Structs for board commands -+ * -+ *********************************************************************/ -+ -+/* -+ * Structure to help build up the command data structure. -+ */ -+typedef struct hifn_base_command { -+ volatile u_int16_t masks; -+ volatile u_int16_t session_num; -+ volatile u_int16_t total_source_count; -+ volatile u_int16_t total_dest_count; -+} hifn_base_command_t; -+ -+#define HIFN_BASE_CMD_MAC 0x0400 -+#define HIFN_BASE_CMD_CRYPT 0x0800 -+#define HIFN_BASE_CMD_DECODE 0x2000 -+#define HIFN_BASE_CMD_SRCLEN_M 0xc000 -+#define HIFN_BASE_CMD_SRCLEN_S 14 -+#define HIFN_BASE_CMD_DSTLEN_M 0x3000 -+#define HIFN_BASE_CMD_DSTLEN_S 12 -+#define HIFN_BASE_CMD_LENMASK_HI 0x30000 -+#define HIFN_BASE_CMD_LENMASK_LO 0x0ffff -+ -+/* -+ * Structure to help build up the command data structure. -+ */ -+typedef struct hifn_crypt_command { -+ volatile u_int16_t masks; -+ volatile u_int16_t header_skip; -+ volatile u_int16_t source_count; -+ volatile u_int16_t reserved; -+} hifn_crypt_command_t; -+ -+#define HIFN_CRYPT_CMD_ALG_MASK 0x0003 /* algorithm: */ -+#define HIFN_CRYPT_CMD_ALG_DES 0x0000 /* DES */ -+#define HIFN_CRYPT_CMD_ALG_3DES 0x0001 /* 3DES */ -+#define HIFN_CRYPT_CMD_ALG_RC4 0x0002 /* RC4 */ -+#define HIFN_CRYPT_CMD_ALG_AES 0x0003 /* AES */ -+#define HIFN_CRYPT_CMD_MODE_MASK 0x0018 /* Encrypt mode: */ -+#define HIFN_CRYPT_CMD_MODE_ECB 0x0000 /* ECB */ -+#define HIFN_CRYPT_CMD_MODE_CBC 0x0008 /* CBC */ -+#define HIFN_CRYPT_CMD_MODE_CFB 0x0010 /* CFB */ -+#define HIFN_CRYPT_CMD_MODE_OFB 0x0018 /* OFB */ -+#define HIFN_CRYPT_CMD_CLR_CTX 0x0040 /* clear context */ -+#define HIFN_CRYPT_CMD_NEW_KEY 0x0800 /* expect new key */ -+#define HIFN_CRYPT_CMD_NEW_IV 0x1000 /* expect new iv */ -+ -+#define HIFN_CRYPT_CMD_SRCLEN_M 0xc000 -+#define HIFN_CRYPT_CMD_SRCLEN_S 14 -+ -+#define HIFN_CRYPT_CMD_KSZ_MASK 0x0600 /* AES key size: */ -+#define HIFN_CRYPT_CMD_KSZ_128 0x0000 /* 128 bit */ -+#define HIFN_CRYPT_CMD_KSZ_192 0x0200 /* 192 bit */ -+#define HIFN_CRYPT_CMD_KSZ_256 0x0400 /* 256 bit */ -+ -+/* -+ * Structure to help build up the command data structure. -+ */ -+typedef struct hifn_mac_command { -+ volatile u_int16_t masks; -+ volatile u_int16_t header_skip; -+ volatile u_int16_t source_count; -+ volatile u_int16_t reserved; -+} hifn_mac_command_t; -+ -+#define HIFN_MAC_CMD_ALG_MASK 0x0001 -+#define HIFN_MAC_CMD_ALG_SHA1 0x0000 -+#define HIFN_MAC_CMD_ALG_MD5 0x0001 -+#define HIFN_MAC_CMD_MODE_MASK 0x000c -+#define HIFN_MAC_CMD_MODE_HMAC 0x0000 -+#define HIFN_MAC_CMD_MODE_SSL_MAC 0x0004 -+#define HIFN_MAC_CMD_MODE_HASH 0x0008 -+#define HIFN_MAC_CMD_MODE_FULL 0x0004 -+#define HIFN_MAC_CMD_TRUNC 0x0010 -+#define HIFN_MAC_CMD_RESULT 0x0020 -+#define HIFN_MAC_CMD_APPEND 0x0040 -+#define HIFN_MAC_CMD_SRCLEN_M 0xc000 -+#define HIFN_MAC_CMD_SRCLEN_S 14 -+ -+/* -+ * MAC POS IPsec initiates authentication after encryption on encodes -+ * and before decryption on decodes. -+ */ -+#define HIFN_MAC_CMD_POS_IPSEC 0x0200 -+#define HIFN_MAC_CMD_NEW_KEY 0x0800 -+ -+/* -+ * The poll frequency and poll scalar defines are unshifted values used -+ * to set fields in the DMA Configuration Register. -+ */ -+#ifndef HIFN_POLL_FREQUENCY -+#define HIFN_POLL_FREQUENCY 0x1 -+#endif -+ -+#ifndef HIFN_POLL_SCALAR -+#define HIFN_POLL_SCALAR 0x0 -+#endif -+ -+#define HIFN_MAX_SEGLEN 0xffff /* maximum dma segment len */ -+#define HIFN_MAX_DMALEN 0x3ffff /* maximum dma length */ -+#endif /* __HIFN_H__ */ -diff -Nur linux-2.6.39.orig/crypto/ocf/hifn/hifn7751var.h linux-2.6.39/crypto/ocf/hifn/hifn7751var.h ---- linux-2.6.39.orig/crypto/ocf/hifn/hifn7751var.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/hifn/hifn7751var.h 2011-08-01 14:38:18.000000000 +0200 -@@ -0,0 +1,369 @@ -+/* $FreeBSD: src/sys/dev/hifn/hifn7751var.h,v 1.9 2007/03/21 03:42:49 sam Exp $ */ -+/* $OpenBSD: hifn7751var.h,v 1.42 2002/04/08 17:49:42 jason Exp $ */ -+ -+/*- -+ * Invertex AEON / Hifn 7751 driver -+ * Copyright (c) 1999 Invertex Inc. All rights reserved. -+ * Copyright (c) 1999 Theo de Raadt -+ * Copyright (c) 2000-2001 Network Security Technologies, Inc. -+ * http://www.netsec.net -+ * -+ * Please send any comments, feedback, bug-fixes, or feature requests to -+ * software@invertex.com. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored in part by the Defense Advanced Research Projects -+ * Agency (DARPA) and Air Force Research Laboratory, Air Force -+ * Materiel Command, USAF, under agreement number F30602-01-2-0537. -+ * -+ */ -+ -+#ifndef __HIFN7751VAR_H__ -+#define __HIFN7751VAR_H__ -+ -+#ifdef __KERNEL__ -+ -+/* -+ * Some configurable values for the driver. By default command+result -+ * descriptor rings are the same size. The src+dst descriptor rings -+ * are sized at 3.5x the number of potential commands. Slower parts -+ * (e.g. 7951) tend to run out of src descriptors; faster parts (7811) -+ * src+cmd/result descriptors. It's not clear that increasing the size -+ * of the descriptor rings helps performance significantly as other -+ * factors tend to come into play (e.g. copying misaligned packets). -+ */ -+#define HIFN_D_CMD_RSIZE 24 /* command descriptors */ -+#define HIFN_D_SRC_RSIZE ((HIFN_D_CMD_RSIZE * 7) / 2) /* source descriptors */ -+#define HIFN_D_RES_RSIZE HIFN_D_CMD_RSIZE /* result descriptors */ -+#define HIFN_D_DST_RSIZE HIFN_D_SRC_RSIZE /* destination descriptors */ -+ -+/* -+ * Length values for cryptography -+ */ -+#define HIFN_DES_KEY_LENGTH 8 -+#define HIFN_3DES_KEY_LENGTH 24 -+#define HIFN_MAX_CRYPT_KEY_LENGTH HIFN_3DES_KEY_LENGTH -+#define HIFN_IV_LENGTH 8 -+#define HIFN_AES_IV_LENGTH 16 -+#define HIFN_MAX_IV_LENGTH HIFN_AES_IV_LENGTH -+ -+/* -+ * Length values for authentication -+ */ -+#define HIFN_MAC_KEY_LENGTH 64 -+#define HIFN_MD5_LENGTH 16 -+#define HIFN_SHA1_LENGTH 20 -+#define HIFN_MAC_TRUNC_LENGTH 12 -+ -+#define MAX_SCATTER 64 -+ -+/* -+ * Data structure to hold all 4 rings and any other ring related data. -+ */ -+struct hifn_dma { -+ /* -+ * Descriptor rings. We add +1 to the size to accomidate the -+ * jump descriptor. -+ */ -+ struct hifn_desc cmdr[HIFN_D_CMD_RSIZE+1]; -+ struct hifn_desc srcr[HIFN_D_SRC_RSIZE+1]; -+ struct hifn_desc dstr[HIFN_D_DST_RSIZE+1]; -+ struct hifn_desc resr[HIFN_D_RES_RSIZE+1]; -+ -+ struct hifn_command *hifn_commands[HIFN_D_RES_RSIZE]; -+ -+ u_char command_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_COMMAND]; -+ u_char result_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_RESULT]; -+ u_int32_t slop[HIFN_D_CMD_RSIZE]; -+ -+ u_int64_t test_src, test_dst; -+ -+ /* -+ * Our current positions for insertion and removal from the desriptor -+ * rings. -+ */ -+ int cmdi, srci, dsti, resi; -+ volatile int cmdu, srcu, dstu, resu; -+ int cmdk, srck, dstk, resk; -+}; -+ -+struct hifn_session { -+ int hs_used; -+ int hs_mlen; -+ u_int8_t hs_iv[HIFN_MAX_IV_LENGTH]; -+}; -+ -+#define HIFN_RING_SYNC(sc, r, i, f) \ -+ /* DAVIDM bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, (f)) */ -+ -+#define HIFN_CMDR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), cmdr, (i), (f)) -+#define HIFN_RESR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), resr, (i), (f)) -+#define HIFN_SRCR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), srcr, (i), (f)) -+#define HIFN_DSTR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), dstr, (i), (f)) -+ -+#define HIFN_CMD_SYNC(sc, i, f) \ -+ /* DAVIDM bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, (f)) */ -+ -+#define HIFN_RES_SYNC(sc, i, f) \ -+ /* DAVIDM bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, (f)) */ -+ -+typedef int bus_size_t; -+ -+/* -+ * Holds data specific to a single HIFN board. -+ */ -+struct hifn_softc { -+ softc_device_decl sc_dev; -+ -+ struct pci_dev *sc_pcidev; /* PCI device pointer */ -+ spinlock_t sc_mtx; /* per-instance lock */ -+ -+ int sc_num; /* for multiple devs */ -+ -+ ocf_iomem_t sc_bar0; -+ bus_size_t sc_bar0_lastreg;/* bar0 last reg written */ -+ ocf_iomem_t sc_bar1; -+ bus_size_t sc_bar1_lastreg;/* bar1 last reg written */ -+ -+ int sc_irq; -+ -+ u_int32_t sc_dmaier; -+ u_int32_t sc_drammodel; /* 1=dram, 0=sram */ -+ u_int32_t sc_pllconfig; /* 7954/7955/7956 PLL config */ -+ -+ struct hifn_dma *sc_dma; -+ dma_addr_t sc_dma_physaddr;/* physical address of sc_dma */ -+ -+ int sc_dmansegs; -+ int32_t sc_cid; -+ int sc_maxses; -+ int sc_nsessions; -+ struct hifn_session *sc_sessions; -+ int sc_ramsize; -+ int sc_flags; -+#define HIFN_HAS_RNG 0x1 /* includes random number generator */ -+#define HIFN_HAS_PUBLIC 0x2 /* includes public key support */ -+#define HIFN_HAS_AES 0x4 /* includes AES support */ -+#define HIFN_IS_7811 0x8 /* Hifn 7811 part */ -+#define HIFN_IS_7956 0x10 /* Hifn 7956/7955 don't have SDRAM */ -+ -+ struct timer_list sc_tickto; /* for managing DMA */ -+ -+ int sc_rngfirst; -+ int sc_rnghz; /* RNG polling frequency */ -+ -+ int sc_c_busy; /* command ring busy */ -+ int sc_s_busy; /* source data ring busy */ -+ int sc_d_busy; /* destination data ring busy */ -+ int sc_r_busy; /* result ring busy */ -+ int sc_active; /* for initial countdown */ -+ int sc_needwakeup; /* ops q'd wating on resources */ -+ int sc_curbatch; /* # ops submitted w/o int */ -+ int sc_suspended; -+#ifdef HIFN_VULCANDEV -+ struct cdev *sc_pkdev; -+#endif -+}; -+ -+#define HIFN_LOCK(_sc) spin_lock_irqsave(&(_sc)->sc_mtx, l_flags) -+#define HIFN_UNLOCK(_sc) spin_unlock_irqrestore(&(_sc)->sc_mtx, l_flags) -+ -+/* -+ * hifn_command_t -+ * -+ * This is the control structure used to pass commands to hifn_encrypt(). -+ * -+ * flags -+ * ----- -+ * Flags is the bitwise "or" values for command configuration. A single -+ * encrypt direction needs to be set: -+ * -+ * HIFN_ENCODE or HIFN_DECODE -+ * -+ * To use cryptography, a single crypto algorithm must be included: -+ * -+ * HIFN_CRYPT_3DES or HIFN_CRYPT_DES -+ * -+ * To use authentication is used, a single MAC algorithm must be included: -+ * -+ * HIFN_MAC_MD5 or HIFN_MAC_SHA1 -+ * -+ * By default MD5 uses a 16 byte hash and SHA-1 uses a 20 byte hash. -+ * If the value below is set, hash values are truncated or assumed -+ * truncated to 12 bytes: -+ * -+ * HIFN_MAC_TRUNC -+ * -+ * Keys for encryption and authentication can be sent as part of a command, -+ * or the last key value used with a particular session can be retrieved -+ * and used again if either of these flags are not specified. -+ * -+ * HIFN_CRYPT_NEW_KEY, HIFN_MAC_NEW_KEY -+ * -+ * session_num -+ * ----------- -+ * A number between 0 and 2048 (for DRAM models) or a number between -+ * 0 and 768 (for SRAM models). Those who don't want to use session -+ * numbers should leave value at zero and send a new crypt key and/or -+ * new MAC key on every command. If you use session numbers and -+ * don't send a key with a command, the last key sent for that same -+ * session number will be used. -+ * -+ * Warning: Using session numbers and multiboard at the same time -+ * is currently broken. -+ * -+ * mbuf -+ * ---- -+ * Either fill in the mbuf pointer and npa=0 or -+ * fill packp[] and packl[] and set npa to > 0 -+ * -+ * mac_header_skip -+ * --------------- -+ * The number of bytes of the source_buf that are skipped over before -+ * authentication begins. This must be a number between 0 and 2^16-1 -+ * and can be used by IPsec implementers to skip over IP headers. -+ * *** Value ignored if authentication not used *** -+ * -+ * crypt_header_skip -+ * ----------------- -+ * The number of bytes of the source_buf that are skipped over before -+ * the cryptographic operation begins. This must be a number between 0 -+ * and 2^16-1. For IPsec, this number will always be 8 bytes larger -+ * than the auth_header_skip (to skip over the ESP header). -+ * *** Value ignored if cryptography not used *** -+ * -+ */ -+struct hifn_operand { -+ union { -+ struct sk_buff *skb; -+ struct uio *io; -+ unsigned char *buf; -+ } u; -+ void *map; -+ bus_size_t mapsize; -+ int nsegs; -+ struct { -+ dma_addr_t ds_addr; -+ int ds_len; -+ } segs[MAX_SCATTER]; -+}; -+ -+struct hifn_command { -+ u_int16_t session_num; -+ u_int16_t base_masks, cry_masks, mac_masks; -+ u_int8_t iv[HIFN_MAX_IV_LENGTH], *ck, mac[HIFN_MAC_KEY_LENGTH]; -+ int cklen; -+ int sloplen, slopidx; -+ -+ struct hifn_operand src; -+ struct hifn_operand dst; -+ -+ struct hifn_softc *softc; -+ struct cryptop *crp; -+ struct cryptodesc *enccrd, *maccrd; -+}; -+ -+#define src_skb src.u.skb -+#define src_io src.u.io -+#define src_map src.map -+#define src_mapsize src.mapsize -+#define src_segs src.segs -+#define src_nsegs src.nsegs -+#define src_buf src.u.buf -+ -+#define dst_skb dst.u.skb -+#define dst_io dst.u.io -+#define dst_map dst.map -+#define dst_mapsize dst.mapsize -+#define dst_segs dst.segs -+#define dst_nsegs dst.nsegs -+#define dst_buf dst.u.buf -+ -+/* -+ * Return values for hifn_crypto() -+ */ -+#define HIFN_CRYPTO_SUCCESS 0 -+#define HIFN_CRYPTO_BAD_INPUT (-1) -+#define HIFN_CRYPTO_RINGS_FULL (-2) -+ -+/************************************************************************** -+ * -+ * Function: hifn_crypto -+ * -+ * Purpose: Called by external drivers to begin an encryption on the -+ * HIFN board. -+ * -+ * Blocking/Non-blocking Issues -+ * ============================ -+ * The driver cannot block in hifn_crypto (no calls to tsleep) currently. -+ * hifn_crypto() returns HIFN_CRYPTO_RINGS_FULL if there is not enough -+ * room in any of the rings for the request to proceed. -+ * -+ * Return Values -+ * ============= -+ * 0 for success, negative values on error -+ * -+ * Defines for negative error codes are: -+ * -+ * HIFN_CRYPTO_BAD_INPUT : The passed in command had invalid settings. -+ * HIFN_CRYPTO_RINGS_FULL : All DMA rings were full and non-blocking -+ * behaviour was requested. -+ * -+ *************************************************************************/ -+ -+/* -+ * Convert back and forth from 'sid' to 'card' and 'session' -+ */ -+#define HIFN_CARD(sid) (((sid) & 0xf0000000) >> 28) -+#define HIFN_SESSION(sid) ((sid) & 0x000007ff) -+#define HIFN_SID(crd,ses) (((crd) << 28) | ((ses) & 0x7ff)) -+ -+#endif /* _KERNEL */ -+ -+struct hifn_stats { -+ u_int64_t hst_ibytes; -+ u_int64_t hst_obytes; -+ u_int32_t hst_ipackets; -+ u_int32_t hst_opackets; -+ u_int32_t hst_invalid; -+ u_int32_t hst_nomem; /* malloc or one of hst_nomem_* */ -+ u_int32_t hst_abort; -+ u_int32_t hst_noirq; /* IRQ for no reason */ -+ u_int32_t hst_totbatch; /* ops submitted w/o interrupt */ -+ u_int32_t hst_maxbatch; /* max ops submitted together */ -+ u_int32_t hst_unaligned; /* unaligned src caused copy */ -+ /* -+ * The following divides hst_nomem into more specific buckets. -+ */ -+ u_int32_t hst_nomem_map; /* bus_dmamap_create failed */ -+ u_int32_t hst_nomem_load; /* bus_dmamap_load_* failed */ -+ u_int32_t hst_nomem_mbuf; /* MGET* failed */ -+ u_int32_t hst_nomem_mcl; /* MCLGET* failed */ -+ u_int32_t hst_nomem_cr; /* out of command/result descriptor */ -+ u_int32_t hst_nomem_sd; /* out of src/dst descriptors */ -+}; -+ -+#endif /* __HIFN7751VAR_H__ */ -diff -Nur linux-2.6.39.orig/crypto/ocf/hifn/hifnHIPP.c linux-2.6.39/crypto/ocf/hifn/hifnHIPP.c ---- linux-2.6.39.orig/crypto/ocf/hifn/hifnHIPP.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/hifn/hifnHIPP.c 2011-08-01 14:38:18.000000000 +0200 -@@ -0,0 +1,420 @@ -+/*- -+ * Driver for Hifn HIPP-I/II chipset -+ * Copyright (c) 2006 Michael Richardson -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored by Hifn Inc. -+ * -+ */ -+ -+/* -+ * Driver for various Hifn encryption processors. -+ */ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "hifnHIPPreg.h" -+#include "hifnHIPPvar.h" -+ -+#if 1 -+#define DPRINTF(a...) if (hipp_debug) { \ -+ printk("%s: ", sc ? \ -+ device_get_nameunit(sc->sc_dev) : "hifn"); \ -+ printk(a); \ -+ } else -+#else -+#define DPRINTF(a...) -+#endif -+ -+typedef int bus_size_t; -+ -+static inline int -+pci_get_revid(struct pci_dev *dev) -+{ -+ u8 rid = 0; -+ pci_read_config_byte(dev, PCI_REVISION_ID, &rid); -+ return rid; -+} -+ -+#define debug hipp_debug -+int hipp_debug = 0; -+module_param(hipp_debug, int, 0644); -+MODULE_PARM_DESC(hipp_debug, "Enable debug"); -+ -+int hipp_maxbatch = 1; -+module_param(hipp_maxbatch, int, 0644); -+MODULE_PARM_DESC(hipp_maxbatch, "max ops to batch w/o interrupt"); -+ -+static int hipp_probe(struct pci_dev *dev, const struct pci_device_id *ent); -+static void hipp_remove(struct pci_dev *dev); -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) -+static irqreturn_t hipp_intr(int irq, void *arg); -+#else -+static irqreturn_t hipp_intr(int irq, void *arg, struct pt_regs *regs); -+#endif -+ -+static int hipp_num_chips = 0; -+static struct hipp_softc *hipp_chip_idx[HIPP_MAX_CHIPS]; -+ -+static int hipp_newsession(device_t, u_int32_t *, struct cryptoini *); -+static int hipp_freesession(device_t, u_int64_t); -+static int hipp_process(device_t, struct cryptop *, int); -+ -+static device_method_t hipp_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, hipp_newsession), -+ DEVMETHOD(cryptodev_freesession,hipp_freesession), -+ DEVMETHOD(cryptodev_process, hipp_process), -+}; -+ -+static __inline u_int32_t -+READ_REG(struct hipp_softc *sc, unsigned int barno, bus_size_t reg) -+{ -+ u_int32_t v = readl(sc->sc_bar[barno] + reg); -+ //sc->sc_bar0_lastreg = (bus_size_t) -1; -+ return (v); -+} -+static __inline void -+WRITE_REG(struct hipp_softc *sc, unsigned int barno, bus_size_t reg, u_int32_t val) -+{ -+ writel(val, sc->sc_bar[barno] + reg); -+} -+ -+#define READ_REG_0(sc, reg) READ_REG(sc, 0, reg) -+#define WRITE_REG_0(sc, reg, val) WRITE_REG(sc,0, reg, val) -+#define READ_REG_1(sc, reg) READ_REG(sc, 1, reg) -+#define WRITE_REG_1(sc, reg, val) WRITE_REG(sc,1, reg, val) -+ -+static int -+hipp_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) -+{ -+ return EINVAL; -+} -+ -+static int -+hipp_freesession(device_t dev, u_int64_t tid) -+{ -+ return EINVAL; -+} -+ -+static int -+hipp_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ return EINVAL; -+} -+ -+static const char* -+hipp_partname(struct hipp_softc *sc, char buf[128], size_t blen) -+{ -+ char *n = NULL; -+ -+ switch (pci_get_vendor(sc->sc_pcidev)) { -+ case PCI_VENDOR_HIFN: -+ switch (pci_get_device(sc->sc_pcidev)) { -+ case PCI_PRODUCT_HIFN_7855: n = "Hifn 7855"; -+ case PCI_PRODUCT_HIFN_8155: n = "Hifn 8155"; -+ case PCI_PRODUCT_HIFN_6500: n = "Hifn 6500"; -+ } -+ } -+ -+ if(n==NULL) { -+ snprintf(buf, blen, "VID=%02x,PID=%02x", -+ pci_get_vendor(sc->sc_pcidev), -+ pci_get_device(sc->sc_pcidev)); -+ } else { -+ buf[0]='\0'; -+ strncat(buf, n, blen); -+ } -+ return buf; -+} -+ -+struct hipp_fs_entry { -+ struct attribute attr; -+ /* other stuff */ -+}; -+ -+ -+static ssize_t -+cryptoid_show(struct device *dev, -+ struct device_attribute *attr, -+ char *buf) -+{ -+ struct hipp_softc *sc; -+ -+ sc = pci_get_drvdata(to_pci_dev (dev)); -+ return sprintf (buf, "%d\n", sc->sc_cid); -+} -+ -+struct device_attribute hipp_dev_cryptoid = __ATTR_RO(cryptoid); -+ -+/* -+ * Attach an interface that successfully probed. -+ */ -+static int -+hipp_probe(struct pci_dev *dev, const struct pci_device_id *ent) -+{ -+ struct hipp_softc *sc = NULL; -+ int i; -+ //char rbase; -+ //u_int16_t ena; -+ int rev; -+ //int rseg; -+ int rc; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (pci_enable_device(dev) < 0) -+ return(-ENODEV); -+ -+ if (pci_set_mwi(dev)) -+ return(-ENODEV); -+ -+ if (!dev->irq) { -+ printk("hifn: found device with no IRQ assigned. check BIOS settings!"); -+ pci_disable_device(dev); -+ return(-ENODEV); -+ } -+ -+ sc = (struct hipp_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); -+ if (!sc) -+ return(-ENOMEM); -+ memset(sc, 0, sizeof(*sc)); -+ -+ softc_device_init(sc, "hifn-hipp", hipp_num_chips, hipp_methods); -+ -+ sc->sc_pcidev = dev; -+ sc->sc_irq = -1; -+ sc->sc_cid = -1; -+ sc->sc_num = hipp_num_chips++; -+ -+ if (sc->sc_num < HIPP_MAX_CHIPS) -+ hipp_chip_idx[sc->sc_num] = sc; -+ -+ pci_set_drvdata(sc->sc_pcidev, sc); -+ -+ spin_lock_init(&sc->sc_mtx); -+ -+ /* -+ * Setup PCI resources. -+ * The READ_REG_0, WRITE_REG_0, READ_REG_1, -+ * and WRITE_REG_1 macros throughout the driver are used -+ * to permit better debugging. -+ */ -+ for(i=0; i<4; i++) { -+ unsigned long mem_start, mem_len; -+ mem_start = pci_resource_start(sc->sc_pcidev, i); -+ mem_len = pci_resource_len(sc->sc_pcidev, i); -+ sc->sc_barphy[i] = (caddr_t)mem_start; -+ sc->sc_bar[i] = (ocf_iomem_t) ioremap(mem_start, mem_len); -+ if (!sc->sc_bar[i]) { -+ device_printf(sc->sc_dev, "cannot map bar%d register space\n", i); -+ goto fail; -+ } -+ } -+ -+ //hipp_reset_board(sc, 0); -+ pci_set_master(sc->sc_pcidev); -+ -+ /* -+ * Arrange the interrupt line. -+ */ -+ rc = request_irq(dev->irq, hipp_intr, IRQF_SHARED, "hifn", sc); -+ if (rc) { -+ device_printf(sc->sc_dev, "could not map interrupt: %d\n", rc); -+ goto fail; -+ } -+ sc->sc_irq = dev->irq; -+ -+ rev = READ_REG_1(sc, HIPP_1_REVID) & 0xffff; -+ -+ { -+ char b[32]; -+ device_printf(sc->sc_dev, "%s, rev %u", -+ hipp_partname(sc, b, sizeof(b)), rev); -+ } -+ -+#if 0 -+ if (sc->sc_flags & HIFN_IS_7956) -+ printf(", pll=0x%x<%s clk, %ux mult>", -+ sc->sc_pllconfig, -+ sc->sc_pllconfig & HIFN_PLL_REF_SEL ? "ext" : "pci", -+ 2 + 2*((sc->sc_pllconfig & HIFN_PLL_ND) >> 11)); -+#endif -+ printf("\n"); -+ -+ sc->sc_cid = crypto_get_driverid(softc_get_device(sc),CRYPTOCAP_F_HARDWARE); -+ if (sc->sc_cid < 0) { -+ device_printf(sc->sc_dev, "could not get crypto driver id\n"); -+ goto fail; -+ } -+ -+#if 0 /* cannot work with a non-GPL module */ -+ /* make a sysfs entry to let the world know what entry we got */ -+ sysfs_create_file(&sc->sc_pcidev->dev.kobj, &hipp_dev_cryptoid.attr); -+#endif -+ -+#if 0 -+ init_timer(&sc->sc_tickto); -+ sc->sc_tickto.function = hifn_tick; -+ sc->sc_tickto.data = (unsigned long) sc->sc_num; -+ mod_timer(&sc->sc_tickto, jiffies + HZ); -+#endif -+ -+#if 0 /* no code here yet ?? */ -+ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); -+#endif -+ -+ return (0); -+ -+fail: -+ if (sc->sc_cid >= 0) -+ crypto_unregister_all(sc->sc_cid); -+ if (sc->sc_irq != -1) -+ free_irq(sc->sc_irq, sc); -+ -+#if 0 -+ if (sc->sc_dma) { -+ /* Turn off DMA polling */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | -+ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); -+ -+ pci_free_consistent(sc->sc_pcidev, -+ sizeof(*sc->sc_dma), -+ sc->sc_dma, sc->sc_dma_physaddr); -+ } -+#endif -+ kfree(sc); -+ return (-ENXIO); -+} -+ -+/* -+ * Detach an interface that successfully probed. -+ */ -+static void -+hipp_remove(struct pci_dev *dev) -+{ -+ struct hipp_softc *sc = pci_get_drvdata(dev); -+ unsigned long l_flags; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ /* disable interrupts */ -+ HIPP_LOCK(sc); -+ -+#if 0 -+ WRITE_REG_1(sc, HIFN_1_DMA_IER, 0); -+ HIFN_UNLOCK(sc); -+ -+ /*XXX other resources */ -+ del_timer_sync(&sc->sc_tickto); -+ -+ /* Turn off DMA polling */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | -+ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); -+#endif -+ -+ crypto_unregister_all(sc->sc_cid); -+ -+ free_irq(sc->sc_irq, sc); -+ -+#if 0 -+ pci_free_consistent(sc->sc_pcidev, sizeof(*sc->sc_dma), -+ sc->sc_dma, sc->sc_dma_physaddr); -+#endif -+} -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) -+static irqreturn_t hipp_intr(int irq, void *arg) -+#else -+static irqreturn_t hipp_intr(int irq, void *arg, struct pt_regs *regs) -+#endif -+{ -+ struct hipp_softc *sc = arg; -+ -+ sc = sc; /* shut up compiler */ -+ -+ return IRQ_HANDLED; -+} -+ -+static struct pci_device_id hipp_pci_tbl[] = { -+ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7855, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_8155, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+}; -+MODULE_DEVICE_TABLE(pci, hipp_pci_tbl); -+ -+static struct pci_driver hipp_driver = { -+ .name = "hipp", -+ .id_table = hipp_pci_tbl, -+ .probe = hipp_probe, -+ .remove = hipp_remove, -+ /* add PM stuff here one day */ -+}; -+ -+static int __init hipp_init (void) -+{ -+ struct hipp_softc *sc = NULL; -+ int rc; -+ -+ DPRINTF("%s(%p)\n", __FUNCTION__, hipp_init); -+ -+ rc = pci_register_driver(&hipp_driver); -+ pci_register_driver_compat(&hipp_driver, rc); -+ -+ return rc; -+} -+ -+static void __exit hipp_exit (void) -+{ -+ pci_unregister_driver(&hipp_driver); -+} -+ -+module_init(hipp_init); -+module_exit(hipp_exit); -+ -+MODULE_LICENSE("BSD"); -+MODULE_AUTHOR("Michael Richardson "); -+MODULE_DESCRIPTION("OCF driver for hifn HIPP-I/II PCI crypto devices"); -diff -Nur linux-2.6.39.orig/crypto/ocf/hifn/hifnHIPPreg.h linux-2.6.39/crypto/ocf/hifn/hifnHIPPreg.h ---- linux-2.6.39.orig/crypto/ocf/hifn/hifnHIPPreg.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/hifn/hifnHIPPreg.h 2011-08-01 14:38:18.000000000 +0200 -@@ -0,0 +1,46 @@ -+/*- -+ * Hifn HIPP-I/HIPP-II (7855/8155) driver. -+ * Copyright (c) 2006 Michael Richardson -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored by Hifn inc. -+ * -+ */ -+ -+#ifndef __HIFNHIPP_H__ -+#define __HIFNHIPP_H__ -+ -+/* -+ * PCI vendor and device identifiers -+ */ -+#define PCI_VENDOR_HIFN 0x13a3 /* Hifn */ -+#define PCI_PRODUCT_HIFN_6500 0x0006 /* 6500 */ -+#define PCI_PRODUCT_HIFN_7855 0x001f /* 7855 */ -+#define PCI_PRODUCT_HIFN_8155 0x999 /* XXX 8155 */ -+ -+#define HIPP_1_REVID 0x01 /* BOGUS */ -+ -+#endif /* __HIPP_H__ */ -diff -Nur linux-2.6.39.orig/crypto/ocf/hifn/hifnHIPPvar.h linux-2.6.39/crypto/ocf/hifn/hifnHIPPvar.h ---- linux-2.6.39.orig/crypto/ocf/hifn/hifnHIPPvar.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/hifn/hifnHIPPvar.h 2011-08-01 14:38:18.000000000 +0200 -@@ -0,0 +1,93 @@ -+/* -+ * Hifn HIPP-I/HIPP-II (7855/8155) driver. -+ * Copyright (c) 2006 Michael Richardson * -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored by Hifn inc. -+ * -+ */ -+ -+#ifndef __HIFNHIPPVAR_H__ -+#define __HIFNHIPPVAR_H__ -+ -+#define HIPP_MAX_CHIPS 8 -+ -+/* -+ * Holds data specific to a single Hifn HIPP-I board. -+ */ -+struct hipp_softc { -+ softc_device_decl sc_dev; -+ -+ struct pci_dev *sc_pcidev; /* device backpointer */ -+ ocf_iomem_t sc_bar[5]; -+ caddr_t sc_barphy[5]; /* physical address */ -+ int sc_num; /* for multiple devs */ -+ spinlock_t sc_mtx; /* per-instance lock */ -+ int32_t sc_cid; -+ int sc_irq; -+ -+#if 0 -+ -+ u_int32_t sc_dmaier; -+ u_int32_t sc_drammodel; /* 1=dram, 0=sram */ -+ u_int32_t sc_pllconfig; /* 7954/7955/7956 PLL config */ -+ -+ struct hifn_dma *sc_dma; -+ dma_addr_t sc_dma_physaddr;/* physical address of sc_dma */ -+ -+ int sc_dmansegs; -+ int sc_maxses; -+ int sc_nsessions; -+ struct hifn_session *sc_sessions; -+ int sc_ramsize; -+ int sc_flags; -+#define HIFN_HAS_RNG 0x1 /* includes random number generator */ -+#define HIFN_HAS_PUBLIC 0x2 /* includes public key support */ -+#define HIFN_HAS_AES 0x4 /* includes AES support */ -+#define HIFN_IS_7811 0x8 /* Hifn 7811 part */ -+#define HIFN_IS_7956 0x10 /* Hifn 7956/7955 don't have SDRAM */ -+ -+ struct timer_list sc_tickto; /* for managing DMA */ -+ -+ int sc_rngfirst; -+ int sc_rnghz; /* RNG polling frequency */ -+ -+ int sc_c_busy; /* command ring busy */ -+ int sc_s_busy; /* source data ring busy */ -+ int sc_d_busy; /* destination data ring busy */ -+ int sc_r_busy; /* result ring busy */ -+ int sc_active; /* for initial countdown */ -+ int sc_needwakeup; /* ops q'd wating on resources */ -+ int sc_curbatch; /* # ops submitted w/o int */ -+ int sc_suspended; -+ struct miscdevice sc_miscdev; -+#endif -+}; -+ -+#define HIPP_LOCK(_sc) spin_lock_irqsave(&(_sc)->sc_mtx, l_flags) -+#define HIPP_UNLOCK(_sc) spin_unlock_irqrestore(&(_sc)->sc_mtx, l_flags) -+ -+#endif /* __HIFNHIPPVAR_H__ */ -diff -Nur linux-2.6.39.orig/crypto/ocf/ixp4xx/Makefile linux-2.6.39/crypto/ocf/ixp4xx/Makefile ---- linux-2.6.39.orig/crypto/ocf/ixp4xx/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/ixp4xx/Makefile 2011-08-01 14:38:18.000000000 +0200 -@@ -0,0 +1,104 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+# -+# You will need to point this at your Intel ixp425 includes, this portion -+# of the Makefile only really works under SGLinux with the appropriate libs -+# installed. They can be downloaded from http://www.snapgear.org/ -+# -+ifeq ($(CONFIG_CPU_IXP46X),y) -+IXPLATFORM = ixp46X -+else -+ifeq ($(CONFIG_CPU_IXP43X),y) -+IXPLATFORM = ixp43X -+else -+IXPLATFORM = ixp42X -+endif -+endif -+ -+ifdef CONFIG_IXP400_LIB_2_4 -+IX_XSCALE_SW = $(ROOTDIR)/modules/ixp425/ixp400-2.4/ixp400_xscale_sw -+OSAL_DIR = $(ROOTDIR)/modules/ixp425/ixp400-2.4/ixp_osal -+endif -+ifdef CONFIG_IXP400_LIB_2_1 -+IX_XSCALE_SW = $(ROOTDIR)/modules/ixp425/ixp400-2.1/ixp400_xscale_sw -+OSAL_DIR = $(ROOTDIR)/modules/ixp425/ixp400-2.1/ixp_osal -+endif -+ifdef CONFIG_IXP400_LIB_2_0 -+IX_XSCALE_SW = $(ROOTDIR)/modules/ixp425/ixp400-2.0/ixp400_xscale_sw -+OSAL_DIR = $(ROOTDIR)/modules/ixp425/ixp400-2.0/ixp_osal -+endif -+ifdef IX_XSCALE_SW -+ifdef CONFIG_IXP400_LIB_2_4 -+IXP_CFLAGS = \ -+ -I$(ROOTDIR)/. \ -+ -I$(IX_XSCALE_SW)/src/include \ -+ -I$(OSAL_DIR)/common/include/ \ -+ -I$(OSAL_DIR)/common/include/modules/ \ -+ -I$(OSAL_DIR)/common/include/modules/ddk/ \ -+ -I$(OSAL_DIR)/common/include/modules/bufferMgt/ \ -+ -I$(OSAL_DIR)/common/include/modules/ioMem/ \ -+ -I$(OSAL_DIR)/common/os/linux/include/ \ -+ -I$(OSAL_DIR)/common/os/linux/include/core/ \ -+ -I$(OSAL_DIR)/common/os/linux/include/modules/ \ -+ -I$(OSAL_DIR)/common/os/linux/include/modules/ddk/ \ -+ -I$(OSAL_DIR)/common/os/linux/include/modules/bufferMgt/ \ -+ -I$(OSAL_DIR)/common/os/linux/include/modules/ioMem/ \ -+ -I$(OSAL_DIR)/platforms/$(IXPLATFORM)/include/ \ -+ -I$(OSAL_DIR)/platforms/$(IXPLATFORM)/os/linux/include/ \ -+ -DENABLE_IOMEM -DENABLE_BUFFERMGT -DENABLE_DDK \ -+ -DUSE_IXP4XX_CRYPTO -+else -+IXP_CFLAGS = \ -+ -I$(ROOTDIR)/. \ -+ -I$(IX_XSCALE_SW)/src/include \ -+ -I$(OSAL_DIR)/ \ -+ -I$(OSAL_DIR)/os/linux/include/ \ -+ -I$(OSAL_DIR)/os/linux/include/modules/ \ -+ -I$(OSAL_DIR)/os/linux/include/modules/ioMem/ \ -+ -I$(OSAL_DIR)/os/linux/include/modules/bufferMgt/ \ -+ -I$(OSAL_DIR)/os/linux/include/core/ \ -+ -I$(OSAL_DIR)/os/linux/include/platforms/ \ -+ -I$(OSAL_DIR)/os/linux/include/platforms/ixp400/ \ -+ -I$(OSAL_DIR)/os/linux/include/platforms/ixp400/ixp425 \ -+ -I$(OSAL_DIR)/os/linux/include/platforms/ixp400/ixp465 \ -+ -I$(OSAL_DIR)/os/linux/include/core/ \ -+ -I$(OSAL_DIR)/include/ \ -+ -I$(OSAL_DIR)/include/modules/ \ -+ -I$(OSAL_DIR)/include/modules/bufferMgt/ \ -+ -I$(OSAL_DIR)/include/modules/ioMem/ \ -+ -I$(OSAL_DIR)/include/platforms/ \ -+ -I$(OSAL_DIR)/include/platforms/ixp400/ \ -+ -DUSE_IXP4XX_CRYPTO -+endif -+endif -+ifdef CONFIG_IXP400_LIB_1_4 -+IXP_CFLAGS = \ -+ -I$(ROOTDIR)/. \ -+ -I$(ROOTDIR)/modules/ixp425/ixp400-1.4/ixp400_xscale_sw/src/include \ -+ -I$(ROOTDIR)/modules/ixp425/ixp400-1.4/ixp400_xscale_sw/src/linux \ -+ -DUSE_IXP4XX_CRYPTO -+endif -+ifndef IXPDIR -+IXPDIR = ixp-version-is-not-supported -+endif -+ -+ifeq ($(CONFIG_CPU_IXP46X),y) -+IXP_CFLAGS += -D__ixp46X -+else -+ifeq ($(CONFIG_CPU_IXP43X),y) -+IXP_CFLAGS += -D__ixp43X -+else -+IXP_CFLAGS += -D__ixp42X -+endif -+endif -+ -+obj-$(CONFIG_OCF_IXP4XX) += ixp4xx.o -+ -+obj ?= . -+EXTRA_CFLAGS += $(IXP_CFLAGS) -I$(obj)/.. -I$(obj)/. -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/ixp4xx/ixp4xx.c linux-2.6.39/crypto/ocf/ixp4xx/ixp4xx.c ---- linux-2.6.39.orig/crypto/ocf/ixp4xx/ixp4xx.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/ixp4xx/ixp4xx.c 2011-08-01 14:38:18.000000000 +0200 -@@ -0,0 +1,1324 @@ -+/* -+ * An OCF module that uses Intels IXP CryptACC API to do the crypto. -+ * This driver requires the IXP400 Access Library that is available -+ * from Intel in order to operate (or compile). -+ * -+ * Written by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * ALTERNATIVELY, provided that this notice is retained in full, this product -+ * may be distributed under the terms of the GNU General Public License (GPL), -+ * in which case the provisions of the GPL apply INSTEAD OF those given above. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ */ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#ifndef IX_MBUF_PRIV -+#define IX_MBUF_PRIV(x) ((x)->priv) -+#endif -+ -+struct ixp_data; -+ -+struct ixp_q { -+ struct list_head ixp_q_list; -+ struct ixp_data *ixp_q_data; -+ struct cryptop *ixp_q_crp; -+ struct cryptodesc *ixp_q_ccrd; -+ struct cryptodesc *ixp_q_acrd; -+ IX_MBUF ixp_q_mbuf; -+ UINT8 *ixp_hash_dest; /* Location for hash in client buffer */ -+ UINT8 *ixp_hash_src; /* Location of hash in internal buffer */ -+ unsigned char ixp_q_iv_data[IX_CRYPTO_ACC_MAX_CIPHER_IV_LENGTH]; -+ unsigned char *ixp_q_iv; -+}; -+ -+struct ixp_data { -+ int ixp_registered; /* is the context registered */ -+ int ixp_crd_flags; /* detect direction changes */ -+ -+ int ixp_cipher_alg; -+ int ixp_auth_alg; -+ -+ UINT32 ixp_ctx_id; -+ UINT32 ixp_hash_key_id; /* used when hashing */ -+ IxCryptoAccCtx ixp_ctx; -+ IX_MBUF ixp_pri_mbuf; -+ IX_MBUF ixp_sec_mbuf; -+ -+ struct work_struct ixp_pending_work; -+ struct work_struct ixp_registration_work; -+ struct list_head ixp_q; /* unprocessed requests */ -+}; -+ -+#ifdef __ixp46X -+ -+#define MAX_IOP_SIZE 64 /* words */ -+#define MAX_OOP_SIZE 128 -+ -+#define MAX_PARAMS 3 -+ -+struct ixp_pkq { -+ struct list_head pkq_list; -+ struct cryptkop *pkq_krp; -+ -+ IxCryptoAccPkeEauInOperands pkq_op; -+ IxCryptoAccPkeEauOpResult pkq_result; -+ -+ UINT32 pkq_ibuf0[MAX_IOP_SIZE]; -+ UINT32 pkq_ibuf1[MAX_IOP_SIZE]; -+ UINT32 pkq_ibuf2[MAX_IOP_SIZE]; -+ UINT32 pkq_obuf[MAX_OOP_SIZE]; -+}; -+ -+static LIST_HEAD(ixp_pkq); /* current PK wait list */ -+static struct ixp_pkq *ixp_pk_cur; -+static spinlock_t ixp_pkq_lock; -+ -+#endif /* __ixp46X */ -+ -+static int ixp_blocked = 0; -+ -+static int32_t ixp_id = -1; -+static struct ixp_data **ixp_sessions = NULL; -+static u_int32_t ixp_sesnum = 0; -+ -+static int ixp_process(device_t, struct cryptop *, int); -+static int ixp_newsession(device_t, u_int32_t *, struct cryptoini *); -+static int ixp_freesession(device_t, u_int64_t); -+#ifdef __ixp46X -+static int ixp_kprocess(device_t, struct cryptkop *krp, int hint); -+#endif -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) -+static kmem_cache_t *qcache; -+#else -+static struct kmem_cache *qcache; -+#endif -+ -+#define debug ixp_debug -+static int ixp_debug = 0; -+module_param(ixp_debug, int, 0644); -+MODULE_PARM_DESC(ixp_debug, "Enable debug"); -+ -+static int ixp_init_crypto = 1; -+module_param(ixp_init_crypto, int, 0444); /* RO after load/boot */ -+MODULE_PARM_DESC(ixp_init_crypto, "Call ixCryptoAccInit (default is 1)"); -+ -+static void ixp_process_pending(void *arg); -+static void ixp_registration(void *arg); -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void ixp_process_pending_wq(struct work_struct *work); -+static void ixp_registration_wq(struct work_struct *work); -+#endif -+ -+/* -+ * dummy device structure -+ */ -+ -+static struct { -+ softc_device_decl sc_dev; -+} ixpdev; -+ -+static device_method_t ixp_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, ixp_newsession), -+ DEVMETHOD(cryptodev_freesession,ixp_freesession), -+ DEVMETHOD(cryptodev_process, ixp_process), -+#ifdef __ixp46X -+ DEVMETHOD(cryptodev_kprocess, ixp_kprocess), -+#endif -+}; -+ -+/* -+ * Generate a new software session. -+ */ -+static int -+ixp_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) -+{ -+ struct ixp_data *ixp; -+ u_int32_t i; -+#define AUTH_LEN(cri, def) \ -+ (cri->cri_mlen ? cri->cri_mlen : (def)) -+ -+ dprintk("%s():alg %d\n", __FUNCTION__,cri->cri_alg); -+ if (sid == NULL || cri == NULL) { -+ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ if (ixp_sessions) { -+ for (i = 1; i < ixp_sesnum; i++) -+ if (ixp_sessions[i] == NULL) -+ break; -+ } else -+ i = 1; /* NB: to silence compiler warning */ -+ -+ if (ixp_sessions == NULL || i == ixp_sesnum) { -+ struct ixp_data **ixpd; -+ -+ if (ixp_sessions == NULL) { -+ i = 1; /* We leave ixp_sessions[0] empty */ -+ ixp_sesnum = CRYPTO_SW_SESSIONS; -+ } else -+ ixp_sesnum *= 2; -+ -+ ixpd = kmalloc(ixp_sesnum * sizeof(struct ixp_data *), SLAB_ATOMIC); -+ if (ixpd == NULL) { -+ /* Reset session number */ -+ if (ixp_sesnum == CRYPTO_SW_SESSIONS) -+ ixp_sesnum = 0; -+ else -+ ixp_sesnum /= 2; -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memset(ixpd, 0, ixp_sesnum * sizeof(struct ixp_data *)); -+ -+ /* Copy existing sessions */ -+ if (ixp_sessions) { -+ memcpy(ixpd, ixp_sessions, -+ (ixp_sesnum / 2) * sizeof(struct ixp_data *)); -+ kfree(ixp_sessions); -+ } -+ -+ ixp_sessions = ixpd; -+ } -+ -+ ixp_sessions[i] = (struct ixp_data *) kmalloc(sizeof(struct ixp_data), -+ SLAB_ATOMIC); -+ if (ixp_sessions[i] == NULL) { -+ ixp_freesession(NULL, i); -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ -+ *sid = i; -+ -+ ixp = ixp_sessions[i]; -+ memset(ixp, 0, sizeof(*ixp)); -+ -+ ixp->ixp_cipher_alg = -1; -+ ixp->ixp_auth_alg = -1; -+ ixp->ixp_ctx_id = -1; -+ INIT_LIST_HEAD(&ixp->ixp_q); -+ -+ ixp->ixp_ctx.useDifferentSrcAndDestMbufs = 0; -+ -+ while (cri) { -+ switch (cri->cri_alg) { -+ case CRYPTO_DES_CBC: -+ ixp->ixp_cipher_alg = cri->cri_alg; -+ ixp->ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_DES; -+ ixp->ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; -+ ixp->ixp_ctx.cipherCtx.cipherKeyLen = (cri->cri_klen + 7) / 8; -+ ixp->ixp_ctx.cipherCtx.cipherBlockLen = IX_CRYPTO_ACC_DES_BLOCK_64; -+ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen = -+ IX_CRYPTO_ACC_DES_IV_64; -+ memcpy(ixp->ixp_ctx.cipherCtx.key.cipherKey, -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ break; -+ -+ case CRYPTO_3DES_CBC: -+ ixp->ixp_cipher_alg = cri->cri_alg; -+ ixp->ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_3DES; -+ ixp->ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; -+ ixp->ixp_ctx.cipherCtx.cipherKeyLen = (cri->cri_klen + 7) / 8; -+ ixp->ixp_ctx.cipherCtx.cipherBlockLen = IX_CRYPTO_ACC_DES_BLOCK_64; -+ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen = -+ IX_CRYPTO_ACC_DES_IV_64; -+ memcpy(ixp->ixp_ctx.cipherCtx.key.cipherKey, -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ break; -+ -+ case CRYPTO_RIJNDAEL128_CBC: -+ ixp->ixp_cipher_alg = cri->cri_alg; -+ ixp->ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_AES; -+ ixp->ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; -+ ixp->ixp_ctx.cipherCtx.cipherKeyLen = (cri->cri_klen + 7) / 8; -+ ixp->ixp_ctx.cipherCtx.cipherBlockLen = 16; -+ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen = 16; -+ memcpy(ixp->ixp_ctx.cipherCtx.key.cipherKey, -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ break; -+ -+ case CRYPTO_MD5: -+ case CRYPTO_MD5_HMAC: -+ ixp->ixp_auth_alg = cri->cri_alg; -+ ixp->ixp_ctx.authCtx.authAlgo = IX_CRYPTO_ACC_AUTH_MD5; -+ ixp->ixp_ctx.authCtx.authDigestLen = AUTH_LEN(cri, MD5_HASH_LEN); -+ ixp->ixp_ctx.authCtx.aadLen = 0; -+ /* Only MD5_HMAC needs a key */ -+ if (cri->cri_alg == CRYPTO_MD5_HMAC) { -+ ixp->ixp_ctx.authCtx.authKeyLen = (cri->cri_klen + 7) / 8; -+ if (ixp->ixp_ctx.authCtx.authKeyLen > -+ sizeof(ixp->ixp_ctx.authCtx.key.authKey)) { -+ printk( -+ "ixp4xx: Invalid key length for MD5_HMAC - %d bits\n", -+ cri->cri_klen); -+ ixp_freesession(NULL, i); -+ return EINVAL; -+ } -+ memcpy(ixp->ixp_ctx.authCtx.key.authKey, -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ } -+ break; -+ -+ case CRYPTO_SHA1: -+ case CRYPTO_SHA1_HMAC: -+ ixp->ixp_auth_alg = cri->cri_alg; -+ ixp->ixp_ctx.authCtx.authAlgo = IX_CRYPTO_ACC_AUTH_SHA1; -+ ixp->ixp_ctx.authCtx.authDigestLen = AUTH_LEN(cri, SHA1_HASH_LEN); -+ ixp->ixp_ctx.authCtx.aadLen = 0; -+ /* Only SHA1_HMAC needs a key */ -+ if (cri->cri_alg == CRYPTO_SHA1_HMAC) { -+ ixp->ixp_ctx.authCtx.authKeyLen = (cri->cri_klen + 7) / 8; -+ if (ixp->ixp_ctx.authCtx.authKeyLen > -+ sizeof(ixp->ixp_ctx.authCtx.key.authKey)) { -+ printk( -+ "ixp4xx: Invalid key length for SHA1_HMAC - %d bits\n", -+ cri->cri_klen); -+ ixp_freesession(NULL, i); -+ return EINVAL; -+ } -+ memcpy(ixp->ixp_ctx.authCtx.key.authKey, -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ } -+ break; -+ -+ default: -+ printk("ixp: unknown algo 0x%x\n", cri->cri_alg); -+ ixp_freesession(NULL, i); -+ return EINVAL; -+ } -+ cri = cri->cri_next; -+ } -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ INIT_WORK(&ixp->ixp_pending_work, ixp_process_pending_wq); -+ INIT_WORK(&ixp->ixp_registration_work, ixp_registration_wq); -+#else -+ INIT_WORK(&ixp->ixp_pending_work, ixp_process_pending, ixp); -+ INIT_WORK(&ixp->ixp_registration_work, ixp_registration, ixp); -+#endif -+ -+ return 0; -+} -+ -+ -+/* -+ * Free a session. -+ */ -+static int -+ixp_freesession(device_t dev, u_int64_t tid) -+{ -+ u_int32_t sid = CRYPTO_SESID2LID(tid); -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid > ixp_sesnum || ixp_sessions == NULL || -+ ixp_sessions[sid] == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ /* Silently accept and return */ -+ if (sid == 0) -+ return 0; -+ -+ if (ixp_sessions[sid]) { -+ if (ixp_sessions[sid]->ixp_ctx_id != -1) { -+ ixCryptoAccCtxUnregister(ixp_sessions[sid]->ixp_ctx_id); -+ ixp_sessions[sid]->ixp_ctx_id = -1; -+ } -+ kfree(ixp_sessions[sid]); -+ } -+ ixp_sessions[sid] = NULL; -+ if (ixp_blocked) { -+ ixp_blocked = 0; -+ crypto_unblock(ixp_id, CRYPTO_SYMQ); -+ } -+ return 0; -+} -+ -+ -+/* -+ * callback for when hash processing is complete -+ */ -+ -+static void -+ixp_hash_perform_cb( -+ UINT32 hash_key_id, -+ IX_MBUF *bufp, -+ IxCryptoAccStatus status) -+{ -+ struct ixp_q *q; -+ -+ dprintk("%s(%u, %p, 0x%x)\n", __FUNCTION__, hash_key_id, bufp, status); -+ -+ if (bufp == NULL) { -+ printk("ixp: NULL buf in %s\n", __FUNCTION__); -+ return; -+ } -+ -+ q = IX_MBUF_PRIV(bufp); -+ if (q == NULL) { -+ printk("ixp: NULL priv in %s\n", __FUNCTION__); -+ return; -+ } -+ -+ if (status == IX_CRYPTO_ACC_STATUS_SUCCESS) { -+ /* On success, need to copy hash back into original client buffer */ -+ memcpy(q->ixp_hash_dest, q->ixp_hash_src, -+ (q->ixp_q_data->ixp_auth_alg == CRYPTO_SHA1) ? -+ SHA1_HASH_LEN : MD5_HASH_LEN); -+ } -+ else { -+ printk("ixp: hash perform failed status=%d\n", status); -+ q->ixp_q_crp->crp_etype = EINVAL; -+ } -+ -+ /* Free internal buffer used for hashing */ -+ kfree(IX_MBUF_MDATA(&q->ixp_q_mbuf)); -+ -+ crypto_done(q->ixp_q_crp); -+ kmem_cache_free(qcache, q); -+} -+ -+/* -+ * setup a request and perform it -+ */ -+static void -+ixp_q_process(struct ixp_q *q) -+{ -+ IxCryptoAccStatus status; -+ struct ixp_data *ixp = q->ixp_q_data; -+ int auth_off = 0; -+ int auth_len = 0; -+ int crypt_off = 0; -+ int crypt_len = 0; -+ int icv_off = 0; -+ char *crypt_func; -+ -+ dprintk("%s(%p)\n", __FUNCTION__, q); -+ -+ if (q->ixp_q_ccrd) { -+ if (q->ixp_q_ccrd->crd_flags & CRD_F_IV_EXPLICIT) { -+ q->ixp_q_iv = q->ixp_q_ccrd->crd_iv; -+ } else { -+ q->ixp_q_iv = q->ixp_q_iv_data; -+ crypto_copydata(q->ixp_q_crp->crp_flags, q->ixp_q_crp->crp_buf, -+ q->ixp_q_ccrd->crd_inject, -+ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen, -+ (caddr_t) q->ixp_q_iv); -+ } -+ -+ if (q->ixp_q_acrd) { -+ auth_off = q->ixp_q_acrd->crd_skip; -+ auth_len = q->ixp_q_acrd->crd_len; -+ icv_off = q->ixp_q_acrd->crd_inject; -+ } -+ -+ crypt_off = q->ixp_q_ccrd->crd_skip; -+ crypt_len = q->ixp_q_ccrd->crd_len; -+ } else { /* if (q->ixp_q_acrd) */ -+ auth_off = q->ixp_q_acrd->crd_skip; -+ auth_len = q->ixp_q_acrd->crd_len; -+ icv_off = q->ixp_q_acrd->crd_inject; -+ } -+ -+ if (q->ixp_q_crp->crp_flags & CRYPTO_F_SKBUF) { -+ struct sk_buff *skb = (struct sk_buff *) q->ixp_q_crp->crp_buf; -+ if (skb_shinfo(skb)->nr_frags) { -+ /* -+ * DAVIDM fix this limitation one day by using -+ * a buffer pool and chaining, it is not currently -+ * needed for current user/kernel space acceleration -+ */ -+ printk("ixp: Cannot handle fragmented skb's yet !\n"); -+ q->ixp_q_crp->crp_etype = ENOENT; -+ goto done; -+ } -+ IX_MBUF_MLEN(&q->ixp_q_mbuf) = -+ IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = skb->len; -+ IX_MBUF_MDATA(&q->ixp_q_mbuf) = skb->data; -+ } else if (q->ixp_q_crp->crp_flags & CRYPTO_F_IOV) { -+ struct uio *uiop = (struct uio *) q->ixp_q_crp->crp_buf; -+ if (uiop->uio_iovcnt != 1) { -+ /* -+ * DAVIDM fix this limitation one day by using -+ * a buffer pool and chaining, it is not currently -+ * needed for current user/kernel space acceleration -+ */ -+ printk("ixp: Cannot handle more than 1 iovec yet !\n"); -+ q->ixp_q_crp->crp_etype = ENOENT; -+ goto done; -+ } -+ IX_MBUF_MLEN(&q->ixp_q_mbuf) = -+ IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = uiop->uio_iov[0].iov_len; -+ IX_MBUF_MDATA(&q->ixp_q_mbuf) = uiop->uio_iov[0].iov_base; -+ } else /* contig buffer */ { -+ IX_MBUF_MLEN(&q->ixp_q_mbuf) = -+ IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = q->ixp_q_crp->crp_ilen; -+ IX_MBUF_MDATA(&q->ixp_q_mbuf) = q->ixp_q_crp->crp_buf; -+ } -+ -+ IX_MBUF_PRIV(&q->ixp_q_mbuf) = q; -+ -+ if (ixp->ixp_auth_alg == CRYPTO_SHA1 || ixp->ixp_auth_alg == CRYPTO_MD5) { -+ /* -+ * For SHA1 and MD5 hash, need to create an internal buffer that is big -+ * enough to hold the original data + the appropriate padding for the -+ * hash algorithm. -+ */ -+ UINT8 *tbuf = NULL; -+ -+ IX_MBUF_MLEN(&q->ixp_q_mbuf) = IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = -+ ((IX_MBUF_MLEN(&q->ixp_q_mbuf) * 8) + 72 + 511) / 8; -+ tbuf = kmalloc(IX_MBUF_MLEN(&q->ixp_q_mbuf), SLAB_ATOMIC); -+ -+ if (IX_MBUF_MDATA(&q->ixp_q_mbuf) == NULL) { -+ printk("ixp: kmalloc(%u, SLAB_ATOMIC) failed\n", -+ IX_MBUF_MLEN(&q->ixp_q_mbuf)); -+ q->ixp_q_crp->crp_etype = ENOMEM; -+ goto done; -+ } -+ memcpy(tbuf, &(IX_MBUF_MDATA(&q->ixp_q_mbuf))[auth_off], auth_len); -+ -+ /* Set location in client buffer to copy hash into */ -+ q->ixp_hash_dest = -+ &(IX_MBUF_MDATA(&q->ixp_q_mbuf))[auth_off + auth_len]; -+ -+ IX_MBUF_MDATA(&q->ixp_q_mbuf) = tbuf; -+ -+ /* Set location in internal buffer for where hash starts */ -+ q->ixp_hash_src = &(IX_MBUF_MDATA(&q->ixp_q_mbuf))[auth_len]; -+ -+ crypt_func = "ixCryptoAccHashPerform"; -+ status = ixCryptoAccHashPerform(ixp->ixp_ctx.authCtx.authAlgo, -+ &q->ixp_q_mbuf, ixp_hash_perform_cb, 0, auth_len, auth_len, -+ &ixp->ixp_hash_key_id); -+ } -+ else { -+ crypt_func = "ixCryptoAccAuthCryptPerform"; -+ status = ixCryptoAccAuthCryptPerform(ixp->ixp_ctx_id, &q->ixp_q_mbuf, -+ NULL, auth_off, auth_len, crypt_off, crypt_len, icv_off, -+ q->ixp_q_iv); -+ } -+ -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) -+ return; -+ -+ if (IX_CRYPTO_ACC_STATUS_QUEUE_FULL == status) { -+ q->ixp_q_crp->crp_etype = ENOMEM; -+ goto done; -+ } -+ -+ printk("ixp: %s failed %u\n", crypt_func, status); -+ q->ixp_q_crp->crp_etype = EINVAL; -+ -+done: -+ crypto_done(q->ixp_q_crp); -+ kmem_cache_free(qcache, q); -+} -+ -+ -+/* -+ * because we cannot process the Q from the Register callback -+ * we do it here on a task Q. -+ */ -+ -+static void -+ixp_process_pending(void *arg) -+{ -+ struct ixp_data *ixp = arg; -+ struct ixp_q *q = NULL; -+ -+ dprintk("%s(%p)\n", __FUNCTION__, arg); -+ -+ if (!ixp) -+ return; -+ -+ while (!list_empty(&ixp->ixp_q)) { -+ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); -+ list_del(&q->ixp_q_list); -+ ixp_q_process(q); -+ } -+} -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void -+ixp_process_pending_wq(struct work_struct *work) -+{ -+ struct ixp_data *ixp = container_of(work, struct ixp_data, ixp_pending_work); -+ ixp_process_pending(ixp); -+} -+#endif -+ -+/* -+ * callback for when context registration is complete -+ */ -+ -+static void -+ixp_register_cb(UINT32 ctx_id, IX_MBUF *bufp, IxCryptoAccStatus status) -+{ -+ int i; -+ struct ixp_data *ixp; -+ struct ixp_q *q; -+ -+ dprintk("%s(%d, %p, %d)\n", __FUNCTION__, ctx_id, bufp, status); -+ -+ /* -+ * free any buffer passed in to this routine -+ */ -+ if (bufp) { -+ IX_MBUF_MLEN(bufp) = IX_MBUF_PKT_LEN(bufp) = 0; -+ kfree(IX_MBUF_MDATA(bufp)); -+ IX_MBUF_MDATA(bufp) = NULL; -+ } -+ -+ for (i = 0; i < ixp_sesnum; i++) { -+ ixp = ixp_sessions[i]; -+ if (ixp && ixp->ixp_ctx_id == ctx_id) -+ break; -+ } -+ if (i >= ixp_sesnum) { -+ printk("ixp: invalid context id %d\n", ctx_id); -+ return; -+ } -+ -+ if (IX_CRYPTO_ACC_STATUS_WAIT == status) { -+ /* this is normal to free the first of two buffers */ -+ dprintk("ixp: register not finished yet.\n"); -+ return; -+ } -+ -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS != status) { -+ printk("ixp: register failed 0x%x\n", status); -+ while (!list_empty(&ixp->ixp_q)) { -+ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); -+ list_del(&q->ixp_q_list); -+ q->ixp_q_crp->crp_etype = EINVAL; -+ crypto_done(q->ixp_q_crp); -+ kmem_cache_free(qcache, q); -+ } -+ return; -+ } -+ -+ /* -+ * we are now registered, we cannot start processing the Q here -+ * or we get strange errors with AES (DES/3DES seem to be ok). -+ */ -+ ixp->ixp_registered = 1; -+ schedule_work(&ixp->ixp_pending_work); -+} -+ -+ -+/* -+ * callback for when data processing is complete -+ */ -+ -+static void -+ixp_perform_cb( -+ UINT32 ctx_id, -+ IX_MBUF *sbufp, -+ IX_MBUF *dbufp, -+ IxCryptoAccStatus status) -+{ -+ struct ixp_q *q; -+ -+ dprintk("%s(%d, %p, %p, 0x%x)\n", __FUNCTION__, ctx_id, sbufp, -+ dbufp, status); -+ -+ if (sbufp == NULL) { -+ printk("ixp: NULL sbuf in ixp_perform_cb\n"); -+ return; -+ } -+ -+ q = IX_MBUF_PRIV(sbufp); -+ if (q == NULL) { -+ printk("ixp: NULL priv in ixp_perform_cb\n"); -+ return; -+ } -+ -+ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { -+ printk("ixp: perform failed status=%d\n", status); -+ q->ixp_q_crp->crp_etype = EINVAL; -+ } -+ -+ crypto_done(q->ixp_q_crp); -+ kmem_cache_free(qcache, q); -+} -+ -+ -+/* -+ * registration is not callable at IRQ time, so we defer -+ * to a task queue, this routines completes the registration for us -+ * when the task queue runs -+ * -+ * Unfortunately this means we cannot tell OCF that the driver is blocked, -+ * we do that on the next request. -+ */ -+ -+static void -+ixp_registration(void *arg) -+{ -+ struct ixp_data *ixp = arg; -+ struct ixp_q *q = NULL; -+ IX_MBUF *pri = NULL, *sec = NULL; -+ int status = IX_CRYPTO_ACC_STATUS_SUCCESS; -+ -+ if (!ixp) { -+ printk("ixp: ixp_registration with no arg\n"); -+ return; -+ } -+ -+ if (ixp->ixp_ctx_id != -1) { -+ ixCryptoAccCtxUnregister(ixp->ixp_ctx_id); -+ ixp->ixp_ctx_id = -1; -+ } -+ -+ if (list_empty(&ixp->ixp_q)) { -+ printk("ixp: ixp_registration with no Q\n"); -+ return; -+ } -+ -+ /* -+ * setup the primary and secondary buffers -+ */ -+ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); -+ if (q->ixp_q_acrd) { -+ pri = &ixp->ixp_pri_mbuf; -+ sec = &ixp->ixp_sec_mbuf; -+ IX_MBUF_MLEN(pri) = IX_MBUF_PKT_LEN(pri) = 128; -+ IX_MBUF_MDATA(pri) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); -+ IX_MBUF_MLEN(sec) = IX_MBUF_PKT_LEN(sec) = 128; -+ IX_MBUF_MDATA(sec) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); -+ } -+ -+ /* Only need to register if a crypt op or HMAC op */ -+ if (!(ixp->ixp_auth_alg == CRYPTO_SHA1 || -+ ixp->ixp_auth_alg == CRYPTO_MD5)) { -+ status = ixCryptoAccCtxRegister( -+ &ixp->ixp_ctx, -+ pri, sec, -+ ixp_register_cb, -+ ixp_perform_cb, -+ &ixp->ixp_ctx_id); -+ } -+ else { -+ /* Otherwise we start processing pending q */ -+ schedule_work(&ixp->ixp_pending_work); -+ } -+ -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) -+ return; -+ -+ if (IX_CRYPTO_ACC_STATUS_EXCEED_MAX_TUNNELS == status) { -+ printk("ixp: ixCryptoAccCtxRegister failed (out of tunnels)\n"); -+ ixp_blocked = 1; -+ /* perhaps we should return EGAIN on queued ops ? */ -+ return; -+ } -+ -+ printk("ixp: ixCryptoAccCtxRegister failed %d\n", status); -+ ixp->ixp_ctx_id = -1; -+ -+ /* -+ * everything waiting is toasted -+ */ -+ while (!list_empty(&ixp->ixp_q)) { -+ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); -+ list_del(&q->ixp_q_list); -+ q->ixp_q_crp->crp_etype = ENOENT; -+ crypto_done(q->ixp_q_crp); -+ kmem_cache_free(qcache, q); -+ } -+} -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void -+ixp_registration_wq(struct work_struct *work) -+{ -+ struct ixp_data *ixp = container_of(work, struct ixp_data, -+ ixp_registration_work); -+ ixp_registration(ixp); -+} -+#endif -+ -+/* -+ * Process a request. -+ */ -+static int -+ixp_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ struct ixp_data *ixp; -+ unsigned int lid; -+ struct ixp_q *q = NULL; -+ int status; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ /* Sanity check */ -+ if (crp == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ crp->crp_etype = 0; -+ -+ if (ixp_blocked) -+ return ERESTART; -+ -+ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ /* -+ * find the session we are using -+ */ -+ -+ lid = crp->crp_sid & 0xffffffff; -+ if (lid >= ixp_sesnum || lid == 0 || ixp_sessions == NULL || -+ ixp_sessions[lid] == NULL) { -+ crp->crp_etype = ENOENT; -+ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); -+ goto done; -+ } -+ ixp = ixp_sessions[lid]; -+ -+ /* -+ * setup a new request ready for queuing -+ */ -+ q = kmem_cache_alloc(qcache, SLAB_ATOMIC); -+ if (q == NULL) { -+ dprintk("%s,%d: ENOMEM\n", __FILE__, __LINE__); -+ crp->crp_etype = ENOMEM; -+ goto done; -+ } -+ /* -+ * save some cycles by only zeroing the important bits -+ */ -+ memset(&q->ixp_q_mbuf, 0, sizeof(q->ixp_q_mbuf)); -+ q->ixp_q_ccrd = NULL; -+ q->ixp_q_acrd = NULL; -+ q->ixp_q_crp = crp; -+ q->ixp_q_data = ixp; -+ -+ /* -+ * point the cipher and auth descriptors appropriately -+ * check that we have something to do -+ */ -+ if (crp->crp_desc->crd_alg == ixp->ixp_cipher_alg) -+ q->ixp_q_ccrd = crp->crp_desc; -+ else if (crp->crp_desc->crd_alg == ixp->ixp_auth_alg) -+ q->ixp_q_acrd = crp->crp_desc; -+ else { -+ crp->crp_etype = ENOENT; -+ dprintk("%s,%d: bad desc match: ENOENT\n", __FILE__, __LINE__); -+ goto done; -+ } -+ if (crp->crp_desc->crd_next) { -+ if (crp->crp_desc->crd_next->crd_alg == ixp->ixp_cipher_alg) -+ q->ixp_q_ccrd = crp->crp_desc->crd_next; -+ else if (crp->crp_desc->crd_next->crd_alg == ixp->ixp_auth_alg) -+ q->ixp_q_acrd = crp->crp_desc->crd_next; -+ else { -+ crp->crp_etype = ENOENT; -+ dprintk("%s,%d: bad desc match: ENOENT\n", __FILE__, __LINE__); -+ goto done; -+ } -+ } -+ -+ /* -+ * If there is a direction change for this context then we mark it as -+ * unregistered and re-register is for the new direction. This is not -+ * a very expensive operation and currently only tends to happen when -+ * user-space application are doing benchmarks -+ * -+ * DM - we should be checking for pending requests before unregistering. -+ */ -+ if (q->ixp_q_ccrd && ixp->ixp_registered && -+ ixp->ixp_crd_flags != (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT)) { -+ dprintk("%s - detected direction change on session\n", __FUNCTION__); -+ ixp->ixp_registered = 0; -+ } -+ -+ /* -+ * if we are registered, call straight into the perform code -+ */ -+ if (ixp->ixp_registered) { -+ ixp_q_process(q); -+ return 0; -+ } -+ -+ /* -+ * the only part of the context not set in newsession is the direction -+ * dependent parts -+ */ -+ if (q->ixp_q_ccrd) { -+ ixp->ixp_crd_flags = (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT); -+ if (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT) { -+ ixp->ixp_ctx.operation = q->ixp_q_acrd ? -+ IX_CRYPTO_ACC_OP_ENCRYPT_AUTH : IX_CRYPTO_ACC_OP_ENCRYPT; -+ } else { -+ ixp->ixp_ctx.operation = q->ixp_q_acrd ? -+ IX_CRYPTO_ACC_OP_AUTH_DECRYPT : IX_CRYPTO_ACC_OP_DECRYPT; -+ } -+ } else { -+ /* q->ixp_q_acrd must be set if we are here */ -+ ixp->ixp_ctx.operation = IX_CRYPTO_ACC_OP_AUTH_CALC; -+ } -+ -+ status = list_empty(&ixp->ixp_q); -+ list_add_tail(&q->ixp_q_list, &ixp->ixp_q); -+ if (status) -+ schedule_work(&ixp->ixp_registration_work); -+ return 0; -+ -+done: -+ if (q) -+ kmem_cache_free(qcache, q); -+ crypto_done(crp); -+ return 0; -+} -+ -+ -+#ifdef __ixp46X -+/* -+ * key processing support for the ixp465 -+ */ -+ -+ -+/* -+ * copy a BN (LE) into a buffer (BE) an fill out the op appropriately -+ * assume zeroed and only copy bits that are significant -+ */ -+ -+static int -+ixp_copy_ibuf(struct crparam *p, IxCryptoAccPkeEauOperand *op, UINT32 *buf) -+{ -+ unsigned char *src = (unsigned char *) p->crp_p; -+ unsigned char *dst; -+ int len, bits = p->crp_nbits; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (bits > MAX_IOP_SIZE * sizeof(UINT32) * 8) { -+ dprintk("%s - ibuf too big (%d > %d)\n", __FUNCTION__, -+ bits, MAX_IOP_SIZE * sizeof(UINT32) * 8); -+ return -1; -+ } -+ -+ len = (bits + 31) / 32; /* the number UINT32's needed */ -+ -+ dst = (unsigned char *) &buf[len]; -+ dst--; -+ -+ while (bits > 0) { -+ *dst-- = *src++; -+ bits -= 8; -+ } -+ -+#if 0 /* no need to zero remaining bits as it is done during request alloc */ -+ while (dst > (unsigned char *) buf) -+ *dst-- = '\0'; -+#endif -+ -+ op->pData = buf; -+ op->dataLen = len; -+ return 0; -+} -+ -+/* -+ * copy out the result, be as forgiving as we can about small output buffers -+ */ -+ -+static int -+ixp_copy_obuf(struct crparam *p, IxCryptoAccPkeEauOpResult *op, UINT32 *buf) -+{ -+ unsigned char *dst = (unsigned char *) p->crp_p; -+ unsigned char *src = (unsigned char *) buf; -+ int len, z, bits = p->crp_nbits; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ len = op->dataLen * sizeof(UINT32); -+ -+ /* skip leading zeroes to be small buffer friendly */ -+ z = 0; -+ while (z < len && src[z] == '\0') -+ z++; -+ -+ src += len; -+ src--; -+ len -= z; -+ -+ while (len > 0 && bits > 0) { -+ *dst++ = *src--; -+ len--; -+ bits -= 8; -+ } -+ -+ while (bits > 0) { -+ *dst++ = '\0'; -+ bits -= 8; -+ } -+ -+ if (len > 0) { -+ dprintk("%s - obuf is %d (z=%d, ob=%d) bytes too small\n", -+ __FUNCTION__, len, z, p->crp_nbits / 8); -+ return -1; -+ } -+ -+ return 0; -+} -+ -+ -+/* -+ * the parameter offsets for exp_mod -+ */ -+ -+#define IXP_PARAM_BASE 0 -+#define IXP_PARAM_EXP 1 -+#define IXP_PARAM_MOD 2 -+#define IXP_PARAM_RES 3 -+ -+/* -+ * key processing complete callback, is also used to start processing -+ * by passing a NULL for pResult -+ */ -+ -+static void -+ixp_kperform_cb( -+ IxCryptoAccPkeEauOperation operation, -+ IxCryptoAccPkeEauOpResult *pResult, -+ BOOL carryOrBorrow, -+ IxCryptoAccStatus status) -+{ -+ struct ixp_pkq *q, *tmp; -+ unsigned long flags; -+ -+ dprintk("%s(0x%x, %p, %d, 0x%x)\n", __FUNCTION__, operation, pResult, -+ carryOrBorrow, status); -+ -+ /* handle a completed request */ -+ if (pResult) { -+ if (ixp_pk_cur && &ixp_pk_cur->pkq_result == pResult) { -+ q = ixp_pk_cur; -+ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { -+ dprintk("%s() - op failed 0x%x\n", __FUNCTION__, status); -+ q->pkq_krp->krp_status = ERANGE; /* could do better */ -+ } else { -+ /* copy out the result */ -+ if (ixp_copy_obuf(&q->pkq_krp->krp_param[IXP_PARAM_RES], -+ &q->pkq_result, q->pkq_obuf)) -+ q->pkq_krp->krp_status = ERANGE; -+ } -+ crypto_kdone(q->pkq_krp); -+ kfree(q); -+ ixp_pk_cur = NULL; -+ } else -+ printk("%s - callback with invalid result pointer\n", __FUNCTION__); -+ } -+ -+ spin_lock_irqsave(&ixp_pkq_lock, flags); -+ if (ixp_pk_cur || list_empty(&ixp_pkq)) { -+ spin_unlock_irqrestore(&ixp_pkq_lock, flags); -+ return; -+ } -+ -+ list_for_each_entry_safe(q, tmp, &ixp_pkq, pkq_list) { -+ -+ list_del(&q->pkq_list); -+ ixp_pk_cur = q; -+ -+ spin_unlock_irqrestore(&ixp_pkq_lock, flags); -+ -+ status = ixCryptoAccPkeEauPerform( -+ IX_CRYPTO_ACC_OP_EAU_MOD_EXP, -+ &q->pkq_op, -+ ixp_kperform_cb, -+ &q->pkq_result); -+ -+ if (status == IX_CRYPTO_ACC_STATUS_SUCCESS) { -+ dprintk("%s() - ixCryptoAccPkeEauPerform SUCCESS\n", __FUNCTION__); -+ return; /* callback will return here for callback */ -+ } else if (status == IX_CRYPTO_ACC_STATUS_RETRY) { -+ printk("%s() - ixCryptoAccPkeEauPerform RETRY\n", __FUNCTION__); -+ } else { -+ printk("%s() - ixCryptoAccPkeEauPerform failed %d\n", -+ __FUNCTION__, status); -+ } -+ q->pkq_krp->krp_status = ERANGE; /* could do better */ -+ crypto_kdone(q->pkq_krp); -+ kfree(q); -+ spin_lock_irqsave(&ixp_pkq_lock, flags); -+ } -+ spin_unlock_irqrestore(&ixp_pkq_lock, flags); -+} -+ -+ -+static int -+ixp_kprocess(device_t dev, struct cryptkop *krp, int hint) -+{ -+ struct ixp_pkq *q; -+ int rc = 0; -+ unsigned long flags; -+ -+ dprintk("%s l1=%d l2=%d l3=%d l4=%d\n", __FUNCTION__, -+ krp->krp_param[IXP_PARAM_BASE].crp_nbits, -+ krp->krp_param[IXP_PARAM_EXP].crp_nbits, -+ krp->krp_param[IXP_PARAM_MOD].crp_nbits, -+ krp->krp_param[IXP_PARAM_RES].crp_nbits); -+ -+ -+ if (krp->krp_op != CRK_MOD_EXP) { -+ krp->krp_status = EOPNOTSUPP; -+ goto err; -+ } -+ -+ q = (struct ixp_pkq *) kmalloc(sizeof(*q), GFP_KERNEL); -+ if (q == NULL) { -+ krp->krp_status = ENOMEM; -+ goto err; -+ } -+ -+ /* -+ * The PKE engine does not appear to zero the output buffer -+ * appropriately, so we need to do it all here. -+ */ -+ memset(q, 0, sizeof(*q)); -+ -+ q->pkq_krp = krp; -+ INIT_LIST_HEAD(&q->pkq_list); -+ -+ if (ixp_copy_ibuf(&krp->krp_param[IXP_PARAM_BASE], &q->pkq_op.modExpOpr.M, -+ q->pkq_ibuf0)) -+ rc = 1; -+ if (!rc && ixp_copy_ibuf(&krp->krp_param[IXP_PARAM_EXP], -+ &q->pkq_op.modExpOpr.e, q->pkq_ibuf1)) -+ rc = 2; -+ if (!rc && ixp_copy_ibuf(&krp->krp_param[IXP_PARAM_MOD], -+ &q->pkq_op.modExpOpr.N, q->pkq_ibuf2)) -+ rc = 3; -+ -+ if (rc) { -+ kfree(q); -+ krp->krp_status = ERANGE; -+ goto err; -+ } -+ -+ q->pkq_result.pData = q->pkq_obuf; -+ q->pkq_result.dataLen = -+ (krp->krp_param[IXP_PARAM_RES].crp_nbits + 31) / 32; -+ -+ spin_lock_irqsave(&ixp_pkq_lock, flags); -+ list_add_tail(&q->pkq_list, &ixp_pkq); -+ spin_unlock_irqrestore(&ixp_pkq_lock, flags); -+ -+ if (!ixp_pk_cur) -+ ixp_kperform_cb(0, NULL, 0, 0); -+ return (0); -+ -+err: -+ crypto_kdone(krp); -+ return (0); -+} -+ -+ -+ -+#ifdef CONFIG_OCF_RANDOMHARVEST -+/* -+ * We run the random number generator output through SHA so that it -+ * is FIPS compliant. -+ */ -+ -+static volatile int sha_done = 0; -+static unsigned char sha_digest[20]; -+ -+static void -+ixp_hash_cb(UINT8 *digest, IxCryptoAccStatus status) -+{ -+ dprintk("%s(%p, %d)\n", __FUNCTION__, digest, status); -+ if (sha_digest != digest) -+ printk("digest error\n"); -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) -+ sha_done = 1; -+ else -+ sha_done = -status; -+} -+ -+static int -+ixp_read_random(void *arg, u_int32_t *buf, int maxwords) -+{ -+ IxCryptoAccStatus status; -+ int i, n, rc; -+ -+ dprintk("%s(%p, %d)\n", __FUNCTION__, buf, maxwords); -+ memset(buf, 0, maxwords * sizeof(*buf)); -+ status = ixCryptoAccPkePseudoRandomNumberGet(maxwords, buf); -+ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { -+ dprintk("%s: ixCryptoAccPkePseudoRandomNumberGet failed %d\n", -+ __FUNCTION__, status); -+ return 0; -+ } -+ -+ /* -+ * run the random data through SHA to make it look more random -+ */ -+ -+ n = sizeof(sha_digest); /* process digest bytes at a time */ -+ -+ rc = 0; -+ for (i = 0; i < maxwords; i += n / sizeof(*buf)) { -+ if ((maxwords - i) * sizeof(*buf) < n) -+ n = (maxwords - i) * sizeof(*buf); -+ sha_done = 0; -+ status = ixCryptoAccPkeHashPerform(IX_CRYPTO_ACC_AUTH_SHA1, -+ (UINT8 *) &buf[i], n, ixp_hash_cb, sha_digest); -+ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { -+ dprintk("ixCryptoAccPkeHashPerform failed %d\n", status); -+ return -EIO; -+ } -+ while (!sha_done) -+ schedule(); -+ if (sha_done < 0) { -+ dprintk("ixCryptoAccPkeHashPerform failed CB %d\n", -sha_done); -+ return 0; -+ } -+ memcpy(&buf[i], sha_digest, n); -+ rc += n / sizeof(*buf);; -+ } -+ -+ return rc; -+} -+#endif /* CONFIG_OCF_RANDOMHARVEST */ -+ -+#endif /* __ixp46X */ -+ -+ -+ -+/* -+ * our driver startup and shutdown routines -+ */ -+ -+static int -+ixp_init(void) -+{ -+ dprintk("%s(%p)\n", __FUNCTION__, ixp_init); -+ -+ if (ixp_init_crypto && ixCryptoAccInit() != IX_CRYPTO_ACC_STATUS_SUCCESS) -+ printk("ixCryptoAccInit failed, assuming already initialised!\n"); -+ -+ qcache = kmem_cache_create("ixp4xx_q", sizeof(struct ixp_q), 0, -+ SLAB_HWCACHE_ALIGN, NULL -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) -+ , NULL -+#endif -+ ); -+ if (!qcache) { -+ printk("failed to create Qcache\n"); -+ return -ENOENT; -+ } -+ -+ memset(&ixpdev, 0, sizeof(ixpdev)); -+ softc_device_init(&ixpdev, "ixp4xx", 0, ixp_methods); -+ -+ ixp_id = crypto_get_driverid(softc_get_device(&ixpdev), -+ CRYPTOCAP_F_HARDWARE); -+ if (ixp_id < 0) -+ panic("IXP/OCF crypto device cannot initialize!"); -+ -+#define REGISTER(alg) \ -+ crypto_register(ixp_id,alg,0,0) -+ -+ REGISTER(CRYPTO_DES_CBC); -+ REGISTER(CRYPTO_3DES_CBC); -+ REGISTER(CRYPTO_RIJNDAEL128_CBC); -+#ifdef CONFIG_OCF_IXP4XX_SHA1_MD5 -+ REGISTER(CRYPTO_MD5); -+ REGISTER(CRYPTO_SHA1); -+#endif -+ REGISTER(CRYPTO_MD5_HMAC); -+ REGISTER(CRYPTO_SHA1_HMAC); -+#undef REGISTER -+ -+#ifdef __ixp46X -+ spin_lock_init(&ixp_pkq_lock); -+ /* -+ * we do not enable the go fast options here as they can potentially -+ * allow timing based attacks -+ * -+ * http://www.openssl.org/news/secadv_20030219.txt -+ */ -+ ixCryptoAccPkeEauExpConfig(0, 0); -+ crypto_kregister(ixp_id, CRK_MOD_EXP, 0); -+#ifdef CONFIG_OCF_RANDOMHARVEST -+ crypto_rregister(ixp_id, ixp_read_random, NULL); -+#endif -+#endif -+ -+ return 0; -+} -+ -+static void -+ixp_exit(void) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ crypto_unregister_all(ixp_id); -+ ixp_id = -1; -+ kmem_cache_destroy(qcache); -+ qcache = NULL; -+} -+ -+module_init(ixp_init); -+module_exit(ixp_exit); -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("ixp (OCF module for IXP4xx crypto)"); -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/Makefile linux-2.6.39/crypto/ocf/kirkwood/Makefile ---- linux-2.6.39.orig/crypto/ocf/kirkwood/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/Makefile 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,19 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+obj-$(CONFIG_OCF_KIRKWOOD) += mv_cesa.o -+ -+mv_cesa-y := cesa/mvCesa.o cesa/mvLru.o cesa/mvMD5.o cesa/mvSHA1.o cesa/AES/mvAesAlg.o cesa/AES/mvAesApi.o cesa/mvCesaDebug.o cesa_ocf_drv.o -+ -+# Extra objects required by the CESA driver -+mv_cesa-y += mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.o mvHal/kw_family/boardEnv/mvBoardEnvLib.o mvHal/mv_hal/twsi/mvTwsi.o mvHal/kw_family/ctrlEnv/sys/mvCpuIf.o mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.o mvHal/kw_family/ctrlEnv/sys/mvSysDram.o mvHal/linux_oss/mvOs.o mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.o mvHal/mv_hal/gpp/mvGpp.o mvHal/kw_family/ctrlEnv/sys/mvSysPex.o mvHal/mv_hal/pex/mvPex.o mvHal/kw_family/boardEnv/mvBoardEnvSpec.o mvHal/common/mvCommon.o mvHal/common/mvDebug.o mvHal/kw_family/ctrlEnv/sys/mvSysCesa.o -+ -+ifdef src -+EXTRA_CFLAGS += -I$(src)/.. -I$(src)/cesa -I$(src)/mvHal -I$(src)/mvHal/common -I$(src)/mvHal/kw_family -I$(src)/mvHal/mv_hal -I$(src)/mvHal/linux_oss -I$(src) -+endif -+ -+EXTRA_CFLAGS += -DMV_LINUX -DMV_CPU_LE -DMV_ARM -DMV_INCLUDE_CESA -DMV_INCLUDE_PEX -DMV_CACHE_COHERENCY=3 -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/cesa/AES/mvAes.h linux-2.6.39/crypto/ocf/kirkwood/cesa/AES/mvAes.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/cesa/AES/mvAes.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/cesa/AES/mvAes.h 2011-08-01 14:38:18.000000000 +0200 -@@ -0,0 +1,62 @@ -+/* mvAes.h v2.0 August '99 -+ * Reference ANSI C code -+ */ -+ -+/* AES Cipher header file for ANSI C Submissions -+ Lawrence E. Bassham III -+ Computer Security Division -+ National Institute of Standards and Technology -+ -+ April 15, 1998 -+ -+ This sample is to assist implementers developing to the Cryptographic -+API Profile for AES Candidate Algorithm Submissions. Please consult this -+document as a cross-reference. -+ -+ ANY CHANGES, WHERE APPROPRIATE, TO INFORMATION PROVIDED IN THIS FILE -+MUST BE DOCUMENTED. CHANGES ARE ONLY APPROPRIATE WHERE SPECIFIED WITH -+THE STRING "CHANGE POSSIBLE". FUNCTION CALLS AND THEIR PARAMETERS CANNOT -+BE CHANGED. STRUCTURES CAN BE ALTERED TO ALLOW IMPLEMENTERS TO INCLUDE -+IMPLEMENTATION SPECIFIC INFORMATION. -+*/ -+ -+/* Includes: -+ Standard include files -+*/ -+ -+#include "mvOs.h" -+ -+ -+/* Error Codes - CHANGE POSSIBLE: inclusion of additional error codes */ -+ -+/* Key direction is invalid, e.g., unknown value */ -+#define AES_BAD_KEY_DIR -1 -+ -+/* Key material not of correct length */ -+#define AES_BAD_KEY_MAT -2 -+ -+/* Key passed is not valid */ -+#define AES_BAD_KEY_INSTANCE -3 -+ -+/* Params struct passed to cipherInit invalid */ -+#define AES_BAD_CIPHER_MODE -4 -+ -+/* Cipher in wrong state (e.g., not initialized) */ -+#define AES_BAD_CIPHER_STATE -5 -+ -+#define AES_BAD_CIPHER_INSTANCE -7 -+ -+ -+/* Function protoypes */ -+/* CHANGED: makeKey(): parameter blockLen added -+ this parameter is absolutely necessary if you want to -+ setup the round keys in a variable block length setting -+ cipherInit(): parameter blockLen added (for obvious reasons) -+ */ -+int aesMakeKey(MV_U8 *expandedKey, MV_U8 *keyMaterial, int keyLen, int blockLen); -+int aesBlockEncrypt128(MV_U8 mode, MV_U8 *IV, MV_U8 *expandedKey, int keyLen, -+ MV_U32 *plain, int numBlocks, MV_U32 *cipher); -+int aesBlockDecrypt128(MV_U8 mode, MV_U8 *IV, MV_U8 *expandedKey, int keyLen, -+ MV_U32 *plain, int numBlocks, MV_U32 *cipher); -+ -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.c linux-2.6.39/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.c ---- linux-2.6.39.orig/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.c 2011-08-01 14:38:18.000000000 +0200 -@@ -0,0 +1,317 @@ -+/* rijndael-alg-ref.c v2.0 August '99 -+ * Reference ANSI C code -+ * authors: Paulo Barreto -+ * Vincent Rijmen, K.U.Leuven -+ * -+ * This code is placed in the public domain. -+ */ -+ -+#include "mvOs.h" -+ -+#include "mvAesAlg.h" -+ -+#include "mvAesBoxes.dat" -+ -+ -+MV_U8 mul1(MV_U8 aa, MV_U8 bb); -+void KeyAddition(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC], MV_U8 BC); -+void ShiftRow128Enc(MV_U8 a[4][MAXBC]); -+void ShiftRow128Dec(MV_U8 a[4][MAXBC]); -+void Substitution(MV_U8 a[4][MAXBC], MV_U8 box[256]); -+void MixColumn(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC]); -+void InvMixColumn(MV_U8 a[4][MAXBC]); -+ -+ -+#define mul(aa, bb) (mask[bb] & Alogtable[aa + Logtable[bb]]) -+ -+MV_U8 mul1(MV_U8 aa, MV_U8 bb) -+{ -+ return mask[bb] & Alogtable[aa + Logtable[bb]]; -+} -+ -+ -+void KeyAddition(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC], MV_U8 BC) -+{ -+ /* Exor corresponding text input and round key input bytes -+ */ -+ ((MV_U32*)(&(a[0][0])))[0] ^= ((MV_U32*)(&(rk[0][0])))[0]; -+ ((MV_U32*)(&(a[1][0])))[0] ^= ((MV_U32*)(&(rk[1][0])))[0]; -+ ((MV_U32*)(&(a[2][0])))[0] ^= ((MV_U32*)(&(rk[2][0])))[0]; -+ ((MV_U32*)(&(a[3][0])))[0] ^= ((MV_U32*)(&(rk[3][0])))[0]; -+ -+} -+ -+void ShiftRow128Enc(MV_U8 a[4][MAXBC]) { -+ /* Row 0 remains unchanged -+ * The other three rows are shifted a variable amount -+ */ -+ MV_U8 tmp[MAXBC]; -+ -+ tmp[0] = a[1][1]; -+ tmp[1] = a[1][2]; -+ tmp[2] = a[1][3]; -+ tmp[3] = a[1][0]; -+ -+ ((MV_U32*)(&(a[1][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; -+ /* -+ a[1][0] = tmp[0]; -+ a[1][1] = tmp[1]; -+ a[1][2] = tmp[2]; -+ a[1][3] = tmp[3]; -+ */ -+ tmp[0] = a[2][2]; -+ tmp[1] = a[2][3]; -+ tmp[2] = a[2][0]; -+ tmp[3] = a[2][1]; -+ -+ ((MV_U32*)(&(a[2][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; -+ /* -+ a[2][0] = tmp[0]; -+ a[2][1] = tmp[1]; -+ a[2][2] = tmp[2]; -+ a[2][3] = tmp[3]; -+ */ -+ tmp[0] = a[3][3]; -+ tmp[1] = a[3][0]; -+ tmp[2] = a[3][1]; -+ tmp[3] = a[3][2]; -+ -+ ((MV_U32*)(&(a[3][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; -+ /* -+ a[3][0] = tmp[0]; -+ a[3][1] = tmp[1]; -+ a[3][2] = tmp[2]; -+ a[3][3] = tmp[3]; -+ */ -+} -+ -+void ShiftRow128Dec(MV_U8 a[4][MAXBC]) { -+ /* Row 0 remains unchanged -+ * The other three rows are shifted a variable amount -+ */ -+ MV_U8 tmp[MAXBC]; -+ -+ tmp[0] = a[1][3]; -+ tmp[1] = a[1][0]; -+ tmp[2] = a[1][1]; -+ tmp[3] = a[1][2]; -+ -+ ((MV_U32*)(&(a[1][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; -+ /* -+ a[1][0] = tmp[0]; -+ a[1][1] = tmp[1]; -+ a[1][2] = tmp[2]; -+ a[1][3] = tmp[3]; -+ */ -+ -+ tmp[0] = a[2][2]; -+ tmp[1] = a[2][3]; -+ tmp[2] = a[2][0]; -+ tmp[3] = a[2][1]; -+ -+ ((MV_U32*)(&(a[2][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; -+ /* -+ a[2][0] = tmp[0]; -+ a[2][1] = tmp[1]; -+ a[2][2] = tmp[2]; -+ a[2][3] = tmp[3]; -+ */ -+ -+ tmp[0] = a[3][1]; -+ tmp[1] = a[3][2]; -+ tmp[2] = a[3][3]; -+ tmp[3] = a[3][0]; -+ -+ ((MV_U32*)(&(a[3][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; -+ /* -+ a[3][0] = tmp[0]; -+ a[3][1] = tmp[1]; -+ a[3][2] = tmp[2]; -+ a[3][3] = tmp[3]; -+ */ -+} -+ -+void Substitution(MV_U8 a[4][MAXBC], MV_U8 box[256]) { -+ /* Replace every byte of the input by the byte at that place -+ * in the nonlinear S-box -+ */ -+ int i, j; -+ -+ for(i = 0; i < 4; i++) -+ for(j = 0; j < 4; j++) a[i][j] = box[a[i][j]] ; -+} -+ -+void MixColumn(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC]) { -+ /* Mix the four bytes of every column in a linear way -+ */ -+ MV_U8 b[4][MAXBC]; -+ int i, j; -+ -+ for(j = 0; j < 4; j++){ -+ b[0][j] = mul(25,a[0][j]) ^ mul(1,a[1][j]) ^ a[2][j] ^ a[3][j]; -+ b[1][j] = mul(25,a[1][j]) ^ mul(1,a[2][j]) ^ a[3][j] ^ a[0][j]; -+ b[2][j] = mul(25,a[2][j]) ^ mul(1,a[3][j]) ^ a[0][j] ^ a[1][j]; -+ b[3][j] = mul(25,a[3][j]) ^ mul(1,a[0][j]) ^ a[1][j] ^ a[2][j]; -+ } -+ for(i = 0; i < 4; i++) -+ /*for(j = 0; j < BC; j++) a[i][j] = b[i][j];*/ -+ ((MV_U32*)(&(a[i][0])))[0] = ((MV_U32*)(&(b[i][0])))[0] ^ ((MV_U32*)(&(rk[i][0])))[0];; -+} -+ -+void InvMixColumn(MV_U8 a[4][MAXBC]) { -+ /* Mix the four bytes of every column in a linear way -+ * This is the opposite operation of Mixcolumn -+ */ -+ MV_U8 b[4][MAXBC]; -+ int i, j; -+ -+ for(j = 0; j < 4; j++){ -+ b[0][j] = mul(223,a[0][j]) ^ mul(104,a[1][j]) ^ mul(238,a[2][j]) ^ mul(199,a[3][j]); -+ b[1][j] = mul(223,a[1][j]) ^ mul(104,a[2][j]) ^ mul(238,a[3][j]) ^ mul(199,a[0][j]); -+ b[2][j] = mul(223,a[2][j]) ^ mul(104,a[3][j]) ^ mul(238,a[0][j]) ^ mul(199,a[1][j]); -+ b[3][j] = mul(223,a[3][j]) ^ mul(104,a[0][j]) ^ mul(238,a[1][j]) ^ mul(199,a[2][j]); -+ } -+ for(i = 0; i < 4; i++) -+ /*for(j = 0; j < BC; j++) a[i][j] = b[i][j];*/ -+ ((MV_U32*)(&(a[i][0])))[0] = ((MV_U32*)(&(b[i][0])))[0]; -+} -+ -+int rijndaelKeySched (MV_U8 k[4][MAXKC], int keyBits, int blockBits, MV_U8 W[MAXROUNDS+1][4][MAXBC]) -+{ -+ /* Calculate the necessary round keys -+ * The number of calculations depends on keyBits and blockBits -+ */ -+ int KC, BC, ROUNDS; -+ int i, j, t, rconpointer = 0; -+ MV_U8 tk[4][MAXKC]; -+ -+ switch (keyBits) { -+ case 128: KC = 4; break; -+ case 192: KC = 6; break; -+ case 256: KC = 8; break; -+ default : return (-1); -+ } -+ -+ switch (blockBits) { -+ case 128: BC = 4; break; -+ case 192: BC = 6; break; -+ case 256: BC = 8; break; -+ default : return (-2); -+ } -+ -+ switch (keyBits >= blockBits ? keyBits : blockBits) { -+ case 128: ROUNDS = 10; break; -+ case 192: ROUNDS = 12; break; -+ case 256: ROUNDS = 14; break; -+ default : return (-3); /* this cannot happen */ -+ } -+ -+ -+ for(j = 0; j < KC; j++) -+ for(i = 0; i < 4; i++) -+ tk[i][j] = k[i][j]; -+ t = 0; -+ /* copy values into round key array */ -+ for(j = 0; (j < KC) && (t < (ROUNDS+1)*BC); j++, t++) -+ for(i = 0; i < 4; i++) W[t / BC][i][t % BC] = tk[i][j]; -+ -+ while (t < (ROUNDS+1)*BC) { /* while not enough round key material calculated */ -+ /* calculate new values */ -+ for(i = 0; i < 4; i++) -+ tk[i][0] ^= S[tk[(i+1)%4][KC-1]]; -+ tk[0][0] ^= rcon[rconpointer++]; -+ -+ if (KC != 8) -+ for(j = 1; j < KC; j++) -+ for(i = 0; i < 4; i++) tk[i][j] ^= tk[i][j-1]; -+ else { -+ for(j = 1; j < KC/2; j++) -+ for(i = 0; i < 4; i++) tk[i][j] ^= tk[i][j-1]; -+ for(i = 0; i < 4; i++) tk[i][KC/2] ^= S[tk[i][KC/2 - 1]]; -+ for(j = KC/2 + 1; j < KC; j++) -+ for(i = 0; i < 4; i++) tk[i][j] ^= tk[i][j-1]; -+ } -+ /* copy values into round key array */ -+ for(j = 0; (j < KC) && (t < (ROUNDS+1)*BC); j++, t++) -+ for(i = 0; i < 4; i++) W[t / BC][i][t % BC] = tk[i][j]; -+ } -+ -+ return 0; -+} -+ -+ -+ -+int rijndaelEncrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds) -+{ -+ /* Encryption of one block. -+ */ -+ int r, BC, ROUNDS; -+ -+ BC = 4; -+ ROUNDS = rounds; -+ -+ /* begin with a key addition -+ */ -+ -+ KeyAddition(a,rk[0],BC); -+ -+ /* ROUNDS-1 ordinary rounds -+ */ -+ for(r = 1; r < ROUNDS; r++) { -+ Substitution(a,S); -+ ShiftRow128Enc(a); -+ MixColumn(a, rk[r]); -+ /*KeyAddition(a,rk[r],BC);*/ -+ } -+ -+ /* Last round is special: there is no MixColumn -+ */ -+ Substitution(a,S); -+ ShiftRow128Enc(a); -+ KeyAddition(a,rk[ROUNDS],BC); -+ -+ return 0; -+} -+ -+ -+int rijndaelDecrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds) -+{ -+ int r, BC, ROUNDS; -+ -+ BC = 4; -+ ROUNDS = rounds; -+ -+ /* To decrypt: apply the inverse operations of the encrypt routine, -+ * in opposite order -+ * -+ * (KeyAddition is an involution: it 's equal to its inverse) -+ * (the inverse of Substitution with table S is Substitution with the inverse table of S) -+ * (the inverse of Shiftrow is Shiftrow over a suitable distance) -+ */ -+ -+ /* First the special round: -+ * without InvMixColumn -+ * with extra KeyAddition -+ */ -+ KeyAddition(a,rk[ROUNDS],BC); -+ ShiftRow128Dec(a); -+ Substitution(a,Si); -+ -+ /* ROUNDS-1 ordinary rounds -+ */ -+ for(r = ROUNDS-1; r > 0; r--) { -+ KeyAddition(a,rk[r],BC); -+ InvMixColumn(a); -+ ShiftRow128Dec(a); -+ Substitution(a,Si); -+ -+ } -+ -+ /* End with the extra key addition -+ */ -+ -+ KeyAddition(a,rk[0],BC); -+ -+ return 0; -+} -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.h linux-2.6.39/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.h 2011-08-01 14:38:18.000000000 +0200 -@@ -0,0 +1,19 @@ -+/* rijndael-alg-ref.h v2.0 August '99 -+ * Reference ANSI C code -+ * authors: Paulo Barreto -+ * Vincent Rijmen, K.U.Leuven -+ */ -+#ifndef __RIJNDAEL_ALG_H -+#define __RIJNDAEL_ALG_H -+ -+#define MAXBC (128/32) -+#define MAXKC (256/32) -+#define MAXROUNDS 14 -+ -+ -+int rijndaelKeySched (MV_U8 k[4][MAXKC], int keyBits, int blockBits, MV_U8 rk[MAXROUNDS+1][4][MAXBC]); -+ -+int rijndaelEncrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds); -+int rijndaelDecrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds); -+ -+#endif /* __RIJNDAEL_ALG_H */ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/cesa/AES/mvAesApi.c linux-2.6.39/crypto/ocf/kirkwood/cesa/AES/mvAesApi.c ---- linux-2.6.39.orig/crypto/ocf/kirkwood/cesa/AES/mvAesApi.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/cesa/AES/mvAesApi.c 2011-08-01 14:38:18.000000000 +0200 -@@ -0,0 +1,312 @@ -+/* rijndael-api-ref.c v2.1 April 2000 -+ * Reference ANSI C code -+ * authors: v2.0 Paulo Barreto -+ * Vincent Rijmen, K.U.Leuven -+ * v2.1 Vincent Rijmen, K.U.Leuven -+ * -+ * This code is placed in the public domain. -+ */ -+#include "mvOs.h" -+ -+#include "mvAes.h" -+#include "mvAesAlg.h" -+ -+ -+/* Defines: -+ Add any additional defines you need -+*/ -+ -+#define MODE_ECB 1 /* Are we ciphering in ECB mode? */ -+#define MODE_CBC 2 /* Are we ciphering in CBC mode? */ -+#define MODE_CFB1 3 /* Are we ciphering in 1-bit CFB mode? */ -+ -+ -+int aesMakeKey(MV_U8 *expandedKey, MV_U8 *keyMaterial, int keyLen, int blockLen) -+{ -+ MV_U8 W[MAXROUNDS+1][4][MAXBC]; -+ MV_U8 k[4][MAXKC]; -+ MV_U8 j; -+ int i, rounds, KC; -+ -+ if (expandedKey == NULL) -+ { -+ return AES_BAD_KEY_INSTANCE; -+ } -+ -+ if (!((keyLen == 128) || (keyLen == 192) || (keyLen == 256))) -+ { -+ return AES_BAD_KEY_MAT; -+ } -+ -+ if (keyMaterial == NULL) -+ { -+ return AES_BAD_KEY_MAT; -+ } -+ -+ /* initialize key schedule: */ -+ for(i=0; i= 3) -+MV_U32 cesaChainLength = 0; -+int chainReqNum = 0; -+MV_U32 chainIndex = 0; -+MV_CESA_REQ* pNextActiveChain = 0; -+MV_CESA_REQ* pEndCurrChain = 0; -+MV_BOOL isFirstReq = MV_TRUE; -+#endif -+ -+static INLINE MV_U8* mvCesaSramAddrGet(void) -+{ -+#ifdef MV_CESA_NO_SRAM -+ return (MV_U8*)cesaSramVirtPtr; -+#else -+ return (MV_U8*)cesaCryptEngBase; -+#endif /* MV_CESA_NO_SRAM */ -+} -+ -+static INLINE MV_ULONG mvCesaSramVirtToPhys(void* pDev, MV_U8* pSramVirt) -+{ -+#ifdef MV_CESA_NO_SRAM -+ return (MV_ULONG)mvOsIoVirtToPhy(NULL, pSramVirt); -+#else -+ return (MV_ULONG)pSramVirt; -+#endif /* MV_CESA_NO_SRAM */ -+} -+ -+/* Internal Function prototypes */ -+ -+static INLINE void mvCesaSramDescrBuild(MV_U32 config, int frag, -+ int cryptoOffset, int ivOffset, int cryptoLength, -+ int macOffset, int digestOffset, int macLength, int macTotalLen, -+ MV_CESA_REQ *pCesaReq, MV_DMA_DESC* pDmaDesc); -+ -+static INLINE void mvCesaSramSaUpdate(short sid, MV_DMA_DESC *pDmaDesc); -+ -+static INLINE int mvCesaDmaCopyPrepare(MV_CESA_MBUF* pMbuf, MV_U8* pSramBuf, -+ MV_DMA_DESC* pDmaDesc, MV_BOOL isToMbuf, -+ int offset, int copySize, MV_BOOL skipFlush); -+ -+static void mvCesaHmacIvGet(MV_CESA_MAC_MODE macMode, unsigned char key[], int keyLength, -+ unsigned char innerIV[], unsigned char outerIV[]); -+ -+static MV_STATUS mvCesaFragAuthComplete(MV_CESA_REQ* pReq, MV_CESA_SA* pSA, -+ int macDataSize); -+ -+static MV_CESA_COMMAND* mvCesaCtrModeInit(void); -+ -+static MV_STATUS mvCesaCtrModePrepare(MV_CESA_COMMAND *pCtrModeCmd, MV_CESA_COMMAND *pCmd); -+static MV_STATUS mvCesaCtrModeComplete(MV_CESA_COMMAND *pOrgCmd, MV_CESA_COMMAND *pCmd); -+static void mvCesaCtrModeFinish(MV_CESA_COMMAND *pCmd); -+ -+static INLINE MV_STATUS mvCesaReqProcess(MV_CESA_REQ* pReq); -+static MV_STATUS mvCesaFragReqProcess(MV_CESA_REQ* pReq, MV_U8 frag); -+ -+static INLINE MV_STATUS mvCesaParamCheck(MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, MV_U8* pFixOffset); -+static INLINE MV_STATUS mvCesaFragParamCheck(MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd); -+ -+static INLINE void mvCesaFragSizeFind(MV_CESA_SA* pSA, MV_CESA_REQ* pReq, -+ int cryptoOffset, int macOffset, -+ int* pCopySize, int* pCryptoDataSize, int* pMacDataSize); -+static MV_STATUS mvCesaMbufCacheUnmap(MV_CESA_MBUF* pMbuf, int offset, int size); -+ -+ -+/* Go to the next request in the request queue */ -+static INLINE MV_CESA_REQ* MV_CESA_REQ_NEXT_PTR(MV_CESA_REQ* pReq) -+{ -+ if(pReq == pCesaReqLast) -+ return pCesaReqFirst; -+ -+ return pReq+1; -+} -+ -+#if (MV_CESA_VERSION >= 3) -+/* Go to the previous request in the request queue */ -+static INLINE MV_CESA_REQ* MV_CESA_REQ_PREV_PTR(MV_CESA_REQ* pReq) -+{ -+ if(pReq == pCesaReqFirst) -+ return pCesaReqLast; -+ -+ return pReq-1; -+} -+ -+#endif -+ -+ -+static INLINE void mvCesaReqProcessStart(MV_CESA_REQ* pReq) -+{ -+ int frag; -+ -+#if (MV_CESA_VERSION >= 3) -+ pReq->state = MV_CESA_CHAIN; -+#else -+ pReq->state = MV_CESA_PROCESS; -+#endif -+ cesaStats.startCount++; -+ -+ if(pReq->fragMode == MV_CESA_FRAG_NONE) -+ { -+ frag = 0; -+ } -+ else -+ { -+ frag = pReq->frags.nextFrag; -+ pReq->frags.nextFrag++; -+ } -+#if (MV_CESA_VERSION >= 2) -+ /* Enable TDMA engine */ -+ MV_REG_WRITE(MV_CESA_TDMA_CURR_DESC_PTR_REG, 0); -+ MV_REG_WRITE(MV_CESA_TDMA_NEXT_DESC_PTR_REG, -+ (MV_U32)mvCesaVirtToPhys(&pReq->dmaDescBuf, pReq->dma[frag].pDmaFirst)); -+#else -+ /* Enable IDMA engine */ -+ MV_REG_WRITE(IDMA_CURR_DESC_PTR_REG(0), 0); -+ MV_REG_WRITE(IDMA_NEXT_DESC_PTR_REG(0), -+ (MV_U32)mvCesaVirtToPhys(&pReq->dmaDescBuf, pReq->dma[frag].pDmaFirst)); -+#endif /* MV_CESA_VERSION >= 2 */ -+ -+#if defined(MV_BRIDGE_SYNC_REORDER) -+ mvOsBridgeReorderWA(); -+#endif -+ -+ /* Start Accelerator */ -+ MV_REG_WRITE(MV_CESA_CMD_REG, MV_CESA_CMD_CHAN_ENABLE_MASK); -+} -+ -+ -+/******************************************************************************* -+* mvCesaHalInit - Initialize the CESA driver -+* -+* DESCRIPTION: -+* This function initialize the CESA driver. -+* 1) Session database -+* 2) Request queue -+* 4) DMA descriptor lists - one list per request. Each list -+* has MV_CESA_MAX_DMA_DESC descriptors. -+* -+* INPUT: -+* numOfSession - maximum number of supported sessions -+* queueDepth - number of elements in the request queue. -+* pSramBase - virtual address of Sram -+* osHandle - A handle used by the OS to allocate memory for the -+* module (Passed to the OS Services layer) -+* -+* RETURN: -+* MV_OK - Success -+* MV_NO_RESOURCE - Fail, can't allocate resources: -+* Session database, request queue, -+* DMA descriptors list, LRU cache database. -+* MV_NOT_ALIGNED - Sram base address is not 8 byte aligned. -+* -+*******************************************************************************/ -+MV_STATUS mvCesaHalInit (int numOfSession, int queueDepth, char* pSramBase, MV_U32 cryptEngBase, -+ void *osHandle) -+{ -+ int i, req; -+ MV_U32 descOffsetReg, configReg; -+ MV_CESA_SRAM_SA *pSramSA; -+ -+ -+ mvOsPrintf("mvCesaInit: sessions=%d, queue=%d, pSram=%p\n", -+ numOfSession, queueDepth, pSramBase); -+ -+ cesaOsHandle = osHandle; -+ /* Create Session database */ -+ pCesaSAD = mvOsMalloc(sizeof(MV_CESA_SA)*numOfSession); -+ if(pCesaSAD == NULL) -+ { -+ mvOsPrintf("mvCesaInit: Can't allocate %u bytes for %d SAs\n", -+ sizeof(MV_CESA_SA)*numOfSession, numOfSession); -+ mvCesaFinish(); -+ return MV_NO_RESOURCE; -+ } -+ memset(pCesaSAD, 0, sizeof(MV_CESA_SA)*numOfSession); -+ cesaMaxSA = numOfSession; -+ -+ /* Allocate imag of sramSA in the DRAM */ -+ cesaSramSaBuf.bufSize = sizeof(MV_CESA_SRAM_SA)*numOfSession + -+ CPU_D_CACHE_LINE_SIZE; -+ -+ cesaSramSaBuf.bufVirtPtr = mvOsIoCachedMalloc(osHandle,cesaSramSaBuf.bufSize, -+ &cesaSramSaBuf.bufPhysAddr, -+ &cesaSramSaBuf.memHandle); -+ -+ if(cesaSramSaBuf.bufVirtPtr == NULL) -+ { -+ mvOsPrintf("mvCesaInit: Can't allocate %d bytes for sramSA structures\n", -+ cesaSramSaBuf.bufSize); -+ mvCesaFinish(); -+ return MV_NO_RESOURCE; -+ } -+ memset(cesaSramSaBuf.bufVirtPtr, 0, cesaSramSaBuf.bufSize); -+ pSramSA = (MV_CESA_SRAM_SA*)MV_ALIGN_UP((MV_ULONG)cesaSramSaBuf.bufVirtPtr, -+ CPU_D_CACHE_LINE_SIZE); -+ for(i=0; i= 3) -+ cesaChainLength = MAX_CESA_CHAIN_LENGTH; -+#endif -+ /* pSramBase must be 8 byte aligned */ -+ if( MV_IS_NOT_ALIGN((MV_ULONG)pSramBase, 8) ) -+ { -+ mvOsPrintf("mvCesaInit: pSramBase (%p) must be 8 byte aligned\n", -+ pSramBase); -+ mvCesaFinish(); -+ return MV_NOT_ALIGNED; -+ } -+ cesaSramVirtPtr = (MV_CESA_SRAM_MAP*)pSramBase; -+ -+ cesaCryptEngBase = cryptEngBase; -+ -+ /*memset(cesaSramVirtPtr, 0, sizeof(MV_CESA_SRAM_MAP));*/ -+ -+ /* Clear registers */ -+ MV_REG_WRITE( MV_CESA_CFG_REG, 0); -+ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); -+ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, 0); -+ -+ /* Initialize DMA descriptor lists for all requests in Request queue */ -+ descOffsetReg = configReg = 0; -+ for(req=0; reqcesaDescBuf.bufSize = sizeof(MV_CESA_DESC)*MV_CESA_MAX_REQ_FRAGS + -+ CPU_D_CACHE_LINE_SIZE; -+ -+ pReq->cesaDescBuf.bufVirtPtr = -+ mvOsIoCachedMalloc(osHandle,pReq->cesaDescBuf.bufSize, -+ &pReq->cesaDescBuf.bufPhysAddr, -+ &pReq->cesaDescBuf.memHandle); -+ -+ if(pReq->cesaDescBuf.bufVirtPtr == NULL) -+ { -+ mvOsPrintf("mvCesaInit: req=%d, Can't allocate %d bytes for CESA descriptors\n", -+ req, pReq->cesaDescBuf.bufSize); -+ mvCesaFinish(); -+ return MV_NO_RESOURCE; -+ } -+ memset(pReq->cesaDescBuf.bufVirtPtr, 0, pReq->cesaDescBuf.bufSize); -+ pReq->pCesaDesc = (MV_CESA_DESC*)MV_ALIGN_UP((MV_ULONG)pReq->cesaDescBuf.bufVirtPtr, -+ CPU_D_CACHE_LINE_SIZE); -+ -+ pReq->dmaDescBuf.bufSize = sizeof(MV_DMA_DESC)*MV_CESA_MAX_DMA_DESC*MV_CESA_MAX_REQ_FRAGS + -+ CPU_D_CACHE_LINE_SIZE; -+ -+ pReq->dmaDescBuf.bufVirtPtr = -+ mvOsIoCachedMalloc(osHandle,pReq->dmaDescBuf.bufSize, -+ &pReq->dmaDescBuf.bufPhysAddr, -+ &pReq->dmaDescBuf.memHandle); -+ -+ if(pReq->dmaDescBuf.bufVirtPtr == NULL) -+ { -+ mvOsPrintf("mvCesaInit: req=%d, Can't allocate %d bytes for DMA descriptor list\n", -+ req, pReq->dmaDescBuf.bufSize); -+ mvCesaFinish(); -+ return MV_NO_RESOURCE; -+ } -+ memset(pReq->dmaDescBuf.bufVirtPtr, 0, pReq->dmaDescBuf.bufSize); -+ pDmaDesc = (MV_DMA_DESC*)MV_ALIGN_UP((MV_ULONG)pReq->dmaDescBuf.bufVirtPtr, -+ CPU_D_CACHE_LINE_SIZE); -+ -+ for(frag=0; fragdma[frag]; -+ -+ pDma->pDmaFirst = pDmaDesc; -+ pDma->pDmaLast = NULL; -+ -+ for(i=0; ipDmaFirst[i].phyNextDescPtr = -+ MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, &pDmaDesc[i+1])); -+ } -+ pDma->pDmaFirst[i].phyNextDescPtr = 0; -+ mvOsCacheFlush(NULL, &pDma->pDmaFirst[0], MV_CESA_MAX_DMA_DESC*sizeof(MV_DMA_DESC)); -+ -+ pDmaDesc += MV_CESA_MAX_DMA_DESC; -+ } -+ } -+ /*mvCesaCryptoIvSet(NULL, MV_CESA_MAX_IV_LENGTH);*/ -+ descOffsetReg = (MV_U16)((MV_U8*)&cesaSramVirtPtr->desc - mvCesaSramAddrGet()); -+ MV_REG_WRITE(MV_CESA_CHAN_DESC_OFFSET_REG, descOffsetReg); -+ -+ configReg |= (MV_CESA_CFG_WAIT_DMA_MASK | MV_CESA_CFG_ACT_DMA_MASK); -+#if (MV_CESA_VERSION >= 3) -+ configReg |= MV_CESA_CFG_CHAIN_MODE_MASK; -+#endif -+ -+#if (MV_CESA_VERSION >= 2) -+ /* Initialize TDMA engine */ -+ MV_REG_WRITE(MV_CESA_TDMA_CTRL_REG, MV_CESA_TDMA_CTRL_VALUE); -+ MV_REG_WRITE(MV_CESA_TDMA_BYTE_COUNT_REG, 0); -+ MV_REG_WRITE(MV_CESA_TDMA_CURR_DESC_PTR_REG, 0); -+#else -+ /* Initialize IDMA #0 engine */ -+ MV_REG_WRITE(IDMA_CTRL_LOW_REG(0), 0); -+ MV_REG_WRITE(IDMA_BYTE_COUNT_REG(0), 0); -+ MV_REG_WRITE(IDMA_CURR_DESC_PTR_REG(0), 0); -+ MV_REG_WRITE(IDMA_CTRL_HIGH_REG(0), ICCHR_ENDIAN_LITTLE -+#ifdef MV_CPU_LE -+ | ICCHR_DESC_BYTE_SWAP_EN -+#endif -+ ); -+ /* Clear Cause Byte of IDMA channel to be used */ -+ MV_REG_WRITE( IDMA_CAUSE_REG, ~ICICR_CAUSE_MASK_ALL(0)); -+ MV_REG_WRITE(IDMA_CTRL_LOW_REG(0), MV_CESA_IDMA_CTRL_LOW_VALUE); -+#endif /* (MV_CESA_VERSION >= 2) */ -+ -+ /* Set CESA configuration registers */ -+ MV_REG_WRITE( MV_CESA_CFG_REG, configReg); -+ mvCesaDebugStatsClear(); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaFinish - Shutdown the CESA driver -+* -+* DESCRIPTION: -+* This function shutdown the CESA driver and free all allocted resources. -+* -+* INPUT: None -+* -+* RETURN: -+* MV_OK - Success -+* Other - Fail -+* -+*******************************************************************************/ -+MV_STATUS mvCesaFinish (void) -+{ -+ int req; -+ MV_CESA_REQ* pReq; -+ -+ mvOsPrintf("mvCesaFinish: \n"); -+ -+ cesaSramVirtPtr = NULL; -+ -+ /* Free all resources: DMA list, etc. */ -+ for(req=0; reqdmaDescBuf.bufVirtPtr != NULL) -+ { -+ mvOsIoCachedFree(cesaOsHandle,pReq->dmaDescBuf.bufSize, -+ pReq->dmaDescBuf.bufPhysAddr, -+ pReq->dmaDescBuf.bufVirtPtr, -+ pReq->dmaDescBuf.memHandle); -+ } -+ if(pReq->cesaDescBuf.bufVirtPtr != NULL) -+ { -+ mvOsIoCachedFree(cesaOsHandle,pReq->cesaDescBuf.bufSize, -+ pReq->cesaDescBuf.bufPhysAddr, -+ pReq->cesaDescBuf.bufVirtPtr, -+ pReq->cesaDescBuf.memHandle); -+ } -+ } -+#if (MV_CESA_VERSION < 2) -+ MV_REG_WRITE(IDMA_CTRL_LOW_REG(0), 0); -+#endif /* (MV_CESA_VERSION < 2) */ -+ -+ /* Free request queue */ -+ if(pCesaReqFirst != NULL) -+ { -+ mvOsFree(pCesaReqFirst); -+ pCesaReqFirst = pCesaReqLast = NULL; -+ pCesaReqEmpty = pCesaReqProcess = NULL; -+ cesaQueueDepth = cesaReqResources = 0; -+ } -+ /* Free SA database */ -+ if(pCesaSAD != NULL) -+ { -+ mvOsFree(pCesaSAD); -+ pCesaSAD = NULL; -+ cesaMaxSA = 0; -+ } -+ MV_REG_WRITE( MV_CESA_CFG_REG, 0); -+ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); -+ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, 0); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaCryptoIvSet - Set IV value for Crypto algorithm working in CBC mode -+* -+* DESCRIPTION: -+* This function set IV value using by Crypto algorithms in CBC mode. -+* Each channel has its own IV value. -+* This function gets IV value from the caller. If no IV value passed from -+* the caller or only part of IV passed, the function will init the rest part -+* of IV value (or the whole IV) by random value. -+* -+* INPUT: -+* MV_U8* pIV - Pointer to IV value supplied by user. If pIV==NULL -+* the function will generate random IV value. -+* int ivSize - size (in bytes) of IV provided by user. If ivSize is -+* smaller than maximum IV size, the function will complete -+* IV by random value. -+* -+* RETURN: -+* MV_OK - Success -+* Other - Fail -+* -+*******************************************************************************/ -+MV_STATUS mvCesaCryptoIvSet(MV_U8* pIV, int ivSize) -+{ -+ MV_U8* pSramIV; -+#if defined(MV646xx) -+ mvOsPrintf("mvCesaCryptoIvSet: ERR. shouldn't use this call on MV64660\n"); -+#endif -+ pSramIV = cesaSramVirtPtr->cryptoIV; -+ if(ivSize > MV_CESA_MAX_IV_LENGTH) -+ { -+ mvOsPrintf("mvCesaCryptoIvSet: ivSize (%d) is too large\n", ivSize); -+ ivSize = MV_CESA_MAX_IV_LENGTH; -+ } -+ if(pIV != NULL) -+ { -+ memcpy(pSramIV, pIV, ivSize); -+ ivSize = MV_CESA_MAX_IV_LENGTH - ivSize; -+ pSramIV += ivSize; -+ } -+ -+ while(ivSize > 0) -+ { -+ int size, mv_random = mvOsRand(); -+ -+ size = MV_MIN(ivSize, sizeof(mv_random)); -+ memcpy(pSramIV, (void*)&mv_random, size); -+ -+ pSramIV += size; -+ ivSize -= size; -+ } -+/* -+ mvOsCacheFlush(NULL, cesaSramVirtPtr->cryptoIV, -+ MV_CESA_MAX_IV_LENGTH); -+ mvOsCacheInvalidate(NULL, cesaSramVirtPtr->cryptoIV, -+ MV_CESA_MAX_IV_LENGTH); -+*/ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaSessionOpen - Open new uni-directional crypto session -+* -+* DESCRIPTION: -+* This function open new session. -+* -+* INPUT: -+* MV_CESA_OPEN_SESSION *pSession - pointer to new session input parameters -+* -+* OUTPUT: -+* short *pSid - session ID, should be used for all future -+* requests over this session. -+* -+* RETURN: -+* MV_OK - Session opend successfully. -+* MV_FULL - All sessions are in use, no free place in -+* SA database. -+* MV_BAD_PARAM - One of session input parameters is invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvCesaSessionOpen(MV_CESA_OPEN_SESSION *pSession, short* pSid) -+{ -+ short sid; -+ MV_U32 config = 0; -+ int digestSize; -+ -+ cesaStats.openedCount++; -+ -+ /* Find free entry in SAD */ -+ for(sid=0; sidoperation >= MV_CESA_MAX_OPERATION) -+ { -+ mvOsPrintf("mvCesaSessionOpen: Unexpected operation %d\n", -+ pSession->operation); -+ return MV_BAD_PARAM; -+ } -+ config |= (pSession->operation << MV_CESA_OPERATION_OFFSET); -+ -+ if( (pSession->direction != MV_CESA_DIR_ENCODE) && -+ (pSession->direction != MV_CESA_DIR_DECODE) ) -+ { -+ mvOsPrintf("mvCesaSessionOpen: Unexpected direction %d\n", -+ pSession->direction); -+ return MV_BAD_PARAM; -+ } -+ config |= (pSession->direction << MV_CESA_DIRECTION_BIT); -+ /* Clear SA entry */ -+ /* memset(&pCesaSAD[sid], 0, sizeof(pCesaSAD[sid])); */ -+ -+ /* Check AUTH parameters and update SA entry */ -+ if(pSession->operation != MV_CESA_CRYPTO_ONLY) -+ { -+ /* For HMAC (MD5 and SHA1) - Maximum Key size is 64 bytes */ -+ if( (pSession->macMode == MV_CESA_MAC_HMAC_MD5) || -+ (pSession->macMode == MV_CESA_MAC_HMAC_SHA1) ) -+ { -+ if(pSession->macKeyLength > MV_CESA_MAX_MAC_KEY_LENGTH) -+ { -+ mvOsPrintf("mvCesaSessionOpen: macKeyLength %d is too large\n", -+ pSession->macKeyLength); -+ return MV_BAD_PARAM; -+ } -+ mvCesaHmacIvGet(pSession->macMode, pSession->macKey, pSession->macKeyLength, -+ pCesaSAD[sid].pSramSA->macInnerIV, -+ pCesaSAD[sid].pSramSA->macOuterIV); -+ pCesaSAD[sid].macKeyLength = pSession->macKeyLength; -+ } -+ switch(pSession->macMode) -+ { -+ case MV_CESA_MAC_MD5: -+ case MV_CESA_MAC_HMAC_MD5: -+ digestSize = MV_CESA_MD5_DIGEST_SIZE; -+ break; -+ -+ case MV_CESA_MAC_SHA1: -+ case MV_CESA_MAC_HMAC_SHA1: -+ digestSize = MV_CESA_SHA1_DIGEST_SIZE; -+ break; -+ -+ default: -+ mvOsPrintf("mvCesaSessionOpen: Unexpected macMode %d\n", -+ pSession->macMode); -+ return MV_BAD_PARAM; -+ } -+ config |= (pSession->macMode << MV_CESA_MAC_MODE_OFFSET); -+ -+ /* Supported digest sizes: MD5 - 16 bytes (128 bits), */ -+ /* SHA1 - 20 bytes (160 bits) or 12 bytes (96 bits) for both */ -+ if( (pSession->digestSize != digestSize) && (pSession->digestSize != 12)) -+ { -+ mvOsPrintf("mvCesaSessionOpen: Unexpected digest size %d\n", -+ pSession->digestSize); -+ mvOsPrintf("\t Valid values [bytes]: MD5-16, SHA1-20, Both-12\n"); -+ return MV_BAD_PARAM; -+ } -+ pCesaSAD[sid].digestSize = pSession->digestSize; -+ -+ if(pCesaSAD[sid].digestSize == 12) -+ { -+ /* Set MV_CESA_MAC_DIGEST_SIZE_BIT if digest size is 96 bits */ -+ config |= (MV_CESA_MAC_DIGEST_96B << MV_CESA_MAC_DIGEST_SIZE_BIT); -+ } -+ } -+ -+ /* Check CRYPTO parameters and update SA entry */ -+ if(pSession->operation != MV_CESA_MAC_ONLY) -+ { -+ switch(pSession->cryptoAlgorithm) -+ { -+ case MV_CESA_CRYPTO_DES: -+ pCesaSAD[sid].cryptoKeyLength = MV_CESA_DES_KEY_LENGTH; -+ pCesaSAD[sid].cryptoBlockSize = MV_CESA_DES_BLOCK_SIZE; -+ break; -+ -+ case MV_CESA_CRYPTO_3DES: -+ pCesaSAD[sid].cryptoKeyLength = MV_CESA_3DES_KEY_LENGTH; -+ pCesaSAD[sid].cryptoBlockSize = MV_CESA_DES_BLOCK_SIZE; -+ /* Only EDE mode is supported */ -+ config |= (MV_CESA_CRYPTO_3DES_EDE << -+ MV_CESA_CRYPTO_3DES_MODE_BIT); -+ break; -+ -+ case MV_CESA_CRYPTO_AES: -+ switch(pSession->cryptoKeyLength) -+ { -+ case 16: -+ pCesaSAD[sid].cryptoKeyLength = MV_CESA_AES_128_KEY_LENGTH; -+ config |= (MV_CESA_CRYPTO_AES_KEY_128 << -+ MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET); -+ break; -+ -+ case 24: -+ pCesaSAD[sid].cryptoKeyLength = MV_CESA_AES_192_KEY_LENGTH; -+ config |= (MV_CESA_CRYPTO_AES_KEY_192 << -+ MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET); -+ break; -+ -+ case 32: -+ default: -+ pCesaSAD[sid].cryptoKeyLength = MV_CESA_AES_256_KEY_LENGTH; -+ config |= (MV_CESA_CRYPTO_AES_KEY_256 << -+ MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET); -+ break; -+ } -+ pCesaSAD[sid].cryptoBlockSize = MV_CESA_AES_BLOCK_SIZE; -+ break; -+ -+ default: -+ mvOsPrintf("mvCesaSessionOpen: Unexpected cryptoAlgorithm %d\n", -+ pSession->cryptoAlgorithm); -+ return MV_BAD_PARAM; -+ } -+ config |= (pSession->cryptoAlgorithm << MV_CESA_CRYPTO_ALG_OFFSET); -+ -+ if(pSession->cryptoKeyLength != pCesaSAD[sid].cryptoKeyLength) -+ { -+ mvOsPrintf("cesaSessionOpen: Wrong CryptoKeySize %d != %d\n", -+ pSession->cryptoKeyLength, pCesaSAD[sid].cryptoKeyLength); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Copy Crypto key */ -+ if( (pSession->cryptoAlgorithm == MV_CESA_CRYPTO_AES) && -+ (pSession->direction == MV_CESA_DIR_DECODE)) -+ { -+ /* Crypto Key for AES decode is computed from original key material */ -+ /* and depend on cryptoKeyLength (128/192/256 bits) */ -+ aesMakeKey(pCesaSAD[sid].pSramSA->cryptoKey, pSession->cryptoKey, -+ pSession->cryptoKeyLength*8, MV_CESA_AES_BLOCK_SIZE*8); -+ } -+ else -+ { -+ /*panic("mvCesaSessionOpen2");*/ -+ memcpy(pCesaSAD[sid].pSramSA->cryptoKey, pSession->cryptoKey, -+ pCesaSAD[sid].cryptoKeyLength); -+ -+ } -+ -+ switch(pSession->cryptoMode) -+ { -+ case MV_CESA_CRYPTO_ECB: -+ pCesaSAD[sid].cryptoIvSize = 0; -+ break; -+ -+ case MV_CESA_CRYPTO_CBC: -+ pCesaSAD[sid].cryptoIvSize = pCesaSAD[sid].cryptoBlockSize; -+ break; -+ -+ case MV_CESA_CRYPTO_CTR: -+ /* Supported only for AES algorithm */ -+ if(pSession->cryptoAlgorithm != MV_CESA_CRYPTO_AES) -+ { -+ mvOsPrintf("mvCesaSessionOpen: CRYPTO CTR mode supported for AES only\n"); -+ return MV_BAD_PARAM; -+ } -+ pCesaSAD[sid].cryptoIvSize = 0; -+ pCesaSAD[sid].ctrMode = 1; -+ /* Replace to ECB mode for HW */ -+ pSession->cryptoMode = MV_CESA_CRYPTO_ECB; -+ break; -+ -+ default: -+ mvOsPrintf("mvCesaSessionOpen: Unexpected cryptoMode %d\n", -+ pSession->cryptoMode); -+ return MV_BAD_PARAM; -+ } -+ -+ config |= (pSession->cryptoMode << MV_CESA_CRYPTO_MODE_BIT); -+ } -+ pCesaSAD[sid].config = config; -+ -+ mvOsCacheFlush(NULL, pCesaSAD[sid].pSramSA, sizeof(MV_CESA_SRAM_SA)); -+ if(pSid != NULL) -+ *pSid = sid; -+ -+ pCesaSAD[sid].valid = 1; -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaSessionClose - Close active crypto session -+* -+* DESCRIPTION: -+* This function closes existing session -+* -+* INPUT: -+* short sid - Unique identifier of the session to be closed -+* -+* RETURN: -+* MV_OK - Session closed successfully. -+* MV_BAD_PARAM - Session identifier is out of valid range. -+* MV_NOT_FOUND - There is no active session with such ID. -+* -+*******************************************************************************/ -+MV_STATUS mvCesaSessionClose(short sid) -+{ -+ cesaStats.closedCount++; -+ -+ if(sid >= cesaMaxSA) -+ { -+ mvOsPrintf("CESA Error: sid (%d) is too big\n", sid); -+ return MV_BAD_PARAM; -+ } -+ if(pCesaSAD[sid].valid == 0) -+ { -+ mvOsPrintf("CESA Warning: Session (sid=%d) is invalid\n", sid); -+ return MV_NOT_FOUND; -+ } -+ if(cesaLastSid == sid) -+ cesaLastSid = -1; -+ -+ pCesaSAD[sid].valid = 0; -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaAction - Perform crypto operation -+* -+* DESCRIPTION: -+* This function set new CESA request FIFO queue for further HW processing. -+* The function checks request parameters before set new request to the queue. -+* If one of the CESA channels is ready for processing the request will be -+* passed to HW. When request processing is finished the CESA interrupt will -+* be generated by HW. The caller should call mvCesaReadyGet() function to -+* complete request processing and get result. -+* -+* INPUT: -+* MV_CESA_COMMAND *pCmd - pointer to new CESA request. -+* It includes pointers to Source and Destination -+* buffers, session identifier get from -+* mvCesaSessionOpen() function, pointer to caller -+* private data and all needed crypto parameters. -+* -+* RETURN: -+* MV_OK - request successfully added to request queue -+* and will be processed. -+* MV_NO_MORE - request successfully added to request queue and will -+* be processed, but request queue became Full and next -+* request will not be accepted. -+* MV_NO_RESOURCE - request queue is FULL and the request can not -+* be processed. -+* MV_OUT_OF_CPU_MEM - memory allocation needed for request processing is -+* failed. Request can not be processed. -+* MV_NOT_ALLOWED - This mixed request (CRYPTO+MAC) can not be processed -+* as one request and should be splitted for two requests: -+* CRYPTO_ONLY and MAC_ONLY. -+* MV_BAD_PARAM - One of the request parameters is out of valid range. -+* The request can not be processed. -+* -+*******************************************************************************/ -+MV_STATUS mvCesaAction (MV_CESA_COMMAND *pCmd) -+{ -+ MV_STATUS status; -+ MV_CESA_REQ* pReq = pCesaReqEmpty; -+ int sid = pCmd->sessionId; -+ MV_CESA_SA* pSA = &pCesaSAD[sid]; -+#if (MV_CESA_VERSION >= 3) -+ MV_CESA_REQ* pFromReq; -+ MV_CESA_REQ* pToReq; -+#endif -+ cesaStats.reqCount++; -+ -+ /* Check that the request queue is not FULL */ -+ if(cesaReqResources == 0) -+ return MV_NO_RESOURCE; -+ -+ if( (sid >= cesaMaxSA) || (!pSA->valid) ) -+ { -+ mvOsPrintf("CESA Action Error: Session sid=%d is INVALID\n", sid); -+ return MV_BAD_PARAM; -+ } -+ pSA->count++; -+ -+ if(pSA->ctrMode) -+ { -+ /* AES in CTR mode can't be mixed with Authentication */ -+ if( (pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ mvOsPrintf("mvCesaAction : CRYPTO CTR mode can't be mixed with AUTH\n"); -+ return MV_NOT_ALLOWED; -+ } -+ /* All other request parameters should not be checked because key stream */ -+ /* (not user data) processed by AES HW engine */ -+ pReq->pOrgCmd = pCmd; -+ /* Allocate temporary pCmd structure for Key stream */ -+ pCmd = mvCesaCtrModeInit(); -+ if(pCmd == NULL) -+ return MV_OUT_OF_CPU_MEM; -+ -+ /* Prepare Key stream */ -+ mvCesaCtrModePrepare(pCmd, pReq->pOrgCmd); -+ pReq->fixOffset = 0; -+ } -+ else -+ { -+ /* Check request parameters and calculae fixOffset */ -+ status = mvCesaParamCheck(pSA, pCmd, &pReq->fixOffset); -+ if(status != MV_OK) -+ { -+ return status; -+ } -+ } -+ pReq->pCmd = pCmd; -+ -+ /* Check if the packet need fragmentation */ -+ if(pCmd->pSrc->mbufSize <= sizeof(cesaSramVirtPtr->buf) ) -+ { -+ /* request size is smaller than single buffer size */ -+ pReq->fragMode = MV_CESA_FRAG_NONE; -+ -+ /* Prepare NOT fragmented packets */ -+ status = mvCesaReqProcess(pReq); -+ if(status != MV_OK) -+ { -+ mvOsPrintf("CesaReady: ReqProcess error: pReq=%p, status=0x%x\n", -+ pReq, status); -+ } -+#if (MV_CESA_VERSION >= 3) -+ pReq->frags.numFrag = 1; -+#endif -+ } -+ else -+ { -+ MV_U8 frag = 0; -+ -+ /* request size is larger than buffer size - needs fragmentation */ -+ -+ /* Check restrictions for processing fragmented packets */ -+ status = mvCesaFragParamCheck(pSA, pCmd); -+ if(status != MV_OK) -+ return status; -+ -+ pReq->fragMode = MV_CESA_FRAG_FIRST; -+ pReq->frags.nextFrag = 0; -+ -+ /* Prepare Process Fragmented packets */ -+ while(pReq->fragMode != MV_CESA_FRAG_LAST) -+ { -+ if(frag >= MV_CESA_MAX_REQ_FRAGS) -+ { -+ mvOsPrintf("mvCesaAction Error: Too large request frag=%d\n", frag); -+ return MV_OUT_OF_CPU_MEM; -+ } -+ status = mvCesaFragReqProcess(pReq, frag); -+ if(status == MV_OK) { -+#if (MV_CESA_VERSION >= 3) -+ if(frag) { -+ pReq->dma[frag-1].pDmaLast->phyNextDescPtr = -+ MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, pReq->dma[frag].pDmaFirst)); -+ mvOsCacheFlush(NULL, pReq->dma[frag-1].pDmaLast, sizeof(MV_DMA_DESC)); -+ } -+#endif -+ frag++; -+ } -+ } -+ pReq->frags.numFrag = frag; -+#if (MV_CESA_VERSION >= 3) -+ if(chainReqNum) { -+ chainReqNum += pReq->frags.numFrag; -+ if(chainReqNum >= MAX_CESA_CHAIN_LENGTH) -+ chainReqNum = MAX_CESA_CHAIN_LENGTH; -+ } -+#endif -+ } -+ -+ pReq->state = MV_CESA_PENDING; -+ -+ pCesaReqEmpty = MV_CESA_REQ_NEXT_PTR(pReq); -+ cesaReqResources -= 1; -+ -+/* #ifdef CESA_DEBUG */ -+ if( (cesaQueueDepth - cesaReqResources) > cesaStats.maxReqCount) -+ cesaStats.maxReqCount = (cesaQueueDepth - cesaReqResources); -+/* #endif CESA_DEBUG */ -+ -+ cesaLastSid = sid; -+ -+#if (MV_CESA_VERSION >= 3) -+ /* Are we within chain bounderies and follows the first request ? */ -+ if((chainReqNum > 0) && (chainReqNum < MAX_CESA_CHAIN_LENGTH)) { -+ if(chainIndex) { -+ pFromReq = MV_CESA_REQ_PREV_PTR(pReq); -+ pToReq = pReq; -+ pReq->state = MV_CESA_CHAIN; -+ /* assume concatenating is possible */ -+ pFromReq->dma[pFromReq->frags.numFrag-1].pDmaLast->phyNextDescPtr = -+ MV_32BIT_LE(mvCesaVirtToPhys(&pToReq->dmaDescBuf, pToReq->dma[0].pDmaFirst)); -+ mvOsCacheFlush(NULL, pFromReq->dma[pFromReq->frags.numFrag-1].pDmaLast, sizeof(MV_DMA_DESC)); -+ -+ /* align active & next pointers */ -+ if(pNextActiveChain->state != MV_CESA_PENDING) -+ pEndCurrChain = pNextActiveChain = MV_CESA_REQ_NEXT_PTR(pReq); -+ } -+ else { /* we have only one chain, start new one */ -+ chainReqNum = 0; -+ chainIndex++; -+ /* align active & next pointers */ -+ if(pNextActiveChain->state != MV_CESA_PENDING) -+ pEndCurrChain = pNextActiveChain = pReq; -+ } -+ } -+ else { -+ /* In case we concatenate full chain */ -+ if(chainReqNum == MAX_CESA_CHAIN_LENGTH) { -+ chainIndex++; -+ if(pNextActiveChain->state != MV_CESA_PENDING) -+ pEndCurrChain = pNextActiveChain = pReq; -+ chainReqNum = 0; -+ } -+ -+ pReq = pCesaReqProcess; -+ if(pReq->state == MV_CESA_PENDING) { -+ pNextActiveChain = pReq; -+ pEndCurrChain = MV_CESA_REQ_NEXT_PTR(pReq); -+ /* Start Process new request */ -+ mvCesaReqProcessStart(pReq); -+ } -+ } -+ -+ chainReqNum++; -+ -+ if((chainIndex < MAX_CESA_CHAIN_LENGTH) && (chainReqNum > cesaStats.maxChainUsage)) -+ cesaStats.maxChainUsage = chainReqNum; -+ -+#else -+ -+ /* Check status of CESA channels and process requests if possible */ -+ pReq = pCesaReqProcess; -+ if(pReq->state == MV_CESA_PENDING) -+ { -+ /* Start Process new request */ -+ mvCesaReqProcessStart(pReq); -+ } -+#endif -+ /* If request queue became FULL - return MV_NO_MORE */ -+ if(cesaReqResources == 0) -+ return MV_NO_MORE; -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvCesaReadyGet - Get crypto request that processing is finished -+* -+* DESCRIPTION: -+* This function complete request processing and return ready request to -+* caller. To don't miss interrupts the caller must call this function -+* while MV_OK or MV_TERMINATE values returned. -+* -+* INPUT: -+* MV_U32 chanMap - map of CESA channels finished thier job -+* accordingly with CESA Cause register. -+* MV_CESA_RESULT* pResult - pointer to structure contains information -+* about ready request. It includes pointer to -+* user private structure "pReqPrv", session identifier -+* for this request "sessionId" and return code. -+* Return code set to MV_FAIL if calculated digest value -+* on decode direction is different than digest value -+* in the packet. -+* -+* RETURN: -+* MV_OK - Success, ready request is returned. -+* MV_NOT_READY - Next request is not ready yet. New interrupt will -+* be generated for futher request processing. -+* MV_EMPTY - There is no more request for processing. -+* MV_BUSY - Fragmented request is not ready yet. -+* MV_TERMINATE - Call this function once more to complete processing -+* of fragmented request. -+* -+*******************************************************************************/ -+MV_STATUS mvCesaReadyGet(MV_CESA_RESULT* pResult) -+{ -+ MV_STATUS status, readyStatus = MV_NOT_READY; -+ MV_U32 statusReg; -+ MV_CESA_REQ* pReq; -+ MV_CESA_SA* pSA; -+ -+#if (MV_CESA_VERSION >= 3) -+ if(isFirstReq == MV_TRUE) { -+ if(chainIndex == 0) -+ chainReqNum = 0; -+ -+ isFirstReq = MV_FALSE; -+ -+ if(pNextActiveChain->state == MV_CESA_PENDING) { -+ /* Start request Process */ -+ mvCesaReqProcessStart(pNextActiveChain); -+ pEndCurrChain = pNextActiveChain; -+ if(chainIndex > 0) -+ chainIndex--; -+ /* Update pNextActiveChain to next chain head */ -+ while(pNextActiveChain->state == MV_CESA_CHAIN) -+ pNextActiveChain = MV_CESA_REQ_NEXT_PTR(pNextActiveChain); -+ } -+ } -+ -+ /* Check if there are more processed requests - can we remove pEndCurrChain ??? */ -+ if(pCesaReqProcess == pEndCurrChain) { -+ isFirstReq = MV_TRUE; -+ pEndCurrChain = pNextActiveChain; -+#else -+ if(pCesaReqProcess->state != MV_CESA_PROCESS) { -+#endif -+ return MV_EMPTY; -+ } -+ -+#ifdef CESA_DEBUG -+ statusReg = MV_REG_READ(MV_CESA_STATUS_REG); -+ if( statusReg & MV_CESA_STATUS_ACTIVE_MASK ) -+ { -+ mvOsPrintf("mvCesaReadyGet: Not Ready, Status = 0x%x\n", statusReg); -+ cesaStats.notReadyCount++; -+ return MV_NOT_READY; -+ } -+#endif /* CESA_DEBUG */ -+ -+ cesaStats.readyCount++; -+ -+ pReq = pCesaReqProcess; -+ pSA = &pCesaSAD[pReq->pCmd->sessionId]; -+ -+ pResult->retCode = MV_OK; -+ if(pReq->fragMode != MV_CESA_FRAG_NONE) -+ { -+ MV_U8* pNewDigest; -+ int frag; -+#if (MV_CESA_VERSION >= 3) -+ pReq->frags.nextFrag = 1; -+ while(pReq->frags.nextFrag <= pReq->frags.numFrag) { -+#endif -+ frag = (pReq->frags.nextFrag - 1); -+ -+ /* Restore DMA descriptor list */ -+ pReq->dma[frag].pDmaLast->phyNextDescPtr = -+ MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, &pReq->dma[frag].pDmaLast[1])); -+ pReq->dma[frag].pDmaLast = NULL; -+ -+ /* Special processing for finished fragmented request */ -+ if(pReq->frags.nextFrag >= pReq->frags.numFrag) -+ { -+ mvCesaMbufCacheUnmap(pReq->pCmd->pDst, 0, pReq->pCmd->pDst->mbufSize); -+ -+ /* Fragmented packet is ready */ -+ if( (pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ int macDataSize = pReq->pCmd->macLength - pReq->frags.macSize; -+ -+ if(macDataSize != 0) -+ { -+ /* Calculate all other blocks by SW */ -+ mvCesaFragAuthComplete(pReq, pSA, macDataSize); -+ } -+ -+ /* Copy new digest from SRAM to the Destination buffer */ -+ pNewDigest = cesaSramVirtPtr->buf + pReq->frags.newDigestOffset; -+ status = mvCesaCopyToMbuf(pNewDigest, pReq->pCmd->pDst, -+ pReq->pCmd->digestOffset, pSA->digestSize); -+ -+ /* For decryption: Compare new digest value with original one */ -+ if((pSA->config & MV_CESA_DIRECTION_MASK) == -+ (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) -+ { -+ if( memcmp(pNewDigest, pReq->frags.orgDigest, pSA->digestSize) != 0) -+ { -+/* -+ mvOsPrintf("Digest error: chan=%d, newDigest=%p, orgDigest=%p, status = 0x%x\n", -+ chan, pNewDigest, pReq->frags.orgDigest, MV_REG_READ(MV_CESA_STATUS_REG)); -+*/ -+ /* Signiture verification is failed */ -+ pResult->retCode = MV_FAIL; -+ } -+ } -+ } -+ readyStatus = MV_OK; -+ } -+#if (MV_CESA_VERSION >= 3) -+ pReq->frags.nextFrag++; -+ } -+#endif -+ } -+ else -+ { -+ mvCesaMbufCacheUnmap(pReq->pCmd->pDst, 0, pReq->pCmd->pDst->mbufSize); -+ -+ /* Restore DMA descriptor list */ -+ pReq->dma[0].pDmaLast->phyNextDescPtr = -+ MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, &pReq->dma[0].pDmaLast[1])); -+ pReq->dma[0].pDmaLast = NULL; -+ if( ((pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) && -+ ((pSA->config & MV_CESA_DIRECTION_MASK) == -+ (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) ) -+ { -+ /* For AUTH on decode : Check Digest result in Status register */ -+ statusReg = MV_REG_READ(MV_CESA_STATUS_REG); -+ if(statusReg & MV_CESA_STATUS_DIGEST_ERR_MASK) -+ { -+/* -+ mvOsPrintf("Digest error: chan=%d, status = 0x%x\n", -+ chan, statusReg); -+*/ -+ /* Signiture verification is failed */ -+ pResult->retCode = MV_FAIL; -+ } -+ } -+ readyStatus = MV_OK; -+ } -+ -+ if(readyStatus == MV_OK) -+ { -+ /* If Request is ready - Prepare pResult structure */ -+ pResult->pReqPrv = pReq->pCmd->pReqPrv; -+ pResult->sessionId = pReq->pCmd->sessionId; -+ -+ pReq->state = MV_CESA_IDLE; -+ pCesaReqProcess = MV_CESA_REQ_NEXT_PTR(pReq); -+ cesaReqResources++; -+ -+ if(pSA->ctrMode) -+ { -+ /* For AES CTR mode - complete processing and free allocated resources */ -+ mvCesaCtrModeComplete(pReq->pOrgCmd, pReq->pCmd); -+ mvCesaCtrModeFinish(pReq->pCmd); -+ pReq->pOrgCmd = NULL; -+ } -+ } -+ -+#if (MV_CESA_VERSION < 3) -+ if(pCesaReqProcess->state == MV_CESA_PROCESS) -+ { -+ /* Start request Process */ -+ mvCesaReqProcessStart(pCesaReqProcess); -+ if(readyStatus == MV_NOT_READY) -+ readyStatus = MV_BUSY; -+ } -+ else if(pCesaReqProcess != pCesaReqEmpty) -+ { -+ /* Start process new request from the queue */ -+ mvCesaReqProcessStart(pCesaReqProcess); -+ } -+#endif -+ return readyStatus; -+} -+ -+/***************** Functions to work with CESA_MBUF structure ******************/ -+ -+/******************************************************************************* -+* mvCesaMbufOffset - Locate offset in the Mbuf structure -+* -+* DESCRIPTION: -+* This function locates offset inside Multi-Bufeer structure. -+* It get fragment number and place in the fragment where the offset -+* is located. -+* -+* -+* INPUT: -+* MV_CESA_MBUF* pMbuf - Pointer to multi-buffer structure -+* int offset - Offset from the beginning of the data presented by -+* the Mbuf structure. -+* -+* OUTPUT: -+* int* pBufOffset - Offset from the beginning of the fragment where -+* the offset is located. -+* -+* RETURN: -+* int - Number of fragment, where the offset is located\ -+* -+*******************************************************************************/ -+int mvCesaMbufOffset(MV_CESA_MBUF* pMbuf, int offset, int* pBufOffset) -+{ -+ int frag = 0; -+ -+ while(offset > 0) -+ { -+ if(frag >= pMbuf->numFrags) -+ { -+ mvOsPrintf("mvCesaMbufOffset: Error: frag (%d) > numFrags (%d)\n", -+ frag, pMbuf->numFrags); -+ return MV_INVALID; -+ } -+ if(offset < pMbuf->pFrags[frag].bufSize) -+ { -+ break; -+ } -+ offset -= pMbuf->pFrags[frag].bufSize; -+ frag++; -+ } -+ if(pBufOffset != NULL) -+ *pBufOffset = offset; -+ -+ return frag; -+} -+ -+/******************************************************************************* -+* mvCesaCopyFromMbuf - Copy data from the Mbuf structure to continuous buffer -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_U8* pDstBuf - Pointer to continuous buffer, where data is -+* copied to. -+* MV_CESA_MBUF* pSrcMbuf - Pointer to multi-buffer structure where data is -+* copied from. -+* int offset - Offset in the Mbuf structure where located first -+* byte of data should be copied. -+* int size - Size of data should be copied -+* -+* RETURN: -+* MV_OK - Success, all data is copied successfully. -+* MV_OUT_OF_RANGE - Failed, offset is out of Multi-buffer data range. -+* No data is copied. -+* MV_EMPTY - Multi-buffer structure has not enough data to copy -+* Data from the offset to end of Mbuf data is copied. -+* -+*******************************************************************************/ -+MV_STATUS mvCesaCopyFromMbuf(MV_U8* pDstBuf, MV_CESA_MBUF* pSrcMbuf, -+ int offset, int size) -+{ -+ int frag, fragOffset, bufSize; -+ MV_U8* pBuf; -+ -+ if(size == 0) -+ return MV_OK; -+ -+ frag = mvCesaMbufOffset(pSrcMbuf, offset, &fragOffset); -+ if(frag == MV_INVALID) -+ { -+ mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); -+ return MV_OUT_OF_RANGE; -+ } -+ -+ bufSize = pSrcMbuf->pFrags[frag].bufSize - fragOffset; -+ pBuf = pSrcMbuf->pFrags[frag].bufVirtPtr + fragOffset; -+ while(MV_TRUE) -+ { -+ if(size <= bufSize) -+ { -+ memcpy(pDstBuf, pBuf, size); -+ return MV_OK; -+ } -+ memcpy(pDstBuf, pBuf, bufSize); -+ size -= bufSize; -+ frag++; -+ pDstBuf += bufSize; -+ if(frag >= pSrcMbuf->numFrags) -+ break; -+ -+ bufSize = pSrcMbuf->pFrags[frag].bufSize; -+ pBuf = pSrcMbuf->pFrags[frag].bufVirtPtr; -+ } -+ mvOsPrintf("mvCesaCopyFromMbuf: Mbuf is EMPTY - %d bytes isn't copied\n", -+ size); -+ return MV_EMPTY; -+} -+ -+/******************************************************************************* -+* mvCesaCopyToMbuf - Copy data from continuous buffer to the Mbuf structure -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_U8* pSrcBuf - Pointer to continuous buffer, where data is -+* copied from. -+* MV_CESA_MBUF* pDstMbuf - Pointer to multi-buffer structure where data is -+* copied to. -+* int offset - Offset in the Mbuf structure where located first -+* byte of data should be copied. -+* int size - Size of data should be copied -+* -+* RETURN: -+* MV_OK - Success, all data is copied successfully. -+* MV_OUT_OF_RANGE - Failed, offset is out of Multi-buffer data range. -+* No data is copied. -+* MV_FULL - Multi-buffer structure has not enough place to copy -+* all data. Data from the offset to end of Mbuf data -+* is copied. -+* -+*******************************************************************************/ -+MV_STATUS mvCesaCopyToMbuf(MV_U8* pSrcBuf, MV_CESA_MBUF* pDstMbuf, -+ int offset, int size) -+{ -+ int frag, fragOffset, bufSize; -+ MV_U8* pBuf; -+ -+ if(size == 0) -+ return MV_OK; -+ -+ frag = mvCesaMbufOffset(pDstMbuf, offset, &fragOffset); -+ if(frag == MV_INVALID) -+ { -+ mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); -+ return MV_OUT_OF_RANGE; -+ } -+ -+ bufSize = pDstMbuf->pFrags[frag].bufSize - fragOffset; -+ pBuf = pDstMbuf->pFrags[frag].bufVirtPtr + fragOffset; -+ while(MV_TRUE) -+ { -+ if(size <= bufSize) -+ { -+ memcpy(pBuf, pSrcBuf, size); -+ return MV_OK; -+ } -+ memcpy(pBuf, pSrcBuf, bufSize); -+ size -= bufSize; -+ frag++; -+ pSrcBuf += bufSize; -+ if(frag >= pDstMbuf->numFrags) -+ break; -+ -+ bufSize = pDstMbuf->pFrags[frag].bufSize; -+ pBuf = pDstMbuf->pFrags[frag].bufVirtPtr; -+ } -+ mvOsPrintf("mvCesaCopyToMbuf: Mbuf is FULL - %d bytes isn't copied\n", -+ size); -+ return MV_FULL; -+} -+ -+/******************************************************************************* -+* mvCesaMbufCopy - Copy data from one Mbuf structure to the other Mbuf structure -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* -+* MV_CESA_MBUF* pDstMbuf - Pointer to multi-buffer structure where data is -+* copied to. -+* int dstMbufOffset - Offset in the dstMbuf structure where first byte -+* of data should be copied to. -+* MV_CESA_MBUF* pSrcMbuf - Pointer to multi-buffer structure where data is -+* copied from. -+* int srcMbufOffset - Offset in the srcMbuf structure where first byte -+* of data should be copied from. -+* int size - Size of data should be copied -+* -+* RETURN: -+* MV_OK - Success, all data is copied successfully. -+* MV_OUT_OF_RANGE - Failed, srcMbufOffset or dstMbufOffset is out of -+* srcMbuf or dstMbuf structure correspondently. -+* No data is copied. -+* MV_BAD_SIZE - srcMbuf or dstMbuf structure is too small to copy -+* all data. Partial data is copied -+* -+*******************************************************************************/ -+MV_STATUS mvCesaMbufCopy(MV_CESA_MBUF* pMbufDst, int dstMbufOffset, -+ MV_CESA_MBUF* pMbufSrc, int srcMbufOffset, int size) -+{ -+ int srcFrag, dstFrag, srcSize, dstSize, srcOffset, dstOffset; -+ int copySize; -+ MV_U8 *pSrc, *pDst; -+ -+ if(size == 0) -+ return MV_OK; -+ -+ srcFrag = mvCesaMbufOffset(pMbufSrc, srcMbufOffset, &srcOffset); -+ if(srcFrag == MV_INVALID) -+ { -+ mvOsPrintf("CESA srcMbuf Error: offset (%d) out of range\n", srcMbufOffset); -+ return MV_OUT_OF_RANGE; -+ } -+ pSrc = pMbufSrc->pFrags[srcFrag].bufVirtPtr + srcOffset; -+ srcSize = pMbufSrc->pFrags[srcFrag].bufSize - srcOffset; -+ -+ dstFrag = mvCesaMbufOffset(pMbufDst, dstMbufOffset, &dstOffset); -+ if(dstFrag == MV_INVALID) -+ { -+ mvOsPrintf("CESA dstMbuf Error: offset (%d) out of range\n", dstMbufOffset); -+ return MV_OUT_OF_RANGE; -+ } -+ pDst = pMbufDst->pFrags[dstFrag].bufVirtPtr + dstOffset; -+ dstSize = pMbufDst->pFrags[dstFrag].bufSize - dstOffset; -+ -+ while(size > 0) -+ { -+ copySize = MV_MIN(srcSize, dstSize); -+ if(size <= copySize) -+ { -+ memcpy(pDst, pSrc, size); -+ return MV_OK; -+ } -+ memcpy(pDst, pSrc, copySize); -+ size -= copySize; -+ srcSize -= copySize; -+ dstSize -= copySize; -+ -+ if(srcSize == 0) -+ { -+ srcFrag++; -+ if(srcFrag >= pMbufSrc->numFrags) -+ break; -+ -+ pSrc = pMbufSrc->pFrags[srcFrag].bufVirtPtr; -+ srcSize = pMbufSrc->pFrags[srcFrag].bufSize; -+ } -+ -+ if(dstSize == 0) -+ { -+ dstFrag++; -+ if(dstFrag >= pMbufDst->numFrags) -+ break; -+ -+ pDst = pMbufDst->pFrags[dstFrag].bufVirtPtr; -+ dstSize = pMbufDst->pFrags[dstFrag].bufSize; -+ } -+ } -+ mvOsPrintf("mvCesaMbufCopy: BAD size - %d bytes isn't copied\n", -+ size); -+ -+ return MV_BAD_SIZE; -+} -+ -+static MV_STATUS mvCesaMbufCacheUnmap(MV_CESA_MBUF* pMbuf, int offset, int size) -+{ -+ int frag, fragOffset, bufSize; -+ MV_U8* pBuf; -+ -+ if(size == 0) -+ return MV_OK; -+ -+ frag = mvCesaMbufOffset(pMbuf, offset, &fragOffset); -+ if(frag == MV_INVALID) -+ { -+ mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); -+ return MV_OUT_OF_RANGE; -+ } -+ -+ bufSize = pMbuf->pFrags[frag].bufSize - fragOffset; -+ pBuf = pMbuf->pFrags[frag].bufVirtPtr + fragOffset; -+ while(MV_TRUE) -+ { -+ if(size <= bufSize) -+ { -+ mvOsCacheUnmap(NULL, mvOsIoVirtToPhy(NULL, pBuf), size); -+ return MV_OK; -+ } -+ -+ mvOsCacheUnmap(NULL, mvOsIoVirtToPhy(NULL, pBuf), bufSize); -+ size -= bufSize; -+ frag++; -+ if(frag >= pMbuf->numFrags) -+ break; -+ -+ bufSize = pMbuf->pFrags[frag].bufSize; -+ pBuf = pMbuf->pFrags[frag].bufVirtPtr; -+ } -+ mvOsPrintf("%s: Mbuf is FULL - %d bytes isn't Unmapped\n", -+ __FUNCTION__, size); -+ return MV_FULL; -+} -+ -+ -+/*************************************** Local Functions ******************************/ -+ -+/******************************************************************************* -+* mvCesaFragReqProcess - Process fragmented request -+* -+* DESCRIPTION: -+* This function processes a fragment of fragmented request (First, Middle or Last) -+* -+* -+* INPUT: -+* MV_CESA_REQ* pReq - Pointer to the request in the request queue. -+* -+* RETURN: -+* MV_OK - The fragment is successfully passed to HW for processing. -+* MV_TERMINATE - Means, that HW finished its work on this packet and no more -+* interrupts will be generated for this request. -+* Function mvCesaReadyGet() must be called to complete request -+* processing and get request result. -+* -+*******************************************************************************/ -+static MV_STATUS mvCesaFragReqProcess(MV_CESA_REQ* pReq, MV_U8 frag) -+{ -+ int i, copySize, cryptoDataSize, macDataSize, sid; -+ int cryptoIvOffset, digestOffset; -+ MV_U32 config; -+ MV_CESA_COMMAND* pCmd = pReq->pCmd; -+ MV_CESA_SA* pSA; -+ MV_CESA_MBUF* pMbuf; -+ MV_DMA_DESC* pDmaDesc = pReq->dma[frag].pDmaFirst; -+ MV_U8* pSramBuf = cesaSramVirtPtr->buf; -+ int macTotalLen = 0; -+ int fixOffset, cryptoOffset, macOffset; -+ -+ cesaStats.fragCount++; -+ -+ sid = pReq->pCmd->sessionId; -+ -+ pSA = &pCesaSAD[sid]; -+ -+ cryptoIvOffset = digestOffset = 0; -+ i = macDataSize = 0; -+ cryptoDataSize = 0; -+ -+ /* First fragment processing */ -+ if(pReq->fragMode == MV_CESA_FRAG_FIRST) -+ { -+ /* pReq->frags monitors processing of fragmented request between fragments */ -+ pReq->frags.bufOffset = 0; -+ pReq->frags.cryptoSize = 0; -+ pReq->frags.macSize = 0; -+ -+ config = pSA->config | (MV_CESA_FRAG_FIRST << MV_CESA_FRAG_MODE_OFFSET); -+ -+ /* fixOffset can be not equal to zero only for FIRST fragment */ -+ fixOffset = pReq->fixOffset; -+ /* For FIRST fragment crypto and mac offsets are taken from pCmd */ -+ cryptoOffset = pCmd->cryptoOffset; -+ macOffset = pCmd->macOffset; -+ -+ copySize = sizeof(cesaSramVirtPtr->buf) - pReq->fixOffset; -+ -+ /* Find fragment size: Must meet all requirements for CRYPTO and MAC -+ * cryptoDataSize - size of data will be encrypted/decrypted in this fragment -+ * macDataSize - size of data will be signed/verified in this fragment -+ * copySize - size of data will be copied from srcMbuf to SRAM and -+ * back to dstMbuf for this fragment -+ */ -+ mvCesaFragSizeFind(pSA, pReq, cryptoOffset, macOffset, -+ ©Size, &cryptoDataSize, &macDataSize); -+ -+ if( (pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) -+ { -+ /* CryptoIV special processing */ -+ if( (pSA->config & MV_CESA_CRYPTO_MODE_MASK) == -+ (MV_CESA_CRYPTO_CBC << MV_CESA_CRYPTO_MODE_BIT) ) -+ { -+ /* In CBC mode for encode direction when IV from user */ -+ if( (pCmd->ivFromUser) && -+ ((pSA->config & MV_CESA_DIRECTION_MASK) == -+ (MV_CESA_DIR_ENCODE << MV_CESA_DIRECTION_BIT)) ) -+ { -+ -+ /* For Crypto Encode in CBC mode HW always takes IV from SRAM IVPointer, -+ * (not from IVBufPointer). So when ivFromUser==1, we should copy IV from user place -+ * in the buffer to SRAM IVPointer -+ */ -+ i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->cryptoIV, &pDmaDesc[i], -+ MV_FALSE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); -+ } -+ -+ /* Special processing when IV is not located in the first fragment */ -+ if(pCmd->ivOffset > (copySize - pSA->cryptoIvSize)) -+ { -+ /* Prepare dummy place for cryptoIV in SRAM */ -+ cryptoIvOffset = cesaSramVirtPtr->tempCryptoIV - mvCesaSramAddrGet(); -+ -+ /* For Decryption: Copy IV value from pCmd->ivOffset to Special SRAM place */ -+ if((pSA->config & MV_CESA_DIRECTION_MASK) == -+ (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) -+ { -+ i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->tempCryptoIV, &pDmaDesc[i], -+ MV_FALSE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); -+ } -+ else -+ { -+ /* For Encryption when IV is NOT from User: */ -+ /* Copy IV from SRAM to buffer (pCmd->ivOffset) */ -+ if(pCmd->ivFromUser == 0) -+ { -+ /* copy IV value from cryptoIV to Buffer (pCmd->ivOffset) */ -+ i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->cryptoIV, &pDmaDesc[i], -+ MV_TRUE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); -+ } -+ } -+ } -+ else -+ { -+ cryptoIvOffset = pCmd->ivOffset; -+ } -+ } -+ } -+ -+ if( (pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ /* MAC digest special processing on Decode direction */ -+ if((pSA->config & MV_CESA_DIRECTION_MASK) == -+ (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) -+ { -+ /* Save digest from pCmd->digestOffset */ -+ mvCesaCopyFromMbuf(pReq->frags.orgDigest, -+ pCmd->pSrc, pCmd->digestOffset, pSA->digestSize); -+ -+ /* If pCmd->digestOffset is not located on the first */ -+ if(pCmd->digestOffset > (copySize - pSA->digestSize)) -+ { -+ MV_U8 digestZero[MV_CESA_MAX_DIGEST_SIZE]; -+ -+ /* Set zeros to pCmd->digestOffset (DRAM) */ -+ memset(digestZero, 0, MV_CESA_MAX_DIGEST_SIZE); -+ mvCesaCopyToMbuf(digestZero, pCmd->pSrc, pCmd->digestOffset, pSA->digestSize); -+ -+ /* Prepare dummy place for digest in SRAM */ -+ digestOffset = cesaSramVirtPtr->tempDigest - mvCesaSramAddrGet(); -+ } -+ else -+ { -+ digestOffset = pCmd->digestOffset; -+ } -+ } -+ } -+ /* Update SA in SRAM */ -+ if(cesaLastSid != sid) -+ { -+ mvCesaSramSaUpdate(sid, &pDmaDesc[i]); -+ i++; -+ } -+ -+ pReq->fragMode = MV_CESA_FRAG_MIDDLE; -+ } -+ else -+ { -+ /* Continue fragment */ -+ fixOffset = 0; -+ cryptoOffset = 0; -+ macOffset = 0; -+ if( (pCmd->pSrc->mbufSize - pReq->frags.bufOffset) <= sizeof(cesaSramVirtPtr->buf)) -+ { -+ /* Last fragment */ -+ config = pSA->config | (MV_CESA_FRAG_LAST << MV_CESA_FRAG_MODE_OFFSET); -+ pReq->fragMode = MV_CESA_FRAG_LAST; -+ copySize = pCmd->pSrc->mbufSize - pReq->frags.bufOffset; -+ -+ if( (pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ macDataSize = pCmd->macLength - pReq->frags.macSize; -+ -+ /* If pCmd->digestOffset is not located on last fragment */ -+ if(pCmd->digestOffset < pReq->frags.bufOffset) -+ { -+ /* Prepare dummy place for digest in SRAM */ -+ digestOffset = cesaSramVirtPtr->tempDigest - mvCesaSramAddrGet(); -+ } -+ else -+ { -+ digestOffset = pCmd->digestOffset - pReq->frags.bufOffset; -+ } -+ pReq->frags.newDigestOffset = digestOffset; -+ macTotalLen = pCmd->macLength; -+ -+ /* HW can't calculate the Digest correctly for fragmented packets -+ * in the following cases: -+ * - MV88F5182 || -+ * - MV88F5181L when total macLength more that 16 Kbytes || -+ * - total macLength more that 64 Kbytes -+ */ -+ if( (mvCtrlModelGet() == MV_5182_DEV_ID) || -+ ( (mvCtrlModelGet() == MV_5181_DEV_ID) && -+ (mvCtrlRevGet() >= MV_5181L_A0_REV) && -+ (pCmd->macLength >= (1 << 14)) ) ) -+ { -+ return MV_TERMINATE; -+ } -+ } -+ if( (pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ cryptoDataSize = pCmd->cryptoLength - pReq->frags.cryptoSize; -+ } -+ -+ /* cryptoIvOffset - don't care */ -+ } -+ else -+ { -+ /* WA for MV88F5182 SHA1 and MD5 fragmentation mode */ -+ if( (mvCtrlModelGet() == MV_5182_DEV_ID) && -+ (((pSA->config & MV_CESA_MAC_MODE_MASK) == -+ (MV_CESA_MAC_MD5 << MV_CESA_MAC_MODE_OFFSET)) || -+ ((pSA->config & MV_CESA_MAC_MODE_MASK) == -+ (MV_CESA_MAC_SHA1 << MV_CESA_MAC_MODE_OFFSET))) ) -+ { -+ pReq->frags.newDigestOffset = cesaSramVirtPtr->tempDigest - mvCesaSramAddrGet(); -+ pReq->fragMode = MV_CESA_FRAG_LAST; -+ -+ return MV_TERMINATE; -+ } -+ /* Middle fragment */ -+ config = pSA->config | (MV_CESA_FRAG_MIDDLE << MV_CESA_FRAG_MODE_OFFSET); -+ copySize = sizeof(cesaSramVirtPtr->buf); -+ /* digestOffset and cryptoIvOffset - don't care */ -+ -+ /* Find fragment size */ -+ mvCesaFragSizeFind(pSA, pReq, cryptoOffset, macOffset, -+ ©Size, &cryptoDataSize, &macDataSize); -+ } -+ } -+ /********* Prepare DMA descriptors to copy from pSrc to SRAM *********/ -+ pMbuf = pCmd->pSrc; -+ i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], -+ MV_FALSE, pReq->frags.bufOffset, copySize, pCmd->skipFlush); -+ -+ /* Prepare CESA descriptor to copy from DRAM to SRAM by DMA */ -+ mvCesaSramDescrBuild(config, frag, -+ cryptoOffset + fixOffset, cryptoIvOffset + fixOffset, -+ cryptoDataSize, macOffset + fixOffset, -+ digestOffset + fixOffset, macDataSize, macTotalLen, -+ pReq, &pDmaDesc[i]); -+ i++; -+ -+ /* Add special descriptor Ownership for CPU */ -+ pDmaDesc[i].byteCnt = 0; -+ pDmaDesc[i].phySrcAdd = 0; -+ pDmaDesc[i].phyDestAdd = 0; -+ i++; -+ -+ /********* Prepare DMA descriptors to copy from SRAM to pDst *********/ -+ pMbuf = pCmd->pDst; -+ i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], -+ MV_TRUE, pReq->frags.bufOffset, copySize, pCmd->skipFlush); -+ -+ /* Next field of Last DMA descriptor must be NULL */ -+ pDmaDesc[i-1].phyNextDescPtr = 0; -+ pReq->dma[frag].pDmaLast = &pDmaDesc[i-1]; -+ mvOsCacheFlush(NULL, pReq->dma[frag].pDmaFirst, -+ i*sizeof(MV_DMA_DESC)); -+ -+ /*mvCesaDebugDescriptor(&cesaSramVirtPtr->desc[frag]);*/ -+ -+ pReq->frags.bufOffset += copySize; -+ pReq->frags.cryptoSize += cryptoDataSize; -+ pReq->frags.macSize += macDataSize; -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvCesaReqProcess - Process regular (Non-fragmented) request -+* -+* DESCRIPTION: -+* This function processes the whole (not fragmented) request -+* -+* INPUT: -+* MV_CESA_REQ* pReq - Pointer to the request in the request queue. -+* -+* RETURN: -+* MV_OK - The request is successfully passed to HW for processing. -+* Other - Failure. The request will not be processed -+* -+*******************************************************************************/ -+static MV_STATUS mvCesaReqProcess(MV_CESA_REQ* pReq) -+{ -+ MV_CESA_MBUF *pMbuf; -+ MV_DMA_DESC *pDmaDesc; -+ MV_U8 *pSramBuf; -+ int sid, i, fixOffset; -+ MV_CESA_SA *pSA; -+ MV_CESA_COMMAND *pCmd = pReq->pCmd; -+ -+ cesaStats.procCount++; -+ -+ sid = pCmd->sessionId; -+ pSA = &pCesaSAD[sid]; -+ pDmaDesc = pReq->dma[0].pDmaFirst; -+ pSramBuf = cesaSramVirtPtr->buf; -+ fixOffset = pReq->fixOffset; -+ -+/* -+ mvOsPrintf("mvCesaReqProcess: sid=%d, pSA=%p, pDmaDesc=%p, pSramBuf=%p\n", -+ sid, pSA, pDmaDesc, pSramBuf); -+*/ -+ i = 0; -+ -+ /* Crypto IV Special processing in CBC mode for Encryption direction */ -+ if( ((pSA->config & MV_CESA_OPERATION_MASK) != (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) && -+ ((pSA->config & MV_CESA_CRYPTO_MODE_MASK) == (MV_CESA_CRYPTO_CBC << MV_CESA_CRYPTO_MODE_BIT)) && -+ ((pSA->config & MV_CESA_DIRECTION_MASK) == (MV_CESA_DIR_ENCODE << MV_CESA_DIRECTION_BIT)) && -+ (pCmd->ivFromUser) ) -+ { -+ /* For Crypto Encode in CBC mode HW always takes IV from SRAM IVPointer, -+ * (not from IVBufPointer). So when ivFromUser==1, we should copy IV from user place -+ * in the buffer to SRAM IVPointer -+ */ -+ i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->cryptoIV, &pDmaDesc[i], -+ MV_FALSE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); -+ } -+ -+ /* Update SA in SRAM */ -+ if(cesaLastSid != sid) -+ { -+ mvCesaSramSaUpdate(sid, &pDmaDesc[i]); -+ i++; -+ } -+ -+ /********* Prepare DMA descriptors to copy from pSrc to SRAM *********/ -+ pMbuf = pCmd->pSrc; -+ i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], -+ MV_FALSE, 0, pMbuf->mbufSize, pCmd->skipFlush); -+ -+ /* Prepare Security Accelerator descriptor to SRAM words 0 - 7 */ -+ mvCesaSramDescrBuild(pSA->config, 0, pCmd->cryptoOffset + fixOffset, -+ pCmd->ivOffset + fixOffset, pCmd->cryptoLength, -+ pCmd->macOffset + fixOffset, pCmd->digestOffset + fixOffset, -+ pCmd->macLength, pCmd->macLength, pReq, &pDmaDesc[i]); -+ i++; -+ -+ /* Add special descriptor Ownership for CPU */ -+ pDmaDesc[i].byteCnt = 0; -+ pDmaDesc[i].phySrcAdd = 0; -+ pDmaDesc[i].phyDestAdd = 0; -+ i++; -+ -+ /********* Prepare DMA descriptors to copy from SRAM to pDst *********/ -+ pMbuf = pCmd->pDst; -+ i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], -+ MV_TRUE, 0, pMbuf->mbufSize, pCmd->skipFlush); -+ -+ /* Next field of Last DMA descriptor must be NULL */ -+ pDmaDesc[i-1].phyNextDescPtr = 0; -+ pReq->dma[0].pDmaLast = &pDmaDesc[i-1]; -+ mvOsCacheFlush(NULL, pReq->dma[0].pDmaFirst, i*sizeof(MV_DMA_DESC)); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvCesaSramDescrBuild - Set CESA descriptor in SRAM -+* -+* DESCRIPTION: -+* This function builds CESA descriptor in SRAM from all Command parameters -+* -+* -+* INPUT: -+* int chan - CESA channel uses the descriptor -+* MV_U32 config - 32 bits of WORD_0 in CESA descriptor structure -+* int cryptoOffset - Offset from the beginning of SRAM buffer where -+* data for encryption/decription is started. -+* int ivOffset - Offset of crypto IV from the SRAM base. Valid only -+* for first fragment. -+* int cryptoLength - Size (in bytes) of data for encryption/descryption -+* operation on this fragment. -+* int macOffset - Offset from the beginning of SRAM buffer where -+* data for Authentication is started -+* int digestOffset - Offset from the beginning of SRAM buffer where -+* digest is located. Valid for first and last fragments. -+* int macLength - Size (in bytes) of data for Authentication -+* operation on this fragment. -+* int macTotalLen - Toatl size (in bytes) of data for Authentication -+* operation on the whole request (packet). Valid for -+* last fragment only. -+* -+* RETURN: None -+* -+*******************************************************************************/ -+static void mvCesaSramDescrBuild(MV_U32 config, int frag, -+ int cryptoOffset, int ivOffset, int cryptoLength, -+ int macOffset, int digestOffset, int macLength, -+ int macTotalLen, MV_CESA_REQ* pReq, MV_DMA_DESC* pDmaDesc) -+{ -+ MV_CESA_DESC* pCesaDesc = &pReq->pCesaDesc[frag]; -+ MV_CESA_DESC* pSramDesc = pSramDesc = &cesaSramVirtPtr->desc; -+ MV_U16 sramBufOffset = (MV_U16)((MV_U8*)cesaSramVirtPtr->buf - mvCesaSramAddrGet()); -+ -+ pCesaDesc->config = MV_32BIT_LE(config); -+ -+ if( (config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ /* word 1 */ -+ pCesaDesc->cryptoSrcOffset = MV_16BIT_LE(sramBufOffset + cryptoOffset); -+ pCesaDesc->cryptoDstOffset = MV_16BIT_LE(sramBufOffset + cryptoOffset); -+ /* word 2 */ -+ pCesaDesc->cryptoDataLen = MV_16BIT_LE(cryptoLength); -+ /* word 3 */ -+ pCesaDesc->cryptoKeyOffset = MV_16BIT_LE((MV_U16)(cesaSramVirtPtr->sramSA.cryptoKey - -+ mvCesaSramAddrGet())); -+ /* word 4 */ -+ pCesaDesc->cryptoIvOffset = MV_16BIT_LE((MV_U16)(cesaSramVirtPtr->cryptoIV - -+ mvCesaSramAddrGet())); -+ pCesaDesc->cryptoIvBufOffset = MV_16BIT_LE(sramBufOffset + ivOffset); -+ } -+ -+ if( (config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ /* word 5 */ -+ pCesaDesc->macSrcOffset = MV_16BIT_LE(sramBufOffset + macOffset); -+ pCesaDesc->macTotalLen = MV_16BIT_LE(macTotalLen); -+ -+ /* word 6 */ -+ pCesaDesc->macDigestOffset = MV_16BIT_LE(sramBufOffset + digestOffset); -+ pCesaDesc->macDataLen = MV_16BIT_LE(macLength); -+ -+ /* word 7 */ -+ pCesaDesc->macInnerIvOffset = MV_16BIT_LE((MV_U16)(cesaSramVirtPtr->sramSA.macInnerIV - -+ mvCesaSramAddrGet())); -+ pCesaDesc->macOuterIvOffset = MV_16BIT_LE((MV_U16)(cesaSramVirtPtr->sramSA.macOuterIV - -+ mvCesaSramAddrGet())); -+ } -+ /* Prepare DMA descriptor to CESA descriptor from DRAM to SRAM */ -+ pDmaDesc->phySrcAdd = MV_32BIT_LE(mvCesaVirtToPhys(&pReq->cesaDescBuf, pCesaDesc)); -+ pDmaDesc->phyDestAdd = MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (MV_U8*)pSramDesc)); -+ pDmaDesc->byteCnt = MV_32BIT_LE(sizeof(MV_CESA_DESC) | BIT31); -+ -+ /* flush Source buffer */ -+ mvOsCacheFlush(NULL, pCesaDesc, sizeof(MV_CESA_DESC)); -+} -+ -+/******************************************************************************* -+* mvCesaSramSaUpdate - Move required SA information to SRAM if needed. -+* -+* DESCRIPTION: -+* Copy to SRAM values of the required SA. -+* -+* -+* INPUT: -+* short sid - Session ID needs SRAM Cache update -+* MV_DMA_DESC *pDmaDesc - Pointer to DMA descriptor used to -+* copy SA values from DRAM to SRAM. -+* -+* RETURN: -+* MV_OK - Cache entry for this SA copied to SRAM. -+* MV_NO_CHANGE - Cache entry for this SA already exist in SRAM -+* -+*******************************************************************************/ -+static INLINE void mvCesaSramSaUpdate(short sid, MV_DMA_DESC *pDmaDesc) -+{ -+ MV_CESA_SA *pSA = &pCesaSAD[sid]; -+ -+ /* Prepare DMA descriptor to Copy CACHE_SA from SA database in DRAM to SRAM */ -+ pDmaDesc->byteCnt = MV_32BIT_LE(sizeof(MV_CESA_SRAM_SA) | BIT31); -+ pDmaDesc->phySrcAdd = MV_32BIT_LE(mvCesaVirtToPhys(&cesaSramSaBuf, pSA->pSramSA)); -+ pDmaDesc->phyDestAdd = -+ MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (MV_U8*)&cesaSramVirtPtr->sramSA)); -+ -+ /* Source buffer is already flushed during OpenSession*/ -+ /*mvOsCacheFlush(NULL, &pSA->sramSA, sizeof(MV_CESA_SRAM_SA));*/ -+} -+ -+/******************************************************************************* -+* mvCesaDmaCopyPrepare - prepare DMA descriptor list to copy data presented by -+* Mbuf structure from DRAM to SRAM -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_CESA_MBUF* pMbuf - pointer to Mbuf structure contains request -+* data in DRAM -+* MV_U8* pSramBuf - pointer to buffer in SRAM where data should -+* be copied to. -+* MV_DMA_DESC* pDmaDesc - pointer to first DMA descriptor for this copy. -+* The function set number of DMA descriptors needed -+* to copy the copySize bytes from Mbuf. -+* MV_BOOL isToMbuf - Copy direction. -+* MV_TRUE means copy from SRAM buffer to Mbuf in DRAM. -+* MV_FALSE means copy from Mbuf in DRAM to SRAM buffer. -+* int offset - Offset in the Mbuf structure that copy should be -+* started from. -+* int copySize - Size of data should be copied. -+* -+* RETURN: -+* int - number of DMA descriptors used for the copy. -+* -+*******************************************************************************/ -+#ifndef MV_NETBSD -+static INLINE int mvCesaDmaCopyPrepare(MV_CESA_MBUF* pMbuf, MV_U8* pSramBuf, -+ MV_DMA_DESC* pDmaDesc, MV_BOOL isToMbuf, -+ int offset, int copySize, MV_BOOL skipFlush) -+{ -+ int bufOffset, bufSize, size, frag, i; -+ MV_U8* pBuf; -+ -+ i = 0; -+ -+ /* Calculate start place for copy: fragment number and offset in the fragment */ -+ frag = mvCesaMbufOffset(pMbuf, offset, &bufOffset); -+ bufSize = pMbuf->pFrags[frag].bufSize - bufOffset; -+ pBuf = pMbuf->pFrags[frag].bufVirtPtr + bufOffset; -+ -+ /* Size accumulate total copy size */ -+ size = 0; -+ -+ /* Create DMA lists to copy mBuf from pSrc to SRAM */ -+ while(size < copySize) -+ { -+ /* Find copy size for each DMA descriptor */ -+ bufSize = MV_MIN(bufSize, (copySize - size)); -+ pDmaDesc[i].byteCnt = MV_32BIT_LE(bufSize | BIT31); -+ if(isToMbuf) -+ { -+ pDmaDesc[i].phyDestAdd = MV_32BIT_LE(mvOsIoVirtToPhy(NULL, pBuf)); -+ pDmaDesc[i].phySrcAdd = -+ MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (pSramBuf + size))); -+ /* invalidate the buffer */ -+ if(skipFlush == MV_FALSE) -+ mvOsCacheInvalidate(NULL, pBuf, bufSize); -+ } -+ else -+ { -+ pDmaDesc[i].phySrcAdd = MV_32BIT_LE(mvOsIoVirtToPhy(NULL, pBuf)); -+ pDmaDesc[i].phyDestAdd = -+ MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (pSramBuf + size))); -+ /* flush the buffer */ -+ if(skipFlush == MV_FALSE) -+ mvOsCacheFlush(NULL, pBuf, bufSize); -+ } -+ -+ /* Count number of used DMA descriptors */ -+ i++; -+ size += bufSize; -+ -+ /* go to next fragment in the Mbuf */ -+ frag++; -+ pBuf = pMbuf->pFrags[frag].bufVirtPtr; -+ bufSize = pMbuf->pFrags[frag].bufSize; -+ } -+ return i; -+} -+#else /* MV_NETBSD */ -+static int mvCesaDmaCopyPrepare(MV_CESA_MBUF* pMbuf, MV_U8* pSramBuf, -+ MV_DMA_DESC* pDmaDesc, MV_BOOL isToMbuf, -+ int offset, int copySize, MV_BOOL skipFlush) -+{ -+ int bufOffset, bufSize, thisSize, size, frag, i; -+ MV_ULONG bufPhys, sramPhys; -+ MV_U8* pBuf; -+ -+ /* -+ * Calculate start place for copy: fragment number and offset in -+ * the fragment -+ */ -+ frag = mvCesaMbufOffset(pMbuf, offset, &bufOffset); -+ -+ /* -+ * Get SRAM physical address only once. We can update it in-place -+ * as we build the descriptor chain. -+ */ -+ sramPhys = mvCesaSramVirtToPhys(NULL, pSramBuf); -+ -+ /* -+ * 'size' accumulates total copy size, 'i' counts desccriptors. -+ */ -+ size = i = 0; -+ -+ /* Create DMA lists to copy mBuf from pSrc to SRAM */ -+ while (size < copySize) { -+ /* -+ * Calculate # of bytes to copy from the current fragment, -+ * and the pointer to the start of data -+ */ -+ bufSize = pMbuf->pFrags[frag].bufSize - bufOffset; -+ pBuf = pMbuf->pFrags[frag].bufVirtPtr + bufOffset; -+ bufOffset = 0; /* First frag may be non-zero */ -+ frag++; -+ -+ /* -+ * As long as there is data in the current fragment... -+ */ -+ while (bufSize > 0) { -+ /* -+ * Ensure we don't cross an MMU page boundary. -+ * XXX: This is NetBSD-specific, but it is a -+ * quick and dirty way to fix the problem. -+ * A true HAL would rely on the OS-specific -+ * driver to do this... -+ */ -+ thisSize = PAGE_SIZE - -+ (((MV_ULONG)pBuf) & (PAGE_SIZE - 1)); -+ thisSize = MV_MIN(bufSize, thisSize); -+ /* -+ * Make sure we don't copy more than requested -+ */ -+ if (thisSize > (copySize - size)) { -+ thisSize = copySize - size; -+ bufSize = 0; -+ } -+ -+ /* -+ * Physicall address of this fragment -+ */ -+ bufPhys = MV_32BIT_LE(mvOsIoVirtToPhy(NULL, pBuf)); -+ -+ /* -+ * Set up the descriptor -+ */ -+ pDmaDesc[i].byteCnt = MV_32BIT_LE(thisSize | BIT31); -+ if(isToMbuf) { -+ pDmaDesc[i].phyDestAdd = bufPhys; -+ pDmaDesc[i].phySrcAdd = MV_32BIT_LE(sramPhys); -+ /* invalidate the buffer */ -+ if(skipFlush == MV_FALSE) -+ mvOsCacheInvalidate(NULL, pBuf, thisSize); -+ } else { -+ pDmaDesc[i].phySrcAdd = bufPhys; -+ pDmaDesc[i].phyDestAdd = MV_32BIT_LE(sramPhys); -+ /* flush the buffer */ -+ if(skipFlush == MV_FALSE) -+ mvOsCacheFlush(NULL, pBuf, thisSize); -+ } -+ -+ pDmaDesc[i].phyNextDescPtr = -+ MV_32BIT_LE(mvOsIoVirtToPhy(NULL,(&pDmaDesc[i+1]))); -+ -+ /* flush the DMA desc */ -+ mvOsCacheFlush(NULL, &pDmaDesc[i], sizeof(MV_DMA_DESC)); -+ -+ /* Update state */ -+ bufSize -= thisSize; -+ sramPhys += thisSize; -+ pBuf += thisSize; -+ size += thisSize; -+ i++; -+ } -+ } -+ -+ return i; -+} -+#endif /* MV_NETBSD */ -+/******************************************************************************* -+* mvCesaHmacIvGet - Calculate Inner and Outter values from HMAC key -+* -+* DESCRIPTION: -+* This function calculate Inner and Outer values used for HMAC algorithm. -+* This operation allows improve performance fro the whole HMAC processing. -+* -+* INPUT: -+* MV_CESA_MAC_MODE macMode - Authentication mode: HMAC_MD5 or HMAC_SHA1. -+* unsigned char key[] - Pointer to HMAC key. -+* int keyLength - Size of HMAC key (maximum 64 bytes) -+* -+* OUTPUT: -+* unsigned char innerIV[] - HASH(key^inner) -+* unsigned char outerIV[] - HASH(key^outter) -+* -+* RETURN: None -+* -+*******************************************************************************/ -+static void mvCesaHmacIvGet(MV_CESA_MAC_MODE macMode, unsigned char key[], int keyLength, -+ unsigned char innerIV[], unsigned char outerIV[]) -+{ -+ unsigned char inner[MV_CESA_MAX_MAC_KEY_LENGTH]; -+ unsigned char outer[MV_CESA_MAX_MAC_KEY_LENGTH]; -+ int i, digestSize = 0; -+#if defined(MV_CPU_LE) || defined(MV_PPC) -+ MV_U32 swapped32, val32, *pVal32; -+#endif -+ for(i=0; ipFrags[frag].bufVirtPtr + fragOffset; -+ size = pMbuf->pFrags[frag].bufSize - fragOffset; -+ -+ /* Complete Inner part */ -+ while(macLeftSize > 0) -+ { -+ if(macLeftSize <= size) -+ { -+ mvSHA1Update(&ctx, pData, macLeftSize); -+ break; -+ } -+ mvSHA1Update(&ctx, pData, size); -+ macLeftSize -= size; -+ frag++; -+ pData = pMbuf->pFrags[frag].bufVirtPtr; -+ size = pMbuf->pFrags[frag].bufSize; -+ } -+ mvSHA1Final(pDigest, &ctx); -+/* -+ mvOsPrintf("mvCesaFragSha1Complete: pOuterIV=%p, macLeftSize=%d, macTotalSize=%d\n", -+ pOuterIV, macLeftSize, macTotalSize); -+ mvDebugMemDump(pDigest, MV_CESA_SHA1_DIGEST_SIZE, 1); -+*/ -+ -+ if(pOuterIV != NULL) -+ { -+ /* If HMAC - Complete Outer part */ -+ for(i=0; ipFrags[frag].bufVirtPtr + fragOffset; -+ size = pMbuf->pFrags[frag].bufSize - fragOffset; -+ -+ /* Complete Inner part */ -+ while(macLeftSize > 0) -+ { -+ if(macLeftSize <= size) -+ { -+ mvMD5Update(&ctx, pData, macLeftSize); -+ break; -+ } -+ mvMD5Update(&ctx, pData, size); -+ macLeftSize -= size; -+ frag++; -+ pData = pMbuf->pFrags[frag].bufVirtPtr; -+ size = pMbuf->pFrags[frag].bufSize; -+ } -+ mvMD5Final(pDigest, &ctx); -+ -+/* -+ mvOsPrintf("mvCesaFragMd5Complete: pOuterIV=%p, macLeftSize=%d, macTotalSize=%d\n", -+ pOuterIV, macLeftSize, macTotalSize); -+ mvDebugMemDump(pDigest, MV_CESA_MD5_DIGEST_SIZE, 1); -+*/ -+ if(pOuterIV != NULL) -+ { -+ /* Complete Outer part */ -+ for(i=0; ipCmd; -+ MV_U8* pDigest; -+ MV_CESA_MAC_MODE macMode; -+ MV_U8* pOuterIV = NULL; -+ -+ /* Copy data from Source fragment to Destination */ -+ if(pCmd->pSrc != pCmd->pDst) -+ { -+ mvCesaMbufCopy(pCmd->pDst, pReq->frags.bufOffset, -+ pCmd->pSrc, pReq->frags.bufOffset, macDataSize); -+ } -+ -+/* -+ mvCesaCopyFromMbuf(cesaSramVirtPtr->buf[0], pCmd->pSrc, pReq->frags.bufOffset, macDataSize); -+ mvCesaCopyToMbuf(cesaSramVirtPtr->buf[0], pCmd->pDst, pReq->frags.bufOffset, macDataSize); -+*/ -+ pDigest = (mvCesaSramAddrGet() + pReq->frags.newDigestOffset); -+ -+ macMode = (pSA->config & MV_CESA_MAC_MODE_MASK) >> MV_CESA_MAC_MODE_OFFSET; -+/* -+ mvOsPrintf("macDataSize=%d, macLength=%d, digestOffset=%d, macMode=%d\n", -+ macDataSize, pCmd->macLength, pCmd->digestOffset, macMode); -+*/ -+ switch(macMode) -+ { -+ case MV_CESA_MAC_HMAC_MD5: -+ pOuterIV = pSA->pSramSA->macOuterIV; -+ -+ case MV_CESA_MAC_MD5: -+ mvCesaFragMd5Complete(pCmd->pDst, pReq->frags.bufOffset, pOuterIV, -+ macDataSize, pCmd->macLength, pDigest); -+ break; -+ -+ case MV_CESA_MAC_HMAC_SHA1: -+ pOuterIV = pSA->pSramSA->macOuterIV; -+ -+ case MV_CESA_MAC_SHA1: -+ mvCesaFragSha1Complete(pCmd->pDst, pReq->frags.bufOffset, pOuterIV, -+ macDataSize, pCmd->macLength, pDigest); -+ break; -+ -+ default: -+ mvOsPrintf("mvCesaFragAuthComplete: Unexpected macMode %d\n", macMode); -+ return MV_BAD_PARAM; -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaCtrModeInit - -+* -+* DESCRIPTION: -+* -+* -+* INPUT: NONE -+* -+* -+* RETURN: -+* MV_CESA_COMMAND* -+* -+*******************************************************************************/ -+static MV_CESA_COMMAND* mvCesaCtrModeInit(void) -+{ -+ MV_CESA_MBUF *pMbuf; -+ MV_U8 *pBuf; -+ MV_CESA_COMMAND *pCmd; -+ -+ pBuf = mvOsMalloc(sizeof(MV_CESA_COMMAND) + -+ sizeof(MV_CESA_MBUF) + sizeof(MV_BUF_INFO) + 100); -+ if(pBuf == NULL) -+ { -+ mvOsPrintf("mvCesaSessionOpen: Can't allocate %u bytes for CTR Mode\n", -+ sizeof(MV_CESA_COMMAND) + sizeof(MV_CESA_MBUF) + sizeof(MV_BUF_INFO) ); -+ return NULL; -+ } -+ pCmd = (MV_CESA_COMMAND*)pBuf; -+ pBuf += sizeof(MV_CESA_COMMAND); -+ -+ pMbuf = (MV_CESA_MBUF*)pBuf; -+ pBuf += sizeof(MV_CESA_MBUF); -+ -+ pMbuf->pFrags = (MV_BUF_INFO*)pBuf; -+ -+ pMbuf->numFrags = 1; -+ pCmd->pSrc = pMbuf; -+ pCmd->pDst = pMbuf; -+/* -+ mvOsPrintf("CtrModeInit: pCmd=%p, pSrc=%p, pDst=%p, pFrags=%p\n", -+ pCmd, pCmd->pSrc, pCmd->pDst, -+ pMbuf->pFrags); -+*/ -+ return pCmd; -+} -+ -+/******************************************************************************* -+* mvCesaCtrModePrepare - -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_CESA_COMMAND *pCtrModeCmd, MV_CESA_COMMAND *pCmd -+* -+* RETURN: -+* MV_STATUS -+* -+*******************************************************************************/ -+static MV_STATUS mvCesaCtrModePrepare(MV_CESA_COMMAND *pCtrModeCmd, MV_CESA_COMMAND *pCmd) -+{ -+ MV_CESA_MBUF *pMbuf; -+ MV_U8 *pBuf, *pIV; -+ MV_U32 counter, *pCounter; -+ int cryptoSize = MV_ALIGN_UP(pCmd->cryptoLength, MV_CESA_AES_BLOCK_SIZE); -+/* -+ mvOsPrintf("CtrModePrepare: pCmd=%p, pCtrSrc=%p, pCtrDst=%p, pOrgCmd=%p, pOrgSrc=%p, pOrgDst=%p\n", -+ pCmd, pCmd->pSrc, pCmd->pDst, -+ pCtrModeCmd, pCtrModeCmd->pSrc, pCtrModeCmd->pDst); -+*/ -+ pMbuf = pCtrModeCmd->pSrc; -+ -+ /* Allocate buffer for Key stream */ -+ pBuf = mvOsIoCachedMalloc(cesaOsHandle,cryptoSize, -+ &pMbuf->pFrags[0].bufPhysAddr, -+ &pMbuf->pFrags[0].memHandle); -+ if(pBuf == NULL) -+ { -+ mvOsPrintf("mvCesaCtrModePrepare: Can't allocate %d bytes\n", cryptoSize); -+ return MV_OUT_OF_CPU_MEM; -+ } -+ memset(pBuf, 0, cryptoSize); -+ mvOsCacheFlush(NULL, pBuf, cryptoSize); -+ -+ pMbuf->pFrags[0].bufVirtPtr = pBuf; -+ pMbuf->mbufSize = cryptoSize; -+ pMbuf->pFrags[0].bufSize = cryptoSize; -+ -+ pCtrModeCmd->pReqPrv = pCmd->pReqPrv; -+ pCtrModeCmd->sessionId = pCmd->sessionId; -+ -+ /* ivFromUser and ivOffset are don't care */ -+ pCtrModeCmd->cryptoOffset = 0; -+ pCtrModeCmd->cryptoLength = cryptoSize; -+ -+ /* digestOffset, macOffset and macLength are don't care */ -+ -+ mvCesaCopyFromMbuf(pBuf, pCmd->pSrc, pCmd->ivOffset, MV_CESA_AES_BLOCK_SIZE); -+ pCounter = (MV_U32*)(pBuf + (MV_CESA_AES_BLOCK_SIZE - sizeof(counter))); -+ counter = *pCounter; -+ counter = MV_32BIT_BE(counter); -+ pIV = pBuf; -+ cryptoSize -= MV_CESA_AES_BLOCK_SIZE; -+ -+ /* fill key stream */ -+ while(cryptoSize > 0) -+ { -+ pBuf += MV_CESA_AES_BLOCK_SIZE; -+ memcpy(pBuf, pIV, MV_CESA_AES_BLOCK_SIZE - sizeof(counter)); -+ pCounter = (MV_U32*)(pBuf + (MV_CESA_AES_BLOCK_SIZE - sizeof(counter))); -+ counter++; -+ *pCounter = MV_32BIT_BE(counter); -+ cryptoSize -= MV_CESA_AES_BLOCK_SIZE; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaCtrModeComplete - -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_CESA_COMMAND *pOrgCmd, MV_CESA_COMMAND *pCmd -+* -+* RETURN: -+* MV_STATUS -+* -+*******************************************************************************/ -+static MV_STATUS mvCesaCtrModeComplete(MV_CESA_COMMAND *pOrgCmd, MV_CESA_COMMAND *pCmd) -+{ -+ int srcFrag, dstFrag, srcOffset, dstOffset, keyOffset, srcSize, dstSize; -+ int cryptoSize = pCmd->cryptoLength; -+ MV_U8 *pSrc, *pDst, *pKey; -+ MV_STATUS status = MV_OK; -+/* -+ mvOsPrintf("CtrModeComplete: pCmd=%p, pCtrSrc=%p, pCtrDst=%p, pOrgCmd=%p, pOrgSrc=%p, pOrgDst=%p\n", -+ pCmd, pCmd->pSrc, pCmd->pDst, -+ pOrgCmd, pOrgCmd->pSrc, pOrgCmd->pDst); -+*/ -+ /* XOR source data with key stream to destination data */ -+ pKey = pCmd->pDst->pFrags[0].bufVirtPtr; -+ keyOffset = 0; -+ -+ if( (pOrgCmd->pSrc != pOrgCmd->pDst) && -+ (pOrgCmd->cryptoOffset > 0) ) -+ { -+ /* Copy Prefix from source buffer to destination buffer */ -+ -+ status = mvCesaMbufCopy(pOrgCmd->pDst, 0, -+ pOrgCmd->pSrc, 0, pOrgCmd->cryptoOffset); -+/* -+ status = mvCesaCopyFromMbuf(tempBuf, pOrgCmd->pSrc, -+ 0, pOrgCmd->cryptoOffset); -+ status = mvCesaCopyToMbuf(tempBuf, pOrgCmd->pDst, -+ 0, pOrgCmd->cryptoOffset); -+*/ -+ } -+ -+ srcFrag = mvCesaMbufOffset(pOrgCmd->pSrc, pOrgCmd->cryptoOffset, &srcOffset); -+ pSrc = pOrgCmd->pSrc->pFrags[srcFrag].bufVirtPtr; -+ srcSize = pOrgCmd->pSrc->pFrags[srcFrag].bufSize; -+ -+ dstFrag = mvCesaMbufOffset(pOrgCmd->pDst, pOrgCmd->cryptoOffset, &dstOffset); -+ pDst = pOrgCmd->pDst->pFrags[dstFrag].bufVirtPtr; -+ dstSize = pOrgCmd->pDst->pFrags[dstFrag].bufSize; -+ -+ while(cryptoSize > 0) -+ { -+ pDst[dstOffset] = (pSrc[srcOffset] ^ pKey[keyOffset]); -+ -+ cryptoSize--; -+ dstOffset++; -+ srcOffset++; -+ keyOffset++; -+ -+ if(srcOffset >= srcSize) -+ { -+ srcFrag++; -+ srcOffset = 0; -+ pSrc = pOrgCmd->pSrc->pFrags[srcFrag].bufVirtPtr; -+ srcSize = pOrgCmd->pSrc->pFrags[srcFrag].bufSize; -+ } -+ -+ if(dstOffset >= dstSize) -+ { -+ dstFrag++; -+ dstOffset = 0; -+ pDst = pOrgCmd->pDst->pFrags[dstFrag].bufVirtPtr; -+ dstSize = pOrgCmd->pDst->pFrags[dstFrag].bufSize; -+ } -+ } -+ -+ if(pOrgCmd->pSrc != pOrgCmd->pDst) -+ { -+ /* Copy Suffix from source buffer to destination buffer */ -+ srcOffset = pOrgCmd->cryptoOffset + pOrgCmd->cryptoLength; -+ -+ if( (pOrgCmd->pDst->mbufSize - srcOffset) > 0) -+ { -+ status = mvCesaMbufCopy(pOrgCmd->pDst, srcOffset, -+ pOrgCmd->pSrc, srcOffset, -+ pOrgCmd->pDst->mbufSize - srcOffset); -+ } -+ -+/* -+ status = mvCesaCopyFromMbuf(tempBuf, pOrgCmd->pSrc, -+ srcOffset, pOrgCmd->pSrc->mbufSize - srcOffset); -+ status = mvCesaCopyToMbuf(tempBuf, pOrgCmd->pDst, -+ srcOffset, pOrgCmd->pDst->mbufSize - srcOffset); -+*/ -+ } -+ -+ /* Free buffer used for Key stream */ -+ mvOsIoCachedFree(cesaOsHandle,pCmd->pDst->pFrags[0].bufSize, -+ pCmd->pDst->pFrags[0].bufPhysAddr, -+ pCmd->pDst->pFrags[0].bufVirtPtr, -+ pCmd->pDst->pFrags[0].memHandle); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaCtrModeFinish - -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_CESA_COMMAND* pCmd -+* -+* RETURN: -+* MV_STATUS -+* -+*******************************************************************************/ -+static void mvCesaCtrModeFinish(MV_CESA_COMMAND* pCmd) -+{ -+ mvOsFree(pCmd); -+} -+ -+/******************************************************************************* -+* mvCesaParamCheck - -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, MV_U8* pFixOffset -+* -+* RETURN: -+* MV_STATUS -+* -+*******************************************************************************/ -+static MV_STATUS mvCesaParamCheck(MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, -+ MV_U8* pFixOffset) -+{ -+ MV_U8 fixOffset = 0xFF; -+ -+ /* Check AUTH operation parameters */ -+ if( ((pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET)) ) -+ { -+ /* MAC offset should be at least 4 byte aligned */ -+ if( MV_IS_NOT_ALIGN(pCmd->macOffset, 4) ) -+ { -+ mvOsPrintf("mvCesaAction: macOffset %d must be 4 byte aligned\n", -+ pCmd->macOffset); -+ return MV_BAD_PARAM; -+ } -+ /* Digest offset must be 4 byte aligned */ -+ if( MV_IS_NOT_ALIGN(pCmd->digestOffset, 4) ) -+ { -+ mvOsPrintf("mvCesaAction: digestOffset %d must be 4 byte aligned\n", -+ pCmd->digestOffset); -+ return MV_BAD_PARAM; -+ } -+ /* In addition all offsets should be the same alignment: 8 or 4 */ -+ if(fixOffset == 0xFF) -+ { -+ fixOffset = (pCmd->macOffset % 8); -+ } -+ else -+ { -+ if( (pCmd->macOffset % 8) != fixOffset) -+ { -+ mvOsPrintf("mvCesaAction: macOffset %d mod 8 must be equal %d\n", -+ pCmd->macOffset, fixOffset); -+ return MV_BAD_PARAM; -+ } -+ } -+ if( (pCmd->digestOffset % 8) != fixOffset) -+ { -+ mvOsPrintf("mvCesaAction: digestOffset %d mod 8 must be equal %d\n", -+ pCmd->digestOffset, fixOffset); -+ return MV_BAD_PARAM; -+ } -+ } -+ /* Check CRYPTO operation parameters */ -+ if( ((pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) ) -+ { -+ /* CryptoOffset should be at least 4 byte aligned */ -+ if( MV_IS_NOT_ALIGN(pCmd->cryptoOffset, 4) ) -+ { -+ mvOsPrintf("CesaAction: cryptoOffset=%d must be 4 byte aligned\n", -+ pCmd->cryptoOffset); -+ return MV_BAD_PARAM; -+ } -+ /* cryptoLength should be the whole number of blocks */ -+ if( MV_IS_NOT_ALIGN(pCmd->cryptoLength, pSA->cryptoBlockSize) ) -+ { -+ mvOsPrintf("mvCesaAction: cryptoLength=%d must be %d byte aligned\n", -+ pCmd->cryptoLength, pSA->cryptoBlockSize); -+ return MV_BAD_PARAM; -+ } -+ if(fixOffset == 0xFF) -+ { -+ fixOffset = (pCmd->cryptoOffset % 8); -+ } -+ else -+ { -+ /* In addition all offsets should be the same alignment: 8 or 4 */ -+ if( (pCmd->cryptoOffset % 8) != fixOffset) -+ { -+ mvOsPrintf("mvCesaAction: cryptoOffset %d mod 8 must be equal %d \n", -+ pCmd->cryptoOffset, fixOffset); -+ return MV_BAD_PARAM; -+ } -+ } -+ -+ /* check for CBC mode */ -+ if(pSA->cryptoIvSize > 0) -+ { -+ /* cryptoIV must not be part of CryptoLength */ -+ if( ((pCmd->ivOffset + pSA->cryptoIvSize) > pCmd->cryptoOffset) && -+ (pCmd->ivOffset < (pCmd->cryptoOffset + pCmd->cryptoLength)) ) -+ { -+ mvOsPrintf("mvCesaFragParamCheck: cryptoIvOffset (%d) is part of cryptoLength (%d+%d)\n", -+ pCmd->ivOffset, pCmd->macOffset, pCmd->macLength); -+ return MV_BAD_PARAM; -+ } -+ -+ /* ivOffset must be 4 byte aligned */ -+ if( MV_IS_NOT_ALIGN(pCmd->ivOffset, 4) ) -+ { -+ mvOsPrintf("CesaAction: ivOffset=%d must be 4 byte aligned\n", -+ pCmd->ivOffset); -+ return MV_BAD_PARAM; -+ } -+ /* In addition all offsets should be the same alignment: 8 or 4 */ -+ if( (pCmd->ivOffset % 8) != fixOffset) -+ { -+ mvOsPrintf("mvCesaAction: ivOffset %d mod 8 must be %d\n", -+ pCmd->ivOffset, fixOffset); -+ return MV_BAD_PARAM; -+ } -+ } -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaFragParamCheck - -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd -+* -+* RETURN: -+* MV_STATUS -+* -+*******************************************************************************/ -+static MV_STATUS mvCesaFragParamCheck(MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd) -+{ -+ int offset; -+ -+ if( ((pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET)) ) -+ { -+ /* macOffset must be less that SRAM buffer size */ -+ if(pCmd->macOffset > (sizeof(cesaSramVirtPtr->buf) - MV_CESA_AUTH_BLOCK_SIZE)) -+ { -+ mvOsPrintf("mvCesaFragParamCheck: macOffset is too large (%d)\n", -+ pCmd->macOffset); -+ return MV_BAD_PARAM; -+ } -+ /* macOffset+macSize must be more than mbufSize - SRAM buffer size */ -+ if( ((pCmd->macOffset + pCmd->macLength) > pCmd->pSrc->mbufSize) || -+ ((pCmd->pSrc->mbufSize - (pCmd->macOffset + pCmd->macLength)) >= -+ sizeof(cesaSramVirtPtr->buf)) ) -+ { -+ mvOsPrintf("mvCesaFragParamCheck: macLength is too large (%d), mbufSize=%d\n", -+ pCmd->macLength, pCmd->pSrc->mbufSize); -+ return MV_BAD_PARAM; -+ } -+ } -+ -+ if( ((pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) ) -+ { -+ /* cryptoOffset must be less that SRAM buffer size */ -+ /* 4 for possible fixOffset */ -+ if( (pCmd->cryptoOffset + 4) > (sizeof(cesaSramVirtPtr->buf) - pSA->cryptoBlockSize)) -+ { -+ mvOsPrintf("mvCesaFragParamCheck: cryptoOffset is too large (%d)\n", -+ pCmd->cryptoOffset); -+ return MV_BAD_PARAM; -+ } -+ -+ /* cryptoOffset+cryptoSize must be more than mbufSize - SRAM buffer size */ -+ if( ((pCmd->cryptoOffset + pCmd->cryptoLength) > pCmd->pSrc->mbufSize) || -+ ((pCmd->pSrc->mbufSize - (pCmd->cryptoOffset + pCmd->cryptoLength)) >= -+ (sizeof(cesaSramVirtPtr->buf) - pSA->cryptoBlockSize)) ) -+ { -+ mvOsPrintf("mvCesaFragParamCheck: cryptoLength is too large (%d), mbufSize=%d\n", -+ pCmd->cryptoLength, pCmd->pSrc->mbufSize); -+ return MV_BAD_PARAM; -+ } -+ } -+ -+ /* When MAC_THEN_CRYPTO or CRYPTO_THEN_MAC */ -+ if( ((pSA->config & MV_CESA_OPERATION_MASK) == -+ (MV_CESA_MAC_THEN_CRYPTO << MV_CESA_OPERATION_OFFSET)) || -+ ((pSA->config & MV_CESA_OPERATION_MASK) == -+ (MV_CESA_CRYPTO_THEN_MAC << MV_CESA_OPERATION_OFFSET)) ) -+ { -+ if( (mvCtrlModelGet() == MV_5182_DEV_ID) || -+ ( (mvCtrlModelGet() == MV_5181_DEV_ID) && -+ (mvCtrlRevGet() >= MV_5181L_A0_REV) && -+ (pCmd->macLength >= (1 << 14)) ) ) -+ { -+ return MV_NOT_ALLOWED; -+ } -+ -+ /* abs(cryptoOffset-macOffset) must be aligned cryptoBlockSize */ -+ if(pCmd->cryptoOffset > pCmd->macOffset) -+ { -+ offset = pCmd->cryptoOffset - pCmd->macOffset; -+ } -+ else -+ { -+ offset = pCmd->macOffset - pCmd->cryptoOffset; -+ } -+ -+ if( MV_IS_NOT_ALIGN(offset, pSA->cryptoBlockSize) ) -+ { -+/* -+ mvOsPrintf("mvCesaFragParamCheck: (cryptoOffset - macOffset) must be %d byte aligned\n", -+ pSA->cryptoBlockSize); -+*/ -+ return MV_NOT_ALLOWED; -+ } -+ /* Digest must not be part of CryptoLength */ -+ if( ((pCmd->digestOffset + pSA->digestSize) > pCmd->cryptoOffset) && -+ (pCmd->digestOffset < (pCmd->cryptoOffset + pCmd->cryptoLength)) ) -+ { -+/* -+ mvOsPrintf("mvCesaFragParamCheck: digestOffset (%d) is part of cryptoLength (%d+%d)\n", -+ pCmd->digestOffset, pCmd->cryptoOffset, pCmd->cryptoLength); -+*/ -+ return MV_NOT_ALLOWED; -+ } -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaFragSizeFind - -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, -+* int cryptoOffset, int macOffset, -+* -+* OUTPUT: -+* int* pCopySize, int* pCryptoDataSize, int* pMacDataSize -+* -+* RETURN: -+* MV_STATUS -+* -+*******************************************************************************/ -+static void mvCesaFragSizeFind(MV_CESA_SA* pSA, MV_CESA_REQ* pReq, -+ int cryptoOffset, int macOffset, -+ int* pCopySize, int* pCryptoDataSize, int* pMacDataSize) -+{ -+ MV_CESA_COMMAND *pCmd = pReq->pCmd; -+ int cryptoDataSize, macDataSize, copySize; -+ -+ cryptoDataSize = macDataSize = 0; -+ copySize = *pCopySize; -+ -+ if( (pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ cryptoDataSize = MV_MIN( (copySize - cryptoOffset), -+ (pCmd->cryptoLength - (pReq->frags.cryptoSize + 1)) ); -+ -+ /* cryptoSize for each fragment must be the whole number of blocksSize */ -+ if( MV_IS_NOT_ALIGN(cryptoDataSize, pSA->cryptoBlockSize) ) -+ { -+ cryptoDataSize = MV_ALIGN_DOWN(cryptoDataSize, pSA->cryptoBlockSize); -+ copySize = cryptoOffset + cryptoDataSize; -+ } -+ } -+ if( (pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ macDataSize = MV_MIN( (copySize - macOffset), -+ (pCmd->macLength - (pReq->frags.macSize + 1))); -+ -+ /* macSize for each fragment (except last) must be the whole number of blocksSize */ -+ if( MV_IS_NOT_ALIGN(macDataSize, MV_CESA_AUTH_BLOCK_SIZE) ) -+ { -+ macDataSize = MV_ALIGN_DOWN(macDataSize, MV_CESA_AUTH_BLOCK_SIZE); -+ copySize = macOffset + macDataSize; -+ } -+ cryptoDataSize = copySize - cryptoOffset; -+ } -+ *pCopySize = copySize; -+ -+ if(pCryptoDataSize != NULL) -+ *pCryptoDataSize = cryptoDataSize; -+ -+ if(pMacDataSize != NULL) -+ *pMacDataSize = macDataSize; -+} -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/cesa/mvCesa.h linux-2.6.39/crypto/ocf/kirkwood/cesa/mvCesa.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/cesa/mvCesa.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/cesa/mvCesa.h 2011-08-01 14:38:18.000000000 +0200 -@@ -0,0 +1,412 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+/******************************************************************************* -+* mvCesa.h - Header File for Cryptographic Engines and Security Accelerator -+* -+* DESCRIPTION: -+* This header file contains macros typedefs and function declaration for -+* the Marvell Cryptographic Engines and Security Accelerator. -+* -+*******************************************************************************/ -+ -+#ifndef __mvCesa_h__ -+#define __mvCesa_h__ -+ -+#include "mvOs.h" -+#include "mvCommon.h" -+#include "mvDebug.h" -+ -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+ -+#include "cesa/mvMD5.h" -+#include "cesa/mvSHA1.h" -+ -+#include "cesa/mvCesa.h" -+#include "cesa/AES/mvAes.h" -+#include "mvSysHwConfig.h" -+ -+#ifdef MV_INCLUDE_IDMA -+#include "idma/mvIdma.h" -+#include "idma/mvIdmaRegs.h" -+#else -+/* Redefine MV_DMA_DESC structure */ -+typedef struct _mvDmaDesc -+{ -+ MV_U32 byteCnt; /* The total number of bytes to transfer */ -+ MV_U32 phySrcAdd; /* The physical source address */ -+ MV_U32 phyDestAdd; /* The physical destination address */ -+ MV_U32 phyNextDescPtr; /* If we are using chain mode DMA transfer, */ -+ /* then this pointer should point to the */ -+ /* physical address of the next descriptor, */ -+ /* otherwise it should be NULL. */ -+}MV_DMA_DESC; -+#endif /* MV_INCLUDE_IDMA */ -+ -+#include "cesa/mvCesaRegs.h" -+ -+#define MV_CESA_AUTH_BLOCK_SIZE 64 /* bytes */ -+ -+#define MV_CESA_MD5_DIGEST_SIZE 16 /* bytes */ -+#define MV_CESA_SHA1_DIGEST_SIZE 20 /* bytes */ -+ -+#define MV_CESA_MAX_DIGEST_SIZE MV_CESA_SHA1_DIGEST_SIZE -+ -+#define MV_CESA_DES_KEY_LENGTH 8 /* bytes = 64 bits */ -+#define MV_CESA_3DES_KEY_LENGTH 24 /* bytes = 192 bits */ -+#define MV_CESA_AES_128_KEY_LENGTH 16 /* bytes = 128 bits */ -+#define MV_CESA_AES_192_KEY_LENGTH 24 /* bytes = 192 bits */ -+#define MV_CESA_AES_256_KEY_LENGTH 32 /* bytes = 256 bits */ -+ -+#define MV_CESA_MAX_CRYPTO_KEY_LENGTH MV_CESA_AES_256_KEY_LENGTH -+ -+#define MV_CESA_DES_BLOCK_SIZE 8 /* bytes = 64 bits */ -+#define MV_CESA_3DES_BLOCK_SIZE 8 /* bytes = 64 bits */ -+ -+#define MV_CESA_AES_BLOCK_SIZE 16 /* bytes = 128 bits */ -+ -+#define MV_CESA_MAX_IV_LENGTH MV_CESA_AES_BLOCK_SIZE -+ -+#define MV_CESA_MAX_MAC_KEY_LENGTH 64 /* bytes */ -+ -+typedef struct -+{ -+ MV_U8 cryptoKey[MV_CESA_MAX_CRYPTO_KEY_LENGTH]; -+ MV_U8 macKey[MV_CESA_MAX_MAC_KEY_LENGTH]; -+ MV_CESA_OPERATION operation; -+ MV_CESA_DIRECTION direction; -+ MV_CESA_CRYPTO_ALG cryptoAlgorithm; -+ MV_CESA_CRYPTO_MODE cryptoMode; -+ MV_U8 cryptoKeyLength; -+ MV_CESA_MAC_MODE macMode; -+ MV_U8 macKeyLength; -+ MV_U8 digestSize; -+ -+} MV_CESA_OPEN_SESSION; -+ -+typedef struct -+{ -+ MV_BUF_INFO *pFrags; -+ MV_U16 numFrags; -+ MV_U16 mbufSize; -+ -+} MV_CESA_MBUF; -+ -+typedef struct -+{ -+ void* pReqPrv; /* instead of reqId */ -+ MV_U32 retCode; -+ MV_16 sessionId; -+ -+} MV_CESA_RESULT; -+ -+typedef void (*MV_CESA_CALLBACK) (MV_CESA_RESULT* pResult); -+ -+ -+typedef struct -+{ -+ void* pReqPrv; /* instead of reqId */ -+ MV_CESA_MBUF* pSrc; -+ MV_CESA_MBUF* pDst; -+ MV_CESA_CALLBACK* pFuncCB; -+ MV_16 sessionId; -+ MV_U16 ivFromUser; -+ MV_U16 ivOffset; -+ MV_U16 cryptoOffset; -+ MV_U16 cryptoLength; -+ MV_U16 digestOffset; -+ MV_U16 macOffset; -+ MV_U16 macLength; -+ MV_BOOL skipFlush; -+} MV_CESA_COMMAND; -+ -+ -+ -+MV_STATUS mvCesaHalInit (int numOfSession, int queueDepth, char* pSramBase, MV_U32 cryptEngBase, void *osHandle); -+MV_STATUS mvCesaFinish (void); -+MV_STATUS mvCesaSessionOpen(MV_CESA_OPEN_SESSION *pSession, short* pSid); -+MV_STATUS mvCesaSessionClose(short sid); -+MV_STATUS mvCesaCryptoIvSet(MV_U8* pIV, int ivSize); -+ -+MV_STATUS mvCesaAction (MV_CESA_COMMAND* pCmd); -+ -+MV_U32 mvCesaInProcessGet(void); -+MV_STATUS mvCesaReadyDispatch(void); -+MV_STATUS mvCesaReadyGet(MV_CESA_RESULT* pResult); -+MV_BOOL mvCesaIsReady(void); -+ -+int mvCesaMbufOffset(MV_CESA_MBUF* pMbuf, int offset, int* pBufOffset); -+MV_STATUS mvCesaCopyFromMbuf(MV_U8* pDst, MV_CESA_MBUF* pSrcMbuf, -+ int offset, int size); -+MV_STATUS mvCesaCopyToMbuf(MV_U8* pSrc, MV_CESA_MBUF* pDstMbuf, -+ int offset, int size); -+MV_STATUS mvCesaMbufCopy(MV_CESA_MBUF* pMbufDst, int dstMbufOffset, -+ MV_CESA_MBUF* pMbufSrc, int srcMbufOffset, int size); -+ -+/********** Debug functions ********/ -+ -+void mvCesaDebugMbuf(const char* str, MV_CESA_MBUF *pMbuf, int offset, int size); -+void mvCesaDebugSA(short sid, int mode); -+void mvCesaDebugStats(void); -+void mvCesaDebugStatsClear(void); -+void mvCesaDebugRegs(void); -+void mvCesaDebugStatus(void); -+void mvCesaDebugQueue(int mode); -+void mvCesaDebugSram(int mode); -+void mvCesaDebugSAD(int mode); -+ -+ -+/******** CESA Private definitions ********/ -+#if (MV_CESA_VERSION >= 2) -+#if (MV_CACHE_COHERENCY == MV_CACHE_COHER_SW) -+#define MV_CESA_TDMA_CTRL_VALUE MV_CESA_TDMA_DST_BURST_MASK(MV_CESA_TDMA_BURST_128B) \ -+ | MV_CESA_TDMA_SRC_BURST_MASK(MV_CESA_TDMA_BURST_128B) \ -+ | MV_CESA_TDMA_OUTSTAND_READ_EN_MASK \ -+ | MV_CESA_TDMA_NO_BYTE_SWAP_MASK \ -+ | MV_CESA_TDMA_ENABLE_MASK -+#else -+#define MV_CESA_TDMA_CTRL_VALUE MV_CESA_TDMA_DST_BURST_MASK(MV_CESA_TDMA_BURST_32B) \ -+ | MV_CESA_TDMA_SRC_BURST_MASK(MV_CESA_TDMA_BURST_128B) \ -+ /*| MV_CESA_TDMA_OUTSTAND_READ_EN_MASK */\ -+ | MV_CESA_TDMA_ENABLE_MASK -+ -+#endif -+#else -+#define MV_CESA_IDMA_CTRL_LOW_VALUE ICCLR_DST_BURST_LIM_128BYTE \ -+ | ICCLR_SRC_BURST_LIM_128BYTE \ -+ | ICCLR_INT_MODE_MASK \ -+ | ICCLR_BLOCK_MODE \ -+ | ICCLR_CHAN_ENABLE \ -+ | ICCLR_DESC_MODE_16M -+#endif /* MV_CESA_VERSION >= 2 */ -+ -+#define MV_CESA_MAX_PKT_SIZE (64 * 1024) -+#define MV_CESA_MAX_MBUF_FRAGS 20 -+ -+#define MV_CESA_MAX_REQ_FRAGS ( (MV_CESA_MAX_PKT_SIZE / MV_CESA_MAX_BUF_SIZE) + 1) -+ -+#define MV_CESA_MAX_DMA_DESC (MV_CESA_MAX_MBUF_FRAGS*2 + 5) -+ -+#define MAX_CESA_CHAIN_LENGTH 20 -+ -+typedef enum -+{ -+ MV_CESA_IDLE = 0, -+ MV_CESA_PENDING, -+ MV_CESA_PROCESS, -+ MV_CESA_READY, -+#if (MV_CESA_VERSION >= 3) -+ MV_CESA_CHAIN, -+#endif -+} MV_CESA_STATE; -+ -+ -+/* Session database */ -+ -+/* Map of Key materials of the session in SRAM. -+ * Each field must be 8 byte aligned -+ * Total size: 32 + 24 + 24 = 80 bytes -+ */ -+typedef struct -+{ -+ MV_U8 cryptoKey[MV_CESA_MAX_CRYPTO_KEY_LENGTH]; -+ MV_U8 macInnerIV[MV_CESA_MAX_DIGEST_SIZE]; -+ MV_U8 reservedInner[4]; -+ MV_U8 macOuterIV[MV_CESA_MAX_DIGEST_SIZE]; -+ MV_U8 reservedOuter[4]; -+ -+} MV_CESA_SRAM_SA; -+ -+typedef struct -+{ -+ MV_CESA_SRAM_SA* pSramSA; -+ MV_U32 config; -+ MV_U8 cryptoKeyLength; -+ MV_U8 cryptoIvSize; -+ MV_U8 cryptoBlockSize; -+ MV_U8 digestSize; -+ MV_U8 macKeyLength; -+ MV_U8 valid; -+ MV_U8 ctrMode; -+ MV_U32 count; -+ -+} MV_CESA_SA; -+ -+/* DMA list management */ -+typedef struct -+{ -+ MV_DMA_DESC* pDmaFirst; -+ MV_DMA_DESC* pDmaLast; -+ -+} MV_CESA_DMA; -+ -+ -+typedef struct -+{ -+ MV_U8 numFrag; -+ MV_U8 nextFrag; -+ int bufOffset; -+ int cryptoSize; -+ int macSize; -+ int newDigestOffset; -+ MV_U8 orgDigest[MV_CESA_MAX_DIGEST_SIZE]; -+ -+} MV_CESA_FRAGS; -+ -+/* Request queue */ -+typedef struct -+{ -+ MV_U8 state; -+ MV_U8 fragMode; -+ MV_U8 fixOffset; -+ MV_CESA_COMMAND* pCmd; -+ MV_CESA_COMMAND* pOrgCmd; -+ MV_BUF_INFO dmaDescBuf; -+ MV_CESA_DMA dma[MV_CESA_MAX_REQ_FRAGS]; -+ MV_BUF_INFO cesaDescBuf; -+ MV_CESA_DESC* pCesaDesc; -+ MV_CESA_FRAGS frags; -+ -+ -+} MV_CESA_REQ; -+ -+ -+/* SRAM map */ -+/* Total SRAM size calculation */ -+/* SRAM size = -+ * MV_CESA_MAX_BUF_SIZE + -+ * sizeof(MV_CESA_DESC) + -+ * MV_CESA_MAX_IV_LENGTH + -+ * MV_CESA_MAX_IV_LENGTH + -+ * MV_CESA_MAX_DIGEST_SIZE + -+ * sizeof(MV_CESA_SRAM_SA) -+ * = 1600 + 32 + 16 + 16 + 24 + 80 + 280 (reserved) = 2048 bytes -+ * = 3200 + 32 + 16 + 16 + 24 + 80 + 728 (reserved) = 4096 bytes -+ */ -+typedef struct -+{ -+ MV_U8 buf[MV_CESA_MAX_BUF_SIZE]; -+ MV_CESA_DESC desc; -+ MV_U8 cryptoIV[MV_CESA_MAX_IV_LENGTH]; -+ MV_U8 tempCryptoIV[MV_CESA_MAX_IV_LENGTH]; -+ MV_U8 tempDigest[MV_CESA_MAX_DIGEST_SIZE+4]; -+ MV_CESA_SRAM_SA sramSA; -+ -+} MV_CESA_SRAM_MAP; -+ -+ -+typedef struct -+{ -+ MV_U32 openedCount; -+ MV_U32 closedCount; -+ MV_U32 fragCount; -+ MV_U32 reqCount; -+ MV_U32 maxReqCount; -+ MV_U32 procCount; -+ MV_U32 readyCount; -+ MV_U32 notReadyCount; -+ MV_U32 startCount; -+#if (MV_CESA_VERSION >= 3) -+ MV_U32 maxChainUsage; -+#endif -+ -+} MV_CESA_STATS; -+ -+ -+/* External variables */ -+ -+extern MV_CESA_STATS cesaStats; -+extern MV_CESA_FRAGS cesaFrags; -+ -+extern MV_BUF_INFO cesaSramSaBuf; -+ -+extern MV_CESA_SA* pCesaSAD; -+extern MV_U16 cesaMaxSA; -+ -+extern MV_CESA_REQ* pCesaReqFirst; -+extern MV_CESA_REQ* pCesaReqLast; -+extern MV_CESA_REQ* pCesaReqEmpty; -+extern MV_CESA_REQ* pCesaReqProcess; -+extern int cesaQueueDepth; -+extern int cesaReqResources; -+#if (MV_CESA_VERSION>= 3) -+extern MV_U32 cesaChainLength; -+#endif -+ -+extern MV_CESA_SRAM_MAP* cesaSramVirtPtr; -+extern MV_U32 cesaSramPhysAddr; -+ -+static INLINE MV_ULONG mvCesaVirtToPhys(MV_BUF_INFO* pBufInfo, void* pVirt) -+{ -+ return (pBufInfo->bufPhysAddr + ((MV_U8*)pVirt - pBufInfo->bufVirtPtr)); -+} -+ -+/* Additional DEBUG functions */ -+void mvCesaDebugSramSA(MV_CESA_SRAM_SA* pSramSA, int mode); -+void mvCesaDebugCmd(MV_CESA_COMMAND* pCmd, int mode); -+void mvCesaDebugDescriptor(MV_CESA_DESC* pDesc); -+ -+ -+ -+#endif /* __mvCesa_h__ */ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/cesa/mvCesaDebug.c linux-2.6.39/crypto/ocf/kirkwood/cesa/mvCesaDebug.c ---- linux-2.6.39.orig/crypto/ocf/kirkwood/cesa/mvCesaDebug.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/cesa/mvCesaDebug.c 2011-08-01 14:38:18.000000000 +0200 -@@ -0,0 +1,484 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "mvOs.h" -+#include "mvDebug.h" -+ -+#include "cesa/mvMD5.h" -+#include "cesa/mvSHA1.h" -+ -+#include "cesa/mvCesa.h" -+#include "cesa/mvCesaRegs.h" -+#include "cesa/AES/mvAes.h" -+ -+static const char* mvCesaDebugStateStr(MV_CESA_STATE state) -+{ -+ switch(state) -+ { -+ case MV_CESA_IDLE: -+ return "Idle"; -+ -+ case MV_CESA_PENDING: -+ return "Pend"; -+ -+ case MV_CESA_PROCESS: -+ return "Proc"; -+ -+ case MV_CESA_READY: -+ return "Ready"; -+ -+ default: -+ break; -+ } -+ return "Unknown"; -+} -+ -+static const char* mvCesaDebugOperStr(MV_CESA_OPERATION oper) -+{ -+ switch(oper) -+ { -+ case MV_CESA_MAC_ONLY: -+ return "MacOnly"; -+ -+ case MV_CESA_CRYPTO_ONLY: -+ return "CryptoOnly"; -+ -+ case MV_CESA_MAC_THEN_CRYPTO: -+ return "MacCrypto"; -+ -+ case MV_CESA_CRYPTO_THEN_MAC: -+ return "CryptoMac"; -+ -+ default: -+ break; -+ } -+ return "Null"; -+} -+ -+static const char* mvCesaDebugCryptoAlgStr(MV_CESA_CRYPTO_ALG cryptoAlg) -+{ -+ switch(cryptoAlg) -+ { -+ case MV_CESA_CRYPTO_DES: -+ return "DES"; -+ -+ case MV_CESA_CRYPTO_3DES: -+ return "3DES"; -+ -+ case MV_CESA_CRYPTO_AES: -+ return "AES"; -+ -+ default: -+ break; -+ } -+ return "Null"; -+} -+ -+static const char* mvCesaDebugMacModeStr(MV_CESA_MAC_MODE macMode) -+{ -+ switch(macMode) -+ { -+ case MV_CESA_MAC_MD5: -+ return "MD5"; -+ -+ case MV_CESA_MAC_SHA1: -+ return "SHA1"; -+ -+ case MV_CESA_MAC_HMAC_MD5: -+ return "HMAC-MD5"; -+ -+ case MV_CESA_MAC_HMAC_SHA1: -+ return "HMAC_SHA1"; -+ -+ default: -+ break; -+ } -+ return "Null"; -+} -+ -+void mvCesaDebugCmd(MV_CESA_COMMAND* pCmd, int mode) -+{ -+ mvOsPrintf("pCmd=%p, pReqPrv=%p, pSrc=%p, pDst=%p, pCB=%p, sid=%d\n", -+ pCmd, pCmd->pReqPrv, pCmd->pSrc, pCmd->pDst, -+ pCmd->pFuncCB, pCmd->sessionId); -+ mvOsPrintf("isUser=%d, ivOffs=%d, crOffs=%d, crLen=%d, digest=%d, macOffs=%d, macLen=%d\n", -+ pCmd->ivFromUser, pCmd->ivOffset, pCmd->cryptoOffset, pCmd->cryptoLength, -+ pCmd->digestOffset, pCmd->macOffset, pCmd->macLength); -+} -+ -+/* no need to use in tool */ -+void mvCesaDebugMbuf(const char* str, MV_CESA_MBUF *pMbuf, int offset, int size) -+{ -+ int frag, len, fragOffset; -+ -+ if(str != NULL) -+ mvOsPrintf("%s: pMbuf=%p, numFrags=%d, mbufSize=%d\n", -+ str, pMbuf, pMbuf->numFrags, pMbuf->mbufSize); -+ -+ frag = mvCesaMbufOffset(pMbuf, offset, &fragOffset); -+ if(frag == MV_INVALID) -+ { -+ mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); -+ return; -+ } -+ -+ for(; fragnumFrags; frag++) -+ { -+ mvOsPrintf("#%2d. bufVirt=%p, bufSize=%d\n", -+ frag, pMbuf->pFrags[frag].bufVirtPtr, -+ pMbuf->pFrags[frag].bufSize); -+ if(size > 0) -+ { -+ len = MV_MIN(pMbuf->pFrags[frag].bufSize, size); -+ mvDebugMemDump(pMbuf->pFrags[frag].bufVirtPtr+fragOffset, len, 1); -+ size -= len; -+ fragOffset = 0; -+ } -+ } -+} -+ -+void mvCesaDebugRegs(void) -+{ -+ mvOsPrintf("\t CESA Registers:\n"); -+ -+ mvOsPrintf("MV_CESA_CMD_REG : 0x%X = 0x%08x\n", -+ MV_CESA_CMD_REG, -+ MV_REG_READ( MV_CESA_CMD_REG ) ); -+ -+ mvOsPrintf("MV_CESA_CHAN_DESC_OFFSET_REG : 0x%X = 0x%08x\n", -+ MV_CESA_CHAN_DESC_OFFSET_REG, -+ MV_REG_READ(MV_CESA_CHAN_DESC_OFFSET_REG) ); -+ -+ mvOsPrintf("MV_CESA_CFG_REG : 0x%X = 0x%08x\n", -+ MV_CESA_CFG_REG, -+ MV_REG_READ( MV_CESA_CFG_REG ) ); -+ -+ mvOsPrintf("MV_CESA_STATUS_REG : 0x%X = 0x%08x\n", -+ MV_CESA_STATUS_REG, -+ MV_REG_READ( MV_CESA_STATUS_REG ) ); -+ -+ mvOsPrintf("MV_CESA_ISR_CAUSE_REG : 0x%X = 0x%08x\n", -+ MV_CESA_ISR_CAUSE_REG, -+ MV_REG_READ( MV_CESA_ISR_CAUSE_REG ) ); -+ -+ mvOsPrintf("MV_CESA_ISR_MASK_REG : 0x%X = 0x%08x\n", -+ MV_CESA_ISR_MASK_REG, -+ MV_REG_READ( MV_CESA_ISR_MASK_REG ) ); -+#if (MV_CESA_VERSION >= 2) -+ mvOsPrintf("MV_CESA_TDMA_CTRL_REG : 0x%X = 0x%08x\n", -+ MV_CESA_TDMA_CTRL_REG, -+ MV_REG_READ( MV_CESA_TDMA_CTRL_REG ) ); -+ -+ mvOsPrintf("MV_CESA_TDMA_BYTE_COUNT_REG : 0x%X = 0x%08x\n", -+ MV_CESA_TDMA_BYTE_COUNT_REG, -+ MV_REG_READ( MV_CESA_TDMA_BYTE_COUNT_REG ) ); -+ -+ mvOsPrintf("MV_CESA_TDMA_SRC_ADDR_REG : 0x%X = 0x%08x\n", -+ MV_CESA_TDMA_SRC_ADDR_REG, -+ MV_REG_READ( MV_CESA_TDMA_SRC_ADDR_REG ) ); -+ -+ mvOsPrintf("MV_CESA_TDMA_DST_ADDR_REG : 0x%X = 0x%08x\n", -+ MV_CESA_TDMA_DST_ADDR_REG, -+ MV_REG_READ( MV_CESA_TDMA_DST_ADDR_REG ) ); -+ -+ mvOsPrintf("MV_CESA_TDMA_NEXT_DESC_PTR_REG : 0x%X = 0x%08x\n", -+ MV_CESA_TDMA_NEXT_DESC_PTR_REG, -+ MV_REG_READ( MV_CESA_TDMA_NEXT_DESC_PTR_REG ) ); -+ -+ mvOsPrintf("MV_CESA_TDMA_CURR_DESC_PTR_REG : 0x%X = 0x%08x\n", -+ MV_CESA_TDMA_CURR_DESC_PTR_REG, -+ MV_REG_READ( MV_CESA_TDMA_CURR_DESC_PTR_REG ) ); -+ -+ mvOsPrintf("MV_CESA_TDMA_ERROR_CAUSE_REG : 0x%X = 0x%08x\n", -+ MV_CESA_TDMA_ERROR_CAUSE_REG, -+ MV_REG_READ( MV_CESA_TDMA_ERROR_CAUSE_REG ) ); -+ -+ mvOsPrintf("MV_CESA_TDMA_ERROR_MASK_REG : 0x%X = 0x%08x\n", -+ MV_CESA_TDMA_ERROR_MASK_REG, -+ MV_REG_READ( MV_CESA_TDMA_ERROR_CAUSE_REG ) ); -+ -+#endif -+} -+ -+void mvCesaDebugStatus(void) -+{ -+ mvOsPrintf("\n\t CESA Status\n\n"); -+ -+ mvOsPrintf("pReqQ=%p, qDepth=%d, reqSize=%ld bytes, qRes=%d, ", -+ pCesaReqFirst, cesaQueueDepth, sizeof(MV_CESA_REQ), -+ cesaReqResources); -+#if (MV_CESA_VERSION >= 3) -+ mvOsPrintf("chainLength=%u\n",cesaChainLength); -+#else -+ mvOsPrintf("\n"); -+#endif -+ -+ mvOsPrintf("pSAD=%p, maxSA=%d, sizeSA=%ld bytes\n", -+ pCesaSAD, cesaMaxSA, sizeof(MV_CESA_SA)); -+ -+ mvOsPrintf("\n"); -+ -+ mvCesaDebugRegs(); -+ mvCesaDebugStats(); -+ mvCesaDebugStatsClear(); -+} -+ -+void mvCesaDebugDescriptor(MV_CESA_DESC* pDesc) -+{ -+ mvOsPrintf("config=0x%08x, crSrcOffs=0x%04x, crDstOffs=0x%04x\n", -+ pDesc->config, pDesc->cryptoSrcOffset, pDesc->cryptoDstOffset); -+ -+ mvOsPrintf("crLen=0x%04x, crKeyOffs=0x%04x, ivOffs=0x%04x, ivBufOffs=0x%04x\n", -+ pDesc->cryptoDataLen, pDesc->cryptoKeyOffset, -+ pDesc->cryptoIvOffset, pDesc->cryptoIvBufOffset); -+ -+ mvOsPrintf("macSrc=0x%04x, digest=0x%04x, macLen=0x%04x, inIv=0x%04x, outIv=0x%04x\n", -+ pDesc->macSrcOffset, pDesc->macDigestOffset, pDesc->macDataLen, -+ pDesc->macInnerIvOffset, pDesc->macOuterIvOffset); -+} -+ -+void mvCesaDebugQueue(int mode) -+{ -+ mvOsPrintf("\n\t CESA Request Queue:\n\n"); -+ -+ mvOsPrintf("pFirstReq=%p, pLastReq=%p, qDepth=%d, reqSize=%ld bytes\n", -+ pCesaReqFirst, pCesaReqLast, cesaQueueDepth, sizeof(MV_CESA_REQ)); -+ -+ mvOsPrintf("pEmpty=%p, pProcess=%p, qResources=%d\n", -+ pCesaReqEmpty, pCesaReqProcess, -+ cesaReqResources); -+ -+ if(mode != 0) -+ { -+ int count = 0; -+ MV_CESA_REQ* pReq = pCesaReqFirst; -+ -+ for(count=0; countstate), -+ pReq->fragMode, pReq->pCmd, pReq->dma[0].pDmaFirst, &pReq->pCesaDesc[0]); -+ if(pReq->fragMode != MV_CESA_FRAG_NONE) -+ { -+ int frag; -+ -+ mvOsPrintf("pFrags=%p, num=%d, next=%d, bufOffset=%d, cryptoSize=%d, macSize=%d\n", -+ &pReq->frags, pReq->frags.numFrag, pReq->frags.nextFrag, -+ pReq->frags.bufOffset, pReq->frags.cryptoSize, pReq->frags.macSize); -+ for(frag=0; fragfrags.numFrag; frag++) -+ { -+ mvOsPrintf("#%d: pDmaFirst=%p, pDesc=%p\n", frag, -+ pReq->dma[frag].pDmaFirst, &pReq->pCesaDesc[frag]); -+ } -+ } -+ if(mode > 1) -+ { -+ /* Print out Command */ -+ mvCesaDebugCmd(pReq->pCmd, mode); -+ -+ /* Print out Descriptor */ -+ mvCesaDebugDescriptor(&pReq->pCesaDesc[0]); -+ } -+ pReq++; -+ } -+ } -+} -+ -+ -+void mvCesaDebugSramSA(MV_CESA_SRAM_SA* pSramSA, int mode) -+{ -+ if(pSramSA == NULL) -+ { -+ mvOsPrintf("cesaSramSA: Unexpected pSramSA=%p\n", pSramSA); -+ return; -+ } -+ mvOsPrintf("pSramSA=%p, sizeSramSA=%ld bytes\n", -+ pSramSA, sizeof(MV_CESA_SRAM_SA)); -+ -+ if(mode != 0) -+ { -+ mvOsPrintf("cryptoKey=%p, maxCryptoKey=%d bytes\n", -+ pSramSA->cryptoKey, MV_CESA_MAX_CRYPTO_KEY_LENGTH); -+ mvDebugMemDump(pSramSA->cryptoKey, MV_CESA_MAX_CRYPTO_KEY_LENGTH, 1); -+ -+ mvOsPrintf("macInnerIV=%p, maxInnerIV=%d bytes\n", -+ pSramSA->macInnerIV, MV_CESA_MAX_DIGEST_SIZE); -+ mvDebugMemDump(pSramSA->macInnerIV, MV_CESA_MAX_DIGEST_SIZE, 1); -+ -+ mvOsPrintf("macOuterIV=%p, maxOuterIV=%d bytes\n", -+ pSramSA->macOuterIV, MV_CESA_MAX_DIGEST_SIZE); -+ mvDebugMemDump(pSramSA->macOuterIV, MV_CESA_MAX_DIGEST_SIZE, 1); -+ } -+} -+ -+void mvCesaDebugSA(short sid, int mode) -+{ -+ MV_CESA_OPERATION oper; -+ MV_CESA_DIRECTION dir; -+ MV_CESA_CRYPTO_ALG cryptoAlg; -+ MV_CESA_CRYPTO_MODE cryptoMode; -+ MV_CESA_MAC_MODE macMode; -+ MV_CESA_SA* pSA = &pCesaSAD[sid]; -+ -+ if( (pSA->valid) || ((pSA->count != 0) && (mode > 0)) || (mode >= 2) ) -+ { -+ mvOsPrintf("\n\nCESA SA Entry #%d (%p) - %s (count=%d)\n", -+ sid, pSA, -+ pSA->valid ? "Valid" : "Invalid", pSA->count); -+ -+ oper = (pSA->config & MV_CESA_OPERATION_MASK) >> MV_CESA_OPERATION_OFFSET; -+ dir = (pSA->config & MV_CESA_DIRECTION_MASK) >> MV_CESA_DIRECTION_BIT; -+ mvOsPrintf("%s - %s ", mvCesaDebugOperStr(oper), -+ (dir == MV_CESA_DIR_ENCODE) ? "Encode" : "Decode"); -+ if(oper != MV_CESA_MAC_ONLY) -+ { -+ cryptoAlg = (pSA->config & MV_CESA_CRYPTO_ALG_MASK) >> MV_CESA_CRYPTO_ALG_OFFSET; -+ cryptoMode = (pSA->config & MV_CESA_CRYPTO_MODE_MASK) >> MV_CESA_CRYPTO_MODE_BIT; -+ mvOsPrintf("- %s - %s ", mvCesaDebugCryptoAlgStr(cryptoAlg), -+ (cryptoMode == MV_CESA_CRYPTO_ECB) ? "ECB" : "CBC"); -+ } -+ if(oper != MV_CESA_CRYPTO_ONLY) -+ { -+ macMode = (pSA->config & MV_CESA_MAC_MODE_MASK) >> MV_CESA_MAC_MODE_OFFSET; -+ mvOsPrintf("- %s ", mvCesaDebugMacModeStr(macMode)); -+ } -+ mvOsPrintf("\n"); -+ -+ if(mode > 0) -+ { -+ mvOsPrintf("config=0x%08x, cryptoKeySize=%d, digestSize=%d\n", -+ pCesaSAD[sid].config, pCesaSAD[sid].cryptoKeyLength, -+ pCesaSAD[sid].digestSize); -+ -+ mvCesaDebugSramSA(pCesaSAD[sid].pSramSA, mode); -+ } -+ } -+} -+ -+ -+/**/ -+void mvCesaDebugSram(int mode) -+{ -+ mvOsPrintf("\n\t SRAM contents: size=%ld, pVirt=%p\n\n", -+ sizeof(MV_CESA_SRAM_MAP), cesaSramVirtPtr); -+ -+ mvOsPrintf("\n\t Sram buffer: size=%d, pVirt=%p\n", -+ MV_CESA_MAX_BUF_SIZE, cesaSramVirtPtr->buf); -+ if(mode != 0) -+ mvDebugMemDump(cesaSramVirtPtr->buf, 64, 1); -+ -+ mvOsPrintf("\n"); -+ mvOsPrintf("\n\t Sram descriptor: size=%ld, pVirt=%p\n", -+ sizeof(MV_CESA_DESC), &cesaSramVirtPtr->desc); -+ if(mode != 0) -+ { -+ mvOsPrintf("\n"); -+ mvCesaDebugDescriptor(&cesaSramVirtPtr->desc); -+ } -+ mvOsPrintf("\n\t Sram IV: size=%d, pVirt=%p\n", -+ MV_CESA_MAX_IV_LENGTH, &cesaSramVirtPtr->cryptoIV); -+ if(mode != 0) -+ { -+ mvOsPrintf("\n"); -+ mvDebugMemDump(cesaSramVirtPtr->cryptoIV, MV_CESA_MAX_IV_LENGTH, 1); -+ } -+ mvOsPrintf("\n"); -+ mvCesaDebugSramSA(&cesaSramVirtPtr->sramSA, 0); -+} -+ -+void mvCesaDebugSAD(int mode) -+{ -+ int sid; -+ -+ mvOsPrintf("\n\t Cesa SAD status: pSAD=%p, maxSA=%d\n", -+ pCesaSAD, cesaMaxSA); -+ -+ for(sid=0; sid= 3) -+ mvOsPrintf("maxChainUsage=%u\n",cesaStats.maxChainUsage); -+#endif -+ mvOsPrintf("\n"); -+ mvOsPrintf("proc=%u, ready=%u, notReady=%u\n", -+ cesaStats.procCount, cesaStats.readyCount, cesaStats.notReadyCount); -+} -+ -+void mvCesaDebugStatsClear(void) -+{ -+ memset(&cesaStats, 0, sizeof(cesaStats)); -+} -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/cesa/mvCesaRegs.h linux-2.6.39/crypto/ocf/kirkwood/cesa/mvCesaRegs.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/cesa/mvCesaRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/cesa/mvCesaRegs.h 2011-08-01 14:38:18.000000000 +0200 -@@ -0,0 +1,357 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __mvCesaRegs_h__ -+#define __mvCesaRegs_h__ -+ -+#include "mvTypes.h" -+ -+typedef struct -+{ -+ /* word 0 */ -+ MV_U32 config; -+ /* word 1 */ -+ MV_U16 cryptoSrcOffset; -+ MV_U16 cryptoDstOffset; -+ /* word 2 */ -+ MV_U16 cryptoDataLen; -+ MV_U16 reserved1; -+ /* word 3 */ -+ MV_U16 cryptoKeyOffset; -+ MV_U16 reserved2; -+ /* word 4 */ -+ MV_U16 cryptoIvOffset; -+ MV_U16 cryptoIvBufOffset; -+ /* word 5 */ -+ MV_U16 macSrcOffset; -+ MV_U16 macTotalLen; -+ /* word 6 */ -+ MV_U16 macDigestOffset; -+ MV_U16 macDataLen; -+ /* word 7 */ -+ MV_U16 macInnerIvOffset; -+ MV_U16 macOuterIvOffset; -+ -+} MV_CESA_DESC; -+ -+/* operation */ -+typedef enum -+{ -+ MV_CESA_MAC_ONLY = 0, -+ MV_CESA_CRYPTO_ONLY = 1, -+ MV_CESA_MAC_THEN_CRYPTO = 2, -+ MV_CESA_CRYPTO_THEN_MAC = 3, -+ -+ MV_CESA_MAX_OPERATION -+ -+} MV_CESA_OPERATION; -+ -+#define MV_CESA_OPERATION_OFFSET 0 -+#define MV_CESA_OPERATION_MASK (0x3 << MV_CESA_OPERATION_OFFSET) -+ -+/* mac algorithm */ -+typedef enum -+{ -+ MV_CESA_MAC_NULL = 0, -+ MV_CESA_MAC_MD5 = 4, -+ MV_CESA_MAC_SHA1 = 5, -+ MV_CESA_MAC_HMAC_MD5 = 6, -+ MV_CESA_MAC_HMAC_SHA1 = 7, -+ -+} MV_CESA_MAC_MODE; -+ -+#define MV_CESA_MAC_MODE_OFFSET 4 -+#define MV_CESA_MAC_MODE_MASK (0x7 << MV_CESA_MAC_MODE_OFFSET) -+ -+typedef enum -+{ -+ MV_CESA_MAC_DIGEST_FULL = 0, -+ MV_CESA_MAC_DIGEST_96B = 1, -+ -+} MV_CESA_MAC_DIGEST_SIZE; -+ -+#define MV_CESA_MAC_DIGEST_SIZE_BIT 7 -+#define MV_CESA_MAC_DIGEST_SIZE_MASK (1 << MV_CESA_MAC_DIGEST_SIZE_BIT) -+ -+ -+typedef enum -+{ -+ MV_CESA_CRYPTO_NULL = 0, -+ MV_CESA_CRYPTO_DES = 1, -+ MV_CESA_CRYPTO_3DES = 2, -+ MV_CESA_CRYPTO_AES = 3, -+ -+} MV_CESA_CRYPTO_ALG; -+ -+#define MV_CESA_CRYPTO_ALG_OFFSET 8 -+#define MV_CESA_CRYPTO_ALG_MASK (0x3 << MV_CESA_CRYPTO_ALG_OFFSET) -+ -+ -+/* direction */ -+typedef enum -+{ -+ MV_CESA_DIR_ENCODE = 0, -+ MV_CESA_DIR_DECODE = 1, -+ -+} MV_CESA_DIRECTION; -+ -+#define MV_CESA_DIRECTION_BIT 12 -+#define MV_CESA_DIRECTION_MASK (1 << MV_CESA_DIRECTION_BIT) -+ -+/* crypto IV mode */ -+typedef enum -+{ -+ MV_CESA_CRYPTO_ECB = 0, -+ MV_CESA_CRYPTO_CBC = 1, -+ -+ /* NO HW Support */ -+ MV_CESA_CRYPTO_CTR = 10, -+ -+} MV_CESA_CRYPTO_MODE; -+ -+#define MV_CESA_CRYPTO_MODE_BIT 16 -+#define MV_CESA_CRYPTO_MODE_MASK (1 << MV_CESA_CRYPTO_MODE_BIT) -+ -+/* 3DES mode */ -+typedef enum -+{ -+ MV_CESA_CRYPTO_3DES_EEE = 0, -+ MV_CESA_CRYPTO_3DES_EDE = 1, -+ -+} MV_CESA_CRYPTO_3DES_MODE; -+ -+#define MV_CESA_CRYPTO_3DES_MODE_BIT 20 -+#define MV_CESA_CRYPTO_3DES_MODE_MASK (1 << MV_CESA_CRYPTO_3DES_MODE_BIT) -+ -+ -+/* AES Key Length */ -+typedef enum -+{ -+ MV_CESA_CRYPTO_AES_KEY_128 = 0, -+ MV_CESA_CRYPTO_AES_KEY_192 = 1, -+ MV_CESA_CRYPTO_AES_KEY_256 = 2, -+ -+} MV_CESA_CRYPTO_AES_KEY_LEN; -+ -+#define MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET 24 -+#define MV_CESA_CRYPTO_AES_KEY_LEN_MASK (0x3 << MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET) -+ -+/* Fragmentation mode */ -+typedef enum -+{ -+ MV_CESA_FRAG_NONE = 0, -+ MV_CESA_FRAG_FIRST = 1, -+ MV_CESA_FRAG_LAST = 2, -+ MV_CESA_FRAG_MIDDLE = 3, -+ -+} MV_CESA_FRAG_MODE; -+ -+#define MV_CESA_FRAG_MODE_OFFSET 30 -+#define MV_CESA_FRAG_MODE_MASK (0x3 << MV_CESA_FRAG_MODE_OFFSET) -+/*---------------------------------------------------------------------------*/ -+ -+/********** Security Accelerator Command Register **************/ -+#define MV_CESA_CMD_REG (MV_CESA_REG_BASE + 0xE00) -+ -+#define MV_CESA_CMD_CHAN_ENABLE_BIT 0 -+#define MV_CESA_CMD_CHAN_ENABLE_MASK (1 << MV_CESA_CMD_CHAN_ENABLE_BIT) -+ -+#define MV_CESA_CMD_CHAN_DISABLE_BIT 2 -+#define MV_CESA_CMD_CHAN_DISABLE_MASK (1 << MV_CESA_CMD_CHAN_DISABLE_BIT) -+ -+/********** Security Accelerator Descriptor Pointers Register **********/ -+#define MV_CESA_CHAN_DESC_OFFSET_REG (MV_CESA_REG_BASE + 0xE04) -+ -+/********** Security Accelerator Configuration Register **********/ -+#define MV_CESA_CFG_REG (MV_CESA_REG_BASE + 0xE08) -+ -+#define MV_CESA_CFG_STOP_DIGEST_ERR_BIT 0 -+#define MV_CESA_CFG_STOP_DIGEST_ERR_MASK (1 << MV_CESA_CFG_STOP_DIGEST_ERR_BIT) -+ -+#define MV_CESA_CFG_WAIT_DMA_BIT 7 -+#define MV_CESA_CFG_WAIT_DMA_MASK (1 << MV_CESA_CFG_WAIT_DMA_BIT) -+ -+#define MV_CESA_CFG_ACT_DMA_BIT 9 -+#define MV_CESA_CFG_ACT_DMA_MASK (1 << MV_CESA_CFG_ACT_DMA_BIT) -+ -+#define MV_CESA_CFG_CHAIN_MODE_BIT 11 -+#define MV_CESA_CFG_CHAIN_MODE_MASK (1 << MV_CESA_CFG_CHAIN_MODE_BIT) -+ -+/********** Security Accelerator Status Register ***********/ -+#define MV_CESA_STATUS_REG (MV_CESA_REG_BASE + 0xE0C) -+ -+#define MV_CESA_STATUS_ACTIVE_BIT 0 -+#define MV_CESA_STATUS_ACTIVE_MASK (1 << MV_CESA_STATUS_ACTIVE_BIT) -+ -+#define MV_CESA_STATUS_DIGEST_ERR_BIT 8 -+#define MV_CESA_STATUS_DIGEST_ERR_MASK (1 << MV_CESA_STATUS_DIGEST_ERR_BIT) -+ -+ -+/* Cryptographic Engines and Security Accelerator Interrupt Cause Register */ -+#define MV_CESA_ISR_CAUSE_REG (MV_CESA_REG_BASE + 0xE20) -+ -+/* Cryptographic Engines and Security Accelerator Interrupt Mask Register */ -+#define MV_CESA_ISR_MASK_REG (MV_CESA_REG_BASE + 0xE24) -+ -+#define MV_CESA_CAUSE_AUTH_MASK (1 << 0) -+#define MV_CESA_CAUSE_DES_MASK (1 << 1) -+#define MV_CESA_CAUSE_AES_ENCR_MASK (1 << 2) -+#define MV_CESA_CAUSE_AES_DECR_MASK (1 << 3) -+#define MV_CESA_CAUSE_DES_ALL_MASK (1 << 4) -+ -+#define MV_CESA_CAUSE_ACC_BIT 5 -+#define MV_CESA_CAUSE_ACC_MASK (1 << MV_CESA_CAUSE_ACC_BIT) -+ -+#define MV_CESA_CAUSE_ACC_DMA_BIT 7 -+#define MV_CESA_CAUSE_ACC_DMA_MASK (1 << MV_CESA_CAUSE_ACC_DMA_BIT) -+#define MV_CESA_CAUSE_ACC_DMA_ALL_MASK (3 << MV_CESA_CAUSE_ACC_DMA_BIT) -+ -+#define MV_CESA_CAUSE_DMA_COMPL_BIT 9 -+#define MV_CESA_CAUSE_DMA_COMPL_MASK (1 << MV_CESA_CAUSE_DMA_COMPL_BIT) -+ -+#define MV_CESA_CAUSE_DMA_OWN_ERR_BIT 10 -+#define MV_CESA_CAUSE_DMA_OWN_ERR_MASK (1 < MV_CESA_CAUSE_DMA_OWN_ERR_BIT) -+ -+#define MV_CESA_CAUSE_DMA_CHAIN_PKT_BIT 11 -+#define MV_CESA_CAUSE_DMA_CHAIN_PKT_MASK (1 < MV_CESA_CAUSE_DMA_CHAIN_PKT_BIT) -+ -+ -+#define MV_CESA_AUTH_DATA_IN_REG (MV_CESA_REG_BASE + 0xd38) -+#define MV_CESA_AUTH_BIT_COUNT_LOW_REG (MV_CESA_REG_BASE + 0xd20) -+#define MV_CESA_AUTH_BIT_COUNT_HIGH_REG (MV_CESA_REG_BASE + 0xd24) -+ -+#define MV_CESA_AUTH_INIT_VAL_DIGEST_REG(i) (MV_CESA_REG_BASE + 0xd00 + (i<<2)) -+ -+#define MV_CESA_AUTH_INIT_VAL_DIGEST_A_REG (MV_CESA_REG_BASE + 0xd00) -+#define MV_CESA_AUTH_INIT_VAL_DIGEST_B_REG (MV_CESA_REG_BASE + 0xd04) -+#define MV_CESA_AUTH_INIT_VAL_DIGEST_C_REG (MV_CESA_REG_BASE + 0xd08) -+#define MV_CESA_AUTH_INIT_VAL_DIGEST_D_REG (MV_CESA_REG_BASE + 0xd0c) -+#define MV_CESA_AUTH_INIT_VAL_DIGEST_E_REG (MV_CESA_REG_BASE + 0xd10) -+#define MV_CESA_AUTH_COMMAND_REG (MV_CESA_REG_BASE + 0xd18) -+ -+#define MV_CESA_AUTH_ALGORITHM_BIT 0 -+#define MV_CESA_AUTH_ALGORITHM_MD5 (0< -+wait_queue_head_t cesaTest_waitq; -+spinlock_t cesaLock; -+ -+#define CESA_TEST_LOCK(flags) spin_lock_irqsave( &cesaLock, flags) -+#define CESA_TEST_UNLOCK(flags) spin_unlock_irqrestore( &cesaLock, flags); -+ -+#define CESA_TEST_WAIT_INIT() init_waitqueue_head(&cesaTest_waitq) -+#define CESA_TEST_WAKE_UP() wake_up(&cesaTest_waitq) -+#define CESA_TEST_WAIT(cond, ms) wait_event_timeout(cesaTest_waitq, (cond), msecs_to_jiffies(ms)) -+ -+#define CESA_TEST_TICK_GET() jiffies -+#define CESA_TEST_TICK_TO_MS(tick) jiffies_to_msecs(tick) -+ -+#elif defined(MV_NETBSD) -+ -+#include -+#include -+static int cesaLock; -+ -+#define CESA_TEST_LOCK(flags) flags = splnet() -+#define CESA_TEST_UNLOCK(flags) splx(flags) -+ -+#define CESA_TEST_WAIT_INIT() /* nothing */ -+#define CESA_TEST_WAKE_UP() wakeup(&cesaLock) -+#define CESA_TEST_WAIT(cond, ms) \ -+do { \ -+ while (!(cond)) \ -+ tsleep(&cesaLock, PWAIT, "cesatest",mstohz(ms)); \ -+} while (/*CONSTCOND*/0) -+ -+#define CESA_TEST_TICK_GET() hardclock_ticks -+#define CESA_TEST_TICK_TO_MS(tick) ((1000/hz)*(tick)) -+ -+#define request_irq(i,h,t,n,a) \ -+ !mv_intr_establish((i),IPL_NET,(int(*)(void *))(h),(a)) -+ -+#else -+#error "Only Linux, VxWorks, or NetBSD OS are supported" -+#endif -+ -+#include "mvDebug.h" -+ -+#include "mvSysHwConfig.h" -+#include "boardEnv/mvBoardEnvLib.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+#include "cntmr/mvCntmr.h" -+#include "cesa/mvCesa.h" -+#include "cesa/mvCesaRegs.h" -+#include "cesa/mvMD5.h" -+#include "cesa/mvSHA1.h" -+ -+#if defined(CONFIG_MV646xx) -+#include "marvell_pic.h" -+#endif -+ -+#define MV_CESA_USE_TIMER_ID 0 -+#define CESA_DEF_BUF_SIZE 1500 -+#define CESA_DEF_BUF_NUM 1 -+#define CESA_DEF_SESSION_NUM 32 -+ -+#define CESA_DEF_ITER_NUM 100 -+ -+#define CESA_DEF_REQ_SIZE 256 -+ -+ -+/* CESA Tests Debug */ -+#undef CESA_TEST_DEBUG -+ -+#ifdef CESA_TEST_DEBUG -+ -+# define CESA_TEST_DEBUG_PRINT(msg) mvOsPrintf msg -+# define CESA_TEST_DEBUG_CODE(code) code -+ -+typedef struct -+{ -+ int type; /* 0 - isrEmpty, 1 - cesaReadyGet, 2 - cesaAction */ -+ MV_U32 timeStamp; -+ MV_U32 cause; -+ MV_U32 realCause; -+ MV_U32 dmaCause; -+ int resources; -+ MV_CESA_REQ* pReqReady; -+ MV_CESA_REQ* pReqEmpty; -+ MV_CESA_REQ* pReqProcess; -+} MV_CESA_TEST_TRACE; -+ -+#define MV_CESA_TEST_TRACE_SIZE 25 -+ -+static int cesaTestTraceIdx = 0; -+static MV_CESA_TEST_TRACE cesaTestTrace[MV_CESA_TEST_TRACE_SIZE]; -+ -+static void cesaTestTraceAdd(int type, MV_U32 cause) -+{ -+ cesaTestTrace[cesaTestTraceIdx].type = type; -+ cesaTestTrace[cesaTestTraceIdx].cause = cause; -+ cesaTestTrace[cesaTestTraceIdx].realCause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); -+ cesaTestTrace[cesaTestTraceIdx].dmaCause = MV_REG_READ(IDMA_CAUSE_REG); -+ cesaTestTrace[cesaTestTraceIdx].resources = cesaReqResources; -+ cesaTestTrace[cesaTestTraceIdx].pReqReady = pCesaReqReady; -+ cesaTestTrace[cesaTestTraceIdx].pReqEmpty = pCesaReqEmpty; -+ cesaTestTrace[cesaTestTraceIdx].pReqProcess = pCesaReqProcess; -+ cesaTestTrace[cesaTestTraceIdx].timeStamp = mvCntmrRead(MV_CESA_USE_TIMER_ID); -+ cesaTestTraceIdx++; -+ if(cesaTestTraceIdx == MV_CESA_TEST_TRACE_SIZE) -+ cesaTestTraceIdx = 0; -+} -+ -+#else -+ -+# define CESA_TEST_DEBUG_PRINT(msg) -+# define CESA_TEST_DEBUG_CODE(code) -+ -+#endif /* CESA_TEST_DEBUG */ -+ -+int cesaExpReqId=0; -+int cesaCbIter=0; -+ -+int cesaIdx; -+int cesaIteration; -+int cesaRateSize; -+int cesaReqSize; -+unsigned long cesaTaskId; -+int cesaBufNum; -+int cesaBufSize; -+int cesaCheckOffset; -+int cesaCheckSize; -+int cesaCheckMode; -+int cesaTestIdx; -+int cesaCaseIdx; -+ -+ -+MV_U32 cesaTestIsrCount = 0; -+MV_U32 cesaTestIsrMissCount = 0; -+ -+MV_U32 cesaCryptoError = 0; -+MV_U32 cesaReqIdError = 0; -+MV_U32 cesaError = 0; -+ -+char* cesaHexBuffer = NULL; -+ -+char* cesaBinBuffer = NULL; -+char* cesaExpBinBuffer = NULL; -+ -+char* cesaInputHexStr = NULL; -+char* cesaOutputHexStr = NULL; -+ -+MV_BUF_INFO cesaReqBufs[CESA_DEF_REQ_SIZE]; -+ -+MV_CESA_COMMAND* cesaCmdRing; -+MV_CESA_RESULT cesaResult; -+ -+int cesaTestFull = 0; -+ -+MV_BOOL cesaIsReady = MV_FALSE; -+MV_U32 cesaCycles = 0; -+MV_U32 cesaBeginTicks = 0; -+MV_U32 cesaEndTicks = 0; -+MV_U32 cesaRate = 0; -+MV_U32 cesaRateAfterDot = 0; -+ -+void *cesaTestOSHandle = NULL; -+ -+enum -+{ -+ CESA_FAST_CHECK_MODE = 0, -+ CESA_FULL_CHECK_MODE, -+ CESA_NULL_CHECK_MODE, -+ CESA_SHOW_CHECK_MODE, -+ CESA_SW_SHOW_CHECK_MODE, -+ CESA_SW_NULL_CHECK_MODE, -+ -+ CESA_MAX_CHECK_MODE -+}; -+ -+enum -+{ -+ DES_TEST_TYPE = 0, -+ TRIPLE_DES_TEST_TYPE = 1, -+ AES_TEST_TYPE = 2, -+ MD5_TEST_TYPE = 3, -+ SHA_TEST_TYPE = 4, -+ COMBINED_TEST_TYPE = 5, -+ -+ MAX_TEST_TYPE -+}; -+ -+/* Tests data base */ -+typedef struct -+{ -+ short sid; -+ char cryptoAlgorithm; /* DES/3DES/AES */ -+ char cryptoMode; /* ECB or CBC */ -+ char macAlgorithm; /* MD5 / SHA1 */ -+ char operation; /* CRYPTO/HMAC/CRYPTO+HMAC/HMAC+CRYPTO */ -+ char direction; /* ENCODE(SIGN)/DECODE(VERIFY) */ -+ unsigned char* pCryptoKey; -+ int cryptoKeySize; -+ unsigned char* pMacKey; -+ int macKeySize; -+ const char* name; -+ -+} MV_CESA_TEST_SESSION; -+ -+typedef struct -+{ -+ MV_CESA_TEST_SESSION* pSessions; -+ int numSessions; -+ -+} MV_CESA_TEST_DB_ENTRY; -+ -+typedef struct -+{ -+ char* plainHexStr; -+ char* cipherHexStr; -+ unsigned char* pCryptoIV; -+ int cryptoLength; -+ int macLength; -+ int digestOffset; -+ -+} MV_CESA_TEST_CASE; -+ -+typedef struct -+{ -+ int size; -+ const char* outputHexStr; -+ -+} MV_CESA_SIZE_TEST; -+ -+static unsigned char cryptoKey1[] = {0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, -+ 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, -+ 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef}; -+ -+static unsigned char cryptoKey7[] = {0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef}; -+static unsigned char iv1[] = {0x12, 0x34, 0x56, 0x78, 0x90, 0xab, 0xcd, 0xef}; -+ -+ -+static unsigned char cryptoKey2[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, -+ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F}; -+ -+static unsigned char cryptoKey3[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, -+ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, -+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17}; -+ -+static unsigned char cryptoKey4[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, -+ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, -+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, -+ 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f}; -+ -+static unsigned char cryptoKey5[] = {0x56, 0xe4, 0x7a, 0x38, 0xc5, 0x59, 0x89, 0x74, -+ 0xbc, 0x46, 0x90, 0x3d, 0xba, 0x29, 0x03, 0x49}; -+ -+ -+static unsigned char key3des1[] = {0x01, 0x23, 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF, -+ 0x23, 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF, 0x01, -+ 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF, 0x01, 0x23}; -+ -+/* Input ASCII string: The quick brown fox jump */ -+static char plain3des1[] = "54686520717566636B2062726F776E20666F78206A756D70"; -+static char cipher3des1[] = "A826FD8CE53B855FCCE21C8112256FE668D5C05DD9B6B900"; -+ -+static unsigned char key3des2[] = {0x62, 0x7f, 0x46, 0x0e, 0x08, 0x10, 0x4a, 0x10, -+ 0x43, 0xcd, 0x26, 0x5d, 0x58, 0x40, 0xea, 0xf1, -+ 0x31, 0x3e, 0xdf, 0x97, 0xdf, 0x2a, 0x8a, 0x8c}; -+ -+static unsigned char iv3des2[] = {0x8e, 0x29, 0xf7, 0x5e, 0xa7, 0x7e, 0x54, 0x75}; -+ -+static char plain3des2[] = "326a494cd33fe756"; -+ -+static char cipher3desCbc2[] = "8e29f75ea77e5475" -+ "b22b8d66de970692"; -+ -+static unsigned char key3des3[] = {0x37, 0xae, 0x5e, 0xbf, 0x46, 0xdf, 0xf2, 0xdc, -+ 0x07, 0x54, 0xb9, 0x4f, 0x31, 0xcb, 0xb3, 0x85, -+ 0x5e, 0x7f, 0xd3, 0x6d, 0xc8, 0x70, 0xbf, 0xae}; -+ -+static unsigned char iv3des3[] = {0x3d, 0x1d, 0xe3, 0xcc, 0x13, 0x2e, 0x3b, 0x65}; -+ -+static char plain3des3[] = "84401f78fe6c10876d8ea23094ea5309"; -+ -+static char cipher3desCbc3[] = "3d1de3cc132e3b65" -+ "7b1f7c7e3b1c948ebd04a75ffba7d2f5"; -+ -+static unsigned char iv5[] = {0x8c, 0xe8, 0x2e, 0xef, 0xbe, 0xa0, 0xda, 0x3c, -+ 0x44, 0x69, 0x9e, 0xd7, 0xdb, 0x51, 0xb7, 0xd9}; -+ -+static unsigned char aesCtrKey[] = {0x76, 0x91, 0xBE, 0x03, 0x5E, 0x50, 0x20, 0xA8, -+ 0xAC, 0x6E, 0x61, 0x85, 0x29, 0xF9, 0xA0, 0xDC}; -+ -+static unsigned char mdKey1[] = {0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, -+ 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b}; -+ -+static unsigned char mdKey2[] = {0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -+ 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa}; -+ -+static unsigned char shaKey1[] = {0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, -+ 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, -+ 0x0b, 0x0b, 0x0b, 0x0b}; -+ -+static unsigned char shaKey2[] = {0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -+ 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -+ 0xaa, 0xaa, 0xaa, 0xaa}; -+ -+static unsigned char mdKey4[] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10}; -+ -+static unsigned char shaKey4[] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10, -+ 0x11, 0x12, 0x13, 0x14}; -+ -+ -+static MV_CESA_TEST_SESSION desTestSessions[] = -+{ -+/*000*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey7, sizeof(cryptoKey7)/sizeof(cryptoKey7[0]), -+ NULL, 0, -+ "DES ECB encode", -+ }, -+/*001*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_DECODE, -+ cryptoKey7, sizeof(cryptoKey7)/sizeof(cryptoKey7[0]), -+ NULL, 0, -+ "DES ECB decode", -+ }, -+/*002*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey7, sizeof(cryptoKey7)/sizeof(cryptoKey7[0]), -+ NULL, 0, -+ "DES CBC encode" -+ }, -+/*003*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_DECODE, -+ cryptoKey7, sizeof(cryptoKey7)/sizeof(cryptoKey7[0]), -+ NULL, 0, -+ "DES CBC decode" -+ }, -+/*004*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, NULL, 0, -+ "NULL Crypto Algorithm encode" -+ }, -+}; -+ -+ -+static MV_CESA_TEST_SESSION tripleDesTestSessions[] = -+{ -+/*100*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ NULL, 0, -+ "3DES ECB encode", -+ }, -+/*101*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_DECODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ NULL, 0, -+ "3DES ECB decode", -+ }, -+/*102*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ NULL, 0, -+ "3DES CBC encode" -+ }, -+/*103*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_DECODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ NULL, 0, -+ "3DES CBC decode" -+ }, -+/*104*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ key3des1, sizeof(key3des1), -+ NULL, 0, -+ "3DES ECB encode" -+ }, -+/*105*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ key3des2, sizeof(key3des2), -+ NULL, 0, -+ "3DES ECB encode" -+ }, -+/*106*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ key3des3, sizeof(key3des3), -+ NULL, 0, -+ "3DES ECB encode" -+ }, -+}; -+ -+ -+static MV_CESA_TEST_SESSION aesTestSessions[] = -+{ -+/*200*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey2, sizeof(cryptoKey2)/sizeof(cryptoKey2[0]), -+ NULL, 0, -+ "AES-128 ECB encode" -+ }, -+/*201*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_DECODE, -+ cryptoKey2, sizeof(cryptoKey2)/sizeof(cryptoKey2[0]), -+ NULL, 0, -+ "AES-128 ECB decode" -+ }, -+/*202*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey5, sizeof(cryptoKey5)/sizeof(cryptoKey5[0]), -+ NULL, 0, -+ "AES-128 CBC encode" -+ }, -+/*203*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_DECODE, -+ cryptoKey5, sizeof(cryptoKey5)/sizeof(cryptoKey5[0]), -+ NULL, 0, -+ "AES-128 CBC decode" -+ }, -+/*204*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey3, sizeof(cryptoKey3)/sizeof(cryptoKey3[0]), -+ NULL, 0, -+ "AES-192 ECB encode" -+ }, -+/*205*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_DECODE, -+ cryptoKey3, sizeof(cryptoKey3)/sizeof(cryptoKey3[0]), -+ NULL, 0, -+ "AES-192 ECB decode" -+ }, -+/*206*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey4, sizeof(cryptoKey4)/sizeof(cryptoKey4[0]), -+ NULL, 0, -+ "AES-256 ECB encode" -+ }, -+/*207*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_DECODE, -+ cryptoKey4, sizeof(cryptoKey4)/sizeof(cryptoKey4[0]), -+ NULL, 0, -+ "AES-256 ECB decode" -+ }, -+/*208*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CTR, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ aesCtrKey, sizeof(aesCtrKey)/sizeof(aesCtrKey[0]), -+ NULL, 0, -+ "AES-128 CTR encode" -+ }, -+}; -+ -+ -+static MV_CESA_TEST_SESSION md5TestSessions[] = -+{ -+/*300*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, -+ mdKey1, sizeof(mdKey1), -+ "HMAC-MD5 Generate Signature" -+ }, -+/*301*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_DECODE, -+ NULL, 0, -+ mdKey1, sizeof(mdKey1), -+ "HMAC-MD5 Verify Signature" -+ }, -+/*302*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, -+ mdKey2, sizeof(mdKey2), -+ "HMAC-MD5 Generate Signature" -+ }, -+/*303*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_DECODE, -+ NULL, 0, -+ mdKey2, sizeof(mdKey2), -+ "HMAC-MD5 Verify Signature" -+ }, -+/*304*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, -+ mdKey4, sizeof(mdKey4), -+ "HMAC-MD5 Generate Signature" -+ }, -+/*305*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_MD5, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, -+ NULL, 0, -+ "HASH-MD5 Generate Signature" -+ }, -+}; -+ -+ -+static MV_CESA_TEST_SESSION shaTestSessions[] = -+{ -+/*400*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, -+ shaKey1, sizeof(shaKey1), -+ "HMAC-SHA1 Generate Signature" -+ }, -+/*401*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_DECODE, -+ NULL, 0, -+ shaKey1, sizeof(shaKey1), -+ "HMAC-SHA1 Verify Signature" -+ }, -+/*402*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, -+ shaKey2, sizeof(shaKey2), -+ "HMAC-SHA1 Generate Signature" -+ }, -+/*403*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_DECODE, -+ NULL, 0, -+ shaKey2, sizeof(shaKey2), -+ "HMAC-SHA1 Verify Signature" -+ }, -+/*404*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, -+ shaKey4, sizeof(shaKey4), -+ "HMAC-SHA1 Generate Signature" -+ }, -+/*405*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_SHA1, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, -+ NULL, 0, -+ "HASH-SHA1 Generate Signature" -+ }, -+}; -+ -+static MV_CESA_TEST_SESSION combinedTestSessions[] = -+{ -+/*500*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey1, MV_CESA_DES_KEY_LENGTH, -+ mdKey4, sizeof(mdKey4), -+ "DES + MD5 encode" -+ }, -+/*501*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey1, MV_CESA_DES_KEY_LENGTH, -+ shaKey4, sizeof(shaKey4), -+ "DES + SHA1 encode" -+ }, -+/*502*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ mdKey4, sizeof(mdKey4), -+ "3DES + MD5 encode" -+ }, -+/*503*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ shaKey4, sizeof(shaKey4), -+ "3DES + SHA1 encode" -+ }, -+/*504*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ mdKey4, sizeof(mdKey4), -+ "3DES CBC + MD5 encode" -+ }, -+/*505*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ shaKey4, sizeof(shaKey4), -+ "3DES CBC + SHA1 encode" -+ }, -+/*506*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey5, sizeof(cryptoKey5)/sizeof(cryptoKey5[0]), -+ mdKey4, sizeof(mdKey4), -+ "AES-128 CBC + MD5 encode" -+ }, -+/*507*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey5, sizeof(cryptoKey5)/sizeof(cryptoKey5[0]), -+ shaKey4, sizeof(shaKey4), -+ "AES-128 CBC + SHA1 encode" -+ }, -+/*508*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_THEN_CRYPTO, -+ MV_CESA_DIR_DECODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ mdKey4, sizeof(mdKey4), -+ "HMAC-MD5 + 3DES decode" -+ }, -+}; -+ -+ -+static MV_CESA_TEST_DB_ENTRY cesaTestsDB[MAX_TEST_TYPE+1] = -+{ -+ { desTestSessions, sizeof(desTestSessions)/sizeof(desTestSessions[0]) }, -+ { tripleDesTestSessions, sizeof(tripleDesTestSessions)/sizeof(tripleDesTestSessions[0]) }, -+ { aesTestSessions, sizeof(aesTestSessions)/sizeof(aesTestSessions[0]) }, -+ { md5TestSessions, sizeof(md5TestSessions)/sizeof(md5TestSessions[0]) }, -+ { shaTestSessions, sizeof(shaTestSessions)/sizeof(shaTestSessions[0]) }, -+ { combinedTestSessions, sizeof(combinedTestSessions)/sizeof(combinedTestSessions[0]) }, -+ { NULL, 0 } -+}; -+ -+ -+char cesaNullPlainHexText[] = "000000000000000000000000000000000000000000000000"; -+ -+char cesaPlainAsciiText[] = "Now is the time for all "; -+char cesaPlainHexEbc[] = "4e6f77206973207468652074696d6520666f7220616c6c20"; -+char cesaCipherHexEcb[] = "3fa40e8a984d48156a271787ab8883f9893d51ec4b563b53"; -+char cesaPlainHexCbc[] = "1234567890abcdef4e6f77206973207468652074696d6520666f7220616c6c20"; -+char cesaCipherHexCbc[] = "1234567890abcdefe5c7cdde872bf27c43e934008c389c0f683788499a7c05f6"; -+ -+char cesaAesPlainHexEcb[] = "000102030405060708090a0b0c0d0e0f"; -+char cesaAes128cipherHexEcb[] = "0a940bb5416ef045f1c39458c653ea5a"; -+char cesaAes192cipherHexEcb[] = "0060bffe46834bb8da5cf9a61ff220ae"; -+char cesaAes256cipherHexEcb[] = "5a6e045708fb7196f02e553d02c3a692"; -+ -+char cesaAsciiStr1[] = "Hi There"; -+char cesaDataHexStr1[] = "4869205468657265"; -+char cesaHmacMd5digestHex1[] = "9294727a3638bb1c13f48ef8158bfc9d"; -+char cesaHmacSha1digestHex1[] = "b617318655057264e28bc0b6fb378c8ef146be00"; -+char cesaDataAndMd5digest1[] = "48692054686572659294727a3638bb1c13f48ef8158bfc9d"; -+char cesaDataAndSha1digest1[] = "4869205468657265b617318655057264e28bc0b6fb378c8ef146be00"; -+ -+char cesaAesPlainText[] = "a0a1a2a3a4a5a6a7a8a9aaabacadaeaf" -+ "b0b1b2b3b4b5b6b7b8b9babbbcbdbebf" -+ "c0c1c2c3c4c5c6c7c8c9cacbcccdcecf" -+ "d0d1d2d3d4d5d6d7d8d9dadbdcdddedf"; -+ -+char cesaAes128CipherCbc[] = "c30e32ffedc0774e6aff6af0869f71aa" -+ "0f3af07a9a31a9c684db207eb0ef8e4e" -+ "35907aa632c3ffdf868bb7b29d3d46ad" -+ "83ce9f9a102ee99d49a53e87f4c3da55"; -+ -+char cesaAesIvPlainText[] = "8ce82eefbea0da3c44699ed7db51b7d9" -+ "a0a1a2a3a4a5a6a7a8a9aaabacadaeaf" -+ "b0b1b2b3b4b5b6b7b8b9babbbcbdbebf" -+ "c0c1c2c3c4c5c6c7c8c9cacbcccdcecf" -+ "d0d1d2d3d4d5d6d7d8d9dadbdcdddedf"; -+ -+char cesaAes128IvCipherCbc[] = "8ce82eefbea0da3c44699ed7db51b7d9" -+ "c30e32ffedc0774e6aff6af0869f71aa" -+ "0f3af07a9a31a9c684db207eb0ef8e4e" -+ "35907aa632c3ffdf868bb7b29d3d46ad" -+ "83ce9f9a102ee99d49a53e87f4c3da55"; -+ -+char cesaAesCtrPlain[] = "00E0017B27777F3F4A1786F000000001" -+ "000102030405060708090A0B0C0D0E0F" -+ "101112131415161718191A1B1C1D1E1F" -+ "20212223"; -+ -+char cesaAesCtrCipher[] = "00E0017B27777F3F4A1786F000000001" -+ "C1CF48A89F2FFDD9CF4652E9EFDB72D7" -+ "4540A42BDE6D7836D59A5CEAAEF31053" -+ "25B2072F"; -+ -+ -+ -+/* Input cesaHmacHex3 is '0xdd' repeated 50 times */ -+char cesaHmacMd5digestHex3[] = "56be34521d144c88dbb8c733f0e8b3f6"; -+char cesaHmacSha1digestHex3[] = "125d7342b9ac11cd91a39af48aa17b4f63f175d3"; -+char cesaDataHexStr3[50*2+1] = ""; -+char cesaDataAndMd5digest3[sizeof(cesaDataHexStr3)+sizeof(cesaHmacMd5digestHex3)+8*2+1] = ""; -+char cesaDataAndSha1digest3[sizeof(cesaDataHexStr3)+sizeof(cesaHmacSha1digestHex3)+8*2+1] = ""; -+ -+/* Ascii string is "abc" */ -+char hashHexStr3[] = "616263"; -+char hashMd5digest3[] = "900150983cd24fb0d6963f7d28e17f72"; -+char hashSha1digest3[] = "a9993e364706816aba3e25717850c26c9cd0d89d"; -+ -+char hashHexStr80[] = "31323334353637383930" -+ "31323334353637383930" -+ "31323334353637383930" -+ "31323334353637383930" -+ "31323334353637383930" -+ "31323334353637383930" -+ "31323334353637383930" -+ "31323334353637383930"; -+ -+char hashMd5digest80[] = "57edf4a22be3c955ac49da2e2107b67a"; -+ -+char tripleDesThenMd5digest80[] = "b7726a03aad490bd6c5a452a89a1b271"; -+char tripleDesThenSha1digest80[] = "b2ddeaca91030eab5b95a234ef2c0f6e738ff883"; -+ -+char cbc3desThenMd5digest80[] = "6f463057e1a90e0e91ae505b527bcec0"; -+char cbc3desThenSha1digest80[] = "1b002ed050be743aa98860cf35659646bb8efcc0"; -+ -+char cbcAes128ThenMd5digest80[] = "6b6e863ac5a71d15e3e9b1c86c9ba05f"; -+char cbcAes128ThenSha1digest80[] = "13558472d1fc1c90dffec6e5136c7203452d509b"; -+ -+ -+static MV_CESA_TEST_CASE cesaTestCases[] = -+{ -+ /* plainHexStr cipherHexStr IV crypto mac digest */ -+ /* Length Length Offset */ -+ /*0*/ { NULL, NULL, NULL, 0, 0, -1 }, -+ /*1*/ { cesaPlainHexEbc, cesaCipherHexEcb, NULL, 24, 0, -1 }, -+ /*2*/ { cesaPlainHexCbc, cesaCipherHexCbc, NULL, 24, 0, -1 }, -+ /*3*/ { cesaAesPlainHexEcb, cesaAes128cipherHexEcb, NULL, 16, 0, -1 }, -+ /*4*/ { cesaAesPlainHexEcb, cesaAes192cipherHexEcb, NULL, 16, 0, -1 }, -+ /*5*/ { cesaAesPlainHexEcb, cesaAes256cipherHexEcb, NULL, 16, 0, -1 }, -+ /*6*/ { cesaDataHexStr1, cesaHmacMd5digestHex1, NULL, 0, 8, -1 }, -+ /*7*/ { NULL, cesaDataAndMd5digest1, NULL, 0, 8, -1 }, -+ /*8*/ { cesaDataHexStr3, cesaHmacMd5digestHex3, NULL, 0, 50, -1 }, -+ /*9*/ { NULL, cesaDataAndMd5digest3, NULL, 0, 50, -1 }, -+/*10*/ { cesaAesPlainText, cesaAes128IvCipherCbc, iv5, 64, 0, -1 }, -+/*11*/ { cesaDataHexStr1, cesaHmacSha1digestHex1, NULL, 0, 8, -1 }, -+/*12*/ { NULL, cesaDataAndSha1digest1, NULL, 0, 8, -1 }, -+/*13*/ { cesaDataHexStr3, cesaHmacSha1digestHex3, NULL, 0, 50, -1 }, -+/*14*/ { NULL, cesaDataAndSha1digest3, NULL, 0, 50, -1 }, -+/*15*/ { hashHexStr3, hashMd5digest3, NULL, 0, 3, -1 }, -+/*16*/ { hashHexStr3, hashSha1digest3, NULL, 0, 3, -1 }, -+/*17*/ { hashHexStr80, tripleDesThenMd5digest80, NULL, 80, 80, -1 }, -+/*18*/ { hashHexStr80, tripleDesThenSha1digest80, NULL, 80, 80, -1 }, -+/*19*/ { hashHexStr80, cbc3desThenMd5digest80, iv1, 80, 80, -1 }, -+/*20*/ { hashHexStr80, cbc3desThenSha1digest80, iv1, 80, 80, -1 }, -+/*21*/ { hashHexStr80, cbcAes128ThenMd5digest80, iv5, 80, 80, -1 }, -+/*22*/ { hashHexStr80, cbcAes128ThenSha1digest80, iv5, 80, 80, -1 }, -+/*23*/ { cesaAesCtrPlain, cesaAesCtrCipher, NULL, 36, 0, -1 }, -+/*24*/ { cesaAesIvPlainText, cesaAes128IvCipherCbc, NULL, 64, 0, -1 }, -+/*25*/ { plain3des1, cipher3des1, NULL, 0, 0, -1 }, -+/*26*/ { plain3des2, cipher3desCbc2, iv3des2,0, 0, -1 }, -+/*27*/ { plain3des3, cipher3desCbc3, iv3des3,0, 0, -1 }, -+}; -+ -+ -+/* Key = 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -+ * 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa -+ * Input 0xdd repeated "size" times -+ */ -+static MV_CESA_SIZE_TEST mdMultiSizeTest302[] = -+{ -+ { 80, "7a031a640c14a4872814930b1ef3a5b2" }, -+ { 512, "5488e6c5a14dc72a79f28312ca5b939b" }, -+ { 1000, "d00814f586a8b78a05724239d2531821" }, -+ { 1001, "bf07df7b7f49d3f5b5ecacd4e9e63281" }, -+ { 1002, "1ed4a1a802e87817a819d4e37bb4d0f7" }, -+ { 1003, "5972ab64a4f265ee371dac2f2f137f90" }, -+ { 1004, "71f95e7ec3aa7df2548e90898abdb28e" }, -+ { 1005, "e082790b4857fcfc266e92e59e608814" }, -+ { 1006, "9500f02fd8ac7fde8b10e4fece9a920d" }, -+ { 1336, "e42edcce57d0b75b01aa09d71427948b" }, -+ { 1344, "bb5454ada0deb49ba0a97ffd60f57071" }, -+ { 1399, "0f44d793e744b24d53f44f295082ee8c" }, -+ { 1400, "359de8a03a9b707928c6c60e0e8d79f1" }, -+ { 1401, "e913858b484cbe2b384099ea88d8855b" }, -+ { 1402, "d9848a164af53620e0540c1d7d87629e" }, -+ { 1403, "0c9ee1c2c9ef45e9b625c26cbaf3e822" }, -+ { 1404, "12edd4f609416e3c936170360561b064" }, -+ { 1405, "7fc912718a05446395345009132bf562" }, -+ { 1406, "882f17425e579ff0d85a91a59f308aa0" }, -+ { 1407, "005cae408630a2fb5db82ad9db7e59da" }, -+ { 1408, "64655f8b404b3fea7a3e3e609bc5088f" }, -+ { 1409, "4a145284a7f74e01b6bb1a0ec6a0dd80" }, -+ { 2048, "67caf64475650732def374ebb8bde3fd" }, -+ { 2049, "6c84f11f472825f7e6cd125c2981884b" }, -+ { 2050, "8999586754a73a99efbe4dbad2816d41" }, -+ { 2051, "ba6946b610e098d286bc81091659dfff" }, -+ { 2052, "d0afa01c92d4d13def2b024f36faed83" }, -+ { 3072, "61d8beac61806afa2585d74a9a0e6974" }, -+ { 3074, "f6501a28dcc24d1e4770505c51a87ed3" }, -+ { 3075, "ea4a6929be67e33e61ff475369248b73" }, -+ { 4048, "aa8c4d68f282a07e7385acdfa69f4bed" }, -+ { 4052, "afb5ed2c0e1d430ea59e59ed5ed6b18a" }, -+ { 4058, "9e8553f9bdd43aebe0bd729f0e600c99" }, -+ { 6144, "f628f3e5d183fe5cdd3a5abee39cf872" }, -+ { 6150, "89a3efcea9a2f25f919168ad4a1fd292" }, -+ { 6400, "cdd176b7fb747873efa4da5e32bdf88f" }, -+ { 6528, "b1d707b027354aca152c45ee559ccd3f" }, -+ { 8192, "c600ea4429ac47f9941f09182166e51a" }, -+ {16384, "16e8754bfbeb4c649218422792267a37" }, -+ {18432, "0fd0607521b0aa8b52219cfbe215f63e" }, -+ { 0, NULL }, -+}; -+ -+/* Key = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ */ -+static MV_CESA_SIZE_TEST mdMultiSizeTest304[] = -+{ -+ { 80, "a456c4723fee6068530af5a2afa71627" }, -+ { 512, "f85c2a2344f5de68b432208ad13e5794" }, -+ { 1000, "35464d6821fd4a293a41eb84e274c8c5" }, -+ { 1001, "c08eedbdce60cceb54bc2d732bb32c8b" }, -+ { 1002, "5664f71800c011cc311cb6943339c1b8" }, -+ { 1003, "779c723b044c585dc7802b13e8501bdc" }, -+ { 1004, "55e500766a2c307bc5c5fdd15e4cacd4" }, -+ { 1005, "d5f978954f5c38529d1679d2b714f068" }, -+ { 1006, "cd3efc827ce628b7281b72172693abf9" }, -+ { 1336, "6f04479910785878ae6335b8d1e87edf" }, -+ { 1344, "b6d27b50c2bce1ba2a8e1b5cc4324368" }, -+ { 1399, "65f70a1d4c86e5eaeb0704c8a7816795" }, -+ { 1400, "3394b5adc4cb3ff98843ca260a44a88a" }, -+ { 1401, "3a06f3582033a66a4e57e0603ce94e74" }, -+ { 1402, "e4d97f5ed51edc48abfa46eeb5c31752" }, -+ { 1403, "3d05e40b080ee3bedf293cb87b7140e7" }, -+ { 1404, "8cf294fc3cd153ab18dccb2a52cbf244" }, -+ { 1405, "d1487bd42f6edd9b4dab316631159221" }, -+ { 1406, "0527123b6bf6936cf5d369dc18c6c70f" }, -+ { 1407, "3224a06639db70212a0cd1ae1fcc570a" }, -+ { 1408, "a9e13335612c0356f5e2c27086e86c43" }, -+ { 1409, "a86d1f37d1ed8a3552e9a4f04dceea98" }, -+ { 2048, "396905c9b961cd0f6152abfb69c4449c" }, -+ { 2049, "49f39bff85d9dcf059fadb89efc4a70f" }, -+ { 2050, "3a2b4823bc4d0415656550226a63e34a" }, -+ { 2051, "dec60580d406c782540f398ad0bcc7e0" }, -+ { 2052, "32f76610a14310309eb748fe025081bf" }, -+ { 3072, "45edc1a42bf9d708a621076b63b774da" }, -+ { 3074, "9be1b333fe7c0c9f835fb369dc45f778" }, -+ { 3075, "8c06fcac7bd0e7b7a17fd6508c09a549" }, -+ { 4048, "0ddaef848184bf0ad98507a10f1e90e4" }, -+ { 4052, "81976bcaeb274223983996c137875cb8" }, -+ { 4058, "0b0a7a1c82bc7cbc64d8b7cd2dc2bb22" }, -+ { 6144, "1c24056f52725ede2dff0d7f9fc9855f" }, -+ { 6150, "b7f4b65681c4e43ee68ca466ca9ca4ec" }, -+ { 6400, "443bbaab9f7331ddd4bf11b659cd43c8" }, -+ { 6528, "216f44f23047cfee03a7a64f88f9a995" }, -+ { 8192, "ac7a993b2cad54879dba1bde63e39097" }, -+ { 8320, "55ed7be9682d6c0025b3221a62088d08" }, -+ {16384, "c6c722087653b62007aea668277175e5" }, -+ {18432, "f1faca8e907872c809e14ffbd85792d6" }, -+ { 0, NULL }, -+}; -+ -+/* HASH-MD5 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ * repeated "size" times -+ */ -+static MV_CESA_SIZE_TEST mdMultiSizeTest305[] = -+{ -+ { 80, "57edf4a22be3c955ac49da2e2107b67a" }, -+ { 512, "c729ae8f0736cc377a9767a660eaa04e" }, -+ { 1000, "f1257a8659eb92d36fe14c6bf3852a6a" }, -+ { 1001, "f8a46fe8ea04fdc8c7de0e84042d3878" }, -+ { 1002, "da188dd67bff87d58aa3c02af2d0cc0f" }, -+ { 1003, "961753017feee04c9b93a8e51658a829" }, -+ { 1004, "dd68c4338608dcc87807a711636bf2af" }, -+ { 1005, "e338d567d3ce66bf69ada29658a8759b" }, -+ { 1006, "443c9811e8b92599b0b149e8d7ec700a" }, -+ { 1336, "89a98511706008ba4cbd0b4a24fa5646" }, -+ { 1344, "335a919805f370b9e402a62c6fe01739" }, -+ { 1399, "5d18d0eddcd84212fe28d812b5e80e3b" }, -+ { 1400, "6b695c240d2dffd0dffc99459ca76db6" }, -+ { 1401, "49590f61298a76719bc93a57a30136f5" }, -+ { 1402, "94c2999fa3ef1910a683d69b2b8476f2" }, -+ { 1403, "37073a02ab00ecba2645c57c228860db" }, -+ { 1404, "1bcd06994fce28b624f0c5fdc2dcdd2b" }, -+ { 1405, "11b93671a64c95079e8cf9e7cddc8b3d" }, -+ { 1406, "4b6695772a4c66313fa4871017d05f36" }, -+ { 1407, "d1539b97fbfda1c075624e958de19c5b" }, -+ { 1408, "b801b9b69920907cd018e8063092ede9" }, -+ { 1409, "b765f1406cfe78e238273ed01bbcaf7e" }, -+ { 2048, "1d7e2c64ac29e2b3fb4c272844ed31f5" }, -+ { 2049, "71d38fac49c6b1f4478d8d88447bcdd0" }, -+ { 2050, "141c34a5592b1bebfa731e0b23d0cdba" }, -+ { 2051, "c5e1853f21c59f5d6039bd13d4b380d8" }, -+ { 2052, "dd44a0d128b63d4b5cccd967906472d7" }, -+ { 3072, "37d158e33b21390822739d13db7b87fe" }, -+ { 3074, "aef3b209d01d39d0597fe03634bbf441" }, -+ { 3075, "335ffb428eabf210bada96d74d5a4012" }, -+ { 4048, "2434c2b43d798d2819487a886261fc64" }, -+ { 4052, "ac2fa84a8a33065b2e92e36432e861f8" }, -+ { 4058, "856781f85616c341c3533d090c1e1e84" }, -+ { 6144, "e5d134c652c18bf19833e115f7a82e9b" }, -+ { 6150, "a09a353be7795fac2401dac5601872e6" }, -+ { 6400, "08b9033ac6a1821398f50af75a2dbc83" }, -+ { 6528, "3d47aa193a8540c091e7e02f779e6751" }, -+ { 8192, "d3164e710c0626f6f395b38f20141cb7" }, -+ { 8320, "b727589d9183ff4e8491dd24466974a3" }, -+ {16384, "3f54d970793d2274d5b20d10a69938ac" }, -+ {18432, "f558511dcf81985b7a1bb57fad970531" }, -+ { 0, NULL }, -+}; -+ -+ -+/* Key = 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -+ * 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa -+ * 0xaa, 0xaa, 0xaa, 0xaa -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ */ -+static MV_CESA_SIZE_TEST shaMultiSizeTest402[] = -+{ -+ { 80, "e812f370e659705a1649940d1f78cd7af18affd3" }, -+ { 512, "e547f886b2c15d995ed76a8a924cb408c8080f66" }, -+ { 1000, "239443194409f1a5342ecde1a092c8f3a3ed790a" }, -+ { 1001, "f278ab9a102850a9f48dc4e9e6822afe2d0c52b5" }, -+ { 1002, "8bcc667df5ab6ece988b3af361d09747c77f4e72" }, -+ { 1003, "0fae6046c7dc1d3e356b25af836f6077a363f338" }, -+ { 1004, "0ea48401cc92ae6bc92ae76685269cb0167fbe1a" }, -+ { 1005, "ecbcd7c879b295bafcd8766cbeac58cc371e31d1" }, -+ { 1006, "eb4a4a3d07d1e9a15e6f1ab8a9c47f243e27324c" }, -+ { 1336, "f5950ee1d77c10e9011d2149699c9366fe52529c" }, -+ { 1344, "b04263604a63c351b0b3b9cf1785b4bdba6c8838" }, -+ { 1399, "8cb1cff61d5b784045974a2fc69386e3b8d24218" }, -+ { 1400, "9bb2f3fcbeddb2b90f0be797cd647334a2816d51" }, -+ { 1401, "23ae462a7a0cb440f7445791079a5d75a535dd33" }, -+ { 1402, "832974b524a4d3f9cc2f45a3cabf5ccef65cd2aa" }, -+ { 1403, "d1c683742fe404c3c20d5704a5430e7832a7ec95" }, -+ { 1404, "867c79042e64f310628e219d8b85594cd0c7adc3" }, -+ { 1405, "c9d81d49d13d94358f56ccfd61af02b36c69f7c3" }, -+ { 1406, "0df43daab2786172f9b8d07d61f14a070cf1287a" }, -+ { 1407, "0fd8f3ad7f169534b274d4c66bbddd89f759e391" }, -+ { 1408, "3987511182b18473a564436003139b808fa46343" }, -+ { 1409, "ef667e063c9e9f539a8987a8d0bd3066ee85d901" }, -+ { 2048, "921109c99f3fedaca21727156d5f2b4460175327" }, -+ { 2049, "47188600dd165eb45f27c27196d3c46f4f042c1b" }, -+ { 2050, "8831939904009338de10e7fa670847041387807d" }, -+ { 2051, "2f8ebb5db2997d614e767be1050366f3641e7520" }, -+ { 2052, "669e51cd730dae158d3bef8adba075bd95a0d011" }, -+ { 3072, "cfee66cfd83abc8451af3c96c6b35a41cc6c55f5" }, -+ { 3074, "216ea26f02976a261b7d21a4dd3085157bedfabd" }, -+ { 3075, "bd612ebba021fd8e012b14c3bd60c8c5161fabc0" }, -+ { 4048, "c2564c1fdf2d5e9d7dde7aace2643428e90662e8" }, -+ { 4052, "91ce61fe924b445dfe7b5a1dcd10a27caec16df6" }, -+ { 4058, "db2a9be5ee8124f091c7ebd699266c5de223c164" }, -+ { 6144, "855109903feae2ba3a7a05a326b8a171116eb368" }, -+ { 6150, "37520bb3a668294d9c7b073e7e3daf8fee248a78" }, -+ { 6400, "60a353c841b6d2b1a05890349dad2fa33c7536b7" }, -+ { 6528, "9e53a43a69bb42d7c8522ca8bd632e421d5edb36" }, -+ { 8192, "a918cb0da862eaea0a33ee0efea50243e6b4927c" }, -+ { 8320, "29a5dcf55d1db29cd113fcf0572ae414f1c71329" }, -+ {16384, "6fb27966138e0c8d5a0d65ace817ebd53633cee1" }, -+ {18432, "ca09900d891c7c9ae2a559b10f63a217003341c1" }, -+ { 0, NULL }, -+}; -+ -+/* Key = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 -+ * 0x11, 0x12, 0x13, 0x14 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ */ -+static MV_CESA_SIZE_TEST shaMultiSizeTest404[] = -+{ -+ { 80, "beaf20a34b06a87558d156c0949bc3957d40222e" }, -+ { 512, "3353955358d886bc2940a3c7f337ff7dafb59c7b" }, -+ { 1000, "8737a542c5e9b2b6244b757ebb69d5bd602a829f" }, -+ { 1001, "fd9e7582d8a5d3c9fe3b923e4e6a41b07a1eb4d4" }, -+ { 1002, "a146d14a6fc3c274ff600568f4d75b977989e00d" }, -+ { 1003, "be22601bbc027ddef2dec97d30b3dc424fd803c5" }, -+ { 1004, "3e71fe99b2fe2b7bfdf4dbf0c7f3da25d7ea35e7" }, -+ { 1005, "2c422735d7295408fddd76f5e8a83a2a8da13df3" }, -+ { 1006, "6d875319049314b61855101a647b9ba3313428e6" }, -+ { 1336, "c1631ea80bad9dc43a180712461b65a0598c711c" }, -+ { 1344, "816069bf91d34581005746e2e0283d0f9c7b7605" }, -+ { 1399, "4e139866dc61cfcb8b67ca2ebd637b3a538593af" }, -+ { 1400, "ff2a0f8dd2b02c5417910f6f55d33a78e081a723" }, -+ { 1401, "ab00c12be62336964cbce31ae97fe2a0002984d5" }, -+ { 1402, "61349e7f999f3a1acc56c3e9a5060a9c4a7b05b6" }, -+ { 1403, "3edbc0f61e435bc1317fa27d840076093fb79353" }, -+ { 1404, "d052c6dfdbe63d45dab23ef9893e2aa4636aca1e" }, -+ { 1405, "0cc16b7388d67bf0add15a31e6e6c753cfae4987" }, -+ { 1406, "c96ba7eaad74253c38c22101b558d2850b1d1b90" }, -+ { 1407, "3445428a40d2c6556e7c55797ad8d323b61a48d9" }, -+ { 1408, "8d6444f937a09317c89834187b8ea9b8d3a8c56b" }, -+ { 1409, "c700acd3ecd19014ea2bdb4d42510c467e088475" }, -+ { 2048, "ee27d2a0cb77470c2f496212dfd68b5bb7b04e4b" }, -+ { 2049, "683762d7a02983b26a6d046e6451d9cd82c25932" }, -+ { 2050, "0fd20f1d55a9ee18363c2a6fd54aa13aee69992f" }, -+ { 2051, "86c267d8cc4bc8d59090e4f8b303da960fd228b7" }, -+ { 2052, "452395ae05b3ec503eea34f86fc0832485ad97c1" }, -+ { 3072, "75198e3cfd0b9bcff2dabdf8e38e6fdaa33ca49a" }, -+ { 3074, "4e24785ef080141ce4aab4675986d9acea624d7c" }, -+ { 3075, "3a20c5978dd637ec0e809bf84f0d9ccf30bc65bf" }, -+ { 4048, "3c32da256be7a7554922bf5fed51b0d2d09e59ad" }, -+ { 4052, "fff898426ea16e54325ae391a32c6c9bce4c23c0" }, -+ { 4058, "c800b9e562e1c91e1310116341a3c91d37f848ec" }, -+ { 6144, "d91d509d0cc4376c2d05bf9a5097717a373530e6" }, -+ { 6150, "d957030e0f13c5df07d9eec298542d8f94a07f12" }, -+ { 6400, "bb745313c3d7dc17b3f955e5534ad500a1082613" }, -+ { 6528, "77905f80d9ca82080bbb3e5654896dabfcfd1bdb" }, -+ { 8192, "5237fd9a81830c974396f99f32047586612ff3c0" }, -+ { 8320, "57668e28d5f2dba0839518a11db0f6af3d7e08bf" }, -+ {16384, "62e093fde467f0748087beea32e9af97d5c61241" }, -+ {18432, "845fb33130c7d6ea554fd5aacb9c50cf7ccb5929" }, -+ { 0, NULL }, -+}; -+ -+/* HASH-SHA1 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ * repeated "size" times -+ */ -+static MV_CESA_SIZE_TEST shaMultiSizeTest405[] = -+{ -+ { 80, "50abf5706a150990a08b2c5ea40fa0e585554732" }, -+ { 512, "f14516a08948fa27917a974d219741a697ba0087" }, -+ { 1000, "0bd18c378d5788817eb4f1e5dc07d867efa5cbf4" }, -+ { 1001, "ca29b85c35db1b8aef83c977893a11159d1b7aa2" }, -+ { 1002, "d83bc973eaaedb8a31437994dabbb3304b0be086" }, -+ { 1003, "2cf7bbef0acd6c00536b5c58ca470df9a3a90b6c" }, -+ { 1004, "e4375d09b1223385a8a393066f8209acfd936a80" }, -+ { 1005, "1029b38043e027745d019ce1d2d68e3d8b9d8f99" }, -+ { 1006, "deea16dcebbd8ac137e2b984deb639b9fb5e9680" }, -+ { 1336, "ea031b065fff63dcfb6a41956e4777520cdbc55d" }, -+ { 1344, "b52096c6445e6c0a8355995c70dc36ae186c863c" }, -+ { 1399, "cde2f6f8379870db4b32cf17471dc828a8dbff2b" }, -+ { 1400, "e53ff664064bc09fe5054c650806bd42d8179518" }, -+ { 1401, "d1156db5ddafcace64cdb510ff0d4af9b9a8ad64" }, -+ { 1402, "34ede0e9a909dd84a2ae291539105c0507b958e1" }, -+ { 1403, "a772ca3536da77e6ad3251e4f9e1234a4d7b87c0" }, -+ { 1404, "29740fd2b04e7a8bfd32242db6233156ad699948" }, -+ { 1405, "65b17397495b70ce4865dad93bf991b74c97cce1" }, -+ { 1406, "a7ee89cd0754061fdb91af7ea6abad2c69d542e3" }, -+ { 1407, "3eebf82f7420188e23d328b7ce93580b279a5715" }, -+ { 1408, "e08d3363a8b9a490dfb3a4c453452b8f114deeec" }, -+ { 1409, "95d74df739181a4ff30b8c39e28793a36598e924" }, -+ { 2048, "aa40262509c2abf84aab0197f83187fc90056d91" }, -+ { 2049, "7dec28ef105bc313bade8d9a7cdeac58b99de5ea" }, -+ { 2050, "d2e30f77ec81197de20f56588a156094ecb88450" }, -+ { 2051, "6b22ccc874833e96551a39da0c0edcaa0d969d92" }, -+ { 2052, "f843141e57875cd669af58744bc60aa9ea59549c" }, -+ { 3072, "09c5fedeaa62c132e673cc3c608a00142273d086" }, -+ { 3074, "b09e95eea9c7b1b007a58accec488301901a7f3d" }, -+ { 3075, "e6226b77b4ada287a8c9bbcf4ed71eec5ce632dc" }, -+ { 4048, "e99394894f855821951ddddf5bfc628547435f5c" }, -+ { 4052, "32d2f1af38be9cfba6cd03d55a254d0b3e1eb382" }, -+ { 4058, "d906552a4f2aca3a22e1fecccbcd183d7289d0ef" }, -+ { 6144, "2e7f62d35a860988e1224dc0543204af19316041" }, -+ { 6150, "d6b89698ee133df46fec9d552fadc328aa5a1b51" }, -+ { 6400, "dff50e90c46853988fa3a4b4ce5dda6945aae976" }, -+ { 6528, "9e63ec0430b96db02d38bc78357a2f63de2ab7f8" }, -+ { 8192, "971eb71ed60394d5ab5abb12e88420bdd41b5992" }, -+ { 8320, "91606a31b46afeaac965cecf87297e791b211013" }, -+ {16384, "547f830a5ec1f5f170ce818f156b1002cabc7569" }, -+ {18432, "f16f272787f3b8d539652e4dc315af6ab4fda0ef" }, -+ { 0, NULL }, -+}; -+ -+/* CryptoKey = 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef; -+ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ * Note: only sizes aligned to 3DES block size (8 bytes) allowed -+ */ -+static MV_CESA_SIZE_TEST tripleDesMdMultiSizeTest502[] = -+{ -+ { 64, "9586962a2aaaef28803dec2e17807a7f" }, -+ { 80, "b7726a03aad490bd6c5a452a89a1b271" }, -+ { 352, "f1ed9563aecc3c0d2766eb2bed3b4e4c" }, -+ { 512, "0f9decb11ab40fe86f4d4d9397bc020e" }, -+ { 1000, "3ba69deac12cab8ff9dff7dbd9669927" }, -+ { 1336, "6cf47bf1e80e03e2c1d0945bc50d37d2" }, -+ { 1344, "4be388dab21ceb3fa1b8d302e9b821f7" }, -+ { 1400, "a58b79fb21dd9bfc6ec93e3b99fb0ef1" }, -+ { 1408, "8bc97379fc2ac3237effcdd4f7a86528" }, -+ { 2048, "1339f03ab3076f25a20bc4cba16eb5bf" }, -+ { 3072, "731204d2d90c4b36ae41f5e1fb874288" }, -+ { 4048, "c028d998cfda5642547b7e1ed5ea16e4" }, -+ { 6144, "b1b19cd910cc51bd22992f1e59f1e068" }, -+ { 6400, "44e4613496ba622deb0e7cb768135a2f" }, -+ { 6528, "3b06b0a86f8db9cd67f9448dfcf10549" }, -+ { 8192, "d581780b7163138a0f412be681457d82" }, -+ {16384, "03b8ac05527faaf1bed03df149c65ccf" }, -+ {18432, "677c8a86a41dab6c5d81b85b8fb10ff6" }, -+ { 0, NULL }, -+}; -+ -+ -+/* CryptoKey = 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef; -+ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 -+ * 0x11, 0x12, 0x13, 0x14 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ * Note: only sizes aligned to 3DES block size (8 bytes) allowed -+ */ -+static MV_CESA_SIZE_TEST tripleDesShaMultiSizeTest503[] = -+{ -+ { 64, "44a1e9bcbfc1429630d9ea68b7a48b0427a684f2" }, -+ { 80, "b2ddeaca91030eab5b95a234ef2c0f6e738ff883" }, -+ { 352, "4b91864c7ff629bdff75d9726421f76705452aaf" }, -+ { 512, "6dd37faceeb2aa98ba74f4242ed6734a4d546af5" }, -+ { 1000, "463661c30300be512a9df40904f0757cde5f1141" }, -+ { 1336, "b931f831d9034fe59c65176400b039fe9c1f44a5" }, -+ { 1344, "af8866b1cd4a4887d6185bfe72470ffdfb3648e1" }, -+ { 1400, "49c6caf07296d5e31d2504d088bc5b20c3ee7cdb" }, -+ { 1408, "fcae8deedbc6ebf0763575dc7e9de075b448a0f4" }, -+ { 2048, "edece5012146c1faa0dd10f50b183ba5d2af58ac" }, -+ { 3072, "5b83625adb43a488b8d64fecf39bb766818547b7" }, -+ { 4048, "d2c533678d26c970293af60f14c8279dc708bfc9" }, -+ { 6144, "b8f67af4f991b08b725f969b049ebf813bfacc5c" }, -+ { 6400, "d9a6c7f746ac7a60ef2edbed2841cf851c25cfb0" }, -+ { 6528, "376792b8c8d18161d15579fb7829e6e3a27e9946" }, -+ { 8192, "d890eabdca195b34ef8724b28360cffa92ae5655" }, -+ {16384, "a167ee52639ec7bf19aee9c6e8f76667c14134b9" }, -+ {18432, "e4396ab56f67296b220985a12078f4a0e365d2cc" }, -+ { 0, NULL }, -+}; -+ -+/* CryptoKey = 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef -+ * IV = 0x12345678, 0x90abcdef -+ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ * Note: only sizes aligned to 3DES block size (8 bytes) allowed -+ */ -+static MV_CESA_SIZE_TEST cbc3desMdMultiSizeTest504[] = -+{ -+ { 64, "8d10e00802460ede0058c139ba48bd2d" }, -+ { 80, "6f463057e1a90e0e91ae505b527bcec0" }, -+ { 352, "4938d48bdf86aece2c6851e7c6079788" }, -+ { 512, "516705d59f3cf810ebf2a13a23a7d42e" }, -+ { 1000, "a5a000ee5c830e67ddc6a2d2e5644b31" }, -+ { 1336, "44af60087b74ed07950088efbe3b126a" }, -+ { 1344, "1f5b39e0577920af731dabbfcf6dfc2a" }, -+ { 1400, "6804ea640e29b9cd39e08bc37dbce734" }, -+ { 1408, "4fb436624b02516fc9d1535466574bf9" }, -+ { 2048, "c909b0985c423d8d86719f701e9e83db" }, -+ { 3072, "cfe0bc34ef97213ee3d3f8b10122db21" }, -+ { 4048, "03ea10b5ae4ddeb20aed6af373082ed1" }, -+ { 6144, "b9a0ff4f87fc14b3c2dc6f0ed0998fdf" }, -+ { 6400, "6995f85d9d4985dd99e974ec7dda9dd6" }, -+ { 6528, "bbbb548ce2fa3d58467f6a6a5168a0e6" }, -+ { 8192, "afe101fbe745bb449ae4f50d10801456" }, -+ {16384, "9741706d0b1c923340c4660ff97cacdf" }, -+ {18432, "b0217becb73cb8f61fd79c7ce9d023fb" }, -+ { 0, NULL }, -+}; -+ -+ -+/* CryptoKey = 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef; -+ * IV = 0x12345678, 0x90abcdef -+ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 -+ * 0x11, 0x12, 0x13, 0x14 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ * Note: only sizes aligned to 3DES block size (8 bytes) allowed -+ */ -+static MV_CESA_SIZE_TEST cbc3desShaMultiSizeTest505[] = -+{ -+ { 64, "409187e5bdb0be4a7754ca3747f7433dc4f01b98" }, -+ { 80, "1b002ed050be743aa98860cf35659646bb8efcc0" }, -+ { 352, "6cbf7ebe50fa4fa6eecc19eca23f9eae553ccfff" }, -+ { 512, "cfb5253fb4bf72b743320c30c7e48c54965853b0" }, -+ { 1000, "95e04e1ca2937e7c5a9aba9e42d2bcdb8a7af21f" }, -+ { 1336, "3b5c1f5eee5837ebf67b83ae01405542d77a6627" }, -+ { 1344, "2b3d42ab25615437f98a1ee310b81d07a02badc2" }, -+ { 1400, "7f8687df7c1af44e4baf3c934b6cca5ab6bc993e" }, -+ { 1408, "473a581c5f04f7527d50793c845471ac87e86430" }, -+ { 2048, "e41d20cae7ebe34e6e828ed62b1e5734019037bb" }, -+ { 3072, "275664afd7a561d804e6b0d204e53939cde653ae" }, -+ { 4048, "0d220cc5b34aeeb46bbbd637dde6290b5a8285a3" }, -+ { 6144, "cb393ddcc8b1c206060625b7d822ef9839e67bc5" }, -+ { 6400, "dd3317e2a627fc04800f74a4b05bfda00fab0347" }, -+ { 6528, "8a74c3b2441ab3f5a7e08895cc432566219a7c41" }, -+ { 8192, "b8e6ef3a549ed0e005bd5b8b1a5fe6689e9711a7" }, -+ {16384, "55f59404008276cdac0e2ba0d193af2d40eac5ce" }, -+ {18432, "86ae6c4fc72369a54cce39938e2d0296cd9c6ec5" }, -+ { 0, NULL }, -+}; -+ -+ -+/* CryptoKey = 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef -+ * IV = 0x12345678, 0x90abcdef -+ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ * Note: only sizes aligned to AES block size (16 bytes) allowed -+ */ -+static MV_CESA_SIZE_TEST cbcAes128md5multiSizeTest506[] = -+{ -+ { 16, "7ca4c2ba866751598720c5c4aa0d6786" }, -+ { 64, "7dba7fb988e80da609b1fea7254bced8" }, -+ { 80, "6b6e863ac5a71d15e3e9b1c86c9ba05f" }, -+ { 352, "a1ceb9c2e3021002400d525187a9f38c" }, -+ { 512, "596c055c1c55db748379223164075641" }, -+ { 1008, "f920989c02f3b3603f53c99d89492377" }, -+ { 1344, "2e496b73759d77ed32ea222dbd2e7b41" }, -+ { 1408, "7178c046b3a8d772efdb6a71c4991ea4" }, -+ { 2048, "a917f0099c69eb94079a8421714b6aad" }, -+ { 3072, "693cd5033d7f5391d3c958519fa9e934" }, -+ { 4048, "139dca91bcff65b3c40771749052906b" }, -+ { 6144, "428d9cef6df4fb70a6e9b6bbe4819e55" }, -+ { 6400, "9c0b909e76daa811e12b1fc17000a0c4" }, -+ { 6528, "ad876f6297186a7be1f1b907ed860eda" }, -+ { 8192, "479cbbaca37dd3191ea1f3e8134a0ef4" }, -+ {16384, "60fda559c74f91df538100c9842f2f15" }, -+ {18432, "4a3eb1cba1fa45f3981270953f720c42" }, -+ { 0, NULL }, -+}; -+ -+ -+/* CryptoKey = 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef; -+ * IV = 0x12345678, 0x90abcdef -+ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 -+ * 0x11, 0x12, 0x13, 0x14 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ * Note: only sizes aligned to AES block size (16 bytes) allowed -+ */ -+static MV_CESA_SIZE_TEST cbcAes128sha1multiSizeTest507[] = -+{ -+ { 16, "9aa8dc1c45f0946daf78057fa978759c625c1fee" }, -+ { 64, "9f588fc1ede851e5f8b20256abc9979465ae2189" }, -+ { 80, "13558472d1fc1c90dffec6e5136c7203452d509b" }, -+ { 352, "6b93518e006cfaa1f7adb24615e7291fb0a27e06" }, -+ { 512, "096874951a77fbbf333e49d80c096ee2016e09bd" }, -+ { 1008, "696fc203c2e4b5ae0ec5d1db3f623c490bc6dbac" }, -+ { 1344, "79bf77509935ccd3528caaac6a5eb6481f74029b" }, -+ { 1408, "627f9462b95fc188e8cfa7eec15119bdc5d4fcf1" }, -+ { 2048, "3d50d0c005feba92fe41502d609fced9c882b4d1" }, -+ { 3072, "758807e5b983e3a91c06fb218fe0f73f77111e94" }, -+ { 4048, "ca90e85242e33f005da3504416a52098d0d31fb2" }, -+ { 6144, "8044c1d4fd06642dfc46990b4f18b61ef1e972cf" }, -+ { 6400, "166f1f4ea57409f04feba9fb1e39af0e00bd6f43" }, -+ { 6528, "0389016a39485d6e330f8b4215ddf718b404f7e9" }, -+ { 8192, "6df7ee2a8b61d6f7f860ce8dbf778f0c2a5b508b" }, -+ {16384, "a70a6d8dfa1f91ded621c3dbaed34162bc48783f" }, -+ {18432, "8dfad627922ce15df1eed10bdbed49244efa57db" }, -+ { 0, NULL }, -+}; -+ -+ -+void cesaTestPrintStatus(void); -+ -+ -+/*------------------------- LOCAL FUNCTIONs ---------------------------------*/ -+MV_STATUS testCmd(int sid, int iter, MV_CESA_COMMAND* pCmd, -+ MV_CESA_TEST_SESSION* pTestSession, MV_U8* pIV, int ivSize); -+MV_STATUS testClose(int idx); -+MV_STATUS testOpen(int idx); -+void close_session(int sid); -+void cesaTestCheckReady(const MV_CESA_RESULT *r); -+void cesaCheckReady(MV_CESA_RESULT* r); -+void printTestResults(int idx, MV_STATUS status, int checkMode); -+void cesaLastResult(void); -+void cesaTestPrintReq(int req, int offset, int size); -+ -+void cesaTestPrintStatus(void); -+void cesaTestPrintSession(int idx); -+void sizeTest(int testIdx, int iter, int checkMode); -+void multiTest(int iter, int reqSize, int checkMode); -+void oneTest(int testIdx, int caseIdx,int iter, int reqSize, int checkMode); -+void multiSizeTest(int idx, int iter, int checkMode, char* inputData); -+void cesaTest(int iter, int reqSize, int checkMode); -+void cesaOneTest(int testIdx, int caseIdx,int iter, int reqSize, int checkMode); -+void combiTest(int iter, int reqSize, int checkMode); -+void shaTest(int iter, int reqSize, int checkMode); -+void mdTest(int iter, int reqSize, int checkMode); -+void aesTest(int iter, int reqSize, int checkMode); -+void tripleDesTest(int iter, int reqSize, int checkMode); -+void desTest(int iter, int reqSize, int checkMode); -+void cesaTestStop(void); -+MV_STATUS testRun(int idx, int caseIdx, int iter,int reqSize, int checkMode); -+void cesaTestStart(int bufNum, int bufSize); -+ -+ -+static MV_U32 getRate(MV_U32* remainder) -+{ -+ MV_U32 kBits, milliSec, rate; -+ -+ milliSec = 0; -+ if( (cesaEndTicks - cesaBeginTicks) > 0) -+ { -+ milliSec = CESA_TEST_TICK_TO_MS(cesaEndTicks - cesaBeginTicks); -+ } -+ if(milliSec == 0) -+ { -+ if(remainder != NULL) -+ *remainder = 0; -+ return 0; -+ } -+ -+ kBits = (cesaIteration*cesaRateSize*8)/1000; -+ rate = kBits/milliSec; -+ if(remainder != NULL) -+ *remainder = ((kBits % milliSec)*10)/milliSec; -+ -+ return rate; -+} -+ -+static char* extractMbuf(MV_CESA_MBUF *pMbuf, -+ int offset, int size, char* hexStr) -+{ -+ mvCesaCopyFromMbuf((MV_U8*)cesaBinBuffer, pMbuf, offset, size); -+ mvBinToHex((const MV_U8*)cesaBinBuffer, hexStr, size); -+ -+ return hexStr; -+} -+ -+static MV_BOOL cesaCheckMbuf(MV_CESA_MBUF *pMbuf, -+ const char* hexString, int offset, -+ int checkSize) -+{ -+ MV_BOOL isFailed = MV_FALSE; -+ MV_STATUS status; -+ int size = strlen(hexString)/2; -+ int checkedSize = 0; -+/* -+ mvOsPrintf("cesaCheckMbuf: pMbuf=%p, offset=%d, checkSize=%d, mBufSize=%d\n", -+ pMbuf, offset, checkSize, pMbuf->mbufSize); -+*/ -+ if(pMbuf->mbufSize < (checkSize + offset)) -+ { -+ mvOsPrintf("checkSize (%d) is too large: offset=%d, mbufSize=%d\n", -+ checkSize, offset, pMbuf->mbufSize); -+ return MV_TRUE; -+ } -+ status = mvCesaCopyFromMbuf((MV_U8*)cesaBinBuffer, pMbuf, offset, checkSize); -+ if(status != MV_OK) -+ { -+ mvOsPrintf("CesaTest: Can't copy %d bytes from Mbuf=%p to checkBuf=%p\n", -+ checkSize, pMbuf, cesaBinBuffer); -+ return MV_TRUE; -+ } -+/* -+ mvDebugMemDump(cesaBinBuffer, size, 1); -+*/ -+ mvHexToBin(hexString, (MV_U8*)cesaExpBinBuffer, size); -+ -+ /* Compare buffers */ -+ while(checkSize > checkedSize) -+ { -+ size = MV_MIN(size, (checkSize - checkedSize)); -+ if(memcmp(cesaExpBinBuffer, &cesaBinBuffer[checkedSize], size) != 0) -+ { -+ mvOsPrintf("CheckMbuf failed: checkSize=%d, size=%d, checkedSize=%d\n", -+ checkSize, size, checkedSize); -+ mvDebugMemDump(&cesaBinBuffer[checkedSize], size, 1); -+ mvDebugMemDump(cesaExpBinBuffer, size, 1); -+ -+ isFailed = MV_TRUE; -+ break; -+ } -+ checkedSize += size; -+ } -+ -+ return isFailed; -+} -+ -+static MV_STATUS cesaSetMbuf(MV_CESA_MBUF *pMbuf, -+ const char* hexString, -+ int offset, int reqSize) -+{ -+ MV_STATUS status = MV_OK; -+ int copySize, size = strlen(hexString)/2; -+ -+ mvHexToBin(hexString, (MV_U8*)cesaBinBuffer, size); -+ -+ copySize = 0; -+ while(reqSize > copySize) -+ { -+ size = MV_MIN(size, (reqSize - copySize)); -+ -+ status = mvCesaCopyToMbuf((MV_U8*)cesaBinBuffer, pMbuf, offset+copySize, size); -+ if(status != MV_OK) -+ { -+ mvOsPrintf("cesaSetMbuf Error: Copy %d of %d bytes to MBuf\n", -+ copySize, reqSize); -+ break; -+ } -+ copySize += size; -+ } -+ pMbuf->mbufSize = offset+copySize; -+ return status; -+} -+ -+static MV_CESA_TEST_SESSION* getTestSessionDb(int idx, int* pTestIdx) -+{ -+ int testIdx, dbIdx = idx/100; -+ -+ if(dbIdx > MAX_TEST_TYPE) -+ { -+ mvOsPrintf("Wrong index %d - No such test type\n", idx); -+ return NULL; -+ } -+ testIdx = idx % 100; -+ -+ if(testIdx >= cesaTestsDB[dbIdx].numSessions) -+ { -+ mvOsPrintf("Wrong index %d - No such test\n", idx); -+ return NULL; -+ } -+ if(pTestIdx != NULL) -+ *pTestIdx = testIdx; -+ -+ return cesaTestsDB[dbIdx].pSessions; -+} -+ -+/* Debug */ -+void cesaTestPrintReq(int req, int offset, int size) -+{ -+ MV_CESA_MBUF* pMbuf; -+ -+ mvOsPrintf("cesaTestPrintReq: req=%d, offset=%d, size=%d\n", -+ req, offset, size); -+ mvDebugMemDump(cesaCmdRing, 128, 4); -+ -+ pMbuf = cesaCmdRing[req].pSrc; -+ mvCesaDebugMbuf("src", pMbuf, offset,size); -+ pMbuf = cesaCmdRing[req].pDst; -+ mvCesaDebugMbuf("dst", pMbuf, offset, size); -+ -+ cesaTestPrintStatus(); -+} -+ -+void cesaLastResult(void) -+{ -+ mvOsPrintf("Last Result: ReqId = %d, SessionId = %d, rc = (%d)\n", -+ (MV_U32)cesaResult.pReqPrv, cesaResult.sessionId, -+ cesaResult.retCode); -+} -+ -+void printTestResults(int idx, MV_STATUS status, int checkMode) -+{ -+ int testIdx; -+ MV_CESA_TEST_SESSION* pTestSessions = getTestSessionDb(idx, &testIdx); -+ -+ if(pTestSessions == NULL) -+ return; -+ -+ mvOsPrintf("%-35s %4dx%-4d : ", pTestSessions[testIdx].name, -+ cesaIteration, cesaReqSize); -+ if( (status == MV_OK) && -+ (cesaCryptoError == 0) && -+ (cesaError == 0) && -+ (cesaReqIdError == 0) ) -+ { -+ mvOsPrintf("Passed, Rate=%3u.%u Mbps (%5u cpp)\n", -+ cesaRate, cesaRateAfterDot, cesaEndTicks - cesaBeginTicks); -+ } -+ else -+ { -+ mvOsPrintf("Failed, Status = 0x%x\n", status); -+ if(cesaCryptoError > 0) -+ mvOsPrintf("cryptoError : %d\n", cesaCryptoError); -+ if(cesaReqIdError > 0) -+ mvOsPrintf("reqIdError : %d\n", cesaReqIdError); -+ if(cesaError > 0) -+ mvOsPrintf("cesaError : %d\n", cesaError); -+ } -+ if(cesaTestIsrMissCount > 0) -+ mvOsPrintf("cesaIsrMissed : %d\n", cesaTestIsrMissCount); -+} -+ -+void cesaCheckReady(MV_CESA_RESULT* r) -+{ -+ int reqId; -+ MV_CESA_MBUF *pMbuf; -+ MV_BOOL isFailed; -+ -+ cesaResult = *r; -+ reqId = (int)cesaResult.pReqPrv; -+ pMbuf = cesaCmdRing[reqId].pDst; -+ -+/* -+ mvOsPrintf("cesaCheckReady: reqId=%d, checkOffset=%d, checkSize=%d\n", -+ reqId, cesaCheckOffset, cesaCheckSize); -+*/ -+ /* Check expected reqId */ -+ if(reqId != cesaExpReqId) -+ { -+ cesaReqIdError++; -+/* -+ mvOsPrintf("CESA reqId Error: cbIter=%d (%d), reqId=%d, expReqId=%d\n", -+ cesaCbIter, cesaIteration, reqId, cesaExpReqId); -+*/ -+ } -+ else -+ { -+ if( (cesaCheckMode == CESA_FULL_CHECK_MODE) || -+ (cesaCheckMode == CESA_FAST_CHECK_MODE) ) -+ { -+ if(cesaResult.retCode != MV_OK) -+ { -+ cesaError++; -+ -+ mvOsPrintf("CESA Error: cbIter=%d (%d), reqId=%d, rc=%d\n", -+ cesaCbIter, cesaIteration, reqId, cesaResult.retCode); -+ } -+ else -+ { -+ if( (cesaCheckSize > 0) && (cesaOutputHexStr != NULL) ) -+ { -+ /* Check expected output */ -+ -+ isFailed = cesaCheckMbuf(pMbuf, cesaOutputHexStr, cesaCheckOffset, cesaCheckSize); -+ if(isFailed) -+ { -+ mvOsPrintf("CESA Crypto Error: cbIter=%d (%d), reqId=%d\n", -+ cesaCbIter, cesaIteration, reqId); -+ -+ CESA_TEST_DEBUG_PRINT(("Error: reqId=%d, reqSize=%d, checkOffset=%d, checkSize=%d\n", -+ reqId, cesaReqSize, cesaCheckOffset, cesaCheckSize)); -+ -+ CESA_TEST_DEBUG_PRINT(("Output str: %s\n", cesaOutputHexStr)); -+ -+ CESA_TEST_DEBUG_CODE( mvCesaDebugMbuf("error", pMbuf, 0, cesaCheckOffset+cesaCheckSize) ); -+ -+ cesaCryptoError++; -+ } -+ } -+ } -+ } -+ } -+ if(cesaCheckMode == CESA_SHOW_CHECK_MODE) -+ { -+ extractMbuf(pMbuf, cesaCheckOffset, cesaCheckSize, cesaHexBuffer); -+ mvOsPrintf("%4d, %s\n", cesaCheckOffset, cesaHexBuffer); -+ } -+ -+ cesaCbIter++; -+ if(cesaCbIter >= cesaIteration) -+ { -+ cesaCbIter = 0; -+ cesaExpReqId = 0; -+ cesaIsReady = MV_TRUE; -+ -+ cesaEndTicks = CESA_TEST_TICK_GET(); -+ cesaRate = getRate(&cesaRateAfterDot); -+ } -+ else -+ { -+ cesaExpReqId = reqId + 1; -+ if(cesaExpReqId == CESA_DEF_REQ_SIZE) -+ cesaExpReqId = 0; -+ } -+} -+ -+ -+#ifdef MV_NETBSD -+static int cesaTestReadyIsr(void *arg) -+#else -+#ifdef __KERNEL__ -+static irqreturn_t cesaTestReadyIsr( int irq , void *dev_id) -+#endif -+#ifdef MV_VXWORKS -+void cesaTestReadyIsr(void) -+#endif -+#endif -+{ -+ MV_U32 cause; -+ MV_STATUS status; -+ MV_CESA_RESULT result; -+ -+ cesaTestIsrCount++; -+ /* Clear cause register */ -+ cause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); -+ if( (cause & MV_CESA_CAUSE_ACC_DMA_ALL_MASK) == 0) -+ { -+ mvOsPrintf("cesaTestReadyIsr: cause=0x%x\n", cause); -+#ifdef MV_NETBSD -+ return 0; -+#else -+#ifdef __KERNEL__ -+ return 1; -+#else -+ return; -+#endif -+#endif -+ } -+ -+ MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); -+ -+ while(MV_TRUE) -+ { -+ /* Get Ready requests */ -+ status = mvCesaReadyGet(&result); -+ if(status == MV_OK) -+ cesaCheckReady(&result); -+ -+ break; -+ } -+ if( (cesaTestFull == 1) && (status != MV_BUSY) ) -+ { -+ cesaTestFull = 0; -+ CESA_TEST_WAKE_UP(); -+ } -+ -+#ifdef __KERNEL__ -+ return 1; -+#endif -+} -+ -+void -+cesaTestCheckReady(const MV_CESA_RESULT *r) -+{ -+ MV_CESA_RESULT result = *r; -+ -+ cesaCheckReady(&result); -+ -+ if (cesaTestFull == 1) { -+ cesaTestFull = 0; -+ CESA_TEST_WAKE_UP(); -+ } -+} -+ -+static INLINE int open_session(MV_CESA_OPEN_SESSION* pOs) -+{ -+ MV_U16 sid; -+ MV_STATUS status; -+ -+ status = mvCesaSessionOpen(pOs, (short*)&sid); -+ if(status != MV_OK) -+ { -+ mvOsPrintf("CesaTest: Can't open new session - status = 0x%x\n", -+ status); -+ return -1; -+ } -+ -+ return (int)sid; -+} -+ -+void close_session(int sid) -+{ -+ MV_STATUS status; -+ -+ status = mvCesaSessionClose(sid); -+ if(status != MV_OK) -+ { -+ mvOsPrintf("CesaTest: Can't close session %d - status = 0x%x\n", -+ sid, status); -+ } -+} -+ -+MV_STATUS testOpen(int idx) -+{ -+ MV_CESA_OPEN_SESSION os; -+ int sid, i, testIdx; -+ MV_CESA_TEST_SESSION* pTestSession; -+ MV_U16 digestSize = 0; -+ -+ pTestSession = getTestSessionDb(idx, &testIdx); -+ if(pTestSession == NULL) -+ { -+ mvOsPrintf("Test %d is not exist\n", idx); -+ return MV_BAD_PARAM; -+ } -+ pTestSession = &pTestSession[testIdx]; -+ -+ if(pTestSession->sid != -1) -+ { -+ mvOsPrintf("Session for test %d already created: sid=%d\n", -+ idx, pTestSession->sid); -+ return MV_OK; -+ } -+ -+ os.cryptoAlgorithm = pTestSession->cryptoAlgorithm; -+ os.macMode = pTestSession->macAlgorithm; -+ switch(os.macMode) -+ { -+ case MV_CESA_MAC_MD5: -+ case MV_CESA_MAC_HMAC_MD5: -+ digestSize = MV_CESA_MD5_DIGEST_SIZE; -+ break; -+ -+ case MV_CESA_MAC_SHA1: -+ case MV_CESA_MAC_HMAC_SHA1: -+ digestSize = MV_CESA_SHA1_DIGEST_SIZE; -+ break; -+ -+ case MV_CESA_MAC_NULL: -+ digestSize = 0; -+ } -+ os.cryptoMode = pTestSession->cryptoMode; -+ os.direction = pTestSession->direction; -+ os.operation = pTestSession->operation; -+ -+ for(i=0; icryptoKeySize; i++) -+ os.cryptoKey[i] = pTestSession->pCryptoKey[i]; -+ -+ os.cryptoKeyLength = pTestSession->cryptoKeySize; -+ -+ for(i=0; imacKeySize; i++) -+ os.macKey[i] = pTestSession->pMacKey[i]; -+ -+ os.macKeyLength = pTestSession->macKeySize; -+ os.digestSize = digestSize; -+ -+ sid = open_session(&os); -+ if(sid == -1) -+ { -+ mvOsPrintf("Can't open session for test %d: rc=0x%x\n", -+ idx, cesaResult.retCode); -+ return cesaResult.retCode; -+ } -+ CESA_TEST_DEBUG_PRINT(("Opened session: sid = %d\n", sid)); -+ pTestSession->sid = sid; -+ return MV_OK; -+} -+ -+MV_STATUS testClose(int idx) -+{ -+ int testIdx; -+ MV_CESA_TEST_SESSION* pTestSession; -+ -+ pTestSession = getTestSessionDb(idx, &testIdx); -+ if(pTestSession == NULL) -+ { -+ mvOsPrintf("Test %d is not exist\n", idx); -+ return MV_BAD_PARAM; -+ } -+ pTestSession = &pTestSession[testIdx]; -+ -+ if(pTestSession->sid == -1) -+ { -+ mvOsPrintf("Test session %d is not opened\n", idx); -+ return MV_NO_SUCH; -+ } -+ -+ close_session(pTestSession->sid); -+ pTestSession->sid = -1; -+ -+ return MV_OK; -+} -+ -+MV_STATUS testCmd(int sid, int iter, MV_CESA_COMMAND* pCmd, -+ MV_CESA_TEST_SESSION* pTestSession, MV_U8* pIV, int ivSize) -+{ -+ int cmdReqId = 0; -+ int i; -+ MV_STATUS rc = MV_OK; -+ char ivZeroHex[] = "0000"; -+ -+ if(iter == 0) -+ iter = CESA_DEF_ITER_NUM; -+ -+ if(pCmd == NULL) -+ { -+ mvOsPrintf("testCmd failed: pCmd=NULL\n"); -+ return MV_BAD_PARAM; -+ } -+ pCmd->sessionId = sid; -+ -+ cesaCryptoError = 0; -+ cesaReqIdError = 0; -+ cesaError = 0; -+ cesaTestIsrMissCount = 0; -+ cesaIsReady = MV_FALSE; -+ cesaIteration = iter; -+ -+ if(cesaInputHexStr == NULL) -+ cesaInputHexStr = cesaPlainHexEbc; -+ -+ for(i=0; ipSrc = (MV_CESA_MBUF*)(cesaCmdRing[i].pSrc); -+ if(pIV != NULL) -+ { -+ /* If IV from SA - set IV in Source buffer to zeros */ -+ cesaSetMbuf(pCmd->pSrc, ivZeroHex, 0, pCmd->cryptoOffset); -+ cesaSetMbuf(pCmd->pSrc, cesaInputHexStr, pCmd->cryptoOffset, -+ (cesaReqSize - pCmd->cryptoOffset)); -+ } -+ else -+ { -+ cesaSetMbuf(pCmd->pSrc, cesaInputHexStr, 0, cesaReqSize); -+ } -+ pCmd->pDst = (MV_CESA_MBUF*)(cesaCmdRing[i].pDst); -+ cesaSetMbuf(pCmd->pDst, cesaNullPlainHexText, 0, cesaReqSize); -+ -+ memcpy(&cesaCmdRing[i], pCmd, sizeof(*pCmd)); -+ } -+ -+ if(cesaCheckMode == CESA_SW_SHOW_CHECK_MODE) -+ { -+ MV_U8 pDigest[MV_CESA_MAX_DIGEST_SIZE]; -+ -+ if(pTestSession->macAlgorithm == MV_CESA_MAC_MD5) -+ { -+ mvMD5(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, pDigest); -+ mvOsPrintf("SW HASH_MD5: reqSize=%d, macLength=%d\n", -+ cesaReqSize, pCmd->macLength); -+ mvDebugMemDump(pDigest, MV_CESA_MD5_DIGEST_SIZE, 1); -+ return MV_OK; -+ } -+ if(pTestSession->macAlgorithm == MV_CESA_MAC_SHA1) -+ { -+ mvSHA1(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, pDigest); -+ mvOsPrintf("SW HASH_SHA1: reqSize=%d, macLength=%d\n", -+ cesaReqSize, pCmd->macLength); -+ mvDebugMemDump(pDigest, MV_CESA_SHA1_DIGEST_SIZE, 1); -+ return MV_OK; -+ } -+ } -+ -+ cesaBeginTicks = CESA_TEST_TICK_GET(); -+ CESA_TEST_DEBUG_CODE( memset(cesaTestTrace, 0, sizeof(cesaTestTrace)); -+ cesaTestTraceIdx = 0; -+ ); -+ -+ if(cesaCheckMode == CESA_SW_NULL_CHECK_MODE) -+ { -+ volatile MV_U8 pDigest[MV_CESA_MAX_DIGEST_SIZE]; -+ -+ for(i=0; imacAlgorithm == MV_CESA_MAC_MD5) -+ { -+ mvMD5(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, (unsigned char*)pDigest); -+ } -+ if(pTestSession->macAlgorithm == MV_CESA_MAC_SHA1) -+ { -+ mvSHA1(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, (MV_U8 *)pDigest); -+ } -+ } -+ cesaEndTicks = CESA_TEST_TICK_GET(); -+ cesaRate = getRate(&cesaRateAfterDot); -+ cesaIsReady = MV_TRUE; -+ -+ return MV_OK; -+ } -+ -+ /*cesaTestIsrCount = 0;*/ -+ /*mvCesaDebugStatsClear();*/ -+ -+#ifndef MV_NETBSD -+ MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); -+#endif -+ -+ for(i=0; ipReqPrv = (void*)cmdReqId; -+ -+ CESA_TEST_LOCK(flags); -+ -+ rc = mvCesaAction(pCmd); -+ if(rc == MV_NO_RESOURCE) -+ cesaTestFull = 1; -+ -+ CESA_TEST_UNLOCK(flags); -+ -+ if(rc == MV_NO_RESOURCE) -+ { -+ CESA_TEST_LOCK(flags); -+ CESA_TEST_WAIT( (cesaTestFull == 0), 100); -+ CESA_TEST_UNLOCK(flags); -+ if(cesaTestFull == 1) -+ { -+ mvOsPrintf("CESA Test timeout: i=%d, iter=%d, cesaTestFull=%d\n", -+ i, iter, cesaTestFull); -+ cesaTestFull = 0; -+ return MV_TIMEOUT; -+ } -+ -+ CESA_TEST_LOCK(flags); -+ -+ rc = mvCesaAction(pCmd); -+ -+ CESA_TEST_UNLOCK(flags); -+ } -+ if( (rc != MV_OK) && (rc != MV_NO_MORE) ) -+ { -+ mvOsPrintf("mvCesaAction failed: rc=%d\n", rc); -+ return rc; -+ } -+ -+ cmdReqId++; -+ if(cmdReqId >= CESA_DEF_REQ_SIZE) -+ cmdReqId = 0; -+ -+#ifdef MV_LINUX -+ /* Reschedule each 16 requests */ -+ if( (i & 0xF) == 0) -+ schedule(); -+#endif -+ } -+ return MV_OK; -+} -+ -+void cesaTestStart(int bufNum, int bufSize) -+{ -+ int i, j, idx; -+ MV_CESA_MBUF *pMbufSrc, *pMbufDst; -+ MV_BUF_INFO *pFragsSrc, *pFragsDst; -+ char *pBuf; -+#ifndef MV_NETBSD -+ int numOfSessions, queueDepth; -+ char *pSram; -+ MV_STATUS status; -+ MV_CPU_DEC_WIN addrDecWin; -+#endif -+ -+ cesaCmdRing = mvOsMalloc(sizeof(MV_CESA_COMMAND) * CESA_DEF_REQ_SIZE); -+ if(cesaCmdRing == NULL) -+ { -+ mvOsPrintf("testStart: Can't allocate %ld bytes of memory\n", -+ sizeof(MV_CESA_COMMAND) * CESA_DEF_REQ_SIZE); -+ return; -+ } -+ memset(cesaCmdRing, 0, sizeof(MV_CESA_COMMAND) * CESA_DEF_REQ_SIZE); -+ -+ if(bufNum == 0) -+ bufNum = CESA_DEF_BUF_NUM; -+ -+ if(bufSize == 0) -+ bufSize = CESA_DEF_BUF_SIZE; -+ -+ cesaBufNum = bufNum; -+ cesaBufSize = bufSize; -+ mvOsPrintf("CESA test started: bufNum = %d, bufSize = %d\n", -+ bufNum, bufSize); -+ -+ cesaHexBuffer = mvOsMalloc(2*bufNum*bufSize); -+ if(cesaHexBuffer == NULL) -+ { -+ mvOsPrintf("testStart: Can't malloc %d bytes for cesaHexBuffer.\n", -+ 2*bufNum*bufSize); -+ return; -+ } -+ memset(cesaHexBuffer, 0, (2*bufNum*bufSize)); -+ -+ cesaBinBuffer = mvOsMalloc(bufNum*bufSize); -+ if(cesaBinBuffer == NULL) -+ { -+ mvOsPrintf("testStart: Can't malloc %d bytes for cesaBinBuffer\n", -+ bufNum*bufSize); -+ return; -+ } -+ memset(cesaBinBuffer, 0, (bufNum*bufSize)); -+ -+ cesaExpBinBuffer = mvOsMalloc(bufNum*bufSize); -+ if(cesaExpBinBuffer == NULL) -+ { -+ mvOsPrintf("testStart: Can't malloc %d bytes for cesaExpBinBuffer\n", -+ bufNum*bufSize); -+ return; -+ } -+ memset(cesaExpBinBuffer, 0, (bufNum*bufSize)); -+ -+ CESA_TEST_WAIT_INIT(); -+ -+ pMbufSrc = mvOsMalloc(sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); -+ pFragsSrc = mvOsMalloc(sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); -+ -+ pMbufDst = mvOsMalloc(sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); -+ pFragsDst = mvOsMalloc(sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); -+ -+ if( (pMbufSrc == NULL) || (pFragsSrc == NULL) || -+ (pMbufDst == NULL) || (pFragsDst == NULL) ) -+ { -+ mvOsPrintf("testStart: Can't malloc Src and Dst pMbuf and pFrags structures.\n"); -+ /* !!!! Dima cesaTestCleanup();*/ -+ return; -+ } -+ -+ memset(pMbufSrc, 0, sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); -+ memset(pFragsSrc, 0, sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); -+ -+ memset(pMbufDst, 0, sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); -+ memset(pFragsDst, 0, sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); -+ -+ mvOsPrintf("Cesa Test Start: pMbufSrc=%p, pFragsSrc=%p, pMbufDst=%p, pFragsDst=%p\n", -+ pMbufSrc, pFragsSrc, pMbufDst, pFragsDst); -+ -+ idx = 0; -+ for(i=0; ipFrags = &pFragsSrc[idx]; -+ cesaCmdRing[i].pSrc->numFrags = bufNum; -+ cesaCmdRing[i].pSrc->mbufSize = 0; -+ -+ cesaCmdRing[i].pDst = &pMbufDst[i]; -+ cesaCmdRing[i].pDst->pFrags = &pFragsDst[idx]; -+ cesaCmdRing[i].pDst->numFrags = bufNum; -+ cesaCmdRing[i].pDst->mbufSize = 0; -+ -+ for(j=0; jpFrags[j].bufVirtPtr = (MV_U8*)pBuf; -+ cesaCmdRing[i].pSrc->pFrags[j].bufSize = bufSize; -+ pBuf += bufSize; -+ cesaCmdRing[i].pDst->pFrags[j].bufVirtPtr = (MV_U8*)pBuf; -+ cesaCmdRing[i].pDst->pFrags[j].bufSize = bufSize; -+ pBuf += bufSize; -+ } -+ idx += bufNum; -+ } -+ -+#ifndef MV_NETBSD -+ if (mvCpuIfTargetWinGet(CRYPT_ENG, &addrDecWin) == MV_OK) -+ pSram = (char*)addrDecWin.addrWin.baseLow; -+ else -+ { -+ mvOsPrintf("mvCesaInit: ERR. mvCpuIfTargetWinGet failed\n"); -+ return; -+ } -+ -+#ifdef MV_CESA_NO_SRAM -+ pSram = mvOsMalloc(4*1024+8); -+ if(pSram == NULL) -+ { -+ mvOsPrintf("CesaTest: can't allocate %d bytes for SRAM simulation\n", -+ 4*1024+8); -+ /* !!!! Dima cesaTestCleanup();*/ -+ return; -+ } -+ pSram = (MV_U8*)MV_ALIGN_UP((MV_U32)pSram, 8); -+#endif /* MV_CESA_NO_SRAM */ -+ -+ numOfSessions = CESA_DEF_SESSION_NUM; -+ queueDepth = CESA_DEF_REQ_SIZE - MV_CESA_MAX_CHAN; -+ -+ status = mvCesaInit(numOfSessions, queueDepth, pSram, NULL); -+ if(status != MV_OK) -+ { -+ mvOsPrintf("mvCesaInit is Failed: status = 0x%x\n", status); -+ /* !!!! Dima cesaTestCleanup();*/ -+ return; -+ } -+#endif /* !MV_NETBSD */ -+ -+ /* Prepare data for tests */ -+ for(i=0; i<50; i++) -+ strcat((char*)cesaDataHexStr3, "dd"); -+ -+ strcpy((char*)cesaDataAndMd5digest3, cesaDataHexStr3); -+ strcpy((char*)cesaDataAndSha1digest3, cesaDataHexStr3); -+ -+ /* Digest must be 8 byte aligned */ -+ for(; i<56; i++) -+ { -+ strcat((char*)cesaDataAndMd5digest3, "00"); -+ strcat((char*)cesaDataAndSha1digest3, "00"); -+ } -+ strcat((char*)cesaDataAndMd5digest3, cesaHmacMd5digestHex3); -+ strcat((char*)cesaDataAndSha1digest3, cesaHmacSha1digestHex3); -+ -+#ifndef MV_NETBSD -+ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); -+ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, MV_CESA_CAUSE_ACC_DMA_MASK); -+#endif -+ -+#ifdef MV_VXWORKS -+ { -+ MV_STATUS status; -+ -+ status = intConnect((VOIDFUNCPTR *)INT_LVL_CESA, cesaTestReadyIsr, (int)NULL); -+ if (status != OK) -+ { -+ mvOsPrintf("CESA: Can't connect CESA (%d) interrupt, status=0x%x \n", -+ INT_LVL_CESA, status); -+ /* !!!! Dima cesaTestCleanup();*/ -+ return; -+ } -+ cesaSemId = semMCreate(SEM_Q_PRIORITY | SEM_INVERSION_SAFE | SEM_DELETE_SAFE); -+ if(cesaSemId == NULL) -+ { -+ mvOsPrintf("cesaTestStart: Can't create semaphore\n"); -+ return; -+ } -+ intEnable(INT_LVL_CESA); -+ } -+#endif /* MV_VXWORKS */ -+ -+#if !defined(MV_NETBSD) && defined(__KERNEL__) -+ if( request_irq(CESA_IRQ, cesaTestReadyIsr, (SA_INTERRUPT) , "cesa_test", NULL ) ) -+ { -+ mvOsPrintf( "cannot assign irq\n" ); -+ /* !!!! Dima cesaTestCleanup();*/ -+ return; -+ } -+ spin_lock_init( &cesaLock ); -+#endif -+} -+ -+MV_STATUS testRun(int idx, int caseIdx, int iter, -+ int reqSize, int checkMode) -+{ -+ int testIdx, count, sid, digestSize; -+ int blockSize; -+ MV_CESA_TEST_SESSION* pTestSession; -+ MV_CESA_COMMAND cmd; -+ MV_STATUS status; -+ -+ memset(&cmd, 0, sizeof(cmd)); -+ -+ pTestSession = getTestSessionDb(idx, &testIdx); -+ if(pTestSession == NULL) -+ { -+ mvOsPrintf("Test %d is not exist\n", idx); -+ return MV_BAD_PARAM; -+ } -+ pTestSession = &pTestSession[testIdx]; -+ -+ sid = pTestSession->sid; -+ if(sid == -1) -+ { -+ mvOsPrintf("Test %d is not opened\n", idx); -+ return MV_BAD_STATE; -+ } -+ switch(pTestSession->cryptoAlgorithm) -+ { -+ case MV_CESA_CRYPTO_DES: -+ case MV_CESA_CRYPTO_3DES: -+ blockSize = MV_CESA_DES_BLOCK_SIZE; -+ break; -+ -+ case MV_CESA_CRYPTO_AES: -+ blockSize = MV_CESA_AES_BLOCK_SIZE; -+ break; -+ -+ case MV_CESA_CRYPTO_NULL: -+ blockSize = 0; -+ break; -+ -+ default: -+ mvOsPrintf("cesaTestRun: Bad CryptoAlgorithm=%d\n", -+ pTestSession->cryptoAlgorithm); -+ return MV_BAD_PARAM; -+ } -+ switch(pTestSession->macAlgorithm) -+ { -+ case MV_CESA_MAC_MD5: -+ case MV_CESA_MAC_HMAC_MD5: -+ digestSize = MV_CESA_MD5_DIGEST_SIZE; -+ break; -+ -+ case MV_CESA_MAC_SHA1: -+ case MV_CESA_MAC_HMAC_SHA1: -+ digestSize = MV_CESA_SHA1_DIGEST_SIZE; -+ break; -+ default: -+ digestSize = 0; -+ } -+ -+ if(iter == 0) -+ iter = CESA_DEF_ITER_NUM; -+ -+ if(pTestSession->direction == MV_CESA_DIR_ENCODE) -+ { -+ cesaOutputHexStr = cesaTestCases[caseIdx].cipherHexStr; -+ cesaInputHexStr = cesaTestCases[caseIdx].plainHexStr; -+ } -+ else -+ { -+ cesaOutputHexStr = cesaTestCases[caseIdx].plainHexStr; -+ cesaInputHexStr = cesaTestCases[caseIdx].cipherHexStr; -+ } -+ -+ cmd.sessionId = sid; -+ if(checkMode == CESA_FAST_CHECK_MODE) -+ { -+ cmd.cryptoLength = cesaTestCases[caseIdx].cryptoLength; -+ cmd.macLength = cesaTestCases[caseIdx].macLength; -+ } -+ else -+ { -+ cmd.cryptoLength = reqSize; -+ cmd.macLength = reqSize; -+ } -+ cesaRateSize = cmd.cryptoLength; -+ cesaReqSize = cmd.cryptoLength; -+ cmd.cryptoOffset = 0; -+ if(pTestSession->operation != MV_CESA_MAC_ONLY) -+ { -+ if( (pTestSession->cryptoMode == MV_CESA_CRYPTO_CBC) || -+ (pTestSession->cryptoMode == MV_CESA_CRYPTO_CTR) ) -+ { -+ cmd.ivOffset = 0; -+ cmd.cryptoOffset = blockSize; -+ if(cesaTestCases[caseIdx].pCryptoIV == NULL) -+ { -+ cmd.ivFromUser = 1; -+ } -+ else -+ { -+ cmd.ivFromUser = 0; -+ mvCesaCryptoIvSet(cesaTestCases[caseIdx].pCryptoIV, blockSize); -+ } -+ cesaReqSize = cmd.cryptoOffset + cmd.cryptoLength; -+ } -+ } -+ -+/* -+ mvOsPrintf("ivFromUser=%d, cryptoLength=%d, cesaReqSize=%d, cryptoOffset=%d\n", -+ cmd.ivFromUser, cmd.cryptoLength, cesaReqSize, cmd.cryptoOffset); -+*/ -+ if(pTestSession->operation != MV_CESA_CRYPTO_ONLY) -+ { -+ cmd.macOffset = cmd.cryptoOffset; -+ -+ if(cesaTestCases[caseIdx].digestOffset == -1) -+ { -+ cmd.digestOffset = cmd.macOffset + cmd.macLength; -+ cmd.digestOffset = MV_ALIGN_UP(cmd.digestOffset, 8); -+ } -+ else -+ { -+ cmd.digestOffset = cesaTestCases[caseIdx].digestOffset; -+ } -+ if( (cmd.digestOffset + digestSize) > cesaReqSize) -+ cesaReqSize = cmd.digestOffset + digestSize; -+ } -+ -+ cesaCheckMode = checkMode; -+ -+ if(checkMode == CESA_NULL_CHECK_MODE) -+ { -+ cesaCheckSize = 0; -+ cesaCheckOffset = 0; -+ } -+ else -+ { -+ if(pTestSession->operation == MV_CESA_CRYPTO_ONLY) -+ { -+ cesaCheckOffset = 0; -+ cesaCheckSize = cmd.cryptoLength; -+ } -+ else -+ { -+ cesaCheckSize = digestSize; -+ cesaCheckOffset = cmd.digestOffset; -+ } -+ } -+/* -+ mvOsPrintf("reqSize=%d, checkSize=%d, checkOffset=%d, checkMode=%d\n", -+ cesaReqSize, cesaCheckSize, cesaCheckOffset, cesaCheckMode); -+ -+ mvOsPrintf("blockSize=%d, ivOffset=%d, ivFromUser=%d, crOffset=%d, crLength=%d\n", -+ blockSize, cmd.ivOffset, cmd.ivFromUser, -+ cmd.cryptoOffset, cmd.cryptoLength); -+ -+ mvOsPrintf("macOffset=%d, digestOffset=%d, macLength=%d\n", -+ cmd.macOffset, cmd.digestOffset, cmd.macLength); -+*/ -+ status = testCmd(sid, iter, &cmd, pTestSession, -+ cesaTestCases[caseIdx].pCryptoIV, blockSize); -+ -+ if(status != MV_OK) -+ return status; -+ -+ /* Wait when all callbacks is received */ -+ count = 0; -+ while(cesaIsReady == MV_FALSE) -+ { -+ mvOsSleep(10); -+ count++; -+ if(count > 100) -+ { -+ mvOsPrintf("testRun: Timeout occured\n"); -+ return MV_TIMEOUT; -+ } -+ } -+ -+ return MV_OK; -+} -+ -+ -+void cesaTestStop(void) -+{ -+ MV_CESA_MBUF *pMbufSrc, *pMbufDst; -+ MV_BUF_INFO *pFragsSrc, *pFragsDst; -+ int i; -+ -+ /* Release all allocated memories */ -+ pMbufSrc = (MV_CESA_MBUF*)(cesaCmdRing[0].pSrc); -+ pFragsSrc = cesaCmdRing[0].pSrc->pFrags; -+ -+ pMbufDst = (MV_CESA_MBUF*)(cesaCmdRing[0].pDst); -+ pFragsDst = cesaCmdRing[0].pDst->pFrags; -+ -+ mvOsFree(pMbufSrc); -+ mvOsFree(pMbufDst); -+ mvOsFree(pFragsSrc); -+ mvOsFree(pFragsDst); -+ -+ for(i=0; i 0) -+ cryptoError++; -+ if(cesaReqIdError > 0) -+ reqIdError++; -+ -+ testClose(idx); -+ } -+ } -+ if(cryptoError > 0) -+ mvOsPrintf("cryptoError : %d\n", cryptoError); -+ if(reqIdError > 0) -+ mvOsPrintf("reqIdError : %d\n", reqIdError); -+ -+ if(openErrors > 0) -+ { -+ mvOsPrintf("Open Errors = %d\n", openErrors); -+ for(i=0; i<100; i++) -+ { -+ if(openErrDisp[i] != 0) -+ mvOsPrintf("Error %d - occurs %d times\n", i, openErrDisp[i]); -+ } -+ } -+} -+ -+ -+void loopback_test(int idx, int iter, int size, char* pPlainData) -+{ -+} -+ -+ -+#if defined(MV_VXWORKS) -+int testMode = 0; -+unsigned __TASKCONV cesaTask(void* args) -+{ -+ int reqSize = cesaReqSize; -+ -+ if(testMode == 0) -+ { -+ cesaOneTest(cesaTestIdx, cesaCaseIdx, cesaIteration, -+ reqSize, cesaCheckMode); -+ } -+ else -+ { -+ if(testMode == 1) -+ { -+ cesaTest(cesaIteration, reqSize, cesaCheckMode); -+ combiTest(cesaIteration, reqSize, cesaCheckMode); -+ } -+ else -+ { -+ multiSizeTest(cesaIdx, cesaIteration, cesaCheckMode, NULL); -+ } -+ } -+ return 0; -+} -+ -+void oneTest(int testIdx, int caseIdx, -+ int iter, int reqSize, int checkMode) -+{ -+ long rc; -+ -+ cesaIteration = iter; -+ cesaReqSize = cesaRateSize = reqSize; -+ cesaCheckMode = checkMode; -+ testMode = 0; -+ cesaTestIdx = testIdx; -+ cesaCaseIdx = caseIdx; -+ rc = mvOsTaskCreate("CESA_T", 100, 4*1024, cesaTask, NULL, &cesaTaskId); -+ if (rc != MV_OK) -+ { -+ mvOsPrintf("hMW: Can't create CESA multiCmd test task, rc = %ld\n", rc); -+ } -+} -+ -+void multiTest(int iter, int reqSize, int checkMode) -+{ -+ long rc; -+ -+ cesaIteration = iter; -+ cesaCheckMode = checkMode; -+ cesaReqSize = reqSize; -+ testMode = 1; -+ rc = mvOsTaskCreate("CESA_T", 100, 4*1024, cesaTask, NULL, &cesaTaskId); -+ if (rc != MV_OK) -+ { -+ mvOsPrintf("hMW: Can't create CESA multiCmd test task, rc = %ld\n", rc); -+ } -+} -+ -+void sizeTest(int testIdx, int iter, int checkMode) -+{ -+ long rc; -+ -+ cesaIteration = iter; -+ cesaCheckMode = checkMode; -+ testMode = 2; -+ cesaIdx = testIdx; -+ rc = mvOsTaskCreate("CESA_T", 100, 4*1024, cesaTask, NULL, &cesaTaskId); -+ if (rc != MV_OK) -+ { -+ mvOsPrintf("hMW: Can't create CESA test task, rc = %ld\n", rc); -+ } -+} -+ -+#endif /* MV_VXWORKS */ -+ -+extern void mvCesaDebugSA(short sid, int mode); -+void cesaTestPrintSession(int idx) -+{ -+ int testIdx; -+ MV_CESA_TEST_SESSION* pTestSession; -+ -+ pTestSession = getTestSessionDb(idx, &testIdx); -+ if(pTestSession == NULL) -+ { -+ mvOsPrintf("Test %d is not exist\n", idx); -+ return; -+ } -+ pTestSession = &pTestSession[testIdx]; -+ -+ if(pTestSession->sid == -1) -+ { -+ mvOsPrintf("Test session %d is not opened\n", idx); -+ return; -+ } -+ -+ mvCesaDebugSA(pTestSession->sid, 1); -+} -+ -+void cesaTestPrintStatus(void) -+{ -+ mvOsPrintf("\n\t Cesa Test Status\n\n"); -+ -+ mvOsPrintf("isrCount=%d\n", -+ cesaTestIsrCount); -+ -+#ifdef CESA_TEST_DEBUG -+ { -+ int i, j; -+ j = cesaTestTraceIdx; -+ mvOsPrintf("No Type Cause rCause iCause Res Time pReady pProc pEmpty\n"); -+ for(i=0; itable = mvOsMalloc(numOfEntries*sizeof(MV_LRU_ENTRY)); -+ if(pLruCache->table == NULL) -+ { -+ mvOsFree(pLruCache); -+ return NULL; -+ } -+ memset(pLruCache->table, 0, numOfEntries*sizeof(MV_LRU_ENTRY)); -+ pLruCache->tableSize = numOfEntries; -+ -+ for(i=0; itable[i].next = i+1; -+ pLruCache->table[i].prev = i-1; -+ } -+ pLruCache->least = 0; -+ pLruCache->most = numOfEntries-1; -+ -+ return pLruCache; -+} -+ -+void mvLruCacheFinish(MV_LRU_CACHE* pLruCache) -+{ -+ mvOsFree(pLruCache->table); -+ mvOsFree(pLruCache); -+} -+ -+/* Update LRU cache database after using cache Index */ -+void mvLruCacheIdxUpdate(MV_LRU_CACHE* pLruHndl, int cacheIdx) -+{ -+ int prev, next; -+ -+ if(cacheIdx == pLruHndl->most) -+ return; -+ -+ next = pLruHndl->table[cacheIdx].next; -+ if(cacheIdx == pLruHndl->least) -+ { -+ pLruHndl->least = next; -+ } -+ else -+ { -+ prev = pLruHndl->table[cacheIdx].prev; -+ -+ pLruHndl->table[next].prev = prev; -+ pLruHndl->table[prev].next = next; -+ } -+ -+ pLruHndl->table[pLruHndl->most].next = cacheIdx; -+ pLruHndl->table[cacheIdx].prev = pLruHndl->most; -+ pLruHndl->most = cacheIdx; -+} -+ -+/* Delete LRU cache entry */ -+void mvLruCacheIdxDelete(MV_LRU_CACHE* pLruHndl, int cacheIdx) -+{ -+ int prev, next; -+ -+ if(cacheIdx == pLruHndl->least) -+ return; -+ -+ prev = pLruHndl->table[cacheIdx].prev; -+ if(cacheIdx == pLruHndl->most) -+ { -+ pLruHndl->most = prev; -+ } -+ else -+ { -+ next = pLruHndl->table[cacheIdx].next; -+ -+ pLruHndl->table[next].prev = prev; -+ pLruHndl->table[prev].next = next; -+ } -+ pLruHndl->table[pLruHndl->least].prev = cacheIdx; -+ pLruHndl->table[cacheIdx].next = pLruHndl->least; -+ pLruHndl->least = cacheIdx; -+} -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/cesa/mvLru.h linux-2.6.39/crypto/ocf/kirkwood/cesa/mvLru.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/cesa/mvLru.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/cesa/mvLru.h 2011-08-01 14:38:18.000000000 +0200 -@@ -0,0 +1,112 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+/******************************************************************************* -+* mvLru.h - Header File for Least Recently Used Cache algorithm -+* -+* DESCRIPTION: -+* This header file contains macros typedefs and function declaration for -+* the Least Recently Used Cache algorithm. -+* -+*******************************************************************************/ -+ -+#ifndef __mvLru_h__ -+#define __mvLru_h__ -+ -+ -+typedef struct -+{ -+ int next; -+ int prev; -+} MV_LRU_ENTRY; -+ -+typedef struct -+{ -+ int least; -+ int most; -+ MV_LRU_ENTRY* table; -+ int tableSize; -+ -+}MV_LRU_CACHE; -+ -+ -+/* Find Cache index for replacement LRU */ -+static INLINE int mvLruCacheIdxFind(MV_LRU_CACHE* pLruHndl) -+{ -+ return pLruHndl->least; -+} -+ -+/* Init LRU cache module */ -+MV_LRU_CACHE* mvLruCacheInit(int numOfEntries); -+ -+/* Finish LRU cache module */ -+void mvLruCacheFinish(MV_LRU_CACHE* pLruHndl); -+ -+/* Update LRU cache database after using cache Index */ -+void mvLruCacheIdxUpdate(MV_LRU_CACHE* pLruHndl, int cacheIdx); -+ -+/* Delete LRU cache entry */ -+void mvLruCacheIdxDelete(MV_LRU_CACHE* pLruHndl, int cacheIdx); -+ -+ -+#endif /* __mvLru_h__ */ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/cesa/mvMD5.c linux-2.6.39/crypto/ocf/kirkwood/cesa/mvMD5.c ---- linux-2.6.39.orig/crypto/ocf/kirkwood/cesa/mvMD5.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/cesa/mvMD5.c 2011-08-01 14:38:18.000000000 +0200 -@@ -0,0 +1,349 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "mvOs.h" -+#include "mvMD5.h" -+ -+static void mvMD5Transform(MV_U32 buf[4], MV_U32 const in[MV_MD5_MAC_LEN]); -+ -+#ifdef MV_CPU_LE -+#define mvByteReverse(buf, len) /* Nothing */ -+#else -+static void mvByteReverse(unsigned char *buf, unsigned longs); -+ -+/* -+ * Note: this code is harmless on little-endian machines. -+ */ -+static void mvByteReverse(unsigned char *buf, unsigned longs) -+{ -+ MV_U32 t; -+ -+ do -+ { -+ t = (MV_U32) ((unsigned) buf[3] << 8 | buf[2]) << 16 | -+ ((unsigned) buf[1] << 8 | buf[0]); -+ *(MV_U32 *) buf = t; -+ buf += 4; -+ } while (--longs); -+} -+#endif -+ -+/* -+ * Start MD5 accumulation. Set bit count to 0 and buffer to mysterious -+ * initialization constants. -+ */ -+void mvMD5Init(MV_MD5_CONTEXT *ctx) -+{ -+ ctx->buf[0] = 0x67452301; -+ ctx->buf[1] = 0xefcdab89; -+ ctx->buf[2] = 0x98badcfe; -+ ctx->buf[3] = 0x10325476; -+ -+ ctx->bits[0] = 0; -+ ctx->bits[1] = 0; -+} -+ -+/* -+ * Update context to reflect the concatenation of another buffer full -+ * of bytes. -+ */ -+void mvMD5Update(MV_MD5_CONTEXT *ctx, unsigned char const *buf, unsigned len) -+{ -+ MV_U32 t; -+ -+ /* Update bitcount */ -+ -+ t = ctx->bits[0]; -+ if ((ctx->bits[0] = t + ((MV_U32) len << 3)) < t) -+ ctx->bits[1]++; /* Carry from low to high */ -+ ctx->bits[1] += len >> 29; -+ -+ t = (t >> 3) & 0x3f; /* Bytes already in shsInfo->data */ -+ -+ /* Handle any leading odd-sized chunks */ -+ -+ if (t) -+ { -+ unsigned char *p = (unsigned char *) ctx->in + t; -+ -+ t = 64 - t; -+ if (len < t) -+ { -+ memcpy(p, buf, len); -+ return; -+ } -+ memcpy(p, buf, t); -+ mvByteReverse(ctx->in, MV_MD5_MAC_LEN); -+ mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in); -+ buf += t; -+ len -= t; -+ } -+ /* Process data in 64-byte chunks */ -+ -+ while (len >= 64) -+ { -+ memcpy(ctx->in, buf, 64); -+ mvByteReverse(ctx->in, MV_MD5_MAC_LEN); -+ mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in); -+ buf += 64; -+ len -= 64; -+ } -+ -+ /* Handle any remaining bytes of data. */ -+ -+ memcpy(ctx->in, buf, len); -+} -+ -+/* -+ * Final wrapup - pad to 64-byte boundary with the bit pattern -+ * 1 0* (64-bit count of bits processed, MSB-first) -+ */ -+void mvMD5Final(unsigned char digest[MV_MD5_MAC_LEN], MV_MD5_CONTEXT *ctx) -+{ -+ unsigned count; -+ unsigned char *p; -+ -+ /* Compute number of bytes mod 64 */ -+ count = (ctx->bits[0] >> 3) & 0x3F; -+ -+ /* Set the first char of padding to 0x80. This is safe since there is -+ always at least one byte free */ -+ p = ctx->in + count; -+ *p++ = 0x80; -+ -+ /* Bytes of padding needed to make 64 bytes */ -+ count = 64 - 1 - count; -+ -+ /* Pad out to 56 mod 64 */ -+ if (count < 8) -+ { -+ /* Two lots of padding: Pad the first block to 64 bytes */ -+ memset(p, 0, count); -+ mvByteReverse(ctx->in, MV_MD5_MAC_LEN); -+ mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in); -+ -+ /* Now fill the next block with 56 bytes */ -+ memset(ctx->in, 0, 56); -+ } -+ else -+ { -+ /* Pad block to 56 bytes */ -+ memset(p, 0, count - 8); -+ } -+ mvByteReverse(ctx->in, 14); -+ -+ /* Append length in bits and transform */ -+ ((MV_U32 *) ctx->in)[14] = ctx->bits[0]; -+ ((MV_U32 *) ctx->in)[15] = ctx->bits[1]; -+ -+ mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in); -+ mvByteReverse((unsigned char *) ctx->buf, 4); -+ memcpy(digest, ctx->buf, MV_MD5_MAC_LEN); -+ memset(ctx, 0, sizeof(ctx)); /* In case it's sensitive */ -+} -+ -+/* The four core functions - F1 is optimized somewhat */ -+ -+/* #define F1(x, y, z) (x & y | ~x & z) */ -+#define F1(x, y, z) (z ^ (x & (y ^ z))) -+#define F2(x, y, z) F1(z, x, y) -+#define F3(x, y, z) (x ^ y ^ z) -+#define F4(x, y, z) (y ^ (x | ~z)) -+ -+/* This is the central step in the MD5 algorithm. */ -+#define MD5STEP(f, w, x, y, z, data, s) \ -+ ( w += f(x, y, z) + data, w = w<>(32-s), w += x ) -+ -+/* -+ * The core of the MD5 algorithm, this alters an existing MD5 hash to -+ * reflect the addition of 16 longwords of new data. MD5Update blocks -+ * the data and converts bytes into longwords for this routine. -+ */ -+static void mvMD5Transform(MV_U32 buf[4], MV_U32 const in[MV_MD5_MAC_LEN]) -+{ -+ register MV_U32 a, b, c, d; -+ -+ a = buf[0]; -+ b = buf[1]; -+ c = buf[2]; -+ d = buf[3]; -+ -+ MD5STEP(F1, a, b, c, d, in[0] + 0xd76aa478, 7); -+ MD5STEP(F1, d, a, b, c, in[1] + 0xe8c7b756, 12); -+ MD5STEP(F1, c, d, a, b, in[2] + 0x242070db, 17); -+ MD5STEP(F1, b, c, d, a, in[3] + 0xc1bdceee, 22); -+ MD5STEP(F1, a, b, c, d, in[4] + 0xf57c0faf, 7); -+ MD5STEP(F1, d, a, b, c, in[5] + 0x4787c62a, 12); -+ MD5STEP(F1, c, d, a, b, in[6] + 0xa8304613, 17); -+ MD5STEP(F1, b, c, d, a, in[7] + 0xfd469501, 22); -+ MD5STEP(F1, a, b, c, d, in[8] + 0x698098d8, 7); -+ MD5STEP(F1, d, a, b, c, in[9] + 0x8b44f7af, 12); -+ MD5STEP(F1, c, d, a, b, in[10] + 0xffff5bb1, 17); -+ MD5STEP(F1, b, c, d, a, in[11] + 0x895cd7be, 22); -+ MD5STEP(F1, a, b, c, d, in[12] + 0x6b901122, 7); -+ MD5STEP(F1, d, a, b, c, in[13] + 0xfd987193, 12); -+ MD5STEP(F1, c, d, a, b, in[14] + 0xa679438e, 17); -+ MD5STEP(F1, b, c, d, a, in[15] + 0x49b40821, 22); -+ -+ MD5STEP(F2, a, b, c, d, in[1] + 0xf61e2562, 5); -+ MD5STEP(F2, d, a, b, c, in[6] + 0xc040b340, 9); -+ MD5STEP(F2, c, d, a, b, in[11] + 0x265e5a51, 14); -+ MD5STEP(F2, b, c, d, a, in[0] + 0xe9b6c7aa, 20); -+ MD5STEP(F2, a, b, c, d, in[5] + 0xd62f105d, 5); -+ MD5STEP(F2, d, a, b, c, in[10] + 0x02441453, 9); -+ MD5STEP(F2, c, d, a, b, in[15] + 0xd8a1e681, 14); -+ MD5STEP(F2, b, c, d, a, in[4] + 0xe7d3fbc8, 20); -+ MD5STEP(F2, a, b, c, d, in[9] + 0x21e1cde6, 5); -+ MD5STEP(F2, d, a, b, c, in[14] + 0xc33707d6, 9); -+ MD5STEP(F2, c, d, a, b, in[3] + 0xf4d50d87, 14); -+ MD5STEP(F2, b, c, d, a, in[8] + 0x455a14ed, 20); -+ MD5STEP(F2, a, b, c, d, in[13] + 0xa9e3e905, 5); -+ MD5STEP(F2, d, a, b, c, in[2] + 0xfcefa3f8, 9); -+ MD5STEP(F2, c, d, a, b, in[7] + 0x676f02d9, 14); -+ MD5STEP(F2, b, c, d, a, in[12] + 0x8d2a4c8a, 20); -+ -+ MD5STEP(F3, a, b, c, d, in[5] + 0xfffa3942, 4); -+ MD5STEP(F3, d, a, b, c, in[8] + 0x8771f681, 11); -+ MD5STEP(F3, c, d, a, b, in[11] + 0x6d9d6122, 16); -+ MD5STEP(F3, b, c, d, a, in[14] + 0xfde5380c, 23); -+ MD5STEP(F3, a, b, c, d, in[1] + 0xa4beea44, 4); -+ MD5STEP(F3, d, a, b, c, in[4] + 0x4bdecfa9, 11); -+ MD5STEP(F3, c, d, a, b, in[7] + 0xf6bb4b60, 16); -+ MD5STEP(F3, b, c, d, a, in[10] + 0xbebfbc70, 23); -+ MD5STEP(F3, a, b, c, d, in[13] + 0x289b7ec6, 4); -+ MD5STEP(F3, d, a, b, c, in[0] + 0xeaa127fa, 11); -+ MD5STEP(F3, c, d, a, b, in[3] + 0xd4ef3085, 16); -+ MD5STEP(F3, b, c, d, a, in[6] + 0x04881d05, 23); -+ MD5STEP(F3, a, b, c, d, in[9] + 0xd9d4d039, 4); -+ MD5STEP(F3, d, a, b, c, in[12] + 0xe6db99e5, 11); -+ MD5STEP(F3, c, d, a, b, in[15] + 0x1fa27cf8, 16); -+ MD5STEP(F3, b, c, d, a, in[2] + 0xc4ac5665, 23); -+ -+ MD5STEP(F4, a, b, c, d, in[0] + 0xf4292244, 6); -+ MD5STEP(F4, d, a, b, c, in[7] + 0x432aff97, 10); -+ MD5STEP(F4, c, d, a, b, in[14] + 0xab9423a7, 15); -+ MD5STEP(F4, b, c, d, a, in[5] + 0xfc93a039, 21); -+ MD5STEP(F4, a, b, c, d, in[12] + 0x655b59c3, 6); -+ MD5STEP(F4, d, a, b, c, in[3] + 0x8f0ccc92, 10); -+ MD5STEP(F4, c, d, a, b, in[10] + 0xffeff47d, 15); -+ MD5STEP(F4, b, c, d, a, in[1] + 0x85845dd1, 21); -+ MD5STEP(F4, a, b, c, d, in[8] + 0x6fa87e4f, 6); -+ MD5STEP(F4, d, a, b, c, in[15] + 0xfe2ce6e0, 10); -+ MD5STEP(F4, c, d, a, b, in[6] + 0xa3014314, 15); -+ MD5STEP(F4, b, c, d, a, in[13] + 0x4e0811a1, 21); -+ MD5STEP(F4, a, b, c, d, in[4] + 0xf7537e82, 6); -+ MD5STEP(F4, d, a, b, c, in[11] + 0xbd3af235, 10); -+ MD5STEP(F4, c, d, a, b, in[2] + 0x2ad7d2bb, 15); -+ MD5STEP(F4, b, c, d, a, in[9] + 0xeb86d391, 21); -+ -+ buf[0] += a; -+ buf[1] += b; -+ buf[2] += c; -+ buf[3] += d; -+} -+ -+void mvMD5(unsigned char const *buf, unsigned len, unsigned char* digest) -+{ -+ MV_MD5_CONTEXT ctx; -+ -+ mvMD5Init(&ctx); -+ mvMD5Update(&ctx, buf, len); -+ mvMD5Final(digest, &ctx); -+} -+ -+ -+void mvHmacMd5(unsigned char const* text, int text_len, -+ unsigned char const* key, int key_len, -+ unsigned char* digest) -+{ -+ int i; -+ MV_MD5_CONTEXT ctx; -+ unsigned char k_ipad[64+1]; /* inner padding - key XORd with ipad */ -+ unsigned char k_opad[64+1]; /* outer padding - key XORd with opad */ -+ -+ /* start out by storing key in pads */ -+ memset(k_ipad, 0, 64); -+ memcpy(k_ipad, key, key_len); -+ memset(k_opad, 0, 64); -+ memcpy(k_opad, key, key_len); -+ -+ /* XOR key with ipad and opad values */ -+ for (i=0; i<64; i++) -+ { -+ k_ipad[i] ^= 0x36; -+ k_opad[i] ^= 0x5c; -+ } -+ -+ /* perform inner MD5 */ -+ mvMD5Init(&ctx); /* init ctx for 1st pass */ -+ mvMD5Update(&ctx, k_ipad, 64); /* start with inner pad */ -+ mvMD5Update(&ctx, text, text_len); /* then text of datagram */ -+ mvMD5Final(digest, &ctx); /* finish up 1st pass */ -+ -+ /* perform outer MD5 */ -+ mvMD5Init(&ctx); /* init ctx for 2nd pass */ -+ mvMD5Update(&ctx, k_opad, 64); /* start with outer pad */ -+ mvMD5Update(&ctx, digest, 16); /* then results of 1st hash */ -+ mvMD5Final(digest, &ctx); /* finish up 2nd pass */ -+} -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/cesa/mvMD5.h linux-2.6.39/crypto/ocf/kirkwood/cesa/mvMD5.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/cesa/mvMD5.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/cesa/mvMD5.h 2011-08-01 14:38:18.000000000 +0200 -@@ -0,0 +1,93 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __mvMD5_h__ -+#define __mvMD5_h__ -+ -+#include "mvMD5.h" -+ -+#define MV_MD5_MAC_LEN 16 -+ -+ -+typedef struct -+{ -+ MV_U32 buf[4]; -+ MV_U32 bits[2]; -+ MV_U8 in[64]; -+ -+} MV_MD5_CONTEXT; -+ -+void mvMD5Init(MV_MD5_CONTEXT *context); -+void mvMD5Update(MV_MD5_CONTEXT *context, unsigned char const *buf, -+ unsigned len); -+void mvMD5Final(unsigned char digest[16], MV_MD5_CONTEXT *context); -+ -+void mvMD5(unsigned char const *buf, unsigned len, unsigned char* digest); -+ -+void mvHmacMd5(unsigned char const* text, int text_len, -+ unsigned char const* key, int key_len, -+ unsigned char* digest); -+ -+ -+#endif /* __mvMD5_h__ */ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/cesa/mvSHA1.c linux-2.6.39/crypto/ocf/kirkwood/cesa/mvSHA1.c ---- linux-2.6.39.orig/crypto/ocf/kirkwood/cesa/mvSHA1.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/cesa/mvSHA1.c 2011-08-01 14:38:18.000000000 +0200 -@@ -0,0 +1,239 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "mvOs.h" -+#include "mvSHA1.h" -+ -+#define SHA1HANDSOFF -+ -+typedef union -+{ -+ MV_U8 c[64]; -+ MV_U32 l[16]; -+ -+} CHAR64LONG16; -+ -+static void mvSHA1Transform(MV_U32 state[5], const MV_U8 *buffer); -+ -+#define rol(value, bits) (((value) << (bits)) | ((value) >> (32 - (bits)))) -+ -+ -+#ifdef MV_CPU_LE -+#define blk0(i) (block->l[i] = (rol(block->l[i], 24) & 0xFF00FF00) | \ -+ (rol(block->l[i], 8) & 0x00FF00FF)) -+#else -+#define blk0(i) block->l[i] -+#endif -+#define blk(i) (block->l[i & 15] = rol(block->l[(i + 13) & 15] ^ \ -+ block->l[(i + 8) & 15] ^ block->l[(i + 2) & 15] ^ block->l[i & 15], 1)) -+ -+/* (R0+R1), R2, R3, R4 are the different operations used in SHA1 */ -+#define R0(v,w,x,y,z,i) \ -+ z += ((w & (x ^ y)) ^ y) + blk0(i) + 0x5A827999 + rol(v, 5); \ -+ w = rol(w, 30); -+#define R1(v,w,x,y,z,i) \ -+ z += ((w & (x ^ y)) ^ y) + blk(i) + 0x5A827999 + rol(v, 5); \ -+ w = rol(w, 30); -+#define R2(v,w,x,y,z,i) \ -+ z += (w ^ x ^ y) + blk(i) + 0x6ED9EBA1 + rol(v, 5); w = rol(w, 30); -+#define R3(v,w,x,y,z,i) \ -+ z += (((w | x) & y) | (w & x)) + blk(i) + 0x8F1BBCDC + rol(v, 5); \ -+ w = rol(w, 30); -+#define R4(v,w,x,y,z,i) \ -+ z += (w ^ x ^ y) + blk(i) + 0xCA62C1D6 + rol(v, 5); \ -+ w=rol(w, 30); -+ -+/* Hash a single 512-bit block. This is the core of the algorithm. */ -+static void mvSHA1Transform(MV_U32 state[5], const MV_U8 *buffer) -+{ -+ MV_U32 a, b, c, d, e; -+ CHAR64LONG16* block; -+ -+#ifdef SHA1HANDSOFF -+ static MV_U32 workspace[16]; -+ -+ block = (CHAR64LONG16 *) workspace; -+ memcpy(block, buffer, 64); -+#else -+ block = (CHAR64LONG16 *) buffer; -+#endif -+ /* Copy context->state[] to working vars */ -+ a = state[0]; -+ b = state[1]; -+ c = state[2]; -+ d = state[3]; -+ e = state[4]; -+ /* 4 rounds of 20 operations each. Loop unrolled. */ -+ R0(a,b,c,d,e, 0); R0(e,a,b,c,d, 1); R0(d,e,a,b,c, 2); R0(c,d,e,a,b, 3); -+ R0(b,c,d,e,a, 4); R0(a,b,c,d,e, 5); R0(e,a,b,c,d, 6); R0(d,e,a,b,c, 7); -+ R0(c,d,e,a,b, 8); R0(b,c,d,e,a, 9); R0(a,b,c,d,e,10); R0(e,a,b,c,d,11); -+ R0(d,e,a,b,c,12); R0(c,d,e,a,b,13); R0(b,c,d,e,a,14); R0(a,b,c,d,e,15); -+ R1(e,a,b,c,d,16); R1(d,e,a,b,c,17); R1(c,d,e,a,b,18); R1(b,c,d,e,a,19); -+ R2(a,b,c,d,e,20); R2(e,a,b,c,d,21); R2(d,e,a,b,c,22); R2(c,d,e,a,b,23); -+ R2(b,c,d,e,a,24); R2(a,b,c,d,e,25); R2(e,a,b,c,d,26); R2(d,e,a,b,c,27); -+ R2(c,d,e,a,b,28); R2(b,c,d,e,a,29); R2(a,b,c,d,e,30); R2(e,a,b,c,d,31); -+ R2(d,e,a,b,c,32); R2(c,d,e,a,b,33); R2(b,c,d,e,a,34); R2(a,b,c,d,e,35); -+ R2(e,a,b,c,d,36); R2(d,e,a,b,c,37); R2(c,d,e,a,b,38); R2(b,c,d,e,a,39); -+ R3(a,b,c,d,e,40); R3(e,a,b,c,d,41); R3(d,e,a,b,c,42); R3(c,d,e,a,b,43); -+ R3(b,c,d,e,a,44); R3(a,b,c,d,e,45); R3(e,a,b,c,d,46); R3(d,e,a,b,c,47); -+ R3(c,d,e,a,b,48); R3(b,c,d,e,a,49); R3(a,b,c,d,e,50); R3(e,a,b,c,d,51); -+ R3(d,e,a,b,c,52); R3(c,d,e,a,b,53); R3(b,c,d,e,a,54); R3(a,b,c,d,e,55); -+ R3(e,a,b,c,d,56); R3(d,e,a,b,c,57); R3(c,d,e,a,b,58); R3(b,c,d,e,a,59); -+ R4(a,b,c,d,e,60); R4(e,a,b,c,d,61); R4(d,e,a,b,c,62); R4(c,d,e,a,b,63); -+ R4(b,c,d,e,a,64); R4(a,b,c,d,e,65); R4(e,a,b,c,d,66); R4(d,e,a,b,c,67); -+ R4(c,d,e,a,b,68); R4(b,c,d,e,a,69); R4(a,b,c,d,e,70); R4(e,a,b,c,d,71); -+ R4(d,e,a,b,c,72); R4(c,d,e,a,b,73); R4(b,c,d,e,a,74); R4(a,b,c,d,e,75); -+ R4(e,a,b,c,d,76); R4(d,e,a,b,c,77); R4(c,d,e,a,b,78); R4(b,c,d,e,a,79); -+ /* Add the working vars back into context.state[] */ -+ state[0] += a; -+ state[1] += b; -+ state[2] += c; -+ state[3] += d; -+ state[4] += e; -+ /* Wipe variables */ -+ a = b = c = d = e = 0; -+} -+ -+void mvSHA1Init(MV_SHA1_CTX* context) -+{ -+ /* SHA1 initialization constants */ -+ context->state[0] = 0x67452301; -+ context->state[1] = 0xEFCDAB89; -+ context->state[2] = 0x98BADCFE; -+ context->state[3] = 0x10325476; -+ context->state[4] = 0xC3D2E1F0; -+ context->count[0] = context->count[1] = 0; -+} -+ -+ -+/* Run your data through this. */ -+void mvSHA1Update(MV_SHA1_CTX *context, MV_U8 const *data, -+ unsigned int len) -+{ -+ MV_U32 i, j; -+ -+ j = (context->count[0] >> 3) & 63; -+ if ((context->count[0] += len << 3) < (len << 3)) -+ context->count[1]++; -+ context->count[1] += (len >> 29); -+ if ((j + len) > 63) -+ { -+ memcpy(&context->buffer[j], data, (i = 64-j)); -+ mvSHA1Transform(context->state, context->buffer); -+ for ( ; i + 63 < len; i += 64) -+ { -+ mvSHA1Transform(context->state, &data[i]); -+ } -+ j = 0; -+ } -+ else -+ { -+ i = 0; -+ } -+ memcpy(&context->buffer[j], &data[i], len - i); -+} -+ -+void mvSHA1Final(MV_U8* digest, MV_SHA1_CTX* context) -+{ -+ MV_U32 i; -+ MV_U8 finalcount[8]; -+ -+ for (i = 0; i < 8; i++) -+ { -+ finalcount[i] = (unsigned char)((context->count[(i >= 4 ? 0 : 1)] >> -+ ((3-(i & 3)) * 8) ) & 255); /* Endian independent */ -+ } -+ mvSHA1Update(context, (const unsigned char *) "\200", 1); -+ while ((context->count[0] & 504) != 448) -+ { -+ mvSHA1Update(context, (const unsigned char *) "\0", 1); -+ } -+ mvSHA1Update(context, finalcount, 8); /* Should cause a mvSHA1Transform() -+ */ -+ for (i = 0; i < 20; i++) -+ { -+ digest[i] = (unsigned char) -+ ((context->state[i >> 2] >> ((3 - (i & 3)) * 8)) & 255); -+ } -+ /* Wipe variables */ -+ i = 0; -+ memset(context->buffer, 0, 64); -+ memset(context->state, 0, 20); -+ memset(context->count, 0, 8); -+ memset(finalcount, 0, 8); -+ -+#ifdef SHA1HANDSOFF /* make SHA1Transform overwrite it's own static vars */ -+ mvSHA1Transform(context->state, context->buffer); -+#endif -+} -+ -+ -+void mvSHA1(MV_U8 const *buf, unsigned int len, MV_U8* digest) -+{ -+ MV_SHA1_CTX ctx; -+ -+ mvSHA1Init(&ctx); -+ mvSHA1Update(&ctx, buf, len); -+ mvSHA1Final(digest, &ctx); -+} -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/cesa/mvSHA1.h linux-2.6.39/crypto/ocf/kirkwood/cesa/mvSHA1.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/cesa/mvSHA1.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/cesa/mvSHA1.h 2011-08-01 14:38:18.000000000 +0200 -@@ -0,0 +1,88 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __mvSHA1_h__ -+#define __mvSHA1_h__ -+ -+#include "mvSHA1.h" -+ -+#define MV_SHA1_MAC_LEN 20 -+ -+ -+typedef struct -+{ -+ MV_U32 state[5]; -+ MV_U32 count[2]; -+ MV_U8 buffer[64]; -+ -+} MV_SHA1_CTX; -+ -+void mvSHA1Init(MV_SHA1_CTX *context); -+void mvSHA1Update(MV_SHA1_CTX *context, MV_U8 const *buf, unsigned int len); -+void mvSHA1Final(MV_U8* digest, MV_SHA1_CTX *context); -+ -+void mvSHA1(MV_U8 const *buf, unsigned int len, MV_U8* digest); -+ -+ -+#endif /* __mvSHA1_h__ */ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/cesa_ocf_drv.c linux-2.6.39/crypto/ocf/kirkwood/cesa_ocf_drv.c ---- linux-2.6.39.orig/crypto/ocf/kirkwood/cesa_ocf_drv.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/cesa_ocf_drv.c 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,1296 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+*******************************************************************************/ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "ctrlEnv/sys/mvSysCesa.h" -+#include "cesa/mvCesa.h" /* moved here before cryptodev.h due to include dependencies */ -+#include -+#include -+#include -+#include -+#include "mvDebug.h" -+ -+#include "cesa/mvMD5.h" -+#include "cesa/mvSHA1.h" -+ -+#include "cesa/mvCesaRegs.h" -+#include "cesa/AES/mvAes.h" -+#include "cesa/mvLru.h" -+ -+#undef RT_DEBUG -+#ifdef RT_DEBUG -+static int debug = 1; -+module_param(debug, int, 1); -+MODULE_PARM_DESC(debug, "Enable debug"); -+#undef dprintk -+#define dprintk(a...) if (debug) { printk(a); } else -+#else -+static int debug = 0; -+#undef dprintk -+#define dprintk(a...) -+#endif -+ -+ -+/* TDMA Regs */ -+#define WINDOW_BASE(i) 0xA00 + (i << 3) -+#define WINDOW_CTRL(i) 0xA04 + (i << 3) -+ -+/* interrupt handling */ -+#undef CESA_OCF_POLLING -+#undef CESA_OCF_TASKLET -+ -+#if defined(CESA_OCF_POLLING) && defined(CESA_OCF_TASKLET) -+#error "don't use both tasklet and polling mode" -+#endif -+ -+extern int cesaReqResources; -+/* support for spliting action into 2 actions */ -+#define CESA_OCF_SPLIT -+ -+/* general defines */ -+#define CESA_OCF_MAX_SES 128 -+#define CESA_Q_SIZE 64 -+ -+ -+/* data structures */ -+struct cesa_ocf_data { -+ int cipher_alg; -+ int auth_alg; -+ int encrypt_tn_auth; -+#define auth_tn_decrypt encrypt_tn_auth -+ int ivlen; -+ int digestlen; -+ short sid_encrypt; -+ short sid_decrypt; -+ /* fragment workaround sessions */ -+ short frag_wa_encrypt; -+ short frag_wa_decrypt; -+ short frag_wa_auth; -+}; -+ -+/* CESA device data */ -+struct cesa_dev { -+ void __iomem *sram; -+ void __iomem *reg; -+ struct mv_cesa_platform_data *plat_data; -+ int irq; -+}; -+ -+#define DIGEST_BUF_SIZE 32 -+struct cesa_ocf_process { -+ MV_CESA_COMMAND cesa_cmd; -+ MV_CESA_MBUF cesa_mbuf; -+ MV_BUF_INFO cesa_bufs[MV_CESA_MAX_MBUF_FRAGS]; -+ char digest[DIGEST_BUF_SIZE]; -+ int digest_len; -+ struct cryptop *crp; -+ int need_cb; -+}; -+ -+/* global variables */ -+static int32_t cesa_ocf_id = -1; -+static struct cesa_ocf_data *cesa_ocf_sessions[CESA_OCF_MAX_SES]; -+static spinlock_t cesa_lock; -+static struct cesa_dev cesa_device; -+ -+/* static APIs */ -+static int cesa_ocf_process (device_t, struct cryptop *, int); -+static int cesa_ocf_newsession (device_t, u_int32_t *, struct cryptoini *); -+static int cesa_ocf_freesession (device_t, u_int64_t); -+static void cesa_callback (unsigned long); -+static irqreturn_t cesa_interrupt_handler (int, void *); -+#ifdef CESA_OCF_POLLING -+static void cesa_interrupt_polling(void); -+#endif -+#ifdef CESA_OCF_TASKLET -+static struct tasklet_struct cesa_ocf_tasklet; -+#endif -+ -+static struct timeval tt_start; -+static struct timeval tt_end; -+ -+/* -+ * dummy device structure -+ */ -+ -+static struct { -+ softc_device_decl sc_dev; -+} mv_cesa_dev; -+ -+static device_method_t mv_cesa_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, cesa_ocf_newsession), -+ DEVMETHOD(cryptodev_freesession,cesa_ocf_freesession), -+ DEVMETHOD(cryptodev_process, cesa_ocf_process), -+ DEVMETHOD(cryptodev_kprocess, NULL), -+}; -+ -+ -+ -+/* Add debug Trace */ -+#undef CESA_OCF_TRACE_DEBUG -+#ifdef CESA_OCF_TRACE_DEBUG -+ -+#define MV_CESA_USE_TIMER_ID 0 -+ -+typedef struct -+{ -+ int type; /* 0 - isrEmpty, 1 - cesaReadyGet, 2 - cesaAction */ -+ MV_U32 timeStamp; -+ MV_U32 cause; -+ MV_U32 realCause; -+ MV_U32 dmaCause; -+ int resources; -+ MV_CESA_REQ* pReqReady; -+ MV_CESA_REQ* pReqEmpty; -+ MV_CESA_REQ* pReqProcess; -+} MV_CESA_TEST_TRACE; -+ -+#define MV_CESA_TEST_TRACE_SIZE 50 -+ -+static int cesaTestTraceIdx = 0; -+static MV_CESA_TEST_TRACE cesaTestTrace[MV_CESA_TEST_TRACE_SIZE]; -+ -+static void cesaTestTraceAdd(int type) -+{ -+ cesaTestTrace[cesaTestTraceIdx].type = type; -+ cesaTestTrace[cesaTestTraceIdx].realCause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); -+ //cesaTestTrace[cesaTestTraceIdx].idmaCause = MV_REG_READ(IDMA_CAUSE_REG); -+ cesaTestTrace[cesaTestTraceIdx].resources = cesaReqResources; -+ cesaTestTrace[cesaTestTraceIdx].pReqReady = pCesaReqReady; -+ cesaTestTrace[cesaTestTraceIdx].pReqEmpty = pCesaReqEmpty; -+ cesaTestTrace[cesaTestTraceIdx].pReqProcess = pCesaReqProcess; -+ cesaTestTrace[cesaTestTraceIdx].timeStamp = mvCntmrRead(MV_CESA_USE_TIMER_ID); -+ cesaTestTraceIdx++; -+ if(cesaTestTraceIdx == MV_CESA_TEST_TRACE_SIZE) -+ cesaTestTraceIdx = 0; -+} -+ -+#else /* CESA_OCF_TRACE_DEBUG */ -+ -+#define cesaTestTraceAdd(x) -+ -+#endif /* CESA_OCF_TRACE_DEBUG */ -+ -+unsigned int -+get_usec(unsigned int start) -+{ -+ if(start) { -+ do_gettimeofday (&tt_start); -+ return 0; -+ } -+ else { -+ do_gettimeofday (&tt_end); -+ tt_end.tv_sec -= tt_start.tv_sec; -+ tt_end.tv_usec -= tt_start.tv_usec; -+ if (tt_end.tv_usec < 0) { -+ tt_end.tv_usec += 1000 * 1000; -+ tt_end.tv_sec -= 1; -+ } -+ } -+ printk("time taken is %d\n", (unsigned int)(tt_end.tv_usec + tt_end.tv_sec * 1000000)); -+ return (tt_end.tv_usec + tt_end.tv_sec * 1000000); -+} -+ -+#ifdef RT_DEBUG -+/* -+ * check that the crp action match the current session -+ */ -+static int -+ocf_check_action(struct cryptop *crp, struct cesa_ocf_data *cesa_ocf_cur_ses) { -+ int count = 0; -+ int encrypt = 0, decrypt = 0, auth = 0; -+ struct cryptodesc *crd; -+ -+ /* Go through crypto descriptors, processing as we go */ -+ for (crd = crp->crp_desc; crd; crd = crd->crd_next, count++) { -+ if(count > 2) { -+ printk("%s,%d: session mode is not supported.\n", __FILE__, __LINE__); -+ return 1; -+ } -+ -+ /* Encryption /Decryption */ -+ if(crd->crd_alg == cesa_ocf_cur_ses->cipher_alg) { -+ /* check that the action is compatible with session */ -+ if(encrypt || decrypt) { -+ printk("%s,%d: session mode is not supported.\n", __FILE__, __LINE__); -+ return 1; -+ } -+ -+ if(crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ -+ if( (count == 2) && (cesa_ocf_cur_ses->encrypt_tn_auth) ) { -+ printk("%s,%d: sequence isn't supported by this session.\n", __FILE__, __LINE__); -+ return 1; -+ } -+ encrypt++; -+ } -+ else { /* decrypt */ -+ if( (count == 2) && !(cesa_ocf_cur_ses->auth_tn_decrypt) ) { -+ printk("%s,%d: sequence isn't supported by this session.\n", __FILE__, __LINE__); -+ return 1; -+ } -+ decrypt++; -+ } -+ -+ } -+ /* Authentication */ -+ else if(crd->crd_alg == cesa_ocf_cur_ses->auth_alg) { -+ /* check that the action is compatible with session */ -+ if(auth) { -+ printk("%s,%d: session mode is not supported.\n", __FILE__, __LINE__); -+ return 1; -+ } -+ if( (count == 2) && (decrypt) && (cesa_ocf_cur_ses->auth_tn_decrypt)) { -+ printk("%s,%d: sequence isn't supported by this session.\n", __FILE__, __LINE__); -+ return 1; -+ } -+ if( (count == 2) && (encrypt) && !(cesa_ocf_cur_ses->encrypt_tn_auth)) { -+ printk("%s,%d: sequence isn't supported by this session.\n", __FILE__, __LINE__); -+ return 1; -+ } -+ auth++; -+ } -+ else { -+ printk("%s,%d: Alg isn't supported by this session.\n", __FILE__, __LINE__); -+ return 1; -+ } -+ } -+ return 0; -+ -+} -+#endif -+ -+/* -+ * Process a request. -+ */ -+static int -+cesa_ocf_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ struct cesa_ocf_process *cesa_ocf_cmd = NULL; -+ struct cesa_ocf_process *cesa_ocf_cmd_wa = NULL; -+ MV_CESA_COMMAND *cesa_cmd; -+ struct cryptodesc *crd; -+ struct cesa_ocf_data *cesa_ocf_cur_ses; -+ int sid = 0, temp_len = 0, i; -+ int encrypt = 0, decrypt = 0, auth = 0; -+ int status; -+ struct sk_buff *skb = NULL; -+ struct uio *uiop = NULL; -+ unsigned char *ivp; -+ MV_BUF_INFO *p_buf_info; -+ MV_CESA_MBUF *p_mbuf_info; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if( cesaReqResources <= 1 ) { -+ dprintk("%s,%d: ERESTART\n", __FILE__, __LINE__); -+ return ERESTART; -+ } -+ -+#ifdef RT_DEBUG -+ /* Sanity check */ -+ if (crp == NULL) { -+ printk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ if (crp->crp_desc == NULL || crp->crp_buf == NULL ) { -+ printk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ return EINVAL; -+ } -+ -+ sid = crp->crp_sid & 0xffffffff; -+ if ((sid >= CESA_OCF_MAX_SES) || (cesa_ocf_sessions[sid] == NULL)) { -+ crp->crp_etype = ENOENT; -+ printk("%s,%d: ENOENT session %d \n", __FILE__, __LINE__, sid); -+ return EINVAL; -+ } -+#endif -+ -+ sid = crp->crp_sid & 0xffffffff; -+ crp->crp_etype = 0; -+ cesa_ocf_cur_ses = cesa_ocf_sessions[sid]; -+ -+#ifdef RT_DEBUG -+ if(ocf_check_action(crp, cesa_ocf_cur_ses)){ -+ goto p_error; -+ } -+#endif -+ -+ /* malloc a new cesa process */ -+ cesa_ocf_cmd = kmalloc(sizeof(struct cesa_ocf_process), GFP_ATOMIC); -+ -+ if (cesa_ocf_cmd == NULL) { -+ printk("%s,%d: ENOBUFS \n", __FILE__, __LINE__); -+ goto p_error; -+ } -+ memset(cesa_ocf_cmd, 0, sizeof(struct cesa_ocf_process)); -+ -+ /* init cesa_process */ -+ cesa_ocf_cmd->crp = crp; -+ /* always call callback */ -+ cesa_ocf_cmd->need_cb = 1; -+ -+ /* init cesa_cmd for usage of the HALs */ -+ cesa_cmd = &cesa_ocf_cmd->cesa_cmd; -+ cesa_cmd->pReqPrv = (void *)cesa_ocf_cmd; -+ cesa_cmd->sessionId = cesa_ocf_cur_ses->sid_encrypt; /* defualt use encrypt */ -+ -+ /* prepare src buffer */ -+ /* we send the entire buffer to the HAL, even if only part of it should be encrypt/auth. */ -+ /* if not using seesions for both encrypt and auth, then it will be wiser to to copy only */ -+ /* from skip to crd_len. */ -+ p_buf_info = cesa_ocf_cmd->cesa_bufs; -+ p_mbuf_info = &cesa_ocf_cmd->cesa_mbuf; -+ -+ p_buf_info += 2; /* save 2 first buffers for IV and digest - -+ we won't append them to the end since, they -+ might be places in an unaligned addresses. */ -+ -+ p_mbuf_info->pFrags = p_buf_info; -+ temp_len = 0; -+ -+ /* handle SKB */ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ -+ dprintk("%s,%d: handle SKB.\n", __FILE__, __LINE__); -+ skb = (struct sk_buff *) crp->crp_buf; -+ -+ if (skb_shinfo(skb)->nr_frags >= (MV_CESA_MAX_MBUF_FRAGS - 1)) { -+ printk("%s,%d: %d nr_frags > MV_CESA_MAX_MBUF_FRAGS", __FILE__, __LINE__, skb_shinfo(skb)->nr_frags); -+ goto p_error; -+ } -+ -+ p_mbuf_info->mbufSize = skb->len; -+ temp_len = skb->len; -+ /* first skb fragment */ -+ p_buf_info->bufSize = skb_headlen(skb); -+ p_buf_info->bufVirtPtr = skb->data; -+ p_buf_info++; -+ -+ /* now handle all other skb fragments */ -+ for ( i = 0; i < skb_shinfo(skb)->nr_frags; i++ ) { -+ skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; -+ p_buf_info->bufSize = frag->size; -+ p_buf_info->bufVirtPtr = page_address(frag->page) + frag->page_offset; -+ p_buf_info++; -+ } -+ p_mbuf_info->numFrags = skb_shinfo(skb)->nr_frags + 1; -+ } -+ /* handle UIO */ -+ else if(crp->crp_flags & CRYPTO_F_IOV) { -+ -+ dprintk("%s,%d: handle UIO.\n", __FILE__, __LINE__); -+ uiop = (struct uio *) crp->crp_buf; -+ -+ if (uiop->uio_iovcnt > (MV_CESA_MAX_MBUF_FRAGS - 1)) { -+ printk("%s,%d: %d uio_iovcnt > MV_CESA_MAX_MBUF_FRAGS \n", __FILE__, __LINE__, uiop->uio_iovcnt); -+ goto p_error; -+ } -+ -+ p_mbuf_info->mbufSize = crp->crp_ilen; -+ p_mbuf_info->numFrags = uiop->uio_iovcnt; -+ for(i = 0; i < uiop->uio_iovcnt; i++) { -+ p_buf_info->bufVirtPtr = uiop->uio_iov[i].iov_base; -+ p_buf_info->bufSize = uiop->uio_iov[i].iov_len; -+ temp_len += p_buf_info->bufSize; -+ dprintk("%s,%d: buf %x-> addr %x, size %x \n" -+ , __FILE__, __LINE__, i, (unsigned int)p_buf_info->bufVirtPtr, p_buf_info->bufSize); -+ p_buf_info++; -+ } -+ -+ } -+ /* handle CONTIG */ -+ else { -+ dprintk("%s,%d: handle CONTIG.\n", __FILE__, __LINE__); -+ p_mbuf_info->numFrags = 1; -+ p_mbuf_info->mbufSize = crp->crp_ilen; -+ p_buf_info->bufVirtPtr = crp->crp_buf; -+ p_buf_info->bufSize = crp->crp_ilen; -+ temp_len = crp->crp_ilen; -+ p_buf_info++; -+ } -+ -+ /* Support up to 64K why? cause! */ -+ if(crp->crp_ilen > 64*1024) { -+ printk("%s,%d: buf too big %x \n", __FILE__, __LINE__, crp->crp_ilen); -+ goto p_error; -+ } -+ -+ if( temp_len != crp->crp_ilen ) { -+ printk("%s,%d: warning size don't match.(%x %x) \n", __FILE__, __LINE__, temp_len, crp->crp_ilen); -+ } -+ -+ cesa_cmd->pSrc = p_mbuf_info; -+ cesa_cmd->pDst = p_mbuf_info; -+ -+ /* restore p_buf_info to point to first available buf */ -+ p_buf_info = cesa_ocf_cmd->cesa_bufs; -+ p_buf_info += 1; -+ -+ -+ /* Go through crypto descriptors, processing as we go */ -+ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { -+ -+ /* Encryption /Decryption */ -+ if(crd->crd_alg == cesa_ocf_cur_ses->cipher_alg) { -+ -+ dprintk("%s,%d: cipher", __FILE__, __LINE__); -+ -+ cesa_cmd->cryptoOffset = crd->crd_skip; -+ cesa_cmd->cryptoLength = crd->crd_len; -+ -+ if(crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ -+ dprintk(" encrypt \n"); -+ encrypt++; -+ -+ /* handle IV */ -+ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { /* IV from USER */ -+ dprintk("%s,%d: IV from USER (offset %x) \n", __FILE__, __LINE__, crd->crd_inject); -+ cesa_cmd->ivFromUser = 1; -+ ivp = crd->crd_iv; -+ -+ /* -+ * do we have to copy the IV back to the buffer ? -+ */ -+ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { -+ dprintk("%s,%d: copy the IV back to the buffer\n", __FILE__, __LINE__); -+ cesa_cmd->ivOffset = crd->crd_inject; -+ crypto_copy_bits_back(crp->crp_buf, crd->crd_inject, ivp, cesa_ocf_cur_ses->ivlen); -+ } -+ else { -+ dprintk("%s,%d: don't copy the IV back to the buffer \n", __FILE__, __LINE__); -+ p_mbuf_info->numFrags++; -+ p_mbuf_info->mbufSize += cesa_ocf_cur_ses->ivlen; -+ p_mbuf_info->pFrags = p_buf_info; -+ -+ p_buf_info->bufVirtPtr = ivp; -+ p_buf_info->bufSize = cesa_ocf_cur_ses->ivlen; -+ p_buf_info--; -+ -+ /* offsets */ -+ cesa_cmd->ivOffset = 0; -+ cesa_cmd->cryptoOffset += cesa_ocf_cur_ses->ivlen; -+ if(auth) { -+ cesa_cmd->macOffset += cesa_ocf_cur_ses->ivlen; -+ cesa_cmd->digestOffset += cesa_ocf_cur_ses->ivlen; -+ } -+ } -+ } -+ else { /* random IV */ -+ dprintk("%s,%d: random IV \n", __FILE__, __LINE__); -+ cesa_cmd->ivFromUser = 0; -+ -+ /* -+ * do we have to copy the IV back to the buffer ? -+ */ -+ /* in this mode the HAL will always copy the IV */ -+ /* given by the session to the ivOffset */ -+ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { -+ cesa_cmd->ivOffset = crd->crd_inject; -+ } -+ else { -+ /* if IV isn't copy, then how will the user know which IV did we use??? */ -+ printk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ goto p_error; -+ } -+ } -+ } -+ else { /* decrypt */ -+ dprintk(" decrypt \n"); -+ decrypt++; -+ cesa_cmd->sessionId = cesa_ocf_cur_ses->sid_decrypt; -+ -+ /* handle IV */ -+ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { -+ dprintk("%s,%d: IV from USER \n", __FILE__, __LINE__); -+ /* append the IV buf to the mbuf */ -+ cesa_cmd->ivFromUser = 1; -+ p_mbuf_info->numFrags++; -+ p_mbuf_info->mbufSize += cesa_ocf_cur_ses->ivlen; -+ p_mbuf_info->pFrags = p_buf_info; -+ -+ p_buf_info->bufVirtPtr = crd->crd_iv; -+ p_buf_info->bufSize = cesa_ocf_cur_ses->ivlen; -+ p_buf_info--; -+ -+ /* offsets */ -+ cesa_cmd->ivOffset = 0; -+ cesa_cmd->cryptoOffset += cesa_ocf_cur_ses->ivlen; -+ if(auth) { -+ cesa_cmd->macOffset += cesa_ocf_cur_ses->ivlen; -+ cesa_cmd->digestOffset += cesa_ocf_cur_ses->ivlen; -+ } -+ } -+ else { -+ dprintk("%s,%d: IV inside the buffer \n", __FILE__, __LINE__); -+ cesa_cmd->ivFromUser = 0; -+ cesa_cmd->ivOffset = crd->crd_inject; -+ } -+ } -+ -+ } -+ /* Authentication */ -+ else if(crd->crd_alg == cesa_ocf_cur_ses->auth_alg) { -+ dprintk("%s,%d: Authentication \n", __FILE__, __LINE__); -+ auth++; -+ cesa_cmd->macOffset = crd->crd_skip; -+ cesa_cmd->macLength = crd->crd_len; -+ -+ /* digest + mac */ -+ cesa_cmd->digestOffset = crd->crd_inject; -+ } -+ else { -+ printk("%s,%d: Alg isn't supported by this session.\n", __FILE__, __LINE__); -+ goto p_error; -+ } -+ } -+ -+ dprintk("\n"); -+ dprintk("%s,%d: Sending Action: \n", __FILE__, __LINE__); -+ dprintk("%s,%d: IV from user: %d. IV offset %x \n", __FILE__, __LINE__, cesa_cmd->ivFromUser, cesa_cmd->ivOffset); -+ dprintk("%s,%d: crypt offset %x len %x \n", __FILE__, __LINE__, cesa_cmd->cryptoOffset, cesa_cmd->cryptoLength); -+ dprintk("%s,%d: Auth offset %x len %x \n", __FILE__, __LINE__, cesa_cmd->macOffset, cesa_cmd->macLength); -+ dprintk("%s,%d: set digest in offset %x . \n", __FILE__, __LINE__, cesa_cmd->digestOffset); -+ if(debug) { -+ mvCesaDebugMbuf("SRC BUFFER", cesa_cmd->pSrc, 0, cesa_cmd->pSrc->mbufSize); -+ } -+ -+ -+ /* send action to HAL */ -+ spin_lock_irqsave(&cesa_lock, flags); -+ status = mvCesaAction(cesa_cmd); -+ spin_unlock_irqrestore(&cesa_lock, flags); -+ -+ /* action not allowed */ -+ if(status == MV_NOT_ALLOWED) { -+#ifdef CESA_OCF_SPLIT -+ /* if both encrypt and auth try to split */ -+ if(auth && (encrypt || decrypt)) { -+ MV_CESA_COMMAND *cesa_cmd_wa; -+ -+ /* malloc a new cesa process and init it */ -+ cesa_ocf_cmd_wa = kmalloc(sizeof(struct cesa_ocf_process), GFP_ATOMIC); -+ -+ if (cesa_ocf_cmd_wa == NULL) { -+ printk("%s,%d: ENOBUFS \n", __FILE__, __LINE__); -+ goto p_error; -+ } -+ memcpy(cesa_ocf_cmd_wa, cesa_ocf_cmd, sizeof(struct cesa_ocf_process)); -+ cesa_cmd_wa = &cesa_ocf_cmd_wa->cesa_cmd; -+ cesa_cmd_wa->pReqPrv = (void *)cesa_ocf_cmd_wa; -+ cesa_ocf_cmd_wa->need_cb = 0; -+ -+ /* break requests to two operation, first operation completion won't call callback */ -+ if((decrypt) && (cesa_ocf_cur_ses->auth_tn_decrypt)) { -+ cesa_cmd_wa->sessionId = cesa_ocf_cur_ses->frag_wa_auth; -+ cesa_cmd->sessionId = cesa_ocf_cur_ses->frag_wa_decrypt; -+ } -+ else if((decrypt) && !(cesa_ocf_cur_ses->auth_tn_decrypt)) { -+ cesa_cmd_wa->sessionId = cesa_ocf_cur_ses->frag_wa_decrypt; -+ cesa_cmd->sessionId = cesa_ocf_cur_ses->frag_wa_auth; -+ } -+ else if((encrypt) && (cesa_ocf_cur_ses->encrypt_tn_auth)) { -+ cesa_cmd_wa->sessionId = cesa_ocf_cur_ses->frag_wa_encrypt; -+ cesa_cmd->sessionId = cesa_ocf_cur_ses->frag_wa_auth; -+ } -+ else if((encrypt) && !(cesa_ocf_cur_ses->encrypt_tn_auth)){ -+ cesa_cmd_wa->sessionId = cesa_ocf_cur_ses->frag_wa_auth; -+ cesa_cmd->sessionId = cesa_ocf_cur_ses->frag_wa_encrypt; -+ } -+ else { -+ printk("%s,%d: Unsupporterd fragment wa mode \n", __FILE__, __LINE__); -+ goto p_error; -+ } -+ -+ /* send the 2 actions to the HAL */ -+ spin_lock_irqsave(&cesa_lock, flags); -+ status = mvCesaAction(cesa_cmd_wa); -+ spin_unlock_irqrestore(&cesa_lock, flags); -+ -+ if((status != MV_NO_MORE) && (status != MV_OK)) { -+ printk("%s,%d: cesa action failed, status = 0x%x\n", __FILE__, __LINE__, status); -+ goto p_error; -+ } -+ spin_lock_irqsave(&cesa_lock, flags); -+ status = mvCesaAction(cesa_cmd); -+ spin_unlock_irqrestore(&cesa_lock, flags); -+ -+ } -+ /* action not allowed and can't split */ -+ else -+#endif -+ { -+ goto p_error; -+ } -+ } -+ -+ /* Hal Q is full, send again. This should never happen */ -+ if(status == MV_NO_RESOURCE) { -+ printk("%s,%d: cesa no more resources \n", __FILE__, __LINE__); -+ if(cesa_ocf_cmd) -+ kfree(cesa_ocf_cmd); -+ if(cesa_ocf_cmd_wa) -+ kfree(cesa_ocf_cmd_wa); -+ return ERESTART; -+ } -+ else if((status != MV_NO_MORE) && (status != MV_OK)) { -+ printk("%s,%d: cesa action failed, status = 0x%x\n", __FILE__, __LINE__, status); -+ goto p_error; -+ } -+ -+ -+#ifdef CESA_OCF_POLLING -+ cesa_interrupt_polling(); -+#endif -+ cesaTestTraceAdd(5); -+ -+ return 0; -+p_error: -+ crp->crp_etype = EINVAL; -+ if(cesa_ocf_cmd) -+ kfree(cesa_ocf_cmd); -+ if(cesa_ocf_cmd_wa) -+ kfree(cesa_ocf_cmd_wa); -+ return EINVAL; -+} -+ -+/* -+ * cesa callback. -+ */ -+static void -+cesa_callback(unsigned long dummy) -+{ -+ struct cesa_ocf_process *cesa_ocf_cmd = NULL; -+ struct cryptop *crp = NULL; -+ MV_CESA_RESULT result[MV_CESA_MAX_CHAN]; -+ int res_idx = 0,i; -+ MV_STATUS status; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+#ifdef CESA_OCF_TASKLET -+ disable_irq(cesa_device.irq); -+#endif -+ while(MV_TRUE) { -+ -+ /* Get Ready requests */ -+ spin_lock(&cesa_lock); -+ status = mvCesaReadyGet(&result[res_idx]); -+ spin_unlock(&cesa_lock); -+ -+ cesaTestTraceAdd(2); -+ -+ if(status != MV_OK) { -+#ifdef CESA_OCF_POLLING -+ if(status == MV_BUSY) { /* Fragment */ -+ cesa_interrupt_polling(); -+ return; -+ } -+#endif -+ break; -+ } -+ res_idx++; -+ break; -+ } -+ -+ for(i = 0; i < res_idx; i++) { -+ -+ if(!result[i].pReqPrv) { -+ printk("%s,%d: warning private is NULL\n", __FILE__, __LINE__); -+ break; -+ } -+ -+ cesa_ocf_cmd = result[i].pReqPrv; -+ crp = cesa_ocf_cmd->crp; -+ -+ // ignore HMAC error. -+ //if(result->retCode) -+ // crp->crp_etype = EIO; -+ -+#if defined(CESA_OCF_POLLING) -+ if(!cesa_ocf_cmd->need_cb){ -+ cesa_interrupt_polling(); -+ } -+#endif -+ if(cesa_ocf_cmd->need_cb) { -+ if(debug) { -+ mvCesaDebugMbuf("DST BUFFER", cesa_ocf_cmd->cesa_cmd.pDst, 0, cesa_ocf_cmd->cesa_cmd.pDst->mbufSize); -+ } -+ crypto_done(crp); -+ } -+ kfree(cesa_ocf_cmd); -+ } -+#ifdef CESA_OCF_TASKLET -+ enable_irq(cesa_device.irq); -+#endif -+ -+ cesaTestTraceAdd(3); -+ -+ return; -+} -+ -+#ifdef CESA_OCF_POLLING -+static void -+cesa_interrupt_polling(void) -+{ -+ u32 cause; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ /* Read cause register */ -+ do { -+ cause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); -+ cause &= MV_CESA_CAUSE_ACC_DMA_ALL_MASK; -+ -+ } while (cause == 0); -+ -+ /* clear interrupts */ -+ MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); -+ -+ cesa_callback(0); -+ -+ return; -+} -+ -+#endif -+ -+/* -+ * cesa Interrupt polling routine. -+ */ -+static irqreturn_t -+cesa_interrupt_handler(int irq, void *arg) -+{ -+ u32 cause; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ cesaTestTraceAdd(0); -+ -+ /* Read cause register */ -+ cause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); -+ -+ if( (cause & MV_CESA_CAUSE_ACC_DMA_ALL_MASK) == 0) -+ { -+ /* Empty interrupt */ -+ dprintk("%s,%d: cesaTestReadyIsr: cause=0x%x\n", __FILE__, __LINE__, cause); -+ return IRQ_HANDLED; -+ } -+ -+ /* clear interrupts */ -+ MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); -+ -+ cesaTestTraceAdd(1); -+#ifdef CESA_OCF_TASKLET -+ tasklet_hi_schedule(&cesa_ocf_tasklet); -+#else -+ cesa_callback(0); -+#endif -+ return IRQ_HANDLED; -+} -+ -+/* -+ * Open a session. -+ */ -+static int -+/*cesa_ocf_newsession(void *arg, u_int32_t *sid, struct cryptoini *cri)*/ -+cesa_ocf_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) -+{ -+ u32 status = 0, i; -+ u32 count = 0, auth = 0, encrypt =0; -+ struct cesa_ocf_data *cesa_ocf_cur_ses; -+ MV_CESA_OPEN_SESSION cesa_session; -+ MV_CESA_OPEN_SESSION *cesa_ses = &cesa_session; -+ -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid == NULL || cri == NULL) { -+ printk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ /* leave first empty like in other implementations */ -+ for (i = 1; i < CESA_OCF_MAX_SES; i++) { -+ if (cesa_ocf_sessions[i] == NULL) -+ break; -+ } -+ -+ if(i >= CESA_OCF_MAX_SES) { -+ printk("%s,%d: no more sessions \n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ cesa_ocf_sessions[i] = (struct cesa_ocf_data *) kmalloc(sizeof(struct cesa_ocf_data), GFP_ATOMIC); -+ if (cesa_ocf_sessions[i] == NULL) { -+ cesa_ocf_freesession(NULL, i); -+ printk("%s,%d: ENOBUFS \n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ dprintk("%s,%d: new session %d \n", __FILE__, __LINE__, i); -+ -+ *sid = i; -+ cesa_ocf_cur_ses = cesa_ocf_sessions[i]; -+ memset(cesa_ocf_cur_ses, 0, sizeof(struct cesa_ocf_data)); -+ cesa_ocf_cur_ses->sid_encrypt = -1; -+ cesa_ocf_cur_ses->sid_decrypt = -1; -+ cesa_ocf_cur_ses->frag_wa_encrypt = -1; -+ cesa_ocf_cur_ses->frag_wa_decrypt = -1; -+ cesa_ocf_cur_ses->frag_wa_auth = -1; -+ -+ /* init the session */ -+ memset(cesa_ses, 0, sizeof(MV_CESA_OPEN_SESSION)); -+ count = 1; -+ while (cri) { -+ if(count > 2) { -+ printk("%s,%d: don't support more then 2 operations\n", __FILE__, __LINE__); -+ goto error; -+ } -+ switch (cri->cri_alg) { -+ case CRYPTO_AES_CBC: -+ dprintk("%s,%d: (%d) AES CBC \n", __FILE__, __LINE__, count); -+ cesa_ocf_cur_ses->cipher_alg = cri->cri_alg; -+ cesa_ocf_cur_ses->ivlen = MV_CESA_AES_BLOCK_SIZE; -+ cesa_ses->cryptoAlgorithm = MV_CESA_CRYPTO_AES; -+ cesa_ses->cryptoMode = MV_CESA_CRYPTO_CBC; -+ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { -+ printk("%s,%d: CRYPTO key too long.\n", __FILE__, __LINE__); -+ goto error; -+ } -+ memcpy(cesa_ses->cryptoKey, cri->cri_key, cri->cri_klen/8); -+ dprintk("%s,%d: key length %d \n", __FILE__, __LINE__, cri->cri_klen/8); -+ cesa_ses->cryptoKeyLength = cri->cri_klen/8; -+ encrypt += count; -+ break; -+ case CRYPTO_3DES_CBC: -+ dprintk("%s,%d: (%d) 3DES CBC \n", __FILE__, __LINE__, count); -+ cesa_ocf_cur_ses->cipher_alg = cri->cri_alg; -+ cesa_ocf_cur_ses->ivlen = MV_CESA_3DES_BLOCK_SIZE; -+ cesa_ses->cryptoAlgorithm = MV_CESA_CRYPTO_3DES; -+ cesa_ses->cryptoMode = MV_CESA_CRYPTO_CBC; -+ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { -+ printk("%s,%d: CRYPTO key too long.\n", __FILE__, __LINE__); -+ goto error; -+ } -+ memcpy(cesa_ses->cryptoKey, cri->cri_key, cri->cri_klen/8); -+ cesa_ses->cryptoKeyLength = cri->cri_klen/8; -+ encrypt += count; -+ break; -+ case CRYPTO_DES_CBC: -+ dprintk("%s,%d: (%d) DES CBC \n", __FILE__, __LINE__, count); -+ cesa_ocf_cur_ses->cipher_alg = cri->cri_alg; -+ cesa_ocf_cur_ses->ivlen = MV_CESA_DES_BLOCK_SIZE; -+ cesa_ses->cryptoAlgorithm = MV_CESA_CRYPTO_DES; -+ cesa_ses->cryptoMode = MV_CESA_CRYPTO_CBC; -+ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { -+ printk("%s,%d: CRYPTO key too long.\n", __FILE__, __LINE__); -+ goto error; -+ } -+ memcpy(cesa_ses->cryptoKey, cri->cri_key, cri->cri_klen/8); -+ cesa_ses->cryptoKeyLength = cri->cri_klen/8; -+ encrypt += count; -+ break; -+ case CRYPTO_MD5: -+ case CRYPTO_MD5_HMAC: -+ dprintk("%s,%d: (%d) %sMD5 CBC \n", __FILE__, __LINE__, count, (cri->cri_alg != CRYPTO_MD5)? "H-":" "); -+ cesa_ocf_cur_ses->auth_alg = cri->cri_alg; -+ cesa_ocf_cur_ses->digestlen = (cri->cri_alg == CRYPTO_MD5)? MV_CESA_MD5_DIGEST_SIZE : 12; -+ cesa_ses->macMode = (cri->cri_alg == CRYPTO_MD5)? MV_CESA_MAC_MD5 : MV_CESA_MAC_HMAC_MD5; -+ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { -+ printk("%s,%d: MAC key too long. \n", __FILE__, __LINE__); -+ goto error; -+ } -+ cesa_ses->macKeyLength = cri->cri_klen/8; -+ memcpy(cesa_ses->macKey, cri->cri_key, cri->cri_klen/8); -+ cesa_ses->digestSize = cesa_ocf_cur_ses->digestlen; -+ auth += count; -+ break; -+ case CRYPTO_SHA1: -+ case CRYPTO_SHA1_HMAC: -+ dprintk("%s,%d: (%d) %sSHA1 CBC \n", __FILE__, __LINE__, count, (cri->cri_alg != CRYPTO_SHA1)? "H-":" "); -+ cesa_ocf_cur_ses->auth_alg = cri->cri_alg; -+ cesa_ocf_cur_ses->digestlen = (cri->cri_alg == CRYPTO_SHA1)? MV_CESA_SHA1_DIGEST_SIZE : 12; -+ cesa_ses->macMode = (cri->cri_alg == CRYPTO_SHA1)? MV_CESA_MAC_SHA1 : MV_CESA_MAC_HMAC_SHA1; -+ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { -+ printk("%s,%d: MAC key too long. \n", __FILE__, __LINE__); -+ goto error; -+ } -+ cesa_ses->macKeyLength = cri->cri_klen/8; -+ memcpy(cesa_ses->macKey, cri->cri_key, cri->cri_klen/8); -+ cesa_ses->digestSize = cesa_ocf_cur_ses->digestlen; -+ auth += count; -+ break; -+ default: -+ printk("%s,%d: unknown algo 0x%x\n", __FILE__, __LINE__, cri->cri_alg); -+ goto error; -+ } -+ cri = cri->cri_next; -+ count++; -+ } -+ -+ if((encrypt > 2) || (auth > 2)) { -+ printk("%s,%d: session mode is not supported.\n", __FILE__, __LINE__); -+ goto error; -+ } -+ /* create new sessions in HAL */ -+ if(encrypt) { -+ cesa_ses->operation = MV_CESA_CRYPTO_ONLY; -+ /* encrypt session */ -+ if(auth == 1) { -+ cesa_ses->operation = MV_CESA_MAC_THEN_CRYPTO; -+ } -+ else if(auth == 2) { -+ cesa_ses->operation = MV_CESA_CRYPTO_THEN_MAC; -+ cesa_ocf_cur_ses->encrypt_tn_auth = 1; -+ } -+ else { -+ cesa_ses->operation = MV_CESA_CRYPTO_ONLY; -+ } -+ cesa_ses->direction = MV_CESA_DIR_ENCODE; -+ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->sid_encrypt); -+ if(status != MV_OK) { -+ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); -+ goto error; -+ } -+ /* decrypt session */ -+ if( cesa_ses->operation == MV_CESA_MAC_THEN_CRYPTO ) { -+ cesa_ses->operation = MV_CESA_CRYPTO_THEN_MAC; -+ } -+ else if( cesa_ses->operation == MV_CESA_CRYPTO_THEN_MAC ) { -+ cesa_ses->operation = MV_CESA_MAC_THEN_CRYPTO; -+ } -+ cesa_ses->direction = MV_CESA_DIR_DECODE; -+ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->sid_decrypt); -+ if(status != MV_OK) { -+ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); -+ goto error; -+ } -+ -+ /* preapre one action sessions for case we will need to split an action */ -+#ifdef CESA_OCF_SPLIT -+ if(( cesa_ses->operation == MV_CESA_MAC_THEN_CRYPTO ) || -+ ( cesa_ses->operation == MV_CESA_CRYPTO_THEN_MAC )) { -+ /* open one session for encode and one for decode */ -+ cesa_ses->operation = MV_CESA_CRYPTO_ONLY; -+ cesa_ses->direction = MV_CESA_DIR_ENCODE; -+ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->frag_wa_encrypt); -+ if(status != MV_OK) { -+ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); -+ goto error; -+ } -+ -+ cesa_ses->direction = MV_CESA_DIR_DECODE; -+ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->frag_wa_decrypt); -+ if(status != MV_OK) { -+ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); -+ goto error; -+ } -+ /* open one session for auth */ -+ cesa_ses->operation = MV_CESA_MAC_ONLY; -+ cesa_ses->direction = MV_CESA_DIR_ENCODE; -+ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->frag_wa_auth); -+ if(status != MV_OK) { -+ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); -+ goto error; -+ } -+ } -+#endif -+ } -+ else { /* only auth */ -+ cesa_ses->operation = MV_CESA_MAC_ONLY; -+ cesa_ses->direction = MV_CESA_DIR_ENCODE; -+ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->sid_encrypt); -+ if(status != MV_OK) { -+ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); -+ goto error; -+ } -+ } -+ -+ return 0; -+error: -+ cesa_ocf_freesession(NULL, *sid); -+ return EINVAL; -+ -+} -+ -+ -+/* -+ * Free a session. -+ */ -+static int -+cesa_ocf_freesession(device_t dev, u_int64_t tid) -+{ -+ struct cesa_ocf_data *cesa_ocf_cur_ses; -+ u_int32_t sid = CRYPTO_SESID2LID(tid); -+ //unsigned long flags; -+ -+ dprintk("%s() %d \n", __FUNCTION__, sid); -+ if ( (sid >= CESA_OCF_MAX_SES) || (cesa_ocf_sessions[sid] == NULL) ) { -+ printk("%s,%d: EINVAL can't free session %d \n", __FILE__, __LINE__, sid); -+ return(EINVAL); -+ } -+ -+ /* Silently accept and return */ -+ if (sid == 0) -+ return(0); -+ -+ /* release session from HAL */ -+ cesa_ocf_cur_ses = cesa_ocf_sessions[sid]; -+ if (cesa_ocf_cur_ses->sid_encrypt != -1) { -+ mvCesaSessionClose(cesa_ocf_cur_ses->sid_encrypt); -+ } -+ if (cesa_ocf_cur_ses->sid_decrypt != -1) { -+ mvCesaSessionClose(cesa_ocf_cur_ses->sid_decrypt); -+ } -+ if (cesa_ocf_cur_ses->frag_wa_encrypt != -1) { -+ mvCesaSessionClose(cesa_ocf_cur_ses->frag_wa_encrypt); -+ } -+ if (cesa_ocf_cur_ses->frag_wa_decrypt != -1) { -+ mvCesaSessionClose(cesa_ocf_cur_ses->frag_wa_decrypt); -+ } -+ if (cesa_ocf_cur_ses->frag_wa_auth != -1) { -+ mvCesaSessionClose(cesa_ocf_cur_ses->frag_wa_auth); -+ } -+ -+ kfree(cesa_ocf_cur_ses); -+ cesa_ocf_sessions[sid] = NULL; -+ -+ return 0; -+} -+ -+ -+/* TDMA Window setup */ -+ -+static void __init -+setup_tdma_mbus_windows(struct cesa_dev *dev) -+{ -+ int i; -+ -+ for (i = 0; i < 4; i++) { -+ writel(0, dev->reg + WINDOW_BASE(i)); -+ writel(0, dev->reg + WINDOW_CTRL(i)); -+ } -+ -+ for (i = 0; i < dev->plat_data->dram->num_cs; i++) { -+ struct mbus_dram_window *cs = dev->plat_data->dram->cs + i; -+ writel( -+ ((cs->size - 1) & 0xffff0000) | -+ (cs->mbus_attr << 8) | -+ (dev->plat_data->dram->mbus_dram_target_id << 4) | 1, -+ dev->reg + WINDOW_CTRL(i) -+ ); -+ writel(cs->base, dev->reg + WINDOW_BASE(i)); -+ } -+} -+ -+/* -+ * our driver startup and shutdown routines -+ */ -+static int -+mv_cesa_ocf_init(struct platform_device *pdev) -+{ -+#if defined(CONFIG_MV78200) || defined(CONFIG_MV632X) -+ if (MV_FALSE == mvSocUnitIsMappedToThisCpu(CESA)) -+ { -+ dprintk("CESA is not mapped to this CPU\n"); -+ return -ENODEV; -+ } -+#endif -+ -+ dprintk("%s\n", __FUNCTION__); -+ memset(&mv_cesa_dev, 0, sizeof(mv_cesa_dev)); -+ softc_device_init(&mv_cesa_dev, "MV CESA", 0, mv_cesa_methods); -+ cesa_ocf_id = crypto_get_driverid(softc_get_device(&mv_cesa_dev),CRYPTOCAP_F_HARDWARE); -+ -+ if (cesa_ocf_id < 0) -+ panic("MV CESA crypto device cannot initialize!"); -+ -+ dprintk("%s,%d: cesa ocf device id is %d \n", __FILE__, __LINE__, cesa_ocf_id); -+ -+ /* CESA unit is auto power on off */ -+#if 0 -+ if (MV_FALSE == mvCtrlPwrClckGet(CESA_UNIT_ID,0)) -+ { -+ printk("\nWarning CESA %d is Powered Off\n",0); -+ return EINVAL; -+ } -+#endif -+ -+ memset(&cesa_device, 0, sizeof(struct cesa_dev)); -+ /* Get the IRQ, and crypto memory regions */ -+ { -+ struct resource *res; -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram"); -+ -+ if (!res) -+ return -ENXIO; -+ -+ cesa_device.sram = ioremap(res->start, res->end - res->start + 1); -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); -+ -+ if (!res) { -+ iounmap(cesa_device.sram); -+ return -ENXIO; -+ } -+ cesa_device.reg = ioremap(res->start, res->end - res->start + 1); -+ cesa_device.irq = platform_get_irq(pdev, 0); -+ cesa_device.plat_data = pdev->dev.platform_data; -+ setup_tdma_mbus_windows(&cesa_device); -+ -+ } -+ -+ -+ if( MV_OK != mvCesaInit(CESA_OCF_MAX_SES*5, CESA_Q_SIZE, cesa_device.reg, -+ NULL) ) { -+ printk("%s,%d: mvCesaInit Failed. \n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ /* clear and unmask Int */ -+ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); -+#ifndef CESA_OCF_POLLING -+ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, MV_CESA_CAUSE_ACC_DMA_MASK); -+#endif -+#ifdef CESA_OCF_TASKLET -+ tasklet_init(&cesa_ocf_tasklet, cesa_callback, (unsigned int) 0); -+#endif -+ /* register interrupt */ -+ if( request_irq( cesa_device.irq, cesa_interrupt_handler, -+ (IRQF_DISABLED) , "cesa", &cesa_ocf_id) < 0) { -+ printk("%s,%d: cannot assign irq %x\n", __FILE__, __LINE__, cesa_device.reg); -+ return EINVAL; -+ } -+ -+ -+ memset(cesa_ocf_sessions, 0, sizeof(struct cesa_ocf_data *) * CESA_OCF_MAX_SES); -+ -+#define REGISTER(alg) \ -+ crypto_register(cesa_ocf_id, alg, 0,0) -+ REGISTER(CRYPTO_AES_CBC); -+ REGISTER(CRYPTO_DES_CBC); -+ REGISTER(CRYPTO_3DES_CBC); -+ REGISTER(CRYPTO_MD5); -+ REGISTER(CRYPTO_MD5_HMAC); -+ REGISTER(CRYPTO_SHA1); -+ REGISTER(CRYPTO_SHA1_HMAC); -+#undef REGISTER -+ -+ return 0; -+} -+ -+static void -+mv_cesa_ocf_exit(struct platform_device *pdev) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ crypto_unregister_all(cesa_ocf_id); -+ cesa_ocf_id = -1; -+ iounmap(cesa_device.reg); -+ iounmap(cesa_device.sram); -+ free_irq(cesa_device.irq, NULL); -+ -+ /* mask and clear Int */ -+ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, 0); -+ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); -+ -+ -+ if( MV_OK != mvCesaFinish() ) { -+ printk("%s,%d: mvCesaFinish Failed. \n", __FILE__, __LINE__); -+ return; -+ } -+} -+ -+ -+void cesa_ocf_debug(void) -+{ -+ -+#ifdef CESA_OCF_TRACE_DEBUG -+ { -+ int i, j; -+ j = cesaTestTraceIdx; -+ mvOsPrintf("No Type rCause iCause Proc Isr Res Time pReady pProc pEmpty\n"); -+ for(i=0; i= _1G) -+ { -+ mvOsOutput("%3dGB ", size / _1G); -+ size %= _1G; -+ if(size) -+ mvOsOutput("+"); -+ } -+ if(size >= _1M ) -+ { -+ mvOsOutput("%3dMB ", size / _1M); -+ size %= _1M; -+ if(size) -+ mvOsOutput("+"); -+ } -+ if(size >= _1K) -+ { -+ mvOsOutput("%3dKB ", size / _1K); -+ size %= _1K; -+ if(size) -+ mvOsOutput("+"); -+ } -+ if(size > 0) -+ { -+ mvOsOutput("%3dB ", size); -+ } -+} -+ -+/******************************************************************************* -+* mvHexToBin - Convert hex to binary -+* -+* DESCRIPTION: -+* This function Convert hex to binary. -+* -+* INPUT: -+* pHexStr - hex buffer pointer. -+* size - Size to convert. -+* -+* OUTPUT: -+* pBin - Binary buffer pointer. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvHexToBin(const char* pHexStr, MV_U8* pBin, int size) -+{ -+ int j, i; -+ char tmp[3]; -+ MV_U8 byte; -+ -+ for(j=0, i=0; j> 1; -+ result++; -+ } -+ return result; -+} -+ -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/common/mvCommon.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/common/mvCommon.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/common/mvCommon.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/common/mvCommon.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,308 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+ -+#ifndef __INCmvCommonh -+#define __INCmvCommonh -+ -+#include "mvTypes.h" -+ -+/* Swap tool */ -+ -+/* 16bit nibble swap. For example 0x1234 -> 0x2143 */ -+#define MV_NIBBLE_SWAP_16BIT(X) (((X&0xf) << 4) | \ -+ ((X&0xf0) >> 4) | \ -+ ((X&0xf00) << 4) | \ -+ ((X&0xf000) >> 4)) -+ -+/* 32bit nibble swap. For example 0x12345678 -> 0x21436587 */ -+#define MV_NIBBLE_SWAP_32BIT(X) (((X&0xf) << 4) | \ -+ ((X&0xf0) >> 4) | \ -+ ((X&0xf00) << 4) | \ -+ ((X&0xf000) >> 4) | \ -+ ((X&0xf0000) << 4) | \ -+ ((X&0xf00000) >> 4) | \ -+ ((X&0xf000000) << 4) | \ -+ ((X&0xf0000000) >> 4)) -+ -+/* 16bit byte swap. For example 0x1122 -> 0x2211 */ -+#define MV_BYTE_SWAP_16BIT(X) ((((X)&0xff)<<8) | (((X)&0xff00)>>8)) -+ -+/* 32bit byte swap. For example 0x11223344 -> 0x44332211 */ -+#define MV_BYTE_SWAP_32BIT(X) ((((X)&0xff)<<24) | \ -+ (((X)&0xff00)<<8) | \ -+ (((X)&0xff0000)>>8) | \ -+ (((X)&0xff000000)>>24)) -+ -+/* 64bit byte swap. For example 0x11223344.55667788 -> 0x88776655.44332211 */ -+#define MV_BYTE_SWAP_64BIT(X) ((l64) ((((X)&0xffULL)<<56) | \ -+ (((X)&0xff00ULL)<<40) | \ -+ (((X)&0xff0000ULL)<<24) | \ -+ (((X)&0xff000000ULL)<<8) | \ -+ (((X)&0xff00000000ULL)>>8) | \ -+ (((X)&0xff0000000000ULL)>>24) | \ -+ (((X)&0xff000000000000ULL)>>40) | \ -+ (((X)&0xff00000000000000ULL)>>56))) -+ -+/* Endianess macros. */ -+#if defined(MV_CPU_LE) -+ #define MV_16BIT_LE(X) (X) -+ #define MV_32BIT_LE(X) (X) -+ #define MV_64BIT_LE(X) (X) -+ #define MV_16BIT_BE(X) MV_BYTE_SWAP_16BIT(X) -+ #define MV_32BIT_BE(X) MV_BYTE_SWAP_32BIT(X) -+ #define MV_64BIT_BE(X) MV_BYTE_SWAP_64BIT(X) -+#elif defined(MV_CPU_BE) -+ #define MV_16BIT_LE(X) MV_BYTE_SWAP_16BIT(X) -+ #define MV_32BIT_LE(X) MV_BYTE_SWAP_32BIT(X) -+ #define MV_64BIT_LE(X) MV_BYTE_SWAP_64BIT(X) -+ #define MV_16BIT_BE(X) (X) -+ #define MV_32BIT_BE(X) (X) -+ #define MV_64BIT_BE(X) (X) -+#else -+ #error "CPU endianess isn't defined!\n" -+#endif -+ -+ -+/* Bit field definitions */ -+#define NO_BIT 0x00000000 -+#define BIT0 0x00000001 -+#define BIT1 0x00000002 -+#define BIT2 0x00000004 -+#define BIT3 0x00000008 -+#define BIT4 0x00000010 -+#define BIT5 0x00000020 -+#define BIT6 0x00000040 -+#define BIT7 0x00000080 -+#define BIT8 0x00000100 -+#define BIT9 0x00000200 -+#define BIT10 0x00000400 -+#define BIT11 0x00000800 -+#define BIT12 0x00001000 -+#define BIT13 0x00002000 -+#define BIT14 0x00004000 -+#define BIT15 0x00008000 -+#define BIT16 0x00010000 -+#define BIT17 0x00020000 -+#define BIT18 0x00040000 -+#define BIT19 0x00080000 -+#define BIT20 0x00100000 -+#define BIT21 0x00200000 -+#define BIT22 0x00400000 -+#define BIT23 0x00800000 -+#define BIT24 0x01000000 -+#define BIT25 0x02000000 -+#define BIT26 0x04000000 -+#define BIT27 0x08000000 -+#define BIT28 0x10000000 -+#define BIT29 0x20000000 -+#define BIT30 0x40000000 -+#define BIT31 0x80000000 -+ -+/* Handy sizes */ -+#define _1K 0x00000400 -+#define _2K 0x00000800 -+#define _4K 0x00001000 -+#define _8K 0x00002000 -+#define _16K 0x00004000 -+#define _32K 0x00008000 -+#define _64K 0x00010000 -+#define _128K 0x00020000 -+#define _256K 0x00040000 -+#define _512K 0x00080000 -+ -+#define _1M 0x00100000 -+#define _2M 0x00200000 -+#define _4M 0x00400000 -+#define _8M 0x00800000 -+#define _16M 0x01000000 -+#define _32M 0x02000000 -+#define _64M 0x04000000 -+#define _128M 0x08000000 -+#define _256M 0x10000000 -+#define _512M 0x20000000 -+ -+#define _1G 0x40000000 -+#define _2G 0x80000000 -+ -+/* Tclock and Sys clock define */ -+#define _100MHz 100000000 -+#define _125MHz 125000000 -+#define _133MHz 133333334 -+#define _150MHz 150000000 -+#define _160MHz 160000000 -+#define _166MHz 166666667 -+#define _175MHz 175000000 -+#define _178MHz 178000000 -+#define _183MHz 183333334 -+#define _187MHz 187000000 -+#define _192MHz 192000000 -+#define _194MHz 194000000 -+#define _200MHz 200000000 -+#define _233MHz 233333334 -+#define _250MHz 250000000 -+#define _266MHz 266666667 -+#define _300MHz 300000000 -+ -+/* For better address window table readability */ -+#define EN MV_TRUE -+#define DIS MV_FALSE -+#define N_A -1 /* Not applicable */ -+ -+/* Cache configuration options for memory (DRAM, SRAM, ... ) */ -+ -+/* Memory uncached, HW or SW cache coherency is not needed */ -+#define MV_UNCACHED 0 -+/* Memory cached, HW cache coherency supported in WriteThrough mode */ -+#define MV_CACHE_COHER_HW_WT 1 -+/* Memory cached, HW cache coherency supported in WriteBack mode */ -+#define MV_CACHE_COHER_HW_WB 2 -+/* Memory cached, No HW cache coherency, Cache coherency must be in SW */ -+#define MV_CACHE_COHER_SW 3 -+ -+ -+/* Macro for testing aligment. Positive if number is NOT aligned */ -+#define MV_IS_NOT_ALIGN(number, align) ((number) & ((align) - 1)) -+ -+/* Macro for alignment up. For example, MV_ALIGN_UP(0x0330, 0x20) = 0x0340 */ -+#define MV_ALIGN_UP(number, align) \ -+(((number) & ((align) - 1)) ? (((number) + (align)) & ~((align)-1)) : (number)) -+ -+/* Macro for alignment down. For example, MV_ALIGN_UP(0x0330, 0x20) = 0x0320 */ -+#define MV_ALIGN_DOWN(number, align) ((number) & ~((align)-1)) -+ -+/* This macro returns absolute value */ -+#define MV_ABS(number) (((int)(number) < 0) ? -(int)(number) : (int)(number)) -+ -+ -+/* Bit fields manipulation macros */ -+ -+/* An integer word which its 'x' bit is set */ -+#define MV_BIT_MASK(bitNum) (1 << (bitNum) ) -+ -+/* Checks wheter bit 'x' in integer word is set */ -+#define MV_BIT_CHECK(word, bitNum) ( (word) & MV_BIT_MASK(bitNum) ) -+ -+/* Clear (reset) bit 'x' in integer word (RMW - Read-Modify-Write) */ -+#define MV_BIT_CLEAR(word, bitNum) ( (word) &= ~(MV_BIT_MASK(bitNum)) ) -+ -+/* Set bit 'x' in integer word (RMW) */ -+#define MV_BIT_SET(word, bitNum) ( (word) |= MV_BIT_MASK(bitNum) ) -+ -+/* Invert bit 'x' in integer word (RMW) */ -+#define MV_BIT_INV(word, bitNum) ( (word) ^= MV_BIT_MASK(bitNum) ) -+ -+/* Get the min between 'a' or 'b' */ -+#define MV_MIN(a,b) (((a) < (b)) ? (a) : (b)) -+ -+/* Get the max between 'a' or 'b' */ -+#define MV_MAX(a,b) (((a) < (b)) ? (b) : (a)) -+ -+/* Temporary */ -+#define mvOsDivide(num, div) \ -+({ \ -+ int i=0, rem=(num); \ -+ \ -+ while(rem >= (div)) \ -+ { \ -+ rem -= (div); \ -+ i++; \ -+ } \ -+ (i); \ -+}) -+ -+/* Temporary */ -+#define mvOsReminder(num, div) \ -+({ \ -+ int rem = (num); \ -+ \ -+ while(rem >= (div)) \ -+ rem -= (div); \ -+ (rem); \ -+}) -+ -+#define MV_IP_QUAD(ipAddr) ((ipAddr >> 24) & 0xFF), ((ipAddr >> 16) & 0xFF), \ -+ ((ipAddr >> 8) & 0xFF), ((ipAddr >> 0) & 0xFF) -+ -+#define MV_IS_POWER_OF_2(num) ((num != 0) && ((num & (num - 1)) == 0)) -+ -+#ifndef MV_ASMLANGUAGE -+/* mvCommon API list */ -+ -+MV_VOID mvHexToBin(const char* pHexStr, MV_U8* pBin, int size); -+void mvAsciiToHex(const char* asciiStr, char* hexStr); -+void mvBinToHex(const MV_U8* bin, char* hexStr, int size); -+void mvBinToAscii(const MV_U8* bin, char* asciiStr, int size); -+ -+MV_STATUS mvMacStrToHex(const char* macStr, MV_U8* macHex); -+MV_STATUS mvMacHexToStr(MV_U8* macHex, char* macStr); -+void mvSizePrint(MV_U32); -+ -+MV_U32 mvLog2(MV_U32 num); -+ -+#endif /* MV_ASMLANGUAGE */ -+ -+ -+#endif /* __INCmvCommonh */ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/common/mvDebug.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/common/mvDebug.c ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/common/mvDebug.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/common/mvDebug.c 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,326 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+ -+/* includes */ -+#include "mvOs.h" -+#include "mv802_3.h" -+#include "mvCommon.h" -+#include "mvDebug.h" -+ -+/* Global variables effect on behave MV_DEBUG_PRINT and MV_DEBUG_CODE macros -+ * mvDebug - map of bits (one for each module) bit=1 means enable -+ * debug code and messages for this module -+ * mvModuleDebug - array of 32 bits varables one for each module -+ */ -+MV_U32 mvDebug = 0; -+MV_U32 mvDebugModules[MV_MODULE_MAX]; -+ -+/* Init mvModuleDebug array to default values */ -+void mvDebugInit(void) -+{ -+ int bit; -+ -+ mvDebug = 0; -+ for(bit=0; bit 0) -+ { -+ mvOsPrintf("%08x: ", memAddr); -+ i = 0; -+ /* 32 bytes in the line */ -+ while(i < 32) -+ { -+ if(memAddr >= (MV_U32)addr) -+ { -+ switch(access) -+ { -+ case 1: -+ if( memAddr == CPU_PHY_MEM(memAddr) ) -+ { -+ mvOsPrintf("%02x ", MV_MEMIO8_READ(memAddr)); -+ } -+ else -+ { -+ mvOsPrintf("%02x ", *((MV_U8*)memAddr)); -+ } -+ break; -+ -+ case 2: -+ if( memAddr == CPU_PHY_MEM(memAddr) ) -+ { -+ mvOsPrintf("%04x ", MV_MEMIO16_READ(memAddr)); -+ } -+ else -+ { -+ mvOsPrintf("%04x ", *((MV_U16*)memAddr)); -+ } -+ break; -+ -+ case 4: -+ if( memAddr == CPU_PHY_MEM(memAddr) ) -+ { -+ mvOsPrintf("%08x ", MV_MEMIO32_READ(memAddr)); -+ } -+ else -+ { -+ mvOsPrintf("%08x ", *((MV_U32*)memAddr)); -+ } -+ break; -+ } -+ } -+ else -+ { -+ for(j=0; j<(access*2+1); j++) -+ mvOsPrintf(" "); -+ } -+ i += access; -+ memAddr += access; -+ size -= access; -+ if(size <= 0) -+ break; -+ } -+ mvOsPrintf("\n"); -+ } -+} -+ -+void mvDebugPrintBufInfo(BUF_INFO* pBufInfo, int size, int access) -+{ -+ if(pBufInfo == NULL) -+ { -+ mvOsPrintf("\n!!! pBufInfo = NULL\n"); -+ return; -+ } -+ mvOsPrintf("\n*** pBufInfo=0x%x, cmdSts=0x%08x, pBuf=0x%x, bufSize=%d\n", -+ (unsigned int)pBufInfo, -+ (unsigned int)pBufInfo->cmdSts, -+ (unsigned int)pBufInfo->pBuff, -+ (unsigned int)pBufInfo->bufSize); -+ mvOsPrintf("pData=0x%x, byteCnt=%d, pNext=0x%x, uInfo1=0x%x, uInfo2=0x%x\n", -+ (unsigned int)pBufInfo->pData, -+ (unsigned int)pBufInfo->byteCnt, -+ (unsigned int)pBufInfo->pNextBufInfo, -+ (unsigned int)pBufInfo->userInfo1, -+ (unsigned int)pBufInfo->userInfo2); -+ if(pBufInfo->pData != NULL) -+ { -+ if(size > pBufInfo->byteCnt) -+ size = pBufInfo->byteCnt; -+ mvDebugMemDump(pBufInfo->pData, size, access); -+ } -+} -+ -+void mvDebugPrintPktInfo(MV_PKT_INFO* pPktInfo, int size, int access) -+{ -+ int frag, len; -+ -+ if(pPktInfo == NULL) -+ { -+ mvOsPrintf("\n!!! pPktInfo = NULL\n"); -+ return; -+ } -+ mvOsPrintf("\npPkt=%p, stat=0x%08x, numFr=%d, size=%d, pFr=%p, osInfo=0x%lx\n", -+ pPktInfo, pPktInfo->status, pPktInfo->numFrags, pPktInfo->pktSize, -+ pPktInfo->pFrags, pPktInfo->osInfo); -+ -+ for(frag=0; fragnumFrags; frag++) -+ { -+ mvOsPrintf("#%2d. bufVirt=%p, bufSize=%d\n", -+ frag, pPktInfo->pFrags[frag].bufVirtPtr, -+ pPktInfo->pFrags[frag].bufSize); -+ if(size > 0) -+ { -+ len = MV_MIN((int)pPktInfo->pFrags[frag].bufSize, size); -+ mvDebugMemDump(pPktInfo->pFrags[frag].bufVirtPtr, len, access); -+ size -= len; -+ } -+ } -+ -+} -+ -+void mvDebugPrintIpAddr(MV_U32 ipAddr) -+{ -+ mvOsPrintf("%d.%d.%d.%d", ((ipAddr >> 24) & 0xFF), ((ipAddr >> 16) & 0xFF), -+ ((ipAddr >> 8) & 0xFF), ((ipAddr >> 0) & 0xFF)); -+} -+ -+void mvDebugPrintMacAddr(const MV_U8* pMacAddr) -+{ -+ int i; -+ -+ mvOsPrintf("%02x", (unsigned int)pMacAddr[0]); -+ for(i=1; ibegin = 0; -+ pTimeEntry->count = count; -+ pTimeEntry->end = 0; -+ pTimeEntry->left = pTimeEntry->count; -+ pTimeEntry->total = 0; -+ pTimeEntry->min = 0xFFFFFFFF; -+ pTimeEntry->max = 0x0; -+ strncpy(pTimeEntry->name, pName, sizeof(pTimeEntry->name)-1); -+ pTimeEntry->name[sizeof(pTimeEntry->name)-1] = '\0'; -+} -+ -+/* Print out MV_DEBUG_TIMES entry */ -+void mvDebugPrintTimeEntry(MV_DEBUG_TIMES* pTimeEntry, MV_BOOL isTitle) -+{ -+ int num; -+ -+ if(isTitle == MV_TRUE) -+ mvOsPrintf("Event NumOfEvents TotalTime Average Min Max\n"); -+ -+ num = pTimeEntry->count-pTimeEntry->left; -+ if(num > 0) -+ { -+ mvOsPrintf("%-11s %6u 0x%08lx %6lu %6lu %6lu\n", -+ pTimeEntry->name, num, pTimeEntry->total, pTimeEntry->total/num, -+ pTimeEntry->min, pTimeEntry->max); -+ } -+} -+ -+/* Update MV_DEBUG_TIMES entry */ -+void mvDebugUpdateTimeEntry(MV_DEBUG_TIMES* pTimeEntry) -+{ -+ MV_U32 delta; -+ -+ if(pTimeEntry->left > 0) -+ { -+ if(pTimeEntry->end <= pTimeEntry->begin) -+ { -+ delta = pTimeEntry->begin - pTimeEntry->end; -+ } -+ else -+ { -+ delta = ((MV_U32)0x10000 - pTimeEntry->end) + pTimeEntry->begin; -+ } -+ pTimeEntry->total += delta; -+ -+ if(delta < pTimeEntry->min) -+ pTimeEntry->min = delta; -+ -+ if(delta > pTimeEntry->max) -+ pTimeEntry->max = delta; -+ -+ pTimeEntry->left--; -+ } -+} -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/common/mvDebug.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/common/mvDebug.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/common/mvDebug.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/common/mvDebug.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,178 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+ -+#ifndef __INCmvDebugh -+#define __INCmvDebugh -+ -+/* includes */ -+#include "mvTypes.h" -+ -+typedef enum -+{ -+ MV_MODULE_INVALID = -1, -+ MV_MODULE_ETH = 0, -+ MV_MODULE_IDMA, -+ MV_MODULE_XOR, -+ MV_MODULE_TWASI, -+ MV_MODULE_MGI, -+ MV_MODULE_USB, -+ MV_MODULE_CESA, -+ -+ MV_MODULE_MAX -+}MV_MODULE_ID; -+ -+/* Define generic flags useful for most of modules */ -+#define MV_DEBUG_FLAG_ALL (0) -+#define MV_DEBUG_FLAG_INIT (1 << 0) -+#define MV_DEBUG_FLAG_RX (1 << 1) -+#define MV_DEBUG_FLAG_TX (1 << 2) -+#define MV_DEBUG_FLAG_ERR (1 << 3) -+#define MV_DEBUG_FLAG_TRACE (1 << 4) -+#define MV_DEBUG_FLAG_DUMP (1 << 5) -+#define MV_DEBUG_FLAG_CACHE (1 << 6) -+#define MV_DEBUG_FLAG_IOCTL (1 << 7) -+#define MV_DEBUG_FLAG_STATS (1 << 8) -+ -+extern MV_U32 mvDebug; -+extern MV_U32 mvDebugModules[MV_MODULE_MAX]; -+ -+#ifdef MV_DEBUG -+# define MV_DEBUG_PRINT(module, flags, msg) mvOsPrintf msg -+# define MV_DEBUG_CODE(module, flags, code) code -+#elif defined(MV_RT_DEBUG) -+# define MV_DEBUG_PRINT(module, flags, msg) \ -+ if( (mvDebug & (1<<(module))) && \ -+ ((mvDebugModules[(module)] & (flags)) == (flags)) ) \ -+ mvOsPrintf msg -+# define MV_DEBUG_CODE(module, flags, code) \ -+ if( (mvDebug & (1<<(module))) && \ -+ ((mvDebugModules[(module)] & (flags)) == (flags)) ) \ -+ code -+#else -+# define MV_DEBUG_PRINT(module, flags, msg) -+# define MV_DEBUG_CODE(module, flags, code) -+#endif -+ -+ -+ -+/* typedefs */ -+ -+/* time measurement structure used to check how much time pass between -+ * two points -+ */ -+typedef struct { -+ char name[20]; /* name of the entry */ -+ unsigned long begin; /* time measured on begin point */ -+ unsigned long end; /* time measured on end point */ -+ unsigned long total; /* Accumulated time */ -+ unsigned long left; /* The rest measurement actions */ -+ unsigned long count; /* Maximum measurement actions */ -+ unsigned long min; /* Minimum time from begin to end */ -+ unsigned long max; /* Maximum time from begin to end */ -+} MV_DEBUG_TIMES; -+ -+ -+/* mvDebug.h API list */ -+ -+/****** Error Recording ******/ -+ -+/* Dump memory in specific format: -+ * address: X1X1X1X1 X2X2X2X2 ... X8X8X8X8 -+ */ -+void mvDebugMemDump(void* addr, int size, int access); -+ -+void mvDebugPrintBufInfo(BUF_INFO* pBufInfo, int size, int access); -+ -+void mvDebugPrintPktInfo(MV_PKT_INFO* pPktInfo, int size, int access); -+ -+void mvDebugPrintIpAddr(MV_U32 ipAddr); -+ -+void mvDebugPrintMacAddr(const MV_U8* pMacAddr); -+ -+/**** There are three functions deals with MV_DEBUG_TIMES structure ****/ -+ -+/* Reset MV_DEBUG_TIMES entry */ -+void mvDebugResetTimeEntry(MV_DEBUG_TIMES* pTimeEntry, int count, char* name); -+ -+/* Update MV_DEBUG_TIMES entry */ -+void mvDebugUpdateTimeEntry(MV_DEBUG_TIMES* pTimeEntry); -+ -+/* Print out MV_DEBUG_TIMES entry */ -+void mvDebugPrintTimeEntry(MV_DEBUG_TIMES* pTimeEntry, MV_BOOL isTitle); -+ -+ -+/******** General ***********/ -+ -+/* Change value of mvDebugPrint global variable */ -+ -+void mvDebugInit(void); -+void mvDebugModuleEnable(MV_MODULE_ID module, MV_BOOL isEnable); -+void mvDebugModuleSetFlags(MV_MODULE_ID module, MV_U32 flags); -+void mvDebugModuleClearFlags(MV_MODULE_ID module, MV_U32 flags); -+ -+ -+#endif /* __INCmvDebug.h */ -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,225 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvDeviceIdh -+#define __INCmvDeviceIdh -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* defines */ -+#define MARVELL_VEN_ID 0x11ab -+ -+/* Disco-3 */ -+#define MV64460_DEV_ID 0x6480 -+#define MV64460B_DEV_ID 0x6485 -+#define MV64430_DEV_ID 0x6420 -+ -+/* Disco-5 */ -+#define MV64560_DEV_ID 0x6450 -+ -+/* Disco-6 */ -+#define MV64660_DEV_ID 0x6460 -+ -+/* Orion */ -+#define MV_1181_DEV_ID 0x1181 -+#define MV_5181_DEV_ID 0x5181 -+#define MV_5281_DEV_ID 0x5281 -+#define MV_5182_DEV_ID 0x5182 -+#define MV_8660_DEV_ID 0x8660 -+#define MV_5180_DEV_ID 0x5180 -+#define MV_5082_DEV_ID 0x5082 -+#define MV_1281_DEV_ID 0x1281 -+#define MV_6082_DEV_ID 0x6082 -+#define MV_6183_DEV_ID 0x6183 -+#define MV_6183L_DEV_ID 0x6083 -+ -+#define MV_5281_D0_REV 0x4 -+#define MV_5281_D0_ID ((MV_5281_DEV_ID << 16) | MV_5281_D0_REV) -+#define MV_5281_D0_NAME "88F5281 D0" -+ -+#define MV_5281_D1_REV 0x5 -+#define MV_5281_D1_ID ((MV_5281_DEV_ID << 16) | MV_5281_D1_REV) -+#define MV_5281_D1_NAME "88F5281 D1" -+ -+#define MV_5281_D2_REV 0x6 -+#define MV_5281_D2_ID ((MV_5281_DEV_ID << 16) | MV_5281_D2_REV) -+#define MV_5281_D2_NAME "88F5281 D2" -+ -+ -+#define MV_5181L_A0_REV 0x8 /* need for PCIE Er */ -+#define MV_5181_A1_REV 0x1 /* for USB Er ..*/ -+#define MV_5181_B0_REV 0x2 -+#define MV_5181_B1_REV 0x3 -+#define MV_5182_A1_REV 0x1 -+#define MV_5180N_B1_REV 0x3 -+#define MV_5181L_A0_ID ((MV_5181_DEV_ID << 16) | MV_5181L_A0_REV) -+ -+ -+ -+/* kw */ -+#define MV_6281_DEV_ID 0x6281 -+#define MV_6192_DEV_ID 0x6192 -+#define MV_6190_DEV_ID 0x6190 -+#define MV_6180_DEV_ID 0x6180 -+ -+#define MV_6281_A0_REV 0x2 -+#define MV_6281_A0_ID ((MV_6281_DEV_ID << 16) | MV_6281_A0_REV) -+#define MV_6281_A0_NAME "88F6281 A0" -+ -+#define MV_6192_A0_REV 0x2 -+#define MV_6192_A0_ID ((MV_6192_DEV_ID << 16) | MV_6192_A0_REV) -+#define MV_6192_A0_NAME "88F6192 A0" -+ -+#define MV_6190_A0_REV 0x2 -+#define MV_6190_A0_ID ((MV_6190_DEV_ID << 16) | MV_6190_A0_REV) -+#define MV_6190_A0_NAME "88F6190 A0" -+ -+#define MV_6180_A0_REV 0x2 -+#define MV_6180_A0_ID ((MV_6180_DEV_ID << 16) | MV_6180_A0_REV) -+#define MV_6180_A0_NAME "88F6180 A0" -+ -+#define MV_6281_A1_REV 0x3 -+#define MV_6281_A1_ID ((MV_6281_DEV_ID << 16) | MV_6281_A1_REV) -+#define MV_6281_A1_NAME "88F6281 A1" -+ -+#define MV_6192_A1_REV 0x3 -+#define MV_6192_A1_ID ((MV_6192_DEV_ID << 16) | MV_6192_A1_REV) -+#define MV_6192_A1_NAME "88F6192 A1" -+ -+#define MV_6190_A1_REV 0x3 -+#define MV_6190_A1_ID ((MV_6190_DEV_ID << 16) | MV_6190_A1_REV) -+#define MV_6190_A1_NAME "88F6190 A1" -+ -+#define MV_6180_A1_REV 0x3 -+#define MV_6180_A1_ID ((MV_6180_DEV_ID << 16) | MV_6180_A1_REV) -+#define MV_6180_A1_NAME "88F6180 A1" -+ -+#define MV_88F6XXX_A0_REV 0x2 -+#define MV_88F6XXX_A1_REV 0x3 -+/* Disco-Duo */ -+#define MV_78XX0_ZY_DEV_ID 0x6381 -+#define MV_78XX0_ZY_NAME "MV78X00" -+ -+#define MV_78XX0_Z0_REV 0x1 -+#define MV_78XX0_Z0_ID ((MV_78XX0_ZY_DEV_ID << 16) | MV_78XX0_Z0_REV) -+#define MV_78XX0_Z0_NAME "78X00 Z0" -+ -+#define MV_78XX0_Y0_REV 0x2 -+#define MV_78XX0_Y0_ID ((MV_78XX0_ZY_DEV_ID << 16) | MV_78XX0_Y0_REV) -+#define MV_78XX0_Y0_NAME "78X00 Y0" -+ -+#define MV_78XX0_DEV_ID 0x7800 -+#define MV_78XX0_NAME "MV78X00" -+ -+#define MV_76100_DEV_ID 0x7610 -+#define MV_78200_DEV_ID 0x7820 -+#define MV_78100_DEV_ID 0x7810 -+#define MV_78XX0_A0_REV 0x1 -+#define MV_78XX0_A1_REV 0x2 -+ -+#define MV_76100_NAME "MV76100" -+#define MV_78100_NAME "MV78100" -+#define MV_78200_NAME "MV78200" -+ -+#define MV_76100_A0_ID ((MV_76100_DEV_ID << 16) | MV_78XX0_A0_REV) -+#define MV_78100_A0_ID ((MV_78100_DEV_ID << 16) | MV_78XX0_A0_REV) -+#define MV_78200_A0_ID ((MV_78200_DEV_ID << 16) | MV_78XX0_A0_REV) -+ -+#define MV_76100_A1_ID ((MV_76100_DEV_ID << 16) | MV_78XX0_A1_REV) -+#define MV_78100_A1_ID ((MV_78100_DEV_ID << 16) | MV_78XX0_A1_REV) -+#define MV_78200_A1_ID ((MV_78200_DEV_ID << 16) | MV_78XX0_A1_REV) -+ -+#define MV_76100_A0_NAME "MV76100 A0" -+#define MV_78100_A0_NAME "MV78100 A0" -+#define MV_78200_A0_NAME "MV78200 A0" -+#define MV_78XX0_A0_NAME "MV78XX0 A0" -+ -+#define MV_76100_A1_NAME "MV76100 A1" -+#define MV_78100_A1_NAME "MV78100 A1" -+#define MV_78200_A1_NAME "MV78200 A1" -+#define MV_78XX0_A1_NAME "MV78XX0 A1" -+ -+/*MV88F632X family*/ -+#define MV_6321_DEV_ID 0x6321 -+#define MV_6322_DEV_ID 0x6322 -+#define MV_6323_DEV_ID 0x6323 -+ -+#define MV_6321_NAME "88F6321" -+#define MV_6322_NAME "88F6322" -+#define MV_6323_NAME "88F6323" -+ -+#define MV_632X_A1_REV 0x2 -+ -+#define MV_6321_A1_ID ((MV_6321_DEV_ID << 16) | MV_632X_A1_REV) -+#define MV_6322_A1_ID ((MV_6322_DEV_ID << 16) | MV_632X_A1_REV) -+#define MV_6323_A1_ID ((MV_6323_DEV_ID << 16) | MV_632X_A1_REV) -+ -+#define MV_6321_A1_NAME "88F6321 A1" -+#define MV_6322_A1_NAME "88F6322 A1" -+#define MV_6323_A1_NAME "88F6323 A1" -+ -+ -+#endif /* __INCmvDeviceIdh */ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/common/mvHalVer.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/common/mvHalVer.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/common/mvHalVer.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/common/mvHalVer.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,73 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvHalVerh -+#define __INCmvHalVerh -+ -+/* Defines */ -+#define MV_HAL_VERSION "FEROCEON_HAL_3_1_7" -+#define MV_RELEASE_BASELINE "SoCandControllers_FEROCEON_RELEASE_7_9_2009_KW_4_3_4_DD_2_1_4_6183_1_1_4" -+ -+#endif /* __INCmvHalVerh */ -\ No newline at end of file -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/common/mvStack.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/common/mvStack.c ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/common/mvStack.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/common/mvStack.c 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,100 @@ -+/******************************************************************************* -+* Copyright 2003, Marvell Semiconductor Israel LTD. * -+* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL. * -+* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT * -+* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE * -+* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL. * -+* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED, * -+* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE. * -+* * -+* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, * -+* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL * -+* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K. * -+* (MJKK), MARVELL SEMICONDUCTOR ISRAEL LTD (MSIL). * -+******************************************************************************** -+* mvQueue.c -+* -+* FILENAME: $Workfile: mvStack.c $ -+* REVISION: $Revision: 1.1 $ -+* LAST UPDATE: $Modtime: $ -+* -+* DESCRIPTION: -+* This file implements simple Stack LIFO functionality. -+*******************************************************************************/ -+ -+/* includes */ -+#include "mvOs.h" -+#include "mvTypes.h" -+#include "mvDebug.h" -+#include "mvStack.h" -+ -+/* defines */ -+ -+ -+/* Public functions */ -+ -+ -+/* Purpose: Create new stack -+ * Inputs: -+ * - MV_U32 noOfElements - maximum number of elements in the stack. -+ * Each element 4 bytes size -+ * Return: void* - pointer to created stack. -+ */ -+void* mvStackCreate(int numOfElements) -+{ -+ MV_STACK* pStack; -+ MV_U32* pStackElements; -+ -+ pStack = (MV_STACK*)mvOsMalloc(sizeof(MV_STACK)); -+ pStackElements = (MV_U32*)mvOsMalloc(numOfElements*sizeof(MV_U32)); -+ if( (pStack == NULL) || (pStackElements == NULL) ) -+ { -+ mvOsPrintf("mvStack: Can't create new stack\n"); -+ return NULL; -+ } -+ memset(pStackElements, 0, numOfElements*sizeof(MV_U32)); -+ pStack->numOfElements = numOfElements; -+ pStack->stackIdx = 0; -+ pStack->stackElements = pStackElements; -+ -+ return pStack; -+} -+ -+/* Purpose: Delete existing stack -+ * Inputs: -+ * - void* stackHndl - Stack handle as returned by "mvStackCreate()" function -+ * -+ * Return: MV_STATUS MV_NOT_FOUND - Failure. StackHandle is not valid. -+ * MV_OK - Success. -+ */ -+MV_STATUS mvStackDelete(void* stackHndl) -+{ -+ MV_STACK* pStack = (MV_STACK*)stackHndl; -+ -+ if( (pStack == NULL) || (pStack->stackElements == NULL) ) -+ return MV_NOT_FOUND; -+ -+ mvOsFree(pStack->stackElements); -+ mvOsFree(pStack); -+ -+ return MV_OK; -+} -+ -+ -+/* PrintOut status of the stack */ -+void mvStackStatus(void* stackHndl, MV_BOOL isPrintElements) -+{ -+ int i; -+ MV_STACK* pStack = (MV_STACK*)stackHndl; -+ -+ mvOsPrintf("StackHandle=%p, pElements=%p, numElements=%d, stackIdx=%d\n", -+ stackHndl, pStack->stackElements, pStack->numOfElements, -+ pStack->stackIdx); -+ if(isPrintElements == MV_TRUE) -+ { -+ for(i=0; istackIdx; i++) -+ { -+ mvOsPrintf("%3d. Value=0x%x\n", i, pStack->stackElements[i]); -+ } -+ } -+} -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/common/mvStack.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/common/mvStack.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/common/mvStack.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/common/mvStack.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,140 @@ -+/******************************************************************************* -+* Copyright 2003, Marvell Semiconductor Israel LTD. * -+* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL. * -+* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT * -+* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE * -+* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL. * -+* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED, * -+* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE. * -+* * -+* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, * -+* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL * -+* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K. * -+* (MJKK), MARVELL SEMICONDUCTOR ISRAEL LTD (MSIL). * -+******************************************************************************** -+* mvStack.h - Header File for : -+* -+* FILENAME: $Workfile: mvStack.h $ -+* REVISION: $Revision: 1.1 $ -+* LAST UPDATE: $Modtime: $ -+* -+* DESCRIPTION: -+* This file defines simple Stack (LIFO) functionality. -+* -+*******************************************************************************/ -+ -+#ifndef __mvStack_h__ -+#define __mvStack_h__ -+ -+ -+/* includes */ -+#include "mvTypes.h" -+ -+ -+/* defines */ -+ -+ -+/* typedefs */ -+/* Data structure describes general purpose Stack */ -+typedef struct -+{ -+ int stackIdx; -+ int numOfElements; -+ MV_U32* stackElements; -+} MV_STACK; -+ -+static INLINE MV_BOOL mvStackIsFull(void* stackHndl) -+{ -+ MV_STACK* pStack = (MV_STACK*)stackHndl; -+ -+ if(pStack->stackIdx == pStack->numOfElements) -+ return MV_TRUE; -+ -+ return MV_FALSE; -+} -+ -+static INLINE MV_BOOL mvStackIsEmpty(void* stackHndl) -+{ -+ MV_STACK* pStack = (MV_STACK*)stackHndl; -+ -+ if(pStack->stackIdx == 0) -+ return MV_TRUE; -+ -+ return MV_FALSE; -+} -+/* Purpose: Push new element to stack -+ * Inputs: -+ * - void* stackHndl - Stack handle as returned by "mvStackCreate()" function. -+ * - MV_U32 value - New element. -+ * -+ * Return: MV_STATUS MV_FULL - Failure. Stack is full. -+ * MV_OK - Success. Element is put to stack. -+ */ -+static INLINE void mvStackPush(void* stackHndl, MV_U32 value) -+{ -+ MV_STACK* pStack = (MV_STACK*)stackHndl; -+ -+#ifdef MV_RT_DEBUG -+ if(pStack->stackIdx == pStack->numOfElements) -+ { -+ mvOsPrintf("mvStackPush: Stack is FULL\n"); -+ return; -+ } -+#endif /* MV_RT_DEBUG */ -+ -+ pStack->stackElements[pStack->stackIdx] = value; -+ pStack->stackIdx++; -+} -+ -+/* Purpose: Pop element from the top of stack and copy it to "pValue" -+ * Inputs: -+ * - void* stackHndl - Stack handle as returned by "mvStackCreate()" function. -+ * - MV_U32 value - Element in the top of stack. -+ * -+ * Return: MV_STATUS MV_EMPTY - Failure. Stack is empty. -+ * MV_OK - Success. Element is removed from the stack and -+ * copied to pValue argument -+ */ -+static INLINE MV_U32 mvStackPop(void* stackHndl) -+{ -+ MV_STACK* pStack = (MV_STACK*)stackHndl; -+ -+#ifdef MV_RT_DEBUG -+ if(pStack->stackIdx == 0) -+ { -+ mvOsPrintf("mvStackPop: Stack is EMPTY\n"); -+ return 0; -+ } -+#endif /* MV_RT_DEBUG */ -+ -+ pStack->stackIdx--; -+ return pStack->stackElements[pStack->stackIdx]; -+} -+ -+static INLINE int mvStackIndex(void* stackHndl) -+{ -+ MV_STACK* pStack = (MV_STACK*)stackHndl; -+ -+ return pStack->stackIdx; -+} -+ -+static INLINE int mvStackFreeElements(void* stackHndl) -+{ -+ MV_STACK* pStack = (MV_STACK*)stackHndl; -+ -+ return (pStack->numOfElements - pStack->stackIdx); -+} -+ -+/* mvStack.h API list */ -+ -+/* Create new Stack */ -+void* mvStackCreate(int numOfElements); -+ -+/* Delete existing stack */ -+MV_STATUS mvStackDelete(void* stackHndl); -+ -+/* Print status of the stack */ -+void mvStackStatus(void* stackHndl, MV_BOOL isPrintElements); -+ -+#endif /* __mvStack_h__ */ -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/common/mvTypes.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/common/mvTypes.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/common/mvTypes.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/common/mvTypes.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,245 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvTypesh -+#define __INCmvTypesh -+ -+/* Defines */ -+ -+/* The following is a list of Marvell status */ -+#define MV_ERROR (-1) -+#define MV_OK (0x00) /* Operation succeeded */ -+#define MV_FAIL (0x01) /* Operation failed */ -+#define MV_BAD_VALUE (0x02) /* Illegal value (general) */ -+#define MV_OUT_OF_RANGE (0x03) /* The value is out of range */ -+#define MV_BAD_PARAM (0x04) /* Illegal parameter in function called */ -+#define MV_BAD_PTR (0x05) /* Illegal pointer value */ -+#define MV_BAD_SIZE (0x06) /* Illegal size */ -+#define MV_BAD_STATE (0x07) /* Illegal state of state machine */ -+#define MV_SET_ERROR (0x08) /* Set operation failed */ -+#define MV_GET_ERROR (0x09) /* Get operation failed */ -+#define MV_CREATE_ERROR (0x0A) /* Fail while creating an item */ -+#define MV_NOT_FOUND (0x0B) /* Item not found */ -+#define MV_NO_MORE (0x0C) /* No more items found */ -+#define MV_NO_SUCH (0x0D) /* No such item */ -+#define MV_TIMEOUT (0x0E) /* Time Out */ -+#define MV_NO_CHANGE (0x0F) /* Parameter(s) is already in this value */ -+#define MV_NOT_SUPPORTED (0x10) /* This request is not support */ -+#define MV_NOT_IMPLEMENTED (0x11) /* Request supported but not implemented */ -+#define MV_NOT_INITIALIZED (0x12) /* The item is not initialized */ -+#define MV_NO_RESOURCE (0x13) /* Resource not available (memory ...) */ -+#define MV_FULL (0x14) /* Item is full (Queue or table etc...) */ -+#define MV_EMPTY (0x15) /* Item is empty (Queue or table etc...) */ -+#define MV_INIT_ERROR (0x16) /* Error occured while INIT process */ -+#define MV_HW_ERROR (0x17) /* Hardware error */ -+#define MV_TX_ERROR (0x18) /* Transmit operation not succeeded */ -+#define MV_RX_ERROR (0x19) /* Recieve operation not succeeded */ -+#define MV_NOT_READY (0x1A) /* The other side is not ready yet */ -+#define MV_ALREADY_EXIST (0x1B) /* Tried to create existing item */ -+#define MV_OUT_OF_CPU_MEM (0x1C) /* Cpu memory allocation failed. */ -+#define MV_NOT_STARTED (0x1D) /* Not started yet */ -+#define MV_BUSY (0x1E) /* Item is busy. */ -+#define MV_TERMINATE (0x1F) /* Item terminates it's work. */ -+#define MV_NOT_ALIGNED (0x20) /* Wrong alignment */ -+#define MV_NOT_ALLOWED (0x21) /* Operation NOT allowed */ -+#define MV_WRITE_PROTECT (0x22) /* Write protected */ -+ -+ -+#define MV_INVALID (int)(-1) -+ -+#define MV_FALSE 0 -+#define MV_TRUE (!(MV_FALSE)) -+ -+ -+#ifndef NULL -+#define NULL ((void*)0) -+#endif -+ -+ -+#ifndef MV_ASMLANGUAGE -+/* typedefs */ -+ -+typedef char MV_8; -+typedef unsigned char MV_U8; -+ -+typedef int MV_32; -+typedef unsigned int MV_U32; -+ -+typedef short MV_16; -+typedef unsigned short MV_U16; -+ -+#ifdef MV_PPC64 -+typedef long MV_64; -+typedef unsigned long MV_U64; -+#else -+typedef long long MV_64; -+typedef unsigned long long MV_U64; -+#endif -+ -+typedef long MV_LONG; /* 32/64 */ -+typedef unsigned long MV_ULONG; /* 32/64 */ -+ -+typedef int MV_STATUS; -+typedef int MV_BOOL; -+typedef void MV_VOID; -+typedef float MV_FLOAT; -+ -+typedef int (*MV_FUNCPTR) (void); /* ptr to function returning int */ -+typedef void (*MV_VOIDFUNCPTR) (void); /* ptr to function returning void */ -+typedef double (*MV_DBLFUNCPTR) (void); /* ptr to function returning double*/ -+typedef float (*MV_FLTFUNCPTR) (void); /* ptr to function returning float */ -+ -+typedef MV_U32 MV_KHZ; -+typedef MV_U32 MV_MHZ; -+typedef MV_U32 MV_HZ; -+ -+ -+/* This enumerator describes the set of commands that can be applied on */ -+/* an engine (e.g. IDMA, XOR). Appling a comman depends on the current */ -+/* status (see MV_STATE enumerator) */ -+/* Start can be applied only when status is IDLE */ -+/* Stop can be applied only when status is IDLE, ACTIVE or PAUSED */ -+/* Pause can be applied only when status is ACTIVE */ -+/* Restart can be applied only when status is PAUSED */ -+typedef enum _mvCommand -+{ -+ MV_START, /* Start */ -+ MV_STOP, /* Stop */ -+ MV_PAUSE, /* Pause */ -+ MV_RESTART /* Restart */ -+} MV_COMMAND; -+ -+/* This enumerator describes the set of state conditions. */ -+/* Moving from one state to other is stricted. */ -+typedef enum _mvState -+{ -+ MV_IDLE, -+ MV_ACTIVE, -+ MV_PAUSED, -+ MV_UNDEFINED_STATE -+} MV_STATE; -+ -+ -+/* This structure describes address space window. Window base can be */ -+/* 64 bit, window size up to 4GB */ -+typedef struct _mvAddrWin -+{ -+ MV_U32 baseLow; /* 32bit base low */ -+ MV_U32 baseHigh; /* 32bit base high */ -+ MV_U32 size; /* 32bit size */ -+}MV_ADDR_WIN; -+ -+/* This binary enumerator describes protection attribute status */ -+typedef enum _mvProtRight -+{ -+ ALLOWED, /* Protection attribute allowed */ -+ FORBIDDEN /* Protection attribute forbidden */ -+}MV_PROT_RIGHT; -+ -+/* Unified struct for Rx and Tx packet operations. The user is required to */ -+/* be familier only with Tx/Rx descriptor command status. */ -+typedef struct _bufInfo -+{ -+ MV_U32 cmdSts; /* Tx/Rx command status */ -+ MV_U16 byteCnt; /* Size of valid data in the buffer */ -+ MV_U16 bufSize; /* Total size of the buffer */ -+ MV_U8 *pBuff; /* Pointer to Buffer */ -+ MV_U8 *pData; /* Pointer to data in the Buffer */ -+ MV_U32 userInfo1; /* Tx/Rx attached user information 1 */ -+ MV_U32 userInfo2; /* Tx/Rx attached user information 2 */ -+ struct _bufInfo *pNextBufInfo; /* Next buffer in packet */ -+} BUF_INFO; -+ -+/* This structure contains information describing one of buffers -+ * (fragments) they are built Ethernet packet. -+ */ -+typedef struct -+{ -+ MV_U8* bufVirtPtr; -+ MV_ULONG bufPhysAddr; -+ MV_U32 bufSize; -+ MV_U32 dataSize; -+ MV_U32 memHandle; -+ MV_32 bufAddrShift; -+} MV_BUF_INFO; -+ -+/* This structure contains information describing Ethernet packet. -+ * The packet can be divided for few buffers (fragments) -+ */ -+typedef struct -+{ -+ MV_ULONG osInfo; -+ MV_BUF_INFO *pFrags; -+ MV_U32 status; -+ MV_U16 pktSize; -+ MV_U16 numFrags; -+ MV_U32 ownerId; -+ MV_U32 fragIP; -+} MV_PKT_INFO; -+ -+#endif /* MV_ASMLANGUAGE */ -+ -+#endif /* __INCmvTypesh */ -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/dbg-trace.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/dbg-trace.c ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/dbg-trace.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/dbg-trace.c 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,110 @@ -+#include -+#include -+#include -+#include "dbg-trace.h" -+ -+#define TRACE_ARR_LEN 800 -+#define STR_LEN 128 -+struct trace { -+ struct timeval tv; -+ char str[STR_LEN]; -+ unsigned int callback_val1; -+ unsigned int callback_val2; -+ char valid; -+}; -+static unsigned int (*trc_callback1) (unsigned char) = NULL; -+static unsigned int (*trc_callback2) (unsigned char) = NULL; -+static unsigned char trc_param1 = 0; -+static unsigned char trc_param2 = 0; -+struct trace *trc_arr; -+static int trc_index; -+static int trc_active = 0; -+ -+void TRC_START() -+{ -+ trc_active = 1; -+} -+ -+void TRC_STOP() -+{ -+ trc_active = 0; -+} -+ -+void TRC_INIT(void *callback1, void *callback2, unsigned char callback1_param, unsigned char callback2_param) -+{ -+ printk("Marvell debug tracing is on\n"); -+ trc_arr = (struct trace *)kmalloc(TRACE_ARR_LEN*sizeof(struct trace),GFP_KERNEL); -+ if(trc_arr == NULL) -+ { -+ printk("Can't allocate Debug Trace buffer\n"); -+ return; -+ } -+ memset(trc_arr,0,TRACE_ARR_LEN*sizeof(struct trace)); -+ trc_index = 0; -+ trc_callback1 = callback1; -+ trc_callback2 = callback2; -+ trc_param1 = callback1_param; -+ trc_param2 = callback2_param; -+} -+void TRC_REC(char *fmt,...) -+{ -+ va_list args; -+ struct trace *trc = &trc_arr[trc_index]; -+ -+ if(trc_active == 0) -+ return; -+ -+ do_gettimeofday(&trc->tv); -+ if(trc_callback1) -+ trc->callback_val1 = trc_callback1(trc_param1); -+ if(trc_callback2) -+ trc->callback_val2 = trc_callback2(trc_param2); -+ va_start(args, fmt); -+ vsprintf(trc->str,fmt,args); -+ va_end(args); -+ trc->valid = 1; -+ if((++trc_index) == TRACE_ARR_LEN) { -+ trc_index = 0; -+ } -+} -+void TRC_OUTPUT(void) -+{ -+ int i,j; -+ struct trace *p; -+ printk("\n\nTrace %d items\n",TRACE_ARR_LEN); -+ for(i=0,j=trc_index; ivalid) { -+ unsigned long uoffs; -+ struct trace *plast; -+ if(p == &trc_arr[0]) -+ plast = &trc_arr[TRACE_ARR_LEN-1]; -+ else -+ plast = p-1; -+ if(p->tv.tv_sec == ((plast)->tv.tv_sec)) -+ uoffs = (p->tv.tv_usec - ((plast)->tv.tv_usec)); -+ else -+ uoffs = (1000000 - ((plast)->tv.tv_usec)) + -+ ((p->tv.tv_sec - ((plast)->tv.tv_sec) - 1) * 1000000) + -+ p->tv.tv_usec; -+ printk("%03d: [+%ld usec]", j, (unsigned long)uoffs); -+ if(trc_callback1) -+ printk("[%u]",p->callback_val1); -+ if(trc_callback2) -+ printk("[%u]",p->callback_val2); -+ printk(": %s",p->str); -+ } -+ p->valid = 0; -+ } -+ memset(trc_arr,0,TRACE_ARR_LEN*sizeof(struct trace)); -+ trc_index = 0; -+} -+void TRC_RELEASE(void) -+{ -+ kfree(trc_arr); -+ trc_index = 0; -+} -+ -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/dbg-trace.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/dbg-trace.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/dbg-trace.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/dbg-trace.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,24 @@ -+ -+#ifndef _MV_DBG_TRCE_H_ -+#define _MV_DBG_TRCE_H_ -+ -+#ifdef CONFIG_MV_DBG_TRACE -+void TRC_INIT(void *callback1, void *callback2, -+ unsigned char callback1_param, unsigned char callback2_param); -+void TRC_REC(char *fmt,...); -+void TRC_OUTPUT(void); -+void TRC_RELEASE(void); -+void TRC_START(void); -+void TRC_STOP(void); -+ -+#else -+#define TRC_INIT(x1,x2,x3,x4) -+#define TRC_REC(X...) -+#define TRC_OUTPUT() -+#define TRC_RELEASE() -+#define TRC_START() -+#define TRC_STOP() -+#endif -+ -+ -+#endif -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,2513 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "boardEnv/mvBoardEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+#include "cpu/mvCpu.h" -+#include "cntmr/mvCntmr.h" -+#include "gpp/mvGpp.h" -+#include "twsi/mvTwsi.h" -+#include "pex/mvPex.h" -+#include "device/mvDevice.h" -+#include "eth/gbe/mvEthRegs.h" -+ -+/* defines */ -+/* #define MV_DEBUG */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+extern MV_CPU_ARM_CLK _cpuARMDDRCLK[]; -+ -+#define CODE_IN_ROM MV_FALSE -+#define CODE_IN_RAM MV_TRUE -+ -+extern MV_BOARD_INFO* boardInfoTbl[]; -+#define BOARD_INFO(boardId) boardInfoTbl[boardId - BOARD_ID_BASE] -+ -+/* Locals */ -+static MV_DEV_CS_INFO* boardGetDevEntry(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); -+ -+MV_U32 tClkRate = -1; -+ -+ -+/******************************************************************************* -+* mvBoardEnvInit - Init board -+* -+* DESCRIPTION: -+* In this function the board environment take care of device bank -+* initialization. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvBoardEnvInit(MV_VOID) -+{ -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardEnvInit:Board unknown.\n"); -+ return; -+ -+ } -+ -+ /* Set GPP Out value */ -+ MV_REG_WRITE(GPP_DATA_OUT_REG(0), BOARD_INFO(boardId)->gppOutValLow); -+ MV_REG_WRITE(GPP_DATA_OUT_REG(1), BOARD_INFO(boardId)->gppOutValHigh); -+ -+ /* set GPP polarity */ -+ mvGppPolaritySet(0, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValLow); -+ mvGppPolaritySet(1, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValHigh); -+ -+ /* Workaround for Erratum FE-MISC-70*/ -+ if(mvCtrlRevGet()==MV_88F6XXX_A0_REV) -+ { -+ BOARD_INFO(boardId)->gppOutEnValLow &= 0xfffffffd; -+ BOARD_INFO(boardId)->gppOutEnValLow |= (BOARD_INFO(boardId)->gppOutEnValHigh) & 0x00000002; -+ } /*End of WA*/ -+ -+ /* Set GPP Out Enable*/ -+ mvGppTypeSet(0, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValLow); -+ mvGppTypeSet(1, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValHigh); -+ -+ /* Nand CE */ -+ MV_REG_BIT_SET(NAND_CTRL_REG, NAND_ACTCEBOOT_BIT); -+} -+ -+/******************************************************************************* -+* mvBoardModelGet - Get Board model -+* -+* DESCRIPTION: -+* This function returns 16bit describing board model. -+* Board model is constructed of one byte major and minor numbers in the -+* following manner: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* String describing board model. -+* -+*******************************************************************************/ -+MV_U16 mvBoardModelGet(MV_VOID) -+{ -+ return (mvBoardIdGet() >> 16); -+} -+ -+/******************************************************************************* -+* mbBoardRevlGet - Get Board revision -+* -+* DESCRIPTION: -+* This function returns a 32bit describing the board revision. -+* Board revision is constructed of 4bytes. 2bytes describes major number -+* and the other 2bytes describes minor munber. -+* For example for board revision 3.4 the function will return -+* 0x00030004. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* String describing board model. -+* -+*******************************************************************************/ -+MV_U16 mvBoardRevGet(MV_VOID) -+{ -+ return (mvBoardIdGet() & 0xFFFF); -+} -+ -+/******************************************************************************* -+* mvBoardNameGet - Get Board name -+* -+* DESCRIPTION: -+* This function returns a string describing the board model and revision. -+* String is extracted from board I2C EEPROM. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* pNameBuff - Buffer to contain board name string. Minimum size 32 chars. -+* -+* RETURN: -+* -+* MV_ERROR if informantion can not be read. -+*******************************************************************************/ -+MV_STATUS mvBoardNameGet(char *pNameBuff) -+{ -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsSPrintf (pNameBuff, "Board unknown.\n"); -+ return MV_ERROR; -+ -+ } -+ -+ mvOsSPrintf (pNameBuff, "%s",BOARD_INFO(boardId)->boardName); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvBoardIsPortInSgmii - -+* -+* DESCRIPTION: -+* This routine returns MV_TRUE for port number works in SGMII or MV_FALSE -+* For all other options. -+* -+* INPUT: -+* ethPortNum - Ethernet port number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE - port in SGMII. -+* MV_FALSE - other. -+* -+*******************************************************************************/ -+MV_BOOL mvBoardIsPortInSgmii(MV_U32 ethPortNum) -+{ -+ MV_BOOL ethPortSgmiiSupport[BOARD_ETH_PORT_NUM] = MV_ETH_PORT_SGMII; -+ -+ if(ethPortNum >= BOARD_ETH_PORT_NUM) -+ { -+ mvOsPrintf ("Invalid portNo=%d\n", ethPortNum); -+ return MV_FALSE; -+ } -+ return ethPortSgmiiSupport[ethPortNum]; -+} -+ -+/******************************************************************************* -+* mvBoardIsPortInGmii - -+* -+* DESCRIPTION: -+* This routine returns MV_TRUE for port number works in GMII or MV_FALSE -+* For all other options. -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE - port in GMII. -+* MV_FALSE - other. -+* -+*******************************************************************************/ -+MV_BOOL mvBoardIsPortInGmii(MV_VOID) -+{ -+ MV_U32 devClassId, devClass = 0; -+ if (mvBoardMppGroupTypeGet(devClass) == MV_BOARD_AUTO) -+ { -+ /* Get MPP module ID */ -+ devClassId = mvBoarModuleTypeGet(devClass); -+ if (MV_BOARD_MODULE_GMII_ID == devClassId) -+ return MV_TRUE; -+ } -+ else if (mvBoardMppGroupTypeGet(devClass) == MV_BOARD_GMII) -+ return MV_TRUE; -+ -+ return MV_FALSE; -+} -+/******************************************************************************* -+* mvBoardPhyAddrGet - Get the phy address -+* -+* DESCRIPTION: -+* This routine returns the Phy address of a given ethernet port. -+* -+* INPUT: -+* ethPortNum - Ethernet port number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit describing Phy address, -1 if the port number is wrong. -+* -+*******************************************************************************/ -+MV_32 mvBoardPhyAddrGet(MV_U32 ethPortNum) -+{ -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardPhyAddrGet: Board unknown.\n"); -+ return MV_ERROR; -+ } -+ -+ return BOARD_INFO(boardId)->pBoardMacInfo[ethPortNum].boardEthSmiAddr; -+} -+ -+/******************************************************************************* -+* mvBoardMacSpeedGet - Get the Mac speed -+* -+* DESCRIPTION: -+* This routine returns the Mac speed if pre define of a given ethernet port. -+* -+* INPUT: -+* ethPortNum - Ethernet port number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BOARD_MAC_SPEED, -1 if the port number is wrong. -+* -+*******************************************************************************/ -+MV_BOARD_MAC_SPEED mvBoardMacSpeedGet(MV_U32 ethPortNum) -+{ -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardMacSpeedGet: Board unknown.\n"); -+ return MV_ERROR; -+ } -+ -+ return BOARD_INFO(boardId)->pBoardMacInfo[ethPortNum].boardMacSpeed; -+} -+ -+/******************************************************************************* -+* mvBoardLinkStatusIrqGet - Get the IRQ number for the link status indication -+* -+* DESCRIPTION: -+* This routine returns the IRQ number for the link status indication. -+* -+* INPUT: -+* ethPortNum - Ethernet port number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* the number of the IRQ for the link status indication, -1 if the port -+* number is wrong or if not relevant. -+* -+*******************************************************************************/ -+MV_32 mvBoardLinkStatusIrqGet(MV_U32 ethPortNum) -+{ -+ MV_U32 boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardLinkStatusIrqGet: Board unknown.\n"); -+ return MV_ERROR; -+ } -+ -+ return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].linkStatusIrq; -+} -+ -+/******************************************************************************* -+* mvBoardSwitchPortGet - Get the mapping between the board connector and the -+* Ethernet Switch port -+* -+* DESCRIPTION: -+* This routine returns the matching Switch port. -+* -+* INPUT: -+* ethPortNum - Ethernet port number. -+* boardPortNum - logical number of the connector on the board -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* the matching Switch port, -1 if the port number is wrong or if not relevant. -+* -+*******************************************************************************/ -+MV_32 mvBoardSwitchPortGet(MV_U32 ethPortNum, MV_U8 boardPortNum) -+{ -+ MV_U32 boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardSwitchPortGet: Board unknown.\n"); -+ return MV_ERROR; -+ } -+ if (boardPortNum >= BOARD_ETH_SWITCH_PORT_NUM) -+ { -+ mvOsPrintf("mvBoardSwitchPortGet: Illegal board port number.\n"); -+ return MV_ERROR; -+ } -+ -+ return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].qdPort[boardPortNum]; -+} -+ -+/******************************************************************************* -+* mvBoardSwitchCpuPortGet - Get the the Ethernet Switch CPU port -+* -+* DESCRIPTION: -+* This routine returns the Switch CPU port. -+* -+* INPUT: -+* ethPortNum - Ethernet port number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* the Switch CPU port, -1 if the port number is wrong or if not relevant. -+* -+*******************************************************************************/ -+MV_32 mvBoardSwitchCpuPortGet(MV_U32 ethPortNum) -+{ -+ MV_U32 boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardSwitchCpuPortGet: Board unknown.\n"); -+ return MV_ERROR; -+ } -+ -+ return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].qdCpuPort; -+} -+ -+/******************************************************************************* -+* mvBoardIsSwitchConnected - Get switch connection status -+* DESCRIPTION: -+* This routine returns port's connection status -+* -+* INPUT: -+* ethPortNum - Ethernet port number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 1 - if ethPortNum is connected to switch, 0 otherwise -+* -+*******************************************************************************/ -+MV_32 mvBoardIsSwitchConnected(MV_U32 ethPortNum) -+{ -+ MV_U32 boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardIsSwitchConnected: Board unknown.\n"); -+ return MV_ERROR; -+ } -+ -+ if(ethPortNum >= BOARD_INFO(boardId)->numBoardMacInfo) -+ { -+ mvOsPrintf("mvBoardIsSwitchConnected: Illegal port number(%u)\n", ethPortNum); -+ return MV_ERROR; -+ } -+ -+ if((MV_32)(BOARD_INFO(boardId)->pSwitchInfo)) -+ return (MV_32)(BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].switchOnPort == ethPortNum); -+ else -+ return 0; -+} -+/******************************************************************************* -+* mvBoardSmiScanModeGet - Get Switch SMI scan mode -+* -+* DESCRIPTION: -+* This routine returns Switch SMI scan mode. -+* -+* INPUT: -+* ethPortNum - Ethernet port number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 1 for SMI_MANUAL_MODE, -1 if the port number is wrong or if not relevant. -+* -+*******************************************************************************/ -+MV_32 mvBoardSmiScanModeGet(MV_U32 ethPortNum) -+{ -+ MV_U32 boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardSmiScanModeGet: Board unknown.\n"); -+ return MV_ERROR; -+ } -+ -+ return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].smiScanMode; -+} -+/******************************************************************************* -+* mvBoardSpecInitGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: Return MV_TRUE and parameters in case board need spesific phy init, -+* otherwise return MV_FALSE. -+* -+* -+*******************************************************************************/ -+ -+MV_BOOL mvBoardSpecInitGet(MV_U32* regOff, MV_U32* data) -+{ -+ return MV_FALSE; -+} -+ -+/******************************************************************************* -+* mvBoardTclkGet - Get the board Tclk (Controller clock) -+* -+* DESCRIPTION: -+* This routine extract the controller core clock. -+* This function uses the controller counters to make identification. -+* Note: In order to avoid interference, make sure task context switch -+* and interrupts will not occure during this function operation -+* -+* INPUT: -+* countNum - Counter number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit clock cycles in Hertz. -+* -+*******************************************************************************/ -+MV_U32 mvBoardTclkGet(MV_VOID) -+{ -+ if(mvCtrlModelGet()==MV_6281_DEV_ID) -+ { -+#if defined(TCLK_AUTO_DETECT) -+ MV_U32 tmpTClkRate = MV_BOARD_TCLK_166MHZ; -+ -+ tmpTClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ tmpTClkRate &= MSAR_TCLCK_MASK; -+ -+ switch (tmpTClkRate) -+ { -+ case MSAR_TCLCK_166: -+ return MV_BOARD_TCLK_166MHZ; -+ break; -+ case MSAR_TCLCK_200: -+ return MV_BOARD_TCLK_200MHZ; -+ break; -+ } -+#else -+ return MV_BOARD_TCLK_200MHZ; -+#endif -+ } -+ -+ return MV_BOARD_TCLK_166MHZ; -+ -+} -+/******************************************************************************* -+* mvBoardSysClkGet - Get the board SysClk (CPU bus clock) -+* -+* DESCRIPTION: -+* This routine extract the CPU bus clock. -+* -+* INPUT: -+* countNum - Counter number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit clock cycles in Hertz. -+* -+*******************************************************************************/ -+static MV_U32 mvBoard6180SysClkGet(MV_VOID) -+{ -+ MV_U32 sysClkRate=0; -+ MV_CPU_ARM_CLK _cpu6180_ddr_l2_CLK[] = MV_CPU6180_DDR_L2_CLCK_TBL; -+ -+ sysClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ sysClkRate = sysClkRate & MSAR_CPUCLCK_MASK_6180; -+ sysClkRate = sysClkRate >> MSAR_CPUCLCK_OFFS_6180; -+ -+ sysClkRate = _cpu6180_ddr_l2_CLK[sysClkRate].ddrClk; -+ -+ return sysClkRate; -+ -+} -+ -+MV_U32 mvBoardSysClkGet(MV_VOID) -+{ -+#ifdef SYSCLK_AUTO_DETECT -+ MV_U32 sysClkRate, tmp, pClkRate, indexDdrRtio; -+ MV_U32 cpuCLK[] = MV_CPU_CLCK_TBL; -+ MV_U32 ddrRtio[][2] = MV_DDR_CLCK_RTIO_TBL; -+ -+ if(mvCtrlModelGet() == MV_6180_DEV_ID) -+ return mvBoard6180SysClkGet(); -+ -+ tmp = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ pClkRate = MSAR_CPUCLCK_EXTRACT(tmp); -+ pClkRate = cpuCLK[pClkRate]; -+ -+ indexDdrRtio = tmp & MSAR_DDRCLCK_RTIO_MASK; -+ indexDdrRtio = indexDdrRtio >> MSAR_DDRCLCK_RTIO_OFFS; -+ if(ddrRtio[indexDdrRtio][0] != 0) -+ sysClkRate = ((pClkRate * ddrRtio[indexDdrRtio][1]) / ddrRtio[indexDdrRtio][0]); -+ else -+ sysClkRate = 0; -+ return sysClkRate; -+#else -+ return MV_BOARD_DEFAULT_SYSCLK; -+#endif -+} -+ -+ -+/******************************************************************************* -+* mvBoardPexBridgeIntPinGet - Get PEX to PCI bridge interrupt pin number -+* -+* DESCRIPTION: -+* Multi-ported PCI Express bridges that is implemented on the board -+* collapse interrupts across multiple conventional PCI/PCI-X buses. -+* A dual-headed PCI Express bridge would map (or "swizzle") the -+* interrupts per the following table (in accordance with the respective -+* logical PCI/PCI-X bridge's Device Number), collapse the INTA#-INTD# -+* signals from its two logical PCI/PCI-X bridges, collapse the -+* INTA#-INTD# signals from any internal sources, and convert the -+* signals to in-band PCI Express messages. 10 -+* This function returns the upstream interrupt as it was converted by -+* the bridge, according to board configuration and the following table: -+* PCI dev num -+* Interrupt pin 7, 8, 9 -+* A -> A D C -+* B -> B A D -+* C -> C B A -+* D -> D C B -+* -+* -+* INPUT: -+* devNum - PCI/PCIX device number. -+* intPin - PCI Int pin -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Int pin connected to the Interrupt controller -+* -+*******************************************************************************/ -+MV_U32 mvBoardPexBridgeIntPinGet(MV_U32 devNum, MV_U32 intPin) -+{ -+ MV_U32 realIntPin = ((intPin + (3 - (devNum % 4))) %4 ); -+ -+ if (realIntPin == 0) return 4; -+ else return realIntPin; -+ -+} -+ -+/******************************************************************************* -+* mvBoardDebugLedNumGet - Get number of debug Leds -+* -+* DESCRIPTION: -+* INPUT: -+* boardId -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_U32 mvBoardDebugLedNumGet(MV_U32 boardId) -+{ -+ return BOARD_INFO(boardId)->activeLedsNumber; -+} -+ -+/******************************************************************************* -+* mvBoardDebugLeg - Set the board debug Leds -+* -+* DESCRIPTION: turn on/off status leds. -+* Note: assume MPP leds are part of group 0 only. -+* -+* INPUT: -+* hexNum - Number to be displied in hex by Leds. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvBoardDebugLed(MV_U32 hexNum) -+{ -+ MV_U32 val = 0,totalMask, currentBitMask = 1,i; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (BOARD_INFO(boardId)->pLedGppPin == NULL) -+ return; -+ -+ totalMask = (1 << BOARD_INFO(boardId)->activeLedsNumber) -1; -+ hexNum &= totalMask; -+ totalMask = 0; -+ -+ for (i = 0 ; i < BOARD_INFO(boardId)->activeLedsNumber ; i++) -+ { -+ if (hexNum & currentBitMask) -+ { -+ val |= (1 << BOARD_INFO(boardId)->pLedGppPin[i]); -+ } -+ -+ totalMask |= (1 << BOARD_INFO(boardId)->pLedGppPin[i]); -+ -+ currentBitMask = (currentBitMask << 1); -+ } -+ -+ if (BOARD_INFO(boardId)->ledsPolarity) -+ { -+ mvGppValueSet(0, totalMask, val); -+ } -+ else -+ { -+ mvGppValueSet(0, totalMask, ~val); -+ } -+} -+ -+ -+/******************************************************************************* -+* mvBoarGpioPinGet - mvBoarGpioPinGet -+* -+* DESCRIPTION: -+* -+* INPUT: -+* class - MV_BOARD_GPP_CLASS enum. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* GPIO pin number. The function return -1 for bad parameters. -+* -+*******************************************************************************/ -+MV_32 mvBoarGpioPinNumGet(MV_BOARD_GPP_CLASS class, MV_U32 index) -+{ -+ MV_U32 boardId, i; -+ MV_U32 indexFound = 0; -+ -+ boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardRTCGpioPinGet:Board unknown.\n"); -+ return MV_ERROR; -+ -+ } -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardGppInfo; i++) -+ if (BOARD_INFO(boardId)->pBoardGppInfo[i].devClass == class) { -+ if (indexFound == index) -+ return (MV_U32)BOARD_INFO(boardId)->pBoardGppInfo[i].gppPinNum; -+ else -+ indexFound++; -+ -+ } -+ -+ return MV_ERROR; -+} -+ -+ -+/******************************************************************************* -+* mvBoardRTCGpioPinGet - mvBoardRTCGpioPinGet -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* GPIO pin number. The function return -1 for bad parameters. -+* -+*******************************************************************************/ -+MV_32 mvBoardRTCGpioPinGet(MV_VOID) -+{ -+ return mvBoarGpioPinNumGet(BOARD_GPP_RTC, 0); -+} -+ -+ -+/******************************************************************************* -+* mvBoardReset - mvBoardReset -+* -+* DESCRIPTION: -+* Reset the board -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None -+* -+*******************************************************************************/ -+MV_VOID mvBoardReset(MV_VOID) -+{ -+ MV_32 resetPin; -+ -+ /* Get gpp reset pin if define */ -+ resetPin = mvBoardResetGpioPinGet(); -+ if (resetPin != MV_ERROR) -+ { -+ MV_REG_BIT_RESET( GPP_DATA_OUT_REG(0) ,(1 << resetPin)); -+ MV_REG_BIT_RESET( GPP_DATA_OUT_EN_REG(0) ,(1 << resetPin)); -+ -+ } -+ else -+ { -+ /* No gpp reset pin was found, try to reset ussing -+ system reset out */ -+ MV_REG_BIT_SET( CPU_RSTOUTN_MASK_REG , BIT2); -+ MV_REG_BIT_SET( CPU_SYS_SOFT_RST_REG , BIT0); -+ } -+} -+ -+/******************************************************************************* -+* mvBoardResetGpioPinGet - mvBoardResetGpioPinGet -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* GPIO pin number. The function return -1 for bad parameters. -+* -+*******************************************************************************/ -+MV_32 mvBoardResetGpioPinGet(MV_VOID) -+{ -+ return mvBoarGpioPinNumGet(BOARD_GPP_RESET, 0); -+} -+/******************************************************************************* -+* mvBoardSDIOGpioPinGet - mvBoardSDIOGpioPinGet -+* -+* DESCRIPTION: -+* used for hotswap detection -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* GPIO pin number. The function return -1 for bad parameters. -+* -+*******************************************************************************/ -+MV_32 mvBoardSDIOGpioPinGet(MV_VOID) -+{ -+ return mvBoarGpioPinNumGet(BOARD_GPP_SDIO_DETECT, 0); -+} -+ -+/******************************************************************************* -+* mvBoardUSBVbusGpioPinGet - return Vbus input GPP -+* -+* DESCRIPTION: -+* -+* INPUT: -+* int devNo. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* GPIO pin number. The function return -1 for bad parameters. -+* -+*******************************************************************************/ -+MV_32 mvBoardUSBVbusGpioPinGet(MV_32 devId) -+{ -+ return mvBoarGpioPinNumGet(BOARD_GPP_USB_VBUS, devId); -+} -+ -+/******************************************************************************* -+* mvBoardUSBVbusEnGpioPinGet - return Vbus Enable output GPP -+* -+* DESCRIPTION: -+* -+* INPUT: -+* int devNo. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* GPIO pin number. The function return -1 for bad parameters. -+* -+*******************************************************************************/ -+MV_32 mvBoardUSBVbusEnGpioPinGet(MV_32 devId) -+{ -+ return mvBoarGpioPinNumGet(BOARD_GPP_USB_VBUS_EN, devId); -+} -+ -+ -+/******************************************************************************* -+* mvBoardGpioIntMaskGet - Get GPIO mask for interrupt pins -+* -+* DESCRIPTION: -+* This function returns a 32-bit mask of GPP pins that connected to -+* interrupt generating sources on board. -+* For example if UART channel A is hardwired to GPP pin 8 and -+* UART channel B is hardwired to GPP pin 4 the fuinction will return -+* the value 0x000000110 -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* See description. The function return -1 if board is not identified. -+* -+*******************************************************************************/ -+MV_32 mvBoardGpioIntMaskLowGet(MV_VOID) -+{ -+ MV_U32 boardId; -+ -+ boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardGpioIntMaskGet:Board unknown.\n"); -+ return MV_ERROR; -+ -+ } -+ -+ return BOARD_INFO(boardId)->intsGppMaskLow; -+} -+MV_32 mvBoardGpioIntMaskHighGet(MV_VOID) -+{ -+ MV_U32 boardId; -+ -+ boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardGpioIntMaskGet:Board unknown.\n"); -+ return MV_ERROR; -+ -+ } -+ -+ return BOARD_INFO(boardId)->intsGppMaskHigh; -+} -+ -+ -+/******************************************************************************* -+* mvBoardMppGet - Get board dependent MPP register value -+* -+* DESCRIPTION: -+* MPP settings are derived from board design. -+* MPP group consist of 8 MPPs. An MPP group represent MPP -+* control register. -+* This function retrieves board dependend MPP register value. -+* -+* INPUT: -+* mppGroupNum - MPP group number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit value describing MPP control register value. -+* -+*******************************************************************************/ -+MV_32 mvBoardMppGet(MV_U32 mppGroupNum) -+{ -+ MV_U32 boardId; -+ -+ boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardMppGet:Board unknown.\n"); -+ return MV_ERROR; -+ -+ } -+ -+ return BOARD_INFO(boardId)->pBoardMppConfigValue[0].mppGroup[mppGroupNum]; -+} -+ -+ -+/******************************************************************************* -+* mvBoardMppGroupId - If MPP group type is AUTO then identify it using twsi -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_VOID mvBoardMppGroupIdUpdate(MV_VOID) -+{ -+ -+ MV_BOARD_MPP_GROUP_CLASS devClass; -+ MV_BOARD_MODULE_ID_CLASS devClassId; -+ MV_BOARD_MPP_TYPE_CLASS mppGroupType; -+ MV_U32 devId; -+ MV_U32 maxMppGrp = 1; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ maxMppGrp = MV_6281_MPP_MAX_MODULE; -+ break; -+ case MV_6192_DEV_ID: -+ maxMppGrp = MV_6192_MPP_MAX_MODULE; -+ break; -+ case MV_6190_DEV_ID: -+ maxMppGrp = MV_6190_MPP_MAX_MODULE; -+ break; -+ case MV_6180_DEV_ID: -+ maxMppGrp = MV_6180_MPP_MAX_MODULE; -+ break; -+ } -+ -+ for (devClass = 0; devClass < maxMppGrp; devClass++) -+ { -+ /* If MPP group can be defined by the module connected to it */ -+ if (mvBoardMppGroupTypeGet(devClass) == MV_BOARD_AUTO) -+ { -+ /* Get MPP module ID */ -+ devClassId = mvBoarModuleTypeGet(devClass); -+ if (MV_ERROR != devClassId) -+ { -+ switch(devClassId) -+ { -+ case MV_BOARD_MODULE_TDM_ID: -+ case MV_BOARD_MODULE_TDM_5CHAN_ID: -+ mppGroupType = MV_BOARD_TDM; -+ break; -+ case MV_BOARD_MODULE_AUDIO_ID: -+ mppGroupType = MV_BOARD_AUDIO; -+ break; -+ case MV_BOARD_MODULE_RGMII_ID: -+ mppGroupType = MV_BOARD_RGMII; -+ break; -+ case MV_BOARD_MODULE_GMII_ID: -+ mppGroupType = MV_BOARD_GMII; -+ break; -+ case MV_BOARD_MODULE_TS_ID: -+ mppGroupType = MV_BOARD_TS; -+ break; -+ case MV_BOARD_MODULE_MII_ID: -+ mppGroupType = MV_BOARD_MII; -+ break; -+ default: -+ mppGroupType = MV_BOARD_OTHER; -+ break; -+ } -+ } -+ else -+ /* The module bay is empty */ -+ mppGroupType = MV_BOARD_OTHER; -+ -+ /* Update MPP group type */ -+ mvBoardMppGroupTypeSet(devClass, mppGroupType); -+ } -+ -+ /* Update MPP output voltage for RGMII 1.8V. Set port to GMII for GMII module */ -+ if ((mvBoardMppGroupTypeGet(devClass) == MV_BOARD_RGMII)) -+ MV_REG_BIT_SET(MPP_OUTPUT_DRIVE_REG,MPP_1_8_RGMII1_OUTPUT_DRIVE | MPP_1_8_RGMII0_OUTPUT_DRIVE); -+ else -+ { -+ if ((mvBoardMppGroupTypeGet(devClass) == MV_BOARD_GMII)) -+ { -+ MV_REG_BIT_RESET(MPP_OUTPUT_DRIVE_REG, BIT7 | BIT15); -+ MV_REG_BIT_RESET(ETH_PORT_SERIAL_CTRL_1_REG(0),BIT3); -+ MV_REG_BIT_RESET(ETH_PORT_SERIAL_CTRL_1_REG(1),BIT3); -+ } -+ else if ((mvBoardMppGroupTypeGet(devClass) == MV_BOARD_MII)) -+ { -+ /* Assumption that the MDC & MDIO should be 3.3V */ -+ MV_REG_BIT_RESET(MPP_OUTPUT_DRIVE_REG, BIT7 | BIT15); -+ /* Assumption that only ETH1 can be MII when using modules on DB */ -+ MV_REG_BIT_RESET(ETH_PORT_SERIAL_CTRL_1_REG(1),BIT3); -+ } -+ } -+ } -+} -+ -+/******************************************************************************* -+* mvBoardMppGroupTypeGet -+* -+* DESCRIPTION: -+* -+* INPUT: -+* mppGroupClass - MPP group number 0 for MPP[35:20] or 1 for MPP[49:36]. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_BOARD_MPP_TYPE_CLASS mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass) -+{ -+ MV_U32 boardId; -+ -+ boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardMppGet:Board unknown.\n"); -+ return MV_ERROR; -+ -+ } -+ -+ if (mppGroupClass == MV_BOARD_MPP_GROUP_1) -+ return BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup1; -+ else -+ return BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup2; -+} -+ -+/******************************************************************************* -+* mvBoardMppGroupTypeSet -+* -+* DESCRIPTION: -+* -+* INPUT: -+* mppGroupClass - MPP group number 0 for MPP[35:20] or 1 for MPP[49:36]. -+* mppGroupType - MPP group type for MPP[35:20] or for MPP[49:36]. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_VOID mvBoardMppGroupTypeSet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass, -+ MV_BOARD_MPP_TYPE_CLASS mppGroupType) -+{ -+ MV_U32 boardId; -+ -+ boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardMppGet:Board unknown.\n"); -+ } -+ -+ if (mppGroupClass == MV_BOARD_MPP_GROUP_1) -+ BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup1 = mppGroupType; -+ else -+ BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup2 = mppGroupType; -+ -+} -+ -+/******************************************************************************* -+* mvBoardMppMuxSet - Update MPP mux -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_VOID mvBoardMppMuxSet(MV_VOID) -+{ -+ -+ MV_BOARD_MPP_GROUP_CLASS devClass; -+ MV_BOARD_MPP_TYPE_CLASS mppGroupType; -+ MV_U32 devId; -+ MV_U8 muxVal = 0xf; -+ MV_U32 maxMppGrp = 1; -+ MV_TWSI_SLAVE twsiSlave; -+ MV_TWSI_ADDR slave; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ maxMppGrp = MV_6281_MPP_MAX_MODULE; -+ break; -+ case MV_6192_DEV_ID: -+ maxMppGrp = MV_6192_MPP_MAX_MODULE; -+ break; -+ case MV_6190_DEV_ID: -+ maxMppGrp = MV_6190_MPP_MAX_MODULE; -+ break; -+ case MV_6180_DEV_ID: -+ maxMppGrp = MV_6180_MPP_MAX_MODULE; -+ break; -+ } -+ -+ for (devClass = 0; devClass < maxMppGrp; devClass++) -+ { -+ mppGroupType = mvBoardMppGroupTypeGet(devClass); -+ -+ switch(mppGroupType) -+ { -+ case MV_BOARD_TDM: -+ muxVal &= ~(devClass ? (0x2 << (devClass * 2)):0x0); -+ break; -+ case MV_BOARD_AUDIO: -+ muxVal &= ~(devClass ? 0x7 : 0x0); /*old Z0 value 0xd:0x0*/ -+ break; -+ case MV_BOARD_TS: -+ muxVal &= ~(devClass ? (0x2 << (devClass * 2)):0x0); -+ break; -+ default: -+ muxVal |= (devClass ? 0xf : 0); -+ break; -+ } -+ } -+ -+ /* TWSI init */ -+ slave.type = ADDR7_BIT; -+ slave.address = 0; -+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); -+ -+ /* Read MPP module ID */ -+ DB(mvOsPrintf("Board: twsi exp set\n")); -+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(MV_BOARD_MUX_I2C_ADDR_ENTRY); -+ twsiSlave.slaveAddr.type = mvBoardTwsiExpAddrTypeGet(MV_BOARD_MUX_I2C_ADDR_ENTRY); -+ twsiSlave.validOffset = MV_TRUE; -+ /* Offset is the first command after the address which indicate the register number to be read -+ in next operation */ -+ twsiSlave.offset = 2; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ -+ -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) -+ { -+ DB(mvOsPrintf("Board: twsi exp out val fail\n")); -+ return; -+ } -+ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); -+ -+ /* Change twsi exp to output */ -+ twsiSlave.offset = 6; -+ muxVal = 0; -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) -+ { -+ DB(mvOsPrintf("Board: twsi exp change to out fail\n")); -+ return; -+ } -+ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); -+ -+} -+ -+/******************************************************************************* -+* mvBoardTdmMppSet - set MPPs in TDM module -+* -+* DESCRIPTION: -+* -+* INPUT: type of second telephony device -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_VOID mvBoardTdmMppSet(MV_32 chType) -+{ -+ -+ MV_BOARD_MPP_GROUP_CLASS devClass; -+ MV_BOARD_MPP_TYPE_CLASS mppGroupType; -+ MV_U32 devId; -+ MV_U8 muxVal = 1; -+ MV_U8 muxValMask = 1; -+ MV_U8 twsiVal; -+ MV_U32 maxMppGrp = 1; -+ MV_TWSI_SLAVE twsiSlave; -+ MV_TWSI_ADDR slave; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ maxMppGrp = MV_6281_MPP_MAX_MODULE; -+ break; -+ case MV_6192_DEV_ID: -+ maxMppGrp = MV_6192_MPP_MAX_MODULE; -+ break; -+ case MV_6190_DEV_ID: -+ maxMppGrp = MV_6190_MPP_MAX_MODULE; -+ break; -+ case MV_6180_DEV_ID: -+ maxMppGrp = MV_6180_MPP_MAX_MODULE; -+ break; -+ } -+ -+ for (devClass = 0; devClass < maxMppGrp; devClass++) -+ { -+ mppGroupType = mvBoardMppGroupTypeGet(devClass); -+ if(mppGroupType == MV_BOARD_TDM) -+ break; -+ } -+ -+ if(devClass == maxMppGrp) -+ return; /* TDM module not found */ -+ -+ /* TWSI init */ -+ slave.type = ADDR7_BIT; -+ slave.address = 0; -+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); -+ -+ /* Read MPP module ID */ -+ DB(mvOsPrintf("Board: twsi exp set\n")); -+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(devClass); -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ /* Offset is the first command after the address which indicate the register number to be read -+ in next operation */ -+ twsiSlave.offset = 3; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ if(mvBoardIdGet() == RD_88F6281A_ID) -+ { -+ muxVal = 0xc; -+ muxValMask = 0xf3; -+ } -+ -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ muxVal = (twsiVal & muxValMask) | muxVal; -+ -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) -+ { -+ mvOsPrintf("Board: twsi exp out val fail\n"); -+ return; -+ } -+ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); -+ -+ /* Change twsi exp to output */ -+ twsiSlave.offset = 7; -+ muxVal = 0xfe; -+ if(mvBoardIdGet() == RD_88F6281A_ID) -+ muxVal = 0xf3; -+ -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ muxVal = (twsiVal & muxVal); -+ -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) -+ { -+ mvOsPrintf("Board: twsi exp change to out fail\n"); -+ return; -+ } -+ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); -+ /* reset the line to 0 */ -+ twsiSlave.offset = 3; -+ muxVal = 0; -+ muxValMask = 1; -+ -+ if(mvBoardIdGet() == RD_88F6281A_ID) { -+ muxVal = 0x0; -+ muxValMask = 0xf3; -+ } -+ -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ muxVal = (twsiVal & muxValMask) | muxVal; -+ -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) -+ { -+ mvOsPrintf("Board: twsi exp out val fail\n"); -+ return; -+ } -+ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); -+ -+ mvOsDelay(20); -+ -+ /* set the line to 1 */ -+ twsiSlave.offset = 3; -+ muxVal = 1; -+ muxValMask = 1; -+ -+ if(mvBoardIdGet() == RD_88F6281A_ID) -+ { -+ muxVal = 0xc; -+ muxValMask = 0xf3; -+ if(chType) /* FXS - issue reset properly */ -+ { -+ MV_REG_BIT_SET(GPP_DATA_OUT_REG(1), MV_GPP12); -+ mvOsDelay(50); -+ MV_REG_BIT_RESET(GPP_DATA_OUT_REG(1), MV_GPP12); -+ } -+ else /* FXO - issue reset via TDM_CODEC_RST*/ -+ { -+ /* change MPP44 type to TDM_CODEC_RST(0x2) */ -+ MV_REG_WRITE(MPP_CONTROL_REG5, ((MV_REG_READ(MPP_CONTROL_REG5) & 0xFFF0FFFF) | BIT17)); -+ } -+ } -+ -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ muxVal = (twsiVal & muxValMask) | muxVal; -+ -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) -+ { -+ mvOsPrintf("Board: twsi exp out val fail\n"); -+ return; -+ } -+ -+ /* TBD - 5 channels */ -+#if defined(MV_TDM_5CHANNELS) -+ /* change MPP38 type to GPIO(0x0) & polarity for TDM_STROBE */ -+ MV_REG_WRITE(MPP_CONTROL_REG4, (MV_REG_READ(MPP_CONTROL_REG4) & 0xF0FFFFFF)); -+ mvGppPolaritySet(1, MV_GPP6, 0); -+ -+ twsiSlave.offset = 6; -+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(2); -+ -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ muxVal = (twsiVal & ~BIT2); -+ -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) -+ { -+ mvOsPrintf("Board: twsi exp change to out fail\n"); -+ return; -+ } -+ -+ -+ twsiSlave.offset = 2; -+ -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ muxVal = (twsiVal & ~BIT2); -+ -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) -+ { -+ mvOsPrintf("Board: twsi exp change to out fail\n"); -+ return; -+ } -+#endif -+ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); -+ -+ -+} -+/******************************************************************************* -+* mvBoardVoiceConnModeGet - return SLIC/DAA connection & interrupt modes -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+ -+MV_VOID mvBoardVoiceConnModeGet(MV_32* connMode, MV_32* irqMode) -+{ -+ switch(mvBoardIdGet()) -+ { -+ case RD_88F6281A_ID: -+ *connMode = DAISY_CHAIN_MODE; -+ *irqMode = INTERRUPT_TO_TDM; -+ break; -+ case DB_88F6281A_BP_ID: -+ *connMode = DUAL_CHIP_SELECT_MODE; -+ *irqMode = INTERRUPT_TO_TDM; -+ break; -+ case RD_88F6192A_ID: -+ *connMode = DUAL_CHIP_SELECT_MODE; -+ *irqMode = INTERRUPT_TO_TDM; -+ break; -+ case DB_88F6192A_BP_ID: -+ *connMode = DUAL_CHIP_SELECT_MODE; -+ *irqMode = INTERRUPT_TO_TDM; -+ break; -+ default: -+ *connMode = *irqMode = -1; -+ mvOsPrintf("mvBoardVoiceAssembleModeGet: TDM not supported(boardId=0x%x)\n",mvBoardIdGet()); -+ } -+ return; -+ -+} -+ -+/******************************************************************************* -+* mvBoardMppModuleTypePrint - print module detect -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_VOID mvBoardMppModuleTypePrint(MV_VOID) -+{ -+ -+ MV_BOARD_MPP_GROUP_CLASS devClass; -+ MV_BOARD_MPP_TYPE_CLASS mppGroupType; -+ MV_U32 devId; -+ MV_U32 maxMppGrp = 1; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ maxMppGrp = MV_6281_MPP_MAX_MODULE; -+ break; -+ case MV_6192_DEV_ID: -+ maxMppGrp = MV_6192_MPP_MAX_MODULE; -+ break; -+ case MV_6190_DEV_ID: -+ maxMppGrp = MV_6190_MPP_MAX_MODULE; -+ break; -+ case MV_6180_DEV_ID: -+ maxMppGrp = MV_6180_MPP_MAX_MODULE; -+ break; -+ } -+ -+ for (devClass = 0; devClass < maxMppGrp; devClass++) -+ { -+ mppGroupType = mvBoardMppGroupTypeGet(devClass); -+ -+ switch(mppGroupType) -+ { -+ case MV_BOARD_TDM: -+ if(devId != MV_6190_DEV_ID) -+ mvOsPrintf("Module %d is TDM\n", devClass); -+ break; -+ case MV_BOARD_AUDIO: -+ if(devId != MV_6190_DEV_ID) -+ mvOsPrintf("Module %d is AUDIO\n", devClass); -+ break; -+ case MV_BOARD_RGMII: -+ if(devId != MV_6190_DEV_ID) -+ mvOsPrintf("Module %d is RGMII\n", devClass); -+ break; -+ case MV_BOARD_GMII: -+ if(devId != MV_6190_DEV_ID) -+ mvOsPrintf("Module %d is GMII\n", devClass); -+ break; -+ case MV_BOARD_TS: -+ if(devId != MV_6190_DEV_ID) -+ mvOsPrintf("Module %d is TS\n", devClass); -+ break; -+ default: -+ break; -+ } -+ } -+} -+ -+/* Board devices API managments */ -+ -+/******************************************************************************* -+* mvBoardGetDeviceNumber - Get number of device of some type on the board -+* -+* DESCRIPTION: -+* -+* INPUT: -+* devType - The device type ( Flash,RTC , etc .. ) -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* If the device is found on the board the then the functions returns the -+* number of those devices else the function returns 0 -+* -+* -+*******************************************************************************/ -+MV_32 mvBoardGetDevicesNumber(MV_BOARD_DEV_CLASS devClass) -+{ -+ MV_U32 foundIndex=0,devNum; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardGetDeviceNumber:Board unknown.\n"); -+ return 0xFFFFFFFF; -+ -+ } -+ -+ for (devNum = START_DEV_CS; devNum < BOARD_INFO(boardId)->numBoardDeviceIf; devNum++) -+ { -+ if (BOARD_INFO(boardId)->pDevCsInfo[devNum].devClass == devClass) -+ { -+ foundIndex++; -+ } -+ } -+ -+ return foundIndex; -+ -+} -+ -+/******************************************************************************* -+* mvBoardGetDeviceBaseAddr - Get base address of a device existing on the board -+* -+* DESCRIPTION: -+* -+* INPUT: -+* devIndex - The device sequential number on the board -+* devType - The device type ( Flash,RTC , etc .. ) -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* If the device is found on the board the then the functions returns the -+* Base address else the function returns 0xffffffff -+* -+* -+*******************************************************************************/ -+MV_32 mvBoardGetDeviceBaseAddr(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) -+{ -+ MV_DEV_CS_INFO* devEntry; -+ devEntry = boardGetDevEntry(devNum,devClass); -+ if (devEntry != NULL) -+ { -+ return mvCpuIfTargetWinBaseLowGet(DEV_TO_TARGET(devEntry->deviceCS)); -+ -+ } -+ -+ return 0xFFFFFFFF; -+} -+ -+/******************************************************************************* -+* mvBoardGetDeviceBusWidth - Get Bus width of a device existing on the board -+* -+* DESCRIPTION: -+* -+* INPUT: -+* devIndex - The device sequential number on the board -+* devType - The device type ( Flash,RTC , etc .. ) -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* If the device is found on the board the then the functions returns the -+* Bus width else the function returns 0xffffffff -+* -+* -+*******************************************************************************/ -+MV_32 mvBoardGetDeviceBusWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) -+{ -+ MV_DEV_CS_INFO* devEntry; -+ -+ devEntry = boardGetDevEntry(devNum,devClass); -+ if (devEntry != NULL) -+ { -+ return 8; -+ } -+ -+ return 0xFFFFFFFF; -+ -+} -+ -+/******************************************************************************* -+* mvBoardGetDeviceWidth - Get dev width of a device existing on the board -+* -+* DESCRIPTION: -+* -+* INPUT: -+* devIndex - The device sequential number on the board -+* devType - The device type ( Flash,RTC , etc .. ) -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* If the device is found on the board the then the functions returns the -+* dev width else the function returns 0xffffffff -+* -+* -+*******************************************************************************/ -+MV_32 mvBoardGetDeviceWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) -+{ -+ MV_DEV_CS_INFO* devEntry; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("Board unknown.\n"); -+ return 0xFFFFFFFF; -+ } -+ -+ devEntry = boardGetDevEntry(devNum,devClass); -+ if (devEntry != NULL) -+ return devEntry->devWidth; -+ -+ return MV_ERROR; -+ -+} -+ -+/******************************************************************************* -+* mvBoardGetDeviceWinSize - Get the window size of a device existing on the board -+* -+* DESCRIPTION: -+* -+* INPUT: -+* devIndex - The device sequential number on the board -+* devType - The device type ( Flash,RTC , etc .. ) -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* If the device is found on the board the then the functions returns the -+* window size else the function returns 0xffffffff -+* -+* -+*******************************************************************************/ -+MV_32 mvBoardGetDeviceWinSize(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) -+{ -+ MV_DEV_CS_INFO* devEntry; -+ MV_U32 boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("Board unknown.\n"); -+ return 0xFFFFFFFF; -+ } -+ -+ devEntry = boardGetDevEntry(devNum,devClass); -+ if (devEntry != NULL) -+ { -+ return mvCpuIfTargetWinSizeGet(DEV_TO_TARGET(devEntry->deviceCS)); -+ } -+ -+ return 0xFFFFFFFF; -+} -+ -+ -+/******************************************************************************* -+* boardGetDevEntry - returns the entry pointer of a device on the board -+* -+* DESCRIPTION: -+* -+* INPUT: -+* devIndex - The device sequential number on the board -+* devType - The device type ( Flash,RTC , etc .. ) -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* If the device is found on the board the then the functions returns the -+* dev number else the function returns 0x0 -+* -+* -+*******************************************************************************/ -+static MV_DEV_CS_INFO* boardGetDevEntry(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) -+{ -+ MV_U32 foundIndex=0,devIndex; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("boardGetDevEntry: Board unknown.\n"); -+ return NULL; -+ -+ } -+ -+ for (devIndex = START_DEV_CS; devIndex < BOARD_INFO(boardId)->numBoardDeviceIf; devIndex++) -+ { -+ /* TBR */ -+ /*if (BOARD_INFO(boardId)->pDevCsInfo[devIndex].deviceCS == MV_BOOTDEVICE_INDEX) -+ continue;*/ -+ -+ if (BOARD_INFO(boardId)->pDevCsInfo[devIndex].devClass == devClass) -+ { -+ if (foundIndex == devNum) -+ { -+ return &(BOARD_INFO(boardId)->pDevCsInfo[devIndex]); -+ } -+ foundIndex++; -+ } -+ } -+ -+ /* device not found */ -+ return NULL; -+} -+ -+/* Get device CS number */ -+ -+MV_U32 boardGetDevCSNum(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) -+{ -+ MV_DEV_CS_INFO* devEntry; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("Board unknown.\n"); -+ return 0xFFFFFFFF; -+ -+ } -+ -+ -+ devEntry = boardGetDevEntry(devNum,devClass); -+ if (devEntry != NULL) -+ return devEntry->deviceCS; -+ -+ return 0xFFFFFFFF; -+ -+} -+ -+/******************************************************************************* -+* mvBoardRtcTwsiAddrTypeGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_U8 mvBoardRtcTwsiAddrTypeGet() -+{ -+ int i; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) -+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_RTC) -+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; -+ return (MV_ERROR); -+} -+ -+/******************************************************************************* -+* mvBoardRtcTwsiAddrGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_U8 mvBoardRtcTwsiAddrGet() -+{ -+ int i; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) -+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_RTC) -+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; -+ return (0xFF); -+} -+ -+/******************************************************************************* -+* mvBoardA2DTwsiAddrTypeGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_U8 mvBoardA2DTwsiAddrTypeGet() -+{ -+ int i; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) -+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_AUDIO_DEC) -+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; -+ return (MV_ERROR); -+} -+ -+/******************************************************************************* -+* mvBoardA2DTwsiAddrGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_U8 mvBoardA2DTwsiAddrGet() -+{ -+ int i; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) -+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_AUDIO_DEC) -+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; -+ return (0xFF); -+} -+ -+/******************************************************************************* -+* mvBoardTwsiExpAddrTypeGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_U8 mvBoardTwsiExpAddrTypeGet(MV_U32 index) -+{ -+ int i; -+ MV_U32 indexFound = 0; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) -+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_EXP) -+ { -+ if (indexFound == index) -+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; -+ else -+ indexFound++; -+ } -+ -+ return (MV_ERROR); -+} -+ -+/******************************************************************************* -+* mvBoardTwsiExpAddrGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_U8 mvBoardTwsiExpAddrGet(MV_U32 index) -+{ -+ int i; -+ MV_U32 indexFound = 0; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) -+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_EXP) -+ { -+ if (indexFound == index) -+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; -+ else -+ indexFound++; -+ } -+ -+ return (0xFF); -+} -+ -+ -+/******************************************************************************* -+* mvBoardTwsiSatRAddrTypeGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_U8 mvBoardTwsiSatRAddrTypeGet(MV_U32 index) -+{ -+ int i; -+ MV_U32 indexFound = 0; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) -+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_SATR) -+ { -+ if (indexFound == index) -+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; -+ else -+ indexFound++; -+ } -+ -+ return (MV_ERROR); -+} -+ -+/******************************************************************************* -+* mvBoardTwsiSatRAddrGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_U8 mvBoardTwsiSatRAddrGet(MV_U32 index) -+{ -+ int i; -+ MV_U32 indexFound = 0; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) -+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_SATR) -+ { -+ if (indexFound == index) -+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; -+ else -+ indexFound++; -+ } -+ -+ return (0xFF); -+} -+ -+/******************************************************************************* -+* mvBoardNandWidthGet - -+* -+* DESCRIPTION: Get the width of the first NAND device in byte. -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: 1, 2, 4 or MV_ERROR -+* -+* -+*******************************************************************************/ -+/* */ -+MV_32 mvBoardNandWidthGet(void) -+{ -+ MV_U32 devNum; -+ MV_U32 devWidth; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (devNum = START_DEV_CS; devNum < BOARD_INFO(boardId)->numBoardDeviceIf; devNum++) -+ { -+ devWidth = mvBoardGetDeviceWidth(devNum, BOARD_DEV_NAND_FLASH); -+ if (devWidth != MV_ERROR) -+ return (devWidth / 8); -+ } -+ -+ /* NAND wasn't found */ -+ return MV_ERROR; -+} -+ -+MV_U32 gBoardId = -1; -+ -+/******************************************************************************* -+* mvBoardIdGet - Get Board model -+* -+* DESCRIPTION: -+* This function returns board ID. -+* Board ID is 32bit word constructed of board model (16bit) and -+* board revision (16bit) in the following way: 0xMMMMRRRR. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit board ID number, '-1' if board is undefined. -+* -+*******************************************************************************/ -+MV_U32 mvBoardIdGet(MV_VOID) -+{ -+ MV_U32 tmpBoardId = -1; -+ -+ if(gBoardId == -1) -+ { -+ #if defined(DB_88F6281A) -+ tmpBoardId = DB_88F6281A_BP_ID; -+ #elif defined(RD_88F6281A) -+ tmpBoardId = RD_88F6281A_ID; -+ #elif defined(DB_88F6192A) -+ tmpBoardId = DB_88F6192A_BP_ID; -+ #elif defined(DB_88F6190A) -+ tmpBoardId = DB_88F6190A_BP_ID; -+ #elif defined(RD_88F6192A) -+ tmpBoardId = RD_88F6192A_ID; -+ #elif defined(RD_88F6190A) -+ tmpBoardId = RD_88F6190A_ID; -+ #elif defined(DB_88F6180A) -+ tmpBoardId = DB_88F6180A_BP_ID; -+ #elif defined(RD_88F6281A_PCAC) -+ tmpBoardId = RD_88F6281A_PCAC_ID; -+ #elif defined(RD_88F6281A_SHEEVA_PLUG) -+ tmpBoardId = SHEEVA_PLUG_ID; -+ #elif defined(DB_CUSTOMER) -+ tmpBoardId = DB_CUSTOMER_ID; -+ #endif -+ gBoardId = tmpBoardId; -+ } -+ -+ return gBoardId; -+} -+ -+ -+/******************************************************************************* -+* mvBoarModuleTypeGet - mvBoarModuleTypeGet -+* -+* DESCRIPTION: -+* -+* INPUT: -+* group num - MV_BOARD_MPP_GROUP_CLASS enum -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* module num - MV_BOARD_MODULE_CLASS enum -+* -+*******************************************************************************/ -+MV_BOARD_MODULE_ID_CLASS mvBoarModuleTypeGet(MV_BOARD_MPP_GROUP_CLASS devClass) -+{ -+ MV_TWSI_SLAVE twsiSlave; -+ MV_TWSI_ADDR slave; -+ MV_U8 data; -+ -+ /* TWSI init */ -+ slave.type = ADDR7_BIT; -+ slave.address = 0; -+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); -+ -+ /* Read MPP module ID */ -+ DB(mvOsPrintf("Board: Read MPP module ID\n")); -+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(devClass); -+ twsiSlave.slaveAddr.type = mvBoardTwsiExpAddrTypeGet(devClass); -+ twsiSlave.validOffset = MV_TRUE; -+ /* Offset is the first command after the address which indicate the register number to be read -+ in next operation */ -+ twsiSlave.offset = 0; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ -+ -+ if( MV_OK != mvTwsiRead (0, &twsiSlave, &data, 1) ) -+ { -+ DB(mvOsPrintf("Board: Read MPP module ID fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: Read MPP module ID succeded\n")); -+ -+ return data; -+} -+ -+/******************************************************************************* -+* mvBoarTwsiSatRGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* device num - one of three devices -+* reg num - 0 or 1 -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* reg value -+* -+*******************************************************************************/ -+MV_U8 mvBoarTwsiSatRGet(MV_U8 devNum, MV_U8 regNum) -+{ -+ MV_TWSI_SLAVE twsiSlave; -+ MV_TWSI_ADDR slave; -+ MV_U8 data; -+ -+ /* TWSI init */ -+ slave.type = ADDR7_BIT; -+ slave.address = 0; -+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); -+ -+ /* Read MPP module ID */ -+ DB(mvOsPrintf("Board: Read S@R device read\n")); -+ twsiSlave.slaveAddr.address = mvBoardTwsiSatRAddrGet(devNum); -+ twsiSlave.slaveAddr.type = mvBoardTwsiSatRAddrTypeGet(devNum); -+ twsiSlave.validOffset = MV_TRUE; -+ /* Use offset as command */ -+ twsiSlave.offset = regNum; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ if( MV_OK != mvTwsiRead (0, &twsiSlave, &data, 1) ) -+ { -+ DB(mvOsPrintf("Board: Read S@R fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: Read S@R succeded\n")); -+ -+ return data; -+} -+ -+/******************************************************************************* -+* mvBoarTwsiSatRSet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* devNum - one of three devices -+* regNum - 0 or 1 -+* regVal - value -+* -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* reg value -+* -+*******************************************************************************/ -+MV_STATUS mvBoarTwsiSatRSet(MV_U8 devNum, MV_U8 regNum, MV_U8 regVal) -+{ -+ MV_TWSI_SLAVE twsiSlave; -+ MV_TWSI_ADDR slave; -+ -+ /* TWSI init */ -+ slave.type = ADDR7_BIT; -+ slave.address = 0; -+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); -+ -+ /* Read MPP module ID */ -+ twsiSlave.slaveAddr.address = mvBoardTwsiSatRAddrGet(devNum); -+ twsiSlave.slaveAddr.type = mvBoardTwsiSatRAddrTypeGet(devNum); -+ twsiSlave.validOffset = MV_TRUE; -+ DB(mvOsPrintf("Board: Write S@R device addr %x, type %x, data %x\n", twsiSlave.slaveAddr.address,\ -+ twsiSlave.slaveAddr.type, regVal)); -+ /* Use offset as command */ -+ twsiSlave.offset = regNum; -+ twsiSlave.moreThen256 = MV_FALSE; -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, ®Val, 1) ) -+ { -+ DB(mvOsPrintf("Board: Write S@R fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: Write S@R succeded\n")); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvBoardSlicGpioPinGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_32 mvBoardSlicGpioPinGet(MV_U32 slicNum) -+{ -+ MV_U32 boardId; -+ boardId = mvBoardIdGet(); -+ -+ switch (boardId) -+ { -+ case DB_88F6281A_BP_ID: -+ case RD_88F6281A_ID: -+ default: -+ return MV_ERROR; -+ break; -+ -+ } -+} -+ -+/******************************************************************************* -+* mvBoardFanPowerControl - Turn on/off the fan power control on the RD-6281A -+* -+* DESCRIPTION: -+* -+* INPUT: -+* mode - MV_TRUE = on ; MV_FALSE = off -+* -+* OUTPUT: -+* MV_STATUS - MV_OK , MV_ERROR. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_STATUS mvBoardFanPowerControl(MV_BOOL mode) -+{ -+ -+ MV_U8 val = 1, twsiVal; -+ MV_TWSI_SLAVE twsiSlave; -+ MV_TWSI_ADDR slave; -+ -+ if(mvBoardIdGet() != RD_88F6281A_ID) -+ return MV_ERROR; -+ -+ /* TWSI init */ -+ slave.type = ADDR7_BIT; -+ slave.address = 0; -+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); -+ -+ /* Read MPP module ID */ -+ DB(mvOsPrintf("Board: twsi exp set\n")); -+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(1); -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ /* Offset is the first command after the address which indicate the register number to be read -+ in next operation */ -+ twsiSlave.offset = 3; -+ twsiSlave.moreThen256 = MV_FALSE; -+ if(mode == MV_TRUE) -+ val = 0x1; -+ else -+ val = 0; -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ val = (twsiVal & 0xfe) | val; -+ -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) -+ { -+ DB(mvOsPrintf("Board: twsi exp out val fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); -+ -+ /* Change twsi exp to output */ -+ twsiSlave.offset = 7; -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ val = (twsiVal & 0xfe); -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) -+ { -+ DB(mvOsPrintf("Board: twsi exp change to out fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvBoardHDDPowerControl - Turn on/off the HDD power control on the RD-6281A -+* -+* DESCRIPTION: -+* -+* INPUT: -+* mode - MV_TRUE = on ; MV_FALSE = off -+* -+* OUTPUT: -+* MV_STATUS - MV_OK , MV_ERROR. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_STATUS mvBoardHDDPowerControl(MV_BOOL mode) -+{ -+ -+ MV_U8 val = 1, twsiVal; -+ MV_TWSI_SLAVE twsiSlave; -+ MV_TWSI_ADDR slave; -+ -+ if(mvBoardIdGet() != RD_88F6281A_ID) -+ return MV_ERROR; -+ -+ /* TWSI init */ -+ slave.type = ADDR7_BIT; -+ slave.address = 0; -+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); -+ -+ /* Read MPP module ID */ -+ DB(mvOsPrintf("Board: twsi exp set\n")); -+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(1); -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ /* Offset is the first command after the address which indicate the register number to be read -+ in next operation */ -+ twsiSlave.offset = 3; -+ twsiSlave.moreThen256 = MV_FALSE; -+ if(mode == MV_TRUE) -+ val = 0x2; -+ else -+ val = 0; -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ val = (twsiVal & 0xfd) | val; -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) -+ { -+ DB(mvOsPrintf("Board: twsi exp out val fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); -+ -+ /* Change twsi exp to output */ -+ twsiSlave.offset = 7; -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ val = (twsiVal & 0xfd); -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) -+ { -+ DB(mvOsPrintf("Board: twsi exp change to out fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvBoardSDioWPControl - Turn on/off the SDIO WP on the RD-6281A -+* -+* DESCRIPTION: -+* -+* INPUT: -+* mode - MV_TRUE = on ; MV_FALSE = off -+* -+* OUTPUT: -+* MV_STATUS - MV_OK , MV_ERROR. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_STATUS mvBoardSDioWPControl(MV_BOOL mode) -+{ -+ -+ MV_U8 val = 1, twsiVal; -+ MV_TWSI_SLAVE twsiSlave; -+ MV_TWSI_ADDR slave; -+ -+ if(mvBoardIdGet() != RD_88F6281A_ID) -+ return MV_ERROR; -+ -+ /* TWSI init */ -+ slave.type = ADDR7_BIT; -+ slave.address = 0; -+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); -+ -+ /* Read MPP module ID */ -+ DB(mvOsPrintf("Board: twsi exp set\n")); -+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(0); -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ /* Offset is the first command after the address which indicate the register number to be read -+ in next operation */ -+ twsiSlave.offset = 3; -+ twsiSlave.moreThen256 = MV_FALSE; -+ if(mode == MV_TRUE) -+ val = 0x10; -+ else -+ val = 0; -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ val = (twsiVal & 0xef) | val; -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) -+ { -+ DB(mvOsPrintf("Board: twsi exp out val fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); -+ -+ /* Change twsi exp to output */ -+ twsiSlave.offset = 7; -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ val = (twsiVal & 0xef); -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) -+ { -+ DB(mvOsPrintf("Board: twsi exp change to out fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); -+ return MV_OK; -+} -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,376 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#ifndef __INCmvBoardEnvLibh -+#define __INCmvBoardEnvLibh -+ -+/* defines */ -+/* The below constant macros defines the board I2C EEPROM data offsets */ -+ -+ -+ -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "mvSysHwConfig.h" -+#include "boardEnv/mvBoardEnvSpec.h" -+ -+ -+/* DUART stuff for Tclk detection only */ -+#define DUART_BAUD_RATE 115200 -+#define MAX_CLOCK_MARGINE 5000000 /* Maximum detected clock margine */ -+ -+/* Voice devices assembly modes */ -+#define DAISY_CHAIN_MODE 1 -+#define DUAL_CHIP_SELECT_MODE 0 -+#define INTERRUPT_TO_MPP 1 -+#define INTERRUPT_TO_TDM 0 -+ -+ -+#define BOARD_ETH_PORT_NUM MV_ETH_MAX_PORTS -+#define BOARD_ETH_SWITCH_PORT_NUM 5 -+ -+#define MV_BOARD_MAX_USB_IF 1 -+#define MV_BOARD_MAX_MPP 7 -+#define MV_BOARD_NAME_LEN 0x20 -+ -+typedef struct _boardData -+{ -+ MV_U32 magic; -+ MV_U16 boardId; -+ MV_U8 boardVer; -+ MV_U8 boardRev; -+ MV_U32 reserved1; -+ MV_U32 reserved2; -+ -+}BOARD_DATA; -+ -+typedef enum _devBoardMppGroupClass -+{ -+ MV_BOARD_MPP_GROUP_1, -+ MV_BOARD_MPP_GROUP_2, -+ MV_BOARD_MAX_MPP_GROUP -+}MV_BOARD_MPP_GROUP_CLASS; -+ -+typedef enum _devBoardMppTypeClass -+{ -+ MV_BOARD_AUTO, -+ MV_BOARD_TDM, -+ MV_BOARD_AUDIO, -+ MV_BOARD_RGMII, -+ MV_BOARD_GMII, -+ MV_BOARD_TS, -+ MV_BOARD_MII, -+ MV_BOARD_OTHER -+}MV_BOARD_MPP_TYPE_CLASS; -+ -+typedef enum _devBoardModuleIdClass -+{ -+ MV_BOARD_MODULE_TDM_ID = 1, -+ MV_BOARD_MODULE_AUDIO_ID, -+ MV_BOARD_MODULE_RGMII_ID, -+ MV_BOARD_MODULE_GMII_ID, -+ MV_BOARD_MODULE_TS_ID, -+ MV_BOARD_MODULE_MII_ID, -+ MV_BOARD_MODULE_TDM_5CHAN_ID, -+ MV_BOARD_MODULE_OTHER_ID -+}MV_BOARD_MODULE_ID_CLASS; -+ -+typedef struct _boardMppTypeInfo -+{ -+ MV_BOARD_MPP_TYPE_CLASS boardMppGroup1; -+ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2; -+ -+}MV_BOARD_MPP_TYPE_INFO; -+ -+ -+typedef enum _devBoardClass -+{ -+ BOARD_DEV_NOR_FLASH, -+ BOARD_DEV_NAND_FLASH, -+ BOARD_DEV_SEVEN_SEG, -+ BOARD_DEV_FPGA, -+ BOARD_DEV_SRAM, -+ BOARD_DEV_SPI_FLASH, -+ BOARD_DEV_OTHER, -+}MV_BOARD_DEV_CLASS; -+ -+typedef enum _devTwsiBoardClass -+{ -+ BOARD_TWSI_RTC, -+ BOARD_DEV_TWSI_EXP, -+ BOARD_DEV_TWSI_SATR, -+ BOARD_TWSI_AUDIO_DEC, -+ BOARD_TWSI_OTHER -+}MV_BOARD_TWSI_CLASS; -+ -+typedef enum _devGppBoardClass -+{ -+ BOARD_GPP_RTC, -+ BOARD_GPP_MV_SWITCH, -+ BOARD_GPP_USB_VBUS, -+ BOARD_GPP_USB_VBUS_EN, -+ BOARD_GPP_USB_OC, -+ BOARD_GPP_USB_HOST_DEVICE, -+ BOARD_GPP_REF_CLCK, -+ BOARD_GPP_VOIP_SLIC, -+ BOARD_GPP_LIFELINE, -+ BOARD_GPP_BUTTON, -+ BOARD_GPP_TS_BUTTON_C, -+ BOARD_GPP_TS_BUTTON_U, -+ BOARD_GPP_TS_BUTTON_D, -+ BOARD_GPP_TS_BUTTON_L, -+ BOARD_GPP_TS_BUTTON_R, -+ BOARD_GPP_POWER_BUTTON, -+ BOARD_GPP_RESTOR_BUTTON, -+ BOARD_GPP_WPS_BUTTON, -+ BOARD_GPP_HDD0_POWER, -+ BOARD_GPP_HDD1_POWER, -+ BOARD_GPP_FAN_POWER, -+ BOARD_GPP_RESET, -+ BOARD_GPP_POWER_ON_LED, -+ BOARD_GPP_HDD_POWER, -+ BOARD_GPP_SDIO_POWER, -+ BOARD_GPP_SDIO_DETECT, -+ BOARD_GPP_SDIO_WP, -+ BOARD_GPP_SWITCH_PHY_INT, -+ BOARD_GPP_TSU_DIRCTION, -+ BOARD_GPP_OTHER -+}MV_BOARD_GPP_CLASS; -+ -+ -+typedef struct _devCsInfo -+{ -+ MV_U8 deviceCS; -+ MV_U32 params; -+ MV_U32 devClass; /* MV_BOARD_DEV_CLASS */ -+ MV_U8 devWidth; -+ -+}MV_DEV_CS_INFO; -+ -+ -+#define MV_BOARD_PHY_FORCE_10MB 0x0 -+#define MV_BOARD_PHY_FORCE_100MB 0x1 -+#define MV_BOARD_PHY_FORCE_1000MB 0x2 -+#define MV_BOARD_PHY_SPEED_AUTO 0x3 -+ -+typedef struct _boardSwitchInfo -+{ -+ MV_32 linkStatusIrq; -+ MV_32 qdPort[BOARD_ETH_SWITCH_PORT_NUM]; -+ MV_32 qdCpuPort; -+ MV_32 smiScanMode; /* 1 for SMI_MANUAL_MODE, 0 otherwise */ -+ MV_32 switchOnPort; -+ -+}MV_BOARD_SWITCH_INFO; -+ -+typedef struct _boardLedInfo -+{ -+ MV_U8 activeLedsNumber; -+ MV_U8 ledsPolarity; /* '0' or '1' to turn on led */ -+ MV_U8* gppPinNum; /* Pointer to GPP values */ -+ -+}MV_BOARD_LED_INFO; -+ -+typedef struct _boardGppInfo -+{ -+ MV_BOARD_GPP_CLASS devClass; -+ MV_U8 gppPinNum; -+ -+}MV_BOARD_GPP_INFO; -+ -+ -+typedef struct _boardTwsiInfo -+{ -+ MV_BOARD_TWSI_CLASS devClass; -+ MV_U8 twsiDevAddr; -+ MV_U8 twsiDevAddrType; -+ -+}MV_BOARD_TWSI_INFO; -+ -+ -+typedef enum _boardMacSpeed -+{ -+ BOARD_MAC_SPEED_10M, -+ BOARD_MAC_SPEED_100M, -+ BOARD_MAC_SPEED_1000M, -+ BOARD_MAC_SPEED_AUTO, -+ -+}MV_BOARD_MAC_SPEED; -+ -+typedef struct _boardMacInfo -+{ -+ MV_BOARD_MAC_SPEED boardMacSpeed; -+ MV_U8 boardEthSmiAddr; -+ -+}MV_BOARD_MAC_INFO; -+ -+typedef struct _boardMppInfo -+{ -+ MV_U32 mppGroup[MV_BOARD_MAX_MPP]; -+ -+}MV_BOARD_MPP_INFO; -+ -+typedef struct _boardInfo -+{ -+ char boardName[MV_BOARD_NAME_LEN]; -+ MV_U8 numBoardMppTypeValue; -+ MV_BOARD_MPP_TYPE_INFO* pBoardMppTypeValue; -+ MV_U8 numBoardMppConfigValue; -+ MV_BOARD_MPP_INFO* pBoardMppConfigValue; -+ MV_U32 intsGppMaskLow; -+ MV_U32 intsGppMaskHigh; -+ MV_U8 numBoardDeviceIf; -+ MV_DEV_CS_INFO* pDevCsInfo; -+ MV_U8 numBoardTwsiDev; -+ MV_BOARD_TWSI_INFO* pBoardTwsiDev; -+ MV_U8 numBoardMacInfo; -+ MV_BOARD_MAC_INFO* pBoardMacInfo; -+ MV_U8 numBoardGppInfo; -+ MV_BOARD_GPP_INFO* pBoardGppInfo; -+ MV_U8 activeLedsNumber; -+ MV_U8* pLedGppPin; -+ MV_U8 ledsPolarity; /* '0' or '1' to turn on led */ -+ /* GPP values */ -+ MV_U32 gppOutEnValLow; -+ MV_U32 gppOutEnValHigh; -+ MV_U32 gppOutValLow; -+ MV_U32 gppOutValHigh; -+ MV_U32 gppPolarityValLow; -+ MV_U32 gppPolarityValHigh; -+ -+ /* Switch Configuration */ -+ MV_BOARD_SWITCH_INFO* pSwitchInfo; -+}MV_BOARD_INFO; -+ -+ -+ -+MV_VOID mvBoardEnvInit(MV_VOID); -+MV_U32 mvBoardIdGet(MV_VOID); -+MV_U16 mvBoardModelGet(MV_VOID); -+MV_U16 mvBoardRevGet(MV_VOID); -+MV_STATUS mvBoardNameGet(char *pNameBuff); -+MV_32 mvBoardPhyAddrGet(MV_U32 ethPortNum); -+MV_BOARD_MAC_SPEED mvBoardMacSpeedGet(MV_U32 ethPortNum); -+MV_32 mvBoardLinkStatusIrqGet(MV_U32 ethPortNum); -+MV_32 mvBoardSwitchPortGet(MV_U32 ethPortNum, MV_U8 boardPortNum); -+MV_32 mvBoardSwitchCpuPortGet(MV_U32 ethPortNum); -+MV_32 mvBoardIsSwitchConnected(MV_U32 ethPortNum); -+MV_32 mvBoardSmiScanModeGet(MV_U32 ethPortNum); -+MV_BOOL mvBoardIsPortInSgmii(MV_U32 ethPortNum); -+MV_BOOL mvBoardIsPortInGmii(MV_VOID); -+MV_U32 mvBoardTclkGet(MV_VOID); -+MV_U32 mvBoardSysClkGet(MV_VOID); -+MV_U32 mvBoardDebugLedNumGet(MV_U32 boardId); -+MV_VOID mvBoardDebugLed(MV_U32 hexNum); -+MV_32 mvBoardMppGet(MV_U32 mppGroupNum); -+ -+MV_U8 mvBoardRtcTwsiAddrTypeGet(MV_VOID); -+MV_U8 mvBoardRtcTwsiAddrGet(MV_VOID); -+ -+MV_U8 mvBoardA2DTwsiAddrTypeGet(MV_VOID); -+MV_U8 mvBoardA2DTwsiAddrGet(MV_VOID); -+ -+MV_U8 mvBoardTwsiExpAddrGet(MV_U32 index); -+MV_U8 mvBoardTwsiSatRAddrTypeGet(MV_U32 index); -+MV_U8 mvBoardTwsiSatRAddrGet(MV_U32 index); -+MV_U8 mvBoardTwsiExpAddrTypeGet(MV_U32 index); -+MV_BOARD_MODULE_ID_CLASS mvBoarModuleTypeGet(MV_BOARD_MPP_GROUP_CLASS devClass); -+MV_BOARD_MPP_TYPE_CLASS mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass); -+MV_VOID mvBoardMppGroupTypeSet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass, -+ MV_BOARD_MPP_TYPE_CLASS mppGroupType); -+MV_VOID mvBoardMppGroupIdUpdate(MV_VOID); -+MV_VOID mvBoardMppMuxSet(MV_VOID); -+MV_VOID mvBoardTdmMppSet(MV_32 chType); -+MV_VOID mvBoardVoiceConnModeGet(MV_32* connMode, MV_32* irqMode); -+ -+MV_VOID mvBoardMppModuleTypePrint(MV_VOID); -+MV_VOID mvBoardReset(MV_VOID); -+MV_U8 mvBoarTwsiSatRGet(MV_U8 devNum, MV_U8 regNum); -+MV_STATUS mvBoarTwsiSatRSet(MV_U8 devNum, MV_U8 regNum, MV_U8 regVal); -+MV_BOOL mvBoardSpecInitGet(MV_U32* regOff, MV_U32* data); -+/* Board devices API managments */ -+MV_32 mvBoardGetDevicesNumber(MV_BOARD_DEV_CLASS devClass); -+MV_32 mvBoardGetDeviceBaseAddr(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); -+MV_32 mvBoardGetDeviceBusWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); -+MV_32 mvBoardGetDeviceWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); -+MV_32 mvBoardGetDeviceWinSize(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); -+MV_U32 boardGetDevCSNum(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); -+ -+/* Gpio Pin Connections API */ -+MV_32 mvBoardUSBVbusGpioPinGet(int devId); -+MV_32 mvBoardUSBVbusEnGpioPinGet(int devId); -+MV_U32 mvBoardPexBridgeIntPinGet(MV_U32 devNum, MV_U32 intPin); -+ -+MV_32 mvBoardResetGpioPinGet(MV_VOID); -+MV_32 mvBoardRTCGpioPinGet(MV_VOID); -+MV_32 mvBoardGpioIntMaskLowGet(MV_VOID); -+MV_32 mvBoardGpioIntMaskHighGet(MV_VOID); -+MV_32 mvBoardSlicGpioPinGet(MV_U32 slicNum); -+ -+MV_32 mvBoardSDIOGpioPinGet(MV_VOID); -+MV_STATUS mvBoardSDioWPControl(MV_BOOL mode); -+MV_32 mvBoarGpioPinNumGet(MV_BOARD_GPP_CLASS class, MV_U32 index); -+ -+MV_32 mvBoardNandWidthGet(void); -+MV_STATUS mvBoardFanPowerControl(MV_BOOL mode); -+MV_STATUS mvBoardHDDPowerControl(MV_BOOL mode); -+#endif /* __INCmvBoardEnvLibh */ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,848 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#include "mvCommon.h" -+#include "mvBoardEnvLib.h" -+#include "mvBoardEnvSpec.h" -+#include "twsi/mvTwsi.h" -+ -+#define DB_88F6281A_BOARD_PCI_IF_NUM 0x0 -+#define DB_88F6281A_BOARD_TWSI_DEF_NUM 0x7 -+#define DB_88F6281A_BOARD_MAC_INFO_NUM 0x2 -+#define DB_88F6281A_BOARD_GPP_INFO_NUM 0x3 -+#define DB_88F6281A_BOARD_MPP_CONFIG_NUM 0x1 -+#define DB_88F6281A_BOARD_MPP_GROUP_TYPE_NUM 0x1 -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ #define DB_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1 -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ #define DB_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x2 -+#else -+ #define DB_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1 -+#endif -+#define DB_88F6281A_BOARD_DEBUG_LED_NUM 0x0 -+ -+ -+MV_BOARD_TWSI_INFO db88f6281AInfoBoardTwsiDev[] = -+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ -+ { -+ {BOARD_DEV_TWSI_EXP, 0x20, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_EXP, 0x21, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_SATR, 0x4D, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_SATR, 0x4E, ADDR7_BIT}, -+ {BOARD_TWSI_AUDIO_DEC, 0x4A, ADDR7_BIT} -+ }; -+ -+MV_BOARD_MAC_INFO db88f6281AInfoBoardMacInfo[] = -+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ -+ { -+ {BOARD_MAC_SPEED_AUTO, 0x8}, -+ {BOARD_MAC_SPEED_AUTO, 0x9} -+ }; -+ -+MV_BOARD_MPP_TYPE_INFO db88f6281AInfoBoardMppTypeInfo[] = -+ /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, -+ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ -+ {{MV_BOARD_AUTO, MV_BOARD_AUTO} -+ }; -+ -+MV_BOARD_GPP_INFO db88f6281AInfoBoardGppInfo[] = -+ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ -+ { -+ {BOARD_GPP_TSU_DIRCTION, 33} -+ /*muxed with TDM/Audio module via IOexpender -+ {BOARD_GPP_SDIO_DETECT, 38}, -+ {BOARD_GPP_USB_VBUS, 49}*/ -+ }; -+ -+MV_DEV_CS_INFO db88f6281AInfoBoardDeCsInfo[] = -+ /*{deviceCS, params, devType, devWidth}*/ -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ { -+ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ -+ {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ -+ }; -+#else -+ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ -+#endif -+ -+MV_BOARD_MPP_INFO db88f6281AInfoBoardMppConfigValue[] = -+ {{{ -+ DB_88F6281A_MPP0_7, -+ DB_88F6281A_MPP8_15, -+ DB_88F6281A_MPP16_23, -+ DB_88F6281A_MPP24_31, -+ DB_88F6281A_MPP32_39, -+ DB_88F6281A_MPP40_47, -+ DB_88F6281A_MPP48_55 -+ }}}; -+ -+ -+MV_BOARD_INFO db88f6281AInfo = { -+ "DB-88F6281A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ -+ DB_88F6281A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ -+ db88f6281AInfoBoardMppTypeInfo, -+ DB_88F6281A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ db88f6281AInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ 0, /* intsGppMaskHigh */ -+ DB_88F6281A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ db88f6281AInfoBoardDeCsInfo, -+ DB_88F6281A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ db88f6281AInfoBoardTwsiDev, -+ DB_88F6281A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ db88f6281AInfoBoardMacInfo, -+ DB_88F6281A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ db88f6281AInfoBoardGppInfo, -+ DB_88F6281A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ NULL, -+ 0, /* ledsPolarity */ -+ DB_88F6281A_OE_LOW, /* gppOutEnLow */ -+ DB_88F6281A_OE_HIGH, /* gppOutEnHigh */ -+ DB_88F6281A_OE_VAL_LOW, /* gppOutValLow */ -+ DB_88F6281A_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ BIT6, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+ -+#define RD_88F6281A_BOARD_PCI_IF_NUM 0x0 -+#define RD_88F6281A_BOARD_TWSI_DEF_NUM 0x2 -+#define RD_88F6281A_BOARD_MAC_INFO_NUM 0x2 -+#define RD_88F6281A_BOARD_GPP_INFO_NUM 0x5 -+#define RD_88F6281A_BOARD_MPP_GROUP_TYPE_NUM 0x1 -+#define RD_88F6281A_BOARD_MPP_CONFIG_NUM 0x1 -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ #define RD_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1 -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ #define RD_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x2 -+#else -+ #define RD_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1 -+#endif -+#define RD_88F6281A_BOARD_DEBUG_LED_NUM 0x0 -+ -+MV_BOARD_MAC_INFO rd88f6281AInfoBoardMacInfo[] = -+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ -+ {{BOARD_MAC_SPEED_1000M, 0xa}, -+ {BOARD_MAC_SPEED_AUTO, 0xb} -+ }; -+ -+MV_BOARD_SWITCH_INFO rd88f6281AInfoBoardSwitchInfo[] = -+ /* MV_32 linkStatusIrq, {MV_32 qdPort0, MV_32 qdPort1, MV_32 qdPort2, MV_32 qdPort3, MV_32 qdPort4}, -+ MV_32 qdCpuPort, MV_32 smiScanMode, MV_32 switchOnPort} */ -+ {{38, {0, 1, 2, 3, -1}, 5, 2, 0}, -+ {-1, {-1}, -1, -1, -1}}; -+ -+MV_BOARD_TWSI_INFO rd88f6281AInfoBoardTwsiDev[] = -+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ -+ { -+ {BOARD_DEV_TWSI_EXP, 0xFF, ADDR7_BIT}, /* dummy entry to align with modules indexes */ -+ {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT} -+ }; -+ -+MV_BOARD_MPP_TYPE_INFO rd88f6281AInfoBoardMppTypeInfo[] = -+ {{MV_BOARD_RGMII, MV_BOARD_TDM} -+ }; -+ -+MV_DEV_CS_INFO rd88f6281AInfoBoardDeCsInfo[] = -+ /*{deviceCS, params, devType, devWidth}*/ -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ { -+ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ -+ {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ -+ }; -+#else -+ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ -+#endif -+ -+MV_BOARD_GPP_INFO rd88f6281AInfoBoardGppInfo[] = -+ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ -+ {{BOARD_GPP_SDIO_DETECT, 28}, -+ {BOARD_GPP_USB_OC, 29}, -+ {BOARD_GPP_WPS_BUTTON, 35}, -+ {BOARD_GPP_MV_SWITCH, 38}, -+ {BOARD_GPP_USB_VBUS, 49} -+ }; -+ -+MV_BOARD_MPP_INFO rd88f6281AInfoBoardMppConfigValue[] = -+ {{{ -+ RD_88F6281A_MPP0_7, -+ RD_88F6281A_MPP8_15, -+ RD_88F6281A_MPP16_23, -+ RD_88F6281A_MPP24_31, -+ RD_88F6281A_MPP32_39, -+ RD_88F6281A_MPP40_47, -+ RD_88F6281A_MPP48_55 -+ }}}; -+ -+MV_BOARD_INFO rd88f6281AInfo = { -+ "RD-88F6281A", /* boardName[MAX_BOARD_NAME_LEN] */ -+ RD_88F6281A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ -+ rd88f6281AInfoBoardMppTypeInfo, -+ RD_88F6281A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ rd88f6281AInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ (1 << 3), /* intsGppMaskHigh */ -+ RD_88F6281A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ rd88f6281AInfoBoardDeCsInfo, -+ RD_88F6281A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ rd88f6281AInfoBoardTwsiDev, -+ RD_88F6281A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ rd88f6281AInfoBoardMacInfo, -+ RD_88F6281A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ rd88f6281AInfoBoardGppInfo, -+ RD_88F6281A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ NULL, -+ 0, /* ledsPolarity */ -+ RD_88F6281A_OE_LOW, /* gppOutEnLow */ -+ RD_88F6281A_OE_HIGH, /* gppOutEnHigh */ -+ RD_88F6281A_OE_VAL_LOW, /* gppOutValLow */ -+ RD_88F6281A_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ BIT6, /* gppPolarityValHigh */ -+ rd88f6281AInfoBoardSwitchInfo /* pSwitchInfo */ -+}; -+ -+ -+#define DB_88F6192A_BOARD_PCI_IF_NUM 0x0 -+#define DB_88F6192A_BOARD_TWSI_DEF_NUM 0x7 -+#define DB_88F6192A_BOARD_MAC_INFO_NUM 0x2 -+#define DB_88F6192A_BOARD_GPP_INFO_NUM 0x3 -+#define DB_88F6192A_BOARD_MPP_GROUP_TYPE_NUM 0x1 -+#define DB_88F6192A_BOARD_MPP_CONFIG_NUM 0x1 -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ #define DB_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x1 -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ #define DB_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x2 -+#else -+ #define DB_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x1 -+#endif -+#define DB_88F6192A_BOARD_DEBUG_LED_NUM 0x0 -+ -+MV_BOARD_TWSI_INFO db88f6192AInfoBoardTwsiDev[] = -+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ -+ { -+ {BOARD_DEV_TWSI_EXP, 0x20, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_EXP, 0x21, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_SATR, 0x4D, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_SATR, 0x4E, ADDR7_BIT}, -+ {BOARD_TWSI_AUDIO_DEC, 0x4A, ADDR7_BIT} -+ }; -+ -+MV_BOARD_MAC_INFO db88f6192AInfoBoardMacInfo[] = -+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ -+ { -+ {BOARD_MAC_SPEED_AUTO, 0x8}, -+ {BOARD_MAC_SPEED_AUTO, 0x9} -+ }; -+ -+MV_BOARD_MPP_TYPE_INFO db88f6192AInfoBoardMppTypeInfo[] = -+ /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, -+ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ -+ {{MV_BOARD_AUTO, MV_BOARD_OTHER} -+ }; -+ -+MV_DEV_CS_INFO db88f6192AInfoBoardDeCsInfo[] = -+ /*{deviceCS, params, devType, devWidth}*/ -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ { -+ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ -+ {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ -+ }; -+#else -+ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ -+#endif -+ -+MV_BOARD_GPP_INFO db88f6192AInfoBoardGppInfo[] = -+ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ -+ { -+ {BOARD_GPP_SDIO_WP, 20}, -+ {BOARD_GPP_USB_VBUS, 22}, -+ {BOARD_GPP_SDIO_DETECT, 23}, -+ }; -+ -+MV_BOARD_MPP_INFO db88f6192AInfoBoardMppConfigValue[] = -+ {{{ -+ DB_88F6192A_MPP0_7, -+ DB_88F6192A_MPP8_15, -+ DB_88F6192A_MPP16_23, -+ DB_88F6192A_MPP24_31, -+ DB_88F6192A_MPP32_35 -+ }}}; -+ -+MV_BOARD_INFO db88f6192AInfo = { -+ "DB-88F6192A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ -+ DB_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ -+ db88f6192AInfoBoardMppTypeInfo, -+ DB_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ db88f6192AInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ (1 << 3), /* intsGppMaskHigh */ -+ DB_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ db88f6192AInfoBoardDeCsInfo, -+ DB_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ db88f6192AInfoBoardTwsiDev, -+ DB_88F6192A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ db88f6192AInfoBoardMacInfo, -+ DB_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ db88f6192AInfoBoardGppInfo, -+ DB_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ NULL, -+ 0, /* ledsPolarity */ -+ DB_88F6192A_OE_LOW, /* gppOutEnLow */ -+ DB_88F6192A_OE_HIGH, /* gppOutEnHigh */ -+ DB_88F6192A_OE_VAL_LOW, /* gppOutValLow */ -+ DB_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ 0, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+#define DB_88F6190A_BOARD_MAC_INFO_NUM 0x1 -+ -+MV_BOARD_INFO db88f6190AInfo = { -+ "DB-88F6190A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ -+ DB_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ -+ db88f6192AInfoBoardMppTypeInfo, -+ DB_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ db88f6192AInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ (1 << 3), /* intsGppMaskHigh */ -+ DB_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ db88f6192AInfoBoardDeCsInfo, -+ DB_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ db88f6192AInfoBoardTwsiDev, -+ DB_88F6190A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ db88f6192AInfoBoardMacInfo, -+ DB_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ db88f6192AInfoBoardGppInfo, -+ DB_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ NULL, -+ 0, /* ledsPolarity */ -+ DB_88F6192A_OE_LOW, /* gppOutEnLow */ -+ DB_88F6192A_OE_HIGH, /* gppOutEnHigh */ -+ DB_88F6192A_OE_VAL_LOW, /* gppOutValLow */ -+ DB_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ 0, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+#define RD_88F6192A_BOARD_PCI_IF_NUM 0x0 -+#define RD_88F6192A_BOARD_TWSI_DEF_NUM 0x0 -+#define RD_88F6192A_BOARD_MAC_INFO_NUM 0x1 -+#define RD_88F6192A_BOARD_GPP_INFO_NUM 0xE -+#define RD_88F6192A_BOARD_MPP_GROUP_TYPE_NUM 0x1 -+#define RD_88F6192A_BOARD_MPP_CONFIG_NUM 0x1 -+#define RD_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x1 -+#define RD_88F6192A_BOARD_DEBUG_LED_NUM 0x3 -+ -+MV_U8 rd88f6192AInfoBoardDebugLedIf[] = -+ {17, 28, 29}; -+ -+MV_BOARD_MAC_INFO rd88f6192AInfoBoardMacInfo[] = -+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ -+ {{BOARD_MAC_SPEED_AUTO, 0x8} -+ }; -+ -+MV_BOARD_MPP_TYPE_INFO rd88f6192AInfoBoardMppTypeInfo[] = -+ /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, -+ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ -+ {{MV_BOARD_OTHER, MV_BOARD_OTHER} -+ }; -+ -+MV_DEV_CS_INFO rd88f6192AInfoBoardDeCsInfo[] = -+ /*{deviceCS, params, devType, devWidth}*/ -+ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ -+ -+MV_BOARD_GPP_INFO rd88f6192AInfoBoardGppInfo[] = -+ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ -+ { -+ {BOARD_GPP_USB_VBUS_EN, 10}, -+ {BOARD_GPP_USB_HOST_DEVICE, 11}, -+ {BOARD_GPP_RESET, 14}, -+ {BOARD_GPP_POWER_ON_LED, 15}, -+ {BOARD_GPP_HDD_POWER, 16}, -+ {BOARD_GPP_WPS_BUTTON, 24}, -+ {BOARD_GPP_TS_BUTTON_C, 25}, -+ {BOARD_GPP_USB_VBUS, 26}, -+ {BOARD_GPP_USB_OC, 27}, -+ {BOARD_GPP_TS_BUTTON_U, 30}, -+ {BOARD_GPP_TS_BUTTON_R, 31}, -+ {BOARD_GPP_TS_BUTTON_L, 32}, -+ {BOARD_GPP_TS_BUTTON_D, 34}, -+ {BOARD_GPP_FAN_POWER, 35} -+ }; -+ -+MV_BOARD_MPP_INFO rd88f6192AInfoBoardMppConfigValue[] = -+ {{{ -+ RD_88F6192A_MPP0_7, -+ RD_88F6192A_MPP8_15, -+ RD_88F6192A_MPP16_23, -+ RD_88F6192A_MPP24_31, -+ RD_88F6192A_MPP32_35 -+ }}}; -+ -+MV_BOARD_INFO rd88f6192AInfo = { -+ "RD-88F6192A-NAS", /* boardName[MAX_BOARD_NAME_LEN] */ -+ RD_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ -+ rd88f6192AInfoBoardMppTypeInfo, -+ RD_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ rd88f6192AInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ (1 << 3), /* intsGppMaskHigh */ -+ RD_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ rd88f6192AInfoBoardDeCsInfo, -+ RD_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ NULL, -+ RD_88F6192A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ rd88f6192AInfoBoardMacInfo, -+ RD_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ rd88f6192AInfoBoardGppInfo, -+ RD_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ rd88f6192AInfoBoardDebugLedIf, -+ 0, /* ledsPolarity */ -+ RD_88F6192A_OE_LOW, /* gppOutEnLow */ -+ RD_88F6192A_OE_HIGH, /* gppOutEnHigh */ -+ RD_88F6192A_OE_VAL_LOW, /* gppOutValLow */ -+ RD_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ 0, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+MV_BOARD_INFO rd88f6190AInfo = { -+ "RD-88F6190A-NAS", /* boardName[MAX_BOARD_NAME_LEN] */ -+ RD_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ -+ rd88f6192AInfoBoardMppTypeInfo, -+ RD_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ rd88f6192AInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ (1 << 3), /* intsGppMaskHigh */ -+ RD_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ rd88f6192AInfoBoardDeCsInfo, -+ RD_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ NULL, -+ RD_88F6192A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ rd88f6192AInfoBoardMacInfo, -+ RD_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ rd88f6192AInfoBoardGppInfo, -+ RD_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ rd88f6192AInfoBoardDebugLedIf, -+ 0, /* ledsPolarity */ -+ RD_88F6192A_OE_LOW, /* gppOutEnLow */ -+ RD_88F6192A_OE_HIGH, /* gppOutEnHigh */ -+ RD_88F6192A_OE_VAL_LOW, /* gppOutValLow */ -+ RD_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ 0, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+#define DB_88F6180A_BOARD_PCI_IF_NUM 0x0 -+#define DB_88F6180A_BOARD_TWSI_DEF_NUM 0x5 -+#define DB_88F6180A_BOARD_MAC_INFO_NUM 0x1 -+#define DB_88F6180A_BOARD_GPP_INFO_NUM 0x0 -+#define DB_88F6180A_BOARD_MPP_GROUP_TYPE_NUM 0x2 -+#define DB_88F6180A_BOARD_MPP_CONFIG_NUM 0x1 -+#define DB_88F6180A_BOARD_DEVICE_CONFIG_NUM 0x1 -+#define DB_88F6180A_BOARD_DEBUG_LED_NUM 0x0 -+ -+MV_BOARD_TWSI_INFO db88f6180AInfoBoardTwsiDev[] = -+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ -+ { -+ {BOARD_DEV_TWSI_EXP, 0x20, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_EXP, 0x21, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, -+ {BOARD_TWSI_AUDIO_DEC, 0x4A, ADDR7_BIT} -+ }; -+ -+MV_BOARD_MAC_INFO db88f6180AInfoBoardMacInfo[] = -+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ -+ {{BOARD_MAC_SPEED_AUTO, 0x8} -+ }; -+ -+MV_BOARD_GPP_INFO db88f6180AInfoBoardGppInfo[] = -+ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ -+ { -+ /* Muxed with TDM/Audio module via IOexpender -+ {BOARD_GPP_USB_VBUS, 6} */ -+ }; -+ -+MV_BOARD_MPP_TYPE_INFO db88f6180AInfoBoardMppTypeInfo[] = -+ /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, -+ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ -+ {{MV_BOARD_OTHER, MV_BOARD_AUTO} -+ }; -+ -+MV_DEV_CS_INFO db88f6180AInfoBoardDeCsInfo[] = -+ /*{deviceCS, params, devType, devWidth}*/ -+#if defined(MV_NAND_BOOT) -+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ -+#else -+ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ -+#endif -+ -+MV_BOARD_MPP_INFO db88f6180AInfoBoardMppConfigValue[] = -+ {{{ -+ DB_88F6180A_MPP0_7, -+ DB_88F6180A_MPP8_15, -+ DB_88F6180A_MPP16_23, -+ DB_88F6180A_MPP24_31, -+ DB_88F6180A_MPP32_39, -+ DB_88F6180A_MPP40_44 -+ }}}; -+ -+MV_BOARD_INFO db88f6180AInfo = { -+ "DB-88F6180A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ -+ DB_88F6180A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ -+ db88f6180AInfoBoardMppTypeInfo, -+ DB_88F6180A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ db88f6180AInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ 0, /* intsGppMaskHigh */ -+ DB_88F6180A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ db88f6180AInfoBoardDeCsInfo, -+ DB_88F6180A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ db88f6180AInfoBoardTwsiDev, -+ DB_88F6180A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ db88f6180AInfoBoardMacInfo, -+ DB_88F6180A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ NULL, -+ DB_88F6180A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ NULL, -+ 0, /* ledsPolarity */ -+ DB_88F6180A_OE_LOW, /* gppOutEnLow */ -+ DB_88F6180A_OE_HIGH, /* gppOutEnHigh */ -+ DB_88F6180A_OE_VAL_LOW, /* gppOutValLow */ -+ DB_88F6180A_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ 0, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+ -+#define RD_88F6281A_PCAC_BOARD_PCI_IF_NUM 0x0 -+#define RD_88F6281A_PCAC_BOARD_TWSI_DEF_NUM 0x1 -+#define RD_88F6281A_PCAC_BOARD_MAC_INFO_NUM 0x1 -+#define RD_88F6281A_PCAC_BOARD_GPP_INFO_NUM 0x0 -+#define RD_88F6281A_PCAC_BOARD_MPP_GROUP_TYPE_NUM 0x1 -+#define RD_88F6281A_PCAC_BOARD_MPP_CONFIG_NUM 0x1 -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ #define RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM 0x1 -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ #define RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM 0x2 -+#else -+ #define RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM 0x1 -+#endif -+#define RD_88F6281A_PCAC_BOARD_DEBUG_LED_NUM 0x4 -+ -+MV_U8 rd88f6281APcacInfoBoardDebugLedIf[] = -+ {38, 39, 40, 41}; -+ -+MV_BOARD_MAC_INFO rd88f6281APcacInfoBoardMacInfo[] = -+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ -+ {{BOARD_MAC_SPEED_AUTO, 0x8} -+ }; -+ -+MV_BOARD_TWSI_INFO rd88f6281APcacInfoBoardTwsiDev[] = -+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ -+ { -+ {BOARD_TWSI_OTHER, 0xa7, ADDR7_BIT} -+ }; -+ -+MV_BOARD_MPP_TYPE_INFO rd88f6281APcacInfoBoardMppTypeInfo[] = -+ {{MV_BOARD_OTHER, MV_BOARD_OTHER} -+ }; -+ -+MV_DEV_CS_INFO rd88f6281APcacInfoBoardDeCsInfo[] = -+ /*{deviceCS, params, devType, devWidth}*/ -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ { -+ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ -+ {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ -+ }; -+#else -+ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ -+#endif -+ -+MV_BOARD_MPP_INFO rd88f6281APcacInfoBoardMppConfigValue[] = -+ {{{ -+ RD_88F6281A_PCAC_MPP0_7, -+ RD_88F6281A_PCAC_MPP8_15, -+ RD_88F6281A_PCAC_MPP16_23, -+ RD_88F6281A_PCAC_MPP24_31, -+ RD_88F6281A_PCAC_MPP32_39, -+ RD_88F6281A_PCAC_MPP40_47, -+ RD_88F6281A_PCAC_MPP48_55 -+ }}}; -+ -+MV_BOARD_INFO rd88f6281APcacInfo = { -+ "RD-88F6281A-PCAC", /* boardName[MAX_BOARD_NAME_LEN] */ -+ RD_88F6281A_PCAC_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ -+ rd88f6281APcacInfoBoardMppTypeInfo, -+ RD_88F6281A_PCAC_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ rd88f6281APcacInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ (1 << 3), /* intsGppMaskHigh */ -+ RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ rd88f6281APcacInfoBoardDeCsInfo, -+ RD_88F6281A_PCAC_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ rd88f6281APcacInfoBoardTwsiDev, -+ RD_88F6281A_PCAC_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ rd88f6281APcacInfoBoardMacInfo, -+ RD_88F6281A_PCAC_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ 0, -+ RD_88F6281A_PCAC_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ NULL, -+ 0, /* ledsPolarity */ -+ RD_88F6281A_PCAC_OE_LOW, /* gppOutEnLow */ -+ RD_88F6281A_PCAC_OE_HIGH, /* gppOutEnHigh */ -+ RD_88F6281A_PCAC_OE_VAL_LOW, /* gppOutValLow */ -+ RD_88F6281A_PCAC_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ 0, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+ -+/* 6281 Sheeva Plug*/ -+ -+#define SHEEVA_PLUG_BOARD_PCI_IF_NUM 0x0 -+#define SHEEVA_PLUG_BOARD_TWSI_DEF_NUM 0x0 -+#define SHEEVA_PLUG_BOARD_MAC_INFO_NUM 0x1 -+#define SHEEVA_PLUG_BOARD_GPP_INFO_NUM 0x0 -+#define SHEEVA_PLUG_BOARD_MPP_GROUP_TYPE_NUN 0x1 -+#define SHEEVA_PLUG_BOARD_MPP_CONFIG_NUM 0x1 -+#define SHEEVA_PLUG_BOARD_DEVICE_CONFIG_NUM 0x1 -+#define SHEEVA_PLUG_BOARD_DEBUG_LED_NUM 0x1 -+ -+MV_U8 sheevaPlugInfoBoardDebugLedIf[] = -+ {49}; -+ -+MV_BOARD_MAC_INFO sheevaPlugInfoBoardMacInfo[] = -+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ -+ {{BOARD_MAC_SPEED_AUTO, 0x0}}; -+ -+MV_BOARD_TWSI_INFO sheevaPlugInfoBoardTwsiDev[] = -+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ -+ {{BOARD_TWSI_OTHER, 0x0, ADDR7_BIT}}; -+ -+MV_BOARD_MPP_TYPE_INFO sheevaPlugInfoBoardMppTypeInfo[] = -+ {{MV_BOARD_OTHER, MV_BOARD_OTHER} -+ }; -+ -+MV_DEV_CS_INFO sheevaPlugInfoBoardDeCsInfo[] = -+ /*{deviceCS, params, devType, devWidth}*/ -+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ -+ -+MV_BOARD_MPP_INFO sheevaPlugInfoBoardMppConfigValue[] = -+ {{{ -+ RD_SHEEVA_PLUG_MPP0_7, -+ RD_SHEEVA_PLUG_MPP8_15, -+ RD_SHEEVA_PLUG_MPP16_23, -+ RD_SHEEVA_PLUG_MPP24_31, -+ RD_SHEEVA_PLUG_MPP32_39, -+ RD_SHEEVA_PLUG_MPP40_47, -+ RD_SHEEVA_PLUG_MPP48_55 -+ }}}; -+ -+MV_BOARD_INFO sheevaPlugInfo = { -+ "SHEEVA PLUG", /* boardName[MAX_BOARD_NAME_LEN] */ -+ SHEEVA_PLUG_BOARD_MPP_GROUP_TYPE_NUN, /* numBoardMppGroupType */ -+ sheevaPlugInfoBoardMppTypeInfo, -+ SHEEVA_PLUG_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ sheevaPlugInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ 0, /* intsGppMaskHigh */ -+ SHEEVA_PLUG_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ sheevaPlugInfoBoardDeCsInfo, -+ SHEEVA_PLUG_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ sheevaPlugInfoBoardTwsiDev, -+ SHEEVA_PLUG_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ sheevaPlugInfoBoardMacInfo, -+ SHEEVA_PLUG_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ 0, -+ SHEEVA_PLUG_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ sheevaPlugInfoBoardDebugLedIf, -+ 0, /* ledsPolarity */ -+ RD_SHEEVA_PLUG_OE_LOW, /* gppOutEnLow */ -+ RD_SHEEVA_PLUG_OE_HIGH, /* gppOutEnHigh */ -+ RD_SHEEVA_PLUG_OE_VAL_LOW, /* gppOutValLow */ -+ RD_SHEEVA_PLUG_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ 0, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+/* Customer specific board place holder*/ -+ -+#define DB_CUSTOMER_BOARD_PCI_IF_NUM 0x0 -+#define DB_CUSTOMER_BOARD_TWSI_DEF_NUM 0x0 -+#define DB_CUSTOMER_BOARD_MAC_INFO_NUM 0x0 -+#define DB_CUSTOMER_BOARD_GPP_INFO_NUM 0x0 -+#define DB_CUSTOMER_BOARD_MPP_GROUP_TYPE_NUN 0x0 -+#define DB_CUSTOMER_BOARD_MPP_CONFIG_NUM 0x0 -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ #define DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM 0x0 -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ #define DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM 0x0 -+#else -+ #define DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM 0x0 -+#endif -+#define DB_CUSTOMER_BOARD_DEBUG_LED_NUM 0x0 -+ -+MV_U8 dbCustomerInfoBoardDebugLedIf[] = -+ {0}; -+ -+MV_BOARD_MAC_INFO dbCustomerInfoBoardMacInfo[] = -+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ -+ {{BOARD_MAC_SPEED_AUTO, 0x0}}; -+ -+MV_BOARD_TWSI_INFO dbCustomerInfoBoardTwsiDev[] = -+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ -+ {{BOARD_TWSI_OTHER, 0x0, ADDR7_BIT}}; -+ -+MV_BOARD_MPP_TYPE_INFO dbCustomerInfoBoardMppTypeInfo[] = -+ {{MV_BOARD_OTHER, MV_BOARD_OTHER} -+ }; -+ -+MV_DEV_CS_INFO dbCustomerInfoBoardDeCsInfo[] = -+ /*{deviceCS, params, devType, devWidth}*/ -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ { -+ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ -+ {2, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ -+ }; -+#else -+ {{2, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ -+#endif -+ -+MV_BOARD_MPP_INFO dbCustomerInfoBoardMppConfigValue[] = -+ {{{ -+ DB_CUSTOMER_MPP0_7, -+ DB_CUSTOMER_MPP8_15, -+ DB_CUSTOMER_MPP16_23, -+ DB_CUSTOMER_MPP24_31, -+ DB_CUSTOMER_MPP32_39, -+ DB_CUSTOMER_MPP40_47, -+ DB_CUSTOMER_MPP48_55 -+ }}}; -+ -+MV_BOARD_INFO dbCustomerInfo = { -+ "DB-CUSTOMER", /* boardName[MAX_BOARD_NAME_LEN] */ -+ DB_CUSTOMER_BOARD_MPP_GROUP_TYPE_NUN, /* numBoardMppGroupType */ -+ dbCustomerInfoBoardMppTypeInfo, -+ DB_CUSTOMER_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ dbCustomerInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ 0, /* intsGppMaskHigh */ -+ DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ dbCustomerInfoBoardDeCsInfo, -+ DB_CUSTOMER_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ dbCustomerInfoBoardTwsiDev, -+ DB_CUSTOMER_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ dbCustomerInfoBoardMacInfo, -+ DB_CUSTOMER_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ 0, -+ DB_CUSTOMER_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ NULL, -+ 0, /* ledsPolarity */ -+ DB_CUSTOMER_OE_LOW, /* gppOutEnLow */ -+ DB_CUSTOMER_OE_HIGH, /* gppOutEnHigh */ -+ DB_CUSTOMER_OE_VAL_LOW, /* gppOutValLow */ -+ DB_CUSTOMER_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ 0, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+MV_BOARD_INFO* boardInfoTbl[] = { -+ &db88f6281AInfo, -+ &rd88f6281AInfo, -+ &db88f6192AInfo, -+ &rd88f6192AInfo, -+ &db88f6180AInfo, -+ &db88f6190AInfo, -+ &rd88f6190AInfo, -+ &rd88f6281APcacInfo, -+ &dbCustomerInfo, -+ &sheevaPlugInfo -+ }; -+ -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,262 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvBoardEnvSpech -+#define __INCmvBoardEnvSpech -+ -+#include "mvSysHwConfig.h" -+ -+ -+/* For future use */ -+#define BD_ID_DATA_START_OFFS 0x0 -+#define BD_DETECT_SEQ_OFFS 0x0 -+#define BD_SYS_NUM_OFFS 0x4 -+#define BD_NAME_OFFS 0x8 -+ -+/* I2C bus addresses */ -+#define MV_BOARD_CTRL_I2C_ADDR 0x0 /* Controller slave addr */ -+#define MV_BOARD_CTRL_I2C_ADDR_TYPE ADDR7_BIT -+#define MV_BOARD_DIMM0_I2C_ADDR 0x56 -+#define MV_BOARD_DIMM0_I2C_ADDR_TYPE ADDR7_BIT -+#define MV_BOARD_DIMM1_I2C_ADDR 0x54 -+#define MV_BOARD_DIMM1_I2C_ADDR_TYPE ADDR7_BIT -+#define MV_BOARD_EEPROM_I2C_ADDR 0x51 -+#define MV_BOARD_EEPROM_I2C_ADDR_TYPE ADDR7_BIT -+#define MV_BOARD_MAIN_EEPROM_I2C_ADDR 0x50 -+#define MV_BOARD_MAIN_EEPROM_I2C_ADDR_TYPE ADDR7_BIT -+#define MV_BOARD_MUX_I2C_ADDR_ENTRY 0x2 -+#define MV_BOARD_DIMM_I2C_CHANNEL 0x0 -+ -+#define BOOT_FLASH_INDEX 0 -+#define MAIN_FLASH_INDEX 1 -+ -+#define BOARD_ETH_START_PORT_NUM 0 -+ -+/* Supported clocks */ -+#define MV_BOARD_TCLK_100MHZ 100000000 -+#define MV_BOARD_TCLK_125MHZ 125000000 -+#define MV_BOARD_TCLK_133MHZ 133333333 -+#define MV_BOARD_TCLK_150MHZ 150000000 -+#define MV_BOARD_TCLK_166MHZ 166666667 -+#define MV_BOARD_TCLK_200MHZ 200000000 -+ -+#define MV_BOARD_SYSCLK_100MHZ 100000000 -+#define MV_BOARD_SYSCLK_125MHZ 125000000 -+#define MV_BOARD_SYSCLK_133MHZ 133333333 -+#define MV_BOARD_SYSCLK_150MHZ 150000000 -+#define MV_BOARD_SYSCLK_166MHZ 166666667 -+#define MV_BOARD_SYSCLK_200MHZ 200000000 -+#define MV_BOARD_SYSCLK_233MHZ 233333333 -+#define MV_BOARD_SYSCLK_250MHZ 250000000 -+#define MV_BOARD_SYSCLK_267MHZ 266666667 -+#define MV_BOARD_SYSCLK_300MHZ 300000000 -+#define MV_BOARD_SYSCLK_333MHZ 333333334 -+#define MV_BOARD_SYSCLK_400MHZ 400000000 -+ -+#define MV_BOARD_REFCLK_25MHZ 25000000 -+ -+/* Board specific */ -+/* =============================== */ -+ -+/* boards ID numbers */ -+ -+#define BOARD_ID_BASE 0x0 -+ -+/* New board ID numbers */ -+#define DB_88F6281A_BP_ID (BOARD_ID_BASE) -+#define DB_88F6281_BP_MLL_ID 1680 -+#define RD_88F6281A_ID (BOARD_ID_BASE+0x1) -+#define RD_88F6281_MLL_ID 1682 -+#define DB_88F6192A_BP_ID (BOARD_ID_BASE+0x2) -+#define RD_88F6192A_ID (BOARD_ID_BASE+0x3) -+#define RD_88F6192_MLL_ID 1681 -+#define DB_88F6180A_BP_ID (BOARD_ID_BASE+0x4) -+#define DB_88F6190A_BP_ID (BOARD_ID_BASE+0x5) -+#define RD_88F6190A_ID (BOARD_ID_BASE+0x6) -+#define RD_88F6281A_PCAC_ID (BOARD_ID_BASE+0x7) -+#define DB_CUSTOMER_ID (BOARD_ID_BASE+0x8) -+#define SHEEVA_PLUG_ID (BOARD_ID_BASE+0x9) -+#define MV_MAX_BOARD_ID (SHEEVA_PLUG_ID + 1) -+ -+/* DB-88F6281A-BP */ -+#if defined(MV_NAND) -+ #define DB_88F6281A_MPP0_7 0x21111111 -+#else -+ #define DB_88F6281A_MPP0_7 0x21112220 -+#endif -+#define DB_88F6281A_MPP8_15 0x11113311 -+#define DB_88F6281A_MPP16_23 0x00551111 -+#define DB_88F6281A_MPP24_31 0x00000000 -+#define DB_88F6281A_MPP32_39 0x00000000 -+#define DB_88F6281A_MPP40_47 0x00000000 -+#define DB_88F6281A_MPP48_55 0x00000000 -+#define DB_88F6281A_OE_LOW 0x0 -+#if defined(MV_TDM_5CHANNELS) -+ #define DB_88F6281A_OE_HIGH (BIT6) -+#else -+#define DB_88F6281A_OE_HIGH 0x0 -+#endif -+#define DB_88F6281A_OE_VAL_LOW 0x0 -+#define DB_88F6281A_OE_VAL_HIGH 0x0 -+ -+/* RD-88F6281A */ -+#if defined(MV_NAND) -+ #define RD_88F6281A_MPP0_7 0x21111111 -+#else -+ #define RD_88F6281A_MPP0_7 0x21112220 -+#endif -+#define RD_88F6281A_MPP8_15 0x11113311 -+#define RD_88F6281A_MPP16_23 0x33331111 -+#define RD_88F6281A_MPP24_31 0x33003333 -+#define RD_88F6281A_MPP32_39 0x20440533 -+#define RD_88F6281A_MPP40_47 0x22202222 -+#define RD_88F6281A_MPP48_55 0x00000002 -+#define RD_88F6281A_OE_LOW (BIT28 | BIT29) -+#define RD_88F6281A_OE_HIGH (BIT3 | BIT6 | BIT17) -+#define RD_88F6281A_OE_VAL_LOW 0x0 -+#define RD_88F6281A_OE_VAL_HIGH 0x0 -+ -+/* DB-88F6192A-BP */ -+#if defined(MV_NAND) -+ #define DB_88F6192A_MPP0_7 0x21111111 -+#else -+ #define DB_88F6192A_MPP0_7 0x21112220 -+#endif -+#define DB_88F6192A_MPP8_15 0x11113311 -+#define DB_88F6192A_MPP16_23 0x00501111 -+#define DB_88F6192A_MPP24_31 0x00000000 -+#define DB_88F6192A_MPP32_35 0x00000000 -+#define DB_88F6192A_OE_LOW (BIT22 | BIT23) -+#define DB_88F6192A_OE_HIGH 0x0 -+#define DB_88F6192A_OE_VAL_LOW 0x0 -+#define DB_88F6192A_OE_VAL_HIGH 0x0 -+ -+/* RD-88F6192A */ -+#define RD_88F6192A_MPP0_7 0x01222222 -+#define RD_88F6192A_MPP8_15 0x00000011 -+#define RD_88F6192A_MPP16_23 0x05550000 -+#define RD_88F6192A_MPP24_31 0x0 -+#define RD_88F6192A_MPP32_35 0x0 -+#define RD_88F6192A_OE_LOW (BIT11 | BIT14 | BIT24 | BIT25 | BIT26 | BIT27 | BIT30 | BIT31) -+#define RD_88F6192A_OE_HIGH (BIT0 | BIT2) -+#define RD_88F6192A_OE_VAL_LOW 0x18400 -+#define RD_88F6192A_OE_VAL_HIGH 0x8 -+ -+/* DB-88F6180A-BP */ -+#if defined(MV_NAND) -+ #define DB_88F6180A_MPP0_7 0x21111111 -+#else -+ #define DB_88F6180A_MPP0_7 0x01112222 -+#endif -+#define DB_88F6180A_MPP8_15 0x11113311 -+#define DB_88F6180A_MPP16_23 0x00001111 -+#define DB_88F6180A_MPP24_31 0x0 -+#define DB_88F6180A_MPP32_39 0x4444c000 -+#define DB_88F6180A_MPP40_44 0x00044444 -+#define DB_88F6180A_OE_LOW 0x0 -+#define DB_88F6180A_OE_HIGH 0x0 -+#define DB_88F6180A_OE_VAL_LOW 0x0 -+#define DB_88F6180A_OE_VAL_HIGH 0x0 -+ -+/* RD-88F6281A_PCAC */ -+#define RD_88F6281A_PCAC_MPP0_7 0x21111111 -+#define RD_88F6281A_PCAC_MPP8_15 0x00003311 -+#define RD_88F6281A_PCAC_MPP16_23 0x00001100 -+#define RD_88F6281A_PCAC_MPP24_31 0x00000000 -+#define RD_88F6281A_PCAC_MPP32_39 0x00000000 -+#define RD_88F6281A_PCAC_MPP40_47 0x00000000 -+#define RD_88F6281A_PCAC_MPP48_55 0x00000000 -+#define RD_88F6281A_PCAC_OE_LOW 0x0 -+#define RD_88F6281A_PCAC_OE_HIGH 0x0 -+#define RD_88F6281A_PCAC_OE_VAL_LOW 0x0 -+#define RD_88F6281A_PCAC_OE_VAL_HIGH 0x0 -+ -+/* SHEEVA PLUG */ -+#define RD_SHEEVA_PLUG_MPP0_7 0x01111111 -+#define RD_SHEEVA_PLUG_MPP8_15 0x11113322 -+#define RD_SHEEVA_PLUG_MPP16_23 0x00001111 -+#define RD_SHEEVA_PLUG_MPP24_31 0x00100000 -+#define RD_SHEEVA_PLUG_MPP32_39 0x00000000 -+#define RD_SHEEVA_PLUG_MPP40_47 0x00000000 -+#define RD_SHEEVA_PLUG_MPP48_55 0x00000000 -+#define RD_SHEEVA_PLUG_OE_LOW 0x0 -+#define RD_SHEEVA_PLUG_OE_HIGH 0x0 -+#define RD_SHEEVA_PLUG_OE_VAL_LOW (BIT29) -+#define RD_SHEEVA_PLUG_OE_VAL_HIGH ((~(BIT17 | BIT16 | BIT15)) | BIT14) -+ -+/* DB-CUSTOMER */ -+#define DB_CUSTOMER_MPP0_7 0x21111111 -+#define DB_CUSTOMER_MPP8_15 0x00003311 -+#define DB_CUSTOMER_MPP16_23 0x00001100 -+#define DB_CUSTOMER_MPP24_31 0x00000000 -+#define DB_CUSTOMER_MPP32_39 0x00000000 -+#define DB_CUSTOMER_MPP40_47 0x00000000 -+#define DB_CUSTOMER_MPP48_55 0x00000000 -+#define DB_CUSTOMER_OE_LOW 0x0 -+#define DB_CUSTOMER_OE_HIGH (~((BIT6) | (BIT7) | (BIT8) | (BIT9))) -+#define DB_CUSTOMER_OE_VAL_LOW 0x0 -+#define DB_CUSTOMER_OE_VAL_HIGH 0x0 -+ -+#endif /* __INCmvBoardEnvSpech */ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,320 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#include "cpu/mvCpu.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvRegs.h" -+#include "ctrlEnv/sys/mvCpuIfRegs.h" -+ -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+/* locals */ -+ -+/******************************************************************************* -+* mvCpuPclkGet - Get the CPU pClk (pipe clock) -+* -+* DESCRIPTION: -+* This routine extract the CPU core clock. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit clock cycles in MHertz. -+* -+*******************************************************************************/ -+/* 6180 have different clk reset sampling */ -+ -+static MV_U32 mvCpu6180PclkGet(MV_VOID) -+{ -+ MV_U32 tmpPClkRate=0; -+ MV_CPU_ARM_CLK cpu6180_ddr_l2_CLK[] = MV_CPU6180_DDR_L2_CLCK_TBL; -+ -+ tmpPClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ tmpPClkRate = tmpPClkRate & MSAR_CPUCLCK_MASK_6180; -+ tmpPClkRate = tmpPClkRate >> MSAR_CPUCLCK_OFFS_6180; -+ -+ tmpPClkRate = cpu6180_ddr_l2_CLK[tmpPClkRate].cpuClk; -+ -+ return tmpPClkRate; -+} -+ -+ -+MV_U32 mvCpuPclkGet(MV_VOID) -+{ -+#if defined(PCLCK_AUTO_DETECT) -+ MV_U32 tmpPClkRate=0; -+ MV_U32 cpuCLK[] = MV_CPU_CLCK_TBL; -+ -+ if(mvCtrlModelGet() == MV_6180_DEV_ID) -+ return mvCpu6180PclkGet(); -+ -+ tmpPClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ tmpPClkRate = MSAR_CPUCLCK_EXTRACT(tmpPClkRate); -+ tmpPClkRate = cpuCLK[tmpPClkRate]; -+ -+ return tmpPClkRate; -+#else -+ return MV_DEFAULT_PCLK -+#endif -+} -+ -+/******************************************************************************* -+* mvCpuL2ClkGet - Get the CPU L2 (CPU bus clock) -+* -+* DESCRIPTION: -+* This routine extract the CPU L2 clock. -+* -+* RETURN: -+* 32bit clock cycles in Hertz. -+* -+*******************************************************************************/ -+static MV_U32 mvCpu6180L2ClkGet(MV_VOID) -+{ -+ MV_U32 L2ClkRate=0; -+ MV_CPU_ARM_CLK _cpu6180_ddr_l2_CLK[] = MV_CPU6180_DDR_L2_CLCK_TBL; -+ -+ L2ClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ L2ClkRate = L2ClkRate & MSAR_CPUCLCK_MASK_6180; -+ L2ClkRate = L2ClkRate >> MSAR_CPUCLCK_OFFS_6180; -+ -+ L2ClkRate = _cpu6180_ddr_l2_CLK[L2ClkRate].l2Clk; -+ -+ return L2ClkRate; -+ -+} -+ -+MV_U32 mvCpuL2ClkGet(MV_VOID) -+{ -+#ifdef L2CLK_AUTO_DETECT -+ MV_U32 L2ClkRate, tmp, pClkRate, indexL2Rtio; -+ MV_U32 L2Rtio[][2] = MV_L2_CLCK_RTIO_TBL; -+ -+ if(mvCtrlModelGet() == MV_6180_DEV_ID) -+ return mvCpu6180L2ClkGet(); -+ -+ pClkRate = mvCpuPclkGet(); -+ -+ tmp = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ indexL2Rtio = MSAR_L2CLCK_EXTRACT(tmp); -+ -+ L2ClkRate = ((pClkRate * L2Rtio[indexL2Rtio][1]) / L2Rtio[indexL2Rtio][0]); -+ -+ return L2ClkRate; -+#else -+ return MV_BOARD_DEFAULT_L2CLK; -+#endif -+} -+ -+ -+/******************************************************************************* -+* mvCpuNameGet - Get CPU name -+* -+* DESCRIPTION: -+* This function returns a string describing the CPU model and revision. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* pNameBuff - Buffer to contain board name string. Minimum size 32 chars. -+* -+* RETURN: -+* None. -+*******************************************************************************/ -+MV_VOID mvCpuNameGet(char *pNameBuff) -+{ -+ MV_U32 cpuModel; -+ -+ cpuModel = mvOsCpuPartGet(); -+ -+ /* The CPU module is indicated in the Processor Version Register (PVR) */ -+ switch(cpuModel) -+ { -+ case CPU_PART_MRVL131: -+ mvOsSPrintf(pNameBuff, "%s (Rev %d)", "Marvell Feroceon",mvOsCpuRevGet()); -+ break; -+ case CPU_PART_ARM926: -+ mvOsSPrintf(pNameBuff, "%s (Rev %d)", "ARM926",mvOsCpuRevGet()); -+ break; -+ case CPU_PART_ARM946: -+ mvOsSPrintf(pNameBuff, "%s (Rev %d)", "ARM946",mvOsCpuRevGet()); -+ break; -+ default: -+ mvOsSPrintf(pNameBuff,"??? (0x%04x) (Rev %d)",cpuModel,mvOsCpuRevGet()); -+ break; -+ } /* switch */ -+ -+ return; -+} -+ -+ -+#define MV_PROC_STR_SIZE 50 -+ -+static void mvCpuIfGetL2EccMode(MV_8 *buf) -+{ -+ MV_U32 regVal = MV_REG_READ(CPU_L2_CONFIG_REG); -+ if (regVal & BIT2) -+ mvOsSPrintf(buf, "L2 ECC Enabled"); -+ else -+ mvOsSPrintf(buf, "L2 ECC Disabled"); -+} -+ -+static void mvCpuIfGetL2Mode(MV_8 *buf) -+{ -+ MV_U32 regVal = 0; -+ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ -+ if (regVal & BIT22) -+ mvOsSPrintf(buf, "L2 Enabled"); -+ else -+ mvOsSPrintf(buf, "L2 Disabled"); -+} -+ -+static void mvCpuIfGetL2PrefetchMode(MV_8 *buf) -+{ -+ MV_U32 regVal = 0; -+ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ -+ if (regVal & BIT24) -+ mvOsSPrintf(buf, "L2 Prefetch Disabled"); -+ else -+ mvOsSPrintf(buf, "L2 Prefetch Enabled"); -+} -+ -+static void mvCpuIfGetWriteAllocMode(MV_8 *buf) -+{ -+ MV_U32 regVal = 0; -+ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ -+ if (regVal & BIT28) -+ mvOsSPrintf(buf, "Write Allocate Enabled"); -+ else -+ mvOsSPrintf(buf, "Write Allocate Disabled"); -+} -+ -+static void mvCpuIfGetCpuStreamMode(MV_8 *buf) -+{ -+ MV_U32 regVal = 0; -+ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ -+ if (regVal & BIT29) -+ mvOsSPrintf(buf, "CPU Streaming Enabled"); -+ else -+ mvOsSPrintf(buf, "CPU Streaming Disabled"); -+} -+ -+static void mvCpuIfPrintCpuRegs(void) -+{ -+ MV_U32 regVal = 0; -+ -+ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ -+ mvOsPrintf("Extra Feature Reg = 0x%x\n",regVal); -+ -+ __asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (regVal)); /* Read Control register */ -+ mvOsPrintf("Control Reg = 0x%x\n",regVal); -+ -+ __asm volatile ("mrc p15, 0, %0, c0, c0, 0" : "=r" (regVal)); /* Read ID Code register */ -+ mvOsPrintf("ID Code Reg = 0x%x\n",regVal); -+ -+ __asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=r" (regVal)); /* Read Cache Type register */ -+ mvOsPrintf("Cache Type Reg = 0x%x\n",regVal); -+ -+} -+ -+MV_U32 mvCpuIfPrintSystemConfig(MV_8 *buffer, MV_U32 index) -+{ -+ MV_U32 count = 0; -+ -+ MV_8 L2_ECC_str[MV_PROC_STR_SIZE]; -+ MV_8 L2_En_str[MV_PROC_STR_SIZE]; -+ MV_8 L2_Prefetch_str[MV_PROC_STR_SIZE]; -+ MV_8 Write_Alloc_str[MV_PROC_STR_SIZE]; -+ MV_8 Cpu_Stream_str[MV_PROC_STR_SIZE]; -+ -+ mvCpuIfGetL2Mode(L2_En_str); -+ mvCpuIfGetL2EccMode(L2_ECC_str); -+ mvCpuIfGetL2PrefetchMode(L2_Prefetch_str); -+ mvCpuIfGetWriteAllocMode(Write_Alloc_str); -+ mvCpuIfGetCpuStreamMode(Cpu_Stream_str); -+ mvCpuIfPrintCpuRegs(); -+ -+ count += mvOsSPrintf(buffer + count + index, "%s\n", L2_En_str); -+ count += mvOsSPrintf(buffer + count + index, "%s\n", L2_ECC_str); -+ count += mvOsSPrintf(buffer + count + index, "%s\n", L2_Prefetch_str); -+ count += mvOsSPrintf(buffer + count + index, "%s\n", Write_Alloc_str); -+ count += mvOsSPrintf(buffer + count + index, "%s\n", Cpu_Stream_str); -+ return count; -+} -+ -+MV_U32 whoAmI(MV_VOID) -+{ -+ return 0; -+} -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,99 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvCpuh -+#define __INCmvCpuh -+ -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+ -+/* defines */ -+#define CPU_PART_MRVL131 0x131 -+#define CPU_PART_ARM926 0x926 -+#define CPU_PART_ARM946 0x946 -+#define MV_CPU_ARM_CLK_ELM_SIZE 12 -+#define MV_CPU_ARM_CLK_RATIO_OFF 8 -+#define MV_CPU_ARM_CLK_DDR_OFF 4 -+ -+#ifndef MV_ASMLANGUAGE -+typedef struct _mvCpuArmClk -+{ -+ MV_U32 cpuClk; /* CPU clock in MHz */ -+ MV_U32 ddrClk; /* DDR clock in MHz */ -+ MV_U32 l2Clk; /* CPU DDR clock ratio */ -+ -+}MV_CPU_ARM_CLK; -+ -+MV_U32 mvCpuPclkGet(MV_VOID); -+MV_VOID mvCpuNameGet(char *pNameBuff); -+MV_U32 mvCpuL2ClkGet(MV_VOID); -+MV_U32 mvCpuIfPrintSystemConfig(MV_8 *buffer, MV_U32 index); -+MV_U32 whoAmI(MV_VOID); -+ -+#endif /* MV_ASMLANGUAGE */ -+ -+ -+#endif /* __INCmvCpuh */ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,296 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+/******************************************************************************* -+* mvCtrlEnvAddrDec.h - Marvell controller address decode library -+* -+* DESCRIPTION: -+* -+* DEPENDENCIES: -+* None. -+* -+*******************************************************************************/ -+ -+/* includes */ -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+#include "ctrlEnv/sys/mvAhbToMbusRegs.h" -+#include "ddr2/mvDramIfRegs.h" -+#include "pex/mvPexRegs.h" -+ -+#define MV_DEBUG -+ -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+/* Default Attributes array */ -+MV_TARGET_ATTRIB mvTargetDefaultsArray[] = TARGETS_DEF_ARRAY; -+extern MV_TARGET *sampleAtResetTargetArray; -+/* Dram\AHBToMbus\PEX share regsiter */ -+ -+#define CTRL_DEC_BASE_OFFS 16 -+#define CTRL_DEC_BASE_MASK (0xffff << CTRL_DEC_BASE_OFFS) -+#define CTRL_DEC_BASE_ALIGNMENT 0x10000 -+ -+#define CTRL_DEC_SIZE_OFFS 16 -+#define CTRL_DEC_SIZE_MASK (0xffff << CTRL_DEC_SIZE_OFFS) -+#define CTRL_DEC_SIZE_ALIGNMENT 0x10000 -+ -+#define CTRL_DEC_WIN_EN BIT0 -+ -+ -+ -+/******************************************************************************* -+* mvCtrlAddrDecToReg - Get address decode register format values -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_STATUS mvCtrlAddrDecToReg(MV_ADDR_WIN *pAddrDecWin, MV_DEC_REGS *pAddrDecRegs) -+{ -+ -+ MV_U32 baseToReg=0 , sizeToReg=0; -+ -+ /* BaseLow[31:16] => base register [31:16] */ -+ baseToReg = pAddrDecWin->baseLow & CTRL_DEC_BASE_MASK; -+ -+ /* Write to address decode Base Address Register */ -+ pAddrDecRegs->baseReg &= ~CTRL_DEC_BASE_MASK; -+ pAddrDecRegs->baseReg |= baseToReg; -+ -+ /* Get size register value according to window size */ -+ sizeToReg = ctrlSizeToReg(pAddrDecWin->size, CTRL_DEC_SIZE_ALIGNMENT); -+ -+ /* Size parameter validity check. */ -+ if (-1 == sizeToReg) -+ { -+ return MV_BAD_PARAM; -+ } -+ -+ /* set size */ -+ pAddrDecRegs->sizeReg &= ~CTRL_DEC_SIZE_MASK; -+ pAddrDecRegs->sizeReg |= (sizeToReg << CTRL_DEC_SIZE_OFFS); -+ -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvCtrlRegToAddrDec - Extract address decode struct from registers. -+* -+* DESCRIPTION: -+* This function extract address decode struct from address decode -+* registers given as parameters. -+* -+* INPUT: -+* pAddrDecRegs - Address decode register struct. -+* -+* OUTPUT: -+* pAddrDecWin - Target window data structure. -+* -+* RETURN: -+* MV_BAD_PARAM if address decode registers data is invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvCtrlRegToAddrDec(MV_DEC_REGS *pAddrDecRegs, MV_ADDR_WIN *pAddrDecWin) -+{ -+ MV_U32 sizeRegVal; -+ -+ sizeRegVal = (pAddrDecRegs->sizeReg & CTRL_DEC_SIZE_MASK) >> -+ CTRL_DEC_SIZE_OFFS; -+ -+ pAddrDecWin->size = ctrlRegToSize(sizeRegVal, CTRL_DEC_SIZE_ALIGNMENT); -+ -+ -+ /* Extract base address */ -+ /* Base register [31:16] ==> baseLow[31:16] */ -+ pAddrDecWin->baseLow = pAddrDecRegs->baseReg & CTRL_DEC_BASE_MASK; -+ -+ pAddrDecWin->baseHigh = 0; -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvCtrlAttribGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+* -+*******************************************************************************/ -+ -+MV_STATUS mvCtrlAttribGet(MV_TARGET target, -+ MV_TARGET_ATTRIB *targetAttrib) -+{ -+ -+ targetAttrib->attrib = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].attrib; -+ targetAttrib->targetId = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId; -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvCtrlGetAttrib - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_TARGET mvCtrlTargetGet(MV_TARGET_ATTRIB *targetAttrib) -+{ -+ MV_TARGET target; -+ MV_TARGET x; -+ for (target = SDRAM_CS0; target < MAX_TARGETS ; target ++) -+ { -+ x = MV_CHANGE_BOOT_CS(target); -+ if ((mvTargetDefaultsArray[x].attrib == targetAttrib->attrib) && -+ (mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId == targetAttrib->targetId)) -+ { -+ /* found it */ -+ break; -+ } -+ } -+ -+ return target; -+} -+ -+MV_STATUS mvCtrlAddrDecToParams(MV_DEC_WIN *pAddrDecWin, -+ MV_DEC_WIN_PARAMS *pWinParam) -+{ -+ MV_U32 baseToReg=0, sizeToReg=0; -+ -+ /* BaseLow[31:16] => base register [31:16] */ -+ baseToReg = pAddrDecWin->addrWin.baseLow & CTRL_DEC_BASE_MASK; -+ -+ /* Write to address decode Base Address Register */ -+ pWinParam->baseAddr &= ~CTRL_DEC_BASE_MASK; -+ pWinParam->baseAddr |= baseToReg; -+ -+ /* Get size register value according to window size */ -+ sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, CTRL_DEC_SIZE_ALIGNMENT); -+ -+ /* Size parameter validity check. */ -+ if (-1 == sizeToReg) -+ { -+ mvOsPrintf("mvCtrlAddrDecToParams: ERR. ctrlSizeToReg failed.\n"); -+ return MV_BAD_PARAM; -+ } -+ pWinParam->size = sizeToReg; -+ -+ pWinParam->attrib = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(pAddrDecWin->target)].attrib; -+ pWinParam->targetId = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(pAddrDecWin->target)].targetId; -+ -+ return MV_OK; -+} -+ -+MV_STATUS mvCtrlParamsToAddrDec(MV_DEC_WIN_PARAMS *pWinParam, -+ MV_DEC_WIN *pAddrDecWin) -+{ -+ MV_TARGET_ATTRIB targetAttrib; -+ -+ pAddrDecWin->addrWin.baseLow = pWinParam->baseAddr; -+ -+ /* Upper 32bit address base is supported under PCI High Address remap */ -+ pAddrDecWin->addrWin.baseHigh = 0; -+ -+ /* Prepare sizeReg to ctrlRegToSize function */ -+ pAddrDecWin->addrWin.size = ctrlRegToSize(pWinParam->size, CTRL_DEC_SIZE_ALIGNMENT); -+ -+ if (-1 == pAddrDecWin->addrWin.size) -+ { -+ DB(mvOsPrintf("mvCtrlParamsToAddrDec: ERR. ctrlRegToSize failed.\n")); -+ return MV_BAD_PARAM; -+ } -+ targetAttrib.targetId = pWinParam->targetId; -+ targetAttrib.attrib = pWinParam->attrib; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ return MV_OK; -+} -+ -+ -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,203 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvCtrlEnvAddrDech -+#define __INCmvCtrlEnvAddrDech -+ -+/* includes */ -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvRegs.h" -+ -+ -+/* defines */ -+/* DUnit attributes */ -+#define ATMWCR_WIN_DUNIT_CS0_OFFS 0 -+#define ATMWCR_WIN_DUNIT_CS0_MASK BIT0 -+#define ATMWCR_WIN_DUNIT_CS0_REQ (0 << ATMWCR_WIN_DUNIT_CS0_OFFS) -+ -+#define ATMWCR_WIN_DUNIT_CS1_OFFS 1 -+#define ATMWCR_WIN_DUNIT_CS1_MASK BIT1 -+#define ATMWCR_WIN_DUNIT_CS1_REQ (0 << ATMWCR_WIN_DUNIT_CS1_OFFS) -+ -+#define ATMWCR_WIN_DUNIT_CS2_OFFS 2 -+#define ATMWCR_WIN_DUNIT_CS2_MASK BIT2 -+#define ATMWCR_WIN_DUNIT_CS2_REQ (0 << ATMWCR_WIN_DUNIT_CS2_OFFS) -+ -+#define ATMWCR_WIN_DUNIT_CS3_OFFS 3 -+#define ATMWCR_WIN_DUNIT_CS3_MASK BIT3 -+#define ATMWCR_WIN_DUNIT_CS3_REQ (0 << ATMWCR_WIN_DUNIT_CS3_OFFS) -+ -+/* RUnit (Device) attributes */ -+#define ATMWCR_WIN_RUNIT_DEVCS0_OFFS 0 -+#define ATMWCR_WIN_RUNIT_DEVCS0_MASK BIT0 -+#define ATMWCR_WIN_RUNIT_DEVCS0_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS0_OFFS) -+ -+#define ATMWCR_WIN_RUNIT_DEVCS1_OFFS 1 -+#define ATMWCR_WIN_RUNIT_DEVCS1_MASK BIT1 -+#define ATMWCR_WIN_RUNIT_DEVCS1_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS1_OFFS) -+ -+#define ATMWCR_WIN_RUNIT_DEVCS2_OFFS 2 -+#define ATMWCR_WIN_RUNIT_DEVCS2_MASK BIT2 -+#define ATMWCR_WIN_RUNIT_DEVCS2_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS2_OFFS) -+ -+#define ATMWCR_WIN_RUNIT_BOOTCS_OFFS 4 -+#define ATMWCR_WIN_RUNIT_BOOTCS_MASK BIT4 -+#define ATMWCR_WIN_RUNIT_BOOTCS_REQ (0 << ATMWCR_WIN_RUNIT_BOOTCS_OFFS) -+ -+/* LMaster (PCI) attributes */ -+#define ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS 0 -+#define ATMWCR_WIN_LUNIT_BYTE_SWP_MASK BIT0 -+#define ATMWCR_WIN_LUNIT_BYTE_SWP (0 << ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS) -+#define ATMWCR_WIN_LUNIT_BYTE_NO_SWP (1 << ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS) -+ -+ -+#define ATMWCR_WIN_LUNIT_WORD_SWP_OFFS 1 -+#define ATMWCR_WIN_LUNIT_WORD_SWP_MASK BIT1 -+#define ATMWCR_WIN_LUNIT_WORD_SWP (0 << ATMWCR_WIN_LUNIT_WORD_SWP_OFFS) -+#define ATMWCR_WIN_LUNIT_WORD_NO_SWP (1 << ATMWCR_WIN_LUNIT_WORD_SWP_OFFS) -+ -+#define ATMWCR_WIN_LUNIT_NO_SNOOP BIT2 -+ -+#define ATMWCR_WIN_LUNIT_TYPE_OFFS 3 -+#define ATMWCR_WIN_LUNIT_TYPE_MASK BIT3 -+#define ATMWCR_WIN_LUNIT_TYPE_IO (0 << ATMWCR_WIN_LUNIT_TYPE_OFFS) -+#define ATMWCR_WIN_LUNIT_TYPE_MEM (1 << ATMWCR_WIN_LUNIT_TYPE_OFFS) -+ -+#define ATMWCR_WIN_LUNIT_FORCE64_OFFS 4 -+#define ATMWCR_WIN_LUNIT_FORCE64_MASK BIT4 -+#define ATMWCR_WIN_LUNIT_FORCE64 (0 << ATMWCR_WIN_LUNIT_FORCE64_OFFS) -+ -+#define ATMWCR_WIN_LUNIT_ORDERING_OFFS 6 -+#define ATMWCR_WIN_LUNIT_ORDERING_MASK BIT6 -+#define ATMWCR_WIN_LUNIT_ORDERING (1 << ATMWCR_WIN_LUNIT_FORCE64_OFFS) -+ -+/* PEX Attributes */ -+#define ATMWCR_WIN_PEX_TYPE_OFFS 3 -+#define ATMWCR_WIN_PEX_TYPE_MASK BIT3 -+#define ATMWCR_WIN_PEX_TYPE_IO (0 << ATMWCR_WIN_PEX_TYPE_OFFS) -+#define ATMWCR_WIN_PEX_TYPE_MEM (1 << ATMWCR_WIN_PEX_TYPE_OFFS) -+ -+/* typedefs */ -+ -+/* Unsupported attributes for address decode: */ -+/* 2) PCI0/1_REQ64n control */ -+ -+typedef struct _mvDecRegs -+{ -+ MV_U32 baseReg; -+ MV_U32 baseRegHigh; -+ MV_U32 sizeReg; -+ -+}MV_DEC_REGS; -+ -+typedef struct _mvTargetAttrib -+{ -+ MV_U8 attrib; /* chip select attributes */ -+ MV_TARGET_ID targetId; /* Target Id of this MV_TARGET */ -+ -+}MV_TARGET_ATTRIB; -+ -+ -+/* This structure describes address decode window */ -+typedef struct _mvDecWin -+{ -+ MV_TARGET target; /* Target for addr decode window */ -+ MV_ADDR_WIN addrWin; /* Address window of target */ -+ MV_BOOL enable; /* Window enable/disable */ -+}MV_DEC_WIN; -+ -+typedef struct _mvDecWinParams -+{ -+ MV_TARGET_ID targetId; /* Target ID field */ -+ MV_U8 attrib; /* Attribute field */ -+ MV_U32 baseAddr; /* Base address in register format */ -+ MV_U32 size; /* Size in register format */ -+}MV_DEC_WIN_PARAMS; -+ -+ -+/* mvCtrlEnvAddrDec API list */ -+ -+MV_STATUS mvCtrlAddrDecToReg(MV_ADDR_WIN *pAddrDecWin, -+ MV_DEC_REGS *pAddrDecRegs); -+ -+MV_STATUS mvCtrlRegToAddrDec(MV_DEC_REGS *pAddrDecRegs, -+ MV_ADDR_WIN *pAddrDecWin); -+ -+MV_STATUS mvCtrlAttribGet(MV_TARGET target, -+ MV_TARGET_ATTRIB *targetAttrib); -+ -+MV_TARGET mvCtrlTargetGet(MV_TARGET_ATTRIB *targetAttrib); -+ -+ -+MV_STATUS mvCtrlAddrDecToParams(MV_DEC_WIN *pAddrDecWin, -+ MV_DEC_WIN_PARAMS *pWinParam); -+ -+MV_STATUS mvCtrlParamsToAddrDec(MV_DEC_WIN_PARAMS *pWinParam, -+ MV_DEC_WIN *pAddrDecWin); -+ -+ -+ -+ -+#endif /* __INCmvCtrlEnvAddrDech */ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,98 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvCtrlEnvAsmh -+#define __INCmvCtrlEnvAsmh -+#include "pex/mvPexRegs.h" -+ -+#define CHIP_BOND_REG 0x10034 -+#define PCKG_OPT_MASK_AS #3 -+#define PXCCARI_REVID_MASK_AS #PXCCARI_REVID_MASK -+ -+/* Read device ID into toReg bits 15:0 from 0xd0000000 */ -+/* defines */ -+#define MV_DV_CTRL_MODEL_GET_ASM(toReg, tmpReg) \ -+ MV_DV_REG_READ_ASM(toReg, tmpReg, CHIP_BOND_REG);\ -+ and toReg, toReg, PCKG_OPT_MASK_AS /* Mask for package ID */ -+ -+/* Read device ID into toReg bits 15:0 from 0xf1000000*/ -+#define MV_CTRL_MODEL_GET_ASM(toReg, tmpReg) \ -+ MV_REG_READ_ASM(toReg, tmpReg, CHIP_BOND_REG);\ -+ and toReg, toReg, PCKG_OPT_MASK_AS /* Mask for package ID */ -+ -+/* Read Revision into toReg bits 7:0 0xd0000000*/ -+#define MV_DV_CTRL_REV_GET_ASM(toReg, tmpReg) \ -+ /* Read device revision */ \ -+ MV_DV_REG_READ_ASM(toReg, tmpReg, PEX_CFG_DIRECT_ACCESS(0,PEX_CLASS_CODE_AND_REVISION_ID));\ -+ and toReg, toReg, PXCCARI_REVID_MASK_AS /* Mask for calss ID */ -+ -+/* Read Revision into toReg bits 7:0 0xf1000000*/ -+#define MV_CTRL_REV_GET_ASM(toReg, tmpReg) \ -+ /* Read device revision */ \ -+ MV_REG_READ_ASM(toReg, tmpReg, PEX_CFG_DIRECT_ACCESS(0,PEX_CLASS_CODE_AND_REVISION_ID));\ -+ and toReg, toReg, PXCCARI_REVID_MASK_AS /* Mask for calss ID */ -+ -+ -+#endif /* __INCmvCtrlEnvAsmh */ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,1825 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+/* includes */ -+#include "mvCommon.h" -+#include "mvCtrlEnvLib.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+ -+#if defined(MV_INCLUDE_PEX) -+#include "pex/mvPex.h" -+#include "ctrlEnv/sys/mvSysPex.h" -+#endif -+ -+#if defined(MV_INCLUDE_GIG_ETH) -+#include "ctrlEnv/sys/mvSysGbe.h" -+#endif -+ -+#if defined(MV_INCLUDE_XOR) -+#include "ctrlEnv/sys/mvSysXor.h" -+#endif -+ -+#if defined(MV_INCLUDE_SATA) -+#include "ctrlEnv/sys/mvSysSata.h" -+#endif -+ -+#if defined(MV_INCLUDE_USB) -+#include "ctrlEnv/sys/mvSysUsb.h" -+#endif -+ -+#if defined(MV_INCLUDE_AUDIO) -+#include "ctrlEnv/sys/mvSysAudio.h" -+#endif -+ -+#if defined(MV_INCLUDE_CESA) -+#include "ctrlEnv/sys/mvSysCesa.h" -+#endif -+ -+#if defined(MV_INCLUDE_TS) -+#include "ctrlEnv/sys/mvSysTs.h" -+#endif -+ -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+/******************************************************************************* -+* mvCtrlEnvInit - Initialize Marvell controller environment. -+* -+* DESCRIPTION: -+* This function get environment information and initialize controller -+* internal/external environment. For example -+* 1) MPP settings according to board MPP macros. -+* NOTE: It is the user responsibility to shut down all DMA channels -+* in device and disable controller sub units interrupts during -+* boot process. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvCtrlEnvInit(MV_VOID) -+{ -+ MV_U32 mppGroup; -+ MV_U32 devId; -+ MV_U32 boardId; -+ MV_U32 i; -+ MV_U32 maxMppGrp = 1; -+ MV_U32 mppVal = 0; -+ MV_U32 bootVal = 0; -+ MV_U32 mppGroupType = 0; -+ MV_U32 mppGroup1[][3] = MPP_GROUP_1_TYPE; -+ MV_U32 mppGroup2[][3] = MPP_GROUP_2_TYPE; -+ -+ devId = mvCtrlModelGet(); -+ boardId= mvBoardIdGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ maxMppGrp = MV_6281_MPP_MAX_GROUP; -+ break; -+ case MV_6192_DEV_ID: -+ maxMppGrp = MV_6192_MPP_MAX_GROUP; -+ break; -+ case MV_6190_DEV_ID: -+ maxMppGrp = MV_6190_MPP_MAX_GROUP; -+ break; -+ case MV_6180_DEV_ID: -+ maxMppGrp = MV_6180_MPP_MAX_GROUP; -+ break; -+ } -+ -+ /* MPP Init */ -+ /* We split mpp init to 3 phases: -+ * 1. We init mpp[19:0] from the board info. mpp[23:20] will be over write -+ * in phase 2. -+ * 2. We detect the mpp group type and according the mpp values [35:20]. -+ * 3. We detect the mpp group type and according the mpp values [49:36]. -+ */ -+ /* Mpp phase 1 mpp[19:0] */ -+ /* Read MPP group from board level and assign to MPP register */ -+ for (mppGroup = 0; mppGroup < 3; mppGroup++) -+ { -+ mppVal = mvBoardMppGet(mppGroup); -+ if (mppGroup == 0) -+ { -+ bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); -+ if (mvCtrlIsBootFromSPI()) -+ { -+ mppVal &= ~0xffff; -+ bootVal &= 0xffff; -+ mppVal |= bootVal; -+ } -+ else if (mvCtrlIsBootFromSPIUseNAND()) -+ { -+ mppVal &= ~0xf0000000; -+ bootVal &= 0xf0000000; -+ mppVal |= bootVal; -+ } -+ else if (mvCtrlIsBootFromNAND()) -+ { -+ mppVal &= ~0xffffff; -+ bootVal &= 0xffffff; -+ mppVal |= bootVal; -+ } -+ } -+ -+ if (mppGroup == 2) -+ { -+ bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); -+ if (mvCtrlIsBootFromNAND()) -+ { -+ mppVal &= ~0xff00; -+ bootVal &= 0xff00; -+ mppVal |= bootVal; -+ } -+ } -+ -+ MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal); -+ } -+ -+ /* Identify MPPs group */ -+ mvBoardMppGroupIdUpdate(); -+ -+ /* Update MPPs mux relevent only on Marvell DB */ -+ if ((boardId == DB_88F6281A_BP_ID) || -+ (boardId == DB_88F6180A_BP_ID)) -+ mvBoardMppMuxSet(); -+ -+ mppGroupType = mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_1); -+ -+ /* Mpp phase 2 */ -+ /* Read MPP group from board level and assign to MPP register */ -+ if (devId != MV_6180_DEV_ID) -+ { -+ i = 0; -+ for (mppGroup = 2; mppGroup < 5; mppGroup++) -+ { -+ if ((mppGroupType == MV_BOARD_OTHER) || -+ (boardId == RD_88F6281A_ID) || -+ (boardId == RD_88F6192A_ID) || -+ (boardId == RD_88F6190A_ID) || -+ (boardId == RD_88F6281A_PCAC_ID) || -+ (boardId == SHEEVA_PLUG_ID)) -+ mppVal = mvBoardMppGet(mppGroup); -+ else -+ { -+ mppVal = mppGroup1[mppGroupType][i]; -+ i++; -+ } -+ -+ /* Group 2 is shared mpp[23:16] */ -+ if (mppGroup == 2) -+ { -+ bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); -+ mppVal &= ~0xffff; -+ bootVal &= 0xffff; -+ mppVal |= bootVal; -+ } -+ -+ MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal); -+ } -+ } -+ -+ if ((devId == MV_6192_DEV_ID) || (devId == MV_6190_DEV_ID)) -+ return MV_OK; -+ -+ /* Mpp phase 3 */ -+ mppGroupType = mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_2); -+ /* Read MPP group from board level and assign to MPP register */ -+ i = 0; -+ for (mppGroup = 4; mppGroup < 7; mppGroup++) -+ { -+ if ((mppGroupType == MV_BOARD_OTHER) || -+ (boardId == RD_88F6281A_ID) || -+ (boardId == RD_88F6281A_PCAC_ID) || -+ (boardId == SHEEVA_PLUG_ID)) -+ mppVal = mvBoardMppGet(mppGroup); -+ else -+ { -+ mppVal = mppGroup2[mppGroupType][i]; -+ i++; -+ } -+ -+ /* Group 4 is shared mpp[35:32] */ -+ if (mppGroup == 4) -+ { -+ bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); -+ mppVal &= ~0xffff; -+ bootVal &= 0xffff; -+ mppVal |= bootVal; -+ } -+ -+ MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal); -+ } -+ /* Update SSCG configuration register*/ -+ if(mvBoardIdGet() == DB_88F6281A_BP_ID || mvBoardIdGet() == DB_88F6192A_BP_ID || -+ mvBoardIdGet() == DB_88F6190A_BP_ID || mvBoardIdGet() == DB_88F6180A_BP_ID) -+ MV_REG_WRITE(0x100d8, 0x53); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCtrlMppRegGet - return reg address of mpp group -+* -+* DESCRIPTION: -+* -+* INPUT: -+* mppGroup - MPP group. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_U32 - Register address. -+* -+*******************************************************************************/ -+MV_U32 mvCtrlMppRegGet(MV_U32 mppGroup) -+{ -+ MV_U32 ret; -+ -+ switch(mppGroup){ -+ case (0): ret = MPP_CONTROL_REG0; -+ break; -+ case (1): ret = MPP_CONTROL_REG1; -+ break; -+ case (2): ret = MPP_CONTROL_REG2; -+ break; -+ case (3): ret = MPP_CONTROL_REG3; -+ break; -+ case (4): ret = MPP_CONTROL_REG4; -+ break; -+ case (5): ret = MPP_CONTROL_REG5; -+ break; -+ case (6): ret = MPP_CONTROL_REG6; -+ break; -+ default: ret = MPP_CONTROL_REG0; -+ break; -+ } -+ return ret; -+} -+#if defined(MV_INCLUDE_PEX) -+/******************************************************************************* -+* mvCtrlPexMaxIfGet - Get Marvell controller number of PEX interfaces. -+* -+* DESCRIPTION: -+* This function returns Marvell controller number of PEX interfaces. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Marvell controller number of PEX interfaces. If controller -+* ID is undefined the function returns '0'. -+* -+*******************************************************************************/ -+MV_U32 mvCtrlPexMaxIfGet(MV_VOID) -+{ -+ -+ return MV_PEX_MAX_IF; -+} -+#endif -+ -+#if defined(MV_INCLUDE_GIG_ETH) -+/******************************************************************************* -+* mvCtrlEthMaxPortGet - Get Marvell controller number of etherent ports. -+* -+* DESCRIPTION: -+* This function returns Marvell controller number of etherent port. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Marvell controller number of etherent port. -+* -+*******************************************************************************/ -+MV_U32 mvCtrlEthMaxPortGet(MV_VOID) -+{ -+ MV_U32 devId; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ return MV_6281_ETH_MAX_PORTS; -+ break; -+ case MV_6192_DEV_ID: -+ return MV_6192_ETH_MAX_PORTS; -+ break; -+ case MV_6190_DEV_ID: -+ return MV_6190_ETH_MAX_PORTS; -+ break; -+ case MV_6180_DEV_ID: -+ return MV_6180_ETH_MAX_PORTS; -+ break; -+ } -+ return 0; -+ -+} -+#endif -+ -+#if defined(MV_INCLUDE_XOR) -+/******************************************************************************* -+* mvCtrlXorMaxChanGet - Get Marvell controller number of XOR channels. -+* -+* DESCRIPTION: -+* This function returns Marvell controller number of XOR channels. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Marvell controller number of XOR channels. -+* -+*******************************************************************************/ -+MV_U32 mvCtrlXorMaxChanGet(MV_VOID) -+{ -+ return MV_XOR_MAX_CHAN; -+} -+#endif -+ -+#if defined(MV_INCLUDE_USB) -+/******************************************************************************* -+* mvCtrlUsbHostMaxGet - Get number of Marvell Usb controllers -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* returns number of Marvell USB controllers. -+* -+*******************************************************************************/ -+MV_U32 mvCtrlUsbMaxGet(void) -+{ -+ return MV_USB_MAX_PORTS; -+} -+#endif -+ -+ -+#if defined(MV_INCLUDE_NAND) -+/******************************************************************************* -+* mvCtrlNandSupport - Return if this controller has integrated NAND flash support -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if NAND is supported and MV_FALSE otherwise -+* -+*******************************************************************************/ -+MV_U32 mvCtrlNandSupport(MV_VOID) -+{ -+ MV_U32 devId; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ return MV_6281_NAND; -+ break; -+ case MV_6192_DEV_ID: -+ return MV_6192_NAND; -+ break; -+ case MV_6190_DEV_ID: -+ return MV_6190_NAND; -+ break; -+ case MV_6180_DEV_ID: -+ return MV_6180_NAND; -+ break; -+ } -+ return 0; -+ -+} -+#endif -+ -+#if defined(MV_INCLUDE_SDIO) -+/******************************************************************************* -+* mvCtrlSdioSupport - Return if this controller has integrated SDIO flash support -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if SDIO is supported and MV_FALSE otherwise -+* -+*******************************************************************************/ -+MV_U32 mvCtrlSdioSupport(MV_VOID) -+{ -+ MV_U32 devId; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ return MV_6281_SDIO; -+ break; -+ case MV_6192_DEV_ID: -+ return MV_6192_SDIO; -+ break; -+ case MV_6190_DEV_ID: -+ return MV_6190_SDIO; -+ break; -+ case MV_6180_DEV_ID: -+ return MV_6180_SDIO; -+ break; -+ } -+ return 0; -+ -+} -+#endif -+ -+#if defined(MV_INCLUDE_TS) -+/******************************************************************************* -+* mvCtrlTsSupport - Return if this controller has integrated TS flash support -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if TS is supported and MV_FALSE otherwise -+* -+*******************************************************************************/ -+MV_U32 mvCtrlTsSupport(MV_VOID) -+{ -+ MV_U32 devId; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ return MV_6281_TS; -+ break; -+ case MV_6192_DEV_ID: -+ return MV_6192_TS; -+ break; -+ case MV_6190_DEV_ID: -+ return MV_6190_TS; -+ break; -+ case MV_6180_DEV_ID: -+ return MV_6180_TS; -+ break; -+ } -+ return 0; -+} -+#endif -+ -+#if defined(MV_INCLUDE_AUDIO) -+/******************************************************************************* -+* mvCtrlAudioSupport - Return if this controller has integrated AUDIO flash support -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if AUDIO is supported and MV_FALSE otherwise -+* -+*******************************************************************************/ -+MV_U32 mvCtrlAudioSupport(MV_VOID) -+{ -+ MV_U32 devId; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ return MV_6281_AUDIO; -+ break; -+ case MV_6192_DEV_ID: -+ return MV_6192_AUDIO; -+ break; -+ case MV_6190_DEV_ID: -+ return MV_6190_AUDIO; -+ break; -+ case MV_6180_DEV_ID: -+ return MV_6180_AUDIO; -+ break; -+ } -+ return 0; -+ -+} -+#endif -+ -+#if defined(MV_INCLUDE_TDM) -+/******************************************************************************* -+* mvCtrlTdmSupport - Return if this controller has integrated TDM flash support -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if TDM is supported and MV_FALSE otherwise -+* -+*******************************************************************************/ -+MV_U32 mvCtrlTdmSupport(MV_VOID) -+{ -+ MV_U32 devId; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ return MV_6281_TDM; -+ break; -+ case MV_6192_DEV_ID: -+ return MV_6192_TDM; -+ break; -+ case MV_6190_DEV_ID: -+ return MV_6190_TDM; -+ break; -+ case MV_6180_DEV_ID: -+ return MV_6180_TDM; -+ break; -+ } -+ return 0; -+ -+} -+#endif -+ -+/******************************************************************************* -+* mvCtrlModelGet - Get Marvell controller device model (Id) -+* -+* DESCRIPTION: -+* This function returns 16bit describing the device model (ID) as defined -+* in PCI Device and Vendor ID configuration register offset 0x0. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 16bit desscribing Marvell controller ID -+* -+*******************************************************************************/ -+MV_U16 mvCtrlModelGet(MV_VOID) -+{ -+ MV_U32 devId; -+ -+ devId = MV_REG_READ(CHIP_BOND_REG); -+ devId &= PCKG_OPT_MASK; -+ -+ switch(devId){ -+ case 2: -+ return MV_6281_DEV_ID; -+ break; -+ case 1: -+ if (((MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0,PEX_DEVICE_AND_VENDOR_ID))& 0xffff0000) >> 16) -+ == MV_6190_DEV_ID) -+ return MV_6190_DEV_ID; -+ else -+ return MV_6192_DEV_ID; -+ break; -+ case 0: -+ return MV_6180_DEV_ID; -+ break; -+ } -+ -+ return 0; -+} -+/******************************************************************************* -+* mvCtrlRevGet - Get Marvell controller device revision number -+* -+* DESCRIPTION: -+* This function returns 8bit describing the device revision as defined -+* in PCI Express Class Code and Revision ID Register. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 8bit desscribing Marvell controller revision number -+* -+*******************************************************************************/ -+MV_U8 mvCtrlRevGet(MV_VOID) -+{ -+ MV_U8 revNum; -+#if defined(MV_INCLUDE_CLK_PWR_CNTRL) -+ /* Check pex power state */ -+ MV_U32 pexPower; -+ pexPower = mvCtrlPwrClckGet(PEX_UNIT_ID,0); -+ if (pexPower == MV_FALSE) -+ mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_TRUE); -+#endif -+ revNum = (MV_U8)MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0,PCI_CLASS_CODE_AND_REVISION_ID)); -+#if defined(MV_INCLUDE_CLK_PWR_CNTRL) -+ /* Return to power off state */ -+ if (pexPower == MV_FALSE) -+ mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_FALSE); -+#endif -+ return ((revNum & PCCRIR_REVID_MASK) >> PCCRIR_REVID_OFFS); -+} -+ -+/******************************************************************************* -+* mvCtrlNameGet - Get Marvell controller name -+* -+* DESCRIPTION: -+* This function returns a string describing the device model and revision. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* pNameBuff - Buffer to contain device name string. Minimum size 30 chars. -+* -+* RETURN: -+* -+* MV_ERROR if informantion can not be read. -+*******************************************************************************/ -+MV_STATUS mvCtrlNameGet(char *pNameBuff) -+{ -+ mvOsSPrintf (pNameBuff, "%s%x Rev %d", SOC_NAME_PREFIX, -+ mvCtrlModelGet(), mvCtrlRevGet()); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCtrlModelRevGet - Get Controller Model (Device ID) and Revision -+* -+* DESCRIPTION: -+* This function returns 32bit value describing both Device ID and Revision -+* as defined in PCI Express Device and Vendor ID Register and device revision -+* as defined in PCI Express Class Code and Revision ID Register. -+ -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit describing both controller device ID and revision number -+* -+*******************************************************************************/ -+MV_U32 mvCtrlModelRevGet(MV_VOID) -+{ -+ return ((mvCtrlModelGet() << 16) | mvCtrlRevGet()); -+} -+ -+/******************************************************************************* -+* mvCtrlModelRevNameGet - Get Marvell controller name -+* -+* DESCRIPTION: -+* This function returns a string describing the device model and revision. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* pNameBuff - Buffer to contain device name string. Minimum size 30 chars. -+* -+* RETURN: -+* -+* MV_ERROR if informantion can not be read. -+*******************************************************************************/ -+ -+MV_STATUS mvCtrlModelRevNameGet(char *pNameBuff) -+{ -+ -+ switch (mvCtrlModelRevGet()) -+ { -+ case MV_6281_A0_ID: -+ mvOsSPrintf (pNameBuff, "%s",MV_6281_A0_NAME); -+ break; -+ case MV_6192_A0_ID: -+ mvOsSPrintf (pNameBuff, "%s",MV_6192_A0_NAME); -+ break; -+ case MV_6180_A0_ID: -+ mvOsSPrintf (pNameBuff, "%s",MV_6180_A0_NAME); -+ break; -+ case MV_6190_A0_ID: -+ mvOsSPrintf (pNameBuff, "%s",MV_6190_A0_NAME); -+ break; -+ case MV_6281_A1_ID: -+ mvOsSPrintf (pNameBuff, "%s",MV_6281_A1_NAME); -+ break; -+ case MV_6192_A1_ID: -+ mvOsSPrintf (pNameBuff, "%s",MV_6192_A1_NAME); -+ break; -+ case MV_6180_A1_ID: -+ mvOsSPrintf (pNameBuff, "%s",MV_6180_A1_NAME); -+ break; -+ case MV_6190_A1_ID: -+ mvOsSPrintf (pNameBuff, "%s",MV_6190_A1_NAME); -+ break; -+ default: -+ mvCtrlNameGet(pNameBuff); -+ break; -+ } -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* ctrlWinOverlapTest - Test address windows for overlaping. -+* -+* DESCRIPTION: -+* This function checks the given two address windows for overlaping. -+* -+* INPUT: -+* pAddrWin1 - Address window 1. -+* pAddrWin2 - Address window 2. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* MV_TRUE if address window overlaps, MV_FALSE otherwise. -+*******************************************************************************/ -+MV_STATUS ctrlWinOverlapTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2) -+{ -+ MV_U32 winBase1, winBase2; -+ MV_U32 winTop1, winTop2; -+ -+ /* check if we have overflow than 4G*/ -+ if (((0xffffffff - pAddrWin1->baseLow) < pAddrWin1->size-1)|| -+ ((0xffffffff - pAddrWin2->baseLow) < pAddrWin2->size-1)) -+ { -+ return MV_TRUE; -+ } -+ -+ winBase1 = pAddrWin1->baseLow; -+ winBase2 = pAddrWin2->baseLow; -+ winTop1 = winBase1 + pAddrWin1->size-1; -+ winTop2 = winBase2 + pAddrWin2->size-1; -+ -+ -+ if (((winBase1 <= winTop2 ) && ( winTop2 <= winTop1)) || -+ ((winBase1 <= winBase2) && (winBase2 <= winTop1))) -+ { -+ return MV_TRUE; -+ } -+ else -+ { -+ return MV_FALSE; -+ } -+} -+ -+/******************************************************************************* -+* ctrlWinWithinWinTest - Test address windows for overlaping. -+* -+* DESCRIPTION: -+* This function checks the given win1 boundries is within -+* win2 boundries. -+* -+* INPUT: -+* pAddrWin1 - Address window 1. -+* pAddrWin2 - Address window 2. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* MV_TRUE if found win1 inside win2, MV_FALSE otherwise. -+*******************************************************************************/ -+MV_STATUS ctrlWinWithinWinTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2) -+{ -+ MV_U32 winBase1, winBase2; -+ MV_U32 winTop1, winTop2; -+ -+ winBase1 = pAddrWin1->baseLow; -+ winBase2 = pAddrWin2->baseLow; -+ winTop1 = winBase1 + pAddrWin1->size -1; -+ winTop2 = winBase2 + pAddrWin2->size -1; -+ -+ if (((winBase1 >= winBase2 ) && ( winBase1 <= winTop2)) || -+ ((winTop1 >= winBase2) && (winTop1 <= winTop2))) -+ { -+ return MV_TRUE; -+ } -+ else -+ { -+ return MV_FALSE; -+ } -+} -+ -+static const char* cntrlName[] = TARGETS_NAME_ARRAY; -+ -+/******************************************************************************* -+* mvCtrlTargetNameGet - Get Marvell controller target name -+* -+* DESCRIPTION: -+* This function convert the trget enumeration to string. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Target name (const MV_8 *) -+*******************************************************************************/ -+const MV_8* mvCtrlTargetNameGet( MV_TARGET target ) -+{ -+ -+ if (target >= MAX_TARGETS) -+ { -+ return "target unknown"; -+ } -+ -+ return cntrlName[target]; -+} -+ -+/******************************************************************************* -+* mvCtrlAddrDecShow - Print the Controller units address decode map. -+* -+* DESCRIPTION: -+* This function the Controller units address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvCtrlAddrDecShow(MV_VOID) -+{ -+ mvCpuIfAddDecShow(); -+ mvAhbToMbusAddDecShow(); -+#if defined(MV_INCLUDE_PEX) -+ mvPexAddrDecShow(); -+#endif -+#if defined(MV_INCLUDE_USB) -+ mvUsbAddrDecShow(); -+#endif -+#if defined(MV_INCLUDE_GIG_ETH) -+ mvEthAddrDecShow(); -+#endif -+#if defined(MV_INCLUDE_XOR) -+ mvXorAddrDecShow(); -+#endif -+#if defined(MV_INCLUDE_SATA) -+ mvSataAddrDecShow(); -+#endif -+#if defined(MV_INCLUDE_AUDIO) -+ mvAudioAddrDecShow(); -+#endif -+#if defined(MV_INCLUDE_TS) -+ mvTsuAddrDecShow(); -+#endif -+} -+ -+/******************************************************************************* -+* ctrlSizeToReg - Extract size value for register assignment. -+* -+* DESCRIPTION: -+* Address decode size parameter must be programed from LSB to MSB as -+* sequence of 1's followed by sequence of 0's. The number of 1's -+* specifies the size of the window in 64 KB granularity (e.g. a -+* value of 0x00ff specifies 256x64k = 16 MB). -+* This function extract the size value from the size parameter according -+* to given aligment paramter. For example for size 0x1000000 (16MB) and -+* aligment 0x10000 (64KB) the function will return 0x00FF. -+* -+* INPUT: -+* size - Size. -+* alignment - Size alignment. Note that alignment must be power of 2! -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit describing size register value correspond to size parameter. -+* If value is '-1' size parameter or aligment are invalid. -+*******************************************************************************/ -+MV_U32 ctrlSizeToReg(MV_U32 size, MV_U32 alignment) -+{ -+ MV_U32 retVal; -+ -+ /* Check size parameter alignment */ -+ if ((0 == size) || (MV_IS_NOT_ALIGN(size, alignment))) -+ { -+ DB(mvOsPrintf("ctrlSizeToReg: ERR. Size is zero or not aligned.\n")); -+ return -1; -+ } -+ -+ /* Take out the "alignment" portion out of the size parameter */ -+ alignment--; /* Now the alignmet is a sequance of '1' (e.g. 0xffff) */ -+ /* and size is 0x1000000 (16MB) for example */ -+ while(alignment & 1) /* Check that alignmet LSB is set */ -+ { -+ size = (size >> 1); /* If LSB is set, move 'size' one bit to right */ -+ alignment = (alignment >> 1); -+ } -+ -+ /* If after the alignment first '0' was met we still have '1' in */ -+ /* it then aligment is invalid (not power of 2) */ -+ if (alignment) -+ { -+ DB(mvOsPrintf("ctrlSizeToReg: ERR. Alignment parameter 0x%x invalid.\n", -+ (MV_U32)alignment)); -+ return -1; -+ } -+ -+ /* Now the size is shifted right according to aligment: 0x0100 */ -+ size--; /* Now the size is a sequance of '1': 0x00ff */ -+ -+ retVal = size ; -+ -+ /* Check that LSB to MSB is sequence of 1's followed by sequence of 0's */ -+ while(size & 1) /* Check that LSB is set */ -+ { -+ size = (size >> 1); /* If LSB is set, move one bit to the right */ -+ } -+ -+ if (size) /* Sequance of 1's is over. Check that we have no other 1's */ -+ { -+ DB(mvOsPrintf("ctrlSizeToReg: ERR. Size parameter 0x%x invalid.\n", -+ size)); -+ return -1; -+ } -+ -+ return retVal; -+ -+} -+ -+/******************************************************************************* -+* ctrlRegToSize - Extract size value from register value. -+* -+* DESCRIPTION: -+* This function extract a size value from the register size parameter -+* according to given aligment paramter. For example for register size -+* value 0xff and aligment 0x10000 the function will return 0x01000000. -+* -+* INPUT: -+* regSize - Size as in register format. See ctrlSizeToReg. -+* alignment - Size alignment. Note that alignment must be power of 2! -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit describing size. -+* If value is '-1' size parameter or aligment are invalid. -+*******************************************************************************/ -+MV_U32 ctrlRegToSize(MV_U32 regSize, MV_U32 alignment) -+{ -+ MV_U32 temp; -+ -+ /* Check that LSB to MSB is sequence of 1's followed by sequence of 0's */ -+ temp = regSize; /* Now the size is a sequance of '1': 0x00ff */ -+ -+ while(temp & 1) /* Check that LSB is set */ -+ { -+ temp = (temp >> 1); /* If LSB is set, move one bit to the right */ -+ } -+ -+ if (temp) /* Sequance of 1's is over. Check that we have no other 1's */ -+ { -+ DB(mvOsPrintf("ctrlRegToSize: ERR. Size parameter 0x%x invalid.\n", -+ regSize)); -+ return -1; -+ } -+ -+ -+ /* Check that aligment is a power of two */ -+ temp = alignment - 1;/* Now the alignmet is a sequance of '1' (0xffff) */ -+ -+ while(temp & 1) /* Check that alignmet LSB is set */ -+ { -+ temp = (temp >> 1); /* If LSB is set, move 'size' one bit to right */ -+ } -+ -+ /* If after the 'temp' first '0' was met we still have '1' in 'temp' */ -+ /* then 'temp' is invalid (not power of 2) */ -+ if (temp) -+ { -+ DB(mvOsPrintf("ctrlSizeToReg: ERR. Alignment parameter 0x%x invalid.\n", -+ alignment)); -+ return -1; -+ } -+ -+ regSize++; /* Now the size is 0x0100 */ -+ -+ /* Add in the "alignment" portion to the register size parameter */ -+ alignment--; /* Now the alignmet is a sequance of '1' (e.g. 0xffff) */ -+ -+ while(alignment & 1) /* Check that alignmet LSB is set */ -+ { -+ regSize = (regSize << 1); /* LSB is set, move 'size' one bit left */ -+ alignment = (alignment >> 1); -+ } -+ -+ return regSize; -+} -+ -+ -+/******************************************************************************* -+* ctrlSizeRegRoundUp - Round up given size -+* -+* DESCRIPTION: -+* This function round up a given size to a size that fits the -+* restrictions of size format given an aligment parameter. -+* to given aligment paramter. For example for size parameter 0xa1000 and -+* aligment 0x1000 the function will return 0xFF000. -+* -+* INPUT: -+* size - Size. -+* alignment - Size alignment. Note that alignment must be power of 2! -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit describing size value correspond to size in register. -+*******************************************************************************/ -+MV_U32 ctrlSizeRegRoundUp(MV_U32 size, MV_U32 alignment) -+{ -+ MV_U32 msbBit = 0; -+ MV_U32 retSize; -+ -+ /* Check if size parameter is already comply with restriction */ -+ if (!(-1 == ctrlSizeToReg(size, alignment))) -+ { -+ return size; -+ } -+ -+ while(size) -+ { -+ size = (size >> 1); -+ msbBit++; -+ } -+ -+ retSize = (1 << msbBit); -+ -+ if (retSize < alignment) -+ { -+ return alignment; -+ } -+ else -+ { -+ return retSize; -+ } -+} -+/******************************************************************************* -+* mvCtrlSysRstLengthCounterGet - Return number of milliseconds the reset button -+* was pressed and clear counter -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: number of milliseconds the reset button was pressed -+*******************************************************************************/ -+MV_U32 mvCtrlSysRstLengthCounterGet(MV_VOID) -+{ -+ static volatile MV_U32 Count = 0; -+ -+ if(!Count) { -+ Count = (MV_REG_READ(SYSRST_LENGTH_COUNTER_REG) & SLCR_COUNT_MASK); -+ Count = (Count / (MV_BOARD_REFCLK_25MHZ / 1000)); -+ /* clear counter for next boot */ -+ MV_REG_BIT_SET(SYSRST_LENGTH_COUNTER_REG, SLCR_CLR_MASK); -+ } -+ -+ DB(mvOsPrintf("mvCtrlSysRstLengthCounterGet: Reset button was pressed for %u milliseconds\n", Count)); -+ -+ return Count; -+} -+ -+MV_BOOL mvCtrlIsBootFromSPI(MV_VOID) -+{ -+ MV_U32 satr = 0; -+ satr = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ if(mvCtrlModelGet() == MV_6180_DEV_ID) -+ { -+ if (MSAR_BOOT_MODE_6180(satr) == MSAR_BOOT_SPI_WITH_BOOTROM_6180) -+ return MV_TRUE; -+ else -+ return MV_FALSE; -+ } -+ satr = satr & MSAR_BOOT_MODE_MASK; -+ if (satr == MSAR_BOOT_SPI_WITH_BOOTROM) -+ return MV_TRUE; -+ else -+ return MV_FALSE; -+} -+ -+MV_BOOL mvCtrlIsBootFromSPIUseNAND(MV_VOID) -+{ -+ MV_U32 satr = 0; -+ if(mvCtrlModelGet() == MV_6180_DEV_ID) -+ return MV_FALSE; -+ satr = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ satr = satr & MSAR_BOOT_MODE_MASK; -+ -+ if (satr == MSAR_BOOT_SPI_USE_NAND_WITH_BOOTROM) -+ return MV_TRUE; -+ else -+ return MV_FALSE; -+} -+ -+MV_BOOL mvCtrlIsBootFromNAND(MV_VOID) -+{ -+ MV_U32 satr = 0; -+ satr = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ if(mvCtrlModelGet() == MV_6180_DEV_ID) -+ { -+ if (MSAR_BOOT_MODE_6180(satr) == MSAR_BOOT_NAND_WITH_BOOTROM_6180) -+ return MV_TRUE; -+ else -+ return MV_FALSE; -+ } -+ satr = satr & MSAR_BOOT_MODE_MASK; -+ if ((satr == MSAR_BOOT_NAND_WITH_BOOTROM)) -+ return MV_TRUE; -+ else -+ return MV_FALSE; -+} -+ -+#if defined(MV_INCLUDE_CLK_PWR_CNTRL) -+/******************************************************************************* -+* mvCtrlPwrSaveOn - Set Power save mode -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+*******************************************************************************/ -+MV_VOID mvCtrlPwrSaveOn(MV_VOID) -+{ -+ unsigned long old,temp; -+ /* Disable int */ -+ __asm__ __volatile__("mrs %0, cpsr\n" -+ "orr %1, %0, #0xc0\n" -+ "msr cpsr_c, %1" -+ : "=r" (old), "=r" (temp) -+ : -+ : "memory"); -+ -+ /* Set SoC in power save */ -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, BIT11); -+ /* Wait for int */ -+ __asm__ __volatile__("mcr p15, 0, r0, c7, c0, 4"); -+ -+ /* Enabled int */ -+ __asm__ __volatile__("msr cpsr_c, %0" -+ : -+ : "r" (old) -+ : "memory"); -+} -+ -+ -+ -+/******************************************************************************* -+* mvCtrlPwrSaveOff - Go out of power save mode -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+*******************************************************************************/ -+MV_VOID mvCtrlPwrSaveOff(MV_VOID) -+{ -+ unsigned long old,temp; -+ /* Disable int */ -+ __asm__ __volatile__("mrs %0, cpsr\n" -+ "orr %1, %0, #0xc0\n" -+ "msr cpsr_c, %1" -+ : "=r" (old), "=r" (temp) -+ : -+ : "memory"); -+ -+ /* Set SoC in power save */ -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, BIT11); -+ /* Wait for int */ -+ __asm__ __volatile__("mcr p15, 0, r0, c7, c0, 4"); -+ -+ /* Enabled int */ -+ __asm__ __volatile__("msr cpsr_c, %0" -+ : -+ : "r" (old) -+ : "memory"); -+} -+ -+/******************************************************************************* -+* mvCtrlPwrClckSet - Set Power State for specific Unit -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+*******************************************************************************/ -+MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) -+{ -+ switch (unitId) -+ { -+#if defined(MV_INCLUDE_PEX) -+ case PEX_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_PEXSTOPCLOCK_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_PEXSTOPCLOCK_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_GIG_ETH) -+ case ETH_GIG_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_GESTOPCLOCK_MASK(index)); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_GESTOPCLOCK_MASK(index)); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_INTEG_SATA) -+ case SATA_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SATASTOPCLOCK_MASK(index)); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SATASTOPCLOCK_MASK(index)); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_CESA) -+ case CESA_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SESTOPCLOCK_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SESTOPCLOCK_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_USB) -+ case USB_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_USBSTOPCLOCK_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_USBSTOPCLOCK_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_AUDIO) -+ case AUDIO_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_AUDIOSTOPCLOCK_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_AUDIOSTOPCLOCK_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_TS) -+ case TS_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_TSSTOPCLOCK_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_TSSTOPCLOCK_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_SDIO) -+ case SDIO_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SDIOSTOPCLOCK_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SDIOSTOPCLOCK_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_TDM) -+ case TDM_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_TDMSTOPCLOCK_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_TDMSTOPCLOCK_MASK); -+ } -+ break; -+#endif -+ -+ default: -+ -+ break; -+ -+ } -+} -+ -+/******************************************************************************* -+* mvCtrlPwrClckGet - Get Power State of specific Unit -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+******************************************************************************/ -+MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index) -+{ -+ MV_U32 reg = MV_REG_READ(POWER_MNG_CTRL_REG); -+ MV_BOOL state = MV_TRUE; -+ -+ switch (unitId) -+ { -+#if defined(MV_INCLUDE_PEX) -+ case PEX_UNIT_ID: -+ if ((reg & PMC_PEXSTOPCLOCK_MASK) == PMC_PEXSTOPCLOCK_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ -+ break; -+#endif -+#if defined(MV_INCLUDE_GIG_ETH) -+ case ETH_GIG_UNIT_ID: -+ if ((reg & PMC_GESTOPCLOCK_MASK(index)) == PMC_GESTOPCLOCK_STOP(index)) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_SATA) -+ case SATA_UNIT_ID: -+ if ((reg & PMC_SATASTOPCLOCK_MASK(index)) == PMC_SATASTOPCLOCK_STOP(index)) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_CESA) -+ case CESA_UNIT_ID: -+ if ((reg & PMC_SESTOPCLOCK_MASK) == PMC_SESTOPCLOCK_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_USB) -+ case USB_UNIT_ID: -+ if ((reg & PMC_USBSTOPCLOCK_MASK) == PMC_USBSTOPCLOCK_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_AUDIO) -+ case AUDIO_UNIT_ID: -+ if ((reg & PMC_AUDIOSTOPCLOCK_MASK) == PMC_AUDIOSTOPCLOCK_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_TS) -+ case TS_UNIT_ID: -+ if ((reg & PMC_TSSTOPCLOCK_MASK) == PMC_TSSTOPCLOCK_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_SDIO) -+ case SDIO_UNIT_ID: -+ if ((reg & PMC_SDIOSTOPCLOCK_MASK)== PMC_SDIOSTOPCLOCK_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_TDM) -+ case TDM_UNIT_ID: -+ if ((reg & PMC_TDMSTOPCLOCK_MASK) == PMC_TDMSTOPCLOCK_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+ -+ default: -+ state = MV_TRUE; -+ break; -+ } -+ -+ -+ return state; -+} -+/******************************************************************************* -+* mvCtrlPwrMemSet - Set Power State for memory on specific Unit -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+*******************************************************************************/ -+MV_VOID mvCtrlPwrMemSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) -+{ -+ switch (unitId) -+ { -+#if defined(MV_INCLUDE_PEX) -+ case PEX_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_PEXSTOPMEM_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_PEXSTOPMEM_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_GIG_ETH) -+ case ETH_GIG_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_GESTOPMEM_MASK(index)); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_GESTOPMEM_MASK(index)); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_INTEG_SATA) -+ case SATA_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_SATASTOPMEM_MASK(index)); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_SATASTOPMEM_MASK(index)); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_CESA) -+ case CESA_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_SESTOPMEM_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_SESTOPMEM_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_USB) -+ case USB_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_USBSTOPMEM_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_USBSTOPMEM_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_AUDIO) -+ case AUDIO_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_AUDIOSTOPMEM_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_AUDIOSTOPMEM_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_XOR) -+ case XOR_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_XORSTOPMEM_MASK(index)); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_XORSTOPMEM_MASK(index)); -+ } -+ break; -+#endif -+ default: -+ -+ break; -+ -+ } -+} -+ -+/******************************************************************************* -+* mvCtrlPwrMemGet - Get Power State of memory on specific Unit -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+******************************************************************************/ -+MV_BOOL mvCtrlPwrMemGet(MV_UNIT_ID unitId, MV_U32 index) -+{ -+ MV_U32 reg = MV_REG_READ(POWER_MNG_MEM_CTRL_REG); -+ MV_BOOL state = MV_TRUE; -+ -+ switch (unitId) -+ { -+#if defined(MV_INCLUDE_PEX) -+ case PEX_UNIT_ID: -+ if ((reg & PMC_PEXSTOPMEM_MASK) == PMC_PEXSTOPMEM_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ -+ break; -+#endif -+#if defined(MV_INCLUDE_GIG_ETH) -+ case ETH_GIG_UNIT_ID: -+ if ((reg & PMC_GESTOPMEM_MASK(index)) == PMC_GESTOPMEM_STOP(index)) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_SATA) -+ case SATA_UNIT_ID: -+ if ((reg & PMC_SATASTOPMEM_MASK(index)) == PMC_SATASTOPMEM_STOP(index)) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_CESA) -+ case CESA_UNIT_ID: -+ if ((reg & PMC_SESTOPMEM_MASK) == PMC_SESTOPMEM_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_USB) -+ case USB_UNIT_ID: -+ if ((reg & PMC_USBSTOPMEM_MASK) == PMC_USBSTOPMEM_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_AUDIO) -+ case AUDIO_UNIT_ID: -+ if ((reg & PMC_AUDIOSTOPMEM_MASK) == PMC_AUDIOSTOPMEM_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_XOR) -+ case XOR_UNIT_ID: -+ if ((reg & PMC_XORSTOPMEM_MASK(index)) == PMC_XORSTOPMEM_STOP(index)) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+ -+ default: -+ state = MV_TRUE; -+ break; -+ } -+ -+ -+ return state; -+} -+#else -+MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) {return;} -+MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index) {return MV_TRUE;} -+#endif /* #if defined(MV_INCLUDE_CLK_PWR_CNTRL) */ -+ -+ -+/******************************************************************************* -+* mvMPPConfigToSPI - Change MPP[3:0] configuration to SPI mode -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+******************************************************************************/ -+MV_VOID mvMPPConfigToSPI(MV_VOID) -+{ -+ MV_U32 mppVal = 0; -+ MV_U32 bootVal = 0; -+ -+ if(!mvCtrlIsBootFromSPIUseNAND()) -+ return; -+ mppVal = 0x00002220; /* Set MPP [3:1] to SPI mode */ -+ bootVal = MV_REG_READ(mvCtrlMppRegGet(0)); -+ bootVal &= 0xffff000f; -+ mppVal |= bootVal; -+ -+ MV_REG_WRITE(mvCtrlMppRegGet(0), mppVal); -+} -+ -+ -+/******************************************************************************* -+* mvMPPConfigToDefault - Change MPP[7:0] configuration to default configuration -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+******************************************************************************/ -+MV_VOID mvMPPConfigToDefault(MV_VOID) -+{ -+ MV_U32 mppVal = 0; -+ MV_U32 bootVal = 0; -+ -+ if(!mvCtrlIsBootFromSPIUseNAND()) -+ return; -+ mppVal = mvBoardMppGet(0); -+ bootVal = MV_REG_READ(mvCtrlMppRegGet(0)); -+ mppVal &= ~0xffff000f; -+ bootVal &= 0xffff000f; -+ mppVal |= bootVal; -+ -+ MV_REG_WRITE(mvCtrlMppRegGet(0), mppVal); -+} -+ -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,185 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvCtrlEnvLibh -+#define __INCmvCtrlEnvLibh -+ -+/* includes */ -+#include "mvSysHwConfig.h" -+#include "mvCommon.h" -+#include "mvTypes.h" -+#include "mvOs.h" -+#include "boardEnv/mvBoardEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+#include "ctrlEnv/mvCtrlEnvRegs.h" -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+ -+ -+/* typedefs */ -+ -+/* This enumerator describes the possible HW cache coherency policies the */ -+/* controllers supports. */ -+typedef enum _mvCachePolicy -+{ -+ NO_COHERENCY, /* No HW cache coherency support */ -+ WT_COHERENCY, /* HW cache coherency supported in Write Through policy */ -+ WB_COHERENCY /* HW cache coherency supported in Write Back policy */ -+}MV_CACHE_POLICY; -+ -+ -+/* The swapping is referred to a 64-bit words (as this is the controller */ -+/* internal data path width). This enumerator describes the possible */ -+/* data swap types. Below is an example of the data 0x0011223344556677 */ -+typedef enum _mvSwapType -+{ -+ MV_BYTE_SWAP, /* Byte Swap 77 66 55 44 33 22 11 00 */ -+ MV_NO_SWAP, /* No swapping 00 11 22 33 44 55 66 77 */ -+ MV_BYTE_WORD_SWAP, /* Both byte and word swap 33 22 11 00 77 66 55 44 */ -+ MV_WORD_SWAP, /* Word swap 44 55 66 77 00 11 22 33 */ -+ SWAP_TYPE_MAX /* Delimiter for this enumerator */ -+}MV_SWAP_TYPE; -+ -+/* This structure describes access rights for Access protection windows */ -+/* that can be found in IDMA, XOR, Ethernet and MPSC units. */ -+/* Note that the permission enumerator coresponds to its register format. */ -+/* For example, Read only premission is presented as "1" in register field. */ -+typedef enum _mvAccessRights -+{ -+ NO_ACCESS_ALLOWED = 0, /* No access allowed */ -+ READ_ONLY = 1, /* Read only permission */ -+ ACC_RESERVED = 2, /* Reserved access right */ -+ FULL_ACCESS = 3, /* Read and Write permission */ -+ MAX_ACC_RIGHTS -+}MV_ACCESS_RIGHTS; -+ -+ -+/* mcspLib.h API list */ -+ -+MV_STATUS mvCtrlEnvInit(MV_VOID); -+MV_U32 mvCtrlMppRegGet(MV_U32 mppGroup); -+ -+#if defined(MV_INCLUDE_PEX) -+MV_U32 mvCtrlPexMaxIfGet(MV_VOID); -+#else -+#define mvCtrlPexMaxIfGet() (0) -+#endif -+ -+#define mvCtrlPciIfMaxIfGet() (0) -+ -+#if defined(MV_INCLUDE_GIG_ETH) -+MV_U32 mvCtrlEthMaxPortGet(MV_VOID); -+#endif -+#if defined(MV_INCLUDE_XOR) -+MV_U32 mvCtrlXorMaxChanGet(MV_VOID); -+#endif -+#if defined(MV_INCLUDE_USB) -+MV_U32 mvCtrlUsbMaxGet(MV_VOID); -+#endif -+#if defined(MV_INCLUDE_NAND) -+MV_U32 mvCtrlNandSupport(MV_VOID); -+#endif -+#if defined(MV_INCLUDE_SDIO) -+MV_U32 mvCtrlSdioSupport(MV_VOID); -+#endif -+#if defined(MV_INCLUDE_TS) -+MV_U32 mvCtrlTsSupport(MV_VOID); -+#endif -+#if defined(MV_INCLUDE_AUDIO) -+MV_U32 mvCtrlAudioSupport(MV_VOID); -+#endif -+#if defined(MV_INCLUDE_TDM) -+MV_U32 mvCtrlTdmSupport(MV_VOID); -+#endif -+ -+MV_U16 mvCtrlModelGet(MV_VOID); -+MV_U8 mvCtrlRevGet(MV_VOID); -+MV_STATUS mvCtrlNameGet(char *pNameBuff); -+MV_U32 mvCtrlModelRevGet(MV_VOID); -+MV_STATUS mvCtrlModelRevNameGet(char *pNameBuff); -+MV_VOID mvCtrlAddrDecShow(MV_VOID); -+const MV_8* mvCtrlTargetNameGet(MV_TARGET target); -+MV_U32 ctrlSizeToReg(MV_U32 size, MV_U32 alignment); -+MV_U32 ctrlRegToSize(MV_U32 regSize, MV_U32 alignment); -+MV_U32 ctrlSizeRegRoundUp(MV_U32 size, MV_U32 alignment); -+MV_U32 mvCtrlSysRstLengthCounterGet(MV_VOID); -+MV_STATUS ctrlWinOverlapTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2); -+MV_STATUS ctrlWinWithinWinTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2); -+ -+MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable); -+MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index); -+MV_VOID mvCtrlPwrMemSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable); -+MV_BOOL mvCtrlIsBootFromSPI(MV_VOID); -+MV_BOOL mvCtrlIsBootFromSPIUseNAND(MV_VOID); -+MV_BOOL mvCtrlIsBootFromNAND(MV_VOID); -+#if defined(MV_INCLUDE_CLK_PWR_CNTRL) -+MV_VOID mvCtrlPwrSaveOn(MV_VOID); -+MV_VOID mvCtrlPwrSaveOff(MV_VOID); -+#endif -+MV_BOOL mvCtrlPwrMemGet(MV_UNIT_ID unitId, MV_U32 index); -+MV_VOID mvMPPConfigToSPI(MV_VOID); -+MV_VOID mvMPPConfigToDefault(MV_VOID); -+ -+ -+#endif /* __INCmvCtrlEnvLibh */ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,419 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvCtrlEnvRegsh -+#define __INCmvCtrlEnvRegsh -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* CV Support */ -+#define PEX0_MEM0 PEX0_MEM -+#define PCI0_MEM0 PEX0_MEM -+ -+/* Controller revision info */ -+#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 -+#define PCCRIR_REVID_OFFS 0 /* Revision ID */ -+#define PCCRIR_REVID_MASK (0xff << PCCRIR_REVID_OFFS) -+ -+/* Controler environment registers offsets */ -+ -+/* Power Managment Control */ -+#define POWER_MNG_MEM_CTRL_REG 0x20118 -+ -+#define PMC_GESTOPMEM_OFFS(port) ((port)? 13 : 0) -+#define PMC_GESTOPMEM_MASK(port) (1 << PMC_GESTOPMEM_OFFS(port)) -+#define PMC_GESTOPMEM_EN(port) (0 << PMC_GESTOPMEM_OFFS(port)) -+#define PMC_GESTOPMEM_STOP(port) (1 << PMC_GESTOPMEM_OFFS(port)) -+ -+#define PMC_PEXSTOPMEM_OFFS 1 -+#define PMC_PEXSTOPMEM_MASK (1 << PMC_PEXSTOPMEM_OFFS) -+#define PMC_PEXSTOPMEM_EN (0 << PMC_PEXSTOPMEM_OFFS) -+#define PMC_PEXSTOPMEM_STOP (1 << PMC_PEXSTOPMEM_OFFS) -+ -+#define PMC_USBSTOPMEM_OFFS 2 -+#define PMC_USBSTOPMEM_MASK (1 << PMC_USBSTOPMEM_OFFS) -+#define PMC_USBSTOPMEM_EN (0 << PMC_USBSTOPMEM_OFFS) -+#define PMC_USBSTOPMEM_STOP (1 << PMC_USBSTOPMEM_OFFS) -+ -+#define PMC_DUNITSTOPMEM_OFFS 3 -+#define PMC_DUNITSTOPMEM_MASK (1 << PMC_DUNITSTOPMEM_OFFS) -+#define PMC_DUNITSTOPMEM_EN (0 << PMC_DUNITSTOPMEM_OFFS) -+#define PMC_DUNITSTOPMEM_STOP (1 << PMC_DUNITSTOPMEM_OFFS) -+ -+#define PMC_RUNITSTOPMEM_OFFS 4 -+#define PMC_RUNITSTOPMEM_MASK (1 << PMC_RUNITSTOPMEM_OFFS) -+#define PMC_RUNITSTOPMEM_EN (0 << PMC_RUNITSTOPMEM_OFFS) -+#define PMC_RUNITSTOPMEM_STOP (1 << PMC_RUNITSTOPMEM_OFFS) -+ -+#define PMC_XORSTOPMEM_OFFS(port) (5+(port*2)) -+#define PMC_XORSTOPMEM_MASK(port) (1 << PMC_XORSTOPMEM_OFFS(port)) -+#define PMC_XORSTOPMEM_EN(port) (0 << PMC_XORSTOPMEM_OFFS(port)) -+#define PMC_XORSTOPMEM_STOP(port) (1 << PMC_XORSTOPMEM_OFFS(port)) -+ -+#define PMC_SATASTOPMEM_OFFS(port) (6+(port*5)) -+#define PMC_SATASTOPMEM_MASK(port) (1 << PMC_SATASTOPMEM_OFFS(port)) -+#define PMC_SATASTOPMEM_EN(port) (0 << PMC_SATASTOPMEM_OFFS(port)) -+#define PMC_SATASTOPMEM_STOP(port) (1 << PMC_SATASTOPMEM_OFFS(port)) -+ -+#define PMC_SESTOPMEM_OFFS 8 -+#define PMC_SESTOPMEM_MASK (1 << PMC_SESTOPMEM_OFFS) -+#define PMC_SESTOPMEM_EN (0 << PMC_SESTOPMEM_OFFS) -+#define PMC_SESTOPMEM_STOP (1 << PMC_SESTOPMEM_OFFS) -+ -+#define PMC_AUDIOSTOPMEM_OFFS 9 -+#define PMC_AUDIOSTOPMEM_MASK (1 << PMC_AUDIOSTOPMEM_OFFS) -+#define PMC_AUDIOSTOPMEM_EN (0 << PMC_AUDIOSTOPMEM_OFFS) -+#define PMC_AUDIOSTOPMEM_STOP (1 << PMC_AUDIOSTOPMEM_OFFS) -+ -+#define POWER_MNG_CTRL_REG 0x2011C -+ -+#define PMC_GESTOPCLOCK_OFFS(port) ((port)? 19 : 0) -+#define PMC_GESTOPCLOCK_MASK(port) (1 << PMC_GESTOPCLOCK_OFFS(port)) -+#define PMC_GESTOPCLOCK_EN(port) (1 << PMC_GESTOPCLOCK_OFFS(port)) -+#define PMC_GESTOPCLOCK_STOP(port) (0 << PMC_GESTOPCLOCK_OFFS(port)) -+ -+#define PMC_PEXPHYSTOPCLOCK_OFFS 1 -+#define PMC_PEXPHYSTOPCLOCK_MASK (1 << PMC_PEXPHYSTOPCLOCK_OFFS) -+#define PMC_PEXPHYSTOPCLOCK_EN (1 << PMC_PEXPHYSTOPCLOCK_OFFS) -+#define PMC_PEXPHYSTOPCLOCK_STOP (0 << PMC_PEXPHYSTOPCLOCK_OFFS) -+ -+#define PMC_PEXSTOPCLOCK_OFFS 2 -+#define PMC_PEXSTOPCLOCK_MASK (1 << PMC_PEXSTOPCLOCK_OFFS) -+#define PMC_PEXSTOPCLOCK_EN (1 << PMC_PEXSTOPCLOCK_OFFS) -+#define PMC_PEXSTOPCLOCK_STOP (0 << PMC_PEXSTOPCLOCK_OFFS) -+ -+#define PMC_USBSTOPCLOCK_OFFS 3 -+#define PMC_USBSTOPCLOCK_MASK (1 << PMC_USBSTOPCLOCK_OFFS) -+#define PMC_USBSTOPCLOCK_EN (1 << PMC_USBSTOPCLOCK_OFFS) -+#define PMC_USBSTOPCLOCK_STOP (0 << PMC_USBSTOPCLOCK_OFFS) -+ -+#define PMC_SDIOSTOPCLOCK_OFFS 4 -+#define PMC_SDIOSTOPCLOCK_MASK (1 << PMC_SDIOSTOPCLOCK_OFFS) -+#define PMC_SDIOSTOPCLOCK_EN (1 << PMC_SDIOSTOPCLOCK_OFFS) -+#define PMC_SDIOSTOPCLOCK_STOP (0 << PMC_SDIOSTOPCLOCK_OFFS) -+ -+#define PMC_TSSTOPCLOCK_OFFS 5 -+#define PMC_TSSTOPCLOCK_MASK (1 << PMC_TSSTOPCLOCK_OFFS) -+#define PMC_TSSTOPCLOCK_EN (1 << PMC_TSSTOPCLOCK_OFFS) -+#define PMC_TSSTOPCLOCK_STOP (0 << PMC_TSSTOPCLOCK_OFFS) -+ -+#define PMC_AUDIOSTOPCLOCK_OFFS 9 -+#define PMC_AUDIOSTOPCLOCK_MASK (1 << PMC_AUDIOSTOPCLOCK_OFFS) -+#define PMC_AUDIOSTOPCLOCK_EN (1 << PMC_AUDIOSTOPCLOCK_OFFS) -+#define PMC_AUDIOSTOPCLOCK_STOP (0 << PMC_AUDIOSTOPCLOCK_OFFS) -+ -+#define PMC_POWERSAVE_OFFS 11 -+#define PMC_POWERSAVE_MASK (1 << PMC_POWERSAVE_OFFS) -+#define PMC_POWERSAVE_EN (1 << PMC_POWERSAVE_OFFS) -+#define PMC_POWERSAVE_STOP (0 << PMC_POWERSAVE_OFFS) -+ -+ -+ -+ -+#define PMC_SATASTOPCLOCK_OFFS(port) (14+(port)) -+#define PMC_SATASTOPCLOCK_MASK(port) (1 << PMC_SATASTOPCLOCK_OFFS(port)) -+#define PMC_SATASTOPCLOCK_EN(port) (1 << PMC_SATASTOPCLOCK_OFFS(port)) -+#define PMC_SATASTOPCLOCK_STOP(port) (0 << PMC_SATASTOPCLOCK_OFFS(port)) -+ -+#define PMC_SESTOPCLOCK_OFFS 17 -+#define PMC_SESTOPCLOCK_MASK (1 << PMC_SESTOPCLOCK_OFFS) -+#define PMC_SESTOPCLOCK_EN (1 << PMC_SESTOPCLOCK_OFFS) -+#define PMC_SESTOPCLOCK_STOP (0 << PMC_SESTOPCLOCK_OFFS) -+ -+#define PMC_TDMSTOPCLOCK_OFFS 20 -+#define PMC_TDMSTOPCLOCK_MASK (1 << PMC_TDMSTOPCLOCK_OFFS) -+#define PMC_TDMSTOPCLOCK_EN (1 << PMC_TDMSTOPCLOCK_OFFS) -+#define PMC_TDMSTOPCLOCK_STOP (0 << PMC_TDMSTOPCLOCK_OFFS) -+ -+ -+/* Controler environment registers offsets */ -+#define MPP_CONTROL_REG0 0x10000 -+#define MPP_CONTROL_REG1 0x10004 -+#define MPP_CONTROL_REG2 0x10008 -+#define MPP_CONTROL_REG3 0x1000C -+#define MPP_CONTROL_REG4 0x10010 -+#define MPP_CONTROL_REG5 0x10014 -+#define MPP_CONTROL_REG6 0x10018 -+#define MPP_SAMPLE_AT_RESET 0x10030 -+#define CHIP_BOND_REG 0x10034 -+#define SYSRST_LENGTH_COUNTER_REG 0x10050 -+#define SLCR_COUNT_OFFS 0 -+#define SLCR_COUNT_MASK (0x1FFFFFFF << SLCR_COUNT_OFFS) -+#define SLCR_CLR_OFFS 31 -+#define SLCR_CLR_MASK (1 << SLCR_CLR_OFFS) -+#define PCKG_OPT_MASK 0x3 -+#define MPP_OUTPUT_DRIVE_REG 0x100E0 -+#define MPP_RGMII0_OUTPUT_DRIVE_OFFS 7 -+#define MPP_3_3_RGMII0_OUTPUT_DRIVE (0x0 << MPP_RGMII0_OUTPUT_DRIVE_OFFS) -+#define MPP_1_8_RGMII0_OUTPUT_DRIVE (0x1 << MPP_RGMII0_OUTPUT_DRIVE_OFFS) -+#define MPP_RGMII1_OUTPUT_DRIVE_OFFS 15 -+#define MPP_3_3_RGMII1_OUTPUT_DRIVE (0x0 << MPP_RGMII1_OUTPUT_DRIVE_OFFS) -+#define MPP_1_8_RGMII1_OUTPUT_DRIVE (0x1 << MPP_RGMII1_OUTPUT_DRIVE_OFFS) -+ -+#define MSAR_BOOT_MODE_OFFS 12 -+#define MSAR_BOOT_MODE_MASK (0x7 << MSAR_BOOT_MODE_OFFS) -+#define MSAR_BOOT_NAND_WITH_BOOTROM (0x5 << MSAR_BOOT_MODE_OFFS) -+#define MSAR_BOOT_SPI_WITH_BOOTROM (0x4 << MSAR_BOOT_MODE_OFFS) -+#define MSAR_BOOT_SPI_USE_NAND_WITH_BOOTROM (0x2 << MSAR_BOOT_MODE_OFFS) -+ -+#define MSAR_BOOT_MODE_6180(X) (((X & 0x3000) >> 12) | \ -+ ((X & 0x2) << 1)) -+#define MSAR_BOOT_SPI_WITH_BOOTROM_6180 0x1 -+#define MSAR_BOOT_NAND_WITH_BOOTROM_6180 0x5 -+ -+#define MSAR_TCLCK_OFFS 21 -+#define MSAR_TCLCK_MASK (0x1 << MSAR_TCLCK_OFFS) -+#define MSAR_TCLCK_166 (0x1 << MSAR_TCLCK_OFFS) -+#define MSAR_TCLCK_200 (0x0 << MSAR_TCLCK_OFFS) -+ -+ -+#define MSAR_CPUCLCK_EXTRACT(X) (((X & 0x2) >> 1) | ((X & 0x400000) >> 21) | \ -+ ((X & 0x18) >> 1)) -+ -+#define MSAR_CPUCLCK_OFFS_6180 2 -+#define MSAR_CPUCLCK_MASK_6180 (0x7 << MSAR_CPUCLCK_OFFS_6180) -+ -+#define MSAR_DDRCLCK_RTIO_OFFS 5 -+#define MSAR_DDRCLCK_RTIO_MASK (0xF << MSAR_DDRCLCK_RTIO_OFFS) -+ -+#define MSAR_L2CLCK_EXTRACT(X) (((X & 0x600) >> 9) | ((X & 0x80000) >> 17)) -+ -+#ifndef MV_ASMLANGUAGE -+/* CPU clock for 6281,6192 0->Resereved */ -+#define MV_CPU_CLCK_TBL { 0, 0, 0, 0, \ -+ 600000000, 0, 800000000, 1000000000, \ -+ 0, 1200000000, 0, 0, \ -+ 1500000000, 0, 0, 0} -+ -+/* DDR clock RATIO for 6281,6192 {0,0}->Reserved */ -+#define MV_DDR_CLCK_RTIO_TBL {\ -+ {0, 0}, {0, 0}, {2, 1}, {0, 0}, \ -+ {3, 1}, {0, 0}, {4, 1}, {9, 2}, \ -+ {5, 1}, {6, 1}, {0, 0}, {0, 0}, \ -+ {0, 0}, {0, 0}, {0, 0}, {0, 0} \ -+} -+ -+/* L2 clock RATIO for 6281,6192 {1,1}->Reserved */ -+#define MV_L2_CLCK_RTIO_TBL {\ -+ {0, 0}, {2, 1}, {0, 0}, {3, 1}, \ -+ {0, 0}, {0, 0}, {0, 0}, {0, 0} \ -+} -+ -+/* 6180 have different clk reset sampling */ -+/* ARM CPU, DDR, L2 clock for 6180 {0,0,0}->Reserved */ -+#define MV_CPU6180_DDR_L2_CLCK_TBL { \ -+ {0, 0, 0 },\ -+ {0, 0, 0 },\ -+ {0, 0, 0 },\ -+ {0, 0, 0 },\ -+ {0, 0, 0 },\ -+ {600000000, 200000000, 300000000 },\ -+ {800000000, 200000000, 400000000 },\ -+ {0, 0, 0 }\ -+} -+ -+ -+ -+/* These macros help units to identify a target Mbus Arbiter group */ -+#define MV_TARGET_IS_DRAM(target) \ -+ ((target >= SDRAM_CS0) && (target <= SDRAM_CS3)) -+ -+#define MV_TARGET_IS_PEX0(target) \ -+ ((target >= PEX0_MEM) && (target <= PEX0_IO)) -+ -+#define MV_TARGET_IS_PEX1(target) 0 -+ -+#define MV_TARGET_IS_PEX(target) (MV_TARGET_IS_PEX0(target) || MV_TARGET_IS_PEX1(target)) -+ -+#define MV_TARGET_IS_DEVICE(target) \ -+ ((target >= DEVICE_CS0) && (target <= DEVICE_CS3)) -+ -+#define MV_PCI_DRAM_BAR_TO_DRAM_TARGET(bar) 0 -+ -+#define MV_TARGET_IS_AS_BOOT(target) ((target) == (sampleAtResetTargetArray[ \ -+ (mvCtrlModelGet() == MV_6180_DEV_ID)? MSAR_BOOT_MODE_6180 \ -+ (MV_REG_READ(MPP_SAMPLE_AT_RESET)):((MV_REG_READ(MPP_SAMPLE_AT_RESET)\ -+ & MSAR_BOOT_MODE_MASK) >> MSAR_BOOT_MODE_OFFS)])) -+ -+ -+#define MV_CHANGE_BOOT_CS(target) (((target) == DEV_BOOCS)?\ -+ sampleAtResetTargetArray[(mvCtrlModelGet() == MV_6180_DEV_ID)? \ -+ MSAR_BOOT_MODE_6180(MV_REG_READ(MPP_SAMPLE_AT_RESET)): \ -+ ((MV_REG_READ(MPP_SAMPLE_AT_RESET) & MSAR_BOOT_MODE_MASK)\ -+ >> MSAR_BOOT_MODE_OFFS)]:(target)) -+ -+#define TCLK_TO_COUNTER_RATIO 1 /* counters running in Tclk */ -+ -+#define BOOT_TARGETS_NAME_ARRAY { \ -+ TBL_TERM, \ -+ TBL_TERM, \ -+ BOOT_ROM_CS, \ -+ TBL_TERM, \ -+ BOOT_ROM_CS, \ -+ BOOT_ROM_CS, \ -+ TBL_TERM, \ -+ TBL_TERM \ -+} -+ -+#define BOOT_TARGETS_NAME_ARRAY_6180 { \ -+ TBL_TERM, \ -+ BOOT_ROM_CS, \ -+ TBL_TERM, \ -+ TBL_TERM, \ -+ TBL_TERM, \ -+ BOOT_ROM_CS, \ -+ TBL_TERM, \ -+ TBL_TERM \ -+} -+ -+ -+/* For old competability */ -+#define DEVICE_CS0 NFLASH_CS -+#define DEVICE_CS1 SPI_CS -+#define DEVICE_CS2 BOOT_ROM_CS -+#define DEVICE_CS3 DEV_BOOCS -+#define MV_BOOTDEVICE_INDEX 0 -+ -+#define START_DEV_CS DEV_CS0 -+#define DEV_TO_TARGET(dev) ((dev) + DEVICE_CS0) -+ -+#define PCI_IF0_MEM0 PEX0_MEM -+#define PCI_IF0_IO PEX0_IO -+ -+ -+/* This enumerator defines the Marvell controller target ID */ -+typedef enum _mvTargetId -+{ -+ DRAM_TARGET_ID = 0 , /* Port 0 -> DRAM interface */ -+ DEV_TARGET_ID = 1, /* Port 1 -> Nand/SPI */ -+ PEX0_TARGET_ID = 4 , /* Port 4 -> PCI Express0 */ -+ CRYPT_TARGET_ID = 3 , /* Port 3 --> Crypto Engine */ -+ SAGE_TARGET_ID = 12 , /* Port 12 -> SAGE Unit */ -+ MAX_TARGETS_ID -+}MV_TARGET_ID; -+ -+ -+/* This enumerator described the possible Controller paripheral targets. */ -+/* Controller peripherals are designated memory/IO address spaces that the */ -+/* controller can access. They are also refered as "targets" */ -+typedef enum _mvTarget -+{ -+ TBL_TERM = -1, /* none valid target, used as targets list terminator*/ -+ SDRAM_CS0, /* SDRAM chip select 0 */ -+ SDRAM_CS1, /* SDRAM chip select 1 */ -+ SDRAM_CS2, /* SDRAM chip select 2 */ -+ SDRAM_CS3, /* SDRAM chip select 3 */ -+ PEX0_MEM, /* PCI Express 0 Memory */ -+ PEX0_IO, /* PCI Express 0 IO */ -+ INTER_REGS, /* Internal registers */ -+ NFLASH_CS, /* NFLASH_CS */ -+ SPI_CS, /* SPI_CS */ -+ BOOT_ROM_CS, /* BOOT_ROM_CS */ -+ DEV_BOOCS, /* DEV_BOOCS */ -+ CRYPT_ENG, /* Crypto Engine */ -+#ifdef MV_INCLUDE_SAGE -+ SAGE_UNIT, /* SAGE Unit */ -+#endif -+ MAX_TARGETS -+ -+}MV_TARGET; -+ -+#define TARGETS_DEF_ARRAY { \ -+ {0x0E, DRAM_TARGET_ID }, /* SDRAM_CS0 */ \ -+ {0x0D, DRAM_TARGET_ID }, /* SDRAM_CS1 */ \ -+ {0x0B, DRAM_TARGET_ID }, /* SDRAM_CS0 */ \ -+ {0x07, DRAM_TARGET_ID }, /* SDRAM_CS1 */ \ -+ {0xE8, PEX0_TARGET_ID }, /* PEX0_MEM */ \ -+ {0xE0, PEX0_TARGET_ID }, /* PEX0_IO */ \ -+ {0xFF, 0xFF }, /* INTER_REGS */ \ -+ {0x2F, DEV_TARGET_ID }, /* NFLASH_CS */ \ -+ {0x1E, DEV_TARGET_ID }, /* SPI_CS */ \ -+ {0x1D, DEV_TARGET_ID }, /* BOOT_ROM_CS */ \ -+ {0x1E, DEV_TARGET_ID }, /* DEV_BOOCS */ \ -+ {0x01, CRYPT_TARGET_ID}, /* CRYPT_ENG */ \ -+ {0x00, SAGE_TARGET_ID } \ -+} -+ -+ -+#define TARGETS_NAME_ARRAY { \ -+ "SDRAM_CS0", /* SDRAM_CS0 */ \ -+ "SDRAM_CS1", /* SDRAM_CS1 */ \ -+ "SDRAM_CS2", /* SDRAM_CS2 */ \ -+ "SDRAM_CS3", /* SDRAM_CS3 */ \ -+ "PEX0_MEM", /* PEX0_MEM */ \ -+ "PEX0_IO", /* PEX0_IO */ \ -+ "INTER_REGS", /* INTER_REGS */ \ -+ "NFLASH_CS", /* NFLASH_CS */ \ -+ "SPI_CS", /* SPI_CS */ \ -+ "BOOT_ROM_CS", /* BOOT_ROM_CS */ \ -+ "DEV_BOOTCS", /* DEV_BOOCS */ \ -+ "CRYPT_ENG", /* CRYPT_ENG */ \ -+ "SAGE_UNIT" /* SAGE_UNIT */ \ -+} -+#endif /* MV_ASMLANGUAGE */ -+ -+ -+#endif -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,257 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvCtrlEnvSpech -+#define __INCmvCtrlEnvSpech -+ -+#include "mvDeviceId.h" -+#include "mvSysHwConfig.h" -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+#define MV_ARM_SOC -+#define SOC_NAME_PREFIX "MV88F" -+ -+ -+/* units base and port numbers */ -+#ifdef MV_ASMLANGUAGE -+#define XOR_UNIT_BASE(unit) 0x60800 -+#else -+#define MV_XOR_REG_BASE 0x60000 -+#define XOR_UNIT_BASE(unit) ((unit)? 0x60900:0x60800) -+#endif -+ -+#define TDM_REG_BASE 0xD0000 -+#define USB_REG_BASE(dev) 0x50000 -+#define AUDIO_REG_BASE 0xA0000 -+#define SATA_REG_BASE 0x80000 -+#define MV_CESA_REG_BASE 0x3D000 -+#define MV_CESA_TDMA_REG_BASE 0x30000 -+#define MV_SDIO_REG_BASE 0x90000 -+#define MV_ETH_REG_BASE(port) (((port) == 0) ? 0x72000 : 0x76000) -+#define MV_UART_CHAN_BASE(chanNum) (0x12000 + (chanNum * 0x100)) -+#define DRAM_BASE 0x0 -+#define CNTMR_BASE 0x20300 -+#define TWSI_SLAVE_BASE(chanNum) 0x11000 -+#define PEX_IF_BASE(pexIf) 0x40000 -+#define MPP_REG_BASE 0x10000 -+#define TSU_GLOBAL_REG_BASE 0xB4000 -+#define MAX_AHB_TO_MBUS_REG_BASE 0x20000 -+ -+#define INTER_REGS_SIZE _1M -+/* This define describes the TWSI interrupt bit and location */ -+#define TWSI_CPU_MAIN_INT_CAUSE_REG 0x20200 -+#define TWSI0_CPU_MAIN_INT_BIT (1<<29) -+#define TWSI_SPEED 100000 -+ -+#define MV_GPP_MAX_GROUP 2 -+#define MV_CNTMR_MAX_COUNTER 2 -+#define MV_UART_MAX_CHAN 2 -+#define MV_XOR_MAX_UNIT 2 -+#define MV_XOR_MAX_CHAN 4 /* total channels for all units together*/ -+#define MV_XOR_MAX_CHAN_PER_UNIT 2 /* channels for units */ -+#define MV_SATA_MAX_CHAN 2 -+ -+#define MV_6281_MPP_MAX_MODULE 2 -+#define MV_6192_MPP_MAX_MODULE 1 -+#define MV_6190_MPP_MAX_MODULE 1 -+#define MV_6180_MPP_MAX_MODULE 2 -+#define MV_6281_MPP_MAX_GROUP 7 -+#define MV_6192_MPP_MAX_GROUP 4 -+#define MV_6190_MPP_MAX_GROUP 4 -+#define MV_6180_MPP_MAX_GROUP 3 -+ -+#define MV_DRAM_MAX_CS 4 -+ -+/* This define describes the maximum number of supported PCI\PCIX Interfaces*/ -+#define MV_PCI_MAX_IF 0 -+#define MV_PCI_START_IF 0 -+ -+/* This define describes the maximum number of supported PEX Interfaces */ -+#define MV_INCLUDE_PEX0 -+#define MV_DISABLE_PEX_DEVICE_BAR -+#define MV_PEX_MAX_IF 1 -+#define MV_PEX_START_IF MV_PCI_MAX_IF -+ -+/* This define describes the maximum number of supported PCI Interfaces */ -+#define MV_PCI_IF_MAX_IF (MV_PEX_MAX_IF+MV_PCI_MAX_IF) -+ -+#define MV_ETH_MAX_PORTS 2 -+#define MV_6281_ETH_MAX_PORTS 2 -+#define MV_6192_ETH_MAX_PORTS 2 -+#define MV_6190_ETH_MAX_PORTS 1 -+#define MV_6180_ETH_MAX_PORTS 1 -+ -+#define MV_IDMA_MAX_CHAN 0 -+ -+#define MV_USB_MAX_PORTS 1 -+ -+#define MV_USB_VERSION 1 -+ -+ -+#define MV_6281_NAND 1 -+#define MV_6192_NAND 1 -+#define MV_6190_NAND 1 -+#define MV_6180_NAND 0 -+ -+#define MV_6281_SDIO 1 -+#define MV_6192_SDIO 1 -+#define MV_6190_SDIO 1 -+#define MV_6180_SDIO 1 -+ -+#define MV_6281_TS 1 -+#define MV_6192_TS 1 -+#define MV_6190_TS 0 -+#define MV_6180_TS 0 -+ -+#define MV_6281_AUDIO 1 -+#define MV_6192_AUDIO 1 -+#define MV_6190_AUDIO 0 -+#define MV_6180_AUDIO 1 -+ -+#define MV_6281_TDM 1 -+#define MV_6192_TDM 1 -+#define MV_6190_TDM 0 -+#define MV_6180_TDM 0 -+ -+#define MV_DEVICE_MAX_CS 4 -+ -+/* Others */ -+#define PEX_HOST_BUS_NUM(pciIf) (pciIf) -+#define PEX_HOST_DEV_NUM(pciIf) 0 -+ -+#define PCI_IO(pciIf) (PEX0_IO) -+#define PCI_MEM(pciIf, memNum) (PEX0_MEM0) -+/* CESA version #2: One channel, 2KB SRAM, TDMA */ -+#if defined(MV_CESA_CHAIN_MODE_SUPPORT) -+ #define MV_CESA_VERSION 3 -+#else -+#define MV_CESA_VERSION 2 -+#endif -+#define MV_CESA_SRAM_SIZE 2*1024 -+/* This define describes the maximum number of supported Ethernet ports */ -+#define MV_ETH_VERSION 4 -+#define MV_ETH_MAX_RXQ 8 -+#define MV_ETH_MAX_TXQ 8 -+#define MV_ETH_PORT_SGMII { MV_FALSE, MV_FALSE } -+/* This define describes the the support of USB */ -+#define MV_USB_VERSION 1 -+ -+#define MV_INCLUDE_SDRAM_CS0 -+#define MV_INCLUDE_SDRAM_CS1 -+#define MV_INCLUDE_SDRAM_CS2 -+#define MV_INCLUDE_SDRAM_CS3 -+ -+#define MV_INCLUDE_DEVICE_CS0 -+#define MV_INCLUDE_DEVICE_CS1 -+#define MV_INCLUDE_DEVICE_CS2 -+#define MV_INCLUDE_DEVICE_CS3 -+ -+#define MPP_GROUP_1_TYPE {\ -+ {0, 0, 0}, /* Reserved for AUTO */ \ -+ {0x22220000, 0x22222222, 0x2222}, /* TDM */ \ -+ {0x44440000, 0x00044444, 0x0000}, /* AUDIO */ \ -+ {0x33330000, 0x33003333, 0x0033}, /* RGMII */ \ -+ {0x33330000, 0x03333333, 0x0033}, /* GMII */ \ -+ {0x11110000, 0x11111111, 0x0001}, /* TS */ \ -+ {0x33330000, 0x33333333, 0x3333} /* MII */ \ -+} -+ -+#define MPP_GROUP_2_TYPE {\ -+ {0, 0, 0}, /* Reserved for AUTO */ \ -+ {0x22220000, 0x22222222, 0x22}, /* TDM */ \ -+ {0x44440000, 0x00044444, 0x0}, /* AUDIO */ \ -+ {0, 0, 0}, /* N_A */ \ -+ {0, 0, 0}, /* N_A */ \ -+ {0x11110000, 0x11111111, 0x01} /* TS */ \ -+} -+ -+#ifndef MV_ASMLANGUAGE -+ -+/* This enumerator defines the Marvell Units ID */ -+typedef enum _mvUnitId -+{ -+ DRAM_UNIT_ID, -+ PEX_UNIT_ID, -+ ETH_GIG_UNIT_ID, -+ USB_UNIT_ID, -+ IDMA_UNIT_ID, -+ XOR_UNIT_ID, -+ SATA_UNIT_ID, -+ TDM_UNIT_ID, -+ UART_UNIT_ID, -+ CESA_UNIT_ID, -+ SPI_UNIT_ID, -+ AUDIO_UNIT_ID, -+ SDIO_UNIT_ID, -+ TS_UNIT_ID, -+ MAX_UNITS_ID -+ -+}MV_UNIT_ID; -+ -+#endif -+ -+#endif /* __INCmvCtrlEnvSpech */ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,1048 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+/* includes */ -+#include "ctrlEnv/sys/mvAhbToMbus.h" -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+ -+#undef MV_DEBUG -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+/* typedefs */ -+ -+ -+/* CPU address remap registers offsets are inconsecutive. This struct */ -+/* describes address remap register offsets */ -+typedef struct _ahbToMbusRemapRegOffs -+{ -+ MV_U32 lowRegOffs; /* Low 32-bit remap register offset */ -+ MV_U32 highRegOffs; /* High 32 bit remap register offset */ -+}AHB_TO_MBUS_REMAP_REG_OFFS; -+ -+/* locals */ -+static MV_STATUS ahbToMbusRemapRegOffsGet (MV_U32 winNum, -+ AHB_TO_MBUS_REMAP_REG_OFFS *pRemapRegs); -+ -+/******************************************************************************* -+* mvAhbToMbusInit - Initialize Ahb To Mbus Address Map ! -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK laways. -+* -+*******************************************************************************/ -+MV_STATUS mvAhbToMbusInit(void) -+{ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvAhbToMbusWinSet - Set CPU-to-peripheral winNum address window -+* -+* DESCRIPTION: -+* This function sets -+* address window, also known as address decode window. -+* A new address decode window is set for specified winNum address window. -+* If address decode window parameter structure enables the window, -+* the routine will also enable the winNum window, allowing CPU to access -+* the winNum window. -+* -+* INPUT: -+* winNum - Windows number. -+* pAddrDecWin - CPU winNum window data structure. -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_OK if CPU winNum window was set correctly, MV_ERROR in case of -+* address window overlapps with other active CPU winNum window or -+* trying to assign 36bit base address while CPU does not support that. -+* The function returns MV_NOT_SUPPORTED, if the winNum is unsupported. -+* -+*******************************************************************************/ -+MV_STATUS mvAhbToMbusWinSet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin) -+{ -+ MV_TARGET_ATTRIB targetAttribs; -+ MV_DEC_REGS decRegs; -+ -+ /* Parameter checking */ -+ if (winNum >= MAX_AHB_TO_MBUS_WINS) -+ { -+ mvOsPrintf("mvAhbToMbusWinSet: ERR. Invalid winNum %d\n", winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ -+ /* read base register*/ -+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum)); -+ } -+ else -+ { -+ decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_INTEREG_REG); -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvAhbToMbusWinSet:Error setting AHB to MBUS window %d to "\ -+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, -+ mvCtrlTargetNameGet(pAddrDecWin->target), -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ /* read control register*/ -+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ decRegs.sizeReg = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum)); -+ } -+ -+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) -+ { -+ mvOsPrintf("mvAhbToMbusWinSet:mvCtrlAddrDecToReg Failed\n"); -+ return MV_ERROR; -+ } -+ -+ /* enable\Disable */ -+ if (MV_TRUE == pAddrDecWin->enable) -+ { -+ decRegs.sizeReg |= ATMWCR_WIN_ENABLE; -+ } -+ else -+ { -+ decRegs.sizeReg &= ~ATMWCR_WIN_ENABLE; -+ } -+ -+ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); -+ -+ /* set attributes */ -+ decRegs.sizeReg &= ~ATMWCR_WIN_ATTR_MASK; -+ decRegs.sizeReg |= targetAttribs.attrib << ATMWCR_WIN_ATTR_OFFS; -+ /* set target ID */ -+ decRegs.sizeReg &= ~ATMWCR_WIN_TARGET_MASK; -+ decRegs.sizeReg |= targetAttribs.targetId << ATMWCR_WIN_TARGET_OFFS; -+ -+#if !defined(MV_RUN_FROM_FLASH) -+ /* To be on the safe side we disable the window before writing the */ -+ /* new values. */ -+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ mvAhbToMbusWinEnable(winNum,MV_FALSE); -+ } -+#endif -+ -+ /* 3) Write to address decode Base Address Register */ -+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum), decRegs.baseReg); -+ } -+ else -+ { -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_INTEREG_REG, decRegs.baseReg); -+ } -+ -+ -+ /* Internal register space have no size */ -+ /* register. Do not perform size register assigment for those targets */ -+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ /* Write to address decode Size Register */ -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), decRegs.sizeReg); -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvAhbToMbusWinGet - Get CPU-to-peripheral winNum address window -+* -+* DESCRIPTION: -+* Get the CPU peripheral winNum address window. -+* -+* INPUT: -+* winNum - Peripheral winNum enumerator -+* -+* OUTPUT: -+* pAddrDecWin - CPU winNum window information data structure. -+* -+* RETURN: -+* MV_OK if winNum exist, MV_ERROR otherwise. -+* -+*******************************************************************************/ -+MV_STATUS mvAhbToMbusWinGet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin) -+{ -+ MV_DEC_REGS decRegs; -+ MV_TARGET_ATTRIB targetAttrib; -+ -+ -+ /* Parameter checking */ -+ if (winNum >= MAX_AHB_TO_MBUS_WINS) -+ { -+ mvOsPrintf("mvAhbToMbusWinGet: ERR. Invalid winNum %d\n", winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ -+ /* Internal register space size have no size register*/ -+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ decRegs.sizeReg = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum)); -+ } -+ else -+ { -+ decRegs.sizeReg = 0; -+ } -+ -+ -+ /* Read base and size */ -+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum)); -+ } -+ else -+ { -+ decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_INTEREG_REG); -+ } -+ -+ -+ -+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) -+ { -+ mvOsPrintf("mvAhbToMbusWinGet: mvCtrlRegToAddrDec Failed \n"); -+ return MV_ERROR; -+ } -+ -+ if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ pAddrDecWin->addrWin.size = INTER_REGS_SIZE; -+ pAddrDecWin->target = INTER_REGS; -+ pAddrDecWin->enable = MV_TRUE; -+ -+ return MV_OK; -+ } -+ -+ -+ if (decRegs.sizeReg & ATMWCR_WIN_ENABLE) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ -+ } -+ -+ -+ -+ if (-1 == pAddrDecWin->addrWin.size) -+ { -+ return MV_ERROR; -+ } -+ -+ /* attrib and targetId */ -+ targetAttrib.attrib = (decRegs.sizeReg & ATMWCR_WIN_ATTR_MASK) >> -+ ATMWCR_WIN_ATTR_OFFS; -+ targetAttrib.targetId = (decRegs.sizeReg & ATMWCR_WIN_TARGET_MASK) >> -+ ATMWCR_WIN_TARGET_OFFS; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvAhbToMbusWinTargetGet - Get Window number associated with target -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_U32 mvAhbToMbusWinTargetGet(MV_TARGET target) -+{ -+ MV_AHB_TO_MBUS_DEC_WIN decWin; -+ MV_U32 winNum; -+ -+ /* Check parameters */ -+ if (target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetGet: target %d is Illigal\n", target); -+ return 0xffffffff; -+ } -+ -+ if (INTER_REGS == target) -+ { -+ return MV_AHB_TO_MBUS_INTREG_WIN; -+ } -+ -+ for (winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS ; winNum++) -+ { -+ if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) -+ continue; -+ -+ if (mvAhbToMbusWinGet(winNum,&decWin) != MV_OK) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetGet: mvAhbToMbusWinGet fail\n"); -+ return 0xffffffff; -+ -+ } -+ -+ if (decWin.enable == MV_TRUE) -+ { -+ if (decWin.target == target) -+ { -+ return winNum; -+ } -+ -+ } -+ -+ } -+ -+ return 0xFFFFFFFF; -+ -+ -+} -+ -+/******************************************************************************* -+* mvAhbToMbusWinAvailGet - Get First Available window number. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_U32 mvAhbToMbusWinAvailGet(MV_VOID) -+{ -+ MV_AHB_TO_MBUS_DEC_WIN decWin; -+ MV_U32 winNum; -+ -+ for (winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS ; winNum++) -+ { -+ if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) -+ continue; -+ -+ if (mvAhbToMbusWinGet(winNum,&decWin) != MV_OK) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetGet: mvAhbToMbusWinGet fail\n"); -+ return 0xffffffff; -+ -+ } -+ -+ if (decWin.enable == MV_FALSE) -+ { -+ return winNum; -+ } -+ -+ } -+ -+ return 0xFFFFFFFF; -+} -+ -+ -+/******************************************************************************* -+* mvAhbToMbusWinEnable - Enable/disable a CPU address decode window -+* -+* DESCRIPTION: -+* This function enable/disable a CPU address decode window. -+* if parameter 'enable' == MV_TRUE the routine will enable the -+* window, thus enabling CPU accesses (before enabling the window it is -+* tested for overlapping). Otherwise, the window will be disabled. -+* -+* INPUT: -+* winNum - Peripheral winNum enumerator. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_ERROR if protection window number was wrong, or the window -+* overlapps other winNum window. -+* -+*******************************************************************************/ -+MV_STATUS mvAhbToMbusWinEnable(MV_U32 winNum, MV_BOOL enable) -+{ -+ -+ /* Parameter checking */ -+ if (winNum >= MAX_AHB_TO_MBUS_WINS) -+ { -+ mvOsPrintf("mvAhbToMbusWinEnable: ERR. Invalid winNum %d\n", winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ /* Internal registers bar can't be disable or enabled */ -+ if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ return (enable ? MV_OK : MV_ERROR); -+ } -+ -+ if (enable == MV_TRUE) -+ { -+ /* enable the window */ -+ MV_REG_BIT_SET(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ATMWCR_WIN_ENABLE); -+ } -+ else -+ { /* Disable address decode winNum window */ -+ MV_REG_BIT_RESET(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ATMWCR_WIN_ENABLE); -+ } -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvAhbToMbusWinRemap - Set CPU remap register for address windows. -+* -+* DESCRIPTION: -+* After a CPU address hits one of PCI address decode windows there is an -+* option to remap the address to a different one. For example, CPU -+* executes a read from PCI winNum window address 0x1200.0000. This -+* can be modified so the address on the PCI bus would be 0x1400.0000 -+* Using the PCI address remap mechanism. -+* -+* INPUT: -+* winNum - Peripheral winNum enumerator. Must be a PCI winNum. -+* pAddrDecWin - CPU winNum window information data structure. -+* Note that caller has to fill in the base field only. The -+* size field is ignored. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR if winNum is not a PCI one, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_U32 mvAhbToMbusWinRemap(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 baseAddr; -+ AHB_TO_MBUS_REMAP_REG_OFFS remapRegOffs; -+ -+ MV_U32 effectiveBaseAddress=0, -+ baseAddrValue=0,windowSizeValue=0; -+ -+ -+ /* Get registers offsets of given winNum */ -+ if (MV_NO_SUCH == ahbToMbusRemapRegOffsGet(winNum, &remapRegOffs)) -+ { -+ return 0xffffffff; -+ } -+ -+ /* 1) Set address remap low */ -+ baseAddr = pAddrWin->baseLow; -+ -+ /* Check base address aligment */ -+ /* -+ if (MV_IS_NOT_ALIGN(baseAddr, ATMWRLR_REMAP_LOW_ALIGNMENT)) -+ { -+ mvOsPrintf("mvAhbToMbusPciRemap: Warning. Target base 0x%x unaligned\n", -+ baseAddr); -+ return MV_ERROR; -+ } -+ */ -+ -+ /* BaseLow[31:16] => base register [31:16] */ -+ baseAddr = baseAddr & ATMWRLR_REMAP_LOW_MASK; -+ -+ MV_REG_WRITE(remapRegOffs.lowRegOffs, baseAddr); -+ -+ MV_REG_WRITE(remapRegOffs.highRegOffs, pAddrWin->baseHigh); -+ -+ -+ baseAddrValue = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum)); -+ windowSizeValue = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum)); -+ -+ baseAddrValue &= ATMWBR_BASE_MASK; -+ windowSizeValue &=ATMWCR_WIN_SIZE_MASK; -+ -+ /* Start calculating the effective Base Address */ -+ effectiveBaseAddress = baseAddrValue ; -+ -+ /* The effective base address will be combined from the chopped (if any) -+ remap value (according to the size value and remap mechanism) and the -+ window's base address */ -+ effectiveBaseAddress |= (((windowSizeValue) | 0xffff) & pAddrWin->baseLow); -+ /* If the effectiveBaseAddress exceed the window boundaries return an -+ invalid value. */ -+ -+ if (effectiveBaseAddress > (baseAddrValue + (windowSizeValue | 0xffff))) -+ { -+ mvOsPrintf("mvAhbToMbusPciRemap: Error\n"); -+ return 0xffffffff; -+ } -+ -+ return effectiveBaseAddress; -+ -+ -+} -+/******************************************************************************* -+* mvAhbToMbusWinTargetSwap - Swap AhbToMbus windows between targets -+* -+* DESCRIPTION: -+* -+* INPUT: -+* target1 - CPU Interface target 1 -+* target2 - CPU Interface target 2 -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR if targets are illigal, or if one of the targets is not -+* associated to a valid window . -+* MV_OK otherwise. -+* -+*******************************************************************************/ -+ -+ -+MV_STATUS mvAhbToMbusWinTargetSwap(MV_TARGET target1,MV_TARGET target2) -+{ -+ MV_U32 winNum1,winNum2; -+ MV_AHB_TO_MBUS_DEC_WIN winDec1,winDec2,winDecTemp; -+ AHB_TO_MBUS_REMAP_REG_OFFS remapRegs1,remapRegs2; -+ MV_U32 remapBaseLow1=0,remapBaseLow2=0; -+ MV_U32 remapBaseHigh1=0,remapBaseHigh2=0; -+ -+ -+ /* Check parameters */ -+ if (target1 >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d is Illigal\n", target1); -+ return MV_ERROR; -+ } -+ -+ if (target2 >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d is Illigal\n", target1); -+ return MV_ERROR; -+ } -+ -+ -+ /* get window associated with this target */ -+ winNum1 = mvAhbToMbusWinTargetGet(target1); -+ -+ if (winNum1 == 0xffffffff) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d has illigal win %d\n", -+ target1,winNum1); -+ return MV_ERROR; -+ -+ } -+ -+ /* get window associated with this target */ -+ winNum2 = mvAhbToMbusWinTargetGet(target2); -+ -+ if (winNum2 == 0xffffffff) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d has illigal win %d\n", -+ target2,winNum2); -+ return MV_ERROR; -+ -+ } -+ -+ /* now Get original values of both Windows */ -+ if (MV_OK != mvAhbToMbusWinGet(winNum1,&winDec1)) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetSwap: mvAhbToMbusWinGet failed win %d\n", -+ winNum1); -+ return MV_ERROR; -+ -+ } -+ if (MV_OK != mvAhbToMbusWinGet(winNum2,&winDec2)) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetSwap: mvAhbToMbusWinGet failed win %d\n", -+ winNum2); -+ return MV_ERROR; -+ -+ } -+ -+ -+ /* disable both windows */ -+ if (MV_OK != mvAhbToMbusWinEnable(winNum1,MV_FALSE)) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetSwap: failed to enable window %d\n", -+ winNum1); -+ return MV_ERROR; -+ -+ } -+ if (MV_OK != mvAhbToMbusWinEnable(winNum2,MV_FALSE)) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetSwap: failed to enable windo %d\n", -+ winNum2); -+ return MV_ERROR; -+ -+ } -+ -+ -+ /* now swap targets */ -+ -+ /* first save winDec2 values */ -+ winDecTemp.addrWin.baseHigh = winDec2.addrWin.baseHigh; -+ winDecTemp.addrWin.baseLow = winDec2.addrWin.baseLow; -+ winDecTemp.addrWin.size = winDec2.addrWin.size; -+ winDecTemp.enable = winDec2.enable; -+ winDecTemp.target = winDec2.target; -+ -+ /* winDec2 = winDec1 */ -+ winDec2.addrWin.baseHigh = winDec1.addrWin.baseHigh; -+ winDec2.addrWin.baseLow = winDec1.addrWin.baseLow; -+ winDec2.addrWin.size = winDec1.addrWin.size; -+ winDec2.enable = winDec1.enable; -+ winDec2.target = winDec1.target; -+ -+ -+ /* winDec1 = winDecTemp */ -+ winDec1.addrWin.baseHigh = winDecTemp.addrWin.baseHigh; -+ winDec1.addrWin.baseLow = winDecTemp.addrWin.baseLow; -+ winDec1.addrWin.size = winDecTemp.addrWin.size; -+ winDec1.enable = winDecTemp.enable; -+ winDec1.target = winDecTemp.target; -+ -+ -+ /* now set the new values */ -+ -+ -+ mvAhbToMbusWinSet(winNum1,&winDec1); -+ mvAhbToMbusWinSet(winNum2,&winDec2); -+ -+ -+ -+ -+ -+ /* now we will treat the remap windows if exist */ -+ -+ -+ /* now check if one or both windows has a remap window -+ as well after the swap ! */ -+ -+ /* if a window had a remap value differnt than the base value -+ before the swap , then after the swap the remap value will be -+ equal to the base value unless both windows has a remap windows*/ -+ -+ /* first get old values */ -+ if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum1,&remapRegs1)) -+ { -+ remapBaseLow1 = MV_REG_READ(remapRegs1.lowRegOffs); -+ remapBaseHigh1 = MV_REG_READ(remapRegs1.highRegOffs); -+ -+ } -+ if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2,&remapRegs2)) -+ { -+ remapBaseLow2 = MV_REG_READ(remapRegs2.lowRegOffs); -+ remapBaseHigh2 = MV_REG_READ(remapRegs2.highRegOffs); -+ -+ -+ } -+ -+ /* now do the swap */ -+ if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum1,&remapRegs1)) -+ { -+ if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2,&remapRegs2)) -+ { -+ /* Two windows has a remap !!! so swap */ -+ -+ MV_REG_WRITE(remapRegs2.highRegOffs,remapBaseHigh1); -+ MV_REG_WRITE(remapRegs2.lowRegOffs,remapBaseLow1); -+ -+ MV_REG_WRITE(remapRegs1.highRegOffs,remapBaseHigh2); -+ MV_REG_WRITE(remapRegs1.lowRegOffs,remapBaseLow2); -+ -+ -+ -+ } -+ else -+ { -+ /* remap == base */ -+ MV_REG_WRITE(remapRegs1.highRegOffs,winDec1.addrWin.baseHigh); -+ MV_REG_WRITE(remapRegs1.lowRegOffs,winDec1.addrWin.baseLow); -+ -+ } -+ -+ } -+ else if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2,&remapRegs2)) -+ { -+ /* remap == base */ -+ MV_REG_WRITE(remapRegs2.highRegOffs,winDec2.addrWin.baseHigh); -+ MV_REG_WRITE(remapRegs2.lowRegOffs,winDec2.addrWin.baseLow); -+ -+ } -+ -+ -+ -+ return MV_OK; -+ -+ -+} -+ -+ -+ -+#if defined(MV_88F1181) -+ -+/******************************************************************************* -+* mvAhbToMbusXbarCtrlSet - Set The CPU master Xbar arbitration. -+* -+* DESCRIPTION: -+* This function sets CPU Mbus Arbiter -+* -+* INPUT: -+* pPizzaArbArray - A priority Structure describing 16 "pizza slices". At -+* each clock cycle, the crossbar arbiter samples all -+* requests and gives the bus to the next agent according -+* to the "pizza". -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_ERROR if paramers to function invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvMbusArbSet(MV_MBUS_ARB_TARGET *pPizzaArbArray) -+{ -+ MV_U32 sliceNum; -+ MV_U32 xbarCtrl = 0; -+ MV_MBUS_ARB_TARGET xbarTarget; -+ -+ /* 1) Set crossbar control low register */ -+ for (sliceNum = 0; sliceNum < MRLR_SLICE_NUM; sliceNum++) -+ { -+ xbarTarget = pPizzaArbArray[sliceNum]; -+ -+ /* sliceNum parameter check */ -+ if (xbarTarget > MAX_MBUS_ARB_TARGETS) -+ { -+ mvOsPrintf("mvAhbToMbusXbarCtrlSet: ERR. Can't set Target %d\n", -+ xbarTarget); -+ return MV_ERROR; -+ } -+ xbarCtrl |= (xbarTarget << MRLR_LOW_ARB_OFFS(sliceNum)); -+ } -+ /* Write to crossbar control low register */ -+ MV_REG_WRITE(MBUS_ARBITER_LOW_REG, xbarCtrl); -+ -+ xbarCtrl = 0; -+ -+ /* 2) Set crossbar control high register */ -+ for (sliceNum = MRLR_SLICE_NUM; -+ sliceNum < MRLR_SLICE_NUM+MRHR_SLICE_NUM; -+ sliceNum++) -+ { -+ -+ xbarTarget = pPizzaArbArray[sliceNum]; -+ -+ /* sliceNum parameter check */ -+ if (xbarTarget > MAX_MBUS_ARB_TARGETS) -+ { -+ mvOsPrintf("mvAhbToMbusXbarCtrlSet: ERR. Can't set Target %d\n", -+ xbarTarget); -+ return MV_ERROR; -+ } -+ xbarCtrl |= (xbarTarget << MRHR_HIGH_ARB_OFFS(sliceNum)); -+ } -+ /* Write to crossbar control high register */ -+ MV_REG_WRITE(MBUS_ARBITER_HIGH_REG, xbarCtrl); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvMbusArbCtrlSet - Set MBus Arbiter control register -+* -+* DESCRIPTION: -+* -+* INPUT: -+* ctrl - pointer to MV_MBUS_ARB_CTRL register -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_ERROR if paramers to function invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvMbusArbCtrlSet(MV_MBUS_ARB_CTRL *ctrl) -+{ -+ -+ if (ctrl->highPrio == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(MBUS_ARBITER_CTRL_REG, MACR_ARB_ARM_TOP); -+ } -+ else -+ { -+ MV_REG_BIT_SET(MBUS_ARBITER_CTRL_REG, MACR_ARB_ARM_TOP); -+ } -+ -+ if (ctrl->fixedRoundRobin == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(MBUS_ARBITER_CTRL_REG, MACR_ARB_TARGET_FIXED); -+ } -+ else -+ { -+ MV_REG_BIT_SET(MBUS_ARBITER_CTRL_REG, MACR_ARB_TARGET_FIXED); -+ } -+ -+ if (ctrl->starvEn == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(MBUS_ARBITER_CTRL_REG, MACR_ARB_REQ_CTRL_EN); -+ } -+ else -+ { -+ MV_REG_BIT_SET(MBUS_ARBITER_CTRL_REG, MACR_ARB_REQ_CTRL_EN); -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvMbusArbCtrlGet - Get MBus Arbiter control register -+* -+* DESCRIPTION: -+* -+* INPUT: -+* ctrl - pointer to MV_MBUS_ARB_CTRL register -+* -+* OUTPUT: -+* ctrl - pointer to MV_MBUS_ARB_CTRL register -+* -+* RETURN: -+* MV_ERROR if paramers to function invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvMbusArbCtrlGet(MV_MBUS_ARB_CTRL *ctrl) -+{ -+ -+ MV_U32 ctrlReg = MV_REG_READ(MBUS_ARBITER_CTRL_REG); -+ -+ if (ctrlReg & MACR_ARB_ARM_TOP) -+ { -+ ctrl->highPrio = MV_TRUE; -+ } -+ else -+ { -+ ctrl->highPrio = MV_FALSE; -+ } -+ -+ if (ctrlReg & MACR_ARB_TARGET_FIXED) -+ { -+ ctrl->fixedRoundRobin = MV_TRUE; -+ } -+ else -+ { -+ ctrl->fixedRoundRobin = MV_FALSE; -+ } -+ -+ if (ctrlReg & MACR_ARB_REQ_CTRL_EN) -+ { -+ ctrl->starvEn = MV_TRUE; -+ } -+ else -+ { -+ ctrl->starvEn = MV_FALSE; -+ } -+ -+ -+ return MV_OK; -+} -+ -+#endif /* #if defined(MV_88F1181) */ -+ -+ -+ -+/******************************************************************************* -+* ahbToMbusRemapRegOffsGet - Get CPU address remap register offsets -+* -+* DESCRIPTION: -+* CPU to PCI address remap registers offsets are inconsecutive. -+* This function returns PCI address remap registers offsets. -+* -+* INPUT: -+* winNum - Address decode window number. See MV_U32 enumerator. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR if winNum is not a PCI one. -+* -+*******************************************************************************/ -+static MV_STATUS ahbToMbusRemapRegOffsGet(MV_U32 winNum, -+ AHB_TO_MBUS_REMAP_REG_OFFS *pRemapRegs) -+{ -+ switch (winNum) -+ { -+ case 0: -+ case 1: -+ pRemapRegs->lowRegOffs = AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum); -+ pRemapRegs->highRegOffs = AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum); -+ break; -+ case 2: -+ case 3: -+ if((mvCtrlModelGet() == MV_5281_DEV_ID) || -+ (mvCtrlModelGet() == MV_1281_DEV_ID) || -+ (mvCtrlModelGet() == MV_6183_DEV_ID) || -+ (mvCtrlModelGet() == MV_6183L_DEV_ID)) -+ { -+ pRemapRegs->lowRegOffs = AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum); -+ pRemapRegs->highRegOffs = AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum); -+ break; -+ } -+ else -+ { -+ pRemapRegs->lowRegOffs = 0; -+ pRemapRegs->highRegOffs = 0; -+ -+ DB(mvOsPrintf("ahbToMbusRemapRegOffsGet: ERR. Invalid winNum %d\n", -+ winNum)); -+ return MV_NO_SUCH; -+ } -+ default: -+ { -+ pRemapRegs->lowRegOffs = 0; -+ pRemapRegs->highRegOffs = 0; -+ -+ DB(mvOsPrintf("ahbToMbusRemapRegOffsGet: ERR. Invalid winNum %d\n", -+ winNum)); -+ return MV_NO_SUCH; -+ } -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvAhbToMbusAddDecShow - Print the AHB to MBus bridge address decode map. -+* -+* DESCRIPTION: -+* This function print the CPU address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvAhbToMbusAddDecShow(MV_VOID) -+{ -+ MV_AHB_TO_MBUS_DEC_WIN win; -+ MV_U32 winNum; -+ mvOsOutput( "\n" ); -+ mvOsOutput( "AHB To MBUS Bridge:\n" ); -+ mvOsOutput( "-------------------\n" ); -+ -+ for( winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS; winNum++ ) -+ { -+ memset( &win, 0, sizeof(MV_AHB_TO_MBUS_DEC_WIN) ); -+ -+ mvOsOutput( "win%d - ", winNum ); -+ -+ if( mvAhbToMbusWinGet( winNum, &win ) == MV_OK ) -+ { -+ if( win.enable ) -+ { -+ mvOsOutput( "%s base %08x, ", -+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); -+ mvOsOutput( "...." ); -+ mvSizePrint( win.addrWin.size ); -+ -+ mvOsOutput( "\n" ); -+ -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ } -+ } -+ -+} -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,130 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvAhbToMbush -+#define __INCmvAhbToMbush -+ -+/* includes */ -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/sys/mvAhbToMbusRegs.h" -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+ -+/* defines */ -+ -+#if defined(MV_88F1181) -+/* This enumerator defines the Marvell controller possible MBUS arbiter */ -+/* target ports. It is used to define crossbar priority scheame (pizza) */ -+typedef enum _mvMBusArbTargetId -+{ -+ DRAM_MBUS_ARB_TARGET = 0, /* Port 0 -> DRAM interface */ -+ TWSI_MBUS_ARB_TARGET = 1, /* Port 1 -> TWSI */ -+ ARM_MBUS_ARB_TARGET = 2, /* Port 2 -> ARM */ -+ PEX1_MBUS_ARB_TARGET = 3, /* Port 3 -> PCI Express 1 */ -+ PEX0_MBUS_ARB_TARGET = 4, /* Port 4 -> PCI Express0 */ -+ MAX_MBUS_ARB_TARGETS -+}MV_MBUS_ARB_TARGET; -+ -+typedef struct _mvMBusArbCtrl -+{ -+ MV_BOOL starvEn; -+ MV_BOOL highPrio; -+ MV_BOOL fixedRoundRobin; -+ -+}MV_MBUS_ARB_CTRL; -+ -+#endif /* #if defined(MV_88F1181) */ -+ -+typedef struct _mvAhbtoMbusDecWin -+{ -+ MV_TARGET target; -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+}MV_AHB_TO_MBUS_DEC_WIN; -+ -+/* mvAhbToMbus.h API list */ -+ -+MV_STATUS mvAhbToMbusInit(MV_VOID); -+MV_STATUS mvAhbToMbusWinSet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin); -+MV_STATUS mvAhbToMbusWinGet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin); -+MV_STATUS mvAhbToMbusWinEnable(MV_U32 winNum,MV_BOOL enable); -+MV_U32 mvAhbToMbusWinRemap(MV_U32 winNum, MV_ADDR_WIN *pAddrDecWin); -+MV_U32 mvAhbToMbusWinTargetGet(MV_TARGET target); -+MV_U32 mvAhbToMbusWinAvailGet(MV_VOID); -+MV_STATUS mvAhbToMbusWinTargetSwap(MV_TARGET target1,MV_TARGET target2); -+ -+#if defined(MV_88F1181) -+ -+MV_STATUS mvMbusArbSet(MV_MBUS_ARB_TARGET *pPizzaArbArray); -+MV_STATUS mvMbusArbCtrlSet(MV_MBUS_ARB_CTRL *ctrl); -+MV_STATUS mvMbusArbCtrlGet(MV_MBUS_ARB_CTRL *ctrl); -+ -+#endif /* #if defined(MV_88F1181) */ -+ -+ -+MV_VOID mvAhbToMbusAddDecShow(MV_VOID); -+ -+ -+#endif /* __INCmvAhbToMbush */ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,143 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvAhbToMbusRegsh -+#define __INCmvAhbToMbusRegsh -+ -+/******************************/ -+/* ARM Address Map Registers */ -+/******************************/ -+ -+#define MAX_AHB_TO_MBUS_WINS 9 -+#define MV_AHB_TO_MBUS_INTREG_WIN 8 -+ -+ -+#define AHB_TO_MBUS_WIN_CTRL_REG(winNum) (0x20000 + (winNum)*0x10) -+#define AHB_TO_MBUS_WIN_BASE_REG(winNum) (0x20004 + (winNum)*0x10) -+#define AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum) (0x20008 + (winNum)*0x10) -+#define AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum) (0x2000C + (winNum)*0x10) -+#define AHB_TO_MBUS_WIN_INTEREG_REG 0x20080 -+ -+/* Window Control Register */ -+/* AHB_TO_MBUS_WIN_CTRL_REG (ATMWCR)*/ -+#define ATMWCR_WIN_ENABLE BIT0 /* Window Enable */ -+ -+#define ATMWCR_WIN_TARGET_OFFS 4 /* The target interface associated -+ with this window*/ -+#define ATMWCR_WIN_TARGET_MASK (0xf << ATMWCR_WIN_TARGET_OFFS) -+ -+#define ATMWCR_WIN_ATTR_OFFS 8 /* The target interface attributes -+ Associated with this window */ -+#define ATMWCR_WIN_ATTR_MASK (0xff << ATMWCR_WIN_ATTR_OFFS) -+ -+ -+/* -+Used with the Base register to set the address window size and location -+Must be programed from LSB to MSB as sequence of 1’s followed -+by sequence of 0’s. The number of 1’s specifies the size of the window -+in 64 KB granularity (e.g. a value of 0x00FF specifies 256 = 16 MB). -+ -+NOTE: A value of 0x0 specifies 64KB size. -+*/ -+#define ATMWCR_WIN_SIZE_OFFS 16 /* Window Size */ -+#define ATMWCR_WIN_SIZE_MASK (0xffff << ATMWCR_WIN_SIZE_OFFS) -+#define ATMWCR_WIN_SIZE_ALIGNMENT 0x10000 -+ -+/* Window Base Register */ -+/* AHB_TO_MBUS_WIN_BASE_REG (ATMWBR) */ -+ -+/* -+Used with the size field to set the address window size and location. -+Corresponds to transaction address[31:16] -+*/ -+#define ATMWBR_BASE_OFFS 16 /* Base Address */ -+#define ATMWBR_BASE_MASK (0xffff << ATMWBR_BASE_OFFS) -+#define ATMWBR_BASE_ALIGNMENT 0x10000 -+ -+/* Window Remap Low Register */ -+/* AHB_TO_MBUS_WIN_REMAP_LOW_REG (ATMWRLR) */ -+ -+/* -+Used with the size field to specifies address bits[31:0] to be driven to -+the target interface.: -+target_addr[31:16] = (addr[31:16] & size[15:0]) | (remap[31:16] & ~size[15:0]) -+*/ -+#define ATMWRLR_REMAP_LOW_OFFS 16 /* Remap Address */ -+#define ATMWRLR_REMAP_LOW_MASK (0xffff << ATMWRLR_REMAP_LOW_OFFS) -+#define ATMWRLR_REMAP_LOW_ALIGNMENT 0x10000 -+ -+/* Window Remap High Register */ -+/* AHB_TO_MBUS_WIN_REMAP_HIGH_REG (ATMWRHR) */ -+ -+/* -+Specifies address bits[63:32] to be driven to the target interface. -+target_addr[63:32] = (RemapHigh[31:0] -+*/ -+#define ATMWRHR_REMAP_HIGH_OFFS 0 /* Remap Address */ -+#define ATMWRHR_REMAP_HIGH_MASK (0xffffffff << ATMWRHR_REMAP_HIGH_OFFS) -+ -+ -+#endif /* __INCmvAhbToMbusRegsh */ -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,1036 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+/* includes */ -+#include "ctrlEnv/sys/mvCpuIf.h" -+#include "ctrlEnv/sys/mvAhbToMbusRegs.h" -+#include "cpu/mvCpu.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "mvSysHwConfig.h" -+#include "mvSysDram.h" -+ -+/*#define MV_DEBUG*/ -+/* defines */ -+ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+/* locals */ -+/* static functions */ -+static MV_BOOL cpuTargetWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin); -+ -+MV_TARGET * sampleAtResetTargetArray; -+MV_TARGET sampleAtResetTargetArrayP[] = BOOT_TARGETS_NAME_ARRAY; -+MV_TARGET sampleAtResetTargetArray6180P[] = BOOT_TARGETS_NAME_ARRAY_6180; -+/******************************************************************************* -+* mvCpuIfInit - Initialize Controller CPU interface -+* -+* DESCRIPTION: -+* This function initialize Controller CPU interface: -+* 1. Set CPU interface configuration registers. -+* 2. Set CPU master Pizza arbiter control according to static -+* configuration described in configuration file. -+* 3. Opens CPU address decode windows. DRAM windows are assumed to be -+* already set (auto detection). -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvCpuIfInit(MV_CPU_DEC_WIN *cpuAddrWinMap) -+{ -+ MV_U32 regVal; -+ MV_TARGET target; -+ MV_ADDR_WIN addrWin; -+ -+ if (cpuAddrWinMap == NULL) -+ { -+ DB(mvOsPrintf("mvCpuIfInit:ERR. cpuAddrWinMap == NULL\n")); -+ return MV_ERROR; -+ } -+ -+ /*Initialize the boot target array according to device type*/ -+ if(mvCtrlModelGet() == MV_6180_DEV_ID) -+ sampleAtResetTargetArray = sampleAtResetTargetArray6180P; -+ else -+ sampleAtResetTargetArray = sampleAtResetTargetArrayP; -+ -+ /* Set ARM Configuration register */ -+ regVal = MV_REG_READ(CPU_CONFIG_REG); -+ regVal &= ~CPU_CONFIG_DEFAULT_MASK; -+ regVal |= CPU_CONFIG_DEFAULT; -+ MV_REG_WRITE(CPU_CONFIG_REG,regVal); -+ -+ /* First disable all CPU target windows */ -+ for (target = 0; cpuAddrWinMap[target].enable != TBL_TERM; target++) -+ { -+ if ((MV_TARGET_IS_DRAM(target))||(target == INTER_REGS)) -+ { -+ continue; -+ } -+ -+#if defined(MV_MEM_OVER_PCI_WA) || defined(MV_UART_OVER_PCI_WA) -+ /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ -+ if (MV_TARGET_IS_PCI(target)) -+ { -+ continue; -+ } -+#endif -+ -+#if defined(MV_MEM_OVER_PEX_WA) || defined(MV_UART_OVER_PEX_WA) -+ /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ -+ if (MV_TARGET_IS_PEX(target)) -+ { -+ continue; -+ } -+#endif -+#if defined(MV_RUN_FROM_FLASH) -+ /* Don't disable the boot device. */ -+ if (target == DEV_BOOCS) -+ { -+ continue; -+ } -+#endif /* MV_RUN_FROM_FLASH */ -+ mvCpuIfTargetWinEnable(MV_CHANGE_BOOT_CS(target),MV_FALSE); -+ } -+ -+#if defined(MV_RUN_FROM_FLASH) -+ /* Resize the bootcs windows before other windows, because this */ -+ /* window is enabled and will cause an overlap if not resized. */ -+ target = DEV_BOOCS; -+ -+ if (MV_OK != mvCpuIfTargetWinSet(target, &cpuAddrWinMap[target])) -+ { -+ DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinSet fail\n")); -+ return MV_ERROR; -+ } -+ -+ addrWin.baseLow = cpuAddrWinMap[target].addrWin.baseLow; -+ addrWin.baseHigh = cpuAddrWinMap[target].addrWin.baseHigh; -+ if (0xffffffff == mvAhbToMbusWinRemap(cpuAddrWinMap[target].winNum ,&addrWin)) -+ { -+ DB(mvOsPrintf("mvCpuIfInit:WARN. mvAhbToMbusWinRemap can't remap winNum=%d\n", -+ cpuAddrWinMap[target].winNum)); -+ } -+ -+#endif /* MV_RUN_FROM_FLASH */ -+ -+ /* Go through all targets in user table until table terminator */ -+ for (target = 0; cpuAddrWinMap[target].enable != TBL_TERM; target++) -+ { -+ -+#if defined(MV_RUN_FROM_FLASH) -+ if (target == DEV_BOOCS) -+ { -+ continue; -+ } -+#endif /* MV_RUN_FROM_FLASH */ -+ -+ /* if DRAM auto sizing is used do not initialized DRAM target windows, */ -+ /* assuming this already has been done earlier. */ -+#ifdef MV_DRAM_AUTO_SIZE -+ if (MV_TARGET_IS_DRAM(target)) -+ { -+ continue; -+ } -+#endif -+ -+#if defined(MV_MEM_OVER_PCI_WA) || defined(MV_UART_OVER_PCI_WA) -+ /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ -+ if (MV_TARGET_IS_PCI(target)) -+ { -+ continue; -+ } -+#endif -+ -+#if defined(MV_MEM_OVER_PEX_WA) || defined(MV_UART_OVER_PEX_WA) -+ /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ -+ if (MV_TARGET_IS_PEX(target)) -+ { -+ continue; -+ } -+#endif -+ /* If the target attribute is the same as the boot device attribute */ -+ /* then it's stays disable */ -+ if (MV_TARGET_IS_AS_BOOT(target)) -+ { -+ continue; -+ } -+ -+ if((0 == cpuAddrWinMap[target].addrWin.size) || -+ (DIS == cpuAddrWinMap[target].enable)) -+ -+ { -+ if (MV_OK != mvCpuIfTargetWinEnable(target, MV_FALSE)) -+ { -+ DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinEnable fail\n")); -+ return MV_ERROR; -+ } -+ -+ } -+ else -+ { -+ if (MV_OK != mvCpuIfTargetWinSet(target, &cpuAddrWinMap[target])) -+ { -+ DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinSet fail\n")); -+ return MV_ERROR; -+ } -+ -+ addrWin.baseLow = cpuAddrWinMap[target].addrWin.baseLow; -+ addrWin.baseHigh = cpuAddrWinMap[target].addrWin.baseHigh; -+ if (0xffffffff == mvAhbToMbusWinRemap(cpuAddrWinMap[target].winNum ,&addrWin)) -+ { -+ DB(mvOsPrintf("mvCpuIfInit:WARN. mvAhbToMbusWinRemap can't remap winNum=%d\n", -+ cpuAddrWinMap[target].winNum)); -+ } -+ -+ -+ } -+ } -+ -+ return MV_OK; -+ -+ -+} -+ -+ -+/******************************************************************************* -+* mvCpuIfTargetWinSet - Set CPU-to-peripheral target address window -+* -+* DESCRIPTION: -+* This function sets a peripheral target (e.g. SDRAM bank0, PCI0_MEM0) -+* address window, also known as address decode window. -+* A new address decode window is set for specified target address window. -+* If address decode window parameter structure enables the window, -+* the routine will also enable the target window, allowing CPU to access -+* the target window. -+* -+* INPUT: -+* target - Peripheral target enumerator. -+* pAddrDecWin - CPU target window data structure. -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_OK if CPU target window was set correctly, MV_ERROR in case of -+* address window overlapps with other active CPU target window or -+* trying to assign 36bit base address while CPU does not support that. -+* The function returns MV_NOT_SUPPORTED, if the target is unsupported. -+* -+*******************************************************************************/ -+MV_STATUS mvCpuIfTargetWinSet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin) -+{ -+ MV_AHB_TO_MBUS_DEC_WIN decWin; -+ MV_U32 existingWinNum; -+ MV_DRAM_DEC_WIN addrDecWin; -+ -+ target = MV_CHANGE_BOOT_CS(target); -+ -+ /* Check parameters */ -+ if (target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvCpuIfTargetWinSet: target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ /* 2) Check if the requested window overlaps with current windows */ -+ if (MV_TRUE == cpuTargetWinOverlap(target, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("mvCpuIfTargetWinSet: ERR. Target %d overlap\n", target); -+ return MV_BAD_PARAM; -+ } -+ -+ if (MV_TARGET_IS_DRAM(target)) -+ { -+ /* copy relevant data to MV_DRAM_DEC_WIN structure */ -+ addrDecWin.addrWin.baseHigh = pAddrDecWin->addrWin.baseHigh; -+ addrDecWin.addrWin.baseLow = pAddrDecWin->addrWin.baseLow; -+ addrDecWin.addrWin.size = pAddrDecWin->addrWin.size; -+ addrDecWin.enable = pAddrDecWin->enable; -+ -+ -+ if (mvDramIfWinSet(target,&addrDecWin) != MV_OK); -+ { -+ mvOsPrintf("mvCpuIfTargetWinSet: mvDramIfWinSet Failed\n"); -+ return MV_ERROR; -+ } -+ -+ } -+ else -+ { -+ /* copy relevant data to MV_AHB_TO_MBUS_DEC_WIN structure */ -+ decWin.addrWin.baseLow = pAddrDecWin->addrWin.baseLow; -+ decWin.addrWin.baseHigh = pAddrDecWin->addrWin.baseHigh; -+ decWin.addrWin.size = pAddrDecWin->addrWin.size; -+ decWin.enable = pAddrDecWin->enable; -+ decWin.target = target; -+ -+ existingWinNum = mvAhbToMbusWinTargetGet(target); -+ -+ /* check if there is already another Window configured -+ for this target */ -+ if ((existingWinNum < MAX_AHB_TO_MBUS_WINS )&& -+ (existingWinNum != pAddrDecWin->winNum)) -+ { -+ /* if we want to enable the new winow number -+ passed by the user , then the old one should -+ be disabled */ -+ if (MV_TRUE == pAddrDecWin->enable) -+ { -+ /* be sure it is disabled */ -+ mvAhbToMbusWinEnable(existingWinNum , MV_FALSE); -+ } -+ } -+ -+ if (mvAhbToMbusWinSet(pAddrDecWin->winNum,&decWin) != MV_OK) -+ { -+ mvOsPrintf("mvCpuIfTargetWinSet: mvAhbToMbusWinSet Failed\n"); -+ return MV_ERROR; -+ } -+ -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCpuIfTargetWinGet - Get CPU-to-peripheral target address window -+* -+* DESCRIPTION: -+* Get the CPU peripheral target address window. -+* -+* INPUT: -+* target - Peripheral target enumerator -+* -+* OUTPUT: -+* pAddrDecWin - CPU target window information data structure. -+* -+* RETURN: -+* MV_OK if target exist, MV_ERROR otherwise. -+* -+*******************************************************************************/ -+MV_STATUS mvCpuIfTargetWinGet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin) -+{ -+ -+ MV_U32 winNum=0xffffffff; -+ MV_AHB_TO_MBUS_DEC_WIN decWin; -+ MV_DRAM_DEC_WIN addrDecWin; -+ -+ target = MV_CHANGE_BOOT_CS(target); -+ -+ /* Check parameters */ -+ if (target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvCpuIfTargetWinGet: target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ if (MV_TARGET_IS_DRAM(target)) -+ { -+ if (mvDramIfWinGet(target,&addrDecWin) != MV_OK) -+ { -+ mvOsPrintf("mvCpuIfTargetWinGet: Failed to get window target %d\n", -+ target); -+ return MV_ERROR; -+ } -+ -+ /* copy relevant data to MV_CPU_DEC_WIN structure */ -+ pAddrDecWin->addrWin.baseLow = addrDecWin.addrWin.baseLow; -+ pAddrDecWin->addrWin.baseHigh = addrDecWin.addrWin.baseHigh; -+ pAddrDecWin->addrWin.size = addrDecWin.addrWin.size; -+ pAddrDecWin->enable = addrDecWin.enable; -+ pAddrDecWin->winNum = 0xffffffff; -+ -+ } -+ else -+ { -+ /* get the Window number associated with this target */ -+ -+ winNum = mvAhbToMbusWinTargetGet(target); -+ if (winNum >= MAX_AHB_TO_MBUS_WINS) -+ { -+ return MV_NO_SUCH; -+ -+ } -+ -+ if (mvAhbToMbusWinGet(winNum , &decWin) != MV_OK) -+ { -+ mvOsPrintf("%s: mvAhbToMbusWinGet Failed at winNum = %d\n", -+ __FUNCTION__, winNum); -+ return MV_ERROR; -+ -+ } -+ -+ /* copy relevant data to MV_CPU_DEC_WIN structure */ -+ pAddrDecWin->addrWin.baseLow = decWin.addrWin.baseLow; -+ pAddrDecWin->addrWin.baseHigh = decWin.addrWin.baseHigh; -+ pAddrDecWin->addrWin.size = decWin.addrWin.size; -+ pAddrDecWin->enable = decWin.enable; -+ pAddrDecWin->winNum = winNum; -+ -+ } -+ -+ -+ -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvCpuIfTargetWinEnable - Enable/disable a CPU address decode window -+* -+* DESCRIPTION: -+* This function enable/disable a CPU address decode window. -+* if parameter 'enable' == MV_TRUE the routine will enable the -+* window, thus enabling CPU accesses (before enabling the window it is -+* tested for overlapping). Otherwise, the window will be disabled. -+* -+* INPUT: -+* target - Peripheral target enumerator. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_ERROR if protection window number was wrong, or the window -+* overlapps other target window. -+* -+*******************************************************************************/ -+MV_STATUS mvCpuIfTargetWinEnable(MV_TARGET target,MV_BOOL enable) -+{ -+ MV_U32 winNum, temp; -+ MV_CPU_DEC_WIN addrDecWin; -+ -+ target = MV_CHANGE_BOOT_CS(target); -+ -+ /* Check parameters */ -+ if (target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvCpuIfTargetWinEnable: target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ /* get the window and check if it exist */ -+ temp = mvCpuIfTargetWinGet(target, &addrDecWin); -+ if (MV_NO_SUCH == temp) -+ { -+ return (enable? MV_ERROR: MV_OK); -+ } -+ else if( MV_OK != temp) -+ { -+ mvOsPrintf("%s: ERR. Getting target %d failed.\n",__FUNCTION__, target); -+ return MV_ERROR; -+ } -+ -+ -+ /* check overlap */ -+ -+ if (MV_TRUE == enable) -+ { -+ if (MV_TRUE == cpuTargetWinOverlap(target, &addrDecWin.addrWin)) -+ { -+ DB(mvOsPrintf("%s: ERR. Target %d overlap\n",__FUNCTION__, target)); -+ return MV_ERROR; -+ } -+ -+ } -+ -+ -+ if (MV_TARGET_IS_DRAM(target)) -+ { -+ if (mvDramIfWinEnable(target , enable) != MV_OK) -+ { -+ mvOsPrintf("mvCpuIfTargetWinGet: mvDramIfWinEnable Failed at \n"); -+ return MV_ERROR; -+ -+ } -+ -+ } -+ else -+ { -+ /* get the Window number associated with this target */ -+ -+ winNum = mvAhbToMbusWinTargetGet(target); -+ -+ if (winNum >= MAX_AHB_TO_MBUS_WINS) -+ { -+ return (enable? MV_ERROR: MV_OK); -+ } -+ -+ if (mvAhbToMbusWinEnable(winNum , enable) != MV_OK) -+ { -+ mvOsPrintf("mvCpuIfTargetWinGet: Failed to enable window = %d\n", -+ winNum); -+ return MV_ERROR; -+ -+ } -+ -+ } -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvCpuIfTargetWinSizeGet - Get CPU target address window size -+* -+* DESCRIPTION: -+* Get the size of CPU-to-peripheral target window. -+* -+* INPUT: -+* target - Peripheral target enumerator -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit size. Function also returns '0' if window is closed. -+* Function returns 0xFFFFFFFF in case of an error. -+* -+*******************************************************************************/ -+MV_U32 mvCpuIfTargetWinSizeGet(MV_TARGET target) -+{ -+ MV_CPU_DEC_WIN addrDecWin; -+ -+ target = MV_CHANGE_BOOT_CS(target); -+ -+ /* Check parameters */ -+ if (target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvCpuIfTargetWinSizeGet: target %d is Illigal\n", target); -+ return 0; -+ } -+ -+ /* Get the winNum window */ -+ if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) -+ { -+ mvOsPrintf("mvCpuIfTargetWinSizeGet:ERR. Getting target %d failed.\n", -+ target); -+ return 0; -+ } -+ -+ /* Check if window is enabled */ -+ if (addrDecWin.enable == MV_TRUE) -+ { -+ return (addrDecWin.addrWin.size); -+ } -+ else -+ { -+ return 0; /* Window disabled. return 0 */ -+ } -+} -+ -+/******************************************************************************* -+* mvCpuIfTargetWinBaseLowGet - Get CPU target address window base low -+* -+* DESCRIPTION: -+* CPU-to-peripheral target address window base is constructed of -+* two parts: Low and high. -+* This function gets the CPU peripheral target low base address. -+* -+* INPUT: -+* target - Peripheral target enumerator -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit low base address. -+* -+*******************************************************************************/ -+MV_U32 mvCpuIfTargetWinBaseLowGet(MV_TARGET target) -+{ -+ MV_CPU_DEC_WIN addrDecWin; -+ -+ target = MV_CHANGE_BOOT_CS(target); -+ -+ /* Check parameters */ -+ if (target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvCpuIfTargetWinBaseLowGet: target %d is Illigal\n", target); -+ return 0xffffffff; -+ } -+ -+ /* Get the target window */ -+ if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) -+ { -+ mvOsPrintf("mvCpuIfTargetWinBaseLowGet:ERR. Getting target %d failed.\n", -+ target); -+ return 0xffffffff; -+ } -+ -+ if (MV_FALSE == addrDecWin.enable) -+ { -+ return 0xffffffff; -+ } -+ return (addrDecWin.addrWin.baseLow); -+} -+ -+/******************************************************************************* -+* mvCpuIfTargetWinBaseHighGet - Get CPU target address window base high -+* -+* DESCRIPTION: -+* CPU-to-peripheral target address window base is constructed of -+* two parts: Low and high. -+* This function gets the CPU peripheral target high base address. -+* -+* INPUT: -+* target - Peripheral target enumerator -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit high base address. -+* -+*******************************************************************************/ -+MV_U32 mvCpuIfTargetWinBaseHighGet(MV_TARGET target) -+{ -+ MV_CPU_DEC_WIN addrDecWin; -+ -+ target = MV_CHANGE_BOOT_CS(target); -+ -+ /* Check parameters */ -+ if (target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvCpuIfTargetWinBaseLowGet: target %d is Illigal\n", target); -+ return 0xffffffff; -+ } -+ -+ /* Get the target window */ -+ if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) -+ { -+ mvOsPrintf("mvCpuIfTargetWinBaseHighGet:ERR. Getting target %d failed.\n", -+ target); -+ return 0xffffffff; -+ } -+ -+ if (MV_FALSE == addrDecWin.enable) -+ { -+ return 0; -+ } -+ -+ return (addrDecWin.addrWin.baseHigh); -+} -+ -+#if defined(MV_INCLUDE_PEX) -+/******************************************************************************* -+* mvCpuIfPexRemap - Set CPU remap register for address windows. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* pexTarget - Peripheral target enumerator. Must be a PEX target. -+* pAddrDecWin - CPU target window information data structure. -+* Note that caller has to fill in the base field only. The -+* size field is ignored. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR if target is not a PEX one, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_U32 mvCpuIfPexRemap(MV_TARGET pexTarget, MV_ADDR_WIN *pAddrDecWin) -+{ -+ MV_U32 winNum; -+ -+ /* Check parameters */ -+ -+ if (mvCtrlPexMaxIfGet() > 1) -+ { -+ if ((!MV_TARGET_IS_PEX1(pexTarget))&&(!MV_TARGET_IS_PEX0(pexTarget))) -+ { -+ mvOsPrintf("mvCpuIfPexRemap: target %d is Illigal\n",pexTarget); -+ return 0xffffffff; -+ } -+ -+ } -+ else -+ { -+ if (!MV_TARGET_IS_PEX0(pexTarget)) -+ { -+ mvOsPrintf("mvCpuIfPexRemap: target %d is Illigal\n",pexTarget); -+ return 0xffffffff; -+ } -+ -+ } -+ -+ /* get the Window number associated with this target */ -+ winNum = mvAhbToMbusWinTargetGet(pexTarget); -+ -+ if (winNum >= MAX_AHB_TO_MBUS_WINS) -+ { -+ mvOsPrintf("mvCpuIfPexRemap: mvAhbToMbusWinTargetGet Failed\n"); -+ return 0xffffffff; -+ -+ } -+ -+ return mvAhbToMbusWinRemap(winNum , pAddrDecWin); -+} -+ -+#endif -+ -+#if defined(MV_INCLUDE_PCI) -+/******************************************************************************* -+* mvCpuIfPciRemap - Set CPU remap register for address windows. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* pciTarget - Peripheral target enumerator. Must be a PCI target. -+* pAddrDecWin - CPU target window information data structure. -+* Note that caller has to fill in the base field only. The -+* size field is ignored. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR if target is not a PCI one, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_U32 mvCpuIfPciRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin) -+{ -+ MV_U32 winNum; -+ -+ /* Check parameters */ -+ if (!MV_TARGET_IS_PCI(pciTarget)) -+ { -+ mvOsPrintf("mvCpuIfPciRemap: target %d is Illigal\n",pciTarget); -+ return 0xffffffff; -+ } -+ -+ /* get the Window number associated with this target */ -+ winNum = mvAhbToMbusWinTargetGet(pciTarget); -+ -+ if (winNum >= MAX_AHB_TO_MBUS_WINS) -+ { -+ mvOsPrintf("mvCpuIfPciRemap: mvAhbToMbusWinTargetGet Failed\n"); -+ return 0xffffffff; -+ -+ } -+ -+ return mvAhbToMbusWinRemap(winNum , pAddrDecWin); -+} -+#endif /* MV_INCLUDE_PCI */ -+ -+ -+/******************************************************************************* -+* mvCpuIfPciIfRemap - Set CPU remap register for address windows. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* pciTarget - Peripheral target enumerator. Must be a PCI target. -+* pAddrDecWin - CPU target window information data structure. -+* Note that caller has to fill in the base field only. The -+* size field is ignored. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR if target is not a PCI one, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_U32 mvCpuIfPciIfRemap(MV_TARGET pciIfTarget, MV_ADDR_WIN *pAddrDecWin) -+{ -+#if defined(MV_INCLUDE_PEX) -+ if (MV_TARGET_IS_PEX(pciIfTarget)) -+ { -+ return mvCpuIfPexRemap(pciIfTarget,pAddrDecWin); -+ } -+#endif -+#if defined(MV_INCLUDE_PCI) -+ -+ if (MV_TARGET_IS_PCI(pciIfTarget)) -+ { -+ return mvCpuIfPciRemap(pciIfTarget,pAddrDecWin); -+ } -+#endif -+ return 0; -+} -+ -+ -+ -+/******************************************************************************* -+* mvCpuIfTargetOfBaseAddressGet - Get the target according to base address -+* -+* DESCRIPTION: -+* -+* INPUT: -+* baseAddress - base address to be checked -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* the target number that baseAddress belongs to or MAX_TARGETS is not -+* found -+* -+*******************************************************************************/ -+ -+MV_TARGET mvCpuIfTargetOfBaseAddressGet(MV_U32 baseAddress) -+{ -+ MV_CPU_DEC_WIN win; -+ MV_U32 target; -+ -+ for( target = 0; target < MAX_TARGETS; target++ ) -+ { -+ if( mvCpuIfTargetWinGet( target, &win ) == MV_OK ) -+ { -+ if( win.enable ) -+ { -+ if ((baseAddress >= win.addrWin.baseLow) && -+ (baseAddress < win.addrWin.baseLow + win.addrWin.size)) break; -+ } -+ } -+ else return MAX_TARGETS; -+ -+ } -+ -+ return target; -+} -+/******************************************************************************* -+* cpuTargetWinOverlap - Detect CPU address decode windows overlapping -+* -+* DESCRIPTION: -+* An unpredicted behaviur is expected in case CPU address decode -+* windows overlapps. -+* This function detects CPU address decode windows overlapping of a -+* specified target. The function does not check the target itself for -+* overlapping. The function also skipps disabled address decode windows. -+* -+* INPUT: -+* target - Peripheral target enumerator. -+* pAddrDecWin - An address decode window struct. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlaps current address -+* decode map, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+static MV_BOOL cpuTargetWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 targetNum; -+ MV_CPU_DEC_WIN addrDecWin; -+ MV_STATUS status; -+ -+ -+ for(targetNum = 0; targetNum < MAX_TARGETS; targetNum++) -+ { -+#if defined(MV_RUN_FROM_FLASH) -+ if(MV_TARGET_IS_AS_BOOT(target)) -+ { -+ if (MV_CHANGE_BOOT_CS(targetNum) == target) -+ continue; -+ } -+#endif /* MV_RUN_FROM_FLASH */ -+ -+ /* don't check our target or illegal targets */ -+ if (targetNum == target) -+ { -+ continue; -+ } -+ -+ /* Get window parameters */ -+ status = mvCpuIfTargetWinGet(targetNum, &addrDecWin); -+ if(MV_NO_SUCH == status) -+ { -+ continue; -+ } -+ if(MV_OK != status) -+ { -+ DB(mvOsPrintf("cpuTargetWinOverlap: ERR. TargetWinGet failed\n")); -+ return MV_TRUE; -+ } -+ -+ /* Do not check disabled windows */ -+ if (MV_FALSE == addrDecWin.enable) -+ { -+ continue; -+ } -+ -+ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) -+ { -+ DB(mvOsPrintf( -+ "cpuTargetWinOverlap: Required target %d overlap current %d\n", -+ target, targetNum)); -+ return MV_TRUE; -+ } -+ } -+ -+ return MV_FALSE; -+ -+} -+ -+/******************************************************************************* -+* mvCpuIfAddDecShow - Print the CPU address decode map. -+* -+* DESCRIPTION: -+* This function print the CPU address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvCpuIfAddDecShow(MV_VOID) -+{ -+ MV_CPU_DEC_WIN win; -+ MV_U32 target; -+ mvOsOutput( "\n" ); -+ mvOsOutput( "CPU Interface\n" ); -+ mvOsOutput( "-------------\n" ); -+ -+ for( target = 0; target < MAX_TARGETS; target++ ) -+ { -+ -+ memset( &win, 0, sizeof(MV_CPU_DEC_WIN) ); -+ -+ mvOsOutput( "%s ",mvCtrlTargetNameGet(target)); -+ mvOsOutput( "...." ); -+ -+ if( mvCpuIfTargetWinGet( target, &win ) == MV_OK ) -+ { -+ if( win.enable ) -+ { -+ mvOsOutput( "base %08x, ", win.addrWin.baseLow ); -+ mvSizePrint( win.addrWin.size ); -+ mvOsOutput( "\n" ); -+ -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ } -+ else if( mvCpuIfTargetWinGet( target, &win ) == MV_NO_SUCH ) -+ { -+ mvOsOutput( "no such\n" ); -+ } -+ } -+} -+ -+/******************************************************************************* -+* mvCpuIfEnablePex - Enable PCI Express. -+* -+* DESCRIPTION: -+* This function Enable PCI Express. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* pexType - MV_PEX_ROOT_COMPLEX - root complex device -+* MV_PEX_END_POINT - end point device -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+#if defined(MV_INCLUDE_PEX) -+MV_VOID mvCpuIfEnablePex(MV_U32 pexIf, MV_PEX_TYPE pexType) -+{ -+ /* Set pex mode incase S@R not exist */ -+ if( pexType == MV_PEX_END_POINT) -+ { -+ MV_REG_BIT_RESET(PEX_CTRL_REG(pexIf),PXCR_DEV_TYPE_CTRL_MASK); -+ /* Change pex mode in capability reg */ -+ MV_REG_BIT_RESET(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_CAPABILITY_REG), BIT22); -+ MV_REG_BIT_SET(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_CAPABILITY_REG), BIT20); -+ -+ } -+ else -+ { -+ MV_REG_BIT_SET(PEX_CTRL_REG(pexIf),PXCR_DEV_TYPE_CTRL_MASK); -+ } -+ -+ /* CPU config register Pex enable */ -+ MV_REG_BIT_SET(CPU_CTRL_STAT_REG,CCSR_PCI_ACCESS_MASK); -+} -+#endif -+ -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,120 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvCpuIfh -+#define __INCmvCpuIfh -+ -+/* includes */ -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/sys/mvCpuIfRegs.h" -+#include "ctrlEnv/sys/mvAhbToMbus.h" -+#include "ddr2/mvDramIf.h" -+#include "ctrlEnv/sys/mvSysDram.h" -+#if defined(MV_INCLUDE_PEX) -+#include "pex/mvPex.h" -+#endif -+ -+/* defines */ -+ -+/* typedefs */ -+/* This structure describes CPU interface address decode window */ -+typedef struct _mvCpuIfDecWin -+{ -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_U32 winNum; /* Window Number in the AHB To Mbus bridge */ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+}MV_CPU_DEC_WIN; -+ -+ -+ -+/* mvCpuIfLib.h API list */ -+ -+/* mvCpuIfLib.h API list */ -+ -+MV_STATUS mvCpuIfInit(MV_CPU_DEC_WIN *cpuAddrWinMap); -+MV_STATUS mvCpuIfTargetWinSet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin); -+MV_STATUS mvCpuIfTargetWinGet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin); -+MV_STATUS mvCpuIfTargetWinEnable(MV_TARGET target,MV_BOOL enable); -+MV_U32 mvCpuIfTargetWinSizeGet(MV_TARGET target); -+MV_U32 mvCpuIfTargetWinBaseLowGet(MV_TARGET target); -+MV_U32 mvCpuIfTargetWinBaseHighGet(MV_TARGET target); -+MV_TARGET mvCpuIfTargetOfBaseAddressGet(MV_U32 baseAddress); -+#if defined(MV_INCLUDE_PEX) -+MV_U32 mvCpuIfPexRemap(MV_TARGET pexTarget, MV_ADDR_WIN *pAddrDecWin); -+MV_VOID mvCpuIfEnablePex(MV_U32 pexIf, MV_PEX_TYPE pexType); -+#endif -+#if defined(MV_INCLUDE_PCI) -+MV_U32 mvCpuIfPciRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin); -+#endif -+MV_U32 mvCpuIfPciIfRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin); -+ -+MV_VOID mvCpuIfAddDecShow(MV_VOID); -+ -+#if defined(MV88F6281) -+MV_STATUS mvCpuIfBridgeReorderWAInit(void); -+#endif -+ -+#endif /* __INCmvCpuIfh */ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,304 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvCpuIfRegsh -+#define __INCmvCpuIfRegsh -+ -+/****************************************/ -+/* ARM Control and Status Registers Map */ -+/****************************************/ -+ -+#define CPU_CONFIG_REG 0x20100 -+#define CPU_CTRL_STAT_REG 0x20104 -+#define CPU_RSTOUTN_MASK_REG 0x20108 -+#define CPU_SYS_SOFT_RST_REG 0x2010C -+#define CPU_AHB_MBUS_CAUSE_INT_REG 0x20110 -+#define CPU_AHB_MBUS_MASK_INT_REG 0x20114 -+#define CPU_FTDLL_CONFIG_REG 0x20120 -+#define CPU_L2_CONFIG_REG 0x20128 -+ -+ -+ -+/* ARM Configuration register */ -+/* CPU_CONFIG_REG (CCR) */ -+ -+ -+/* Reset vector location */ -+#define CCR_VEC_INIT_LOC_OFFS 1 -+#define CCR_VEC_INIT_LOC_MASK BIT1 -+/* reset at 0x00000000 */ -+#define CCR_VEC_INIT_LOC_0000 (0 << CCR_VEC_INIT_LOC_OFFS) -+/* reset at 0xFFFF0000 */ -+#define CCR_VEC_INIT_LOC_FF00 (1 << CCR_VEC_INIT_LOC_OFFS) -+ -+ -+#define CCR_AHB_ERROR_PROP_OFFS 2 -+#define CCR_AHB_ERROR_PROP_MASK BIT2 -+/* Erros are not propogated to AHB */ -+#define CCR_AHB_ERROR_PROP_NO_INDICATE (0 << CCR_AHB_ERROR_PROP_OFFS) -+/* Erros are propogated to AHB */ -+#define CCR_AHB_ERROR_PROP_INDICATE (1 << CCR_AHB_ERROR_PROP_OFFS) -+ -+ -+#define CCR_ENDIAN_INIT_OFFS 3 -+#define CCR_ENDIAN_INIT_MASK BIT3 -+#define CCR_ENDIAN_INIT_LITTLE (0 << CCR_ENDIAN_INIT_OFFS) -+#define CCR_ENDIAN_INIT_BIG (1 << CCR_ENDIAN_INIT_OFFS) -+ -+ -+#define CCR_INCR_EN_OFFS 4 -+#define CCR_INCR_EN_MASK BIT4 -+#define CCR_INCR_EN BIT4 -+ -+ -+#define CCR_NCB_BLOCKING_OFFS 5 -+#define CCR_NCB_BLOCKING_MASK (1 << CCR_NCB_BLOCKING_OFFS) -+#define CCR_NCB_BLOCKING_NON (0 << CCR_NCB_BLOCKING_OFFS) -+#define CCR_NCB_BLOCKING_EN (1 << CCR_NCB_BLOCKING_OFFS) -+ -+#define CCR_CPU_2_MBUSL_TICK_DRV_OFFS 8 -+#define CCR_CPU_2_MBUSL_TICK_DRV_MASK (0xF << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) -+#define CCR_CPU_2_MBUSL_TICK_SMPL_OFFS 12 -+#define CCR_CPU_2_MBUSL_TICK_SMPL_MASK (0xF << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS) -+#define CCR_ICACH_PREF_BUF_ENABLE BIT16 -+#define CCR_DCACH_PREF_BUF_ENABLE BIT17 -+ -+/* Ratio options for CPU to DDR for 6281/6192/6190 */ -+#define CPU_2_DDR_CLK_1x3 4 -+#define CPU_2_DDR_CLK_1x4 6 -+ -+/* Ratio options for CPU to DDR for 6281 only */ -+#define CPU_2_DDR_CLK_2x9 7 -+#define CPU_2_DDR_CLK_1x5 8 -+#define CPU_2_DDR_CLK_1x6 9 -+ -+/* Ratio options for CPU to DDR for 6180 only */ -+#define CPU_2_DDR_CLK_1x3_1 0x5 -+#define CPU_2_DDR_CLK_1x4_1 0x6 -+ -+/* Default values for CPU to Mbus-L DDR Interface Tick Driver and */ -+/* CPU to Mbus-L Tick Sample fields in CPU config register */ -+ -+#define TICK_DRV_1x1 0 -+#define TICK_DRV_1x2 0 -+#define TICK_DRV_1x3 1 -+#define TICK_DRV_1x4 2 -+#define TICK_SMPL_1x1 0 -+#define TICK_SMPL_1x2 1 -+#define TICK_SMPL_1x3 0 -+#define TICK_SMPL_1x4 0 -+ -+#define CPU_2_MBUSL_DDR_CLK_1x2 \ -+ ((TICK_DRV_1x2 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \ -+ (TICK_SMPL_1x2 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS)) -+#define CPU_2_MBUSL_DDR_CLK_1x3 \ -+ ((TICK_DRV_1x3 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \ -+ (TICK_SMPL_1x3 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS)) -+#define CPU_2_MBUSL_DDR_CLK_1x4 \ -+ ((TICK_DRV_1x4 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \ -+ (TICK_SMPL_1x4 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS)) -+ -+/* ARM Control and Status register */ -+/* CPU_CTRL_STAT_REG (CCSR) */ -+ -+ -+/* -+This is used to block PCI express\PCI from access Socrates/Feroceon GP -+while ARM boot is still in progress -+*/ -+ -+#define CCSR_PCI_ACCESS_OFFS 0 -+#define CCSR_PCI_ACCESS_MASK BIT0 -+#define CCSR_PCI_ACCESS_ENABLE (0 << CCSR_PCI_ACCESS_OFFS) -+#define CCSR_PCI_ACCESS_DISBALE (1 << CCSR_PCI_ACCESS_OFFS) -+ -+#define CCSR_ARM_RESET BIT1 -+#define CCSR_SELF_INT BIT2 -+#define CCSR_BIG_ENDIAN BIT15 -+ -+ -+/* RSTOUTn Mask Register */ -+/* CPU_RSTOUTN_MASK_REG (CRMR) */ -+ -+#define CRMR_PEX_RST_OUT_OFFS 0 -+#define CRMR_PEX_RST_OUT_MASK BIT0 -+#define CRMR_PEX_RST_OUT_ENABLE (1 << CRMR_PEX_RST_OUT_OFFS) -+#define CRMR_PEX_RST_OUT_DISABLE (0 << CRMR_PEX_RST_OUT_OFFS) -+ -+#define CRMR_WD_RST_OUT_OFFS 1 -+#define CRMR_WD_RST_OUT_MASK BIT1 -+#define CRMR_WD_RST_OUT_ENABLE (1 << CRMR_WD_RST_OUT_OFFS) -+#define CRMR_WD_RST_OUT_DISBALE (0 << CRMR_WD_RST_OUT_OFFS) -+ -+#define CRMR_SOFT_RST_OUT_OFFS 2 -+#define CRMR_SOFT_RST_OUT_MASK BIT2 -+#define CRMR_SOFT_RST_OUT_ENABLE (1 << CRMR_SOFT_RST_OUT_OFFS) -+#define CRMR_SOFT_RST_OUT_DISBALE (0 << CRMR_SOFT_RST_OUT_OFFS) -+ -+/* System Software Reset Register */ -+/* CPU_SYS_SOFT_RST_REG (CSSRR) */ -+ -+#define CSSRR_SYSTEM_SOFT_RST BIT0 -+ -+/* AHB to Mbus Bridge Interrupt Cause Register*/ -+/* CPU_AHB_MBUS_CAUSE_INT_REG (CAMCIR) */ -+ -+#define CAMCIR_ARM_SELF_INT BIT0 -+#define CAMCIR_ARM_TIMER0_INT_REQ BIT1 -+#define CAMCIR_ARM_TIMER1_INT_REQ BIT2 -+#define CAMCIR_ARM_WD_TIMER_INT_REQ BIT3 -+ -+ -+/* AHB to Mbus Bridge Interrupt Mask Register*/ -+/* CPU_AHB_MBUS_MASK_INT_REG (CAMMIR) */ -+ -+#define CAMCIR_ARM_SELF_INT_OFFS 0 -+#define CAMCIR_ARM_SELF_INT_MASK BIT0 -+#define CAMCIR_ARM_SELF_INT_EN (1 << CAMCIR_ARM_SELF_INT_OFFS) -+#define CAMCIR_ARM_SELF_INT_DIS (0 << CAMCIR_ARM_SELF_INT_OFFS) -+ -+ -+#define CAMCIR_ARM_TIMER0_INT_REQ_OFFS 1 -+#define CAMCIR_ARM_TIMER0_INT_REQ_MASK BIT1 -+#define CAMCIR_ARM_TIMER0_INT_REQ_EN (1 << CAMCIR_ARM_TIMER0_INT_REQ_OFFS) -+#define CAMCIR_ARM_TIMER0_INT_REQ_DIS (0 << CAMCIR_ARM_TIMER0_INT_REQ_OFFS) -+ -+#define CAMCIR_ARM_TIMER1_INT_REQ_OFFS 2 -+#define CAMCIR_ARM_TIMER1_INT_REQ_MASK BIT2 -+#define CAMCIR_ARM_TIMER1_INT_REQ_EN (1 << CAMCIR_ARM_TIMER1_INT_REQ_OFFS) -+#define CAMCIR_ARM_TIMER1_INT_REQ_DIS (0 << CAMCIR_ARM_TIMER1_INT_REQ_OFFS) -+ -+#define CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS 3 -+#define CAMCIR_ARM_WD_TIMER_INT_REQ_MASK BIT3 -+#define CAMCIR_ARM_WD_TIMER_INT_REQ_EN (1 << CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS) -+#define CAMCIR_ARM_WD_TIMER_INT_REQ_DIS (0 << CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS) -+ -+/* CPU FTDLL Config register (CFCR) fields */ -+#define CFCR_FTDLL_ICACHE_TAG_OFFS 0 -+#define CFCR_FTDLL_ICACHE_TAG_MASK (0x7F << CFCR_FTDLL_ICACHE_TAG_OFFS) -+#define CFCR_FTDLL_DCACHE_TAG_OFFS 8 -+#define CFCR_FTDLL_DCACHE_TAG_MASK (0x7F << CFCR_FTDLL_DCACHE_TAG_OFFS) -+#define CFCR_FTDLL_OVERWRITE_ENABLE (1 << 15) -+/* For Orion 2 D2 only */ -+#define CFCR_MRVL_CPU_ID_OFFS 16 -+#define CFCR_MRVL_CPU_ID_MASK (0x1 << CFCR_MRVL_CPU_ID_OFFS) -+#define CFCR_ARM_CPU_ID (0x0 << CFCR_MRVL_CPU_ID_OFFS) -+#define CFCR_MRVL_CPU_ID (0x1 << CFCR_MRVL_CPU_ID_OFFS) -+#define CFCR_VFP_SUB_ARC_NUM_OFFS 7 -+#define CFCR_VFP_SUB_ARC_NUM_MASK (0x1 << CFCR_VFP_SUB_ARC_NUM_OFFS) -+#define CFCR_VFP_SUB_ARC_NUM_1 (0x0 << CFCR_VFP_SUB_ARC_NUM_OFFS) -+#define CFCR_VFP_SUB_ARC_NUM_2 (0x1 << CFCR_VFP_SUB_ARC_NUM_OFFS) -+ -+/* CPU_L2_CONFIG_REG fields */ -+#ifdef MV_CPU_LE -+#define CL2CR_L2_ECC_EN_OFFS 2 -+#define CL2CR_L2_WT_MODE_OFFS 4 -+#else -+#define CL2CR_L2_ECC_EN_OFFS 26 -+#define CL2CR_L2_WT_MODE_OFFS 28 -+#endif -+ -+#define CL2CR_L2_ECC_EN_MASK (1 << CL2CR_L2_ECC_EN_OFFS) -+#define CL2CR_L2_WT_MODE_MASK (1 << CL2CR_L2_WT_MODE_OFFS) -+ -+/*******************************************/ -+/* Main Interrupt Controller Registers Map */ -+/*******************************************/ -+ -+#define CPU_MAIN_INT_CAUSE_REG 0x20200 -+#define CPU_MAIN_IRQ_MASK_REG 0x20204 -+#define CPU_MAIN_FIQ_MASK_REG 0x20208 -+#define CPU_ENPOINT_MASK_REG 0x2020C -+#define CPU_MAIN_INT_CAUSE_HIGH_REG 0x20210 -+#define CPU_MAIN_IRQ_MASK_HIGH_REG 0x20214 -+#define CPU_MAIN_FIQ_MASK_HIGH_REG 0x20218 -+#define CPU_ENPOINT_MASK_HIGH_REG 0x2021C -+ -+ -+/*******************************************/ -+/* ARM Doorbell Registers Map */ -+/*******************************************/ -+ -+#define CPU_HOST_TO_ARM_DRBL_REG 0x20400 -+#define CPU_HOST_TO_ARM_MASK_REG 0x20404 -+#define CPU_ARM_TO_HOST_DRBL_REG 0x20408 -+#define CPU_ARM_TO_HOST_MASK_REG 0x2040C -+ -+ -+ -+/* CPU control register map */ -+/* Set bits means value is about to change according to new value */ -+#define CPU_CONFIG_DEFAULT_MASK (CCR_VEC_INIT_LOC_MASK | CCR_AHB_ERROR_PROP_MASK) -+ -+#define CPU_CONFIG_DEFAULT (CCR_VEC_INIT_LOC_FF00) -+ -+/* CPU Control and status defaults */ -+#define CPU_CTRL_STAT_DEFAULT_MASK (CCSR_PCI_ACCESS_MASK) -+ -+ -+#define CPU_CTRL_STAT_DEFAULT (CCSR_PCI_ACCESS_ENABLE) -+ -+#endif /* __INCmvCpuIfRegsh */ -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,324 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#include "mvSysAudio.h" -+ -+/******************************************************************************* -+* mvAudioWinSet - Set AUDIO target address window -+* -+* DESCRIPTION: -+* This function sets a peripheral target (e.g. SDRAM bank0, PCI_MEM0) -+* address window, also known as address decode window. -+* After setting this target window, the AUDIO will be able to access the -+* target within the address window. -+* -+* INPUT: -+* winNum - AUDIO target address decode window number. -+* pAddrDecWin - AUDIO target window data structure. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR if address window overlapps with other address decode windows. -+* MV_BAD_PARAM if base address is invalid parameter or target is -+* unknown. -+* -+*******************************************************************************/ -+MV_STATUS mvAudioWinSet(MV_U32 winNum, MV_AUDIO_DEC_WIN *pAddrDecWin) -+{ -+ MV_TARGET_ATTRIB targetAttribs; -+ MV_DEC_REGS decRegs; -+ -+ /* Parameter checking */ -+ if (winNum >= MV_AUDIO_MAX_ADDR_DECODE_WIN) -+ { -+ mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvAudioWinSet:Error setting AUDIO window %d to "\ -+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, -+ mvCtrlTargetNameGet(pAddrDecWin->target), -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ decRegs.baseReg = 0; -+ decRegs.sizeReg = 0; -+ -+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) -+ { -+ mvOsPrintf("%s: mvCtrlAddrDecToReg Failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); -+ -+ /* set attributes */ -+ decRegs.sizeReg &= ~MV_AUDIO_WIN_ATTR_MASK; -+ decRegs.sizeReg |= (targetAttribs.attrib << MV_AUDIO_WIN_ATTR_OFFSET); -+ -+ /* set target ID */ -+ decRegs.sizeReg &= ~MV_AUDIO_WIN_TARGET_MASK; -+ decRegs.sizeReg |= (targetAttribs.targetId << MV_AUDIO_WIN_TARGET_OFFSET); -+ -+ if (pAddrDecWin->enable == MV_TRUE) -+ { -+ decRegs.sizeReg |= MV_AUDIO_WIN_ENABLE_MASK; -+ } -+ else -+ { -+ decRegs.sizeReg &= ~MV_AUDIO_WIN_ENABLE_MASK; -+ } -+ -+ MV_REG_WRITE( MV_AUDIO_WIN_CTRL_REG(winNum), decRegs.sizeReg); -+ MV_REG_WRITE( MV_AUDIO_WIN_BASE_REG(winNum), decRegs.baseReg); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvAudioWinGet - Get AUDIO peripheral target address window. -+* -+* DESCRIPTION: -+* Get AUDIO peripheral target address window. -+* -+* INPUT: -+* winNum - AUDIO target address decode window number. -+* -+* OUTPUT: -+* pAddrDecWin - AUDIO target window data structure. -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvAudioWinGet(MV_U32 winNum, MV_AUDIO_DEC_WIN *pAddrDecWin) -+{ -+ MV_DEC_REGS decRegs; -+ MV_TARGET_ATTRIB targetAttrib; -+ -+ /* Parameter checking */ -+ if (winNum >= MV_AUDIO_MAX_ADDR_DECODE_WIN) -+ { -+ mvOsPrintf("%s : ERR. Invalid winNum %d\n", -+ __FUNCTION__, winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ decRegs.baseReg = MV_REG_READ( MV_AUDIO_WIN_BASE_REG(winNum) ); -+ decRegs.sizeReg = MV_REG_READ( MV_AUDIO_WIN_CTRL_REG(winNum) ); -+ -+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs, &pAddrDecWin->addrWin) ) -+ { -+ mvOsPrintf("%s: mvCtrlRegToAddrDec Failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ /* attrib and targetId */ -+ targetAttrib.attrib = (decRegs.sizeReg & MV_AUDIO_WIN_ATTR_MASK) >> -+ MV_AUDIO_WIN_ATTR_OFFSET; -+ targetAttrib.targetId = (decRegs.sizeReg & MV_AUDIO_WIN_TARGET_MASK) >> -+ MV_AUDIO_WIN_TARGET_OFFSET; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ /* Check if window is enabled */ -+ if(decRegs.sizeReg & MV_AUDIO_WIN_ENABLE_MASK) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ } -+ return MV_OK; -+} -+/******************************************************************************* -+* mvAudioAddrDecShow - Print the AUDIO address decode map. -+* -+* DESCRIPTION: -+* This function print the AUDIO address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvAudioAddrDecShow(MV_VOID) -+{ -+ -+ MV_AUDIO_DEC_WIN win; -+ int i; -+ -+ if (MV_FALSE == mvCtrlPwrClckGet(AUDIO_UNIT_ID, 0)) -+ return; -+ -+ -+ mvOsOutput( "\n" ); -+ mvOsOutput( "AUDIO:\n" ); -+ mvOsOutput( "----\n" ); -+ -+ for( i = 0; i < MV_AUDIO_MAX_ADDR_DECODE_WIN; i++ ) -+ { -+ memset( &win, 0, sizeof(MV_AUDIO_DEC_WIN) ); -+ -+ mvOsOutput( "win%d - ", i ); -+ -+ if( mvAudioWinGet( i, &win ) == MV_OK ) -+ { -+ if( win.enable ) -+ { -+ mvOsOutput( "%s base %08x, ", -+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); -+ mvOsOutput( "...." ); -+ -+ mvSizePrint( win.addrWin.size ); -+ -+ mvOsOutput( "\n" ); -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ } -+ } -+} -+ -+ -+/******************************************************************************* -+* mvAudioWinInit - Initialize the integrated AUDIO target address window. -+* -+* DESCRIPTION: -+* Initialize the AUDIO peripheral target address window. -+* -+* INPUT: -+* -+* -+* OUTPUT: -+* -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvAudioInit(MV_VOID) -+{ -+ int winNum; -+ MV_AUDIO_DEC_WIN audioWin; -+ MV_CPU_DEC_WIN cpuAddrDecWin; -+ MV_U32 status; -+ -+ mvAudioHalInit(); -+ -+ /* Initiate Audio address decode */ -+ -+ /* First disable all address decode windows */ -+ for(winNum = 0; winNum < MV_AUDIO_MAX_ADDR_DECODE_WIN; winNum++) -+ { -+ MV_U32 regVal = MV_REG_READ(MV_AUDIO_WIN_CTRL_REG(winNum)); -+ regVal &= ~MV_AUDIO_WIN_ENABLE_MASK; -+ MV_REG_WRITE(MV_AUDIO_WIN_CTRL_REG(winNum), regVal); -+ } -+ -+ for(winNum = 0; winNum < MV_AUDIO_MAX_ADDR_DECODE_WIN; winNum++) -+ { -+ -+ /* We will set the Window to DRAM_CS0 in default */ -+ /* first get attributes from CPU If */ -+ status = mvCpuIfTargetWinGet(SDRAM_CS0, -+ &cpuAddrDecWin); -+ -+ if (MV_OK != status) -+ { -+ mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ if (cpuAddrDecWin.enable == MV_TRUE) -+ { -+ audioWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; -+ audioWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; -+ audioWin.addrWin.size = cpuAddrDecWin.addrWin.size; -+ audioWin.enable = MV_TRUE; -+ audioWin.target = SDRAM_CS0; -+ -+ if(MV_OK != mvAudioWinSet(winNum, &audioWin)) -+ { -+ return MV_ERROR; -+ } -+ } -+ } -+ -+ return MV_OK; -+} -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,123 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#ifndef __INCMVSysAudioH -+#define __INCMVSysAudioH -+ -+#include "mvCommon.h" -+#include "audio/mvAudio.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+ -+/***********************************/ -+/* Audio Address Decoding registers*/ -+/***********************************/ -+ -+#define MV_AUDIO_MAX_ADDR_DECODE_WIN 2 -+#define MV_AUDIO_RECORD_WIN_NUM 0 -+#define MV_AUDIO_PLAYBACK_WIN_NUM 1 -+ -+#define MV_AUDIO_WIN_CTRL_REG(win) (AUDIO_REG_BASE + 0xA04 + ((win)<<3)) -+#define MV_AUDIO_WIN_BASE_REG(win) (AUDIO_REG_BASE + 0xA00 + ((win)<<3)) -+ -+#define MV_AUDIO_RECORD_WIN_CTRL_REG MV_AUDIO_WIN_CTRL_REG(MV_AUDIO_RECORD_WIN_NUM) -+#define MV_AUDIO_RECORD_WIN_BASE_REG MV_AUDIO_WIN_BASE_REG(MV_AUDIO_RECORD_WIN_NUM) -+#define MV_AUDIO_PLAYBACK_WIN_CTRL_REG MV_AUDIO_WIN_CTRL_REG(MV_AUDIO_PLAYBACK_WIN_NUM) -+#define MV_AUDIO_PLAYBACK_WIN_BASE_REG MV_AUDIO_WIN_BASE_REG(MV_AUDIO_PLAYBACK_WIN_NUM) -+ -+ -+/* BITs in Windows 0-3 Control and Base Registers */ -+#define MV_AUDIO_WIN_ENABLE_BIT 0 -+#define MV_AUDIO_WIN_ENABLE_MASK (1<= 2) -+MV_TARGET tdmaAddrDecPrioTable[] = -+{ -+#if defined(MV_INCLUDE_SDRAM_CS0) -+ SDRAM_CS0, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS1) -+ SDRAM_CS1, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS2) -+ SDRAM_CS2, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS3) -+ SDRAM_CS3, -+#endif -+#if defined(MV_INCLUDE_PEX) -+ PEX0_MEM, -+#endif -+ -+ TBL_TERM -+}; -+ -+/******************************************************************************* -+* mvCesaWinGet - Get TDMA target address window. -+* -+* DESCRIPTION: -+* Get TDMA target address window. -+* -+* INPUT: -+* winNum - TDMA target address decode window number. -+* -+* OUTPUT: -+* pDecWin - TDMA target window data structure. -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+static MV_STATUS mvCesaWinGet(MV_U32 winNum, MV_DEC_WIN *pDecWin) -+{ -+ MV_DEC_WIN_PARAMS winParam; -+ MV_U32 sizeReg, baseReg; -+ -+ /* Parameter checking */ -+ if (winNum >= MV_CESA_TDMA_ADDR_DEC_WIN) -+ { -+ mvOsPrintf("%s : ERR. Invalid winNum %d\n", -+ __FUNCTION__, winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ baseReg = MV_REG_READ( MV_CESA_TDMA_BASE_ADDR_REG(winNum) ); -+ sizeReg = MV_REG_READ( MV_CESA_TDMA_WIN_CTRL_REG(winNum) ); -+ -+ /* Check if window is enabled */ -+ if(sizeReg & MV_CESA_TDMA_WIN_ENABLE_MASK) -+ { -+ pDecWin->enable = MV_TRUE; -+ -+ /* Extract window parameters from registers */ -+ winParam.targetId = (sizeReg & MV_CESA_TDMA_WIN_TARGET_MASK) >> MV_CESA_TDMA_WIN_TARGET_OFFSET; -+ winParam.attrib = (sizeReg & MV_CESA_TDMA_WIN_ATTR_MASK) >> MV_CESA_TDMA_WIN_ATTR_OFFSET; -+ winParam.size = (sizeReg & MV_CESA_TDMA_WIN_SIZE_MASK) >> MV_CESA_TDMA_WIN_SIZE_OFFSET; -+ winParam.baseAddr = (baseReg & MV_CESA_TDMA_WIN_BASE_MASK); -+ -+ /* Translate the decode window parameters to address decode struct */ -+ if (MV_OK != mvCtrlParamsToAddrDec(&winParam, pDecWin)) -+ { -+ mvOsPrintf("Failed to translate register parameters to CESA address" \ -+ " decode window structure\n"); -+ return MV_ERROR; -+ } -+ } -+ else -+ { -+ pDecWin->enable = MV_FALSE; -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* cesaWinOverlapDetect - Detect CESA TDMA address windows overlapping -+* -+* DESCRIPTION: -+* An unpredicted behaviur is expected in case TDMA address decode -+* windows overlapps. -+* This function detects TDMA address decode windows overlapping of a -+* specified window. The function does not check the window itself for -+* overlapping. The function also skipps disabled address decode windows. -+* -+* INPUT: -+* winNum - address decode window number. -+* pAddrDecWin - An address decode window struct. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE - if the given address window overlap current address -+* decode map, -+* MV_FALSE - otherwise, MV_ERROR if reading invalid data -+* from registers. -+* -+*******************************************************************************/ -+static MV_STATUS cesaWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 winNumIndex; -+ MV_DEC_WIN addrDecWin; -+ -+ for(winNumIndex=0; winNumIndex= MV_CESA_TDMA_ADDR_DEC_WIN) -+ { -+ mvOsPrintf("mvCesaTdmaWinSet: ERR. Invalid win num %d\n",winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlapps with current windows */ -+ if (MV_TRUE == cesaWinOverlapDetect(winNum, &pDecWin->addrWin)) -+ { -+ mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); -+ return MV_ERROR; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pDecWin->addrWin.baseLow, pDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvCesaTdmaWinSet: Error setting CESA TDMA window %d to "\ -+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, -+ mvCtrlTargetNameGet(pDecWin->target), -+ pDecWin->addrWin.baseLow, -+ pDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ if(MV_OK != mvCtrlAddrDecToParams(pDecWin, &winParams)) -+ { -+ mvOsPrintf("%s: mvCtrlAddrDecToParams Failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ /* set Size, Attributes and TargetID */ -+ sizeReg = (((winParams.targetId << MV_CESA_TDMA_WIN_TARGET_OFFSET) & MV_CESA_TDMA_WIN_TARGET_MASK) | -+ ((winParams.attrib << MV_CESA_TDMA_WIN_ATTR_OFFSET) & MV_CESA_TDMA_WIN_ATTR_MASK) | -+ ((winParams.size << MV_CESA_TDMA_WIN_SIZE_OFFSET) & MV_CESA_TDMA_WIN_SIZE_MASK)); -+ -+ if (pDecWin->enable == MV_TRUE) -+ { -+ sizeReg |= MV_CESA_TDMA_WIN_ENABLE_MASK; -+ } -+ else -+ { -+ sizeReg &= ~MV_CESA_TDMA_WIN_ENABLE_MASK; -+ } -+ -+ /* Update Base value */ -+ baseReg = (winParams.baseAddr & MV_CESA_TDMA_WIN_BASE_MASK); -+ -+ MV_REG_WRITE( MV_CESA_TDMA_WIN_CTRL_REG(winNum), sizeReg); -+ MV_REG_WRITE( MV_CESA_TDMA_BASE_ADDR_REG(winNum), baseReg); -+ -+ return MV_OK; -+} -+ -+ -+static MV_STATUS mvCesaTdmaAddrDecInit (void) -+{ -+ MV_U32 winNum; -+ MV_STATUS status; -+ MV_CPU_DEC_WIN cpuAddrDecWin; -+ MV_DEC_WIN cesaWin; -+ MV_U32 winPrioIndex = 0; -+ -+ /* First disable all address decode windows */ -+ for(winNum=0; winNum= 2 */ -+ -+ -+ -+ -+MV_STATUS mvCesaInit (int numOfSession, int queueDepth, char* pSramBase, void *osHandle) -+{ -+ MV_U32 cesaCryptEngBase; -+ MV_CPU_DEC_WIN addrDecWin; -+ -+ if(sizeof(MV_CESA_SRAM_MAP) > MV_CESA_SRAM_SIZE) -+ { -+ mvOsPrintf("mvCesaInit: Wrong SRAM map - %ld > %d\n", -+ sizeof(MV_CESA_SRAM_MAP), MV_CESA_SRAM_SIZE); -+ return MV_FAIL; -+ } -+#if 0 -+ if (mvCpuIfTargetWinGet(CRYPT_ENG, &addrDecWin) == MV_OK) -+ cesaCryptEngBase = addrDecWin.addrWin.baseLow; -+ else -+ { -+ mvOsPrintf("mvCesaInit: ERR. mvCpuIfTargetWinGet failed\n"); -+ return MV_ERROR; -+ } -+#else -+ cesaCryptEngBase = (MV_U32)pSramBase; -+#endif -+ -+#if 0 /* Already done in the platform init */ -+#if (MV_CESA_VERSION >= 2) -+ mvCesaTdmaAddrDecInit(); -+#endif /* MV_CESA_VERSION >= 2 */ -+#endif -+ return mvCesaHalInit(numOfSession, queueDepth, pSramBase, cesaCryptEngBase, -+ osHandle); -+ -+} -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,100 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __mvSysCesa_h__ -+#define __mvSysCesa_h__ -+ -+ -+#include "mvCommon.h" -+#include "cesa/mvCesa.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+ -+/***************************** TDMA Registers *************************************/ -+ -+#define MV_CESA_TDMA_ADDR_DEC_WIN 4 -+ -+#define MV_CESA_TDMA_BASE_ADDR_REG(win) (MV_CESA_TDMA_REG_BASE + 0xa00 + (win<<3)) -+ -+#define MV_CESA_TDMA_WIN_CTRL_REG(win) (MV_CESA_TDMA_REG_BASE + 0xa04 + (win<<3)) -+ -+#define MV_CESA_TDMA_WIN_ENABLE_BIT 0 -+#define MV_CESA_TDMA_WIN_ENABLE_MASK (1 << MV_CESA_TDMA_WIN_ENABLE_BIT) -+ -+#define MV_CESA_TDMA_WIN_TARGET_OFFSET 4 -+#define MV_CESA_TDMA_WIN_TARGET_MASK (0xf << MV_CESA_TDMA_WIN_TARGET_OFFSET) -+ -+#define MV_CESA_TDMA_WIN_ATTR_OFFSET 8 -+#define MV_CESA_TDMA_WIN_ATTR_MASK (0xff << MV_CESA_TDMA_WIN_ATTR_OFFSET) -+ -+#define MV_CESA_TDMA_WIN_SIZE_OFFSET 16 -+#define MV_CESA_TDMA_WIN_SIZE_MASK (0xFFFF << MV_CESA_TDMA_WIN_SIZE_OFFSET) -+ -+#define MV_CESA_TDMA_WIN_BASE_OFFSET 16 -+#define MV_CESA_TDMA_WIN_BASE_MASK (0xFFFF << MV_CESA_TDMA_WIN_BASE_OFFSET) -+ -+ -+MV_STATUS mvCesaInit (int numOfSession, int queueDepth, char* pSramBase, void *osHandle); -+ -+#endif -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.c ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.c 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,348 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+/* includes */ -+ -+#include "ddr2/mvDramIf.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+#include "ctrlEnv/sys/mvSysDram.h" -+ -+/* #define MV_DEBUG */ -+#ifdef MV_DEBUG -+#define DB(x) x -+#else -+#define DB(x) -+#endif -+ -+static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin); -+ -+/******************************************************************************* -+* mvDramIfWinSet - Set DRAM interface address decode window -+* -+* DESCRIPTION: -+* This function sets DRAM interface address decode window. -+* -+* INPUT: -+* target - System target. Use only SDRAM targets. -+* pAddrDecWin - SDRAM address window structure. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK -+* otherwise. -+*******************************************************************************/ -+MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) -+{ -+ MV_U32 baseReg=0,sizeReg=0; -+ MV_U32 baseToReg=0 , sizeToReg=0; -+ -+ /* Check parameters */ -+ if (!MV_TARGET_IS_DRAM(target)) -+ { -+ mvOsPrintf("mvDramIfWinSet: target %d is not SDRAM\n", target); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlaps with current enabled windows */ -+ if (MV_TRUE == sdramIfWinOverlap(target, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("mvDramIfWinSet: ERR. Target %d overlaps\n", target); -+ return MV_BAD_PARAM; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvDramIfWinSet:Error setting DRAM interface window %d."\ -+ "\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ target, -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ /* read base register*/ -+ baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(0,target)); -+ -+ /* read size register */ -+ sizeReg = MV_REG_READ(SDRAM_SIZE_REG(0,target)); -+ -+ /* BaseLow[31:16] => base register [31:16] */ -+ baseToReg = pAddrDecWin->addrWin.baseLow & SCBAR_BASE_MASK; -+ -+ /* Write to address decode Base Address Register */ -+ baseReg &= ~SCBAR_BASE_MASK; -+ baseReg |= baseToReg; -+ -+ /* Translate the given window size to register format */ -+ sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, SCSR_SIZE_ALIGNMENT); -+ -+ /* Size parameter validity check. */ -+ if (-1 == sizeToReg) -+ { -+ mvOsPrintf("mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n",target); -+ return MV_BAD_PARAM; -+ } -+ -+ /* set size */ -+ sizeReg &= ~SCSR_SIZE_MASK; -+ /* Size is located at upper 16 bits */ -+ sizeReg |= (sizeToReg << SCSR_SIZE_OFFS); -+ -+ /* enable/Disable */ -+ if (MV_TRUE == pAddrDecWin->enable) -+ { -+ sizeReg |= SCSR_WIN_EN; -+ } -+ else -+ { -+ sizeReg &= ~SCSR_WIN_EN; -+ } -+ -+ /* 3) Write to address decode Base Address Register */ -+ MV_REG_WRITE(SDRAM_BASE_ADDR_REG(0,target), baseReg); -+ -+ /* Write to address decode Size Register */ -+ MV_REG_WRITE(SDRAM_SIZE_REG(0,target), sizeReg); -+ -+ return MV_OK; -+} -+/******************************************************************************* -+* mvDramIfWinGet - Get DRAM interface address decode window -+* -+* DESCRIPTION: -+* This function gets DRAM interface address decode window. -+* -+* INPUT: -+* target - System target. Use only SDRAM targets. -+* -+* OUTPUT: -+* pAddrDecWin - SDRAM address window structure. -+* -+* RETURN: -+* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK -+* otherwise. -+*******************************************************************************/ -+MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) -+{ -+ MV_U32 baseReg,sizeReg; -+ MV_U32 sizeRegVal; -+ /* Check parameters */ -+ if (!MV_TARGET_IS_DRAM(target)) -+ { -+ mvOsPrintf("mvDramIfWinGet: target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ /* Read base and size registers */ -+ sizeReg = MV_REG_READ(SDRAM_SIZE_REG(0,target)); -+ baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(0,target)); -+ -+ sizeRegVal = (sizeReg & SCSR_SIZE_MASK) >> SCSR_SIZE_OFFS; -+ -+ pAddrDecWin->addrWin.size = ctrlRegToSize(sizeRegVal, -+ SCSR_SIZE_ALIGNMENT); -+ -+ /* Check if ctrlRegToSize returned OK */ -+ if (-1 == pAddrDecWin->addrWin.size) -+ { -+ mvOsPrintf("mvDramIfWinGet: size of target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ /* Extract base address */ -+ /* Base register [31:16] ==> baseLow[31:16] */ -+ pAddrDecWin->addrWin.baseLow = baseReg & SCBAR_BASE_MASK; -+ -+ pAddrDecWin->addrWin.baseHigh = 0; -+ -+ -+ if (sizeReg & SCSR_WIN_EN) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ } -+ -+ return MV_OK; -+} -+/******************************************************************************* -+* mvDramIfWinEnable - Enable/Disable SDRAM address decode window -+* -+* DESCRIPTION: -+* This function enable/Disable SDRAM address decode window. -+* -+* INPUT: -+* target - System target. Use only SDRAM targets. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR in case function parameter are invalid, MV_OK otherewise. -+* -+*******************************************************************************/ -+MV_STATUS mvDramIfWinEnable(MV_TARGET target, MV_BOOL enable) -+{ -+ MV_DRAM_DEC_WIN addrDecWin; -+ -+ /* Check parameters */ -+ if (!MV_TARGET_IS_DRAM(target)) -+ { -+ mvOsPrintf("mvDramIfWinEnable: target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ if (enable == MV_TRUE) -+ { /* First check for overlap with other enabled windows */ -+ if (MV_OK != mvDramIfWinGet(target, &addrDecWin)) -+ { -+ mvOsPrintf("mvDramIfWinEnable:ERR. Getting target %d failed.\n", -+ target); -+ return MV_ERROR; -+ } -+ /* Check for overlapping */ -+ if (MV_FALSE == sdramIfWinOverlap(target, &(addrDecWin.addrWin))) -+ { -+ /* No Overlap. Enable address decode winNum window */ -+ MV_REG_BIT_SET(SDRAM_SIZE_REG(0,target), SCSR_WIN_EN); -+ } -+ else -+ { /* Overlap detected */ -+ mvOsPrintf("mvDramIfWinEnable: ERR. Target %d overlap detect\n", -+ target); -+ return MV_ERROR; -+ } -+ } -+ else -+ { /* Disable address decode winNum window */ -+ MV_REG_BIT_RESET(SDRAM_SIZE_REG(0, target), SCSR_WIN_EN); -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* sdramIfWinOverlap - Check if an address window overlap an SDRAM address window -+* -+* DESCRIPTION: -+* This function scan each SDRAM address decode window to test if it -+* overlapps the given address windoow -+* -+* INPUT: -+* target - SDRAM target where the function skips checking. -+* pAddrDecWin - The tested address window for overlapping with -+* SDRAM windows. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlaps any enabled address -+* decode map, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_TARGET targetNum; -+ MV_DRAM_DEC_WIN addrDecWin; -+ -+ for(targetNum = SDRAM_CS0; targetNum < MV_DRAM_MAX_CS ; targetNum++) -+ { -+ /* don't check our winNum or illegal targets */ -+ if (targetNum == target) -+ { -+ continue; -+ } -+ -+ /* Get window parameters */ -+ if (MV_OK != mvDramIfWinGet(targetNum, &addrDecWin)) -+ { -+ mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); -+ return MV_ERROR; -+ } -+ -+ /* Do not check disabled windows */ -+ if (MV_FALSE == addrDecWin.enable) -+ { -+ continue; -+ } -+ -+ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) -+ { -+ mvOsPrintf( -+ "sdramIfWinOverlap: Required target %d overlap winNum %d\n", -+ target, targetNum); -+ return MV_TRUE; -+ } -+ } -+ -+ return MV_FALSE; -+} -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,80 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __sysDram -+#define __sysDram -+ -+/* This structure describes CPU interface address decode window */ -+typedef struct _mvDramIfDecWin -+{ -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+}MV_DRAM_DEC_WIN; -+ -+MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); -+MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); -+MV_STATUS mvDramIfWinEnable(MV_TARGET target, MV_BOOL enable); -+ -+#endif -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,658 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#include "ctrlEnv/sys/mvSysGbe.h" -+ -+ -+ -+typedef struct _mvEthDecWin -+{ -+ MV_TARGET target; -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+}MV_ETH_DEC_WIN; -+ -+MV_TARGET ethAddrDecPrioTap[] = -+{ -+#if defined(MV_INCLUDE_SDRAM_CS0) -+ SDRAM_CS0, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS1) -+ SDRAM_CS1, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS2) -+ SDRAM_CS2, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS3) -+ SDRAM_CS3, -+#endif -+#if defined(MV_INCLUDE_DEVICE_CS0) -+ DEVICE_CS0, -+#endif -+#if defined(MV_INCLUDE_DEVICE_CS1) -+ DEVICE_CS1, -+#endif -+#if defined(MV_INCLUDE_DEVICE_CS2) -+ DEVICE_CS2, -+#endif -+#if defined(MV_INCLUDE_DEVICE_CS3) -+ DEVICE_CS3, -+#endif -+#if defined(MV_INCLUDE_PEX) -+ PEX0_IO, -+#endif -+ TBL_TERM -+}; -+ -+static MV_STATUS ethWinOverlapDetect(int port, MV_U32 winNum, MV_ADDR_WIN *pAddrWin); -+static MV_STATUS mvEthWinSet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin); -+static MV_STATUS mvEthWinGet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin); -+ -+ -+/******************************************************************************* -+* mvEthWinInit - Initialize ETH address decode windows -+* -+* DESCRIPTION: -+* This function initialize ETH window decode unit. It set the -+* default address decode windows of the unit. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR if setting fail. -+*******************************************************************************/ -+/* Configure EthDrv memory map registes. */ -+MV_STATUS mvEthWinInit (int port) -+{ -+ MV_U32 winNum, status, winPrioIndex=0, i, regVal=0; -+ MV_ETH_DEC_WIN ethWin; -+ MV_CPU_DEC_WIN cpuAddrDecWin; -+ static MV_U32 accessProtReg = 0; -+ -+#if (MV_ETH_VERSION <= 1) -+ static MV_BOOL isFirst = MV_TRUE; -+ -+ if(isFirst == MV_FALSE) -+ { -+ MV_REG_WRITE(ETH_ACCESS_PROTECT_REG(port), accessProtReg); -+ return MV_OK; -+ } -+ isFirst = MV_FALSE; -+#endif /* MV_GIGA_ETH_VERSION */ -+ -+ /* Initiate Ethernet address decode */ -+ -+ /* First disable all address decode windows */ -+ for(winNum=0; winNum= ETH_MAX_DECODE_WIN) -+ { -+ mvOsPrintf("mvEthWinSet: ERR. Invalid win num %d\n",winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlapps with current windows */ -+ if (MV_TRUE == ethWinOverlapDetect(port, winNum, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("mvEthWinSet: ERR. Window %d overlap\n", winNum); -+ return MV_ERROR; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvEthWinSet: Error setting Ethernet window %d to "\ -+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, -+ mvCtrlTargetNameGet(pAddrDecWin->target), -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ -+ decRegs.baseReg = MV_REG_READ(ETH_WIN_BASE_REG(port, winNum)); -+ decRegs.sizeReg = MV_REG_READ(ETH_WIN_SIZE_REG(port, winNum)); -+ -+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) -+ { -+ mvOsPrintf("mvEthWinSet:mvCtrlAddrDecToReg Failed\n"); -+ return MV_ERROR; -+ } -+ -+ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); -+ -+ /* set attributes */ -+ decRegs.baseReg &= ~ETH_WIN_ATTR_MASK; -+ decRegs.baseReg |= targetAttribs.attrib << ETH_WIN_ATTR_OFFS; -+ /* set target ID */ -+ decRegs.baseReg &= ~ETH_WIN_TARGET_MASK; -+ decRegs.baseReg |= targetAttribs.targetId << ETH_WIN_TARGET_OFFS; -+ -+ /* for the safe side we disable the window before writing the new -+ values */ -+ mvEthWinEnable(port, winNum, MV_FALSE); -+ MV_REG_WRITE(ETH_WIN_BASE_REG(port, winNum), decRegs.baseReg); -+ -+ /* Write to address decode Size Register */ -+ MV_REG_WRITE(ETH_WIN_SIZE_REG(port, winNum), decRegs.sizeReg); -+ -+ /* Enable address decode target window */ -+ if (pAddrDecWin->enable == MV_TRUE) -+ { -+ mvEthWinEnable(port, winNum, MV_TRUE); -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvETHWinGet - Get dma peripheral target address window. -+* -+* DESCRIPTION: -+* Get ETH peripheral target address window. -+* -+* INPUT: -+* winNum - ETH to target address decode window number. -+* -+* OUTPUT: -+* pAddrDecWin - ETH target window data structure. -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvEthWinGet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin) -+{ -+ MV_DEC_REGS decRegs; -+ MV_TARGET_ATTRIB targetAttrib; -+ -+ /* Parameter checking */ -+ if (winNum >= ETH_MAX_DECODE_WIN) -+ { -+ mvOsPrintf("mvEthWinGet: ERR. Invalid winNum %d\n", winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ decRegs.baseReg = MV_REG_READ(ETH_WIN_BASE_REG(port, winNum)); -+ decRegs.sizeReg = MV_REG_READ(ETH_WIN_SIZE_REG(port, winNum)); -+ -+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) -+ { -+ mvOsPrintf("mvAhbToMbusWinGet: mvCtrlRegToAddrDec Failed \n"); -+ return MV_ERROR; -+ } -+ -+ /* attrib and targetId */ -+ targetAttrib.attrib = -+ (decRegs.baseReg & ETH_WIN_ATTR_MASK) >> ETH_WIN_ATTR_OFFS; -+ targetAttrib.targetId = -+ (decRegs.baseReg & ETH_WIN_TARGET_MASK) >> ETH_WIN_TARGET_OFFS; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ /* Check if window is enabled */ -+ if (~(MV_REG_READ(ETH_BASE_ADDR_ENABLE_REG(port))) & (1 << winNum) ) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthWinEnable - Enable/disable a ETH to target address window -+* -+* DESCRIPTION: -+* This function enable/disable a ETH to target address window. -+* According to parameter 'enable' the routine will enable the -+* window, thus enabling ETH accesses (before enabling the window it is -+* tested for overlapping). Otherwise, the window will be disabled. -+* -+* INPUT: -+* winNum - ETH to target address decode window number. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_ERROR if decode window number was wrong or enabled window overlapps. -+* -+*******************************************************************************/ -+MV_STATUS mvEthWinEnable(int port, MV_U32 winNum,MV_BOOL enable) -+{ -+ MV_ETH_DEC_WIN addrDecWin; -+ -+ /* Parameter checking */ -+ if (winNum >= ETH_MAX_DECODE_WIN) -+ { -+ mvOsPrintf("mvEthTargetWinEnable:ERR. Invalid winNum%d\n",winNum); -+ return MV_ERROR; -+ } -+ -+ if (enable == MV_TRUE) -+ { /* First check for overlap with other enabled windows */ -+ /* Get current window */ -+ if (MV_OK != mvEthWinGet(port, winNum, &addrDecWin)) -+ { -+ mvOsPrintf("mvEthTargetWinEnable:ERR. targetWinGet fail\n"); -+ return MV_ERROR; -+ } -+ /* Check for overlapping */ -+ if (MV_FALSE == ethWinOverlapDetect(port, winNum, &(addrDecWin.addrWin))) -+ { -+ /* No Overlap. Enable address decode target window */ -+ MV_REG_BIT_RESET(ETH_BASE_ADDR_ENABLE_REG(port), (1 << winNum)); -+ } -+ else -+ { /* Overlap detected */ -+ mvOsPrintf("mvEthTargetWinEnable:ERR. Overlap detected\n"); -+ return MV_ERROR; -+ } -+ } -+ else -+ { /* Disable address decode target window */ -+ MV_REG_BIT_SET(ETH_BASE_ADDR_ENABLE_REG(port), (1 << winNum)); -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthWinTargetGet - Get Window number associated with target -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+* window number -+* -+*******************************************************************************/ -+MV_U32 mvEthWinTargetGet(int port, MV_TARGET target) -+{ -+ MV_ETH_DEC_WIN decWin; -+ MV_U32 winNum; -+ -+ /* Check parameters */ -+ if (target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetGet: target %d is Illigal\n", target); -+ return 0xffffffff; -+ } -+ -+ for (winNum=0; winNum= mvCtrlEthMaxPortGet()) -+ { -+ mvOsPrintf("mvEthProtWinSet:ERR. Invalid port number %d\n", portNo); -+ return MV_ERROR; -+ } -+ -+ if (winNum >= ETH_MAX_DECODE_WIN) -+ { -+ mvOsPrintf("mvEthProtWinSet:ERR. Invalid winNum%d\n",winNum); -+ return MV_ERROR; -+ } -+ -+ if((access == ACC_RESERVED) || (access >= MAX_ACC_RIGHTS)) -+ { -+ mvOsPrintf("mvEthProtWinSet:ERR. Inv access param %d\n", access); -+ return MV_ERROR; -+ } -+ /* Read current protection register */ -+ protReg = MV_REG_READ(ETH_ACCESS_PROTECT_REG(portNo)); -+ -+ /* Clear protection window field */ -+ protReg &= ~(ETH_PROT_WIN_MASK(winNum)); -+ -+ /* Set new protection field value */ -+ protReg |= (access << (ETH_PROT_WIN_OFFS(winNum))); -+ -+ /* Write protection register back */ -+ MV_REG_WRITE(ETH_ACCESS_PROTECT_REG(portNo), protReg); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* ethWinOverlapDetect - Detect ETH address windows overlapping -+* -+* DESCRIPTION: -+* An unpredicted behaviur is expected in case ETH address decode -+* windows overlapps. -+* This function detects ETH address decode windows overlapping of a -+* specified window. The function does not check the window itself for -+* overlapping. The function also skipps disabled address decode windows. -+* -+* INPUT: -+* winNum - address decode window number. -+* pAddrDecWin - An address decode window struct. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data -+* from registers. -+* -+*******************************************************************************/ -+static MV_STATUS ethWinOverlapDetect(int port, MV_U32 winNum, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 baseAddrEnableReg; -+ MV_U32 winNumIndex; -+ MV_ETH_DEC_WIN addrDecWin; -+ -+ /* Read base address enable register. Do not check disabled windows */ -+ baseAddrEnableReg = MV_REG_READ(ETH_BASE_ADDR_ENABLE_REG(port)); -+ -+ for (winNumIndex=0; winNumIndex= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexInit: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Enabled CPU access to PCI-Express */ -+ mvCpuIfEnablePex(pexIf, pexType); -+ -+ /* Start with bars */ -+ /* First disable all PEX bars*/ -+ for (bar = 0; bar < PEX_MAX_BARS; bar++) -+ { -+ if (PEX_INTER_REGS_BAR != bar) -+ { -+ if (MV_OK != mvPexBarEnable(pexIf, bar, MV_FALSE)) -+ { -+ mvOsPrintf("mvPexInit:mvPexBarEnable bar =%d failed \n",bar); -+ return MV_ERROR; -+ } -+ -+ } -+ -+ } -+ -+ /* and disable all PEX target windows */ -+ for (winNum = 0; winNum < PEX_MAX_TARGET_WIN - 2; winNum++) -+ { -+ if (MV_OK != mvPexTargetWinEnable(pexIf, winNum, MV_FALSE)) -+ { -+ mvOsPrintf("mvPexInit:mvPexTargetWinEnable winNum =%d failed \n", -+ winNum); -+ return MV_ERROR; -+ -+ } -+ } -+ -+ /* Now, go through all bars*/ -+ -+ -+ -+/******************************************************************************/ -+/* Internal registers bar */ -+/******************************************************************************/ -+ bar = PEX_INTER_REGS_BAR; -+ -+ /* we only open the bar , no need to open windows for this bar */ -+ -+ /* first get the CS attribute from the CPU Interface */ -+ if (MV_OK !=mvCpuIfTargetWinGet(INTER_REGS,&addrDecWin)) -+ { -+ mvOsPrintf("mvPexInit: ERR. mvCpuIfTargetWinGet failed target =%d\n",INTER_REGS); -+ return MV_ERROR; -+ } -+ -+ pexBar.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; -+ pexBar.addrWin.baseLow = addrDecWin.addrWin.baseLow; -+ pexBar.addrWin.size = addrDecWin.addrWin.size; -+ pexBar.enable = MV_TRUE; -+ -+ if (MV_OK != mvPexBarSet(pexIf, bar, &pexBar)) -+ { -+ mvOsPrintf("mvPexInit: ERR. mvPexBarSet %d failed\n", bar); -+ return MV_ERROR; -+ } -+ -+/******************************************************************************/ -+/* DRAM bar */ -+/******************************************************************************/ -+ -+ bar = PEX_DRAM_BAR; -+ -+ pexBar.addrWin.size = 0; -+ -+ for (target = SDRAM_CS0;target < MV_DRAM_MAX_CS; target++ ) -+ { -+ -+ status = mvCpuIfTargetWinGet(target,&addrDecWin); -+ -+ if((MV_NO_SUCH == status)&&(target != SDRAM_CS0)) -+ { -+ continue; -+ } -+ -+ /* first get attributes from CPU If */ -+ if (MV_OK != status) -+ { -+ mvOsPrintf("mvPexInit: ERR. mvCpuIfTargetWinGet failed target =%d\n",target); -+ return MV_ERROR; -+ } -+ if (addrDecWin.enable == MV_TRUE) -+ { -+ /* the base is the base of DRAM CS0 always */ -+ if (SDRAM_CS0 == target ) -+ { -+ pexBar.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; -+ pexBar.addrWin.baseLow = addrDecWin.addrWin.baseLow; -+ -+ } -+ -+ /* increment the bar size to be the sum of the size of all -+ DRAM chips selecs */ -+ pexBar.addrWin.size += addrDecWin.addrWin.size; -+ -+ /* set a Pex window for this target ! -+ DRAM CS always will have a Pex Window , and is not a -+ part of the priority table */ -+ pexWin.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; -+ pexWin.addrWin.baseLow = addrDecWin.addrWin.baseLow; -+ pexWin.addrWin.size = addrDecWin.addrWin.size; -+ -+ /* we disable the windows at first because we are not -+ sure that it is witihin bar boundries */ -+ pexWin.enable =MV_FALSE; -+ pexWin.target = target; -+ pexWin.targetBar = bar; -+ -+ if (MV_OK != mvPexTargetWinSet(pexIf,pexCurrWin++,&pexWin)) -+ { -+ mvOsPrintf("mvPexInit: ERR. mvPexTargetWinSet failed\n"); -+ return MV_ERROR; -+ } -+ } -+ } -+ -+ /* check if the size of the bar is illeggal */ -+ if (-1 == ctrlSizeToReg(pexBar.addrWin.size, PXBCR_BAR_SIZE_ALIGNMENT)) -+ { -+ /* try to get a good size */ -+ pexBar.addrWin.size = ctrlSizeRegRoundUp(pexBar.addrWin.size, -+ PXBCR_BAR_SIZE_ALIGNMENT); -+ } -+ -+ /* check if the size and base are valid */ -+ if (MV_TRUE == pexBarOverlapDetect(pexIf,bar,&pexBar.addrWin)) -+ { -+ mvOsPrintf("mvPexInit:Warning :Bar %d size is illigal\n",bar); -+ mvOsPrintf("it will be disabled\n"); -+ mvOsPrintf("please check Pex and CPU windows configuration\n"); -+ } -+ else -+ { -+ pexBar.enable = MV_TRUE; -+ -+ /* configure the bar */ -+ if (MV_OK != mvPexBarSet(pexIf, bar, &pexBar)) -+ { -+ mvOsPrintf("mvPexInit: ERR. mvPexBarSet %d failed\n", bar); -+ return MV_ERROR; -+ } -+ -+ /* after the bar was configured then we enable the Pex windows*/ -+ for (winNum = 0;winNum < pexCurrWin ;winNum++) -+ { -+ if (MV_OK != mvPexTargetWinEnable(pexIf, winNum, MV_TRUE)) -+ { -+ mvOsPrintf("mvPexInit: Can't enable window =%d\n",winNum); -+ return MV_ERROR; -+ } -+ -+ } -+ } -+ -+/******************************************************************************/ -+/* DEVICE bar */ -+/******************************************************************************/ -+ -+/* Open the Device BAR for non linux only */ -+#ifndef MV_DISABLE_PEX_DEVICE_BAR -+ -+ /* then device bar*/ -+ bar = PEX_DEVICE_BAR; -+ -+ /* save the starting window */ -+ pexStartWindow = pexCurrWin; -+ pexBar.addrWin.size = 0; -+ pexBar.addrWin.baseLow = 0xffffffff; -+ pexBar.addrWin.baseHigh = 0; -+ maxBase = 0; -+ -+ for (target = DEV_TO_TARGET(START_DEV_CS);target < DEV_TO_TARGET(MV_DEV_MAX_CS); target++ ) -+ { -+ status = mvCpuIfTargetWinGet(target,&addrDecWin); -+ -+ if (MV_NO_SUCH == status) -+ { -+ continue; -+ } -+ -+ if (MV_OK != status) -+ { -+ mvOsPrintf("mvPexInit: ERR. mvCpuIfTargetWinGet failed target =%d\n",target); -+ return MV_ERROR; -+ } -+ -+ if (addrDecWin.enable == MV_TRUE) -+ { -+ /* get the minimum base */ -+ if (addrDecWin.addrWin.baseLow < pexBar.addrWin.baseLow) -+ { -+ pexBar.addrWin.baseLow = addrDecWin.addrWin.baseLow; -+ } -+ -+ /* get the maximum base */ -+ if (addrDecWin.addrWin.baseLow > maxBase) -+ { -+ maxBase = addrDecWin.addrWin.baseLow; -+ sizeOfMaxBase = addrDecWin.addrWin.size; -+ } -+ -+ /* search in the priority table for this target */ -+ for (winIndex = 0; pexDevBarPrioTable[winIndex] != TBL_TERM; -+ winIndex++) -+ { -+ if (pexDevBarPrioTable[winIndex] != target) -+ { -+ continue; -+ } -+ else if (pexDevBarPrioTable[winIndex] == target) -+ { -+ /*found it */ -+ -+ /* if the index of this target in the prio table is valid -+ then we set the Pex window for this target, a valid index is -+ an index that is lower than the number of the windows that -+ was not configured yet */ -+ -+ /* we subtract 2 always because the default and expantion -+ rom windows are always configured */ -+ if ( pexCurrWin < PEX_MAX_TARGET_WIN - 2) -+ { -+ /* set a Pex window for this target ! */ -+ pexWin.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; -+ pexWin.addrWin.baseLow = addrDecWin.addrWin.baseLow; -+ pexWin.addrWin.size = addrDecWin.addrWin.size; -+ -+ /* we disable the windows at first because we are not -+ sure that it is witihin bar boundries */ -+ pexWin.enable = MV_FALSE; -+ pexWin.target = target; -+ pexWin.targetBar = bar; -+ -+ if (MV_OK != mvPexTargetWinSet(pexIf,pexCurrWin++, -+ &pexWin)) -+ { -+ mvOsPrintf("mvPexInit: ERR. Window Set failed\n"); -+ return MV_ERROR; -+ } -+ } -+ } -+ } -+ } -+ } -+ -+ pexBar.addrWin.size = maxBase - pexBar.addrWin.baseLow + sizeOfMaxBase; -+ pexBar.enable = MV_TRUE; -+ -+ /* check if the size of the bar is illegal */ -+ if (-1 == ctrlSizeToReg(pexBar.addrWin.size, PXBCR_BAR_SIZE_ALIGNMENT)) -+ { -+ /* try to get a good size */ -+ pexBar.addrWin.size = ctrlSizeRegRoundUp(pexBar.addrWin.size, -+ PXBCR_BAR_SIZE_ALIGNMENT); -+ } -+ -+ /* check if the size and base are valid */ -+ if (MV_TRUE == pexBarOverlapDetect(pexIf,bar,&pexBar.addrWin)) -+ { -+ mvOsPrintf("mvPexInit:Warning :Bar %d size is illigal\n",bar); -+ mvOsPrintf("it will be disabled\n"); -+ mvOsPrintf("please check Pex and CPU windows configuration\n"); -+ } -+ else -+ { -+ if (MV_OK != mvPexBarSet(pexIf, bar, &pexBar)) -+ { -+ mvOsPrintf("mvPexInit: ERR. mvPexBarSet %d failed\n", bar); -+ return MV_ERROR; -+ } -+ -+ /* now enable the windows */ -+ for (winNum = pexStartWindow; winNum < pexCurrWin ; winNum++) -+ { -+ if (MV_OK != mvPexTargetWinEnable(pexIf, winNum, MV_TRUE)) -+ { -+ mvOsPrintf("mvPexInit:mvPexTargetWinEnable winNum =%d failed \n", -+ winNum); -+ return MV_ERROR; -+ } -+ } -+ } -+ -+#endif -+ -+ return mvPexHalInit(pexIf, pexType); -+ -+} -+ -+/******************************************************************************* -+* mvPexTargetWinSet - Set PEX to peripheral target address window BAR -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_OK if PEX BAR target window was set correctly, -+* MV_BAD_PARAM on bad params -+* MV_ERROR otherwise -+* (e.g. address window overlapps with other active PEX target window). -+* -+*******************************************************************************/ -+MV_STATUS mvPexTargetWinSet(MV_U32 pexIf, MV_U32 winNum, -+ MV_PEX_DEC_WIN *pAddrDecWin) -+{ -+ -+ MV_DEC_REGS decRegs; -+ PEX_WIN_REG_INFO winRegInfo; -+ MV_TARGET_ATTRIB targetAttribs; -+ -+ /* Parameter checking */ -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexTargetWinSet: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ -+ if (winNum >= PEX_MAX_TARGET_WIN) -+ { -+ mvOsPrintf("mvPexTargetWinSet: ERR. Invalid PEX winNum %d\n", winNum); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ /* get the pex Window registers offsets */ -+ pexWinRegInfoGet(pexIf,winNum,&winRegInfo); -+ -+ -+ if (MV_TRUE == pAddrDecWin->enable) -+ { -+ -+ /* 2) Check if the requested window overlaps with current windows */ -+ if (MV_TRUE == pexWinOverlapDetect(pexIf,winNum, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("mvPexTargetWinSet: ERR. Target %d overlap\n", winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* 2) Check if the requested window overlaps with current windows */ -+ if (MV_FALSE == pexIsWinWithinBar(pexIf,&pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("mvPexTargetWinSet: Win %d should be in bar boundries\n", -+ winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ } -+ -+ -+ -+ /* read base register*/ -+ -+ if (winRegInfo.baseLowRegOffs) -+ { -+ decRegs.baseReg = MV_REG_READ(winRegInfo.baseLowRegOffs); -+ } -+ else -+ { -+ decRegs.baseReg = 0; -+ } -+ -+ if (winRegInfo.sizeRegOffs) -+ { -+ decRegs.sizeReg = MV_REG_READ(winRegInfo.sizeRegOffs); -+ } -+ else -+ { -+ decRegs.sizeReg =0; -+ } -+ -+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) -+ { -+ mvOsPrintf("mvPexTargetWinSet:mvCtrlAddrDecToReg Failed\n"); -+ return MV_ERROR; -+ } -+ -+ /* enable\Disable */ -+ if (MV_TRUE == pAddrDecWin->enable) -+ { -+ decRegs.sizeReg |= PXWCR_WIN_EN; -+ } -+ else -+ { -+ decRegs.sizeReg &= ~PXWCR_WIN_EN; -+ } -+ -+ -+ /* clear bit location */ -+ decRegs.sizeReg &= ~PXWCR_WIN_BAR_MAP_MASK; -+ -+ /* set bar Mapping */ -+ if (pAddrDecWin->targetBar == 1) -+ { -+ decRegs.sizeReg |= PXWCR_WIN_BAR_MAP_BAR1; -+ } -+ else if (pAddrDecWin->targetBar == 2) -+ { -+ decRegs.sizeReg |= PXWCR_WIN_BAR_MAP_BAR2; -+ } -+ -+ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); -+ -+ /* set attributes */ -+ decRegs.sizeReg &= ~PXWCR_ATTRIB_MASK; -+ decRegs.sizeReg |= targetAttribs.attrib << PXWCR_ATTRIB_OFFS; -+ /* set target ID */ -+ decRegs.sizeReg &= ~PXWCR_TARGET_MASK; -+ decRegs.sizeReg |= targetAttribs.targetId << PXWCR_TARGET_OFFS; -+ -+ -+ /* 3) Write to address decode Base Address Register */ -+ -+ if (winRegInfo.baseLowRegOffs) -+ { -+ MV_REG_WRITE(winRegInfo.baseLowRegOffs, decRegs.baseReg); -+ } -+ -+ /* write size reg */ -+ if (winRegInfo.sizeRegOffs) -+ { -+ if ((MV_PEX_WIN_DEFAULT == winNum)|| -+ (MV_PEX_WIN_EXP_ROM == winNum)) -+ { -+ /* clear size because there is no size field*/ -+ decRegs.sizeReg &= ~PXWCR_SIZE_MASK; -+ -+ /* clear enable because there is no enable field*/ -+ decRegs.sizeReg &= ~PXWCR_WIN_EN; -+ -+ } -+ -+ MV_REG_WRITE(winRegInfo.sizeRegOffs, decRegs.sizeReg); -+ } -+ -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvPexTargetWinGet - Get PEX to peripheral target address window -+* -+* DESCRIPTION: -+* Get the PEX to peripheral target address window BAR. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* bar - BAR to be accessed by slave. -+* -+* OUTPUT: -+* pAddrBarWin - PEX target window information data structure. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexTargetWinGet(MV_U32 pexIf, MV_U32 winNum, -+ MV_PEX_DEC_WIN *pAddrDecWin) -+{ -+ MV_TARGET_ATTRIB targetAttrib; -+ MV_DEC_REGS decRegs; -+ -+ PEX_WIN_REG_INFO winRegInfo; -+ -+ /* Parameter checking */ -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexTargetWinGet: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ -+ if (winNum >= PEX_MAX_TARGET_WIN) -+ { -+ mvOsPrintf("mvPexTargetWinGet: ERR. Invalid PEX winNum %d\n", winNum); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ /* get the pex Window registers offsets */ -+ pexWinRegInfoGet(pexIf,winNum,&winRegInfo); -+ -+ /* read base register*/ -+ if (winRegInfo.baseLowRegOffs) -+ { -+ decRegs.baseReg = MV_REG_READ(winRegInfo.baseLowRegOffs); -+ } -+ else -+ { -+ decRegs.baseReg = 0; -+ } -+ -+ /* read size reg */ -+ if (winRegInfo.sizeRegOffs) -+ { -+ decRegs.sizeReg = MV_REG_READ(winRegInfo.sizeRegOffs); -+ } -+ else -+ { -+ decRegs.sizeReg =0; -+ } -+ -+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) -+ { -+ mvOsPrintf("mvPexTargetWinGet: mvCtrlRegToAddrDec Failed \n"); -+ return MV_ERROR; -+ -+ } -+ -+ if (decRegs.sizeReg & PXWCR_WIN_EN) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ -+ } -+ -+ -+ #if 0 -+ if (-1 == pAddrDecWin->addrWin.size) -+ { -+ return MV_ERROR; -+ } -+ #endif -+ -+ -+ /* get target bar */ -+ if ((decRegs.sizeReg & PXWCR_WIN_BAR_MAP_MASK) == PXWCR_WIN_BAR_MAP_BAR1 ) -+ { -+ pAddrDecWin->targetBar = 1; -+ } -+ else if ((decRegs.sizeReg & PXWCR_WIN_BAR_MAP_MASK) == -+ PXWCR_WIN_BAR_MAP_BAR2 ) -+ { -+ pAddrDecWin->targetBar = 2; -+ } -+ -+ /* attrib and targetId */ -+ pAddrDecWin->attrib = (decRegs.sizeReg & PXWCR_ATTRIB_MASK) >> -+ PXWCR_ATTRIB_OFFS; -+ pAddrDecWin->targetId = (decRegs.sizeReg & PXWCR_TARGET_MASK) >> -+ PXWCR_TARGET_OFFS; -+ -+ targetAttrib.attrib = pAddrDecWin->attrib; -+ targetAttrib.targetId = pAddrDecWin->targetId; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ return MV_OK; -+ -+} -+ -+ -+/******************************************************************************* -+* mvPexTargetWinEnable - Enable/disable a PEX BAR window -+* -+* DESCRIPTION: -+* This function enable/disable a PEX BAR window. -+* if parameter 'enable' == MV_TRUE the routine will enable the -+* window, thus enabling PEX accesses for that BAR (before enabling the -+* window it is tested for overlapping). Otherwise, the window will -+* be disabled. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* bar - BAR to be accessed by slave. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexTargetWinEnable(MV_U32 pexIf,MV_U32 winNum, MV_BOOL enable) -+{ -+ PEX_WIN_REG_INFO winRegInfo; -+ MV_PEX_DEC_WIN addrDecWin; -+ -+ /* Parameter checking */ -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexTargetWinEnable: ERR. Invalid PEX If %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ -+ if (winNum >= PEX_MAX_TARGET_WIN) -+ { -+ mvOsPrintf("mvPexTargetWinEnable ERR. Invalid PEX winNum %d\n", winNum); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ -+ /* get the pex Window registers offsets */ -+ pexWinRegInfoGet(pexIf,winNum,&winRegInfo); -+ -+ -+ /* if the address windows is disabled , we only disable the appropriare -+ pex window and ignore other settings */ -+ -+ if (MV_FALSE == enable) -+ { -+ -+ /* this is not relevant to default and expantion rom -+ windows */ -+ if (winRegInfo.sizeRegOffs) -+ { -+ if ((MV_PEX_WIN_DEFAULT != winNum)&& -+ (MV_PEX_WIN_EXP_ROM != winNum)) -+ { -+ MV_REG_BIT_RESET(winRegInfo.sizeRegOffs, PXWCR_WIN_EN); -+ } -+ } -+ -+ } -+ else -+ { -+ if (MV_OK != mvPexTargetWinGet(pexIf,winNum, &addrDecWin)) -+ { -+ mvOsPrintf("mvPexTargetWinEnable: mvPexTargetWinGet Failed\n"); -+ return MV_ERROR; -+ } -+ -+ /* Check if the requested window overlaps with current windows */ -+ if (MV_TRUE == pexWinOverlapDetect(pexIf,winNum, &addrDecWin.addrWin)) -+ { -+ mvOsPrintf("mvPexTargetWinEnable: ERR. Target %d overlap\n", winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ if (MV_FALSE == pexIsWinWithinBar(pexIf,&addrDecWin.addrWin)) -+ { -+ mvOsPrintf("mvPexTargetWinEnable: Win %d should be in bar boundries\n", -+ winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ -+ /* this is not relevant to default and expantion rom -+ windows */ -+ if (winRegInfo.sizeRegOffs) -+ { -+ if ((MV_PEX_WIN_DEFAULT != winNum)&& -+ (MV_PEX_WIN_EXP_ROM != winNum)) -+ { -+ MV_REG_BIT_SET(winRegInfo.sizeRegOffs, PXWCR_WIN_EN); -+ } -+ } -+ -+ -+ } -+ -+ return MV_OK; -+ -+} -+ -+ -+ -+/******************************************************************************* -+* mvPexTargetWinRemap - Set PEX to target address window remap. -+* -+* DESCRIPTION: -+* The PEX interface supports remap of the BAR original address window. -+* For each BAR it is possible to define a remap address. For example -+* an address 0x12345678 that hits BAR 0x10 (SDRAM CS[0]) will be modified -+* according to remap register but will also be targeted to the -+* SDRAM CS[0]. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* bar - Peripheral target enumerator accessed by slave. -+* pAddrWin - Address window to be checked. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexTargetWinRemap(MV_U32 pexIf, MV_U32 winNum, -+ MV_PEX_REMAP_WIN *pAddrWin) -+{ -+ -+ PEX_WIN_REG_INFO winRegInfo; -+ -+ /* Parameter checking */ -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX interface num %d\n", -+ pexIf); -+ return MV_BAD_PARAM; -+ } -+ if (MV_PEX_WIN_DEFAULT == winNum) -+ { -+ mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX win num %d\n", -+ winNum); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ if (MV_IS_NOT_ALIGN(pAddrWin->addrWin.baseLow, PXWRR_REMAP_ALIGNMENT)) -+ { -+ mvOsPrintf("mvPexTargetWinRemap: Error remap PEX interface %d win %d."\ -+ "\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ pexIf, -+ winNum, -+ pAddrWin->addrWin.baseLow, -+ pAddrWin->addrWin.size); -+ -+ return MV_ERROR; -+ } -+ -+ pexWinRegInfoGet(pexIf, winNum, &winRegInfo); -+ -+ /* Set remap low register value */ -+ MV_REG_WRITE(winRegInfo.remapLowRegOffs, pAddrWin->addrWin.baseLow); -+ -+ /* Skip base high settings if the BAR has only base low (32-bit) */ -+ if (0 != winRegInfo.remapHighRegOffs) -+ { -+ MV_REG_WRITE(winRegInfo.remapHighRegOffs, pAddrWin->addrWin.baseHigh); -+ } -+ -+ -+ if (pAddrWin->enable == MV_TRUE) -+ { -+ MV_REG_BIT_SET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvPexTargetWinRemapEnable - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+ -+MV_STATUS mvPexTargetWinRemapEnable(MV_U32 pexIf, MV_U32 winNum, -+ MV_BOOL enable) -+{ -+ PEX_WIN_REG_INFO winRegInfo; -+ -+ /* Parameter checking */ -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX interface num %d\n", -+ pexIf); -+ return MV_BAD_PARAM; -+ } -+ if (MV_PEX_WIN_DEFAULT == winNum) -+ { -+ mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX win num %d\n", -+ winNum); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ -+ pexWinRegInfoGet(pexIf, winNum, &winRegInfo); -+ -+ if (enable == MV_TRUE) -+ { -+ MV_REG_BIT_SET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); -+ } -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvPexBarSet - Set PEX bar address and size -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexBarSet(MV_U32 pexIf, -+ MV_U32 barNum, -+ MV_PEX_BAR *pAddrWin) -+{ -+ MV_U32 regBaseLow; -+ MV_U32 regSize,sizeToReg; -+ -+ -+ /* check parameters */ -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexBarSet: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ -+ if(barNum >= PEX_MAX_BARS) -+ { -+ mvOsPrintf("mvPexBarSet: ERR. Invalid bar number %d\n", barNum); -+ return MV_BAD_PARAM; -+ } -+ -+ -+ if (pAddrWin->addrWin.size == 0) -+ { -+ mvOsPrintf("mvPexBarSet: Size zero is Illigal\n" ); -+ return MV_BAD_PARAM; -+ } -+ -+ -+ /* Check if the window complies with PEX spec */ -+ if (MV_TRUE != pexBarIsValid(pAddrWin->addrWin.baseLow, -+ pAddrWin->addrWin.size)) -+ { -+ mvOsPrintf("mvPexBarSet: ERR. Target %d window invalid\n", barNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* 2) Check if the requested bar overlaps with current bars */ -+ if (MV_TRUE == pexBarOverlapDetect(pexIf,barNum, &pAddrWin->addrWin)) -+ { -+ mvOsPrintf("mvPexBarSet: ERR. Target %d overlap\n", barNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Get size register value according to window size */ -+ sizeToReg = ctrlSizeToReg(pAddrWin->addrWin.size, PXBCR_BAR_SIZE_ALIGNMENT); -+ -+ /* Read bar size */ -+ if (PEX_INTER_REGS_BAR != barNum) /* internal registers have no size */ -+ { -+ regSize = MV_REG_READ(PEX_BAR_CTRL_REG(pexIf,barNum)); -+ -+ /* Size parameter validity check. */ -+ if (-1 == sizeToReg) -+ { -+ mvOsPrintf("mvPexBarSet: ERR. Target BAR %d size invalid.\n",barNum); -+ return MV_BAD_PARAM; -+ } -+ -+ regSize &= ~PXBCR_BAR_SIZE_MASK; -+ regSize |= (sizeToReg << PXBCR_BAR_SIZE_OFFS) ; -+ -+ MV_REG_WRITE(PEX_BAR_CTRL_REG(pexIf,barNum),regSize); -+ -+ } -+ -+ /* set size */ -+ -+ -+ -+ /* Read base address low */ -+ regBaseLow = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, -+ PEX_MV_BAR_BASE(barNum))); -+ -+ /* clear current base */ -+ if (PEX_INTER_REGS_BAR == barNum) -+ { -+ regBaseLow &= ~PXBIR_BASE_MASK; -+ regBaseLow |= (pAddrWin->addrWin.baseLow & PXBIR_BASE_MASK); -+ } -+ else -+ { -+ regBaseLow &= ~PXBR_BASE_MASK; -+ regBaseLow |= (pAddrWin->addrWin.baseLow & PXBR_BASE_MASK); -+ } -+ -+ /* if we had a previous value that contain the bar type (MeM\IO), we want to -+ restore it */ -+ regBaseLow |= PEX_BAR_DEFAULT_ATTRIB; -+ -+ -+ -+ /* write base low */ -+ MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE(barNum)), -+ regBaseLow); -+ -+ if (pAddrWin->addrWin.baseHigh != 0) -+ { -+ /* Read base address high */ -+ MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE_HIGH(barNum)), -+ pAddrWin->addrWin.baseHigh); -+ -+ } -+ -+ /* lastly enable the Bar */ -+ if (pAddrWin->enable == MV_TRUE) -+ { -+ if (PEX_INTER_REGS_BAR != barNum) /* internal registers -+ are enabled always */ -+ { -+ MV_REG_BIT_SET(PEX_BAR_CTRL_REG(pexIf,barNum),PXBCR_BAR_EN); -+ } -+ } -+ else if (MV_FALSE == pAddrWin->enable) -+ { -+ if (PEX_INTER_REGS_BAR != barNum) /* internal registers -+ are enabled always */ -+ { -+ MV_REG_BIT_RESET(PEX_BAR_CTRL_REG(pexIf,barNum),PXBCR_BAR_EN); -+ } -+ -+ } -+ -+ -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPexBarGet - Get PEX bar address and size -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+ -+MV_STATUS mvPexBarGet(MV_U32 pexIf, -+ MV_U32 barNum, -+ MV_PEX_BAR *pAddrWin) -+{ -+ /* check parameters */ -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexBarGet: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ -+ if(barNum >= PEX_MAX_BARS) -+ { -+ mvOsPrintf("mvPexBarGet: ERR. Invalid bar number %d\n", barNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* read base low */ -+ pAddrWin->addrWin.baseLow = -+ MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE(barNum))); -+ -+ -+ if (PEX_INTER_REGS_BAR == barNum) -+ { -+ pAddrWin->addrWin.baseLow &= PXBIR_BASE_MASK; -+ } -+ else -+ { -+ pAddrWin->addrWin.baseLow &= PXBR_BASE_MASK; -+ } -+ -+ -+ /* read base high */ -+ pAddrWin->addrWin.baseHigh = -+ MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE_HIGH(barNum))); -+ -+ -+ /* Read bar size */ -+ if (PEX_INTER_REGS_BAR != barNum) /* internal registers have no size */ -+ { -+ pAddrWin->addrWin.size = MV_REG_READ(PEX_BAR_CTRL_REG(pexIf,barNum)); -+ -+ /* check if enable or not */ -+ if (pAddrWin->addrWin.size & PXBCR_BAR_EN) -+ { -+ pAddrWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrWin->enable = MV_FALSE; -+ } -+ -+ /* now get the size */ -+ pAddrWin->addrWin.size &= PXBCR_BAR_SIZE_MASK; -+ pAddrWin->addrWin.size >>= PXBCR_BAR_SIZE_OFFS; -+ -+ pAddrWin->addrWin.size = ctrlRegToSize(pAddrWin->addrWin.size, -+ PXBCR_BAR_SIZE_ALIGNMENT); -+ -+ } -+ else /* PEX_INTER_REGS_BAR */ -+ { -+ pAddrWin->addrWin.size = INTER_REGS_SIZE; -+ pAddrWin->enable = MV_TRUE; -+ } -+ -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvPexBarEnable - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+ -+ -+MV_STATUS mvPexBarEnable(MV_U32 pexIf, MV_U32 barNum, MV_BOOL enable) -+{ -+ -+ MV_PEX_BAR pexBar; -+ -+ /* check parameters */ -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexBarEnable: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ -+ -+ if(barNum >= PEX_MAX_BARS) -+ { -+ mvOsPrintf("mvPexBarEnable: ERR. Invalid bar number %d\n", barNum); -+ return MV_BAD_PARAM; -+ } -+ -+ if (PEX_INTER_REGS_BAR == barNum) -+ { -+ if (MV_TRUE == enable) -+ { -+ return MV_OK; -+ } -+ else -+ { -+ return MV_ERROR; -+ } -+ } -+ -+ -+ if (MV_FALSE == enable) -+ { -+ /* disable bar and quit */ -+ MV_REG_BIT_RESET(PEX_BAR_CTRL_REG(pexIf,barNum),PXBCR_BAR_EN); -+ return MV_OK; -+ } -+ -+ /* else */ -+ -+ if (mvPexBarGet(pexIf,barNum,&pexBar) != MV_OK) -+ { -+ mvOsPrintf("mvPexBarEnable: mvPexBarGet Failed\n"); -+ return MV_ERROR; -+ -+ } -+ -+ if (MV_TRUE == pexBar.enable) -+ { -+ /* it is already enabled !!! */ -+ return MV_OK; -+ } -+ -+ /* else enable the bar*/ -+ -+ pexBar.enable = MV_TRUE; -+ -+ if (mvPexBarSet(pexIf,barNum,&pexBar) != MV_OK) -+ { -+ mvOsPrintf("mvPexBarEnable: mvPexBarSet Failed\n"); -+ return MV_ERROR; -+ -+ } -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* pexWinOverlapDetect - Detect address windows overlapping -+* -+* DESCRIPTION: -+* This function detects address window overlapping of a given address -+* window in PEX BARs. -+* -+* INPUT: -+* pAddrWin - Address window to be checked. -+* bar - BAR to be accessed by slave. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+static MV_BOOL pexWinOverlapDetect(MV_U32 pexIf, -+ MV_U32 winNum, -+ MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 win; -+ MV_PEX_DEC_WIN addrDecWin; -+ -+ -+ for(win = 0; win < PEX_MAX_TARGET_WIN -2 ; win++) -+ { -+ /* don't check our target or illegal targets */ -+ if (winNum == win) -+ { -+ continue; -+ } -+ -+ /* Get window parameters */ -+ if (MV_OK != mvPexTargetWinGet(pexIf, win, &addrDecWin)) -+ { -+ mvOsPrintf("pexWinOverlapDetect: ERR. TargetWinGet failed win=%x\n", -+ win); -+ return MV_ERROR; -+ } -+ -+ /* Do not check disabled windows */ -+ if (MV_FALSE == addrDecWin.enable) -+ { -+ continue; -+ } -+ -+ -+ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) -+ { -+ mvOsPrintf("pexWinOverlapDetect: winNum %d overlap current %d\n", -+ winNum, win); -+ return MV_TRUE; -+ } -+ } -+ -+ return MV_FALSE; -+} -+ -+/******************************************************************************* -+* pexIsWinWithinBar - Detect if address is within PEX bar boundries -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+static MV_BOOL pexIsWinWithinBar(MV_U32 pexIf, -+ MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 bar; -+ MV_PEX_BAR addrDecWin; -+ -+ for(bar = 0; bar < PEX_MAX_BARS; bar++) -+ { -+ -+ /* Get window parameters */ -+ if (MV_OK != mvPexBarGet(pexIf, bar, &addrDecWin)) -+ { -+ mvOsPrintf("pexIsWinWithinBar: ERR. mvPexBarGet failed\n"); -+ return MV_ERROR; -+ } -+ -+ /* Do not check disabled bars */ -+ if (MV_FALSE == addrDecWin.enable) -+ { -+ continue; -+ } -+ -+ -+ if(MV_TRUE == ctrlWinWithinWinTest(pAddrWin, &addrDecWin.addrWin)) -+ { -+ return MV_TRUE; -+ } -+ } -+ -+ return MV_FALSE; -+ -+} -+ -+/******************************************************************************* -+* pexBarOverlapDetect - Detect address windows overlapping -+* -+* DESCRIPTION: -+* This function detects address window overlapping of a given address -+* window in PEX BARs. -+* -+* INPUT: -+* pAddrWin - Address window to be checked. -+* bar - BAR to be accessed by slave. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+static MV_BOOL pexBarOverlapDetect(MV_U32 pexIf, -+ MV_U32 barNum, -+ MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 bar; -+ MV_PEX_BAR barDecWin; -+ -+ -+ for(bar = 0; bar < PEX_MAX_BARS; bar++) -+ { -+ /* don't check our target or illegal targets */ -+ if (barNum == bar) -+ { -+ continue; -+ } -+ -+ /* Get window parameters */ -+ if (MV_OK != mvPexBarGet(pexIf, bar, &barDecWin)) -+ { -+ mvOsPrintf("pexBarOverlapDetect: ERR. TargetWinGet failed\n"); -+ return MV_ERROR; -+ } -+ -+ /* don'nt check disabled bars */ -+ if (barDecWin.enable == MV_FALSE) -+ { -+ continue; -+ } -+ -+ -+ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &barDecWin.addrWin)) -+ { -+ mvOsPrintf("pexBarOverlapDetect: winNum %d overlap current %d\n", -+ barNum, bar); -+ return MV_TRUE; -+ } -+ } -+ -+ return MV_FALSE; -+} -+ -+/******************************************************************************* -+* pexBarIsValid - Check if the given address window is valid -+* -+* DESCRIPTION: -+* PEX spec restrict BAR base to be aligned to BAR size. -+* This function checks if the given address window is valid. -+* -+* INPUT: -+* baseLow - 32bit low base address. -+* size - Window size. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the address window is valid, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+static MV_STATUS pexBarIsValid(MV_U32 baseLow, MV_U32 size) -+{ -+ -+ /* PCI spec restrict BAR base to be aligned to BAR size */ -+ if(MV_IS_NOT_ALIGN(baseLow, size)) -+ { -+ return MV_ERROR; -+ } -+ else -+ { -+ return MV_TRUE; -+ } -+ -+ return MV_TRUE; -+} -+ -+/******************************************************************************* -+* pexBarRegInfoGet - Get BAR register information -+* -+* DESCRIPTION: -+* PEX BARs registers offsets are inconsecutive. -+* This function gets a PEX BAR register information like register offsets -+* and function location of the BAR. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* bar - The PEX BAR in question. -+* -+* OUTPUT: -+* pBarRegInfo - BAR register info struct. -+* -+* RETURN: -+* MV_BAD_PARAM when bad parameters ,MV_ERROR on error ,othewise MV_OK -+* -+*******************************************************************************/ -+static MV_STATUS pexWinRegInfoGet(MV_U32 pexIf, -+ MV_U32 winNum, -+ PEX_WIN_REG_INFO *pWinRegInfo) -+{ -+ -+ if ((winNum >= 0)&&(winNum <=3)) -+ { -+ pWinRegInfo->baseLowRegOffs = PEX_WIN0_3_BASE_REG(pexIf,winNum); -+ pWinRegInfo->baseHighRegOffs = 0; -+ pWinRegInfo->sizeRegOffs = PEX_WIN0_3_CTRL_REG(pexIf,winNum); -+ pWinRegInfo->remapLowRegOffs = PEX_WIN0_3_REMAP_REG(pexIf,winNum); -+ pWinRegInfo->remapHighRegOffs = 0; -+ } -+ else if ((winNum >= 4)&&(winNum <=5)) -+ { -+ pWinRegInfo->baseLowRegOffs = PEX_WIN4_5_BASE_REG(pexIf,winNum); -+ pWinRegInfo->baseHighRegOffs = 0; -+ pWinRegInfo->sizeRegOffs = PEX_WIN4_5_CTRL_REG(pexIf,winNum); -+ pWinRegInfo->remapLowRegOffs = PEX_WIN4_5_REMAP_REG(pexIf,winNum); -+ pWinRegInfo->remapHighRegOffs = PEX_WIN4_5_REMAP_HIGH_REG(pexIf,winNum); -+ -+ } -+ else if (MV_PEX_WIN_DEFAULT == winNum) -+ { -+ pWinRegInfo->baseLowRegOffs = 0; -+ pWinRegInfo->baseHighRegOffs = 0; -+ pWinRegInfo->sizeRegOffs = PEX_WIN_DEFAULT_CTRL_REG(pexIf); -+ pWinRegInfo->remapLowRegOffs = 0; -+ pWinRegInfo->remapHighRegOffs = 0; -+ } -+ else if (MV_PEX_WIN_EXP_ROM == winNum) -+ { -+ pWinRegInfo->baseLowRegOffs = 0; -+ pWinRegInfo->baseHighRegOffs = 0; -+ pWinRegInfo->sizeRegOffs = PEX_WIN_EXP_ROM_CTRL_REG(pexIf); -+ pWinRegInfo->remapLowRegOffs = PEX_WIN_EXP_ROM_REMAP_REG(pexIf); -+ pWinRegInfo->remapHighRegOffs = 0; -+ -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* pexBarNameGet - Get the string name of PEX BAR. -+* -+* DESCRIPTION: -+* This function get the string name of PEX BAR. -+* -+* INPUT: -+* bar - PEX bar number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* pointer to the string name of PEX BAR. -+* -+*******************************************************************************/ -+const MV_8* pexBarNameGet( MV_U32 bar ) -+{ -+ switch( bar ) -+ { -+ case PEX_INTER_REGS_BAR: -+ return "Internal Regs Bar0...."; -+ case PEX_DRAM_BAR: -+ return "DRAM Bar1............."; -+ case PEX_DEVICE_BAR: -+ return "Devices Bar2.........."; -+ default: -+ return "Bar unknown"; -+ } -+} -+/******************************************************************************* -+* mvPexAddrDecShow - Print the PEX address decode map (BARs and windows). -+* -+* DESCRIPTION: -+* This function print the PEX address decode map (BARs and windows). -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvPexAddrDecShow(MV_VOID) -+{ -+ MV_PEX_BAR pexBar; -+ MV_PEX_DEC_WIN win; -+ MV_U32 pexIf; -+ MV_U32 bar,winNum; -+ -+ for( pexIf = 0; pexIf < mvCtrlPexMaxIfGet(); pexIf++ ) -+ { -+ if (MV_FALSE == mvCtrlPwrClckGet(PEX_UNIT_ID, pexIf)) continue; -+ mvOsOutput( "\n" ); -+ mvOsOutput( "PEX%d:\n", pexIf ); -+ mvOsOutput( "-----\n" ); -+ -+ mvOsOutput( "\nPex Bars \n\n"); -+ -+ for( bar = 0; bar < PEX_MAX_BARS; bar++ ) -+ { -+ memset( &pexBar, 0, sizeof(MV_PEX_BAR) ); -+ -+ mvOsOutput( "%s ", pexBarNameGet(bar) ); -+ -+ if( mvPexBarGet( pexIf, bar, &pexBar ) == MV_OK ) -+ { -+ if( pexBar.enable ) -+ { -+ mvOsOutput( "base %08x, ", pexBar.addrWin.baseLow ); -+ mvSizePrint( pexBar.addrWin.size ); -+ mvOsOutput( "\n" ); -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ } -+ } -+ mvOsOutput( "\nPex Decode Windows\n\n"); -+ -+ for( winNum = 0; winNum < PEX_MAX_TARGET_WIN - 2; winNum++) -+ { -+ memset( &win, 0,sizeof(MV_PEX_DEC_WIN) ); -+ -+ mvOsOutput( "win%d - ", winNum ); -+ -+ if ( mvPexTargetWinGet(pexIf,winNum,&win) == MV_OK) -+ { -+ if (win.enable) -+ { -+ mvOsOutput( "%s base %08x, ", -+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); -+ mvOsOutput( "...." ); -+ mvSizePrint( win.addrWin.size ); -+ -+ mvOsOutput( "\n" ); -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ -+ -+ } -+ } -+ -+ memset( &win, 0,sizeof(MV_PEX_DEC_WIN) ); -+ -+ mvOsOutput( "default win - " ); -+ -+ if ( mvPexTargetWinGet(pexIf, MV_PEX_WIN_DEFAULT, &win) == MV_OK) -+ { -+ mvOsOutput( "%s ", -+ mvCtrlTargetNameGet(win.target) ); -+ mvOsOutput( "\n" ); -+ } -+ memset( &win, 0,sizeof(MV_PEX_DEC_WIN) ); -+ -+ mvOsOutput( "Expansion ROM - " ); -+ -+ if ( mvPexTargetWinGet(pexIf, MV_PEX_WIN_EXP_ROM, &win) == MV_OK) -+ { -+ mvOsOutput( "%s ", -+ mvCtrlTargetNameGet(win.target) ); -+ mvOsOutput( "\n" ); -+ } -+ -+ } -+} -+ -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,348 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCSysPEXH -+#define __INCSysPEXH -+ -+#include "mvCommon.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+ -+/* 4KB granularity */ -+#define MINIMUM_WINDOW_SIZE 0x1000 -+#define MINIMUM_BAR_SIZE 0x1000 -+#define MINIMUM_BAR_SIZE_MASK 0xFFFFF000 -+#define BAR_SIZE_OFFS 12 -+#define BAR_SIZE_MASK (0xFFFFF << BAR_SIZE_OFFS) -+ -+ -+ -+#define MV_PEX_WIN_DEFAULT 6 -+#define MV_PEX_WIN_EXP_ROM 7 -+#define PEX_MAX_TARGET_WIN 8 -+ -+ -+#define PEX_MAX_BARS 3 -+#define PEX_INTER_REGS_BAR 0 -+#define PEX_DRAM_BAR 1 -+#define PEX_DEVICE_BAR 2 -+ -+/*************************************/ -+/* PCI Express BAR Control Registers */ -+/*************************************/ -+#define PEX_BAR_CTRL_REG(pexIf,bar) (0x41804 + (bar-1)*4- (pexIf)*0x10000) -+#define PEX_EXP_ROM_BAR_CTRL_REG(pexIf) (0x4180C - (pexIf)*0x10000) -+ -+ -+/* PCI Express BAR Control Register */ -+/* PEX_BAR_CTRL_REG (PXBCR) */ -+ -+#define PXBCR_BAR_EN BIT0 -+#define PXBCR_BAR_SIZE_OFFS 16 -+#define PXBCR_BAR_SIZE_MASK (0xffff << PXBCR_BAR_SIZE_OFFS) -+#define PXBCR_BAR_SIZE_ALIGNMENT 0x10000 -+ -+ -+ -+/* PCI Express Expansion ROM BAR Control Register */ -+/* PEX_EXP_ROM_BAR_CTRL_REG (PXERBCR) */ -+ -+#define PXERBCR_EXPROM_EN BIT0 -+#define PXERBCR_EXPROMSZ_OFFS 19 -+#define PXERBCR_EXPROMSZ_MASK (0xf << PXERBCR_EXPROMSZ_OFFS) -+#define PXERBCR_EXPROMSZ_512KB (0x0 << PXERBCR_EXPROMSZ_OFFS) -+#define PXERBCR_EXPROMSZ_1024KB (0x1 << PXERBCR_EXPROMSZ_OFFS) -+#define PXERBCR_EXPROMSZ_2048KB (0x3 << PXERBCR_EXPROMSZ_OFFS) -+#define PXERBCR_EXPROMSZ_4096KB (0x7 << PXERBCR_EXPROMSZ_OFFS) -+ -+/************************************************/ -+/* PCI Express Address Window Control Registers */ -+/************************************************/ -+#define PEX_WIN0_3_CTRL_REG(pexIf,winNum) \ -+ (0x41820 + (winNum) * 0x10 - (pexIf) * 0x10000) -+#define PEX_WIN0_3_BASE_REG(pexIf,winNum) \ -+ (0x41824 + (winNum) * 0x10 - (pexIf) * 0x10000) -+#define PEX_WIN0_3_REMAP_REG(pexIf,winNum) \ -+ (0x4182C + (winNum) * 0x10 - (pexIf) * 0x10000) -+#define PEX_WIN4_5_CTRL_REG(pexIf,winNum) \ -+ (0x41860 + (winNum - 4) * 0x20 - (pexIf) * 0x10000) -+#define PEX_WIN4_5_BASE_REG(pexIf,winNum) \ -+ (0x41864 + (winNum - 4) * 0x20 - (pexIf) * 0x10000) -+#define PEX_WIN4_5_REMAP_REG(pexIf,winNum) \ -+ (0x4186C + (winNum - 4) * 0x20 - (pexIf) * 0x10000) -+#define PEX_WIN4_5_REMAP_HIGH_REG(pexIf,winNum) \ -+ (0x41870 + (winNum - 4) * 0x20 - (pexIf) * 0x10000) -+ -+#define PEX_WIN_DEFAULT_CTRL_REG(pexIf) (0x418B0 - (pexIf) * 0x10000) -+#define PEX_WIN_EXP_ROM_CTRL_REG(pexIf) (0x418C0 - (pexIf) * 0x10000) -+#define PEX_WIN_EXP_ROM_REMAP_REG(pexIf) (0x418C4 - (pexIf) * 0x10000) -+ -+/* PCI Express Window Control Register */ -+/* PEX_WIN_CTRL_REG (PXWCR) */ -+ -+#define PXWCR_WIN_EN BIT0 /* Window Enable.*/ -+ -+#define PXWCR_WIN_BAR_MAP_OFFS 1 /* Mapping to BAR.*/ -+#define PXWCR_WIN_BAR_MAP_MASK BIT1 -+#define PXWCR_WIN_BAR_MAP_BAR1 (0 << PXWCR_WIN_BAR_MAP_OFFS) -+#define PXWCR_WIN_BAR_MAP_BAR2 (1 << PXWCR_WIN_BAR_MAP_OFFS) -+ -+#define PXWCR_TARGET_OFFS 4 /*Unit ID */ -+#define PXWCR_TARGET_MASK (0xf << PXWCR_TARGET_OFFS) -+ -+#define PXWCR_ATTRIB_OFFS 8 /* target attributes */ -+#define PXWCR_ATTRIB_MASK (0xff << PXWCR_ATTRIB_OFFS) -+ -+#define PXWCR_SIZE_OFFS 16 /* size */ -+#define PXWCR_SIZE_MASK (0xffff << PXWCR_SIZE_OFFS) -+#define PXWCR_SIZE_ALIGNMENT 0x10000 -+ -+/* PCI Express Window Base Register */ -+/* PEX_WIN_BASE_REG (PXWBR)*/ -+ -+#define PXWBR_BASE_OFFS 16 /* address[31:16] */ -+#define PXWBR_BASE_MASK (0xffff << PXWBR_BASE_OFFS) -+#define PXWBR_BASE_ALIGNMENT 0x10000 -+ -+/* PCI Express Window Remap Register */ -+/* PEX_WIN_REMAP_REG (PXWRR)*/ -+ -+#define PXWRR_REMAP_EN BIT0 -+#define PXWRR_REMAP_OFFS 16 -+#define PXWRR_REMAP_MASK (0xffff << PXWRR_REMAP_OFFS) -+#define PXWRR_REMAP_ALIGNMENT 0x10000 -+ -+/* PCI Express Window Remap (High) Register */ -+/* PEX_WIN_REMAP_HIGH_REG (PXWRHR)*/ -+ -+#define PXWRHR_REMAP_HIGH_OFFS 0 -+#define PXWRHR_REMAP_HIGH_MASK (0xffffffff << PXWRHR_REMAP_HIGH_OFFS) -+ -+/* PCI Express Default Window Control Register */ -+/* PEX_WIN_DEFAULT_CTRL_REG (PXWDCR) */ -+ -+#define PXWDCR_TARGET_OFFS 4 /*Unit ID */ -+#define PXWDCR_TARGET_MASK (0xf << PXWDCR_TARGET_OFFS) -+#define PXWDCR_ATTRIB_OFFS 8 /* target attributes */ -+#define PXWDCR_ATTRIB_MASK (0xff << PXWDCR_ATTRIB_OFFS) -+ -+/* PCI Express Expansion ROM Window Control Register */ -+/* PEX_WIN_EXP_ROM_CTRL_REG (PXWERCR)*/ -+ -+#define PXWERCR_TARGET_OFFS 4 /*Unit ID */ -+#define PXWERCR_TARGET_MASK (0xf << PXWERCR_TARGET_OFFS) -+#define PXWERCR_ATTRIB_OFFS 8 /* target attributes */ -+#define PXWERCR_ATTRIB_MASK (0xff << PXWERCR_ATTRIB_OFFS) -+ -+/* PCI Express Expansion ROM Window Remap Register */ -+/* PEX_WIN_EXP_ROM_REMAP_REG (PXWERRR)*/ -+ -+#define PXWERRR_REMAP_EN BIT0 -+#define PXWERRR_REMAP_OFFS 16 -+#define PXWERRR_REMAP_MASK (0xffff << PXWERRR_REMAP_OFFS) -+#define PXWERRR_REMAP_ALIGNMENT 0x10000 -+ -+ -+ -+/*PEX_MEMORY_BAR_BASE_ADDR(barNum) (PXMBBA)*/ -+/* PCI Express BAR0 Internal Register*/ -+/*PEX BAR0_INTER_REG (PXBIR)*/ -+ -+#define PXBIR_IOSPACE BIT0 /* Memory Space Indicator */ -+ -+#define PXBIR_TYPE_OFFS 1 /* BAR Type/Init Val. */ -+#define PXBIR_TYPE_MASK (0x3 << PXBIR_TYPE_OFFS) -+#define PXBIR_TYPE_32BIT_ADDR (0x0 << PXBIR_TYPE_OFFS) -+#define PXBIR_TYPE_64BIT_ADDR (0x2 << PXBIR_TYPE_OFFS) -+ -+#define PXBIR_PREFETCH_EN BIT3 /* Prefetch Enable */ -+ -+#define PXBIR_BASE_OFFS 20 /* Base address. Address bits [31:20] */ -+#define PXBIR_BASE_MASK (0xfff << PXBIR_BASE_OFFS) -+#define PXBIR_BASE_ALIGNMET (1 << PXBIR_BASE_OFFS) -+ -+ -+/* PCI Express BAR0 Internal (High) Register*/ -+/*PEX BAR0_INTER_REG_HIGH (PXBIRH)*/ -+ -+#define PXBIRH_BASE_OFFS 0 /* Base address. Bits [63:32] */ -+#define PXBIRH_BASE_MASK (0xffffffff << PBBHR_BASE_OFFS) -+ -+ -+#define PEX_BAR_DEFAULT_ATTRIB 0xc /* Memory - Prefetch - 64 bit address */ -+#define PEX_BAR0_DEFAULT_ATTRIB PEX_BAR_DEFAULT_ATTRIB -+#define PEX_BAR1_DEFAULT_ATTRIB PEX_BAR_DEFAULT_ATTRIB -+#define PEX_BAR2_DEFAULT_ATTRIB PEX_BAR_DEFAULT_ATTRIB -+ -+ -+/* PCI Express BAR1 Register */ -+/* PCI Express BAR2 Register*/ -+/*PEX BAR1_REG (PXBR)*/ -+/*PEX BAR2_REG (PXBR)*/ -+ -+#define PXBR_IOSPACE BIT0 /* Memory Space Indicator */ -+ -+#define PXBR_TYPE_OFFS 1 /* BAR Type/Init Val. */ -+#define PXBR_TYPE_MASK (0x3 << PXBR_TYPE_OFFS) -+#define PXBR_TYPE_32BIT_ADDR (0x0 << PXBR_TYPE_OFFS) -+#define PXBR_TYPE_64BIT_ADDR (0x2 << PXBR_TYPE_OFFS) -+ -+#define PXBR_PREFETCH_EN BIT3 /* Prefetch Enable */ -+ -+#define PXBR_BASE_OFFS 16 /* Base address. Address bits [31:16] */ -+#define PXBR_BASE_MASK (0xffff << PXBR_BASE_OFFS) -+#define PXBR_BASE_ALIGNMET (1 << PXBR_BASE_OFFS) -+ -+ -+/* PCI Express BAR1 (High) Register*/ -+/* PCI Express BAR2 (High) Register*/ -+/*PEX BAR1_REG_HIGH (PXBRH)*/ -+/*PEX BAR2_REG_HIGH (PXBRH)*/ -+ -+#define PXBRH_BASE_OFFS 0 /* Base address. Address bits [63:32] */ -+#define PXBRH_BASE_MASK (0xffffffff << PXBRH_BASE_OFFS) -+ -+/* PCI Express Expansion ROM BAR Register*/ -+/*PEX_EXPANSION_ROM_BASE_ADDR_REG (PXERBAR)*/ -+ -+#define PXERBAR_EXPROMEN BIT0 /* Expansion ROM Enable */ -+ -+#define PXERBAR_BASE_512K_OFFS 19 /* Expansion ROM Base Address */ -+#define PXERBAR_BASE_512K_MASK (0x1fff << PXERBAR_BASE_512K_OFFS) -+ -+#define PXERBAR_BASE_1MB_OFFS 20 /* Expansion ROM Base Address */ -+#define PXERBAR_BASE_1MB_MASK (0xfff << PXERBAR_BASE_1MB_OFFS) -+ -+#define PXERBAR_BASE_2MB_OFFS 21 /* Expansion ROM Base Address */ -+#define PXERBAR_BASE_2MB_MASK (0x7ff << PXERBAR_BASE_2MB_OFFS) -+ -+#define PXERBAR_BASE_4MB_OFFS 22 /* Expansion ROM Base Address */ -+#define PXERBAR_BASE_4MB_MASK (0x3ff << PXERBAR_BASE_4MB_OFFS) -+ -+/* PEX Bar attributes */ -+typedef struct _mvPexBar -+{ -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+}MV_PEX_BAR; -+ -+/* PEX Remap Window attributes */ -+typedef struct _mvPexRemapWin -+{ -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+}MV_PEX_REMAP_WIN; -+ -+/* PEX Remap Window attributes */ -+typedef struct _mvPexDecWin -+{ -+ MV_TARGET target; -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_U32 targetBar; -+ MV_U8 attrib; /* chip select attributes */ -+ MV_TARGET_ID targetId; /* Target Id of this MV_TARGET */ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+}MV_PEX_DEC_WIN; -+ -+/* Global Functions prototypes */ -+/* mvPexHalInit - Initialize PEX interfaces*/ -+MV_STATUS mvPexInit(MV_U32 pexIf, MV_PEX_TYPE pexType); -+ -+ -+/* mvPexTargetWinSet - Set PEX to peripheral target address window BAR*/ -+MV_STATUS mvPexTargetWinSet(MV_U32 pexIf, MV_U32 winNum, -+ MV_PEX_DEC_WIN *pAddrDecWin); -+ -+/* mvPexTargetWinGet - Get PEX to peripheral target address window*/ -+MV_STATUS mvPexTargetWinGet(MV_U32 pexIf, MV_U32 winNum, -+ MV_PEX_DEC_WIN *pAddrDecWin); -+ -+/* mvPexTargetWinEnable - Enable/disable a PEX BAR window*/ -+MV_STATUS mvPexTargetWinEnable(MV_U32 pexIf,MV_U32 winNum, MV_BOOL enable); -+ -+/* mvPexTargetWinRemap - Set PEX to target address window remap.*/ -+MV_STATUS mvPexTargetWinRemap(MV_U32 pexIf, MV_U32 winNum, -+ MV_PEX_REMAP_WIN *pAddrWin); -+ -+/* mvPexTargetWinRemapEnable -enable\disable a PEX Window remap.*/ -+MV_STATUS mvPexTargetWinRemapEnable(MV_U32 pexIf, MV_U32 winNum, -+ MV_BOOL enable); -+ -+/* mvPexBarSet - Set PEX bar address and size */ -+MV_STATUS mvPexBarSet(MV_U32 pexIf, MV_U32 barNum, MV_PEX_BAR *addrWin); -+ -+/* mvPexBarGet - Get PEX bar address and size */ -+MV_STATUS mvPexBarGet(MV_U32 pexIf, MV_U32 barNum, MV_PEX_BAR *addrWin); -+ -+/* mvPexBarEnable - enable\disable a PEX bar*/ -+MV_STATUS mvPexBarEnable(MV_U32 pexIf, MV_U32 barNum, MV_BOOL enable); -+ -+/* mvPexAddrDecShow - Display address decode windows attributes */ -+MV_VOID mvPexAddrDecShow(MV_VOID); -+ -+#endif -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.c ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.c 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,430 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#include "mvTypes.h" -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "cpu/mvCpu.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+#include "sata/CoreDriver/mvRegs.h" -+#include "ctrlEnv/sys/mvSysSata.h" -+ -+MV_TARGET sataAddrDecPrioTab[] = -+{ -+#if defined(MV_INCLUDE_SDRAM_CS0) -+ SDRAM_CS0, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS1) -+ SDRAM_CS1, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS2) -+ SDRAM_CS2, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS3) -+ SDRAM_CS3, -+#endif -+#if defined(MV_INCLUDE_PEX) -+ PEX0_MEM, -+#endif -+ TBL_TERM -+}; -+ -+ -+/******************************************************************************* -+* sataWinOverlapDetect - Detect SATA address windows overlapping -+* -+* DESCRIPTION: -+* An unpredicted behaviur is expected in case SATA address decode -+* windows overlapps. -+* This function detects SATA address decode windows overlapping of a -+* specified window. The function does not check the window itself for -+* overlapping. The function also skipps disabled address decode windows. -+* -+* INPUT: -+* winNum - address decode window number. -+* pAddrDecWin - An address decode window struct. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data -+* from registers. -+* -+*******************************************************************************/ -+static MV_STATUS sataWinOverlapDetect(int dev, MV_U32 winNum, -+ MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 winNumIndex; -+ MV_SATA_DEC_WIN addrDecWin; -+ -+ for(winNumIndex=0; winNumIndex= MV_SATA_MAX_ADDR_DECODE_WIN) -+ { -+ mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlapps with current windows */ -+ if (MV_TRUE == sataWinOverlapDetect(dev, winNum, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); -+ return MV_ERROR; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvSataWinSet:Error setting SATA window %d to "\ -+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, -+ mvCtrlTargetNameGet(pAddrDecWin->target), -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ decRegs.baseReg = 0; -+ decRegs.sizeReg = 0; -+ -+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) -+ { -+ mvOsPrintf("%s: mvCtrlAddrDecToReg Failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); -+ -+ /* set attributes */ -+ decRegs.sizeReg &= ~MV_SATA_WIN_ATTR_MASK; -+ decRegs.sizeReg |= (targetAttribs.attrib << MV_SATA_WIN_ATTR_OFFSET); -+ -+ /* set target ID */ -+ decRegs.sizeReg &= ~MV_SATA_WIN_TARGET_MASK; -+ decRegs.sizeReg |= (targetAttribs.targetId << MV_SATA_WIN_TARGET_OFFSET); -+ -+ if (pAddrDecWin->enable == MV_TRUE) -+ { -+ decRegs.sizeReg |= MV_SATA_WIN_ENABLE_MASK; -+ } -+ else -+ { -+ decRegs.sizeReg &= ~MV_SATA_WIN_ENABLE_MASK; -+ } -+ -+ MV_REG_WRITE( MV_SATA_WIN_CTRL_REG(dev, winNum), decRegs.sizeReg); -+ MV_REG_WRITE( MV_SATA_WIN_BASE_REG(dev, winNum), decRegs.baseReg); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSataWinGet - Get SATA peripheral target address window. -+* -+* DESCRIPTION: -+* Get SATA peripheral target address window. -+* -+* INPUT: -+* winNum - SATA target address decode window number. -+* -+* OUTPUT: -+* pAddrDecWin - SATA target window data structure. -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvSataWinGet(int dev, MV_U32 winNum, MV_SATA_DEC_WIN *pAddrDecWin) -+{ -+ MV_DEC_REGS decRegs; -+ MV_TARGET_ATTRIB targetAttrib; -+ -+ /* Parameter checking */ -+ if (winNum >= MV_SATA_MAX_ADDR_DECODE_WIN) -+ { -+ mvOsPrintf("%s (dev=%d): ERR. Invalid winNum %d\n", -+ __FUNCTION__, dev, winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ decRegs.baseReg = MV_REG_READ( MV_SATA_WIN_BASE_REG(dev, winNum) ); -+ decRegs.sizeReg = MV_REG_READ( MV_SATA_WIN_CTRL_REG(dev, winNum) ); -+ -+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs, &pAddrDecWin->addrWin) ) -+ { -+ mvOsPrintf("%s: mvCtrlRegToAddrDec Failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ /* attrib and targetId */ -+ targetAttrib.attrib = (decRegs.sizeReg & MV_SATA_WIN_ATTR_MASK) >> -+ MV_SATA_WIN_ATTR_OFFSET; -+ targetAttrib.targetId = (decRegs.sizeReg & MV_SATA_WIN_TARGET_MASK) >> -+ MV_SATA_WIN_TARGET_OFFSET; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ /* Check if window is enabled */ -+ if(decRegs.sizeReg & MV_SATA_WIN_ENABLE_MASK) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ } -+ return MV_OK; -+} -+/******************************************************************************* -+* mvSataAddrDecShow - Print the SATA address decode map. -+* -+* DESCRIPTION: -+* This function print the SATA address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvSataAddrDecShow(MV_VOID) -+{ -+ -+ MV_SATA_DEC_WIN win; -+ int i,j; -+ -+ -+ -+ for( j = 0; j < MV_SATA_MAX_CHAN; j++ ) -+ { -+ if (MV_FALSE == mvCtrlPwrClckGet(SATA_UNIT_ID, j)) -+ return; -+ -+ mvOsOutput( "\n" ); -+ mvOsOutput( "SATA %d:\n", j ); -+ mvOsOutput( "----\n" ); -+ -+ for( i = 0; i < MV_SATA_MAX_ADDR_DECODE_WIN; i++ ) -+ { -+ memset( &win, 0, sizeof(MV_SATA_DEC_WIN) ); -+ -+ mvOsOutput( "win%d - ", i ); -+ -+ if( mvSataWinGet(j, i, &win ) == MV_OK ) -+ { -+ if( win.enable ) -+ { -+ mvOsOutput( "%s base %08x, ", -+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); -+ mvOsOutput( "...." ); -+ -+ mvSizePrint( win.addrWin.size ); -+ -+ mvOsOutput( "\n" ); -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ } -+ } -+ } -+} -+ -+ -+/******************************************************************************* -+* mvSataWinInit - Initialize the integrated SATA target address window. -+* -+* DESCRIPTION: -+* Initialize the SATA peripheral target address window. -+* -+* INPUT: -+* -+* -+* OUTPUT: -+* -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvSataWinInit(MV_VOID) -+{ -+ int winNum; -+ MV_SATA_DEC_WIN sataWin; -+ MV_CPU_DEC_WIN cpuAddrDecWin; -+ MV_U32 status, winPrioIndex = 0; -+ -+ /* Initiate Sata address decode */ -+ -+ /* First disable all address decode windows */ -+ for(winNum = 0; winNum < MV_SATA_MAX_ADDR_DECODE_WIN; winNum++) -+ { -+ MV_U32 regVal = MV_REG_READ(MV_SATA_WIN_CTRL_REG(0, winNum)); -+ regVal &= ~MV_SATA_WIN_ENABLE_MASK; -+ MV_REG_WRITE(MV_SATA_WIN_CTRL_REG(0, winNum), regVal); -+ } -+ -+ winNum = 0; -+ while( (sataAddrDecPrioTab[winPrioIndex] != TBL_TERM) && -+ (winNum < MV_SATA_MAX_ADDR_DECODE_WIN) ) -+ { -+ /* first get attributes from CPU If */ -+ status = mvCpuIfTargetWinGet(sataAddrDecPrioTab[winPrioIndex], -+ &cpuAddrDecWin); -+ -+ if(MV_NO_SUCH == status) -+ { -+ winPrioIndex++; -+ continue; -+ } -+ if (MV_OK != status) -+ { -+ mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ if (cpuAddrDecWin.enable == MV_TRUE) -+ { -+ sataWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; -+ sataWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; -+ sataWin.addrWin.size = cpuAddrDecWin.addrWin.size; -+ sataWin.enable = MV_TRUE; -+ sataWin.target = sataAddrDecPrioTab[winPrioIndex]; -+ -+ if(MV_OK != mvSataWinSet(0/*dev*/, winNum, &sataWin)) -+ { -+ return MV_ERROR; -+ } -+ winNum++; -+ } -+ winPrioIndex++; -+ } -+ return MV_OK; -+} -+ -+ -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,128 @@ -+ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#ifndef __INCMVSysSataAddrDech -+#define __INCMVSysSataAddrDech -+ -+#include "mvCommon.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+ -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+typedef struct _mvSataDecWin -+{ -+ MV_TARGET target; -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+} MV_SATA_DEC_WIN; -+ -+ -+#define MV_SATA_MAX_ADDR_DECODE_WIN 4 -+ -+#define MV_SATA_WIN_CTRL_REG(dev, win) (SATA_REG_BASE + 0x30 + ((win)<<4)) -+#define MV_SATA_WIN_BASE_REG(dev, win) (SATA_REG_BASE + 0x34 + ((win)<<4)) -+ -+/* BITs in Bridge Interrupt Cause and Mask registers */ -+#define MV_SATA_ADDR_DECODE_ERROR_BIT 0 -+#define MV_SATA_ADDR_DECODE_ERROR_MASK (1<= MV_SDMMC_MAX_ADDR_DECODE_WIN) -+ { -+ mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlapps with current windows */ -+ if (MV_TRUE == sdmmcWinOverlapDetect(dev, winNum, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); -+ return MV_ERROR; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvSdmmcWinSet:Error setting SDMMC window %d to "\ -+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, -+ mvCtrlTargetNameGet(pAddrDecWin->target), -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ decRegs.baseReg = 0; -+ decRegs.sizeReg = 0; -+ -+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) -+ { -+ mvOsPrintf("%s: mvCtrlAddrDecToReg Failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); -+ -+ /* set attributes */ -+ decRegs.sizeReg &= ~MV_SDMMC_WIN_ATTR_MASK; -+ decRegs.sizeReg |= (targetAttribs.attrib << MV_SDMMC_WIN_ATTR_OFFSET); -+ -+ /* set target ID */ -+ decRegs.sizeReg &= ~MV_SDMMC_WIN_TARGET_MASK; -+ decRegs.sizeReg |= (targetAttribs.targetId << MV_SDMMC_WIN_TARGET_OFFSET); -+ -+ if (pAddrDecWin->enable == MV_TRUE) -+ { -+ decRegs.sizeReg |= MV_SDMMC_WIN_ENABLE_MASK; -+ } -+ else -+ { -+ decRegs.sizeReg &= ~MV_SDMMC_WIN_ENABLE_MASK; -+ } -+ -+ MV_REG_WRITE( MV_SDMMC_WIN_CTRL_REG(dev, winNum), decRegs.sizeReg); -+ MV_REG_WRITE( MV_SDMMC_WIN_BASE_REG(dev, winNum), decRegs.baseReg); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSdmmcWinGet - Get SDMMC peripheral target address window. -+* -+* DESCRIPTION: -+* Get SDMMC peripheral target address window. -+* -+* INPUT: -+* winNum - SDMMC target address decode window number. -+*d -+* OUTPUT: -+* pAddrDecWin - SDMMC target window data structure. -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvSdmmcWinGet(int dev, MV_U32 winNum, MV_SDMMC_DEC_WIN *pAddrDecWin) -+{ -+ MV_DEC_REGS decRegs; -+ MV_TARGET_ATTRIB targetAttrib; -+ -+ /* Parameter checking */ -+ if (winNum >= MV_SDMMC_MAX_ADDR_DECODE_WIN) -+ { -+ mvOsPrintf("%s (dev=%d): ERR. Invalid winNum %d\n", -+ __FUNCTION__, dev, winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ decRegs.baseReg = MV_REG_READ( MV_SDMMC_WIN_BASE_REG(dev, winNum) ); -+ decRegs.sizeReg = MV_REG_READ( MV_SDMMC_WIN_CTRL_REG(dev, winNum) ); -+ -+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs, &pAddrDecWin->addrWin) ) -+ { -+ mvOsPrintf("%s: mvCtrlRegToAddrDec Failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ /* attrib and targetId */ -+ targetAttrib.attrib = (decRegs.sizeReg & MV_SDMMC_WIN_ATTR_MASK) >> -+ MV_SDMMC_WIN_ATTR_OFFSET; -+ targetAttrib.targetId = (decRegs.sizeReg & MV_SDMMC_WIN_TARGET_MASK) >> -+ MV_SDMMC_WIN_TARGET_OFFSET; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ /* Check if window is enabled */ -+ if(decRegs.sizeReg & MV_SDMMC_WIN_ENABLE_MASK) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ } -+ return MV_OK; -+} -+/******************************************************************************* -+* mvSdmmcAddrDecShow - Print the SDMMC address decode map. -+* -+* DESCRIPTION: -+* This function print the SDMMC address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvSdmmcAddrDecShow(MV_VOID) -+{ -+ -+ MV_SDMMC_DEC_WIN win; -+ int i,j=0; -+ -+ -+ -+ if (MV_FALSE == mvCtrlPwrClckGet(SDIO_UNIT_ID, 0)) -+ return; -+ -+ mvOsOutput( "\n" ); -+ mvOsOutput( "SDMMC %d:\n", j ); -+ mvOsOutput( "----\n" ); -+ -+ for( i = 0; i < MV_SDMMC_MAX_ADDR_DECODE_WIN; i++ ) -+ { -+ memset( &win, 0, sizeof(MV_SDMMC_DEC_WIN) ); -+ -+ mvOsOutput( "win%d - ", i ); -+ -+ if( mvSdmmcWinGet(j, i, &win ) == MV_OK ) -+ { -+ if( win.enable ) -+ { -+ mvOsOutput( "%s base %08x, ", -+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); -+ mvOsOutput( "...." ); -+ -+ mvSizePrint( win.addrWin.size ); -+ -+ mvOsOutput( "\n" ); -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ } -+ } -+} -+ -+ -+/******************************************************************************* -+* mvSdmmcWinInit - Initialize the integrated SDMMC target address window. -+* -+* DESCRIPTION: -+* Initialize the SDMMC peripheral target address window. -+* -+* INPUT: -+* -+* -+* OUTPUT: -+* -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvSdmmcWinInit(MV_VOID) -+{ -+ int winNum; -+ MV_SDMMC_DEC_WIN sdmmcWin; -+ MV_CPU_DEC_WIN cpuAddrDecWin; -+ MV_U32 status, winPrioIndex = 0; -+ -+ /* Initiate Sdmmc address decode */ -+ -+ /* First disable all address decode windows */ -+ for(winNum = 0; winNum < MV_SDMMC_MAX_ADDR_DECODE_WIN; winNum++) -+ { -+ MV_U32 regVal = MV_REG_READ(MV_SDMMC_WIN_CTRL_REG(0, winNum)); -+ regVal &= ~MV_SDMMC_WIN_ENABLE_MASK; -+ MV_REG_WRITE(MV_SDMMC_WIN_CTRL_REG(0, winNum), regVal); -+ } -+ -+ winNum = 0; -+ while( (sdmmcAddrDecPrioTab[winPrioIndex] != TBL_TERM) && -+ (winNum < MV_SDMMC_MAX_ADDR_DECODE_WIN) ) -+ { -+ /* first get attributes from CPU If */ -+ status = mvCpuIfTargetWinGet(sdmmcAddrDecPrioTab[winPrioIndex], -+ &cpuAddrDecWin); -+ -+ if(MV_NO_SUCH == status) -+ { -+ winPrioIndex++; -+ continue; -+ } -+ if (MV_OK != status) -+ { -+ mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ if (cpuAddrDecWin.enable == MV_TRUE) -+ { -+ sdmmcWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; -+ sdmmcWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; -+ sdmmcWin.addrWin.size = cpuAddrDecWin.addrWin.size; -+ sdmmcWin.enable = MV_TRUE; -+ sdmmcWin.target = sdmmcAddrDecPrioTab[winPrioIndex]; -+ -+ if(MV_OK != mvSdmmcWinSet(0/*dev*/, winNum, &sdmmcWin)) -+ { -+ return MV_ERROR; -+ } -+ winNum++; -+ } -+ winPrioIndex++; -+ } -+ return MV_OK; -+} -+ -+ -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,125 @@ -+ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#ifndef __INCMVSysSdmmcAddrDech -+#define __INCMVSysSdmmcAddrDech -+ -+#include "mvCommon.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+ -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+typedef struct _mvSdmmcDecWin -+{ -+ MV_TARGET target; -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+} MV_SDMMC_DEC_WIN; -+ -+ -+#define MV_SDMMC_MAX_ADDR_DECODE_WIN 4 -+ -+#define MV_SDMMC_WIN_CTRL_REG(dev, win) (MV_SDIO_REG_BASE + 0x108 + ((win)<<3)) -+#define MV_SDMMC_WIN_BASE_REG(dev, win) (MV_SDIO_REG_BASE + 0x10c + ((win)<<3)) -+ -+ -+/* BITs in Windows 0-3 Control and Base Registers */ -+#define MV_SDMMC_WIN_ENABLE_BIT 0 -+#define MV_SDMMC_WIN_ENABLE_MASK (1<= TDM_MBUS_MAX_WIN) -+ { -+ mvOsPrintf("mvTdmWinSet: ERR. Invalid win num %d\n",winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlapps with current windows */ -+ if (MV_TRUE == tdmWinOverlapDetect(winNum, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("mvTdmWinSet: ERR. Window %d overlap\n", winNum); -+ return MV_ERROR; -+ } -+ -+ /* check if address is aligned to the size */ -+ if (MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvTdmWinSet: Error setting TDM window %d to "\ -+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, -+ mvCtrlTargetNameGet(pAddrDecWin->target), -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ decRegs.baseReg = MV_REG_READ(TDM_WIN_BASE_REG(winNum)); -+ decRegs.sizeReg = (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_SIZE_MASK) >> TDM_WIN_SIZE_OFFS; -+ -+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) -+ { -+ mvOsPrintf("mvTdmWinSet: mvCtrlAddrDecToReg Failed\n"); -+ return MV_ERROR; -+ } -+ -+ mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); -+ -+ /* for the safe side we disable the window before writing the new -+ values */ -+ mvTdmWinEnable(winNum, MV_FALSE); -+ -+ ctrlReg |= (targetAttribs.attrib << TDM_WIN_ATTRIB_OFFS); -+ ctrlReg |= (targetAttribs.targetId << TDM_WIN_TARGET_OFFS); -+ ctrlReg |= (decRegs.sizeReg & TDM_WIN_SIZE_MASK); -+ -+ /* Write to address base and control registers */ -+ MV_REG_WRITE(TDM_WIN_BASE_REG(winNum), decRegs.baseReg); -+ MV_REG_WRITE(TDM_WIN_CTRL_REG(winNum), ctrlReg); -+ /* Enable address decode target window */ -+ if (pAddrDecWin->enable == MV_TRUE) -+ { -+ mvTdmWinEnable(winNum, MV_TRUE); -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvTdmWinGet - Get peripheral target address window. -+* -+* DESCRIPTION: -+* Get TDM peripheral target address window. -+* -+* INPUT: -+* winNum - TDM to target address decode window number. -+* -+* OUTPUT: -+* pAddrDecWin - TDM target window data structure. -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+ -+MV_STATUS mvTdmWinGet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin) -+{ -+ -+ MV_DEC_REGS decRegs; -+ MV_TARGET_ATTRIB targetAttrib; -+ -+ /* Parameter checking */ -+ if (winNum >= TDM_MBUS_MAX_WIN) -+ { -+ mvOsPrintf("mvTdmWinGet: ERR. Invalid winNum %d\n", winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ decRegs.baseReg = MV_REG_READ(TDM_WIN_BASE_REG(winNum)); -+ decRegs.sizeReg = (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_SIZE_MASK) >> TDM_WIN_SIZE_OFFS; -+ -+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) -+ { -+ mvOsPrintf("mvTdmWinGet: mvCtrlRegToAddrDec Failed \n"); -+ return MV_ERROR; -+ } -+ -+ /* attrib and targetId */ -+ targetAttrib.attrib = -+ (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ATTRIB_MASK) >> TDM_WIN_ATTRIB_OFFS; -+ targetAttrib.targetId = -+ (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_TARGET_MASK) >> TDM_WIN_TARGET_OFFS; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ /* Check if window is enabled */ -+ if (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ENABLE_MASK) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvTdmWinEnable - Enable/disable a TDM to target address window -+* -+* DESCRIPTION: -+* This function enable/disable a TDM to target address window. -+* According to parameter 'enable' the routine will enable the -+* window, thus enabling TDM accesses (before enabling the window it is -+* tested for overlapping). Otherwise, the window will be disabled. -+* -+* INPUT: -+* winNum - TDM to target address decode window number. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_ERROR if decode window number was wrong or enabled window overlapps. -+* -+*******************************************************************************/ -+MV_STATUS mvTdmWinEnable(int winNum, MV_BOOL enable) -+{ -+ MV_TDM_DEC_WIN addrDecWin; -+ -+ if (MV_TRUE == enable) -+ { -+ if (winNum >= TDM_MBUS_MAX_WIN) -+ { -+ mvOsPrintf("mvTdmWinEnable:ERR. Invalid winNum%d\n",winNum); -+ return MV_ERROR; -+ } -+ -+ /* First check for overlap with other enabled windows */ -+ /* Get current window */ -+ if (MV_OK != mvTdmWinGet(winNum, &addrDecWin)) -+ { -+ mvOsPrintf("mvTdmWinEnable:ERR. targetWinGet fail\n"); -+ return MV_ERROR; -+ } -+ /* Check for overlapping */ -+ if (MV_FALSE == tdmWinOverlapDetect(winNum, &(addrDecWin.addrWin))) -+ { -+ /* No Overlap. Enable address decode target window */ -+ MV_REG_BIT_SET(TDM_WIN_CTRL_REG(winNum), TDM_WIN_ENABLE_MASK); -+ } -+ else -+ { /* Overlap detected */ -+ mvOsPrintf("mvTdmWinEnable:ERR. Overlap detected\n"); -+ return MV_ERROR; -+ } -+ } -+ else -+ { -+ MV_REG_BIT_RESET(TDM_WIN_CTRL_REG(winNum), TDM_WIN_ENABLE_MASK); -+ } -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* tdmWinOverlapDetect - Detect TDM address windows overlapping -+* -+* DESCRIPTION: -+* An unpredicted behaviour is expected in case TDM address decode -+* windows overlapps. -+* This function detects TDM address decode windows overlapping of a -+* specified window. The function does not check the window itself for -+* overlapping. The function also skipps disabled address decode windows. -+* -+* INPUT: -+* winNum - address decode window number. -+* pAddrDecWin - An address decode window struct. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data -+* from registers. -+* -+*******************************************************************************/ -+static MV_STATUS tdmWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 winNumIndex; -+ MV_TDM_DEC_WIN addrDecWin; -+ -+ for (winNumIndex = 0; winNumIndex < TDM_MBUS_MAX_WIN; winNumIndex++) -+ { -+ /* Do not check window itself */ -+ if (winNumIndex == winNum) -+ { -+ continue; -+ } -+ /* Do not check disabled windows */ -+ if (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ENABLE_MASK) -+ { -+ /* Get window parameters */ -+ if (MV_OK != mvTdmWinGet(winNumIndex, &addrDecWin)) -+ { -+ DB(mvOsPrintf("dmaWinOverlapDetect: ERR. TargetWinGet failed\n")); -+ return MV_ERROR; -+ } -+ -+ if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin))) -+ { -+ return MV_TRUE; -+ } -+ } -+ } -+ return MV_FALSE; -+} -+ -+/******************************************************************************* -+* mvTdmAddrDecShow - Print the TDM address decode map. -+* -+* DESCRIPTION: -+* This function print the TDM address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvTdmAddrDecShow(MV_VOID) -+{ -+ MV_TDM_DEC_WIN win; -+ int i; -+ -+ mvOsOutput( "\n" ); -+ mvOsOutput( "TDM:\n" ); -+ mvOsOutput( "----\n" ); -+ -+ for( i = 0; i < TDM_MBUS_MAX_WIN; i++ ) -+ { -+ memset( &win, 0, sizeof(MV_TDM_DEC_WIN) ); -+ -+ mvOsOutput( "win%d - ", i ); -+ -+ if (mvTdmWinGet(i, &win ) == MV_OK ) -+ { -+ if( win.enable ) -+ { -+ mvOsOutput( "%s base %08x, ", -+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow); -+ mvOsOutput( "...." ); -+ mvSizePrint( win.addrWin.size ); -+ mvOsOutput( "\n" ); -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ } -+ } -+} -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,106 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvSysTdmh -+#define __INCmvSysTdmh -+ -+#include "ctrlEnv/sys/mvCpuIf.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+ -+typedef struct _mvTdmDecWin -+{ -+ MV_TARGET target; -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+} MV_TDM_DEC_WIN; -+ -+MV_STATUS mvTdmWinInit(MV_VOID); -+MV_STATUS mvTdmWinSet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin); -+MV_STATUS mvTdmWinGet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin); -+MV_STATUS mvTdmWinEnable(int winNum, MV_BOOL enable); -+MV_VOID mvTdmAddrDecShow(MV_VOID); -+ -+ -+#define TDM_MBUS_MAX_WIN 4 -+#define TDM_WIN_CTRL_REG(win) ((TDM_REG_BASE + 0x4030) + (win<<4)) -+#define TDM_WIN_BASE_REG(win) ((TDM_REG_BASE +0x4034) + (win<<4)) -+ -+/* TDM_WIN_CTRL_REG bits */ -+#define TDM_WIN_ENABLE_OFFS 0 -+#define TDM_WIN_ENABLE_MASK (1<= TSU_MAX_DECODE_WIN) -+ { -+ mvOsPrintf("mvTsuWinSet: ERR. Invalid win num %d\n",winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlapps with current windows */ -+ if(MV_TRUE == tsuWinOverlapDetect(winNum, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("mvTsuWinSet: ERR. Window %d overlap\n", winNum); -+ return MV_ERROR; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow,pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvTsuWinSet: Error setting TSU window %d to target " -+ "%s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, mvCtrlTargetNameGet(pAddrDecWin->target), -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ decRegs.baseReg = MV_REG_READ(MV_TSU_WIN_BASE_REG(winNum)); -+ decRegs.sizeReg = MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNum)); -+ -+ if(MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) -+ { -+ mvOsPrintf("mvTsuWinSet: mvCtrlAddrDecToReg Failed\n"); -+ return MV_ERROR; -+ } -+ -+ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); -+ -+ /* set attributes */ -+ decRegs.sizeReg &= ~TSU_WIN_CTRL_ATTR_MASK; -+ decRegs.sizeReg |= targetAttribs.attrib << TSU_WIN_CTRL_ATTR_OFFS; -+ /* set target ID */ -+ decRegs.sizeReg &= ~TSU_WIN_CTRL_TARGET_MASK; -+ decRegs.sizeReg |= targetAttribs.targetId << TSU_WIN_CTRL_TARGET_OFFS; -+ -+ /* for the safe side we disable the window before writing the new */ -+ /* values */ -+ mvTsuWinEnable(winNum, MV_FALSE); -+ MV_REG_WRITE(MV_TSU_WIN_CTRL_REG(winNum),decRegs.sizeReg); -+ -+ /* Write to address decode Size Register */ -+ MV_REG_WRITE(MV_TSU_WIN_BASE_REG(winNum), decRegs.baseReg); -+ -+ /* Enable address decode target window */ -+ if(pAddrDecWin->enable == MV_TRUE) -+ { -+ mvTsuWinEnable(winNum,MV_TRUE); -+ } -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvTsuWinGet -+* -+* DESCRIPTION: -+* Get TSU peripheral target address window. -+* -+* INPUT: -+* winNum - TSU to target address decode window number. -+* -+* OUTPUT: -+* pAddrDecWin - TSU target window data structure. -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvTsuWinGet(MV_U32 winNum, MV_TSU_DEC_WIN *pAddrDecWin) -+{ -+ MV_DEC_REGS decRegs; -+ MV_TARGET_ATTRIB targetAttrib; -+ -+ /* Parameter checking */ -+ if(winNum >= TSU_MAX_DECODE_WIN) -+ { -+ mvOsPrintf("mvTsuWinGet: ERR. Invalid winNum %d\n", winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ decRegs.baseReg = MV_REG_READ(MV_TSU_WIN_BASE_REG(winNum)); -+ decRegs.sizeReg = MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNum)); -+ -+ if(MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) -+ { -+ mvOsPrintf("mvTsuWinGet: mvCtrlRegToAddrDec Failed \n"); -+ return MV_ERROR; -+ } -+ -+ /* attrib and targetId */ -+ targetAttrib.attrib = -+ (decRegs.sizeReg & TSU_WIN_CTRL_ATTR_MASK) >> TSU_WIN_CTRL_ATTR_OFFS; -+ targetAttrib.targetId = -+ (decRegs.sizeReg & TSU_WIN_CTRL_TARGET_MASK) >> TSU_WIN_CTRL_TARGET_OFFS; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ /* Check if window is enabled */ -+ if((MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNum)) & TSU_WIN_CTRL_EN_MASK)) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ } -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvTsuWinEnable -+* -+* DESCRIPTION: -+* This function enable/disable a TSU to target address window. -+* According to parameter 'enable' the routine will enable the -+* window, thus enabling TSU accesses (before enabling the window it is -+* tested for overlapping). Otherwise, the window will be disabled. -+* -+* INPUT: -+* winNum - TSU to target address decode window number. -+* enable - Enable / disable parameter. -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_ERROR if decode window number was wrong or enabled window overlapps. -+* -+*******************************************************************************/ -+MV_STATUS mvTsuWinEnable(MV_U32 winNum,MV_BOOL enable) -+{ -+ MV_TSU_DEC_WIN addrDecWin; -+ -+ /* Parameter checking */ -+ if(winNum >= TSU_MAX_DECODE_WIN) -+ { -+ mvOsPrintf("mvTsuWinEnable: ERR. Invalid winNum%d\n",winNum); -+ return MV_ERROR; -+ } -+ -+ if(enable == MV_TRUE) -+ { -+ /* First check for overlap with other enabled windows */ -+ /* Get current window. */ -+ if(MV_OK != mvTsuWinGet(winNum,&addrDecWin)) -+ { -+ mvOsPrintf("mvTsuWinEnable: ERR. targetWinGet fail\n"); -+ return MV_ERROR; -+ } -+ /* Check for overlapping. */ -+ if(MV_FALSE == tsuWinOverlapDetect(winNum,&(addrDecWin.addrWin))) -+ { -+ /* No Overlap. Enable address decode target window */ -+ MV_REG_BIT_SET(MV_TSU_WIN_CTRL_REG(winNum), -+ TSU_WIN_CTRL_EN_MASK); -+ } -+ else -+ { -+ /* Overlap detected */ -+ mvOsPrintf("mvTsuWinEnable: ERR. Overlap detected\n"); -+ return MV_ERROR; -+ } -+ } -+ else -+ { -+ /* Disable address decode target window */ -+ MV_REG_BIT_RESET(MV_TSU_WIN_CTRL_REG(winNum), -+ TSU_WIN_CTRL_EN_MASK); -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvTsuWinTargetGet -+* -+* DESCRIPTION: -+* Get Window number associated with target -+* -+* INPUT: -+* target - Target ID to get the window number for. -+* OUTPUT: -+* -+* RETURN: -+* window number or 0xFFFFFFFF on error. -+* -+*******************************************************************************/ -+MV_U32 mvTsuWinTargetGet(MV_TARGET target) -+{ -+ MV_TSU_DEC_WIN decWin; -+ MV_U32 winNum; -+ -+ /* Check parameters */ -+ if(target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvTsuWinTargetGet: target %d is Illigal\n", target); -+ return 0xffffffff; -+ } -+ -+ for(winNum = 0; winNum < TSU_MAX_DECODE_WIN; winNum++) -+ { -+ if(mvTsuWinGet(winNum,&decWin) != MV_OK) -+ { -+ mvOsPrintf("mvTsuWinGet: window returned error\n"); -+ return 0xffffffff; -+ } -+ -+ if (decWin.enable == MV_TRUE) -+ { -+ if(decWin.target == target) -+ { -+ return winNum; -+ } -+ } -+ } -+ return 0xFFFFFFFF; -+} -+ -+ -+/******************************************************************************* -+* tsuWinOverlapDetect -+* -+* DESCRIPTION: -+* Detect TSU address windows overlapping -+* An unpredicted behaviur is expected in case TSU address decode -+* windows overlapps. -+* This function detects TSU address decode windows overlapping of a -+* specified window. The function does not check the window itself for -+* overlapping. The function also skipps disabled address decode windows. -+* -+* INPUT: -+* winNum - address decode window number. -+* pAddrDecWin - An address decode window struct. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data -+* from registers. -+* -+*******************************************************************************/ -+static MV_STATUS tsuWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 ctrlReg; -+ MV_U32 winNumIndex; -+ MV_TSU_DEC_WIN addrDecWin; -+ -+ for(winNumIndex = 0; winNumIndex < TSU_MAX_DECODE_WIN; winNumIndex++) -+ { -+ /* Do not check window itself */ -+ if(winNumIndex == winNum) -+ { -+ continue; -+ } -+ -+ /* Do not check disabled windows */ -+ ctrlReg = MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNumIndex)); -+ if((ctrlReg & TSU_WIN_CTRL_EN_MASK) == 0) -+ { -+ continue; -+ } -+ -+ /* Get window parameters */ -+ if (MV_OK != mvTsuWinGet(winNumIndex, &addrDecWin)) -+ { -+ mvOsPrintf("tsuWinOverlapDetect: ERR. mvTsuWinGet failed\n"); -+ return MV_ERROR; -+ } -+ -+ if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin))) -+ { -+ return MV_TRUE; -+ } -+ } -+ return MV_FALSE; -+} -+ -+ -+/******************************************************************************* -+* mvTsuAddrDecShow -+* -+* DESCRIPTION: -+* Print the TSU address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+void mvTsuAddrDecShow(void) -+{ -+ MV_TSU_DEC_WIN win; -+ int i; -+ -+ if (MV_FALSE == mvCtrlPwrClckGet(TS_UNIT_ID, 0)) -+ return; -+ -+ mvOsOutput( "\n" ); -+ mvOsOutput( "TSU:\n"); -+ mvOsOutput( "----\n" ); -+ -+ for(i = 0; i < TSU_MAX_DECODE_WIN; i++) -+ { -+ memset(&win, 0, sizeof(TSU_MAX_DECODE_WIN)); -+ mvOsOutput( "win%d - ", i ); -+ -+ if(mvTsuWinGet(i, &win ) == MV_OK ) -+ { -+ if(win.enable == MV_TRUE) -+ { -+ mvOsOutput("%s base %08x, ", -+ mvCtrlTargetNameGet(win.target), -+ win.addrWin.baseLow); -+ mvOsOutput( "...." ); -+ mvSizePrint(win.addrWin.size ); -+ mvOsOutput( "\n" ); -+ } -+ else -+ { -+ mvOsOutput( "disable\n" ); -+ } -+ } -+ } -+ return; -+} -+ -+ -+/******************************************************************************* -+* mvTsuInit -+* -+* DESCRIPTION: -+* Initialize the TSU unit, and get unit out of reset. -+* -+* INPUT: -+* coreClock - The core clock at which the TSU should operate. -+* mode - The mode on configure the unit into (serial/parallel). -+* memHandle - Memory handle used for memory allocations. -+* OUTPUT: -+* None. -+* RETURN: -+* MV_OK - on success, -+* -+*******************************************************************************/ -+MV_STATUS mvTsuInit(MV_TSU_CORE_CLOCK coreClock, MV_TSU_PORTS_MODE mode, -+ void *osHandle) -+{ -+ MV_STATUS status; -+ -+ status = mvTsuWinInit(); -+ if(status == MV_OK) -+ status = mvTsuHalInit(coreClock,mode,osHandle); -+ -+ return status; -+} -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,110 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvSysTsh -+#define __INCmvSysTsh -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* includes */ -+#include "ts/mvTsu.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+ -+#define TSU_MAX_DECODE_WIN 4 -+ -+ -+/*******************************************/ -+/* TSU Windows Registers */ -+/*******************************************/ -+#define MV_TSU_WIN_CTRL_REG(win) (TSU_GLOBAL_REG_BASE +0x30 + 0x10 * win) -+#define MV_TSU_WIN_BASE_REG(win) (TSU_GLOBAL_REG_BASE +0x34 + 0x10 * win) -+ -+/* TSU windows control register. */ -+#define TSU_WIN_CTRL_EN_MASK (0x1 << 0) -+#define TSU_WIN_CTRL_TARGET_OFFS 4 -+#define TSU_WIN_CTRL_TARGET_MASK (0xF << TSU_WIN_CTRL_TARGET_OFFS) -+#define TSU_WIN_CTRL_ATTR_OFFS 8 -+#define TSU_WIN_CTRL_ATTR_MASK (0xFF << TSU_WIN_CTRL_ATTR_OFFS) -+#define TSU_WIN_CTRL_SIZE_OFFS 16 -+#define TSU_WIN_CTRL_SIZE_MASK (0xFFFF << TSU_WIN_CTRL_SIZE_OFFS) -+ -+/* TSU windows base register. */ -+#define TSU_WIN_BASE_OFFS 16 -+#define TSU_WIN_BASE_MASK (0xFFFF << TSU_WIN_BASE_OFFS) -+ -+MV_STATUS mvTsuWinInit(void); -+ -+void mvTsuAddrDecShow(void); -+MV_STATUS mvTsuInit(MV_TSU_CORE_CLOCK coreClock, MV_TSU_PORTS_MODE mode, -+ void *osHandle); -+ -+#ifdef __cplusplus -+} -+#endif /* __cplusplus */ -+ -+#endif /* __INCmvTsh */ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.c ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.c 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,497 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "ctrlEnv/sys/mvSysUsb.h" -+ -+MV_TARGET usbAddrDecPrioTab[] = -+{ -+#if defined(MV_INCLUDE_SDRAM_CS0) -+ SDRAM_CS0, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS1) -+ SDRAM_CS1, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS2) -+ SDRAM_CS2, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS3) -+ SDRAM_CS3, -+#endif -+#if defined(MV_INCLUDE_CESA) && defined(USB_UNDERRUN_WA) -+ CRYPT_ENG, -+#endif -+#if defined(MV_INCLUDE_PEX) -+ PEX0_MEM, -+#endif -+ TBL_TERM -+}; -+ -+ -+ -+MV_STATUS mvUsbInit(int dev, MV_BOOL isHost) -+{ -+ MV_STATUS status; -+ -+ status = mvUsbWinInit(dev); -+ if(status != MV_OK) -+ return status; -+ -+ return mvUsbHalInit(dev, isHost); -+} -+ -+ -+/******************************************************************************* -+* usbWinOverlapDetect - Detect USB address windows overlapping -+* -+* DESCRIPTION: -+* An unpredicted behaviur is expected in case USB address decode -+* windows overlapps. -+* This function detects USB address decode windows overlapping of a -+* specified window. The function does not check the window itself for -+* overlapping. The function also skipps disabled address decode windows. -+* -+* INPUT: -+* winNum - address decode window number. -+* pAddrDecWin - An address decode window struct. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data -+* from registers. -+* -+*******************************************************************************/ -+static MV_STATUS usbWinOverlapDetect(int dev, MV_U32 winNum, -+ MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 winNumIndex; -+ MV_DEC_WIN addrDecWin; -+ -+ for(winNumIndex=0; winNumIndex= MV_USB_MAX_ADDR_DECODE_WIN) -+ { -+ mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlapps with current windows */ -+ if (MV_TRUE == usbWinOverlapDetect(dev, winNum, &pDecWin->addrWin)) -+ { -+ mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); -+ return MV_ERROR; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pDecWin->addrWin.baseLow, pDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvUsbWinSet:Error setting USB window %d to "\ -+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, -+ mvCtrlTargetNameGet(pDecWin->target), -+ pDecWin->addrWin.baseLow, -+ pDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ if(MV_OK != mvCtrlAddrDecToParams(pDecWin, &winParams)) -+ { -+ mvOsPrintf("%s: mvCtrlAddrDecToParams Failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ /* set Size, Attributes and TargetID */ -+ sizeReg = (((winParams.targetId << MV_USB_WIN_TARGET_OFFSET) & MV_USB_WIN_TARGET_MASK) | -+ ((winParams.attrib << MV_USB_WIN_ATTR_OFFSET) & MV_USB_WIN_ATTR_MASK) | -+ ((winParams.size << MV_USB_WIN_SIZE_OFFSET) & MV_USB_WIN_SIZE_MASK)); -+ -+#if defined(MV645xx) || defined(MV646xx) -+ /* If window is DRAM with HW cache coherency, make sure bit2 is set */ -+ sizeReg &= ~MV_USB_WIN_BURST_WR_LIMIT_MASK; -+ -+ if((MV_TARGET_IS_DRAM(pDecWin->target)) && -+ (pDecWin->addrWinAttr.cachePolicy != NO_COHERENCY)) -+ { -+ sizeReg |= MV_USB_WIN_BURST_WR_32BIT_LIMIT; -+ } -+ else -+ { -+ sizeReg |= MV_USB_WIN_BURST_WR_NO_LIMIT; -+ } -+#endif /* MV645xx || MV646xx */ -+ -+ if (pDecWin->enable == MV_TRUE) -+ { -+ sizeReg |= MV_USB_WIN_ENABLE_MASK; -+ } -+ else -+ { -+ sizeReg &= ~MV_USB_WIN_ENABLE_MASK; -+ } -+ -+ /* Update Base value */ -+ baseReg = (winParams.baseAddr & MV_USB_WIN_BASE_MASK); -+ -+ MV_REG_WRITE( MV_USB_WIN_CTRL_REG(dev, winNum), sizeReg); -+ MV_REG_WRITE( MV_USB_WIN_BASE_REG(dev, winNum), baseReg); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvUsbWinGet - Get USB peripheral target address window. -+* -+* DESCRIPTION: -+* Get USB peripheral target address window. -+* -+* INPUT: -+* winNum - USB target address decode window number. -+* -+* OUTPUT: -+* pDecWin - USB target window data structure. -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvUsbWinGet(int dev, MV_U32 winNum, MV_DEC_WIN *pDecWin) -+{ -+ MV_DEC_WIN_PARAMS winParam; -+ MV_U32 sizeReg, baseReg; -+ -+ /* Parameter checking */ -+ if (winNum >= MV_USB_MAX_ADDR_DECODE_WIN) -+ { -+ mvOsPrintf("%s (dev=%d): ERR. Invalid winNum %d\n", -+ __FUNCTION__, dev, winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ baseReg = MV_REG_READ( MV_USB_WIN_BASE_REG(dev, winNum) ); -+ sizeReg = MV_REG_READ( MV_USB_WIN_CTRL_REG(dev, winNum) ); -+ -+ /* Check if window is enabled */ -+ if(sizeReg & MV_USB_WIN_ENABLE_MASK) -+ { -+ pDecWin->enable = MV_TRUE; -+ -+ /* Extract window parameters from registers */ -+ winParam.targetId = (sizeReg & MV_USB_WIN_TARGET_MASK) >> MV_USB_WIN_TARGET_OFFSET; -+ winParam.attrib = (sizeReg & MV_USB_WIN_ATTR_MASK) >> MV_USB_WIN_ATTR_OFFSET; -+ winParam.size = (sizeReg & MV_USB_WIN_SIZE_MASK) >> MV_USB_WIN_SIZE_OFFSET; -+ winParam.baseAddr = (baseReg & MV_USB_WIN_BASE_MASK); -+ -+ /* Translate the decode window parameters to address decode struct */ -+ if (MV_OK != mvCtrlParamsToAddrDec(&winParam, pDecWin)) -+ { -+ mvOsPrintf("Failed to translate register parameters to USB address" \ -+ " decode window structure\n"); -+ return MV_ERROR; -+ } -+ } -+ else -+ { -+ pDecWin->enable = MV_FALSE; -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvUsbWinInit - -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvUsbWinInit(int dev) -+{ -+ MV_STATUS status; -+ MV_DEC_WIN usbWin; -+ MV_CPU_DEC_WIN cpuAddrDecWin; -+ int winNum; -+ MV_U32 winPrioIndex = 0; -+ -+ /* First disable all address decode windows */ -+ for(winNum = 0; winNum < MV_USB_MAX_ADDR_DECODE_WIN; winNum++) -+ { -+ MV_REG_BIT_RESET(MV_USB_WIN_CTRL_REG(dev, winNum), MV_USB_WIN_ENABLE_MASK); -+ } -+ -+ /* Go through all windows in user table until table terminator */ -+ winNum = 0; -+ while( (usbAddrDecPrioTab[winPrioIndex] != TBL_TERM) && -+ (winNum < MV_USB_MAX_ADDR_DECODE_WIN) ) -+ { -+ /* first get attributes from CPU If */ -+ status = mvCpuIfTargetWinGet(usbAddrDecPrioTab[winPrioIndex], -+ &cpuAddrDecWin); -+ -+ if(MV_NO_SUCH == status) -+ { -+ winPrioIndex++; -+ continue; -+ } -+ if (MV_OK != status) -+ { -+ mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ if (cpuAddrDecWin.enable == MV_TRUE) -+ { -+ usbWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; -+ usbWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; -+ usbWin.addrWin.size = cpuAddrDecWin.addrWin.size; -+ usbWin.enable = MV_TRUE; -+ usbWin.target = usbAddrDecPrioTab[winPrioIndex]; -+ -+#if defined(MV645xx) || defined(MV646xx) -+ /* Get the default attributes for that target window */ -+ mvCtrlDefAttribGet(usbWin.target, &usbWin.addrWinAttr); -+#endif /* MV645xx || MV646xx */ -+ -+ if(MV_OK != mvUsbWinSet(dev, winNum, &usbWin)) -+ { -+ return MV_ERROR; -+ } -+ winNum++; -+ } -+ winPrioIndex++; -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvUsbAddrDecShow - Print the USB address decode map. -+* -+* DESCRIPTION: -+* This function print the USB address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvUsbAddrDecShow(MV_VOID) -+{ -+ MV_DEC_WIN addrDecWin; -+ int i, winNum; -+ -+ mvOsOutput( "\n" ); -+ mvOsOutput( "USB:\n" ); -+ mvOsOutput( "----\n" ); -+ -+ for(i=0; i= XOR_MAX_ADDR_DEC_WIN) -+ { -+ DB(mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum)); -+ return MV_BAD_PARAM; -+ } -+ if (pAddrDecWin == NULL) -+ { -+ DB(mvOsPrintf("%s: ERR. pAddrDecWin is NULL pointer\n", __FUNCTION__ )); -+ return MV_BAD_PTR; -+ } -+ /* Check if the requested window overlaps with current windows */ -+ if (MV_TRUE == xorWinOverlapDetect(unit, winNum, &pAddrDecWin->addrWin)) -+ { -+ DB(mvOsPrintf("%s: ERR. Window %d overlap\n",__FUNCTION__,winNum)); -+ return MV_ERROR; -+ } -+ -+ xorDecRegs.baseReg = MV_REG_READ(XOR_BASE_ADDR_REG(unit,winNum)); -+ xorDecRegs.sizeReg = MV_REG_READ(XOR_SIZE_MASK_REG(unit,winNum)); -+ -+ /* Get Base Address and size registers values */ -+ if(MV_OK != mvCtrlAddrDecToReg(&pAddrDecWin->addrWin, &xorDecRegs)) -+ { -+ DB(mvOsPrintf("%s: ERR. Invalid addr dec window\n",__FUNCTION__)); -+ return MV_BAD_PARAM; -+ } -+ -+ -+ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); -+ -+ /* set attributes */ -+ xorDecRegs.baseReg &= ~XEBARX_ATTR_MASK; -+ xorDecRegs.baseReg |= targetAttribs.attrib << XEBARX_ATTR_OFFS; -+ /* set target ID */ -+ xorDecRegs.baseReg &= ~XEBARX_TARGET_MASK; -+ xorDecRegs.baseReg |= targetAttribs.targetId << XEBARX_TARGET_OFFS; -+ -+ -+ /* Write to address decode Base Address Register */ -+ MV_REG_WRITE(XOR_BASE_ADDR_REG(unit,winNum), xorDecRegs.baseReg); -+ -+ /* Write to Size Register */ -+ MV_REG_WRITE(XOR_SIZE_MASK_REG(unit,winNum), xorDecRegs.sizeReg); -+ -+ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) -+ { -+ if (pAddrDecWin->enable) -+ { -+ MV_REG_BIT_SET(XOR_WINDOW_CTRL_REG(unit,chan), -+ XEXWCR_WIN_EN_MASK(winNum)); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(XOR_WINDOW_CTRL_REG(unit,chan), -+ XEXWCR_WIN_EN_MASK(winNum)); -+ } -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvXorTargetWinGet - Get xor peripheral target address window. -+* -+* DESCRIPTION: -+* Get xor peripheral target address window. -+* -+* INPUT: -+* winNum - One of the possible XOR memory decode windows. -+* -+* OUTPUT: -+* base - Window base address. -+* size - Window size. -+* enable - window enable/disable. -+* -+* RETURN: -+* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_STATUS mvXorTargetWinGet(MV_U32 unit,MV_U32 winNum, MV_XOR_DEC_WIN *pAddrDecWin) -+{ -+ MV_DEC_REGS xorDecRegs; -+ MV_TARGET_ATTRIB targetAttrib; -+ MV_U32 chan=0,chanWinEn; -+ -+ /* Parameter checking */ -+ if (winNum >= XOR_MAX_ADDR_DEC_WIN) -+ { -+ DB(mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__ , winNum)); -+ return MV_ERROR; -+ } -+ -+ if (NULL == pAddrDecWin) -+ { -+ DB(mvOsPrintf("%s: ERR. pAddrDecWin is NULL pointer\n", __FUNCTION__ )); -+ return MV_BAD_PTR; -+ } -+ -+ chanWinEn = MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,0)) & XEXWCR_WIN_EN_MASK(winNum); -+ -+ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) /* we should scan here all channels per unit */ -+ { -+ /* Check if enable bit is equal for all channels */ -+ if ((MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,chan)) & -+ XEXWCR_WIN_EN_MASK(winNum)) != chanWinEn) -+ { -+ mvOsPrintf("%s: ERR. Window enable field must be equal in " -+ "all channels(chan=%d)\n",__FUNCTION__, chan); -+ return MV_ERROR; -+ } -+ } -+ -+ -+ -+ xorDecRegs.baseReg = MV_REG_READ(XOR_BASE_ADDR_REG(unit,winNum)); -+ xorDecRegs.sizeReg = MV_REG_READ(XOR_SIZE_MASK_REG(unit,winNum)); -+ -+ if (MV_OK != mvCtrlRegToAddrDec(&xorDecRegs, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("%s: ERR. mvCtrlRegToAddrDec failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ /* attrib and targetId */ -+ targetAttrib.attrib = -+ (xorDecRegs.baseReg & XEBARX_ATTR_MASK) >> XEBARX_ATTR_OFFS; -+ targetAttrib.targetId = -+ (xorDecRegs.baseReg & XEBARX_TARGET_MASK) >> XEBARX_TARGET_OFFS; -+ -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ if(chanWinEn) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else pAddrDecWin->enable = MV_FALSE; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvXorTargetWinEnable - Enable/disable a Xor address decode window -+* -+* DESCRIPTION: -+* This function enable/disable a XOR address decode window. -+* if parameter 'enable' == MV_TRUE the routine will enable the -+* window, thus enabling XOR accesses (before enabling the window it is -+* tested for overlapping). Otherwise, the window will be disabled. -+* -+* INPUT: -+* winNum - Decode window number. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_STATUS mvXorTargetWinEnable(MV_U32 unit,MV_U32 winNum, MV_BOOL enable) -+{ -+ MV_XOR_DEC_WIN addrDecWin; -+ MV_U32 chan; -+ -+ /* Parameter checking */ -+ if (winNum >= XOR_MAX_ADDR_DEC_WIN) -+ { -+ DB(mvOsPrintf("%s: ERR. Invalid winNum%d\n", __FUNCTION__, winNum)); -+ return MV_ERROR; -+ } -+ -+ if (enable == MV_TRUE) -+ { -+ /* Get current window */ -+ if (MV_OK != mvXorTargetWinGet(unit,winNum, &addrDecWin)) -+ { -+ DB(mvOsPrintf("%s: ERR. targetWinGet fail\n", __FUNCTION__)); -+ return MV_ERROR; -+ } -+ -+ /* Check for overlapping */ -+ if (MV_TRUE == xorWinOverlapDetect(unit,winNum, &(addrDecWin.addrWin))) -+ { -+ /* Overlap detected */ -+ DB(mvOsPrintf("%s: ERR. Overlap detected\n", __FUNCTION__)); -+ return MV_ERROR; -+ } -+ -+ /* No Overlap. Enable address decode target window */ -+ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) -+ { -+ MV_REG_BIT_SET(XOR_WINDOW_CTRL_REG(unit,chan), -+ XEXWCR_WIN_EN_MASK(winNum)); -+ } -+ -+ } -+ else -+ { -+ /* Disable address decode target window */ -+ -+ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) -+ { -+ MV_REG_BIT_RESET(XOR_WINDOW_CTRL_REG(unit,chan), -+ XEXWCR_WIN_EN_MASK(winNum)); -+ } -+ -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvXorSetProtWinSet - Configure access attributes of a XOR engine -+* to one of the XOR memory windows. -+* -+* DESCRIPTION: -+* Each engine can be configured with access attributes for each of the -+* memory spaces. This function sets access attributes -+* to a given window for the given engine -+* -+* INPUTS: -+* chan - One of the possible engines. -+* winNum - One of the possible XOR memory spaces. -+* access - Protection access rights. -+* write - Write rights. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_STATUS mvXorProtWinSet (MV_U32 unit,MV_U32 chan, MV_U32 winNum, MV_BOOL access, -+ MV_BOOL write) -+{ -+ MV_U32 temp; -+ -+ /* Parameter checking */ -+ if (chan >= MV_XOR_MAX_CHAN_PER_UNIT) -+ { -+ DB(mvOsPrintf("%s: ERR. Invalid chan num %d\n", __FUNCTION__ , chan)); -+ return MV_BAD_PARAM; -+ } -+ if (winNum >= XOR_MAX_ADDR_DEC_WIN) -+ { -+ DB(mvOsPrintf("%s: ERR. Invalid win num %d\n", __FUNCTION__, winNum)); -+ return MV_BAD_PARAM; -+ } -+ -+ temp = MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,chan)) & -+ (~XEXWCR_WIN_ACC_MASK(winNum)); -+ -+ /* if access is disable */ -+ if (!access) -+ { -+ /* disable access */ -+ temp |= XEXWCR_WIN_ACC_NO_ACC(winNum); -+ } -+ /* if access is enable */ -+ else -+ { -+ /* if write is enable */ -+ if (write) -+ { -+ /* enable write */ -+ temp |= XEXWCR_WIN_ACC_RW(winNum); -+ } -+ /* if write is disable */ -+ else -+ { -+ /* disable write */ -+ temp |= XEXWCR_WIN_ACC_RO(winNum); -+ } -+ } -+ MV_REG_WRITE(XOR_WINDOW_CTRL_REG(unit,chan),temp); -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvXorPciRemap - Set XOR remap register for PCI address windows. -+* -+* DESCRIPTION: -+* only Windows 0-3 can be remapped. -+* -+* INPUT: -+* winNum - window number -+* pAddrDecWin - pointer to address space window structure -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_STATUS mvXorPciRemap(MV_U32 unit,MV_U32 winNum, MV_U32 addrHigh) -+{ -+ /* Parameter checking */ -+ if (winNum >= XOR_MAX_REMAP_WIN) -+ { -+ DB(mvOsPrintf("%s: ERR. Invalid win num %d\n", __FUNCTION__, winNum)); -+ return MV_BAD_PARAM; -+ } -+ -+ MV_REG_WRITE(XOR_HIGH_ADDR_REMAP_REG(unit,winNum), addrHigh); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* xorWinOverlapDetect - Detect XOR address windows overlaping -+* -+* DESCRIPTION: -+* An unpredicted behaviour is expected in case XOR address decode -+* windows overlaps. -+* This function detects XOR address decode windows overlaping of a -+* specified window. The function does not check the window itself for -+* overlaping. The function also skipps disabled address decode windows. -+* -+* INPUT: -+* winNum - address decode window number. -+* pAddrDecWin - An address decode window struct. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data -+* from registers. -+* -+*******************************************************************************/ -+static MV_STATUS xorWinOverlapDetect(MV_U32 unit,MV_U32 winNum, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 baseAddrEnableReg; -+ MV_U32 winNumIndex,chan; -+ MV_XOR_DEC_WIN addrDecWin; -+ -+ if (pAddrWin == NULL) -+ { -+ DB(mvOsPrintf("%s: ERR. pAddrWin is NULL pointer\n", __FUNCTION__ )); -+ return MV_BAD_PTR; -+ } -+ -+ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) -+ { -+ /* Read base address enable register. Do not check disabled windows */ -+ baseAddrEnableReg = MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,chan)); -+ -+ for (winNumIndex = 0; winNumIndex < XOR_MAX_ADDR_DEC_WIN; winNumIndex++) -+ { -+ /* Do not check window itself */ -+ if (winNumIndex == winNum) -+ { -+ continue; -+ } -+ -+ /* Do not check disabled windows */ -+ if ((baseAddrEnableReg & XEXWCR_WIN_EN_MASK(winNumIndex)) == 0) -+ { -+ continue; -+ } -+ -+ /* Get window parameters */ -+ if (MV_OK != mvXorTargetWinGet(unit,winNumIndex, &addrDecWin)) -+ { -+ DB(mvOsPrintf("%s: ERR. TargetWinGet failed\n", __FUNCTION__ )); -+ return MV_ERROR; -+ } -+ -+ if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin))) -+ { -+ return MV_TRUE; -+ } -+ } -+ } -+ -+ return MV_FALSE; -+} -+ -+static MV_VOID mvXorAddrDecShowUnit(MV_U32 unit) -+{ -+ MV_XOR_DEC_WIN win; -+ int i; -+ -+ mvOsOutput( "\n" ); -+ mvOsOutput( "XOR %d:\n", unit ); -+ mvOsOutput( "----\n" ); -+ -+ for( i = 0; i < XOR_MAX_ADDR_DEC_WIN; i++ ) -+ { -+ memset( &win, 0, sizeof(MV_XOR_DEC_WIN) ); -+ -+ mvOsOutput( "win%d - ", i ); -+ -+ if( mvXorTargetWinGet(unit, i, &win ) == MV_OK ) -+ { -+ if( win.enable ) -+ { -+ mvOsOutput( "%s base %x, ", -+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); -+ -+ mvSizePrint( win.addrWin.size ); -+ -+ mvOsOutput( "\n" ); -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ } -+ } -+} -+ -+/******************************************************************************* -+* mvXorAddrDecShow - Print the XOR address decode map. -+* -+* DESCRIPTION: -+* This function print the XOR address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvXorAddrDecShow(MV_VOID) -+{ -+ int i; -+ -+ for( i = 0; i < MV_XOR_MAX_UNIT; i++ ) -+ mvXorAddrDecShowUnit(i); -+ -+} -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,140 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCMVSysXorh -+#define __INCMVSysXorh -+ -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+#include "ctrlEnv/sys/mvCpuIf.h" -+ -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+ -+#define XOR_MAX_ADDR_DEC_WIN 8 /* Maximum address decode windows */ -+#define XOR_MAX_REMAP_WIN 4 /* Maximum address arbiter windows */ -+ -+/* XOR Engine Address Decoding Register Map */ -+#define XOR_WINDOW_CTRL_REG(unit,chan) (XOR_UNIT_BASE(unit)+(0x240 + ((chan) * 4))) -+#define XOR_BASE_ADDR_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x250 + ((winNum) * 4))) -+#define XOR_SIZE_MASK_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x270 + ((winNum) * 4))) -+#define XOR_HIGH_ADDR_REMAP_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x290 + ((winNum) * 4))) -+ -+/* XOR Engine [0..1] Window Control Registers (XExWCR) */ -+#define XEXWCR_WIN_EN_OFFS(winNum) (winNum) -+#define XEXWCR_WIN_EN_MASK(winNum) (1 << (XEXWCR_WIN_EN_OFFS(winNum))) -+#define XEXWCR_WIN_EN_ENABLE(winNum) (1 << (XEXWCR_WIN_EN_OFFS(winNum))) -+#define XEXWCR_WIN_EN_DISABLE(winNum) (0 << (XEXWCR_WIN_EN_OFFS(winNum))) -+ -+#define XEXWCR_WIN_ACC_OFFS(winNum) ((2 * winNum) + 16) -+#define XEXWCR_WIN_ACC_MASK(winNum) (3 << (XEXWCR_WIN_ACC_OFFS(winNum))) -+#define XEXWCR_WIN_ACC_NO_ACC(winNum) (0 << (XEXWCR_WIN_ACC_OFFS(winNum))) -+#define XEXWCR_WIN_ACC_RO(winNum) (1 << (XEXWCR_WIN_ACC_OFFS(winNum))) -+#define XEXWCR_WIN_ACC_RW(winNum) (3 << (XEXWCR_WIN_ACC_OFFS(winNum))) -+ -+/* XOR Engine Base Address Registers (XEBARx) */ -+#define XEBARX_TARGET_OFFS (0) -+#define XEBARX_TARGET_MASK (0xF << XEBARX_TARGET_OFFS) -+#define XEBARX_ATTR_OFFS (8) -+#define XEBARX_ATTR_MASK (0xFF << XEBARX_ATTR_OFFS) -+#define XEBARX_BASE_OFFS (16) -+#define XEBARX_BASE_MASK (0xFFFF << XEBARX_BASE_OFFS) -+ -+/* XOR Engine Size Mask Registers (XESMRx) */ -+#define XESMRX_SIZE_MASK_OFFS (16) -+#define XESMRX_SIZE_MASK_MASK (0xFFFF << XESMRX_SIZE_MASK_OFFS) -+ -+/* XOR Engine High Address Remap Register (XEHARRx1) */ -+#define XEHARRX_REMAP_OFFS (0) -+#define XEHARRX_REMAP_MASK (0xFFFFFFFF << XEHARRX_REMAP_OFFS) -+ -+typedef struct _mvXorDecWin -+{ -+ MV_TARGET target; -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+}MV_XOR_DEC_WIN; -+ -+MV_STATUS mvXorInit (MV_VOID); -+MV_STATUS mvXorTargetWinSet(MV_U32 unit, MV_U32 winNum, -+ MV_XOR_DEC_WIN *pAddrDecWin); -+MV_STATUS mvXorTargetWinGet(MV_U32 unit, MV_U32 winNum, -+ MV_XOR_DEC_WIN *pAddrDecWin); -+MV_STATUS mvXorTargetWinEnable(MV_U32 unit, -+ MV_U32 winNum, MV_BOOL enable); -+MV_STATUS mvXorProtWinSet (MV_U32 unit,MV_U32 chan, MV_U32 winNum, MV_BOOL access, -+ MV_BOOL write); -+MV_STATUS mvXorPciRemap(MV_U32 unit, MV_U32 winNum, MV_U32 addrHigh); -+ -+MV_VOID mvXorAddrDecShow(MV_VOID); -+ -+#ifdef __cplusplus -+} -+#endif -+ -+#endif -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.c ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.c 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,75 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "device/mvDevice.h" -+ -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+ -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,74 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvDeviceH -+#define __INCmvDeviceH -+ -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+#include "device/mvDeviceRegs.h" -+ -+ -+#endif /* #ifndef __INCmvDeviceH */ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDeviceRegs.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDeviceRegs.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDeviceRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDeviceRegs.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,101 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvDeviceRegsH -+#define __INCmvDeviceRegsH -+ -+#ifndef MV_ASMLANGUAGE -+#include "ctrlEnv/mvCtrlEnvLib.h" -+/* This enumerator describes the Marvell controller possible devices that */ -+/* can be connected to its device interface. */ -+typedef enum _mvDevice -+{ -+#if defined(MV_INCLUDE_DEVICE_CS0) -+ DEV_CS0 = 0, /* Device connected to dev CS[0] */ -+#endif -+#if defined(MV_INCLUDE_DEVICE_CS1) -+ DEV_CS1 = 1, /* Device connected to dev CS[1] */ -+#endif -+#if defined(MV_INCLUDE_DEVICE_CS2) -+ DEV_CS2 = 2, /* Device connected to dev CS[2] */ -+#endif -+#if defined(MV_INCLUDE_DEVICE_CS3) -+ DEV_CS3 = 3, /* Device connected to dev CS[2] */ -+#endif -+#if defined(MV_INCLUDE_DEVICE_CS4) -+ DEV_CS4 = 4, /* Device connected to BOOT dev */ -+#endif -+ MV_DEV_MAX_CS = MV_DEVICE_MAX_CS -+}MV_DEVICE; -+ -+ -+#endif /* MV_ASMLANGUAGE */ -+ -+ -+#define NAND_CTRL_REG 0x10470 -+ -+#define NAND_ACTCEBOOT_BIT BIT1 -+ -+ -+#endif /* #ifndef __INCmvDeviceRegsH */ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.c ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.c 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,211 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+*******************************************************************************/ -+/******************************************************************************* -+* mvOsCpuArchLib.c - Marvell CPU architecture library -+* -+* DESCRIPTION: -+* This library introduce Marvell API for OS dependent CPU architecture -+* APIs. This library introduce single CPU architecture services APKI -+* cross OS. -+* -+* DEPENDENCIES: -+* None. -+* -+*******************************************************************************/ -+ -+/* includes */ -+#include -+#include "mvOs.h" -+ -+static MV_U32 read_p15_c0 (void); -+ -+/* defines */ -+#define ARM_ID_REVISION_OFFS 0 -+#define ARM_ID_REVISION_MASK (0xf << ARM_ID_REVISION_OFFS) -+ -+#define ARM_ID_PART_NUM_OFFS 4 -+#define ARM_ID_PART_NUM_MASK (0xfff << ARM_ID_PART_NUM_OFFS) -+ -+#define ARM_ID_ARCH_OFFS 16 -+#define ARM_ID_ARCH_MASK (0xf << ARM_ID_ARCH_OFFS) -+ -+#define ARM_ID_VAR_OFFS 20 -+#define ARM_ID_VAR_MASK (0xf << ARM_ID_VAR_OFFS) -+ -+#define ARM_ID_ASCII_OFFS 24 -+#define ARM_ID_ASCII_MASK (0xff << ARM_ID_ASCII_OFFS) -+ -+ -+ -+void* mvOsIoCachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, -+ MV_U32 *memHandle) -+{ -+ void *p = kmalloc( size, GFP_KERNEL ); -+ *pPhyAddr = pci_map_single( osHandle, p, 0, PCI_DMA_BIDIRECTIONAL ); -+ return p; -+} -+void* mvOsIoUncachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, -+ MV_U32 *memHandle) -+{ -+ return pci_alloc_consistent( osHandle, size, (dma_addr_t *)pPhyAddr ); -+} -+ -+void mvOsIoUncachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, -+ MV_U32 memHandle) -+{ -+ return pci_free_consistent( osHandle, size, pVirtAddr, (dma_addr_t)phyAddr ); -+} -+ -+void mvOsIoCachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, -+ MV_U32 memHandle ) -+{ -+ return kfree( pVirtAddr ); -+} -+ -+int mvOsRand(void) -+{ -+ int rand; -+ get_random_bytes(&rand, sizeof(rand) ); -+ return rand; -+} -+ -+/******************************************************************************* -+* mvOsCpuVerGet() - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit CPU Revision -+* -+*******************************************************************************/ -+MV_U32 mvOsCpuRevGet( MV_VOID ) -+{ -+ return ((read_p15_c0() & ARM_ID_REVISION_MASK ) >> ARM_ID_REVISION_OFFS); -+} -+/******************************************************************************* -+* mvOsCpuPartGet() - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit CPU Part number -+* -+*******************************************************************************/ -+MV_U32 mvOsCpuPartGet( MV_VOID ) -+{ -+ return ((read_p15_c0() & ARM_ID_PART_NUM_MASK ) >> ARM_ID_PART_NUM_OFFS); -+} -+/******************************************************************************* -+* mvOsCpuArchGet() - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit CPU Architicture number -+* -+*******************************************************************************/ -+MV_U32 mvOsCpuArchGet( MV_VOID ) -+{ -+ return ((read_p15_c0() & ARM_ID_ARCH_MASK ) >> ARM_ID_ARCH_OFFS); -+} -+/******************************************************************************* -+* mvOsCpuVarGet() - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit CPU Variant number -+* -+*******************************************************************************/ -+MV_U32 mvOsCpuVarGet( MV_VOID ) -+{ -+ return ((read_p15_c0() & ARM_ID_VAR_MASK ) >> ARM_ID_VAR_OFFS); -+} -+/******************************************************************************* -+* mvOsCpuAsciiGet() - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit CPU Variant number -+* -+*******************************************************************************/ -+MV_U32 mvOsCpuAsciiGet( MV_VOID ) -+{ -+ return ((read_p15_c0() & ARM_ID_ASCII_MASK ) >> ARM_ID_ASCII_OFFS); -+} -+ -+ -+ -+/* -+static unsigned long read_p15_c0 (void) -+*/ -+/* read co-processor 15, register #0 (ID register) */ -+static MV_U32 read_p15_c0 (void) -+{ -+ MV_U32 value; -+ -+ __asm__ __volatile__( -+ "mrc p15, 0, %0, c0, c0, 0 @ read control reg\n" -+ : "=r" (value) -+ : -+ : "memory"); -+ -+ return value; -+} -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,423 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+*******************************************************************************/ -+#ifndef _MV_OS_LNX_H_ -+#define _MV_OS_LNX_H_ -+ -+ -+#ifdef __KERNEL__ -+/* for kernel space */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "dbg-trace.h" -+ -+extern void mv_early_printk(char *fmt,...); -+ -+#define MV_ASM __asm__ __volatile__ -+#define INLINE inline -+#define MV_TRC_REC TRC_REC -+#define mvOsPrintf printk -+#define mvOsEarlyPrintf mv_early_printk -+#define mvOsOutput printk -+#define mvOsSPrintf sprintf -+#define mvOsMalloc(_size_) kmalloc(_size_,GFP_ATOMIC) -+#define mvOsFree kfree -+#define mvOsMemcpy memcpy -+#define mvOsSleep(_mils_) mdelay(_mils_) -+#define mvOsTaskLock() -+#define mvOsTaskUnlock() -+#define strtol simple_strtoul -+#define mvOsDelay(x) mdelay(x) -+#define mvOsUDelay(x) udelay(x) -+#define mvCopyFromOs copy_from_user -+#define mvCopyToOs copy_to_user -+ -+ -+#include "mvTypes.h" -+#include "mvCommon.h" -+ -+#ifdef MV_NDEBUG -+#define mvOsAssert(cond) -+#else -+#define mvOsAssert(cond) { do { if(!(cond)) { BUG(); } }while(0); } -+#endif /* MV_NDEBUG */ -+ -+#else /* __KERNEL__ */ -+ -+/* for user space applications */ -+#include -+#include -+#include -+#include -+ -+#define INLINE inline -+#define mvOsPrintf printf -+#define mvOsOutput printf -+#define mvOsMalloc(_size_) malloc(_size_) -+#define mvOsFree free -+#define mvOsAssert(cond) assert(cond) -+ -+#endif /* __KERNEL__ */ -+#define mvOsIoVirtToPhy(pDev, pVirtAddr) \ -+ pci_map_single( (pDev), (pVirtAddr), 0, PCI_DMA_BIDIRECTIONAL ) -+ -+#define mvOsCacheClear(pDev, p, size ) \ -+ pci_map_single( (pDev), (p), (size), PCI_DMA_BIDIRECTIONAL) -+ -+#define mvOsCacheFlush(pDev, p, size ) \ -+ pci_map_single( (pDev), (p), (size), PCI_DMA_TODEVICE) -+ -+#define mvOsCacheInvalidate(pDev, p, size) \ -+ pci_map_single( (pDev), (p), (size), PCI_DMA_FROMDEVICE ) -+ -+#define mvOsCacheUnmap(pDev, phys, size) \ -+ pci_unmap_single( (pDev), (dma_addr_t)(phys), (size), PCI_DMA_FROMDEVICE ) -+ -+ -+#define CPU_PHY_MEM(x) (MV_U32)x -+#define CPU_MEMIO_CACHED_ADDR(x) (void*)x -+#define CPU_MEMIO_UNCACHED_ADDR(x) (void*)x -+ -+ -+/* CPU architecture dependent 32, 16, 8 bit read/write IO addresses */ -+#define MV_MEMIO32_WRITE(addr, data) \ -+ ((*((volatile unsigned int*)(addr))) = ((unsigned int)(data))) -+ -+#define MV_MEMIO32_READ(addr) \ -+ ((*((volatile unsigned int*)(addr)))) -+ -+#define MV_MEMIO16_WRITE(addr, data) \ -+ ((*((volatile unsigned short*)(addr))) = ((unsigned short)(data))) -+ -+#define MV_MEMIO16_READ(addr) \ -+ ((*((volatile unsigned short*)(addr)))) -+ -+#define MV_MEMIO8_WRITE(addr, data) \ -+ ((*((volatile unsigned char*)(addr))) = ((unsigned char)(data))) -+ -+#define MV_MEMIO8_READ(addr) \ -+ ((*((volatile unsigned char*)(addr)))) -+ -+ -+/* No Fast Swap implementation (in assembler) for ARM */ -+#define MV_32BIT_LE_FAST(val) MV_32BIT_LE(val) -+#define MV_16BIT_LE_FAST(val) MV_16BIT_LE(val) -+#define MV_32BIT_BE_FAST(val) MV_32BIT_BE(val) -+#define MV_16BIT_BE_FAST(val) MV_16BIT_BE(val) -+ -+/* 32 and 16 bit read/write in big/little endian mode */ -+ -+/* 16bit write in little endian mode */ -+#define MV_MEMIO_LE16_WRITE(addr, data) \ -+ MV_MEMIO16_WRITE(addr, MV_16BIT_LE_FAST(data)) -+ -+/* 16bit read in little endian mode */ -+static __inline MV_U16 MV_MEMIO_LE16_READ(MV_U32 addr) -+{ -+ MV_U16 data; -+ -+ data= (MV_U16)MV_MEMIO16_READ(addr); -+ -+ return (MV_U16)MV_16BIT_LE_FAST(data); -+} -+ -+/* 32bit write in little endian mode */ -+#define MV_MEMIO_LE32_WRITE(addr, data) \ -+ MV_MEMIO32_WRITE(addr, MV_32BIT_LE_FAST(data)) -+ -+/* 32bit read in little endian mode */ -+static __inline MV_U32 MV_MEMIO_LE32_READ(MV_U32 addr) -+{ -+ MV_U32 data; -+ -+ data= (MV_U32)MV_MEMIO32_READ(addr); -+ -+ return (MV_U32)MV_32BIT_LE_FAST(data); -+} -+ -+static __inline void mvOsBCopy(char* srcAddr, char* dstAddr, int byteCount) -+{ -+ while(byteCount != 0) -+ { -+ *dstAddr = *srcAddr; -+ dstAddr++; -+ srcAddr++; -+ byteCount--; -+ } -+} -+ -+static INLINE MV_U64 mvOsDivMod64(MV_U64 divided, MV_U64 divisor, MV_U64* modulu) -+{ -+ MV_U64 division = 0; -+ -+ if(divisor == 1) -+ return divided; -+ -+ while(divided >= divisor) -+ { -+ division++; -+ divided -= divisor; -+ } -+ if (modulu != NULL) -+ *modulu = divided; -+ -+ return division; -+} -+ -+#if defined(MV_BRIDGE_SYNC_REORDER) -+extern MV_U32 *mvUncachedParam; -+ -+static __inline void mvOsBridgeReorderWA(void) -+{ -+ volatile MV_U32 val = 0; -+ -+ val = mvUncachedParam[0]; -+} -+#endif -+ -+ -+/* Flash APIs */ -+#define MV_FL_8_READ MV_MEMIO8_READ -+#define MV_FL_16_READ MV_MEMIO_LE16_READ -+#define MV_FL_32_READ MV_MEMIO_LE32_READ -+#define MV_FL_8_DATA_READ MV_MEMIO8_READ -+#define MV_FL_16_DATA_READ MV_MEMIO16_READ -+#define MV_FL_32_DATA_READ MV_MEMIO32_READ -+#define MV_FL_8_WRITE MV_MEMIO8_WRITE -+#define MV_FL_16_WRITE MV_MEMIO_LE16_WRITE -+#define MV_FL_32_WRITE MV_MEMIO_LE32_WRITE -+#define MV_FL_8_DATA_WRITE MV_MEMIO8_WRITE -+#define MV_FL_16_DATA_WRITE MV_MEMIO16_WRITE -+#define MV_FL_32_DATA_WRITE MV_MEMIO32_WRITE -+ -+ -+/* CPU cache information */ -+#define CPU_I_CACHE_LINE_SIZE 32 /* 2do: replace 32 with linux core macro */ -+#define CPU_D_CACHE_LINE_SIZE 32 /* 2do: replace 32 with linux core macro */ -+ -+#ifdef CONFIG_L2_CACHE_ENABLE -+/* Data cache flush one line */ -+#define mvOsCacheLineFlushInv(handle, addr) \ -+{ \ -+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c14, 1" : : "r" (addr));\ -+ __asm__ __volatile__ ("mcr p15, 1, %0, c15, c10, 1" : : "r" (addr));\ -+ __asm__ __volatile__ ("mcr p15, 0, r0, c7, c10, 4"); \ -+} -+ -+#else -+ -+/* Data cache flush one line */ -+#define mvOsCacheLineFlushInv(handle, addr) \ -+{ \ -+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c14, 1" : : "r" (addr));\ -+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" : : "r" (addr)); \ -+} -+#endif -+ -+#ifdef CONFIG_L2_CACHE_ENABLE -+#define mvOsCacheLineInv(handle,addr) \ -+{ \ -+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c6, 1" : : "r" (addr)); \ -+ __asm__ __volatile__ ("mcr p15, 1, %0, c15, c11, 1" : : "r" (addr)); \ -+} -+#else -+#define mvOsCacheLineInv(handle,addr) \ -+{ \ -+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c6, 1" : : "r" (addr)); \ -+} -+#endif -+ -+#ifdef CONFIG_L2_CACHE_ENABLE -+/* Data cache flush one line */ -+#define mvOsCacheLineFlush(handle, addr) \ -+{ \ -+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 1" : : "r" (addr));\ -+ __asm__ __volatile__ ("mcr p15, 1, %0, c15, c9, 1" : : "r" (addr));\ -+ __asm__ __volatile__ ("mcr p15, 0, r0, c7, c10, 4"); \ -+} -+ -+#else -+/* Data cache flush one line */ -+#define mvOsCacheLineFlush(handle, addr) \ -+{ \ -+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 1" : : "r" (addr));\ -+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" : : "r" (addr)); \ -+} -+#endif -+ -+static __inline void mvOsPrefetch(const void *ptr) -+{ -+#ifdef CONFIG_USE_DSP -+ __asm__ __volatile__( -+ "pld\t%0" -+ : -+ : "o" (*(char *)ptr) -+ : "cc"); -+#else -+ return; -+#endif -+} -+ -+ -+/* Flush CPU pipe */ -+#define CPU_PIPE_FLUSH -+ -+ -+ -+ -+ -+/* register manipulations */ -+ -+/****************************************************************************** -+* This debug function enable the write of each register that u-boot access to -+* to an array in the DRAM, the function record only MV_REG_WRITE access. -+* The function could not be operate when booting from flash. -+* In order to print the array we use the printreg command. -+******************************************************************************/ -+/* #define REG_DEBUG */ -+#if defined(REG_DEBUG) -+extern int reg_arry[2048][2]; -+extern int reg_arry_index; -+#endif -+ -+/* Marvell controller register read/write macros */ -+#define MV_REG_VALUE(offset) \ -+ (MV_MEMIO32_READ((INTER_REGS_BASE | (offset)))) -+ -+#define MV_REG_READ(offset) \ -+ (MV_MEMIO_LE32_READ(INTER_REGS_BASE | (offset))) -+ -+#if defined(REG_DEBUG) -+#define MV_REG_WRITE(offset, val) \ -+ MV_MEMIO_LE32_WRITE((INTER_REGS_BASE | (offset)), (val)); \ -+ { \ -+ reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\ -+ reg_arry[reg_arry_index][1] = (val);\ -+ reg_arry_index++;\ -+ } -+#else -+#define MV_REG_WRITE(offset, val) \ -+ MV_MEMIO_LE32_WRITE((INTER_REGS_BASE | (offset)), (val)); -+#endif -+ -+#define MV_REG_BYTE_READ(offset) \ -+ (MV_MEMIO8_READ((INTER_REGS_BASE | (offset)))) -+ -+#if defined(REG_DEBUG) -+#define MV_REG_BYTE_WRITE(offset, val) \ -+ MV_MEMIO8_WRITE((INTER_REGS_BASE | (offset)), (val)); \ -+ { \ -+ reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\ -+ reg_arry[reg_arry_index][1] = (val);\ -+ reg_arry_index++;\ -+ } -+#else -+#define MV_REG_BYTE_WRITE(offset, val) \ -+ MV_MEMIO8_WRITE((INTER_REGS_BASE | (offset)), (val)) -+#endif -+ -+#if defined(REG_DEBUG) -+#define MV_REG_BIT_SET(offset, bitMask) \ -+ (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ -+ (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) | \ -+ MV_32BIT_LE_FAST(bitMask)))); \ -+ { \ -+ reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\ -+ reg_arry[reg_arry_index][1] = (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)));\ -+ reg_arry_index++;\ -+ } -+#else -+#define MV_REG_BIT_SET(offset, bitMask) \ -+ (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ -+ (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) | \ -+ MV_32BIT_LE_FAST(bitMask)))) -+#endif -+ -+#if defined(REG_DEBUG) -+#define MV_REG_BIT_RESET(offset,bitMask) \ -+ (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ -+ (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) & \ -+ MV_32BIT_LE_FAST(~bitMask)))); \ -+ { \ -+ reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\ -+ reg_arry[reg_arry_index][1] = (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)));\ -+ reg_arry_index++;\ -+ } -+#else -+#define MV_REG_BIT_RESET(offset,bitMask) \ -+ (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ -+ (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) & \ -+ MV_32BIT_LE_FAST(~bitMask)))) -+#endif -+ -+ -+ -+/* ARM architecture APIs */ -+MV_U32 mvOsCpuRevGet (MV_VOID); -+MV_U32 mvOsCpuPartGet (MV_VOID); -+MV_U32 mvOsCpuArchGet (MV_VOID); -+MV_U32 mvOsCpuVarGet (MV_VOID); -+MV_U32 mvOsCpuAsciiGet (MV_VOID); -+ -+/* Other APIs */ -+void* mvOsIoCachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, MV_U32 *memHandle); -+void* mvOsIoUncachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, MV_U32 *memHandle ); -+void mvOsIoUncachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, MV_U32 memHandle ); -+void mvOsIoCachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, MV_U32 memHandle ); -+int mvOsRand(void); -+ -+#endif /* _MV_OS_LNX_H_ */ -+ -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOsSata.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/linux_oss/mvOsSata.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOsSata.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/linux_oss/mvOsSata.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,158 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+*******************************************************************************/ -+/******************************************************************************* -+* mvOsLinux.h - O.S. interface header file for Linux -+* -+* DESCRIPTION: -+* This header file contains OS dependent definition under Linux -+* -+* DEPENDENCIES: -+* Linux kernel header files. -+* -+* FILE REVISION NUMBER: -+* $Revision: 1.1 $ -+*******************************************************************************/ -+ -+#ifndef __INCmvOsLinuxh -+#define __INCmvOsLinuxh -+ -+/* Includes */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include "mvOs.h" -+ -+ -+/* Definitions */ -+#define MV_DEFAULT_QUEUE_DEPTH 2 -+#define MV_SATA_SUPPORT_EDMA_SINGLE_DATA_REGION -+#define MV_SATA_SUPPORT_GEN2E_128_QUEUE_LEN -+ -+#ifdef CONFIG_MV88F6082 -+ #define MV_SATA_OVERRIDE_SW_QUEUE_SIZE -+ #define MV_SATA_REQUESTED_SW_QUEUE_SIZE 2 -+ #undef MV_SATA_SUPPORT_GEN2E_128_QUEUE_LEN -+#endif -+ -+/* System dependent macro for flushing CPU write cache */ -+#if defined (MV_BRIDGE_SYNC_REORDER) -+#define MV_CPU_WRITE_BUFFER_FLUSH() do { \ -+ wmb(); \ -+ mvOsBridgeReorderWA(); \ -+ } while (0) -+#else -+#define MV_CPU_WRITE_BUFFER_FLUSH() wmb() -+#endif /* CONFIG_MV78XX0 */ -+ -+/* System dependent little endian from / to CPU conversions */ -+#define MV_CPU_TO_LE16(x) cpu_to_le16(x) -+#define MV_CPU_TO_LE32(x) cpu_to_le32(x) -+ -+#define MV_LE16_TO_CPU(x) le16_to_cpu(x) -+#define MV_LE32_TO_CPU(x) le32_to_cpu(x) -+ -+#ifdef __BIG_ENDIAN_BITFIELD -+#define MV_BIG_ENDIAN_BITFIELD -+#endif -+ -+/* System dependent register read / write in byte/word/dword variants */ -+#define MV_REG_WRITE_BYTE(base, offset, val) writeb(val, base + offset) -+#define MV_REG_WRITE_WORD(base, offset, val) writew(val, base + offset) -+#define MV_REG_WRITE_DWORD(base, offset, val) writel(val, base + offset) -+#define MV_REG_READ_BYTE(base, offset) readb(base + offset) -+#define MV_REG_READ_WORD(base, offset) readw(base + offset) -+#define MV_REG_READ_DWORD(base, offset) readl(base + offset) -+ -+ -+/* Typedefs */ -+ -+/* System dependant typedefs */ -+typedef void *MV_VOID_PTR; -+typedef u32 *MV_U32_PTR; -+typedef u16 *MV_U16_PTR; -+typedef u8 *MV_U8_PTR; -+typedef char *MV_CHAR_PTR; -+typedef void *MV_BUS_ADDR_T; -+typedef unsigned long MV_CPU_FLAGS; -+ -+ -+/* Structures */ -+/* System dependent structure */ -+typedef struct mvOsSemaphore -+{ -+ int notUsed; -+} MV_OS_SEMAPHORE; -+ -+ -+/* Functions (User implemented)*/ -+ -+/* Semaphore init, take and release */ -+#define mvOsSemInit(x) MV_TRUE -+#define mvOsSemTake(x) -+#define mvOsSemRelease(x) -+ -+/* Interrupt masking and unmasking functions */ -+MV_CPU_FLAGS mvOsSaveFlagsAndMaskCPUInterrupts(MV_VOID); -+MV_VOID mvOsRestoreFlags(MV_CPU_FLAGS); -+ -+/* Delay function in micro seconds resolution */ -+void mvMicroSecondsDelay(MV_VOID_PTR, MV_U32); -+ -+/* Typedefs */ -+typedef enum mvBoolean -+{ -+ MV_SFALSE, MV_STRUE -+} MV_BOOLEAN; -+ -+/* System logging function */ -+#include "mvLog.h" -+/* Enable READ/WRITE Long SCSI command only when driver is compiled for debugging */ -+#ifdef MV_LOGGER -+#define MV_SATA_SUPPORT_READ_WRITE_LONG -+#endif -+ -+#define MV_IAL_LOG_ID 3 -+ -+#endif /* __INCmvOsLinuxh */ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mvSysHwConfig.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mvSysHwConfig.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mvSysHwConfig.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mvSysHwConfig.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,375 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+ -+*******************************************************************************/ -+/******************************************************************************* -+* mvSysHwCfg.h - Marvell system HW configuration file -+* -+* DESCRIPTION: -+* None. -+* -+* DEPENDENCIES: -+* None. -+* -+*******************************************************************************/ -+ -+#ifndef __INCmvSysHwConfigh -+#define __INCmvSysHwConfigh -+ -+#include "../../../../include/linux/autoconf.h" -+ -+#define CONFIG_MARVELL 1 -+ -+/* includes */ -+#define _1K 0x00000400 -+#define _4K 0x00001000 -+#define _8K 0x00002000 -+#define _16K 0x00004000 -+#define _32K 0x00008000 -+#define _64K 0x00010000 -+#define _128K 0x00020000 -+#define _256K 0x00040000 -+#define _512K 0x00080000 -+ -+#define _1M 0x00100000 -+#define _2M 0x00200000 -+#define _4M 0x00400000 -+#define _8M 0x00800000 -+#define _16M 0x01000000 -+#define _32M 0x02000000 -+#define _64M 0x04000000 -+#define _128M 0x08000000 -+#define _256M 0x10000000 -+#define _512M 0x20000000 -+ -+#define _1G 0x40000000 -+#define _2G 0x80000000 -+ -+/****************************************/ -+/* Soc supporeted Units definitions */ -+/****************************************/ -+ -+#ifdef CONFIG_MV_INCLUDE_PEX -+#define MV_INCLUDE_PEX -+#endif -+#ifdef CONFIG_MV_INCLUDE_TWSI -+#define MV_INCLUDE_TWSI -+#endif -+#ifdef CONFIG_MV_INCLUDE_CESA -+#define MV_INCLUDE_CESA -+#endif -+#ifdef CONFIG_MV_INCLUDE_GIG_ETH -+#define MV_INCLUDE_GIG_ETH -+#endif -+#ifdef CONFIG_MV_INCLUDE_INTEG_SATA -+#define MV_INCLUDE_INTEG_SATA -+#define MV_INCLUDE_SATA -+#endif -+#ifdef CONFIG_MV_INCLUDE_USB -+#define MV_INCLUDE_USB -+#define MV_USB_VOLTAGE_FIX -+#endif -+#ifdef CONFIG_MV_INCLUDE_NAND -+#define MV_INCLUDE_NAND -+#endif -+#ifdef CONFIG_MV_INCLUDE_TDM -+#define MV_INCLUDE_TDM -+#endif -+#ifdef CONFIG_MV_INCLUDE_XOR -+#define MV_INCLUDE_XOR -+#endif -+#ifdef CONFIG_MV_INCLUDE_TWSI -+#define MV_INCLUDE_TWSI -+#endif -+#ifdef CONFIG_MV_INCLUDE_UART -+#define MV_INCLUDE_UART -+#endif -+#ifdef CONFIG_MV_INCLUDE_SPI -+#define MV_INCLUDE_SPI -+#endif -+#ifdef CONFIG_MV_INCLUDE_SFLASH_MTD -+#define MV_INCLUDE_SFLASH_MTD -+#endif -+#ifdef CONFIG_MV_INCLUDE_AUDIO -+#define MV_INCLUDE_AUDIO -+#endif -+#ifdef CONFIG_MV_INCLUDE_TS -+#define MV_INCLUDE_TS -+#endif -+#ifdef CONFIG_MV_INCLUDE_SDIO -+#define MV_INCLUDE_SDIO -+#endif -+ -+ -+/* NAND flash stuff */ -+#ifdef CONFIG_MV_NAND_BOOT -+#define MV_NAND_BOOT -+#endif -+#ifdef CONFIG_MV_NAND -+#define MV_NAND -+#endif -+ -+/* SPI flash stuff */ -+#ifdef CONFIG_MV_SPI_BOOT -+#define MV_SPI_BOOT -+#endif -+ -+ -+/****************************************************************/ -+/************* General configuration ********************/ -+/****************************************************************/ -+ -+/* Enable Clock Power Control */ -+#define MV_INCLUDE_CLK_PWR_CNTRL -+ -+/* Disable the DEVICE BAR in the PEX */ -+#define MV_DISABLE_PEX_DEVICE_BAR -+ -+/* Allow the usage of early printings during initialization */ -+#define MV_INCLUDE_EARLY_PRINTK -+ -+/****************************************************************/ -+/************* NFP configuration ********************************/ -+/****************************************************************/ -+#define MV_NFP_SEC_Q_SIZE 64 -+#define MV_NFP_SEC_REQ_Q_SIZE 1000 -+ -+ -+ -+/****************************************************************/ -+/************* CESA configuration ********************/ -+/****************************************************************/ -+ -+#ifdef MV_INCLUDE_CESA -+ -+#define MV_CESA_MAX_CHAN 4 -+ -+/* Use 2K of SRAM */ -+#define MV_CESA_MAX_BUF_SIZE 1600 -+ -+#endif /* MV_INCLUDE_CESA */ -+ -+#if defined(CONFIG_MV_INCLUDE_GIG_ETH) -+ -+#ifdef CONFIG_MV_NFP_STATS -+#define MV_FP_STATISTICS -+#else -+#undef MV_FP_STATISTICS -+#endif -+/* Default configuration for SKB_REUSE: 0 - Disabled, 1 - Enabled */ -+#define MV_ETH_SKB_REUSE_DEFAULT 1 -+/* Default configuration for TX_EN workaround: 0 - Disabled, 1 - Enabled */ -+#define MV_ETH_TX_EN_DEFAULT 0 -+ -+/* un-comment if you want to perform tx_done from within the poll function */ -+/* #define ETH_TX_DONE_ISR */ -+ -+/* put descriptors in uncached memory */ -+/* #define ETH_DESCR_UNCACHED */ -+ -+/* Descriptors location: DRAM/internal-SRAM */ -+#define ETH_DESCR_IN_SDRAM -+#undef ETH_DESCR_IN_SRAM /* No integrated SRAM in 88Fxx81 devices */ -+ -+#if defined(ETH_DESCR_IN_SRAM) -+#if defined(ETH_DESCR_UNCACHED) -+ #define ETH_DESCR_CONFIG_STR "Uncached descriptors in integrated SRAM" -+#else -+ #define ETH_DESCR_CONFIG_STR "Cached descriptors in integrated SRAM" -+#endif -+#elif defined(ETH_DESCR_IN_SDRAM) -+#if defined(ETH_DESCR_UNCACHED) -+ #define ETH_DESCR_CONFIG_STR "Uncached descriptors in DRAM" -+#else -+ #define ETH_DESCR_CONFIG_STR "Cached descriptors in DRAM" -+#endif -+#else -+ #error "Ethernet descriptors location undefined" -+#endif /* ETH_DESCR_IN_SRAM or ETH_DESCR_IN_SDRAM*/ -+ -+/* SW Sync-Barrier: not relevant for 88fxx81*/ -+/* Reasnable to define this macro when descriptors in SRAM and buffers in DRAM */ -+/* In RX the CPU theoretically might see himself as the descriptor owner, */ -+/* although the buffer hadn't been written to DRAM yet. Performance cost. */ -+/* #define INCLUDE_SYNC_BARR */ -+ -+/* Buffers cache coherency method (buffers in DRAM) */ -+#ifndef MV_CACHE_COHER_SW -+/* Taken from mvCommon.h */ -+/* Memory uncached, HW or SW cache coherency is not needed */ -+#define MV_UNCACHED 0 -+/* Memory cached, HW cache coherency supported in WriteThrough mode */ -+#define MV_CACHE_COHER_HW_WT 1 -+/* Memory cached, HW cache coherency supported in WriteBack mode */ -+#define MV_CACHE_COHER_HW_WB 2 -+/* Memory cached, No HW cache coherency, Cache coherency must be in SW */ -+#define MV_CACHE_COHER_SW 3 -+ -+#endif -+ -+/* DRAM cache coherency configuration */ -+#define MV_CACHE_COHERENCY MV_CACHE_COHER_SW -+ -+ -+#define ETHER_DRAM_COHER MV_CACHE_COHER_SW /* No HW coherency in 88Fxx81 devices */ -+ -+#if (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WB) -+ #define ETH_SDRAM_CONFIG_STR "DRAM HW cache coherency (write-back)" -+#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WT) -+ #define ETH_SDRAM_CONFIG_STR "DRAM HW cache coherency (write-through)" -+#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) -+ #define ETH_SDRAM_CONFIG_STR "DRAM SW cache-coherency" -+#elif (ETHER_DRAM_COHER == MV_UNCACHED) -+# define ETH_SDRAM_CONFIG_STR "DRAM uncached" -+#else -+ #error "Ethernet-DRAM undefined" -+#endif /* ETHER_DRAM_COHER */ -+ -+ -+/****************************************************************/ -+/************* Ethernet driver configuration ********************/ -+/****************************************************************/ -+ -+/* port's default queueus */ -+#define ETH_DEF_TXQ 0 -+#define ETH_DEF_RXQ 0 -+ -+#define MV_ETH_RX_Q_NUM CONFIG_MV_ETH_RX_Q_NUM -+#define MV_ETH_TX_Q_NUM CONFIG_MV_ETH_TX_Q_NUM -+ -+/* interrupt coalescing setting */ -+#define ETH_TX_COAL 200 -+#define ETH_RX_COAL 200 -+ -+/* Checksum offloading */ -+#define TX_CSUM_OFFLOAD -+#define RX_CSUM_OFFLOAD -+ -+#endif /* CONFIG_MV_INCLUDE_GIG_ETH */ -+ -+/****************************************************************/ -+/*************** Telephony configuration ************************/ -+/****************************************************************/ -+#if defined(CONFIG_MV_TDM_LINEAR_MODE) -+ #define MV_TDM_LINEAR_MODE -+#elif defined(CONFIG_MV_TDM_ULAW_MODE) -+ #define MV_TDM_ULAW_MODE -+#endif -+ -+#if defined(CONFIG_MV_TDM_5CHANNELS) -+ #define MV_TDM_5CHANNELS -+#endif -+ -+#if defined(CONFIG_MV_TDM_USE_EXTERNAL_PCLK_SOURCE) -+ #define MV_TDM_USE_EXTERNAL_PCLK_SOURCE -+#endif -+ -+/* We use the following registers to store DRAM interface pre configuration */ -+/* auto-detection results */ -+/* IMPORTANT: We are using mask register for that purpose. Before writing */ -+/* to units mask register, make sure main maks register is set to disable */ -+/* all interrupts. */ -+#define DRAM_BUF_REG0 0x30810 /* sdram bank 0 size */ -+#define DRAM_BUF_REG1 0x30820 /* sdram config */ -+#define DRAM_BUF_REG2 0x30830 /* sdram mode */ -+#define DRAM_BUF_REG3 0x308c4 /* dunit control low */ -+#define DRAM_BUF_REG4 0x60a90 /* sdram address control */ -+#define DRAM_BUF_REG5 0x60a94 /* sdram timing control low */ -+#define DRAM_BUF_REG6 0x60a98 /* sdram timing control high */ -+#define DRAM_BUF_REG7 0x60a9c /* sdram ODT control low */ -+#define DRAM_BUF_REG8 0x60b90 /* sdram ODT control high */ -+#define DRAM_BUF_REG9 0x60b94 /* sdram Dunit ODT control */ -+#define DRAM_BUF_REG10 0x60b98 /* sdram Extended Mode */ -+#define DRAM_BUF_REG11 0x60b9c /* sdram Ddr2 Time Low Reg */ -+#define DRAM_BUF_REG12 0x60a00 /* sdram Ddr2 Time High Reg */ -+#define DRAM_BUF_REG13 0x60a04 /* dunit Ctrl High */ -+#define DRAM_BUF_REG14 0x60b00 /* sdram second DIMM exist */ -+ -+/* Following the pre-configuration registers default values restored after */ -+/* auto-detection is done */ -+#define DRAM_BUF_REG_DV 0 -+ -+/* System Mapping */ -+#define SDRAM_CS0_BASE 0x00000000 -+#define SDRAM_CS0_SIZE _256M -+ -+#define SDRAM_CS1_BASE 0x10000000 -+#define SDRAM_CS1_SIZE _256M -+ -+#define SDRAM_CS2_BASE 0x20000000 -+#define SDRAM_CS2_SIZE _256M -+ -+#define SDRAM_CS3_BASE 0x30000000 -+#define SDRAM_CS3_SIZE _256M -+ -+/* PEX */ -+#define PEX0_MEM_BASE 0xe8000000 -+#define PEX0_MEM_SIZE _128M -+ -+#define PEX0_IO_BASE 0xf2000000 -+#define PEX0_IO_SIZE _1M -+ -+/* Device Chip Selects */ -+#define NFLASH_CS_BASE 0xfa000000 -+#define NFLASH_CS_SIZE _2M -+ -+#define SPI_CS_BASE 0xf4000000 -+#define SPI_CS_SIZE _16M -+ -+#define CRYPT_ENG_BASE 0xf0000000 -+#define CRYPT_ENG_SIZE _2M -+ -+#define BOOTDEV_CS_BASE 0xff800000 -+#define BOOTDEV_CS_SIZE _8M -+ -+/* CS2 - BOOTROM */ -+#define DEVICE_CS2_BASE 0xff900000 -+#define DEVICE_CS2_SIZE _1M -+ -+/* PEX Work arround */ -+/* the target we will use for the workarround */ -+#define PEX_CONFIG_RW_WA_TARGET PEX0_MEM -+/*a flag that indicates if we are going to use the -+size and base of the target we using for the workarround -+window */ -+#define PEX_CONFIG_RW_WA_USE_ORIGINAL_WIN_VALUES 1 -+/* if the above flag is 0 then the following values -+will be used for the workarround window base and size, -+otherwise the following defines will be ignored */ -+#define PEX_CONFIG_RW_WA_BASE 0xF3000000 -+#define PEX_CONFIG_RW_WA_SIZE _16M -+ -+/* Internal registers: size is defined in Controllerenvironment */ -+#define INTER_REGS_BASE 0xFEE00000 -+ -+/* DRAM detection stuff */ -+#define MV_DRAM_AUTO_SIZE -+ -+/* Board clock detection */ -+#define TCLK_AUTO_DETECT /* Use Tclk auto detection */ -+#define SYSCLK_AUTO_DETECT /* Use SysClk auto detection */ -+#define PCLCK_AUTO_DETECT /* Use PClk auto detection */ -+#define L2CLK_AUTO_DETECT /* Use L2Clk auto detection */ -+ -+/* PEX-PCI\PCI-PCI Bridge*/ -+#define PCI0_IF_PTP 0 /* Bridge exist on pciIf0*/ -+ -+ -+ -+#endif /* __INCmvSysHwConfigh */ -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.c ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.c 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,376 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "mvCntmr.h" -+#include "cpu/mvCpu.h" -+ -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+extern unsigned int whoAmI(void); -+ -+/******************************************************************************* -+* mvCntmrLoad - -+* -+* DESCRIPTION: -+* Load an init Value to a given counter/timer -+* -+* INPUT: -+* countNum - counter number -+* value - value to be loaded -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess -+*******************************************************************************/ -+MV_STATUS mvCntmrLoad(MV_U32 countNum, MV_U32 value) -+{ -+ if (countNum >= MV_CNTMR_MAX_COUNTER ) -+ { -+ -+ mvOsPrintf(("mvCntmrLoad: Err. Illigal counter number \n")); -+ return MV_BAD_PARAM;; -+ -+ } -+ -+ MV_REG_WRITE(CNTMR_RELOAD_REG(countNum),value); -+ MV_REG_WRITE(CNTMR_VAL_REG(countNum),value); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCntmrRead - -+* -+* DESCRIPTION: -+* Returns the value of the given Counter/Timer -+* -+* INPUT: -+* countNum - counter number -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_U32 counter value -+*******************************************************************************/ -+MV_U32 mvCntmrRead(MV_U32 countNum) -+{ -+ return MV_REG_READ(CNTMR_VAL_REG(countNum)); -+} -+ -+/******************************************************************************* -+* mvCntmrWrite - -+* -+* DESCRIPTION: -+* Returns the value of the given Counter/Timer -+* -+* INPUT: -+* countNum - counter number -+* countVal - value to write -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None -+*******************************************************************************/ -+void mvCntmrWrite(MV_U32 countNum,MV_U32 countVal) -+{ -+ MV_REG_WRITE(CNTMR_VAL_REG(countNum),countVal); -+} -+ -+/******************************************************************************* -+* mvCntmrCtrlSet - -+* -+* DESCRIPTION: -+* Set the Control to a given counter/timer -+* -+* INPUT: -+* countNum - counter number -+* pCtrl - pointer to MV_CNTMR_CTRL structure -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess -+*******************************************************************************/ -+MV_STATUS mvCntmrCtrlSet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl) -+{ -+ MV_U32 cntmrCtrl; -+ -+ if (countNum >= MV_CNTMR_MAX_COUNTER ) -+ { -+ -+ DB(mvOsPrintf(("mvCntmrCtrlSet: Err. Illigal counter number \n"))); -+ return MV_BAD_PARAM;; -+ -+ } -+ -+ /* read control register */ -+ cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG); -+ -+ -+ if (pCtrl->enable) /* enable counter\timer */ -+ { -+ cntmrCtrl |= CTCR_ARM_TIMER_EN(countNum); -+ } -+ else /* disable counter\timer */ -+ { -+ cntmrCtrl &= ~CTCR_ARM_TIMER_EN(countNum); -+ } -+ -+ if ( pCtrl->autoEnable ) /* Auto mode */ -+ { -+ cntmrCtrl |= CTCR_ARM_TIMER_AUTO_EN(countNum); -+ -+ } -+ else /* no auto mode */ -+ { -+ cntmrCtrl &= ~CTCR_ARM_TIMER_AUTO_EN(countNum); -+ } -+ -+ MV_REG_WRITE(CNTMR_CTRL_REG,cntmrCtrl); -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvCntmrCtrlGet - -+* -+* DESCRIPTION: -+* Get the Control value of a given counter/timer -+* -+* INPUT: -+* countNum - counter number -+* pCtrl - pointer to MV_CNTMR_CTRL structure -+* -+* OUTPUT: -+* Counter\Timer control value -+* -+* RETURN: -+* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess -+*******************************************************************************/ -+MV_STATUS mvCntmrCtrlGet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl) -+{ -+ MV_U32 cntmrCtrl; -+ -+ if (countNum >= MV_CNTMR_MAX_COUNTER ) -+ { -+ DB(mvOsPrintf(("mvCntmrCtrlGet: Err. Illigal counter number \n"))); -+ return MV_BAD_PARAM;; -+ } -+ -+ /* read control register */ -+ cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG); -+ -+ /* enable counter\timer */ -+ if (cntmrCtrl & CTCR_ARM_TIMER_EN(countNum)) -+ { -+ pCtrl->enable = MV_TRUE; -+ } -+ else -+ { -+ pCtrl->enable = MV_FALSE; -+ } -+ -+ /* counter mode */ -+ if (cntmrCtrl & CTCR_ARM_TIMER_AUTO_EN(countNum)) -+ { -+ pCtrl->autoEnable = MV_TRUE; -+ } -+ else -+ { -+ pCtrl->autoEnable = MV_FALSE; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCntmrEnable - -+* -+* DESCRIPTION: -+* Set the Enable-Bit to logic '1' ==> starting the counter -+* -+* INPUT: -+* countNum - counter number -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess -+*******************************************************************************/ -+MV_STATUS mvCntmrEnable(MV_U32 countNum) -+{ -+ MV_U32 cntmrCtrl; -+ -+ if (countNum >= MV_CNTMR_MAX_COUNTER ) -+ { -+ -+ DB(mvOsPrintf(("mvCntmrEnable: Err. Illigal counter number \n"))); -+ return MV_BAD_PARAM;; -+ -+ } -+ -+ /* read control register */ -+ cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG); -+ -+ /* enable counter\timer */ -+ cntmrCtrl |= CTCR_ARM_TIMER_EN(countNum); -+ -+ -+ MV_REG_WRITE(CNTMR_CTRL_REG,cntmrCtrl); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCntmrDisable - -+* -+* DESCRIPTION: -+* Stop the counter/timer running, and returns its Value -+* -+* INPUT: -+* countNum - counter number -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_U32 counter\timer value -+*******************************************************************************/ -+MV_STATUS mvCntmrDisable(MV_U32 countNum) -+{ -+ MV_U32 cntmrCtrl; -+ -+ if (countNum >= MV_CNTMR_MAX_COUNTER ) -+ { -+ -+ DB(mvOsPrintf(("mvCntmrDisable: Err. Illigal counter number \n"))); -+ return MV_BAD_PARAM;; -+ -+ } -+ -+ /* read control register */ -+ cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG); -+ -+ /* disable counter\timer */ -+ cntmrCtrl &= ~CTCR_ARM_TIMER_EN(countNum); -+ -+ MV_REG_WRITE(CNTMR_CTRL_REG,cntmrCtrl); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCntmrStart - -+* -+* DESCRIPTION: -+* Combined all the sub-operations above to one function: Load,setMode,Enable -+* -+* INPUT: -+* countNum - counter number -+* value - value of the counter\timer to be set -+* pCtrl - pointer to MV_CNTMR_CTRL structure -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess -+*******************************************************************************/ -+MV_STATUS mvCntmrStart(MV_U32 countNum, MV_U32 value, -+ MV_CNTMR_CTRL *pCtrl) -+{ -+ -+ if (countNum >= MV_CNTMR_MAX_COUNTER ) -+ { -+ -+ mvOsPrintf(("mvCntmrDisable: Err. Illigal counter number \n")); -+ return MV_BAD_PARAM;; -+ -+ } -+ -+ /* load value onto counter\timer */ -+ mvCntmrLoad(countNum,value); -+ -+ /* set the counter to load in the first time */ -+ mvCntmrWrite(countNum,value); -+ -+ /* set control for timer \ cunter and enable */ -+ mvCntmrCtrlSet(countNum,pCtrl); -+ -+ return MV_OK; -+} -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,121 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvTmrWtdgh -+#define __INCmvTmrWtdgh -+ -+/* includes */ -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "cntmr/mvCntmrRegs.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+ -+ -+/* This enumerator describe counters\watchdog numbers */ -+typedef enum _mvCntmrID -+{ -+ TIMER0 = 0, -+ TIMER1, -+ WATCHDOG, -+ TIMER2, -+ TIMER3, -+}MV_CNTMR_ID; -+ -+ -+/* Counter / Timer control structure */ -+typedef struct _mvCntmrCtrl -+{ -+ MV_BOOL enable; /* enable */ -+ MV_BOOL autoEnable; /* counter/Timer */ -+}MV_CNTMR_CTRL; -+ -+ -+/* Functions */ -+ -+/* Load an init Value to a given counter/timer */ -+MV_STATUS mvCntmrLoad(MV_U32 countNum, MV_U32 value); -+ -+/* Returns the value of the given Counter/Timer */ -+MV_U32 mvCntmrRead(MV_U32 countNum); -+ -+/* Write a value of the given Counter/Timer */ -+void mvCntmrWrite(MV_U32 countNum,MV_U32 countVal); -+ -+/* Set the Control to a given counter/timer */ -+MV_STATUS mvCntmrCtrlSet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl); -+ -+/* Get the value of a given counter/timer */ -+MV_STATUS mvCntmrCtrlGet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl); -+ -+/* Set the Enable-Bit to logic '1' ==> starting the counter. */ -+MV_STATUS mvCntmrEnable(MV_U32 countNum); -+ -+/* Stop the counter/timer running, and returns its Value. */ -+MV_STATUS mvCntmrDisable(MV_U32 countNum); -+ -+/* Combined all the sub-operations above to one function: Load,setMode,Enable */ -+MV_STATUS mvCntmrStart(MV_U32 countNum, MV_U32 value, -+ MV_CNTMR_CTRL *pCtrl); -+ -+#endif /* __INCmvTmrWtdgh */ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmrRegs.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmrRegs.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmrRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmrRegs.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,121 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvTmrwtdgRegsh -+#define __INCmvTmrwtdgRegsh -+ -+/*******************************************/ -+/* ARM Timers Registers Map */ -+/*******************************************/ -+ -+#define CNTMR_RELOAD_REG(tmrNum) (CNTMR_BASE + 0x10 + (tmrNum)*8 + \ -+ (((tmrNum) <= 3)?0:8)) -+#define CNTMR_VAL_REG(tmrNum) (CNTMR_BASE + 0x14 + (tmrNum)*8 + \ -+ (((tmrNum) <= 3)?0:8)) -+#define CNTMR_CTRL_REG (CNTMR_BASE) -+ -+/*For MV78XX0*/ -+#define CNTMR_CAUSE_REG (CPU_AHB_MBUS_CAUSE_INT_REG(whoAmI())) -+#define CNTMR_MASK_REG (CPU_AHB_MBUS_MASK_INT_REG(whoAmI())) -+ -+/* ARM Timers Registers Map */ -+/*******************************************/ -+ -+ -+/* ARM Timers Control Register */ -+/* CPU_TIMERS_CTRL_REG (CTCR) */ -+ -+#define TIMER0_NUM 0 -+#define TIMER1_NUM 1 -+#define WATCHDOG_NUM 2 -+#define TIMER2_NUM 3 -+#define TIMER3_NUM 4 -+ -+#define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2) -+#define CTCR_ARM_TIMER_EN_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS) -+#define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr)) -+#define CTCR_ARM_TIMER_DIS(cntr) (0 << CTCR_ARM_TIMER_EN_OFFS(cntr)) -+ -+#define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1) -+#define CTCR_ARM_TIMER_AUTO_MASK(cntr) BIT1 -+#define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) -+#define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) -+ -+ -+/* ARM Timer\Watchdog Reload Register */ -+/* CNTMR_RELOAD_REG (TRR) */ -+ -+#define TRG_ARM_TIMER_REL_OFFS 0 -+#define TRG_ARM_TIMER_REL_MASK 0xffffffff -+ -+/* ARM Timer\Watchdog Register */ -+/* CNTMR_VAL_REG (TVRG) */ -+ -+#define TVR_ARM_TIMER_OFFS 0 -+#define TVR_ARM_TIMER_MASK 0xffffffff -+#define TVR_ARM_TIMER_MAX 0xffffffff -+ -+ -+ -+#endif /* __INCmvTmrwtdgRegsh */ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,207 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include "mvOs.h" -+#include "mvCpuCntrs.h" -+ -+ -+const static MV_CPU_CNTRS_OPS mvCpuCntrsOpsTbl[MV_CPU_CNTRS_NUM][MV_CPU_CNTRS_OPS_NUM] = -+{ -+ /*0*/ -+ { -+ MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_DCACHE_READ_HIT, MV_CPU_CNTRS_DCACHE_READ_MISS, -+ MV_CPU_CNTRS_DCACHE_WRITE_HIT, MV_CPU_CNTRS_DCACHE_WRITE_MISS, MV_CPU_CNTRS_INSTRUCTIONS, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, -+ MV_CPU_CNTRS_MMU_READ_LATENCY, MV_CPU_CNTRS_ICACHE_READ_LATENCY, MV_CPU_CNTRS_WB_WRITE_LATENCY, -+ MV_CPU_CNTRS_LDM_STM_HOLD, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, -+ MV_CPU_CNTRS_DATA_WRITE_ACCESS, MV_CPU_CNTRS_DATA_READ_ACCESS, MV_CPU_CNTRS_INVALID, -+ MV_CPU_CNTRS_BRANCH_PREDICT_COUNT, -+ }, -+ /*1*/ -+ { -+ MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_ICACHE_READ_MISS, MV_CPU_CNTRS_DCACHE_READ_MISS, -+ MV_CPU_CNTRS_DCACHE_WRITE_MISS, MV_CPU_CNTRS_ITLB_MISS, MV_CPU_CNTRS_SINGLE_ISSUE, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BRANCH_RETIRED, MV_CPU_CNTRS_INVALID, -+ MV_CPU_CNTRS_MMU_READ_BEAT, MV_CPU_CNTRS_ICACHE_READ_LATENCY, MV_CPU_CNTRS_WB_WRITE_BEAT, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_IS_HOLD, MV_CPU_CNTRS_DATA_READ_ACCESS, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, -+ MV_CPU_CNTRS_INVALID, -+ }, -+ /*2*/ -+ { -+ MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DCACHE_ACCESS, -+ MV_CPU_CNTRS_DTLB_MISS, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BRANCH_PREDICT_MISS, MV_CPU_CNTRS_WB_WRITE_BEAT, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DCACHE_READ_LATENCY, MV_CPU_CNTRS_DCACHE_WRITE_LATENCY, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BIU_SIMULT_ACCESS, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, -+ MV_CPU_CNTRS_INVALID, -+ }, -+ /*3*/ -+ { -+ MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_DCACHE_READ_MISS, MV_CPU_CNTRS_DCACHE_WRITE_MISS, -+ MV_CPU_CNTRS_TLB_MISS, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BRANCH_TAKEN, MV_CPU_CNTRS_WB_FULL_CYCLES, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DCACHE_READ_BEAT, MV_CPU_CNTRS_DCACHE_WRITE_BEAT, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BIU_ANY_ACCESS, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DATA_WRITE_ACCESS, -+ MV_CPU_CNTRS_INVALID, -+ } -+}; -+ -+MV_CPU_CNTRS_ENTRY mvCpuCntrsTbl[MV_CPU_CNTRS_NUM]; -+ -+MV_CPU_CNTRS_EVENT* mvCpuCntrsEventTbl[128]; -+ -+void mvCpuCntrsReset(void) -+{ -+ MV_U32 reg = 0; -+ -+ MV_ASM ("mcr p15, 0, %0, c15, c13, 0" : : "r" (reg)); -+ MV_ASM ("mcr p15, 0, %0, c15, c13, 1" : : "r" (reg)); -+ MV_ASM ("mcr p15, 0, %0, c15, c13, 2" : : "r" (reg)); -+ MV_ASM ("mcr p15, 0, %0, c15, c13, 3" : : "r" (reg)); -+ MV_ASM ("mcr p15, 0, %0, c15, c13, 4" : : "r" (reg)); -+ MV_ASM ("mcr p15, 0, %0, c15, c13, 5" : : "r" (reg)); -+ MV_ASM ("mcr p15, 0, %0, c15, c13, 6" : : "r" (reg)); -+ MV_ASM ("mcr p15, 0, %0, c15, c13, 7" : : "r" (reg)); -+} -+ -+void program_counter(int counter, int op) -+{ -+ MV_U32 reg = (1 << op) | 0x1; /*enable*/ -+ -+ switch(counter) -+ { -+ case 0: -+ __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 0" : : "r" (reg)); -+ return; -+ -+ case 1: -+ __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 1" : : "r" (reg)); -+ return; -+ -+ case 2: -+ __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 2" : : "r" (reg)); -+ return; -+ -+ case 3: -+ __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 3" : : "r" (reg)); -+ return; -+ -+ default: -+ mvOsPrintf("error in program_counter: bad counter number (%d)\n", counter); -+ } -+ return; -+} -+ -+void mvCpuCntrsEventClear(MV_CPU_CNTRS_EVENT* pEvent) -+{ -+ int i; -+ -+ for(i=0; icounters_sum[i] = 0; -+ } -+ pEvent->num_of_measurements = 0; -+} -+ -+ -+MV_CPU_CNTRS_EVENT* mvCpuCntrsEventCreate(char* name, MV_U32 print_threshold) -+{ -+ int i; -+ MV_CPU_CNTRS_EVENT* event = mvOsMalloc(sizeof(MV_CPU_CNTRS_EVENT)); -+ -+ if(event) -+ { -+ strncpy(event->name, name, sizeof(event->name)); -+ event->num_of_measurements = 0; -+ event->avg_sample_count = print_threshold; -+ for(i=0; icounters_before[i] = 0; -+ event->counters_after[i] = 0; -+ event->counters_sum[i] = 0; -+ } -+ } -+ return event; -+} -+ -+void mvCpuCntrsEventDelete(MV_CPU_CNTRS_EVENT* event) -+{ -+ if(event != NULL) -+ mvOsFree(event); -+} -+ -+ -+MV_STATUS mvCpuCntrsProgram(int counter, MV_CPU_CNTRS_OPS op, -+ char* name, MV_U32 overhead) -+{ -+ int i; -+ -+ /* Find required operations */ -+ for(i=0; inum_of_measurements < pEvent->avg_sample_count) -+ return; -+ -+ mvOsPrintf("%16s: ", pEvent->name); -+ for(i=0; icounters_sum[i], -+ pEvent->num_of_measurements, NULL); -+ if(counters_avg >= mvCpuCntrsTbl[i].overhead) -+ counters_avg -= mvCpuCntrsTbl[i].overhead; -+ else -+ counters_avg = 0; -+ -+ mvOsPrintf("%s=%5llu, ", mvCpuCntrsTbl[i].name, counters_avg); -+ } -+ mvOsPrintf("\n"); -+ mvCpuCntrsEventClear(pEvent); -+ mvCpuCntrsReset(); -+} -+ -+void mvCpuCntrsStatus(void) -+{ -+ int i; -+ -+ for(i=0; icounters_before[i] = mvCpuCntrsRead(i); -+#else -+ pEvent->counters_before[1] = mvCpuCntrsRead(1); -+ pEvent->counters_before[3] = mvCpuCntrsRead(3); -+ pEvent->counters_before[0] = mvCpuCntrsRead(0); -+ pEvent->counters_before[2] = mvCpuCntrsRead(2); -+#endif -+} -+ -+static INLINE void mvCpuCntrsReadAfter(MV_CPU_CNTRS_EVENT* pEvent) -+{ -+ int i; -+ -+#if 0 -+ /* order is important - we want to measure the cycle count first here! */ -+ for(i=0; icounters_after[i] = mvCpuCntrsRead(i); -+#else -+ pEvent->counters_after[2] = mvCpuCntrsRead(2); -+ pEvent->counters_after[0] = mvCpuCntrsRead(0); -+ pEvent->counters_after[3] = mvCpuCntrsRead(3); -+ pEvent->counters_after[1] = mvCpuCntrsRead(1); -+#endif -+ -+ for(i=0; icounters_sum[i] += (pEvent->counters_after[i] - pEvent->counters_before[i]); -+ } -+ pEvent->num_of_measurements++; -+} -+ -+ -+#ifdef CONFIG_MV_CPU_PERF_CNTRS -+ -+#define MV_CPU_CNTRS_READ(counter) mvCpuCntrsRead(counter) -+ -+#define MV_CPU_CNTRS_START(event) mvCpuCntrsReadBefore(event) -+ -+#define MV_CPU_CNTRS_STOP(event) mvCpuCntrsReadAfter(event) -+ -+#define MV_CPU_CNTRS_SHOW(event) mvCpuCntrsShow(event) -+ -+#else -+ -+#define MV_CPU_CNTRS_READ(counter) -+#define MV_CPU_CNTRS_START(event) -+#define MV_CPU_CNTRS_STOP(event) -+#define MV_CPU_CNTRS_SHOW(event) -+ -+#endif /* CONFIG_MV_CPU_PERF_CNTRS */ -+ -+ -+#endif /* __mvCpuCntrs_h__ */ -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,143 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include "mvOs.h" -+#include "mvCpuL2Cntrs.h" -+ -+ -+ -+MV_CPU_L2_CNTRS_ENTRY mvCpuL2CntrsTbl[MV_CPU_L2_CNTRS_NUM]; -+ -+MV_CPU_L2_CNTRS_EVENT* mvCpuL2CntrsEventTbl[128]; -+ -+void mvCpuL2CntrsReset(void) -+{ -+ MV_U32 reg = 0; -+ -+ MV_ASM ("mcr p15, 6, %0, c15, c13, 0" : : "r" (reg)); -+ MV_ASM ("mcr p15, 6, %0, c15, c13, 1" : : "r" (reg)); -+ MV_ASM ("mcr p15, 6, %0, c15, c13, 2" : : "r" (reg)); -+ MV_ASM ("mcr p15, 6, %0, c15, c13, 3" : : "r" (reg)); -+} -+ -+static void mvCpuL2CntrConfig(int counter, int op) -+{ -+ MV_U32 reg = (1 << op) | 0x1; /*enable*/ -+ -+ switch(counter) -+ { -+ case 0: -+ MV_ASM ("mcr p15, 6, %0, c15, c12, 0" : : "r" (reg)); -+ return; -+ -+ case 1: -+ MV_ASM ("mcr p15, 6, %0, c15, c12, 1" : : "r" (reg)); -+ return; -+ -+ default: -+ mvOsPrintf("mvCpuL2CntrConfig: bad counter number (%d)\n", counter); -+ } -+ return; -+} -+ -+void mvCpuL2CntrsEventClear(MV_CPU_L2_CNTRS_EVENT* pEvent) -+{ -+ int i; -+ -+ for(i=0; icounters_sum[i] = 0; -+ } -+ pEvent->num_of_measurements = 0; -+} -+ -+ -+MV_CPU_L2_CNTRS_EVENT* mvCpuL2CntrsEventCreate(char* name, MV_U32 print_threshold) -+{ -+ int i; -+ MV_CPU_L2_CNTRS_EVENT* event = mvOsMalloc(sizeof(MV_CPU_L2_CNTRS_EVENT)); -+ -+ if(event) -+ { -+ strncpy(event->name, name, sizeof(event->name)); -+ event->num_of_measurements = 0; -+ event->avg_sample_count = print_threshold; -+ for(i=0; icounters_before[i] = 0; -+ event->counters_after[i] = 0; -+ event->counters_sum[i] = 0; -+ } -+ } -+ return event; -+} -+ -+void mvCpuL2CntrsEventDelete(MV_CPU_L2_CNTRS_EVENT* event) -+{ -+ if(event != NULL) -+ mvOsFree(event); -+} -+ -+ -+MV_STATUS mvCpuL2CntrsProgram(int counter, MV_CPU_L2_CNTRS_OPS op, -+ char* name, MV_U32 overhead) -+{ -+ strncpy(mvCpuL2CntrsTbl[counter].name, name, sizeof(mvCpuL2CntrsTbl[counter].name)); -+ mvCpuL2CntrsTbl[counter].operation = op; -+ mvCpuL2CntrsTbl[counter].opIdx = op; -+ mvCpuL2CntrsTbl[counter].overhead = overhead; -+ mvCpuL2CntrConfig(counter, op); -+ mvOsPrintf("CPU L2 Counter %d: operation=%d, overhead=%d\n", -+ counter, op, overhead); -+ return MV_OK; -+} -+ -+void mvCpuL2CntrsShow(MV_CPU_L2_CNTRS_EVENT* pEvent) -+{ -+ int i; -+ MV_U64 counters_avg; -+ -+ if(pEvent->num_of_measurements < pEvent->avg_sample_count) -+ return; -+ -+ mvOsPrintf("%16s: ", pEvent->name); -+ for(i=0; icounters_sum[i], -+ pEvent->num_of_measurements, NULL); -+ -+ if(counters_avg >= mvCpuL2CntrsTbl[i].overhead) -+ counters_avg -= mvCpuL2CntrsTbl[i].overhead; -+ else -+ counters_avg = 0; -+ -+ mvOsPrintf("%s=%5llu, ", mvCpuL2CntrsTbl[i].name, counters_avg); -+ } -+ mvOsPrintf("\n"); -+ mvCpuL2CntrsEventClear(pEvent); -+ mvCpuL2CntrsReset(); -+} -+ -+void mvCpuL2CntrsStatus(void) -+{ -+ int i; -+ -+ for(i=0; icounters_before[i] = mvCpuL2CntrsRead(i); -+} -+ -+static INLINE void mvCpuL2CntrsReadAfter(MV_CPU_L2_CNTRS_EVENT* pEvent) -+{ -+ int i; -+ -+ for(i=0; icounters_after[i] = mvCpuL2CntrsRead(i); -+ pEvent->counters_sum[i] += (pEvent->counters_after[i] - pEvent->counters_before[i]); -+ } -+ pEvent->num_of_measurements++; -+} -+ -+ -+#ifdef CONFIG_MV_CPU_L2_PERF_CNTRS -+ -+#define MV_CPU_L2_CNTRS_READ(counter) mvCpuL2CntrsRead(counter) -+ -+#define MV_CPU_L2_CNTRS_START(event) mvCpuL2CntrsReadBefore(event) -+ -+#define MV_CPU_L2_CNTRS_STOP(event) mvCpuL2CntrsReadAfter(event) -+ -+#define MV_CPU_L2_CNTRS_SHOW(event) mvCpuL2CntrsShow(event) -+ -+#else -+ -+#define MV_CPU_L2_CNTRS_READ(counter) -+#define MV_CPU_L2_CNTRS_START(event) -+#define MV_CPU_L2_CNTRS_STOP(event) -+#define MV_CPU_L2_CNTRS_SHOW(event) -+ -+#endif /* CONFIG_MV_CPU_L2_PERF_CNTRS */ -+ -+ -+#endif /* __mvCpuL2Cntrs_h__ */ -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,1479 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "ddr1_2/mvDram.h" -+#include "boardEnv/mvBoardEnvLib.h" -+ -+#undef MV_DEBUG -+#ifdef MV_DEBUG -+#define DB(x) x -+#else -+#define DB(x) -+#endif -+ -+static MV_VOID cpyDimm2BankInfo(MV_DIMM_INFO *pDimmInfo, -+ MV_DRAM_BANK_INFO *pBankInfo); -+static MV_U32 cas2ps(MV_U8 spd_byte); -+/******************************************************************************* -+* mvDramBankGet - Get the DRAM bank paramters. -+* -+* DESCRIPTION: -+* This function retrieves DRAM bank parameters as described in -+* DRAM_BANK_INFO struct to the controller DRAM unit. In case the board -+* has its DRAM on DIMMs it will use its EEPROM to extract SPD data -+* from it. Otherwise, if the DRAM is soldered on board, the function -+* should insert its bank information into MV_DRAM_BANK_INFO struct. -+* -+* INPUT: -+* bankNum - Board DRAM bank number. -+* -+* OUTPUT: -+* pBankInfo - DRAM bank information struct. -+* -+* RETURN: -+* MV_FAIL - Bank parameters could not be read. -+* -+*******************************************************************************/ -+MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo) -+{ -+ MV_DIMM_INFO dimmInfo; -+ -+ DB(mvOsPrintf("Dram: mvDramBankInfoGet bank %d\n", bankNum)); -+ /* zero pBankInfo structure */ -+ memset(pBankInfo, 0, sizeof(*pBankInfo)); -+ -+ if((NULL == pBankInfo) || (bankNum >= MV_DRAM_MAX_CS )) -+ { -+ DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); -+ return MV_BAD_PARAM; -+ } -+ if( MV_OK != dimmSpdGet((MV_U32)(bankNum/2), &dimmInfo)) -+ { -+ DB(mvOsPrintf("Dram: ERR dimmSpdGet failed to get dimm info \n")); -+ return MV_FAIL; -+ } -+ if((dimmInfo.numOfModuleBanks == 1) && ((bankNum % 2) == 1)) -+ { -+ DB(mvOsPrintf("Dram: ERR dimmSpdGet. Can't find DIMM bank 2 \n")); -+ return MV_FAIL; -+ } -+ -+ /* convert Dimm info to Bank info */ -+ cpyDimm2BankInfo(&dimmInfo, pBankInfo); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* cpyDimm2BankInfo - Convert a Dimm info struct into a bank info struct. -+* -+* DESCRIPTION: -+* Convert a Dimm info struct into a bank info struct. -+* -+* INPUT: -+* pDimmInfo - DIMM information structure. -+* -+* OUTPUT: -+* pBankInfo - DRAM bank information struct. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+static MV_VOID cpyDimm2BankInfo(MV_DIMM_INFO *pDimmInfo, -+ MV_DRAM_BANK_INFO *pBankInfo) -+{ -+ pBankInfo->memoryType = pDimmInfo->memoryType; -+ -+ /* DIMM dimensions */ -+ pBankInfo->numOfRowAddr = pDimmInfo->numOfRowAddr; -+ pBankInfo->numOfColAddr = pDimmInfo->numOfColAddr; -+ pBankInfo->dataWidth = pDimmInfo->dataWidth; -+ pBankInfo->errorCheckType = pDimmInfo->errorCheckType; -+ pBankInfo->sdramWidth = pDimmInfo->sdramWidth; -+ pBankInfo->errorCheckDataWidth = pDimmInfo->errorCheckDataWidth; -+ pBankInfo->numOfBanksOnEachDevice = pDimmInfo->numOfBanksOnEachDevice; -+ pBankInfo->suportedCasLatencies = pDimmInfo->suportedCasLatencies; -+ pBankInfo->refreshInterval = pDimmInfo->refreshInterval; -+ -+ /* DIMM timing parameters */ -+ pBankInfo->minCycleTimeAtMaxCasLatPs = pDimmInfo->minCycleTimeAtMaxCasLatPs; -+ pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps = -+ pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps; -+ pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps = -+ pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps; -+ -+ pBankInfo->minRowPrechargeTime = pDimmInfo->minRowPrechargeTime; -+ pBankInfo->minRowActiveToRowActive = pDimmInfo->minRowActiveToRowActive; -+ pBankInfo->minRasToCasDelay = pDimmInfo->minRasToCasDelay; -+ pBankInfo->minRasPulseWidth = pDimmInfo->minRasPulseWidth; -+ pBankInfo->minWriteRecoveryTime = pDimmInfo->minWriteRecoveryTime; -+ pBankInfo->minWriteToReadCmdDelay = pDimmInfo->minWriteToReadCmdDelay; -+ pBankInfo->minReadToPrechCmdDelay = pDimmInfo->minReadToPrechCmdDelay; -+ pBankInfo->minRefreshToActiveCmd = pDimmInfo->minRefreshToActiveCmd; -+ -+ /* Parameters calculated from the extracted DIMM information */ -+ pBankInfo->size = pDimmInfo->size/pDimmInfo->numOfModuleBanks; -+ pBankInfo->deviceDensity = pDimmInfo->deviceDensity; -+ pBankInfo->numberOfDevices = pDimmInfo->numberOfDevices / -+ pDimmInfo->numOfModuleBanks; -+ -+ /* DIMM attributes (MV_TRUE for yes) */ -+ -+ if ((pDimmInfo->memoryType == MEM_TYPE_SDRAM) || -+ (pDimmInfo->memoryType == MEM_TYPE_DDR1) ) -+ { -+ if (pDimmInfo->dimmAttributes & BIT1) -+ pBankInfo->registeredAddrAndControlInputs = MV_TRUE; -+ else -+ pBankInfo->registeredAddrAndControlInputs = MV_FALSE; -+ } -+ else /* pDimmInfo->memoryType == MEM_TYPE_DDR2 */ -+ { -+ if (pDimmInfo->dimmTypeInfo & (BIT0 | BIT4)) -+ pBankInfo->registeredAddrAndControlInputs = MV_TRUE; -+ else -+ pBankInfo->registeredAddrAndControlInputs = MV_FALSE; -+ } -+ -+ return; -+} -+ -+/******************************************************************************* -+* dimmSpdCpy - Cpy SPD parameters from dimm 0 to dimm 1. -+* -+* DESCRIPTION: -+* Read the DIMM SPD parameters from dimm 0 into dimm 1 SPD. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+MV_STATUS dimmSpdCpy(MV_VOID) -+{ -+ MV_U32 i; -+ MV_U32 spdChecksum; -+ -+ MV_TWSI_SLAVE twsiSlave; -+ MV_U8 data[SPD_SIZE]; -+ -+ /* zero dimmInfo structure */ -+ memset(data, 0, SPD_SIZE); -+ -+ /* read the dimm eeprom */ -+ DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); -+ twsiSlave.slaveAddr.address = MV_BOARD_DIMM0_I2C_ADDR; -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ twsiSlave.offset = 0; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, -+ &twsiSlave, data, SPD_SIZE) ) -+ { -+ DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 0\n")); -+ return MV_FAIL; -+ } -+ DB(puts("DRAM: Reading dimm info succeded.\n")); -+ -+ /* calculate SPD checksum */ -+ spdChecksum = 0; -+ -+ for(i = 0 ; i <= 62 ; i++) -+ { -+ spdChecksum += data[i]; -+ } -+ -+ if ((spdChecksum & 0xff) != data[63]) -+ { -+ DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", -+ (MV_U32)(spdChecksum & 0xff), data[63])); -+ } -+ else -+ { -+ DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); -+ } -+ -+ /* copy the SPD content 1:1 into the DIMM 1 SPD */ -+ twsiSlave.slaveAddr.address = MV_BOARD_DIMM1_I2C_ADDR; -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ twsiSlave.offset = 0; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ for(i = 0 ; i < SPD_SIZE ; i++) -+ { -+ twsiSlave.offset = i; -+ if( MV_OK != mvTwsiWrite (MV_BOARD_DIMM_I2C_CHANNEL, -+ &twsiSlave, &data[i], 1) ) -+ { -+ mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 1 byte %d \n",i); -+ return MV_FAIL; -+ } -+ mvOsDelay(5); -+ } -+ -+ DB(puts("DRAM: Reading dimm info succeded.\n")); -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* dimmSpdGet - Get the SPD parameters. -+* -+* DESCRIPTION: -+* Read the DIMM SPD parameters into given struct parameter. -+* -+* INPUT: -+* dimmNum - DIMM number. See MV_BOARD_DIMM_NUM enumerator. -+* -+* OUTPUT: -+* pDimmInfo - DIMM information structure. -+* -+* RETURN: -+* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo) -+{ -+ MV_U32 i; -+ MV_U32 density = 1; -+ MV_U32 spdChecksum; -+ -+ MV_TWSI_SLAVE twsiSlave; -+ MV_U8 data[SPD_SIZE]; -+ -+ if((NULL == pDimmInfo)|| (dimmNum >= MAX_DIMM_NUM)) -+ { -+ DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); -+ return MV_BAD_PARAM; -+ } -+ -+ /* zero dimmInfo structure */ -+ memset(data, 0, SPD_SIZE); -+ -+ /* read the dimm eeprom */ -+ DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); -+ twsiSlave.slaveAddr.address = (dimmNum == 0) ? -+ MV_BOARD_DIMM0_I2C_ADDR : MV_BOARD_DIMM1_I2C_ADDR; -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ twsiSlave.offset = 0; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, -+ &twsiSlave, data, SPD_SIZE) ) -+ { -+ DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum %d \n", dimmNum)); -+ return MV_FAIL; -+ } -+ DB(puts("DRAM: Reading dimm info succeded.\n")); -+ -+ /* calculate SPD checksum */ -+ spdChecksum = 0; -+ -+ for(i = 0 ; i <= 62 ; i++) -+ { -+ spdChecksum += data[i]; -+ } -+ -+ if ((spdChecksum & 0xff) != data[63]) -+ { -+ DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", -+ (MV_U32)(spdChecksum & 0xff), data[63])); -+ } -+ else -+ { -+ DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); -+ } -+ -+ /* copy the SPD content 1:1 into the dimmInfo structure*/ -+ for(i = 0 ; i < SPD_SIZE ; i++) -+ { -+ pDimmInfo->spdRawData[i] = data[i]; -+ DB(mvOsPrintf("SPD-EEPROM Byte %3d = %3x (%3d)\n",i, data[i], data[i])); -+ } -+ -+ DB(mvOsPrintf("DRAM SPD Information:\n")); -+ -+ /* Memory type (DDR / SDRAM) */ -+ switch (data[DIMM_MEM_TYPE]) -+ { -+ case (DIMM_MEM_TYPE_SDRAM): -+ pDimmInfo->memoryType = MEM_TYPE_SDRAM; -+ DB(mvOsPrintf("DRAM Memeory type SDRAM\n")); -+ break; -+ case (DIMM_MEM_TYPE_DDR1): -+ pDimmInfo->memoryType = MEM_TYPE_DDR1; -+ DB(mvOsPrintf("DRAM Memeory type DDR1\n")); -+ break; -+ case (DIMM_MEM_TYPE_DDR2): -+ pDimmInfo->memoryType = MEM_TYPE_DDR2; -+ DB(mvOsPrintf("DRAM Memeory type DDR2\n")); -+ break; -+ default: -+ mvOsPrintf("ERROR: Undefined memory type!\n"); -+ return MV_ERROR; -+ } -+ -+ -+ /* Number Of Row Addresses */ -+ pDimmInfo->numOfRowAddr = data[DIMM_ROW_NUM]; -+ DB(mvOsPrintf("DRAM numOfRowAddr[3] %d\n",pDimmInfo->numOfRowAddr)); -+ -+ /* Number Of Column Addresses */ -+ pDimmInfo->numOfColAddr = data[DIMM_COL_NUM]; -+ DB(mvOsPrintf("DRAM numOfColAddr[4] %d\n",pDimmInfo->numOfColAddr)); -+ -+ /* Number Of Module Banks */ -+ pDimmInfo->numOfModuleBanks = data[DIMM_MODULE_BANK_NUM]; -+ DB(mvOsPrintf("DRAM numOfModuleBanks[5] 0x%x\n", -+ pDimmInfo->numOfModuleBanks)); -+ -+ /* Number of module banks encoded differently for DDR2 */ -+ if (pDimmInfo->memoryType == MEM_TYPE_DDR2) -+ pDimmInfo->numOfModuleBanks = (pDimmInfo->numOfModuleBanks & 0x7)+1; -+ -+ /* Data Width */ -+ pDimmInfo->dataWidth = data[DIMM_DATA_WIDTH]; -+ DB(mvOsPrintf("DRAM dataWidth[6] 0x%x\n", pDimmInfo->dataWidth)); -+ -+ /* Minimum Cycle Time At Max CasLatancy */ -+ pDimmInfo->minCycleTimeAtMaxCasLatPs = cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS]); -+ -+ /* Error Check Type */ -+ pDimmInfo->errorCheckType = data[DIMM_ERR_CHECK_TYPE]; -+ DB(mvOsPrintf("DRAM errorCheckType[11] 0x%x\n", -+ pDimmInfo->errorCheckType)); -+ -+ /* Refresh Interval */ -+ pDimmInfo->refreshInterval = data[DIMM_REFRESH_INTERVAL]; -+ DB(mvOsPrintf("DRAM refreshInterval[12] 0x%x\n", -+ pDimmInfo->refreshInterval)); -+ -+ /* Sdram Width */ -+ pDimmInfo->sdramWidth = data[DIMM_SDRAM_WIDTH]; -+ DB(mvOsPrintf("DRAM sdramWidth[13] 0x%x\n",pDimmInfo->sdramWidth)); -+ -+ /* Error Check Data Width */ -+ pDimmInfo->errorCheckDataWidth = data[DIMM_ERR_CHECK_DATA_WIDTH]; -+ DB(mvOsPrintf("DRAM errorCheckDataWidth[14] 0x%x\n", -+ pDimmInfo->errorCheckDataWidth)); -+ -+ /* Burst Length Supported */ -+ /* SDRAM/DDR1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * -+ *********************************************************/ -+ /* DDR2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * -+ *********************************************************/ -+ -+ pDimmInfo->burstLengthSupported = data[DIMM_BURST_LEN_SUP]; -+ DB(mvOsPrintf("DRAM burstLengthSupported[16] 0x%x\n", -+ pDimmInfo->burstLengthSupported)); -+ -+ /* Number Of Banks On Each Device */ -+ pDimmInfo->numOfBanksOnEachDevice = data[DIMM_DEV_BANK_NUM]; -+ DB(mvOsPrintf("DRAM numOfBanksOnEachDevice[17] 0x%x\n", -+ pDimmInfo->numOfBanksOnEachDevice)); -+ -+ /* Suported Cas Latencies */ -+ -+ /* SDRAM: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * -+ ********************************************************/ -+ -+ /* DDR 1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * -+ *********************************************************/ -+ -+ /* DDR 2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * -+ *********************************************************/ -+ -+ pDimmInfo->suportedCasLatencies = data[DIMM_SUP_CAL]; -+ DB(mvOsPrintf("DRAM suportedCasLatencies[18] 0x%x\n", -+ pDimmInfo->suportedCasLatencies)); -+ -+ /* For DDR2 only, get the DIMM type information */ -+ if (pDimmInfo->memoryType == MEM_TYPE_DDR2) -+ { -+ pDimmInfo->dimmTypeInfo = data[DIMM_DDR2_TYPE_INFORMATION]; -+ DB(mvOsPrintf("DRAM dimmTypeInfo[20] (DDR2) 0x%x\n", -+ pDimmInfo->dimmTypeInfo)); -+ } -+ -+ /* SDRAM Modules Attributes */ -+ pDimmInfo->dimmAttributes = data[DIMM_BUF_ADDR_CONT_IN]; -+ DB(mvOsPrintf("DRAM dimmAttributes[21] 0x%x\n", -+ pDimmInfo->dimmAttributes)); -+ -+ /* Minimum Cycle Time At Max CasLatancy Minus 1*/ -+ pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps = -+ cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS1]); -+ -+ /* Minimum Cycle Time At Max CasLatancy Minus 2*/ -+ pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps = -+ cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS2]); -+ -+ pDimmInfo->minRowPrechargeTime = data[DIMM_MIN_ROW_PRECHARGE_TIME]; -+ DB(mvOsPrintf("DRAM minRowPrechargeTime[27] 0x%x\n", -+ pDimmInfo->minRowPrechargeTime)); -+ pDimmInfo->minRowActiveToRowActive = data[DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE]; -+ DB(mvOsPrintf("DRAM minRowActiveToRowActive[28] 0x%x\n", -+ pDimmInfo->minRowActiveToRowActive)); -+ pDimmInfo->minRasToCasDelay = data[DIMM_MIN_RAS_TO_CAS_DELAY]; -+ DB(mvOsPrintf("DRAM minRasToCasDelay[29] 0x%x\n", -+ pDimmInfo->minRasToCasDelay)); -+ pDimmInfo->minRasPulseWidth = data[DIMM_MIN_RAS_PULSE_WIDTH]; -+ DB(mvOsPrintf("DRAM minRasPulseWidth[30] 0x%x\n", -+ pDimmInfo->minRasPulseWidth)); -+ -+ /* DIMM Bank Density */ -+ pDimmInfo->dimmBankDensity = data[DIMM_BANK_DENSITY]; -+ DB(mvOsPrintf("DRAM dimmBankDensity[31] 0x%x\n", -+ pDimmInfo->dimmBankDensity)); -+ -+ /* Only DDR2 includes Write Recovery Time field. Other SDRAM ignore */ -+ pDimmInfo->minWriteRecoveryTime = data[DIMM_MIN_WRITE_RECOVERY_TIME]; -+ DB(mvOsPrintf("DRAM minWriteRecoveryTime[36] 0x%x\n", -+ pDimmInfo->minWriteRecoveryTime)); -+ -+ /* Only DDR2 includes Internal Write To Read Command Delay field. */ -+ pDimmInfo->minWriteToReadCmdDelay = data[DIMM_MIN_WRITE_TO_READ_CMD_DELAY]; -+ DB(mvOsPrintf("DRAM minWriteToReadCmdDelay[37] 0x%x\n", -+ pDimmInfo->minWriteToReadCmdDelay)); -+ -+ /* Only DDR2 includes Internal Read To Precharge Command Delay field. */ -+ pDimmInfo->minReadToPrechCmdDelay = data[DIMM_MIN_READ_TO_PRECH_CMD_DELAY]; -+ DB(mvOsPrintf("DRAM minReadToPrechCmdDelay[38] 0x%x\n", -+ pDimmInfo->minReadToPrechCmdDelay)); -+ -+ /* Only DDR2 includes Minimum Refresh to Activate/Refresh Command field */ -+ pDimmInfo->minRefreshToActiveCmd = data[DIMM_MIN_REFRESH_TO_ACTIVATE_CMD]; -+ DB(mvOsPrintf("DRAM minRefreshToActiveCmd[42] 0x%x\n", -+ pDimmInfo->minRefreshToActiveCmd)); -+ -+ /* calculating the sdram density. Representing device density from */ -+ /* bit 20 to allow representation of 4GB and above. */ -+ /* For example, if density is 512Mbit 0x20000000, will be represent in */ -+ /* deviceDensity by 0x20000000 >> 16 --> 0x00000200. Another example */ -+ /* is density 8GB 0x200000000 >> 16 --> 0x00002000. */ -+ density = (1 << ((pDimmInfo->numOfRowAddr + pDimmInfo->numOfColAddr) - 20)); -+ pDimmInfo->deviceDensity = density * -+ pDimmInfo->numOfBanksOnEachDevice * -+ pDimmInfo->sdramWidth; -+ DB(mvOsPrintf("DRAM deviceDensity %d\n",pDimmInfo->deviceDensity)); -+ -+ /* Number of devices includeing Error correction */ -+ pDimmInfo->numberOfDevices = (pDimmInfo->dataWidth/pDimmInfo->sdramWidth) * -+ pDimmInfo->numOfModuleBanks; -+ DB(mvOsPrintf("DRAM numberOfDevices %d\n", -+ pDimmInfo->numberOfDevices)); -+ -+ pDimmInfo->size = 0; -+ -+ /* Note that pDimmInfo->size is in MB units */ -+ if (pDimmInfo->memoryType == MEM_TYPE_SDRAM) -+ { -+ if (pDimmInfo->dimmBankDensity & BIT0) -+ pDimmInfo->size += 1024; /* Equal to 1GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT1) -+ pDimmInfo->size += 8; /* Equal to 8MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT2) -+ pDimmInfo->size += 16; /* Equal to 16MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT3) -+ pDimmInfo->size += 32; /* Equal to 32MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT4) -+ pDimmInfo->size += 64; /* Equal to 64MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT5) -+ pDimmInfo->size += 128; /* Equal to 128MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT6) -+ pDimmInfo->size += 256; /* Equal to 256MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT7) -+ pDimmInfo->size += 512; /* Equal to 512MB */ -+ } -+ else if (pDimmInfo->memoryType == MEM_TYPE_DDR1) -+ { -+ if (pDimmInfo->dimmBankDensity & BIT0) -+ pDimmInfo->size += 1024; /* Equal to 1GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT1) -+ pDimmInfo->size += 2048; /* Equal to 2GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT2) -+ pDimmInfo->size += 16; /* Equal to 16MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT3) -+ pDimmInfo->size += 32; /* Equal to 32MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT4) -+ pDimmInfo->size += 64; /* Equal to 64MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT5) -+ pDimmInfo->size += 128; /* Equal to 128MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT6) -+ pDimmInfo->size += 256; /* Equal to 256MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT7) -+ pDimmInfo->size += 512; /* Equal to 512MB */ -+ } -+ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ -+ { -+ if (pDimmInfo->dimmBankDensity & BIT0) -+ pDimmInfo->size += 1024; /* Equal to 1GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT1) -+ pDimmInfo->size += 2048; /* Equal to 2GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT2) -+ pDimmInfo->size += 4096; /* Equal to 4GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT3) -+ pDimmInfo->size += 8192; /* Equal to 8GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT4) -+ pDimmInfo->size += 16384; /* Equal to 16GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT5) -+ pDimmInfo->size += 128; /* Equal to 128MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT6) -+ pDimmInfo->size += 256; /* Equal to 256MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT7) -+ pDimmInfo->size += 512; /* Equal to 512MB */ -+ } -+ -+ pDimmInfo->size *= pDimmInfo->numOfModuleBanks; -+ -+ DB(mvOsPrintf("Dram: dimm size %dMB \n",pDimmInfo->size)); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* dimmSpdPrint - Print the SPD parameters. -+* -+* DESCRIPTION: -+* Print the Dimm SPD parameters. -+* -+* INPUT: -+* pDimmInfo - DIMM information structure. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID dimmSpdPrint(MV_U32 dimmNum) -+{ -+ MV_DIMM_INFO dimmInfo; -+ MV_U32 i, temp = 0; -+ MV_U32 k, maskLeftOfPoint = 0, maskRightOfPoint = 0; -+ MV_U32 rightOfPoint = 0,leftOfPoint = 0, div, time_tmp, shift; -+ MV_U32 busClkPs; -+ MV_U8 trp_clocks=0, trcd_clocks, tras_clocks, trrd_clocks, -+ temp_buf[40], *spdRawData; -+ -+ busClkPs = 1000000000 / (mvBoardSysClkGet() / 100); /* in 10 ps units */ -+ -+ spdRawData = dimmInfo.spdRawData; -+ -+ if(MV_OK != dimmSpdGet(dimmNum, &dimmInfo)) -+ { -+ mvOsOutput("ERROR: Could not read SPD information!\n"); -+ return; -+ } -+ -+ /* find Manufactura of Dimm Module */ -+ mvOsOutput("\nManufacturer's JEDEC ID Code: "); -+ for(i = 0 ; i < DIMM_MODULE_MANU_SIZE ; i++) -+ { -+ mvOsOutput("%x",spdRawData[DIMM_MODULE_MANU_OFFS + i]); -+ } -+ mvOsOutput("\n"); -+ -+ /* Manufacturer's Specific Data */ -+ for(i = 0 ; i < DIMM_MODULE_ID_SIZE ; i++) -+ { -+ temp_buf[i] = spdRawData[DIMM_MODULE_ID_OFFS + i]; -+ } -+ mvOsOutput("Manufacturer's Specific Data: %s\n", temp_buf); -+ -+ /* Module Part Number */ -+ for(i = 0 ; i < DIMM_MODULE_VEN_SIZE ; i++) -+ { -+ temp_buf[i] = spdRawData[DIMM_MODULE_VEN_OFFS + i]; -+ } -+ mvOsOutput("Module Part Number: %s\n", temp_buf); -+ -+ /* Module Serial Number */ -+ for(i = 0; i < sizeof(MV_U32); i++) -+ { -+ temp |= spdRawData[95+i] << 8*i; -+ } -+ mvOsOutput("DIMM Serial No. %ld (%lx)\n", (long)temp, -+ (long)temp); -+ -+ /* find Manufac-Data of Dimm Module */ -+ mvOsOutput("Manufactoring Date: Year 20%d%d/ ww %d%d\n", -+ ((spdRawData[93] & 0xf0) >> 4), (spdRawData[93] & 0xf), -+ ((spdRawData[94] & 0xf0) >> 4), (spdRawData[94] & 0xf)); -+ /* find modul_revision of Dimm Module */ -+ mvOsOutput("Module Revision: %d.%d\n", -+ spdRawData[91], spdRawData[92]); -+ -+ /* find manufac_place of Dimm Module */ -+ mvOsOutput("manufac_place: %d\n", spdRawData[72]); -+ -+ /* go over the first 35 I2C data bytes */ -+ for(i = 2 ; i <= 35 ; i++) -+ switch(i) -+ { -+ case 2: /* Memory type (DDR1/2 / SDRAM) */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ mvOsOutput("Dram Type is: SDRAM\n"); -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ mvOsOutput("Dram Type is: SDRAM DDR1\n"); -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) -+ mvOsOutput("Dram Type is: SDRAM DDR2\n"); -+ else -+ mvOsOutput("Dram Type unknown\n"); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 3: /* Number Of Row Addresses */ -+ mvOsOutput("Module Number of row addresses: %d\n", -+ dimmInfo.numOfRowAddr); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 4: /* Number Of Column Addresses */ -+ mvOsOutput("Module Number of col addresses: %d\n", -+ dimmInfo.numOfColAddr); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 5: /* Number Of Module Banks */ -+ mvOsOutput("Number of Banks on Mod.: %d\n", -+ dimmInfo.numOfModuleBanks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 6: /* Data Width */ -+ mvOsOutput("Module Data Width: %d bit\n", -+ dimmInfo.dataWidth); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 8: /* Voltage Interface */ -+ switch(spdRawData[i]) -+ { -+ case 0x0: -+ mvOsOutput("Module is TTL_5V_TOLERANT\n"); -+ break; -+ case 0x1: -+ mvOsOutput("Module is LVTTL\n"); -+ break; -+ case 0x2: -+ mvOsOutput("Module is HSTL_1_5V\n"); -+ break; -+ case 0x3: -+ mvOsOutput("Module is SSTL_3_3V\n"); -+ break; -+ case 0x4: -+ mvOsOutput("Module is SSTL_2_5V\n"); -+ break; -+ case 0x5: -+ if (dimmInfo.memoryType != MEM_TYPE_SDRAM) -+ { -+ mvOsOutput("Module is SSTL_1_8V\n"); -+ break; -+ } -+ default: -+ mvOsOutput("Module is VOLTAGE_UNKNOWN\n"); -+ break; -+ } -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 9: /* Minimum Cycle Time At Max CasLatancy */ -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ rightOfPoint = (spdRawData[i] & 0x0f) * 10; -+ -+ /* DDR2 addition of right of point */ -+ if ((spdRawData[i] & 0x0f) == 0xA) -+ { -+ rightOfPoint = 25; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xB) -+ { -+ rightOfPoint = 33; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xC) -+ { -+ rightOfPoint = 66; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xD) -+ { -+ rightOfPoint = 75; -+ } -+ mvOsOutput("Minimum Cycle Time At Max CL: %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 10: /* Clock To Data Out */ -+ div = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 10:100; -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / div; -+ rightOfPoint = time_tmp % div; -+ mvOsOutput("Clock To Data Out: %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 11: /* Error Check Type */ -+ mvOsOutput("Error Check Type (0=NONE): %d\n", -+ dimmInfo.errorCheckType); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 12: /* Refresh Interval */ -+ mvOsOutput("Refresh Rate: %x\n", -+ dimmInfo.refreshInterval); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 13: /* Sdram Width */ -+ mvOsOutput("Sdram Width: %d bits\n", -+ dimmInfo.sdramWidth); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 14: /* Error Check Data Width */ -+ mvOsOutput("Error Check Data Width: %d bits\n", -+ dimmInfo.errorCheckDataWidth); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 15: /* Minimum Clock Delay is unsupported */ -+ if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || -+ (dimmInfo.memoryType == MEM_TYPE_DDR1)) -+ { -+ mvOsOutput("Minimum Clk Delay back to back: %d\n", -+ spdRawData[i]); -+ } -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 16: /* Burst Length Supported */ -+ /* SDRAM/DDR1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * -+ *********************************************************/ -+ /* DDR2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * -+ *********************************************************/ -+ mvOsOutput("Burst Length Supported: "); -+ if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || -+ (dimmInfo.memoryType == MEM_TYPE_DDR1)) -+ { -+ if (dimmInfo.burstLengthSupported & BIT0) -+ mvOsOutput("1, "); -+ if (dimmInfo.burstLengthSupported & BIT1) -+ mvOsOutput("2, "); -+ } -+ if (dimmInfo.burstLengthSupported & BIT2) -+ mvOsOutput("4, "); -+ if (dimmInfo.burstLengthSupported & BIT3) -+ mvOsOutput("8, "); -+ -+ mvOsOutput(" Bit \n"); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 17: /* Number Of Banks On Each Device */ -+ mvOsOutput("Number Of Banks On Each Chip: %d\n", -+ dimmInfo.numOfBanksOnEachDevice); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 18: /* Suported Cas Latencies */ -+ -+ /* SDRAM: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * -+ ********************************************************/ -+ -+ /* DDR 1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * -+ *********************************************************/ -+ -+ /* DDR 2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * -+ *********************************************************/ -+ -+ mvOsOutput("Suported Cas Latencies: (CL) "); -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ for (k = 0; k <=7; k++) -+ { -+ if (dimmInfo.suportedCasLatencies & (1 << k)) -+ mvOsOutput("%d, ", k+1); -+ } -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ { -+ if (dimmInfo.suportedCasLatencies & BIT0) -+ mvOsOutput("1, "); -+ if (dimmInfo.suportedCasLatencies & BIT1) -+ mvOsOutput("1.5, "); -+ if (dimmInfo.suportedCasLatencies & BIT2) -+ mvOsOutput("2, "); -+ if (dimmInfo.suportedCasLatencies & BIT3) -+ mvOsOutput("2.5, "); -+ if (dimmInfo.suportedCasLatencies & BIT4) -+ mvOsOutput("3, "); -+ if (dimmInfo.suportedCasLatencies & BIT5) -+ mvOsOutput("3.5, "); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) -+ { -+ if (dimmInfo.suportedCasLatencies & BIT2) -+ mvOsOutput("2, "); -+ if (dimmInfo.suportedCasLatencies & BIT3) -+ mvOsOutput("3, "); -+ if (dimmInfo.suportedCasLatencies & BIT4) -+ mvOsOutput("4, "); -+ if (dimmInfo.suportedCasLatencies & BIT5) -+ mvOsOutput("5, "); -+ } -+ else -+ mvOsOutput("?.?, "); -+ mvOsOutput("\n"); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 20: /* DDR2 DIMM type info */ -+ if (dimmInfo.memoryType == MEM_TYPE_DDR2) -+ { -+ if (dimmInfo.dimmTypeInfo & (BIT0 | BIT4)) -+ mvOsOutput("Registered DIMM (RDIMM)\n"); -+ else if (dimmInfo.dimmTypeInfo & (BIT1 | BIT5)) -+ mvOsOutput("Unbuffered DIMM (UDIMM)\n"); -+ else -+ mvOsOutput("Unknown DIMM type.\n"); -+ } -+ -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 21: /* SDRAM Modules Attributes */ -+ mvOsOutput("\nModule Attributes (SPD Byte 21): \n"); -+ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ if (dimmInfo.dimmAttributes & BIT0) -+ mvOsOutput(" Buffered Addr/Control Input: Yes\n"); -+ else -+ mvOsOutput(" Buffered Addr/Control Input: No\n"); -+ -+ if (dimmInfo.dimmAttributes & BIT1) -+ mvOsOutput(" Registered Addr/Control Input: Yes\n"); -+ else -+ mvOsOutput(" Registered Addr/Control Input: No\n"); -+ -+ if (dimmInfo.dimmAttributes & BIT2) -+ mvOsOutput(" On-Card PLL (clock): Yes \n"); -+ else -+ mvOsOutput(" On-Card PLL (clock): No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT3) -+ mvOsOutput(" Bufferd DQMB Input: Yes \n"); -+ else -+ mvOsOutput(" Bufferd DQMB Inputs: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT4) -+ mvOsOutput(" Registered DQMB Inputs: Yes \n"); -+ else -+ mvOsOutput(" Registered DQMB Inputs: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT5) -+ mvOsOutput(" Differential Clock Input: Yes \n"); -+ else -+ mvOsOutput(" Differential Clock Input: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT6) -+ mvOsOutput(" redundant Row Addressing: Yes \n"); -+ else -+ mvOsOutput(" redundant Row Addressing: No \n"); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ { -+ if (dimmInfo.dimmAttributes & BIT0) -+ mvOsOutput(" Buffered Addr/Control Input: Yes\n"); -+ else -+ mvOsOutput(" Buffered Addr/Control Input: No\n"); -+ -+ if (dimmInfo.dimmAttributes & BIT1) -+ mvOsOutput(" Registered Addr/Control Input: Yes\n"); -+ else -+ mvOsOutput(" Registered Addr/Control Input: No\n"); -+ -+ if (dimmInfo.dimmAttributes & BIT2) -+ mvOsOutput(" On-Card PLL (clock): Yes \n"); -+ else -+ mvOsOutput(" On-Card PLL (clock): No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT3) -+ mvOsOutput(" FET Switch On-Card Enabled: Yes \n"); -+ else -+ mvOsOutput(" FET Switch On-Card Enabled: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT4) -+ mvOsOutput(" FET Switch External Enabled: Yes \n"); -+ else -+ mvOsOutput(" FET Switch External Enabled: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT5) -+ mvOsOutput(" Differential Clock Input: Yes \n"); -+ else -+ mvOsOutput(" Differential Clock Input: No \n"); -+ } -+ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ -+ { -+ mvOsOutput(" Number of Active Registers on the DIMM: %d\n", -+ (dimmInfo.dimmAttributes & 0x3) + 1); -+ -+ mvOsOutput(" Number of PLLs on the DIMM: %d\n", -+ ((dimmInfo.dimmAttributes) >> 2) & 0x3); -+ -+ if (dimmInfo.dimmAttributes & BIT4) -+ mvOsOutput(" FET Switch External Enabled: Yes \n"); -+ else -+ mvOsOutput(" FET Switch External Enabled: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT6) -+ mvOsOutput(" Analysis probe installed: Yes \n"); -+ else -+ mvOsOutput(" Analysis probe installed: No \n"); -+ } -+ -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 22: /* Suported AutoPreCharge */ -+ mvOsOutput("\nModul Attributes (SPD Byte 22): \n"); -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ if ( spdRawData[i] & BIT0 ) -+ mvOsOutput(" Early Ras Precharge: Yes \n"); -+ else -+ mvOsOutput(" Early Ras Precharge: No \n"); -+ -+ if ( spdRawData[i] & BIT1 ) -+ mvOsOutput(" AutoPreCharge: Yes \n"); -+ else -+ mvOsOutput(" AutoPreCharge: No \n"); -+ -+ if ( spdRawData[i] & BIT2 ) -+ mvOsOutput(" Precharge All: Yes \n"); -+ else -+ mvOsOutput(" Precharge All: No \n"); -+ -+ if ( spdRawData[i] & BIT3 ) -+ mvOsOutput(" Write 1/ReadBurst: Yes \n"); -+ else -+ mvOsOutput(" Write 1/ReadBurst: No \n"); -+ -+ if ( spdRawData[i] & BIT4 ) -+ mvOsOutput(" lower VCC tolerance: 5%%\n"); -+ else -+ mvOsOutput(" lower VCC tolerance: 10%%\n"); -+ -+ if ( spdRawData[i] & BIT5 ) -+ mvOsOutput(" upper VCC tolerance: 5%%\n"); -+ else -+ mvOsOutput(" upper VCC tolerance: 10%%\n"); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ { -+ if ( spdRawData[i] & BIT0 ) -+ mvOsOutput(" Supports Weak Driver: Yes \n"); -+ else -+ mvOsOutput(" Supports Weak Driver: No \n"); -+ -+ if ( !(spdRawData[i] & BIT4) ) -+ mvOsOutput(" lower VCC tolerance: 0.2V\n"); -+ -+ if ( !(spdRawData[i] & BIT5) ) -+ mvOsOutput(" upper VCC tolerance: 0.2V\n"); -+ -+ if ( spdRawData[i] & BIT6 ) -+ mvOsOutput(" Concurrent Auto Preharge: Yes \n"); -+ else -+ mvOsOutput(" Concurrent Auto Preharge: No \n"); -+ -+ if ( spdRawData[i] & BIT7 ) -+ mvOsOutput(" Supports Fast AP: Yes \n"); -+ else -+ mvOsOutput(" Supports Fast AP: No \n"); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) -+ { -+ if ( spdRawData[i] & BIT0 ) -+ mvOsOutput(" Supports Weak Driver: Yes \n"); -+ else -+ mvOsOutput(" Supports Weak Driver: No \n"); -+ } -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 23: -+ /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */ -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ rightOfPoint = (spdRawData[i] & 0x0f) * 10; -+ -+ /* DDR2 addition of right of point */ -+ if ((spdRawData[i] & 0x0f) == 0xA) -+ { -+ rightOfPoint = 25; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xB) -+ { -+ rightOfPoint = 33; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xC) -+ { -+ rightOfPoint = 66; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xD) -+ { -+ rightOfPoint = 75; -+ } -+ -+ mvOsOutput("Minimum Cycle Time At 2nd highest CasLatancy" -+ "(0 = Not supported): %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint ); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 24: /* Clock To Data Out 2nd highest Cas Latency Value*/ -+ div = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? 10:100; -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / div; -+ rightOfPoint = time_tmp % div; -+ mvOsOutput("Clock To Data Out (2nd CL value): %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 25: -+ /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ leftOfPoint = (spdRawData[i] & 0xfc) >> 2; -+ rightOfPoint = (spdRawData[i] & 0x3) * 25; -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ rightOfPoint = (spdRawData[i] & 0x0f) * 10; -+ -+ /* DDR2 addition of right of point */ -+ if ((spdRawData[i] & 0x0f) == 0xA) -+ { -+ rightOfPoint = 25; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xB) -+ { -+ rightOfPoint = 33; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xC) -+ { -+ rightOfPoint = 66; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xD) -+ { -+ rightOfPoint = 75; -+ } -+ } -+ mvOsOutput("Minimum Cycle Time At 3rd highest CasLatancy" -+ "(0 = Not supported): %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint ); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 26: /* Clock To Data Out 3rd highest Cas Latency Value*/ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ leftOfPoint = (spdRawData[i] & 0xfc) >> 2; -+ rightOfPoint = (spdRawData[i] & 0x3) * 25; -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = 0; -+ rightOfPoint = time_tmp; -+ } -+ mvOsOutput("Clock To Data Out (3rd CL value): %d.%2d[ns]\n", -+ leftOfPoint, rightOfPoint ); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 27: /* Minimum Row Precharge Time */ -+ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; -+ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0xff : 0xfc; -+ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0x00 : 0x03; -+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); -+ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; -+ temp = ((leftOfPoint*100) + rightOfPoint);/* in 10ps Intervals*/ -+ trp_clocks = (temp + (busClkPs-1)) / busClkPs; -+ mvOsOutput("Minimum Row Precharge Time [ns]: %d.%d = " -+ "in Clk cycles %d\n", -+ leftOfPoint, rightOfPoint, trp_clocks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 28: /* Minimum Row Active to Row Active Time */ -+ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; -+ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0xff : 0xfc; -+ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0x00 : 0x03; -+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); -+ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; -+ temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ -+ trrd_clocks = (temp + (busClkPs-1)) / busClkPs; -+ mvOsOutput("Minimum Row Active -To- Row Active Delay [ns]: " -+ "%d.%d = in Clk cycles %d\n", -+ leftOfPoint, rightOfPoint, trp_clocks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 29: /* Minimum Ras-To-Cas Delay */ -+ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; -+ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0xff : 0xfc; -+ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0x00 : 0x03; -+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); -+ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; -+ temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ -+ trcd_clocks = (temp + (busClkPs-1) )/ busClkPs; -+ mvOsOutput("Minimum Ras-To-Cas Delay [ns]: %d.%d = " -+ "in Clk cycles %d\n", -+ leftOfPoint, rightOfPoint, trp_clocks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 30: /* Minimum Ras Pulse Width */ -+ tras_clocks = (cas2ps(spdRawData[i])+(busClkPs-1)) / busClkPs; -+ mvOsOutput("Minimum Ras Pulse Width [ns]: %d = " -+ "in Clk cycles %d\n", spdRawData[i], tras_clocks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 31: /* Module Bank Density */ -+ mvOsOutput("Module Bank Density (more than 1= Multisize-Module):"); -+ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ if (dimmInfo.dimmBankDensity & BIT0) -+ mvOsOutput("1GB, "); -+ if (dimmInfo.dimmBankDensity & BIT1) -+ mvOsOutput("8MB, "); -+ if (dimmInfo.dimmBankDensity & BIT2) -+ mvOsOutput("16MB, "); -+ if (dimmInfo.dimmBankDensity & BIT3) -+ mvOsOutput("32MB, "); -+ if (dimmInfo.dimmBankDensity & BIT4) -+ mvOsOutput("64MB, "); -+ if (dimmInfo.dimmBankDensity & BIT5) -+ mvOsOutput("128MB, "); -+ if (dimmInfo.dimmBankDensity & BIT6) -+ mvOsOutput("256MB, "); -+ if (dimmInfo.dimmBankDensity & BIT7) -+ mvOsOutput("512MB, "); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ { -+ if (dimmInfo.dimmBankDensity & BIT0) -+ mvOsOutput("1GB, "); -+ if (dimmInfo.dimmBankDensity & BIT1) -+ mvOsOutput("2GB, "); -+ if (dimmInfo.dimmBankDensity & BIT2) -+ mvOsOutput("16MB, "); -+ if (dimmInfo.dimmBankDensity & BIT3) -+ mvOsOutput("32MB, "); -+ if (dimmInfo.dimmBankDensity & BIT4) -+ mvOsOutput("64MB, "); -+ if (dimmInfo.dimmBankDensity & BIT5) -+ mvOsOutput("128MB, "); -+ if (dimmInfo.dimmBankDensity & BIT6) -+ mvOsOutput("256MB, "); -+ if (dimmInfo.dimmBankDensity & BIT7) -+ mvOsOutput("512MB, "); -+ } -+ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ -+ { -+ if (dimmInfo.dimmBankDensity & BIT0) -+ mvOsOutput("1GB, "); -+ if (dimmInfo.dimmBankDensity & BIT1) -+ mvOsOutput("2GB, "); -+ if (dimmInfo.dimmBankDensity & BIT2) -+ mvOsOutput("4GB, "); -+ if (dimmInfo.dimmBankDensity & BIT3) -+ mvOsOutput("8GB, "); -+ if (dimmInfo.dimmBankDensity & BIT4) -+ mvOsOutput("16GB, "); -+ if (dimmInfo.dimmBankDensity & BIT5) -+ mvOsOutput("128MB, "); -+ if (dimmInfo.dimmBankDensity & BIT6) -+ mvOsOutput("256MB, "); -+ if (dimmInfo.dimmBankDensity & BIT7) -+ mvOsOutput("512MB, "); -+ } -+ mvOsOutput("\n"); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 32: /* Address And Command Setup Time (measured in ns/1000) */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ rightOfPoint = (spdRawData[i] & 0x0f); -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ if(leftOfPoint > 7) -+ { -+ leftOfPoint *= -1; -+ } -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / 100; -+ rightOfPoint = time_tmp % 100; -+ } -+ mvOsOutput("Address And Command Setup Time [ns]: %d.%d\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 33: /* Address And Command Hold Time */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ rightOfPoint = (spdRawData[i] & 0x0f); -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ if(leftOfPoint > 7) -+ { -+ leftOfPoint *= -1; -+ } -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / 100; -+ rightOfPoint = time_tmp % 100; -+ } -+ mvOsOutput("Address And Command Hold Time [ns]: %d.%d\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 34: /* Data Input Setup Time */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ rightOfPoint = (spdRawData[i] & 0x0f); -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ if(leftOfPoint > 7) -+ { -+ leftOfPoint *= -1; -+ } -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / 100; -+ rightOfPoint = time_tmp % 100; -+ } -+ mvOsOutput("Data Input Setup Time [ns]: %d.%d\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 35: /* Data Input Hold Time */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ rightOfPoint = (spdRawData[i] & 0x0f); -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ if(leftOfPoint > 7) -+ { -+ leftOfPoint *= -1; -+ } -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / 100; -+ rightOfPoint = time_tmp % 100; -+ } -+ mvOsOutput("Data Input Hold Time [ns]: %d.%d\n\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 36: /* Relevant for DDR2 only: Write Recovery Time */ -+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> 2); -+ rightOfPoint = (spdRawData[i] & maskRightOfPoint) * 25; -+ mvOsOutput("Write Recovery Time [ns]: %d.%d\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ } -+ -+} -+ -+ -+/* -+ * translate ns.ns/10 coding of SPD timing values -+ * into ps unit values -+ */ -+/******************************************************************************* -+* cas2ps - Translate x.y ns parameter to pico-seconds values -+* -+* DESCRIPTION: -+* This function translates x.y nano seconds to its value in pico seconds. -+* For example 3.75ns will return 3750. -+* -+* INPUT: -+* spd_byte - DIMM SPD byte. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* value in pico seconds. -+* -+*******************************************************************************/ -+static MV_U32 cas2ps(MV_U8 spd_byte) -+{ -+ MV_U32 ns, ns10; -+ -+ /* isolate upper nibble */ -+ ns = (spd_byte >> 4) & 0x0F; -+ /* isolate lower nibble */ -+ ns10 = (spd_byte & 0x0F); -+ -+ if( ns10 < 10 ) { -+ ns10 *= 10; -+ } -+ else if( ns10 == 10 ) -+ ns10 = 25; -+ else if( ns10 == 11 ) -+ ns10 = 33; -+ else if( ns10 == 12 ) -+ ns10 = 66; -+ else if( ns10 == 13 ) -+ ns10 = 75; -+ else -+ { -+ mvOsOutput("cas2ps Err. unsupported cycle time.\n"); -+ } -+ -+ return (ns*1000 + ns10*10); -+} -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,191 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvDram -+#define __INCmvDram -+ -+#include "ddr1_2/mvDramIf.h" -+#include "twsi/mvTwsi.h" -+ -+#define MAX_DIMM_NUM 2 -+#define SPD_SIZE 128 -+ -+/* Dimm spd offsets */ -+#define DIMM_MEM_TYPE 2 -+#define DIMM_ROW_NUM 3 -+#define DIMM_COL_NUM 4 -+#define DIMM_MODULE_BANK_NUM 5 -+#define DIMM_DATA_WIDTH 6 -+#define DIMM_VOLT_IF 8 -+#define DIMM_MIN_CC_AT_MAX_CAS 9 -+#define DIMM_ERR_CHECK_TYPE 11 -+#define DIMM_REFRESH_INTERVAL 12 -+#define DIMM_SDRAM_WIDTH 13 -+#define DIMM_ERR_CHECK_DATA_WIDTH 14 -+#define DIMM_MIN_CLK_DEL 15 -+#define DIMM_BURST_LEN_SUP 16 -+#define DIMM_DEV_BANK_NUM 17 -+#define DIMM_SUP_CAL 18 -+#define DIMM_DDR2_TYPE_INFORMATION 20 /* DDR2 only */ -+#define DIMM_BUF_ADDR_CONT_IN 21 -+#define DIMM_MIN_CC_AT_MAX_CAS_MINUS1 23 -+#define DIMM_MIN_CC_AT_MAX_CAS_MINUS2 25 -+#define DIMM_MIN_ROW_PRECHARGE_TIME 27 -+#define DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE 28 -+#define DIMM_MIN_RAS_TO_CAS_DELAY 29 -+#define DIMM_MIN_RAS_PULSE_WIDTH 30 -+#define DIMM_BANK_DENSITY 31 -+#define DIMM_MIN_WRITE_RECOVERY_TIME 36 -+#define DIMM_MIN_WRITE_TO_READ_CMD_DELAY 37 -+#define DIMM_MIN_READ_TO_PRECH_CMD_DELAY 38 -+#define DIMM_MIN_REFRESH_TO_ACTIVATE_CMD 42 -+ -+/* Dimm Memory Type values */ -+#define DIMM_MEM_TYPE_SDRAM 0x4 -+#define DIMM_MEM_TYPE_DDR1 0x7 -+#define DIMM_MEM_TYPE_DDR2 0x8 -+ -+#define DIMM_MODULE_MANU_OFFS 64 -+#define DIMM_MODULE_MANU_SIZE 8 -+#define DIMM_MODULE_VEN_OFFS 73 -+#define DIMM_MODULE_VEN_SIZE 25 -+#define DIMM_MODULE_ID_OFFS 99 -+#define DIMM_MODULE_ID_SIZE 18 -+ -+/* enumeration for voltage levels. */ -+typedef enum _mvDimmVoltageIf -+{ -+ TTL_5V_TOLERANT, -+ LVTTL, -+ HSTL_1_5V, -+ SSTL_3_3V, -+ SSTL_2_5V, -+ VOLTAGE_UNKNOWN, -+} MV_DIMM_VOLTAGE_IF; -+ -+ -+/* enumaration for SDRAM CAS Latencies. */ -+typedef enum _mvDimmSdramCas -+{ -+ SD_CL_1 =1, -+ SD_CL_2, -+ SD_CL_3, -+ SD_CL_4, -+ SD_CL_5, -+ SD_CL_6, -+ SD_CL_7, -+ SD_FAULT -+}MV_DIMM_SDRAM_CAS; -+ -+ -+/* DIMM information structure */ -+typedef struct _mvDimmInfo -+{ -+ MV_MEMORY_TYPE memoryType; /* DDR or SDRAM */ -+ -+ MV_U8 spdRawData[SPD_SIZE]; /* Content of SPD-EEPROM copied 1:1 */ -+ -+ /* DIMM dimensions */ -+ MV_U32 numOfRowAddr; -+ MV_U32 numOfColAddr; -+ MV_U32 numOfModuleBanks; -+ MV_U32 dataWidth; -+ MV_U32 errorCheckType; /* ECC , PARITY..*/ -+ MV_U32 sdramWidth; /* 4,8,16 or 32 */ -+ MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ -+ MV_U32 burstLengthSupported; -+ MV_U32 numOfBanksOnEachDevice; -+ MV_U32 suportedCasLatencies; -+ MV_U32 refreshInterval; -+ MV_U32 dimmBankDensity; -+ MV_U32 dimmTypeInfo; /* DDR2 only */ -+ MV_U32 dimmAttributes; -+ -+ /* DIMM timing parameters */ -+ MV_U32 minCycleTimeAtMaxCasLatPs; -+ MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; -+ MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; -+ MV_U32 minRowPrechargeTime; -+ MV_U32 minRowActiveToRowActive; -+ MV_U32 minRasToCasDelay; -+ MV_U32 minRasPulseWidth; -+ MV_U32 minWriteRecoveryTime; /* DDR2 only */ -+ MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ -+ MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ -+ MV_U32 minRefreshToActiveCmd; /* DDR2 only */ -+ -+ /* Parameters calculated from the extracted DIMM information */ -+ MV_U32 size; /* 16,64,128,256 or 512 MByte in MB units */ -+ MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit in MB units */ -+ MV_U32 numberOfDevices; -+ -+} MV_DIMM_INFO; -+ -+ -+MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo); -+MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo); -+MV_VOID dimmSpdPrint(MV_U32 dimmNum); -+MV_STATUS dimmSpdCpy(MV_VOID); -+ -+#endif /* __INCmvDram */ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,1599 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+/* includes */ -+#include "ddr1_2/mvDramIf.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+ -+ -+ -+#ifdef MV_DEBUG -+#define DB(x) x -+#else -+#define DB(x) -+#endif -+ -+/* DRAM bank presence encoding */ -+#define BANK_PRESENT_CS0 0x1 -+#define BANK_PRESENT_CS0_CS1 0x3 -+#define BANK_PRESENT_CS0_CS2 0x5 -+#define BANK_PRESENT_CS0_CS1_CS2 0x7 -+#define BANK_PRESENT_CS0_CS2_CS3 0xd -+#define BANK_PRESENT_CS0_CS2_CS3_CS4 0xf -+ -+/* locals */ -+static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin); -+#if defined(MV_INC_BOARD_DDIM) -+static void sdramDDr2OdtConfig(MV_DRAM_BANK_INFO *pBankInfo); -+static MV_U32 dunitCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas); -+static MV_U32 sdramModeRegCalc(MV_U32 minCas); -+static MV_U32 sdramExtModeRegCalc(MV_DRAM_BANK_INFO *pBankInfo); -+static MV_U32 sdramAddrCtrlRegCalc(MV_DRAM_BANK_INFO *pBankInfo); -+static MV_U32 sdramConfigRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk); -+static MV_U32 minCasCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk, -+ MV_U32 forcedCl); -+static MV_U32 sdramTimeCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, -+ MV_U32 minCas, MV_U32 busClk); -+static MV_U32 sdramTimeCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, -+ MV_U32 busClk); -+ -+/******************************************************************************* -+* mvDramIfDetect - Prepare DRAM interface configuration values. -+* -+* DESCRIPTION: -+* This function implements the full DRAM detection and timing -+* configuration for best system performance. -+* Since this routine runs from a ROM device (Boot Flash), its stack -+* resides on RAM, that might be the system DRAM. Changing DRAM -+* configuration values while keeping vital data in DRAM is risky. That -+* is why the function does not preform the configuration setting but -+* prepare those in predefined 32bit registers (in this case IDMA -+* registers are used) for other routine to perform the settings. -+* The function will call for board DRAM SPD information for each DRAM -+* chip select. The function will then analyze those SPD parameters of -+* all DRAM banks in order to decide on DRAM configuration compatible -+* for all DRAM banks. -+* The function will set the CPU DRAM address decode registers. -+* Note: This routine prepares values that will overide configuration of -+* mvDramBasicAsmInit(). -+* -+* INPUT: -+* forcedCl - Forced CAL Latency. If equal to zero, do not force. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvDramIfDetect(MV_U32 forcedCl) -+{ -+ MV_U32 retVal = MV_OK; /* return value */ -+ MV_DRAM_BANK_INFO bankInfo[MV_DRAM_MAX_CS]; -+ MV_U32 busClk, size, base = 0, i, temp, deviceW, dimmW; -+ MV_U8 minCas; -+ MV_DRAM_DEC_WIN dramDecWin; -+ -+ dramDecWin.addrWin.baseHigh = 0; -+ -+ busClk = mvBoardSysClkGet(); -+ -+ if (0 == busClk) -+ { -+ mvOsPrintf("Dram: ERR. Can't detect system clock! \n"); -+ return MV_ERROR; -+ } -+ -+ /* Close DRAM banks except bank 0 (in case code is excecuting from it...) */ -+#if defined(MV_INCLUDE_SDRAM_CS1) -+ for(i= SDRAM_CS1; i < MV_DRAM_MAX_CS; i++) -+ mvCpuIfTargetWinEnable(i, MV_FALSE); -+#endif -+ -+ /* we will use bank 0 as the representative of the all the DRAM banks, */ -+ /* since bank 0 must exist. */ -+ for(i = 0; i < MV_DRAM_MAX_CS; i++) -+ { -+ /* if Bank exist */ -+ if(MV_OK == mvDramBankInfoGet(i, &bankInfo[i])) -+ { -+ /* check it isn't SDRAM */ -+ if(bankInfo[i].memoryType == MEM_TYPE_SDRAM) -+ { -+ mvOsPrintf("Dram: ERR. SDRAM type not supported !!!\n"); -+ return MV_ERROR; -+ } -+ /* All banks must support registry in order to activate it */ -+ if(bankInfo[i].registeredAddrAndControlInputs != -+ bankInfo[0].registeredAddrAndControlInputs) -+ { -+ mvOsPrintf("Dram: ERR. different Registered settings !!!\n"); -+ return MV_ERROR; -+ } -+ -+ /* Init the CPU window decode */ -+ /* Note that the size in Bank info is in MB units */ -+ /* Note that the Dimm width might be different then the device DRAM width */ -+ temp = MV_REG_READ(SDRAM_CONFIG_REG); -+ -+ deviceW = ((temp & SDRAM_DWIDTH_MASK) == SDRAM_DWIDTH_16BIT )? 16 : 32; -+ dimmW = bankInfo[0].dataWidth - (bankInfo[0].dataWidth % 16); -+ size = ((bankInfo[i].size << 20) / (dimmW/deviceW)); -+ -+ /* We can not change DRAM window settings while excecuting */ -+ /* code from it. That is why we skip the DRAM CS[0], saving */ -+ /* it to the ROM configuration routine */ -+ if(i == SDRAM_CS0) -+ { -+ MV_U32 sizeToReg; -+ -+ /* Translate the given window size to register format */ -+ sizeToReg = ctrlSizeToReg(size, SCSR_SIZE_ALIGNMENT); -+ -+ /* Size parameter validity check. */ -+ if (-1 == sizeToReg) -+ { -+ mvOsPrintf("mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n" -+ ,i); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Size is located at upper 16 bits */ -+ sizeToReg <<= SCSR_SIZE_OFFS; -+ -+ /* enable it */ -+ sizeToReg |= SCSR_WIN_EN; -+ -+ MV_REG_WRITE(DRAM_BUF_REG0, sizeToReg); -+ } -+ else -+ { -+ dramDecWin.addrWin.baseLow = base; -+ dramDecWin.addrWin.size = size; -+ dramDecWin.enable = MV_TRUE; -+ -+ if (MV_OK != mvDramIfWinSet(SDRAM_CS0 + i, &dramDecWin)) -+ { -+ mvOsPrintf("Dram: ERR. Fail to set bank %d!!!\n", -+ SDRAM_CS0 + i); -+ return MV_ERROR; -+ } -+ } -+ -+ base += size; -+ -+ /* update the suportedCasLatencies mask */ -+ bankInfo[0].suportedCasLatencies &= bankInfo[i].suportedCasLatencies; -+ -+ } -+ else -+ { -+ if( i == 0 ) /* bank 0 doesn't exist */ -+ { -+ mvOsPrintf("Dram: ERR. Fail to detect bank 0 !!!\n"); -+ return MV_ERROR; -+ } -+ else -+ { -+ DB(mvOsPrintf("Dram: Could not find bank %d\n", i)); -+ bankInfo[i].size = 0; /* Mark this bank as non exist */ -+ } -+ } -+ } -+ -+ /* calculate minimum CAS */ -+ minCas = minCasCalc(&bankInfo[0], busClk, forcedCl); -+ if (0 == minCas) -+ { -+ mvOsOutput("Dram: Warn: Could not find CAS compatible to SysClk %dMhz\n", -+ (busClk / 1000000)); -+ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ minCas = DDR2_CL_4; /* Continue with this CAS */ -+ mvOsPrintf("Set default CAS latency 4\n"); -+ } -+ else -+ { -+ minCas = DDR1_CL_3; /* Continue with this CAS */ -+ mvOsPrintf("Set default CAS latency 3\n"); -+ } -+ } -+ -+ /* calc SDRAM_CONFIG_REG and save it to temp register */ -+ temp = sdramConfigRegCalc(&bankInfo[0], busClk); -+ if(-1 == temp) -+ { -+ mvOsPrintf("Dram: ERR. sdramConfigRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG1, temp); -+ -+ /* calc SDRAM_MODE_REG and save it to temp register */ -+ temp = sdramModeRegCalc(minCas); -+ if(-1 == temp) -+ { -+ mvOsPrintf("Dram: ERR. sdramModeRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG2, temp); -+ -+ /* calc SDRAM_EXTENDED_MODE_REG and save it to temp register */ -+ temp = sdramExtModeRegCalc(&bankInfo[0]); -+ if(-1 == temp) -+ { -+ mvOsPrintf("Dram: ERR. sdramModeRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG10, temp); -+ -+ /* calc D_UNIT_CONTROL_LOW and save it to temp register */ -+ temp = dunitCtrlLowRegCalc(&bankInfo[0], minCas); -+ if(-1 == temp) -+ { -+ mvOsPrintf("Dram: ERR. dunitCtrlLowRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG3, temp); -+ -+ /* calc SDRAM_ADDR_CTRL_REG and save it to temp register */ -+ temp = sdramAddrCtrlRegCalc(&bankInfo[0]); -+ if(-1 == temp) -+ { -+ mvOsPrintf("Dram: ERR. sdramAddrCtrlRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG4, temp); -+ -+ /* calc SDRAM_TIMING_CTRL_LOW_REG and save it to temp register */ -+ temp = sdramTimeCtrlLowRegCalc(&bankInfo[0], minCas, busClk); -+ if(-1 == temp) -+ { -+ mvOsPrintf("Dram: ERR. sdramTimeCtrlLowRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG5, temp); -+ -+ /* calc SDRAM_TIMING_CTRL_HIGH_REG and save it to temp register */ -+ temp = sdramTimeCtrlHighRegCalc(&bankInfo[0], busClk); -+ if(-1 == temp) -+ { -+ mvOsPrintf("Dram: ERR. sdramTimeCtrlHighRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG6, temp); -+ -+ /* Config DDR2 On Die Termination (ODT) registers */ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ sdramDDr2OdtConfig(bankInfo); -+ } -+ -+ /* Note that DDR SDRAM Address/Control and Data pad calibration */ -+ /* settings is done in mvSdramIfConfig.s */ -+ -+ return retVal; -+} -+ -+/******************************************************************************* -+* minCasCalc - Calculate the Minimum CAS latency which can be used. -+* -+* DESCRIPTION: -+* Calculate the minimum CAS latency that can be used, base on the DRAM -+* parameters and the SDRAM bus Clock freq. -+* -+* INPUT: -+* busClk - the DRAM bus Clock. -+* pBankInfo - bank info parameters. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* The minimum CAS Latency. The function returns 0 if max CAS latency -+* supported by banks is incompatible with system bus clock frequancy. -+* -+*******************************************************************************/ -+static MV_U32 minCasCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk, -+ MV_U32 forcedCl) -+{ -+ MV_U32 count = 1, j; -+ MV_U32 busClkPs = 1000000000 / (busClk / 1000); /* in ps units */ -+ MV_U32 startBit, stopBit; -+ -+ /* DDR 1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * -+ *********************************************************/ -+ -+ /* DDR 2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * -+ *********************************************************/ -+ -+ -+ /* If we are asked to use the forced CAL */ -+ if (forcedCl) -+ { -+ mvOsPrintf("DRAM: Using forced CL %d.%d\n", (forcedCl / 10), -+ (forcedCl % 10)); -+ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ if (forcedCl == 30) -+ pBankInfo->suportedCasLatencies = 0x08; -+ else if (forcedCl == 40) -+ pBankInfo->suportedCasLatencies = 0x10; -+ else -+ { -+ mvOsPrintf("Forced CL %d.%d not supported. Set default CL 4\n", -+ (forcedCl / 10), (forcedCl % 10)); -+ pBankInfo->suportedCasLatencies = 0x10; -+ } -+ } -+ else -+ { -+ if (forcedCl == 15) -+ pBankInfo->suportedCasLatencies = 0x02; -+ else if (forcedCl == 20) -+ pBankInfo->suportedCasLatencies = 0x04; -+ else if (forcedCl == 25) -+ pBankInfo->suportedCasLatencies = 0x08; -+ else if (forcedCl == 30) -+ pBankInfo->suportedCasLatencies = 0x10; -+ else if (forcedCl == 40) -+ pBankInfo->suportedCasLatencies = 0x40; -+ else -+ { -+ mvOsPrintf("Forced CL %d.%d not supported. Set default CL 3\n", -+ (forcedCl / 10), (forcedCl % 10)); -+ pBankInfo->suportedCasLatencies = 0x10; -+ } -+ } -+ -+ return pBankInfo->suportedCasLatencies; -+ } -+ -+ /* go over the supported cas mask from Max Cas down and check if the */ -+ /* SysClk stands in its time requirments. */ -+ -+ -+ DB(mvOsPrintf("Dram: minCasCalc supported mask = %x busClkPs = %x \n", -+ pBankInfo->suportedCasLatencies,busClkPs )); -+ for(j = 7; j > 0; j--) -+ { -+ if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) -+ { -+ /* Reset the bits for CL incompatible for the sysClk */ -+ switch (count) -+ { -+ case 1: -+ if (pBankInfo->minCycleTimeAtMaxCasLatPs > busClkPs) -+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ case 2: -+ if (pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps > busClkPs) -+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ case 3: -+ if (pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps > busClkPs) -+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ default: -+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); -+ break; -+ } -+ } -+ } -+ -+ DB(mvOsPrintf("Dram: minCasCalc support = %x (after SysCC calc)\n", -+ pBankInfo->suportedCasLatencies )); -+ -+ /* SDRAM DDR1 controller supports CL 1.5 to 3.5 */ -+ /* SDRAM DDR2 controller supports CL 3 to 5 */ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ startBit = 3; /* DDR2 support CL start with CL3 (bit 3) */ -+ stopBit = 5; /* DDR2 support CL stops with CL5 (bit 5) */ -+ } -+ else -+ { -+ startBit = 1; /* DDR1 support CL start with CL1.5 (bit 3) */ -+ stopBit = 4; /* DDR1 support CL stops with CL3 (bit 4) */ -+ } -+ -+ for(j = startBit; j <= stopBit ; j++) -+ { -+ if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) -+ { -+ DB(mvOsPrintf("Dram: minCasCalc choose CAS %x \n",(BIT0 << j))); -+ return (BIT0 << j); -+ } -+ } -+ -+ return 0; -+} -+ -+/******************************************************************************* -+* sdramConfigRegCalc - Calculate sdram config register -+* -+* DESCRIPTION: Calculate sdram config register optimized value based -+* on the bank info parameters. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram config reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramConfigRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) -+{ -+ MV_U32 sdramConfig = 0; -+ MV_U32 refreshPeriod; -+ -+ busClk /= 1000000; /* we work with busClk in MHz */ -+ -+ sdramConfig = MV_REG_READ(SDRAM_CONFIG_REG); -+ -+ /* figure out the memory refresh internal */ -+ switch (pBankInfo->refreshInterval & 0xf) -+ { -+ case 0x0: /* refresh period is 15.625 usec */ -+ refreshPeriod = 15625; -+ break; -+ case 0x1: /* refresh period is 3.9 usec */ -+ refreshPeriod = 3900; -+ break; -+ case 0x2: /* refresh period is 7.8 usec */ -+ refreshPeriod = 7800; -+ break; -+ case 0x3: /* refresh period is 31.3 usec */ -+ refreshPeriod = 31300; -+ break; -+ case 0x4: /* refresh period is 62.5 usec */ -+ refreshPeriod = 62500; -+ break; -+ case 0x5: /* refresh period is 125 usec */ -+ refreshPeriod = 125000; -+ break; -+ default: /* refresh period undefined */ -+ mvOsPrintf("Dram: ERR. DRAM refresh period is unknown!\n"); -+ return -1; -+ } -+ -+ /* Now the refreshPeriod is in register format value */ -+ refreshPeriod = (busClk * refreshPeriod) / 1000; -+ -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc calculated refresh interval %0x\n", -+ refreshPeriod)); -+ -+ /* make sure the refresh value is only 14 bits */ -+ if(refreshPeriod > SDRAM_REFRESH_MAX) -+ { -+ refreshPeriod = SDRAM_REFRESH_MAX; -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc adjusted refresh interval %0x\n", -+ refreshPeriod)); -+ } -+ -+ /* Clear the refresh field */ -+ sdramConfig &= ~SDRAM_REFRESH_MASK; -+ -+ /* Set new value to refresh field */ -+ sdramConfig |= (refreshPeriod & SDRAM_REFRESH_MASK); -+ -+ /* registered DRAM ? */ -+ if ( pBankInfo->registeredAddrAndControlInputs ) -+ { -+ /* it's registered DRAM, so set the reg. DRAM bit */ -+ sdramConfig |= SDRAM_REGISTERED; -+ mvOsPrintf("DRAM Attribute: Registered address and control inputs.\n"); -+ } -+ -+ /* set DDR SDRAM devices configuration */ -+ sdramConfig &= ~SDRAM_DCFG_MASK; /* Clear Dcfg field */ -+ -+ switch (pBankInfo->sdramWidth) -+ { -+ case 8: /* memory is x8 */ -+ sdramConfig |= SDRAM_DCFG_X8_DEV; -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc SDRAM device width x8\n")); -+ break; -+ case 16: -+ sdramConfig |= SDRAM_DCFG_X16_DEV; -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc SDRAM device width x16\n")); -+ break; -+ default: /* memory width unsupported */ -+ mvOsPrintf("Dram: ERR. DRAM chip width is unknown!\n"); -+ return -1; -+ } -+ -+ /* Set static default settings */ -+ sdramConfig |= SDRAM_CONFIG_DV; -+ -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc set sdramConfig to 0x%x\n", -+ sdramConfig)); -+ -+ return sdramConfig; -+} -+ -+/******************************************************************************* -+* sdramModeRegCalc - Calculate sdram mode register -+* -+* DESCRIPTION: Calculate sdram mode register optimized value based -+* on the bank info parameters and the minCas. -+* -+* INPUT: -+* minCas - minimum CAS supported. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram mode reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramModeRegCalc(MV_U32 minCas) -+{ -+ MV_U32 sdramMode; -+ -+ sdramMode = MV_REG_READ(SDRAM_MODE_REG); -+ -+ /* Clear CAS Latency field */ -+ sdramMode &= ~SDRAM_CL_MASK; -+ -+ mvOsPrintf("DRAM CAS Latency "); -+ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ switch (minCas) -+ { -+ case DDR2_CL_3: -+ sdramMode |= SDRAM_DDR2_CL_3; -+ mvOsPrintf("3.\n"); -+ break; -+ case DDR2_CL_4: -+ sdramMode |= SDRAM_DDR2_CL_4; -+ mvOsPrintf("4.\n"); -+ break; -+ case DDR2_CL_5: -+ sdramMode |= SDRAM_DDR2_CL_5; -+ mvOsPrintf("5.\n"); -+ break; -+ default: -+ mvOsPrintf("\nsdramModeRegCalc ERROR: Max. CL out of range\n"); -+ return -1; -+ } -+ sdramMode |= DDR2_MODE_REG_DV; -+ } -+ else /* DDR1 */ -+ { -+ switch (minCas) -+ { -+ case DDR1_CL_1_5: -+ sdramMode |= SDRAM_DDR1_CL_1_5; -+ mvOsPrintf("1.5\n"); -+ break; -+ case DDR1_CL_2: -+ sdramMode |= SDRAM_DDR1_CL_2; -+ mvOsPrintf("2\n"); -+ break; -+ case DDR1_CL_2_5: -+ sdramMode |= SDRAM_DDR1_CL_2_5; -+ mvOsPrintf("2.5\n"); -+ break; -+ case DDR1_CL_3: -+ sdramMode |= SDRAM_DDR1_CL_3; -+ mvOsPrintf("3\n"); -+ break; -+ case DDR1_CL_4: -+ sdramMode |= SDRAM_DDR1_CL_4; -+ mvOsPrintf("4\n"); -+ break; -+ default: -+ mvOsPrintf("\nsdramModeRegCalc ERROR: Max. CL out of range\n"); -+ return -1; -+ } -+ sdramMode |= DDR1_MODE_REG_DV; -+ } -+ -+ DB(mvOsPrintf("nsdramModeRegCalc register 0x%x\n", sdramMode )); -+ -+ return sdramMode; -+} -+ -+/******************************************************************************* -+* sdramExtModeRegCalc - Calculate sdram Extended mode register -+* -+* DESCRIPTION: -+* Return sdram Extended mode register value based -+* on the bank info parameters and bank presence. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram Extended mode reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramExtModeRegCalc(MV_DRAM_BANK_INFO *pBankInfo) -+{ -+ MV_U32 populateBanks = 0; -+ int bankNum; -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ /* Represent the populate banks in binary form */ -+ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ if (0 != pBankInfo[bankNum].size) -+ { -+ populateBanks |= (1 << bankNum); -+ } -+ } -+ -+ switch(populateBanks) -+ { -+ case(BANK_PRESENT_CS0): -+ return DDR_SDRAM_EXT_MODE_CS0_DV; -+ -+ case(BANK_PRESENT_CS0_CS1): -+ return DDR_SDRAM_EXT_MODE_CS0_DV; -+ -+ case(BANK_PRESENT_CS0_CS2): -+ return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; -+ -+ case(BANK_PRESENT_CS0_CS1_CS2): -+ return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; -+ -+ case(BANK_PRESENT_CS0_CS2_CS3): -+ return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; -+ -+ case(BANK_PRESENT_CS0_CS2_CS3_CS4): -+ return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; -+ -+ default: -+ mvOsPrintf("sdramExtModeRegCalc: Invalid DRAM bank presence\n"); -+ return -1; -+ } -+ } -+ return 0; -+} -+ -+/******************************************************************************* -+* dunitCtrlLowRegCalc - Calculate sdram dunit control low register -+* -+* DESCRIPTION: Calculate sdram dunit control low register optimized value based -+* on the bank info parameters and the minCas. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* minCas - minimum CAS supported. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram dunit control low reg value. -+* -+*******************************************************************************/ -+static MV_U32 dunitCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas) -+{ -+ MV_U32 dunitCtrlLow; -+ -+ dunitCtrlLow = MV_REG_READ(SDRAM_DUNIT_CTRL_REG); -+ -+ /* Clear StBurstDel field */ -+ dunitCtrlLow &= ~SDRAM_ST_BURST_DEL_MASK; -+ -+#ifdef MV_88W8660 -+ /* Clear address/control output timing field */ -+ dunitCtrlLow &= ~SDRAM_CTRL_POS_RISE; -+#endif /* MV_88W8660 */ -+ -+ DB(mvOsPrintf("Dram: dunitCtrlLowRegCalc\n")); -+ -+ /* For proper sample of read data set the Dunit Control register's */ -+ /* stBurstDel bits [27:24] */ -+ /********-********-********-********-********-********* -+ * CL=1.5 | CL=2 | CL=2.5 | CL=3 | CL=4 | CL=5 * -+ *********-********-********-********-********-********* -+Not Reg. * 0011 | 0011 | 0100 | 0100 | 0101 | TBD * -+ *********-********-********-********-********-********* -+Registered * 0100 | 0100 | 0101 | 0101 | 0110 | TBD * -+ *********-********-********-********-********-*********/ -+ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ switch (minCas) -+ { -+ case DDR2_CL_3: -+ /* registerd DDR SDRAM? */ -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; -+ else -+ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; -+ break; -+ case DDR2_CL_4: -+ /* registerd DDR SDRAM? */ -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ dunitCtrlLow |= 0x6 << SDRAM_ST_BURST_DEL_OFFS; -+ else -+ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; -+ break; -+ default: -+ mvOsPrintf("Dram: dunitCtrlLowRegCalc Max. CL out of range %d\n", -+ minCas); -+ return -1; -+ } -+ } -+ else /* DDR1 */ -+ { -+ switch (minCas) -+ { -+ case DDR1_CL_1_5: -+ /* registerd DDR SDRAM? */ -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; -+ else -+ dunitCtrlLow |= 0x3 << SDRAM_ST_BURST_DEL_OFFS; -+ break; -+ case DDR1_CL_2: -+ /* registerd DDR SDRAM? */ -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; -+ else -+ dunitCtrlLow |= 0x3 << SDRAM_ST_BURST_DEL_OFFS; -+ break; -+ case DDR1_CL_2_5: -+ /* registerd DDR SDRAM? */ -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; -+ else -+ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; -+ break; -+ case DDR1_CL_3: -+ /* registerd DDR SDRAM? */ -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; -+ else -+ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; -+ break; -+ case DDR1_CL_4: -+ /* registerd DDR SDRAM? */ -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ dunitCtrlLow |= 0x6 << SDRAM_ST_BURST_DEL_OFFS; -+ else -+ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; -+ break; -+ default: -+ mvOsPrintf("Dram: dunitCtrlLowRegCalc Max. CL out of range %d\n", -+ minCas); -+ return -1; -+ } -+ -+ } -+ DB(mvOsPrintf("Dram: Reg dunit control low = %x\n", dunitCtrlLow )); -+ -+ return dunitCtrlLow; -+} -+ -+/******************************************************************************* -+* sdramAddrCtrlRegCalc - Calculate sdram address control register -+* -+* DESCRIPTION: Calculate sdram address control register optimized value based -+* on the bank info parameters and the minCas. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram address control reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramAddrCtrlRegCalc(MV_DRAM_BANK_INFO *pBankInfo) -+{ -+ MV_U32 addrCtrl = 0; -+ -+ /* Set Address Control register static configuration bits */ -+ addrCtrl = MV_REG_READ(SDRAM_ADDR_CTRL_REG); -+ -+ /* Set address control default value */ -+ addrCtrl |= SDRAM_ADDR_CTRL_DV; -+ -+ /* Clear DSize field */ -+ addrCtrl &= ~SDRAM_DSIZE_MASK; -+ -+ /* Note that density is in MB units */ -+ switch (pBankInfo->deviceDensity) -+ { -+ case 128: /* 128 Mbit */ -+ DB(mvOsPrintf("DRAM Device Density 128Mbit\n")); -+ addrCtrl |= SDRAM_DSIZE_128Mb; -+ break; -+ case 256: /* 256 Mbit */ -+ DB(mvOsPrintf("DRAM Device Density 256Mbit\n")); -+ addrCtrl |= SDRAM_DSIZE_256Mb; -+ break; -+ case 512: /* 512 Mbit */ -+ DB(mvOsPrintf("DRAM Device Density 512Mbit\n")); -+ addrCtrl |= SDRAM_DSIZE_512Mb; -+ break; -+ default: -+ mvOsPrintf("Dram: sdramAddrCtrl unsupported RAM-Device size %d\n", -+ pBankInfo->deviceDensity); -+ return -1; -+ } -+ -+ /* SDRAM address control */ -+ DB(mvOsPrintf("Dram: setting sdram address control with: %x \n", addrCtrl)); -+ -+ return addrCtrl; -+} -+ -+/******************************************************************************* -+* sdramTimeCtrlLowRegCalc - Calculate sdram timing control low register -+* -+* DESCRIPTION: -+* This function calculates sdram timing control low register -+* optimized value based on the bank info parameters and the minCas. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* busClk - Bus clock -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram timinf control low reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramTimeCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, -+ MV_U32 minCas, MV_U32 busClk) -+{ -+ MV_U32 tRp = 0; -+ MV_U32 tRrd = 0; -+ MV_U32 tRcd = 0; -+ MV_U32 tRas = 0; -+ MV_U32 tWr = 0; -+ MV_U32 tWtr = 0; -+ MV_U32 tRtp = 0; -+ -+ MV_U32 bankNum; -+ -+ busClk = busClk / 1000000; /* In MHz */ -+ -+ /* Scan all DRAM banks to find maximum timing values */ -+ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ tRp = MV_MAX(tRp, pBankInfo[bankNum].minRowPrechargeTime); -+ tRrd = MV_MAX(tRrd, pBankInfo[bankNum].minRowActiveToRowActive); -+ tRcd = MV_MAX(tRcd, pBankInfo[bankNum].minRasToCasDelay); -+ tRas = MV_MAX(tRas, pBankInfo[bankNum].minRasPulseWidth); -+ } -+ -+ /* Extract timing (in ns) from SPD value. We ignore the tenth ns part. */ -+ /* by shifting the data two bits right. */ -+ tRp = tRp >> 2; /* For example 0x50 -> 20ns */ -+ tRrd = tRrd >> 2; -+ tRcd = tRcd >> 2; -+ -+ /* Extract clock cycles from time parameter. We need to round up */ -+ tRp = ((busClk * tRp) / 1000) + (((busClk * tRp) % 1000) ? 1 : 0); -+ /* Micron work around for 133MHz */ -+ if (busClk == 133) -+ tRp += 1; -+ DB(mvOsPrintf("Dram Timing Low: tRp = %d ", tRp)); -+ tRrd = ((busClk * tRrd) / 1000) + (((busClk * tRrd) % 1000) ? 1 : 0); -+ /* JEDEC min reqeirments tRrd = 2 */ -+ if (tRrd < 2) -+ tRrd = 2; -+ DB(mvOsPrintf("tRrd = %d ", tRrd)); -+ tRcd = ((busClk * tRcd) / 1000) + (((busClk * tRcd) % 1000) ? 1 : 0); -+ DB(mvOsPrintf("tRcd = %d ", tRcd)); -+ tRas = ((busClk * tRas) / 1000) + (((busClk * tRas) % 1000) ? 1 : 0); -+ DB(mvOsPrintf("tRas = %d ", tRas)); -+ -+ /* tWr and tWtr is different for DDR1 and DDR2. tRtp is only for DDR2 */ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ /* Scan all DRAM banks to find maximum timing values */ -+ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ tWr = MV_MAX(tWr, pBankInfo[bankNum].minWriteRecoveryTime); -+ tWtr = MV_MAX(tWtr, pBankInfo[bankNum].minWriteToReadCmdDelay); -+ tRtp = MV_MAX(tRtp, pBankInfo[bankNum].minReadToPrechCmdDelay); -+ } -+ -+ /* Extract timing (in ns) from SPD value. We ignore the tenth ns */ -+ /* part by shifting the data two bits right. */ -+ tWr = tWr >> 2; /* For example 0x50 -> 20ns */ -+ tWtr = tWtr >> 2; -+ tRtp = tRtp >> 2; -+ -+ /* Extract clock cycles from time parameter. We need to round up */ -+ tWr = ((busClk * tWr) / 1000) + (((busClk * tWr) % 1000) ? 1 : 0); -+ DB(mvOsPrintf("tWr = %d ", tWr)); -+ tWtr = ((busClk * tWtr) / 1000) + (((busClk * tWtr) % 1000) ? 1 : 0); -+ /* JEDEC min reqeirments tWtr = 2 */ -+ if (tWtr < 2) -+ tWtr = 2; -+ DB(mvOsPrintf("tWtr = %d ", tWtr)); -+ tRtp = ((busClk * tRtp) / 1000) + (((busClk * tRtp) % 1000) ? 1 : 0); -+ /* JEDEC min reqeirments tRtp = 2 */ -+ if (tRtp < 2) -+ tRtp = 2; -+ DB(mvOsPrintf("tRtp = %d ", tRtp)); -+ } -+ else -+ { -+ tWr = ((busClk*SDRAM_TWR) / 1000) + (((busClk*SDRAM_TWR) % 1000)?1:0); -+ -+ if ((200 == busClk) || ((100 == busClk) && (DDR1_CL_1_5 == minCas))) -+ { -+ tWtr = 2; -+ } -+ else -+ { -+ tWtr = 1; -+ } -+ -+ tRtp = 2; /* Must be set to 0x1 (two cycles) when using DDR1 */ -+ } -+ -+ DB(mvOsPrintf("tWtr = %d\n", tWtr)); -+ -+ /* Note: value of 0 in register means one cycle, 1 means two and so on */ -+ return (((tRp - 1) << SDRAM_TRP_OFFS) | -+ ((tRrd - 1) << SDRAM_TRRD_OFFS) | -+ ((tRcd - 1) << SDRAM_TRCD_OFFS) | -+ ((tRas - 1) << SDRAM_TRAS_OFFS) | -+ ((tWr - 1) << SDRAM_TWR_OFFS) | -+ ((tWtr - 1) << SDRAM_TWTR_OFFS) | -+ ((tRtp - 1) << SDRAM_TRTP_OFFS)); -+} -+ -+/******************************************************************************* -+* sdramTimeCtrlHighRegCalc - Calculate sdram timing control high register -+* -+* DESCRIPTION: -+* This function calculates sdram timing control high register -+* optimized value based on the bank info parameters and the bus clock. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* busClk - Bus clock -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram timinf control high reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramTimeCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, -+ MV_U32 busClk) -+{ -+ MV_U32 tRfc; -+ MV_U32 timeNs = 0; -+ int bankNum; -+ MV_U32 sdramTw2wCyc = 0; -+ -+ busClk = busClk / 1000000; /* In MHz */ -+ -+ /* tRfc is different for DDR1 and DDR2. */ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ MV_U32 bankNum; -+ -+ /* Scan all DRAM banks to find maximum timing values */ -+ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ timeNs = MV_MAX(timeNs, pBankInfo[bankNum].minRefreshToActiveCmd); -+ } -+ else -+ { -+ if (pBankInfo[0].deviceDensity == _1G) -+ { -+ timeNs = SDRAM_TRFC_1G; -+ } -+ else -+ { -+ if (200 == busClk) -+ { -+ timeNs = SDRAM_TRFC_64_512M_AT_200MHZ; -+ } -+ else -+ { -+ timeNs = SDRAM_TRFC_64_512M; -+ } -+ } -+ } -+ -+ tRfc = ((busClk * timeNs) / 1000) + (((busClk * timeNs) % 1000) ? 1 : 0); -+ -+ DB(mvOsPrintf("Dram Timing High: tRfc = %d\n", tRfc)); -+ -+ -+ /* Represent the populate banks in binary form */ -+ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ if (0 != pBankInfo[bankNum].size) -+ sdramTw2wCyc++; -+ } -+ -+ /* If we have more the 1 bank then we need the TW2W in 1 for ODT switch */ -+ if (sdramTw2wCyc > 1) -+ sdramTw2wCyc = 1; -+ else -+ sdramTw2wCyc = 0; -+ -+ /* Note: value of 0 in register means one cycle, 1 means two and so on */ -+ return ((((tRfc - 1) & SDRAM_TRFC_MASK) << SDRAM_TRFC_OFFS) | -+ ((SDRAM_TR2R_CYC - 1) << SDRAM_TR2R_OFFS) | -+ ((SDRAM_TR2WW2R_CYC - 1) << SDRAM_TR2W_W2R_OFFS) | -+ (((tRfc - 1) >> 4) << SDRAM_TRFC_EXT_OFFS) | -+ (sdramTw2wCyc << SDRAM_TW2W_OFFS)); -+ -+} -+ -+/******************************************************************************* -+* sdramDDr2OdtConfig - Set DRAM DDR2 On Die Termination registers. -+* -+* DESCRIPTION: -+* This function config DDR2 On Die Termination (ODT) registers. -+* ODT configuration is done according to DIMM presence: -+* -+* Presence Ctrl Low Ctrl High Dunit Ctrl Ext Mode -+* CS0 0x84210000 0x00000000 0x0000780F 0x00000440 -+* CS0+CS1 0x84210000 0x00000000 0x0000780F 0x00000440 -+* CS0+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 -+* CS0+CS1+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 -+* CS0+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 -+* CS0+CS1+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 -+* -+* INPUT: -+* pBankInfo - bank info parameters. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* None -+*******************************************************************************/ -+static void sdramDDr2OdtConfig(MV_DRAM_BANK_INFO *pBankInfo) -+{ -+ MV_U32 populateBanks = 0; -+ MV_U32 odtCtrlLow, odtCtrlHigh, dunitOdtCtrl; -+ int bankNum; -+ -+ /* Represent the populate banks in binary form */ -+ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ if (0 != pBankInfo[bankNum].size) -+ { -+ populateBanks |= (1 << bankNum); -+ } -+ } -+ -+ switch(populateBanks) -+ { -+ case(BANK_PRESENT_CS0): -+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_DV; -+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_DV; -+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_DV; -+ break; -+ case(BANK_PRESENT_CS0_CS1): -+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_DV; -+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_DV; -+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_DV; -+ break; -+ case(BANK_PRESENT_CS0_CS2): -+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; -+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; -+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; -+ break; -+ case(BANK_PRESENT_CS0_CS1_CS2): -+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; -+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; -+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; -+ break; -+ case(BANK_PRESENT_CS0_CS2_CS3): -+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; -+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; -+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; -+ break; -+ case(BANK_PRESENT_CS0_CS2_CS3_CS4): -+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; -+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; -+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; -+ break; -+ default: -+ mvOsPrintf("sdramDDr2OdtConfig: Invalid DRAM bank presence\n"); -+ return; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG7, odtCtrlLow); -+ MV_REG_WRITE(DRAM_BUF_REG8, odtCtrlHigh); -+ MV_REG_WRITE(DRAM_BUF_REG9, dunitOdtCtrl); -+ return; -+} -+#endif /* defined(MV_INC_BOARD_DDIM) */ -+ -+/******************************************************************************* -+* mvDramIfWinSet - Set DRAM interface address decode window -+* -+* DESCRIPTION: -+* This function sets DRAM interface address decode window. -+* -+* INPUT: -+* target - System target. Use only SDRAM targets. -+* pAddrDecWin - SDRAM address window structure. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK -+* otherwise. -+*******************************************************************************/ -+MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) -+{ -+ MV_U32 baseReg=0,sizeReg=0; -+ MV_U32 baseToReg=0 , sizeToReg=0; -+ -+ /* Check parameters */ -+ if (!MV_TARGET_IS_DRAM(target)) -+ { -+ mvOsPrintf("mvDramIfWinSet: target %d is not SDRAM\n", target); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlaps with current enabled windows */ -+ if (MV_TRUE == sdramIfWinOverlap(target, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("mvDramIfWinSet: ERR. Target %d overlaps\n", target); -+ return MV_BAD_PARAM; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvDramIfWinSet:Error setting DRAM interface window %d."\ -+ "\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ target, -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ /* read base register*/ -+ baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(target)); -+ -+ /* read size register */ -+ sizeReg = MV_REG_READ(SDRAM_SIZE_REG(target)); -+ -+ /* BaseLow[31:16] => base register [31:16] */ -+ baseToReg = pAddrDecWin->addrWin.baseLow & SCBAR_BASE_MASK; -+ -+ /* Write to address decode Base Address Register */ -+ baseReg &= ~SCBAR_BASE_MASK; -+ baseReg |= baseToReg; -+ -+ /* Translate the given window size to register format */ -+ sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, SCSR_SIZE_ALIGNMENT); -+ -+ /* Size parameter validity check. */ -+ if (-1 == sizeToReg) -+ { -+ mvOsPrintf("mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n",target); -+ return MV_BAD_PARAM; -+ } -+ -+ /* set size */ -+ sizeReg &= ~SCSR_SIZE_MASK; -+ /* Size is located at upper 16 bits */ -+ sizeReg |= (sizeToReg << SCSR_SIZE_OFFS); -+ -+ /* enable/Disable */ -+ if (MV_TRUE == pAddrDecWin->enable) -+ { -+ sizeReg |= SCSR_WIN_EN; -+ } -+ else -+ { -+ sizeReg &= ~SCSR_WIN_EN; -+ } -+ -+ /* 3) Write to address decode Base Address Register */ -+ MV_REG_WRITE(SDRAM_BASE_ADDR_REG(target), baseReg); -+ -+ /* Write to address decode Size Register */ -+ MV_REG_WRITE(SDRAM_SIZE_REG(target), sizeReg); -+ -+ return MV_OK; -+} -+/******************************************************************************* -+* mvDramIfWinGet - Get DRAM interface address decode window -+* -+* DESCRIPTION: -+* This function gets DRAM interface address decode window. -+* -+* INPUT: -+* target - System target. Use only SDRAM targets. -+* -+* OUTPUT: -+* pAddrDecWin - SDRAM address window structure. -+* -+* RETURN: -+* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK -+* otherwise. -+*******************************************************************************/ -+MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) -+{ -+ MV_U32 baseReg,sizeReg; -+ MV_U32 sizeRegVal; -+ -+ /* Check parameters */ -+ if (!MV_TARGET_IS_DRAM(target)) -+ { -+ mvOsPrintf("mvDramIfWinGet: target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ /* Read base and size registers */ -+ sizeReg = MV_REG_READ(SDRAM_SIZE_REG(target)); -+ baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(target)); -+ -+ sizeRegVal = (sizeReg & SCSR_SIZE_MASK) >> SCSR_SIZE_OFFS; -+ -+ pAddrDecWin->addrWin.size = ctrlRegToSize(sizeRegVal, -+ SCSR_SIZE_ALIGNMENT); -+ -+ /* Check if ctrlRegToSize returned OK */ -+ if (-1 == pAddrDecWin->addrWin.size) -+ { -+ mvOsPrintf("mvDramIfWinGet: size of target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ /* Extract base address */ -+ /* Base register [31:16] ==> baseLow[31:16] */ -+ pAddrDecWin->addrWin.baseLow = baseReg & SCBAR_BASE_MASK; -+ -+ pAddrDecWin->addrWin.baseHigh = 0; -+ -+ -+ if (sizeReg & SCSR_WIN_EN) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ } -+ -+ return MV_OK; -+} -+/******************************************************************************* -+* mvDramIfWinEnable - Enable/Disable SDRAM address decode window -+* -+* DESCRIPTION: -+* This function enable/Disable SDRAM address decode window. -+* -+* INPUT: -+* target - System target. Use only SDRAM targets. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR in case function parameter are invalid, MV_OK otherewise. -+* -+*******************************************************************************/ -+MV_STATUS mvDramIfWinEnable(MV_TARGET target,MV_BOOL enable) -+{ -+ MV_DRAM_DEC_WIN addrDecWin; -+ -+ /* Check parameters */ -+ if (!MV_TARGET_IS_DRAM(target)) -+ { -+ mvOsPrintf("mvDramIfWinEnable: target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ if (enable == MV_TRUE) -+ { /* First check for overlap with other enabled windows */ -+ if (MV_OK != mvDramIfWinGet(target, &addrDecWin)) -+ { -+ mvOsPrintf("mvDramIfWinEnable:ERR. Getting target %d failed.\n", -+ target); -+ return MV_ERROR; -+ } -+ /* Check for overlapping */ -+ if (MV_FALSE == sdramIfWinOverlap(target, &(addrDecWin.addrWin))) -+ { -+ /* No Overlap. Enable address decode winNum window */ -+ MV_REG_BIT_SET(SDRAM_SIZE_REG(target), SCSR_WIN_EN); -+ } -+ else -+ { /* Overlap detected */ -+ mvOsPrintf("mvDramIfWinEnable: ERR. Target %d overlap detect\n", -+ target); -+ return MV_ERROR; -+ } -+ } -+ else -+ { /* Disable address decode winNum window */ -+ MV_REG_BIT_RESET(SDRAM_SIZE_REG(target), SCSR_WIN_EN); -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* sdramIfWinOverlap - Check if an address window overlap an SDRAM address window -+* -+* DESCRIPTION: -+* This function scan each SDRAM address decode window to test if it -+* overlapps the given address windoow -+* -+* INPUT: -+* target - SDRAM target where the function skips checking. -+* pAddrDecWin - The tested address window for overlapping with -+* SDRAM windows. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlaps any enabled address -+* decode map, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_TARGET targetNum; -+ MV_DRAM_DEC_WIN addrDecWin; -+ -+ for(targetNum = SDRAM_CS0; targetNum < MV_DRAM_MAX_CS ; targetNum++) -+ { -+ /* don't check our winNum or illegal targets */ -+ if (targetNum == target) -+ { -+ continue; -+ } -+ -+ /* Get window parameters */ -+ if (MV_OK != mvDramIfWinGet(targetNum, &addrDecWin)) -+ { -+ mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); -+ return MV_ERROR; -+ } -+ -+ /* Do not check disabled windows */ -+ if (MV_FALSE == addrDecWin.enable) -+ { -+ continue; -+ } -+ -+ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) -+ { -+ mvOsPrintf( -+ "sdramIfWinOverlap: Required target %d overlap winNum %d\n", -+ target, targetNum); -+ return MV_TRUE; -+ } -+ } -+ -+ return MV_FALSE; -+} -+ -+/******************************************************************************* -+* mvDramIfBankSizeGet - Get DRAM interface bank size. -+* -+* DESCRIPTION: -+* This function returns the size of a given DRAM bank. -+* -+* INPUT: -+* bankNum - Bank number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* DRAM bank size. If bank is disabled the function return '0'. In case -+* or paramter is invalid, the function returns -1. -+* -+*******************************************************************************/ -+MV_32 mvDramIfBankSizeGet(MV_U32 bankNum) -+{ -+ MV_DRAM_DEC_WIN addrDecWin; -+ -+ /* Check parameters */ -+ if (!MV_TARGET_IS_DRAM(bankNum)) -+ { -+ mvOsPrintf("mvDramIfBankBaseGet: bankNum %d is invalid\n", bankNum); -+ return -1; -+ } -+ /* Get window parameters */ -+ if (MV_OK != mvDramIfWinGet(bankNum, &addrDecWin)) -+ { -+ mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); -+ return -1; -+ } -+ -+ if (MV_TRUE == addrDecWin.enable) -+ { -+ return addrDecWin.addrWin.size; -+ } -+ else -+ { -+ return 0; -+ } -+} -+ -+ -+/******************************************************************************* -+* mvDramIfSizeGet - Get DRAM interface total size. -+* -+* DESCRIPTION: -+* This function get the DRAM total size. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* DRAM total size. In case or paramter is invalid, the function -+* returns -1. -+* -+*******************************************************************************/ -+MV_32 mvDramIfSizeGet(MV_VOID) -+{ -+ MV_U32 totalSize = 0, bankSize = 0, bankNum; -+ -+ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ bankSize = mvDramIfBankSizeGet(bankNum); -+ -+ if (-1 == bankSize) -+ { -+ mvOsPrintf("Dram: mvDramIfSizeGet error with bank %d \n",bankNum); -+ return -1; -+ } -+ else -+ { -+ totalSize += bankSize; -+ } -+ } -+ -+ DB(mvOsPrintf("Dram: Total DRAM size is 0x%x \n",totalSize)); -+ -+ return totalSize; -+} -+ -+/******************************************************************************* -+* mvDramIfBankBaseGet - Get DRAM interface bank base. -+* -+* DESCRIPTION: -+* This function returns the 32 bit base address of a given DRAM bank. -+* -+* INPUT: -+* bankNum - Bank number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* DRAM bank size. If bank is disabled or paramter is invalid, the -+* function returns -1. -+* -+*******************************************************************************/ -+MV_32 mvDramIfBankBaseGet(MV_U32 bankNum) -+{ -+ MV_DRAM_DEC_WIN addrDecWin; -+ -+ /* Check parameters */ -+ if (!MV_TARGET_IS_DRAM(bankNum)) -+ { -+ mvOsPrintf("mvDramIfBankBaseGet: bankNum %d is invalid\n", bankNum); -+ return -1; -+ } -+ /* Get window parameters */ -+ if (MV_OK != mvDramIfWinGet(bankNum, &addrDecWin)) -+ { -+ mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); -+ return -1; -+ } -+ -+ if (MV_TRUE == addrDecWin.enable) -+ { -+ return addrDecWin.addrWin.baseLow; -+ } -+ else -+ { -+ return -1; -+ } -+} -+ -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,179 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvDramIfh -+#define __INCmvDramIfh -+ -+/* includes */ -+#include "ddr1_2/mvDramIfRegs.h" -+#include "ddr1_2/mvDramIfConfig.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+ -+/* defines */ -+/* DRAM Timing parameters */ -+#define SDRAM_TWR 15 /* ns tWr */ -+#define SDRAM_TRFC_64_512M_AT_200MHZ 70 /* ns tRfc for dens 64-512 @ 200MHz */ -+#define SDRAM_TRFC_64_512M 75 /* ns tRfc for dens 64-512 */ -+#define SDRAM_TRFC_1G 120 /* ns tRfc for dens 1GB */ -+#define SDRAM_TR2R_CYC 1 /* cycle for tR2r */ -+#define SDRAM_TR2WW2R_CYC 1 /* cycle for tR2wW2r */ -+ -+/* typedefs */ -+ -+/* enumeration for memory types */ -+typedef enum _mvMemoryType -+{ -+ MEM_TYPE_SDRAM, -+ MEM_TYPE_DDR1, -+ MEM_TYPE_DDR2 -+}MV_MEMORY_TYPE; -+ -+/* enumeration for DDR1 supported CAS Latencies */ -+typedef enum _mvDimmDdr1Cas -+{ -+ DDR1_CL_1_5 = 0x02, -+ DDR1_CL_2 = 0x04, -+ DDR1_CL_2_5 = 0x08, -+ DDR1_CL_3 = 0x10, -+ DDR1_CL_4 = 0x40, -+ DDR1_CL_FAULT -+} MV_DIMM_DDR1_CAS; -+ -+/* enumeration for DDR2 supported CAS Latencies */ -+typedef enum _mvDimmDdr2Cas -+{ -+ DDR2_CL_3 = 0x08, -+ DDR2_CL_4 = 0x10, -+ DDR2_CL_5 = 0x20, -+ DDR2_CL_FAULT -+} MV_DIMM_DDR2_CAS; -+ -+ -+typedef struct _mvDramBankInfo -+{ -+ MV_MEMORY_TYPE memoryType; /* DDR1, DDR2 or SDRAM */ -+ -+ /* DIMM dimensions */ -+ MV_U32 numOfRowAddr; -+ MV_U32 numOfColAddr; -+ MV_U32 dataWidth; -+ MV_U32 errorCheckType; /* ECC , PARITY..*/ -+ MV_U32 sdramWidth; /* 4,8,16 or 32 */ -+ MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ -+ MV_U32 burstLengthSupported; -+ MV_U32 numOfBanksOnEachDevice; -+ MV_U32 suportedCasLatencies; -+ MV_U32 refreshInterval; -+ -+ /* DIMM timing parameters */ -+ MV_U32 minCycleTimeAtMaxCasLatPs; -+ MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; -+ MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; -+ MV_U32 minRowPrechargeTime; -+ MV_U32 minRowActiveToRowActive; -+ MV_U32 minRasToCasDelay; -+ MV_U32 minRasPulseWidth; -+ MV_U32 minWriteRecoveryTime; /* DDR2 only */ -+ MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ -+ MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ -+ MV_U32 minRefreshToActiveCmd; /* DDR2 only */ -+ -+ /* Parameters calculated from the extracted DIMM information */ -+ MV_U32 size; -+ MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit */ -+ MV_U32 numberOfDevices; -+ -+ /* DIMM attributes (MV_TRUE for yes) */ -+ MV_BOOL registeredAddrAndControlInputs; -+ -+}MV_DRAM_BANK_INFO; -+ -+/* This structure describes CPU interface address decode window */ -+typedef struct _mvDramIfDecWin -+{ -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+}MV_DRAM_DEC_WIN; -+ -+#include "ddr1_2/mvDram.h" -+ -+/* mvDramIf.h API list */ -+MV_VOID mvDramIfBasicAsmInit(MV_VOID); -+MV_STATUS mvDramIfDetect(MV_U32 forcedCl); -+MV_VOID _mvDramIfConfig(MV_VOID); -+ -+MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); -+MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); -+MV_STATUS mvDramIfWinEnable(MV_TARGET target,MV_BOOL enable); -+MV_32 mvDramIfBankSizeGet(MV_U32 bankNum); -+MV_32 mvDramIfBankBaseGet(MV_U32 bankNum); -+MV_32 mvDramIfSizeGet(MV_VOID); -+ -+#if 0 -+MV_STATUS mvDramIfMbusCtrlSet(MV_XBAR_TARGET *pPizzaArbArray); -+MV_STATUS mvDramIfMbusToutSet(MV_U32 timeout, MV_BOOL enable); -+#endif -+ -+#endif /* __INCmvDramIfh */ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,192 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvDramIfConfigh -+#define __INCmvDramIfConfigh -+ -+/* includes */ -+ -+/* defines */ -+ -+/* registers defaults values */ -+ -+#define SDRAM_CONFIG_DV \ -+ (SDRAM_PERR_WRITE | \ -+ SDRAM_SRMODE | \ -+ SDRAM_SRCLK_GATED) -+ -+#define SDRAM_DUNIT_CTRL_LOW_DV \ -+ (SDRAM_CTRL_POS_RISE | \ -+ SDRAM_CLK1DRV_NORMAL | \ -+ SDRAM_LOCKEN_ENABLE) -+ -+#define SDRAM_ADDR_CTRL_DV 0 -+ -+#define SDRAM_TIMING_CTRL_LOW_REG_DV \ -+ ((0x2 << SDRAM_TRCD_OFFS) | \ -+ (0x2 << SDRAM_TRP_OFFS) | \ -+ (0x1 << SDRAM_TWR_OFFS) | \ -+ (0x0 << SDRAM_TWTR_OFFS) | \ -+ (0x5 << SDRAM_TRAS_OFFS) | \ -+ (0x1 << SDRAM_TRRD_OFFS)) -+/* TRFC 0x27, TW2W 0x1 */ -+#define SDRAM_TIMING_CTRL_HIGH_REG_DV (( 0x7 << SDRAM_TRFC_OFFS ) |\ -+ ( 0x2 << SDRAM_TRFC_EXT_OFFS) |\ -+ ( 0x1 << SDRAM_TW2W_OFFS)) -+ -+#define SDRAM_OPEN_PAGES_CTRL_REG_DV SDRAM_OPEN_PAGE_EN -+ -+/* DDR2 ODT default register values */ -+ -+/* Presence Ctrl Low Ctrl High Dunit Ctrl Ext Mode */ -+/* CS0 0x84210000 0x00000000 0x0000780F 0x00000440 */ -+/* CS0+CS1 0x84210000 0x00000000 0x0000780F 0x00000440 */ -+/* CS0+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -+/* CS0+CS1+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -+/* CS0+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -+/* CS0+CS1+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -+ -+#define DDR2_ODT_CTRL_LOW_CS0_DV 0x84210000 -+#define DDR2_ODT_CTRL_HIGH_CS0_DV 0x00000000 -+#define DDR2_DUNIT_ODT_CTRL_CS0_DV 0x0000780F -+#define DDR_SDRAM_EXT_MODE_CS0_DV 0x00000440 -+ -+#define DDR2_ODT_CTRL_LOW_CS0_CS2_DV 0x030C030C -+#define DDR2_ODT_CTRL_HIGH_CS0_CS2_DV 0x00000000 -+#define DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV 0x0000740F -+#define DDR_SDRAM_EXT_MODE_CS0_CS2_DV 0x00000404 -+ -+ -+/* DDR SDRAM Adderss/Control and Data Pads Calibration default values */ -+#define DDR1_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \ -+ (1 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) -+#define DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \ -+ (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) -+ -+ -+#define DDR1_DATA_PAD_STRENGTH_TYPICAL_DV \ -+ (1 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) -+#define DDR2_DATA_PAD_STRENGTH_TYPICAL_DV \ -+ (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) -+ -+/* DDR SDRAM Mode Register default value */ -+#define DDR1_MODE_REG_DV 0x00000000 -+#define DDR2_MODE_REG_DV 0x00000400 -+ -+/* DDR SDRAM Timing parameter default values */ -+#define DDR1_TIMING_LOW_DV 0x11602220 -+#define DDR1_TIMING_HIGH_DV 0x0000000d -+ -+#define DDR2_TIMING_LOW_DV 0x11812220 -+#define DDR2_TIMING_HIGH_DV 0x0000030f -+ -+/* For Guideline (GL# MEM-4) DQS Reference Delay Tuning */ -+#define FTDLL_DDR1_166MHZ ((0x1 << 0) | \ -+ (0x7F<< 12) | \ -+ (0x1 << 22)) -+ -+#define FTDLL_DDR1_133MHZ FTDLL_DDR1_166MHZ -+ -+#define FTDLL_DDR1_200MHZ ((0x1 << 0) | \ -+ (0x1 << 12) | \ -+ (0x3 << 14) | \ -+ (0x1 << 18) | \ -+ (0x1 << 22)) -+ -+ -+#define FTDLL_DDR2_166MHZ ((0x1 << 0) | \ -+ (0x1 << 12) | \ -+ (0x1 << 14) | \ -+ (0x1 << 16) | \ -+ (0x1 << 19) | \ -+ (0xF << 20)) -+ -+#define FTDLL_DDR2_133MHZ FTDLL_DDR2_166MHZ -+ -+#define FTDLL_DDR2_200MHZ ((0x1 << 0) | \ -+ (0x1 << 12) | \ -+ (0x1 << 14) | \ -+ (0x1 << 16) | \ -+ (0x1 << 19) | \ -+ (0xF << 20)) -+ -+#define FTDLL_DDR2_250MHZ 0x445001 -+ -+/* Orion 1 B1 and above */ -+#define FTDLL_DDR1_166MHZ_5181_B1 0x45D001 -+ -+/* Orion nas */ -+#define FTDLL_DDR2_166MHZ_5182 0x597001 -+ -+/* Orion 2 D0 and above */ -+#define FTDLL_DDR1_166MHZ_5281_D0 0x8D0001 -+#define FTDLL_DDR1_200MHZ_5281_D0 0x8D0001 -+#define FTDLL_DDR2_166MHZ_5281_D0 0x485001 -+#define FTDLL_DDR2_200MHZ_5281_D0 0x485001 -+#define FTDLL_DDR2_250MHZ_5281_D0 0x445001 -+#define FTDLL_DDR2_200MHZ_5281_D1 0x995001 -+#define FTDLL_DDR2_250MHZ_5281_D1 0x984801 -+ -+#endif /* __INCmvDramIfh */ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,306 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvDramIfRegsh -+#define __INCmvDramIfRegsh -+ -+ -+/* DDR SDRAM Controller Address Decode Registers */ -+/* SDRAM CSn Base Address Register (SCBAR) */ -+#define SDRAM_BASE_ADDR_REG(csNum) (0x1500 + (csNum * 8)) -+#define SCBAR_BASE_OFFS 16 -+#define SCBAR_BASE_MASK (0xffff << SCBAR_BASE_OFFS) -+#define SCBAR_BASE_ALIGNMENT 0x10000 -+ -+/* SDRAM CSn Size Register (SCSR) */ -+#define SDRAM_SIZE_REG(csNum) (0x1504 + (csNum * 8)) -+#define SCSR_WIN_EN BIT0 -+#define SCSR_SIZE_OFFS 16 -+#define SCSR_SIZE_MASK (0xffff << SCSR_SIZE_OFFS) -+#define SCSR_SIZE_ALIGNMENT 0x10000 -+ -+/* configuration register */ -+#define SDRAM_CONFIG_REG 0x1400 -+#define SDRAM_REFRESH_OFFS 0 -+#define SDRAM_REFRESH_MAX 0x3000 -+#define SDRAM_REFRESH_MASK (SDRAM_REFRESH_MAX << SDRAM_REFRESH_OFFS) -+#define SDRAM_DWIDTH_OFFS 14 -+#define SDRAM_DWIDTH_MASK (3 << SDRAM_DWIDTH_OFFS) -+#define SDRAM_DWIDTH_16BIT (1 << SDRAM_DWIDTH_OFFS) -+#define SDRAM_DWIDTH_32BIT (2 << SDRAM_DWIDTH_OFFS) -+#define SDRAM_DTYPE_OFFS 16 -+#define SDRAM_DTYPE_MASK (1 << SDRAM_DTYPE_OFFS) -+#define SDRAM_DTYPE_DDR1 (0 << SDRAM_DTYPE_OFFS) -+#define SDRAM_DTYPE_DDR2 (1 << SDRAM_DTYPE_OFFS) -+#define SDRAM_REGISTERED (1 << 17) -+#define SDRAM_PERR_OFFS 18 -+#define SDRAM_PERR_MASK (1 << SDRAM_PERR_OFFS) -+#define SDRAM_PERR_NO_WRITE (0 << SDRAM_PERR_OFFS) -+#define SDRAM_PERR_WRITE (1 << SDRAM_PERR_OFFS) -+#define SDRAM_DCFG_OFFS 20 -+#define SDRAM_DCFG_MASK (0x3 << SDRAM_DCFG_OFFS) -+#define SDRAM_DCFG_X16_DEV (1 << SDRAM_DCFG_OFFS) -+#define SDRAM_DCFG_X8_DEV (2 << SDRAM_DCFG_OFFS) -+#define SDRAM_SRMODE (1 << 24) -+#define SDRAM_SRCLK_OFFS 25 -+#define SDRAM_SRCLK_MASK (1 << SDRAM_SRCLK_OFFS) -+#define SDRAM_SRCLK_KEPT (0 << SDRAM_SRCLK_OFFS) -+#define SDRAM_SRCLK_GATED (1 << SDRAM_SRCLK_OFFS) -+#define SDRAM_CATTH_OFFS 26 -+#define SDRAM_CATTHR_EN (1 << SDRAM_CATTH_OFFS) -+ -+ -+/* dunit control register */ -+#define SDRAM_DUNIT_CTRL_REG 0x1404 -+#define SDRAM_CTRL_POS_OFFS 6 -+#define SDRAM_CTRL_POS_FALL (0 << SDRAM_CTRL_POS_OFFS) -+#define SDRAM_CTRL_POS_RISE (1 << SDRAM_CTRL_POS_OFFS) -+#define SDRAM_CLK1DRV_OFFS 12 -+#define SDRAM_CLK1DRV_MASK (1 << SDRAM_CLK1DRV_OFFS) -+#define SDRAM_CLK1DRV_HIGH_Z (0 << SDRAM_CLK1DRV_OFFS) -+#define SDRAM_CLK1DRV_NORMAL (1 << SDRAM_CLK1DRV_OFFS) -+#define SDRAM_LOCKEN_OFFS 18 -+#define SDRAM_LOCKEN_MASK (1 << SDRAM_LOCKEN_OFFS) -+#define SDRAM_LOCKEN_DISABLE (0 << SDRAM_LOCKEN_OFFS) -+#define SDRAM_LOCKEN_ENABLE (1 << SDRAM_LOCKEN_OFFS) -+#define SDRAM_ST_BURST_DEL_OFFS 24 -+#define SDRAM_ST_BURST_DEL_MAX 0xf -+#define SDRAM_ST_BURST_DEL_MASK (SDRAM_ST_BURST_DEL_MAX< busClkPs) -+ { -+ mvOsOutput("Dram: ERR. Bank %d doesn't support memory clock!!!\n", i); -+ return MV_ERROR; -+ } -+ -+ /* All banks must support registry in order to activate it */ -+ if(bankInfo[i].registeredAddrAndControlInputs != -+ bankInfo[0].registeredAddrAndControlInputs) -+ { -+ mvOsOutput("Dram: ERR. different Registered settings !!!\n"); -+ return MV_ERROR; -+ } -+ -+ /* All banks must support same ECC mode */ -+ if(bankInfo[i].errorCheckType != -+ bankInfo[0].errorCheckType) -+ { -+ mvOsOutput("Dram: ERR. different ECC settings !!!\n"); -+ return MV_ERROR; -+ } -+ -+ } -+ else -+ { -+ if( i == 0 ) /* bank 0 doesn't exist */ -+ { -+ mvOsOutput("Dram: ERR. Fail to detect bank 0 !!!\n"); -+ return MV_ERROR; -+ } -+ else -+ { -+ DB(mvOsPrintf("Dram: Could not find bank %d\n", i)); -+ bankInfo[i].size = 0; /* Mark this bank as non exist */ -+ } -+ } -+ } -+ -+#ifdef MV_INCLUDE_SDRAM_CS2 -+ if (bankInfo[SDRAM_CS0].size < bankInfo[SDRAM_CS2].size) -+ { -+ MV_DRAM_CS_order[0] = SDRAM_CS2; -+ MV_DRAM_CS_order[1] = SDRAM_CS3; -+ MV_DRAM_CS_order[2] = SDRAM_CS0; -+ MV_DRAM_CS_order[3] = SDRAM_CS1; -+ DRAM_CS_Order[0] = SDRAM_CS2; -+ DRAM_CS_Order[1] = SDRAM_CS3; -+ DRAM_CS_Order[2] = SDRAM_CS0; -+ DRAM_CS_Order[3] = SDRAM_CS1; -+ -+ } -+ else -+#endif -+ { -+ MV_DRAM_CS_order[0] = SDRAM_CS0; -+ MV_DRAM_CS_order[1] = SDRAM_CS1; -+ DRAM_CS_Order[0] = SDRAM_CS0; -+ DRAM_CS_Order[1] = SDRAM_CS1; -+#ifdef MV_INCLUDE_SDRAM_CS2 -+ MV_DRAM_CS_order[2] = SDRAM_CS2; -+ MV_DRAM_CS_order[3] = SDRAM_CS3; -+ DRAM_CS_Order[2] = SDRAM_CS2; -+ DRAM_CS_Order[3] = SDRAM_CS3; -+#endif -+ } -+ -+ for(j = 0; j < MV_DRAM_MAX_CS; j++) -+ { -+ i = MV_DRAM_CS_order[j]; -+ -+ if (0 == bankInfo[i].size) -+ continue; -+ -+ /* Init the CPU window decode */ -+ /* Note that the Dimm width might be different then the device DRAM width */ -+#ifdef MV78XX0 -+ temp = MV_REG_READ(SDRAM_CONFIG_REG); -+ deviceW = ((temp & SDRAM_DWIDTH_MASK) == SDRAM_DWIDTH_32BIT )? 32 : 64; -+#else -+ deviceW = 16 /* KW family */; -+#endif -+ dimmW = bankInfo[0].dataWidth - (bankInfo[0].dataWidth % 16); -+ size = ((bankInfo[i].size << 20) / (dimmW/deviceW)); -+ -+ /* We can not change DRAM window settings while excecuting */ -+ /* code from it. That is why we skip the DRAM CS[0], saving */ -+ /* it to the ROM configuration routine */ -+ -+ numOfAllDevices += bankInfo[i].numberOfDevices; -+ if (i == MV_DRAM_CS_order[0]) -+ { -+ MV_U32 sizeToReg; -+ /* Translate the given window size to register format */ -+ sizeToReg = ctrlSizeToReg(size, SCSR_SIZE_ALIGNMENT); -+ /* Size parameter validity check. */ -+ if (-1 == sizeToReg) -+ { -+ mvOsOutput("DRAM: mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n" -+ ,i); -+ return MV_BAD_PARAM; -+ } -+ -+ DB(mvOsPrintf("Dram: Bank 0 Size - %x\n",sizeToReg);) -+ sizeToReg = (sizeToReg << SCSR_SIZE_OFFS); -+ sizeToReg |= SCSR_WIN_EN; -+ MV_REG_WRITE(DRAM_BUF_REG0, sizeToReg); -+ } -+ else -+ { -+ dramDecWin.addrWin.baseLow = base; -+ dramDecWin.addrWin.size = size; -+ dramDecWin.enable = MV_TRUE; -+ DB(mvOsPrintf("Dram: Enable window %d base 0x%x, size=0x%x\n",i, base, size)); -+ -+ /* Check if the DRAM size is more then 3GByte */ -+ if (base < 0xC0000000) -+ { -+ DB(mvOsPrintf("Dram: Enable window %d base 0x%x, size=0x%x\n",i, base, size)); -+ if (MV_OK != mvCpuIfTargetWinSet(i, &dramDecWin)) -+ { -+ mvOsPrintf("Dram: ERR. Fail to set bank %d!!!\n", SDRAM_CS0 + i); -+ return MV_ERROR; -+ } -+ } -+ } -+ -+ base += size; -+ -+ /* update the suportedCasLatencies mask */ -+ bankInfo[0].suportedCasLatencies &= bankInfo[i].suportedCasLatencies; -+ } -+ -+ /* calculate minimum CAS */ -+ minCas = minCasCalc(&bankInfo[0], &bankInfo[2], busClk, forcedCl); -+ if (0 == minCas) -+ { -+ mvOsOutput("Dram: Warn: Could not find CAS compatible to SysClk %dMhz\n", -+ (busClk / 1000000)); -+ -+ minCas = DDR2_CL_4; /* Continue with this CAS */ -+ mvOsOutput("Set default CAS latency 4\n"); -+ } -+ -+ /* calc SDRAM_CONFIG_REG and save it to temp register */ -+ temp = sdramConfigRegCalc(&bankInfo[0],&bankInfo[2], busClk); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. sdramConfigRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ -+ /* check if ECC is enabled by the user */ -+ if(eccDisable) -+ { -+ /* turn off ECC*/ -+ temp &= ~BIT18; -+ } -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG1, temp); -+ -+ /* calc SDRAM_MODE_REG and save it to temp register */ -+ temp = sdramModeRegCalc(minCas); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. sdramModeRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: sdramModeRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG2, temp); -+ -+ /* calc SDRAM_EXTENDED_MODE_REG and save it to temp register */ -+ temp = sdramExtModeRegCalc(&bankInfo[0], busClk); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. sdramExtModeRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: sdramExtModeRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG10, temp); -+ -+ /* calc D_UNIT_CONTROL_LOW and save it to temp register */ -+ TTMode = MV_FALSE; -+ DB(mvOsPrintf("Dram: numOfAllDevices = %x\n",numOfAllDevices);) -+ if( (numOfAllDevices > 9) && (bankInfo[0].registeredAddrAndControlInputs == MV_FALSE) ) -+ { -+ if ( ( (numOfAllDevices > 9) && (busClk > MV_BOARD_SYSCLK_200MHZ) ) || -+ (numOfAllDevices > 18) ) -+ { -+ mvOsOutput("Enable 2T "); -+ TTMode = MV_TRUE; -+ } -+ } -+ -+ temp = dunitCtrlLowRegCalc(&bankInfo[0], minCas, busClk, TTMode ); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. dunitCtrlLowRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: dunitCtrlLowRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG3, temp); -+ -+ /* calc D_UNIT_CONTROL_HIGH and save it to temp register */ -+ temp = dunitCtrlHighRegCalc(&bankInfo[0], busClk); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. dunitCtrlHighRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: dunitCtrlHighRegCalc - %x\n",temp);) -+ /* check if ECC is enabled by the user */ -+ if(eccDisable) -+ { -+ /* turn off sample stage if no ecc */ -+ temp &= ~SDRAM__D2P_EN;; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG13, temp); -+ -+ /* calc SDRAM_ADDR_CTRL_REG and save it to temp register */ -+ temp = sdramAddrCtrlRegCalc(&bankInfo[0],&bankInfo[2]); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. sdramAddrCtrlRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: sdramAddrCtrlRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG4, temp); -+ -+ /* calc SDRAM_TIMING_CTRL_LOW_REG and save it to temp register */ -+ temp = sdramTimeCtrlLowRegCalc(&bankInfo[0], minCas, busClk); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. sdramTimeCtrlLowRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: sdramTimeCtrlLowRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG5, temp); -+ -+ /* calc SDRAM_TIMING_CTRL_HIGH_REG and save it to temp register */ -+ temp = sdramTimeCtrlHighRegCalc(&bankInfo[0], busClk); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. sdramTimeCtrlHighRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: sdramTimeCtrlHighRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG6, temp); -+ -+ sdramDDr2OdtConfig(bankInfo); -+ -+ /* calc DDR2_SDRAM_TIMING_LOW_REG and save it to temp register */ -+ temp = sdramDdr2TimeLoRegCalc(minCas); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. sdramDdr2TimeLoRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: sdramDdr2TimeLoRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG11, temp); -+ -+ /* calc DDR2_SDRAM_TIMING_HIGH_REG and save it to temp register */ -+ temp = sdramDdr2TimeHiRegCalc(minCas); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. sdramDdr2TimeHiRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: sdramDdr2TimeHiRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG12, temp); -+#endif -+ -+ /* Note that DDR SDRAM Address/Control and Data pad calibration */ -+ /* settings is done in mvSdramIfConfig.s */ -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvDramIfBankBaseGet - Get DRAM interface bank base. -+* -+* DESCRIPTION: -+* This function returns the 32 bit base address of a given DRAM bank. -+* -+* INPUT: -+* bankNum - Bank number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* DRAM bank size. If bank is disabled or paramter is invalid, the -+* function returns -1. -+* -+*******************************************************************************/ -+MV_U32 mvDramIfBankBaseGet(MV_U32 bankNum) -+{ -+ DB(mvOsPrintf("Dram: mvDramIfBankBaseGet Bank %d base addr is %x \n", -+ bankNum, mvCpuIfTargetWinBaseLowGet(SDRAM_CS0 + bankNum))); -+ return mvCpuIfTargetWinBaseLowGet(SDRAM_CS0 + bankNum); -+} -+ -+/******************************************************************************* -+* mvDramIfBankSizeGet - Get DRAM interface bank size. -+* -+* DESCRIPTION: -+* This function returns the size of a given DRAM bank. -+* -+* INPUT: -+* bankNum - Bank number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* DRAM bank size. If bank is disabled the function return '0'. In case -+* or paramter is invalid, the function returns -1. -+* -+*******************************************************************************/ -+MV_U32 mvDramIfBankSizeGet(MV_U32 bankNum) -+{ -+ DB(mvOsPrintf("Dram: mvDramIfBankSizeGet Bank %d size is %x \n", -+ bankNum, mvCpuIfTargetWinSizeGet(SDRAM_CS0 + bankNum))); -+ return mvCpuIfTargetWinSizeGet(SDRAM_CS0 + bankNum); -+} -+ -+ -+/******************************************************************************* -+* mvDramIfSizeGet - Get DRAM interface total size. -+* -+* DESCRIPTION: -+* This function get the DRAM total size. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* DRAM total size. In case or paramter is invalid, the function -+* returns -1. -+* -+*******************************************************************************/ -+MV_U32 mvDramIfSizeGet(MV_VOID) -+{ -+ MV_U32 size = 0, i; -+ -+ for(i = 0; i < MV_DRAM_MAX_CS; i++) -+ size += mvDramIfBankSizeGet(i); -+ -+ DB(mvOsPrintf("Dram: mvDramIfSizeGet size is %x \n",size)); -+ return size; -+} -+ -+/******************************************************************************* -+* mvDramIfSingleBitErrThresholdSet - Set single bit ECC threshold. -+* -+* DESCRIPTION: -+* The ECC single bit error threshold is the number of single bit -+* errors to happen before the Dunit generates an interrupt. -+* This function set single bit ECC threshold. -+* -+* INPUT: -+* threshold - threshold. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM if threshold is to big, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_STATUS mvDramIfSingleBitErrThresholdSet(MV_U32 threshold) -+{ -+ MV_U32 regVal; -+ -+ if (threshold > SECR_THRECC_MAX) -+ { -+ return MV_BAD_PARAM; -+ } -+ -+ regVal = MV_REG_READ(SDRAM_ECC_CONTROL_REG); -+ regVal &= ~SECR_THRECC_MASK; -+ regVal |= ((SECR_THRECC(threshold) & SECR_THRECC_MASK)); -+ MV_REG_WRITE(SDRAM_ECC_CONTROL_REG, regVal); -+ -+ return MV_OK; -+} -+ -+#ifndef MV_STATIC_DRAM_ON_BOARD -+/******************************************************************************* -+* minCasCalc - Calculate the Minimum CAS latency which can be used. -+* -+* DESCRIPTION: -+* Calculate the minimum CAS latency that can be used, base on the DRAM -+* parameters and the SDRAM bus Clock freq. -+* -+* INPUT: -+* busClk - the DRAM bus Clock. -+* pBankInfo - bank info parameters. -+* forcedCl - Forced CAS Latency multiplied by 10. If equal to zero, do not force. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* The minimum CAS Latency. The function returns 0 if max CAS latency -+* supported by banks is incompatible with system bus clock frequancy. -+* -+*******************************************************************************/ -+ -+static MV_U32 minCasCalc(MV_DRAM_BANK_INFO *pBankInfo,MV_DRAM_BANK_INFO *pBankInfo2, MV_U32 busClk, MV_U32 forcedCl) -+{ -+ MV_U32 count = 1, j; -+ MV_U32 busClkPs = 1000000000 / (busClk / 1000); /* in ps units */ -+ MV_U32 startBit, stopBit; -+ MV_U32 minCas0 = 0, minCas2 = 0; -+ -+ -+ /* DDR 2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * -+ Disco VI= * TBD | TBD | 5 | 4 | 3 | TBD | TBD | TBD * -+ Disco Duo= * TBD | 6 | 5 | 4 | 3 | TBD | TBD | TBD * -+ *********************************************************/ -+ -+ -+ /* If we are asked to use the forced CAL we change the suported CAL to be forcedCl only */ -+ if (forcedCl) -+ { -+ mvOsOutput("DRAM: Using forced CL %d.%d\n", (forcedCl / 10), (forcedCl % 10)); -+ -+ if (forcedCl == 30) -+ pBankInfo->suportedCasLatencies = 0x08; -+ else if (forcedCl == 40) -+ pBankInfo->suportedCasLatencies = 0x10; -+ else if (forcedCl == 50) -+ pBankInfo->suportedCasLatencies = 0x20; -+ else if (forcedCl == 60) -+ pBankInfo->suportedCasLatencies = 0x40; -+ else -+ { -+ mvOsPrintf("Forced CL %d.%d not supported. Set default CL 4\n", -+ (forcedCl / 10), (forcedCl % 10)); -+ pBankInfo->suportedCasLatencies = 0x10; -+ } -+ -+ return pBankInfo->suportedCasLatencies; -+ } -+ -+ /* go over the supported cas mask from Max Cas down and check if the */ -+ /* SysClk stands in its time requirments. */ -+ -+ DB(mvOsPrintf("Dram: minCasCalc supported mask = %x busClkPs = %x \n", -+ pBankInfo->suportedCasLatencies,busClkPs )); -+ count = 1; -+ for(j = 7; j > 0; j--) -+ { -+ if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) -+ { -+ /* Reset the bits for CL incompatible for the sysClk */ -+ switch (count) -+ { -+ case 1: -+ if (pBankInfo->minCycleTimeAtMaxCasLatPs > busClkPs) -+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ case 2: -+ if (pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps > busClkPs) -+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ case 3: -+ if (pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps > busClkPs) -+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ default: -+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); -+ break; -+ } -+ } -+ } -+ -+ DB(mvOsPrintf("Dram: minCasCalc support = %x (after SysCC calc)\n", -+ pBankInfo->suportedCasLatencies )); -+ -+ count = 1; -+ DB(mvOsPrintf("Dram2: minCasCalc supported mask = %x busClkPs = %x \n", -+ pBankInfo2->suportedCasLatencies,busClkPs )); -+ for(j = 7; j > 0; j--) -+ { -+ if((pBankInfo2->suportedCasLatencies >> j) & BIT0 ) -+ { -+ /* Reset the bits for CL incompatible for the sysClk */ -+ switch (count) -+ { -+ case 1: -+ if (pBankInfo2->minCycleTimeAtMaxCasLatPs > busClkPs) -+ pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ case 2: -+ if (pBankInfo2->minCycleTimeAtMaxCasLatMinus1Ps > busClkPs) -+ pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ case 3: -+ if (pBankInfo2->minCycleTimeAtMaxCasLatMinus2Ps > busClkPs) -+ pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ default: -+ pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); -+ break; -+ } -+ } -+ } -+ -+ DB(mvOsPrintf("Dram2: minCasCalc support = %x (after SysCC calc)\n", -+ pBankInfo2->suportedCasLatencies )); -+ -+ startBit = 3; /* DDR2 support CL start with CL3 (bit 3) */ -+ stopBit = 6; /* DDR2 support CL stops with CL6 (bit 6) */ -+ -+ for(j = startBit; j <= stopBit ; j++) -+ { -+ if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) -+ { -+ DB(mvOsPrintf("Dram: minCasCalc choose CAS %x \n",(BIT0 << j))); -+ minCas0 = (BIT0 << j); -+ break; -+ } -+ } -+ -+ for(j = startBit; j <= stopBit ; j++) -+ { -+ if((pBankInfo2->suportedCasLatencies >> j) & BIT0 ) -+ { -+ DB(mvOsPrintf("Dram: minCasCalc choose CAS %x \n",(BIT0 << j))); -+ minCas2 = (BIT0 << j); -+ break; -+ } -+ } -+ -+ if (minCas2 > minCas0) -+ return minCas2; -+ else -+ return minCas0; -+ -+ return 0; -+} -+ -+/******************************************************************************* -+* sdramConfigRegCalc - Calculate sdram config register -+* -+* DESCRIPTION: Calculate sdram config register optimized value based -+* on the bank info parameters. -+* -+* INPUT: -+* busClk - the DRAM bus Clock. -+* pBankInfo - sdram bank parameters -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram config reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramConfigRegCalc(MV_DRAM_BANK_INFO *pBankInfo,MV_DRAM_BANK_INFO *pBankInfo2, MV_U32 busClk) -+{ -+ MV_U32 sdramConfig = 0; -+ MV_U32 refreshPeriod; -+ -+ busClk /= 1000000; /* we work with busClk in MHz */ -+ -+ sdramConfig = MV_REG_READ(SDRAM_CONFIG_REG); -+ -+ /* figure out the memory refresh internal */ -+ switch (pBankInfo->refreshInterval & 0xf) -+ { -+ case 0x0: /* refresh period is 15.625 usec */ -+ refreshPeriod = 15625; -+ break; -+ case 0x1: /* refresh period is 3.9 usec */ -+ refreshPeriod = 3900; -+ break; -+ case 0x2: /* refresh period is 7.8 usec */ -+ refreshPeriod = 7800; -+ break; -+ case 0x3: /* refresh period is 31.3 usec */ -+ refreshPeriod = 31300; -+ break; -+ case 0x4: /* refresh period is 62.5 usec */ -+ refreshPeriod = 62500; -+ break; -+ case 0x5: /* refresh period is 125 usec */ -+ refreshPeriod = 125000; -+ break; -+ default: /* refresh period undefined */ -+ mvOsPrintf("Dram: ERR. DRAM refresh period is unknown!\n"); -+ return -1; -+ } -+ -+ /* Now the refreshPeriod is in register format value */ -+ refreshPeriod = (busClk * refreshPeriod) / 1000; -+ -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc calculated refresh interval %0x\n", -+ refreshPeriod)); -+ -+ /* make sure the refresh value is only 14 bits */ -+ if(refreshPeriod > SDRAM_REFRESH_MAX) -+ { -+ refreshPeriod = SDRAM_REFRESH_MAX; -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc adjusted refresh interval %0x\n", -+ refreshPeriod)); -+ } -+ -+ /* Clear the refresh field */ -+ sdramConfig &= ~SDRAM_REFRESH_MASK; -+ -+ /* Set new value to refresh field */ -+ sdramConfig |= (refreshPeriod & SDRAM_REFRESH_MASK); -+ -+ /* registered DRAM ? */ -+ if ( pBankInfo->registeredAddrAndControlInputs ) -+ { -+ /* it's registered DRAM, so set the reg. DRAM bit */ -+ sdramConfig |= SDRAM_REGISTERED; -+ DB(mvOsPrintf("DRAM Attribute: Registered address and control inputs.\n");) -+ } -+ -+ /* ECC and IERR support */ -+ sdramConfig &= ~SDRAM_ECC_MASK; /* Clear ECC field */ -+ sdramConfig &= ~SDRAM_IERR_MASK; /* Clear IErr field */ -+ -+ if ( pBankInfo->errorCheckType ) -+ { -+ sdramConfig |= SDRAM_ECC_EN; -+ sdramConfig |= SDRAM_IERR_REPORTE; -+ DB(mvOsPrintf("Dram: mvDramIfDetect Enabling ECC\n")); -+ } -+ else -+ { -+ sdramConfig |= SDRAM_ECC_DIS; -+ sdramConfig |= SDRAM_IERR_IGNORE; -+ DB(mvOsPrintf("Dram: mvDramIfDetect Disabling ECC!\n")); -+ } -+ /* Set static default settings */ -+ sdramConfig |= SDRAM_CONFIG_DV; -+ -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc set sdramConfig to 0x%x\n", -+ sdramConfig)); -+ -+ return sdramConfig; -+} -+ -+/******************************************************************************* -+* sdramModeRegCalc - Calculate sdram mode register -+* -+* DESCRIPTION: Calculate sdram mode register optimized value based -+* on the bank info parameters and the minCas. -+* -+* INPUT: -+* minCas - minimum CAS supported. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram mode reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramModeRegCalc(MV_U32 minCas) -+{ -+ MV_U32 sdramMode; -+ -+ sdramMode = MV_REG_READ(SDRAM_MODE_REG); -+ -+ /* Clear CAS Latency field */ -+ sdramMode &= ~SDRAM_CL_MASK; -+ -+ DB(mvOsPrintf("DRAM CAS Latency ");) -+ -+ switch (minCas) -+ { -+ case DDR2_CL_3: -+ sdramMode |= SDRAM_DDR2_CL_3; -+ DB(mvOsPrintf("3.\n");) -+ break; -+ case DDR2_CL_4: -+ sdramMode |= SDRAM_DDR2_CL_4; -+ DB(mvOsPrintf("4.\n");) -+ break; -+ case DDR2_CL_5: -+ sdramMode |= SDRAM_DDR2_CL_5; -+ DB(mvOsPrintf("5.\n");) -+ break; -+ case DDR2_CL_6: -+ sdramMode |= SDRAM_DDR2_CL_6; -+ DB(mvOsPrintf("6.\n");) -+ break; -+ default: -+ mvOsOutput("\nsdramModeRegCalc ERROR: Max. CL out of range\n"); -+ return -1; -+ } -+ -+ DB(mvOsPrintf("\nsdramModeRegCalc register 0x%x\n", sdramMode )); -+ -+ return sdramMode; -+} -+/******************************************************************************* -+* sdramExtModeRegCalc - Calculate sdram Extended mode register -+* -+* DESCRIPTION: -+* Return sdram Extended mode register value based -+* on the bank info parameters and bank presence. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* busClk - DRAM frequency -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram Extended mode reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramExtModeRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) -+{ -+ MV_U32 populateBanks = 0; -+ int bankNum; -+ -+ /* Represent the populate banks in binary form */ -+ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ if (0 != pBankInfo[bankNum].size) -+ { -+ populateBanks |= (1 << bankNum); -+ } -+ } -+ -+ switch(populateBanks) -+ { -+ case(BANK_PRESENT_CS0): -+ case(BANK_PRESENT_CS0_CS1): -+ return DDR_SDRAM_EXT_MODE_CS0_CS1_DV; -+ -+ case(BANK_PRESENT_CS0_CS2): -+ case(BANK_PRESENT_CS0_CS1_CS2): -+ case(BANK_PRESENT_CS0_CS2_CS3): -+ case(BANK_PRESENT_CS0_CS2_CS3_CS4): -+ if (busClk >= MV_BOARD_SYSCLK_267MHZ) -+ return DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV; -+ else -+ return DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV; -+ -+ default: -+ mvOsOutput("sdramExtModeRegCalc: Invalid DRAM bank presence\n"); -+ return -1; -+ } -+ return 0; -+} -+ -+/******************************************************************************* -+* dunitCtrlLowRegCalc - Calculate sdram dunit control low register -+* -+* DESCRIPTION: Calculate sdram dunit control low register optimized value based -+* on the bank info parameters and the minCas. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* minCas - minimum CAS supported. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram dunit control low reg value. -+* -+*******************************************************************************/ -+static MV_U32 dunitCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas, MV_U32 busClk, MV_STATUS TTMode) -+{ -+ MV_U32 dunitCtrlLow, cl; -+ MV_U32 sbOutR[4]={3,5,7,9} ; -+ MV_U32 sbOutU[4]={1,3,5,7} ; -+ -+ dunitCtrlLow = MV_REG_READ(SDRAM_DUNIT_CTRL_REG); -+ -+ DB(mvOsPrintf("Dram: dunitCtrlLowRegCalc\n")); -+ -+ /* Clear StBurstOutDel field */ -+ dunitCtrlLow &= ~SDRAM_SB_OUT_MASK; -+ -+ /* Clear StBurstInDel field */ -+ dunitCtrlLow &= ~SDRAM_SB_IN_MASK; -+ -+ /* Clear CtrlPos field */ -+ dunitCtrlLow &= ~SDRAM_CTRL_POS_MASK; -+ -+ /* Clear 2T field */ -+ dunitCtrlLow &= ~SDRAM_2T_MASK; -+ if (TTMode == MV_TRUE) -+ { -+ dunitCtrlLow |= SDRAM_2T_MODE; -+ } -+ -+ /* For proper sample of read data set the Dunit Control register's */ -+ /* stBurstInDel bits [27:24] */ -+ /* 200MHz - 267MHz None reg = CL + 1 */ -+ /* 200MHz - 267MHz reg = CL + 2 */ -+ /* > 267MHz None reg = CL + 2 */ -+ /* > 267MHz reg = CL + 3 */ -+ -+ /* For proper sample of read data set the Dunit Control register's */ -+ /* stBurstOutDel bits [23:20] */ -+ /********-********-********-********- -+ * CL=3 | CL=4 | CL=5 | CL=6 | -+ *********-********-********-********- -+ Not Reg. * 0001 | 0011 | 0101 | 0111 | -+ *********-********-********-********- -+ Registered * 0011 | 0101 | 0111 | 1001 | -+ *********-********-********-********/ -+ -+ /* Set Dunit Control low default value */ -+ dunitCtrlLow |= SDRAM_DUNIT_CTRL_LOW_DDR2_DV; -+ -+ switch (minCas) -+ { -+ case DDR2_CL_3: cl = 3; break; -+ case DDR2_CL_4: cl = 4; break; -+ case DDR2_CL_5: cl = 5; break; -+ case DDR2_CL_6: cl = 6; break; -+ default: -+ mvOsOutput("Dram: dunitCtrlLowRegCalc Max. CL out of range %d\n", minCas); -+ return -1; -+ } -+ -+ /* registerd DDR SDRAM? */ -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ { -+ dunitCtrlLow |= (sbOutR[cl-3]) << SDRAM_SB_OUT_DEL_OFFS; -+ } -+ else -+ { -+ dunitCtrlLow |= (sbOutU[cl-3]) << SDRAM_SB_OUT_DEL_OFFS; -+ } -+ -+ DB(mvOsPrintf("\n\ndunitCtrlLowRegCalc: CL = %d, frequencies=%d\n", cl, busClk)); -+ -+ if (busClk <= MV_BOARD_SYSCLK_267MHZ) -+ { -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ cl = cl + 2; -+ else -+ cl = cl + 1; -+ } -+ else -+ { -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ cl = cl + 3; -+ else -+ cl = cl + 2; -+ } -+ -+ DB(mvOsPrintf("dunitCtrlLowRegCalc: SDRAM_SB_IN_DEL_OFFS = %d \n", cl)); -+ dunitCtrlLow |= cl << SDRAM_SB_IN_DEL_OFFS; -+ -+ DB(mvOsPrintf("Dram: Reg dunit control low = %x\n", dunitCtrlLow )); -+ -+ return dunitCtrlLow; -+} -+ -+/******************************************************************************* -+* dunitCtrlHighRegCalc - Calculate sdram dunit control high register -+* -+* DESCRIPTION: Calculate sdram dunit control high register optimized value based -+* on the bus clock. -+* -+* INPUT: -+* busClk - DRAM frequency. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram dunit control high reg value. -+* -+*******************************************************************************/ -+static MV_U32 dunitCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) -+{ -+ MV_U32 dunitCtrlHigh; -+ dunitCtrlHigh = MV_REG_READ(SDRAM_DUNIT_CTRL_HI_REG); -+ if(busClk > MV_BOARD_SYSCLK_300MHZ) -+ dunitCtrlHigh |= SDRAM__P2D_EN; -+ else -+ dunitCtrlHigh &= ~SDRAM__P2D_EN; -+ -+ if(busClk > MV_BOARD_SYSCLK_267MHZ) -+ dunitCtrlHigh |= (SDRAM__WR_MESH_DELAY_EN | SDRAM__PUP_ZERO_SKEW_EN | SDRAM__ADD_HALF_FCC_EN); -+ -+ /* If ECC support we turn on D2P sample */ -+ dunitCtrlHigh &= ~SDRAM__D2P_EN; /* Clear D2P bit */ -+ if (( pBankInfo->errorCheckType ) && (busClk > MV_BOARD_SYSCLK_267MHZ)) -+ dunitCtrlHigh |= SDRAM__D2P_EN; -+ -+ return dunitCtrlHigh; -+} -+ -+/******************************************************************************* -+* sdramAddrCtrlRegCalc - Calculate sdram address control register -+* -+* DESCRIPTION: Calculate sdram address control register optimized value based -+* on the bank info parameters and the minCas. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram address control reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramAddrCtrlRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_DRAM_BANK_INFO *pBankInfoDIMM1) -+{ -+ MV_U32 addrCtrl = 0; -+ -+ if (pBankInfoDIMM1->size) -+ { -+ switch (pBankInfoDIMM1->sdramWidth) -+ { -+ case 4: /* memory is x4 */ -+ mvOsOutput("sdramAddrCtrlRegCalc: Error - x4 not supported!\n"); -+ return -1; -+ break; -+ case 8: /* memory is x8 */ -+ addrCtrl |= SDRAM_ADDRSEL_X8(2) | SDRAM_ADDRSEL_X8(3); -+ DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device DIMM2 width x8\n")); -+ break; -+ case 16: -+ addrCtrl |= SDRAM_ADDRSEL_X16(2) | SDRAM_ADDRSEL_X16(3); -+ DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device DIMM2 width x16\n")); -+ break; -+ default: /* memory width unsupported */ -+ mvOsOutput("sdramAddrCtrlRegCalc: ERR. DRAM chip width is unknown!\n"); -+ return -1; -+ } -+ } -+ -+ switch (pBankInfo->sdramWidth) -+ { -+ case 4: /* memory is x4 */ -+ mvOsOutput("sdramAddrCtrlRegCalc: Error - x4 not supported!\n"); -+ return -1; -+ break; -+ case 8: /* memory is x8 */ -+ addrCtrl |= SDRAM_ADDRSEL_X8(0) | SDRAM_ADDRSEL_X8(1); -+ DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device width x8\n")); -+ break; -+ case 16: -+ addrCtrl |= SDRAM_ADDRSEL_X16(0) | SDRAM_ADDRSEL_X16(1); -+ DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device width x16\n")); -+ break; -+ default: /* memory width unsupported */ -+ mvOsOutput("sdramAddrCtrlRegCalc: ERR. DRAM chip width is unknown!\n"); -+ return -1; -+ } -+ -+ /* Note that density is in MB units */ -+ switch (pBankInfo->deviceDensity) -+ { -+ case 256: /* 256 Mbit */ -+ DB(mvOsPrintf("DRAM Device Density 256Mbit\n")); -+ addrCtrl |= SDRAM_DSIZE_256Mb(0) | SDRAM_DSIZE_256Mb(1); -+ break; -+ case 512: /* 512 Mbit */ -+ DB(mvOsPrintf("DRAM Device Density 512Mbit\n")); -+ addrCtrl |= SDRAM_DSIZE_512Mb(0) | SDRAM_DSIZE_512Mb(1); -+ break; -+ case 1024: /* 1 Gbit */ -+ DB(mvOsPrintf("DRAM Device Density 1Gbit\n")); -+ addrCtrl |= SDRAM_DSIZE_1Gb(0) | SDRAM_DSIZE_1Gb(1); -+ break; -+ case 2048: /* 2 Gbit */ -+ DB(mvOsPrintf("DRAM Device Density 2Gbit\n")); -+ addrCtrl |= SDRAM_DSIZE_2Gb(0) | SDRAM_DSIZE_2Gb(1); -+ break; -+ default: -+ mvOsOutput("Dram: sdramAddrCtrl unsupported RAM-Device size %d\n", -+ pBankInfo->deviceDensity); -+ return -1; -+ } -+ -+ if (pBankInfoDIMM1->size) -+ { -+ switch (pBankInfoDIMM1->deviceDensity) -+ { -+ case 256: /* 256 Mbit */ -+ DB(mvOsPrintf("DIMM2: DRAM Device Density 256Mbit\n")); -+ addrCtrl |= SDRAM_DSIZE_256Mb(2) | SDRAM_DSIZE_256Mb(3); -+ break; -+ case 512: /* 512 Mbit */ -+ DB(mvOsPrintf("DIMM2: DRAM Device Density 512Mbit\n")); -+ addrCtrl |= SDRAM_DSIZE_512Mb(2) | SDRAM_DSIZE_512Mb(3); -+ break; -+ case 1024: /* 1 Gbit */ -+ DB(mvOsPrintf("DIMM2: DRAM Device Density 1Gbit\n")); -+ addrCtrl |= SDRAM_DSIZE_1Gb(2) | SDRAM_DSIZE_1Gb(3); -+ break; -+ case 2048: /* 2 Gbit */ -+ DB(mvOsPrintf("DIMM2: DRAM Device Density 2Gbit\n")); -+ addrCtrl |= SDRAM_DSIZE_2Gb(2) | SDRAM_DSIZE_2Gb(3); -+ break; -+ default: -+ mvOsOutput("DIMM2: Dram: sdramAddrCtrl unsupported RAM-Device size %d\n", -+ pBankInfoDIMM1->deviceDensity); -+ return -1; -+ } -+ } -+ /* SDRAM address control */ -+ DB(mvOsPrintf("Dram: setting sdram address control with: %x \n", addrCtrl)); -+ -+ return addrCtrl; -+} -+ -+/******************************************************************************* -+* sdramTimeCtrlLowRegCalc - Calculate sdram timing control low register -+* -+* DESCRIPTION: -+* This function calculates sdram timing control low register -+* optimized value based on the bank info parameters and the minCas. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* minCas - minimum CAS supported. -+* busClk - Bus clock -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram timing control low reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramTimeCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas, MV_U32 busClk) -+{ -+ MV_U32 tRp = 0; -+ MV_U32 tRrd = 0; -+ MV_U32 tRcd = 0; -+ MV_U32 tRas = 0; -+ MV_U32 tWr = 0; -+ MV_U32 tWtr = 0; -+ MV_U32 tRtp = 0; -+ MV_U32 timeCtrlLow = 0; -+ -+ MV_U32 bankNum; -+ -+ busClk = busClk / 1000000; /* In MHz */ -+ -+ /* Scan all DRAM banks to find maximum timing values */ -+ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ tRp = MV_MAX(tRp, pBankInfo[bankNum].minRowPrechargeTime); -+ tRrd = MV_MAX(tRrd, pBankInfo[bankNum].minRowActiveToRowActive); -+ tRcd = MV_MAX(tRcd, pBankInfo[bankNum].minRasToCasDelay); -+ tRas = MV_MAX(tRas, pBankInfo[bankNum].minRasPulseWidth); -+ } -+ -+ /* Extract timing (in ns) from SPD value. We ignore the tenth ns part. */ -+ /* by shifting the data two bits right. */ -+ tRp = tRp >> 2; /* For example 0x50 -> 20ns */ -+ tRrd = tRrd >> 2; -+ tRcd = tRcd >> 2; -+ -+ /* Extract clock cycles from time parameter. We need to round up */ -+ tRp = ((busClk * tRp) / 1000) + (((busClk * tRp) % 1000) ? 1 : 0); -+ DB(mvOsPrintf("Dram Timing Low: tRp = %d ", tRp)); -+ tRrd = ((busClk * tRrd) / 1000) + (((busClk * tRrd) % 1000) ? 1 : 0); -+ /* JEDEC min reqeirments tRrd = 2 */ -+ if (tRrd < 2) -+ tRrd = 2; -+ DB(mvOsPrintf("tRrd = %d ", tRrd)); -+ tRcd = ((busClk * tRcd) / 1000) + (((busClk * tRcd) % 1000) ? 1 : 0); -+ DB(mvOsPrintf("tRcd = %d ", tRcd)); -+ tRas = ((busClk * tRas) / 1000) + (((busClk * tRas) % 1000) ? 1 : 0); -+ DB(mvOsPrintf("tRas = %d ", tRas)); -+ -+ /* tWr and tWtr is different for DDR1 and DDR2. tRtp is only for DDR2 */ -+ /* Scan all DRAM banks to find maximum timing values */ -+ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ tWr = MV_MAX(tWr, pBankInfo[bankNum].minWriteRecoveryTime); -+ tWtr = MV_MAX(tWtr, pBankInfo[bankNum].minWriteToReadCmdDelay); -+ tRtp = MV_MAX(tRtp, pBankInfo[bankNum].minReadToPrechCmdDelay); -+ } -+ -+ /* Extract timing (in ns) from SPD value. We ignore the tenth ns */ -+ /* part by shifting the data two bits right. */ -+ tWr = tWr >> 2; /* For example 0x50 -> 20ns */ -+ tWtr = tWtr >> 2; -+ tRtp = tRtp >> 2; -+ /* Extract clock cycles from time parameter. We need to round up */ -+ tWr = ((busClk * tWr) / 1000) + (((busClk * tWr) % 1000) ? 1 : 0); -+ DB(mvOsPrintf("tWr = %d ", tWr)); -+ tWtr = ((busClk * tWtr) / 1000) + (((busClk * tWtr) % 1000) ? 1 : 0); -+ /* JEDEC min reqeirments tWtr = 2 */ -+ if (tWtr < 2) -+ tWtr = 2; -+ DB(mvOsPrintf("tWtr = %d ", tWtr)); -+ tRtp = ((busClk * tRtp) / 1000) + (((busClk * tRtp) % 1000) ? 1 : 0); -+ /* JEDEC min reqeirments tRtp = 2 */ -+ if (tRtp < 2) -+ tRtp = 2; -+ DB(mvOsPrintf("tRtp = %d ", tRtp)); -+ -+ /* Note: value of 0 in register means one cycle, 1 means two and so on */ -+ timeCtrlLow = (((tRp - 1) << SDRAM_TRP_OFFS) | -+ ((tRrd - 1) << SDRAM_TRRD_OFFS) | -+ ((tRcd - 1) << SDRAM_TRCD_OFFS) | -+ (((tRas - 1) << SDRAM_TRAS_OFFS) & SDRAM_TRAS_MASK)| -+ ((tWr - 1) << SDRAM_TWR_OFFS) | -+ ((tWtr - 1) << SDRAM_TWTR_OFFS) | -+ ((tRtp - 1) << SDRAM_TRTP_OFFS)); -+ -+ /* Check extended tRas bit */ -+ if ((tRas - 1) & BIT4) -+ timeCtrlLow |= (1 << SDRAM_EXT_TRAS_OFFS); -+ -+ return timeCtrlLow; -+} -+ -+/******************************************************************************* -+* sdramTimeCtrlHighRegCalc - Calculate sdram timing control high register -+* -+* DESCRIPTION: -+* This function calculates sdram timing control high register -+* optimized value based on the bank info parameters and the bus clock. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* busClk - Bus clock -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram timing control high reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramTimeCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) -+{ -+ MV_U32 tRfc; -+ MV_U32 timingHigh; -+ MV_U32 timeNs = 0; -+ MV_U32 bankNum; -+ -+ busClk = busClk / 1000000; /* In MHz */ -+ -+ /* Set DDR timing high register static configuration bits */ -+ timingHigh = MV_REG_READ(SDRAM_TIMING_CTRL_HIGH_REG); -+ -+ /* Set DDR timing high register default value */ -+ timingHigh |= SDRAM_TIMING_CTRL_HIGH_REG_DV; -+ -+ /* Clear tRfc field */ -+ timingHigh &= ~SDRAM_TRFC_MASK; -+ -+ /* Scan all DRAM banks to find maximum timing values */ -+ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ timeNs = MV_MAX(timeNs, pBankInfo[bankNum].minRefreshToActiveCmd); -+ DB(mvOsPrintf("Dram: Timing High: minRefreshToActiveCmd = %d\n", -+ pBankInfo[bankNum].minRefreshToActiveCmd)); -+ } -+ if(busClk >= 333 && mvCtrlModelGet() == MV_78XX0_A1_REV) -+ { -+ timingHigh |= 0x1 << SDRAM_TR2W_W2R_OFFS; -+ } -+ -+ tRfc = ((busClk * timeNs) / 1000) + (((busClk * timeNs) % 1000) ? 1 : 0); -+ /* Note: value of 0 in register means one cycle, 1 means two and so on */ -+ DB(mvOsPrintf("Dram: Timing High: tRfc = %d\n", tRfc)); -+ timingHigh |= (((tRfc - 1) & SDRAM_TRFC_MASK) << SDRAM_TRFC_OFFS); -+ DB(mvOsPrintf("Dram: Timing High: tRfc = %d\n", tRfc)); -+ -+ /* SDRAM timing high */ -+ DB(mvOsPrintf("Dram: setting timing high with: %x \n", timingHigh)); -+ -+ return timingHigh; -+} -+/******************************************************************************* -+* sdramDDr2OdtConfig - Set DRAM DDR2 On Die Termination registers. -+* -+* DESCRIPTION: -+* This function config DDR2 On Die Termination (ODT) registers. -+* -+* INPUT: -+* pBankInfo - bank info parameters. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* None -+*******************************************************************************/ -+static void sdramDDr2OdtConfig(MV_DRAM_BANK_INFO *pBankInfo) -+{ -+ MV_U32 populateBanks = 0; -+ MV_U32 odtCtrlLow, odtCtrlHigh, dunitOdtCtrl; -+ int bankNum; -+ -+ /* Represent the populate banks in binary form */ -+ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ if (0 != pBankInfo[bankNum].size) -+ { -+ populateBanks |= (1 << bankNum); -+ } -+ } -+ -+ switch(populateBanks) -+ { -+ case(BANK_PRESENT_CS0): -+ case(BANK_PRESENT_CS0_CS1): -+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS1_DV; -+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS1_DV; -+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV; -+ break; -+ case(BANK_PRESENT_CS0_CS2): -+ case(BANK_PRESENT_CS0_CS1_CS2): -+ case(BANK_PRESENT_CS0_CS2_CS3): -+ case(BANK_PRESENT_CS0_CS2_CS3_CS4): -+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV; -+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS1_CS2_CS3_DV; -+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV; -+ break; -+ default: -+ DB(mvOsPrintf("sdramDDr2OdtConfig: Invalid DRAM bank presence\n")); -+ return; -+ } -+ /* DDR2 SDRAM ODT ctrl low */ -+ DB(mvOsPrintf("Dram: DDR2 setting ODT ctrl low with: %x \n", odtCtrlLow)); -+ MV_REG_WRITE(DRAM_BUF_REG7, odtCtrlLow); -+ -+ /* DDR2 SDRAM ODT ctrl high */ -+ DB(mvOsPrintf("Dram: DDR2 setting ODT ctrl high with: %x \n", odtCtrlHigh)); -+ MV_REG_WRITE(DRAM_BUF_REG8, odtCtrlHigh); -+ -+ /* DDR2 DUNIT ODT ctrl */ -+ if ( ((mvCtrlModelGet() == MV_78XX0_DEV_ID) && (mvCtrlRevGet() == MV_78XX0_Y0_REV)) || -+ (mvCtrlModelGet() == MV_76100_DEV_ID) || -+ (mvCtrlModelGet() == MV_78100_DEV_ID) || -+ (mvCtrlModelGet() == MV_78200_DEV_ID) ) -+ dunitOdtCtrl &= ~(BIT9|BIT8); /* Clear ODT always on */ -+ -+ DB(mvOsPrintf("DUNIT: DDR2 setting ODT ctrl with: %x \n", dunitOdtCtrl)); -+ MV_REG_WRITE(DRAM_BUF_REG9, dunitOdtCtrl); -+ return; -+} -+/******************************************************************************* -+* sdramDdr2TimeLoRegCalc - Set DDR2 DRAM Timing Low registers. -+* -+* DESCRIPTION: -+* This function config DDR2 DRAM Timing low registers. -+* -+* INPUT: -+* minCas - minimum CAS supported. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* DDR2 sdram timing low reg value. -+*******************************************************************************/ -+static MV_U32 sdramDdr2TimeLoRegCalc(MV_U32 minCas) -+{ -+ MV_U8 cl = -1; -+ MV_U32 ddr2TimeLoReg; -+ -+ /* read and clear the feilds we are going to set */ -+ ddr2TimeLoReg = MV_REG_READ(SDRAM_DDR2_TIMING_LO_REG); -+ ddr2TimeLoReg &= ~(SD2TLR_TODT_ON_RD_MASK | -+ SD2TLR_TODT_OFF_RD_MASK | -+ SD2TLR_TODT_ON_CTRL_RD_MASK | -+ SD2TLR_TODT_OFF_CTRL_RD_MASK); -+ -+ if( minCas == DDR2_CL_3 ) -+ { -+ cl = 3; -+ } -+ else if( minCas == DDR2_CL_4 ) -+ { -+ cl = 4; -+ } -+ else if( minCas == DDR2_CL_5 ) -+ { -+ cl = 5; -+ } -+ else if( minCas == DDR2_CL_6 ) -+ { -+ cl = 6; -+ } -+ else -+ { -+ DB(mvOsPrintf("sdramDdr2TimeLoRegCalc: CAS latency %d unsupported. using CAS latency 4\n", -+ minCas)); -+ cl = 4; -+ } -+ -+ ddr2TimeLoReg |= ((cl-3) << SD2TLR_TODT_ON_RD_OFFS); -+ ddr2TimeLoReg |= ( cl << SD2TLR_TODT_OFF_RD_OFFS); -+ ddr2TimeLoReg |= ( cl << SD2TLR_TODT_ON_CTRL_RD_OFFS); -+ ddr2TimeLoReg |= ((cl+3) << SD2TLR_TODT_OFF_CTRL_RD_OFFS); -+ -+ /* DDR2 SDRAM timing low */ -+ DB(mvOsPrintf("Dram: DDR2 setting timing low with: %x \n", ddr2TimeLoReg)); -+ -+ return ddr2TimeLoReg; -+} -+ -+/******************************************************************************* -+* sdramDdr2TimeHiRegCalc - Set DDR2 DRAM Timing High registers. -+* -+* DESCRIPTION: -+* This function config DDR2 DRAM Timing high registers. -+* -+* INPUT: -+* minCas - minimum CAS supported. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* DDR2 sdram timing high reg value. -+*******************************************************************************/ -+static MV_U32 sdramDdr2TimeHiRegCalc(MV_U32 minCas) -+{ -+ MV_U8 cl = -1; -+ MV_U32 ddr2TimeHiReg; -+ -+ /* read and clear the feilds we are going to set */ -+ ddr2TimeHiReg = MV_REG_READ(SDRAM_DDR2_TIMING_HI_REG); -+ ddr2TimeHiReg &= ~(SD2THR_TODT_ON_WR_MASK | -+ SD2THR_TODT_OFF_WR_MASK | -+ SD2THR_TODT_ON_CTRL_WR_MASK | -+ SD2THR_TODT_OFF_CTRL_WR_MASK); -+ -+ if( minCas == DDR2_CL_3 ) -+ { -+ cl = 3; -+ } -+ else if( minCas == DDR2_CL_4 ) -+ { -+ cl = 4; -+ } -+ else if( minCas == DDR2_CL_5 ) -+ { -+ cl = 5; -+ } -+ else if( minCas == DDR2_CL_6 ) -+ { -+ cl = 6; -+ } -+ else -+ { -+ mvOsOutput("sdramDdr2TimeHiRegCalc: CAS latency %d unsupported. using CAS latency 4\n", -+ minCas); -+ cl = 4; -+ } -+ -+ ddr2TimeHiReg |= ((cl-3) << SD2THR_TODT_ON_WR_OFFS); -+ ddr2TimeHiReg |= ( cl << SD2THR_TODT_OFF_WR_OFFS); -+ ddr2TimeHiReg |= ( cl << SD2THR_TODT_ON_CTRL_WR_OFFS); -+ ddr2TimeHiReg |= ((cl+3) << SD2THR_TODT_OFF_CTRL_WR_OFFS); -+ -+ /* DDR2 SDRAM timin high */ -+ DB(mvOsPrintf("Dram: DDR2 setting timing high with: %x \n", ddr2TimeHiReg)); -+ -+ return ddr2TimeHiReg; -+} -+#endif -+ -+/******************************************************************************* -+* mvDramIfCalGet - Get CAS Latency -+* -+* DESCRIPTION: -+* This function get the CAS Latency. -+* -+* INPUT: -+* None -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* CAS latency times 10 (to avoid using floating point). -+* -+*******************************************************************************/ -+MV_U32 mvDramIfCalGet(void) -+{ -+ MV_U32 sdramCasLat, casLatMask; -+ -+ casLatMask = (MV_REG_READ(SDRAM_MODE_REG) & SDRAM_CL_MASK); -+ -+ switch (casLatMask) -+ { -+ case SDRAM_DDR2_CL_3: -+ sdramCasLat = 30; -+ break; -+ case SDRAM_DDR2_CL_4: -+ sdramCasLat = 40; -+ break; -+ case SDRAM_DDR2_CL_5: -+ sdramCasLat = 50; -+ break; -+ case SDRAM_DDR2_CL_6: -+ sdramCasLat = 60; -+ break; -+ default: -+ mvOsOutput("mvDramIfCalGet: Err, unknown DDR2 CAL\n"); -+ return -1; -+ } -+ -+ return sdramCasLat; -+} -+ -+ -+/******************************************************************************* -+* mvDramIfSelfRefreshSet - Put the dram in self refresh mode - -+* -+* DESCRIPTION: -+* add support in power management. -+* -+* -+* INPUT: -+* None -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* None -+* -+*******************************************************************************/ -+ -+MV_VOID mvDramIfSelfRefreshSet() -+{ -+ MV_U32 operReg; -+ -+ operReg = MV_REG_READ(SDRAM_OPERATION_REG); -+ MV_REG_WRITE(SDRAM_OPERATION_REG ,operReg |SDRAM_CMD_SLF_RFRSH); -+ /* Read until register is reset to 0 */ -+ while(MV_REG_READ(SDRAM_OPERATION_REG)); -+} -+/******************************************************************************* -+* mvDramIfDimGetSPDversion - return DIMM SPD version. -+* -+* DESCRIPTION: -+* This function prints the DRAM controller information. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+static void mvDramIfDimGetSPDversion(MV_U32 *pMajor, MV_U32 *pMinor, MV_U32 bankNum) -+{ -+ MV_DIMM_INFO dimmInfo; -+ if (bankNum >= MV_DRAM_MAX_CS ) -+ { -+ DB(mvOsPrintf("Dram: mvDramIfDimGetSPDversion bad params \n")); -+ return ; -+ } -+ memset(&dimmInfo,0,sizeof(dimmInfo)); -+ if ( MV_OK != dimmSpdGet((MV_U32)(bankNum/2), &dimmInfo)) -+ { -+ DB(mvOsPrintf("Dram: ERR dimmSpdGet failed to get dimm info \n")); -+ return ; -+ } -+ *pMajor = dimmInfo.spdRawData[DIMM_SPD_VERSION]/10; -+ *pMinor = dimmInfo.spdRawData[DIMM_SPD_VERSION]%10; -+} -+/******************************************************************************* -+* mvDramIfShow - Show DRAM controller information. -+* -+* DESCRIPTION: -+* This function prints the DRAM controller information. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+void mvDramIfShow(void) -+{ -+ int i, sdramCasLat, sdramCsSize; -+ MV_U32 Major=0, Minor=0; -+ -+ mvOsOutput("DRAM Controller info:\n"); -+ -+ mvOsOutput("Total DRAM "); -+ mvSizePrint(mvDramIfSizeGet()); -+ mvOsOutput("\n"); -+ -+ for(i = 0; i < MV_DRAM_MAX_CS; i++) -+ { -+ sdramCsSize = mvDramIfBankSizeGet(i); -+ if (sdramCsSize) -+ { -+ if (0 == (i & 1)) -+ { -+ mvDramIfDimGetSPDversion(&Major, &Minor,i); -+ mvOsOutput("DIMM %d version %d.%d\n", i/2, Major, Minor); -+ } -+ mvOsOutput("\tDRAM CS[%d] ", i); -+ mvSizePrint(sdramCsSize); -+ mvOsOutput("\n"); -+ } -+ } -+ sdramCasLat = mvDramIfCalGet(); -+ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_ECC_EN) -+ { -+ mvOsOutput("ECC enabled, "); -+ } -+ else -+ { -+ mvOsOutput("ECC Disabled, "); -+ } -+ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_REGISTERED) -+ { -+ mvOsOutput("Registered DIMM\n"); -+ } -+ else -+ { -+ mvOsOutput("Non registered DIMM\n"); -+ } -+ -+ mvOsOutput("Configured CAS Latency %d.%d\n", sdramCasLat/10, sdramCasLat%10); -+} -+/******************************************************************************* -+* mvDramIfGetFirstCS - find the DRAM bank on the lower address -+* -+* -+* DESCRIPTION: -+* This function return the fisrt CS on address 0 -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* SDRAM_CS0 or SDRAM_CS2 -+* -+*******************************************************************************/ -+MV_U32 mvDramIfGetFirstCS(void) -+{ -+ MV_DRAM_BANK_INFO bankInfo[MV_DRAM_MAX_CS]; -+ -+ if (DRAM_CS_Order[0] == N_A) -+ { -+ mvDramBankInfoGet(SDRAM_CS0, &bankInfo[SDRAM_CS0]); -+#ifdef MV_INCLUDE_SDRAM_CS2 -+ mvDramBankInfoGet(SDRAM_CS2, &bankInfo[SDRAM_CS2]); -+#endif -+ -+#ifdef MV_INCLUDE_SDRAM_CS2 -+ if (bankInfo[SDRAM_CS0].size < bankInfo[SDRAM_CS2].size) -+ { -+ DRAM_CS_Order[0] = SDRAM_CS2; -+ DRAM_CS_Order[1] = SDRAM_CS3; -+ DRAM_CS_Order[2] = SDRAM_CS0; -+ DRAM_CS_Order[3] = SDRAM_CS1; -+ -+ return SDRAM_CS2; -+ } -+#endif -+ DRAM_CS_Order[0] = SDRAM_CS0; -+ DRAM_CS_Order[1] = SDRAM_CS1; -+#ifdef MV_INCLUDE_SDRAM_CS2 -+ DRAM_CS_Order[2] = SDRAM_CS2; -+ DRAM_CS_Order[3] = SDRAM_CS3; -+#endif -+ return SDRAM_CS0; -+ } -+ return DRAM_CS_Order[0]; -+} -+/******************************************************************************* -+* mvDramIfGetCSorder - -+* -+* -+* DESCRIPTION: -+* This function return the fisrt CS on address 0 -+* -+* INPUT: -+* CS number. -+* -+* OUTPUT: -+* CS order. -+* -+* RETURN: -+* SDRAM_CS0 or SDRAM_CS2 -+* -+* NOTE: mvDramIfGetFirstCS must be caled before this subroutine -+*******************************************************************************/ -+MV_U32 mvDramIfGetCSorder(MV_U32 csOrder ) -+{ -+ return DRAM_CS_Order[csOrder]; -+} -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,172 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvDramIfh -+#define __INCmvDramIfh -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* includes */ -+#include "ddr2/mvDramIfRegs.h" -+#include "ddr2/mvDramIfConfig.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+ -+/* defines */ -+/* DRAM Timing parameters */ -+#define SDRAM_TWR 15 /* ns tWr */ -+#define SDRAM_TRFC_64_512M_AT_200MHZ 70 /* ns tRfc for dens 64-512 @ 200MHz */ -+#define SDRAM_TRFC_64_512M 75 /* ns tRfc for dens 64-512 */ -+#define SDRAM_TRFC_1G 120 /* ns tRfc for dens 1GB */ -+#define SDRAM_TR2R_CYC 1 /* cycle for tR2r */ -+ -+#define CAL_AUTO_DETECT 0 /* Do not force CAS latancy (mvDramIfDetect) */ -+#define ECC_DISABLE 1 /* Force ECC to Disable */ -+#define ECC_ENABLE 0 /* Force ECC to ENABLE */ -+/* typedefs */ -+ -+/* enumeration for memory types */ -+typedef enum _mvMemoryType -+{ -+ MEM_TYPE_SDRAM, -+ MEM_TYPE_DDR1, -+ MEM_TYPE_DDR2 -+}MV_MEMORY_TYPE; -+ -+/* enumeration for DDR2 supported CAS Latencies */ -+typedef enum _mvDimmDdr2Cas -+{ -+ DDR2_CL_3 = 0x08, -+ DDR2_CL_4 = 0x10, -+ DDR2_CL_5 = 0x20, -+ DDR2_CL_6 = 0x40, -+ DDR2_CL_FAULT -+} MV_DIMM_DDR2_CAS; -+ -+ -+typedef struct _mvDramBankInfo -+{ -+ MV_MEMORY_TYPE memoryType; /* DDR1, DDR2 or SDRAM */ -+ -+ /* DIMM dimensions */ -+ MV_U32 numOfRowAddr; -+ MV_U32 numOfColAddr; -+ MV_U32 dataWidth; -+ MV_U32 errorCheckType; /* ECC , PARITY..*/ -+ MV_U32 sdramWidth; /* 4,8,16 or 32 */ -+ MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ -+ MV_U32 burstLengthSupported; -+ MV_U32 numOfBanksOnEachDevice; -+ MV_U32 suportedCasLatencies; -+ MV_U32 refreshInterval; -+ -+ /* DIMM timing parameters */ -+ MV_U32 minCycleTimeAtMaxCasLatPs; -+ MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; -+ MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; -+ MV_U32 minRowPrechargeTime; -+ MV_U32 minRowActiveToRowActive; -+ MV_U32 minRasToCasDelay; -+ MV_U32 minRasPulseWidth; -+ MV_U32 minWriteRecoveryTime; /* DDR2 only */ -+ MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ -+ MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ -+ MV_U32 minRefreshToActiveCmd; /* DDR2 only */ -+ -+ /* Parameters calculated from the extracted DIMM information */ -+ MV_U32 size; -+ MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit */ -+ MV_U32 numberOfDevices; -+ -+ /* DIMM attributes (MV_TRUE for yes) */ -+ MV_BOOL registeredAddrAndControlInputs; -+ MV_BOOL registeredDQMBinputs; -+ -+}MV_DRAM_BANK_INFO; -+ -+#include "ddr2/spd/mvSpd.h" -+ -+/* mvDramIf.h API list */ -+MV_VOID mvDramIfBasicAsmInit(MV_VOID); -+MV_STATUS mvDramIfDetect(MV_U32 forcedCl, MV_BOOL eccDisable); -+MV_VOID _mvDramIfConfig(int entryNum); -+ -+MV_U32 mvDramIfBankSizeGet(MV_U32 bankNum); -+MV_U32 mvDramIfBankBaseGet(MV_U32 bankNum); -+MV_U32 mvDramIfSizeGet(MV_VOID); -+MV_U32 mvDramIfCalGet(void); -+MV_STATUS mvDramIfSingleBitErrThresholdSet(MV_U32 threshold); -+MV_VOID mvDramIfSelfRefreshSet(void); -+void mvDramIfShow(void); -+MV_U32 mvDramIfGetFirstCS(void); -+MV_U32 mvDramIfGetCSorder(MV_U32 csOrder ); -+MV_U32 mvDramCsSizeGet(MV_U32 csNum); -+ -+#ifdef __cplusplus -+} -+#endif /* __cplusplus */ -+ -+#endif /* __INCmvDramIfh */ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,157 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvDramIfConfigh -+#define __INCmvDramIfConfigh -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* includes */ -+ -+/* defines */ -+ -+/* registers defaults values */ -+ -+#define SDRAM_CONFIG_DV (SDRAM_SRMODE_DRAM | BIT25 | BIT30) -+ -+#define SDRAM_DUNIT_CTRL_LOW_DDR2_DV \ -+ (SDRAM_SRCLK_KEPT | \ -+ SDRAM_CLK1DRV_NORMAL | \ -+ (BIT28 | BIT29)) -+ -+#define SDRAM_ADDR_CTRL_DV 2 -+ -+#define SDRAM_TIMING_CTRL_LOW_REG_DV \ -+ ((0x2 << SDRAM_TRCD_OFFS) | \ -+ (0x2 << SDRAM_TRP_OFFS) | \ -+ (0x1 << SDRAM_TWR_OFFS) | \ -+ (0x0 << SDRAM_TWTR_OFFS) | \ -+ (0x5 << SDRAM_TRAS_OFFS) | \ -+ (0x1 << SDRAM_TRRD_OFFS)) -+ -+/* Note: value of 0 in register means one cycle, 1 means two and so on */ -+#define SDRAM_TIMING_CTRL_HIGH_REG_DV \ -+ ((0x0 << SDRAM_TR2R_OFFS) | \ -+ (0x0 << SDRAM_TR2W_W2R_OFFS) | \ -+ (0x1 << SDRAM_TW2W_OFFS)) -+ -+#define SDRAM_OPEN_PAGES_CTRL_REG_DV SDRAM_OPEN_PAGE_EN -+ -+/* Presence Ctrl Low Ctrl High Dunit Ctrl Ext Mode */ -+/* CS0 0x84210000 0x00000000 0x0000780F 0x00000440 */ -+/* CS0+CS1 0x84210000 0x00000000 0x0000780F 0x00000440 */ -+/* CS0+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -+/* CS0+CS1+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -+/* CS0+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -+/* CS0+CS1+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -+ -+#define DDR2_ODT_CTRL_LOW_CS0_CS1_DV 0x84210000 -+#define DDR2_ODT_CTRL_HIGH_CS0_CS1_DV 0x00000000 -+#define DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV 0x0000E80F -+#ifdef MV78XX0 -+#define DDR_SDRAM_EXT_MODE_CS0_CS1_DV 0x00000040 -+#else -+#define DDR_SDRAM_EXT_MODE_CS0_CS1_DV 0x00000440 -+#endif -+ -+#define DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV 0x030C030C -+#define DDR2_ODT_CTRL_HIGH_CS0_CS1_CS2_CS3_DV 0x00000000 -+#define DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV 0x0000F40F -+#ifdef MV78XX0 -+#define DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV 0x00000004 -+#define DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV 0x00000044 -+#else -+#define DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV 0x00000404 -+#define DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV 0x00000444 -+#endif -+ -+/* DDR SDRAM Adderss/Control and Data Pads Calibration default values */ -+#define DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \ -+ (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) -+ -+#define DDR2_DATA_PAD_STRENGTH_TYPICAL_DV \ -+ (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) -+ -+/* DDR SDRAM Mode Register default value */ -+#define DDR2_MODE_REG_DV (SDRAM_BURST_LEN_4 | SDRAM_WR_3_CYC) -+/* DDR SDRAM Timing parameter default values */ -+#define SDRAM_TIMING_CTRL_LOW_REG_DEFAULT 0x33136552 -+#define SDRAM_TRFC_DEFAULT_VALUE 0x34 -+#define SDRAM_TRFC_DEFAULT SDRAM_TRFC_DEFAULT_VALUE -+#define SDRAM_TW2W_DEFALT (0x1 << SDRAM_TW2W_OFFS) -+ -+#define SDRAM_TIMING_CTRL_HIGH_REG_DEFAULT (SDRAM_TRFC_DEFAULT | SDRAM_TW2W_DEFALT) -+ -+#define SDRAM_FTDLL_REG_DEFAULT_LEFT 0x88C800 -+#define SDRAM_FTDLL_REG_DEFAULT_RIGHT 0x88C800 -+#define SDRAM_FTDLL_REG_DEFAULT_UP 0x88C800 -+ -+#ifdef __cplusplus -+} -+#endif /* __cplusplus */ -+ -+#endif /* __INCmvDramIfh */ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,423 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvDramIfRegsh -+#define __INCmvDramIfRegsh -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* DDR SDRAM Controller Address Decode Registers */ -+ /* SDRAM CSn Base Address Register (SCBAR) */ -+#define SDRAM_BASE_ADDR_REG(cpu,csNum) (0x1500 + ((csNum) * 8) + ((cpu) * 0x70)) -+#define SCBAR_BASE_OFFS 16 -+#define SCBAR_BASE_MASK (0xffff << SCBAR_BASE_OFFS) -+#define SCBAR_BASE_ALIGNMENT 0x10000 -+ -+/* SDRAM CSn Size Register (SCSR) */ -+#define SDRAM_SIZE_REG(cpu,csNum) (0x1504 + ((csNum) * 8) + ((cpu) * 0x70)) -+#define SCSR_SIZE_OFFS 24 -+#define SCSR_SIZE_MASK (0xff << SCSR_SIZE_OFFS) -+#define SCSR_SIZE_ALIGNMENT 0x1000000 -+#define SCSR_WIN_EN BIT0 -+ -+/* configuration register */ -+#define SDRAM_CONFIG_REG (DRAM_BASE + 0x1400) -+#define SDRAM_REFRESH_OFFS 0 -+#define SDRAM_REFRESH_MAX 0x3FFF -+#define SDRAM_REFRESH_MASK (SDRAM_REFRESH_MAX << SDRAM_REFRESH_OFFS) -+#define SDRAM_DWIDTH_OFFS 15 -+#define SDRAM_DWIDTH_MASK (1 << SDRAM_DWIDTH_OFFS) -+#define SDRAM_DWIDTH_32BIT (0 << SDRAM_DWIDTH_OFFS) -+#define SDRAM_DWIDTH_64BIT (1 << SDRAM_DWIDTH_OFFS) -+#define SDRAM_REGISTERED (1 << 17) -+#define SDRAM_ECC_OFFS 18 -+#define SDRAM_ECC_MASK (1 << SDRAM_ECC_OFFS) -+#define SDRAM_ECC_DIS (0 << SDRAM_ECC_OFFS) -+#define SDRAM_ECC_EN (1 << SDRAM_ECC_OFFS) -+#define SDRAM_IERR_OFFS 19 -+#define SDRAM_IERR_MASK (1 << SDRAM_IERR_OFFS) -+#define SDRAM_IERR_REPORTE (0 << SDRAM_IERR_OFFS) -+#define SDRAM_IERR_IGNORE (1 << SDRAM_IERR_OFFS) -+#define SDRAM_SRMODE_OFFS 24 -+#define SDRAM_SRMODE_MASK (1 << SDRAM_SRMODE_OFFS) -+#define SDRAM_SRMODE_POWER (0 << SDRAM_SRMODE_OFFS) -+#define SDRAM_SRMODE_DRAM (1 << SDRAM_SRMODE_OFFS) -+ -+/* dunit control low register */ -+#define SDRAM_DUNIT_CTRL_REG (DRAM_BASE + 0x1404) -+#define SDRAM_2T_OFFS 4 -+#define SDRAM_2T_MASK (1 << SDRAM_2T_OFFS) -+#define SDRAM_2T_MODE (1 << SDRAM_2T_OFFS) -+ -+#define SDRAM_SRCLK_OFFS 5 -+#define SDRAM_SRCLK_MASK (1 << SDRAM_SRCLK_OFFS) -+#define SDRAM_SRCLK_KEPT (0 << SDRAM_SRCLK_OFFS) -+#define SDRAM_SRCLK_GATED (1 << SDRAM_SRCLK_OFFS) -+#define SDRAM_CTRL_POS_OFFS 6 -+#define SDRAM_CTRL_POS_MASK (1 << SDRAM_CTRL_POS_OFFS) -+#define SDRAM_CTRL_POS_FALL (0 << SDRAM_CTRL_POS_OFFS) -+#define SDRAM_CTRL_POS_RISE (1 << SDRAM_CTRL_POS_OFFS) -+#define SDRAM_CLK1DRV_OFFS 12 -+#define SDRAM_CLK1DRV_MASK (1 << SDRAM_CLK1DRV_OFFS) -+#define SDRAM_CLK1DRV_HIGH_Z (0 << SDRAM_CLK1DRV_OFFS) -+#define SDRAM_CLK1DRV_NORMAL (1 << SDRAM_CLK1DRV_OFFS) -+#define SDRAM_CLK2DRV_OFFS 13 -+#define SDRAM_CLK2DRV_MASK (1 << SDRAM_CLK2DRV_OFFS) -+#define SDRAM_CLK2DRV_HIGH_Z (0 << SDRAM_CLK2DRV_OFFS) -+#define SDRAM_CLK2DRV_NORMAL (1 << SDRAM_CLK2DRV_OFFS) -+#define SDRAM_SB_OUT_DEL_OFFS 20 -+#define SDRAM_SB_OUT_DEL_MAX 0xf -+#define SDRAM_SB_OUT_MASK (SDRAM_SB_OUT_DEL_MAX<= MV_DRAM_MAX_CS )) -+ { -+ DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); -+ return MV_BAD_PARAM; -+ } -+ memset(pBankInfo, 0, sizeof(*pBankInfo)); -+ -+ if ( MV_OK != dimmSpdGet((MV_U32)(bankNum/2), &dimmInfo)) -+ { -+ DB(mvOsPrintf("Dram: ERR dimmSpdGet failed to get dimm info \n")); -+ return MV_FAIL; -+ } -+ if ((dimmInfo.numOfModuleBanks == 1) && ((bankNum % 2) == 1)) -+ { -+ DB(mvOsPrintf("Dram: ERR dimmSpdGet. Can't find DIMM bank 2 \n")); -+ return MV_FAIL; -+ } -+ /* convert Dimm info to Bank info */ -+ cpyDimm2BankInfo(&dimmInfo, pBankInfo); -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* cpyDimm2BankInfo - Convert a Dimm info struct into a bank info struct. -+* -+* DESCRIPTION: -+* Convert a Dimm info struct into a bank info struct. -+* -+* INPUT: -+* pDimmInfo - DIMM information structure. -+* -+* OUTPUT: -+* pBankInfo - DRAM bank information struct. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+static MV_VOID cpyDimm2BankInfo(MV_DIMM_INFO *pDimmInfo, -+ MV_DRAM_BANK_INFO *pBankInfo) -+{ -+ pBankInfo->memoryType = pDimmInfo->memoryType; -+ -+ /* DIMM dimensions */ -+ pBankInfo->numOfRowAddr = pDimmInfo->numOfRowAddr; -+ pBankInfo->numOfColAddr = pDimmInfo->numOfColAddr; -+ pBankInfo->dataWidth = pDimmInfo->dataWidth; -+ pBankInfo->errorCheckType = pDimmInfo->errorCheckType; -+ pBankInfo->sdramWidth = pDimmInfo->sdramWidth; -+ pBankInfo->errorCheckDataWidth = pDimmInfo->errorCheckDataWidth; -+ pBankInfo->numOfBanksOnEachDevice = pDimmInfo->numOfBanksOnEachDevice; -+ pBankInfo->suportedCasLatencies = pDimmInfo->suportedCasLatencies; -+ pBankInfo->refreshInterval = pDimmInfo->refreshInterval; -+ -+ /* DIMM timing parameters */ -+ pBankInfo->minCycleTimeAtMaxCasLatPs = pDimmInfo->minCycleTimeAtMaxCasLatPs; -+ pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps = -+ pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps; -+ pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps = -+ pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps; -+ -+ pBankInfo->minRowPrechargeTime = pDimmInfo->minRowPrechargeTime; -+ pBankInfo->minRowActiveToRowActive = pDimmInfo->minRowActiveToRowActive; -+ pBankInfo->minRasToCasDelay = pDimmInfo->minRasToCasDelay; -+ pBankInfo->minRasPulseWidth = pDimmInfo->minRasPulseWidth; -+ pBankInfo->minWriteRecoveryTime = pDimmInfo->minWriteRecoveryTime; -+ pBankInfo->minWriteToReadCmdDelay = pDimmInfo->minWriteToReadCmdDelay; -+ pBankInfo->minReadToPrechCmdDelay = pDimmInfo->minReadToPrechCmdDelay; -+ pBankInfo->minRefreshToActiveCmd = pDimmInfo->minRefreshToActiveCmd; -+ -+ /* Parameters calculated from the extracted DIMM information */ -+ pBankInfo->size = pDimmInfo->size/pDimmInfo->numOfModuleBanks; -+ pBankInfo->deviceDensity = pDimmInfo->deviceDensity; -+ pBankInfo->numberOfDevices = pDimmInfo->numberOfDevices / -+ pDimmInfo->numOfModuleBanks; -+ -+ /* DIMM attributes (MV_TRUE for yes) */ -+ -+ if ((pDimmInfo->memoryType == MEM_TYPE_SDRAM) || -+ (pDimmInfo->memoryType == MEM_TYPE_DDR1) ) -+ { -+ if (pDimmInfo->dimmAttributes & BIT1) -+ pBankInfo->registeredAddrAndControlInputs = MV_TRUE; -+ else -+ pBankInfo->registeredAddrAndControlInputs = MV_FALSE; -+ } -+ else /* pDimmInfo->memoryType == MEM_TYPE_DDR2 */ -+ { -+ if (pDimmInfo->dimmTypeInfo & (BIT0 | BIT4)) -+ pBankInfo->registeredAddrAndControlInputs = MV_TRUE; -+ else -+ pBankInfo->registeredAddrAndControlInputs = MV_FALSE; -+ } -+ -+ return; -+} -+/******************************************************************************* -+* dimmSpdCpy - Cpy SPD parameters from dimm 0 to dimm 1. -+* -+* DESCRIPTION: -+* Read the DIMM SPD parameters from dimm 0 into dimm 1 SPD. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+MV_STATUS dimmSpdCpy(MV_VOID) -+{ -+ MV_U32 i; -+ MV_U32 spdChecksum; -+ -+ MV_TWSI_SLAVE twsiSlave; -+ MV_U8 data[SPD_SIZE]; -+ -+ /* zero dimmInfo structure */ -+ memset(data, 0, SPD_SIZE); -+ -+ /* read the dimm eeprom */ -+ DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); -+ twsiSlave.slaveAddr.address = MV_BOARD_DIMM0_I2C_ADDR; -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ twsiSlave.offset = 0; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, &twsiSlave, data, SPD_SIZE) ) -+ { -+ DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 0\n")); -+ return MV_FAIL; -+ } -+ DB(puts("DRAM: Reading dimm info succeded.\n")); -+ -+ /* calculate SPD checksum */ -+ spdChecksum = 0; -+ -+ for(i = 0 ; i <= 62 ; i++) -+ { -+ spdChecksum += data[i]; -+ } -+ -+ if ((spdChecksum & 0xff) != data[63]) -+ { -+ DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", -+ (MV_U32)(spdChecksum & 0xff), data[63])); -+ } -+ else -+ { -+ DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); -+ } -+ -+ /* copy the SPD content 1:1 into the DIMM 1 SPD */ -+ twsiSlave.slaveAddr.address = MV_BOARD_DIMM1_I2C_ADDR; -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ twsiSlave.offset = 0; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ for(i = 0 ; i < SPD_SIZE ; i++) -+ { -+ twsiSlave.offset = i; -+ if( MV_OK != mvTwsiWrite (MV_BOARD_DIMM_I2C_CHANNEL, &twsiSlave, &data[i], 1) ) -+ { -+ mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 1 byte %d \n",i); -+ return MV_FAIL; -+ } -+ mvOsDelay(5); -+ } -+ -+ DB(puts("DRAM: Reading dimm info succeded.\n")); -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* dimmSpdGet - Get the SPD parameters. -+* -+* DESCRIPTION: -+* Read the DIMM SPD parameters into given struct parameter. -+* -+* INPUT: -+* dimmNum - DIMM number. See MV_BOARD_DIMM_NUM enumerator. -+* -+* OUTPUT: -+* pDimmInfo - DIMM information structure. -+* -+* RETURN: -+* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo) -+{ -+ MV_U32 i; -+ MV_U32 density = 1; -+ MV_U32 spdChecksum; -+ -+ MV_TWSI_SLAVE twsiSlave; -+ MV_U8 data[SPD_SIZE]; -+ -+ if((NULL == pDimmInfo)|| (dimmNum >= MAX_DIMM_NUM)) -+ { -+ DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); -+ return MV_BAD_PARAM; -+ } -+ -+ /* zero dimmInfo structure */ -+ memset(data, 0, SPD_SIZE); -+ -+ /* read the dimm eeprom */ -+ DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); -+ twsiSlave.slaveAddr.address = (dimmNum == 0) ? -+ MV_BOARD_DIMM0_I2C_ADDR : MV_BOARD_DIMM1_I2C_ADDR; -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ twsiSlave.offset = 0; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, &twsiSlave, data, SPD_SIZE) ) -+ { -+ DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum %d \n", dimmNum)); -+ return MV_FAIL; -+ } -+ DB(puts("DRAM: Reading dimm info succeded.\n")); -+ -+ /* calculate SPD checksum */ -+ spdChecksum = 0; -+ -+ for(i = 0 ; i <= 62 ; i++) -+ { -+ spdChecksum += data[i]; -+ } -+ -+ if ((spdChecksum & 0xff) != data[63]) -+ { -+ DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", -+ (MV_U32)(spdChecksum & 0xff), data[63])); -+ } -+ else -+ { -+ DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); -+ } -+ -+ /* copy the SPD content 1:1 into the dimmInfo structure*/ -+ for(i = 0 ; i < SPD_SIZE ; i++) -+ { -+ pDimmInfo->spdRawData[i] = data[i]; -+ DB(mvOsPrintf("SPD-EEPROM Byte %3d = %3x (%3d)\n",i, data[i], data[i])); -+ } -+ -+ DB(mvOsPrintf("DRAM SPD Information:\n")); -+ -+ /* Memory type (DDR / SDRAM) */ -+ switch (data[DIMM_MEM_TYPE]) -+ { -+ case (DIMM_MEM_TYPE_SDRAM): -+ pDimmInfo->memoryType = MEM_TYPE_SDRAM; -+ DB(mvOsPrintf("DRAM Memeory type SDRAM\n")); -+ break; -+ case (DIMM_MEM_TYPE_DDR1): -+ pDimmInfo->memoryType = MEM_TYPE_DDR1; -+ DB(mvOsPrintf("DRAM Memeory type DDR1\n")); -+ break; -+ case (DIMM_MEM_TYPE_DDR2): -+ pDimmInfo->memoryType = MEM_TYPE_DDR2; -+ DB(mvOsPrintf("DRAM Memeory type DDR2\n")); -+ break; -+ default: -+ mvOsPrintf("ERROR: Undefined memory type!\n"); -+ return MV_ERROR; -+ } -+ -+ -+ /* Number Of Row Addresses */ -+ pDimmInfo->numOfRowAddr = data[DIMM_ROW_NUM]; -+ DB(mvOsPrintf("DRAM numOfRowAddr[3] %d\n",pDimmInfo->numOfRowAddr)); -+ -+ /* Number Of Column Addresses */ -+ pDimmInfo->numOfColAddr = data[DIMM_COL_NUM]; -+ DB(mvOsPrintf("DRAM numOfColAddr[4] %d\n",pDimmInfo->numOfColAddr)); -+ -+ /* Number Of Module Banks */ -+ pDimmInfo->numOfModuleBanks = data[DIMM_MODULE_BANK_NUM]; -+ DB(mvOsPrintf("DRAM numOfModuleBanks[5] 0x%x\n", -+ pDimmInfo->numOfModuleBanks)); -+ -+ /* Number of module banks encoded differently for DDR2 */ -+ if (pDimmInfo->memoryType == MEM_TYPE_DDR2) -+ pDimmInfo->numOfModuleBanks = (pDimmInfo->numOfModuleBanks & 0x7)+1; -+ -+ /* Data Width */ -+ pDimmInfo->dataWidth = data[DIMM_DATA_WIDTH]; -+ DB(mvOsPrintf("DRAM dataWidth[6] 0x%x\n", pDimmInfo->dataWidth)); -+ -+ /* Minimum Cycle Time At Max CasLatancy */ -+ pDimmInfo->minCycleTimeAtMaxCasLatPs = cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS]); -+ -+ /* Error Check Type */ -+ pDimmInfo->errorCheckType = data[DIMM_ERR_CHECK_TYPE]; -+ DB(mvOsPrintf("DRAM errorCheckType[11] 0x%x\n", -+ pDimmInfo->errorCheckType)); -+ -+ /* Refresh Interval */ -+ pDimmInfo->refreshInterval = data[DIMM_REFRESH_INTERVAL]; -+ DB(mvOsPrintf("DRAM refreshInterval[12] 0x%x\n", -+ pDimmInfo->refreshInterval)); -+ -+ /* Sdram Width */ -+ pDimmInfo->sdramWidth = data[DIMM_SDRAM_WIDTH]; -+ DB(mvOsPrintf("DRAM sdramWidth[13] 0x%x\n",pDimmInfo->sdramWidth)); -+ -+ /* Error Check Data Width */ -+ pDimmInfo->errorCheckDataWidth = data[DIMM_ERR_CHECK_DATA_WIDTH]; -+ DB(mvOsPrintf("DRAM errorCheckDataWidth[14] 0x%x\n", -+ pDimmInfo->errorCheckDataWidth)); -+ -+ /* Burst Length Supported */ -+ /* SDRAM/DDR1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * -+ *********************************************************/ -+ /* DDR2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * -+ *********************************************************/ -+ -+ pDimmInfo->burstLengthSupported = data[DIMM_BURST_LEN_SUP]; -+ DB(mvOsPrintf("DRAM burstLengthSupported[16] 0x%x\n", -+ pDimmInfo->burstLengthSupported)); -+ -+ /* Number Of Banks On Each Device */ -+ pDimmInfo->numOfBanksOnEachDevice = data[DIMM_DEV_BANK_NUM]; -+ DB(mvOsPrintf("DRAM numOfBanksOnEachDevice[17] 0x%x\n", -+ pDimmInfo->numOfBanksOnEachDevice)); -+ -+ /* Suported Cas Latencies */ -+ -+ /* SDRAM: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * -+ ********************************************************/ -+ -+ /* DDR 1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * -+ *********************************************************/ -+ -+ /* DDR 2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * -+ *********************************************************/ -+ -+ pDimmInfo->suportedCasLatencies = data[DIMM_SUP_CAL]; -+ DB(mvOsPrintf("DRAM suportedCasLatencies[18] 0x%x\n", -+ pDimmInfo->suportedCasLatencies)); -+ -+ /* For DDR2 only, get the DIMM type information */ -+ if (pDimmInfo->memoryType == MEM_TYPE_DDR2) -+ { -+ pDimmInfo->dimmTypeInfo = data[DIMM_DDR2_TYPE_INFORMATION]; -+ DB(mvOsPrintf("DRAM dimmTypeInfo[20] (DDR2) 0x%x\n", -+ pDimmInfo->dimmTypeInfo)); -+ } -+ -+ /* SDRAM Modules Attributes */ -+ pDimmInfo->dimmAttributes = data[DIMM_BUF_ADDR_CONT_IN]; -+ DB(mvOsPrintf("DRAM dimmAttributes[21] 0x%x\n", -+ pDimmInfo->dimmAttributes)); -+ -+ /* Minimum Cycle Time At Max CasLatancy Minus 1*/ -+ pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps = -+ cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS1]); -+ -+ /* Minimum Cycle Time At Max CasLatancy Minus 2*/ -+ pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps = -+ cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS2]); -+ -+ pDimmInfo->minRowPrechargeTime = data[DIMM_MIN_ROW_PRECHARGE_TIME]; -+ DB(mvOsPrintf("DRAM minRowPrechargeTime[27] 0x%x\n", -+ pDimmInfo->minRowPrechargeTime)); -+ pDimmInfo->minRowActiveToRowActive = data[DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE]; -+ DB(mvOsPrintf("DRAM minRowActiveToRowActive[28] 0x%x\n", -+ pDimmInfo->minRowActiveToRowActive)); -+ pDimmInfo->minRasToCasDelay = data[DIMM_MIN_RAS_TO_CAS_DELAY]; -+ DB(mvOsPrintf("DRAM minRasToCasDelay[29] 0x%x\n", -+ pDimmInfo->minRasToCasDelay)); -+ pDimmInfo->minRasPulseWidth = data[DIMM_MIN_RAS_PULSE_WIDTH]; -+ DB(mvOsPrintf("DRAM minRasPulseWidth[30] 0x%x\n", -+ pDimmInfo->minRasPulseWidth)); -+ -+ /* DIMM Bank Density */ -+ pDimmInfo->dimmBankDensity = data[DIMM_BANK_DENSITY]; -+ DB(mvOsPrintf("DRAM dimmBankDensity[31] 0x%x\n", -+ pDimmInfo->dimmBankDensity)); -+ -+ /* Only DDR2 includes Write Recovery Time field. Other SDRAM ignore */ -+ pDimmInfo->minWriteRecoveryTime = data[DIMM_MIN_WRITE_RECOVERY_TIME]; -+ DB(mvOsPrintf("DRAM minWriteRecoveryTime[36] 0x%x\n", -+ pDimmInfo->minWriteRecoveryTime)); -+ -+ /* Only DDR2 includes Internal Write To Read Command Delay field. */ -+ pDimmInfo->minWriteToReadCmdDelay = data[DIMM_MIN_WRITE_TO_READ_CMD_DELAY]; -+ DB(mvOsPrintf("DRAM minWriteToReadCmdDelay[37] 0x%x\n", -+ pDimmInfo->minWriteToReadCmdDelay)); -+ -+ /* Only DDR2 includes Internal Read To Precharge Command Delay field. */ -+ pDimmInfo->minReadToPrechCmdDelay = data[DIMM_MIN_READ_TO_PRECH_CMD_DELAY]; -+ DB(mvOsPrintf("DRAM minReadToPrechCmdDelay[38] 0x%x\n", -+ pDimmInfo->minReadToPrechCmdDelay)); -+ -+ /* Only DDR2 includes Minimum Refresh to Activate/Refresh Command field */ -+ pDimmInfo->minRefreshToActiveCmd = data[DIMM_MIN_REFRESH_TO_ACTIVATE_CMD]; -+ DB(mvOsPrintf("DRAM minRefreshToActiveCmd[42] 0x%x\n", -+ pDimmInfo->minRefreshToActiveCmd)); -+ -+ /* calculating the sdram density. Representing device density from */ -+ /* bit 20 to allow representation of 4GB and above. */ -+ /* For example, if density is 512Mbit 0x20000000, will be represent in */ -+ /* deviceDensity by 0x20000000 >> 16 --> 0x00000200. Another example */ -+ /* is density 8GB 0x200000000 >> 16 --> 0x00002000. */ -+ density = (1 << ((pDimmInfo->numOfRowAddr + pDimmInfo->numOfColAddr) - 20)); -+ pDimmInfo->deviceDensity = density * -+ pDimmInfo->numOfBanksOnEachDevice * -+ pDimmInfo->sdramWidth; -+ DB(mvOsPrintf("DRAM deviceDensity %d\n",pDimmInfo->deviceDensity)); -+ -+ /* Number of devices includeing Error correction */ -+ pDimmInfo->numberOfDevices = (pDimmInfo->dataWidth/pDimmInfo->sdramWidth) * -+ pDimmInfo->numOfModuleBanks; -+ DB(mvOsPrintf("DRAM numberOfDevices %d\n", -+ pDimmInfo->numberOfDevices)); -+ -+ pDimmInfo->size = 0; -+ -+ /* Note that pDimmInfo->size is in MB units */ -+ if (pDimmInfo->memoryType == MEM_TYPE_SDRAM) -+ { -+ if (pDimmInfo->dimmBankDensity & BIT0) -+ pDimmInfo->size += 1024; /* Equal to 1GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT1) -+ pDimmInfo->size += 8; /* Equal to 8MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT2) -+ pDimmInfo->size += 16; /* Equal to 16MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT3) -+ pDimmInfo->size += 32; /* Equal to 32MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT4) -+ pDimmInfo->size += 64; /* Equal to 64MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT5) -+ pDimmInfo->size += 128; /* Equal to 128MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT6) -+ pDimmInfo->size += 256; /* Equal to 256MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT7) -+ pDimmInfo->size += 512; /* Equal to 512MB */ -+ } -+ else if (pDimmInfo->memoryType == MEM_TYPE_DDR1) -+ { -+ if (pDimmInfo->dimmBankDensity & BIT0) -+ pDimmInfo->size += 1024; /* Equal to 1GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT1) -+ pDimmInfo->size += 2048; /* Equal to 2GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT2) -+ pDimmInfo->size += 16; /* Equal to 16MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT3) -+ pDimmInfo->size += 32; /* Equal to 32MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT4) -+ pDimmInfo->size += 64; /* Equal to 64MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT5) -+ pDimmInfo->size += 128; /* Equal to 128MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT6) -+ pDimmInfo->size += 256; /* Equal to 256MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT7) -+ pDimmInfo->size += 512; /* Equal to 512MB */ -+ } -+ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ -+ { -+ if (pDimmInfo->dimmBankDensity & BIT0) -+ pDimmInfo->size += 1024; /* Equal to 1GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT1) -+ pDimmInfo->size += 2048; /* Equal to 2GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT2) -+ pDimmInfo->size += 4096; /* Equal to 4GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT3) -+ pDimmInfo->size += 8192; /* Equal to 8GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT4) -+ pDimmInfo->size += 16384; /* Equal to 16GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT5) -+ pDimmInfo->size += 128; /* Equal to 128MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT6) -+ pDimmInfo->size += 256; /* Equal to 256MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT7) -+ pDimmInfo->size += 512; /* Equal to 512MB */ -+ } -+ -+ pDimmInfo->size *= pDimmInfo->numOfModuleBanks; -+ -+ DB(mvOsPrintf("Dram: dimm size %dMB \n",pDimmInfo->size)); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* dimmSpdPrint - Print the SPD parameters. -+* -+* DESCRIPTION: -+* Print the Dimm SPD parameters. -+* -+* INPUT: -+* pDimmInfo - DIMM information structure. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID dimmSpdPrint(MV_U32 dimmNum) -+{ -+ MV_DIMM_INFO dimmInfo; -+ MV_U32 i, temp = 0; -+ MV_U32 k, maskLeftOfPoint = 0, maskRightOfPoint = 0; -+ MV_U32 rightOfPoint = 0,leftOfPoint = 0, div, time_tmp, shift; -+ MV_U32 busClkPs; -+ MV_U8 trp_clocks=0, trcd_clocks, tras_clocks, trrd_clocks, -+ temp_buf[40], *spdRawData; -+ -+ busClkPs = 1000000000 / (mvBoardSysClkGet() / 100); /* in 10 ps units */ -+ -+ spdRawData = dimmInfo.spdRawData; -+ -+ if(MV_OK != dimmSpdGet(dimmNum, &dimmInfo)) -+ { -+ mvOsOutput("ERROR: Could not read SPD information!\n"); -+ return; -+ } -+ -+ /* find Manufactura of Dimm Module */ -+ mvOsOutput("\nManufacturer's JEDEC ID Code: "); -+ for(i = 0 ; i < DIMM_MODULE_MANU_SIZE ; i++) -+ { -+ mvOsOutput("%x",spdRawData[DIMM_MODULE_MANU_OFFS + i]); -+ } -+ mvOsOutput("\n"); -+ -+ /* Manufacturer's Specific Data */ -+ for(i = 0 ; i < DIMM_MODULE_ID_SIZE ; i++) -+ { -+ temp_buf[i] = spdRawData[DIMM_MODULE_ID_OFFS + i]; -+ } -+ mvOsOutput("Manufacturer's Specific Data: %s\n", temp_buf); -+ -+ /* Module Part Number */ -+ for(i = 0 ; i < DIMM_MODULE_VEN_SIZE ; i++) -+ { -+ temp_buf[i] = spdRawData[DIMM_MODULE_VEN_OFFS + i]; -+ } -+ mvOsOutput("Module Part Number: %s\n", temp_buf); -+ -+ /* Module Serial Number */ -+ for(i = 0; i < sizeof(MV_U32); i++) -+ { -+ temp |= spdRawData[95+i] << 8*i; -+ } -+ mvOsOutput("DIMM Serial No. %ld (%lx)\n", (long)temp, -+ (long)temp); -+ -+ /* find Manufac-Data of Dimm Module */ -+ mvOsOutput("Manufactoring Date: Year 20%d%d/ ww %d%d\n", -+ ((spdRawData[93] & 0xf0) >> 4), (spdRawData[93] & 0xf), -+ ((spdRawData[94] & 0xf0) >> 4), (spdRawData[94] & 0xf)); -+ /* find modul_revision of Dimm Module */ -+ mvOsOutput("Module Revision: %d.%d\n", -+ spdRawData[62]/10, spdRawData[62]%10); -+ -+ /* find manufac_place of Dimm Module */ -+ mvOsOutput("manufac_place: %d\n", spdRawData[72]); -+ -+ /* go over the first 35 I2C data bytes */ -+ for(i = 2 ; i <= 35 ; i++) -+ switch(i) -+ { -+ case 2: /* Memory type (DDR1/2 / SDRAM) */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ mvOsOutput("Dram Type is: SDRAM\n"); -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ mvOsOutput("Dram Type is: SDRAM DDR1\n"); -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) -+ mvOsOutput("Dram Type is: SDRAM DDR2\n"); -+ else -+ mvOsOutput("Dram Type unknown\n"); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 3: /* Number Of Row Addresses */ -+ mvOsOutput("Module Number of row addresses: %d\n", -+ dimmInfo.numOfRowAddr); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 4: /* Number Of Column Addresses */ -+ mvOsOutput("Module Number of col addresses: %d\n", -+ dimmInfo.numOfColAddr); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 5: /* Number Of Module Banks */ -+ mvOsOutput("Number of Banks on Mod.: %d\n", -+ dimmInfo.numOfModuleBanks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 6: /* Data Width */ -+ mvOsOutput("Module Data Width: %d bit\n", -+ dimmInfo.dataWidth); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 8: /* Voltage Interface */ -+ switch(spdRawData[i]) -+ { -+ case 0x0: -+ mvOsOutput("Module is TTL_5V_TOLERANT\n"); -+ break; -+ case 0x1: -+ mvOsOutput("Module is LVTTL\n"); -+ break; -+ case 0x2: -+ mvOsOutput("Module is HSTL_1_5V\n"); -+ break; -+ case 0x3: -+ mvOsOutput("Module is SSTL_3_3V\n"); -+ break; -+ case 0x4: -+ mvOsOutput("Module is SSTL_2_5V\n"); -+ break; -+ case 0x5: -+ if (dimmInfo.memoryType != MEM_TYPE_SDRAM) -+ { -+ mvOsOutput("Module is SSTL_1_8V\n"); -+ break; -+ } -+ default: -+ mvOsOutput("Module is VOLTAGE_UNKNOWN\n"); -+ break; -+ } -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 9: /* Minimum Cycle Time At Max CasLatancy */ -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ rightOfPoint = (spdRawData[i] & 0x0f) * 10; -+ -+ /* DDR2 addition of right of point */ -+ if ((spdRawData[i] & 0x0f) == 0xA) -+ { -+ rightOfPoint = 25; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xB) -+ { -+ rightOfPoint = 33; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xC) -+ { -+ rightOfPoint = 66; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xD) -+ { -+ rightOfPoint = 75; -+ } -+ mvOsOutput("Minimum Cycle Time At Max CL: %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 10: /* Clock To Data Out */ -+ div = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 10:100; -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / div; -+ rightOfPoint = time_tmp % div; -+ mvOsOutput("Clock To Data Out: %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 11: /* Error Check Type */ -+ mvOsOutput("Error Check Type (0=NONE): %d\n", -+ dimmInfo.errorCheckType); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 12: /* Refresh Interval */ -+ mvOsOutput("Refresh Rate: %x\n", -+ dimmInfo.refreshInterval); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 13: /* Sdram Width */ -+ mvOsOutput("Sdram Width: %d bits\n", -+ dimmInfo.sdramWidth); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 14: /* Error Check Data Width */ -+ mvOsOutput("Error Check Data Width: %d bits\n", -+ dimmInfo.errorCheckDataWidth); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 15: /* Minimum Clock Delay is unsupported */ -+ if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || -+ (dimmInfo.memoryType == MEM_TYPE_DDR1)) -+ { -+ mvOsOutput("Minimum Clk Delay back to back: %d\n", -+ spdRawData[i]); -+ } -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 16: /* Burst Length Supported */ -+ /* SDRAM/DDR1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * -+ *********************************************************/ -+ /* DDR2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * -+ *********************************************************/ -+ mvOsOutput("Burst Length Supported: "); -+ if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || -+ (dimmInfo.memoryType == MEM_TYPE_DDR1)) -+ { -+ if (dimmInfo.burstLengthSupported & BIT0) -+ mvOsOutput("1, "); -+ if (dimmInfo.burstLengthSupported & BIT1) -+ mvOsOutput("2, "); -+ } -+ if (dimmInfo.burstLengthSupported & BIT2) -+ mvOsOutput("4, "); -+ if (dimmInfo.burstLengthSupported & BIT3) -+ mvOsOutput("8, "); -+ -+ mvOsOutput(" Bit \n"); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 17: /* Number Of Banks On Each Device */ -+ mvOsOutput("Number Of Banks On Each Chip: %d\n", -+ dimmInfo.numOfBanksOnEachDevice); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 18: /* Suported Cas Latencies */ -+ -+ /* SDRAM: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * -+ ********************************************************/ -+ -+ /* DDR 1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * -+ *********************************************************/ -+ -+ /* DDR 2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * -+ *********************************************************/ -+ -+ mvOsOutput("Suported Cas Latencies: (CL) "); -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ for (k = 0; k <=7; k++) -+ { -+ if (dimmInfo.suportedCasLatencies & (1 << k)) -+ mvOsOutput("%d, ", k+1); -+ } -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ { -+ if (dimmInfo.suportedCasLatencies & BIT0) -+ mvOsOutput("1, "); -+ if (dimmInfo.suportedCasLatencies & BIT1) -+ mvOsOutput("1.5, "); -+ if (dimmInfo.suportedCasLatencies & BIT2) -+ mvOsOutput("2, "); -+ if (dimmInfo.suportedCasLatencies & BIT3) -+ mvOsOutput("2.5, "); -+ if (dimmInfo.suportedCasLatencies & BIT4) -+ mvOsOutput("3, "); -+ if (dimmInfo.suportedCasLatencies & BIT5) -+ mvOsOutput("3.5, "); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) -+ { -+ if (dimmInfo.suportedCasLatencies & BIT2) -+ mvOsOutput("2, "); -+ if (dimmInfo.suportedCasLatencies & BIT3) -+ mvOsOutput("3, "); -+ if (dimmInfo.suportedCasLatencies & BIT4) -+ mvOsOutput("4, "); -+ if (dimmInfo.suportedCasLatencies & BIT5) -+ mvOsOutput("5, "); -+ } -+ else -+ mvOsOutput("?.?, "); -+ mvOsOutput("\n"); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 20: /* DDR2 DIMM type info */ -+ if (dimmInfo.memoryType == MEM_TYPE_DDR2) -+ { -+ if (dimmInfo.dimmTypeInfo & (BIT0 | BIT4)) -+ mvOsOutput("Registered DIMM (RDIMM)\n"); -+ else if (dimmInfo.dimmTypeInfo & (BIT1 | BIT5)) -+ mvOsOutput("Unbuffered DIMM (UDIMM)\n"); -+ else -+ mvOsOutput("Unknown DIMM type.\n"); -+ } -+ -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 21: /* SDRAM Modules Attributes */ -+ mvOsOutput("\nModule Attributes (SPD Byte 21): \n"); -+ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ if (dimmInfo.dimmAttributes & BIT0) -+ mvOsOutput(" Buffered Addr/Control Input: Yes\n"); -+ else -+ mvOsOutput(" Buffered Addr/Control Input: No\n"); -+ -+ if (dimmInfo.dimmAttributes & BIT1) -+ mvOsOutput(" Registered Addr/Control Input: Yes\n"); -+ else -+ mvOsOutput(" Registered Addr/Control Input: No\n"); -+ -+ if (dimmInfo.dimmAttributes & BIT2) -+ mvOsOutput(" On-Card PLL (clock): Yes \n"); -+ else -+ mvOsOutput(" On-Card PLL (clock): No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT3) -+ mvOsOutput(" Bufferd DQMB Input: Yes \n"); -+ else -+ mvOsOutput(" Bufferd DQMB Inputs: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT4) -+ mvOsOutput(" Registered DQMB Inputs: Yes \n"); -+ else -+ mvOsOutput(" Registered DQMB Inputs: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT5) -+ mvOsOutput(" Differential Clock Input: Yes \n"); -+ else -+ mvOsOutput(" Differential Clock Input: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT6) -+ mvOsOutput(" redundant Row Addressing: Yes \n"); -+ else -+ mvOsOutput(" redundant Row Addressing: No \n"); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ { -+ if (dimmInfo.dimmAttributes & BIT0) -+ mvOsOutput(" Buffered Addr/Control Input: Yes\n"); -+ else -+ mvOsOutput(" Buffered Addr/Control Input: No\n"); -+ -+ if (dimmInfo.dimmAttributes & BIT1) -+ mvOsOutput(" Registered Addr/Control Input: Yes\n"); -+ else -+ mvOsOutput(" Registered Addr/Control Input: No\n"); -+ -+ if (dimmInfo.dimmAttributes & BIT2) -+ mvOsOutput(" On-Card PLL (clock): Yes \n"); -+ else -+ mvOsOutput(" On-Card PLL (clock): No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT3) -+ mvOsOutput(" FET Switch On-Card Enabled: Yes \n"); -+ else -+ mvOsOutput(" FET Switch On-Card Enabled: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT4) -+ mvOsOutput(" FET Switch External Enabled: Yes \n"); -+ else -+ mvOsOutput(" FET Switch External Enabled: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT5) -+ mvOsOutput(" Differential Clock Input: Yes \n"); -+ else -+ mvOsOutput(" Differential Clock Input: No \n"); -+ } -+ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ -+ { -+ mvOsOutput(" Number of Active Registers on the DIMM: %d\n", -+ (dimmInfo.dimmAttributes & 0x3) + 1); -+ -+ mvOsOutput(" Number of PLLs on the DIMM: %d\n", -+ ((dimmInfo.dimmAttributes) >> 2) & 0x3); -+ -+ if (dimmInfo.dimmAttributes & BIT4) -+ mvOsOutput(" FET Switch External Enabled: Yes \n"); -+ else -+ mvOsOutput(" FET Switch External Enabled: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT6) -+ mvOsOutput(" Analysis probe installed: Yes \n"); -+ else -+ mvOsOutput(" Analysis probe installed: No \n"); -+ } -+ -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 22: /* Suported AutoPreCharge */ -+ mvOsOutput("\nModul Attributes (SPD Byte 22): \n"); -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ if ( spdRawData[i] & BIT0 ) -+ mvOsOutput(" Early Ras Precharge: Yes \n"); -+ else -+ mvOsOutput(" Early Ras Precharge: No \n"); -+ -+ if ( spdRawData[i] & BIT1 ) -+ mvOsOutput(" AutoPreCharge: Yes \n"); -+ else -+ mvOsOutput(" AutoPreCharge: No \n"); -+ -+ if ( spdRawData[i] & BIT2 ) -+ mvOsOutput(" Precharge All: Yes \n"); -+ else -+ mvOsOutput(" Precharge All: No \n"); -+ -+ if ( spdRawData[i] & BIT3 ) -+ mvOsOutput(" Write 1/ReadBurst: Yes \n"); -+ else -+ mvOsOutput(" Write 1/ReadBurst: No \n"); -+ -+ if ( spdRawData[i] & BIT4 ) -+ mvOsOutput(" lower VCC tolerance: 5%%\n"); -+ else -+ mvOsOutput(" lower VCC tolerance: 10%%\n"); -+ -+ if ( spdRawData[i] & BIT5 ) -+ mvOsOutput(" upper VCC tolerance: 5%%\n"); -+ else -+ mvOsOutput(" upper VCC tolerance: 10%%\n"); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ { -+ if ( spdRawData[i] & BIT0 ) -+ mvOsOutput(" Supports Weak Driver: Yes \n"); -+ else -+ mvOsOutput(" Supports Weak Driver: No \n"); -+ -+ if ( !(spdRawData[i] & BIT4) ) -+ mvOsOutput(" lower VCC tolerance: 0.2V\n"); -+ -+ if ( !(spdRawData[i] & BIT5) ) -+ mvOsOutput(" upper VCC tolerance: 0.2V\n"); -+ -+ if ( spdRawData[i] & BIT6 ) -+ mvOsOutput(" Concurrent Auto Preharge: Yes \n"); -+ else -+ mvOsOutput(" Concurrent Auto Preharge: No \n"); -+ -+ if ( spdRawData[i] & BIT7 ) -+ mvOsOutput(" Supports Fast AP: Yes \n"); -+ else -+ mvOsOutput(" Supports Fast AP: No \n"); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) -+ { -+ if ( spdRawData[i] & BIT0 ) -+ mvOsOutput(" Supports Weak Driver: Yes \n"); -+ else -+ mvOsOutput(" Supports Weak Driver: No \n"); -+ } -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 23: -+ /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */ -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ rightOfPoint = (spdRawData[i] & 0x0f) * 10; -+ -+ /* DDR2 addition of right of point */ -+ if ((spdRawData[i] & 0x0f) == 0xA) -+ { -+ rightOfPoint = 25; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xB) -+ { -+ rightOfPoint = 33; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xC) -+ { -+ rightOfPoint = 66; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xD) -+ { -+ rightOfPoint = 75; -+ } -+ -+ mvOsOutput("Minimum Cycle Time At 2nd highest CasLatancy" -+ "(0 = Not supported): %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint ); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 24: /* Clock To Data Out 2nd highest Cas Latency Value*/ -+ div = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? 10:100; -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / div; -+ rightOfPoint = time_tmp % div; -+ mvOsOutput("Clock To Data Out (2nd CL value): %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 25: -+ /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ leftOfPoint = (spdRawData[i] & 0xfc) >> 2; -+ rightOfPoint = (spdRawData[i] & 0x3) * 25; -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ rightOfPoint = (spdRawData[i] & 0x0f) * 10; -+ -+ /* DDR2 addition of right of point */ -+ if ((spdRawData[i] & 0x0f) == 0xA) -+ { -+ rightOfPoint = 25; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xB) -+ { -+ rightOfPoint = 33; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xC) -+ { -+ rightOfPoint = 66; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xD) -+ { -+ rightOfPoint = 75; -+ } -+ } -+ mvOsOutput("Minimum Cycle Time At 3rd highest CasLatancy" -+ "(0 = Not supported): %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint ); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 26: /* Clock To Data Out 3rd highest Cas Latency Value*/ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ leftOfPoint = (spdRawData[i] & 0xfc) >> 2; -+ rightOfPoint = (spdRawData[i] & 0x3) * 25; -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = 0; -+ rightOfPoint = time_tmp; -+ } -+ mvOsOutput("Clock To Data Out (3rd CL value): %d.%2d[ns]\n", -+ leftOfPoint, rightOfPoint ); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 27: /* Minimum Row Precharge Time */ -+ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; -+ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0xff : 0xfc; -+ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0x00 : 0x03; -+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); -+ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; -+ temp = ((leftOfPoint*100) + rightOfPoint);/* in 10ps Intervals*/ -+ trp_clocks = (temp + (busClkPs-1)) / busClkPs; -+ mvOsOutput("Minimum Row Precharge Time [ns]: %d.%d = " -+ "in Clk cycles %d\n", -+ leftOfPoint, rightOfPoint, trp_clocks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 28: /* Minimum Row Active to Row Active Time */ -+ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; -+ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0xff : 0xfc; -+ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0x00 : 0x03; -+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); -+ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; -+ temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ -+ trrd_clocks = (temp + (busClkPs-1)) / busClkPs; -+ mvOsOutput("Minimum Row Active -To- Row Active Delay [ns]: " -+ "%d.%d = in Clk cycles %d\n", -+ leftOfPoint, rightOfPoint, trp_clocks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 29: /* Minimum Ras-To-Cas Delay */ -+ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; -+ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0xff : 0xfc; -+ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0x00 : 0x03; -+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); -+ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; -+ temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ -+ trcd_clocks = (temp + (busClkPs-1) )/ busClkPs; -+ mvOsOutput("Minimum Ras-To-Cas Delay [ns]: %d.%d = " -+ "in Clk cycles %d\n", -+ leftOfPoint, rightOfPoint, trp_clocks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 30: /* Minimum Ras Pulse Width */ -+ tras_clocks = (cas2ps(spdRawData[i])+(busClkPs-1)) / busClkPs; -+ mvOsOutput("Minimum Ras Pulse Width [ns]: %d = " -+ "in Clk cycles %d\n", spdRawData[i], tras_clocks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 31: /* Module Bank Density */ -+ mvOsOutput("Module Bank Density (more than 1= Multisize-Module):"); -+ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ if (dimmInfo.dimmBankDensity & BIT0) -+ mvOsOutput("1GB, "); -+ if (dimmInfo.dimmBankDensity & BIT1) -+ mvOsOutput("8MB, "); -+ if (dimmInfo.dimmBankDensity & BIT2) -+ mvOsOutput("16MB, "); -+ if (dimmInfo.dimmBankDensity & BIT3) -+ mvOsOutput("32MB, "); -+ if (dimmInfo.dimmBankDensity & BIT4) -+ mvOsOutput("64MB, "); -+ if (dimmInfo.dimmBankDensity & BIT5) -+ mvOsOutput("128MB, "); -+ if (dimmInfo.dimmBankDensity & BIT6) -+ mvOsOutput("256MB, "); -+ if (dimmInfo.dimmBankDensity & BIT7) -+ mvOsOutput("512MB, "); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ { -+ if (dimmInfo.dimmBankDensity & BIT0) -+ mvOsOutput("1GB, "); -+ if (dimmInfo.dimmBankDensity & BIT1) -+ mvOsOutput("2GB, "); -+ if (dimmInfo.dimmBankDensity & BIT2) -+ mvOsOutput("16MB, "); -+ if (dimmInfo.dimmBankDensity & BIT3) -+ mvOsOutput("32MB, "); -+ if (dimmInfo.dimmBankDensity & BIT4) -+ mvOsOutput("64MB, "); -+ if (dimmInfo.dimmBankDensity & BIT5) -+ mvOsOutput("128MB, "); -+ if (dimmInfo.dimmBankDensity & BIT6) -+ mvOsOutput("256MB, "); -+ if (dimmInfo.dimmBankDensity & BIT7) -+ mvOsOutput("512MB, "); -+ } -+ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ -+ { -+ if (dimmInfo.dimmBankDensity & BIT0) -+ mvOsOutput("1GB, "); -+ if (dimmInfo.dimmBankDensity & BIT1) -+ mvOsOutput("2GB, "); -+ if (dimmInfo.dimmBankDensity & BIT2) -+ mvOsOutput("4GB, "); -+ if (dimmInfo.dimmBankDensity & BIT3) -+ mvOsOutput("8GB, "); -+ if (dimmInfo.dimmBankDensity & BIT4) -+ mvOsOutput("16GB, "); -+ if (dimmInfo.dimmBankDensity & BIT5) -+ mvOsOutput("128MB, "); -+ if (dimmInfo.dimmBankDensity & BIT6) -+ mvOsOutput("256MB, "); -+ if (dimmInfo.dimmBankDensity & BIT7) -+ mvOsOutput("512MB, "); -+ } -+ mvOsOutput("\n"); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 32: /* Address And Command Setup Time (measured in ns/1000) */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ rightOfPoint = (spdRawData[i] & 0x0f); -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ if(leftOfPoint > 7) -+ { -+ leftOfPoint *= -1; -+ } -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / 100; -+ rightOfPoint = time_tmp % 100; -+ } -+ mvOsOutput("Address And Command Setup Time [ns]: %d.%d\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 33: /* Address And Command Hold Time */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ rightOfPoint = (spdRawData[i] & 0x0f); -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ if(leftOfPoint > 7) -+ { -+ leftOfPoint *= -1; -+ } -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / 100; -+ rightOfPoint = time_tmp % 100; -+ } -+ mvOsOutput("Address And Command Hold Time [ns]: %d.%d\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 34: /* Data Input Setup Time */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ rightOfPoint = (spdRawData[i] & 0x0f); -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ if(leftOfPoint > 7) -+ { -+ leftOfPoint *= -1; -+ } -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / 100; -+ rightOfPoint = time_tmp % 100; -+ } -+ mvOsOutput("Data Input Setup Time [ns]: %d.%d\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 35: /* Data Input Hold Time */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ rightOfPoint = (spdRawData[i] & 0x0f); -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ if(leftOfPoint > 7) -+ { -+ leftOfPoint *= -1; -+ } -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / 100; -+ rightOfPoint = time_tmp % 100; -+ } -+ mvOsOutput("Data Input Hold Time [ns]: %d.%d\n\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 36: /* Relevant for DDR2 only: Write Recovery Time */ -+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> 2); -+ rightOfPoint = (spdRawData[i] & maskRightOfPoint) * 25; -+ mvOsOutput("Write Recovery Time [ns]: %d.%d\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ } -+ -+} -+ -+ -+/* -+ * translate ns.ns/10 coding of SPD timing values -+ * into ps unit values -+ */ -+/******************************************************************************* -+* cas2ps - Translate x.y ns parameter to pico-seconds values -+* -+* DESCRIPTION: -+* This function translates x.y nano seconds to its value in pico seconds. -+* For example 3.75ns will return 3750. -+* -+* INPUT: -+* spd_byte - DIMM SPD byte. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* value in pico seconds. -+* -+*******************************************************************************/ -+static MV_U32 cas2ps(MV_U8 spd_byte) -+{ -+ MV_U32 ns, ns10; -+ -+ /* isolate upper nibble */ -+ ns = (spd_byte >> 4) & 0x0F; -+ /* isolate lower nibble */ -+ ns10 = (spd_byte & 0x0F); -+ -+ if( ns10 < 10 ) { -+ ns10 *= 10; -+ } -+ else if( ns10 == 10 ) -+ ns10 = 25; -+ else if( ns10 == 11 ) -+ ns10 = 33; -+ else if( ns10 == 12 ) -+ ns10 = 66; -+ else if( ns10 == 13 ) -+ ns10 = 75; -+ else -+ { -+ mvOsOutput("cas2ps Err. unsupported cycle time.\n"); -+ } -+ -+ return (ns*1000 + ns10*10); -+} -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,192 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvDram -+#define __INCmvDram -+ -+#include "ddr2/mvDramIf.h" -+#include "twsi/mvTwsi.h" -+ -+#define MAX_DIMM_NUM 2 -+#define SPD_SIZE 128 -+ -+/* Dimm spd offsets */ -+#define DIMM_MEM_TYPE 2 -+#define DIMM_ROW_NUM 3 -+#define DIMM_COL_NUM 4 -+#define DIMM_MODULE_BANK_NUM 5 -+#define DIMM_DATA_WIDTH 6 -+#define DIMM_VOLT_IF 8 -+#define DIMM_MIN_CC_AT_MAX_CAS 9 -+#define DIMM_ERR_CHECK_TYPE 11 -+#define DIMM_REFRESH_INTERVAL 12 -+#define DIMM_SDRAM_WIDTH 13 -+#define DIMM_ERR_CHECK_DATA_WIDTH 14 -+#define DIMM_MIN_CLK_DEL 15 -+#define DIMM_BURST_LEN_SUP 16 -+#define DIMM_DEV_BANK_NUM 17 -+#define DIMM_SUP_CAL 18 -+#define DIMM_DDR2_TYPE_INFORMATION 20 /* DDR2 only */ -+#define DIMM_BUF_ADDR_CONT_IN 21 -+#define DIMM_MIN_CC_AT_MAX_CAS_MINUS1 23 -+#define DIMM_MIN_CC_AT_MAX_CAS_MINUS2 25 -+#define DIMM_MIN_ROW_PRECHARGE_TIME 27 -+#define DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE 28 -+#define DIMM_MIN_RAS_TO_CAS_DELAY 29 -+#define DIMM_MIN_RAS_PULSE_WIDTH 30 -+#define DIMM_BANK_DENSITY 31 -+#define DIMM_MIN_WRITE_RECOVERY_TIME 36 -+#define DIMM_MIN_WRITE_TO_READ_CMD_DELAY 37 -+#define DIMM_MIN_READ_TO_PRECH_CMD_DELAY 38 -+#define DIMM_MIN_REFRESH_TO_ACTIVATE_CMD 42 -+#define DIMM_SPD_VERSION 62 -+ -+/* Dimm Memory Type values */ -+#define DIMM_MEM_TYPE_SDRAM 0x4 -+#define DIMM_MEM_TYPE_DDR1 0x7 -+#define DIMM_MEM_TYPE_DDR2 0x8 -+ -+#define DIMM_MODULE_MANU_OFFS 64 -+#define DIMM_MODULE_MANU_SIZE 8 -+#define DIMM_MODULE_VEN_OFFS 73 -+#define DIMM_MODULE_VEN_SIZE 25 -+#define DIMM_MODULE_ID_OFFS 99 -+#define DIMM_MODULE_ID_SIZE 18 -+ -+/* enumeration for voltage levels. */ -+typedef enum _mvDimmVoltageIf -+{ -+ TTL_5V_TOLERANT, -+ LVTTL, -+ HSTL_1_5V, -+ SSTL_3_3V, -+ SSTL_2_5V, -+ VOLTAGE_UNKNOWN, -+} MV_DIMM_VOLTAGE_IF; -+ -+ -+/* enumaration for SDRAM CAS Latencies. */ -+typedef enum _mvDimmSdramCas -+{ -+ SD_CL_1 =1, -+ SD_CL_2, -+ SD_CL_3, -+ SD_CL_4, -+ SD_CL_5, -+ SD_CL_6, -+ SD_CL_7, -+ SD_FAULT -+}MV_DIMM_SDRAM_CAS; -+ -+ -+/* DIMM information structure */ -+typedef struct _mvDimmInfo -+{ -+ MV_MEMORY_TYPE memoryType; /* DDR or SDRAM */ -+ -+ MV_U8 spdRawData[SPD_SIZE]; /* Content of SPD-EEPROM copied 1:1 */ -+ -+ /* DIMM dimensions */ -+ MV_U32 numOfRowAddr; -+ MV_U32 numOfColAddr; -+ MV_U32 numOfModuleBanks; -+ MV_U32 dataWidth; -+ MV_U32 errorCheckType; /* ECC , PARITY..*/ -+ MV_U32 sdramWidth; /* 4,8,16 or 32 */ -+ MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ -+ MV_U32 burstLengthSupported; -+ MV_U32 numOfBanksOnEachDevice; -+ MV_U32 suportedCasLatencies; -+ MV_U32 refreshInterval; -+ MV_U32 dimmBankDensity; -+ MV_U32 dimmTypeInfo; /* DDR2 only */ -+ MV_U32 dimmAttributes; -+ -+ /* DIMM timing parameters */ -+ MV_U32 minCycleTimeAtMaxCasLatPs; -+ MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; -+ MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; -+ MV_U32 minRowPrechargeTime; -+ MV_U32 minRowActiveToRowActive; -+ MV_U32 minRasToCasDelay; -+ MV_U32 minRasPulseWidth; -+ MV_U32 minWriteRecoveryTime; /* DDR2 only */ -+ MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ -+ MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ -+ MV_U32 minRefreshToActiveCmd; /* DDR2 only */ -+ -+ /* Parameters calculated from the extracted DIMM information */ -+ MV_U32 size; /* 16,64,128,256 or 512 MByte in MB units */ -+ MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit in MB units */ -+ MV_U32 numberOfDevices; -+ -+} MV_DIMM_INFO; -+ -+ -+MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo); -+MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo); -+MV_VOID dimmSpdPrint(MV_U32 dimmNum); -+MV_STATUS dimmSpdCpy(MV_VOID); -+ -+#endif /* __INCmvDram */ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEth.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEth.c ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEth.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEth.c 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,2952 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+/******************************************************************************* -+* mvEth.c - Marvell's Gigabit Ethernet controller low level driver -+* -+* DESCRIPTION: -+* This file introduce OS independent APIs to Marvell's Gigabit Ethernet -+* controller. This Gigabit Ethernet Controller driver API controls -+* 1) Operations (i.e. port Init, Finish, Up, Down, PhyReset etc'). -+* 2) Data flow (i.e. port Send, Receive etc'). -+* 3) MAC Filtering functions (ethSetMcastAddr, ethSetRxFilterMode, etc.) -+* 4) MIB counters support (ethReadMibCounter) -+* 5) Debug functions (ethPortRegs, ethPortCounters, ethPortQueues, etc.) -+* Each Gigabit Ethernet port is controlled via ETH_PORT_CTRL struct. -+* This struct includes configuration information as well as driver -+* internal data needed for its operations. -+* -+* Supported Features: -+* - OS independent. All required OS services are implemented via external -+* OS dependent components (like osLayer or ethOsg) -+* - The user is free from Rx/Tx queue managing. -+* - Simple Gigabit Ethernet port operation API. -+* - Simple Gigabit Ethernet port data flow API. -+* - Data flow and operation API support per queue functionality. -+* - Support cached descriptors for better performance. -+* - PHY access and control API. -+* - Port Configuration API. -+* - Full control over Special and Other Multicast MAC tables. -+* -+*******************************************************************************/ -+/* includes */ -+#include "mvTypes.h" -+#include "mv802_3.h" -+#include "mvDebug.h" -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "eth-phy/mvEthPhy.h" -+#include "eth/mvEth.h" -+#include "eth/gbe/mvEthGbe.h" -+#include "cpu/mvCpu.h" -+ -+#ifdef INCLUDE_SYNC_BARR -+#include "sys/mvCpuIf.h" -+#endif -+ -+#ifdef MV_RT_DEBUG -+# define ETH_DEBUG -+#endif -+ -+ -+/* locals */ -+MV_BOOL ethDescInSram; -+MV_BOOL ethDescSwCoher; -+ -+/* This array holds the control structure of each port */ -+ETH_PORT_CTRL* ethPortCtrl[MV_ETH_MAX_PORTS]; -+ -+/* Ethernet Port Local routines */ -+ -+static void ethInitRxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue); -+ -+static void ethInitTxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue); -+ -+static void ethSetUcastTable(int portNo, int queue); -+ -+static MV_BOOL ethSetUcastAddr (int ethPortNum, MV_U8 lastNibble, int queue); -+static MV_BOOL ethSetSpecialMcastAddr(int ethPortNum, MV_U8 lastByte, int queue); -+static MV_BOOL ethSetOtherMcastAddr(int ethPortNum, MV_U8 crc8, int queue); -+ -+static void ethFreeDescrMemory(ETH_PORT_CTRL* pEthPortCtrl, MV_BUF_INFO* pDescBuf); -+static MV_U8* ethAllocDescrMemory(ETH_PORT_CTRL* pEthPortCtrl, int size, -+ MV_ULONG* pPhysAddr, MV_U32 *memHandle); -+ -+static MV_U32 mvEthMruGet(MV_U32 maxRxPktSize); -+ -+static void mvEthPortSgmiiConfig(int port); -+ -+ -+ -+/******************************************************************************/ -+/* EthDrv Initialization functions */ -+/******************************************************************************/ -+ -+/******************************************************************************* -+* mvEthHalInit - Initialize the Giga Ethernet unit -+* -+* DESCRIPTION: -+* This function initialize the Giga Ethernet unit. -+* 1) Configure Address decode windows of the unit -+* 2) Set registers to HW default values. -+* 3) Clear and Disable interrupts -+* -+* INPUT: NONE -+* -+* RETURN: NONE -+* -+* NOTE: this function is called once in the boot process. -+*******************************************************************************/ -+void mvEthHalInit(void) -+{ -+ int port; -+ -+ /* Init static data structures */ -+ for (port=0; port 0) -+ { -+ isSram = MV_TRUE; -+ #if (INTEG_SRAM_COHER == MV_CACHE_COHER_SW) -+ isSwCoher = MV_TRUE; -+ #else -+ isSwCoher = MV_FALSE; -+ #endif -+ } -+#endif /* ETH_DESCR_IN_SRAM */ -+ -+ if(pIsSram != NULL) -+ *pIsSram = isSram; -+ -+ if(pIsSwCoher != NULL) -+ *pIsSwCoher = isSwCoher; -+} -+ -+ -+ -+/******************************************************************************/ -+/* Port Initialization functions */ -+/******************************************************************************/ -+ -+/******************************************************************************* -+* mvEthPortInit - Initialize the Ethernet port driver -+* -+* DESCRIPTION: -+* This function initialize the ethernet port. -+* 1) Allocate and initialize internal port Control structure. -+* 2) Create RX and TX descriptor rings for default RX and TX queues -+* 3) Disable RX and TX operations, clear cause registers and -+* mask all interrupts. -+* 4) Set all registers to default values and clean all MAC tables. -+* -+* INPUT: -+* int portNo - Ethernet port number -+* ETH_PORT_INIT *pEthPortInit - Ethernet port init structure -+* -+* RETURN: -+* void* - ethernet port handler, that should be passed to the most other -+* functions dealing with this port. -+* -+* NOTE: This function is called once per port when loading the eth module. -+*******************************************************************************/ -+void* mvEthPortInit(int portNo, MV_ETH_PORT_INIT *pEthPortInit) -+{ -+ int queue, descSize; -+ ETH_PORT_CTRL* pPortCtrl; -+ -+ /* Check validity of parameters */ -+ if( (portNo >= (int)mvCtrlEthMaxPortGet()) || -+ (pEthPortInit->rxDefQ >= MV_ETH_RX_Q_NUM) || -+ (pEthPortInit->maxRxPktSize < 1518) ) -+ { -+ mvOsPrintf("EthPort #%d: Bad initialization parameters\n", portNo); -+ return NULL; -+ } -+ if( (pEthPortInit->rxDescrNum[pEthPortInit->rxDefQ]) == 0) -+ { -+ mvOsPrintf("EthPort #%d: rxDefQ (%d) must be created\n", -+ portNo, pEthPortInit->rxDefQ); -+ return NULL; -+ } -+ -+ pPortCtrl = (ETH_PORT_CTRL*)mvOsMalloc( sizeof(ETH_PORT_CTRL) ); -+ if(pPortCtrl == NULL) -+ { -+ mvOsPrintf("EthDrv: Can't allocate %dB for port #%d control structure!\n", -+ (int)sizeof(ETH_PORT_CTRL), portNo); -+ return NULL; -+ } -+ -+ memset(pPortCtrl, 0, sizeof(ETH_PORT_CTRL) ); -+ ethPortCtrl[portNo] = pPortCtrl; -+ -+ pPortCtrl->portState = MV_UNDEFINED_STATE; -+ -+ pPortCtrl->portNo = portNo; -+ -+ pPortCtrl->osHandle = pEthPortInit->osHandle; -+ -+ /* Copy Configuration parameters */ -+ pPortCtrl->portConfig.maxRxPktSize = pEthPortInit->maxRxPktSize; -+ pPortCtrl->portConfig.rxDefQ = pEthPortInit->rxDefQ; -+ pPortCtrl->portConfig.ejpMode = 0; -+ -+ for( queue=0; queuerxQueueConfig[queue].descrNum = pEthPortInit->rxDescrNum[queue]; -+ } -+ for( queue=0; queuetxQueueConfig[queue].descrNum = pEthPortInit->txDescrNum[queue]; -+ } -+ -+ mvEthPortDisable(pPortCtrl); -+ -+ /* Set the board information regarding PHY address */ -+ mvEthPhyAddrSet(pPortCtrl, mvBoardPhyAddrGet(portNo) ); -+ -+ /* Create all requested RX queues */ -+ for(queue=0; queuerxQueueConfig[queue].descrNum == 0) -+ continue; -+ -+ /* Allocate memory for RX descriptors */ -+ descSize = ((pPortCtrl->rxQueueConfig[queue].descrNum * ETH_RX_DESC_ALIGNED_SIZE) + -+ CPU_D_CACHE_LINE_SIZE); -+ -+ pPortCtrl->rxQueue[queue].descBuf.bufVirtPtr = -+ ethAllocDescrMemory(pPortCtrl, descSize, -+ &pPortCtrl->rxQueue[queue].descBuf.bufPhysAddr, -+ &pPortCtrl->rxQueue[queue].descBuf.memHandle); -+ pPortCtrl->rxQueue[queue].descBuf.bufSize = descSize; -+ if(pPortCtrl->rxQueue[queue].descBuf.bufVirtPtr == NULL) -+ { -+ mvOsPrintf("EthPort #%d, rxQ=%d: Can't allocate %d bytes in %s for %d RX descr\n", -+ pPortCtrl->portNo, queue, descSize, -+ ethDescInSram ? "SRAM" : "DRAM", -+ pPortCtrl->rxQueueConfig[queue].descrNum); -+ return NULL; -+ } -+ -+ ethInitRxDescRing(pPortCtrl, queue); -+ } -+ /* Create TX queues */ -+ for(queue=0; queuetxQueueConfig[queue].descrNum == 0) -+ continue; -+ -+ /* Allocate memory for TX descriptors */ -+ descSize = ((pPortCtrl->txQueueConfig[queue].descrNum * ETH_TX_DESC_ALIGNED_SIZE) + -+ CPU_D_CACHE_LINE_SIZE); -+ -+ pPortCtrl->txQueue[queue].descBuf.bufVirtPtr = -+ ethAllocDescrMemory(pPortCtrl, descSize, -+ &pPortCtrl->txQueue[queue].descBuf.bufPhysAddr, -+ &pPortCtrl->txQueue[queue].descBuf.memHandle); -+ pPortCtrl->txQueue[queue].descBuf.bufSize = descSize; -+ if(pPortCtrl->txQueue[queue].descBuf.bufVirtPtr == NULL) -+ { -+ mvOsPrintf("EthPort #%d, txQ=%d: Can't allocate %d bytes in %s for %d TX descr\n", -+ pPortCtrl->portNo, queue, descSize, ethDescInSram ? "SRAM" : "DRAM", -+ pPortCtrl->txQueueConfig[queue].descrNum); -+ return NULL; -+ } -+ -+ ethInitTxDescRing(pPortCtrl, queue); -+ } -+ mvEthDefaultsSet(pPortCtrl); -+ -+ pPortCtrl->portState = MV_IDLE; -+ return pPortCtrl; -+} -+ -+/******************************************************************************* -+* ethPortFinish - Finish the Ethernet port driver -+* -+* DESCRIPTION: -+* This function finish the ethernet port. -+* 1) Down ethernet port if needed. -+* 2) Delete RX and TX descriptor rings for all created RX and TX queues -+* 3) Free internal port Control structure. -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet port handler -+* -+* RETURN: NONE. -+* -+*******************************************************************************/ -+void mvEthPortFinish(void* pPortHndl) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ int queue, portNo = pPortCtrl->portNo; -+ -+ if(pPortCtrl->portState == MV_ACTIVE) -+ { -+ mvOsPrintf("ethPort #%d: Warning !!! Finish port in Active state\n", -+ portNo); -+ mvEthPortDisable(pPortHndl); -+ } -+ -+ /* Free all allocated RX queues */ -+ for(queue=0; queuerxQueue[queue].descBuf); -+ } -+ -+ /* Free all allocated TX queues */ -+ for(queue=0; queuetxQueue[queue].descBuf); -+ } -+ -+ /* Free port control structure */ -+ mvOsFree(pPortCtrl); -+ -+ ethPortCtrl[portNo] = NULL; -+} -+ -+/******************************************************************************* -+* mvEthDefaultsSet - Set defaults to the ethernet port -+* -+* DESCRIPTION: -+* This function set default values to the ethernet port. -+* 1) Clear Cause registers and Mask all interrupts -+* 2) Clear all MAC tables -+* 3) Set defaults to all registers -+* 4) Reset all created RX and TX descriptors ring -+* 5) Reset PHY -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet port handler -+* -+* RETURN: MV_STATUS -+* MV_OK - Success, Others - Failure -+* NOTE: -+* This function update all the port configuration except those set -+* Initialy by the OsGlue by MV_ETH_PORT_INIT. -+* This function can be called after portDown to return the port setting -+* to defaults. -+*******************************************************************************/ -+MV_STATUS mvEthDefaultsSet(void* pPortHndl) -+{ -+ int ethPortNo, queue; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ MV_U32 txPrio; -+ MV_U32 portCfgReg, portCfgExtReg, portSerialCtrlReg, portSerialCtrl1Reg, portSdmaCfgReg; -+ MV_BOARD_MAC_SPEED boardMacCfg; -+ -+ ethPortNo = pPortCtrl->portNo; -+ -+ /* Clear Cause registers */ -+ MV_REG_WRITE(ETH_INTR_CAUSE_REG(ethPortNo),0); -+ MV_REG_WRITE(ETH_INTR_CAUSE_EXT_REG(ethPortNo),0); -+ -+ /* Mask all interrupts */ -+ MV_REG_WRITE(ETH_INTR_MASK_REG(ethPortNo),0); -+ MV_REG_WRITE(ETH_INTR_MASK_EXT_REG(ethPortNo),0); -+ -+ portCfgReg = PORT_CONFIG_VALUE; -+ portCfgExtReg = PORT_CONFIG_EXTEND_VALUE; -+ -+ boardMacCfg = mvBoardMacSpeedGet(ethPortNo); -+ -+ if(boardMacCfg == BOARD_MAC_SPEED_100M) -+ { -+ portSerialCtrlReg = PORT_SERIAL_CONTROL_100MB_FORCE_VALUE; -+ } -+ else if(boardMacCfg == BOARD_MAC_SPEED_1000M) -+ { -+ portSerialCtrlReg = PORT_SERIAL_CONTROL_1000MB_FORCE_VALUE; -+ } -+ else -+ { -+ portSerialCtrlReg = PORT_SERIAL_CONTROL_VALUE; -+ } -+ -+ /* build PORT_SDMA_CONFIG_REG */ -+ portSdmaCfgReg = ETH_TX_INTR_COAL_MASK(0); -+ portSdmaCfgReg |= ETH_TX_BURST_SIZE_MASK(ETH_BURST_SIZE_16_64BIT_VALUE); -+ -+#if ( (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WB) || \ -+ (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WT) ) -+ /* some devices have restricted RX burst size when using HW coherency */ -+ portSdmaCfgReg |= ETH_RX_BURST_SIZE_MASK(ETH_BURST_SIZE_4_64BIT_VALUE); -+#else -+ portSdmaCfgReg |= ETH_RX_BURST_SIZE_MASK(ETH_BURST_SIZE_16_64BIT_VALUE); -+#endif -+ -+#if defined(MV_CPU_BE) -+ /* big endian */ -+# if defined(MV_ARM) -+ portSdmaCfgReg |= (ETH_RX_NO_DATA_SWAP_MASK | -+ ETH_TX_NO_DATA_SWAP_MASK | -+ ETH_DESC_SWAP_MASK); -+# elif defined(MV_PPC) -+ portSdmaCfgReg |= (ETH_RX_DATA_SWAP_MASK | -+ ETH_TX_DATA_SWAP_MASK | -+ ETH_NO_DESC_SWAP_MASK); -+# else -+# error "Giga Ethernet Swap policy is not defined for the CPU_ARCH" -+# endif /* MV_ARM / MV_PPC */ -+ -+#else /* MV_CPU_LE */ -+ /* little endian */ -+ portSdmaCfgReg |= (ETH_RX_NO_DATA_SWAP_MASK | -+ ETH_TX_NO_DATA_SWAP_MASK | -+ ETH_NO_DESC_SWAP_MASK); -+#endif /* MV_CPU_BE / MV_CPU_LE */ -+ -+ pPortCtrl->portRxQueueCmdReg = 0; -+ pPortCtrl->portTxQueueCmdReg = 0; -+ -+#if (MV_ETH_VERSION >= 4) -+ if(pPortCtrl->portConfig.ejpMode == MV_TRUE) -+ { -+ MV_REG_WRITE(ETH_TXQ_CMD_1_REG(ethPortNo), ETH_TX_EJP_ENABLE_MASK); -+ } -+ else -+ { -+ MV_REG_WRITE(ETH_TXQ_CMD_1_REG(ethPortNo), 0) -+ } -+#endif /* (MV_ETH_VERSION >= 4) */ -+ -+ ethSetUcastTable(ethPortNo, -1); -+ mvEthSetSpecialMcastTable(ethPortNo, -1); -+ mvEthSetOtherMcastTable(ethPortNo, -1); -+ -+ portSerialCtrlReg &= ~ETH_MAX_RX_PACKET_SIZE_MASK; -+ -+ portSerialCtrlReg |= mvEthMruGet(pPortCtrl->portConfig.maxRxPktSize); -+ -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNo), portSerialCtrlReg); -+ -+ /* Update value of PortConfig register accordingly with all RxQueue types */ -+ pPortCtrl->portConfig.rxArpQ = pPortCtrl->portConfig.rxDefQ; -+ pPortCtrl->portConfig.rxBpduQ = pPortCtrl->portConfig.rxDefQ; -+ pPortCtrl->portConfig.rxTcpQ = pPortCtrl->portConfig.rxDefQ; -+ pPortCtrl->portConfig.rxUdpQ = pPortCtrl->portConfig.rxDefQ; -+ -+ portCfgReg &= ~ETH_DEF_RX_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_QUEUE_MASK(pPortCtrl->portConfig.rxDefQ); -+ -+ portCfgReg &= ~ETH_DEF_RX_ARP_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_ARP_QUEUE_MASK(pPortCtrl->portConfig.rxArpQ); -+ -+ portCfgReg &= ~ETH_DEF_RX_BPDU_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_BPDU_QUEUE_MASK(pPortCtrl->portConfig.rxBpduQ); -+ -+ portCfgReg &= ~ETH_DEF_RX_TCP_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_TCP_QUEUE_MASK(pPortCtrl->portConfig.rxTcpQ); -+ -+ portCfgReg &= ~ETH_DEF_RX_UDP_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_UDP_QUEUE_MASK(pPortCtrl->portConfig.rxUdpQ); -+ -+ /* Assignment of Tx CTRP of given queue */ -+ txPrio = 0; -+ -+ for(queue=0; queuetxQueue[queue]; -+ -+ if(pQueueCtrl->pFirstDescr != NULL) -+ { -+ ethResetTxDescRing(pPortCtrl, queue); -+ -+ MV_REG_WRITE(ETH_TXQ_TOKEN_COUNT_REG(ethPortNo, queue), -+ 0x3fffffff); -+ MV_REG_WRITE(ETH_TXQ_TOKEN_CFG_REG(ethPortNo, queue), -+ 0x03ffffff); -+ } -+ else -+ { -+ MV_REG_WRITE(ETH_TXQ_TOKEN_COUNT_REG(ethPortNo, queue), 0x0); -+ MV_REG_WRITE(ETH_TXQ_TOKEN_CFG_REG(ethPortNo, queue), 0x0); -+ } -+ } -+ -+ /* Assignment of Rx CRDP of given queue */ -+ for(queue=0; queueportNo; -+ -+ if( (pPortCtrl->portState != MV_ACTIVE) && -+ (pPortCtrl->portState != MV_PAUSED) ) -+ { -+ mvOsPrintf("ethDrv port%d: Unexpected port state %d\n", -+ ethPortNo, pPortCtrl->portState); -+ return MV_BAD_STATE; -+ } -+ -+ ethPortNo = pPortCtrl->portNo; -+ -+ /* Enable port RX. */ -+ MV_REG_WRITE(ETH_RX_QUEUE_COMMAND_REG(ethPortNo), pPortCtrl->portRxQueueCmdReg); -+ -+ /* Enable port TX. */ -+ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(ethPortNo)) = pPortCtrl->portTxQueueCmdReg; -+ -+ pPortCtrl->portState = MV_ACTIVE; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* ethPortDown - Stop the Ethernet port activity. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet port handler -+* -+* RETURN: MV_STATUS -+* MV_OK - Success, Others - Failure. -+* -+* NOTE : used for port link down. -+*******************************************************************************/ -+MV_STATUS mvEthPortDown(void* pEthPortHndl) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ int ethPortNum = pPortCtrl->portNo; -+ unsigned int regData; -+ volatile int uDelay, mDelay; -+ -+ /* Stop Rx port activity. Check port Rx activity. */ -+ regData = (MV_REG_READ(ETH_RX_QUEUE_COMMAND_REG(ethPortNum))) & ETH_RXQ_ENABLE_MASK; -+ if(regData != 0) -+ { -+ /* Issue stop command for active channels only */ -+ MV_REG_WRITE(ETH_RX_QUEUE_COMMAND_REG(ethPortNum), (regData << ETH_RXQ_DISABLE_OFFSET)); -+ } -+ -+ /* Stop Tx port activity. Check port Tx activity. */ -+ regData = (MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(ethPortNum))) & ETH_TXQ_ENABLE_MASK; -+ if(regData != 0) -+ { -+ /* Issue stop command for active channels only */ -+ MV_REG_WRITE(ETH_TX_QUEUE_COMMAND_REG(ethPortNum), -+ (regData << ETH_TXQ_DISABLE_OFFSET) ); -+ } -+ -+ /* Force link down */ -+/* -+ regData = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNum)); -+ regData &= ~(ETH_DO_NOT_FORCE_LINK_FAIL_MASK); -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNum), regData); -+*/ -+ /* Wait for all Rx activity to terminate. */ -+ mDelay = 0; -+ do -+ { -+ if(mDelay >= RX_DISABLE_TIMEOUT_MSEC) -+ { -+ mvOsPrintf("ethPort_%d: TIMEOUT for RX stopped !!! rxQueueCmd - 0x08%x\n", -+ ethPortNum, regData); -+ break; -+ } -+ mvOsDelay(1); -+ mDelay++; -+ -+ /* Check port RX Command register that all Rx queues are stopped */ -+ regData = MV_REG_READ(ETH_RX_QUEUE_COMMAND_REG(ethPortNum)); -+ } -+ while(regData & 0xFF); -+ -+ /* Wait for all Tx activity to terminate. */ -+ mDelay = 0; -+ do -+ { -+ if(mDelay >= TX_DISABLE_TIMEOUT_MSEC) -+ { -+ mvOsPrintf("ethPort_%d: TIMEOUT for TX stoped !!! txQueueCmd - 0x08%x\n", -+ ethPortNum, regData); -+ break; -+ } -+ mvOsDelay(1); -+ mDelay++; -+ -+ /* Check port TX Command register that all Tx queues are stopped */ -+ regData = MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(ethPortNum)); -+ } -+ while(regData & 0xFF); -+ -+ /* Double check to Verify that TX FIFO is Empty */ -+ mDelay = 0; -+ while(MV_TRUE) -+ { -+ do -+ { -+ if(mDelay >= TX_FIFO_EMPTY_TIMEOUT_MSEC) -+ { -+ mvOsPrintf("\n ethPort_%d: TIMEOUT for TX FIFO empty !!! portStatus - 0x08%x\n", -+ ethPortNum, regData); -+ break; -+ } -+ mvOsDelay(1); -+ mDelay++; -+ -+ regData = MV_REG_READ(ETH_PORT_STATUS_REG(ethPortNum)); -+ } -+ while( ((regData & ETH_TX_FIFO_EMPTY_MASK) == 0) || -+ ((regData & ETH_TX_IN_PROGRESS_MASK) != 0) ); -+ -+ if(mDelay >= TX_FIFO_EMPTY_TIMEOUT_MSEC) -+ break; -+ -+ /* Double check */ -+ regData = MV_REG_READ(ETH_PORT_STATUS_REG(ethPortNum)); -+ if( ((regData & ETH_TX_FIFO_EMPTY_MASK) != 0) && -+ ((regData & ETH_TX_IN_PROGRESS_MASK) == 0) ) -+ { -+ break; -+ } -+ else -+ mvOsPrintf("ethPort_%d: TX FIFO Empty double check failed. %d msec, portStatus=0x%x\n", -+ ethPortNum, mDelay, regData); -+ } -+ -+ /* Do NOT force link down */ -+/* -+ regData = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNum)); -+ regData |= (ETH_DO_NOT_FORCE_LINK_FAIL_MASK); -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNum), regData); -+*/ -+ /* Wait about 2500 tclk cycles */ -+ uDelay = (PORT_DISABLE_WAIT_TCLOCKS/(mvBoardTclkGet()/1000000)); -+ mvOsUDelay(uDelay); -+ -+ pPortCtrl->portState = MV_PAUSED; -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* ethPortEnable - Enable the Ethernet port and Start RX and TX. -+* -+* DESCRIPTION: -+* This routine enable the Ethernet port and Rx and Tx activity: -+* -+* Note: Each Rx and Tx queue descriptor's list must be initialized prior -+* to calling this function (use etherInitTxDescRing for Tx queues and -+* etherInitRxDescRing for Rx queues). -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet port handler -+* -+* RETURN: MV_STATUS -+* MV_OK - Success, Others - Failure. -+* -+* NOTE: main usage is to enable the port after ifconfig up. -+*******************************************************************************/ -+MV_STATUS mvEthPortEnable(void* pEthPortHndl) -+{ -+ int ethPortNo; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ MV_U32 portSerialCtrlReg; -+ -+ ethPortNo = pPortCtrl->portNo; -+ -+ /* Enable port */ -+ portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNo)); -+ portSerialCtrlReg |= (ETH_DO_NOT_FORCE_LINK_FAIL_MASK | ETH_PORT_ENABLE_MASK); -+ -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNo), portSerialCtrlReg); -+ -+ mvEthMibCountersClear(pEthPortHndl); -+ -+ pPortCtrl->portState = MV_PAUSED; -+ -+ /* If Link is UP, Start RX and TX traffic */ -+ if( MV_REG_READ( ETH_PORT_STATUS_REG(ethPortNo) ) & ETH_LINK_UP_MASK) -+ return( mvEthPortUp(pEthPortHndl) ); -+ -+ return MV_NOT_READY; -+} -+ -+ -+/******************************************************************************* -+* mvEthPortDisable - Stop RX and TX activities and Disable the Ethernet port. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet port handler -+* -+* RETURN: MV_STATUS -+* MV_OK - Success, Others - Failure. -+* -+* NOTE: main usage is to disable the port after ifconfig down. -+*******************************************************************************/ -+MV_STATUS mvEthPortDisable(void* pEthPortHndl) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ int ethPortNum = pPortCtrl->portNo; -+ unsigned int regData; -+ volatile int mvDelay; -+ -+ if(pPortCtrl->portState == MV_ACTIVE) -+ { -+ /* Stop RX and TX activities */ -+ mvEthPortDown(pEthPortHndl); -+ } -+ -+ /* Reset the Enable bit in the Serial Control Register */ -+ regData = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNum)); -+ regData &= ~(ETH_PORT_ENABLE_MASK); -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNum), regData); -+ -+ /* Wait about 2500 tclk cycles */ -+ mvDelay = (PORT_DISABLE_WAIT_TCLOCKS*(mvCpuPclkGet()/mvBoardTclkGet())); -+ for(mvDelay; mvDelay>0; mvDelay--); -+ -+ pPortCtrl->portState = MV_IDLE; -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthPortForceTxDone - Get next buffer from TX queue in spite of buffer ownership. -+* -+* DESCRIPTION: -+* This routine used to free buffers attached to the Tx ring and should -+* be called only when Giga Ethernet port is Down -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet Port handler. -+* int txQueue - Number of TX queue. -+* -+* OUTPUT: -+* MV_PKT_INFO *pPktInfo - Pointer to packet was sent. -+* -+* RETURN: -+* MV_EMPTY - There is no more buffers in this queue. -+* MV_OK - Buffer detached from the queue and pPktInfo structure -+* filled with relevant information. -+* -+*******************************************************************************/ -+MV_PKT_INFO* mvEthPortForceTxDone(void* pEthPortHndl, int txQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ MV_PKT_INFO* pPktInfo; -+ ETH_TX_DESC* pTxDesc; -+ int port = pPortCtrl->portNo; -+ -+ pQueueCtrl = &pPortCtrl->txQueue[txQueue]; -+ -+ while( (pQueueCtrl->pUsedDescr != pQueueCtrl->pCurrentDescr) || -+ (pQueueCtrl->resource == 0) ) -+ { -+ /* Free next descriptor */ -+ pQueueCtrl->resource++; -+ pTxDesc = (ETH_TX_DESC*)pQueueCtrl->pUsedDescr; -+ -+ /* pPktInfo is available only in descriptors which are last descriptors */ -+ pPktInfo = (MV_PKT_INFO*)pTxDesc->returnInfo; -+ if (pPktInfo) -+ pPktInfo->status = pTxDesc->cmdSts; -+ -+ pTxDesc->cmdSts = 0x0; -+ pTxDesc->returnInfo = 0x0; -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxDesc); -+ -+ pQueueCtrl->pUsedDescr = TX_NEXT_DESC_PTR(pTxDesc, pQueueCtrl); -+ -+ if (pPktInfo) -+ if (pPktInfo->status & ETH_TX_LAST_DESC_MASK) -+ return pPktInfo; -+ } -+ MV_REG_WRITE( ETH_TX_CUR_DESC_PTR_REG(port, txQueue), -+ (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); -+ return NULL; -+} -+ -+ -+ -+/******************************************************************************* -+* mvEthPortForceRx - Get next buffer from RX queue in spite of buffer ownership. -+* -+* DESCRIPTION: -+* This routine used to free buffers attached to the Rx ring and should -+* be called only when Giga Ethernet port is Down -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet Port handler. -+* int rxQueue - Number of Rx queue. -+* -+* OUTPUT: -+* MV_PKT_INFO *pPktInfo - Pointer to received packet. -+* -+* RETURN: -+* MV_EMPTY - There is no more buffers in this queue. -+* MV_OK - Buffer detached from the queue and pBufInfo structure -+* filled with relevant information. -+* -+*******************************************************************************/ -+MV_PKT_INFO* mvEthPortForceRx(void* pEthPortHndl, int rxQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ ETH_RX_DESC* pRxDesc; -+ MV_PKT_INFO* pPktInfo; -+ int port = pPortCtrl->portNo; -+ -+ pQueueCtrl = &pPortCtrl->rxQueue[rxQueue]; -+ -+ if(pQueueCtrl->resource == 0) -+ { -+ MV_REG_WRITE( ETH_RX_CUR_DESC_PTR_REG(port, rxQueue), -+ (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); -+ -+ return NULL; -+ } -+ /* Free next descriptor */ -+ pQueueCtrl->resource--; -+ pRxDesc = (ETH_RX_DESC*)pQueueCtrl->pCurrentDescr; -+ pPktInfo = (MV_PKT_INFO*)pRxDesc->returnInfo; -+ -+ pPktInfo->status = pRxDesc->cmdSts; -+ pRxDesc->cmdSts = 0x0; -+ pRxDesc->returnInfo = 0x0; -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxDesc); -+ -+ pQueueCtrl->pCurrentDescr = RX_NEXT_DESC_PTR(pRxDesc, pQueueCtrl); -+ return pPktInfo; -+} -+ -+ -+/******************************************************************************/ -+/* Port Configuration functions */ -+/******************************************************************************/ -+/******************************************************************************* -+* mvEthMruGet - Get MRU configuration for Max Rx packet size. -+* -+* INPUT: -+* MV_U32 maxRxPktSize - max packet size. -+* -+* RETURN: MV_U32 - MRU configuration. -+* -+*******************************************************************************/ -+static MV_U32 mvEthMruGet(MV_U32 maxRxPktSize) -+{ -+ MV_U32 portSerialCtrlReg = 0; -+ -+ if(maxRxPktSize > 9192) -+ portSerialCtrlReg |= ETH_MAX_RX_PACKET_9700BYTE; -+ else if(maxRxPktSize > 9022) -+ portSerialCtrlReg |= ETH_MAX_RX_PACKET_9192BYTE; -+ else if(maxRxPktSize > 1552) -+ portSerialCtrlReg |= ETH_MAX_RX_PACKET_9022BYTE; -+ else if(maxRxPktSize > 1522) -+ portSerialCtrlReg |= ETH_MAX_RX_PACKET_1552BYTE; -+ else if(maxRxPktSize > 1518) -+ portSerialCtrlReg |= ETH_MAX_RX_PACKET_1522BYTE; -+ else -+ portSerialCtrlReg |= ETH_MAX_RX_PACKET_1518BYTE; -+ -+ return portSerialCtrlReg; -+} -+ -+/******************************************************************************* -+* mvEthRxCoalSet - Sets coalescing interrupt mechanism on RX path -+* -+* DESCRIPTION: -+* This routine sets the RX coalescing interrupt mechanism parameter. -+* This parameter is a timeout counter, that counts in 64 tClk -+* chunks, that when timeout event occurs a maskable interrupt occurs. -+* The parameter is calculated using the tCLK frequency of the -+* MV-64xxx chip, and the required number is in micro seconds. -+* -+* INPUT: -+* void* pPortHndl - Ethernet Port handler. -+* MV_U32 uSec - Number of micro seconds between -+* RX interrupts -+* -+* RETURN: -+* None. -+* -+* COMMENT: -+* 1 sec - TCLK_RATE clocks -+* 1 uSec - TCLK_RATE / 1,000,000 clocks -+* -+* Register Value for N micro seconds - ((N * ( (TCLK_RATE / 1,000,000)) / 64) -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_U32 mvEthRxCoalSet (void* pPortHndl, MV_U32 uSec) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ MV_U32 coal = ((uSec * (mvBoardTclkGet() / 1000000)) / 64); -+ MV_U32 portSdmaCfgReg; -+ -+ portSdmaCfgReg = MV_REG_READ(ETH_SDMA_CONFIG_REG(pPortCtrl->portNo)); -+ portSdmaCfgReg &= ~ETH_RX_INTR_COAL_ALL_MASK; -+ -+ portSdmaCfgReg |= ETH_RX_INTR_COAL_MASK(coal); -+ -+#if (MV_ETH_VERSION >= 2) -+ /* Set additional bit if needed ETH_RX_INTR_COAL_MSB_BIT (25) */ -+ if(ETH_RX_INTR_COAL_MASK(coal) > ETH_RX_INTR_COAL_ALL_MASK) -+ portSdmaCfgReg |= ETH_RX_INTR_COAL_MSB_MASK; -+#endif /* MV_ETH_VERSION >= 2 */ -+ -+ MV_REG_WRITE (ETH_SDMA_CONFIG_REG(pPortCtrl->portNo), portSdmaCfgReg); -+ return coal; -+} -+ -+/******************************************************************************* -+* mvEthTxCoalSet - Sets coalescing interrupt mechanism on TX path -+* -+* DESCRIPTION: -+* This routine sets the TX coalescing interrupt mechanism parameter. -+* This parameter is a timeout counter, that counts in 64 tClk -+* chunks, that when timeout event occurs a maskable interrupt -+* occurs. -+* The parameter is calculated using the tCLK frequency of the -+* MV-64xxx chip, and the required number is in micro seconds. -+* -+* INPUT: -+* void* pPortHndl - Ethernet Port handler. -+* MV_U32 uSec - Number of micro seconds between -+* RX interrupts -+* -+* RETURN: -+* None. -+* -+* COMMENT: -+* 1 sec - TCLK_RATE clocks -+* 1 uSec - TCLK_RATE / 1,000,000 clocks -+* -+* Register Value for N micro seconds - ((N * ( (TCLK_RATE / 1,000,000)) / 64) -+* -+*******************************************************************************/ -+MV_U32 mvEthTxCoalSet(void* pPortHndl, MV_U32 uSec) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ MV_U32 coal = ((uSec * (mvBoardTclkGet() / 1000000)) / 64); -+ MV_U32 regVal; -+ -+ regVal = MV_REG_READ(ETH_TX_FIFO_URGENT_THRESH_REG(pPortCtrl->portNo)); -+ regVal &= ~ETH_TX_INTR_COAL_ALL_MASK; -+ regVal |= ETH_TX_INTR_COAL_MASK(coal); -+ -+ /* Set TX Coalescing mechanism */ -+ MV_REG_WRITE (ETH_TX_FIFO_URGENT_THRESH_REG(pPortCtrl->portNo), regVal); -+ return coal; -+} -+ -+/******************************************************************************* -+* mvEthCoalGet - Gets RX and TX coalescing values in micro seconds -+* -+* DESCRIPTION: -+* This routine gets the RX and TX coalescing interrupt values. -+* The parameter is calculated using the tCLK frequency of the -+* MV-64xxx chip, and the returned numbers are in micro seconds. -+* -+* INPUTs: -+* void* pPortHndl - Ethernet Port handler. -+* -+* OUTPUTs: -+* MV_U32* pRxCoal - Number of micro seconds between RX interrupts -+* MV_U32* pTxCoal - Number of micro seconds between TX interrupts -+* -+* RETURN: -+* MV_STATUS MV_OK - success -+* Others - failure. -+* -+* COMMENT: -+* 1 sec - TCLK_RATE clocks -+* 1 uSec - TCLK_RATE / 1,000,000 clocks -+* -+* Register Value for N micro seconds - ((N * ( (TCLK_RATE / 1,000,000)) / 64) -+* -+*******************************************************************************/ -+MV_STATUS mvEthCoalGet(void* pPortHndl, MV_U32* pRxCoal, MV_U32* pTxCoal) -+{ -+ MV_U32 regVal, coal, usec; -+ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ -+ /* get TX Coalescing */ -+ regVal = MV_REG_READ (ETH_TX_FIFO_URGENT_THRESH_REG(pPortCtrl->portNo)); -+ coal = ((regVal & ETH_TX_INTR_COAL_ALL_MASK) >> ETH_TX_INTR_COAL_OFFSET); -+ -+ usec = (coal * 64) / (mvBoardTclkGet() / 1000000); -+ if(pTxCoal != NULL) -+ *pTxCoal = usec; -+ -+ /* Get RX Coalescing */ -+ regVal = MV_REG_READ(ETH_SDMA_CONFIG_REG(pPortCtrl->portNo)); -+ coal = ((regVal & ETH_RX_INTR_COAL_ALL_MASK) >> ETH_RX_INTR_COAL_OFFSET); -+ -+#if (MV_ETH_VERSION >= 2) -+ if(regVal & ETH_RX_INTR_COAL_MSB_MASK) -+ { -+ /* Add MSB */ -+ coal |= (ETH_RX_INTR_COAL_ALL_MASK + 1); -+ } -+#endif /* MV_ETH_VERSION >= 2 */ -+ -+ usec = (coal * 64) / (mvBoardTclkGet() / 1000000); -+ if(pRxCoal != NULL) -+ *pRxCoal = usec; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthMaxRxSizeSet - -+* -+* DESCRIPTION: -+* Change maximum receive size of the port. This configuration will take place -+* after next call of ethPortSetDefaults() function. -+* -+* INPUT: -+* -+* RETURN: -+*******************************************************************************/ -+MV_STATUS mvEthMaxRxSizeSet(void* pPortHndl, int maxRxSize) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ MV_U32 portSerialCtrlReg; -+ -+ if((maxRxSize < 1518) || (maxRxSize & ~ETH_RX_BUFFER_MASK)) -+ return MV_BAD_PARAM; -+ -+ pPortCtrl->portConfig.maxRxPktSize = maxRxSize; -+ -+ portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(pPortCtrl->portNo)); -+ portSerialCtrlReg &= ~ETH_MAX_RX_PACKET_SIZE_MASK; -+ portSerialCtrlReg |= mvEthMruGet(pPortCtrl->portConfig.maxRxPktSize); -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(pPortCtrl->portNo), portSerialCtrlReg); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************/ -+/* MAC Filtering functions */ -+/******************************************************************************/ -+ -+/******************************************************************************* -+* mvEthRxFilterModeSet - Configure Fitering mode of Ethernet port -+* -+* DESCRIPTION: -+* This routine used to free buffers attached to the Rx ring and should -+* be called only when Giga Ethernet port is Down -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet Port handler. -+* MV_BOOL isPromisc - Promiscous mode -+* MV_TRUE - accept all Broadcast, Multicast -+* and Unicast packets -+* MV_FALSE - accept all Broadcast, -+* specially added Multicast and -+* single Unicast packets -+* -+* RETURN: MV_STATUS MV_OK - Success, Other - Failure -+* -+*******************************************************************************/ -+MV_STATUS mvEthRxFilterModeSet(void* pEthPortHndl, MV_BOOL isPromisc) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ int queue; -+ MV_U32 portCfgReg; -+ -+ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); -+ /* Set / Clear UPM bit in port configuration register */ -+ if(isPromisc) -+ { -+ /* Accept all multicast packets to RX default queue */ -+ queue = pPortCtrl->portConfig.rxDefQ; -+ portCfgReg |= ETH_UNICAST_PROMISCUOUS_MODE_MASK; -+ memset(pPortCtrl->mcastCount, 1, sizeof(pPortCtrl->mcastCount)); -+ MV_REG_WRITE(ETH_MAC_ADDR_LOW_REG(pPortCtrl->portNo),0xFFFF); -+ MV_REG_WRITE(ETH_MAC_ADDR_HIGH_REG(pPortCtrl->portNo),0xFFFFFFFF); -+ } -+ else -+ { -+ /* Reject all Multicast addresses */ -+ queue = -1; -+ portCfgReg &= ~ETH_UNICAST_PROMISCUOUS_MODE_MASK; -+ /* Clear all mcastCount */ -+ memset(pPortCtrl->mcastCount, 0, sizeof(pPortCtrl->mcastCount)); -+ } -+ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); -+ -+ /* Set Special Multicast and Other Multicast tables */ -+ mvEthSetSpecialMcastTable(pPortCtrl->portNo, queue); -+ mvEthSetOtherMcastTable(pPortCtrl->portNo, queue); -+ ethSetUcastTable(pPortCtrl->portNo, queue); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthMacAddrSet - This function Set the port Unicast address. -+* -+* DESCRIPTION: -+* This function Set the port Ethernet MAC address. This address -+* will be used to send Pause frames if enabled. Packets with this -+* address will be accepted and dispatched to default RX queue -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet port handler. -+* char* pAddr - Address to be set -+* -+* RETURN: MV_STATUS -+* MV_OK - Success, Other - Faulure -+* -+*******************************************************************************/ -+MV_STATUS mvEthMacAddrSet(void* pPortHndl, unsigned char *pAddr, int queue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ unsigned int macH; -+ unsigned int macL; -+ -+ if(queue >= MV_ETH_RX_Q_NUM) -+ { -+ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", queue); -+ return MV_BAD_PARAM; -+ } -+ -+ if(queue != -1) -+ { -+ macL = (pAddr[4] << 8) | (pAddr[5]); -+ macH = (pAddr[0] << 24)| (pAddr[1] << 16) | -+ (pAddr[2] << 8) | (pAddr[3] << 0); -+ -+ MV_REG_WRITE(ETH_MAC_ADDR_LOW_REG(pPortCtrl->portNo), macL); -+ MV_REG_WRITE(ETH_MAC_ADDR_HIGH_REG(pPortCtrl->portNo), macH); -+ } -+ -+ /* Accept frames of this address */ -+ ethSetUcastAddr(pPortCtrl->portNo, pAddr[5], queue); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthMacAddrGet - This function returns the port Unicast address. -+* -+* DESCRIPTION: -+* This function returns the port Ethernet MAC address. -+* -+* INPUT: -+* int portNo - Ethernet port number. -+* char* pAddr - Pointer where address will be written to -+* -+* RETURN: MV_STATUS -+* MV_OK - Success, Other - Faulure -+* -+*******************************************************************************/ -+MV_STATUS mvEthMacAddrGet(int portNo, unsigned char *pAddr) -+{ -+ unsigned int macH; -+ unsigned int macL; -+ -+ if(pAddr == NULL) -+ { -+ mvOsPrintf("mvEthMacAddrGet: NULL pointer.\n"); -+ return MV_BAD_PARAM; -+ } -+ -+ macH = MV_REG_READ(ETH_MAC_ADDR_HIGH_REG(portNo)); -+ macL = MV_REG_READ(ETH_MAC_ADDR_LOW_REG(portNo)); -+ pAddr[0] = (macH >> 24) & 0xff; -+ pAddr[1] = (macH >> 16) & 0xff; -+ pAddr[2] = (macH >> 8) & 0xff; -+ pAddr[3] = macH & 0xff; -+ pAddr[4] = (macL >> 8) & 0xff; -+ pAddr[5] = macL & 0xff; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthMcastCrc8Get - Calculate CRC8 of MAC address. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* MV_U8* pAddr - Address to calculate CRC-8 -+* -+* RETURN: MV_U8 - CRC-8 of this MAC address -+* -+*******************************************************************************/ -+MV_U8 mvEthMcastCrc8Get(MV_U8* pAddr) -+{ -+ unsigned int macH; -+ unsigned int macL; -+ int macArray[48]; -+ int crc[8]; -+ int i; -+ unsigned char crcResult = 0; -+ -+ /* Calculate CRC-8 out of the given address */ -+ macH = (pAddr[0] << 8) | (pAddr[1]); -+ macL = (pAddr[2] << 24)| (pAddr[3] << 16) | -+ (pAddr[4] << 8) | (pAddr[5] << 0); -+ -+ for(i=0; i<32; i++) -+ macArray[i] = (macL >> i) & 0x1; -+ -+ for(i=32; i<48; i++) -+ macArray[i] = (macH >> (i - 32)) & 0x1; -+ -+ crc[0] = macArray[45] ^ macArray[43] ^ macArray[40] ^ macArray[39] ^ -+ macArray[35] ^ macArray[34] ^ macArray[31] ^ macArray[30] ^ -+ macArray[28] ^ macArray[23] ^ macArray[21] ^ macArray[19] ^ -+ macArray[18] ^ macArray[16] ^ macArray[14] ^ macArray[12] ^ -+ macArray[8] ^ macArray[7] ^ macArray[6] ^ macArray[0]; -+ -+ crc[1] = macArray[46] ^ macArray[45] ^ macArray[44] ^ macArray[43] ^ -+ macArray[41] ^ macArray[39] ^ macArray[36] ^ macArray[34] ^ -+ macArray[32] ^ macArray[30] ^ macArray[29] ^ macArray[28] ^ -+ macArray[24] ^ macArray[23] ^ macArray[22] ^ macArray[21] ^ -+ macArray[20] ^ macArray[18] ^ macArray[17] ^ macArray[16] ^ -+ macArray[15] ^ macArray[14] ^ macArray[13] ^ macArray[12] ^ -+ macArray[9] ^ macArray[6] ^ macArray[1] ^ macArray[0]; -+ -+ crc[2] = macArray[47] ^ macArray[46] ^ macArray[44] ^ macArray[43] ^ -+ macArray[42] ^ macArray[39] ^ macArray[37] ^ macArray[34] ^ -+ macArray[33] ^ macArray[29] ^ macArray[28] ^ macArray[25] ^ -+ macArray[24] ^ macArray[22] ^ macArray[17] ^ macArray[15] ^ -+ macArray[13] ^ macArray[12] ^ macArray[10] ^ macArray[8] ^ -+ macArray[6] ^ macArray[2] ^ macArray[1] ^ macArray[0]; -+ -+ crc[3] = macArray[47] ^ macArray[45] ^ macArray[44] ^ macArray[43] ^ -+ macArray[40] ^ macArray[38] ^ macArray[35] ^ macArray[34] ^ -+ macArray[30] ^ macArray[29] ^ macArray[26] ^ macArray[25] ^ -+ macArray[23] ^ macArray[18] ^ macArray[16] ^ macArray[14] ^ -+ macArray[13] ^ macArray[11] ^ macArray[9] ^ macArray[7] ^ -+ macArray[3] ^ macArray[2] ^ macArray[1]; -+ -+ crc[4] = macArray[46] ^ macArray[45] ^ macArray[44] ^ macArray[41] ^ -+ macArray[39] ^ macArray[36] ^ macArray[35] ^ macArray[31] ^ -+ macArray[30] ^ macArray[27] ^ macArray[26] ^ macArray[24] ^ -+ macArray[19] ^ macArray[17] ^ macArray[15] ^ macArray[14] ^ -+ macArray[12] ^ macArray[10] ^ macArray[8] ^ macArray[4] ^ -+ macArray[3] ^ macArray[2]; -+ -+ crc[5] = macArray[47] ^ macArray[46] ^ macArray[45] ^ macArray[42] ^ -+ macArray[40] ^ macArray[37] ^ macArray[36] ^ macArray[32] ^ -+ macArray[31] ^ macArray[28] ^ macArray[27] ^ macArray[25] ^ -+ macArray[20] ^ macArray[18] ^ macArray[16] ^ macArray[15] ^ -+ macArray[13] ^ macArray[11] ^ macArray[9] ^ macArray[5] ^ -+ macArray[4] ^ macArray[3]; -+ -+ crc[6] = macArray[47] ^ macArray[46] ^ macArray[43] ^ macArray[41] ^ -+ macArray[38] ^ macArray[37] ^ macArray[33] ^ macArray[32] ^ -+ macArray[29] ^ macArray[28] ^ macArray[26] ^ macArray[21] ^ -+ macArray[19] ^ macArray[17] ^ macArray[16] ^ macArray[14] ^ -+ macArray[12] ^ macArray[10] ^ macArray[6] ^ macArray[5] ^ -+ macArray[4]; -+ -+ crc[7] = macArray[47] ^ macArray[44] ^ macArray[42] ^ macArray[39] ^ -+ macArray[38] ^ macArray[34] ^ macArray[33] ^ macArray[30] ^ -+ macArray[29] ^ macArray[27] ^ macArray[22] ^ macArray[20] ^ -+ macArray[18] ^ macArray[17] ^ macArray[15] ^ macArray[13] ^ -+ macArray[11] ^ macArray[7] ^ macArray[6] ^ macArray[5]; -+ -+ for(i=0; i<8; i++) -+ crcResult = crcResult | (crc[i] << i); -+ -+ return crcResult; -+} -+/******************************************************************************* -+* mvEthMcastAddrSet - Multicast address settings. -+* -+* DESCRIPTION: -+* This API controls the MV device MAC multicast support. -+* The MV device supports multicast using two tables: -+* 1) Special Multicast Table for MAC addresses of the form -+* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). -+* The MAC DA[7:0] bits are used as a pointer to the Special Multicast -+* Table entries in the DA-Filter table. -+* In this case, the function calls ethPortSmcAddr() routine to set the -+* Special Multicast Table. -+* 2) Other Multicast Table for multicast of another type. A CRC-8bit -+* is used as an index to the Other Multicast Table entries in the -+* DA-Filter table. -+* In this case, the function calculates the CRC-8bit value and calls -+* ethPortOmcAddr() routine to set the Other Multicast Table. -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet port handler. -+* MV_U8* pAddr - Address to be set -+* int queue - RX queue to capture all packets with this -+* Multicast MAC address. -+* -1 means delete this Multicast address. -+* -+* RETURN: MV_STATUS -+* MV_TRUE - Success, Other - Failure -+* -+*******************************************************************************/ -+MV_STATUS mvEthMcastAddrSet(void* pPortHndl, MV_U8 *pAddr, int queue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ unsigned char crcResult = 0; -+ -+ if(queue >= MV_ETH_RX_Q_NUM) -+ { -+ mvOsPrintf("ethPort %d: RX queue #%d is out of range\n", -+ pPortCtrl->portNo, queue); -+ return MV_BAD_PARAM; -+ } -+ -+ if((pAddr[0] == 0x01) && -+ (pAddr[1] == 0x00) && -+ (pAddr[2] == 0x5E) && -+ (pAddr[3] == 0x00) && -+ (pAddr[4] == 0x00)) -+ { -+ ethSetSpecialMcastAddr(pPortCtrl->portNo, pAddr[5], queue); -+ } -+ else -+ { -+ crcResult = mvEthMcastCrc8Get(pAddr); -+ -+ /* Check Add counter for this CRC value */ -+ if(queue == -1) -+ { -+ if(pPortCtrl->mcastCount[crcResult] == 0) -+ { -+ mvOsPrintf("ethPort #%d: No valid Mcast for crc8=0x%02x\n", -+ pPortCtrl->portNo, (unsigned)crcResult); -+ return MV_NO_SUCH; -+ } -+ -+ pPortCtrl->mcastCount[crcResult]--; -+ if(pPortCtrl->mcastCount[crcResult] != 0) -+ { -+ mvOsPrintf("ethPort #%d: After delete there are %d valid Mcast for crc8=0x%02x\n", -+ pPortCtrl->portNo, pPortCtrl->mcastCount[crcResult], -+ (unsigned)crcResult); -+ return MV_NO_CHANGE; -+ } -+ } -+ else -+ { -+ pPortCtrl->mcastCount[crcResult]++; -+ if(pPortCtrl->mcastCount[crcResult] > 1) -+ { -+ mvOsPrintf("ethPort #%d: Valid Mcast for crc8=0x%02x already exists\n", -+ pPortCtrl->portNo, (unsigned)crcResult); -+ return MV_NO_CHANGE; -+ } -+ } -+ ethSetOtherMcastAddr(pPortCtrl->portNo, crcResult, queue); -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* ethSetUcastTable - Unicast address settings. -+* -+* DESCRIPTION: -+* Set all entries in the Unicast MAC Table queue==-1 means reject all -+* INPUT: -+* -+* RETURN: -+* -+*******************************************************************************/ -+static void ethSetUcastTable(int portNo, int queue) -+{ -+ int offset; -+ MV_U32 regValue; -+ -+ if(queue == -1) -+ { -+ regValue = 0; -+ } -+ else -+ { -+ regValue = (((0x01 | (queue<<1)) << 0) | -+ ((0x01 | (queue<<1)) << 8) | -+ ((0x01 | (queue<<1)) << 16) | -+ ((0x01 | (queue<<1)) << 24)); -+ } -+ -+ for (offset=0; offset<=0xC; offset+=4) -+ MV_REG_WRITE((ETH_DA_FILTER_UCAST_BASE(portNo) + offset), regValue); -+} -+ -+/******************************************************************************* -+* mvEthSetSpecialMcastTable - Special Multicast address settings. -+* -+* DESCRIPTION: -+* Set all entries to the Special Multicast MAC Table. queue==-1 means reject all -+* INPUT: -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_VOID mvEthSetSpecialMcastTable(int portNo, int queue) -+{ -+ int offset; -+ MV_U32 regValue; -+ -+ if(queue == -1) -+ { -+ regValue = 0; -+ } -+ else -+ { -+ regValue = (((0x01 | (queue<<1)) << 0) | -+ ((0x01 | (queue<<1)) << 8) | -+ ((0x01 | (queue<<1)) << 16) | -+ ((0x01 | (queue<<1)) << 24)); -+ } -+ -+ for (offset=0; offset<=0xFC; offset+=4) -+ { -+ MV_REG_WRITE((ETH_DA_FILTER_SPEC_MCAST_BASE(portNo) + -+ offset), regValue); -+ } -+} -+ -+/******************************************************************************* -+* mvEthSetOtherMcastTable - Other Multicast address settings. -+* -+* DESCRIPTION: -+* Set all entries to the Other Multicast MAC Table. queue==-1 means reject all -+* INPUT: -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_VOID mvEthSetOtherMcastTable(int portNo, int queue) -+{ -+ int offset; -+ MV_U32 regValue; -+ -+ if(queue == -1) -+ { -+ regValue = 0; -+ } -+ else -+ { -+ regValue = (((0x01 | (queue<<1)) << 0) | -+ ((0x01 | (queue<<1)) << 8) | -+ ((0x01 | (queue<<1)) << 16) | -+ ((0x01 | (queue<<1)) << 24)); -+ } -+ -+ for (offset=0; offset<=0xFC; offset+=4) -+ { -+ MV_REG_WRITE((ETH_DA_FILTER_OTH_MCAST_BASE(portNo) + -+ offset), regValue); -+ } -+} -+ -+/******************************************************************************* -+* ethSetUcastAddr - This function Set the port unicast address table -+* -+* DESCRIPTION: -+* This function locates the proper entry in the Unicast table for the -+* specified MAC nibble and sets its properties according to function -+* parameters. -+* -+* INPUT: -+* int ethPortNum - Port number. -+* MV_U8 lastNibble - Unicast MAC Address last nibble. -+* int queue - Rx queue number for this MAC address. -+* value "-1" means remove address -+* -+* OUTPUT: -+* This function add/removes MAC addresses from the port unicast address -+* table. -+* -+* RETURN: -+* MV_TRUE is output succeeded. -+* MV_FALSE if option parameter is invalid. -+* -+*******************************************************************************/ -+static MV_BOOL ethSetUcastAddr(int portNo, MV_U8 lastNibble, int queue) -+{ -+ unsigned int unicastReg; -+ unsigned int tblOffset; -+ unsigned int regOffset; -+ -+ /* Locate the Unicast table entry */ -+ lastNibble = (0xf & lastNibble); -+ tblOffset = (lastNibble / 4) * 4; /* Register offset from unicast table base*/ -+ regOffset = lastNibble % 4; /* Entry offset within the above register */ -+ -+ -+ unicastReg = MV_REG_READ( (ETH_DA_FILTER_UCAST_BASE(portNo) + -+ tblOffset)); -+ -+ -+ if(queue == -1) -+ { -+ /* Clear accepts frame bit at specified unicast DA table entry */ -+ unicastReg &= ~(0xFF << (8*regOffset)); -+ } -+ else -+ { -+ unicastReg &= ~(0xFF << (8*regOffset)); -+ unicastReg |= ((0x01 | (queue<<1)) << (8*regOffset)); -+ } -+ MV_REG_WRITE( (ETH_DA_FILTER_UCAST_BASE(portNo) + tblOffset), -+ unicastReg); -+ -+ return MV_TRUE; -+} -+ -+/******************************************************************************* -+* ethSetSpecialMcastAddr - Special Multicast address settings. -+* -+* DESCRIPTION: -+* This routine controls the MV device special MAC multicast support. -+* The Special Multicast Table for MAC addresses supports MAC of the form -+* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). -+* The MAC DA[7:0] bits are used as a pointer to the Special Multicast -+* Table entries in the DA-Filter table. -+* This function set the Special Multicast Table appropriate entry -+* according to the argument given. -+* -+* INPUT: -+* int ethPortNum Port number. -+* unsigned char mcByte Multicast addr last byte (MAC DA[7:0] bits). -+* int queue Rx queue number for this MAC address. -+* int option 0 = Add, 1 = remove address. -+* -+* OUTPUT: -+* See description. -+* -+* RETURN: -+* MV_TRUE is output succeeded. -+* MV_FALSE if option parameter is invalid. -+* -+*******************************************************************************/ -+static MV_BOOL ethSetSpecialMcastAddr(int ethPortNum, MV_U8 lastByte, int queue) -+{ -+ unsigned int smcTableReg; -+ unsigned int tblOffset; -+ unsigned int regOffset; -+ -+ /* Locate the SMC table entry */ -+ tblOffset = (lastByte / 4); /* Register offset from SMC table base */ -+ regOffset = lastByte % 4; /* Entry offset within the above register */ -+ -+ smcTableReg = MV_REG_READ((ETH_DA_FILTER_SPEC_MCAST_BASE(ethPortNum) + tblOffset*4)); -+ -+ if(queue == -1) -+ { -+ /* Clear accepts frame bit at specified Special DA table entry */ -+ smcTableReg &= ~(0xFF << (8 * regOffset)); -+ } -+ else -+ { -+ smcTableReg &= ~(0xFF << (8 * regOffset)); -+ smcTableReg |= ((0x01 | (queue<<1)) << (8 * regOffset)); -+ } -+ MV_REG_WRITE((ETH_DA_FILTER_SPEC_MCAST_BASE(ethPortNum) + -+ tblOffset*4), smcTableReg); -+ -+ return MV_TRUE; -+} -+ -+/******************************************************************************* -+* ethSetOtherMcastAddr - Multicast address settings. -+* -+* DESCRIPTION: -+* This routine controls the MV device Other MAC multicast support. -+* The Other Multicast Table is used for multicast of another type. -+* A CRC-8bit is used as an index to the Other Multicast Table entries -+* in the DA-Filter table. -+* The function gets the CRC-8bit value from the calling routine and -+* set the Other Multicast Table appropriate entry according to the -+* CRC-8 argument given. -+* -+* INPUT: -+* int ethPortNum Port number. -+* MV_U8 crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1). -+* int queue Rx queue number for this MAC address. -+* -+* OUTPUT: -+* See description. -+* -+* RETURN: -+* MV_TRUE is output succeeded. -+* MV_FALSE if option parameter is invalid. -+* -+*******************************************************************************/ -+static MV_BOOL ethSetOtherMcastAddr(int ethPortNum, MV_U8 crc8, int queue) -+{ -+ unsigned int omcTableReg; -+ unsigned int tblOffset; -+ unsigned int regOffset; -+ -+ /* Locate the OMC table entry */ -+ tblOffset = (crc8 / 4) * 4; /* Register offset from OMC table base */ -+ regOffset = crc8 % 4; /* Entry offset within the above register */ -+ -+ omcTableReg = MV_REG_READ( -+ (ETH_DA_FILTER_OTH_MCAST_BASE(ethPortNum) + tblOffset)); -+ -+ if(queue == -1) -+ { -+ /* Clear accepts frame bit at specified Other DA table entry */ -+ omcTableReg &= ~(0xFF << (8 * regOffset)); -+ } -+ else -+ { -+ omcTableReg &= ~(0xFF << (8 * regOffset)); -+ omcTableReg |= ((0x01 | (queue<<1)) << (8 * regOffset)); -+ } -+ -+ MV_REG_WRITE((ETH_DA_FILTER_OTH_MCAST_BASE(ethPortNum) + tblOffset), -+ omcTableReg); -+ -+ return MV_TRUE; -+} -+ -+ -+/******************************************************************************/ -+/* MIB Counters functions */ -+/******************************************************************************/ -+ -+ -+/******************************************************************************* -+* mvEthMibCounterRead - Read a MIB counter -+* -+* DESCRIPTION: -+* This function reads a MIB counter of a specific ethernet port. -+* NOTE - Read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW or -+* ETH_MIB_GOOD_OCTETS_SENT_LOW counters will return 64 bits value, -+* so pHigh32 pointer should not be NULL in this case. -+* -+* INPUT: -+* int ethPortNum - Ethernet Port number. -+* unsigned int mibOffset - MIB counter offset. -+* -+* OUTPUT: -+* MV_U32* pHigh32 - pointer to place where 32 most significant bits -+* of the counter will be stored. -+* -+* RETURN: -+* 32 low sgnificant bits of MIB counter value. -+* -+*******************************************************************************/ -+MV_U32 mvEthMibCounterRead(void* pPortHandle, unsigned int mibOffset, -+ MV_U32* pHigh32) -+{ -+ int portNo; -+ MV_U32 valLow32, valHigh32; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ -+ portNo = pPortCtrl->portNo; -+ -+ valLow32 = MV_REG_READ(ETH_MIB_COUNTERS_BASE(portNo) + mibOffset); -+ -+ /* Implement FEr ETH. Erroneous Value when Reading the Upper 32-bits */ -+ /* of a 64-bit MIB Counter. */ -+ if( (mibOffset == ETH_MIB_GOOD_OCTETS_RECEIVED_LOW) || -+ (mibOffset == ETH_MIB_GOOD_OCTETS_SENT_LOW) ) -+ { -+ valHigh32 = MV_REG_READ(ETH_MIB_COUNTERS_BASE(portNo) + mibOffset + 4); -+ if(pHigh32 != NULL) -+ *pHigh32 = valHigh32; -+ } -+ return valLow32; -+} -+ -+/******************************************************************************* -+* mvEthMibCountersClear - Clear all MIB counters -+* -+* DESCRIPTION: -+* This function clears all MIB counters -+* -+* INPUT: -+* int ethPortNum - Ethernet Port number. -+* -+* -+* RETURN: void -+* -+*******************************************************************************/ -+void mvEthMibCountersClear(void* pPortHandle) -+{ -+ int i, portNo; -+ unsigned int dummy; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ -+ portNo = pPortCtrl->portNo; -+ -+ /* Perform dummy reads from MIB counters */ -+ for(i=ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i 0xFF) -+ { -+ mvOsPrintf("eth_%d: tos=0x%x is out of range\n", pPortCtrl->portNo, tos); -+ return -1; -+ } -+ regIdx = mvOsDivide(tos>>2, 10); -+ regOffs = mvOsReminder(tos>>2, 10); -+ -+ regValue = MV_REG_READ(ETH_DIFF_SERV_PRIO_REG(pPortCtrl->portNo, regIdx) ); -+ rxq = (regValue >> (regOffs*3)); -+ rxq &= 0x7; -+ -+ return rxq; -+} -+ -+/******************************************************************************* -+* mvEthTosToRxqSet - Map packets with special TOS value to special RX queue -+* -+* DESCRIPTION: -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* int tos - TOS value in the IP header of the packet -+* int rxq - RX Queue for packets with the configured TOS value -+* Negative value (-1) means no special processing for these packets, -+* so they will be processed as regular packets. -+* -+* RETURN: MV_STATUS -+*******************************************************************************/ -+MV_STATUS mvEthTosToRxqSet(void* pPortHandle, int tos, int rxq) -+{ -+ MV_U32 regValue; -+ int regIdx, regOffs; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ -+ if( (rxq < 0) || (rxq >= MV_ETH_RX_Q_NUM) ) -+ { -+ mvOsPrintf("eth_%d: RX queue #%d is out of range\n", pPortCtrl->portNo, rxq); -+ return MV_BAD_PARAM; -+ } -+ if(tos > 0xFF) -+ { -+ mvOsPrintf("eth_%d: tos=0x%x is out of range\n", pPortCtrl->portNo, tos); -+ return MV_BAD_PARAM; -+ } -+ regIdx = mvOsDivide(tos>>2, 10); -+ regOffs = mvOsReminder(tos>>2, 10); -+ -+ regValue = MV_REG_READ(ETH_DIFF_SERV_PRIO_REG(pPortCtrl->portNo, regIdx) ); -+ regValue &= ~(0x7 << (regOffs*3)); -+ regValue |= (rxq << (regOffs*3)); -+ -+ MV_REG_WRITE(ETH_DIFF_SERV_PRIO_REG(pPortCtrl->portNo, regIdx), regValue); -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthVlanPrioRxQueue - Configure RX queue to capture VLAN tagged packets with -+* special priority bits [0-2] -+* -+* DESCRIPTION: -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* int bpduQueue - Special queue to capture VLAN tagged packets with special -+* priority. -+* Negative value (-1) means no special processing for these packets, -+* so they will be processed as regular packets. -+* -+* RETURN: MV_STATUS -+* MV_OK - Success -+* MV_FAIL - Failed. -+* -+*******************************************************************************/ -+MV_STATUS mvEthVlanPrioRxQueue(void* pPortHandle, int vlanPrio, int vlanPrioQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ MV_U32 vlanPrioReg; -+ -+ if(vlanPrioQueue >= MV_ETH_RX_Q_NUM) -+ { -+ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", vlanPrioQueue); -+ return MV_BAD_PARAM; -+ } -+ if(vlanPrio >= 8) -+ { -+ mvOsPrintf("ethDrv: vlanPrio=%d is out of range\n", vlanPrio); -+ return MV_BAD_PARAM; -+ } -+ -+ vlanPrioReg = MV_REG_READ(ETH_VLAN_TAG_TO_PRIO_REG(pPortCtrl->portNo)); -+ vlanPrioReg &= ~(0x7 << (vlanPrio*3)); -+ vlanPrioReg |= (vlanPrioQueue << (vlanPrio*3)); -+ MV_REG_WRITE(ETH_VLAN_TAG_TO_PRIO_REG(pPortCtrl->portNo), vlanPrioReg); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvEthBpduRxQueue - Configure RX queue to capture BPDU packets. -+* -+* DESCRIPTION: -+* This function defines processing of BPDU packets. -+* BPDU packets can be accepted and captured to one of RX queues -+* or can be processing as regular Multicast packets. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* int bpduQueue - Special queue to capture BPDU packets (DA is equal to -+* 01-80-C2-00-00-00 through 01-80-C2-00-00-FF, -+* except for the Flow-Control Pause packets). -+* Negative value (-1) means no special processing for BPDU, -+* packets so they will be processed as regular Multicast packets. -+* -+* RETURN: MV_STATUS -+* MV_OK - Success -+* MV_FAIL - Failed. -+* -+*******************************************************************************/ -+MV_STATUS mvEthBpduRxQueue(void* pPortHandle, int bpduQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ MV_U32 portCfgReg; -+ MV_U32 portCfgExtReg; -+ -+ if(bpduQueue >= MV_ETH_RX_Q_NUM) -+ { -+ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", bpduQueue); -+ return MV_BAD_PARAM; -+ } -+ -+ portCfgExtReg = MV_REG_READ(ETH_PORT_CONFIG_EXTEND_REG(pPortCtrl->portNo)); -+ -+ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); -+ if(bpduQueue >= 0) -+ { -+ pPortCtrl->portConfig.rxBpduQ = bpduQueue; -+ -+ portCfgReg &= ~ETH_DEF_RX_BPDU_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_BPDU_QUEUE_MASK(pPortCtrl->portConfig.rxBpduQ); -+ -+ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); -+ -+ portCfgExtReg |= ETH_CAPTURE_SPAN_BPDU_ENABLE_MASK; -+ } -+ else -+ { -+ pPortCtrl->portConfig.rxBpduQ = -1; -+ /* no special processing for BPDU packets */ -+ portCfgExtReg &= (~ETH_CAPTURE_SPAN_BPDU_ENABLE_MASK); -+ } -+ -+ MV_REG_WRITE(ETH_PORT_CONFIG_EXTEND_REG(pPortCtrl->portNo), portCfgExtReg); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvEthArpRxQueue - Configure RX queue to capture ARP packets. -+* -+* DESCRIPTION: -+* This function defines processing of ARP (type=0x0806) packets. -+* ARP packets can be accepted and captured to one of RX queues -+* or can be processed as other Broadcast packets. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* int arpQueue - Special queue to capture ARP packets (type=0x806). -+* Negative value (-1) means discard ARP packets -+* -+* RETURN: MV_STATUS -+* MV_OK - Success -+* MV_FAIL - Failed. -+* -+*******************************************************************************/ -+MV_STATUS mvEthArpRxQueue(void* pPortHandle, int arpQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ MV_U32 portCfgReg; -+ -+ if(arpQueue >= MV_ETH_RX_Q_NUM) -+ { -+ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", arpQueue); -+ return MV_BAD_PARAM; -+ } -+ -+ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); -+ -+ if(arpQueue >= 0) -+ { -+ pPortCtrl->portConfig.rxArpQ = arpQueue; -+ portCfgReg &= ~ETH_DEF_RX_ARP_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_ARP_QUEUE_MASK(pPortCtrl->portConfig.rxArpQ); -+ -+ portCfgReg &= (~ETH_REJECT_ARP_BCAST_MASK); -+ } -+ else -+ { -+ pPortCtrl->portConfig.rxArpQ = -1; -+ portCfgReg |= ETH_REJECT_ARP_BCAST_MASK; -+ } -+ -+ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvEthTcpRxQueue - Configure RX queue to capture TCP packets. -+* -+* DESCRIPTION: -+* This function defines processing of TCP packets. -+* TCP packets can be accepted and captured to one of RX queues -+* or can be processed as regular Unicast packets. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* int tcpQueue - Special queue to capture TCP packets. Value "-1" -+* means no special processing for TCP packets, -+* so they will be processed as regular -+* -+* RETURN: MV_STATUS -+* MV_OK - Success -+* MV_FAIL - Failed. -+* -+*******************************************************************************/ -+MV_STATUS mvEthTcpRxQueue(void* pPortHandle, int tcpQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ MV_U32 portCfgReg; -+ -+ if(tcpQueue >= MV_ETH_RX_Q_NUM) -+ { -+ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", tcpQueue); -+ return MV_BAD_PARAM; -+ } -+ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); -+ -+ if(tcpQueue >= 0) -+ { -+ pPortCtrl->portConfig.rxTcpQ = tcpQueue; -+ portCfgReg &= ~ETH_DEF_RX_TCP_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_TCP_QUEUE_MASK(pPortCtrl->portConfig.rxTcpQ); -+ -+ portCfgReg |= ETH_CAPTURE_TCP_FRAMES_ENABLE_MASK; -+ } -+ else -+ { -+ pPortCtrl->portConfig.rxTcpQ = -1; -+ portCfgReg &= (~ETH_CAPTURE_TCP_FRAMES_ENABLE_MASK); -+ } -+ -+ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvEthUdpRxQueue - Configure RX queue to capture UDP packets. -+* -+* DESCRIPTION: -+* This function defines processing of UDP packets. -+* TCP packets can be accepted and captured to one of RX queues -+* or can be processed as regular Unicast packets. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* int udpQueue - Special queue to capture UDP packets. Value "-1" -+* means no special processing for UDP packets, -+* so they will be processed as regular -+* -+* RETURN: MV_STATUS -+* MV_OK - Success -+* MV_FAIL - Failed. -+* -+*******************************************************************************/ -+MV_STATUS mvEthUdpRxQueue(void* pPortHandle, int udpQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ MV_U32 portCfgReg; -+ -+ if(udpQueue >= MV_ETH_RX_Q_NUM) -+ { -+ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", udpQueue); -+ return MV_BAD_PARAM; -+ } -+ -+ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); -+ -+ if(udpQueue >= 0) -+ { -+ pPortCtrl->portConfig.rxUdpQ = udpQueue; -+ portCfgReg &= ~ETH_DEF_RX_UDP_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_UDP_QUEUE_MASK(pPortCtrl->portConfig.rxUdpQ); -+ -+ portCfgReg |= ETH_CAPTURE_UDP_FRAMES_ENABLE_MASK; -+ } -+ else -+ { -+ pPortCtrl->portConfig.rxUdpQ = -1; -+ portCfgReg &= ~ETH_CAPTURE_UDP_FRAMES_ENABLE_MASK; -+ } -+ -+ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************/ -+/* Speed, Duplex, FlowControl routines */ -+/******************************************************************************/ -+ -+/******************************************************************************* -+* mvEthSpeedDuplexSet - Set Speed and Duplex of the port. -+* -+* DESCRIPTION: -+* This function configure the port to work with desirable Duplex and Speed. -+* Changing of these parameters are allowed only when port is disabled. -+* This function disable the port if was enabled, change duplex and speed -+* and, enable the port back if needed. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* ETH_PORT_SPEED speed - Speed of the port. -+* ETH_PORT_SPEED duplex - Duplex of the port. -+* -+* RETURN: MV_STATUS -+* MV_OK - Success -+* MV_OUT_OF_RANGE - Failed. Port is out of valid range -+* MV_NOT_FOUND - Failed. Port is not initialized. -+* MV_BAD_PARAM - Input parameters (speed/duplex) in conflict. -+* MV_BAD_VALUE - Value of one of input parameters (speed, duplex) -+* is not valid -+* -+*******************************************************************************/ -+MV_STATUS mvEthSpeedDuplexSet(void* pPortHandle, MV_ETH_PORT_SPEED speed, -+ MV_ETH_PORT_DUPLEX duplex) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ int port = pPortCtrl->portNo; -+ MV_U32 portSerialCtrlReg; -+ -+ if( (port < 0) || (port >= (int)mvCtrlEthMaxPortGet()) ) -+ return MV_OUT_OF_RANGE; -+ -+ pPortCtrl = ethPortCtrl[port]; -+ if(pPortCtrl == NULL) -+ return MV_NOT_FOUND; -+ -+ /* Check validity */ -+ if( (speed == MV_ETH_SPEED_1000) && (duplex == MV_ETH_DUPLEX_HALF) ) -+ return MV_BAD_PARAM; -+ -+ portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port)); -+ /* Set Speed */ -+ switch(speed) -+ { -+ case MV_ETH_SPEED_AN: -+ portSerialCtrlReg &= ~ETH_DISABLE_SPEED_AUTO_NEG_MASK; -+ break; -+ -+ case MV_ETH_SPEED_10: -+ portSerialCtrlReg |= ETH_DISABLE_SPEED_AUTO_NEG_MASK; -+ portSerialCtrlReg &= ~ETH_SET_GMII_SPEED_1000_MASK; -+ portSerialCtrlReg &= ~ETH_SET_MII_SPEED_100_MASK; -+ break; -+ -+ case MV_ETH_SPEED_100: -+ portSerialCtrlReg |= ETH_DISABLE_SPEED_AUTO_NEG_MASK; -+ portSerialCtrlReg &= ~ETH_SET_GMII_SPEED_1000_MASK; -+ portSerialCtrlReg |= ETH_SET_MII_SPEED_100_MASK; -+ break; -+ -+ case MV_ETH_SPEED_1000: -+ portSerialCtrlReg |= ETH_DISABLE_SPEED_AUTO_NEG_MASK; -+ portSerialCtrlReg |= ETH_SET_GMII_SPEED_1000_MASK; -+ break; -+ -+ default: -+ mvOsPrintf("ethDrv: Unexpected Speed value %d\n", speed); -+ return MV_BAD_VALUE; -+ } -+ /* Set duplex */ -+ switch(duplex) -+ { -+ case MV_ETH_DUPLEX_AN: -+ portSerialCtrlReg &= ~ETH_DISABLE_DUPLEX_AUTO_NEG_MASK; -+ break; -+ -+ case MV_ETH_DUPLEX_HALF: -+ portSerialCtrlReg |= ETH_DISABLE_DUPLEX_AUTO_NEG_MASK; -+ portSerialCtrlReg &= ~ETH_SET_FULL_DUPLEX_MASK; -+ break; -+ -+ case MV_ETH_DUPLEX_FULL: -+ portSerialCtrlReg |= ETH_DISABLE_DUPLEX_AUTO_NEG_MASK; -+ portSerialCtrlReg |= ETH_SET_FULL_DUPLEX_MASK; -+ break; -+ -+ default: -+ mvOsPrintf("ethDrv: Unexpected Duplex value %d\n", duplex); -+ return MV_BAD_VALUE; -+ } -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(port), portSerialCtrlReg); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthFlowCtrlSet - Set Flow Control of the port. -+* -+* DESCRIPTION: -+* This function configure the port to work with desirable Duplex and -+* Speed. Changing of these parameters are allowed only when port is -+* disabled. This function disable the port if was enabled, change -+* duplex and speed and, enable the port back if needed. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* MV_ETH_PORT_FC flowControl - Flow control of the port. -+* -+* RETURN: MV_STATUS -+* MV_OK - Success -+* MV_OUT_OF_RANGE - Failed. Port is out of valid range -+* MV_NOT_FOUND - Failed. Port is not initialized. -+* MV_BAD_VALUE - Value flowControl parameters is not valid -+* -+*******************************************************************************/ -+MV_STATUS mvEthFlowCtrlSet(void* pPortHandle, MV_ETH_PORT_FC flowControl) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ int port = pPortCtrl->portNo; -+ MV_U32 portSerialCtrlReg; -+ -+ if( (port < 0) || (port >= (int)mvCtrlEthMaxPortGet() ) ) -+ return MV_OUT_OF_RANGE; -+ -+ pPortCtrl = ethPortCtrl[port]; -+ if(pPortCtrl == NULL) -+ return MV_NOT_FOUND; -+ -+ portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port)); -+ switch(flowControl) -+ { -+ case MV_ETH_FC_AN_ADV_DIS: -+ portSerialCtrlReg &= ~ETH_DISABLE_FC_AUTO_NEG_MASK; -+ portSerialCtrlReg &= ~ETH_ADVERTISE_SYM_FC_MASK; -+ break; -+ -+ case MV_ETH_FC_AN_ADV_SYM: -+ portSerialCtrlReg &= ~ETH_DISABLE_FC_AUTO_NEG_MASK; -+ portSerialCtrlReg |= ETH_ADVERTISE_SYM_FC_MASK; -+ break; -+ -+ case MV_ETH_FC_DISABLE: -+ portSerialCtrlReg |= ETH_DISABLE_FC_AUTO_NEG_MASK; -+ portSerialCtrlReg &= ~ETH_SET_FLOW_CTRL_MASK; -+ break; -+ -+ case MV_ETH_FC_ENABLE: -+ portSerialCtrlReg |= ETH_DISABLE_FC_AUTO_NEG_MASK; -+ portSerialCtrlReg |= ETH_SET_FLOW_CTRL_MASK; -+ break; -+ -+ default: -+ mvOsPrintf("ethDrv: Unexpected FlowControl value %d\n", flowControl); -+ return MV_BAD_VALUE; -+ } -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(port), portSerialCtrlReg); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthHeaderModeSet - Set port header mode. -+* -+* DESCRIPTION: -+* This function configures the port to work in Marvell-Header mode. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* MV_ETH_HEADER_MODE headerMode - The header mode to set the port in. -+* -+* RETURN: MV_STATUS -+* MV_OK - Success -+* MV_NOT_SUPPORTED- Feature not supported. -+* MV_OUT_OF_RANGE - Failed. Port is out of valid range -+* MV_NOT_FOUND - Failed. Port is not initialized. -+* MV_BAD_VALUE - Value of headerMode or numRxQueue parameter is not valid. -+* -+*******************************************************************************/ -+MV_STATUS mvEthHeaderModeSet(void* pPortHandle, MV_ETH_HEADER_MODE headerMode) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ int port = pPortCtrl->portNo; -+ MV_U32 mvHeaderReg; -+ MV_U32 numRxQ = MV_ETH_RX_Q_NUM; -+ -+ if((port < 0) || (port >= mvCtrlEthMaxPortGet())) -+ return MV_OUT_OF_RANGE; -+ -+ pPortCtrl = ethPortCtrl[port]; -+ if(pPortCtrl == NULL) -+ return MV_NOT_FOUND; -+ -+ mvHeaderReg = MV_REG_READ(ETH_PORT_MARVELL_HEADER_REG(port)); -+ /* Disable header mode. */ -+ mvHeaderReg &= ~ETH_MVHDR_EN_MASK; -+ -+ if(headerMode != MV_ETH_DISABLE_HEADER_MODE) -+ { -+ /* Enable Header mode. */ -+ mvHeaderReg |= ETH_MVHDR_EN_MASK; -+ -+ /* Clear DA-Prefix & MHMask fields.*/ -+ mvHeaderReg &= ~(ETH_MVHDR_DAPREFIX_MASK | ETH_MVHDR_MHMASK_MASK); -+ -+ if(numRxQ > 1) -+ { -+ switch (headerMode) -+ { -+ case(MV_ETH_ENABLE_HEADER_MODE_PRI_2_1): -+ mvHeaderReg |= ETH_MVHDR_DAPREFIX_PRI_1_2; -+ break; -+ case(MV_ETH_ENABLE_HEADER_MODE_PRI_DBNUM): -+ mvHeaderReg |= ETH_MVHDR_DAPREFIX_DBNUM_PRI; -+ break; -+ case(MV_ETH_ENABLE_HEADER_MODE_PRI_SPID): -+ mvHeaderReg |= ETH_MVHDR_DAPREFIX_SPID_PRI; -+ break; -+ default: -+ break; -+ } -+ -+ switch (numRxQ) -+ { -+ case (4): -+ mvHeaderReg |= ETH_MVHDR_MHMASK_4_QUEUE; -+ break; -+ case (8): -+ mvHeaderReg |= ETH_MVHDR_MHMASK_8_QUEUE; -+ break; -+ default: -+ break; -+ } -+ } -+ } -+ -+ MV_REG_WRITE(ETH_PORT_MARVELL_HEADER_REG(port), mvHeaderReg); -+ -+ return MV_OK; -+} -+ -+#if (MV_ETH_VERSION >= 4) -+/******************************************************************************* -+* mvEthEjpModeSet - Enable / Disable EJP policy for TX. -+* -+* DESCRIPTION: -+* This function -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* MV_BOOL TRUE - enable EJP mode -+* FALSE - disable EJP mode -+* -+* OUTPUT: MV_STATUS -+* MV_OK - Success -+* Other - Failure -+* -+* RETURN: None. -+* -+*******************************************************************************/ -+MV_STATUS mvEthEjpModeSet(void* pPortHandle, int mode) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ int port = pPortCtrl->portNo; -+ -+ if((port < 0) || (port >= mvCtrlEthMaxPortGet())) -+ return MV_OUT_OF_RANGE; -+ -+ pPortCtrl = ethPortCtrl[port]; -+ if(pPortCtrl == NULL) -+ return MV_NOT_FOUND; -+ -+ pPortCtrl->portConfig.ejpMode = mode; -+ if(mode) -+ { -+ /* EJP enabled */ -+ MV_REG_WRITE(ETH_TXQ_CMD_1_REG(port), ETH_TX_EJP_ENABLE_MASK); -+ } -+ else -+ { -+ /* EJP disabled */ -+ MV_REG_WRITE(ETH_TXQ_CMD_1_REG(port), 0); -+ } -+ mvOsPrintf("eth_%d: EJP %s - ETH_TXQ_CMD_1_REG: 0x%x = 0x%08x\n", -+ port, mode ? "Enabled" : "Disabled", ETH_TXQ_CMD_1_REG(port), -+ MV_REG_READ(ETH_TXQ_CMD_1_REG(port))); -+ -+ return MV_OK; -+} -+#endif /* MV_ETH_VERSION >= 4 */ -+ -+/******************************************************************************* -+* mvEthStatusGet - Get major properties of the port . -+* -+* DESCRIPTION: -+* This function get major properties of the port (link, speed, duplex, -+* flowControl, etc) and return them using the single structure. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* -+* OUTPUT: -+* MV_ETH_PORT_STATUS* pStatus - Pointer to structure, were port status -+* will be placed. -+* -+* RETURN: None. -+* -+*******************************************************************************/ -+void mvEthStatusGet(void* pPortHandle, MV_ETH_PORT_STATUS* pStatus) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ int port = pPortCtrl->portNo; -+ -+ MV_U32 regValue; -+ -+ regValue = MV_REG_READ( ETH_PORT_STATUS_REG(port) ); -+ -+ if(regValue & ETH_GMII_SPEED_1000_MASK) -+ pStatus->speed = MV_ETH_SPEED_1000; -+ else if(regValue & ETH_MII_SPEED_100_MASK) -+ pStatus->speed = MV_ETH_SPEED_100; -+ else -+ pStatus->speed = MV_ETH_SPEED_10; -+ -+ if(regValue & ETH_LINK_UP_MASK) -+ pStatus->isLinkUp = MV_TRUE; -+ else -+ pStatus->isLinkUp = MV_FALSE; -+ -+ if(regValue & ETH_FULL_DUPLEX_MASK) -+ pStatus->duplex = MV_ETH_DUPLEX_FULL; -+ else -+ pStatus->duplex = MV_ETH_DUPLEX_HALF; -+ -+ -+ if(regValue & ETH_ENABLE_RCV_FLOW_CTRL_MASK) -+ pStatus->flowControl = MV_ETH_FC_ENABLE; -+ else -+ pStatus->flowControl = MV_ETH_FC_DISABLE; -+} -+ -+ -+/******************************************************************************/ -+/* PHY Control Functions */ -+/******************************************************************************/ -+ -+ -+/******************************************************************************* -+* mvEthPhyAddrSet - Set the ethernet port PHY address. -+* -+* DESCRIPTION: -+* This routine set the ethernet port PHY address according to given -+* parameter. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* int phyAddr - PHY address -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+void mvEthPhyAddrSet(void* pPortHandle, int phyAddr) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ int port = pPortCtrl->portNo; -+ unsigned int regData; -+ -+ regData = MV_REG_READ(ETH_PHY_ADDR_REG(port)); -+ -+ regData &= ~ETH_PHY_ADDR_MASK; -+ regData |= phyAddr; -+ -+ MV_REG_WRITE(ETH_PHY_ADDR_REG(port), regData); -+ -+ return; -+} -+ -+/******************************************************************************* -+* mvEthPhyAddrGet - Get the ethernet port PHY address. -+* -+* DESCRIPTION: -+* This routine returns the given ethernet port PHY address. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* -+* -+* RETURN: int - PHY address. -+* -+*******************************************************************************/ -+int mvEthPhyAddrGet(void* pPortHandle) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ int port = pPortCtrl->portNo; -+ unsigned int regData; -+ -+ regData = MV_REG_READ(ETH_PHY_ADDR_REG(port)); -+ -+ return ((regData >> (5 * port)) & 0x1f); -+} -+ -+/******************************************************************************/ -+/* Descriptor handling Functions */ -+/******************************************************************************/ -+ -+/******************************************************************************* -+* etherInitRxDescRing - Curve a Rx chain desc list and buffer in memory. -+* -+* DESCRIPTION: -+* This function prepares a Rx chained list of descriptors and packet -+* buffers in a form of a ring. The routine must be called after port -+* initialization routine and before port start routine. -+* The Ethernet SDMA engine uses CPU bus addresses to access the various -+* devices in the system (i.e. DRAM). This function uses the ethernet -+* struct 'virtual to physical' routine (set by the user) to set the ring -+* with physical addresses. -+* -+* INPUT: -+* ETH_QUEUE_CTRL *pEthPortCtrl Ethernet Port Control srtuct. -+* int rxQueue Number of Rx queue. -+* int rxDescNum Number of Rx descriptors -+* MV_U8* rxDescBaseAddr Rx descriptors memory area base addr. -+* -+* OUTPUT: -+* The routine updates the Ethernet port control struct with information -+* regarding the Rx descriptors and buffers. -+* -+* RETURN: None -+* -+*******************************************************************************/ -+static void ethInitRxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue) -+{ -+ ETH_RX_DESC *pRxDescBase, *pRxDesc, *pRxPrevDesc; -+ int ix, rxDescNum = pPortCtrl->rxQueueConfig[queue].descrNum; -+ ETH_QUEUE_CTRL *pQueueCtrl = &pPortCtrl->rxQueue[queue]; -+ -+ /* Make sure descriptor address is cache line size aligned */ -+ pRxDescBase = (ETH_RX_DESC*)MV_ALIGN_UP((MV_ULONG)pQueueCtrl->descBuf.bufVirtPtr, -+ CPU_D_CACHE_LINE_SIZE); -+ -+ pRxDesc = (ETH_RX_DESC*)pRxDescBase; -+ pRxPrevDesc = pRxDesc; -+ -+ /* initialize the Rx descriptors ring */ -+ for (ix=0; ixbufSize = 0x0; -+ pRxDesc->byteCnt = 0x0; -+ pRxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; -+ pRxDesc->bufPtr = 0x0; -+ pRxDesc->returnInfo = 0x0; -+ pRxPrevDesc = pRxDesc; -+ if(ix == (rxDescNum-1)) -+ { -+ /* Closing Rx descriptors ring */ -+ pRxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pRxDescBase); -+ } -+ else -+ { -+ pRxDesc = (ETH_RX_DESC*)((MV_ULONG)pRxDesc + ETH_RX_DESC_ALIGNED_SIZE); -+ pRxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pRxDesc); -+ } -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxPrevDesc); -+ } -+ -+ pQueueCtrl->pCurrentDescr = pRxDescBase; -+ pQueueCtrl->pUsedDescr = pRxDescBase; -+ -+ pQueueCtrl->pFirstDescr = pRxDescBase; -+ pQueueCtrl->pLastDescr = pRxDesc; -+ pQueueCtrl->resource = 0; -+} -+ -+void ethResetRxDescRing(void* pPortHndl, int queue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->rxQueue[queue]; -+ ETH_RX_DESC* pRxDesc = (ETH_RX_DESC*)pQueueCtrl->pFirstDescr; -+ -+ pQueueCtrl->resource = 0; -+ if(pQueueCtrl->pFirstDescr != NULL) -+ { -+ while(MV_TRUE) -+ { -+ pRxDesc->bufSize = 0x0; -+ pRxDesc->byteCnt = 0x0; -+ pRxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; -+ pRxDesc->bufPtr = 0x0; -+ pRxDesc->returnInfo = 0x0; -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxDesc); -+ if( (void*)pRxDesc == pQueueCtrl->pLastDescr) -+ break; -+ pRxDesc = RX_NEXT_DESC_PTR(pRxDesc, pQueueCtrl); -+ } -+ pQueueCtrl->pCurrentDescr = pQueueCtrl->pFirstDescr; -+ pQueueCtrl->pUsedDescr = pQueueCtrl->pFirstDescr; -+ -+ /* Update RX Command register */ -+ pPortCtrl->portRxQueueCmdReg |= (1 << queue); -+ -+ /* update HW */ -+ MV_REG_WRITE( ETH_RX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), -+ (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); -+ } -+ else -+ { -+ /* Update RX Command register */ -+ pPortCtrl->portRxQueueCmdReg &= ~(1 << queue); -+ -+ /* update HW */ -+ MV_REG_WRITE( ETH_RX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), 0); -+ } -+} -+ -+/******************************************************************************* -+* etherInitTxDescRing - Curve a Tx chain desc list and buffer in memory. -+* -+* DESCRIPTION: -+* This function prepares a Tx chained list of descriptors and packet -+* buffers in a form of a ring. The routine must be called after port -+* initialization routine and before port start routine. -+* The Ethernet SDMA engine uses CPU bus addresses to access the various -+* devices in the system (i.e. DRAM). This function uses the ethernet -+* struct 'virtual to physical' routine (set by the user) to set the ring -+* with physical addresses. -+* -+* INPUT: -+* ETH_PORT_CTRL *pEthPortCtrl Ethernet Port Control srtuct. -+* int txQueue Number of Tx queue. -+* int txDescNum Number of Tx descriptors -+* int txBuffSize Size of Tx buffer -+* MV_U8* pTxDescBase Tx descriptors memory area base addr. -+* -+* OUTPUT: -+* The routine updates the Ethernet port control struct with information -+* regarding the Tx descriptors and buffers. -+* -+* RETURN: None. -+* -+*******************************************************************************/ -+static void ethInitTxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue) -+{ -+ ETH_TX_DESC *pTxDescBase, *pTxDesc, *pTxPrevDesc; -+ int ix, txDescNum = pPortCtrl->txQueueConfig[queue].descrNum; -+ ETH_QUEUE_CTRL *pQueueCtrl = &pPortCtrl->txQueue[queue]; -+ -+ /* Make sure descriptor address is cache line size aligned */ -+ pTxDescBase = (ETH_TX_DESC*)MV_ALIGN_UP((MV_ULONG)pQueueCtrl->descBuf.bufVirtPtr, -+ CPU_D_CACHE_LINE_SIZE); -+ -+ pTxDesc = (ETH_TX_DESC*)pTxDescBase; -+ pTxPrevDesc = pTxDesc; -+ -+ /* initialize the Tx descriptors ring */ -+ for (ix=0; ixbyteCnt = 0x0000; -+ pTxDesc->L4iChk = 0x0000; -+ pTxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; -+ pTxDesc->bufPtr = 0x0; -+ pTxDesc->returnInfo = 0x0; -+ -+ pTxPrevDesc = pTxDesc; -+ -+ if(ix == (txDescNum-1)) -+ { -+ /* Closing Tx descriptors ring */ -+ pTxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pTxDescBase); -+ } -+ else -+ { -+ pTxDesc = (ETH_TX_DESC*)((MV_ULONG)pTxDesc + ETH_TX_DESC_ALIGNED_SIZE); -+ pTxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pTxDesc); -+ } -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxPrevDesc); -+ } -+ -+ pQueueCtrl->pCurrentDescr = pTxDescBase; -+ pQueueCtrl->pUsedDescr = pTxDescBase; -+ -+ pQueueCtrl->pFirstDescr = pTxDescBase; -+ pQueueCtrl->pLastDescr = pTxDesc; -+ /* Leave one TX descriptor out of use */ -+ pQueueCtrl->resource = txDescNum - 1; -+} -+ -+void ethResetTxDescRing(void* pPortHndl, int queue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->txQueue[queue]; -+ ETH_TX_DESC* pTxDesc = (ETH_TX_DESC*)pQueueCtrl->pFirstDescr; -+ -+ pQueueCtrl->resource = 0; -+ if(pQueueCtrl->pFirstDescr != NULL) -+ { -+ while(MV_TRUE) -+ { -+ pTxDesc->byteCnt = 0x0000; -+ pTxDesc->L4iChk = 0x0000; -+ pTxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; -+ pTxDesc->bufPtr = 0x0; -+ pTxDesc->returnInfo = 0x0; -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxDesc); -+ pQueueCtrl->resource++; -+ if( (void*)pTxDesc == pQueueCtrl->pLastDescr) -+ break; -+ pTxDesc = TX_NEXT_DESC_PTR(pTxDesc, pQueueCtrl); -+ } -+ /* Leave one TX descriptor out of use */ -+ pQueueCtrl->resource--; -+ pQueueCtrl->pCurrentDescr = pQueueCtrl->pFirstDescr; -+ pQueueCtrl->pUsedDescr = pQueueCtrl->pFirstDescr; -+ -+ /* Update TX Command register */ -+ pPortCtrl->portTxQueueCmdReg |= MV_32BIT_LE_FAST(1 << queue); -+ /* update HW */ -+ MV_REG_WRITE( ETH_TX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), -+ (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); -+ } -+ else -+ { -+ /* Update TX Command register */ -+ pPortCtrl->portTxQueueCmdReg &= MV_32BIT_LE_FAST(~(1 << queue)); -+ /* update HW */ -+ MV_REG_WRITE( ETH_TX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), 0 ); -+ } -+} -+ -+/******************************************************************************* -+* ethAllocDescrMemory - Free memory allocated for RX and TX descriptors. -+* -+* DESCRIPTION: -+* This function allocates memory for RX and TX descriptors. -+* - If ETH_DESCR_IN_SRAM defined, allocate memory from SRAM. -+* - If ETH_DESCR_IN_SDRAM defined, allocate memory in SDRAM. -+* -+* INPUT: -+* int size - size of memory should be allocated. -+* -+* RETURN: None -+* -+*******************************************************************************/ -+static MV_U8* ethAllocDescrMemory(ETH_PORT_CTRL* pPortCtrl, int descSize, -+ MV_ULONG* pPhysAddr, MV_U32 *memHandle) -+{ -+ MV_U8* pVirt; -+ -+#if defined(ETH_DESCR_IN_SRAM) -+ if(ethDescInSram == MV_TRUE) -+ pVirt = (char*)mvSramMalloc(descSize, pPhysAddr); -+ else -+#endif /* ETH_DESCR_IN_SRAM */ -+ { -+#ifdef ETH_DESCR_UNCACHED -+ pVirt = (MV_U8*)mvOsIoUncachedMalloc(pPortCtrl->osHandle, descSize, -+ pPhysAddr,memHandle); -+#else -+ pVirt = (MV_U8*)mvOsIoCachedMalloc(pPortCtrl->osHandle, descSize, -+ pPhysAddr, memHandle); -+#endif /* ETH_DESCR_UNCACHED */ -+ } -+ memset(pVirt, 0, descSize); -+ -+ return pVirt; -+} -+ -+/******************************************************************************* -+* ethFreeDescrMemory - Free memory allocated for RX and TX descriptors. -+* -+* DESCRIPTION: -+* This function frees memory allocated for RX and TX descriptors. -+* - If ETH_DESCR_IN_SRAM defined, free memory using gtSramFree() function. -+* - If ETH_DESCR_IN_SDRAM defined, free memory using mvOsFree() function. -+* -+* INPUT: -+* void* pVirtAddr - virtual pointer to memory allocated for RX and TX -+* desriptors. -+* -+* RETURN: None -+* -+*******************************************************************************/ -+void ethFreeDescrMemory(ETH_PORT_CTRL* pPortCtrl, MV_BUF_INFO* pDescBuf) -+{ -+ if( (pDescBuf == NULL) || (pDescBuf->bufVirtPtr == NULL) ) -+ return; -+ -+#if defined(ETH_DESCR_IN_SRAM) -+ if( ethDescInSram ) -+ { -+ mvSramFree(pDescBuf->bufSize, pDescBuf->bufPhysAddr, pDescBuf->bufVirtPtr); -+ return; -+ } -+#endif /* ETH_DESCR_IN_SRAM */ -+ -+#ifdef ETH_DESCR_UNCACHED -+ mvOsIoUncachedFree(pPortCtrl->osHandle, pDescBuf->bufSize, pDescBuf->bufPhysAddr, -+ pDescBuf->bufVirtPtr,pDescBuf->memHandle); -+#else -+ mvOsIoCachedFree(pPortCtrl->osHandle, pDescBuf->bufSize, pDescBuf->bufPhysAddr, -+ pDescBuf->bufVirtPtr,pDescBuf->memHandle); -+#endif /* ETH_DESCR_UNCACHED */ -+} -+ -+/******************************************************************************/ -+/* Other Functions */ -+/******************************************************************************/ -+ -+void mvEthPortPowerUp(int port) -+{ -+ MV_U32 regVal; -+ -+ /* MAC Cause register should be cleared */ -+ MV_REG_WRITE(ETH_UNIT_INTR_CAUSE_REG(port), 0); -+ -+ if (mvBoardIsPortInSgmii(port)) -+ mvEthPortSgmiiConfig(port); -+ -+ /* Cancel Port Reset */ -+ regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)); -+ regVal &= (~ETH_PORT_RESET_MASK); -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal); -+ while( (MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)) & ETH_PORT_RESET_MASK) != 0); -+} -+ -+void mvEthPortPowerDown(int port) -+{ -+ MV_U32 regVal; -+ -+ /* Port must be DISABLED */ -+ regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port)); -+ if( (regVal & ETH_PORT_ENABLE_MASK) != 0) -+ { -+ mvOsPrintf("ethPort #%d: PowerDown - port must be Disabled (PSC=0x%x)\n", -+ port, regVal); -+ return; -+ } -+ -+ /* Port Reset (Read after write the register as a precaution) */ -+ regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)); -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal | ETH_PORT_RESET_MASK); -+ while((MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)) & ETH_PORT_RESET_MASK) == 0); -+} -+ -+static void mvEthPortSgmiiConfig(int port) -+{ -+ MV_U32 regVal; -+ -+ regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)); -+ -+ regVal |= (ETH_SGMII_MODE_MASK /*| ETH_INBAND_AUTO_NEG_ENABLE_MASK */); -+ regVal &= (~ETH_INBAND_AUTO_NEG_BYPASS_MASK); -+ -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal); -+} -+ -+ -+ -+ -+ -+ -+ -+ -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,748 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+/******************************************************************************* -+* mvEthDebug.c - Source file for user friendly debug functions -+* -+* DESCRIPTION: -+* -+* DEPENDENCIES: -+* None. -+* -+*******************************************************************************/ -+ -+#include "mvOs.h" -+#include "mvCommon.h" -+#include "mvTypes.h" -+#include "mv802_3.h" -+#include "mvDebug.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "eth-phy/mvEthPhy.h" -+#include "eth/mvEth.h" -+#include "eth/gbe/mvEthDebug.h" -+ -+/* #define mvOsPrintf printf */ -+ -+void mvEthPortShow(void* pHndl); -+void mvEthQueuesShow(void* pHndl, int rxQueue, int txQueue, int mode); -+ -+/******************************************************************************/ -+/* Debug functions */ -+/******************************************************************************/ -+void ethRxCoal(int port, int usec) -+{ -+ void* pHndl; -+ -+ pHndl = mvEthPortHndlGet(port); -+ if(pHndl != NULL) -+ { -+ mvEthRxCoalSet(pHndl, usec); -+ } -+} -+ -+void ethTxCoal(int port, int usec) -+{ -+ void* pHndl; -+ -+ pHndl = mvEthPortHndlGet(port); -+ if(pHndl != NULL) -+ { -+ mvEthTxCoalSet(pHndl, usec); -+ } -+} -+ -+#if (MV_ETH_VERSION >= 4) -+void ethEjpModeSet(int port, int mode) -+{ -+ void* pHndl; -+ -+ pHndl = mvEthPortHndlGet(port); -+ if(pHndl != NULL) -+ { -+ mvEthEjpModeSet(pHndl, mode); -+ } -+} -+#endif /* (MV_ETH_VERSION >= 4) */ -+ -+void ethBpduRxQ(int port, int bpduQueue) -+{ -+ void* pHndl; -+ -+ pHndl = mvEthPortHndlGet(port); -+ if(pHndl != NULL) -+ { -+ mvEthBpduRxQueue(pHndl, bpduQueue); -+ } -+} -+ -+void ethArpRxQ(int port, int arpQueue) -+{ -+ void* pHndl; -+ -+ pHndl = mvEthPortHndlGet(port); -+ if(pHndl != NULL) -+ { -+ mvEthArpRxQueue(pHndl, arpQueue); -+ } -+} -+ -+void ethTcpRxQ(int port, int tcpQueue) -+{ -+ void* pHndl; -+ -+ pHndl = mvEthPortHndlGet(port); -+ if(pHndl != NULL) -+ { -+ mvEthTcpRxQueue(pHndl, tcpQueue); -+ } -+} -+ -+void ethUdpRxQ(int port, int udpQueue) -+{ -+ void* pHndl; -+ -+ pHndl = mvEthPortHndlGet(port); -+ if(pHndl != NULL) -+ { -+ mvEthUdpRxQueue(pHndl, udpQueue); -+ } -+} -+ -+void ethTxPolicyRegs(int port) -+{ -+ int queue; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)mvEthPortHndlGet(port); -+ -+ if(pPortCtrl == NULL) -+ { -+ return; -+ } -+ mvOsPrintf("Port #%d TX Policy: EJP=%d, TXQs: ", -+ port, pPortCtrl->portConfig.ejpMode); -+ for(queue=0; queuetxQueueConfig[queue].descrNum > 0) -+ mvOsPrintf("%d, ", queue); -+ } -+ mvOsPrintf("\n"); -+ -+ mvOsPrintf("\n\t TX policy Port #%d configuration registers\n", port); -+ -+ mvOsPrintf("ETH_TX_QUEUE_COMMAND_REG : 0x%X = 0x%08x\n", -+ ETH_TX_QUEUE_COMMAND_REG(port), -+ MV_REG_READ( ETH_TX_QUEUE_COMMAND_REG(port) ) ); -+ -+ mvOsPrintf("ETH_TX_FIXED_PRIO_CFG_REG : 0x%X = 0x%08x\n", -+ ETH_TX_FIXED_PRIO_CFG_REG(port), -+ MV_REG_READ( ETH_TX_FIXED_PRIO_CFG_REG(port) ) ); -+ -+ mvOsPrintf("ETH_TX_TOKEN_RATE_CFG_REG : 0x%X = 0x%08x\n", -+ ETH_TX_TOKEN_RATE_CFG_REG(port), -+ MV_REG_READ( ETH_TX_TOKEN_RATE_CFG_REG(port) ) ); -+ -+ mvOsPrintf("ETH_MAX_TRANSMIT_UNIT_REG : 0x%X = 0x%08x\n", -+ ETH_MAX_TRANSMIT_UNIT_REG(port), -+ MV_REG_READ( ETH_MAX_TRANSMIT_UNIT_REG(port) ) ); -+ -+ mvOsPrintf("ETH_TX_TOKEN_BUCKET_SIZE_REG : 0x%X = 0x%08x\n", -+ ETH_TX_TOKEN_BUCKET_SIZE_REG(port), -+ MV_REG_READ( ETH_TX_TOKEN_BUCKET_SIZE_REG(port) ) ); -+ -+ mvOsPrintf("ETH_TX_TOKEN_BUCKET_COUNT_REG : 0x%X = 0x%08x\n", -+ ETH_TX_TOKEN_BUCKET_COUNT_REG(port), -+ MV_REG_READ( ETH_TX_TOKEN_BUCKET_COUNT_REG(port) ) ); -+ -+ for(queue=0; queue> 24) & 0xff), ((macH >> 16) & 0xff), -+ ((macH >> 8) & 0xff), (macH & 0xff), -+ ((macL >> 8) & 0xff), (macL & 0xff) ); -+ -+ for (i=0; i<4; i++) -+ { -+ unicastReg = MV_REG_READ( (ETH_DA_FILTER_UCAST_BASE(port) + i*4)); -+ for(j=0; j<4; j++) -+ { -+ MV_U8 macEntry = (unicastReg >> (8*j)) & 0xFF; -+ -+ mvOsPrintf("%X: %8s, Q = %d\n", i*4+j, -+ (macEntry & BIT0) ? "Accept" : "Reject", (macEntry >> 1) & 0x7); -+ } -+ } -+} -+ -+void ethMcastAdd(int port, char* macStr, int queue) -+{ -+ void* pHndl; -+ MV_U8 macAddr[MV_MAC_ADDR_SIZE]; -+ -+ pHndl = mvEthPortHndlGet(port); -+ if(pHndl != NULL) -+ { -+ mvMacStrToHex(macStr, macAddr); -+ mvEthMcastAddrSet(pHndl, macAddr, queue); -+ } -+} -+ -+void ethPortMcast(int port) -+{ -+ int tblIdx, regIdx; -+ MV_U32 regVal; -+ -+ mvOsPrintf("\n\t Port #%d Special (IP) Multicast table: 01:00:5E:00:00:XX\n\n", -+ port); -+ -+ for(tblIdx=0; tblIdx<(256/4); tblIdx++) -+ { -+ regVal = MV_REG_READ((ETH_DA_FILTER_SPEC_MCAST_BASE(port) + tblIdx*4)); -+ for(regIdx=0; regIdx<4; regIdx++) -+ { -+ if((regVal & (0x01 << (regIdx*8))) != 0) -+ { -+ mvOsPrintf("0x%02X: Accepted, rxQ = %d\n", -+ tblIdx*4+regIdx, ((regVal >> (regIdx*8+1)) & 0x07)); -+ } -+ } -+ } -+ mvOsPrintf("\n\t Port #%d Other Multicast table\n\n", port); -+ for(tblIdx=0; tblIdx<(256/4); tblIdx++) -+ { -+ regVal = MV_REG_READ((ETH_DA_FILTER_OTH_MCAST_BASE(port) + tblIdx*4)); -+ for(regIdx=0; regIdx<4; regIdx++) -+ { -+ if((regVal & (0x01 << (regIdx*8))) != 0) -+ { -+ mvOsPrintf("Crc8=0x%02X: Accepted, rxQ = %d\n", -+ tblIdx*4+regIdx, ((regVal >> (regIdx*8+1)) & 0x07)); -+ } -+ } -+ } -+} -+ -+ -+/* Print status of Ethernet port */ -+void mvEthPortShow(void* pHndl) -+{ -+ MV_U32 regValue, rxCoal, txCoal; -+ int speed, queue, port; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pHndl; -+ -+ port = pPortCtrl->portNo; -+ -+ regValue = MV_REG_READ( ETH_PORT_STATUS_REG(port) ); -+ -+ mvOsPrintf("\n\t ethGiga #%d port Status: 0x%04x = 0x%08x\n\n", -+ port, ETH_PORT_STATUS_REG(port), regValue); -+ -+ mvOsPrintf("descInSram=%d, descSwCoher=%d\n", -+ ethDescInSram, ethDescSwCoher); -+ -+ if(regValue & ETH_GMII_SPEED_1000_MASK) -+ speed = 1000; -+ else if(regValue & ETH_MII_SPEED_100_MASK) -+ speed = 100; -+ else -+ speed = 10; -+ -+ mvEthCoalGet(pPortCtrl, &rxCoal, &txCoal); -+ -+ /* Link, Speed, Duplex, FlowControl */ -+ mvOsPrintf("Link=%s, Speed=%d, Duplex=%s, RxFlowControl=%s", -+ (regValue & ETH_LINK_UP_MASK) ? "UP" : "DOWN", -+ speed, -+ (regValue & ETH_FULL_DUPLEX_MASK) ? "FULL" : "HALF", -+ (regValue & ETH_ENABLE_RCV_FLOW_CTRL_MASK) ? "ENABLE" : "DISABLE"); -+ -+ mvOsPrintf("\n"); -+ -+ mvOsPrintf("RxCoal = %d usec, TxCoal = %d usec\n", -+ rxCoal, txCoal); -+ -+ mvOsPrintf("rxDefQ=%d, arpQ=%d, bpduQ=%d, tcpQ=%d, udpQ=%d\n\n", -+ pPortCtrl->portConfig.rxDefQ, pPortCtrl->portConfig.rxArpQ, -+ pPortCtrl->portConfig.rxBpduQ, -+ pPortCtrl->portConfig.rxTcpQ, pPortCtrl->portConfig.rxUdpQ); -+ -+ /* Print all RX and TX queues */ -+ for(queue=0; queuerxQueue[queue].pFirstDescr, -+ mvEthRxResourceGet(pPortCtrl, queue) ); -+ } -+ mvOsPrintf("\n"); -+ for(queue=0; queuetxQueue[queue].pFirstDescr, -+ mvEthTxResourceGet(pPortCtrl, queue) ); -+ } -+} -+ -+/* Print RX and TX queue of the Ethernet port */ -+void mvEthQueuesShow(void* pHndl, int rxQueue, int txQueue, int mode) -+{ -+ ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL*)pHndl; -+ ETH_QUEUE_CTRL *pQueueCtrl; -+ MV_U32 regValue; -+ ETH_RX_DESC *pRxDescr; -+ ETH_TX_DESC *pTxDescr; -+ int i, port = pPortCtrl->portNo; -+ -+ if( (rxQueue >=0) && (rxQueue < MV_ETH_RX_Q_NUM) ) -+ { -+ pQueueCtrl = &(pPortCtrl->rxQueue[rxQueue]); -+ mvOsPrintf("Port #%d, RX Queue #%d\n\n", port, rxQueue); -+ -+ mvOsPrintf("CURR_RX_DESC_PTR : 0x%X = 0x%08x\n", -+ ETH_RX_CUR_DESC_PTR_REG(port, rxQueue), -+ MV_REG_READ( ETH_RX_CUR_DESC_PTR_REG(port, rxQueue))); -+ -+ -+ if(pQueueCtrl->pFirstDescr != NULL) -+ { -+ mvOsPrintf("pFirstDescr=0x%lx, pLastDescr=0x%lx, numOfResources=%d\n", -+ (MV_ULONG)pQueueCtrl->pFirstDescr, (MV_ULONG)pQueueCtrl->pLastDescr, -+ pQueueCtrl->resource); -+ mvOsPrintf("pCurrDescr: 0x%lx, pUsedDescr: 0x%lx\n", -+ (MV_ULONG)pQueueCtrl->pCurrentDescr, -+ (MV_ULONG)pQueueCtrl->pUsedDescr); -+ -+ if(mode == 1) -+ { -+ pRxDescr = (ETH_RX_DESC*)pQueueCtrl->pFirstDescr; -+ i = 0; -+ do -+ { -+ mvOsPrintf("%3d. desc=%08x (%08x), cmd=%08x, data=%4d, buf=%4d, buf=%08x, pkt=%lx, os=%lx\n", -+ i, (MV_U32)pRxDescr, (MV_U32)ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pRxDescr), -+ pRxDescr->cmdSts, pRxDescr->byteCnt, (MV_U32)pRxDescr->bufSize, -+ (unsigned int)pRxDescr->bufPtr, (MV_ULONG)pRxDescr->returnInfo, -+ ((MV_PKT_INFO*)pRxDescr->returnInfo)->osInfo); -+ -+ ETH_DESCR_INV(pPortCtrl, pRxDescr); -+ pRxDescr = RX_NEXT_DESC_PTR(pRxDescr, pQueueCtrl); -+ i++; -+ } while (pRxDescr != pQueueCtrl->pFirstDescr); -+ } -+ } -+ else -+ mvOsPrintf("RX Queue #%d is NOT CREATED\n", rxQueue); -+ } -+ -+ if( (txQueue >=0) && (txQueue < MV_ETH_TX_Q_NUM) ) -+ { -+ pQueueCtrl = &(pPortCtrl->txQueue[txQueue]); -+ mvOsPrintf("Port #%d, TX Queue #%d\n\n", port, txQueue); -+ -+ regValue = MV_REG_READ( ETH_TX_CUR_DESC_PTR_REG(port, txQueue)); -+ mvOsPrintf("CURR_TX_DESC_PTR : 0x%X = 0x%08x\n", -+ ETH_TX_CUR_DESC_PTR_REG(port, txQueue), regValue); -+ -+ if(pQueueCtrl->pFirstDescr != NULL) -+ { -+ mvOsPrintf("pFirstDescr=0x%lx, pLastDescr=0x%lx, numOfResources=%d\n", -+ (MV_ULONG)pQueueCtrl->pFirstDescr, -+ (MV_ULONG)pQueueCtrl->pLastDescr, -+ pQueueCtrl->resource); -+ mvOsPrintf("pCurrDescr: 0x%lx, pUsedDescr: 0x%lx\n", -+ (MV_ULONG)pQueueCtrl->pCurrentDescr, -+ (MV_ULONG)pQueueCtrl->pUsedDescr); -+ -+ if(mode == 1) -+ { -+ pTxDescr = (ETH_TX_DESC*)pQueueCtrl->pFirstDescr; -+ i = 0; -+ do -+ { -+ mvOsPrintf("%3d. desc=%08x (%08x), cmd=%08x, data=%4d, buf=%08x, pkt=%lx, os=%lx\n", -+ i, (MV_U32)pTxDescr, (MV_U32)ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pTxDescr), -+ pTxDescr->cmdSts, pTxDescr->byteCnt, -+ (MV_U32)pTxDescr->bufPtr, (MV_ULONG)pTxDescr->returnInfo, -+ pTxDescr->returnInfo ? (((MV_PKT_INFO*)pTxDescr->returnInfo)->osInfo) : 0x0); -+ -+ ETH_DESCR_INV(pPortCtrl, pTxDescr); -+ pTxDescr = TX_NEXT_DESC_PTR(pTxDescr, pQueueCtrl); -+ i++; -+ } while (pTxDescr != pQueueCtrl->pFirstDescr); -+ } -+ } -+ else -+ mvOsPrintf("TX Queue #%d is NOT CREATED\n", txQueue); -+ } -+} -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,146 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#ifndef __MV_ETH_DEBUG_H__ -+#define __MV_ETH_DEBUG_H__ -+ -+#if 0 -+/* -+ ** Externs -+ */ -+void ethBpduRxQ(int port, int bpduQueue); -+void ethArpRxQ(int port, int bpduQueue); -+void ethTcpRxQ(int port, int bpduQueue); -+void ethUdpRxQ(int port, int bpduQueue); -+void ethMcastAdd(int port, char* macStr, int queue); -+ -+#ifdef INCLUDE_MULTI_QUEUE -+void ethRxPolicy( int port); -+void ethTxPolicy( int port); -+void ethTxPolDA(int port, char* macStr, int txQ, char* headerHexStr); -+void ethRxPolMode(int port, MV_ETH_PRIO_MODE prioMode); -+void ethRxPolQ(int port, int rxQueue, int rxQuota); -+#endif /* INCLUDE_MULTI_QUEUE */ -+ -+void print_egiga_stat(void *sc, unsigned int port); -+void ethPortStatus (int port); -+void ethPortQueues( int port, int rxQueue, int txQueue, int mode); -+void ethPortMcast(int port); -+void ethPortRegs(int port); -+void ethPortCounters(int port); -+void ethPortRmonCounters(int port); -+void ethRxCoal(int port, int usec); -+void ethTxCoal(int port, int usec); -+ -+void ethRegs(int port); -+void ethClearCounters(int port); -+void ethUcastSet(int port, char* macStr, int queue); -+void ethPortUcastShow(int port); -+ -+#ifdef CONFIG_MV_ETH_HEADER -+void run_com_header(const char *buffer); -+#endif -+ -+#ifdef INCLUDE_MULTI_QUEUE -+void ethRxPolMode(int port, MV_ETH_PRIO_MODE prioMode); -+void ethRxPolQ(int port, int queue, int quota); -+void ethRxPolicy(int port); -+void ethTxPolDef(int port, int txQ, char* headerHexStr); -+void ethTxPolDA(int port, char* macStr, int txQ, char* headerHexStr); -+void ethTxPolicy(int port); -+#endif /* INCLUDE_MULTI_QUEUE */ -+ -+#if (MV_ETH_VERSION >= 4) -+void ethEjpModeSet(int port, int mode) -+#endif -+#endif /* 0 */ -+ -+ -+ -+ -+void ethRxCoal(int port, int usec); -+void ethTxCoal(int port, int usec); -+#if (MV_ETH_VERSION >= 4) -+void ethEjpModeSet(int port, int mode); -+#endif /* (MV_ETH_VERSION >= 4) */ -+ -+void ethBpduRxQ(int port, int bpduQueue); -+void ethArpRxQ(int port, int arpQueue); -+void ethTcpRxQ(int port, int tcpQueue); -+void ethUdpRxQ(int port, int udpQueue); -+void ethTxPolicyRegs(int port); -+void ethPortRegs(int port); -+void ethRegs(int port); -+void ethClearCounters(int port); -+void ethPortCounters(int port); -+void ethPortRmonCounters(int port); -+void ethPortStatus(int port); -+void ethPortQueues(int port, int rxQueue, int txQueue, int mode); -+void ethUcastSet(int port, char* macStr, int queue); -+void ethPortUcastShow(int port); -+void ethMcastAdd(int port, char* macStr, int queue); -+void ethPortMcast(int port); -+void mvEthPortShow(void* pHndl); -+void mvEthQueuesShow(void* pHndl, int rxQueue, int txQueue, int mode); -+ -+#endif -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthGbe.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthGbe.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthGbe.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthGbe.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,751 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+/******************************************************************************* -+* mvEth.h - Header File for : Marvell Gigabit Ethernet Controller -+* -+* DESCRIPTION: -+* This header file contains macros typedefs and function declaration specific to -+* the Marvell Gigabit Ethernet Controller. -+* -+* DEPENDENCIES: -+* None. -+* -+*******************************************************************************/ -+ -+#ifndef __mvEthGbe_h__ -+#define __mvEthGbe_h__ -+ -+extern MV_BOOL ethDescInSram; -+extern MV_BOOL ethDescSwCoher; -+extern ETH_PORT_CTRL* ethPortCtrl[]; -+ -+static INLINE MV_ULONG ethDescVirtToPhy(ETH_QUEUE_CTRL* pQueueCtrl, MV_U8* pDesc) -+{ -+#if defined (ETH_DESCR_IN_SRAM) -+ if( ethDescInSram ) -+ return mvSramVirtToPhy(pDesc); -+ else -+#endif /* ETH_DESCR_IN_SRAM */ -+ return (pQueueCtrl->descBuf.bufPhysAddr + (pDesc - pQueueCtrl->descBuf.bufVirtPtr)); -+} -+/* Return port handler */ -+#define mvEthPortHndlGet(port) ethPortCtrl[port] -+ -+/* Used as WA for HW/SW race on TX */ -+static INLINE int mvEthPortTxEnable(void* pPortHndl, int queue, int max_deep) -+{ -+ int deep = 0; -+ MV_U32 txCurrReg, txEnReg; -+ ETH_TX_DESC* pTxLastDesc; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ -+ txEnReg = MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)); -+ if( (txEnReg & MV_32BIT_LE_FAST(ETH_TXQ_ENABLE_MASK)) == 0) -+ { -+ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) = pPortCtrl->portTxQueueCmdReg; -+ return 0; -+ } -+ -+ pQueueCtrl = &pPortCtrl->txQueue[queue]; -+ pTxLastDesc = pQueueCtrl->pCurrentDescr; -+ txCurrReg = MV_REG_READ(ETH_TX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue)); -+ if(ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pTxLastDesc) == txCurrReg) -+ { -+ /* All descriptors are processed, no chance for race */ -+ return 0; -+ } -+ -+ /* Check distance betwee HW and SW location: */ -+ /* If distance between HW and SW pointers is less than max_deep descriptors */ -+ /* Race condition is possible, so wait end of TX and restart TXQ */ -+ while(deep < max_deep) -+ { -+ pTxLastDesc = TX_PREV_DESC_PTR(pTxLastDesc, pQueueCtrl); -+ if(ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pTxLastDesc) == txCurrReg) -+ { -+ int count = 0; -+ -+ while( (txEnReg & MV_32BIT_LE_FAST(ETH_TXQ_ENABLE_MASK)) != 0) -+ { -+ count++; -+ if(count > 10000) -+ { -+ mvOsPrintf("mvEthPortTxEnable: timeout - TXQ_CMD=0x%08x\n", -+ MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) ); -+ break; -+ } -+ txEnReg = MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)); -+ } -+ -+ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) = pPortCtrl->portTxQueueCmdReg; -+ return count; -+ } -+ deep++; -+ } -+ /* Distance between HW and SW pointers is more than max_deep descriptors, */ -+ /* So NO race condition - do nothing */ -+ return -1; -+} -+ -+ -+/* defines */ -+#define ETH_CSUM_MIN_BYTE_COUNT 72 -+ -+/* Tailgate and Kirwood have only 2K TX FIFO */ -+#if (MV_ETH_VERSION == 2) || (MV_ETH_VERSION == 4) -+#define ETH_CSUM_MAX_BYTE_COUNT 1600 -+#else -+#define ETH_CSUM_MAX_BYTE_COUNT 9*1024 -+#endif /* MV_ETH_VERSION */ -+ -+#define ETH_MV_HEADER_SIZE 2 -+#define ETH_MV_TX_EN -+ -+/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */ -+#define MIN_TX_BUFF_LOAD 8 -+#define TX_BUF_OFFSET_IN_DESC (ETH_TX_DESC_ALIGNED_SIZE - MIN_TX_BUFF_LOAD) -+ -+/* Default port configuration value */ -+#define PORT_CONFIG_VALUE \ -+ ETH_DEF_RX_QUEUE_MASK(0) | \ -+ ETH_DEF_RX_ARP_QUEUE_MASK(0) | \ -+ ETH_DEF_RX_TCP_QUEUE_MASK(0) | \ -+ ETH_DEF_RX_UDP_QUEUE_MASK(0) | \ -+ ETH_DEF_RX_BPDU_QUEUE_MASK(0) | \ -+ ETH_RX_CHECKSUM_WITH_PSEUDO_HDR -+ -+/* Default port extend configuration value */ -+#define PORT_CONFIG_EXTEND_VALUE 0 -+ -+#define PORT_SERIAL_CONTROL_VALUE \ -+ ETH_DISABLE_FC_AUTO_NEG_MASK | \ -+ BIT9 | \ -+ ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ -+ ETH_MAX_RX_PACKET_1552BYTE | \ -+ ETH_SET_FULL_DUPLEX_MASK -+ -+#define PORT_SERIAL_CONTROL_100MB_FORCE_VALUE \ -+ ETH_FORCE_LINK_PASS_MASK | \ -+ ETH_DISABLE_DUPLEX_AUTO_NEG_MASK | \ -+ ETH_DISABLE_FC_AUTO_NEG_MASK | \ -+ BIT9 | \ -+ ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ -+ ETH_DISABLE_SPEED_AUTO_NEG_MASK | \ -+ ETH_SET_FULL_DUPLEX_MASK | \ -+ ETH_SET_MII_SPEED_100_MASK | \ -+ ETH_MAX_RX_PACKET_1552BYTE -+ -+ -+#define PORT_SERIAL_CONTROL_1000MB_FORCE_VALUE \ -+ ETH_FORCE_LINK_PASS_MASK | \ -+ ETH_DISABLE_DUPLEX_AUTO_NEG_MASK | \ -+ ETH_DISABLE_FC_AUTO_NEG_MASK | \ -+ BIT9 | \ -+ ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ -+ ETH_DISABLE_SPEED_AUTO_NEG_MASK | \ -+ ETH_SET_FULL_DUPLEX_MASK | \ -+ ETH_SET_GMII_SPEED_1000_MASK | \ -+ ETH_MAX_RX_PACKET_1552BYTE -+ -+#define PORT_SERIAL_CONTROL_SGMII_IBAN_VALUE \ -+ ETH_DISABLE_FC_AUTO_NEG_MASK | \ -+ BIT9 | \ -+ ETH_IN_BAND_AN_EN_MASK | \ -+ ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ -+ ETH_MAX_RX_PACKET_1552BYTE -+ -+/* Function headers: */ -+MV_VOID mvEthSetSpecialMcastTable(int portNo, int queue); -+MV_STATUS mvEthArpRxQueue(void* pPortHandle, int arpQueue); -+MV_STATUS mvEthUdpRxQueue(void* pPortHandle, int udpQueue); -+MV_STATUS mvEthTcpRxQueue(void* pPortHandle, int tcpQueue); -+MV_STATUS mvEthMacAddrGet(int portNo, unsigned char *pAddr); -+MV_VOID mvEthSetOtherMcastTable(int portNo, int queue); -+MV_STATUS mvEthHeaderModeSet(void* pPortHandle, MV_ETH_HEADER_MODE headerMode); -+/* Interrupt Coalesting functions */ -+MV_U32 mvEthRxCoalSet(void* pPortHndl, MV_U32 uSec); -+MV_U32 mvEthTxCoalSet(void* pPortHndl, MV_U32 uSec); -+MV_STATUS mvEthCoalGet(void* pPortHndl, MV_U32* pRxCoal, MV_U32* pTxCoal); -+ -+/******************************************************************************/ -+/* Data Flow functions */ -+/******************************************************************************/ -+static INLINE void mvEthPortTxRestart(void* pPortHndl) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ -+ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) = pPortCtrl->portTxQueueCmdReg; -+} -+ -+/* Get number of Free resources in specific TX queue */ -+static INLINE int mvEthTxResourceGet(void* pPortHndl, int txQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ -+ return (pPortCtrl->txQueue[txQueue].resource); -+} -+ -+/* Get number of Free resources in specific RX queue */ -+static INLINE int mvEthRxResourceGet(void* pPortHndl, int rxQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ -+ return (pPortCtrl->rxQueue[rxQueue].resource); -+} -+ -+static INLINE int mvEthTxQueueIsFull(void* pPortHndl, int txQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ -+ if(pPortCtrl->txQueue[txQueue].resource == 0) -+ return MV_TRUE; -+ -+ return MV_FALSE; -+} -+ -+/* Get number of Free resources in specific RX queue */ -+static INLINE int mvEthRxQueueIsFull(void* pPortHndl, int rxQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->rxQueue[rxQueue]; -+ -+ if( (pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) && -+ (pQueueCtrl->resource != 0) ) -+ return MV_TRUE; -+ -+ return MV_FALSE; -+} -+ -+static INLINE int mvEthTxQueueIsEmpty(void* pPortHndl, int txQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->txQueue[txQueue]; -+ -+ if( (pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) && -+ (pQueueCtrl->resource != 0) ) -+ { -+ return MV_TRUE; -+ } -+ return MV_FALSE; -+} -+ -+/* Get number of Free resources in specific RX queue */ -+static INLINE int mvEthRxQueueIsEmpty(void* pPortHndl, int rxQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ -+ if(pPortCtrl->rxQueue[rxQueue].resource == 0) -+ return MV_TRUE; -+ -+ return MV_FALSE; -+} -+ -+/******************************************************************************* -+* mvEthPortTx - Send an Ethernet packet -+* -+* DESCRIPTION: -+* This routine send a given packet described by pPktInfo parameter. -+* Single buffer only. -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet Port handler. -+* int txQueue - Number of Tx queue. -+* MV_PKT_INFO *pPktInfo - User packet to send. -+* -+* RETURN: -+* MV_NO_RESOURCE - No enough resources to send this packet. -+* MV_ERROR - Unexpected Fatal error. -+* MV_OK - Packet send successfully. -+* -+*******************************************************************************/ -+static INLINE MV_STATUS mvEthPortTx(void* pEthPortHndl, int txQueue, MV_PKT_INFO* pPktInfo) -+{ -+ ETH_TX_DESC* pTxCurrDesc; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ int portNo; -+ MV_BUF_INFO* pBufInfo = pPktInfo->pFrags; -+ -+#ifdef ETH_DEBUG -+ if(pPortCtrl->portState != MV_ACTIVE) -+ return MV_BAD_STATE; -+#endif /* ETH_DEBUG */ -+ -+ portNo = pPortCtrl->portNo; -+ pQueueCtrl = &pPortCtrl->txQueue[txQueue]; -+ -+ /* Get the Tx Desc ring indexes */ -+ pTxCurrDesc = pQueueCtrl->pCurrentDescr; -+ -+ /* Check if there is enough resources to send the packet */ -+ if(pQueueCtrl->resource == 0) -+ return MV_NO_RESOURCE; -+ -+ pTxCurrDesc->byteCnt = pBufInfo->dataSize; -+ -+ /* Flash Buffer */ -+ if(pPktInfo->pktSize != 0) -+ { -+#ifdef MV_NETBSD -+ pTxCurrDesc->bufPtr = pBufInfo->bufPhysAddr; -+ ETH_PACKET_CACHE_FLUSH(pBufInfo->bufVirtPtr, pPktInfo->pktSize); -+#else -+ pTxCurrDesc->bufPtr = ETH_PACKET_CACHE_FLUSH(pBufInfo->bufVirtPtr, pPktInfo->pktSize); -+#endif -+ pPktInfo->pktSize = 0; -+ } -+ else -+ pTxCurrDesc->bufPtr = pBufInfo->bufPhysAddr; -+ -+ pTxCurrDesc->returnInfo = (MV_ULONG)pPktInfo; -+ -+ /* There is only one buffer in the packet */ -+ /* The OSG might set some bits for checksum offload, so add them to first descriptor */ -+ pTxCurrDesc->cmdSts = pPktInfo->status | -+ ETH_BUFFER_OWNED_BY_DMA | -+ ETH_TX_GENERATE_CRC_MASK | -+ ETH_TX_ENABLE_INTERRUPT_MASK | -+ ETH_TX_ZERO_PADDING_MASK | -+ ETH_TX_FIRST_DESC_MASK | -+ ETH_TX_LAST_DESC_MASK; -+ -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); -+ -+ pQueueCtrl->resource--; -+ pQueueCtrl->pCurrentDescr = TX_NEXT_DESC_PTR(pTxCurrDesc, pQueueCtrl); -+ -+ /* Apply send command */ -+ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(portNo)) = pPortCtrl->portTxQueueCmdReg; -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvEthPortSgTx - Send an Ethernet packet -+* -+* DESCRIPTION: -+* This routine send a given packet described by pBufInfo parameter. It -+* supports transmitting of a packet spaned over multiple buffers. -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet Port handler. -+* int txQueue - Number of Tx queue. -+* MV_PKT_INFO *pPktInfo - User packet to send. -+* -+* RETURN: -+* MV_NO_RESOURCE - No enough resources to send this packet. -+* MV_ERROR - Unexpected Fatal error. -+* MV_OK - Packet send successfully. -+* -+*******************************************************************************/ -+static INLINE MV_STATUS mvEthPortSgTx(void* pEthPortHndl, int txQueue, MV_PKT_INFO* pPktInfo) -+{ -+ ETH_TX_DESC* pTxFirstDesc; -+ ETH_TX_DESC* pTxCurrDesc; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ int portNo, bufCount; -+ MV_BUF_INFO* pBufInfo = pPktInfo->pFrags; -+ MV_U8* pTxBuf; -+ -+#ifdef ETH_DEBUG -+ if(pPortCtrl->portState != MV_ACTIVE) -+ return MV_BAD_STATE; -+#endif /* ETH_DEBUG */ -+ -+ portNo = pPortCtrl->portNo; -+ pQueueCtrl = &pPortCtrl->txQueue[txQueue]; -+ -+ /* Get the Tx Desc ring indexes */ -+ pTxCurrDesc = pQueueCtrl->pCurrentDescr; -+ -+ /* Check if there is enough resources to send the packet */ -+ if(pQueueCtrl->resource < pPktInfo->numFrags) -+ return MV_NO_RESOURCE; -+ -+ /* Remember first desc */ -+ pTxFirstDesc = pTxCurrDesc; -+ -+ bufCount = 0; -+ while(MV_TRUE) -+ { -+ if(pBufInfo[bufCount].dataSize <= MIN_TX_BUFF_LOAD) -+ { -+ /* Buffers with a payload smaller than MIN_TX_BUFF_LOAD (8 bytes) must be aligned */ -+ /* to 64-bit boundary. Two options here: */ -+ /* 1) Usually, copy the payload to the reserved 8 bytes inside descriptor. */ -+ /* 2) In the Half duplex workaround, the reserved 8 bytes inside descriptor are used */ -+ /* as a pointer to the aligned buffer, copy the small payload to this buffer. */ -+ pTxBuf = ((MV_U8*)pTxCurrDesc)+TX_BUF_OFFSET_IN_DESC; -+ mvOsBCopy(pBufInfo[bufCount].bufVirtPtr, pTxBuf, pBufInfo[bufCount].dataSize); -+ pTxCurrDesc->bufPtr = ethDescVirtToPhy(pQueueCtrl, pTxBuf); -+ } -+ else -+ { -+ /* Flash Buffer */ -+#ifdef MV_NETBSD -+ pTxCurrDesc->bufPtr = pBufInfo[bufCount].bufPhysAddr; -+ ETH_PACKET_CACHE_FLUSH(pBufInfo[bufCount].bufVirtPtr, pBufInfo[bufCount].dataSize); -+#else -+ pTxCurrDesc->bufPtr = ETH_PACKET_CACHE_FLUSH(pBufInfo[bufCount].bufVirtPtr, pBufInfo[bufCount].dataSize); -+#endif -+ } -+ -+ pTxCurrDesc->byteCnt = pBufInfo[bufCount].dataSize; -+ bufCount++; -+ -+ if(bufCount >= pPktInfo->numFrags) -+ break; -+ -+ if(bufCount > 1) -+ { -+ /* There is middle buffer of the packet Not First and Not Last */ -+ pTxCurrDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA; -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); -+ } -+ /* Go to next descriptor and next buffer */ -+ pTxCurrDesc = TX_NEXT_DESC_PTR(pTxCurrDesc, pQueueCtrl); -+ } -+ /* Set last desc with DMA ownership and interrupt enable. */ -+ pTxCurrDesc->returnInfo = (MV_ULONG)pPktInfo; -+ if(bufCount == 1) -+ { -+ /* There is only one buffer in the packet */ -+ /* The OSG might set some bits for checksum offload, so add them to first descriptor */ -+ pTxCurrDesc->cmdSts = pPktInfo->status | -+ ETH_BUFFER_OWNED_BY_DMA | -+ ETH_TX_GENERATE_CRC_MASK | -+ ETH_TX_ENABLE_INTERRUPT_MASK | -+ ETH_TX_ZERO_PADDING_MASK | -+ ETH_TX_FIRST_DESC_MASK | -+ ETH_TX_LAST_DESC_MASK; -+ -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); -+ } -+ else -+ { -+ /* Last but not First */ -+ pTxCurrDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA | -+ ETH_TX_ENABLE_INTERRUPT_MASK | -+ ETH_TX_ZERO_PADDING_MASK | -+ ETH_TX_LAST_DESC_MASK; -+ -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); -+ -+ /* Update First when more than one buffer in the packet */ -+ /* The OSG might set some bits for checksum offload, so add them to first descriptor */ -+ pTxFirstDesc->cmdSts = pPktInfo->status | -+ ETH_BUFFER_OWNED_BY_DMA | -+ ETH_TX_GENERATE_CRC_MASK | -+ ETH_TX_FIRST_DESC_MASK; -+ -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxFirstDesc); -+ } -+ /* Update txQueue state */ -+ pQueueCtrl->resource -= bufCount; -+ pQueueCtrl->pCurrentDescr = TX_NEXT_DESC_PTR(pTxCurrDesc, pQueueCtrl); -+ -+ /* Apply send command */ -+ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(portNo)) = pPortCtrl->portTxQueueCmdReg; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthPortTxDone - Free all used Tx descriptors and mBlks. -+* -+* DESCRIPTION: -+* This routine returns the transmitted packet information to the caller. -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet Port handler. -+* int txQueue - Number of Tx queue. -+* -+* OUTPUT: -+* MV_PKT_INFO *pPktInfo - Pointer to packet was sent. -+* -+* RETURN: -+* MV_NOT_FOUND - No transmitted packets to return. Transmit in progress. -+* MV_EMPTY - No transmitted packets to return. TX Queue is empty. -+* MV_ERROR - Unexpected Fatal error. -+* MV_OK - There is transmitted packet in the queue, -+* 'pPktInfo' filled with relevant information. -+* -+*******************************************************************************/ -+static INLINE MV_PKT_INFO* mvEthPortTxDone(void* pEthPortHndl, int txQueue) -+{ -+ ETH_TX_DESC* pTxCurrDesc; -+ ETH_TX_DESC* pTxUsedDesc; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ MV_PKT_INFO* pPktInfo; -+ MV_U32 commandStatus; -+ -+ pQueueCtrl = &pPortCtrl->txQueue[txQueue]; -+ -+ pTxUsedDesc = pQueueCtrl->pUsedDescr; -+ pTxCurrDesc = pQueueCtrl->pCurrentDescr; -+ -+ while(MV_TRUE) -+ { -+ /* No more used descriptors */ -+ commandStatus = pTxUsedDesc->cmdSts; -+ if (commandStatus & (ETH_BUFFER_OWNED_BY_DMA)) -+ { -+ ETH_DESCR_INV(pPortCtrl, pTxUsedDesc); -+ return NULL; -+ } -+ if( (pTxUsedDesc == pTxCurrDesc) && -+ (pQueueCtrl->resource != 0) ) -+ { -+ return NULL; -+ } -+ pQueueCtrl->resource++; -+ pQueueCtrl->pUsedDescr = TX_NEXT_DESC_PTR(pTxUsedDesc, pQueueCtrl); -+ if(commandStatus & (ETH_TX_LAST_DESC_MASK)) -+ { -+ pPktInfo = (MV_PKT_INFO*)pTxUsedDesc->returnInfo; -+ pPktInfo->status = commandStatus; -+ return pPktInfo; -+ } -+ pTxUsedDesc = pQueueCtrl->pUsedDescr; -+ } -+} -+ -+/******************************************************************************* -+* mvEthPortRx - Get new received packets from Rx queue. -+* -+* DESCRIPTION: -+* This routine returns the received data to the caller. There is no -+* data copying during routine operation. All information is returned -+* using pointer to packet information struct passed from the caller. -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet Port handler. -+* int rxQueue - Number of Rx queue. -+* -+* OUTPUT: -+* MV_PKT_INFO *pPktInfo - Pointer to received packet. -+* -+* RETURN: -+* MV_NO_RESOURCE - No free resources in RX queue. -+* MV_ERROR - Unexpected Fatal error. -+* MV_OK - New packet received and 'pBufInfo' structure filled -+* with relevant information. -+* -+*******************************************************************************/ -+static INLINE MV_PKT_INFO* mvEthPortRx(void* pEthPortHndl, int rxQueue) -+{ -+ ETH_RX_DESC *pRxCurrDesc; -+ MV_U32 commandStatus; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ MV_PKT_INFO* pPktInfo; -+ -+ pQueueCtrl = &(pPortCtrl->rxQueue[rxQueue]); -+ -+ /* Check resources */ -+ if(pQueueCtrl->resource == 0) -+ { -+ mvOsPrintf("ethPortRx: no more resources\n"); -+ return NULL; -+ } -+ while(MV_TRUE) -+ { -+ /* Get the Rx Desc ring 'curr and 'used' indexes */ -+ pRxCurrDesc = pQueueCtrl->pCurrentDescr; -+ -+ commandStatus = pRxCurrDesc->cmdSts; -+ if (commandStatus & (ETH_BUFFER_OWNED_BY_DMA)) -+ { -+ /* Nothing to receive... */ -+ ETH_DESCR_INV(pPortCtrl, pRxCurrDesc); -+ return NULL; -+ } -+ -+ /* Valid RX only if FIRST and LAST bits are set */ -+ if( (commandStatus & (ETH_RX_LAST_DESC_MASK | ETH_RX_FIRST_DESC_MASK)) == -+ (ETH_RX_LAST_DESC_MASK | ETH_RX_FIRST_DESC_MASK) ) -+ { -+ pPktInfo = (MV_PKT_INFO*)pRxCurrDesc->returnInfo; -+ pPktInfo->pFrags->dataSize = pRxCurrDesc->byteCnt - 4; -+ pPktInfo->status = commandStatus; -+ pPktInfo->fragIP = pRxCurrDesc->bufSize & ETH_RX_IP_FRAGMENTED_FRAME_MASK; -+ -+ pQueueCtrl->resource--; -+ /* Update 'curr' in data structure */ -+ pQueueCtrl->pCurrentDescr = RX_NEXT_DESC_PTR(pRxCurrDesc, pQueueCtrl); -+ -+#ifdef INCLUDE_SYNC_BARR -+ mvCpuIfSyncBarr(DRAM_TARGET); -+#endif -+ return pPktInfo; -+ } -+ else -+ { -+ ETH_RX_DESC* pRxUsedDesc = pQueueCtrl->pUsedDescr; -+ -+#ifdef ETH_DEBUG -+ mvOsPrintf("ethDrv: Unexpected Jumbo frame: " -+ "status=0x%08x, byteCnt=%d, pData=0x%x\n", -+ commandStatus, pRxCurrDesc->byteCnt, pRxCurrDesc->bufPtr); -+#endif /* ETH_DEBUG */ -+ -+ /* move buffer from pCurrentDescr position to pUsedDescr position */ -+ pRxUsedDesc->bufPtr = pRxCurrDesc->bufPtr; -+ pRxUsedDesc->returnInfo = pRxCurrDesc->returnInfo; -+ pRxUsedDesc->bufSize = pRxCurrDesc->bufSize & ETH_RX_BUFFER_MASK; -+ -+ /* Return the descriptor to DMA ownership */ -+ pRxUsedDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA | -+ ETH_RX_ENABLE_INTERRUPT_MASK; -+ -+ /* Flush descriptor and CPU pipe */ -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxUsedDesc); -+ -+ /* Move the used descriptor pointer to the next descriptor */ -+ pQueueCtrl->pUsedDescr = RX_NEXT_DESC_PTR(pRxUsedDesc, pQueueCtrl); -+ pQueueCtrl->pCurrentDescr = RX_NEXT_DESC_PTR(pRxCurrDesc, pQueueCtrl); -+ } -+ } -+} -+ -+/******************************************************************************* -+* mvEthPortRxDone - Returns a Rx buffer back to the Rx ring. -+* -+* DESCRIPTION: -+* This routine returns a Rx buffer back to the Rx ring. -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet Port handler. -+* int rxQueue - Number of Rx queue. -+* MV_PKT_INFO *pPktInfo - Pointer to received packet. -+* -+* RETURN: -+* MV_ERROR - Unexpected Fatal error. -+* MV_OUT_OF_RANGE - RX queue is already FULL, so this buffer can't be -+* returned to this queue. -+* MV_FULL - Buffer returned successfully and RX queue became full. -+* More buffers should not be returned at the time. -+* MV_OK - Buffer returned successfully and there are more free -+* places in the queue. -+* -+*******************************************************************************/ -+static INLINE MV_STATUS mvEthPortRxDone(void* pEthPortHndl, int rxQueue, MV_PKT_INFO *pPktInfo) -+{ -+ ETH_RX_DESC* pRxUsedDesc; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ -+ pQueueCtrl = &pPortCtrl->rxQueue[rxQueue]; -+ -+ /* Get 'used' Rx descriptor */ -+ pRxUsedDesc = pQueueCtrl->pUsedDescr; -+ -+ /* Check that ring is not FULL */ -+ if( (pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) && -+ (pQueueCtrl->resource != 0) ) -+ { -+ mvOsPrintf("%s %d: out of range Error resource=%d, curr=%p, used=%p\n", -+ __FUNCTION__, pPortCtrl->portNo, pQueueCtrl->resource, -+ pQueueCtrl->pCurrentDescr, pQueueCtrl->pUsedDescr); -+ return MV_OUT_OF_RANGE; -+ } -+ -+ pRxUsedDesc->bufPtr = pPktInfo->pFrags->bufPhysAddr; -+ pRxUsedDesc->returnInfo = (MV_ULONG)pPktInfo; -+ pRxUsedDesc->bufSize = pPktInfo->pFrags->bufSize & ETH_RX_BUFFER_MASK; -+ -+ /* Invalidate data buffer accordingly with pktSize */ -+ if(pPktInfo->pktSize != 0) -+ { -+ ETH_PACKET_CACHE_INVALIDATE(pPktInfo->pFrags->bufVirtPtr, pPktInfo->pktSize); -+ pPktInfo->pktSize = 0; -+ } -+ -+ /* Return the descriptor to DMA ownership */ -+ pRxUsedDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT_MASK; -+ -+ /* Flush descriptor and CPU pipe */ -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxUsedDesc); -+ -+ pQueueCtrl->resource++; -+ -+ /* Move the used descriptor pointer to the next descriptor */ -+ pQueueCtrl->pUsedDescr = RX_NEXT_DESC_PTR(pRxUsedDesc, pQueueCtrl); -+ -+ /* If ring became Full return MV_FULL */ -+ if(pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) -+ return MV_FULL; -+ -+ return MV_OK; -+} -+ -+ -+#endif /* __mvEthGbe_h__ */ -+ -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,700 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvEthRegsh -+#define __INCmvEthRegsh -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+ -+/****************************************/ -+/* Ethernet Unit Registers */ -+/****************************************/ -+#define ETH_REG_BASE MV_ETH_REG_BASE -+ -+#define ETH_PHY_ADDR_REG(port) (ETH_REG_BASE(port) + 0x000) -+#define ETH_SMI_REG(port) (ETH_REG_BASE(port) + 0x004) -+#define ETH_UNIT_DEF_ADDR_REG(port) (ETH_REG_BASE(port) + 0x008) -+#define ETH_UNIT_DEF_ID_REG(port) (ETH_REG_BASE(port) + 0x00c) -+#define ETH_UNIT_RESERVED(port) (ETH_REG_BASE(port) + 0x014) -+#define ETH_UNIT_INTR_CAUSE_REG(port) (ETH_REG_BASE(port) + 0x080) -+#define ETH_UNIT_INTR_MASK_REG(port) (ETH_REG_BASE(port) + 0x084) -+ -+ -+#define ETH_UNIT_ERROR_ADDR_REG(port) (ETH_REG_BASE(port) + 0x094) -+#define ETH_UNIT_INT_ADDR_ERROR_REG(port) (ETH_REG_BASE(port) + 0x098) -+#define ETH_UNIT_CONTROL_REG(port) (ETH_REG_BASE(port) + 0x0B0) -+ -+#define ETH_PORT_CONFIG_REG(port) (ETH_REG_BASE(port) + 0x400) -+#define ETH_PORT_CONFIG_EXTEND_REG(port) (ETH_REG_BASE(port) + 0x404) -+#define ETH_MII_SERIAL_PARAM_REG(port) (ETH_REG_BASE(port) + 0x408) -+#define ETH_GMII_SERIAL_PARAM_REG(port) (ETH_REG_BASE(port) + 0x40c) -+#define ETH_VLAN_ETHER_TYPE_REG(port) (ETH_REG_BASE(port) + 0x410) -+#define ETH_MAC_ADDR_LOW_REG(port) (ETH_REG_BASE(port) + 0x414) -+#define ETH_MAC_ADDR_HIGH_REG(port) (ETH_REG_BASE(port) + 0x418) -+#define ETH_SDMA_CONFIG_REG(port) (ETH_REG_BASE(port) + 0x41c) -+#define ETH_DIFF_SERV_PRIO_REG(port, code) (ETH_REG_BASE(port) + 0x420 + ((code)<<2)) -+#define ETH_PORT_SERIAL_CTRL_REG(port) (ETH_REG_BASE(port) + 0x43c) -+#define ETH_VLAN_TAG_TO_PRIO_REG(port) (ETH_REG_BASE(port) + 0x440) -+#define ETH_PORT_STATUS_REG(port) (ETH_REG_BASE(port) + 0x444) -+ -+#define ETH_RX_QUEUE_COMMAND_REG(port) (ETH_REG_BASE(port) + 0x680) -+#define ETH_TX_QUEUE_COMMAND_REG(port) (ETH_REG_BASE(port) + 0x448) -+ -+#define ETH_PORT_SERIAL_CTRL_1_REG(port) (ETH_REG_BASE(port) + 0x44c) -+#define ETH_PORT_STATUS_1_REG(port) (ETH_REG_BASE(port) + 0x450) -+#define ETH_PORT_MARVELL_HEADER_REG(port) (ETH_REG_BASE(port) + 0x454) -+#define ETH_PORT_FIFO_PARAMS_REG(port) (ETH_REG_BASE(port) + 0x458) -+#define ETH_MAX_TOKEN_BUCKET_SIZE_REG(port) (ETH_REG_BASE(port) + 0x45c) -+#define ETH_INTR_CAUSE_REG(port) (ETH_REG_BASE(port) + 0x460) -+#define ETH_INTR_CAUSE_EXT_REG(port) (ETH_REG_BASE(port) + 0x464) -+#define ETH_INTR_MASK_REG(port) (ETH_REG_BASE(port) + 0x468) -+#define ETH_INTR_MASK_EXT_REG(port) (ETH_REG_BASE(port) + 0x46c) -+#define ETH_TX_FIFO_URGENT_THRESH_REG(port) (ETH_REG_BASE(port) + 0x474) -+#define ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (ETH_REG_BASE(port) + 0x47c) -+#define ETH_RX_DISCARD_PKTS_CNTR_REG(port) (ETH_REG_BASE(port) + 0x484) -+#define ETH_RX_OVERRUN_PKTS_CNTR_REG(port) (ETH_REG_BASE(port) + 0x488) -+#define ETH_INTERNAL_ADDR_ERROR_REG(port) (ETH_REG_BASE(port) + 0x494) -+#define ETH_TX_FIXED_PRIO_CFG_REG(port) (ETH_REG_BASE(port) + 0x4dc) -+#define ETH_TX_TOKEN_RATE_CFG_REG(port) (ETH_REG_BASE(port) + 0x4e0) -+#define ETH_TX_QUEUE_COMMAND1_REG(port) (ETH_REG_BASE(port) + 0x4e4) -+#define ETH_MAX_TRANSMIT_UNIT_REG(port) (ETH_REG_BASE(port) + 0x4e8) -+#define ETH_TX_TOKEN_BUCKET_SIZE_REG(port) (ETH_REG_BASE(port) + 0x4ec) -+#define ETH_TX_TOKEN_BUCKET_COUNT_REG(port) (ETH_REG_BASE(port) + 0x780) -+#define ETH_RX_DESCR_STAT_CMD_REG(port, q) (ETH_REG_BASE(port) + 0x600 + ((q)<<4)) -+#define ETH_RX_BYTE_COUNT_REG(port, q) (ETH_REG_BASE(port) + 0x604 + ((q)<<4)) -+#define ETH_RX_BUF_PTR_REG(port, q) (ETH_REG_BASE(port) + 0x608 + ((q)<<4)) -+#define ETH_RX_CUR_DESC_PTR_REG(port, q) (ETH_REG_BASE(port) + 0x60c + ((q)<<4)) -+#define ETH_TX_CUR_DESC_PTR_REG(port, q) (ETH_REG_BASE(port) + 0x6c0 + ((q)<<2)) -+ -+#define ETH_TXQ_TOKEN_COUNT_REG(port, q) (ETH_REG_BASE(port) + 0x700 + ((q)<<4)) -+#define ETH_TXQ_TOKEN_CFG_REG(port, q) (ETH_REG_BASE(port) + 0x704 + ((q)<<4)) -+#define ETH_TXQ_ARBITER_CFG_REG(port, q) (ETH_REG_BASE(port) + 0x708 + ((q)<<4)) -+ -+#if (MV_ETH_VERSION >= 4) -+#define ETH_TXQ_CMD_1_REG(port) (ETH_REG_BASE(port) + 0x4E4) -+#define ETH_EJP_TX_HI_IPG_REG(port) (ETH_REG_BASE(port) + 0x7A8) -+#define ETH_EJP_TX_LO_IPG_REG(port) (ETH_REG_BASE(port) + 0x7B8) -+#define ETH_EJP_HI_TKN_LO_PKT_REG(port) (ETH_REG_BASE(port) + 0x7C0) -+#define ETH_EJP_HI_TKN_ASYNC_PKT_REG(port) (ETH_REG_BASE(port) + 0x7C4) -+#define ETH_EJP_LO_TKN_ASYNC_PKT_REG(port) (ETH_REG_BASE(port) + 0x7C8) -+#define ETH_EJP_TX_SPEED_REG(port) (ETH_REG_BASE(port) + 0x7D0) -+#endif /* MV_ETH_VERSION >= 4 */ -+ -+#define ETH_MIB_COUNTERS_BASE(port) (ETH_REG_BASE(port) + 0x1000) -+#define ETH_DA_FILTER_SPEC_MCAST_BASE(port) (ETH_REG_BASE(port) + 0x1400) -+#define ETH_DA_FILTER_OTH_MCAST_BASE(port) (ETH_REG_BASE(port) + 0x1500) -+#define ETH_DA_FILTER_UCAST_BASE(port) (ETH_REG_BASE(port) + 0x1600) -+ -+/* Phy address register definitions */ -+#define ETH_PHY_ADDR_OFFS 0 -+#define ETH_PHY_ADDR_MASK (0x1f <= 4) -+#define ETH_TX_EJP_RESET_BIT 0 -+#define ETH_TX_EJP_RESET_MASK (1 << ETH_TX_EJP_RESET_BIT) -+ -+#define ETH_TX_EJP_ENABLE_BIT 2 -+#define ETH_TX_EJP_ENABLE_MASK (1 << ETH_TX_EJP_ENABLE_BIT) -+ -+#define ETH_TX_LEGACY_WRR_BIT 3 -+#define ETH_TX_LEGACY_WRR_MASK (1 << ETH_TX_LEGACY_WRR_BIT) -+#endif /* (MV_ETH_VERSION >= 4) */ -+ -+/***** BITs of Ethernet Port Status reg (PSR) *****/ -+#define ETH_LINK_UP_BIT 1 -+#define ETH_LINK_UP_MASK (1<= 4) -+MV_STATUS mvEthEjpModeSet(void* pPortHandle, int mode); -+#endif /* (MV_ETH_VERSION >= 4) */ -+ -+void mvEthStatusGet(void* pPortHandle, MV_ETH_PORT_STATUS* pStatus); -+ -+/* Marvell Header control */ -+MV_STATUS mvEthHeaderModeSet(void* pPortHandle, MV_ETH_HEADER_MODE headerMode); -+ -+/* PHY routines */ -+void mvEthPhyAddrSet(void* pPortHandle, int phyAddr); -+int mvEthPhyAddrGet(void* pPortHandle); -+ -+/* Power management routines */ -+void mvEthPortPowerDown(int port); -+void mvEthPortPowerUp(int port); -+ -+/******************** ETH PRIVATE ************************/ -+ -+/*#define UNCACHED_TX_BUFFERS*/ -+/*#define UNCACHED_RX_BUFFERS*/ -+ -+ -+/* Port attributes */ -+/* Size of a Tx/Rx descriptor used in chain list data structure */ -+#define ETH_RX_DESC_ALIGNED_SIZE 32 -+#define ETH_TX_DESC_ALIGNED_SIZE 32 -+ -+#define TX_DISABLE_TIMEOUT_MSEC 1000 -+#define RX_DISABLE_TIMEOUT_MSEC 1000 -+#define TX_FIFO_EMPTY_TIMEOUT_MSEC 10000 -+#define PORT_DISABLE_WAIT_TCLOCKS 5000 -+ -+/* Macros that save access to desc in order to find next desc pointer */ -+#define RX_NEXT_DESC_PTR(pRxDescr, pQueueCtrl) \ -+ ((pRxDescr) == (pQueueCtrl)->pLastDescr) ? \ -+ (ETH_RX_DESC*)((pQueueCtrl)->pFirstDescr) : \ -+ (ETH_RX_DESC*)(((MV_ULONG)(pRxDescr)) + ETH_RX_DESC_ALIGNED_SIZE) -+ -+#define TX_NEXT_DESC_PTR(pTxDescr, pQueueCtrl) \ -+ ((pTxDescr) == (pQueueCtrl)->pLastDescr) ? \ -+ (ETH_TX_DESC*)((pQueueCtrl)->pFirstDescr) : \ -+ (ETH_TX_DESC*)(((MV_ULONG)(pTxDescr)) + ETH_TX_DESC_ALIGNED_SIZE) -+ -+#define RX_PREV_DESC_PTR(pRxDescr, pQueueCtrl) \ -+ ((pRxDescr) == (pQueueCtrl)->pFirstDescr) ? \ -+ (ETH_RX_DESC*)((pQueueCtrl)->pLastDescr) : \ -+ (ETH_RX_DESC*)(((MV_ULONG)(pRxDescr)) - ETH_RX_DESC_ALIGNED_SIZE) -+ -+#define TX_PREV_DESC_PTR(pTxDescr, pQueueCtrl) \ -+ ((pTxDescr) == (pQueueCtrl)->pFirstDescr) ? \ -+ (ETH_TX_DESC*)((pQueueCtrl)->pLastDescr) : \ -+ (ETH_TX_DESC*)(((MV_ULONG)(pTxDescr)) - ETH_TX_DESC_ALIGNED_SIZE) -+ -+ -+/* Queue specific information */ -+typedef struct -+{ -+ void* pFirstDescr; -+ void* pLastDescr; -+ void* pCurrentDescr; -+ void* pUsedDescr; -+ int resource; -+ MV_BUF_INFO descBuf; -+} ETH_QUEUE_CTRL; -+ -+ -+/* Ethernet port specific infomation */ -+typedef struct _ethPortCtrl -+{ -+ int portNo; -+ ETH_QUEUE_CTRL rxQueue[MV_ETH_RX_Q_NUM]; /* Rx ring resource */ -+ ETH_QUEUE_CTRL txQueue[MV_ETH_TX_Q_NUM]; /* Tx ring resource */ -+ -+ MV_ETH_PORT_CFG portConfig; -+ MV_ETH_RX_Q_CFG rxQueueConfig[MV_ETH_RX_Q_NUM]; -+ MV_ETH_TX_Q_CFG txQueueConfig[MV_ETH_TX_Q_NUM]; -+ -+ /* Register images - For DP */ -+ MV_U32 portTxQueueCmdReg; /* Port active Tx queues summary */ -+ MV_U32 portRxQueueCmdReg; /* Port active Rx queues summary */ -+ -+ MV_STATE portState; -+ -+ MV_U8 mcastCount[256]; -+ MV_U32* hashPtr; -+ void *osHandle; -+} ETH_PORT_CTRL; -+ -+/************** MACROs ****************/ -+ -+/* MACROs to Flush / Invalidate TX / RX Buffers */ -+#if (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) && !defined(UNCACHED_TX_BUFFERS) -+# define ETH_PACKET_CACHE_FLUSH(pAddr, size) \ -+ mvOsCacheClear(NULL, (pAddr), (size)); \ -+ /*CPU_PIPE_FLUSH;*/ -+#else -+# define ETH_PACKET_CACHE_FLUSH(pAddr, size) \ -+ mvOsIoVirtToPhy(NULL, (pAddr)); -+#endif /* ETHER_DRAM_COHER == MV_CACHE_COHER_SW */ -+ -+#if ( (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) && !defined(UNCACHED_RX_BUFFERS) ) -+# define ETH_PACKET_CACHE_INVALIDATE(pAddr, size) \ -+ mvOsCacheInvalidate (NULL, (pAddr), (size)); \ -+ /*CPU_PIPE_FLUSH;*/ -+#else -+# define ETH_PACKET_CACHE_INVALIDATE(pAddr, size) -+#endif /* ETHER_DRAM_COHER == MV_CACHE_COHER_SW && !UNCACHED_RX_BUFFERS */ -+ -+#ifdef ETH_DESCR_UNCACHED -+ -+#define ETH_DESCR_FLUSH_INV(pPortCtrl, pDescr) -+#define ETH_DESCR_INV(pPortCtrl, pDescr) -+ -+#else -+ -+#define ETH_DESCR_FLUSH_INV(pPortCtrl, pDescr) \ -+ mvOsCacheLineFlushInv(pPortCtrl->osHandle, (MV_ULONG)(pDescr)) -+ -+#define ETH_DESCR_INV(pPortCtrl, pDescr) \ -+ mvOsCacheLineInv(pPortCtrl->osHandle, (MV_ULONG)(pDescr)) -+ -+#endif /* ETH_DESCR_UNCACHED */ -+ -+#include "eth/gbe/mvEthGbe.h" -+ -+#endif /* __mvEth_h__ */ -+ -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.c ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.c 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,362 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "gpp/mvGpp.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+static MV_VOID gppRegSet(MV_U32 group, MV_U32 regOffs,MV_U32 mask,MV_U32 value); -+ -+/******************************************************************************* -+* mvGppTypeSet - Enable a GPP (OUT) pin -+* -+* DESCRIPTION: -+* -+* INPUT: -+* group - GPP group number -+* mask - 32bit mask value. Each set bit in the mask means that the type -+* of corresponding GPP will be set. Other GPPs are ignored. -+* value - 32bit value that describes GPP type per pin. -+* -+* OUTPUT: -+* None. -+* -+* EXAMPLE: -+* Set GPP8 to input and GPP15 to output. -+* mvGppTypeSet(0, (GPP8 | GPP15), -+* ((MV_GPP_IN & GPP8) | (MV_GPP_OUT & GPP15)) ); -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvGppTypeSet(MV_U32 group, MV_U32 mask, MV_U32 value) -+{ -+ if (group >= MV_GPP_MAX_GROUP) -+ { -+ DB(mvOsPrintf("mvGppTypeSet: ERR. invalid group number \n")); -+ return MV_BAD_PARAM; -+ } -+ -+ gppRegSet(group, GPP_DATA_OUT_EN_REG(group), mask, value); -+ -+ /* Workaround for Erratum FE-MISC-70*/ -+ if(mvCtrlRevGet()==MV_88F6XXX_A0_REV && (group == 1)) -+ { -+ mask &= 0x2; -+ gppRegSet(0, GPP_DATA_OUT_EN_REG(0), mask, value); -+ } /*End of WA*/ -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvGppBlinkEn - Set a GPP (IN) Pin list to blink every ~100ms -+* -+* DESCRIPTION: -+* -+* INPUT: -+* group - GPP group number -+* mask - 32bit mask value. Each set bit in the mask means that the type -+* of corresponding GPP will be set. Other GPPs are ignored. -+* value - 32bit value that describes GPP blink per pin. -+* -+* OUTPUT: -+* None. -+* -+* EXAMPLE: -+* Set GPP8 to be static and GPP15 to be blinking. -+* mvGppBlinkEn(0, (GPP8 | GPP15), -+* ((MV_GPP_OUT_STATIC & GPP8) | (MV_GPP_OUT_BLINK & GPP15)) ); -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvGppBlinkEn(MV_U32 group, MV_U32 mask, MV_U32 value) -+{ -+ if (group >= MV_GPP_MAX_GROUP) -+ { -+ DB(mvOsPrintf("mvGppBlinkEn: ERR. invalid group number \n")); -+ return MV_BAD_PARAM; -+ } -+ -+ gppRegSet(group, GPP_BLINK_EN_REG(group), mask, value); -+ -+ return MV_OK; -+ -+} -+/******************************************************************************* -+* mvGppPolaritySet - Set a GPP (IN) Pin list Polarity mode -+* -+* DESCRIPTION: -+* -+* INPUT: -+* group - GPP group number -+* mask - 32bit mask value. Each set bit in the mask means that the type -+* of corresponding GPP will be set. Other GPPs are ignored. -+* value - 32bit value that describes GPP polarity per pin. -+* -+* OUTPUT: -+* None. -+* -+* EXAMPLE: -+* Set GPP8 to the actual pin value and GPP15 to be inverted. -+* mvGppPolaritySet(0, (GPP8 | GPP15), -+* ((MV_GPP_IN_ORIGIN & GPP8) | (MV_GPP_IN_INVERT & GPP15)) ); -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvGppPolaritySet(MV_U32 group, MV_U32 mask, MV_U32 value) -+{ -+ if (group >= MV_GPP_MAX_GROUP) -+ { -+ DB(mvOsPrintf("mvGppPolaritySet: ERR. invalid group number \n")); -+ return MV_BAD_PARAM; -+ } -+ -+ gppRegSet(group, GPP_DATA_IN_POL_REG(group), mask, value); -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvGppPolarityGet - Get a value of relevant bits from GPP Polarity register. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* group - GPP group number -+* mask - 32bit mask value. Each set bit in the mask means that the -+* returned value is valid for it. -+* -+* OUTPUT: -+* None. -+* -+* EXAMPLE: -+* Get GPP8 and GPP15 value. -+* mvGppPolarityGet(0, (GPP8 | GPP15)); -+* -+* RETURN: -+* 32bit value that describes GPP polatity mode per pin. -+* -+*******************************************************************************/ -+MV_U32 mvGppPolarityGet(MV_U32 group, MV_U32 mask) -+{ -+ MV_U32 regVal; -+ -+ if (group >= MV_GPP_MAX_GROUP) -+ { -+ DB(mvOsPrintf("mvGppActiveSet: Error invalid group number \n")); -+ return MV_ERROR; -+ } -+ regVal = MV_REG_READ(GPP_DATA_IN_POL_REG(group)); -+ -+ return (regVal & mask); -+} -+ -+/******************************************************************************* -+* mvGppValueGet - Get a GPP Pin list value. -+* -+* DESCRIPTION: -+* This function get GPP value. -+* -+* INPUT: -+* group - GPP group number -+* mask - 32bit mask value. Each set bit in the mask means that the -+* returned value is valid for it. -+* -+* OUTPUT: -+* None. -+* -+* EXAMPLE: -+* Get GPP8 and GPP15 value. -+* mvGppValueGet(0, (GPP8 | GPP15)); -+* -+* RETURN: -+* 32bit value that describes GPP activity mode per pin. -+* -+*******************************************************************************/ -+MV_U32 mvGppValueGet(MV_U32 group, MV_U32 mask) -+{ -+ MV_U32 gppData; -+ -+ gppData = MV_REG_READ(GPP_DATA_IN_REG(group)); -+ -+ gppData &= mask; -+ -+ return gppData; -+ -+} -+ -+/******************************************************************************* -+* mvGppValueSet - Set a GPP Pin list value. -+* -+* DESCRIPTION: -+* This function set value for given GPP pin list. -+* -+* INPUT: -+* group - GPP group number -+* mask - 32bit mask value. Each set bit in the mask means that the -+* value of corresponding GPP will be set accordingly. Other GPP -+* are not affected. -+* value - 32bit value that describes GPP value per pin. -+* -+* OUTPUT: -+* None. -+* -+* EXAMPLE: -+* Set GPP8 value of '0' and GPP15 value of '1'. -+* mvGppActiveSet(0, (GPP8 | GPP15), ((0 & GPP8) | (GPP15)) ); -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvGppValueSet (MV_U32 group, MV_U32 mask, MV_U32 value) -+{ -+ MV_U32 outEnable, tmp; -+ MV_U32 i; -+ -+ if (group >= MV_GPP_MAX_GROUP) -+ { -+ DB(mvOsPrintf("mvGppValueSet: Error invalid group number \n")); -+ return MV_BAD_PARAM; -+ } -+ -+ /* verify that the gpp pin is configured as output */ -+ /* Note that in the register out enabled -> bit = '0'. */ -+ outEnable = ~MV_REG_READ(GPP_DATA_OUT_EN_REG(group)); -+ -+ /* Workaround for Erratum FE-MISC-70*/ -+ if(mvCtrlRevGet()==MV_88F6XXX_A0_REV && (group == 1)) -+ { -+ tmp = ~MV_REG_READ(GPP_DATA_OUT_EN_REG(0)); -+ outEnable &= 0xfffffffd; -+ outEnable |= (tmp & 0x2); -+ } /*End of WA*/ -+ -+ for (i = 0 ; i < 32 ;i++) -+ { -+ if (((mask & (1 << i)) & (outEnable & (1 << i))) != (mask & (1 << i))) -+ { -+ mvOsPrintf("mvGppValueSet: Err. An attempt to set output "\ -+ "value to GPP %d in input mode.\n", i); -+ return MV_ERROR; -+ } -+ } -+ -+ gppRegSet(group, GPP_DATA_OUT_REG(group), mask, value); -+ -+ return MV_OK; -+ -+} -+/******************************************************************************* -+* gppRegSet - Set a specific GPP pin on a specific GPP register -+* -+* DESCRIPTION: -+* This function set a specific GPP pin on a specific GPP register -+* -+* INPUT: -+* regOffs - GPP Register offset -+* group - GPP group number -+* mask - 32bit mask value. Each set bit in the mask means that the -+* value of corresponding GPP will be set accordingly. Other GPP -+* are not affected. -+* value - 32bit value that describes GPP value per pin. -+* -+* OUTPUT: -+* None. -+* -+* EXAMPLE: -+* Set GPP8 value of '0' and GPP15 value of '1'. -+* mvGppActiveSet(0, (GPP8 | GPP15), ((0 & GPP8) | (1 & GPP15)) ); -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+static MV_VOID gppRegSet (MV_U32 group, MV_U32 regOffs,MV_U32 mask,MV_U32 value) -+{ -+ MV_U32 gppData; -+ -+ gppData = MV_REG_READ(regOffs); -+ -+ gppData &= ~mask; -+ -+ gppData |= (value & mask); -+ -+ MV_REG_WRITE(regOffs, gppData); -+} -+ -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,118 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvGppH -+#define __INCmvGppH -+ -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+#include "gpp/mvGppRegs.h" -+ -+/* These macros describes the GPP type. Each of the GPPs pins can */ -+/* be assigned to act as a general purpose input or output pin. */ -+#define MV_GPP_IN 0xFFFFFFFF /* GPP input */ -+#define MV_GPP_OUT 0 /* GPP output */ -+ -+ -+/* These macros describes the GPP Out Enable. */ -+#define MV_GPP_OUT_DIS 0xFFFFFFFF /* Out pin disabled*/ -+#define MV_GPP_OUT_EN 0 /* Out pin enabled*/ -+ -+/* These macros describes the GPP Out Blinking. */ -+/* When set and the corresponding bit in GPIO Data Out Enable Control */ -+/* Register is enabled, the GPIO pin blinks every ~100 ms (a period of */ -+/* 2^24 TCLK clocks). */ -+#define MV_GPP_OUT_BLINK 0xFFFFFFFF /* Out pin blinking*/ -+#define MV_GPP_OUT_STATIC 0 /* Out pin static*/ -+ -+ -+/* These macros describes the GPP Polarity. */ -+/* When set to 1 GPIO Data In Register reflects the inverted value of the */ -+/* corresponding pin. */ -+ -+#define MV_GPP_IN_INVERT 0xFFFFFFFF /* Inverted value is got*/ -+#define MV_GPP_IN_ORIGIN 0 /* original value is got*/ -+ -+/* mvGppTypeSet - Set PP pin mode (IN or OUT) */ -+MV_STATUS mvGppTypeSet(MV_U32 group, MV_U32 mask, MV_U32 value); -+ -+/* mvGppBlinkEn - Set a GPP (IN) Pin list to blink every ~100ms */ -+MV_STATUS mvGppBlinkEn(MV_U32 group, MV_U32 mask, MV_U32 value); -+ -+/* mvGppPolaritySet - Set a GPP (IN) Pin list Polarity mode. */ -+MV_STATUS mvGppPolaritySet(MV_U32 group, MV_U32 mask, MV_U32 value); -+ -+/* mvGppPolarityGet - Get the Polarity of a GPP Pin */ -+MV_U32 mvGppPolarityGet(MV_U32 group, MV_U32 mask); -+ -+/* mvGppValueGet - Get a GPP Pin list value.*/ -+MV_U32 mvGppValueGet(MV_U32 group, MV_U32 mask); -+ -+ -+/* mvGppValueSet - Set a GPP Pin list value. */ -+MV_STATUS mvGppValueSet (MV_U32 group, MV_U32 mask, MV_U32 value); -+ -+#endif /* #ifndef __INCmvGppH */ -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGppRegs.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGppRegs.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGppRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGppRegs.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,116 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvGppRegsH -+#define __INCmvGppRegsH -+ -+#define MV_GPP0 BIT0 -+#define MV_GPP1 BIT1 -+#define MV_GPP2 BIT2 -+#define MV_GPP3 BIT3 -+#define MV_GPP4 BIT4 -+#define MV_GPP5 BIT5 -+#define MV_GPP6 BIT6 -+#define MV_GPP7 BIT7 -+#define MV_GPP8 BIT8 -+#define MV_GPP9 BIT9 -+#define MV_GPP10 BIT10 -+#define MV_GPP11 BIT11 -+#define MV_GPP12 BIT12 -+#define MV_GPP13 BIT13 -+#define MV_GPP14 BIT14 -+#define MV_GPP15 BIT15 -+#define MV_GPP16 BIT16 -+#define MV_GPP17 BIT17 -+#define MV_GPP18 BIT18 -+#define MV_GPP19 BIT19 -+#define MV_GPP20 BIT20 -+#define MV_GPP21 BIT21 -+#define MV_GPP22 BIT22 -+#define MV_GPP23 BIT23 -+#define MV_GPP24 BIT24 -+#define MV_GPP25 BIT25 -+#define MV_GPP26 BIT26 -+#define MV_GPP27 BIT27 -+#define MV_GPP28 BIT28 -+#define MV_GPP29 BIT29 -+#define MV_GPP30 BIT30 -+#define MV_GPP31 BIT31 -+ -+ -+/* registers offsets */ -+ -+#define GPP_DATA_OUT_REG(grp) ((grp == 0) ? 0x10100 : 0x10140) -+#define GPP_DATA_OUT_EN_REG(grp) ((grp == 0) ? 0x10104 : 0x10144) -+#define GPP_BLINK_EN_REG(grp) ((grp == 0) ? 0x10108 : 0x10148) -+#define GPP_DATA_IN_POL_REG(grp) ((grp == 0) ? 0x1010C : 0x1014c) -+#define GPP_DATA_IN_REG(grp) ((grp == 0) ? 0x10110 : 0x10150) -+#define GPP_INT_CAUSE_REG(grp) ((grp == 0) ? 0x10114 : 0x10154) -+#define GPP_INT_MASK_REG(grp) ((grp == 0) ? 0x10118 : 0x10158) -+#define GPP_INT_LVL_REG(grp) ((grp == 0) ? 0x1011c : 0x1015c) -+ -+#define GPP_DATA_OUT_SET_REG 0x10120 -+#define GPP_DATA_OUT_CLEAR_REG 0x10124 -+ -+#endif /* #ifndef __INCmvGppRegsH */ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.c ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.c 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,1047 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#include "pci/mvPci.h" -+ -+#include "ctrlEnv/mvCtrlEnvLib.h" -+ -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+ -+ -+MV_VOID mvPciHalInit(MV_U32 pciIf, MV_PCI_MOD pciIfmod) -+{ -+ if (MV_PCI_MOD_HOST == pciIfmod) -+ { -+ -+ mvPciLocalBusNumSet(pciIf, PCI_HOST_BUS_NUM(pciIf)); -+ mvPciLocalDevNumSet(pciIf, PCI_HOST_DEV_NUM(pciIf)); -+ -+ /* Local device master Enable */ -+ mvPciMasterEnable(pciIf, MV_TRUE); -+ -+ /* Local device slave Enable */ -+ mvPciSlaveEnable(pciIf, mvPciLocalBusNumGet(pciIf), -+ mvPciLocalDevNumGet(pciIf), MV_TRUE); -+ } -+ /* enable CPU-2-PCI ordering */ -+ MV_REG_BIT_SET(PCI_CMD_REG(0), PCR_CPU_TO_PCI_ORDER_EN); -+} -+ -+/******************************************************************************* -+* mvPciCommandSet - Set PCI comman register value. -+* -+* DESCRIPTION: -+* This function sets a given PCI interface with its command register -+* value. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* command - 32bit value to be written to comamnd register. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM if pciIf is not in range otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciCommandSet(MV_U32 pciIf, MV_U32 command) -+{ -+ MV_U32 locBusNum, locDevNum, regVal; -+ -+ locBusNum = mvPciLocalBusNumGet(pciIf); -+ locDevNum = mvPciLocalDevNumGet(pciIf); -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciCommandSet: ERR. Invalid PCI IF num %d\n", pciIf); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Set command register */ -+ MV_REG_WRITE(PCI_CMD_REG(pciIf), command); -+ -+ /* Upodate device max outstanding split tarnsaction */ -+ if ((command & PCR_CPU_TO_PCI_ORDER_EN) && -+ (command & PCR_PCI_TO_CPU_ORDER_EN)) -+ { -+ /* Read PCI-X command register */ -+ regVal = mvPciConfigRead (pciIf, locBusNum, locDevNum, 0, PCIX_COMMAND); -+ -+ /* clear bits 22:20 */ -+ regVal &= 0xff8fffff; -+ -+ /* set reset value */ -+ regVal |= (0x3 << 20); -+ -+ /* Write back the value */ -+ mvPciConfigWrite (pciIf, locBusNum, locDevNum, 0, PCIX_COMMAND, regVal); -+ } -+ -+ return MV_OK; -+ -+ -+} -+ -+ -+/******************************************************************************* -+* mvPciModeGet - Get PCI interface mode. -+* -+* DESCRIPTION: -+* This function returns the given PCI interface mode. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* -+* OUTPUT: -+* pPciMode - Pointer to PCI mode structure. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciModeGet(MV_U32 pciIf, MV_PCI_MODE *pPciMode) -+{ -+ MV_U32 pciMode; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciModeGet: ERR. Invalid PCI interface %d\n", pciIf); -+ return MV_BAD_PARAM; -+ } -+ if (NULL == pPciMode) -+ { -+ mvOsPrintf("mvPciModeGet: ERR. pPciMode = NULL \n"); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Read pci mode register */ -+ pciMode = MV_REG_READ(PCI_MODE_REG(pciIf)); -+ -+ switch (pciMode & PMR_PCI_MODE_MASK) -+ { -+ case PMR_PCI_MODE_CONV: -+ pPciMode->pciType = MV_PCI_CONV; -+ -+ if (MV_REG_READ(PCI_DLL_CTRL_REG(pciIf)) & PDC_DLL_EN) -+ { -+ pPciMode->pciSpeed = 66000000; /* 66MHZ */ -+ } -+ else -+ { -+ pPciMode->pciSpeed = 33000000; /* 33MHZ */ -+ } -+ -+ break; -+ -+ case PMR_PCI_MODE_PCIX_66MHZ: -+ pPciMode->pciType = MV_PCIX; -+ pPciMode->pciSpeed = 66000000; /* 66MHZ */ -+ break; -+ -+ case PMR_PCI_MODE_PCIX_100MHZ: -+ pPciMode->pciType = MV_PCIX; -+ pPciMode->pciSpeed = 100000000; /* 100MHZ */ -+ break; -+ -+ case PMR_PCI_MODE_PCIX_133MHZ: -+ pPciMode->pciType = MV_PCIX; -+ pPciMode->pciSpeed = 133000000; /* 133MHZ */ -+ break; -+ -+ default: -+ { -+ mvOsPrintf("mvPciModeGet: ERR. Non existing mode !!\n"); -+ return MV_ERROR; -+ } -+ } -+ -+ switch (pciMode & PMR_PCI_64_MASK) -+ { -+ case PMR_PCI_64_64BIT: -+ pPciMode->pciWidth = MV_PCI_64; -+ break; -+ -+ case PMR_PCI_64_32BIT: -+ pPciMode->pciWidth = MV_PCI_32; -+ break; -+ -+ default: -+ { -+ mvOsPrintf("mvPciModeGet: ERR. Non existing mode !!\n"); -+ return MV_ERROR; -+ } -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvPciRetrySet - Set PCI retry counters -+* -+* DESCRIPTION: -+* This function specifies the number of times the PCI controller -+* retries a transaction before it quits. -+* Applies to the PCI Master when acting as a requester. -+* Applies to the PCI slave when acting as a completer (PCI-X mode). -+* A 0x00 value means a "retry forever". -+* -+* INPUT: -+* pciIf - PCI interface number. -+* counter - Number of times PCI controller retry. Use counter value -+* up to PRR_RETRY_CNTR_MAX. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciRetrySet(MV_U32 pciIf, MV_U32 counter) -+{ -+ MV_U32 pciRetry; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciRetrySet: ERR. Invalid PCI interface %d\n", pciIf); -+ return MV_BAD_PARAM; -+ } -+ -+ if (counter >= PRR_RETRY_CNTR_MAX) -+ { -+ mvOsPrintf("mvPciRetrySet: ERR. Invalid counter: %d\n", counter); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ /* Reading PCI retry register */ -+ pciRetry = MV_REG_READ(PCI_RETRY_REG(pciIf)); -+ -+ pciRetry &= ~PRR_RETRY_CNTR_MASK; -+ -+ pciRetry |= (counter << PRR_RETRY_CNTR_OFFS); -+ -+ /* write new value */ -+ MV_REG_WRITE(PCI_RETRY_REG(pciIf), pciRetry); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPciDiscardTimerSet - Set PCI discard timer -+* -+* DESCRIPTION: -+* This function set PCI discard timer. -+* In conventional PCI mode: -+* Specifies the number of PCLK cycles the PCI slave keeps a non-accessed -+* read buffers (non-completed delayed read) before invalidate the buffer. -+* Set to '0' to disable the timer. The PCI slave waits for delayed -+* read completion forever. -+* In PCI-X mode: -+* Specifies the number of PCLK cycles the PCI master waits for split -+* completion transaction, before it invalidates the pre-allocated read -+* buffer. -+* Set to '0' to disable the timer. The PCI master waits for split -+* completion forever. -+* NOTE: Must be set to a number greater than MV_PCI_MAX_DISCARD_CLK, -+* unless using the "wait for ever" setting 0x0. -+* NOTE: Must not be updated while there are pending read requests. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* pClkCycles - Number of PCI clock cycles. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciDiscardTimerSet(MV_U32 pciIf, MV_U32 pClkCycles) -+{ -+ MV_U32 pciDiscardTimer; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciDiscardTimerSet: ERR. Invalid PCI interface %d\n", -+ pciIf); -+ return MV_BAD_PARAM; -+ } -+ -+ if (pClkCycles >= PDTR_TIMER_MIN) -+ { -+ mvOsPrintf("mvPciDiscardTimerSet: ERR. Invalid Clk value: %d\n", -+ pClkCycles); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ /* Read PCI Discard Timer */ -+ pciDiscardTimer = MV_REG_READ(PCI_DISCARD_TIMER_REG(pciIf)); -+ -+ pciDiscardTimer &= ~PDTR_TIMER_MASK; -+ -+ pciDiscardTimer |= (pClkCycles << PDTR_TIMER_OFFS); -+ -+ /* Write new value */ -+ MV_REG_WRITE(PCI_DISCARD_TIMER_REG(pciIf), pciDiscardTimer); -+ -+ return MV_OK; -+ -+} -+ -+/* PCI Arbiter routines */ -+ -+/******************************************************************************* -+* mvPciArbEnable - PCI arbiter enable/disable -+* -+* DESCRIPTION: -+* This fuction enable/disables a given PCI interface arbiter. -+* NOTE: Arbiter setting can not be changed while in work. It should only -+* be set once. -+* INPUT: -+* pciIf - PCI interface number. -+* enable - Enable/disable parameter. If enable = MV_TRUE then enable. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvPciArbEnable(MV_U32 pciIf, MV_BOOL enable) -+{ -+ MV_U32 regVal; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciArbEnable: ERR. Invalid PCI interface %d\n", pciIf); -+ return MV_ERROR; -+ } -+ -+ /* Set PCI Arbiter Control register according to default configuration */ -+ regVal = MV_REG_READ(PCI_ARBITER_CTRL_REG(pciIf)); -+ -+ /* Make sure arbiter disabled before changing its values */ -+ MV_REG_BIT_RESET(PCI_ARBITER_CTRL_REG(pciIf), PACR_ARB_ENABLE); -+ -+ regVal &= ~PCI_ARBITER_CTRL_DEFAULT_MASK; -+ -+ regVal |= PCI_ARBITER_CTRL_DEFAULT; /* Set default configuration */ -+ -+ if (MV_TRUE == enable) -+ { -+ regVal |= PACR_ARB_ENABLE; -+ } -+ else -+ { -+ regVal &= ~PACR_ARB_ENABLE; -+ } -+ -+ /* Write to register */ -+ MV_REG_WRITE(PCI_ARBITER_CTRL_REG(pciIf), regVal); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPciArbParkDis - Disable arbiter parking on agent -+* -+* DESCRIPTION: -+* This function disables the PCI arbiter from parking on the given agent -+* list. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* pciAgentMask - When a bit in the mask is set to '1', parking on -+* the associated PCI master is disabled. Mask bit -+* refers to bit 0 - 6. For example disable parking on PCI -+* agent 3 set pciAgentMask 0x4 (bit 3 is set). -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvPciArbParkDis(MV_U32 pciIf, MV_U32 pciAgentMask) -+{ -+ MV_U32 pciArbiterCtrl; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciArbParkDis: ERR. Invalid PCI interface %d\n", pciIf); -+ return MV_ERROR; -+ } -+ -+ /* Reading Arbiter Control register */ -+ pciArbiterCtrl = MV_REG_READ(PCI_ARBITER_CTRL_REG(pciIf)); -+ -+ /* Arbiter must be disabled before changing parking */ -+ MV_REG_BIT_RESET(PCI_ARBITER_CTRL_REG(pciIf), PACR_ARB_ENABLE); -+ -+ /* do the change */ -+ pciArbiterCtrl &= ~PACR_PARK_DIS_MASK; -+ pciArbiterCtrl |= (pciAgentMask << PACR_PARK_DIS_OFFS); -+ -+ /* writing new value ( if th earbiter was enabled before the change */ -+ /* here it will be reenabled */ -+ MV_REG_WRITE(PCI_ARBITER_CTRL_REG(pciIf), pciArbiterCtrl); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPciArbBrokDetectSet - Set PCI arbiter broken detection -+* -+* DESCRIPTION: -+* This function sets the maximum number of cycles that the arbiter -+* waits for a PCI master to respond to its grant assertion. If a -+* PCI agent fails to respond within this time, the PCI arbiter aborts -+* the transaction and performs a new arbitration cycle. -+* NOTE: Value must be greater than '1' for conventional PCI and -+* greater than '5' for PCI-X. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* pClkCycles - Number of PCI clock cycles. If equal to '0' the broken -+* master detection is disabled. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciArbBrokDetectSet(MV_U32 pciIf, MV_U32 pClkCycles) -+{ -+ MV_U32 pciArbiterCtrl; -+ MV_U32 pciMode; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciArbBrokDetectSet: ERR. Invalid PCI interface %d\n", -+ pciIf); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Checking PCI mode and if pClkCycles is legal value */ -+ pciMode = MV_REG_READ(PCI_MODE_REG(pciIf)); -+ pciMode &= PMR_PCI_MODE_MASK; -+ -+ if (PMR_PCI_MODE_CONV == pciMode) -+ { -+ if (pClkCycles < PACR_BROKEN_VAL_CONV_MIN) -+ return MV_ERROR; -+ } -+ else -+ { -+ if (pClkCycles < PACR_BROKEN_VAL_PCIX_MIN) -+ return MV_ERROR; -+ } -+ -+ pClkCycles <<= PACR_BROKEN_VAL_OFFS; -+ -+ /* Reading Arbiter Control register */ -+ pciArbiterCtrl = MV_REG_READ(PCI_ARBITER_CTRL_REG(pciIf)); -+ pciArbiterCtrl &= ~PACR_BROKEN_VAL_MASK; -+ pciArbiterCtrl |= pClkCycles; -+ -+ /* Arbiter must be disabled before changing broken detection */ -+ MV_REG_BIT_RESET(PCI_ARBITER_CTRL_REG(pciIf), PACR_ARB_ENABLE); -+ -+ /* writing new value ( if th earbiter was enabled before the change */ -+ /* here it will be reenabled */ -+ -+ MV_REG_WRITE(PCI_ARBITER_CTRL_REG(pciIf), pciArbiterCtrl); -+ -+ return MV_OK; -+} -+ -+/* PCI configuration space read write */ -+ -+/******************************************************************************* -+* mvPciConfigRead - Read from configuration space -+* -+* DESCRIPTION: -+* This function performs a 32 bit read from PCI configuration space. -+* It supports both type 0 and type 1 of Configuration Transactions -+* (local and over bridge). In order to read from local bus segment, use -+* bus number retrieved from mvPciLocalBusNumGet(). Other bus numbers -+* will result configuration transaction of type 1 (over bridge). -+* -+* INPUT: -+* pciIf - PCI interface number. -+* bus - PCI segment bus number. -+* dev - PCI device number. -+* func - Function number. -+* regOffs - Register offset. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit register data, 0xffffffff on error -+* -+*******************************************************************************/ -+MV_U32 mvPciConfigRead (MV_U32 pciIf, MV_U32 bus, MV_U32 dev, MV_U32 func, -+ MV_U32 regOff) -+{ -+ MV_U32 pciData = 0; -+ -+ /* Parameter checking */ -+ if (PCI_DEFAULT_IF != pciIf) -+ { -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciConfigRead: ERR. Invalid PCI interface %d\n",pciIf); -+ return 0xFFFFFFFF; -+ } -+ } -+ -+ if (dev >= MAX_PCI_DEVICES) -+ { -+ DB(mvOsPrintf("mvPciConfigRead: ERR. device number illigal %d\n", dev)); -+ return 0xFFFFFFFF; -+ } -+ -+ if (func >= MAX_PCI_FUNCS) -+ { -+ DB(mvOsPrintf("mvPciConfigRead: ERR. function number illigal %d\n", func)); -+ return 0xFFFFFFFF; -+ } -+ -+ if (bus >= MAX_PCI_BUSSES) -+ { -+ DB(mvOsPrintf("mvPciConfigRead: ERR. bus number illigal %d\n", bus)); -+ return MV_ERROR; -+ } -+ -+ -+ /* Creating PCI address to be passed */ -+ pciData |= (bus << PCAR_BUS_NUM_OFFS); -+ pciData |= (dev << PCAR_DEVICE_NUM_OFFS); -+ pciData |= (func << PCAR_FUNC_NUM_OFFS); -+ pciData |= (regOff & PCAR_REG_NUM_MASK); -+ -+ pciData |= PCAR_CONFIG_EN; -+ -+ /* Write the address to the PCI configuration address register */ -+ MV_REG_WRITE(PCI_CONFIG_ADDR_REG(pciIf), pciData); -+ -+ /* In order to let the PCI controller absorbed the address of the read */ -+ /* transaction we perform a validity check that the address was written */ -+ if(pciData != MV_REG_READ(PCI_CONFIG_ADDR_REG(pciIf))) -+ { -+ return MV_ERROR; -+ } -+ /* Read the Data returned in the PCI Data register */ -+ pciData = MV_REG_READ(PCI_CONFIG_DATA_REG(pciIf)); -+ -+ return pciData; -+} -+ -+/******************************************************************************* -+* mvPciConfigWrite - Write to configuration space -+* -+* DESCRIPTION: -+* This function performs a 32 bit write to PCI configuration space. -+* It supports both type 0 and type 1 of Configuration Transactions -+* (local and over bridge). In order to write to local bus segment, use -+* bus number retrieved from mvPciLocalBusNumGet(). Other bus numbers -+* will result configuration transaction of type 1 (over bridge). -+* -+* INPUT: -+* pciIf - PCI interface number. -+* bus - PCI segment bus number. -+* dev - PCI device number. -+* func - Function number. -+* regOffs - Register offset. -+* data - 32bit data. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciConfigWrite(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data) -+{ -+ MV_U32 pciData = 0; -+ -+ /* Parameter checking */ -+ if (PCI_DEFAULT_IF != pciIf) -+ { -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciConfigWrite: ERR. Invalid PCI interface %d\n", -+ pciIf); -+ return 0xFFFFFFFF; -+ } -+ } -+ -+ if (dev >= MAX_PCI_DEVICES) -+ { -+ mvOsPrintf("mvPciConfigWrite: ERR. device number illigal %d\n",dev); -+ return MV_BAD_PARAM; -+ } -+ -+ if (func >= MAX_PCI_FUNCS) -+ { -+ mvOsPrintf("mvPciConfigWrite: ERR. function number illigal %d\n", func); -+ return MV_ERROR; -+ } -+ -+ if (bus >= MAX_PCI_BUSSES) -+ { -+ mvOsPrintf("mvPciConfigWrite: ERR. bus number illigal %d\n", bus); -+ return MV_ERROR; -+ } -+ -+ /* Creating PCI address to be passed */ -+ pciData |= (bus << PCAR_BUS_NUM_OFFS); -+ pciData |= (dev << PCAR_DEVICE_NUM_OFFS); -+ pciData |= (func << PCAR_FUNC_NUM_OFFS); -+ pciData |= (regOff & PCAR_REG_NUM_MASK); -+ -+ pciData |= PCAR_CONFIG_EN; -+ -+ /* Write the address to the PCI configuration address register */ -+ MV_REG_WRITE(PCI_CONFIG_ADDR_REG(pciIf), pciData); -+ -+ /* In order to let the PCI controller absorbed the address of the read */ -+ /* transaction we perform a validity check that the address was written */ -+ if(pciData != MV_REG_READ(PCI_CONFIG_ADDR_REG(pciIf))) -+ { -+ return MV_ERROR; -+ } -+ -+ /* Write the Data passed to the PCI Data register */ -+ MV_REG_WRITE(PCI_CONFIG_DATA_REG(pciIf), data); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvPciMasterEnable - Enable/disale PCI interface master transactions. -+* -+* DESCRIPTION: -+* This function performs read modified write to PCI command status -+* (offset 0x4) to set/reset bit 2. After this bit is set, the PCI -+* master is allowed to gain ownership on the bus, otherwise it is -+* incapable to do so. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciMasterEnable(MV_U32 pciIf, MV_BOOL enable) -+{ -+ MV_U32 pciCommandStatus; -+ MV_U32 RegOffs; -+ MV_U32 localBus; -+ MV_U32 localDev; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciMasterEnable: ERR. Invalid PCI interface %d\n", pciIf); -+ return MV_ERROR; -+ } -+ -+ localBus = mvPciLocalBusNumGet(pciIf); -+ localDev = mvPciLocalDevNumGet(pciIf); -+ -+ RegOffs = PCI_STATUS_AND_COMMAND; -+ -+ pciCommandStatus = mvPciConfigRead(pciIf, localBus, localDev, 0, RegOffs); -+ -+ if (MV_TRUE == enable) -+ { -+ pciCommandStatus |= PSCR_MASTER_EN; -+ } -+ else -+ { -+ pciCommandStatus &= ~PSCR_MASTER_EN; -+ } -+ -+ mvPciConfigWrite(pciIf, localBus, localDev, 0, RegOffs, pciCommandStatus); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPciSlaveEnable - Enable/disale PCI interface slave transactions. -+* -+* DESCRIPTION: -+* This function performs read modified write to PCI command status -+* (offset 0x4) to set/reset bit 0 and 1. After those bits are set, -+* the PCI slave is allowed to respond to PCI IO space access (bit 0) -+* and PCI memory space access (bit 1). -+* -+* INPUT: -+* pciIf - PCI interface number. -+* dev - PCI device number. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciSlaveEnable(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, MV_BOOL enable) -+{ -+ MV_U32 pciCommandStatus; -+ MV_U32 RegOffs; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciSlaveEnable: ERR. Invalid PCI interface %d\n", pciIf); -+ return MV_BAD_PARAM; -+ } -+ if (dev >= MAX_PCI_DEVICES) -+ { -+ mvOsPrintf("mvPciLocalDevNumSet: ERR. device number illigal %d\n", dev); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ RegOffs = PCI_STATUS_AND_COMMAND; -+ -+ pciCommandStatus=mvPciConfigRead(pciIf, bus, dev, 0, RegOffs); -+ -+ if (MV_TRUE == enable) -+ { -+ pciCommandStatus |= (PSCR_IO_EN | PSCR_MEM_EN); -+ } -+ else -+ { -+ pciCommandStatus &= ~(PSCR_IO_EN | PSCR_MEM_EN); -+ } -+ -+ mvPciConfigWrite(pciIf, bus, dev, 0, RegOffs, pciCommandStatus); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvPciLocalBusNumSet - Set PCI interface local bus number. -+* -+* DESCRIPTION: -+* This function sets given PCI interface its local bus number. -+* Note: In case the PCI interface is PCI-X, the information is read-only. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* busNum - Bus number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_NOT_ALLOWED in case PCI interface is PCI-X. -+* MV_BAD_PARAM on bad parameters , -+* otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciLocalBusNumSet(MV_U32 pciIf, MV_U32 busNum) -+{ -+ MV_U32 pciP2PConfig; -+ MV_PCI_MODE pciMode; -+ MV_U32 localBus; -+ MV_U32 localDev; -+ -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciLocalBusNumSet: ERR. Invalid PCI interface %d\n",pciIf); -+ return MV_BAD_PARAM; -+ } -+ if (busNum >= MAX_PCI_BUSSES) -+ { -+ mvOsPrintf("mvPciLocalBusNumSet: ERR. bus number illigal %d\n", busNum); -+ return MV_ERROR; -+ -+ } -+ -+ localBus = mvPciLocalBusNumGet(pciIf); -+ localDev = mvPciLocalDevNumGet(pciIf); -+ -+ -+ /* PCI interface mode */ -+ mvPciModeGet(pciIf, &pciMode); -+ -+ /* if PCI type is PCI-X then it is not allowed to change the dev number */ -+ if (MV_PCIX == pciMode.pciType) -+ { -+ pciP2PConfig = mvPciConfigRead(pciIf, localBus, localDev, 0, PCIX_STATUS ); -+ -+ pciP2PConfig &= ~PXS_BN_MASK; -+ -+ pciP2PConfig |= (busNum << PXS_BN_OFFS) & PXS_BN_MASK; -+ -+ mvPciConfigWrite(pciIf, localBus, localDev, 0, PCIX_STATUS,pciP2PConfig ); -+ -+ } -+ else -+ { -+ pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); -+ -+ pciP2PConfig &= ~PPCR_BUS_NUM_MASK; -+ -+ pciP2PConfig |= (busNum << PPCR_BUS_NUM_OFFS) & PPCR_BUS_NUM_MASK; -+ -+ MV_REG_WRITE(PCI_P2P_CONFIG_REG(pciIf), pciP2PConfig); -+ -+ } -+ -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPciLocalBusNumGet - Get PCI interface local bus number. -+* -+* DESCRIPTION: -+* This function gets the local bus number of a given PCI interface. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Local bus number.0xffffffff on Error -+* -+*******************************************************************************/ -+MV_U32 mvPciLocalBusNumGet(MV_U32 pciIf) -+{ -+ MV_U32 pciP2PConfig; -+ -+ /* Parameter checking */ -+ if (PCI_DEFAULT_IF != pciIf) -+ { -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciLocalBusNumGet: ERR. Invalid PCI interface %d\n", -+ pciIf); -+ return 0xFFFFFFFF; -+ } -+ } -+ -+ pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); -+ pciP2PConfig &= PPCR_BUS_NUM_MASK; -+ return (pciP2PConfig >> PPCR_BUS_NUM_OFFS); -+} -+ -+ -+/******************************************************************************* -+* mvPciLocalDevNumSet - Set PCI interface local device number. -+* -+* DESCRIPTION: -+* This function sets given PCI interface its local device number. -+* Note: In case the PCI interface is PCI-X, the information is read-only. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* devNum - Device number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_NOT_ALLOWED in case PCI interface is PCI-X. MV_BAD_PARAM on bad parameters , -+* otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciLocalDevNumSet(MV_U32 pciIf, MV_U32 devNum) -+{ -+ MV_U32 pciP2PConfig; -+ MV_PCI_MODE pciMode; -+ MV_U32 localBus; -+ MV_U32 localDev; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciLocalDevNumSet: ERR. Invalid PCI interface %d\n",pciIf); -+ return MV_BAD_PARAM; -+ } -+ if (devNum >= MAX_PCI_DEVICES) -+ { -+ mvOsPrintf("mvPciLocalDevNumSet: ERR. device number illigal %d\n", -+ devNum); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ localBus = mvPciLocalBusNumGet(pciIf); -+ localDev = mvPciLocalDevNumGet(pciIf); -+ -+ /* PCI interface mode */ -+ mvPciModeGet(pciIf, &pciMode); -+ -+ /* if PCI type is PCIX then it is not allowed to change the dev number */ -+ if (MV_PCIX == pciMode.pciType) -+ { -+ pciP2PConfig = mvPciConfigRead(pciIf, localBus, localDev, 0, PCIX_STATUS ); -+ -+ pciP2PConfig &= ~PXS_DN_MASK; -+ -+ pciP2PConfig |= (devNum << PXS_DN_OFFS) & PXS_DN_MASK; -+ -+ mvPciConfigWrite(pciIf,localBus, localDev, 0, PCIX_STATUS,pciP2PConfig ); -+ } -+ else -+ { -+ pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); -+ -+ pciP2PConfig &= ~PPCR_DEV_NUM_MASK; -+ -+ pciP2PConfig |= (devNum << PPCR_DEV_NUM_OFFS) & PPCR_DEV_NUM_MASK; -+ -+ MV_REG_WRITE(PCI_P2P_CONFIG_REG(pciIf), pciP2PConfig); -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvPciLocalDevNumGet - Get PCI interface local device number. -+* -+* DESCRIPTION: -+* This function gets the local device number of a given PCI interface. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Local device number. 0xffffffff on Error -+* -+*******************************************************************************/ -+MV_U32 mvPciLocalDevNumGet(MV_U32 pciIf) -+{ -+ MV_U32 pciP2PConfig; -+ -+ /* Parameter checking */ -+ -+ if (PCI_DEFAULT_IF != pciIf) -+ { -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciLocalDevNumGet: ERR. Invalid PCI interface %d\n", -+ pciIf); -+ return 0xFFFFFFFF; -+ } -+ } -+ -+ pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); -+ -+ pciP2PConfig &= PPCR_DEV_NUM_MASK; -+ -+ return (pciP2PConfig >> PPCR_DEV_NUM_OFFS); -+} -+ -+ -+ -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,185 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCPCIH -+#define __INCPCIH -+ -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+#include "pci/mvPciRegs.h" -+ -+ -+/* NOTE not supported in this driver: -+ -+ Built In Self Test (BIST) -+ Vital Product Data (VPD) -+ Message Signaled Interrupt (MSI) -+ Power Management -+ Compact PCI Hot Swap -+ Header retarget -+ -+Registers not supported: -+1) PCI DLL Status and Control (PCI0 0x1D20, PCI1 0x1DA0) -+2) PCI/MPP Pads Calibration (CI0/MPP[31:16] 0x1D1C, PCI1/MPP[15:0] 0X1D9C) -+*/ -+ -+/* defines */ -+/* The number of supported PCI interfaces depend on Marvell controller */ -+/* device number. This device number ID is located on the PCI unit */ -+/* configuration header. This creates a loop where calling PCI */ -+/* configuration read/write routine results a call to get PCI configuration */ -+/* information etc. This macro defines a default PCI interface. This PCI */ -+/* interface is sure to exist. */ -+#define PCI_DEFAULT_IF 0 -+ -+ -+/* typedefs */ -+/* The Marvell controller supports both conventional PCI and PCI-X. */ -+/* This enumeration describes the PCI type. */ -+typedef enum _mvPciType -+{ -+ MV_PCI_CONV, /* Conventional PCI */ -+ MV_PCIX /* PCI-X */ -+}MV_PCI_TYPE; -+ -+typedef enum _mvPciMod -+{ -+ MV_PCI_MOD_HOST, -+ MV_PCI_MOD_DEVICE -+}MV_PCI_MOD; -+ -+ -+/* The Marvell controller supports both PCI width of 32 and 64 bit. */ -+/* This enumerator describes PCI width */ -+typedef enum _mvPciWidth -+{ -+ MV_PCI_32, /* PCI width 32bit */ -+ MV_PCI_64 /* PCI width 64bit */ -+}MV_PCI_WIDTH; -+ -+/* This structure describes the PCI unit configured type, speed and width. */ -+typedef struct _mvPciMode -+{ -+ MV_PCI_TYPE pciType; /* PCI type */ -+ MV_U32 pciSpeed; /* Assuming PCI base clock on board is 33MHz */ -+ MV_PCI_WIDTH pciWidth; /* PCI bus width */ -+}MV_PCI_MODE; -+ -+/* mvPciInit - Initialize PCI interfaces*/ -+MV_VOID mvPciHalInit(MV_U32 pciIf, MV_PCI_MOD pciIfmod); -+ -+/* mvPciCommandSet - Set PCI comman register value.*/ -+MV_STATUS mvPciCommandSet(MV_U32 pciIf, MV_U32 command); -+ -+/* mvPciModeGet - Get PCI interface mode.*/ -+MV_STATUS mvPciModeGet(MV_U32 pciIf, MV_PCI_MODE *pPciMode); -+ -+/* mvPciRetrySet - Set PCI retry counters*/ -+MV_STATUS mvPciRetrySet(MV_U32 pciIf, MV_U32 counter); -+ -+/* mvPciDiscardTimerSet - Set PCI discard timer*/ -+MV_STATUS mvPciDiscardTimerSet(MV_U32 pciIf, MV_U32 pClkCycles); -+ -+/* mvPciArbEnable - PCI arbiter enable/disable*/ -+MV_STATUS mvPciArbEnable(MV_U32 pciIf, MV_BOOL enable); -+ -+/* mvPciArbParkDis - Disable arbiter parking on agent */ -+MV_STATUS mvPciArbParkDis(MV_U32 pciIf, MV_U32 pciAgentMask); -+ -+/* mvPciArbBrokDetectSet - Set PCI arbiter broken detection */ -+MV_STATUS mvPciArbBrokDetectSet(MV_U32 pciIf, MV_U32 pClkCycles); -+ -+/* mvPciConfigRead - Read from configuration space */ -+MV_U32 mvPciConfigRead (MV_U32 pciIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func,MV_U32 regOff); -+ -+/* mvPciConfigWrite - Write to configuration space */ -+MV_STATUS mvPciConfigWrite(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data); -+ -+/* mvPciMasterEnable - Enable/disale PCI interface master transactions.*/ -+MV_STATUS mvPciMasterEnable(MV_U32 pciIf, MV_BOOL enable); -+ -+/* mvPciSlaveEnable - Enable/disale PCI interface slave transactions.*/ -+MV_STATUS mvPciSlaveEnable(MV_U32 pciIf, MV_U32 bus, MV_U32 dev,MV_BOOL enable); -+ -+/* mvPciLocalBusNumSet - Set PCI interface local bus number.*/ -+MV_STATUS mvPciLocalBusNumSet(MV_U32 pciIf, MV_U32 busNum); -+ -+/* mvPciLocalBusNumGet - Get PCI interface local bus number.*/ -+MV_U32 mvPciLocalBusNumGet(MV_U32 pciIf); -+ -+/* mvPciLocalDevNumSet - Set PCI interface local device number.*/ -+MV_STATUS mvPciLocalDevNumSet(MV_U32 pciIf, MV_U32 devNum); -+ -+/* mvPciLocalDevNumGet - Get PCI interface local device number.*/ -+MV_U32 mvPciLocalDevNumGet(MV_U32 pciIf); -+ -+ -+#endif /* #ifndef __INCPCIH */ -+ -+ -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,411 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCPCIREGSH -+#define __INCPCIREGSH -+ -+ -+#include "pci-if/mvPciIfRegs.h" -+/* defines */ -+#define MAX_PCI_DEVICES 32 -+#define MAX_PCI_FUNCS 8 -+#define MAX_PCI_BUSSES 128 -+ -+/* enumerators */ -+ -+/* This enumerator described the possible PCI slave targets. */ -+/* PCI slave targets are designated memory/IO address spaces that the */ -+/* PCI slave targets can access. They are also refered as "targets" */ -+/* this enumeratoe order is determined by the content of : -+ PCI_BASE_ADDR_ENABLE_REG */ -+ -+ -+/* registers offsetes defines */ -+ -+ -+ -+/*************************/ -+/* PCI control registers */ -+/*************************/ -+/* maen : should add new registers */ -+#define PCI_CMD_REG(pciIf) (0x30c00 + ((pciIf) * 0x80)) -+#define PCI_MODE_REG(pciIf) (0x30d00 + ((pciIf) * 0x80)) -+#define PCI_RETRY_REG(pciIf) (0x30c04 + ((pciIf) * 0x80)) -+#define PCI_DISCARD_TIMER_REG(pciIf) (0x30d04 + ((pciIf) * 0x80)) -+#define PCI_ARBITER_CTRL_REG(pciIf) (0x31d00 + ((pciIf) * 0x80)) -+#define PCI_P2P_CONFIG_REG(pciIf) (0x31d14 + ((pciIf) * 0x80)) -+#define PCI_ACCESS_CTRL_BASEL_REG(pciIf, targetWin) \ -+ (0x31e00 + ((pciIf) * 0x80) + ((targetWin) * 0x10)) -+#define PCI_ACCESS_CTRL_BASEH_REG(pciIf, targetWin) \ -+ (0x31e04 + ((pciIf) * 0x80) + ((targetWin) * 0x10)) -+#define PCI_ACCESS_CTRL_SIZE_REG(pciIf, targetWin) \ -+ (0x31e08 + ((pciIf) * 0x80) + ((targetWin) * 0x10)) -+ -+#define PCI_DLL_CTRL_REG(pciIf) (0x31d20 + ((pciIf) * 0x80)) -+ -+/* PCI Dll Control (PDC)*/ -+#define PDC_DLL_EN BIT0 -+ -+ -+/* PCI Command Register (PCR) */ -+#define PCR_MASTER_BYTE_SWAP_EN BIT0 -+#define PCR_MASTER_WR_COMBINE_EN BIT4 -+#define PCR_MASTER_RD_COMBINE_EN BIT5 -+#define PCR_MASTER_WR_TRIG_WHOLE BIT6 -+#define PCR_MASTER_RD_TRIG_WHOLE BIT7 -+#define PCR_MASTER_MEM_RD_LINE_EN BIT8 -+#define PCR_MASTER_MEM_RD_MULT_EN BIT9 -+#define PCR_MASTER_WORD_SWAP_EN BIT10 -+#define PCR_SLAVE_WORD_SWAP_EN BIT11 -+#define PCR_NS_ACCORDING_RCV_TRANS BIT14 -+#define PCR_MASTER_PCIX_REQ64N_EN BIT15 -+#define PCR_SLAVE_BYTE_SWAP_EN BIT16 -+#define PCR_MASTER_DAC_EN BIT17 -+#define PCR_MASTER_M64_ALLIGN BIT18 -+#define PCR_ERRORS_PROPAGATION_EN BIT19 -+#define PCR_SLAVE_SWAP_ENABLE BIT20 -+#define PCR_MASTER_SWAP_ENABLE BIT21 -+#define PCR_MASTER_INT_SWAP_EN BIT22 -+#define PCR_LOOP_BACK_ENABLE BIT23 -+#define PCR_SLAVE_INTREG_SWAP_OFFS 24 -+#define PCR_SLAVE_INTREG_SWAP_MASK 0x3 -+#define PCR_SLAVE_INTREG_BYTE_SWAP \ -+ (MV_BYTE_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) -+#define PCR_SLAVE_INTREG_NO_SWAP \ -+ (MV_NO_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) -+#define PCR_SLAVE_INTREG_BYTE_WORD \ -+ (MV_BYTE_WORD_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) -+#define PCR_SLAVE_INTREG_WORD_SWAP \ -+ (MV_WORD_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) -+#define PCR_RESET_REASSERTION_EN BIT26 -+#define PCR_PCI_TO_CPU_REG_ORDER_EN BIT28 -+#define PCR_CPU_TO_PCI_ORDER_EN BIT29 -+#define PCR_PCI_TO_CPU_ORDER_EN BIT30 -+ -+/* PCI Mode Register (PMR) */ -+#define PMR_PCI_ID_OFFS 0 /* PCI Interface ID */ -+#define PMR_PCI_ID_MASK (0x1 << PMR_PCI_ID_OFFS) -+#define PMR_PCI_ID_PCI(pciNum) ((pciNum) << PCI_MODE_PCIID_OFFS) -+ -+#define PMR_PCI_64_OFFS 2 /* 64-bit PCI Interface */ -+#define PMR_PCI_64_MASK (0x1 << PMR_PCI_64_OFFS) -+#define PMR_PCI_64_64BIT (0x1 << PMR_PCI_64_OFFS) -+#define PMR_PCI_64_32BIT (0x0 << PMR_PCI_64_OFFS) -+ -+#define PMR_PCI_MODE_OFFS 4 /* PCI interface mode of operation */ -+#define PMR_PCI_MODE_MASK (0x3 << PMR_PCI_MODE_OFFS) -+#define PMR_PCI_MODE_CONV (0x0 << PMR_PCI_MODE_OFFS) -+#define PMR_PCI_MODE_PCIX_66MHZ (0x1 << PMR_PCI_MODE_OFFS) -+#define PMR_PCI_MODE_PCIX_100MHZ (0x2 << PMR_PCI_MODE_OFFS) -+#define PMR_PCI_MODE_PCIX_133MHZ (0x3 << PMR_PCI_MODE_OFFS) -+ -+#define PMR_EXP_ROM_SUPPORT BIT8 /* Expansion ROM Active */ -+ -+#define PMR_PCI_RESET_OFFS 31 /* PCI Interface Reset Indication */ -+#define PMR_PCI_RESET_MASK (0x1 << PMR_PCI_RESET_OFFS) -+#define PMR_PCI_RESET_PCIXRST (0x0 << PMR_PCI_RESET_OFFS) -+ -+ -+/* PCI Retry Register (PRR) */ -+#define PRR_RETRY_CNTR_OFFS 16 /* Retry Counter */ -+#define PRR_RETRY_CNTR_MAX 0xff -+#define PRR_RETRY_CNTR_MASK (PRR_RETRY_CNTR_MAX << PRR_RETRY_CNTR_OFFS) -+ -+ -+/* PCI Discard Timer Register (PDTR) */ -+#define PDTR_TIMER_OFFS 0 /* Timer */ -+#define PDTR_TIMER_MAX 0xffff -+#define PDTR_TIMER_MIN 0x7F -+#define PDTR_TIMER_MASK (PDTR_TIMER_MAX << PDTR_TIMER_OFFS) -+ -+ -+/* PCI Arbiter Control Register (PACR) */ -+#define PACR_BROKEN_DETECT_EN BIT1 /* Broken Detection Enable */ -+ -+#define PACR_BROKEN_VAL_OFFS 3 /* Broken Value */ -+#define PACR_BROKEN_VAL_MASK (0xf << PACR_BROKEN_VAL_OFFS) -+#define PACR_BROKEN_VAL_CONV_MIN 0x2 -+#define PACR_BROKEN_VAL_PCIX_MIN 0x6 -+ -+#define PACR_PARK_DIS_OFFS 14 /* Parking Disable */ -+#define PACR_PARK_DIS_MAX_AGENT 0x3f -+#define PACR_PARK_DIS_MASK (PACR_PARK_DIS_MAX_AGENT<= MV_PCI_START_IF)&&(pciIf < MV_PCI_MAX_IF + MV_PCI_START_IF)) -+ { -+ return PCI_IF_TYPE_CONVEN_PCIX; -+ } -+ else if ((pciIf >= MV_PEX_START_IF) && -+ (pciIf < MV_PEX_MAX_IF + MV_PEX_START_IF)) -+ { -+ return PCI_IF_TYPE_PEX; -+ -+ } -+ else -+ { -+ mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf); -+ } -+ -+ return 0xffffffff; -+ -+} -+ -+/******************************************************************************* -+* mvPciIfTypeGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+ -+MV_U32 mvPciRealIfNumGet(MV_U32 pciIf) -+{ -+ -+ PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf); -+ -+ if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType) -+ { -+ return (pciIf - MV_PCI_START_IF); -+ } -+ else if (PCI_IF_TYPE_PEX == pciIfType) -+ { -+ return (pciIf - MV_PEX_START_IF); -+ -+ } -+ else -+ { -+ mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf); -+ } -+ -+ return 0xffffffff; -+ -+} -+ -+ -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,134 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCPCIIFH -+#define __INCPCIIFH -+ -+#include "mvSysHwConfig.h" -+#include "pci-if/mvPciIfRegs.h" -+#if defined(MV_INCLUDE_PEX) -+#include "pex/mvPex.h" -+#endif -+#if defined(MV_INCLUDE_PCI) -+#include "pci/mvPci.h" -+#endif -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+ -+typedef enum _mvPCIIfType -+{ -+ PCI_IF_TYPE_CONVEN_PCIX, -+ PCI_IF_TYPE_PEX -+ -+}PCI_IF_TYPE; -+ -+typedef enum _mvPCIIfMode -+{ -+ PCI_IF_MODE_HOST, -+ PCI_IF_MODE_DEVICE -+}PCI_IF_MODE; -+ -+ -+/* Global Functions prototypes */ -+ -+/* mvPciIfInit - Initialize PCI interfaces*/ -+MV_STATUS mvPciIfInit(MV_U32 pciIf, PCI_IF_MODE pciIfmode); -+ -+/* mvPciIfConfigRead - Read from configuration space */ -+MV_U32 mvPciIfConfigRead (MV_U32 pciIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func,MV_U32 regOff); -+ -+/* mvPciIfConfigWrite - Write to configuration space */ -+MV_STATUS mvPciIfConfigWrite(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data); -+ -+/* mvPciIfMasterEnable - Enable/disale PCI interface master transactions.*/ -+MV_STATUS mvPciIfMasterEnable(MV_U32 pciIf, MV_BOOL enable); -+ -+/* mvPciIfSlaveEnable - Enable/disale PCI interface slave transactions.*/ -+MV_STATUS mvPciIfSlaveEnable(MV_U32 pciIf,MV_U32 bus, MV_U32 dev, -+ MV_BOOL enable); -+ -+/* mvPciIfLocalBusNumSet - Set PCI interface local bus number.*/ -+MV_STATUS mvPciIfLocalBusNumSet(MV_U32 pciIf, MV_U32 busNum); -+ -+/* mvPciIfLocalBusNumGet - Get PCI interface local bus number.*/ -+MV_U32 mvPciIfLocalBusNumGet(MV_U32 pciIf); -+ -+/* mvPciIfLocalDevNumSet - Set PCI interface local device number.*/ -+MV_STATUS mvPciIfLocalDevNumSet(MV_U32 pciIf, MV_U32 devNum); -+ -+/* mvPciIfLocalDevNumGet - Get PCI interface local device number.*/ -+MV_U32 mvPciIfLocalDevNumGet(MV_U32 pciIf); -+ -+/* mvPciIfTypeGet - Get PCI If type*/ -+PCI_IF_TYPE mvPciIfTypeGet(MV_U32 pciIf); -+ -+MV_U32 mvPciRealIfNumGet(MV_U32 pciIf); -+ -+/* mvPciIfAddrDecShow - Display address decode windows attributes */ -+MV_VOID mvPciIfAddrDecShow(MV_VOID); -+ -+#endif /* #ifndef __INCPCIIFH */ -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,245 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCPCIIFREGSH -+#define __INCPCIIFREGSH -+ -+ -+/* defines */ -+#define MAX_PCI_DEVICES 32 -+#define MAX_PCI_FUNCS 8 -+#define MAX_PCI_BUSSES 128 -+ -+/***************************************/ -+/* PCI Configuration registers */ -+/***************************************/ -+ -+/*********************************************/ -+/* PCI Configuration, Function 0, Registers */ -+/*********************************************/ -+ -+ -+/* Standard registers */ -+#define PCI_DEVICE_AND_VENDOR_ID 0x000 -+#define PCI_STATUS_AND_COMMAND 0x004 -+#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 -+#define PCI_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE 0x00C -+#define PCI_MEMORY_BAR_BASE_ADDR(barNum) (0x010 + ((barNum) << 2)) -+#define PCI_SUBSYS_ID_AND_SUBSYS_VENDOR_ID 0x02C -+#define PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030 -+#define PCI_CAPABILTY_LIST_POINTER 0x034 -+#define PCI_INTERRUPT_PIN_AND_LINE 0x03C -+ -+ -+/* PCI Device and Vendor ID Register (PDVIR) */ -+#define PDVIR_VEN_ID_OFFS 0 /* Vendor ID */ -+#define PDVIR_VEN_ID_MASK (0xffff << PDVIR_VEN_ID_OFFS) -+ -+#define PDVIR_DEV_ID_OFFS 16 /* Device ID */ -+#define PDVIR_DEV_ID_MASK (0xffff << PDVIR_DEV_ID_OFFS) -+ -+/* PCI Status and Command Register (PSCR) */ -+#define PSCR_IO_EN BIT0 /* IO Enable */ -+#define PSCR_MEM_EN BIT1 /* Memory Enable */ -+#define PSCR_MASTER_EN BIT2 /* Master Enable */ -+#define PSCR_SPECIAL_EN BIT3 /* Special Cycle Enable */ -+#define PSCR_MEM_WRI_INV BIT4 /* Memory Write and Invalidate Enable */ -+#define PSCR_VGA BIT5 /* VGA Palette Snoops */ -+#define PSCR_PERR_EN BIT6 /* Parity Errors Respond Enable */ -+#define PSCR_ADDR_STEP BIT7 /* Address Stepping Enable (Wait Cycle En)*/ -+#define PSCR_SERR_EN BIT8 /* Ability to assert SERR# line */ -+#define PSCR_FAST_BTB_EN BIT9 /* generate fast back-to-back transactions*/ -+#define PSCR_CAP_LIST BIT20 /* Capability List Support */ -+#define PSCR_66MHZ_EN BIT21 /* 66 MHz Capable */ -+#define PSCR_UDF_EN BIT22 /* User definable features */ -+#define PSCR_TAR_FAST_BB BIT23 /* fast back-to-back transactions capable */ -+#define PSCR_DATA_PERR BIT24 /* Data Parity reported */ -+ -+#define PSCR_DEVSEL_TIM_OFFS 25 /* DEVSEL timing */ -+#define PSCR_DEVSEL_TIM_MASK (0x3 << PSCR_DEVSEL_TIM_OFFS) -+#define PSCR_DEVSEL_TIM_FAST (0x0 << PSCR_DEVSEL_TIM_OFFS) -+#define PSCR_DEVSEL_TIM_MED (0x1 << PSCR_DEVSEL_TIM_OFFS) -+#define PSCR_DEVSEL_TIM_SLOW (0x2 << PSCR_DEVSEL_TIM_OFFS) -+ -+#define PSCR_SLAVE_TABORT BIT27 /* Signalled Target Abort */ -+#define PSCR_MASTER_TABORT BIT28 /* Recieved Target Abort */ -+#define PSCR_MABORT BIT29 /* Recieved Master Abort */ -+#define PSCR_SYSERR BIT30 /* Signalled system error */ -+#define PSCR_DET_PARERR BIT31 /* Detect Parity Error */ -+ -+/* PCI configuration register offset=0x08 fields -+ (PCI_CLASS_CODE_AND_REVISION_ID)(PCCRI) */ -+ -+#define PCCRIR_REVID_OFFS 0 /* Revision ID */ -+#define PCCRIR_REVID_MASK (0xff << PCCRIR_REVID_OFFS) -+ -+#define PCCRIR_FULL_CLASS_OFFS 8 /* Full Class Code */ -+#define PCCRIR_FULL_CLASS_MASK (0xffffff << PCCRIR_FULL_CLASS_OFFS) -+ -+#define PCCRIR_PROGIF_OFFS 8 /* Prog .I/F*/ -+#define PCCRIR_PROGIF_MASK (0xff << PCCRIR_PROGIF_OFFS) -+ -+#define PCCRIR_SUB_CLASS_OFFS 16 /* Sub Class*/ -+#define PCCRIR_SUB_CLASS_MASK (0xff << PCCRIR_SUB_CLASS_OFFS) -+ -+#define PCCRIR_BASE_CLASS_OFFS 24 /* Base Class*/ -+#define PCCRIR_BASE_CLASS_MASK (0xff << PCCRIR_BASE_CLASS_OFFS) -+ -+/* PCI configuration register offset=0x0C fields -+ (PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE)(PBHTLTCL) */ -+ -+#define PBHTLTCLR_CACHELINE_OFFS 0 /* Specifies the cache line size */ -+#define PBHTLTCLR_CACHELINE_MASK (0xff << PBHTLTCLR_CACHELINE_OFFS) -+ -+#define PBHTLTCLR_LATTIMER_OFFS 8 /* latency timer */ -+#define PBHTLTCLR_LATTIMER_MASK (0xff << PBHTLTCLR_LATTIMER_OFFS) -+ -+#define PBHTLTCLR_HEADTYPE_FULL_OFFS 16 /* Full Header Type */ -+#define PBHTLTCLR_HEADTYPE_FULL_MASK (0xff << PBHTLTCLR_HEADTYPE_FULL_OFFS) -+ -+#define PBHTLTCLR_MULTI_FUNC BIT23 /* Multi/Single function */ -+ -+#define PBHTLTCLR_HEADER_OFFS 16 /* Header type */ -+#define PBHTLTCLR_HEADER_MASK (0x7f << PBHTLTCLR_HEADER_OFFS) -+#define PBHTLTCLR_HEADER_STANDARD (0x0 << PBHTLTCLR_HEADER_OFFS) -+#define PBHTLTCLR_HEADER_PCI2PCI_BRIDGE (0x1 << PBHTLTCLR_HEADER_OFFS) -+ -+ -+#define PBHTLTCLR_BISTCOMP_OFFS 24 /* BIST Completion Code */ -+#define PBHTLTCLR_BISTCOMP_MASK (0xf << PBHTLTCLR_BISTCOMP_OFFS) -+ -+#define PBHTLTCLR_BISTACT BIT30 /* BIST Activate bit */ -+#define PBHTLTCLR_BISTCAP BIT31 /* BIST Capable Bit */ -+ -+ -+/* PCI Bar Base Low Register (PBBLR) */ -+#define PBBLR_IOSPACE BIT0 /* Memory Space Indicator */ -+ -+#define PBBLR_TYPE_OFFS 1 /* BAR Type/Init Val. */ -+#define PBBLR_TYPE_MASK (0x3 << PBBLR_TYPE_OFFS) -+#define PBBLR_TYPE_32BIT_ADDR (0x0 << PBBLR_TYPE_OFFS) -+#define PBBLR_TYPE_64BIT_ADDR (0x2 << PBBLR_TYPE_OFFS) -+ -+#define PBBLR_PREFETCH_EN BIT3 /* Prefetch Enable */ -+ -+ -+#define PBBLR_MEM_BASE_OFFS 4 /* Memory Bar Base address. Corresponds to -+ address bits [31:4] */ -+#define PBBLR_MEM_BASE_MASK (0xfffffff << PBBLR_MEM_BASE_OFFS) -+ -+#define PBBLR_IO_BASE_OFFS 2 /* IO Bar Base address. Corresponds to -+ address bits [31:2] */ -+#define PBBLR_IO_BASE_MASK (0x3fffffff << PBBLR_IO_BASE_OFFS) -+ -+ -+#define PBBLR_BASE_OFFS 12 /* Base address. Address bits [31:12] */ -+#define PBBLR_BASE_MASK (0xfffff << PBBLR_BASE_OFFS) -+#define PBBLR_BASE_ALIGNMET (1 << PBBLR_BASE_OFFS) -+ -+ -+/* PCI Bar Base High Fegister (PBBHR) */ -+#define PBBHR_BASE_OFFS 0 /* Base address. Address bits [31:12] */ -+#define PBBHR_BASE_MASK (0xffffffff << PBBHR_BASE_OFFS) -+ -+ -+/* PCI configuration register offset=0x2C fields -+ (PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID)(PSISVI) */ -+ -+#define PSISVIR_VENID_OFFS 0 /* Subsystem Manufacturer Vendor ID Number */ -+#define PSISVIR_VENID_MASK (0xffff << PSISVIR_VENID_OFFS) -+ -+#define PSISVIR_DEVID_OFFS 16 /* Subsystem Device ID Number */ -+#define PSISVIR_DEVID_MASK (0xffff << PSISVIR_DEVID_OFFS) -+ -+/* PCI configuration register offset=0x30 fields -+ (PCI_EXPANSION_ROM_BASE_ADDR_REG)(PERBA) */ -+ -+#define PERBAR_EXPROMEN BIT0 /* Expansion ROM Enable */ -+ -+#define PERBAR_BASE_OFFS 12 /* Expansion ROM Base Address */ -+#define PERBAR_BASE_MASK (0xfffff << PERBAR_BASE_OFFS) -+ -+/* PCI configuration register offset=0x34 fields -+ (PCI_CAPABILTY_LIST_POINTER)(PCLP) */ -+ -+#define PCLPR_CAPPTR_OFFS 0 /* Capability List Pointer */ -+#define PCLPR_CAPPTR_MASK (0xff << PCLPR_CAPPTR_OFFS) -+ -+/* PCI configuration register offset=0x3C fields -+ (PCI_INTERRUPT_PIN_AND_LINE)(PIPL) */ -+ -+#define PIPLR_INTLINE_OFFS 0 /* Interrupt line (IRQ) */ -+#define PIPLR_INTLINE_MASK (0xff << PIPLR_INTLINE_OFFS) -+ -+#define PIPLR_INTPIN_OFFS 8 /* interrupt pin (A,B,C,D) */ -+#define PIPLR_INTPIN_MASK (0xff << PIPLR_INTPIN_OFFS) -+ -+#define PIPLR_MINGRANT_OFFS 16 /* Minimum Grant on 250 nano seconds units */ -+#define PIPLR_MINGRANT_MASK (0xff << PIPLR_MINGRANT_OFFS) -+ -+#define PIPLR_MAXLATEN_OFFS 24 /* Maximum latency on 250 nano seconds units */ -+#define PIPLR_MAXLATEN_MASK (0xff << PIPLR_MAXLATEN_OFFS) -+ -+#endif /* #ifndef __INCPCIIFREGSH */ -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.c ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.c 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,1006 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+/* includes */ -+#include "mvPciUtils.h" -+ -+#include "ctrlEnv/mvCtrlEnvLib.h" -+ -+/* #define MV_DEBUG */ -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+ #define mvOsPrintf printf -+#else -+ #define DB(x) -+#endif -+ -+/* -+This module only support scanning of Header type 00h of pci devices -+There is no suppotr for Header type 01h of pci devices ( PCI bridges ) -+*/ -+ -+ -+static MV_STATUS pciDetectDevice(MV_U32 pciIf, -+ MV_U32 bus, -+ MV_U32 dev, -+ MV_U32 func, -+ MV_PCI_DEVICE *pPciAgent); -+ -+static MV_U32 pciDetectDeviceBars(MV_U32 pciIf, -+ MV_U32 bus, -+ MV_U32 dev, -+ MV_U32 func, -+ MV_PCI_DEVICE *pPciAgent); -+ -+ -+ -+ -+ -+ -+/******************************************************************************* -+* mvPciScan - Scan a PCI interface bus -+* -+* DESCRIPTION: -+* Performs a full scan on a PCI interface and returns all possible details -+* on the agents found on the bus. -+* -+* INPUT: -+* pciIf - PCI Interface -+* pPciAgents - Pointer to an Array of the pci agents to be detected -+* pPciAgentsNum - pPciAgents array maximum number of elements -+* -+* OUTPUT: -+* pPciAgents - Array of the pci agents detected on the bus -+* pPciAgentsNum - Number of pci agents detected on the bus -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+ -+MV_STATUS mvPciScan(MV_U32 pciIf, -+ MV_PCI_DEVICE *pPciAgents, -+ MV_U32 *pPciAgentsNum) -+{ -+ -+ MV_U32 devIndex,funcIndex=0,busIndex=0,detectedDevNum=0; -+ MV_U32 localBus=mvPciIfLocalBusNumGet(pciIf); -+ MV_PCI_DEVICE *pPciDevice; -+ MV_PCI_DEVICE *pMainDevice; -+ -+ DB(mvOsPrintf("mvPciScan: PCI interface num %d\n", pciIf)); -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPexMaxIfGet()) -+ { -+ DB(mvOsPrintf("mvPciScan: ERR. Invalid PCI interface num %d\n", pciIf)); -+ return MV_BAD_PARAM; -+ } -+ if (NULL == pPciAgents) -+ { -+ DB(mvOsPrintf("mvPciScan: ERR. pPciAgents=NULL \n")); -+ return MV_BAD_PARAM; -+ } -+ if (NULL == pPciAgentsNum) -+ { -+ DB(mvOsPrintf("mvPciScan: ERR. pPciAgentsNum=NULL \n")); -+ return MV_BAD_PARAM; -+ } -+ -+ -+ DB(mvOsPrintf("mvPciScan: PCI interface num %d mvPciMasterEnable\n", pciIf)); -+ /* Master enable the MV PCI master */ -+ if (MV_OK != mvPciIfMasterEnable(pciIf,MV_TRUE)) -+ { -+ DB(mvOsPrintf("mvPciScan: ERR. mvPciMasterEnable failed \n")); -+ return MV_ERROR; -+ -+ } -+ -+ DB(mvOsPrintf("mvPciScan: PCI interface num scan%d\n", pciIf)); -+ -+ /* go through all busses */ -+ for (busIndex=localBus ; busIndex < MAX_PCI_BUSSES ; busIndex++) -+ { -+ /* go through all possible devices on the local bus */ -+ for (devIndex=0 ; devIndex < MAX_PCI_DEVICES ; devIndex++) -+ { -+ /* always start with function equal to zero */ -+ funcIndex=0; -+ -+ pPciDevice=&pPciAgents[detectedDevNum]; -+ DB(mvOsPrintf("mvPciScan: PCI interface num scan%d:%d\n", busIndex, devIndex)); -+ -+ if (MV_ERROR == pciDetectDevice(pciIf, -+ busIndex, -+ devIndex, -+ funcIndex, -+ pPciDevice)) -+ { -+ /* no device detected , try the next address */ -+ continue; -+ } -+ -+ /* We are here ! means we have detected a device*/ -+ /* always we start with only one function per device */ -+ pMainDevice = pPciDevice; -+ pPciDevice->funtionsNum = 1; -+ -+ -+ /* move on */ -+ detectedDevNum++; -+ -+ -+ /* check if we have no more room for a new device */ -+ if (detectedDevNum == *pPciAgentsNum) -+ { -+ DB(mvOsPrintf("mvPciScan: ERR. array passed too small \n")); -+ return MV_ERROR; -+ } -+ -+ /* check the detected device if it is a multi functional device then -+ scan all device functions*/ -+ if (pPciDevice->isMultiFunction == MV_TRUE) -+ { -+ /* start with function number 1 because we have already detected -+ function 0 */ -+ for (funcIndex=1; funcIndexfuntionsNum++; -+ detectedDevNum++; -+ -+ /* check if we have no more room for a new device */ -+ if (detectedDevNum == *pPciAgentsNum) -+ { -+ DB(mvOsPrintf("mvPciScan: ERR. Array too small\n")); -+ return MV_ERROR; -+ } -+ -+ -+ } -+ } -+ -+ } -+ -+ } -+ -+ /* return the number of devices actually detected on the bus ! */ -+ *pPciAgentsNum = detectedDevNum; -+ -+ return MV_OK; -+ -+} -+ -+ -+/******************************************************************************* -+* pciDetectDevice - Detect a pci device parameters -+* -+* DESCRIPTION: -+* This function detect if a pci agent exist on certain address ! -+* and if exists then it fills all possible information on the -+* agent -+* -+* INPUT: -+* pciIf - PCI Interface -+* bus - Bus number -+* dev - Device number -+* func - Function number -+* -+* -+* -+* OUTPUT: -+* pPciAgent - pointer to the pci agent filled with its information -+* -+* RETURN: -+* MV_ERROR if no device , MV_OK otherwise -+* -+*******************************************************************************/ -+ -+static MV_STATUS pciDetectDevice(MV_U32 pciIf, -+ MV_U32 bus, -+ MV_U32 dev, -+ MV_U32 func, -+ MV_PCI_DEVICE *pPciAgent) -+{ -+ MV_U32 pciData; -+ -+ /* no Parameters checking ! because it is static function and it is assumed -+ that all parameters were checked in the calling function */ -+ -+ -+ /* Try read the PCI Vendor ID and Device ID */ -+ -+ /* We will scan only ourselves and the PCI slots that exist on the -+ board, because we may have a case that we have one slot that has -+ a Cardbus connector, and because CardBus answers all IDsels we want -+ to scan only this slot and ourseleves. -+ -+ */ -+ #if defined(MV_INCLUDE_PCI) -+ if ((PCI_IF_TYPE_CONVEN_PCIX == mvPciIfTypeGet(pciIf)) && -+ (DB_88F5181_DDR1_PRPMC != mvBoardIdGet()) && -+ (DB_88F5181_DDR1_PEXPCI != mvBoardIdGet()) && -+ (DB_88F5181_DDR1_MNG != mvBoardIdGet())) -+ { -+ -+ if (mvBoardIsOurPciSlot(bus, dev) == MV_FALSE) -+ { -+ return MV_ERROR; -+ } -+ } -+ #endif /* defined(MV_INCLUDE_PCI) */ -+ -+ pciData = mvPciIfConfigRead(pciIf, bus,dev,func, PCI_DEVICE_AND_VENDOR_ID); -+ -+ if (PCI_ERROR_CODE == pciData) -+ { -+ /* no device exist */ -+ return MV_ERROR; -+ } -+ -+ /* we are here ! means a device is detected */ -+ -+ /* fill basic information */ -+ pPciAgent->busNumber=bus; -+ pPciAgent->deviceNum=dev; -+ pPciAgent->function=func; -+ -+ /* Fill the PCI Vendor ID and Device ID */ -+ -+ pPciAgent->venID = (pciData & PDVIR_VEN_ID_MASK) >> PDVIR_VEN_ID_OFFS; -+ pPciAgent->deviceID = (pciData & PDVIR_DEV_ID_MASK) >> PDVIR_DEV_ID_OFFS; -+ -+ /* Read Status and command */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_STATUS_AND_COMMAND); -+ -+ -+ /* Fill related Status and Command information*/ -+ -+ if (pciData & PSCR_TAR_FAST_BB) -+ { -+ pPciAgent->isFastB2BCapable = MV_TRUE; -+ } -+ else -+ { -+ pPciAgent->isFastB2BCapable = MV_FALSE; -+ } -+ -+ if (pciData & PSCR_CAP_LIST) -+ { -+ pPciAgent->isCapListSupport=MV_TRUE; -+ } -+ else -+ { -+ pPciAgent->isCapListSupport=MV_FALSE; -+ } -+ -+ if (pciData & PSCR_66MHZ_EN) -+ { -+ pPciAgent->is66MHZCapable=MV_TRUE; -+ } -+ else -+ { -+ pPciAgent->is66MHZCapable=MV_FALSE; -+ } -+ -+ /* Read Class Code and Revision */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_CLASS_CODE_AND_REVISION_ID); -+ -+ -+ pPciAgent->baseClassCode = -+ (pciData & PCCRIR_BASE_CLASS_MASK) >> PCCRIR_BASE_CLASS_OFFS; -+ -+ pPciAgent->subClassCode = -+ (pciData & PCCRIR_SUB_CLASS_MASK) >> PCCRIR_SUB_CLASS_OFFS; -+ -+ pPciAgent->progIf = -+ (pciData & PCCRIR_PROGIF_MASK) >> PCCRIR_PROGIF_OFFS; -+ -+ pPciAgent->revisionID = -+ (pciData & PCCRIR_REVID_MASK) >> PCCRIR_REVID_OFFS; -+ -+ /* Read PCI_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE); -+ -+ -+ -+ pPciAgent->pciCacheLine= -+ (pciData & PBHTLTCLR_CACHELINE_MASK ) >> PBHTLTCLR_CACHELINE_OFFS; -+ pPciAgent->pciLatencyTimer= -+ (pciData & PBHTLTCLR_LATTIMER_MASK) >> PBHTLTCLR_LATTIMER_OFFS; -+ -+ switch (pciData & PBHTLTCLR_HEADER_MASK) -+ { -+ case PBHTLTCLR_HEADER_STANDARD: -+ -+ pPciAgent->pciHeader=MV_PCI_STANDARD; -+ break; -+ case PBHTLTCLR_HEADER_PCI2PCI_BRIDGE: -+ -+ pPciAgent->pciHeader=MV_PCI_PCI2PCI_BRIDGE; -+ break; -+ -+ } -+ -+ if (pciData & PBHTLTCLR_MULTI_FUNC) -+ { -+ pPciAgent->isMultiFunction=MV_TRUE; -+ } -+ else -+ { -+ pPciAgent->isMultiFunction=MV_FALSE; -+ } -+ -+ if (pciData & PBHTLTCLR_BISTCAP) -+ { -+ pPciAgent->isBISTCapable=MV_TRUE; -+ } -+ else -+ { -+ pPciAgent->isBISTCapable=MV_FALSE; -+ } -+ -+ -+ /* read this device pci bars */ -+ -+ pciDetectDeviceBars(pciIf, -+ bus,dev,func, -+ pPciAgent); -+ -+ -+ /* check if we are bridge*/ -+ if ((pPciAgent->baseClassCode == PCI_BRIDGE_CLASS)&& -+ (pPciAgent->subClassCode == P2P_BRIDGE_SUB_CLASS_CODE)) -+ { -+ -+ /* Read P2P_BUSSES_NUM */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ P2P_BUSSES_NUM); -+ -+ pPciAgent->p2pPrimBusNum = -+ (pciData & PBM_PRIME_BUS_NUM_MASK) >> PBM_PRIME_BUS_NUM_OFFS; -+ -+ pPciAgent->p2pSecBusNum = -+ (pciData & PBM_SEC_BUS_NUM_MASK) >> PBM_SEC_BUS_NUM_OFFS; -+ -+ pPciAgent->p2pSubBusNum = -+ (pciData & PBM_SUB_BUS_NUM_MASK) >> PBM_SUB_BUS_NUM_OFFS; -+ -+ pPciAgent->p2pSecLatencyTimer = -+ (pciData & PBM_SEC_LAT_TMR_MASK) >> PBM_SEC_LAT_TMR_OFFS; -+ -+ /* Read P2P_IO_BASE_LIMIT_SEC_STATUS */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ P2P_IO_BASE_LIMIT_SEC_STATUS); -+ -+ pPciAgent->p2pSecStatus = -+ (pciData & PIBLSS_SEC_STATUS_MASK) >> PIBLSS_SEC_STATUS_OFFS; -+ -+ -+ pPciAgent->p2pIObase = -+ (pciData & PIBLSS_IO_BASE_MASK) << PIBLSS_IO_LIMIT_OFFS; -+ -+ /* clear low address (should be zero)*/ -+ pPciAgent->p2pIObase &= PIBLSS_HIGH_ADDR_MASK; -+ -+ pPciAgent->p2pIOLimit = -+ (pciData & PIBLSS_IO_LIMIT_MASK); -+ -+ /* fill low address with 0xfff */ -+ pPciAgent->p2pIOLimit |= PIBLSS_LOW_ADDR_MASK; -+ -+ -+ switch ((pciData & PIBLSS_ADD_CAP_MASK) >> PIBLSS_ADD_CAP_OFFS) -+ { -+ case PIBLSS_ADD_CAP_16BIT: -+ -+ pPciAgent->bIO32 = MV_FALSE; -+ -+ break; -+ case PIBLSS_ADD_CAP_32BIT: -+ -+ pPciAgent->bIO32 = MV_TRUE; -+ -+ /* Read P2P_IO_BASE_LIMIT_UPPER_16 */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ P2P_IO_BASE_LIMIT_UPPER_16); -+ -+ pPciAgent->p2pIObase |= -+ (pciData & PRBU_IO_UPP_BASE_MASK) << PRBU_IO_UPP_LIMIT_OFFS; -+ -+ -+ pPciAgent->p2pIOLimit |= -+ (pciData & PRBU_IO_UPP_LIMIT_MASK); -+ -+ break; -+ -+ } -+ -+ -+ /* Read P2P_MEM_BASE_LIMIT */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ P2P_MEM_BASE_LIMIT); -+ -+ pPciAgent->p2pMemBase = -+ (pciData & PMBL_MEM_BASE_MASK) << PMBL_MEM_LIMIT_OFFS; -+ -+ /* clear low address */ -+ pPciAgent->p2pMemBase &= PMBL_HIGH_ADDR_MASK; -+ -+ pPciAgent->p2pMemLimit = -+ (pciData & PMBL_MEM_LIMIT_MASK); -+ -+ /* add 0xfffff */ -+ pPciAgent->p2pMemLimit |= PMBL_LOW_ADDR_MASK; -+ -+ -+ /* Read P2P_PREF_MEM_BASE_LIMIT */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ P2P_PREF_MEM_BASE_LIMIT); -+ -+ -+ pPciAgent->p2pPrefMemBase = -+ (pciData & PRMBL_PREF_MEM_BASE_MASK) << PRMBL_PREF_MEM_LIMIT_OFFS; -+ -+ /* get high address only */ -+ pPciAgent->p2pPrefMemBase &= PRMBL_HIGH_ADDR_MASK; -+ -+ -+ -+ pPciAgent->p2pPrefMemLimit = -+ (pciData & PRMBL_PREF_MEM_LIMIT_MASK); -+ -+ /* add 0xfffff */ -+ pPciAgent->p2pPrefMemLimit |= PRMBL_LOW_ADDR_MASK; -+ -+ switch (pciData & PRMBL_ADD_CAP_MASK) -+ { -+ case PRMBL_ADD_CAP_32BIT: -+ -+ pPciAgent->bPrefMem64 = MV_FALSE; -+ -+ /* Read P2P_PREF_BASE_UPPER_32 */ -+ pPciAgent->p2pPrefBaseUpper32Bits = 0; -+ -+ /* Read P2P_PREF_LIMIT_UPPER_32 */ -+ pPciAgent->p2pPrefLimitUpper32Bits = 0; -+ -+ break; -+ case PRMBL_ADD_CAP_64BIT: -+ -+ pPciAgent->bPrefMem64 = MV_TRUE; -+ -+ /* Read P2P_PREF_BASE_UPPER_32 */ -+ pPciAgent->p2pPrefBaseUpper32Bits = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ P2P_PREF_BASE_UPPER_32); -+ -+ /* Read P2P_PREF_LIMIT_UPPER_32 */ -+ pPciAgent->p2pPrefLimitUpper32Bits = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ P2P_PREF_LIMIT_UPPER_32); -+ -+ break; -+ -+ } -+ -+ } -+ else /* no bridge */ -+ { -+ /* Read PCI_SUBSYS_ID_AND_SUBSYS_VENDOR_ID */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_SUBSYS_ID_AND_SUBSYS_VENDOR_ID); -+ -+ -+ pPciAgent->subSysVenID = -+ (pciData & PSISVIR_VENID_MASK) >> PSISVIR_VENID_OFFS; -+ pPciAgent->subSysID = -+ (pciData & PSISVIR_DEVID_MASK) >> PSISVIR_DEVID_OFFS; -+ -+ -+ /* Read PCI_EXPANSION_ROM_BASE_ADDR_REG */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_EXPANSION_ROM_BASE_ADDR_REG); -+ -+ -+ if (pciData & PERBAR_EXPROMEN) -+ { -+ pPciAgent->isExpRom = MV_TRUE; -+ } -+ else -+ { -+ pPciAgent->isExpRom = MV_FALSE; -+ } -+ -+ pPciAgent->expRomAddr = -+ (pciData & PERBAR_BASE_MASK) >> PERBAR_BASE_OFFS; -+ -+ } -+ -+ -+ if (MV_TRUE == pPciAgent->isCapListSupport) -+ { -+ /* Read PCI_CAPABILTY_LIST_POINTER */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_CAPABILTY_LIST_POINTER); -+ -+ pPciAgent->capListPointer = -+ (pciData & PCLPR_CAPPTR_MASK) >> PCLPR_CAPPTR_OFFS; -+ -+ } -+ -+ /* Read PCI_INTERRUPT_PIN_AND_LINE */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_INTERRUPT_PIN_AND_LINE); -+ -+ -+ pPciAgent->irqLine= -+ (pciData & PIPLR_INTLINE_MASK) >> PIPLR_INTLINE_OFFS; -+ -+ pPciAgent->intPin= -+ (MV_PCI_INT_PIN)(pciData & PIPLR_INTPIN_MASK) >> PIPLR_INTPIN_OFFS; -+ -+ pPciAgent->minGrant= -+ (pciData & PIPLR_MINGRANT_MASK) >> PIPLR_MINGRANT_OFFS; -+ pPciAgent->maxLatency= -+ (pciData & PIPLR_MAXLATEN_MASK) >> PIPLR_MAXLATEN_OFFS; -+ -+ mvPciClassNameGet(pPciAgent->baseClassCode, -+ (MV_8 *)pPciAgent->type); -+ -+ return MV_OK; -+ -+ -+} -+ -+/******************************************************************************* -+* pciDetectDeviceBars - Detect a pci device bars -+* -+* DESCRIPTION: -+* This function detects all pci agent bars -+* -+* INPUT: -+* pciIf - PCI Interface -+* bus - Bus number -+* dev - Device number -+* func - Function number -+* -+* -+* -+* OUTPUT: -+* pPciAgent - pointer to the pci agent filled with its information -+* -+* RETURN: -+* detected bars number -+* -+*******************************************************************************/ -+static MV_U32 pciDetectDeviceBars(MV_U32 pciIf, -+ MV_U32 bus, -+ MV_U32 dev, -+ MV_U32 func, -+ MV_PCI_DEVICE *pPciAgent) -+{ -+ MV_U32 pciData,barIndex,detectedBar=0; -+ MV_U32 tmpBaseHigh=0,tmpBaseLow=0; -+ MV_U32 pciMaxBars=0; -+ -+ pPciAgent->barsNum=0; -+ -+ /* check if we are bridge*/ -+ if ((pPciAgent->baseClassCode == PCI_BRIDGE_CLASS)&& -+ (pPciAgent->subClassCode == P2P_BRIDGE_SUB_CLASS_CODE)) -+ { -+ pciMaxBars = 2; -+ } -+ else /* no bridge */ -+ { -+ pciMaxBars = 6; -+ } -+ -+ /* read this device pci bars */ -+ for (barIndex = 0 ; barIndex < pciMaxBars ; barIndex++ ) -+ { -+ /* Read PCI_MEMORY_BAR_BASE_ADDR */ -+ tmpBaseLow = pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex)); -+ -+ pPciAgent->pciBar[detectedBar].barOffset = -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex); -+ -+ /* check if the bar is 32bit or 64bit bar */ -+ switch (pciData & PBBLR_TYPE_MASK) -+ { -+ case PBBLR_TYPE_32BIT_ADDR: -+ pPciAgent->pciBar[detectedBar].barType = PCI_32BIT_BAR; -+ break; -+ case PBBLR_TYPE_64BIT_ADDR: -+ pPciAgent->pciBar[detectedBar].barType = PCI_64BIT_BAR; -+ break; -+ -+ } -+ -+ /* check if it is memory or IO bar */ -+ if (pciData & PBBLR_IOSPACE) -+ { -+ pPciAgent->pciBar[detectedBar].barMapping=PCI_IO_BAR; -+ } -+ else -+ { -+ pPciAgent->pciBar[detectedBar].barMapping=PCI_MEMORY_BAR; -+ } -+ -+ /* if it is memory bar then check if it is prefetchable */ -+ if (PCI_MEMORY_BAR == pPciAgent->pciBar[detectedBar].barMapping) -+ { -+ if (pciData & PBBLR_PREFETCH_EN) -+ { -+ pPciAgent->pciBar[detectedBar].isPrefetchable = MV_TRUE; -+ } -+ else -+ { -+ pPciAgent->pciBar[detectedBar].isPrefetchable = MV_FALSE; -+ } -+ -+ pPciAgent->pciBar[detectedBar].barBaseLow = -+ pciData & PBBLR_MEM_BASE_MASK; -+ -+ -+ } -+ else /* IO Bar */ -+ { -+ pPciAgent->pciBar[detectedBar].barBaseLow = -+ pciData & PBBLR_IO_BASE_MASK; -+ -+ } -+ -+ pPciAgent->pciBar[detectedBar].barBaseHigh=0; -+ -+ if (PCI_64BIT_BAR == pPciAgent->pciBar[detectedBar].barType) -+ { -+ barIndex++; -+ -+ tmpBaseHigh = pPciAgent->pciBar[detectedBar].barBaseHigh = -+ mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex)); -+ -+ -+ } -+ -+ /* calculating full base address (64bit) */ -+ pPciAgent->pciBar[detectedBar].barBaseAddr = -+ (MV_U64)pPciAgent->pciBar[detectedBar].barBaseHigh; -+ -+ pPciAgent->pciBar[detectedBar].barBaseAddr <<= 32; -+ -+ pPciAgent->pciBar[detectedBar].barBaseAddr |= -+ (MV_U64)pPciAgent->pciBar[detectedBar].barBaseLow; -+ -+ -+ -+ /* get the sizes of the the bar */ -+ -+ pPciAgent->pciBar[detectedBar].barSizeHigh=0; -+ -+ if ((PCI_64BIT_BAR == pPciAgent->pciBar[detectedBar].barType) && -+ (PCI_MEMORY_BAR == pPciAgent->pciBar[detectedBar].barMapping)) -+ -+ { -+ /* write oxffffffff to the bar to get the size */ -+ /* start with sizelow ( original value was saved in tmpBaseLow ) */ -+ mvPciIfConfigWrite(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex-1), -+ 0xffffffff); -+ -+ /* read size */ -+ pPciAgent->pciBar[detectedBar].barSizeLow = -+ mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex-1)); -+ -+ -+ -+ /* restore original value */ -+ mvPciIfConfigWrite(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex-1), -+ tmpBaseLow); -+ -+ -+ /* now do the same for BaseHigh */ -+ -+ /* write oxffffffff to the bar to get the size */ -+ mvPciIfConfigWrite(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex), -+ 0xffffffff); -+ -+ /* read size */ -+ pPciAgent->pciBar[detectedBar].barSizeHigh = -+ mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex)); -+ -+ /* restore original value */ -+ mvPciIfConfigWrite(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex), -+ tmpBaseHigh); -+ -+ if ((0 == pPciAgent->pciBar[detectedBar].barSizeLow)&& -+ (0 == pPciAgent->pciBar[detectedBar].barSizeHigh)) -+ { -+ /* this bar is not applicable for this device, -+ ignore all previous settings and check the next bar*/ -+ -+ /* we though this was a 64bit bar , and it seems this -+ was wrong ! so decrement barIndex */ -+ barIndex--; -+ continue; -+ } -+ -+ /* calculate the full 64 bit size */ -+ -+ if (0 != pPciAgent->pciBar[detectedBar].barSizeHigh) -+ { -+ pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_MEM_BASE_MASK; -+ -+ pPciAgent->pciBar[detectedBar].barSizeLow = -+ ~pPciAgent->pciBar[detectedBar].barSizeLow + 1; -+ -+ pPciAgent->pciBar[detectedBar].barSizeHigh = 0; -+ -+ } -+ else -+ { -+ -+ pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_MEM_BASE_MASK; -+ -+ pPciAgent->pciBar[detectedBar].barSizeLow = -+ ~pPciAgent->pciBar[detectedBar].barSizeLow + 1; -+ -+ pPciAgent->pciBar[detectedBar].barSizeHigh = 0; -+ -+ } -+ -+ -+ -+ } -+ else /* 32bit bar */ -+ { -+ /* write oxffffffff to the bar to get the size */ -+ mvPciIfConfigWrite(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex), -+ 0xffffffff); -+ -+ /* read size */ -+ pPciAgent->pciBar[detectedBar].barSizeLow = -+ mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex)); -+ -+ if (0 == pPciAgent->pciBar[detectedBar].barSizeLow) -+ { -+ /* this bar is not applicable for this device, -+ ignore all previous settings and check the next bar*/ -+ continue; -+ } -+ -+ -+ /* restore original value */ -+ mvPciIfConfigWrite(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex), -+ tmpBaseLow); -+ -+ /* calculate size low */ -+ -+ if (PCI_MEMORY_BAR == pPciAgent->pciBar[detectedBar].barMapping) -+ { -+ pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_MEM_BASE_MASK; -+ } -+ else -+ { -+ pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_IO_BASE_MASK; -+ } -+ -+ pPciAgent->pciBar[detectedBar].barSizeLow = -+ ~pPciAgent->pciBar[detectedBar].barSizeLow + 1; -+ -+ pPciAgent->pciBar[detectedBar].barSizeHigh = 0; -+ pPciAgent->pciBar[detectedBar].barSize = -+ (MV_U64)pPciAgent->pciBar[detectedBar].barSizeLow; -+ -+ -+ } -+ -+ /* we are here ! this means we have already detected a bar for -+ this device , now move on */ -+ -+ detectedBar++; -+ pPciAgent->barsNum++; -+ } -+ -+ return detectedBar; -+} -+ -+ -+/******************************************************************************* -+* mvPciClassNameGet - get PCI class name -+* -+* DESCRIPTION: -+* This function returns the PCI class name -+* -+* INPUT: -+* baseClassCode - Base Class Code. -+* -+* OUTPUT: -+* pType - the class name -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciClassNameGet(MV_U32 baseClassCode, MV_8 *pType) -+{ -+ -+ switch(baseClassCode) -+ { -+ case 0x0: -+ strcpy(pType,"Old generation device"); -+ break; -+ case 0x1: -+ strcpy(pType,"Mass storage controller"); -+ break; -+ case 0x2: -+ strcpy(pType,"Network controller"); -+ break; -+ case 0x3: -+ strcpy(pType,"Display controller"); -+ break; -+ case 0x4: -+ strcpy(pType,"Multimedia device"); -+ break; -+ case 0x5: -+ strcpy(pType,"Memory controller"); -+ break; -+ case 0x6: -+ strcpy(pType,"Bridge Device"); -+ break; -+ case 0x7: -+ strcpy(pType,"Simple Communication controllers"); -+ break; -+ case 0x8: -+ strcpy(pType,"Base system peripherals"); -+ break; -+ case 0x9: -+ strcpy(pType,"Input Devices"); -+ break; -+ case 0xa: -+ strcpy(pType,"Docking stations"); -+ break; -+ case 0xb: -+ strcpy(pType,"Processors"); -+ break; -+ case 0xc: -+ strcpy(pType,"Serial bus controllers"); -+ break; -+ case 0xd: -+ strcpy(pType,"Wireless controllers"); -+ break; -+ case 0xe: -+ strcpy(pType,"Intelligent I/O controllers"); -+ break; -+ case 0xf: -+ strcpy(pType,"Satellite communication controllers"); -+ break; -+ case 0x10: -+ strcpy(pType,"Encryption/Decryption controllers"); -+ break; -+ case 0x11: -+ strcpy(pType,"Data acquisition and signal processing controllers"); -+ break; -+ default: -+ strcpy(pType,"Unknown device"); -+ break; -+ } -+ -+ return MV_OK; -+ -+} -+ -+ -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,323 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvPciUtilsh -+#define __INCmvPciUtilsh -+ -+/* -+This module only support scanning of Header type 00h of pci devices -+There is no suppotr for Header type 01h of pci devices ( PCI bridges ) -+*/ -+ -+/* includes */ -+#include "mvSysHwConfig.h" -+#include "pci-if/mvPciIf.h" -+#include "pci/mvPciRegs.h" -+ -+ -+ -+/* PCI base address low bar mask */ -+#define PCI_ERROR_CODE 0xffffffff -+ -+#define PCI_BRIDGE_CLASS 0x6 -+#define P2P_BRIDGE_SUB_CLASS_CODE 0x4 -+ -+ -+#define P2P_BUSSES_NUM 0x18 -+#define P2P_IO_BASE_LIMIT_SEC_STATUS 0x1C -+#define P2P_MEM_BASE_LIMIT 0x20 -+#define P2P_PREF_MEM_BASE_LIMIT 0x24 -+#define P2P_PREF_BASE_UPPER_32 0x28 -+#define P2P_PREF_LIMIT_UPPER_32 0x2C -+#define P2P_IO_BASE_LIMIT_UPPER_16 0x30 -+#define P2P_EXP_ROM 0x38 -+ -+/* P2P_BUSSES_NUM (PBM) */ -+ -+#define PBM_PRIME_BUS_NUM_OFFS 0 -+#define PBM_PRIME_BUS_NUM_MASK (0xff << PBM_PRIME_BUS_NUM_OFFS) -+ -+#define PBM_SEC_BUS_NUM_OFFS 8 -+#define PBM_SEC_BUS_NUM_MASK (0xff << PBM_SEC_BUS_NUM_OFFS) -+ -+#define PBM_SUB_BUS_NUM_OFFS 16 -+#define PBM_SUB_BUS_NUM_MASK (0xff << PBM_SUB_BUS_NUM_OFFS) -+ -+#define PBM_SEC_LAT_TMR_OFFS 24 -+#define PBM_SEC_LAT_TMR_MASK (0xff << PBM_SEC_LAT_TMR_OFFS) -+ -+/* P2P_IO_BASE_LIMIT_SEC_STATUS (PIBLSS) */ -+ -+#define PIBLSS_IO_BASE_OFFS 0 -+#define PIBLSS_IO_BASE_MASK (0xff << PIBLSS_IO_BASE_OFFS) -+ -+#define PIBLSS_ADD_CAP_OFFS 0 -+#define PIBLSS_ADD_CAP_MASK (0x3 << PIBLSS_ADD_CAP_OFFS) -+#define PIBLSS_ADD_CAP_16BIT (0x0 << PIBLSS_ADD_CAP_OFFS) -+#define PIBLSS_ADD_CAP_32BIT (0x1 << PIBLSS_ADD_CAP_OFFS) -+ -+#define PIBLSS_LOW_ADDR_OFFS 0 -+#define PIBLSS_LOW_ADDR_MASK (0xFFF << PIBLSS_LOW_ADDR_OFFS) -+ -+#define PIBLSS_HIGH_ADDR_OFFS 12 -+#define PIBLSS_HIGH_ADDR_MASK (0xF << PIBLSS_HIGH_ADDR_OFFS) -+ -+#define PIBLSS_IO_LIMIT_OFFS 8 -+#define PIBLSS_IO_LIMIT_MASK (0xff << PIBLSS_IO_LIMIT_OFFS) -+ -+#define PIBLSS_SEC_STATUS_OFFS 16 -+#define PIBLSS_SEC_STATUS_MASK (0xffff << PIBLSS_SEC_STATUS_OFFS) -+ -+ -+/* P2P_MEM_BASE_LIMIT (PMBL)*/ -+ -+#define PMBL_MEM_BASE_OFFS 0 -+#define PMBL_MEM_BASE_MASK (0xffff << PMBL_MEM_BASE_OFFS) -+ -+#define PMBL_MEM_LIMIT_OFFS 16 -+#define PMBL_MEM_LIMIT_MASK (0xffff << PMBL_MEM_LIMIT_OFFS) -+ -+ -+#define PMBL_LOW_ADDR_OFFS 0 -+#define PMBL_LOW_ADDR_MASK (0xFFFFF << PMBL_LOW_ADDR_OFFS) -+ -+#define PMBL_HIGH_ADDR_OFFS 20 -+#define PMBL_HIGH_ADDR_MASK (0xFFF << PMBL_HIGH_ADDR_OFFS) -+ -+ -+/* P2P_PREF_MEM_BASE_LIMIT (PRMBL) */ -+ -+#define PRMBL_PREF_MEM_BASE_OFFS 0 -+#define PRMBL_PREF_MEM_BASE_MASK (0xffff << PRMBL_PREF_MEM_BASE_OFFS) -+ -+#define PRMBL_PREF_MEM_LIMIT_OFFS 16 -+#define PRMBL_PREF_MEM_LIMIT_MASK (0xffff<= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexModeGet: ERR. Invalid PEX interface %d\n",pexIf); -+ return MV_ERROR; -+ } -+ } -+ -+ pexData = MV_REG_READ(PEX_CTRL_REG(pexIf)); -+ -+ switch (pexData & PXCR_DEV_TYPE_CTRL_MASK) -+ { -+ case PXCR_DEV_TYPE_CTRL_CMPLX: -+ pexMode->pexType = MV_PEX_ROOT_COMPLEX; -+ break; -+ case PXCR_DEV_TYPE_CTRL_POINT: -+ pexMode->pexType = MV_PEX_END_POINT; -+ break; -+ -+ } -+ -+ /* Check if we have link */ -+ if (MV_REG_READ(PEX_STATUS_REG(pexIf)) & PXSR_DL_DOWN) -+ { -+ pexMode->pexLinkUp = MV_FALSE; -+ -+ /* If there is no link, the auto negotiation data is worthless */ -+ pexMode->pexWidth = MV_PEX_WITDH_INVALID; -+ } -+ else -+ { -+ pexMode->pexLinkUp = MV_TRUE; -+ -+ /* We have link. The link width is now valid */ -+ pexData = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG)); -+ pexMode->pexWidth = ((pexData & PXLCSR_NEG_LNK_WDTH_MASK) >> -+ PXLCSR_NEG_LNK_WDTH_OFFS); -+ } -+ -+ return MV_OK; -+} -+ -+ -+/* PEX configuration space read write */ -+ -+/******************************************************************************* -+* mvPexConfigRead - Read from configuration space -+* -+* DESCRIPTION: -+* This function performs a 32 bit read from PEX configuration space. -+* It supports both type 0 and type 1 of Configuration Transactions -+* (local and over bridge). In order to read from local bus segment, use -+* bus number retrieved from mvPexLocalBusNumGet(). Other bus numbers -+* will result configuration transaction of type 1 (over bridge). -+* -+* INPUT: -+* pexIf - PEX interface number. -+* bus - PEX segment bus number. -+* dev - PEX device number. -+* func - Function number. -+* regOffs - Register offset. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit register data, 0xffffffff on error -+* -+*******************************************************************************/ -+MV_U32 mvPexConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, -+ MV_U32 regOff) -+{ -+#if defined(PCIE_VIRTUAL_BRIDGE_SUPPORT) -+ return mvPexVrtBrgConfigRead (pexIf, bus, dev, func, regOff); -+} -+ -+MV_U32 mvPexHwConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, -+ MV_U32 regOff) -+{ -+#endif -+ MV_U32 pexData = 0; -+ MV_U32 localDev,localBus; -+ -+ /* Parameter checking */ -+ if (PEX_DEFAULT_IF != pexIf) -+ { -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexConfigRead: ERR. Invalid PEX interface %d\n",pexIf); -+ return 0xFFFFFFFF; -+ } -+ } -+ -+ if (dev >= MAX_PEX_DEVICES) -+ { -+ DB(mvOsPrintf("mvPexConfigRead: ERR. device number illigal %d\n", dev)); -+ return 0xFFFFFFFF; -+ } -+ -+ if (func >= MAX_PEX_FUNCS) -+ { -+ DB(mvOsPrintf("mvPexConfigRead: ERR. function num illigal %d\n", func)); -+ return 0xFFFFFFFF; -+ } -+ -+ if (bus >= MAX_PEX_BUSSES) -+ { -+ DB(mvOsPrintf("mvPexConfigRead: ERR. bus number illigal %d\n", bus)); -+ return MV_ERROR; -+ } -+ -+ DB(mvOsPrintf("mvPexConfigRead: pexIf %d, bus %d, dev %d, func %d, regOff 0x%x\n", -+ pexIf, bus, dev, func, regOff)); -+ -+ localDev = mvPexLocalDevNumGet(pexIf); -+ localBus = mvPexLocalBusNumGet(pexIf); -+ -+ /* Speed up the process. In case on no link, return MV_ERROR */ -+ if ((dev != localDev) || (bus != localBus)) -+ { -+ pexData = MV_REG_READ(PEX_STATUS_REG(pexIf)); -+ -+ if ((pexData & PXSR_DL_DOWN)) -+ { -+ return MV_ERROR; -+ } -+ } -+ -+ /* in PCI Express we have only one device number */ -+ /* and this number is the first number we encounter -+ else that the localDev*/ -+ /* spec pex define return on config read/write on any device */ -+ if (bus == localBus) -+ { -+ if (localDev == 0) -+ { -+ /* if local dev is 0 then the first number we encounter -+ after 0 is 1 */ -+ if ((dev != 1)&&(dev != localDev)) -+ { -+ return MV_ERROR; -+ } -+ } -+ else -+ { -+ /* if local dev is not 0 then the first number we encounter -+ is 0 */ -+ -+ if ((dev != 0)&&(dev != localDev)) -+ { -+ return MV_ERROR; -+ } -+ } -+ if(func != 0 ) /* i.e bridge */ -+ { -+ return MV_ERROR; -+ } -+ } -+ -+ -+ /* Creating PEX address to be passed */ -+ pexData = (bus << PXCAR_BUS_NUM_OFFS); -+ pexData |= (dev << PXCAR_DEVICE_NUM_OFFS); -+ pexData |= (func << PXCAR_FUNC_NUM_OFFS); -+ pexData |= (regOff & PXCAR_REG_NUM_MASK); /* lgacy register space */ -+ /* extended register space */ -+ pexData |=(((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >> -+ PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS); -+ -+ pexData |= PXCAR_CONFIG_EN; -+ -+ /* Write the address to the PEX configuration address register */ -+ MV_REG_WRITE(PEX_CFG_ADDR_REG(pexIf), pexData); -+ -+ DB(mvOsPrintf("mvPexConfigRead:address pexData=%x ",pexData)); -+ -+ -+ /* In order to let the PEX controller absorbed the address of the read */ -+ /* transaction we perform a validity check that the address was written */ -+ if(pexData != MV_REG_READ(PEX_CFG_ADDR_REG(pexIf))) -+ { -+ return MV_ERROR; -+ } -+ -+ /* cleaning Master Abort */ -+ MV_REG_BIT_SET(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_STATUS_AND_COMMAND), -+ PXSAC_MABORT); -+#if 0 -+ /* Guideline (GL# PCI Express-1) Erroneous Read Data on Configuration */ -+ /* This guideline is relevant for all devices except of the following devices: -+ 88F5281-BO and above, 88F5181L-A0 and above, 88F1281 A0 and above -+ 88F6183 A0 and above, 88F6183L */ -+ if ( ( (dev != localDev) || (bus != localBus) ) && -+ ( -+ !(MV_5281_DEV_ID == mvCtrlModelGet())&& -+ !((MV_5181_DEV_ID == mvCtrlModelGet())&& (mvCtrlRevGet() >= MV_5181L_A0_REV))&& -+ !(MV_1281_DEV_ID == mvCtrlModelGet())&& -+ !(MV_6183_DEV_ID == mvCtrlModelGet())&& -+ !(MV_6183L_DEV_ID == mvCtrlModelGet())&& -+ !(MV_6281_DEV_ID == mvCtrlModelGet())&& -+ !(MV_6192_DEV_ID == mvCtrlModelGet())&& -+ !(MV_6190_DEV_ID == mvCtrlModelGet())&& -+ !(MV_6180_DEV_ID == mvCtrlModelGet())&& -+ !(MV_78XX0_DEV_ID == mvCtrlModelGet()) -+ )) -+ { -+ -+ /* PCI-Express configuration read work-around */ -+ -+ /* we will use one of the Punit (AHBToMbus) windows to access the xbar -+ and read the data from there */ -+ /* -+ Need to configure the 2 free Punit (AHB to MBus bridge) -+ address decoding windows: -+ Configure the flash Window to handle Configuration space requests -+ for PEX0/1: -+ 1. write 0x7931/0x7941 to the flash window and the size, -+ 79-xbar attr (pci cfg), 3/4-xbar target (pex0/1), 1-WinEn -+ 2. write base to flash window -+ -+ Configuration transactions from the CPU should write/read the data -+ to/from address of the form: -+ addr[31:28] = 0x5 (for PEX0) or 0x6 (for PEX1) -+ addr[27:24] = extended register number -+ addr[23:16] = bus number -+ addr[15:11] = device number -+ addr[10:8] = function number -+ addr[7:0] = register number -+ */ -+ -+ #include "ctrlEnv/sys/mvAhbToMbus.h" -+ { -+ MV_U32 winNum; -+ MV_AHB_TO_MBUS_DEC_WIN originWin; -+ MV_U32 pciAddr=0; -+ MV_U32 remapLow=0,remapHigh=0; -+ -+ /* -+ We will use DEV_CS2\Flash window for this workarround -+ */ -+ -+ winNum = mvAhbToMbusWinTargetGet(PEX_CONFIG_RW_WA_TARGET); -+ -+ /* save remap values if exist */ -+ if ((1 == winNum)||(0 == winNum)) -+ { -+ remapLow = MV_REG_READ(AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum)); -+ remapHigh = MV_REG_READ(AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum)); -+ -+ } -+ -+ -+ /* save the original window values */ -+ mvAhbToMbusWinGet(winNum,&originWin); -+ -+ if (PEX_CONFIG_RW_WA_USE_ORIGINAL_WIN_VALUES) -+ { -+ /* set the window as xbar window */ -+ if (pexIf) -+ { -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), -+ (0x7931 | (((originWin.addrWin.size >> 16)-1) ) << 16)); -+ } -+ else -+ { -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), -+ (0x7941 | (((originWin.addrWin.size >> 16)-1) ) << 16)); -+ } -+ -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum), -+ originWin.addrWin.baseLow); -+ -+ /*pciAddr = originWin.addrWin.baseLow;*/ -+ pciAddr = (MV_U32)CPU_MEMIO_UNCACHED_ADDR( -+ (MV_U32)originWin.addrWin.baseLow); -+ -+ } -+ else -+ { -+ /* set the window as xbar window */ -+ if (pexIf) -+ { -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), -+ (0x7931 | (((PEX_CONFIG_RW_WA_SIZE >> 16)-1) ) << 16)); -+ } -+ else -+ { -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), -+ (0x7941 | (((PEX_CONFIG_RW_WA_SIZE >> 16)-1) ) << 16)); -+ } -+ -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum), -+ PEX_CONFIG_RW_WA_BASE); -+ -+ pciAddr = (MV_U32)CPU_MEMIO_UNCACHED_ADDR(PEX_CONFIG_RW_WA_BASE); -+ } -+ -+ -+ /* remap should be as base */ -+ if ((1 == winNum)||(0 == winNum)) -+ { -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum),pciAddr); -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum),0); -+ -+ } -+ -+ /* extended register space */ -+ pciAddr |= (bus << 16); -+ pciAddr |= (dev << 11); -+ pciAddr |= (func << 8); -+ pciAddr |= (regOff & PXCAR_REG_NUM_MASK); /* lgacy register space */ -+ -+ pexData = *(MV_U32*)pciAddr; -+ pexData = MV_32BIT_LE(pexData); /* Data always in LE */ -+ -+ /* restore the original window values */ -+ mvAhbToMbusWinSet(winNum,&originWin); -+ -+ /* restore original remap values*/ -+ if ((1 == winNum)||(0 == winNum)) -+ { -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum),remapLow); -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum),remapHigh); -+ -+ } -+ } -+ } -+ else -+#endif -+ { -+ /* Read the Data returned in the PEX Data register */ -+ pexData = MV_REG_READ(PEX_CFG_DATA_REG(pexIf)); -+ -+ } -+ -+ DB(mvOsPrintf("mvPexConfigRead: got : %x \n",pexData)); -+ -+ return pexData; -+ -+} -+ -+/******************************************************************************* -+* mvPexConfigWrite - Write to configuration space -+* -+* DESCRIPTION: -+* This function performs a 32 bit write to PEX configuration space. -+* It supports both type 0 and type 1 of Configuration Transactions -+* (local and over bridge). In order to write to local bus segment, use -+* bus number retrieved from mvPexLocalBusNumGet(). Other bus numbers -+* will result configuration transaction of type 1 (over bridge). -+* -+* INPUT: -+* pexIf - PEX interface number. -+* bus - PEX segment bus number. -+* dev - PEX device number. -+* func - Function number. -+* regOffs - Register offset. -+* data - 32bit data. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data) -+{ -+#if defined(PCIE_VIRTUAL_BRIDGE_SUPPORT) -+ return mvPexVrtBrgConfigWrite (pexIf, bus, dev, func, regOff, data); -+} -+ -+MV_STATUS mvPexHwConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data) -+{ -+#endif -+ MV_U32 pexData = 0; -+ MV_U32 localDev,localBus; -+ -+ /* Parameter checking */ -+ if (PEX_DEFAULT_IF != pexIf) -+ { -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexConfigWrite: ERR. Invalid PEX interface %d\n", -+ pexIf); -+ return MV_ERROR; -+ } -+ } -+ -+ if (dev >= MAX_PEX_DEVICES) -+ { -+ mvOsPrintf("mvPexConfigWrite: ERR. device number illigal %d\n",dev); -+ return MV_BAD_PARAM; -+ } -+ -+ if (func >= MAX_PEX_FUNCS) -+ { -+ mvOsPrintf("mvPexConfigWrite: ERR. function number illigal %d\n", func); -+ return MV_ERROR; -+ } -+ -+ if (bus >= MAX_PEX_BUSSES) -+ { -+ mvOsPrintf("mvPexConfigWrite: ERR. bus number illigal %d\n", bus); -+ return MV_ERROR; -+ } -+ -+ -+ -+ localDev = mvPexLocalDevNumGet(pexIf); -+ localBus = mvPexLocalBusNumGet(pexIf); -+ -+ -+ /* in PCI Express we have only one device number other than ourselves*/ -+ /* and this number is the first number we encounter -+ else than the localDev that can be any valid dev number*/ -+ /* pex spec define return on config read/write on any device */ -+ if (bus == localBus) -+ { -+ -+ if (localDev == 0) -+ { -+ /* if local dev is 0 then the first number we encounter -+ after 0 is 1 */ -+ if ((dev != 1)&&(dev != localDev)) -+ { -+ return MV_ERROR; -+ } -+ -+ } -+ else -+ { -+ /* if local dev is not 0 then the first number we encounter -+ is 0 */ -+ -+ if ((dev != 0)&&(dev != localDev)) -+ { -+ return MV_ERROR; -+ } -+ } -+ -+ -+ } -+ -+ /* if we are not accessing ourselves , then check the link */ -+ if ((dev != localDev) || (bus != localBus) ) -+ { -+ /* workarround */ -+ /* when no link return MV_ERROR */ -+ -+ pexData = MV_REG_READ(PEX_STATUS_REG(pexIf)); -+ -+ if ((pexData & PXSR_DL_DOWN)) -+ { -+ return MV_ERROR; -+ } -+ -+ } -+ -+ pexData =0; -+ -+ /* Creating PEX address to be passed */ -+ pexData |= (bus << PXCAR_BUS_NUM_OFFS); -+ pexData |= (dev << PXCAR_DEVICE_NUM_OFFS); -+ pexData |= (func << PXCAR_FUNC_NUM_OFFS); -+ pexData |= (regOff & PXCAR_REG_NUM_MASK); /* lgacy register space */ -+ /* extended register space */ -+ pexData |=(((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >> -+ PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS); -+ pexData |= PXCAR_CONFIG_EN; -+ -+ DB(mvOsPrintf("mvPexConfigWrite: If=%x bus=%x func=%x dev=%x regOff=%x data=%x \n", -+ pexIf,bus,func,dev,regOff,data,pexData) ); -+ -+ /* Write the address to the PEX configuration address register */ -+ MV_REG_WRITE(PEX_CFG_ADDR_REG(pexIf), pexData); -+ -+ /* Clear CPU pipe. Important where CPU can perform OOO execution */ -+ CPU_PIPE_FLUSH; -+ -+ /* In order to let the PEX controller absorbed the address of the read */ -+ /* transaction we perform a validity check that the address was written */ -+ if(pexData != MV_REG_READ(PEX_CFG_ADDR_REG(pexIf))) -+ { -+ return MV_ERROR; -+ } -+ -+ /* Write the Data passed to the PEX Data register */ -+ MV_REG_WRITE(PEX_CFG_DATA_REG(pexIf), data); -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvPexMasterEnable - Enable/disale PEX interface master transactions. -+* -+* DESCRIPTION: -+* This function performs read modified write to PEX command status -+* (offset 0x4) to set/reset bit 2. After this bit is set, the PEX -+* master is allowed to gain ownership on the bus, otherwise it is -+* incapable to do so. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexMasterEnable(MV_U32 pexIf, MV_BOOL enable) -+{ -+ MV_U32 pexCommandStatus; -+ MV_U32 localBus; -+ MV_U32 localDev; -+ -+ /* Parameter checking */ -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexMasterEnable: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_ERROR; -+ } -+ -+ localBus = mvPexLocalBusNumGet(pexIf); -+ localDev = mvPexLocalDevNumGet(pexIf); -+ -+ pexCommandStatus = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, -+ PEX_STATUS_AND_COMMAND)); -+ -+ -+ if (MV_TRUE == enable) -+ { -+ pexCommandStatus |= PXSAC_MASTER_EN; -+ } -+ else -+ { -+ pexCommandStatus &= ~PXSAC_MASTER_EN; -+ } -+ -+ -+ MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_STATUS_AND_COMMAND), -+ pexCommandStatus); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPexSlaveEnable - Enable/disale PEX interface slave transactions. -+* -+* DESCRIPTION: -+* This function performs read modified write to PEX command status -+* (offset 0x4) to set/reset bit 0 and 1. After those bits are set, -+* the PEX slave is allowed to respond to PEX IO space access (bit 0) -+* and PEX memory space access (bit 1). -+* -+* INPUT: -+* pexIf - PEX interface number. -+* dev - PEX device number. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexSlaveEnable(MV_U32 pexIf, MV_U32 bus,MV_U32 dev, MV_BOOL enable) -+{ -+ MV_U32 pexCommandStatus; -+ MV_U32 RegOffs; -+ -+ /* Parameter checking */ -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexSlaveEnable: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ if (dev >= MAX_PEX_DEVICES) -+ { -+ mvOsPrintf("mvPexLocalDevNumSet: ERR. device number illigal %d\n", dev); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ -+ RegOffs = PEX_STATUS_AND_COMMAND; -+ -+ pexCommandStatus = mvPexConfigRead(pexIf, bus, dev, 0, RegOffs); -+ -+ if (MV_TRUE == enable) -+ { -+ pexCommandStatus |= (PXSAC_IO_EN | PXSAC_MEM_EN); -+ } -+ else -+ { -+ pexCommandStatus &= ~(PXSAC_IO_EN | PXSAC_MEM_EN); -+ } -+ -+ mvPexConfigWrite(pexIf, bus, dev, 0, RegOffs, pexCommandStatus); -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvPexLocalBusNumSet - Set PEX interface local bus number. -+* -+* DESCRIPTION: -+* This function sets given PEX interface its local bus number. -+* Note: In case the PEX interface is PEX-X, the information is read-only. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* busNum - Bus number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_NOT_ALLOWED in case PEX interface is PEX-X. -+* MV_BAD_PARAM on bad parameters , -+* otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexLocalBusNumSet(MV_U32 pexIf, MV_U32 busNum) -+{ -+ MV_U32 pexStatus; -+ MV_U32 localBus; -+ MV_U32 localDev; -+ -+ -+ /* Parameter checking */ -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexLocalBusNumSet: ERR. Invalid PEX interface %d\n",pexIf); -+ return MV_BAD_PARAM; -+ } -+ if (busNum >= MAX_PEX_BUSSES) -+ { -+ mvOsPrintf("mvPexLocalBusNumSet: ERR. bus number illigal %d\n", busNum); -+ return MV_ERROR; -+ -+ } -+ -+ localBus = mvPexLocalBusNumGet(pexIf); -+ localDev = mvPexLocalDevNumGet(pexIf); -+ -+ -+ -+ pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); -+ -+ pexStatus &= ~PXSR_PEX_BUS_NUM_MASK; -+ -+ pexStatus |= (busNum << PXSR_PEX_BUS_NUM_OFFS) & PXSR_PEX_BUS_NUM_MASK; -+ -+ MV_REG_WRITE(PEX_STATUS_REG(pexIf), pexStatus); -+ -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPexLocalBusNumGet - Get PEX interface local bus number. -+* -+* DESCRIPTION: -+* This function gets the local bus number of a given PEX interface. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Local bus number.0xffffffff on Error -+* -+*******************************************************************************/ -+MV_U32 mvPexLocalBusNumGet(MV_U32 pexIf) -+{ -+ MV_U32 pexStatus; -+ -+ /* Parameter checking */ -+ if (PEX_DEFAULT_IF != pexIf) -+ { -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexLocalBusNumGet: ERR. Invalid PEX interface %d\n",pexIf); -+ return 0xFFFFFFFF; -+ } -+ } -+ -+ -+ pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); -+ -+ pexStatus &= PXSR_PEX_BUS_NUM_MASK; -+ -+ return (pexStatus >> PXSR_PEX_BUS_NUM_OFFS); -+ -+} -+ -+ -+/******************************************************************************* -+* mvPexLocalDevNumSet - Set PEX interface local device number. -+* -+* DESCRIPTION: -+* This function sets given PEX interface its local device number. -+* Note: In case the PEX interface is PEX-X, the information is read-only. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* devNum - Device number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_NOT_ALLOWED in case PEX interface is PEX-X. -+* MV_BAD_PARAM on bad parameters , -+* otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexLocalDevNumSet(MV_U32 pexIf, MV_U32 devNum) -+{ -+ MV_U32 pexStatus; -+ MV_U32 localBus; -+ MV_U32 localDev; -+ -+ /* Parameter checking */ -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexLocalDevNumSet: ERR. Invalid PEX interface %d\n",pexIf); -+ return MV_BAD_PARAM; -+ } -+ if (devNum >= MAX_PEX_DEVICES) -+ { -+ mvOsPrintf("mvPexLocalDevNumSet: ERR. device number illigal %d\n", -+ devNum); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ localBus = mvPexLocalBusNumGet(pexIf); -+ localDev = mvPexLocalDevNumGet(pexIf); -+ -+ -+ pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); -+ -+ pexStatus &= ~PXSR_PEX_DEV_NUM_MASK; -+ -+ pexStatus |= (devNum << PXSR_PEX_DEV_NUM_OFFS) & PXSR_PEX_DEV_NUM_MASK; -+ -+ MV_REG_WRITE(PEX_STATUS_REG(pexIf), pexStatus); -+ -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvPexLocalDevNumGet - Get PEX interface local device number. -+* -+* DESCRIPTION: -+* This function gets the local device number of a given PEX interface. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Local device number. 0xffffffff on Error -+* -+*******************************************************************************/ -+MV_U32 mvPexLocalDevNumGet(MV_U32 pexIf) -+{ -+ MV_U32 pexStatus; -+ -+ /* Parameter checking */ -+ -+ if (PEX_DEFAULT_IF != pexIf) -+ { -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexLocalDevNumGet: ERR. Invalid PEX interface %d\n", -+ pexIf); -+ return 0xFFFFFFFF; -+ } -+ } -+ -+ pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); -+ -+ pexStatus &= PXSR_PEX_DEV_NUM_MASK; -+ -+ return (pexStatus >> PXSR_PEX_DEV_NUM_OFFS); -+} -+ -+MV_VOID mvPexPhyRegRead(MV_U32 pexIf, MV_U32 regOffset, MV_U16 *value) -+{ -+ -+ MV_U32 regAddr; -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexPhyRegRead: ERR. Invalid PEX interface %d\n", pexIf); -+ return; -+ } -+ regAddr = (BIT31 | ((regOffset & 0x3fff) << 16)); -+ MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexIf), regAddr); -+ *value = MV_REG_READ(PEX_PHY_ACCESS_REG(pexIf)); -+} -+ -+ -+MV_VOID mvPexPhyRegWrite(MV_U32 pexIf, MV_U32 regOffset, MV_U16 value) -+{ -+ -+ MV_U32 regAddr; -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexPhyRegWrite: ERR. Invalid PEX interface %d\n", pexIf); -+ return; -+ } -+ regAddr = (((regOffset & 0x3fff) << 16) | value); -+ MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexIf), regAddr); -+} -+ -+/******************************************************************************* -+* mvPexActiveStateLinkPMEnable -+* -+* DESCRIPTION: -+* Enable Active Link State Power Management -+* -+* INPUT: -+* pexIf - PEX interface number. -+* enable - MV_TRUE to enable ASPM, MV_FALSE to disable. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* MV_OK on success , MV_ERROR otherwise -+* -+*******************************************************************************/ -+MV_STATUS mvPexActiveStateLinkPMEnable(MV_U32 pexIf, MV_BOOL enable) -+{ -+ MV_U32 reg; -+ -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexActiveStateLinkPMEnable: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_ERROR; -+ } -+ -+ reg = MV_REG_READ(PEX_PWR_MNG_EXT_REG(pexIf)) & ~PXPMER_L1_ASPM_EN_MASK; -+ if(enable == MV_TRUE) -+ reg |= PXPMER_L1_ASPM_EN_MASK; -+ MV_REG_WRITE(PEX_PWR_MNG_EXT_REG(pexIf), reg); -+ -+ /* Enable / Disable L0/1 entry */ -+ reg = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG)) -+ & ~PXLCSR_ASPM_CNT_MASK; -+ if(enable == MV_TRUE) -+ reg |= PXLCSR_ASPM_CNT_L0S_L1S_ENT_SUPP; -+ MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG), reg); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPexForceX1 -+* -+* DESCRIPTION: -+* shut down lanes 1-3 if recognize that attached to an x1 end-point -+* INPUT: -+* pexIf - PEX interface number. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* MV_OK on success , MV_ERROR otherwise -+* -+*******************************************************************************/ -+MV_U32 mvPexForceX1(MV_U32 pexIf) -+{ -+ MV_U32 regData = 0; -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexForceX1: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ -+ regData = MV_REG_READ(PEX_CTRL_REG(pexIf)) & ~(PXCR_CONF_LINK_MASK) ; -+ regData |= PXCR_CONF_LINK_X1; -+ -+ MV_REG_WRITE(PEX_CTRL_REG(pexIf), regData); -+ return MV_OK; -+} -+ -+MV_BOOL mvPexIsPowerUp(MV_U32 pexIf) -+{ -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexIsPowerUp: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_FALSE; -+ } -+ return mvCtrlPwrClckGet(PEX_UNIT_ID, pexIf); -+} -+ -+ -+MV_VOID mvPexPowerDown(MV_U32 pexIf) -+{ -+ if ( (mvCtrlModelGet() == MV_78XX0_DEV_ID) || -+ (mvCtrlModelGet() == MV_76100_DEV_ID) || -+ (mvCtrlModelGet() == MV_78100_DEV_ID) || -+ (mvCtrlModelGet() == MV_78200_DEV_ID) ) -+ { -+ mvCtrlPwrClckSet(PEX_UNIT_ID, pexIf, MV_FALSE); -+ } -+ else -+ { -+ MV_REG_WRITE((0x41B00 -(pexIf)*0x10000), 0x20800087); -+ } -+} -+ -+ -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,168 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCPEXH -+#define __INCPEXH -+ -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "pex/mvPexRegs.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+ -+ -+ -+/* NOTE not supported in this driver:*/ -+ -+ -+/* defines */ -+/* The number of supported PEX interfaces depend on Marvell controller */ -+/* device number. This device number ID is located on the PEX unit */ -+/* configuration header. This creates a loop where calling PEX */ -+/* configuration read/write routine results a call to get PEX configuration */ -+/* information etc. This macro defines a default PEX interface. This PEX */ -+/* interface is sure to exist. */ -+#define PEX_DEFAULT_IF 0 -+ -+ -+/* typedefs */ -+/* The Marvell controller supports both root complex and end point devices */ -+/* This enumeration describes the PEX type. */ -+typedef enum _mvPexType -+{ -+ MV_PEX_ROOT_COMPLEX, /* root complex device */ -+ MV_PEX_END_POINT /* end point device */ -+}MV_PEX_TYPE; -+ -+typedef enum _mvPexWidth -+{ -+ MV_PEX_WITDH_X1 = 1, -+ MV_PEX_WITDH_X2, -+ MV_PEX_WITDH_X3, -+ MV_PEX_WITDH_X4, -+ MV_PEX_WITDH_INVALID -+}MV_PEX_WIDTH; -+ -+/* PEX Bar attributes */ -+typedef struct _mvPexMode -+{ -+ MV_PEX_TYPE pexType; -+ MV_PEX_WIDTH pexWidth; -+ MV_BOOL pexLinkUp; -+}MV_PEX_MODE; -+ -+ -+ -+/* Global Functions prototypes */ -+/* mvPexInit - Initialize PEX interfaces*/ -+MV_STATUS mvPexHalInit(MV_U32 pexIf, MV_PEX_TYPE pexType); -+ -+/* mvPexModeGet - Get Pex If mode */ -+MV_U32 mvPexModeGet(MV_U32 pexIf,MV_PEX_MODE *pexMode); -+ -+/* mvPexConfigRead - Read from configuration space */ -+MV_U32 mvPexConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func,MV_U32 regOff); -+ -+/* mvPexConfigWrite - Write to configuration space */ -+MV_STATUS mvPexConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data); -+ -+/* mvPexMasterEnable - Enable/disale PEX interface master transactions.*/ -+MV_STATUS mvPexMasterEnable(MV_U32 pexIf, MV_BOOL enable); -+ -+/* mvPexSlaveEnable - Enable/disale PEX interface slave transactions.*/ -+MV_STATUS mvPexSlaveEnable(MV_U32 pexIf, MV_U32 bus,MV_U32 dev, MV_BOOL enable); -+ -+/* mvPexLocalBusNumSet - Set PEX interface local bus number.*/ -+MV_STATUS mvPexLocalBusNumSet(MV_U32 pexIf, MV_U32 busNum); -+ -+/* mvPexLocalBusNumGet - Get PEX interface local bus number.*/ -+MV_U32 mvPexLocalBusNumGet(MV_U32 pexIf); -+ -+/* mvPexLocalDevNumSet - Set PEX interface local device number.*/ -+MV_STATUS mvPexLocalDevNumSet(MV_U32 pexIf, MV_U32 devNum); -+ -+/* mvPexLocalDevNumGet - Get PEX interface local device number.*/ -+MV_U32 mvPexLocalDevNumGet(MV_U32 pexIf); -+/* mvPexForceX1 - Force PEX interface to X1 mode. */ -+MV_U32 mvPexForceX1(MV_U32 pexIf); -+ -+/* mvPexIsPowerUp - Is PEX interface Power up? */ -+MV_BOOL mvPexIsPowerUp(MV_U32 pexIf); -+ -+/* mvPexPowerDown - Power Down */ -+MV_VOID mvPexPowerDown(MV_U32 pexIf); -+ -+/* mvPexPowerUp - Power Up */ -+MV_VOID mvPexPowerUp(MV_U32 pexIf); -+ -+/* mvPexPhyRegRead - Pex phy read */ -+MV_VOID mvPexPhyRegRead(MV_U32 pexIf, MV_U32 regOffset, MV_U16 *value); -+ -+/* mvPexPhyRegWrite - Pex phy write */ -+MV_VOID mvPexPhyRegWrite(MV_U32 pexIf, MV_U32 regOffset, MV_U16 value); -+ -+MV_STATUS mvPexActiveStateLinkPMEnable(MV_U32 pexIf, MV_BOOL enable); -+ -+#endif /* #ifndef __INCPEXH */ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,751 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCPEXREGSH -+#define __INCPEXREGSH -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* defines */ -+#define MAX_PEX_DEVICES 32 -+#define MAX_PEX_FUNCS 8 -+#define MAX_PEX_BUSSES 256 -+ -+ -+ -+/*********************************************************/ -+/* PCI Express Configuration Cycles Generation Registers */ -+/*********************************************************/ -+ -+#define PEX_CFG_ADDR_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x18F8) -+#define PEX_CFG_DATA_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x18FC) -+#define PEX_PHY_ACCESS_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1B00) -+/* PCI Express Configuration Address Register */ -+/* PEX_CFG_ADDR_REG (PXCAR)*/ -+ -+#define PXCAR_REG_NUM_OFFS 2 -+#define PXCAR_REG_NUM_MAX 0x3F -+#define PXCAR_REG_NUM_MASK (PXCAR_REG_NUM_MAX << PXCAR_REG_NUM_OFFS) -+#define PXCAR_FUNC_NUM_OFFS 8 -+#define PXCAR_FUNC_NUM_MAX 0x7 -+#define PXCAR_FUNC_NUM_MASK (PXCAR_FUNC_NUM_MAX << PXCAR_FUNC_NUM_OFFS) -+#define PXCAR_DEVICE_NUM_OFFS 11 -+#define PXCAR_DEVICE_NUM_MAX 0x1F -+#define PXCAR_DEVICE_NUM_MASK (PXCAR_DEVICE_NUM_MAX << PXCAR_DEVICE_NUM_OFFS) -+#define PXCAR_BUS_NUM_OFFS 16 -+#define PXCAR_BUS_NUM_MAX 0xFF -+#define PXCAR_BUS_NUM_MASK (PXCAR_BUS_NUM_MAX << PXCAR_BUS_NUM_OFFS) -+#define PXCAR_EXT_REG_NUM_OFFS 24 -+#define PXCAR_EXT_REG_NUM_MAX 0xF -+ -+/* in pci express register address is now the legacy register address (8 bits) -+with the new extended register address (more 4 bits) , below is the mask of -+the upper 4 bits of the full register address */ -+ -+#define PXCAR_REAL_EXT_REG_NUM_OFFS 8 -+#define PXCAR_EXT_REG_NUM_MASK (PXCAR_EXT_REG_NUM_MAX << PXCAR_EXT_REG_NUM_OFFS) -+#define PXCAR_CONFIG_EN BIT31 -+ -+#define PXCAR_REAL_EXT_REG_NUM_OFFS 8 -+#define PXCAR_REAL_EXT_REG_NUM_MASK (0xF << PXCAR_REAL_EXT_REG_NUM_OFFS) -+ -+/* The traditional PCI spec defined 6-bit field to describe register offset.*/ -+/* The new PCI Express extend the register offset by an extra 4-bits. */ -+/* The below macro assign 10-bit register offset into the apprpreate */ -+/* fields in the CFG_ADDR_REG */ -+#define PXCAR_REG_OFFS_SET(regOffs) \ -+ ( (regOff & PXCAR_REG_NUM_MASK) | \ -+ ( ((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >> PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS) ) -+ -+/***********************************/ -+/* PCI Express Interrupt registers */ -+/***********************************/ -+#define PEX_CAUSE_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1900) -+#define PEX_MASK_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1910) -+ -+#define PXICR_TX_REQ_IN_DLDOWN_ERR BIT0 /* Transmit request while field */ -+ /* of the PCI Express */ -+/* PCI Express Interrupt Cause */ -+/* PEX_INT_CAUSE_REG (PXICR)*/ -+/* PEX_INT_MASK_REG*/ -+/* -+NOTE:All bits except bits[27:24] are Read/Write Clear only. A cause bit sets -+upon an error event occurrence. A write of 0 clears the bit. A write of 1 has -+no affect. Bits[24:27} are set and cleared upon reception of interrupt -+emulation messages. -+ -+Mask bit per cause bit. If a bit is set to 1, the corresponding event is -+enabled. Mask does not affect setting of the Interrupt Cause register bits; -+it only affects the assertion of the interrupt .*/ -+ -+ -+#define PXICR_MDIS_CAUSE BIT1 /* Attempt to generate PCI transaction -+ while master is disabled */ -+#define PXICR_ERR_WRTO_REG_CAUSE BIT3 /* Erroneous write attempt to -+ PCI Express internal register*/ -+#define PXICR_HIT_DFLT_WIN_ERR BIT4 /* Hit Default Window Error */ -+#define PXICR_RX_RAM_PAR_ERR BIT6 /* Rx RAM Parity Error */ -+#define PXICR_TX_RAM_PAR_ERR BIT7 /* Tx RAM Parity Error */ -+#define PXICR_COR_ERR_DET BIT8 /* Correctable Error Detected*/ -+#define PXICR_NF_ERR_DET BIT9 /* Non-Fatal Error Detected*/ -+#define PXICR_FERR_DET BIT10 /* Fatal Error Detected*/ -+#define PXICR_DSTATE_CHANGE BIT11 /* Dstate Change Indication*/ -+#define PXICR_BIST BIT12 /* PCI-Express BIST activated*/ -+#define PXICR_FLW_CTRL_PROT BIT14 /* Flow Control Protocol Error */ -+ -+#define PXICR_RCV_UR_CA_ERR BIT15 /* Received UR or CA status. */ -+#define PXICR_RCV_ERR_FATAL BIT16 /* Received ERR_FATAL message.*/ -+#define PXICR_RCV_ERR_NON_FATAL BIT17 /* Received ERR_NONFATAL message*/ -+#define PXICR_RCV_ERR_COR BIT18 /* Received ERR_COR message.*/ -+#define PXICR_RCV_CRS BIT19 /* Received CRS completion status*/ -+#define PXICR_SLV_HOT_RESET BIT20 /* Received Hot Reset Indication*/ -+#define PXICR_SLV_DIS_LINK BIT21 /* Slave Disable Link Indication*/ -+#define PXICR_SLV_LB BIT22 /* Slave Loopback Indication*/ -+#define PXICR_LINK_FAIL BIT23 /* Link Failure indication.*/ -+#define PXICR_RCV_INTA BIT24 /* IntA status.*/ -+#define PXICR_RCV_INTB BIT25 /* IntB status.*/ -+#define PXICR_RCV_INTC BIT26 /* IntC status.*/ -+#define PXICR_RCV_INTD BIT27 /* IntD status.*/ -+#define PXICR_RCV_PM_PME BIT28 /* Received PM_PME message. */ -+ -+ -+/********************************************/ -+/* PCI Express Control and Status Registers */ -+/********************************************/ -+#define PEX_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A00) -+#define PEX_STATUS_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A04) -+#define PEX_COMPLT_TMEOUT_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A10) -+#define PEX_PWR_MNG_EXT_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A18) -+#define PEX_FLOW_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A20) -+#define PEX_ACK_TMR_4X_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A30) -+#define PEX_ACK_TMR_1X_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A40) -+#define PEX_TL_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1AB0) -+ -+ -+#define PEX_RAM_PARITY_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A50) -+/* PCI Express Control Register */ -+/* PEX_CTRL_REG (PXCR) */ -+ -+#define PXCR_CONF_LINK_OFFS 0 -+#define PXCR_CONF_LINK_MASK (1 << PXCR_CONF_LINK_OFFS) -+#define PXCR_CONF_LINK_X4 (0 << PXCR_CONF_LINK_OFFS) -+#define PXCR_CONF_LINK_X1 (1 << PXCR_CONF_LINK_OFFS) -+#define PXCR_DEV_TYPE_CTRL_OFFS 1 /*PCI ExpressDevice Type Control*/ -+#define PXCR_DEV_TYPE_CTRL_MASK BIT1 -+#define PXCR_DEV_TYPE_CTRL_CMPLX (1 << PXCR_DEV_TYPE_CTRL_OFFS) -+#define PXCR_DEV_TYPE_CTRL_POINT (0 << PXCR_DEV_TYPE_CTRL_OFFS) -+#define PXCR_CFG_MAP_TO_MEM_EN BIT2 /* Configuration Header Mapping -+ to Memory Space Enable */ -+ -+#define PXCR_CFG_MAP_TO_MEM_EN BIT2 /* Configuration Header Mapping -+ to Memory Space Enable*/ -+ -+#define PXCR_RSRV1_OFFS 5 -+#define PXCR_RSRV1_MASK (0x7 << PXCR_RSRV1_OFFS) -+#define PXCR_RSRV1_VAL (0x0 << PXCR_RSRV1_OFFS) -+ -+#define PXCR_CONF_MAX_OUTSTND_OFFS 8 /*Maximum outstanding NP requests as a master*/ -+#define PXCR_CONF_MAX_OUTSTND_MASK (0x3 << PXCR_CONF_MAX_OUTSTND_OFFS) -+ -+ -+#define PXCR_CONF_NFTS_OFFS 16 /*number of FTS Ordered-Sets*/ -+#define PXCR_CONF_NFTS_MASK (0xff << PXCR_CONF_NFTS_OFFS) -+ -+#define PXCR_CONF_MSTR_HOT_RESET BIT24 /*Master Hot-Reset.*/ -+#define PXCR_CONF_MSTR_LB BIT26 /* Master Loopback */ -+#define PXCR_CONF_MSTR_DIS_SCRMB BIT27 /* Master Disable Scrambling*/ -+#define PXCR_CONF_DIRECT_DIS_SCRMB BIT28 /* Direct Disable Scrambling*/ -+ -+/* PCI Express Status Register */ -+/* PEX_STATUS_REG (PXSR) */ -+ -+#define PXSR_DL_DOWN BIT0 /* DL_Down indication.*/ -+ -+#define PXSR_PEX_BUS_NUM_OFFS 8 /* Bus Number Indication */ -+#define PXSR_PEX_BUS_NUM_MASK (0xff << PXSR_PEX_BUS_NUM_OFFS) -+ -+#define PXSR_PEX_DEV_NUM_OFFS 16 /* Device Number Indication */ -+#define PXSR_PEX_DEV_NUM_MASK (0x1f << PXSR_PEX_DEV_NUM_OFFS) -+ -+#define PXSR_PEX_SLV_HOT_RESET BIT24 /* Slave Hot Reset Indication*/ -+#define PXSR_PEX_SLV_DIS_LINK BIT25 /* Slave Disable Link Indication*/ -+#define PXSR_PEX_SLV_LB BIT26 /* Slave Loopback Indication*/ -+#define PXSR_PEX_SLV_DIS_SCRMB BIT27 /* Slave Disable Scrambling Indication*/ -+ -+ -+/* PCI Express Completion Timeout Register */ -+/* PEX_COMPLT_TMEOUT_REG (PXCTR)*/ -+ -+#define PXCTR_CMP_TO_THRSHLD_OFFS 0 /* Completion Timeout Threshold */ -+#define PXCTR_CMP_TO_THRSHLD_MASK (0xffff << PXCTR_CMP_TO_THRSHLD_OFFS) -+ -+/* PCI Express Power Management Extended Register */ -+/* PEX_PWR_MNG_EXT_REG (PXPMER) */ -+ -+#define PXPMER_L1_ASPM_EN_OFFS 1 -+#define PXPMER_L1_ASPM_EN_MASK (0x1 << PXPMER_L1_ASPM_EN_OFFS) -+ -+/* PCI Express Flow Control Register */ -+/* PEX_FLOW_CTRL_REG (PXFCR)*/ -+ -+#define PXFCR_PH_INIT_FC_OFFS 0 /*Posted Headers Flow Control Credit -+ Initial Value.*/ -+#define PXFCR_PH_INIT_FC_MASK (0xff << PXFCR_PH_INIT_FC_OFFS) -+ -+ -+#define PXFCR_NPH_INIT_FC_OFFS 8 /* Classified Non-Posted Headers -+ Flow Control Credit Initial Value*/ -+#define PXFCR_NPH_INIT_FC_MASK (0xff << PXFCR_NPH_INIT_FC_OFFS) -+ -+#define PXFCR_CH_INIT_FC_OFFS 16 /* Completion Headers Flow Control -+ Credit Initial Value Infinite*/ -+ -+#define PXFCR_CH_INIT_FC_MASK (0xff << PXFCR_CH_INIT_FC_OFFS) -+ -+#define PXFCR_FC_UPDATE_TO_OFFS 24 /* Flow Control Update Timeout */ -+#define PXFCR_FC_UPDATE_TO_MASK (0xff << PXFCR_FC_UPDATE_TO_OFFS) -+ -+/* PCI Express Acknowledge Timers (4X) Register */ -+/* PEX_ACK_TMR_4X_REG (PXAT4R) */ -+#define PXAT1R_ACK_LAT_TOX4_OFFS 0 /* Ack Latency Timer Timeout Value */ -+#define PXAT1R_ACK_LAT_TOX4_MASK (0xffff << PXAT4R_ACK_LAT_TOX1_OFFS) -+#define PXAT1R_ACK_RPLY_TOX4_OFFS 16 /* Ack Replay Timer Timeout Value */ -+#define PXAT1R_ACK_RPLY_TOX4_MASK (0xffff << PXAT1R_ACK_RPLY_TOX1_OFFS) -+ -+/* PCI Express Acknowledge Timers (1X) Register */ -+/* PEX_ACK_TMR_1X_REG (PXAT1R) */ -+ -+#define PXAT1R_ACK_LAT_TOX1_OFFS 0 /* Acknowledge Latency Timer Timeout -+ Value for 1X Link*/ -+#define PXAT1R_ACK_LAT_TOX1_MASK (0xffff << PXAT1R_ACK_LAT_TOX1_OFFS) -+ -+#define PXAT1R_ACK_RPLY_TOX1_OFFS 16 /* Acknowledge Replay Timer Timeout -+ Value for 1X*/ -+#define PXAT1R_ACK_RPLY_TOX1_MASK (0xffff << PXAT1R_ACK_RPLY_TOX1_OFFS) -+ -+ -+/* PCI Express TL Control Register */ -+/* PEX_TL_CTRL_REG (PXTCR) */ -+ -+#define PXTCR_TX_CMP_BUFF_NO_OFFS 8 /*Number of completion buffers in Tx*/ -+#define PXTCR_TX_CMP_BUFF_NO_MASK (0xf << PXTCR_TX_CMP_BUFF_NO_OFFS) -+ -+/* PCI Express Debug MAC Control Register */ -+/* PEX_DEBUG_MAC_CTRL_REG (PXDMCR) */ -+ -+#define PXDMCR_LINKUP BIT4 -+ -+ -+ -+/**********************************************/ -+/* PCI Express Configuration Header Registers */ -+/**********************************************/ -+#define PEX_CFG_DIRECT_ACCESS(pexIf,cfgReg) ((PEX_IF_BASE(pexIf)) + (cfgReg)) -+ -+#define PEX_DEVICE_AND_VENDOR_ID 0x000 -+#define PEX_STATUS_AND_COMMAND 0x004 -+#define PEX_CLASS_CODE_AND_REVISION_ID 0x008 -+#define PEX_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE 0x00C -+#define PEX_MEMORY_BAR_BASE_ADDR(barNum) (0x010 + ((barNum) << 2)) -+#define PEX_MV_BAR_BASE(barNum) (0x010 + (barNum) * 8) -+#define PEX_MV_BAR_BASE_HIGH(barNum) (0x014 + (barNum) * 8) -+#define PEX_BAR0_INTER_REG 0x010 -+#define PEX_BAR0_INTER_REG_HIGH 0x014 -+#define PEX_BAR1_REG 0x018 -+#define PEX_BAR1_REG_HIGH 0x01C -+#define PEX_BAR2_REG 0x020 -+#define PEX_BAR2_REG_HIGH 0x024 -+ -+#define PEX_SUBSYS_ID_AND_SUBSYS_VENDOR_ID 0x02C -+#define PEX_EXPANSION_ROM_BASE_ADDR_REG 0x030 -+#define PEX_CAPABILTY_LIST_POINTER 0x034 -+#define PEX_INTERRUPT_PIN_AND_LINE 0x03C -+ -+/* capability list */ -+#define PEX_POWER_MNG_CAPABILITY 0x040 -+#define PEX_POWER_MNG_STATUS_CONTROL 0x044 -+ -+#define PEX_MSI_MESSAGE_CONTROL 0x050 -+#define PEX_MSI_MESSAGE_ADDR 0x054 -+#define PEX_MSI_MESSAGE_HIGH_ADDR 0x058 -+#define PEX_MSI_MESSAGE_DATA 0x05C -+ -+#define PEX_CAPABILITY_REG 0x60 -+#define PEX_DEV_CAPABILITY_REG 0x64 -+#define PEX_DEV_CTRL_STAT_REG 0x68 -+#define PEX_LINK_CAPABILITY_REG 0x6C -+#define PEX_LINK_CTRL_STAT_REG 0x70 -+ -+#define PEX_ADV_ERR_RPRT_HDR_TRGT_REG 0x100 -+#define PEX_UNCORRECT_ERR_STAT_REG 0x104 -+#define PEX_UNCORRECT_ERR_MASK_REG 0x108 -+#define PEX_UNCORRECT_ERR_SERVITY_REG 0x10C -+#define PEX_CORRECT_ERR_STAT_REG 0x110 -+#define PEX_CORRECT_ERR_MASK_REG 0x114 -+#define PEX_ADV_ERR_CAPABILITY_CTRL_REG 0x118 -+#define PEX_HDR_LOG_FIRST_DWORD_REG 0x11C -+#define PEX_HDR_LOG_SECOND_DWORD_REG 0x120 -+#define PEX_HDR_LOG_THIRD_DWORD_REG 0x124 -+#define PEX_HDR_LOG_FOURTH_DWORD_REG 0x128 -+ -+ -+ -+/* PCI Express Device and Vendor ID Register*/ -+/*PEX_DEVICE_AND_VENDOR_ID (PXDAVI)*/ -+ -+#define PXDAVI_VEN_ID_OFFS 0 /* Vendor ID */ -+#define PXDAVI_VEN_ID_MASK (0xffff << PXDAVI_VEN_ID_OFFS) -+ -+#define PXDAVI_DEV_ID_OFFS 16 /* Device ID */ -+#define PXDAVI_DEV_ID_MASK (0xffff << PXDAVI_DEV_ID_OFFS) -+ -+ -+/* PCI Express Command and Status Register*/ -+/*PEX_STATUS_AND_COMMAND (PXSAC)*/ -+ -+#define PXSAC_IO_EN BIT0 /* IO Enable */ -+#define PXSAC_MEM_EN BIT1 /* Memory Enable */ -+#define PXSAC_MASTER_EN BIT2 /* Master Enable */ -+#define PXSAC_PERR_EN BIT6 /* Parity Errors Respond Enable */ -+#define PXSAC_SERR_EN BIT8 /* Ability to assert SERR# line */ -+#define PXSAC_INT_DIS BIT10 /* Interrupt Disable */ -+#define PXSAC_INT_STAT BIT19 /* Interrupt Status */ -+#define PXSAC_CAP_LIST BIT20 /* Capability List Support */ -+#define PXSAC_MAS_DATA_PERR BIT24 /* Master Data Parity Error */ -+#define PXSAC_SLAVE_TABORT BIT27 /* Signalled Target Abort */ -+#define PXSAC_RT_ABORT BIT28 /* Recieved Target Abort */ -+#define PXSAC_MABORT BIT29 /* Recieved Master Abort */ -+#define PXSAC_SYSERR BIT30 /* Signalled system error */ -+#define PXSAC_DET_PARERR BIT31 /* Detect Parity Error */ -+ -+ -+/* PCI Express Class Code and Revision ID Register*/ -+/*PEX_CLASS_CODE_AND_REVISION_ID (PXCCARI)*/ -+ -+#define PXCCARI_REVID_OFFS 0 /* Revision ID */ -+#define PXCCARI_REVID_MASK (0xff << PXCCARI_REVID_OFFS) -+ -+#define PXCCARI_FULL_CLASS_OFFS 8 /* Full Class Code */ -+#define PXCCARI_FULL_CLASS_MASK (0xffffff << PXCCARI_FULL_CLASS_OFFS) -+ -+#define PXCCARI_PROGIF_OFFS 8 /* Prog .I/F*/ -+#define PXCCARI_PROGIF_MASK (0xff << PXCCARI_PROGIF_OFFS) -+ -+#define PXCCARI_SUB_CLASS_OFFS 16 /* Sub Class*/ -+#define PXCCARI_SUB_CLASS_MASK (0xff << PXCCARI_SUB_CLASS_OFFS) -+ -+#define PXCCARI_BASE_CLASS_OFFS 24 /* Base Class*/ -+#define PXCCARI_BASE_CLASS_MASK (0xff << PXCCARI_BASE_CLASS_OFFS) -+ -+ -+/* PCI Express BIST, Header Type and Cache Line Size Register*/ -+/*PEX_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE (PXBHTLTCL)*/ -+ -+#define PXBHTLTCL_CACHELINE_OFFS 0 /* Specifies the cache line size */ -+#define PXBHTLTCL_CACHELINE_MASK (0xff << PXBHTLTCL_CACHELINE_OFFS) -+ -+#define PXBHTLTCL_HEADTYPE_FULL_OFFS 16 /* Full Header Type */ -+#define PXBHTLTCL_HEADTYPE_FULL_MASK (0xff << PXBHTLTCL_HEADTYPE_FULL_OFFS) -+ -+#define PXBHTLTCL_MULTI_FUNC BIT23 /* Multi/Single function */ -+ -+#define PXBHTLTCL_HEADER_OFFS 16 /* Header type */ -+#define PXBHTLTCL_HEADER_MASK (0x7f << PXBHTLTCL_HEADER_OFFS) -+#define PXBHTLTCL_HEADER_STANDARD (0x0 << PXBHTLTCL_HEADER_OFFS) -+#define PXBHTLTCL_HEADER_PCI2PCI_BRIDGE (0x1 << PXBHTLTCL_HEADER_OFFS) -+ -+ -+#define PXBHTLTCL_BISTCOMP_OFFS 24 /* BIST Completion Code */ -+#define PXBHTLTCL_BISTCOMP_MASK (0xf << PXBHTLTCL_BISTCOMP_OFFS) -+ -+#define PXBHTLTCL_BISTACT BIT30 /* BIST Activate bit */ -+#define PXBHTLTCL_BISTCAP BIT31 /* BIST Capable Bit */ -+#define PXBHTLTCL_BISTCAP_OFFS 31 -+#define PXBHTLTCL_BISTCAP_MASK BIT31 -+#define PXBHTLTCL_BISTCAP_VAL 0 -+ -+ -+/* PCI Express Subsystem Device and Vendor ID */ -+/*PEX_SUBSYS_ID_AND_SUBSYS_VENDOR_ID (PXSIASVI)*/ -+ -+#define PXSIASVI_VENID_OFFS 0 /* Subsystem Manufacturer Vendor ID Number */ -+#define PXSIASVI_VENID_MASK (0xffff << PXSIASVI_VENID_OFFS) -+ -+#define PXSIASVI_DEVID_OFFS 16 /* Subsystem Device ID Number */ -+#define PXSIASVI_DEVID_MASK (0xffff << PXSIASVI_DEVID_OFFS) -+ -+ -+/* PCI Express Capability List Pointer Register*/ -+/*PEX_CAPABILTY_LIST_POINTER (PXCLP)*/ -+ -+#define PXCLP_CAPPTR_OFFS 0 /* Capability List Pointer */ -+#define PXCLP_CAPPTR_MASK (0xff << PXCLP_CAPPTR_OFFS) -+ -+/* PCI Express Interrupt Pin and Line Register */ -+/*PEX_INTERRUPT_PIN_AND_LINE (PXIPAL)*/ -+ -+#define PXIPAL_INTLINE_OFFS 0 /* Interrupt line (IRQ) */ -+#define PXIPAL_INTLINE_MASK (0xff << PXIPAL_INTLINE_OFFS) -+ -+#define PXIPAL_INTPIN_OFFS 8 /* interrupt pin (A,B,C,D) */ -+#define PXIPAL_INTPIN_MASK (0xff << PXIPAL_INTPIN_OFFS) -+ -+ -+/* PCI Express Power Management Capability Header Register*/ -+/*PEX_POWER_MNG_CAPABILITY (PXPMC)*/ -+ -+#define PXPMC_CAP_ID_OFFS 0 /* Capability ID */ -+#define PXPMC_CAP_ID_MASK (0xff << PXPMC_CAP_ID_OFFS) -+ -+#define PXPMC_NEXT_PTR_OFFS 8 /* Next Item Pointer */ -+#define PXPMC_NEXT_PTR_MASK (0xff << PXPMC_NEXT_PTR_OFFS) -+ -+#define PXPMC_PMC_VER_OFFS 16 /* PCI Power Management Capability Version*/ -+#define PXPMC_PMC_VER_MASK (0x7 << PXPMC_PMC_VER_OFFS) -+ -+#define PXPMC_DSI BIT21/* Device Specific Initialization */ -+ -+#define PXPMC_AUX_CUR_OFFS 22 /* Auxiliary Current Requirements */ -+#define PXPMC_AUX_CUR_MASK (0x7 << PXPMC_AUX_CUR_OFFS) -+ -+#define PXPMC_D1_SUP BIT25 /* D1 Power Management support*/ -+ -+#define PXPMC_D2_SUP BIT26 /* D2 Power Management support*/ -+ -+#define PXPMC_PME_SUP_OFFS 27 /* PM Event generation support*/ -+#define PXPMC_PME_SUP_MASK (0x1f << PXPMC_PME_SUP_OFFS) -+ -+/* PCI Express Power Management Control and Status Register*/ -+/*PEX_POWER_MNG_STATUS_CONTROL (PXPMSC)*/ -+ -+#define PXPMSC_PM_STATE_OFFS 0 /* Power State */ -+#define PXPMSC_PM_STATE_MASK (0x3 << PXPMSC_PM_STATE_OFFS) -+#define PXPMSC_PM_STATE_D0 (0x0 << PXPMSC_PM_STATE_OFFS) -+#define PXPMSC_PM_STATE_D1 (0x1 << PXPMSC_PM_STATE_OFFS) -+#define PXPMSC_PM_STATE_D2 (0x2 << PXPMSC_PM_STATE_OFFS) -+#define PXPMSC_PM_STATE_D3 (0x3 << PXPMSC_PM_STATE_OFFS) -+ -+#define PXPMSC_PME_EN BIT8/* PM_PME Message Generation Enable */ -+ -+#define PXPMSC_PM_DATA_SEL_OFFS 9 /* Data Select*/ -+#define PXPMSC_PM_DATA_SEL_MASK (0xf << PXPMSC_PM_DATA_SEL_OFFS) -+ -+#define PXPMSC_PM_DATA_SCALE_OFFS 13 /* Data Scale */ -+#define PXPMSC_PM_DATA_SCALE_MASK (0x3 << PXPMSC_PM_DATA_SCALE_OFFS) -+ -+#define PXPMSC_PME_STAT BIT15/* PME Status */ -+ -+#define PXPMSC_PM_DATA_OFFS 24 /* State Data */ -+#define PXPMSC_PM_DATA_MASK (0xff << PXPMSC_PM_DATA_OFFS) -+ -+ -+/* PCI Express MSI Message Control Register*/ -+/*PEX_MSI_MESSAGE_CONTROL (PXMMC)*/ -+ -+#define PXMMC_CAP_ID_OFFS 0 /* Capability ID */ -+#define PXMMC_CAP_ID_MASK (0xff << PXMMC_CAP_ID_OFFS) -+ -+#define PXMMC_NEXT_PTR_OFFS 8 /* Next Item Pointer */ -+#define PXMMC_NEXT_PTR_MASK (0xff << PXMMC_NEXT_PTR_OFFS) -+ -+#define PXMMC_MSI_EN BIT18 /* MSI Enable */ -+ -+#define PXMMC_MULTI_CAP_OFFS 17 /* Multiple Message Capable */ -+#define PXMMC_MULTI_CAP_MASK (0x7 << PXMMC_MULTI_CAP_OFFS) -+ -+#define PXMMC_MULTI_EN_OFFS 20 /* Multiple Messages Enable */ -+#define PXMMC_MULTI_EN_MASK (0x7 << PXMMC_MULTI_EN_OFFS) -+ -+#define PXMMC_ADDR64 BIT23 /* 64-bit Addressing Capable */ -+ -+ -+/* PCI Express MSI Message Address Register*/ -+/*PEX_MSI_MESSAGE_ADDR (PXMMA)*/ -+ -+#define PXMMA_MSI_ADDR_OFFS 2 /* Message Address corresponds to -+ Address[31:2] of the MSI MWr TLP*/ -+#define PXMMA_MSI_ADDR_MASK (0x3fffffff << PXMMA_MSI_ADDR_OFFS) -+ -+ -+/* PCI Express MSI Message Address (High) Register */ -+/*PEX_MSI_MESSAGE_HIGH_ADDR (PXMMHA)*/ -+ -+#define PXMMA_MSI_ADDR_H_OFFS 0 /* Message Upper Address corresponds to -+ Address[63:32] of the MSI MWr TLP*/ -+#define PXMMA_MSI_ADDR_H_MASK (0xffffffff << PXMMA_MSI_ADDR_H_OFFS ) -+ -+ -+/* PCI Express MSI Message Data Register*/ -+/*PEX_MSI_MESSAGE_DATA (PXMMD)*/ -+ -+#define PXMMD_MSI_DATA_OFFS 0 /* Message Data */ -+#define PXMMD_MSI_DATA_MASK (0xffff << PXMMD_MSI_DATA_OFFS ) -+ -+ -+/* PCI Express Capability Register*/ -+/*PEX_CAPABILITY_REG (PXCR)*/ -+ -+#define PXCR_CAP_ID_OFFS 0 /* Capability ID*/ -+#define PXCR_CAP_ID_MASK (0xff << PXCR_CAP_ID_OFFS) -+ -+#define PXCR_NEXT_PTR_OFFS 8 /* Next Item Pointer*/ -+#define PXCR_NEXT_PTR_MASK (0xff << PXCR_NEXT_PTR_OFFS) -+ -+#define PXCR_CAP_VER_OFFS 16 /* Capability Version*/ -+#define PXCR_CAP_VER_MASK (0xf << PXCR_CAP_VER_OFFS) -+ -+#define PXCR_DEV_TYPE_OFFS 20 /* Device/Port Type*/ -+#define PXCR_DEV_TYPE_MASK (0xf << PXCR_DEV_TYPE_OFFS) -+ -+#define PXCR_SLOT_IMP BIT24 /* Slot Implemented*/ -+ -+#define PXCR_INT_MSG_NUM_OFFS 25 /* Interrupt Message Number*/ -+#define PXCR_INT_MSG_NUM_MASK (0x1f << PXCR_INT_MSG_NUM_OFFS) -+ -+ -+/* PCI Express Device Capabilities Register */ -+/*PEX_DEV_CAPABILITY_REG (PXDCR)*/ -+ -+#define PXDCR_MAX_PLD_SIZE_SUP_OFFS 0 /* Maximum Payload Size Supported*/ -+#define PXDCR_MAX_PLD_SIZE_SUP_MASK (0x7 << PXDCR_MAX_PLD_SIZE_SUP_OFFS) -+ -+#define PXDCR_EP_L0S_ACC_LAT_OFFS 6/* Endpoint L0s Acceptable Latency*/ -+#define PXDCR_EP_L0S_ACC_LAT_MASK (0x7 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+#define PXDCR_EP_L0S_ACC_LAT_64NS_LESS (0x0 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+#define PXDCR_EP_L0S_ACC_LAT_64NS_128NS (0x1 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+#define PXDCR_EP_L0S_ACC_LAT_128NS_256NS (0x2 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+#define PXDCR_EP_L0S_ACC_LAT_256NS_512NS (0x3 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+#define PXDCR_EP_L0S_ACC_LAT_512NS_1US (0x4 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+#define PXDCR_EP_L0S_ACC_LAT_1US_2US (0x5 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+#define PXDCR_EP_L0S_ACC_LAT_2US_4US (0x6 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+#define PXDCR_EP_L0S_ACC_LAT_4US_MORE (0x7 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+ -+#define PXDCR_EP_L1_ACC_LAT_OFFS 9 /* Endpoint L1 Acceptable Latency*/ -+#define PXDCR_EP_L1_ACC_LAT_MASK (0x7 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXDCR_EP_L1_ACC_LAT_64NS_LESS (0x0 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXDCR_EP_L1_ACC_LAT_64NS_128NS (0x1 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXDCR_EP_L1_ACC_LAT_128NS_256NS (0x2 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXDCR_EP_L1_ACC_LAT_256NS_512NS (0x3 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXDCR_EP_L1_ACC_LAT_512NS_1US (0x4 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXDCR_EP_L1_ACC_LAT_1US_2US (0x5 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXDCR_EP_L1_ACC_LAT_2US_4US (0x6 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXDCR_EP_L1_ACC_LAT_4US_MORE (0x7 << PXDCR_EP_L1_ACC_LAT_OFFS) -+ -+ -+#define PXDCR_ATT_BUT_PRS_OFFS 12 /* Attention Button Present*/ -+#define PXDCR_ATT_BUT_PRS_MASK BIT12 -+#define PXDCR_ATT_BUT_PRS_IMPLEMENTED BIT12 -+ -+#define PXDCR_ATT_IND_PRS_OFFS 13 /* Attention Indicator Present*/ -+#define PXDCR_ATT_IND_PRS_MASK BIT13 -+#define PXDCR_ATT_IND_PRS_IMPLEMENTED BIT13 -+ -+#define PXDCR_PWR_IND_PRS_OFFS 14/* Power Indicator Present*/ -+#define PXDCR_PWR_IND_PRS_MASK BIT14 -+#define PXDCR_PWR_IND_PRS_IMPLEMENTED BIT14 -+ -+#define PXDCR_CAP_SPL_VAL_OFFS 18 /*Captured Slot Power Limit -+ Value*/ -+#define PXDCR_CAP_SPL_VAL_MASK (0xff << PXDCR_CAP_SPL_VAL_OFFS) -+ -+#define PXDCR_CAP_SP_LSCL_OFFS 26 /* Captured Slot Power Limit -+ Scale */ -+#define PXDCR_CAP_SP_LSCL_MASK (0x3 << PXDCR_CAP_SP_LSCL_OFFS) -+ -+/* PCI Express Device Control Status Register */ -+/*PEX_DEV_CTRL_STAT_REG (PXDCSR)*/ -+ -+#define PXDCSR_COR_ERR_REP_EN BIT0 /* Correctable Error Reporting Enable*/ -+#define PXDCSR_NF_ERR_REP_EN BIT1 /* Non-Fatal Error Reporting Enable*/ -+#define PXDCSR_F_ERR_REP_EN BIT2 /* Fatal Error Reporting Enable*/ -+#define PXDCSR_UR_REP_EN BIT3 /* Unsupported Request (UR) -+ Reporting Enable*/ -+#define PXDCSR_EN_RO BIT4 /* Enable Relaxed Ordering*/ -+ -+#define PXDCSR_MAX_PLD_SZ_OFFS 5 /* Maximum Payload Size*/ -+#define PXDCSR_MAX_PLD_SZ_MASK (0x7 << PXDCSR_MAX_PLD_SZ_OFFS) -+#define PXDCSR_MAX_PLD_SZ_128B (0x0 << PXDCSR_MAX_PLD_SZ_OFFS) -+#define PXDCSR_EN_NS BIT11 /* Enable No Snoop*/ -+ -+#define PXDCSR_MAX_RD_RQ_SZ_OFFS 12 /* Maximum Read Request Size*/ -+#define PXDCSR_MAX_RD_RQ_SZ_MASK (0x7 << PXDCSR_MAX_RD_RQ_SZ_OFFS) -+#define PXDCSR_MAX_RD_RQ_SZ_128B (0x0 << PXDCSR_MAX_RD_RQ_SZ_OFFS) -+#define PXDCSR_MAX_RD_RQ_SZ_256B (0x1 << PXDCSR_MAX_RD_RQ_SZ_OFFS) -+#define PXDCSR_MAX_RD_RQ_SZ_512B (0x2 << PXDCSR_MAX_RD_RQ_SZ_OFFS) -+#define PXDCSR_MAX_RD_RQ_SZ_1KB (0x3 << PXDCSR_MAX_RD_RQ_SZ_OFFS) -+#define PXDCSR_MAX_RD_RQ_SZ_2KB (0x4 << PXDCSR_MAX_RD_RQ_SZ_OFFS) -+#define PXDCSR_MAX_RD_RQ_SZ_4KB (0x5 << PXDCSR_MAX_RD_RQ_SZ_OFFS) -+ -+#define PXDCSR_COR_ERR_DET BIT16 /* Correctable Error Detected*/ -+#define PXDCSR_NF_ERR_DET BIT17 /* Non-Fatal Error Detected.*/ -+#define PXDCSR_F_ERR_DET BIT18 /* Fatal Error Detected.*/ -+#define PXDCSR_UR_DET BIT19 /* Unsupported Request Detected */ -+#define PXDCSR_AUX_PWR_DET BIT20 /* Reserved*/ -+ -+#define PXDCSR_TRANS_PEND_OFFS 21 /* Transactions Pending*/ -+#define PXDCSR_TRANS_PEND_MASK BIT21 -+#define PXDCSR_TRANS_PEND_NOT_COMPLETED (0x1 << PXDCSR_TRANS_PEND_OFFS) -+ -+ -+/* PCI Express Link Capabilities Register*/ -+/*PEX_LINK_CAPABILITY_REG (PXLCR)*/ -+ -+#define PXLCR_MAX_LINK_SPD_OFFS 0 /* Maximum Link Speed*/ -+#define PXLCR_MAX_LINK_SPD_MASK (0xf << PXLCR_MAX_LINK_SPD_OFFS) -+ -+#define PXLCR_MAX_LNK_WDTH_OFFS 3 /* Maximum Link Width*/ -+#define PXLCR_MAX_LNK_WDTH_MASK (0x3f << PXLCR_MAX_LNK_WDTH_OFFS) -+ -+#define PXLCR_ASPM_SUP_OFFS 10 /* Active State Link PM Support*/ -+#define PXLCR_ASPM_SUP_MASK (0x3 << PXLCR_ASPM_SUP_OFFS) -+ -+#define PXLCR_L0S_EXT_LAT_OFFS 12 /* L0s Exit Latency*/ -+#define PXLCR_L0S_EXT_LAT_MASK (0x7 << PXLCR_L0S_EXT_LAT_OFFS) -+#define PXLCR_L0S_EXT_LAT_64NS_LESS (0x0 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXLCR_L0S_EXT_LAT_64NS_128NS (0x1 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXLCR_L0S_EXT_LAT_128NS_256NS (0x2 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXLCR_L0S_EXT_LAT_256NS_512NS (0x3 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXLCR_L0S_EXT_LAT_512NS_1US (0x4 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXLCR_L0S_EXT_LAT_1US_2US (0x5 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXLCR_L0S_EXT_LAT_2US_4US (0x6 << PXDCR_EP_L1_ACC_LAT_OFFS) -+ -+#define PXLCR_POR_TNUM_OFFS 24 /* Port Number */ -+#define PXLCR_POR_TNUM_MASK (0xff << PXLCR_POR_TNUM_OFFS) -+ -+/* PCI Express Link Control Status Register */ -+/*PEX_LINK_CTRL_STAT_REG (PXLCSR)*/ -+ -+#define PXLCSR_ASPM_CNT_OFFS 0 /* Active State Link PM Control */ -+#define PXLCSR_ASPM_CNT_MASK (0x3 << PXLCSR_ASPM_CNT_OFFS) -+#define PXLCSR_ASPM_CNT_DISABLED (0x0 << PXLCSR_ASPM_CNT_OFFS) -+#define PXLCSR_ASPM_CNT_L0S_ENT_SUPP (0x1 << PXLCSR_ASPM_CNT_OFFS) -+#define PXLCSR_ASPM_CNT_L1S_ENT_SUPP (0x2 << PXLCSR_ASPM_CNT_OFFS) -+#define PXLCSR_ASPM_CNT_L0S_L1S_ENT_SUPP (0x3 << PXLCSR_ASPM_CNT_OFFS) -+ -+#define PXLCSR_RCB_OFFS 3 /* Read Completion Boundary */ -+#define PXLCSR_RCB_MASK BIT3 -+#define PXLCSR_RCB_64B (0 << PXLCSR_RCB_OFFS) -+#define PXLCSR_RCB_128B (1 << PXLCSR_RCB_OFFS) -+ -+#define PXLCSR_LNK_DIS BIT4 /* Link Disable */ -+#define PXLCSR_RETRN_LNK BIT5 /* Retrain Link */ -+#define PXLCSR_CMN_CLK_CFG BIT6 /* Common Clock Configuration */ -+#define PXLCSR_EXTD_SNC BIT7 /* Extended Sync */ -+ -+#define PXLCSR_LNK_SPD_OFFS 16 /* Link Speed */ -+#define PXLCSR_LNK_SPD_MASK (0xf << PXLCSR_LNK_SPD_OFFS) -+ -+#define PXLCSR_NEG_LNK_WDTH_OFFS 20 /* Negotiated Link Width */ -+#define PXLCSR_NEG_LNK_WDTH_MASK (0x3f << PXLCSR_NEG_LNK_WDTH_OFFS) -+#define PXLCSR_NEG_LNK_WDTH_X1 (0x1 << PXLCSR_NEG_LNK_WDTH_OFFS) -+ -+#define PXLCSR_LNK_TRN BIT27 /* Link Training */ -+ -+#define PXLCSR_SLT_CLK_CFG_OFFS 28 /* Slot Clock Configuration */ -+#define PXLCSR_SLT_CLK_CFG_MASK BIT28 -+#define PXLCSR_SLT_CLK_CFG_INDPNT (0x0 << PXLCSR_SLT_CLK_CFG_OFFS) -+#define PXLCSR_SLT_CLK_CFG_REF (0x1 << PXLCSR_SLT_CLK_CFG_OFFS) -+ -+/* PCI Express Advanced Error Report Header Register */ -+/*PEX_ADV_ERR_RPRT_HDR_TRGT_REG (PXAERHTR)*/ -+ -+/* PCI Express Uncorrectable Error Status Register*/ -+/*PEX_UNCORRECT_ERR_STAT_REG (PXUESR)*/ -+ -+/* PCI Express Uncorrectable Error Mask Register */ -+/*PEX_UNCORRECT_ERR_MASK_REG (PXUEMR)*/ -+ -+/* PCI Express Uncorrectable Error Severity Register */ -+/*PEX_UNCORRECT_ERR_SERVITY_REG (PXUESR)*/ -+ -+/* PCI Express Correctable Error Status Register */ -+/*PEX_CORRECT_ERR_STAT_REG (PXCESR)*/ -+ -+/* PCI Express Correctable Error Mask Register */ -+/*PEX_CORRECT_ERR_MASK_REG (PXCEMR)*/ -+ -+/* PCI Express Advanced Error Capability and Control Register*/ -+/*PEX_ADV_ERR_CAPABILITY_CTRL_REG (PXAECCR)*/ -+ -+/* PCI Express Header Log First DWORD Register*/ -+/*PEX_HDR_LOG_FIRST_DWORD_REG (PXHLFDR)*/ -+ -+/* PCI Express Header Log Second DWORD Register*/ -+/*PEX_HDR_LOG_SECOND_DWORD_REG (PXHLSDR)*/ -+ -+/* PCI Express Header Log Third DWORD Register*/ -+/*PEX_HDR_LOG_THIRD_DWORD_REG (PXHLTDR)*/ -+ -+/* PCI Express Header Log Fourth DWORD Register*/ -+/*PEX_HDR_LOG_FOURTH_DWORD_REG (PXHLFDR)*/ -+ -+#ifdef __cplusplus -+} -+#endif /* __cplusplus */ -+ -+#endif /* #ifndef __INCPEXREGSH */ -+ -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,313 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "mvPex.h" -+ -+//#define MV_DEBUG -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+/* locals */ -+typedef struct -+{ -+ MV_U32 data; -+ MV_U32 mask; -+}PEX_HEADER_DATA; -+ -+/* local function forwad decleration */ -+MV_U32 mvPexHwConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, -+ MV_U32 regOff); -+MV_STATUS mvPexHwConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data); -+void resetPexConfig(MV_U32 pexIf, MV_U32 bus, MV_U32 dev); -+ -+ -+PEX_HEADER_DATA configHdr[16] = -+{ -+{0x888811ab, 0x00000000}, /*[device ID, vendor ID] */ -+{0x00100007, 0x0000ffff}, /*[status register, command register] */ -+{0x0604000e, 0x00000000}, /*[programming interface, sub class code, class code, revision ID] */ -+{0x00010008, 0x00000000}, /*[BIST, header type, latency time, cache line] */ -+{0x00000000, 0x00000000}, /*[base address 0] */ -+{0x00000000, 0x00000000}, /*[base address 1] */ -+{0x00000000, 0x00ffffff}, /*[secondary latency timersubordinate bus number, secondary bus number, primary bus number] */ -+{0x0000f101, 0x00000000}, /*[secondary status ,IO limit, IO base] */ -+{0x9ff0a000, 0x00000000}, /*[memory limit, memory base] */ -+{0x0001fff1, 0x00000000}, /*[prefetch memory limit, prefetch memory base] */ -+{0xffffffff, 0x00000000}, /*[prefetch memory base upper] */ -+{0x00000000, 0x00000000}, /*[prefetch memory limit upper] */ -+{0xeffff000, 0x00000000}, /*[IO limit upper 16 bits, IO base upper 16 bits] */ -+{0x00000000, 0x00000000}, /*[reserved, capability pointer] */ -+{0x00000000, 0x00000000}, /*[expansion ROM base address] */ -+{0x00000000, 0x000000FF}, /*[bridge control, interrupt pin, interrupt line] */ -+}; -+ -+ -+#define HEADER_WRITE(data, offset) configHdr[offset/4].data = ((configHdr[offset/4].data & ~configHdr[offset/4].mask) | \ -+ (data & configHdr[offset/4].mask)) -+#define HEADER_READ(offset) configHdr[offset/4].data -+ -+/******************************************************************************* -+* mvVrtBrgPexInit - Initialize PEX interfaces -+* -+* DESCRIPTION: -+* -+* This function is responsible of intialization of the Pex Interface , It -+* configure the Pex Bars and Windows in the following manner: -+* -+* Assumptions : -+* Bar0 is always internal registers bar -+* Bar1 is always the DRAM bar -+* Bar2 is always the Device bar -+* -+* 1) Sets the Internal registers bar base by obtaining the base from -+* the CPU Interface -+* 2) Sets the DRAM bar base and size by getting the base and size from -+* the CPU Interface when the size is the sum of all enabled DRAM -+* chip selects and the base is the base of CS0 . -+* 3) Sets the Device bar base and size by getting these values from the -+* CPU Interface when the base is the base of the lowest base of the -+* Device chip selects, and the -+* -+* -+* INPUT: -+* -+* pexIf - PEX interface number. -+* -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK if function success otherwise MV_ERROR or MV_BAD_PARAM -+* -+*******************************************************************************/ -+MV_STATUS mvPexVrtBrgInit(MV_U32 pexIf) -+{ -+ /* reset PEX tree to recover previous U-boot/Boot configurations */ -+ MV_U32 localBus = mvPexLocalBusNumGet(pexIf); -+ -+ -+ resetPexConfig(pexIf, localBus, 1); -+ return MV_OK; -+} -+ -+ -+MV_U32 mvPexVrtBrgConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, -+ MV_U32 regOff) -+{ -+ -+ MV_U32 localBus = mvPexLocalBusNumGet(pexIf); -+ MV_U32 localDev = mvPexLocalDevNumGet(pexIf); -+ MV_U32 val; -+ if(bus == localBus) -+ { -+ if(dev > 1) -+ { -+/* on the local device allow only device #0 & #1 */ -+ return 0xffffffff; -+ } -+ else -+ if (dev == localDev) -+ { -+ /* read the memory controller registers */ -+ return mvPexHwConfigRead (pexIf, bus, dev, func, regOff); -+ } -+ else -+ { -+ /* access the virtual brg header */ -+ return HEADER_READ(regOff); -+ } -+ } -+ else -+ if(bus == (localBus + 1)) -+ { -+ /* access the device behind the virtual bridge */ -+ if((dev == localDev) || (dev > 1)) -+ { -+ return 0xffffffff; -+ } -+ else -+ { -+ /* access the device behind the virtual bridge, in this case -+ * change the bus number to the local bus number in order to -+ * generate type 0 config cycle -+ */ -+ mvPexLocalBusNumSet(pexIf, bus); -+ mvPexLocalDevNumSet(pexIf, 1); -+ val = mvPexHwConfigRead (pexIf, bus, 0, func, regOff); -+ mvPexLocalBusNumSet(pexIf, localBus); -+ mvPexLocalDevNumSet(pexIf, localDev); -+ return val; -+ } -+ } -+ /* for all other devices use the HW function to get the -+ * requested registers -+ */ -+ mvPexLocalDevNumSet(pexIf, 1); -+ val = mvPexHwConfigRead (pexIf, bus, dev, func, regOff); -+ mvPexLocalDevNumSet(pexIf, localDev); -+ return val; -+} -+ -+ -+MV_STATUS mvPexVrtBrgConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data) -+{ -+ MV_U32 localBus = mvPexLocalBusNumGet(pexIf); -+ MV_U32 localDev = mvPexLocalDevNumGet(pexIf); -+ MV_STATUS status; -+ -+ if(bus == localBus) -+ { -+ if(dev > 1) -+ { -+ /* on the local device allow only device #0 & #1 */ -+ return MV_ERROR; -+ } -+ else -+ if (dev == localDev) -+ { -+ /* read the memory controller registers */ -+ return mvPexHwConfigWrite (pexIf, bus, dev, func, regOff, data); -+ } -+ else -+ { -+ /* access the virtual brg header */ -+ HEADER_WRITE(data, regOff); -+ return MV_OK; -+ } -+ } -+ else -+ if(bus == (localBus + 1)) -+ { -+ /* access the device behind the virtual bridge */ -+ if((dev == localDev) || (dev > 1)) -+ { -+ return MV_ERROR; -+ } -+ else -+ { -+ /* access the device behind the virtual bridge, in this case -+ * change the bus number to the local bus number in order to -+ * generate type 0 config cycle -+ */ -+ //return mvPexHwConfigWrite (pexIf, localBus, dev, func, regOff, data); -+ mvPexLocalBusNumSet(pexIf, bus); -+ mvPexLocalDevNumSet(pexIf, 1); -+ status = mvPexHwConfigWrite (pexIf, bus, 0, func, regOff, data); -+ mvPexLocalBusNumSet(pexIf, localBus); -+ mvPexLocalDevNumSet(pexIf, localDev); -+ return status; -+ -+ } -+ } -+ /* for all other devices use the HW function to get the -+ * requested registers -+ */ -+ mvPexLocalDevNumSet(pexIf, 1); -+ status = mvPexHwConfigWrite (pexIf, bus, dev, func, regOff, data); -+ mvPexLocalDevNumSet(pexIf, localDev); -+ return status; -+} -+ -+ -+ -+ -+void resetPexConfig(MV_U32 pexIf, MV_U32 bus, MV_U32 dev) -+{ -+ MV_U32 tData; -+ MV_U32 i; -+ -+ /* restore the PEX configuration to initialization state */ -+ /* in case PEX P2P call recursive and reset config */ -+ tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x0); -+ if(tData != 0xffffffff) -+ { -+ /* agent had been found - check whether P2P */ -+ tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x8); -+ if((tData & 0xffff0000) == 0x06040000) -+ {/* P2P */ -+ /* get the sec bus and the subordinate */ -+ MV_U32 secBus; -+ tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x18); -+ secBus = ((tData >> 8) & 0xff); -+ /* now scan on sec bus */ -+ for(i = 0;i < 0xff;i++) -+ { -+ resetPexConfig(pexIf, secBus, i); -+ } -+ /* now reset this device */ -+ DB(mvOsPrintf("Reset bus %d dev %d\n", bus, dev)); -+ mvPexHwConfigWrite(pexIf, bus, dev, 0x0, 0x18, 0x0); -+ DB(mvOsPrintf("Reset bus %d dev %d\n", bus, dev)); -+ } -+ } -+} -+ -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,82 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCVRTBRGPEXH -+#define __INCVRTBRGPEXH -+ -+ -+/* Global Functions prototypes */ -+/* mvPexInit - Initialize PEX interfaces*/ -+MV_STATUS mvPexVrtBrgInit(MV_U32 pexIf); -+ -+/* mvPexConfigRead - Read from configuration space */ -+MV_U32 mvPexVrtBrgConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func,MV_U32 regOff); -+ -+/* mvPexConfigWrite - Write to configuration space */ -+MV_STATUS mvPexVrtBrgConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data); -+ -+ -+#endif /* #ifndef __INCPEXH */ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.c ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.c 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,1522 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#include "mvOs.h" -+#include "sflash/mvSFlash.h" -+#include "sflash/mvSFlashSpec.h" -+#include "spi/mvSpi.h" -+#include "spi/mvSpiCmnd.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+ -+/*#define MV_DEBUG*/ -+#ifdef MV_DEBUG -+#define DB(x) x -+#else -+#define DB(x) -+#endif -+ -+/* Globals */ -+static MV_SFLASH_DEVICE_PARAMS sflash[] = { -+ /* ST M25P32 SPI flash, 4MB, 64 sectors of 64K each */ -+ { -+ MV_M25P_WREN_CMND_OPCD, -+ MV_M25P_WRDI_CMND_OPCD, -+ MV_M25P_RDID_CMND_OPCD, -+ MV_M25P_RDSR_CMND_OPCD, -+ MV_M25P_WRSR_CMND_OPCD, -+ MV_M25P_READ_CMND_OPCD, -+ MV_M25P_FAST_RD_CMND_OPCD, -+ MV_M25P_PP_CMND_OPCD, -+ MV_M25P_SE_CMND_OPCD, -+ MV_M25P_BE_CMND_OPCD, -+ MV_M25P_RES_CMND_OPCD, -+ MV_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */ -+ MV_M25P32_SECTOR_SIZE, -+ MV_M25P32_SECTOR_NUMBER, -+ MV_M25P_PAGE_SIZE, -+ "ST M25P32", -+ MV_M25PXXX_ST_MANF_ID, -+ MV_M25P32_DEVICE_ID, -+ MV_M25P32_MAX_SPI_FREQ, -+ MV_M25P32_MAX_FAST_SPI_FREQ, -+ MV_M25P32_FAST_READ_DUMMY_BYTES -+ }, -+ /* ST M25P64 SPI flash, 8MB, 128 sectors of 64K each */ -+ { -+ MV_M25P_WREN_CMND_OPCD, -+ MV_M25P_WRDI_CMND_OPCD, -+ MV_M25P_RDID_CMND_OPCD, -+ MV_M25P_RDSR_CMND_OPCD, -+ MV_M25P_WRSR_CMND_OPCD, -+ MV_M25P_READ_CMND_OPCD, -+ MV_M25P_FAST_RD_CMND_OPCD, -+ MV_M25P_PP_CMND_OPCD, -+ MV_M25P_SE_CMND_OPCD, -+ MV_M25P_BE_CMND_OPCD, -+ MV_M25P_RES_CMND_OPCD, -+ MV_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */ -+ MV_M25P64_SECTOR_SIZE, -+ MV_M25P64_SECTOR_NUMBER, -+ MV_M25P_PAGE_SIZE, -+ "ST M25P64", -+ MV_M25PXXX_ST_MANF_ID, -+ MV_M25P64_DEVICE_ID, -+ MV_M25P64_MAX_SPI_FREQ, -+ MV_M25P64_MAX_FAST_SPI_FREQ, -+ MV_M25P64_FAST_READ_DUMMY_BYTES -+ }, -+ /* ST M25P128 SPI flash, 16MB, 64 sectors of 256K each */ -+ { -+ MV_M25P_WREN_CMND_OPCD, -+ MV_M25P_WRDI_CMND_OPCD, -+ MV_M25P_RDID_CMND_OPCD, -+ MV_M25P_RDSR_CMND_OPCD, -+ MV_M25P_WRSR_CMND_OPCD, -+ MV_M25P_READ_CMND_OPCD, -+ MV_M25P_FAST_RD_CMND_OPCD, -+ MV_M25P_PP_CMND_OPCD, -+ MV_M25P_SE_CMND_OPCD, -+ MV_M25P_BE_CMND_OPCD, -+ MV_M25P_RES_CMND_OPCD, -+ MV_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */ -+ MV_M25P128_SECTOR_SIZE, -+ MV_M25P128_SECTOR_NUMBER, -+ MV_M25P_PAGE_SIZE, -+ "ST M25P128", -+ MV_M25PXXX_ST_MANF_ID, -+ MV_M25P128_DEVICE_ID, -+ MV_M25P128_MAX_SPI_FREQ, -+ MV_M25P128_MAX_FAST_SPI_FREQ, -+ MV_M25P128_FAST_READ_DUMMY_BYTES -+ }, -+ /* Macronix MXIC MX25L6405 SPI flash, 8MB, 128 sectors of 64K each */ -+ { -+ MV_MX25L_WREN_CMND_OPCD, -+ MV_MX25L_WRDI_CMND_OPCD, -+ MV_MX25L_RDID_CMND_OPCD, -+ MV_MX25L_RDSR_CMND_OPCD, -+ MV_MX25L_WRSR_CMND_OPCD, -+ MV_MX25L_READ_CMND_OPCD, -+ MV_MX25L_FAST_RD_CMND_OPCD, -+ MV_MX25L_PP_CMND_OPCD, -+ MV_MX25L_SE_CMND_OPCD, -+ MV_MX25L_BE_CMND_OPCD, -+ MV_MX25L_RES_CMND_OPCD, -+ MV_MX25L_DP_CMND_OPCD, -+ MV_MX25L6405_SECTOR_SIZE, -+ MV_MX25L6405_SECTOR_NUMBER, -+ MV_MXIC_PAGE_SIZE, -+ "MXIC MX25L6405", -+ MV_MXIC_MANF_ID, -+ MV_MX25L6405_DEVICE_ID, -+ MV_MX25L6405_MAX_SPI_FREQ, -+ MV_MX25L6405_MAX_FAST_SPI_FREQ, -+ MV_MX25L6405_FAST_READ_DUMMY_BYTES -+ }, -+ /* SPANSION S25FL128P SPI flash, 16MB, 64 sectors of 256K each */ -+ { -+ MV_S25FL_WREN_CMND_OPCD, -+ MV_S25FL_WRDI_CMND_OPCD, -+ MV_S25FL_RDID_CMND_OPCD, -+ MV_S25FL_RDSR_CMND_OPCD, -+ MV_S25FL_WRSR_CMND_OPCD, -+ MV_S25FL_READ_CMND_OPCD, -+ MV_S25FL_FAST_RD_CMND_OPCD, -+ MV_S25FL_PP_CMND_OPCD, -+ MV_S25FL_SE_CMND_OPCD, -+ MV_S25FL_BE_CMND_OPCD, -+ MV_S25FL_RES_CMND_OPCD, -+ MV_S25FL_DP_CMND_OPCD, -+ MV_S25FL128_SECTOR_SIZE, -+ MV_S25FL128_SECTOR_NUMBER, -+ MV_S25FL_PAGE_SIZE, -+ "SPANSION S25FL128", -+ MV_SPANSION_MANF_ID, -+ MV_S25FL128_DEVICE_ID, -+ MV_S25FL128_MAX_SPI_FREQ, -+ MV_M25P128_MAX_FAST_SPI_FREQ, -+ MV_M25P128_FAST_READ_DUMMY_BYTES -+ } -+}; -+ -+/* Static Functions */ -+static MV_STATUS mvWriteEnable (MV_SFLASH_INFO * pFlinfo); -+static MV_STATUS mvStatusRegGet (MV_SFLASH_INFO * pFlinfo, MV_U8 * pStatReg); -+static MV_STATUS mvStatusRegSet (MV_SFLASH_INFO * pFlinfo, MV_U8 sr); -+static MV_STATUS mvWaitOnWipClear(MV_SFLASH_INFO * pFlinfo); -+static MV_STATUS mvSFlashPageWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, \ -+ MV_U8* pPageBuff, MV_U32 buffSize); -+static MV_STATUS mvSFlashWithDefaultsIdGet (MV_SFLASH_INFO * pFlinfo, \ -+ MV_U8* manId, MV_U16* devId); -+ -+/******************************************************************************* -+* mvWriteEnable - serialize the write enable sequence -+* -+* DESCRIPTION: -+* transmit the sequence for write enable -+* -+********************************************************************************/ -+static MV_STATUS mvWriteEnable(MV_SFLASH_INFO * pFlinfo) -+{ -+ MV_U8 cmd[MV_SFLASH_WREN_CMND_LENGTH]; -+ -+ -+ cmd[0] = sflash[pFlinfo->index].opcdWREN; -+ -+ return mvSpiWriteThenRead(cmd, MV_SFLASH_WREN_CMND_LENGTH, NULL, 0, 0); -+} -+ -+/******************************************************************************* -+* mvStatusRegGet - Retrieve the value of the status register -+* -+* DESCRIPTION: -+* perform the RDSR sequence to get the 8bit status register -+* -+********************************************************************************/ -+static MV_STATUS mvStatusRegGet(MV_SFLASH_INFO * pFlinfo, MV_U8 * pStatReg) -+{ -+ MV_STATUS ret; -+ MV_U8 cmd[MV_SFLASH_RDSR_CMND_LENGTH]; -+ MV_U8 sr[MV_SFLASH_RDSR_REPLY_LENGTH]; -+ -+ -+ -+ -+ cmd[0] = sflash[pFlinfo->index].opcdRDSR; -+ -+ if ((ret = mvSpiWriteThenRead(cmd, MV_SFLASH_RDSR_CMND_LENGTH, sr, -+ MV_SFLASH_RDSR_REPLY_LENGTH,0)) != MV_OK) -+ return ret; -+ -+ *pStatReg = sr[0]; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvWaitOnWipClear - Block waiting for the WIP (write in progress) to be cleared -+* -+* DESCRIPTION: -+* Block waiting for the WIP (write in progress) to be cleared -+* -+********************************************************************************/ -+static MV_STATUS mvWaitOnWipClear(MV_SFLASH_INFO * pFlinfo) -+{ -+ MV_STATUS ret; -+ MV_U32 i; -+ MV_U8 stat; -+ -+ for (i=0; iindex].opcdWRSR; -+ cmd[1] = sr; -+ -+ if ((ret = mvSpiWriteThenRead(cmd, MV_SFLASH_WRSR_CMND_LENGTH, NULL, 0, 0)) != MV_OK) -+ return ret; -+ -+ if ((ret = mvWaitOnWipClear(pFlinfo)) != MV_OK) -+ return ret; -+ -+ mvOsDelay(1); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSFlashPageWr - Write up to 256 Bytes in the same page -+* -+* DESCRIPTION: -+* Write a buffer up to the page size in length provided that the whole address -+* range is within the same page (alligned to page bounderies) -+* -+*******************************************************************************/ -+static MV_STATUS mvSFlashPageWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, -+ MV_U8* pPageBuff, MV_U32 buffSize) -+{ -+ MV_STATUS ret; -+ MV_U8 cmd[MV_SFLASH_PP_CMND_LENGTH]; -+ -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invalid parameter device index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* check that we do not cross the page bounderies */ -+ if (((offset & (sflash[pFlinfo->index].pageSize - 1)) + buffSize) > -+ sflash[pFlinfo->index].pageSize) -+ { -+ DB(mvOsPrintf("%s WARNING: Page allignment problem!\n", __FUNCTION__);) -+ return MV_OUT_OF_RANGE; -+ } -+ -+ /* Issue the Write enable command prior the page program command */ -+ if ((ret = mvWriteEnable(pFlinfo)) != MV_OK) -+ return ret; -+ -+ cmd[0] = sflash[pFlinfo->index].opcdPP; -+ cmd[1] = ((offset >> 16) & 0xFF); -+ cmd[2] = ((offset >> 8) & 0xFF); -+ cmd[3] = (offset & 0xFF); -+ -+ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_PP_CMND_LENGTH, pPageBuff, buffSize)) != MV_OK) -+ return ret; -+ -+ if ((ret = mvWaitOnWipClear(pFlinfo)) != MV_OK) -+ return ret; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSFlashWithDefaultsIdGet - Try to read the manufacturer and Device IDs from -+* the device using the default RDID opcode and the default WREN opcode. -+* -+* DESCRIPTION: -+* This is used to detect a generic device that uses the default opcodes -+* for the WREN and RDID. -+* -+********************************************************************************/ -+static MV_STATUS mvSFlashWithDefaultsIdGet (MV_SFLASH_INFO * pFlinfo, MV_U8* manId, MV_U16* devId) -+{ -+ MV_STATUS ret; -+ MV_U8 cmdRDID[MV_SFLASH_RDID_CMND_LENGTH]; -+ MV_U8 id[MV_SFLASH_RDID_REPLY_LENGTH]; -+ -+ -+ -+ /* Use the default RDID opcode to read the IDs */ -+ cmdRDID[0] = MV_SFLASH_DEFAULT_RDID_OPCD; /* unknown model try default */ -+ if ((ret = mvSpiWriteThenRead(cmdRDID, MV_SFLASH_RDID_CMND_LENGTH, id, MV_SFLASH_RDID_REPLY_LENGTH, 0)) != MV_OK) -+ return ret; -+ -+ *manId = id[0]; -+ *devId = 0; -+ *devId |= (id[1] << 8); -+ *devId |= id[2]; -+ -+ return MV_OK; -+} -+ -+/* -+##################################################################################### -+##################################################################################### -+*/ -+ -+/******************************************************************************* -+* mvSFlashInit - Initialize the serial flash device -+* -+* DESCRIPTION: -+* Perform the neccessary initialization and configuration -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* pFlinfo->baseAddr: base address in fast mode. -+* pFlinfo->index: Index of the flash in the sflash tabel. If the SPI -+* flash device does not support read Id command with -+* the standard opcode, then the user should supply this -+* as an input to skip the autodetection process!!!! -+* -+* OUTPUT: -+* pFlinfo: pointer to the Flash information structure after detection -+* pFlinfo->manufacturerId: Manufacturer ID -+* pFlinfo->deviceId: Device ID -+* pFlinfo->sectorSize: size of the sector (all sectors are the same). -+* pFlinfo->sectorNumber: number of sectors. -+* pFlinfo->pageSize: size of the page. -+* pFlinfo->index: Index of the detected flash in the sflash tabel -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashInit (MV_SFLASH_INFO * pFlinfo) -+{ -+ MV_STATUS ret; -+ MV_U8 manf; -+ MV_U16 dev; -+ MV_U32 indx; -+ MV_BOOL detectFlag = MV_FALSE; -+ -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Initialize the SPI interface with low frequency to make sure that the read ID succeeds */ -+ if ((ret = mvSpiInit(MV_SFLASH_BASIC_SPI_FREQ)) != MV_OK) -+ { -+ mvOsPrintf("%s ERROR: Failed to initialize the SPI interface!\n", __FUNCTION__); -+ return ret; -+ } -+ -+ /* First try to read the Manufacturer and Device IDs */ -+ if ((ret = mvSFlashIdGet(pFlinfo, &manf, &dev)) != MV_OK) -+ { -+ mvOsPrintf("%s ERROR: Failed to get the SFlash ID!\n", __FUNCTION__); -+ return ret; -+ } -+ -+ /* loop over the whole table and look for the appropriate SFLASH */ -+ for (indx=0; indxmanufacturerId = manf; -+ pFlinfo->deviceId = dev; -+ pFlinfo->index = indx; -+ detectFlag = MV_TRUE; -+ } -+ } -+ -+ if(!detectFlag) -+ { -+ mvOsPrintf("%s ERROR: Unknown SPI flash device!\n", __FUNCTION__); -+ return MV_FAIL; -+ } -+ -+ /* fill the info based on the model detected */ -+ pFlinfo->sectorSize = sflash[pFlinfo->index].sectorSize; -+ pFlinfo->sectorNumber = sflash[pFlinfo->index].sectorNumber; -+ pFlinfo->pageSize = sflash[pFlinfo->index].pageSize; -+ -+ /* Set the SPI frequency to the MAX allowed for the device for best performance */ -+ if ((ret = mvSpiBaudRateSet(sflash[pFlinfo->index].spiMaxFreq)) != MV_OK) -+ { -+ mvOsPrintf("%s ERROR: Failed to set the SPI frequency!\n", __FUNCTION__); -+ return ret; -+ } -+ -+ /* As default lock the SR */ -+ if ((ret = mvSFlashStatRegLock(pFlinfo, MV_TRUE)) != MV_OK) -+ return ret; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSFlashSectorErase - Erasse a single sector of the serial flash -+* -+* DESCRIPTION: -+* Issue the erase sector command and address -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* secNumber: sector Number to erase (0 -> (sectorNumber-1)) -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashSectorErase (MV_SFLASH_INFO * pFlinfo, MV_U32 secNumber) -+{ -+ MV_STATUS ret; -+ MV_U8 cmd[MV_SFLASH_SE_CMND_LENGTH]; -+ -+ MV_U32 secAddr = (secNumber * pFlinfo->sectorSize); -+#if 0 -+ MV_U32 i; -+ MV_U32 * pW = (MV_U32*) (secAddr + pFlinfo->baseAddr); -+ MV_U32 erasedWord = 0xFFFFFFFF; -+ MV_U32 wordsPerSector = (pFlinfo->sectorSize / sizeof(MV_U32)); -+ MV_BOOL eraseNeeded = MV_FALSE; -+#endif -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* check that the sector number is valid */ -+ if (secNumber >= pFlinfo->sectorNumber) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter sector number!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* we don't want to access SPI in direct mode from in-direct API, -+ becasue of timing issue between CS asserts. */ -+#if 0 -+ /* First compare to FF and check if erase is needed */ -+ for (i=0; iindex].opcdSE; -+ cmd[1] = ((secAddr >> 16) & 0xFF); -+ cmd[2] = ((secAddr >> 8) & 0xFF); -+ cmd[3] = (secAddr & 0xFF); -+ -+ /* Issue the Write enable command prior the sector erase command */ -+ if ((ret = mvWriteEnable(pFlinfo)) != MV_OK) -+ return ret; -+ -+ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_SE_CMND_LENGTH, NULL, 0)) != MV_OK) -+ return ret; -+ -+ if ((ret = mvWaitOnWipClear(pFlinfo)) != MV_OK) -+ return ret; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSFlashChipErase - Erasse the whole serial flash -+* -+* DESCRIPTION: -+* Issue the bulk (chip) erase command -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashChipErase (MV_SFLASH_INFO * pFlinfo) -+{ -+ MV_STATUS ret; -+ MV_U8 cmd[MV_SFLASH_BE_CMND_LENGTH]; -+ -+ -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ cmd[0] = sflash[pFlinfo->index].opcdBE; -+ -+ /* Issue the Write enable command prior the Bulk erase command */ -+ if ((ret = mvWriteEnable(pFlinfo)) != MV_OK) -+ return ret; -+ -+ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_BE_CMND_LENGTH, NULL, 0)) != MV_OK) -+ return ret; -+ -+ if ((ret = mvWaitOnChipEraseDone(pFlinfo)) != MV_OK) -+ return ret; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSFlashBlockRd - Read from the serial flash -+* -+* DESCRIPTION: -+* Issue the read command and address then perfom the needed read -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* offset: byte offset with the flash to start reading from -+* pReadBuff: pointer to the buffer to read the data in -+* buffSize: size of the buffer to read. -+* -+* OUTPUT: -+* pReadBuff: pointer to the buffer containing the read data -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, -+ MV_U8* pReadBuff, MV_U32 buffSize) -+{ -+ MV_U8 cmd[MV_SFLASH_READ_CMND_LENGTH]; -+ -+ -+ /* check for NULL pointer */ -+ if ((pFlinfo == NULL) || (pReadBuff == NULL)) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ cmd[0] = sflash[pFlinfo->index].opcdREAD; -+ cmd[1] = ((offset >> 16) & 0xFF); -+ cmd[2] = ((offset >> 8) & 0xFF); -+ cmd[3] = (offset & 0xFF); -+ -+ return mvSpiWriteThenRead(cmd, MV_SFLASH_READ_CMND_LENGTH, pReadBuff, buffSize, 0); -+} -+ -+/******************************************************************************* -+* mvSFlashFastBlockRd - Fast read from the serial flash -+* -+* DESCRIPTION: -+* Issue the fast read command and address then perfom the needed read -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* offset: byte offset with the flash to start reading from -+* pReadBuff: pointer to the buffer to read the data in -+* buffSize: size of the buffer to read. -+* -+* OUTPUT: -+* pReadBuff: pointer to the buffer containing the read data -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashFastBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, -+ MV_U8* pReadBuff, MV_U32 buffSize) -+{ -+ MV_U8 cmd[MV_SFLASH_READ_CMND_LENGTH]; -+ MV_STATUS ret; -+ -+ /* check for NULL pointer */ -+ if ((pFlinfo == NULL) || (pReadBuff == NULL)) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* Set the SPI frequency to the MAX allowed for fast-read operations */ -+ mvOsPrintf("Setting freq to %d.\n",sflash[pFlinfo->index].spiMaxFastFreq); -+ if ((ret = mvSpiBaudRateSet(sflash[pFlinfo->index].spiMaxFastFreq)) != MV_OK) -+ { -+ mvOsPrintf("%s ERROR: Failed to set the SPI fast frequency!\n", __FUNCTION__); -+ return ret; -+ } -+ -+ cmd[0] = sflash[pFlinfo->index].opcdFSTRD; -+ cmd[1] = ((offset >> 16) & 0xFF); -+ cmd[2] = ((offset >> 8) & 0xFF); -+ cmd[3] = (offset & 0xFF); -+ -+ -+ ret = mvSpiWriteThenRead(cmd, MV_SFLASH_READ_CMND_LENGTH, pReadBuff, buffSize, -+ sflash[pFlinfo->index].spiFastRdDummyBytes); -+ -+ /* Reset the SPI frequency to the MAX allowed for the device for best performance */ -+ if ((ret = mvSpiBaudRateSet(sflash[pFlinfo->index].spiMaxFreq)) != MV_OK) -+ { -+ mvOsPrintf("%s ERROR: Failed to set the SPI frequency!\n", __FUNCTION__); -+ return ret; -+ } -+ -+ return ret; -+} -+ -+ -+/******************************************************************************* -+* mvSFlashBlockWr - Write a buffer with any size -+* -+* DESCRIPTION: -+* write regardless of the page boundaries and size limit per Page -+* program command -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* offset: byte offset within the flash region -+* pWriteBuff: pointer to the buffer holding the data to program -+* buffSize: size of the buffer to write -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashBlockWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, -+ MV_U8* pWriteBuff, MV_U32 buffSize) -+{ -+ MV_STATUS ret; -+ MV_U32 data2write = buffSize; -+ MV_U32 preAllOffset = (offset & MV_SFLASH_PAGE_ALLIGN_MASK(MV_M25P_PAGE_SIZE)); -+ MV_U32 preAllSz = (preAllOffset ? (MV_M25P_PAGE_SIZE - preAllOffset) : 0); -+ MV_U32 writeOffset = offset; -+ -+ /* check for NULL pointer */ -+#ifndef CONFIG_MARVELL -+ if(NULL == pWriteBuff) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+#endif -+ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* check that the buffer size does not exceed the flash size */ -+ if ((offset + buffSize) > mvSFlashSizeGet(pFlinfo)) -+ { -+ DB(mvOsPrintf("%s WARNING: Write exceeds flash size!\n", __FUNCTION__);) -+ return MV_OUT_OF_RANGE; -+ } -+ -+ /* check if the total block size is less than the first chunk remainder */ -+ if (data2write < preAllSz) -+ preAllSz = data2write; -+ -+ /* check if programing does not start at a 64byte alligned offset */ -+ if (preAllSz) -+ { -+ if ((ret = mvSFlashPageWr(pFlinfo, writeOffset, pWriteBuff, preAllSz)) != MV_OK) -+ return ret; -+ -+ /* increment pointers and counters */ -+ writeOffset += preAllSz; -+ data2write -= preAllSz; -+ pWriteBuff += preAllSz; -+ } -+ -+ /* program the data that fits in complete page chunks */ -+ while (data2write >= sflash[pFlinfo->index].pageSize) -+ { -+ if ((ret = mvSFlashPageWr(pFlinfo, writeOffset, pWriteBuff, sflash[pFlinfo->index].pageSize)) != MV_OK) -+ return ret; -+ -+ /* increment pointers and counters */ -+ writeOffset += sflash[pFlinfo->index].pageSize; -+ data2write -= sflash[pFlinfo->index].pageSize; -+ pWriteBuff += sflash[pFlinfo->index].pageSize; -+ } -+ -+ /* program the last partial chunk */ -+ if (data2write) -+ { -+ if ((ret = mvSFlashPageWr(pFlinfo, writeOffset, pWriteBuff, data2write)) != MV_OK) -+ return ret; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSFlashIdGet - Get the manufacturer and device IDs. -+* -+* DESCRIPTION: -+* Get the Manufacturer and device IDs from the serial flash through -+* writing the RDID command then reading 3 bytes of data. In case that -+* this command was called for the first time in order to detect the -+* manufacturer and device IDs, then the default RDID opcode will be used -+* unless the device index is indicated by the user (in case the SPI flash -+* does not use the default RDID opcode). -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* pManId: pointer to the 8bit variable to hold the manufacturing ID -+* pDevId: pointer to the 16bit variable to hold the device ID -+* -+* OUTPUT: -+* pManId: pointer to the 8bit variable holding the manufacturing ID -+* pDevId: pointer to the 16bit variable holding the device ID -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashIdGet (MV_SFLASH_INFO * pFlinfo, MV_U8* pManId, MV_U16* pDevId) -+{ -+ MV_STATUS ret; -+ MV_U8 cmd[MV_SFLASH_RDID_CMND_LENGTH]; -+ MV_U8 id[MV_SFLASH_RDID_REPLY_LENGTH]; -+ -+ -+ -+ /* check for NULL pointer */ -+ if ((pFlinfo == NULL) || (pManId == NULL) || (pDevId == NULL)) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ return mvSFlashWithDefaultsIdGet(pFlinfo, pManId, pDevId); -+ else -+ cmd[0] = sflash[pFlinfo->index].opcdRDID; -+ -+ if ((ret = mvSpiWriteThenRead(cmd, MV_SFLASH_RDID_CMND_LENGTH, id, MV_SFLASH_RDID_REPLY_LENGTH, 0)) != MV_OK) -+ return ret; -+ -+ *pManId = id[0]; -+ *pDevId = 0; -+ *pDevId |= (id[1] << 8); -+ *pDevId |= id[2]; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSFlashWpRegionSet - Set the Write-Protected region -+* -+* DESCRIPTION: -+* Set the Write-Protected region -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* wpRegion: which region will be protected -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashWpRegionSet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION wpRegion) -+{ -+ MV_U8 wpMask; -+ -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the chip is an ST flash; then WP supports only 3 bits */ -+ if (pFlinfo->manufacturerId == MV_M25PXXX_ST_MANF_ID) -+ { -+ switch (wpRegion) -+ { -+ case MV_WP_NONE: -+ wpMask = MV_M25P_STATUS_BP_NONE; -+ break; -+ -+ case MV_WP_UPR_1OF128: -+ DB(mvOsPrintf("%s WARNING: Invaild option for this flash chip!\n", __FUNCTION__);) -+ return MV_NOT_SUPPORTED; -+ -+ case MV_WP_UPR_1OF64: -+ wpMask = MV_M25P_STATUS_BP_1_OF_64; -+ break; -+ -+ case MV_WP_UPR_1OF32: -+ wpMask = MV_M25P_STATUS_BP_1_OF_32; -+ break; -+ -+ case MV_WP_UPR_1OF16: -+ wpMask = MV_M25P_STATUS_BP_1_OF_16; -+ break; -+ -+ case MV_WP_UPR_1OF8: -+ wpMask = MV_M25P_STATUS_BP_1_OF_8; -+ break; -+ -+ case MV_WP_UPR_1OF4: -+ wpMask = MV_M25P_STATUS_BP_1_OF_4; -+ break; -+ -+ case MV_WP_UPR_1OF2: -+ wpMask = MV_M25P_STATUS_BP_1_OF_2; -+ break; -+ -+ case MV_WP_ALL: -+ wpMask = MV_M25P_STATUS_BP_ALL; -+ break; -+ -+ default: -+ DB(mvOsPrintf("%s WARNING: Invaild parameter WP region!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ } -+ /* check if the manufacturer is MXIC then the WP is 4bits */ -+ else if (pFlinfo->manufacturerId == MV_MXIC_MANF_ID) -+ { -+ switch (wpRegion) -+ { -+ case MV_WP_NONE: -+ wpMask = MV_MX25L_STATUS_BP_NONE; -+ break; -+ -+ case MV_WP_UPR_1OF128: -+ wpMask = MV_MX25L_STATUS_BP_1_OF_128; -+ break; -+ -+ case MV_WP_UPR_1OF64: -+ wpMask = MV_MX25L_STATUS_BP_1_OF_64; -+ break; -+ -+ case MV_WP_UPR_1OF32: -+ wpMask = MV_MX25L_STATUS_BP_1_OF_32; -+ break; -+ -+ case MV_WP_UPR_1OF16: -+ wpMask = MV_MX25L_STATUS_BP_1_OF_16; -+ break; -+ -+ case MV_WP_UPR_1OF8: -+ wpMask = MV_MX25L_STATUS_BP_1_OF_8; -+ break; -+ -+ case MV_WP_UPR_1OF4: -+ wpMask = MV_MX25L_STATUS_BP_1_OF_4; -+ break; -+ -+ case MV_WP_UPR_1OF2: -+ wpMask = MV_MX25L_STATUS_BP_1_OF_2; -+ break; -+ -+ case MV_WP_ALL: -+ wpMask = MV_MX25L_STATUS_BP_ALL; -+ break; -+ -+ default: -+ DB(mvOsPrintf("%s WARNING: Invaild parameter WP region!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ } -+ /* check if the manufacturer is SPANSION then the WP is 4bits */ -+ else if (pFlinfo->manufacturerId == MV_SPANSION_MANF_ID) -+ { -+ switch (wpRegion) -+ { -+ case MV_WP_NONE: -+ wpMask = MV_S25FL_STATUS_BP_NONE; -+ break; -+ -+ case MV_WP_UPR_1OF128: -+ DB(mvOsPrintf("%s WARNING: Invaild option for this flash chip!\n", __FUNCTION__);) -+ return MV_NOT_SUPPORTED; -+ -+ case MV_WP_UPR_1OF64: -+ wpMask = MV_S25FL_STATUS_BP_1_OF_64; -+ break; -+ -+ case MV_WP_UPR_1OF32: -+ wpMask = MV_S25FL_STATUS_BP_1_OF_32; -+ break; -+ -+ case MV_WP_UPR_1OF16: -+ wpMask = MV_S25FL_STATUS_BP_1_OF_16; -+ break; -+ -+ case MV_WP_UPR_1OF8: -+ wpMask = MV_S25FL_STATUS_BP_1_OF_8; -+ break; -+ -+ case MV_WP_UPR_1OF4: -+ wpMask = MV_S25FL_STATUS_BP_1_OF_4; -+ break; -+ -+ case MV_WP_UPR_1OF2: -+ wpMask = MV_S25FL_STATUS_BP_1_OF_2; -+ break; -+ -+ case MV_WP_ALL: -+ wpMask = MV_S25FL_STATUS_BP_ALL; -+ break; -+ -+ -+ default: -+ DB(mvOsPrintf("%s WARNING: Invaild parameter WP region!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ } -+ else -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter Manufacturer ID!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* Verify that the SRWD bit is always set - register is s/w locked */ -+ wpMask |= MV_SFLASH_STATUS_REG_SRWD_MASK; -+ -+ return mvStatusRegSet(pFlinfo, wpMask); -+} -+ -+/******************************************************************************* -+* mvSFlashWpRegionGet - Get the Write-Protected region configured -+* -+* DESCRIPTION: -+* Get from the chip the Write-Protected region configured -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* pWpRegion: pointer to the variable to return the WP region in -+* -+* OUTPUT: -+* wpRegion: pointer to the variable holding the WP region configured -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashWpRegionGet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION * pWpRegion) -+{ -+ MV_STATUS ret; -+ MV_U8 reg; -+ -+ /* check for NULL pointer */ -+ if ((pFlinfo == NULL) || (pWpRegion == NULL)) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ if ((ret = mvStatusRegGet(pFlinfo, ®)) != MV_OK) -+ return ret; -+ -+ /* Check if the chip is an ST flash; then WP supports only 3 bits */ -+ if (pFlinfo->manufacturerId == MV_M25PXXX_ST_MANF_ID) -+ { -+ switch ((reg & MV_M25P_STATUS_REG_WP_MASK)) -+ { -+ case MV_M25P_STATUS_BP_NONE: -+ *pWpRegion = MV_WP_NONE; -+ break; -+ -+ case MV_M25P_STATUS_BP_1_OF_64: -+ *pWpRegion = MV_WP_UPR_1OF64; -+ break; -+ -+ case MV_M25P_STATUS_BP_1_OF_32: -+ *pWpRegion = MV_WP_UPR_1OF32; -+ break; -+ -+ case MV_M25P_STATUS_BP_1_OF_16: -+ *pWpRegion = MV_WP_UPR_1OF16; -+ break; -+ -+ case MV_M25P_STATUS_BP_1_OF_8: -+ *pWpRegion = MV_WP_UPR_1OF8; -+ break; -+ -+ case MV_M25P_STATUS_BP_1_OF_4: -+ *pWpRegion = MV_WP_UPR_1OF4; -+ break; -+ -+ case MV_M25P_STATUS_BP_1_OF_2: -+ *pWpRegion = MV_WP_UPR_1OF2; -+ break; -+ -+ case MV_M25P_STATUS_BP_ALL: -+ *pWpRegion = MV_WP_ALL; -+ break; -+ -+ default: -+ DB(mvOsPrintf("%s WARNING: Unidentified WP region in h/w!\n", __FUNCTION__);) -+ return MV_BAD_VALUE; -+ } -+ } -+ /* check if the manufacturer is MXIC then the WP is 4bits */ -+ else if (pFlinfo->manufacturerId == MV_MXIC_MANF_ID) -+ { -+ switch ((reg & MV_MX25L_STATUS_REG_WP_MASK)) -+ { -+ case MV_MX25L_STATUS_BP_NONE: -+ *pWpRegion = MV_WP_NONE; -+ break; -+ -+ case MV_MX25L_STATUS_BP_1_OF_128: -+ *pWpRegion = MV_WP_UPR_1OF128; -+ break; -+ -+ case MV_MX25L_STATUS_BP_1_OF_64: -+ *pWpRegion = MV_WP_UPR_1OF64; -+ break; -+ -+ case MV_MX25L_STATUS_BP_1_OF_32: -+ *pWpRegion = MV_WP_UPR_1OF32; -+ break; -+ -+ case MV_MX25L_STATUS_BP_1_OF_16: -+ *pWpRegion = MV_WP_UPR_1OF16; -+ break; -+ -+ case MV_MX25L_STATUS_BP_1_OF_8: -+ *pWpRegion = MV_WP_UPR_1OF8; -+ break; -+ -+ case MV_MX25L_STATUS_BP_1_OF_4: -+ *pWpRegion = MV_WP_UPR_1OF4; -+ break; -+ -+ case MV_MX25L_STATUS_BP_1_OF_2: -+ *pWpRegion = MV_WP_UPR_1OF2; -+ break; -+ -+ case MV_MX25L_STATUS_BP_ALL: -+ *pWpRegion = MV_WP_ALL; -+ break; -+ -+ default: -+ DB(mvOsPrintf("%s WARNING: Unidentified WP region in h/w!\n", __FUNCTION__);) -+ return MV_BAD_VALUE; -+ } -+ } -+ /* Check if the chip is an SPANSION flash; then WP supports only 3 bits */ -+ else if (pFlinfo->manufacturerId == MV_SPANSION_MANF_ID) -+ { -+ switch ((reg & MV_S25FL_STATUS_REG_WP_MASK)) -+ { -+ case MV_S25FL_STATUS_BP_NONE: -+ *pWpRegion = MV_WP_NONE; -+ break; -+ -+ case MV_S25FL_STATUS_BP_1_OF_64: -+ *pWpRegion = MV_WP_UPR_1OF64; -+ break; -+ -+ case MV_S25FL_STATUS_BP_1_OF_32: -+ *pWpRegion = MV_WP_UPR_1OF32; -+ break; -+ -+ case MV_S25FL_STATUS_BP_1_OF_16: -+ *pWpRegion = MV_WP_UPR_1OF16; -+ break; -+ -+ case MV_S25FL_STATUS_BP_1_OF_8: -+ *pWpRegion = MV_WP_UPR_1OF8; -+ break; -+ -+ case MV_S25FL_STATUS_BP_1_OF_4: -+ *pWpRegion = MV_WP_UPR_1OF4; -+ break; -+ -+ case MV_S25FL_STATUS_BP_1_OF_2: -+ *pWpRegion = MV_WP_UPR_1OF2; -+ break; -+ -+ case MV_S25FL_STATUS_BP_ALL: -+ *pWpRegion = MV_WP_ALL; -+ break; -+ -+ default: -+ DB(mvOsPrintf("%s WARNING: Unidentified WP region in h/w!\n", __FUNCTION__);) -+ return MV_BAD_VALUE; -+ } -+ } -+ else -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter Manufacturer ID!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSFlashStatRegLock - Lock the status register for writing - W/Vpp -+* pin should be low to take effect -+* -+* DESCRIPTION: -+* Lock the access to the Status Register for writing. This will -+* cause the flash to enter the hardware protection mode if the W/Vpp -+* is low. If the W/Vpp is hi, the chip will be in soft protection mode, but -+* the register will continue to be writable if WREN sequence was used. -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* srLock: enable/disable (MV_TRUE/MV_FALSE) status registor lock mechanism -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashStatRegLock (MV_SFLASH_INFO * pFlinfo, MV_BOOL srLock) -+{ -+ MV_STATUS ret; -+ MV_U8 reg; -+ -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ if ((ret = mvStatusRegGet(pFlinfo, ®)) != MV_OK) -+ return ret; -+ -+ if (srLock) -+ reg |= MV_SFLASH_STATUS_REG_SRWD_MASK; -+ else -+ reg &= ~MV_SFLASH_STATUS_REG_SRWD_MASK; -+ -+ return mvStatusRegSet(pFlinfo, reg); -+} -+ -+/******************************************************************************* -+* mvSFlashSizeGet - Get the size of the SPI flash -+* -+* DESCRIPTION: -+* based on the sector number and size of each sector calculate the total -+* size of the flash memory. -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Size of the flash in bytes. -+* -+* -+*******************************************************************************/ -+MV_U32 mvSFlashSizeGet (MV_SFLASH_INFO * pFlinfo) -+{ -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return 0; -+ } -+ -+ return (pFlinfo->sectorSize * pFlinfo->sectorNumber); -+} -+ -+/******************************************************************************* -+* mvSFlashPowerSaveEnter - Cause the falsh device to go into power save mode -+* -+* DESCRIPTION: -+* Enter a special power save mode. -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Size of the flash in bytes. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashPowerSaveEnter(MV_SFLASH_INFO * pFlinfo) -+{ -+ MV_STATUS ret; -+ MV_U8 cmd[MV_SFLASH_DP_CMND_LENGTH]; -+ -+ -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return 0; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* check that power save mode is supported in the specific device */ -+ if (sflash[pFlinfo->index].opcdPwrSave == MV_SFLASH_NO_SPECIFIC_OPCD) -+ { -+ DB(mvOsPrintf("%s WARNING: Power save not supported for this device!\n", __FUNCTION__);) -+ return MV_NOT_SUPPORTED; -+ } -+ -+ cmd[0] = sflash[pFlinfo->index].opcdPwrSave; -+ -+ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_DP_CMND_LENGTH, NULL, 0)) != MV_OK) -+ return ret; -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvSFlashPowerSaveExit - Cause the falsh device to exit the power save mode -+* -+* DESCRIPTION: -+* Exit the deep power save mode. -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Size of the flash in bytes. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashPowerSaveExit (MV_SFLASH_INFO * pFlinfo) -+{ -+ MV_STATUS ret; -+ MV_U8 cmd[MV_SFLASH_RES_CMND_LENGTH]; -+ -+ -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return 0; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* check that power save mode is supported in the specific device */ -+ if (sflash[pFlinfo->index].opcdRES == MV_SFLASH_NO_SPECIFIC_OPCD) -+ { -+ DB(mvOsPrintf("%s WARNING: Read Electronic Signature not supported for this device!\n", __FUNCTION__);) -+ return MV_NOT_SUPPORTED; -+ } -+ -+ cmd[0] = sflash[pFlinfo->index].opcdRES; -+ -+ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_RES_CMND_LENGTH, NULL, 0)) != MV_OK) -+ return ret; -+ -+ /* add the delay needed for the device to wake up */ -+ mvOsDelay(MV_MXIC_DP_EXIT_DELAY); /* 30 ms */ -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvSFlashModelGet - Retreive the string with the device manufacturer and model -+* -+* DESCRIPTION: -+* Retreive the string with the device manufacturer and model -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* pointer to the string indicating the device manufacturer and model -+* -+* -+*******************************************************************************/ -+const MV_8 * mvSFlashModelGet (MV_SFLASH_INFO * pFlinfo) -+{ -+ static const MV_8 * unknModel = (const MV_8 *)"Unknown"; -+ -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return 0; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return unknModel; -+ } -+ -+ return sflash[pFlinfo->index].deviceModel; -+} -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,166 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvSFlashH -+#define __INCmvSFlashH -+ -+#include "mvTypes.h" -+ -+/* MCAROS */ -+#define MV_SFLASH_PAGE_ALLIGN_MASK(pgSz) (pgSz-1) -+#define MV_ARRAY_SIZE(a) ((sizeof(a)) / (sizeof(a[0]))) -+ -+/* Constants */ -+#define MV_INVALID_DEVICE_NUMBER 0xFFFFFFFF -+/* 10 MHz is the minimum possible SPI frequency when tclk is set 200MHz*/ -+#define MV_SFLASH_BASIC_SPI_FREQ 10000000 -+/* enumerations */ -+typedef enum -+{ -+ MV_WP_NONE, /* Unprotect the whole chip */ -+ MV_WP_UPR_1OF128, /* Write protect the upper 1/128 part */ -+ MV_WP_UPR_1OF64, /* Write protect the upper 1/64 part */ -+ MV_WP_UPR_1OF32, /* Write protect the upper 1/32 part */ -+ MV_WP_UPR_1OF16, /* Write protect the upper 1/16 part */ -+ MV_WP_UPR_1OF8, /* Write protect the upper 1/8 part */ -+ MV_WP_UPR_1OF4, /* Write protect the upper 1/4 part */ -+ MV_WP_UPR_1OF2, /* Write protect the upper 1/2 part */ -+ MV_WP_ALL /* Write protect the whole chip */ -+} MV_SFLASH_WP_REGION; -+ -+/* Type Definitions */ -+typedef struct -+{ -+ MV_U8 opcdWREN; /* Write enable opcode */ -+ MV_U8 opcdWRDI; /* Write disable opcode */ -+ MV_U8 opcdRDID; /* Read ID opcode */ -+ MV_U8 opcdRDSR; /* Read Status Register opcode */ -+ MV_U8 opcdWRSR; /* Write Status register opcode */ -+ MV_U8 opcdREAD; /* Read opcode */ -+ MV_U8 opcdFSTRD; /* Fast Read opcode */ -+ MV_U8 opcdPP; /* Page program opcode */ -+ MV_U8 opcdSE; /* Sector erase opcode */ -+ MV_U8 opcdBE; /* Bulk erase opcode */ -+ MV_U8 opcdRES; /* Read electronic signature */ -+ MV_U8 opcdPwrSave; /* Go into power save mode */ -+ MV_U32 sectorSize; /* Size of each sector */ -+ MV_U32 sectorNumber; /* Number of sectors */ -+ MV_U32 pageSize; /* size of each page */ -+ const char * deviceModel; /* string with the device model */ -+ MV_U32 manufacturerId; /* The manufacturer ID */ -+ MV_U32 deviceId; /* Device ID */ -+ MV_U32 spiMaxFreq; /* The MAX frequency that can be used with the device */ -+ MV_U32 spiMaxFastFreq; /* The MAX frequency that can be used with the device for fast reads */ -+ MV_U32 spiFastRdDummyBytes; /* Number of dumy bytes to read before real data when working in fast read mode. */ -+} MV_SFLASH_DEVICE_PARAMS; -+ -+typedef struct -+{ -+ MV_U32 baseAddr; /* Flash Base Address used in fast mode */ -+ MV_U8 manufacturerId; /* Manufacturer ID */ -+ MV_U16 deviceId; /* Device ID */ -+ MV_U32 sectorSize; /* Size of each sector - all the same */ -+ MV_U32 sectorNumber; /* Number of sectors */ -+ MV_U32 pageSize; /* Page size - affect allignment */ -+ MV_U32 index; /* index of the device in the sflash table (internal parameter) */ -+} MV_SFLASH_INFO; -+ -+/* Function Prototypes */ -+/* Init */ -+MV_STATUS mvSFlashInit (MV_SFLASH_INFO * pFlinfo); -+ -+/* erase */ -+MV_STATUS mvSFlashSectorErase (MV_SFLASH_INFO * pFlinfo, MV_U32 secNumber); -+MV_STATUS mvSFlashChipErase (MV_SFLASH_INFO * pFlinfo); -+ -+/* Read */ -+MV_STATUS mvSFlashBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, -+ MV_U8* pReadBuff, MV_U32 buffSize); -+MV_STATUS mvSFlashFastBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, -+ MV_U8* pReadBuff, MV_U32 buffSize); -+ -+/* write regardless of the page boundaries and size limit per Page program command */ -+MV_STATUS mvSFlashBlockWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, -+ MV_U8* pWriteBuff, MV_U32 buffSize); -+/* Get IDs */ -+MV_STATUS mvSFlashIdGet (MV_SFLASH_INFO * pFlinfo, MV_U8* pManId, MV_U16* pDevId); -+ -+/* Set and Get the Write Protection region - if the Status register is not locked */ -+MV_STATUS mvSFlashWpRegionSet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION wpRegion); -+MV_STATUS mvSFlashWpRegionGet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION * pWpRegion); -+ -+/* Lock the status register for writing - W/Vpp pin should be low to take effect */ -+MV_STATUS mvSFlashStatRegLock (MV_SFLASH_INFO * pFlinfo, MV_BOOL srLock); -+ -+/* Get the regions sizes */ -+MV_U32 mvSFlashSizeGet (MV_SFLASH_INFO * pFlinfo); -+ -+/* Cause the falsh device to go into power save mode */ -+MV_STATUS mvSFlashPowerSaveEnter(MV_SFLASH_INFO * pFlinfo); -+MV_STATUS mvSFlashPowerSaveExit (MV_SFLASH_INFO * pFlinfo); -+ -+/* Retreive the string with the device manufacturer and model */ -+const MV_8 * mvSFlashModelGet (MV_SFLASH_INFO * pFlinfo); -+ -+#endif /* __INCmvSFlashH */ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlashSpec.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlashSpec.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlashSpec.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlashSpec.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,233 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvSFlashSpecH -+#define __INCmvSFlashSpecH -+ -+/* Constants */ -+#define MV_SFLASH_READ_CMND_LENGTH 4 /* 1B opcode + 3B address */ -+#define MV_SFLASH_SE_CMND_LENGTH 4 /* 1B opcode + 3B address */ -+#define MV_SFLASH_BE_CMND_LENGTH 1 /* 1B opcode */ -+#define MV_SFLASH_PP_CMND_LENGTH 4 /* 1B opcode + 3B address */ -+#define MV_SFLASH_WREN_CMND_LENGTH 1 /* 1B opcode */ -+#define MV_SFLASH_WRDI_CMND_LENGTH 1 /* 1B opcode */ -+#define MV_SFLASH_RDID_CMND_LENGTH 1 /* 1B opcode */ -+#define MV_SFLASH_RDID_REPLY_LENGTH 3 /* 1B manf ID and 2B device ID */ -+#define MV_SFLASH_RDSR_CMND_LENGTH 1 /* 1B opcode */ -+#define MV_SFLASH_RDSR_REPLY_LENGTH 1 /* 1B status */ -+#define MV_SFLASH_WRSR_CMND_LENGTH 2 /* 1B opcode + 1B status value */ -+#define MV_SFLASH_DP_CMND_LENGTH 1 /* 1B opcode */ -+#define MV_SFLASH_RES_CMND_LENGTH 1 /* 1B opcode */ -+ -+/* Status Register Bit Masks */ -+#define MV_SFLASH_STATUS_REG_WIP_OFFSET 0 /* bit 0; write in progress */ -+#define MV_SFLASH_STATUS_REG_WP_OFFSET 2 /* bit 2-4; write protect option */ -+#define MV_SFLASH_STATUS_REG_SRWD_OFFSET 7 /* bit 7; lock status register write */ -+#define MV_SFLASH_STATUS_REG_WIP_MASK (0x1 << MV_SFLASH_STATUS_REG_WIP_OFFSET) -+#define MV_SFLASH_STATUS_REG_SRWD_MASK (0x1 << MV_SFLASH_STATUS_REG_SRWD_OFFSET) -+ -+#define MV_SFLASH_MAX_WAIT_LOOP 1000000 -+#define MV_SFLASH_CHIP_ERASE_MAX_WAIT_LOOP 0x50000000 -+ -+#define MV_SFLASH_DEFAULT_RDID_OPCD 0x9F /* Default Read ID */ -+#define MV_SFLASH_DEFAULT_WREN_OPCD 0x06 /* Default Write Enable */ -+#define MV_SFLASH_NO_SPECIFIC_OPCD 0x00 -+ -+/********************************/ -+/* ST M25Pxxx Device Specific */ -+/********************************/ -+ -+/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ -+#define MV_M25PXXX_ST_MANF_ID 0x20 -+#define MV_M25P32_DEVICE_ID 0x2016 -+#define MV_M25P32_MAX_SPI_FREQ 20000000 /* 20MHz */ -+#define MV_M25P32_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ -+#define MV_M25P32_FAST_READ_DUMMY_BYTES 1 -+#define MV_M25P64_DEVICE_ID 0x2017 -+#define MV_M25P64_MAX_SPI_FREQ 20000000 /* 20MHz */ -+#define MV_M25P64_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ -+#define MV_M25P64_FAST_READ_DUMMY_BYTES 1 -+#define MV_M25P128_DEVICE_ID 0x2018 -+#define MV_M25P128_MAX_SPI_FREQ 20000000 /* 20MHz */ -+#define MV_M25P128_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ -+#define MV_M25P128_FAST_READ_DUMMY_BYTES 1 -+ -+ -+/* Sector Sizes and population per device model*/ -+#define MV_M25P32_SECTOR_SIZE 0x10000 /* 64K */ -+#define MV_M25P64_SECTOR_SIZE 0x10000 /* 64K */ -+#define MV_M25P128_SECTOR_SIZE 0x40000 /* 256K */ -+#define MV_M25P32_SECTOR_NUMBER 64 -+#define MV_M25P64_SECTOR_NUMBER 128 -+#define MV_M25P128_SECTOR_NUMBER 64 -+#define MV_M25P_PAGE_SIZE 0x100 /* 256 byte */ -+ -+#define MV_M25P_WREN_CMND_OPCD 0x06 /* Write Enable */ -+#define MV_M25P_WRDI_CMND_OPCD 0x04 /* Write Disable */ -+#define MV_M25P_RDID_CMND_OPCD 0x9F /* Read ID */ -+#define MV_M25P_RDSR_CMND_OPCD 0x05 /* Read Status Register */ -+#define MV_M25P_WRSR_CMND_OPCD 0x01 /* Write Status Register */ -+#define MV_M25P_READ_CMND_OPCD 0x03 /* Sequential Read */ -+#define MV_M25P_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ -+#define MV_M25P_PP_CMND_OPCD 0x02 /* Page Program */ -+#define MV_M25P_SE_CMND_OPCD 0xD8 /* Sector Erase */ -+#define MV_M25P_BE_CMND_OPCD 0xC7 /* Bulk Erase */ -+#define MV_M25P_RES_CMND_OPCD 0xAB /* Read Electronic Signature */ -+ -+/* Status Register Write Protect Bit Masks - 3bits */ -+#define MV_M25P_STATUS_REG_WP_MASK (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_M25P_STATUS_BP_NONE (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_M25P_STATUS_BP_1_OF_64 (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_M25P_STATUS_BP_1_OF_32 (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_M25P_STATUS_BP_1_OF_16 (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_M25P_STATUS_BP_1_OF_8 (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_M25P_STATUS_BP_1_OF_4 (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_M25P_STATUS_BP_1_OF_2 (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_M25P_STATUS_BP_ALL (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+ -+/************************************/ -+/* MXIC MX25L6405 Device Specific */ -+/************************************/ -+ -+/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ -+#define MV_MXIC_MANF_ID 0xC2 -+#define MV_MX25L6405_DEVICE_ID 0x2017 -+#define MV_MX25L6405_MAX_SPI_FREQ 20000000 /* 20MHz */ -+#define MV_MX25L6405_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ -+#define MV_MX25L6405_FAST_READ_DUMMY_BYTES 1 -+#define MV_MXIC_DP_EXIT_DELAY 30 /* 30 ms */ -+ -+/* Sector Sizes and population per device model*/ -+#define MV_MX25L6405_SECTOR_SIZE 0x10000 /* 64K */ -+#define MV_MX25L6405_SECTOR_NUMBER 128 -+#define MV_MXIC_PAGE_SIZE 0x100 /* 256 byte */ -+ -+#define MV_MX25L_WREN_CMND_OPCD 0x06 /* Write Enable */ -+#define MV_MX25L_WRDI_CMND_OPCD 0x04 /* Write Disable */ -+#define MV_MX25L_RDID_CMND_OPCD 0x9F /* Read ID */ -+#define MV_MX25L_RDSR_CMND_OPCD 0x05 /* Read Status Register */ -+#define MV_MX25L_WRSR_CMND_OPCD 0x01 /* Write Status Register */ -+#define MV_MX25L_READ_CMND_OPCD 0x03 /* Sequential Read */ -+#define MV_MX25L_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ -+#define MV_MX25L_PP_CMND_OPCD 0x02 /* Page Program */ -+#define MV_MX25L_SE_CMND_OPCD 0xD8 /* Sector Erase */ -+#define MV_MX25L_BE_CMND_OPCD 0xC7 /* Bulk Erase */ -+#define MV_MX25L_DP_CMND_OPCD 0xB9 /* Deep Power Down */ -+#define MV_MX25L_RES_CMND_OPCD 0xAB /* Read Electronic Signature */ -+ -+/* Status Register Write Protect Bit Masks - 4bits */ -+#define MV_MX25L_STATUS_REG_WP_MASK (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_NONE (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_1_OF_128 (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_1_OF_64 (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_1_OF_32 (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_1_OF_16 (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_1_OF_8 (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_1_OF_4 (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_1_OF_2 (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_ALL (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) -+ -+/************************************/ -+/* SPANSION S25FL128P Device Specific */ -+/************************************/ -+ -+/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ -+#define MV_SPANSION_MANF_ID 0x01 -+#define MV_S25FL128_DEVICE_ID 0x2018 -+#define MV_S25FL128_MAX_SPI_FREQ 33000000 /* 33MHz */ -+#define MV_S25FL128_MAX_FAST_SPI_FREQ 104000000 /* 104MHz */ -+#define MV_S25FL128_FAST_READ_DUMMY_BYTES 1 -+ -+/* Sector Sizes and population per device model*/ -+#define MV_S25FL128_SECTOR_SIZE 0x40000 /* 256K */ -+#define MV_S25FL128_SECTOR_NUMBER 64 -+#define MV_S25FL_PAGE_SIZE 0x100 /* 256 byte */ -+ -+#define MV_S25FL_WREN_CMND_OPCD 0x06 /* Write Enable */ -+#define MV_S25FL_WRDI_CMND_OPCD 0x04 /* Write Disable */ -+#define MV_S25FL_RDID_CMND_OPCD 0x9F /* Read ID */ -+#define MV_S25FL_RDSR_CMND_OPCD 0x05 /* Read Status Register */ -+#define MV_S25FL_WRSR_CMND_OPCD 0x01 /* Write Status Register */ -+#define MV_S25FL_READ_CMND_OPCD 0x03 /* Sequential Read */ -+#define MV_S25FL_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ -+#define MV_S25FL_PP_CMND_OPCD 0x02 /* Page Program */ -+#define MV_S25FL_SE_CMND_OPCD 0xD8 /* Sector Erase */ -+#define MV_S25FL_BE_CMND_OPCD 0xC7 /* Bulk Erase */ -+#define MV_S25FL_DP_CMND_OPCD 0xB9 /* Deep Power Down */ -+#define MV_S25FL_RES_CMND_OPCD 0xAB /* Read Electronic Signature */ -+ -+/* Status Register Write Protect Bit Masks - 4bits */ -+#define MV_S25FL_STATUS_REG_WP_MASK (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_NONE (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_1_OF_128 (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_1_OF_64 (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_1_OF_32 (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_1_OF_16 (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_1_OF_8 (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_1_OF_4 (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_1_OF_2 (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_ALL (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) -+ -+#endif /* __INCmvSFlashSpecH */ -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.c ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.c 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,576 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "spi/mvSpi.h" -+#include "spi/mvSpiSpec.h" -+ -+#include "ctrlEnv/mvCtrlEnvLib.h" -+ -+/* #define MV_DEBUG */ -+#ifdef MV_DEBUG -+#define DB(x) x -+#define mvOsPrintf printf -+#else -+#define DB(x) -+#endif -+ -+ -+/******************************************************************************* -+* mvSpi16bitDataTxRx - Transmt and receive data -+* -+* DESCRIPTION: -+* Tx data and block waiting for data to be transmitted -+* -+********************************************************************************/ -+static MV_STATUS mvSpi16bitDataTxRx (MV_U16 txData, MV_U16 * pRxData) -+{ -+ MV_U32 i; -+ MV_BOOL ready = MV_FALSE; -+ -+ /* First clear the bit in the interrupt cause register */ -+ MV_REG_WRITE(MV_SPI_INT_CAUSE_REG, 0x0); -+ -+ /* Transmit data */ -+ MV_REG_WRITE(MV_SPI_DATA_OUT_REG, MV_16BIT_LE(txData)); -+ -+ /* wait with timeout for memory ready */ -+ for (i=0; i> 8) & 0xFF); -+ -+#elif defined(MV_CPU_BE) -+ -+ /* perform the data write to the buffer in two stages with 8bit each */ -+ MV_U8 * bptr = (MV_U8 *)pRxData; -+ MV_U16 data = MV_16BIT_LE(MV_REG_READ(MV_SPI_DATA_IN_REG)); -+ *bptr = ((data >> 8) & 0xFF); -+ ++bptr; -+ *bptr = (data & 0xFF); -+ -+#else -+ #error "CPU endianess isn't defined!\n" -+#endif -+ -+ } -+ else -+ *pRxData = MV_16BIT_LE(MV_REG_READ(MV_SPI_DATA_IN_REG)); -+ } -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvSpi8bitDataTxRx - Transmt and receive data (8bits) -+* -+* DESCRIPTION: -+* Tx data and block waiting for data to be transmitted -+* -+********************************************************************************/ -+static MV_STATUS mvSpi8bitDataTxRx (MV_U8 txData, MV_U8 * pRxData) -+{ -+ MV_U32 i; -+ MV_BOOL ready = MV_FALSE; -+ -+ /* First clear the bit in the interrupt cause register */ -+ MV_REG_WRITE(MV_SPI_INT_CAUSE_REG, 0x0); -+ -+ /* Transmit data */ -+ MV_REG_WRITE(MV_SPI_DATA_OUT_REG, txData); -+ -+ /* wait with timeout for memory ready */ -+ for (i=0; i serialBaudRate) -+ continue; -+ -+ /* check for exact fit */ -+ if ((cpuClk / preScale[i]) == serialBaudRate) -+ { -+ bestPrescaleIndx = i; -+ break; -+ } -+ -+ /* check if this is better than the previous one */ -+ if ((serialBaudRate - (cpuClk / preScale[i])) < minBaudOffset) -+ { -+ minBaudOffset = (serialBaudRate - (cpuClk / preScale[i])); -+ bestPrescaleIndx = i; -+ } -+ } -+ -+ if (bestPrescaleIndx > 14) -+ { -+ mvOsPrintf("%s ERROR: SPI baud rate prescale error!\n", __FUNCTION__); -+ return MV_OUT_OF_RANGE; -+ } -+ -+ /* configure the Prescale */ -+ tempReg = MV_REG_READ(MV_SPI_IF_CONFIG_REG); -+ tempReg = ((tempReg & ~MV_SPI_CLK_PRESCALE_MASK) | (bestPrescaleIndx + 0x12)); -+ MV_REG_WRITE(MV_SPI_IF_CONFIG_REG, tempReg); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSpiCsAssert - Assert the Chip Select pin indicating a new transfer -+* -+* DESCRIPTION: -+* Assert The chip select - used to select an external SPI device -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Success or Error code. -+* -+********************************************************************************/ -+MV_VOID mvSpiCsAssert(MV_VOID) -+{ -+ /* For devices in which the SPI is muxed on the MPP with other interfaces*/ -+ mvMPPConfigToSPI(); -+ mvOsUDelay(1); -+ MV_REG_BIT_SET(MV_SPI_IF_CTRL_REG, MV_SPI_CS_ENABLE_MASK); -+} -+ -+/******************************************************************************* -+* mvSpiCsDeassert - DeAssert the Chip Select pin indicating the end of a -+* SPI transfer sequence -+* -+* DESCRIPTION: -+* DeAssert the chip select pin -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Success or Error code. -+* -+********************************************************************************/ -+MV_VOID mvSpiCsDeassert(MV_VOID) -+{ -+ MV_REG_BIT_RESET(MV_SPI_IF_CTRL_REG, MV_SPI_CS_ENABLE_MASK); -+ -+ /* For devices in which the SPI is muxed on the MPP with other interfaces*/ -+ mvMPPConfigToDefault(); -+} -+ -+/******************************************************************************* -+* mvSpiRead - Read a buffer over the SPI interface -+* -+* DESCRIPTION: -+* Receive (read) a buffer over the SPI interface in 16bit chunks. If the -+* buffer size is odd, then the last chunk will be 8bits. Chip select is not -+* handled at this level. -+* -+* INPUT: -+* pRxBuff: Pointer to the buffer to hold the received data -+* buffSize: length of the pRxBuff -+* -+* OUTPUT: -+* pRxBuff: Pointer to the buffer with the received data -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSpiRead (MV_U8* pRxBuff, MV_U32 buffSize) -+{ -+ MV_STATUS ret; -+ MV_U32 bytesLeft = buffSize; -+ MV_U16* rxPtr = (MV_U16*)pRxBuff; -+ -+ /* check for null parameters */ -+ if (pRxBuff == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check that the buffer pointer and the buffer size are 16bit aligned */ -+ if ((((MV_U32)buffSize & 1) == 0) && (((MV_U32)pRxBuff & 1) == 0)) -+ { -+ /* Verify that the SPI mode is in 16bit mode */ -+ MV_REG_BIT_SET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); -+ -+ /* TX/RX as long we have complete 16bit chunks */ -+ while (bytesLeft >= MV_SPI_16_BIT_CHUNK_SIZE) -+ { -+ /* Transmitted and wait for the transfer to be completed */ -+ if ((ret = mvSpi16bitDataTxRx(MV_SPI_DUMMY_WRITE_16BITS, rxPtr)) != MV_OK) -+ return ret; -+ -+ /* increment the pointers */ -+ rxPtr++; -+ bytesLeft -= MV_SPI_16_BIT_CHUNK_SIZE; -+ } -+ -+ } -+ else -+ { -+ /* Verify that the SPI mode is in 8bit mode */ -+ MV_REG_BIT_RESET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); -+ -+ /* TX/RX in 8bit chanks */ -+ while (bytesLeft > 0) -+ { -+ /* Transmitted and wait for the transfer to be completed */ -+ if ((ret = mvSpi8bitDataTxRx(MV_SPI_DUMMY_WRITE_8BITS, pRxBuff)) != MV_OK) -+ return ret; -+ /* increment the pointers */ -+ pRxBuff++; -+ bytesLeft--; -+ } -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSpiWrite - Transmit a buffer over the SPI interface -+* -+* DESCRIPTION: -+* Transmit a buffer over the SPI interface in 16bit chunks. If the -+* buffer size is odd, then the last chunk will be 8bits. No chip select -+* action is taken. -+* -+* INPUT: -+* pTxBuff: Pointer to the buffer holding the TX data -+* buffSize: length of the pTxBuff -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSpiWrite(MV_U8* pTxBuff, MV_U32 buffSize) -+{ -+ MV_STATUS ret; -+ MV_U32 bytesLeft = buffSize; -+ MV_U16* txPtr = (MV_U16*)pTxBuff; -+ -+ /* check for null parameters */ -+ if (pTxBuff == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check that the buffer pointer and the buffer size are 16bit aligned */ -+ if ((((MV_U32)buffSize & 1) == 0) && (((MV_U32)pTxBuff & 1) == 0)) -+ { -+ /* Verify that the SPI mode is in 16bit mode */ -+ MV_REG_BIT_SET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); -+ -+ /* TX/RX as long we have complete 16bit chunks */ -+ while (bytesLeft >= MV_SPI_16_BIT_CHUNK_SIZE) -+ { -+ /* Transmitted and wait for the transfer to be completed */ -+ if ((ret = mvSpi16bitDataTxRx(*txPtr, NULL)) != MV_OK) -+ return ret; -+ -+ /* increment the pointers */ -+ txPtr++; -+ bytesLeft -= MV_SPI_16_BIT_CHUNK_SIZE; -+ } -+ } -+ else -+ { -+ -+ /* Verify that the SPI mode is in 8bit mode */ -+ MV_REG_BIT_RESET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); -+ -+ /* TX/RX in 8bit chanks */ -+ while (bytesLeft > 0) -+ { -+ /* Transmitted and wait for the transfer to be completed */ -+ if ((ret = mvSpi8bitDataTxRx(*pTxBuff, NULL)) != MV_OK) -+ return ret; -+ -+ /* increment the pointers */ -+ pTxBuff++; -+ bytesLeft--; -+ } -+ } -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvSpiReadWrite - Read and Write a buffer simultanuosely -+* -+* DESCRIPTION: -+* Transmit and receive a buffer over the SPI in 16bit chunks. If the -+* buffer size is odd, then the last chunk will be 8bits. The SPI chip -+* select is not handled implicitely. -+* -+* INPUT: -+* pRxBuff: Pointer to the buffer to write the RX info in -+* pTxBuff: Pointer to the buffer holding the TX info -+* buffSize: length of both the pTxBuff and pRxBuff -+* -+* OUTPUT: -+* pRxBuff: Pointer of the buffer holding the RX data -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSpiReadWrite(MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize) -+{ -+ MV_STATUS ret; -+ MV_U32 bytesLeft = buffSize; -+ MV_U16* txPtr = (MV_U16*)pTxBuff; -+ MV_U16* rxPtr = (MV_U16*)pRxBuff; -+ -+ /* check for null parameters */ -+ if ((pRxBuff == NULL) || (pTxBuff == NULL)) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check that the buffer pointer and the buffer size are 16bit aligned */ -+ if ((((MV_U32)buffSize & 1) == 0) && (((MV_U32)pTxBuff & 1) == 0) && (((MV_U32)pRxBuff & 1) == 0)) -+ { -+ /* Verify that the SPI mode is in 16bit mode */ -+ MV_REG_BIT_SET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); -+ -+ /* TX/RX as long we have complete 16bit chunks */ -+ while (bytesLeft >= MV_SPI_16_BIT_CHUNK_SIZE) -+ { -+ /* Transmitted and wait for the transfer to be completed */ -+ if ((ret = mvSpi16bitDataTxRx(*txPtr, rxPtr)) != MV_OK) -+ return ret; -+ -+ /* increment the pointers */ -+ txPtr++; -+ rxPtr++; -+ bytesLeft -= MV_SPI_16_BIT_CHUNK_SIZE; -+ } -+ } -+ else -+ { -+ /* Verify that the SPI mode is in 8bit mode */ -+ MV_REG_BIT_RESET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); -+ -+ /* TX/RX in 8bit chanks */ -+ while (bytesLeft > 0) -+ { -+ /* Transmitted and wait for the transfer to be completed */ -+ if ( (ret = mvSpi8bitDataTxRx(*pTxBuff, pRxBuff) ) != MV_OK) -+ return ret; -+ pRxBuff++; -+ pTxBuff++; -+ bytesLeft--; -+ } -+ } -+ -+ return MV_OK; -+} -+ -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,94 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvSpihH -+#define __INCmvSpihH -+ -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+ -+/* Function Prototypes */ -+/* Init */ -+MV_STATUS mvSpiInit (MV_U32 serialBaudRate); -+ -+/* Set the Frequency of the Spi clock */ -+MV_STATUS mvSpiBaudRateSet(MV_U32 serialBaudRate); -+ -+/* Assert the SPI chip select */ -+MV_VOID mvSpiCsAssert (MV_VOID); -+ -+/* De-assert the SPI chip select */ -+MV_VOID mvSpiCsDeassert (MV_VOID); -+ -+/* Simultanuous Read and write */ -+MV_STATUS mvSpiReadWrite (MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize); -+ -+/* serialize a buffer on the TX line - Rx is ignored */ -+MV_STATUS mvSpiWrite (MV_U8* pTxBuff, MV_U32 buffSize); -+ -+/* read from the RX line by writing dummy values to the TX line */ -+MV_STATUS mvSpiRead (MV_U8* pRxBuff, MV_U32 buffSize); -+ -+#endif /* __INCmvSpihH */ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.c ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.c 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,249 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "spi/mvSpi.h" -+#include "spi/mvSpiSpec.h" -+ -+/*#define MV_DEBUG*/ -+#ifdef MV_DEBUG -+#define DB(x) x -+#else -+#define DB(x) -+#endif -+ -+ -+/******************************************************************************* -+* mvSpiReadAndWrite - Read and Write a buffer simultanuousely -+* -+* DESCRIPTION: -+* Transmit and receive a buffer over the SPI in 16bit chunks. If the -+* buffer size is odd, then the last chunk will be 8bits. -+* -+* INPUT: -+* pRxBuff: Pointer to the buffer to write the RX info in -+* pTxBuff: Pointer to the buffer holding the TX info -+* buffSize: length of both the pTxBuff and pRxBuff -+* -+* OUTPUT: -+* pRxBuff: Pointer of the buffer holding the RX data -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSpiReadAndWrite(MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize) -+{ -+ MV_STATUS ret; -+ -+ /* check for null parameters */ -+ if ((pRxBuff == NULL) || (pTxBuff == NULL) || (buffSize == 0)) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* First assert the chip select */ -+ mvSpiCsAssert(); -+ -+ ret = mvSpiReadWrite(pRxBuff, pTxBuff, buffSize); -+ -+ /* Finally deassert the chip select */ -+ mvSpiCsDeassert(); -+ -+ return ret; -+} -+ -+/******************************************************************************* -+* mvSpiWriteThenWrite - Serialize a command followed by the data over the TX line -+* -+* DESCRIPTION: -+* Assert the chip select line. Transmit the command buffer followed by -+* the data buffer. Then deassert the CS line. -+* -+* INPUT: -+* pCmndBuff: Pointer to the command buffer to transmit -+* cmndSize: length of the command size -+* pTxDataBuff: Pointer to the data buffer to transmit -+* txDataSize: length of the data buffer -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSpiWriteThenWrite (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pTxDataBuff, -+ MV_U32 txDataSize) -+{ -+ MV_STATUS ret = MV_OK, tempRet; -+ -+ /* check for null parameters */ -+#ifndef CONFIG_MARVELL -+ if(NULL == pTxDataBuff) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+#endif -+ -+ if (pCmndBuff == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* First assert the chip select */ -+ mvSpiCsAssert(); -+ -+ /* first write the command */ -+ if ((cmndSize) && (pCmndBuff != NULL)) -+ { -+ if ((tempRet = mvSpiWrite(pCmndBuff, cmndSize)) != MV_OK) -+ ret = tempRet; -+ } -+ -+ /* Then write the data buffer */ -+#ifndef CONFIG_MARVELL -+ if (txDataSize) -+#else -+ if ((txDataSize) && (pTxDataBuff != NULL)) -+#endif -+ { -+ if ((tempRet = mvSpiWrite(pTxDataBuff, txDataSize)) != MV_OK) -+ ret = tempRet; -+ } -+ -+ /* Finally deassert the chip select */ -+ mvSpiCsDeassert(); -+ -+ return ret; -+} -+ -+/******************************************************************************* -+* mvSpiWriteThenRead - Serialize a command then read a data buffer -+* -+* DESCRIPTION: -+* Assert the chip select line. Transmit the command buffer then read -+* the data buffer. Then deassert the CS line. -+* -+* INPUT: -+* pCmndBuff: Pointer to the command buffer to transmit -+* cmndSize: length of the command size -+* pRxDataBuff: Pointer to the buffer to read the data in -+* txDataSize: length of the data buffer -+* -+* OUTPUT: -+* pRxDataBuff: Pointer to the buffer holding the data -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSpiWriteThenRead (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pRxDataBuff, -+ MV_U32 rxDataSize,MV_U32 dummyBytesToRead) -+{ -+ MV_STATUS ret = MV_OK, tempRet; -+ MV_U8 dummyByte; -+ -+ /* check for null parameters */ -+ if ((pCmndBuff == NULL) && (pRxDataBuff == NULL)) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* First assert the chip select */ -+ mvSpiCsAssert(); -+ -+ /* first write the command */ -+ if ((cmndSize) && (pCmndBuff != NULL)) -+ { -+ if ((tempRet = mvSpiWrite(pCmndBuff, cmndSize)) != MV_OK) -+ ret = tempRet; -+ } -+ -+ /* Read dummy bytes before real data. */ -+ while(dummyBytesToRead) -+ { -+ mvSpiRead(&dummyByte,1); -+ dummyBytesToRead--; -+ } -+ -+ /* Then write the data buffer */ -+ if ((rxDataSize) && (pRxDataBuff != NULL)) -+ { -+ if ((tempRet = mvSpiRead(pRxDataBuff, rxDataSize)) != MV_OK) -+ ret = tempRet; -+ } -+ -+ /* Finally deassert the chip select */ -+ mvSpiCsDeassert(); -+ -+ return ret; -+} -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,82 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvSpiCmndhH -+#define __INCmvSpiCmndhH -+ -+#include "mvTypes.h" -+ -+/* Function Prototypes */ -+ -+/* Simultanuous Read and write */ -+MV_STATUS mvSpiReadAndWrite (MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize); -+ -+/* write command - write a command and then write data */ -+MV_STATUS mvSpiWriteThenWrite (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pTxDataBuff, MV_U32 txDataSize); -+ -+/* read command - write a command and then read data by writing dummy data */ -+MV_STATUS mvSpiWriteThenRead (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pRxDataBuff, -+ MV_U32 rxDataSize,MV_U32 dummyBytesToRead); -+ -+#endif /* __INCmvSpiCmndhH */ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiSpec.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiSpec.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiSpec.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiSpec.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,98 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvSpiSpecH -+#define __INCmvSpiSpecH -+ -+/* Constants */ -+#define MV_SPI_WAIT_RDY_MAX_LOOP 100000 -+#define MV_SPI_16_BIT_CHUNK_SIZE 2 -+#define MV_SPI_DUMMY_WRITE_16BITS 0xFFFF -+#define MV_SPI_DUMMY_WRITE_8BITS 0xFF -+ -+/* Marvell Flash Device Controller Registers */ -+#define MV_SPI_CTRLR_OFST 0x10600 -+#define MV_SPI_IF_CTRL_REG (MV_SPI_CTRLR_OFST + 0x00) -+#define MV_SPI_IF_CONFIG_REG (MV_SPI_CTRLR_OFST + 0x04) -+#define MV_SPI_DATA_OUT_REG (MV_SPI_CTRLR_OFST + 0x08) -+#define MV_SPI_DATA_IN_REG (MV_SPI_CTRLR_OFST + 0x0c) -+#define MV_SPI_INT_CAUSE_REG (MV_SPI_CTRLR_OFST + 0x10) -+#define MV_SPI_INT_CAUSE_MASK_REG (MV_SPI_CTRLR_OFST + 0x14) -+ -+/* Serial Memory Interface Control Register Masks */ -+#define MV_SPI_CS_ENABLE_OFFSET 0 /* bit 0 */ -+#define MV_SPI_MEMORY_READY_OFFSET 1 /* bit 1 */ -+#define MV_SPI_CS_ENABLE_MASK (0x1 << MV_SPI_CS_ENABLE_OFFSET) -+#define MV_SPI_MEMORY_READY_MASK (0x1 << MV_SPI_MEMORY_READY_OFFSET) -+ -+/* Serial Memory Interface Configuration Register Masks */ -+#define MV_SPI_CLK_PRESCALE_OFFSET 0 /* bit 0-4 */ -+#define MV_SPI_BYTE_LENGTH_OFFSET 5 /* bit 5 */ -+#define MV_SPI_ADDRESS_BURST_LENGTH_OFFSET 8 /* bit 8-9 */ -+#define MV_SPI_CLK_PRESCALE_MASK (0x1F << MV_SPI_CLK_PRESCALE_OFFSET) -+#define MV_SPI_BYTE_LENGTH_MASK (0x1 << MV_SPI_BYTE_LENGTH_OFFSET) -+#define MV_SPI_ADDRESS_BURST_LENGTH_MASK (0x3 << MV_SPI_ADDRESS_BURST_LENGTH_OFFSET) -+ -+#endif /* __INCmvSpiSpecH */ -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.c linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.c ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.c 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,1023 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#include "mvTwsi.h" -+#include "mvTwsiSpec.h" -+#include "cpu/mvCpu.h" -+ -+ -+/*#define MV_DEBUG*/ -+#ifdef MV_DEBUG -+#define DB(x) x -+#else -+#define DB(x) -+#endif -+ -+static MV_VOID twsiIntFlgClr(MV_U8 chanNum); -+static MV_BOOL twsiMainIntGet(MV_U8 chanNum); -+static MV_VOID twsiAckBitSet(MV_U8 chanNum); -+static MV_U32 twsiStsGet(MV_U8 chanNum); -+static MV_VOID twsiReset(MV_U8 chanNum); -+static MV_STATUS twsiAddr7BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command); -+static MV_STATUS twsiAddr10BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command); -+static MV_STATUS twsiDataTransmit(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize); -+static MV_STATUS twsiDataReceive(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize); -+static MV_STATUS twsiTargetOffsSet(MV_U8 chanNum, MV_U32 offset,MV_BOOL moreThen256); -+ -+ -+static MV_BOOL twsiTimeoutChk(MV_U32 timeout, const MV_8 *pString) -+{ -+ if(timeout >= TWSI_TIMEOUT_VALUE) -+ { -+ DB(mvOsPrintf("%s",pString)); -+ return MV_TRUE; -+ } -+ return MV_FALSE; -+ -+} -+/******************************************************************************* -+* mvTwsiStartBitSet - Set start bit on the bus -+* -+* DESCRIPTION: -+* This routine sets the start bit on the TWSI bus. -+* The routine first checks for interrupt flag condition, then it sets -+* the start bit in the TWSI Control register. -+* If the interrupt flag condition check previously was set, the function -+* will clear it. -+* The function then wait for the start bit to be cleared by the HW. -+* Then it waits for the interrupt flag to be set and eventually, the -+* TWSI status is checked to be 0x8 or 0x10(repeated start bit). -+* -+* INPUT: -+* chanNum - TWSI channel. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK is start bit was set successfuly on the bus. -+* MV_FAIL if interrupt flag was set before setting start bit. -+* -+*******************************************************************************/ -+MV_STATUS mvTwsiStartBitSet(MV_U8 chanNum) -+{ -+ MV_BOOL isIntFlag = MV_FALSE; -+ MV_U32 timeout, temp; -+ -+ DB(mvOsPrintf("TWSI: mvTwsiStartBitSet \n")); -+ /* check Int flag */ -+ if(twsiMainIntGet(chanNum)) -+ isIntFlag = MV_TRUE; -+ /* set start Bit */ -+ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); -+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp | TWSI_CONTROL_START_BIT); -+ -+ /* in case that the int flag was set before i.e. repeated start bit */ -+ if(isIntFlag){ -+ DB(mvOsPrintf("TWSI: mvTwsiStartBitSet repeated start Bit\n")); -+ twsiIntFlgClr(chanNum); -+ } -+ -+ /* wait for interrupt */ -+ timeout = 0; -+ while(!twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: mvTwsiStartBitSet ERROR - Start Clear bit TimeOut .\n")) -+ return MV_TIMEOUT; -+ -+ -+ /* check that start bit went down */ -+ if((MV_REG_READ(TWSI_CONTROL_REG(chanNum)) & TWSI_CONTROL_START_BIT) != 0) -+ { -+ mvOsPrintf("TWSI: mvTwsiStartBitSet ERROR - start bit didn't went down\n"); -+ return MV_FAIL; -+ } -+ -+ /* check the status */ -+ temp = twsiStsGet(chanNum); -+ if(( temp != TWSI_START_CON_TRA ) && ( temp != TWSI_REPEATED_START_CON_TRA )) -+ { -+ mvOsPrintf("TWSI: mvTwsiStartBitSet ERROR - status %x after Set Start Bit. \n",temp); -+ return MV_FAIL; -+ } -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvTwsiStopBitSet - Set stop bit on the bus -+* -+* DESCRIPTION: -+* This routine set the stop bit on the TWSI bus. -+* The function then wait for the stop bit to be cleared by the HW. -+* Finally the function checks for status of 0xF8. -+* -+* INPUT: -+* chanNum - TWSI channel -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE is stop bit was set successfuly on the bus. -+* -+*******************************************************************************/ -+MV_STATUS mvTwsiStopBitSet(MV_U8 chanNum) -+{ -+ MV_U32 timeout, temp; -+ -+ /* Generate stop bit */ -+ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); -+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp | TWSI_CONTROL_STOP_BIT); -+ -+ twsiIntFlgClr(chanNum); -+ -+ /* wait for stop bit to come down */ -+ timeout = 0; -+ while( ((MV_REG_READ(TWSI_CONTROL_REG(chanNum)) & TWSI_CONTROL_STOP_BIT) != 0) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: mvTwsiStopBitSet ERROR - Stop bit TimeOut .\n")) -+ return MV_TIMEOUT; -+ -+ /* check that the stop bit went down */ -+ if((MV_REG_READ(TWSI_CONTROL_REG(chanNum)) & TWSI_CONTROL_STOP_BIT) != 0) -+ { -+ mvOsPrintf("TWSI: mvTwsiStopBitSet ERROR - stop bit didn't went down. \n"); -+ return MV_FAIL; -+ } -+ -+ /* check the status */ -+ temp = twsiStsGet(chanNum); -+ if( temp != TWSI_NO_REL_STS_INT_FLAG_IS_KEPT_0){ -+ mvOsPrintf("TWSI: mvTwsiStopBitSet ERROR - status %x after Stop Bit. \n", temp); -+ return MV_FAIL; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* twsiMainIntGet - Get twsi bit from main Interrupt cause. -+* -+* DESCRIPTION: -+* This routine returns the twsi interrupt flag value. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE is interrupt flag is set, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+static MV_BOOL twsiMainIntGet(MV_U8 chanNum) -+{ -+ MV_U32 temp; -+ -+ /* get the int flag bit */ -+ -+ temp = MV_REG_READ(TWSI_CPU_MAIN_INT_CAUSE_REG); -+ if (temp & (TWSI0_CPU_MAIN_INT_BIT << chanNum)) -+ return MV_TRUE; -+ -+ return MV_FALSE; -+} -+/******************************************************************************* -+* twsiIntFlgClr - Clear Interrupt flag. -+* -+* DESCRIPTION: -+* This routine clears the interrupt flag. It does NOT poll the interrupt -+* to make sure the clear. After clearing the interrupt, it waits for at -+* least 1 miliseconds. -+* -+* INPUT: -+* chanNum - TWSI channel -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+static MV_VOID twsiIntFlgClr(MV_U8 chanNum) -+{ -+ MV_U32 temp; -+ -+ /* wait for 1 mili to prevent TWSI register write after write problems */ -+ mvOsDelay(1); -+ /* clear the int flag bit */ -+ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); -+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum),temp & ~(TWSI_CONTROL_INT_FLAG_SET)); -+ -+ /* wait for 1 mili sec for the clear to take effect */ -+ mvOsDelay(1); -+ -+ return; -+} -+ -+ -+/******************************************************************************* -+* twsiAckBitSet - Set acknowledge bit on the bus -+* -+* DESCRIPTION: -+* This routine set the acknowledge bit on the TWSI bus. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+static MV_VOID twsiAckBitSet(MV_U8 chanNum) -+{ -+ MV_U32 temp; -+ -+ /*Set the Ack bit */ -+ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); -+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp | TWSI_CONTROL_ACK); -+ -+ /* Add delay of 1ms */ -+ mvOsDelay(1); -+ return; -+} -+ -+ -+/******************************************************************************* -+* twsiInit - Initialize TWSI interface -+* -+* DESCRIPTION: -+* This routine: -+* -Reset the TWSI. -+* -Initialize the TWSI clock baud rate according to given frequancy -+* parameter based on Tclk frequancy and enables TWSI slave. -+* -Set the ack bit. -+* -Assign the TWSI slave address according to the TWSI address Type. -+* -+* -+* INPUT: -+* chanNum - TWSI channel -+* frequancy - TWSI frequancy in KHz. (up to 100KHZ) -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Actual frequancy. -+* -+*******************************************************************************/ -+MV_U32 mvTwsiInit(MV_U8 chanNum, MV_HZ frequancy, MV_U32 Tclk, MV_TWSI_ADDR *pTwsiAddr, MV_BOOL generalCallEnable) -+{ -+ MV_U32 n,m,freq,margin,minMargin = 0xffffffff; -+ MV_U32 power; -+ MV_U32 actualFreq = 0,actualN = 0,actualM = 0,val; -+ -+ if(frequancy > 100000) -+ { -+ mvOsPrintf("Warning TWSI frequancy is too high, please use up tp 100Khz. \n"); -+ } -+ -+ DB(mvOsPrintf("TWSI: mvTwsiInit - Tclk = %d freq = %d\n",Tclk,frequancy)); -+ /* Calucalte N and M for the TWSI clock baud rate */ -+ for(n = 0 ; n < 8 ; n++) -+ { -+ for(m = 0 ; m < 16 ; m++) -+ { -+ power = 2 << n; /* power = 2^(n+1) */ -+ freq = Tclk/(10*(m+1)*power); -+ margin = MV_ABS(frequancy - freq); -+ if(margin < minMargin) -+ { -+ minMargin = margin; -+ actualFreq = freq; -+ actualN = n; -+ actualM = m; -+ } -+ } -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiInit - actN %d actM %d actFreq %d\n",actualN , actualM, actualFreq)); -+ /* Reset the TWSI logic */ -+ twsiReset(chanNum); -+ -+ /* Set the baud rate */ -+ val = ((actualM<< TWSI_BAUD_RATE_M_OFFS) | actualN << TWSI_BAUD_RATE_N_OFFS); -+ MV_REG_WRITE(TWSI_STATUS_BAUDE_RATE_REG(chanNum),val); -+ -+ /* Enable the TWSI and slave */ -+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), TWSI_CONTROL_ENA | TWSI_CONTROL_ACK); -+ -+ /* set the TWSI slave address */ -+ if( pTwsiAddr->type == ADDR10_BIT )/* 10 Bit deviceAddress */ -+ { -+ /* writing the 2 most significant bits of the 10 bit address*/ -+ val = ((pTwsiAddr->address & TWSI_SLAVE_ADDR_10BIT_MASK) >> TWSI_SLAVE_ADDR_10BIT_OFFS ); -+ /* bits 7:3 must be 0x11110 */ -+ val |= TWSI_SLAVE_ADDR_10BIT_CONST; -+ /* set GCE bit */ -+ if(generalCallEnable) -+ val |= TWSI_SLAVE_ADDR_GCE_ENA; -+ /* write slave address */ -+ MV_REG_WRITE(TWSI_SLAVE_ADDR_REG(chanNum),val); -+ -+ /* writing the 8 least significant bits of the 10 bit address*/ -+ val = (pTwsiAddr->address << TWSI_EXTENDED_SLAVE_OFFS) & TWSI_EXTENDED_SLAVE_MASK; -+ MV_REG_WRITE(TWSI_EXTENDED_SLAVE_ADDR_REG(chanNum), val); -+ } -+ else /*7 bit address*/ -+ { -+ /* set the 7 Bits address */ -+ MV_REG_WRITE(TWSI_EXTENDED_SLAVE_ADDR_REG(chanNum),0x0); -+ val = (pTwsiAddr->address << TWSI_SLAVE_ADDR_7BIT_OFFS) & TWSI_SLAVE_ADDR_7BIT_MASK; -+ MV_REG_WRITE(TWSI_SLAVE_ADDR_REG(chanNum), val); -+ } -+ -+ /* unmask twsi int */ -+ val = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); -+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), val | TWSI_CONTROL_INT_ENA); -+ /* Add delay of 1ms */ -+ mvOsDelay(1); -+ -+ return actualFreq; -+} -+ -+ -+/******************************************************************************* -+* twsiStsGet - Get the TWSI status value. -+* -+* DESCRIPTION: -+* This routine returns the TWSI status value. -+* -+* INPUT: -+* chanNum - TWSI channel -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_U32 - the TWSI status. -+* -+*******************************************************************************/ -+static MV_U32 twsiStsGet(MV_U8 chanNum) -+{ -+ return MV_REG_READ(TWSI_STATUS_BAUDE_RATE_REG(chanNum)); -+ -+} -+ -+/******************************************************************************* -+* twsiReset - Reset the TWSI. -+* -+* DESCRIPTION: -+* Resets the TWSI logic and sets all TWSI registers to their reset values. -+* -+* INPUT: -+* chanNum - TWSI channel -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None -+* -+*******************************************************************************/ -+static MV_VOID twsiReset(MV_U8 chanNum) -+{ -+ /* Reset the TWSI logic */ -+ MV_REG_WRITE(TWSI_SOFT_RESET_REG(chanNum),0); -+ -+ /* wait for 2 mili sec */ -+ mvOsDelay(2); -+ -+ return; -+} -+ -+ -+ -+ -+/******************************* POLICY ****************************************/ -+ -+ -+ -+/******************************************************************************* -+* mvTwsiAddrSet - Set address on TWSI bus. -+* -+* DESCRIPTION: -+* This function Set address (7 or 10 Bit address) on the Twsi Bus. -+* -+* INPUT: -+* chanNum - TWSI channel -+* pTwsiAddr - twsi address. -+* command - read / write . -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK - if setting the address completed succesfully. -+* MV_FAIL otherwmise. -+* -+*******************************************************************************/ -+MV_STATUS mvTwsiAddrSet(MV_U8 chanNum, MV_TWSI_ADDR *pTwsiAddr, MV_TWSI_CMD command) -+{ -+ DB(mvOsPrintf("TWSI: mvTwsiAddr7BitSet addr %x , type %d, cmd is %s\n",pTwsiAddr->address,\ -+ pTwsiAddr->type, ((command==MV_TWSI_WRITE)?"Write":"Read") )); -+ /* 10 Bit address */ -+ if(pTwsiAddr->type == ADDR10_BIT) -+ { -+ return twsiAddr10BitSet(chanNum, pTwsiAddr->address,command); -+ } -+ /* 7 Bit address */ -+ else -+ { -+ return twsiAddr7BitSet(chanNum, pTwsiAddr->address,command); -+ } -+ -+} -+ -+/******************************************************************************* -+* twsiAddr10BitSet - Set 10 Bit address on TWSI bus. -+* -+* DESCRIPTION: -+* There are two address phases: -+* 1) Write '11110' to data register bits [7:3] and 10-bit address MSB -+* (bits [9:8]) to data register bits [2:1] plus a write(0) or read(1) bit -+* to the Data register. Then it clears interrupt flag which drive -+* the address on the TWSI bus. The function then waits for interrupt -+* flag to be active and status 0x18 (write) or 0x40 (read) to be set. -+* 2) write the rest of 10-bit address to data register and clears -+* interrupt flag which drive the address on the TWSI bus. The -+* function then waits for interrupt flag to be active and status -+* 0xD0 (write) or 0xE0 (read) to be set. -+* -+* INPUT: -+* chanNum - TWSI channel -+* deviceAddress - twsi address. -+* command - read / write . -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK - if setting the address completed succesfully. -+* MV_FAIL otherwmise. -+* -+*******************************************************************************/ -+static MV_STATUS twsiAddr10BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command) -+{ -+ MV_U32 val,timeout; -+ -+ /* writing the 2 most significant bits of the 10 bit address*/ -+ val = ((deviceAddress & TWSI_DATA_ADDR_10BIT_MASK) >> TWSI_DATA_ADDR_10BIT_OFFS ); -+ /* bits 7:3 must be 0x11110 */ -+ val |= TWSI_DATA_ADDR_10BIT_CONST; -+ /* set command */ -+ val |= command; -+ MV_REG_WRITE(TWSI_DATA_REG(chanNum), val); -+ /* WA add a delay */ -+ mvOsDelay(1); -+ -+ /* clear Int flag */ -+ twsiIntFlgClr(chanNum); -+ -+ /* wait for Int to be Set */ -+ timeout = 0; -+ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiAddr10BitSet ERROR - 1st addr (10Bit) Int TimeOut.\n")) -+ return MV_TIMEOUT; -+ -+ /* check the status */ -+ val = twsiStsGet(chanNum); -+ if(( (val != TWSI_AD_PLS_RD_BIT_TRA_ACK_REC) && (command == MV_TWSI_READ ) ) || -+ ( (val != TWSI_AD_PLS_WR_BIT_TRA_ACK_REC) && (command == MV_TWSI_WRITE) )) -+ { -+ mvOsPrintf("TWSI: twsiAddr10BitSet ERROR - status %x 1st addr (10 Bit) in %s mode.\n"\ -+ ,val, ((command==MV_TWSI_WRITE)?"Write":"Read") ); -+ return MV_FAIL; -+ } -+ -+ /* set 8 LSB of the address */ -+ val = (deviceAddress << TWSI_DATA_ADDR_7BIT_OFFS) & TWSI_DATA_ADDR_7BIT_MASK; -+ MV_REG_WRITE(TWSI_DATA_REG(chanNum), val); -+ -+ /* clear Int flag */ -+ twsiIntFlgClr(chanNum); -+ -+ /* wait for Int to be Set */ -+ timeout = 0; -+ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiAddr10BitSet ERROR - 2nd (10 Bit) Int TimOut.\n")) -+ return MV_TIMEOUT; -+ -+ /* check the status */ -+ val = twsiStsGet(chanNum); -+ if(( (val != TWSI_SEC_AD_PLS_RD_BIT_TRA_ACK_REC) && (command == MV_TWSI_READ ) ) || -+ ( (val != TWSI_SEC_AD_PLS_WR_BIT_TRA_ACK_REC) && (command == MV_TWSI_WRITE) )) -+ { -+ mvOsPrintf("TWSI: twsiAddr10BitSet ERROR - status %x 2nd addr(10 Bit) in %s mode.\n"\ -+ ,val, ((command==MV_TWSI_WRITE)?"Write":"Read") ); -+ return MV_FAIL; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* twsiAddr7BitSet - Set 7 Bit address on TWSI bus. -+* -+* DESCRIPTION: -+* This function writes 7 bit address plus a write or read bit to the -+* Data register. Then it clears interrupt flag which drive the address on -+* the TWSI bus. The function then waits for interrupt flag to be active -+* and status 0x18 (write) or 0x40 (read) to be set. -+* -+* INPUT: -+* chanNum - TWSI channel -+* deviceAddress - twsi address. -+* command - read / write . -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK - if setting the address completed succesfully. -+* MV_FAIL otherwmise. -+* -+*******************************************************************************/ -+static MV_STATUS twsiAddr7BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command) -+{ -+ MV_U32 val,timeout; -+ -+ /* set the address */ -+ val = (deviceAddress << TWSI_DATA_ADDR_7BIT_OFFS) & TWSI_DATA_ADDR_7BIT_MASK; -+ /* set command */ -+ val |= command; -+ MV_REG_WRITE(TWSI_DATA_REG(chanNum), val); -+ /* WA add a delay */ -+ mvOsDelay(1); -+ -+ /* clear Int flag */ -+ twsiIntFlgClr(chanNum); -+ -+ /* wait for Int to be Set */ -+ timeout = 0; -+ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiAddr7BitSet ERROR - Addr (7 Bit) int TimeOut.\n")) -+ return MV_TIMEOUT; -+ -+ /* check the status */ -+ val = twsiStsGet(chanNum); -+ if(( (val != TWSI_AD_PLS_RD_BIT_TRA_ACK_REC) && (command == MV_TWSI_READ ) ) || -+ ( (val != TWSI_AD_PLS_WR_BIT_TRA_ACK_REC) && (command == MV_TWSI_WRITE) )) -+ { -+ /* only in debug, since in boot we try to read the SPD of both DRAM, and we don't -+ want error messeges in case DIMM doesn't exist. */ -+ DB(mvOsPrintf("TWSI: twsiAddr7BitSet ERROR - status %x addr (7 Bit) in %s mode.\n"\ -+ ,val,((command==MV_TWSI_WRITE)?"Write":"Read") )); -+ return MV_FAIL; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* twsiDataWrite - Trnasmit a data block over TWSI bus. -+* -+* DESCRIPTION: -+* This function writes a given data block to TWSI bus in 8 bit granularity. -+* first The function waits for interrupt flag to be active then -+* For each 8-bit data: -+* The function writes data to data register. It then clears -+* interrupt flag which drives the data on the TWSI bus. -+* The function then waits for interrupt flag to be active and status -+* 0x28 to be set. -+* -+* -+* INPUT: -+* chanNum - TWSI channel -+* pBlock - Data block. -+* blockSize - number of chars in pBlock. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK - if transmiting the block completed succesfully, -+* MV_BAD_PARAM - if pBlock is NULL, -+* MV_FAIL otherwmise. -+* -+*******************************************************************************/ -+static MV_STATUS twsiDataTransmit(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize) -+{ -+ MV_U32 timeout, temp, blockSizeWr = blockSize; -+ -+ if(NULL == pBlock) -+ return MV_BAD_PARAM; -+ -+ /* wait for Int to be Set */ -+ timeout = 0; -+ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataTransmit ERROR - Read Data Int TimeOut.\n")) -+ return MV_TIMEOUT; -+ -+ while(blockSizeWr) -+ { -+ /* write the data*/ -+ MV_REG_WRITE(TWSI_DATA_REG(chanNum),(MV_U32)*pBlock); -+ DB(mvOsPrintf("TWSI: twsiDataTransmit place = %d write %x \n",\ -+ blockSize - blockSizeWr, *pBlock)); -+ pBlock++; -+ blockSizeWr--; -+ -+ twsiIntFlgClr(chanNum); -+ -+ /* wait for Int to be Set */ -+ timeout = 0; -+ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataTransmit ERROR - Read Data Int TimeOut.\n")) -+ return MV_TIMEOUT; -+ -+ /* check the status */ -+ temp = twsiStsGet(chanNum); -+ if(temp != TWSI_M_TRAN_DATA_BYTE_ACK_REC) -+ { -+ mvOsPrintf("TWSI: twsiDataTransmit ERROR - status %x in write trans\n",temp); -+ return MV_FAIL; -+ } -+ -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* twsiDataReceive - Receive data block from TWSI bus. -+* -+* DESCRIPTION: -+* This function receive data block from TWSI bus in 8bit granularity -+* into pBlock buffer. -+* first The function waits for interrupt flag to be active then -+* For each 8-bit data: -+* It clears the interrupt flag which allows the next data to be -+* received from TWSI bus. -+* The function waits for interrupt flag to be active, -+* and status reg is 0x50. -+* Then the function reads data from data register, and copies it to -+* the given buffer. -+* -+* INPUT: -+* chanNum - TWSI channel -+* blockSize - number of bytes to read. -+* -+* OUTPUT: -+* pBlock - Data block. -+* -+* RETURN: -+* MV_OK - if receive transaction completed succesfully, -+* MV_BAD_PARAM - if pBlock is NULL, -+* MV_FAIL otherwmise. -+* -+*******************************************************************************/ -+static MV_STATUS twsiDataReceive(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize) -+{ -+ MV_U32 timeout, temp, blockSizeRd = blockSize; -+ if(NULL == pBlock) -+ return MV_BAD_PARAM; -+ -+ /* wait for Int to be Set */ -+ timeout = 0; -+ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataReceive ERROR - Read Data int Time out .\n")) -+ return MV_TIMEOUT; -+ -+ while(blockSizeRd) -+ { -+ if(blockSizeRd == 1) -+ { -+ /* clear ack and Int flag */ -+ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); -+ temp &= ~(TWSI_CONTROL_ACK); -+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp); -+ } -+ twsiIntFlgClr(chanNum); -+ /* wait for Int to be Set */ -+ timeout = 0; -+ while( (!twsiMainIntGet(chanNum)) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataReceive ERROR - Read Data Int Time out .\n")) -+ return MV_TIMEOUT; -+ -+ /* check the status */ -+ temp = twsiStsGet(chanNum); -+ if((temp != TWSI_M_REC_RD_DATA_ACK_TRA) && (blockSizeRd !=1)) -+ { -+ mvOsPrintf("TWSI: twsiDataReceive ERROR - status %x in read trans \n",temp); -+ return MV_FAIL; -+ } -+ else if((temp != TWSI_M_REC_RD_DATA_ACK_NOT_TRA) && (blockSizeRd ==1)) -+ { -+ mvOsPrintf("TWSI: twsiDataReceive ERROR - status %x in Rd Terminate\n",temp); -+ return MV_FAIL; -+ } -+ -+ /* read the data*/ -+ *pBlock = (MV_U8)MV_REG_READ(TWSI_DATA_REG(chanNum)); -+ DB(mvOsPrintf("TWSI: twsiDataReceive place %d read %x \n",\ -+ blockSize - blockSizeRd,*pBlock)); -+ pBlock++; -+ blockSizeRd--; -+ } -+ -+ return MV_OK; -+} -+ -+ -+ -+/******************************************************************************* -+* twsiTargetOffsSet - Set TWST target offset on TWSI bus. -+* -+* DESCRIPTION: -+* The function support TWSI targets that have inside address space (for -+* example EEPROMs). The function: -+* 1) Convert the given offset into pBlock and size. -+* in case the offset should be set to a TWSI slave which support -+* more then 256 bytes offset, the offset setting will be done -+* in 2 transactions. -+* 2) Use twsiDataTransmit to place those on the bus. -+* -+* INPUT: -+* chanNum - TWSI channel -+* offset - offset to be set on the EEPROM device. -+* moreThen256 - whether the EEPROM device support more then 256 byte offset. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK - if setting the offset completed succesfully. -+* MV_FAIL otherwmise. -+* -+*******************************************************************************/ -+static MV_STATUS twsiTargetOffsSet(MV_U8 chanNum, MV_U32 offset, MV_BOOL moreThen256) -+{ -+ MV_U8 offBlock[2]; -+ MV_U32 offSize; -+ -+ if(moreThen256 == MV_TRUE) -+ { -+ offBlock[0] = (offset >> 8) & 0xff; -+ offBlock[1] = offset & 0xff; -+ offSize = 2; -+ } -+ else -+ { -+ offBlock[0] = offset & 0xff; -+ offSize = 1; -+ } -+ DB(mvOsPrintf("TWSI: twsiTargetOffsSet offSize = %x addr1 = %x addr2 = %x\n",\ -+ offSize,offBlock[0],offBlock[1])); -+ return twsiDataTransmit(chanNum, offBlock, offSize); -+ -+} -+ -+/******************************************************************************* -+* mvTwsiRead - Read data block from a TWSI Slave. -+* -+* DESCRIPTION: -+* The function calls the following functions: -+* -) mvTwsiStartBitSet(); -+* if(EEPROM device) -+* -) mvTwsiAddrSet(w); -+* -) twsiTargetOffsSet(); -+* -) mvTwsiStartBitSet(); -+* -) mvTwsiAddrSet(r); -+* -) twsiDataReceive(); -+* -) mvTwsiStopBitSet(); -+* -+* INPUT: -+* chanNum - TWSI channel -+* pTwsiSlave - Twsi Slave structure. -+* blockSize - number of bytes to read. -+* -+* OUTPUT: -+* pBlock - Data block. -+* -+* RETURN: -+* MV_OK - if EEPROM read transaction completed succesfully, -+* MV_BAD_PARAM - if pBlock is NULL, -+* MV_FAIL otherwmise. -+* -+*******************************************************************************/ -+MV_STATUS mvTwsiRead(MV_U8 chanNum, MV_TWSI_SLAVE *pTwsiSlave, MV_U8 *pBlock, MV_U32 blockSize) -+{ -+ if((NULL == pBlock) || (NULL == pTwsiSlave)) -+ return MV_BAD_PARAM; -+ if(MV_OK != mvTwsiStartBitSet(chanNum)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ -+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiStartBitSet\n")); -+ -+ /* in case offset exsist (i.e. eeprom ) */ -+ if(MV_TRUE == pTwsiSlave->validOffset) -+ { -+ if(MV_OK != mvTwsiAddrSet(chanNum, &(pTwsiSlave->slaveAddr), MV_TWSI_WRITE)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiAddrSet\n")); -+ if(MV_OK != twsiTargetOffsSet(chanNum, pTwsiSlave->offset, pTwsiSlave->moreThen256)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after twsiTargetOffsSet\n")); -+ if(MV_OK != mvTwsiStartBitSet(chanNum)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiStartBitSet\n")); -+ } -+ if(MV_OK != mvTwsiAddrSet(chanNum, &(pTwsiSlave->slaveAddr), MV_TWSI_READ)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiAddrSet\n")); -+ if(MV_OK != twsiDataReceive(chanNum, pBlock, blockSize)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after twsiDataReceive\n")); -+ -+ if(MV_OK != mvTwsiStopBitSet(chanNum)) -+ { -+ return MV_FAIL; -+ } -+ -+ twsiAckBitSet(chanNum); -+ -+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiStopBitSet\n")); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvTwsiWrite - Write data block to a TWSI Slave. -+* -+* DESCRIPTION: -+* The function calls the following functions: -+* -) mvTwsiStartBitSet(); -+* -) mvTwsiAddrSet(); -+* -)if(EEPROM device) -+* -) twsiTargetOffsSet(); -+* -) twsiDataTransmit(); -+* -) mvTwsiStopBitSet(); -+* -+* INPUT: -+* chanNum - TWSI channel -+* eepromAddress - eeprom address. -+* blockSize - number of bytes to write. -+* pBlock - Data block. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* MV_OK - if EEPROM read transaction completed succesfully. -+* MV_BAD_PARAM - if pBlock is NULL, -+* MV_FAIL otherwmise. -+* -+* NOTE: Part of the EEPROM, required that the offset will be aligned to the -+* max write burst supported. -+*******************************************************************************/ -+MV_STATUS mvTwsiWrite(MV_U8 chanNum, MV_TWSI_SLAVE *pTwsiSlave, MV_U8 *pBlock, MV_U32 blockSize) -+{ -+ if((NULL == pBlock) || (NULL == pTwsiSlave)) -+ return MV_BAD_PARAM; -+ -+ if(MV_OK != mvTwsiStartBitSet(chanNum)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ -+ DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after mvTwsiStartBitSet\n")); -+ if(MV_OK != mvTwsiAddrSet(chanNum, &(pTwsiSlave->slaveAddr), MV_TWSI_WRITE)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI :mvTwsiEepromWrite after mvTwsiAddrSet\n")); -+ -+ /* in case offset exsist (i.e. eeprom ) */ -+ if(MV_TRUE == pTwsiSlave->validOffset) -+ { -+ if(MV_OK != twsiTargetOffsSet(chanNum, pTwsiSlave->offset, pTwsiSlave->moreThen256)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after twsiTargetOffsSet\n")); -+ } -+ if(MV_OK != twsiDataTransmit(chanNum, pBlock, blockSize)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after twsiDataTransmit\n")); -+ if(MV_OK != mvTwsiStopBitSet(chanNum)) -+ { -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after mvTwsiStopBitSet\n")); -+ -+ return MV_OK; -+} -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,121 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#ifndef __INCmvTwsiH -+#define __INCmvTwsiH -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* need to update this includes */ -+#include "twsi/mvTwsiSpec.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+ -+ -+/* The TWSI interface supports both 7-bit and 10-bit addressing. */ -+/* This enumerator describes addressing type. */ -+typedef enum _mvTwsiAddrType -+{ -+ ADDR7_BIT, /* 7 bit address */ -+ ADDR10_BIT /* 10 bit address */ -+}MV_TWSI_ADDR_TYPE; -+ -+/* This structure describes TWSI address. */ -+typedef struct _mvTwsiAddr -+{ -+ MV_U32 address; /* address */ -+ MV_TWSI_ADDR_TYPE type; /* Address type */ -+}MV_TWSI_ADDR; -+ -+/* This structure describes a TWSI slave. */ -+typedef struct _mvTwsiSlave -+{ -+ MV_TWSI_ADDR slaveAddr; -+ MV_BOOL validOffset; /* whether the slave has offset (i.e. Eeprom etc.) */ -+ MV_U32 offset; /* offset in the slave. */ -+ MV_BOOL moreThen256; /* whether the ofset is bigger then 256 */ -+}MV_TWSI_SLAVE; -+ -+/* This enumerator describes TWSI protocol commands. */ -+typedef enum _mvTwsiCmd -+{ -+ MV_TWSI_WRITE, /* TWSI write command - 0 according to spec */ -+ MV_TWSI_READ /* TWSI read command - 1 according to spec */ -+}MV_TWSI_CMD; -+ -+MV_STATUS mvTwsiStartBitSet(MV_U8 chanNum); -+MV_STATUS mvTwsiStopBitSet(MV_U8 chanNum); -+MV_STATUS mvTwsiAddrSet(MV_U8 chanNum, MV_TWSI_ADDR *twsiAddr, MV_TWSI_CMD command); -+ -+MV_U32 mvTwsiInit(MV_U8 chanNum, MV_KHZ frequancy, MV_U32 Tclk, MV_TWSI_ADDR *twsiAddr, MV_BOOL generalCallEnable); -+MV_STATUS mvTwsiRead (MV_U8 chanNum, MV_TWSI_SLAVE *twsiSlave, MV_U8 *pBlock, MV_U32 blockSize); -+MV_STATUS mvTwsiWrite(MV_U8 chanNum, MV_TWSI_SLAVE *twsiSlave, MV_U8 *pBlock, MV_U32 blockSize); -+ -+ -+#ifdef __cplusplus -+} -+#endif /* __cplusplus */ -+ -+#endif /* __INCmvTwsiH */ -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiSpec.h linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiSpec.h ---- linux-2.6.39.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiSpec.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiSpec.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,160 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+/****************************************/ -+/* TWSI Registers */ -+/****************************************/ -+#ifndef __INCmvTwsiSpech -+#define __INCmvTwsiSpech -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* defines */ -+#define TWSI_SLAVE_ADDR_REG(chanNum) (TWSI_SLAVE_BASE(chanNum)+ 0x00) -+ -+#define TWSI_SLAVE_ADDR_GCE_ENA BIT0 -+#define TWSI_SLAVE_ADDR_7BIT_OFFS 0x1 -+#define TWSI_SLAVE_ADDR_7BIT_MASK (0xFF << TWSI_SLAVE_ADDR_7BIT_OFFS) -+#define TWSI_SLAVE_ADDR_10BIT_OFFS 0x7 -+#define TWSI_SLAVE_ADDR_10BIT_MASK 0x300 -+#define TWSI_SLAVE_ADDR_10BIT_CONST 0xF0 -+ -+ -+#define TWSI_EXTENDED_SLAVE_ADDR_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x10) -+#define TWSI_EXTENDED_SLAVE_OFFS 0 -+#define TWSI_EXTENDED_SLAVE_MASK (0xFF << TWSI_EXTENDED_SLAVE_OFFS) -+ -+ -+#define TWSI_DATA_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x04) -+#define TWSI_DATA_COMMAND_OFFS 0x0 -+#define TWSI_DATA_COMMAND_MASK (0x1 << TWSI_DATA_COMMAND_OFFS) -+#define TWSI_DATA_COMMAND_WR (0x1 << TWSI_DATA_COMMAND_OFFS) -+#define TWSI_DATA_COMMAND_RD (0x0 << TWSI_DATA_COMMAND_OFFS) -+#define TWSI_DATA_ADDR_7BIT_OFFS 0x1 -+#define TWSI_DATA_ADDR_7BIT_MASK (0xFF << TWSI_DATA_ADDR_7BIT_OFFS) -+#define TWSI_DATA_ADDR_10BIT_OFFS 0x7 -+#define TWSI_DATA_ADDR_10BIT_MASK 0x300 -+#define TWSI_DATA_ADDR_10BIT_CONST 0xF0 -+ -+ -+#define TWSI_CONTROL_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x08) -+#define TWSI_CONTROL_ACK BIT2 -+#define TWSI_CONTROL_INT_FLAG_SET BIT3 -+#define TWSI_CONTROL_STOP_BIT BIT4 -+#define TWSI_CONTROL_START_BIT BIT5 -+#define TWSI_CONTROL_ENA BIT6 -+#define TWSI_CONTROL_INT_ENA BIT7 -+ -+ -+#define TWSI_STATUS_BAUDE_RATE_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x0c) -+#define TWSI_BAUD_RATE_N_OFFS 0 -+#define TWSI_BAUD_RATE_N_MASK (0x7 << TWSI_BAUD_RATE_N_OFFS) -+#define TWSI_BAUD_RATE_M_OFFS 3 -+#define TWSI_BAUD_RATE_M_MASK (0xF << TWSI_BAUD_RATE_M_OFFS) -+ -+#define TWSI_SOFT_RESET_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x1c) -+ -+/* defines */ -+#define TWSI_TIMEOUT_VALUE 0x500 -+ -+/* TWSI status codes */ -+#define TWSI_BUS_ERROR 0x00 -+#define TWSI_START_CON_TRA 0x08 -+#define TWSI_REPEATED_START_CON_TRA 0x10 -+#define TWSI_AD_PLS_WR_BIT_TRA_ACK_REC 0x18 -+#define TWSI_AD_PLS_WR_BIT_TRA_ACK_NOT_REC 0x20 -+#define TWSI_M_TRAN_DATA_BYTE_ACK_REC 0x28 -+#define TWSI_M_TRAN_DATA_BYTE_ACK_NOT_REC 0x30 -+#define TWSI_M_LOST_ARB_DUR_AD_OR_DATA_TRA 0x38 -+#define TWSI_AD_PLS_RD_BIT_TRA_ACK_REC 0x40 -+#define TWSI_AD_PLS_RD_BIT_TRA_ACK_NOT_REC 0x48 -+#define TWSI_M_REC_RD_DATA_ACK_TRA 0x50 -+#define TWSI_M_REC_RD_DATA_ACK_NOT_TRA 0x58 -+#define TWSI_SLA_REC_AD_PLS_WR_BIT_ACK_TRA 0x60 -+#define TWSI_M_LOST_ARB_DUR_AD_TRA_AD_IS_TRGT_TO_SLA_ACK_TRA_W 0x68 -+#define TWSI_GNL_CALL_REC_ACK_TRA 0x70 -+#define TWSI_M_LOST_ARB_DUR_AD_TRA_GNL_CALL_AD_REC_ACK_TRA 0x78 -+#define TWSI_SLA_REC_WR_DATA_AF_REC_SLA_AD_ACK_TRAN 0x80 -+#define TWSI_SLA_REC_WR_DATA_AF_REC_SLA_AD_ACK_NOT_TRAN 0x88 -+#define TWSI_SLA_REC_WR_DATA_AF_REC_GNL_CALL_ACK_TRAN 0x90 -+#define TWSI_SLA_REC_WR_DATA_AF_REC_GNL_CALL_ACK_NOT_TRAN 0x98 -+#define TWSI_SLA_REC_STOP_OR_REPEATED_STRT_CON 0xA0 -+#define TWSI_SLA_REC_AD_PLS_RD_BIT_ACK_TRA 0xA8 -+#define TWSI_M_LOST_ARB_DUR_AD_TRA_AD_IS_TRGT_TO_SLA_ACK_TRA_R 0xB0 -+#define TWSI_SLA_TRA_RD_DATA_ACK_REC 0xB8 -+#define TWSI_SLA_TRA_RD_DATA_ACK_NOT_REC 0xC0 -+#define TWSI_SLA_TRA_LAST_RD_DATA_ACK_REC 0xC8 -+#define TWSI_SEC_AD_PLS_WR_BIT_TRA_ACK_REC 0xD0 -+#define TWSI_SEC_AD_PLS_WR_BIT_TRA_ACK_NOT_REC 0xD8 -+#define TWSI_SEC_AD_PLS_RD_BIT_TRA_ACK_REC 0xE0 -+#define TWSI_SEC_AD_PLS_RD_BIT_TRA_ACK_NOT_REC 0xE8 -+#define TWSI_NO_REL_STS_INT_FLAG_IS_KEPT_0 0xF8 -+ -+ -+#ifdef __cplusplus -+} -+#endif /* __cplusplus */ -+ -+#endif /* __INCmvTwsiSpech */ -diff -Nur linux-2.6.39.orig/crypto/ocf/ocf-bench.c linux-2.6.39/crypto/ocf/ocf-bench.c ---- linux-2.6.39.orig/crypto/ocf/ocf-bench.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/ocf-bench.c 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,436 @@ -+/* -+ * A loadable module that benchmarks the OCF crypto speed from kernel space. -+ * -+ * Copyright (C) 2004-2010 David McCullough -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * ALTERNATIVELY, provided that this notice is retained in full, this product -+ * may be distributed under the terms of the GNU General Public License (GPL), -+ * in which case the provisions of the GPL apply INSTEAD OF those given above. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ */ -+ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#ifdef I_HAVE_AN_XSCALE_WITH_INTEL_SDK -+#define BENCH_IXP_ACCESS_LIB 1 -+#endif -+#ifdef BENCH_IXP_ACCESS_LIB -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#endif -+ -+/* -+ * support for access lib version 1.4 -+ */ -+#ifndef IX_MBUF_PRIV -+#define IX_MBUF_PRIV(x) ((x)->priv) -+#endif -+ -+/* -+ * the number of simultaneously active requests -+ */ -+static int request_q_len = 20; -+module_param(request_q_len, int, 0); -+MODULE_PARM_DESC(request_q_len, "Number of outstanding requests"); -+/* -+ * how many requests we want to have processed -+ */ -+static int request_num = 1024; -+module_param(request_num, int, 0); -+MODULE_PARM_DESC(request_num, "run for at least this many requests"); -+/* -+ * the size of each request -+ */ -+static int request_size = 1500; -+module_param(request_size, int, 0); -+MODULE_PARM_DESC(request_size, "size of each request"); -+ -+/* -+ * a structure for each request -+ */ -+typedef struct { -+ struct work_struct work; -+#ifdef BENCH_IXP_ACCESS_LIB -+ IX_MBUF mbuf; -+#endif -+ unsigned char *buffer; -+} request_t; -+ -+static request_t *requests; -+ -+static int outstanding; -+static int total; -+ -+/*************************************************************************/ -+/* -+ * OCF benchmark routines -+ */ -+ -+static uint64_t ocf_cryptoid; -+static int ocf_init(void); -+static int ocf_cb(struct cryptop *crp); -+static void ocf_request(void *arg); -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void ocf_request_wq(struct work_struct *work); -+#endif -+ -+static int -+ocf_init(void) -+{ -+ int error; -+ struct cryptoini crie, cria; -+ struct cryptodesc crda, crde; -+ -+ memset(&crie, 0, sizeof(crie)); -+ memset(&cria, 0, sizeof(cria)); -+ memset(&crde, 0, sizeof(crde)); -+ memset(&crda, 0, sizeof(crda)); -+ -+ cria.cri_alg = CRYPTO_SHA1_HMAC; -+ cria.cri_klen = 20 * 8; -+ cria.cri_key = "0123456789abcdefghij"; -+ -+ crie.cri_alg = CRYPTO_3DES_CBC; -+ crie.cri_klen = 24 * 8; -+ crie.cri_key = "0123456789abcdefghijklmn"; -+ -+ crie.cri_next = &cria; -+ -+ error = crypto_newsession(&ocf_cryptoid, &crie, 0); -+ if (error) { -+ printk("crypto_newsession failed %d\n", error); -+ return -1; -+ } -+ return 0; -+} -+ -+static int -+ocf_cb(struct cryptop *crp) -+{ -+ request_t *r = (request_t *) crp->crp_opaque; -+ -+ if (crp->crp_etype) -+ printk("Error in OCF processing: %d\n", crp->crp_etype); -+ total++; -+ crypto_freereq(crp); -+ crp = NULL; -+ -+ if (total > request_num) { -+ outstanding--; -+ return 0; -+ } -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ INIT_WORK(&r->work, ocf_request_wq); -+#else -+ INIT_WORK(&r->work, ocf_request, r); -+#endif -+ schedule_work(&r->work); -+ return 0; -+} -+ -+ -+static void -+ocf_request(void *arg) -+{ -+ request_t *r = arg; -+ struct cryptop *crp = crypto_getreq(2); -+ struct cryptodesc *crde, *crda; -+ -+ if (!crp) { -+ outstanding--; -+ return; -+ } -+ -+ crde = crp->crp_desc; -+ crda = crde->crd_next; -+ -+ crda->crd_skip = 0; -+ crda->crd_flags = 0; -+ crda->crd_len = request_size; -+ crda->crd_inject = request_size; -+ crda->crd_alg = CRYPTO_SHA1_HMAC; -+ crda->crd_key = "0123456789abcdefghij"; -+ crda->crd_klen = 20 * 8; -+ -+ crde->crd_skip = 0; -+ crde->crd_flags = CRD_F_IV_EXPLICIT | CRD_F_ENCRYPT; -+ crde->crd_len = request_size; -+ crde->crd_inject = request_size; -+ crde->crd_alg = CRYPTO_3DES_CBC; -+ crde->crd_key = "0123456789abcdefghijklmn"; -+ crde->crd_klen = 24 * 8; -+ -+ crp->crp_ilen = request_size + 64; -+ crp->crp_flags = CRYPTO_F_CBIMM; -+ crp->crp_buf = (caddr_t) r->buffer; -+ crp->crp_callback = ocf_cb; -+ crp->crp_sid = ocf_cryptoid; -+ crp->crp_opaque = (caddr_t) r; -+ crypto_dispatch(crp); -+} -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void -+ocf_request_wq(struct work_struct *work) -+{ -+ request_t *r = container_of(work, request_t, work); -+ ocf_request(r); -+} -+#endif -+ -+/*************************************************************************/ -+#ifdef BENCH_IXP_ACCESS_LIB -+/*************************************************************************/ -+/* -+ * CryptoAcc benchmark routines -+ */ -+ -+static IxCryptoAccCtx ixp_ctx; -+static UINT32 ixp_ctx_id; -+static IX_MBUF ixp_pri; -+static IX_MBUF ixp_sec; -+static int ixp_registered = 0; -+ -+static void ixp_register_cb(UINT32 ctx_id, IX_MBUF *bufp, -+ IxCryptoAccStatus status); -+static void ixp_perform_cb(UINT32 ctx_id, IX_MBUF *sbufp, IX_MBUF *dbufp, -+ IxCryptoAccStatus status); -+static void ixp_request(void *arg); -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void ixp_request_wq(struct work_struct *work); -+#endif -+ -+static int -+ixp_init(void) -+{ -+ IxCryptoAccStatus status; -+ -+ ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_3DES; -+ ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; -+ ixp_ctx.cipherCtx.cipherKeyLen = 24; -+ ixp_ctx.cipherCtx.cipherBlockLen = IX_CRYPTO_ACC_DES_BLOCK_64; -+ ixp_ctx.cipherCtx.cipherInitialVectorLen = IX_CRYPTO_ACC_DES_IV_64; -+ memcpy(ixp_ctx.cipherCtx.key.cipherKey, "0123456789abcdefghijklmn", 24); -+ -+ ixp_ctx.authCtx.authAlgo = IX_CRYPTO_ACC_AUTH_SHA1; -+ ixp_ctx.authCtx.authDigestLen = 12; -+ ixp_ctx.authCtx.aadLen = 0; -+ ixp_ctx.authCtx.authKeyLen = 20; -+ memcpy(ixp_ctx.authCtx.key.authKey, "0123456789abcdefghij", 20); -+ -+ ixp_ctx.useDifferentSrcAndDestMbufs = 0; -+ ixp_ctx.operation = IX_CRYPTO_ACC_OP_ENCRYPT_AUTH ; -+ -+ IX_MBUF_MLEN(&ixp_pri) = IX_MBUF_PKT_LEN(&ixp_pri) = 128; -+ IX_MBUF_MDATA(&ixp_pri) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); -+ IX_MBUF_MLEN(&ixp_sec) = IX_MBUF_PKT_LEN(&ixp_sec) = 128; -+ IX_MBUF_MDATA(&ixp_sec) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); -+ -+ status = ixCryptoAccCtxRegister(&ixp_ctx, &ixp_pri, &ixp_sec, -+ ixp_register_cb, ixp_perform_cb, &ixp_ctx_id); -+ -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) { -+ while (!ixp_registered) -+ schedule(); -+ return ixp_registered < 0 ? -1 : 0; -+ } -+ -+ printk("ixp: ixCryptoAccCtxRegister failed %d\n", status); -+ return -1; -+} -+ -+static void -+ixp_register_cb(UINT32 ctx_id, IX_MBUF *bufp, IxCryptoAccStatus status) -+{ -+ if (bufp) { -+ IX_MBUF_MLEN(bufp) = IX_MBUF_PKT_LEN(bufp) = 0; -+ kfree(IX_MBUF_MDATA(bufp)); -+ IX_MBUF_MDATA(bufp) = NULL; -+ } -+ -+ if (IX_CRYPTO_ACC_STATUS_WAIT == status) -+ return; -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) -+ ixp_registered = 1; -+ else -+ ixp_registered = -1; -+} -+ -+static void -+ixp_perform_cb( -+ UINT32 ctx_id, -+ IX_MBUF *sbufp, -+ IX_MBUF *dbufp, -+ IxCryptoAccStatus status) -+{ -+ request_t *r = NULL; -+ -+ total++; -+ if (total > request_num) { -+ outstanding--; -+ return; -+ } -+ -+ if (!sbufp || !(r = IX_MBUF_PRIV(sbufp))) { -+ printk("crappo %p %p\n", sbufp, r); -+ outstanding--; -+ return; -+ } -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ INIT_WORK(&r->work, ixp_request_wq); -+#else -+ INIT_WORK(&r->work, ixp_request, r); -+#endif -+ schedule_work(&r->work); -+} -+ -+static void -+ixp_request(void *arg) -+{ -+ request_t *r = arg; -+ IxCryptoAccStatus status; -+ -+ memset(&r->mbuf, 0, sizeof(r->mbuf)); -+ IX_MBUF_MLEN(&r->mbuf) = IX_MBUF_PKT_LEN(&r->mbuf) = request_size + 64; -+ IX_MBUF_MDATA(&r->mbuf) = r->buffer; -+ IX_MBUF_PRIV(&r->mbuf) = r; -+ status = ixCryptoAccAuthCryptPerform(ixp_ctx_id, &r->mbuf, NULL, -+ 0, request_size, 0, request_size, request_size, r->buffer); -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS != status) { -+ printk("status1 = %d\n", status); -+ outstanding--; -+ return; -+ } -+ return; -+} -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void -+ixp_request_wq(struct work_struct *work) -+{ -+ request_t *r = container_of(work, request_t, work); -+ ixp_request(r); -+} -+#endif -+ -+/*************************************************************************/ -+#endif /* BENCH_IXP_ACCESS_LIB */ -+/*************************************************************************/ -+ -+int -+ocfbench_init(void) -+{ -+ int i, jstart, jstop; -+ -+ printk("Crypto Speed tests\n"); -+ -+ requests = kmalloc(sizeof(request_t) * request_q_len, GFP_KERNEL); -+ if (!requests) { -+ printk("malloc failed\n"); -+ return -EINVAL; -+ } -+ -+ for (i = 0; i < request_q_len; i++) { -+ /* +64 for return data */ -+ requests[i].buffer = kmalloc(request_size + 128, GFP_DMA); -+ if (!requests[i].buffer) { -+ printk("malloc failed\n"); -+ return -EINVAL; -+ } -+ memset(requests[i].buffer, '0' + i, request_size + 128); -+ } -+ -+ /* -+ * OCF benchmark -+ */ -+ printk("OCF: testing ...\n"); -+ ocf_init(); -+ total = outstanding = 0; -+ jstart = jiffies; -+ for (i = 0; i < request_q_len; i++) { -+ outstanding++; -+ ocf_request(&requests[i]); -+ } -+ while (outstanding > 0) -+ schedule(); -+ jstop = jiffies; -+ -+ printk("OCF: %d requests of %d bytes in %d jiffies\n", total, request_size, -+ jstop - jstart); -+ -+#ifdef BENCH_IXP_ACCESS_LIB -+ /* -+ * IXP benchmark -+ */ -+ printk("IXP: testing ...\n"); -+ ixp_init(); -+ total = outstanding = 0; -+ jstart = jiffies; -+ for (i = 0; i < request_q_len; i++) { -+ outstanding++; -+ ixp_request(&requests[i]); -+ } -+ while (outstanding > 0) -+ schedule(); -+ jstop = jiffies; -+ -+ printk("IXP: %d requests of %d bytes in %d jiffies\n", total, request_size, -+ jstop - jstart); -+#endif /* BENCH_IXP_ACCESS_LIB */ -+ -+ for (i = 0; i < request_q_len; i++) -+ kfree(requests[i].buffer); -+ kfree(requests); -+ return -EINVAL; /* always fail to load so it can be re-run quickly ;-) */ -+} -+ -+static void __exit ocfbench_exit(void) -+{ -+} -+ -+module_init(ocfbench_init); -+module_exit(ocfbench_exit); -+ -+MODULE_LICENSE("BSD"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("Benchmark various in-kernel crypto speeds"); -diff -Nur linux-2.6.39.orig/crypto/ocf/ocf-compat.h linux-2.6.39/crypto/ocf/ocf-compat.h ---- linux-2.6.39.orig/crypto/ocf/ocf-compat.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/ocf-compat.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,294 @@ -+#ifndef _BSD_COMPAT_H_ -+#define _BSD_COMPAT_H_ 1 -+/****************************************************************************/ -+/* -+ * Provide compat routines for older linux kernels and BSD kernels -+ * -+ * Written by David McCullough -+ * Copyright (C) 2010 David McCullough -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * ALTERNATIVELY, provided that this notice is retained in full, this file -+ * may be distributed under the terms of the GNU General Public License (GPL), -+ * in which case the provisions of the GPL apply INSTEAD OF those given above. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ */ -+/****************************************************************************/ -+#ifdef __KERNEL__ -+/* -+ * fake some BSD driver interface stuff specifically for OCF use -+ */ -+ -+typedef struct ocf_device *device_t; -+ -+typedef struct { -+ int (*cryptodev_newsession)(device_t dev, u_int32_t *sidp, struct cryptoini *cri); -+ int (*cryptodev_freesession)(device_t dev, u_int64_t tid); -+ int (*cryptodev_process)(device_t dev, struct cryptop *crp, int hint); -+ int (*cryptodev_kprocess)(device_t dev, struct cryptkop *krp, int hint); -+} device_method_t; -+#define DEVMETHOD(id, func) id: func -+ -+struct ocf_device { -+ char name[32]; /* the driver name */ -+ char nameunit[32]; /* the driver name + HW instance */ -+ int unit; -+ device_method_t methods; -+ void *softc; -+}; -+ -+#define CRYPTODEV_NEWSESSION(dev, sid, cri) \ -+ ((*(dev)->methods.cryptodev_newsession)(dev,sid,cri)) -+#define CRYPTODEV_FREESESSION(dev, sid) \ -+ ((*(dev)->methods.cryptodev_freesession)(dev, sid)) -+#define CRYPTODEV_PROCESS(dev, crp, hint) \ -+ ((*(dev)->methods.cryptodev_process)(dev, crp, hint)) -+#define CRYPTODEV_KPROCESS(dev, krp, hint) \ -+ ((*(dev)->methods.cryptodev_kprocess)(dev, krp, hint)) -+ -+#define device_get_name(dev) ((dev)->name) -+#define device_get_nameunit(dev) ((dev)->nameunit) -+#define device_get_unit(dev) ((dev)->unit) -+#define device_get_softc(dev) ((dev)->softc) -+ -+#define softc_device_decl \ -+ struct ocf_device _device; \ -+ device_t -+ -+#define softc_device_init(_sc, _name, _unit, _methods) \ -+ if (1) {\ -+ strncpy((_sc)->_device.name, _name, sizeof((_sc)->_device.name) - 1); \ -+ snprintf((_sc)->_device.nameunit, sizeof((_sc)->_device.name), "%s%d", _name, _unit); \ -+ (_sc)->_device.unit = _unit; \ -+ (_sc)->_device.methods = _methods; \ -+ (_sc)->_device.softc = (void *) _sc; \ -+ *(device_t *)((softc_get_device(_sc))+1) = &(_sc)->_device; \ -+ } else -+ -+#define softc_get_device(_sc) (&(_sc)->_device) -+ -+/* -+ * iomem support for 2.4 and 2.6 kernels -+ */ -+#include -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+#define ocf_iomem_t unsigned long -+ -+/* -+ * implement simple workqueue like support for older kernels -+ */ -+ -+#include -+ -+#define work_struct tq_struct -+ -+#define INIT_WORK(wp, fp, ap) \ -+ do { \ -+ (wp)->sync = 0; \ -+ (wp)->routine = (fp); \ -+ (wp)->data = (ap); \ -+ } while (0) -+ -+#define schedule_work(wp) \ -+ do { \ -+ queue_task((wp), &tq_immediate); \ -+ mark_bh(IMMEDIATE_BH); \ -+ } while (0) -+ -+#define flush_scheduled_work() run_task_queue(&tq_immediate) -+ -+#else -+#define ocf_iomem_t void __iomem * -+ -+#include -+ -+#endif -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26) -+#include -+#elif LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) -+#define files_fdtable(files) (files) -+#endif -+ -+#ifdef MODULE_PARM -+#undef module_param /* just in case */ -+#define module_param(a,b,c) MODULE_PARM(a,"i") -+#endif -+ -+#define bzero(s,l) memset(s,0,l) -+#define bcopy(s,d,l) memcpy(d,s,l) -+#define bcmp(x, y, l) memcmp(x,y,l) -+ -+#define MIN(x,y) ((x) < (y) ? (x) : (y)) -+ -+#define device_printf(dev, a...) ({ \ -+ printk("%s: ", device_get_nameunit(dev)); printk(a); \ -+ }) -+ -+#undef printf -+#define printf(fmt...) printk(fmt) -+ -+#define KASSERT(c,p) if (!(c)) { printk p ; } else -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+#define ocf_daemonize(str) \ -+ daemonize(); \ -+ spin_lock_irq(¤t->sigmask_lock); \ -+ sigemptyset(¤t->blocked); \ -+ recalc_sigpending(current); \ -+ spin_unlock_irq(¤t->sigmask_lock); \ -+ sprintf(current->comm, str); -+#else -+#define ocf_daemonize(str) daemonize(str); -+#endif -+ -+#define TAILQ_INSERT_TAIL(q,d,m) list_add_tail(&(d)->m, (q)) -+#define TAILQ_EMPTY(q) list_empty(q) -+#define TAILQ_FOREACH(v, q, m) list_for_each_entry(v, q, m) -+ -+#define read_random(p,l) get_random_bytes(p,l) -+ -+#define DELAY(x) ((x) > 2000 ? mdelay((x)/1000) : udelay(x)) -+#define strtoul simple_strtoul -+ -+#define pci_get_vendor(dev) ((dev)->vendor) -+#define pci_get_device(dev) ((dev)->device) -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+#define pci_set_consistent_dma_mask(dev, mask) (0) -+#endif -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10) -+#define pci_dma_sync_single_for_cpu pci_dma_sync_single -+#endif -+ -+#ifndef DMA_32BIT_MASK -+#define DMA_32BIT_MASK 0x00000000ffffffffULL -+#endif -+ -+#ifndef htole32 -+#define htole32(x) cpu_to_le32(x) -+#endif -+#ifndef htobe32 -+#define htobe32(x) cpu_to_be32(x) -+#endif -+#ifndef htole16 -+#define htole16(x) cpu_to_le16(x) -+#endif -+#ifndef htobe16 -+#define htobe16(x) cpu_to_be16(x) -+#endif -+ -+/* older kernels don't have these */ -+ -+#include -+#if !defined(IRQ_NONE) && !defined(IRQ_RETVAL) -+#define IRQ_NONE -+#define IRQ_HANDLED -+#define IRQ_WAKE_THREAD -+#define IRQ_RETVAL -+#define irqreturn_t void -+typedef irqreturn_t (*irq_handler_t)(int irq, void *arg, struct pt_regs *regs); -+#endif -+#ifndef IRQF_SHARED -+#define IRQF_SHARED SA_SHIRQ -+#endif -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) -+# define strlcpy(dest,src,len) \ -+ ({strncpy(dest,src,(len)-1); ((char *)dest)[(len)-1] = '\0'; }) -+#endif -+ -+#ifndef MAX_ERRNO -+#define MAX_ERRNO 4095 -+#endif -+#ifndef IS_ERR_VALUE -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,5) -+#include -+#endif -+#ifndef IS_ERR_VALUE -+#define IS_ERR_VALUE(x) ((unsigned long)(x) >= (unsigned long)-MAX_ERRNO) -+#endif -+#endif -+ -+/* -+ * common debug for all -+ */ -+#if 1 -+#define dprintk(a...) do { if (debug) printk(a); } while(0) -+#else -+#define dprintk(a...) -+#endif -+ -+#ifndef SLAB_ATOMIC -+/* Changed in 2.6.20, must use GFP_ATOMIC now */ -+#define SLAB_ATOMIC GFP_ATOMIC -+#endif -+ -+/* -+ * need some additional support for older kernels */ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,2) -+#define pci_register_driver_compat(driver, rc) \ -+ do { \ -+ if ((rc) > 0) { \ -+ (rc) = 0; \ -+ } else if (rc == 0) { \ -+ (rc) = -ENODEV; \ -+ } else { \ -+ pci_unregister_driver(driver); \ -+ } \ -+ } while (0) -+#elif LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10) -+#define pci_register_driver_compat(driver,rc) ((rc) = (rc) < 0 ? (rc) : 0) -+#else -+#define pci_register_driver_compat(driver,rc) -+#endif -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) -+ -+#include -+#include -+ -+static inline void sg_set_page(struct scatterlist *sg, struct page *page, -+ unsigned int len, unsigned int offset) -+{ -+ sg->page = page; -+ sg->offset = offset; -+ sg->length = len; -+} -+ -+static inline void *sg_virt(struct scatterlist *sg) -+{ -+ return page_address(sg->page) + sg->offset; -+} -+ -+#define sg_init_table(sg, n) -+ -+#endif -+ -+#ifndef late_initcall -+#define late_initcall(init) module_init(init) -+#endif -+ -+#endif /* __KERNEL__ */ -+ -+/****************************************************************************/ -+#endif /* _BSD_COMPAT_H_ */ -diff -Nur linux-2.6.39.orig/crypto/ocf/ocfnull/Makefile linux-2.6.39/crypto/ocf/ocfnull/Makefile ---- linux-2.6.39.orig/crypto/ocf/ocfnull/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/ocfnull/Makefile 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,12 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+obj-$(CONFIG_OCF_OCFNULL) += ocfnull.o -+ -+obj ?= . -+EXTRA_CFLAGS += -I$(obj)/.. -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/ocfnull/ocfnull.c linux-2.6.39/crypto/ocf/ocfnull/ocfnull.c ---- linux-2.6.39.orig/crypto/ocf/ocfnull/ocfnull.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/ocfnull/ocfnull.c 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,203 @@ -+/* -+ * An OCF module for determining the cost of crypto versus the cost of -+ * IPSec processing outside of OCF. This modules gives us the effect of -+ * zero cost encryption, of course you will need to run it at both ends -+ * since it does no crypto at all. -+ * -+ * Written by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * ALTERNATIVELY, provided that this notice is retained in full, this product -+ * may be distributed under the terms of the GNU General Public License (GPL), -+ * in which case the provisions of the GPL apply INSTEAD OF those given above. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ */ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+static int32_t null_id = -1; -+static u_int32_t null_sesnum = 0; -+ -+static int null_process(device_t, struct cryptop *, int); -+static int null_newsession(device_t, u_int32_t *, struct cryptoini *); -+static int null_freesession(device_t, u_int64_t); -+ -+#define debug ocfnull_debug -+int ocfnull_debug = 0; -+module_param(ocfnull_debug, int, 0644); -+MODULE_PARM_DESC(ocfnull_debug, "Enable debug"); -+ -+/* -+ * dummy device structure -+ */ -+ -+static struct { -+ softc_device_decl sc_dev; -+} nulldev; -+ -+static device_method_t null_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, null_newsession), -+ DEVMETHOD(cryptodev_freesession,null_freesession), -+ DEVMETHOD(cryptodev_process, null_process), -+}; -+ -+/* -+ * Generate a new software session. -+ */ -+static int -+null_newsession(device_t arg, u_int32_t *sid, struct cryptoini *cri) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid == NULL || cri == NULL) { -+ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ if (null_sesnum == 0) -+ null_sesnum++; -+ *sid = null_sesnum++; -+ return 0; -+} -+ -+ -+/* -+ * Free a session. -+ */ -+static int -+null_freesession(device_t arg, u_int64_t tid) -+{ -+ u_int32_t sid = CRYPTO_SESID2LID(tid); -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid > null_sesnum) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ /* Silently accept and return */ -+ if (sid == 0) -+ return 0; -+ return 0; -+} -+ -+ -+/* -+ * Process a request. -+ */ -+static int -+null_process(device_t arg, struct cryptop *crp, int hint) -+{ -+ unsigned int lid; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ /* Sanity check */ -+ if (crp == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ crp->crp_etype = 0; -+ -+ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ /* -+ * find the session we are using -+ */ -+ -+ lid = crp->crp_sid & 0xffffffff; -+ if (lid >= null_sesnum || lid == 0) { -+ crp->crp_etype = ENOENT; -+ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); -+ goto done; -+ } -+ -+done: -+ crypto_done(crp); -+ return 0; -+} -+ -+ -+/* -+ * our driver startup and shutdown routines -+ */ -+ -+static int -+null_init(void) -+{ -+ dprintk("%s(%p)\n", __FUNCTION__, null_init); -+ -+ memset(&nulldev, 0, sizeof(nulldev)); -+ softc_device_init(&nulldev, "ocfnull", 0, null_methods); -+ -+ null_id = crypto_get_driverid(softc_get_device(&nulldev), -+ CRYPTOCAP_F_HARDWARE); -+ if (null_id < 0) -+ panic("ocfnull: crypto device cannot initialize!"); -+ -+#define REGISTER(alg) \ -+ crypto_register(null_id,alg,0,0) -+ REGISTER(CRYPTO_DES_CBC); -+ REGISTER(CRYPTO_3DES_CBC); -+ REGISTER(CRYPTO_RIJNDAEL128_CBC); -+ REGISTER(CRYPTO_MD5); -+ REGISTER(CRYPTO_SHA1); -+ REGISTER(CRYPTO_MD5_HMAC); -+ REGISTER(CRYPTO_SHA1_HMAC); -+#undef REGISTER -+ -+ return 0; -+} -+ -+static void -+null_exit(void) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ crypto_unregister_all(null_id); -+ null_id = -1; -+} -+ -+module_init(null_init); -+module_exit(null_exit); -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("ocfnull - claims a lot but does nothing"); -diff -Nur linux-2.6.39.orig/crypto/ocf/pasemi/Makefile linux-2.6.39/crypto/ocf/pasemi/Makefile ---- linux-2.6.39.orig/crypto/ocf/pasemi/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/pasemi/Makefile 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,12 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+obj-$(CONFIG_OCF_PASEMI) += pasemi.o -+ -+obj ?= . -+EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/pasemi/pasemi.c linux-2.6.39/crypto/ocf/pasemi/pasemi.c ---- linux-2.6.39.orig/crypto/ocf/pasemi/pasemi.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/pasemi/pasemi.c 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,1009 @@ -+/* -+ * Copyright (C) 2007 PA Semi, Inc -+ * -+ * Driver for the PA Semi PWRficient DMA Crypto Engine -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "pasemi_fnu.h" -+ -+#define DRV_NAME "pasemi" -+ -+#define TIMER_INTERVAL 1000 -+ -+static void __devexit pasemi_dma_remove(struct pci_dev *pdev); -+static struct pasdma_status volatile * dma_status; -+ -+static int debug; -+module_param(debug, int, 0644); -+MODULE_PARM_DESC(debug, "Enable debug"); -+ -+static void pasemi_desc_start(struct pasemi_desc *desc, u64 hdr) -+{ -+ desc->postop = 0; -+ desc->quad[0] = hdr; -+ desc->quad_cnt = 1; -+ desc->size = 1; -+} -+ -+static void pasemi_desc_build(struct pasemi_desc *desc, u64 val) -+{ -+ desc->quad[desc->quad_cnt++] = val; -+ desc->size = (desc->quad_cnt + 1) / 2; -+} -+ -+static void pasemi_desc_hdr(struct pasemi_desc *desc, u64 hdr) -+{ -+ desc->quad[0] |= hdr; -+} -+ -+static int pasemi_desc_size(struct pasemi_desc *desc) -+{ -+ return desc->size; -+} -+ -+static void pasemi_ring_add_desc( -+ struct pasemi_fnu_txring *ring, -+ struct pasemi_desc *desc, -+ struct cryptop *crp) { -+ int i; -+ int ring_index = 2 * (ring->next_to_fill & (TX_RING_SIZE-1)); -+ -+ TX_DESC_INFO(ring, ring->next_to_fill).desc_size = desc->size; -+ TX_DESC_INFO(ring, ring->next_to_fill).desc_postop = desc->postop; -+ TX_DESC_INFO(ring, ring->next_to_fill).cf_crp = crp; -+ -+ for (i = 0; i < desc->quad_cnt; i += 2) { -+ ring_index = 2 * (ring->next_to_fill & (TX_RING_SIZE-1)); -+ ring->desc[ring_index] = desc->quad[i]; -+ ring->desc[ring_index + 1] = desc->quad[i + 1]; -+ ring->next_to_fill++; -+ } -+ -+ if (desc->quad_cnt & 1) -+ ring->desc[ring_index + 1] = 0; -+} -+ -+static void pasemi_ring_incr(struct pasemi_softc *sc, int chan_index, int incr) -+{ -+ out_le32(sc->dma_regs + PAS_DMA_TXCHAN_INCR(sc->base_chan + chan_index), -+ incr); -+} -+ -+/* -+ * Generate a new software session. -+ */ -+static int -+pasemi_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) -+{ -+ struct cryptoini *c, *encini = NULL, *macini = NULL; -+ struct pasemi_softc *sc = device_get_softc(dev); -+ struct pasemi_session *ses = NULL, **sespp; -+ int sesn, blksz = 0; -+ u64 ccmd = 0; -+ unsigned long flags; -+ struct pasemi_desc init_desc; -+ struct pasemi_fnu_txring *txring; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ if (sidp == NULL || cri == NULL || sc == NULL) { -+ DPRINTF("%s,%d - EINVAL\n", __FILE__, __LINE__); -+ return -EINVAL; -+ } -+ for (c = cri; c != NULL; c = c->cri_next) { -+ if (ALG_IS_SIG(c->cri_alg)) { -+ if (macini) -+ return -EINVAL; -+ macini = c; -+ } else if (ALG_IS_CIPHER(c->cri_alg)) { -+ if (encini) -+ return -EINVAL; -+ encini = c; -+ } else { -+ DPRINTF("UNKNOWN c->cri_alg %d\n", c->cri_alg); -+ return -EINVAL; -+ } -+ } -+ if (encini == NULL && macini == NULL) -+ return -EINVAL; -+ if (encini) { -+ /* validate key length */ -+ switch (encini->cri_alg) { -+ case CRYPTO_DES_CBC: -+ if (encini->cri_klen != 64) -+ return -EINVAL; -+ ccmd = DMA_CALGO_DES; -+ break; -+ case CRYPTO_3DES_CBC: -+ if (encini->cri_klen != 192) -+ return -EINVAL; -+ ccmd = DMA_CALGO_3DES; -+ break; -+ case CRYPTO_AES_CBC: -+ if (encini->cri_klen != 128 && -+ encini->cri_klen != 192 && -+ encini->cri_klen != 256) -+ return -EINVAL; -+ ccmd = DMA_CALGO_AES; -+ break; -+ case CRYPTO_ARC4: -+ if (encini->cri_klen != 128) -+ return -EINVAL; -+ ccmd = DMA_CALGO_ARC; -+ break; -+ default: -+ DPRINTF("UNKNOWN encini->cri_alg %d\n", -+ encini->cri_alg); -+ return -EINVAL; -+ } -+ } -+ -+ if (macini) { -+ switch (macini->cri_alg) { -+ case CRYPTO_MD5: -+ case CRYPTO_MD5_HMAC: -+ blksz = 16; -+ break; -+ case CRYPTO_SHA1: -+ case CRYPTO_SHA1_HMAC: -+ blksz = 20; -+ break; -+ default: -+ DPRINTF("UNKNOWN macini->cri_alg %d\n", -+ macini->cri_alg); -+ return -EINVAL; -+ } -+ if (((macini->cri_klen + 7) / 8) > blksz) { -+ DPRINTF("key length %d bigger than blksize %d not supported\n", -+ ((macini->cri_klen + 7) / 8), blksz); -+ return -EINVAL; -+ } -+ } -+ -+ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { -+ if (sc->sc_sessions[sesn] == NULL) { -+ sc->sc_sessions[sesn] = (struct pasemi_session *) -+ kzalloc(sizeof(struct pasemi_session), GFP_ATOMIC); -+ ses = sc->sc_sessions[sesn]; -+ break; -+ } else if (sc->sc_sessions[sesn]->used == 0) { -+ ses = sc->sc_sessions[sesn]; -+ break; -+ } -+ } -+ -+ if (ses == NULL) { -+ sespp = (struct pasemi_session **) -+ kzalloc(sc->sc_nsessions * 2 * -+ sizeof(struct pasemi_session *), GFP_ATOMIC); -+ if (sespp == NULL) -+ return -ENOMEM; -+ memcpy(sespp, sc->sc_sessions, -+ sc->sc_nsessions * sizeof(struct pasemi_session *)); -+ kfree(sc->sc_sessions); -+ sc->sc_sessions = sespp; -+ sesn = sc->sc_nsessions; -+ ses = sc->sc_sessions[sesn] = (struct pasemi_session *) -+ kzalloc(sizeof(struct pasemi_session), GFP_ATOMIC); -+ if (ses == NULL) -+ return -ENOMEM; -+ sc->sc_nsessions *= 2; -+ } -+ -+ ses->used = 1; -+ -+ ses->dma_addr = pci_map_single(sc->dma_pdev, (void *) ses->civ, -+ sizeof(struct pasemi_session), DMA_TO_DEVICE); -+ -+ /* enter the channel scheduler */ -+ spin_lock_irqsave(&sc->sc_chnlock, flags); -+ -+ /* ARC4 has to be processed by the even channel */ -+ if (encini && (encini->cri_alg == CRYPTO_ARC4)) -+ ses->chan = sc->sc_lastchn & ~1; -+ else -+ ses->chan = sc->sc_lastchn; -+ sc->sc_lastchn = (sc->sc_lastchn + 1) % sc->sc_num_channels; -+ -+ spin_unlock_irqrestore(&sc->sc_chnlock, flags); -+ -+ txring = &sc->tx[ses->chan]; -+ -+ if (encini) { -+ ses->ccmd = ccmd; -+ -+ /* get an IV */ -+ /* XXX may read fewer than requested */ -+ get_random_bytes(ses->civ, sizeof(ses->civ)); -+ -+ ses->keysz = (encini->cri_klen - 63) / 64; -+ memcpy(ses->key, encini->cri_key, (ses->keysz + 1) * 8); -+ -+ pasemi_desc_start(&init_desc, -+ XCT_CTRL_HDR(ses->chan, (encini && macini) ? 0x68 : 0x40, DMA_FN_CIV0)); -+ pasemi_desc_build(&init_desc, -+ XCT_FUN_SRC_PTR((encini && macini) ? 0x68 : 0x40, ses->dma_addr)); -+ } -+ if (macini) { -+ if (macini->cri_alg == CRYPTO_MD5_HMAC || -+ macini->cri_alg == CRYPTO_SHA1_HMAC) -+ memcpy(ses->hkey, macini->cri_key, blksz); -+ else { -+ /* Load initialization constants(RFC 1321, 3174) */ -+ ses->hiv[0] = 0x67452301efcdab89ULL; -+ ses->hiv[1] = 0x98badcfe10325476ULL; -+ ses->hiv[2] = 0xc3d2e1f000000000ULL; -+ } -+ ses->hseq = 0ULL; -+ } -+ -+ spin_lock_irqsave(&txring->fill_lock, flags); -+ -+ if (((txring->next_to_fill + pasemi_desc_size(&init_desc)) - -+ txring->next_to_clean) > TX_RING_SIZE) { -+ spin_unlock_irqrestore(&txring->fill_lock, flags); -+ return ERESTART; -+ } -+ -+ if (encini) { -+ pasemi_ring_add_desc(txring, &init_desc, NULL); -+ pasemi_ring_incr(sc, ses->chan, -+ pasemi_desc_size(&init_desc)); -+ } -+ -+ txring->sesn = sesn; -+ spin_unlock_irqrestore(&txring->fill_lock, flags); -+ -+ *sidp = PASEMI_SID(sesn); -+ return 0; -+} -+ -+/* -+ * Deallocate a session. -+ */ -+static int -+pasemi_freesession(device_t dev, u_int64_t tid) -+{ -+ struct pasemi_softc *sc = device_get_softc(dev); -+ int session; -+ u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (sc == NULL) -+ return -EINVAL; -+ session = PASEMI_SESSION(sid); -+ if (session >= sc->sc_nsessions || !sc->sc_sessions[session]) -+ return -EINVAL; -+ -+ pci_unmap_single(sc->dma_pdev, -+ sc->sc_sessions[session]->dma_addr, -+ sizeof(struct pasemi_session), DMA_TO_DEVICE); -+ memset(sc->sc_sessions[session], 0, -+ sizeof(struct pasemi_session)); -+ -+ return 0; -+} -+ -+static int -+pasemi_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ -+ int err = 0, ivsize, srclen = 0, reinit = 0, reinit_size = 0, chsel; -+ struct pasemi_softc *sc = device_get_softc(dev); -+ struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; -+ caddr_t ivp; -+ struct pasemi_desc init_desc, work_desc; -+ struct pasemi_session *ses; -+ struct sk_buff *skb; -+ struct uio *uiop; -+ unsigned long flags; -+ struct pasemi_fnu_txring *txring; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (crp == NULL || crp->crp_callback == NULL || sc == NULL) -+ return -EINVAL; -+ -+ crp->crp_etype = 0; -+ if (PASEMI_SESSION(crp->crp_sid) >= sc->sc_nsessions) -+ return -EINVAL; -+ -+ ses = sc->sc_sessions[PASEMI_SESSION(crp->crp_sid)]; -+ -+ crd1 = crp->crp_desc; -+ if (crd1 == NULL) { -+ err = -EINVAL; -+ goto errout; -+ } -+ crd2 = crd1->crd_next; -+ -+ if (ALG_IS_SIG(crd1->crd_alg)) { -+ maccrd = crd1; -+ if (crd2 == NULL) -+ enccrd = NULL; -+ else if (ALG_IS_CIPHER(crd2->crd_alg) && -+ (crd2->crd_flags & CRD_F_ENCRYPT) == 0) -+ enccrd = crd2; -+ else -+ goto erralg; -+ } else if (ALG_IS_CIPHER(crd1->crd_alg)) { -+ enccrd = crd1; -+ if (crd2 == NULL) -+ maccrd = NULL; -+ else if (ALG_IS_SIG(crd2->crd_alg) && -+ (crd1->crd_flags & CRD_F_ENCRYPT)) -+ maccrd = crd2; -+ else -+ goto erralg; -+ } else -+ goto erralg; -+ -+ chsel = ses->chan; -+ -+ txring = &sc->tx[chsel]; -+ -+ if (enccrd && !maccrd) { -+ if (enccrd->crd_alg == CRYPTO_ARC4) -+ reinit = 1; -+ reinit_size = 0x40; -+ srclen = crp->crp_ilen; -+ -+ pasemi_desc_start(&work_desc, XCT_FUN_O | XCT_FUN_I -+ | XCT_FUN_FUN(chsel)); -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) -+ pasemi_desc_hdr(&work_desc, XCT_FUN_CRM_ENC); -+ else -+ pasemi_desc_hdr(&work_desc, XCT_FUN_CRM_DEC); -+ } else if (enccrd && maccrd) { -+ if (enccrd->crd_alg == CRYPTO_ARC4) -+ reinit = 1; -+ reinit_size = 0x68; -+ -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) { -+ /* Encrypt -> Authenticate */ -+ pasemi_desc_start(&work_desc, XCT_FUN_O | XCT_FUN_I | XCT_FUN_CRM_ENC_SIG -+ | XCT_FUN_A | XCT_FUN_FUN(chsel)); -+ srclen = maccrd->crd_skip + maccrd->crd_len; -+ } else { -+ /* Authenticate -> Decrypt */ -+ pasemi_desc_start(&work_desc, XCT_FUN_O | XCT_FUN_I | XCT_FUN_CRM_SIG_DEC -+ | XCT_FUN_24BRES | XCT_FUN_FUN(chsel)); -+ pasemi_desc_build(&work_desc, 0); -+ pasemi_desc_build(&work_desc, 0); -+ pasemi_desc_build(&work_desc, 0); -+ work_desc.postop = PASEMI_CHECK_SIG; -+ srclen = crp->crp_ilen; -+ } -+ -+ pasemi_desc_hdr(&work_desc, XCT_FUN_SHL(maccrd->crd_skip / 4)); -+ pasemi_desc_hdr(&work_desc, XCT_FUN_CHL(enccrd->crd_skip - maccrd->crd_skip)); -+ } else if (!enccrd && maccrd) { -+ srclen = maccrd->crd_len; -+ -+ pasemi_desc_start(&init_desc, -+ XCT_CTRL_HDR(chsel, 0x58, DMA_FN_HKEY0)); -+ pasemi_desc_build(&init_desc, -+ XCT_FUN_SRC_PTR(0x58, ((struct pasemi_session *)ses->dma_addr)->hkey)); -+ -+ pasemi_desc_start(&work_desc, XCT_FUN_O | XCT_FUN_I | XCT_FUN_CRM_SIG -+ | XCT_FUN_A | XCT_FUN_FUN(chsel)); -+ } -+ -+ if (enccrd) { -+ switch (enccrd->crd_alg) { -+ case CRYPTO_3DES_CBC: -+ pasemi_desc_hdr(&work_desc, XCT_FUN_ALG_3DES | -+ XCT_FUN_BCM_CBC); -+ ivsize = sizeof(u64); -+ break; -+ case CRYPTO_DES_CBC: -+ pasemi_desc_hdr(&work_desc, XCT_FUN_ALG_DES | -+ XCT_FUN_BCM_CBC); -+ ivsize = sizeof(u64); -+ break; -+ case CRYPTO_AES_CBC: -+ pasemi_desc_hdr(&work_desc, XCT_FUN_ALG_AES | -+ XCT_FUN_BCM_CBC); -+ ivsize = 2 * sizeof(u64); -+ break; -+ case CRYPTO_ARC4: -+ pasemi_desc_hdr(&work_desc, XCT_FUN_ALG_ARC); -+ ivsize = 0; -+ break; -+ default: -+ printk(DRV_NAME ": unimplemented enccrd->crd_alg %d\n", -+ enccrd->crd_alg); -+ err = -EINVAL; -+ goto errout; -+ } -+ -+ ivp = (ivsize == sizeof(u64)) ? (caddr_t) &ses->civ[1] : (caddr_t) &ses->civ[0]; -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) { -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) -+ memcpy(ivp, enccrd->crd_iv, ivsize); -+ /* If IV is not present in the buffer already, it has to be copied there */ -+ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ enccrd->crd_inject, ivsize, ivp); -+ } else { -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) -+ /* IV is provided expicitly in descriptor */ -+ memcpy(ivp, enccrd->crd_iv, ivsize); -+ else -+ /* IV is provided in the packet */ -+ crypto_copydata(crp->crp_flags, crp->crp_buf, -+ enccrd->crd_inject, ivsize, -+ ivp); -+ } -+ } -+ -+ if (maccrd) { -+ switch (maccrd->crd_alg) { -+ case CRYPTO_MD5: -+ pasemi_desc_hdr(&work_desc, XCT_FUN_SIG_MD5 | -+ XCT_FUN_HSZ((crp->crp_ilen - maccrd->crd_inject) / 4)); -+ break; -+ case CRYPTO_SHA1: -+ pasemi_desc_hdr(&work_desc, XCT_FUN_SIG_SHA1 | -+ XCT_FUN_HSZ((crp->crp_ilen - maccrd->crd_inject) / 4)); -+ break; -+ case CRYPTO_MD5_HMAC: -+ pasemi_desc_hdr(&work_desc, XCT_FUN_SIG_HMAC_MD5 | -+ XCT_FUN_HSZ((crp->crp_ilen - maccrd->crd_inject) / 4)); -+ break; -+ case CRYPTO_SHA1_HMAC: -+ pasemi_desc_hdr(&work_desc, XCT_FUN_SIG_HMAC_SHA1 | -+ XCT_FUN_HSZ((crp->crp_ilen - maccrd->crd_inject) / 4)); -+ break; -+ default: -+ printk(DRV_NAME ": unimplemented maccrd->crd_alg %d\n", -+ maccrd->crd_alg); -+ err = -EINVAL; -+ goto errout; -+ } -+ } -+ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ /* using SKB buffers */ -+ skb = (struct sk_buff *)crp->crp_buf; -+ if (skb_shinfo(skb)->nr_frags) { -+ printk(DRV_NAME ": skb frags unimplemented\n"); -+ err = -EINVAL; -+ goto errout; -+ } -+ pasemi_desc_build( -+ &work_desc, -+ XCT_FUN_DST_PTR(skb->len, pci_map_single( -+ sc->dma_pdev, skb->data, -+ skb->len, DMA_TO_DEVICE))); -+ pasemi_desc_build( -+ &work_desc, -+ XCT_FUN_SRC_PTR( -+ srclen, pci_map_single( -+ sc->dma_pdev, skb->data, -+ srclen, DMA_TO_DEVICE))); -+ pasemi_desc_hdr(&work_desc, XCT_FUN_LLEN(srclen)); -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ /* using IOV buffers */ -+ uiop = (struct uio *)crp->crp_buf; -+ if (uiop->uio_iovcnt > 1) { -+ printk(DRV_NAME ": iov frags unimplemented\n"); -+ err = -EINVAL; -+ goto errout; -+ } -+ -+ /* crp_olen is never set; always use crp_ilen */ -+ pasemi_desc_build( -+ &work_desc, -+ XCT_FUN_DST_PTR(crp->crp_ilen, pci_map_single( -+ sc->dma_pdev, -+ uiop->uio_iov->iov_base, -+ crp->crp_ilen, DMA_TO_DEVICE))); -+ pasemi_desc_hdr(&work_desc, XCT_FUN_LLEN(srclen)); -+ -+ pasemi_desc_build( -+ &work_desc, -+ XCT_FUN_SRC_PTR(srclen, pci_map_single( -+ sc->dma_pdev, -+ uiop->uio_iov->iov_base, -+ srclen, DMA_TO_DEVICE))); -+ } else { -+ /* using contig buffers */ -+ pasemi_desc_build( -+ &work_desc, -+ XCT_FUN_DST_PTR(crp->crp_ilen, pci_map_single( -+ sc->dma_pdev, -+ crp->crp_buf, -+ crp->crp_ilen, DMA_TO_DEVICE))); -+ pasemi_desc_build( -+ &work_desc, -+ XCT_FUN_SRC_PTR(srclen, pci_map_single( -+ sc->dma_pdev, -+ crp->crp_buf, srclen, -+ DMA_TO_DEVICE))); -+ pasemi_desc_hdr(&work_desc, XCT_FUN_LLEN(srclen)); -+ } -+ -+ spin_lock_irqsave(&txring->fill_lock, flags); -+ -+ if (txring->sesn != PASEMI_SESSION(crp->crp_sid)) { -+ txring->sesn = PASEMI_SESSION(crp->crp_sid); -+ reinit = 1; -+ } -+ -+ if (enccrd) { -+ pasemi_desc_start(&init_desc, -+ XCT_CTRL_HDR(chsel, reinit ? reinit_size : 0x10, DMA_FN_CIV0)); -+ pasemi_desc_build(&init_desc, -+ XCT_FUN_SRC_PTR(reinit ? reinit_size : 0x10, ses->dma_addr)); -+ } -+ -+ if (((txring->next_to_fill + pasemi_desc_size(&init_desc) + -+ pasemi_desc_size(&work_desc)) - -+ txring->next_to_clean) > TX_RING_SIZE) { -+ spin_unlock_irqrestore(&txring->fill_lock, flags); -+ err = ERESTART; -+ goto errout; -+ } -+ -+ pasemi_ring_add_desc(txring, &init_desc, NULL); -+ pasemi_ring_add_desc(txring, &work_desc, crp); -+ -+ pasemi_ring_incr(sc, chsel, -+ pasemi_desc_size(&init_desc) + -+ pasemi_desc_size(&work_desc)); -+ -+ spin_unlock_irqrestore(&txring->fill_lock, flags); -+ -+ mod_timer(&txring->crypto_timer, jiffies + TIMER_INTERVAL); -+ -+ return 0; -+ -+erralg: -+ printk(DRV_NAME ": unsupported algorithm or algorithm order alg1 %d alg2 %d\n", -+ crd1->crd_alg, crd2->crd_alg); -+ err = -EINVAL; -+ -+errout: -+ if (err != ERESTART) { -+ crp->crp_etype = err; -+ crypto_done(crp); -+ } -+ return err; -+} -+ -+static int pasemi_clean_tx(struct pasemi_softc *sc, int chan) -+{ -+ int i, j, ring_idx; -+ struct pasemi_fnu_txring *ring = &sc->tx[chan]; -+ u16 delta_cnt; -+ int flags, loops = 10; -+ int desc_size; -+ struct cryptop *crp; -+ -+ spin_lock_irqsave(&ring->clean_lock, flags); -+ -+ while ((delta_cnt = (dma_status->tx_sta[sc->base_chan + chan] -+ & PAS_STATUS_PCNT_M) - ring->total_pktcnt) -+ && loops--) { -+ -+ for (i = 0; i < delta_cnt; i++) { -+ desc_size = TX_DESC_INFO(ring, ring->next_to_clean).desc_size; -+ crp = TX_DESC_INFO(ring, ring->next_to_clean).cf_crp; -+ if (crp) { -+ ring_idx = 2 * (ring->next_to_clean & (TX_RING_SIZE-1)); -+ if (TX_DESC_INFO(ring, ring->next_to_clean).desc_postop & PASEMI_CHECK_SIG) { -+ /* Need to make sure signature matched, -+ * if not - return error */ -+ if (!(ring->desc[ring_idx + 1] & (1ULL << 63))) -+ crp->crp_etype = -EINVAL; -+ } -+ crypto_done(TX_DESC_INFO(ring, -+ ring->next_to_clean).cf_crp); -+ TX_DESC_INFO(ring, ring->next_to_clean).cf_crp = NULL; -+ pci_unmap_single( -+ sc->dma_pdev, -+ XCT_PTR_ADDR_LEN(ring->desc[ring_idx + 1]), -+ PCI_DMA_TODEVICE); -+ -+ ring->desc[ring_idx] = ring->desc[ring_idx + 1] = 0; -+ -+ ring->next_to_clean++; -+ for (j = 1; j < desc_size; j++) { -+ ring_idx = 2 * -+ (ring->next_to_clean & -+ (TX_RING_SIZE-1)); -+ pci_unmap_single( -+ sc->dma_pdev, -+ XCT_PTR_ADDR_LEN(ring->desc[ring_idx]), -+ PCI_DMA_TODEVICE); -+ if (ring->desc[ring_idx + 1]) -+ pci_unmap_single( -+ sc->dma_pdev, -+ XCT_PTR_ADDR_LEN( -+ ring->desc[ -+ ring_idx + 1]), -+ PCI_DMA_TODEVICE); -+ ring->desc[ring_idx] = -+ ring->desc[ring_idx + 1] = 0; -+ ring->next_to_clean++; -+ } -+ } else { -+ for (j = 0; j < desc_size; j++) { -+ ring_idx = 2 * (ring->next_to_clean & (TX_RING_SIZE-1)); -+ ring->desc[ring_idx] = -+ ring->desc[ring_idx + 1] = 0; -+ ring->next_to_clean++; -+ } -+ } -+ } -+ -+ ring->total_pktcnt += delta_cnt; -+ } -+ spin_unlock_irqrestore(&ring->clean_lock, flags); -+ -+ return 0; -+} -+ -+static void sweepup_tx(struct pasemi_softc *sc) -+{ -+ int i; -+ -+ for (i = 0; i < sc->sc_num_channels; i++) -+ pasemi_clean_tx(sc, i); -+} -+ -+static irqreturn_t pasemi_intr(int irq, void *arg, struct pt_regs *regs) -+{ -+ struct pasemi_softc *sc = arg; -+ unsigned int reg; -+ int chan = irq - sc->base_irq; -+ int chan_index = sc->base_chan + chan; -+ u64 stat = dma_status->tx_sta[chan_index]; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (!(stat & PAS_STATUS_CAUSE_M)) -+ return IRQ_NONE; -+ -+ pasemi_clean_tx(sc, chan); -+ -+ stat = dma_status->tx_sta[chan_index]; -+ -+ reg = PAS_IOB_DMA_TXCH_RESET_PINTC | -+ PAS_IOB_DMA_TXCH_RESET_PCNT(sc->tx[chan].total_pktcnt); -+ -+ if (stat & PAS_STATUS_SOFT) -+ reg |= PAS_IOB_DMA_RXCH_RESET_SINTC; -+ -+ out_le32(sc->iob_regs + PAS_IOB_DMA_TXCH_RESET(chan_index), reg); -+ -+ -+ return IRQ_HANDLED; -+} -+ -+static int pasemi_dma_setup_tx_resources(struct pasemi_softc *sc, int chan) -+{ -+ u32 val; -+ int chan_index = chan + sc->base_chan; -+ int ret; -+ struct pasemi_fnu_txring *ring; -+ -+ ring = &sc->tx[chan]; -+ -+ spin_lock_init(&ring->fill_lock); -+ spin_lock_init(&ring->clean_lock); -+ -+ ring->desc_info = kzalloc(sizeof(struct pasemi_desc_info) * -+ TX_RING_SIZE, GFP_KERNEL); -+ if (!ring->desc_info) -+ return -ENOMEM; -+ -+ /* Allocate descriptors */ -+ ring->desc = dma_alloc_coherent(&sc->dma_pdev->dev, -+ TX_RING_SIZE * -+ 2 * sizeof(u64), -+ &ring->dma, GFP_KERNEL); -+ if (!ring->desc) -+ return -ENOMEM; -+ -+ memset((void *) ring->desc, 0, TX_RING_SIZE * 2 * sizeof(u64)); -+ -+ out_le32(sc->iob_regs + PAS_IOB_DMA_TXCH_RESET(chan_index), 0x30); -+ -+ ring->total_pktcnt = 0; -+ -+ out_le32(sc->dma_regs + PAS_DMA_TXCHAN_BASEL(chan_index), -+ PAS_DMA_TXCHAN_BASEL_BRBL(ring->dma)); -+ -+ val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->dma >> 32); -+ val |= PAS_DMA_TXCHAN_BASEU_SIZ(TX_RING_SIZE >> 2); -+ -+ out_le32(sc->dma_regs + PAS_DMA_TXCHAN_BASEU(chan_index), val); -+ -+ out_le32(sc->dma_regs + PAS_DMA_TXCHAN_CFG(chan_index), -+ PAS_DMA_TXCHAN_CFG_TY_FUNC | -+ PAS_DMA_TXCHAN_CFG_TATTR(chan) | -+ PAS_DMA_TXCHAN_CFG_WT(2)); -+ -+ /* enable tx channel */ -+ out_le32(sc->dma_regs + -+ PAS_DMA_TXCHAN_TCMDSTA(chan_index), -+ PAS_DMA_TXCHAN_TCMDSTA_EN); -+ -+ out_le32(sc->iob_regs + PAS_IOB_DMA_TXCH_CFG(chan_index), -+ PAS_IOB_DMA_TXCH_CFG_CNTTH(1000)); -+ -+ ring->next_to_fill = 0; -+ ring->next_to_clean = 0; -+ -+ snprintf(ring->irq_name, sizeof(ring->irq_name), -+ "%s%d", "crypto", chan); -+ -+ ring->irq = irq_create_mapping(NULL, sc->base_irq + chan); -+ ret = request_irq(ring->irq, (irq_handler_t) -+ pasemi_intr, IRQF_DISABLED, ring->irq_name, sc); -+ if (ret) { -+ printk(KERN_ERR DRV_NAME ": failed to hook irq %d ret %d\n", -+ ring->irq, ret); -+ ring->irq = -1; -+ return ret; -+ } -+ -+ setup_timer(&ring->crypto_timer, (void *) sweepup_tx, (unsigned long) sc); -+ -+ return 0; -+} -+ -+static device_method_t pasemi_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, pasemi_newsession), -+ DEVMETHOD(cryptodev_freesession, pasemi_freesession), -+ DEVMETHOD(cryptodev_process, pasemi_process), -+}; -+ -+/* Set up the crypto device structure, private data, -+ * and anything else we need before we start */ -+ -+static int __devinit -+pasemi_dma_probe(struct pci_dev *pdev, const struct pci_device_id *ent) -+{ -+ struct pasemi_softc *sc; -+ int ret, i; -+ -+ DPRINTF(KERN_ERR "%s()\n", __FUNCTION__); -+ -+ sc = kzalloc(sizeof(*sc), GFP_KERNEL); -+ if (!sc) -+ return -ENOMEM; -+ -+ softc_device_init(sc, DRV_NAME, 1, pasemi_methods); -+ -+ pci_set_drvdata(pdev, sc); -+ -+ spin_lock_init(&sc->sc_chnlock); -+ -+ sc->sc_sessions = (struct pasemi_session **) -+ kzalloc(PASEMI_INITIAL_SESSIONS * -+ sizeof(struct pasemi_session *), GFP_ATOMIC); -+ if (sc->sc_sessions == NULL) { -+ ret = -ENOMEM; -+ goto out; -+ } -+ -+ sc->sc_nsessions = PASEMI_INITIAL_SESSIONS; -+ sc->sc_lastchn = 0; -+ sc->base_irq = pdev->irq + 6; -+ sc->base_chan = 6; -+ sc->sc_cid = -1; -+ sc->dma_pdev = pdev; -+ -+ sc->iob_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL); -+ if (!sc->iob_pdev) { -+ dev_err(&pdev->dev, "Can't find I/O Bridge\n"); -+ ret = -ENODEV; -+ goto out; -+ } -+ -+ /* This is hardcoded and ugly, but we have some firmware versions -+ * who don't provide the register space in the device tree. Luckily -+ * they are at well-known locations so we can just do the math here. -+ */ -+ sc->dma_regs = -+ ioremap(0xe0000000 + (sc->dma_pdev->devfn << 12), 0x2000); -+ sc->iob_regs = -+ ioremap(0xe0000000 + (sc->iob_pdev->devfn << 12), 0x2000); -+ if (!sc->dma_regs || !sc->iob_regs) { -+ dev_err(&pdev->dev, "Can't map registers\n"); -+ ret = -ENODEV; -+ goto out; -+ } -+ -+ dma_status = __ioremap(0xfd800000, 0x1000, 0); -+ if (!dma_status) { -+ ret = -ENODEV; -+ dev_err(&pdev->dev, "Can't map dmastatus space\n"); -+ goto out; -+ } -+ -+ sc->tx = (struct pasemi_fnu_txring *) -+ kzalloc(sizeof(struct pasemi_fnu_txring) -+ * 8, GFP_KERNEL); -+ if (!sc->tx) { -+ ret = -ENOMEM; -+ goto out; -+ } -+ -+ /* Initialize the h/w */ -+ out_le32(sc->dma_regs + PAS_DMA_COM_CFG, -+ (in_le32(sc->dma_regs + PAS_DMA_COM_CFG) | -+ PAS_DMA_COM_CFG_FWF)); -+ out_le32(sc->dma_regs + PAS_DMA_COM_TXCMD, PAS_DMA_COM_TXCMD_EN); -+ -+ for (i = 0; i < PASEMI_FNU_CHANNELS; i++) { -+ sc->sc_num_channels++; -+ ret = pasemi_dma_setup_tx_resources(sc, i); -+ if (ret) -+ goto out; -+ } -+ -+ sc->sc_cid = crypto_get_driverid(softc_get_device(sc), -+ CRYPTOCAP_F_HARDWARE); -+ if (sc->sc_cid < 0) { -+ printk(KERN_ERR DRV_NAME ": could not get crypto driver id\n"); -+ ret = -ENXIO; -+ goto out; -+ } -+ -+ /* register algorithms with the framework */ -+ printk(DRV_NAME ":"); -+ -+ crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); -+ -+ return 0; -+ -+out: -+ pasemi_dma_remove(pdev); -+ return ret; -+} -+ -+#define MAX_RETRIES 5000 -+ -+static void pasemi_free_tx_resources(struct pasemi_softc *sc, int chan) -+{ -+ struct pasemi_fnu_txring *ring = &sc->tx[chan]; -+ int chan_index = chan + sc->base_chan; -+ int retries; -+ u32 stat; -+ -+ /* Stop the channel */ -+ out_le32(sc->dma_regs + -+ PAS_DMA_TXCHAN_TCMDSTA(chan_index), -+ PAS_DMA_TXCHAN_TCMDSTA_ST); -+ -+ for (retries = 0; retries < MAX_RETRIES; retries++) { -+ stat = in_le32(sc->dma_regs + -+ PAS_DMA_TXCHAN_TCMDSTA(chan_index)); -+ if (!(stat & PAS_DMA_TXCHAN_TCMDSTA_ACT)) -+ break; -+ cond_resched(); -+ } -+ -+ if (stat & PAS_DMA_TXCHAN_TCMDSTA_ACT) -+ dev_err(&sc->dma_pdev->dev, "Failed to stop tx channel %d\n", -+ chan_index); -+ -+ /* Disable the channel */ -+ out_le32(sc->dma_regs + -+ PAS_DMA_TXCHAN_TCMDSTA(chan_index), -+ 0); -+ -+ if (ring->desc_info) -+ kfree((void *) ring->desc_info); -+ if (ring->desc) -+ dma_free_coherent(&sc->dma_pdev->dev, -+ TX_RING_SIZE * -+ 2 * sizeof(u64), -+ (void *) ring->desc, ring->dma); -+ if (ring->irq != -1) -+ free_irq(ring->irq, sc); -+ -+ del_timer(&ring->crypto_timer); -+} -+ -+static void __devexit pasemi_dma_remove(struct pci_dev *pdev) -+{ -+ struct pasemi_softc *sc = pci_get_drvdata(pdev); -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (sc->sc_cid >= 0) { -+ crypto_unregister_all(sc->sc_cid); -+ } -+ -+ if (sc->tx) { -+ for (i = 0; i < sc->sc_num_channels; i++) -+ pasemi_free_tx_resources(sc, i); -+ -+ kfree(sc->tx); -+ } -+ if (sc->sc_sessions) { -+ for (i = 0; i < sc->sc_nsessions; i++) -+ kfree(sc->sc_sessions[i]); -+ kfree(sc->sc_sessions); -+ } -+ if (sc->iob_pdev) -+ pci_dev_put(sc->iob_pdev); -+ if (sc->dma_regs) -+ iounmap(sc->dma_regs); -+ if (sc->iob_regs) -+ iounmap(sc->iob_regs); -+ kfree(sc); -+} -+ -+static struct pci_device_id pasemi_dma_pci_tbl[] = { -+ { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa007) }, -+}; -+ -+MODULE_DEVICE_TABLE(pci, pasemi_dma_pci_tbl); -+ -+static struct pci_driver pasemi_dma_driver = { -+ .name = "pasemi_dma", -+ .id_table = pasemi_dma_pci_tbl, -+ .probe = pasemi_dma_probe, -+ .remove = __devexit_p(pasemi_dma_remove), -+}; -+ -+static void __exit pasemi_dma_cleanup_module(void) -+{ -+ pci_unregister_driver(&pasemi_dma_driver); -+ __iounmap(dma_status); -+ dma_status = NULL; -+} -+ -+int pasemi_dma_init_module(void) -+{ -+ return pci_register_driver(&pasemi_dma_driver); -+} -+ -+module_init(pasemi_dma_init_module); -+module_exit(pasemi_dma_cleanup_module); -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_AUTHOR("Egor Martovetsky egor@pasemi.com"); -+MODULE_DESCRIPTION("OCF driver for PA Semi PWRficient DMA Crypto Engine"); -diff -Nur linux-2.6.39.orig/crypto/ocf/pasemi/pasemi_fnu.h linux-2.6.39/crypto/ocf/pasemi/pasemi_fnu.h ---- linux-2.6.39.orig/crypto/ocf/pasemi/pasemi_fnu.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/pasemi/pasemi_fnu.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,410 @@ -+/* -+ * Copyright (C) 2007 PA Semi, Inc -+ * -+ * Driver for the PA Semi PWRficient DMA Crypto Engine, soft state and -+ * hardware register layouts. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef PASEMI_FNU_H -+#define PASEMI_FNU_H -+ -+#include -+ -+#define PASEMI_SESSION(sid) ((sid) & 0xffffffff) -+#define PASEMI_SID(sesn) ((sesn) & 0xffffffff) -+#define DPRINTF(a...) if (debug) { printk(DRV_NAME ": " a); } -+ -+/* Must be a power of two */ -+#define RX_RING_SIZE 512 -+#define TX_RING_SIZE 512 -+#define TX_DESC(ring, num) ((ring)->desc[2 * (num & (TX_RING_SIZE-1))]) -+#define TX_DESC_INFO(ring, num) ((ring)->desc_info[(num) & (TX_RING_SIZE-1)]) -+#define MAX_DESC_SIZE 8 -+#define PASEMI_INITIAL_SESSIONS 10 -+#define PASEMI_FNU_CHANNELS 8 -+ -+/* DMA descriptor */ -+struct pasemi_desc { -+ u64 quad[2*MAX_DESC_SIZE]; -+ int quad_cnt; -+ int size; -+ int postop; -+}; -+ -+/* -+ * Holds per descriptor data -+ */ -+struct pasemi_desc_info { -+ int desc_size; -+ int desc_postop; -+#define PASEMI_CHECK_SIG 0x1 -+ -+ struct cryptop *cf_crp; -+}; -+ -+/* -+ * Holds per channel data -+ */ -+struct pasemi_fnu_txring { -+ volatile u64 *desc; -+ volatile struct -+ pasemi_desc_info *desc_info; -+ dma_addr_t dma; -+ struct timer_list crypto_timer; -+ spinlock_t fill_lock; -+ spinlock_t clean_lock; -+ unsigned int next_to_fill; -+ unsigned int next_to_clean; -+ u16 total_pktcnt; -+ int irq; -+ int sesn; -+ char irq_name[10]; -+}; -+ -+/* -+ * Holds data specific to a single pasemi device. -+ */ -+struct pasemi_softc { -+ softc_device_decl sc_cdev; -+ struct pci_dev *dma_pdev; /* device backpointer */ -+ struct pci_dev *iob_pdev; /* device backpointer */ -+ void __iomem *dma_regs; -+ void __iomem *iob_regs; -+ int base_irq; -+ int base_chan; -+ int32_t sc_cid; /* crypto tag */ -+ int sc_nsessions; -+ struct pasemi_session **sc_sessions; -+ int sc_num_channels;/* number of crypto channels */ -+ -+ /* pointer to the array of txring datastructures, one txring per channel */ -+ struct pasemi_fnu_txring *tx; -+ -+ /* -+ * mutual exclusion for the channel scheduler -+ */ -+ spinlock_t sc_chnlock; -+ /* last channel used, for now use round-robin to allocate channels */ -+ int sc_lastchn; -+}; -+ -+struct pasemi_session { -+ u64 civ[2]; -+ u64 keysz; -+ u64 key[4]; -+ u64 ccmd; -+ u64 hkey[4]; -+ u64 hseq; -+ u64 giv[2]; -+ u64 hiv[4]; -+ -+ int used; -+ dma_addr_t dma_addr; -+ int chan; -+}; -+ -+/* status register layout in IOB region, at 0xfd800000 */ -+struct pasdma_status { -+ u64 rx_sta[64]; -+ u64 tx_sta[20]; -+}; -+ -+#define ALG_IS_CIPHER(alg) ((alg == CRYPTO_DES_CBC) || \ -+ (alg == CRYPTO_3DES_CBC) || \ -+ (alg == CRYPTO_AES_CBC) || \ -+ (alg == CRYPTO_ARC4) || \ -+ (alg == CRYPTO_NULL_CBC)) -+ -+#define ALG_IS_SIG(alg) ((alg == CRYPTO_MD5) || \ -+ (alg == CRYPTO_MD5_HMAC) || \ -+ (alg == CRYPTO_SHA1) || \ -+ (alg == CRYPTO_SHA1_HMAC) || \ -+ (alg == CRYPTO_NULL_HMAC)) -+ -+enum { -+ PAS_DMA_COM_TXCMD = 0x100, /* Transmit Command Register */ -+ PAS_DMA_COM_TXSTA = 0x104, /* Transmit Status Register */ -+ PAS_DMA_COM_RXCMD = 0x108, /* Receive Command Register */ -+ PAS_DMA_COM_RXSTA = 0x10c, /* Receive Status Register */ -+ PAS_DMA_COM_CFG = 0x114, /* DMA Configuration Register */ -+}; -+ -+/* All these registers live in the PCI configuration space for the DMA PCI -+ * device. Use the normal PCI config access functions for them. -+ */ -+ -+#define PAS_DMA_COM_CFG_FWF 0x18000000 -+ -+#define PAS_DMA_COM_TXCMD_EN 0x00000001 /* enable */ -+#define PAS_DMA_COM_TXSTA_ACT 0x00000001 /* active */ -+#define PAS_DMA_COM_RXCMD_EN 0x00000001 /* enable */ -+#define PAS_DMA_COM_RXSTA_ACT 0x00000001 /* active */ -+ -+#define _PAS_DMA_TXCHAN_STRIDE 0x20 /* Size per channel */ -+#define _PAS_DMA_TXCHAN_TCMDSTA 0x300 /* Command / Status */ -+#define _PAS_DMA_TXCHAN_CFG 0x304 /* Configuration */ -+#define _PAS_DMA_TXCHAN_DSCRBU 0x308 /* Descriptor BU Allocation */ -+#define _PAS_DMA_TXCHAN_INCR 0x310 /* Descriptor increment */ -+#define _PAS_DMA_TXCHAN_CNT 0x314 /* Descriptor count/offset */ -+#define _PAS_DMA_TXCHAN_BASEL 0x318 /* Descriptor ring base (low) */ -+#define _PAS_DMA_TXCHAN_BASEU 0x31c /* (high) */ -+#define PAS_DMA_TXCHAN_TCMDSTA(c) (0x300+(c)*_PAS_DMA_TXCHAN_STRIDE) -+#define PAS_DMA_TXCHAN_TCMDSTA_EN 0x00000001 /* Enabled */ -+#define PAS_DMA_TXCHAN_TCMDSTA_ST 0x00000002 /* Stop interface */ -+#define PAS_DMA_TXCHAN_TCMDSTA_ACT 0x00010000 /* Active */ -+#define PAS_DMA_TXCHAN_CFG(c) (0x304+(c)*_PAS_DMA_TXCHAN_STRIDE) -+#define PAS_DMA_TXCHAN_CFG_TY_FUNC 0x00000002 /* Type = interface */ -+#define PAS_DMA_TXCHAN_CFG_TY_IFACE 0x00000000 /* Type = interface */ -+#define PAS_DMA_TXCHAN_CFG_TATTR_M 0x0000003c -+#define PAS_DMA_TXCHAN_CFG_TATTR_S 2 -+#define PAS_DMA_TXCHAN_CFG_TATTR(x) (((x) << PAS_DMA_TXCHAN_CFG_TATTR_S) & \ -+ PAS_DMA_TXCHAN_CFG_TATTR_M) -+#define PAS_DMA_TXCHAN_CFG_WT_M 0x000001c0 -+#define PAS_DMA_TXCHAN_CFG_WT_S 6 -+#define PAS_DMA_TXCHAN_CFG_WT(x) (((x) << PAS_DMA_TXCHAN_CFG_WT_S) & \ -+ PAS_DMA_TXCHAN_CFG_WT_M) -+#define PAS_DMA_TXCHAN_CFG_LPSQ_FAST 0x00000400 -+#define PAS_DMA_TXCHAN_CFG_LPDQ_FAST 0x00000800 -+#define PAS_DMA_TXCHAN_CFG_CF 0x00001000 /* Clean first line */ -+#define PAS_DMA_TXCHAN_CFG_CL 0x00002000 /* Clean last line */ -+#define PAS_DMA_TXCHAN_CFG_UP 0x00004000 /* update tx descr when sent */ -+#define PAS_DMA_TXCHAN_INCR(c) (0x310+(c)*_PAS_DMA_TXCHAN_STRIDE) -+#define PAS_DMA_TXCHAN_BASEL(c) (0x318+(c)*_PAS_DMA_TXCHAN_STRIDE) -+#define PAS_DMA_TXCHAN_BASEL_BRBL_M 0xffffffc0 -+#define PAS_DMA_TXCHAN_BASEL_BRBL_S 0 -+#define PAS_DMA_TXCHAN_BASEL_BRBL(x) (((x) << PAS_DMA_TXCHAN_BASEL_BRBL_S) & \ -+ PAS_DMA_TXCHAN_BASEL_BRBL_M) -+#define PAS_DMA_TXCHAN_BASEU(c) (0x31c+(c)*_PAS_DMA_TXCHAN_STRIDE) -+#define PAS_DMA_TXCHAN_BASEU_BRBH_M 0x00000fff -+#define PAS_DMA_TXCHAN_BASEU_BRBH_S 0 -+#define PAS_DMA_TXCHAN_BASEU_BRBH(x) (((x) << PAS_DMA_TXCHAN_BASEU_BRBH_S) & \ -+ PAS_DMA_TXCHAN_BASEU_BRBH_M) -+/* # of cache lines worth of buffer ring */ -+#define PAS_DMA_TXCHAN_BASEU_SIZ_M 0x3fff0000 -+#define PAS_DMA_TXCHAN_BASEU_SIZ_S 16 /* 0 = 16K */ -+#define PAS_DMA_TXCHAN_BASEU_SIZ(x) (((x) << PAS_DMA_TXCHAN_BASEU_SIZ_S) & \ -+ PAS_DMA_TXCHAN_BASEU_SIZ_M) -+ -+#define PAS_STATUS_PCNT_M 0x000000000000ffffull -+#define PAS_STATUS_PCNT_S 0 -+#define PAS_STATUS_DCNT_M 0x00000000ffff0000ull -+#define PAS_STATUS_DCNT_S 16 -+#define PAS_STATUS_BPCNT_M 0x0000ffff00000000ull -+#define PAS_STATUS_BPCNT_S 32 -+#define PAS_STATUS_CAUSE_M 0xf000000000000000ull -+#define PAS_STATUS_TIMER 0x1000000000000000ull -+#define PAS_STATUS_ERROR 0x2000000000000000ull -+#define PAS_STATUS_SOFT 0x4000000000000000ull -+#define PAS_STATUS_INT 0x8000000000000000ull -+ -+#define PAS_IOB_DMA_RXCH_CFG(i) (0x1100 + (i)*4) -+#define PAS_IOB_DMA_RXCH_CFG_CNTTH_M 0x00000fff -+#define PAS_IOB_DMA_RXCH_CFG_CNTTH_S 0 -+#define PAS_IOB_DMA_RXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_RXCH_CFG_CNTTH_S) & \ -+ PAS_IOB_DMA_RXCH_CFG_CNTTH_M) -+#define PAS_IOB_DMA_TXCH_CFG(i) (0x1200 + (i)*4) -+#define PAS_IOB_DMA_TXCH_CFG_CNTTH_M 0x00000fff -+#define PAS_IOB_DMA_TXCH_CFG_CNTTH_S 0 -+#define PAS_IOB_DMA_TXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_TXCH_CFG_CNTTH_S) & \ -+ PAS_IOB_DMA_TXCH_CFG_CNTTH_M) -+#define PAS_IOB_DMA_RXCH_STAT(i) (0x1300 + (i)*4) -+#define PAS_IOB_DMA_RXCH_STAT_INTGEN 0x00001000 -+#define PAS_IOB_DMA_RXCH_STAT_CNTDEL_M 0x00000fff -+#define PAS_IOB_DMA_RXCH_STAT_CNTDEL_S 0 -+#define PAS_IOB_DMA_RXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_RXCH_STAT_CNTDEL_S) &\ -+ PAS_IOB_DMA_RXCH_STAT_CNTDEL_M) -+#define PAS_IOB_DMA_TXCH_STAT(i) (0x1400 + (i)*4) -+#define PAS_IOB_DMA_TXCH_STAT_INTGEN 0x00001000 -+#define PAS_IOB_DMA_TXCH_STAT_CNTDEL_M 0x00000fff -+#define PAS_IOB_DMA_TXCH_STAT_CNTDEL_S 0 -+#define PAS_IOB_DMA_TXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_TXCH_STAT_CNTDEL_S) &\ -+ PAS_IOB_DMA_TXCH_STAT_CNTDEL_M) -+#define PAS_IOB_DMA_RXCH_RESET(i) (0x1500 + (i)*4) -+#define PAS_IOB_DMA_RXCH_RESET_PCNT_M 0xffff0000 -+#define PAS_IOB_DMA_RXCH_RESET_PCNT_S 16 -+#define PAS_IOB_DMA_RXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_RXCH_RESET_PCNT_S) & \ -+ PAS_IOB_DMA_RXCH_RESET_PCNT_M) -+#define PAS_IOB_DMA_RXCH_RESET_PCNTRST 0x00000020 -+#define PAS_IOB_DMA_RXCH_RESET_DCNTRST 0x00000010 -+#define PAS_IOB_DMA_RXCH_RESET_TINTC 0x00000008 -+#define PAS_IOB_DMA_RXCH_RESET_DINTC 0x00000004 -+#define PAS_IOB_DMA_RXCH_RESET_SINTC 0x00000002 -+#define PAS_IOB_DMA_RXCH_RESET_PINTC 0x00000001 -+#define PAS_IOB_DMA_TXCH_RESET(i) (0x1600 + (i)*4) -+#define PAS_IOB_DMA_TXCH_RESET_PCNT_M 0xffff0000 -+#define PAS_IOB_DMA_TXCH_RESET_PCNT_S 16 -+#define PAS_IOB_DMA_TXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_TXCH_RESET_PCNT_S) & \ -+ PAS_IOB_DMA_TXCH_RESET_PCNT_M) -+#define PAS_IOB_DMA_TXCH_RESET_PCNTRST 0x00000020 -+#define PAS_IOB_DMA_TXCH_RESET_DCNTRST 0x00000010 -+#define PAS_IOB_DMA_TXCH_RESET_TINTC 0x00000008 -+#define PAS_IOB_DMA_TXCH_RESET_DINTC 0x00000004 -+#define PAS_IOB_DMA_TXCH_RESET_SINTC 0x00000002 -+#define PAS_IOB_DMA_TXCH_RESET_PINTC 0x00000001 -+ -+#define PAS_IOB_DMA_COM_TIMEOUTCFG 0x1700 -+#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M 0x00ffffff -+#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S 0 -+#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(x) (((x) << PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S) & \ -+ PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M) -+ -+/* Transmit descriptor fields */ -+#define XCT_MACTX_T 0x8000000000000000ull -+#define XCT_MACTX_ST 0x4000000000000000ull -+#define XCT_MACTX_NORES 0x0000000000000000ull -+#define XCT_MACTX_8BRES 0x1000000000000000ull -+#define XCT_MACTX_24BRES 0x2000000000000000ull -+#define XCT_MACTX_40BRES 0x3000000000000000ull -+#define XCT_MACTX_I 0x0800000000000000ull -+#define XCT_MACTX_O 0x0400000000000000ull -+#define XCT_MACTX_E 0x0200000000000000ull -+#define XCT_MACTX_VLAN_M 0x0180000000000000ull -+#define XCT_MACTX_VLAN_NOP 0x0000000000000000ull -+#define XCT_MACTX_VLAN_REMOVE 0x0080000000000000ull -+#define XCT_MACTX_VLAN_INSERT 0x0100000000000000ull -+#define XCT_MACTX_VLAN_REPLACE 0x0180000000000000ull -+#define XCT_MACTX_CRC_M 0x0060000000000000ull -+#define XCT_MACTX_CRC_NOP 0x0000000000000000ull -+#define XCT_MACTX_CRC_INSERT 0x0020000000000000ull -+#define XCT_MACTX_CRC_PAD 0x0040000000000000ull -+#define XCT_MACTX_CRC_REPLACE 0x0060000000000000ull -+#define XCT_MACTX_SS 0x0010000000000000ull -+#define XCT_MACTX_LLEN_M 0x00007fff00000000ull -+#define XCT_MACTX_LLEN_S 32ull -+#define XCT_MACTX_LLEN(x) ((((long)(x)) << XCT_MACTX_LLEN_S) & \ -+ XCT_MACTX_LLEN_M) -+#define XCT_MACTX_IPH_M 0x00000000f8000000ull -+#define XCT_MACTX_IPH_S 27ull -+#define XCT_MACTX_IPH(x) ((((long)(x)) << XCT_MACTX_IPH_S) & \ -+ XCT_MACTX_IPH_M) -+#define XCT_MACTX_IPO_M 0x0000000007c00000ull -+#define XCT_MACTX_IPO_S 22ull -+#define XCT_MACTX_IPO(x) ((((long)(x)) << XCT_MACTX_IPO_S) & \ -+ XCT_MACTX_IPO_M) -+#define XCT_MACTX_CSUM_M 0x0000000000000060ull -+#define XCT_MACTX_CSUM_NOP 0x0000000000000000ull -+#define XCT_MACTX_CSUM_TCP 0x0000000000000040ull -+#define XCT_MACTX_CSUM_UDP 0x0000000000000060ull -+#define XCT_MACTX_V6 0x0000000000000010ull -+#define XCT_MACTX_C 0x0000000000000004ull -+#define XCT_MACTX_AL2 0x0000000000000002ull -+ -+#define XCT_PTR_T 0x8000000000000000ull -+#define XCT_PTR_LEN_M 0x7ffff00000000000ull -+#define XCT_PTR_LEN_S 44 -+#define XCT_PTR_LEN(x) ((((long)(x)) << XCT_PTR_LEN_S) & \ -+ XCT_PTR_LEN_M) -+#define XCT_PTR_ADDR_M 0x00000fffffffffffull -+#define XCT_PTR_ADDR_S 0 -+#define XCT_PTR_ADDR(x) ((((long)(x)) << XCT_PTR_ADDR_S) & \ -+ XCT_PTR_ADDR_M) -+ -+/* Function descriptor fields */ -+#define XCT_FUN_T 0x8000000000000000ull -+#define XCT_FUN_ST 0x4000000000000000ull -+#define XCT_FUN_NORES 0x0000000000000000ull -+#define XCT_FUN_8BRES 0x1000000000000000ull -+#define XCT_FUN_24BRES 0x2000000000000000ull -+#define XCT_FUN_40BRES 0x3000000000000000ull -+#define XCT_FUN_I 0x0800000000000000ull -+#define XCT_FUN_O 0x0400000000000000ull -+#define XCT_FUN_E 0x0200000000000000ull -+#define XCT_FUN_FUN_S 54 -+#define XCT_FUN_FUN_M 0x01c0000000000000ull -+#define XCT_FUN_FUN(num) ((((long)(num)) << XCT_FUN_FUN_S) & \ -+ XCT_FUN_FUN_M) -+#define XCT_FUN_CRM_NOP 0x0000000000000000ull -+#define XCT_FUN_CRM_SIG 0x0008000000000000ull -+#define XCT_FUN_CRM_ENC 0x0010000000000000ull -+#define XCT_FUN_CRM_DEC 0x0018000000000000ull -+#define XCT_FUN_CRM_SIG_ENC 0x0020000000000000ull -+#define XCT_FUN_CRM_ENC_SIG 0x0028000000000000ull -+#define XCT_FUN_CRM_SIG_DEC 0x0030000000000000ull -+#define XCT_FUN_CRM_DEC_SIG 0x0038000000000000ull -+#define XCT_FUN_LLEN_M 0x0007ffff00000000ull -+#define XCT_FUN_LLEN_S 32ULL -+#define XCT_FUN_LLEN(x) ((((long)(x)) << XCT_FUN_LLEN_S) & \ -+ XCT_FUN_LLEN_M) -+#define XCT_FUN_SHL_M 0x00000000f8000000ull -+#define XCT_FUN_SHL_S 27ull -+#define XCT_FUN_SHL(x) ((((long)(x)) << XCT_FUN_SHL_S) & \ -+ XCT_FUN_SHL_M) -+#define XCT_FUN_CHL_M 0x0000000007c00000ull -+#define XCT_FUN_CHL_S 22ull -+#define XCT_FUN_CHL(x) ((((long)(x)) << XCT_FUN_CHL_S) & \ -+ XCT_FUN_CHL_M) -+#define XCT_FUN_HSZ_M 0x00000000003c0000ull -+#define XCT_FUN_HSZ_S 18ull -+#define XCT_FUN_HSZ(x) ((((long)(x)) << XCT_FUN_HSZ_S) & \ -+ XCT_FUN_HSZ_M) -+#define XCT_FUN_ALG_DES 0x0000000000000000ull -+#define XCT_FUN_ALG_3DES 0x0000000000008000ull -+#define XCT_FUN_ALG_AES 0x0000000000010000ull -+#define XCT_FUN_ALG_ARC 0x0000000000018000ull -+#define XCT_FUN_ALG_KASUMI 0x0000000000020000ull -+#define XCT_FUN_BCM_ECB 0x0000000000000000ull -+#define XCT_FUN_BCM_CBC 0x0000000000001000ull -+#define XCT_FUN_BCM_CFB 0x0000000000002000ull -+#define XCT_FUN_BCM_OFB 0x0000000000003000ull -+#define XCT_FUN_BCM_CNT 0x0000000000003800ull -+#define XCT_FUN_BCM_KAS_F8 0x0000000000002800ull -+#define XCT_FUN_BCM_KAS_F9 0x0000000000001800ull -+#define XCT_FUN_BCP_NO_PAD 0x0000000000000000ull -+#define XCT_FUN_BCP_ZRO 0x0000000000000200ull -+#define XCT_FUN_BCP_PL 0x0000000000000400ull -+#define XCT_FUN_BCP_INCR 0x0000000000000600ull -+#define XCT_FUN_SIG_MD5 (0ull << 4) -+#define XCT_FUN_SIG_SHA1 (2ull << 4) -+#define XCT_FUN_SIG_HMAC_MD5 (8ull << 4) -+#define XCT_FUN_SIG_HMAC_SHA1 (10ull << 4) -+#define XCT_FUN_A 0x0000000000000008ull -+#define XCT_FUN_C 0x0000000000000004ull -+#define XCT_FUN_AL2 0x0000000000000002ull -+#define XCT_FUN_SE 0x0000000000000001ull -+ -+#define XCT_FUN_SRC_PTR(len, addr) (XCT_PTR_LEN(len) | XCT_PTR_ADDR(addr)) -+#define XCT_FUN_DST_PTR(len, addr) (XCT_FUN_SRC_PTR(len, addr) | \ -+ 0x8000000000000000ull) -+ -+#define XCT_CTRL_HDR_FUN_NUM_M 0x01c0000000000000ull -+#define XCT_CTRL_HDR_FUN_NUM_S 54 -+#define XCT_CTRL_HDR_LEN_M 0x0007ffff00000000ull -+#define XCT_CTRL_HDR_LEN_S 32 -+#define XCT_CTRL_HDR_REG_M 0x00000000000000ffull -+#define XCT_CTRL_HDR_REG_S 0 -+ -+#define XCT_CTRL_HDR(funcN,len,reg) (0x9400000000000000ull | \ -+ ((((long)(funcN)) << XCT_CTRL_HDR_FUN_NUM_S) \ -+ & XCT_CTRL_HDR_FUN_NUM_M) | \ -+ ((((long)(len)) << \ -+ XCT_CTRL_HDR_LEN_S) & XCT_CTRL_HDR_LEN_M) | \ -+ ((((long)(reg)) << \ -+ XCT_CTRL_HDR_REG_S) & XCT_CTRL_HDR_REG_M)) -+ -+/* Function config command options */ -+#define DMA_CALGO_DES 0x00 -+#define DMA_CALGO_3DES 0x01 -+#define DMA_CALGO_AES 0x02 -+#define DMA_CALGO_ARC 0x03 -+ -+#define DMA_FN_CIV0 0x02 -+#define DMA_FN_CIV1 0x03 -+#define DMA_FN_HKEY0 0x0a -+ -+#define XCT_PTR_ADDR_LEN(ptr) ((ptr) & XCT_PTR_ADDR_M), \ -+ (((ptr) & XCT_PTR_LEN_M) >> XCT_PTR_LEN_S) -+ -+#endif /* PASEMI_FNU_H */ -diff -Nur linux-2.6.39.orig/crypto/ocf/random.c linux-2.6.39/crypto/ocf/random.c ---- linux-2.6.39.orig/crypto/ocf/random.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/random.c 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,322 @@ -+/* -+ * A system independant way of adding entropy to the kernels pool -+ * this way the drivers can focus on the real work and we can take -+ * care of pushing it to the appropriate place in the kernel. -+ * -+ * This should be fast and callable from timers/interrupts -+ * -+ * Written by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * ALTERNATIVELY, provided that this notice is retained in full, this product -+ * may be distributed under the terms of the GNU General Public License (GPL), -+ * in which case the provisions of the GPL apply INSTEAD OF those given above. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ */ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#ifdef CONFIG_OCF_FIPS -+#include "rndtest.h" -+#endif -+ -+#ifndef HAS_RANDOM_INPUT_WAIT -+#error "Please do not enable OCF_RANDOMHARVEST unless you have applied patches" -+#endif -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) -+#include -+#define kill_proc(p,s,v) send_sig(s,find_task_by_vpid(p),0) -+#endif -+ -+/* -+ * a hack to access the debug levels from the crypto driver -+ */ -+extern int crypto_debug; -+#define debug crypto_debug -+ -+/* -+ * a list of all registered random providers -+ */ -+static LIST_HEAD(random_ops); -+static int started = 0; -+static int initted = 0; -+ -+struct random_op { -+ struct list_head random_list; -+ u_int32_t driverid; -+ int (*read_random)(void *arg, u_int32_t *buf, int len); -+ void *arg; -+}; -+ -+static int random_proc(void *arg); -+ -+static pid_t randomproc = (pid_t) -1; -+static spinlock_t random_lock; -+ -+/* -+ * just init the spin locks -+ */ -+static int -+crypto_random_init(void) -+{ -+ spin_lock_init(&random_lock); -+ initted = 1; -+ return(0); -+} -+ -+/* -+ * Add the given random reader to our list (if not present) -+ * and start the thread (if not already started) -+ * -+ * we have to assume that driver id is ok for now -+ */ -+int -+crypto_rregister( -+ u_int32_t driverid, -+ int (*read_random)(void *arg, u_int32_t *buf, int len), -+ void *arg) -+{ -+ unsigned long flags; -+ int ret = 0; -+ struct random_op *rops, *tmp; -+ -+ dprintk("%s,%d: %s(0x%x, %p, %p)\n", __FILE__, __LINE__, -+ __FUNCTION__, driverid, read_random, arg); -+ -+ if (!initted) -+ crypto_random_init(); -+ -+#if 0 -+ struct cryptocap *cap; -+ -+ cap = crypto_checkdriver(driverid); -+ if (!cap) -+ return EINVAL; -+#endif -+ -+ list_for_each_entry_safe(rops, tmp, &random_ops, random_list) { -+ if (rops->driverid == driverid && rops->read_random == read_random) -+ return EEXIST; -+ } -+ -+ rops = (struct random_op *) kmalloc(sizeof(*rops), GFP_KERNEL); -+ if (!rops) -+ return ENOMEM; -+ -+ rops->driverid = driverid; -+ rops->read_random = read_random; -+ rops->arg = arg; -+ -+ spin_lock_irqsave(&random_lock, flags); -+ list_add_tail(&rops->random_list, &random_ops); -+ if (!started) { -+ randomproc = kernel_thread(random_proc, NULL, CLONE_FS|CLONE_FILES); -+ if (randomproc < 0) { -+ ret = randomproc; -+ printk("crypto: crypto_rregister cannot start random thread; " -+ "error %d", ret); -+ } else -+ started = 1; -+ } -+ spin_unlock_irqrestore(&random_lock, flags); -+ -+ return ret; -+} -+EXPORT_SYMBOL(crypto_rregister); -+ -+int -+crypto_runregister_all(u_int32_t driverid) -+{ -+ struct random_op *rops, *tmp; -+ unsigned long flags; -+ -+ dprintk("%s,%d: %s(0x%x)\n", __FILE__, __LINE__, __FUNCTION__, driverid); -+ -+ list_for_each_entry_safe(rops, tmp, &random_ops, random_list) { -+ if (rops->driverid == driverid) { -+ list_del(&rops->random_list); -+ kfree(rops); -+ } -+ } -+ -+ spin_lock_irqsave(&random_lock, flags); -+ if (list_empty(&random_ops) && started) -+ kill_proc(randomproc, SIGKILL, 1); -+ spin_unlock_irqrestore(&random_lock, flags); -+ return(0); -+} -+EXPORT_SYMBOL(crypto_runregister_all); -+ -+/* -+ * while we can add entropy to random.c continue to read random data from -+ * the drivers and push it to random. -+ */ -+static int -+random_proc(void *arg) -+{ -+ int n; -+ int wantcnt; -+ int bufcnt = 0; -+ int retval = 0; -+ int *buf = NULL; -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ daemonize(); -+ spin_lock_irq(¤t->sigmask_lock); -+ sigemptyset(¤t->blocked); -+ recalc_sigpending(current); -+ spin_unlock_irq(¤t->sigmask_lock); -+ sprintf(current->comm, "ocf-random"); -+#else -+ daemonize("ocf-random"); -+ allow_signal(SIGKILL); -+#endif -+ -+ (void) get_fs(); -+ set_fs(get_ds()); -+ -+#ifdef CONFIG_OCF_FIPS -+#define NUM_INT (RNDTEST_NBYTES/sizeof(int)) -+#else -+#define NUM_INT 32 -+#endif -+ -+ /* -+ * some devices can transferr their RNG data direct into memory, -+ * so make sure it is device friendly -+ */ -+ buf = kmalloc(NUM_INT * sizeof(int), GFP_DMA); -+ if (NULL == buf) { -+ printk("crypto: RNG could not allocate memory\n"); -+ retval = -ENOMEM; -+ goto bad_alloc; -+ } -+ -+ wantcnt = NUM_INT; /* start by adding some entropy */ -+ -+ /* -+ * its possible due to errors or driver removal that we no longer -+ * have anything to do, if so exit or we will consume all the CPU -+ * doing nothing -+ */ -+ while (!list_empty(&random_ops)) { -+ struct random_op *rops, *tmp; -+ -+#ifdef CONFIG_OCF_FIPS -+ if (wantcnt) -+ wantcnt = NUM_INT; /* FIPs mode can do 20000 bits or none */ -+#endif -+ -+ /* see if we can get enough entropy to make the world -+ * a better place. -+ */ -+ while (bufcnt < wantcnt && bufcnt < NUM_INT) { -+ list_for_each_entry_safe(rops, tmp, &random_ops, random_list) { -+ -+ n = (*rops->read_random)(rops->arg, &buf[bufcnt], -+ NUM_INT - bufcnt); -+ -+ /* on failure remove the random number generator */ -+ if (n == -1) { -+ list_del(&rops->random_list); -+ printk("crypto: RNG (driverid=0x%x) failed, disabling\n", -+ rops->driverid); -+ kfree(rops); -+ } else if (n > 0) -+ bufcnt += n; -+ } -+ /* give up CPU for a bit, just in case as this is a loop */ -+ schedule(); -+ } -+ -+ -+#ifdef CONFIG_OCF_FIPS -+ if (bufcnt > 0 && rndtest_buf((unsigned char *) &buf[0])) { -+ dprintk("crypto: buffer had fips errors, discarding\n"); -+ bufcnt = 0; -+ } -+#endif -+ -+ /* -+ * if we have a certified buffer, we can send some data -+ * to /dev/random and move along -+ */ -+ if (bufcnt > 0) { -+ /* add what we have */ -+ random_input_words(buf, bufcnt, bufcnt*sizeof(int)*8); -+ bufcnt = 0; -+ } -+ -+ /* give up CPU for a bit so we don't hog while filling */ -+ schedule(); -+ -+ /* wait for needing more */ -+ wantcnt = random_input_wait(); -+ -+ if (wantcnt <= 0) -+ wantcnt = 0; /* try to get some info again */ -+ else -+ /* round up to one word or we can loop forever */ -+ wantcnt = (wantcnt + (sizeof(int)*8)) / (sizeof(int)*8); -+ if (wantcnt > NUM_INT) { -+ wantcnt = NUM_INT; -+ } -+ -+ if (signal_pending(current)) { -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ spin_lock_irq(¤t->sigmask_lock); -+#endif -+ flush_signals(current); -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ spin_unlock_irq(¤t->sigmask_lock); -+#endif -+ } -+ } -+ -+ kfree(buf); -+ -+bad_alloc: -+ spin_lock_irq(&random_lock); -+ randomproc = (pid_t) -1; -+ started = 0; -+ spin_unlock_irq(&random_lock); -+ -+ return retval; -+} -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/rndtest.c linux-2.6.39/crypto/ocf/rndtest.c ---- linux-2.6.39.orig/crypto/ocf/rndtest.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/rndtest.c 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,300 @@ -+/* $OpenBSD$ */ -+ -+/* -+ * OCF/Linux port done by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * The license and original author are listed below. -+ * -+ * Copyright (c) 2002 Jason L. Wright (jason@thought.net) -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. All advertising materials mentioning features or use of this software -+ * must display the following acknowledgement: -+ * This product includes software developed by Jason L. Wright -+ * 4. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "rndtest.h" -+ -+static struct rndtest_stats rndstats; -+ -+static void rndtest_test(struct rndtest_state *); -+ -+/* The tests themselves */ -+static int rndtest_monobit(struct rndtest_state *); -+static int rndtest_runs(struct rndtest_state *); -+static int rndtest_longruns(struct rndtest_state *); -+static int rndtest_chi_4(struct rndtest_state *); -+ -+static int rndtest_runs_check(struct rndtest_state *, int, int *); -+static void rndtest_runs_record(struct rndtest_state *, int, int *); -+ -+static const struct rndtest_testfunc { -+ int (*test)(struct rndtest_state *); -+} rndtest_funcs[] = { -+ { rndtest_monobit }, -+ { rndtest_runs }, -+ { rndtest_chi_4 }, -+ { rndtest_longruns }, -+}; -+ -+#define RNDTEST_NTESTS (sizeof(rndtest_funcs)/sizeof(rndtest_funcs[0])) -+ -+static void -+rndtest_test(struct rndtest_state *rsp) -+{ -+ int i, rv = 0; -+ -+ rndstats.rst_tests++; -+ for (i = 0; i < RNDTEST_NTESTS; i++) -+ rv |= (*rndtest_funcs[i].test)(rsp); -+ rsp->rs_discard = (rv != 0); -+} -+ -+ -+extern int crypto_debug; -+#define rndtest_verbose 2 -+#define rndtest_report(rsp, failure, fmt, a...) \ -+ { if (failure || crypto_debug) { printk("rng_test: " fmt "\n", a); } else; } -+ -+#define RNDTEST_MONOBIT_MINONES 9725 -+#define RNDTEST_MONOBIT_MAXONES 10275 -+ -+static int -+rndtest_monobit(struct rndtest_state *rsp) -+{ -+ int i, ones = 0, j; -+ u_int8_t r; -+ -+ for (i = 0; i < RNDTEST_NBYTES; i++) { -+ r = rsp->rs_buf[i]; -+ for (j = 0; j < 8; j++, r <<= 1) -+ if (r & 0x80) -+ ones++; -+ } -+ if (ones > RNDTEST_MONOBIT_MINONES && -+ ones < RNDTEST_MONOBIT_MAXONES) { -+ if (rndtest_verbose > 1) -+ rndtest_report(rsp, 0, "monobit pass (%d < %d < %d)", -+ RNDTEST_MONOBIT_MINONES, ones, -+ RNDTEST_MONOBIT_MAXONES); -+ return (0); -+ } else { -+ if (rndtest_verbose) -+ rndtest_report(rsp, 1, -+ "monobit failed (%d ones)", ones); -+ rndstats.rst_monobit++; -+ return (-1); -+ } -+} -+ -+#define RNDTEST_RUNS_NINTERVAL 6 -+ -+static const struct rndtest_runs_tabs { -+ u_int16_t min, max; -+} rndtest_runs_tab[] = { -+ { 2343, 2657 }, -+ { 1135, 1365 }, -+ { 542, 708 }, -+ { 251, 373 }, -+ { 111, 201 }, -+ { 111, 201 }, -+}; -+ -+static int -+rndtest_runs(struct rndtest_state *rsp) -+{ -+ int i, j, ones, zeros, rv = 0; -+ int onei[RNDTEST_RUNS_NINTERVAL], zeroi[RNDTEST_RUNS_NINTERVAL]; -+ u_int8_t c; -+ -+ bzero(onei, sizeof(onei)); -+ bzero(zeroi, sizeof(zeroi)); -+ ones = zeros = 0; -+ for (i = 0; i < RNDTEST_NBYTES; i++) { -+ c = rsp->rs_buf[i]; -+ for (j = 0; j < 8; j++, c <<= 1) { -+ if (c & 0x80) { -+ ones++; -+ rndtest_runs_record(rsp, zeros, zeroi); -+ zeros = 0; -+ } else { -+ zeros++; -+ rndtest_runs_record(rsp, ones, onei); -+ ones = 0; -+ } -+ } -+ } -+ rndtest_runs_record(rsp, ones, onei); -+ rndtest_runs_record(rsp, zeros, zeroi); -+ -+ rv |= rndtest_runs_check(rsp, 0, zeroi); -+ rv |= rndtest_runs_check(rsp, 1, onei); -+ -+ if (rv) -+ rndstats.rst_runs++; -+ -+ return (rv); -+} -+ -+static void -+rndtest_runs_record(struct rndtest_state *rsp, int len, int *intrv) -+{ -+ if (len == 0) -+ return; -+ if (len > RNDTEST_RUNS_NINTERVAL) -+ len = RNDTEST_RUNS_NINTERVAL; -+ len -= 1; -+ intrv[len]++; -+} -+ -+static int -+rndtest_runs_check(struct rndtest_state *rsp, int val, int *src) -+{ -+ int i, rv = 0; -+ -+ for (i = 0; i < RNDTEST_RUNS_NINTERVAL; i++) { -+ if (src[i] < rndtest_runs_tab[i].min || -+ src[i] > rndtest_runs_tab[i].max) { -+ rndtest_report(rsp, 1, -+ "%s interval %d failed (%d, %d-%d)", -+ val ? "ones" : "zeros", -+ i + 1, src[i], rndtest_runs_tab[i].min, -+ rndtest_runs_tab[i].max); -+ rv = -1; -+ } else { -+ rndtest_report(rsp, 0, -+ "runs pass %s interval %d (%d < %d < %d)", -+ val ? "ones" : "zeros", -+ i + 1, rndtest_runs_tab[i].min, src[i], -+ rndtest_runs_tab[i].max); -+ } -+ } -+ return (rv); -+} -+ -+static int -+rndtest_longruns(struct rndtest_state *rsp) -+{ -+ int i, j, ones = 0, zeros = 0, maxones = 0, maxzeros = 0; -+ u_int8_t c; -+ -+ for (i = 0; i < RNDTEST_NBYTES; i++) { -+ c = rsp->rs_buf[i]; -+ for (j = 0; j < 8; j++, c <<= 1) { -+ if (c & 0x80) { -+ zeros = 0; -+ ones++; -+ if (ones > maxones) -+ maxones = ones; -+ } else { -+ ones = 0; -+ zeros++; -+ if (zeros > maxzeros) -+ maxzeros = zeros; -+ } -+ } -+ } -+ -+ if (maxones < 26 && maxzeros < 26) { -+ rndtest_report(rsp, 0, "longruns pass (%d ones, %d zeros)", -+ maxones, maxzeros); -+ return (0); -+ } else { -+ rndtest_report(rsp, 1, "longruns fail (%d ones, %d zeros)", -+ maxones, maxzeros); -+ rndstats.rst_longruns++; -+ return (-1); -+ } -+} -+ -+/* -+ * chi^2 test over 4 bits: (this is called the poker test in FIPS 140-2, -+ * but it is really the chi^2 test over 4 bits (the poker test as described -+ * by Knuth vol 2 is something different, and I take him as authoritative -+ * on nomenclature over NIST). -+ */ -+#define RNDTEST_CHI4_K 16 -+#define RNDTEST_CHI4_K_MASK (RNDTEST_CHI4_K - 1) -+ -+/* -+ * The unnormalized values are used so that we don't have to worry about -+ * fractional precision. The "real" value is found by: -+ * (V - 1562500) * (16 / 5000) = Vn (where V is the unnormalized value) -+ */ -+#define RNDTEST_CHI4_VMIN 1563181 /* 2.1792 */ -+#define RNDTEST_CHI4_VMAX 1576929 /* 46.1728 */ -+ -+static int -+rndtest_chi_4(struct rndtest_state *rsp) -+{ -+ unsigned int freq[RNDTEST_CHI4_K], i, sum; -+ -+ for (i = 0; i < RNDTEST_CHI4_K; i++) -+ freq[i] = 0; -+ -+ /* Get number of occurances of each 4 bit pattern */ -+ for (i = 0; i < RNDTEST_NBYTES; i++) { -+ freq[(rsp->rs_buf[i] >> 4) & RNDTEST_CHI4_K_MASK]++; -+ freq[(rsp->rs_buf[i] >> 0) & RNDTEST_CHI4_K_MASK]++; -+ } -+ -+ for (i = 0, sum = 0; i < RNDTEST_CHI4_K; i++) -+ sum += freq[i] * freq[i]; -+ -+ if (sum >= 1563181 && sum <= 1576929) { -+ rndtest_report(rsp, 0, "chi^2(4): pass (sum %u)", sum); -+ return (0); -+ } else { -+ rndtest_report(rsp, 1, "chi^2(4): failed (sum %u)", sum); -+ rndstats.rst_chi++; -+ return (-1); -+ } -+} -+ -+int -+rndtest_buf(unsigned char *buf) -+{ -+ struct rndtest_state rsp; -+ -+ memset(&rsp, 0, sizeof(rsp)); -+ rsp.rs_buf = buf; -+ rndtest_test(&rsp); -+ return(rsp.rs_discard); -+} -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/rndtest.h linux-2.6.39/crypto/ocf/rndtest.h ---- linux-2.6.39.orig/crypto/ocf/rndtest.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/rndtest.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,54 @@ -+/* $FreeBSD: src/sys/dev/rndtest/rndtest.h,v 1.1 2003/03/11 22:54:44 sam Exp $ */ -+/* $OpenBSD$ */ -+ -+/* -+ * Copyright (c) 2002 Jason L. Wright (jason@thought.net) -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. All advertising materials mentioning features or use of this software -+ * must display the following acknowledgement: -+ * This product includes software developed by Jason L. Wright -+ * 4. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/* Some of the tests depend on these values */ -+#define RNDTEST_NBYTES 2500 -+#define RNDTEST_NBITS (8 * RNDTEST_NBYTES) -+ -+struct rndtest_state { -+ int rs_discard; /* discard/accept random data */ -+ u_int8_t *rs_buf; -+}; -+ -+struct rndtest_stats { -+ u_int32_t rst_discard; /* number of bytes discarded */ -+ u_int32_t rst_tests; /* number of test runs */ -+ u_int32_t rst_monobit; /* monobit test failures */ -+ u_int32_t rst_runs; /* 0/1 runs failures */ -+ u_int32_t rst_longruns; /* longruns failures */ -+ u_int32_t rst_chi; /* chi^2 failures */ -+}; -+ -+extern int rndtest_buf(unsigned char *buf); -diff -Nur linux-2.6.39.orig/crypto/ocf/safe/Makefile linux-2.6.39/crypto/ocf/safe/Makefile ---- linux-2.6.39.orig/crypto/ocf/safe/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/safe/Makefile 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,12 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+obj-$(CONFIG_OCF_SAFE) += safe.o -+ -+obj ?= . -+EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/safe/md5.c linux-2.6.39/crypto/ocf/safe/md5.c ---- linux-2.6.39.orig/crypto/ocf/safe/md5.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/safe/md5.c 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,308 @@ -+/* $KAME: md5.c,v 1.5 2000/11/08 06:13:08 itojun Exp $ */ -+/* -+ * Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. Neither the name of the project nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ */ -+ -+#if 0 -+#include -+__FBSDID("$FreeBSD: src/sys/crypto/md5.c,v 1.9 2004/01/27 19:49:19 des Exp $"); -+ -+#include -+#include -+#include -+#include -+#include -+#endif -+ -+#define SHIFT(X, s) (((X) << (s)) | ((X) >> (32 - (s)))) -+ -+#define F(X, Y, Z) (((X) & (Y)) | ((~X) & (Z))) -+#define G(X, Y, Z) (((X) & (Z)) | ((Y) & (~Z))) -+#define H(X, Y, Z) ((X) ^ (Y) ^ (Z)) -+#define I(X, Y, Z) ((Y) ^ ((X) | (~Z))) -+ -+#define ROUND1(a, b, c, d, k, s, i) { \ -+ (a) = (a) + F((b), (c), (d)) + X[(k)] + T[(i)]; \ -+ (a) = SHIFT((a), (s)); \ -+ (a) = (b) + (a); \ -+} -+ -+#define ROUND2(a, b, c, d, k, s, i) { \ -+ (a) = (a) + G((b), (c), (d)) + X[(k)] + T[(i)]; \ -+ (a) = SHIFT((a), (s)); \ -+ (a) = (b) + (a); \ -+} -+ -+#define ROUND3(a, b, c, d, k, s, i) { \ -+ (a) = (a) + H((b), (c), (d)) + X[(k)] + T[(i)]; \ -+ (a) = SHIFT((a), (s)); \ -+ (a) = (b) + (a); \ -+} -+ -+#define ROUND4(a, b, c, d, k, s, i) { \ -+ (a) = (a) + I((b), (c), (d)) + X[(k)] + T[(i)]; \ -+ (a) = SHIFT((a), (s)); \ -+ (a) = (b) + (a); \ -+} -+ -+#define Sa 7 -+#define Sb 12 -+#define Sc 17 -+#define Sd 22 -+ -+#define Se 5 -+#define Sf 9 -+#define Sg 14 -+#define Sh 20 -+ -+#define Si 4 -+#define Sj 11 -+#define Sk 16 -+#define Sl 23 -+ -+#define Sm 6 -+#define Sn 10 -+#define So 15 -+#define Sp 21 -+ -+#define MD5_A0 0x67452301 -+#define MD5_B0 0xefcdab89 -+#define MD5_C0 0x98badcfe -+#define MD5_D0 0x10325476 -+ -+/* Integer part of 4294967296 times abs(sin(i)), where i is in radians. */ -+static const u_int32_t T[65] = { -+ 0, -+ 0xd76aa478, 0xe8c7b756, 0x242070db, 0xc1bdceee, -+ 0xf57c0faf, 0x4787c62a, 0xa8304613, 0xfd469501, -+ 0x698098d8, 0x8b44f7af, 0xffff5bb1, 0x895cd7be, -+ 0x6b901122, 0xfd987193, 0xa679438e, 0x49b40821, -+ -+ 0xf61e2562, 0xc040b340, 0x265e5a51, 0xe9b6c7aa, -+ 0xd62f105d, 0x2441453, 0xd8a1e681, 0xe7d3fbc8, -+ 0x21e1cde6, 0xc33707d6, 0xf4d50d87, 0x455a14ed, -+ 0xa9e3e905, 0xfcefa3f8, 0x676f02d9, 0x8d2a4c8a, -+ -+ 0xfffa3942, 0x8771f681, 0x6d9d6122, 0xfde5380c, -+ 0xa4beea44, 0x4bdecfa9, 0xf6bb4b60, 0xbebfbc70, -+ 0x289b7ec6, 0xeaa127fa, 0xd4ef3085, 0x4881d05, -+ 0xd9d4d039, 0xe6db99e5, 0x1fa27cf8, 0xc4ac5665, -+ -+ 0xf4292244, 0x432aff97, 0xab9423a7, 0xfc93a039, -+ 0x655b59c3, 0x8f0ccc92, 0xffeff47d, 0x85845dd1, -+ 0x6fa87e4f, 0xfe2ce6e0, 0xa3014314, 0x4e0811a1, -+ 0xf7537e82, 0xbd3af235, 0x2ad7d2bb, 0xeb86d391, -+}; -+ -+static const u_int8_t md5_paddat[MD5_BUFLEN] = { -+ 0x80, 0, 0, 0, 0, 0, 0, 0, -+ 0, 0, 0, 0, 0, 0, 0, 0, -+ 0, 0, 0, 0, 0, 0, 0, 0, -+ 0, 0, 0, 0, 0, 0, 0, 0, -+ 0, 0, 0, 0, 0, 0, 0, 0, -+ 0, 0, 0, 0, 0, 0, 0, 0, -+ 0, 0, 0, 0, 0, 0, 0, 0, -+ 0, 0, 0, 0, 0, 0, 0, 0, -+}; -+ -+static void md5_calc(u_int8_t *, md5_ctxt *); -+ -+void md5_init(ctxt) -+ md5_ctxt *ctxt; -+{ -+ ctxt->md5_n = 0; -+ ctxt->md5_i = 0; -+ ctxt->md5_sta = MD5_A0; -+ ctxt->md5_stb = MD5_B0; -+ ctxt->md5_stc = MD5_C0; -+ ctxt->md5_std = MD5_D0; -+ bzero(ctxt->md5_buf, sizeof(ctxt->md5_buf)); -+} -+ -+void md5_loop(ctxt, input, len) -+ md5_ctxt *ctxt; -+ u_int8_t *input; -+ u_int len; /* number of bytes */ -+{ -+ u_int gap, i; -+ -+ ctxt->md5_n += len * 8; /* byte to bit */ -+ gap = MD5_BUFLEN - ctxt->md5_i; -+ -+ if (len >= gap) { -+ bcopy((void *)input, (void *)(ctxt->md5_buf + ctxt->md5_i), -+ gap); -+ md5_calc(ctxt->md5_buf, ctxt); -+ -+ for (i = gap; i + MD5_BUFLEN <= len; i += MD5_BUFLEN) { -+ md5_calc((u_int8_t *)(input + i), ctxt); -+ } -+ -+ ctxt->md5_i = len - i; -+ bcopy((void *)(input + i), (void *)ctxt->md5_buf, ctxt->md5_i); -+ } else { -+ bcopy((void *)input, (void *)(ctxt->md5_buf + ctxt->md5_i), -+ len); -+ ctxt->md5_i += len; -+ } -+} -+ -+void md5_pad(ctxt) -+ md5_ctxt *ctxt; -+{ -+ u_int gap; -+ -+ /* Don't count up padding. Keep md5_n. */ -+ gap = MD5_BUFLEN - ctxt->md5_i; -+ if (gap > 8) { -+ bcopy(md5_paddat, -+ (void *)(ctxt->md5_buf + ctxt->md5_i), -+ gap - sizeof(ctxt->md5_n)); -+ } else { -+ /* including gap == 8 */ -+ bcopy(md5_paddat, (void *)(ctxt->md5_buf + ctxt->md5_i), -+ gap); -+ md5_calc(ctxt->md5_buf, ctxt); -+ bcopy((md5_paddat + gap), -+ (void *)ctxt->md5_buf, -+ MD5_BUFLEN - sizeof(ctxt->md5_n)); -+ } -+ -+ /* 8 byte word */ -+#if BYTE_ORDER == LITTLE_ENDIAN -+ bcopy(&ctxt->md5_n8[0], &ctxt->md5_buf[56], 8); -+#endif -+#if BYTE_ORDER == BIG_ENDIAN -+ ctxt->md5_buf[56] = ctxt->md5_n8[7]; -+ ctxt->md5_buf[57] = ctxt->md5_n8[6]; -+ ctxt->md5_buf[58] = ctxt->md5_n8[5]; -+ ctxt->md5_buf[59] = ctxt->md5_n8[4]; -+ ctxt->md5_buf[60] = ctxt->md5_n8[3]; -+ ctxt->md5_buf[61] = ctxt->md5_n8[2]; -+ ctxt->md5_buf[62] = ctxt->md5_n8[1]; -+ ctxt->md5_buf[63] = ctxt->md5_n8[0]; -+#endif -+ -+ md5_calc(ctxt->md5_buf, ctxt); -+} -+ -+void md5_result(digest, ctxt) -+ u_int8_t *digest; -+ md5_ctxt *ctxt; -+{ -+ /* 4 byte words */ -+#if BYTE_ORDER == LITTLE_ENDIAN -+ bcopy(&ctxt->md5_st8[0], digest, 16); -+#endif -+#if BYTE_ORDER == BIG_ENDIAN -+ digest[ 0] = ctxt->md5_st8[ 3]; digest[ 1] = ctxt->md5_st8[ 2]; -+ digest[ 2] = ctxt->md5_st8[ 1]; digest[ 3] = ctxt->md5_st8[ 0]; -+ digest[ 4] = ctxt->md5_st8[ 7]; digest[ 5] = ctxt->md5_st8[ 6]; -+ digest[ 6] = ctxt->md5_st8[ 5]; digest[ 7] = ctxt->md5_st8[ 4]; -+ digest[ 8] = ctxt->md5_st8[11]; digest[ 9] = ctxt->md5_st8[10]; -+ digest[10] = ctxt->md5_st8[ 9]; digest[11] = ctxt->md5_st8[ 8]; -+ digest[12] = ctxt->md5_st8[15]; digest[13] = ctxt->md5_st8[14]; -+ digest[14] = ctxt->md5_st8[13]; digest[15] = ctxt->md5_st8[12]; -+#endif -+} -+ -+static void md5_calc(b64, ctxt) -+ u_int8_t *b64; -+ md5_ctxt *ctxt; -+{ -+ u_int32_t A = ctxt->md5_sta; -+ u_int32_t B = ctxt->md5_stb; -+ u_int32_t C = ctxt->md5_stc; -+ u_int32_t D = ctxt->md5_std; -+#if BYTE_ORDER == LITTLE_ENDIAN -+ u_int32_t *X = (u_int32_t *)b64; -+#endif -+#if BYTE_ORDER == BIG_ENDIAN -+ /* 4 byte words */ -+ /* what a brute force but fast! */ -+ u_int32_t X[16]; -+ u_int8_t *y = (u_int8_t *)X; -+ y[ 0] = b64[ 3]; y[ 1] = b64[ 2]; y[ 2] = b64[ 1]; y[ 3] = b64[ 0]; -+ y[ 4] = b64[ 7]; y[ 5] = b64[ 6]; y[ 6] = b64[ 5]; y[ 7] = b64[ 4]; -+ y[ 8] = b64[11]; y[ 9] = b64[10]; y[10] = b64[ 9]; y[11] = b64[ 8]; -+ y[12] = b64[15]; y[13] = b64[14]; y[14] = b64[13]; y[15] = b64[12]; -+ y[16] = b64[19]; y[17] = b64[18]; y[18] = b64[17]; y[19] = b64[16]; -+ y[20] = b64[23]; y[21] = b64[22]; y[22] = b64[21]; y[23] = b64[20]; -+ y[24] = b64[27]; y[25] = b64[26]; y[26] = b64[25]; y[27] = b64[24]; -+ y[28] = b64[31]; y[29] = b64[30]; y[30] = b64[29]; y[31] = b64[28]; -+ y[32] = b64[35]; y[33] = b64[34]; y[34] = b64[33]; y[35] = b64[32]; -+ y[36] = b64[39]; y[37] = b64[38]; y[38] = b64[37]; y[39] = b64[36]; -+ y[40] = b64[43]; y[41] = b64[42]; y[42] = b64[41]; y[43] = b64[40]; -+ y[44] = b64[47]; y[45] = b64[46]; y[46] = b64[45]; y[47] = b64[44]; -+ y[48] = b64[51]; y[49] = b64[50]; y[50] = b64[49]; y[51] = b64[48]; -+ y[52] = b64[55]; y[53] = b64[54]; y[54] = b64[53]; y[55] = b64[52]; -+ y[56] = b64[59]; y[57] = b64[58]; y[58] = b64[57]; y[59] = b64[56]; -+ y[60] = b64[63]; y[61] = b64[62]; y[62] = b64[61]; y[63] = b64[60]; -+#endif -+ -+ ROUND1(A, B, C, D, 0, Sa, 1); ROUND1(D, A, B, C, 1, Sb, 2); -+ ROUND1(C, D, A, B, 2, Sc, 3); ROUND1(B, C, D, A, 3, Sd, 4); -+ ROUND1(A, B, C, D, 4, Sa, 5); ROUND1(D, A, B, C, 5, Sb, 6); -+ ROUND1(C, D, A, B, 6, Sc, 7); ROUND1(B, C, D, A, 7, Sd, 8); -+ ROUND1(A, B, C, D, 8, Sa, 9); ROUND1(D, A, B, C, 9, Sb, 10); -+ ROUND1(C, D, A, B, 10, Sc, 11); ROUND1(B, C, D, A, 11, Sd, 12); -+ ROUND1(A, B, C, D, 12, Sa, 13); ROUND1(D, A, B, C, 13, Sb, 14); -+ ROUND1(C, D, A, B, 14, Sc, 15); ROUND1(B, C, D, A, 15, Sd, 16); -+ -+ ROUND2(A, B, C, D, 1, Se, 17); ROUND2(D, A, B, C, 6, Sf, 18); -+ ROUND2(C, D, A, B, 11, Sg, 19); ROUND2(B, C, D, A, 0, Sh, 20); -+ ROUND2(A, B, C, D, 5, Se, 21); ROUND2(D, A, B, C, 10, Sf, 22); -+ ROUND2(C, D, A, B, 15, Sg, 23); ROUND2(B, C, D, A, 4, Sh, 24); -+ ROUND2(A, B, C, D, 9, Se, 25); ROUND2(D, A, B, C, 14, Sf, 26); -+ ROUND2(C, D, A, B, 3, Sg, 27); ROUND2(B, C, D, A, 8, Sh, 28); -+ ROUND2(A, B, C, D, 13, Se, 29); ROUND2(D, A, B, C, 2, Sf, 30); -+ ROUND2(C, D, A, B, 7, Sg, 31); ROUND2(B, C, D, A, 12, Sh, 32); -+ -+ ROUND3(A, B, C, D, 5, Si, 33); ROUND3(D, A, B, C, 8, Sj, 34); -+ ROUND3(C, D, A, B, 11, Sk, 35); ROUND3(B, C, D, A, 14, Sl, 36); -+ ROUND3(A, B, C, D, 1, Si, 37); ROUND3(D, A, B, C, 4, Sj, 38); -+ ROUND3(C, D, A, B, 7, Sk, 39); ROUND3(B, C, D, A, 10, Sl, 40); -+ ROUND3(A, B, C, D, 13, Si, 41); ROUND3(D, A, B, C, 0, Sj, 42); -+ ROUND3(C, D, A, B, 3, Sk, 43); ROUND3(B, C, D, A, 6, Sl, 44); -+ ROUND3(A, B, C, D, 9, Si, 45); ROUND3(D, A, B, C, 12, Sj, 46); -+ ROUND3(C, D, A, B, 15, Sk, 47); ROUND3(B, C, D, A, 2, Sl, 48); -+ -+ ROUND4(A, B, C, D, 0, Sm, 49); ROUND4(D, A, B, C, 7, Sn, 50); -+ ROUND4(C, D, A, B, 14, So, 51); ROUND4(B, C, D, A, 5, Sp, 52); -+ ROUND4(A, B, C, D, 12, Sm, 53); ROUND4(D, A, B, C, 3, Sn, 54); -+ ROUND4(C, D, A, B, 10, So, 55); ROUND4(B, C, D, A, 1, Sp, 56); -+ ROUND4(A, B, C, D, 8, Sm, 57); ROUND4(D, A, B, C, 15, Sn, 58); -+ ROUND4(C, D, A, B, 6, So, 59); ROUND4(B, C, D, A, 13, Sp, 60); -+ ROUND4(A, B, C, D, 4, Sm, 61); ROUND4(D, A, B, C, 11, Sn, 62); -+ ROUND4(C, D, A, B, 2, So, 63); ROUND4(B, C, D, A, 9, Sp, 64); -+ -+ ctxt->md5_sta += A; -+ ctxt->md5_stb += B; -+ ctxt->md5_stc += C; -+ ctxt->md5_std += D; -+} -diff -Nur linux-2.6.39.orig/crypto/ocf/safe/md5.h linux-2.6.39/crypto/ocf/safe/md5.h ---- linux-2.6.39.orig/crypto/ocf/safe/md5.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/safe/md5.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,76 @@ -+/* $FreeBSD: src/sys/crypto/md5.h,v 1.4 2002/03/20 05:13:50 alfred Exp $ */ -+/* $KAME: md5.h,v 1.4 2000/03/27 04:36:22 sumikawa Exp $ */ -+ -+/* -+ * Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. Neither the name of the project nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ */ -+ -+#ifndef _NETINET6_MD5_H_ -+#define _NETINET6_MD5_H_ -+ -+#define MD5_BUFLEN 64 -+ -+typedef struct { -+ union { -+ u_int32_t md5_state32[4]; -+ u_int8_t md5_state8[16]; -+ } md5_st; -+ -+#define md5_sta md5_st.md5_state32[0] -+#define md5_stb md5_st.md5_state32[1] -+#define md5_stc md5_st.md5_state32[2] -+#define md5_std md5_st.md5_state32[3] -+#define md5_st8 md5_st.md5_state8 -+ -+ union { -+ u_int64_t md5_count64; -+ u_int8_t md5_count8[8]; -+ } md5_count; -+#define md5_n md5_count.md5_count64 -+#define md5_n8 md5_count.md5_count8 -+ -+ u_int md5_i; -+ u_int8_t md5_buf[MD5_BUFLEN]; -+} md5_ctxt; -+ -+extern void md5_init(md5_ctxt *); -+extern void md5_loop(md5_ctxt *, u_int8_t *, u_int); -+extern void md5_pad(md5_ctxt *); -+extern void md5_result(u_int8_t *, md5_ctxt *); -+ -+/* compatibility */ -+#define MD5_CTX md5_ctxt -+#define MD5Init(x) md5_init((x)) -+#define MD5Update(x, y, z) md5_loop((x), (y), (z)) -+#define MD5Final(x, y) \ -+do { \ -+ md5_pad((y)); \ -+ md5_result((x), (y)); \ -+} while (0) -+ -+#endif /* ! _NETINET6_MD5_H_*/ -diff -Nur linux-2.6.39.orig/crypto/ocf/safe/safe.c linux-2.6.39/crypto/ocf/safe/safe.c ---- linux-2.6.39.orig/crypto/ocf/safe/safe.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/safe/safe.c 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,2288 @@ -+/*- -+ * Linux port done by David McCullough -+ * Copyright (C) 2004-2010 David McCullough -+ * The license and original author are listed below. -+ * -+ * Copyright (c) 2003 Sam Leffler, Errno Consulting -+ * Copyright (c) 2003 Global Technology Associates, Inc. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ * -+__FBSDID("$FreeBSD: src/sys/dev/safe/safe.c,v 1.18 2007/03/21 03:42:50 sam Exp $"); -+ */ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* -+ * SafeNet SafeXcel-1141 hardware crypto accelerator -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#if 1 -+#define DPRINTF(a) do { \ -+ if (debug) { \ -+ printk("%s: ", sc ? \ -+ device_get_nameunit(sc->sc_dev) : "safe"); \ -+ printk a; \ -+ } \ -+ } while (0) -+#else -+#define DPRINTF(a) -+#endif -+ -+/* -+ * until we find a cleaner way, include the BSD md5/sha1 code -+ * here -+ */ -+#define HMAC_HACK 1 -+#ifdef HMAC_HACK -+#define LITTLE_ENDIAN 1234 -+#define BIG_ENDIAN 4321 -+#ifdef __LITTLE_ENDIAN -+#define BYTE_ORDER LITTLE_ENDIAN -+#endif -+#ifdef __BIG_ENDIAN -+#define BYTE_ORDER BIG_ENDIAN -+#endif -+#include -+#include -+#include -+#include -+ -+u_int8_t hmac_ipad_buffer[64] = { -+ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, -+ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, -+ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, -+ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, -+ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, -+ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, -+ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, -+ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36 -+}; -+ -+u_int8_t hmac_opad_buffer[64] = { -+ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, -+ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, -+ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, -+ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, -+ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, -+ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, -+ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, -+ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C -+}; -+#endif /* HMAC_HACK */ -+ -+/* add proc entry for this */ -+struct safe_stats safestats; -+ -+#define debug safe_debug -+int safe_debug = 0; -+module_param(safe_debug, int, 0644); -+MODULE_PARM_DESC(safe_debug, "Enable debug"); -+ -+static void safe_callback(struct safe_softc *, struct safe_ringentry *); -+static void safe_feed(struct safe_softc *, struct safe_ringentry *); -+#if defined(CONFIG_OCF_RANDOMHARVEST) && !defined(SAFE_NO_RNG) -+static void safe_rng_init(struct safe_softc *); -+int safe_rngbufsize = 8; /* 32 bytes each read */ -+module_param(safe_rngbufsize, int, 0644); -+MODULE_PARM_DESC(safe_rngbufsize, "RNG polling buffer size (32-bit words)"); -+int safe_rngmaxalarm = 8; /* max alarms before reset */ -+module_param(safe_rngmaxalarm, int, 0644); -+MODULE_PARM_DESC(safe_rngmaxalarm, "RNG max alarms before reset"); -+#endif /* SAFE_NO_RNG */ -+ -+static void safe_totalreset(struct safe_softc *sc); -+static int safe_dmamap_aligned(struct safe_softc *sc, const struct safe_operand *op); -+static int safe_dmamap_uniform(struct safe_softc *sc, const struct safe_operand *op); -+static int safe_free_entry(struct safe_softc *sc, struct safe_ringentry *re); -+static int safe_kprocess(device_t dev, struct cryptkop *krp, int hint); -+static int safe_kstart(struct safe_softc *sc); -+static int safe_ksigbits(struct safe_softc *sc, struct crparam *cr); -+static void safe_kfeed(struct safe_softc *sc); -+static void safe_kpoll(unsigned long arg); -+static void safe_kload_reg(struct safe_softc *sc, u_int32_t off, -+ u_int32_t len, struct crparam *n); -+ -+static int safe_newsession(device_t, u_int32_t *, struct cryptoini *); -+static int safe_freesession(device_t, u_int64_t); -+static int safe_process(device_t, struct cryptop *, int); -+ -+static device_method_t safe_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, safe_newsession), -+ DEVMETHOD(cryptodev_freesession,safe_freesession), -+ DEVMETHOD(cryptodev_process, safe_process), -+ DEVMETHOD(cryptodev_kprocess, safe_kprocess), -+}; -+ -+#define READ_REG(sc,r) readl((sc)->sc_base_addr + (r)) -+#define WRITE_REG(sc,r,val) writel((val), (sc)->sc_base_addr + (r)) -+ -+#define SAFE_MAX_CHIPS 8 -+static struct safe_softc *safe_chip_idx[SAFE_MAX_CHIPS]; -+ -+/* -+ * split our buffers up into safe DMAable byte fragments to avoid lockup -+ * bug in 1141 HW on rev 1.0. -+ */ -+ -+static int -+pci_map_linear( -+ struct safe_softc *sc, -+ struct safe_operand *buf, -+ void *addr, -+ int len) -+{ -+ dma_addr_t tmp; -+ int chunk, tlen = len; -+ -+ tmp = pci_map_single(sc->sc_pcidev, addr, len, PCI_DMA_BIDIRECTIONAL); -+ -+ buf->mapsize += len; -+ while (len > 0) { -+ chunk = (len > sc->sc_max_dsize) ? sc->sc_max_dsize : len; -+ buf->segs[buf->nsegs].ds_addr = tmp; -+ buf->segs[buf->nsegs].ds_len = chunk; -+ buf->segs[buf->nsegs].ds_tlen = tlen; -+ buf->nsegs++; -+ tmp += chunk; -+ len -= chunk; -+ tlen = 0; -+ } -+ return 0; -+} -+ -+/* -+ * map in a given uio buffer (great on some arches :-) -+ */ -+ -+static int -+pci_map_uio(struct safe_softc *sc, struct safe_operand *buf, struct uio *uio) -+{ -+ struct iovec *iov = uio->uio_iov; -+ int n; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ buf->mapsize = 0; -+ buf->nsegs = 0; -+ -+ for (n = 0; n < uio->uio_iovcnt; n++) { -+ pci_map_linear(sc, buf, iov->iov_base, iov->iov_len); -+ iov++; -+ } -+ -+ /* identify this buffer by the first segment */ -+ buf->map = (void *) buf->segs[0].ds_addr; -+ return(0); -+} -+ -+/* -+ * map in a given sk_buff -+ */ -+ -+static int -+pci_map_skb(struct safe_softc *sc,struct safe_operand *buf,struct sk_buff *skb) -+{ -+ int i; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ buf->mapsize = 0; -+ buf->nsegs = 0; -+ -+ pci_map_linear(sc, buf, skb->data, skb_headlen(skb)); -+ -+ for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { -+ pci_map_linear(sc, buf, -+ page_address(skb_shinfo(skb)->frags[i].page) + -+ skb_shinfo(skb)->frags[i].page_offset, -+ skb_shinfo(skb)->frags[i].size); -+ } -+ -+ /* identify this buffer by the first segment */ -+ buf->map = (void *) buf->segs[0].ds_addr; -+ return(0); -+} -+ -+ -+#if 0 /* not needed at this time */ -+static void -+pci_sync_operand(struct safe_softc *sc, struct safe_operand *buf) -+{ -+ int i; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ for (i = 0; i < buf->nsegs; i++) -+ pci_dma_sync_single_for_cpu(sc->sc_pcidev, buf->segs[i].ds_addr, -+ buf->segs[i].ds_len, PCI_DMA_BIDIRECTIONAL); -+} -+#endif -+ -+static void -+pci_unmap_operand(struct safe_softc *sc, struct safe_operand *buf) -+{ -+ int i; -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ for (i = 0; i < buf->nsegs; i++) { -+ if (buf->segs[i].ds_tlen) { -+ DPRINTF(("%s - unmap %d 0x%x %d\n", __FUNCTION__, i, buf->segs[i].ds_addr, buf->segs[i].ds_tlen)); -+ pci_unmap_single(sc->sc_pcidev, buf->segs[i].ds_addr, -+ buf->segs[i].ds_tlen, PCI_DMA_BIDIRECTIONAL); -+ DPRINTF(("%s - unmap %d 0x%x %d done\n", __FUNCTION__, i, buf->segs[i].ds_addr, buf->segs[i].ds_tlen)); -+ } -+ buf->segs[i].ds_addr = 0; -+ buf->segs[i].ds_len = 0; -+ buf->segs[i].ds_tlen = 0; -+ } -+ buf->nsegs = 0; -+ buf->mapsize = 0; -+ buf->map = 0; -+} -+ -+ -+/* -+ * SafeXcel Interrupt routine -+ */ -+static irqreturn_t -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) -+safe_intr(int irq, void *arg) -+#else -+safe_intr(int irq, void *arg, struct pt_regs *regs) -+#endif -+{ -+ struct safe_softc *sc = arg; -+ int stat; -+ unsigned long flags; -+ -+ stat = READ_REG(sc, SAFE_HM_STAT); -+ -+ DPRINTF(("%s(stat=0x%x)\n", __FUNCTION__, stat)); -+ -+ if (stat == 0) /* shared irq, not for us */ -+ return IRQ_NONE; -+ -+ WRITE_REG(sc, SAFE_HI_CLR, stat); /* IACK */ -+ -+ if ((stat & SAFE_INT_PE_DDONE)) { -+ /* -+ * Descriptor(s) done; scan the ring and -+ * process completed operations. -+ */ -+ spin_lock_irqsave(&sc->sc_ringmtx, flags); -+ while (sc->sc_back != sc->sc_front) { -+ struct safe_ringentry *re = sc->sc_back; -+ -+#ifdef SAFE_DEBUG -+ if (debug) { -+ safe_dump_ringstate(sc, __func__); -+ safe_dump_request(sc, __func__, re); -+ } -+#endif -+ /* -+ * safe_process marks ring entries that were allocated -+ * but not used with a csr of zero. This insures the -+ * ring front pointer never needs to be set backwards -+ * in the event that an entry is allocated but not used -+ * because of a setup error. -+ */ -+ DPRINTF(("%s re->re_desc.d_csr=0x%x\n", __FUNCTION__, re->re_desc.d_csr)); -+ if (re->re_desc.d_csr != 0) { -+ if (!SAFE_PE_CSR_IS_DONE(re->re_desc.d_csr)) { -+ DPRINTF(("%s !CSR_IS_DONE\n", __FUNCTION__)); -+ break; -+ } -+ if (!SAFE_PE_LEN_IS_DONE(re->re_desc.d_len)) { -+ DPRINTF(("%s !LEN_IS_DONE\n", __FUNCTION__)); -+ break; -+ } -+ sc->sc_nqchip--; -+ safe_callback(sc, re); -+ } -+ if (++(sc->sc_back) == sc->sc_ringtop) -+ sc->sc_back = sc->sc_ring; -+ } -+ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); -+ } -+ -+ /* -+ * Check to see if we got any DMA Error -+ */ -+ if (stat & SAFE_INT_PE_ERROR) { -+ printk("%s: dmaerr dmastat %08x\n", device_get_nameunit(sc->sc_dev), -+ (int)READ_REG(sc, SAFE_PE_DMASTAT)); -+ safestats.st_dmaerr++; -+ safe_totalreset(sc); -+#if 0 -+ safe_feed(sc); -+#endif -+ } -+ -+ if (sc->sc_needwakeup) { /* XXX check high watermark */ -+ int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); -+ DPRINTF(("%s: wakeup crypto %x\n", __func__, -+ sc->sc_needwakeup)); -+ sc->sc_needwakeup &= ~wakeup; -+ crypto_unblock(sc->sc_cid, wakeup); -+ } -+ -+ return IRQ_HANDLED; -+} -+ -+/* -+ * safe_feed() - post a request to chip -+ */ -+static void -+safe_feed(struct safe_softc *sc, struct safe_ringentry *re) -+{ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+#ifdef SAFE_DEBUG -+ if (debug) { -+ safe_dump_ringstate(sc, __func__); -+ safe_dump_request(sc, __func__, re); -+ } -+#endif -+ sc->sc_nqchip++; -+ if (sc->sc_nqchip > safestats.st_maxqchip) -+ safestats.st_maxqchip = sc->sc_nqchip; -+ /* poke h/w to check descriptor ring, any value can be written */ -+ WRITE_REG(sc, SAFE_HI_RD_DESCR, 0); -+} -+ -+#define N(a) (sizeof(a) / sizeof (a[0])) -+static void -+safe_setup_enckey(struct safe_session *ses, caddr_t key) -+{ -+ int i; -+ -+ bcopy(key, ses->ses_key, ses->ses_klen / 8); -+ -+ /* PE is little-endian, insure proper byte order */ -+ for (i = 0; i < N(ses->ses_key); i++) -+ ses->ses_key[i] = htole32(ses->ses_key[i]); -+} -+ -+static void -+safe_setup_mackey(struct safe_session *ses, int algo, caddr_t key, int klen) -+{ -+#ifdef HMAC_HACK -+ MD5_CTX md5ctx; -+ SHA1_CTX sha1ctx; -+ int i; -+ -+ -+ for (i = 0; i < klen; i++) -+ key[i] ^= HMAC_IPAD_VAL; -+ -+ if (algo == CRYPTO_MD5_HMAC) { -+ MD5Init(&md5ctx); -+ MD5Update(&md5ctx, key, klen); -+ MD5Update(&md5ctx, hmac_ipad_buffer, MD5_HMAC_BLOCK_LEN - klen); -+ bcopy(md5ctx.md5_st8, ses->ses_hminner, sizeof(md5ctx.md5_st8)); -+ } else { -+ SHA1Init(&sha1ctx); -+ SHA1Update(&sha1ctx, key, klen); -+ SHA1Update(&sha1ctx, hmac_ipad_buffer, -+ SHA1_HMAC_BLOCK_LEN - klen); -+ bcopy(sha1ctx.h.b32, ses->ses_hminner, sizeof(sha1ctx.h.b32)); -+ } -+ -+ for (i = 0; i < klen; i++) -+ key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); -+ -+ if (algo == CRYPTO_MD5_HMAC) { -+ MD5Init(&md5ctx); -+ MD5Update(&md5ctx, key, klen); -+ MD5Update(&md5ctx, hmac_opad_buffer, MD5_HMAC_BLOCK_LEN - klen); -+ bcopy(md5ctx.md5_st8, ses->ses_hmouter, sizeof(md5ctx.md5_st8)); -+ } else { -+ SHA1Init(&sha1ctx); -+ SHA1Update(&sha1ctx, key, klen); -+ SHA1Update(&sha1ctx, hmac_opad_buffer, -+ SHA1_HMAC_BLOCK_LEN - klen); -+ bcopy(sha1ctx.h.b32, ses->ses_hmouter, sizeof(sha1ctx.h.b32)); -+ } -+ -+ for (i = 0; i < klen; i++) -+ key[i] ^= HMAC_OPAD_VAL; -+ -+#if 0 -+ /* -+ * this code prevents SHA working on a BE host, -+ * so it is obviously wrong. I think the byte -+ * swap setup we do with the chip fixes this for us -+ */ -+ -+ /* PE is little-endian, insure proper byte order */ -+ for (i = 0; i < N(ses->ses_hminner); i++) { -+ ses->ses_hminner[i] = htole32(ses->ses_hminner[i]); -+ ses->ses_hmouter[i] = htole32(ses->ses_hmouter[i]); -+ } -+#endif -+#else /* HMAC_HACK */ -+ printk("safe: md5/sha not implemented\n"); -+#endif /* HMAC_HACK */ -+} -+#undef N -+ -+/* -+ * Allocate a new 'session' and return an encoded session id. 'sidp' -+ * contains our registration id, and should contain an encoded session -+ * id on successful allocation. -+ */ -+static int -+safe_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) -+{ -+ struct safe_softc *sc = device_get_softc(dev); -+ struct cryptoini *c, *encini = NULL, *macini = NULL; -+ struct safe_session *ses = NULL; -+ int sesn; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (sidp == NULL || cri == NULL || sc == NULL) -+ return (EINVAL); -+ -+ for (c = cri; c != NULL; c = c->cri_next) { -+ if (c->cri_alg == CRYPTO_MD5_HMAC || -+ c->cri_alg == CRYPTO_SHA1_HMAC || -+ c->cri_alg == CRYPTO_NULL_HMAC) { -+ if (macini) -+ return (EINVAL); -+ macini = c; -+ } else if (c->cri_alg == CRYPTO_DES_CBC || -+ c->cri_alg == CRYPTO_3DES_CBC || -+ c->cri_alg == CRYPTO_AES_CBC || -+ c->cri_alg == CRYPTO_NULL_CBC) { -+ if (encini) -+ return (EINVAL); -+ encini = c; -+ } else -+ return (EINVAL); -+ } -+ if (encini == NULL && macini == NULL) -+ return (EINVAL); -+ if (encini) { /* validate key length */ -+ switch (encini->cri_alg) { -+ case CRYPTO_DES_CBC: -+ if (encini->cri_klen != 64) -+ return (EINVAL); -+ break; -+ case CRYPTO_3DES_CBC: -+ if (encini->cri_klen != 192) -+ return (EINVAL); -+ break; -+ case CRYPTO_AES_CBC: -+ if (encini->cri_klen != 128 && -+ encini->cri_klen != 192 && -+ encini->cri_klen != 256) -+ return (EINVAL); -+ break; -+ } -+ } -+ -+ if (sc->sc_sessions == NULL) { -+ ses = sc->sc_sessions = (struct safe_session *) -+ kmalloc(sizeof(struct safe_session), SLAB_ATOMIC); -+ if (ses == NULL) -+ return (ENOMEM); -+ memset(ses, 0, sizeof(struct safe_session)); -+ sesn = 0; -+ sc->sc_nsessions = 1; -+ } else { -+ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { -+ if (sc->sc_sessions[sesn].ses_used == 0) { -+ ses = &sc->sc_sessions[sesn]; -+ break; -+ } -+ } -+ -+ if (ses == NULL) { -+ sesn = sc->sc_nsessions; -+ ses = (struct safe_session *) -+ kmalloc((sesn + 1) * sizeof(struct safe_session), SLAB_ATOMIC); -+ if (ses == NULL) -+ return (ENOMEM); -+ memset(ses, 0, (sesn + 1) * sizeof(struct safe_session)); -+ bcopy(sc->sc_sessions, ses, sesn * -+ sizeof(struct safe_session)); -+ bzero(sc->sc_sessions, sesn * -+ sizeof(struct safe_session)); -+ kfree(sc->sc_sessions); -+ sc->sc_sessions = ses; -+ ses = &sc->sc_sessions[sesn]; -+ sc->sc_nsessions++; -+ } -+ } -+ -+ bzero(ses, sizeof(struct safe_session)); -+ ses->ses_used = 1; -+ -+ if (encini) { -+ /* get an IV */ -+ /* XXX may read fewer than requested */ -+ read_random(ses->ses_iv, sizeof(ses->ses_iv)); -+ -+ ses->ses_klen = encini->cri_klen; -+ if (encini->cri_key != NULL) -+ safe_setup_enckey(ses, encini->cri_key); -+ } -+ -+ if (macini) { -+ ses->ses_mlen = macini->cri_mlen; -+ if (ses->ses_mlen == 0) { -+ if (macini->cri_alg == CRYPTO_MD5_HMAC) -+ ses->ses_mlen = MD5_HASH_LEN; -+ else -+ ses->ses_mlen = SHA1_HASH_LEN; -+ } -+ -+ if (macini->cri_key != NULL) { -+ safe_setup_mackey(ses, macini->cri_alg, macini->cri_key, -+ macini->cri_klen / 8); -+ } -+ } -+ -+ *sidp = SAFE_SID(device_get_unit(sc->sc_dev), sesn); -+ return (0); -+} -+ -+/* -+ * Deallocate a session. -+ */ -+static int -+safe_freesession(device_t dev, u_int64_t tid) -+{ -+ struct safe_softc *sc = device_get_softc(dev); -+ int session, ret; -+ u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (sc == NULL) -+ return (EINVAL); -+ -+ session = SAFE_SESSION(sid); -+ if (session < sc->sc_nsessions) { -+ bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session])); -+ ret = 0; -+ } else -+ ret = EINVAL; -+ return (ret); -+} -+ -+ -+static int -+safe_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ struct safe_softc *sc = device_get_softc(dev); -+ int err = 0, i, nicealign, uniform; -+ struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; -+ int bypass, oplen, ivsize; -+ caddr_t iv; -+ int16_t coffset; -+ struct safe_session *ses; -+ struct safe_ringentry *re; -+ struct safe_sarec *sa; -+ struct safe_pdesc *pd; -+ u_int32_t cmd0, cmd1, staterec; -+ unsigned long flags; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { -+ safestats.st_invalid++; -+ return (EINVAL); -+ } -+ if (SAFE_SESSION(crp->crp_sid) >= sc->sc_nsessions) { -+ safestats.st_badsession++; -+ return (EINVAL); -+ } -+ -+ spin_lock_irqsave(&sc->sc_ringmtx, flags); -+ if (sc->sc_front == sc->sc_back && sc->sc_nqchip != 0) { -+ safestats.st_ringfull++; -+ sc->sc_needwakeup |= CRYPTO_SYMQ; -+ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); -+ return (ERESTART); -+ } -+ re = sc->sc_front; -+ -+ staterec = re->re_sa.sa_staterec; /* save */ -+ /* NB: zero everything but the PE descriptor */ -+ bzero(&re->re_sa, sizeof(struct safe_ringentry) - sizeof(re->re_desc)); -+ re->re_sa.sa_staterec = staterec; /* restore */ -+ -+ re->re_crp = crp; -+ re->re_sesn = SAFE_SESSION(crp->crp_sid); -+ -+ re->re_src.nsegs = 0; -+ re->re_dst.nsegs = 0; -+ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ re->re_src_skb = (struct sk_buff *)crp->crp_buf; -+ re->re_dst_skb = (struct sk_buff *)crp->crp_buf; -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ re->re_src_io = (struct uio *)crp->crp_buf; -+ re->re_dst_io = (struct uio *)crp->crp_buf; -+ } else { -+ safestats.st_badflags++; -+ err = EINVAL; -+ goto errout; /* XXX we don't handle contiguous blocks! */ -+ } -+ -+ sa = &re->re_sa; -+ ses = &sc->sc_sessions[re->re_sesn]; -+ -+ crd1 = crp->crp_desc; -+ if (crd1 == NULL) { -+ safestats.st_nodesc++; -+ err = EINVAL; -+ goto errout; -+ } -+ crd2 = crd1->crd_next; -+ -+ cmd0 = SAFE_SA_CMD0_BASIC; /* basic group operation */ -+ cmd1 = 0; -+ if (crd2 == NULL) { -+ if (crd1->crd_alg == CRYPTO_MD5_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1_HMAC || -+ crd1->crd_alg == CRYPTO_NULL_HMAC) { -+ maccrd = crd1; -+ enccrd = NULL; -+ cmd0 |= SAFE_SA_CMD0_OP_HASH; -+ } else if (crd1->crd_alg == CRYPTO_DES_CBC || -+ crd1->crd_alg == CRYPTO_3DES_CBC || -+ crd1->crd_alg == CRYPTO_AES_CBC || -+ crd1->crd_alg == CRYPTO_NULL_CBC) { -+ maccrd = NULL; -+ enccrd = crd1; -+ cmd0 |= SAFE_SA_CMD0_OP_CRYPT; -+ } else { -+ safestats.st_badalg++; -+ err = EINVAL; -+ goto errout; -+ } -+ } else { -+ if ((crd1->crd_alg == CRYPTO_MD5_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1_HMAC || -+ crd1->crd_alg == CRYPTO_NULL_HMAC) && -+ (crd2->crd_alg == CRYPTO_DES_CBC || -+ crd2->crd_alg == CRYPTO_3DES_CBC || -+ crd2->crd_alg == CRYPTO_AES_CBC || -+ crd2->crd_alg == CRYPTO_NULL_CBC) && -+ ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { -+ maccrd = crd1; -+ enccrd = crd2; -+ } else if ((crd1->crd_alg == CRYPTO_DES_CBC || -+ crd1->crd_alg == CRYPTO_3DES_CBC || -+ crd1->crd_alg == CRYPTO_AES_CBC || -+ crd1->crd_alg == CRYPTO_NULL_CBC) && -+ (crd2->crd_alg == CRYPTO_MD5_HMAC || -+ crd2->crd_alg == CRYPTO_SHA1_HMAC || -+ crd2->crd_alg == CRYPTO_NULL_HMAC) && -+ (crd1->crd_flags & CRD_F_ENCRYPT)) { -+ enccrd = crd1; -+ maccrd = crd2; -+ } else { -+ safestats.st_badalg++; -+ err = EINVAL; -+ goto errout; -+ } -+ cmd0 |= SAFE_SA_CMD0_OP_BOTH; -+ } -+ -+ if (enccrd) { -+ if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) -+ safe_setup_enckey(ses, enccrd->crd_key); -+ -+ if (enccrd->crd_alg == CRYPTO_DES_CBC) { -+ cmd0 |= SAFE_SA_CMD0_DES; -+ cmd1 |= SAFE_SA_CMD1_CBC; -+ ivsize = 2*sizeof(u_int32_t); -+ } else if (enccrd->crd_alg == CRYPTO_3DES_CBC) { -+ cmd0 |= SAFE_SA_CMD0_3DES; -+ cmd1 |= SAFE_SA_CMD1_CBC; -+ ivsize = 2*sizeof(u_int32_t); -+ } else if (enccrd->crd_alg == CRYPTO_AES_CBC) { -+ cmd0 |= SAFE_SA_CMD0_AES; -+ cmd1 |= SAFE_SA_CMD1_CBC; -+ if (ses->ses_klen == 128) -+ cmd1 |= SAFE_SA_CMD1_AES128; -+ else if (ses->ses_klen == 192) -+ cmd1 |= SAFE_SA_CMD1_AES192; -+ else -+ cmd1 |= SAFE_SA_CMD1_AES256; -+ ivsize = 4*sizeof(u_int32_t); -+ } else { -+ cmd0 |= SAFE_SA_CMD0_CRYPT_NULL; -+ ivsize = 0; -+ } -+ -+ /* -+ * Setup encrypt/decrypt state. When using basic ops -+ * we can't use an inline IV because hash/crypt offset -+ * must be from the end of the IV to the start of the -+ * crypt data and this leaves out the preceding header -+ * from the hash calculation. Instead we place the IV -+ * in the state record and set the hash/crypt offset to -+ * copy both the header+IV. -+ */ -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) { -+ cmd0 |= SAFE_SA_CMD0_OUTBOUND; -+ -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) -+ iv = enccrd->crd_iv; -+ else -+ iv = (caddr_t) ses->ses_iv; -+ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ enccrd->crd_inject, ivsize, iv); -+ } -+ bcopy(iv, re->re_sastate.sa_saved_iv, ivsize); -+ /* make iv LE */ -+ for (i = 0; i < ivsize/sizeof(re->re_sastate.sa_saved_iv[0]); i++) -+ re->re_sastate.sa_saved_iv[i] = -+ cpu_to_le32(re->re_sastate.sa_saved_iv[i]); -+ cmd0 |= SAFE_SA_CMD0_IVLD_STATE | SAFE_SA_CMD0_SAVEIV; -+ re->re_flags |= SAFE_QFLAGS_COPYOUTIV; -+ } else { -+ cmd0 |= SAFE_SA_CMD0_INBOUND; -+ -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) { -+ bcopy(enccrd->crd_iv, -+ re->re_sastate.sa_saved_iv, ivsize); -+ } else { -+ crypto_copydata(crp->crp_flags, crp->crp_buf, -+ enccrd->crd_inject, ivsize, -+ (caddr_t)re->re_sastate.sa_saved_iv); -+ } -+ /* make iv LE */ -+ for (i = 0; i < ivsize/sizeof(re->re_sastate.sa_saved_iv[0]); i++) -+ re->re_sastate.sa_saved_iv[i] = -+ cpu_to_le32(re->re_sastate.sa_saved_iv[i]); -+ cmd0 |= SAFE_SA_CMD0_IVLD_STATE; -+ } -+ /* -+ * For basic encryption use the zero pad algorithm. -+ * This pads results to an 8-byte boundary and -+ * suppresses padding verification for inbound (i.e. -+ * decrypt) operations. -+ * -+ * NB: Not sure if the 8-byte pad boundary is a problem. -+ */ -+ cmd0 |= SAFE_SA_CMD0_PAD_ZERO; -+ -+ /* XXX assert key bufs have the same size */ -+ bcopy(ses->ses_key, sa->sa_key, sizeof(sa->sa_key)); -+ } -+ -+ if (maccrd) { -+ if (maccrd->crd_flags & CRD_F_KEY_EXPLICIT) { -+ safe_setup_mackey(ses, maccrd->crd_alg, -+ maccrd->crd_key, maccrd->crd_klen / 8); -+ } -+ -+ if (maccrd->crd_alg == CRYPTO_MD5_HMAC) { -+ cmd0 |= SAFE_SA_CMD0_MD5; -+ cmd1 |= SAFE_SA_CMD1_HMAC; /* NB: enable HMAC */ -+ } else if (maccrd->crd_alg == CRYPTO_SHA1_HMAC) { -+ cmd0 |= SAFE_SA_CMD0_SHA1; -+ cmd1 |= SAFE_SA_CMD1_HMAC; /* NB: enable HMAC */ -+ } else { -+ cmd0 |= SAFE_SA_CMD0_HASH_NULL; -+ } -+ /* -+ * Digest data is loaded from the SA and the hash -+ * result is saved to the state block where we -+ * retrieve it for return to the caller. -+ */ -+ /* XXX assert digest bufs have the same size */ -+ bcopy(ses->ses_hminner, sa->sa_indigest, -+ sizeof(sa->sa_indigest)); -+ bcopy(ses->ses_hmouter, sa->sa_outdigest, -+ sizeof(sa->sa_outdigest)); -+ -+ cmd0 |= SAFE_SA_CMD0_HSLD_SA | SAFE_SA_CMD0_SAVEHASH; -+ re->re_flags |= SAFE_QFLAGS_COPYOUTICV; -+ } -+ -+ if (enccrd && maccrd) { -+ /* -+ * The offset from hash data to the start of -+ * crypt data is the difference in the skips. -+ */ -+ bypass = maccrd->crd_skip; -+ coffset = enccrd->crd_skip - maccrd->crd_skip; -+ if (coffset < 0) { -+ DPRINTF(("%s: hash does not precede crypt; " -+ "mac skip %u enc skip %u\n", -+ __func__, maccrd->crd_skip, enccrd->crd_skip)); -+ safestats.st_skipmismatch++; -+ err = EINVAL; -+ goto errout; -+ } -+ oplen = enccrd->crd_skip + enccrd->crd_len; -+ if (maccrd->crd_skip + maccrd->crd_len != oplen) { -+ DPRINTF(("%s: hash amount %u != crypt amount %u\n", -+ __func__, maccrd->crd_skip + maccrd->crd_len, -+ oplen)); -+ safestats.st_lenmismatch++; -+ err = EINVAL; -+ goto errout; -+ } -+#ifdef SAFE_DEBUG -+ if (debug) { -+ printf("mac: skip %d, len %d, inject %d\n", -+ maccrd->crd_skip, maccrd->crd_len, -+ maccrd->crd_inject); -+ printf("enc: skip %d, len %d, inject %d\n", -+ enccrd->crd_skip, enccrd->crd_len, -+ enccrd->crd_inject); -+ printf("bypass %d coffset %d oplen %d\n", -+ bypass, coffset, oplen); -+ } -+#endif -+ if (coffset & 3) { /* offset must be 32-bit aligned */ -+ DPRINTF(("%s: coffset %u misaligned\n", -+ __func__, coffset)); -+ safestats.st_coffmisaligned++; -+ err = EINVAL; -+ goto errout; -+ } -+ coffset >>= 2; -+ if (coffset > 255) { /* offset must be <256 dwords */ -+ DPRINTF(("%s: coffset %u too big\n", -+ __func__, coffset)); -+ safestats.st_cofftoobig++; -+ err = EINVAL; -+ goto errout; -+ } -+ /* -+ * Tell the hardware to copy the header to the output. -+ * The header is defined as the data from the end of -+ * the bypass to the start of data to be encrypted. -+ * Typically this is the inline IV. Note that you need -+ * to do this even if src+dst are the same; it appears -+ * that w/o this bit the crypted data is written -+ * immediately after the bypass data. -+ */ -+ cmd1 |= SAFE_SA_CMD1_HDRCOPY; -+ /* -+ * Disable IP header mutable bit handling. This is -+ * needed to get correct HMAC calculations. -+ */ -+ cmd1 |= SAFE_SA_CMD1_MUTABLE; -+ } else { -+ if (enccrd) { -+ bypass = enccrd->crd_skip; -+ oplen = bypass + enccrd->crd_len; -+ } else { -+ bypass = maccrd->crd_skip; -+ oplen = bypass + maccrd->crd_len; -+ } -+ coffset = 0; -+ } -+ /* XXX verify multiple of 4 when using s/g */ -+ if (bypass > 96) { /* bypass offset must be <= 96 bytes */ -+ DPRINTF(("%s: bypass %u too big\n", __func__, bypass)); -+ safestats.st_bypasstoobig++; -+ err = EINVAL; -+ goto errout; -+ } -+ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ if (pci_map_skb(sc, &re->re_src, re->re_src_skb)) { -+ safestats.st_noload++; -+ err = ENOMEM; -+ goto errout; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ if (pci_map_uio(sc, &re->re_src, re->re_src_io)) { -+ safestats.st_noload++; -+ err = ENOMEM; -+ goto errout; -+ } -+ } -+ nicealign = safe_dmamap_aligned(sc, &re->re_src); -+ uniform = safe_dmamap_uniform(sc, &re->re_src); -+ -+ DPRINTF(("src nicealign %u uniform %u nsegs %u\n", -+ nicealign, uniform, re->re_src.nsegs)); -+ if (re->re_src.nsegs > 1) { -+ re->re_desc.d_src = sc->sc_spalloc.dma_paddr + -+ ((caddr_t) sc->sc_spfree - (caddr_t) sc->sc_spring); -+ for (i = 0; i < re->re_src_nsegs; i++) { -+ /* NB: no need to check if there's space */ -+ pd = sc->sc_spfree; -+ if (++(sc->sc_spfree) == sc->sc_springtop) -+ sc->sc_spfree = sc->sc_spring; -+ -+ KASSERT((pd->pd_flags&3) == 0 || -+ (pd->pd_flags&3) == SAFE_PD_DONE, -+ ("bogus source particle descriptor; flags %x", -+ pd->pd_flags)); -+ pd->pd_addr = re->re_src_segs[i].ds_addr; -+ pd->pd_size = re->re_src_segs[i].ds_len; -+ pd->pd_flags = SAFE_PD_READY; -+ } -+ cmd0 |= SAFE_SA_CMD0_IGATHER; -+ } else { -+ /* -+ * No need for gather, reference the operand directly. -+ */ -+ re->re_desc.d_src = re->re_src_segs[0].ds_addr; -+ } -+ -+ if (enccrd == NULL && maccrd != NULL) { -+ /* -+ * Hash op; no destination needed. -+ */ -+ } else { -+ if (crp->crp_flags & (CRYPTO_F_IOV|CRYPTO_F_SKBUF)) { -+ if (!nicealign) { -+ safestats.st_iovmisaligned++; -+ err = EINVAL; -+ goto errout; -+ } -+ if (uniform != 1) { -+ device_printf(sc->sc_dev, "!uniform source\n"); -+ if (!uniform) { -+ /* -+ * There's no way to handle the DMA -+ * requirements with this uio. We -+ * could create a separate DMA area for -+ * the result and then copy it back, -+ * but for now we just bail and return -+ * an error. Note that uio requests -+ * > SAFE_MAX_DSIZE are handled because -+ * the DMA map and segment list for the -+ * destination wil result in a -+ * destination particle list that does -+ * the necessary scatter DMA. -+ */ -+ safestats.st_iovnotuniform++; -+ err = EINVAL; -+ goto errout; -+ } -+ } else -+ re->re_dst = re->re_src; -+ } else { -+ safestats.st_badflags++; -+ err = EINVAL; -+ goto errout; -+ } -+ -+ if (re->re_dst.nsegs > 1) { -+ re->re_desc.d_dst = sc->sc_dpalloc.dma_paddr + -+ ((caddr_t) sc->sc_dpfree - (caddr_t) sc->sc_dpring); -+ for (i = 0; i < re->re_dst_nsegs; i++) { -+ pd = sc->sc_dpfree; -+ KASSERT((pd->pd_flags&3) == 0 || -+ (pd->pd_flags&3) == SAFE_PD_DONE, -+ ("bogus dest particle descriptor; flags %x", -+ pd->pd_flags)); -+ if (++(sc->sc_dpfree) == sc->sc_dpringtop) -+ sc->sc_dpfree = sc->sc_dpring; -+ pd->pd_addr = re->re_dst_segs[i].ds_addr; -+ pd->pd_flags = SAFE_PD_READY; -+ } -+ cmd0 |= SAFE_SA_CMD0_OSCATTER; -+ } else { -+ /* -+ * No need for scatter, reference the operand directly. -+ */ -+ re->re_desc.d_dst = re->re_dst_segs[0].ds_addr; -+ } -+ } -+ -+ /* -+ * All done with setup; fillin the SA command words -+ * and the packet engine descriptor. The operation -+ * is now ready for submission to the hardware. -+ */ -+ sa->sa_cmd0 = cmd0 | SAFE_SA_CMD0_IPCI | SAFE_SA_CMD0_OPCI; -+ sa->sa_cmd1 = cmd1 -+ | (coffset << SAFE_SA_CMD1_OFFSET_S) -+ | SAFE_SA_CMD1_SAREV1 /* Rev 1 SA data structure */ -+ | SAFE_SA_CMD1_SRPCI -+ ; -+ /* -+ * NB: the order of writes is important here. In case the -+ * chip is scanning the ring because of an outstanding request -+ * it might nab this one too. In that case we need to make -+ * sure the setup is complete before we write the length -+ * field of the descriptor as it signals the descriptor is -+ * ready for processing. -+ */ -+ re->re_desc.d_csr = SAFE_PE_CSR_READY | SAFE_PE_CSR_SAPCI; -+ if (maccrd) -+ re->re_desc.d_csr |= SAFE_PE_CSR_LOADSA | SAFE_PE_CSR_HASHFINAL; -+ wmb(); -+ re->re_desc.d_len = oplen -+ | SAFE_PE_LEN_READY -+ | (bypass << SAFE_PE_LEN_BYPASS_S) -+ ; -+ -+ safestats.st_ipackets++; -+ safestats.st_ibytes += oplen; -+ -+ if (++(sc->sc_front) == sc->sc_ringtop) -+ sc->sc_front = sc->sc_ring; -+ -+ /* XXX honor batching */ -+ safe_feed(sc, re); -+ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); -+ return (0); -+ -+errout: -+ if (re->re_src.map != re->re_dst.map) -+ pci_unmap_operand(sc, &re->re_dst); -+ if (re->re_src.map) -+ pci_unmap_operand(sc, &re->re_src); -+ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); -+ if (err != ERESTART) { -+ crp->crp_etype = err; -+ crypto_done(crp); -+ } else { -+ sc->sc_needwakeup |= CRYPTO_SYMQ; -+ } -+ return (err); -+} -+ -+static void -+safe_callback(struct safe_softc *sc, struct safe_ringentry *re) -+{ -+ struct cryptop *crp = (struct cryptop *)re->re_crp; -+ struct cryptodesc *crd; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ safestats.st_opackets++; -+ safestats.st_obytes += re->re_dst.mapsize; -+ -+ if (re->re_desc.d_csr & SAFE_PE_CSR_STATUS) { -+ device_printf(sc->sc_dev, "csr 0x%x cmd0 0x%x cmd1 0x%x\n", -+ re->re_desc.d_csr, -+ re->re_sa.sa_cmd0, re->re_sa.sa_cmd1); -+ safestats.st_peoperr++; -+ crp->crp_etype = EIO; /* something more meaningful? */ -+ } -+ -+ if (re->re_dst.map != NULL && re->re_dst.map != re->re_src.map) -+ pci_unmap_operand(sc, &re->re_dst); -+ pci_unmap_operand(sc, &re->re_src); -+ -+ /* -+ * If result was written to a differet mbuf chain, swap -+ * it in as the return value and reclaim the original. -+ */ -+ if ((crp->crp_flags & CRYPTO_F_SKBUF) && re->re_src_skb != re->re_dst_skb) { -+ device_printf(sc->sc_dev, "no CRYPTO_F_SKBUF swapping support\n"); -+ /* kfree_skb(skb) */ -+ /* crp->crp_buf = (caddr_t)re->re_dst_skb */ -+ return; -+ } -+ -+ if (re->re_flags & SAFE_QFLAGS_COPYOUTIV) { -+ /* copy out IV for future use */ -+ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { -+ int i; -+ int ivsize; -+ -+ if (crd->crd_alg == CRYPTO_DES_CBC || -+ crd->crd_alg == CRYPTO_3DES_CBC) { -+ ivsize = 2*sizeof(u_int32_t); -+ } else if (crd->crd_alg == CRYPTO_AES_CBC) { -+ ivsize = 4*sizeof(u_int32_t); -+ } else -+ continue; -+ crypto_copydata(crp->crp_flags, crp->crp_buf, -+ crd->crd_skip + crd->crd_len - ivsize, ivsize, -+ (caddr_t)sc->sc_sessions[re->re_sesn].ses_iv); -+ for (i = 0; -+ i < ivsize/sizeof(sc->sc_sessions[re->re_sesn].ses_iv[0]); -+ i++) -+ sc->sc_sessions[re->re_sesn].ses_iv[i] = -+ cpu_to_le32(sc->sc_sessions[re->re_sesn].ses_iv[i]); -+ break; -+ } -+ } -+ -+ if (re->re_flags & SAFE_QFLAGS_COPYOUTICV) { -+ /* copy out ICV result */ -+ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { -+ if (!(crd->crd_alg == CRYPTO_MD5_HMAC || -+ crd->crd_alg == CRYPTO_SHA1_HMAC || -+ crd->crd_alg == CRYPTO_NULL_HMAC)) -+ continue; -+ if (crd->crd_alg == CRYPTO_SHA1_HMAC) { -+ /* -+ * SHA-1 ICV's are byte-swapped; fix 'em up -+ * before copy them to their destination. -+ */ -+ re->re_sastate.sa_saved_indigest[0] = -+ cpu_to_be32(re->re_sastate.sa_saved_indigest[0]); -+ re->re_sastate.sa_saved_indigest[1] = -+ cpu_to_be32(re->re_sastate.sa_saved_indigest[1]); -+ re->re_sastate.sa_saved_indigest[2] = -+ cpu_to_be32(re->re_sastate.sa_saved_indigest[2]); -+ } else { -+ re->re_sastate.sa_saved_indigest[0] = -+ cpu_to_le32(re->re_sastate.sa_saved_indigest[0]); -+ re->re_sastate.sa_saved_indigest[1] = -+ cpu_to_le32(re->re_sastate.sa_saved_indigest[1]); -+ re->re_sastate.sa_saved_indigest[2] = -+ cpu_to_le32(re->re_sastate.sa_saved_indigest[2]); -+ } -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, -+ sc->sc_sessions[re->re_sesn].ses_mlen, -+ (caddr_t)re->re_sastate.sa_saved_indigest); -+ break; -+ } -+ } -+ crypto_done(crp); -+} -+ -+ -+#if defined(CONFIG_OCF_RANDOMHARVEST) && !defined(SAFE_NO_RNG) -+#define SAFE_RNG_MAXWAIT 1000 -+ -+static void -+safe_rng_init(struct safe_softc *sc) -+{ -+ u_int32_t w, v; -+ int i; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ WRITE_REG(sc, SAFE_RNG_CTRL, 0); -+ /* use default value according to the manual */ -+ WRITE_REG(sc, SAFE_RNG_CNFG, 0x834); /* magic from SafeNet */ -+ WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); -+ -+ /* -+ * There is a bug in rev 1.0 of the 1140 that when the RNG -+ * is brought out of reset the ready status flag does not -+ * work until the RNG has finished its internal initialization. -+ * -+ * So in order to determine the device is through its -+ * initialization we must read the data register, using the -+ * status reg in the read in case it is initialized. Then read -+ * the data register until it changes from the first read. -+ * Once it changes read the data register until it changes -+ * again. At this time the RNG is considered initialized. -+ * This could take between 750ms - 1000ms in time. -+ */ -+ i = 0; -+ w = READ_REG(sc, SAFE_RNG_OUT); -+ do { -+ v = READ_REG(sc, SAFE_RNG_OUT); -+ if (v != w) { -+ w = v; -+ break; -+ } -+ DELAY(10); -+ } while (++i < SAFE_RNG_MAXWAIT); -+ -+ /* Wait Until data changes again */ -+ i = 0; -+ do { -+ v = READ_REG(sc, SAFE_RNG_OUT); -+ if (v != w) -+ break; -+ DELAY(10); -+ } while (++i < SAFE_RNG_MAXWAIT); -+} -+ -+static __inline void -+safe_rng_disable_short_cycle(struct safe_softc *sc) -+{ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ WRITE_REG(sc, SAFE_RNG_CTRL, -+ READ_REG(sc, SAFE_RNG_CTRL) &~ SAFE_RNG_CTRL_SHORTEN); -+} -+ -+static __inline void -+safe_rng_enable_short_cycle(struct safe_softc *sc) -+{ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ WRITE_REG(sc, SAFE_RNG_CTRL, -+ READ_REG(sc, SAFE_RNG_CTRL) | SAFE_RNG_CTRL_SHORTEN); -+} -+ -+static __inline u_int32_t -+safe_rng_read(struct safe_softc *sc) -+{ -+ int i; -+ -+ i = 0; -+ while (READ_REG(sc, SAFE_RNG_STAT) != 0 && ++i < SAFE_RNG_MAXWAIT) -+ ; -+ return READ_REG(sc, SAFE_RNG_OUT); -+} -+ -+static int -+safe_read_random(void *arg, u_int32_t *buf, int maxwords) -+{ -+ struct safe_softc *sc = (struct safe_softc *) arg; -+ int i, rc; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ safestats.st_rng++; -+ /* -+ * Fetch the next block of data. -+ */ -+ if (maxwords > safe_rngbufsize) -+ maxwords = safe_rngbufsize; -+ if (maxwords > SAFE_RNG_MAXBUFSIZ) -+ maxwords = SAFE_RNG_MAXBUFSIZ; -+retry: -+ /* read as much as we can */ -+ for (rc = 0; rc < maxwords; rc++) { -+ if (READ_REG(sc, SAFE_RNG_STAT) != 0) -+ break; -+ buf[rc] = READ_REG(sc, SAFE_RNG_OUT); -+ } -+ if (rc == 0) -+ return 0; -+ /* -+ * Check the comparator alarm count and reset the h/w if -+ * it exceeds our threshold. This guards against the -+ * hardware oscillators resonating with external signals. -+ */ -+ if (READ_REG(sc, SAFE_RNG_ALM_CNT) > safe_rngmaxalarm) { -+ u_int32_t freq_inc, w; -+ -+ DPRINTF(("%s: alarm count %u exceeds threshold %u\n", __func__, -+ (unsigned)READ_REG(sc, SAFE_RNG_ALM_CNT), safe_rngmaxalarm)); -+ safestats.st_rngalarm++; -+ safe_rng_enable_short_cycle(sc); -+ freq_inc = 18; -+ for (i = 0; i < 64; i++) { -+ w = READ_REG(sc, SAFE_RNG_CNFG); -+ freq_inc = ((w + freq_inc) & 0x3fL); -+ w = ((w & ~0x3fL) | freq_inc); -+ WRITE_REG(sc, SAFE_RNG_CNFG, w); -+ -+ WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); -+ -+ (void) safe_rng_read(sc); -+ DELAY(25); -+ -+ if (READ_REG(sc, SAFE_RNG_ALM_CNT) == 0) { -+ safe_rng_disable_short_cycle(sc); -+ goto retry; -+ } -+ freq_inc = 1; -+ } -+ safe_rng_disable_short_cycle(sc); -+ } else -+ WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); -+ -+ return(rc); -+} -+#endif /* defined(CONFIG_OCF_RANDOMHARVEST) && !defined(SAFE_NO_RNG) */ -+ -+ -+/* -+ * Resets the board. Values in the regesters are left as is -+ * from the reset (i.e. initial values are assigned elsewhere). -+ */ -+static void -+safe_reset_board(struct safe_softc *sc) -+{ -+ u_int32_t v; -+ /* -+ * Reset the device. The manual says no delay -+ * is needed between marking and clearing reset. -+ */ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ v = READ_REG(sc, SAFE_PE_DMACFG) &~ -+ (SAFE_PE_DMACFG_PERESET | SAFE_PE_DMACFG_PDRRESET | -+ SAFE_PE_DMACFG_SGRESET); -+ WRITE_REG(sc, SAFE_PE_DMACFG, v -+ | SAFE_PE_DMACFG_PERESET -+ | SAFE_PE_DMACFG_PDRRESET -+ | SAFE_PE_DMACFG_SGRESET); -+ WRITE_REG(sc, SAFE_PE_DMACFG, v); -+} -+ -+/* -+ * Initialize registers we need to touch only once. -+ */ -+static void -+safe_init_board(struct safe_softc *sc) -+{ -+ u_int32_t v, dwords; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ v = READ_REG(sc, SAFE_PE_DMACFG); -+ v &=~ ( SAFE_PE_DMACFG_PEMODE -+ | SAFE_PE_DMACFG_FSENA /* failsafe enable */ -+ | SAFE_PE_DMACFG_GPRPCI /* gather ring on PCI */ -+ | SAFE_PE_DMACFG_SPRPCI /* scatter ring on PCI */ -+ | SAFE_PE_DMACFG_ESDESC /* endian-swap descriptors */ -+ | SAFE_PE_DMACFG_ESPDESC /* endian-swap part. desc's */ -+ | SAFE_PE_DMACFG_ESSA /* endian-swap SA's */ -+ | SAFE_PE_DMACFG_ESPACKET /* swap the packet data */ -+ ); -+ v |= SAFE_PE_DMACFG_FSENA /* failsafe enable */ -+ | SAFE_PE_DMACFG_GPRPCI /* gather ring on PCI */ -+ | SAFE_PE_DMACFG_SPRPCI /* scatter ring on PCI */ -+ | SAFE_PE_DMACFG_ESDESC /* endian-swap descriptors */ -+ | SAFE_PE_DMACFG_ESPDESC /* endian-swap part. desc's */ -+ | SAFE_PE_DMACFG_ESSA /* endian-swap SA's */ -+#if 0 -+ | SAFE_PE_DMACFG_ESPACKET /* swap the packet data */ -+#endif -+ ; -+ WRITE_REG(sc, SAFE_PE_DMACFG, v); -+ -+#ifdef __BIG_ENDIAN -+ /* tell the safenet that we are 4321 and not 1234 */ -+ WRITE_REG(sc, SAFE_ENDIAN, 0xe4e41b1b); -+#endif -+ -+ if (sc->sc_chiprev == SAFE_REV(1,0)) { -+ /* -+ * Avoid large PCI DMA transfers. Rev 1.0 has a bug where -+ * "target mode transfers" done while the chip is DMA'ing -+ * >1020 bytes cause the hardware to lockup. To avoid this -+ * we reduce the max PCI transfer size and use small source -+ * particle descriptors (<= 256 bytes). -+ */ -+ WRITE_REG(sc, SAFE_DMA_CFG, 256); -+ device_printf(sc->sc_dev, -+ "Reduce max DMA size to %u words for rev %u.%u WAR\n", -+ (unsigned) ((READ_REG(sc, SAFE_DMA_CFG)>>2) & 0xff), -+ (unsigned) SAFE_REV_MAJ(sc->sc_chiprev), -+ (unsigned) SAFE_REV_MIN(sc->sc_chiprev)); -+ sc->sc_max_dsize = 256; -+ } else { -+ sc->sc_max_dsize = SAFE_MAX_DSIZE; -+ } -+ -+ /* NB: operands+results are overlaid */ -+ WRITE_REG(sc, SAFE_PE_PDRBASE, sc->sc_ringalloc.dma_paddr); -+ WRITE_REG(sc, SAFE_PE_RDRBASE, sc->sc_ringalloc.dma_paddr); -+ /* -+ * Configure ring entry size and number of items in the ring. -+ */ -+ KASSERT((sizeof(struct safe_ringentry) % sizeof(u_int32_t)) == 0, -+ ("PE ring entry not 32-bit aligned!")); -+ dwords = sizeof(struct safe_ringentry) / sizeof(u_int32_t); -+ WRITE_REG(sc, SAFE_PE_RINGCFG, -+ (dwords << SAFE_PE_RINGCFG_OFFSET_S) | SAFE_MAX_NQUEUE); -+ WRITE_REG(sc, SAFE_PE_RINGPOLL, 0); /* disable polling */ -+ -+ WRITE_REG(sc, SAFE_PE_GRNGBASE, sc->sc_spalloc.dma_paddr); -+ WRITE_REG(sc, SAFE_PE_SRNGBASE, sc->sc_dpalloc.dma_paddr); -+ WRITE_REG(sc, SAFE_PE_PARTSIZE, -+ (SAFE_TOTAL_DPART<<16) | SAFE_TOTAL_SPART); -+ /* -+ * NB: destination particles are fixed size. We use -+ * an mbuf cluster and require all results go to -+ * clusters or smaller. -+ */ -+ WRITE_REG(sc, SAFE_PE_PARTCFG, sc->sc_max_dsize); -+ -+ /* it's now safe to enable PE mode, do it */ -+ WRITE_REG(sc, SAFE_PE_DMACFG, v | SAFE_PE_DMACFG_PEMODE); -+ -+ /* -+ * Configure hardware to use level-triggered interrupts and -+ * to interrupt after each descriptor is processed. -+ */ -+ WRITE_REG(sc, SAFE_HI_CFG, SAFE_HI_CFG_LEVEL); -+ WRITE_REG(sc, SAFE_HI_CLR, 0xffffffff); -+ WRITE_REG(sc, SAFE_HI_DESC_CNT, 1); -+ WRITE_REG(sc, SAFE_HI_MASK, SAFE_INT_PE_DDONE | SAFE_INT_PE_ERROR); -+} -+ -+ -+/* -+ * Clean up after a chip crash. -+ * It is assumed that the caller in splimp() -+ */ -+static void -+safe_cleanchip(struct safe_softc *sc) -+{ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (sc->sc_nqchip != 0) { -+ struct safe_ringentry *re = sc->sc_back; -+ -+ while (re != sc->sc_front) { -+ if (re->re_desc.d_csr != 0) -+ safe_free_entry(sc, re); -+ if (++re == sc->sc_ringtop) -+ re = sc->sc_ring; -+ } -+ sc->sc_back = re; -+ sc->sc_nqchip = 0; -+ } -+} -+ -+/* -+ * free a safe_q -+ * It is assumed that the caller is within splimp(). -+ */ -+static int -+safe_free_entry(struct safe_softc *sc, struct safe_ringentry *re) -+{ -+ struct cryptop *crp; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ /* -+ * Free header MCR -+ */ -+ if ((re->re_dst_skb != NULL) && (re->re_src_skb != re->re_dst_skb)) -+#ifdef NOTYET -+ m_freem(re->re_dst_m); -+#else -+ printk("%s,%d: SKB not supported\n", __FILE__, __LINE__); -+#endif -+ -+ crp = (struct cryptop *)re->re_crp; -+ -+ re->re_desc.d_csr = 0; -+ -+ crp->crp_etype = EFAULT; -+ crypto_done(crp); -+ return(0); -+} -+ -+/* -+ * Routine to reset the chip and clean up. -+ * It is assumed that the caller is in splimp() -+ */ -+static void -+safe_totalreset(struct safe_softc *sc) -+{ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ safe_reset_board(sc); -+ safe_init_board(sc); -+ safe_cleanchip(sc); -+} -+ -+/* -+ * Is the operand suitable aligned for direct DMA. Each -+ * segment must be aligned on a 32-bit boundary and all -+ * but the last segment must be a multiple of 4 bytes. -+ */ -+static int -+safe_dmamap_aligned(struct safe_softc *sc, const struct safe_operand *op) -+{ -+ int i; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ for (i = 0; i < op->nsegs; i++) { -+ if (op->segs[i].ds_addr & 3) -+ return (0); -+ if (i != (op->nsegs - 1) && (op->segs[i].ds_len & 3)) -+ return (0); -+ } -+ return (1); -+} -+ -+/* -+ * Is the operand suitable for direct DMA as the destination -+ * of an operation. The hardware requires that each ``particle'' -+ * but the last in an operation result have the same size. We -+ * fix that size at SAFE_MAX_DSIZE bytes. This routine returns -+ * 0 if some segment is not a multiple of of this size, 1 if all -+ * segments are exactly this size, or 2 if segments are at worst -+ * a multple of this size. -+ */ -+static int -+safe_dmamap_uniform(struct safe_softc *sc, const struct safe_operand *op) -+{ -+ int result = 1; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (op->nsegs > 0) { -+ int i; -+ -+ for (i = 0; i < op->nsegs-1; i++) { -+ if (op->segs[i].ds_len % sc->sc_max_dsize) -+ return (0); -+ if (op->segs[i].ds_len != sc->sc_max_dsize) -+ result = 2; -+ } -+ } -+ return (result); -+} -+ -+static int -+safe_kprocess(device_t dev, struct cryptkop *krp, int hint) -+{ -+ struct safe_softc *sc = device_get_softc(dev); -+ struct safe_pkq *q; -+ unsigned long flags; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (sc == NULL) { -+ krp->krp_status = EINVAL; -+ goto err; -+ } -+ -+ if (krp->krp_op != CRK_MOD_EXP) { -+ krp->krp_status = EOPNOTSUPP; -+ goto err; -+ } -+ -+ q = (struct safe_pkq *) kmalloc(sizeof(*q), GFP_KERNEL); -+ if (q == NULL) { -+ krp->krp_status = ENOMEM; -+ goto err; -+ } -+ memset(q, 0, sizeof(*q)); -+ q->pkq_krp = krp; -+ INIT_LIST_HEAD(&q->pkq_list); -+ -+ spin_lock_irqsave(&sc->sc_pkmtx, flags); -+ list_add_tail(&q->pkq_list, &sc->sc_pkq); -+ safe_kfeed(sc); -+ spin_unlock_irqrestore(&sc->sc_pkmtx, flags); -+ return (0); -+ -+err: -+ crypto_kdone(krp); -+ return (0); -+} -+ -+#define SAFE_CRK_PARAM_BASE 0 -+#define SAFE_CRK_PARAM_EXP 1 -+#define SAFE_CRK_PARAM_MOD 2 -+ -+static int -+safe_kstart(struct safe_softc *sc) -+{ -+ struct cryptkop *krp = sc->sc_pkq_cur->pkq_krp; -+ int exp_bits, mod_bits, base_bits; -+ u_int32_t op, a_off, b_off, c_off, d_off; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (krp->krp_iparams < 3 || krp->krp_oparams != 1) { -+ krp->krp_status = EINVAL; -+ return (1); -+ } -+ -+ base_bits = safe_ksigbits(sc, &krp->krp_param[SAFE_CRK_PARAM_BASE]); -+ if (base_bits > 2048) -+ goto too_big; -+ if (base_bits <= 0) /* 5. base not zero */ -+ goto too_small; -+ -+ exp_bits = safe_ksigbits(sc, &krp->krp_param[SAFE_CRK_PARAM_EXP]); -+ if (exp_bits > 2048) -+ goto too_big; -+ if (exp_bits <= 0) /* 1. exponent word length > 0 */ -+ goto too_small; /* 4. exponent not zero */ -+ -+ mod_bits = safe_ksigbits(sc, &krp->krp_param[SAFE_CRK_PARAM_MOD]); -+ if (mod_bits > 2048) -+ goto too_big; -+ if (mod_bits <= 32) /* 2. modulus word length > 1 */ -+ goto too_small; /* 8. MSW of modulus != zero */ -+ if (mod_bits < exp_bits) /* 3 modulus len >= exponent len */ -+ goto too_small; -+ if ((krp->krp_param[SAFE_CRK_PARAM_MOD].crp_p[0] & 1) == 0) -+ goto bad_domain; /* 6. modulus is odd */ -+ if (mod_bits > krp->krp_param[krp->krp_iparams].crp_nbits) -+ goto too_small; /* make sure result will fit */ -+ -+ /* 7. modulus > base */ -+ if (mod_bits < base_bits) -+ goto too_small; -+ if (mod_bits == base_bits) { -+ u_int8_t *basep, *modp; -+ int i; -+ -+ basep = krp->krp_param[SAFE_CRK_PARAM_BASE].crp_p + -+ ((base_bits + 7) / 8) - 1; -+ modp = krp->krp_param[SAFE_CRK_PARAM_MOD].crp_p + -+ ((mod_bits + 7) / 8) - 1; -+ -+ for (i = 0; i < (mod_bits + 7) / 8; i++, basep--, modp--) { -+ if (*modp < *basep) -+ goto too_small; -+ if (*modp > *basep) -+ break; -+ } -+ } -+ -+ /* And on the 9th step, he rested. */ -+ -+ WRITE_REG(sc, SAFE_PK_A_LEN, (exp_bits + 31) / 32); -+ WRITE_REG(sc, SAFE_PK_B_LEN, (mod_bits + 31) / 32); -+ if (mod_bits > 1024) { -+ op = SAFE_PK_FUNC_EXP4; -+ a_off = 0x000; -+ b_off = 0x100; -+ c_off = 0x200; -+ d_off = 0x300; -+ } else { -+ op = SAFE_PK_FUNC_EXP16; -+ a_off = 0x000; -+ b_off = 0x080; -+ c_off = 0x100; -+ d_off = 0x180; -+ } -+ sc->sc_pk_reslen = b_off - a_off; -+ sc->sc_pk_resoff = d_off; -+ -+ /* A is exponent, B is modulus, C is base, D is result */ -+ safe_kload_reg(sc, a_off, b_off - a_off, -+ &krp->krp_param[SAFE_CRK_PARAM_EXP]); -+ WRITE_REG(sc, SAFE_PK_A_ADDR, a_off >> 2); -+ safe_kload_reg(sc, b_off, b_off - a_off, -+ &krp->krp_param[SAFE_CRK_PARAM_MOD]); -+ WRITE_REG(sc, SAFE_PK_B_ADDR, b_off >> 2); -+ safe_kload_reg(sc, c_off, b_off - a_off, -+ &krp->krp_param[SAFE_CRK_PARAM_BASE]); -+ WRITE_REG(sc, SAFE_PK_C_ADDR, c_off >> 2); -+ WRITE_REG(sc, SAFE_PK_D_ADDR, d_off >> 2); -+ -+ WRITE_REG(sc, SAFE_PK_FUNC, op | SAFE_PK_FUNC_RUN); -+ -+ return (0); -+ -+too_big: -+ krp->krp_status = E2BIG; -+ return (1); -+too_small: -+ krp->krp_status = ERANGE; -+ return (1); -+bad_domain: -+ krp->krp_status = EDOM; -+ return (1); -+} -+ -+static int -+safe_ksigbits(struct safe_softc *sc, struct crparam *cr) -+{ -+ u_int plen = (cr->crp_nbits + 7) / 8; -+ int i, sig = plen * 8; -+ u_int8_t c, *p = cr->crp_p; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ for (i = plen - 1; i >= 0; i--) { -+ c = p[i]; -+ if (c != 0) { -+ while ((c & 0x80) == 0) { -+ sig--; -+ c <<= 1; -+ } -+ break; -+ } -+ sig -= 8; -+ } -+ return (sig); -+} -+ -+static void -+safe_kfeed(struct safe_softc *sc) -+{ -+ struct safe_pkq *q, *tmp; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (list_empty(&sc->sc_pkq) && sc->sc_pkq_cur == NULL) -+ return; -+ if (sc->sc_pkq_cur != NULL) -+ return; -+ list_for_each_entry_safe(q, tmp, &sc->sc_pkq, pkq_list) { -+ sc->sc_pkq_cur = q; -+ list_del(&q->pkq_list); -+ if (safe_kstart(sc) != 0) { -+ crypto_kdone(q->pkq_krp); -+ kfree(q); -+ sc->sc_pkq_cur = NULL; -+ } else { -+ /* op started, start polling */ -+ mod_timer(&sc->sc_pkto, jiffies + 1); -+ break; -+ } -+ } -+} -+ -+static void -+safe_kpoll(unsigned long arg) -+{ -+ struct safe_softc *sc = NULL; -+ struct safe_pkq *q; -+ struct crparam *res; -+ int i; -+ u_int32_t buf[64]; -+ unsigned long flags; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (arg >= SAFE_MAX_CHIPS) -+ return; -+ sc = safe_chip_idx[arg]; -+ if (!sc) { -+ DPRINTF(("%s() - bad callback\n", __FUNCTION__)); -+ return; -+ } -+ -+ spin_lock_irqsave(&sc->sc_pkmtx, flags); -+ if (sc->sc_pkq_cur == NULL) -+ goto out; -+ if (READ_REG(sc, SAFE_PK_FUNC) & SAFE_PK_FUNC_RUN) { -+ /* still running, check back later */ -+ mod_timer(&sc->sc_pkto, jiffies + 1); -+ goto out; -+ } -+ -+ q = sc->sc_pkq_cur; -+ res = &q->pkq_krp->krp_param[q->pkq_krp->krp_iparams]; -+ bzero(buf, sizeof(buf)); -+ bzero(res->crp_p, (res->crp_nbits + 7) / 8); -+ for (i = 0; i < sc->sc_pk_reslen >> 2; i++) -+ buf[i] = le32_to_cpu(READ_REG(sc, SAFE_PK_RAM_START + -+ sc->sc_pk_resoff + (i << 2))); -+ bcopy(buf, res->crp_p, (res->crp_nbits + 7) / 8); -+ /* -+ * reduce the bits that need copying if possible -+ */ -+ res->crp_nbits = min(res->crp_nbits,sc->sc_pk_reslen * 8); -+ res->crp_nbits = safe_ksigbits(sc, res); -+ -+ for (i = SAFE_PK_RAM_START; i < SAFE_PK_RAM_END; i += 4) -+ WRITE_REG(sc, i, 0); -+ -+ crypto_kdone(q->pkq_krp); -+ kfree(q); -+ sc->sc_pkq_cur = NULL; -+ -+ safe_kfeed(sc); -+out: -+ spin_unlock_irqrestore(&sc->sc_pkmtx, flags); -+} -+ -+static void -+safe_kload_reg(struct safe_softc *sc, u_int32_t off, u_int32_t len, -+ struct crparam *n) -+{ -+ u_int32_t buf[64], i; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ bzero(buf, sizeof(buf)); -+ bcopy(n->crp_p, buf, (n->crp_nbits + 7) / 8); -+ -+ for (i = 0; i < len >> 2; i++) -+ WRITE_REG(sc, SAFE_PK_RAM_START + off + (i << 2), -+ cpu_to_le32(buf[i])); -+} -+ -+#ifdef SAFE_DEBUG -+static void -+safe_dump_dmastatus(struct safe_softc *sc, const char *tag) -+{ -+ printf("%s: ENDIAN 0x%x SRC 0x%x DST 0x%x STAT 0x%x\n" -+ , tag -+ , READ_REG(sc, SAFE_DMA_ENDIAN) -+ , READ_REG(sc, SAFE_DMA_SRCADDR) -+ , READ_REG(sc, SAFE_DMA_DSTADDR) -+ , READ_REG(sc, SAFE_DMA_STAT) -+ ); -+} -+ -+static void -+safe_dump_intrstate(struct safe_softc *sc, const char *tag) -+{ -+ printf("%s: HI_CFG 0x%x HI_MASK 0x%x HI_DESC_CNT 0x%x HU_STAT 0x%x HM_STAT 0x%x\n" -+ , tag -+ , READ_REG(sc, SAFE_HI_CFG) -+ , READ_REG(sc, SAFE_HI_MASK) -+ , READ_REG(sc, SAFE_HI_DESC_CNT) -+ , READ_REG(sc, SAFE_HU_STAT) -+ , READ_REG(sc, SAFE_HM_STAT) -+ ); -+} -+ -+static void -+safe_dump_ringstate(struct safe_softc *sc, const char *tag) -+{ -+ u_int32_t estat = READ_REG(sc, SAFE_PE_ERNGSTAT); -+ -+ /* NB: assume caller has lock on ring */ -+ printf("%s: ERNGSTAT %x (next %u) back %lu front %lu\n", -+ tag, -+ estat, (estat >> SAFE_PE_ERNGSTAT_NEXT_S), -+ (unsigned long)(sc->sc_back - sc->sc_ring), -+ (unsigned long)(sc->sc_front - sc->sc_ring)); -+} -+ -+static void -+safe_dump_request(struct safe_softc *sc, const char* tag, struct safe_ringentry *re) -+{ -+ int ix, nsegs; -+ -+ ix = re - sc->sc_ring; -+ printf("%s: %p (%u): csr %x src %x dst %x sa %x len %x\n" -+ , tag -+ , re, ix -+ , re->re_desc.d_csr -+ , re->re_desc.d_src -+ , re->re_desc.d_dst -+ , re->re_desc.d_sa -+ , re->re_desc.d_len -+ ); -+ if (re->re_src.nsegs > 1) { -+ ix = (re->re_desc.d_src - sc->sc_spalloc.dma_paddr) / -+ sizeof(struct safe_pdesc); -+ for (nsegs = re->re_src.nsegs; nsegs; nsegs--) { -+ printf(" spd[%u] %p: %p size %u flags %x" -+ , ix, &sc->sc_spring[ix] -+ , (caddr_t)(uintptr_t) sc->sc_spring[ix].pd_addr -+ , sc->sc_spring[ix].pd_size -+ , sc->sc_spring[ix].pd_flags -+ ); -+ if (sc->sc_spring[ix].pd_size == 0) -+ printf(" (zero!)"); -+ printf("\n"); -+ if (++ix == SAFE_TOTAL_SPART) -+ ix = 0; -+ } -+ } -+ if (re->re_dst.nsegs > 1) { -+ ix = (re->re_desc.d_dst - sc->sc_dpalloc.dma_paddr) / -+ sizeof(struct safe_pdesc); -+ for (nsegs = re->re_dst.nsegs; nsegs; nsegs--) { -+ printf(" dpd[%u] %p: %p flags %x\n" -+ , ix, &sc->sc_dpring[ix] -+ , (caddr_t)(uintptr_t) sc->sc_dpring[ix].pd_addr -+ , sc->sc_dpring[ix].pd_flags -+ ); -+ if (++ix == SAFE_TOTAL_DPART) -+ ix = 0; -+ } -+ } -+ printf("sa: cmd0 %08x cmd1 %08x staterec %x\n", -+ re->re_sa.sa_cmd0, re->re_sa.sa_cmd1, re->re_sa.sa_staterec); -+ printf("sa: key %x %x %x %x %x %x %x %x\n" -+ , re->re_sa.sa_key[0] -+ , re->re_sa.sa_key[1] -+ , re->re_sa.sa_key[2] -+ , re->re_sa.sa_key[3] -+ , re->re_sa.sa_key[4] -+ , re->re_sa.sa_key[5] -+ , re->re_sa.sa_key[6] -+ , re->re_sa.sa_key[7] -+ ); -+ printf("sa: indigest %x %x %x %x %x\n" -+ , re->re_sa.sa_indigest[0] -+ , re->re_sa.sa_indigest[1] -+ , re->re_sa.sa_indigest[2] -+ , re->re_sa.sa_indigest[3] -+ , re->re_sa.sa_indigest[4] -+ ); -+ printf("sa: outdigest %x %x %x %x %x\n" -+ , re->re_sa.sa_outdigest[0] -+ , re->re_sa.sa_outdigest[1] -+ , re->re_sa.sa_outdigest[2] -+ , re->re_sa.sa_outdigest[3] -+ , re->re_sa.sa_outdigest[4] -+ ); -+ printf("sr: iv %x %x %x %x\n" -+ , re->re_sastate.sa_saved_iv[0] -+ , re->re_sastate.sa_saved_iv[1] -+ , re->re_sastate.sa_saved_iv[2] -+ , re->re_sastate.sa_saved_iv[3] -+ ); -+ printf("sr: hashbc %u indigest %x %x %x %x %x\n" -+ , re->re_sastate.sa_saved_hashbc -+ , re->re_sastate.sa_saved_indigest[0] -+ , re->re_sastate.sa_saved_indigest[1] -+ , re->re_sastate.sa_saved_indigest[2] -+ , re->re_sastate.sa_saved_indigest[3] -+ , re->re_sastate.sa_saved_indigest[4] -+ ); -+} -+ -+static void -+safe_dump_ring(struct safe_softc *sc, const char *tag) -+{ -+ unsigned long flags; -+ -+ spin_lock_irqsave(&sc->sc_ringmtx, flags); -+ printf("\nSafeNet Ring State:\n"); -+ safe_dump_intrstate(sc, tag); -+ safe_dump_dmastatus(sc, tag); -+ safe_dump_ringstate(sc, tag); -+ if (sc->sc_nqchip) { -+ struct safe_ringentry *re = sc->sc_back; -+ do { -+ safe_dump_request(sc, tag, re); -+ if (++re == sc->sc_ringtop) -+ re = sc->sc_ring; -+ } while (re != sc->sc_front); -+ } -+ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); -+} -+#endif /* SAFE_DEBUG */ -+ -+ -+static int safe_probe(struct pci_dev *dev, const struct pci_device_id *ent) -+{ -+ struct safe_softc *sc = NULL; -+ u32 mem_start, mem_len, cmd; -+ int i, rc, devinfo; -+ dma_addr_t raddr; -+ static int num_chips = 0; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (pci_enable_device(dev) < 0) -+ return(-ENODEV); -+ -+ if (!dev->irq) { -+ printk("safe: found device with no IRQ assigned. check BIOS settings!"); -+ pci_disable_device(dev); -+ return(-ENODEV); -+ } -+ -+ if (pci_set_mwi(dev)) { -+ printk("safe: pci_set_mwi failed!"); -+ return(-ENODEV); -+ } -+ -+ sc = (struct safe_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); -+ if (!sc) -+ return(-ENOMEM); -+ memset(sc, 0, sizeof(*sc)); -+ -+ softc_device_init(sc, "safe", num_chips, safe_methods); -+ -+ sc->sc_irq = -1; -+ sc->sc_cid = -1; -+ sc->sc_pcidev = dev; -+ if (num_chips < SAFE_MAX_CHIPS) { -+ safe_chip_idx[device_get_unit(sc->sc_dev)] = sc; -+ num_chips++; -+ } -+ -+ INIT_LIST_HEAD(&sc->sc_pkq); -+ spin_lock_init(&sc->sc_pkmtx); -+ -+ pci_set_drvdata(sc->sc_pcidev, sc); -+ -+ /* we read its hardware registers as memory */ -+ mem_start = pci_resource_start(sc->sc_pcidev, 0); -+ mem_len = pci_resource_len(sc->sc_pcidev, 0); -+ -+ sc->sc_base_addr = (ocf_iomem_t) ioremap(mem_start, mem_len); -+ if (!sc->sc_base_addr) { -+ device_printf(sc->sc_dev, "failed to ioremap 0x%x-0x%x\n", -+ mem_start, mem_start + mem_len - 1); -+ goto out; -+ } -+ -+ /* fix up the bus size */ -+ if (pci_set_dma_mask(sc->sc_pcidev, DMA_32BIT_MASK)) { -+ device_printf(sc->sc_dev, "No usable DMA configuration, aborting.\n"); -+ goto out; -+ } -+ if (pci_set_consistent_dma_mask(sc->sc_pcidev, DMA_32BIT_MASK)) { -+ device_printf(sc->sc_dev, "No usable consistent DMA configuration, aborting.\n"); -+ goto out; -+ } -+ -+ pci_set_master(sc->sc_pcidev); -+ -+ pci_read_config_dword(sc->sc_pcidev, PCI_COMMAND, &cmd); -+ -+ if (!(cmd & PCI_COMMAND_MEMORY)) { -+ device_printf(sc->sc_dev, "failed to enable memory mapping\n"); -+ goto out; -+ } -+ -+ if (!(cmd & PCI_COMMAND_MASTER)) { -+ device_printf(sc->sc_dev, "failed to enable bus mastering\n"); -+ goto out; -+ } -+ -+ rc = request_irq(dev->irq, safe_intr, IRQF_SHARED, "safe", sc); -+ if (rc) { -+ device_printf(sc->sc_dev, "failed to hook irq %d\n", sc->sc_irq); -+ goto out; -+ } -+ sc->sc_irq = dev->irq; -+ -+ sc->sc_chiprev = READ_REG(sc, SAFE_DEVINFO) & -+ (SAFE_DEVINFO_REV_MAJ | SAFE_DEVINFO_REV_MIN); -+ -+ /* -+ * Allocate packet engine descriptors. -+ */ -+ sc->sc_ringalloc.dma_vaddr = pci_alloc_consistent(sc->sc_pcidev, -+ SAFE_MAX_NQUEUE * sizeof (struct safe_ringentry), -+ &sc->sc_ringalloc.dma_paddr); -+ if (!sc->sc_ringalloc.dma_vaddr) { -+ device_printf(sc->sc_dev, "cannot allocate PE descriptor ring\n"); -+ goto out; -+ } -+ -+ /* -+ * Hookup the static portion of all our data structures. -+ */ -+ sc->sc_ring = (struct safe_ringentry *) sc->sc_ringalloc.dma_vaddr; -+ sc->sc_ringtop = sc->sc_ring + SAFE_MAX_NQUEUE; -+ sc->sc_front = sc->sc_ring; -+ sc->sc_back = sc->sc_ring; -+ raddr = sc->sc_ringalloc.dma_paddr; -+ bzero(sc->sc_ring, SAFE_MAX_NQUEUE * sizeof(struct safe_ringentry)); -+ for (i = 0; i < SAFE_MAX_NQUEUE; i++) { -+ struct safe_ringentry *re = &sc->sc_ring[i]; -+ -+ re->re_desc.d_sa = raddr + -+ offsetof(struct safe_ringentry, re_sa); -+ re->re_sa.sa_staterec = raddr + -+ offsetof(struct safe_ringentry, re_sastate); -+ -+ raddr += sizeof (struct safe_ringentry); -+ } -+ spin_lock_init(&sc->sc_ringmtx); -+ -+ /* -+ * Allocate scatter and gather particle descriptors. -+ */ -+ sc->sc_spalloc.dma_vaddr = pci_alloc_consistent(sc->sc_pcidev, -+ SAFE_TOTAL_SPART * sizeof (struct safe_pdesc), -+ &sc->sc_spalloc.dma_paddr); -+ if (!sc->sc_spalloc.dma_vaddr) { -+ device_printf(sc->sc_dev, "cannot allocate source particle descriptor ring\n"); -+ goto out; -+ } -+ sc->sc_spring = (struct safe_pdesc *) sc->sc_spalloc.dma_vaddr; -+ sc->sc_springtop = sc->sc_spring + SAFE_TOTAL_SPART; -+ sc->sc_spfree = sc->sc_spring; -+ bzero(sc->sc_spring, SAFE_TOTAL_SPART * sizeof(struct safe_pdesc)); -+ -+ sc->sc_dpalloc.dma_vaddr = pci_alloc_consistent(sc->sc_pcidev, -+ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), -+ &sc->sc_dpalloc.dma_paddr); -+ if (!sc->sc_dpalloc.dma_vaddr) { -+ device_printf(sc->sc_dev, "cannot allocate destination particle descriptor ring\n"); -+ goto out; -+ } -+ sc->sc_dpring = (struct safe_pdesc *) sc->sc_dpalloc.dma_vaddr; -+ sc->sc_dpringtop = sc->sc_dpring + SAFE_TOTAL_DPART; -+ sc->sc_dpfree = sc->sc_dpring; -+ bzero(sc->sc_dpring, SAFE_TOTAL_DPART * sizeof(struct safe_pdesc)); -+ -+ sc->sc_cid = crypto_get_driverid(softc_get_device(sc), CRYPTOCAP_F_HARDWARE); -+ if (sc->sc_cid < 0) { -+ device_printf(sc->sc_dev, "could not get crypto driver id\n"); -+ goto out; -+ } -+ -+ printf("%s:", device_get_nameunit(sc->sc_dev)); -+ -+ devinfo = READ_REG(sc, SAFE_DEVINFO); -+ if (devinfo & SAFE_DEVINFO_RNG) { -+ sc->sc_flags |= SAFE_FLAGS_RNG; -+ printf(" rng"); -+ } -+ if (devinfo & SAFE_DEVINFO_PKEY) { -+ printf(" key"); -+ sc->sc_flags |= SAFE_FLAGS_KEY; -+ crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0); -+#if 0 -+ crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0); -+#endif -+ init_timer(&sc->sc_pkto); -+ sc->sc_pkto.function = safe_kpoll; -+ sc->sc_pkto.data = (unsigned long) device_get_unit(sc->sc_dev); -+ } -+ if (devinfo & SAFE_DEVINFO_DES) { -+ printf(" des/3des"); -+ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); -+ } -+ if (devinfo & SAFE_DEVINFO_AES) { -+ printf(" aes"); -+ crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); -+ } -+ if (devinfo & SAFE_DEVINFO_MD5) { -+ printf(" md5"); -+ crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); -+ } -+ if (devinfo & SAFE_DEVINFO_SHA1) { -+ printf(" sha1"); -+ crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); -+ } -+ printf(" null"); -+ crypto_register(sc->sc_cid, CRYPTO_NULL_CBC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_NULL_HMAC, 0, 0); -+ /* XXX other supported algorithms */ -+ printf("\n"); -+ -+ safe_reset_board(sc); /* reset h/w */ -+ safe_init_board(sc); /* init h/w */ -+ -+#if defined(CONFIG_OCF_RANDOMHARVEST) && !defined(SAFE_NO_RNG) -+ if (sc->sc_flags & SAFE_FLAGS_RNG) { -+ safe_rng_init(sc); -+ crypto_rregister(sc->sc_cid, safe_read_random, sc); -+ } -+#endif /* SAFE_NO_RNG */ -+ -+ return (0); -+ -+out: -+ if (sc->sc_cid >= 0) -+ crypto_unregister_all(sc->sc_cid); -+ if (sc->sc_irq != -1) -+ free_irq(sc->sc_irq, sc); -+ if (sc->sc_ringalloc.dma_vaddr) -+ pci_free_consistent(sc->sc_pcidev, -+ SAFE_MAX_NQUEUE * sizeof (struct safe_ringentry), -+ sc->sc_ringalloc.dma_vaddr, sc->sc_ringalloc.dma_paddr); -+ if (sc->sc_spalloc.dma_vaddr) -+ pci_free_consistent(sc->sc_pcidev, -+ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), -+ sc->sc_spalloc.dma_vaddr, sc->sc_spalloc.dma_paddr); -+ if (sc->sc_dpalloc.dma_vaddr) -+ pci_free_consistent(sc->sc_pcidev, -+ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), -+ sc->sc_dpalloc.dma_vaddr, sc->sc_dpalloc.dma_paddr); -+ kfree(sc); -+ return(-ENODEV); -+} -+ -+static void safe_remove(struct pci_dev *dev) -+{ -+ struct safe_softc *sc = pci_get_drvdata(dev); -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ /* XXX wait/abort active ops */ -+ -+ WRITE_REG(sc, SAFE_HI_MASK, 0); /* disable interrupts */ -+ -+ del_timer_sync(&sc->sc_pkto); -+ -+ crypto_unregister_all(sc->sc_cid); -+ -+ safe_cleanchip(sc); -+ -+ if (sc->sc_irq != -1) -+ free_irq(sc->sc_irq, sc); -+ if (sc->sc_ringalloc.dma_vaddr) -+ pci_free_consistent(sc->sc_pcidev, -+ SAFE_MAX_NQUEUE * sizeof (struct safe_ringentry), -+ sc->sc_ringalloc.dma_vaddr, sc->sc_ringalloc.dma_paddr); -+ if (sc->sc_spalloc.dma_vaddr) -+ pci_free_consistent(sc->sc_pcidev, -+ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), -+ sc->sc_spalloc.dma_vaddr, sc->sc_spalloc.dma_paddr); -+ if (sc->sc_dpalloc.dma_vaddr) -+ pci_free_consistent(sc->sc_pcidev, -+ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), -+ sc->sc_dpalloc.dma_vaddr, sc->sc_dpalloc.dma_paddr); -+ sc->sc_irq = -1; -+ sc->sc_ringalloc.dma_vaddr = NULL; -+ sc->sc_spalloc.dma_vaddr = NULL; -+ sc->sc_dpalloc.dma_vaddr = NULL; -+} -+ -+static struct pci_device_id safe_pci_tbl[] = { -+ { PCI_VENDOR_SAFENET, PCI_PRODUCT_SAFEXCEL, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ { }, -+}; -+MODULE_DEVICE_TABLE(pci, safe_pci_tbl); -+ -+static struct pci_driver safe_driver = { -+ .name = "safe", -+ .id_table = safe_pci_tbl, -+ .probe = safe_probe, -+ .remove = safe_remove, -+ /* add PM stuff here one day */ -+}; -+ -+static int __init safe_init (void) -+{ -+ struct safe_softc *sc = NULL; -+ int rc; -+ -+ DPRINTF(("%s(%p)\n", __FUNCTION__, safe_init)); -+ -+ rc = pci_register_driver(&safe_driver); -+ pci_register_driver_compat(&safe_driver, rc); -+ -+ return rc; -+} -+ -+static void __exit safe_exit (void) -+{ -+ pci_unregister_driver(&safe_driver); -+} -+ -+module_init(safe_init); -+module_exit(safe_exit); -+ -+MODULE_LICENSE("BSD"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("OCF driver for safenet PCI crypto devices"); -diff -Nur linux-2.6.39.orig/crypto/ocf/safe/safereg.h linux-2.6.39/crypto/ocf/safe/safereg.h ---- linux-2.6.39.orig/crypto/ocf/safe/safereg.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/safe/safereg.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,421 @@ -+/*- -+ * Copyright (c) 2003 Sam Leffler, Errno Consulting -+ * Copyright (c) 2003 Global Technology Associates, Inc. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ * -+ * $FreeBSD: src/sys/dev/safe/safereg.h,v 1.1 2003/07/21 21:46:07 sam Exp $ -+ */ -+#ifndef _SAFE_SAFEREG_H_ -+#define _SAFE_SAFEREG_H_ -+ -+/* -+ * Register definitions for SafeNet SafeXcel-1141 crypto device. -+ * Definitions from revision 1.3 (Nov 6 2002) of the User's Manual. -+ */ -+ -+#define BS_BAR 0x10 /* DMA base address register */ -+#define BS_TRDY_TIMEOUT 0x40 /* TRDY timeout */ -+#define BS_RETRY_TIMEOUT 0x41 /* DMA retry timeout */ -+ -+#define PCI_VENDOR_SAFENET 0x16ae /* SafeNet, Inc. */ -+ -+/* SafeNet */ -+#define PCI_PRODUCT_SAFEXCEL 0x1141 /* 1141 */ -+ -+#define SAFE_PE_CSR 0x0000 /* Packet Enginge Ctrl/Status */ -+#define SAFE_PE_SRC 0x0004 /* Packet Engine Source */ -+#define SAFE_PE_DST 0x0008 /* Packet Engine Destination */ -+#define SAFE_PE_SA 0x000c /* Packet Engine SA */ -+#define SAFE_PE_LEN 0x0010 /* Packet Engine Length */ -+#define SAFE_PE_DMACFG 0x0040 /* Packet Engine DMA Configuration */ -+#define SAFE_PE_DMASTAT 0x0044 /* Packet Engine DMA Status */ -+#define SAFE_PE_PDRBASE 0x0048 /* Packet Engine Descriptor Ring Base */ -+#define SAFE_PE_RDRBASE 0x004c /* Packet Engine Result Ring Base */ -+#define SAFE_PE_RINGCFG 0x0050 /* Packet Engine Ring Configuration */ -+#define SAFE_PE_RINGPOLL 0x0054 /* Packet Engine Ring Poll */ -+#define SAFE_PE_IRNGSTAT 0x0058 /* Packet Engine Internal Ring Status */ -+#define SAFE_PE_ERNGSTAT 0x005c /* Packet Engine External Ring Status */ -+#define SAFE_PE_IOTHRESH 0x0060 /* Packet Engine I/O Threshold */ -+#define SAFE_PE_GRNGBASE 0x0064 /* Packet Engine Gather Ring Base */ -+#define SAFE_PE_SRNGBASE 0x0068 /* Packet Engine Scatter Ring Base */ -+#define SAFE_PE_PARTSIZE 0x006c /* Packet Engine Particlar Ring Size */ -+#define SAFE_PE_PARTCFG 0x0070 /* Packet Engine Particle Ring Config */ -+#define SAFE_CRYPTO_CTRL 0x0080 /* Crypto Control */ -+#define SAFE_DEVID 0x0084 /* Device ID */ -+#define SAFE_DEVINFO 0x0088 /* Device Info */ -+#define SAFE_HU_STAT 0x00a0 /* Host Unmasked Status */ -+#define SAFE_HM_STAT 0x00a4 /* Host Masked Status (read-only) */ -+#define SAFE_HI_CLR 0x00a4 /* Host Clear Interrupt (write-only) */ -+#define SAFE_HI_MASK 0x00a8 /* Host Mask Control */ -+#define SAFE_HI_CFG 0x00ac /* Interrupt Configuration */ -+#define SAFE_HI_RD_DESCR 0x00b4 /* Force Descriptor Read */ -+#define SAFE_HI_DESC_CNT 0x00b8 /* Host Descriptor Done Count */ -+#define SAFE_DMA_ENDIAN 0x00c0 /* Master Endian Status */ -+#define SAFE_DMA_SRCADDR 0x00c4 /* DMA Source Address Status */ -+#define SAFE_DMA_DSTADDR 0x00c8 /* DMA Destination Address Status */ -+#define SAFE_DMA_STAT 0x00cc /* DMA Current Status */ -+#define SAFE_DMA_CFG 0x00d4 /* DMA Configuration/Status */ -+#define SAFE_ENDIAN 0x00e0 /* Endian Configuration */ -+#define SAFE_PK_A_ADDR 0x0800 /* Public Key A Address */ -+#define SAFE_PK_B_ADDR 0x0804 /* Public Key B Address */ -+#define SAFE_PK_C_ADDR 0x0808 /* Public Key C Address */ -+#define SAFE_PK_D_ADDR 0x080c /* Public Key D Address */ -+#define SAFE_PK_A_LEN 0x0810 /* Public Key A Length */ -+#define SAFE_PK_B_LEN 0x0814 /* Public Key B Length */ -+#define SAFE_PK_SHIFT 0x0818 /* Public Key Shift */ -+#define SAFE_PK_FUNC 0x081c /* Public Key Function */ -+#define SAFE_PK_RAM_START 0x1000 /* Public Key RAM start address */ -+#define SAFE_PK_RAM_END 0x1fff /* Public Key RAM end address */ -+ -+#define SAFE_RNG_OUT 0x0100 /* RNG Output */ -+#define SAFE_RNG_STAT 0x0104 /* RNG Status */ -+#define SAFE_RNG_CTRL 0x0108 /* RNG Control */ -+#define SAFE_RNG_A 0x010c /* RNG A */ -+#define SAFE_RNG_B 0x0110 /* RNG B */ -+#define SAFE_RNG_X_LO 0x0114 /* RNG X [31:0] */ -+#define SAFE_RNG_X_MID 0x0118 /* RNG X [63:32] */ -+#define SAFE_RNG_X_HI 0x011c /* RNG X [80:64] */ -+#define SAFE_RNG_X_CNTR 0x0120 /* RNG Counter */ -+#define SAFE_RNG_ALM_CNT 0x0124 /* RNG Alarm Count */ -+#define SAFE_RNG_CNFG 0x0128 /* RNG Configuration */ -+#define SAFE_RNG_LFSR1_LO 0x012c /* RNG LFSR1 [31:0] */ -+#define SAFE_RNG_LFSR1_HI 0x0130 /* RNG LFSR1 [47:32] */ -+#define SAFE_RNG_LFSR2_LO 0x0134 /* RNG LFSR1 [31:0] */ -+#define SAFE_RNG_LFSR2_HI 0x0138 /* RNG LFSR1 [47:32] */ -+ -+#define SAFE_PE_CSR_READY 0x00000001 /* ready for processing */ -+#define SAFE_PE_CSR_DONE 0x00000002 /* h/w completed processing */ -+#define SAFE_PE_CSR_LOADSA 0x00000004 /* load SA digests */ -+#define SAFE_PE_CSR_HASHFINAL 0x00000010 /* do hash pad & write result */ -+#define SAFE_PE_CSR_SABUSID 0x000000c0 /* bus id for SA */ -+#define SAFE_PE_CSR_SAPCI 0x00000040 /* PCI bus id for SA */ -+#define SAFE_PE_CSR_NXTHDR 0x0000ff00 /* next hdr value for IPsec */ -+#define SAFE_PE_CSR_FPAD 0x0000ff00 /* fixed pad for basic ops */ -+#define SAFE_PE_CSR_STATUS 0x00ff0000 /* operation result status */ -+#define SAFE_PE_CSR_AUTH_FAIL 0x00010000 /* ICV mismatch (inbound) */ -+#define SAFE_PE_CSR_PAD_FAIL 0x00020000 /* pad verify fail (inbound) */ -+#define SAFE_PE_CSR_SEQ_FAIL 0x00040000 /* sequence number (inbound) */ -+#define SAFE_PE_CSR_XERROR 0x00080000 /* extended error follows */ -+#define SAFE_PE_CSR_XECODE 0x00f00000 /* extended error code */ -+#define SAFE_PE_CSR_XECODE_S 20 -+#define SAFE_PE_CSR_XECODE_BADCMD 0 /* invalid command */ -+#define SAFE_PE_CSR_XECODE_BADALG 1 /* invalid algorithm */ -+#define SAFE_PE_CSR_XECODE_ALGDIS 2 /* algorithm disabled */ -+#define SAFE_PE_CSR_XECODE_ZEROLEN 3 /* zero packet length */ -+#define SAFE_PE_CSR_XECODE_DMAERR 4 /* bus DMA error */ -+#define SAFE_PE_CSR_XECODE_PIPEABORT 5 /* secondary bus DMA error */ -+#define SAFE_PE_CSR_XECODE_BADSPI 6 /* IPsec SPI mismatch */ -+#define SAFE_PE_CSR_XECODE_TIMEOUT 10 /* failsafe timeout */ -+#define SAFE_PE_CSR_PAD 0xff000000 /* ESP padding control/status */ -+#define SAFE_PE_CSR_PAD_MIN 0x00000000 /* minimum IPsec padding */ -+#define SAFE_PE_CSR_PAD_16 0x08000000 /* pad to 16-byte boundary */ -+#define SAFE_PE_CSR_PAD_32 0x10000000 /* pad to 32-byte boundary */ -+#define SAFE_PE_CSR_PAD_64 0x20000000 /* pad to 64-byte boundary */ -+#define SAFE_PE_CSR_PAD_128 0x40000000 /* pad to 128-byte boundary */ -+#define SAFE_PE_CSR_PAD_256 0x80000000 /* pad to 256-byte boundary */ -+ -+/* -+ * Check the CSR to see if the PE has returned ownership to -+ * the host. Note that before processing a descriptor this -+ * must be done followed by a check of the SAFE_PE_LEN register -+ * status bits to avoid premature processing of a descriptor -+ * on its way back to the host. -+ */ -+#define SAFE_PE_CSR_IS_DONE(_csr) \ -+ (((_csr) & (SAFE_PE_CSR_READY | SAFE_PE_CSR_DONE)) == SAFE_PE_CSR_DONE) -+ -+#define SAFE_PE_LEN_LENGTH 0x000fffff /* total length (bytes) */ -+#define SAFE_PE_LEN_READY 0x00400000 /* ready for processing */ -+#define SAFE_PE_LEN_DONE 0x00800000 /* h/w completed processing */ -+#define SAFE_PE_LEN_BYPASS 0xff000000 /* bypass offset (bytes) */ -+#define SAFE_PE_LEN_BYPASS_S 24 -+ -+#define SAFE_PE_LEN_IS_DONE(_len) \ -+ (((_len) & (SAFE_PE_LEN_READY | SAFE_PE_LEN_DONE)) == SAFE_PE_LEN_DONE) -+ -+/* NB: these apply to HU_STAT, HM_STAT, HI_CLR, and HI_MASK */ -+#define SAFE_INT_PE_CDONE 0x00000002 /* PE context done */ -+#define SAFE_INT_PE_DDONE 0x00000008 /* PE descriptor done */ -+#define SAFE_INT_PE_ERROR 0x00000010 /* PE error */ -+#define SAFE_INT_PE_ODONE 0x00000020 /* PE operation done */ -+ -+#define SAFE_HI_CFG_PULSE 0x00000001 /* use pulse interrupt */ -+#define SAFE_HI_CFG_LEVEL 0x00000000 /* use level interrupt */ -+#define SAFE_HI_CFG_AUTOCLR 0x00000002 /* auto-clear pulse interrupt */ -+ -+#define SAFE_ENDIAN_PASS 0x000000e4 /* straight pass-thru */ -+#define SAFE_ENDIAN_SWAB 0x0000001b /* swap bytes in 32-bit word */ -+ -+#define SAFE_PE_DMACFG_PERESET 0x00000001 /* reset packet engine */ -+#define SAFE_PE_DMACFG_PDRRESET 0x00000002 /* reset PDR counters/ptrs */ -+#define SAFE_PE_DMACFG_SGRESET 0x00000004 /* reset scatter/gather cache */ -+#define SAFE_PE_DMACFG_FSENA 0x00000008 /* enable failsafe reset */ -+#define SAFE_PE_DMACFG_PEMODE 0x00000100 /* packet engine mode */ -+#define SAFE_PE_DMACFG_SAPREC 0x00000200 /* SA precedes packet */ -+#define SAFE_PE_DMACFG_PKFOLL 0x00000400 /* packet follows descriptor */ -+#define SAFE_PE_DMACFG_GPRBID 0x00003000 /* gather particle ring busid */ -+#define SAFE_PE_DMACFG_GPRPCI 0x00001000 /* PCI gather particle ring */ -+#define SAFE_PE_DMACFG_SPRBID 0x0000c000 /* scatter part. ring busid */ -+#define SAFE_PE_DMACFG_SPRPCI 0x00004000 /* PCI scatter part. ring */ -+#define SAFE_PE_DMACFG_ESDESC 0x00010000 /* endian swap descriptors */ -+#define SAFE_PE_DMACFG_ESSA 0x00020000 /* endian swap SA data */ -+#define SAFE_PE_DMACFG_ESPACKET 0x00040000 /* endian swap packet data */ -+#define SAFE_PE_DMACFG_ESPDESC 0x00080000 /* endian swap particle desc. */ -+#define SAFE_PE_DMACFG_NOPDRUP 0x00100000 /* supp. PDR ownership update */ -+#define SAFE_PD_EDMACFG_PCIMODE 0x01000000 /* PCI target mode */ -+ -+#define SAFE_PE_DMASTAT_PEIDONE 0x00000001 /* PE core input done */ -+#define SAFE_PE_DMASTAT_PEODONE 0x00000002 /* PE core output done */ -+#define SAFE_PE_DMASTAT_ENCDONE 0x00000004 /* encryption done */ -+#define SAFE_PE_DMASTAT_IHDONE 0x00000008 /* inner hash done */ -+#define SAFE_PE_DMASTAT_OHDONE 0x00000010 /* outer hash (HMAC) done */ -+#define SAFE_PE_DMASTAT_PADFLT 0x00000020 /* crypto pad fault */ -+#define SAFE_PE_DMASTAT_ICVFLT 0x00000040 /* ICV fault */ -+#define SAFE_PE_DMASTAT_SPIMIS 0x00000080 /* SPI mismatch */ -+#define SAFE_PE_DMASTAT_CRYPTO 0x00000100 /* crypto engine timeout */ -+#define SAFE_PE_DMASTAT_CQACT 0x00000200 /* command queue active */ -+#define SAFE_PE_DMASTAT_IRACT 0x00000400 /* input request active */ -+#define SAFE_PE_DMASTAT_ORACT 0x00000800 /* output request active */ -+#define SAFE_PE_DMASTAT_PEISIZE 0x003ff000 /* PE input size:32-bit words */ -+#define SAFE_PE_DMASTAT_PEOSIZE 0xffc00000 /* PE out. size:32-bit words */ -+ -+#define SAFE_PE_RINGCFG_SIZE 0x000003ff /* ring size (descriptors) */ -+#define SAFE_PE_RINGCFG_OFFSET 0xffff0000 /* offset btw desc's (dwords) */ -+#define SAFE_PE_RINGCFG_OFFSET_S 16 -+ -+#define SAFE_PE_RINGPOLL_POLL 0x00000fff /* polling frequency/divisor */ -+#define SAFE_PE_RINGPOLL_RETRY 0x03ff0000 /* polling frequency/divisor */ -+#define SAFE_PE_RINGPOLL_CONT 0x80000000 /* continuously poll */ -+ -+#define SAFE_PE_IRNGSTAT_CQAVAIL 0x00000001 /* command queue available */ -+ -+#define SAFE_PE_ERNGSTAT_NEXT 0x03ff0000 /* index of next packet desc. */ -+#define SAFE_PE_ERNGSTAT_NEXT_S 16 -+ -+#define SAFE_PE_IOTHRESH_INPUT 0x000003ff /* input threshold (dwords) */ -+#define SAFE_PE_IOTHRESH_OUTPUT 0x03ff0000 /* output threshold (dwords) */ -+ -+#define SAFE_PE_PARTCFG_SIZE 0x0000ffff /* scatter particle size */ -+#define SAFE_PE_PARTCFG_GBURST 0x00030000 /* gather particle burst */ -+#define SAFE_PE_PARTCFG_GBURST_2 0x00000000 -+#define SAFE_PE_PARTCFG_GBURST_4 0x00010000 -+#define SAFE_PE_PARTCFG_GBURST_8 0x00020000 -+#define SAFE_PE_PARTCFG_GBURST_16 0x00030000 -+#define SAFE_PE_PARTCFG_SBURST 0x000c0000 /* scatter particle burst */ -+#define SAFE_PE_PARTCFG_SBURST_2 0x00000000 -+#define SAFE_PE_PARTCFG_SBURST_4 0x00040000 -+#define SAFE_PE_PARTCFG_SBURST_8 0x00080000 -+#define SAFE_PE_PARTCFG_SBURST_16 0x000c0000 -+ -+#define SAFE_PE_PARTSIZE_SCAT 0xffff0000 /* scatter particle ring size */ -+#define SAFE_PE_PARTSIZE_GATH 0x0000ffff /* gather particle ring size */ -+ -+#define SAFE_CRYPTO_CTRL_3DES 0x00000001 /* enable 3DES support */ -+#define SAFE_CRYPTO_CTRL_PKEY 0x00010000 /* enable public key support */ -+#define SAFE_CRYPTO_CTRL_RNG 0x00020000 /* enable RNG support */ -+ -+#define SAFE_DEVINFO_REV_MIN 0x0000000f /* minor rev for chip */ -+#define SAFE_DEVINFO_REV_MAJ 0x000000f0 /* major rev for chip */ -+#define SAFE_DEVINFO_REV_MAJ_S 4 -+#define SAFE_DEVINFO_DES 0x00000100 /* DES/3DES support present */ -+#define SAFE_DEVINFO_ARC4 0x00000200 /* ARC4 support present */ -+#define SAFE_DEVINFO_AES 0x00000400 /* AES support present */ -+#define SAFE_DEVINFO_MD5 0x00001000 /* MD5 support present */ -+#define SAFE_DEVINFO_SHA1 0x00002000 /* SHA-1 support present */ -+#define SAFE_DEVINFO_RIPEMD 0x00004000 /* RIPEMD support present */ -+#define SAFE_DEVINFO_DEFLATE 0x00010000 /* Deflate support present */ -+#define SAFE_DEVINFO_SARAM 0x00100000 /* on-chip SA RAM present */ -+#define SAFE_DEVINFO_EMIBUS 0x00200000 /* EMI bus present */ -+#define SAFE_DEVINFO_PKEY 0x00400000 /* public key support present */ -+#define SAFE_DEVINFO_RNG 0x00800000 /* RNG present */ -+ -+#define SAFE_REV(_maj, _min) (((_maj) << SAFE_DEVINFO_REV_MAJ_S) | (_min)) -+#define SAFE_REV_MAJ(_chiprev) \ -+ (((_chiprev) & SAFE_DEVINFO_REV_MAJ) >> SAFE_DEVINFO_REV_MAJ_S) -+#define SAFE_REV_MIN(_chiprev) ((_chiprev) & SAFE_DEVINFO_REV_MIN) -+ -+#define SAFE_PK_FUNC_MULT 0x00000001 /* Multiply function */ -+#define SAFE_PK_FUNC_SQUARE 0x00000004 /* Square function */ -+#define SAFE_PK_FUNC_ADD 0x00000010 /* Add function */ -+#define SAFE_PK_FUNC_SUB 0x00000020 /* Subtract function */ -+#define SAFE_PK_FUNC_LSHIFT 0x00000040 /* Left-shift function */ -+#define SAFE_PK_FUNC_RSHIFT 0x00000080 /* Right-shift function */ -+#define SAFE_PK_FUNC_DIV 0x00000100 /* Divide function */ -+#define SAFE_PK_FUNC_CMP 0x00000400 /* Compare function */ -+#define SAFE_PK_FUNC_COPY 0x00000800 /* Copy function */ -+#define SAFE_PK_FUNC_EXP16 0x00002000 /* Exponentiate (4-bit ACT) */ -+#define SAFE_PK_FUNC_EXP4 0x00004000 /* Exponentiate (2-bit ACT) */ -+#define SAFE_PK_FUNC_RUN 0x00008000 /* start/status */ -+ -+#define SAFE_RNG_STAT_BUSY 0x00000001 /* busy, data not valid */ -+ -+#define SAFE_RNG_CTRL_PRE_LFSR 0x00000001 /* enable output pre-LFSR */ -+#define SAFE_RNG_CTRL_TST_MODE 0x00000002 /* enable test mode */ -+#define SAFE_RNG_CTRL_TST_RUN 0x00000004 /* start test state machine */ -+#define SAFE_RNG_CTRL_ENA_RING1 0x00000008 /* test entropy oscillator #1 */ -+#define SAFE_RNG_CTRL_ENA_RING2 0x00000010 /* test entropy oscillator #2 */ -+#define SAFE_RNG_CTRL_DIS_ALARM 0x00000020 /* disable RNG alarm reports */ -+#define SAFE_RNG_CTRL_TST_CLOCK 0x00000040 /* enable test clock */ -+#define SAFE_RNG_CTRL_SHORTEN 0x00000080 /* shorten state timers */ -+#define SAFE_RNG_CTRL_TST_ALARM 0x00000100 /* simulate alarm state */ -+#define SAFE_RNG_CTRL_RST_LFSR 0x00000200 /* reset LFSR */ -+ -+/* -+ * Packet engine descriptor. Note that d_csr is a copy of the -+ * SAFE_PE_CSR register and all definitions apply, and d_len -+ * is a copy of the SAFE_PE_LEN register and all definitions apply. -+ * d_src and d_len may point directly to contiguous data or to a -+ * list of ``particle descriptors'' when using scatter/gather i/o. -+ */ -+struct safe_desc { -+ u_int32_t d_csr; /* per-packet control/status */ -+ u_int32_t d_src; /* source address */ -+ u_int32_t d_dst; /* destination address */ -+ u_int32_t d_sa; /* SA address */ -+ u_int32_t d_len; /* length, bypass, status */ -+}; -+ -+/* -+ * Scatter/Gather particle descriptor. -+ * -+ * NB: scatter descriptors do not specify a size; this is fixed -+ * by the setting of the SAFE_PE_PARTCFG register. -+ */ -+struct safe_pdesc { -+ u_int32_t pd_addr; /* particle address */ -+#ifdef __BIG_ENDIAN -+ u_int16_t pd_flags; /* control word */ -+ u_int16_t pd_size; /* particle size (bytes) */ -+#else -+ u_int16_t pd_flags; /* control word */ -+ u_int16_t pd_size; /* particle size (bytes) */ -+#endif -+}; -+ -+#define SAFE_PD_READY 0x0001 /* ready for processing */ -+#define SAFE_PD_DONE 0x0002 /* h/w completed processing */ -+ -+/* -+ * Security Association (SA) Record (Rev 1). One of these is -+ * required for each operation processed by the packet engine. -+ */ -+struct safe_sarec { -+ u_int32_t sa_cmd0; -+ u_int32_t sa_cmd1; -+ u_int32_t sa_resv0; -+ u_int32_t sa_resv1; -+ u_int32_t sa_key[8]; /* DES/3DES/AES key */ -+ u_int32_t sa_indigest[5]; /* inner digest */ -+ u_int32_t sa_outdigest[5]; /* outer digest */ -+ u_int32_t sa_spi; /* SPI */ -+ u_int32_t sa_seqnum; /* sequence number */ -+ u_int32_t sa_seqmask[2]; /* sequence number mask */ -+ u_int32_t sa_resv2; -+ u_int32_t sa_staterec; /* address of state record */ -+ u_int32_t sa_resv3[2]; -+ u_int32_t sa_samgmt0; /* SA management field 0 */ -+ u_int32_t sa_samgmt1; /* SA management field 0 */ -+}; -+ -+#define SAFE_SA_CMD0_OP 0x00000007 /* operation code */ -+#define SAFE_SA_CMD0_OP_CRYPT 0x00000000 /* encrypt/decrypt (basic) */ -+#define SAFE_SA_CMD0_OP_BOTH 0x00000001 /* encrypt-hash/hash-decrypto */ -+#define SAFE_SA_CMD0_OP_HASH 0x00000003 /* hash (outbound-only) */ -+#define SAFE_SA_CMD0_OP_ESP 0x00000000 /* ESP in/out (proto) */ -+#define SAFE_SA_CMD0_OP_AH 0x00000001 /* AH in/out (proto) */ -+#define SAFE_SA_CMD0_INBOUND 0x00000008 /* inbound operation */ -+#define SAFE_SA_CMD0_OUTBOUND 0x00000000 /* outbound operation */ -+#define SAFE_SA_CMD0_GROUP 0x00000030 /* operation group */ -+#define SAFE_SA_CMD0_BASIC 0x00000000 /* basic operation */ -+#define SAFE_SA_CMD0_PROTO 0x00000010 /* protocol/packet operation */ -+#define SAFE_SA_CMD0_BUNDLE 0x00000020 /* bundled operation (resvd) */ -+#define SAFE_SA_CMD0_PAD 0x000000c0 /* crypto pad method */ -+#define SAFE_SA_CMD0_PAD_IPSEC 0x00000000 /* IPsec padding */ -+#define SAFE_SA_CMD0_PAD_PKCS7 0x00000040 /* PKCS#7 padding */ -+#define SAFE_SA_CMD0_PAD_CONS 0x00000080 /* constant padding */ -+#define SAFE_SA_CMD0_PAD_ZERO 0x000000c0 /* zero padding */ -+#define SAFE_SA_CMD0_CRYPT_ALG 0x00000f00 /* symmetric crypto algorithm */ -+#define SAFE_SA_CMD0_DES 0x00000000 /* DES crypto algorithm */ -+#define SAFE_SA_CMD0_3DES 0x00000100 /* 3DES crypto algorithm */ -+#define SAFE_SA_CMD0_AES 0x00000300 /* AES crypto algorithm */ -+#define SAFE_SA_CMD0_CRYPT_NULL 0x00000f00 /* null crypto algorithm */ -+#define SAFE_SA_CMD0_HASH_ALG 0x0000f000 /* hash algorithm */ -+#define SAFE_SA_CMD0_MD5 0x00000000 /* MD5 hash algorithm */ -+#define SAFE_SA_CMD0_SHA1 0x00001000 /* SHA-1 hash algorithm */ -+#define SAFE_SA_CMD0_HASH_NULL 0x0000f000 /* null hash algorithm */ -+#define SAFE_SA_CMD0_HDR_PROC 0x00080000 /* header processing */ -+#define SAFE_SA_CMD0_IBUSID 0x00300000 /* input bus id */ -+#define SAFE_SA_CMD0_IPCI 0x00100000 /* PCI input bus id */ -+#define SAFE_SA_CMD0_OBUSID 0x00c00000 /* output bus id */ -+#define SAFE_SA_CMD0_OPCI 0x00400000 /* PCI output bus id */ -+#define SAFE_SA_CMD0_IVLD 0x03000000 /* IV loading */ -+#define SAFE_SA_CMD0_IVLD_NONE 0x00000000 /* IV no load (reuse) */ -+#define SAFE_SA_CMD0_IVLD_IBUF 0x01000000 /* IV load from input buffer */ -+#define SAFE_SA_CMD0_IVLD_STATE 0x02000000 /* IV load from state */ -+#define SAFE_SA_CMD0_HSLD 0x0c000000 /* hash state loading */ -+#define SAFE_SA_CMD0_HSLD_SA 0x00000000 /* hash state load from SA */ -+#define SAFE_SA_CMD0_HSLD_STATE 0x08000000 /* hash state load from state */ -+#define SAFE_SA_CMD0_HSLD_NONE 0x0c000000 /* hash state no load */ -+#define SAFE_SA_CMD0_SAVEIV 0x10000000 /* save IV */ -+#define SAFE_SA_CMD0_SAVEHASH 0x20000000 /* save hash state */ -+#define SAFE_SA_CMD0_IGATHER 0x40000000 /* input gather */ -+#define SAFE_SA_CMD0_OSCATTER 0x80000000 /* output scatter */ -+ -+#define SAFE_SA_CMD1_HDRCOPY 0x00000002 /* copy header to output */ -+#define SAFE_SA_CMD1_PAYCOPY 0x00000004 /* copy payload to output */ -+#define SAFE_SA_CMD1_PADCOPY 0x00000008 /* copy pad to output */ -+#define SAFE_SA_CMD1_IPV4 0x00000000 /* IPv4 protocol */ -+#define SAFE_SA_CMD1_IPV6 0x00000010 /* IPv6 protocol */ -+#define SAFE_SA_CMD1_MUTABLE 0x00000020 /* mutable bit processing */ -+#define SAFE_SA_CMD1_SRBUSID 0x000000c0 /* state record bus id */ -+#define SAFE_SA_CMD1_SRPCI 0x00000040 /* state record from PCI */ -+#define SAFE_SA_CMD1_CRMODE 0x00000300 /* crypto mode */ -+#define SAFE_SA_CMD1_ECB 0x00000000 /* ECB crypto mode */ -+#define SAFE_SA_CMD1_CBC 0x00000100 /* CBC crypto mode */ -+#define SAFE_SA_CMD1_OFB 0x00000200 /* OFB crypto mode */ -+#define SAFE_SA_CMD1_CFB 0x00000300 /* CFB crypto mode */ -+#define SAFE_SA_CMD1_CRFEEDBACK 0x00000c00 /* crypto feedback mode */ -+#define SAFE_SA_CMD1_64BIT 0x00000000 /* 64-bit crypto feedback */ -+#define SAFE_SA_CMD1_8BIT 0x00000400 /* 8-bit crypto feedback */ -+#define SAFE_SA_CMD1_1BIT 0x00000800 /* 1-bit crypto feedback */ -+#define SAFE_SA_CMD1_128BIT 0x00000c00 /* 128-bit crypto feedback */ -+#define SAFE_SA_CMD1_OPTIONS 0x00001000 /* HMAC/options mutable bit */ -+#define SAFE_SA_CMD1_HMAC SAFE_SA_CMD1_OPTIONS -+#define SAFE_SA_CMD1_SAREV1 0x00008000 /* SA Revision 1 */ -+#define SAFE_SA_CMD1_OFFSET 0x00ff0000 /* hash/crypto offset(dwords) */ -+#define SAFE_SA_CMD1_OFFSET_S 16 -+#define SAFE_SA_CMD1_AESKEYLEN 0x0f000000 /* AES key length */ -+#define SAFE_SA_CMD1_AES128 0x02000000 /* 128-bit AES key */ -+#define SAFE_SA_CMD1_AES192 0x03000000 /* 192-bit AES key */ -+#define SAFE_SA_CMD1_AES256 0x04000000 /* 256-bit AES key */ -+ -+/* -+ * Security Associate State Record (Rev 1). -+ */ -+struct safe_sastate { -+ u_int32_t sa_saved_iv[4]; /* saved IV (DES/3DES/AES) */ -+ u_int32_t sa_saved_hashbc; /* saved hash byte count */ -+ u_int32_t sa_saved_indigest[5]; /* saved inner digest */ -+}; -+#endif /* _SAFE_SAFEREG_H_ */ -diff -Nur linux-2.6.39.orig/crypto/ocf/safe/safevar.h linux-2.6.39/crypto/ocf/safe/safevar.h ---- linux-2.6.39.orig/crypto/ocf/safe/safevar.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/safe/safevar.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,230 @@ -+/*- -+ * The linux port of this code done by David McCullough -+ * Copyright (C) 2004-2010 David McCullough -+ * The license and original author are listed below. -+ * -+ * Copyright (c) 2003 Sam Leffler, Errno Consulting -+ * Copyright (c) 2003 Global Technology Associates, Inc. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ * -+ * $FreeBSD: src/sys/dev/safe/safevar.h,v 1.2 2006/05/17 18:34:26 pjd Exp $ -+ */ -+#ifndef _SAFE_SAFEVAR_H_ -+#define _SAFE_SAFEVAR_H_ -+ -+/* Maximum queue length */ -+#ifndef SAFE_MAX_NQUEUE -+#define SAFE_MAX_NQUEUE 60 -+#endif -+ -+#define SAFE_MAX_PART 64 /* Maximum scatter/gather depth */ -+#define SAFE_DMA_BOUNDARY 0 /* No boundary for source DMA ops */ -+#define SAFE_MAX_DSIZE 2048 /* MCLBYTES Fixed scatter particle size */ -+#define SAFE_MAX_SSIZE 0x0ffff /* Maximum gather particle size */ -+#define SAFE_MAX_DMA 0xfffff /* Maximum PE operand size (20 bits) */ -+/* total src+dst particle descriptors */ -+#define SAFE_TOTAL_DPART (SAFE_MAX_NQUEUE * SAFE_MAX_PART) -+#define SAFE_TOTAL_SPART (SAFE_MAX_NQUEUE * SAFE_MAX_PART) -+ -+#define SAFE_RNG_MAXBUFSIZ 128 /* 32-bit words */ -+ -+#define SAFE_CARD(sid) (((sid) & 0xf0000000) >> 28) -+#define SAFE_SESSION(sid) ( (sid) & 0x0fffffff) -+#define SAFE_SID(crd, sesn) (((crd) << 28) | ((sesn) & 0x0fffffff)) -+ -+#define SAFE_DEF_RTY 0xff /* PCI Retry Timeout */ -+#define SAFE_DEF_TOUT 0xff /* PCI TRDY Timeout */ -+#define SAFE_DEF_CACHELINE 0x01 /* Cache Line setting */ -+ -+#ifdef __KERNEL__ -+/* -+ * State associated with the allocation of each chunk -+ * of memory setup for DMA. -+ */ -+struct safe_dma_alloc { -+ dma_addr_t dma_paddr; -+ void *dma_vaddr; -+}; -+ -+/* -+ * Cryptographic operand state. One of these exists for each -+ * source and destination operand passed in from the crypto -+ * subsystem. When possible source and destination operands -+ * refer to the same memory. More often they are distinct. -+ * We track the virtual address of each operand as well as -+ * where each is mapped for DMA. -+ */ -+struct safe_operand { -+ union { -+ struct sk_buff *skb; -+ struct uio *io; -+ } u; -+ void *map; -+ int mapsize; /* total number of bytes in segs */ -+ struct { -+ dma_addr_t ds_addr; -+ int ds_len; -+ int ds_tlen; -+ } segs[SAFE_MAX_PART]; -+ int nsegs; -+}; -+ -+/* -+ * Packet engine ring entry and cryptographic operation state. -+ * The packet engine requires a ring of descriptors that contain -+ * pointers to various cryptographic state. However the ring -+ * configuration register allows you to specify an arbitrary size -+ * for ring entries. We use this feature to collect most of the -+ * state for each cryptographic request into one spot. Other than -+ * ring entries only the ``particle descriptors'' (scatter/gather -+ * lists) and the actual operand data are kept separate. The -+ * particle descriptors must also be organized in rings. The -+ * operand data can be located aribtrarily (modulo alignment constraints). -+ * -+ * Note that the descriptor ring is mapped onto the PCI bus so -+ * the hardware can DMA data. This means the entire ring must be -+ * contiguous. -+ */ -+struct safe_ringentry { -+ struct safe_desc re_desc; /* command descriptor */ -+ struct safe_sarec re_sa; /* SA record */ -+ struct safe_sastate re_sastate; /* SA state record */ -+ -+ struct cryptop *re_crp; /* crypto operation */ -+ -+ struct safe_operand re_src; /* source operand */ -+ struct safe_operand re_dst; /* destination operand */ -+ -+ int re_sesn; /* crypto session ID */ -+ int re_flags; -+#define SAFE_QFLAGS_COPYOUTIV 0x1 /* copy back on completion */ -+#define SAFE_QFLAGS_COPYOUTICV 0x2 /* copy back on completion */ -+}; -+ -+#define re_src_skb re_src.u.skb -+#define re_src_io re_src.u.io -+#define re_src_map re_src.map -+#define re_src_nsegs re_src.nsegs -+#define re_src_segs re_src.segs -+#define re_src_mapsize re_src.mapsize -+ -+#define re_dst_skb re_dst.u.skb -+#define re_dst_io re_dst.u.io -+#define re_dst_map re_dst.map -+#define re_dst_nsegs re_dst.nsegs -+#define re_dst_segs re_dst.segs -+#define re_dst_mapsize re_dst.mapsize -+ -+struct rndstate_test; -+ -+struct safe_session { -+ u_int32_t ses_used; -+ u_int32_t ses_klen; /* key length in bits */ -+ u_int32_t ses_key[8]; /* DES/3DES/AES key */ -+ u_int32_t ses_mlen; /* hmac length in bytes */ -+ u_int32_t ses_hminner[5]; /* hmac inner state */ -+ u_int32_t ses_hmouter[5]; /* hmac outer state */ -+ u_int32_t ses_iv[4]; /* DES/3DES/AES iv */ -+}; -+ -+struct safe_pkq { -+ struct list_head pkq_list; -+ struct cryptkop *pkq_krp; -+}; -+ -+struct safe_softc { -+ softc_device_decl sc_dev; -+ u32 sc_irq; -+ -+ struct pci_dev *sc_pcidev; -+ ocf_iomem_t sc_base_addr; -+ -+ u_int sc_chiprev; /* major/minor chip revision */ -+ int sc_flags; /* device specific flags */ -+#define SAFE_FLAGS_KEY 0x01 /* has key accelerator */ -+#define SAFE_FLAGS_RNG 0x02 /* hardware rng */ -+ int sc_suspended; -+ int sc_needwakeup; /* notify crypto layer */ -+ int32_t sc_cid; /* crypto tag */ -+ -+ struct safe_dma_alloc sc_ringalloc; /* PE ring allocation state */ -+ struct safe_ringentry *sc_ring; /* PE ring */ -+ struct safe_ringentry *sc_ringtop; /* PE ring top */ -+ struct safe_ringentry *sc_front; /* next free entry */ -+ struct safe_ringentry *sc_back; /* next pending entry */ -+ int sc_nqchip; /* # passed to chip */ -+ spinlock_t sc_ringmtx; /* PE ring lock */ -+ struct safe_pdesc *sc_spring; /* src particle ring */ -+ struct safe_pdesc *sc_springtop; /* src particle ring top */ -+ struct safe_pdesc *sc_spfree; /* next free src particle */ -+ struct safe_dma_alloc sc_spalloc; /* src particle ring state */ -+ struct safe_pdesc *sc_dpring; /* dest particle ring */ -+ struct safe_pdesc *sc_dpringtop; /* dest particle ring top */ -+ struct safe_pdesc *sc_dpfree; /* next free dest particle */ -+ struct safe_dma_alloc sc_dpalloc; /* dst particle ring state */ -+ int sc_nsessions; /* # of sessions */ -+ struct safe_session *sc_sessions; /* sessions */ -+ -+ struct timer_list sc_pkto; /* PK polling */ -+ spinlock_t sc_pkmtx; /* PK lock */ -+ struct list_head sc_pkq; /* queue of PK requests */ -+ struct safe_pkq *sc_pkq_cur; /* current processing request */ -+ u_int32_t sc_pk_reslen, sc_pk_resoff; -+ -+ int sc_max_dsize; /* maximum safe DMA size */ -+}; -+#endif /* __KERNEL__ */ -+ -+struct safe_stats { -+ u_int64_t st_ibytes; -+ u_int64_t st_obytes; -+ u_int32_t st_ipackets; -+ u_int32_t st_opackets; -+ u_int32_t st_invalid; /* invalid argument */ -+ u_int32_t st_badsession; /* invalid session id */ -+ u_int32_t st_badflags; /* flags indicate !(mbuf | uio) */ -+ u_int32_t st_nodesc; /* op submitted w/o descriptors */ -+ u_int32_t st_badalg; /* unsupported algorithm */ -+ u_int32_t st_ringfull; /* PE descriptor ring full */ -+ u_int32_t st_peoperr; /* PE marked error */ -+ u_int32_t st_dmaerr; /* PE DMA error */ -+ u_int32_t st_bypasstoobig; /* bypass > 96 bytes */ -+ u_int32_t st_skipmismatch; /* enc part begins before auth part */ -+ u_int32_t st_lenmismatch; /* enc length different auth length */ -+ u_int32_t st_coffmisaligned; /* crypto offset not 32-bit aligned */ -+ u_int32_t st_cofftoobig; /* crypto offset > 255 words */ -+ u_int32_t st_iovmisaligned; /* iov op not aligned */ -+ u_int32_t st_iovnotuniform; /* iov op not suitable */ -+ u_int32_t st_unaligned; /* unaligned src caused copy */ -+ u_int32_t st_notuniform; /* non-uniform src caused copy */ -+ u_int32_t st_nomap; /* bus_dmamap_create failed */ -+ u_int32_t st_noload; /* bus_dmamap_load_* failed */ -+ u_int32_t st_nombuf; /* MGET* failed */ -+ u_int32_t st_nomcl; /* MCLGET* failed */ -+ u_int32_t st_maxqchip; /* max mcr1 ops out for processing */ -+ u_int32_t st_rng; /* RNG requests */ -+ u_int32_t st_rngalarm; /* RNG alarm requests */ -+ u_int32_t st_noicvcopy; /* ICV data copies suppressed */ -+}; -+#endif /* _SAFE_SAFEVAR_H_ */ -diff -Nur linux-2.6.39.orig/crypto/ocf/safe/sha1.c linux-2.6.39/crypto/ocf/safe/sha1.c ---- linux-2.6.39.orig/crypto/ocf/safe/sha1.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/safe/sha1.c 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,279 @@ -+/* $KAME: sha1.c,v 1.5 2000/11/08 06:13:08 itojun Exp $ */ -+/* -+ * Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. Neither the name of the project nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ */ -+ -+/* -+ * FIPS pub 180-1: Secure Hash Algorithm (SHA-1) -+ * based on: http://csrc.nist.gov/fips/fip180-1.txt -+ * implemented by Jun-ichiro itojun Itoh -+ */ -+ -+#if 0 -+#include -+__FBSDID("$FreeBSD: src/sys/crypto/sha1.c,v 1.9 2003/06/10 21:36:57 obrien Exp $"); -+ -+#include -+#include -+#include -+#include -+ -+#include -+#endif -+ -+/* sanity check */ -+#if BYTE_ORDER != BIG_ENDIAN -+# if BYTE_ORDER != LITTLE_ENDIAN -+# define unsupported 1 -+# endif -+#endif -+ -+#ifndef unsupported -+ -+/* constant table */ -+static u_int32_t _K[] = { 0x5a827999, 0x6ed9eba1, 0x8f1bbcdc, 0xca62c1d6 }; -+#define K(t) _K[(t) / 20] -+ -+#define F0(b, c, d) (((b) & (c)) | ((~(b)) & (d))) -+#define F1(b, c, d) (((b) ^ (c)) ^ (d)) -+#define F2(b, c, d) (((b) & (c)) | ((b) & (d)) | ((c) & (d))) -+#define F3(b, c, d) (((b) ^ (c)) ^ (d)) -+ -+#define S(n, x) (((x) << (n)) | ((x) >> (32 - n))) -+ -+#undef H -+#define H(n) (ctxt->h.b32[(n)]) -+#define COUNT (ctxt->count) -+#define BCOUNT (ctxt->c.b64[0] / 8) -+#define W(n) (ctxt->m.b32[(n)]) -+ -+#define PUTBYTE(x) { \ -+ ctxt->m.b8[(COUNT % 64)] = (x); \ -+ COUNT++; \ -+ COUNT %= 64; \ -+ ctxt->c.b64[0] += 8; \ -+ if (COUNT % 64 == 0) \ -+ sha1_step(ctxt); \ -+ } -+ -+#define PUTPAD(x) { \ -+ ctxt->m.b8[(COUNT % 64)] = (x); \ -+ COUNT++; \ -+ COUNT %= 64; \ -+ if (COUNT % 64 == 0) \ -+ sha1_step(ctxt); \ -+ } -+ -+static void sha1_step(struct sha1_ctxt *); -+ -+static void -+sha1_step(ctxt) -+ struct sha1_ctxt *ctxt; -+{ -+ u_int32_t a, b, c, d, e; -+ size_t t, s; -+ u_int32_t tmp; -+ -+#if BYTE_ORDER == LITTLE_ENDIAN -+ struct sha1_ctxt tctxt; -+ bcopy(&ctxt->m.b8[0], &tctxt.m.b8[0], 64); -+ ctxt->m.b8[0] = tctxt.m.b8[3]; ctxt->m.b8[1] = tctxt.m.b8[2]; -+ ctxt->m.b8[2] = tctxt.m.b8[1]; ctxt->m.b8[3] = tctxt.m.b8[0]; -+ ctxt->m.b8[4] = tctxt.m.b8[7]; ctxt->m.b8[5] = tctxt.m.b8[6]; -+ ctxt->m.b8[6] = tctxt.m.b8[5]; ctxt->m.b8[7] = tctxt.m.b8[4]; -+ ctxt->m.b8[8] = tctxt.m.b8[11]; ctxt->m.b8[9] = tctxt.m.b8[10]; -+ ctxt->m.b8[10] = tctxt.m.b8[9]; ctxt->m.b8[11] = tctxt.m.b8[8]; -+ ctxt->m.b8[12] = tctxt.m.b8[15]; ctxt->m.b8[13] = tctxt.m.b8[14]; -+ ctxt->m.b8[14] = tctxt.m.b8[13]; ctxt->m.b8[15] = tctxt.m.b8[12]; -+ ctxt->m.b8[16] = tctxt.m.b8[19]; ctxt->m.b8[17] = tctxt.m.b8[18]; -+ ctxt->m.b8[18] = tctxt.m.b8[17]; ctxt->m.b8[19] = tctxt.m.b8[16]; -+ ctxt->m.b8[20] = tctxt.m.b8[23]; ctxt->m.b8[21] = tctxt.m.b8[22]; -+ ctxt->m.b8[22] = tctxt.m.b8[21]; ctxt->m.b8[23] = tctxt.m.b8[20]; -+ ctxt->m.b8[24] = tctxt.m.b8[27]; ctxt->m.b8[25] = tctxt.m.b8[26]; -+ ctxt->m.b8[26] = tctxt.m.b8[25]; ctxt->m.b8[27] = tctxt.m.b8[24]; -+ ctxt->m.b8[28] = tctxt.m.b8[31]; ctxt->m.b8[29] = tctxt.m.b8[30]; -+ ctxt->m.b8[30] = tctxt.m.b8[29]; ctxt->m.b8[31] = tctxt.m.b8[28]; -+ ctxt->m.b8[32] = tctxt.m.b8[35]; ctxt->m.b8[33] = tctxt.m.b8[34]; -+ ctxt->m.b8[34] = tctxt.m.b8[33]; ctxt->m.b8[35] = tctxt.m.b8[32]; -+ ctxt->m.b8[36] = tctxt.m.b8[39]; ctxt->m.b8[37] = tctxt.m.b8[38]; -+ ctxt->m.b8[38] = tctxt.m.b8[37]; ctxt->m.b8[39] = tctxt.m.b8[36]; -+ ctxt->m.b8[40] = tctxt.m.b8[43]; ctxt->m.b8[41] = tctxt.m.b8[42]; -+ ctxt->m.b8[42] = tctxt.m.b8[41]; ctxt->m.b8[43] = tctxt.m.b8[40]; -+ ctxt->m.b8[44] = tctxt.m.b8[47]; ctxt->m.b8[45] = tctxt.m.b8[46]; -+ ctxt->m.b8[46] = tctxt.m.b8[45]; ctxt->m.b8[47] = tctxt.m.b8[44]; -+ ctxt->m.b8[48] = tctxt.m.b8[51]; ctxt->m.b8[49] = tctxt.m.b8[50]; -+ ctxt->m.b8[50] = tctxt.m.b8[49]; ctxt->m.b8[51] = tctxt.m.b8[48]; -+ ctxt->m.b8[52] = tctxt.m.b8[55]; ctxt->m.b8[53] = tctxt.m.b8[54]; -+ ctxt->m.b8[54] = tctxt.m.b8[53]; ctxt->m.b8[55] = tctxt.m.b8[52]; -+ ctxt->m.b8[56] = tctxt.m.b8[59]; ctxt->m.b8[57] = tctxt.m.b8[58]; -+ ctxt->m.b8[58] = tctxt.m.b8[57]; ctxt->m.b8[59] = tctxt.m.b8[56]; -+ ctxt->m.b8[60] = tctxt.m.b8[63]; ctxt->m.b8[61] = tctxt.m.b8[62]; -+ ctxt->m.b8[62] = tctxt.m.b8[61]; ctxt->m.b8[63] = tctxt.m.b8[60]; -+#endif -+ -+ a = H(0); b = H(1); c = H(2); d = H(3); e = H(4); -+ -+ for (t = 0; t < 20; t++) { -+ s = t & 0x0f; -+ if (t >= 16) { -+ W(s) = S(1, W((s+13) & 0x0f) ^ W((s+8) & 0x0f) ^ W((s+2) & 0x0f) ^ W(s)); -+ } -+ tmp = S(5, a) + F0(b, c, d) + e + W(s) + K(t); -+ e = d; d = c; c = S(30, b); b = a; a = tmp; -+ } -+ for (t = 20; t < 40; t++) { -+ s = t & 0x0f; -+ W(s) = S(1, W((s+13) & 0x0f) ^ W((s+8) & 0x0f) ^ W((s+2) & 0x0f) ^ W(s)); -+ tmp = S(5, a) + F1(b, c, d) + e + W(s) + K(t); -+ e = d; d = c; c = S(30, b); b = a; a = tmp; -+ } -+ for (t = 40; t < 60; t++) { -+ s = t & 0x0f; -+ W(s) = S(1, W((s+13) & 0x0f) ^ W((s+8) & 0x0f) ^ W((s+2) & 0x0f) ^ W(s)); -+ tmp = S(5, a) + F2(b, c, d) + e + W(s) + K(t); -+ e = d; d = c; c = S(30, b); b = a; a = tmp; -+ } -+ for (t = 60; t < 80; t++) { -+ s = t & 0x0f; -+ W(s) = S(1, W((s+13) & 0x0f) ^ W((s+8) & 0x0f) ^ W((s+2) & 0x0f) ^ W(s)); -+ tmp = S(5, a) + F3(b, c, d) + e + W(s) + K(t); -+ e = d; d = c; c = S(30, b); b = a; a = tmp; -+ } -+ -+ H(0) = H(0) + a; -+ H(1) = H(1) + b; -+ H(2) = H(2) + c; -+ H(3) = H(3) + d; -+ H(4) = H(4) + e; -+ -+ bzero(&ctxt->m.b8[0], 64); -+} -+ -+/*------------------------------------------------------------*/ -+ -+void -+sha1_init(ctxt) -+ struct sha1_ctxt *ctxt; -+{ -+ bzero(ctxt, sizeof(struct sha1_ctxt)); -+ H(0) = 0x67452301; -+ H(1) = 0xefcdab89; -+ H(2) = 0x98badcfe; -+ H(3) = 0x10325476; -+ H(4) = 0xc3d2e1f0; -+} -+ -+void -+sha1_pad(ctxt) -+ struct sha1_ctxt *ctxt; -+{ -+ size_t padlen; /*pad length in bytes*/ -+ size_t padstart; -+ -+ PUTPAD(0x80); -+ -+ padstart = COUNT % 64; -+ padlen = 64 - padstart; -+ if (padlen < 8) { -+ bzero(&ctxt->m.b8[padstart], padlen); -+ COUNT += padlen; -+ COUNT %= 64; -+ sha1_step(ctxt); -+ padstart = COUNT % 64; /* should be 0 */ -+ padlen = 64 - padstart; /* should be 64 */ -+ } -+ bzero(&ctxt->m.b8[padstart], padlen - 8); -+ COUNT += (padlen - 8); -+ COUNT %= 64; -+#if BYTE_ORDER == BIG_ENDIAN -+ PUTPAD(ctxt->c.b8[0]); PUTPAD(ctxt->c.b8[1]); -+ PUTPAD(ctxt->c.b8[2]); PUTPAD(ctxt->c.b8[3]); -+ PUTPAD(ctxt->c.b8[4]); PUTPAD(ctxt->c.b8[5]); -+ PUTPAD(ctxt->c.b8[6]); PUTPAD(ctxt->c.b8[7]); -+#else -+ PUTPAD(ctxt->c.b8[7]); PUTPAD(ctxt->c.b8[6]); -+ PUTPAD(ctxt->c.b8[5]); PUTPAD(ctxt->c.b8[4]); -+ PUTPAD(ctxt->c.b8[3]); PUTPAD(ctxt->c.b8[2]); -+ PUTPAD(ctxt->c.b8[1]); PUTPAD(ctxt->c.b8[0]); -+#endif -+} -+ -+void -+sha1_loop(ctxt, input, len) -+ struct sha1_ctxt *ctxt; -+ const u_int8_t *input; -+ size_t len; -+{ -+ size_t gaplen; -+ size_t gapstart; -+ size_t off; -+ size_t copysiz; -+ -+ off = 0; -+ -+ while (off < len) { -+ gapstart = COUNT % 64; -+ gaplen = 64 - gapstart; -+ -+ copysiz = (gaplen < len - off) ? gaplen : len - off; -+ bcopy(&input[off], &ctxt->m.b8[gapstart], copysiz); -+ COUNT += copysiz; -+ COUNT %= 64; -+ ctxt->c.b64[0] += copysiz * 8; -+ if (COUNT % 64 == 0) -+ sha1_step(ctxt); -+ off += copysiz; -+ } -+} -+ -+void -+sha1_result(ctxt, digest0) -+ struct sha1_ctxt *ctxt; -+ caddr_t digest0; -+{ -+ u_int8_t *digest; -+ -+ digest = (u_int8_t *)digest0; -+ sha1_pad(ctxt); -+#if BYTE_ORDER == BIG_ENDIAN -+ bcopy(&ctxt->h.b8[0], digest, 20); -+#else -+ digest[0] = ctxt->h.b8[3]; digest[1] = ctxt->h.b8[2]; -+ digest[2] = ctxt->h.b8[1]; digest[3] = ctxt->h.b8[0]; -+ digest[4] = ctxt->h.b8[7]; digest[5] = ctxt->h.b8[6]; -+ digest[6] = ctxt->h.b8[5]; digest[7] = ctxt->h.b8[4]; -+ digest[8] = ctxt->h.b8[11]; digest[9] = ctxt->h.b8[10]; -+ digest[10] = ctxt->h.b8[9]; digest[11] = ctxt->h.b8[8]; -+ digest[12] = ctxt->h.b8[15]; digest[13] = ctxt->h.b8[14]; -+ digest[14] = ctxt->h.b8[13]; digest[15] = ctxt->h.b8[12]; -+ digest[16] = ctxt->h.b8[19]; digest[17] = ctxt->h.b8[18]; -+ digest[18] = ctxt->h.b8[17]; digest[19] = ctxt->h.b8[16]; -+#endif -+} -+ -+#endif /*unsupported*/ -diff -Nur linux-2.6.39.orig/crypto/ocf/safe/sha1.h linux-2.6.39/crypto/ocf/safe/sha1.h ---- linux-2.6.39.orig/crypto/ocf/safe/sha1.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/safe/sha1.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,72 @@ -+/* $FreeBSD: src/sys/crypto/sha1.h,v 1.8 2002/03/20 05:13:50 alfred Exp $ */ -+/* $KAME: sha1.h,v 1.5 2000/03/27 04:36:23 sumikawa Exp $ */ -+ -+/* -+ * Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. Neither the name of the project nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ */ -+/* -+ * FIPS pub 180-1: Secure Hash Algorithm (SHA-1) -+ * based on: http://csrc.nist.gov/fips/fip180-1.txt -+ * implemented by Jun-ichiro itojun Itoh -+ */ -+ -+#ifndef _NETINET6_SHA1_H_ -+#define _NETINET6_SHA1_H_ -+ -+struct sha1_ctxt { -+ union { -+ u_int8_t b8[20]; -+ u_int32_t b32[5]; -+ } h; -+ union { -+ u_int8_t b8[8]; -+ u_int64_t b64[1]; -+ } c; -+ union { -+ u_int8_t b8[64]; -+ u_int32_t b32[16]; -+ } m; -+ u_int8_t count; -+}; -+ -+#ifdef __KERNEL__ -+extern void sha1_init(struct sha1_ctxt *); -+extern void sha1_pad(struct sha1_ctxt *); -+extern void sha1_loop(struct sha1_ctxt *, const u_int8_t *, size_t); -+extern void sha1_result(struct sha1_ctxt *, caddr_t); -+ -+/* compatibilty with other SHA1 source codes */ -+typedef struct sha1_ctxt SHA1_CTX; -+#define SHA1Init(x) sha1_init((x)) -+#define SHA1Update(x, y, z) sha1_loop((x), (y), (z)) -+#define SHA1Final(x, y) sha1_result((y), (x)) -+#endif /* __KERNEL__ */ -+ -+#define SHA1_RESULTLEN (160/8) -+ -+#endif /*_NETINET6_SHA1_H_*/ -diff -Nur linux-2.6.39.orig/crypto/ocf/talitos/Makefile linux-2.6.39/crypto/ocf/talitos/Makefile ---- linux-2.6.39.orig/crypto/ocf/talitos/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/talitos/Makefile 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,12 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+obj-$(CONFIG_OCF_TALITOS) += talitos.o -+ -+obj ?= . -+EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff -Nur linux-2.6.39.orig/crypto/ocf/talitos/talitos.c linux-2.6.39/crypto/ocf/talitos/talitos.c ---- linux-2.6.39.orig/crypto/ocf/talitos/talitos.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/talitos/talitos.c 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,1359 @@ -+/* -+ * crypto/ocf/talitos/talitos.c -+ * -+ * An OCF-Linux module that uses Freescale's SEC to do the crypto. -+ * Based on crypto/ocf/hifn and crypto/ocf/safe OCF drivers -+ * -+ * Copyright (c) 2006 Freescale Semiconductor, Inc. -+ * -+ * This code written by Kim A. B. Phillips -+ * some code copied from files with the following: -+ * Copyright (C) 2004-2007 David McCullough -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * --------------------------------------------------------------------------- -+ * -+ * NOTES: -+ * -+ * The Freescale SEC (also known as 'talitos') resides on the -+ * internal bus, and runs asynchronous to the processor core. It has -+ * a wide gamut of cryptographic acceleration features, including single- -+ * pass IPsec (also known as algorithm chaining). To properly utilize -+ * all of the SEC's performance enhancing features, further reworking -+ * of higher level code (framework, applications) will be necessary. -+ * -+ * The following table shows which SEC version is present in which devices: -+ * -+ * Devices SEC version -+ * -+ * 8272, 8248 SEC 1.0 -+ * 885, 875 SEC 1.2 -+ * 8555E, 8541E SEC 2.0 -+ * 8349E SEC 2.01 -+ * 8548E SEC 2.1 -+ * -+ * The following table shows the features offered by each SEC version: -+ * -+ * Max. chan- -+ * version Bus I/F Clock nels DEU AESU AFEU MDEU PKEU RNG KEU -+ * -+ * SEC 1.0 internal 64b 100MHz 4 1 1 1 1 1 1 0 -+ * SEC 1.2 internal 32b 66MHz 1 1 1 0 1 0 0 0 -+ * SEC 2.0 internal 64b 166MHz 4 1 1 1 1 1 1 0 -+ * SEC 2.01 internal 64b 166MHz 4 1 1 1 1 1 1 0 -+ * SEC 2.1 internal 64b 333MHz 4 1 1 1 1 1 1 1 -+ * -+ * Each execution unit in the SEC has two modes of execution; channel and -+ * slave/debug. This driver employs the channel infrastructure in the -+ * device for convenience. Only the RNG is directly accessed due to the -+ * convenience of its random fifo pool. The relationship between the -+ * channels and execution units is depicted in the following diagram: -+ * -+ * ------- ------------ -+ * ---| ch0 |---| | -+ * ------- | | -+ * | |------+-------+-------+-------+------------ -+ * ------- | | | | | | | -+ * ---| ch1 |---| | | | | | | -+ * ------- | | ------ ------ ------ ------ ------ -+ * |controller| |DEU | |AESU| |MDEU| |PKEU| ... |RNG | -+ * ------- | | ------ ------ ------ ------ ------ -+ * ---| ch2 |---| | | | | | | -+ * ------- | | | | | | | -+ * | |------+-------+-------+-------+------------ -+ * ------- | | -+ * ---| ch3 |---| | -+ * ------- ------------ -+ * -+ * Channel ch0 may drive an aes operation to the aes unit (AESU), -+ * and, at the same time, ch1 may drive a message digest operation -+ * to the mdeu. Each channel has an input descriptor FIFO, and the -+ * FIFO can contain, e.g. on the 8541E, up to 24 entries, before a -+ * a buffer overrun error is triggered. The controller is responsible -+ * for fetching the data from descriptor pointers, and passing the -+ * data to the appropriate EUs. The controller also writes the -+ * cryptographic operation's result to memory. The SEC notifies -+ * completion by triggering an interrupt and/or setting the 1st byte -+ * of the hdr field to 0xff. -+ * -+ * TODO: -+ * o support more algorithms -+ * o support more versions of the SEC -+ * o add support for linux 2.4 -+ * o scatter-gather (sg) support -+ * o add support for public key ops (PKEU) -+ * o add statistics -+ */ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include /* dma_map_single() */ -+#include -+ -+#include -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,15) -+#include -+#endif -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) -+#include -+#endif -+ -+#include -+#include -+ -+#define DRV_NAME "talitos" -+ -+#include "talitos_dev.h" -+#include "talitos_soft.h" -+ -+#define read_random(p,l) get_random_bytes(p,l) -+ -+const char talitos_driver_name[] = "Talitos OCF"; -+const char talitos_driver_version[] = "0.2"; -+ -+static int talitos_newsession(device_t dev, u_int32_t *sidp, -+ struct cryptoini *cri); -+static int talitos_freesession(device_t dev, u_int64_t tid); -+static int talitos_process(device_t dev, struct cryptop *crp, int hint); -+static void dump_talitos_status(struct talitos_softc *sc); -+static int talitos_submit(struct talitos_softc *sc, struct talitos_desc *td, -+ int chsel); -+static void talitos_doneprocessing(struct talitos_softc *sc); -+static void talitos_init_device(struct talitos_softc *sc); -+static void talitos_reset_device_master(struct talitos_softc *sc); -+static void talitos_reset_device(struct talitos_softc *sc); -+static void talitos_errorprocessing(struct talitos_softc *sc); -+#ifdef CONFIG_PPC_MERGE -+static int talitos_probe(struct of_device *ofdev, const struct of_device_id *match); -+static int talitos_remove(struct of_device *ofdev); -+#else -+static int talitos_probe(struct platform_device *pdev); -+static int talitos_remove(struct platform_device *pdev); -+#endif -+#ifdef CONFIG_OCF_RANDOMHARVEST -+static int talitos_read_random(void *arg, u_int32_t *buf, int maxwords); -+static void talitos_rng_init(struct talitos_softc *sc); -+#endif -+ -+static device_method_t talitos_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, talitos_newsession), -+ DEVMETHOD(cryptodev_freesession,talitos_freesession), -+ DEVMETHOD(cryptodev_process, talitos_process), -+}; -+ -+#define debug talitos_debug -+int talitos_debug = 0; -+module_param(talitos_debug, int, 0644); -+MODULE_PARM_DESC(talitos_debug, "Enable debug"); -+ -+static inline void talitos_write(volatile unsigned *addr, u32 val) -+{ -+ out_be32(addr, val); -+} -+ -+static inline u32 talitos_read(volatile unsigned *addr) -+{ -+ u32 val; -+ val = in_be32(addr); -+ return val; -+} -+ -+static void dump_talitos_status(struct talitos_softc *sc) -+{ -+ unsigned int v, v_hi, i, *ptr; -+ v = talitos_read(sc->sc_base_addr + TALITOS_MCR); -+ v_hi = talitos_read(sc->sc_base_addr + TALITOS_MCR_HI); -+ printk(KERN_INFO "%s: MCR 0x%08x_%08x\n", -+ device_get_nameunit(sc->sc_cdev), v, v_hi); -+ v = talitos_read(sc->sc_base_addr + TALITOS_IMR); -+ v_hi = talitos_read(sc->sc_base_addr + TALITOS_IMR_HI); -+ printk(KERN_INFO "%s: IMR 0x%08x_%08x\n", -+ device_get_nameunit(sc->sc_cdev), v, v_hi); -+ v = talitos_read(sc->sc_base_addr + TALITOS_ISR); -+ v_hi = talitos_read(sc->sc_base_addr + TALITOS_ISR_HI); -+ printk(KERN_INFO "%s: ISR 0x%08x_%08x\n", -+ device_get_nameunit(sc->sc_cdev), v, v_hi); -+ for (i = 0; i < sc->sc_num_channels; i++) { -+ v = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + -+ TALITOS_CH_CDPR); -+ v_hi = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + -+ TALITOS_CH_CDPR_HI); -+ printk(KERN_INFO "%s: CDPR ch%d 0x%08x_%08x\n", -+ device_get_nameunit(sc->sc_cdev), i, v, v_hi); -+ } -+ for (i = 0; i < sc->sc_num_channels; i++) { -+ v = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + -+ TALITOS_CH_CCPSR); -+ v_hi = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + -+ TALITOS_CH_CCPSR_HI); -+ printk(KERN_INFO "%s: CCPSR ch%d 0x%08x_%08x\n", -+ device_get_nameunit(sc->sc_cdev), i, v, v_hi); -+ } -+ ptr = sc->sc_base_addr + TALITOS_CH_DESCBUF; -+ for (i = 0; i < 16; i++) { -+ v = talitos_read(ptr++); v_hi = talitos_read(ptr++); -+ printk(KERN_INFO "%s: DESCBUF ch0 0x%08x_%08x (tdp%02d)\n", -+ device_get_nameunit(sc->sc_cdev), v, v_hi, i); -+ } -+ return; -+} -+ -+ -+#ifdef CONFIG_OCF_RANDOMHARVEST -+/* -+ * pull random numbers off the RNG FIFO, not exceeding amount available -+ */ -+static int -+talitos_read_random(void *arg, u_int32_t *buf, int maxwords) -+{ -+ struct talitos_softc *sc = (struct talitos_softc *) arg; -+ int rc; -+ u_int32_t v; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ /* check for things like FIFO underflow */ -+ v = talitos_read(sc->sc_base_addr + TALITOS_RNGISR_HI); -+ if (unlikely(v)) { -+ printk(KERN_ERR "%s: RNGISR_HI error %08x\n", -+ device_get_nameunit(sc->sc_cdev), v); -+ return 0; -+ } -+ /* -+ * OFL is number of available 64-bit words, -+ * shift and convert to a 32-bit word count -+ */ -+ v = talitos_read(sc->sc_base_addr + TALITOS_RNGSR_HI); -+ v = (v & TALITOS_RNGSR_HI_OFL) >> (16 - 1); -+ if (maxwords > v) -+ maxwords = v; -+ for (rc = 0; rc < maxwords; rc++) { -+ buf[rc] = talitos_read(sc->sc_base_addr + -+ TALITOS_RNG_FIFO + rc*sizeof(u_int32_t)); -+ } -+ if (maxwords & 1) { -+ /* -+ * RNG will complain with an AE in the RNGISR -+ * if we don't complete the pairs of 32-bit reads -+ * to its 64-bit register based FIFO -+ */ -+ v = talitos_read(sc->sc_base_addr + -+ TALITOS_RNG_FIFO + rc*sizeof(u_int32_t)); -+ } -+ -+ return rc; -+} -+ -+static void -+talitos_rng_init(struct talitos_softc *sc) -+{ -+ u_int32_t v; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ /* reset RNG EU */ -+ v = talitos_read(sc->sc_base_addr + TALITOS_RNGRCR_HI); -+ v |= TALITOS_RNGRCR_HI_SR; -+ talitos_write(sc->sc_base_addr + TALITOS_RNGRCR_HI, v); -+ while ((talitos_read(sc->sc_base_addr + TALITOS_RNGSR_HI) -+ & TALITOS_RNGSR_HI_RD) == 0) -+ cpu_relax(); -+ /* -+ * we tell the RNG to start filling the RNG FIFO -+ * by writing the RNGDSR -+ */ -+ v = talitos_read(sc->sc_base_addr + TALITOS_RNGDSR_HI); -+ talitos_write(sc->sc_base_addr + TALITOS_RNGDSR_HI, v); -+ /* -+ * 64 bits of data will be pushed onto the FIFO every -+ * 256 SEC cycles until the FIFO is full. The RNG then -+ * attempts to keep the FIFO full. -+ */ -+ v = talitos_read(sc->sc_base_addr + TALITOS_RNGISR_HI); -+ if (v) { -+ printk(KERN_ERR "%s: RNGISR_HI error %08x\n", -+ device_get_nameunit(sc->sc_cdev), v); -+ return; -+ } -+ /* -+ * n.b. we need to add a FIPS test here - if the RNG is going -+ * to fail, it's going to fail at reset time -+ */ -+ return; -+} -+#endif /* CONFIG_OCF_RANDOMHARVEST */ -+ -+/* -+ * Generate a new software session. -+ */ -+static int -+talitos_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) -+{ -+ struct cryptoini *c, *encini = NULL, *macini = NULL; -+ struct talitos_softc *sc = device_get_softc(dev); -+ struct talitos_session *ses = NULL; -+ int sesn; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ if (sidp == NULL || cri == NULL || sc == NULL) { -+ DPRINTF("%s,%d - EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ for (c = cri; c != NULL; c = c->cri_next) { -+ if (c->cri_alg == CRYPTO_MD5 || -+ c->cri_alg == CRYPTO_MD5_HMAC || -+ c->cri_alg == CRYPTO_SHA1 || -+ c->cri_alg == CRYPTO_SHA1_HMAC || -+ c->cri_alg == CRYPTO_NULL_HMAC) { -+ if (macini) -+ return EINVAL; -+ macini = c; -+ } else if (c->cri_alg == CRYPTO_DES_CBC || -+ c->cri_alg == CRYPTO_3DES_CBC || -+ c->cri_alg == CRYPTO_AES_CBC || -+ c->cri_alg == CRYPTO_NULL_CBC) { -+ if (encini) -+ return EINVAL; -+ encini = c; -+ } else { -+ DPRINTF("UNKNOWN c->cri_alg %d\n", encini->cri_alg); -+ return EINVAL; -+ } -+ } -+ if (encini == NULL && macini == NULL) -+ return EINVAL; -+ if (encini) { -+ /* validate key length */ -+ switch (encini->cri_alg) { -+ case CRYPTO_DES_CBC: -+ if (encini->cri_klen != 64) -+ return EINVAL; -+ break; -+ case CRYPTO_3DES_CBC: -+ if (encini->cri_klen != 192) { -+ return EINVAL; -+ } -+ break; -+ case CRYPTO_AES_CBC: -+ if (encini->cri_klen != 128 && -+ encini->cri_klen != 192 && -+ encini->cri_klen != 256) -+ return EINVAL; -+ break; -+ default: -+ DPRINTF("UNKNOWN encini->cri_alg %d\n", -+ encini->cri_alg); -+ return EINVAL; -+ } -+ } -+ -+ if (sc->sc_sessions == NULL) { -+ ses = sc->sc_sessions = (struct talitos_session *) -+ kmalloc(sizeof(struct talitos_session), SLAB_ATOMIC); -+ if (ses == NULL) -+ return ENOMEM; -+ memset(ses, 0, sizeof(struct talitos_session)); -+ sesn = 0; -+ sc->sc_nsessions = 1; -+ } else { -+ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { -+ if (sc->sc_sessions[sesn].ses_used == 0) { -+ ses = &sc->sc_sessions[sesn]; -+ break; -+ } -+ } -+ -+ if (ses == NULL) { -+ /* allocating session */ -+ sesn = sc->sc_nsessions; -+ ses = (struct talitos_session *) kmalloc( -+ (sesn + 1) * sizeof(struct talitos_session), -+ SLAB_ATOMIC); -+ if (ses == NULL) -+ return ENOMEM; -+ memset(ses, 0, -+ (sesn + 1) * sizeof(struct talitos_session)); -+ memcpy(ses, sc->sc_sessions, -+ sesn * sizeof(struct talitos_session)); -+ memset(sc->sc_sessions, 0, -+ sesn * sizeof(struct talitos_session)); -+ kfree(sc->sc_sessions); -+ sc->sc_sessions = ses; -+ ses = &sc->sc_sessions[sesn]; -+ sc->sc_nsessions++; -+ } -+ } -+ -+ ses->ses_used = 1; -+ -+ if (encini) { -+ /* get an IV */ -+ /* XXX may read fewer than requested */ -+ read_random(ses->ses_iv, sizeof(ses->ses_iv)); -+ -+ ses->ses_klen = (encini->cri_klen + 7) / 8; -+ memcpy(ses->ses_key, encini->cri_key, ses->ses_klen); -+ if (macini) { -+ /* doing hash on top of cipher */ -+ ses->ses_hmac_len = (macini->cri_klen + 7) / 8; -+ memcpy(ses->ses_hmac, macini->cri_key, -+ ses->ses_hmac_len); -+ } -+ } else if (macini) { -+ /* doing hash */ -+ ses->ses_klen = (macini->cri_klen + 7) / 8; -+ memcpy(ses->ses_key, macini->cri_key, ses->ses_klen); -+ } -+ -+ /* back compat way of determining MSC result len */ -+ if (macini) { -+ ses->ses_mlen = macini->cri_mlen; -+ if (ses->ses_mlen == 0) { -+ if (macini->cri_alg == CRYPTO_MD5_HMAC) -+ ses->ses_mlen = MD5_HASH_LEN; -+ else -+ ses->ses_mlen = SHA1_HASH_LEN; -+ } -+ } -+ -+ /* really should make up a template td here, -+ * and only fill things like i/o and direction in process() */ -+ -+ /* assign session ID */ -+ *sidp = TALITOS_SID(sc->sc_num, sesn); -+ return 0; -+} -+ -+/* -+ * Deallocate a session. -+ */ -+static int -+talitos_freesession(device_t dev, u_int64_t tid) -+{ -+ struct talitos_softc *sc = device_get_softc(dev); -+ int session, ret; -+ u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; -+ -+ if (sc == NULL) -+ return EINVAL; -+ session = TALITOS_SESSION(sid); -+ if (session < sc->sc_nsessions) { -+ memset(&sc->sc_sessions[session], 0, -+ sizeof(sc->sc_sessions[session])); -+ ret = 0; -+ } else -+ ret = EINVAL; -+ return ret; -+} -+ -+/* -+ * launch device processing - it will come back with done notification -+ * in the form of an interrupt and/or HDR_DONE_BITS in header -+ */ -+static int -+talitos_submit( -+ struct talitos_softc *sc, -+ struct talitos_desc *td, -+ int chsel) -+{ -+ u_int32_t v; -+ -+ v = dma_map_single(NULL, td, sizeof(*td), DMA_TO_DEVICE); -+ talitos_write(sc->sc_base_addr + -+ chsel*TALITOS_CH_OFFSET + TALITOS_CH_FF, 0); -+ talitos_write(sc->sc_base_addr + -+ chsel*TALITOS_CH_OFFSET + TALITOS_CH_FF_HI, v); -+ return 0; -+} -+ -+static int -+talitos_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ int i, err = 0, ivsize; -+ struct talitos_softc *sc = device_get_softc(dev); -+ struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; -+ caddr_t iv; -+ struct talitos_session *ses; -+ struct talitos_desc *td; -+ unsigned long flags; -+ /* descriptor mappings */ -+ int hmac_key, hmac_data, cipher_iv, cipher_key, -+ in_fifo, out_fifo, cipher_iv_out; -+ static int chsel = -1; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { -+ return EINVAL; -+ } -+ crp->crp_etype = 0; -+ if (TALITOS_SESSION(crp->crp_sid) >= sc->sc_nsessions) { -+ return EINVAL; -+ } -+ -+ ses = &sc->sc_sessions[TALITOS_SESSION(crp->crp_sid)]; -+ -+ /* enter the channel scheduler */ -+ spin_lock_irqsave(&sc->sc_chnfifolock[sc->sc_num_channels], flags); -+ -+ /* reuse channel that already had/has requests for the required EU */ -+ for (i = 0; i < sc->sc_num_channels; i++) { -+ if (sc->sc_chnlastalg[i] == crp->crp_desc->crd_alg) -+ break; -+ } -+ if (i == sc->sc_num_channels) { -+ /* -+ * haven't seen this algo the last sc_num_channels or more -+ * use round robin in this case -+ * nb: sc->sc_num_channels must be power of 2 -+ */ -+ chsel = (chsel + 1) & (sc->sc_num_channels - 1); -+ } else { -+ /* -+ * matches channel with same target execution unit; -+ * use same channel in this case -+ */ -+ chsel = i; -+ } -+ sc->sc_chnlastalg[chsel] = crp->crp_desc->crd_alg; -+ -+ /* release the channel scheduler lock */ -+ spin_unlock_irqrestore(&sc->sc_chnfifolock[sc->sc_num_channels], flags); -+ -+ /* acquire the selected channel fifo lock */ -+ spin_lock_irqsave(&sc->sc_chnfifolock[chsel], flags); -+ -+ /* find and reserve next available descriptor-cryptop pair */ -+ for (i = 0; i < sc->sc_chfifo_len; i++) { -+ if (sc->sc_chnfifo[chsel][i].cf_desc.hdr == 0) { -+ /* -+ * ensure correct descriptor formation by -+ * avoiding inadvertently setting "optional" entries -+ * e.g. not using "optional" dptr2 for MD/HMAC descs -+ */ -+ memset(&sc->sc_chnfifo[chsel][i].cf_desc, -+ 0, sizeof(*td)); -+ /* reserve it with done notification request bit */ -+ sc->sc_chnfifo[chsel][i].cf_desc.hdr |= -+ TALITOS_DONE_NOTIFY; -+ break; -+ } -+ } -+ spin_unlock_irqrestore(&sc->sc_chnfifolock[chsel], flags); -+ -+ if (i == sc->sc_chfifo_len) { -+ /* fifo full */ -+ err = ERESTART; -+ goto errout; -+ } -+ -+ td = &sc->sc_chnfifo[chsel][i].cf_desc; -+ sc->sc_chnfifo[chsel][i].cf_crp = crp; -+ -+ crd1 = crp->crp_desc; -+ if (crd1 == NULL) { -+ err = EINVAL; -+ goto errout; -+ } -+ crd2 = crd1->crd_next; -+ /* prevent compiler warning */ -+ hmac_key = 0; -+ hmac_data = 0; -+ if (crd2 == NULL) { -+ td->hdr |= TD_TYPE_COMMON_NONSNOOP_NO_AFEU; -+ /* assign descriptor dword ptr mappings for this desc. type */ -+ cipher_iv = 1; -+ cipher_key = 2; -+ in_fifo = 3; -+ cipher_iv_out = 5; -+ if (crd1->crd_alg == CRYPTO_MD5_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1 || -+ crd1->crd_alg == CRYPTO_MD5) { -+ out_fifo = 5; -+ maccrd = crd1; -+ enccrd = NULL; -+ } else if (crd1->crd_alg == CRYPTO_DES_CBC || -+ crd1->crd_alg == CRYPTO_3DES_CBC || -+ crd1->crd_alg == CRYPTO_AES_CBC || -+ crd1->crd_alg == CRYPTO_ARC4) { -+ out_fifo = 4; -+ maccrd = NULL; -+ enccrd = crd1; -+ } else { -+ DPRINTF("UNKNOWN crd1->crd_alg %d\n", crd1->crd_alg); -+ err = EINVAL; -+ goto errout; -+ } -+ } else { -+ if (sc->sc_desc_types & TALITOS_HAS_DT_IPSEC_ESP) { -+ td->hdr |= TD_TYPE_IPSEC_ESP; -+ } else { -+ DPRINTF("unimplemented: multiple descriptor ipsec\n"); -+ err = EINVAL; -+ goto errout; -+ } -+ /* assign descriptor dword ptr mappings for this desc. type */ -+ hmac_key = 0; -+ hmac_data = 1; -+ cipher_iv = 2; -+ cipher_key = 3; -+ in_fifo = 4; -+ out_fifo = 5; -+ cipher_iv_out = 6; -+ if ((crd1->crd_alg == CRYPTO_MD5_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1_HMAC || -+ crd1->crd_alg == CRYPTO_MD5 || -+ crd1->crd_alg == CRYPTO_SHA1) && -+ (crd2->crd_alg == CRYPTO_DES_CBC || -+ crd2->crd_alg == CRYPTO_3DES_CBC || -+ crd2->crd_alg == CRYPTO_AES_CBC || -+ crd2->crd_alg == CRYPTO_ARC4) && -+ ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { -+ maccrd = crd1; -+ enccrd = crd2; -+ } else if ((crd1->crd_alg == CRYPTO_DES_CBC || -+ crd1->crd_alg == CRYPTO_ARC4 || -+ crd1->crd_alg == CRYPTO_3DES_CBC || -+ crd1->crd_alg == CRYPTO_AES_CBC) && -+ (crd2->crd_alg == CRYPTO_MD5_HMAC || -+ crd2->crd_alg == CRYPTO_SHA1_HMAC || -+ crd2->crd_alg == CRYPTO_MD5 || -+ crd2->crd_alg == CRYPTO_SHA1) && -+ (crd1->crd_flags & CRD_F_ENCRYPT)) { -+ enccrd = crd1; -+ maccrd = crd2; -+ } else { -+ /* We cannot order the SEC as requested */ -+ printk("%s: cannot do the order\n", -+ device_get_nameunit(sc->sc_cdev)); -+ err = EINVAL; -+ goto errout; -+ } -+ } -+ /* assign in_fifo and out_fifo based on input/output struct type */ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ /* using SKB buffers */ -+ struct sk_buff *skb = (struct sk_buff *)crp->crp_buf; -+ if (skb_shinfo(skb)->nr_frags) { -+ printk("%s: skb frags unimplemented\n", -+ device_get_nameunit(sc->sc_cdev)); -+ err = EINVAL; -+ goto errout; -+ } -+ td->ptr[in_fifo].ptr = dma_map_single(NULL, skb->data, -+ skb->len, DMA_TO_DEVICE); -+ td->ptr[in_fifo].len = skb->len; -+ td->ptr[out_fifo].ptr = dma_map_single(NULL, skb->data, -+ skb->len, DMA_TO_DEVICE); -+ td->ptr[out_fifo].len = skb->len; -+ td->ptr[hmac_data].ptr = dma_map_single(NULL, skb->data, -+ skb->len, DMA_TO_DEVICE); -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ /* using IOV buffers */ -+ struct uio *uiop = (struct uio *)crp->crp_buf; -+ if (uiop->uio_iovcnt > 1) { -+ printk("%s: iov frags unimplemented\n", -+ device_get_nameunit(sc->sc_cdev)); -+ err = EINVAL; -+ goto errout; -+ } -+ td->ptr[in_fifo].ptr = dma_map_single(NULL, -+ uiop->uio_iov->iov_base, crp->crp_ilen, DMA_TO_DEVICE); -+ td->ptr[in_fifo].len = crp->crp_ilen; -+ /* crp_olen is never set; always use crp_ilen */ -+ td->ptr[out_fifo].ptr = dma_map_single(NULL, -+ uiop->uio_iov->iov_base, -+ crp->crp_ilen, DMA_TO_DEVICE); -+ td->ptr[out_fifo].len = crp->crp_ilen; -+ } else { -+ /* using contig buffers */ -+ td->ptr[in_fifo].ptr = dma_map_single(NULL, -+ crp->crp_buf, crp->crp_ilen, DMA_TO_DEVICE); -+ td->ptr[in_fifo].len = crp->crp_ilen; -+ td->ptr[out_fifo].ptr = dma_map_single(NULL, -+ crp->crp_buf, crp->crp_ilen, DMA_TO_DEVICE); -+ td->ptr[out_fifo].len = crp->crp_ilen; -+ } -+ if (enccrd) { -+ switch (enccrd->crd_alg) { -+ case CRYPTO_3DES_CBC: -+ td->hdr |= TALITOS_MODE0_DEU_3DES; -+ /* FALLTHROUGH */ -+ case CRYPTO_DES_CBC: -+ td->hdr |= TALITOS_SEL0_DEU -+ | TALITOS_MODE0_DEU_CBC; -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) -+ td->hdr |= TALITOS_MODE0_DEU_ENC; -+ ivsize = 2*sizeof(u_int32_t); -+ DPRINTF("%cDES ses %d ch %d len %d\n", -+ (td->hdr & TALITOS_MODE0_DEU_3DES)?'3':'1', -+ (u32)TALITOS_SESSION(crp->crp_sid), -+ chsel, td->ptr[in_fifo].len); -+ break; -+ case CRYPTO_AES_CBC: -+ td->hdr |= TALITOS_SEL0_AESU -+ | TALITOS_MODE0_AESU_CBC; -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) -+ td->hdr |= TALITOS_MODE0_AESU_ENC; -+ ivsize = 4*sizeof(u_int32_t); -+ DPRINTF("AES ses %d ch %d len %d\n", -+ (u32)TALITOS_SESSION(crp->crp_sid), -+ chsel, td->ptr[in_fifo].len); -+ break; -+ default: -+ printk("%s: unimplemented enccrd->crd_alg %d\n", -+ device_get_nameunit(sc->sc_cdev), enccrd->crd_alg); -+ err = EINVAL; -+ goto errout; -+ } -+ /* -+ * Setup encrypt/decrypt state. When using basic ops -+ * we can't use an inline IV because hash/crypt offset -+ * must be from the end of the IV to the start of the -+ * crypt data and this leaves out the preceding header -+ * from the hash calculation. Instead we place the IV -+ * in the state record and set the hash/crypt offset to -+ * copy both the header+IV. -+ */ -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) { -+ td->hdr |= TALITOS_DIR_OUTBOUND; -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) -+ iv = enccrd->crd_iv; -+ else -+ iv = (caddr_t) ses->ses_iv; -+ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ enccrd->crd_inject, ivsize, iv); -+ } -+ } else { -+ td->hdr |= TALITOS_DIR_INBOUND; -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) { -+ iv = enccrd->crd_iv; -+ bcopy(enccrd->crd_iv, iv, ivsize); -+ } else { -+ iv = (caddr_t) ses->ses_iv; -+ crypto_copydata(crp->crp_flags, crp->crp_buf, -+ enccrd->crd_inject, ivsize, iv); -+ } -+ } -+ td->ptr[cipher_iv].ptr = dma_map_single(NULL, iv, ivsize, -+ DMA_TO_DEVICE); -+ td->ptr[cipher_iv].len = ivsize; -+ /* -+ * we don't need the cipher iv out length/pointer -+ * field to do ESP IPsec. Therefore we set the len field as 0, -+ * which tells the SEC not to do anything with this len/ptr -+ * field. Previously, when length/pointer as pointing to iv, -+ * it gave us corruption of packets. -+ */ -+ td->ptr[cipher_iv_out].len = 0; -+ } -+ if (enccrd && maccrd) { -+ /* this is ipsec only for now */ -+ td->hdr |= TALITOS_SEL1_MDEU -+ | TALITOS_MODE1_MDEU_INIT -+ | TALITOS_MODE1_MDEU_PAD; -+ switch (maccrd->crd_alg) { -+ case CRYPTO_MD5: -+ td->hdr |= TALITOS_MODE1_MDEU_MD5; -+ break; -+ case CRYPTO_MD5_HMAC: -+ td->hdr |= TALITOS_MODE1_MDEU_MD5_HMAC; -+ break; -+ case CRYPTO_SHA1: -+ td->hdr |= TALITOS_MODE1_MDEU_SHA1; -+ break; -+ case CRYPTO_SHA1_HMAC: -+ td->hdr |= TALITOS_MODE1_MDEU_SHA1_HMAC; -+ break; -+ default: -+ /* We cannot order the SEC as requested */ -+ printk("%s: cannot do the order\n", -+ device_get_nameunit(sc->sc_cdev)); -+ err = EINVAL; -+ goto errout; -+ } -+ if ((maccrd->crd_alg == CRYPTO_MD5_HMAC) || -+ (maccrd->crd_alg == CRYPTO_SHA1_HMAC)) { -+ /* -+ * The offset from hash data to the start of -+ * crypt data is the difference in the skips. -+ */ -+ /* ipsec only for now */ -+ td->ptr[hmac_key].ptr = dma_map_single(NULL, -+ ses->ses_hmac, ses->ses_hmac_len, DMA_TO_DEVICE); -+ td->ptr[hmac_key].len = ses->ses_hmac_len; -+ td->ptr[in_fifo].ptr += enccrd->crd_skip; -+ td->ptr[in_fifo].len = enccrd->crd_len; -+ td->ptr[out_fifo].ptr += enccrd->crd_skip; -+ td->ptr[out_fifo].len = enccrd->crd_len; -+ /* bytes of HMAC to postpend to ciphertext */ -+ td->ptr[out_fifo].extent = ses->ses_mlen; -+ td->ptr[hmac_data].ptr += maccrd->crd_skip; -+ td->ptr[hmac_data].len = enccrd->crd_skip - maccrd->crd_skip; -+ } -+ if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) { -+ printk("%s: CRD_F_KEY_EXPLICIT unimplemented\n", -+ device_get_nameunit(sc->sc_cdev)); -+ } -+ } -+ if (!enccrd && maccrd) { -+ /* single MD5 or SHA */ -+ td->hdr |= TALITOS_SEL0_MDEU -+ | TALITOS_MODE0_MDEU_INIT -+ | TALITOS_MODE0_MDEU_PAD; -+ switch (maccrd->crd_alg) { -+ case CRYPTO_MD5: -+ td->hdr |= TALITOS_MODE0_MDEU_MD5; -+ DPRINTF("MD5 ses %d ch %d len %d\n", -+ (u32)TALITOS_SESSION(crp->crp_sid), -+ chsel, td->ptr[in_fifo].len); -+ break; -+ case CRYPTO_MD5_HMAC: -+ td->hdr |= TALITOS_MODE0_MDEU_MD5_HMAC; -+ break; -+ case CRYPTO_SHA1: -+ td->hdr |= TALITOS_MODE0_MDEU_SHA1; -+ DPRINTF("SHA1 ses %d ch %d len %d\n", -+ (u32)TALITOS_SESSION(crp->crp_sid), -+ chsel, td->ptr[in_fifo].len); -+ break; -+ case CRYPTO_SHA1_HMAC: -+ td->hdr |= TALITOS_MODE0_MDEU_SHA1_HMAC; -+ break; -+ default: -+ /* We cannot order the SEC as requested */ -+ DPRINTF("cannot do the order\n"); -+ err = EINVAL; -+ goto errout; -+ } -+ -+ if (crp->crp_flags & CRYPTO_F_IOV) -+ td->ptr[out_fifo].ptr += maccrd->crd_inject; -+ -+ if ((maccrd->crd_alg == CRYPTO_MD5_HMAC) || -+ (maccrd->crd_alg == CRYPTO_SHA1_HMAC)) { -+ td->ptr[hmac_key].ptr = dma_map_single(NULL, -+ ses->ses_hmac, ses->ses_hmac_len, -+ DMA_TO_DEVICE); -+ td->ptr[hmac_key].len = ses->ses_hmac_len; -+ } -+ } -+ else { -+ /* using process key (session data has duplicate) */ -+ td->ptr[cipher_key].ptr = dma_map_single(NULL, -+ enccrd->crd_key, (enccrd->crd_klen + 7) / 8, -+ DMA_TO_DEVICE); -+ td->ptr[cipher_key].len = (enccrd->crd_klen + 7) / 8; -+ } -+ /* descriptor complete - GO! */ -+ return talitos_submit(sc, td, chsel); -+ -+errout: -+ if (err != ERESTART) { -+ crp->crp_etype = err; -+ crypto_done(crp); -+ } -+ return err; -+} -+ -+/* go through all channels descriptors, notifying OCF what has -+ * _and_hasn't_ successfully completed and reset the device -+ * (otherwise it's up to decoding desc hdrs!) -+ */ -+static void talitos_errorprocessing(struct talitos_softc *sc) -+{ -+ unsigned long flags; -+ int i, j; -+ -+ /* disable further scheduling until under control */ -+ spin_lock_irqsave(&sc->sc_chnfifolock[sc->sc_num_channels], flags); -+ -+ if (debug) dump_talitos_status(sc); -+ /* go through descriptors, try and salvage those successfully done, -+ * and EIO those that weren't -+ */ -+ for (i = 0; i < sc->sc_num_channels; i++) { -+ spin_lock_irqsave(&sc->sc_chnfifolock[i], flags); -+ for (j = 0; j < sc->sc_chfifo_len; j++) { -+ if (sc->sc_chnfifo[i][j].cf_desc.hdr) { -+ if ((sc->sc_chnfifo[i][j].cf_desc.hdr -+ & TALITOS_HDR_DONE_BITS) -+ != TALITOS_HDR_DONE_BITS) { -+ /* this one didn't finish */ -+ /* signify in crp->etype */ -+ sc->sc_chnfifo[i][j].cf_crp->crp_etype -+ = EIO; -+ } -+ } else -+ continue; /* free entry */ -+ /* either way, notify ocf */ -+ crypto_done(sc->sc_chnfifo[i][j].cf_crp); -+ /* and tag it available again -+ * -+ * memset to ensure correct descriptor formation by -+ * avoiding inadvertently setting "optional" entries -+ * e.g. not using "optional" dptr2 MD/HMAC processing -+ */ -+ memset(&sc->sc_chnfifo[i][j].cf_desc, -+ 0, sizeof(struct talitos_desc)); -+ } -+ spin_unlock_irqrestore(&sc->sc_chnfifolock[i], flags); -+ } -+ /* reset and initialize the SEC h/w device */ -+ talitos_reset_device(sc); -+ talitos_init_device(sc); -+#ifdef CONFIG_OCF_RANDOMHARVEST -+ if (sc->sc_exec_units & TALITOS_HAS_EU_RNG) -+ talitos_rng_init(sc); -+#endif -+ -+ /* Okay. Stand by. */ -+ spin_unlock_irqrestore(&sc->sc_chnfifolock[sc->sc_num_channels], flags); -+ -+ return; -+} -+ -+/* go through all channels descriptors, notifying OCF what's been done */ -+static void talitos_doneprocessing(struct talitos_softc *sc) -+{ -+ unsigned long flags; -+ int i, j; -+ -+ /* go through descriptors looking for done bits */ -+ for (i = 0; i < sc->sc_num_channels; i++) { -+ spin_lock_irqsave(&sc->sc_chnfifolock[i], flags); -+ for (j = 0; j < sc->sc_chfifo_len; j++) { -+ /* descriptor has done bits set? */ -+ if ((sc->sc_chnfifo[i][j].cf_desc.hdr -+ & TALITOS_HDR_DONE_BITS) -+ == TALITOS_HDR_DONE_BITS) { -+ /* notify ocf */ -+ crypto_done(sc->sc_chnfifo[i][j].cf_crp); -+ /* and tag it available again -+ * -+ * memset to ensure correct descriptor formation by -+ * avoiding inadvertently setting "optional" entries -+ * e.g. not using "optional" dptr2 MD/HMAC processing -+ */ -+ memset(&sc->sc_chnfifo[i][j].cf_desc, -+ 0, sizeof(struct talitos_desc)); -+ } -+ } -+ spin_unlock_irqrestore(&sc->sc_chnfifolock[i], flags); -+ } -+ return; -+} -+ -+static irqreturn_t -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) -+talitos_intr(int irq, void *arg) -+#else -+talitos_intr(int irq, void *arg, struct pt_regs *regs) -+#endif -+{ -+ struct talitos_softc *sc = arg; -+ u_int32_t v, v_hi; -+ -+ /* ack */ -+ v = talitos_read(sc->sc_base_addr + TALITOS_ISR); -+ v_hi = talitos_read(sc->sc_base_addr + TALITOS_ISR_HI); -+ talitos_write(sc->sc_base_addr + TALITOS_ICR, v); -+ talitos_write(sc->sc_base_addr + TALITOS_ICR_HI, v_hi); -+ -+ if (unlikely(v & TALITOS_ISR_ERROR)) { -+ /* Okay, Houston, we've had a problem here. */ -+ printk(KERN_DEBUG "%s: got error interrupt - ISR 0x%08x_%08x\n", -+ device_get_nameunit(sc->sc_cdev), v, v_hi); -+ talitos_errorprocessing(sc); -+ } else -+ if (likely(v & TALITOS_ISR_DONE)) { -+ talitos_doneprocessing(sc); -+ } -+ return IRQ_HANDLED; -+} -+ -+/* -+ * Initialize registers we need to touch only once. -+ */ -+static void -+talitos_init_device(struct talitos_softc *sc) -+{ -+ u_int32_t v; -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ /* init all channels */ -+ for (i = 0; i < sc->sc_num_channels; i++) { -+ v = talitos_read(sc->sc_base_addr + -+ i*TALITOS_CH_OFFSET + TALITOS_CH_CCCR_HI); -+ v |= TALITOS_CH_CCCR_HI_CDWE -+ | TALITOS_CH_CCCR_HI_CDIE; /* invoke interrupt if done */ -+ talitos_write(sc->sc_base_addr + -+ i*TALITOS_CH_OFFSET + TALITOS_CH_CCCR_HI, v); -+ } -+ /* enable all interrupts */ -+ v = talitos_read(sc->sc_base_addr + TALITOS_IMR); -+ v |= TALITOS_IMR_ALL; -+ talitos_write(sc->sc_base_addr + TALITOS_IMR, v); -+ v = talitos_read(sc->sc_base_addr + TALITOS_IMR_HI); -+ v |= TALITOS_IMR_HI_ERRONLY; -+ talitos_write(sc->sc_base_addr + TALITOS_IMR_HI, v); -+ return; -+} -+ -+/* -+ * set the master reset bit on the device. -+ */ -+static void -+talitos_reset_device_master(struct talitos_softc *sc) -+{ -+ u_int32_t v; -+ -+ /* Reset the device by writing 1 to MCR:SWR and waiting 'til cleared */ -+ v = talitos_read(sc->sc_base_addr + TALITOS_MCR); -+ talitos_write(sc->sc_base_addr + TALITOS_MCR, v | TALITOS_MCR_SWR); -+ -+ while (talitos_read(sc->sc_base_addr + TALITOS_MCR) & TALITOS_MCR_SWR) -+ cpu_relax(); -+ -+ return; -+} -+ -+/* -+ * Resets the device. Values in the registers are left as is -+ * from the reset (i.e. initial values are assigned elsewhere). -+ */ -+static void -+talitos_reset_device(struct talitos_softc *sc) -+{ -+ u_int32_t v; -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ /* -+ * Master reset -+ * errata documentation: warning: certain SEC interrupts -+ * are not fully cleared by writing the MCR:SWR bit, -+ * set bit twice to completely reset -+ */ -+ talitos_reset_device_master(sc); /* once */ -+ talitos_reset_device_master(sc); /* and once again */ -+ -+ /* reset all channels */ -+ for (i = 0; i < sc->sc_num_channels; i++) { -+ v = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + -+ TALITOS_CH_CCCR); -+ talitos_write(sc->sc_base_addr + i*TALITOS_CH_OFFSET + -+ TALITOS_CH_CCCR, v | TALITOS_CH_CCCR_RESET); -+ } -+} -+ -+/* Set up the crypto device structure, private data, -+ * and anything else we need before we start */ -+#ifdef CONFIG_PPC_MERGE -+static int talitos_probe(struct of_device *ofdev, const struct of_device_id *match) -+#else -+static int talitos_probe(struct platform_device *pdev) -+#endif -+{ -+ struct talitos_softc *sc = NULL; -+ struct resource *r; -+#ifdef CONFIG_PPC_MERGE -+ struct device *device = &ofdev->dev; -+ struct device_node *np = ofdev->node; -+ const unsigned int *prop; -+ int err; -+ struct resource res; -+#endif -+ static int num_chips = 0; -+ int rc; -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ sc = (struct talitos_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); -+ if (!sc) -+ return -ENOMEM; -+ memset(sc, 0, sizeof(*sc)); -+ -+ softc_device_init(sc, DRV_NAME, num_chips, talitos_methods); -+ -+ sc->sc_irq = -1; -+ sc->sc_cid = -1; -+#ifndef CONFIG_PPC_MERGE -+ sc->sc_dev = pdev; -+#endif -+ sc->sc_num = num_chips++; -+ -+#ifdef CONFIG_PPC_MERGE -+ dev_set_drvdata(device, sc); -+#else -+ platform_set_drvdata(sc->sc_dev, sc); -+#endif -+ -+ /* get the irq line */ -+#ifdef CONFIG_PPC_MERGE -+ err = of_address_to_resource(np, 0, &res); -+ if (err) -+ return -EINVAL; -+ r = &res; -+ -+ sc->sc_irq = irq_of_parse_and_map(np, 0); -+#else -+ /* get a pointer to the register memory */ -+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ -+ sc->sc_irq = platform_get_irq(pdev, 0); -+#endif -+ rc = request_irq(sc->sc_irq, talitos_intr, 0, -+ device_get_nameunit(sc->sc_cdev), sc); -+ if (rc) { -+ printk(KERN_ERR "%s: failed to hook irq %d\n", -+ device_get_nameunit(sc->sc_cdev), sc->sc_irq); -+ sc->sc_irq = -1; -+ goto out; -+ } -+ -+ sc->sc_base_addr = (ocf_iomem_t) ioremap(r->start, (r->end - r->start)); -+ if (!sc->sc_base_addr) { -+ printk(KERN_ERR "%s: failed to ioremap\n", -+ device_get_nameunit(sc->sc_cdev)); -+ goto out; -+ } -+ -+ /* figure out our SEC's properties and capabilities */ -+ sc->sc_chiprev = (u64)talitos_read(sc->sc_base_addr + TALITOS_ID) << 32 -+ | talitos_read(sc->sc_base_addr + TALITOS_ID_HI); -+ DPRINTF("sec id 0x%llx\n", sc->sc_chiprev); -+ -+#ifdef CONFIG_PPC_MERGE -+ /* get SEC properties from device tree, defaulting to SEC 2.0 */ -+ -+ prop = of_get_property(np, "num-channels", NULL); -+ sc->sc_num_channels = prop ? *prop : TALITOS_NCHANNELS_SEC_2_0; -+ -+ prop = of_get_property(np, "channel-fifo-len", NULL); -+ sc->sc_chfifo_len = prop ? *prop : TALITOS_CHFIFOLEN_SEC_2_0; -+ -+ prop = of_get_property(np, "exec-units-mask", NULL); -+ sc->sc_exec_units = prop ? *prop : TALITOS_HAS_EUS_SEC_2_0; -+ -+ prop = of_get_property(np, "descriptor-types-mask", NULL); -+ sc->sc_desc_types = prop ? *prop : TALITOS_HAS_DESCTYPES_SEC_2_0; -+#else -+ /* bulk should go away with openfirmware flat device tree support */ -+ if (sc->sc_chiprev & TALITOS_ID_SEC_2_0) { -+ sc->sc_num_channels = TALITOS_NCHANNELS_SEC_2_0; -+ sc->sc_chfifo_len = TALITOS_CHFIFOLEN_SEC_2_0; -+ sc->sc_exec_units = TALITOS_HAS_EUS_SEC_2_0; -+ sc->sc_desc_types = TALITOS_HAS_DESCTYPES_SEC_2_0; -+ } else { -+ printk(KERN_ERR "%s: failed to id device\n", -+ device_get_nameunit(sc->sc_cdev)); -+ goto out; -+ } -+#endif -+ -+ /* + 1 is for the meta-channel lock used by the channel scheduler */ -+ sc->sc_chnfifolock = (spinlock_t *) kmalloc( -+ (sc->sc_num_channels + 1) * sizeof(spinlock_t), GFP_KERNEL); -+ if (!sc->sc_chnfifolock) -+ goto out; -+ for (i = 0; i < sc->sc_num_channels + 1; i++) { -+ spin_lock_init(&sc->sc_chnfifolock[i]); -+ } -+ -+ sc->sc_chnlastalg = (int *) kmalloc( -+ sc->sc_num_channels * sizeof(int), GFP_KERNEL); -+ if (!sc->sc_chnlastalg) -+ goto out; -+ memset(sc->sc_chnlastalg, 0, sc->sc_num_channels * sizeof(int)); -+ -+ sc->sc_chnfifo = (struct desc_cryptop_pair **) kmalloc( -+ sc->sc_num_channels * sizeof(struct desc_cryptop_pair *), -+ GFP_KERNEL); -+ if (!sc->sc_chnfifo) -+ goto out; -+ for (i = 0; i < sc->sc_num_channels; i++) { -+ sc->sc_chnfifo[i] = (struct desc_cryptop_pair *) kmalloc( -+ sc->sc_chfifo_len * sizeof(struct desc_cryptop_pair), -+ GFP_KERNEL); -+ if (!sc->sc_chnfifo[i]) -+ goto out; -+ memset(sc->sc_chnfifo[i], 0, -+ sc->sc_chfifo_len * sizeof(struct desc_cryptop_pair)); -+ } -+ -+ /* reset and initialize the SEC h/w device */ -+ talitos_reset_device(sc); -+ talitos_init_device(sc); -+ -+ sc->sc_cid = crypto_get_driverid(softc_get_device(sc),CRYPTOCAP_F_HARDWARE); -+ if (sc->sc_cid < 0) { -+ printk(KERN_ERR "%s: could not get crypto driver id\n", -+ device_get_nameunit(sc->sc_cdev)); -+ goto out; -+ } -+ -+ /* register algorithms with the framework */ -+ printk("%s:", device_get_nameunit(sc->sc_cdev)); -+ -+ if (sc->sc_exec_units & TALITOS_HAS_EU_RNG) { -+ printk(" rng"); -+#ifdef CONFIG_OCF_RANDOMHARVEST -+ talitos_rng_init(sc); -+ crypto_rregister(sc->sc_cid, talitos_read_random, sc); -+#endif -+ } -+ if (sc->sc_exec_units & TALITOS_HAS_EU_DEU) { -+ printk(" des/3des"); -+ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); -+ } -+ if (sc->sc_exec_units & TALITOS_HAS_EU_AESU) { -+ printk(" aes"); -+ crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); -+ } -+ if (sc->sc_exec_units & TALITOS_HAS_EU_MDEU) { -+ printk(" md5"); -+ crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0); -+ /* HMAC support only with IPsec for now */ -+ crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); -+ printk(" sha1"); -+ crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0); -+ /* HMAC support only with IPsec for now */ -+ crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); -+ } -+ printk("\n"); -+ return 0; -+ -+out: -+#ifndef CONFIG_PPC_MERGE -+ talitos_remove(pdev); -+#endif -+ return -ENOMEM; -+} -+ -+#ifdef CONFIG_PPC_MERGE -+static int talitos_remove(struct of_device *ofdev) -+#else -+static int talitos_remove(struct platform_device *pdev) -+#endif -+{ -+#ifdef CONFIG_PPC_MERGE -+ struct talitos_softc *sc = dev_get_drvdata(&ofdev->dev); -+#else -+ struct talitos_softc *sc = platform_get_drvdata(pdev); -+#endif -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ if (sc->sc_cid >= 0) -+ crypto_unregister_all(sc->sc_cid); -+ if (sc->sc_chnfifo) { -+ for (i = 0; i < sc->sc_num_channels; i++) -+ if (sc->sc_chnfifo[i]) -+ kfree(sc->sc_chnfifo[i]); -+ kfree(sc->sc_chnfifo); -+ } -+ if (sc->sc_chnlastalg) -+ kfree(sc->sc_chnlastalg); -+ if (sc->sc_chnfifolock) -+ kfree(sc->sc_chnfifolock); -+ if (sc->sc_irq != -1) -+ free_irq(sc->sc_irq, sc); -+ if (sc->sc_base_addr) -+ iounmap((void *) sc->sc_base_addr); -+ kfree(sc); -+ return 0; -+} -+ -+#ifdef CONFIG_PPC_MERGE -+static struct of_device_id talitos_match[] = { -+ { -+ .type = "crypto", -+ .compatible = "talitos", -+ }, -+ {}, -+}; -+ -+MODULE_DEVICE_TABLE(of, talitos_match); -+ -+static struct of_platform_driver talitos_driver = { -+ .name = DRV_NAME, -+ .match_table = talitos_match, -+ .probe = talitos_probe, -+ .remove = talitos_remove, -+}; -+ -+static int __init talitos_init(void) -+{ -+ return of_register_platform_driver(&talitos_driver); -+} -+ -+static void __exit talitos_exit(void) -+{ -+ of_unregister_platform_driver(&talitos_driver); -+} -+#else -+/* Structure for a platform device driver */ -+static struct platform_driver talitos_driver = { -+ .probe = talitos_probe, -+ .remove = talitos_remove, -+ .driver = { -+ .name = "fsl-sec2", -+ } -+}; -+ -+static int __init talitos_init(void) -+{ -+ return platform_driver_register(&talitos_driver); -+} -+ -+static void __exit talitos_exit(void) -+{ -+ platform_driver_unregister(&talitos_driver); -+} -+#endif -+ -+module_init(talitos_init); -+module_exit(talitos_exit); -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_AUTHOR("kim.phillips@freescale.com"); -+MODULE_DESCRIPTION("OCF driver for Freescale SEC (talitos)"); -diff -Nur linux-2.6.39.orig/crypto/ocf/talitos/talitos_dev.h linux-2.6.39/crypto/ocf/talitos/talitos_dev.h ---- linux-2.6.39.orig/crypto/ocf/talitos/talitos_dev.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/talitos/talitos_dev.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,277 @@ -+/* -+ * Freescale SEC (talitos) device dependent data structures -+ * -+ * Copyright (c) 2006 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ */ -+ -+/* device ID register values */ -+#define TALITOS_ID_SEC_2_0 0x40 -+#define TALITOS_ID_SEC_2_1 0x40 /* cross ref with IP block revision reg */ -+ -+/* -+ * following num_channels, channel-fifo-depth, exec-unit-mask, and -+ * descriptor-types-mask are for forward-compatibility with openfirmware -+ * flat device trees -+ */ -+ -+/* -+ * num_channels : the number of channels available in each SEC version. -+ */ -+ -+/* n.b. this driver requires these values be a power of 2 */ -+#define TALITOS_NCHANNELS_SEC_1_0 4 -+#define TALITOS_NCHANNELS_SEC_1_2 1 -+#define TALITOS_NCHANNELS_SEC_2_0 4 -+#define TALITOS_NCHANNELS_SEC_2_01 4 -+#define TALITOS_NCHANNELS_SEC_2_1 4 -+#define TALITOS_NCHANNELS_SEC_2_4 4 -+ -+/* -+ * channel-fifo-depth : The number of descriptor -+ * pointers a channel fetch fifo can hold. -+ */ -+#define TALITOS_CHFIFOLEN_SEC_1_0 1 -+#define TALITOS_CHFIFOLEN_SEC_1_2 1 -+#define TALITOS_CHFIFOLEN_SEC_2_0 24 -+#define TALITOS_CHFIFOLEN_SEC_2_01 24 -+#define TALITOS_CHFIFOLEN_SEC_2_1 24 -+#define TALITOS_CHFIFOLEN_SEC_2_4 24 -+ -+/* -+ * exec-unit-mask : The bitmask representing what Execution Units (EUs) -+ * are available. EU information should be encoded following the SEC's -+ * EU_SEL0 bitfield documentation, i.e. as follows: -+ * -+ * bit 31 = set if SEC permits no-EU selection (should be always set) -+ * bit 30 = set if SEC has the ARC4 EU (AFEU) -+ * bit 29 = set if SEC has the des/3des EU (DEU) -+ * bit 28 = set if SEC has the message digest EU (MDEU) -+ * bit 27 = set if SEC has the random number generator EU (RNG) -+ * bit 26 = set if SEC has the public key EU (PKEU) -+ * bit 25 = set if SEC has the aes EU (AESU) -+ * bit 24 = set if SEC has the Kasumi EU (KEU) -+ * -+ */ -+#define TALITOS_HAS_EU_NONE (1<<0) -+#define TALITOS_HAS_EU_AFEU (1<<1) -+#define TALITOS_HAS_EU_DEU (1<<2) -+#define TALITOS_HAS_EU_MDEU (1<<3) -+#define TALITOS_HAS_EU_RNG (1<<4) -+#define TALITOS_HAS_EU_PKEU (1<<5) -+#define TALITOS_HAS_EU_AESU (1<<6) -+#define TALITOS_HAS_EU_KEU (1<<7) -+ -+/* the corresponding masks for each SEC version */ -+#define TALITOS_HAS_EUS_SEC_1_0 0x7f -+#define TALITOS_HAS_EUS_SEC_1_2 0x4d -+#define TALITOS_HAS_EUS_SEC_2_0 0x7f -+#define TALITOS_HAS_EUS_SEC_2_01 0x7f -+#define TALITOS_HAS_EUS_SEC_2_1 0xff -+#define TALITOS_HAS_EUS_SEC_2_4 0x7f -+ -+/* -+ * descriptor-types-mask : The bitmask representing what descriptors -+ * are available. Descriptor type information should be encoded -+ * following the SEC's Descriptor Header Dword DESC_TYPE field -+ * documentation, i.e. as follows: -+ * -+ * bit 0 = set if SEC supports the aesu_ctr_nonsnoop desc. type -+ * bit 1 = set if SEC supports the ipsec_esp descriptor type -+ * bit 2 = set if SEC supports the common_nonsnoop desc. type -+ * bit 3 = set if SEC supports the 802.11i AES ccmp desc. type -+ * bit 4 = set if SEC supports the hmac_snoop_no_afeu desc. type -+ * bit 5 = set if SEC supports the srtp descriptor type -+ * bit 6 = set if SEC supports the non_hmac_snoop_no_afeu desc.type -+ * bit 7 = set if SEC supports the pkeu_assemble descriptor type -+ * bit 8 = set if SEC supports the aesu_key_expand_output desc.type -+ * bit 9 = set if SEC supports the pkeu_ptmul descriptor type -+ * bit 10 = set if SEC supports the common_nonsnoop_afeu desc. type -+ * bit 11 = set if SEC supports the pkeu_ptadd_dbl descriptor type -+ * -+ * ..and so on and so forth. -+ */ -+#define TALITOS_HAS_DT_AESU_CTR_NONSNOOP (1<<0) -+#define TALITOS_HAS_DT_IPSEC_ESP (1<<1) -+#define TALITOS_HAS_DT_COMMON_NONSNOOP (1<<2) -+ -+/* the corresponding masks for each SEC version */ -+#define TALITOS_HAS_DESCTYPES_SEC_2_0 0x01010ebf -+#define TALITOS_HAS_DESCTYPES_SEC_2_1 0x012b0ebf -+ -+/* -+ * a TALITOS_xxx_HI address points to the low data bits (32-63) of the register -+ */ -+ -+/* global register offset addresses */ -+#define TALITOS_ID 0x1020 -+#define TALITOS_ID_HI 0x1024 -+#define TALITOS_MCR 0x1030 /* master control register */ -+#define TALITOS_MCR_HI 0x1038 /* master control register */ -+#define TALITOS_MCR_SWR 0x1 -+#define TALITOS_IMR 0x1008 /* interrupt mask register */ -+#define TALITOS_IMR_ALL 0x00010fff /* enable all interrupts mask */ -+#define TALITOS_IMR_ERRONLY 0x00010aaa /* enable error interrupts */ -+#define TALITOS_IMR_HI 0x100C /* interrupt mask register */ -+#define TALITOS_IMR_HI_ALL 0x00323333 /* enable all interrupts mask */ -+#define TALITOS_IMR_HI_ERRONLY 0x00222222 /* enable error interrupts */ -+#define TALITOS_ISR 0x1010 /* interrupt status register */ -+#define TALITOS_ISR_ERROR 0x00010faa /* errors mask */ -+#define TALITOS_ISR_DONE 0x00000055 /* channel(s) done mask */ -+#define TALITOS_ISR_HI 0x1014 /* interrupt status register */ -+#define TALITOS_ICR 0x1018 /* interrupt clear register */ -+#define TALITOS_ICR_HI 0x101C /* interrupt clear register */ -+ -+/* channel register address stride */ -+#define TALITOS_CH_OFFSET 0x100 -+ -+/* channel register offset addresses and bits */ -+#define TALITOS_CH_CCCR 0x1108 /* Crypto-Channel Config Register */ -+#define TALITOS_CH_CCCR_RESET 0x1 /* Channel Reset bit */ -+#define TALITOS_CH_CCCR_HI 0x110c /* Crypto-Channel Config Register */ -+#define TALITOS_CH_CCCR_HI_CDWE 0x10 /* Channel done writeback enable bit */ -+#define TALITOS_CH_CCCR_HI_NT 0x4 /* Notification type bit */ -+#define TALITOS_CH_CCCR_HI_CDIE 0x2 /* Channel Done Interrupt Enable bit */ -+#define TALITOS_CH_CCPSR 0x1110 /* Crypto-Channel Pointer Status Reg */ -+#define TALITOS_CH_CCPSR_HI 0x1114 /* Crypto-Channel Pointer Status Reg */ -+#define TALITOS_CH_FF 0x1148 /* Fetch FIFO */ -+#define TALITOS_CH_FF_HI 0x114c /* Fetch FIFO's FETCH_ADRS */ -+#define TALITOS_CH_CDPR 0x1140 /* Crypto-Channel Pointer Status Reg */ -+#define TALITOS_CH_CDPR_HI 0x1144 /* Crypto-Channel Pointer Status Reg */ -+#define TALITOS_CH_DESCBUF 0x1180 /* (thru 11bf) Crypto-Channel -+ * Descriptor Buffer (debug) */ -+ -+/* execution unit register offset addresses and bits */ -+#define TALITOS_DEUSR 0x2028 /* DEU status register */ -+#define TALITOS_DEUSR_HI 0x202c /* DEU status register */ -+#define TALITOS_DEUISR 0x2030 /* DEU interrupt status register */ -+#define TALITOS_DEUISR_HI 0x2034 /* DEU interrupt status register */ -+#define TALITOS_DEUICR 0x2038 /* DEU interrupt control register */ -+#define TALITOS_DEUICR_HI 0x203c /* DEU interrupt control register */ -+#define TALITOS_AESUISR 0x4030 /* AESU interrupt status register */ -+#define TALITOS_AESUISR_HI 0x4034 /* AESU interrupt status register */ -+#define TALITOS_AESUICR 0x4038 /* AESU interrupt control register */ -+#define TALITOS_AESUICR_HI 0x403c /* AESU interrupt control register */ -+#define TALITOS_MDEUISR 0x6030 /* MDEU interrupt status register */ -+#define TALITOS_MDEUISR_HI 0x6034 /* MDEU interrupt status register */ -+#define TALITOS_RNGSR 0xa028 /* RNG status register */ -+#define TALITOS_RNGSR_HI 0xa02c /* RNG status register */ -+#define TALITOS_RNGSR_HI_RD 0x1 /* RNG Reset done */ -+#define TALITOS_RNGSR_HI_OFL 0xff0000/* number of dwords in RNG output FIFO*/ -+#define TALITOS_RNGDSR 0xa010 /* RNG data size register */ -+#define TALITOS_RNGDSR_HI 0xa014 /* RNG data size register */ -+#define TALITOS_RNG_FIFO 0xa800 /* RNG FIFO - pool of random numbers */ -+#define TALITOS_RNGISR 0xa030 /* RNG Interrupt status register */ -+#define TALITOS_RNGISR_HI 0xa034 /* RNG Interrupt status register */ -+#define TALITOS_RNGRCR 0xa018 /* RNG Reset control register */ -+#define TALITOS_RNGRCR_HI 0xa01c /* RNG Reset control register */ -+#define TALITOS_RNGRCR_HI_SR 0x1 /* RNG RNGRCR:Software Reset */ -+ -+/* descriptor pointer entry */ -+struct talitos_desc_ptr { -+ u16 len; /* length */ -+ u8 extent; /* jump (to s/g link table) and extent */ -+ u8 res; /* reserved */ -+ u32 ptr; /* pointer */ -+}; -+ -+/* descriptor */ -+struct talitos_desc { -+ u32 hdr; /* header */ -+ u32 res; /* reserved */ -+ struct talitos_desc_ptr ptr[7]; /* ptr/len pair array */ -+}; -+ -+/* talitos descriptor header (hdr) bits */ -+ -+/* primary execution unit select */ -+#define TALITOS_SEL0_AFEU 0x10000000 -+#define TALITOS_SEL0_DEU 0x20000000 -+#define TALITOS_SEL0_MDEU 0x30000000 -+#define TALITOS_SEL0_RNG 0x40000000 -+#define TALITOS_SEL0_PKEU 0x50000000 -+#define TALITOS_SEL0_AESU 0x60000000 -+ -+/* primary execution unit mode (MODE0) and derivatives */ -+#define TALITOS_MODE0_AESU_CBC 0x00200000 -+#define TALITOS_MODE0_AESU_ENC 0x00100000 -+#define TALITOS_MODE0_DEU_CBC 0x00400000 -+#define TALITOS_MODE0_DEU_3DES 0x00200000 -+#define TALITOS_MODE0_DEU_ENC 0x00100000 -+#define TALITOS_MODE0_MDEU_INIT 0x01000000 /* init starting regs */ -+#define TALITOS_MODE0_MDEU_HMAC 0x00800000 -+#define TALITOS_MODE0_MDEU_PAD 0x00400000 /* PD */ -+#define TALITOS_MODE0_MDEU_MD5 0x00200000 -+#define TALITOS_MODE0_MDEU_SHA256 0x00100000 -+#define TALITOS_MODE0_MDEU_SHA1 0x00000000 /* SHA-160 */ -+#define TALITOS_MODE0_MDEU_MD5_HMAC \ -+ (TALITOS_MODE0_MDEU_MD5 | TALITOS_MODE0_MDEU_HMAC) -+#define TALITOS_MODE0_MDEU_SHA256_HMAC \ -+ (TALITOS_MODE0_MDEU_SHA256 | TALITOS_MODE0_MDEU_HMAC) -+#define TALITOS_MODE0_MDEU_SHA1_HMAC \ -+ (TALITOS_MODE0_MDEU_SHA1 | TALITOS_MODE0_MDEU_HMAC) -+ -+/* secondary execution unit select (SEL1) */ -+/* it's MDEU or nothing */ -+#define TALITOS_SEL1_MDEU 0x00030000 -+ -+/* secondary execution unit mode (MODE1) and derivatives */ -+#define TALITOS_MODE1_MDEU_INIT 0x00001000 /* init starting regs */ -+#define TALITOS_MODE1_MDEU_HMAC 0x00000800 -+#define TALITOS_MODE1_MDEU_PAD 0x00000400 /* PD */ -+#define TALITOS_MODE1_MDEU_MD5 0x00000200 -+#define TALITOS_MODE1_MDEU_SHA256 0x00000100 -+#define TALITOS_MODE1_MDEU_SHA1 0x00000000 /* SHA-160 */ -+#define TALITOS_MODE1_MDEU_MD5_HMAC \ -+ (TALITOS_MODE1_MDEU_MD5 | TALITOS_MODE1_MDEU_HMAC) -+#define TALITOS_MODE1_MDEU_SHA256_HMAC \ -+ (TALITOS_MODE1_MDEU_SHA256 | TALITOS_MODE1_MDEU_HMAC) -+#define TALITOS_MODE1_MDEU_SHA1_HMAC \ -+ (TALITOS_MODE1_MDEU_SHA1 | TALITOS_MODE1_MDEU_HMAC) -+ -+/* direction of overall data flow (DIR) */ -+#define TALITOS_DIR_OUTBOUND 0x00000000 -+#define TALITOS_DIR_INBOUND 0x00000002 -+ -+/* done notification (DN) */ -+#define TALITOS_DONE_NOTIFY 0x00000001 -+ -+/* descriptor types */ -+/* odd numbers here are valid on SEC2 and greater only (e.g. ipsec_esp) */ -+#define TD_TYPE_AESU_CTR_NONSNOOP (0 << 3) -+#define TD_TYPE_IPSEC_ESP (1 << 3) -+#define TD_TYPE_COMMON_NONSNOOP_NO_AFEU (2 << 3) -+#define TD_TYPE_HMAC_SNOOP_NO_AFEU (4 << 3) -+ -+#define TALITOS_HDR_DONE_BITS 0xff000000 -+ -+#define DPRINTF(a...) do { \ -+ if (debug) { \ -+ printk("%s: ", sc ? \ -+ device_get_nameunit(sc->sc_cdev) : "talitos"); \ -+ printk(a); \ -+ } \ -+ } while (0) -diff -Nur linux-2.6.39.orig/crypto/ocf/talitos/talitos_soft.h linux-2.6.39/crypto/ocf/talitos/talitos_soft.h ---- linux-2.6.39.orig/crypto/ocf/talitos/talitos_soft.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/talitos/talitos_soft.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,77 @@ -+/* -+ * Freescale SEC data structures for integration with ocf-linux -+ * -+ * Copyright (c) 2006 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/* -+ * paired descriptor and associated crypto operation -+ */ -+struct desc_cryptop_pair { -+ struct talitos_desc cf_desc; /* descriptor ptr */ -+ struct cryptop *cf_crp; /* cryptop ptr */ -+}; -+ -+/* -+ * Holds data specific to a single talitos device. -+ */ -+struct talitos_softc { -+ softc_device_decl sc_cdev; -+ struct platform_device *sc_dev; /* device backpointer */ -+ ocf_iomem_t sc_base_addr; -+ int sc_irq; -+ int sc_num; /* if we have multiple chips */ -+ int32_t sc_cid; /* crypto tag */ -+ u64 sc_chiprev; /* major/minor chip revision */ -+ int sc_nsessions; -+ struct talitos_session *sc_sessions; -+ int sc_num_channels;/* number of crypto channels */ -+ int sc_chfifo_len; /* channel fetch fifo len */ -+ int sc_exec_units; /* execution units mask */ -+ int sc_desc_types; /* descriptor types mask */ -+ /* -+ * mutual exclusion for intra-channel resources, e.g. fetch fifos -+ * the last entry is a meta-channel lock used by the channel scheduler -+ */ -+ spinlock_t *sc_chnfifolock; -+ /* sc_chnlastalgo contains last algorithm for that channel */ -+ int *sc_chnlastalg; -+ /* sc_chnfifo holds pending descriptor--crypto operation pairs */ -+ struct desc_cryptop_pair **sc_chnfifo; -+}; -+ -+struct talitos_session { -+ u_int32_t ses_used; -+ u_int32_t ses_klen; /* key length in bits */ -+ u_int32_t ses_key[8]; /* DES/3DES/AES key */ -+ u_int32_t ses_hmac[5]; /* hmac inner state */ -+ u_int32_t ses_hmac_len; /* hmac length */ -+ u_int32_t ses_iv[4]; /* DES/3DES/AES iv */ -+ u_int32_t ses_mlen; /* desired hash result len (12=ipsec or 16) */ -+}; -+ -+#define TALITOS_SESSION(sid) ((sid) & 0x0fffffff) -+#define TALITOS_SID(crd, sesn) (((crd) << 28) | ((sesn) & 0x0fffffff)) -diff -Nur linux-2.6.39.orig/crypto/ocf/uio.h linux-2.6.39/crypto/ocf/uio.h ---- linux-2.6.39.orig/crypto/ocf/uio.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/crypto/ocf/uio.h 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,54 @@ -+#ifndef _OCF_UIO_H_ -+#define _OCF_UIO_H_ -+ -+#include -+ -+/* -+ * The linux uio.h doesn't have all we need. To be fully api compatible -+ * with the BSD cryptodev, we need to keep this around. Perhaps this can -+ * be moved back into the linux/uio.h -+ * -+ * Linux port done by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * ALTERNATIVELY, provided that this notice is retained in full, this product -+ * may be distributed under the terms of the GNU General Public License (GPL), -+ * in which case the provisions of the GPL apply INSTEAD OF those given above. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ * --------------------------------------------------------------------------- -+ */ -+ -+struct uio { -+ struct iovec *uio_iov; -+ int uio_iovcnt; -+ off_t uio_offset; -+ int uio_resid; -+#if 0 -+ enum uio_seg uio_segflg; -+ enum uio_rw uio_rw; -+ struct thread *uio_td; -+#endif -+}; -+ -+#endif -diff -Nur linux-2.6.39.orig/drivers/char/random.c linux-2.6.39/drivers/char/random.c ---- linux-2.6.39.orig/drivers/char/random.c 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/drivers/char/random.c 2011-08-01 14:38:19.000000000 +0200 -@@ -130,6 +130,9 @@ - * void add_interrupt_randomness(int irq); - * void add_disk_randomness(struct gendisk *disk); - * -+ * void random_input_words(__u32 *buf, size_t wordcount, int ent_count) -+ * int random_input_wait(void); -+ * - * add_input_randomness() uses the input layer interrupt timing, as well as - * the event type information from the hardware. - * -@@ -147,6 +150,13 @@ - * seek times do not make for good sources of entropy, as their seek - * times are usually fairly consistent. - * -+ * random_input_words() just provides a raw block of entropy to the input -+ * pool, such as from a hardware entropy generator. -+ * -+ * random_input_wait() suspends the caller until such time as the -+ * entropy pool falls below the write threshold, and returns a count of how -+ * much entropy (in bits) is needed to sustain the pool. -+ * - * All of these routines try to estimate how many bits of randomness a - * particular randomness source. They do this by keeping track of the - * first and second order deltas of the event timings. -@@ -266,6 +276,7 @@ - #define SEC_XFER_SIZE 512 - #define EXTRACT_SIZE 10 - -+ - /* - * The minimum number of bits of entropy before we wake up a read on - * /dev/random. Should be enough to do a significant reseed. -@@ -559,6 +570,60 @@ - spin_unlock_irqrestore(&r->lock, flags); - } - -+/* -+ * random_input_words - add bulk entropy to pool -+ * -+ * @buf: buffer to add -+ * @wordcount: number of __u32 words to add -+ * @ent_count: total amount of entropy (in bits) to credit -+ * -+ * this provides bulk input of entropy to the input pool -+ * -+ */ -+void random_input_words(__u32 *buf, size_t wordcount, int ent_count) -+{ -+ mix_pool_bytes(&input_pool, buf, wordcount*4); -+ -+ credit_entropy_bits(&input_pool, ent_count); -+ -+ DEBUG_ENT("crediting %d bits => %d\n", -+ ent_count, input_pool.entropy_count); -+ /* -+ * Wake up waiting processes if we have enough -+ * entropy. -+ */ -+ if (input_pool.entropy_count >= random_read_wakeup_thresh) -+ wake_up_interruptible(&random_read_wait); -+} -+EXPORT_SYMBOL(random_input_words); -+ -+/* -+ * random_input_wait - wait until random needs entropy -+ * -+ * this function sleeps until the /dev/random subsystem actually -+ * needs more entropy, and then return the amount of entropy -+ * that it would be nice to have added to the system. -+ */ -+int random_input_wait(void) -+{ -+ int count; -+ -+ wait_event_interruptible(random_write_wait, -+ input_pool.entropy_count < random_write_wakeup_thresh); -+ -+ count = random_write_wakeup_thresh - input_pool.entropy_count; -+ -+ /* likely we got woken up due to a signal */ -+ if (count <= 0) count = random_read_wakeup_thresh; -+ -+ DEBUG_ENT("requesting %d bits from input_wait()er %d<%d\n", -+ count, -+ input_pool.entropy_count, random_write_wakeup_thresh); -+ -+ return count; -+} -+EXPORT_SYMBOL(random_input_wait); -+ - /********************************************************************* - * - * Entropy input management -diff -Nur linux-2.6.39.orig/drivers/char/random.c.orig linux-2.6.39/drivers/char/random.c.orig ---- linux-2.6.39.orig/drivers/char/random.c.orig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/drivers/char/random.c.orig 2011-08-01 14:38:19.000000000 +0200 -@@ -0,0 +1,1667 @@ -+/* -+ * random.c -- A strong random number generator -+ * -+ * Copyright Matt Mackall , 2003, 2004, 2005 -+ * -+ * Copyright Theodore Ts'o, 1994, 1995, 1996, 1997, 1998, 1999. All -+ * rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, and the entire permission notice in its entirety, -+ * including the disclaimer of warranties. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote -+ * products derived from this software without specific prior -+ * written permission. -+ * -+ * ALTERNATIVELY, this product may be distributed under the terms of -+ * the GNU General Public License, in which case the provisions of the GPL are -+ * required INSTEAD OF the above restrictions. (This clause is -+ * necessary due to a potential bad interaction between the GPL and -+ * the restrictions contained in a BSD-style copyright.) -+ * -+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED -+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ALL OF -+ * WHICH ARE HEREBY DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT -+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE -+ * USE OF THIS SOFTWARE, EVEN IF NOT ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ */ -+ -+/* -+ * (now, with legal B.S. out of the way.....) -+ * -+ * This routine gathers environmental noise from device drivers, etc., -+ * and returns good random numbers, suitable for cryptographic use. -+ * Besides the obvious cryptographic uses, these numbers are also good -+ * for seeding TCP sequence numbers, and other places where it is -+ * desirable to have numbers which are not only random, but hard to -+ * predict by an attacker. -+ * -+ * Theory of operation -+ * =================== -+ * -+ * Computers are very predictable devices. Hence it is extremely hard -+ * to produce truly random numbers on a computer --- as opposed to -+ * pseudo-random numbers, which can easily generated by using a -+ * algorithm. Unfortunately, it is very easy for attackers to guess -+ * the sequence of pseudo-random number generators, and for some -+ * applications this is not acceptable. So instead, we must try to -+ * gather "environmental noise" from the computer's environment, which -+ * must be hard for outside attackers to observe, and use that to -+ * generate random numbers. In a Unix environment, this is best done -+ * from inside the kernel. -+ * -+ * Sources of randomness from the environment include inter-keyboard -+ * timings, inter-interrupt timings from some interrupts, and other -+ * events which are both (a) non-deterministic and (b) hard for an -+ * outside observer to measure. Randomness from these sources are -+ * added to an "entropy pool", which is mixed using a CRC-like function. -+ * This is not cryptographically strong, but it is adequate assuming -+ * the randomness is not chosen maliciously, and it is fast enough that -+ * the overhead of doing it on every interrupt is very reasonable. -+ * As random bytes are mixed into the entropy pool, the routines keep -+ * an *estimate* of how many bits of randomness have been stored into -+ * the random number generator's internal state. -+ * -+ * When random bytes are desired, they are obtained by taking the SHA -+ * hash of the contents of the "entropy pool". The SHA hash avoids -+ * exposing the internal state of the entropy pool. It is believed to -+ * be computationally infeasible to derive any useful information -+ * about the input of SHA from its output. Even if it is possible to -+ * analyze SHA in some clever way, as long as the amount of data -+ * returned from the generator is less than the inherent entropy in -+ * the pool, the output data is totally unpredictable. For this -+ * reason, the routine decreases its internal estimate of how many -+ * bits of "true randomness" are contained in the entropy pool as it -+ * outputs random numbers. -+ * -+ * If this estimate goes to zero, the routine can still generate -+ * random numbers; however, an attacker may (at least in theory) be -+ * able to infer the future output of the generator from prior -+ * outputs. This requires successful cryptanalysis of SHA, which is -+ * not believed to be feasible, but there is a remote possibility. -+ * Nonetheless, these numbers should be useful for the vast majority -+ * of purposes. -+ * -+ * Exported interfaces ---- output -+ * =============================== -+ * -+ * There are three exported interfaces; the first is one designed to -+ * be used from within the kernel: -+ * -+ * void get_random_bytes(void *buf, int nbytes); -+ * -+ * This interface will return the requested number of random bytes, -+ * and place it in the requested buffer. -+ * -+ * The two other interfaces are two character devices /dev/random and -+ * /dev/urandom. /dev/random is suitable for use when very high -+ * quality randomness is desired (for example, for key generation or -+ * one-time pads), as it will only return a maximum of the number of -+ * bits of randomness (as estimated by the random number generator) -+ * contained in the entropy pool. -+ * -+ * The /dev/urandom device does not have this limit, and will return -+ * as many bytes as are requested. As more and more random bytes are -+ * requested without giving time for the entropy pool to recharge, -+ * this will result in random numbers that are merely cryptographically -+ * strong. For many applications, however, this is acceptable. -+ * -+ * Exported interfaces ---- input -+ * ============================== -+ * -+ * The current exported interfaces for gathering environmental noise -+ * from the devices are: -+ * -+ * void add_input_randomness(unsigned int type, unsigned int code, -+ * unsigned int value); -+ * void add_interrupt_randomness(int irq); -+ * void add_disk_randomness(struct gendisk *disk); -+ * -+ * add_input_randomness() uses the input layer interrupt timing, as well as -+ * the event type information from the hardware. -+ * -+ * add_interrupt_randomness() uses the inter-interrupt timing as random -+ * inputs to the entropy pool. Note that not all interrupts are good -+ * sources of randomness! For example, the timer interrupts is not a -+ * good choice, because the periodicity of the interrupts is too -+ * regular, and hence predictable to an attacker. Network Interface -+ * Controller interrupts are a better measure, since the timing of the -+ * NIC interrupts are more unpredictable. -+ * -+ * add_disk_randomness() uses what amounts to the seek time of block -+ * layer request events, on a per-disk_devt basis, as input to the -+ * entropy pool. Note that high-speed solid state drives with very low -+ * seek times do not make for good sources of entropy, as their seek -+ * times are usually fairly consistent. -+ * -+ * All of these routines try to estimate how many bits of randomness a -+ * particular randomness source. They do this by keeping track of the -+ * first and second order deltas of the event timings. -+ * -+ * Ensuring unpredictability at system startup -+ * ============================================ -+ * -+ * When any operating system starts up, it will go through a sequence -+ * of actions that are fairly predictable by an adversary, especially -+ * if the start-up does not involve interaction with a human operator. -+ * This reduces the actual number of bits of unpredictability in the -+ * entropy pool below the value in entropy_count. In order to -+ * counteract this effect, it helps to carry information in the -+ * entropy pool across shut-downs and start-ups. To do this, put the -+ * following lines an appropriate script which is run during the boot -+ * sequence: -+ * -+ * echo "Initializing random number generator..." -+ * random_seed=/var/run/random-seed -+ * # Carry a random seed from start-up to start-up -+ * # Load and then save the whole entropy pool -+ * if [ -f $random_seed ]; then -+ * cat $random_seed >/dev/urandom -+ * else -+ * touch $random_seed -+ * fi -+ * chmod 600 $random_seed -+ * dd if=/dev/urandom of=$random_seed count=1 bs=512 -+ * -+ * and the following lines in an appropriate script which is run as -+ * the system is shutdown: -+ * -+ * # Carry a random seed from shut-down to start-up -+ * # Save the whole entropy pool -+ * echo "Saving random seed..." -+ * random_seed=/var/run/random-seed -+ * touch $random_seed -+ * chmod 600 $random_seed -+ * dd if=/dev/urandom of=$random_seed count=1 bs=512 -+ * -+ * For example, on most modern systems using the System V init -+ * scripts, such code fragments would be found in -+ * /etc/rc.d/init.d/random. On older Linux systems, the correct script -+ * location might be in /etc/rcb.d/rc.local or /etc/rc.d/rc.0. -+ * -+ * Effectively, these commands cause the contents of the entropy pool -+ * to be saved at shut-down time and reloaded into the entropy pool at -+ * start-up. (The 'dd' in the addition to the bootup script is to -+ * make sure that /etc/random-seed is different for every start-up, -+ * even if the system crashes without executing rc.0.) Even with -+ * complete knowledge of the start-up activities, predicting the state -+ * of the entropy pool requires knowledge of the previous history of -+ * the system. -+ * -+ * Configuring the /dev/random driver under Linux -+ * ============================================== -+ * -+ * The /dev/random driver under Linux uses minor numbers 8 and 9 of -+ * the /dev/mem major number (#1). So if your system does not have -+ * /dev/random and /dev/urandom created already, they can be created -+ * by using the commands: -+ * -+ * mknod /dev/random c 1 8 -+ * mknod /dev/urandom c 1 9 -+ * -+ * Acknowledgements: -+ * ================= -+ * -+ * Ideas for constructing this random number generator were derived -+ * from Pretty Good Privacy's random number generator, and from private -+ * discussions with Phil Karn. Colin Plumb provided a faster random -+ * number generator, which speed up the mixing function of the entropy -+ * pool, taken from PGPfone. Dale Worley has also contributed many -+ * useful ideas and suggestions to improve this driver. -+ * -+ * Any flaws in the design are solely my responsibility, and should -+ * not be attributed to the Phil, Colin, or any of authors of PGP. -+ * -+ * Further background information on this topic may be obtained from -+ * RFC 1750, "Randomness Recommendations for Security", by Donald -+ * Eastlake, Steve Crocker, and Jeff Schiller. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#ifdef CONFIG_GENERIC_HARDIRQS -+# include -+#endif -+ -+#include -+#include -+#include -+#include -+ -+/* -+ * Configuration information -+ */ -+#define INPUT_POOL_WORDS 128 -+#define OUTPUT_POOL_WORDS 32 -+#define SEC_XFER_SIZE 512 -+#define EXTRACT_SIZE 10 -+ -+/* -+ * The minimum number of bits of entropy before we wake up a read on -+ * /dev/random. Should be enough to do a significant reseed. -+ */ -+static int random_read_wakeup_thresh = 64; -+ -+/* -+ * If the entropy count falls under this number of bits, then we -+ * should wake up processes which are selecting or polling on write -+ * access to /dev/random. -+ */ -+static int random_write_wakeup_thresh = 128; -+ -+/* -+ * When the input pool goes over trickle_thresh, start dropping most -+ * samples to avoid wasting CPU time and reduce lock contention. -+ */ -+ -+static int trickle_thresh __read_mostly = INPUT_POOL_WORDS * 28; -+ -+static DEFINE_PER_CPU(int, trickle_count); -+ -+/* -+ * A pool of size .poolwords is stirred with a primitive polynomial -+ * of degree .poolwords over GF(2). The taps for various sizes are -+ * defined below. They are chosen to be evenly spaced (minimum RMS -+ * distance from evenly spaced; the numbers in the comments are a -+ * scaled squared error sum) except for the last tap, which is 1 to -+ * get the twisting happening as fast as possible. -+ */ -+static struct poolinfo { -+ int poolwords; -+ int tap1, tap2, tap3, tap4, tap5; -+} poolinfo_table[] = { -+ /* x^128 + x^103 + x^76 + x^51 +x^25 + x + 1 -- 105 */ -+ { 128, 103, 76, 51, 25, 1 }, -+ /* x^32 + x^26 + x^20 + x^14 + x^7 + x + 1 -- 15 */ -+ { 32, 26, 20, 14, 7, 1 }, -+#if 0 -+ /* x^2048 + x^1638 + x^1231 + x^819 + x^411 + x + 1 -- 115 */ -+ { 2048, 1638, 1231, 819, 411, 1 }, -+ -+ /* x^1024 + x^817 + x^615 + x^412 + x^204 + x + 1 -- 290 */ -+ { 1024, 817, 615, 412, 204, 1 }, -+ -+ /* x^1024 + x^819 + x^616 + x^410 + x^207 + x^2 + 1 -- 115 */ -+ { 1024, 819, 616, 410, 207, 2 }, -+ -+ /* x^512 + x^411 + x^308 + x^208 + x^104 + x + 1 -- 225 */ -+ { 512, 411, 308, 208, 104, 1 }, -+ -+ /* x^512 + x^409 + x^307 + x^206 + x^102 + x^2 + 1 -- 95 */ -+ { 512, 409, 307, 206, 102, 2 }, -+ /* x^512 + x^409 + x^309 + x^205 + x^103 + x^2 + 1 -- 95 */ -+ { 512, 409, 309, 205, 103, 2 }, -+ -+ /* x^256 + x^205 + x^155 + x^101 + x^52 + x + 1 -- 125 */ -+ { 256, 205, 155, 101, 52, 1 }, -+ -+ /* x^128 + x^103 + x^78 + x^51 + x^27 + x^2 + 1 -- 70 */ -+ { 128, 103, 78, 51, 27, 2 }, -+ -+ /* x^64 + x^52 + x^39 + x^26 + x^14 + x + 1 -- 15 */ -+ { 64, 52, 39, 26, 14, 1 }, -+#endif -+}; -+ -+#define POOLBITS poolwords*32 -+#define POOLBYTES poolwords*4 -+ -+/* -+ * For the purposes of better mixing, we use the CRC-32 polynomial as -+ * well to make a twisted Generalized Feedback Shift Reigster -+ * -+ * (See M. Matsumoto & Y. Kurita, 1992. Twisted GFSR generators. ACM -+ * Transactions on Modeling and Computer Simulation 2(3):179-194. -+ * Also see M. Matsumoto & Y. Kurita, 1994. Twisted GFSR generators -+ * II. ACM Transactions on Mdeling and Computer Simulation 4:254-266) -+ * -+ * Thanks to Colin Plumb for suggesting this. -+ * -+ * We have not analyzed the resultant polynomial to prove it primitive; -+ * in fact it almost certainly isn't. Nonetheless, the irreducible factors -+ * of a random large-degree polynomial over GF(2) are more than large enough -+ * that periodicity is not a concern. -+ * -+ * The input hash is much less sensitive than the output hash. All -+ * that we want of it is that it be a good non-cryptographic hash; -+ * i.e. it not produce collisions when fed "random" data of the sort -+ * we expect to see. As long as the pool state differs for different -+ * inputs, we have preserved the input entropy and done a good job. -+ * The fact that an intelligent attacker can construct inputs that -+ * will produce controlled alterations to the pool's state is not -+ * important because we don't consider such inputs to contribute any -+ * randomness. The only property we need with respect to them is that -+ * the attacker can't increase his/her knowledge of the pool's state. -+ * Since all additions are reversible (knowing the final state and the -+ * input, you can reconstruct the initial state), if an attacker has -+ * any uncertainty about the initial state, he/she can only shuffle -+ * that uncertainty about, but never cause any collisions (which would -+ * decrease the uncertainty). -+ * -+ * The chosen system lets the state of the pool be (essentially) the input -+ * modulo the generator polymnomial. Now, for random primitive polynomials, -+ * this is a universal class of hash functions, meaning that the chance -+ * of a collision is limited by the attacker's knowledge of the generator -+ * polynomail, so if it is chosen at random, an attacker can never force -+ * a collision. Here, we use a fixed polynomial, but we *can* assume that -+ * ###--> it is unknown to the processes generating the input entropy. <-### -+ * Because of this important property, this is a good, collision-resistant -+ * hash; hash collisions will occur no more often than chance. -+ */ -+ -+/* -+ * Static global variables -+ */ -+static DECLARE_WAIT_QUEUE_HEAD(random_read_wait); -+static DECLARE_WAIT_QUEUE_HEAD(random_write_wait); -+static struct fasync_struct *fasync; -+ -+#if 0 -+static int debug; -+module_param(debug, bool, 0644); -+#define DEBUG_ENT(fmt, arg...) do { \ -+ if (debug) \ -+ printk(KERN_DEBUG "random %04d %04d %04d: " \ -+ fmt,\ -+ input_pool.entropy_count,\ -+ blocking_pool.entropy_count,\ -+ nonblocking_pool.entropy_count,\ -+ ## arg); } while (0) -+#else -+#define DEBUG_ENT(fmt, arg...) do {} while (0) -+#endif -+ -+/********************************************************************** -+ * -+ * OS independent entropy store. Here are the functions which handle -+ * storing entropy in an entropy pool. -+ * -+ **********************************************************************/ -+ -+struct entropy_store; -+struct entropy_store { -+ /* read-only data: */ -+ struct poolinfo *poolinfo; -+ __u32 *pool; -+ const char *name; -+ struct entropy_store *pull; -+ int limit; -+ -+ /* read-write data: */ -+ spinlock_t lock; -+ unsigned add_ptr; -+ int entropy_count; -+ int input_rotate; -+ __u8 last_data[EXTRACT_SIZE]; -+}; -+ -+static __u32 input_pool_data[INPUT_POOL_WORDS]; -+static __u32 blocking_pool_data[OUTPUT_POOL_WORDS]; -+static __u32 nonblocking_pool_data[OUTPUT_POOL_WORDS]; -+ -+static struct entropy_store input_pool = { -+ .poolinfo = &poolinfo_table[0], -+ .name = "input", -+ .limit = 1, -+ .lock = __SPIN_LOCK_UNLOCKED(&input_pool.lock), -+ .pool = input_pool_data -+}; -+ -+static struct entropy_store blocking_pool = { -+ .poolinfo = &poolinfo_table[1], -+ .name = "blocking", -+ .limit = 1, -+ .pull = &input_pool, -+ .lock = __SPIN_LOCK_UNLOCKED(&blocking_pool.lock), -+ .pool = blocking_pool_data -+}; -+ -+static struct entropy_store nonblocking_pool = { -+ .poolinfo = &poolinfo_table[1], -+ .name = "nonblocking", -+ .pull = &input_pool, -+ .lock = __SPIN_LOCK_UNLOCKED(&nonblocking_pool.lock), -+ .pool = nonblocking_pool_data -+}; -+ -+/* -+ * This function adds bytes into the entropy "pool". It does not -+ * update the entropy estimate. The caller should call -+ * credit_entropy_bits if this is appropriate. -+ * -+ * The pool is stirred with a primitive polynomial of the appropriate -+ * degree, and then twisted. We twist by three bits at a time because -+ * it's cheap to do so and helps slightly in the expected case where -+ * the entropy is concentrated in the low-order bits. -+ */ -+static void mix_pool_bytes_extract(struct entropy_store *r, const void *in, -+ int nbytes, __u8 out[64]) -+{ -+ static __u32 const twist_table[8] = { -+ 0x00000000, 0x3b6e20c8, 0x76dc4190, 0x4db26158, -+ 0xedb88320, 0xd6d6a3e8, 0x9b64c2b0, 0xa00ae278 }; -+ unsigned long i, j, tap1, tap2, tap3, tap4, tap5; -+ int input_rotate; -+ int wordmask = r->poolinfo->poolwords - 1; -+ const char *bytes = in; -+ __u32 w; -+ unsigned long flags; -+ -+ /* Taps are constant, so we can load them without holding r->lock. */ -+ tap1 = r->poolinfo->tap1; -+ tap2 = r->poolinfo->tap2; -+ tap3 = r->poolinfo->tap3; -+ tap4 = r->poolinfo->tap4; -+ tap5 = r->poolinfo->tap5; -+ -+ spin_lock_irqsave(&r->lock, flags); -+ input_rotate = r->input_rotate; -+ i = r->add_ptr; -+ -+ /* mix one byte at a time to simplify size handling and churn faster */ -+ while (nbytes--) { -+ w = rol32(*bytes++, input_rotate & 31); -+ i = (i - 1) & wordmask; -+ -+ /* XOR in the various taps */ -+ w ^= r->pool[i]; -+ w ^= r->pool[(i + tap1) & wordmask]; -+ w ^= r->pool[(i + tap2) & wordmask]; -+ w ^= r->pool[(i + tap3) & wordmask]; -+ w ^= r->pool[(i + tap4) & wordmask]; -+ w ^= r->pool[(i + tap5) & wordmask]; -+ -+ /* Mix the result back in with a twist */ -+ r->pool[i] = (w >> 3) ^ twist_table[w & 7]; -+ -+ /* -+ * Normally, we add 7 bits of rotation to the pool. -+ * At the beginning of the pool, add an extra 7 bits -+ * rotation, so that successive passes spread the -+ * input bits across the pool evenly. -+ */ -+ input_rotate += i ? 7 : 14; -+ } -+ -+ r->input_rotate = input_rotate; -+ r->add_ptr = i; -+ -+ if (out) -+ for (j = 0; j < 16; j++) -+ ((__u32 *)out)[j] = r->pool[(i - j) & wordmask]; -+ -+ spin_unlock_irqrestore(&r->lock, flags); -+} -+ -+static void mix_pool_bytes(struct entropy_store *r, const void *in, int bytes) -+{ -+ mix_pool_bytes_extract(r, in, bytes, NULL); -+} -+ -+/* -+ * Credit (or debit) the entropy store with n bits of entropy -+ */ -+static void credit_entropy_bits(struct entropy_store *r, int nbits) -+{ -+ unsigned long flags; -+ int entropy_count; -+ -+ if (!nbits) -+ return; -+ -+ spin_lock_irqsave(&r->lock, flags); -+ -+ DEBUG_ENT("added %d entropy credits to %s\n", nbits, r->name); -+ entropy_count = r->entropy_count; -+ entropy_count += nbits; -+ if (entropy_count < 0) { -+ DEBUG_ENT("negative entropy/overflow\n"); -+ entropy_count = 0; -+ } else if (entropy_count > r->poolinfo->POOLBITS) -+ entropy_count = r->poolinfo->POOLBITS; -+ r->entropy_count = entropy_count; -+ -+ /* should we wake readers? */ -+ if (r == &input_pool && entropy_count >= random_read_wakeup_thresh) { -+ wake_up_interruptible(&random_read_wait); -+ kill_fasync(&fasync, SIGIO, POLL_IN); -+ } -+ spin_unlock_irqrestore(&r->lock, flags); -+} -+ -+/********************************************************************* -+ * -+ * Entropy input management -+ * -+ *********************************************************************/ -+ -+/* There is one of these per entropy source */ -+struct timer_rand_state { -+ cycles_t last_time; -+ long last_delta, last_delta2; -+ unsigned dont_count_entropy:1; -+}; -+ -+#ifndef CONFIG_GENERIC_HARDIRQS -+ -+static struct timer_rand_state *irq_timer_state[NR_IRQS]; -+ -+static struct timer_rand_state *get_timer_rand_state(unsigned int irq) -+{ -+ return irq_timer_state[irq]; -+} -+ -+static void set_timer_rand_state(unsigned int irq, -+ struct timer_rand_state *state) -+{ -+ irq_timer_state[irq] = state; -+} -+ -+#else -+ -+static struct timer_rand_state *get_timer_rand_state(unsigned int irq) -+{ -+ struct irq_desc *desc; -+ -+ desc = irq_to_desc(irq); -+ -+ return desc->timer_rand_state; -+} -+ -+static void set_timer_rand_state(unsigned int irq, -+ struct timer_rand_state *state) -+{ -+ struct irq_desc *desc; -+ -+ desc = irq_to_desc(irq); -+ -+ desc->timer_rand_state = state; -+} -+#endif -+ -+static struct timer_rand_state input_timer_state; -+ -+/* -+ * This function adds entropy to the entropy "pool" by using timing -+ * delays. It uses the timer_rand_state structure to make an estimate -+ * of how many bits of entropy this call has added to the pool. -+ * -+ * The number "num" is also added to the pool - it should somehow describe -+ * the type of event which just happened. This is currently 0-255 for -+ * keyboard scan codes, and 256 upwards for interrupts. -+ * -+ */ -+static void add_timer_randomness(struct timer_rand_state *state, unsigned num) -+{ -+ struct { -+ cycles_t cycles; -+ long jiffies; -+ unsigned num; -+ } sample; -+ long delta, delta2, delta3; -+ -+ preempt_disable(); -+ /* if over the trickle threshold, use only 1 in 4096 samples */ -+ if (input_pool.entropy_count > trickle_thresh && -+ ((__this_cpu_inc_return(trickle_count) - 1) & 0xfff)) -+ goto out; -+ -+ sample.jiffies = jiffies; -+ sample.cycles = get_cycles(); -+ sample.num = num; -+ mix_pool_bytes(&input_pool, &sample, sizeof(sample)); -+ -+ /* -+ * Calculate number of bits of randomness we probably added. -+ * We take into account the first, second and third-order deltas -+ * in order to make our estimate. -+ */ -+ -+ if (!state->dont_count_entropy) { -+ delta = sample.jiffies - state->last_time; -+ state->last_time = sample.jiffies; -+ -+ delta2 = delta - state->last_delta; -+ state->last_delta = delta; -+ -+ delta3 = delta2 - state->last_delta2; -+ state->last_delta2 = delta2; -+ -+ if (delta < 0) -+ delta = -delta; -+ if (delta2 < 0) -+ delta2 = -delta2; -+ if (delta3 < 0) -+ delta3 = -delta3; -+ if (delta > delta2) -+ delta = delta2; -+ if (delta > delta3) -+ delta = delta3; -+ -+ /* -+ * delta is now minimum absolute delta. -+ * Round down by 1 bit on general principles, -+ * and limit entropy entimate to 12 bits. -+ */ -+ credit_entropy_bits(&input_pool, -+ min_t(int, fls(delta>>1), 11)); -+ } -+out: -+ preempt_enable(); -+} -+ -+void add_input_randomness(unsigned int type, unsigned int code, -+ unsigned int value) -+{ -+ static unsigned char last_value; -+ -+ /* ignore autorepeat and the like */ -+ if (value == last_value) -+ return; -+ -+ DEBUG_ENT("input event\n"); -+ last_value = value; -+ add_timer_randomness(&input_timer_state, -+ (type << 4) ^ code ^ (code >> 4) ^ value); -+} -+EXPORT_SYMBOL_GPL(add_input_randomness); -+ -+void add_interrupt_randomness(int irq) -+{ -+ struct timer_rand_state *state; -+ -+ state = get_timer_rand_state(irq); -+ -+ if (state == NULL) -+ return; -+ -+ DEBUG_ENT("irq event %d\n", irq); -+ add_timer_randomness(state, 0x100 + irq); -+} -+ -+#ifdef CONFIG_BLOCK -+void add_disk_randomness(struct gendisk *disk) -+{ -+ if (!disk || !disk->random) -+ return; -+ /* first major is 1, so we get >= 0x200 here */ -+ DEBUG_ENT("disk event %d:%d\n", -+ MAJOR(disk_devt(disk)), MINOR(disk_devt(disk))); -+ -+ add_timer_randomness(disk->random, 0x100 + disk_devt(disk)); -+} -+#endif -+ -+/********************************************************************* -+ * -+ * Entropy extraction routines -+ * -+ *********************************************************************/ -+ -+static ssize_t extract_entropy(struct entropy_store *r, void *buf, -+ size_t nbytes, int min, int rsvd); -+ -+/* -+ * This utility inline function is responsible for transferring entropy -+ * from the primary pool to the secondary extraction pool. We make -+ * sure we pull enough for a 'catastrophic reseed'. -+ */ -+static void xfer_secondary_pool(struct entropy_store *r, size_t nbytes) -+{ -+ __u32 tmp[OUTPUT_POOL_WORDS]; -+ -+ if (r->pull && r->entropy_count < nbytes * 8 && -+ r->entropy_count < r->poolinfo->POOLBITS) { -+ /* If we're limited, always leave two wakeup worth's BITS */ -+ int rsvd = r->limit ? 0 : random_read_wakeup_thresh/4; -+ int bytes = nbytes; -+ -+ /* pull at least as many as BYTES as wakeup BITS */ -+ bytes = max_t(int, bytes, random_read_wakeup_thresh / 8); -+ /* but never more than the buffer size */ -+ bytes = min_t(int, bytes, sizeof(tmp)); -+ -+ DEBUG_ENT("going to reseed %s with %d bits " -+ "(%d of %d requested)\n", -+ r->name, bytes * 8, nbytes * 8, r->entropy_count); -+ -+ bytes = extract_entropy(r->pull, tmp, bytes, -+ random_read_wakeup_thresh / 8, rsvd); -+ mix_pool_bytes(r, tmp, bytes); -+ credit_entropy_bits(r, bytes*8); -+ } -+} -+ -+/* -+ * These functions extracts randomness from the "entropy pool", and -+ * returns it in a buffer. -+ * -+ * The min parameter specifies the minimum amount we can pull before -+ * failing to avoid races that defeat catastrophic reseeding while the -+ * reserved parameter indicates how much entropy we must leave in the -+ * pool after each pull to avoid starving other readers. -+ * -+ * Note: extract_entropy() assumes that .poolwords is a multiple of 16 words. -+ */ -+ -+static size_t account(struct entropy_store *r, size_t nbytes, int min, -+ int reserved) -+{ -+ unsigned long flags; -+ -+ /* Hold lock while accounting */ -+ spin_lock_irqsave(&r->lock, flags); -+ -+ BUG_ON(r->entropy_count > r->poolinfo->POOLBITS); -+ DEBUG_ENT("trying to extract %d bits from %s\n", -+ nbytes * 8, r->name); -+ -+ /* Can we pull enough? */ -+ if (r->entropy_count / 8 < min + reserved) { -+ nbytes = 0; -+ } else { -+ /* If limited, never pull more than available */ -+ if (r->limit && nbytes + reserved >= r->entropy_count / 8) -+ nbytes = r->entropy_count/8 - reserved; -+ -+ if (r->entropy_count / 8 >= nbytes + reserved) -+ r->entropy_count -= nbytes*8; -+ else -+ r->entropy_count = reserved; -+ -+ if (r->entropy_count < random_write_wakeup_thresh) { -+ wake_up_interruptible(&random_write_wait); -+ kill_fasync(&fasync, SIGIO, POLL_OUT); -+ } -+ } -+ -+ DEBUG_ENT("debiting %d entropy credits from %s%s\n", -+ nbytes * 8, r->name, r->limit ? "" : " (unlimited)"); -+ -+ spin_unlock_irqrestore(&r->lock, flags); -+ -+ return nbytes; -+} -+ -+static void extract_buf(struct entropy_store *r, __u8 *out) -+{ -+ int i; -+ __u32 hash[5], workspace[SHA_WORKSPACE_WORDS]; -+ __u8 extract[64]; -+ -+ /* Generate a hash across the pool, 16 words (512 bits) at a time */ -+ sha_init(hash); -+ for (i = 0; i < r->poolinfo->poolwords; i += 16) -+ sha_transform(hash, (__u8 *)(r->pool + i), workspace); -+ -+ /* -+ * We mix the hash back into the pool to prevent backtracking -+ * attacks (where the attacker knows the state of the pool -+ * plus the current outputs, and attempts to find previous -+ * ouputs), unless the hash function can be inverted. By -+ * mixing at least a SHA1 worth of hash data back, we make -+ * brute-forcing the feedback as hard as brute-forcing the -+ * hash. -+ */ -+ mix_pool_bytes_extract(r, hash, sizeof(hash), extract); -+ -+ /* -+ * To avoid duplicates, we atomically extract a portion of the -+ * pool while mixing, and hash one final time. -+ */ -+ sha_transform(hash, extract, workspace); -+ memset(extract, 0, sizeof(extract)); -+ memset(workspace, 0, sizeof(workspace)); -+ -+ /* -+ * In case the hash function has some recognizable output -+ * pattern, we fold it in half. Thus, we always feed back -+ * twice as much data as we output. -+ */ -+ hash[0] ^= hash[3]; -+ hash[1] ^= hash[4]; -+ hash[2] ^= rol32(hash[2], 16); -+ memcpy(out, hash, EXTRACT_SIZE); -+ memset(hash, 0, sizeof(hash)); -+} -+ -+static ssize_t extract_entropy(struct entropy_store *r, void *buf, -+ size_t nbytes, int min, int reserved) -+{ -+ ssize_t ret = 0, i; -+ __u8 tmp[EXTRACT_SIZE]; -+ unsigned long flags; -+ -+ xfer_secondary_pool(r, nbytes); -+ nbytes = account(r, nbytes, min, reserved); -+ -+ while (nbytes) { -+ extract_buf(r, tmp); -+ -+ if (fips_enabled) { -+ spin_lock_irqsave(&r->lock, flags); -+ if (!memcmp(tmp, r->last_data, EXTRACT_SIZE)) -+ panic("Hardware RNG duplicated output!\n"); -+ memcpy(r->last_data, tmp, EXTRACT_SIZE); -+ spin_unlock_irqrestore(&r->lock, flags); -+ } -+ i = min_t(int, nbytes, EXTRACT_SIZE); -+ memcpy(buf, tmp, i); -+ nbytes -= i; -+ buf += i; -+ ret += i; -+ } -+ -+ /* Wipe data just returned from memory */ -+ memset(tmp, 0, sizeof(tmp)); -+ -+ return ret; -+} -+ -+static ssize_t extract_entropy_user(struct entropy_store *r, void __user *buf, -+ size_t nbytes) -+{ -+ ssize_t ret = 0, i; -+ __u8 tmp[EXTRACT_SIZE]; -+ -+ xfer_secondary_pool(r, nbytes); -+ nbytes = account(r, nbytes, 0, 0); -+ -+ while (nbytes) { -+ if (need_resched()) { -+ if (signal_pending(current)) { -+ if (ret == 0) -+ ret = -ERESTARTSYS; -+ break; -+ } -+ schedule(); -+ } -+ -+ extract_buf(r, tmp); -+ i = min_t(int, nbytes, EXTRACT_SIZE); -+ if (copy_to_user(buf, tmp, i)) { -+ ret = -EFAULT; -+ break; -+ } -+ -+ nbytes -= i; -+ buf += i; -+ ret += i; -+ } -+ -+ /* Wipe data just returned from memory */ -+ memset(tmp, 0, sizeof(tmp)); -+ -+ return ret; -+} -+ -+/* -+ * This function is the exported kernel interface. It returns some -+ * number of good random numbers, suitable for seeding TCP sequence -+ * numbers, etc. -+ */ -+void get_random_bytes(void *buf, int nbytes) -+{ -+ extract_entropy(&nonblocking_pool, buf, nbytes, 0, 0); -+} -+EXPORT_SYMBOL(get_random_bytes); -+ -+/* -+ * init_std_data - initialize pool with system data -+ * -+ * @r: pool to initialize -+ * -+ * This function clears the pool's entropy count and mixes some system -+ * data into the pool to prepare it for use. The pool is not cleared -+ * as that can only decrease the entropy in the pool. -+ */ -+static void init_std_data(struct entropy_store *r) -+{ -+ ktime_t now; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&r->lock, flags); -+ r->entropy_count = 0; -+ spin_unlock_irqrestore(&r->lock, flags); -+ -+ now = ktime_get_real(); -+ mix_pool_bytes(r, &now, sizeof(now)); -+ mix_pool_bytes(r, utsname(), sizeof(*(utsname()))); -+} -+ -+static int rand_initialize(void) -+{ -+ init_std_data(&input_pool); -+ init_std_data(&blocking_pool); -+ init_std_data(&nonblocking_pool); -+ return 0; -+} -+module_init(rand_initialize); -+ -+void rand_initialize_irq(int irq) -+{ -+ struct timer_rand_state *state; -+ -+ state = get_timer_rand_state(irq); -+ -+ if (state) -+ return; -+ -+ /* -+ * If kzalloc returns null, we just won't use that entropy -+ * source. -+ */ -+ state = kzalloc(sizeof(struct timer_rand_state), GFP_KERNEL); -+ if (state) -+ set_timer_rand_state(irq, state); -+} -+ -+#ifdef CONFIG_BLOCK -+void rand_initialize_disk(struct gendisk *disk) -+{ -+ struct timer_rand_state *state; -+ -+ /* -+ * If kzalloc returns null, we just won't use that entropy -+ * source. -+ */ -+ state = kzalloc(sizeof(struct timer_rand_state), GFP_KERNEL); -+ if (state) -+ disk->random = state; -+} -+#endif -+ -+static ssize_t -+random_read(struct file *file, char __user *buf, size_t nbytes, loff_t *ppos) -+{ -+ ssize_t n, retval = 0, count = 0; -+ -+ if (nbytes == 0) -+ return 0; -+ -+ while (nbytes > 0) { -+ n = nbytes; -+ if (n > SEC_XFER_SIZE) -+ n = SEC_XFER_SIZE; -+ -+ DEBUG_ENT("reading %d bits\n", n*8); -+ -+ n = extract_entropy_user(&blocking_pool, buf, n); -+ -+ DEBUG_ENT("read got %d bits (%d still needed)\n", -+ n*8, (nbytes-n)*8); -+ -+ if (n == 0) { -+ if (file->f_flags & O_NONBLOCK) { -+ retval = -EAGAIN; -+ break; -+ } -+ -+ DEBUG_ENT("sleeping?\n"); -+ -+ wait_event_interruptible(random_read_wait, -+ input_pool.entropy_count >= -+ random_read_wakeup_thresh); -+ -+ DEBUG_ENT("awake\n"); -+ -+ if (signal_pending(current)) { -+ retval = -ERESTARTSYS; -+ break; -+ } -+ -+ continue; -+ } -+ -+ if (n < 0) { -+ retval = n; -+ break; -+ } -+ count += n; -+ buf += n; -+ nbytes -= n; -+ break; /* This break makes the device work */ -+ /* like a named pipe */ -+ } -+ -+ return (count ? count : retval); -+} -+ -+static ssize_t -+urandom_read(struct file *file, char __user *buf, size_t nbytes, loff_t *ppos) -+{ -+ return extract_entropy_user(&nonblocking_pool, buf, nbytes); -+} -+ -+static unsigned int -+random_poll(struct file *file, poll_table * wait) -+{ -+ unsigned int mask; -+ -+ poll_wait(file, &random_read_wait, wait); -+ poll_wait(file, &random_write_wait, wait); -+ mask = 0; -+ if (input_pool.entropy_count >= random_read_wakeup_thresh) -+ mask |= POLLIN | POLLRDNORM; -+ if (input_pool.entropy_count < random_write_wakeup_thresh) -+ mask |= POLLOUT | POLLWRNORM; -+ return mask; -+} -+ -+static int -+write_pool(struct entropy_store *r, const char __user *buffer, size_t count) -+{ -+ size_t bytes; -+ __u32 buf[16]; -+ const char __user *p = buffer; -+ -+ while (count > 0) { -+ bytes = min(count, sizeof(buf)); -+ if (copy_from_user(&buf, p, bytes)) -+ return -EFAULT; -+ -+ count -= bytes; -+ p += bytes; -+ -+ mix_pool_bytes(r, buf, bytes); -+ cond_resched(); -+ } -+ -+ return 0; -+} -+ -+static ssize_t random_write(struct file *file, const char __user *buffer, -+ size_t count, loff_t *ppos) -+{ -+ size_t ret; -+ -+ ret = write_pool(&blocking_pool, buffer, count); -+ if (ret) -+ return ret; -+ ret = write_pool(&nonblocking_pool, buffer, count); -+ if (ret) -+ return ret; -+ -+ return (ssize_t)count; -+} -+ -+static long random_ioctl(struct file *f, unsigned int cmd, unsigned long arg) -+{ -+ int size, ent_count; -+ int __user *p = (int __user *)arg; -+ int retval; -+ -+ switch (cmd) { -+ case RNDGETENTCNT: -+ /* inherently racy, no point locking */ -+ if (put_user(input_pool.entropy_count, p)) -+ return -EFAULT; -+ return 0; -+ case RNDADDTOENTCNT: -+ if (!capable(CAP_SYS_ADMIN)) -+ return -EPERM; -+ if (get_user(ent_count, p)) -+ return -EFAULT; -+ credit_entropy_bits(&input_pool, ent_count); -+ return 0; -+ case RNDADDENTROPY: -+ if (!capable(CAP_SYS_ADMIN)) -+ return -EPERM; -+ if (get_user(ent_count, p++)) -+ return -EFAULT; -+ if (ent_count < 0) -+ return -EINVAL; -+ if (get_user(size, p++)) -+ return -EFAULT; -+ retval = write_pool(&input_pool, (const char __user *)p, -+ size); -+ if (retval < 0) -+ return retval; -+ credit_entropy_bits(&input_pool, ent_count); -+ return 0; -+ case RNDZAPENTCNT: -+ case RNDCLEARPOOL: -+ /* Clear the entropy pool counters. */ -+ if (!capable(CAP_SYS_ADMIN)) -+ return -EPERM; -+ rand_initialize(); -+ return 0; -+ default: -+ return -EINVAL; -+ } -+} -+ -+static int random_fasync(int fd, struct file *filp, int on) -+{ -+ return fasync_helper(fd, filp, on, &fasync); -+} -+ -+const struct file_operations random_fops = { -+ .read = random_read, -+ .write = random_write, -+ .poll = random_poll, -+ .unlocked_ioctl = random_ioctl, -+ .fasync = random_fasync, -+ .llseek = noop_llseek, -+}; -+ -+const struct file_operations urandom_fops = { -+ .read = urandom_read, -+ .write = random_write, -+ .unlocked_ioctl = random_ioctl, -+ .fasync = random_fasync, -+ .llseek = noop_llseek, -+}; -+ -+/*************************************************************** -+ * Random UUID interface -+ * -+ * Used here for a Boot ID, but can be useful for other kernel -+ * drivers. -+ ***************************************************************/ -+ -+/* -+ * Generate random UUID -+ */ -+void generate_random_uuid(unsigned char uuid_out[16]) -+{ -+ get_random_bytes(uuid_out, 16); -+ /* Set UUID version to 4 --- truly random generation */ -+ uuid_out[6] = (uuid_out[6] & 0x0F) | 0x40; -+ /* Set the UUID variant to DCE */ -+ uuid_out[8] = (uuid_out[8] & 0x3F) | 0x80; -+} -+EXPORT_SYMBOL(generate_random_uuid); -+ -+/******************************************************************** -+ * -+ * Sysctl interface -+ * -+ ********************************************************************/ -+ -+#ifdef CONFIG_SYSCTL -+ -+#include -+ -+static int min_read_thresh = 8, min_write_thresh; -+static int max_read_thresh = INPUT_POOL_WORDS * 32; -+static int max_write_thresh = INPUT_POOL_WORDS * 32; -+static char sysctl_bootid[16]; -+ -+/* -+ * These functions is used to return both the bootid UUID, and random -+ * UUID. The difference is in whether table->data is NULL; if it is, -+ * then a new UUID is generated and returned to the user. -+ * -+ * If the user accesses this via the proc interface, it will be returned -+ * as an ASCII string in the standard UUID format. If accesses via the -+ * sysctl system call, it is returned as 16 bytes of binary data. -+ */ -+static int proc_do_uuid(ctl_table *table, int write, -+ void __user *buffer, size_t *lenp, loff_t *ppos) -+{ -+ ctl_table fake_table; -+ unsigned char buf[64], tmp_uuid[16], *uuid; -+ -+ uuid = table->data; -+ if (!uuid) { -+ uuid = tmp_uuid; -+ uuid[8] = 0; -+ } -+ if (uuid[8] == 0) -+ generate_random_uuid(uuid); -+ -+ sprintf(buf, "%pU", uuid); -+ -+ fake_table.data = buf; -+ fake_table.maxlen = sizeof(buf); -+ -+ return proc_dostring(&fake_table, write, buffer, lenp, ppos); -+} -+ -+static int sysctl_poolsize = INPUT_POOL_WORDS * 32; -+ctl_table random_table[] = { -+ { -+ .procname = "poolsize", -+ .data = &sysctl_poolsize, -+ .maxlen = sizeof(int), -+ .mode = 0444, -+ .proc_handler = proc_dointvec, -+ }, -+ { -+ .procname = "entropy_avail", -+ .maxlen = sizeof(int), -+ .mode = 0444, -+ .proc_handler = proc_dointvec, -+ .data = &input_pool.entropy_count, -+ }, -+ { -+ .procname = "read_wakeup_threshold", -+ .data = &random_read_wakeup_thresh, -+ .maxlen = sizeof(int), -+ .mode = 0644, -+ .proc_handler = proc_dointvec_minmax, -+ .extra1 = &min_read_thresh, -+ .extra2 = &max_read_thresh, -+ }, -+ { -+ .procname = "write_wakeup_threshold", -+ .data = &random_write_wakeup_thresh, -+ .maxlen = sizeof(int), -+ .mode = 0644, -+ .proc_handler = proc_dointvec_minmax, -+ .extra1 = &min_write_thresh, -+ .extra2 = &max_write_thresh, -+ }, -+ { -+ .procname = "boot_id", -+ .data = &sysctl_bootid, -+ .maxlen = 16, -+ .mode = 0444, -+ .proc_handler = proc_do_uuid, -+ }, -+ { -+ .procname = "uuid", -+ .maxlen = 16, -+ .mode = 0444, -+ .proc_handler = proc_do_uuid, -+ }, -+ { } -+}; -+#endif /* CONFIG_SYSCTL */ -+ -+/******************************************************************** -+ * -+ * Random functions for networking -+ * -+ ********************************************************************/ -+ -+/* -+ * TCP initial sequence number picking. This uses the random number -+ * generator to pick an initial secret value. This value is hashed -+ * along with the TCP endpoint information to provide a unique -+ * starting point for each pair of TCP endpoints. This defeats -+ * attacks which rely on guessing the initial TCP sequence number. -+ * This algorithm was suggested by Steve Bellovin. -+ * -+ * Using a very strong hash was taking an appreciable amount of the total -+ * TCP connection establishment time, so this is a weaker hash, -+ * compensated for by changing the secret periodically. -+ */ -+ -+/* F, G and H are basic MD4 functions: selection, majority, parity */ -+#define F(x, y, z) ((z) ^ ((x) & ((y) ^ (z)))) -+#define G(x, y, z) (((x) & (y)) + (((x) ^ (y)) & (z))) -+#define H(x, y, z) ((x) ^ (y) ^ (z)) -+ -+/* -+ * The generic round function. The application is so specific that -+ * we don't bother protecting all the arguments with parens, as is generally -+ * good macro practice, in favor of extra legibility. -+ * Rotation is separate from addition to prevent recomputation -+ */ -+#define ROUND(f, a, b, c, d, x, s) \ -+ (a += f(b, c, d) + x, a = (a << s) | (a >> (32 - s))) -+#define K1 0 -+#define K2 013240474631UL -+#define K3 015666365641UL -+ -+#if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE) -+ -+static __u32 twothirdsMD4Transform(__u32 const buf[4], __u32 const in[12]) -+{ -+ __u32 a = buf[0], b = buf[1], c = buf[2], d = buf[3]; -+ -+ /* Round 1 */ -+ ROUND(F, a, b, c, d, in[ 0] + K1, 3); -+ ROUND(F, d, a, b, c, in[ 1] + K1, 7); -+ ROUND(F, c, d, a, b, in[ 2] + K1, 11); -+ ROUND(F, b, c, d, a, in[ 3] + K1, 19); -+ ROUND(F, a, b, c, d, in[ 4] + K1, 3); -+ ROUND(F, d, a, b, c, in[ 5] + K1, 7); -+ ROUND(F, c, d, a, b, in[ 6] + K1, 11); -+ ROUND(F, b, c, d, a, in[ 7] + K1, 19); -+ ROUND(F, a, b, c, d, in[ 8] + K1, 3); -+ ROUND(F, d, a, b, c, in[ 9] + K1, 7); -+ ROUND(F, c, d, a, b, in[10] + K1, 11); -+ ROUND(F, b, c, d, a, in[11] + K1, 19); -+ -+ /* Round 2 */ -+ ROUND(G, a, b, c, d, in[ 1] + K2, 3); -+ ROUND(G, d, a, b, c, in[ 3] + K2, 5); -+ ROUND(G, c, d, a, b, in[ 5] + K2, 9); -+ ROUND(G, b, c, d, a, in[ 7] + K2, 13); -+ ROUND(G, a, b, c, d, in[ 9] + K2, 3); -+ ROUND(G, d, a, b, c, in[11] + K2, 5); -+ ROUND(G, c, d, a, b, in[ 0] + K2, 9); -+ ROUND(G, b, c, d, a, in[ 2] + K2, 13); -+ ROUND(G, a, b, c, d, in[ 4] + K2, 3); -+ ROUND(G, d, a, b, c, in[ 6] + K2, 5); -+ ROUND(G, c, d, a, b, in[ 8] + K2, 9); -+ ROUND(G, b, c, d, a, in[10] + K2, 13); -+ -+ /* Round 3 */ -+ ROUND(H, a, b, c, d, in[ 3] + K3, 3); -+ ROUND(H, d, a, b, c, in[ 7] + K3, 9); -+ ROUND(H, c, d, a, b, in[11] + K3, 11); -+ ROUND(H, b, c, d, a, in[ 2] + K3, 15); -+ ROUND(H, a, b, c, d, in[ 6] + K3, 3); -+ ROUND(H, d, a, b, c, in[10] + K3, 9); -+ ROUND(H, c, d, a, b, in[ 1] + K3, 11); -+ ROUND(H, b, c, d, a, in[ 5] + K3, 15); -+ ROUND(H, a, b, c, d, in[ 9] + K3, 3); -+ ROUND(H, d, a, b, c, in[ 0] + K3, 9); -+ ROUND(H, c, d, a, b, in[ 4] + K3, 11); -+ ROUND(H, b, c, d, a, in[ 8] + K3, 15); -+ -+ return buf[1] + b; /* "most hashed" word */ -+ /* Alternative: return sum of all words? */ -+} -+#endif -+ -+#undef ROUND -+#undef F -+#undef G -+#undef H -+#undef K1 -+#undef K2 -+#undef K3 -+ -+/* This should not be decreased so low that ISNs wrap too fast. */ -+#define REKEY_INTERVAL (300 * HZ) -+/* -+ * Bit layout of the tcp sequence numbers (before adding current time): -+ * bit 24-31: increased after every key exchange -+ * bit 0-23: hash(source,dest) -+ * -+ * The implementation is similar to the algorithm described -+ * in the Appendix of RFC 1185, except that -+ * - it uses a 1 MHz clock instead of a 250 kHz clock -+ * - it performs a rekey every 5 minutes, which is equivalent -+ * to a (source,dest) tulple dependent forward jump of the -+ * clock by 0..2^(HASH_BITS+1) -+ * -+ * Thus the average ISN wraparound time is 68 minutes instead of -+ * 4.55 hours. -+ * -+ * SMP cleanup and lock avoidance with poor man's RCU. -+ * Manfred Spraul -+ * -+ */ -+#define COUNT_BITS 8 -+#define COUNT_MASK ((1 << COUNT_BITS) - 1) -+#define HASH_BITS 24 -+#define HASH_MASK ((1 << HASH_BITS) - 1) -+ -+static struct keydata { -+ __u32 count; /* already shifted to the final position */ -+ __u32 secret[12]; -+} ____cacheline_aligned ip_keydata[2]; -+ -+static unsigned int ip_cnt; -+ -+static void rekey_seq_generator(struct work_struct *work); -+ -+static DECLARE_DELAYED_WORK(rekey_work, rekey_seq_generator); -+ -+/* -+ * Lock avoidance: -+ * The ISN generation runs lockless - it's just a hash over random data. -+ * State changes happen every 5 minutes when the random key is replaced. -+ * Synchronization is performed by having two copies of the hash function -+ * state and rekey_seq_generator always updates the inactive copy. -+ * The copy is then activated by updating ip_cnt. -+ * The implementation breaks down if someone blocks the thread -+ * that processes SYN requests for more than 5 minutes. Should never -+ * happen, and even if that happens only a not perfectly compliant -+ * ISN is generated, nothing fatal. -+ */ -+static void rekey_seq_generator(struct work_struct *work) -+{ -+ struct keydata *keyptr = &ip_keydata[1 ^ (ip_cnt & 1)]; -+ -+ get_random_bytes(keyptr->secret, sizeof(keyptr->secret)); -+ keyptr->count = (ip_cnt & COUNT_MASK) << HASH_BITS; -+ smp_wmb(); -+ ip_cnt++; -+ schedule_delayed_work(&rekey_work, -+ round_jiffies_relative(REKEY_INTERVAL)); -+} -+ -+static inline struct keydata *get_keyptr(void) -+{ -+ struct keydata *keyptr = &ip_keydata[ip_cnt & 1]; -+ -+ smp_rmb(); -+ -+ return keyptr; -+} -+ -+static __init int seqgen_init(void) -+{ -+ rekey_seq_generator(NULL); -+ return 0; -+} -+late_initcall(seqgen_init); -+ -+#if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE) -+__u32 secure_tcpv6_sequence_number(__be32 *saddr, __be32 *daddr, -+ __be16 sport, __be16 dport) -+{ -+ __u32 seq; -+ __u32 hash[12]; -+ struct keydata *keyptr = get_keyptr(); -+ -+ /* The procedure is the same as for IPv4, but addresses are longer. -+ * Thus we must use twothirdsMD4Transform. -+ */ -+ -+ memcpy(hash, saddr, 16); -+ hash[4] = ((__force u16)sport << 16) + (__force u16)dport; -+ memcpy(&hash[5], keyptr->secret, sizeof(__u32) * 7); -+ -+ seq = twothirdsMD4Transform((const __u32 *)daddr, hash) & HASH_MASK; -+ seq += keyptr->count; -+ -+ seq += ktime_to_ns(ktime_get_real()); -+ -+ return seq; -+} -+EXPORT_SYMBOL(secure_tcpv6_sequence_number); -+#endif -+ -+/* The code below is shamelessly stolen from secure_tcp_sequence_number(). -+ * All blames to Andrey V. Savochkin . -+ */ -+__u32 secure_ip_id(__be32 daddr) -+{ -+ struct keydata *keyptr; -+ __u32 hash[4]; -+ -+ keyptr = get_keyptr(); -+ -+ /* -+ * Pick a unique starting offset for each IP destination. -+ * The dest ip address is placed in the starting vector, -+ * which is then hashed with random data. -+ */ -+ hash[0] = (__force __u32)daddr; -+ hash[1] = keyptr->secret[9]; -+ hash[2] = keyptr->secret[10]; -+ hash[3] = keyptr->secret[11]; -+ -+ return half_md4_transform(hash, keyptr->secret); -+} -+ -+#ifdef CONFIG_INET -+ -+__u32 secure_tcp_sequence_number(__be32 saddr, __be32 daddr, -+ __be16 sport, __be16 dport) -+{ -+ __u32 seq; -+ __u32 hash[4]; -+ struct keydata *keyptr = get_keyptr(); -+ -+ /* -+ * Pick a unique starting offset for each TCP connection endpoints -+ * (saddr, daddr, sport, dport). -+ * Note that the words are placed into the starting vector, which is -+ * then mixed with a partial MD4 over random data. -+ */ -+ hash[0] = (__force u32)saddr; -+ hash[1] = (__force u32)daddr; -+ hash[2] = ((__force u16)sport << 16) + (__force u16)dport; -+ hash[3] = keyptr->secret[11]; -+ -+ seq = half_md4_transform(hash, keyptr->secret) & HASH_MASK; -+ seq += keyptr->count; -+ /* -+ * As close as possible to RFC 793, which -+ * suggests using a 250 kHz clock. -+ * Further reading shows this assumes 2 Mb/s networks. -+ * For 10 Mb/s Ethernet, a 1 MHz clock is appropriate. -+ * For 10 Gb/s Ethernet, a 1 GHz clock should be ok, but -+ * we also need to limit the resolution so that the u32 seq -+ * overlaps less than one time per MSL (2 minutes). -+ * Choosing a clock of 64 ns period is OK. (period of 274 s) -+ */ -+ seq += ktime_to_ns(ktime_get_real()) >> 6; -+ -+ return seq; -+} -+ -+/* Generate secure starting point for ephemeral IPV4 transport port search */ -+u32 secure_ipv4_port_ephemeral(__be32 saddr, __be32 daddr, __be16 dport) -+{ -+ struct keydata *keyptr = get_keyptr(); -+ u32 hash[4]; -+ -+ /* -+ * Pick a unique starting offset for each ephemeral port search -+ * (saddr, daddr, dport) and 48bits of random data. -+ */ -+ hash[0] = (__force u32)saddr; -+ hash[1] = (__force u32)daddr; -+ hash[2] = (__force u32)dport ^ keyptr->secret[10]; -+ hash[3] = keyptr->secret[11]; -+ -+ return half_md4_transform(hash, keyptr->secret); -+} -+EXPORT_SYMBOL_GPL(secure_ipv4_port_ephemeral); -+ -+#if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE) -+u32 secure_ipv6_port_ephemeral(const __be32 *saddr, const __be32 *daddr, -+ __be16 dport) -+{ -+ struct keydata *keyptr = get_keyptr(); -+ u32 hash[12]; -+ -+ memcpy(hash, saddr, 16); -+ hash[4] = (__force u32)dport; -+ memcpy(&hash[5], keyptr->secret, sizeof(__u32) * 7); -+ -+ return twothirdsMD4Transform((const __u32 *)daddr, hash); -+} -+#endif -+ -+#if defined(CONFIG_IP_DCCP) || defined(CONFIG_IP_DCCP_MODULE) -+/* Similar to secure_tcp_sequence_number but generate a 48 bit value -+ * bit's 32-47 increase every key exchange -+ * 0-31 hash(source, dest) -+ */ -+u64 secure_dccp_sequence_number(__be32 saddr, __be32 daddr, -+ __be16 sport, __be16 dport) -+{ -+ u64 seq; -+ __u32 hash[4]; -+ struct keydata *keyptr = get_keyptr(); -+ -+ hash[0] = (__force u32)saddr; -+ hash[1] = (__force u32)daddr; -+ hash[2] = ((__force u16)sport << 16) + (__force u16)dport; -+ hash[3] = keyptr->secret[11]; -+ -+ seq = half_md4_transform(hash, keyptr->secret); -+ seq |= ((u64)keyptr->count) << (32 - HASH_BITS); -+ -+ seq += ktime_to_ns(ktime_get_real()); -+ seq &= (1ull << 48) - 1; -+ -+ return seq; -+} -+EXPORT_SYMBOL(secure_dccp_sequence_number); -+#endif -+ -+#endif /* CONFIG_INET */ -+ -+ -+/* -+ * Get a random word for internal kernel use only. Similar to urandom but -+ * with the goal of minimal entropy pool depletion. As a result, the random -+ * value is not cryptographically secure but for several uses the cost of -+ * depleting entropy is too high -+ */ -+DEFINE_PER_CPU(__u32 [4], get_random_int_hash); -+unsigned int get_random_int(void) -+{ -+ struct keydata *keyptr; -+ __u32 *hash = get_cpu_var(get_random_int_hash); -+ int ret; -+ -+ keyptr = get_keyptr(); -+ hash[0] += current->pid + jiffies + get_cycles(); -+ -+ ret = half_md4_transform(hash, keyptr->secret); -+ put_cpu_var(get_random_int_hash); -+ -+ return ret; -+} -+ -+/* -+ * randomize_range() returns a start address such that -+ * -+ * [...... .....] -+ * start end -+ * -+ * a with size "len" starting at the return value is inside in the -+ * area defined by [start, end], but is otherwise randomized. -+ */ -+unsigned long -+randomize_range(unsigned long start, unsigned long end, unsigned long len) -+{ -+ unsigned long range = end - len - start; -+ -+ if (end <= start + len) -+ return 0; -+ return PAGE_ALIGN(get_random_int() % range + start); -+} -diff -Nur linux-2.6.39.orig/fs/fcntl.c linux-2.6.39/fs/fcntl.c ---- linux-2.6.39.orig/fs/fcntl.c 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/fs/fcntl.c 2011-08-01 14:38:19.000000000 +0200 -@@ -142,6 +142,7 @@ - } - return ret; - } -+EXPORT_SYMBOL(sys_dup); - - #define SETFL_MASK (O_APPEND | O_NONBLOCK | O_NDELAY | O_DIRECT | O_NOATIME) - -diff -Nur linux-2.6.39.orig/include/linux/miscdevice.h linux-2.6.39/include/linux/miscdevice.h ---- linux-2.6.39.orig/include/linux/miscdevice.h 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/include/linux/miscdevice.h 2011-08-01 14:38:19.000000000 +0200 -@@ -18,6 +18,7 @@ - #define APOLLO_MOUSE_MINOR 7 - #define PC110PAD_MINOR 9 - /*#define ADB_MOUSE_MINOR 10 FIXME OBSOLETE */ -+#define CRYPTODEV_MINOR 70 /* /dev/crypto */ - #define WATCHDOG_MINOR 130 /* Watchdog timer */ - #define TEMP_MINOR 131 /* Temperature Sensor */ - #define RTC_MINOR 135 -diff -Nur linux-2.6.39.orig/include/linux/random.h linux-2.6.39/include/linux/random.h ---- linux-2.6.39.orig/include/linux/random.h 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/include/linux/random.h 2011-08-01 14:38:19.000000000 +0200 -@@ -9,6 +9,7 @@ - - #include - #include -+#include /* for __u32 in user space */ - #include - - /* ioctl()'s for the random number generator */ -@@ -34,6 +35,30 @@ - /* Clear the entropy pool and associated counters. (Superuser only.) */ - #define RNDCLEARPOOL _IO( 'R', 0x06 ) - -+#ifdef CONFIG_FIPS_RNG -+ -+/* Size of seed value - equal to AES blocksize */ -+#define AES_BLOCK_SIZE_BYTES 16 -+#define SEED_SIZE_BYTES AES_BLOCK_SIZE_BYTES -+/* Size of AES key */ -+#define KEY_SIZE_BYTES 16 -+ -+/* ioctl() structure used by FIPS 140-2 Tests */ -+struct rand_fips_test { -+ unsigned char key[KEY_SIZE_BYTES]; /* Input */ -+ unsigned char datetime[SEED_SIZE_BYTES]; /* Input */ -+ unsigned char seed[SEED_SIZE_BYTES]; /* Input */ -+ unsigned char result[SEED_SIZE_BYTES]; /* Output */ -+}; -+ -+/* FIPS 140-2 RNG Variable Seed Test. (Superuser only.) */ -+#define RNDFIPSVST _IOWR('R', 0x10, struct rand_fips_test) -+ -+/* FIPS 140-2 RNG Monte Carlo Test. (Superuser only.) */ -+#define RNDFIPSMCT _IOWR('R', 0x11, struct rand_fips_test) -+ -+#endif /* #ifdef CONFIG_FIPS_RNG */ -+ - struct rand_pool_info { - int entropy_count; - int buf_size; -@@ -54,6 +79,10 @@ - unsigned int value); - extern void add_interrupt_randomness(int irq); - -+extern void random_input_words(__u32 *buf, size_t wordcount, int ent_count); -+extern int random_input_wait(void); -+#define HAS_RANDOM_INPUT_WAIT 1 -+ - extern void get_random_bytes(void *buf, int nbytes); - void generate_random_uuid(unsigned char uuid_out[16]); - diff --git a/target/linux/patches/2.6.39/rb4xx.patch b/target/linux/patches/2.6.39/rb4xx.patch deleted file mode 100644 index 4f2e1cd84..000000000 --- a/target/linux/patches/2.6.39/rb4xx.patch +++ /dev/null @@ -1,25253 +0,0 @@ -diff -Nur linux-2.6.39.orig/arch/mips/Kconfig linux-2.6.39/arch/mips/Kconfig ---- linux-2.6.39.orig/arch/mips/Kconfig 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/arch/mips/Kconfig 2011-08-24 18:17:24.000000000 +0200 -@@ -84,6 +84,23 @@ - help - Support for the Atheros AR71XX/AR724X/AR913X SoCs. - -+config ATHEROS_AR71XX -+ bool "Atheros AR71xx based boards" -+ select CEVT_R4K -+ select CSRC_R4K -+ select DMA_NONCOHERENT -+ select HW_HAS_PCI -+ select IRQ_CPU -+ select ARCH_REQUIRE_GPIOLIB -+ select SYS_HAS_CPU_MIPS32_R1 -+ select SYS_HAS_CPU_MIPS32_R2 -+ select SYS_SUPPORTS_32BIT_KERNEL -+ select SYS_SUPPORTS_BIG_ENDIAN -+ select SYS_HAS_EARLY_PRINTK -+ select MIPS_MACHINE -+ help -+ Support for Atheros AR71xx based boards. -+ - config BCM47XX - bool "Broadcom BCM47XX based boards" - select CEVT_R4K -@@ -739,6 +756,7 @@ - endchoice - - source "arch/mips/alchemy/Kconfig" -+source "arch/mips/ar71xx/Kconfig" - source "arch/mips/ath79/Kconfig" - source "arch/mips/bcm63xx/Kconfig" - source "arch/mips/jazz/Kconfig" -@@ -907,6 +925,9 @@ - config MIPS_DISABLE_OBSOLETE_IDE - bool - -+config MYLOADER -+ bool -+ - config SYNC_R4K - bool - -diff -Nur linux-2.6.39.orig/arch/mips/Makefile linux-2.6.39/arch/mips/Makefile ---- linux-2.6.39.orig/arch/mips/Makefile 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/arch/mips/Makefile 2011-08-24 18:17:24.000000000 +0200 -@@ -158,6 +158,13 @@ - endif - cflags-$(CONFIG_CAVIUM_CN63XXP1) += -Wa,-mfix-cn63xxp1 - -+# -+# Atheros AR71xx -+# -+core-$(CONFIG_ATHEROS_AR71XX) += arch/mips/ar71xx/ -+cflags-$(CONFIG_ATHEROS_AR71XX) += -I$(srctree)/arch/mips/include/asm/mach-ar71xx -+load-$(CONFIG_ATHEROS_AR71XX) += 0xffffffff80060000 -+ - cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,) - cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += $(call cc-option,-mfix-r4400,) - cflags-$(CONFIG_CPU_DADDI_WORKAROUNDS) += $(call cc-option,-mno-daddi,) -@@ -174,6 +181,7 @@ - # - libs-$(CONFIG_ARC) += arch/mips/fw/arc/ - libs-$(CONFIG_CFE) += arch/mips/fw/cfe/ -+libs-$(CONFIG_MYLOADER) += arch/mips/fw/myloader/ - libs-$(CONFIG_SNIPROM) += arch/mips/fw/sni/ - libs-y += arch/mips/fw/lib/ - -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/Kconfig linux-2.6.39/arch/mips/ar71xx/Kconfig ---- linux-2.6.39.orig/arch/mips/ar71xx/Kconfig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/Kconfig 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,420 @@ -+if ATHEROS_AR71XX -+ -+menu "Atheros AR71xx machine selection" -+ -+config AR71XX_MACH_AP81 -+ bool "Atheros AP81 board support" -+ select SOC_AR913X -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AR9XXX_WMAC -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ default n -+ -+config AR71XX_MACH_AP83 -+ bool "Atheros AP83 board support" -+ select SOC_AR913X -+ select AR71XX_DEV_AR9XXX_WMAC -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ default n -+ -+config AR71XX_MACH_AP96 -+ bool "Atheros AP96 board support" -+ select SOC_AR71XX -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AP94_PCI if PCI -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ default n -+ -+config AR71XX_MACH_AP121 -+ bool "Atheros AP121 board support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ select AR71XX_DEV_AR9XXX_WMAC -+ select SOC_AR933X -+ default n -+ -+config AR71XX_MACH_DB120 -+ bool "Atheros DB120 board support" -+ select SOC_AR934X -+ select AR71XX_DEV_AR9XXX_WMAC -+ select AR71XX_DEV_DB120_PCI if PCI -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ default n -+ -+config AR71XX_MACH_DIR_600_A1 -+ bool "D-Link DIR-600 rev. A1 support" -+ select SOC_AR724X -+ select AR71XX_DEV_AP91_PCI if PCI -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_NVRAM -+ default n -+ -+config AR71XX_MACH_DIR_615_C1 -+ bool "D-Link DIR-615 rev. C1 support" -+ select SOC_AR913X -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AR9XXX_WMAC -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_NVRAM -+ default n -+ -+config AR71XX_MACH_DIR_825_B1 -+ bool "D-Link DIR-825 rev. B1 board support" -+ select SOC_AR71XX -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AP94_PCI if PCI -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ default n -+ -+config AR71XX_MACH_JA76PF -+ bool "jjPlus JA76PF board support" -+ select SOC_AR71XX -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_PB42_PCI if PCI -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ default n -+ -+config AR71XX_MACH_JWAP003 -+ bool "jjPlus JWAP003 board support" -+ select SOC_AR71XX -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_PB42_PCI if PCI -+ select AR71XX_DEV_USB -+ default n -+ -+config AR71XX_MACH_PB42 -+ bool "Atheros PB42 board support" -+ select SOC_AR71XX -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_PB42_PCI if PCI -+ default n -+ -+config AR71XX_MACH_PB44 -+ bool "Atheros PB44 board support" -+ select SOC_AR71XX -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_PB42_PCI if PCI -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ default n -+ -+config AR71XX_MACH_PB92 -+ bool "Atheros PB92 board support" -+ select SOC_AR724X -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_PB9X_PCI if PCI -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ default n -+ -+config AR71XX_MACH_AW_NR580 -+ bool "AzureWave AW-NR580 board support" -+ select SOC_AR71XX -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_PB42_PCI if PCI -+ select AR71XX_DEV_LEDS_GPIO -+ default n -+ -+config AR71XX_MACH_WZR_HP_AG300H -+ bool "Buffalo WZR-HP-AG300H board support" -+ select SOC_AR71XX -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ default n -+ -+config AR71XX_MACH_WZR_HP_G300NH -+ bool "Buffalo WZR-HP-G300NH board support" -+ select SOC_AR913X -+ select AR71XX_DEV_AR9XXX_WMAC -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ select RTL8366_SMI -+ default n -+ -+config AR71XX_MACH_WP543 -+ bool "Compex WP543/WPJ543 board support" -+ select SOC_AR71XX -+ select MYLOADER -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_PB42_PCI if PCI -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ default n -+ -+config AR71XX_MACH_WRT160NL -+ bool "Linksys WRT160NL board support" -+ select SOC_AR913X -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AR9XXX_WMAC -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ select AR71XX_NVRAM -+ default n -+ -+config AR71XX_MACH_WRT400N -+ bool "Linksys WRT400N board support" -+ select SOC_AR71XX -+ select AR71XX_DEV_AP94_PCI if PCI -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ default n -+ -+config AR71XX_MACH_RB4XX -+ bool "MikroTik RouterBOARD 4xx series support" -+ select SOC_AR71XX -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ default n -+ -+config AR71XX_MACH_RB750 -+ bool "MikroTik RouterBOARD 750 support" -+ select SOC_AR724X -+ default n -+ -+config AR71XX_MACH_WNDR3700 -+ bool "NETGEAR WNDR3700 board support" -+ select SOC_AR71XX -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AP94_PCI if PCI -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ default n -+ -+config AR71XX_MACH_WNR2000 -+ bool "NETGEAR WNR2000 board support" -+ select SOC_AR913X -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AR9XXX_WMAC -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ default n -+ -+config AR71XX_MACH_MZK_W04NU -+ bool "Planex MZK-W04NU board support" -+ select SOC_AR913X -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AR9XXX_WMAC -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ default n -+ -+config AR71XX_MACH_MZK_W300NH -+ bool "Planex MZK-W300NH board support" -+ select SOC_AR913X -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AR9XXX_WMAC -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ default n -+ -+config AR71XX_MACH_NBG460N -+ bool "Zyxel NBG460N/550N/550NH board support" -+ select SOC_AR913X -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AR9XXX_WMAC -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ default n -+ -+config AR71XX_MACH_TL_MR3X20 -+ bool "TP-LINK TL-MR3220/3420 support" -+ select SOC_AR724X -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AP91_PCI if PCI -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ default n -+ -+config AR71XX_MACH_TL_WA901ND -+ bool "TP-LINK TL-WA901ND support" -+ select SOC_AR724X -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AP91_PCI if PCI -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ default n -+ -+config AR71XX_MACH_TL_WA901ND_V2 -+ bool "TP-LINK TL-WA901ND v2 support" -+ select SOC_AR913X -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AR9XXX_WMAC -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ default n -+ -+config AR71XX_MACH_TL_WR741ND -+ bool "TP-LINK TL-WR741ND support" -+ select SOC_AR724X -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AP91_PCI if PCI -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ default n -+ -+config AR71XX_MACH_TL_WR841N_V1 -+ bool "TP-LINK TL-WR841N v1 support" -+ select SOC_AR71XX -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_PB42_PCI if PCI -+ select AR71XX_DEV_DSA -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ default n -+ -+config AR71XX_MACH_TL_WR941ND -+ bool "TP-LINK TL-WR941ND support" -+ select SOC_AR913X -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AR9XXX_WMAC -+ select AR71XX_DEV_DSA -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ default n -+ -+config AR71XX_MACH_TL_WR1043ND -+ bool "TP-LINK TL-WR1043ND support" -+ select SOC_AR913X -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AR9XXX_WMAC -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ default n -+ -+config AR71XX_MACH_TEW_632BRP -+ bool "TRENDnet TEW-632BRP support" -+ select SOC_AR913X -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AR9XXX_WMAC -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_NVRAM -+ default n -+ -+config AR71XX_MACH_UBNT -+ bool "Ubiquiti AR71xx based boards support" -+ select SOC_AR71XX -+ select SOC_AR724X -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AP91_PCI if PCI -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_PB42_PCI if PCI -+ select AR71XX_DEV_USB -+ default n -+ -+config AR71XX_MACH_EAP7660D -+ bool "Senao EAP7660D support" -+ select SOC_AR71XX -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ default n -+ -+config AR71XX_MACH_ZCN_1523H -+ bool "Zcomax ZCN-1523H support" -+ select SOC_AR724X -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AP91_PCI if PCI -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ default n -+ -+endmenu -+ -+config SOC_AR71XX -+ bool -+ select USB_ARCH_HAS_EHCI -+ select USB_ARCH_HAS_OHCI -+ -+config SOC_AR724X -+ bool -+ select USB_ARCH_HAS_EHCI -+ select USB_ARCH_HAS_OHCI -+ -+config SOC_AR913X -+ bool -+ select USB_ARCH_HAS_EHCI -+ -+config SOC_AR934X -+ bool -+ select USB_ARCH_HAS_EHCI -+ -+config AR71XX_DEV_M25P80 -+ def_bool n -+ -+config AR71XX_DEV_AP91_PCI -+ select AR71XX_PCI_ATH9K_FIXUP -+ def_bool n -+ -+config AR71XX_DEV_AP94_PCI -+ select AR71XX_PCI_ATH9K_FIXUP -+ def_bool n -+ -+config AR71XX_DEV_AR9XXX_WMAC -+ def_bool n -+ -+config AR71XX_DEV_DB120_PCI -+ select AR71XX_PCI_ATH9K_FIXUP -+ def_bool n -+ -+config AR71XX_DEV_DSA -+ def_bool n -+ -+config AR71XX_DEV_GPIO_BUTTONS -+ def_bool n -+ -+config AR71XX_DEV_LEDS_GPIO -+ def_bool n -+ -+config AR71XX_DEV_PB42_PCI -+ def_bool n -+ -+config AR71XX_DEV_PB9X_PCI -+ def_bool n -+ -+config AR71XX_DEV_USB -+ def_bool n -+ -+config AR71XX_NVRAM -+ def_bool n -+ -+config AR71XX_PCI_ATH9K_FIXUP -+ def_bool n -+ -+config SOC_AR933X -+ bool -+ select USB_ARCH_HAS_EHCI -+ -+endif -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/Makefile linux-2.6.39/arch/mips/ar71xx/Makefile ---- linux-2.6.39.orig/arch/mips/ar71xx/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/Makefile 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,67 @@ -+# -+# Makefile for the Atheros AR71xx SoC specific parts of the kernel -+# -+# Copyright (C) 2008-2009 Gabor Juhos -+# Copyright (C) 2008 Imre Kaloz -+# -+# This program is free software; you can redistribute it and/or modify it -+# under the terms of the GNU General Public License version 2 as published -+# by the Free Software Foundation. -+ -+obj-y := prom.o irq.o setup.o devices.o gpio.o ar71xx.o -+ -+obj-$(CONFIG_EARLY_PRINTK) += early_printk.o -+obj-$(CONFIG_PCI) += pci.o -+ -+obj-$(CONFIG_AR71XX_DEV_AP91_PCI) += dev-ap91-pci.o -+obj-$(CONFIG_AR71XX_DEV_AP94_PCI) += dev-ap94-pci.o -+obj-$(CONFIG_AR71XX_DEV_AR9XXX_WMAC) += dev-ar9xxx-wmac.o -+obj-$(CONFIG_AR71XX_DEV_DB120_PCI) += dev-db120-pci.o -+obj-$(CONFIG_AR71XX_DEV_DSA) += dev-dsa.o -+obj-$(CONFIG_AR71XX_DEV_GPIO_BUTTONS) += dev-gpio-buttons.o -+obj-$(CONFIG_AR71XX_DEV_LEDS_GPIO) += dev-leds-gpio.o -+obj-$(CONFIG_AR71XX_DEV_M25P80) += dev-m25p80.o -+obj-$(CONFIG_AR71XX_DEV_PB42_PCI) += dev-pb42-pci.o -+obj-$(CONFIG_AR71XX_DEV_PB9X_PCI) += dev-pb9x-pci.o -+obj-$(CONFIG_AR71XX_DEV_USB) += dev-usb.o -+ -+obj-$(CONFIG_AR71XX_NVRAM) += nvram.o -+obj-$(CONFIG_AR71XX_PCI_ATH9K_FIXUP) += pci-ath9k-fixup.o -+ -+obj-$(CONFIG_AR71XX_MACH_AP121) += mach-ap121.o -+obj-$(CONFIG_AR71XX_MACH_AP81) += mach-ap81.o -+obj-$(CONFIG_AR71XX_MACH_AP83) += mach-ap83.o -+obj-$(CONFIG_AR71XX_MACH_AP96) += mach-ap96.o -+obj-$(CONFIG_AR71XX_MACH_AW_NR580) += mach-aw-nr580.o -+obj-$(CONFIG_AR71XX_MACH_DB120) += mach-db120.o -+obj-$(CONFIG_AR71XX_MACH_DIR_600_A1) += mach-dir-600-a1.o -+obj-$(CONFIG_AR71XX_MACH_DIR_615_C1) += mach-dir-615-c1.o -+obj-$(CONFIG_AR71XX_MACH_DIR_825_B1) += mach-dir-825-b1.o -+obj-$(CONFIG_AR71XX_MACH_EAP7660D) += mach-eap7660d.o -+obj-$(CONFIG_AR71XX_MACH_JA76PF) += mach-ja76pf.o -+obj-$(CONFIG_AR71XX_MACH_JWAP003) += mach-jwap003.o -+obj-$(CONFIG_AR71XX_MACH_MZK_W04NU) += mach-mzk-w04nu.o -+obj-$(CONFIG_AR71XX_MACH_MZK_W300NH) += mach-mzk-w300nh.o -+obj-$(CONFIG_AR71XX_MACH_NBG460N) += mach-nbg460n.o -+obj-$(CONFIG_AR71XX_MACH_PB42) += mach-pb42.o -+obj-$(CONFIG_AR71XX_MACH_PB44) += mach-pb44.o -+obj-$(CONFIG_AR71XX_MACH_PB92) += mach-pb92.o -+obj-$(CONFIG_AR71XX_MACH_RB4XX) += mach-rb4xx.o -+obj-$(CONFIG_AR71XX_MACH_RB750) += mach-rb750.o -+obj-$(CONFIG_AR71XX_MACH_TEW_632BRP) += mach-tew-632brp.o -+obj-$(CONFIG_AR71XX_MACH_TL_MR3X20) += mach-tl-mr3x20.o -+obj-$(CONFIG_AR71XX_MACH_TL_WA901ND) += mach-tl-wa901nd.o -+obj-$(CONFIG_AR71XX_MACH_TL_WA901ND_V2) += mach-tl-wa901nd-v2.o -+obj-$(CONFIG_AR71XX_MACH_TL_WR741ND) += mach-tl-wr741nd.o -+obj-$(CONFIG_AR71XX_MACH_TL_WR841N_V1) += mach-tl-wr841n.o -+obj-$(CONFIG_AR71XX_MACH_TL_WR941ND) += mach-tl-wr941nd.o -+obj-$(CONFIG_AR71XX_MACH_TL_WR1043ND) += mach-tl-wr1043nd.o -+obj-$(CONFIG_AR71XX_MACH_UBNT) += mach-ubnt.o -+obj-$(CONFIG_AR71XX_MACH_WNDR3700) += mach-wndr3700.o -+obj-$(CONFIG_AR71XX_MACH_WNR2000) += mach-wnr2000.o -+obj-$(CONFIG_AR71XX_MACH_WP543) += mach-wp543.o -+obj-$(CONFIG_AR71XX_MACH_WRT160NL) += mach-wrt160nl.o -+obj-$(CONFIG_AR71XX_MACH_WRT400N) += mach-wrt400n.o -+obj-$(CONFIG_AR71XX_MACH_WZR_HP_G300NH) += mach-wzr-hp-g300nh.o -+obj-$(CONFIG_AR71XX_MACH_WZR_HP_AG300H) += mach-wzr-hp-ag300h.o -+obj-$(CONFIG_AR71XX_MACH_ZCN_1523H) += mach-zcn-1523h.o -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/ar71xx.c linux-2.6.39/arch/mips/ar71xx/ar71xx.c ---- linux-2.6.39.orig/arch/mips/ar71xx/ar71xx.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/ar71xx.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,230 @@ -+/* -+ * AR71xx SoC routines -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+static DEFINE_MUTEX(ar71xx_flash_mutex); -+static DEFINE_SPINLOCK(ar71xx_device_lock); -+ -+void __iomem *ar71xx_ddr_base; -+EXPORT_SYMBOL_GPL(ar71xx_ddr_base); -+ -+void __iomem *ar71xx_pll_base; -+EXPORT_SYMBOL_GPL(ar71xx_pll_base); -+ -+void __iomem *ar71xx_reset_base; -+EXPORT_SYMBOL_GPL(ar71xx_reset_base); -+ -+void __iomem *ar71xx_gpio_base; -+EXPORT_SYMBOL_GPL(ar71xx_gpio_base); -+ -+void __iomem *ar71xx_usb_ctrl_base; -+EXPORT_SYMBOL_GPL(ar71xx_usb_ctrl_base); -+ -+void ar71xx_device_stop(u32 mask) -+{ -+ unsigned long flags; -+ u32 mask_inv; -+ u32 t; -+ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7130: -+ case AR71XX_SOC_AR7141: -+ case AR71XX_SOC_AR7161: -+ spin_lock_irqsave(&ar71xx_device_lock, flags); -+ t = ar71xx_reset_rr(AR71XX_RESET_REG_RESET_MODULE); -+ ar71xx_reset_wr(AR71XX_RESET_REG_RESET_MODULE, t | mask); -+ spin_unlock_irqrestore(&ar71xx_device_lock, flags); -+ break; -+ -+ case AR71XX_SOC_AR7240: -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ mask_inv = mask & RESET_MODULE_USB_OHCI_DLL_7240; -+ spin_lock_irqsave(&ar71xx_device_lock, flags); -+ t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE); -+ t |= mask; -+ t &= ~mask_inv; -+ ar71xx_reset_wr(AR724X_RESET_REG_RESET_MODULE, t); -+ spin_unlock_irqrestore(&ar71xx_device_lock, flags); -+ break; -+ -+ case AR71XX_SOC_AR9130: -+ case AR71XX_SOC_AR9132: -+ spin_lock_irqsave(&ar71xx_device_lock, flags); -+ t = ar71xx_reset_rr(AR91XX_RESET_REG_RESET_MODULE); -+ ar71xx_reset_wr(AR91XX_RESET_REG_RESET_MODULE, t | mask); -+ spin_unlock_irqrestore(&ar71xx_device_lock, flags); -+ break; -+ -+ case AR71XX_SOC_AR9330: -+ case AR71XX_SOC_AR9331: -+ spin_lock_irqsave(&ar71xx_device_lock, flags); -+ t = ar71xx_reset_rr(AR933X_RESET_REG_RESET_MODULE); -+ ar71xx_reset_wr(AR933X_RESET_REG_RESET_MODULE, t | mask); -+ spin_unlock_irqrestore(&ar71xx_device_lock, flags); -+ break; -+ -+ case AR71XX_SOC_AR9341: -+ case AR71XX_SOC_AR9342: -+ case AR71XX_SOC_AR9344: -+ spin_lock_irqsave(&ar71xx_device_lock, flags); -+ t = ar71xx_reset_rr(AR934X_RESET_REG_RESET_MODULE); -+ ar71xx_reset_wr(AR934X_RESET_REG_RESET_MODULE, t | mask); -+ spin_unlock_irqrestore(&ar71xx_device_lock, flags); -+ break; -+ -+ default: -+ BUG(); -+ } -+} -+EXPORT_SYMBOL_GPL(ar71xx_device_stop); -+ -+void ar71xx_device_start(u32 mask) -+{ -+ unsigned long flags; -+ u32 mask_inv; -+ u32 t; -+ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7130: -+ case AR71XX_SOC_AR7141: -+ case AR71XX_SOC_AR7161: -+ spin_lock_irqsave(&ar71xx_device_lock, flags); -+ t = ar71xx_reset_rr(AR71XX_RESET_REG_RESET_MODULE); -+ ar71xx_reset_wr(AR71XX_RESET_REG_RESET_MODULE, t & ~mask); -+ spin_unlock_irqrestore(&ar71xx_device_lock, flags); -+ break; -+ -+ case AR71XX_SOC_AR7240: -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ mask_inv = mask & RESET_MODULE_USB_OHCI_DLL_7240; -+ spin_lock_irqsave(&ar71xx_device_lock, flags); -+ t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE); -+ t &= ~mask; -+ t |= mask_inv; -+ ar71xx_reset_wr(AR724X_RESET_REG_RESET_MODULE, t); -+ spin_unlock_irqrestore(&ar71xx_device_lock, flags); -+ break; -+ -+ case AR71XX_SOC_AR9130: -+ case AR71XX_SOC_AR9132: -+ spin_lock_irqsave(&ar71xx_device_lock, flags); -+ t = ar71xx_reset_rr(AR91XX_RESET_REG_RESET_MODULE); -+ ar71xx_reset_wr(AR91XX_RESET_REG_RESET_MODULE, t & ~mask); -+ spin_unlock_irqrestore(&ar71xx_device_lock, flags); -+ break; -+ -+ case AR71XX_SOC_AR9330: -+ case AR71XX_SOC_AR9331: -+ spin_lock_irqsave(&ar71xx_device_lock, flags); -+ t = ar71xx_reset_rr(AR933X_RESET_REG_RESET_MODULE); -+ ar71xx_reset_wr(AR933X_RESET_REG_RESET_MODULE, t & ~mask); -+ spin_unlock_irqrestore(&ar71xx_device_lock, flags); -+ break; -+ -+ case AR71XX_SOC_AR9341: -+ case AR71XX_SOC_AR9342: -+ case AR71XX_SOC_AR9344: -+ spin_lock_irqsave(&ar71xx_device_lock, flags); -+ t = ar71xx_reset_rr(AR934X_RESET_REG_RESET_MODULE); -+ ar71xx_reset_wr(AR934X_RESET_REG_RESET_MODULE, t & ~mask); -+ spin_unlock_irqrestore(&ar71xx_device_lock, flags); -+ break; -+ -+ default: -+ BUG(); -+ } -+} -+EXPORT_SYMBOL_GPL(ar71xx_device_start); -+ -+int ar71xx_device_stopped(u32 mask) -+{ -+ unsigned long flags; -+ u32 t; -+ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7130: -+ case AR71XX_SOC_AR7141: -+ case AR71XX_SOC_AR7161: -+ spin_lock_irqsave(&ar71xx_device_lock, flags); -+ t = ar71xx_reset_rr(AR71XX_RESET_REG_RESET_MODULE); -+ spin_unlock_irqrestore(&ar71xx_device_lock, flags); -+ break; -+ -+ case AR71XX_SOC_AR7240: -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ spin_lock_irqsave(&ar71xx_device_lock, flags); -+ t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE); -+ spin_unlock_irqrestore(&ar71xx_device_lock, flags); -+ break; -+ -+ case AR71XX_SOC_AR9130: -+ case AR71XX_SOC_AR9132: -+ spin_lock_irqsave(&ar71xx_device_lock, flags); -+ t = ar71xx_reset_rr(AR91XX_RESET_REG_RESET_MODULE); -+ spin_unlock_irqrestore(&ar71xx_device_lock, flags); -+ break; -+ -+ case AR71XX_SOC_AR9330: -+ case AR71XX_SOC_AR9331: -+ spin_lock_irqsave(&ar71xx_device_lock, flags); -+ t = ar71xx_reset_rr(AR933X_RESET_REG_RESET_MODULE); -+ spin_unlock_irqrestore(&ar71xx_device_lock, flags); -+ break; -+ -+ case AR71XX_SOC_AR9341: -+ case AR71XX_SOC_AR9342: -+ case AR71XX_SOC_AR9344: -+ spin_lock_irqsave(&ar71xx_device_lock, flags); -+ t = ar71xx_reset_rr(AR934X_RESET_REG_RESET_MODULE); -+ spin_unlock_irqrestore(&ar71xx_device_lock, flags); -+ break; -+ -+ default: -+ BUG(); -+ } -+ -+ return ((t & mask) == mask); -+} -+EXPORT_SYMBOL_GPL(ar71xx_device_stopped); -+ -+void ar71xx_ddr_flush(u32 reg) -+{ -+ ar71xx_ddr_wr(reg, 1); -+ while ((ar71xx_ddr_rr(reg) & 0x1)) -+ ; -+ -+ ar71xx_ddr_wr(reg, 1); -+ while ((ar71xx_ddr_rr(reg) & 0x1)) -+ ; -+} -+EXPORT_SYMBOL_GPL(ar71xx_ddr_flush); -+ -+void ar71xx_flash_acquire(void) -+{ -+ mutex_lock(&ar71xx_flash_mutex); -+} -+EXPORT_SYMBOL_GPL(ar71xx_flash_acquire); -+ -+void ar71xx_flash_release(void) -+{ -+ mutex_unlock(&ar71xx_flash_mutex); -+} -+EXPORT_SYMBOL_GPL(ar71xx_flash_release); -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/dev-ap91-pci.c linux-2.6.39/arch/mips/ar71xx/dev-ap91-pci.c ---- linux-2.6.39.orig/arch/mips/ar71xx/dev-ap91-pci.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/dev-ap91-pci.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,71 @@ -+/* -+ * Atheros AP91 reference board PCI initialization -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include "dev-ap91-pci.h" -+#include "pci-ath9k-fixup.h" -+ -+static struct ath9k_platform_data ap91_wmac_data = { -+ .led_pin = -1, -+}; -+static char ap91_wmac_mac[6]; -+ -+static struct ar71xx_pci_irq ap91_pci_irqs[] __initdata = { -+ { -+ .slot = 0, -+ .pin = 1, -+ .irq = AR71XX_PCI_IRQ_DEV0, -+ } -+}; -+ -+static int ap91_pci_plat_dev_init(struct pci_dev *dev) -+{ -+ switch (PCI_SLOT(dev->devfn)) { -+ case 0: -+ dev->dev.platform_data = &ap91_wmac_data; -+ break; -+ } -+ -+ return 0; -+} -+ -+__init void ap91_pci_setup_wmac_led_pin(int pin) -+{ -+ ap91_wmac_data.led_pin = pin; -+} -+ -+__init void ap91_pci_setup_wmac_gpio(u32 mask, u32 val) -+{ -+ ap91_wmac_data.gpio_mask = mask; -+ ap91_wmac_data.gpio_val = val; -+} -+ -+void __init ap91_pci_init(u8 *cal_data, u8 *mac_addr) -+{ -+ if (cal_data) -+ memcpy(ap91_wmac_data.eeprom_data, cal_data, -+ sizeof(ap91_wmac_data.eeprom_data)); -+ -+ if (mac_addr) { -+ memcpy(ap91_wmac_mac, mac_addr, sizeof(ap91_wmac_mac)); -+ ap91_wmac_data.macaddr = ap91_wmac_mac; -+ } -+ -+ ar71xx_pci_plat_dev_init = ap91_pci_plat_dev_init; -+ ar71xx_pci_init(ARRAY_SIZE(ap91_pci_irqs), ap91_pci_irqs); -+ -+ pci_enable_ath9k_fixup(0, ap91_wmac_data.eeprom_data); -+} -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/dev-ap91-pci.h linux-2.6.39/arch/mips/ar71xx/dev-ap91-pci.h ---- linux-2.6.39.orig/arch/mips/ar71xx/dev-ap91-pci.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/dev-ap91-pci.h 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,25 @@ -+/* -+ * Atheros AP91 reference board PCI initialization -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_DEV_AP91_PCI_H -+#define _AR71XX_DEV_AP91_PCI_H -+ -+#if defined(CONFIG_AR71XX_DEV_AP91_PCI) -+void ap91_pci_init(u8 *cal_data, u8 *mac_addr) __init; -+void ap91_pci_setup_wmac_led_pin(int pin) __init; -+void ap91_pci_setup_wmac_gpio(u32 mask, u32 val) __init; -+#else -+static inline void ap91_pci_init(u8 *cal_data, u8 *mac_addr) { } -+static inline void ap91_pci_setup_wmac_led_pin(int pin) { } -+static inline void ap91_pci_setup_wmac_gpio(u32 mask, u32 gpio) { } -+#endif -+ -+#endif /* _AR71XX_DEV_AP91_PCI_H */ -+ -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/dev-ap94-pci.c linux-2.6.39/arch/mips/ar71xx/dev-ap94-pci.c ---- linux-2.6.39.orig/arch/mips/ar71xx/dev-ap94-pci.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/dev-ap94-pci.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,109 @@ -+/* -+ * Atheros AP94 reference board PCI initialization -+ * -+ * Copyright (C) 2009-2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include "dev-ap94-pci.h" -+#include "pci-ath9k-fixup.h" -+ -+static struct ath9k_platform_data ap94_wmac0_data = { -+ .led_pin = -1, -+}; -+static struct ath9k_platform_data ap94_wmac1_data = { -+ .led_pin = -1, -+}; -+static char ap94_wmac0_mac[6]; -+static char ap94_wmac1_mac[6]; -+ -+static struct ar71xx_pci_irq ap94_pci_irqs[] __initdata = { -+ { -+ .slot = 0, -+ .pin = 1, -+ .irq = AR71XX_PCI_IRQ_DEV0, -+ }, { -+ .slot = 1, -+ .pin = 1, -+ .irq = AR71XX_PCI_IRQ_DEV1, -+ } -+}; -+ -+static int ap94_pci_plat_dev_init(struct pci_dev *dev) -+{ -+ switch (PCI_SLOT(dev->devfn)) { -+ case 17: -+ dev->dev.platform_data = &ap94_wmac0_data; -+ break; -+ -+ case 18: -+ dev->dev.platform_data = &ap94_wmac1_data; -+ break; -+ } -+ -+ return 0; -+} -+ -+__init void ap94_pci_setup_wmac_led_pin(unsigned wmac, int pin) -+{ -+ switch (wmac) { -+ case 0: -+ ap94_wmac0_data.led_pin = pin; -+ break; -+ case 1: -+ ap94_wmac1_data.led_pin = pin; -+ break; -+ } -+} -+ -+__init void ap94_pci_setup_wmac_gpio(unsigned wmac, u32 mask, u32 val) -+{ -+ switch (wmac) { -+ case 0: -+ ap94_wmac0_data.gpio_mask = mask; -+ ap94_wmac0_data.gpio_val = val; -+ break; -+ case 1: -+ ap94_wmac1_data.gpio_mask = mask; -+ ap94_wmac1_data.gpio_val = val; -+ break; -+ } -+} -+ -+void __init ap94_pci_init(u8 *cal_data0, u8 *mac_addr0, -+ u8 *cal_data1, u8 *mac_addr1) -+{ -+ if (cal_data0) -+ memcpy(ap94_wmac0_data.eeprom_data, cal_data0, -+ sizeof(ap94_wmac0_data.eeprom_data)); -+ -+ if (cal_data1) -+ memcpy(ap94_wmac1_data.eeprom_data, cal_data1, -+ sizeof(ap94_wmac1_data.eeprom_data)); -+ -+ if (mac_addr0) { -+ memcpy(ap94_wmac0_mac, mac_addr0, sizeof(ap94_wmac0_mac)); -+ ap94_wmac0_data.macaddr = ap94_wmac0_mac; -+ } -+ -+ if (mac_addr1) { -+ memcpy(ap94_wmac1_mac, mac_addr1, sizeof(ap94_wmac1_mac)); -+ ap94_wmac1_data.macaddr = ap94_wmac1_mac; -+ } -+ -+ ar71xx_pci_plat_dev_init = ap94_pci_plat_dev_init; -+ ar71xx_pci_init(ARRAY_SIZE(ap94_pci_irqs), ap94_pci_irqs); -+ -+ pci_enable_ath9k_fixup(17, ap94_wmac0_data.eeprom_data); -+ pci_enable_ath9k_fixup(18, ap94_wmac1_data.eeprom_data); -+} -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/dev-ap94-pci.h linux-2.6.39/arch/mips/ar71xx/dev-ap94-pci.h ---- linux-2.6.39.orig/arch/mips/ar71xx/dev-ap94-pci.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/dev-ap94-pci.h 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,31 @@ -+/* -+ * Atheros AP94 reference board PCI initialization -+ * -+ * Copyright (C) 2009-2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_DEV_AP94_PCI_H -+#define _AR71XX_DEV_AP94_PCI_H -+ -+#if defined(CONFIG_AR71XX_DEV_AP94_PCI) -+void ap94_pci_init(u8 *cal_data0, u8 *mac_addr0, -+ u8 *cal_data1, u8 *mac_addr1) __init; -+ -+void ap94_pci_setup_wmac_led_pin(unsigned wmac, int pin) __init; -+void ap94_pci_setup_wmac_gpio(unsigned wmac, u32 mask, u32 val) __init; -+ -+#else -+static inline void ap94_pci_init(u8 *cal_data0, u8 *mac_addr0, -+ u8 *cal_data1, u8 *mac_addr1) {} -+ -+static inline void ap94_pci_setup_wmac_led_pin(unsigned wmac, int pin) {} -+static inline void ap94_pci_setup_wmac_gpio(unsigned wmac, -+ u32 mask, u32 val) {} -+#endif -+ -+#endif /* _AR71XX_DEV_AP94_PCI_H */ -+ -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/dev-ar9xxx-wmac.c linux-2.6.39/arch/mips/ar71xx/dev-ar9xxx-wmac.c ---- linux-2.6.39.orig/arch/mips/ar71xx/dev-ar9xxx-wmac.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/dev-ar9xxx-wmac.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,154 @@ -+/* -+ * Atheros AR9XXX SoCs built-in WMAC device support -+ * -+ * Copyright (C) 2010-2011 Jaiganesh Narayanan -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros 2.6.15/2.6.31 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "dev-ar9xxx-wmac.h" -+ -+#define MHZ_25 (25 * 1000 * 1000) -+ -+static struct ath9k_platform_data ar9xxx_wmac_data = { -+ .led_pin = -1, -+}; -+static char ar9xxx_wmac_mac[6]; -+ -+static struct resource ar9xxx_wmac_resources[] = { -+ { -+ /* .start and .end fields are filled dynamically */ -+ .flags = IORESOURCE_MEM, -+ }, { -+ .start = AR71XX_CPU_IRQ_IP2, -+ .end = AR71XX_CPU_IRQ_IP2, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct platform_device ar9xxx_wmac_device = { -+ .name = "ath9k", -+ .id = -1, -+ .resource = ar9xxx_wmac_resources, -+ .num_resources = ARRAY_SIZE(ar9xxx_wmac_resources), -+ .dev = { -+ .platform_data = &ar9xxx_wmac_data, -+ }, -+}; -+ -+static void ar913x_wmac_init(void) -+{ -+ ar71xx_device_stop(RESET_MODULE_AMBA2WMAC); -+ mdelay(10); -+ -+ ar71xx_device_start(RESET_MODULE_AMBA2WMAC); -+ mdelay(10); -+ -+ ar9xxx_wmac_resources[0].start = AR91XX_WMAC_BASE; -+ ar9xxx_wmac_resources[0].end = AR91XX_WMAC_BASE + AR91XX_WMAC_SIZE - 1; -+} -+ -+static int ar933x_r1_get_wmac_revision(void) -+{ -+ return ar71xx_soc_rev; -+} -+ -+static int ar933x_wmac_reset(void) -+{ -+ unsigned retries = 0; -+ -+ ar71xx_device_stop(AR933X_RESET_WMAC); -+ ar71xx_device_start(AR933X_RESET_WMAC); -+ -+ while (1) { -+ u32 bootstrap; -+ -+ bootstrap = ar71xx_reset_rr(AR933X_RESET_REG_BOOTSTRAP); -+ if ((bootstrap & AR933X_BOOTSTRAP_EEPBUSY) == 0) -+ return 0; -+ -+ if (retries > 20) -+ break; -+ -+ udelay(10000); -+ retries++; -+ } -+ -+ pr_err("ar93xx: WMAC reset timed out"); -+ return -ETIMEDOUT; -+} -+ -+static void ar933x_wmac_init(void) -+{ -+ ar9xxx_wmac_device.name = "ar933x_wmac"; -+ ar9xxx_wmac_resources[0].start = AR933X_WMAC_BASE; -+ ar9xxx_wmac_resources[0].end = AR933X_WMAC_BASE + AR933X_WMAC_SIZE - 1; -+ if (ar71xx_ref_freq == MHZ_25) -+ ar9xxx_wmac_data.is_clk_25mhz = true; -+ -+ if (ar71xx_soc_rev == 1) -+ ar9xxx_wmac_data.get_mac_revision = ar933x_r1_get_wmac_revision; -+ -+ ar9xxx_wmac_data.external_reset = ar933x_wmac_reset; -+ -+ ar933x_wmac_reset(); -+} -+ -+static void ar934x_wmac_init(void) -+{ -+ ar9xxx_wmac_device.name = "ar934x_wmac"; -+ ar9xxx_wmac_resources[0].start = AR934X_WMAC_BASE; -+ ar9xxx_wmac_resources[0].end = AR934X_WMAC_BASE + AR934X_WMAC_SIZE - 1; -+ if (ar71xx_ref_freq == MHZ_25) -+ ar9xxx_wmac_data.is_clk_25mhz = true; -+} -+ -+void __init ar9xxx_add_device_wmac(u8 *cal_data, u8 *mac_addr) -+{ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR9130: -+ case AR71XX_SOC_AR9132: -+ ar913x_wmac_init(); -+ break; -+ -+ case AR71XX_SOC_AR9330: -+ case AR71XX_SOC_AR9331: -+ ar933x_wmac_init(); -+ break; -+ -+ case AR71XX_SOC_AR9341: -+ case AR71XX_SOC_AR9342: -+ case AR71XX_SOC_AR9344: -+ ar934x_wmac_init(); -+ break; -+ -+ default: -+ BUG(); -+ } -+ -+ if (cal_data) -+ memcpy(ar9xxx_wmac_data.eeprom_data, cal_data, -+ sizeof(ar9xxx_wmac_data.eeprom_data)); -+ -+ if (mac_addr) { -+ memcpy(ar9xxx_wmac_mac, mac_addr, sizeof(ar9xxx_wmac_mac)); -+ ar9xxx_wmac_data.macaddr = ar9xxx_wmac_mac; -+ } -+ -+ platform_device_register(&ar9xxx_wmac_device); -+} -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/dev-ar9xxx-wmac.h linux-2.6.39/arch/mips/ar71xx/dev-ar9xxx-wmac.h ---- linux-2.6.39.orig/arch/mips/ar71xx/dev-ar9xxx-wmac.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/dev-ar9xxx-wmac.h 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,20 @@ -+/* -+ * Atheros AR9XXX SoCs built-in WMAC device support -+ * -+ * Copyright (C) 2010-2011 Jaiganesh Narayanan -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros 2.6.15/2.6.31 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_DEV_AR9XXX_WMAC_H -+#define _AR71XX_DEV_AR9XXX_WMAC_H -+ -+void ar9xxx_add_device_wmac(u8 *cal_data, u8 *mac_addr) __init; -+ -+#endif /* _AR71XX_DEV_AR9XXX_WMAC_H */ -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/dev-db120-pci.c linux-2.6.39/arch/mips/ar71xx/dev-db120-pci.c ---- linux-2.6.39.orig/arch/mips/ar71xx/dev-db120-pci.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/dev-db120-pci.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,31 @@ -+/* -+ * Atheros db120 reference board PCI initialization -+ * -+ * Copyright (C) 2010-2011 Jaiganesh Narayanan -+ * -+ * Parts of this file are based on Atheros linux 2.6.31 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+ -+#include -+#include -+ -+#include "dev-db120-pci.h" -+ -+static struct ar71xx_pci_irq db120_pci_irqs[] __initdata = { -+ { -+ .slot = 0, -+ .pin = 1, -+ .irq = AR71XX_PCI_IRQ_DEV0, -+ } -+}; -+ -+void __init db120_pci_init(void) -+{ -+ ar71xx_pci_init(ARRAY_SIZE(db120_pci_irqs), db120_pci_irqs); -+} -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/dev-db120-pci.h linux-2.6.39/arch/mips/ar71xx/dev-db120-pci.h ---- linux-2.6.39.orig/arch/mips/ar71xx/dev-db120-pci.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/dev-db120-pci.h 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,22 @@ -+/* -+ * Atheros DB120 reference board PCI initialization -+ * -+ * Copyright (C) 2010-2011 Jaiganesh Narayanan -+ * -+ * Parts of this file are based on Atheros linux 2.6.31 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_DEV_DB120_PCI_H -+#define _AR71XX_DEV_DB120_PCI_H -+ -+#if defined(CONFIG_AR71XX_DEV_DB120_PCI) -+void db120_pci_init(void); -+#else -+static inline void db120_pci_init(void) { } -+#endif -+ -+#endif /* _AR71XX_DEV_DB120_PCI_H */ -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/dev-dsa.c linux-2.6.39/arch/mips/ar71xx/dev-dsa.c ---- linux-2.6.39.orig/arch/mips/ar71xx/dev-dsa.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/dev-dsa.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,50 @@ -+/* -+ * Atheros AR71xx DSA switch device support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "devices.h" -+#include "dev-dsa.h" -+ -+static struct platform_device ar71xx_dsa_switch_device = { -+ .name = "dsa", -+ .id = 0, -+}; -+ -+void __init ar71xx_add_device_dsa(unsigned int id, -+ struct dsa_platform_data *d) -+{ -+ int i; -+ -+ switch (id) { -+ case 0: -+ d->netdev = &ar71xx_eth0_device.dev; -+ break; -+ case 1: -+ d->netdev = &ar71xx_eth1_device.dev; -+ break; -+ default: -+ printk(KERN_ERR -+ "ar71xx: invalid ethernet id %d for DSA switch\n", -+ id); -+ return; -+ } -+ -+ for (i = 0; i < d->nr_chips; i++) -+ d->chip[i].mii_bus = &ar71xx_mdio_device.dev; -+ -+ ar71xx_dsa_switch_device.dev.platform_data = d; -+ -+ platform_device_register(&ar71xx_dsa_switch_device); -+} -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/dev-dsa.h linux-2.6.39/arch/mips/ar71xx/dev-dsa.h ---- linux-2.6.39.orig/arch/mips/ar71xx/dev-dsa.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/dev-dsa.h 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,20 @@ -+/* -+ * Atheros AR71xx DSA switch device support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_DEV_DSA_H -+#define _AR71XX_DEV_DSA_H -+ -+#include -+ -+void ar71xx_add_device_dsa(unsigned int id, -+ struct dsa_platform_data *d) __init; -+ -+#endif /* _AR71XX_DEV_DSA_H */ -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/dev-gpio-buttons.c linux-2.6.39/arch/mips/ar71xx/dev-gpio-buttons.c ---- linux-2.6.39.orig/arch/mips/ar71xx/dev-gpio-buttons.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/dev-gpio-buttons.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,58 @@ -+/* -+ * Atheros AR71xx GPIO button support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include "linux/init.h" -+#include "linux/slab.h" -+#include -+ -+#include "dev-gpio-buttons.h" -+ -+void __init ar71xx_register_gpio_keys_polled(int id, -+ unsigned poll_interval, -+ unsigned nbuttons, -+ struct gpio_keys_button *buttons) -+{ -+ struct platform_device *pdev; -+ struct gpio_keys_platform_data pdata; -+ struct gpio_keys_button *p; -+ int err; -+ -+ p = kmalloc(nbuttons * sizeof(*p), GFP_KERNEL); -+ if (!p) -+ return; -+ -+ memcpy(p, buttons, nbuttons * sizeof(*p)); -+ -+ pdev = platform_device_alloc("gpio-keys-polled", id); -+ if (!pdev) -+ goto err_free_buttons; -+ -+ memset(&pdata, 0, sizeof(pdata)); -+ pdata.poll_interval = poll_interval; -+ pdata.nbuttons = nbuttons; -+ pdata.buttons = p; -+ -+ err = platform_device_add_data(pdev, &pdata, sizeof(pdata)); -+ if (err) -+ goto err_put_pdev; -+ -+ err = platform_device_add(pdev); -+ if (err) -+ goto err_put_pdev; -+ -+ return; -+ -+err_put_pdev: -+ platform_device_put(pdev); -+ -+err_free_buttons: -+ kfree(p); -+} -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/dev-gpio-buttons.h linux-2.6.39/arch/mips/ar71xx/dev-gpio-buttons.h ---- linux-2.6.39.orig/arch/mips/ar71xx/dev-gpio-buttons.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/dev-gpio-buttons.h 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,23 @@ -+/* -+ * Atheros AR71xx GPIO button support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_DEV_GPIO_BUTTONS_H -+#define _AR71XX_DEV_GPIO_BUTTONS_H -+ -+#include -+#include -+ -+void ar71xx_register_gpio_keys_polled(int id, -+ unsigned poll_interval, -+ unsigned nbuttons, -+ struct gpio_keys_button *buttons); -+ -+#endif /* _AR71XX_DEV_GPIO_BUTTONS_H */ -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/dev-leds-gpio.c linux-2.6.39/arch/mips/ar71xx/dev-leds-gpio.c ---- linux-2.6.39.orig/arch/mips/ar71xx/dev-leds-gpio.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/dev-leds-gpio.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,57 @@ -+/* -+ * Atheros AR71xx GPIO LED device support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+ -+#include "dev-leds-gpio.h" -+ -+void __init ar71xx_add_device_leds_gpio(int id, unsigned num_leds, -+ struct gpio_led *leds) -+{ -+ struct platform_device *pdev; -+ struct gpio_led_platform_data pdata; -+ struct gpio_led *p; -+ int err; -+ -+ p = kmalloc(num_leds * sizeof(*p), GFP_KERNEL); -+ if (!p) -+ return; -+ -+ memcpy(p, leds, num_leds * sizeof(*p)); -+ -+ pdev = platform_device_alloc("leds-gpio", id); -+ if (!pdev) -+ goto err_free_leds; -+ -+ memset(&pdata, 0, sizeof(pdata)); -+ pdata.num_leds = num_leds; -+ pdata.leds = p; -+ -+ err = platform_device_add_data(pdev, &pdata, sizeof(pdata)); -+ if (err) -+ goto err_put_pdev; -+ -+ err = platform_device_add(pdev); -+ if (err) -+ goto err_put_pdev; -+ -+ return; -+ -+err_put_pdev: -+ platform_device_put(pdev); -+ -+err_free_leds: -+ kfree(p); -+} -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/dev-leds-gpio.h linux-2.6.39/arch/mips/ar71xx/dev-leds-gpio.h ---- linux-2.6.39.orig/arch/mips/ar71xx/dev-leds-gpio.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/dev-leds-gpio.h 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,21 @@ -+/* -+ * Atheros AR71xx GPIO LED device support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_DEV_LEDS_GPIO_H -+#define _AR71XX_DEV_LEDS_GPIO_H -+ -+#include -+ -+void ar71xx_add_device_leds_gpio(int id, -+ unsigned num_leds, -+ struct gpio_led *leds) __init; -+ -+#endif /* _AR71XX_DEV_LEDS_GPIO_H */ -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/dev-m25p80.c linux-2.6.39/arch/mips/ar71xx/dev-m25p80.c ---- linux-2.6.39.orig/arch/mips/ar71xx/dev-m25p80.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/dev-m25p80.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,30 @@ -+/* -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+ -+#include "devices.h" -+#include "dev-m25p80.h" -+ -+static struct spi_board_info ar71xx_spi_info[] = { -+ { -+ .bus_num = 0, -+ .chip_select = 0, -+ .max_speed_hz = 25000000, -+ .modalias = "m25p80", -+ } -+}; -+ -+void __init ar71xx_add_device_m25p80(struct flash_platform_data *pdata) -+{ -+ ar71xx_spi_info[0].platform_data = pdata; -+ ar71xx_add_device_spi(NULL, ar71xx_spi_info, -+ ARRAY_SIZE(ar71xx_spi_info)); -+} -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/dev-m25p80.h linux-2.6.39/arch/mips/ar71xx/dev-m25p80.h ---- linux-2.6.39.orig/arch/mips/ar71xx/dev-m25p80.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/dev-m25p80.h 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,16 @@ -+/* -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_DEV_M25P80_H -+#define _AR71XX_DEV_M25P80_H -+ -+#include -+ -+void ar71xx_add_device_m25p80(struct flash_platform_data *pdata) __init; -+ -+#endif /* _AR71XX_DEV_M25P80_H */ -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/dev-pb42-pci.c linux-2.6.39/arch/mips/ar71xx/dev-pb42-pci.c ---- linux-2.6.39.orig/arch/mips/ar71xx/dev-pb42-pci.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/dev-pb42-pci.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,40 @@ -+/* -+ * Atheros PB42 reference board PCI initialization -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+ -+#include -+#include -+ -+#include "dev-pb42-pci.h" -+ -+static struct ar71xx_pci_irq pb42_pci_irqs[] __initdata = { -+ { -+ .slot = 0, -+ .pin = 1, -+ .irq = AR71XX_PCI_IRQ_DEV0, -+ }, { -+ .slot = 1, -+ .pin = 1, -+ .irq = AR71XX_PCI_IRQ_DEV1, -+ }, { -+ .slot = 2, -+ .pin = 1, -+ .irq = AR71XX_PCI_IRQ_DEV2, -+ } -+}; -+ -+void __init pb42_pci_init(void) -+{ -+ ar71xx_pci_init(ARRAY_SIZE(pb42_pci_irqs), pb42_pci_irqs); -+} -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/dev-pb42-pci.h linux-2.6.39/arch/mips/ar71xx/dev-pb42-pci.h ---- linux-2.6.39.orig/arch/mips/ar71xx/dev-pb42-pci.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/dev-pb42-pci.h 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,21 @@ -+/* -+ * Atheros PB42 reference board PCI initialization -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_DEV_PB42_PCI_H -+#define _AR71XX_DEV_PB42_PCI_H -+ -+#if defined(CONFIG_AR71XX_DEV_PB42_PCI) -+void pb42_pci_init(void) __init; -+#else -+static inline void pb42_pci_init(void) { } -+#endif -+ -+#endif /* _AR71XX_DEV_PB42_PCI_H */ -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/dev-pb9x-pci.c linux-2.6.39/arch/mips/ar71xx/dev-pb9x-pci.c ---- linux-2.6.39.orig/arch/mips/ar71xx/dev-pb9x-pci.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/dev-pb9x-pci.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,33 @@ -+/* -+ * Atheros PB9x reference board PCI initialization -+ * -+ * Copyright (C) 2010 Felix Fietkau -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+ -+#include -+#include -+ -+#include "dev-pb9x-pci.h" -+ -+static struct ar71xx_pci_irq pb9x_pci_irqs[] __initdata = { -+ { -+ .slot = 0, -+ .pin = 1, -+ .irq = AR71XX_PCI_IRQ_DEV0, -+ } -+}; -+ -+void __init pb9x_pci_init(void) -+{ -+ ar71xx_pci_init(ARRAY_SIZE(pb9x_pci_irqs), pb9x_pci_irqs); -+} -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/dev-pb9x-pci.h linux-2.6.39/arch/mips/ar71xx/dev-pb9x-pci.h ---- linux-2.6.39.orig/arch/mips/ar71xx/dev-pb9x-pci.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/dev-pb9x-pci.h 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,22 @@ -+/* -+ * Atheros PB9x reference board PCI initialization -+ * -+ * Copyright (C) 2010 Felix Fietkau -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_DEV_PB9X_PCI_H -+#define _AR71XX_DEV_PB9X_PCI_H -+ -+#if defined(CONFIG_AR71XX_DEV_PB9X_PCI) -+void pb9x_pci_init(void) __init; -+#else -+static inline void pb9x_pci_init(void) { } -+#endif -+ -+#endif /* _AR71XX_DEV_PB9X_PCI_H */ -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/dev-usb.c linux-2.6.39/arch/mips/ar71xx/dev-usb.c ---- linux-2.6.39.orig/arch/mips/ar71xx/dev-usb.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/dev-usb.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,199 @@ -+/* -+ * Atheros AR71xx USB host device support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include "dev-usb.h" -+ -+/* -+ * OHCI (USB full speed host controller) -+ */ -+static struct resource ar71xx_ohci_resources[] = { -+ [0] = { -+ .start = AR71XX_OHCI_BASE, -+ .end = AR71XX_OHCI_BASE + AR71XX_OHCI_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+ [1] = { -+ .start = AR71XX_MISC_IRQ_OHCI, -+ .end = AR71XX_MISC_IRQ_OHCI, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct resource ar7240_ohci_resources[] = { -+ [0] = { -+ .start = AR7240_OHCI_BASE, -+ .end = AR7240_OHCI_BASE + AR7240_OHCI_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+ [1] = { -+ .start = AR71XX_CPU_IRQ_USB, -+ .end = AR71XX_CPU_IRQ_USB, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static u64 ar71xx_ohci_dmamask = DMA_BIT_MASK(32); -+static struct platform_device ar71xx_ohci_device = { -+ .name = "ar71xx-ohci", -+ .id = -1, -+ .resource = ar71xx_ohci_resources, -+ .num_resources = ARRAY_SIZE(ar71xx_ohci_resources), -+ .dev = { -+ .dma_mask = &ar71xx_ohci_dmamask, -+ .coherent_dma_mask = DMA_BIT_MASK(32), -+ }, -+}; -+ -+/* -+ * EHCI (USB high/full speed host controller) -+ */ -+static struct resource ar71xx_ehci_resources[] = { -+ [0] = { -+ .start = AR71XX_EHCI_BASE, -+ .end = AR71XX_EHCI_BASE + AR71XX_EHCI_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+ [1] = { -+ .start = AR71XX_CPU_IRQ_USB, -+ .end = AR71XX_CPU_IRQ_USB, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static u64 ar71xx_ehci_dmamask = DMA_BIT_MASK(32); -+static struct ar71xx_ehci_platform_data ar71xx_ehci_data; -+ -+static struct platform_device ar71xx_ehci_device = { -+ .name = "ar71xx-ehci", -+ .id = -1, -+ .resource = ar71xx_ehci_resources, -+ .num_resources = ARRAY_SIZE(ar71xx_ehci_resources), -+ .dev = { -+ .dma_mask = &ar71xx_ehci_dmamask, -+ .coherent_dma_mask = DMA_BIT_MASK(32), -+ .platform_data = &ar71xx_ehci_data, -+ }, -+}; -+ -+#define AR71XX_USB_RESET_MASK \ -+ (RESET_MODULE_USB_HOST | RESET_MODULE_USB_PHY \ -+ | RESET_MODULE_USB_OHCI_DLL) -+ -+#define AR7240_USB_RESET_MASK \ -+ (RESET_MODULE_USB_HOST | RESET_MODULE_USB_OHCI_DLL_7240) -+ -+static void __init ar71xx_usb_setup(void) -+{ -+ ar71xx_device_stop(AR71XX_USB_RESET_MASK); -+ mdelay(1000); -+ ar71xx_device_start(AR71XX_USB_RESET_MASK); -+ -+ /* Turning on the Buff and Desc swap bits */ -+ ar71xx_usb_ctrl_wr(USB_CTRL_REG_CONFIG, 0xf0000); -+ -+ /* WAR for HW bug. Here it adjusts the duration between two SOFS */ -+ ar71xx_usb_ctrl_wr(USB_CTRL_REG_FLADJ, 0x20c00); -+ -+ mdelay(900); -+ -+ platform_device_register(&ar71xx_ohci_device); -+ platform_device_register(&ar71xx_ehci_device); -+} -+ -+static void __init ar7240_usb_setup(void) -+{ -+ ar71xx_device_stop(AR7240_USB_RESET_MASK); -+ mdelay(1000); -+ ar71xx_device_start(AR7240_USB_RESET_MASK); -+ -+ /* WAR for HW bug. Here it adjusts the duration between two SOFS */ -+ ar71xx_usb_ctrl_wr(USB_CTRL_REG_FLADJ, 0x3); -+ -+ ar71xx_ohci_device.resource = ar7240_ohci_resources; -+ ar71xx_ohci_device.num_resources = ARRAY_SIZE(ar7240_ohci_resources); -+ platform_device_register(&ar71xx_ohci_device); -+} -+ -+static void __init ar7241_usb_setup(void) -+{ -+ ar71xx_device_start(AR724X_RESET_USBSUS_OVERRIDE); -+ mdelay(10); -+ -+ ar71xx_device_start(AR724X_RESET_USB_HOST); -+ mdelay(10); -+ -+ ar71xx_device_start(AR724X_RESET_USB_PHY); -+ mdelay(10); -+ -+ ar71xx_ehci_data.is_ar91xx = 1; -+ ar71xx_ehci_device.resource = ar7240_ohci_resources; -+ ar71xx_ehci_device.num_resources = ARRAY_SIZE(ar7240_ohci_resources); -+ platform_device_register(&ar71xx_ehci_device); -+} -+ -+static void __init ar91xx_usb_setup(void) -+{ -+ ar71xx_device_stop(RESET_MODULE_USBSUS_OVERRIDE); -+ mdelay(10); -+ -+ ar71xx_device_start(RESET_MODULE_USB_HOST); -+ mdelay(10); -+ -+ ar71xx_device_start(RESET_MODULE_USB_PHY); -+ mdelay(10); -+ -+ ar71xx_ehci_data.is_ar91xx = 1; -+ platform_device_register(&ar71xx_ehci_device); -+} -+ -+void __init ar71xx_add_device_usb(void) -+{ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7240: -+ ar7240_usb_setup(); -+ break; -+ -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ ar7241_usb_setup(); -+ break; -+ -+ case AR71XX_SOC_AR7130: -+ case AR71XX_SOC_AR7141: -+ case AR71XX_SOC_AR7161: -+ ar71xx_usb_setup(); -+ break; -+ -+ case AR71XX_SOC_AR9130: -+ case AR71XX_SOC_AR9132: -+ case AR71XX_SOC_AR9330: -+ case AR71XX_SOC_AR9331: -+ case AR71XX_SOC_AR9341: -+ case AR71XX_SOC_AR9342: -+ case AR71XX_SOC_AR9344: -+ ar91xx_usb_setup(); -+ break; -+ -+ default: -+ BUG(); -+ } -+} -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/dev-usb.h linux-2.6.39/arch/mips/ar71xx/dev-usb.h ---- linux-2.6.39.orig/arch/mips/ar71xx/dev-usb.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/dev-usb.h 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,17 @@ -+/* -+ * Atheros AR71xx USB host device support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_DEV_USB_H -+#define _AR71XX_DEV_USB_H -+ -+void ar71xx_add_device_usb(void) __init; -+ -+#endif /* _AR71XX_DEV_USB_H */ -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/devices.c linux-2.6.39/arch/mips/ar71xx/devices.c ---- linux-2.6.39.orig/arch/mips/ar71xx/devices.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/devices.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,765 @@ -+/* -+ * Atheros AR71xx SoC platform devices -+ * -+ * Copyright (C) 2010-2011 Jaiganesh Narayanan -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros 2.6.15 BSP -+ * Parts of this file are based on Atheros 2.6.31 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include "devices.h" -+ -+unsigned char ar71xx_mac_base[ETH_ALEN] __initdata; -+ -+static struct resource ar71xx_uart_resources[] = { -+ { -+ .start = AR71XX_UART_BASE, -+ .end = AR71XX_UART_BASE + AR71XX_UART_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+}; -+ -+#define AR71XX_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP) -+static struct plat_serial8250_port ar71xx_uart_data[] = { -+ { -+ .mapbase = AR71XX_UART_BASE, -+ .irq = AR71XX_MISC_IRQ_UART, -+ .flags = AR71XX_UART_FLAGS, -+ .iotype = UPIO_MEM32, -+ .regshift = 2, -+ }, { -+ /* terminating entry */ -+ } -+}; -+ -+static struct platform_device ar71xx_uart_device = { -+ .name = "serial8250", -+ .id = PLAT8250_DEV_PLATFORM, -+ .resource = ar71xx_uart_resources, -+ .num_resources = ARRAY_SIZE(ar71xx_uart_resources), -+ .dev = { -+ .platform_data = ar71xx_uart_data -+ }, -+}; -+ -+static struct resource ar933x_uart_resources[] = { -+ { -+ .start = AR933X_UART_BASE, -+ .end = AR933X_UART_BASE + AR71XX_UART_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+ { -+ .start = AR71XX_MISC_IRQ_UART, -+ .end = AR71XX_MISC_IRQ_UART, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct ar933x_uart_platform_data ar933x_uart_data; -+static struct platform_device ar933x_uart_device = { -+ .name = "ar933x-uart", -+ .id = -1, -+ .resource = ar933x_uart_resources, -+ .num_resources = ARRAY_SIZE(ar933x_uart_resources), -+ .dev = { -+ .platform_data = &ar933x_uart_data, -+ }, -+}; -+ -+void __init ar71xx_add_device_uart(void) -+{ -+ struct platform_device *pdev; -+ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7130: -+ case AR71XX_SOC_AR7141: -+ case AR71XX_SOC_AR7161: -+ case AR71XX_SOC_AR7240: -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ case AR71XX_SOC_AR9130: -+ case AR71XX_SOC_AR9132: -+ pdev = &ar71xx_uart_device; -+ ar71xx_uart_data[0].uartclk = ar71xx_ahb_freq; -+ break; -+ -+ case AR71XX_SOC_AR9330: -+ case AR71XX_SOC_AR9331: -+ pdev = &ar933x_uart_device; -+ ar933x_uart_data.uartclk = ar71xx_ref_freq; -+ break; -+ -+ case AR71XX_SOC_AR9341: -+ case AR71XX_SOC_AR9342: -+ case AR71XX_SOC_AR9344: -+ pdev = &ar71xx_uart_device; -+ ar71xx_uart_data[0].uartclk = ar71xx_ref_freq; -+ break; -+ -+ default: -+ BUG(); -+ } -+ -+ platform_device_register(pdev); -+} -+ -+static struct resource ar71xx_mdio_resources[] = { -+ { -+ .name = "mdio_base", -+ .flags = IORESOURCE_MEM, -+ .start = AR71XX_GE0_BASE, -+ .end = AR71XX_GE0_BASE + 0x200 - 1, -+ } -+}; -+ -+static struct ag71xx_mdio_platform_data ar71xx_mdio_data; -+ -+struct platform_device ar71xx_mdio_device = { -+ .name = "ag71xx-mdio", -+ .id = -1, -+ .resource = ar71xx_mdio_resources, -+ .num_resources = ARRAY_SIZE(ar71xx_mdio_resources), -+ .dev = { -+ .platform_data = &ar71xx_mdio_data, -+ }, -+}; -+ -+static void ar71xx_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift) -+{ -+ void __iomem *base; -+ u32 t; -+ -+ base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE); -+ -+ t = __raw_readl(base + cfg_reg); -+ t &= ~(3 << shift); -+ t |= (2 << shift); -+ __raw_writel(t, base + cfg_reg); -+ udelay(100); -+ -+ __raw_writel(pll_val, base + pll_reg); -+ -+ t |= (3 << shift); -+ __raw_writel(t, base + cfg_reg); -+ udelay(100); -+ -+ t &= ~(3 << shift); -+ __raw_writel(t, base + cfg_reg); -+ udelay(100); -+ -+ printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n", -+ (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg)); -+ -+ iounmap(base); -+} -+ -+void __init ar71xx_add_device_mdio(u32 phy_mask) -+{ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7240: -+ ar71xx_mdio_data.is_ar7240 = 1; -+ break; -+ case AR71XX_SOC_AR7241: -+ ar71xx_mdio_data.is_ar7240 = 1; -+ ar71xx_mdio_resources[0].start = AR71XX_GE1_BASE; -+ ar71xx_mdio_resources[0].end = AR71XX_GE1_BASE + 0x200 - 1; -+ break; -+ case AR71XX_SOC_AR7242: -+ ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, -+ AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000, -+ AR71XX_ETH0_PLL_SHIFT); -+ break; -+ case AR71XX_SOC_AR9330: -+ case AR71XX_SOC_AR9331: -+ ar71xx_mdio_data.is_ar7240 = 1; -+ ar71xx_mdio_resources[0].start = AR71XX_GE1_BASE; -+ ar71xx_mdio_resources[0].end = AR71XX_GE1_BASE + 0x200 - 1; -+ break; -+ default: -+ break; -+ } -+ -+ ar71xx_mdio_data.phy_mask = phy_mask; -+ -+ platform_device_register(&ar71xx_mdio_device); -+} -+ -+struct ar71xx_eth_pll_data ar71xx_eth0_pll_data; -+struct ar71xx_eth_pll_data ar71xx_eth1_pll_data; -+ -+static u32 ar71xx_get_eth_pll(unsigned int mac, int speed) -+{ -+ struct ar71xx_eth_pll_data *pll_data; -+ u32 pll_val; -+ -+ switch (mac) { -+ case 0: -+ pll_data = &ar71xx_eth0_pll_data; -+ break; -+ case 1: -+ pll_data = &ar71xx_eth1_pll_data; -+ break; -+ default: -+ BUG(); -+ } -+ -+ switch (speed) { -+ case SPEED_10: -+ pll_val = pll_data->pll_10; -+ break; -+ case SPEED_100: -+ pll_val = pll_data->pll_100; -+ break; -+ case SPEED_1000: -+ pll_val = pll_data->pll_1000; -+ break; -+ default: -+ BUG(); -+ } -+ -+ return pll_val; -+} -+ -+static void ar71xx_set_pll_ge0(int speed) -+{ -+ u32 val = ar71xx_get_eth_pll(0, speed); -+ -+ ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK, -+ val, AR71XX_ETH0_PLL_SHIFT); -+} -+ -+static void ar71xx_set_pll_ge1(int speed) -+{ -+ u32 val = ar71xx_get_eth_pll(1, speed); -+ -+ ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK, -+ val, AR71XX_ETH1_PLL_SHIFT); -+} -+ -+static void ar724x_set_pll_ge0(int speed) -+{ -+ /* TODO */ -+} -+ -+static void ar724x_set_pll_ge1(int speed) -+{ -+ /* TODO */ -+} -+ -+static void ar7242_set_pll_ge0(int speed) -+{ -+ u32 val = ar71xx_get_eth_pll(0, speed); -+ -+ ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR7242_PLL_REG_ETH0_INT_CLOCK, -+ val, AR71XX_ETH0_PLL_SHIFT); -+} -+ -+static void ar91xx_set_pll_ge0(int speed) -+{ -+ u32 val = ar71xx_get_eth_pll(0, speed); -+ -+ ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH0_INT_CLOCK, -+ val, AR91XX_ETH0_PLL_SHIFT); -+} -+ -+static void ar91xx_set_pll_ge1(int speed) -+{ -+ u32 val = ar71xx_get_eth_pll(1, speed); -+ -+ ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH1_INT_CLOCK, -+ val, AR91XX_ETH1_PLL_SHIFT); -+} -+ -+static void ar933x_set_pll_ge0(int speed) -+{ -+ /* TODO */ -+} -+ -+static void ar933x_set_pll_ge1(int speed) -+{ -+ /* TODO */ -+} -+ -+static void ar71xx_ddr_flush_ge0(void) -+{ -+ ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE0); -+} -+ -+static void ar71xx_ddr_flush_ge1(void) -+{ -+ ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE1); -+} -+ -+static void ar724x_ddr_flush_ge0(void) -+{ -+ ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE0); -+} -+ -+static void ar724x_ddr_flush_ge1(void) -+{ -+ ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE1); -+} -+ -+static void ar91xx_ddr_flush_ge0(void) -+{ -+ ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0); -+} -+ -+static void ar91xx_ddr_flush_ge1(void) -+{ -+ ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE1); -+} -+ -+static void ar933x_ddr_flush_ge0(void) -+{ -+ ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE0); -+} -+ -+static void ar933x_ddr_flush_ge1(void) -+{ -+ ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE1); -+} -+ -+static struct resource ar71xx_eth0_resources[] = { -+ { -+ .name = "mac_base", -+ .flags = IORESOURCE_MEM, -+ .start = AR71XX_GE0_BASE, -+ .end = AR71XX_GE0_BASE + 0x200 - 1, -+ }, { -+ .name = "mii_ctrl", -+ .flags = IORESOURCE_MEM, -+ .start = AR71XX_MII_BASE + MII_REG_MII0_CTRL, -+ .end = AR71XX_MII_BASE + MII_REG_MII0_CTRL + 3, -+ }, { -+ .name = "mac_irq", -+ .flags = IORESOURCE_IRQ, -+ .start = AR71XX_CPU_IRQ_GE0, -+ .end = AR71XX_CPU_IRQ_GE0, -+ }, -+}; -+ -+struct ag71xx_platform_data ar71xx_eth0_data = { -+ .reset_bit = RESET_MODULE_GE0_MAC, -+}; -+ -+struct platform_device ar71xx_eth0_device = { -+ .name = "ag71xx", -+ .id = 0, -+ .resource = ar71xx_eth0_resources, -+ .num_resources = ARRAY_SIZE(ar71xx_eth0_resources), -+ .dev = { -+ .platform_data = &ar71xx_eth0_data, -+ }, -+}; -+ -+static struct resource ar71xx_eth1_resources[] = { -+ { -+ .name = "mac_base", -+ .flags = IORESOURCE_MEM, -+ .start = AR71XX_GE1_BASE, -+ .end = AR71XX_GE1_BASE + 0x200 - 1, -+ }, { -+ .name = "mii_ctrl", -+ .flags = IORESOURCE_MEM, -+ .start = AR71XX_MII_BASE + MII_REG_MII1_CTRL, -+ .end = AR71XX_MII_BASE + MII_REG_MII1_CTRL + 3, -+ }, { -+ .name = "mac_irq", -+ .flags = IORESOURCE_IRQ, -+ .start = AR71XX_CPU_IRQ_GE1, -+ .end = AR71XX_CPU_IRQ_GE1, -+ }, -+}; -+ -+struct ag71xx_platform_data ar71xx_eth1_data = { -+ .reset_bit = RESET_MODULE_GE1_MAC, -+}; -+ -+struct platform_device ar71xx_eth1_device = { -+ .name = "ag71xx", -+ .id = 1, -+ .resource = ar71xx_eth1_resources, -+ .num_resources = ARRAY_SIZE(ar71xx_eth1_resources), -+ .dev = { -+ .platform_data = &ar71xx_eth1_data, -+ }, -+}; -+ -+#define AR71XX_PLL_VAL_1000 0x00110000 -+#define AR71XX_PLL_VAL_100 0x00001099 -+#define AR71XX_PLL_VAL_10 0x00991099 -+ -+#define AR724X_PLL_VAL_1000 0x00110000 -+#define AR724X_PLL_VAL_100 0x00001099 -+#define AR724X_PLL_VAL_10 0x00991099 -+ -+#define AR7242_PLL_VAL_1000 0x1c000000 -+#define AR7242_PLL_VAL_100 0x00000101 -+#define AR7242_PLL_VAL_10 0x00001616 -+ -+#define AR91XX_PLL_VAL_1000 0x1a000000 -+#define AR91XX_PLL_VAL_100 0x13000a44 -+#define AR91XX_PLL_VAL_10 0x00441099 -+ -+#define AR933X_PLL_VAL_1000 0x00110000 -+#define AR933X_PLL_VAL_100 0x00001099 -+#define AR933X_PLL_VAL_10 0x00991099 -+ -+static void __init ar71xx_init_eth_pll_data(unsigned int id) -+{ -+ struct ar71xx_eth_pll_data *pll_data; -+ u32 pll_10, pll_100, pll_1000; -+ -+ switch (id) { -+ case 0: -+ pll_data = &ar71xx_eth0_pll_data; -+ break; -+ case 1: -+ pll_data = &ar71xx_eth1_pll_data; -+ break; -+ default: -+ BUG(); -+ } -+ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7130: -+ case AR71XX_SOC_AR7141: -+ case AR71XX_SOC_AR7161: -+ pll_10 = AR71XX_PLL_VAL_10; -+ pll_100 = AR71XX_PLL_VAL_100; -+ pll_1000 = AR71XX_PLL_VAL_1000; -+ break; -+ -+ case AR71XX_SOC_AR7240: -+ case AR71XX_SOC_AR7241: -+ pll_10 = AR724X_PLL_VAL_10; -+ pll_100 = AR724X_PLL_VAL_100; -+ pll_1000 = AR724X_PLL_VAL_1000; -+ break; -+ -+ case AR71XX_SOC_AR7242: -+ pll_10 = AR7242_PLL_VAL_10; -+ pll_100 = AR7242_PLL_VAL_100; -+ pll_1000 = AR7242_PLL_VAL_1000; -+ break; -+ -+ case AR71XX_SOC_AR9130: -+ case AR71XX_SOC_AR9132: -+ pll_10 = AR91XX_PLL_VAL_10; -+ pll_100 = AR91XX_PLL_VAL_100; -+ pll_1000 = AR91XX_PLL_VAL_1000; -+ break; -+ -+ case AR71XX_SOC_AR9330: -+ case AR71XX_SOC_AR9331: -+ pll_10 = AR933X_PLL_VAL_10; -+ pll_100 = AR933X_PLL_VAL_100; -+ pll_1000 = AR933X_PLL_VAL_1000; -+ break; -+ -+ default: -+ BUG(); -+ } -+ -+ if (!pll_data->pll_10) -+ pll_data->pll_10 = pll_10; -+ -+ if (!pll_data->pll_100) -+ pll_data->pll_100 = pll_100; -+ -+ if (!pll_data->pll_1000) -+ pll_data->pll_1000 = pll_1000; -+} -+ -+static int ar71xx_eth_instance __initdata; -+void __init ar71xx_add_device_eth(unsigned int id) -+{ -+ struct platform_device *pdev; -+ struct ag71xx_platform_data *pdata; -+ -+ ar71xx_init_eth_pll_data(id); -+ -+ switch (id) { -+ case 0: -+ switch (ar71xx_eth0_data.phy_if_mode) { -+ case PHY_INTERFACE_MODE_MII: -+ ar71xx_eth0_data.mii_if = MII0_CTRL_IF_MII; -+ break; -+ case PHY_INTERFACE_MODE_GMII: -+ ar71xx_eth0_data.mii_if = MII0_CTRL_IF_GMII; -+ break; -+ case PHY_INTERFACE_MODE_RGMII: -+ ar71xx_eth0_data.mii_if = MII0_CTRL_IF_RGMII; -+ break; -+ case PHY_INTERFACE_MODE_RMII: -+ ar71xx_eth0_data.mii_if = MII0_CTRL_IF_RMII; -+ break; -+ default: -+ printk(KERN_ERR "ar71xx: invalid PHY interface mode " -+ "for eth0\n"); -+ return; -+ } -+ pdev = &ar71xx_eth0_device; -+ break; -+ case 1: -+ switch (ar71xx_eth1_data.phy_if_mode) { -+ case PHY_INTERFACE_MODE_RMII: -+ ar71xx_eth1_data.mii_if = MII1_CTRL_IF_RMII; -+ break; -+ case PHY_INTERFACE_MODE_RGMII: -+ ar71xx_eth1_data.mii_if = MII1_CTRL_IF_RGMII; -+ break; -+ default: -+ printk(KERN_ERR "ar71xx: invalid PHY interface mode " -+ "for eth1\n"); -+ return; -+ } -+ pdev = &ar71xx_eth1_device; -+ break; -+ default: -+ printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id); -+ return; -+ } -+ -+ pdata = pdev->dev.platform_data; -+ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7130: -+ pdata->ddr_flush = id ? ar71xx_ddr_flush_ge1 -+ : ar71xx_ddr_flush_ge0; -+ pdata->set_pll = id ? ar71xx_set_pll_ge1 -+ : ar71xx_set_pll_ge0; -+ break; -+ -+ case AR71XX_SOC_AR7141: -+ case AR71XX_SOC_AR7161: -+ pdata->ddr_flush = id ? ar71xx_ddr_flush_ge1 -+ : ar71xx_ddr_flush_ge0; -+ pdata->set_pll = id ? ar71xx_set_pll_ge1 -+ : ar71xx_set_pll_ge0; -+ pdata->has_gbit = 1; -+ break; -+ -+ case AR71XX_SOC_AR7242: -+ ar71xx_eth0_data.reset_bit |= AR724X_RESET_GE0_MDIO | -+ RESET_MODULE_GE0_PHY; -+ ar71xx_eth1_data.reset_bit |= AR724X_RESET_GE1_MDIO | -+ RESET_MODULE_GE1_PHY; -+ pdata->ddr_flush = id ? ar724x_ddr_flush_ge1 -+ : ar724x_ddr_flush_ge0; -+ pdata->set_pll = id ? ar724x_set_pll_ge1 -+ : ar7242_set_pll_ge0; -+ pdata->has_gbit = 1; -+ pdata->is_ar724x = 1; -+ -+ if (!pdata->fifo_cfg1) -+ pdata->fifo_cfg1 = 0x0010ffff; -+ if (!pdata->fifo_cfg2) -+ pdata->fifo_cfg2 = 0x015500aa; -+ if (!pdata->fifo_cfg3) -+ pdata->fifo_cfg3 = 0x01f00140; -+ break; -+ -+ case AR71XX_SOC_AR7241: -+ ar71xx_eth0_data.reset_bit |= AR724X_RESET_GE0_MDIO; -+ ar71xx_eth1_data.reset_bit |= AR724X_RESET_GE1_MDIO; -+ /* fall through */ -+ case AR71XX_SOC_AR7240: -+ ar71xx_eth0_data.reset_bit |= RESET_MODULE_GE0_PHY; -+ ar71xx_eth1_data.reset_bit |= RESET_MODULE_GE1_PHY; -+ pdata->ddr_flush = id ? ar724x_ddr_flush_ge1 -+ : ar724x_ddr_flush_ge0; -+ pdata->set_pll = id ? ar724x_set_pll_ge1 -+ : ar724x_set_pll_ge0; -+ pdata->is_ar724x = 1; -+ if (ar71xx_soc == AR71XX_SOC_AR7240) -+ pdata->is_ar7240 = 1; -+ -+ if (!pdata->fifo_cfg1) -+ pdata->fifo_cfg1 = 0x0010ffff; -+ if (!pdata->fifo_cfg2) -+ pdata->fifo_cfg2 = 0x015500aa; -+ if (!pdata->fifo_cfg3) -+ pdata->fifo_cfg3 = 0x01f00140; -+ break; -+ -+ case AR71XX_SOC_AR9130: -+ pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1 -+ : ar91xx_ddr_flush_ge0; -+ pdata->set_pll = id ? ar91xx_set_pll_ge1 -+ : ar91xx_set_pll_ge0; -+ pdata->is_ar91xx = 1; -+ break; -+ -+ case AR71XX_SOC_AR9132: -+ pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1 -+ : ar91xx_ddr_flush_ge0; -+ pdata->set_pll = id ? ar91xx_set_pll_ge1 -+ : ar91xx_set_pll_ge0; -+ pdata->is_ar91xx = 1; -+ pdata->has_gbit = 1; -+ break; -+ -+ case AR71XX_SOC_AR9330: -+ case AR71XX_SOC_AR9331: -+ ar71xx_eth0_data.reset_bit = AR933X_RESET_GE0_MAC | -+ AR933X_RESET_GE0_MDIO; -+ ar71xx_eth1_data.reset_bit = AR933X_RESET_GE1_MAC | -+ AR933X_RESET_GE1_MDIO; -+ pdata->ddr_flush = id ? ar933x_ddr_flush_ge1 -+ : ar933x_ddr_flush_ge0; -+ pdata->set_pll = id ? ar933x_set_pll_ge1 -+ : ar933x_set_pll_ge0; -+ pdata->has_gbit = 1; -+ pdata->is_ar724x = 1; -+ -+ if (!pdata->fifo_cfg1) -+ pdata->fifo_cfg1 = 0x0010ffff; -+ if (!pdata->fifo_cfg2) -+ pdata->fifo_cfg2 = 0x015500aa; -+ if (!pdata->fifo_cfg3) -+ pdata->fifo_cfg3 = 0x01f00140; -+ break; -+ -+ default: -+ BUG(); -+ } -+ -+ switch (pdata->phy_if_mode) { -+ case PHY_INTERFACE_MODE_GMII: -+ case PHY_INTERFACE_MODE_RGMII: -+ if (!pdata->has_gbit) { -+ printk(KERN_ERR "ar71xx: no gbit available on eth%d\n", -+ id); -+ return; -+ } -+ /* fallthrough */ -+ default: -+ break; -+ } -+ -+ if (!is_valid_ether_addr(pdata->mac_addr)) { -+ random_ether_addr(pdata->mac_addr); -+ printk(KERN_DEBUG -+ "ar71xx: using random MAC address for eth%d\n", -+ ar71xx_eth_instance); -+ } -+ -+ if (pdata->mii_bus_dev == NULL) -+ pdata->mii_bus_dev = &ar71xx_mdio_device.dev; -+ -+ /* Reset the device */ -+ ar71xx_device_stop(pdata->reset_bit); -+ mdelay(100); -+ -+ ar71xx_device_start(pdata->reset_bit); -+ mdelay(100); -+ -+ platform_device_register(pdev); -+ ar71xx_eth_instance++; -+} -+ -+static struct resource ar71xx_spi_resources[] = { -+ [0] = { -+ .start = AR71XX_SPI_BASE, -+ .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+}; -+ -+static struct platform_device ar71xx_spi_device = { -+ .name = "ar71xx-spi", -+ .id = -1, -+ .resource = ar71xx_spi_resources, -+ .num_resources = ARRAY_SIZE(ar71xx_spi_resources), -+}; -+ -+void __init ar71xx_add_device_spi(struct ar71xx_spi_platform_data *pdata, -+ struct spi_board_info const *info, -+ unsigned n) -+{ -+ spi_register_board_info(info, n); -+ ar71xx_spi_device.dev.platform_data = pdata; -+ platform_device_register(&ar71xx_spi_device); -+} -+ -+void __init ar71xx_add_device_wdt(void) -+{ -+ platform_device_register_simple("ar71xx-wdt", -1, NULL, 0); -+} -+ -+void __init ar71xx_set_mac_base(unsigned char *mac) -+{ -+ memcpy(ar71xx_mac_base, mac, ETH_ALEN); -+} -+ -+void __init ar71xx_parse_mac_addr(char *mac_str) -+{ -+ u8 tmp[ETH_ALEN]; -+ int t; -+ -+ t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", -+ &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]); -+ -+ if (t != ETH_ALEN) -+ t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx", -+ &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]); -+ -+ if (t == ETH_ALEN) -+ ar71xx_set_mac_base(tmp); -+ else -+ printk(KERN_DEBUG "ar71xx: failed to parse mac address " -+ "\"%s\"\n", mac_str); -+} -+ -+static int __init ar71xx_ethaddr_setup(char *str) -+{ -+ ar71xx_parse_mac_addr(str); -+ return 1; -+} -+__setup("ethaddr=", ar71xx_ethaddr_setup); -+ -+static int __init ar71xx_kmac_setup(char *str) -+{ -+ ar71xx_parse_mac_addr(str); -+ return 1; -+} -+__setup("kmac=", ar71xx_kmac_setup); -+ -+void __init ar71xx_init_mac(unsigned char *dst, const unsigned char *src, -+ unsigned offset) -+{ -+ u32 t; -+ -+ if (!is_valid_ether_addr(src)) { -+ memset(dst, '\0', ETH_ALEN); -+ return; -+ } -+ -+ t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]); -+ t += offset; -+ -+ dst[0] = src[0]; -+ dst[1] = src[1]; -+ dst[2] = src[2]; -+ dst[3] = (t >> 16) & 0xff; -+ dst[4] = (t >> 8) & 0xff; -+ dst[5] = t & 0xff; -+} -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/devices.h linux-2.6.39/arch/mips/ar71xx/devices.h ---- linux-2.6.39.orig/arch/mips/ar71xx/devices.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/devices.h 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,50 @@ -+/* -+ * Atheros AR71xx SoC device definitions -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef __AR71XX_DEVICES_H -+#define __AR71XX_DEVICES_H -+ -+#include -+ -+struct platform_device; -+ -+void ar71xx_add_device_spi(struct ar71xx_spi_platform_data *pdata, -+ struct spi_board_info const *info, -+ unsigned n) __init; -+ -+extern unsigned char ar71xx_mac_base[] __initdata; -+void ar71xx_parse_mac_addr(char *mac_str) __init; -+void ar71xx_init_mac(unsigned char *dst, const unsigned char *src, -+ unsigned offset) __init; -+ -+struct ar71xx_eth_pll_data { -+ u32 pll_10; -+ u32 pll_100; -+ u32 pll_1000; -+}; -+ -+extern struct ar71xx_eth_pll_data ar71xx_eth0_pll_data; -+extern struct ar71xx_eth_pll_data ar71xx_eth1_pll_data; -+ -+extern struct ag71xx_platform_data ar71xx_eth0_data; -+extern struct ag71xx_platform_data ar71xx_eth1_data; -+extern struct platform_device ar71xx_eth0_device; -+extern struct platform_device ar71xx_eth1_device; -+void ar71xx_add_device_eth(unsigned int id) __init; -+ -+extern struct platform_device ar71xx_mdio_device; -+void ar71xx_add_device_mdio(u32 phy_mask) __init; -+ -+void ar71xx_add_device_uart(void) __init; -+ -+void ar71xx_add_device_wdt(void) __init; -+ -+#endif /* __AR71XX_DEVICES_H */ -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/early_printk.c linux-2.6.39/arch/mips/ar71xx/early_printk.c ---- linux-2.6.39.orig/arch/mips/ar71xx/early_printk.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/early_printk.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,96 @@ -+/* -+ * Atheros AR7xxx/AR9xxx SoC early printk support -+ * -+ * Copyright (C) 2008-2011 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+static void (*_prom_putchar) (unsigned char); -+ -+static inline void prom_putchar_wait(void __iomem *reg, u32 mask, u32 val) -+{ -+ u32 t; -+ -+ do { -+ t = __raw_readl(reg); -+ if ((t & mask) == val) -+ break; -+ } while (1); -+} -+ -+static void prom_putchar_ar71xx(unsigned char ch) -+{ -+ void __iomem *base = (void __iomem *)(KSEG1ADDR(AR71XX_UART_BASE)); -+ -+ prom_putchar_wait(base + UART_LSR * 4, UART_LSR_THRE, UART_LSR_THRE); -+ __raw_writel(ch, base + UART_TX * 4); -+ prom_putchar_wait(base + UART_LSR * 4, UART_LSR_THRE, UART_LSR_THRE); -+} -+ -+static void prom_putchar_ar933x(unsigned char ch) -+{ -+ void __iomem *base = (void __iomem *)(KSEG1ADDR(AR933X_UART_BASE)); -+ -+ prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR, -+ AR933X_UART_DATA_TX_CSR); -+ __raw_writel(AR933X_UART_DATA_TX_CSR | ch, base + AR933X_UART_DATA_REG); -+ prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR, -+ AR933X_UART_DATA_TX_CSR); -+} -+ -+static void prom_putchar_dummy(unsigned char ch) -+{ -+ /* nothing to do */ -+} -+ -+static void prom_putchar_init(void) -+{ -+ void __iomem *base; -+ u32 id; -+ -+ base = (void __iomem *)(KSEG1ADDR(AR71XX_RESET_BASE)); -+ id = __raw_readl(base + AR71XX_RESET_REG_REV_ID); -+ id &= REV_ID_MAJOR_MASK; -+ -+ switch (id) { -+ case REV_ID_MAJOR_AR71XX: -+ case REV_ID_MAJOR_AR7240: -+ case REV_ID_MAJOR_AR7241: -+ case REV_ID_MAJOR_AR7242: -+ case REV_ID_MAJOR_AR913X: -+ case REV_ID_MAJOR_AR9341: -+ case REV_ID_MAJOR_AR9342: -+ case REV_ID_MAJOR_AR9344: -+ _prom_putchar = prom_putchar_ar71xx; -+ break; -+ -+ case REV_ID_MAJOR_AR9330: -+ case REV_ID_MAJOR_AR9331: -+ _prom_putchar = prom_putchar_ar933x; -+ break; -+ -+ default: -+ _prom_putchar = prom_putchar_dummy; -+ break; -+ } -+} -+ -+void prom_putchar(unsigned char ch) -+{ -+ if (!_prom_putchar) -+ prom_putchar_init(); -+ -+ _prom_putchar(ch); -+} -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/gpio.c linux-2.6.39/arch/mips/ar71xx/gpio.c ---- linux-2.6.39.orig/arch/mips/ar71xx/gpio.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/gpio.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,193 @@ -+/* -+ * Atheros AR7XXX/AR9XXX SoC GPIO API support -+ * -+ * Copyright (C) 2008-2011 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+static DEFINE_SPINLOCK(ar71xx_gpio_lock); -+ -+unsigned long ar71xx_gpio_count; -+EXPORT_SYMBOL(ar71xx_gpio_count); -+ -+void __ar71xx_gpio_set_value(unsigned gpio, int value) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ -+ if (value) -+ __raw_writel(1 << gpio, base + GPIO_REG_SET); -+ else -+ __raw_writel(1 << gpio, base + GPIO_REG_CLEAR); -+} -+EXPORT_SYMBOL(__ar71xx_gpio_set_value); -+ -+int __ar71xx_gpio_get_value(unsigned gpio) -+{ -+ return (__raw_readl(ar71xx_gpio_base + GPIO_REG_IN) >> gpio) & 1; -+} -+EXPORT_SYMBOL(__ar71xx_gpio_get_value); -+ -+static int ar71xx_gpio_get_value(struct gpio_chip *chip, unsigned offset) -+{ -+ return __ar71xx_gpio_get_value(offset); -+} -+ -+static void ar71xx_gpio_set_value(struct gpio_chip *chip, -+ unsigned offset, int value) -+{ -+ __ar71xx_gpio_set_value(offset, value); -+} -+ -+static int ar71xx_gpio_direction_input(struct gpio_chip *chip, -+ unsigned offset) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&ar71xx_gpio_lock, flags); -+ -+ __raw_writel(__raw_readl(base + GPIO_REG_OE) & ~(1 << offset), -+ base + GPIO_REG_OE); -+ -+ spin_unlock_irqrestore(&ar71xx_gpio_lock, flags); -+ -+ return 0; -+} -+ -+static int ar71xx_gpio_direction_output(struct gpio_chip *chip, -+ unsigned offset, int value) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&ar71xx_gpio_lock, flags); -+ -+ if (value) -+ __raw_writel(1 << offset, base + GPIO_REG_SET); -+ else -+ __raw_writel(1 << offset, base + GPIO_REG_CLEAR); -+ -+ __raw_writel(__raw_readl(base + GPIO_REG_OE) | (1 << offset), -+ base + GPIO_REG_OE); -+ -+ spin_unlock_irqrestore(&ar71xx_gpio_lock, flags); -+ -+ return 0; -+} -+ -+static struct gpio_chip ar71xx_gpio_chip = { -+ .label = "ar71xx", -+ .get = ar71xx_gpio_get_value, -+ .set = ar71xx_gpio_set_value, -+ .direction_input = ar71xx_gpio_direction_input, -+ .direction_output = ar71xx_gpio_direction_output, -+ .base = 0, -+ .ngpio = AR71XX_GPIO_COUNT, -+}; -+ -+void ar71xx_gpio_function_enable(u32 mask) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&ar71xx_gpio_lock, flags); -+ -+ __raw_writel(__raw_readl(base + GPIO_REG_FUNC) | mask, -+ base + GPIO_REG_FUNC); -+ /* flush write */ -+ (void) __raw_readl(base + GPIO_REG_FUNC); -+ -+ spin_unlock_irqrestore(&ar71xx_gpio_lock, flags); -+} -+ -+void ar71xx_gpio_function_disable(u32 mask) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&ar71xx_gpio_lock, flags); -+ -+ __raw_writel(__raw_readl(base + GPIO_REG_FUNC) & ~mask, -+ base + GPIO_REG_FUNC); -+ /* flush write */ -+ (void) __raw_readl(base + GPIO_REG_FUNC); -+ -+ spin_unlock_irqrestore(&ar71xx_gpio_lock, flags); -+} -+ -+void ar71xx_gpio_function_setup(u32 set, u32 clear) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&ar71xx_gpio_lock, flags); -+ -+ __raw_writel((__raw_readl(base + GPIO_REG_FUNC) & ~clear) | set, -+ base + GPIO_REG_FUNC); -+ /* flush write */ -+ (void) __raw_readl(base + GPIO_REG_FUNC); -+ -+ spin_unlock_irqrestore(&ar71xx_gpio_lock, flags); -+} -+EXPORT_SYMBOL(ar71xx_gpio_function_setup); -+ -+void __init ar71xx_gpio_init(void) -+{ -+ int err; -+ -+ if (!request_mem_region(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE, -+ "AR71xx GPIO controller")) -+ panic("cannot allocate AR71xx GPIO registers page"); -+ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7130: -+ case AR71XX_SOC_AR7141: -+ case AR71XX_SOC_AR7161: -+ ar71xx_gpio_chip.ngpio = AR71XX_GPIO_COUNT; -+ break; -+ -+ case AR71XX_SOC_AR7240: -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ ar71xx_gpio_chip.ngpio = AR724X_GPIO_COUNT; -+ break; -+ -+ case AR71XX_SOC_AR9130: -+ case AR71XX_SOC_AR9132: -+ ar71xx_gpio_chip.ngpio = AR91XX_GPIO_COUNT; -+ break; -+ -+ case AR71XX_SOC_AR9330: -+ case AR71XX_SOC_AR9331: -+ ar71xx_gpio_chip.ngpio = AR933X_GPIO_COUNT; -+ break; -+ -+ case AR71XX_SOC_AR9341: -+ case AR71XX_SOC_AR9342: -+ case AR71XX_SOC_AR9344: -+ ar71xx_gpio_chip.ngpio = AR934X_GPIO_COUNT; -+ break; -+ -+ default: -+ BUG(); -+ } -+ -+ err = gpiochip_add(&ar71xx_gpio_chip); -+ if (err) -+ panic("cannot add AR71xx GPIO chip, error=%d", err); -+} -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/irq.c linux-2.6.39/arch/mips/ar71xx/irq.c ---- linux-2.6.39.orig/arch/mips/ar71xx/irq.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/irq.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,377 @@ -+/* -+ * Atheros AR71xx SoC specific interrupt handling -+ * -+ * Copyright (C) 2010-2011 Jaiganesh Narayanan -+ * Copyright (C) 2008-2010 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros 2.6.15 BSP -+ * Parts of this file are based on Atheros 2.6.31 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include -+ -+static void ar71xx_gpio_irq_dispatch(void) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ u32 pending; -+ -+ pending = __raw_readl(base + GPIO_REG_INT_PENDING) & -+ __raw_readl(base + GPIO_REG_INT_ENABLE); -+ -+ if (pending) -+ do_IRQ(AR71XX_GPIO_IRQ_BASE + fls(pending) - 1); -+ else -+ spurious_interrupt(); -+} -+ -+static void ar71xx_gpio_irq_unmask(struct irq_data *d) -+{ -+ unsigned int irq = d->irq - AR71XX_GPIO_IRQ_BASE; -+ void __iomem *base = ar71xx_gpio_base; -+ u32 t; -+ -+ t = __raw_readl(base + GPIO_REG_INT_ENABLE); -+ __raw_writel(t | (1 << irq), base + GPIO_REG_INT_ENABLE); -+ -+ /* flush write */ -+ (void) __raw_readl(base + GPIO_REG_INT_ENABLE); -+} -+ -+static void ar71xx_gpio_irq_mask(struct irq_data *d) -+{ -+ unsigned int irq = d->irq - AR71XX_GPIO_IRQ_BASE; -+ void __iomem *base = ar71xx_gpio_base; -+ u32 t; -+ -+ t = __raw_readl(base + GPIO_REG_INT_ENABLE); -+ __raw_writel(t & ~(1 << irq), base + GPIO_REG_INT_ENABLE); -+ -+ /* flush write */ -+ (void) __raw_readl(base + GPIO_REG_INT_ENABLE); -+} -+ -+static struct irq_chip ar71xx_gpio_irq_chip = { -+ .name = "AR71XX GPIO", -+ .irq_unmask = ar71xx_gpio_irq_unmask, -+ .irq_mask = ar71xx_gpio_irq_mask, -+ .irq_mask_ack = ar71xx_gpio_irq_mask, -+}; -+ -+static struct irqaction ar71xx_gpio_irqaction = { -+ .handler = no_action, -+ .name = "cascade [AR71XX GPIO]", -+}; -+ -+#define GPIO_INT_ALL 0xffff -+ -+static void __init ar71xx_gpio_irq_init(void) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ int i; -+ -+ __raw_writel(0, base + GPIO_REG_INT_ENABLE); -+ __raw_writel(0, base + GPIO_REG_INT_PENDING); -+ -+ /* setup type of all GPIO interrupts to level sensitive */ -+ __raw_writel(GPIO_INT_ALL, base + GPIO_REG_INT_TYPE); -+ -+ /* setup polarity of all GPIO interrupts to active high */ -+ __raw_writel(GPIO_INT_ALL, base + GPIO_REG_INT_POLARITY); -+ -+ for (i = AR71XX_GPIO_IRQ_BASE; -+ i < AR71XX_GPIO_IRQ_BASE + AR71XX_GPIO_IRQ_COUNT; i++) -+ irq_set_chip_and_handler(i, &ar71xx_gpio_irq_chip, -+ handle_level_irq); -+ -+ setup_irq(AR71XX_MISC_IRQ_GPIO, &ar71xx_gpio_irqaction); -+} -+ -+static void ar71xx_misc_irq_dispatch(void) -+{ -+ u32 pending; -+ -+ pending = ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS) -+ & ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE); -+ -+ if (pending & MISC_INT_UART) -+ do_IRQ(AR71XX_MISC_IRQ_UART); -+ -+ else if (pending & MISC_INT_DMA) -+ do_IRQ(AR71XX_MISC_IRQ_DMA); -+ -+ else if (pending & MISC_INT_PERFC) -+ do_IRQ(AR71XX_MISC_IRQ_PERFC); -+ -+ else if (pending & MISC_INT_TIMER) -+ do_IRQ(AR71XX_MISC_IRQ_TIMER); -+ -+ else if (pending & MISC_INT_OHCI) -+ do_IRQ(AR71XX_MISC_IRQ_OHCI); -+ -+ else if (pending & MISC_INT_ERROR) -+ do_IRQ(AR71XX_MISC_IRQ_ERROR); -+ -+ else if (pending & MISC_INT_GPIO) -+ ar71xx_gpio_irq_dispatch(); -+ -+ else if (pending & MISC_INT_WDOG) -+ do_IRQ(AR71XX_MISC_IRQ_WDOG); -+ -+ else if (pending & MISC_INT_TIMER2) -+ do_IRQ(AR71XX_MISC_IRQ_TIMER2); -+ -+ else if (pending & MISC_INT_TIMER3) -+ do_IRQ(AR71XX_MISC_IRQ_TIMER3); -+ -+ else if (pending & MISC_INT_TIMER4) -+ do_IRQ(AR71XX_MISC_IRQ_TIMER4); -+ -+ else if (pending & MISC_INT_DDR_PERF) -+ do_IRQ(AR71XX_MISC_IRQ_DDR_PERF); -+ -+ else if (pending & MISC_INT_ENET_LINK) -+ do_IRQ(AR71XX_MISC_IRQ_ENET_LINK); -+ -+ else -+ spurious_interrupt(); -+} -+ -+static void ar71xx_misc_irq_unmask(struct irq_data *d) -+{ -+ unsigned int irq = d->irq - AR71XX_MISC_IRQ_BASE; -+ void __iomem *base = ar71xx_reset_base; -+ u32 t; -+ -+ t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); -+ __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE); -+ -+ /* flush write */ -+ (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); -+} -+ -+static void ar71xx_misc_irq_mask(struct irq_data *d) -+{ -+ unsigned int irq = d->irq - AR71XX_MISC_IRQ_BASE; -+ void __iomem *base = ar71xx_reset_base; -+ u32 t; -+ -+ t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); -+ __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE); -+ -+ /* flush write */ -+ (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); -+} -+ -+static void ar724x_misc_irq_ack(struct irq_data *d) -+{ -+ unsigned int irq = d->irq - AR71XX_MISC_IRQ_BASE; -+ void __iomem *base = ar71xx_reset_base; -+ u32 t; -+ -+ t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS); -+ __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_STATUS); -+ -+ /* flush write */ -+ (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS); -+} -+ -+static struct irq_chip ar71xx_misc_irq_chip = { -+ .name = "AR71XX MISC", -+ .irq_unmask = ar71xx_misc_irq_unmask, -+ .irq_mask = ar71xx_misc_irq_mask, -+}; -+ -+static struct irqaction ar71xx_misc_irqaction = { -+ .handler = no_action, -+ .name = "cascade [AR71XX MISC]", -+}; -+ -+static void __init ar71xx_misc_irq_init(void) -+{ -+ void __iomem *base = ar71xx_reset_base; -+ int i; -+ -+ __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE); -+ __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS); -+ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7240: -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ case AR71XX_SOC_AR9330: -+ case AR71XX_SOC_AR9331: -+ case AR71XX_SOC_AR9341: -+ case AR71XX_SOC_AR9342: -+ case AR71XX_SOC_AR9344: -+ ar71xx_misc_irq_chip.irq_ack = ar724x_misc_irq_ack; -+ break; -+ default: -+ ar71xx_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask; -+ break; -+ } -+ -+ for (i = AR71XX_MISC_IRQ_BASE; -+ i < AR71XX_MISC_IRQ_BASE + AR71XX_MISC_IRQ_COUNT; i++) -+ irq_set_chip_and_handler(i, &ar71xx_misc_irq_chip, -+ handle_level_irq); -+ -+ setup_irq(AR71XX_CPU_IRQ_MISC, &ar71xx_misc_irqaction); -+} -+ -+/* -+ * The IP2/IP3 lines are tied to a PCI/WMAC/USB device. Drivers for -+ * these devices typically allocate coherent DMA memory, however the -+ * DMA controller may still have some unsynchronized data in the FIFO. -+ * Issue a flush in the handlers to ensure that the driver sees -+ * the update. -+ */ -+static void ar71xx_ip2_handler(void) -+{ -+ ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_PCI); -+ do_IRQ(AR71XX_CPU_IRQ_IP2); -+} -+ -+static void ar724x_ip2_handler(void) -+{ -+ ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_PCIE); -+ do_IRQ(AR71XX_CPU_IRQ_IP2); -+} -+ -+static void ar913x_ip2_handler(void) -+{ -+ ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_WMAC); -+ do_IRQ(AR71XX_CPU_IRQ_IP2); -+} -+ -+static void ar933x_ip2_handler(void) -+{ -+ ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_WMAC); -+ do_IRQ(AR71XX_CPU_IRQ_IP2); -+} -+ -+static void ar934x_ip2_handler(void) -+{ -+ ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_PCIE); -+ do_IRQ(AR71XX_CPU_IRQ_IP2); -+} -+ -+static void ar71xx_ip3_handler(void) -+{ -+ ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_USB); -+ do_IRQ(AR71XX_CPU_IRQ_USB); -+} -+ -+static void ar724x_ip3_handler(void) -+{ -+ ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_USB); -+ do_IRQ(AR71XX_CPU_IRQ_USB); -+} -+ -+static void ar913x_ip3_handler(void) -+{ -+ ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_USB); -+ do_IRQ(AR71XX_CPU_IRQ_USB); -+} -+ -+static void ar933x_ip3_handler(void) -+{ -+ ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_USB); -+ do_IRQ(AR71XX_CPU_IRQ_USB); -+} -+ -+static void ar934x_ip3_handler(void) -+{ -+ do_IRQ(AR71XX_CPU_IRQ_USB); -+} -+ -+static void (*ip2_handler)(void); -+static void (*ip3_handler)(void); -+ -+asmlinkage void plat_irq_dispatch(void) -+{ -+ unsigned long pending; -+ -+ pending = read_c0_status() & read_c0_cause() & ST0_IM; -+ -+ if (pending & STATUSF_IP7) -+ do_IRQ(AR71XX_CPU_IRQ_TIMER); -+ -+ else if (pending & STATUSF_IP2) -+ ip2_handler(); -+ -+ else if (pending & STATUSF_IP4) -+ do_IRQ(AR71XX_CPU_IRQ_GE0); -+ -+ else if (pending & STATUSF_IP5) -+ do_IRQ(AR71XX_CPU_IRQ_GE1); -+ -+ else if (pending & STATUSF_IP3) -+ ip3_handler(); -+ -+ else if (pending & STATUSF_IP6) -+ ar71xx_misc_irq_dispatch(); -+ -+ spurious_interrupt(); -+} -+ -+void __init arch_init_irq(void) -+{ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7130: -+ case AR71XX_SOC_AR7141: -+ case AR71XX_SOC_AR7161: -+ ip2_handler = ar71xx_ip2_handler; -+ ip3_handler = ar71xx_ip3_handler; -+ break; -+ -+ case AR71XX_SOC_AR7240: -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ ip2_handler = ar724x_ip2_handler; -+ ip3_handler = ar724x_ip3_handler; -+ break; -+ -+ case AR71XX_SOC_AR9130: -+ case AR71XX_SOC_AR9132: -+ ip2_handler = ar913x_ip2_handler; -+ ip3_handler = ar913x_ip3_handler; -+ break; -+ -+ case AR71XX_SOC_AR9330: -+ case AR71XX_SOC_AR9331: -+ ip2_handler = ar933x_ip2_handler; -+ ip3_handler = ar933x_ip3_handler; -+ break; -+ -+ case AR71XX_SOC_AR9341: -+ case AR71XX_SOC_AR9342: -+ case AR71XX_SOC_AR9344: -+ ip2_handler = ar934x_ip2_handler; -+ ip3_handler = ar934x_ip3_handler; -+ break; -+ -+ default: -+ BUG(); -+ } -+ -+ mips_cpu_irq_init(); -+ -+ ar71xx_misc_irq_init(); -+ -+ cp0_perfcount_irq = AR71XX_MISC_IRQ_PERFC; -+ -+ ar71xx_gpio_irq_init(); -+} -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-ap121.c linux-2.6.39/arch/mips/ar71xx/mach-ap121.c ---- linux-2.6.39.orig/arch/mips/ar71xx/mach-ap121.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/mach-ap121.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,245 @@ -+/* -+ * Atheros AP121 board support -+ * -+ * Copyright (C) 2011 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-ar9xxx-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-m25p80.h" -+#include "dev-usb.h" -+ -+#define AP121_GPIO_LED_WLAN 0 -+#define AP121_GPIO_LED_USB 1 -+ -+#define AP121_GPIO_BTN_JUMPSTART 11 -+#define AP121_GPIO_BTN_RESET 12 -+ -+#define AP121_KEYS_POLL_INTERVAL 20 /* msecs */ -+#define AP121_KEYS_DEBOUNCE_INTERVAL (3 * AP121_KEYS_POLL_INTERVAL) -+ -+#define AP121_MAC0_OFFSET 0x0000 -+#define AP121_MAC1_OFFSET 0x0006 -+#define AP121_CALDATA_OFFSET 0x1000 -+#define AP121_WMAC_MAC_OFFSET 0x1002 -+ -+#define AP121_MINI_GPIO_LED_WLAN 0 -+#define AP121_MINI_GPIO_BTN_JUMPSTART 12 -+#define AP121_MINI_GPIO_BTN_RESET 11 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition ap121_parts[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ }, -+ { -+ .name = "rootfs", -+ .offset = 0x010000, -+ .size = 0x130000, -+ }, -+ { -+ .name = "uImage", -+ .offset = 0x140000, -+ .size = 0x0a0000, -+ }, -+ { -+ .name = "NVRAM", -+ .offset = 0x1e0000, -+ .size = 0x010000, -+ }, -+ { -+ .name = "ART", -+ .offset = 0x1f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ }, -+}; -+#define ap121_nr_parts ARRAY_SIZE(ap121_parts) -+ -+static struct mtd_partition ap121_mini_parts[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x040000, -+ .mask_flags = MTD_WRITEABLE, -+ }, -+ { -+ .name = "u-boot-env", -+ .offset = 0x040000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ }, -+ { -+ .name = "rootfs", -+ .offset = 0x050000, -+ .size = 0x2b0000, -+ }, -+ { -+ .name = "uImage", -+ .offset = 0x300000, -+ .size = 0x0e0000, -+ }, -+ { -+ .name = "NVRAM", -+ .offset = 0x3e0000, -+ .size = 0x010000, -+ }, -+ { -+ .name = "ART", -+ .offset = 0x3f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ }, -+}; -+ -+#define ap121_mini_nr_parts ARRAY_SIZE(ap121_parts) -+ -+#else -+#define ap121_parts NULL -+#define ap121_nr_parts 0 -+#define ap121_mini_parts NULL -+#define ap121_mini_nr_parts 0 -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data ap121_flash_data = { -+ .parts = ap121_parts, -+ .nr_parts = ap121_nr_parts, -+}; -+ -+static struct gpio_led ap121_leds_gpio[] __initdata = { -+ { -+ .name = "ap121:green:usb", -+ .gpio = AP121_GPIO_LED_USB, -+ .active_low = 0, -+ }, -+ { -+ .name = "ap121:green:wlan", -+ .gpio = AP121_GPIO_LED_WLAN, -+ .active_low = 0, -+ }, -+}; -+ -+static struct gpio_keys_button ap121_gpio_keys[] __initdata = { -+ { -+ .desc = "jumpstart button", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = AP121_GPIO_BTN_JUMPSTART, -+ .active_low = 1, -+ }, -+ { -+ .desc = "reset button", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = AP121_GPIO_BTN_RESET, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_led ap121_mini_leds_gpio[] __initdata = { -+ { -+ .name = "ap121:green:wlan", -+ .gpio = AP121_MINI_GPIO_LED_WLAN, -+ .active_low = 0, -+ }, -+}; -+ -+static struct gpio_keys_button ap121_mini_gpio_keys[] __initdata = { -+ { -+ .desc = "jumpstart button", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = AP121_MINI_GPIO_BTN_JUMPSTART, -+ .active_low = 1, -+ }, -+ { -+ .desc = "reset button", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .debounce_interval = AP121_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = AP121_MINI_GPIO_BTN_RESET, -+ .active_low = 1, -+ } -+}; -+ -+static void __init ap121_common_setup(void) -+{ -+ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); -+ -+ ar71xx_add_device_m25p80(&ap121_flash_data); -+ -+ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, art + AP121_MAC0_OFFSET, 0); -+ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, art + AP121_MAC1_OFFSET, 0); -+ -+ /* WAN port */ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ ar71xx_eth0_data.phy_mask = BIT(4); -+ -+ /* LAN ports */ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.speed = SPEED_1000; -+ ar71xx_eth1_data.duplex = DUPLEX_FULL; -+ ar71xx_eth1_data.has_ar7240_switch = 1; -+ -+ ar71xx_add_device_mdio(0x0); -+ ar71xx_add_device_eth(1); -+ ar71xx_add_device_eth(0); -+ -+ ar9xxx_add_device_wmac(art + AP121_CALDATA_OFFSET, -+ art + AP121_WMAC_MAC_OFFSET); -+} -+ -+static void __init ap121_setup(void) -+{ -+ ap121_flash_data.parts = ap121_parts; -+ ap121_flash_data.nr_parts = ap121_nr_parts; -+ -+ ap121_common_setup(); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ap121_leds_gpio), -+ ap121_leds_gpio); -+ ar71xx_register_gpio_keys_polled(-1, AP121_KEYS_POLL_INTERVAL, -+ ARRAY_SIZE(ap121_gpio_keys), -+ ap121_gpio_keys); -+ -+ ar71xx_add_device_usb(); -+} -+ -+static void __init ap121_mini_setup(void) -+{ -+ ap121_flash_data.parts = ap121_mini_parts; -+ ap121_flash_data.nr_parts = ap121_mini_nr_parts; -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ap121_mini_leds_gpio), -+ ap121_mini_leds_gpio); -+ ar71xx_register_gpio_keys_polled(-1, AP121_KEYS_POLL_INTERVAL, -+ ARRAY_SIZE(ap121_mini_gpio_keys), -+ ap121_mini_gpio_keys); -+ -+ ap121_common_setup(); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_AP121, "AP121", "Atheros AP121", -+ ap121_setup); -+ -+MIPS_MACHINE(AR71XX_MACH_AP121_MINI, "AP121-MINI", "Atheros AP121-MINI", -+ ap121_mini_setup); -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-ap81.c linux-2.6.39/arch/mips/ar71xx/mach-ap81.c ---- linux-2.6.39.orig/arch/mips/ar71xx/mach-ap81.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/mach-ap81.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,142 @@ -+/* -+ * Atheros AP81 board support -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * Copyright (C) 2009 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ar9xxx-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-usb.h" -+ -+#define AP81_GPIO_LED_STATUS 1 -+#define AP81_GPIO_LED_AOSS 3 -+#define AP81_GPIO_LED_WLAN 6 -+#define AP81_GPIO_LED_POWER 14 -+ -+#define AP81_GPIO_BTN_SW4 12 -+#define AP81_GPIO_BTN_SW1 21 -+ -+#define AP81_KEYS_POLL_INTERVAL 20 /* msecs */ -+#define AP81_KEYS_DEBOUNCE_INTERVAL (3 * AP81_KEYS_POLL_INTERVAL) -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition ap81_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x040000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "u-boot-env", -+ .offset = 0x040000, -+ .size = 0x010000, -+ }, { -+ .name = "rootfs", -+ .offset = 0x050000, -+ .size = 0x500000, -+ }, { -+ .name = "uImage", -+ .offset = 0x550000, -+ .size = 0x100000, -+ }, { -+ .name = "ART", -+ .offset = 0x650000, -+ .size = 0x1b0000, -+ .mask_flags = MTD_WRITEABLE, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data ap81_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = ap81_partitions, -+ .nr_parts = ARRAY_SIZE(ap81_partitions), -+#endif -+}; -+ -+static struct gpio_led ap81_leds_gpio[] __initdata = { -+ { -+ .name = "ap81:green:status", -+ .gpio = AP81_GPIO_LED_STATUS, -+ .active_low = 1, -+ }, { -+ .name = "ap81:amber:aoss", -+ .gpio = AP81_GPIO_LED_AOSS, -+ .active_low = 1, -+ }, { -+ .name = "ap81:green:wlan", -+ .gpio = AP81_GPIO_LED_WLAN, -+ .active_low = 1, -+ }, { -+ .name = "ap81:green:power", -+ .gpio = AP81_GPIO_LED_POWER, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_keys_button ap81_gpio_keys[] __initdata = { -+ { -+ .desc = "sw1", -+ .type = EV_KEY, -+ .code = BTN_0, -+ .debounce_interval = AP81_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = AP81_GPIO_BTN_SW1, -+ .active_low = 1, -+ }, { -+ .desc = "sw4", -+ .type = EV_KEY, -+ .code = BTN_1, -+ .debounce_interval = AP81_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = AP81_GPIO_BTN_SW4, -+ .active_low = 1, -+ } -+}; -+ -+static void __init ap81_setup(void) -+{ -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ -+ ar71xx_add_device_mdio(0x0); -+ -+ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, eeprom, 0); -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ ar71xx_eth0_data.has_ar8216 = 1; -+ -+ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, eeprom, 1); -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.phy_mask = 0x10; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_usb(); -+ -+ ar71xx_add_device_m25p80(&ap81_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ap81_leds_gpio), -+ ap81_leds_gpio); -+ -+ ar71xx_register_gpio_keys_polled(-1, AP81_KEYS_POLL_INTERVAL, -+ ARRAY_SIZE(ap81_gpio_keys), -+ ap81_gpio_keys); -+ -+ ar9xxx_add_device_wmac(eeprom, NULL); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_AP81, "AP81", "Atheros AP81", ap81_setup); -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-ap83.c linux-2.6.39/arch/mips/ar71xx/mach-ap83.c ---- linux-2.6.39.orig/arch/mips/ar71xx/mach-ap83.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/mach-ap83.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,267 @@ -+/* -+ * Atheros AP83 board support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-ar9xxx-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-usb.h" -+ -+#define AP83_GPIO_LED_WLAN 6 -+#define AP83_GPIO_LED_POWER 14 -+#define AP83_GPIO_LED_JUMPSTART 15 -+#define AP83_GPIO_BTN_JUMPSTART 12 -+#define AP83_GPIO_BTN_RESET 21 -+ -+#define AP83_050_GPIO_VSC7385_CS 1 -+#define AP83_050_GPIO_VSC7385_MISO 3 -+#define AP83_050_GPIO_VSC7385_MOSI 16 -+#define AP83_050_GPIO_VSC7385_SCK 17 -+ -+#define AP83_KEYS_POLL_INTERVAL 20 /* msecs */ -+#define AP83_KEYS_DEBOUNCE_INTERVAL (3 * AP83_KEYS_POLL_INTERVAL) -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition ap83_flash_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x040000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "u-boot-env", -+ .offset = 0x040000, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "kernel", -+ .offset = 0x060000, -+ .size = 0x140000, -+ }, { -+ .name = "rootfs", -+ .offset = 0x1a0000, -+ .size = 0x650000, -+ }, { -+ .name = "art", -+ .offset = 0x7f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "firmware", -+ .offset = 0x060000, -+ .size = 0x790000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct ar91xx_flash_platform_data ap83_flash_data = { -+ .width = 2, -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = ap83_flash_partitions, -+ .nr_parts = ARRAY_SIZE(ap83_flash_partitions), -+#endif -+}; -+ -+static struct resource ap83_flash_resources[] = { -+ [0] = { -+ .start = AR71XX_SPI_BASE, -+ .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+}; -+ -+static struct platform_device ap83_flash_device = { -+ .name = "ar91xx-flash", -+ .id = -1, -+ .resource = ap83_flash_resources, -+ .num_resources = ARRAY_SIZE(ap83_flash_resources), -+ .dev = { -+ .platform_data = &ap83_flash_data, -+ } -+}; -+ -+static struct gpio_led ap83_leds_gpio[] __initdata = { -+ { -+ .name = "ap83:green:jumpstart", -+ .gpio = AP83_GPIO_LED_JUMPSTART, -+ .active_low = 0, -+ }, { -+ .name = "ap83:green:power", -+ .gpio = AP83_GPIO_LED_POWER, -+ .active_low = 0, -+ }, { -+ .name = "ap83:green:wlan", -+ .gpio = AP83_GPIO_LED_WLAN, -+ .active_low = 0, -+ }, -+}; -+ -+static struct gpio_keys_button ap83_gpio_keys[] __initdata = { -+ { -+ .desc = "soft_reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .debounce_interval = AP83_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = AP83_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "jumpstart", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .debounce_interval = AP83_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = AP83_GPIO_BTN_JUMPSTART, -+ .active_low = 1, -+ } -+}; -+ -+static struct resource ap83_040_spi_resources[] = { -+ [0] = { -+ .start = AR71XX_SPI_BASE, -+ .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+}; -+ -+static struct platform_device ap83_040_spi_device = { -+ .name = "ap83-spi", -+ .id = 0, -+ .resource = ap83_040_spi_resources, -+ .num_resources = ARRAY_SIZE(ap83_040_spi_resources), -+}; -+ -+static struct spi_gpio_platform_data ap83_050_spi_data = { -+ .miso = AP83_050_GPIO_VSC7385_MISO, -+ .mosi = AP83_050_GPIO_VSC7385_MOSI, -+ .sck = AP83_050_GPIO_VSC7385_SCK, -+ .num_chipselect = 1, -+}; -+ -+static struct platform_device ap83_050_spi_device = { -+ .name = "spi_gpio", -+ .id = 0, -+ .dev = { -+ .platform_data = &ap83_050_spi_data, -+ } -+}; -+ -+static void ap83_vsc7385_reset(void) -+{ -+ ar71xx_device_stop(RESET_MODULE_GE1_PHY); -+ udelay(10); -+ ar71xx_device_start(RESET_MODULE_GE1_PHY); -+ mdelay(50); -+} -+ -+static struct vsc7385_platform_data ap83_vsc7385_data = { -+ .reset = ap83_vsc7385_reset, -+ .ucode_name = "vsc7385_ucode_ap83.bin", -+ .mac_cfg = { -+ .tx_ipg = 6, -+ .bit2 = 0, -+ .clk_sel = 3, -+ }, -+}; -+ -+static struct spi_board_info ap83_spi_info[] = { -+ { -+ .bus_num = 0, -+ .chip_select = 0, -+ .max_speed_hz = 25000000, -+ .modalias = "spi-vsc7385", -+ .platform_data = &ap83_vsc7385_data, -+ .controller_data = (void *) AP83_050_GPIO_VSC7385_CS, -+ } -+}; -+ -+static void __init ap83_generic_setup(void) -+{ -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ -+ ar71xx_add_device_mdio(0xfffffffe); -+ -+ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, eeprom, 0); -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth0_data.phy_mask = 0x1; -+ -+ ar71xx_add_device_eth(0); -+ -+ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, eeprom, 1); -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth1_data.speed = SPEED_1000; -+ ar71xx_eth1_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_eth1_pll_data.pll_1000 = 0x1f000000; -+ -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ap83_leds_gpio), -+ ap83_leds_gpio); -+ -+ ar71xx_register_gpio_keys_polled(-1, AP83_KEYS_POLL_INTERVAL, -+ ARRAY_SIZE(ap83_gpio_keys), -+ ap83_gpio_keys); -+ -+ ar71xx_add_device_usb(); -+ -+ ar9xxx_add_device_wmac(eeprom, NULL); -+ -+ platform_device_register(&ap83_flash_device); -+ -+ spi_register_board_info(ap83_spi_info, ARRAY_SIZE(ap83_spi_info)); -+} -+ -+static void __init ap83_040_setup(void) -+{ -+ ap83_flash_data.is_shared = 1; -+ ap83_generic_setup(); -+ platform_device_register(&ap83_040_spi_device); -+} -+ -+static void __init ap83_050_setup(void) -+{ -+ ap83_generic_setup(); -+ platform_device_register(&ap83_050_spi_device); -+} -+ -+static void __init ap83_setup(void) -+{ -+ u8 *board_id = (u8 *) KSEG1ADDR(0x1fff1244); -+ unsigned int board_version; -+ -+ board_version = (unsigned int)(board_id[0] - '0'); -+ board_version += ((unsigned int)(board_id[1] - '0')) * 10; -+ -+ switch (board_version) { -+ case 40: -+ ap83_040_setup(); -+ break; -+ case 50: -+ ap83_050_setup(); -+ break; -+ default: -+ printk(KERN_WARNING "AP83-%03u board is not yet supported\n", -+ board_version); -+ } -+} -+ -+MIPS_MACHINE(AR71XX_MACH_AP83, "AP83", "Atheros AP83", ap83_setup); -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-ap96.c linux-2.6.39/arch/mips/ar71xx/mach-ap96.c ---- linux-2.6.39.orig/arch/mips/ar71xx/mach-ap96.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/mach-ap96.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,180 @@ -+/* -+ * Atheros AP96 board support -+ * -+ * Copyright (C) 2009 Marco Porsch -+ * Copyright (C) 2009-2010 Gabor Juhos -+ * Copyright (C) 2010 Atheros Communications -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ap94-pci.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-usb.h" -+ -+#define AP96_GPIO_LED_12_GREEN 0 -+#define AP96_GPIO_LED_3_GREEN 1 -+#define AP96_GPIO_LED_2_GREEN 2 -+#define AP96_GPIO_LED_WPS_GREEN 4 -+#define AP96_GPIO_LED_5_GREEN 5 -+#define AP96_GPIO_LED_4_ORANGE 6 -+ -+/* Reset button - next to the power connector */ -+#define AP96_GPIO_BTN_RESET 3 -+/* WPS button - next to a led on right */ -+#define AP96_GPIO_BTN_WPS 8 -+ -+#define AP96_KEYS_POLL_INTERVAL 20 /* msecs */ -+#define AP96_KEYS_DEBOUNCE_INTERVAL (3 * AP96_KEYS_POLL_INTERVAL) -+ -+#define AP96_WMAC0_MAC_OFFSET 0x120c -+#define AP96_WMAC1_MAC_OFFSET 0x520c -+#define AP96_CALDATA0_OFFSET 0x1000 -+#define AP96_CALDATA1_OFFSET 0x5000 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition ap96_partitions[] = { -+ { -+ .name = "uboot", -+ .offset = 0, -+ .size = 0x030000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "env", -+ .offset = 0x030000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "rootfs", -+ .offset = 0x040000, -+ .size = 0x600000, -+ }, { -+ .name = "uImage", -+ .offset = 0x640000, -+ .size = 0x1b0000, -+ }, { -+ .name = "caldata", -+ .offset = 0x7f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data ap96_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = ap96_partitions, -+ .nr_parts = ARRAY_SIZE(ap96_partitions), -+#endif -+}; -+ -+/* -+ * AP96 has 12 unlabeled leds in the front; these are numbered from 1 to 12 -+ * below (from left to right on the board). Led 1 seems to be on whenever the -+ * board is powered. Led 11 shows LAN link activity actity. Led 3 is orange; -+ * others are green. -+ * -+ * In addition, there is one led next to a button on the right side for WPS. -+ */ -+static struct gpio_led ap96_leds_gpio[] __initdata = { -+ { -+ .name = "ap96:green:led2", -+ .gpio = AP96_GPIO_LED_2_GREEN, -+ .active_low = 1, -+ }, { -+ .name = "ap96:green:led3", -+ .gpio = AP96_GPIO_LED_3_GREEN, -+ .active_low = 1, -+ }, { -+ .name = "ap96:orange:led4", -+ .gpio = AP96_GPIO_LED_4_ORANGE, -+ .active_low = 1, -+ }, { -+ .name = "ap96:green:led5", -+ .gpio = AP96_GPIO_LED_5_GREEN, -+ .active_low = 1, -+ }, { -+ .name = "ap96:green:led12", -+ .gpio = AP96_GPIO_LED_12_GREEN, -+ .active_low = 1, -+ }, { /* next to a button on right */ -+ .name = "ap96:green:wps", -+ .gpio = AP96_GPIO_LED_WPS_GREEN, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_keys_button ap96_gpio_keys[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .debounce_interval = AP96_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = AP96_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "wps", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .debounce_interval = AP96_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = AP96_GPIO_BTN_WPS, -+ .active_low = 1, -+ } -+}; -+ -+#define AP96_WAN_PHYMASK 0x10 -+#define AP96_LAN_PHYMASK 0x0f -+ -+static void __init ap96_setup(void) -+{ -+ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); -+ -+ ar71xx_add_device_mdio(~(AP96_WAN_PHYMASK | AP96_LAN_PHYMASK)); -+ -+ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, art, 0); -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth0_data.phy_mask = AP96_LAN_PHYMASK; -+ ar71xx_eth0_data.speed = SPEED_1000; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_add_device_eth(0); -+ -+ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, art, 1); -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth1_data.phy_mask = AP96_WAN_PHYMASK; -+ -+ ar71xx_eth1_pll_data.pll_1000 = 0x1f000000; -+ -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_usb(); -+ -+ ar71xx_add_device_m25p80(&ap96_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ap96_leds_gpio), -+ ap96_leds_gpio); -+ -+ ar71xx_register_gpio_keys_polled(-1, AP96_KEYS_POLL_INTERVAL, -+ ARRAY_SIZE(ap96_gpio_keys), -+ ap96_gpio_keys); -+ -+ ap94_pci_init(art + AP96_CALDATA0_OFFSET, -+ art + AP96_WMAC0_MAC_OFFSET, -+ art + AP96_CALDATA1_OFFSET, -+ art + AP96_WMAC1_MAC_OFFSET); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_AP96, "AP96", "Atheros AP96", ap96_setup); -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-aw-nr580.c linux-2.6.39/arch/mips/ar71xx/mach-aw-nr580.c ---- linux-2.6.39.orig/arch/mips/ar71xx/mach-aw-nr580.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/mach-aw-nr580.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,102 @@ -+/* -+ * AzureWave AW-NR580 board support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-gpio-buttons.h" -+#include "dev-pb42-pci.h" -+#include "dev-leds-gpio.h" -+ -+#define AW_NR580_GPIO_LED_READY_RED 0 -+#define AW_NR580_GPIO_LED_WLAN 1 -+#define AW_NR580_GPIO_LED_READY_GREEN 2 -+#define AW_NR580_GPIO_LED_WPS_GREEN 4 -+#define AW_NR580_GPIO_LED_WPS_AMBER 5 -+ -+#define AW_NR580_GPIO_BTN_WPS 3 -+#define AW_NR580_GPIO_BTN_RESET 11 -+ -+#define AW_NR580_KEYS_POLL_INTERVAL 20 /* msecs */ -+#define AW_NR580_KEYS_DEBOUNCE_INTERVAL (3 * AW_NR580_KEYS_POLL_INTERVAL) -+ -+static struct gpio_led aw_nr580_leds_gpio[] __initdata = { -+ { -+ .name = "aw-nr580:red:ready", -+ .gpio = AW_NR580_GPIO_LED_READY_RED, -+ .active_low = 0, -+ }, { -+ .name = "aw-nr580:green:ready", -+ .gpio = AW_NR580_GPIO_LED_READY_GREEN, -+ .active_low = 0, -+ }, { -+ .name = "aw-nr580:green:wps", -+ .gpio = AW_NR580_GPIO_LED_WPS_GREEN, -+ .active_low = 0, -+ }, { -+ .name = "aw-nr580:amber:wps", -+ .gpio = AW_NR580_GPIO_LED_WPS_AMBER, -+ .active_low = 0, -+ }, { -+ .name = "aw-nr580:green:wlan", -+ .gpio = AW_NR580_GPIO_LED_WLAN, -+ .active_low = 0, -+ } -+}; -+ -+static struct gpio_keys_button aw_nr580_gpio_keys[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .debounce_interval = AW_NR580_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = AW_NR580_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "wps", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .debounce_interval = AW_NR580_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = AW_NR580_GPIO_BTN_WPS, -+ .active_low = 1, -+ } -+}; -+ -+static void __init aw_nr580_setup(void) -+{ -+ ar71xx_add_device_mdio(0x0); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_add_device_eth(0); -+ -+ pb42_pci_init(); -+ -+ ar71xx_add_device_m25p80(NULL); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(aw_nr580_leds_gpio), -+ aw_nr580_leds_gpio); -+ -+ ar71xx_register_gpio_keys_polled(-1, AW_NR580_KEYS_POLL_INTERVAL, -+ ARRAY_SIZE(aw_nr580_gpio_keys), -+ aw_nr580_gpio_keys); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_AW_NR580, "AW-NR580", "AzureWave AW-NR580", -+ aw_nr580_setup); -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-db120.c linux-2.6.39/arch/mips/ar71xx/mach-db120.c ---- linux-2.6.39.orig/arch/mips/ar71xx/mach-db120.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/mach-db120.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,134 @@ -+/* -+ * Atheros DB120 board (WASP SoC) support -+ * -+ * Copyright (C) 2010-2011 Jaiganesh Narayanan -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-usb.h" -+#include "dev-ar9xxx-wmac.h" -+#include "dev-db120-pci.h" -+ -+#define DB120_GPIO_LED_USB 11 -+#define DB120_GPIO_LED_WLAN_5G 12 -+#define DB120_GPIO_LED_WLAN_2G 13 -+#define DB120_GPIO_LED_STATUS 14 -+#define DB120_GPIO_LED_WPS 15 -+ -+#define DB120_GPIO_BTN_SW1 16 -+ -+#define DB120_CALDATA_OFFSET 0x1000 -+#define DB120_WMAC_MAC_OFFSET 0x1002 -+ -+#define DB120_KEYS_POLL_INTERVAL 20 /* msecs */ -+#define DB120_KEYS_DEBOUNCE_INTERVAL (3 * DB120_KEYS_POLL_INTERVAL) -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition db120_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x040000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "u-boot-env", -+ .offset = 0x040000, -+ .size = 0x010000, -+ }, { -+ .name = "rootfs", -+ .offset = 0x050000, -+ .size = 0x630000, -+ }, { -+ .name = "uImage", -+ .offset = 0x680000, -+ .size = 0x160000, -+ }, { -+ .name = "NVRAM", -+ .offset = 0x7E0000, -+ .size = 0x010000, -+ }, { -+ .name = "ART", -+ .offset = 0x7F0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data db120_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = db120_partitions, -+ .nr_parts = ARRAY_SIZE(db120_partitions), -+#endif -+}; -+ -+static struct gpio_led db120_leds_gpio[] __initdata = { -+ { -+ .name = "db120:green:status", -+ .gpio = DB120_GPIO_LED_STATUS, -+ .active_low = 1, -+ }, { -+ .name = "db120:green:wps", -+ .gpio = DB120_GPIO_LED_WPS, -+ .active_low = 1, -+ }, { -+ .name = "db120:green:wlan-5g", -+ .gpio = DB120_GPIO_LED_WLAN_5G, -+ .active_low = 1, -+ }, { -+ .name = "db120:green:wlan-2g", -+ .gpio = DB120_GPIO_LED_WLAN_2G, -+ .active_low = 1, -+ }, { -+ .name = "db120:green:usb", -+ .gpio = DB120_GPIO_LED_USB, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_keys_button db120_gpio_keys[] __initdata = { -+ { -+ .desc = "sw1", -+ .type = EV_KEY, -+ .code = BTN_0, -+ .debounce_interval = DB120_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = DB120_GPIO_BTN_SW1, -+ .active_low = 1, -+ } -+}; -+ -+static void __init db120_setup(void) -+{ -+ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); -+ -+ ar71xx_add_device_usb(); -+ -+ ar71xx_add_device_m25p80(&db120_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(db120_leds_gpio), -+ db120_leds_gpio); -+ -+ ar71xx_register_gpio_keys_polled(-1, DB120_KEYS_POLL_INTERVAL, -+ ARRAY_SIZE(db120_gpio_keys), -+ db120_gpio_keys); -+ -+ ar9xxx_add_device_wmac(art + DB120_CALDATA_OFFSET, -+ art + DB120_WMAC_MAC_OFFSET); -+ -+ db120_pci_init(); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_DB120, "DB120", "Atheros DB120", db120_setup); -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-dir-600-a1.c linux-2.6.39/arch/mips/ar71xx/mach-dir-600-a1.c ---- linux-2.6.39.orig/arch/mips/ar71xx/mach-dir-600-a1.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/mach-dir-600-a1.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,159 @@ -+/* -+ * D-Link DIR-600 rev. A1 board support -+ * -+ * Copyright (C) 2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ap91-pci.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "nvram.h" -+ -+#define DIR_600_A1_GPIO_LED_WPS 0 -+#define DIR_600_A1_GPIO_LED_POWER_AMBER 1 -+#define DIR_600_A1_GPIO_LED_POWER_GREEN 6 -+ -+#define DIR_600_A1_GPIO_BTN_RESET 8 -+#define DIR_600_A1_GPIO_BTN_WPS 12 -+ -+#define DIR_600_A1_KEYS_POLL_INTERVAL 20 /* msecs */ -+#define DIR_600_A1_KEYS_DEBOUNCE_INTERVAL (3 * DIR_600_A1_KEYS_POLL_INTERVAL) -+ -+#define DIR_600_A1_NVRAM_ADDR 0x1f030000 -+#define DIR_600_A1_NVRAM_SIZE 0x10000 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition dir_600_a1_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x030000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "nvram", -+ .offset = 0x030000, -+ .size = 0x010000, -+ }, { -+ .name = "kernel", -+ .offset = 0x040000, -+ .size = 0x0e0000, -+ }, { -+ .name = "rootfs", -+ .offset = 0x120000, -+ .size = 0x2c0000, -+ }, { -+ .name = "mac", -+ .offset = 0x3e0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "art", -+ .offset = 0x3f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "firmware", -+ .offset = 0x040000, -+ .size = 0x3a0000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data dir_600_a1_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = dir_600_a1_partitions, -+ .nr_parts = ARRAY_SIZE(dir_600_a1_partitions), -+#endif -+}; -+ -+static struct gpio_led dir_600_a1_leds_gpio[] __initdata = { -+ { -+ .name = "dir-600-a1:green:power", -+ .gpio = DIR_600_A1_GPIO_LED_POWER_GREEN, -+ }, { -+ .name = "dir-600-a1:amber:power", -+ .gpio = DIR_600_A1_GPIO_LED_POWER_AMBER, -+ }, { -+ .name = "dir-600-a1:blue:wps", -+ .gpio = DIR_600_A1_GPIO_LED_WPS, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_keys_button dir_600_a1_gpio_keys[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .debounce_interval = DIR_600_A1_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = DIR_600_A1_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "wps", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .debounce_interval = DIR_600_A1_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = DIR_600_A1_GPIO_BTN_WPS, -+ .active_low = 1, -+ } -+}; -+ -+static void __init dir_600_a1_setup(void) -+{ -+ const char *nvram = (char *) KSEG1ADDR(DIR_600_A1_NVRAM_ADDR); -+ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); -+ u8 mac_buff[6]; -+ u8 *mac = NULL; -+ -+ if (nvram_parse_mac_addr(nvram, DIR_600_A1_NVRAM_SIZE, -+ "lan_mac=", mac_buff) == 0) { -+ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac_buff, 0); -+ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, mac_buff, 1); -+ mac = mac_buff; -+ } -+ -+ ar71xx_add_device_m25p80(&dir_600_a1_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(dir_600_a1_leds_gpio), -+ dir_600_a1_leds_gpio); -+ -+ ar71xx_register_gpio_keys_polled(-1, DIR_600_A1_KEYS_POLL_INTERVAL, -+ ARRAY_SIZE(dir_600_a1_gpio_keys), -+ dir_600_a1_gpio_keys); -+ -+ ar71xx_eth1_data.has_ar7240_switch = 1; -+ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac, 0); -+ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, mac, 1); -+ -+ /* WAN port */ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ ar71xx_eth0_data.phy_mask = BIT(4); -+ -+ /* LAN ports */ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.speed = SPEED_1000; -+ ar71xx_eth1_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_add_device_mdio(0x0); -+ ar71xx_add_device_eth(1); -+ ar71xx_add_device_eth(0); -+ -+ ap91_pci_init(ee, mac); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_DIR_600_A1, "DIR-600-A1", "D-Link DIR-600 rev. A1", -+ dir_600_a1_setup); -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-dir-615-c1.c linux-2.6.39/arch/mips/ar71xx/mach-dir-615-c1.c ---- linux-2.6.39.orig/arch/mips/ar71xx/mach-dir-615-c1.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/mach-dir-615-c1.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,175 @@ -+/* -+ * D-Link DIR-615 rev C1 board support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ar9xxx-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "nvram.h" -+ -+#define DIR_615C1_GPIO_LED_ORANGE_STATUS 1 /* ORANGE:STATUS:TRICOLOR */ -+#define DIR_615C1_GPIO_LED_BLUE_WPS 3 /* BLUE:WPS */ -+#define DIR_615C1_GPIO_LED_GREEN_WAN 4 /* GREEN:WAN:TRICOLOR */ -+#define DIR_615C1_GPIO_LED_GREEN_WANCPU 5 /* GREEN:WAN:CPU:TRICOLOR */ -+#define DIR_615C1_GPIO_LED_GREEN_WLAN 6 /* GREEN:WLAN */ -+#define DIR_615C1_GPIO_LED_GREEN_STATUS 14 /* GREEN:STATUS:TRICOLOR */ -+#define DIR_615C1_GPIO_LED_ORANGE_WAN 15 /* ORANGE:WAN:TRICOLOR */ -+ -+/* buttons may need refinement */ -+ -+#define DIR_615C1_GPIO_BTN_WPS 12 -+#define DIR_615C1_GPIO_BTN_RESET 21 -+ -+#define DIR_615C1_KEYS_POLL_INTERVAL 20 /* msecs */ -+#define DIR_615C1_KEYS_DEBOUNCE_INTERVAL (3 * DIR_615C1_KEYS_POLL_INTERVAL) -+ -+#define DIR_615C1_CONFIG_ADDR 0x1f020000 -+#define DIR_615C1_CONFIG_SIZE 0x10000 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition dir_615c1_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "config", -+ .offset = 0x020000, -+ .size = 0x010000, -+ }, { -+ .name = "kernel", -+ .offset = 0x030000, -+ .size = 0x0e0000, -+ }, { -+ .name = "rootfs", -+ .offset = 0x110000, -+ .size = 0x2e0000, -+ }, { -+ .name = "art", -+ .offset = 0x3f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "firmware", -+ .offset = 0x030000, -+ .size = 0x3c0000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data dir_615c1_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = dir_615c1_partitions, -+ .nr_parts = ARRAY_SIZE(dir_615c1_partitions), -+#endif -+}; -+ -+static struct gpio_led dir_615c1_leds_gpio[] __initdata = { -+ { -+ .name = "dir-615c1:orange:status", -+ .gpio = DIR_615C1_GPIO_LED_ORANGE_STATUS, -+ .active_low = 1, -+ }, { -+ .name = "dir-615c1:blue:wps", -+ .gpio = DIR_615C1_GPIO_LED_BLUE_WPS, -+ .active_low = 1, -+ }, { -+ .name = "dir-615c1:green:wan", -+ .gpio = DIR_615C1_GPIO_LED_GREEN_WAN, -+ .active_low = 1, -+ }, { -+ .name = "dir-615c1:green:wancpu", -+ .gpio = DIR_615C1_GPIO_LED_GREEN_WANCPU, -+ .active_low = 1, -+ }, { -+ .name = "dir-615c1:green:wlan", -+ .gpio = DIR_615C1_GPIO_LED_GREEN_WLAN, -+ .active_low = 1, -+ }, { -+ .name = "dir-615c1:green:status", -+ .gpio = DIR_615C1_GPIO_LED_GREEN_STATUS, -+ .active_low = 1, -+ }, { -+ .name = "dir-615c1:orange:wan", -+ .gpio = DIR_615C1_GPIO_LED_ORANGE_WAN, -+ .active_low = 1, -+ } -+ -+}; -+ -+static struct gpio_keys_button dir_615c1_gpio_keys[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .debounce_interval = DIR_615C1_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = DIR_615C1_GPIO_BTN_RESET, -+ }, { -+ .desc = "wps", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .debounce_interval = DIR_615C1_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = DIR_615C1_GPIO_BTN_WPS, -+ } -+}; -+ -+#define DIR_615C1_LAN_PHYMASK BIT(0) -+#define DIR_615C1_WAN_PHYMASK BIT(4) -+#define DIR_615C1_MDIO_MASK (~(DIR_615C1_LAN_PHYMASK | \ -+ DIR_615C1_WAN_PHYMASK)) -+ -+static void __init dir_615c1_setup(void) -+{ -+ const char *config = (char *) KSEG1ADDR(DIR_615C1_CONFIG_ADDR); -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ u8 mac[6]; -+ u8 *wlan_mac = NULL; -+ -+ if (nvram_parse_mac_addr(config, DIR_615C1_CONFIG_SIZE, -+ "lan_mac=", mac) == 0) { -+ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac, 0); -+ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, mac, 1); -+ wlan_mac = mac; -+ } -+ -+ ar71xx_add_device_mdio(DIR_615C1_MDIO_MASK); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.phy_mask = DIR_615C1_LAN_PHYMASK; -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.phy_mask = DIR_615C1_WAN_PHYMASK; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_m25p80(&dir_615c1_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(dir_615c1_leds_gpio), -+ dir_615c1_leds_gpio); -+ -+ ar71xx_register_gpio_keys_polled(-1, DIR_615C1_KEYS_POLL_INTERVAL, -+ ARRAY_SIZE(dir_615c1_gpio_keys), -+ dir_615c1_gpio_keys); -+ -+ ar9xxx_add_device_wmac(eeprom, wlan_mac); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_DIR_615_C1, "DIR-615-C1", "D-Link DIR-615 rev. C1", -+ dir_615c1_setup); -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-dir-825-b1.c linux-2.6.39/arch/mips/ar71xx/mach-dir-825-b1.c ---- linux-2.6.39.orig/arch/mips/ar71xx/mach-dir-825-b1.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/mach-dir-825-b1.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,198 @@ -+/* -+ * D-Link DIR-825 rev. B1 board support -+ * -+ * Copyright (C) 2009 Lukas Kuna, Evkanet, s.r.o. -+ * -+ * based on mach-wndr3700.c -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ap94-pci.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-usb.h" -+ -+#define DIR825B1_GPIO_LED_BLUE_USB 0 -+#define DIR825B1_GPIO_LED_ORANGE_POWER 1 -+#define DIR825B1_GPIO_LED_BLUE_POWER 2 -+#define DIR825B1_GPIO_LED_BLUE_WPS 4 -+#define DIR825B1_GPIO_LED_ORANGE_PLANET 6 -+#define DIR825B1_GPIO_LED_BLUE_PLANET 11 -+ -+#define DIR825B1_GPIO_BTN_RESET 3 -+#define DIR825B1_GPIO_BTN_WPS 8 -+ -+#define DIR825B1_GPIO_RTL8366_SDA 5 -+#define DIR825B1_GPIO_RTL8366_SCK 7 -+ -+#define DIR825B1_KEYS_POLL_INTERVAL 20 /* msecs */ -+#define DIR825B1_KEYS_DEBOUNCE_INTERVAL (3 * DIR825B1_KEYS_POLL_INTERVAL) -+ -+#define DIR825B1_CAL_LOCATION_0 0x1f661000 -+#define DIR825B1_CAL_LOCATION_1 0x1f665000 -+ -+#define DIR825B1_MAC_LOCATION_0 0x2ffa81b8 -+#define DIR825B1_MAC_LOCATION_1 0x2ffa8370 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition dir825b1_partitions[] = { -+ { -+ .name = "uboot", -+ .offset = 0, -+ .size = 0x040000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "config", -+ .offset = 0x040000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "firmware", -+ .offset = 0x050000, -+ .size = 0x610000, -+ }, { -+ .name = "caldata", -+ .offset = 0x660000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "unknown", -+ .offset = 0x670000, -+ .size = 0x190000, -+ .mask_flags = MTD_WRITEABLE, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data dir825b1_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = dir825b1_partitions, -+ .nr_parts = ARRAY_SIZE(dir825b1_partitions), -+#endif -+}; -+ -+static struct gpio_led dir825b1_leds_gpio[] __initdata = { -+ { -+ .name = "dir825b1:blue:usb", -+ .gpio = DIR825B1_GPIO_LED_BLUE_USB, -+ .active_low = 1, -+ }, { -+ .name = "dir825b1:orange:power", -+ .gpio = DIR825B1_GPIO_LED_ORANGE_POWER, -+ .active_low = 1, -+ }, { -+ .name = "dir825b1:blue:power", -+ .gpio = DIR825B1_GPIO_LED_BLUE_POWER, -+ .active_low = 1, -+ }, { -+ .name = "dir825b1:blue:wps", -+ .gpio = DIR825B1_GPIO_LED_BLUE_WPS, -+ .active_low = 1, -+ }, { -+ .name = "dir825b1:orange:planet", -+ .gpio = DIR825B1_GPIO_LED_ORANGE_PLANET, -+ .active_low = 1, -+ }, { -+ .name = "dir825b1:blue:planet", -+ .gpio = DIR825B1_GPIO_LED_BLUE_PLANET, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_keys_button dir825b1_gpio_keys[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .debounce_interval = DIR825B1_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = DIR825B1_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "wps", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .debounce_interval = DIR825B1_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = DIR825B1_GPIO_BTN_WPS, -+ .active_low = 1, -+ } -+}; -+ -+static struct rtl8366_initval dir825b1_rtl8366s_initvals[] = { -+ { .reg = 0x06, .val = 0x0108 }, -+}; -+ -+static struct rtl8366_platform_data dir825b1_rtl8366s_data = { -+ .gpio_sda = DIR825B1_GPIO_RTL8366_SDA, -+ .gpio_sck = DIR825B1_GPIO_RTL8366_SCK, -+ .num_initvals = ARRAY_SIZE(dir825b1_rtl8366s_initvals), -+ .initvals = dir825b1_rtl8366s_initvals, -+}; -+ -+static struct platform_device dir825b1_rtl8366s_device = { -+ .name = RTL8366S_DRIVER_NAME, -+ .id = -1, -+ .dev = { -+ .platform_data = &dir825b1_rtl8366s_data, -+ } -+}; -+ -+static void __init dir825b1_setup(void) -+{ -+ u8 *mac = (u8 *) KSEG1ADDR(DIR825B1_MAC_LOCATION_1); -+ -+ ar71xx_add_device_mdio(0x0); -+ -+ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac, 1); -+ ar71xx_eth0_data.mii_bus_dev = &dir825b1_rtl8366s_device.dev; -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth0_data.speed = SPEED_1000; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ ar71xx_eth0_pll_data.pll_1000 = 0x11110000; -+ -+ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, mac, 2); -+ ar71xx_eth1_data.mii_bus_dev = &dir825b1_rtl8366s_device.dev; -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth1_data.phy_mask = 0x10; -+ ar71xx_eth1_pll_data.pll_1000 = 0x11110000; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_m25p80(&dir825b1_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(dir825b1_leds_gpio), -+ dir825b1_leds_gpio); -+ -+ ar71xx_register_gpio_keys_polled(-1, DIR825B1_KEYS_POLL_INTERVAL, -+ ARRAY_SIZE(dir825b1_gpio_keys), -+ dir825b1_gpio_keys); -+ -+ ar71xx_add_device_usb(); -+ -+ platform_device_register(&dir825b1_rtl8366s_device); -+ -+ ap94_pci_setup_wmac_led_pin(0, 5); -+ ap94_pci_setup_wmac_led_pin(1, 5); -+ -+ ap94_pci_init((u8 *) KSEG1ADDR(DIR825B1_CAL_LOCATION_0), -+ (u8 *) KSEG1ADDR(DIR825B1_MAC_LOCATION_0), -+ (u8 *) KSEG1ADDR(DIR825B1_CAL_LOCATION_1), -+ (u8 *) KSEG1ADDR(DIR825B1_MAC_LOCATION_1)); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_DIR_825_B1, "DIR-825-B1", "D-Link DIR-825 rev. B1", -+ dir825b1_setup); -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-eap7660d.c linux-2.6.39/arch/mips/ar71xx/mach-eap7660d.c ---- linux-2.6.39.orig/arch/mips/ar71xx/mach-eap7660d.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/mach-eap7660d.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,180 @@ -+/* -+ * Senao EAP7660D board support -+ * -+ * Copyright (C) 2010 Daniel Golle -+ * Copyright (C) 2008 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-m25p80.h" -+ -+#define EAP7660D_KEYS_POLL_INTERVAL 20 /* msecs */ -+#define EAP7660D_KEYS_DEBOUNCE_INTERVAL (3 * EAP7660D_KEYS_POLL_INTERVAL) -+ -+#define EAP7660D_GPIO_DS4 7 -+#define EAP7660D_GPIO_DS5 2 -+#define EAP7660D_GPIO_DS7 0 -+#define EAP7660D_GPIO_DS8 4 -+#define EAP7660D_GPIO_SW1 3 -+#define EAP7660D_GPIO_SW3 8 -+#define EAP7660D_PHYMASK BIT(20) -+#define EAP7660D_BOARDCONFIG 0x1F7F0000 -+#define EAP7660D_GBIC_MAC_OFFSET 0x1000 -+#define EAP7660D_WMAC0_MAC_OFFSET 0x1010 -+#define EAP7660D_WMAC1_MAC_OFFSET 0x1016 -+#define EAP7660D_WMAC0_CALDATA_OFFSET 0x2000 -+#define EAP7660D_WMAC1_CALDATA_OFFSET 0x3000 -+ -+static struct ath5k_platform_data eap7660d_wmac0_data; -+static struct ath5k_platform_data eap7660d_wmac1_data; -+static char eap7660d_wmac0_mac[6]; -+static char eap7660d_wmac1_mac[6]; -+static u16 eap7660d_wmac0_eeprom[ATH5K_PLAT_EEP_MAX_WORDS]; -+static u16 eap7660d_wmac1_eeprom[ATH5K_PLAT_EEP_MAX_WORDS]; -+ -+#ifdef CONFIG_PCI -+static struct ar71xx_pci_irq eap7660d_pci_irqs[] __initdata = { -+ { -+ .slot = 0, -+ .pin = 1, -+ .irq = AR71XX_PCI_IRQ_DEV0, -+ }, { -+ .slot = 1, -+ .pin = 1, -+ .irq = AR71XX_PCI_IRQ_DEV1, -+ } -+}; -+ -+static int eap7660d_pci_plat_dev_init(struct pci_dev *dev) -+{ -+ switch (PCI_SLOT(dev->devfn)) { -+ case 17: -+ dev->dev.platform_data = &eap7660d_wmac0_data; -+ break; -+ -+ case 18: -+ dev->dev.platform_data = &eap7660d_wmac1_data; -+ break; -+ } -+ -+ return 0; -+} -+ -+void __init eap7660d_pci_init(u8 *cal_data0, u8 *mac_addr0, -+ u8 *cal_data1, u8 *mac_addr1) -+{ -+ if (cal_data0 && *cal_data0 == 0xa55a) { -+ memcpy(eap7660d_wmac0_eeprom, cal_data0, -+ ATH5K_PLAT_EEP_MAX_WORDS); -+ eap7660d_wmac0_data.eeprom_data = eap7660d_wmac0_eeprom; -+ } -+ -+ if (cal_data1 && *cal_data1 == 0xa55a) { -+ memcpy(eap7660d_wmac1_eeprom, cal_data1, -+ ATH5K_PLAT_EEP_MAX_WORDS); -+ eap7660d_wmac1_data.eeprom_data = eap7660d_wmac1_eeprom; -+ } -+ -+ if (mac_addr0) { -+ memcpy(eap7660d_wmac0_mac, mac_addr0, -+ sizeof(eap7660d_wmac0_mac)); -+ eap7660d_wmac0_data.macaddr = eap7660d_wmac0_mac; -+ } -+ -+ if (mac_addr1) { -+ memcpy(eap7660d_wmac1_mac, mac_addr1, -+ sizeof(eap7660d_wmac1_mac)); -+ eap7660d_wmac1_data.macaddr = eap7660d_wmac1_mac; -+ } -+ -+ ar71xx_pci_plat_dev_init = eap7660d_pci_plat_dev_init; -+ ar71xx_pci_init(ARRAY_SIZE(eap7660d_pci_irqs), eap7660d_pci_irqs); -+} -+#else -+static inline void eap7660d_pci_init(u8 *cal_data0, u8 *mac_addr0, -+ u8 *cal_data1, u8 *mac_addr1) -+{ -+} -+#endif /* CONFIG_PCI */ -+ -+static struct gpio_led eap7660d_leds_gpio[] __initdata = { -+ { -+ .name = "eap7660d:green:ds8", -+ .gpio = EAP7660D_GPIO_DS8, -+ .active_low = 0, -+ }, -+ { -+ .name = "eap7660d:green:ds5", -+ .gpio = EAP7660D_GPIO_DS5, -+ .active_low = 0, -+ }, -+ { -+ .name = "eap7660d:green:ds7", -+ .gpio = EAP7660D_GPIO_DS7, -+ .active_low = 0, -+ }, -+ { -+ .name = "eap7660d:green:ds4", -+ .gpio = EAP7660D_GPIO_DS4, -+ .active_low = 0, -+ } -+}; -+ -+static struct gpio_keys_button eap7660d_gpio_keys[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .debounce_interval = EAP7660D_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = EAP7660D_GPIO_SW1, -+ .active_low = 1, -+ }, -+ { -+ .desc = "wps", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .debounce_interval = EAP7660D_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = EAP7660D_GPIO_SW3, -+ .active_low = 1, -+ } -+}; -+ -+static void __init eap7660d_setup(void) -+{ -+ u8 *boardconfig = (u8 *) KSEG1ADDR(EAP7660D_BOARDCONFIG); -+ -+ ar71xx_add_device_mdio(~EAP7660D_PHYMASK); -+ -+ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, -+ boardconfig + EAP7660D_GBIC_MAC_OFFSET, 0); -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth0_data.phy_mask = EAP7660D_PHYMASK; -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_m25p80(NULL); -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(eap7660d_leds_gpio), -+ eap7660d_leds_gpio); -+ ar71xx_register_gpio_keys_polled(-1, EAP7660D_KEYS_POLL_INTERVAL, -+ ARRAY_SIZE(eap7660d_gpio_keys), -+ eap7660d_gpio_keys); -+ eap7660d_pci_init(boardconfig + EAP7660D_WMAC0_CALDATA_OFFSET, -+ boardconfig + EAP7660D_WMAC0_MAC_OFFSET, -+ boardconfig + EAP7660D_WMAC1_CALDATA_OFFSET, -+ boardconfig + EAP7660D_WMAC1_MAC_OFFSET); -+}; -+ -+MIPS_MACHINE(AR71XX_MACH_EAP7660D, "EAP7660D", "Senao EAP7660D", -+ eap7660d_setup); -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-ja76pf.c linux-2.6.39/arch/mips/ar71xx/mach-ja76pf.c ---- linux-2.6.39.orig/arch/mips/ar71xx/mach-ja76pf.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/mach-ja76pf.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,102 @@ -+/* -+ * jjPlus JA76PF board support -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-gpio-buttons.h" -+#include "dev-pb42-pci.h" -+#include "dev-usb.h" -+#include "dev-leds-gpio.h" -+ -+#define JA76PF_KEYS_POLL_INTERVAL 20 /* msecs */ -+#define JA76PF_KEYS_DEBOUNCE_INTERVAL (3 * JA76PF_KEYS_POLL_INTERVAL) -+ -+#define JA76PF_GPIO_I2C_SCL 0 -+#define JA76PF_GPIO_I2C_SDA 1 -+#define JA76PF_GPIO_LED_1 5 -+#define JA76PF_GPIO_LED_2 4 -+#define JA76PF_GPIO_LED_3 3 -+#define JA76PF_GPIO_BTN_RESET 11 -+ -+static struct gpio_led ja76pf_leds_gpio[] __initdata = { -+ { -+ .name = "ja76pf:green:led1", -+ .gpio = JA76PF_GPIO_LED_1, -+ .active_low = 1, -+ }, { -+ .name = "ja76pf:green:led2", -+ .gpio = JA76PF_GPIO_LED_2, -+ .active_low = 1, -+ }, { -+ .name = "ja76pf:green:led3", -+ .gpio = JA76PF_GPIO_LED_3, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_keys_button ja76pf_gpio_keys[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .debounce_interval = JA76PF_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = JA76PF_GPIO_BTN_RESET, -+ .active_low = 1, -+ } -+}; -+ -+static struct i2c_gpio_platform_data ja76pf_i2c_gpio_data = { -+ .sda_pin = JA76PF_GPIO_I2C_SDA, -+ .scl_pin = JA76PF_GPIO_I2C_SCL, -+}; -+ -+static struct platform_device ja76pf_i2c_gpio_device = { -+ .name = "i2c-gpio", -+ .id = 0, -+ .dev = { -+ .platform_data = &ja76pf_i2c_gpio_data, -+ } -+}; -+ -+#define JA76PF_WAN_PHYMASK (1 << 4) -+#define JA76PF_LAN_PHYMASK ((1 << 0) | (1 << 1) | (1 << 2) | (1 < 3)) -+#define JA76PF_MDIO_PHYMASK (JA76PF_LAN_PHYMASK | JA76PF_WAN_PHYMASK) -+ -+static void __init ja76pf_init(void) -+{ -+ ar71xx_add_device_m25p80(NULL); -+ -+ ar71xx_add_device_mdio(~JA76PF_MDIO_PHYMASK); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth0_data.phy_mask = JA76PF_LAN_PHYMASK; -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth1_data.phy_mask = JA76PF_WAN_PHYMASK; -+ ar71xx_eth1_data.speed = SPEED_1000; -+ ar71xx_eth1_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ platform_device_register(&ja76pf_i2c_gpio_device); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ja76pf_leds_gpio), -+ ja76pf_leds_gpio); -+ -+ ar71xx_register_gpio_keys_polled(-1, JA76PF_KEYS_POLL_INTERVAL, -+ ARRAY_SIZE(ja76pf_gpio_keys), -+ ja76pf_gpio_keys); -+ -+ ar71xx_add_device_usb(); -+ pb42_pci_init(); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_JA76PF, "JA76PF", "jjPlus JA76PF", ja76pf_init); -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-jwap003.c linux-2.6.39/arch/mips/ar71xx/mach-jwap003.c ---- linux-2.6.39.orig/arch/mips/ar71xx/mach-jwap003.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/mach-jwap003.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,83 @@ -+/* -+ * jjPlus JWAP003 board support -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-gpio-buttons.h" -+#include "dev-pb42-pci.h" -+#include "dev-usb.h" -+ -+#define JWAP003_KEYS_POLL_INTERVAL 20 /* msecs */ -+#define JWAP003_KEYS_DEBOUNCE_INTERVAL (3 * JWAP003_KEYS_POLL_INTERVAL) -+ -+#define JWAP003_GPIO_WPS 11 -+#define JWAP003_GPIO_I2C_SCL 0 -+#define JWAP003_GPIO_I2C_SDA 1 -+ -+static struct gpio_keys_button jwap003_gpio_keys[] __initdata = { -+ { -+ .desc = "wps", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .debounce_interval = JWAP003_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = JWAP003_GPIO_WPS, -+ .active_low = 1, -+ } -+}; -+ -+static struct i2c_gpio_platform_data jwap003_i2c_gpio_data = { -+ .sda_pin = JWAP003_GPIO_I2C_SDA, -+ .scl_pin = JWAP003_GPIO_I2C_SCL, -+}; -+ -+static struct platform_device jwap003_i2c_gpio_device = { -+ .name = "i2c-gpio", -+ .id = 0, -+ .dev = { -+ .platform_data = &jwap003_i2c_gpio_data, -+ } -+}; -+ -+#define JWAP003_WAN_PHYMASK BIT(0) -+#define JWAP003_LAN_PHYMASK BIT(4) -+ -+static void __init jwap003_init(void) -+{ -+ ar71xx_add_device_m25p80(NULL); -+ -+ ar71xx_add_device_mdio(0x0); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.phy_mask = JWAP003_WAN_PHYMASK; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ ar71xx_eth0_data.has_ar8216 = 1; -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.phy_mask = JWAP003_LAN_PHYMASK; -+ ar71xx_eth1_data.speed = SPEED_100; -+ ar71xx_eth1_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ platform_device_register(&jwap003_i2c_gpio_device); -+ -+ ar71xx_add_device_usb(); -+ -+ ar71xx_register_gpio_keys_polled(-1, JWAP003_KEYS_POLL_INTERVAL, -+ ARRAY_SIZE(jwap003_gpio_keys), -+ jwap003_gpio_keys); -+ -+ pb42_pci_init(); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_JWAP003, "JWAP003", "jjPlus JWAP003", jwap003_init); -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-mzk-w04nu.c linux-2.6.39/arch/mips/ar71xx/mach-mzk-w04nu.c ---- linux-2.6.39.orig/arch/mips/ar71xx/mach-mzk-w04nu.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/mach-mzk-w04nu.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,166 @@ -+/* -+ * Planex MZK-W04NU board support -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-ar9xxx-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-m25p80.h" -+#include "dev-usb.h" -+ -+#define MZK_W04NU_GPIO_LED_USB 0 -+#define MZK_W04NU_GPIO_LED_STATUS 1 -+#define MZK_W04NU_GPIO_LED_WPS 3 -+#define MZK_W04NU_GPIO_LED_WLAN 6 -+#define MZK_W04NU_GPIO_LED_AP 15 -+#define MZK_W04NU_GPIO_LED_ROUTER 16 -+ -+#define MZK_W04NU_GPIO_BTN_APROUTER 5 -+#define MZK_W04NU_GPIO_BTN_WPS 12 -+#define MZK_W04NU_GPIO_BTN_RESET 21 -+ -+#define MZK_W04NU_KEYS_POLL_INTERVAL 20 /* msecs */ -+#define MZK_W04NU_KEYS_DEBOUNCE_INTERVAL (3 * MZK_W04NU_KEYS_POLL_INTERVAL) -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition mzk_w04nu_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x040000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "u-boot-env", -+ .offset = 0x040000, -+ .size = 0x010000, -+ }, { -+ .name = "kernel", -+ .offset = 0x050000, -+ .size = 0x160000, -+ }, { -+ .name = "rootfs", -+ .offset = 0x1b0000, -+ .size = 0x630000, -+ }, { -+ .name = "art", -+ .offset = 0x7e0000, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "firmware", -+ .offset = 0x050000, -+ .size = 0x790000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data mzk_w04nu_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = mzk_w04nu_partitions, -+ .nr_parts = ARRAY_SIZE(mzk_w04nu_partitions), -+#endif -+}; -+ -+static struct gpio_led mzk_w04nu_leds_gpio[] __initdata = { -+ { -+ .name = "mzk-w04nu:green:status", -+ .gpio = MZK_W04NU_GPIO_LED_STATUS, -+ .active_low = 1, -+ }, { -+ .name = "mzk-w04nu:blue:wps", -+ .gpio = MZK_W04NU_GPIO_LED_WPS, -+ .active_low = 1, -+ }, { -+ .name = "mzk-w04nu:green:wlan", -+ .gpio = MZK_W04NU_GPIO_LED_WLAN, -+ .active_low = 1, -+ }, { -+ .name = "mzk-w04nu:green:usb", -+ .gpio = MZK_W04NU_GPIO_LED_USB, -+ .active_low = 1, -+ }, { -+ .name = "mzk-w04nu:green:ap", -+ .gpio = MZK_W04NU_GPIO_LED_AP, -+ .active_low = 1, -+ }, { -+ .name = "mzk-w04nu:green:router", -+ .gpio = MZK_W04NU_GPIO_LED_ROUTER, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_keys_button mzk_w04nu_gpio_keys[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .debounce_interval = MZK_W04NU_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = MZK_W04NU_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "wps", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .debounce_interval = MZK_W04NU_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = MZK_W04NU_GPIO_BTN_WPS, -+ .active_low = 1, -+ }, { -+ .desc = "aprouter", -+ .type = EV_KEY, -+ .code = BTN_2, -+ .debounce_interval = MZK_W04NU_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = MZK_W04NU_GPIO_BTN_APROUTER, -+ .active_low = 0, -+ } -+}; -+ -+#define MZK_W04NU_WAN_PHYMASK BIT(4) -+#define MZK_W04NU_MDIO_MASK (~MZK_W04NU_WAN_PHYMASK) -+ -+static void __init mzk_w04nu_setup(void) -+{ -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ -+ ar71xx_add_device_mdio(MZK_W04NU_MDIO_MASK); -+ -+ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, eeprom, 0); -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ ar71xx_eth0_data.has_ar8216 = 1; -+ -+ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, eeprom, 1); -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.phy_mask = MZK_W04NU_WAN_PHYMASK; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_m25p80(&mzk_w04nu_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(mzk_w04nu_leds_gpio), -+ mzk_w04nu_leds_gpio); -+ -+ ar71xx_register_gpio_keys_polled(-1, MZK_W04NU_KEYS_POLL_INTERVAL, -+ ARRAY_SIZE(mzk_w04nu_gpio_keys), -+ mzk_w04nu_gpio_keys); -+ ar71xx_add_device_usb(); -+ -+ ar9xxx_add_device_wmac(eeprom, NULL); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_MZK_W04NU, "MZK-W04NU", "Planex MZK-W04NU", -+ mzk_w04nu_setup); -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-mzk-w300nh.c linux-2.6.39/arch/mips/ar71xx/mach-mzk-w300nh.c ---- linux-2.6.39.orig/arch/mips/ar71xx/mach-mzk-w300nh.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/mach-mzk-w300nh.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,159 @@ -+/* -+ * Planex MZK-W300NH board support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ar9xxx-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+ -+#define MZK_W300NH_GPIO_LED_STATUS 1 -+#define MZK_W300NH_GPIO_LED_WPS 3 -+#define MZK_W300NH_GPIO_LED_WLAN 6 -+#define MZK_W300NH_GPIO_LED_AP 15 -+#define MZK_W300NH_GPIO_LED_ROUTER 16 -+ -+#define MZK_W300NH_GPIO_BTN_APROUTER 5 -+#define MZK_W300NH_GPIO_BTN_WPS 12 -+#define MZK_W300NH_GPIO_BTN_RESET 21 -+ -+#define MZK_W300NH_KEYS_POLL_INTERVAL 20 /* msecs */ -+#define MZK_W300NH_KEYS_DEBOUNCE_INTERVAL (3 * MZK_W300NH_KEYS_POLL_INTERVAL) -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition mzk_w300nh_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x040000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "u-boot-env", -+ .offset = 0x040000, -+ .size = 0x010000, -+ }, { -+ .name = "kernel", -+ .offset = 0x050000, -+ .size = 0x160000, -+ }, { -+ .name = "rootfs", -+ .offset = 0x1b0000, -+ .size = 0x630000, -+ }, { -+ .name = "art", -+ .offset = 0x7e0000, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "firmware", -+ .offset = 0x050000, -+ .size = 0x790000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data mzk_w300nh_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = mzk_w300nh_partitions, -+ .nr_parts = ARRAY_SIZE(mzk_w300nh_partitions), -+#endif -+}; -+ -+static struct gpio_led mzk_w300nh_leds_gpio[] __initdata = { -+ { -+ .name = "mzk-w300nh:green:status", -+ .gpio = MZK_W300NH_GPIO_LED_STATUS, -+ .active_low = 1, -+ }, { -+ .name = "mzk-w300nh:blue:wps", -+ .gpio = MZK_W300NH_GPIO_LED_WPS, -+ .active_low = 1, -+ }, { -+ .name = "mzk-w300nh:green:wlan", -+ .gpio = MZK_W300NH_GPIO_LED_WLAN, -+ .active_low = 1, -+ }, { -+ .name = "mzk-w300nh:green:ap", -+ .gpio = MZK_W300NH_GPIO_LED_AP, -+ .active_low = 1, -+ }, { -+ .name = "mzk-w300nh:green:router", -+ .gpio = MZK_W300NH_GPIO_LED_ROUTER, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_keys_button mzk_w300nh_gpio_keys[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .debounce_interval = MZK_W300NH_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = MZK_W300NH_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "wps", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .debounce_interval = MZK_W300NH_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = MZK_W300NH_GPIO_BTN_WPS, -+ .active_low = 1, -+ }, { -+ .desc = "aprouter", -+ .type = EV_KEY, -+ .code = BTN_2, -+ .debounce_interval = MZK_W300NH_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = MZK_W300NH_GPIO_BTN_APROUTER, -+ .active_low = 0, -+ } -+}; -+ -+#define MZK_W300NH_WAN_PHYMASK BIT(4) -+#define MZK_W300NH_MDIO_MASK (~MZK_W300NH_WAN_PHYMASK) -+ -+static void __init mzk_w300nh_setup(void) -+{ -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ -+ ar71xx_add_device_mdio(MZK_W300NH_MDIO_MASK); -+ -+ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, eeprom, 0); -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ ar71xx_eth0_data.has_ar8216 = 1; -+ -+ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, eeprom, 1); -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.phy_mask = MZK_W300NH_WAN_PHYMASK; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_m25p80(&mzk_w300nh_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(mzk_w300nh_leds_gpio), -+ mzk_w300nh_leds_gpio); -+ -+ ar71xx_register_gpio_keys_polled(-1, MZK_W300NH_KEYS_POLL_INTERVAL, -+ ARRAY_SIZE(mzk_w300nh_gpio_keys), -+ mzk_w300nh_gpio_keys); -+ ar9xxx_add_device_wmac(eeprom, NULL); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_MZK_W300NH, "MZK-W300NH", "Planex MZK-W300NH", -+ mzk_w300nh_setup); -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-nbg460n.c linux-2.6.39/arch/mips/ar71xx/mach-nbg460n.c ---- linux-2.6.39.orig/arch/mips/ar71xx/mach-nbg460n.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/mach-nbg460n.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,225 @@ -+/* -+ * Zyxel NBG 460N/550N/550NH board support -+ * -+ * Copyright (C) 2010 Michael Kurz -+ * -+ * based on mach-tl-wr1043nd.c -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ar9xxx-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+ -+/* LEDs */ -+#define NBG460N_GPIO_LED_WPS 3 -+#define NBG460N_GPIO_LED_WAN 6 -+#define NBG460N_GPIO_LED_POWER 14 -+#define NBG460N_GPIO_LED_WLAN 15 -+ -+/* Buttons */ -+#define NBG460N_GPIO_BTN_WPS 12 -+#define NBG460N_GPIO_BTN_RESET 21 -+ -+#define NBG460N_KEYS_POLL_INTERVAL 20 /* msecs */ -+#define NBG460N_KEYS_DEBOUNCE_INTERVAL (3 * NBG460N_KEYS_POLL_INTERVAL) -+ -+/* RTC chip PCF8563 I2C interface */ -+#define NBG460N_GPIO_PCF8563_SDA 8 -+#define NBG460N_GPIO_PCF8563_SCK 7 -+ -+/* Switch configuration I2C interface */ -+#define NBG460N_GPIO_RTL8366_SDA 16 -+#define NBG460N_GPIO_RTL8366_SCK 18 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition nbg460n_partitions[] = { -+ { -+ .name = "Bootbase", -+ .offset = 0, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "U-Boot Config", -+ .offset = 0x010000, -+ .size = 0x030000, -+ }, { -+ .name = "U-Boot", -+ .offset = 0x040000, -+ .size = 0x030000, -+ }, { -+ .name = "linux", -+ .offset = 0x070000, -+ .size = 0x0e0000, -+ }, { -+ .name = "rootfs", -+ .offset = 0x150000, -+ .size = 0x2a0000, -+ }, { -+ .name = "CalibData", -+ .offset = 0x3f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "firmware", -+ .offset = 0x070000, -+ .size = 0x380000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data nbg460n_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = nbg460n_partitions, -+ .nr_parts = ARRAY_SIZE(nbg460n_partitions), -+#endif -+}; -+ -+static struct gpio_led nbg460n_leds_gpio[] __initdata = { -+ { -+ .name = "nbg460n:green:power", -+ .gpio = NBG460N_GPIO_LED_POWER, -+ .active_low = 0, -+ .default_trigger = "default-on", -+ }, { -+ .name = "nbg460n:green:wps", -+ .gpio = NBG460N_GPIO_LED_WPS, -+ .active_low = 0, -+ }, { -+ .name = "nbg460n:green:wlan", -+ .gpio = NBG460N_GPIO_LED_WLAN, -+ .active_low = 0, -+ }, { -+ /* Not really for controlling the LED, -+ when set low the LED blinks uncontrollable */ -+ .name = "nbg460n:green:wan", -+ .gpio = NBG460N_GPIO_LED_WAN, -+ .active_low = 0, -+ } -+}; -+ -+static struct gpio_keys_button nbg460n_gpio_keys[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .debounce_interval = NBG460N_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = NBG460N_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "wps", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .debounce_interval = NBG460N_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = NBG460N_GPIO_BTN_WPS, -+ .active_low = 1, -+ } -+}; -+ -+static struct i2c_gpio_platform_data nbg460n_i2c_device_platdata = { -+ .sda_pin = NBG460N_GPIO_PCF8563_SDA, -+ .scl_pin = NBG460N_GPIO_PCF8563_SCK, -+ .udelay = 10, -+}; -+ -+static struct platform_device nbg460n_i2c_device = { -+ .name = "i2c-gpio", -+ .id = -1, -+ .num_resources = 0, -+ .resource = NULL, -+ .dev = { -+ .platform_data = &nbg460n_i2c_device_platdata, -+ }, -+}; -+ -+static struct i2c_board_info nbg460n_i2c_devs[] __initdata = { -+ { -+ I2C_BOARD_INFO("pcf8563", 0x51), -+ }, -+}; -+ -+static void __devinit nbg460n_i2c_init(void) -+{ -+ /* The gpio interface */ -+ platform_device_register(&nbg460n_i2c_device); -+ /* I2C devices */ -+ i2c_register_board_info(0, nbg460n_i2c_devs, -+ ARRAY_SIZE(nbg460n_i2c_devs)); -+} -+ -+ -+static struct rtl8366_platform_data nbg460n_rtl8366s_data = { -+ .gpio_sda = NBG460N_GPIO_RTL8366_SDA, -+ .gpio_sck = NBG460N_GPIO_RTL8366_SCK, -+}; -+ -+static struct platform_device nbg460n_rtl8366s_device = { -+ .name = RTL8366S_DRIVER_NAME, -+ .id = -1, -+ .dev = { -+ .platform_data = &nbg460n_rtl8366s_data, -+ } -+}; -+ -+static void __init nbg460n_setup(void) -+{ -+ /* end of bootloader sector contains mac address */ -+ u8 *mac = (u8 *) KSEG1ADDR(0x1fc0fff8); -+ /* last sector contains wlan calib data */ -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ -+ /* LAN Port */ -+ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac, 0); -+ ar71xx_eth0_data.mii_bus_dev = &nbg460n_rtl8366s_device.dev; -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth0_data.speed = SPEED_1000; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ -+ /* WAN Port */ -+ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, mac, 1); -+ ar71xx_eth1_data.mii_bus_dev = &nbg460n_rtl8366s_device.dev; -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth1_data.phy_mask = 0x10; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ /* register the switch phy */ -+ platform_device_register(&nbg460n_rtl8366s_device); -+ -+ /* register flash */ -+ ar71xx_add_device_m25p80(&nbg460n_flash_data); -+ -+ ar9xxx_add_device_wmac(eeprom, mac); -+ -+ /* register RTC chip */ -+ nbg460n_i2c_init(); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(nbg460n_leds_gpio), -+ nbg460n_leds_gpio); -+ -+ ar71xx_register_gpio_keys_polled(-1, NBG460N_KEYS_POLL_INTERVAL, -+ ARRAY_SIZE(nbg460n_gpio_keys), -+ nbg460n_gpio_keys); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_NBG460N, "NBG460N", "Zyxel NBG460N/550N/550NH", -+ nbg460n_setup); -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-pb42.c linux-2.6.39/arch/mips/ar71xx/mach-pb42.c ---- linux-2.6.39.orig/arch/mips/ar71xx/mach-pb42.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/mach-pb42.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,74 @@ -+/* -+ * Atheros PB42 board support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-gpio-buttons.h" -+#include "dev-pb42-pci.h" -+#include "dev-usb.h" -+ -+#define PB42_KEYS_POLL_INTERVAL 20 /* msecs */ -+#define PB42_KEYS_DEBOUNCE_INTERVAL (3 * PB42_KEYS_POLL_INTERVAL) -+ -+#define PB42_GPIO_BTN_SW4 8 -+#define PB42_GPIO_BTN_SW5 3 -+ -+static struct gpio_keys_button pb42_gpio_keys[] __initdata = { -+ { -+ .desc = "sw4", -+ .type = EV_KEY, -+ .code = BTN_0, -+ .debounce_interval = PB42_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = PB42_GPIO_BTN_SW4, -+ .active_low = 1, -+ }, { -+ .desc = "sw5", -+ .type = EV_KEY, -+ .code = BTN_1, -+ .debounce_interval = PB42_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = PB42_GPIO_BTN_SW5, -+ .active_low = 1, -+ } -+}; -+ -+#define PB42_WAN_PHYMASK BIT(20) -+#define PB42_LAN_PHYMASK (BIT(16) | BIT(17) | BIT(18) | BIT(19)) -+#define PB42_MDIO_PHYMASK (PB42_LAN_PHYMASK | PB42_WAN_PHYMASK) -+ -+static void __init pb42_init(void) -+{ -+ ar71xx_add_device_m25p80(NULL); -+ -+ ar71xx_add_device_mdio(~PB42_MDIO_PHYMASK); -+ -+ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, ar71xx_mac_base, 0); -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; -+ ar71xx_eth0_data.phy_mask = PB42_WAN_PHYMASK; -+ -+ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, ar71xx_mac_base, 1); -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.speed = SPEED_100; -+ ar71xx_eth1_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_register_gpio_keys_polled(-1, PB42_KEYS_POLL_INTERVAL, -+ ARRAY_SIZE(pb42_gpio_keys), -+ pb42_gpio_keys); -+ -+ pb42_pci_init(); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_PB42, "PB42", "Atheros PB42", pb42_init); -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-pb44.c linux-2.6.39/arch/mips/ar71xx/mach-pb44.c ---- linux-2.6.39.orig/arch/mips/ar71xx/mach-pb44.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/mach-pb44.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,213 @@ -+/* -+ * Atheros PB44 board support -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-pb42-pci.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-usb.h" -+ -+#define PB44_PCF8757_VSC7395_CS 0 -+#define PB44_PCF8757_STEREO_CS 1 -+#define PB44_PCF8757_SLIC_CS0 2 -+#define PB44_PCF8757_SLIC_TEST 3 -+#define PB44_PCF8757_SLIC_INT0 4 -+#define PB44_PCF8757_SLIC_INT1 5 -+#define PB44_PCF8757_SW_RESET 6 -+#define PB44_PCF8757_SW_JUMP 8 -+#define PB44_PCF8757_LED_JUMP1 9 -+#define PB44_PCF8757_LED_JUMP2 10 -+#define PB44_PCF8757_TP24 11 -+#define PB44_PCF8757_TP25 12 -+#define PB44_PCF8757_TP26 13 -+#define PB44_PCF8757_TP27 14 -+#define PB44_PCF8757_TP28 15 -+ -+#define PB44_GPIO_I2C_SCL 0 -+#define PB44_GPIO_I2C_SDA 1 -+ -+#define PB44_GPIO_EXP_BASE 16 -+#define PB44_GPIO_VSC7395_CS (PB44_GPIO_EXP_BASE + PB44_PCF8757_VSC7395_CS) -+#define PB44_GPIO_SW_RESET (PB44_GPIO_EXP_BASE + PB44_PCF8757_SW_RESET) -+#define PB44_GPIO_SW_JUMP (PB44_GPIO_EXP_BASE + PB44_PCF8757_SW_JUMP) -+#define PB44_GPIO_LED_JUMP1 (PB44_GPIO_EXP_BASE + PB44_PCF8757_LED_JUMP1) -+#define PB44_GPIO_LED_JUMP2 (PB44_GPIO_EXP_BASE + PB44_PCF8757_LED_JUMP2) -+ -+#define PB44_KEYS_POLL_INTERVAL 20 /* msecs */ -+#define PB44_KEYS_DEBOUNCE_INTERVAL (3 * PB44_KEYS_POLL_INTERVAL) -+ -+static struct i2c_gpio_platform_data pb44_i2c_gpio_data = { -+ .sda_pin = PB44_GPIO_I2C_SDA, -+ .scl_pin = PB44_GPIO_I2C_SCL, -+}; -+ -+static struct platform_device pb44_i2c_gpio_device = { -+ .name = "i2c-gpio", -+ .id = 0, -+ .dev = { -+ .platform_data = &pb44_i2c_gpio_data, -+ } -+}; -+ -+static struct pcf857x_platform_data pb44_pcf857x_data = { -+ .gpio_base = PB44_GPIO_EXP_BASE, -+}; -+ -+static struct i2c_board_info pb44_i2c_board_info[] __initdata = { -+ { -+ I2C_BOARD_INFO("pcf8575", 0x20), -+ .platform_data = &pb44_pcf857x_data, -+ }, -+}; -+ -+static struct gpio_led pb44_leds_gpio[] __initdata = { -+ { -+ .name = "pb44:amber:jump1", -+ .gpio = PB44_GPIO_LED_JUMP1, -+ .active_low = 1, -+ }, { -+ .name = "pb44:green:jump2", -+ .gpio = PB44_GPIO_LED_JUMP2, -+ .active_low = 1, -+ }, -+}; -+ -+static struct gpio_keys_button pb44_gpio_keys[] __initdata = { -+ { -+ .desc = "soft_reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .debounce_interval = PB44_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = PB44_GPIO_SW_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "jumpstart", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .debounce_interval = PB44_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = PB44_GPIO_SW_JUMP, -+ .active_low = 1, -+ } -+}; -+ -+static void pb44_vsc7395_reset(void) -+{ -+ ar71xx_device_stop(RESET_MODULE_GE1_PHY); -+ udelay(10); -+ ar71xx_device_start(RESET_MODULE_GE1_PHY); -+ mdelay(50); -+} -+ -+static struct vsc7385_platform_data pb44_vsc7395_data = { -+ .reset = pb44_vsc7395_reset, -+ .ucode_name = "vsc7395_ucode_pb44.bin", -+ .mac_cfg = { -+ .tx_ipg = 6, -+ .bit2 = 1, -+ .clk_sel = 0, -+ }, -+}; -+ -+static struct spi_board_info pb44_spi_info[] = { -+ { -+ .bus_num = 0, -+ .chip_select = 0, -+ .max_speed_hz = 25000000, -+ .modalias = "m25p80", -+ }, { -+ .bus_num = 0, -+ .chip_select = 1, -+ .max_speed_hz = 25000000, -+ .modalias = "spi-vsc7385", -+ .platform_data = &pb44_vsc7395_data, -+ .controller_data = (void *) PB44_GPIO_VSC7395_CS, -+ }, -+}; -+ -+static struct resource pb44_spi_resources[] = { -+ [0] = { -+ .start = AR71XX_SPI_BASE, -+ .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+}; -+ -+static struct ar71xx_spi_platform_data pb44_spi_data = { -+ .bus_num = 0, -+ .num_chipselect = 2, -+}; -+ -+static struct platform_device pb44_spi_device = { -+ .name = "pb44-spi", -+ .id = -1, -+ .resource = pb44_spi_resources, -+ .num_resources = ARRAY_SIZE(pb44_spi_resources), -+ .dev = { -+ .platform_data = &pb44_spi_data, -+ }, -+}; -+ -+#define PB44_WAN_PHYMASK BIT(0) -+#define PB44_LAN_PHYMASK 0 -+#define PB44_MDIO_PHYMASK (PB44_LAN_PHYMASK | PB44_WAN_PHYMASK) -+ -+static void __init pb44_init(void) -+{ -+ ar71xx_add_device_mdio(~PB44_MDIO_PHYMASK); -+ -+ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, ar71xx_mac_base, 0); -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth0_data.phy_mask = PB44_WAN_PHYMASK; -+ -+ ar71xx_add_device_eth(0); -+ -+ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, ar71xx_mac_base, 1); -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth1_data.speed = SPEED_1000; -+ ar71xx_eth1_data.duplex = DUPLEX_FULL; -+ ar71xx_eth1_pll_data.pll_1000 = 0x110000; -+ -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_usb(); -+ -+ pb42_pci_init(); -+ -+ i2c_register_board_info(0, pb44_i2c_board_info, -+ ARRAY_SIZE(pb44_i2c_board_info)); -+ -+ platform_device_register(&pb44_i2c_gpio_device); -+ -+ spi_register_board_info(pb44_spi_info, ARRAY_SIZE(pb44_spi_info)); -+ platform_device_register(&pb44_spi_device); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(pb44_leds_gpio), -+ pb44_leds_gpio); -+ -+ ar71xx_register_gpio_keys_polled(-1, PB44_KEYS_POLL_INTERVAL, -+ ARRAY_SIZE(pb44_gpio_keys), -+ pb44_gpio_keys); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_PB44, "PB44", "Atheros PB44", pb44_init); -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-pb92.c linux-2.6.39/arch/mips/ar71xx/mach-pb92.c ---- linux-2.6.39.orig/arch/mips/ar71xx/mach-pb92.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/mach-pb92.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,105 @@ -+/* -+ * Atheros PB92 board support -+ * -+ * Copyright (C) 2010 Felix Fietkau -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-gpio-buttons.h" -+#include "dev-pb9x-pci.h" -+#include "dev-usb.h" -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition pb92_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x040000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "u-boot-env", -+ .offset = 0x040000, -+ .size = 0x010000, -+ }, { -+ .name = "rootfs", -+ .offset = 0x050000, -+ .size = 0x2b0000, -+ }, { -+ .name = "uImage", -+ .offset = 0x300000, -+ .size = 0x0e0000, -+ }, { -+ .name = "ART", -+ .offset = 0x3e0000, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data pb92_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = pb92_partitions, -+ .nr_parts = ARRAY_SIZE(pb92_partitions), -+#endif -+}; -+ -+#define PB92_KEYS_POLL_INTERVAL 20 /* msecs */ -+#define PB92_KEYS_DEBOUNCE_INTERVAL (3 * PB92_KEYS_POLL_INTERVAL) -+ -+#define PB92_GPIO_BTN_SW4 8 -+#define PB92_GPIO_BTN_SW5 3 -+ -+static struct gpio_keys_button pb92_gpio_keys[] __initdata = { -+ { -+ .desc = "sw4", -+ .type = EV_KEY, -+ .code = BTN_0, -+ .debounce_interval = PB92_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = PB92_GPIO_BTN_SW4, -+ .active_low = 1, -+ }, { -+ .desc = "sw5", -+ .type = EV_KEY, -+ .code = BTN_1, -+ .debounce_interval = PB92_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = PB92_GPIO_BTN_SW5, -+ .active_low = 1, -+ } -+}; -+ -+static void __init pb92_init(void) -+{ -+ u8 *mac = (u8 *) KSEG1ADDR(0x1fff0000); -+ -+ ar71xx_add_device_m25p80(&pb92_flash_data); -+ -+ ar71xx_add_device_mdio(~BIT(0)); -+ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac, 0); -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth0_data.speed = SPEED_1000; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ ar71xx_eth0_data.phy_mask = BIT(0); -+ -+ ar71xx_add_device_eth(0); -+ -+ ar71xx_register_gpio_keys_polled(-1, PB92_KEYS_POLL_INTERVAL, -+ ARRAY_SIZE(pb92_gpio_keys), -+ pb92_gpio_keys); -+ -+ pb9x_pci_init(); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_PB92, "PB92", "Atheros PB92", pb92_init); -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-rb4xx.c linux-2.6.39/arch/mips/ar71xx/mach-rb4xx.c ---- linux-2.6.39.orig/arch/mips/ar71xx/mach-rb4xx.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/mach-rb4xx.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,344 @@ -+/* -+ * MikroTik RouterBOARD 4xx series support -+ * -+ * Copyright (C) 2008-2010 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-usb.h" -+ -+#define RB4XX_GPIO_USER_LED 4 -+#define RB4XX_GPIO_RESET_SWITCH 7 -+ -+#define RB4XX_GPIO_CPLD_BASE 32 -+#define RB4XX_GPIO_CPLD_LED1 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED1) -+#define RB4XX_GPIO_CPLD_LED2 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED2) -+#define RB4XX_GPIO_CPLD_LED3 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED3) -+#define RB4XX_GPIO_CPLD_LED4 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED4) -+#define RB4XX_GPIO_CPLD_LED5 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED5) -+ -+#define RB4XX_KEYS_POLL_INTERVAL 20 /* msecs */ -+#define RB4XX_KEYS_DEBOUNCE_INTERVAL (3 * RB4XX_KEYS_POLL_INTERVAL) -+ -+static struct gpio_led rb4xx_leds_gpio[] __initdata = { -+ { -+ .name = "rb4xx:yellow:user", -+ .gpio = RB4XX_GPIO_USER_LED, -+ .active_low = 0, -+ }, { -+ .name = "rb4xx:green:led1", -+ .gpio = RB4XX_GPIO_CPLD_LED1, -+ .active_low = 1, -+ }, { -+ .name = "rb4xx:green:led2", -+ .gpio = RB4XX_GPIO_CPLD_LED2, -+ .active_low = 1, -+ }, { -+ .name = "rb4xx:green:led3", -+ .gpio = RB4XX_GPIO_CPLD_LED3, -+ .active_low = 1, -+ }, { -+ .name = "rb4xx:green:led4", -+ .gpio = RB4XX_GPIO_CPLD_LED4, -+ .active_low = 1, -+ }, { -+ .name = "rb4xx:green:led5", -+ .gpio = RB4XX_GPIO_CPLD_LED5, -+ .active_low = 0, -+ }, -+}; -+ -+static struct gpio_keys_button rb4xx_gpio_keys[] __initdata = { -+ { -+ .desc = "reset_switch", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .debounce_interval = RB4XX_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = RB4XX_GPIO_RESET_SWITCH, -+ .active_low = 1, -+ } -+}; -+ -+static struct platform_device rb4xx_nand_device = { -+ .name = "rb4xx-nand", -+ .id = -1, -+}; -+ -+static struct ar71xx_pci_irq rb4xx_pci_irqs[] __initdata = { -+ { -+ .slot = 0, -+ .pin = 1, -+ .irq = AR71XX_PCI_IRQ_DEV2, -+ }, { -+ .slot = 1, -+ .pin = 1, -+ .irq = AR71XX_PCI_IRQ_DEV0, -+ }, { -+ .slot = 1, -+ .pin = 2, -+ .irq = AR71XX_PCI_IRQ_DEV1, -+ }, { -+ .slot = 2, -+ .pin = 1, -+ .irq = AR71XX_PCI_IRQ_DEV1, -+ }, { -+ .slot = 3, -+ .pin = 1, -+ .irq = AR71XX_PCI_IRQ_DEV2, -+ } -+}; -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition rb4xx_partitions[] = { -+ { -+ .name = "routerboot", -+ .offset = 0, -+ .size = 0x0b000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "hard_config", -+ .offset = 0x0b000, -+ .size = 0x01000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "bios", -+ .offset = 0x0d000, -+ .size = 0x02000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "soft_config", -+ .offset = 0x0f000, -+ .size = 0x01000, -+ } -+}; -+#define rb4xx_num_partitions ARRAY_SIZE(rb4xx_partitions) -+#else /* CONFIG_MTD_PARTITIONS */ -+#define rb4xx_partitions NULL -+#define rb4xx_num_partitions 0 -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data rb4xx_flash_data = { -+ .type = "pm25lv512", -+ .parts = rb4xx_partitions, -+ .nr_parts = rb4xx_num_partitions, -+}; -+ -+static struct rb4xx_cpld_platform_data rb4xx_cpld_data = { -+ .gpio_base = RB4XX_GPIO_CPLD_BASE, -+}; -+ -+static struct mmc_spi_platform_data rb4xx_mmc_data = { -+ .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, -+}; -+ -+static struct spi_board_info rb4xx_spi_info[] = { -+ { -+ .bus_num = 0, -+ .chip_select = 0, -+ .max_speed_hz = 25000000, -+ .modalias = "m25p80", -+ .platform_data = &rb4xx_flash_data, -+ }, { -+ .bus_num = 0, -+ .chip_select = 1, -+ .max_speed_hz = 25000000, -+ .modalias = "spi-rb4xx-cpld", -+ .platform_data = &rb4xx_cpld_data, -+ } -+}; -+ -+static struct spi_board_info rb4xx_microsd_info[] = { -+ { -+ .bus_num = 0, -+ .chip_select = 2, -+ .max_speed_hz = 25000000, -+ .modalias = "mmc_spi", -+ .platform_data = &rb4xx_mmc_data, -+ } -+}; -+ -+ -+static struct resource rb4xx_spi_resources[] = { -+ { -+ .start = AR71XX_SPI_BASE, -+ .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+}; -+ -+static struct platform_device rb4xx_spi_device = { -+ .name = "rb4xx-spi", -+ .id = -1, -+ .resource = rb4xx_spi_resources, -+ .num_resources = ARRAY_SIZE(rb4xx_spi_resources), -+}; -+ -+static void __init rb4xx_generic_setup(void) -+{ -+ ar71xx_gpio_function_enable(AR71XX_GPIO_FUNC_SPI_CS1_EN | -+ AR71XX_GPIO_FUNC_SPI_CS2_EN); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(rb4xx_leds_gpio), -+ rb4xx_leds_gpio); -+ -+ ar71xx_register_gpio_keys_polled(-1, RB4XX_KEYS_POLL_INTERVAL, -+ ARRAY_SIZE(rb4xx_gpio_keys), -+ rb4xx_gpio_keys); -+ -+ spi_register_board_info(rb4xx_spi_info, ARRAY_SIZE(rb4xx_spi_info)); -+ platform_device_register(&rb4xx_spi_device); -+ platform_device_register(&rb4xx_nand_device); -+} -+ -+static void __init rb411_setup(void) -+{ -+ rb4xx_generic_setup(); -+ spi_register_board_info(rb4xx_microsd_info, -+ ARRAY_SIZE(rb4xx_microsd_info)); -+ -+ ar71xx_add_device_mdio(0xfffffffc); -+ -+ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, ar71xx_mac_base, 0); -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; -+ ar71xx_eth0_data.phy_mask = 0x00000003; -+ -+ ar71xx_add_device_eth(0); -+ -+ ar71xx_pci_init(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_RB_411, "411", "MikroTik RouterBOARD 411/A/AH", -+ rb411_setup); -+ -+static void __init rb411u_setup(void) -+{ -+ rb411_setup(); -+ ar71xx_add_device_usb(); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_RB_411U, "411U", "MikroTik RouterBOARD 411U", -+ rb411u_setup); -+ -+#define RB433_LAN_PHYMASK BIT(0) -+#define RB433_WAN_PHYMASK BIT(4) -+#define RB433_MDIO_PHYMASK (RB433_LAN_PHYMASK | RB433_WAN_PHYMASK) -+ -+static void __init rb433_setup(void) -+{ -+ rb4xx_generic_setup(); -+ spi_register_board_info(rb4xx_microsd_info, -+ ARRAY_SIZE(rb4xx_microsd_info)); -+ -+ ar71xx_add_device_mdio(~RB433_MDIO_PHYMASK); -+ -+ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, ar71xx_mac_base, 1); -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; -+ ar71xx_eth0_data.phy_mask = RB433_LAN_PHYMASK; -+ -+ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, ar71xx_mac_base, 0); -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.phy_mask = RB433_WAN_PHYMASK; -+ -+ ar71xx_add_device_eth(1); -+ ar71xx_add_device_eth(0); -+ -+ ar71xx_pci_init(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_RB_433, "433", "MikroTik RouterBOARD 433/AH", -+ rb433_setup); -+ -+static void __init rb433u_setup(void) -+{ -+ rb433_setup(); -+ ar71xx_add_device_usb(); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_RB_433U, "433U", "MikroTik RouterBOARD 433UAH", -+ rb433u_setup); -+ -+#define RB450_LAN_PHYMASK BIT(0) -+#define RB450_WAN_PHYMASK BIT(4) -+#define RB450_MDIO_PHYMASK (RB450_LAN_PHYMASK | RB450_WAN_PHYMASK) -+ -+static void __init rb450_generic_setup(int gige) -+{ -+ rb4xx_generic_setup(); -+ ar71xx_add_device_mdio(~RB450_MDIO_PHYMASK); -+ -+ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, ar71xx_mac_base, 1); -+ ar71xx_eth0_data.phy_if_mode = (gige) ? -+ PHY_INTERFACE_MODE_RGMII : PHY_INTERFACE_MODE_MII; -+ ar71xx_eth0_data.phy_mask = RB450_LAN_PHYMASK; -+ -+ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, ar71xx_mac_base, 0); -+ ar71xx_eth1_data.phy_if_mode = (gige) ? -+ PHY_INTERFACE_MODE_RGMII : PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.phy_mask = RB450_WAN_PHYMASK; -+ -+ ar71xx_add_device_eth(1); -+ ar71xx_add_device_eth(0); -+} -+ -+static void __init rb450_setup(void) -+{ -+ rb450_generic_setup(0); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_RB_450, "450", "MikroTik RouterBOARD 450", -+ rb450_setup); -+ -+static void __init rb450g_setup(void) -+{ -+ rb450_generic_setup(1); -+ spi_register_board_info(rb4xx_microsd_info, -+ ARRAY_SIZE(rb4xx_microsd_info)); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_RB_450G, "450G", "MikroTik RouterBOARD 450G", -+ rb450g_setup); -+ -+static void __init rb493_setup(void) -+{ -+ rb4xx_generic_setup(); -+ -+ ar71xx_add_device_mdio(0x3fffff00); -+ -+ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, ar71xx_mac_base, 0); -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, ar71xx_mac_base, 1); -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.phy_mask = 0x00000001; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_pci_init(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_RB_493, "493", "MikroTik RouterBOARD 493/AH", -+ rb493_setup); -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-rb750.c linux-2.6.39/arch/mips/ar71xx/mach-rb750.c ---- linux-2.6.39.orig/arch/mips/ar71xx/mach-rb750.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/mach-rb750.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,144 @@ -+/* -+ * MikroTik RouterBOARD 750 support -+ * -+ * Copyright (C) 2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+ -+static struct rb750_led_data rb750_leds[] = { -+ { -+ .name = "rb750:green:act", -+ .mask = RB750_LED_ACT, -+ .active_low = 1, -+ }, { -+ .name = "rb750:green:port1", -+ .mask = RB750_LED_PORT5, -+ .active_low = 1, -+ }, { -+ .name = "rb750:green:port2", -+ .mask = RB750_LED_PORT4, -+ .active_low = 1, -+ }, { -+ .name = "rb750:green:port3", -+ .mask = RB750_LED_PORT3, -+ .active_low = 1, -+ }, { -+ .name = "rb750:green:port4", -+ .mask = RB750_LED_PORT2, -+ .active_low = 1, -+ }, { -+ .name = "rb750:green:port5", -+ .mask = RB750_LED_PORT1, -+ .active_low = 1, -+ } -+}; -+ -+static struct rb750_led_platform_data rb750_leds_data = { -+ .num_leds = ARRAY_SIZE(rb750_leds), -+ .leds = rb750_leds, -+}; -+ -+static struct platform_device rb750_leds_device = { -+ .name = "leds-rb750", -+ .dev = { -+ .platform_data = &rb750_leds_data, -+ } -+}; -+ -+static struct platform_device rb750_nand_device = { -+ .name = "rb750-nand", -+ .id = -1, -+}; -+ -+int rb750_latch_change(u32 mask_clr, u32 mask_set) -+{ -+ static DEFINE_SPINLOCK(lock); -+ static u32 latch_set = RB750_LED_BITS | RB750_LVC573_LE; -+ static u32 latch_oe; -+ static u32 latch_clr; -+ unsigned long flags; -+ u32 t; -+ int ret = 0; -+ -+ spin_lock_irqsave(&lock, flags); -+ -+ if ((mask_clr & BIT(31)) != 0 && -+ (latch_set & RB750_LVC573_LE) == 0) { -+ goto unlock; -+ } -+ -+ latch_set = (latch_set | mask_set) & ~mask_clr; -+ latch_clr = (latch_clr | mask_clr) & ~mask_set; -+ -+ if (latch_oe == 0) -+ latch_oe = __raw_readl(ar71xx_gpio_base + GPIO_REG_OE); -+ -+ if (likely(latch_set & RB750_LVC573_LE)) { -+ void __iomem *base = ar71xx_gpio_base; -+ -+ t = __raw_readl(base + GPIO_REG_OE); -+ t |= mask_clr | latch_oe | mask_set; -+ -+ __raw_writel(t, base + GPIO_REG_OE); -+ __raw_writel(latch_clr, base + GPIO_REG_CLEAR); -+ __raw_writel(latch_set, base + GPIO_REG_SET); -+ } else if (mask_clr & RB750_LVC573_LE) { -+ void __iomem *base = ar71xx_gpio_base; -+ -+ latch_oe = __raw_readl(base + GPIO_REG_OE); -+ __raw_writel(RB750_LVC573_LE, base + GPIO_REG_CLEAR); -+ /* flush write */ -+ __raw_readl(base + GPIO_REG_CLEAR); -+ } -+ -+ ret = 1; -+ -+unlock: -+ spin_unlock_irqrestore(&lock, flags); -+ return ret; -+} -+EXPORT_SYMBOL_GPL(rb750_latch_change); -+ -+static void __init rb750_setup(void) -+{ -+ ar71xx_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN | -+ AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN | -+ AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN | -+ AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN | -+ AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN); -+ -+ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, ar71xx_mac_base, 0); -+ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, ar71xx_mac_base, 1); -+ -+ /* WAN port */ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ ar71xx_eth0_data.phy_mask = BIT(4); -+ -+ /* LAN ports */ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.speed = SPEED_1000; -+ ar71xx_eth1_data.duplex = DUPLEX_FULL; -+ ar71xx_eth1_data.has_ar7240_switch = 1; -+ -+ ar71xx_add_device_mdio(0x0); -+ ar71xx_add_device_eth(1); -+ ar71xx_add_device_eth(0); -+ -+ platform_device_register(&rb750_leds_device); -+ platform_device_register(&rb750_nand_device); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_RB_750, "750i", "MikroTik RouterBOARD 750", -+ rb750_setup); -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-tew-632brp.c linux-2.6.39/arch/mips/ar71xx/mach-tew-632brp.c ---- linux-2.6.39.orig/arch/mips/ar71xx/mach-tew-632brp.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/mach-tew-632brp.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,151 @@ -+/* -+ * TrendNET TEW-632BRP board support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ar9xxx-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "nvram.h" -+ -+#define TEW_632BRP_GPIO_LED_STATUS 1 -+#define TEW_632BRP_GPIO_LED_WPS 3 -+#define TEW_632BRP_GPIO_LED_WLAN 6 -+#define TEW_632BRP_GPIO_BTN_WPS 12 -+#define TEW_632BRP_GPIO_BTN_RESET 21 -+ -+#define TEW_632BRP_KEYS_POLL_INTERVAL 20 /* msecs */ -+#define TEW_632BRP_KEYS_DEBOUNCE_INTERVAL (3 * TEW_632BRP_KEYS_POLL_INTERVAL) -+ -+#define TEW_632BRP_CONFIG_ADDR 0x1f020000 -+#define TEW_632BRP_CONFIG_SIZE 0x10000 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition tew_632brp_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "config", -+ .offset = 0x020000, -+ .size = 0x010000, -+ }, { -+ .name = "kernel", -+ .offset = 0x030000, -+ .size = 0x0e0000, -+ }, { -+ .name = "rootfs", -+ .offset = 0x110000, -+ .size = 0x2e0000, -+ }, { -+ .name = "art", -+ .offset = 0x3f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "firmware", -+ .offset = 0x030000, -+ .size = 0x3c0000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data tew_632brp_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = tew_632brp_partitions, -+ .nr_parts = ARRAY_SIZE(tew_632brp_partitions), -+#endif -+}; -+ -+static struct gpio_led tew_632brp_leds_gpio[] __initdata = { -+ { -+ .name = "tew-632brp:green:status", -+ .gpio = TEW_632BRP_GPIO_LED_STATUS, -+ .active_low = 1, -+ }, { -+ .name = "tew-632brp:blue:wps", -+ .gpio = TEW_632BRP_GPIO_LED_WPS, -+ .active_low = 1, -+ }, { -+ .name = "tew-632brp:green:wlan", -+ .gpio = TEW_632BRP_GPIO_LED_WLAN, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_keys_button tew_632brp_gpio_keys[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .debounce_interval = TEW_632BRP_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = TEW_632BRP_GPIO_BTN_RESET, -+ }, { -+ .desc = "wps", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .debounce_interval = TEW_632BRP_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = TEW_632BRP_GPIO_BTN_WPS, -+ } -+}; -+ -+#define TEW_632BRP_LAN_PHYMASK BIT(0) -+#define TEW_632BRP_WAN_PHYMASK BIT(4) -+#define TEW_632BRP_MDIO_MASK (~(TEW_632BRP_LAN_PHYMASK | \ -+ TEW_632BRP_WAN_PHYMASK)) -+ -+static void __init tew_632brp_setup(void) -+{ -+ const char *config = (char *) KSEG1ADDR(TEW_632BRP_CONFIG_ADDR); -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ u8 mac[6]; -+ u8 *wlan_mac = NULL; -+ -+ if (nvram_parse_mac_addr(config, TEW_632BRP_CONFIG_SIZE, -+ "lan_mac=", mac) == 0) { -+ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac, 0); -+ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, mac, 1); -+ wlan_mac = mac; -+ } -+ -+ ar71xx_add_device_mdio(TEW_632BRP_MDIO_MASK); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.phy_mask = TEW_632BRP_LAN_PHYMASK; -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.phy_mask = TEW_632BRP_WAN_PHYMASK; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_m25p80(&tew_632brp_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(tew_632brp_leds_gpio), -+ tew_632brp_leds_gpio); -+ -+ ar71xx_register_gpio_keys_polled(-1, TEW_632BRP_KEYS_POLL_INTERVAL, -+ ARRAY_SIZE(tew_632brp_gpio_keys), -+ tew_632brp_gpio_keys); -+ -+ ar9xxx_add_device_wmac(eeprom, wlan_mac); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_TEW_632BRP, "TEW-632BRP", "TRENDnet TEW-632BRP", -+ tew_632brp_setup); -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-tl-mr3x20.c linux-2.6.39/arch/mips/ar71xx/mach-tl-mr3x20.c ---- linux-2.6.39.orig/arch/mips/ar71xx/mach-tl-mr3x20.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/mach-tl-mr3x20.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,166 @@ -+/* -+ * TP-LINK TL-MR3220/3420 board support -+ * -+ * Copyright (C) 2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ap91-pci.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-usb.h" -+ -+#define TL_MR3X20_GPIO_LED_QSS 0 -+#define TL_MR3X20_GPIO_LED_SYSTEM 1 -+#define TL_MR3X20_GPIO_LED_3G 8 -+ -+#define TL_MR3X20_GPIO_BTN_RESET 11 -+#define TL_MR3X20_GPIO_BTN_QSS 12 -+ -+#define TL_MR3X20_GPIO_USB_POWER 6 -+ -+#define TL_MR3X20_KEYS_POLL_INTERVAL 20 /* msecs */ -+#define TL_MR3X20_KEYS_DEBOUNCE_INTERVAL (3 * TL_MR3X20_KEYS_POLL_INTERVAL) -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition tl_mr3x20_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "kernel", -+ .offset = 0x020000, -+ .size = 0x140000, -+ }, { -+ .name = "rootfs", -+ .offset = 0x160000, -+ .size = 0x290000, -+ }, { -+ .name = "art", -+ .offset = 0x3f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "firmware", -+ .offset = 0x020000, -+ .size = 0x3d0000, -+ } -+}; -+#define tl_mr3x20_num_partitions ARRAY_SIZE(tl_mr3x20_partitions) -+#else -+#define tl_mr3x20_partitions NULL -+#define tl_mr3x20_num_partitions 0 -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data tl_mr3x20_flash_data = { -+ .parts = tl_mr3x20_partitions, -+ .nr_parts = tl_mr3x20_num_partitions, -+}; -+ -+static struct gpio_led tl_mr3x20_leds_gpio[] __initdata = { -+ { -+ .name = "tl-mr3x20:green:system", -+ .gpio = TL_MR3X20_GPIO_LED_SYSTEM, -+ .active_low = 1, -+ }, { -+ .name = "tl-mr3x20:green:qss", -+ .gpio = TL_MR3X20_GPIO_LED_QSS, -+ .active_low = 1, -+ }, { -+ .name = "tl-mr3x20:green:3g", -+ .gpio = TL_MR3X20_GPIO_LED_3G, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_keys_button tl_mr3x20_gpio_keys[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .debounce_interval = TL_MR3X20_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = TL_MR3X20_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "qss", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .debounce_interval = TL_MR3X20_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = TL_MR3X20_GPIO_BTN_QSS, -+ .active_low = 1, -+ } -+}; -+ -+static void __init tl_mr3x20_setup(void) -+{ -+ u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); -+ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); -+ -+ /* enable power for the USB port */ -+ gpio_request(TL_MR3X20_GPIO_USB_POWER, "USB power"); -+ gpio_direction_output(TL_MR3X20_GPIO_USB_POWER, 1); -+ -+ ar71xx_add_device_m25p80(&tl_mr3x20_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(tl_mr3x20_leds_gpio), -+ tl_mr3x20_leds_gpio); -+ -+ ar71xx_register_gpio_keys_polled(-1, TL_MR3X20_KEYS_POLL_INTERVAL, -+ ARRAY_SIZE(tl_mr3x20_gpio_keys), -+ tl_mr3x20_gpio_keys); -+ -+ ar71xx_eth1_data.has_ar7240_switch = 1; -+ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac, 0); -+ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, mac, 1); -+ -+ /* WAN port */ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ ar71xx_eth0_data.phy_mask = BIT(4); -+ -+ /* LAN ports */ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.speed = SPEED_1000; -+ ar71xx_eth1_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_add_device_mdio(0x0); -+ ar71xx_add_device_eth(1); -+ ar71xx_add_device_eth(0); -+ -+ ar71xx_add_device_usb(); -+ -+ ap91_pci_init(ee, mac); -+} -+ -+static void __init tl_mr3220_setup(void) -+{ -+ tl_mr3x20_setup(); -+ ap91_pci_setup_wmac_led_pin(1); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_TL_MR3220, "TL-MR3220", "TP-LINK TL-MR3220", -+ tl_mr3220_setup); -+ -+static void __init tl_mr3420_setup(void) -+{ -+ tl_mr3x20_setup(); -+ ap91_pci_setup_wmac_led_pin(0); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_TL_MR3420, "TL-MR3420", "TP-LINK TL-MR3420", -+ tl_mr3420_setup); -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-tl-wa901nd-v2.c linux-2.6.39/arch/mips/ar71xx/mach-tl-wa901nd-v2.c ---- linux-2.6.39.orig/arch/mips/ar71xx/mach-tl-wa901nd-v2.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/mach-tl-wa901nd-v2.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,132 @@ -+/* -+ * TP-LINK TL-WA901ND v2 board support -+ * -+ * Copyright (C) 2009-2010 Gabor Juhos -+ * Copyright (C) 2010 Pieter Hollants -+ * Copyright (C) 2011 Jonathan Bennett -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-ar9xxx-wmac.h" -+ -+#define TL_WA901ND_V2_GPIO_LED_QSS 4 -+#define TL_WA901ND_V2_GPIO_LED_SYSTEM 2 -+#define TL_WA901ND_V2_GPIO_LED_WLAN 9 -+ -+ -+#define TL_WA901ND_V2_GPIO_BTN_RESET 3 -+#define TL_WA901ND_V2_GPIO_BTN_QSS 7 -+ -+#define TL_WA901ND_V2_KEYS_POLL_INTERVAL 20 /* msecs */ -+#define TL_WA901ND_V2_KEYS_DEBOUNCE_INTERVAL \ -+ (3 * TL_WA901ND_V2_KEYS_POLL_INTERVAL) -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition tl_wa901nd_v2_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "kernel", -+ .offset = 0x020000, -+ .size = 0x140000, -+ }, { -+ .name = "rootfs", -+ .offset = 0x160000, -+ .size = 0x290000, -+ }, { -+ .name = "art", -+ .offset = 0x3f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "firmware", -+ .offset = 0x020000, -+ .size = 0x3d0000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data tl_wa901nd_v2_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = tl_wa901nd_v2_partitions, -+ .nr_parts = ARRAY_SIZE(tl_wa901nd_v2_partitions), -+#endif -+}; -+ -+static struct gpio_led tl_wa901nd_v2_leds_gpio[] __initdata = { -+ { -+ .name = "tl-wa901nd-v2:green:system", -+ .gpio = TL_WA901ND_V2_GPIO_LED_SYSTEM, -+ .active_low = 1, -+ }, { -+ .name = "tl-wa901nd-v2:green:qss", -+ .gpio = TL_WA901ND_V2_GPIO_LED_QSS, -+ }, { -+ .name = "tl-wa901nd-v2:green:wlan", -+ .gpio = TL_WA901ND_V2_GPIO_LED_WLAN, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_keys_button tl_wa901nd_v2_gpio_keys[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .debounce_interval = TL_WA901ND_V2_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = TL_WA901ND_V2_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "qss", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .debounce_interval = TL_WA901ND_V2_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = TL_WA901ND_V2_GPIO_BTN_QSS, -+ .active_low = 1, -+ } -+}; -+ -+static void __init tl_wa901nd_v2_setup(void) -+{ -+ u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ -+ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac, 0); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; -+ ar71xx_eth0_data.phy_mask = 0x00001000; -+ ar71xx_add_device_mdio(0x0); -+ -+ ar71xx_eth0_data.reset_bit = RESET_MODULE_GE0_MAC | -+ RESET_MODULE_GE0_PHY; -+ ar71xx_add_device_eth(0); -+ -+ ar71xx_add_device_m25p80(&tl_wa901nd_v2_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(tl_wa901nd_v2_leds_gpio), -+ tl_wa901nd_v2_leds_gpio); -+ -+ ar71xx_register_gpio_keys_polled(-1, TL_WA901ND_V2_KEYS_POLL_INTERVAL, -+ ARRAY_SIZE(tl_wa901nd_v2_gpio_keys), -+ tl_wa901nd_v2_gpio_keys); -+ -+ ar9xxx_add_device_wmac(eeprom, mac); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_TL_WA901ND_V2, "TL-WA901ND-v2", -+ "TP-LINK TL-WA901ND v2", tl_wa901nd_v2_setup); -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-tl-wa901nd.c linux-2.6.39/arch/mips/ar71xx/mach-tl-wa901nd.c ---- linux-2.6.39.orig/arch/mips/ar71xx/mach-tl-wa901nd.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/mach-tl-wa901nd.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,130 @@ -+/* -+ * TP-LINK TL-WA901ND board support -+ * -+ * Copyright (C) 2009-2010 Gabor Juhos -+ * Copyright (C) 2010 Pieter Hollants -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ap91-pci.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+ -+#define TL_WA901ND_GPIO_LED_QSS 0 -+#define TL_WA901ND_GPIO_LED_SYSTEM 1 -+ -+#define TL_WA901ND_GPIO_BTN_RESET 11 -+#define TL_WA901ND_GPIO_BTN_QSS 12 -+ -+#define TL_WA901ND_KEYS_POLL_INTERVAL 20 /* msecs */ -+#define TL_WA901ND_KEYS_DEBOUNCE_INTERVAL (3 * TL_WA901ND_KEYS_POLL_INTERVAL) -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition tl_wa901nd_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "kernel", -+ .offset = 0x020000, -+ .size = 0x140000, -+ }, { -+ .name = "rootfs", -+ .offset = 0x160000, -+ .size = 0x290000, -+ }, { -+ .name = "art", -+ .offset = 0x3f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "firmware", -+ .offset = 0x020000, -+ .size = 0x3d0000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data tl_wa901nd_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = tl_wa901nd_partitions, -+ .nr_parts = ARRAY_SIZE(tl_wa901nd_partitions), -+#endif -+}; -+ -+static struct gpio_led tl_wa901nd_leds_gpio[] __initdata = { -+ { -+ .name = "tl-wa901nd:green:system", -+ .gpio = TL_WA901ND_GPIO_LED_SYSTEM, -+ .active_low = 1, -+ }, { -+ .name = "tl-wa901nd:green:qss", -+ .gpio = TL_WA901ND_GPIO_LED_QSS, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_keys_button tl_wa901nd_gpio_keys[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = BTN_0, -+ .debounce_interval = TL_WA901ND_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = TL_WA901ND_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "qss", -+ .type = EV_KEY, -+ .code = BTN_1, -+ .debounce_interval = TL_WA901ND_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = TL_WA901ND_GPIO_BTN_QSS, -+ .active_low = 1, -+ } -+}; -+ -+static void __init tl_wa901nd_setup(void) -+{ -+ u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); -+ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); -+ -+ /* -+ * ar71xx_eth0 would be the WAN port, but is not connected on -+ * the TL-WA901ND. ar71xx_eth1 connects to the internal switch chip, -+ * however we have a single LAN port only. -+ */ -+ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, mac, 0); -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.speed = SPEED_1000; -+ ar71xx_eth1_data.duplex = DUPLEX_FULL; -+ ar71xx_eth1_data.has_ar7240_switch = 1; -+ -+ ar71xx_add_device_mdio(0x0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_m25p80(&tl_wa901nd_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(tl_wa901nd_leds_gpio), -+ tl_wa901nd_leds_gpio); -+ -+ ar71xx_register_gpio_keys_polled(-1, TL_WA901ND_KEYS_POLL_INTERVAL, -+ ARRAY_SIZE(tl_wa901nd_gpio_keys), -+ tl_wa901nd_gpio_keys); -+ -+ ap91_pci_init(ee, mac); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_TL_WA901ND, "TL-WA901ND", "TP-LINK TL-WA901ND", -+ tl_wa901nd_setup); -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-tl-wr1043nd.c linux-2.6.39/arch/mips/ar71xx/mach-tl-wr1043nd.c ---- linux-2.6.39.orig/arch/mips/ar71xx/mach-tl-wr1043nd.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/mach-tl-wr1043nd.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,156 @@ -+/* -+ * TP-LINK TL-WR1043ND board support -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ar9xxx-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-usb.h" -+ -+#define TL_WR1043ND_GPIO_LED_USB 1 -+#define TL_WR1043ND_GPIO_LED_SYSTEM 2 -+#define TL_WR1043ND_GPIO_LED_QSS 5 -+#define TL_WR1043ND_GPIO_LED_WLAN 9 -+ -+#define TL_WR1043ND_GPIO_BTN_RESET 3 -+#define TL_WR1043ND_GPIO_BTN_QSS 7 -+ -+#define TL_WR1043ND_GPIO_RTL8366_SDA 18 -+#define TL_WR1043ND_GPIO_RTL8366_SCK 19 -+ -+#define TL_WR1043ND_KEYS_POLL_INTERVAL 20 /* msecs */ -+#define TL_WR1043ND_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR1043ND_KEYS_POLL_INTERVAL) -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition tl_wr1043nd_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "kernel", -+ .offset = 0x020000, -+ .size = 0x140000, -+ }, { -+ .name = "rootfs", -+ .offset = 0x160000, -+ .size = 0x690000, -+ }, { -+ .name = "art", -+ .offset = 0x7f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "firmware", -+ .offset = 0x020000, -+ .size = 0x7d0000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data tl_wr1043nd_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = tl_wr1043nd_partitions, -+ .nr_parts = ARRAY_SIZE(tl_wr1043nd_partitions), -+#endif -+}; -+ -+static struct gpio_led tl_wr1043nd_leds_gpio[] __initdata = { -+ { -+ .name = "tl-wr1043nd:green:usb", -+ .gpio = TL_WR1043ND_GPIO_LED_USB, -+ .active_low = 1, -+ }, { -+ .name = "tl-wr1043nd:green:system", -+ .gpio = TL_WR1043ND_GPIO_LED_SYSTEM, -+ .active_low = 1, -+ }, { -+ .name = "tl-wr1043nd:green:qss", -+ .gpio = TL_WR1043ND_GPIO_LED_QSS, -+ .active_low = 0, -+ }, { -+ .name = "tl-wr1043nd:green:wlan", -+ .gpio = TL_WR1043ND_GPIO_LED_WLAN, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_keys_button tl_wr1043nd_gpio_keys[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .debounce_interval = TL_WR1043ND_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = TL_WR1043ND_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "qss", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .debounce_interval = TL_WR1043ND_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = TL_WR1043ND_GPIO_BTN_QSS, -+ .active_low = 1, -+ } -+}; -+ -+static struct rtl8366_platform_data tl_wr1043nd_rtl8366rb_data = { -+ .gpio_sda = TL_WR1043ND_GPIO_RTL8366_SDA, -+ .gpio_sck = TL_WR1043ND_GPIO_RTL8366_SCK, -+}; -+ -+static struct platform_device tl_wr1043nd_rtl8366rb_device = { -+ .name = RTL8366RB_DRIVER_NAME, -+ .id = -1, -+ .dev = { -+ .platform_data = &tl_wr1043nd_rtl8366rb_data, -+ } -+}; -+ -+static void __init tl_wr1043nd_setup(void) -+{ -+ u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ -+ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac, 0); -+ ar71xx_eth0_data.mii_bus_dev = &tl_wr1043nd_rtl8366rb_device.dev; -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth0_data.speed = SPEED_1000; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ ar71xx_eth0_pll_data.pll_1000 = 0x1a000000; -+ -+ ar71xx_add_device_eth(0); -+ -+ ar71xx_add_device_usb(); -+ -+ ar71xx_add_device_m25p80(&tl_wr1043nd_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(tl_wr1043nd_leds_gpio), -+ tl_wr1043nd_leds_gpio); -+ -+ platform_device_register(&tl_wr1043nd_rtl8366rb_device); -+ -+ ar71xx_register_gpio_keys_polled(-1, TL_WR1043ND_KEYS_POLL_INTERVAL, -+ ARRAY_SIZE(tl_wr1043nd_gpio_keys), -+ tl_wr1043nd_gpio_keys); -+ -+ ar9xxx_add_device_wmac(eeprom, mac); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_TL_WR1043ND, "TL-WR1043ND", "TP-LINK TL-WR1043ND", -+ tl_wr1043nd_setup); -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-tl-wr741nd.c linux-2.6.39/arch/mips/ar71xx/mach-tl-wr741nd.c ---- linux-2.6.39.orig/arch/mips/ar71xx/mach-tl-wr741nd.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/mach-tl-wr741nd.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,135 @@ -+/* -+ * TP-LINK TL-WR741ND board support -+ * -+ * Copyright (C) 2009-2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ap91-pci.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+ -+#define TL_WR741ND_GPIO_LED_QSS 0 -+#define TL_WR741ND_GPIO_LED_SYSTEM 1 -+ -+#define TL_WR741ND_GPIO_BTN_RESET 11 -+#define TL_WR741ND_GPIO_BTN_QSS 12 -+ -+#define TL_WR741ND_KEYS_POLL_INTERVAL 20 /* msecs */ -+#define TL_WR741ND_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR741ND_KEYS_POLL_INTERVAL) -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition tl_wr741nd_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "kernel", -+ .offset = 0x020000, -+ .size = 0x140000, -+ }, { -+ .name = "rootfs", -+ .offset = 0x160000, -+ .size = 0x290000, -+ }, { -+ .name = "art", -+ .offset = 0x3f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "firmware", -+ .offset = 0x020000, -+ .size = 0x3d0000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data tl_wr741nd_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = tl_wr741nd_partitions, -+ .nr_parts = ARRAY_SIZE(tl_wr741nd_partitions), -+#endif -+}; -+ -+static struct gpio_led tl_wr741nd_leds_gpio[] __initdata = { -+ { -+ .name = "tl-wr741nd:green:system", -+ .gpio = TL_WR741ND_GPIO_LED_SYSTEM, -+ .active_low = 1, -+ }, { -+ .name = "tl-wr741nd:green:qss", -+ .gpio = TL_WR741ND_GPIO_LED_QSS, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_keys_button tl_wr741nd_gpio_keys[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .debounce_interval = TL_WR741ND_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = TL_WR741ND_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "qss", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .debounce_interval = TL_WR741ND_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = TL_WR741ND_GPIO_BTN_QSS, -+ .active_low = 1, -+ } -+}; -+ -+static void __init tl_wr741nd_setup(void) -+{ -+ u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); -+ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); -+ -+ ar71xx_add_device_m25p80(&tl_wr741nd_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(tl_wr741nd_leds_gpio), -+ tl_wr741nd_leds_gpio); -+ -+ ar71xx_register_gpio_keys_polled(-1, TL_WR741ND_KEYS_POLL_INTERVAL, -+ ARRAY_SIZE(tl_wr741nd_gpio_keys), -+ tl_wr741nd_gpio_keys); -+ -+ ar71xx_eth1_data.has_ar7240_switch = 1; -+ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac, 0); -+ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, mac, 1); -+ -+ /* WAN port */ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ ar71xx_eth0_data.phy_mask = BIT(4); -+ -+ /* LAN ports */ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.speed = SPEED_1000; -+ ar71xx_eth1_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_add_device_mdio(0x0); -+ ar71xx_add_device_eth(1); -+ ar71xx_add_device_eth(0); -+ -+ ap91_pci_setup_wmac_led_pin(1); -+ -+ ap91_pci_init(ee, mac); -+} -+MIPS_MACHINE(AR71XX_MACH_TL_WR741ND, "TL-WR741ND", "TP-LINK TL-WR741ND", -+ tl_wr741nd_setup); -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-tl-wr841n.c linux-2.6.39/arch/mips/ar71xx/mach-tl-wr841n.c ---- linux-2.6.39.orig/arch/mips/ar71xx/mach-tl-wr841n.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/mach-tl-wr841n.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,144 @@ -+/* -+ * TP-LINK TL-WR841N board support -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-dsa.h" -+#include "dev-m25p80.h" -+#include "dev-gpio-buttons.h" -+#include "dev-pb42-pci.h" -+#include "dev-leds-gpio.h" -+ -+#define TL_WR841ND_V1_GPIO_LED_SYSTEM 2 -+#define TL_WR841ND_V1_GPIO_LED_QSS_GREEN 4 -+#define TL_WR841ND_V1_GPIO_LED_QSS_RED 5 -+ -+#define TL_WR841ND_V1_GPIO_BTN_RESET 3 -+#define TL_WR841ND_V1_GPIO_BTN_QSS 7 -+ -+#define TL_WR841ND_V1_KEYS_POLL_INTERVAL 20 /* msecs */ -+#define TL_WR841ND_V1_KEYS_DEBOUNCE_INTERVAL \ -+ (3 * TL_WR841ND_V1_KEYS_POLL_INTERVAL) -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition tl_wr841n_v1_partitions[] = { -+ { -+ .name = "redboot", -+ .offset = 0, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "kernel", -+ .offset = 0x020000, -+ .size = 0x140000, -+ }, { -+ .name = "rootfs", -+ .offset = 0x160000, -+ .size = 0x280000, -+ }, { -+ .name = "config", -+ .offset = 0x3e0000, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "firmware", -+ .offset = 0x020000, -+ .size = 0x3c0000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data tl_wr841n_v1_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = tl_wr841n_v1_partitions, -+ .nr_parts = ARRAY_SIZE(tl_wr841n_v1_partitions), -+#endif -+}; -+ -+static struct gpio_led tl_wr841n_v1_leds_gpio[] __initdata = { -+ { -+ .name = "tl-wr841n:green:system", -+ .gpio = TL_WR841ND_V1_GPIO_LED_SYSTEM, -+ .active_low = 1, -+ }, { -+ .name = "tl-wr841n:red:qss", -+ .gpio = TL_WR841ND_V1_GPIO_LED_QSS_RED, -+ }, { -+ .name = "tl-wr841n:green:qss", -+ .gpio = TL_WR841ND_V1_GPIO_LED_QSS_GREEN, -+ } -+}; -+ -+static struct gpio_keys_button tl_wr841n_v1_gpio_keys[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .debounce_interval = TL_WR841ND_V1_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = TL_WR841ND_V1_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "qss", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .debounce_interval = TL_WR841ND_V1_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = TL_WR841ND_V1_GPIO_BTN_QSS, -+ .active_low = 1, -+ } -+}; -+ -+static struct dsa_chip_data tl_wr841n_v1_dsa_chip = { -+ .port_names[0] = "wan", -+ .port_names[1] = "lan1", -+ .port_names[2] = "lan2", -+ .port_names[3] = "lan3", -+ .port_names[4] = "lan4", -+ .port_names[5] = "cpu", -+}; -+ -+static struct dsa_platform_data tl_wr841n_v1_dsa_data = { -+ .nr_chips = 1, -+ .chip = &tl_wr841n_v1_dsa_chip, -+}; -+ -+static void __init tl_wr841n_v1_setup(void) -+{ -+ u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); -+ -+ ar71xx_add_device_mdio(0x0); -+ -+ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac, 0); -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_add_device_eth(0); -+ -+ ar71xx_add_device_dsa(0, &tl_wr841n_v1_dsa_data); -+ -+ ar71xx_add_device_m25p80(&tl_wr841n_v1_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(tl_wr841n_v1_leds_gpio), -+ tl_wr841n_v1_leds_gpio); -+ -+ ar71xx_register_gpio_keys_polled(-1, TL_WR841ND_V1_KEYS_POLL_INTERVAL, -+ ARRAY_SIZE(tl_wr841n_v1_gpio_keys), -+ tl_wr841n_v1_gpio_keys); -+ -+ pb42_pci_init(); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_TL_WR841N_V1, "TL-WR841N-v1.5", "TP-LINK TL-WR841N v1", -+ tl_wr841n_v1_setup); -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-tl-wr941nd.c linux-2.6.39/arch/mips/ar71xx/mach-tl-wr941nd.c ---- linux-2.6.39.orig/arch/mips/ar71xx/mach-tl-wr941nd.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/mach-tl-wr941nd.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,147 @@ -+/* -+ * TP-LINK TL-WR941ND board support -+ * -+ * Copyright (C) 2009-2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-dsa.h" -+#include "dev-m25p80.h" -+#include "dev-ar9xxx-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+ -+#define TL_WR941ND_GPIO_LED_SYSTEM 2 -+#define TL_WR941ND_GPIO_LED_QSS_RED 4 -+#define TL_WR941ND_GPIO_LED_QSS_GREEN 5 -+#define TL_WR941ND_GPIO_LED_WLAN 9 -+ -+#define TL_WR941ND_GPIO_BTN_RESET 3 -+#define TL_WR941ND_GPIO_BTN_QSS 7 -+ -+#define TL_WR941ND_KEYS_POLL_INTERVAL 20 /* msecs */ -+#define TL_WR941ND_KEYS_DEBOUNCE_INTERVAL (3 * TL_WR941ND_KEYS_POLL_INTERVAL) -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition tl_wr941nd_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "kernel", -+ .offset = 0x020000, -+ .size = 0x140000, -+ }, { -+ .name = "rootfs", -+ .offset = 0x160000, -+ .size = 0x290000, -+ }, { -+ .name = "art", -+ .offset = 0x3f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "firmware", -+ .offset = 0x020000, -+ .size = 0x3d0000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data tl_wr941nd_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = tl_wr941nd_partitions, -+ .nr_parts = ARRAY_SIZE(tl_wr941nd_partitions), -+#endif -+}; -+ -+static struct gpio_led tl_wr941nd_leds_gpio[] __initdata = { -+ { -+ .name = "tl-wr941nd:green:system", -+ .gpio = TL_WR941ND_GPIO_LED_SYSTEM, -+ .active_low = 1, -+ }, { -+ .name = "tl-wr941nd:red:qss", -+ .gpio = TL_WR941ND_GPIO_LED_QSS_RED, -+ }, { -+ .name = "tl-wr941nd:green:qss", -+ .gpio = TL_WR941ND_GPIO_LED_QSS_GREEN, -+ }, { -+ .name = "tl-wr941nd:green:wlan", -+ .gpio = TL_WR941ND_GPIO_LED_WLAN, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_keys_button tl_wr941nd_gpio_keys[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .debounce_interval = TL_WR941ND_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = TL_WR941ND_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "qss", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .debounce_interval = TL_WR941ND_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = TL_WR941ND_GPIO_BTN_QSS, -+ .active_low = 1, -+ } -+}; -+ -+static struct dsa_chip_data tl_wr941nd_dsa_chip = { -+ .port_names[0] = "wan", -+ .port_names[1] = "lan1", -+ .port_names[2] = "lan2", -+ .port_names[3] = "lan3", -+ .port_names[4] = "lan4", -+ .port_names[5] = "cpu", -+}; -+ -+static struct dsa_platform_data tl_wr941nd_dsa_data = { -+ .nr_chips = 1, -+ .chip = &tl_wr941nd_dsa_chip, -+}; -+ -+static void __init tl_wr941nd_setup(void) -+{ -+ u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ -+ ar71xx_add_device_mdio(0x0); -+ -+ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac, 0); -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_dsa(0, &tl_wr941nd_dsa_data); -+ -+ ar71xx_add_device_m25p80(&tl_wr941nd_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(tl_wr941nd_leds_gpio), -+ tl_wr941nd_leds_gpio); -+ -+ ar71xx_register_gpio_keys_polled(-1, TL_WR941ND_KEYS_POLL_INTERVAL, -+ ARRAY_SIZE(tl_wr941nd_gpio_keys), -+ tl_wr941nd_gpio_keys); -+ ar9xxx_add_device_wmac(eeprom, mac); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_TL_WR941ND, "TL-WR941ND", "TP-LINK TL-WR941ND", -+ tl_wr941nd_setup); -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-ubnt.c linux-2.6.39/arch/mips/ar71xx/mach-ubnt.c ---- linux-2.6.39.orig/arch/mips/ar71xx/mach-ubnt.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/mach-ubnt.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,333 @@ -+/* -+ * Ubiquiti RouterStation support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * Copyright (C) 2008 Ubiquiti -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ap91-pci.h" -+#include "dev-gpio-buttons.h" -+#include "dev-pb42-pci.h" -+#include "dev-leds-gpio.h" -+#include "dev-usb.h" -+ -+#define UBNT_RS_GPIO_LED_RF 2 -+#define UBNT_RS_GPIO_SW4 8 -+ -+#define UBNT_LS_SR71_GPIO_LED_D25 0 -+#define UBNT_LS_SR71_GPIO_LED_D26 1 -+#define UBNT_LS_SR71_GPIO_LED_D24 2 -+#define UBNT_LS_SR71_GPIO_LED_D23 4 -+#define UBNT_LS_SR71_GPIO_LED_D22 5 -+#define UBNT_LS_SR71_GPIO_LED_D27 6 -+#define UBNT_LS_SR71_GPIO_LED_D28 7 -+ -+#define UBNT_M_GPIO_LED_L1 0 -+#define UBNT_M_GPIO_LED_L2 1 -+#define UBNT_M_GPIO_LED_L3 11 -+#define UBNT_M_GPIO_LED_L4 7 -+#define UBNT_M_GPIO_BTN_RESET 12 -+ -+#define UBNT_KEYS_POLL_INTERVAL 20 /* msecs */ -+#define UBNT_KEYS_DEBOUNCE_INTERVAL (3 * UBNT_KEYS_POLL_INTERVAL) -+ -+static struct gpio_led ubnt_rs_leds_gpio[] __initdata = { -+ { -+ .name = "ubnt:green:rf", -+ .gpio = UBNT_RS_GPIO_LED_RF, -+ .active_low = 0, -+ } -+}; -+ -+static struct gpio_led ubnt_ls_sr71_leds_gpio[] __initdata = { -+ { -+ .name = "ubnt:green:d22", -+ .gpio = UBNT_LS_SR71_GPIO_LED_D22, -+ .active_low = 0, -+ }, { -+ .name = "ubnt:green:d23", -+ .gpio = UBNT_LS_SR71_GPIO_LED_D23, -+ .active_low = 0, -+ }, { -+ .name = "ubnt:green:d24", -+ .gpio = UBNT_LS_SR71_GPIO_LED_D24, -+ .active_low = 0, -+ }, { -+ .name = "ubnt:red:d25", -+ .gpio = UBNT_LS_SR71_GPIO_LED_D25, -+ .active_low = 0, -+ }, { -+ .name = "ubnt:red:d26", -+ .gpio = UBNT_LS_SR71_GPIO_LED_D26, -+ .active_low = 0, -+ }, { -+ .name = "ubnt:green:d27", -+ .gpio = UBNT_LS_SR71_GPIO_LED_D27, -+ .active_low = 0, -+ }, { -+ .name = "ubnt:green:d28", -+ .gpio = UBNT_LS_SR71_GPIO_LED_D28, -+ .active_low = 0, -+ } -+}; -+ -+static struct gpio_led ubnt_m_leds_gpio[] __initdata = { -+ { -+ .name = "ubnt:red:link1", -+ .gpio = UBNT_M_GPIO_LED_L1, -+ .active_low = 0, -+ }, { -+ .name = "ubnt:orange:link2", -+ .gpio = UBNT_M_GPIO_LED_L2, -+ .active_low = 0, -+ }, { -+ .name = "ubnt:green:link3", -+ .gpio = UBNT_M_GPIO_LED_L3, -+ .active_low = 0, -+ }, { -+ .name = "ubnt:green:link4", -+ .gpio = UBNT_M_GPIO_LED_L4, -+ .active_low = 0, -+ } -+}; -+ -+static struct gpio_keys_button ubnt_gpio_keys[] __initdata = { -+ { -+ .desc = "sw4", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .debounce_interval = UBNT_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = UBNT_RS_GPIO_SW4, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_keys_button ubnt_m_gpio_keys[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .debounce_interval = UBNT_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = UBNT_M_GPIO_BTN_RESET, -+ .active_low = 1, -+ } -+}; -+ -+static void __init ubnt_generic_setup(void) -+{ -+ ar71xx_add_device_m25p80(NULL); -+ -+ ar71xx_register_gpio_keys_polled(-1, UBNT_KEYS_POLL_INTERVAL, -+ ARRAY_SIZE(ubnt_gpio_keys), -+ ubnt_gpio_keys); -+ -+ pb42_pci_init(); -+} -+ -+/* -+ * There is Secondary MAC address duplicate problem with some UBNT HW batches. -+ * Do not increase Secondary MAC address by 1 but do workaround -+ * with 'Locally Administrated' bit. -+ */ -+static void __init ubnt_init_secondary_mac(unsigned char *mac_base) -+{ -+ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, mac_base, 0); -+ ar71xx_eth1_data.mac_addr[0] |= 0x02; -+} -+ -+#define UBNT_RS_WAN_PHYMASK BIT(20) -+#define UBNT_RS_LAN_PHYMASK (BIT(16) | BIT(17) | BIT(18) | BIT(19)) -+ -+static void __init ubnt_rs_setup(void) -+{ -+ ubnt_generic_setup(); -+ -+ ar71xx_add_device_mdio(~(UBNT_RS_WAN_PHYMASK | UBNT_RS_LAN_PHYMASK)); -+ -+ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, ar71xx_mac_base, 0); -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; -+ ar71xx_eth0_data.phy_mask = UBNT_RS_WAN_PHYMASK; -+ -+ ubnt_init_secondary_mac(ar71xx_mac_base); -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.speed = SPEED_100; -+ ar71xx_eth1_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_usb(); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ubnt_rs_leds_gpio), -+ ubnt_rs_leds_gpio); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_UBNT_RS, "UBNT-RS", "Ubiquiti RouterStation", -+ ubnt_rs_setup); -+ -+#define UBNT_RSPRO_WAN_PHYMASK BIT(4) -+#define UBNT_RSPRO_LAN_PHYMASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) -+ -+static void __init ubnt_rspro_setup(void) -+{ -+ ubnt_generic_setup(); -+ -+ ar71xx_add_device_mdio(~(UBNT_RSPRO_WAN_PHYMASK | -+ UBNT_RSPRO_LAN_PHYMASK)); -+ -+ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, ar71xx_mac_base, 0); -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth0_data.phy_mask = UBNT_RSPRO_WAN_PHYMASK; -+ -+ ubnt_init_secondary_mac(ar71xx_mac_base); -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth1_data.phy_mask = UBNT_RSPRO_LAN_PHYMASK; -+ ar71xx_eth1_data.speed = SPEED_1000; -+ ar71xx_eth1_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_usb(); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ubnt_rs_leds_gpio), -+ ubnt_rs_leds_gpio); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_UBNT_RSPRO, "UBNT-RSPRO", "Ubiquiti RouterStation Pro", -+ ubnt_rspro_setup); -+ -+static void __init ubnt_lsx_setup(void) -+{ -+ ubnt_generic_setup(); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_UBNT_LSX, "UBNT-LSX", "Ubiquiti LSX", ubnt_lsx_setup); -+ -+#define UBNT_LSSR71_PHY_MASK BIT(1) -+ -+static void __init ubnt_lssr71_setup(void) -+{ -+ ubnt_generic_setup(); -+ -+ ar71xx_add_device_mdio(~UBNT_LSSR71_PHY_MASK); -+ -+ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, ar71xx_mac_base, 0); -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; -+ ar71xx_eth0_data.phy_mask = UBNT_LSSR71_PHY_MASK; -+ -+ ar71xx_add_device_eth(0); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ubnt_ls_sr71_leds_gpio), -+ ubnt_ls_sr71_leds_gpio); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_UBNT_LSSR71, "UBNT-LS-SR71", "Ubiquiti LS-SR71", -+ ubnt_lssr71_setup); -+ -+#define UBNT_M_WAN_PHYMASK BIT(4) -+ -+static void __init ubnt_m_setup(void) -+{ -+ u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000); -+ u8 *mac2 = (u8 *) KSEG1ADDR(0x1fff0000 + ETH_ALEN); -+ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); -+ -+ ar71xx_add_device_m25p80(NULL); -+ -+ ar71xx_add_device_mdio(~UBNT_M_WAN_PHYMASK); -+ -+ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac1, 0); -+ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, mac2, 0); -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ ar71xx_eth0_data.phy_mask = UBNT_M_WAN_PHYMASK; -+ -+ ar71xx_add_device_eth(0); -+ -+ ap91_pci_init(ee, NULL); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ubnt_m_leds_gpio), -+ ubnt_m_leds_gpio); -+ -+ ar71xx_register_gpio_keys_polled(-1, UBNT_KEYS_POLL_INTERVAL, -+ ARRAY_SIZE(ubnt_m_gpio_keys), -+ ubnt_m_gpio_keys); -+} -+ -+static void __init ubnt_rocket_m_setup(void) -+{ -+ ubnt_m_setup(); -+ ar71xx_add_device_usb(); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_UBNT_BULLET_M, "UBNT-BM", "Ubiquiti Bullet M", -+ ubnt_m_setup); -+MIPS_MACHINE(AR71XX_MACH_UBNT_ROCKET_M, "UBNT-RM", "Ubiquiti Rocket M", -+ ubnt_rocket_m_setup); -+ -+/* TODO detect the second ethernet port and use one -+ init function for all Ubiquiti MIMO series products */ -+static void __init ubnt_nano_m_setup(void) -+{ -+ ubnt_m_setup(); -+ -+ ar71xx_eth1_data.has_ar7240_switch = 1; -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.speed = SPEED_1000; -+ ar71xx_eth1_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_add_device_eth(1); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_UBNT_NANO_M, "UBNT-NM", "Ubiquiti Nanostation M", -+ ubnt_nano_m_setup); -+ -+static struct gpio_led ubnt_unifi_leds_gpio[] __initdata = { -+ { -+ .name = "ubnt:orange:dome", -+ .gpio = 1, -+ .active_low = 0, -+ }, { -+ .name = "ubnt:green:dome", -+ .gpio = 0, -+ .active_low = 0, -+ } -+}; -+ -+static void __init ubnt_unifi_setup(void) -+{ -+ u8 *mac = (u8 *) KSEG1ADDR(0x1fff0000); -+ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); -+ -+ ar71xx_add_device_m25p80(NULL); -+ -+ ar71xx_add_device_mdio(~UBNT_M_WAN_PHYMASK); -+ -+ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac, 0); -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ ar71xx_eth0_data.phy_mask = UBNT_M_WAN_PHYMASK; -+ -+ ar71xx_add_device_eth(0); -+ -+ ap91_pci_init(ee, NULL); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ubnt_unifi_leds_gpio), -+ ubnt_unifi_leds_gpio); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_UBNT_UNIFI, "UBNT-XM", "Ubiquiti UniFi", -+ ubnt_unifi_setup); -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-wndr3700.c linux-2.6.39/arch/mips/ar71xx/mach-wndr3700.c ---- linux-2.6.39.orig/arch/mips/ar71xx/mach-wndr3700.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/mach-wndr3700.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,290 @@ -+/* -+ * Netgear WNDR3700 board support -+ * -+ * Copyright (C) 2009 Marco Porsch -+ * Copyright (C) 2009-2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ap94-pci.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-usb.h" -+ -+#define WNDR3700_GPIO_LED_WPS_ORANGE 0 -+#define WNDR3700_GPIO_LED_POWER_ORANGE 1 -+#define WNDR3700_GPIO_LED_POWER_GREEN 2 -+#define WNDR3700_GPIO_LED_WPS_GREEN 4 -+#define WNDR3700_GPIO_LED_WAN_GREEN 6 -+ -+#define WNDR3700_GPIO_BTN_WPS 3 -+#define WNDR3700_GPIO_BTN_RESET 8 -+#define WNDR3700_GPIO_BTN_WIFI 11 -+ -+#define WNDR3700_GPIO_RTL8366_SDA 5 -+#define WNDR3700_GPIO_RTL8366_SCK 7 -+ -+#define WNDR3700_KEYS_POLL_INTERVAL 20 /* msecs */ -+#define WNDR3700_KEYS_DEBOUNCE_INTERVAL (3 * WNDR3700_KEYS_POLL_INTERVAL) -+ -+#define WNDR3700_ETH0_MAC_OFFSET 0 -+#define WNDR3700_ETH1_MAC_OFFSET 0x6 -+ -+#define WNDR3700_WMAC0_MAC_OFFSET 0 -+#define WNDR3700_WMAC1_MAC_OFFSET 0xc -+#define WNDR3700_CALDATA0_OFFSET 0x1000 -+#define WNDR3700_CALDATA1_OFFSET 0x5000 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition wndr3700_partitions[] = { -+ { -+ .name = "uboot", -+ .offset = 0, -+ .size = 0x050000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "env", -+ .offset = 0x050000, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "rootfs", -+ .offset = 0x070000, -+ .size = 0x720000, -+ }, { -+ .name = "config", -+ .offset = 0x790000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "config_bak", -+ .offset = 0x7a0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "pot", -+ .offset = 0x7b0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "traffic_meter", -+ .offset = 0x7c0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "language", -+ .offset = 0x7d0000, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "caldata", -+ .offset = 0x7f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } -+}; -+ -+static struct mtd_partition wndr3700v2_partitions[] = { -+ { -+ .name = "uboot", -+ .offset = 0, -+ .size = 0x050000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "env", -+ .offset = 0x050000, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "rootfs", -+ .offset = 0x070000, -+ .size = 0xe40000, -+ }, { -+ .name = "config", -+ .offset = 0xeb0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "config_bak", -+ .offset = 0xec0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "pot", -+ .offset = 0xed0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "traffic_meter", -+ .offset = 0xee0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "language", -+ .offset = 0xef0000, -+ .size = 0x100000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "caldata", -+ .offset = 0xff0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } -+}; -+#define wndr3700_num_partitions ARRAY_SIZE(wndr3700_partitions) -+#define wndr3700v2_num_partitions ARRAY_SIZE(wndr3700v2_partitions) -+#else -+#define wndr3700_partitions NULL -+#define wndr3700_num_partitions 0 -+#define wndr3700v2_partitions NULL -+#define wndr3700v2_num_partitions 0 -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data wndr3700_flash_data; -+ -+static struct gpio_led wndr3700_leds_gpio[] __initdata = { -+ { -+ .name = "wndr3700:green:power", -+ .gpio = WNDR3700_GPIO_LED_POWER_GREEN, -+ .active_low = 1, -+ }, { -+ .name = "wndr3700:orange:power", -+ .gpio = WNDR3700_GPIO_LED_POWER_ORANGE, -+ .active_low = 1, -+ }, { -+ .name = "wndr3700:green:wps", -+ .gpio = WNDR3700_GPIO_LED_WPS_GREEN, -+ .active_low = 1, -+ }, { -+ .name = "wndr3700:orange:wps", -+ .gpio = WNDR3700_GPIO_LED_WPS_ORANGE, -+ .active_low = 1, -+ }, { -+ .name = "wndr3700:green:wan", -+ .gpio = WNDR3700_GPIO_LED_WAN_GREEN, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_keys_button wndr3700_gpio_keys[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .debounce_interval = WNDR3700_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = WNDR3700_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "wps", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .debounce_interval = WNDR3700_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = WNDR3700_GPIO_BTN_WPS, -+ .active_low = 1, -+ }, { -+ .desc = "wifi", -+ .type = EV_KEY, -+ .code = BTN_2, -+ .debounce_interval = WNDR3700_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = WNDR3700_GPIO_BTN_WIFI, -+ .active_low = 1, -+ } -+}; -+ -+static struct rtl8366_platform_data wndr3700_rtl8366s_data = { -+ .gpio_sda = WNDR3700_GPIO_RTL8366_SDA, -+ .gpio_sck = WNDR3700_GPIO_RTL8366_SCK, -+}; -+ -+static struct platform_device wndr3700_rtl8366s_device = { -+ .name = RTL8366S_DRIVER_NAME, -+ .id = -1, -+ .dev = { -+ .platform_data = &wndr3700_rtl8366s_data, -+ } -+}; -+ -+static void __init wndr3700_common_setup(void) -+{ -+ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); -+ -+ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, -+ art + WNDR3700_ETH0_MAC_OFFSET, 0); -+ ar71xx_eth0_pll_data.pll_1000 = 0x11110000; -+ ar71xx_eth0_data.mii_bus_dev = &wndr3700_rtl8366s_device.dev; -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth0_data.speed = SPEED_1000; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, -+ art + WNDR3700_ETH1_MAC_OFFSET, 0); -+ ar71xx_eth1_pll_data.pll_1000 = 0x11110000; -+ ar71xx_eth1_data.mii_bus_dev = &wndr3700_rtl8366s_device.dev; -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth1_data.phy_mask = 0x10; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_usb(); -+ -+ ar71xx_add_device_m25p80(&wndr3700_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(wndr3700_leds_gpio), -+ wndr3700_leds_gpio); -+ -+ ar71xx_register_gpio_keys_polled(-1, WNDR3700_KEYS_POLL_INTERVAL, -+ ARRAY_SIZE(wndr3700_gpio_keys), -+ wndr3700_gpio_keys); -+ -+ platform_device_register(&wndr3700_rtl8366s_device); -+ platform_device_register_simple("wndr3700-led-usb", -1, NULL, 0); -+ -+ ap94_pci_setup_wmac_led_pin(0, 5); -+ ap94_pci_setup_wmac_led_pin(1, 5); -+ -+ /* 2.4 GHz uses the first fixed antenna group (1, 0, 1, 0) */ -+ ap94_pci_setup_wmac_gpio(0, (0xf << 6), (0xa << 6)); -+ -+ /* 5 GHz uses the second fixed antenna group (0, 1, 1, 0) */ -+ ap94_pci_setup_wmac_gpio(1, (0xf << 6), (0x6 << 6)); -+ -+ ap94_pci_init(art + WNDR3700_CALDATA0_OFFSET, -+ art + WNDR3700_WMAC0_MAC_OFFSET, -+ art + WNDR3700_CALDATA1_OFFSET, -+ art + WNDR3700_WMAC1_MAC_OFFSET); -+} -+ -+static void __init wndr3700_setup(void) -+{ -+ wndr3700_flash_data.parts = wndr3700_partitions, -+ wndr3700_flash_data.nr_parts = wndr3700_num_partitions, -+ wndr3700_common_setup(); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_WNDR3700, "WNDR3700", "NETGEAR WNDR3700", -+ wndr3700_setup); -+ -+static void __init wndr3700v2_setup(void) -+{ -+ wndr3700_flash_data.parts = wndr3700v2_partitions, -+ wndr3700_flash_data.nr_parts = wndr3700v2_num_partitions, -+ wndr3700_common_setup(); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_WNDR3700V2, "WNDR3700v2", "NETGEAR WNDR3700v2", -+ wndr3700v2_setup); -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-wnr2000.c linux-2.6.39/arch/mips/ar71xx/mach-wnr2000.c ---- linux-2.6.39.orig/arch/mips/ar71xx/mach-wnr2000.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/mach-wnr2000.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,150 @@ -+/* -+ * NETGEAR WNR2000 board support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * Copyright (C) 2008-2009 Andy Boyett -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ar9xxx-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+ -+#define WNR2000_GPIO_LED_PWR_GREEN 14 -+#define WNR2000_GPIO_LED_PWR_AMBER 7 -+#define WNR2000_GPIO_LED_WPS 4 -+#define WNR2000_GPIO_LED_WLAN 6 -+#define WNR2000_GPIO_BTN_RESET 21 -+#define WNR2000_GPIO_BTN_WPS 8 -+ -+#define WNR2000_KEYS_POLL_INTERVAL 20 /* msecs */ -+#define WNR2000_KEYS_DEBOUNCE_INTERVAL (3 * WNR2000_KEYS_POLL_INTERVAL) -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition wnr2000_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x040000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "u-boot-env", -+ .offset = 0x040000, -+ .size = 0x010000, -+ }, { -+ .name = "rootfs", -+ .offset = 0x050000, -+ .size = 0x240000, -+ }, { -+ .name = "user-config", -+ .offset = 0x290000, -+ .size = 0x010000, -+ }, { -+ .name = "uImage", -+ .offset = 0x2a0000, -+ .size = 0x120000, -+ }, { -+ .name = "language_table", -+ .offset = 0x3c0000, -+ .size = 0x020000, -+ }, { -+ .name = "rootfs_checksum", -+ .offset = 0x3e0000, -+ .size = 0x010000, -+ }, { -+ .name = "art", -+ .offset = 0x3f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data wnr2000_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = wnr2000_partitions, -+ .nr_parts = ARRAY_SIZE(wnr2000_partitions), -+#endif -+}; -+ -+static struct gpio_led wnr2000_leds_gpio[] __initdata = { -+ { -+ .name = "wnr2000:green:power", -+ .gpio = WNR2000_GPIO_LED_PWR_GREEN, -+ .active_low = 1, -+ }, { -+ .name = "wnr2000:amber:power", -+ .gpio = WNR2000_GPIO_LED_PWR_AMBER, -+ .active_low = 1, -+ }, { -+ .name = "wnr2000:green:wps", -+ .gpio = WNR2000_GPIO_LED_WPS, -+ .active_low = 1, -+ }, { -+ .name = "wnr2000:blue:wlan", -+ .gpio = WNR2000_GPIO_LED_WLAN, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_keys_button wnr2000_gpio_keys[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .debounce_interval = WNR2000_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = WNR2000_GPIO_BTN_RESET, -+ }, { -+ .desc = "wps", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .debounce_interval = WNR2000_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = WNR2000_GPIO_BTN_WPS, -+ } -+}; -+ -+static void __init wnr2000_setup(void) -+{ -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ -+ ar71xx_add_device_mdio(0x0); -+ -+ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, eeprom, 0); -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ ar71xx_eth0_data.has_ar8216 = 1; -+ -+ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, eeprom, 1); -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.phy_mask = 0x10; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_m25p80(&wnr2000_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(wnr2000_leds_gpio), -+ wnr2000_leds_gpio); -+ -+ ar71xx_register_gpio_keys_polled(-1, WNR2000_KEYS_POLL_INTERVAL, -+ ARRAY_SIZE(wnr2000_gpio_keys), -+ wnr2000_gpio_keys); -+ -+ -+ ar9xxx_add_device_wmac(eeprom, NULL); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_WNR2000, "WNR2000", "NETGEAR WNR2000", wnr2000_setup); -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-wp543.c linux-2.6.39/arch/mips/ar71xx/mach-wp543.c ---- linux-2.6.39.orig/arch/mips/ar71xx/mach-wp543.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/mach-wp543.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,101 @@ -+/* -+ * Compex WP543/WPJ543 board support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-pb42-pci.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-usb.h" -+ -+#define WP543_GPIO_SW6 2 -+#define WP543_GPIO_LED_1 3 -+#define WP543_GPIO_LED_2 4 -+#define WP543_GPIO_LED_WLAN 5 -+#define WP543_GPIO_LED_CONN 6 -+#define WP543_GPIO_LED_DIAG 7 -+#define WP543_GPIO_SW4 8 -+ -+#define WP543_KEYS_POLL_INTERVAL 20 /* msecs */ -+#define WP543_KEYS_DEBOUNCE_INTERVAL (3 * WP543_KEYS_POLL_INTERVAL) -+ -+static struct gpio_led wp543_leds_gpio[] __initdata = { -+ { -+ .name = "wp543:green:led1", -+ .gpio = WP543_GPIO_LED_1, -+ .active_low = 1, -+ }, { -+ .name = "wp543:green:led2", -+ .gpio = WP543_GPIO_LED_2, -+ .active_low = 1, -+ }, { -+ .name = "wp543:green:wlan", -+ .gpio = WP543_GPIO_LED_WLAN, -+ .active_low = 1, -+ }, { -+ .name = "wp543:green:conn", -+ .gpio = WP543_GPIO_LED_CONN, -+ .active_low = 1, -+ }, { -+ .name = "wp543:green:diag", -+ .gpio = WP543_GPIO_LED_DIAG, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_keys_button wp543_gpio_keys[] __initdata = { -+ { -+ .desc = "sw6", -+ .type = EV_KEY, -+ .code = BTN_0, -+ .debounce_interval = WP543_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = WP543_GPIO_SW6, -+ }, { -+ .desc = "sw4", -+ .type = EV_KEY, -+ .code = BTN_1, -+ .debounce_interval = WP543_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = WP543_GPIO_SW4, -+ } -+}; -+ -+static void __init wp543_setup(void) -+{ -+ ar71xx_add_device_m25p80(NULL); -+ -+ ar71xx_add_device_mdio(0xfffffff7); -+ -+ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, ar71xx_mac_base, 0); -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; -+ ar71xx_eth0_data.phy_mask = 0x08; -+ ar71xx_eth0_data.reset_bit = RESET_MODULE_GE0_MAC | -+ RESET_MODULE_GE0_PHY; -+ ar71xx_add_device_eth(0); -+ -+ ar71xx_add_device_usb(); -+ -+ pb42_pci_init(); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(wp543_leds_gpio), -+ wp543_leds_gpio); -+ -+ ar71xx_register_gpio_keys_polled(-1, WP543_KEYS_POLL_INTERVAL, -+ ARRAY_SIZE(wp543_gpio_keys), -+ wp543_gpio_keys); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_WP543, "WP543", "Compex WP543", wp543_setup); -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-wrt160nl.c linux-2.6.39/arch/mips/ar71xx/mach-wrt160nl.c ---- linux-2.6.39.orig/arch/mips/ar71xx/mach-wrt160nl.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/mach-wrt160nl.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,161 @@ -+/* -+ * Linksys WRT160NL board support -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ar9xxx-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-usb.h" -+#include "nvram.h" -+ -+#define WRT160NL_GPIO_LED_POWER 14 -+#define WRT160NL_GPIO_LED_WPS_AMBER 9 -+#define WRT160NL_GPIO_LED_WPS_BLUE 8 -+#define WRT160NL_GPIO_LED_WLAN 6 -+ -+#define WRT160NL_GPIO_BTN_WPS 7 -+#define WRT160NL_GPIO_BTN_RESET 21 -+ -+#define WRT160NL_KEYS_POLL_INTERVAL 20 /* msecs */ -+#define WRT160NL_KEYS_DEBOUNCE_INTERVAL (3 * WRT160NL_KEYS_POLL_INTERVAL) -+ -+#define WRT160NL_NVRAM_ADDR 0x1f7e0000 -+#define WRT160NL_NVRAM_SIZE 0x10000 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition wrt160nl_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x040000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "kernel", -+ .offset = 0x040000, -+ .size = 0x0e0000, -+ }, { -+ .name = "filesytem", -+ .offset = 0x120000, -+ .size = 0x6c0000, -+ }, { -+ .name = "nvram", -+ .offset = 0x7e0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "ART", -+ .offset = 0x7f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "firmware", -+ .offset = 0x040000, -+ .size = 0x7a0000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data wrt160nl_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = wrt160nl_partitions, -+ .nr_parts = ARRAY_SIZE(wrt160nl_partitions), -+#endif -+}; -+ -+static struct gpio_led wrt160nl_leds_gpio[] __initdata = { -+ { -+ .name = "wrt160nl:blue:power", -+ .gpio = WRT160NL_GPIO_LED_POWER, -+ .active_low = 1, -+ .default_trigger = "default-on", -+ }, { -+ .name = "wrt160nl:amber:wps", -+ .gpio = WRT160NL_GPIO_LED_WPS_AMBER, -+ .active_low = 1, -+ }, { -+ .name = "wrt160nl:blue:wps", -+ .gpio = WRT160NL_GPIO_LED_WPS_BLUE, -+ .active_low = 1, -+ }, { -+ .name = "wrt160nl:blue:wlan", -+ .gpio = WRT160NL_GPIO_LED_WLAN, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_keys_button wrt160nl_gpio_keys[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .debounce_interval = WRT160NL_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = WRT160NL_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "wps", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .debounce_interval = WRT160NL_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = WRT160NL_GPIO_BTN_WPS, -+ .active_low = 1, -+ } -+}; -+ -+static void __init wrt160nl_setup(void) -+{ -+ const char *nvram = (char *) KSEG1ADDR(WRT160NL_NVRAM_ADDR); -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ u8 mac[6]; -+ -+ if (nvram_parse_mac_addr(nvram, WRT160NL_NVRAM_SIZE, -+ "lan_hwaddr=", mac) == 0) { -+ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac, 0); -+ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, mac, 1); -+ } -+ -+ ar71xx_add_device_mdio(0x0); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.phy_mask = 0x01; -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.phy_mask = 0x10; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_m25p80(&wrt160nl_flash_data); -+ -+ ar71xx_add_device_usb(); -+ -+ if (nvram_parse_mac_addr(nvram, WRT160NL_NVRAM_SIZE, -+ "wl0_hwaddr=", mac) == 0) -+ ar9xxx_add_device_wmac(eeprom, mac); -+ else -+ ar9xxx_add_device_wmac(eeprom, NULL); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(wrt160nl_leds_gpio), -+ wrt160nl_leds_gpio); -+ -+ ar71xx_register_gpio_keys_polled(-1, WRT160NL_KEYS_POLL_INTERVAL, -+ ARRAY_SIZE(wrt160nl_gpio_keys), -+ wrt160nl_gpio_keys); -+ -+} -+ -+MIPS_MACHINE(AR71XX_MACH_WRT160NL, "WRT160NL", "Linksys WRT160NL", -+ wrt160nl_setup); -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-wrt400n.c linux-2.6.39/arch/mips/ar71xx/mach-wrt400n.c ---- linux-2.6.39.orig/arch/mips/ar71xx/mach-wrt400n.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/mach-wrt400n.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,164 @@ -+/* -+ * Linksys WRT400N board support -+ * -+ * Copyright (C) 2009-2010 Gabor Juhos -+ * Copyright (C) 2009 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-ap94-pci.h" -+#include "dev-m25p80.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+ -+#define WRT400N_GPIO_LED_ORANGE 5 -+#define WRT400N_GPIO_LED_GREEN 4 -+#define WRT400N_GPIO_LED_POWER 1 -+#define WRT400N_GPIO_LED_WLAN 0 -+ -+#define WRT400N_GPIO_BTN_RESET 8 -+#define WRT400N_GPIO_BTN_WLSEC 3 -+ -+#define WRT400N_KEYS_POLL_INTERVAL 20 /* msecs */ -+#define WRT400N_KEYS_DEBOUNE_INTERVAL (3 * WRT400N_KEYS_POLL_INTERVAL) -+ -+#define WRT400N_MAC_ADDR_OFFSET 0x120c -+#define WRT400N_CALDATA0_OFFSET 0x1000 -+#define WRT400N_CALDATA1_OFFSET 0x5000 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition wrt400n_partitions[] = { -+ { -+ .name = "uboot", -+ .offset = 0, -+ .size = 0x030000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "env", -+ .offset = 0x030000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "linux", -+ .offset = 0x040000, -+ .size = 0x140000, -+ }, { -+ .name = "rootfs", -+ .offset = 0x180000, -+ .size = 0x630000, -+ }, { -+ .name = "nvram", -+ .offset = 0x7b0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "factory", -+ .offset = 0x7c0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "language", -+ .offset = 0x7d0000, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "caldata", -+ .offset = 0x7f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "firmware", -+ .offset = 0x040000, -+ .size = 0x770000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data wrt400n_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = wrt400n_partitions, -+ .nr_parts = ARRAY_SIZE(wrt400n_partitions), -+#endif -+}; -+ -+static struct gpio_led wrt400n_leds_gpio[] __initdata = { -+ { -+ .name = "wrt400n:green:status", -+ .gpio = WRT400N_GPIO_LED_GREEN, -+ .active_low = 1, -+ }, { -+ .name = "wrt400n:amber:aoss", -+ .gpio = WRT400N_GPIO_LED_ORANGE, -+ .active_low = 1, -+ }, { -+ .name = "wrt400n:green:wlan", -+ .gpio = WRT400N_GPIO_LED_WLAN, -+ .active_low = 1, -+ }, { -+ .name = "wrt400n:green:power", -+ .gpio = WRT400N_GPIO_LED_POWER, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_keys_button wrt400n_gpio_keys[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .debounce_interval = WRT400N_KEYS_DEBOUNE_INTERVAL, -+ .gpio = WRT400N_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "wlsec", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .debounce_interval = WRT400N_KEYS_DEBOUNE_INTERVAL, -+ .gpio = WRT400N_GPIO_BTN_WLSEC, -+ .active_low = 1, -+ } -+}; -+ -+static void __init wrt400n_setup(void) -+{ -+ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); -+ u8 *mac = art + WRT400N_MAC_ADDR_OFFSET; -+ -+ ar71xx_add_device_mdio(0x0); -+ -+ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac, 1); -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, mac, 2); -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.phy_mask = 0x10; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_m25p80(&wrt400n_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(wrt400n_leds_gpio), -+ wrt400n_leds_gpio); -+ -+ ar71xx_register_gpio_keys_polled(-1, WRT400N_KEYS_POLL_INTERVAL, -+ ARRAY_SIZE(wrt400n_gpio_keys), -+ wrt400n_gpio_keys); -+ -+ ap94_pci_init(art + WRT400N_CALDATA0_OFFSET, NULL, -+ art + WRT400N_CALDATA1_OFFSET, NULL); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_WRT400N, "WRT400N", "Linksys WRT400N", wrt400n_setup); -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-wzr-hp-ag300h.c linux-2.6.39/arch/mips/ar71xx/mach-wzr-hp-ag300h.c ---- linux-2.6.39.orig/arch/mips/ar71xx/mach-wzr-hp-ag300h.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/mach-wzr-hp-ag300h.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,231 @@ -+/* -+ * Buffalo WZR-HP-AG300H board support -+ * -+ * Copyright (C) 2011 Felix Fietkau -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-ap94-pci.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-m25p80.h" -+#include "dev-usb.h" -+ -+#define WZRHPAG300H_MAC_OFFSET 0x20c -+#define WZRHPAG300H_KEYS_POLL_INTERVAL 20 /* msecs */ -+#define WZRHPAG300H_KEYS_DEBOUNCE_INTERVAL (3 * WZRHPAG300H_KEYS_POLL_INTERVAL) -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition wzrhpag300h_flash_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x0040000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "u-boot-env", -+ .offset = 0x0040000, -+ .size = 0x0010000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "art", -+ .offset = 0x0050000, -+ .size = 0x0010000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "kernel", -+ .offset = 0x0060000, -+ .size = 0x0100000, -+ }, { -+ .name = "rootfs", -+ .offset = 0x0160000, -+ .size = 0x1e90000, -+ }, { -+ .name = "user_property", -+ .offset = 0x1ff0000, -+ .size = 0x0010000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "firmware", -+ .offset = 0x0060000, -+ .size = 0x1f90000, -+ } -+}; -+ -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct mtd_info *concat_devs[2] = { NULL, NULL }; -+static struct work_struct mtd_concat_work; -+ -+static void mtd_concat_add_work(struct work_struct *work) -+{ -+ struct mtd_info *mtd; -+ -+ mtd = mtd_concat_create(concat_devs, ARRAY_SIZE(concat_devs), "flash"); -+ -+#ifdef CONFIG_MTD_PARTITIONS -+ add_mtd_partitions(mtd, wzrhpag300h_flash_partitions, -+ ARRAY_SIZE(wzrhpag300h_flash_partitions)); -+#else -+ add_mtd_device(mtd); -+#endif -+} -+ -+static void mtd_concat_add(struct mtd_info *mtd) -+{ -+ static bool registered = false; -+ -+ if (registered) -+ return; -+ -+ if (!strcmp(mtd->name, "spi0.0")) -+ concat_devs[0] = mtd; -+ else if (!strcmp(mtd->name, "spi0.1")) -+ concat_devs[1] = mtd; -+ else -+ return; -+ -+ if (!concat_devs[0] || !concat_devs[1]) -+ return; -+ -+ registered = true; -+ INIT_WORK(&mtd_concat_work, mtd_concat_add_work); -+ schedule_work(&mtd_concat_work); -+} -+ -+static void mtd_concat_remove(struct mtd_info *mtd) -+{ -+} -+ -+static void add_mtd_concat_notifier(void) -+{ -+ static struct mtd_notifier not = { -+ .add = mtd_concat_add, -+ .remove = mtd_concat_remove, -+ }; -+ -+ register_mtd_user(¬); -+} -+ -+static struct gpio_led wzrhpag300h_leds_gpio[] __initdata = { -+ { -+ .name = "wzr-hp-ag300h:red:diag", -+ .gpio = 1, -+ .active_low = 1, -+ }, -+}; -+ -+ -+static struct gpio_keys_button wzrhpag300h_gpio_keys[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .debounce_interval = WZRHPAG300H_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = 11, -+ .active_low = 1, -+ }, { -+ .desc = "usb", -+ .type = EV_KEY, -+ .code = BTN_2, -+ .debounce_interval = WZRHPAG300H_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = 3, -+ .active_low = 1, -+ }, { -+ .desc = "aoss", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .debounce_interval = WZRHPAG300H_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = 5, -+ .active_low = 1, -+ }, { -+ .desc = "router_auto", -+ .type = EV_KEY, -+ .code = BTN_6, -+ .debounce_interval = WZRHPAG300H_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = 6, -+ .active_low = 1, -+ }, { -+ .desc = "router_off", -+ .type = EV_KEY, -+ .code = BTN_5, -+ .debounce_interval = WZRHPAG300H_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = 7, -+ .active_low = 1, -+ } -+}; -+ -+static struct spi_board_info ar71xx_spi_info[] = { -+ { -+ .bus_num = 0, -+ .chip_select = 0, -+ .max_speed_hz = 25000000, -+ .modalias = "m25p80", -+ }, -+ { -+ .bus_num = 0, -+ .chip_select = 1, -+ .max_speed_hz = 25000000, -+ .modalias = "m25p80", -+ } -+}; -+ -+static void __init wzrhpag300h_setup(void) -+{ -+ u8 *eeprom1 = (u8 *) KSEG1ADDR(0x1f051000); -+ u8 *eeprom2 = (u8 *) KSEG1ADDR(0x1f055000); -+ u8 *mac1 = eeprom1 + WZRHPAG300H_MAC_OFFSET; -+ u8 *mac2 = eeprom2 + WZRHPAG300H_MAC_OFFSET; -+ -+ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac1, 0); -+ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, mac2, 1); -+ -+ ar71xx_add_device_mdio(~(BIT(0) | BIT(4))); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth0_data.speed = SPEED_1000; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ ar71xx_eth0_data.phy_mask = BIT(0); -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth1_data.phy_mask = BIT(4); -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_usb(); -+ gpio_request(2, "usb"); -+ gpio_direction_output(2, 1); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(wzrhpag300h_leds_gpio), -+ wzrhpag300h_leds_gpio); -+ -+ ar71xx_register_gpio_keys_polled(-1, WZRHPAG300H_KEYS_POLL_INTERVAL, -+ ARRAY_SIZE(wzrhpag300h_gpio_keys), -+ wzrhpag300h_gpio_keys); -+ -+ ar71xx_add_device_spi(NULL, ar71xx_spi_info, -+ ARRAY_SIZE(ar71xx_spi_info)); -+ -+ add_mtd_concat_notifier(); -+ -+ ap94_pci_init(eeprom1, mac1, eeprom2, mac2); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_WZR_HP_AG300H, "WZR-HP-AG300H", -+ "Buffalo WZR-HP-AG300H", wzrhpag300h_setup); -+ -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-wzr-hp-g300nh.c linux-2.6.39/arch/mips/ar71xx/mach-wzr-hp-g300nh.c ---- linux-2.6.39.orig/arch/mips/ar71xx/mach-wzr-hp-g300nh.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/mach-wzr-hp-g300nh.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,292 @@ -+/* -+ * Buffalo WZR-HP-G300NH board support -+ * -+ * Copyright (C) 2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-ar9xxx-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-usb.h" -+ -+#define WZRHPG300NH_GPIO_LED_USB 0 -+#define WZRHPG300NH_GPIO_LED_DIAG 1 -+#define WZRHPG300NH_GPIO_LED_WIRELESS 6 -+#define WZRHPG300NH_GPIO_LED_SECURITY 17 -+#define WZRHPG300NH_GPIO_LED_ROUTER 18 -+ -+#define WZRHPG300NH_GPIO_RTL8366_SDA 19 -+#define WZRHPG300NH_GPIO_RTL8366_SCK 20 -+ -+#define WZRHPG300NH_GPIO_74HC153_S0 9 -+#define WZRHPG300NH_GPIO_74HC153_S1 11 -+#define WZRHPG300NH_GPIO_74HC153_1Y 12 -+#define WZRHPG300NH_GPIO_74HC153_2Y 14 -+ -+#define WZRHPG300NH_GPIO_EXP_BASE 32 -+#define WZRHPG300NH_GPIO_BTN_AOSS (WZRHPG300NH_GPIO_EXP_BASE + 0) -+#define WZRHPG300NH_GPIO_BTN_RESET (WZRHPG300NH_GPIO_EXP_BASE + 1) -+#define WZRHPG300NH_GPIO_BTN_ROUTER_ON (WZRHPG300NH_GPIO_EXP_BASE + 2) -+#define WZRHPG300NH_GPIO_BTN_QOS_ON (WZRHPG300NH_GPIO_EXP_BASE + 3) -+#define WZRHPG300NH_GPIO_BTN_USB (WZRHPG300NH_GPIO_EXP_BASE + 5) -+#define WZRHPG300NH_GPIO_BTN_ROUTER_AUTO (WZRHPG300NH_GPIO_EXP_BASE + 6) -+#define WZRHPG300NH_GPIO_BTN_QOS_OFF (WZRHPG300NH_GPIO_EXP_BASE + 7) -+ -+#define WZRHPG300NH_KEYS_POLL_INTERVAL 20 /* msecs */ -+#define WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL (3 * WZRHPG300NH_KEYS_POLL_INTERVAL) -+ -+#define WZRHPG300NH_MAC_OFFSET 0x20c -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition wzrhpg300nh_flash_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x0040000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "u-boot-env", -+ .offset = 0x0040000, -+ .size = 0x0020000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "kernel", -+ .offset = 0x0060000, -+ .size = 0x0100000, -+ }, { -+ .name = "rootfs", -+ .offset = 0x0160000, -+ .size = 0x1e60000, -+ }, { -+ .name = "user_property", -+ .offset = 0x1fc0000, -+ .size = 0x0020000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "art", -+ .offset = 0x1fe0000, -+ .size = 0x0020000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "firmware", -+ .offset = 0x0060000, -+ .size = 0x1f60000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct ar91xx_flash_platform_data wzrhpg300nh_flash_data = { -+ .width = 2, -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = wzrhpg300nh_flash_partitions, -+ .nr_parts = ARRAY_SIZE(wzrhpg300nh_flash_partitions), -+#endif -+}; -+ -+#define WZRHPG300NH_FLASH_BASE 0x1e000000 -+#define WZRHPG300NH_FLASH_SIZE (32 * 1024 * 1024) -+ -+static struct resource wzrhpg300nh_flash_resources[] = { -+ [0] = { -+ .start = WZRHPG300NH_FLASH_BASE, -+ .end = WZRHPG300NH_FLASH_BASE + WZRHPG300NH_FLASH_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+}; -+ -+static struct platform_device wzrhpg300nh_flash_device = { -+ .name = "ar91xx-flash", -+ .id = -1, -+ .resource = wzrhpg300nh_flash_resources, -+ .num_resources = ARRAY_SIZE(wzrhpg300nh_flash_resources), -+ .dev = { -+ .platform_data = &wzrhpg300nh_flash_data, -+ } -+}; -+ -+static struct gpio_led wzrhpg300nh_leds_gpio[] __initdata = { -+ { -+ .name = "wzr-hp-g300nh:orange:security", -+ .gpio = WZRHPG300NH_GPIO_LED_SECURITY, -+ .active_low = 1, -+ }, { -+ .name = "wzr-hp-g300nh:green:wireless", -+ .gpio = WZRHPG300NH_GPIO_LED_WIRELESS, -+ .active_low = 1, -+ }, { -+ .name = "wzr-hp-g300nh:green:router", -+ .gpio = WZRHPG300NH_GPIO_LED_ROUTER, -+ .active_low = 1, -+ }, { -+ .name = "wzr-hp-g300nh:red:diag", -+ .gpio = WZRHPG300NH_GPIO_LED_DIAG, -+ .active_low = 1, -+ }, { -+ .name = "wzr-hp-g300nh:blue:usb", -+ .gpio = WZRHPG300NH_GPIO_LED_USB, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_keys_button wzrhpg300nh_gpio_keys[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = WZRHPG300NH_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "aoss", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = WZRHPG300NH_GPIO_BTN_AOSS, -+ .active_low = 1, -+ }, { -+ .desc = "usb", -+ .type = EV_KEY, -+ .code = BTN_2, -+ .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = WZRHPG300NH_GPIO_BTN_USB, -+ .active_low = 1, -+ }, { -+ .desc = "qos_on", -+ .type = EV_KEY, -+ .code = BTN_3, -+ .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = WZRHPG300NH_GPIO_BTN_QOS_ON, -+ .active_low = 0, -+ }, { -+ .desc = "qos_off", -+ .type = EV_KEY, -+ .code = BTN_4, -+ .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = WZRHPG300NH_GPIO_BTN_QOS_OFF, -+ .active_low = 0, -+ }, { -+ .desc = "router_on", -+ .type = EV_KEY, -+ .code = BTN_5, -+ .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = WZRHPG300NH_GPIO_BTN_ROUTER_ON, -+ .active_low = 0, -+ }, { -+ .desc = "router_auto", -+ .type = EV_KEY, -+ .code = BTN_6, -+ .debounce_interval = WZRHPG300NH_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = WZRHPG300NH_GPIO_BTN_ROUTER_AUTO, -+ .active_low = 0, -+ } -+}; -+ -+static struct nxp_74hc153_platform_data wzrhpg300nh_74hc153_data = { -+ .gpio_base = WZRHPG300NH_GPIO_EXP_BASE, -+ .gpio_pin_s0 = WZRHPG300NH_GPIO_74HC153_S0, -+ .gpio_pin_s1 = WZRHPG300NH_GPIO_74HC153_S1, -+ .gpio_pin_1y = WZRHPG300NH_GPIO_74HC153_1Y, -+ .gpio_pin_2y = WZRHPG300NH_GPIO_74HC153_2Y, -+}; -+ -+static struct platform_device wzrhpg300nh_74hc153_device = { -+ .name = NXP_74HC153_DRIVER_NAME, -+ .id = -1, -+ .dev = { -+ .platform_data = &wzrhpg300nh_74hc153_data, -+ } -+}; -+ -+static struct rtl8366_platform_data wzrhpg300nh_rtl8366_data = { -+ .gpio_sda = WZRHPG300NH_GPIO_RTL8366_SDA, -+ .gpio_sck = WZRHPG300NH_GPIO_RTL8366_SCK, -+}; -+ -+static struct platform_device wzrhpg300nh_rtl8366s_device = { -+ .name = RTL8366S_DRIVER_NAME, -+ .id = -1, -+ .dev = { -+ .platform_data = &wzrhpg300nh_rtl8366_data, -+ } -+}; -+ -+static struct platform_device wzrhpg300nh_rtl8366rb_device = { -+ .name = RTL8366RB_DRIVER_NAME, -+ .id = -1, -+ .dev = { -+ .platform_data = &wzrhpg300nh_rtl8366_data, -+ } -+}; -+ -+static void __init wzrhpg300nh_setup(void) -+{ -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ u8 *mac = eeprom + WZRHPG300NH_MAC_OFFSET; -+ bool hasrtl8366rb = false; -+ -+ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac, 0); -+ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, mac, 1); -+ -+ if (rtl8366_smi_detect(&wzrhpg300nh_rtl8366_data) == RTL8366_TYPE_RB) -+ hasrtl8366rb = true; -+ -+ if (hasrtl8366rb) { -+ ar71xx_eth0_pll_data.pll_1000 = 0x1f000000; -+ ar71xx_eth0_data.mii_bus_dev = &wzrhpg300nh_rtl8366rb_device.dev; -+ ar71xx_eth1_pll_data.pll_1000 = 0x100; -+ ar71xx_eth1_data.mii_bus_dev = &wzrhpg300nh_rtl8366rb_device.dev; -+ } else { -+ ar71xx_eth0_pll_data.pll_1000 = 0x1e000100; -+ ar71xx_eth0_data.mii_bus_dev = &wzrhpg300nh_rtl8366s_device.dev; -+ ar71xx_eth1_pll_data.pll_1000 = 0x1e000100; -+ ar71xx_eth1_data.mii_bus_dev = &wzrhpg300nh_rtl8366s_device.dev; -+ } -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth0_data.speed = SPEED_1000; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth1_data.phy_mask = 0x10; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_usb(); -+ ar9xxx_add_device_wmac(eeprom, NULL); -+ -+ platform_device_register(&wzrhpg300nh_74hc153_device); -+ platform_device_register(&wzrhpg300nh_flash_device); -+ -+ if (hasrtl8366rb) -+ platform_device_register(&wzrhpg300nh_rtl8366rb_device); -+ else -+ platform_device_register(&wzrhpg300nh_rtl8366s_device); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(wzrhpg300nh_leds_gpio), -+ wzrhpg300nh_leds_gpio); -+ -+ ar71xx_register_gpio_keys_polled(-1, WZRHPG300NH_KEYS_POLL_INTERVAL, -+ ARRAY_SIZE(wzrhpg300nh_gpio_keys), -+ wzrhpg300nh_gpio_keys); -+ -+} -+ -+MIPS_MACHINE(AR71XX_MACH_WZR_HP_G300NH, "WZR-HP-G300NH", -+ "Buffalo WZR-HP-G300NH", wzrhpg300nh_setup); -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/mach-zcn-1523h.c linux-2.6.39/arch/mips/ar71xx/mach-zcn-1523h.c ---- linux-2.6.39.orig/arch/mips/ar71xx/mach-zcn-1523h.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/mach-zcn-1523h.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,214 @@ -+/* -+ * Zcomax ZCN-1523H-2-8/5-16 board support -+ * -+ * Copyright (C) 2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ap91-pci.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+ -+#define ZCN_1523H_GPIO_BTN_RESET 0 -+#define ZCN_1523H_GPIO_LED_INIT 11 -+#define ZCN_1523H_GPIO_LED_LAN1 17 -+ -+#define ZCN_1523H_2_GPIO_LED_WEAK 13 -+#define ZCN_1523H_2_GPIO_LED_MEDIUM 14 -+#define ZCN_1523H_2_GPIO_LED_STRONG 15 -+ -+#define ZCN_1523H_5_GPIO_LED_UNKNOWN 1 -+#define ZCN_1523H_5_GPIO_LED_LAN2 13 -+#define ZCN_1523H_5_GPIO_LED_WEAK 14 -+#define ZCN_1523H_5_GPIO_LED_MEDIUM 15 -+#define ZCN_1523H_5_GPIO_LED_STRONG 16 -+ -+#define ZCN_1523H_KEYS_POLL_INTERVAL 20 /* msecs */ -+#define ZCN_1523H_KEYS_DEBOUNCE_INTERVAL (3 * ZCN_1523H_KEYS_POLL_INTERVAL) -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition zcn_1523h_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x040000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "u-boot-env", -+ .offset = 0x040000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "rootfs", -+ .offset = 0x050000, -+ .size = 0x610000, -+ }, { -+ .name = "kernel", -+ .offset = 0x660000, -+ .size = 0x170000, -+ }, { -+ .name = "configure", -+ .offset = 0x7d0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "mfg", -+ .offset = 0x7e0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "eeprom", -+ .offset = 0x7f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "firmware", -+ .offset = 0x050000, -+ .size = 0x780000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data zcn_1523h_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = zcn_1523h_partitions, -+ .nr_parts = ARRAY_SIZE(zcn_1523h_partitions), -+#endif -+}; -+ -+static struct gpio_keys_button zcn_1523h_gpio_keys[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .debounce_interval = ZCN_1523H_KEYS_DEBOUNCE_INTERVAL, -+ .gpio = ZCN_1523H_GPIO_BTN_RESET, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_led zcn_1523h_leds_gpio[] __initdata = { -+ { -+ .name = "zcn-1523h:amber:init", -+ .gpio = ZCN_1523H_GPIO_LED_INIT, -+ .active_low = 1, -+ }, { -+ .name = "zcn-1523h:green:lan1", -+ .gpio = ZCN_1523H_GPIO_LED_LAN1, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_led zcn_1523h_2_leds_gpio[] __initdata = { -+ { -+ .name = "zcn-1523h:red:weak", -+ .gpio = ZCN_1523H_2_GPIO_LED_WEAK, -+ .active_low = 1, -+ }, { -+ .name = "zcn-1523h:amber:medium", -+ .gpio = ZCN_1523H_2_GPIO_LED_MEDIUM, -+ .active_low = 1, -+ }, { -+ .name = "zcn-1523h:green:strong", -+ .gpio = ZCN_1523H_2_GPIO_LED_STRONG, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_led zcn_1523h_5_leds_gpio[] __initdata = { -+ { -+ .name = "zcn-1523h:red:weak", -+ .gpio = ZCN_1523H_5_GPIO_LED_WEAK, -+ .active_low = 1, -+ }, { -+ .name = "zcn-1523h:amber:medium", -+ .gpio = ZCN_1523H_5_GPIO_LED_MEDIUM, -+ .active_low = 1, -+ }, { -+ .name = "zcn-1523h:green:strong", -+ .gpio = ZCN_1523H_5_GPIO_LED_STRONG, -+ .active_low = 1, -+ }, { -+ .name = "zcn-1523h:green:lan2", -+ .gpio = ZCN_1523H_5_GPIO_LED_LAN2, -+ .active_low = 1, -+ }, { -+ .name = "zcn-1523h:amber:unknown", -+ .gpio = ZCN_1523H_5_GPIO_LED_UNKNOWN, -+ } -+}; -+ -+static void __init zcn_1523h_generic_setup(void) -+{ -+ u8 *mac = (u8 *) KSEG1ADDR(0x1f7e0004); -+ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); -+ -+ ar71xx_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN | -+ AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN | -+ AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN | -+ AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN | -+ AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN); -+ -+ ar71xx_add_device_m25p80(&zcn_1523h_flash_data); -+ -+ ar71xx_add_device_leds_gpio(0, ARRAY_SIZE(zcn_1523h_leds_gpio), -+ zcn_1523h_leds_gpio); -+ -+ ar71xx_register_gpio_keys_polled(-1, ZCN_1523H_KEYS_POLL_INTERVAL, -+ ARRAY_SIZE(zcn_1523h_gpio_keys), -+ zcn_1523h_gpio_keys); -+ -+ ap91_pci_init(ee, mac); -+ -+ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac, 0); -+ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, mac, 1); -+ -+ /* LAN1 port */ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ -+ /* LAN2 port */ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.speed = SPEED_1000; -+ ar71xx_eth1_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_add_device_mdio(0x0); -+ ar71xx_add_device_eth(0); -+} -+ -+static void __init zcn_1523h_2_setup(void) -+{ -+ zcn_1523h_generic_setup(); -+ ap91_pci_setup_wmac_gpio(BIT(9), 0); -+ -+ ar71xx_add_device_leds_gpio(1, ARRAY_SIZE(zcn_1523h_2_leds_gpio), -+ zcn_1523h_2_leds_gpio); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_ZCN_1523H_2, "ZCN-1523H-2", "Zcomax ZCN-1523H-2", -+ zcn_1523h_2_setup); -+ -+static void __init zcn_1523h_5_setup(void) -+{ -+ zcn_1523h_generic_setup(); -+ ap91_pci_setup_wmac_gpio(BIT(8), 0); -+ -+ ar71xx_add_device_leds_gpio(1, ARRAY_SIZE(zcn_1523h_5_leds_gpio), -+ zcn_1523h_5_leds_gpio); -+ ar71xx_add_device_eth(1); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_ZCN_1523H_5, "ZCN-1523H-5", "Zcomax ZCN-1523H-5", -+ zcn_1523h_5_setup); -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/machtype.h linux-2.6.39/arch/mips/ar71xx/machtype.h ---- linux-2.6.39.orig/arch/mips/ar71xx/machtype.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/machtype.h 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,75 @@ -+/* -+ * Atheros AR71xx machine type definitions -+ * -+ * Copyright (C) 2008-2010 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_MACHTYPE_H -+#define _AR71XX_MACHTYPE_H -+ -+#include -+ -+enum ar71xx_mach_type { -+ AR71XX_MACH_GENERIC = 0, -+ AR71XX_MACH_AP121, /* Atheros AP121 */ -+ AR71XX_MACH_AP121_MINI, /* Atheros AP121-MINI */ -+ AR71XX_MACH_AP81, /* Atheros AP81 */ -+ AR71XX_MACH_AP83, /* Atheros AP83 */ -+ AR71XX_MACH_AW_NR580, /* AzureWave AW-NR580 */ -+ AR71XX_MACH_DIR_600_A1, /* D-Link DIR-600 rev. A1 */ -+ AR71XX_MACH_DIR_615_C1, /* D-Link DIR-615 rev. C1 */ -+ AR71XX_MACH_DIR_825_B1, /* D-Link DIR-825 rev. B1 */ -+ AR71XX_MACH_JA76PF, /* jjPlus JA76PF */ -+ AR71XX_MACH_JWAP003, /* jjPlus JWAP003 */ -+ AR71XX_MACH_RB_411, /* MikroTik RouterBOARD 411/411A/411AH */ -+ AR71XX_MACH_RB_411U, /* MikroTik RouterBOARD 411U */ -+ AR71XX_MACH_RB_433, /* MikroTik RouterBOARD 433/433AH */ -+ AR71XX_MACH_RB_433U, /* MikroTik RouterBOARD 433UAH */ -+ AR71XX_MACH_RB_450, /* MikroTik RouterBOARD 450 */ -+ AR71XX_MACH_RB_450G, /* MikroTik RouterBOARD 450G */ -+ AR71XX_MACH_RB_493, /* Mikrotik RouterBOARD 493/493AH */ -+ AR71XX_MACH_RB_750, /* MikroTik RouterBOARD 750 */ -+ AR71XX_MACH_PB42, /* Atheros PB42 */ -+ AR71XX_MACH_PB44, /* Atheros PB44 */ -+ AR71XX_MACH_PB92, /* Atheros PB92 */ -+ AR71XX_MACH_MZK_W04NU, /* Planex MZK-W04NU */ -+ AR71XX_MACH_MZK_W300NH, /* Planex MZK-W300NH */ -+ AR71XX_MACH_NBG460N, /* Zyxel NBG460N/550N/550NH */ -+ AR71XX_MACH_TEW_632BRP, /* TRENDnet TEW-632BRP */ -+ AR71XX_MACH_TL_MR3220, /* TP-LINK TL-MR3220 */ -+ AR71XX_MACH_TL_MR3420, /* TP-LINK TL-MR3420 */ -+ AR71XX_MACH_TL_WA901ND, /* TP-LINK TL-WA901ND */ -+ AR71XX_MACH_TL_WA901ND_V2, /* TP-LINK TL-WA901ND v2 */ -+ AR71XX_MACH_TL_WR741ND, /* TP-LINK TL-WR741ND */ -+ AR71XX_MACH_TL_WR841N_V1, /* TP-LINK TL-WR841N v1 */ -+ AR71XX_MACH_TL_WR941ND, /* TP-LINK TL-WR941ND */ -+ AR71XX_MACH_TL_WR1043ND, /* TP-LINK TL-WR1041ND */ -+ AR71XX_MACH_UBNT_LSSR71, /* Ubiquiti LS-SR71 */ -+ AR71XX_MACH_UBNT_LSX, /* Ubiquiti LSX */ -+ AR71XX_MACH_UBNT_RS, /* Ubiquiti RouterStation */ -+ AR71XX_MACH_UBNT_RSPRO, /* Ubiquiti RouterStation Pro */ -+ AR71XX_MACH_UBNT_BULLET_M, /* Ubiquiti Bullet M */ -+ AR71XX_MACH_UBNT_ROCKET_M, /* Ubiquiti Rocket M */ -+ AR71XX_MACH_UBNT_NANO_M, /* Ubiquiti NanoStation M */ -+ AR71XX_MACH_WNDR3700, /* NETGEAR WNDR3700 */ -+ AR71XX_MACH_WNDR3700V2, /* NETGEAR WNDR3700v2 */ -+ AR71XX_MACH_WNR2000, /* NETGEAR WNR2000 */ -+ AR71XX_MACH_WP543, /* Compex WP543 */ -+ AR71XX_MACH_WRT160NL, /* Linksys WRT160NL */ -+ AR71XX_MACH_WRT400N, /* Linksys WRT400N */ -+ AR71XX_MACH_WZR_HP_AG300H, /* Buffalo WZR-HP-AG300H */ -+ AR71XX_MACH_WZR_HP_G300NH, /* Buffalo WZR-HP-G300NH */ -+ AR71XX_MACH_EAP7660D, /* Senao EAP7660D */ -+ AR71XX_MACH_ZCN_1523H_2, /* Zcomax ZCN-1523H-2-xx */ -+ AR71XX_MACH_ZCN_1523H_5, /* Zcomax ZCN-1523H-5-xx */ -+ AR71XX_MACH_AP96, /* Atheros AP96 */ -+ AR71XX_MACH_UBNT_UNIFI, /* Unifi */ -+ AR71XX_MACH_DB120, /* Atheros DB120 (AR934x based) */ -+}; -+ -+#endif /* _AR71XX_MACHTYPE_H */ -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/nvram.c linux-2.6.39/arch/mips/ar71xx/nvram.c ---- linux-2.6.39.orig/arch/mips/ar71xx/nvram.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/nvram.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,75 @@ -+/* -+ * Atheros AR71xx minimal nvram support -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include "nvram.h" -+ -+char *nvram_find_var(const char *name, const char *buf, unsigned buf_len) -+{ -+ unsigned len = strlen(name); -+ char *cur, *last; -+ -+ if (buf_len == 0 || len == 0) -+ return NULL; -+ -+ if (buf_len < len) -+ return NULL; -+ -+ if (len == 1) -+ return memchr(buf, (int) *name, buf_len); -+ -+ last = (char *) buf + buf_len - len; -+ for (cur = (char *) buf; cur <= last; cur++) -+ if (cur[0] == name[0] && memcmp(cur, name, len) == 0) -+ return cur + len; -+ -+ return NULL; -+} -+ -+int nvram_parse_mac_addr(const char *nvram, unsigned nvram_len, -+ const char *name, char *mac) -+{ -+ char *buf; -+ char *mac_str; -+ int ret; -+ int t; -+ -+ buf = vmalloc(nvram_len); -+ if (!buf) -+ return -ENOMEM; -+ -+ memcpy(buf, nvram, nvram_len); -+ buf[nvram_len - 1] = '\0'; -+ -+ mac_str = nvram_find_var(name, buf, nvram_len); -+ if (!mac_str) { -+ ret = -EINVAL; -+ goto free; -+ } -+ -+ t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", -+ &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]); -+ -+ if (t != 6) { -+ ret = -EINVAL; -+ goto free; -+ } -+ -+ ret = 0; -+ -+free: -+ vfree(buf); -+ return ret; -+} -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/nvram.h linux-2.6.39/arch/mips/ar71xx/nvram.h ---- linux-2.6.39.orig/arch/mips/ar71xx/nvram.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/nvram.h 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,19 @@ -+/* -+ * Atheros AR71xx minimal nvram support -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_NVRAM_H -+#define _AR71XX_NVRAM_H -+ -+char *nvram_find_var(const char *name, const char *buf, -+ unsigned buf_len) __init; -+int nvram_parse_mac_addr(const char *nvram, unsigned nvram_len, -+ const char *name, char *mac) __init; -+ -+#endif /* _AR71XX_NVRAM_H */ -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/pci-ath9k-fixup.c linux-2.6.39/arch/mips/ar71xx/pci-ath9k-fixup.c ---- linux-2.6.39.orig/arch/mips/ar71xx/pci-ath9k-fixup.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/pci-ath9k-fixup.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,123 @@ -+/* -+ * Atheros AP94 reference board PCI initialization -+ * -+ * Copyright (C) 2009-2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+#include -+ -+struct ath9k_fixup { -+ u16 *cal_data; -+ unsigned slot; -+}; -+ -+static int ath9k_num_fixups; -+static struct ath9k_fixup ath9k_fixups[2]; -+ -+static void ath9k_pci_fixup(struct pci_dev *dev) -+{ -+ void __iomem *mem; -+ u16 *cal_data = NULL; -+ u16 cmd; -+ u32 bar0; -+ u32 val; -+ unsigned i; -+ -+ for (i = 0; i < ath9k_num_fixups; i++) { -+ if (ath9k_fixups[i].cal_data == NULL) -+ continue; -+ -+ if (ath9k_fixups[i].slot != PCI_SLOT(dev->devfn)) -+ continue; -+ -+ cal_data = ath9k_fixups[i].cal_data; -+ break; -+ } -+ -+ if (cal_data == NULL) -+ return; -+ -+ if (*cal_data != 0xa55a) { -+ pr_err("pci %s: invalid calibration data\n", pci_name(dev)); -+ return; -+ } -+ -+ pr_info("pci %s: fixup device configuration\n", pci_name(dev)); -+ -+ mem = ioremap(AR71XX_PCI_MEM_BASE, 0x10000); -+ if (!mem) { -+ pr_err("pci %s: ioremap error\n", pci_name(dev)); -+ return; -+ } -+ -+ pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0); -+ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7161: -+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, -+ AR71XX_PCI_MEM_BASE); -+ break; -+ case AR71XX_SOC_AR7240: -+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0xffff); -+ break; -+ -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0x1000ffff); -+ break; -+ -+ default: -+ BUG(); -+ } -+ -+ pci_read_config_word(dev, PCI_COMMAND, &cmd); -+ cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; -+ pci_write_config_word(dev, PCI_COMMAND, cmd); -+ -+ /* set pointer to first reg address */ -+ cal_data += 3; -+ while (*cal_data != 0xffff) { -+ u32 reg; -+ reg = *cal_data++; -+ val = *cal_data++; -+ val |= (*cal_data++) << 16; -+ -+ __raw_writel(val, mem + reg); -+ udelay(100); -+ } -+ -+ pci_read_config_dword(dev, PCI_VENDOR_ID, &val); -+ dev->vendor = val & 0xffff; -+ dev->device = (val >> 16) & 0xffff; -+ -+ pci_read_config_dword(dev, PCI_CLASS_REVISION, &val); -+ dev->revision = val & 0xff; -+ dev->class = val >> 8; /* upper 3 bytes */ -+ -+ pci_read_config_word(dev, PCI_COMMAND, &cmd); -+ cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); -+ pci_write_config_word(dev, PCI_COMMAND, cmd); -+ -+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, bar0); -+ -+ iounmap(mem); -+} -+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ath9k_pci_fixup); -+ -+void __init pci_enable_ath9k_fixup(unsigned slot, u16 *cal_data) -+{ -+ if (ath9k_num_fixups >= ARRAY_SIZE(ath9k_fixups)) -+ return; -+ -+ ath9k_fixups[ath9k_num_fixups].slot = slot; -+ ath9k_fixups[ath9k_num_fixups].cal_data = cal_data; -+ ath9k_num_fixups++; -+} -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/pci-ath9k-fixup.h linux-2.6.39/arch/mips/ar71xx/pci-ath9k-fixup.h ---- linux-2.6.39.orig/arch/mips/ar71xx/pci-ath9k-fixup.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/pci-ath9k-fixup.h 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,6 @@ -+#ifndef _PCI_ATH9K_FIXUP -+#define _PCI_ATH9K_FIXUP -+ -+void pci_enable_ath9k_fixup(unsigned slot, u16 *cal_data) __init; -+ -+#endif /* _PCI_ATH9K_FIXUP */ -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/pci.c linux-2.6.39/arch/mips/ar71xx/pci.c ---- linux-2.6.39.orig/arch/mips/ar71xx/pci.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/pci.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,97 @@ -+/* -+ * Atheros AR71xx PCI setup code -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+ -+#include -+ -+#include -+#include -+ -+unsigned ar71xx_pci_nr_irqs __initdata; -+struct ar71xx_pci_irq *ar71xx_pci_irq_map __initdata; -+ -+int (*ar71xx_pci_plat_dev_init)(struct pci_dev *dev); -+ -+static int ar71xx_be_handler(struct pt_regs *regs, int is_fixup) -+{ -+ int err = 0; -+ -+ err = ar71xx_pci_be_handler(is_fixup); -+ -+ return (is_fixup && !err) ? MIPS_BE_FIXUP : MIPS_BE_FATAL; -+} -+ -+int pcibios_plat_dev_init(struct pci_dev *dev) -+{ -+ if (ar71xx_pci_plat_dev_init) -+ return ar71xx_pci_plat_dev_init(dev); -+ -+ return 0; -+} -+ -+int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin) -+{ -+ int ret = 0; -+ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7130: -+ case AR71XX_SOC_AR7141: -+ case AR71XX_SOC_AR7161: -+ ret = ar71xx_pcibios_map_irq(dev, slot, pin); -+ break; -+ -+ case AR71XX_SOC_AR7240: -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ case AR71XX_SOC_AR9342: -+ case AR71XX_SOC_AR9344: -+ ret = ar724x_pcibios_map_irq(dev, slot, pin); -+ break; -+ -+ default: -+ break; -+ } -+ -+ return ret; -+} -+ -+int __init ar71xx_pci_init(unsigned nr_irqs, struct ar71xx_pci_irq *map) -+{ -+ int ret = 0; -+ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7130: -+ case AR71XX_SOC_AR7141: -+ case AR71XX_SOC_AR7161: -+ board_be_handler = ar71xx_be_handler; -+ ret = ar71xx_pcibios_init(); -+ break; -+ -+ case AR71XX_SOC_AR7240: -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ case AR71XX_SOC_AR9342: -+ case AR71XX_SOC_AR9344: -+ ret = ar724x_pcibios_init(); -+ break; -+ -+ default: -+ return 0; -+ } -+ -+ ar71xx_pci_nr_irqs = nr_irqs; -+ ar71xx_pci_irq_map = map; -+ -+ return ret; -+} -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/prom.c linux-2.6.39/arch/mips/ar71xx/prom.c ---- linux-2.6.39.orig/arch/mips/ar71xx/prom.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/prom.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,189 @@ -+/* -+ * Atheros AR71xx SoC specific prom routines -+ * -+ * Copyright (C) 2008-2010 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+#include -+ -+static inline int is_valid_ram_addr(void *addr) -+{ -+ if (((u32) addr > KSEG0) && -+ ((u32) addr < (KSEG0 + AR71XX_MEM_SIZE_MAX))) -+ return 1; -+ -+ if (((u32) addr > KSEG1) && -+ ((u32) addr < (KSEG1 + AR71XX_MEM_SIZE_MAX))) -+ return 1; -+ -+ return 0; -+} -+ -+static void __init ar71xx_prom_append_cmdline(const char *name, -+ const char *value) -+{ -+ char buf[COMMAND_LINE_SIZE]; -+ -+ snprintf(buf, sizeof(buf), " %s=%s", name, value); -+ strlcat(arcs_cmdline, buf, sizeof(arcs_cmdline)); -+} -+ -+static const char * __init ar71xx_prom_find_env(char **envp, const char *name) -+{ -+ const char *ret = NULL; -+ int len; -+ char **p; -+ -+ if (!is_valid_ram_addr(envp)) -+ return NULL; -+ -+ len = strlen(name); -+ for (p = envp; is_valid_ram_addr(*p); p++) { -+ if (strncmp(name, *p, len) == 0 && (*p)[len] == '=') { -+ ret = *p + len + 1; -+ break; -+ } -+ -+ /* RedBoot env comes in pointer pairs - key, value */ -+ if (strncmp(name, *p, len) == 0 && (*p)[len] == 0) -+ if (is_valid_ram_addr(*(++p))) { -+ ret = *p; -+ break; -+ } -+ } -+ -+ return ret; -+} -+ -+static int __init ar71xx_prom_init_myloader(void) -+{ -+ struct myloader_info *mylo; -+ char mac_buf[32]; -+ char *mac; -+ -+ mylo = myloader_get_info(); -+ if (!mylo) -+ return 0; -+ -+ switch (mylo->did) { -+ case DEVID_COMPEX_WP543: -+ ar71xx_prom_append_cmdline("board", "WP543"); -+ break; -+ default: -+ printk(KERN_WARNING "prom: unknown device id: %x\n", -+ mylo->did); -+ return 0; -+ } -+ -+ mac = mylo->macs[0]; -+ snprintf(mac_buf, sizeof(mac_buf), "%02x:%02x:%02x:%02x:%02x:%02x", -+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); -+ -+ ar71xx_prom_append_cmdline("ethaddr", mac_buf); -+ -+ return 1; -+} -+ -+#ifdef CONFIG_IMAGE_CMDLINE_HACK -+extern char __image_cmdline[]; -+ -+static int __init ar71xx_use__image_cmdline(void) -+{ -+ char *p = __image_cmdline; -+ int replace = 0; -+ -+ if (*p == '-') { -+ replace = 1; -+ p++; -+ } -+ -+ if (*p == '\0') -+ return 0; -+ -+ if (replace) { -+ strlcpy(arcs_cmdline, p, sizeof(arcs_cmdline)); -+ } else { -+ strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline)); -+ strlcat(arcs_cmdline, p, sizeof(arcs_cmdline)); -+ } -+ -+ return 1; -+} -+#else -+static inline int ar71xx_use__image_cmdline(void) { return 0; } -+#endif -+ -+static __init void ar71xx_prom_init_cmdline(int argc, char **argv) -+{ -+ int i; -+ -+ if (ar71xx_use__image_cmdline()) -+ return; -+ -+ if (!is_valid_ram_addr(argv)) -+ return; -+ -+ for (i = 0; i < argc; i++) -+ if (is_valid_ram_addr(argv[i])) { -+ strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline)); -+ strlcat(arcs_cmdline, argv[i], sizeof(arcs_cmdline)); -+ } -+} -+ -+void __init prom_init(void) -+{ -+ const char *env; -+ char **envp; -+ -+ printk(KERN_DEBUG "prom: fw_arg0=%08x, fw_arg1=%08x, " -+ "fw_arg2=%08x, fw_arg3=%08x\n", -+ (unsigned int)fw_arg0, (unsigned int)fw_arg1, -+ (unsigned int)fw_arg2, (unsigned int)fw_arg3); -+ -+ -+ if (ar71xx_prom_init_myloader()) -+ return; -+ -+ ar71xx_prom_init_cmdline(fw_arg0, (char **)fw_arg1); -+ -+ envp = (char **)fw_arg2; -+ if (!strstr(arcs_cmdline, "ethaddr=")) { -+ env = ar71xx_prom_find_env(envp, "ethaddr"); -+ if (env) -+ ar71xx_prom_append_cmdline("ethaddr", env); -+ } -+ -+ if (!strstr(arcs_cmdline, "board=")) { -+ env = ar71xx_prom_find_env(envp, "board"); -+ if (env) { -+ /* Workaround for buggy bootloaders */ -+ if (strcmp(env, "RouterStation") == 0 || -+ strcmp(env, "Ubiquiti AR71xx-based board") == 0) -+ env = "UBNT-RS"; -+ -+ if (strcmp(env, "RouterStation PRO") == 0) -+ env = "UBNT-RSPRO"; -+ -+ ar71xx_prom_append_cmdline("board", env); -+ } -+ } -+} -+ -+void __init prom_free_prom_memory(void) -+{ -+ /* We do not have to prom memory to free */ -+} -diff -Nur linux-2.6.39.orig/arch/mips/ar71xx/setup.c linux-2.6.39/arch/mips/ar71xx/setup.c ---- linux-2.6.39.orig/arch/mips/ar71xx/setup.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/ar71xx/setup.c 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,446 @@ -+/* -+ * Atheros AR71xx SoC specific setup -+ * -+ * Copyright (C) 2010-2011 Jaiganesh Narayanan -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros 2.6.15 BSP -+ * Parts of this file are based on Atheros 2.6.31 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+ -+#include -+#include /* for mips_hpt_frequency */ -+#include /* for _machine_{restart,halt} */ -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+ -+#define AR71XX_SYS_TYPE_LEN 64 -+ -+u32 ar71xx_cpu_freq; -+EXPORT_SYMBOL_GPL(ar71xx_cpu_freq); -+ -+u32 ar71xx_ahb_freq; -+EXPORT_SYMBOL_GPL(ar71xx_ahb_freq); -+ -+u32 ar71xx_ddr_freq; -+EXPORT_SYMBOL_GPL(ar71xx_ddr_freq); -+ -+u32 ar71xx_ref_freq; -+EXPORT_SYMBOL_GPL(ar71xx_ref_freq); -+ -+enum ar71xx_soc_type ar71xx_soc; -+EXPORT_SYMBOL_GPL(ar71xx_soc); -+ -+u32 ar71xx_soc_rev; -+EXPORT_SYMBOL_GPL(ar71xx_soc_rev); -+ -+static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN]; -+ -+static void ar71xx_restart(char *command) -+{ -+ ar71xx_device_stop(RESET_MODULE_FULL_CHIP); -+ for (;;) -+ if (cpu_wait) -+ cpu_wait(); -+} -+ -+static void ar71xx_halt(void) -+{ -+ while (1) -+ cpu_wait(); -+} -+ -+static void __init ar71xx_detect_mem_size(void) -+{ -+ unsigned long size; -+ -+ for (size = AR71XX_MEM_SIZE_MIN; size < AR71XX_MEM_SIZE_MAX; -+ size <<= 1) { -+ if (!memcmp(ar71xx_detect_mem_size, -+ ar71xx_detect_mem_size + size, 1024)) -+ break; -+ } -+ -+ add_memory_region(0, size, BOOT_MEM_RAM); -+} -+ -+static void __init ar71xx_detect_sys_type(void) -+{ -+ char *chip = "????"; -+ u32 id; -+ u32 major; -+ u32 minor; -+ u32 rev = 0; -+ -+ id = ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID); -+ major = id & REV_ID_MAJOR_MASK; -+ -+ switch (major) { -+ case REV_ID_MAJOR_AR71XX: -+ minor = id & AR71XX_REV_ID_MINOR_MASK; -+ rev = id >> AR71XX_REV_ID_REVISION_SHIFT; -+ rev &= AR71XX_REV_ID_REVISION_MASK; -+ switch (minor) { -+ case AR71XX_REV_ID_MINOR_AR7130: -+ ar71xx_soc = AR71XX_SOC_AR7130; -+ chip = "7130"; -+ break; -+ -+ case AR71XX_REV_ID_MINOR_AR7141: -+ ar71xx_soc = AR71XX_SOC_AR7141; -+ chip = "7141"; -+ break; -+ -+ case AR71XX_REV_ID_MINOR_AR7161: -+ ar71xx_soc = AR71XX_SOC_AR7161; -+ chip = "7161"; -+ break; -+ } -+ break; -+ -+ case REV_ID_MAJOR_AR7240: -+ ar71xx_soc = AR71XX_SOC_AR7240; -+ chip = "7240"; -+ rev = id & AR724X_REV_ID_REVISION_MASK; -+ break; -+ -+ case REV_ID_MAJOR_AR7241: -+ ar71xx_soc = AR71XX_SOC_AR7241; -+ chip = "7241"; -+ rev = id & AR724X_REV_ID_REVISION_MASK; -+ break; -+ -+ case REV_ID_MAJOR_AR7242: -+ ar71xx_soc = AR71XX_SOC_AR7242; -+ chip = "7242"; -+ rev = id & AR724X_REV_ID_REVISION_MASK; -+ break; -+ -+ case REV_ID_MAJOR_AR913X: -+ minor = id & AR91XX_REV_ID_MINOR_MASK; -+ rev = id >> AR91XX_REV_ID_REVISION_SHIFT; -+ rev &= AR91XX_REV_ID_REVISION_MASK; -+ switch (minor) { -+ case AR91XX_REV_ID_MINOR_AR9130: -+ ar71xx_soc = AR71XX_SOC_AR9130; -+ chip = "9130"; -+ break; -+ -+ case AR91XX_REV_ID_MINOR_AR9132: -+ ar71xx_soc = AR71XX_SOC_AR9132; -+ chip = "9132"; -+ break; -+ } -+ break; -+ -+ case REV_ID_MAJOR_AR9330: -+ ar71xx_soc = AR71XX_SOC_AR9330; -+ chip = "9330"; -+ rev = id & AR933X_REV_ID_REVISION_MASK; -+ break; -+ -+ case REV_ID_MAJOR_AR9331: -+ ar71xx_soc = AR71XX_SOC_AR9331; -+ chip = "9331"; -+ rev = id & AR933X_REV_ID_REVISION_MASK; -+ break; -+ -+ case REV_ID_MAJOR_AR9342: -+ ar71xx_soc = AR71XX_SOC_AR9342; -+ chip = "9342"; -+ rev = id & AR934X_REV_ID_REVISION_MASK; -+ break; -+ -+ case REV_ID_MAJOR_AR9344: -+ ar71xx_soc = AR71XX_SOC_AR9344; -+ chip = "9344"; -+ rev = id & AR934X_REV_ID_REVISION_MASK; -+ break; -+ -+ default: -+ panic("ar71xx: unknown chip id:0x%08x\n", id); -+ } -+ -+ ar71xx_soc_rev = rev; -+ -+ sprintf(ar71xx_sys_type, "Atheros AR%s rev %u", chip, rev); -+ pr_info("SoC: %s\n", ar71xx_sys_type); -+} -+ -+static void __init ar934x_detect_sys_frequency(void) -+{ -+ u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; -+ -+ if (ar71xx_reset_rr(AR934X_RESET_REG_BOOTSTRAP) & AR934X_REF_CLK_40) -+ ar71xx_ref_freq = 40 * 1000 * 1000; -+ else -+ ar71xx_ref_freq = 25 * 1000 * 1000; -+ -+ clk_ctrl = ar71xx_pll_rr(AR934X_PLL_REG_DDR_CTRL_CLOCK); -+ -+ pll = ar71xx_pll_rr(AR934X_PLL_REG_CPU_CONFIG); -+ out_div = AR934X_CPU_PLL_CFG_OUTDIV_GET(pll); -+ ref_div = AR934X_CPU_PLL_CFG_REFDIV_GET(pll); -+ nint = AR934X_CPU_PLL_CFG_NINT_GET(pll); -+ frac = AR934X_CPU_PLL_CFG_NFRAC_GET(pll); -+ postdiv = AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_GET(clk_ctrl); -+ ar71xx_cpu_freq = ((nint * ar71xx_ref_freq / ref_div) >> out_div) / -+ (postdiv + 1); -+ -+ out_div = AR934X_DDR_PLL_CFG_OUTDIV_GET(pll); -+ ref_div = AR934X_DDR_PLL_CFG_REFDIV_GET(pll); -+ nint = AR934X_DDR_PLL_CFG_NINT_GET(pll); -+ frac = AR934X_DDR_PLL_CFG_NFRAC_GET(pll); -+ postdiv = AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_GET(clk_ctrl); -+ ar71xx_ddr_freq = ((nint * ar71xx_ref_freq / ref_div) >> out_div) / -+ (postdiv + 1); -+ -+ postdiv = AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_GET(clk_ctrl); -+ -+ if (AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_GET(clk_ctrl)) { -+ ar71xx_ahb_freq = ar71xx_ddr_freq / (postdiv + 1); -+ } else { -+ ar71xx_ahb_freq = ar71xx_cpu_freq / (postdiv + 1); -+ } -+ -+} -+ -+static void __init ar91xx_detect_sys_frequency(void) -+{ -+ u32 pll; -+ u32 freq; -+ u32 div; -+ -+ ar71xx_ref_freq = 5 * 1000 * 1000; -+ -+ pll = ar71xx_pll_rr(AR91XX_PLL_REG_CPU_CONFIG); -+ -+ div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK); -+ freq = div * ar71xx_ref_freq; -+ -+ ar71xx_cpu_freq = freq; -+ -+ div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1; -+ ar71xx_ddr_freq = freq / div; -+ -+ div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2; -+ ar71xx_ahb_freq = ar71xx_cpu_freq / div; -+} -+ -+static void __init ar71xx_detect_sys_frequency(void) -+{ -+ u32 pll; -+ u32 freq; -+ u32 div; -+ -+ ar71xx_ref_freq = 40 * 1000 * 1000; -+ -+ pll = ar71xx_pll_rr(AR71XX_PLL_REG_CPU_CONFIG); -+ -+ div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1; -+ freq = div * ar71xx_ref_freq; -+ -+ div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1; -+ ar71xx_cpu_freq = freq / div; -+ -+ div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1; -+ ar71xx_ddr_freq = freq / div; -+ -+ div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2; -+ ar71xx_ahb_freq = ar71xx_cpu_freq / div; -+} -+ -+static void __init ar724x_detect_sys_frequency(void) -+{ -+ u32 pll; -+ u32 freq; -+ u32 div; -+ -+ ar71xx_ref_freq = 5 * 1000 * 1000; -+ -+ pll = ar71xx_pll_rr(AR724X_PLL_REG_CPU_CONFIG); -+ -+ div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK); -+ freq = div * ar71xx_ref_freq; -+ -+ div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK); -+ freq *= div; -+ -+ ar71xx_cpu_freq = freq; -+ -+ div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1; -+ ar71xx_ddr_freq = freq / div; -+ -+ div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2; -+ ar71xx_ahb_freq = ar71xx_cpu_freq / div; -+} -+ -+static void __init ar933x_detect_sys_frequency(void) -+{ -+ u32 clock_ctrl; -+ u32 cpu_config; -+ u32 freq; -+ u32 t; -+ -+ t = ar71xx_reset_rr(AR933X_RESET_REG_BOOTSTRAP); -+ if (t & AR933X_BOOTSTRAP_REF_CLK_40) -+ ar71xx_ref_freq = (40 * 1000 * 1000); -+ else -+ ar71xx_ref_freq = (25 * 1000 * 1000); -+ -+ clock_ctrl = ar71xx_pll_rr(AR933X_PLL_CLOCK_CTRL_REG); -+ if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) { -+ ar71xx_cpu_freq = ar71xx_ref_freq; -+ ar71xx_ahb_freq = ar71xx_ref_freq; -+ ar71xx_ddr_freq = ar71xx_ref_freq; -+ } else { -+ cpu_config = ar71xx_pll_rr(AR933X_PLL_CPU_CONFIG_REG); -+ -+ t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) & -+ AR933X_PLL_CPU_CONFIG_REFDIV_MASK; -+ freq = ar71xx_ref_freq / t; -+ -+ t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) & -+ AR933X_PLL_CPU_CONFIG_NINT_MASK; -+ freq *= t; -+ -+ t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & -+ AR933X_PLL_CPU_CONFIG_OUTDIV_MASK; -+ if (t == 0) -+ t = 1; -+ -+ freq >>= t; -+ -+ t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) & -+ AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1; -+ ar71xx_cpu_freq = freq / t; -+ -+ t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) & -+ AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1; -+ ar71xx_ddr_freq = freq / t; -+ -+ t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) & -+ AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1; -+ ar71xx_ahb_freq = freq / t; -+ } -+} -+ -+static void __init detect_sys_frequency(void) -+{ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7130: -+ case AR71XX_SOC_AR7141: -+ case AR71XX_SOC_AR7161: -+ ar71xx_detect_sys_frequency(); -+ break; -+ -+ case AR71XX_SOC_AR7240: -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ ar724x_detect_sys_frequency(); -+ break; -+ -+ case AR71XX_SOC_AR9130: -+ case AR71XX_SOC_AR9132: -+ ar91xx_detect_sys_frequency(); -+ break; -+ -+ case AR71XX_SOC_AR9330: -+ case AR71XX_SOC_AR9331: -+ ar933x_detect_sys_frequency(); -+ break; -+ -+ case AR71XX_SOC_AR9341: -+ case AR71XX_SOC_AR9342: -+ case AR71XX_SOC_AR9344: -+ ar934x_detect_sys_frequency(); -+ break; -+ default: -+ BUG(); -+ } -+} -+ -+const char *get_system_type(void) -+{ -+ return ar71xx_sys_type; -+} -+ -+unsigned int __cpuinit get_c0_compare_irq(void) -+{ -+ return CP0_LEGACY_COMPARE_IRQ; -+} -+ -+void __init plat_mem_setup(void) -+{ -+ set_io_port_base(KSEG1); -+ -+ ar71xx_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE, -+ AR71XX_DDR_CTRL_SIZE); -+ -+ ar71xx_pll_base = ioremap_nocache(AR71XX_PLL_BASE, -+ AR71XX_PLL_SIZE); -+ -+ ar71xx_reset_base = ioremap_nocache(AR71XX_RESET_BASE, -+ AR71XX_RESET_SIZE); -+ -+ ar71xx_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE); -+ -+ ar71xx_usb_ctrl_base = ioremap_nocache(AR71XX_USB_CTRL_BASE, -+ AR71XX_USB_CTRL_SIZE); -+ -+ ar71xx_detect_mem_size(); -+ ar71xx_detect_sys_type(); -+ detect_sys_frequency(); -+ -+ pr_info("Clocks: CPU:%u.%03uMHz, DDR:%u.%03uMHz, AHB:%u.%03uMHz, " -+ "Ref:%u.%03uMHz", -+ ar71xx_cpu_freq / 1000000, (ar71xx_cpu_freq / 1000) % 1000, -+ ar71xx_ddr_freq / 1000000, (ar71xx_ddr_freq / 1000) % 1000, -+ ar71xx_ahb_freq / 1000000, (ar71xx_ahb_freq / 1000) % 1000, -+ ar71xx_ref_freq / 1000000, (ar71xx_ref_freq / 1000) % 1000); -+ -+ _machine_restart = ar71xx_restart; -+ _machine_halt = ar71xx_halt; -+ pm_power_off = ar71xx_halt; -+} -+ -+void __init plat_time_init(void) -+{ -+ mips_hpt_frequency = ar71xx_cpu_freq / 2; -+} -+ -+__setup("board=", mips_machtype_setup); -+ -+static int __init ar71xx_machine_setup(void) -+{ -+ ar71xx_gpio_init(); -+ -+ ar71xx_add_device_uart(); -+ ar71xx_add_device_wdt(); -+ -+ mips_machine_setup(); -+ return 0; -+} -+ -+arch_initcall(ar71xx_machine_setup); -+ -+static void __init ar71xx_generic_init(void) -+{ -+ /* Nothing to do */ -+} -+ -+MIPS_MACHINE(AR71XX_MACH_GENERIC, "Generic", "Generic AR71xx board", -+ ar71xx_generic_init); -diff -Nur linux-2.6.39.orig/arch/mips/include/asm/checksum.h linux-2.6.39/arch/mips/include/asm/checksum.h ---- linux-2.6.39.orig/arch/mips/include/asm/checksum.h 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/arch/mips/include/asm/checksum.h 2011-08-24 18:17:23.000000000 +0200 -@@ -12,6 +12,7 @@ - #define _ASM_CHECKSUM_H - - #include -+#include - - #include - -@@ -104,26 +105,30 @@ - const unsigned int *stop = word + ihl; - unsigned int csum; - int carry; -+ unsigned int w; - -- csum = word[0]; -- csum += word[1]; -- carry = (csum < word[1]); -+ csum = __get_unaligned_cpu32(word++); -+ -+ w = __get_unaligned_cpu32(word++); -+ csum += w; -+ carry = (csum < w); - csum += carry; - -- csum += word[2]; -- carry = (csum < word[2]); -+ w = __get_unaligned_cpu32(word++); -+ csum += w; -+ carry = (csum < w); - csum += carry; - -- csum += word[3]; -- carry = (csum < word[3]); -+ w = __get_unaligned_cpu32(word++); -+ csum += w; -+ carry = (csum < w); - csum += carry; - -- word += 4; - do { -- csum += *word; -- carry = (csum < *word); -+ w = __get_unaligned_cpu32(word++); -+ csum += w; -+ carry = (csum < w); - csum += carry; -- word++; - } while (word != stop); - - return csum_fold(csum); -diff -Nur linux-2.6.39.orig/arch/mips/include/asm/fw/myloader/myloader.h linux-2.6.39/arch/mips/include/asm/fw/myloader/myloader.h ---- linux-2.6.39.orig/arch/mips/include/asm/fw/myloader/myloader.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/include/asm/fw/myloader/myloader.h 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,34 @@ -+/* -+ * Compex's MyLoader specific definitions -+ * -+ * Copyright (C) 2006-2008 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ */ -+ -+#ifndef _ASM_MIPS_FW_MYLOADER_H -+#define _ASM_MIPS_FW_MYLOADER_H -+ -+#include -+ -+struct myloader_info { -+ uint32_t vid; -+ uint32_t did; -+ uint32_t svid; -+ uint32_t sdid; -+ uint8_t macs[MYLO_ETHADDR_COUNT][6]; -+}; -+ -+#ifdef CONFIG_MYLOADER -+extern struct myloader_info *myloader_get_info(void) __init; -+#else -+static inline struct myloader_info *myloader_get_info(void) -+{ -+ return NULL; -+} -+#endif /* CONFIG_MYLOADER */ -+ -+#endif /* _ASM_MIPS_FW_MYLOADER_H */ -diff -Nur linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/ar71xx.h linux-2.6.39/arch/mips/include/asm/mach-ar71xx/ar71xx.h ---- linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/ar71xx.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/include/asm/mach-ar71xx/ar71xx.h 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,769 @@ -+/* -+ * Atheros AR71xx SoC specific definitions -+ * -+ * Copyright (C) 2010-2011 Jaiganesh Narayanan -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros 2.6.15 BSP -+ * Parts of this file are based on Atheros 2.6.31 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef __ASM_MACH_AR71XX_H -+#define __ASM_MACH_AR71XX_H -+ -+#include -+#include -+#include -+#include -+ -+#ifndef __ASSEMBLER__ -+ -+#define AR71XX_PCI_MEM_BASE 0x10000000 -+#define AR71XX_PCI_MEM_SIZE 0x08000000 -+#define AR71XX_APB_BASE 0x18000000 -+#define AR71XX_GE0_BASE 0x19000000 -+#define AR71XX_GE0_SIZE 0x01000000 -+#define AR71XX_GE1_BASE 0x1a000000 -+#define AR71XX_GE1_SIZE 0x01000000 -+#define AR71XX_EHCI_BASE 0x1b000000 -+#define AR71XX_EHCI_SIZE 0x01000000 -+#define AR71XX_OHCI_BASE 0x1c000000 -+#define AR71XX_OHCI_SIZE 0x01000000 -+#define AR7240_OHCI_BASE 0x1b000000 -+#define AR7240_OHCI_SIZE 0x01000000 -+#define AR71XX_SPI_BASE 0x1f000000 -+#define AR71XX_SPI_SIZE 0x01000000 -+ -+#define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000) -+#define AR71XX_DDR_CTRL_SIZE 0x10000 -+#define AR71XX_CPU_BASE (AR71XX_APB_BASE + 0x00010000) -+#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000) -+#define AR71XX_UART_SIZE 0x10000 -+#define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) -+#define AR71XX_USB_CTRL_SIZE 0x10000 -+#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000) -+#define AR71XX_GPIO_SIZE 0x10000 -+#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000) -+#define AR71XX_PLL_SIZE 0x10000 -+#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) -+#define AR71XX_RESET_SIZE 0x10000 -+#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000) -+#define AR71XX_MII_SIZE 0x10000 -+#define AR71XX_SLIC_BASE (AR71XX_APB_BASE + 0x00090000) -+#define AR71XX_SLIC_SIZE 0x10000 -+#define AR71XX_DMA_BASE (AR71XX_APB_BASE + 0x000A0000) -+#define AR71XX_DMA_SIZE 0x10000 -+#define AR71XX_STEREO_BASE (AR71XX_APB_BASE + 0x000B0000) -+#define AR71XX_STEREO_SIZE 0x10000 -+ -+#define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000C0000) -+#define AR724X_PCI_CRP_SIZE 0x100 -+ -+#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000F0000) -+#define AR724X_PCI_CTRL_SIZE 0x100 -+ -+#define AR91XX_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000) -+#define AR91XX_WMAC_SIZE 0x30000 -+ -+#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000) -+#define AR933X_UART_SIZE 0x14 -+#define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) -+#define AR933X_WMAC_SIZE 0x20000 -+ -+#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) -+#define AR934X_WMAC_SIZE 0x20000 -+ -+#define AR71XX_MEM_SIZE_MIN 0x0200000 -+#define AR71XX_MEM_SIZE_MAX 0x10000000 -+ -+#define AR71XX_CPU_IRQ_BASE 0 -+#define AR71XX_MISC_IRQ_BASE 8 -+#define AR71XX_MISC_IRQ_COUNT 32 -+#define AR71XX_GPIO_IRQ_BASE 40 -+#define AR71XX_GPIO_IRQ_COUNT 32 -+#define AR71XX_PCI_IRQ_BASE 72 -+#define AR71XX_PCI_IRQ_COUNT 8 -+ -+#define AR71XX_CPU_IRQ_IP2 (AR71XX_CPU_IRQ_BASE + 2) -+#define AR71XX_CPU_IRQ_USB (AR71XX_CPU_IRQ_BASE + 3) -+#define AR71XX_CPU_IRQ_GE0 (AR71XX_CPU_IRQ_BASE + 4) -+#define AR71XX_CPU_IRQ_GE1 (AR71XX_CPU_IRQ_BASE + 5) -+#define AR71XX_CPU_IRQ_MISC (AR71XX_CPU_IRQ_BASE + 6) -+#define AR71XX_CPU_IRQ_TIMER (AR71XX_CPU_IRQ_BASE + 7) -+ -+#define AR71XX_MISC_IRQ_TIMER (AR71XX_MISC_IRQ_BASE + 0) -+#define AR71XX_MISC_IRQ_ERROR (AR71XX_MISC_IRQ_BASE + 1) -+#define AR71XX_MISC_IRQ_GPIO (AR71XX_MISC_IRQ_BASE + 2) -+#define AR71XX_MISC_IRQ_UART (AR71XX_MISC_IRQ_BASE + 3) -+#define AR71XX_MISC_IRQ_WDOG (AR71XX_MISC_IRQ_BASE + 4) -+#define AR71XX_MISC_IRQ_PERFC (AR71XX_MISC_IRQ_BASE + 5) -+#define AR71XX_MISC_IRQ_OHCI (AR71XX_MISC_IRQ_BASE + 6) -+#define AR71XX_MISC_IRQ_DMA (AR71XX_MISC_IRQ_BASE + 7) -+#define AR71XX_MISC_IRQ_TIMER2 (AR71XX_MISC_IRQ_BASE + 8) -+#define AR71XX_MISC_IRQ_TIMER3 (AR71XX_MISC_IRQ_BASE + 9) -+#define AR71XX_MISC_IRQ_TIMER4 (AR71XX_MISC_IRQ_BASE + 10) -+#define AR71XX_MISC_IRQ_DDR_PERF (AR71XX_MISC_IRQ_BASE + 11) -+#define AR71XX_MISC_IRQ_ENET_LINK (AR71XX_MISC_IRQ_BASE + 12) -+ -+#define AR71XX_GPIO_IRQ(_x) (AR71XX_GPIO_IRQ_BASE + (_x)) -+ -+#define AR71XX_PCI_IRQ_DEV0 (AR71XX_PCI_IRQ_BASE + 0) -+#define AR71XX_PCI_IRQ_DEV1 (AR71XX_PCI_IRQ_BASE + 1) -+#define AR71XX_PCI_IRQ_DEV2 (AR71XX_PCI_IRQ_BASE + 2) -+#define AR71XX_PCI_IRQ_CORE (AR71XX_PCI_IRQ_BASE + 4) -+ -+extern u32 ar71xx_ahb_freq; -+extern u32 ar71xx_cpu_freq; -+extern u32 ar71xx_ddr_freq; -+extern u32 ar71xx_ref_freq; -+ -+enum ar71xx_soc_type { -+ AR71XX_SOC_UNKNOWN, -+ AR71XX_SOC_AR7130, -+ AR71XX_SOC_AR7141, -+ AR71XX_SOC_AR7161, -+ AR71XX_SOC_AR7240, -+ AR71XX_SOC_AR7241, -+ AR71XX_SOC_AR7242, -+ AR71XX_SOC_AR9130, -+ AR71XX_SOC_AR9132, -+ AR71XX_SOC_AR9330, -+ AR71XX_SOC_AR9331, -+ AR71XX_SOC_AR9341, -+ AR71XX_SOC_AR9342, -+ AR71XX_SOC_AR9344, -+}; -+extern u32 ar71xx_soc_rev; -+ -+extern enum ar71xx_soc_type ar71xx_soc; -+ -+/* -+ * PLL block -+ */ -+#define AR71XX_PLL_REG_CPU_CONFIG 0x00 -+#define AR71XX_PLL_REG_SEC_CONFIG 0x04 -+#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10 -+#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14 -+ -+#define AR71XX_PLL_DIV_SHIFT 3 -+#define AR71XX_PLL_DIV_MASK 0x1f -+#define AR71XX_CPU_DIV_SHIFT 16 -+#define AR71XX_CPU_DIV_MASK 0x3 -+#define AR71XX_DDR_DIV_SHIFT 18 -+#define AR71XX_DDR_DIV_MASK 0x3 -+#define AR71XX_AHB_DIV_SHIFT 20 -+#define AR71XX_AHB_DIV_MASK 0x7 -+ -+#define AR71XX_ETH0_PLL_SHIFT 17 -+#define AR71XX_ETH1_PLL_SHIFT 19 -+ -+#define AR724X_PLL_REG_CPU_CONFIG 0x00 -+#define AR724X_PLL_REG_PCIE_CONFIG 0x18 -+ -+#define AR724X_PLL_DIV_SHIFT 0 -+#define AR724X_PLL_DIV_MASK 0x3ff -+#define AR724X_PLL_REF_DIV_SHIFT 10 -+#define AR724X_PLL_REF_DIV_MASK 0xf -+#define AR724X_AHB_DIV_SHIFT 19 -+#define AR724X_AHB_DIV_MASK 0x1 -+#define AR724X_DDR_DIV_SHIFT 22 -+#define AR724X_DDR_DIV_MASK 0x3 -+ -+#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c -+ -+#define AR91XX_PLL_REG_CPU_CONFIG 0x00 -+#define AR91XX_PLL_REG_ETH_CONFIG 0x04 -+#define AR91XX_PLL_REG_ETH0_INT_CLOCK 0x14 -+#define AR91XX_PLL_REG_ETH1_INT_CLOCK 0x18 -+ -+#define AR91XX_PLL_DIV_SHIFT 0 -+#define AR91XX_PLL_DIV_MASK 0x3ff -+#define AR91XX_DDR_DIV_SHIFT 22 -+#define AR91XX_DDR_DIV_MASK 0x3 -+#define AR91XX_AHB_DIV_SHIFT 19 -+#define AR91XX_AHB_DIV_MASK 0x1 -+ -+#define AR91XX_ETH0_PLL_SHIFT 20 -+#define AR91XX_ETH1_PLL_SHIFT 22 -+ -+#define AR933X_PLL_CPU_CONFIG_REG 0x00 -+#define AR933X_PLL_CLOCK_CTRL_REG 0x08 -+ -+#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10 -+#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f -+#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16 -+#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f -+#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23 -+#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 -+ -+#define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2) -+#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5 -+#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3 -+#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10 -+#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3 -+#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15 -+#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7 -+ -+#define AR934X_PLL_REG_CPU_CONFIG 0x00 -+#define AR934X_PLL_REG_DDR_CTRL_CLOCK 0x8 -+ -+#define AR934X_CPU_PLL_CFG_OUTDIV_MSB 21 -+#define AR934X_CPU_PLL_CFG_OUTDIV_LSB 19 -+#define AR934X_CPU_PLL_CFG_OUTDIV_MASK 0x00380000 -+ -+#define AR934X_CPU_PLL_CFG_OUTDIV_GET(x) \ -+ (((x) & AR934X_CPU_PLL_CFG_OUTDIV_MASK) >> \ -+ AR934X_CPU_PLL_CFG_OUTDIV_LSB) -+ -+#define AR934X_DDR_PLL_CFG_OUTDIV_MSB 25 -+#define AR934X_DDR_PLL_CFG_OUTDIV_LSB 23 -+#define AR934X_DDR_PLL_CFG_OUTDIV_MASK 0x03800000 -+ -+#define AR934X_DDR_PLL_CFG_OUTDIV_GET(x) \ -+ (((x) & AR934X_DDR_PLL_CFG_OUTDIV_MASK) >> \ -+ AR934X_DDR_PLL_CFG_OUTDIV_LSB) -+ -+#define AR934X_DDR_PLL_CFG_OUTDIV_SET(x) \ -+ (((x) << AR934X_DDR_PLL_CFG_OUTDIV_LSB) & \ -+ AR934X_DDR_PLL_CFG_OUTDIV_MASK) -+ -+#define AR934X_CPU_PLL_CFG_REFDIV_MSB 16 -+#define AR934X_CPU_PLL_CFG_REFDIV_LSB 12 -+#define AR934X_CPU_PLL_CFG_REFDIV_MASK 0x0001f000 -+ -+#define AR934X_CPU_PLL_CFG_REFDIV_GET(x) \ -+ (((x) & AR934X_CPU_PLL_CFG_REFDIV_MASK) >> \ -+ AR934X_CPU_PLL_CFG_REFDIV_LSB) -+ -+#define AR934X_CPU_PLL_CFG_REFDIV_SET(x) \ -+ (((x) << AR934X_CPU_PLL_CFG_REFDIV_LSB) & \ -+ AR934X_CPU_PLL_CFG_REFDIV_MASK) -+ -+#define AR934X_CPU_PLL_CFG_REFDIV_RESET 2 -+ -+#define AR934X_CPU_PLL_CFG_NINT_MSB 11 -+#define AR934X_CPU_PLL_CFG_NINT_LSB 6 -+#define AR934X_CPU_PLL_CFG_NINT_MASK 0x00000fc0 -+ -+#define AR934X_CPU_PLL_CFG_NINT_GET(x) \ -+ (((x) & AR934X_CPU_PLL_CFG_NINT_MASK) >> \ -+ AR934X_CPU_PLL_CFG_NINT_LSB) -+ -+#define AR934X_CPU_PLL_CFG_NINT_SET(x) \ -+ (((x) << AR934X_CPU_PLL_CFG_NINT_LSB) & \ -+ AR934X_CPU_PLL_CFG_NINT_MASK) -+ -+#define AR934X_CPU_PLL_CFG_NINT_RESET 20 -+ -+#define AR934X_CPU_PLL_CFG_NFRAC_MSB 5 -+#define AR934X_CPU_PLL_CFG_NFRAC_LSB 0 -+#define AR934X_CPU_PLL_CFG_NFRAC_MASK 0x0000003f -+ -+#define AR934X_CPU_PLL_CFG_NFRAC_GET(x) \ -+ (((x) & AR934X_CPU_PLL_CFG_NFRAC_MASK) >> \ -+ AR934X_CPU_PLL_CFG_NFRAC_LSB) -+ -+#define AR934X_CPU_PLL_CFG_NFRAC_SET(x) \ -+ (((x) << AR934X_CPU_PLL_CFG_NFRAC_LSB) & \ -+ AR934X_CPU_PLL_CFG_NFRAC_MASK) -+ -+#define AR934X_DDR_PLL_CFG_REFDIV_MSB 20 -+#define AR934X_DDR_PLL_CFG_REFDIV_LSB 16 -+#define AR934X_DDR_PLL_CFG_REFDIV_MASK 0x001f0000 -+ -+#define AR934X_DDR_PLL_CFG_REFDIV_GET(x) \ -+ (((x) & AR934X_DDR_PLL_CFG_REFDIV_MASK) >> \ -+ AR934X_DDR_PLL_CFG_REFDIV_LSB) -+ -+#define AR934X_DDR_PLL_CFG_REFDIV_SET(x) \ -+ (((x) << AR934X_DDR_PLL_CFG_REFDIV_LSB) & \ -+ AR934X_DDR_PLL_CFG_REFDIV_MASK) -+ -+#define AR934X_DDR_PLL_CFG_REFDIV_RESET 2 -+ -+#define AR934X_DDR_PLL_CFG_NINT_MSB 15 -+#define AR934X_DDR_PLL_CFG_NINT_LSB 10 -+#define AR934X_DDR_PLL_CFG_NINT_MASK 0x0000fc00 -+ -+#define AR934X_DDR_PLL_CFG_NINT_GET(x) \ -+ (((x) & AR934X_DDR_PLL_CFG_NINT_MASK) >> \ -+ AR934X_DDR_PLL_CFG_NINT_LSB) -+ -+#define AR934X_DDR_PLL_CFG_NINT_SET(x) \ -+ (((x) << AR934X_DDR_PLL_CFG_NINT_LSB) & \ -+ AR934X_DDR_PLL_CFG_NINT_MASK) -+ -+#define AR934X_DDR_PLL_CFG_NINT_RESET 20 -+ -+#define AR934X_DDR_PLL_CFG_NFRAC_MSB 9 -+#define AR934X_DDR_PLL_CFG_NFRAC_LSB 0 -+#define AR934X_DDR_PLL_CFG_NFRAC_MASK 0x000003ff -+ -+#define AR934X_DDR_PLL_CFG_NFRAC_GET(x) \ -+ (((x) & AR934X_DDR_PLL_CFG_NFRAC_MASK) >> \ -+ AR934X_DDR_PLL_CFG_NFRAC_LSB) -+ -+#define AR934X_DDR_PLL_CFG_NFRAC_SET(x) \ -+ (((x) << AR934X_DDR_PLL_CFG_NFRAC_LSB) & \ -+ AR934X_DDR_PLL_CFG_NFRAC_MASK) -+ -+#define AR934X_DDR_PLL_CFG_NFRAC_RESET 512 -+ -+#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MSB 19 -+#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_LSB 15 -+#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK 0x000f8000 -+ -+#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_GET(x) \ -+ (((x) & AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK) >> \ -+ AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_LSB) -+ -+#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SET(x) \ -+ (((x) << AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_LSB) & \ -+ AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK) -+ -+#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_RESET 0 -+ -+#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MSB 14 -+#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_LSB 10 -+#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK 0x00007c00 -+ -+#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_GET(x) \ -+ (((x) & AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK) >> \ -+ AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_LSB) -+ -+#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SET(x) \ -+ (((x) << AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_LSB) & \ -+ AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK) -+ -+#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_RESET 0 -+ -+#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MSB 9 -+#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_LSB 5 -+#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK 0x000003e0 -+ -+#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_GET(x) \ -+ (((x) & AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK) >> \ -+ AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_LSB) -+ -+#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SET(x) \ -+ (((x) << AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_LSB) & \ -+ AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK) -+ -+#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_RESET 0 -+ -+#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MSB 24 -+#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_LSB 24 -+#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK 0x01000000 -+ -+#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_GET(x) \ -+ (((x) & AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK) >> \ -+ AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_LSB) -+ -+#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_SET(x) \ -+ (((x) << AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_LSB) & \ -+ AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK) -+ -+#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_RESET 1 -+ -+extern void __iomem *ar71xx_pll_base; -+ -+static inline void ar71xx_pll_wr(unsigned reg, u32 val) -+{ -+ __raw_writel(val, ar71xx_pll_base + reg); -+} -+ -+static inline u32 ar71xx_pll_rr(unsigned reg) -+{ -+ return __raw_readl(ar71xx_pll_base + reg); -+} -+ -+/* -+ * USB_CONFIG block -+ */ -+#define USB_CTRL_REG_FLADJ 0x00 -+#define USB_CTRL_REG_CONFIG 0x04 -+ -+extern void __iomem *ar71xx_usb_ctrl_base; -+ -+static inline void ar71xx_usb_ctrl_wr(unsigned reg, u32 val) -+{ -+ __raw_writel(val, ar71xx_usb_ctrl_base + reg); -+} -+ -+static inline u32 ar71xx_usb_ctrl_rr(unsigned reg) -+{ -+ return __raw_readl(ar71xx_usb_ctrl_base + reg); -+} -+ -+/* -+ * GPIO block -+ */ -+#define GPIO_REG_OE 0x00 -+#define GPIO_REG_IN 0x04 -+#define GPIO_REG_OUT 0x08 -+#define GPIO_REG_SET 0x0c -+#define GPIO_REG_CLEAR 0x10 -+#define GPIO_REG_INT_MODE 0x14 -+#define GPIO_REG_INT_TYPE 0x18 -+#define GPIO_REG_INT_POLARITY 0x1c -+#define GPIO_REG_INT_PENDING 0x20 -+#define GPIO_REG_INT_ENABLE 0x24 -+#define GPIO_REG_FUNC 0x28 -+ -+#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17) -+#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16) -+#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13) -+#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12) -+#define AR71XX_GPIO_FUNC_UART_EN BIT(8) -+#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4) -+#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0) -+ -+#define AR71XX_GPIO_COUNT 16 -+ -+#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19) -+#define AR724X_GPIO_FUNC_SPI_EN BIT(18) -+#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14) -+#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13) -+#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12) -+#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11) -+#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10) -+#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9) -+#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8) -+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) -+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) -+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) -+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) -+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) -+#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) -+#define AR724X_GPIO_FUNC_UART_EN BIT(1) -+#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0) -+ -+#define AR724X_GPIO_COUNT 18 -+ -+#define AR91XX_GPIO_FUNC_WMAC_LED_EN BIT(22) -+#define AR91XX_GPIO_FUNC_EXP_PORT_CS_EN BIT(21) -+#define AR91XX_GPIO_FUNC_I2S_REFCLKEN BIT(20) -+#define AR91XX_GPIO_FUNC_I2S_MCKEN BIT(19) -+#define AR91XX_GPIO_FUNC_I2S1_EN BIT(18) -+#define AR91XX_GPIO_FUNC_I2S0_EN BIT(17) -+#define AR91XX_GPIO_FUNC_SLIC_EN BIT(16) -+#define AR91XX_GPIO_FUNC_UART_RTSCTS_EN BIT(9) -+#define AR91XX_GPIO_FUNC_UART_EN BIT(8) -+#define AR91XX_GPIO_FUNC_USB_CLK_EN BIT(4) -+ -+#define AR91XX_GPIO_COUNT 22 -+ -+#define AR933X_GPIO_COUNT 30 -+ -+#define AR934X_GPIO_FUNC_SPI_CS_1_EN BIT(14) -+#define AR934X_GPIO_FUNC_SPI_CS_0_EN BIT(13) -+ -+#define AR934X_GPIO_COUNT 32 -+#define AR934X_GPIO_FUNC_DDR_DQOE_EN BIT(17) -+ -+extern void __iomem *ar71xx_gpio_base; -+ -+static inline void ar71xx_gpio_wr(unsigned reg, u32 value) -+{ -+ __raw_writel(value, ar71xx_gpio_base + reg); -+} -+ -+static inline u32 ar71xx_gpio_rr(unsigned reg) -+{ -+ return __raw_readl(ar71xx_gpio_base + reg); -+} -+ -+void ar71xx_gpio_init(void) __init; -+void ar71xx_gpio_function_enable(u32 mask); -+void ar71xx_gpio_function_disable(u32 mask); -+void ar71xx_gpio_function_setup(u32 set, u32 clear); -+ -+/* -+ * DDR_CTRL block -+ */ -+#define AR71XX_DDR_REG_PCI_WIN0 0x7c -+#define AR71XX_DDR_REG_PCI_WIN1 0x80 -+#define AR71XX_DDR_REG_PCI_WIN2 0x84 -+#define AR71XX_DDR_REG_PCI_WIN3 0x88 -+#define AR71XX_DDR_REG_PCI_WIN4 0x8c -+#define AR71XX_DDR_REG_PCI_WIN5 0x90 -+#define AR71XX_DDR_REG_PCI_WIN6 0x94 -+#define AR71XX_DDR_REG_PCI_WIN7 0x98 -+#define AR71XX_DDR_REG_FLUSH_GE0 0x9c -+#define AR71XX_DDR_REG_FLUSH_GE1 0xa0 -+#define AR71XX_DDR_REG_FLUSH_USB 0xa4 -+#define AR71XX_DDR_REG_FLUSH_PCI 0xa8 -+ -+#define AR724X_DDR_REG_FLUSH_GE0 0x7c -+#define AR724X_DDR_REG_FLUSH_GE1 0x80 -+#define AR724X_DDR_REG_FLUSH_USB 0x84 -+#define AR724X_DDR_REG_FLUSH_PCIE 0x88 -+ -+#define AR91XX_DDR_REG_FLUSH_GE0 0x7c -+#define AR91XX_DDR_REG_FLUSH_GE1 0x80 -+#define AR91XX_DDR_REG_FLUSH_USB 0x84 -+#define AR91XX_DDR_REG_FLUSH_WMAC 0x88 -+ -+#define AR933X_DDR_REG_FLUSH_GE0 0x7c -+#define AR933X_DDR_REG_FLUSH_GE1 0x80 -+#define AR933X_DDR_REG_FLUSH_USB 0x84 -+#define AR933X_DDR_REG_FLUSH_WMAC 0x88 -+ -+#define AR934X_DDR_REG_FLUSH_GE0 0x9c -+#define AR934X_DDR_REG_FLUSH_GE1 0xa0 -+#define AR934X_DDR_REG_FLUSH_USB 0xa4 -+#define AR934X_DDR_REG_FLUSH_PCIE 0xa8 -+ -+ -+#define PCI_WIN0_OFFS 0x10000000 -+#define PCI_WIN1_OFFS 0x11000000 -+#define PCI_WIN2_OFFS 0x12000000 -+#define PCI_WIN3_OFFS 0x13000000 -+#define PCI_WIN4_OFFS 0x14000000 -+#define PCI_WIN5_OFFS 0x15000000 -+#define PCI_WIN6_OFFS 0x16000000 -+#define PCI_WIN7_OFFS 0x07000000 -+ -+extern void __iomem *ar71xx_ddr_base; -+ -+static inline void ar71xx_ddr_wr(unsigned reg, u32 val) -+{ -+ __raw_writel(val, ar71xx_ddr_base + reg); -+} -+ -+static inline u32 ar71xx_ddr_rr(unsigned reg) -+{ -+ return __raw_readl(ar71xx_ddr_base + reg); -+} -+ -+void ar71xx_ddr_flush(u32 reg); -+ -+/* -+ * PCI block -+ */ -+#define AR71XX_PCI_CFG_BASE (AR71XX_PCI_MEM_BASE + PCI_WIN7_OFFS + 0x10000) -+#define AR71XX_PCI_CFG_SIZE 0x100 -+ -+#define PCI_REG_CRP_AD_CBE 0x00 -+#define PCI_REG_CRP_WRDATA 0x04 -+#define PCI_REG_CRP_RDDATA 0x08 -+#define PCI_REG_CFG_AD 0x0c -+#define PCI_REG_CFG_CBE 0x10 -+#define PCI_REG_CFG_WRDATA 0x14 -+#define PCI_REG_CFG_RDDATA 0x18 -+#define PCI_REG_PCI_ERR 0x1c -+#define PCI_REG_PCI_ERR_ADDR 0x20 -+#define PCI_REG_AHB_ERR 0x24 -+#define PCI_REG_AHB_ERR_ADDR 0x28 -+ -+#define PCI_CRP_CMD_WRITE 0x00010000 -+#define PCI_CRP_CMD_READ 0x00000000 -+#define PCI_CFG_CMD_READ 0x0000000a -+#define PCI_CFG_CMD_WRITE 0x0000000b -+ -+#define PCI_IDSEL_ADL_START 17 -+ -+#define AR724X_PCI_CFG_BASE (AR71XX_PCI_MEM_BASE + 0x4000000) -+#define AR724X_PCI_CFG_SIZE 0x1000 -+ -+#define AR724X_PCI_REG_APP 0x00 -+#define AR724X_PCI_REG_RESET 0x18 -+#define AR724X_PCI_REG_INT_STATUS 0x4c -+#define AR724X_PCI_REG_INT_MASK 0x50 -+ -+#define AR724X_PCI_APP_LTSSM_ENABLE BIT(0) -+#define AR724X_PCI_RESET_LINK_UP BIT(0) -+ -+#define AR724X_PCI_INT_DEV0 BIT(14) -+ -+/* -+ * RESET block -+ */ -+#define AR71XX_RESET_REG_TIMER 0x00 -+#define AR71XX_RESET_REG_TIMER_RELOAD 0x04 -+#define AR71XX_RESET_REG_WDOG_CTRL 0x08 -+#define AR71XX_RESET_REG_WDOG 0x0c -+#define AR71XX_RESET_REG_MISC_INT_STATUS 0x10 -+#define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14 -+#define AR71XX_RESET_REG_PCI_INT_STATUS 0x18 -+#define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c -+#define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20 -+#define AR71XX_RESET_REG_RESET_MODULE 0x24 -+#define AR71XX_RESET_REG_PERFC_CTRL 0x2c -+#define AR71XX_RESET_REG_PERFC0 0x30 -+#define AR71XX_RESET_REG_PERFC1 0x34 -+#define AR71XX_RESET_REG_REV_ID 0x90 -+ -+#define AR91XX_RESET_REG_GLOBAL_INT_STATUS 0x18 -+#define AR91XX_RESET_REG_RESET_MODULE 0x1c -+#define AR91XX_RESET_REG_PERF_CTRL 0x20 -+#define AR91XX_RESET_REG_PERFC0 0x24 -+#define AR91XX_RESET_REG_PERFC1 0x28 -+ -+#define AR724X_RESET_REG_RESET_MODULE 0x1c -+ -+#define AR933X_RESET_REG_RESET_MODULE 0x1c -+#define AR933X_RESET_REG_BOOTSTRAP 0xac -+#define AR933X_BOOTSTRAP_EEPBUSY BIT(4) -+#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) -+ -+#define AR934X_RESET_REG_RESET_MODULE 0x1c -+#define AR934X_RESET_REG_BOOTSTRAP 0xb0 -+/* 0 - 25MHz 1 - 40 MHz */ -+#define AR934X_REF_CLK_40 (1 << 4) -+ -+#define WDOG_CTRL_LAST_RESET BIT(31) -+#define WDOG_CTRL_ACTION_MASK 3 -+#define WDOG_CTRL_ACTION_NONE 0 /* no action */ -+#define WDOG_CTRL_ACTION_GPI 1 /* general purpose interrupt */ -+#define WDOG_CTRL_ACTION_NMI 2 /* NMI */ -+#define WDOG_CTRL_ACTION_FCR 3 /* full chip reset */ -+ -+#define MISC_INT_ENET_LINK BIT(12) -+#define MISC_INT_DDR_PERF BIT(11) -+#define MISC_INT_TIMER4 BIT(10) -+#define MISC_INT_TIMER3 BIT(9) -+#define MISC_INT_TIMER2 BIT(8) -+#define MISC_INT_DMA BIT(7) -+#define MISC_INT_OHCI BIT(6) -+#define MISC_INT_PERFC BIT(5) -+#define MISC_INT_WDOG BIT(4) -+#define MISC_INT_UART BIT(3) -+#define MISC_INT_GPIO BIT(2) -+#define MISC_INT_ERROR BIT(1) -+#define MISC_INT_TIMER BIT(0) -+ -+#define PCI_INT_CORE BIT(4) -+#define PCI_INT_DEV2 BIT(2) -+#define PCI_INT_DEV1 BIT(1) -+#define PCI_INT_DEV0 BIT(0) -+ -+#define RESET_MODULE_EXTERNAL BIT(28) -+#define RESET_MODULE_FULL_CHIP BIT(24) -+#define RESET_MODULE_AMBA2WMAC BIT(22) -+#define RESET_MODULE_CPU_NMI BIT(21) -+#define RESET_MODULE_CPU_COLD BIT(20) -+#define RESET_MODULE_DMA BIT(19) -+#define RESET_MODULE_SLIC BIT(18) -+#define RESET_MODULE_STEREO BIT(17) -+#define RESET_MODULE_DDR BIT(16) -+#define RESET_MODULE_GE1_MAC BIT(13) -+#define RESET_MODULE_GE1_PHY BIT(12) -+#define RESET_MODULE_USBSUS_OVERRIDE BIT(10) -+#define RESET_MODULE_GE0_MAC BIT(9) -+#define RESET_MODULE_GE0_PHY BIT(8) -+#define RESET_MODULE_USB_OHCI_DLL BIT(6) -+#define RESET_MODULE_USB_HOST BIT(5) -+#define RESET_MODULE_USB_PHY BIT(4) -+#define RESET_MODULE_USB_OHCI_DLL_7240 BIT(3) -+#define RESET_MODULE_PCI_BUS BIT(1) -+#define RESET_MODULE_PCI_CORE BIT(0) -+ -+#define AR724X_RESET_GE1_MDIO BIT(23) -+#define AR724X_RESET_GE0_MDIO BIT(22) -+#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10) -+#define AR724X_RESET_PCIE_PHY BIT(7) -+#define AR724X_RESET_PCIE BIT(6) -+#define AR724X_RESET_USB_HOST BIT(5) -+#define AR724X_RESET_USB_PHY BIT(4) -+#define AR724X_RESET_USBSUS_OVERRIDE BIT(3) -+ -+#define AR933X_RESET_WMAC BIT(11) -+#define AR933X_RESET_GE1_MDIO BIT(23) -+#define AR933X_RESET_GE0_MDIO BIT(22) -+#define AR933X_RESET_GE1_MAC BIT(13) -+#define AR933X_RESET_GE0_MAC BIT(9) -+ -+#define REV_ID_MAJOR_MASK 0xfff0 -+#define REV_ID_MAJOR_AR71XX 0x00a0 -+#define REV_ID_MAJOR_AR913X 0x00b0 -+#define REV_ID_MAJOR_AR7240 0x00c0 -+#define REV_ID_MAJOR_AR7241 0x0100 -+#define REV_ID_MAJOR_AR7242 0x1100 -+#define REV_ID_MAJOR_AR9330 0x0110 -+#define REV_ID_MAJOR_AR9331 0x1110 -+#define REV_ID_MAJOR_AR9341 0x0120 -+#define REV_ID_MAJOR_AR9342 0x1120 -+#define REV_ID_MAJOR_AR9344 0x2120 -+ -+#define AR71XX_REV_ID_MINOR_MASK 0x3 -+#define AR71XX_REV_ID_MINOR_AR7130 0x0 -+#define AR71XX_REV_ID_MINOR_AR7141 0x1 -+#define AR71XX_REV_ID_MINOR_AR7161 0x2 -+#define AR71XX_REV_ID_REVISION_MASK 0x3 -+#define AR71XX_REV_ID_REVISION_SHIFT 2 -+ -+#define AR91XX_REV_ID_MINOR_MASK 0x3 -+#define AR91XX_REV_ID_MINOR_AR9130 0x0 -+#define AR91XX_REV_ID_MINOR_AR9132 0x1 -+#define AR91XX_REV_ID_REVISION_MASK 0x3 -+#define AR91XX_REV_ID_REVISION_SHIFT 2 -+ -+#define AR724X_REV_ID_REVISION_MASK 0x3 -+ -+#define AR933X_REV_ID_REVISION_MASK 0xf -+ -+#define AR934X_REV_ID_REVISION_MASK 0xf -+ -+extern void __iomem *ar71xx_reset_base; -+ -+static inline void ar71xx_reset_wr(unsigned reg, u32 val) -+{ -+ __raw_writel(val, ar71xx_reset_base + reg); -+} -+ -+static inline u32 ar71xx_reset_rr(unsigned reg) -+{ -+ return __raw_readl(ar71xx_reset_base + reg); -+} -+ -+void ar71xx_device_stop(u32 mask); -+void ar71xx_device_start(u32 mask); -+int ar71xx_device_stopped(u32 mask); -+ -+/* -+ * SPI block -+ */ -+#define SPI_REG_FS 0x00 /* Function Select */ -+#define SPI_REG_CTRL 0x04 /* SPI Control */ -+#define SPI_REG_IOC 0x08 /* SPI I/O Control */ -+#define SPI_REG_RDS 0x0c /* Read Data Shift */ -+ -+#define SPI_FS_GPIO BIT(0) /* Enable GPIO mode */ -+ -+#define SPI_CTRL_RD BIT(6) /* Remap Disable */ -+#define SPI_CTRL_DIV_MASK 0x3f -+ -+#define SPI_IOC_DO BIT(0) /* Data Out pin */ -+#define SPI_IOC_CLK BIT(8) /* CLK pin */ -+#define SPI_IOC_CS(n) BIT(16 + (n)) -+#define SPI_IOC_CS0 SPI_IOC_CS(0) -+#define SPI_IOC_CS1 SPI_IOC_CS(1) -+#define SPI_IOC_CS2 SPI_IOC_CS(2) -+#define SPI_IOC_CS_ALL (SPI_IOC_CS0 | SPI_IOC_CS1 | SPI_IOC_CS2) -+ -+void ar71xx_flash_acquire(void); -+void ar71xx_flash_release(void); -+ -+/* -+ * MII_CTRL block -+ */ -+#define MII_REG_MII0_CTRL 0x00 -+#define MII_REG_MII1_CTRL 0x04 -+ -+#define MII0_CTRL_IF_GMII 0 -+#define MII0_CTRL_IF_MII 1 -+#define MII0_CTRL_IF_RGMII 2 -+#define MII0_CTRL_IF_RMII 3 -+ -+#define MII1_CTRL_IF_RGMII 0 -+#define MII1_CTRL_IF_RMII 1 -+ -+#endif /* __ASSEMBLER__ */ -+ -+#endif /* __ASM_MACH_AR71XX_H */ -diff -Nur linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/ar91xx_flash.h linux-2.6.39/arch/mips/include/asm/mach-ar71xx/ar91xx_flash.h ---- linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/ar91xx_flash.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/include/asm/mach-ar71xx/ar91xx_flash.h 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,26 @@ -+/* -+ * AR91xx parallel flash driver platform data definitions -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef __AR91XX_FLASH_H -+#define __AR91XX_FLASH_H -+ -+struct mtd_partition; -+ -+struct ar91xx_flash_platform_data { -+ unsigned int width; -+ u8 is_shared:1; -+#ifdef CONFIG_MTD_PARTITIONS -+ unsigned int nr_parts; -+ struct mtd_partition *parts; -+#endif -+}; -+ -+#endif /* __AR91XX_FLASH_H */ -diff -Nur linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/ar933x_uart.h linux-2.6.39/arch/mips/include/asm/mach-ar71xx/ar933x_uart.h ---- linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/ar933x_uart.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/include/asm/mach-ar71xx/ar933x_uart.h 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,67 @@ -+/* -+ * Atheros AR933X UART defines -+ * -+ * Copyright (C) 2011 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef __AR933X_UART_H -+#define __AR933X_UART_H -+ -+#define AR933X_UART_REGS_SIZE 20 -+#define AR933X_UART_FIFO_SIZE 16 -+ -+#define AR933X_UART_DATA_REG 0x00 -+#define AR933X_UART_CS_REG 0x04 -+#define AR933X_UART_CLOCK_REG 0x08 -+#define AR933X_UART_INT_REG 0x0c -+#define AR933X_UART_INT_EN_REG 0x10 -+ -+#define AR933X_UART_DATA_TX_RX_MASK 0xff -+#define AR933X_UART_DATA_RX_CSR BIT(8) -+#define AR933X_UART_DATA_TX_CSR BIT(9) -+ -+#define AR933X_UART_CS_PARITY_S 0 -+#define AR933X_UART_CS_PARITY_M 0x3 -+#define AR933X_UART_CS_PARITY_NONE 0 -+#define AR933X_UART_CS_PARITY_ODD 1 -+#define AR933X_UART_CS_PARITY_EVEN 2 -+#define AR933X_UART_CS_IF_MODE_S 2 -+#define AR933X_UART_CS_IF_MODE_M 0x3 -+#define AR933X_UART_CS_IF_MODE_NONE 0 -+#define AR933X_UART_CS_IF_MODE_DTE 1 -+#define AR933X_UART_CS_IF_MODE_DCE 2 -+#define AR933X_UART_CS_FLOW_CTRL_S 4 -+#define AR933X_UART_CS_FLOW_CTRL_M 0x3 -+#define AR933X_UART_CS_DMA_EN BIT(6) -+#define AR933X_UART_CS_TX_READY_ORIDE BIT(7) -+#define AR933X_UART_CS_RX_READY_ORIDE BIT(8) -+#define AR933X_UART_CS_TX_READY BIT(9) -+#define AR933X_UART_CS_RX_BREAK BIT(10) -+#define AR933X_UART_CS_TX_BREAK BIT(11) -+#define AR933X_UART_CS_HOST_INT BIT(12) -+#define AR933X_UART_CS_HOST_INT_EN BIT(13) -+#define AR933X_UART_CS_TX_BUSY BIT(14) -+#define AR933X_UART_CS_RX_BUSY BIT(15) -+ -+#define AR933X_UART_CLOCK_STEP_M 0xffff -+#define AR933X_UART_CLOCK_SCALE_M 0xfff -+#define AR933X_UART_CLOCK_SCALE_S 16 -+#define AR933X_UART_CLOCK_STEP_M 0xffff -+ -+#define AR933X_UART_INT_RX_VALID BIT(0) -+#define AR933X_UART_INT_TX_READY BIT(1) -+#define AR933X_UART_INT_RX_FRAMING_ERR BIT(2) -+#define AR933X_UART_INT_RX_OFLOW_ERR BIT(3) -+#define AR933X_UART_INT_TX_OFLOW_ERR BIT(4) -+#define AR933X_UART_INT_RX_PARITY_ERR BIT(5) -+#define AR933X_UART_INT_RX_BREAK_ON BIT(6) -+#define AR933X_UART_INT_RX_BREAK_OFF BIT(7) -+#define AR933X_UART_INT_RX_FULL BIT(8) -+#define AR933X_UART_INT_TX_EMPTY BIT(9) -+#define AR933X_UART_INT_ALLINTS 0x3ff -+ -+#endif /* __AR933X_UART_H */ -diff -Nur linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/ar933x_uart_platform.h linux-2.6.39/arch/mips/include/asm/mach-ar71xx/ar933x_uart_platform.h ---- linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/ar933x_uart_platform.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/include/asm/mach-ar71xx/ar933x_uart_platform.h 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,18 @@ -+/* -+ * Platform data definition for Atheros AR933X UART -+ * -+ * Copyright (C) 2011 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR933X_UART_PLATFORM_H -+#define _AR933X_UART_PLATFORM_H -+ -+struct ar933x_uart_platform_data { -+ unsigned uartclk; -+}; -+ -+#endif /* _AR933X_UART_PLATFORM_H */ -diff -Nur linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/cpu-feature-overrides.h linux-2.6.39/arch/mips/include/asm/mach-ar71xx/cpu-feature-overrides.h ---- linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/cpu-feature-overrides.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/include/asm/mach-ar71xx/cpu-feature-overrides.h 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,56 @@ -+/* -+ * Atheros AR71xx specific CPU feature overrides -+ * -+ * Copyright (C) 2008 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This file was derived from: include/asm-mips/cpu-features.h -+ * Copyright (C) 2003, 2004 Ralf Baechle -+ * Copyright (C) 2004 Maciej W. Rozycki -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ */ -+#ifndef __ASM_MACH_AR71XX_CPU_FEATURE_OVERRIDES_H -+#define __ASM_MACH_AR71XX_CPU_FEATURE_OVERRIDES_H -+ -+#define cpu_has_tlb 1 -+#define cpu_has_4kex 1 -+#define cpu_has_3k_cache 0 -+#define cpu_has_4k_cache 1 -+#define cpu_has_tx39_cache 0 -+#define cpu_has_sb1_cache 0 -+#define cpu_has_fpu 0 -+#define cpu_has_32fpr 0 -+#define cpu_has_counter 1 -+#define cpu_has_watch 1 -+#define cpu_has_divec 1 -+ -+#define cpu_has_prefetch 1 -+#define cpu_has_ejtag 1 -+#define cpu_has_llsc 1 -+ -+#define cpu_has_mips16 1 -+#define cpu_has_mdmx 0 -+#define cpu_has_mips3d 0 -+#define cpu_has_smartmips 0 -+ -+#define cpu_has_mips32r1 1 -+#define cpu_has_mips32r2 1 -+#define cpu_has_mips64r1 0 -+#define cpu_has_mips64r2 0 -+ -+#define cpu_has_dsp 0 -+#define cpu_has_mipsmt 0 -+ -+#define cpu_has_64bits 0 -+#define cpu_has_64bit_zero_reg 0 -+#define cpu_has_64bit_gp_regs 0 -+#define cpu_has_64bit_addresses 0 -+ -+#define cpu_dcache_line_size() 32 -+#define cpu_icache_line_size() 32 -+ -+#endif /* __ASM_MACH_AR71XX_CPU_FEATURE_OVERRIDES_H */ -diff -Nur linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/gpio.h linux-2.6.39/arch/mips/include/asm/mach-ar71xx/gpio.h ---- linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/gpio.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/include/asm/mach-ar71xx/gpio.h 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,53 @@ -+/* -+ * Atheros AR71xx GPIO API definitions -+ * -+ * Copyright (C) 2008 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ */ -+ -+#ifndef __ASM_MACH_AR71XX_GPIO_H -+#define __ASM_MACH_AR71XX_GPIO_H -+ -+#define ARCH_NR_GPIOS 64 -+#include -+ -+#include -+ -+extern unsigned long ar71xx_gpio_count; -+extern void __ar71xx_gpio_set_value(unsigned gpio, int value); -+extern int __ar71xx_gpio_get_value(unsigned gpio); -+ -+static inline int gpio_to_irq(unsigned gpio) -+{ -+ return AR71XX_GPIO_IRQ(gpio); -+} -+ -+static inline int irq_to_gpio(unsigned irq) -+{ -+ return irq - AR71XX_GPIO_IRQ_BASE; -+} -+ -+static inline int gpio_get_value(unsigned gpio) -+{ -+ if (gpio < ar71xx_gpio_count) -+ return __ar71xx_gpio_get_value(gpio); -+ -+ return __gpio_get_value(gpio); -+} -+ -+static inline void gpio_set_value(unsigned gpio, int value) -+{ -+ if (gpio < ar71xx_gpio_count) -+ __ar71xx_gpio_set_value(gpio, value); -+ else -+ __gpio_set_value(gpio, value); -+} -+ -+#define gpio_cansleep __gpio_cansleep -+ -+#endif /* __ASM_MACH_AR71XX_GPIO_H */ -diff -Nur linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/irq.h linux-2.6.39/arch/mips/include/asm/mach-ar71xx/irq.h ---- linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/irq.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/include/asm/mach-ar71xx/irq.h 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,17 @@ -+/* -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+#ifndef __ASM_MACH_AR71XX_IRQ_H -+#define __ASM_MACH_AR71XX_IRQ_H -+ -+#define MIPS_CPU_IRQ_BASE 0 -+#define NR_IRQS 80 -+ -+#include_next -+ -+#endif /* __ASM_MACH_AR71XX_IRQ_H */ -diff -Nur linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/kernel-entry-init.h linux-2.6.39/arch/mips/include/asm/mach-ar71xx/kernel-entry-init.h ---- linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/kernel-entry-init.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/include/asm/mach-ar71xx/kernel-entry-init.h 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,32 @@ -+/* -+ * Atheros AR71xx specific kernel entry setup -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ */ -+#ifndef __ASM_MACH_AR71XX_KERNEL_ENTRY_H -+#define __ASM_MACH_AR71XX_KERNEL_ENTRY_H -+ -+ /* -+ * Some bootloaders set the 'Kseg0 coherency algorithm' to -+ * 'Cacheable, noncoherent, write-through, no write allocate' -+ * and this cause performance issues. Let's go and change it to -+ * 'Cacheable, noncoherent, write-back, write allocate' -+ */ -+ .macro kernel_entry_setup -+ mfc0 t0, CP0_CONFIG -+ li t1, ~CONF_CM_CMASK -+ and t0, t1 -+ ori t0, CONF_CM_CACHABLE_NONCOHERENT -+ mtc0 t0, CP0_CONFIG -+ nop -+ .endm -+ -+ .macro smp_slave_setup -+ .endm -+ -+#endif /* __ASM_MACH_AR71XX_KERNEL_ENTRY_H */ -diff -Nur linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/mach-rb750.h linux-2.6.39/arch/mips/include/asm/mach-ar71xx/mach-rb750.h ---- linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/mach-rb750.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/include/asm/mach-ar71xx/mach-rb750.h 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,66 @@ -+/* -+ * MikroTik RouterBOARD 750 definitions -+ * -+ * Copyright (C) 2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+#ifndef _MACH_RB750_H -+#define _MACH_RB750_H -+ -+#include -+ -+#define RB750_GPIO_LVC573_LE 0 /* Latch enable on LVC573 */ -+#define RB750_GPIO_NAND_IO0 1 /* NAND I/O 0 */ -+#define RB750_GPIO_NAND_IO1 2 /* NAND I/O 1 */ -+#define RB750_GPIO_NAND_IO2 3 /* NAND I/O 2 */ -+#define RB750_GPIO_NAND_IO3 4 /* NAND I/O 3 */ -+#define RB750_GPIO_NAND_IO4 5 /* NAND I/O 4 */ -+#define RB750_GPIO_NAND_IO5 6 /* NAND I/O 5 */ -+#define RB750_GPIO_NAND_IO6 7 /* NAND I/O 6 */ -+#define RB750_GPIO_NAND_IO7 8 /* NAND I/O 7 */ -+#define RB750_GPIO_NAND_NCE 11 /* NAND Chip Enable (active low) */ -+#define RB750_GPIO_NAND_RDY 12 /* NAND Ready */ -+#define RB750_GPIO_NAND_CLE 14 /* NAND Command Latch Enable */ -+#define RB750_GPIO_NAND_ALE 15 /* NAND Address Latch Enable */ -+#define RB750_GPIO_NAND_NRE 16 /* NAND Read Enable (active low) */ -+#define RB750_GPIO_NAND_NWE 17 /* NAND Write Enable (active low) */ -+ -+#define RB750_GPIO_BTN_RESET 1 -+#define RB750_GPIO_SPI_CS0 2 -+#define RB750_GPIO_LED_ACT 12 -+#define RB750_GPIO_LED_PORT1 13 -+#define RB750_GPIO_LED_PORT2 14 -+#define RB750_GPIO_LED_PORT3 15 -+#define RB750_GPIO_LED_PORT4 16 -+#define RB750_GPIO_LED_PORT5 17 -+ -+#define RB750_LED_ACT BIT(RB750_GPIO_LED_ACT) -+#define RB750_LED_PORT1 BIT(RB750_GPIO_LED_PORT1) -+#define RB750_LED_PORT2 BIT(RB750_GPIO_LED_PORT2) -+#define RB750_LED_PORT3 BIT(RB750_GPIO_LED_PORT3) -+#define RB750_LED_PORT4 BIT(RB750_GPIO_LED_PORT4) -+#define RB750_LED_PORT5 BIT(RB750_GPIO_LED_PORT5) -+ -+#define RB750_LVC573_LE BIT(RB750_GPIO_LVC573_LE) -+ -+#define RB750_LED_BITS (RB750_LED_PORT1 | RB750_LED_PORT2 | RB750_LED_PORT3 | \ -+ RB750_LED_PORT4 | RB750_LED_PORT5 | RB750_LED_ACT) -+ -+struct rb750_led_data { -+ char *name; -+ char *default_trigger; -+ u32 mask; -+ int active_low; -+}; -+ -+struct rb750_led_platform_data { -+ int num_leds; -+ struct rb750_led_data *leds; -+}; -+ -+int rb750_latch_change(u32 mask_clr, u32 mask_set); -+ -+#endif /* _MACH_RB750_H */ -\ No newline at end of file -diff -Nur linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/mangle-port.h linux-2.6.39/arch/mips/include/asm/mach-ar71xx/mangle-port.h ---- linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/mangle-port.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/include/asm/mach-ar71xx/mangle-port.h 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,45 @@ -+/* -+ * Copyright (C) 2008 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This file was derived from: inlude/asm-mips/mach-generic/mangle-port.h -+ * Copyright (C) 2003, 2004 Ralf Baechle -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef __ASM_MACH_AR71XX_MANGLE_PORT_H -+#define __ASM_MACH_AR71XX_MANGLE_PORT_H -+ -+#define __swizzle_addr_b(port) ((port) ^ 3) -+#define __swizzle_addr_w(port) ((port) ^ 2) -+#define __swizzle_addr_l(port) (port) -+#define __swizzle_addr_q(port) (port) -+ -+#if defined(CONFIG_SWAP_IO_SPACE) -+ -+# define ioswabb(a, x) (x) -+# define __mem_ioswabb(a, x) (x) -+# define ioswabw(a, x) le16_to_cpu(x) -+# define __mem_ioswabw(a, x) (x) -+# define ioswabl(a, x) le32_to_cpu(x) -+# define __mem_ioswabl(a, x) (x) -+# define ioswabq(a, x) le64_to_cpu(x) -+# define __mem_ioswabq(a, x) (x) -+ -+#else -+ -+# define ioswabb(a, x) (x) -+# define __mem_ioswabb(a, x) (x) -+# define ioswabw(a, x) (x) -+# define __mem_ioswabw(a, x) cpu_to_le16(x) -+# define ioswabl(a, x) (x) -+# define __mem_ioswabl(a, x) cpu_to_le32(x) -+# define ioswabq(a, x) (x) -+# define __mem_ioswabq(a, x) cpu_to_le64(x) -+ -+#endif -+ -+#endif /* __ASM_MACH_AR71XX_MANGLE_PORT_H */ -diff -Nur linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/pci.h linux-2.6.39/arch/mips/include/asm/mach-ar71xx/pci.h ---- linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/pci.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/include/asm/mach-ar71xx/pci.h 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,46 @@ -+/* -+ * Atheros AR71xx SoC specific PCI definitions -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef __ASM_MACH_AR71XX_PCI_H -+#define __ASM_MACH_AR71XX_PCI_H -+ -+struct pci_dev; -+ -+struct ar71xx_pci_irq { -+ int irq; -+ u8 slot; -+ u8 pin; -+}; -+ -+#ifdef CONFIG_PCI -+extern int (*ar71xx_pci_plat_dev_init)(struct pci_dev *dev); -+extern unsigned ar71xx_pci_nr_irqs __initdata; -+extern struct ar71xx_pci_irq *ar71xx_pci_irq_map __initdata; -+ -+int ar71xx_pcibios_map_irq(const struct pci_dev *dev, -+ uint8_t slot, uint8_t pin) __init; -+int ar71xx_pcibios_init(void) __init; -+ -+int ar71xx_pci_be_handler(int is_fixup); -+ -+int ar724x_pcibios_map_irq(const struct pci_dev *dev, -+ uint8_t slot, uint8_t pin) __init; -+int ar724x_pcibios_init(void) __init; -+ -+int ar71xx_pci_init(unsigned nr_irqs, struct ar71xx_pci_irq *map) __init; -+#else -+static inline int ar71xx_pci_init(unsigned nr_irqs, struct ar71xx_pci_irq *map) -+{ -+ return 0; -+} -+#endif -+ -+#endif /* __ASM_MACH_AR71XX_PCI_H */ -diff -Nur linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/platform.h linux-2.6.39/arch/mips/include/asm/mach-ar71xx/platform.h ---- linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/platform.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/include/asm/mach-ar71xx/platform.h 2011-08-24 18:17:23.000000000 +0200 -@@ -0,0 +1,63 @@ -+/* -+ * Atheros AR71xx SoC specific platform data definitions -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef __ASM_MACH_AR71XX_PLATFORM_H -+#define __ASM_MACH_AR71XX_PLATFORM_H -+ -+#include -+#include -+#include -+#include -+ -+struct ag71xx_platform_data { -+ phy_interface_t phy_if_mode; -+ u32 phy_mask; -+ int speed; -+ int duplex; -+ u32 reset_bit; -+ u32 mii_if; -+ u8 mac_addr[ETH_ALEN]; -+ struct device *mii_bus_dev; -+ -+ u8 has_gbit:1; -+ u8 is_ar91xx:1; -+ u8 is_ar7240:1; -+ u8 is_ar724x:1; -+ u8 has_ar8216:1; -+ u8 has_ar7240_switch:1; -+ -+ void (*ddr_flush)(void); -+ void (*set_pll)(int speed); -+ -+ u32 fifo_cfg1; -+ u32 fifo_cfg2; -+ u32 fifo_cfg3; -+}; -+ -+struct ag71xx_mdio_platform_data { -+ u32 phy_mask; -+ int is_ar7240; -+}; -+ -+struct ar71xx_ehci_platform_data { -+ u8 is_ar91xx; -+}; -+ -+struct ar71xx_spi_platform_data { -+ unsigned bus_num; -+ unsigned num_chipselect; -+ u32 (*get_ioc_base)(u8 chip_select, int cs_high, int is_on); -+}; -+ -+#define AR71XX_SPI_CS_INACTIVE 0 -+#define AR71XX_SPI_CS_ACTIVE 1 -+ -+#endif /* __ASM_MACH_AR71XX_PLATFORM_H */ -diff -Nur linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/rb4xx_cpld.h linux-2.6.39/arch/mips/include/asm/mach-ar71xx/rb4xx_cpld.h ---- linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/rb4xx_cpld.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/include/asm/mach-ar71xx/rb4xx_cpld.h 2011-08-24 18:17:24.000000000 +0200 -@@ -0,0 +1,48 @@ -+/* -+ * SPI driver definitions for the CPLD chip on the Mikrotik RB4xx boards -+ * -+ * Copyright (C) 2010 Gabor Juhos -+ * -+ * This file was based on the patches for Linux 2.6.27.39 published by -+ * MikroTik for their RouterBoard 4xx series devices. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#define CPLD_GPIO_nLED1 0 -+#define CPLD_GPIO_nLED2 1 -+#define CPLD_GPIO_nLED3 2 -+#define CPLD_GPIO_nLED4 3 -+#define CPLD_GPIO_FAN 4 -+#define CPLD_GPIO_ALE 5 -+#define CPLD_GPIO_CLE 6 -+#define CPLD_GPIO_nCE 7 -+#define CPLD_GPIO_nLED5 8 -+ -+#define CPLD_NUM_GPIOS 9 -+ -+#define CPLD_CFG_nLED1 BIT(CPLD_GPIO_nLED1) -+#define CPLD_CFG_nLED2 BIT(CPLD_GPIO_nLED2) -+#define CPLD_CFG_nLED3 BIT(CPLD_GPIO_nLED3) -+#define CPLD_CFG_nLED4 BIT(CPLD_GPIO_nLED4) -+#define CPLD_CFG_FAN BIT(CPLD_GPIO_FAN) -+#define CPLD_CFG_ALE BIT(CPLD_GPIO_ALE) -+#define CPLD_CFG_CLE BIT(CPLD_GPIO_CLE) -+#define CPLD_CFG_nCE BIT(CPLD_GPIO_nCE) -+#define CPLD_CFG_nLED5 BIT(CPLD_GPIO_nLED5) -+ -+struct rb4xx_cpld_platform_data { -+ unsigned gpio_base; -+}; -+ -+extern int rb4xx_cpld_change_cfg(unsigned mask, unsigned value); -+extern int rb4xx_cpld_read(unsigned char *rx_buf, -+ const unsigned char *verify_buf, -+ unsigned cnt); -+extern int rb4xx_cpld_read_from(unsigned addr, -+ unsigned char *rx_buf, -+ const unsigned char *verify_buf, -+ unsigned cnt); -+extern int rb4xx_cpld_write(const unsigned char *buf, unsigned count); -diff -Nur linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/war.h linux-2.6.39/arch/mips/include/asm/mach-ar71xx/war.h ---- linux-2.6.39.orig/arch/mips/include/asm/mach-ar71xx/war.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/include/asm/mach-ar71xx/war.h 2011-08-24 18:17:24.000000000 +0200 -@@ -0,0 +1,25 @@ -+/* -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle -+ */ -+#ifndef __ASM_MACH_AR71XX_WAR_H -+#define __ASM_MACH_AR71XX_WAR_H -+ -+#define R4600_V1_INDEX_ICACHEOP_WAR 0 -+#define R4600_V1_HIT_CACHEOP_WAR 0 -+#define R4600_V2_HIT_CACHEOP_WAR 0 -+#define R5432_CP0_INTERRUPT_WAR 0 -+#define BCM1250_M3_WAR 0 -+#define SIBYTE_1956_WAR 0 -+#define MIPS4K_ICACHE_REFILL_WAR 0 -+#define MIPS_CACHE_SYNC_WAR 0 -+#define TX49XX_ICACHE_INDEX_INV_WAR 0 -+#define RM9000_CDEX_SMP_WAR 0 -+#define ICACHE_REFILLS_WORKAROUND_WAR 0 -+#define R10000_LLSC_WAR 0 -+#define MIPS34K_MISSED_ITLB_WAR 0 -+ -+#endif /* __ASM_MACH_AR71XX_WAR_H */ -diff -Nur linux-2.6.39.orig/arch/mips/include/asm/time.h linux-2.6.39/arch/mips/include/asm/time.h ---- linux-2.6.39.orig/arch/mips/include/asm/time.h 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/arch/mips/include/asm/time.h 2011-08-24 18:17:24.000000000 +0200 -@@ -52,6 +52,7 @@ - */ - #ifdef CONFIG_CEVT_R4K_LIB - extern unsigned int __weak get_c0_compare_int(void); -+extern unsigned int __weak get_c0_compare_irq(void); - extern int r4k_clockevent_init(void); - #endif - -diff -Nur linux-2.6.39.orig/arch/mips/kernel/traps.c linux-2.6.39/arch/mips/kernel/traps.c ---- linux-2.6.39.orig/arch/mips/kernel/traps.c 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/arch/mips/kernel/traps.c 2011-08-24 18:17:24.000000000 +0200 -@@ -54,6 +54,7 @@ - #include - #include - #include -+#include - - extern void check_wait(void); - extern asmlinkage void r4k_wait(void); -@@ -1576,6 +1577,8 @@ - if (cpu_has_mips_r2) { - cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP; - cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7; -+ if (get_c0_compare_irq) -+ cp0_compare_irq = get_c0_compare_irq(); - cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7; - if (cp0_perfcount_irq == cp0_compare_irq) - cp0_perfcount_irq = -1; -diff -Nur linux-2.6.39.orig/arch/mips/pci/Makefile linux-2.6.39/arch/mips/pci/Makefile ---- linux-2.6.39.orig/arch/mips/pci/Makefile 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/arch/mips/pci/Makefile 2011-08-24 18:17:24.000000000 +0200 -@@ -18,6 +18,7 @@ - obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o - obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \ - ops-bcm63xx.o -+obj-$(CONFIG_ATHEROS_AR71XX) += pci-ar71xx.o pci-ar724x.o - - # - # These are still pretty much in the old state, watch, go blind. -diff -Nur linux-2.6.39.orig/arch/mips/pci/pci-ar71xx.c linux-2.6.39/arch/mips/pci/pci-ar71xx.c ---- linux-2.6.39.orig/arch/mips/pci/pci-ar71xx.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/pci/pci-ar71xx.c 2011-08-24 18:17:24.000000000 +0200 -@@ -0,0 +1,415 @@ -+/* -+ * Atheros AR71xx PCI host controller driver -+ * -+ * Copyright (C) 2008-2010 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#undef DEBUG -+#ifdef DEBUG -+#define DBG(fmt, args...) printk(KERN_DEBUG fmt, ## args) -+#else -+#define DBG(fmt, args...) -+#endif -+ -+#define AR71XX_PCI_DELAY 100 /* msecs */ -+ -+#if 0 -+#define PCI_IDSEL_BASE PCI_IDSEL_ADL_START -+#else -+#define PCI_IDSEL_BASE 0 -+#endif -+ -+static void __iomem *ar71xx_pcicfg_base; -+static DEFINE_SPINLOCK(ar71xx_pci_lock); -+static int ar71xx_pci_fixup_enable; -+ -+static inline void ar71xx_pci_delay(void) -+{ -+ mdelay(AR71XX_PCI_DELAY); -+} -+ -+/* Byte lane enable bits */ -+static u8 ble_table[4][4] = { -+ {0x0, 0xf, 0xf, 0xf}, -+ {0xe, 0xd, 0xb, 0x7}, -+ {0xc, 0xf, 0x3, 0xf}, -+ {0xf, 0xf, 0xf, 0xf}, -+}; -+ -+static inline u32 ar71xx_pci_get_ble(int where, int size, int local) -+{ -+ u32 t; -+ -+ t = ble_table[size & 3][where & 3]; -+ BUG_ON(t == 0xf); -+ t <<= (local) ? 20 : 4; -+ return t; -+} -+ -+static inline u32 ar71xx_pci_bus_addr(struct pci_bus *bus, unsigned int devfn, -+ int where) -+{ -+ u32 ret; -+ -+ if (!bus->number) { -+ /* type 0 */ -+ ret = (1 << (PCI_IDSEL_BASE + PCI_SLOT(devfn))) -+ | (PCI_FUNC(devfn) << 8) | (where & ~3); -+ } else { -+ /* type 1 */ -+ ret = (bus->number << 16) | (PCI_SLOT(devfn) << 11) -+ | (PCI_FUNC(devfn) << 8) | (where & ~3) | 1; -+ } -+ -+ return ret; -+} -+ -+int ar71xx_pci_be_handler(int is_fixup) -+{ -+ void __iomem *base = ar71xx_pcicfg_base; -+ u32 pci_err; -+ u32 ahb_err; -+ -+ pci_err = __raw_readl(base + PCI_REG_PCI_ERR) & 3; -+ if (pci_err) { -+ if (!is_fixup) -+ printk(KERN_ALERT "PCI error %d at PCI addr 0x%x\n", -+ pci_err, -+ __raw_readl(base + PCI_REG_PCI_ERR_ADDR)); -+ -+ __raw_writel(pci_err, base + PCI_REG_PCI_ERR); -+ } -+ -+ ahb_err = __raw_readl(base + PCI_REG_AHB_ERR) & 1; -+ if (ahb_err) { -+ if (!is_fixup) -+ printk(KERN_ALERT "AHB error at AHB address 0x%x\n", -+ __raw_readl(base + PCI_REG_AHB_ERR_ADDR)); -+ -+ __raw_writel(ahb_err, base + PCI_REG_AHB_ERR); -+ } -+ -+ return (ahb_err | pci_err) ? 1 : 0; -+} -+ -+static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus, -+ unsigned int devfn, int where, int size, u32 cmd) -+{ -+ void __iomem *base = ar71xx_pcicfg_base; -+ u32 addr; -+ -+ addr = ar71xx_pci_bus_addr(bus, devfn, where); -+ -+ DBG("PCI: set cfgaddr: %02x:%02x.%01x/%02x:%01d, addr=%08x\n", -+ bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), -+ where, size, addr); -+ -+ __raw_writel(addr, base + PCI_REG_CFG_AD); -+ __raw_writel(cmd | ar71xx_pci_get_ble(where, size, 0), -+ base + PCI_REG_CFG_CBE); -+ -+ return ar71xx_pci_be_handler(1); -+} -+ -+static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, -+ int where, int size, u32 *value) -+{ -+ void __iomem *base = ar71xx_pcicfg_base; -+ static u32 mask[8] = {0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0}; -+ unsigned long flags; -+ u32 data; -+ int retry = 0; -+ int ret; -+ -+ ret = PCIBIOS_SUCCESSFUL; -+ -+ DBG("PCI: read config: %02x:%02x.%01x/%02x:%01d\n", bus->number, -+ PCI_SLOT(devfn), PCI_FUNC(devfn), where, size); -+ -+retry: -+ spin_lock_irqsave(&ar71xx_pci_lock, flags); -+ -+ if (bus->number == 0 && devfn == 0) { -+ u32 t; -+ -+ t = PCI_CRP_CMD_READ | (where & ~3); -+ -+ __raw_writel(t, base + PCI_REG_CRP_AD_CBE); -+ data = __raw_readl(base + PCI_REG_CRP_RDDATA); -+ -+ DBG("PCI: rd local cfg, ad_cbe:%08x, data:%08x\n", t, data); -+ -+ } else { -+ int err; -+ -+ err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size, -+ PCI_CFG_CMD_READ); -+ -+ if (err == 0) { -+ data = __raw_readl(base + PCI_REG_CFG_RDDATA); -+ } else { -+ ret = PCIBIOS_DEVICE_NOT_FOUND; -+ data = ~0; -+ } -+ } -+ -+ spin_unlock_irqrestore(&ar71xx_pci_lock, flags); -+ -+ DBG("PCI: read config: data=%08x raw=%08x\n", -+ (data >> (8 * (where & 3))) & mask[size & 7], data); -+ -+ *value = (data >> (8 * (where & 3))) & mask[size & 7]; -+ -+ /* -+ * PCI controller bug: sometimes reads to the PCI_COMMAND register -+ * return 0xffff, even though the PCI trace shows the correct value. -+ * Work around this by retrying reads to this register -+ */ -+ if (where == PCI_COMMAND && (*value & 0xffff) == 0xffff && retry++ < 2) -+ goto retry; -+ -+ return ret; -+} -+ -+static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn, -+ int where, int size, u32 value) -+{ -+ void __iomem *base = ar71xx_pcicfg_base; -+ unsigned long flags; -+ int ret; -+ -+ DBG("PCI: write config: %02x:%02x.%01x/%02x:%01d value=%08x\n", -+ bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), -+ where, size, value); -+ -+ value = value << (8 * (where & 3)); -+ ret = PCIBIOS_SUCCESSFUL; -+ -+ spin_lock_irqsave(&ar71xx_pci_lock, flags); -+ if (bus->number == 0 && devfn == 0) { -+ u32 t; -+ -+ t = PCI_CRP_CMD_WRITE | (where & ~3); -+ t |= ar71xx_pci_get_ble(where, size, 1); -+ -+ DBG("PCI: wr local cfg, ad_cbe:%08x, value:%08x\n", t, value); -+ -+ __raw_writel(t, base + PCI_REG_CRP_AD_CBE); -+ __raw_writel(value, base + PCI_REG_CRP_WRDATA); -+ } else { -+ int err; -+ -+ err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size, -+ PCI_CFG_CMD_WRITE); -+ -+ if (err == 0) -+ __raw_writel(value, base + PCI_REG_CFG_WRDATA); -+ else -+ ret = PCIBIOS_DEVICE_NOT_FOUND; -+ } -+ spin_unlock_irqrestore(&ar71xx_pci_lock, flags); -+ -+ return ret; -+} -+ -+static void ar71xx_pci_fixup(struct pci_dev *dev) -+{ -+ u32 t; -+ -+ if (!ar71xx_pci_fixup_enable) -+ return; -+ -+ if (dev->bus->number != 0 || dev->devfn != 0) -+ return; -+ -+ DBG("PCI: fixup host controller %s (%04x:%04x)\n", pci_name(dev), -+ dev->vendor, dev->device); -+ -+ /* setup COMMAND register */ -+ t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE -+ | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK; -+ -+ pci_write_config_word(dev, PCI_COMMAND, t); -+} -+DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ar71xx_pci_fixup); -+ -+int __init ar71xx_pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, -+ uint8_t pin) -+{ -+ int irq = -1; -+ int i; -+ -+ slot -= PCI_IDSEL_ADL_START - PCI_IDSEL_BASE; -+ -+ for (i = 0; i < ar71xx_pci_nr_irqs; i++) { -+ struct ar71xx_pci_irq *entry; -+ -+ entry = &ar71xx_pci_irq_map[i]; -+ if (entry->slot == slot && entry->pin == pin) { -+ irq = entry->irq; -+ break; -+ } -+ } -+ -+ if (irq < 0) { -+ printk(KERN_ALERT "PCI: no irq found for pin%u@%s\n", -+ pin, pci_name((struct pci_dev *)dev)); -+ } else { -+ printk(KERN_INFO "PCI: mapping irq %d to pin%u@%s\n", -+ irq, pin, pci_name((struct pci_dev *)dev)); -+ } -+ -+ return irq; -+} -+ -+static struct pci_ops ar71xx_pci_ops = { -+ .read = ar71xx_pci_read_config, -+ .write = ar71xx_pci_write_config, -+}; -+ -+static struct resource ar71xx_pci_io_resource = { -+ .name = "PCI IO space", -+ .start = 0, -+ .end = 0, -+ .flags = IORESOURCE_IO, -+}; -+ -+static struct resource ar71xx_pci_mem_resource = { -+ .name = "PCI memory space", -+ .start = AR71XX_PCI_MEM_BASE, -+ .end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1, -+ .flags = IORESOURCE_MEM -+}; -+ -+static struct pci_controller ar71xx_pci_controller = { -+ .pci_ops = &ar71xx_pci_ops, -+ .mem_resource = &ar71xx_pci_mem_resource, -+ .io_resource = &ar71xx_pci_io_resource, -+}; -+ -+static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc) -+{ -+ void __iomem *base = ar71xx_reset_base; -+ u32 pending; -+ -+ pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) & -+ __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); -+ -+ if (pending & PCI_INT_DEV0) -+ generic_handle_irq(AR71XX_PCI_IRQ_DEV0); -+ -+ else if (pending & PCI_INT_DEV1) -+ generic_handle_irq(AR71XX_PCI_IRQ_DEV1); -+ -+ else if (pending & PCI_INT_DEV2) -+ generic_handle_irq(AR71XX_PCI_IRQ_DEV2); -+ -+ else if (pending & PCI_INT_CORE) -+ generic_handle_irq(AR71XX_PCI_IRQ_CORE); -+ -+ else -+ spurious_interrupt(); -+} -+ -+static void ar71xx_pci_irq_unmask(struct irq_data *d) -+{ -+ unsigned int irq = d->irq - AR71XX_PCI_IRQ_BASE; -+ void __iomem *base = ar71xx_reset_base; -+ u32 t; -+ -+ t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); -+ __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); -+ -+ /* flush write */ -+ (void) __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); -+} -+ -+static void ar71xx_pci_irq_mask(struct irq_data *d) -+{ -+ unsigned int irq = d->irq - AR71XX_PCI_IRQ_BASE; -+ void __iomem *base = ar71xx_reset_base; -+ u32 t; -+ -+ t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); -+ __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); -+ -+ /* flush write */ -+ (void) __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); -+} -+ -+static struct irq_chip ar71xx_pci_irq_chip = { -+ .name = "AR71XX PCI ", -+ .irq_mask = ar71xx_pci_irq_mask, -+ .irq_unmask = ar71xx_pci_irq_unmask, -+ .irq_mask_ack = ar71xx_pci_irq_mask, -+}; -+ -+static void __init ar71xx_pci_irq_init(void) -+{ -+ void __iomem *base = ar71xx_reset_base; -+ int i; -+ -+ __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE); -+ __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS); -+ -+ for (i = AR71XX_PCI_IRQ_BASE; -+ i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) -+ irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip, -+ handle_level_irq); -+ -+ irq_set_chained_handler(AR71XX_CPU_IRQ_IP2, ar71xx_pci_irq_handler); -+} -+ -+int __init ar71xx_pcibios_init(void) -+{ -+ void __iomem *ddr_base = ar71xx_ddr_base; -+ -+ ar71xx_device_stop(RESET_MODULE_PCI_BUS | RESET_MODULE_PCI_CORE); -+ ar71xx_pci_delay(); -+ -+ ar71xx_device_start(RESET_MODULE_PCI_BUS | RESET_MODULE_PCI_CORE); -+ ar71xx_pci_delay(); -+ -+ ar71xx_pcicfg_base = ioremap_nocache(AR71XX_PCI_CFG_BASE, -+ AR71XX_PCI_CFG_SIZE); -+ if (ar71xx_pcicfg_base == NULL) -+ return -ENOMEM; -+ -+ __raw_writel(PCI_WIN0_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN0); -+ __raw_writel(PCI_WIN1_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN1); -+ __raw_writel(PCI_WIN2_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN2); -+ __raw_writel(PCI_WIN3_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN3); -+ __raw_writel(PCI_WIN4_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN4); -+ __raw_writel(PCI_WIN5_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN5); -+ __raw_writel(PCI_WIN6_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN6); -+ __raw_writel(PCI_WIN7_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN7); -+ -+ ar71xx_pci_delay(); -+ -+ /* clear bus errors */ -+ (void)ar71xx_pci_be_handler(1); -+ -+ ar71xx_pci_fixup_enable = 1; -+ ar71xx_pci_irq_init(); -+ register_pci_controller(&ar71xx_pci_controller); -+ -+ return 0; -+} -diff -Nur linux-2.6.39.orig/arch/mips/pci/pci-ar724x.c linux-2.6.39/arch/mips/pci/pci-ar724x.c ---- linux-2.6.39.orig/arch/mips/pci/pci-ar724x.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/arch/mips/pci/pci-ar724x.c 2011-08-24 18:17:24.000000000 +0200 -@@ -0,0 +1,389 @@ -+/* -+ * Atheros AR724x PCI host controller driver -+ * -+ * Copyright (C) 2009-2010 Gabor Juhos -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#undef DEBUG -+#ifdef DEBUG -+#define DBG(fmt, args...) printk(KERN_INFO fmt, ## args) -+#else -+#define DBG(fmt, args...) -+#endif -+ -+static void __iomem *ar724x_pci_localcfg_base; -+static void __iomem *ar724x_pci_devcfg_base; -+static void __iomem *ar724x_pci_ctrl_base; -+static int ar724x_pci_fixup_enable; -+ -+static DEFINE_SPINLOCK(ar724x_pci_lock); -+ -+static void ar724x_pci_read(void __iomem *base, int where, int size, u32 *value) -+{ -+ unsigned long flags; -+ u32 data; -+ -+ spin_lock_irqsave(&ar724x_pci_lock, flags); -+ data = __raw_readl(base + (where & ~3)); -+ -+ switch (size) { -+ case 1: -+ if (where & 1) -+ data >>= 8; -+ if (where & 2) -+ data >>= 16; -+ data &= 0xFF; -+ break; -+ case 2: -+ if (where & 2) -+ data >>= 16; -+ data &= 0xFFFF; -+ break; -+ } -+ -+ *value = data; -+ spin_unlock_irqrestore(&ar724x_pci_lock, flags); -+} -+ -+static void ar724x_pci_write(void __iomem *base, int where, int size, u32 value) -+{ -+ unsigned long flags; -+ u32 data; -+ int s; -+ -+ spin_lock_irqsave(&ar724x_pci_lock, flags); -+ data = __raw_readl(base + (where & ~3)); -+ -+ switch (size) { -+ case 1: -+ s = ((where & 3) << 3); -+ data &= ~(0xFF << s); -+ data |= ((value & 0xFF) << s); -+ break; -+ case 2: -+ s = ((where & 2) << 3); -+ data &= ~(0xFFFF << s); -+ data |= ((value & 0xFFFF) << s); -+ break; -+ case 4: -+ data = value; -+ break; -+ } -+ -+ __raw_writel(data, base + (where & ~3)); -+ /* flush write */ -+ (void)__raw_readl(base + (where & ~3)); -+ spin_unlock_irqrestore(&ar724x_pci_lock, flags); -+} -+ -+static int ar724x_pci_read_config(struct pci_bus *bus, unsigned int devfn, -+ int where, int size, u32 *value) -+{ -+ -+ if (bus->number != 0 || devfn != 0) -+ return PCIBIOS_DEVICE_NOT_FOUND; -+ -+ ar724x_pci_read(ar724x_pci_devcfg_base, where, size, value); -+ -+ DBG("PCI: read config: %02x:%02x.%01x/%02x:%01d, value=%08x\n", -+ bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), -+ where, size, *value); -+ -+ /* -+ * WAR for BAR issue - We are unable to access the PCI device space -+ * if we set the BAR with proper base address -+ */ -+ if ((where == 0x10) && (size == 4)) { -+ u32 val; -+ val = (ar71xx_soc == AR71XX_SOC_AR7240) ? 0xffff : 0x1000ffff; -+ ar724x_pci_write(ar724x_pci_devcfg_base, where, size, val); -+ } -+ -+ return PCIBIOS_SUCCESSFUL; -+} -+ -+static int ar724x_pci_write_config(struct pci_bus *bus, unsigned int devfn, -+ int where, int size, u32 value) -+{ -+ if (bus->number != 0 || devfn != 0) -+ return PCIBIOS_DEVICE_NOT_FOUND; -+ -+ DBG("PCI: write config: %02x:%02x.%01x/%02x:%01d, value=%08x\n", -+ bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), -+ where, size, value); -+ -+ ar724x_pci_write(ar724x_pci_devcfg_base, where, size, value); -+ -+ return PCIBIOS_SUCCESSFUL; -+} -+ -+static void ar724x_pci_fixup(struct pci_dev *dev) -+{ -+ u16 cmd; -+ -+ if (!ar724x_pci_fixup_enable) -+ return; -+ -+ if (dev->bus->number != 0 || dev->devfn != 0) -+ return; -+ -+ /* setup COMMAND register */ -+ pci_read_config_word(dev, PCI_COMMAND, &cmd); -+ cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | -+ PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | -+ PCI_COMMAND_FAST_BACK; -+ -+ pci_write_config_word(dev, PCI_COMMAND, cmd); -+} -+DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ar724x_pci_fixup); -+ -+int __init ar724x_pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, -+ uint8_t pin) -+{ -+ int irq = -1; -+ int i; -+ -+ for (i = 0; i < ar71xx_pci_nr_irqs; i++) { -+ struct ar71xx_pci_irq *entry; -+ entry = &ar71xx_pci_irq_map[i]; -+ -+ if (entry->slot == slot && entry->pin == pin) { -+ irq = entry->irq; -+ break; -+ } -+ } -+ -+ if (irq < 0) -+ printk(KERN_ALERT "PCI: no irq found for pin%u@%s\n", -+ pin, pci_name((struct pci_dev *)dev)); -+ else -+ printk(KERN_INFO "PCI: mapping irq %d to pin%u@%s\n", -+ irq, pin, pci_name((struct pci_dev *)dev)); -+ -+ return irq; -+} -+ -+static struct pci_ops ar724x_pci_ops = { -+ .read = ar724x_pci_read_config, -+ .write = ar724x_pci_write_config, -+}; -+ -+static struct resource ar724x_pci_io_resource = { -+ .name = "PCI IO space", -+ .start = 0, -+ .end = 0, -+ .flags = IORESOURCE_IO, -+}; -+ -+static struct resource ar724x_pci_mem_resource = { -+ .name = "PCI memory space", -+ .start = AR71XX_PCI_MEM_BASE, -+ .end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1, -+ .flags = IORESOURCE_MEM -+}; -+ -+static struct pci_controller ar724x_pci_controller = { -+ .pci_ops = &ar724x_pci_ops, -+ .mem_resource = &ar724x_pci_mem_resource, -+ .io_resource = &ar724x_pci_io_resource, -+}; -+ -+static void __init ar724x_pci_reset(void) -+{ -+ ar71xx_device_stop(AR724X_RESET_PCIE); -+ ar71xx_device_stop(AR724X_RESET_PCIE_PHY); -+ ar71xx_device_stop(AR724X_RESET_PCIE_PHY_SERIAL); -+ udelay(100); -+ -+ ar71xx_device_start(AR724X_RESET_PCIE_PHY_SERIAL); -+ udelay(100); -+ ar71xx_device_start(AR724X_RESET_PCIE_PHY); -+ ar71xx_device_start(AR724X_RESET_PCIE); -+} -+ -+static int __init ar724x_pci_setup(void) -+{ -+ void __iomem *base = ar724x_pci_ctrl_base; -+ u32 t; -+ -+ /* setup COMMAND register */ -+ t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE | -+ PCI_COMMAND_PARITY|PCI_COMMAND_SERR|PCI_COMMAND_FAST_BACK; -+ -+ ar724x_pci_write(ar724x_pci_localcfg_base, PCI_COMMAND, 4, t); -+ ar724x_pci_write(ar724x_pci_localcfg_base, 0x20, 4, 0x1ff01000); -+ ar724x_pci_write(ar724x_pci_localcfg_base, 0x24, 4, 0x1ff01000); -+ -+ t = __raw_readl(base + AR724X_PCI_REG_RESET); -+ if (t != 0x7) { -+ udelay(100000); -+ __raw_writel(0, base + AR724X_PCI_REG_RESET); -+ udelay(100); -+ __raw_writel(4, base + AR724X_PCI_REG_RESET); -+ udelay(100000); -+ } -+ -+ if (ar71xx_soc == AR71XX_SOC_AR7240) -+ t = AR724X_PCI_APP_LTSSM_ENABLE; -+ else -+ t = 0x1ffc1; -+ __raw_writel(t, base + AR724X_PCI_REG_APP); -+ /* flush write */ -+ (void) __raw_readl(base + AR724X_PCI_REG_APP); -+ udelay(1000); -+ -+ t = __raw_readl(base + AR724X_PCI_REG_RESET); -+ if ((t & AR724X_PCI_RESET_LINK_UP) == 0x0) { -+ printk(KERN_WARNING "PCI: no PCIe module found\n"); -+ return -ENODEV; -+ } -+ -+ if (ar71xx_soc == AR71XX_SOC_AR7241 || -+ ar71xx_soc == AR71XX_SOC_AR7242) { -+ t = __raw_readl(base + AR724X_PCI_REG_APP); -+ t |= BIT(16); -+ __raw_writel(t, base + AR724X_PCI_REG_APP); -+ } -+ -+ return 0; -+} -+ -+static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc) -+{ -+ void __iomem *base = ar724x_pci_ctrl_base; -+ u32 pending; -+ -+ pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) & -+ __raw_readl(base + AR724X_PCI_REG_INT_MASK); -+ -+ if (pending & AR724X_PCI_INT_DEV0) -+ generic_handle_irq(AR71XX_PCI_IRQ_DEV0); -+ -+ else -+ spurious_interrupt(); -+} -+ -+static void ar724x_pci_irq_unmask(struct irq_data *d) -+{ -+ void __iomem *base = ar724x_pci_ctrl_base; -+ u32 t; -+ -+ switch (d->irq) { -+ case AR71XX_PCI_IRQ_DEV0: -+ t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); -+ __raw_writel(t | AR724X_PCI_INT_DEV0, -+ base + AR724X_PCI_REG_INT_MASK); -+ /* flush write */ -+ (void) __raw_readl(base + AR724X_PCI_REG_INT_MASK); -+ } -+} -+ -+static void ar724x_pci_irq_mask(struct irq_data *d) -+{ -+ void __iomem *base = ar724x_pci_ctrl_base; -+ u32 t; -+ -+ switch (d->irq) { -+ case AR71XX_PCI_IRQ_DEV0: -+ t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); -+ __raw_writel(t & ~AR724X_PCI_INT_DEV0, -+ base + AR724X_PCI_REG_INT_MASK); -+ -+ /* flush write */ -+ (void) __raw_readl(base + AR724X_PCI_REG_INT_MASK); -+ -+ t = __raw_readl(base + AR724X_PCI_REG_INT_STATUS); -+ __raw_writel(t | AR724X_PCI_INT_DEV0, -+ base + AR724X_PCI_REG_INT_STATUS); -+ -+ /* flush write */ -+ (void) __raw_readl(base + AR724X_PCI_REG_INT_STATUS); -+ } -+} -+ -+static struct irq_chip ar724x_pci_irq_chip = { -+ .name = "AR724X PCI ", -+ .irq_mask = ar724x_pci_irq_mask, -+ .irq_unmask = ar724x_pci_irq_unmask, -+ .irq_mask_ack = ar724x_pci_irq_mask, -+}; -+ -+static void __init ar724x_pci_irq_init(void) -+{ -+ void __iomem *base = ar724x_pci_ctrl_base; -+ u32 t; -+ int i; -+ -+ t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE); -+ if (t & (AR724X_RESET_PCIE | AR724X_RESET_PCIE_PHY | -+ AR724X_RESET_PCIE_PHY_SERIAL)) { -+ return; -+ } -+ -+ __raw_writel(0, base + AR724X_PCI_REG_INT_MASK); -+ __raw_writel(0, base + AR724X_PCI_REG_INT_STATUS); -+ -+ for (i = AR71XX_PCI_IRQ_BASE; -+ i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) -+ irq_set_chip_and_handler(i, &ar724x_pci_irq_chip, -+ handle_level_irq); -+ -+ irq_set_chained_handler(AR71XX_CPU_IRQ_IP2, ar724x_pci_irq_handler); -+} -+ -+int __init ar724x_pcibios_init(void) -+{ -+ int ret = -ENOMEM; -+ -+ ar724x_pci_localcfg_base = ioremap_nocache(AR724X_PCI_CRP_BASE, -+ AR724X_PCI_CRP_SIZE); -+ if (ar724x_pci_localcfg_base == NULL) -+ goto err; -+ -+ ar724x_pci_devcfg_base = ioremap_nocache(AR724X_PCI_CFG_BASE, -+ AR724X_PCI_CFG_SIZE); -+ if (ar724x_pci_devcfg_base == NULL) -+ goto err_unmap_localcfg; -+ -+ ar724x_pci_ctrl_base = ioremap_nocache(AR724X_PCI_CTRL_BASE, -+ AR724X_PCI_CTRL_SIZE); -+ if (ar724x_pci_ctrl_base == NULL) -+ goto err_unmap_devcfg; -+ -+ ar724x_pci_reset(); -+ ret = ar724x_pci_setup(); -+ if (ret) -+ goto err_unmap_ctrl; -+ -+ ar724x_pci_fixup_enable = 1; -+ ar724x_pci_irq_init(); -+ register_pci_controller(&ar724x_pci_controller); -+ -+ return 0; -+ -+err_unmap_ctrl: -+ iounmap(ar724x_pci_ctrl_base); -+err_unmap_devcfg: -+ iounmap(ar724x_pci_devcfg_base); -+err_unmap_localcfg: -+ iounmap(ar724x_pci_localcfg_base); -+err: -+ return ret; -+} -diff -Nur linux-2.6.39.orig/drivers/Makefile linux-2.6.39/drivers/Makefile ---- linux-2.6.39.orig/drivers/Makefile 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/drivers/Makefile 2011-08-24 18:17:24.000000000 +0200 -@@ -46,8 +46,8 @@ - obj-$(CONFIG_SCSI) += scsi/ - obj-$(CONFIG_ATA) += ata/ - obj-$(CONFIG_TARGET_CORE) += target/ --obj-$(CONFIG_MTD) += mtd/ - obj-$(CONFIG_SPI) += spi/ -+obj-$(CONFIG_MTD) += mtd/ - obj-y += net/ - obj-$(CONFIG_ATM) += atm/ - obj-$(CONFIG_FUSION) += message/ -diff -Nur linux-2.6.39.orig/drivers/gpio/nxp_74hc153.c linux-2.6.39/drivers/gpio/nxp_74hc153.c ---- linux-2.6.39.orig/drivers/gpio/nxp_74hc153.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/drivers/gpio/nxp_74hc153.c 2011-08-24 18:17:24.000000000 +0200 -@@ -0,0 +1,247 @@ -+/* -+ * NXP 74HC153 - Dual 4-input multiplexer GPIO driver -+ * -+ * Copyright (C) 2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define NXP_74HC153_NUM_GPIOS 8 -+#define NXP_74HC153_S0_MASK 0x1 -+#define NXP_74HC153_S1_MASK 0x2 -+#define NXP_74HC153_BANK_MASK 0x4 -+ -+struct nxp_74hc153_chip { -+ struct device *parent; -+ struct gpio_chip gpio_chip; -+ struct mutex lock; -+}; -+ -+static struct nxp_74hc153_chip *gpio_to_nxp(struct gpio_chip *gc) -+{ -+ return container_of(gc, struct nxp_74hc153_chip, gpio_chip); -+} -+ -+static int nxp_74hc153_direction_input(struct gpio_chip *gc, unsigned offset) -+{ -+ return 0; -+} -+ -+static int nxp_74hc153_direction_output(struct gpio_chip *gc, -+ unsigned offset, int val) -+{ -+ return -EINVAL; -+} -+ -+static int nxp_74hc153_get_value(struct gpio_chip *gc, unsigned offset) -+{ -+ struct nxp_74hc153_chip *nxp; -+ struct nxp_74hc153_platform_data *pdata; -+ unsigned s0; -+ unsigned s1; -+ unsigned pin; -+ int ret; -+ -+ nxp = gpio_to_nxp(gc); -+ pdata = nxp->parent->platform_data; -+ -+ s0 = !!(offset & NXP_74HC153_S0_MASK); -+ s1 = !!(offset & NXP_74HC153_S1_MASK); -+ pin = (offset & NXP_74HC153_BANK_MASK) ? pdata->gpio_pin_2y -+ : pdata->gpio_pin_1y; -+ -+ mutex_lock(&nxp->lock); -+ gpio_set_value(pdata->gpio_pin_s0, s0); -+ gpio_set_value(pdata->gpio_pin_s1, s1); -+ ret = gpio_get_value(pin); -+ mutex_unlock(&nxp->lock); -+ -+ return ret; -+} -+ -+static void nxp_74hc153_set_value(struct gpio_chip *gc, -+ unsigned offset, int val) -+{ -+ /* not supported */ -+} -+ -+static int __devinit nxp_74hc153_probe(struct platform_device *pdev) -+{ -+ struct nxp_74hc153_platform_data *pdata; -+ struct nxp_74hc153_chip *nxp; -+ struct gpio_chip *gc; -+ int err; -+ -+ pdata = pdev->dev.platform_data; -+ if (pdata == NULL) { -+ dev_dbg(&pdev->dev, "no platform data specified\n"); -+ return -EINVAL; -+ } -+ -+ nxp = kzalloc(sizeof(struct nxp_74hc153_chip), GFP_KERNEL); -+ if (nxp == NULL) { -+ dev_err(&pdev->dev, "no memory for private data\n"); -+ return -ENOMEM; -+ } -+ -+ err = gpio_request(pdata->gpio_pin_s0, dev_name(&pdev->dev)); -+ if (err) { -+ dev_err(&pdev->dev, "unable to claim gpio %u, err=%d\n", -+ pdata->gpio_pin_s0, err); -+ goto err_free_nxp; -+ } -+ -+ err = gpio_request(pdata->gpio_pin_s1, dev_name(&pdev->dev)); -+ if (err) { -+ dev_err(&pdev->dev, "unable to claim gpio %u, err=%d\n", -+ pdata->gpio_pin_s1, err); -+ goto err_free_s0; -+ } -+ -+ err = gpio_request(pdata->gpio_pin_1y, dev_name(&pdev->dev)); -+ if (err) { -+ dev_err(&pdev->dev, "unable to claim gpio %u, err=%d\n", -+ pdata->gpio_pin_1y, err); -+ goto err_free_s1; -+ } -+ -+ err = gpio_request(pdata->gpio_pin_2y, dev_name(&pdev->dev)); -+ if (err) { -+ dev_err(&pdev->dev, "unable to claim gpio %u, err=%d\n", -+ pdata->gpio_pin_2y, err); -+ goto err_free_1y; -+ } -+ -+ err = gpio_direction_output(pdata->gpio_pin_s0, 0); -+ if (err) { -+ dev_err(&pdev->dev, -+ "unable to set direction of gpio %u, err=%d\n", -+ pdata->gpio_pin_s0, err); -+ goto err_free_2y; -+ } -+ -+ err = gpio_direction_output(pdata->gpio_pin_s1, 0); -+ if (err) { -+ dev_err(&pdev->dev, -+ "unable to set direction of gpio %u, err=%d\n", -+ pdata->gpio_pin_s1, err); -+ goto err_free_2y; -+ } -+ -+ err = gpio_direction_input(pdata->gpio_pin_1y); -+ if (err) { -+ dev_err(&pdev->dev, -+ "unable to set direction of gpio %u, err=%d\n", -+ pdata->gpio_pin_1y, err); -+ goto err_free_2y; -+ } -+ -+ err = gpio_direction_input(pdata->gpio_pin_2y); -+ if (err) { -+ dev_err(&pdev->dev, -+ "unable to set direction of gpio %u, err=%d\n", -+ pdata->gpio_pin_2y, err); -+ goto err_free_2y; -+ } -+ -+ nxp->parent = &pdev->dev; -+ mutex_init(&nxp->lock); -+ -+ gc = &nxp->gpio_chip; -+ -+ gc->direction_input = nxp_74hc153_direction_input; -+ gc->direction_output = nxp_74hc153_direction_output; -+ gc->get = nxp_74hc153_get_value; -+ gc->set = nxp_74hc153_set_value; -+ gc->can_sleep = 1; -+ -+ gc->base = pdata->gpio_base; -+ gc->ngpio = NXP_74HC153_NUM_GPIOS; -+ gc->label = dev_name(nxp->parent); -+ gc->dev = nxp->parent; -+ gc->owner = THIS_MODULE; -+ -+ err = gpiochip_add(&nxp->gpio_chip); -+ if (err) { -+ dev_err(&pdev->dev, "unable to add gpio chip, err=%d\n", err); -+ goto err_free_2y; -+ } -+ -+ platform_set_drvdata(pdev, nxp); -+ return 0; -+ -+err_free_2y: -+ gpio_free(pdata->gpio_pin_2y); -+err_free_1y: -+ gpio_free(pdata->gpio_pin_1y); -+err_free_s1: -+ gpio_free(pdata->gpio_pin_s1); -+err_free_s0: -+ gpio_free(pdata->gpio_pin_s0); -+err_free_nxp: -+ kfree(nxp); -+ return err; -+} -+ -+static int nxp_74hc153_remove(struct platform_device *pdev) -+{ -+ struct nxp_74hc153_chip *nxp = platform_get_drvdata(pdev); -+ struct nxp_74hc153_platform_data *pdata = pdev->dev.platform_data; -+ -+ if (nxp) { -+ int err; -+ -+ err = gpiochip_remove(&nxp->gpio_chip); -+ if (err) { -+ dev_err(&pdev->dev, -+ "unable to remove gpio chip, err=%d\n", -+ err); -+ return err; -+ } -+ -+ gpio_free(pdata->gpio_pin_2y); -+ gpio_free(pdata->gpio_pin_1y); -+ gpio_free(pdata->gpio_pin_s1); -+ gpio_free(pdata->gpio_pin_s0); -+ -+ kfree(nxp); -+ platform_set_drvdata(pdev, NULL); -+ } -+ -+ return 0; -+} -+ -+static struct platform_driver nxp_74hc153_driver = { -+ .probe = nxp_74hc153_probe, -+ .remove = __devexit_p(nxp_74hc153_remove), -+ .driver = { -+ .name = NXP_74HC153_DRIVER_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init nxp_74hc153_init(void) -+{ -+ return platform_driver_register(&nxp_74hc153_driver); -+} -+subsys_initcall(nxp_74hc153_init); -+ -+static void __exit nxp_74hc153_exit(void) -+{ -+ platform_driver_unregister(&nxp_74hc153_driver); -+} -+module_exit(nxp_74hc153_exit); -+ -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_DESCRIPTION("GPIO expander driver for NXP 74HC153"); -+MODULE_LICENSE("GPL v2"); -+MODULE_ALIAS("platform:" NXP_74HC153_DRIVER_NAME); -diff -Nur linux-2.6.39.orig/drivers/leds/leds-rb750.c linux-2.6.39/drivers/leds/leds-rb750.c ---- linux-2.6.39.orig/drivers/leds/leds-rb750.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/drivers/leds/leds-rb750.c 2011-08-24 18:17:24.000000000 +0200 -@@ -0,0 +1,141 @@ -+/* -+ * LED driver for the RouterBOARD 750 -+ * -+ * Copyright (C) 2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ */ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#define DRV_NAME "leds-rb750" -+ -+struct rb750_led_dev { -+ struct led_classdev cdev; -+ u32 mask; -+ int active_low; -+}; -+ -+struct rb750_led_drvdata { -+ struct rb750_led_dev *led_devs; -+ int num_leds; -+}; -+ -+static inline struct rb750_led_dev *to_rbled(struct led_classdev *led_cdev) -+{ -+ return (struct rb750_led_dev *)container_of(led_cdev, -+ struct rb750_led_dev, cdev); -+} -+ -+static void rb750_led_brightness_set(struct led_classdev *led_cdev, -+ enum led_brightness value) -+{ -+ struct rb750_led_dev *rbled = to_rbled(led_cdev); -+ int level; -+ -+ level = (value == LED_OFF) ? 0 : 1; -+ level ^= rbled->active_low; -+ -+ if (level) -+ rb750_latch_change(0, rbled->mask); -+ else -+ rb750_latch_change(rbled->mask, 0); -+} -+ -+static int __devinit rb750_led_probe(struct platform_device *pdev) -+{ -+ struct rb750_led_platform_data *pdata; -+ struct rb750_led_drvdata *drvdata; -+ int ret = 0; -+ int i; -+ -+ pdata = pdev->dev.platform_data; -+ if (!pdata) -+ return -EINVAL; -+ -+ drvdata = kzalloc(sizeof(struct rb750_led_drvdata) + -+ sizeof(struct rb750_led_dev) * pdata->num_leds, -+ GFP_KERNEL); -+ if (!drvdata) -+ return -ENOMEM; -+ -+ drvdata->num_leds = pdata->num_leds; -+ drvdata->led_devs = (struct rb750_led_dev *) &drvdata[1]; -+ -+ for (i = 0; i < drvdata->num_leds; i++) { -+ struct rb750_led_dev *rbled = &drvdata->led_devs[i]; -+ struct rb750_led_data *led_data = &pdata->leds[i]; -+ -+ rbled->cdev.name = led_data->name; -+ rbled->cdev.default_trigger = led_data->default_trigger; -+ rbled->cdev.brightness_set = rb750_led_brightness_set; -+ rbled->cdev.brightness = LED_OFF; -+ -+ rbled->mask = led_data->mask; -+ rbled->active_low = !!led_data->active_low; -+ -+ ret = led_classdev_register(&pdev->dev, &rbled->cdev); -+ if (ret) -+ goto err; -+ } -+ -+ platform_set_drvdata(pdev, drvdata); -+ return 0; -+ -+err: -+ for (i = i - 1; i >= 0; i--) -+ led_classdev_unregister(&drvdata->led_devs[i].cdev); -+ -+ kfree(drvdata); -+ return ret; -+} -+ -+static int __devexit rb750_led_remove(struct platform_device *pdev) -+{ -+ struct rb750_led_drvdata *drvdata; -+ int i; -+ -+ drvdata = platform_get_drvdata(pdev); -+ for (i = 0; i < drvdata->num_leds; i++) -+ led_classdev_unregister(&drvdata->led_devs[i].cdev); -+ -+ kfree(drvdata); -+ return 0; -+} -+ -+static struct platform_driver rb750_led_driver = { -+ .probe = rb750_led_probe, -+ .remove = __devexit_p(rb750_led_remove), -+ .driver = { -+ .name = DRV_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+MODULE_ALIAS("platform:leds-rb750"); -+ -+static int __init rb750_led_init(void) -+{ -+ return platform_driver_register(&rb750_led_driver); -+} -+ -+static void __exit rb750_led_exit(void) -+{ -+ platform_driver_unregister(&rb750_led_driver); -+} -+ -+module_init(rb750_led_init); -+module_exit(rb750_led_exit); -+ -+MODULE_DESCRIPTION(DRV_NAME); -+MODULE_DESCRIPTION("LED driver for the RouterBOARD 750"); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_LICENSE("GPL v2"); -diff -Nur linux-2.6.39.orig/drivers/leds/leds-wndr3700-usb.c linux-2.6.39/drivers/leds/leds-wndr3700-usb.c ---- linux-2.6.39.orig/drivers/leds/leds-wndr3700-usb.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/drivers/leds/leds-wndr3700-usb.c 2011-08-24 18:17:24.000000000 +0200 -@@ -0,0 +1,75 @@ -+/* -+ * USB LED driver for the NETGEAR WNDR3700 -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+ -+#include -+ -+#define DRIVER_NAME "wndr3700-led-usb" -+ -+static void wndr3700_usb_led_set(struct led_classdev *cdev, -+ enum led_brightness brightness) -+{ -+ if (brightness) -+ ar71xx_device_start(RESET_MODULE_GE1_PHY); -+ else -+ ar71xx_device_stop(RESET_MODULE_GE1_PHY); -+} -+ -+static enum led_brightness wndr3700_usb_led_get(struct led_classdev *cdev) -+{ -+ return ar71xx_device_stopped(RESET_MODULE_GE1_PHY) ? LED_OFF : LED_FULL; -+} -+ -+static struct led_classdev wndr3700_usb_led = { -+ .name = "wndr3700:green:usb", -+ .brightness_set = wndr3700_usb_led_set, -+ .brightness_get = wndr3700_usb_led_get, -+}; -+ -+static int __devinit wndr3700_usb_led_probe(struct platform_device *pdev) -+{ -+ return led_classdev_register(&pdev->dev, &wndr3700_usb_led); -+} -+ -+static int __devexit wndr3700_usb_led_remove(struct platform_device *pdev) -+{ -+ led_classdev_unregister(&wndr3700_usb_led); -+ return 0; -+} -+ -+static struct platform_driver wndr3700_usb_led_driver = { -+ .probe = wndr3700_usb_led_probe, -+ .remove = __devexit_p(wndr3700_usb_led_remove), -+ .driver = { -+ .name = DRIVER_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init wndr3700_usb_led_init(void) -+{ -+ return platform_driver_register(&wndr3700_usb_led_driver); -+} -+ -+static void __exit wndr3700_usb_led_exit(void) -+{ -+ platform_driver_unregister(&wndr3700_usb_led_driver); -+} -+ -+module_init(wndr3700_usb_led_init); -+module_exit(wndr3700_usb_led_exit); -+ -+MODULE_DESCRIPTION("USB LED driver for the NETGEAR WNDR3700"); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_LICENSE("GPL v2"); -+MODULE_ALIAS("platform:" DRIVER_NAME); -diff -Nur linux-2.6.39.orig/drivers/mtd/chips/cfi_cmdset_0002.c linux-2.6.39/drivers/mtd/chips/cfi_cmdset_0002.c ---- linux-2.6.39.orig/drivers/mtd/chips/cfi_cmdset_0002.c 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/drivers/mtd/chips/cfi_cmdset_0002.c 2011-08-24 18:17:24.000000000 +0200 -@@ -39,7 +39,7 @@ - #include - - #define AMD_BOOTLOC_BUG --#define FORCE_WORD_WRITE 0 -+#define FORCE_WORD_WRITE 1 - - #define MAX_WORD_RETRIES 3 - -@@ -50,7 +50,9 @@ - - static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *); - static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *); -+#if !FORCE_WORD_WRITE - static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *); -+#endif - static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *); - static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *); - static void cfi_amdstd_sync (struct mtd_info *); -@@ -186,6 +188,7 @@ - } - #endif - -+#if !FORCE_WORD_WRITE - static void fixup_use_write_buffers(struct mtd_info *mtd) - { - struct map_info *map = mtd->priv; -@@ -195,6 +198,7 @@ - mtd->write = cfi_amdstd_write_buffers; - } - } -+#endif /* !FORCE_WORD_WRITE */ - - /* Atmel chips don't use the same PRI format as AMD chips */ - static void fixup_convert_atmel_pri(struct mtd_info *mtd) -@@ -1377,6 +1381,7 @@ - /* - * FIXME: interleaved mode not tested, and probably not supported! - */ -+#if !FORCE_WORD_WRITE - static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip, - unsigned long adr, const u_char *buf, - int len) -@@ -1487,7 +1492,6 @@ - return ret; - } - -- - static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len, - size_t *retlen, const u_char *buf) - { -@@ -1566,6 +1570,7 @@ - - return 0; - } -+#endif /* !FORCE_WORD_WRITE */ - - - /* -diff -Nur linux-2.6.39.orig/drivers/mtd/maps/Kconfig linux-2.6.39/drivers/mtd/maps/Kconfig ---- linux-2.6.39.orig/drivers/mtd/maps/Kconfig 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/drivers/mtd/maps/Kconfig 2011-08-24 18:17:24.000000000 +0200 -@@ -260,6 +260,13 @@ - Support for parsing CFE image tag and creating MTD partitions on - Broadcom BCM63xx boards. - -+config MTD_AR91XX_FLASH -+ tristate "Atheros AR91xx parallel flash support" -+ depends on ATHEROS_AR71XX -+ select MTD_COMPLEX_MAPPINGS -+ help -+ Parallel flash driver for the Atheros AR91xx based boards. -+ - config MTD_DILNETPC - tristate "CFI Flash device mapped on DIL/Net PC" - depends on X86 && MTD_PARTITIONS && MTD_CFI_INTELEXT && BROKEN -diff -Nur linux-2.6.39.orig/drivers/mtd/maps/Makefile linux-2.6.39/drivers/mtd/maps/Makefile ---- linux-2.6.39.orig/drivers/mtd/maps/Makefile 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/drivers/mtd/maps/Makefile 2011-08-24 18:17:24.000000000 +0200 -@@ -40,6 +40,7 @@ - obj-$(CONFIG_MTD_DBOX2) += dbox2-flash.o - obj-$(CONFIG_MTD_SOLUTIONENGINE)+= solutionengine.o - obj-$(CONFIG_MTD_PCI) += pci.o -+obj-$(CONFIG_MTD_AR91XX_FLASH) += ar91xx_flash.o - obj-$(CONFIG_MTD_AUTCPU12) += autcpu12-nvram.o - obj-$(CONFIG_MTD_EDB7312) += edb7312.o - obj-$(CONFIG_MTD_IMPA7) += impa7.o -diff -Nur linux-2.6.39.orig/drivers/mtd/maps/ar91xx_flash.c linux-2.6.39/drivers/mtd/maps/ar91xx_flash.c ---- linux-2.6.39.orig/drivers/mtd/maps/ar91xx_flash.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/drivers/mtd/maps/ar91xx_flash.c 2011-08-24 18:17:24.000000000 +0200 -@@ -0,0 +1,310 @@ -+/* -+ * Parallel flash driver for the Atheros AR91xx SoC -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#define DRV_NAME "ar91xx-flash" -+ -+struct ar91xx_flash_info { -+ struct mtd_info *mtd; -+ struct map_info map; -+#ifdef CONFIG_MTD_PARTITIONS -+ int nr_parts; -+ struct mtd_partition *parts; -+#endif -+}; -+ -+static map_word ar91xx_flash_read(struct map_info *map, unsigned long ofs) -+{ -+ map_word val; -+ -+ if (map_bankwidth_is_1(map)) -+ val.x[0] = __raw_readb(map->virt + (ofs ^ 3)); -+ else if (map_bankwidth_is_2(map)) -+ val.x[0] = __raw_readw(map->virt + (ofs ^ 2)); -+ else -+ val = map_word_ff(map); -+ -+ return val; -+} -+ -+static void ar91xx_flash_write(struct map_info *map, map_word d, -+ unsigned long ofs) -+{ -+ if (map_bankwidth_is_1(map)) -+ __raw_writeb(d.x[0], map->virt + (ofs ^ 3)); -+ else if (map_bankwidth_is_2(map)) -+ __raw_writew(d.x[0], map->virt + (ofs ^ 2)); -+ -+ mb(); -+} -+ -+static map_word ar91xx_flash_read_lock(struct map_info *map, unsigned long ofs) -+{ -+ map_word ret; -+ -+ ar71xx_flash_acquire(); -+ ret = ar91xx_flash_read(map, ofs); -+ ar71xx_flash_release(); -+ -+ return ret; -+} -+ -+static void ar91xx_flash_write_lock(struct map_info *map, map_word d, -+ unsigned long ofs) -+{ -+ ar71xx_flash_acquire(); -+ ar91xx_flash_write(map, d, ofs); -+ ar71xx_flash_release(); -+} -+ -+static void ar91xx_flash_copy_from_lock(struct map_info *map, void *to, -+ unsigned long from, ssize_t len) -+{ -+ ar71xx_flash_acquire(); -+ inline_map_copy_from(map, to, from, len); -+ ar71xx_flash_release(); -+} -+ -+static void ar91xx_flash_copy_to_lock(struct map_info *map, unsigned long to, -+ const void *from, ssize_t len) -+{ -+ ar71xx_flash_acquire(); -+ inline_map_copy_to(map, to, from, len); -+ ar71xx_flash_release(); -+} -+ -+static int ar91xx_flash_remove(struct platform_device *pdev) -+{ -+ struct ar91xx_flash_platform_data *pdata; -+ struct ar91xx_flash_info *info; -+ -+ info = platform_get_drvdata(pdev); -+ if (info == NULL) -+ return 0; -+ -+ platform_set_drvdata(pdev, NULL); -+ -+ if (info->mtd == NULL) -+ return 0; -+ -+ pdata = pdev->dev.platform_data; -+#ifdef CONFIG_MTD_PARTITIONS -+ if (info->nr_parts) { -+ del_mtd_partitions(info->mtd); -+ kfree(info->parts); -+ } else if (pdata->nr_parts) { -+ del_mtd_partitions(info->mtd); -+ } else { -+ del_mtd_device(info->mtd); -+ } -+#else -+ del_mtd_device(info->mtd); -+#endif -+ map_destroy(info->mtd); -+ -+ return 0; -+} -+ -+static const char *rom_probe_types[] = { "cfi_probe", "jedec_probe", NULL }; -+#ifdef CONFIG_MTD_PARTITIONS -+static const char *part_probe_types[] = { "cmdlinepart", "RedBoot", NULL }; -+#endif -+ -+static int ar91xx_flash_probe(struct platform_device *pdev) -+{ -+ struct ar91xx_flash_platform_data *pdata; -+ struct ar91xx_flash_info *info; -+ struct resource *res; -+ struct resource *region; -+ const char **probe_type; -+ int err = 0; -+ -+ pdata = pdev->dev.platform_data; -+ if (pdata == NULL) -+ return -EINVAL; -+ -+ info = devm_kzalloc(&pdev->dev, sizeof(struct ar91xx_flash_info), -+ GFP_KERNEL); -+ if (info == NULL) { -+ err = -ENOMEM; -+ goto err_out; -+ } -+ -+ platform_set_drvdata(pdev, info); -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (res == NULL) { -+ err = -ENOENT; -+ goto err_out; -+ } -+ -+ dev_info(&pdev->dev, "%.8llx at %.8llx\n", -+ (unsigned long long)(res->end - res->start + 1), -+ (unsigned long long)res->start); -+ -+ region = devm_request_mem_region(&pdev->dev, -+ res->start, res->end - res->start + 1, -+ dev_name(&pdev->dev)); -+ if (region == NULL) { -+ dev_err(&pdev->dev, "could not reserve memory region\n"); -+ err = -ENOMEM; -+ goto err_out; -+ } -+ -+ info->map.name = dev_name(&pdev->dev); -+ info->map.phys = res->start; -+ info->map.size = res->end - res->start + 1; -+ info->map.bankwidth = pdata->width; -+ -+ info->map.virt = devm_ioremap(&pdev->dev, info->map.phys, -+ info->map.size); -+ if (info->map.virt == NULL) { -+ dev_err(&pdev->dev, "failed to ioremap flash region\n"); -+ err = -EIO; -+ goto err_out; -+ } -+ -+ simple_map_init(&info->map); -+ if (pdata->is_shared) { -+ info->map.read = ar91xx_flash_read_lock; -+ info->map.write = ar91xx_flash_write_lock; -+ info->map.copy_from = ar91xx_flash_copy_from_lock; -+ info->map.copy_to = ar91xx_flash_copy_to_lock; -+ } else { -+ info->map.read = ar91xx_flash_read; -+ info->map.write = ar91xx_flash_write; -+ } -+ -+ probe_type = rom_probe_types; -+ for (; info->mtd == NULL && *probe_type != NULL; probe_type++) -+ info->mtd = do_map_probe(*probe_type, &info->map); -+ -+ if (info->mtd == NULL) { -+ dev_err(&pdev->dev, "map_probe failed\n"); -+ err = -ENXIO; -+ goto err_out; -+ } -+ -+ info->mtd->owner = THIS_MODULE; -+ -+#ifdef CONFIG_MTD_PARTITIONS -+ if (pdata->nr_parts) { -+ dev_info(&pdev->dev, "using static partition mapping\n"); -+ add_mtd_partitions(info->mtd, pdata->parts, pdata->nr_parts); -+ return 0; -+ } -+ -+ err = parse_mtd_partitions(info->mtd, part_probe_types, -+ &info->parts, 0); -+ if (err > 0) { -+ add_mtd_partitions(info->mtd, info->parts, err); -+ return 0; -+ } -+#endif -+ -+ add_mtd_device(info->mtd); -+ return 0; -+ -+err_out: -+ ar91xx_flash_remove(pdev); -+ return err; -+} -+ -+#ifdef CONFIG_PM -+static int ar91xx_flash_suspend(struct platform_device *dev, pm_message_t state) -+{ -+ struct ar91xx_flash_info *info = platform_get_drvdata(dev); -+ int ret = 0; -+ -+ if (info->mtd->suspend) -+ ret = info->mtd->suspend(info->mtd); -+ -+ if (ret) -+ goto fail; -+ -+ return 0; -+ -+fail: -+ if (info->mtd->suspend) { -+ BUG_ON(!info->mtd->resume); -+ info->mtd->resume(info->mtd); -+ } -+ -+ return ret; -+} -+ -+static int ar91xx_flash_resume(struct platform_device *pdev) -+{ -+ struct ar91xx_flash_info *info = platform_get_drvdata(pdev); -+ -+ if (info->mtd->resume) -+ info->mtd->resume(info->mtd); -+ -+ return 0; -+} -+ -+static void ar91xx_flash_shutdown(struct platform_device *pdev) -+{ -+ struct ar91xx_flash_info *info = platform_get_drvdata(pdev); -+ -+ if (info->mtd->suspend && info->mtd->resume) -+ if (info->mtd->suspend(info->mtd) == 0) -+ info->mtd->resume(info->mtd); -+} -+#else -+#define ar91xx_flash_suspend NULL -+#define ar91xx_flash_resume NULL -+#define ar91xx_flash_shutdown NULL -+#endif -+ -+static struct platform_driver ar91xx_flash_driver = { -+ .probe = ar91xx_flash_probe, -+ .remove = ar91xx_flash_remove, -+ .suspend = ar91xx_flash_suspend, -+ .resume = ar91xx_flash_resume, -+ .shutdown = ar91xx_flash_shutdown, -+ .driver = { -+ .name = DRV_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init ar91xx_flash_init(void) -+{ -+ return platform_driver_register(&ar91xx_flash_driver); -+} -+ -+static void __exit ar91xx_flash_exit(void) -+{ -+ platform_driver_unregister(&ar91xx_flash_driver); -+} -+ -+module_init(ar91xx_flash_init); -+module_exit(ar91xx_flash_exit); -+ -+MODULE_LICENSE("GPL v2"); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_DESCRIPTION("Parallel flash driver for the Atheros AR91xx SoC"); -+MODULE_ALIAS("platform:" DRV_NAME); -diff -Nur linux-2.6.39.orig/drivers/mtd/nand/Kconfig linux-2.6.39/drivers/mtd/nand/Kconfig ---- linux-2.6.39.orig/drivers/mtd/nand/Kconfig 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/drivers/mtd/nand/Kconfig 2011-08-24 18:17:24.000000000 +0200 -@@ -531,4 +531,9 @@ - Enables support for NAND Flash chips on the ST Microelectronics - Flexible Static Memory Controller (FSMC) - -+config MTD_NAND_RB4XX -+ tristate "NAND flash driver for RouterBoard 4xx series" -+ depends on MTD_NAND && AR71XX_MACH_RB4XX -+ select SPI_AR71XX -+ - endif # MTD_NAND -diff -Nur linux-2.6.39.orig/drivers/mtd/nand/Makefile linux-2.6.39/drivers/mtd/nand/Makefile ---- linux-2.6.39.orig/drivers/mtd/nand/Makefile 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/drivers/mtd/nand/Makefile 2011-08-24 18:17:24.000000000 +0200 -@@ -34,6 +34,7 @@ - obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx_nand.o - obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o - obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o -+obj-$(CONFIG_MTD_NAND_RB4XX) += rb4xx_nand.o - obj-$(CONFIG_MTD_ALAUDA) += alauda.o - obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o - obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o -diff -Nur linux-2.6.39.orig/drivers/mtd/nand/rb4xx_nand.c linux-2.6.39/drivers/mtd/nand/rb4xx_nand.c ---- linux-2.6.39.orig/drivers/mtd/nand/rb4xx_nand.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/drivers/mtd/nand/rb4xx_nand.c 2011-08-24 18:17:24.000000000 +0200 -@@ -0,0 +1,311 @@ -+/* -+ * NAND flash driver for the MikroTik RouterBoard 4xx series -+ * -+ * Copyright (C) 2008-2011 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This file was based on the driver for Linux 2.6.22 published by -+ * MikroTik for their RouterBoard 4xx series devices. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#define DRV_NAME "rb4xx-nand" -+#define DRV_VERSION "0.2.0" -+#define DRV_DESC "NAND flash driver for RouterBoard 4xx series" -+ -+#define RB4XX_NAND_GPIO_READY 5 -+#define RB4XX_NAND_GPIO_ALE 37 -+#define RB4XX_NAND_GPIO_CLE 38 -+#define RB4XX_NAND_GPIO_NCE 39 -+ -+struct rb4xx_nand_info { -+ struct nand_chip chip; -+ struct mtd_info mtd; -+}; -+ -+/* -+ * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader -+ * will not be able to find the kernel that we load. -+ */ -+static struct nand_ecclayout rb4xx_nand_ecclayout = { -+ .eccbytes = 6, -+ .eccpos = { 8, 9, 10, 13, 14, 15 }, -+ .oobavail = 9, -+ .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } } -+}; -+ -+static struct mtd_partition rb4xx_nand_partitions[] = { -+ { -+ .name = "booter", -+ .offset = 0, -+ .size = (256 * 1024), -+ .mask_flags = MTD_WRITEABLE, -+ }, -+ { -+ .name = "kernel", -+ .offset = (256 * 1024), -+ .size = (6 * 1024 * 1024) - (256 * 1024), -+ }, -+ { -+ .name = "rootfs", -+ .offset = MTDPART_OFS_NXTBLK, -+ .size = MTDPART_SIZ_FULL, -+ }, -+}; -+ -+static int rb4xx_nand_dev_ready(struct mtd_info *mtd) -+{ -+ return gpio_get_value_cansleep(RB4XX_NAND_GPIO_READY); -+} -+ -+static void rb4xx_nand_write_cmd(unsigned char cmd) -+{ -+ unsigned char data = cmd; -+ int err; -+ -+ err = rb4xx_cpld_write(&data, 1); -+ if (err) -+ pr_err("rb4xx_nand: write cmd failed, err=%d\n", err); -+} -+ -+static void rb4xx_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, -+ unsigned int ctrl) -+{ -+ if (ctrl & NAND_CTRL_CHANGE) { -+ gpio_set_value_cansleep(RB4XX_NAND_GPIO_CLE, -+ (ctrl & NAND_CLE) ? 1 : 0); -+ gpio_set_value_cansleep(RB4XX_NAND_GPIO_ALE, -+ (ctrl & NAND_ALE) ? 1 : 0); -+ gpio_set_value_cansleep(RB4XX_NAND_GPIO_NCE, -+ (ctrl & NAND_NCE) ? 0 : 1); -+ } -+ -+ if (cmd != NAND_CMD_NONE) -+ rb4xx_nand_write_cmd(cmd); -+} -+ -+static unsigned char rb4xx_nand_read_byte(struct mtd_info *mtd) -+{ -+ unsigned char data = 0; -+ int err; -+ -+ err = rb4xx_cpld_read(&data, NULL, 1); -+ if (err) { -+ pr_err("rb4xx_nand: read data failed, err=%d\n", err); -+ data = 0xff; -+ } -+ -+ return data; -+} -+ -+static void rb4xx_nand_write_buf(struct mtd_info *mtd, const unsigned char *buf, -+ int len) -+{ -+ int err; -+ -+ err = rb4xx_cpld_write(buf, len); -+ if (err) -+ pr_err("rb4xx_nand: write buf failed, err=%d\n", err); -+} -+ -+static void rb4xx_nand_read_buf(struct mtd_info *mtd, unsigned char *buf, -+ int len) -+{ -+ int err; -+ -+ err = rb4xx_cpld_read(buf, NULL, len); -+ if (err) -+ pr_err("rb4xx_nand: read buf failed, err=%d\n", err); -+} -+ -+static int __init rb4xx_nand_probe(struct platform_device *pdev) -+{ -+ struct rb4xx_nand_info *info; -+ int ret; -+ -+ printk(KERN_INFO DRV_DESC " version " DRV_VERSION "\n"); -+ -+ ret = gpio_request(RB4XX_NAND_GPIO_READY, "NAND RDY"); -+ if (ret) { -+ dev_err(&pdev->dev, "unable to request gpio %d\n", -+ RB4XX_NAND_GPIO_READY); -+ goto err; -+ } -+ -+ ret = gpio_direction_input(RB4XX_NAND_GPIO_READY); -+ if (ret) { -+ dev_err(&pdev->dev, "unable to set input mode on gpio %d\n", -+ RB4XX_NAND_GPIO_READY); -+ goto err_free_gpio_ready; -+ } -+ -+ ret = gpio_request(RB4XX_NAND_GPIO_ALE, "NAND ALE"); -+ if (ret) { -+ dev_err(&pdev->dev, "unable to request gpio %d\n", -+ RB4XX_NAND_GPIO_ALE); -+ goto err_free_gpio_ready; -+ } -+ -+ ret = gpio_direction_output(RB4XX_NAND_GPIO_ALE, 0); -+ if (ret) { -+ dev_err(&pdev->dev, "unable to set output mode on gpio %d\n", -+ RB4XX_NAND_GPIO_ALE); -+ goto err_free_gpio_ale; -+ } -+ -+ ret = gpio_request(RB4XX_NAND_GPIO_CLE, "NAND CLE"); -+ if (ret) { -+ dev_err(&pdev->dev, "unable to request gpio %d\n", -+ RB4XX_NAND_GPIO_CLE); -+ goto err_free_gpio_ale; -+ } -+ -+ ret = gpio_direction_output(RB4XX_NAND_GPIO_CLE, 0); -+ if (ret) { -+ dev_err(&pdev->dev, "unable to set output mode on gpio %d\n", -+ RB4XX_NAND_GPIO_CLE); -+ goto err_free_gpio_cle; -+ } -+ -+ ret = gpio_request(RB4XX_NAND_GPIO_NCE, "NAND NCE"); -+ if (ret) { -+ dev_err(&pdev->dev, "unable to request gpio %d\n", -+ RB4XX_NAND_GPIO_NCE); -+ goto err_free_gpio_cle; -+ } -+ -+ ret = gpio_direction_output(RB4XX_NAND_GPIO_NCE, 1); -+ if (ret) { -+ dev_err(&pdev->dev, "unable to set output mode on gpio %d\n", -+ RB4XX_NAND_GPIO_ALE); -+ goto err_free_gpio_nce; -+ } -+ -+ info = kzalloc(sizeof(*info), GFP_KERNEL); -+ if (!info) { -+ dev_err(&pdev->dev, "rb4xx-nand: no memory for private data\n"); -+ ret = -ENOMEM; -+ goto err_free_gpio_nce; -+ } -+ -+ info->chip.priv = &info; -+ info->mtd.priv = &info->chip; -+ info->mtd.owner = THIS_MODULE; -+ -+ info->chip.cmd_ctrl = rb4xx_nand_cmd_ctrl; -+ info->chip.dev_ready = rb4xx_nand_dev_ready; -+ info->chip.read_byte = rb4xx_nand_read_byte; -+ info->chip.write_buf = rb4xx_nand_write_buf; -+ info->chip.read_buf = rb4xx_nand_read_buf; -+#if 0 -+ info->chip.verify_buf = rb4xx_nand_verify_buf; -+#endif -+ -+ info->chip.chip_delay = 25; -+ info->chip.ecc.mode = NAND_ECC_SOFT; -+ info->chip.options |= NAND_NO_AUTOINCR; -+ -+ platform_set_drvdata(pdev, info); -+ -+ ret = nand_scan_ident(&info->mtd, 1, NULL); -+ if (ret) { -+ ret = -ENXIO; -+ goto err_free_info; -+ } -+ -+ if (info->mtd.writesize == 512) -+ info->chip.ecc.layout = &rb4xx_nand_ecclayout; -+ -+ ret = nand_scan_tail(&info->mtd); -+ if (ret) { -+ return -ENXIO; -+ goto err_set_drvdata; -+ } -+ -+#ifdef CONFIG_MTD_PARTITIONS -+ ret = add_mtd_partitions(&info->mtd, rb4xx_nand_partitions, -+ ARRAY_SIZE(rb4xx_nand_partitions)); -+#else -+ ret = add_mtd_device(&info->mtd); -+#endif -+ if (ret) -+ goto err_release_nand; -+ -+ return 0; -+ -+err_release_nand: -+ nand_release(&info->mtd); -+err_set_drvdata: -+ platform_set_drvdata(pdev, NULL); -+err_free_info: -+ kfree(info); -+err_free_gpio_nce: -+ gpio_free(RB4XX_NAND_GPIO_NCE); -+err_free_gpio_cle: -+ gpio_free(RB4XX_NAND_GPIO_CLE); -+err_free_gpio_ale: -+ gpio_free(RB4XX_NAND_GPIO_ALE); -+err_free_gpio_ready: -+ gpio_free(RB4XX_NAND_GPIO_READY); -+err: -+ return ret; -+} -+ -+static int __devexit rb4xx_nand_remove(struct platform_device *pdev) -+{ -+ struct rb4xx_nand_info *info = platform_get_drvdata(pdev); -+ -+ nand_release(&info->mtd); -+ platform_set_drvdata(pdev, NULL); -+ kfree(info); -+ gpio_free(RB4XX_NAND_GPIO_NCE); -+ gpio_free(RB4XX_NAND_GPIO_CLE); -+ gpio_free(RB4XX_NAND_GPIO_ALE); -+ gpio_free(RB4XX_NAND_GPIO_READY); -+ -+ return 0; -+} -+ -+static struct platform_driver rb4xx_nand_driver = { -+ .probe = rb4xx_nand_probe, -+ .remove = __devexit_p(rb4xx_nand_remove), -+ .driver = { -+ .name = DRV_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init rb4xx_nand_init(void) -+{ -+ return platform_driver_register(&rb4xx_nand_driver); -+} -+ -+static void __exit rb4xx_nand_exit(void) -+{ -+ platform_driver_unregister(&rb4xx_nand_driver); -+} -+ -+module_init(rb4xx_nand_init); -+module_exit(rb4xx_nand_exit); -+ -+MODULE_DESCRIPTION(DRV_DESC); -+MODULE_VERSION(DRV_VERSION); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_AUTHOR("Imre Kaloz "); -+MODULE_LICENSE("GPL v2"); -diff -Nur linux-2.6.39.orig/drivers/mtd/nand/rb750_nand.c linux-2.6.39/drivers/mtd/nand/rb750_nand.c ---- linux-2.6.39.orig/drivers/mtd/nand/rb750_nand.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/drivers/mtd/nand/rb750_nand.c 2011-08-24 18:17:24.000000000 +0200 -@@ -0,0 +1,361 @@ -+/* -+ * NAND flash driver for the MikroTik RouterBOARD 750 -+ * -+ * Copyright (C) 2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#define DRV_NAME "rb750-nand" -+#define DRV_VERSION "0.1.0" -+#define DRV_DESC "NAND flash driver for the RouterBOARD 750" -+ -+#define RB750_NAND_IO0 BIT(RB750_GPIO_NAND_IO0) -+#define RB750_NAND_ALE BIT(RB750_GPIO_NAND_ALE) -+#define RB750_NAND_CLE BIT(RB750_GPIO_NAND_CLE) -+#define RB750_NAND_NRE BIT(RB750_GPIO_NAND_NRE) -+#define RB750_NAND_NWE BIT(RB750_GPIO_NAND_NWE) -+#define RB750_NAND_RDY BIT(RB750_GPIO_NAND_RDY) -+#define RB750_NAND_NCE BIT(RB750_GPIO_NAND_NCE) -+ -+#define RB750_NAND_DATA_SHIFT 1 -+#define RB750_NAND_DATA_BITS (0xff << RB750_NAND_DATA_SHIFT) -+#define RB750_NAND_INPUT_BITS (RB750_NAND_DATA_BITS | RB750_NAND_RDY) -+#define RB750_NAND_OUTPUT_BITS (RB750_NAND_ALE | RB750_NAND_CLE | \ -+ RB750_NAND_NRE | RB750_NAND_NWE | \ -+ RB750_NAND_NCE) -+ -+struct rb750_nand_info { -+ struct nand_chip chip; -+ struct mtd_info mtd; -+}; -+ -+/* -+ * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader -+ * will not be able to find the kernel that we load. -+ */ -+static struct nand_ecclayout rb750_nand_ecclayout = { -+ .eccbytes = 6, -+ .eccpos = { 8, 9, 10, 13, 14, 15 }, -+ .oobavail = 9, -+ .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } } -+}; -+ -+static struct mtd_partition rb750_nand_partitions[] = { -+ { -+ .name = "booter", -+ .offset = 0, -+ .size = (256 * 1024), -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "kernel", -+ .offset = (256 * 1024), -+ .size = (4 * 1024 * 1024) - (256 * 1024), -+ }, { -+ .name = "rootfs", -+ .offset = MTDPART_OFS_NXTBLK, -+ .size = MTDPART_SIZ_FULL, -+ }, -+}; -+ -+static void rb750_nand_write(const u8 *buf, unsigned len) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ u32 out; -+ unsigned i; -+ -+ /* set data lines to output mode */ -+ __raw_writel(__raw_readl(base + GPIO_REG_OE) | RB750_NAND_DATA_BITS, -+ base + GPIO_REG_OE); -+ -+ out = __raw_readl(base + GPIO_REG_OUT); -+ out &= ~(RB750_NAND_DATA_BITS | RB750_NAND_NWE); -+ for (i = 0; i != len; i++) { -+ u32 data; -+ -+ data = buf[i]; -+ data <<= RB750_NAND_DATA_SHIFT; -+ data |= out; -+ __raw_writel(data, base + GPIO_REG_OUT); -+ -+ __raw_writel(data | RB750_NAND_NWE, base + GPIO_REG_OUT); -+ /* flush write */ -+ __raw_readl(base + GPIO_REG_OUT); -+ } -+ -+ /* set data lines to input mode */ -+ __raw_writel(__raw_readl(base + GPIO_REG_OE) & ~RB750_NAND_DATA_BITS, -+ base + GPIO_REG_OE); -+ /* flush write */ -+ __raw_readl(base + GPIO_REG_OE); -+} -+ -+static int rb750_nand_read_verify(u8 *read_buf, unsigned len, -+ const u8 *verify_buf) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ unsigned i; -+ -+ for (i = 0; i < len; i++) { -+ u8 data; -+ -+ /* activate RE line */ -+ __raw_writel(RB750_NAND_NRE, base + GPIO_REG_CLEAR); -+ /* flush write */ -+ __raw_readl(base + GPIO_REG_CLEAR); -+ -+ /* read input lines */ -+ data = __raw_readl(base + GPIO_REG_IN) >> RB750_NAND_DATA_SHIFT; -+ -+ /* deactivate RE line */ -+ __raw_writel(RB750_NAND_NRE, base + GPIO_REG_SET); -+ -+ if (read_buf) -+ read_buf[i] = data; -+ else if (verify_buf && verify_buf[i] != data) -+ return -EFAULT; -+ } -+ -+ return 0; -+} -+ -+static void rb750_nand_select_chip(struct mtd_info *mtd, int chip) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ u32 func; -+ -+ func = __raw_readl(base + GPIO_REG_FUNC); -+ if (chip >= 0) { -+ /* disable latch */ -+ rb750_latch_change(RB750_LVC573_LE, 0); -+ -+ /* disable alternate functions */ -+ ar71xx_gpio_function_setup(AR724X_GPIO_FUNC_JTAG_DISABLE, -+ AR724X_GPIO_FUNC_SPI_EN); -+ -+ /* set input mode for data lines */ -+ __raw_writel(__raw_readl(base + GPIO_REG_OE) & -+ ~RB750_NAND_INPUT_BITS, -+ base + GPIO_REG_OE); -+ -+ /* deactivate RE and WE lines */ -+ __raw_writel(RB750_NAND_NRE | RB750_NAND_NWE, -+ base + GPIO_REG_SET); -+ /* flush write */ -+ (void) __raw_readl(base + GPIO_REG_SET); -+ -+ /* activate CE line */ -+ __raw_writel(RB750_NAND_NCE, base + GPIO_REG_CLEAR); -+ } else { -+ /* deactivate CE line */ -+ __raw_writel(RB750_NAND_NCE, base + GPIO_REG_SET); -+ /* flush write */ -+ (void) __raw_readl(base + GPIO_REG_SET); -+ -+ __raw_writel(__raw_readl(base + GPIO_REG_OE) | -+ RB750_NAND_IO0 | RB750_NAND_RDY, -+ base + GPIO_REG_OE); -+ -+ /* restore alternate functions */ -+ ar71xx_gpio_function_setup(AR724X_GPIO_FUNC_SPI_EN, -+ AR724X_GPIO_FUNC_JTAG_DISABLE); -+ -+ /* enable latch */ -+ rb750_latch_change(0, RB750_LVC573_LE); -+ } -+} -+ -+static int rb750_nand_dev_ready(struct mtd_info *mtd) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ -+ return !!(__raw_readl(base + GPIO_REG_IN) & RB750_NAND_RDY); -+} -+ -+static void rb750_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, -+ unsigned int ctrl) -+{ -+ if (ctrl & NAND_CTRL_CHANGE) { -+ void __iomem *base = ar71xx_gpio_base; -+ u32 t; -+ -+ t = __raw_readl(base + GPIO_REG_OUT); -+ -+ t &= ~(RB750_NAND_CLE | RB750_NAND_ALE); -+ t |= (ctrl & NAND_CLE) ? RB750_NAND_CLE : 0; -+ t |= (ctrl & NAND_ALE) ? RB750_NAND_ALE : 0; -+ -+ __raw_writel(t, base + GPIO_REG_OUT); -+ /* flush write */ -+ __raw_readl(base + GPIO_REG_OUT); -+ } -+ -+ if (cmd != NAND_CMD_NONE) { -+ u8 t = cmd; -+ rb750_nand_write(&t, 1); -+ } -+} -+ -+static u8 rb750_nand_read_byte(struct mtd_info *mtd) -+{ -+ u8 data = 0; -+ rb750_nand_read_verify(&data, 1, NULL); -+ return data; -+} -+ -+static void rb750_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len) -+{ -+ rb750_nand_read_verify(buf, len, NULL); -+} -+ -+static void rb750_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len) -+{ -+ rb750_nand_write(buf, len); -+} -+ -+static int rb750_nand_verify_buf(struct mtd_info *mtd, const u8 *buf, int len) -+{ -+ return rb750_nand_read_verify(NULL, len, buf); -+} -+ -+static void __init rb750_nand_gpio_init(void) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ u32 out; -+ -+ out = __raw_readl(base + GPIO_REG_OUT); -+ -+ /* setup output levels */ -+ __raw_writel(RB750_NAND_NCE | RB750_NAND_NRE | RB750_NAND_NWE, -+ base + GPIO_REG_SET); -+ -+ __raw_writel(RB750_NAND_ALE | RB750_NAND_CLE, -+ base + GPIO_REG_CLEAR); -+ -+ /* setup input lines */ -+ __raw_writel(__raw_readl(base + GPIO_REG_OE) & ~(RB750_NAND_INPUT_BITS), -+ base + GPIO_REG_OE); -+ -+ /* setup output lines */ -+ __raw_writel(__raw_readl(base + GPIO_REG_OE) | RB750_NAND_OUTPUT_BITS, -+ base + GPIO_REG_OE); -+ -+ rb750_latch_change(~out & RB750_NAND_IO0, out & RB750_NAND_IO0); -+} -+ -+static int __init rb750_nand_probe(struct platform_device *pdev) -+{ -+ struct rb750_nand_info *info; -+ int ret; -+ -+ printk(KERN_INFO DRV_DESC " version " DRV_VERSION "\n"); -+ -+ rb750_nand_gpio_init(); -+ -+ info = kzalloc(sizeof(*info), GFP_KERNEL); -+ if (!info) -+ return -ENOMEM; -+ -+ info->chip.priv = &info; -+ info->mtd.priv = &info->chip; -+ info->mtd.owner = THIS_MODULE; -+ -+ info->chip.select_chip = rb750_nand_select_chip; -+ info->chip.cmd_ctrl = rb750_nand_cmd_ctrl; -+ info->chip.dev_ready = rb750_nand_dev_ready; -+ info->chip.read_byte = rb750_nand_read_byte; -+ info->chip.write_buf = rb750_nand_write_buf; -+ info->chip.read_buf = rb750_nand_read_buf; -+ info->chip.verify_buf = rb750_nand_verify_buf; -+ -+ info->chip.chip_delay = 25; -+ info->chip.ecc.mode = NAND_ECC_SOFT; -+ info->chip.options |= NAND_NO_AUTOINCR; -+ -+ platform_set_drvdata(pdev, info); -+ -+ ret = nand_scan_ident(&info->mtd, 1); -+ if (ret) { -+ ret = -ENXIO; -+ goto err_free_info; -+ } -+ -+ if (info->mtd.writesize == 512) -+ info->chip.ecc.layout = &rb750_nand_ecclayout; -+ -+ ret = nand_scan_tail(&info->mtd); -+ if (ret) { -+ return -ENXIO; -+ goto err_set_drvdata; -+ } -+ -+#ifdef CONFIG_MTD_PARTITIONS -+ ret = add_mtd_partitions(&info->mtd, rb750_nand_partitions, -+ ARRAY_SIZE(rb750_nand_partitions)); -+#else -+ ret = add_mtd_device(&info->mtd); -+#endif -+ if (ret) -+ goto err_release_nand; -+ -+ return 0; -+ -+err_release_nand: -+ nand_release(&info->mtd); -+err_set_drvdata: -+ platform_set_drvdata(pdev, NULL); -+err_free_info: -+ kfree(info); -+ return ret; -+} -+ -+static int __devexit rb750_nand_remove(struct platform_device *pdev) -+{ -+ struct rb750_nand_info *info = platform_get_drvdata(pdev); -+ -+ nand_release(&info->mtd); -+ platform_set_drvdata(pdev, NULL); -+ kfree(info); -+ -+ return 0; -+} -+ -+static struct platform_driver rb750_nand_driver = { -+ .probe = rb750_nand_probe, -+ .remove = __devexit_p(rb750_nand_remove), -+ .driver = { -+ .name = DRV_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init rb750_nand_init(void) -+{ -+ return platform_driver_register(&rb750_nand_driver); -+} -+ -+static void __exit rb750_nand_exit(void) -+{ -+ platform_driver_unregister(&rb750_nand_driver); -+} -+ -+module_init(rb750_nand_init); -+module_exit(rb750_nand_exit); -+ -+MODULE_DESCRIPTION(DRV_DESC); -+MODULE_VERSION(DRV_VERSION); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_LICENSE("GPL v2"); -diff -Nur linux-2.6.39.orig/drivers/mtd/wrt160nl_part.c linux-2.6.39/drivers/mtd/wrt160nl_part.c ---- linux-2.6.39.orig/drivers/mtd/wrt160nl_part.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/drivers/mtd/wrt160nl_part.c 2011-08-24 18:17:24.000000000 +0200 -@@ -0,0 +1,190 @@ -+/* -+ * Copyright (C) 2009 Christian Daniel -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ * -+ * TRX flash partition table. -+ * Based on ar7 map by Felix Fietkau -+ * -+ */ -+ -+#include -+#include -+#include -+ -+#include -+#include -+ -+struct cybertan_header { -+ char magic[4]; -+ u8 res1[4]; -+ char fw_date[3]; -+ char fw_ver[3]; -+ char id[4]; -+ char hw_ver; -+ char unused; -+ u8 flags[2]; -+ u8 res2[10]; -+}; -+ -+#define TRX_PARTS 6 -+#define TRX_MAGIC 0x30524448 -+#define TRX_MAX_OFFSET 3 -+ -+struct trx_header { -+ uint32_t magic; /* "HDR0" */ -+ uint32_t len; /* Length of file including header */ -+ uint32_t crc32; /* 32-bit CRC from flag_version to end of file */ -+ uint32_t flag_version; /* 0:15 flags, 16:31 version */ -+ uint32_t offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */ -+}; -+ -+#define IH_MAGIC 0x27051956 /* Image Magic Number */ -+#define IH_NMLEN 32 /* Image Name Length */ -+ -+struct uimage_header { -+ uint32_t ih_magic; /* Image Header Magic Number */ -+ uint32_t ih_hcrc; /* Image Header CRC Checksum */ -+ uint32_t ih_time; /* Image Creation Timestamp */ -+ uint32_t ih_size; /* Image Data Size */ -+ uint32_t ih_load; /* Data» Load Address */ -+ uint32_t ih_ep; /* Entry Point Address */ -+ uint32_t ih_dcrc; /* Image Data CRC Checksum */ -+ uint8_t ih_os; /* Operating System */ -+ uint8_t ih_arch; /* CPU architecture */ -+ uint8_t ih_type; /* Image Type */ -+ uint8_t ih_comp; /* Compression Type */ -+ uint8_t ih_name[IH_NMLEN]; /* Image Name */ -+}; -+ -+struct wrt160nl_header { -+ struct cybertan_header cybertan; -+ struct trx_header trx; -+ struct uimage_header uimage; -+} __attribute__ ((packed)); -+ -+static struct mtd_partition trx_parts[TRX_PARTS]; -+ -+#define WRT160NL_UBOOT_LEN 0x40000 -+#define WRT160NL_ART_LEN 0x10000 -+#define WRT160NL_NVRAM_LEN 0x10000 -+ -+static int wrt160nl_parse_partitions(struct mtd_info *master, -+ struct mtd_partition **pparts, -+ unsigned long origin) -+{ -+ struct wrt160nl_header *header; -+ struct trx_header *theader; -+ struct uimage_header *uheader; -+ size_t retlen; -+ unsigned int kernel_len; -+ unsigned int uboot_len = max(master->erasesize, WRT160NL_UBOOT_LEN); -+ unsigned int nvram_len = max(master->erasesize, WRT160NL_NVRAM_LEN); -+ unsigned int art_len = max(master->erasesize, WRT160NL_ART_LEN); -+ int ret; -+ -+ header = vmalloc(sizeof(*header)); -+ if (!header) { -+ return -ENOMEM; -+ goto out; -+ } -+ -+ ret = master->read(master, uboot_len, sizeof(*header), -+ &retlen, (void *) header); -+ if (ret) -+ goto free_hdr; -+ -+ if (retlen != sizeof(*header)) { -+ ret = -EIO; -+ goto free_hdr; -+ } -+ -+ if (strncmp(header->cybertan.magic, "NL16", 4) != 0) { -+ printk(KERN_NOTICE "%s: no WRT160NL signature found\n", -+ master->name); -+ goto free_hdr; -+ } -+ -+ theader = &header->trx; -+ if (le32_to_cpu(theader->magic) != TRX_MAGIC) { -+ printk(KERN_NOTICE "%s: no TRX header found\n", master->name); -+ goto free_hdr; -+ } -+ -+ uheader = &header->uimage; -+ if (uheader->ih_magic != IH_MAGIC) { -+ printk(KERN_NOTICE "%s: no uImage found\n", master->name); -+ goto free_hdr; -+ } -+ -+ kernel_len = le32_to_cpu(theader->offsets[1]) + -+ sizeof(struct cybertan_header); -+ -+ trx_parts[0].name = "u-boot"; -+ trx_parts[0].offset = 0; -+ trx_parts[0].size = uboot_len; -+ trx_parts[0].mask_flags = MTD_WRITEABLE; -+ -+ trx_parts[1].name = "kernel"; -+ trx_parts[1].offset = trx_parts[0].offset + trx_parts[0].size; -+ trx_parts[1].size = kernel_len; -+ trx_parts[1].mask_flags = 0; -+ -+ trx_parts[2].name = "rootfs"; -+ trx_parts[2].offset = trx_parts[1].offset + trx_parts[1].size; -+ trx_parts[2].size = master->size - uboot_len - nvram_len - art_len - -+ trx_parts[1].size; -+ trx_parts[2].mask_flags = 0; -+ -+ trx_parts[3].name = "nvram"; -+ trx_parts[3].offset = master->size - nvram_len - art_len; -+ trx_parts[3].size = nvram_len; -+ trx_parts[3].mask_flags = MTD_WRITEABLE; -+ -+ trx_parts[4].name = "art"; -+ trx_parts[4].offset = master->size - art_len; -+ trx_parts[4].size = art_len; -+ trx_parts[4].mask_flags = MTD_WRITEABLE; -+ -+ trx_parts[5].name = "firmware"; -+ trx_parts[5].offset = uboot_len; -+ trx_parts[5].size = master->size - uboot_len - nvram_len - art_len; -+ trx_parts[5].mask_flags = 0; -+ -+ *pparts = trx_parts; -+ ret = TRX_PARTS; -+ -+free_hdr: -+ vfree(header); -+out: -+ return ret; -+} -+ -+static struct mtd_part_parser wrt160nl_parser = { -+ .owner = THIS_MODULE, -+ .parse_fn = wrt160nl_parse_partitions, -+ .name = "wrt160nl", -+}; -+ -+static int __init wrt160nl_parser_init(void) -+{ -+ return register_mtd_parser(&wrt160nl_parser); -+} -+ -+module_init(wrt160nl_parser_init); -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Christian Daniel "); -diff -Nur linux-2.6.39.orig/drivers/net/Kconfig linux-2.6.39/drivers/net/Kconfig ---- linux-2.6.39.orig/drivers/net/Kconfig 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/drivers/net/Kconfig 2011-08-24 18:17:24.000000000 +0200 -@@ -2071,6 +2071,8 @@ - - The safe and default value for this is N. - -+source drivers/net/ag71xx/Kconfig -+ - config DL2K - tristate "DL2000/TC902x-based Gigabit Ethernet support" - depends on PCI -diff -Nur linux-2.6.39.orig/drivers/net/Makefile linux-2.6.39/drivers/net/Makefile ---- linux-2.6.39.orig/drivers/net/Makefile 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/drivers/net/Makefile 2011-08-24 18:17:24.000000000 +0200 -@@ -112,6 +112,7 @@ - # end link order section - # - -+obj-$(CONFIG_AG71XX) += ag71xx/ - obj-$(CONFIG_SUNDANCE) += sundance.o - obj-$(CONFIG_HAMACHI) += hamachi.o - obj-$(CONFIG_NET) += Space.o loopback.o -diff -Nur linux-2.6.39.orig/drivers/net/ag71xx/Kconfig linux-2.6.39/drivers/net/ag71xx/Kconfig ---- linux-2.6.39.orig/drivers/net/ag71xx/Kconfig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/drivers/net/ag71xx/Kconfig 2011-08-24 18:17:24.000000000 +0200 -@@ -0,0 +1,33 @@ -+config AG71XX -+ tristate "Atheros AR71xx built-in ethernet mac support" -+ depends on ATHEROS_AR71XX -+ select PHYLIB -+ help -+ If you wish to compile a kernel for AR71xx/91xx and enable -+ ethernet support, then you should always answer Y to this. -+ -+if AG71XX -+ -+config AG71XX_DEBUG -+ bool "Atheros AR71xx built-in ethernet driver debugging" -+ default n -+ help -+ Atheros AR71xx built-in ethernet driver debugging messages. -+ -+config AG71XX_DEBUG_FS -+ bool "Atheros AR71xx built-in ethernet driver debugfs support" -+ depends on DEBUG_FS -+ default n -+ help -+ Say Y, if you need access to various statistics provided by -+ the ag71xx driver. -+ -+config AG71XX_AR8216_SUPPORT -+ bool "special support for the Atheros AR8216 switch" -+ default n -+ default y if AR71XX_MACH_WNR2000 || AR71XX_MACH_MZK_W04NU -+ help -+ Say 'y' here if you want to enable special support for the -+ Atheros AR8216 switch found on some boards. -+ -+endif -diff -Nur linux-2.6.39.orig/drivers/net/ag71xx/Makefile linux-2.6.39/drivers/net/ag71xx/Makefile ---- linux-2.6.39.orig/drivers/net/ag71xx/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/drivers/net/ag71xx/Makefile 2011-08-24 18:17:24.000000000 +0200 -@@ -0,0 +1,15 @@ -+# -+# Makefile for the Atheros AR71xx built-in ethernet macs -+# -+ -+ag71xx-y += ag71xx_main.o -+ag71xx-y += ag71xx_ethtool.o -+ag71xx-y += ag71xx_phy.o -+ag71xx-y += ag71xx_mdio.o -+ag71xx-y += ag71xx_ar7240.o -+ -+ag71xx-$(CONFIG_AG71XX_DEBUG_FS) += ag71xx_debugfs.o -+ag71xx-$(CONFIG_AG71XX_AR8216_SUPPORT) += ag71xx_ar8216.o -+ -+obj-$(CONFIG_AG71XX) += ag71xx.o -+ -diff -Nur linux-2.6.39.orig/drivers/net/ag71xx/ag71xx.h linux-2.6.39/drivers/net/ag71xx/ag71xx.h ---- linux-2.6.39.orig/drivers/net/ag71xx/ag71xx.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/drivers/net/ag71xx/ag71xx.h 2011-08-24 18:17:24.000000000 +0200 -@@ -0,0 +1,518 @@ -+/* -+ * Atheros AR71xx built-in ethernet mac driver -+ * -+ * Copyright (C) 2008-2010 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Based on Atheros' AG7100 driver -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef __AG71XX_H -+#define __AG71XX_H -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include -+#include -+ -+#define AG71XX_DRV_NAME "ag71xx" -+#define AG71XX_DRV_VERSION "0.5.35" -+ -+#define AG71XX_NAPI_WEIGHT 64 -+#define AG71XX_OOM_REFILL (1 + HZ/10) -+ -+#define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE) -+#define AG71XX_INT_TX (AG71XX_INT_TX_PS) -+#define AG71XX_INT_RX (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF) -+ -+#define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX) -+#define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL) -+ -+#define AG71XX_TX_MTU_LEN 1540 -+#define AG71XX_RX_PKT_RESERVE 64 -+#define AG71XX_RX_PKT_SIZE \ -+ (AG71XX_RX_PKT_RESERVE + ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN) -+ -+#define AG71XX_TX_RING_SIZE_DEFAULT 64 -+#define AG71XX_RX_RING_SIZE_DEFAULT 128 -+ -+#define AG71XX_TX_RING_SIZE_MAX 256 -+#define AG71XX_RX_RING_SIZE_MAX 256 -+ -+#ifdef CONFIG_AG71XX_DEBUG -+#define DBG(fmt, args...) printk(KERN_DEBUG fmt, ## args) -+#else -+#define DBG(fmt, args...) do {} while (0) -+#endif -+ -+#define ag71xx_assert(_cond) \ -+do { \ -+ if (_cond) \ -+ break; \ -+ printk("%s,%d: assertion failed\n", __FILE__, __LINE__); \ -+ BUG(); \ -+} while (0) -+ -+struct ag71xx_desc { -+ u32 data; -+ u32 ctrl; -+#define DESC_EMPTY BIT(31) -+#define DESC_MORE BIT(24) -+#define DESC_PKTLEN_M 0xfff -+ u32 next; -+ u32 pad; -+} __attribute__((aligned(4))); -+ -+struct ag71xx_buf { -+ struct sk_buff *skb; -+ struct ag71xx_desc *desc; -+ dma_addr_t dma_addr; -+ unsigned long timestamp; -+}; -+ -+struct ag71xx_ring { -+ struct ag71xx_buf *buf; -+ u8 *descs_cpu; -+ dma_addr_t descs_dma; -+ unsigned int desc_size; -+ unsigned int curr; -+ unsigned int dirty; -+ unsigned int size; -+}; -+ -+struct ag71xx_mdio { -+ struct mii_bus *mii_bus; -+ int mii_irq[PHY_MAX_ADDR]; -+ void __iomem *mdio_base; -+ struct ag71xx_mdio_platform_data *pdata; -+}; -+ -+struct ag71xx_int_stats { -+ unsigned long rx_pr; -+ unsigned long rx_be; -+ unsigned long rx_of; -+ unsigned long tx_ps; -+ unsigned long tx_be; -+ unsigned long tx_ur; -+ unsigned long total; -+}; -+ -+struct ag71xx_napi_stats { -+ unsigned long napi_calls; -+ unsigned long rx_count; -+ unsigned long rx_packets; -+ unsigned long rx_packets_max; -+ unsigned long tx_count; -+ unsigned long tx_packets; -+ unsigned long tx_packets_max; -+ -+ unsigned long rx[AG71XX_NAPI_WEIGHT + 1]; -+ unsigned long tx[AG71XX_NAPI_WEIGHT + 1]; -+}; -+ -+struct ag71xx_debug { -+ struct dentry *debugfs_dir; -+ -+ struct ag71xx_int_stats int_stats; -+ struct ag71xx_napi_stats napi_stats; -+}; -+ -+struct ag71xx { -+ void __iomem *mac_base; -+ void __iomem *mii_ctrl; -+ -+ spinlock_t lock; -+ struct platform_device *pdev; -+ struct net_device *dev; -+ struct napi_struct napi; -+ u32 msg_enable; -+ -+ struct ag71xx_desc *stop_desc; -+ dma_addr_t stop_desc_dma; -+ -+ struct ag71xx_ring rx_ring; -+ struct ag71xx_ring tx_ring; -+ -+ struct mii_bus *mii_bus; -+ struct phy_device *phy_dev; -+ void *phy_priv; -+ -+ unsigned int link; -+ unsigned int speed; -+ int duplex; -+ -+ struct work_struct restart_work; -+ struct delayed_work link_work; -+ struct timer_list oom_timer; -+ -+#ifdef CONFIG_AG71XX_DEBUG_FS -+ struct ag71xx_debug debug; -+#endif -+}; -+ -+extern struct ethtool_ops ag71xx_ethtool_ops; -+void ag71xx_link_adjust(struct ag71xx *ag); -+ -+int ag71xx_mdio_driver_init(void) __init; -+void ag71xx_mdio_driver_exit(void); -+ -+int ag71xx_phy_connect(struct ag71xx *ag); -+void ag71xx_phy_disconnect(struct ag71xx *ag); -+void ag71xx_phy_start(struct ag71xx *ag); -+void ag71xx_phy_stop(struct ag71xx *ag); -+ -+static inline struct ag71xx_platform_data *ag71xx_get_pdata(struct ag71xx *ag) -+{ -+ return ag->pdev->dev.platform_data; -+} -+ -+static inline int ag71xx_desc_empty(struct ag71xx_desc *desc) -+{ -+ return (desc->ctrl & DESC_EMPTY) != 0; -+} -+ -+static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc) -+{ -+ return desc->ctrl & DESC_PKTLEN_M; -+} -+ -+/* Register offsets */ -+#define AG71XX_REG_MAC_CFG1 0x0000 -+#define AG71XX_REG_MAC_CFG2 0x0004 -+#define AG71XX_REG_MAC_IPG 0x0008 -+#define AG71XX_REG_MAC_HDX 0x000c -+#define AG71XX_REG_MAC_MFL 0x0010 -+#define AG71XX_REG_MII_CFG 0x0020 -+#define AG71XX_REG_MII_CMD 0x0024 -+#define AG71XX_REG_MII_ADDR 0x0028 -+#define AG71XX_REG_MII_CTRL 0x002c -+#define AG71XX_REG_MII_STATUS 0x0030 -+#define AG71XX_REG_MII_IND 0x0034 -+#define AG71XX_REG_MAC_IFCTL 0x0038 -+#define AG71XX_REG_MAC_ADDR1 0x0040 -+#define AG71XX_REG_MAC_ADDR2 0x0044 -+#define AG71XX_REG_FIFO_CFG0 0x0048 -+#define AG71XX_REG_FIFO_CFG1 0x004c -+#define AG71XX_REG_FIFO_CFG2 0x0050 -+#define AG71XX_REG_FIFO_CFG3 0x0054 -+#define AG71XX_REG_FIFO_CFG4 0x0058 -+#define AG71XX_REG_FIFO_CFG5 0x005c -+#define AG71XX_REG_FIFO_RAM0 0x0060 -+#define AG71XX_REG_FIFO_RAM1 0x0064 -+#define AG71XX_REG_FIFO_RAM2 0x0068 -+#define AG71XX_REG_FIFO_RAM3 0x006c -+#define AG71XX_REG_FIFO_RAM4 0x0070 -+#define AG71XX_REG_FIFO_RAM5 0x0074 -+#define AG71XX_REG_FIFO_RAM6 0x0078 -+#define AG71XX_REG_FIFO_RAM7 0x007c -+ -+#define AG71XX_REG_TX_CTRL 0x0180 -+#define AG71XX_REG_TX_DESC 0x0184 -+#define AG71XX_REG_TX_STATUS 0x0188 -+#define AG71XX_REG_RX_CTRL 0x018c -+#define AG71XX_REG_RX_DESC 0x0190 -+#define AG71XX_REG_RX_STATUS 0x0194 -+#define AG71XX_REG_INT_ENABLE 0x0198 -+#define AG71XX_REG_INT_STATUS 0x019c -+ -+#define AG71XX_REG_FIFO_DEPTH 0x01a8 -+#define AG71XX_REG_RX_SM 0x01b0 -+#define AG71XX_REG_TX_SM 0x01b4 -+ -+#define MAC_CFG1_TXE BIT(0) /* Tx Enable */ -+#define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */ -+#define MAC_CFG1_RXE BIT(2) /* Rx Enable */ -+#define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */ -+#define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */ -+#define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */ -+#define MAC_CFG1_LB BIT(8) /* Loopback mode */ -+#define MAC_CFG1_SR BIT(31) /* Soft Reset */ -+ -+#define MAC_CFG2_FDX BIT(0) -+#define MAC_CFG2_CRC_EN BIT(1) -+#define MAC_CFG2_PAD_CRC_EN BIT(2) -+#define MAC_CFG2_LEN_CHECK BIT(4) -+#define MAC_CFG2_HUGE_FRAME_EN BIT(5) -+#define MAC_CFG2_IF_1000 BIT(9) -+#define MAC_CFG2_IF_10_100 BIT(8) -+ -+#define FIFO_CFG0_WTM BIT(0) /* Watermark Module */ -+#define FIFO_CFG0_RXS BIT(1) /* Rx System Module */ -+#define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */ -+#define FIFO_CFG0_TXS BIT(3) /* Tx System Module */ -+#define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */ -+#define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \ -+ | FIFO_CFG0_TXS | FIFO_CFG0_TXF) -+ -+#define FIFO_CFG0_ENABLE_SHIFT 8 -+ -+#define FIFO_CFG4_DE BIT(0) /* Drop Event */ -+#define FIFO_CFG4_DV BIT(1) /* RX_DV Event */ -+#define FIFO_CFG4_FC BIT(2) /* False Carrier */ -+#define FIFO_CFG4_CE BIT(3) /* Code Error */ -+#define FIFO_CFG4_CR BIT(4) /* CRC error */ -+#define FIFO_CFG4_LM BIT(5) /* Length Mismatch */ -+#define FIFO_CFG4_LO BIT(6) /* Length out of range */ -+#define FIFO_CFG4_OK BIT(7) /* Packet is OK */ -+#define FIFO_CFG4_MC BIT(8) /* Multicast Packet */ -+#define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */ -+#define FIFO_CFG4_DR BIT(10) /* Dribble */ -+#define FIFO_CFG4_LE BIT(11) /* Long Event */ -+#define FIFO_CFG4_CF BIT(12) /* Control Frame */ -+#define FIFO_CFG4_PF BIT(13) /* Pause Frame */ -+#define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */ -+#define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */ -+#define FIFO_CFG4_FT BIT(16) /* Frame Truncated */ -+#define FIFO_CFG4_UC BIT(17) /* Unicast Packet */ -+ -+#define FIFO_CFG5_DE BIT(0) /* Drop Event */ -+#define FIFO_CFG5_DV BIT(1) /* RX_DV Event */ -+#define FIFO_CFG5_FC BIT(2) /* False Carrier */ -+#define FIFO_CFG5_CE BIT(3) /* Code Error */ -+#define FIFO_CFG5_LM BIT(4) /* Length Mismatch */ -+#define FIFO_CFG5_LO BIT(5) /* Length Out of Range */ -+#define FIFO_CFG5_OK BIT(6) /* Packet is OK */ -+#define FIFO_CFG5_MC BIT(7) /* Multicast Packet */ -+#define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */ -+#define FIFO_CFG5_DR BIT(9) /* Dribble */ -+#define FIFO_CFG5_CF BIT(10) /* Control Frame */ -+#define FIFO_CFG5_PF BIT(11) /* Pause Frame */ -+#define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */ -+#define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */ -+#define FIFO_CFG5_LE BIT(14) /* Long Event */ -+#define FIFO_CFG5_FT BIT(15) /* Frame Truncated */ -+#define FIFO_CFG5_16 BIT(16) /* unknown */ -+#define FIFO_CFG5_17 BIT(17) /* unknown */ -+#define FIFO_CFG5_SF BIT(18) /* Short Frame */ -+#define FIFO_CFG5_BM BIT(19) /* Byte Mode */ -+ -+#define AG71XX_INT_TX_PS BIT(0) -+#define AG71XX_INT_TX_UR BIT(1) -+#define AG71XX_INT_TX_BE BIT(3) -+#define AG71XX_INT_RX_PR BIT(4) -+#define AG71XX_INT_RX_OF BIT(6) -+#define AG71XX_INT_RX_BE BIT(7) -+ -+#define MAC_IFCTL_SPEED BIT(16) -+ -+#define MII_CFG_CLK_DIV_4 0 -+#define MII_CFG_CLK_DIV_6 2 -+#define MII_CFG_CLK_DIV_8 3 -+#define MII_CFG_CLK_DIV_10 4 -+#define MII_CFG_CLK_DIV_14 5 -+#define MII_CFG_CLK_DIV_20 6 -+#define MII_CFG_CLK_DIV_28 7 -+#define MII_CFG_RESET BIT(31) -+ -+#define MII_CMD_WRITE 0x0 -+#define MII_CMD_READ 0x1 -+#define MII_ADDR_SHIFT 8 -+#define MII_IND_BUSY BIT(0) -+#define MII_IND_INVALID BIT(2) -+ -+#define TX_CTRL_TXE BIT(0) /* Tx Enable */ -+ -+#define TX_STATUS_PS BIT(0) /* Packet Sent */ -+#define TX_STATUS_UR BIT(1) /* Tx Underrun */ -+#define TX_STATUS_BE BIT(3) /* Bus Error */ -+ -+#define RX_CTRL_RXE BIT(0) /* Rx Enable */ -+ -+#define RX_STATUS_PR BIT(0) /* Packet Received */ -+#define RX_STATUS_OF BIT(2) /* Rx Overflow */ -+#define RX_STATUS_BE BIT(3) /* Bus Error */ -+ -+#define MII_CTRL_IF_MASK 3 -+#define MII_CTRL_SPEED_SHIFT 4 -+#define MII_CTRL_SPEED_MASK 3 -+#define MII_CTRL_SPEED_10 0 -+#define MII_CTRL_SPEED_100 1 -+#define MII_CTRL_SPEED_1000 2 -+ -+static inline void ag71xx_check_reg_offset(struct ag71xx *ag, unsigned reg) -+{ -+ switch (reg) { -+ case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL: -+ case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS: -+ case AG71XX_REG_MII_CFG: -+ break; -+ -+ default: -+ BUG(); -+ } -+} -+ -+static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value) -+{ -+ ag71xx_check_reg_offset(ag, reg); -+ -+ __raw_writel(value, ag->mac_base + reg); -+ /* flush write */ -+ (void) __raw_readl(ag->mac_base + reg); -+} -+ -+static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg) -+{ -+ ag71xx_check_reg_offset(ag, reg); -+ -+ return __raw_readl(ag->mac_base + reg); -+} -+ -+static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask) -+{ -+ void __iomem *r; -+ -+ ag71xx_check_reg_offset(ag, reg); -+ -+ r = ag->mac_base + reg; -+ __raw_writel(__raw_readl(r) | mask, r); -+ /* flush write */ -+ (void)__raw_readl(r); -+} -+ -+static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask) -+{ -+ void __iomem *r; -+ -+ ag71xx_check_reg_offset(ag, reg); -+ -+ r = ag->mac_base + reg; -+ __raw_writel(__raw_readl(r) & ~mask, r); -+ /* flush write */ -+ (void) __raw_readl(r); -+} -+ -+static inline void ag71xx_int_enable(struct ag71xx *ag, u32 ints) -+{ -+ ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints); -+} -+ -+static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints) -+{ -+ ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints); -+} -+ -+static inline void ag71xx_mii_ctrl_wr(struct ag71xx *ag, u32 value) -+{ -+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); -+ -+ if (pdata->is_ar724x) -+ return; -+ -+ __raw_writel(value, ag->mii_ctrl); -+ -+ /* flush write */ -+ __raw_readl(ag->mii_ctrl); -+} -+ -+static inline u32 ag71xx_mii_ctrl_rr(struct ag71xx *ag) -+{ -+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); -+ -+ if (pdata->is_ar724x) -+ return 0xffffffff; -+ -+ return __raw_readl(ag->mii_ctrl); -+} -+ -+static inline void ag71xx_mii_ctrl_set_if(struct ag71xx *ag, -+ unsigned int mii_if) -+{ -+ u32 t; -+ -+ t = ag71xx_mii_ctrl_rr(ag); -+ t &= ~(MII_CTRL_IF_MASK); -+ t |= (mii_if & MII_CTRL_IF_MASK); -+ ag71xx_mii_ctrl_wr(ag, t); -+} -+ -+static inline void ag71xx_mii_ctrl_set_speed(struct ag71xx *ag, -+ unsigned int speed) -+{ -+ u32 t; -+ -+ t = ag71xx_mii_ctrl_rr(ag); -+ t &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT); -+ t |= (speed & MII_CTRL_SPEED_MASK) << MII_CTRL_SPEED_SHIFT; -+ ag71xx_mii_ctrl_wr(ag, t); -+} -+ -+#ifdef CONFIG_AG71XX_AR8216_SUPPORT -+void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb); -+int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb, -+ int pktlen); -+static inline int ag71xx_has_ar8216(struct ag71xx *ag) -+{ -+ return ag71xx_get_pdata(ag)->has_ar8216; -+} -+#else -+static inline void ag71xx_add_ar8216_header(struct ag71xx *ag, -+ struct sk_buff *skb) -+{ -+} -+ -+static inline int ag71xx_remove_ar8216_header(struct ag71xx *ag, -+ struct sk_buff *skb, -+ int pktlen) -+{ -+ return 0; -+} -+static inline int ag71xx_has_ar8216(struct ag71xx *ag) -+{ -+ return 0; -+} -+#endif -+ -+#ifdef CONFIG_AG71XX_DEBUG_FS -+int ag71xx_debugfs_root_init(void); -+void ag71xx_debugfs_root_exit(void); -+int ag71xx_debugfs_init(struct ag71xx *ag); -+void ag71xx_debugfs_exit(struct ag71xx *ag); -+void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, u32 status); -+void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, int rx, int tx); -+#else -+static inline int ag71xx_debugfs_root_init(void) { return 0; } -+static inline void ag71xx_debugfs_root_exit(void) {} -+static inline int ag71xx_debugfs_init(struct ag71xx *ag) { return 0; } -+static inline void ag71xx_debugfs_exit(struct ag71xx *ag) {} -+static inline void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, -+ u32 status) {} -+static inline void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, -+ int rx, int tx) {} -+#endif /* CONFIG_AG71XX_DEBUG_FS */ -+ -+void ag71xx_ar7240_start(struct ag71xx *ag); -+void ag71xx_ar7240_stop(struct ag71xx *ag); -+int ag71xx_ar7240_init(struct ag71xx *ag); -+void ag71xx_ar7240_cleanup(struct ag71xx *ag); -+ -+int ag71xx_mdio_mii_read(struct ag71xx_mdio *am, int addr, int reg); -+void ag71xx_mdio_mii_write(struct ag71xx_mdio *am, int addr, int reg, u16 val); -+ -+u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr, -+ unsigned reg_addr); -+int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr, -+ unsigned reg_addr, u16 reg_val); -+ -+#endif /* _AG71XX_H */ -diff -Nur linux-2.6.39.orig/drivers/net/ag71xx/ag71xx_ar7240.c linux-2.6.39/drivers/net/ag71xx/ag71xx_ar7240.c ---- linux-2.6.39.orig/drivers/net/ag71xx/ag71xx_ar7240.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/drivers/net/ag71xx/ag71xx_ar7240.c 2011-08-24 18:17:24.000000000 +0200 -@@ -0,0 +1,913 @@ -+/* -+ * Driver for the built-in ethernet switch of the Atheros AR7240 SoC -+ * Copyright (c) 2010 Gabor Juhos -+ * Copyright (c) 2010 Felix Fietkau -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "ag71xx.h" -+ -+#define BITM(_count) (BIT(_count) - 1) -+#define BITS(_shift, _count) (BITM(_count) << _shift) -+ -+#define AR7240_REG_MASK_CTRL 0x00 -+#define AR7240_MASK_CTRL_REVISION_M BITM(8) -+#define AR7240_MASK_CTRL_VERSION_M BITM(8) -+#define AR7240_MASK_CTRL_VERSION_S 8 -+#define AR7240_MASK_CTRL_SOFT_RESET BIT(31) -+ -+#define AR7240_REG_MAC_ADDR0 0x20 -+#define AR7240_REG_MAC_ADDR1 0x24 -+ -+#define AR7240_REG_FLOOD_MASK 0x2c -+#define AR7240_FLOOD_MASK_BROAD_TO_CPU BIT(26) -+ -+#define AR7240_REG_GLOBAL_CTRL 0x30 -+#define AR7240_GLOBAL_CTRL_MTU_M BITM(12) -+ -+#define AR7240_REG_VTU 0x0040 -+#define AR7240_VTU_OP BITM(3) -+#define AR7240_VTU_OP_NOOP 0x0 -+#define AR7240_VTU_OP_FLUSH 0x1 -+#define AR7240_VTU_OP_LOAD 0x2 -+#define AR7240_VTU_OP_PURGE 0x3 -+#define AR7240_VTU_OP_REMOVE_PORT 0x4 -+#define AR7240_VTU_ACTIVE BIT(3) -+#define AR7240_VTU_FULL BIT(4) -+#define AR7240_VTU_PORT BITS(8, 4) -+#define AR7240_VTU_PORT_S 8 -+#define AR7240_VTU_VID BITS(16, 12) -+#define AR7240_VTU_VID_S 16 -+#define AR7240_VTU_PRIO BITS(28, 3) -+#define AR7240_VTU_PRIO_S 28 -+#define AR7240_VTU_PRIO_EN BIT(31) -+ -+#define AR7240_REG_VTU_DATA 0x0044 -+#define AR7240_VTUDATA_MEMBER BITS(0, 10) -+#define AR7240_VTUDATA_VALID BIT(11) -+ -+#define AR7240_REG_ATU 0x50 -+#define AR7240_ATU_FLUSH_ALL 0x1 -+ -+#define AR7240_REG_AT_CTRL 0x5c -+#define AR7240_AT_CTRL_AGE_TIME BITS(0, 15) -+#define AR7240_AT_CTRL_AGE_EN BIT(17) -+#define AR7240_AT_CTRL_LEARN_CHANGE BIT(18) -+#define AR7240_AT_CTRL_ARP_EN BIT(20) -+ -+#define AR7240_REG_TAG_PRIORITY 0x70 -+ -+#define AR7240_REG_SERVICE_TAG 0x74 -+#define AR7240_SERVICE_TAG_M BITM(16) -+ -+#define AR7240_REG_CPU_PORT 0x78 -+#define AR7240_MIRROR_PORT_S 4 -+#define AR7240_CPU_PORT_EN BIT(8) -+ -+#define AR7240_REG_MIB_FUNCTION0 0x80 -+#define AR7240_MIB_TIMER_M BITM(16) -+#define AR7240_MIB_AT_HALF_EN BIT(16) -+#define AR7240_MIB_BUSY BIT(17) -+#define AR7240_MIB_FUNC_S 24 -+#define AR7240_MIB_FUNC_NO_OP 0x0 -+#define AR7240_MIB_FUNC_FLUSH 0x1 -+#define AR7240_MIB_FUNC_CAPTURE 0x3 -+ -+#define AR7240_REG_MDIO_CTRL 0x98 -+#define AR7240_MDIO_CTRL_DATA_M BITM(16) -+#define AR7240_MDIO_CTRL_REG_ADDR_S 16 -+#define AR7240_MDIO_CTRL_PHY_ADDR_S 21 -+#define AR7240_MDIO_CTRL_CMD_WRITE 0 -+#define AR7240_MDIO_CTRL_CMD_READ BIT(27) -+#define AR7240_MDIO_CTRL_MASTER_EN BIT(30) -+#define AR7240_MDIO_CTRL_BUSY BIT(31) -+ -+#define AR7240_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100) -+ -+#define AR7240_REG_PORT_STATUS(_port) (AR7240_REG_PORT_BASE((_port)) + 0x00) -+#define AR7240_PORT_STATUS_SPEED_M BITM(2) -+#define AR7240_PORT_STATUS_SPEED_10 0 -+#define AR7240_PORT_STATUS_SPEED_100 1 -+#define AR7240_PORT_STATUS_SPEED_1000 2 -+#define AR7240_PORT_STATUS_TXMAC BIT(2) -+#define AR7240_PORT_STATUS_RXMAC BIT(3) -+#define AR7240_PORT_STATUS_TXFLOW BIT(4) -+#define AR7240_PORT_STATUS_RXFLOW BIT(5) -+#define AR7240_PORT_STATUS_DUPLEX BIT(6) -+#define AR7240_PORT_STATUS_LINK_UP BIT(8) -+#define AR7240_PORT_STATUS_LINK_AUTO BIT(9) -+#define AR7240_PORT_STATUS_LINK_PAUSE BIT(10) -+ -+#define AR7240_REG_PORT_CTRL(_port) (AR7240_REG_PORT_BASE((_port)) + 0x04) -+#define AR7240_PORT_CTRL_STATE_M BITM(3) -+#define AR7240_PORT_CTRL_STATE_DISABLED 0 -+#define AR7240_PORT_CTRL_STATE_BLOCK 1 -+#define AR7240_PORT_CTRL_STATE_LISTEN 2 -+#define AR7240_PORT_CTRL_STATE_LEARN 3 -+#define AR7240_PORT_CTRL_STATE_FORWARD 4 -+#define AR7240_PORT_CTRL_LEARN_LOCK BIT(7) -+#define AR7240_PORT_CTRL_VLAN_MODE_S 8 -+#define AR7240_PORT_CTRL_VLAN_MODE_KEEP 0 -+#define AR7240_PORT_CTRL_VLAN_MODE_STRIP 1 -+#define AR7240_PORT_CTRL_VLAN_MODE_ADD 2 -+#define AR7240_PORT_CTRL_VLAN_MODE_DOUBLE_TAG 3 -+#define AR7240_PORT_CTRL_IGMP_SNOOP BIT(10) -+#define AR7240_PORT_CTRL_HEADER BIT(11) -+#define AR7240_PORT_CTRL_MAC_LOOP BIT(12) -+#define AR7240_PORT_CTRL_SINGLE_VLAN BIT(13) -+#define AR7240_PORT_CTRL_LEARN BIT(14) -+#define AR7240_PORT_CTRL_DOUBLE_TAG BIT(15) -+#define AR7240_PORT_CTRL_MIRROR_TX BIT(16) -+#define AR7240_PORT_CTRL_MIRROR_RX BIT(17) -+ -+#define AR7240_REG_PORT_VLAN(_port) (AR7240_REG_PORT_BASE((_port)) + 0x08) -+ -+#define AR7240_PORT_VLAN_DEFAULT_ID_S 0 -+#define AR7240_PORT_VLAN_DEST_PORTS_S 16 -+#define AR7240_PORT_VLAN_MODE_S 30 -+#define AR7240_PORT_VLAN_MODE_PORT_ONLY 0 -+#define AR7240_PORT_VLAN_MODE_PORT_FALLBACK 1 -+#define AR7240_PORT_VLAN_MODE_VLAN_ONLY 2 -+#define AR7240_PORT_VLAN_MODE_SECURE 3 -+ -+ -+#define AR7240_REG_STATS_BASE(_port) (0x20000 + (_port) * 0x100) -+ -+#define AR7240_STATS_RXBROAD 0x00 -+#define AR7240_STATS_RXPAUSE 0x04 -+#define AR7240_STATS_RXMULTI 0x08 -+#define AR7240_STATS_RXFCSERR 0x0c -+#define AR7240_STATS_RXALIGNERR 0x10 -+#define AR7240_STATS_RXRUNT 0x14 -+#define AR7240_STATS_RXFRAGMENT 0x18 -+#define AR7240_STATS_RX64BYTE 0x1c -+#define AR7240_STATS_RX128BYTE 0x20 -+#define AR7240_STATS_RX256BYTE 0x24 -+#define AR7240_STATS_RX512BYTE 0x28 -+#define AR7240_STATS_RX1024BYTE 0x2c -+#define AR7240_STATS_RX1518BYTE 0x30 -+#define AR7240_STATS_RXMAXBYTE 0x34 -+#define AR7240_STATS_RXTOOLONG 0x38 -+#define AR7240_STATS_RXGOODBYTE 0x3c -+#define AR7240_STATS_RXBADBYTE 0x44 -+#define AR7240_STATS_RXOVERFLOW 0x4c -+#define AR7240_STATS_FILTERED 0x50 -+#define AR7240_STATS_TXBROAD 0x54 -+#define AR7240_STATS_TXPAUSE 0x58 -+#define AR7240_STATS_TXMULTI 0x5c -+#define AR7240_STATS_TXUNDERRUN 0x60 -+#define AR7240_STATS_TX64BYTE 0x64 -+#define AR7240_STATS_TX128BYTE 0x68 -+#define AR7240_STATS_TX256BYTE 0x6c -+#define AR7240_STATS_TX512BYTE 0x70 -+#define AR7240_STATS_TX1024BYTE 0x74 -+#define AR7240_STATS_TX1518BYTE 0x78 -+#define AR7240_STATS_TXMAXBYTE 0x7c -+#define AR7240_STATS_TXOVERSIZE 0x80 -+#define AR7240_STATS_TXBYTE 0x84 -+#define AR7240_STATS_TXCOLLISION 0x8c -+#define AR7240_STATS_TXABORTCOL 0x90 -+#define AR7240_STATS_TXMULTICOL 0x94 -+#define AR7240_STATS_TXSINGLECOL 0x98 -+#define AR7240_STATS_TXEXCDEFER 0x9c -+#define AR7240_STATS_TXDEFER 0xa0 -+#define AR7240_STATS_TXLATECOL 0xa4 -+ -+#define AR7240_PORT_CPU 0 -+#define AR7240_NUM_PORTS 6 -+#define AR7240_NUM_PHYS 5 -+ -+#define AR7240_PHY_ID1 0x004d -+#define AR7240_PHY_ID2 0xd041 -+ -+#define AR7240_PORT_MASK(_port) BIT((_port)) -+#define AR7240_PORT_MASK_ALL BITM(AR7240_NUM_PORTS) -+#define AR7240_PORT_MASK_BUT(_port) (AR7240_PORT_MASK_ALL & ~BIT((_port))) -+ -+#define AR7240_MAX_VLANS 16 -+ -+#define sw_to_ar7240(_dev) container_of(_dev, struct ar7240sw, swdev) -+ -+struct ar7240sw { -+ struct mii_bus *mii_bus; -+ struct switch_dev swdev; -+ bool vlan; -+ u16 vlan_id[AR7240_MAX_VLANS]; -+ u8 vlan_table[AR7240_MAX_VLANS]; -+ u8 vlan_tagged; -+ u16 pvid[AR7240_NUM_PORTS]; -+}; -+ -+struct ar7240sw_hw_stat { -+ char string[ETH_GSTRING_LEN]; -+ int sizeof_stat; -+ int reg; -+}; -+ -+static DEFINE_MUTEX(reg_mutex); -+ -+static inline void ar7240sw_init(struct ar7240sw *as, struct mii_bus *mii) -+{ -+ as->mii_bus = mii; -+} -+ -+static inline u16 mk_phy_addr(u32 reg) -+{ -+ return 0x17 & ((reg >> 4) | 0x10); -+} -+ -+static inline u16 mk_phy_reg(u32 reg) -+{ -+ return (reg << 1) & 0x1e; -+} -+ -+static inline u16 mk_high_addr(u32 reg) -+{ -+ return (reg >> 7) & 0x1ff; -+} -+ -+static u32 __ar7240sw_reg_read(struct mii_bus *mii, u32 reg) -+{ -+ unsigned long flags; -+ u16 phy_addr; -+ u16 phy_reg; -+ u32 hi, lo; -+ -+ reg = (reg & 0xfffffffc) >> 2; -+ phy_addr = mk_phy_addr(reg); -+ phy_reg = mk_phy_reg(reg); -+ -+ local_irq_save(flags); -+ ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg)); -+ lo = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg); -+ hi = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg + 1); -+ local_irq_restore(flags); -+ -+ return (hi << 16) | lo; -+} -+ -+static void __ar7240sw_reg_write(struct mii_bus *mii, u32 reg, u32 val) -+{ -+ unsigned long flags; -+ u16 phy_addr; -+ u16 phy_reg; -+ -+ reg = (reg & 0xfffffffc) >> 2; -+ phy_addr = mk_phy_addr(reg); -+ phy_reg = mk_phy_reg(reg); -+ -+ local_irq_save(flags); -+ ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg)); -+ ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg + 1, (val >> 16)); -+ ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg, (val & 0xffff)); -+ local_irq_restore(flags); -+} -+ -+static u32 ar7240sw_reg_read(struct mii_bus *mii, u32 reg_addr) -+{ -+ u32 ret; -+ -+ mutex_lock(®_mutex); -+ ret = __ar7240sw_reg_read(mii, reg_addr); -+ mutex_unlock(®_mutex); -+ -+ return ret; -+} -+ -+static void ar7240sw_reg_write(struct mii_bus *mii, u32 reg_addr, u32 reg_val) -+{ -+ mutex_lock(®_mutex); -+ __ar7240sw_reg_write(mii, reg_addr, reg_val); -+ mutex_unlock(®_mutex); -+} -+ -+static u32 ar7240sw_reg_rmw(struct mii_bus *mii, u32 reg, u32 mask, u32 val) -+{ -+ u32 t; -+ -+ mutex_lock(®_mutex); -+ t = __ar7240sw_reg_read(mii, reg); -+ t &= ~mask; -+ t |= val; -+ __ar7240sw_reg_write(mii, reg, t); -+ mutex_unlock(®_mutex); -+ -+ return t; -+} -+ -+static void ar7240sw_reg_set(struct mii_bus *mii, u32 reg, u32 val) -+{ -+ u32 t; -+ -+ mutex_lock(®_mutex); -+ t = __ar7240sw_reg_read(mii, reg); -+ t |= val; -+ __ar7240sw_reg_write(mii, reg, t); -+ mutex_unlock(®_mutex); -+} -+ -+static int __ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val, -+ unsigned timeout) -+{ -+ int i; -+ -+ for (i = 0; i < timeout; i++) { -+ u32 t; -+ -+ t = __ar7240sw_reg_read(mii, reg); -+ if ((t & mask) == val) -+ return 0; -+ -+ msleep(1); -+ } -+ -+ return -ETIMEDOUT; -+} -+ -+static int ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val, -+ unsigned timeout) -+{ -+ int ret; -+ -+ mutex_lock(®_mutex); -+ ret = __ar7240sw_reg_wait(mii, reg, mask, val, timeout); -+ mutex_unlock(®_mutex); -+ return ret; -+} -+ -+u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr, -+ unsigned reg_addr) -+{ -+ u32 t, val = 0xffff; -+ int err; -+ -+ if (phy_addr >= AR7240_NUM_PHYS) -+ return 0xffff; -+ -+ mutex_lock(®_mutex); -+ t = (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) | -+ (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) | -+ AR7240_MDIO_CTRL_MASTER_EN | -+ AR7240_MDIO_CTRL_BUSY | -+ AR7240_MDIO_CTRL_CMD_READ; -+ -+ __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t); -+ err = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL, -+ AR7240_MDIO_CTRL_BUSY, 0, 5); -+ if (!err) -+ val = __ar7240sw_reg_read(mii, AR7240_REG_MDIO_CTRL); -+ mutex_unlock(®_mutex); -+ -+ return val & AR7240_MDIO_CTRL_DATA_M; -+} -+ -+int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr, -+ unsigned reg_addr, u16 reg_val) -+{ -+ u32 t; -+ int ret; -+ -+ if (phy_addr >= AR7240_NUM_PHYS) -+ return -EINVAL; -+ -+ mutex_lock(®_mutex); -+ t = (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) | -+ (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) | -+ AR7240_MDIO_CTRL_MASTER_EN | -+ AR7240_MDIO_CTRL_BUSY | -+ AR7240_MDIO_CTRL_CMD_WRITE | -+ reg_val; -+ -+ __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t); -+ ret = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL, -+ AR7240_MDIO_CTRL_BUSY, 0, 5); -+ mutex_unlock(®_mutex); -+ -+ return ret; -+} -+ -+static int ar7240sw_capture_stats(struct ar7240sw *as) -+{ -+ struct mii_bus *mii = as->mii_bus; -+ int ret; -+ -+ /* Capture the hardware statistics for all ports */ -+ ar7240sw_reg_write(mii, AR7240_REG_MIB_FUNCTION0, -+ (AR7240_MIB_FUNC_CAPTURE << AR7240_MIB_FUNC_S)); -+ -+ /* Wait for the capturing to complete. */ -+ ret = ar7240sw_reg_wait(mii, AR7240_REG_MIB_FUNCTION0, -+ AR7240_MIB_BUSY, 0, 10); -+ return ret; -+} -+ -+static void ar7240sw_disable_port(struct ar7240sw *as, unsigned port) -+{ -+ ar7240sw_reg_write(as->mii_bus, AR7240_REG_PORT_CTRL(port), -+ AR7240_PORT_CTRL_STATE_DISABLED); -+} -+ -+static void ar7240sw_setup(struct ar7240sw *as) -+{ -+ struct mii_bus *mii = as->mii_bus; -+ -+ /* Enable CPU port, and disable mirror port */ -+ ar7240sw_reg_write(mii, AR7240_REG_CPU_PORT, -+ AR7240_CPU_PORT_EN | -+ (15 << AR7240_MIRROR_PORT_S)); -+ -+ /* Setup TAG priority mapping */ -+ ar7240sw_reg_write(mii, AR7240_REG_TAG_PRIORITY, 0xfa50); -+ -+ /* Enable ARP frame acknowledge, aging, MAC replacing */ -+ ar7240sw_reg_write(mii, AR7240_REG_AT_CTRL, -+ 0x2b /* 5 min age time */ | -+ AR7240_AT_CTRL_AGE_EN | -+ AR7240_AT_CTRL_ARP_EN | -+ AR7240_AT_CTRL_LEARN_CHANGE); -+ -+ /* Enable Broadcast frames transmitted to the CPU */ -+ ar7240sw_reg_set(mii, AR7240_REG_FLOOD_MASK, -+ AR7240_FLOOD_MASK_BROAD_TO_CPU); -+ -+ /* setup MTU */ -+ ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL, AR7240_GLOBAL_CTRL_MTU_M, -+ 1536); -+ -+ /* setup Service TAG */ -+ ar7240sw_reg_rmw(mii, AR7240_REG_SERVICE_TAG, AR7240_SERVICE_TAG_M, 0); -+} -+ -+static int ar7240sw_reset(struct ar7240sw *as) -+{ -+ struct mii_bus *mii = as->mii_bus; -+ int ret; -+ int i; -+ -+ /* Set all ports to disabled state. */ -+ for (i = 0; i < AR7240_NUM_PORTS; i++) -+ ar7240sw_disable_port(as, i); -+ -+ /* Wait for transmit queues to drain. */ -+ msleep(2); -+ -+ /* Reset the switch. */ -+ ar7240sw_reg_write(mii, AR7240_REG_MASK_CTRL, -+ AR7240_MASK_CTRL_SOFT_RESET); -+ -+ ret = ar7240sw_reg_wait(mii, AR7240_REG_MASK_CTRL, -+ AR7240_MASK_CTRL_SOFT_RESET, 0, 1000); -+ -+ ar7240sw_setup(as); -+ return ret; -+} -+ -+static void ar7240sw_setup_port(struct ar7240sw *as, unsigned port, u8 portmask) -+{ -+ struct mii_bus *mii = as->mii_bus; -+ u32 ctrl; -+ u32 dest_ports; -+ u32 vlan; -+ -+ ctrl = AR7240_PORT_CTRL_STATE_FORWARD | AR7240_PORT_CTRL_LEARN | -+ AR7240_PORT_CTRL_SINGLE_VLAN; -+ -+ if (port == AR7240_PORT_CPU) { -+ ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port), -+ AR7240_PORT_STATUS_SPEED_1000 | -+ AR7240_PORT_STATUS_TXFLOW | -+ AR7240_PORT_STATUS_RXFLOW | -+ AR7240_PORT_STATUS_TXMAC | -+ AR7240_PORT_STATUS_RXMAC | -+ AR7240_PORT_STATUS_DUPLEX); -+ } else { -+ ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port), -+ AR7240_PORT_STATUS_LINK_AUTO); -+ } -+ -+ /* Set the default VID for this port */ -+ if (as->vlan) { -+ vlan = as->vlan_id[as->pvid[port]]; -+ vlan |= AR7240_PORT_VLAN_MODE_SECURE << -+ AR7240_PORT_VLAN_MODE_S; -+ } else { -+ vlan = port; -+ vlan |= AR7240_PORT_VLAN_MODE_PORT_ONLY << -+ AR7240_PORT_VLAN_MODE_S; -+ } -+ -+ if (as->vlan && (as->vlan_tagged & BIT(port))) { -+ ctrl |= AR7240_PORT_CTRL_VLAN_MODE_ADD << -+ AR7240_PORT_CTRL_VLAN_MODE_S; -+ } else { -+ ctrl |= AR7240_PORT_CTRL_VLAN_MODE_STRIP << -+ AR7240_PORT_CTRL_VLAN_MODE_S; -+ } -+ -+ if (!portmask) { -+ if (port == AR7240_PORT_CPU) -+ portmask = AR7240_PORT_MASK_BUT(AR7240_PORT_CPU); -+ else -+ portmask = AR7240_PORT_MASK(AR7240_PORT_CPU); -+ } -+ -+ /* allow the port to talk to all other ports, but exclude its -+ * own ID to prevent frames from being reflected back to the -+ * port that they came from */ -+ dest_ports = AR7240_PORT_MASK_BUT(port); -+ -+ /* set default VID and and destination ports for this VLAN */ -+ vlan |= (portmask << AR7240_PORT_VLAN_DEST_PORTS_S); -+ -+ ar7240sw_reg_write(mii, AR7240_REG_PORT_CTRL(port), ctrl); -+ ar7240sw_reg_write(mii, AR7240_REG_PORT_VLAN(port), vlan); -+} -+ -+static int ar7240_set_addr(struct ar7240sw *as, u8 *addr) -+{ -+ struct mii_bus *mii = as->mii_bus; -+ u32 t; -+ -+ t = (addr[4] << 8) | addr[5]; -+ ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR0, t); -+ -+ t = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]; -+ ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR1, t); -+ -+ return 0; -+} -+ -+static int -+ar7240_set_vid(struct switch_dev *dev, const struct switch_attr *attr, -+ struct switch_val *val) -+{ -+ struct ar7240sw *as = sw_to_ar7240(dev); -+ as->vlan_id[val->port_vlan] = val->value.i; -+ return 0; -+} -+ -+static int -+ar7240_get_vid(struct switch_dev *dev, const struct switch_attr *attr, -+ struct switch_val *val) -+{ -+ struct ar7240sw *as = sw_to_ar7240(dev); -+ val->value.i = as->vlan_id[val->port_vlan]; -+ return 0; -+} -+ -+static int -+ar7240_set_pvid(struct switch_dev *dev, int port, int vlan) -+{ -+ struct ar7240sw *as = sw_to_ar7240(dev); -+ -+ /* make sure no invalid PVIDs get set */ -+ -+ if (vlan >= dev->vlans) -+ return -EINVAL; -+ -+ as->pvid[port] = vlan; -+ return 0; -+} -+ -+static int -+ar7240_get_pvid(struct switch_dev *dev, int port, int *vlan) -+{ -+ struct ar7240sw *as = sw_to_ar7240(dev); -+ *vlan = as->pvid[port]; -+ return 0; -+} -+ -+static int -+ar7240_get_ports(struct switch_dev *dev, struct switch_val *val) -+{ -+ struct ar7240sw *as = sw_to_ar7240(dev); -+ u8 ports = as->vlan_table[val->port_vlan]; -+ int i; -+ -+ val->len = 0; -+ for (i = 0; i < AR7240_NUM_PORTS; i++) { -+ struct switch_port *p; -+ -+ if (!(ports & (1 << i))) -+ continue; -+ -+ p = &val->value.ports[val->len++]; -+ p->id = i; -+ if (as->vlan_tagged & (1 << i)) -+ p->flags = (1 << SWITCH_PORT_FLAG_TAGGED); -+ else -+ p->flags = 0; -+ } -+ return 0; -+} -+ -+static int -+ar7240_set_ports(struct switch_dev *dev, struct switch_val *val) -+{ -+ struct ar7240sw *as = sw_to_ar7240(dev); -+ u8 *vt = &as->vlan_table[val->port_vlan]; -+ int i, j; -+ -+ *vt = 0; -+ for (i = 0; i < val->len; i++) { -+ struct switch_port *p = &val->value.ports[i]; -+ -+ if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) -+ as->vlan_tagged |= (1 << p->id); -+ else { -+ as->vlan_tagged &= ~(1 << p->id); -+ as->pvid[p->id] = val->port_vlan; -+ -+ /* make sure that an untagged port does not -+ * appear in other vlans */ -+ for (j = 0; j < AR7240_MAX_VLANS; j++) { -+ if (j == val->port_vlan) -+ continue; -+ as->vlan_table[j] &= ~(1 << p->id); -+ } -+ } -+ -+ *vt |= 1 << p->id; -+ } -+ return 0; -+} -+ -+static int -+ar7240_set_vlan(struct switch_dev *dev, const struct switch_attr *attr, -+ struct switch_val *val) -+{ -+ struct ar7240sw *as = sw_to_ar7240(dev); -+ as->vlan = !!val->value.i; -+ return 0; -+} -+ -+static int -+ar7240_get_vlan(struct switch_dev *dev, const struct switch_attr *attr, -+ struct switch_val *val) -+{ -+ struct ar7240sw *as = sw_to_ar7240(dev); -+ val->value.i = as->vlan; -+ return 0; -+} -+ -+ -+static void -+ar7240_vtu_op(struct ar7240sw *as, u32 op, u32 val) -+{ -+ struct mii_bus *mii = as->mii_bus; -+ -+ if (ar7240sw_reg_wait(mii, AR7240_REG_VTU, AR7240_VTU_ACTIVE, 0, 5)) -+ return; -+ -+ if ((op & AR7240_VTU_OP) == AR7240_VTU_OP_LOAD) { -+ val &= AR7240_VTUDATA_MEMBER; -+ val |= AR7240_VTUDATA_VALID; -+ ar7240sw_reg_write(mii, AR7240_REG_VTU_DATA, val); -+ } -+ op |= AR7240_VTU_ACTIVE; -+ ar7240sw_reg_write(mii, AR7240_REG_VTU, op); -+} -+ -+static int -+ar7240_hw_apply(struct switch_dev *dev) -+{ -+ struct ar7240sw *as = sw_to_ar7240(dev); -+ u8 portmask[AR7240_NUM_PORTS]; -+ int i, j; -+ -+ /* flush all vlan translation unit entries */ -+ ar7240_vtu_op(as, AR7240_VTU_OP_FLUSH, 0); -+ -+ memset(portmask, 0, sizeof(portmask)); -+ if (as->vlan) { -+ /* calculate the port destination masks and load vlans -+ * into the vlan translation unit */ -+ for (j = 0; j < AR7240_MAX_VLANS; j++) { -+ u8 vp = as->vlan_table[j]; -+ -+ if (!vp) -+ continue; -+ -+ for (i = 0; i < AR7240_NUM_PORTS; i++) { -+ u8 mask = (1 << i); -+ if (vp & mask) -+ portmask[i] |= vp & ~mask; -+ } -+ -+ ar7240_vtu_op(as, -+ AR7240_VTU_OP_LOAD | -+ (as->vlan_id[j] << AR7240_VTU_VID_S), -+ as->vlan_table[j]); -+ } -+ } else { -+ /* vlan disabled: -+ * isolate all ports, but connect them to the cpu port */ -+ for (i = 0; i < AR7240_NUM_PORTS; i++) { -+ if (i == AR7240_PORT_CPU) -+ continue; -+ -+ portmask[i] = 1 << AR7240_PORT_CPU; -+ portmask[AR7240_PORT_CPU] |= (1 << i); -+ } -+ } -+ -+ /* update the port destination mask registers and tag settings */ -+ for (i = 0; i < AR7240_NUM_PORTS; i++) -+ ar7240sw_setup_port(as, i, portmask[i]); -+ -+ return 0; -+} -+ -+static int -+ar7240_reset_switch(struct switch_dev *dev) -+{ -+ struct ar7240sw *as = sw_to_ar7240(dev); -+ ar7240sw_reset(as); -+ return 0; -+} -+ -+static struct switch_attr ar7240_globals[] = { -+ { -+ .type = SWITCH_TYPE_INT, -+ .name = "enable_vlan", -+ .description = "Enable VLAN mode", -+ .set = ar7240_set_vlan, -+ .get = ar7240_get_vlan, -+ .max = 1 -+ }, -+}; -+ -+static struct switch_attr ar7240_port[] = { -+}; -+ -+static struct switch_attr ar7240_vlan[] = { -+ { -+ .type = SWITCH_TYPE_INT, -+ .name = "vid", -+ .description = "VLAN ID", -+ .set = ar7240_set_vid, -+ .get = ar7240_get_vid, -+ .max = 4094, -+ }, -+}; -+ -+static const struct switch_dev_ops ar7240_ops = { -+ .attr_global = { -+ .attr = ar7240_globals, -+ .n_attr = ARRAY_SIZE(ar7240_globals), -+ }, -+ .attr_port = { -+ .attr = ar7240_port, -+ .n_attr = ARRAY_SIZE(ar7240_port), -+ }, -+ .attr_vlan = { -+ .attr = ar7240_vlan, -+ .n_attr = ARRAY_SIZE(ar7240_vlan), -+ }, -+ .get_port_pvid = ar7240_get_pvid, -+ .set_port_pvid = ar7240_set_pvid, -+ .get_vlan_ports = ar7240_get_ports, -+ .set_vlan_ports = ar7240_set_ports, -+ .apply_config = ar7240_hw_apply, -+ .reset_switch = ar7240_reset_switch, -+}; -+ -+static struct ar7240sw *ar7240_probe(struct ag71xx *ag) -+{ -+ struct mii_bus *mii = ag->mii_bus; -+ struct ar7240sw *as; -+ struct switch_dev *swdev; -+ u32 ctrl; -+ u16 phy_id1; -+ u16 phy_id2; -+ u8 ver; -+ int i; -+ -+ as = kzalloc(sizeof(*as), GFP_KERNEL); -+ if (!as) -+ return NULL; -+ -+ ar7240sw_init(as, mii); -+ -+ ctrl = ar7240sw_reg_read(mii, AR7240_REG_MASK_CTRL); -+ -+ ver = (ctrl >> AR7240_MASK_CTRL_VERSION_S) & AR7240_MASK_CTRL_VERSION_M; -+ if (ver != 1) { -+ pr_err("%s: unsupported chip, ctrl=%08x\n", -+ ag->dev->name, ctrl); -+ return NULL; -+ } -+ -+ phy_id1 = ar7240sw_phy_read(mii, 0, MII_PHYSID1); -+ phy_id2 = ar7240sw_phy_read(mii, 0, MII_PHYSID2); -+ if (phy_id1 != AR7240_PHY_ID1 || phy_id2 != AR7240_PHY_ID2) { -+ pr_err("%s: unknown phy id '%04x:%04x'\n", -+ ag->dev->name, phy_id1, phy_id2); -+ return NULL; -+ } -+ -+ swdev = &as->swdev; -+ swdev->name = "AR7240 built-in switch"; -+ swdev->ports = AR7240_NUM_PORTS; -+ swdev->cpu_port = AR7240_PORT_CPU; -+ swdev->vlans = AR7240_MAX_VLANS; -+ swdev->ops = &ar7240_ops; -+ -+ if (register_switch(&as->swdev, ag->dev) < 0) { -+ kfree(as); -+ return NULL; -+ } -+ -+ pr_info("%s: Found an AR7240 built-in switch\n", ag->dev->name); -+ -+ /* initialize defaults */ -+ for (i = 0; i < AR7240_MAX_VLANS; i++) -+ as->vlan_id[i] = i; -+ -+ as->vlan_table[0] = AR7240_PORT_MASK_ALL; -+ -+ return as; -+} -+ -+static void link_function(struct work_struct *work) { -+ struct ag71xx *ag = container_of(work, struct ag71xx, link_work.work); -+ unsigned long flags; -+ int i; -+ int status = 0; -+ -+ for (i = 0; i < 4; i++) { -+ int link = ar7240sw_phy_read(ag->mii_bus, i, MII_BMSR); -+ if(link & BMSR_LSTATUS) { -+ status = 1; -+ break; -+ } -+ } -+ -+ spin_lock_irqsave(&ag->lock, flags); -+ if(status != ag->link) { -+ ag->link = status; -+ ag71xx_link_adjust(ag); -+ } -+ spin_unlock_irqrestore(&ag->lock, flags); -+ -+ schedule_delayed_work(&ag->link_work, HZ / 2); -+} -+ -+void ag71xx_ar7240_start(struct ag71xx *ag) -+{ -+ struct ar7240sw *as = ag->phy_priv; -+ -+ ar7240sw_reset(as); -+ -+ ag->speed = SPEED_1000; -+ ag->duplex = 1; -+ -+ ar7240_set_addr(as, ag->dev->dev_addr); -+ ar7240_hw_apply(&as->swdev); -+ -+ schedule_delayed_work(&ag->link_work, HZ / 10); -+} -+ -+void ag71xx_ar7240_stop(struct ag71xx *ag) -+{ -+ cancel_delayed_work_sync(&ag->link_work); -+} -+ -+int __devinit ag71xx_ar7240_init(struct ag71xx *ag) -+{ -+ struct ar7240sw *as; -+ -+ as = ar7240_probe(ag); -+ if (!as) -+ return -ENODEV; -+ -+ ag->phy_priv = as; -+ ar7240sw_reset(as); -+ -+ INIT_DELAYED_WORK(&ag->link_work, link_function); -+ -+ return 0; -+} -+ -+void ag71xx_ar7240_cleanup(struct ag71xx *ag) -+{ -+ struct ar7240sw *as = ag->phy_priv; -+ -+ if (!as) -+ return; -+ -+ unregister_switch(&as->swdev); -+ kfree(as); -+ ag->phy_priv = NULL; -+} -diff -Nur linux-2.6.39.orig/drivers/net/ag71xx/ag71xx_ar8216.c linux-2.6.39/drivers/net/ag71xx/ag71xx_ar8216.c ---- linux-2.6.39.orig/drivers/net/ag71xx/ag71xx_ar8216.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/drivers/net/ag71xx/ag71xx_ar8216.c 2011-08-24 18:17:24.000000000 +0200 -@@ -0,0 +1,44 @@ -+/* -+ * Atheros AR71xx built-in ethernet mac driver -+ * Special support for the Atheros ar8216 switch chip -+ * -+ * Copyright (C) 2009-2010 Gabor Juhos -+ * -+ * Based on Atheros' AG7100 driver -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include "ag71xx.h" -+ -+#define AR8216_PACKET_TYPE_MASK 0xf -+#define AR8216_PACKET_TYPE_NORMAL 0 -+ -+#define AR8216_HEADER_LEN 2 -+ -+void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb) -+{ -+ skb_push(skb, AR8216_HEADER_LEN); -+ skb->data[0] = 0x10; -+ skb->data[1] = 0x80; -+} -+ -+int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb, -+ int pktlen) -+{ -+ u8 type; -+ -+ type = skb->data[1] & AR8216_PACKET_TYPE_MASK; -+ switch (type) { -+ case AR8216_PACKET_TYPE_NORMAL: -+ break; -+ -+ default: -+ return -EINVAL; -+ } -+ -+ skb_pull(skb, AR8216_HEADER_LEN); -+ return 0; -+} -diff -Nur linux-2.6.39.orig/drivers/net/ag71xx/ag71xx_debugfs.c linux-2.6.39/drivers/net/ag71xx/ag71xx_debugfs.c ---- linux-2.6.39.orig/drivers/net/ag71xx/ag71xx_debugfs.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/drivers/net/ag71xx/ag71xx_debugfs.c 2011-08-24 18:17:24.000000000 +0200 -@@ -0,0 +1,280 @@ -+/* -+ * Atheros AR71xx built-in ethernet mac driver -+ * -+ * Copyright (C) 2008-2010 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Based on Atheros' AG7100 driver -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+ -+#include "ag71xx.h" -+ -+static struct dentry *ag71xx_debugfs_root; -+ -+static int ag71xx_debugfs_generic_open(struct inode *inode, struct file *file) -+{ -+ file->private_data = inode->i_private; -+ return 0; -+} -+ -+void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, u32 status) -+{ -+ if (status) -+ ag->debug.int_stats.total++; -+ if (status & AG71XX_INT_TX_PS) -+ ag->debug.int_stats.tx_ps++; -+ if (status & AG71XX_INT_TX_UR) -+ ag->debug.int_stats.tx_ur++; -+ if (status & AG71XX_INT_TX_BE) -+ ag->debug.int_stats.tx_be++; -+ if (status & AG71XX_INT_RX_PR) -+ ag->debug.int_stats.rx_pr++; -+ if (status & AG71XX_INT_RX_OF) -+ ag->debug.int_stats.rx_of++; -+ if (status & AG71XX_INT_RX_BE) -+ ag->debug.int_stats.rx_be++; -+} -+ -+static ssize_t read_file_int_stats(struct file *file, char __user *user_buf, -+ size_t count, loff_t *ppos) -+{ -+#define PR_INT_STAT(_label, _field) \ -+ len += snprintf(buf + len, sizeof(buf) - len, \ -+ "%20s: %10lu\n", _label, ag->debug.int_stats._field); -+ -+ struct ag71xx *ag = file->private_data; -+ char buf[256]; -+ unsigned int len = 0; -+ -+ PR_INT_STAT("TX Packet Sent", tx_ps); -+ PR_INT_STAT("TX Underrun", tx_ur); -+ PR_INT_STAT("TX Bus Error", tx_be); -+ PR_INT_STAT("RX Packet Received", rx_pr); -+ PR_INT_STAT("RX Overflow", rx_of); -+ PR_INT_STAT("RX Bus Error", rx_be); -+ len += snprintf(buf + len, sizeof(buf) - len, "\n"); -+ PR_INT_STAT("Total", total); -+ -+ return simple_read_from_buffer(user_buf, count, ppos, buf, len); -+#undef PR_INT_STAT -+} -+ -+static const struct file_operations ag71xx_fops_int_stats = { -+ .open = ag71xx_debugfs_generic_open, -+ .read = read_file_int_stats, -+ .owner = THIS_MODULE -+}; -+ -+void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, int rx, int tx) -+{ -+ struct ag71xx_napi_stats *stats = &ag->debug.napi_stats; -+ -+ if (rx) { -+ stats->rx_count++; -+ stats->rx_packets += rx; -+ if (rx <= AG71XX_NAPI_WEIGHT) -+ stats->rx[rx]++; -+ if (rx > stats->rx_packets_max) -+ stats->rx_packets_max = rx; -+ } -+ -+ if (tx) { -+ stats->tx_count++; -+ stats->tx_packets += tx; -+ if (tx <= AG71XX_NAPI_WEIGHT) -+ stats->tx[tx]++; -+ if (tx > stats->tx_packets_max) -+ stats->tx_packets_max = tx; -+ } -+} -+ -+static ssize_t read_file_napi_stats(struct file *file, char __user *user_buf, -+ size_t count, loff_t *ppos) -+{ -+ struct ag71xx *ag = file->private_data; -+ struct ag71xx_napi_stats *stats = &ag->debug.napi_stats; -+ char *buf; -+ unsigned int buflen; -+ unsigned int len = 0; -+ unsigned long rx_avg = 0; -+ unsigned long tx_avg = 0; -+ int ret; -+ int i; -+ -+ buflen = 2048; -+ buf = kmalloc(buflen, GFP_KERNEL); -+ if (!buf) -+ return -ENOMEM; -+ -+ if (stats->rx_count) -+ rx_avg = stats->rx_packets / stats->rx_count; -+ -+ if (stats->tx_count) -+ tx_avg = stats->tx_packets / stats->tx_count; -+ -+ len += snprintf(buf + len, buflen - len, "%3s %10s %10s\n", -+ "len", "rx", "tx"); -+ -+ for (i = 1; i <= AG71XX_NAPI_WEIGHT; i++) -+ len += snprintf(buf + len, buflen - len, -+ "%3d: %10lu %10lu\n", -+ i, stats->rx[i], stats->tx[i]); -+ -+ len += snprintf(buf + len, buflen - len, "\n"); -+ -+ len += snprintf(buf + len, buflen - len, "%3s: %10lu %10lu\n", -+ "sum", stats->rx_count, stats->tx_count); -+ len += snprintf(buf + len, buflen - len, "%3s: %10lu %10lu\n", -+ "avg", rx_avg, tx_avg); -+ len += snprintf(buf + len, buflen - len, "%3s: %10lu %10lu\n", -+ "max", stats->rx_packets_max, stats->tx_packets_max); -+ len += snprintf(buf + len, buflen - len, "%3s: %10lu %10lu\n", -+ "pkt", stats->rx_packets, stats->tx_packets); -+ -+ ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); -+ kfree(buf); -+ -+ return ret; -+} -+ -+static const struct file_operations ag71xx_fops_napi_stats = { -+ .open = ag71xx_debugfs_generic_open, -+ .read = read_file_napi_stats, -+ .owner = THIS_MODULE -+}; -+ -+#define DESC_PRINT_LEN 64 -+ -+static ssize_t read_file_ring(struct file *file, char __user *user_buf, -+ size_t count, loff_t *ppos, -+ struct ag71xx *ag, -+ struct ag71xx_ring *ring, -+ unsigned desc_reg) -+{ -+ char *buf; -+ unsigned int buflen; -+ unsigned int len = 0; -+ unsigned long flags; -+ ssize_t ret; -+ int curr; -+ int dirty; -+ u32 desc_hw; -+ int i; -+ -+ buflen = (ring->size * DESC_PRINT_LEN); -+ buf = kmalloc(buflen, GFP_KERNEL); -+ if (!buf) -+ return -ENOMEM; -+ -+ len += snprintf(buf + len, buflen - len, -+ "Idx ... %-8s %-8s %-8s %-8s . %-10s\n", -+ "desc", "next", "data", "ctrl", "timestamp"); -+ -+ spin_lock_irqsave(&ag->lock, flags); -+ -+ curr = (ring->curr % ring->size); -+ dirty = (ring->dirty % ring->size); -+ desc_hw = ag71xx_rr(ag, desc_reg); -+ for (i = 0; i < ring->size; i++) { -+ struct ag71xx_buf *ab = &ring->buf[i]; -+ u32 desc_dma = ((u32) ring->descs_dma) + i * ring->desc_size; -+ -+ len += snprintf(buf + len, buflen - len, -+ "%3d %c%c%c %08x %08x %08x %08x %c %10lu\n", -+ i, -+ (i == curr) ? 'C' : ' ', -+ (i == dirty) ? 'D' : ' ', -+ (desc_hw == desc_dma) ? 'H' : ' ', -+ desc_dma, -+ ab->desc->next, -+ ab->desc->data, -+ ab->desc->ctrl, -+ (ab->desc->ctrl & DESC_EMPTY) ? 'E' : '*', -+ ab->timestamp); -+ } -+ -+ spin_unlock_irqrestore(&ag->lock, flags); -+ -+ ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); -+ kfree(buf); -+ -+ return ret; -+} -+ -+static ssize_t read_file_tx_ring(struct file *file, char __user *user_buf, -+ size_t count, loff_t *ppos) -+{ -+ struct ag71xx *ag = file->private_data; -+ -+ return read_file_ring(file, user_buf, count, ppos, ag, &ag->tx_ring, -+ AG71XX_REG_TX_DESC); -+} -+ -+static const struct file_operations ag71xx_fops_tx_ring = { -+ .open = ag71xx_debugfs_generic_open, -+ .read = read_file_tx_ring, -+ .owner = THIS_MODULE -+}; -+ -+static ssize_t read_file_rx_ring(struct file *file, char __user *user_buf, -+ size_t count, loff_t *ppos) -+{ -+ struct ag71xx *ag = file->private_data; -+ -+ return read_file_ring(file, user_buf, count, ppos, ag, &ag->rx_ring, -+ AG71XX_REG_RX_DESC); -+} -+ -+static const struct file_operations ag71xx_fops_rx_ring = { -+ .open = ag71xx_debugfs_generic_open, -+ .read = read_file_rx_ring, -+ .owner = THIS_MODULE -+}; -+ -+void ag71xx_debugfs_exit(struct ag71xx *ag) -+{ -+ debugfs_remove_recursive(ag->debug.debugfs_dir); -+} -+ -+int ag71xx_debugfs_init(struct ag71xx *ag) -+{ -+ ag->debug.debugfs_dir = debugfs_create_dir(ag->dev->name, -+ ag71xx_debugfs_root); -+ if (!ag->debug.debugfs_dir) -+ return -ENOMEM; -+ -+ debugfs_create_file("int_stats", S_IRUGO, ag->debug.debugfs_dir, -+ ag, &ag71xx_fops_int_stats); -+ debugfs_create_file("napi_stats", S_IRUGO, ag->debug.debugfs_dir, -+ ag, &ag71xx_fops_napi_stats); -+ debugfs_create_file("tx_ring", S_IRUGO, ag->debug.debugfs_dir, -+ ag, &ag71xx_fops_tx_ring); -+ debugfs_create_file("rx_ring", S_IRUGO, ag->debug.debugfs_dir, -+ ag, &ag71xx_fops_rx_ring); -+ -+ return 0; -+} -+ -+int ag71xx_debugfs_root_init(void) -+{ -+ if (ag71xx_debugfs_root) -+ return -EBUSY; -+ -+ ag71xx_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL); -+ if (!ag71xx_debugfs_root) -+ return -ENOENT; -+ -+ return 0; -+} -+ -+void ag71xx_debugfs_root_exit(void) -+{ -+ debugfs_remove(ag71xx_debugfs_root); -+ ag71xx_debugfs_root = NULL; -+} -diff -Nur linux-2.6.39.orig/drivers/net/ag71xx/ag71xx_ethtool.c linux-2.6.39/drivers/net/ag71xx/ag71xx_ethtool.c ---- linux-2.6.39.orig/drivers/net/ag71xx/ag71xx_ethtool.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/drivers/net/ag71xx/ag71xx_ethtool.c 2011-08-24 18:17:24.000000000 +0200 -@@ -0,0 +1,124 @@ -+/* -+ * Atheros AR71xx built-in ethernet mac driver -+ * -+ * Copyright (C) 2008-2010 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Based on Atheros' AG7100 driver -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include "ag71xx.h" -+ -+static int ag71xx_ethtool_get_settings(struct net_device *dev, -+ struct ethtool_cmd *cmd) -+{ -+ struct ag71xx *ag = netdev_priv(dev); -+ struct phy_device *phydev = ag->phy_dev; -+ -+ if (!phydev) -+ return -ENODEV; -+ -+ return phy_ethtool_gset(phydev, cmd); -+} -+ -+static int ag71xx_ethtool_set_settings(struct net_device *dev, -+ struct ethtool_cmd *cmd) -+{ -+ struct ag71xx *ag = netdev_priv(dev); -+ struct phy_device *phydev = ag->phy_dev; -+ -+ if (!phydev) -+ return -ENODEV; -+ -+ return phy_ethtool_sset(phydev, cmd); -+} -+ -+static void ag71xx_ethtool_get_drvinfo(struct net_device *dev, -+ struct ethtool_drvinfo *info) -+{ -+ struct ag71xx *ag = netdev_priv(dev); -+ -+ strcpy(info->driver, ag->pdev->dev.driver->name); -+ strcpy(info->version, AG71XX_DRV_VERSION); -+ strcpy(info->bus_info, dev_name(&ag->pdev->dev)); -+} -+ -+static u32 ag71xx_ethtool_get_msglevel(struct net_device *dev) -+{ -+ struct ag71xx *ag = netdev_priv(dev); -+ -+ return ag->msg_enable; -+} -+ -+static void ag71xx_ethtool_set_msglevel(struct net_device *dev, u32 msg_level) -+{ -+ struct ag71xx *ag = netdev_priv(dev); -+ -+ ag->msg_enable = msg_level; -+} -+ -+static void ag71xx_ethtool_get_ringparam(struct net_device *dev, -+ struct ethtool_ringparam *er) -+{ -+ struct ag71xx *ag = netdev_priv(dev); -+ -+ er->tx_max_pending = AG71XX_TX_RING_SIZE_MAX; -+ er->rx_max_pending = AG71XX_RX_RING_SIZE_MAX; -+ er->rx_mini_max_pending = 0; -+ er->rx_jumbo_max_pending = 0; -+ -+ er->tx_pending = ag->tx_ring.size; -+ er->rx_pending = ag->rx_ring.size; -+ er->rx_mini_pending = 0; -+ er->rx_jumbo_pending = 0; -+} -+ -+static int ag71xx_ethtool_set_ringparam(struct net_device *dev, -+ struct ethtool_ringparam *er) -+{ -+ struct ag71xx *ag = netdev_priv(dev); -+ unsigned tx_size; -+ unsigned rx_size; -+ int err; -+ -+ if (er->rx_mini_pending != 0|| -+ er->rx_jumbo_pending != 0 || -+ er->rx_pending == 0 || -+ er->tx_pending == 0) -+ return -EINVAL; -+ -+ tx_size = er->tx_pending < AG71XX_TX_RING_SIZE_MAX ? -+ er->tx_pending : AG71XX_TX_RING_SIZE_MAX; -+ -+ rx_size = er->rx_pending < AG71XX_RX_RING_SIZE_MAX ? -+ er->rx_pending : AG71XX_RX_RING_SIZE_MAX; -+ -+ if (netif_running(dev)) { -+ err = dev->netdev_ops->ndo_stop(dev); -+ if (err) -+ return err; -+ } -+ -+ ag->tx_ring.size = tx_size; -+ ag->rx_ring.size = rx_size; -+ -+ if (netif_running(dev)) -+ err = dev->netdev_ops->ndo_open(dev); -+ -+ return err; -+} -+ -+struct ethtool_ops ag71xx_ethtool_ops = { -+ .set_settings = ag71xx_ethtool_set_settings, -+ .get_settings = ag71xx_ethtool_get_settings, -+ .get_drvinfo = ag71xx_ethtool_get_drvinfo, -+ .get_msglevel = ag71xx_ethtool_get_msglevel, -+ .set_msglevel = ag71xx_ethtool_set_msglevel, -+ .get_ringparam = ag71xx_ethtool_get_ringparam, -+ .set_ringparam = ag71xx_ethtool_set_ringparam, -+ .get_link = ethtool_op_get_link, -+}; -diff -Nur linux-2.6.39.orig/drivers/net/ag71xx/ag71xx_main.c linux-2.6.39/drivers/net/ag71xx/ag71xx_main.c ---- linux-2.6.39.orig/drivers/net/ag71xx/ag71xx_main.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/drivers/net/ag71xx/ag71xx_main.c 2011-08-24 18:17:24.000000000 +0200 -@@ -0,0 +1,1291 @@ -+/* -+ * Atheros AR71xx built-in ethernet mac driver -+ * -+ * Copyright (C) 2008-2010 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Based on Atheros' AG7100 driver -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include "ag71xx.h" -+ -+#define AG71XX_DEFAULT_MSG_ENABLE \ -+ (NETIF_MSG_DRV \ -+ | NETIF_MSG_PROBE \ -+ | NETIF_MSG_LINK \ -+ | NETIF_MSG_TIMER \ -+ | NETIF_MSG_IFDOWN \ -+ | NETIF_MSG_IFUP \ -+ | NETIF_MSG_RX_ERR \ -+ | NETIF_MSG_TX_ERR) -+ -+static int ag71xx_msg_level = -1; -+ -+module_param_named(msg_level, ag71xx_msg_level, int, 0); -+MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); -+ -+static void ag71xx_dump_dma_regs(struct ag71xx *ag) -+{ -+ DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n", -+ ag->dev->name, -+ ag71xx_rr(ag, AG71XX_REG_TX_CTRL), -+ ag71xx_rr(ag, AG71XX_REG_TX_DESC), -+ ag71xx_rr(ag, AG71XX_REG_TX_STATUS)); -+ -+ DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n", -+ ag->dev->name, -+ ag71xx_rr(ag, AG71XX_REG_RX_CTRL), -+ ag71xx_rr(ag, AG71XX_REG_RX_DESC), -+ ag71xx_rr(ag, AG71XX_REG_RX_STATUS)); -+} -+ -+static void ag71xx_dump_regs(struct ag71xx *ag) -+{ -+ DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n", -+ ag->dev->name, -+ ag71xx_rr(ag, AG71XX_REG_MAC_CFG1), -+ ag71xx_rr(ag, AG71XX_REG_MAC_CFG2), -+ ag71xx_rr(ag, AG71XX_REG_MAC_IPG), -+ ag71xx_rr(ag, AG71XX_REG_MAC_HDX), -+ ag71xx_rr(ag, AG71XX_REG_MAC_MFL)); -+ DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n", -+ ag->dev->name, -+ ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL), -+ ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1), -+ ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2)); -+ DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n", -+ ag->dev->name, -+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0), -+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1), -+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2)); -+ DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n", -+ ag->dev->name, -+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3), -+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4), -+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5)); -+} -+ -+static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr) -+{ -+ DBG("%s: %s intr=%08x %s%s%s%s%s%s\n", -+ ag->dev->name, label, intr, -+ (intr & AG71XX_INT_TX_PS) ? "TXPS " : "", -+ (intr & AG71XX_INT_TX_UR) ? "TXUR " : "", -+ (intr & AG71XX_INT_TX_BE) ? "TXBE " : "", -+ (intr & AG71XX_INT_RX_PR) ? "RXPR " : "", -+ (intr & AG71XX_INT_RX_OF) ? "RXOF " : "", -+ (intr & AG71XX_INT_RX_BE) ? "RXBE " : ""); -+} -+ -+static void ag71xx_ring_free(struct ag71xx_ring *ring) -+{ -+ kfree(ring->buf); -+ -+ if (ring->descs_cpu) -+ dma_free_coherent(NULL, ring->size * ring->desc_size, -+ ring->descs_cpu, ring->descs_dma); -+} -+ -+static int ag71xx_ring_alloc(struct ag71xx_ring *ring) -+{ -+ int err; -+ int i; -+ -+ ring->desc_size = sizeof(struct ag71xx_desc); -+ if (ring->desc_size % cache_line_size()) { -+ DBG("ag71xx: ring %p, desc size %u rounded to %u\n", -+ ring, ring->desc_size, -+ roundup(ring->desc_size, cache_line_size())); -+ ring->desc_size = roundup(ring->desc_size, cache_line_size()); -+ } -+ -+ ring->descs_cpu = dma_alloc_coherent(NULL, ring->size * ring->desc_size, -+ &ring->descs_dma, GFP_ATOMIC); -+ if (!ring->descs_cpu) { -+ err = -ENOMEM; -+ goto err; -+ } -+ -+ -+ ring->buf = kzalloc(ring->size * sizeof(*ring->buf), GFP_KERNEL); -+ if (!ring->buf) { -+ err = -ENOMEM; -+ goto err; -+ } -+ -+ for (i = 0; i < ring->size; i++) { -+ int idx = i * ring->desc_size; -+ ring->buf[i].desc = (struct ag71xx_desc *)&ring->descs_cpu[idx]; -+ DBG("ag71xx: ring %p, desc %d at %p\n", -+ ring, i, ring->buf[i].desc); -+ } -+ -+ return 0; -+ -+err: -+ return err; -+} -+ -+static void ag71xx_ring_tx_clean(struct ag71xx *ag) -+{ -+ struct ag71xx_ring *ring = &ag->tx_ring; -+ struct net_device *dev = ag->dev; -+ -+ while (ring->curr != ring->dirty) { -+ u32 i = ring->dirty % ring->size; -+ -+ if (!ag71xx_desc_empty(ring->buf[i].desc)) { -+ ring->buf[i].desc->ctrl = 0; -+ dev->stats.tx_errors++; -+ } -+ -+ if (ring->buf[i].skb) -+ dev_kfree_skb_any(ring->buf[i].skb); -+ -+ ring->buf[i].skb = NULL; -+ -+ ring->dirty++; -+ } -+ -+ /* flush descriptors */ -+ wmb(); -+ -+} -+ -+static void ag71xx_ring_tx_init(struct ag71xx *ag) -+{ -+ struct ag71xx_ring *ring = &ag->tx_ring; -+ int i; -+ -+ for (i = 0; i < ring->size; i++) { -+ ring->buf[i].desc->next = (u32) (ring->descs_dma + -+ ring->desc_size * ((i + 1) % ring->size)); -+ -+ ring->buf[i].desc->ctrl = DESC_EMPTY; -+ ring->buf[i].skb = NULL; -+ } -+ -+ /* flush descriptors */ -+ wmb(); -+ -+ ring->curr = 0; -+ ring->dirty = 0; -+} -+ -+static void ag71xx_ring_rx_clean(struct ag71xx *ag) -+{ -+ struct ag71xx_ring *ring = &ag->rx_ring; -+ int i; -+ -+ if (!ring->buf) -+ return; -+ -+ for (i = 0; i < ring->size; i++) -+ if (ring->buf[i].skb) { -+ dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr, -+ AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE); -+ kfree_skb(ring->buf[i].skb); -+ } -+} -+ -+static int ag71xx_rx_reserve(struct ag71xx *ag) -+{ -+ int reserve = 0; -+ -+ if (ag71xx_get_pdata(ag)->is_ar724x) { -+ if (!ag71xx_has_ar8216(ag)) -+ reserve = 2; -+ -+ if (ag->phy_dev) -+ reserve += 4 - (ag->phy_dev->pkt_align % 4); -+ -+ reserve %= 4; -+ } -+ -+ return reserve + AG71XX_RX_PKT_RESERVE; -+} -+ -+ -+static int ag71xx_ring_rx_init(struct ag71xx *ag) -+{ -+ struct ag71xx_ring *ring = &ag->rx_ring; -+ unsigned int reserve = ag71xx_rx_reserve(ag); -+ unsigned int i; -+ int ret; -+ -+ ret = 0; -+ for (i = 0; i < ring->size; i++) { -+ ring->buf[i].desc->next = (u32) (ring->descs_dma + -+ ring->desc_size * ((i + 1) % ring->size)); -+ -+ DBG("ag71xx: RX desc at %p, next is %08x\n", -+ ring->buf[i].desc, -+ ring->buf[i].desc->next); -+ } -+ -+ for (i = 0; i < ring->size; i++) { -+ struct sk_buff *skb; -+ dma_addr_t dma_addr; -+ -+ skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + reserve); -+ if (!skb) { -+ ret = -ENOMEM; -+ break; -+ } -+ -+ skb->dev = ag->dev; -+ skb_reserve(skb, reserve); -+ -+ dma_addr = dma_map_single(&ag->dev->dev, skb->data, -+ AG71XX_RX_PKT_SIZE, -+ DMA_FROM_DEVICE); -+ ring->buf[i].skb = skb; -+ ring->buf[i].dma_addr = dma_addr; -+ ring->buf[i].desc->data = (u32) dma_addr; -+ ring->buf[i].desc->ctrl = DESC_EMPTY; -+ } -+ -+ /* flush descriptors */ -+ wmb(); -+ -+ ring->curr = 0; -+ ring->dirty = 0; -+ -+ return ret; -+} -+ -+static int ag71xx_ring_rx_refill(struct ag71xx *ag) -+{ -+ struct ag71xx_ring *ring = &ag->rx_ring; -+ unsigned int reserve = ag71xx_rx_reserve(ag); -+ unsigned int count; -+ -+ count = 0; -+ for (; ring->curr - ring->dirty > 0; ring->dirty++) { -+ unsigned int i; -+ -+ i = ring->dirty % ring->size; -+ -+ if (ring->buf[i].skb == NULL) { -+ dma_addr_t dma_addr; -+ struct sk_buff *skb; -+ -+ skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + reserve); -+ if (skb == NULL) -+ break; -+ -+ skb_reserve(skb, reserve); -+ skb->dev = ag->dev; -+ -+ dma_addr = dma_map_single(&ag->dev->dev, skb->data, -+ AG71XX_RX_PKT_SIZE, -+ DMA_FROM_DEVICE); -+ -+ ring->buf[i].skb = skb; -+ ring->buf[i].dma_addr = dma_addr; -+ ring->buf[i].desc->data = (u32) dma_addr; -+ } -+ -+ ring->buf[i].desc->ctrl = DESC_EMPTY; -+ count++; -+ } -+ -+ /* flush descriptors */ -+ wmb(); -+ -+ DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count); -+ -+ return count; -+} -+ -+static int ag71xx_rings_init(struct ag71xx *ag) -+{ -+ int ret; -+ -+ ret = ag71xx_ring_alloc(&ag->tx_ring); -+ if (ret) -+ return ret; -+ -+ ag71xx_ring_tx_init(ag); -+ -+ ret = ag71xx_ring_alloc(&ag->rx_ring); -+ if (ret) -+ return ret; -+ -+ ret = ag71xx_ring_rx_init(ag); -+ return ret; -+} -+ -+static void ag71xx_rings_cleanup(struct ag71xx *ag) -+{ -+ ag71xx_ring_rx_clean(ag); -+ ag71xx_ring_free(&ag->rx_ring); -+ -+ ag71xx_ring_tx_clean(ag); -+ ag71xx_ring_free(&ag->tx_ring); -+} -+ -+static unsigned char *ag71xx_speed_str(struct ag71xx *ag) -+{ -+ switch (ag->speed) { -+ case SPEED_1000: -+ return "1000"; -+ case SPEED_100: -+ return "100"; -+ case SPEED_10: -+ return "10"; -+ } -+ -+ return "?"; -+} -+ -+static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac) -+{ -+ u32 t; -+ -+ t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16) -+ | (((u32) mac[3]) << 8) | ((u32) mac[2]); -+ -+ ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t); -+ -+ t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16); -+ ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t); -+} -+ -+static void ag71xx_dma_reset(struct ag71xx *ag) -+{ -+ u32 val; -+ int i; -+ -+ ag71xx_dump_dma_regs(ag); -+ -+ /* stop RX and TX */ -+ ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0); -+ ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0); -+ -+ /* -+ * give the hardware some time to really stop all rx/tx activity -+ * clearing the descriptors too early causes random memory corruption -+ */ -+ mdelay(1); -+ -+ /* clear descriptor addresses */ -+ ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma); -+ ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma); -+ -+ /* clear pending RX/TX interrupts */ -+ for (i = 0; i < 256; i++) { -+ ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR); -+ ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS); -+ } -+ -+ /* clear pending errors */ -+ ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF); -+ ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR); -+ -+ val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS); -+ if (val) -+ printk(KERN_ALERT "%s: unable to clear DMA Rx status: %08x\n", -+ ag->dev->name, val); -+ -+ val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS); -+ -+ /* mask out reserved bits */ -+ val &= ~0xff000000; -+ -+ if (val) -+ printk(KERN_ALERT "%s: unable to clear DMA Tx status: %08x\n", -+ ag->dev->name, val); -+ -+ ag71xx_dump_dma_regs(ag); -+} -+ -+#define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \ -+ MAC_CFG1_SRX | MAC_CFG1_STX) -+ -+#define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT) -+ -+#define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \ -+ FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \ -+ FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \ -+ FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \ -+ FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \ -+ FIFO_CFG4_VT) -+ -+#define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \ -+ FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \ -+ FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \ -+ FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \ -+ FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \ -+ FIFO_CFG5_17 | FIFO_CFG5_SF) -+ -+static void ag71xx_hw_stop(struct ag71xx *ag) -+{ -+ /* disable all interrupts and stop the rx/tx engine */ -+ ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0); -+ ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0); -+ ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0); -+} -+ -+static void ag71xx_hw_setup(struct ag71xx *ag) -+{ -+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); -+ -+ /* setup MAC configuration registers */ -+ ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT); -+ -+ ag71xx_sb(ag, AG71XX_REG_MAC_CFG2, -+ MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK); -+ -+ /* setup max frame length */ -+ ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN); -+ -+ /* setup MII interface type */ -+ ag71xx_mii_ctrl_set_if(ag, pdata->mii_if); -+ -+ /* setup FIFO configuration registers */ -+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT); -+ if (pdata->is_ar724x) { -+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1); -+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2); -+ } else { -+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000); -+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff); -+ } -+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT); -+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT); -+} -+ -+static void ag71xx_hw_init(struct ag71xx *ag) -+{ -+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); -+ u32 reset_mask = pdata->reset_bit; -+ -+ ag71xx_hw_stop(ag); -+ -+ if (pdata->is_ar724x) { -+ u32 reset_phy = reset_mask; -+ -+ reset_phy &= RESET_MODULE_GE0_PHY | RESET_MODULE_GE1_PHY; -+ reset_mask &= ~(RESET_MODULE_GE0_PHY | RESET_MODULE_GE1_PHY); -+ -+ ar71xx_device_stop(reset_phy); -+ mdelay(50); -+ ar71xx_device_start(reset_phy); -+ mdelay(200); -+ } -+ -+ ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR); -+ udelay(20); -+ -+ ar71xx_device_stop(reset_mask); -+ mdelay(100); -+ ar71xx_device_start(reset_mask); -+ mdelay(200); -+ -+ ag71xx_hw_setup(ag); -+ -+ ag71xx_dma_reset(ag); -+} -+ -+static void ag71xx_fast_reset(struct ag71xx *ag) -+{ -+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); -+ struct net_device *dev = ag->dev; -+ u32 reset_mask = pdata->reset_bit; -+ u32 rx_ds, tx_ds; -+ u32 mii_reg; -+ -+ reset_mask &= RESET_MODULE_GE0_MAC | RESET_MODULE_GE1_MAC; -+ -+ mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG); -+ rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC); -+ tx_ds = ag71xx_rr(ag, AG71XX_REG_TX_DESC); -+ -+ ar71xx_device_stop(reset_mask); -+ udelay(10); -+ ar71xx_device_start(reset_mask); -+ udelay(10); -+ -+ ag71xx_dma_reset(ag); -+ ag71xx_hw_setup(ag); -+ -+ ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds); -+ ag71xx_wr(ag, AG71XX_REG_TX_DESC, tx_ds); -+ ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg); -+ -+ ag71xx_hw_set_macaddr(ag, dev->dev_addr); -+} -+ -+static void ag71xx_hw_start(struct ag71xx *ag) -+{ -+ /* start RX engine */ -+ ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE); -+ -+ /* enable interrupts */ -+ ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT); -+} -+ -+void ag71xx_link_adjust(struct ag71xx *ag) -+{ -+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); -+ u32 cfg2; -+ u32 ifctl; -+ u32 fifo5; -+ u32 mii_speed; -+ -+ if (!ag->link) { -+ ag71xx_hw_stop(ag); -+ netif_carrier_off(ag->dev); -+ if (netif_msg_link(ag)) -+ printk(KERN_INFO "%s: link down\n", ag->dev->name); -+ return; -+ } -+ -+ if (pdata->is_ar724x) -+ ag71xx_fast_reset(ag); -+ -+ cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2); -+ cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX); -+ cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0; -+ -+ ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL); -+ ifctl &= ~(MAC_IFCTL_SPEED); -+ -+ fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5); -+ fifo5 &= ~FIFO_CFG5_BM; -+ -+ switch (ag->speed) { -+ case SPEED_1000: -+ mii_speed = MII_CTRL_SPEED_1000; -+ cfg2 |= MAC_CFG2_IF_1000; -+ fifo5 |= FIFO_CFG5_BM; -+ break; -+ case SPEED_100: -+ mii_speed = MII_CTRL_SPEED_100; -+ cfg2 |= MAC_CFG2_IF_10_100; -+ ifctl |= MAC_IFCTL_SPEED; -+ break; -+ case SPEED_10: -+ mii_speed = MII_CTRL_SPEED_10; -+ cfg2 |= MAC_CFG2_IF_10_100; -+ break; -+ default: -+ BUG(); -+ return; -+ } -+ -+ if (pdata->is_ar91xx) -+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x00780fff); -+ else if (pdata->is_ar724x) -+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, pdata->fifo_cfg3); -+ else -+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x008001ff); -+ -+ if (pdata->set_pll) -+ pdata->set_pll(ag->speed); -+ -+ ag71xx_mii_ctrl_set_speed(ag, mii_speed); -+ -+ ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2); -+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5); -+ ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl); -+ ag71xx_hw_start(ag); -+ -+ netif_carrier_on(ag->dev); -+ if (netif_msg_link(ag)) -+ printk(KERN_INFO "%s: link up (%sMbps/%s duplex)\n", -+ ag->dev->name, -+ ag71xx_speed_str(ag), -+ (DUPLEX_FULL == ag->duplex) ? "Full" : "Half"); -+ -+ DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n", -+ ag->dev->name, -+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0), -+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1), -+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2)); -+ -+ DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n", -+ ag->dev->name, -+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3), -+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4), -+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5)); -+ -+ DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x, mii_ctrl=%#x\n", -+ ag->dev->name, -+ ag71xx_rr(ag, AG71XX_REG_MAC_CFG2), -+ ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL), -+ ag71xx_mii_ctrl_rr(ag)); -+} -+ -+static int ag71xx_open(struct net_device *dev) -+{ -+ struct ag71xx *ag = netdev_priv(dev); -+ int ret; -+ -+ ret = ag71xx_rings_init(ag); -+ if (ret) -+ goto err; -+ -+ napi_enable(&ag->napi); -+ -+ netif_carrier_off(dev); -+ ag71xx_phy_start(ag); -+ -+ ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma); -+ ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma); -+ -+ ag71xx_hw_set_macaddr(ag, dev->dev_addr); -+ -+ netif_start_queue(dev); -+ -+ return 0; -+ -+err: -+ ag71xx_rings_cleanup(ag); -+ return ret; -+} -+ -+static int ag71xx_stop(struct net_device *dev) -+{ -+ struct ag71xx *ag = netdev_priv(dev); -+ unsigned long flags; -+ -+ netif_carrier_off(dev); -+ ag71xx_phy_stop(ag); -+ -+ spin_lock_irqsave(&ag->lock, flags); -+ -+ netif_stop_queue(dev); -+ -+ ag71xx_hw_stop(ag); -+ ag71xx_dma_reset(ag); -+ -+ napi_disable(&ag->napi); -+ del_timer_sync(&ag->oom_timer); -+ -+ spin_unlock_irqrestore(&ag->lock, flags); -+ -+ ag71xx_rings_cleanup(ag); -+ -+ return 0; -+} -+ -+static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb, -+ struct net_device *dev) -+{ -+ struct ag71xx *ag = netdev_priv(dev); -+ struct ag71xx_ring *ring = &ag->tx_ring; -+ struct ag71xx_desc *desc; -+ dma_addr_t dma_addr; -+ int i; -+ -+ i = ring->curr % ring->size; -+ desc = ring->buf[i].desc; -+ -+ if (!ag71xx_desc_empty(desc)) -+ goto err_drop; -+ -+ if (ag71xx_has_ar8216(ag)) -+ ag71xx_add_ar8216_header(ag, skb); -+ -+ if (skb->len <= 0) { -+ DBG("%s: packet len is too small\n", ag->dev->name); -+ goto err_drop; -+ } -+ -+ dma_addr = dma_map_single(&dev->dev, skb->data, skb->len, -+ DMA_TO_DEVICE); -+ -+ ring->buf[i].skb = skb; -+ ring->buf[i].timestamp = jiffies; -+ -+ /* setup descriptor fields */ -+ desc->data = (u32) dma_addr; -+ desc->ctrl = (skb->len & DESC_PKTLEN_M); -+ -+ /* flush descriptor */ -+ wmb(); -+ -+ ring->curr++; -+ if (ring->curr == (ring->dirty + ring->size)) { -+ DBG("%s: tx queue full\n", ag->dev->name); -+ netif_stop_queue(dev); -+ } -+ -+ DBG("%s: packet injected into TX queue\n", ag->dev->name); -+ -+ /* enable TX engine */ -+ ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE); -+ -+ return NETDEV_TX_OK; -+ -+err_drop: -+ dev->stats.tx_dropped++; -+ -+ dev_kfree_skb(skb); -+ return NETDEV_TX_OK; -+} -+ -+static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) -+{ -+ struct ag71xx *ag = netdev_priv(dev); -+ int ret; -+ -+ switch (cmd) { -+ case SIOCETHTOOL: -+ if (ag->phy_dev == NULL) -+ break; -+ -+ spin_lock_irq(&ag->lock); -+ ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data); -+ spin_unlock_irq(&ag->lock); -+ return ret; -+ -+ case SIOCSIFHWADDR: -+ if (copy_from_user -+ (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr))) -+ return -EFAULT; -+ return 0; -+ -+ case SIOCGIFHWADDR: -+ if (copy_to_user -+ (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr))) -+ return -EFAULT; -+ return 0; -+ -+ case SIOCGMIIPHY: -+ case SIOCGMIIREG: -+ case SIOCSMIIREG: -+ if (ag->phy_dev == NULL) -+ break; -+ -+ return phy_mii_ioctl(ag->phy_dev, ifr, cmd); -+ -+ default: -+ break; -+ } -+ -+ return -EOPNOTSUPP; -+} -+ -+static void ag71xx_oom_timer_handler(unsigned long data) -+{ -+ struct net_device *dev = (struct net_device *) data; -+ struct ag71xx *ag = netdev_priv(dev); -+ -+ napi_schedule(&ag->napi); -+} -+ -+static void ag71xx_tx_timeout(struct net_device *dev) -+{ -+ struct ag71xx *ag = netdev_priv(dev); -+ -+ if (netif_msg_tx_err(ag)) -+ printk(KERN_DEBUG "%s: tx timeout\n", ag->dev->name); -+ -+ schedule_work(&ag->restart_work); -+} -+ -+static void ag71xx_restart_work_func(struct work_struct *work) -+{ -+ struct ag71xx *ag = container_of(work, struct ag71xx, restart_work); -+ -+ if (ag71xx_get_pdata(ag)->is_ar724x) { -+ ag->link = 0; -+ ag71xx_link_adjust(ag); -+ return; -+ } -+ -+ ag71xx_stop(ag->dev); -+ ag71xx_open(ag->dev); -+} -+ -+static bool ag71xx_check_dma_stuck(struct ag71xx *ag, unsigned long timestamp) -+{ -+ u32 rx_sm, tx_sm, rx_fd; -+ -+ if (likely(time_before(jiffies, timestamp + HZ/10))) -+ return false; -+ -+ if (!netif_carrier_ok(ag->dev)) -+ return false; -+ -+ rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM); -+ if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6) -+ return true; -+ -+ tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM); -+ rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH); -+ if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) && -+ ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0) -+ return true; -+ -+ return false; -+} -+ -+static int ag71xx_tx_packets(struct ag71xx *ag) -+{ -+ struct ag71xx_ring *ring = &ag->tx_ring; -+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); -+ int sent; -+ -+ DBG("%s: processing TX ring\n", ag->dev->name); -+ -+ sent = 0; -+ while (ring->dirty != ring->curr) { -+ unsigned int i = ring->dirty % ring->size; -+ struct ag71xx_desc *desc = ring->buf[i].desc; -+ struct sk_buff *skb = ring->buf[i].skb; -+ -+ if (!ag71xx_desc_empty(desc)) { -+ if (pdata->is_ar7240 && -+ ag71xx_check_dma_stuck(ag, ring->buf[i].timestamp)) -+ schedule_work(&ag->restart_work); -+ break; -+ } -+ -+ ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS); -+ -+ ag->dev->stats.tx_bytes += skb->len; -+ ag->dev->stats.tx_packets++; -+ -+ dev_kfree_skb_any(skb); -+ ring->buf[i].skb = NULL; -+ -+ ring->dirty++; -+ sent++; -+ } -+ -+ DBG("%s: %d packets sent out\n", ag->dev->name, sent); -+ -+ if ((ring->curr - ring->dirty) < (ring->size * 3) / 4) -+ netif_wake_queue(ag->dev); -+ -+ return sent; -+} -+ -+static int ag71xx_rx_packets(struct ag71xx *ag, int limit) -+{ -+ struct net_device *dev = ag->dev; -+ struct ag71xx_ring *ring = &ag->rx_ring; -+ int done = 0; -+ -+ DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n", -+ dev->name, limit, ring->curr, ring->dirty); -+ -+ while (done < limit) { -+ unsigned int i = ring->curr % ring->size; -+ struct ag71xx_desc *desc = ring->buf[i].desc; -+ struct sk_buff *skb; -+ int pktlen; -+ int err = 0; -+ -+ if (ag71xx_desc_empty(desc)) -+ break; -+ -+ if ((ring->dirty + ring->size) == ring->curr) { -+ ag71xx_assert(0); -+ break; -+ } -+ -+ ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR); -+ -+ skb = ring->buf[i].skb; -+ pktlen = ag71xx_desc_pktlen(desc); -+ pktlen -= ETH_FCS_LEN; -+ -+ dma_unmap_single(&dev->dev, ring->buf[i].dma_addr, -+ AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE); -+ -+ dev->last_rx = jiffies; -+ dev->stats.rx_packets++; -+ dev->stats.rx_bytes += pktlen; -+ -+ skb_put(skb, pktlen); -+ if (ag71xx_has_ar8216(ag)) -+ err = ag71xx_remove_ar8216_header(ag, skb, pktlen); -+ -+ if (err) { -+ dev->stats.rx_dropped++; -+ kfree_skb(skb); -+ } else { -+ skb->dev = dev; -+ skb->ip_summed = CHECKSUM_NONE; -+ if (ag->phy_dev) { -+ ag->phy_dev->netif_receive_skb(skb); -+ } else { -+ skb->protocol = eth_type_trans(skb, dev); -+ netif_receive_skb(skb); -+ } -+ } -+ -+ ring->buf[i].skb = NULL; -+ done++; -+ -+ ring->curr++; -+ } -+ -+ ag71xx_ring_rx_refill(ag); -+ -+ DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n", -+ dev->name, ring->curr, ring->dirty, done); -+ -+ return done; -+} -+ -+static int ag71xx_poll(struct napi_struct *napi, int limit) -+{ -+ struct ag71xx *ag = container_of(napi, struct ag71xx, napi); -+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); -+ struct net_device *dev = ag->dev; -+ struct ag71xx_ring *rx_ring; -+ unsigned long flags; -+ u32 status; -+ int tx_done; -+ int rx_done; -+ -+ pdata->ddr_flush(); -+ tx_done = ag71xx_tx_packets(ag); -+ -+ DBG("%s: processing RX ring\n", dev->name); -+ rx_done = ag71xx_rx_packets(ag, limit); -+ -+ ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done); -+ -+ rx_ring = &ag->rx_ring; -+ if (rx_ring->buf[rx_ring->dirty % rx_ring->size].skb == NULL) -+ goto oom; -+ -+ status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS); -+ if (unlikely(status & RX_STATUS_OF)) { -+ ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF); -+ dev->stats.rx_fifo_errors++; -+ -+ /* restart RX */ -+ ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE); -+ } -+ -+ if (rx_done < limit) { -+ if (status & RX_STATUS_PR) -+ goto more; -+ -+ status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS); -+ if (status & TX_STATUS_PS) -+ goto more; -+ -+ DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n", -+ dev->name, rx_done, tx_done, limit); -+ -+ napi_complete(napi); -+ -+ /* enable interrupts */ -+ spin_lock_irqsave(&ag->lock, flags); -+ ag71xx_int_enable(ag, AG71XX_INT_POLL); -+ spin_unlock_irqrestore(&ag->lock, flags); -+ return rx_done; -+ } -+ -+more: -+ DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n", -+ dev->name, rx_done, tx_done, limit); -+ return rx_done; -+ -+oom: -+ if (netif_msg_rx_err(ag)) -+ printk(KERN_DEBUG "%s: out of memory\n", dev->name); -+ -+ mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL); -+ napi_complete(napi); -+ return 0; -+} -+ -+static irqreturn_t ag71xx_interrupt(int irq, void *dev_id) -+{ -+ struct net_device *dev = dev_id; -+ struct ag71xx *ag = netdev_priv(dev); -+ u32 status; -+ -+ status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS); -+ ag71xx_dump_intr(ag, "raw", status); -+ -+ if (unlikely(!status)) -+ return IRQ_NONE; -+ -+ if (unlikely(status & AG71XX_INT_ERR)) { -+ if (status & AG71XX_INT_TX_BE) { -+ ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE); -+ dev_err(&dev->dev, "TX BUS error\n"); -+ } -+ if (status & AG71XX_INT_RX_BE) { -+ ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE); -+ dev_err(&dev->dev, "RX BUS error\n"); -+ } -+ } -+ -+ if (likely(status & AG71XX_INT_POLL)) { -+ ag71xx_int_disable(ag, AG71XX_INT_POLL); -+ DBG("%s: enable polling mode\n", dev->name); -+ napi_schedule(&ag->napi); -+ } -+ -+ ag71xx_debugfs_update_int_stats(ag, status); -+ -+ return IRQ_HANDLED; -+} -+ -+static void ag71xx_set_multicast_list(struct net_device *dev) -+{ -+ /* TODO */ -+} -+ -+#ifdef CONFIG_NET_POLL_CONTROLLER -+/* -+ * Polling 'interrupt' - used by things like netconsole to send skbs -+ * without having to re-enable interrupts. It's not called while -+ * the interrupt routine is executing. -+ */ -+static void ag71xx_netpoll(struct net_device *dev) -+{ -+ disable_irq(dev->irq); -+ ag71xx_interrupt(dev->irq, dev); -+ enable_irq(dev->irq); -+} -+#endif -+ -+static const struct net_device_ops ag71xx_netdev_ops = { -+ .ndo_open = ag71xx_open, -+ .ndo_stop = ag71xx_stop, -+ .ndo_start_xmit = ag71xx_hard_start_xmit, -+ .ndo_set_multicast_list = ag71xx_set_multicast_list, -+ .ndo_do_ioctl = ag71xx_do_ioctl, -+ .ndo_tx_timeout = ag71xx_tx_timeout, -+ .ndo_change_mtu = eth_change_mtu, -+ .ndo_set_mac_address = eth_mac_addr, -+ .ndo_validate_addr = eth_validate_addr, -+#ifdef CONFIG_NET_POLL_CONTROLLER -+ .ndo_poll_controller = ag71xx_netpoll, -+#endif -+}; -+ -+static int __devinit ag71xx_probe(struct platform_device *pdev) -+{ -+ struct net_device *dev; -+ struct resource *res; -+ struct ag71xx *ag; -+ struct ag71xx_platform_data *pdata; -+ int err; -+ -+ pdata = pdev->dev.platform_data; -+ if (!pdata) { -+ dev_err(&pdev->dev, "no platform data specified\n"); -+ err = -ENXIO; -+ goto err_out; -+ } -+ -+ if (pdata->mii_bus_dev == NULL) { -+ dev_err(&pdev->dev, "no MII bus device specified\n"); -+ err = -EINVAL; -+ goto err_out; -+ } -+ -+ dev = alloc_etherdev(sizeof(*ag)); -+ if (!dev) { -+ dev_err(&pdev->dev, "alloc_etherdev failed\n"); -+ err = -ENOMEM; -+ goto err_out; -+ } -+ -+ SET_NETDEV_DEV(dev, &pdev->dev); -+ -+ ag = netdev_priv(dev); -+ ag->pdev = pdev; -+ ag->dev = dev; -+ ag->msg_enable = netif_msg_init(ag71xx_msg_level, -+ AG71XX_DEFAULT_MSG_ENABLE); -+ spin_lock_init(&ag->lock); -+ -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base"); -+ if (!res) { -+ dev_err(&pdev->dev, "no mac_base resource found\n"); -+ err = -ENXIO; -+ goto err_out; -+ } -+ -+ ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1); -+ if (!ag->mac_base) { -+ dev_err(&pdev->dev, "unable to ioremap mac_base\n"); -+ err = -ENOMEM; -+ goto err_free_dev; -+ } -+ -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mii_ctrl"); -+ if (!res) { -+ dev_err(&pdev->dev, "no mii_ctrl resource found\n"); -+ err = -ENXIO; -+ goto err_unmap_base; -+ } -+ -+ ag->mii_ctrl = ioremap_nocache(res->start, res->end - res->start + 1); -+ if (!ag->mii_ctrl) { -+ dev_err(&pdev->dev, "unable to ioremap mii_ctrl\n"); -+ err = -ENOMEM; -+ goto err_unmap_base; -+ } -+ -+ dev->irq = platform_get_irq(pdev, 0); -+ err = request_irq(dev->irq, ag71xx_interrupt, -+ IRQF_DISABLED, -+ dev->name, dev); -+ if (err) { -+ dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq); -+ goto err_unmap_mii_ctrl; -+ } -+ -+ dev->base_addr = (unsigned long)ag->mac_base; -+ dev->netdev_ops = &ag71xx_netdev_ops; -+ dev->ethtool_ops = &ag71xx_ethtool_ops; -+ -+ INIT_WORK(&ag->restart_work, ag71xx_restart_work_func); -+ -+ init_timer(&ag->oom_timer); -+ ag->oom_timer.data = (unsigned long) dev; -+ ag->oom_timer.function = ag71xx_oom_timer_handler; -+ -+ ag->tx_ring.size = AG71XX_TX_RING_SIZE_DEFAULT; -+ ag->rx_ring.size = AG71XX_RX_RING_SIZE_DEFAULT; -+ -+ ag->stop_desc = dma_alloc_coherent(NULL, -+ sizeof(struct ag71xx_desc), &ag->stop_desc_dma, GFP_KERNEL); -+ -+ if (!ag->stop_desc) -+ goto err_free_irq; -+ -+ ag->stop_desc->data = 0; -+ ag->stop_desc->ctrl = 0; -+ ag->stop_desc->next = (u32) ag->stop_desc_dma; -+ -+ memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN); -+ -+ netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT); -+ -+ err = register_netdev(dev); -+ if (err) { -+ dev_err(&pdev->dev, "unable to register net device\n"); -+ goto err_free_desc; -+ } -+ -+ printk(KERN_INFO "%s: Atheros AG71xx at 0x%08lx, irq %d\n", -+ dev->name, dev->base_addr, dev->irq); -+ -+ ag71xx_dump_regs(ag); -+ -+ ag71xx_hw_init(ag); -+ -+ ag71xx_dump_regs(ag); -+ -+ err = ag71xx_phy_connect(ag); -+ if (err) -+ goto err_unregister_netdev; -+ -+ err = ag71xx_debugfs_init(ag); -+ if (err) -+ goto err_phy_disconnect; -+ -+ platform_set_drvdata(pdev, dev); -+ -+ return 0; -+ -+err_phy_disconnect: -+ ag71xx_phy_disconnect(ag); -+err_unregister_netdev: -+ unregister_netdev(dev); -+err_free_desc: -+ dma_free_coherent(NULL, sizeof(struct ag71xx_desc), ag->stop_desc, -+ ag->stop_desc_dma); -+err_free_irq: -+ free_irq(dev->irq, dev); -+err_unmap_mii_ctrl: -+ iounmap(ag->mii_ctrl); -+err_unmap_base: -+ iounmap(ag->mac_base); -+err_free_dev: -+ kfree(dev); -+err_out: -+ platform_set_drvdata(pdev, NULL); -+ return err; -+} -+ -+static int __devexit ag71xx_remove(struct platform_device *pdev) -+{ -+ struct net_device *dev = platform_get_drvdata(pdev); -+ -+ if (dev) { -+ struct ag71xx *ag = netdev_priv(dev); -+ -+ ag71xx_debugfs_exit(ag); -+ ag71xx_phy_disconnect(ag); -+ unregister_netdev(dev); -+ free_irq(dev->irq, dev); -+ iounmap(ag->mii_ctrl); -+ iounmap(ag->mac_base); -+ kfree(dev); -+ platform_set_drvdata(pdev, NULL); -+ } -+ -+ return 0; -+} -+ -+static struct platform_driver ag71xx_driver = { -+ .probe = ag71xx_probe, -+ .remove = __exit_p(ag71xx_remove), -+ .driver = { -+ .name = AG71XX_DRV_NAME, -+ } -+}; -+ -+static int __init ag71xx_module_init(void) -+{ -+ int ret; -+ -+ ret = ag71xx_debugfs_root_init(); -+ if (ret) -+ goto err_out; -+ -+ ret = ag71xx_mdio_driver_init(); -+ if (ret) -+ goto err_debugfs_exit; -+ -+ ret = platform_driver_register(&ag71xx_driver); -+ if (ret) -+ goto err_mdio_exit; -+ -+ return 0; -+ -+err_mdio_exit: -+ ag71xx_mdio_driver_exit(); -+err_debugfs_exit: -+ ag71xx_debugfs_root_exit(); -+err_out: -+ return ret; -+} -+ -+static void __exit ag71xx_module_exit(void) -+{ -+ platform_driver_unregister(&ag71xx_driver); -+ ag71xx_mdio_driver_exit(); -+ ag71xx_debugfs_root_exit(); -+} -+ -+module_init(ag71xx_module_init); -+module_exit(ag71xx_module_exit); -+ -+MODULE_VERSION(AG71XX_DRV_VERSION); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_AUTHOR("Imre Kaloz "); -+MODULE_LICENSE("GPL v2"); -+MODULE_ALIAS("platform:" AG71XX_DRV_NAME); -diff -Nur linux-2.6.39.orig/drivers/net/ag71xx/ag71xx_mdio.c linux-2.6.39/drivers/net/ag71xx/ag71xx_mdio.c ---- linux-2.6.39.orig/drivers/net/ag71xx/ag71xx_mdio.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/drivers/net/ag71xx/ag71xx_mdio.c 2011-08-24 18:17:24.000000000 +0200 -@@ -0,0 +1,248 @@ -+/* -+ * Atheros AR71xx built-in ethernet mac driver -+ * -+ * Copyright (C) 2008-2010 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Based on Atheros' AG7100 driver -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include "ag71xx.h" -+ -+#define AG71XX_MDIO_RETRY 1000 -+#define AG71XX_MDIO_DELAY 5 -+ -+static inline void ag71xx_mdio_wr(struct ag71xx_mdio *am, unsigned reg, -+ u32 value) -+{ -+ void __iomem *r; -+ -+ r = am->mdio_base + reg; -+ __raw_writel(value, r); -+ -+ /* flush write */ -+ (void) __raw_readl(r); -+} -+ -+static inline u32 ag71xx_mdio_rr(struct ag71xx_mdio *am, unsigned reg) -+{ -+ return __raw_readl(am->mdio_base + reg); -+} -+ -+static void ag71xx_mdio_dump_regs(struct ag71xx_mdio *am) -+{ -+ DBG("%s: mii_cfg=%08x, mii_cmd=%08x, mii_addr=%08x\n", -+ am->mii_bus->name, -+ ag71xx_mdio_rr(am, AG71XX_REG_MII_CFG), -+ ag71xx_mdio_rr(am, AG71XX_REG_MII_CMD), -+ ag71xx_mdio_rr(am, AG71XX_REG_MII_ADDR)); -+ DBG("%s: mii_ctrl=%08x, mii_status=%08x, mii_ind=%08x\n", -+ am->mii_bus->name, -+ ag71xx_mdio_rr(am, AG71XX_REG_MII_CTRL), -+ ag71xx_mdio_rr(am, AG71XX_REG_MII_STATUS), -+ ag71xx_mdio_rr(am, AG71XX_REG_MII_IND)); -+} -+ -+int ag71xx_mdio_mii_read(struct ag71xx_mdio *am, int addr, int reg) -+{ -+ int ret; -+ int i; -+ -+ ag71xx_mdio_wr(am, AG71XX_REG_MII_CMD, MII_CMD_WRITE); -+ ag71xx_mdio_wr(am, AG71XX_REG_MII_ADDR, -+ ((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff)); -+ ag71xx_mdio_wr(am, AG71XX_REG_MII_CMD, MII_CMD_READ); -+ -+ i = AG71XX_MDIO_RETRY; -+ while (ag71xx_mdio_rr(am, AG71XX_REG_MII_IND) & MII_IND_BUSY) { -+ if (i-- == 0) { -+ printk(KERN_ERR "%s: mii_read timed out\n", -+ am->mii_bus->name); -+ ret = 0xffff; -+ goto out; -+ } -+ udelay(AG71XX_MDIO_DELAY); -+ } -+ -+ ret = ag71xx_mdio_rr(am, AG71XX_REG_MII_STATUS) & 0xffff; -+ ag71xx_mdio_wr(am, AG71XX_REG_MII_CMD, MII_CMD_WRITE); -+ -+ DBG("mii_read: addr=%04x, reg=%04x, value=%04x\n", addr, reg, ret); -+ -+out: -+ return ret; -+} -+ -+void ag71xx_mdio_mii_write(struct ag71xx_mdio *am, int addr, int reg, u16 val) -+{ -+ int i; -+ -+ DBG("mii_write: addr=%04x, reg=%04x, value=%04x\n", addr, reg, val); -+ -+ ag71xx_mdio_wr(am, AG71XX_REG_MII_ADDR, -+ ((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff)); -+ ag71xx_mdio_wr(am, AG71XX_REG_MII_CTRL, val); -+ -+ i = AG71XX_MDIO_RETRY; -+ while (ag71xx_mdio_rr(am, AG71XX_REG_MII_IND) & MII_IND_BUSY) { -+ if (i-- == 0) { -+ printk(KERN_ERR "%s: mii_write timed out\n", -+ am->mii_bus->name); -+ break; -+ } -+ udelay(AG71XX_MDIO_DELAY); -+ } -+} -+ -+static int ag71xx_mdio_reset(struct mii_bus *bus) -+{ -+ struct ag71xx_mdio *am = bus->priv; -+ u32 t; -+ -+ if (am->pdata->is_ar7240) -+ t = MII_CFG_CLK_DIV_6; -+ else -+ t = MII_CFG_CLK_DIV_28; -+ -+ ag71xx_mdio_wr(am, AG71XX_REG_MII_CFG, t | MII_CFG_RESET); -+ udelay(100); -+ -+ ag71xx_mdio_wr(am, AG71XX_REG_MII_CFG, t); -+ udelay(100); -+ -+ return 0; -+} -+ -+static int ag71xx_mdio_read(struct mii_bus *bus, int addr, int reg) -+{ -+ struct ag71xx_mdio *am = bus->priv; -+ -+ if (am->pdata->is_ar7240) -+ return ar7240sw_phy_read(bus, addr, reg); -+ else -+ return ag71xx_mdio_mii_read(am, addr, reg); -+} -+ -+static int ag71xx_mdio_write(struct mii_bus *bus, int addr, int reg, u16 val) -+{ -+ struct ag71xx_mdio *am = bus->priv; -+ -+ if (am->pdata->is_ar7240) -+ ar7240sw_phy_write(bus, addr, reg, val); -+ else -+ ag71xx_mdio_mii_write(am, addr, reg, val); -+ return 0; -+} -+ -+static int __devinit ag71xx_mdio_probe(struct platform_device *pdev) -+{ -+ struct ag71xx_mdio_platform_data *pdata; -+ struct ag71xx_mdio *am; -+ struct resource *res; -+ int i; -+ int err; -+ -+ pdata = pdev->dev.platform_data; -+ if (!pdata) { -+ dev_err(&pdev->dev, "no platform data specified\n"); -+ return -EINVAL; -+ } -+ -+ am = kzalloc(sizeof(*am), GFP_KERNEL); -+ if (!am) { -+ err = -ENOMEM; -+ goto err_out; -+ } -+ -+ am->pdata = pdata; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (!res) { -+ dev_err(&pdev->dev, "no iomem resource found\n"); -+ err = -ENXIO; -+ goto err_out; -+ } -+ -+ am->mdio_base = ioremap_nocache(res->start, res->end - res->start + 1); -+ if (!am->mdio_base) { -+ dev_err(&pdev->dev, "unable to ioremap registers\n"); -+ err = -ENOMEM; -+ goto err_free_mdio; -+ } -+ -+ am->mii_bus = mdiobus_alloc(); -+ if (am->mii_bus == NULL) { -+ err = -ENOMEM; -+ goto err_iounmap; -+ } -+ -+ am->mii_bus->name = "ag71xx_mdio"; -+ am->mii_bus->read = ag71xx_mdio_read; -+ am->mii_bus->write = ag71xx_mdio_write; -+ am->mii_bus->reset = ag71xx_mdio_reset; -+ am->mii_bus->irq = am->mii_irq; -+ am->mii_bus->priv = am; -+ am->mii_bus->parent = &pdev->dev; -+ snprintf(am->mii_bus->id, MII_BUS_ID_SIZE, "%s", dev_name(&pdev->dev)); -+ am->mii_bus->phy_mask = pdata->phy_mask; -+ -+ for (i = 0; i < PHY_MAX_ADDR; i++) -+ am->mii_irq[i] = PHY_POLL; -+ -+ ag71xx_mdio_wr(am, AG71XX_REG_MAC_CFG1, 0); -+ -+ err = mdiobus_register(am->mii_bus); -+ if (err) -+ goto err_free_bus; -+ -+ ag71xx_mdio_dump_regs(am); -+ -+ platform_set_drvdata(pdev, am); -+ return 0; -+ -+err_free_bus: -+ mdiobus_free(am->mii_bus); -+err_iounmap: -+ iounmap(am->mdio_base); -+err_free_mdio: -+ kfree(am); -+err_out: -+ return err; -+} -+ -+static int __devexit ag71xx_mdio_remove(struct platform_device *pdev) -+{ -+ struct ag71xx_mdio *am = platform_get_drvdata(pdev); -+ -+ if (am) { -+ mdiobus_unregister(am->mii_bus); -+ mdiobus_free(am->mii_bus); -+ iounmap(am->mdio_base); -+ kfree(am); -+ platform_set_drvdata(pdev, NULL); -+ } -+ -+ return 0; -+} -+ -+static struct platform_driver ag71xx_mdio_driver = { -+ .probe = ag71xx_mdio_probe, -+ .remove = __exit_p(ag71xx_mdio_remove), -+ .driver = { -+ .name = "ag71xx-mdio", -+ } -+}; -+ -+int __init ag71xx_mdio_driver_init(void) -+{ -+ return platform_driver_register(&ag71xx_mdio_driver); -+} -+ -+void ag71xx_mdio_driver_exit(void) -+{ -+ platform_driver_unregister(&ag71xx_mdio_driver); -+} -diff -Nur linux-2.6.39.orig/drivers/net/ag71xx/ag71xx_phy.c linux-2.6.39/drivers/net/ag71xx/ag71xx_phy.c ---- linux-2.6.39.orig/drivers/net/ag71xx/ag71xx_phy.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/drivers/net/ag71xx/ag71xx_phy.c 2011-08-24 18:17:24.000000000 +0200 -@@ -0,0 +1,228 @@ -+/* -+ * Atheros AR71xx built-in ethernet mac driver -+ * -+ * Copyright (C) 2008-2010 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Based on Atheros' AG7100 driver -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include "ag71xx.h" -+ -+static void ag71xx_phy_link_adjust(struct net_device *dev) -+{ -+ struct ag71xx *ag = netdev_priv(dev); -+ struct phy_device *phydev = ag->phy_dev; -+ unsigned long flags; -+ int status_change = 0; -+ -+ spin_lock_irqsave(&ag->lock, flags); -+ -+ if (phydev->link) { -+ if (ag->duplex != phydev->duplex -+ || ag->speed != phydev->speed) { -+ status_change = 1; -+ } -+ } -+ -+ if (phydev->link != ag->link) -+ status_change = 1; -+ -+ ag->link = phydev->link; -+ ag->duplex = phydev->duplex; -+ ag->speed = phydev->speed; -+ -+ if (status_change) -+ ag71xx_link_adjust(ag); -+ -+ spin_unlock_irqrestore(&ag->lock, flags); -+} -+ -+void ag71xx_phy_start(struct ag71xx *ag) -+{ -+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); -+ -+ if (ag->phy_dev) { -+ phy_start(ag->phy_dev); -+ } else if (pdata->has_ar7240_switch) { -+ ag71xx_ar7240_start(ag); -+ } else { -+ ag->link = 1; -+ ag71xx_link_adjust(ag); -+ } -+} -+ -+void ag71xx_phy_stop(struct ag71xx *ag) -+{ -+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); -+ -+ if (ag->phy_dev) { -+ phy_stop(ag->phy_dev); -+ } else { -+ if (pdata->has_ar7240_switch) -+ ag71xx_ar7240_stop(ag); -+ ag->link = 0; -+ ag71xx_link_adjust(ag); -+ } -+} -+ -+static int ag71xx_phy_connect_fixed(struct ag71xx *ag) -+{ -+ struct net_device *dev = ag->dev; -+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); -+ int ret = 0; -+ -+ /* use fixed settings */ -+ switch (pdata->speed) { -+ case SPEED_10: -+ case SPEED_100: -+ case SPEED_1000: -+ break; -+ default: -+ printk(KERN_ERR "%s: invalid speed specified\n", dev->name); -+ ret = -EINVAL; -+ break; -+ } -+ -+ printk(KERN_DEBUG "%s: using fixed link parameters\n", dev->name); -+ -+ ag->duplex = pdata->duplex; -+ ag->speed = pdata->speed; -+ -+ return ret; -+} -+ -+static int ag71xx_phy_connect_multi(struct ag71xx *ag) -+{ -+ struct net_device *dev = ag->dev; -+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); -+ struct phy_device *phydev = NULL; -+ int phy_addr; -+ int ret = 0; -+ -+ for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { -+ if (!(pdata->phy_mask & (1 << phy_addr))) -+ continue; -+ -+ if (ag->mii_bus->phy_map[phy_addr] == NULL) -+ continue; -+ -+ DBG("%s: PHY found at %s, uid=%08x\n", -+ dev->name, -+ dev_name(&ag->mii_bus->phy_map[phy_addr]->dev), -+ ag->mii_bus->phy_map[phy_addr]->phy_id); -+ -+ if (phydev == NULL) -+ phydev = ag->mii_bus->phy_map[phy_addr]; -+ } -+ -+ if (!phydev) { -+ printk(KERN_ERR "%s: no PHY found with phy_mask=%08x\n", -+ dev->name, pdata->phy_mask); -+ return -ENODEV; -+ } -+ -+ ag->phy_dev = phy_connect(dev, dev_name(&phydev->dev), -+ &ag71xx_phy_link_adjust, 0, -+ pdata->phy_if_mode); -+ -+ if (IS_ERR(ag->phy_dev)) { -+ printk(KERN_ERR "%s: could not connect to PHY at %s\n", -+ dev->name, dev_name(&phydev->dev)); -+ return PTR_ERR(ag->phy_dev); -+ } -+ -+ /* mask with MAC supported features */ -+ if (pdata->has_gbit) -+ phydev->supported &= PHY_GBIT_FEATURES; -+ else -+ phydev->supported &= PHY_BASIC_FEATURES; -+ -+ phydev->advertising = phydev->supported; -+ -+ printk(KERN_DEBUG "%s: connected to PHY at %s [uid=%08x, driver=%s]\n", -+ dev->name, dev_name(&phydev->dev), -+ phydev->phy_id, phydev->drv->name); -+ -+ ag->link = 0; -+ ag->speed = 0; -+ ag->duplex = -1; -+ -+ return ret; -+} -+ -+static int dev_is_class(struct device *dev, void *class) -+{ -+ if (dev->class != NULL && !strcmp(dev->class->name, class)) -+ return 1; -+ -+ return 0; -+} -+ -+static struct device *dev_find_class(struct device *parent, char *class) -+{ -+ if (dev_is_class(parent, class)) { -+ get_device(parent); -+ return parent; -+ } -+ -+ return device_find_child(parent, class, dev_is_class); -+} -+ -+static struct mii_bus *dev_to_mii_bus(struct device *dev) -+{ -+ struct device *d; -+ -+ d = dev_find_class(dev, "mdio_bus"); -+ if (d != NULL) { -+ struct mii_bus *bus; -+ -+ bus = to_mii_bus(d); -+ put_device(d); -+ -+ return bus; -+ } -+ -+ return NULL; -+} -+ -+int __devinit ag71xx_phy_connect(struct ag71xx *ag) -+{ -+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); -+ -+ ag->mii_bus = dev_to_mii_bus(pdata->mii_bus_dev); -+ if (ag->mii_bus == NULL) { -+ printk(KERN_ERR "%s: unable to find MII bus on device '%s'\n", -+ ag->dev->name, dev_name(pdata->mii_bus_dev)); -+ return -ENODEV; -+ } -+ -+ /* Reset the mdio bus explicitly */ -+ if (ag->mii_bus->reset) { -+ mutex_lock(&ag->mii_bus->mdio_lock); -+ ag->mii_bus->reset(ag->mii_bus); -+ mutex_unlock(&ag->mii_bus->mdio_lock); -+ } -+ -+ if (pdata->has_ar7240_switch) -+ return ag71xx_ar7240_init(ag); -+ -+ if (pdata->phy_mask) -+ return ag71xx_phy_connect_multi(ag); -+ -+ return ag71xx_phy_connect_fixed(ag); -+} -+ -+void ag71xx_phy_disconnect(struct ag71xx *ag) -+{ -+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); -+ -+ if (pdata->has_ar7240_switch) -+ ag71xx_ar7240_cleanup(ag); -+ else if (ag->phy_dev) -+ phy_disconnect(ag->phy_dev); -+} -diff -Nur linux-2.6.39.orig/drivers/net/phy/Kconfig linux-2.6.39/drivers/net/phy/Kconfig ---- linux-2.6.39.orig/drivers/net/phy/Kconfig 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/drivers/net/phy/Kconfig 2011-08-24 18:17:24.000000000 +0200 -@@ -13,6 +13,12 @@ - - if PHYLIB - -+config SWCONFIG -+ tristate "Switch configuration API" -+ ---help--- -+ Switch configuration API using netlink. This allows -+ you to configure the VLAN features of certain switches. -+ - comment "MII PHY device drivers" - - config MARVELL_PHY -diff -Nur linux-2.6.39.orig/drivers/net/phy/Makefile linux-2.6.39/drivers/net/phy/Makefile ---- linux-2.6.39.orig/drivers/net/phy/Makefile 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/drivers/net/phy/Makefile 2011-08-24 18:17:24.000000000 +0200 -@@ -3,6 +3,7 @@ - libphy-objs := phy.o phy_device.o mdio_bus.o - - obj-$(CONFIG_PHYLIB) += libphy.o -+obj-$(CONFIG_SWCONFIG) += swconfig.o - obj-$(CONFIG_MARVELL_PHY) += marvell.o - obj-$(CONFIG_DAVICOM_PHY) += davicom.o - obj-$(CONFIG_CICADA_PHY) += cicada.o -diff -Nur linux-2.6.39.orig/drivers/net/phy/micrel.c linux-2.6.39/drivers/net/phy/micrel.c ---- linux-2.6.39.orig/drivers/net/phy/micrel.c 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/drivers/net/phy/micrel.c 2011-08-24 18:17:24.000000000 +0200 -@@ -1,251 +1,82 @@ - /* -- * drivers/net/phy/micrel.c -+ * Driver for Micrel/Kendin PHYs - * -- * Driver for Micrel PHYs -+ * Copyright (c) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz - * -- * Author: David J. Choi -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. - * -- * Copyright (c) 2010 Micrel, Inc. -- * -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License as published by the -- * Free Software Foundation; either version 2 of the License, or (at your -- * option) any later version. -- * -- * Support : ksz9021 1000/100/10 phy from Micrel -- * ks8001, ks8737, ks8721, ks8041, ks8051 100/10 phy - */ - --#include --#include -+#include -+#include - #include --#include - --/* general Interrupt control/status reg in vendor specific block. */ --#define MII_KSZPHY_INTCS 0x1B --#define KSZPHY_INTCS_JABBER (1 << 15) --#define KSZPHY_INTCS_RECEIVE_ERR (1 << 14) --#define KSZPHY_INTCS_PAGE_RECEIVE (1 << 13) --#define KSZPHY_INTCS_PARELLEL (1 << 12) --#define KSZPHY_INTCS_LINK_PARTNER_ACK (1 << 11) --#define KSZPHY_INTCS_LINK_DOWN (1 << 10) --#define KSZPHY_INTCS_REMOTE_FAULT (1 << 9) --#define KSZPHY_INTCS_LINK_UP (1 << 8) --#define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\ -- KSZPHY_INTCS_LINK_DOWN) -- --/* general PHY control reg in vendor specific block. */ --#define MII_KSZPHY_CTRL 0x1F --/* bitmap of PHY register to set interrupt mode */ --#define KSZPHY_CTRL_INT_ACTIVE_HIGH (1 << 9) --#define KSZ9021_CTRL_INT_ACTIVE_HIGH (1 << 14) --#define KS8737_CTRL_INT_ACTIVE_HIGH (1 << 14) --#define KSZ8051_RMII_50MHZ_CLK (1 << 7) -+#define KSZ_REG_INT_CTRL 0x1b - --static int kszphy_ack_interrupt(struct phy_device *phydev) --{ -- /* bit[7..0] int status, which is a read and clear register. */ -- int rc; -+#define KSZ_INT_LU_EN (1 << 8) /* enable Link Up interrupt */ -+#define KSZ_INT_RF_EN (1 << 9) /* enable Remote Fault interrupt */ -+#define KSZ_INT_LD_EN (1 << 10) /* enable Link Down interrupt */ - -- rc = phy_read(phydev, MII_KSZPHY_INTCS); -- -- return (rc < 0) ? rc : 0; --} -+#define KSZ_INT_INIT (KSZ_INT_LU_EN | KSZ_INT_LD_EN) - --static int kszphy_set_interrupt(struct phy_device *phydev) -+static int ksz8041_ack_interrupt(struct phy_device *phydev) - { -- int temp; -- temp = (PHY_INTERRUPT_ENABLED == phydev->interrupts) ? -- KSZPHY_INTCS_ALL : 0; -- return phy_write(phydev, MII_KSZPHY_INTCS, temp); --} -+ int err; - --static int kszphy_config_intr(struct phy_device *phydev) --{ -- int temp, rc; -+ err = phy_read(phydev, KSZ_REG_INT_CTRL); - -- /* set the interrupt pin active low */ -- temp = phy_read(phydev, MII_KSZPHY_CTRL); -- temp &= ~KSZPHY_CTRL_INT_ACTIVE_HIGH; -- phy_write(phydev, MII_KSZPHY_CTRL, temp); -- rc = kszphy_set_interrupt(phydev); -- return rc < 0 ? rc : 0; -+ return (err < 0) ? err : 0; - } - --static int ksz9021_config_intr(struct phy_device *phydev) -+static int ksz8041_config_intr(struct phy_device *phydev) - { -- int temp, rc; -+ int err; - -- /* set the interrupt pin active low */ -- temp = phy_read(phydev, MII_KSZPHY_CTRL); -- temp &= ~KSZ9021_CTRL_INT_ACTIVE_HIGH; -- phy_write(phydev, MII_KSZPHY_CTRL, temp); -- rc = kszphy_set_interrupt(phydev); -- return rc < 0 ? rc : 0; --} -- --static int ks8737_config_intr(struct phy_device *phydev) --{ -- int temp, rc; -+ if (phydev->interrupts == PHY_INTERRUPT_ENABLED) -+ err = phy_write(phydev, KSZ_REG_INT_CTRL, -+ KSZ_INT_INIT); -+ else -+ err = phy_write(phydev, KSZ_REG_INT_CTRL, 0); - -- /* set the interrupt pin active low */ -- temp = phy_read(phydev, MII_KSZPHY_CTRL); -- temp &= ~KS8737_CTRL_INT_ACTIVE_HIGH; -- phy_write(phydev, MII_KSZPHY_CTRL, temp); -- rc = kszphy_set_interrupt(phydev); -- return rc < 0 ? rc : 0; -+ return err; - } - --static int kszphy_config_init(struct phy_device *phydev) --{ -- return 0; --} -- --static int ks8051_config_init(struct phy_device *phydev) --{ -- int regval; -- -- if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) { -- regval = phy_read(phydev, MII_KSZPHY_CTRL); -- regval |= KSZ8051_RMII_50MHZ_CLK; -- phy_write(phydev, MII_KSZPHY_CTRL, regval); -- } -- -- return 0; --} -- --static struct phy_driver ks8737_driver = { -- .phy_id = PHY_ID_KS8737, -- .phy_id_mask = 0x00fffff0, -- .name = "Micrel KS8737", -- .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause), -- .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, -- .config_init = kszphy_config_init, -+static struct phy_driver ksz8041_phy_driver = { -+ .phy_id = 0x00221512, -+ .name = "Micrel KSZ8041", -+ .phy_id_mask = 0x001fffff, -+ .features = PHY_BASIC_FEATURES, -+ .flags = PHY_HAS_INTERRUPT, - .config_aneg = genphy_config_aneg, - .read_status = genphy_read_status, -- .ack_interrupt = kszphy_ack_interrupt, -- .config_intr = ks8737_config_intr, -- .driver = { .owner = THIS_MODULE,}, -+ .ack_interrupt = ksz8041_ack_interrupt, -+ .config_intr = ksz8041_config_intr, -+ .driver = { -+ .owner = THIS_MODULE, -+ }, - }; - --static struct phy_driver ks8041_driver = { -- .phy_id = PHY_ID_KS8041, -- .phy_id_mask = 0x00fffff0, -- .name = "Micrel KS8041", -- .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause -- | SUPPORTED_Asym_Pause), -- .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, -- .config_init = kszphy_config_init, -- .config_aneg = genphy_config_aneg, -- .read_status = genphy_read_status, -- .ack_interrupt = kszphy_ack_interrupt, -- .config_intr = kszphy_config_intr, -- .driver = { .owner = THIS_MODULE,}, --}; -- --static struct phy_driver ks8051_driver = { -- .phy_id = PHY_ID_KS8051, -- .phy_id_mask = 0x00fffff0, -- .name = "Micrel KS8051", -- .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause -- | SUPPORTED_Asym_Pause), -- .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, -- .config_init = ks8051_config_init, -- .config_aneg = genphy_config_aneg, -- .read_status = genphy_read_status, -- .ack_interrupt = kszphy_ack_interrupt, -- .config_intr = kszphy_config_intr, -- .driver = { .owner = THIS_MODULE,}, --}; -- --static struct phy_driver ks8001_driver = { -- .phy_id = PHY_ID_KS8001, -- .name = "Micrel KS8001 or KS8721", -- .phy_id_mask = 0x00fffff0, -- .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause), -- .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, -- .config_init = kszphy_config_init, -- .config_aneg = genphy_config_aneg, -- .read_status = genphy_read_status, -- .ack_interrupt = kszphy_ack_interrupt, -- .config_intr = kszphy_config_intr, -- .driver = { .owner = THIS_MODULE,}, --}; -- --static struct phy_driver ksz9021_driver = { -- .phy_id = PHY_ID_KSZ9021, -- .phy_id_mask = 0x000fff10, -- .name = "Micrel KSZ9021 Gigabit PHY", -- .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause -- | SUPPORTED_Asym_Pause), -- .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, -- .config_init = kszphy_config_init, -- .config_aneg = genphy_config_aneg, -- .read_status = genphy_read_status, -- .ack_interrupt = kszphy_ack_interrupt, -- .config_intr = ksz9021_config_intr, -- .driver = { .owner = THIS_MODULE, }, --}; -- --static int __init ksphy_init(void) -+static int __init micrel_phy_init(void) - { -- int ret; -- -- ret = phy_driver_register(&ks8001_driver); -- if (ret) -- goto err1; -- -- ret = phy_driver_register(&ksz9021_driver); -- if (ret) -- goto err2; -- -- ret = phy_driver_register(&ks8737_driver); -- if (ret) -- goto err3; -- ret = phy_driver_register(&ks8041_driver); -- if (ret) -- goto err4; -- ret = phy_driver_register(&ks8051_driver); -- if (ret) -- goto err5; -- -- return 0; -- --err5: -- phy_driver_unregister(&ks8041_driver); --err4: -- phy_driver_unregister(&ks8737_driver); --err3: -- phy_driver_unregister(&ksz9021_driver); --err2: -- phy_driver_unregister(&ks8001_driver); --err1: -- return ret; -+ return phy_driver_register(&ksz8041_phy_driver); - } - --static void __exit ksphy_exit(void) -+static void __exit micrel_phy_exit(void) - { -- phy_driver_unregister(&ks8001_driver); -- phy_driver_unregister(&ks8737_driver); -- phy_driver_unregister(&ksz9021_driver); -- phy_driver_unregister(&ks8041_driver); -- phy_driver_unregister(&ks8051_driver); -+ phy_driver_unregister(&ksz8041_phy_driver); - } - --module_init(ksphy_init); --module_exit(ksphy_exit); -- --MODULE_DESCRIPTION("Micrel PHY driver"); --MODULE_AUTHOR("David J. Choi"); --MODULE_LICENSE("GPL"); -- --static struct mdio_device_id __maybe_unused micrel_tbl[] = { -- { PHY_ID_KSZ9021, 0x000fff10 }, -- { PHY_ID_KS8001, 0x00fffff0 }, -- { PHY_ID_KS8737, 0x00fffff0 }, -- { PHY_ID_KS8041, 0x00fffff0 }, -- { PHY_ID_KS8051, 0x00fffff0 }, -- { } --}; -+#ifdef MODULE -+module_init(micrel_phy_init); -+module_exit(micrel_phy_exit); -+#else -+subsys_initcall(micrel_phy_init); -+#endif - --MODULE_DEVICE_TABLE(mdio, micrel_tbl); -+MODULE_DESCRIPTION("Micrel/Kendin PHY driver"); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_AUTHOR("Imre Kaloz "); -+MODULE_LICENSE("GPL v2"); -diff -Nur linux-2.6.39.orig/drivers/net/phy/phy.c linux-2.6.39/drivers/net/phy/phy.c ---- linux-2.6.39.orig/drivers/net/phy/phy.c 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/drivers/net/phy/phy.c 2011-08-24 18:17:24.000000000 +0200 -@@ -297,6 +297,50 @@ - } - EXPORT_SYMBOL(phy_ethtool_gset); - -+int phy_ethtool_ioctl(struct phy_device *phydev, void *useraddr) -+{ -+ u32 cmd; -+ int tmp; -+ struct ethtool_cmd ecmd = { ETHTOOL_GSET }; -+ struct ethtool_value edata = { ETHTOOL_GLINK }; -+ -+ if (get_user(cmd, (u32 *) useraddr)) -+ return -EFAULT; -+ -+ switch (cmd) { -+ case ETHTOOL_GSET: -+ phy_ethtool_gset(phydev, &ecmd); -+ if (copy_to_user(useraddr, &ecmd, sizeof(ecmd))) -+ return -EFAULT; -+ return 0; -+ -+ case ETHTOOL_SSET: -+ if (copy_from_user(&ecmd, useraddr, sizeof(ecmd))) -+ return -EFAULT; -+ return phy_ethtool_sset(phydev, &ecmd); -+ -+ case ETHTOOL_NWAY_RST: -+ /* if autoneg is off, it's an error */ -+ tmp = phy_read(phydev, MII_BMCR); -+ if (tmp & BMCR_ANENABLE) { -+ tmp |= (BMCR_ANRESTART); -+ phy_write(phydev, MII_BMCR, tmp); -+ return 0; -+ } -+ return -EINVAL; -+ -+ case ETHTOOL_GLINK: -+ edata.data = (phy_read(phydev, -+ MII_BMSR) & BMSR_LSTATUS) ? 1 : 0; -+ if (copy_to_user(useraddr, &edata, sizeof(edata))) -+ return -EFAULT; -+ return 0; -+ } -+ -+ return -EOPNOTSUPP; -+} -+EXPORT_SYMBOL(phy_ethtool_ioctl); -+ - /** - * phy_mii_ioctl - generic PHY MII ioctl interface - * @phydev: the phy_device struct -@@ -472,7 +516,7 @@ - int idx; - - idx = phy_find_setting(phydev->speed, phydev->duplex); -- -+ - idx++; - - idx = phy_find_valid(idx, phydev->supported); -diff -Nur linux-2.6.39.orig/drivers/net/phy/phy_device.c linux-2.6.39/drivers/net/phy/phy_device.c ---- linux-2.6.39.orig/drivers/net/phy/phy_device.c 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/drivers/net/phy/phy_device.c 2011-08-24 18:17:24.000000000 +0200 -@@ -149,6 +149,18 @@ - } - EXPORT_SYMBOL(phy_scan_fixups); - -+static int generic_receive_skb(struct sk_buff *skb) -+{ -+ skb->protocol = eth_type_trans(skb, skb->dev); -+ return netif_receive_skb(skb); -+} -+ -+static int generic_rx(struct sk_buff *skb) -+{ -+ skb->protocol = eth_type_trans(skb, skb->dev); -+ return netif_rx(skb); -+} -+ - static struct phy_device* phy_device_create(struct mii_bus *bus, - int addr, int phy_id) - { -@@ -180,6 +192,8 @@ - dev_set_name(&dev->dev, PHY_ID_FMT, bus->id, addr); - - dev->state = PHY_DOWN; -+ dev->netif_receive_skb = &generic_receive_skb; -+ dev->netif_rx = &generic_rx; - - mutex_init(&dev->lock); - INIT_DELAYED_WORK(&dev->state_queue, phy_state_machine); -diff -Nur linux-2.6.39.orig/drivers/net/phy/swconfig.c linux-2.6.39/drivers/net/phy/swconfig.c ---- linux-2.6.39.orig/drivers/net/phy/swconfig.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/drivers/net/phy/swconfig.c 2011-08-24 18:17:24.000000000 +0200 -@@ -0,0 +1,954 @@ -+/* -+ * swconfig.c: Switch configuration API -+ * -+ * Copyright (C) 2008 Felix Fietkau -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+//#define DEBUG 1 -+#ifdef DEBUG -+#define DPRINTF(format, ...) printk("%s: " format, __func__, ##__VA_ARGS__) -+#else -+#define DPRINTF(...) do {} while(0) -+#endif -+ -+#define SWCONFIG_DEVNAME "switch%d" -+ -+MODULE_AUTHOR("Felix Fietkau "); -+MODULE_LICENSE("GPL"); -+ -+static int swdev_id = 0; -+static struct list_head swdevs; -+static DEFINE_SPINLOCK(swdevs_lock); -+struct swconfig_callback; -+ -+struct swconfig_callback -+{ -+ struct sk_buff *msg; -+ struct genlmsghdr *hdr; -+ struct genl_info *info; -+ int cmd; -+ -+ /* callback for filling in the message data */ -+ int (*fill)(struct swconfig_callback *cb, void *arg); -+ -+ /* callback for closing the message before sending it */ -+ int (*close)(struct swconfig_callback *cb, void *arg); -+ -+ struct nlattr *nest[4]; -+ int args[4]; -+}; -+ -+/* defaults */ -+ -+static int -+swconfig_get_vlan_ports(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) -+{ -+ int ret; -+ if (val->port_vlan >= dev->vlans) -+ return -EINVAL; -+ -+ if (!dev->ops->get_vlan_ports) -+ return -EOPNOTSUPP; -+ -+ ret = dev->ops->get_vlan_ports(dev, val); -+ return ret; -+} -+ -+static int -+swconfig_set_vlan_ports(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) -+{ -+ struct switch_port *ports = val->value.ports; -+ const struct switch_dev_ops *ops = dev->ops; -+ int i; -+ -+ if (val->port_vlan >= dev->vlans) -+ return -EINVAL; -+ -+ /* validate ports */ -+ if (val->len > dev->ports) -+ return -EINVAL; -+ -+ if (!ops->set_vlan_ports) -+ return -EOPNOTSUPP; -+ -+ for (i = 0; i < val->len; i++) { -+ if (ports[i].id >= dev->ports) -+ return -EINVAL; -+ -+ if (ops->set_port_pvid && -+ !(ports[i].flags & (1 << SWITCH_PORT_FLAG_TAGGED))) -+ ops->set_port_pvid(dev, ports[i].id, val->port_vlan); -+ } -+ -+ return ops->set_vlan_ports(dev, val); -+} -+ -+static int -+swconfig_set_pvid(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) -+{ -+ if (val->port_vlan >= dev->ports) -+ return -EINVAL; -+ -+ if (!dev->ops->set_port_pvid) -+ return -EOPNOTSUPP; -+ -+ return dev->ops->set_port_pvid(dev, val->port_vlan, val->value.i); -+} -+ -+static int -+swconfig_get_pvid(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) -+{ -+ if (val->port_vlan >= dev->ports) -+ return -EINVAL; -+ -+ if (!dev->ops->get_port_pvid) -+ return -EOPNOTSUPP; -+ -+ return dev->ops->get_port_pvid(dev, val->port_vlan, &val->value.i); -+} -+ -+static int -+swconfig_apply_config(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) -+{ -+ /* don't complain if not supported by the switch driver */ -+ if (!dev->ops->apply_config) -+ return 0; -+ -+ return dev->ops->apply_config(dev); -+} -+ -+static int -+swconfig_reset_switch(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val) -+{ -+ /* don't complain if not supported by the switch driver */ -+ if (!dev->ops->reset_switch) -+ return 0; -+ -+ return dev->ops->reset_switch(dev); -+} -+ -+enum global_defaults { -+ GLOBAL_APPLY, -+ GLOBAL_RESET, -+}; -+ -+enum vlan_defaults { -+ VLAN_PORTS, -+}; -+ -+enum port_defaults { -+ PORT_PVID, -+}; -+ -+static struct switch_attr default_global[] = { -+ [GLOBAL_APPLY] = { -+ .type = SWITCH_TYPE_NOVAL, -+ .name = "apply", -+ .description = "Activate changes in the hardware", -+ .set = swconfig_apply_config, -+ }, -+ [GLOBAL_RESET] = { -+ .type = SWITCH_TYPE_NOVAL, -+ .name = "reset", -+ .description = "Reset the switch", -+ .set = swconfig_reset_switch, -+ } -+}; -+ -+static struct switch_attr default_port[] = { -+ [PORT_PVID] = { -+ .type = SWITCH_TYPE_INT, -+ .name = "pvid", -+ .description = "Primary VLAN ID", -+ .set = swconfig_set_pvid, -+ .get = swconfig_get_pvid, -+ } -+}; -+ -+static struct switch_attr default_vlan[] = { -+ [VLAN_PORTS] = { -+ .type = SWITCH_TYPE_PORTS, -+ .name = "ports", -+ .description = "VLAN port mapping", -+ .set = swconfig_set_vlan_ports, -+ .get = swconfig_get_vlan_ports, -+ }, -+}; -+ -+ -+static void swconfig_defaults_init(struct switch_dev *dev) -+{ -+ const struct switch_dev_ops *ops = dev->ops; -+ -+ dev->def_global = 0; -+ dev->def_vlan = 0; -+ dev->def_port = 0; -+ -+ if (ops->get_vlan_ports || ops->set_vlan_ports) -+ set_bit(VLAN_PORTS, &dev->def_vlan); -+ -+ if (ops->get_port_pvid || ops->set_port_pvid) -+ set_bit(PORT_PVID, &dev->def_port); -+ -+ /* always present, can be no-op */ -+ set_bit(GLOBAL_APPLY, &dev->def_global); -+ set_bit(GLOBAL_RESET, &dev->def_global); -+} -+ -+ -+static struct genl_family switch_fam = { -+ .id = GENL_ID_GENERATE, -+ .name = "switch", -+ .hdrsize = 0, -+ .version = 1, -+ .maxattr = SWITCH_ATTR_MAX, -+}; -+ -+static const struct nla_policy switch_policy[SWITCH_ATTR_MAX+1] = { -+ [SWITCH_ATTR_ID] = { .type = NLA_U32 }, -+ [SWITCH_ATTR_OP_ID] = { .type = NLA_U32 }, -+ [SWITCH_ATTR_OP_PORT] = { .type = NLA_U32 }, -+ [SWITCH_ATTR_OP_VLAN] = { .type = NLA_U32 }, -+ [SWITCH_ATTR_OP_VALUE_INT] = { .type = NLA_U32 }, -+ [SWITCH_ATTR_OP_VALUE_STR] = { .type = NLA_NUL_STRING }, -+ [SWITCH_ATTR_OP_VALUE_PORTS] = { .type = NLA_NESTED }, -+ [SWITCH_ATTR_TYPE] = { .type = NLA_U32 }, -+}; -+ -+static const struct nla_policy port_policy[SWITCH_PORT_ATTR_MAX+1] = { -+ [SWITCH_PORT_ID] = { .type = NLA_U32 }, -+ [SWITCH_PORT_FLAG_TAGGED] = { .type = NLA_FLAG }, -+}; -+ -+static inline void -+swconfig_lock(void) -+{ -+ spin_lock(&swdevs_lock); -+} -+ -+static inline void -+swconfig_unlock(void) -+{ -+ spin_unlock(&swdevs_lock); -+} -+ -+static struct switch_dev * -+swconfig_get_dev(struct genl_info *info) -+{ -+ struct switch_dev *dev = NULL; -+ struct switch_dev *p; -+ int id; -+ -+ if (!info->attrs[SWITCH_ATTR_ID]) -+ goto done; -+ -+ id = nla_get_u32(info->attrs[SWITCH_ATTR_ID]); -+ swconfig_lock(); -+ list_for_each_entry(p, &swdevs, dev_list) { -+ if (id != p->id) -+ continue; -+ -+ dev = p; -+ break; -+ } -+ if (dev) -+ spin_lock(&dev->lock); -+ else -+ DPRINTF("device %d not found\n", id); -+ swconfig_unlock(); -+done: -+ return dev; -+} -+ -+static inline void -+swconfig_put_dev(struct switch_dev *dev) -+{ -+ spin_unlock(&dev->lock); -+} -+ -+static int -+swconfig_dump_attr(struct swconfig_callback *cb, void *arg) -+{ -+ struct switch_attr *op = arg; -+ struct genl_info *info = cb->info; -+ struct sk_buff *msg = cb->msg; -+ int id = cb->args[0]; -+ void *hdr; -+ -+ hdr = genlmsg_put(msg, info->snd_pid, info->snd_seq, &switch_fam, -+ NLM_F_MULTI, SWITCH_CMD_NEW_ATTR); -+ if (IS_ERR(hdr)) -+ return -1; -+ -+ NLA_PUT_U32(msg, SWITCH_ATTR_OP_ID, id); -+ NLA_PUT_U32(msg, SWITCH_ATTR_OP_TYPE, op->type); -+ NLA_PUT_STRING(msg, SWITCH_ATTR_OP_NAME, op->name); -+ if (op->description) -+ NLA_PUT_STRING(msg, SWITCH_ATTR_OP_DESCRIPTION, -+ op->description); -+ -+ return genlmsg_end(msg, hdr); -+nla_put_failure: -+ genlmsg_cancel(msg, hdr); -+ return -EMSGSIZE; -+} -+ -+/* spread multipart messages across multiple message buffers */ -+static int -+swconfig_send_multipart(struct swconfig_callback *cb, void *arg) -+{ -+ struct genl_info *info = cb->info; -+ int restart = 0; -+ int err; -+ -+ do { -+ if (!cb->msg) { -+ cb->msg = nlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL); -+ if (cb->msg == NULL) -+ goto error; -+ } -+ -+ if (!(cb->fill(cb, arg) < 0)) -+ break; -+ -+ /* fill failed, check if this was already the second attempt */ -+ if (restart) -+ goto error; -+ -+ /* try again in a new message, send the current one */ -+ restart = 1; -+ if (cb->close) { -+ if (cb->close(cb, arg) < 0) -+ goto error; -+ } -+ err = genlmsg_reply(cb->msg, info); -+ cb->msg = NULL; -+ if (err < 0) -+ goto error; -+ -+ } while (restart); -+ -+ return 0; -+ -+error: -+ if (cb->msg) -+ nlmsg_free(cb->msg); -+ return -1; -+} -+ -+static int -+swconfig_list_attrs(struct sk_buff *skb, struct genl_info *info) -+{ -+ struct genlmsghdr *hdr = nlmsg_data(info->nlhdr); -+ const struct switch_attrlist *alist; -+ struct switch_dev *dev; -+ struct swconfig_callback cb; -+ int err = -EINVAL; -+ int i; -+ -+ /* defaults */ -+ struct switch_attr *def_list; -+ unsigned long *def_active; -+ int n_def; -+ -+ dev = swconfig_get_dev(info); -+ if (!dev) -+ return -EINVAL; -+ -+ switch(hdr->cmd) { -+ case SWITCH_CMD_LIST_GLOBAL: -+ alist = &dev->ops->attr_global; -+ def_list = default_global; -+ def_active = &dev->def_global; -+ n_def = ARRAY_SIZE(default_global); -+ break; -+ case SWITCH_CMD_LIST_VLAN: -+ alist = &dev->ops->attr_vlan; -+ def_list = default_vlan; -+ def_active = &dev->def_vlan; -+ n_def = ARRAY_SIZE(default_vlan); -+ break; -+ case SWITCH_CMD_LIST_PORT: -+ alist = &dev->ops->attr_port; -+ def_list = default_port; -+ def_active = &dev->def_port; -+ n_def = ARRAY_SIZE(default_port); -+ break; -+ default: -+ WARN_ON(1); -+ goto out; -+ } -+ -+ memset(&cb, 0, sizeof(cb)); -+ cb.info = info; -+ cb.fill = swconfig_dump_attr; -+ for (i = 0; i < alist->n_attr; i++) { -+ if (alist->attr[i].disabled) -+ continue; -+ cb.args[0] = i; -+ err = swconfig_send_multipart(&cb, (void *) &alist->attr[i]); -+ if (err < 0) -+ goto error; -+ } -+ -+ /* defaults */ -+ for (i = 0; i < n_def; i++) { -+ if (!test_bit(i, def_active)) -+ continue; -+ cb.args[0] = SWITCH_ATTR_DEFAULTS_OFFSET + i; -+ err = swconfig_send_multipart(&cb, (void *) &def_list[i]); -+ if (err < 0) -+ goto error; -+ } -+ swconfig_put_dev(dev); -+ -+ if (!cb.msg) -+ return 0; -+ -+ return genlmsg_reply(cb.msg, info); -+ -+error: -+ if (cb.msg) -+ nlmsg_free(cb.msg); -+out: -+ swconfig_put_dev(dev); -+ return err; -+} -+ -+static const struct switch_attr * -+swconfig_lookup_attr(struct switch_dev *dev, struct genl_info *info, -+ struct switch_val *val) -+{ -+ struct genlmsghdr *hdr = nlmsg_data(info->nlhdr); -+ const struct switch_attrlist *alist; -+ const struct switch_attr *attr = NULL; -+ int attr_id; -+ -+ /* defaults */ -+ struct switch_attr *def_list; -+ unsigned long *def_active; -+ int n_def; -+ -+ if (!info->attrs[SWITCH_ATTR_OP_ID]) -+ goto done; -+ -+ switch(hdr->cmd) { -+ case SWITCH_CMD_SET_GLOBAL: -+ case SWITCH_CMD_GET_GLOBAL: -+ alist = &dev->ops->attr_global; -+ def_list = default_global; -+ def_active = &dev->def_global; -+ n_def = ARRAY_SIZE(default_global); -+ break; -+ case SWITCH_CMD_SET_VLAN: -+ case SWITCH_CMD_GET_VLAN: -+ alist = &dev->ops->attr_vlan; -+ def_list = default_vlan; -+ def_active = &dev->def_vlan; -+ n_def = ARRAY_SIZE(default_vlan); -+ if (!info->attrs[SWITCH_ATTR_OP_VLAN]) -+ goto done; -+ val->port_vlan = nla_get_u32(info->attrs[SWITCH_ATTR_OP_VLAN]); -+ if (val->port_vlan >= dev->vlans) -+ goto done; -+ break; -+ case SWITCH_CMD_SET_PORT: -+ case SWITCH_CMD_GET_PORT: -+ alist = &dev->ops->attr_port; -+ def_list = default_port; -+ def_active = &dev->def_port; -+ n_def = ARRAY_SIZE(default_port); -+ if (!info->attrs[SWITCH_ATTR_OP_PORT]) -+ goto done; -+ val->port_vlan = nla_get_u32(info->attrs[SWITCH_ATTR_OP_PORT]); -+ if (val->port_vlan >= dev->ports) -+ goto done; -+ break; -+ default: -+ WARN_ON(1); -+ goto done; -+ } -+ -+ if (!alist) -+ goto done; -+ -+ attr_id = nla_get_u32(info->attrs[SWITCH_ATTR_OP_ID]); -+ if (attr_id >= SWITCH_ATTR_DEFAULTS_OFFSET) { -+ attr_id -= SWITCH_ATTR_DEFAULTS_OFFSET; -+ if (attr_id >= n_def) -+ goto done; -+ if (!test_bit(attr_id, def_active)) -+ goto done; -+ attr = &def_list[attr_id]; -+ } else { -+ if (attr_id >= alist->n_attr) -+ goto done; -+ attr = &alist->attr[attr_id]; -+ } -+ -+ if (attr->disabled) -+ attr = NULL; -+ -+done: -+ if (!attr) -+ DPRINTF("attribute lookup failed\n"); -+ val->attr = attr; -+ return attr; -+} -+ -+static int -+swconfig_parse_ports(struct sk_buff *msg, struct nlattr *head, -+ struct switch_val *val, int max) -+{ -+ struct nlattr *nla; -+ int rem; -+ -+ val->len = 0; -+ nla_for_each_nested(nla, head, rem) { -+ struct nlattr *tb[SWITCH_PORT_ATTR_MAX+1]; -+ struct switch_port *port = &val->value.ports[val->len]; -+ -+ if (val->len >= max) -+ return -EINVAL; -+ -+ if (nla_parse_nested(tb, SWITCH_PORT_ATTR_MAX, nla, -+ port_policy)) -+ return -EINVAL; -+ -+ if (!tb[SWITCH_PORT_ID]) -+ return -EINVAL; -+ -+ port->id = nla_get_u32(tb[SWITCH_PORT_ID]); -+ if (tb[SWITCH_PORT_FLAG_TAGGED]) -+ port->flags |= (1 << SWITCH_PORT_FLAG_TAGGED); -+ val->len++; -+ } -+ -+ return 0; -+} -+ -+static int -+swconfig_set_attr(struct sk_buff *skb, struct genl_info *info) -+{ -+ const struct switch_attr *attr; -+ struct switch_dev *dev; -+ struct switch_val val; -+ int err = -EINVAL; -+ -+ dev = swconfig_get_dev(info); -+ if (!dev) -+ return -EINVAL; -+ -+ memset(&val, 0, sizeof(val)); -+ attr = swconfig_lookup_attr(dev, info, &val); -+ if (!attr || !attr->set) -+ goto error; -+ -+ val.attr = attr; -+ switch(attr->type) { -+ case SWITCH_TYPE_NOVAL: -+ break; -+ case SWITCH_TYPE_INT: -+ if (!info->attrs[SWITCH_ATTR_OP_VALUE_INT]) -+ goto error; -+ val.value.i = -+ nla_get_u32(info->attrs[SWITCH_ATTR_OP_VALUE_INT]); -+ break; -+ case SWITCH_TYPE_STRING: -+ if (!info->attrs[SWITCH_ATTR_OP_VALUE_STR]) -+ goto error; -+ val.value.s = -+ nla_data(info->attrs[SWITCH_ATTR_OP_VALUE_STR]); -+ break; -+ case SWITCH_TYPE_PORTS: -+ val.value.ports = dev->portbuf; -+ memset(dev->portbuf, 0, -+ sizeof(struct switch_port) * dev->ports); -+ -+ /* TODO: implement multipart? */ -+ if (info->attrs[SWITCH_ATTR_OP_VALUE_PORTS]) { -+ err = swconfig_parse_ports(skb, -+ info->attrs[SWITCH_ATTR_OP_VALUE_PORTS], &val, dev->ports); -+ if (err < 0) -+ goto error; -+ } else { -+ val.len = 0; -+ err = 0; -+ } -+ break; -+ default: -+ goto error; -+ } -+ -+ err = attr->set(dev, attr, &val); -+error: -+ swconfig_put_dev(dev); -+ return err; -+} -+ -+static int -+swconfig_close_portlist(struct swconfig_callback *cb, void *arg) -+{ -+ if (cb->nest[0]) -+ nla_nest_end(cb->msg, cb->nest[0]); -+ return 0; -+} -+ -+static int -+swconfig_send_port(struct swconfig_callback *cb, void *arg) -+{ -+ const struct switch_port *port = arg; -+ struct nlattr *p = NULL; -+ -+ if (!cb->nest[0]) { -+ cb->nest[0] = nla_nest_start(cb->msg, cb->cmd); -+ if (!cb->nest[0]) -+ return -1; -+ } -+ -+ p = nla_nest_start(cb->msg, SWITCH_ATTR_PORT); -+ if (!p) -+ goto error; -+ -+ NLA_PUT_U32(cb->msg, SWITCH_PORT_ID, port->id); -+ if (port->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) -+ NLA_PUT_FLAG(cb->msg, SWITCH_PORT_FLAG_TAGGED); -+ -+ nla_nest_end(cb->msg, p); -+ return 0; -+ -+nla_put_failure: -+ nla_nest_cancel(cb->msg, p); -+error: -+ nla_nest_cancel(cb->msg, cb->nest[0]); -+ return -1; -+} -+ -+static int -+swconfig_send_ports(struct sk_buff **msg, struct genl_info *info, int attr, -+ const struct switch_val *val) -+{ -+ struct swconfig_callback cb; -+ int err = 0; -+ int i; -+ -+ if (!val->value.ports) -+ return -EINVAL; -+ -+ memset(&cb, 0, sizeof(cb)); -+ cb.cmd = attr; -+ cb.msg = *msg; -+ cb.info = info; -+ cb.fill = swconfig_send_port; -+ cb.close = swconfig_close_portlist; -+ -+ cb.nest[0] = nla_nest_start(cb.msg, cb.cmd); -+ for (i = 0; i < val->len; i++) { -+ err = swconfig_send_multipart(&cb, &val->value.ports[i]); -+ if (err) -+ goto done; -+ } -+ err = val->len; -+ swconfig_close_portlist(&cb, NULL); -+ *msg = cb.msg; -+ -+done: -+ return err; -+} -+ -+static int -+swconfig_get_attr(struct sk_buff *skb, struct genl_info *info) -+{ -+ struct genlmsghdr *hdr = nlmsg_data(info->nlhdr); -+ const struct switch_attr *attr; -+ struct switch_dev *dev; -+ struct sk_buff *msg = NULL; -+ struct switch_val val; -+ int err = -EINVAL; -+ int cmd = hdr->cmd; -+ -+ dev = swconfig_get_dev(info); -+ if (!dev) -+ return -EINVAL; -+ -+ memset(&val, 0, sizeof(val)); -+ attr = swconfig_lookup_attr(dev, info, &val); -+ if (!attr || !attr->get) -+ goto error; -+ -+ if (attr->type == SWITCH_TYPE_PORTS) { -+ val.value.ports = dev->portbuf; -+ memset(dev->portbuf, 0, -+ sizeof(struct switch_port) * dev->ports); -+ } -+ -+ err = attr->get(dev, attr, &val); -+ if (err) -+ goto error; -+ -+ msg = nlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL); -+ if (!msg) -+ goto error; -+ -+ hdr = genlmsg_put(msg, info->snd_pid, info->snd_seq, &switch_fam, -+ 0, cmd); -+ if (IS_ERR(hdr)) -+ goto nla_put_failure; -+ -+ switch(attr->type) { -+ case SWITCH_TYPE_INT: -+ NLA_PUT_U32(msg, SWITCH_ATTR_OP_VALUE_INT, val.value.i); -+ break; -+ case SWITCH_TYPE_STRING: -+ NLA_PUT_STRING(msg, SWITCH_ATTR_OP_VALUE_STR, val.value.s); -+ break; -+ case SWITCH_TYPE_PORTS: -+ err = swconfig_send_ports(&msg, info, -+ SWITCH_ATTR_OP_VALUE_PORTS, &val); -+ if (err < 0) -+ goto nla_put_failure; -+ break; -+ default: -+ DPRINTF("invalid type in attribute\n"); -+ err = -EINVAL; -+ goto error; -+ } -+ err = genlmsg_end(msg, hdr); -+ if (err < 0) -+ goto nla_put_failure; -+ -+ swconfig_put_dev(dev); -+ return genlmsg_reply(msg, info); -+ -+nla_put_failure: -+ if (msg) -+ nlmsg_free(msg); -+error: -+ swconfig_put_dev(dev); -+ if (!err) -+ err = -ENOMEM; -+ return err; -+} -+ -+static int -+swconfig_send_switch(struct sk_buff *msg, u32 pid, u32 seq, int flags, -+ const struct switch_dev *dev) -+{ -+ void *hdr; -+ -+ hdr = genlmsg_put(msg, pid, seq, &switch_fam, flags, -+ SWITCH_CMD_NEW_ATTR); -+ if (IS_ERR(hdr)) -+ return -1; -+ -+ NLA_PUT_U32(msg, SWITCH_ATTR_ID, dev->id); -+ NLA_PUT_STRING(msg, SWITCH_ATTR_DEV_NAME, dev->devname); -+ NLA_PUT_STRING(msg, SWITCH_ATTR_ALIAS, dev->alias); -+ NLA_PUT_STRING(msg, SWITCH_ATTR_NAME, dev->name); -+ NLA_PUT_U32(msg, SWITCH_ATTR_VLANS, dev->vlans); -+ NLA_PUT_U32(msg, SWITCH_ATTR_PORTS, dev->ports); -+ NLA_PUT_U32(msg, SWITCH_ATTR_CPU_PORT, dev->cpu_port); -+ -+ return genlmsg_end(msg, hdr); -+nla_put_failure: -+ genlmsg_cancel(msg, hdr); -+ return -EMSGSIZE; -+} -+ -+static int swconfig_dump_switches(struct sk_buff *skb, -+ struct netlink_callback *cb) -+{ -+ struct switch_dev *dev; -+ int start = cb->args[0]; -+ int idx = 0; -+ -+ swconfig_lock(); -+ list_for_each_entry(dev, &swdevs, dev_list) { -+ if (++idx <= start) -+ continue; -+ if (swconfig_send_switch(skb, NETLINK_CB(cb->skb).pid, -+ cb->nlh->nlmsg_seq, NLM_F_MULTI, -+ dev) < 0) -+ break; -+ } -+ swconfig_unlock(); -+ cb->args[0] = idx; -+ -+ return skb->len; -+} -+ -+static int -+swconfig_done(struct netlink_callback *cb) -+{ -+ return 0; -+} -+ -+static struct genl_ops swconfig_ops[] = { -+ { -+ .cmd = SWITCH_CMD_LIST_GLOBAL, -+ .doit = swconfig_list_attrs, -+ .policy = switch_policy, -+ }, -+ { -+ .cmd = SWITCH_CMD_LIST_VLAN, -+ .doit = swconfig_list_attrs, -+ .policy = switch_policy, -+ }, -+ { -+ .cmd = SWITCH_CMD_LIST_PORT, -+ .doit = swconfig_list_attrs, -+ .policy = switch_policy, -+ }, -+ { -+ .cmd = SWITCH_CMD_GET_GLOBAL, -+ .doit = swconfig_get_attr, -+ .policy = switch_policy, -+ }, -+ { -+ .cmd = SWITCH_CMD_GET_VLAN, -+ .doit = swconfig_get_attr, -+ .policy = switch_policy, -+ }, -+ { -+ .cmd = SWITCH_CMD_GET_PORT, -+ .doit = swconfig_get_attr, -+ .policy = switch_policy, -+ }, -+ { -+ .cmd = SWITCH_CMD_SET_GLOBAL, -+ .doit = swconfig_set_attr, -+ .policy = switch_policy, -+ }, -+ { -+ .cmd = SWITCH_CMD_SET_VLAN, -+ .doit = swconfig_set_attr, -+ .policy = switch_policy, -+ }, -+ { -+ .cmd = SWITCH_CMD_SET_PORT, -+ .doit = swconfig_set_attr, -+ .policy = switch_policy, -+ }, -+ { -+ .cmd = SWITCH_CMD_GET_SWITCH, -+ .dumpit = swconfig_dump_switches, -+ .policy = switch_policy, -+ .done = swconfig_done, -+ } -+}; -+ -+int -+register_switch(struct switch_dev *dev, struct net_device *netdev) -+{ -+ struct switch_dev *sdev; -+ const int max_switches = 8 * sizeof(unsigned long); -+ unsigned long in_use = 0; -+ int i; -+ -+ INIT_LIST_HEAD(&dev->dev_list); -+ if (netdev) { -+ dev->netdev = netdev; -+ if (!dev->alias) -+ dev->alias = netdev->name; -+ } -+ BUG_ON(!dev->alias); -+ -+ if (dev->ports > 0) { -+ dev->portbuf = kzalloc(sizeof(struct switch_port) * dev->ports, -+ GFP_KERNEL); -+ if (!dev->portbuf) -+ return -ENOMEM; -+ } -+ swconfig_defaults_init(dev); -+ spin_lock_init(&dev->lock); -+ swconfig_lock(); -+ dev->id = ++swdev_id; -+ -+ list_for_each_entry(sdev, &swdevs, dev_list) { -+ if (!sscanf(sdev->devname, SWCONFIG_DEVNAME, &i)) -+ continue; -+ if (i < 0 || i > max_switches) -+ continue; -+ -+ set_bit(i, &in_use); -+ } -+ i = find_first_zero_bit(&in_use, max_switches); -+ -+ if (i == max_switches) -+ return -ENFILE; -+ -+ /* fill device name */ -+ snprintf(dev->devname, IFNAMSIZ, SWCONFIG_DEVNAME, i); -+ -+ list_add(&dev->dev_list, &swdevs); -+ swconfig_unlock(); -+ -+ return 0; -+} -+EXPORT_SYMBOL_GPL(register_switch); -+ -+void -+unregister_switch(struct switch_dev *dev) -+{ -+ kfree(dev->portbuf); -+ spin_lock(&dev->lock); -+ swconfig_lock(); -+ list_del(&dev->dev_list); -+ swconfig_unlock(); -+ spin_unlock(&dev->lock); -+} -+EXPORT_SYMBOL_GPL(unregister_switch); -+ -+ -+static int __init -+swconfig_init(void) -+{ -+ int i, err; -+ -+ INIT_LIST_HEAD(&swdevs); -+ err = genl_register_family(&switch_fam); -+ if (err) -+ return err; -+ -+ for (i = 0; i < ARRAY_SIZE(swconfig_ops); i++) { -+ err = genl_register_ops(&switch_fam, &swconfig_ops[i]); -+ if (err) -+ goto unregister; -+ } -+ -+ return 0; -+ -+unregister: -+ genl_unregister_family(&switch_fam); -+ return err; -+} -+ -+static void __exit -+swconfig_exit(void) -+{ -+ genl_unregister_family(&switch_fam); -+} -+ -+module_init(swconfig_init); -+module_exit(swconfig_exit); -+ -diff -Nur linux-2.6.39.orig/drivers/spi/Kconfig linux-2.6.39/drivers/spi/Kconfig ---- linux-2.6.39.orig/drivers/spi/Kconfig 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/drivers/spi/Kconfig 2011-08-24 18:17:24.000000000 +0200 -@@ -67,6 +67,13 @@ - This enables support for the SPI controller present on the - Atheros AR71XX/AR724X/AR913X SoCs. - -+config SPI_AR71XX -+ tristate "Atheros AR71xx SPI Controller" -+ depends on SPI_MASTER && ATHEROS_AR71XX -+ select SPI_BITBANG -+ help -+ This is the SPI contoller driver for Atheros AR71xx. -+ - config SPI_ATMEL - tristate "Atmel SPI Controller" - depends on (ARCH_AT91 || AVR32) -@@ -301,6 +308,12 @@ - config SPI_PXA2XX_PCI - def_bool SPI_PXA2XX && X86_32 && PCI - -+config SPI_RB4XX -+ tristate "Mikrotik RB4XX SPI master" -+ depends on SPI_MASTER && AR71XX_MACH_RB4XX -+ help -+ SPI controller driver for the Mikrotik RB4xx series boards. -+ - config SPI_S3C24XX - tristate "Samsung S3C24XX series SPI" - depends on ARCH_S3C2410 && EXPERIMENTAL -@@ -457,6 +470,13 @@ - sysfs interface, with each line presented as a kind of GPIO - exposing both switch control and diagnostic feedback. - -+config SPI_RB4XX_CPLD -+ tristate "MikroTik RB4XX CPLD driver" -+ depends on AR71XX_MACH_RB4XX -+ help -+ SPI driver for the Xilinx CPLD chip present on the -+ MikroTik RB4xx boards. -+ - # - # Add new SPI protocol masters in alphabetical order above this line - # -diff -Nur linux-2.6.39.orig/drivers/spi/Makefile linux-2.6.39/drivers/spi/Makefile ---- linux-2.6.39.orig/drivers/spi/Makefile 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/drivers/spi/Makefile 2011-08-24 18:17:24.000000000 +0200 -@@ -10,6 +10,7 @@ - - # SPI master controller drivers (bus) - obj-$(CONFIG_SPI_ALTERA) += spi_altera.o -+obj-$(CONFIG_SPI_AR71XX) += ar71xx_spi.o - obj-$(CONFIG_SPI_ATMEL) += atmel_spi.o - obj-$(CONFIG_SPI_ATH79) += ath79_spi.o - obj-$(CONFIG_SPI_BFIN) += spi_bfin5xx.o -@@ -54,6 +55,7 @@ - obj-$(CONFIG_SPI_SH_MSIOF) += spi_sh_msiof.o - obj-$(CONFIG_SPI_STMP3XXX) += spi_stmp.o - obj-$(CONFIG_SPI_NUC900) += spi_nuc900.o -+obj-$(CONFIG_SPI_RB4XX) += rb4xx_spi.o - - # special build for s3c24xx spi driver with fiq support - spi_s3c24xx_hw-y := spi_s3c24xx.o -@@ -62,6 +64,7 @@ - # ... add above this line ... - - # SPI protocol drivers (device/link on bus) -+obj-$(CONFIG_SPI_RB4XX_CPLD) += spi_rb4xx_cpld.o - obj-$(CONFIG_SPI_SPIDEV) += spidev.o - obj-$(CONFIG_SPI_TLE62X0) += tle62x0.o - # ... add above this line ... -diff -Nur linux-2.6.39.orig/drivers/spi/ap83_spi.c linux-2.6.39/drivers/spi/ap83_spi.c ---- linux-2.6.39.orig/drivers/spi/ap83_spi.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/drivers/spi/ap83_spi.c 2011-08-24 18:17:24.000000000 +0200 -@@ -0,0 +1,283 @@ -+/* -+ * Atheros AP83 board specific SPI Controller driver -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#define DRV_DESC "Atheros AP83 board SPI Controller driver" -+#define DRV_VERSION "0.1.0" -+#define DRV_NAME "ap83-spi" -+ -+#define AP83_SPI_CLK_HIGH (1 << 23) -+#define AP83_SPI_CLK_LOW 0 -+#define AP83_SPI_MOSI_HIGH (1 << 22) -+#define AP83_SPI_MOSI_LOW 0 -+ -+#define AP83_SPI_GPIO_CS 1 -+#define AP83_SPI_GPIO_MISO 3 -+ -+struct ap83_spi { -+ struct spi_bitbang bitbang; -+ void __iomem *base; -+ u32 addr; -+ -+ struct platform_device *pdev; -+}; -+ -+static inline u32 ap83_spi_rr(struct ap83_spi *sp, u32 reg) -+{ -+ return __raw_readl(sp->base + reg); -+} -+ -+static inline struct ap83_spi *spidev_to_sp(struct spi_device *spi) -+{ -+ return spi_master_get_devdata(spi->master); -+} -+ -+static inline void setsck(struct spi_device *spi, int val) -+{ -+ struct ap83_spi *sp = spidev_to_sp(spi); -+ -+ if (val) -+ sp->addr |= AP83_SPI_CLK_HIGH; -+ else -+ sp->addr &= ~AP83_SPI_CLK_HIGH; -+ -+ dev_dbg(&spi->dev, "addr=%08x, SCK set to %s\n", -+ sp->addr, (val) ? "HIGH" : "LOW"); -+ -+ ap83_spi_rr(sp, sp->addr); -+} -+ -+static inline void setmosi(struct spi_device *spi, int val) -+{ -+ struct ap83_spi *sp = spidev_to_sp(spi); -+ -+ if (val) -+ sp->addr |= AP83_SPI_MOSI_HIGH; -+ else -+ sp->addr &= ~AP83_SPI_MOSI_HIGH; -+ -+ dev_dbg(&spi->dev, "addr=%08x, MOSI set to %s\n", -+ sp->addr, (val) ? "HIGH" : "LOW"); -+ -+ ap83_spi_rr(sp, sp->addr); -+} -+ -+static inline u32 getmiso(struct spi_device *spi) -+{ -+ u32 ret; -+ -+ ret = gpio_get_value(AP83_SPI_GPIO_MISO) ? 1 : 0; -+ dev_dbg(&spi->dev, "get MISO: %d\n", ret); -+ -+ return ret; -+} -+ -+static inline void do_spidelay(struct spi_device *spi, unsigned nsecs) -+{ -+ ndelay(nsecs); -+} -+ -+static void ap83_spi_chipselect(struct spi_device *spi, int on) -+{ -+ struct ap83_spi *sp = spidev_to_sp(spi); -+ -+ dev_dbg(&spi->dev, "set CS to %d\n", (on) ? 0 : 1); -+ -+ if (on) { -+ ar71xx_flash_acquire(); -+ -+ sp->addr = 0; -+ ap83_spi_rr(sp, sp->addr); -+ -+ gpio_set_value(AP83_SPI_GPIO_CS, 0); -+ } else { -+ gpio_set_value(AP83_SPI_GPIO_CS, 1); -+ ar71xx_flash_release(); -+ } -+} -+ -+#define spidelay(nsecs) \ -+ do { \ -+ /* Steal the spi_device pointer from our caller. \ -+ * The bitbang-API should probably get fixed here... */ \ -+ do_spidelay(spi, nsecs); \ -+ } while (0) -+ -+#define EXPAND_BITBANG_TXRX -+#include -+#include "spi_bitbang_txrx.h" -+ -+static u32 ap83_spi_txrx_mode0(struct spi_device *spi, -+ unsigned nsecs, u32 word, u8 bits) -+{ -+ dev_dbg(&spi->dev, "TXRX0 word=%08x, bits=%u\n", word, bits); -+ return bitbang_txrx_be_cpha0(spi, nsecs, 0, 0, word, bits); -+} -+ -+static u32 ap83_spi_txrx_mode1(struct spi_device *spi, -+ unsigned nsecs, u32 word, u8 bits) -+{ -+ dev_dbg(&spi->dev, "TXRX1 word=%08x, bits=%u\n", word, bits); -+ return bitbang_txrx_be_cpha1(spi, nsecs, 0, 0, word, bits); -+} -+ -+static u32 ap83_spi_txrx_mode2(struct spi_device *spi, -+ unsigned nsecs, u32 word, u8 bits) -+{ -+ dev_dbg(&spi->dev, "TXRX2 word=%08x, bits=%u\n", word, bits); -+ return bitbang_txrx_be_cpha0(spi, nsecs, 1, 0, word, bits); -+} -+ -+static u32 ap83_spi_txrx_mode3(struct spi_device *spi, -+ unsigned nsecs, u32 word, u8 bits) -+{ -+ dev_dbg(&spi->dev, "TXRX3 word=%08x, bits=%u\n", word, bits); -+ return bitbang_txrx_be_cpha1(spi, nsecs, 1, 0, word, bits); -+} -+ -+static int ap83_spi_probe(struct platform_device *pdev) -+{ -+ struct spi_master *master; -+ struct ap83_spi *sp; -+ struct ap83_spi_platform_data *pdata; -+ struct resource *r; -+ int ret; -+ -+ ret = gpio_request(AP83_SPI_GPIO_MISO, "spi-miso"); -+ if (ret) { -+ dev_err(&pdev->dev, "gpio request failed for MISO\n"); -+ return ret; -+ } -+ -+ ret = gpio_request(AP83_SPI_GPIO_CS, "spi-cs"); -+ if (ret) { -+ dev_err(&pdev->dev, "gpio request failed for CS\n"); -+ goto err_free_miso; -+ } -+ -+ ret = gpio_direction_input(AP83_SPI_GPIO_MISO); -+ if (ret) { -+ dev_err(&pdev->dev, "unable to set direction of MISO\n"); -+ goto err_free_cs; -+ } -+ -+ ret = gpio_direction_output(AP83_SPI_GPIO_CS, 0); -+ if (ret) { -+ dev_err(&pdev->dev, "unable to set direction of CS\n"); -+ goto err_free_cs; -+ } -+ -+ master = spi_alloc_master(&pdev->dev, sizeof(*sp)); -+ if (master == NULL) { -+ dev_err(&pdev->dev, "failed to allocate spi master\n"); -+ return -ENOMEM; -+ } -+ -+ sp = spi_master_get_devdata(master); -+ platform_set_drvdata(pdev, sp); -+ -+ pdata = pdev->dev.platform_data; -+ -+ sp->bitbang.master = spi_master_get(master); -+ sp->bitbang.chipselect = ap83_spi_chipselect; -+ sp->bitbang.txrx_word[SPI_MODE_0] = ap83_spi_txrx_mode0; -+ sp->bitbang.txrx_word[SPI_MODE_1] = ap83_spi_txrx_mode1; -+ sp->bitbang.txrx_word[SPI_MODE_2] = ap83_spi_txrx_mode2; -+ sp->bitbang.txrx_word[SPI_MODE_3] = ap83_spi_txrx_mode3; -+ -+ sp->bitbang.master->bus_num = pdev->id; -+ sp->bitbang.master->num_chipselect = 1; -+ -+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (r == NULL) { -+ ret = -ENOENT; -+ goto err_spi_put; -+ } -+ -+ sp->base = ioremap_nocache(r->start, r->end - r->start + 1); -+ if (!sp->base) { -+ ret = -ENXIO; -+ goto err_spi_put; -+ } -+ -+ ret = spi_bitbang_start(&sp->bitbang); -+ if (!ret) -+ goto err_unmap; -+ -+ dev_info(&pdev->dev, "AP83 SPI adapter at %08x\n", r->start); -+ -+ return 0; -+ -+err_unmap: -+ iounmap(sp->base); -+err_spi_put: -+ platform_set_drvdata(pdev, NULL); -+ spi_master_put(sp->bitbang.master); -+ -+err_free_cs: -+ gpio_free(AP83_SPI_GPIO_CS); -+err_free_miso: -+ gpio_free(AP83_SPI_GPIO_MISO); -+ return ret; -+} -+ -+static int ap83_spi_remove(struct platform_device *pdev) -+{ -+ struct ap83_spi *sp = platform_get_drvdata(pdev); -+ -+ spi_bitbang_stop(&sp->bitbang); -+ iounmap(sp->base); -+ platform_set_drvdata(pdev, NULL); -+ spi_master_put(sp->bitbang.master); -+ -+ return 0; -+} -+ -+static struct platform_driver ap83_spi_drv = { -+ .probe = ap83_spi_probe, -+ .remove = ap83_spi_remove, -+ .driver = { -+ .name = DRV_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init ap83_spi_init(void) -+{ -+ return platform_driver_register(&ap83_spi_drv); -+} -+module_init(ap83_spi_init); -+ -+static void __exit ap83_spi_exit(void) -+{ -+ platform_driver_unregister(&ap83_spi_drv); -+} -+module_exit(ap83_spi_exit); -+ -+MODULE_ALIAS("platform:" DRV_NAME); -+MODULE_DESCRIPTION(DRV_DESC); -+MODULE_VERSION(DRV_VERSION); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_LICENSE("GPL v2"); -diff -Nur linux-2.6.39.orig/drivers/spi/ar71xx_spi.c linux-2.6.39/drivers/spi/ar71xx_spi.c ---- linux-2.6.39.orig/drivers/spi/ar71xx_spi.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/drivers/spi/ar71xx_spi.c 2011-08-24 18:17:24.000000000 +0200 -@@ -0,0 +1,283 @@ -+/* -+ * Atheros AR71xx SPI Controller driver -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#define DRV_DESC "Atheros AR71xx SPI Controller driver" -+#define DRV_VERSION "0.2.4" -+#define DRV_NAME "ar71xx-spi" -+ -+#undef PER_BIT_READ -+ -+struct ar71xx_spi { -+ struct spi_bitbang bitbang; -+ u32 ioc_base; -+ u32 reg_ctrl; -+ -+ void __iomem *base; -+ -+ struct platform_device *pdev; -+ u32 (*get_ioc_base)(u8 chip_select, int cs_high, -+ int is_on); -+}; -+ -+static inline u32 ar71xx_spi_rr(struct ar71xx_spi *sp, unsigned reg) -+{ -+ return __raw_readl(sp->base + reg); -+} -+ -+static inline void ar71xx_spi_wr(struct ar71xx_spi *sp, unsigned reg, u32 val) -+{ -+ __raw_writel(val, sp->base + reg); -+} -+ -+static inline struct ar71xx_spi *spidev_to_sp(struct spi_device *spi) -+{ -+ return spi_master_get_devdata(spi->master); -+} -+ -+static u32 ar71xx_spi_get_ioc_base(u8 chip_select, int cs_high, int is_on) -+{ -+ u32 ret; -+ -+ if (is_on == AR71XX_SPI_CS_INACTIVE) -+ ret = SPI_IOC_CS_ALL; -+ else -+ ret = SPI_IOC_CS_ALL & ~SPI_IOC_CS(chip_select); -+ -+ return ret; -+} -+ -+static void ar71xx_spi_chipselect(struct spi_device *spi, int value) -+{ -+ struct ar71xx_spi *sp = spidev_to_sp(spi); -+ void __iomem *base = sp->base; -+ u32 ioc_base; -+ -+ switch (value) { -+ case BITBANG_CS_INACTIVE: -+ ioc_base = sp->get_ioc_base(spi->chip_select, -+ (spi->mode & SPI_CS_HIGH) != 0, -+ AR71XX_SPI_CS_INACTIVE); -+ __raw_writel(ioc_base, base + SPI_REG_IOC); -+ break; -+ -+ case BITBANG_CS_ACTIVE: -+ ioc_base = sp->get_ioc_base(spi->chip_select, -+ (spi->mode & SPI_CS_HIGH) != 0, -+ AR71XX_SPI_CS_ACTIVE); -+ -+ __raw_writel(ioc_base, base + SPI_REG_IOC); -+ sp->ioc_base = ioc_base; -+ break; -+ } -+} -+ -+static void ar71xx_spi_setup_regs(struct spi_device *spi) -+{ -+ struct ar71xx_spi *sp = spidev_to_sp(spi); -+ -+ /* enable GPIO mode */ -+ ar71xx_spi_wr(sp, SPI_REG_FS, SPI_FS_GPIO); -+ -+ /* save CTRL register */ -+ sp->reg_ctrl = ar71xx_spi_rr(sp, SPI_REG_CTRL); -+ -+ /* TODO: setup speed? */ -+ ar71xx_spi_wr(sp, SPI_REG_CTRL, 0x43); -+} -+ -+static void ar71xx_spi_restore_regs(struct spi_device *spi) -+{ -+ struct ar71xx_spi *sp = spidev_to_sp(spi); -+ -+ /* restore CTRL register */ -+ ar71xx_spi_wr(sp, SPI_REG_CTRL, sp->reg_ctrl); -+ /* disable GPIO mode */ -+ ar71xx_spi_wr(sp, SPI_REG_FS, 0); -+} -+ -+static int ar71xx_spi_setup(struct spi_device *spi) -+{ -+ int status; -+ -+ if (spi->bits_per_word > 32) -+ return -EINVAL; -+ -+ if (!spi->controller_state) -+ ar71xx_spi_setup_regs(spi); -+ -+ status = spi_bitbang_setup(spi); -+ if (status && !spi->controller_state) -+ ar71xx_spi_restore_regs(spi); -+ -+ return status; -+} -+ -+static void ar71xx_spi_cleanup(struct spi_device *spi) -+{ -+ ar71xx_spi_restore_regs(spi); -+ spi_bitbang_cleanup(spi); -+} -+ -+static u32 ar71xx_spi_txrx_mode0(struct spi_device *spi, unsigned nsecs, -+ u32 word, u8 bits) -+{ -+ struct ar71xx_spi *sp = spidev_to_sp(spi); -+ void __iomem *base = sp->base; -+ u32 ioc = sp->ioc_base; -+ u32 ret; -+ -+ /* clock starts at inactive polarity */ -+ for (word <<= (32 - bits); likely(bits); bits--) { -+ u32 out; -+ -+ if (word & (1 << 31)) -+ out = ioc | SPI_IOC_DO; -+ else -+ out = ioc & ~SPI_IOC_DO; -+ -+ /* setup MSB (to slave) on trailing edge */ -+ __raw_writel(out, base + SPI_REG_IOC); -+ -+ __raw_writel(out | SPI_IOC_CLK, base + SPI_REG_IOC); -+ -+ word <<= 1; -+ -+#ifdef PER_BIT_READ -+ /* sample MSB (from slave) on leading edge */ -+ ret = __raw_readl(base + SPI_REG_RDS); -+ __raw_writel(out, base + SPI_REG_IOC); -+#endif -+ -+ } -+ -+#ifndef PER_BIT_READ -+ ret = __raw_readl(base + SPI_REG_RDS); -+#endif -+ return ret; -+} -+ -+static int ar71xx_spi_probe(struct platform_device *pdev) -+{ -+ struct spi_master *master; -+ struct ar71xx_spi *sp; -+ struct ar71xx_spi_platform_data *pdata; -+ struct resource *r; -+ int ret; -+ -+ master = spi_alloc_master(&pdev->dev, sizeof(*sp)); -+ if (master == NULL) { -+ dev_err(&pdev->dev, "failed to allocate spi master\n"); -+ return -ENOMEM; -+ } -+ -+ sp = spi_master_get_devdata(master); -+ platform_set_drvdata(pdev, sp); -+ -+ pdata = pdev->dev.platform_data; -+ -+ master->setup = ar71xx_spi_setup; -+ master->cleanup = ar71xx_spi_cleanup; -+ -+ sp->bitbang.master = spi_master_get(master); -+ sp->bitbang.chipselect = ar71xx_spi_chipselect; -+ sp->bitbang.txrx_word[SPI_MODE_0] = ar71xx_spi_txrx_mode0; -+ sp->bitbang.setup_transfer = spi_bitbang_setup_transfer; -+ -+ sp->get_ioc_base = ar71xx_spi_get_ioc_base; -+ if (pdata) { -+ sp->bitbang.master->bus_num = pdata->bus_num; -+ sp->bitbang.master->num_chipselect = pdata->num_chipselect; -+ if (pdata->get_ioc_base) -+ sp->get_ioc_base = pdata->get_ioc_base; -+ } else { -+ sp->bitbang.master->bus_num = 0; -+ sp->bitbang.master->num_chipselect = 3; -+ } -+ -+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (r == NULL) { -+ ret = -ENOENT; -+ goto err1; -+ } -+ -+ sp->base = ioremap_nocache(r->start, r->end - r->start + 1); -+ if (!sp->base) { -+ ret = -ENXIO; -+ goto err1; -+ } -+ -+ ret = spi_bitbang_start(&sp->bitbang); -+ if (!ret) -+ return 0; -+ -+ iounmap(sp->base); -+err1: -+ platform_set_drvdata(pdev, NULL); -+ spi_master_put(sp->bitbang.master); -+ -+ return ret; -+} -+ -+static int ar71xx_spi_remove(struct platform_device *pdev) -+{ -+ struct ar71xx_spi *sp = platform_get_drvdata(pdev); -+ -+ spi_bitbang_stop(&sp->bitbang); -+ iounmap(sp->base); -+ platform_set_drvdata(pdev, NULL); -+ spi_master_put(sp->bitbang.master); -+ -+ return 0; -+} -+ -+static struct platform_driver ar71xx_spi_drv = { -+ .probe = ar71xx_spi_probe, -+ .remove = ar71xx_spi_remove, -+ .driver = { -+ .name = DRV_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init ar71xx_spi_init(void) -+{ -+ printk(KERN_INFO DRV_DESC " version " DRV_VERSION "\n"); -+ return platform_driver_register(&ar71xx_spi_drv); -+} -+module_init(ar71xx_spi_init); -+ -+static void __exit ar71xx_spi_exit(void) -+{ -+ platform_driver_unregister(&ar71xx_spi_drv); -+} -+module_exit(ar71xx_spi_exit); -+ -+MODULE_ALIAS("platform:" DRV_NAME); -+MODULE_DESCRIPTION(DRV_DESC); -+MODULE_VERSION(DRV_VERSION); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_AUTHOR("Imre Kaloz "); -+MODULE_LICENSE("GPL v2"); -diff -Nur linux-2.6.39.orig/drivers/spi/pb44_spi.c linux-2.6.39/drivers/spi/pb44_spi.c ---- linux-2.6.39.orig/drivers/spi/pb44_spi.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/drivers/spi/pb44_spi.c 2011-08-24 18:17:24.000000000 +0200 -@@ -0,0 +1,299 @@ -+/* -+ * Atheros PB44 board SPI controller driver -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#define DRV_DESC "Atheros PB44 SPI Controller driver" -+#define DRV_VERSION "0.1.0" -+#define DRV_NAME "pb44-spi" -+ -+#undef PER_BIT_READ -+ -+struct ar71xx_spi { -+ struct spi_bitbang bitbang; -+ u32 ioc_base; -+ u32 reg_ctrl; -+ -+ void __iomem *base; -+ -+ struct platform_device *pdev; -+}; -+ -+static inline u32 pb44_spi_rr(struct ar71xx_spi *sp, unsigned reg) -+{ -+ return __raw_readl(sp->base + reg); -+} -+ -+static inline void pb44_spi_wr(struct ar71xx_spi *sp, unsigned reg, u32 val) -+{ -+ __raw_writel(val, sp->base + reg); -+} -+ -+static inline struct ar71xx_spi *spidev_to_sp(struct spi_device *spi) -+{ -+ return spi_master_get_devdata(spi->master); -+} -+ -+static void pb44_spi_chipselect(struct spi_device *spi, int is_active) -+{ -+ struct ar71xx_spi *sp = spidev_to_sp(spi); -+ int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active; -+ -+ if (is_active) { -+ /* set initial clock polarity */ -+ if (spi->mode & SPI_CPOL) -+ sp->ioc_base |= SPI_IOC_CLK; -+ else -+ sp->ioc_base &= ~SPI_IOC_CLK; -+ -+ pb44_spi_wr(sp, SPI_REG_IOC, sp->ioc_base); -+ } -+ -+ if (spi->chip_select) { -+ unsigned long gpio = (unsigned long) spi->controller_data; -+ -+ /* SPI is normally active-low */ -+ gpio_set_value(gpio, cs_high); -+ } else { -+ if (cs_high) -+ sp->ioc_base |= SPI_IOC_CS0; -+ else -+ sp->ioc_base &= ~SPI_IOC_CS0; -+ -+ pb44_spi_wr(sp, SPI_REG_IOC, sp->ioc_base); -+ } -+ -+} -+ -+static int pb44_spi_setup_cs(struct spi_device *spi) -+{ -+ struct ar71xx_spi *sp = spidev_to_sp(spi); -+ -+ /* enable GPIO mode */ -+ pb44_spi_wr(sp, SPI_REG_FS, SPI_FS_GPIO); -+ -+ /* save CTRL register */ -+ sp->reg_ctrl = pb44_spi_rr(sp, SPI_REG_CTRL); -+ sp->ioc_base = pb44_spi_rr(sp, SPI_REG_IOC); -+ -+ /* TODO: setup speed? */ -+ pb44_spi_wr(sp, SPI_REG_CTRL, 0x43); -+ -+ if (spi->chip_select) { -+ unsigned long gpio = (unsigned long) spi->controller_data; -+ int status = 0; -+ -+ status = gpio_request(gpio, dev_name(&spi->dev)); -+ if (status) -+ return status; -+ -+ status = gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH); -+ if (status) { -+ gpio_free(gpio); -+ return status; -+ } -+ } else { -+ if (spi->mode & SPI_CS_HIGH) -+ sp->ioc_base |= SPI_IOC_CS0; -+ else -+ sp->ioc_base &= ~SPI_IOC_CS0; -+ pb44_spi_wr(sp, SPI_REG_IOC, sp->ioc_base); -+ } -+ -+ return 0; -+} -+ -+static void pb44_spi_cleanup_cs(struct spi_device *spi) -+{ -+ struct ar71xx_spi *sp = spidev_to_sp(spi); -+ -+ if (spi->chip_select) { -+ unsigned long gpio = (unsigned long) spi->controller_data; -+ gpio_free(gpio); -+ } -+ -+ /* restore CTRL register */ -+ pb44_spi_wr(sp, SPI_REG_CTRL, sp->reg_ctrl); -+ /* disable GPIO mode */ -+ pb44_spi_wr(sp, SPI_REG_FS, 0); -+} -+ -+static int pb44_spi_setup(struct spi_device *spi) -+{ -+ int status = 0; -+ -+ if (spi->bits_per_word > 32) -+ return -EINVAL; -+ -+ if (!spi->controller_state) { -+ status = pb44_spi_setup_cs(spi); -+ if (status) -+ return status; -+ } -+ -+ status = spi_bitbang_setup(spi); -+ if (status && !spi->controller_state) -+ pb44_spi_cleanup_cs(spi); -+ -+ return status; -+} -+ -+static void pb44_spi_cleanup(struct spi_device *spi) -+{ -+ pb44_spi_cleanup_cs(spi); -+ spi_bitbang_cleanup(spi); -+} -+ -+static u32 pb44_spi_txrx_mode0(struct spi_device *spi, unsigned nsecs, -+ u32 word, u8 bits) -+{ -+ struct ar71xx_spi *sp = spidev_to_sp(spi); -+ u32 ioc = sp->ioc_base; -+ u32 ret; -+ -+ /* clock starts at inactive polarity */ -+ for (word <<= (32 - bits); likely(bits); bits--) { -+ u32 out; -+ -+ if (word & (1 << 31)) -+ out = ioc | SPI_IOC_DO; -+ else -+ out = ioc & ~SPI_IOC_DO; -+ -+ /* setup MSB (to slave) on trailing edge */ -+ pb44_spi_wr(sp, SPI_REG_IOC, out); -+ pb44_spi_wr(sp, SPI_REG_IOC, out | SPI_IOC_CLK); -+ -+ word <<= 1; -+ -+#ifdef PER_BIT_READ -+ /* sample MSB (from slave) on leading edge */ -+ ret = pb44_spi_rr(sp, SPI_REG_RDS); -+ pb44_spi_wr(sp, SPI_REG_IOC, out); -+#endif -+ } -+ -+#ifndef PER_BIT_READ -+ ret = pb44_spi_rr(sp, SPI_REG_RDS); -+#endif -+ return ret; -+} -+ -+static int pb44_spi_probe(struct platform_device *pdev) -+{ -+ struct spi_master *master; -+ struct ar71xx_spi *sp; -+ struct ar71xx_spi_platform_data *pdata; -+ struct resource *r; -+ int ret; -+ -+ master = spi_alloc_master(&pdev->dev, sizeof(*sp)); -+ if (master == NULL) { -+ dev_err(&pdev->dev, "failed to allocate spi master\n"); -+ return -ENOMEM; -+ } -+ -+ sp = spi_master_get_devdata(master); -+ platform_set_drvdata(pdev, sp); -+ -+ pdata = pdev->dev.platform_data; -+ -+ master->setup = pb44_spi_setup; -+ master->cleanup = pb44_spi_cleanup; -+ if (pdata) { -+ master->bus_num = pdata->bus_num; -+ master->num_chipselect = pdata->num_chipselect; -+ } else { -+ master->bus_num = 0; -+ master->num_chipselect = 1; -+ } -+ -+ sp->bitbang.master = spi_master_get(master); -+ sp->bitbang.chipselect = pb44_spi_chipselect; -+ sp->bitbang.txrx_word[SPI_MODE_0] = pb44_spi_txrx_mode0; -+ sp->bitbang.setup_transfer = spi_bitbang_setup_transfer; -+ sp->bitbang.flags = SPI_CS_HIGH; -+ -+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (r == NULL) { -+ ret = -ENOENT; -+ goto err1; -+ } -+ -+ sp->base = ioremap_nocache(r->start, r->end - r->start + 1); -+ if (!sp->base) { -+ ret = -ENXIO; -+ goto err1; -+ } -+ -+ ret = spi_bitbang_start(&sp->bitbang); -+ if (!ret) -+ return 0; -+ -+ iounmap(sp->base); -+err1: -+ platform_set_drvdata(pdev, NULL); -+ spi_master_put(sp->bitbang.master); -+ -+ return ret; -+} -+ -+static int pb44_spi_remove(struct platform_device *pdev) -+{ -+ struct ar71xx_spi *sp = platform_get_drvdata(pdev); -+ -+ spi_bitbang_stop(&sp->bitbang); -+ iounmap(sp->base); -+ platform_set_drvdata(pdev, NULL); -+ spi_master_put(sp->bitbang.master); -+ -+ return 0; -+} -+ -+static struct platform_driver pb44_spi_drv = { -+ .probe = pb44_spi_probe, -+ .remove = pb44_spi_remove, -+ .driver = { -+ .name = DRV_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init pb44_spi_init(void) -+{ -+ return platform_driver_register(&pb44_spi_drv); -+} -+module_init(pb44_spi_init); -+ -+static void __exit pb44_spi_exit(void) -+{ -+ platform_driver_unregister(&pb44_spi_drv); -+} -+module_exit(pb44_spi_exit); -+ -+MODULE_ALIAS("platform:" DRV_NAME); -+MODULE_DESCRIPTION(DRV_DESC); -+MODULE_VERSION(DRV_VERSION); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_LICENSE("GPL v2"); -diff -Nur linux-2.6.39.orig/drivers/spi/rb4xx_spi.c linux-2.6.39/drivers/spi/rb4xx_spi.c ---- linux-2.6.39.orig/drivers/spi/rb4xx_spi.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/drivers/spi/rb4xx_spi.c 2011-08-24 18:17:24.000000000 +0200 -@@ -0,0 +1,474 @@ -+/* -+ * SPI controller driver for the Mikrotik RB4xx boards -+ * -+ * Copyright (C) 2010 Gabor Juhos -+ * -+ * This file was based on the patches for Linux 2.6.27.39 published by -+ * MikroTik for their RouterBoard 4xx series devices. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#define DRV_NAME "rb4xx-spi" -+#define DRV_DESC "Mikrotik RB4xx SPI controller driver" -+#define DRV_VERSION "0.1.0" -+ -+#define SPI_CTRL_FASTEST 0x40 -+#define SPI_FLASH_HZ 33333334 -+#define SPI_CPLD_HZ 33333334 -+ -+#define CPLD_CMD_READ_FAST 0x0b -+ -+#undef RB4XX_SPI_DEBUG -+ -+struct rb4xx_spi { -+ void __iomem *base; -+ struct spi_master *master; -+ -+ unsigned spi_ctrl_flash; -+ unsigned spi_ctrl_fread; -+ -+ spinlock_t lock; -+ struct list_head queue; -+ int busy:1; -+ int cs_wait; -+}; -+ -+static unsigned spi_clk_low = SPI_IOC_CS1; -+ -+#ifdef RB4XX_SPI_DEBUG -+static inline void do_spi_delay(void) -+{ -+ ndelay(20000); -+} -+#else -+static inline void do_spi_delay(void) { } -+#endif -+ -+static inline void do_spi_init(struct spi_device *spi) -+{ -+ unsigned cs = SPI_IOC_CS0 | SPI_IOC_CS1; -+ -+ if (!(spi->mode & SPI_CS_HIGH)) -+ cs ^= (spi->chip_select == 2) ? SPI_IOC_CS1 : SPI_IOC_CS0; -+ -+ spi_clk_low = cs; -+} -+ -+static inline void do_spi_finish(void __iomem *base) -+{ -+ do_spi_delay(); -+ __raw_writel(SPI_IOC_CS0 | SPI_IOC_CS1, base + SPI_REG_IOC); -+} -+ -+static inline void do_spi_clk(void __iomem *base, int bit) -+{ -+ unsigned bval = spi_clk_low | ((bit & 1) ? SPI_IOC_DO : 0); -+ -+ do_spi_delay(); -+ __raw_writel(bval, base + SPI_REG_IOC); -+ do_spi_delay(); -+ __raw_writel(bval | SPI_IOC_CLK, base + SPI_REG_IOC); -+} -+ -+static void do_spi_byte(void __iomem *base, unsigned char byte) -+{ -+ do_spi_clk(base, byte >> 7); -+ do_spi_clk(base, byte >> 6); -+ do_spi_clk(base, byte >> 5); -+ do_spi_clk(base, byte >> 4); -+ do_spi_clk(base, byte >> 3); -+ do_spi_clk(base, byte >> 2); -+ do_spi_clk(base, byte >> 1); -+ do_spi_clk(base, byte); -+ -+ pr_debug("spi_byte sent 0x%02x got 0x%02x\n", -+ (unsigned)byte, -+ (unsigned char)__raw_readl(base + SPI_REG_RDS)); -+} -+ -+static inline void do_spi_clk_fast(void __iomem *base, unsigned bit1, -+ unsigned bit2) -+{ -+ unsigned bval = (spi_clk_low | -+ ((bit1 & 1) ? SPI_IOC_DO : 0) | -+ ((bit2 & 1) ? SPI_IOC_CS2 : 0)); -+ do_spi_delay(); -+ __raw_writel(bval, base + SPI_REG_IOC); -+ do_spi_delay(); -+ __raw_writel(bval | SPI_IOC_CLK, base + SPI_REG_IOC); -+} -+ -+static void do_spi_byte_fast(void __iomem *base, unsigned char byte) -+{ -+ do_spi_clk_fast(base, byte >> 7, byte >> 6); -+ do_spi_clk_fast(base, byte >> 5, byte >> 4); -+ do_spi_clk_fast(base, byte >> 3, byte >> 2); -+ do_spi_clk_fast(base, byte >> 1, byte >> 0); -+ -+ pr_debug("spi_byte_fast sent 0x%02x got 0x%02x\n", -+ (unsigned)byte, -+ (unsigned char) __raw_readl(base + SPI_REG_RDS)); -+} -+ -+static int rb4xx_spi_txrx(void __iomem *base, struct spi_transfer *t) -+{ -+ const unsigned char *rxv_ptr = NULL; -+ const unsigned char *tx_ptr = t->tx_buf; -+ unsigned char *rx_ptr = t->rx_buf; -+ unsigned i; -+ -+ pr_debug("spi_txrx len %u tx %u rx %u\n", -+ t->len, -+ (t->tx_buf ? 1 : 0), -+ (t->rx_buf ? 1 : 0)); -+ -+ if (t->verify) { -+ rxv_ptr = tx_ptr; -+ tx_ptr = NULL; -+ } -+ -+ for (i = 0; i < t->len; ++i) { -+ unsigned char sdata = tx_ptr ? tx_ptr[i] : 0; -+ -+ if (t->fast_write) -+ do_spi_byte_fast(base, sdata); -+ else -+ do_spi_byte(base, sdata); -+ -+ if (rx_ptr) { -+ rx_ptr[i] = __raw_readl(base + SPI_REG_RDS) & 0xff; -+ } else if (rxv_ptr) { -+ unsigned char c = __raw_readl(base + SPI_REG_RDS); -+ if (rxv_ptr[i] != c) -+ return i; -+ } -+ } -+ -+ return i; -+} -+ -+static int rb4xx_spi_read_fast(struct rb4xx_spi *rbspi, -+ struct spi_message *m) -+{ -+ struct spi_transfer *t; -+ const unsigned char *tx_ptr; -+ unsigned addr; -+ void __iomem *base = rbspi->base; -+ -+ /* check for exactly two transfers */ -+ if (list_empty(&m->transfers) || -+ list_is_last(m->transfers.next, &m->transfers) || -+ !list_is_last(m->transfers.next->next, &m->transfers)) { -+ return -1; -+ } -+ -+ /* first transfer contains command and address */ -+ t = list_entry(m->transfers.next, -+ struct spi_transfer, transfer_list); -+ -+ if (t->len != 5 || t->tx_buf == NULL) -+ return -1; -+ -+ tx_ptr = t->tx_buf; -+ if (tx_ptr[0] != CPLD_CMD_READ_FAST) -+ return -1; -+ -+ addr = tx_ptr[1]; -+ addr = tx_ptr[2] | (addr << 8); -+ addr = tx_ptr[3] | (addr << 8); -+ addr += (unsigned) base; -+ -+ m->actual_length += t->len; -+ -+ /* second transfer contains data itself */ -+ t = list_entry(m->transfers.next->next, -+ struct spi_transfer, transfer_list); -+ -+ if (t->tx_buf && !t->verify) -+ return -1; -+ -+ __raw_writel(SPI_FS_GPIO, base + SPI_REG_FS); -+ __raw_writel(rbspi->spi_ctrl_fread, base + SPI_REG_CTRL); -+ __raw_writel(0, base + SPI_REG_FS); -+ -+ if (t->rx_buf) { -+ memcpy(t->rx_buf, (const void *)addr, t->len); -+ } else if (t->tx_buf) { -+ unsigned char buf[t->len]; -+ memcpy(buf, (const void *)addr, t->len); -+ if (memcmp(t->tx_buf, buf, t->len) != 0) -+ m->status = -EMSGSIZE; -+ } -+ m->actual_length += t->len; -+ -+ if (rbspi->spi_ctrl_flash != rbspi->spi_ctrl_fread) { -+ __raw_writel(SPI_FS_GPIO, base + SPI_REG_FS); -+ __raw_writel(rbspi->spi_ctrl_flash, base + SPI_REG_CTRL); -+ __raw_writel(0, base + SPI_REG_FS); -+ } -+ -+ return 0; -+} -+ -+static int rb4xx_spi_msg(struct rb4xx_spi *rbspi, struct spi_message *m) -+{ -+ struct spi_transfer *t = NULL; -+ void __iomem *base = rbspi->base; -+ -+ m->status = 0; -+ if (list_empty(&m->transfers)) -+ return -1; -+ -+ if (m->fast_read) -+ if (rb4xx_spi_read_fast(rbspi, m) == 0) -+ return -1; -+ -+ __raw_writel(SPI_FS_GPIO, base + SPI_REG_FS); -+ __raw_writel(SPI_CTRL_FASTEST, base + SPI_REG_CTRL); -+ do_spi_init(m->spi); -+ -+ list_for_each_entry(t, &m->transfers, transfer_list) { -+ int len; -+ -+ len = rb4xx_spi_txrx(base, t); -+ if (len != t->len) { -+ m->status = -EMSGSIZE; -+ break; -+ } -+ m->actual_length += len; -+ -+ if (t->cs_change) { -+ if (list_is_last(&t->transfer_list, &m->transfers)) { -+ /* wait for continuation */ -+ return m->spi->chip_select; -+ } -+ do_spi_finish(base); -+ ndelay(100); -+ } -+ } -+ -+ do_spi_finish(base); -+ __raw_writel(rbspi->spi_ctrl_flash, base + SPI_REG_CTRL); -+ __raw_writel(0, base + SPI_REG_FS); -+ return -1; -+} -+ -+static void rb4xx_spi_process_queue_locked(struct rb4xx_spi *rbspi, -+ unsigned long *flags) -+{ -+ int cs = rbspi->cs_wait; -+ -+ rbspi->busy = 1; -+ while (!list_empty(&rbspi->queue)) { -+ struct spi_message *m; -+ -+ list_for_each_entry(m, &rbspi->queue, queue) -+ if (cs < 0 || cs == m->spi->chip_select) -+ break; -+ -+ if (&m->queue == &rbspi->queue) -+ break; -+ -+ list_del_init(&m->queue); -+ spin_unlock_irqrestore(&rbspi->lock, *flags); -+ -+ cs = rb4xx_spi_msg(rbspi, m); -+ m->complete(m->context); -+ -+ spin_lock_irqsave(&rbspi->lock, *flags); -+ } -+ -+ rbspi->cs_wait = cs; -+ rbspi->busy = 0; -+ -+ if (cs >= 0) { -+ /* TODO: add timer to unlock cs after 1s inactivity */ -+ } -+} -+ -+static int rb4xx_spi_transfer(struct spi_device *spi, -+ struct spi_message *m) -+{ -+ struct rb4xx_spi *rbspi = spi_master_get_devdata(spi->master); -+ unsigned long flags; -+ -+ m->actual_length = 0; -+ m->status = -EINPROGRESS; -+ -+ spin_lock_irqsave(&rbspi->lock, flags); -+ list_add_tail(&m->queue, &rbspi->queue); -+ if (rbspi->busy || -+ (rbspi->cs_wait >= 0 && rbspi->cs_wait != m->spi->chip_select)) { -+ /* job will be done later */ -+ spin_unlock_irqrestore(&rbspi->lock, flags); -+ return 0; -+ } -+ -+ /* process job in current context */ -+ rb4xx_spi_process_queue_locked(rbspi, &flags); -+ spin_unlock_irqrestore(&rbspi->lock, flags); -+ -+ return 0; -+} -+ -+static int rb4xx_spi_setup(struct spi_device *spi) -+{ -+ struct rb4xx_spi *rbspi = spi_master_get_devdata(spi->master); -+ unsigned long flags; -+ -+ if (spi->mode & ~(SPI_CS_HIGH)) { -+ dev_err(&spi->dev, "mode %x not supported\n", -+ (unsigned) spi->mode); -+ return -EINVAL; -+ } -+ -+ if (spi->bits_per_word != 8 && spi->bits_per_word != 0) { -+ dev_err(&spi->dev, "bits_per_word %u not supported\n", -+ (unsigned) spi->bits_per_word); -+ return -EINVAL; -+ } -+ -+ spin_lock_irqsave(&rbspi->lock, flags); -+ if (rbspi->cs_wait == spi->chip_select && !rbspi->busy) { -+ rbspi->cs_wait = -1; -+ rb4xx_spi_process_queue_locked(rbspi, &flags); -+ } -+ spin_unlock_irqrestore(&rbspi->lock, flags); -+ -+ return 0; -+} -+ -+static unsigned get_spi_ctrl(unsigned hz_max, const char *name) -+{ -+ unsigned div; -+ -+ div = (ar71xx_ahb_freq - 1) / (2 * hz_max); -+ -+ /* -+ * CPU has a bug at (div == 0) - first bit read is random -+ */ -+ if (div == 0) -+ ++div; -+ -+ if (name) { -+ unsigned ahb_khz = (ar71xx_ahb_freq + 500) / 1000; -+ unsigned div_real = 2 * (div + 1); -+ pr_debug("rb4xx: %s SPI clock %u kHz (AHB %u kHz / %u)\n", -+ name, -+ ahb_khz / div_real, -+ ahb_khz, div_real); -+ } -+ -+ return SPI_CTRL_FASTEST + div; -+} -+ -+static int rb4xx_spi_probe(struct platform_device *pdev) -+{ -+ struct spi_master *master; -+ struct rb4xx_spi *rbspi; -+ struct resource *r; -+ int err = 0; -+ -+ master = spi_alloc_master(&pdev->dev, sizeof(*rbspi)); -+ if (master == NULL) { -+ dev_err(&pdev->dev, "no memory for spi_master\n"); -+ err = -ENOMEM; -+ goto err_out; -+ } -+ -+ master->bus_num = 0; -+ master->num_chipselect = 3; -+ master->setup = rb4xx_spi_setup; -+ master->transfer = rb4xx_spi_transfer; -+ -+ rbspi = spi_master_get_devdata(master); -+ platform_set_drvdata(pdev, rbspi); -+ -+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (r == NULL) { -+ err = -ENOENT; -+ goto err_put_master; -+ } -+ -+ rbspi->base = ioremap(r->start, r->end - r->start + 1); -+ if (!rbspi->base) { -+ err = -ENXIO; -+ goto err_put_master; -+ } -+ -+ rbspi->master = master; -+ rbspi->spi_ctrl_flash = get_spi_ctrl(SPI_FLASH_HZ, "FLASH"); -+ rbspi->spi_ctrl_fread = get_spi_ctrl(SPI_CPLD_HZ, "CPLD"); -+ rbspi->cs_wait = -1; -+ -+ spin_lock_init(&rbspi->lock); -+ INIT_LIST_HEAD(&rbspi->queue); -+ -+ err = spi_register_master(master); -+ if (err) { -+ dev_err(&pdev->dev, "failed to register SPI master\n"); -+ goto err_iounmap; -+ } -+ -+ return 0; -+ -+err_iounmap: -+ iounmap(rbspi->base); -+err_put_master: -+ platform_set_drvdata(pdev, NULL); -+ spi_master_put(master); -+err_out: -+ return err; -+} -+ -+static int rb4xx_spi_remove(struct platform_device *pdev) -+{ -+ struct rb4xx_spi *rbspi = platform_get_drvdata(pdev); -+ -+ iounmap(rbspi->base); -+ platform_set_drvdata(pdev, NULL); -+ spi_master_put(rbspi->master); -+ -+ return 0; -+} -+ -+static struct platform_driver rb4xx_spi_drv = { -+ .probe = rb4xx_spi_probe, -+ .remove = rb4xx_spi_remove, -+ .driver = { -+ .name = DRV_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init rb4xx_spi_init(void) -+{ -+ return platform_driver_register(&rb4xx_spi_drv); -+} -+subsys_initcall(rb4xx_spi_init); -+ -+static void __exit rb4xx_spi_exit(void) -+{ -+ platform_driver_unregister(&rb4xx_spi_drv); -+} -+ -+module_exit(rb4xx_spi_exit); -+ -+MODULE_DESCRIPTION(DRV_DESC); -+MODULE_VERSION(DRV_VERSION); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_LICENSE("GPL v2"); -diff -Nur linux-2.6.39.orig/drivers/spi/spi_rb4xx_cpld.c linux-2.6.39/drivers/spi/spi_rb4xx_cpld.c ---- linux-2.6.39.orig/drivers/spi/spi_rb4xx_cpld.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/drivers/spi/spi_rb4xx_cpld.c 2011-08-24 18:17:24.000000000 +0200 -@@ -0,0 +1,440 @@ -+/* -+ * SPI driver for the CPLD chip on the Mikrotik RB4xx boards -+ * -+ * Copyright (C) 2010 Gabor Juhos -+ * -+ * This file was based on the patches for Linux 2.6.27.39 published by -+ * MikroTik for their RouterBoard 4xx series devices. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#define DRV_NAME "spi-rb4xx-cpld" -+#define DRV_DESC "RB4xx CPLD driver" -+#define DRV_VERSION "0.1.0" -+ -+#define CPLD_CMD_WRITE_NAND 0x08 /* send cmd, n x send data, send indle */ -+#define CPLD_CMD_WRITE_CFG 0x09 /* send cmd, n x send cfg */ -+#define CPLD_CMD_READ_NAND 0x0a /* send cmd, send idle, n x read data */ -+#define CPLD_CMD_READ_FAST 0x0b /* send cmd, 4 x idle, n x read data */ -+#define CPLD_CMD_LED5_ON 0x0c /* send cmd */ -+#define CPLD_CMD_LED5_OFF 0x0d /* send cmd */ -+ -+struct rb4xx_cpld { -+ struct spi_device *spi; -+ struct mutex lock; -+ struct gpio_chip chip; -+ unsigned int config; -+}; -+ -+static struct rb4xx_cpld *rb4xx_cpld; -+ -+static inline struct rb4xx_cpld *gpio_to_cpld(struct gpio_chip *chip) -+{ -+ return container_of(chip, struct rb4xx_cpld, chip); -+} -+ -+static int rb4xx_cpld_write_cmd(struct rb4xx_cpld *cpld, unsigned char cmd) -+{ -+ struct spi_transfer t[1]; -+ struct spi_message m; -+ unsigned char tx_buf[1]; -+ int err; -+ -+ spi_message_init(&m); -+ memset(&t, 0, sizeof(t)); -+ -+ t[0].tx_buf = tx_buf; -+ t[0].len = sizeof(tx_buf); -+ spi_message_add_tail(&t[0], &m); -+ -+ tx_buf[0] = cmd; -+ -+ err = spi_sync(cpld->spi, &m); -+ return err; -+} -+ -+static int rb4xx_cpld_write_cfg(struct rb4xx_cpld *cpld, unsigned char config) -+{ -+ struct spi_transfer t[1]; -+ struct spi_message m; -+ unsigned char cmd[2]; -+ int err; -+ -+ spi_message_init(&m); -+ memset(&t, 0, sizeof(t)); -+ -+ t[0].tx_buf = cmd; -+ t[0].len = sizeof(cmd); -+ spi_message_add_tail(&t[0], &m); -+ -+ cmd[0] = CPLD_CMD_WRITE_CFG; -+ cmd[1] = config; -+ -+ err = spi_sync(cpld->spi, &m); -+ return err; -+} -+ -+static int __rb4xx_cpld_change_cfg(struct rb4xx_cpld *cpld, unsigned mask, -+ unsigned value) -+{ -+ unsigned int config; -+ int err; -+ -+ config = cpld->config & ~mask; -+ config |= value; -+ -+ if ((cpld->config ^ config) & 0xff) { -+ err = rb4xx_cpld_write_cfg(cpld, config); -+ if (err) -+ return err; -+ } -+ -+ if ((cpld->config ^ config) & CPLD_CFG_nLED5) { -+ err = rb4xx_cpld_write_cmd(cpld, (value) ? CPLD_CMD_LED5_ON : -+ CPLD_CMD_LED5_OFF); -+ if (err) -+ return err; -+ } -+ -+ cpld->config = config; -+ return 0; -+} -+ -+int rb4xx_cpld_change_cfg(unsigned mask, unsigned value) -+{ -+ int ret; -+ -+ if (rb4xx_cpld == NULL) -+ return -ENODEV; -+ -+ mutex_lock(&rb4xx_cpld->lock); -+ ret = __rb4xx_cpld_change_cfg(rb4xx_cpld, mask, value); -+ mutex_unlock(&rb4xx_cpld->lock); -+ -+ return ret; -+} -+EXPORT_SYMBOL_GPL(rb4xx_cpld_change_cfg); -+ -+int rb4xx_cpld_read_from(unsigned addr, unsigned char *rx_buf, -+ const unsigned char *verify_buf, unsigned count) -+{ -+ const unsigned char cmd[5] = { -+ CPLD_CMD_READ_FAST, -+ (addr >> 16) & 0xff, -+ (addr >> 8) & 0xff, -+ addr & 0xff, -+ 0 -+ }; -+ struct spi_transfer t[2] = { -+ { -+ .tx_buf = &cmd, -+ .len = 5, -+ }, -+ { -+ .tx_buf = verify_buf, -+ .rx_buf = rx_buf, -+ .len = count, -+ .verify = (verify_buf != NULL), -+ }, -+ }; -+ struct spi_message m; -+ -+ if (rb4xx_cpld == NULL) -+ return -ENODEV; -+ -+ spi_message_init(&m); -+ m.fast_read = 1; -+ spi_message_add_tail(&t[0], &m); -+ spi_message_add_tail(&t[1], &m); -+ return spi_sync(rb4xx_cpld->spi, &m); -+} -+EXPORT_SYMBOL_GPL(rb4xx_cpld_read_from); -+ -+#if 0 -+int rb4xx_cpld_read(unsigned char *buf, unsigned char *verify_buf, -+ unsigned count) -+{ -+ struct spi_transfer t[2]; -+ struct spi_message m; -+ unsigned char cmd[2]; -+ -+ if (rb4xx_cpld == NULL) -+ return -ENODEV; -+ -+ spi_message_init(&m); -+ memset(&t, 0, sizeof(t)); -+ -+ /* send command */ -+ t[0].tx_buf = cmd; -+ t[0].len = sizeof(cmd); -+ spi_message_add_tail(&t[0], &m); -+ -+ cmd[0] = CPLD_CMD_READ_NAND; -+ cmd[1] = 0; -+ -+ /* read data */ -+ t[1].rx_buf = buf; -+ t[1].len = count; -+ spi_message_add_tail(&t[1], &m); -+ -+ return spi_sync(rb4xx_cpld->spi, &m); -+} -+#else -+int rb4xx_cpld_read(unsigned char *rx_buf, const unsigned char *verify_buf, -+ unsigned count) -+{ -+ static const unsigned char cmd[2] = { CPLD_CMD_READ_NAND, 0 }; -+ struct spi_transfer t[2] = { -+ { -+ .tx_buf = &cmd, -+ .len = 2, -+ }, { -+ .tx_buf = verify_buf, -+ .rx_buf = rx_buf, -+ .len = count, -+ .verify = (verify_buf != NULL), -+ }, -+ }; -+ struct spi_message m; -+ -+ if (rb4xx_cpld == NULL) -+ return -ENODEV; -+ -+ spi_message_init(&m); -+ spi_message_add_tail(&t[0], &m); -+ spi_message_add_tail(&t[1], &m); -+ return spi_sync(rb4xx_cpld->spi, &m); -+} -+#endif -+EXPORT_SYMBOL_GPL(rb4xx_cpld_read); -+ -+int rb4xx_cpld_write(const unsigned char *buf, unsigned count) -+{ -+#if 0 -+ struct spi_transfer t[3]; -+ struct spi_message m; -+ unsigned char cmd[1]; -+ -+ if (rb4xx_cpld == NULL) -+ return -ENODEV; -+ -+ memset(&t, 0, sizeof(t)); -+ spi_message_init(&m); -+ -+ /* send command */ -+ t[0].tx_buf = cmd; -+ t[0].len = sizeof(cmd); -+ spi_message_add_tail(&t[0], &m); -+ -+ cmd[0] = CPLD_CMD_WRITE_NAND; -+ -+ /* write data */ -+ t[1].tx_buf = buf; -+ t[1].len = count; -+ spi_message_add_tail(&t[1], &m); -+ -+ /* send idle */ -+ t[2].len = 1; -+ spi_message_add_tail(&t[2], &m); -+ -+ return spi_sync(rb4xx_cpld->spi, &m); -+#else -+ static const unsigned char cmd = CPLD_CMD_WRITE_NAND; -+ struct spi_transfer t[3] = { -+ { -+ .tx_buf = &cmd, -+ .len = 1, -+ }, { -+ .tx_buf = buf, -+ .len = count, -+ .fast_write = 1, -+ }, { -+ .len = 1, -+ .fast_write = 1, -+ }, -+ }; -+ struct spi_message m; -+ -+ if (rb4xx_cpld == NULL) -+ return -ENODEV; -+ -+ spi_message_init(&m); -+ spi_message_add_tail(&t[0], &m); -+ spi_message_add_tail(&t[1], &m); -+ spi_message_add_tail(&t[2], &m); -+ return spi_sync(rb4xx_cpld->spi, &m); -+#endif -+} -+EXPORT_SYMBOL_GPL(rb4xx_cpld_write); -+ -+static int rb4xx_cpld_gpio_get(struct gpio_chip *chip, unsigned offset) -+{ -+ struct rb4xx_cpld *cpld = gpio_to_cpld(chip); -+ int ret; -+ -+ mutex_lock(&cpld->lock); -+ ret = (cpld->config >> offset) & 1; -+ mutex_unlock(&cpld->lock); -+ -+ return ret; -+} -+ -+static void rb4xx_cpld_gpio_set(struct gpio_chip *chip, unsigned offset, -+ int value) -+{ -+ struct rb4xx_cpld *cpld = gpio_to_cpld(chip); -+ -+ mutex_lock(&cpld->lock); -+ __rb4xx_cpld_change_cfg(cpld, (1 << offset), !!value << offset); -+ mutex_unlock(&cpld->lock); -+} -+ -+static int rb4xx_cpld_gpio_direction_input(struct gpio_chip *chip, -+ unsigned offset) -+{ -+ return -EOPNOTSUPP; -+} -+ -+static int rb4xx_cpld_gpio_direction_output(struct gpio_chip *chip, -+ unsigned offset, -+ int value) -+{ -+ struct rb4xx_cpld *cpld = gpio_to_cpld(chip); -+ int ret; -+ -+ mutex_lock(&cpld->lock); -+ ret = __rb4xx_cpld_change_cfg(cpld, (1 << offset), !!value << offset); -+ mutex_unlock(&cpld->lock); -+ -+ return ret; -+} -+ -+static int rb4xx_cpld_gpio_init(struct rb4xx_cpld *cpld, unsigned int base) -+{ -+ int err; -+ -+ /* init config */ -+ cpld->config = CPLD_CFG_nLED1 | CPLD_CFG_nLED2 | CPLD_CFG_nLED3 | -+ CPLD_CFG_nLED4 | CPLD_CFG_nCE; -+ rb4xx_cpld_write_cfg(cpld, cpld->config); -+ -+ /* setup GPIO chip */ -+ cpld->chip.label = DRV_NAME; -+ -+ cpld->chip.get = rb4xx_cpld_gpio_get; -+ cpld->chip.set = rb4xx_cpld_gpio_set; -+ cpld->chip.direction_input = rb4xx_cpld_gpio_direction_input; -+ cpld->chip.direction_output = rb4xx_cpld_gpio_direction_output; -+ -+ cpld->chip.base = base; -+ cpld->chip.ngpio = CPLD_NUM_GPIOS; -+ cpld->chip.can_sleep = 1; -+ cpld->chip.dev = &cpld->spi->dev; -+ cpld->chip.owner = THIS_MODULE; -+ -+ err = gpiochip_add(&cpld->chip); -+ if (err) -+ dev_err(&cpld->spi->dev, "adding GPIO chip failed, err=%d\n", -+ err); -+ -+ return err; -+} -+ -+static int __devinit rb4xx_cpld_probe(struct spi_device *spi) -+{ -+ struct rb4xx_cpld *cpld; -+ struct rb4xx_cpld_platform_data *pdata; -+ int err; -+ -+ pdata = spi->dev.platform_data; -+ if (!pdata) { -+ dev_dbg(&spi->dev, "no platform data\n"); -+ return -EINVAL; -+ } -+ -+ cpld = kzalloc(sizeof(*cpld), GFP_KERNEL); -+ if (!cpld) { -+ dev_err(&spi->dev, "no memory for private data\n"); -+ return -ENOMEM; -+ } -+ -+ mutex_init(&cpld->lock); -+ cpld->spi = spi_dev_get(spi); -+ dev_set_drvdata(&spi->dev, cpld); -+ -+ spi->mode = SPI_MODE_0; -+ spi->bits_per_word = 8; -+ err = spi_setup(spi); -+ if (err) { -+ dev_err(&spi->dev, "spi_setup failed, err=%d\n", err); -+ goto err_drvdata; -+ } -+ -+ err = rb4xx_cpld_gpio_init(cpld, pdata->gpio_base); -+ if (err) -+ goto err_drvdata; -+ -+ rb4xx_cpld = cpld; -+ -+ return 0; -+ -+err_drvdata: -+ dev_set_drvdata(&spi->dev, NULL); -+ kfree(cpld); -+ -+ return err; -+} -+ -+static int __devexit rb4xx_cpld_remove(struct spi_device *spi) -+{ -+ struct rb4xx_cpld *cpld; -+ -+ rb4xx_cpld = NULL; -+ cpld = dev_get_drvdata(&spi->dev); -+ dev_set_drvdata(&spi->dev, NULL); -+ kfree(cpld); -+ -+ return 0; -+} -+ -+static struct spi_driver rb4xx_cpld_driver = { -+ .driver = { -+ .name = DRV_NAME, -+ .bus = &spi_bus_type, -+ .owner = THIS_MODULE, -+ }, -+ .probe = rb4xx_cpld_probe, -+ .remove = __devexit_p(rb4xx_cpld_remove), -+}; -+ -+static int __init rb4xx_cpld_init(void) -+{ -+ return spi_register_driver(&rb4xx_cpld_driver); -+} -+module_init(rb4xx_cpld_init); -+ -+static void __exit rb4xx_cpld_exit(void) -+{ -+ spi_unregister_driver(&rb4xx_cpld_driver); -+} -+module_exit(rb4xx_cpld_exit); -+ -+MODULE_DESCRIPTION(DRV_DESC); -+MODULE_VERSION(DRV_VERSION); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_LICENSE("GPL v2"); -diff -Nur linux-2.6.39.orig/drivers/spi/spi_vsc7385.c linux-2.6.39/drivers/spi/spi_vsc7385.c ---- linux-2.6.39.orig/drivers/spi/spi_vsc7385.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/drivers/spi/spi_vsc7385.c 2011-08-24 18:17:24.000000000 +0200 -@@ -0,0 +1,621 @@ -+/* -+ * SPI driver for the Vitesse VSC7385 ethernet switch -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define DRV_NAME "spi-vsc7385" -+#define DRV_DESC "Vitesse VSC7385 Gbit ethernet switch driver" -+#define DRV_VERSION "0.1.0" -+ -+#define VSC73XX_BLOCK_MAC 0x1 -+#define VSC73XX_BLOCK_2 0x2 -+#define VSC73XX_BLOCK_MII 0x3 -+#define VSC73XX_BLOCK_4 0x4 -+#define VSC73XX_BLOCK_5 0x5 -+#define VSC73XX_BLOCK_SYSTEM 0x7 -+ -+#define VSC73XX_SUBBLOCK_PORT_0 0 -+#define VSC73XX_SUBBLOCK_PORT_1 1 -+#define VSC73XX_SUBBLOCK_PORT_2 2 -+#define VSC73XX_SUBBLOCK_PORT_3 3 -+#define VSC73XX_SUBBLOCK_PORT_4 4 -+#define VSC73XX_SUBBLOCK_PORT_MAC 6 -+ -+/* MAC Block registers */ -+#define VSC73XX_MAC_CFG 0x0 -+#define VSC73XX_ADVPORTM 0x19 -+#define VSC73XX_RXOCT 0x50 -+#define VSC73XX_TXOCT 0x51 -+#define VSC73XX_C_RX0 0x52 -+#define VSC73XX_C_RX1 0x53 -+#define VSC73XX_C_RX2 0x54 -+#define VSC73XX_C_TX0 0x55 -+#define VSC73XX_C_TX1 0x56 -+#define VSC73XX_C_TX2 0x57 -+#define VSC73XX_C_CFG 0x58 -+ -+/* MAC_CFG register bits */ -+#define VSC73XX_MAC_CFG_WEXC_DIS (1 << 31) -+#define VSC73XX_MAC_CFG_PORT_RST (1 << 29) -+#define VSC73XX_MAC_CFG_TX_EN (1 << 28) -+#define VSC73XX_MAC_CFG_SEED_LOAD (1 << 27) -+#define VSC73XX_MAC_CFG_FDX (1 << 18) -+#define VSC73XX_MAC_CFG_GIGE (1 << 17) -+#define VSC73XX_MAC_CFG_RX_EN (1 << 16) -+#define VSC73XX_MAC_CFG_VLAN_DBLAWR (1 << 15) -+#define VSC73XX_MAC_CFG_VLAN_AWR (1 << 14) -+#define VSC73XX_MAC_CFG_100_BASE_T (1 << 13) -+#define VSC73XX_MAC_CFG_TX_IPG(x) (((x) & 0x1f) << 6) -+#define VSC73XX_MAC_CFG_MAC_RX_RST (1 << 5) -+#define VSC73XX_MAC_CFG_MAC_TX_RST (1 << 4) -+#define VSC73XX_MAC_CFG_BIT2 (1 << 2) -+#define VSC73XX_MAC_CFG_CLK_SEL(x) ((x) & 0x3) -+ -+/* ADVPORTM register bits */ -+#define VSC73XX_ADVPORTM_IFG_PPM (1 << 7) -+#define VSC73XX_ADVPORTM_EXC_COL_CONT (1 << 6) -+#define VSC73XX_ADVPORTM_EXT_PORT (1 << 5) -+#define VSC73XX_ADVPORTM_INV_GTX (1 << 4) -+#define VSC73XX_ADVPORTM_ENA_GTX (1 << 3) -+#define VSC73XX_ADVPORTM_DDR_MODE (1 << 2) -+#define VSC73XX_ADVPORTM_IO_LOOPBACK (1 << 1) -+#define VSC73XX_ADVPORTM_HOST_LOOPBACK (1 << 0) -+ -+/* MII Block registers */ -+#define VSC73XX_MII_STAT 0x0 -+#define VSC73XX_MII_CMD 0x1 -+#define VSC73XX_MII_DATA 0x2 -+ -+/* System Block registers */ -+#define VSC73XX_ICPU_SIPAD 0x01 -+#define VSC73XX_ICPU_CLOCK_DELAY 0x05 -+#define VSC73XX_ICPU_CTRL 0x10 -+#define VSC73XX_ICPU_ADDR 0x11 -+#define VSC73XX_ICPU_SRAM 0x12 -+#define VSC73XX_ICPU_MBOX_VAL 0x15 -+#define VSC73XX_ICPU_MBOX_SET 0x16 -+#define VSC73XX_ICPU_MBOX_CLR 0x17 -+#define VSC73XX_ICPU_CHIPID 0x18 -+#define VSC73XX_ICPU_GPIO 0x34 -+ -+#define VSC73XX_ICPU_CTRL_CLK_DIV (1 << 8) -+#define VSC73XX_ICPU_CTRL_SRST_HOLD (1 << 7) -+#define VSC73XX_ICPU_CTRL_BOOT_EN (1 << 3) -+#define VSC73XX_ICPU_CTRL_EXT_ACC_EN (1 << 2) -+#define VSC73XX_ICPU_CTRL_CLK_EN (1 << 1) -+#define VSC73XX_ICPU_CTRL_SRST (1 << 0) -+ -+#define VSC73XX_ICPU_CHIPID_ID_SHIFT 12 -+#define VSC73XX_ICPU_CHIPID_ID_MASK 0xffff -+#define VSC73XX_ICPU_CHIPID_REV_SHIFT 28 -+#define VSC73XX_ICPU_CHIPID_REV_MASK 0xf -+#define VSC73XX_ICPU_CHIPID_ID_7385 0x7385 -+#define VSC73XX_ICPU_CHIPID_ID_7395 0x7395 -+ -+#define VSC73XX_CMD_MODE_READ 0 -+#define VSC73XX_CMD_MODE_WRITE 1 -+#define VSC73XX_CMD_MODE_SHIFT 4 -+#define VSC73XX_CMD_BLOCK_SHIFT 5 -+#define VSC73XX_CMD_BLOCK_MASK 0x7 -+#define VSC73XX_CMD_SUBBLOCK_MASK 0xf -+ -+#define VSC7385_CLOCK_DELAY ((3 << 4) | 3) -+#define VSC7385_CLOCK_DELAY_MASK ((3 << 4) | 3) -+ -+#define VSC73XX_ICPU_CTRL_STOP (VSC73XX_ICPU_CTRL_SRST_HOLD | \ -+ VSC73XX_ICPU_CTRL_BOOT_EN | \ -+ VSC73XX_ICPU_CTRL_EXT_ACC_EN) -+ -+#define VSC73XX_ICPU_CTRL_START (VSC73XX_ICPU_CTRL_CLK_DIV | \ -+ VSC73XX_ICPU_CTRL_BOOT_EN | \ -+ VSC73XX_ICPU_CTRL_CLK_EN | \ -+ VSC73XX_ICPU_CTRL_SRST) -+ -+#define VSC7385_ADVPORTM_MASK (VSC73XX_ADVPORTM_IFG_PPM | \ -+ VSC73XX_ADVPORTM_EXC_COL_CONT | \ -+ VSC73XX_ADVPORTM_EXT_PORT | \ -+ VSC73XX_ADVPORTM_INV_GTX | \ -+ VSC73XX_ADVPORTM_ENA_GTX | \ -+ VSC73XX_ADVPORTM_DDR_MODE | \ -+ VSC73XX_ADVPORTM_IO_LOOPBACK | \ -+ VSC73XX_ADVPORTM_HOST_LOOPBACK) -+ -+#define VSC7385_ADVPORTM_INIT (VSC73XX_ADVPORTM_EXT_PORT | \ -+ VSC73XX_ADVPORTM_ENA_GTX | \ -+ VSC73XX_ADVPORTM_DDR_MODE) -+ -+#define VSC7385_MAC_CFG_RESET (VSC73XX_MAC_CFG_PORT_RST | \ -+ VSC73XX_MAC_CFG_MAC_RX_RST | \ -+ VSC73XX_MAC_CFG_MAC_TX_RST) -+ -+#define VSC73XX_MAC_CFG_INIT (VSC73XX_MAC_CFG_TX_EN | \ -+ VSC73XX_MAC_CFG_FDX | \ -+ VSC73XX_MAC_CFG_GIGE | \ -+ VSC73XX_MAC_CFG_RX_EN) -+ -+#define VSC73XX_RESET_DELAY 100 -+ -+struct vsc7385 { -+ struct spi_device *spi; -+ struct mutex lock; -+ struct vsc7385_platform_data *pdata; -+}; -+ -+static int vsc7385_is_addr_valid(u8 block, u8 subblock) -+{ -+ switch (block) { -+ case VSC73XX_BLOCK_MAC: -+ switch (subblock) { -+ case 0 ... 4: -+ case 6: -+ return 1; -+ } -+ break; -+ -+ case VSC73XX_BLOCK_2: -+ case VSC73XX_BLOCK_SYSTEM: -+ switch (subblock) { -+ case 0: -+ return 1; -+ } -+ break; -+ -+ case VSC73XX_BLOCK_MII: -+ case VSC73XX_BLOCK_4: -+ case VSC73XX_BLOCK_5: -+ switch (subblock) { -+ case 0 ... 1: -+ return 1; -+ } -+ break; -+ } -+ -+ return 0; -+} -+ -+static inline u8 vsc7385_make_addr(u8 mode, u8 block, u8 subblock) -+{ -+ u8 ret; -+ -+ ret = (block & VSC73XX_CMD_BLOCK_MASK) << VSC73XX_CMD_BLOCK_SHIFT; -+ ret |= (mode & 1) << VSC73XX_CMD_MODE_SHIFT; -+ ret |= subblock & VSC73XX_CMD_SUBBLOCK_MASK; -+ -+ return ret; -+} -+ -+static int vsc7385_read(struct vsc7385 *vsc, u8 block, u8 subblock, u8 reg, -+ u32 *value) -+{ -+ u8 cmd[4]; -+ u8 buf[4]; -+ struct spi_transfer t[2]; -+ struct spi_message m; -+ int err; -+ -+ if (!vsc7385_is_addr_valid(block, subblock)) -+ return -EINVAL; -+ -+ spi_message_init(&m); -+ -+ memset(&t, 0, sizeof(t)); -+ -+ t[0].tx_buf = cmd; -+ t[0].len = sizeof(cmd); -+ spi_message_add_tail(&t[0], &m); -+ -+ t[1].rx_buf = buf; -+ t[1].len = sizeof(buf); -+ spi_message_add_tail(&t[1], &m); -+ -+ cmd[0] = vsc7385_make_addr(VSC73XX_CMD_MODE_READ, block, subblock); -+ cmd[1] = reg; -+ cmd[2] = 0; -+ cmd[3] = 0; -+ -+ mutex_lock(&vsc->lock); -+ err = spi_sync(vsc->spi, &m); -+ mutex_unlock(&vsc->lock); -+ -+ if (err) -+ return err; -+ -+ *value = (((u32) buf[0]) << 24) | (((u32) buf[1]) << 16) | -+ (((u32) buf[2]) << 8) | ((u32) buf[3]); -+ -+ return 0; -+} -+ -+ -+static int vsc7385_write(struct vsc7385 *vsc, u8 block, u8 subblock, u8 reg, -+ u32 value) -+{ -+ u8 cmd[2]; -+ u8 buf[4]; -+ struct spi_transfer t[2]; -+ struct spi_message m; -+ int err; -+ -+ if (!vsc7385_is_addr_valid(block, subblock)) -+ return -EINVAL; -+ -+ spi_message_init(&m); -+ -+ memset(&t, 0, sizeof(t)); -+ -+ t[0].tx_buf = cmd; -+ t[0].len = sizeof(cmd); -+ spi_message_add_tail(&t[0], &m); -+ -+ t[1].tx_buf = buf; -+ t[1].len = sizeof(buf); -+ spi_message_add_tail(&t[1], &m); -+ -+ cmd[0] = vsc7385_make_addr(VSC73XX_CMD_MODE_WRITE, block, subblock); -+ cmd[1] = reg; -+ -+ buf[0] = (value >> 24) & 0xff; -+ buf[1] = (value >> 16) & 0xff; -+ buf[2] = (value >> 8) & 0xff; -+ buf[3] = value & 0xff; -+ -+ mutex_lock(&vsc->lock); -+ err = spi_sync(vsc->spi, &m); -+ mutex_unlock(&vsc->lock); -+ -+ return err; -+} -+ -+static inline int vsc7385_write_verify(struct vsc7385 *vsc, u8 block, -+ u8 subblock, u8 reg, u32 value, -+ u32 read_mask, u32 read_val) -+{ -+ struct spi_device *spi = vsc->spi; -+ u32 t; -+ int err; -+ -+ err = vsc7385_write(vsc, block, subblock, reg, value); -+ if (err) -+ return err; -+ -+ err = vsc7385_read(vsc, block, subblock, reg, &t); -+ if (err) -+ return err; -+ -+ if ((t & read_mask) != read_val) { -+ dev_err(&spi->dev, "register write error\n"); -+ return -EIO; -+ } -+ -+ return 0; -+} -+ -+static inline int vsc7385_set_clock_delay(struct vsc7385 *vsc, u32 val) -+{ -+ return vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, -+ VSC73XX_ICPU_CLOCK_DELAY, val); -+} -+ -+static inline int vsc7385_get_clock_delay(struct vsc7385 *vsc, u32 *val) -+{ -+ return vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, -+ VSC73XX_ICPU_CLOCK_DELAY, val); -+} -+ -+static inline int vsc7385_icpu_stop(struct vsc7385 *vsc) -+{ -+ return vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_ICPU_CTRL, -+ VSC73XX_ICPU_CTRL_STOP); -+} -+ -+static inline int vsc7385_icpu_start(struct vsc7385 *vsc) -+{ -+ return vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_ICPU_CTRL, -+ VSC73XX_ICPU_CTRL_START); -+} -+ -+static inline int vsc7385_icpu_reset(struct vsc7385 *vsc) -+{ -+ int rc; -+ -+ rc = vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_ICPU_ADDR, -+ 0x0000); -+ if (rc) -+ dev_err(&vsc->spi->dev, -+ "could not reset microcode, err=%d\n", rc); -+ -+ return rc; -+} -+ -+static int vsc7385_upload_ucode(struct vsc7385 *vsc) -+{ -+ struct spi_device *spi = vsc->spi; -+ const struct firmware *firmware; -+ char *ucode_name; -+ unsigned char *dp; -+ unsigned int curVal; -+ int i; -+ int diffs; -+ int rc; -+ -+ ucode_name = (vsc->pdata->ucode_name) ? vsc->pdata->ucode_name -+ : "vsc7385_ucode.bin"; -+ rc = request_firmware(&firmware, ucode_name, &spi->dev); -+ if (rc) { -+ dev_err(&spi->dev, "request_firmware failed, err=%d\n", -+ rc); -+ return rc; -+ } -+ -+ rc = vsc7385_icpu_stop(vsc); -+ if (rc) -+ goto out; -+ -+ rc = vsc7385_icpu_reset(vsc); -+ if (rc) -+ goto out; -+ -+ dev_info(&spi->dev, "uploading microcode...\n"); -+ -+ dp = (unsigned char *) firmware->data; -+ for (i = 0; i < firmware->size; i++) { -+ rc = vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, -+ VSC73XX_ICPU_SRAM, *dp++); -+ if (rc) { -+ dev_err(&spi->dev, "could not load microcode, err=%d\n", -+ rc); -+ goto out; -+ } -+ } -+ -+ rc = vsc7385_icpu_reset(vsc); -+ if (rc) -+ goto out; -+ -+ dev_info(&spi->dev, "verifying microcode...\n"); -+ -+ dp = (unsigned char *) firmware->data; -+ diffs = 0; -+ for (i = 0; i < firmware->size; i++) { -+ rc = vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, -+ VSC73XX_ICPU_SRAM, &curVal); -+ if (rc) { -+ dev_err(&spi->dev, "could not read microcode %d\n", -+ rc); -+ goto out; -+ } -+ -+ if (curVal > 0xff) { -+ dev_err(&spi->dev, "bad val read: %04x : %02x %02x\n", -+ i, *dp, curVal); -+ rc = -EIO; -+ goto out; -+ } -+ -+ if ((curVal & 0xff) != *dp) { -+ diffs++; -+ dev_err(&spi->dev, "verify error: %04x : %02x %02x\n", -+ i, *dp, curVal); -+ -+ if (diffs > 4) -+ break; -+ } -+ dp++; -+ } -+ -+ if (diffs) { -+ dev_err(&spi->dev, "microcode verification failed\n"); -+ rc = -EIO; -+ goto out; -+ } -+ -+ dev_info(&spi->dev, "microcode uploaded\n"); -+ -+ rc = vsc7385_icpu_start(vsc); -+ -+out: -+ release_firmware(firmware); -+ return rc; -+} -+ -+static int vsc7385_setup(struct vsc7385 *vsc) -+{ -+ struct vsc7385_platform_data *pdata = vsc->pdata; -+ u32 t; -+ int err; -+ -+ err = vsc7385_write_verify(vsc, VSC73XX_BLOCK_SYSTEM, 0, -+ VSC73XX_ICPU_CLOCK_DELAY, -+ VSC7385_CLOCK_DELAY, -+ VSC7385_CLOCK_DELAY_MASK, -+ VSC7385_CLOCK_DELAY); -+ if (err) -+ goto err; -+ -+ err = vsc7385_write_verify(vsc, VSC73XX_BLOCK_MAC, -+ VSC73XX_SUBBLOCK_PORT_MAC, VSC73XX_ADVPORTM, -+ VSC7385_ADVPORTM_INIT, -+ VSC7385_ADVPORTM_MASK, -+ VSC7385_ADVPORTM_INIT); -+ if (err) -+ goto err; -+ -+ err = vsc7385_write(vsc, VSC73XX_BLOCK_MAC, VSC73XX_SUBBLOCK_PORT_MAC, -+ VSC73XX_MAC_CFG, VSC7385_MAC_CFG_RESET); -+ if (err) -+ goto err; -+ -+ t = VSC73XX_MAC_CFG_INIT; -+ t |= VSC73XX_MAC_CFG_TX_IPG(pdata->mac_cfg.tx_ipg); -+ t |= VSC73XX_MAC_CFG_CLK_SEL(pdata->mac_cfg.clk_sel); -+ if (pdata->mac_cfg.bit2) -+ t |= VSC73XX_MAC_CFG_BIT2; -+ -+ err = vsc7385_write(vsc, VSC73XX_BLOCK_MAC, VSC73XX_SUBBLOCK_PORT_MAC, -+ VSC73XX_MAC_CFG, t); -+ if (err) -+ goto err; -+ -+ return 0; -+ -+err: -+ return err; -+} -+ -+static int vsc7385_detect(struct vsc7385 *vsc) -+{ -+ struct spi_device *spi = vsc->spi; -+ u32 t; -+ u32 id; -+ u32 rev; -+ int err; -+ -+ err = vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, -+ VSC73XX_ICPU_MBOX_VAL, &t); -+ if (err) { -+ dev_err(&spi->dev, "unable to read mailbox, err=%d\n", err); -+ return err; -+ } -+ -+ if (t == 0xffffffff) { -+ dev_dbg(&spi->dev, "assert chip reset\n"); -+ if (vsc->pdata->reset) -+ vsc->pdata->reset(); -+ -+ } -+ -+ err = vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, -+ VSC73XX_ICPU_CHIPID, &t); -+ if (err) { -+ dev_err(&spi->dev, "unable to read chip id, err=%d\n", err); -+ return err; -+ } -+ -+ id = (t >> VSC73XX_ICPU_CHIPID_ID_SHIFT) & VSC73XX_ICPU_CHIPID_ID_MASK; -+ switch (id) { -+ case VSC73XX_ICPU_CHIPID_ID_7385: -+ case VSC73XX_ICPU_CHIPID_ID_7395: -+ break; -+ default: -+ dev_err(&spi->dev, "unsupported chip, id=%04x\n", id); -+ return -ENODEV; -+ } -+ -+ rev = (t >> VSC73XX_ICPU_CHIPID_REV_SHIFT) & -+ VSC73XX_ICPU_CHIPID_REV_MASK; -+ dev_info(&spi->dev, "VSC%04X (rev. %d) switch found\n", id, rev); -+ -+ return 0; -+} -+ -+static int __devinit vsc7385_probe(struct spi_device *spi) -+{ -+ struct vsc7385 *vsc; -+ struct vsc7385_platform_data *pdata; -+ int err; -+ -+ printk(KERN_INFO DRV_DESC " version " DRV_VERSION"\n"); -+ -+ pdata = spi->dev.platform_data; -+ if (!pdata) { -+ dev_err(&spi->dev, "no platform data specified\n"); -+ return -ENODEV; -+ } -+ -+ vsc = kzalloc(sizeof(*vsc), GFP_KERNEL); -+ if (!vsc) { -+ dev_err(&spi->dev, "no memory for private data\n"); -+ return -ENOMEM; -+ } -+ -+ mutex_init(&vsc->lock); -+ vsc->pdata = pdata; -+ vsc->spi = spi_dev_get(spi); -+ dev_set_drvdata(&spi->dev, vsc); -+ -+ spi->mode = SPI_MODE_0; -+ spi->bits_per_word = 8; -+ err = spi_setup(spi); -+ if (err) { -+ dev_err(&spi->dev, "spi_setup failed, err=%d\n", err); -+ goto err_drvdata; -+ } -+ -+ err = vsc7385_detect(vsc); -+ if (err) { -+ dev_err(&spi->dev, "no chip found, err=%d\n", err); -+ goto err_drvdata; -+ } -+ -+ err = vsc7385_upload_ucode(vsc); -+ if (err) -+ goto err_drvdata; -+ -+ err = vsc7385_setup(vsc); -+ if (err) -+ goto err_drvdata; -+ -+ return 0; -+ -+err_drvdata: -+ dev_set_drvdata(&spi->dev, NULL); -+ kfree(vsc); -+ return err; -+} -+ -+static int __devexit vsc7385_remove(struct spi_device *spi) -+{ -+ struct vsc7385_data *vsc; -+ -+ vsc = dev_get_drvdata(&spi->dev); -+ dev_set_drvdata(&spi->dev, NULL); -+ kfree(vsc); -+ -+ return 0; -+} -+ -+static struct spi_driver vsc7385_driver = { -+ .driver = { -+ .name = DRV_NAME, -+ .bus = &spi_bus_type, -+ .owner = THIS_MODULE, -+ }, -+ .probe = vsc7385_probe, -+ .remove = __devexit_p(vsc7385_remove), -+}; -+ -+static int __init vsc7385_init(void) -+{ -+ return spi_register_driver(&vsc7385_driver); -+} -+module_init(vsc7385_init); -+ -+static void __exit vsc7385_exit(void) -+{ -+ spi_unregister_driver(&vsc7385_driver); -+} -+module_exit(vsc7385_exit); -+ -+MODULE_DESCRIPTION(DRV_DESC); -+MODULE_VERSION(DRV_VERSION); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_LICENSE("GPL v2"); -+ -diff -Nur linux-2.6.39.orig/drivers/tty/serial/ar933x_uart.c linux-2.6.39/drivers/tty/serial/ar933x_uart.c ---- linux-2.6.39.orig/drivers/tty/serial/ar933x_uart.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/drivers/tty/serial/ar933x_uart.c 2011-08-24 18:17:24.000000000 +0200 -@@ -0,0 +1,688 @@ -+/* -+ * Atheros AR933X SoC built-in UART driver -+ * -+ * Copyright (C) 2011 Gabor Juhos -+ * -+ * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#define DRIVER_NAME "ar933x-uart" -+ -+#define AR933X_DUMMY_STATUS_RD 0x01 -+ -+static struct uart_driver ar933x_uart_driver; -+ -+struct ar933x_uart_port { -+ struct uart_port port; -+ unsigned int ier; /* shadow Interrupt Enable Register */ -+}; -+ -+static inline unsigned int ar933x_uart_read(struct ar933x_uart_port *up, -+ int offset) -+{ -+ return readl(up->port.membase + offset); -+} -+ -+static inline void ar933x_uart_write(struct ar933x_uart_port *up, -+ int offset, unsigned int value) -+{ -+ writel(value, up->port.membase + offset); -+} -+ -+static inline void ar933x_uart_rmw(struct ar933x_uart_port *up, -+ unsigned int offset, -+ unsigned int mask, -+ unsigned int val) -+{ -+ unsigned int t; -+ -+ t = ar933x_uart_read(up, offset); -+ t &= ~mask; -+ t |= val; -+ ar933x_uart_write(up, offset, t); -+} -+ -+static inline void ar933x_uart_rmw_set(struct ar933x_uart_port *up, -+ unsigned int offset, -+ unsigned int val) -+{ -+ ar933x_uart_rmw(up, offset, 0, val); -+} -+ -+static inline void ar933x_uart_rmw_clear(struct ar933x_uart_port *up, -+ unsigned int offset, -+ unsigned int val) -+{ -+ ar933x_uart_rmw(up, offset, val, 0); -+} -+ -+static inline void ar933x_uart_start_tx_interrupt(struct ar933x_uart_port *up) -+{ -+ up->ier |= AR933X_UART_INT_TX_EMPTY; -+ ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier); -+} -+ -+static inline void ar933x_uart_stop_tx_interrupt(struct ar933x_uart_port *up) -+{ -+ up->ier &= ~AR933X_UART_INT_TX_EMPTY; -+ ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier); -+} -+ -+static inline void ar933x_uart_putc(struct ar933x_uart_port *up, int ch) -+{ -+ unsigned int rdata; -+ -+ rdata = ch & AR933X_UART_DATA_TX_RX_MASK; -+ rdata |= AR933X_UART_DATA_TX_CSR; -+ ar933x_uart_write(up, AR933X_UART_DATA_REG, rdata); -+} -+ -+static unsigned int ar933x_uart_tx_empty(struct uart_port *port) -+{ -+ struct ar933x_uart_port *up = (struct ar933x_uart_port *) port; -+ unsigned long flags; -+ unsigned int rdata; -+ -+ spin_lock_irqsave(&up->port.lock, flags); -+ rdata = ar933x_uart_read(up, AR933X_UART_DATA_REG); -+ spin_unlock_irqrestore(&up->port.lock, flags); -+ -+ return (rdata & AR933X_UART_DATA_TX_CSR) ? 0 : TIOCSER_TEMT; -+} -+ -+static unsigned int ar933x_uart_get_mctrl(struct uart_port *port) -+{ -+ return TIOCM_CAR; -+} -+ -+static void ar933x_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) -+{ -+} -+ -+static void ar933x_uart_start_tx(struct uart_port *port) -+{ -+ struct ar933x_uart_port *up = (struct ar933x_uart_port *) port; -+ -+ ar933x_uart_start_tx_interrupt(up); -+} -+ -+static void ar933x_uart_stop_tx(struct uart_port *port) -+{ -+ struct ar933x_uart_port *up = (struct ar933x_uart_port *) port; -+ -+ ar933x_uart_stop_tx_interrupt(up); -+} -+ -+static void ar933x_uart_stop_rx(struct uart_port *port) -+{ -+ struct ar933x_uart_port *up = (struct ar933x_uart_port *) port; -+ -+ up->ier &= ~AR933X_UART_INT_RX_VALID; -+ ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier); -+} -+ -+static void ar933x_uart_break_ctl(struct uart_port *port, int break_state) -+{ -+ struct ar933x_uart_port *up = (struct ar933x_uart_port *) port; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&up->port.lock, flags); -+ if (break_state == -1) -+ ar933x_uart_rmw_set(up, AR933X_UART_CS_REG, -+ AR933X_UART_CS_TX_BREAK); -+ else -+ ar933x_uart_rmw_clear(up, AR933X_UART_CS_REG, -+ AR933X_UART_CS_TX_BREAK); -+ spin_unlock_irqrestore(&up->port.lock, flags); -+} -+ -+static void ar933x_uart_enable_ms(struct uart_port *port) -+{ -+} -+ -+static void ar933x_uart_set_termios(struct uart_port *port, -+ struct ktermios *new, -+ struct ktermios *old) -+{ -+ struct ar933x_uart_port *up = (struct ar933x_uart_port *) port; -+ unsigned int cs; -+ unsigned long flags; -+ unsigned int baud, scale; -+ -+ /* Only CS8 is supported */ -+ new->c_cflag &= ~CSIZE; -+ new->c_cflag |= CS8; -+ -+ /* Only one stop bit is supported */ -+ new->c_cflag &= ~CSTOPB; -+ -+ cs = 0; -+ if (new->c_cflag & PARENB) { -+ if (!(new->c_cflag & PARODD)) -+ cs |= AR933X_UART_CS_PARITY_EVEN; -+ else -+ cs |= AR933X_UART_CS_PARITY_ODD; -+ } else { -+ cs |= AR933X_UART_CS_PARITY_NONE; -+ } -+ -+ /* Mark/space parity is not supported */ -+ new->c_cflag &= ~CMSPAR; -+ -+ baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16); -+ scale = (port->uartclk / (16 * baud)) - 1; -+ -+ /* -+ * Ok, we're now changing the port state. Do it with -+ * interrupts disabled. -+ */ -+ spin_lock_irqsave(&up->port.lock, flags); -+ -+ /* Update the per-port timeout. */ -+ uart_update_timeout(port, new->c_cflag, baud); -+ -+ up->port.ignore_status_mask = 0; -+ -+ /* ignore all characters if CREAD is not set */ -+ if ((new->c_cflag & CREAD) == 0) -+ up->port.ignore_status_mask |= AR933X_DUMMY_STATUS_RD; -+ -+ ar933x_uart_write(up, AR933X_UART_CLOCK_REG, -+ scale << AR933X_UART_CLOCK_SCALE_S | 8192); -+ -+ /* setup configuration register */ -+ ar933x_uart_rmw(up, AR933X_UART_CS_REG, AR933X_UART_CS_PARITY_M, cs); -+ -+ /* enable host interrupt */ -+ ar933x_uart_rmw_set(up, AR933X_UART_CS_REG, -+ AR933X_UART_CS_HOST_INT_EN); -+ -+ spin_unlock_irqrestore(&up->port.lock, flags); -+ -+ if (tty_termios_baud_rate(new)) -+ tty_termios_encode_baud_rate(new, baud, baud); -+} -+ -+static void ar933x_uart_rx_chars(struct ar933x_uart_port *up) -+{ -+ struct tty_struct *tty; -+ int max_count = 256; -+ -+ tty = tty_port_tty_get(&up->port.state->port); -+ do { -+ unsigned int rdata; -+ unsigned char ch; -+ -+ rdata = ar933x_uart_read(up, AR933X_UART_DATA_REG); -+ if ((rdata & AR933X_UART_DATA_RX_CSR) == 0) -+ break; -+ -+ /* remove the character from the FIFO */ -+ ar933x_uart_write(up, AR933X_UART_DATA_REG, -+ AR933X_UART_DATA_RX_CSR); -+ -+ if (!tty) { -+ /* discard the data if no tty available */ -+ continue; -+ } -+ -+ up->port.icount.rx++; -+ ch = rdata & AR933X_UART_DATA_TX_RX_MASK; -+ -+ if (uart_handle_sysrq_char(&up->port, ch)) -+ continue; -+ -+ if ((up->port.ignore_status_mask & AR933X_DUMMY_STATUS_RD) == 0) -+ tty_insert_flip_char(tty, ch, TTY_NORMAL); -+ } while (max_count-- > 0); -+ -+ if (tty) { -+ tty_flip_buffer_push(tty); -+ tty_kref_put(tty); -+ } -+} -+ -+static void ar933x_uart_tx_chars(struct ar933x_uart_port *up) -+{ -+ struct circ_buf *xmit = &up->port.state->xmit; -+ int count; -+ -+ if (uart_tx_stopped(&up->port)) -+ return; -+ -+ count = up->port.fifosize; -+ do { -+ unsigned int rdata; -+ -+ rdata = ar933x_uart_read(up, AR933X_UART_DATA_REG); -+ if ((rdata & AR933X_UART_DATA_TX_CSR) == 0) -+ break; -+ -+ if (up->port.x_char) { -+ ar933x_uart_putc(up, up->port.x_char); -+ up->port.icount.tx++; -+ up->port.x_char = 0; -+ continue; -+ } -+ -+ if (uart_circ_empty(xmit)) -+ break; -+ -+ ar933x_uart_putc(up, xmit->buf[xmit->tail]); -+ -+ xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); -+ up->port.icount.tx++; -+ } while (--count > 0); -+ -+ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) -+ uart_write_wakeup(&up->port); -+ -+ if (!uart_circ_empty(xmit)) -+ ar933x_uart_start_tx_interrupt(up); -+} -+ -+static irqreturn_t ar933x_uart_interrupt(int irq, void *dev_id) -+{ -+ struct ar933x_uart_port *up = dev_id; -+ unsigned int status; -+ -+ status = ar933x_uart_read(up, AR933X_UART_CS_REG); -+ if ((status & AR933X_UART_CS_HOST_INT) == 0) -+ return IRQ_NONE; -+ -+ spin_lock(&up->port.lock); -+ -+ status = ar933x_uart_read(up, AR933X_UART_INT_REG); -+ status &= ar933x_uart_read(up, AR933X_UART_INT_EN_REG); -+ -+ if (status & AR933X_UART_INT_RX_VALID) { -+ ar933x_uart_write(up, AR933X_UART_INT_REG, -+ AR933X_UART_INT_RX_VALID); -+ ar933x_uart_rx_chars(up); -+ } -+ -+ if (status & AR933X_UART_INT_TX_EMPTY) { -+ ar933x_uart_write(up, AR933X_UART_INT_REG, -+ AR933X_UART_INT_TX_EMPTY); -+ ar933x_uart_stop_tx_interrupt(up); -+ ar933x_uart_tx_chars(up); -+ } -+ -+ spin_unlock(&up->port.lock); -+ -+ return IRQ_HANDLED; -+} -+ -+static int ar933x_uart_startup(struct uart_port *port) -+{ -+ struct ar933x_uart_port *up = (struct ar933x_uart_port *) port; -+ unsigned long flags; -+ int ret; -+ -+ ret = request_irq(up->port.irq, ar933x_uart_interrupt, -+ up->port.irqflags, dev_name(up->port.dev), up); -+ if (ret) -+ return ret; -+ -+ spin_lock_irqsave(&up->port.lock, flags); -+ -+ /* Enable HOST interrupts */ -+ ar933x_uart_rmw_set(up, AR933X_UART_CS_REG, -+ AR933X_UART_CS_HOST_INT_EN); -+ -+ /* Enable RX interrupts */ -+ up->ier = AR933X_UART_INT_RX_VALID; -+ ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier); -+ -+ spin_unlock_irqrestore(&up->port.lock, flags); -+ -+ return 0; -+} -+ -+static void ar933x_uart_shutdown(struct uart_port *port) -+{ -+ struct ar933x_uart_port *up = (struct ar933x_uart_port *) port; -+ -+ /* Disable all interrupts */ -+ up->ier = 0; -+ ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier); -+ -+ /* Disable break condition */ -+ ar933x_uart_rmw_clear(up, AR933X_UART_CS_REG, -+ AR933X_UART_CS_TX_BREAK); -+ -+ free_irq(up->port.irq, up); -+} -+ -+static const char *ar933x_uart_type(struct uart_port *port) -+{ -+ return (port->type == PORT_AR933X) ? "AR933X UART" : NULL; -+} -+ -+static void ar933x_uart_release_port(struct uart_port *port) -+{ -+ /* Nothing to release ... */ -+} -+ -+static int ar933x_uart_request_port(struct uart_port *port) -+{ -+ /* UARTs always present */ -+ return 0; -+} -+ -+static void ar933x_uart_config_port(struct uart_port *port, int flags) -+{ -+ if (flags & UART_CONFIG_TYPE) -+ port->type = PORT_AR933X; -+} -+ -+static int ar933x_uart_verify_port(struct uart_port *port, -+ struct serial_struct *ser) -+{ -+ if (ser->type != PORT_UNKNOWN && -+ ser->type != PORT_AR933X) -+ return -EINVAL; -+ -+ if (ser->irq < 0 || ser->irq >= NR_IRQS) -+ return -EINVAL; -+ -+ if (ser->baud_base < 28800) -+ return -EINVAL; -+ -+ return 0; -+} -+ -+static struct uart_ops ar933x_uart_ops = { -+ .tx_empty = ar933x_uart_tx_empty, -+ .set_mctrl = ar933x_uart_set_mctrl, -+ .get_mctrl = ar933x_uart_get_mctrl, -+ .stop_tx = ar933x_uart_stop_tx, -+ .start_tx = ar933x_uart_start_tx, -+ .stop_rx = ar933x_uart_stop_rx, -+ .enable_ms = ar933x_uart_enable_ms, -+ .break_ctl = ar933x_uart_break_ctl, -+ .startup = ar933x_uart_startup, -+ .shutdown = ar933x_uart_shutdown, -+ .set_termios = ar933x_uart_set_termios, -+ .type = ar933x_uart_type, -+ .release_port = ar933x_uart_release_port, -+ .request_port = ar933x_uart_request_port, -+ .config_port = ar933x_uart_config_port, -+ .verify_port = ar933x_uart_verify_port, -+}; -+ -+#ifdef CONFIG_SERIAL_AR933X_CONSOLE -+ -+static struct ar933x_uart_port * -+ar933x_console_ports[CONFIG_SERIAL_AR933X_NR_UARTS]; -+ -+static void ar933x_uart_wait_xmitr(struct ar933x_uart_port *up) -+{ -+ unsigned int status; -+ unsigned int timeout = 60000; -+ -+ /* Wait up to 60ms for the character(s) to be sent. */ -+ do { -+ status = ar933x_uart_read(up, AR933X_UART_DATA_REG); -+ if (--timeout == 0) -+ break; -+ udelay(1); -+ } while ((status & AR933X_UART_DATA_TX_CSR) == 0); -+} -+ -+static void ar933x_uart_console_putchar(struct uart_port *port, int ch) -+{ -+ struct ar933x_uart_port *up = (struct ar933x_uart_port *) port; -+ -+ ar933x_uart_wait_xmitr(up); -+ ar933x_uart_putc(up, ch); -+} -+ -+static void ar933x_uart_console_write(struct console *co, const char *s, -+ unsigned int count) -+{ -+ struct ar933x_uart_port *up = ar933x_console_ports[co->index]; -+ unsigned long flags; -+ unsigned int int_en; -+ int locked = 1; -+ -+ local_irq_save(flags); -+ -+ if (up->port.sysrq) -+ locked = 0; -+ else if (oops_in_progress) -+ locked = spin_trylock(&up->port.lock); -+ else -+ spin_lock(&up->port.lock); -+ -+ /* -+ * First save the IER then disable the interrupts -+ */ -+ int_en = ar933x_uart_read(up, AR933X_UART_INT_EN_REG); -+ ar933x_uart_write(up, AR933X_UART_INT_EN_REG, 0); -+ -+ uart_console_write(&up->port, s, count, ar933x_uart_console_putchar); -+ -+ /* -+ * Finally, wait for transmitter to become empty -+ * and restore the IER -+ */ -+ ar933x_uart_wait_xmitr(up); -+ ar933x_uart_write(up, AR933X_UART_INT_EN_REG, int_en); -+ -+ ar933x_uart_write(up, AR933X_UART_INT_REG, AR933X_UART_INT_ALLINTS); -+ -+ if (locked) -+ spin_unlock(&up->port.lock); -+ -+ local_irq_restore(flags); -+} -+ -+static int ar933x_uart_console_setup(struct console *co, char *options) -+{ -+ struct ar933x_uart_port *up; -+ int baud = 115200; -+ int bits = 8; -+ int parity = 'n'; -+ int flow = 'n'; -+ -+ if (co->index < 0 || co->index >= CONFIG_SERIAL_AR933X_NR_UARTS) -+ return -EINVAL; -+ -+ up = ar933x_console_ports[co->index]; -+ if (!up) -+ return -ENODEV; -+ -+ if (options) -+ uart_parse_options(options, &baud, &parity, &bits, &flow); -+ -+ return uart_set_options(&up->port, co, baud, parity, bits, flow); -+} -+ -+static struct console ar933x_uart_console = { -+ .name = "ttyATH", -+ .write = ar933x_uart_console_write, -+ .device = uart_console_device, -+ .setup = ar933x_uart_console_setup, -+ .flags = CON_PRINTBUFFER, -+ .index = -1, -+ .data = &ar933x_uart_driver, -+}; -+ -+static void ar933x_uart_add_console_port(struct ar933x_uart_port *up) -+{ -+ ar933x_console_ports[up->port.line] = up; -+} -+ -+#define AR933X_SERIAL_CONSOLE (&ar933x_uart_console) -+ -+#else -+ -+static inline void ar933x_uart_add_console_port(struct ar933x_uart_port *up) {} -+ -+#define AR933X_SERIAL_CONSOLE NULL -+ -+#endif /* CONFIG_SERIAL_AR933X_CONSOLE */ -+ -+static struct uart_driver ar933x_uart_driver = { -+ .owner = THIS_MODULE, -+ .driver_name = DRIVER_NAME, -+ .dev_name = "ttyATH", -+ .nr = CONFIG_SERIAL_AR933X_NR_UARTS, -+ .cons = AR933X_SERIAL_CONSOLE, -+}; -+ -+static int __devinit ar933x_uart_probe(struct platform_device *pdev) -+{ -+ struct ar933x_uart_platform_data *pdata; -+ struct ar933x_uart_port *up; -+ struct uart_port *port; -+ struct resource *mem_res; -+ struct resource *irq_res; -+ int id; -+ int ret; -+ -+ pdata = pdev->dev.platform_data; -+ if (!pdata) -+ return -EINVAL; -+ -+ id = pdev->id; -+ if (id == -1) -+ id = 0; -+ -+ if (id > CONFIG_SERIAL_AR933X_NR_UARTS) -+ return -EINVAL; -+ -+ mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (!mem_res) { -+ dev_err(&pdev->dev, "no MEM resource\n"); -+ return -EINVAL; -+ } -+ -+ irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); -+ if (!irq_res) { -+ dev_err(&pdev->dev, "no IRQ resource\n"); -+ return -EINVAL; -+ } -+ -+ up = kzalloc(sizeof(struct ar933x_uart_port), GFP_KERNEL); -+ if (!up) -+ return -ENOMEM; -+ -+ port = &up->port; -+ port->mapbase = mem_res->start; -+ -+ port->membase = ioremap(mem_res->start, AR933X_UART_REGS_SIZE); -+ if (!port->membase) { -+ ret = -ENOMEM; -+ goto err_free_up; -+ } -+ -+ port->line = id; -+ port->irq = irq_res->start; -+ port->dev = &pdev->dev; -+ port->type = PORT_AR933X; -+ port->iotype = UPIO_MEM32; -+ port->uartclk = pdata->uartclk; -+ -+ port->regshift = 2; -+ port->fifosize = AR933X_UART_FIFO_SIZE; -+ port->ops = &ar933x_uart_ops; -+ -+ ar933x_uart_add_console_port(up); -+ -+ ret = uart_add_one_port(&ar933x_uart_driver, &up->port); -+ if (ret) -+ goto err_unmap; -+ -+ platform_set_drvdata(pdev, up); -+ return 0; -+ -+err_unmap: -+ iounmap(up->port.membase); -+err_free_up: -+ kfree(up); -+ return ret; -+} -+ -+static int __devexit ar933x_uart_remove(struct platform_device *pdev) -+{ -+ struct ar933x_uart_port *up; -+ -+ up = platform_get_drvdata(pdev); -+ platform_set_drvdata(pdev, NULL); -+ -+ if (up) { -+ uart_remove_one_port(&ar933x_uart_driver, &up->port); -+ iounmap(up->port.membase); -+ kfree(up); -+ } -+ -+ return 0; -+} -+ -+static struct platform_driver ar933x_uart_platform_driver = { -+ .probe = ar933x_uart_probe, -+ .remove = __devexit_p(ar933x_uart_remove), -+ .driver = { -+ .name = DRIVER_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init ar933x_uart_init(void) -+{ -+ int ret; -+ -+ ar933x_uart_driver.nr = CONFIG_SERIAL_AR933X_NR_UARTS; -+ ret = uart_register_driver(&ar933x_uart_driver); -+ if (ret) -+ goto err_out; -+ -+ ret = platform_driver_register(&ar933x_uart_platform_driver); -+ if (ret) -+ goto err_unregister_uart_driver; -+ -+ return 0; -+ -+err_unregister_uart_driver: -+ uart_unregister_driver(&ar933x_uart_driver); -+err_out: -+ return ret; -+} -+ -+static void __exit ar933x_uart_exit(void) -+{ -+ platform_driver_unregister(&ar933x_uart_platform_driver); -+ uart_unregister_driver(&ar933x_uart_driver); -+} -+ -+module_init(ar933x_uart_init); -+module_exit(ar933x_uart_exit); -+ -+MODULE_DESCRIPTION("Atheros AR933X UART driver"); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_LICENSE("GPL v2"); -+MODULE_ALIAS("platform:" DRIVER_NAME); -diff -Nur linux-2.6.39.orig/drivers/usb/host/Kconfig linux-2.6.39/drivers/usb/host/Kconfig ---- linux-2.6.39.orig/drivers/usb/host/Kconfig 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/drivers/usb/host/Kconfig 2011-08-24 18:17:24.000000000 +0200 -@@ -129,6 +129,13 @@ - config USB_FSL_MPH_DR_OF - tristate - -+config USB_EHCI_AR71XX -+ bool "USB EHCI support for AR71xx" -+ depends on USB_EHCI_HCD && ATHEROS_AR71XX -+ default y -+ help -+ Support for Atheros AR71xx built-in EHCI controller -+ - config USB_EHCI_FSL - bool "Support for Freescale on-chip EHCI USB controller" - depends on USB_EHCI_HCD && FSL_SOC -@@ -287,6 +294,13 @@ - Enables support for the on-chip OHCI controller on - OMAP3 and later chips. - -+config USB_OHCI_AR71XX -+ bool "USB OHCI support for Atheros AR71xx" -+ depends on USB_OHCI_HCD && ATHEROS_AR71XX -+ default y -+ help -+ Support for Atheros AR71xx built-in OHCI controller -+ - config USB_OHCI_HCD_PPC_SOC - bool "OHCI support for on-chip PPC USB controller" - depends on USB_OHCI_HCD && (STB03xxx || PPC_MPC52xx) -diff -Nur linux-2.6.39.orig/drivers/usb/host/ehci-ar71xx.c linux-2.6.39/drivers/usb/host/ehci-ar71xx.c ---- linux-2.6.39.orig/drivers/usb/host/ehci-ar71xx.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/drivers/usb/host/ehci-ar71xx.c 2011-08-24 18:17:24.000000000 +0200 -@@ -0,0 +1,242 @@ -+/* -+ * Bus Glue for Atheros AR71xx built-in EHCI controller. -+ * -+ * Copyright (C) 2008-2010 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * Copyright (C) 2007 Atheros Communications, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+extern int usb_disabled(void); -+ -+static int ehci_ar71xx_init(struct usb_hcd *hcd) -+{ -+ struct ehci_hcd *ehci = hcd_to_ehci(hcd); -+ int ret; -+ -+ ehci->caps = hcd->regs; -+ ehci->regs = hcd->regs + -+ HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); -+ ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); -+ -+ ehci->sbrn = 0x20; -+ ehci->has_synopsys_hc_bug = 1; -+ -+ ehci_reset(ehci); -+ -+ ret = ehci_init(hcd); -+ if (ret) -+ return ret; -+ -+ ehci_port_power(ehci, 0); -+ -+ return 0; -+} -+ -+static int ehci_ar91xx_init(struct usb_hcd *hcd) -+{ -+ struct ehci_hcd *ehci = hcd_to_ehci(hcd); -+ int ret; -+ -+ ehci->caps = hcd->regs + 0x100; -+ ehci->regs = hcd->regs + 0x100 + -+ HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); -+ ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); -+ -+ hcd->has_tt = 1; -+ ehci->sbrn = 0x20; -+ -+ ehci_reset(ehci); -+ -+ ret = ehci_init(hcd); -+ if (ret) -+ return ret; -+ -+ ehci_port_power(ehci, 0); -+ -+ return 0; -+} -+ -+static int ehci_ar71xx_probe(const struct hc_driver *driver, -+ struct usb_hcd **hcd_out, -+ struct platform_device *pdev) -+{ -+ struct usb_hcd *hcd; -+ struct resource *res; -+ int irq; -+ int ret; -+ -+ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); -+ if (!res) { -+ dev_dbg(&pdev->dev, "no IRQ specified for %s\n", -+ dev_name(&pdev->dev)); -+ return -ENODEV; -+ } -+ irq = res->start; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (!res) { -+ dev_dbg(&pdev->dev, "no base address specified for %s\n", -+ dev_name(&pdev->dev)); -+ return -ENODEV; -+ } -+ -+ hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev)); -+ if (!hcd) -+ return -ENOMEM; -+ -+ hcd->rsrc_start = res->start; -+ hcd->rsrc_len = res->end - res->start + 1; -+ -+ if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { -+ dev_dbg(&pdev->dev, "controller already in use\n"); -+ ret = -EBUSY; -+ goto err_put_hcd; -+ } -+ -+ hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); -+ if (!hcd->regs) { -+ dev_dbg(&pdev->dev, "error mapping memory\n"); -+ ret = -EFAULT; -+ goto err_release_region; -+ } -+ -+ ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED); -+ if (ret) -+ goto err_iounmap; -+ -+ return 0; -+ -+err_iounmap: -+ iounmap(hcd->regs); -+ -+err_release_region: -+ release_mem_region(hcd->rsrc_start, hcd->rsrc_len); -+err_put_hcd: -+ usb_put_hcd(hcd); -+ return ret; -+} -+ -+static void ehci_ar71xx_remove(struct usb_hcd *hcd, -+ struct platform_device *pdev) -+{ -+ usb_remove_hcd(hcd); -+ iounmap(hcd->regs); -+ release_mem_region(hcd->rsrc_start, hcd->rsrc_len); -+ usb_put_hcd(hcd); -+} -+ -+static const struct hc_driver ehci_ar71xx_hc_driver = { -+ .description = hcd_name, -+ .product_desc = "Atheros AR71xx built-in EHCI controller", -+ .hcd_priv_size = sizeof(struct ehci_hcd), -+ -+ .irq = ehci_irq, -+ .flags = HCD_MEMORY | HCD_USB2, -+ -+ .reset = ehci_ar71xx_init, -+ .start = ehci_run, -+ .stop = ehci_stop, -+ .shutdown = ehci_shutdown, -+ -+ .urb_enqueue = ehci_urb_enqueue, -+ .urb_dequeue = ehci_urb_dequeue, -+ .endpoint_disable = ehci_endpoint_disable, -+ .endpoint_reset = ehci_endpoint_reset, -+ -+ .get_frame_number = ehci_get_frame, -+ -+ .hub_status_data = ehci_hub_status_data, -+ .hub_control = ehci_hub_control, -+#ifdef CONFIG_PM -+ .hub_suspend = ehci_hub_suspend, -+ .hub_resume = ehci_hub_resume, -+#endif -+ .relinquish_port = ehci_relinquish_port, -+ .port_handed_over = ehci_port_handed_over, -+ -+ .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, -+}; -+ -+static const struct hc_driver ehci_ar91xx_hc_driver = { -+ .description = hcd_name, -+ .product_desc = "Atheros AR91xx built-in EHCI controller", -+ .hcd_priv_size = sizeof(struct ehci_hcd), -+ .irq = ehci_irq, -+ .flags = HCD_MEMORY | HCD_USB2, -+ -+ .reset = ehci_ar91xx_init, -+ .start = ehci_run, -+ .stop = ehci_stop, -+ .shutdown = ehci_shutdown, -+ -+ .urb_enqueue = ehci_urb_enqueue, -+ .urb_dequeue = ehci_urb_dequeue, -+ .endpoint_disable = ehci_endpoint_disable, -+ .endpoint_reset = ehci_endpoint_reset, -+ -+ .get_frame_number = ehci_get_frame, -+ -+ .hub_status_data = ehci_hub_status_data, -+ .hub_control = ehci_hub_control, -+#ifdef CONFIG_PM -+ .hub_suspend = ehci_hub_suspend, -+ .hub_resume = ehci_hub_resume, -+#endif -+ .relinquish_port = ehci_relinquish_port, -+ .port_handed_over = ehci_port_handed_over, -+ -+ .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, -+}; -+ -+static int ehci_ar71xx_driver_probe(struct platform_device *pdev) -+{ -+ struct ar71xx_ehci_platform_data *pdata; -+ struct usb_hcd *hcd = NULL; -+ int ret; -+ -+ if (usb_disabled()) -+ return -ENODEV; -+ -+ pdata = pdev->dev.platform_data; -+ if (!pdata) { -+ dev_err(&pdev->dev, "no platform data specified for %s\n", -+ dev_name(&pdev->dev)); -+ return -ENODEV; -+ } -+ -+ if (pdata->is_ar91xx) -+ ret = ehci_ar71xx_probe(&ehci_ar91xx_hc_driver, &hcd, pdev); -+ else -+ ret = ehci_ar71xx_probe(&ehci_ar71xx_hc_driver, &hcd, pdev); -+ -+ return ret; -+} -+ -+static int ehci_ar71xx_driver_remove(struct platform_device *pdev) -+{ -+ struct usb_hcd *hcd = platform_get_drvdata(pdev); -+ -+ ehci_ar71xx_remove(hcd, pdev); -+ return 0; -+} -+ -+MODULE_ALIAS("platform:ar71xx-ehci"); -+ -+static struct platform_driver ehci_ar71xx_driver = { -+ .probe = ehci_ar71xx_driver_probe, -+ .remove = ehci_ar71xx_driver_remove, -+ .driver = { -+ .name = "ar71xx-ehci", -+ } -+}; -diff -Nur linux-2.6.39.orig/drivers/usb/host/ehci-hcd.c linux-2.6.39/drivers/usb/host/ehci-hcd.c ---- linux-2.6.39.orig/drivers/usb/host/ehci-hcd.c 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/drivers/usb/host/ehci-hcd.c 2011-08-24 18:17:24.000000000 +0200 -@@ -1265,6 +1265,11 @@ - #define PLATFORM_DRIVER tegra_ehci_driver - #endif - -+#ifdef CONFIG_USB_EHCI_AR71XX -+#include "ehci-ar71xx.c" -+#define PLATFORM_DRIVER ehci_ar71xx_driver -+#endif -+ - #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ - !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \ - !defined(XILINX_OF_PLATFORM_DRIVER) -diff -Nur linux-2.6.39.orig/drivers/usb/host/ohci-ar71xx.c linux-2.6.39/drivers/usb/host/ohci-ar71xx.c ---- linux-2.6.39.orig/drivers/usb/host/ohci-ar71xx.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/drivers/usb/host/ohci-ar71xx.c 2011-08-24 18:17:24.000000000 +0200 -@@ -0,0 +1,165 @@ -+/* -+ * OHCI HCD (Host Controller Driver) for USB. -+ * -+ * Bus Glue for Atheros AR71xx built-in OHCI controller. -+ * -+ * Copyright (C) 2008 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * Copyright (C) 2007 Atheros Communications, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+extern int usb_disabled(void); -+ -+static int usb_hcd_ar71xx_probe(const struct hc_driver *driver, -+ struct platform_device *pdev) -+{ -+ struct usb_hcd *hcd; -+ struct resource *res; -+ int irq; -+ int ret; -+ -+ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); -+ if (!res) { -+ dev_dbg(&pdev->dev, "no IRQ specified for %s\n", -+ dev_name(&pdev->dev)); -+ return -ENODEV; -+ } -+ irq = res->start; -+ -+ hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev)); -+ if (!hcd) -+ return -ENOMEM; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (!res) { -+ dev_dbg(&pdev->dev, "no base address specified for %s\n", -+ dev_name(&pdev->dev)); -+ ret = -ENODEV; -+ goto err_put_hcd; -+ } -+ hcd->rsrc_start = res->start; -+ hcd->rsrc_len = res->end - res->start + 1; -+ -+ if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { -+ dev_dbg(&pdev->dev, "controller already in use\n"); -+ ret = -EBUSY; -+ goto err_put_hcd; -+ } -+ -+ hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); -+ if (!hcd->regs) { -+ dev_dbg(&pdev->dev, "error mapping memory\n"); -+ ret = -EFAULT; -+ goto err_release_region; -+ } -+ -+ ohci_hcd_init(hcd_to_ohci(hcd)); -+ -+ ret = usb_add_hcd(hcd, irq, IRQF_DISABLED); -+ if (ret) -+ goto err_stop_hcd; -+ -+ return 0; -+ -+err_stop_hcd: -+ iounmap(hcd->regs); -+err_release_region: -+ release_mem_region(hcd->rsrc_start, hcd->rsrc_len); -+err_put_hcd: -+ usb_put_hcd(hcd); -+ return ret; -+} -+ -+void usb_hcd_ar71xx_remove(struct usb_hcd *hcd, struct platform_device *pdev) -+{ -+ usb_remove_hcd(hcd); -+ iounmap(hcd->regs); -+ release_mem_region(hcd->rsrc_start, hcd->rsrc_len); -+ usb_put_hcd(hcd); -+} -+ -+static int __devinit ohci_ar71xx_start(struct usb_hcd *hcd) -+{ -+ struct ohci_hcd *ohci = hcd_to_ohci(hcd); -+ int ret; -+ -+ ret = ohci_init(ohci); -+ if (ret < 0) -+ return ret; -+ -+ ret = ohci_run(ohci); -+ if (ret < 0) -+ goto err; -+ -+ return 0; -+ -+err: -+ ohci_stop(hcd); -+ return ret; -+} -+ -+static const struct hc_driver ohci_ar71xx_hc_driver = { -+ .description = hcd_name, -+ .product_desc = "Atheros AR71xx built-in OHCI controller", -+ .hcd_priv_size = sizeof(struct ohci_hcd), -+ -+ .irq = ohci_irq, -+ .flags = HCD_USB11 | HCD_MEMORY, -+ -+ .start = ohci_ar71xx_start, -+ .stop = ohci_stop, -+ .shutdown = ohci_shutdown, -+ -+ .urb_enqueue = ohci_urb_enqueue, -+ .urb_dequeue = ohci_urb_dequeue, -+ .endpoint_disable = ohci_endpoint_disable, -+ -+ /* -+ * scheduling support -+ */ -+ .get_frame_number = ohci_get_frame, -+ -+ /* -+ * root hub support -+ */ -+ .hub_status_data = ohci_hub_status_data, -+ .hub_control = ohci_hub_control, -+ .start_port_reset = ohci_start_port_reset, -+}; -+ -+static int ohci_hcd_ar71xx_drv_probe(struct platform_device *pdev) -+{ -+ if (usb_disabled()) -+ return -ENODEV; -+ -+ return usb_hcd_ar71xx_probe(&ohci_ar71xx_hc_driver, pdev); -+} -+ -+static int ohci_hcd_ar71xx_drv_remove(struct platform_device *pdev) -+{ -+ struct usb_hcd *hcd = platform_get_drvdata(pdev); -+ -+ usb_hcd_ar71xx_remove(hcd, pdev); -+ return 0; -+} -+ -+MODULE_ALIAS("platform:ar71xx-ohci"); -+ -+static struct platform_driver ohci_hcd_ar71xx_driver = { -+ .probe = ohci_hcd_ar71xx_drv_probe, -+ .remove = ohci_hcd_ar71xx_drv_remove, -+ .shutdown = usb_hcd_platform_shutdown, -+ .driver = { -+ .name = "ar71xx-ohci", -+ .owner = THIS_MODULE, -+ }, -+}; -diff -Nur linux-2.6.39.orig/drivers/usb/host/ohci-hcd.c linux-2.6.39/drivers/usb/host/ohci-hcd.c ---- linux-2.6.39.orig/drivers/usb/host/ohci-hcd.c 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/drivers/usb/host/ohci-hcd.c 2011-08-24 18:17:24.000000000 +0200 -@@ -1105,6 +1105,11 @@ - #define PLATFORM_DRIVER ohci_hcd_cns3xxx_driver - #endif - -+#ifdef CONFIG_USB_OHCI_AR71XX -+#include "ohci-ar71xx.c" -+#define PLATFORM_DRIVER ohci_hcd_ar71xx_driver -+#endif -+ - #if !defined(PCI_DRIVER) && \ - !defined(PLATFORM_DRIVER) && \ - !defined(OMAP1_PLATFORM_DRIVER) && \ -diff -Nur linux-2.6.39.orig/drivers/watchdog/Kconfig linux-2.6.39/drivers/watchdog/Kconfig ---- linux-2.6.39.orig/drivers/watchdog/Kconfig 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/drivers/watchdog/Kconfig 2011-08-24 18:17:24.000000000 +0200 -@@ -990,6 +990,13 @@ - To compile this driver as a loadable module, choose M here. - The module will be called bcm63xx_wdt. - -+config AR71XX_WDT -+ tristate "Atheros AR71xx Watchdog Timer" -+ depends on ATHEROS_AR71XX -+ help -+ Hardware driver for the built-in watchdog timer on the Atheros -+ AR71xx SoCs. -+ - # PARISC Architecture - - # POWERPC Architecture -diff -Nur linux-2.6.39.orig/drivers/watchdog/Makefile linux-2.6.39/drivers/watchdog/Makefile ---- linux-2.6.39.orig/drivers/watchdog/Makefile 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/drivers/watchdog/Makefile 2011-08-24 18:17:24.000000000 +0200 -@@ -119,6 +119,7 @@ - obj-$(CONFIG_WDT_MTX1) += mtx-1_wdt.o - obj-$(CONFIG_PNX833X_WDT) += pnx833x_wdt.o - obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o -+obj-$(CONFIG_AR71XX_WDT) += ar71xx_wdt.o - obj-$(CONFIG_AR7_WDT) += ar7_wdt.o - obj-$(CONFIG_TXX9_WDT) += txx9wdt.o - obj-$(CONFIG_OCTEON_WDT) += octeon-wdt.o -diff -Nur linux-2.6.39.orig/drivers/watchdog/ar71xx_wdt.c linux-2.6.39/drivers/watchdog/ar71xx_wdt.c ---- linux-2.6.39.orig/drivers/watchdog/ar71xx_wdt.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/drivers/watchdog/ar71xx_wdt.c 2011-08-24 18:17:24.000000000 +0200 -@@ -0,0 +1,299 @@ -+/* -+ * Driver for the Atheros AR71xx SoC's built-in hardware watchdog timer. -+ * -+ * Copyright (C) 2010-2011 Jaiganesh Narayanan -+ * Copyright (C) 2008 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros 2.6.31 BSP -+ * -+ * This driver was based on: drivers/watchdog/ixp4xx_wdt.c -+ * Author: Deepak Saxena -+ * Copyright 2004 (c) MontaVista, Software, Inc. -+ * -+ * which again was based on sa1100 driver, -+ * Copyright (C) 2000 Oleg Drokin -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#define DRV_NAME "ar71xx-wdt" -+#define DRV_DESC "Atheros AR71xx hardware watchdog driver" -+#define DRV_VERSION "0.1.0" -+ -+#define WDT_TIMEOUT 15 /* seconds */ -+ -+static int nowayout = WATCHDOG_NOWAYOUT; -+ -+#ifdef CONFIG_WATCHDOG_NOWAYOUT -+module_param(nowayout, int, 0); -+MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started " -+ "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); -+#endif -+ -+static unsigned long wdt_flags; -+ -+#define WDT_FLAGS_BUSY 0 -+#define WDT_FLAGS_EXPECT_CLOSE 1 -+ -+static int wdt_timeout = WDT_TIMEOUT; -+static int boot_status; -+static int max_timeout; -+static u32 wdt_clk_freq; -+ -+static inline void ar71xx_wdt_keepalive(void) -+{ -+ ar71xx_reset_wr(AR71XX_RESET_REG_WDOG, wdt_clk_freq * wdt_timeout); -+} -+ -+static inline void ar71xx_wdt_enable(void) -+{ -+ printk(KERN_DEBUG DRV_NAME ": enabling watchdog timer\n"); -+ ar71xx_wdt_keepalive(); -+ udelay(2); -+ ar71xx_reset_wr(AR71XX_RESET_REG_WDOG_CTRL, WDOG_CTRL_ACTION_FCR); -+} -+ -+static inline void ar71xx_wdt_disable(void) -+{ -+ printk(KERN_DEBUG DRV_NAME ": disabling watchdog timer\n"); -+ ar71xx_reset_wr(AR71XX_RESET_REG_WDOG_CTRL, WDOG_CTRL_ACTION_NONE); -+} -+ -+static int ar71xx_wdt_set_timeout(int val) -+{ -+ if (val < 1 || val > max_timeout) -+ return -EINVAL; -+ -+ wdt_timeout = val; -+ ar71xx_wdt_keepalive(); -+ -+ printk(KERN_DEBUG DRV_NAME ": timeout=%d secs\n", wdt_timeout); -+ -+ return 0; -+} -+ -+static int ar71xx_wdt_open(struct inode *inode, struct file *file) -+{ -+ if (test_and_set_bit(WDT_FLAGS_BUSY, &wdt_flags)) -+ return -EBUSY; -+ -+ clear_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags); -+ -+ ar71xx_wdt_enable(); -+ -+ return nonseekable_open(inode, file); -+} -+ -+static int ar71xx_wdt_release(struct inode *inode, struct file *file) -+{ -+ if (test_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags)) { -+ ar71xx_wdt_disable(); -+ } else { -+ printk(KERN_CRIT DRV_NAME ": device closed unexpectedly, " -+ "watchdog timer will not stop!\n"); -+ } -+ -+ clear_bit(WDT_FLAGS_BUSY, &wdt_flags); -+ clear_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags); -+ -+ return 0; -+} -+ -+static ssize_t ar71xx_wdt_write(struct file *file, const char *data, -+ size_t len, loff_t *ppos) -+{ -+ if (len) { -+ if (!nowayout) { -+ size_t i; -+ -+ clear_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags); -+ -+ for (i = 0; i != len; i++) { -+ char c; -+ -+ if (get_user(c, data + i)) -+ return -EFAULT; -+ -+ if (c == 'V') -+ set_bit(WDT_FLAGS_EXPECT_CLOSE, -+ &wdt_flags); -+ } -+ } -+ -+ ar71xx_wdt_keepalive(); -+ } -+ -+ return len; -+} -+ -+static struct watchdog_info ar71xx_wdt_info = { -+ .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | -+ WDIOF_MAGICCLOSE | WDIOF_CARDRESET, -+ .firmware_version = 0, -+ .identity = "AR71XX watchdog", -+}; -+ -+static long ar71xx_wdt_ioctl(struct file *file, -+ unsigned int cmd, unsigned long arg) -+{ -+ int t; -+ int ret; -+ -+ switch (cmd) { -+ case WDIOC_GETSUPPORT: -+ ret = copy_to_user((struct watchdog_info *)arg, -+ &ar71xx_wdt_info, -+ sizeof(ar71xx_wdt_info)) ? -EFAULT : 0; -+ break; -+ -+ case WDIOC_GETSTATUS: -+ ret = put_user(0, (int *)arg) ? -EFAULT : 0; -+ break; -+ -+ case WDIOC_GETBOOTSTATUS: -+ ret = put_user(boot_status, (int *)arg) ? -EFAULT : 0; -+ break; -+ -+ case WDIOC_KEEPALIVE: -+ ar71xx_wdt_keepalive(); -+ ret = 0; -+ break; -+ -+ case WDIOC_SETTIMEOUT: -+ ret = get_user(t, (int *)arg) ? -EFAULT : 0; -+ if (ret) -+ break; -+ -+ ret = ar71xx_wdt_set_timeout(t); -+ if (ret) -+ break; -+ -+ /* fallthrough */ -+ case WDIOC_GETTIMEOUT: -+ ret = put_user(wdt_timeout, (int *)arg) ? -EFAULT : 0; -+ break; -+ -+ default: -+ ret = -ENOTTY; -+ break; -+ } -+ -+ return ret; -+} -+ -+static const struct file_operations ar71xx_wdt_fops = { -+ .owner = THIS_MODULE, -+ .write = ar71xx_wdt_write, -+ .unlocked_ioctl = ar71xx_wdt_ioctl, -+ .open = ar71xx_wdt_open, -+ .release = ar71xx_wdt_release, -+}; -+ -+static struct miscdevice ar71xx_wdt_miscdev = { -+ .minor = WATCHDOG_MINOR, -+ .name = "watchdog", -+ .fops = &ar71xx_wdt_fops, -+}; -+ -+static int __devinit ar71xx_wdt_probe(struct platform_device *pdev) -+{ -+ int ret; -+ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7130: -+ case AR71XX_SOC_AR7141: -+ case AR71XX_SOC_AR7161: -+ case AR71XX_SOC_AR7240: -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ case AR71XX_SOC_AR9130: -+ case AR71XX_SOC_AR9132: -+ wdt_clk_freq = ar71xx_ahb_freq; -+ break; -+ -+ case AR71XX_SOC_AR9330: -+ case AR71XX_SOC_AR9331: -+ case AR71XX_SOC_AR9341: -+ case AR71XX_SOC_AR9342: -+ case AR71XX_SOC_AR9344: -+ wdt_clk_freq = ar71xx_ref_freq; -+ break; -+ -+ default: -+ BUG(); -+ } -+ -+ max_timeout = (0xfffffffful / wdt_clk_freq); -+ wdt_timeout = (max_timeout < WDT_TIMEOUT) ? max_timeout : WDT_TIMEOUT; -+ -+ if (ar71xx_reset_rr(AR71XX_RESET_REG_WDOG_CTRL) & WDOG_CTRL_LAST_RESET) -+ boot_status = WDIOF_CARDRESET; -+ -+ ret = misc_register(&ar71xx_wdt_miscdev); -+ if (ret) -+ goto err_out; -+ -+ printk(KERN_INFO DRV_DESC " version " DRV_VERSION "\n"); -+ -+ printk(KERN_DEBUG DRV_NAME ": timeout=%d secs (max=%d)\n", -+ wdt_timeout, max_timeout); -+ -+ return 0; -+ -+err_out: -+ return ret; -+} -+ -+static int __devexit ar71xx_wdt_remove(struct platform_device *pdev) -+{ -+ misc_deregister(&ar71xx_wdt_miscdev); -+ return 0; -+} -+ -+static struct platform_driver ar71xx_wdt_driver = { -+ .probe = ar71xx_wdt_probe, -+ .remove = __devexit_p(ar71xx_wdt_remove), -+ .driver = { -+ .name = DRV_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init ar71xx_wdt_init(void) -+{ -+ return platform_driver_register(&ar71xx_wdt_driver); -+} -+module_init(ar71xx_wdt_init); -+ -+static void __exit ar71xx_wdt_exit(void) -+{ -+ platform_driver_unregister(&ar71xx_wdt_driver); -+} -+module_exit(ar71xx_wdt_exit); -+ -+MODULE_DESCRIPTION(DRV_DESC); -+MODULE_VERSION(DRV_VERSION); -+MODULE_AUTHOR("Gabor Juhos -diff -Nur linux-2.6.39.orig/include/linux/ipv6.h linux-2.6.39/include/linux/ipv6.h ---- linux-2.6.39.orig/include/linux/ipv6.h 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/include/linux/ipv6.h 2011-08-24 18:17:24.000000000 +0200 -@@ -126,7 +126,7 @@ - - struct in6_addr saddr; - struct in6_addr daddr; --}; -+} __packed; - - #ifdef __KERNEL__ - /* -diff -Nur linux-2.6.39.orig/include/linux/myloader.h linux-2.6.39/include/linux/myloader.h ---- linux-2.6.39.orig/include/linux/myloader.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/include/linux/myloader.h 2011-08-24 18:17:24.000000000 +0200 -@@ -0,0 +1,120 @@ -+/* -+ * Compex's MyLoader specific definitions -+ * -+ * Copyright (C) 2006-2008 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ */ -+ -+#ifndef _MYLOADER_H_ -+#define _MYLOADER_H_ -+ -+/* Myloader specific magic numbers */ -+#define MYLO_MAGIC_SYS_PARAMS 0x20021107 -+#define MYLO_MAGIC_PARTITIONS 0x20021103 -+#define MYLO_MAGIC_BOARD_PARAMS 0x20021103 -+ -+/* Vendor ID's (seems to be same as the PCI vendor ID's) */ -+#define VENID_COMPEX 0x11F6 -+ -+/* Devices based on the ADM5120 */ -+#define DEVID_COMPEX_NP27G 0x0078 -+#define DEVID_COMPEX_NP28G 0x044C -+#define DEVID_COMPEX_NP28GHS 0x044E -+#define DEVID_COMPEX_WP54Gv1C 0x0514 -+#define DEVID_COMPEX_WP54G 0x0515 -+#define DEVID_COMPEX_WP54AG 0x0546 -+#define DEVID_COMPEX_WPP54AG 0x0550 -+#define DEVID_COMPEX_WPP54G 0x0555 -+ -+/* Devices based on the Atheros AR2317 */ -+#define DEVID_COMPEX_NP25G 0x05E6 -+#define DEVID_COMPEX_WPE53G 0x05DC -+ -+/* Devices based on the Atheros AR71xx */ -+#define DEVID_COMPEX_WP543 0x0640 -+ -+/* Devices based on the IXP422 */ -+#define DEVID_COMPEX_WP18 0x047E -+#define DEVID_COMPEX_NP18A 0x0489 -+ -+/* Other devices */ -+#define DEVID_COMPEX_NP26G8M 0x03E8 -+#define DEVID_COMPEX_NP26G16M 0x03E9 -+ -+struct mylo_partition { -+ uint16_t flags; /* partition flags */ -+ uint16_t type; /* type of the partition */ -+ uint32_t addr; /* relative address of the partition from the -+ flash start */ -+ uint32_t size; /* size of the partition in bytes */ -+ uint32_t param; /* if this is the active partition, the -+ MyLoader load code to this address */ -+}; -+ -+#define PARTITION_FLAG_ACTIVE 0x8000 /* this is the active partition, -+ * MyLoader loads firmware from here */ -+#define PARTITION_FLAG_ISRAM 0x2000 /* FIXME: this is a RAM partition? */ -+#define PARTIIION_FLAG_RAMLOAD 0x1000 /* FIXME: load this partition into the RAM? */ -+#define PARTITION_FLAG_PRELOAD 0x0800 /* the partition data preloaded to RAM -+ * before decompression */ -+#define PARTITION_FLAG_LZMA 0x0100 /* partition data compressed by LZMA */ -+#define PARTITION_FLAG_HAVEHDR 0x0002 /* the partition data have a header */ -+ -+#define PARTITION_TYPE_FREE 0 -+#define PARTITION_TYPE_USED 1 -+ -+#define MYLO_MAX_PARTITIONS 8 /* maximum number of partitions in the -+ partition table */ -+ -+struct mylo_partition_table { -+ uint32_t magic; /* must be MYLO_MAGIC_PARTITIONS */ -+ uint32_t res0; /* unknown/unused */ -+ uint32_t res1; /* unknown/unused */ -+ uint32_t res2; /* unknown/unused */ -+ struct mylo_partition partitions[MYLO_MAX_PARTITIONS]; -+}; -+ -+struct mylo_partition_header { -+ uint32_t len; /* length of the partition data */ -+ uint32_t crc; /* CRC value of the partition data */ -+}; -+ -+struct mylo_system_params { -+ uint32_t magic; /* must be MYLO_MAGIC_SYS_PARAMS */ -+ uint32_t res0; -+ uint32_t res1; -+ uint32_t mylo_ver; -+ uint16_t vid; /* Vendor ID */ -+ uint16_t did; /* Device ID */ -+ uint16_t svid; /* Sub Vendor ID */ -+ uint16_t sdid; /* Sub Device ID */ -+ uint32_t rev; /* device revision */ -+ uint32_t fwhi; -+ uint32_t fwlo; -+ uint32_t tftp_addr; -+ uint32_t prog_start; -+ uint32_t flash_size; /* size of boot FLASH in bytes */ -+ uint32_t dram_size; /* size of onboard RAM in bytes */ -+}; -+ -+struct mylo_eth_addr { -+ uint8_t mac[6]; -+ uint8_t csum[2]; -+}; -+ -+#define MYLO_ETHADDR_COUNT 8 /* maximum number of ethernet address -+ in the board parameters */ -+ -+struct mylo_board_params { -+ uint32_t magic; /* must be MYLO_MAGIC_BOARD_PARAMS */ -+ uint32_t res0; -+ uint32_t res1; -+ uint32_t res2; -+ struct mylo_eth_addr addr[MYLO_ETHADDR_COUNT]; -+}; -+ -+#endif /* _MYLOADER_H_*/ -diff -Nur linux-2.6.39.orig/include/linux/netdevice.h linux-2.6.39/include/linux/netdevice.h ---- linux-2.6.39.orig/include/linux/netdevice.h 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/include/linux/netdevice.h 2011-08-24 18:17:24.000000000 +0200 -@@ -1182,6 +1182,7 @@ - void *ax25_ptr; /* AX.25 specific data */ - struct wireless_dev *ieee80211_ptr; /* IEEE 802.11 specific data, - assign before registering */ -+ void *phy_ptr; /* PHY device specific data */ - - /* - * Cache lines mostly used on receive path (including eth_type_trans()) -diff -Nur linux-2.6.39.orig/include/linux/nxp_74hc153.h linux-2.6.39/include/linux/nxp_74hc153.h ---- linux-2.6.39.orig/include/linux/nxp_74hc153.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/include/linux/nxp_74hc153.h 2011-08-24 18:17:24.000000000 +0200 -@@ -0,0 +1,24 @@ -+/* -+ * NXP 74HC153 - Dual 4-input multiplexer defines -+ * -+ * Copyright (C) 2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#ifndef _NXP_74HC153_H -+#define _NXP_74HC153_H -+ -+#define NXP_74HC153_DRIVER_NAME "nxp-74hc153" -+ -+struct nxp_74hc153_platform_data { -+ unsigned gpio_base; -+ unsigned gpio_pin_s0; -+ unsigned gpio_pin_s1; -+ unsigned gpio_pin_1y; -+ unsigned gpio_pin_2y; -+}; -+ -+#endif /* _NXP_74HC153_H */ -diff -Nur linux-2.6.39.orig/include/linux/phy.h linux-2.6.39/include/linux/phy.h ---- linux-2.6.39.orig/include/linux/phy.h 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/include/linux/phy.h 2011-08-24 18:17:24.000000000 +0200 -@@ -332,6 +332,20 @@ - void (*adjust_link)(struct net_device *dev); - - void (*adjust_state)(struct net_device *dev); -+ -+ /* -+ * By default these point to the original functions -+ * with the same name. adding them to the phy_device -+ * allows the phy driver to override them for packet -+ * mangling if the ethernet driver supports it -+ * This is required to support some really horrible -+ * switches such as the Marvell 88E6060 -+ */ -+ int (*netif_receive_skb)(struct sk_buff *skb); -+ int (*netif_rx)(struct sk_buff *skb); -+ -+ /* alignment offset for packets */ -+ int pkt_align; - }; - #define to_phy_device(d) container_of(d, struct phy_device, dev) - -@@ -508,6 +522,7 @@ - void phy_stop_machine(struct phy_device *phydev); - int phy_ethtool_sset(struct phy_device *phydev, struct ethtool_cmd *cmd); - int phy_ethtool_gset(struct phy_device *phydev, struct ethtool_cmd *cmd); -+int phy_ethtool_ioctl(struct phy_device *phydev, void *useraddr); - int phy_mii_ioctl(struct phy_device *phydev, - struct ifreq *ifr, int cmd); - int phy_start_interrupts(struct phy_device *phydev); -diff -Nur linux-2.6.39.orig/include/linux/spi/spi.h linux-2.6.39/include/linux/spi/spi.h ---- linux-2.6.39.orig/include/linux/spi/spi.h 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/include/linux/spi/spi.h 2011-08-24 18:17:24.000000000 +0200 -@@ -441,6 +441,8 @@ - dma_addr_t rx_dma; - - unsigned cs_change:1; -+ unsigned verify:1; -+ unsigned fast_write:1; - u8 bits_per_word; - u16 delay_usecs; - u32 speed_hz; -@@ -482,6 +484,7 @@ - struct spi_device *spi; - - unsigned is_dma_mapped:1; -+ unsigned fast_read:1; - - /* REVISIT: we might want a flag affecting the behavior of the - * last transfer ... allowing things like "read 16 bit length L" -diff -Nur linux-2.6.39.orig/include/linux/spi/vsc7385.h linux-2.6.39/include/linux/spi/vsc7385.h ---- linux-2.6.39.orig/include/linux/spi/vsc7385.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/include/linux/spi/vsc7385.h 2011-08-24 18:17:24.000000000 +0200 -@@ -0,0 +1,19 @@ -+/* -+ * Platform data definition for the Vitesse VSC7385 ethernet switch driver -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+struct vsc7385_platform_data { -+ void (*reset)(void); -+ char *ucode_name; -+ struct { -+ u32 tx_ipg:5; -+ u32 bit2:1; -+ u32 clk_sel:3; -+ } mac_cfg; -+}; -diff -Nur linux-2.6.39.orig/include/linux/switch.h linux-2.6.39/include/linux/switch.h ---- linux-2.6.39.orig/include/linux/switch.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/include/linux/switch.h 2011-08-24 18:17:24.000000000 +0200 -@@ -0,0 +1,204 @@ -+/* -+ * switch.h: Switch configuration API -+ * -+ * Copyright (C) 2008 Felix Fietkau -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#ifndef __LINUX_SWITCH_H -+#define __LINUX_SWITCH_H -+ -+#include -+#include -+#include -+#include -+#ifndef __KERNEL__ -+#include -+#include -+#include -+#else -+#include -+#endif -+ -+/* main attributes */ -+enum { -+ SWITCH_ATTR_UNSPEC, -+ /* global */ -+ SWITCH_ATTR_TYPE, -+ /* device */ -+ SWITCH_ATTR_ID, -+ SWITCH_ATTR_DEV_NAME, -+ SWITCH_ATTR_ALIAS, -+ SWITCH_ATTR_NAME, -+ SWITCH_ATTR_VLANS, -+ SWITCH_ATTR_PORTS, -+ SWITCH_ATTR_CPU_PORT, -+ /* attributes */ -+ SWITCH_ATTR_OP_ID, -+ SWITCH_ATTR_OP_TYPE, -+ SWITCH_ATTR_OP_NAME, -+ SWITCH_ATTR_OP_PORT, -+ SWITCH_ATTR_OP_VLAN, -+ SWITCH_ATTR_OP_VALUE_INT, -+ SWITCH_ATTR_OP_VALUE_STR, -+ SWITCH_ATTR_OP_VALUE_PORTS, -+ SWITCH_ATTR_OP_DESCRIPTION, -+ /* port lists */ -+ SWITCH_ATTR_PORT, -+ SWITCH_ATTR_MAX -+}; -+ -+/* commands */ -+enum { -+ SWITCH_CMD_UNSPEC, -+ SWITCH_CMD_GET_SWITCH, -+ SWITCH_CMD_NEW_ATTR, -+ SWITCH_CMD_LIST_GLOBAL, -+ SWITCH_CMD_GET_GLOBAL, -+ SWITCH_CMD_SET_GLOBAL, -+ SWITCH_CMD_LIST_PORT, -+ SWITCH_CMD_GET_PORT, -+ SWITCH_CMD_SET_PORT, -+ SWITCH_CMD_LIST_VLAN, -+ SWITCH_CMD_GET_VLAN, -+ SWITCH_CMD_SET_VLAN -+}; -+ -+/* data types */ -+enum switch_val_type { -+ SWITCH_TYPE_UNSPEC, -+ SWITCH_TYPE_INT, -+ SWITCH_TYPE_STRING, -+ SWITCH_TYPE_PORTS, -+ SWITCH_TYPE_NOVAL, -+}; -+ -+/* port nested attributes */ -+enum { -+ SWITCH_PORT_UNSPEC, -+ SWITCH_PORT_ID, -+ SWITCH_PORT_FLAG_TAGGED, -+ SWITCH_PORT_ATTR_MAX -+}; -+ -+#define SWITCH_ATTR_DEFAULTS_OFFSET 0x1000 -+ -+#ifdef __KERNEL__ -+ -+struct switch_dev; -+struct switch_op; -+struct switch_val; -+struct switch_attr; -+struct switch_attrlist; -+ -+int register_switch(struct switch_dev *dev, struct net_device *netdev); -+void unregister_switch(struct switch_dev *dev); -+ -+/** -+ * struct switch_attrlist - attribute list -+ * -+ * @n_attr: number of attributes -+ * @attr: pointer to the attributes array -+ */ -+struct switch_attrlist { -+ int n_attr; -+ const struct switch_attr *attr; -+}; -+ -+/** -+ * struct switch_dev_ops - switch driver operations -+ * -+ * @attr_global: global switch attribute list -+ * @attr_port: port attribute list -+ * @attr_vlan: vlan attribute list -+ * -+ * Callbacks: -+ * -+ * @get_vlan_ports: read the port list of a VLAN -+ * @set_vlan_ports: set the port list of a VLAN -+ * -+ * @get_port_pvid: get the primary VLAN ID of a port -+ * @set_port_pvid: set the primary VLAN ID of a port -+ * -+ * @apply_config: apply all changed settings to the switch -+ * @reset_switch: resetting the switch -+ */ -+struct switch_dev_ops { -+ struct switch_attrlist attr_global, attr_port, attr_vlan; -+ -+ int (*get_vlan_ports)(struct switch_dev *dev, struct switch_val *val); -+ int (*set_vlan_ports)(struct switch_dev *dev, struct switch_val *val); -+ -+ int (*get_port_pvid)(struct switch_dev *dev, int port, int *val); -+ int (*set_port_pvid)(struct switch_dev *dev, int port, int val); -+ -+ int (*apply_config)(struct switch_dev *dev); -+ int (*reset_switch)(struct switch_dev *dev); -+}; -+ -+struct switch_dev { -+ const struct switch_dev_ops *ops; -+ /* will be automatically filled */ -+ char devname[IFNAMSIZ]; -+ -+ const char *name; -+ /* NB: either alias or netdev must be set */ -+ const char *alias; -+ struct net_device *netdev; -+ -+ int ports; -+ int vlans; -+ int cpu_port; -+ -+ /* the following fields are internal for swconfig */ -+ int id; -+ struct list_head dev_list; -+ unsigned long def_global, def_port, def_vlan; -+ -+ spinlock_t lock; -+ struct switch_port *portbuf; -+}; -+ -+struct switch_port { -+ u32 id; -+ u32 flags; -+}; -+ -+struct switch_val { -+ const struct switch_attr *attr; -+ int port_vlan; -+ int len; -+ union { -+ const char *s; -+ u32 i; -+ struct switch_port *ports; -+ } value; -+}; -+ -+struct switch_attr { -+ int disabled; -+ int type; -+ const char *name; -+ const char *description; -+ -+ int (*set)(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val); -+ int (*get)(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val); -+ -+ /* for driver internal use */ -+ int id; -+ int ofs; -+ int max; -+}; -+ -+#endif -+ -+#endif -diff -Nur linux-2.6.39.orig/include/linux/tcp.h linux-2.6.39/include/linux/tcp.h ---- linux-2.6.39.orig/include/linux/tcp.h 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/include/linux/tcp.h 2011-08-24 18:17:24.000000000 +0200 -@@ -54,7 +54,7 @@ - __be16 window; - __sum16 check; - __be16 urg_ptr; --}; -+} __packed; - - /* - * The union cast uses a gcc extension to avoid aliasing problems -diff -Nur linux-2.6.39.orig/include/linux/udp.h linux-2.6.39/include/linux/udp.h ---- linux-2.6.39.orig/include/linux/udp.h 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/include/linux/udp.h 2011-08-24 18:17:24.000000000 +0200 -@@ -24,7 +24,7 @@ - __be16 dest; - __be16 len; - __sum16 check; --}; -+} __packed; - - /* UDP socket options */ - #define UDP_CORK 1 /* Never send partially complete segments */ -diff -Nur linux-2.6.39.orig/net/dsa/mv88e6063.c linux-2.6.39/net/dsa/mv88e6063.c ---- linux-2.6.39.orig/net/dsa/mv88e6063.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39/net/dsa/mv88e6063.c 2011-08-24 18:17:24.000000000 +0200 -@@ -0,0 +1,294 @@ -+/* -+ * net/dsa/mv88e6063.c - Driver for Marvell 88e6063 switch chips -+ * Copyright (c) 2009 Gabor Juhos -+ * -+ * This driver was base on: net/dsa/mv88e6060.c -+ * net/dsa/mv88e6063.c - Driver for Marvell 88e6060 switch chips -+ * Copyright (c) 2008-2009 Marvell Semiconductor -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ */ -+ -+#include -+#include -+#include -+#include "dsa_priv.h" -+ -+#define REG_BASE 0x10 -+#define REG_PHY(p) (REG_BASE + (p)) -+#define REG_PORT(p) (REG_BASE + 8 + (p)) -+#define REG_GLOBAL (REG_BASE + 0x0f) -+#define NUM_PORTS 7 -+ -+static int reg_read(struct dsa_switch *ds, int addr, int reg) -+{ -+ return mdiobus_read(ds->master_mii_bus, addr, reg); -+} -+ -+#define REG_READ(addr, reg) \ -+ ({ \ -+ int __ret; \ -+ \ -+ __ret = reg_read(ds, addr, reg); \ -+ if (__ret < 0) \ -+ return __ret; \ -+ __ret; \ -+ }) -+ -+ -+static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val) -+{ -+ return mdiobus_write(ds->master_mii_bus, addr, reg, val); -+} -+ -+#define REG_WRITE(addr, reg, val) \ -+ ({ \ -+ int __ret; \ -+ \ -+ __ret = reg_write(ds, addr, reg, val); \ -+ if (__ret < 0) \ -+ return __ret; \ -+ }) -+ -+static char *mv88e6063_probe(struct mii_bus *bus, int sw_addr) -+{ -+ int ret; -+ -+ ret = mdiobus_read(bus, REG_PORT(0), 0x03); -+ if (ret >= 0) { -+ ret &= 0xfff0; -+ if (ret == 0x1530) -+ return "Marvell 88E6063"; -+ } -+ -+ return NULL; -+} -+ -+static int mv88e6063_switch_reset(struct dsa_switch *ds) -+{ -+ int i; -+ int ret; -+ -+ /* -+ * Set all ports to the disabled state. -+ */ -+ for (i = 0; i < NUM_PORTS; i++) { -+ ret = REG_READ(REG_PORT(i), 0x04); -+ REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc); -+ } -+ -+ /* -+ * Wait for transmit queues to drain. -+ */ -+ msleep(2); -+ -+ /* -+ * Reset the switch. -+ */ -+ REG_WRITE(REG_GLOBAL, 0x0a, 0xa130); -+ -+ /* -+ * Wait up to one second for reset to complete. -+ */ -+ for (i = 0; i < 1000; i++) { -+ ret = REG_READ(REG_GLOBAL, 0x00); -+ if ((ret & 0x8000) == 0x0000) -+ break; -+ -+ msleep(1); -+ } -+ if (i == 1000) -+ return -ETIMEDOUT; -+ -+ return 0; -+} -+ -+static int mv88e6063_setup_global(struct dsa_switch *ds) -+{ -+ /* -+ * Disable discarding of frames with excessive collisions, -+ * set the maximum frame size to 1536 bytes, and mask all -+ * interrupt sources. -+ */ -+ REG_WRITE(REG_GLOBAL, 0x04, 0x0800); -+ -+ /* -+ * Enable automatic address learning, set the address -+ * database size to 1024 entries, and set the default aging -+ * time to 5 minutes. -+ */ -+ REG_WRITE(REG_GLOBAL, 0x0a, 0x2130); -+ -+ return 0; -+} -+ -+static int mv88e6063_setup_port(struct dsa_switch *ds, int p) -+{ -+ int addr = REG_PORT(p); -+ -+ /* -+ * Do not force flow control, disable Ingress and Egress -+ * Header tagging, disable VLAN tunneling, and set the port -+ * state to Forwarding. Additionally, if this is the CPU -+ * port, enable Ingress and Egress Trailer tagging mode. -+ */ -+ REG_WRITE(addr, 0x04, dsa_is_cpu_port(ds, p) ? 0x4103 : 0x0003); -+ -+ /* -+ * Port based VLAN map: give each port its own address -+ * database, allow the CPU port to talk to each of the 'real' -+ * ports, and allow each of the 'real' ports to only talk to -+ * the CPU port. -+ */ -+ REG_WRITE(addr, 0x06, -+ ((p & 0xf) << 12) | -+ (dsa_is_cpu_port(ds, p) ? -+ ds->phys_port_mask : -+ (1 << ds->dst->cpu_port))); -+ -+ /* -+ * Port Association Vector: when learning source addresses -+ * of packets, add the address to the address database using -+ * a port bitmap that has only the bit for this port set and -+ * the other bits clear. -+ */ -+ REG_WRITE(addr, 0x0b, 1 << p); -+ -+ return 0; -+} -+ -+static int mv88e6063_setup(struct dsa_switch *ds) -+{ -+ int i; -+ int ret; -+ -+ ret = mv88e6063_switch_reset(ds); -+ if (ret < 0) -+ return ret; -+ -+ /* @@@ initialise atu */ -+ -+ ret = mv88e6063_setup_global(ds); -+ if (ret < 0) -+ return ret; -+ -+ for (i = 0; i < NUM_PORTS; i++) { -+ ret = mv88e6063_setup_port(ds, i); -+ if (ret < 0) -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static int mv88e6063_set_addr(struct dsa_switch *ds, u8 *addr) -+{ -+ REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) | addr[1]); -+ REG_WRITE(REG_GLOBAL, 0x02, (addr[2] << 8) | addr[3]); -+ REG_WRITE(REG_GLOBAL, 0x03, (addr[4] << 8) | addr[5]); -+ -+ return 0; -+} -+ -+static int mv88e6063_port_to_phy_addr(int port) -+{ -+ if (port >= 0 && port <= NUM_PORTS) -+ return REG_PHY(port); -+ return -1; -+} -+ -+static int mv88e6063_phy_read(struct dsa_switch *ds, int port, int regnum) -+{ -+ int addr; -+ -+ addr = mv88e6063_port_to_phy_addr(port); -+ if (addr == -1) -+ return 0xffff; -+ -+ return reg_read(ds, addr, regnum); -+} -+ -+static int -+mv88e6063_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val) -+{ -+ int addr; -+ -+ addr = mv88e6063_port_to_phy_addr(port); -+ if (addr == -1) -+ return 0xffff; -+ -+ return reg_write(ds, addr, regnum, val); -+} -+ -+static void mv88e6063_poll_link(struct dsa_switch *ds) -+{ -+ int i; -+ -+ for (i = 0; i < DSA_MAX_PORTS; i++) { -+ struct net_device *dev; -+ int uninitialized_var(port_status); -+ int link; -+ int speed; -+ int duplex; -+ int fc; -+ -+ dev = ds->ports[i]; -+ if (dev == NULL) -+ continue; -+ -+ link = 0; -+ if (dev->flags & IFF_UP) { -+ port_status = reg_read(ds, REG_PORT(i), 0x00); -+ if (port_status < 0) -+ continue; -+ -+ link = !!(port_status & 0x1000); -+ } -+ -+ if (!link) { -+ if (netif_carrier_ok(dev)) { -+ printk(KERN_INFO "%s: link down\n", dev->name); -+ netif_carrier_off(dev); -+ } -+ continue; -+ } -+ -+ speed = (port_status & 0x0100) ? 100 : 10; -+ duplex = (port_status & 0x0200) ? 1 : 0; -+ fc = ((port_status & 0xc000) == 0xc000) ? 1 : 0; -+ -+ if (!netif_carrier_ok(dev)) { -+ printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, " -+ "flow control %sabled\n", dev->name, -+ speed, duplex ? "full" : "half", -+ fc ? "en" : "dis"); -+ netif_carrier_on(dev); -+ } -+ } -+} -+ -+static struct dsa_switch_driver mv88e6063_switch_driver = { -+ .tag_protocol = htons(ETH_P_TRAILER), -+ .probe = mv88e6063_probe, -+ .setup = mv88e6063_setup, -+ .set_addr = mv88e6063_set_addr, -+ .phy_read = mv88e6063_phy_read, -+ .phy_write = mv88e6063_phy_write, -+ .poll_link = mv88e6063_poll_link, -+}; -+ -+static int __init mv88e6063_init(void) -+{ -+ register_switch_driver(&mv88e6063_switch_driver); -+ return 0; -+} -+module_init(mv88e6063_init); -+ -+static void __exit mv88e6063_cleanup(void) -+{ -+ unregister_switch_driver(&mv88e6063_switch_driver); -+} -+module_exit(mv88e6063_cleanup); -diff -Nur linux-2.6.39.orig/net/ipv4/netfilter/nf_conntrack_l3proto_ipv4.c linux-2.6.39/net/ipv4/netfilter/nf_conntrack_l3proto_ipv4.c ---- linux-2.6.39.orig/net/ipv4/netfilter/nf_conntrack_l3proto_ipv4.c 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/net/ipv4/netfilter/nf_conntrack_l3proto_ipv4.c 2011-08-24 18:17:24.000000000 +0200 -@@ -14,6 +14,7 @@ - #include - #include - #include -+#include - #include - #include - -@@ -44,8 +45,8 @@ - if (ap == NULL) - return false; - -- tuple->src.u3.ip = ap[0]; -- tuple->dst.u3.ip = ap[1]; -+ tuple->src.u3.ip = __get_unaligned_cpu32(ap++); -+ tuple->dst.u3.ip = __get_unaligned_cpu32(ap); - - return true; - } diff --git a/target/linux/patches/2.6.39/sparc-include.patch b/target/linux/patches/2.6.39/sparc-include.patch deleted file mode 100644 index 2f8ffd061..000000000 --- a/target/linux/patches/2.6.39/sparc-include.patch +++ /dev/null @@ -1,11 +0,0 @@ -diff -Nur linux-2.6.39-rc7.orig/arch/sparc/boot/btfixupprep.c linux-2.6.39-rc7/arch/sparc/boot/btfixupprep.c ---- linux-2.6.39-rc7.orig/arch/sparc/boot/btfixupprep.c 2011-05-10 04:33:54.000000000 +0200 -+++ linux-2.6.39-rc7/arch/sparc/boot/btfixupprep.c 2011-05-21 13:34:40.000000000 +0200 -@@ -25,7 +25,6 @@ - #include - #include - #include --#include - - #define MAXSYMS 1024 - diff --git a/target/linux/patches/2.6.39/startup.patch b/target/linux/patches/2.6.39/startup.patch deleted file mode 100644 index 68e8987b0..000000000 --- a/target/linux/patches/2.6.39/startup.patch +++ /dev/null @@ -1,20 +0,0 @@ -diff -Nur linux-2.6.34.orig/init/main.c linux-2.6.34/init/main.c ---- linux-2.6.34.orig/init/main.c 2010-05-16 23:17:36.000000000 +0200 -+++ linux-2.6.34/init/main.c 2010-05-20 20:13:26.321613615 +0200 -@@ -842,6 +842,7 @@ - printk(KERN_WARNING "Failed to execute %s. Attempting " - "defaults...\n", execute_command); - } -+ run_init_process("/init"); - run_init_process("/sbin/init"); - run_init_process("/etc/init"); - run_init_process("/bin/init"); -@@ -889,6 +890,8 @@ - if (sys_open((const char __user *) "/dev/console", O_RDWR, 0) < 0) - printk(KERN_WARNING "Warning: unable to open an initial console.\n"); - -+ printk(KERN_WARNING "Starting Linux (built with OpenADK).\n"); -+ - (void) sys_dup(0); - (void) sys_dup(0); - /* diff --git a/target/linux/patches/2.6.39/usb-defaults-off.patch b/target/linux/patches/2.6.39/usb-defaults-off.patch deleted file mode 100644 index 31367108a..000000000 --- a/target/linux/patches/2.6.39/usb-defaults-off.patch +++ /dev/null @@ -1,32 +0,0 @@ -diff -Nur linux-2.6.37.orig//drivers/usb/core/Kconfig linux-2.6.37/drivers/usb/core/Kconfig ---- linux-2.6.37.orig//drivers/usb/core/Kconfig 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/usb/core/Kconfig 2011-04-12 19:04:23.000000000 +0200 -@@ -59,7 +59,7 @@ - config USB_DEVICE_CLASS - bool "USB device class-devices (DEPRECATED)" - depends on USB -- default y -+ default n - ---help--- - Userspace access to USB devices is granted by device-nodes exported - directly from the usbdev in sysfs. Old versions of the driver -diff -Nur linux-2.6.37.orig//drivers/usb/host/Kconfig linux-2.6.37/drivers/usb/host/Kconfig ---- linux-2.6.37.orig//drivers/usb/host/Kconfig 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/usb/host/Kconfig 2011-04-12 19:04:48.000000000 +0200 -@@ -62,6 +62,7 @@ - config USB_EHCI_ROOT_HUB_TT - bool "Root Hub Transaction Translators" - depends on USB_EHCI_HCD -+ default n - ---help--- - Some EHCI chips have vendor-specific extensions to integrate - transaction translators, so that no OHCI or UHCI companion -@@ -74,7 +75,7 @@ - config USB_EHCI_TT_NEWSCHED - bool "Improved Transaction Translator scheduling" - depends on USB_EHCI_HCD -- default y -+ default n - ---help--- - This changes the periodic scheduling code to fill more of the low - and full speed bandwidth available from the Transaction Translator diff --git a/target/linux/patches/2.6.39/uuid.patch b/target/linux/patches/2.6.39/uuid.patch deleted file mode 100644 index 2529fdab5..000000000 --- a/target/linux/patches/2.6.39/uuid.patch +++ /dev/null @@ -1,255 +0,0 @@ -diff -Nur linux-2.6.38.4.orig/block/genhd.c linux-2.6.38.4/block/genhd.c ---- linux-2.6.38.4.orig/block/genhd.c 2011-04-21 23:34:46.000000000 +0200 -+++ linux-2.6.38.4/block/genhd.c 2011-04-27 19:21:18.668912036 +0200 -@@ -34,7 +34,7 @@ - static DEFINE_MUTEX(ext_devt_mutex); - static DEFINE_IDR(ext_devt_idr); - --static struct device_type disk_type; -+struct device_type disk_type; - - static void disk_add_events(struct gendisk *disk); - static void disk_del_events(struct gendisk *disk); -@@ -1118,7 +1118,7 @@ - return NULL; - } - --static struct device_type disk_type = { -+struct device_type disk_type = { - .name = "disk", - .groups = disk_attr_groups, - .release = disk_release, -diff -Nur linux-2.6.38.4.orig/init/do_mounts.c linux-2.6.38.4/init/do_mounts.c ---- linux-2.6.38.4.orig/init/do_mounts.c 2011-04-21 23:34:46.000000000 +0200 -+++ linux-2.6.38.4/init/do_mounts.c 2011-04-27 19:26:52.721413000 +0200 -@@ -32,6 +32,132 @@ - - dev_t ROOT_DEV; - -+#ifdef CONFIG_EXT2_FS -+/* support for root=UUID=ce40d6b2-18eb-4a75-aefe-7ddb0995ce63 bootargs */ -+ -+#include -+ -+__u8 root_dev_uuid[16]; -+int root_dev_type; /* 0 = normal (/dev/hda1, 0301); 1 = UUID; 3 = bad */ -+ -+/* imported from block/genhd.c after removing its static qualifier */ -+extern struct device_type disk_type; -+ -+/* helper function */ -+static __u8 __init fromhex(char c) -+{ -+ if (c >= '0' && c <= '9') -+ return (c - '0'); -+ c &= ~32; -+ if (c >= 'A' && c <= 'F') -+ return (c - 'A' + 10); -+ return (0xFF); -+} -+ -+static void __init parse_uuid(const char *s) -+{ -+ int i; -+ __u8 j, k; -+ -+ if (strlen(s) != 36 || s[8] != '-' || s[13] != '-' || -+ s[18] != '-' || s[23] != '-') -+ goto bad_uuid; -+ for (i = 0; i < 16; i++) { -+ if (*s == '-') -+ ++s; -+ j = fromhex(*s++); -+ k = fromhex(*s++); -+ if (j == 0xFF || k == 0xFF) -+ goto bad_uuid; -+ root_dev_uuid[i] = (j << 4) | k; -+ } -+ return; -+ bad_uuid: -+ /* we cannot panic here, defer */ -+ root_dev_type = 3; -+} -+ -+/* from drivers/md/md.c */ -+static void __init initcode_bi_complete(struct bio *bio, int error) -+{ -+ complete((struct completion*)bio->bi_private); -+} -+ -+static int __init initcode_sync_page_read(struct block_device *bdev, -+ sector_t sector, int size, struct page *page) -+{ -+ struct bio *bio = bio_alloc(GFP_NOIO, 1); -+ struct completion event; -+ int ret, rw = READ; -+ -+ rw |= REQ_SYNC; -+ -+ bio->bi_bdev = bdev; -+ bio->bi_sector = sector; -+ bio_add_page(bio, page, size, 0); -+ init_completion(&event); -+ bio->bi_private = &event; -+ bio->bi_end_io = initcode_bi_complete; -+ submit_bio(rw, bio); -+ wait_for_completion(&event); -+ -+ ret = test_bit(BIO_UPTODATE, &bio->bi_flags); -+ bio_put(bio); -+ /* 0 = failure */ -+ return ret; -+} -+ -+/* most of this taken from fs/ext2/super.c */ -+static int __init check_dev(struct gendisk *thedisk, dev_t devt, -+ int blocksize, struct page *page) -+{ -+ struct ext2_super_block * es; -+ struct block_device *bdev; -+ unsigned long sb_block = 1; -+ unsigned long logic_sb_block; -+ unsigned long offset = 0; -+ int rv = /* not found */ 0; -+ char bff[22]; -+ -+ bdev = bdget(devt); -+ if (blkdev_get(bdev, FMODE_READ, NULL)) { -+ printk(KERN_ERR "VFS: opening block device %s failed!\n", -+ format_dev_t(bff, devt)); -+ return (0); -+ } -+ -+ if (blocksize != BLOCK_SIZE) { -+ logic_sb_block = (sb_block*BLOCK_SIZE) / blocksize; -+ offset = (sb_block*BLOCK_SIZE) % blocksize; -+ } else { -+ logic_sb_block = sb_block; -+ } -+ -+// printk(KERN_ERR "D: attempting to read %d @%lu from " -+// "bdev %p devt %08X %s\n", blocksize, logic_sb_block, -+// bdev, devt, format_dev_t(bff, devt)); -+ if (!initcode_sync_page_read(bdev, logic_sb_block, blocksize, page)) { -+// printk(KERN_ERR "D: failed!\n"); -+ goto out; -+ } -+ es = (struct ext2_super_block *)(((char *)page_address(page)) + offset); -+ if (le16_to_cpu(es->s_magic) == EXT2_SUPER_MAGIC) { -+// printk(KERN_ERR "D: has uuid " -+// "%02X%02X%02X%02X-%02X%02X-%02X%02X-%02X%02X-%02X%02X%02X%02X%02X%02X\n", -+// es->s_uuid[0], es->s_uuid[1], es->s_uuid[2], es->s_uuid[3], -+// es->s_uuid[4], es->s_uuid[5], es->s_uuid[6], es->s_uuid[7], -+// es->s_uuid[8], es->s_uuid[9], es->s_uuid[10], es->s_uuid[11], -+// es->s_uuid[12], es->s_uuid[13], es->s_uuid[14], es->s_uuid[15]); -+ if (!memcmp(es->s_uuid, root_dev_uuid, 16)) -+ rv = /* found */ 1; -+ } -+// else printk(KERN_ERR "D: bad ext2fs magic\n"); -+ out: -+ blkdev_put(bdev, FMODE_READ); -+ return (rv); -+} -+#endif /* CONFIG_EXT2_FS for UUID support */ -+ - static int __init load_ramdisk(char *str) - { - rd_doload = simple_strtol(str,NULL,0) & 3; -@@ -218,6 +344,13 @@ - static int __init root_dev_setup(char *line) - { - strlcpy(saved_root_name, line, sizeof(saved_root_name)); -+#ifdef CONFIG_EXT2_FS -+ root_dev_type = 0; -+ if (!strncmp(line, "UUID=", 5)) { -+ root_dev_type = 1; -+ parse_uuid(line + 5); -+ } -+#endif /* CONFIG_EXT2_FS for UUID support */ - return 1; - } - -@@ -403,6 +536,83 @@ - - void __init mount_root(void) - { -+#ifdef CONFIG_EXT2_FS -+ /* UUID support */ -+// printk_all_partitions(); -+ if (root_dev_type == 1) { -+ int blocksize; -+ -+ /* from block/genhd.c printk_all_partitions */ -+ struct class_dev_iter iter; -+ struct device *dev; -+ -+ /* from drivers/md/md.c */ -+ struct page *sb_page; -+ -+ if (!(sb_page = alloc_page(GFP_KERNEL))) { -+ printk(KERN_ERR "VFS: no memory for bio page\n"); -+ goto nomemforbio; -+ } -+ -+// printk(KERN_ERR "D: root is: " -+// "%02X%02X%02X%02X-%02X%02X-%02X%02X-%02X%02X-%02X%02X%02X%02X%02X%02X\n", -+// root_dev_uuid[0], root_dev_uuid[1], root_dev_uuid[2], root_dev_uuid[3], -+// root_dev_uuid[4], root_dev_uuid[5], root_dev_uuid[6], root_dev_uuid[7], -+// root_dev_uuid[8], root_dev_uuid[9], root_dev_uuid[10], root_dev_uuid[11], -+// root_dev_uuid[12], root_dev_uuid[13], root_dev_uuid[14], root_dev_uuid[15]); -+ /* from block/genhd.c printk_all_partitions */ -+// printk(KERN_ERR "D: begin iter\n"); -+ class_dev_iter_init(&iter, &block_class, NULL, &disk_type); -+ while (root_dev_type && (dev = class_dev_iter_next(&iter))) { -+// char bff[22]; -+ struct gendisk *disk = dev_to_disk(dev); -+ struct disk_part_iter piter; -+ struct hd_struct *part; -+ if (get_capacity(disk) == 0 || -+ (disk->flags & GENHD_FL_SUPPRESS_PARTITION_INFO)) { -+// printk(KERN_ERR "D: ignoring\n"); -+ continue; -+ } -+ blocksize = queue_logical_block_size(disk->queue); -+// printk(KERN_ERR "D: gendisk, blocksize %d " -+// "name '%s' devt %08X %s #part %d\n", blocksize, -+// disk->disk_name, dev->devt, -+// format_dev_t(bff, dev->devt), -+// disk_max_parts(disk)); -+ disk_part_iter_init(&piter, disk, DISK_PITER_INCL_PART0); -+ while (root_dev_type && (part = disk_part_iter_next(&piter))) { -+ /* avoid empty or too small partitions */ -+// printk(KERN_ERR "D: part #%d start %llu " -+// "nr %llu\n", part->partno, -+// (__u64)part->start_sect, -+// (__u64)part->nr_sects); -+ if (part->nr_sects < 8) -+ continue; -+ if (check_dev(disk, MKDEV(MAJOR(dev->devt), -+ MINOR(dev->devt) + part->partno), -+ blocksize, sb_page)) { -+ ROOT_DEV = part_devt(part); -+// printk(KERN_ERR "D: got match!\n"); -+ // comment out below for debugging -+ root_dev_type = 0; -+ } -+ } -+ disk_part_iter_exit(&piter); -+ } -+// printk(KERN_ERR "D: end iter\n"); -+ class_dev_iter_exit(&iter); -+ put_page(sb_page); -+ } -+ nomemforbio: -+ if (root_dev_type == 1) -+ printk(KERN_ERR "VFS: Unable to find root by UUID %s.\n", -+ saved_root_name + 5); -+ else if (root_dev_type == 3) -+ /* execute deferred panic from parse_uuid */ -+ panic("Badly formatted UUID %s was supplied as kernel " -+ "parameter root", saved_root_name + 5); -+#endif /* CONFIG_EXT2_FS for UUID support */ -+ - #ifdef CONFIG_ROOT_NFS - if (MAJOR(ROOT_DEV) == UNNAMED_MAJOR) { - if (mount_nfs_root()) diff --git a/target/linux/patches/2.6.39/vga-cons-default-off.patch b/target/linux/patches/2.6.39/vga-cons-default-off.patch deleted file mode 100644 index 178aeeeb9..000000000 --- a/target/linux/patches/2.6.39/vga-cons-default-off.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff -Nur linux-2.6.37.orig//drivers/video/console/Kconfig linux-2.6.37/drivers/video/console/Kconfig ---- linux-2.6.37.orig//drivers/video/console/Kconfig 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/video/console/Kconfig 2011-04-12 16:29:34.000000000 +0200 -@@ -7,7 +7,7 @@ - config VGA_CONSOLE - bool "VGA text console" if EMBEDDED || !X86 - depends on !4xx && !8xx && !SPARC && !M68K && !PARISC && !FRV && !SUPERH && !BLACKFIN && !AVR32 && !MN10300 && (!ARM || ARCH_FOOTBRIDGE || ARCH_INTEGRATOR || ARCH_NETWINDER) -- default y -+ default n - help - Saying Y here will allow you to use Linux in text mode through a - display that complies with the generic VGA standard. Virtually diff --git a/target/linux/patches/2.6.39/wlan-cf.patch b/target/linux/patches/2.6.39/wlan-cf.patch deleted file mode 100644 index fc20759e2..000000000 --- a/target/linux/patches/2.6.39/wlan-cf.patch +++ /dev/null @@ -1,11 +0,0 @@ -diff -Nur linux-2.6.39.orig/drivers/net/wireless/hostap/hostap_cs.c linux-2.6.39/drivers/net/wireless/hostap/hostap_cs.c ---- linux-2.6.39.orig/drivers/net/wireless/hostap/hostap_cs.c 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/drivers/net/wireless/hostap/hostap_cs.c 2011-09-12 02:46:26.987984145 +0200 -@@ -623,6 +623,7 @@ - static struct pcmcia_device_id hostap_cs_ids[] = { - PCMCIA_DEVICE_MANF_CARD(0x000b, 0x7100), - PCMCIA_DEVICE_MANF_CARD(0x000b, 0x7300), -+ PCMCIA_DEVICE_MANF_CARD(0x0004, 0x2003), - PCMCIA_DEVICE_MANF_CARD(0x0101, 0x0777), - PCMCIA_DEVICE_MANF_CARD(0x0126, 0x8000), - PCMCIA_DEVICE_MANF_CARD(0x0138, 0x0002), diff --git a/target/linux/patches/2.6.39/x86-build.patch b/target/linux/patches/2.6.39/x86-build.patch deleted file mode 100644 index 339140f41..000000000 --- a/target/linux/patches/2.6.39/x86-build.patch +++ /dev/null @@ -1,11 +0,0 @@ -diff -Nur linux-2.6.39-rc6.orig/arch/x86/boot/tools/build.c linux-2.6.39-rc6/arch/x86/boot/tools/build.c ---- linux-2.6.39-rc6.orig/arch/x86/boot/tools/build.c 2011-05-04 04:59:13.000000000 +0200 -+++ linux-2.6.39-rc6/arch/x86/boot/tools/build.c 2011-05-05 20:10:07.000000000 +0200 -@@ -29,7 +29,6 @@ - #include - #include - #include --#include - #include - #include - #include diff --git a/target/linux/patches/2.6.39/zlib-inflate.patch b/target/linux/patches/2.6.39/zlib-inflate.patch deleted file mode 100644 index 58e1f6d21..000000000 --- a/target/linux/patches/2.6.39/zlib-inflate.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff -Nur linux-2.6.37.orig/lib/Kconfig linux-2.6.37/lib/Kconfig ---- linux-2.6.37.orig/lib/Kconfig 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/lib/Kconfig 2011-03-01 20:10:29.833370667 +0100 -@@ -95,7 +95,7 @@ - # compression support is select'ed if needed - # - config ZLIB_INFLATE -- tristate -+ boolean - - config ZLIB_DEFLATE - tristate diff --git a/target/linux/patches/3.0.4/bsd-compatibility.patch b/target/linux/patches/3.0.4/bsd-compatibility.patch deleted file mode 100644 index 9e91a62de..000000000 --- a/target/linux/patches/3.0.4/bsd-compatibility.patch +++ /dev/null @@ -1,2512 +0,0 @@ -diff -Nur linux-2.6.36.orig/scripts/Makefile.lib linux-2.6.36/scripts/Makefile.lib ---- linux-2.6.36.orig/scripts/Makefile.lib 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/scripts/Makefile.lib 2010-11-28 18:34:22.000000000 +0100 -@@ -216,7 +216,12 @@ - size_append = printf $(shell \ - dec_size=0; \ - for F in $1; do \ -- fsize=$$(stat -c "%s" $$F); \ -+ if stat -qs .>/dev/null 2>&1; then \ -+ statcmd='stat -f %z'; \ -+ else \ -+ statcmd='stat -c %s'; \ -+ fi; \ -+ fsize=$$($$statcmd $$F); \ - dec_size=$$(expr $$dec_size + $$fsize); \ - done; \ - printf "%08x\n" $$dec_size | \ -diff -Nur linux-2.6.36.orig/scripts/mod/mk_elfconfig.c linux-2.6.36/scripts/mod/mk_elfconfig.c ---- linux-2.6.36.orig/scripts/mod/mk_elfconfig.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/scripts/mod/mk_elfconfig.c 2010-11-28 18:33:24.000000000 +0100 -@@ -1,7 +1,18 @@ - #include - #include - #include --#include -+ -+#define EI_NIDENT (16) -+#define ELFMAG "\177ELF" -+ -+#define SELFMAG 4 -+#define EI_CLASS 4 -+#define ELFCLASS32 1 /* 32-bit objects */ -+#define ELFCLASS64 2 /* 64-bit objects */ -+ -+#define EI_DATA 5 /* Data encoding byte index */ -+#define ELFDATA2LSB 1 /* 2's complement, little endian */ -+#define ELFDATA2MSB 2 /* 2's complement, big endian */ - - int - main(int argc, char **argv) -diff -Nur linux-2.6.36.orig/scripts/mod/modpost.h linux-2.6.36/scripts/mod/modpost.h ---- linux-2.6.36.orig/scripts/mod/modpost.h 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/scripts/mod/modpost.h 2010-11-28 18:33:24.000000000 +0100 -@@ -7,7 +7,2453 @@ - #include - #include - #include --#include -+ -+ -+/* This file defines standard ELF types, structures, and macros. -+ Copyright (C) 1995-1999,2000,2001,2002,2003 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#ifndef _ELF_H -+#define _ELF_H 1 -+ -+__BEGIN_DECLS -+ -+/* Standard ELF types. */ -+ -+#include -+ -+/* Type for a 16-bit quantity. */ -+typedef uint16_t Elf32_Half; -+typedef uint16_t Elf64_Half; -+ -+/* Types for signed and unsigned 32-bit quantities. */ -+typedef uint32_t Elf32_Word; -+typedef int32_t Elf32_Sword; -+typedef uint32_t Elf64_Word; -+typedef int32_t Elf64_Sword; -+ -+/* Types for signed and unsigned 64-bit quantities. */ -+typedef uint64_t Elf32_Xword; -+typedef int64_t Elf32_Sxword; -+typedef uint64_t Elf64_Xword; -+typedef int64_t Elf64_Sxword; -+ -+/* Type of addresses. */ -+typedef uint32_t Elf32_Addr; -+typedef uint64_t Elf64_Addr; -+ -+/* Type of file offsets. */ -+typedef uint32_t Elf32_Off; -+typedef uint64_t Elf64_Off; -+ -+/* Type for section indices, which are 16-bit quantities. */ -+typedef uint16_t Elf32_Section; -+typedef uint16_t Elf64_Section; -+ -+/* Type for version symbol information. */ -+typedef Elf32_Half Elf32_Versym; -+typedef Elf64_Half Elf64_Versym; -+ -+ -+/* The ELF file header. This appears at the start of every ELF file. */ -+ -+#define EI_NIDENT (16) -+ -+typedef struct -+{ -+ unsigned char e_ident[EI_NIDENT]; /* Magic number and other info */ -+ Elf32_Half e_type; /* Object file type */ -+ Elf32_Half e_machine; /* Architecture */ -+ Elf32_Word e_version; /* Object file version */ -+ Elf32_Addr e_entry; /* Entry point virtual address */ -+ Elf32_Off e_phoff; /* Program header table file offset */ -+ Elf32_Off e_shoff; /* Section header table file offset */ -+ Elf32_Word e_flags; /* Processor-specific flags */ -+ Elf32_Half e_ehsize; /* ELF header size in bytes */ -+ Elf32_Half e_phentsize; /* Program header table entry size */ -+ Elf32_Half e_phnum; /* Program header table entry count */ -+ Elf32_Half e_shentsize; /* Section header table entry size */ -+ Elf32_Half e_shnum; /* Section header table entry count */ -+ Elf32_Half e_shstrndx; /* Section header string table index */ -+} Elf32_Ehdr; -+ -+typedef struct -+{ -+ unsigned char e_ident[EI_NIDENT]; /* Magic number and other info */ -+ Elf64_Half e_type; /* Object file type */ -+ Elf64_Half e_machine; /* Architecture */ -+ Elf64_Word e_version; /* Object file version */ -+ Elf64_Addr e_entry; /* Entry point virtual address */ -+ Elf64_Off e_phoff; /* Program header table file offset */ -+ Elf64_Off e_shoff; /* Section header table file offset */ -+ Elf64_Word e_flags; /* Processor-specific flags */ -+ Elf64_Half e_ehsize; /* ELF header size in bytes */ -+ Elf64_Half e_phentsize; /* Program header table entry size */ -+ Elf64_Half e_phnum; /* Program header table entry count */ -+ Elf64_Half e_shentsize; /* Section header table entry size */ -+ Elf64_Half e_shnum; /* Section header table entry count */ -+ Elf64_Half e_shstrndx; /* Section header string table index */ -+} Elf64_Ehdr; -+ -+/* Fields in the e_ident array. The EI_* macros are indices into the -+ array. The macros under each EI_* macro are the values the byte -+ may have. */ -+ -+#define EI_MAG0 0 /* File identification byte 0 index */ -+#define ELFMAG0 0x7f /* Magic number byte 0 */ -+ -+#define EI_MAG1 1 /* File identification byte 1 index */ -+#define ELFMAG1 'E' /* Magic number byte 1 */ -+ -+#define EI_MAG2 2 /* File identification byte 2 index */ -+#define ELFMAG2 'L' /* Magic number byte 2 */ -+ -+#define EI_MAG3 3 /* File identification byte 3 index */ -+#define ELFMAG3 'F' /* Magic number byte 3 */ -+ -+/* Conglomeration of the identification bytes, for easy testing as a word. */ -+#define ELFMAG "\177ELF" -+#define SELFMAG 4 -+ -+#define EI_CLASS 4 /* File class byte index */ -+#define ELFCLASSNONE 0 /* Invalid class */ -+#define ELFCLASS32 1 /* 32-bit objects */ -+#define ELFCLASS64 2 /* 64-bit objects */ -+#define ELFCLASSNUM 3 -+ -+#define EI_DATA 5 /* Data encoding byte index */ -+#define ELFDATANONE 0 /* Invalid data encoding */ -+#define ELFDATA2LSB 1 /* 2's complement, little endian */ -+#define ELFDATA2MSB 2 /* 2's complement, big endian */ -+#define ELFDATANUM 3 -+ -+#define EI_VERSION 6 /* File version byte index */ -+ /* Value must be EV_CURRENT */ -+ -+#define EI_OSABI 7 /* OS ABI identification */ -+#define ELFOSABI_NONE 0 /* UNIX System V ABI */ -+#define ELFOSABI_SYSV 0 /* Alias. */ -+#define ELFOSABI_HPUX 1 /* HP-UX */ -+#define ELFOSABI_NETBSD 2 /* NetBSD. */ -+#define ELFOSABI_LINUX 3 /* Linux. */ -+#define ELFOSABI_SOLARIS 6 /* Sun Solaris. */ -+#define ELFOSABI_AIX 7 /* IBM AIX. */ -+#define ELFOSABI_IRIX 8 /* SGI Irix. */ -+#define ELFOSABI_FREEBSD 9 /* FreeBSD. */ -+#define ELFOSABI_TRU64 10 /* Compaq TRU64 UNIX. */ -+#define ELFOSABI_MODESTO 11 /* Novell Modesto. */ -+#define ELFOSABI_OPENBSD 12 /* OpenBSD. */ -+#define ELFOSABI_ARM 97 /* ARM */ -+#define ELFOSABI_STANDALONE 255 /* Standalone (embedded) application */ -+ -+#define EI_ABIVERSION 8 /* ABI version */ -+ -+#define EI_PAD 9 /* Byte index of padding bytes */ -+ -+/* Legal values for e_type (object file type). */ -+ -+#define ET_NONE 0 /* No file type */ -+#define ET_REL 1 /* Relocatable file */ -+#define ET_EXEC 2 /* Executable file */ -+#define ET_DYN 3 /* Shared object file */ -+#define ET_CORE 4 /* Core file */ -+#define ET_NUM 5 /* Number of defined types */ -+#define ET_LOOS 0xfe00 /* OS-specific range start */ -+#define ET_HIOS 0xfeff /* OS-specific range end */ -+#define ET_LOPROC 0xff00 /* Processor-specific range start */ -+#define ET_HIPROC 0xffff /* Processor-specific range end */ -+ -+/* Legal values for e_machine (architecture). */ -+ -+#define EM_NONE 0 /* No machine */ -+#define EM_M32 1 /* AT&T WE 32100 */ -+#define EM_SPARC 2 /* SUN SPARC */ -+#define EM_386 3 /* Intel 80386 */ -+#define EM_68K 4 /* Motorola m68k family */ -+#define EM_88K 5 /* Motorola m88k family */ -+#define EM_860 7 /* Intel 80860 */ -+#define EM_MIPS 8 /* MIPS R3000 big-endian */ -+#define EM_S370 9 /* IBM System/370 */ -+#define EM_MIPS_RS3_LE 10 /* MIPS R3000 little-endian */ -+ -+#define EM_PARISC 15 /* HPPA */ -+#define EM_VPP500 17 /* Fujitsu VPP500 */ -+#define EM_SPARC32PLUS 18 /* Sun's "v8plus" */ -+#define EM_960 19 /* Intel 80960 */ -+#define EM_PPC 20 /* PowerPC */ -+#define EM_PPC64 21 /* PowerPC 64-bit */ -+#define EM_S390 22 /* IBM S390 */ -+ -+#define EM_V800 36 /* NEC V800 series */ -+#define EM_FR20 37 /* Fujitsu FR20 */ -+#define EM_RH32 38 /* TRW RH-32 */ -+#define EM_RCE 39 /* Motorola RCE */ -+#define EM_ARM 40 /* ARM */ -+#define EM_FAKE_ALPHA 41 /* Digital Alpha */ -+#define EM_SH 42 /* Hitachi SH */ -+#define EM_SPARCV9 43 /* SPARC v9 64-bit */ -+#define EM_TRICORE 44 /* Siemens Tricore */ -+#define EM_ARC 45 /* Argonaut RISC Core */ -+#define EM_H8_300 46 /* Hitachi H8/300 */ -+#define EM_H8_300H 47 /* Hitachi H8/300H */ -+#define EM_H8S 48 /* Hitachi H8S */ -+#define EM_H8_500 49 /* Hitachi H8/500 */ -+#define EM_IA_64 50 /* Intel Merced */ -+#define EM_MIPS_X 51 /* Stanford MIPS-X */ -+#define EM_COLDFIRE 52 /* Motorola Coldfire */ -+#define EM_68HC12 53 /* Motorola M68HC12 */ -+#define EM_MMA 54 /* Fujitsu MMA Multimedia Accelerator*/ -+#define EM_PCP 55 /* Siemens PCP */ -+#define EM_NCPU 56 /* Sony nCPU embeeded RISC */ -+#define EM_NDR1 57 /* Denso NDR1 microprocessor */ -+#define EM_STARCORE 58 /* Motorola Start*Core processor */ -+#define EM_ME16 59 /* Toyota ME16 processor */ -+#define EM_ST100 60 /* STMicroelectronic ST100 processor */ -+#define EM_TINYJ 61 /* Advanced Logic Corp. Tinyj emb.fam*/ -+#define EM_X86_64 62 /* AMD x86-64 architecture */ -+#define EM_PDSP 63 /* Sony DSP Processor */ -+ -+#define EM_FX66 66 /* Siemens FX66 microcontroller */ -+#define EM_ST9PLUS 67 /* STMicroelectronics ST9+ 8/16 mc */ -+#define EM_ST7 68 /* STmicroelectronics ST7 8 bit mc */ -+#define EM_68HC16 69 /* Motorola MC68HC16 microcontroller */ -+#define EM_68HC11 70 /* Motorola MC68HC11 microcontroller */ -+#define EM_68HC08 71 /* Motorola MC68HC08 microcontroller */ -+#define EM_68HC05 72 /* Motorola MC68HC05 microcontroller */ -+#define EM_SVX 73 /* Silicon Graphics SVx */ -+#define EM_ST19 74 /* STMicroelectronics ST19 8 bit mc */ -+#define EM_VAX 75 /* Digital VAX */ -+#define EM_CRIS 76 /* Axis Communications 32-bit embedded processor */ -+#define EM_JAVELIN 77 /* Infineon Technologies 32-bit embedded processor */ -+#define EM_FIREPATH 78 /* Element 14 64-bit DSP Processor */ -+#define EM_ZSP 79 /* LSI Logic 16-bit DSP Processor */ -+#define EM_MMIX 80 /* Donald Knuth's educational 64-bit processor */ -+#define EM_HUANY 81 /* Harvard University machine-independent object files */ -+#define EM_PRISM 82 /* SiTera Prism */ -+#define EM_AVR 83 /* Atmel AVR 8-bit microcontroller */ -+#define EM_FR30 84 /* Fujitsu FR30 */ -+#define EM_D10V 85 /* Mitsubishi D10V */ -+#define EM_D30V 86 /* Mitsubishi D30V */ -+#define EM_V850 87 /* NEC v850 */ -+#define EM_M32R 88 /* Mitsubishi M32R */ -+#define EM_MN10300 89 /* Matsushita MN10300 */ -+#define EM_MN10200 90 /* Matsushita MN10200 */ -+#define EM_PJ 91 /* picoJava */ -+#define EM_OPENRISC 92 /* OpenRISC 32-bit embedded processor */ -+#define EM_ARC_A5 93 /* ARC Cores Tangent-A5 */ -+#define EM_XTENSA 94 /* Tensilica Xtensa Architecture */ -+#define EM_NUM 95 -+ -+/* If it is necessary to assign new unofficial EM_* values, please -+ pick large random numbers (0x8523, 0xa7f2, etc.) to minimize the -+ chances of collision with official or non-GNU unofficial values. */ -+ -+#define EM_ALPHA 0x9026 -+ -+/* Legal values for e_version (version). */ -+ -+#define EV_NONE 0 /* Invalid ELF version */ -+#define EV_CURRENT 1 /* Current version */ -+#define EV_NUM 2 -+ -+/* Section header. */ -+ -+typedef struct -+{ -+ Elf32_Word sh_name; /* Section name (string tbl index) */ -+ Elf32_Word sh_type; /* Section type */ -+ Elf32_Word sh_flags; /* Section flags */ -+ Elf32_Addr sh_addr; /* Section virtual addr at execution */ -+ Elf32_Off sh_offset; /* Section file offset */ -+ Elf32_Word sh_size; /* Section size in bytes */ -+ Elf32_Word sh_link; /* Link to another section */ -+ Elf32_Word sh_info; /* Additional section information */ -+ Elf32_Word sh_addralign; /* Section alignment */ -+ Elf32_Word sh_entsize; /* Entry size if section holds table */ -+} Elf32_Shdr; -+ -+typedef struct -+{ -+ Elf64_Word sh_name; /* Section name (string tbl index) */ -+ Elf64_Word sh_type; /* Section type */ -+ Elf64_Xword sh_flags; /* Section flags */ -+ Elf64_Addr sh_addr; /* Section virtual addr at execution */ -+ Elf64_Off sh_offset; /* Section file offset */ -+ Elf64_Xword sh_size; /* Section size in bytes */ -+ Elf64_Word sh_link; /* Link to another section */ -+ Elf64_Word sh_info; /* Additional section information */ -+ Elf64_Xword sh_addralign; /* Section alignment */ -+ Elf64_Xword sh_entsize; /* Entry size if section holds table */ -+} Elf64_Shdr; -+ -+/* Special section indices. */ -+ -+#define SHN_UNDEF 0 /* Undefined section */ -+#define SHN_LORESERVE 0xff00 /* Start of reserved indices */ -+#define SHN_LOPROC 0xff00 /* Start of processor-specific */ -+#define SHN_HIPROC 0xff1f /* End of processor-specific */ -+#define SHN_LOOS 0xff20 /* Start of OS-specific */ -+#define SHN_HIOS 0xff3f /* End of OS-specific */ -+#define SHN_ABS 0xfff1 /* Associated symbol is absolute */ -+#define SHN_COMMON 0xfff2 /* Associated symbol is common */ -+#define SHN_XINDEX 0xffff /* Index is in extra table. */ -+#define SHN_HIRESERVE 0xffff /* End of reserved indices */ -+ -+/* Legal values for sh_type (section type). */ -+ -+#define SHT_NULL 0 /* Section header table entry unused */ -+#define SHT_PROGBITS 1 /* Program data */ -+#define SHT_SYMTAB 2 /* Symbol table */ -+#define SHT_STRTAB 3 /* String table */ -+#define SHT_RELA 4 /* Relocation entries with addends */ -+#define SHT_HASH 5 /* Symbol hash table */ -+#define SHT_DYNAMIC 6 /* Dynamic linking information */ -+#define SHT_NOTE 7 /* Notes */ -+#define SHT_NOBITS 8 /* Program space with no data (bss) */ -+#define SHT_REL 9 /* Relocation entries, no addends */ -+#define SHT_SHLIB 10 /* Reserved */ -+#define SHT_DYNSYM 11 /* Dynamic linker symbol table */ -+#define SHT_INIT_ARRAY 14 /* Array of constructors */ -+#define SHT_FINI_ARRAY 15 /* Array of destructors */ -+#define SHT_PREINIT_ARRAY 16 /* Array of pre-constructors */ -+#define SHT_GROUP 17 /* Section group */ -+#define SHT_SYMTAB_SHNDX 18 /* Extended section indeces */ -+#define SHT_NUM 19 /* Number of defined types. */ -+#define SHT_LOOS 0x60000000 /* Start OS-specific */ -+#define SHT_GNU_LIBLIST 0x6ffffff7 /* Prelink library list */ -+#define SHT_CHECKSUM 0x6ffffff8 /* Checksum for DSO content. */ -+#define SHT_LOSUNW 0x6ffffffa /* Sun-specific low bound. */ -+#define SHT_SUNW_move 0x6ffffffa -+#define SHT_SUNW_COMDAT 0x6ffffffb -+#define SHT_SUNW_syminfo 0x6ffffffc -+#define SHT_GNU_verdef 0x6ffffffd /* Version definition section. */ -+#define SHT_GNU_verneed 0x6ffffffe /* Version needs section. */ -+#define SHT_GNU_versym 0x6fffffff /* Version symbol table. */ -+#define SHT_HISUNW 0x6fffffff /* Sun-specific high bound. */ -+#define SHT_HIOS 0x6fffffff /* End OS-specific type */ -+#define SHT_LOPROC 0x70000000 /* Start of processor-specific */ -+#define SHT_HIPROC 0x7fffffff /* End of processor-specific */ -+#define SHT_LOUSER 0x80000000 /* Start of application-specific */ -+#define SHT_HIUSER 0x8fffffff /* End of application-specific */ -+ -+/* Legal values for sh_flags (section flags). */ -+ -+#define SHF_WRITE (1 << 0) /* Writable */ -+#define SHF_ALLOC (1 << 1) /* Occupies memory during execution */ -+#define SHF_EXECINSTR (1 << 2) /* Executable */ -+#define SHF_MERGE (1 << 4) /* Might be merged */ -+#define SHF_STRINGS (1 << 5) /* Contains nul-terminated strings */ -+#define SHF_INFO_LINK (1 << 6) /* `sh_info' contains SHT index */ -+#define SHF_LINK_ORDER (1 << 7) /* Preserve order after combining */ -+#define SHF_OS_NONCONFORMING (1 << 8) /* Non-standard OS specific handling -+ required */ -+#define SHF_GROUP (1 << 9) /* Section is member of a group. */ -+#define SHF_TLS (1 << 10) /* Section hold thread-local data. */ -+#define SHF_MASKOS 0x0ff00000 /* OS-specific. */ -+#define SHF_MASKPROC 0xf0000000 /* Processor-specific */ -+ -+/* Section group handling. */ -+#define GRP_COMDAT 0x1 /* Mark group as COMDAT. */ -+ -+/* Symbol table entry. */ -+ -+typedef struct -+{ -+ Elf32_Word st_name; /* Symbol name (string tbl index) */ -+ Elf32_Addr st_value; /* Symbol value */ -+ Elf32_Word st_size; /* Symbol size */ -+ unsigned char st_info; /* Symbol type and binding */ -+ unsigned char st_other; /* Symbol visibility */ -+ Elf32_Section st_shndx; /* Section index */ -+} Elf32_Sym; -+ -+typedef struct -+{ -+ Elf64_Word st_name; /* Symbol name (string tbl index) */ -+ unsigned char st_info; /* Symbol type and binding */ -+ unsigned char st_other; /* Symbol visibility */ -+ Elf64_Section st_shndx; /* Section index */ -+ Elf64_Addr st_value; /* Symbol value */ -+ Elf64_Xword st_size; /* Symbol size */ -+} Elf64_Sym; -+ -+/* The syminfo section if available contains additional information about -+ every dynamic symbol. */ -+ -+typedef struct -+{ -+ Elf32_Half si_boundto; /* Direct bindings, symbol bound to */ -+ Elf32_Half si_flags; /* Per symbol flags */ -+} Elf32_Syminfo; -+ -+typedef struct -+{ -+ Elf64_Half si_boundto; /* Direct bindings, symbol bound to */ -+ Elf64_Half si_flags; /* Per symbol flags */ -+} Elf64_Syminfo; -+ -+/* Possible values for si_boundto. */ -+#define SYMINFO_BT_SELF 0xffff /* Symbol bound to self */ -+#define SYMINFO_BT_PARENT 0xfffe /* Symbol bound to parent */ -+#define SYMINFO_BT_LOWRESERVE 0xff00 /* Beginning of reserved entries */ -+ -+/* Possible bitmasks for si_flags. */ -+#define SYMINFO_FLG_DIRECT 0x0001 /* Direct bound symbol */ -+#define SYMINFO_FLG_PASSTHRU 0x0002 /* Pass-thru symbol for translator */ -+#define SYMINFO_FLG_COPY 0x0004 /* Symbol is a copy-reloc */ -+#define SYMINFO_FLG_LAZYLOAD 0x0008 /* Symbol bound to object to be lazy -+ loaded */ -+/* Syminfo version values. */ -+#define SYMINFO_NONE 0 -+#define SYMINFO_CURRENT 1 -+#define SYMINFO_NUM 2 -+ -+ -+/* How to extract and insert information held in the st_info field. */ -+ -+#define ELF32_ST_BIND(val) (((unsigned char) (val)) >> 4) -+#define ELF32_ST_TYPE(val) ((val) & 0xf) -+#define ELF32_ST_INFO(bind, type) (((bind) << 4) + ((type) & 0xf)) -+ -+/* Both Elf32_Sym and Elf64_Sym use the same one-byte st_info field. */ -+#define ELF64_ST_BIND(val) ELF32_ST_BIND (val) -+#define ELF64_ST_TYPE(val) ELF32_ST_TYPE (val) -+#define ELF64_ST_INFO(bind, type) ELF32_ST_INFO ((bind), (type)) -+ -+/* Legal values for ST_BIND subfield of st_info (symbol binding). */ -+ -+#define STB_LOCAL 0 /* Local symbol */ -+#define STB_GLOBAL 1 /* Global symbol */ -+#define STB_WEAK 2 /* Weak symbol */ -+#define STB_NUM 3 /* Number of defined types. */ -+#define STB_LOOS 10 /* Start of OS-specific */ -+#define STB_HIOS 12 /* End of OS-specific */ -+#define STB_LOPROC 13 /* Start of processor-specific */ -+#define STB_HIPROC 15 /* End of processor-specific */ -+ -+/* Legal values for ST_TYPE subfield of st_info (symbol type). */ -+ -+#define STT_NOTYPE 0 /* Symbol type is unspecified */ -+#define STT_OBJECT 1 /* Symbol is a data object */ -+#define STT_FUNC 2 /* Symbol is a code object */ -+#define STT_SECTION 3 /* Symbol associated with a section */ -+#define STT_FILE 4 /* Symbol's name is file name */ -+#define STT_COMMON 5 /* Symbol is a common data object */ -+#define STT_TLS 6 /* Symbol is thread-local data object*/ -+#define STT_NUM 7 /* Number of defined types. */ -+#define STT_LOOS 10 /* Start of OS-specific */ -+#define STT_HIOS 12 /* End of OS-specific */ -+#define STT_LOPROC 13 /* Start of processor-specific */ -+#define STT_HIPROC 15 /* End of processor-specific */ -+ -+ -+/* Symbol table indices are found in the hash buckets and chain table -+ of a symbol hash table section. This special index value indicates -+ the end of a chain, meaning no further symbols are found in that bucket. */ -+ -+#define STN_UNDEF 0 /* End of a chain. */ -+ -+ -+/* How to extract and insert information held in the st_other field. */ -+ -+#define ELF32_ST_VISIBILITY(o) ((o) & 0x03) -+ -+/* For ELF64 the definitions are the same. */ -+#define ELF64_ST_VISIBILITY(o) ELF32_ST_VISIBILITY (o) -+ -+/* Symbol visibility specification encoded in the st_other field. */ -+#define STV_DEFAULT 0 /* Default symbol visibility rules */ -+#define STV_INTERNAL 1 /* Processor specific hidden class */ -+#define STV_HIDDEN 2 /* Sym unavailable in other modules */ -+#define STV_PROTECTED 3 /* Not preemptible, not exported */ -+ -+ -+/* Relocation table entry without addend (in section of type SHT_REL). */ -+ -+typedef struct -+{ -+ Elf32_Addr r_offset; /* Address */ -+ Elf32_Word r_info; /* Relocation type and symbol index */ -+} Elf32_Rel; -+ -+/* I have seen two different definitions of the Elf64_Rel and -+ Elf64_Rela structures, so we'll leave them out until Novell (or -+ whoever) gets their act together. */ -+/* The following, at least, is used on Sparc v9, MIPS, and Alpha. */ -+ -+typedef struct -+{ -+ Elf64_Addr r_offset; /* Address */ -+ Elf64_Xword r_info; /* Relocation type and symbol index */ -+} Elf64_Rel; -+ -+/* Relocation table entry with addend (in section of type SHT_RELA). */ -+ -+typedef struct -+{ -+ Elf32_Addr r_offset; /* Address */ -+ Elf32_Word r_info; /* Relocation type and symbol index */ -+ Elf32_Sword r_addend; /* Addend */ -+} Elf32_Rela; -+ -+typedef struct -+{ -+ Elf64_Addr r_offset; /* Address */ -+ Elf64_Xword r_info; /* Relocation type and symbol index */ -+ Elf64_Sxword r_addend; /* Addend */ -+} Elf64_Rela; -+ -+/* How to extract and insert information held in the r_info field. */ -+ -+#define ELF32_R_SYM(val) ((val) >> 8) -+#define ELF32_R_TYPE(val) ((val) & 0xff) -+#define ELF32_R_INFO(sym, type) (((sym) << 8) + ((type) & 0xff)) -+ -+#define ELF64_R_SYM(i) ((i) >> 32) -+#define ELF64_R_TYPE(i) ((i) & 0xffffffff) -+#define ELF64_R_INFO(sym,type) ((((Elf64_Xword) (sym)) << 32) + (type)) -+ -+/* Program segment header. */ -+ -+typedef struct -+{ -+ Elf32_Word p_type; /* Segment type */ -+ Elf32_Off p_offset; /* Segment file offset */ -+ Elf32_Addr p_vaddr; /* Segment virtual address */ -+ Elf32_Addr p_paddr; /* Segment physical address */ -+ Elf32_Word p_filesz; /* Segment size in file */ -+ Elf32_Word p_memsz; /* Segment size in memory */ -+ Elf32_Word p_flags; /* Segment flags */ -+ Elf32_Word p_align; /* Segment alignment */ -+} Elf32_Phdr; -+ -+typedef struct -+{ -+ Elf64_Word p_type; /* Segment type */ -+ Elf64_Word p_flags; /* Segment flags */ -+ Elf64_Off p_offset; /* Segment file offset */ -+ Elf64_Addr p_vaddr; /* Segment virtual address */ -+ Elf64_Addr p_paddr; /* Segment physical address */ -+ Elf64_Xword p_filesz; /* Segment size in file */ -+ Elf64_Xword p_memsz; /* Segment size in memory */ -+ Elf64_Xword p_align; /* Segment alignment */ -+} Elf64_Phdr; -+ -+/* Legal values for p_type (segment type). */ -+ -+#define PT_NULL 0 /* Program header table entry unused */ -+#define PT_LOAD 1 /* Loadable program segment */ -+#define PT_DYNAMIC 2 /* Dynamic linking information */ -+#define PT_INTERP 3 /* Program interpreter */ -+#define PT_NOTE 4 /* Auxiliary information */ -+#define PT_SHLIB 5 /* Reserved */ -+#define PT_PHDR 6 /* Entry for header table itself */ -+#define PT_TLS 7 /* Thread-local storage segment */ -+#define PT_NUM 8 /* Number of defined types */ -+#define PT_LOOS 0x60000000 /* Start of OS-specific */ -+#define PT_GNU_EH_FRAME 0x6474e550 /* GCC .eh_frame_hdr segment */ -+#define PT_GNU_STACK 0x6474e551 /* Indicates stack executability */ -+#define PT_LOSUNW 0x6ffffffa -+#define PT_SUNWBSS 0x6ffffffa /* Sun Specific segment */ -+#define PT_SUNWSTACK 0x6ffffffb /* Stack segment */ -+#define PT_HISUNW 0x6fffffff -+#define PT_HIOS 0x6fffffff /* End of OS-specific */ -+#define PT_LOPROC 0x70000000 /* Start of processor-specific */ -+#define PT_HIPROC 0x7fffffff /* End of processor-specific */ -+ -+/* Legal values for p_flags (segment flags). */ -+ -+#define PF_X (1 << 0) /* Segment is executable */ -+#define PF_W (1 << 1) /* Segment is writable */ -+#define PF_R (1 << 2) /* Segment is readable */ -+#define PF_MASKOS 0x0ff00000 /* OS-specific */ -+#define PF_MASKPROC 0xf0000000 /* Processor-specific */ -+ -+/* Legal values for note segment descriptor types for core files. */ -+ -+#define NT_PRSTATUS 1 /* Contains copy of prstatus struct */ -+#define NT_FPREGSET 2 /* Contains copy of fpregset struct */ -+#define NT_PRPSINFO 3 /* Contains copy of prpsinfo struct */ -+#define NT_PRXREG 4 /* Contains copy of prxregset struct */ -+#define NT_TASKSTRUCT 4 /* Contains copy of task structure */ -+#define NT_PLATFORM 5 /* String from sysinfo(SI_PLATFORM) */ -+#define NT_AUXV 6 /* Contains copy of auxv array */ -+#define NT_GWINDOWS 7 /* Contains copy of gwindows struct */ -+#define NT_ASRS 8 /* Contains copy of asrset struct */ -+#define NT_PSTATUS 10 /* Contains copy of pstatus struct */ -+#define NT_PSINFO 13 /* Contains copy of psinfo struct */ -+#define NT_PRCRED 14 /* Contains copy of prcred struct */ -+#define NT_UTSNAME 15 /* Contains copy of utsname struct */ -+#define NT_LWPSTATUS 16 /* Contains copy of lwpstatus struct */ -+#define NT_LWPSINFO 17 /* Contains copy of lwpinfo struct */ -+#define NT_PRFPXREG 20 /* Contains copy of fprxregset struct*/ -+ -+/* Legal values for the note segment descriptor types for object files. */ -+ -+#define NT_VERSION 1 /* Contains a version string. */ -+ -+ -+/* Dynamic section entry. */ -+ -+typedef struct -+{ -+ Elf32_Sword d_tag; /* Dynamic entry type */ -+ union -+ { -+ Elf32_Word d_val; /* Integer value */ -+ Elf32_Addr d_ptr; /* Address value */ -+ } d_un; -+} Elf32_Dyn; -+ -+typedef struct -+{ -+ Elf64_Sxword d_tag; /* Dynamic entry type */ -+ union -+ { -+ Elf64_Xword d_val; /* Integer value */ -+ Elf64_Addr d_ptr; /* Address value */ -+ } d_un; -+} Elf64_Dyn; -+ -+/* Legal values for d_tag (dynamic entry type). */ -+ -+#define DT_NULL 0 /* Marks end of dynamic section */ -+#define DT_NEEDED 1 /* Name of needed library */ -+#define DT_PLTRELSZ 2 /* Size in bytes of PLT relocs */ -+#define DT_PLTGOT 3 /* Processor defined value */ -+#define DT_HASH 4 /* Address of symbol hash table */ -+#define DT_STRTAB 5 /* Address of string table */ -+#define DT_SYMTAB 6 /* Address of symbol table */ -+#define DT_RELA 7 /* Address of Rela relocs */ -+#define DT_RELASZ 8 /* Total size of Rela relocs */ -+#define DT_RELAENT 9 /* Size of one Rela reloc */ -+#define DT_STRSZ 10 /* Size of string table */ -+#define DT_SYMENT 11 /* Size of one symbol table entry */ -+#define DT_INIT 12 /* Address of init function */ -+#define DT_FINI 13 /* Address of termination function */ -+#define DT_SONAME 14 /* Name of shared object */ -+#define DT_RPATH 15 /* Library search path (deprecated) */ -+#define DT_SYMBOLIC 16 /* Start symbol search here */ -+#define DT_REL 17 /* Address of Rel relocs */ -+#define DT_RELSZ 18 /* Total size of Rel relocs */ -+#define DT_RELENT 19 /* Size of one Rel reloc */ -+#define DT_PLTREL 20 /* Type of reloc in PLT */ -+#define DT_DEBUG 21 /* For debugging; unspecified */ -+#define DT_TEXTREL 22 /* Reloc might modify .text */ -+#define DT_JMPREL 23 /* Address of PLT relocs */ -+#define DT_BIND_NOW 24 /* Process relocations of object */ -+#define DT_INIT_ARRAY 25 /* Array with addresses of init fct */ -+#define DT_FINI_ARRAY 26 /* Array with addresses of fini fct */ -+#define DT_INIT_ARRAYSZ 27 /* Size in bytes of DT_INIT_ARRAY */ -+#define DT_FINI_ARRAYSZ 28 /* Size in bytes of DT_FINI_ARRAY */ -+#define DT_RUNPATH 29 /* Library search path */ -+#define DT_FLAGS 30 /* Flags for the object being loaded */ -+#define DT_ENCODING 32 /* Start of encoded range */ -+#define DT_PREINIT_ARRAY 32 /* Array with addresses of preinit fct*/ -+#define DT_PREINIT_ARRAYSZ 33 /* size in bytes of DT_PREINIT_ARRAY */ -+#define DT_NUM 34 /* Number used */ -+#define DT_LOOS 0x6000000d /* Start of OS-specific */ -+#define DT_HIOS 0x6ffff000 /* End of OS-specific */ -+#define DT_LOPROC 0x70000000 /* Start of processor-specific */ -+#define DT_HIPROC 0x7fffffff /* End of processor-specific */ -+#define DT_PROCNUM DT_MIPS_NUM /* Most used by any processor */ -+ -+/* DT_* entries which fall between DT_VALRNGHI & DT_VALRNGLO use the -+ Dyn.d_un.d_val field of the Elf*_Dyn structure. This follows Sun's -+ approach. */ -+#define DT_VALRNGLO 0x6ffffd00 -+#define DT_GNU_PRELINKED 0x6ffffdf5 /* Prelinking timestamp */ -+#define DT_GNU_CONFLICTSZ 0x6ffffdf6 /* Size of conflict section */ -+#define DT_GNU_LIBLISTSZ 0x6ffffdf7 /* Size of library list */ -+#define DT_CHECKSUM 0x6ffffdf8 -+#define DT_PLTPADSZ 0x6ffffdf9 -+#define DT_MOVEENT 0x6ffffdfa -+#define DT_MOVESZ 0x6ffffdfb -+#define DT_FEATURE_1 0x6ffffdfc /* Feature selection (DTF_*). */ -+#define DT_POSFLAG_1 0x6ffffdfd /* Flags for DT_* entries, effecting -+ the following DT_* entry. */ -+#define DT_SYMINSZ 0x6ffffdfe /* Size of syminfo table (in bytes) */ -+#define DT_SYMINENT 0x6ffffdff /* Entry size of syminfo */ -+#define DT_VALRNGHI 0x6ffffdff -+#define DT_VALTAGIDX(tag) (DT_VALRNGHI - (tag)) /* Reverse order! */ -+#define DT_VALNUM 12 -+ -+/* DT_* entries which fall between DT_ADDRRNGHI & DT_ADDRRNGLO use the -+ Dyn.d_un.d_ptr field of the Elf*_Dyn structure. -+ -+ If any adjustment is made to the ELF object after it has been -+ built these entries will need to be adjusted. */ -+#define DT_ADDRRNGLO 0x6ffffe00 -+#define DT_GNU_CONFLICT 0x6ffffef8 /* Start of conflict section */ -+#define DT_GNU_LIBLIST 0x6ffffef9 /* Library list */ -+#define DT_CONFIG 0x6ffffefa /* Configuration information. */ -+#define DT_DEPAUDIT 0x6ffffefb /* Dependency auditing. */ -+#define DT_AUDIT 0x6ffffefc /* Object auditing. */ -+#define DT_PLTPAD 0x6ffffefd /* PLT padding. */ -+#define DT_MOVETAB 0x6ffffefe /* Move table. */ -+#define DT_SYMINFO 0x6ffffeff /* Syminfo table. */ -+#define DT_ADDRRNGHI 0x6ffffeff -+#define DT_ADDRTAGIDX(tag) (DT_ADDRRNGHI - (tag)) /* Reverse order! */ -+#define DT_ADDRNUM 10 -+ -+/* The versioning entry types. The next are defined as part of the -+ GNU extension. */ -+#define DT_VERSYM 0x6ffffff0 -+ -+#define DT_RELACOUNT 0x6ffffff9 -+#define DT_RELCOUNT 0x6ffffffa -+ -+/* These were chosen by Sun. */ -+#define DT_FLAGS_1 0x6ffffffb /* State flags, see DF_1_* below. */ -+#define DT_VERDEF 0x6ffffffc /* Address of version definition -+ table */ -+#define DT_VERDEFNUM 0x6ffffffd /* Number of version definitions */ -+#define DT_VERNEED 0x6ffffffe /* Address of table with needed -+ versions */ -+#define DT_VERNEEDNUM 0x6fffffff /* Number of needed versions */ -+#define DT_VERSIONTAGIDX(tag) (DT_VERNEEDNUM - (tag)) /* Reverse order! */ -+#define DT_VERSIONTAGNUM 16 -+ -+/* Sun added these machine-independent extensions in the "processor-specific" -+ range. Be compatible. */ -+#define DT_AUXILIARY 0x7ffffffd /* Shared object to load before self */ -+#define DT_FILTER 0x7fffffff /* Shared object to get values from */ -+#define DT_EXTRATAGIDX(tag) ((Elf32_Word)-((Elf32_Sword) (tag) <<1>>1)-1) -+#define DT_EXTRANUM 3 -+ -+/* Values of `d_un.d_val' in the DT_FLAGS entry. */ -+#define DF_ORIGIN 0x00000001 /* Object may use DF_ORIGIN */ -+#define DF_SYMBOLIC 0x00000002 /* Symbol resolutions starts here */ -+#define DF_TEXTREL 0x00000004 /* Object contains text relocations */ -+#define DF_BIND_NOW 0x00000008 /* No lazy binding for this object */ -+#define DF_STATIC_TLS 0x00000010 /* Module uses the static TLS model */ -+ -+/* State flags selectable in the `d_un.d_val' element of the DT_FLAGS_1 -+ entry in the dynamic section. */ -+#define DF_1_NOW 0x00000001 /* Set RTLD_NOW for this object. */ -+#define DF_1_GLOBAL 0x00000002 /* Set RTLD_GLOBAL for this object. */ -+#define DF_1_GROUP 0x00000004 /* Set RTLD_GROUP for this object. */ -+#define DF_1_NODELETE 0x00000008 /* Set RTLD_NODELETE for this object.*/ -+#define DF_1_LOADFLTR 0x00000010 /* Trigger filtee loading at runtime.*/ -+#define DF_1_INITFIRST 0x00000020 /* Set RTLD_INITFIRST for this object*/ -+#define DF_1_NOOPEN 0x00000040 /* Set RTLD_NOOPEN for this object. */ -+#define DF_1_ORIGIN 0x00000080 /* $ORIGIN must be handled. */ -+#define DF_1_DIRECT 0x00000100 /* Direct binding enabled. */ -+#define DF_1_TRANS 0x00000200 -+#define DF_1_INTERPOSE 0x00000400 /* Object is used to interpose. */ -+#define DF_1_NODEFLIB 0x00000800 /* Ignore default lib search path. */ -+#define DF_1_NODUMP 0x00001000 /* Object can't be dldump'ed. */ -+#define DF_1_CONFALT 0x00002000 /* Configuration alternative created.*/ -+#define DF_1_ENDFILTEE 0x00004000 /* Filtee terminates filters search. */ -+#define DF_1_DISPRELDNE 0x00008000 /* Disp reloc applied at build time. */ -+#define DF_1_DISPRELPND 0x00010000 /* Disp reloc applied at run-time. */ -+ -+/* Flags for the feature selection in DT_FEATURE_1. */ -+#define DTF_1_PARINIT 0x00000001 -+#define DTF_1_CONFEXP 0x00000002 -+ -+/* Flags in the DT_POSFLAG_1 entry effecting only the next DT_* entry. */ -+#define DF_P1_LAZYLOAD 0x00000001 /* Lazyload following object. */ -+#define DF_P1_GROUPPERM 0x00000002 /* Symbols from next object are not -+ generally available. */ -+ -+/* Version definition sections. */ -+ -+typedef struct -+{ -+ Elf32_Half vd_version; /* Version revision */ -+ Elf32_Half vd_flags; /* Version information */ -+ Elf32_Half vd_ndx; /* Version Index */ -+ Elf32_Half vd_cnt; /* Number of associated aux entries */ -+ Elf32_Word vd_hash; /* Version name hash value */ -+ Elf32_Word vd_aux; /* Offset in bytes to verdaux array */ -+ Elf32_Word vd_next; /* Offset in bytes to next verdef -+ entry */ -+} Elf32_Verdef; -+ -+typedef struct -+{ -+ Elf64_Half vd_version; /* Version revision */ -+ Elf64_Half vd_flags; /* Version information */ -+ Elf64_Half vd_ndx; /* Version Index */ -+ Elf64_Half vd_cnt; /* Number of associated aux entries */ -+ Elf64_Word vd_hash; /* Version name hash value */ -+ Elf64_Word vd_aux; /* Offset in bytes to verdaux array */ -+ Elf64_Word vd_next; /* Offset in bytes to next verdef -+ entry */ -+} Elf64_Verdef; -+ -+ -+/* Legal values for vd_version (version revision). */ -+#define VER_DEF_NONE 0 /* No version */ -+#define VER_DEF_CURRENT 1 /* Current version */ -+#define VER_DEF_NUM 2 /* Given version number */ -+ -+/* Legal values for vd_flags (version information flags). */ -+#define VER_FLG_BASE 0x1 /* Version definition of file itself */ -+#define VER_FLG_WEAK 0x2 /* Weak version identifier */ -+ -+/* Versym symbol index values. */ -+#define VER_NDX_LOCAL 0 /* Symbol is local. */ -+#define VER_NDX_GLOBAL 1 /* Symbol is global. */ -+#define VER_NDX_LORESERVE 0xff00 /* Beginning of reserved entries. */ -+#define VER_NDX_ELIMINATE 0xff01 /* Symbol is to be eliminated. */ -+ -+/* Auxialiary version information. */ -+ -+typedef struct -+{ -+ Elf32_Word vda_name; /* Version or dependency names */ -+ Elf32_Word vda_next; /* Offset in bytes to next verdaux -+ entry */ -+} Elf32_Verdaux; -+ -+typedef struct -+{ -+ Elf64_Word vda_name; /* Version or dependency names */ -+ Elf64_Word vda_next; /* Offset in bytes to next verdaux -+ entry */ -+} Elf64_Verdaux; -+ -+ -+/* Version dependency section. */ -+ -+typedef struct -+{ -+ Elf32_Half vn_version; /* Version of structure */ -+ Elf32_Half vn_cnt; /* Number of associated aux entries */ -+ Elf32_Word vn_file; /* Offset of filename for this -+ dependency */ -+ Elf32_Word vn_aux; /* Offset in bytes to vernaux array */ -+ Elf32_Word vn_next; /* Offset in bytes to next verneed -+ entry */ -+} Elf32_Verneed; -+ -+typedef struct -+{ -+ Elf64_Half vn_version; /* Version of structure */ -+ Elf64_Half vn_cnt; /* Number of associated aux entries */ -+ Elf64_Word vn_file; /* Offset of filename for this -+ dependency */ -+ Elf64_Word vn_aux; /* Offset in bytes to vernaux array */ -+ Elf64_Word vn_next; /* Offset in bytes to next verneed -+ entry */ -+} Elf64_Verneed; -+ -+ -+/* Legal values for vn_version (version revision). */ -+#define VER_NEED_NONE 0 /* No version */ -+#define VER_NEED_CURRENT 1 /* Current version */ -+#define VER_NEED_NUM 2 /* Given version number */ -+ -+/* Auxiliary needed version information. */ -+ -+typedef struct -+{ -+ Elf32_Word vna_hash; /* Hash value of dependency name */ -+ Elf32_Half vna_flags; /* Dependency specific information */ -+ Elf32_Half vna_other; /* Unused */ -+ Elf32_Word vna_name; /* Dependency name string offset */ -+ Elf32_Word vna_next; /* Offset in bytes to next vernaux -+ entry */ -+} Elf32_Vernaux; -+ -+typedef struct -+{ -+ Elf64_Word vna_hash; /* Hash value of dependency name */ -+ Elf64_Half vna_flags; /* Dependency specific information */ -+ Elf64_Half vna_other; /* Unused */ -+ Elf64_Word vna_name; /* Dependency name string offset */ -+ Elf64_Word vna_next; /* Offset in bytes to next vernaux -+ entry */ -+} Elf64_Vernaux; -+ -+ -+/* Legal values for vna_flags. */ -+#define VER_FLG_WEAK 0x2 /* Weak version identifier */ -+ -+ -+/* Auxiliary vector. */ -+ -+/* This vector is normally only used by the program interpreter. The -+ usual definition in an ABI supplement uses the name auxv_t. The -+ vector is not usually defined in a standard file, but it -+ can't hurt. We rename it to avoid conflicts. The sizes of these -+ types are an arrangement between the exec server and the program -+ interpreter, so we don't fully specify them here. */ -+ -+typedef struct -+{ -+ int a_type; /* Entry type */ -+ union -+ { -+ long int a_val; /* Integer value */ -+ void *a_ptr; /* Pointer value */ -+ void (*a_fcn) (void); /* Function pointer value */ -+ } a_un; -+} Elf32_auxv_t; -+ -+typedef struct -+{ -+ long int a_type; /* Entry type */ -+ union -+ { -+ long int a_val; /* Integer value */ -+ void *a_ptr; /* Pointer value */ -+ void (*a_fcn) (void); /* Function pointer value */ -+ } a_un; -+} Elf64_auxv_t; -+ -+/* Legal values for a_type (entry type). */ -+ -+#define AT_NULL 0 /* End of vector */ -+#define AT_IGNORE 1 /* Entry should be ignored */ -+#define AT_EXECFD 2 /* File descriptor of program */ -+#define AT_PHDR 3 /* Program headers for program */ -+#define AT_PHENT 4 /* Size of program header entry */ -+#define AT_PHNUM 5 /* Number of program headers */ -+#define AT_PAGESZ 6 /* System page size */ -+#define AT_BASE 7 /* Base address of interpreter */ -+#define AT_FLAGS 8 /* Flags */ -+#define AT_ENTRY 9 /* Entry point of program */ -+#define AT_NOTELF 10 /* Program is not ELF */ -+#define AT_UID 11 /* Real uid */ -+#define AT_EUID 12 /* Effective uid */ -+#define AT_GID 13 /* Real gid */ -+#define AT_EGID 14 /* Effective gid */ -+#define AT_CLKTCK 17 /* Frequency of times() */ -+ -+/* Some more special a_type values describing the hardware. */ -+#define AT_PLATFORM 15 /* String identifying platform. */ -+#define AT_HWCAP 16 /* Machine dependent hints about -+ processor capabilities. */ -+ -+/* This entry gives some information about the FPU initialization -+ performed by the kernel. */ -+#define AT_FPUCW 18 /* Used FPU control word. */ -+ -+/* Cache block sizes. */ -+#define AT_DCACHEBSIZE 19 /* Data cache block size. */ -+#define AT_ICACHEBSIZE 20 /* Instruction cache block size. */ -+#define AT_UCACHEBSIZE 21 /* Unified cache block size. */ -+ -+/* A special ignored value for PPC, used by the kernel to control the -+ interpretation of the AUXV. Must be > 16. */ -+#define AT_IGNOREPPC 22 /* Entry should be ignored. */ -+ -+#define AT_SECURE 23 /* Boolean, was exec setuid-like? */ -+ -+/* Pointer to the global system page used for system calls and other -+ nice things. */ -+#define AT_SYSINFO 32 -+#define AT_SYSINFO_EHDR 33 -+ -+ -+/* Note section contents. Each entry in the note section begins with -+ a header of a fixed form. */ -+ -+typedef struct -+{ -+ Elf32_Word n_namesz; /* Length of the note's name. */ -+ Elf32_Word n_descsz; /* Length of the note's descriptor. */ -+ Elf32_Word n_type; /* Type of the note. */ -+} Elf32_Nhdr; -+ -+typedef struct -+{ -+ Elf64_Word n_namesz; /* Length of the note's name. */ -+ Elf64_Word n_descsz; /* Length of the note's descriptor. */ -+ Elf64_Word n_type; /* Type of the note. */ -+} Elf64_Nhdr; -+ -+/* Known names of notes. */ -+ -+/* Solaris entries in the note section have this name. */ -+#define ELF_NOTE_SOLARIS "SUNW Solaris" -+ -+/* Note entries for GNU systems have this name. */ -+#define ELF_NOTE_GNU "GNU" -+ -+ -+/* Defined types of notes for Solaris. */ -+ -+/* Value of descriptor (one word) is desired pagesize for the binary. */ -+#define ELF_NOTE_PAGESIZE_HINT 1 -+ -+ -+/* Defined note types for GNU systems. */ -+ -+/* ABI information. The descriptor consists of words: -+ word 0: OS descriptor -+ word 1: major version of the ABI -+ word 2: minor version of the ABI -+ word 3: subminor version of the ABI -+*/ -+#define ELF_NOTE_ABI 1 -+ -+/* Known OSes. These value can appear in word 0 of an ELF_NOTE_ABI -+ note section entry. */ -+#define ELF_NOTE_OS_LINUX 0 -+#define ELF_NOTE_OS_GNU 1 -+#define ELF_NOTE_OS_SOLARIS2 2 -+#define ELF_NOTE_OS_FREEBSD 3 -+ -+ -+/* Move records. */ -+typedef struct -+{ -+ Elf32_Xword m_value; /* Symbol value. */ -+ Elf32_Word m_info; /* Size and index. */ -+ Elf32_Word m_poffset; /* Symbol offset. */ -+ Elf32_Half m_repeat; /* Repeat count. */ -+ Elf32_Half m_stride; /* Stride info. */ -+} Elf32_Move; -+ -+typedef struct -+{ -+ Elf64_Xword m_value; /* Symbol value. */ -+ Elf64_Xword m_info; /* Size and index. */ -+ Elf64_Xword m_poffset; /* Symbol offset. */ -+ Elf64_Half m_repeat; /* Repeat count. */ -+ Elf64_Half m_stride; /* Stride info. */ -+} Elf64_Move; -+ -+/* Macro to construct move records. */ -+#define ELF32_M_SYM(info) ((info) >> 8) -+#define ELF32_M_SIZE(info) ((unsigned char) (info)) -+#define ELF32_M_INFO(sym, size) (((sym) << 8) + (unsigned char) (size)) -+ -+#define ELF64_M_SYM(info) ELF32_M_SYM (info) -+#define ELF64_M_SIZE(info) ELF32_M_SIZE (info) -+#define ELF64_M_INFO(sym, size) ELF32_M_INFO (sym, size) -+ -+ -+/* Motorola 68k specific definitions. */ -+ -+/* Values for Elf32_Ehdr.e_flags. */ -+#define EF_CPU32 0x00810000 -+ -+/* m68k relocs. */ -+ -+#define R_68K_NONE 0 /* No reloc */ -+#define R_68K_32 1 /* Direct 32 bit */ -+#define R_68K_16 2 /* Direct 16 bit */ -+#define R_68K_8 3 /* Direct 8 bit */ -+#define R_68K_PC32 4 /* PC relative 32 bit */ -+#define R_68K_PC16 5 /* PC relative 16 bit */ -+#define R_68K_PC8 6 /* PC relative 8 bit */ -+#define R_68K_GOT32 7 /* 32 bit PC relative GOT entry */ -+#define R_68K_GOT16 8 /* 16 bit PC relative GOT entry */ -+#define R_68K_GOT8 9 /* 8 bit PC relative GOT entry */ -+#define R_68K_GOT32O 10 /* 32 bit GOT offset */ -+#define R_68K_GOT16O 11 /* 16 bit GOT offset */ -+#define R_68K_GOT8O 12 /* 8 bit GOT offset */ -+#define R_68K_PLT32 13 /* 32 bit PC relative PLT address */ -+#define R_68K_PLT16 14 /* 16 bit PC relative PLT address */ -+#define R_68K_PLT8 15 /* 8 bit PC relative PLT address */ -+#define R_68K_PLT32O 16 /* 32 bit PLT offset */ -+#define R_68K_PLT16O 17 /* 16 bit PLT offset */ -+#define R_68K_PLT8O 18 /* 8 bit PLT offset */ -+#define R_68K_COPY 19 /* Copy symbol at runtime */ -+#define R_68K_GLOB_DAT 20 /* Create GOT entry */ -+#define R_68K_JMP_SLOT 21 /* Create PLT entry */ -+#define R_68K_RELATIVE 22 /* Adjust by program base */ -+/* Keep this the last entry. */ -+#define R_68K_NUM 23 -+ -+/* Intel 80386 specific definitions. */ -+ -+/* i386 relocs. */ -+ -+#define R_386_NONE 0 /* No reloc */ -+#define R_386_32 1 /* Direct 32 bit */ -+#define R_386_PC32 2 /* PC relative 32 bit */ -+#define R_386_GOT32 3 /* 32 bit GOT entry */ -+#define R_386_PLT32 4 /* 32 bit PLT address */ -+#define R_386_COPY 5 /* Copy symbol at runtime */ -+#define R_386_GLOB_DAT 6 /* Create GOT entry */ -+#define R_386_JMP_SLOT 7 /* Create PLT entry */ -+#define R_386_RELATIVE 8 /* Adjust by program base */ -+#define R_386_GOTOFF 9 /* 32 bit offset to GOT */ -+#define R_386_GOTPC 10 /* 32 bit PC relative offset to GOT */ -+#define R_386_32PLT 11 -+#define R_386_TLS_TPOFF 14 /* Offset in static TLS block */ -+#define R_386_TLS_IE 15 /* Address of GOT entry for static TLS -+ block offset */ -+#define R_386_TLS_GOTIE 16 /* GOT entry for static TLS block -+ offset */ -+#define R_386_TLS_LE 17 /* Offset relative to static TLS -+ block */ -+#define R_386_TLS_GD 18 /* Direct 32 bit for GNU version of -+ general dynamic thread local data */ -+#define R_386_TLS_LDM 19 /* Direct 32 bit for GNU version of -+ local dynamic thread local data -+ in LE code */ -+#define R_386_16 20 -+#define R_386_PC16 21 -+#define R_386_8 22 -+#define R_386_PC8 23 -+#define R_386_TLS_GD_32 24 /* Direct 32 bit for general dynamic -+ thread local data */ -+#define R_386_TLS_GD_PUSH 25 /* Tag for pushl in GD TLS code */ -+#define R_386_TLS_GD_CALL 26 /* Relocation for call to -+ __tls_get_addr() */ -+#define R_386_TLS_GD_POP 27 /* Tag for popl in GD TLS code */ -+#define R_386_TLS_LDM_32 28 /* Direct 32 bit for local dynamic -+ thread local data in LE code */ -+#define R_386_TLS_LDM_PUSH 29 /* Tag for pushl in LDM TLS code */ -+#define R_386_TLS_LDM_CALL 30 /* Relocation for call to -+ __tls_get_addr() in LDM code */ -+#define R_386_TLS_LDM_POP 31 /* Tag for popl in LDM TLS code */ -+#define R_386_TLS_LDO_32 32 /* Offset relative to TLS block */ -+#define R_386_TLS_IE_32 33 /* GOT entry for negated static TLS -+ block offset */ -+#define R_386_TLS_LE_32 34 /* Negated offset relative to static -+ TLS block */ -+#define R_386_TLS_DTPMOD32 35 /* ID of module containing symbol */ -+#define R_386_TLS_DTPOFF32 36 /* Offset in TLS block */ -+#define R_386_TLS_TPOFF32 37 /* Negated offset in static TLS block */ -+/* Keep this the last entry. */ -+#define R_386_NUM 38 -+ -+/* SUN SPARC specific definitions. */ -+ -+/* Legal values for ST_TYPE subfield of st_info (symbol type). */ -+ -+#define STT_REGISTER 13 /* Global register reserved to app. */ -+ -+/* Values for Elf64_Ehdr.e_flags. */ -+ -+#define EF_SPARCV9_MM 3 -+#define EF_SPARCV9_TSO 0 -+#define EF_SPARCV9_PSO 1 -+#define EF_SPARCV9_RMO 2 -+#define EF_SPARC_LEDATA 0x800000 /* little endian data */ -+#define EF_SPARC_EXT_MASK 0xFFFF00 -+#define EF_SPARC_32PLUS 0x000100 /* generic V8+ features */ -+#define EF_SPARC_SUN_US1 0x000200 /* Sun UltraSPARC1 extensions */ -+#define EF_SPARC_HAL_R1 0x000400 /* HAL R1 extensions */ -+#define EF_SPARC_SUN_US3 0x000800 /* Sun UltraSPARCIII extensions */ -+ -+/* SPARC relocs. */ -+ -+#define R_SPARC_NONE 0 /* No reloc */ -+#define R_SPARC_8 1 /* Direct 8 bit */ -+#define R_SPARC_16 2 /* Direct 16 bit */ -+#define R_SPARC_32 3 /* Direct 32 bit */ -+#define R_SPARC_DISP8 4 /* PC relative 8 bit */ -+#define R_SPARC_DISP16 5 /* PC relative 16 bit */ -+#define R_SPARC_DISP32 6 /* PC relative 32 bit */ -+#define R_SPARC_WDISP30 7 /* PC relative 30 bit shifted */ -+#define R_SPARC_WDISP22 8 /* PC relative 22 bit shifted */ -+#define R_SPARC_HI22 9 /* High 22 bit */ -+#define R_SPARC_22 10 /* Direct 22 bit */ -+#define R_SPARC_13 11 /* Direct 13 bit */ -+#define R_SPARC_LO10 12 /* Truncated 10 bit */ -+#define R_SPARC_GOT10 13 /* Truncated 10 bit GOT entry */ -+#define R_SPARC_GOT13 14 /* 13 bit GOT entry */ -+#define R_SPARC_GOT22 15 /* 22 bit GOT entry shifted */ -+#define R_SPARC_PC10 16 /* PC relative 10 bit truncated */ -+#define R_SPARC_PC22 17 /* PC relative 22 bit shifted */ -+#define R_SPARC_WPLT30 18 /* 30 bit PC relative PLT address */ -+#define R_SPARC_COPY 19 /* Copy symbol at runtime */ -+#define R_SPARC_GLOB_DAT 20 /* Create GOT entry */ -+#define R_SPARC_JMP_SLOT 21 /* Create PLT entry */ -+#define R_SPARC_RELATIVE 22 /* Adjust by program base */ -+#define R_SPARC_UA32 23 /* Direct 32 bit unaligned */ -+ -+/* Additional Sparc64 relocs. */ -+ -+#define R_SPARC_PLT32 24 /* Direct 32 bit ref to PLT entry */ -+#define R_SPARC_HIPLT22 25 /* High 22 bit PLT entry */ -+#define R_SPARC_LOPLT10 26 /* Truncated 10 bit PLT entry */ -+#define R_SPARC_PCPLT32 27 /* PC rel 32 bit ref to PLT entry */ -+#define R_SPARC_PCPLT22 28 /* PC rel high 22 bit PLT entry */ -+#define R_SPARC_PCPLT10 29 /* PC rel trunc 10 bit PLT entry */ -+#define R_SPARC_10 30 /* Direct 10 bit */ -+#define R_SPARC_11 31 /* Direct 11 bit */ -+#define R_SPARC_64 32 /* Direct 64 bit */ -+#define R_SPARC_OLO10 33 /* 10bit with secondary 13bit addend */ -+#define R_SPARC_HH22 34 /* Top 22 bits of direct 64 bit */ -+#define R_SPARC_HM10 35 /* High middle 10 bits of ... */ -+#define R_SPARC_LM22 36 /* Low middle 22 bits of ... */ -+#define R_SPARC_PC_HH22 37 /* Top 22 bits of pc rel 64 bit */ -+#define R_SPARC_PC_HM10 38 /* High middle 10 bit of ... */ -+#define R_SPARC_PC_LM22 39 /* Low miggle 22 bits of ... */ -+#define R_SPARC_WDISP16 40 /* PC relative 16 bit shifted */ -+#define R_SPARC_WDISP19 41 /* PC relative 19 bit shifted */ -+#define R_SPARC_7 43 /* Direct 7 bit */ -+#define R_SPARC_5 44 /* Direct 5 bit */ -+#define R_SPARC_6 45 /* Direct 6 bit */ -+#define R_SPARC_DISP64 46 /* PC relative 64 bit */ -+#define R_SPARC_PLT64 47 /* Direct 64 bit ref to PLT entry */ -+#define R_SPARC_HIX22 48 /* High 22 bit complemented */ -+#define R_SPARC_LOX10 49 /* Truncated 11 bit complemented */ -+#define R_SPARC_H44 50 /* Direct high 12 of 44 bit */ -+#define R_SPARC_M44 51 /* Direct mid 22 of 44 bit */ -+#define R_SPARC_L44 52 /* Direct low 10 of 44 bit */ -+#define R_SPARC_REGISTER 53 /* Global register usage */ -+#define R_SPARC_UA64 54 /* Direct 64 bit unaligned */ -+#define R_SPARC_UA16 55 /* Direct 16 bit unaligned */ -+#define R_SPARC_TLS_GD_HI22 56 -+#define R_SPARC_TLS_GD_LO10 57 -+#define R_SPARC_TLS_GD_ADD 58 -+#define R_SPARC_TLS_GD_CALL 59 -+#define R_SPARC_TLS_LDM_HI22 60 -+#define R_SPARC_TLS_LDM_LO10 61 -+#define R_SPARC_TLS_LDM_ADD 62 -+#define R_SPARC_TLS_LDM_CALL 63 -+#define R_SPARC_TLS_LDO_HIX22 64 -+#define R_SPARC_TLS_LDO_LOX10 65 -+#define R_SPARC_TLS_LDO_ADD 66 -+#define R_SPARC_TLS_IE_HI22 67 -+#define R_SPARC_TLS_IE_LO10 68 -+#define R_SPARC_TLS_IE_LD 69 -+#define R_SPARC_TLS_IE_LDX 70 -+#define R_SPARC_TLS_IE_ADD 71 -+#define R_SPARC_TLS_LE_HIX22 72 -+#define R_SPARC_TLS_LE_LOX10 73 -+#define R_SPARC_TLS_DTPMOD32 74 -+#define R_SPARC_TLS_DTPMOD64 75 -+#define R_SPARC_TLS_DTPOFF32 76 -+#define R_SPARC_TLS_DTPOFF64 77 -+#define R_SPARC_TLS_TPOFF32 78 -+#define R_SPARC_TLS_TPOFF64 79 -+/* Keep this the last entry. */ -+#define R_SPARC_NUM 80 -+ -+/* For Sparc64, legal values for d_tag of Elf64_Dyn. */ -+ -+#define DT_SPARC_REGISTER 0x70000001 -+#define DT_SPARC_NUM 2 -+ -+/* Bits present in AT_HWCAP, primarily for Sparc32. */ -+ -+#define HWCAP_SPARC_FLUSH 1 /* The cpu supports flush insn. */ -+#define HWCAP_SPARC_STBAR 2 -+#define HWCAP_SPARC_SWAP 4 -+#define HWCAP_SPARC_MULDIV 8 -+#define HWCAP_SPARC_V9 16 /* The cpu is v9, so v8plus is ok. */ -+#define HWCAP_SPARC_ULTRA3 32 -+ -+/* MIPS R3000 specific definitions. */ -+ -+/* Legal values for e_flags field of Elf32_Ehdr. */ -+ -+#define EF_MIPS_NOREORDER 1 /* A .noreorder directive was used */ -+#define EF_MIPS_PIC 2 /* Contains PIC code */ -+#define EF_MIPS_CPIC 4 /* Uses PIC calling sequence */ -+#define EF_MIPS_XGOT 8 -+#define EF_MIPS_64BIT_WHIRL 16 -+#define EF_MIPS_ABI2 32 -+#define EF_MIPS_ABI_ON32 64 -+#define EF_MIPS_ARCH 0xf0000000 /* MIPS architecture level */ -+ -+/* Legal values for MIPS architecture level. */ -+ -+#define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ -+#define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ -+#define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ -+#define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ -+#define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ -+#define EF_MIPS_ARCH_32 0x60000000 /* MIPS32 code. */ -+#define EF_MIPS_ARCH_64 0x70000000 /* MIPS64 code. */ -+ -+/* The following are non-official names and should not be used. */ -+ -+#define E_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ -+#define E_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ -+#define E_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ -+#define E_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ -+#define E_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ -+#define E_MIPS_ARCH_32 0x60000000 /* MIPS32 code. */ -+#define E_MIPS_ARCH_64 0x70000000 /* MIPS64 code. */ -+ -+/* Special section indices. */ -+ -+#define SHN_MIPS_ACOMMON 0xff00 /* Allocated common symbols */ -+#define SHN_MIPS_TEXT 0xff01 /* Allocated test symbols. */ -+#define SHN_MIPS_DATA 0xff02 /* Allocated data symbols. */ -+#define SHN_MIPS_SCOMMON 0xff03 /* Small common symbols */ -+#define SHN_MIPS_SUNDEFINED 0xff04 /* Small undefined symbols */ -+ -+/* Legal values for sh_type field of Elf32_Shdr. */ -+ -+#define SHT_MIPS_LIBLIST 0x70000000 /* Shared objects used in link */ -+#define SHT_MIPS_MSYM 0x70000001 -+#define SHT_MIPS_CONFLICT 0x70000002 /* Conflicting symbols */ -+#define SHT_MIPS_GPTAB 0x70000003 /* Global data area sizes */ -+#define SHT_MIPS_UCODE 0x70000004 /* Reserved for SGI/MIPS compilers */ -+#define SHT_MIPS_DEBUG 0x70000005 /* MIPS ECOFF debugging information*/ -+#define SHT_MIPS_REGINFO 0x70000006 /* Register usage information */ -+#define SHT_MIPS_PACKAGE 0x70000007 -+#define SHT_MIPS_PACKSYM 0x70000008 -+#define SHT_MIPS_RELD 0x70000009 -+#define SHT_MIPS_IFACE 0x7000000b -+#define SHT_MIPS_CONTENT 0x7000000c -+#define SHT_MIPS_OPTIONS 0x7000000d /* Miscellaneous options. */ -+#define SHT_MIPS_SHDR 0x70000010 -+#define SHT_MIPS_FDESC 0x70000011 -+#define SHT_MIPS_EXTSYM 0x70000012 -+#define SHT_MIPS_DENSE 0x70000013 -+#define SHT_MIPS_PDESC 0x70000014 -+#define SHT_MIPS_LOCSYM 0x70000015 -+#define SHT_MIPS_AUXSYM 0x70000016 -+#define SHT_MIPS_OPTSYM 0x70000017 -+#define SHT_MIPS_LOCSTR 0x70000018 -+#define SHT_MIPS_LINE 0x70000019 -+#define SHT_MIPS_RFDESC 0x7000001a -+#define SHT_MIPS_DELTASYM 0x7000001b -+#define SHT_MIPS_DELTAINST 0x7000001c -+#define SHT_MIPS_DELTACLASS 0x7000001d -+#define SHT_MIPS_DWARF 0x7000001e /* DWARF debugging information. */ -+#define SHT_MIPS_DELTADECL 0x7000001f -+#define SHT_MIPS_SYMBOL_LIB 0x70000020 -+#define SHT_MIPS_EVENTS 0x70000021 /* Event section. */ -+#define SHT_MIPS_TRANSLATE 0x70000022 -+#define SHT_MIPS_PIXIE 0x70000023 -+#define SHT_MIPS_XLATE 0x70000024 -+#define SHT_MIPS_XLATE_DEBUG 0x70000025 -+#define SHT_MIPS_WHIRL 0x70000026 -+#define SHT_MIPS_EH_REGION 0x70000027 -+#define SHT_MIPS_XLATE_OLD 0x70000028 -+#define SHT_MIPS_PDR_EXCEPTION 0x70000029 -+ -+/* Legal values for sh_flags field of Elf32_Shdr. */ -+ -+#define SHF_MIPS_GPREL 0x10000000 /* Must be part of global data area */ -+#define SHF_MIPS_MERGE 0x20000000 -+#define SHF_MIPS_ADDR 0x40000000 -+#define SHF_MIPS_STRINGS 0x80000000 -+#define SHF_MIPS_NOSTRIP 0x08000000 -+#define SHF_MIPS_LOCAL 0x04000000 -+#define SHF_MIPS_NAMES 0x02000000 -+#define SHF_MIPS_NODUPE 0x01000000 -+ -+ -+/* Symbol tables. */ -+ -+/* MIPS specific values for `st_other'. */ -+#define STO_MIPS_DEFAULT 0x0 -+#define STO_MIPS_INTERNAL 0x1 -+#define STO_MIPS_HIDDEN 0x2 -+#define STO_MIPS_PROTECTED 0x3 -+#define STO_MIPS_SC_ALIGN_UNUSED 0xff -+ -+/* MIPS specific values for `st_info'. */ -+#define STB_MIPS_SPLIT_COMMON 13 -+ -+/* Entries found in sections of type SHT_MIPS_GPTAB. */ -+ -+typedef union -+{ -+ struct -+ { -+ Elf32_Word gt_current_g_value; /* -G value used for compilation */ -+ Elf32_Word gt_unused; /* Not used */ -+ } gt_header; /* First entry in section */ -+ struct -+ { -+ Elf32_Word gt_g_value; /* If this value were used for -G */ -+ Elf32_Word gt_bytes; /* This many bytes would be used */ -+ } gt_entry; /* Subsequent entries in section */ -+} Elf32_gptab; -+ -+/* Entry found in sections of type SHT_MIPS_REGINFO. */ -+ -+typedef struct -+{ -+ Elf32_Word ri_gprmask; /* General registers used */ -+ Elf32_Word ri_cprmask[4]; /* Coprocessor registers used */ -+ Elf32_Sword ri_gp_value; /* $gp register value */ -+} Elf32_RegInfo; -+ -+/* Entries found in sections of type SHT_MIPS_OPTIONS. */ -+ -+typedef struct -+{ -+ unsigned char kind; /* Determines interpretation of the -+ variable part of descriptor. */ -+ unsigned char size; /* Size of descriptor, including header. */ -+ Elf32_Section section; /* Section header index of section affected, -+ 0 for global options. */ -+ Elf32_Word info; /* Kind-specific information. */ -+} Elf_Options; -+ -+/* Values for `kind' field in Elf_Options. */ -+ -+#define ODK_NULL 0 /* Undefined. */ -+#define ODK_REGINFO 1 /* Register usage information. */ -+#define ODK_EXCEPTIONS 2 /* Exception processing options. */ -+#define ODK_PAD 3 /* Section padding options. */ -+#define ODK_HWPATCH 4 /* Hardware workarounds performed */ -+#define ODK_FILL 5 /* record the fill value used by the linker. */ -+#define ODK_TAGS 6 /* reserve space for desktop tools to write. */ -+#define ODK_HWAND 7 /* HW workarounds. 'AND' bits when merging. */ -+#define ODK_HWOR 8 /* HW workarounds. 'OR' bits when merging. */ -+ -+/* Values for `info' in Elf_Options for ODK_EXCEPTIONS entries. */ -+ -+#define OEX_FPU_MIN 0x1f /* FPE's which MUST be enabled. */ -+#define OEX_FPU_MAX 0x1f00 /* FPE's which MAY be enabled. */ -+#define OEX_PAGE0 0x10000 /* page zero must be mapped. */ -+#define OEX_SMM 0x20000 /* Force sequential memory mode? */ -+#define OEX_FPDBUG 0x40000 /* Force floating point debug mode? */ -+#define OEX_PRECISEFP OEX_FPDBUG -+#define OEX_DISMISS 0x80000 /* Dismiss invalid address faults? */ -+ -+#define OEX_FPU_INVAL 0x10 -+#define OEX_FPU_DIV0 0x08 -+#define OEX_FPU_OFLO 0x04 -+#define OEX_FPU_UFLO 0x02 -+#define OEX_FPU_INEX 0x01 -+ -+/* Masks for `info' in Elf_Options for an ODK_HWPATCH entry. */ -+ -+#define OHW_R4KEOP 0x1 /* R4000 end-of-page patch. */ -+#define OHW_R8KPFETCH 0x2 /* may need R8000 prefetch patch. */ -+#define OHW_R5KEOP 0x4 /* R5000 end-of-page patch. */ -+#define OHW_R5KCVTL 0x8 /* R5000 cvt.[ds].l bug. clean=1. */ -+ -+#define OPAD_PREFIX 0x1 -+#define OPAD_POSTFIX 0x2 -+#define OPAD_SYMBOL 0x4 -+ -+/* Entry found in `.options' section. */ -+ -+typedef struct -+{ -+ Elf32_Word hwp_flags1; /* Extra flags. */ -+ Elf32_Word hwp_flags2; /* Extra flags. */ -+} Elf_Options_Hw; -+ -+/* Masks for `info' in ElfOptions for ODK_HWAND and ODK_HWOR entries. */ -+ -+#define OHWA0_R4KEOP_CHECKED 0x00000001 -+#define OHWA1_R4KEOP_CLEAN 0x00000002 -+ -+/* MIPS relocs. */ -+ -+#define R_MIPS_NONE 0 /* No reloc */ -+#define R_MIPS_16 1 /* Direct 16 bit */ -+#define R_MIPS_32 2 /* Direct 32 bit */ -+#define R_MIPS_REL32 3 /* PC relative 32 bit */ -+#define R_MIPS_26 4 /* Direct 26 bit shifted */ -+#define R_MIPS_HI16 5 /* High 16 bit */ -+#define R_MIPS_LO16 6 /* Low 16 bit */ -+#define R_MIPS_GPREL16 7 /* GP relative 16 bit */ -+#define R_MIPS_LITERAL 8 /* 16 bit literal entry */ -+#define R_MIPS_GOT16 9 /* 16 bit GOT entry */ -+#define R_MIPS_PC16 10 /* PC relative 16 bit */ -+#define R_MIPS_CALL16 11 /* 16 bit GOT entry for function */ -+#define R_MIPS_GPREL32 12 /* GP relative 32 bit */ -+ -+#define R_MIPS_SHIFT5 16 -+#define R_MIPS_SHIFT6 17 -+#define R_MIPS_64 18 -+#define R_MIPS_GOT_DISP 19 -+#define R_MIPS_GOT_PAGE 20 -+#define R_MIPS_GOT_OFST 21 -+#define R_MIPS_GOT_HI16 22 -+#define R_MIPS_GOT_LO16 23 -+#define R_MIPS_SUB 24 -+#define R_MIPS_INSERT_A 25 -+#define R_MIPS_INSERT_B 26 -+#define R_MIPS_DELETE 27 -+#define R_MIPS_HIGHER 28 -+#define R_MIPS_HIGHEST 29 -+#define R_MIPS_CALL_HI16 30 -+#define R_MIPS_CALL_LO16 31 -+#define R_MIPS_SCN_DISP 32 -+#define R_MIPS_REL16 33 -+#define R_MIPS_ADD_IMMEDIATE 34 -+#define R_MIPS_PJUMP 35 -+#define R_MIPS_RELGOT 36 -+#define R_MIPS_JALR 37 -+/* Keep this the last entry. */ -+#define R_MIPS_NUM 38 -+ -+/* Legal values for p_type field of Elf32_Phdr. */ -+ -+#define PT_MIPS_REGINFO 0x70000000 /* Register usage information */ -+#define PT_MIPS_RTPROC 0x70000001 /* Runtime procedure table. */ -+#define PT_MIPS_OPTIONS 0x70000002 -+ -+/* Special program header types. */ -+ -+#define PF_MIPS_LOCAL 0x10000000 -+ -+/* Legal values for d_tag field of Elf32_Dyn. */ -+ -+#define DT_MIPS_RLD_VERSION 0x70000001 /* Runtime linker interface version */ -+#define DT_MIPS_TIME_STAMP 0x70000002 /* Timestamp */ -+#define DT_MIPS_ICHECKSUM 0x70000003 /* Checksum */ -+#define DT_MIPS_IVERSION 0x70000004 /* Version string (string tbl index) */ -+#define DT_MIPS_FLAGS 0x70000005 /* Flags */ -+#define DT_MIPS_BASE_ADDRESS 0x70000006 /* Base address */ -+#define DT_MIPS_MSYM 0x70000007 -+#define DT_MIPS_CONFLICT 0x70000008 /* Address of CONFLICT section */ -+#define DT_MIPS_LIBLIST 0x70000009 /* Address of LIBLIST section */ -+#define DT_MIPS_LOCAL_GOTNO 0x7000000a /* Number of local GOT entries */ -+#define DT_MIPS_CONFLICTNO 0x7000000b /* Number of CONFLICT entries */ -+#define DT_MIPS_LIBLISTNO 0x70000010 /* Number of LIBLIST entries */ -+#define DT_MIPS_SYMTABNO 0x70000011 /* Number of DYNSYM entries */ -+#define DT_MIPS_UNREFEXTNO 0x70000012 /* First external DYNSYM */ -+#define DT_MIPS_GOTSYM 0x70000013 /* First GOT entry in DYNSYM */ -+#define DT_MIPS_HIPAGENO 0x70000014 /* Number of GOT page table entries */ -+#define DT_MIPS_RLD_MAP 0x70000016 /* Address of run time loader map. */ -+#define DT_MIPS_DELTA_CLASS 0x70000017 /* Delta C++ class definition. */ -+#define DT_MIPS_DELTA_CLASS_NO 0x70000018 /* Number of entries in -+ DT_MIPS_DELTA_CLASS. */ -+#define DT_MIPS_DELTA_INSTANCE 0x70000019 /* Delta C++ class instances. */ -+#define DT_MIPS_DELTA_INSTANCE_NO 0x7000001a /* Number of entries in -+ DT_MIPS_DELTA_INSTANCE. */ -+#define DT_MIPS_DELTA_RELOC 0x7000001b /* Delta relocations. */ -+#define DT_MIPS_DELTA_RELOC_NO 0x7000001c /* Number of entries in -+ DT_MIPS_DELTA_RELOC. */ -+#define DT_MIPS_DELTA_SYM 0x7000001d /* Delta symbols that Delta -+ relocations refer to. */ -+#define DT_MIPS_DELTA_SYM_NO 0x7000001e /* Number of entries in -+ DT_MIPS_DELTA_SYM. */ -+#define DT_MIPS_DELTA_CLASSSYM 0x70000020 /* Delta symbols that hold the -+ class declaration. */ -+#define DT_MIPS_DELTA_CLASSSYM_NO 0x70000021 /* Number of entries in -+ DT_MIPS_DELTA_CLASSSYM. */ -+#define DT_MIPS_CXX_FLAGS 0x70000022 /* Flags indicating for C++ flavor. */ -+#define DT_MIPS_PIXIE_INIT 0x70000023 -+#define DT_MIPS_SYMBOL_LIB 0x70000024 -+#define DT_MIPS_LOCALPAGE_GOTIDX 0x70000025 -+#define DT_MIPS_LOCAL_GOTIDX 0x70000026 -+#define DT_MIPS_HIDDEN_GOTIDX 0x70000027 -+#define DT_MIPS_PROTECTED_GOTIDX 0x70000028 -+#define DT_MIPS_OPTIONS 0x70000029 /* Address of .options. */ -+#define DT_MIPS_INTERFACE 0x7000002a /* Address of .interface. */ -+#define DT_MIPS_DYNSTR_ALIGN 0x7000002b -+#define DT_MIPS_INTERFACE_SIZE 0x7000002c /* Size of the .interface section. */ -+#define DT_MIPS_RLD_TEXT_RESOLVE_ADDR 0x7000002d /* Address of rld_text_rsolve -+ function stored in GOT. */ -+#define DT_MIPS_PERF_SUFFIX 0x7000002e /* Default suffix of dso to be added -+ by rld on dlopen() calls. */ -+#define DT_MIPS_COMPACT_SIZE 0x7000002f /* (O32)Size of compact rel section. */ -+#define DT_MIPS_GP_VALUE 0x70000030 /* GP value for aux GOTs. */ -+#define DT_MIPS_AUX_DYNAMIC 0x70000031 /* Address of aux .dynamic. */ -+#define DT_MIPS_NUM 0x32 -+ -+/* Legal values for DT_MIPS_FLAGS Elf32_Dyn entry. */ -+ -+#define RHF_NONE 0 /* No flags */ -+#define RHF_QUICKSTART (1 << 0) /* Use quickstart */ -+#define RHF_NOTPOT (1 << 1) /* Hash size not power of 2 */ -+#define RHF_NO_LIBRARY_REPLACEMENT (1 << 2) /* Ignore LD_LIBRARY_PATH */ -+#define RHF_NO_MOVE (1 << 3) -+#define RHF_SGI_ONLY (1 << 4) -+#define RHF_GUARANTEE_INIT (1 << 5) -+#define RHF_DELTA_C_PLUS_PLUS (1 << 6) -+#define RHF_GUARANTEE_START_INIT (1 << 7) -+#define RHF_PIXIE (1 << 8) -+#define RHF_DEFAULT_DELAY_LOAD (1 << 9) -+#define RHF_REQUICKSTART (1 << 10) -+#define RHF_REQUICKSTARTED (1 << 11) -+#define RHF_CORD (1 << 12) -+#define RHF_NO_UNRES_UNDEF (1 << 13) -+#define RHF_RLD_ORDER_SAFE (1 << 14) -+ -+/* Entries found in sections of type SHT_MIPS_LIBLIST. */ -+ -+typedef struct -+{ -+ Elf32_Word l_name; /* Name (string table index) */ -+ Elf32_Word l_time_stamp; /* Timestamp */ -+ Elf32_Word l_checksum; /* Checksum */ -+ Elf32_Word l_version; /* Interface version */ -+ Elf32_Word l_flags; /* Flags */ -+} Elf32_Lib; -+ -+typedef struct -+{ -+ Elf64_Word l_name; /* Name (string table index) */ -+ Elf64_Word l_time_stamp; /* Timestamp */ -+ Elf64_Word l_checksum; /* Checksum */ -+ Elf64_Word l_version; /* Interface version */ -+ Elf64_Word l_flags; /* Flags */ -+} Elf64_Lib; -+ -+ -+/* Legal values for l_flags. */ -+ -+#define LL_NONE 0 -+#define LL_EXACT_MATCH (1 << 0) /* Require exact match */ -+#define LL_IGNORE_INT_VER (1 << 1) /* Ignore interface version */ -+#define LL_REQUIRE_MINOR (1 << 2) -+#define LL_EXPORTS (1 << 3) -+#define LL_DELAY_LOAD (1 << 4) -+#define LL_DELTA (1 << 5) -+ -+/* Entries found in sections of type SHT_MIPS_CONFLICT. */ -+ -+typedef Elf32_Addr Elf32_Conflict; -+ -+ -+/* HPPA specific definitions. */ -+ -+/* Legal values for e_flags field of Elf32_Ehdr. */ -+ -+#define EF_PARISC_TRAPNIL 0x00010000 /* Trap nil pointer dereference. */ -+#define EF_PARISC_EXT 0x00020000 /* Program uses arch. extensions. */ -+#define EF_PARISC_LSB 0x00040000 /* Program expects little endian. */ -+#define EF_PARISC_WIDE 0x00080000 /* Program expects wide mode. */ -+#define EF_PARISC_NO_KABP 0x00100000 /* No kernel assisted branch -+ prediction. */ -+#define EF_PARISC_LAZYSWAP 0x00400000 /* Allow lazy swapping. */ -+#define EF_PARISC_ARCH 0x0000ffff /* Architecture version. */ -+ -+/* Defined values for `e_flags & EF_PARISC_ARCH' are: */ -+ -+#define EFA_PARISC_1_0 0x020b /* PA-RISC 1.0 big-endian. */ -+#define EFA_PARISC_1_1 0x0210 /* PA-RISC 1.1 big-endian. */ -+#define EFA_PARISC_2_0 0x0214 /* PA-RISC 2.0 big-endian. */ -+ -+/* Additional section indeces. */ -+ -+#define SHN_PARISC_ANSI_COMMON 0xff00 /* Section for tenatively declared -+ symbols in ANSI C. */ -+#define SHN_PARISC_HUGE_COMMON 0xff01 /* Common blocks in huge model. */ -+ -+/* Legal values for sh_type field of Elf32_Shdr. */ -+ -+#define SHT_PARISC_EXT 0x70000000 /* Contains product specific ext. */ -+#define SHT_PARISC_UNWIND 0x70000001 /* Unwind information. */ -+#define SHT_PARISC_DOC 0x70000002 /* Debug info for optimized code. */ -+ -+/* Legal values for sh_flags field of Elf32_Shdr. */ -+ -+#define SHF_PARISC_SHORT 0x20000000 /* Section with short addressing. */ -+#define SHF_PARISC_HUGE 0x40000000 /* Section far from gp. */ -+#define SHF_PARISC_SBP 0x80000000 /* Static branch prediction code. */ -+ -+/* Legal values for ST_TYPE subfield of st_info (symbol type). */ -+ -+#define STT_PARISC_MILLICODE 13 /* Millicode function entry point. */ -+ -+#define STT_HP_OPAQUE (STT_LOOS + 0x1) -+#define STT_HP_STUB (STT_LOOS + 0x2) -+ -+/* HPPA relocs. */ -+ -+#define R_PARISC_NONE 0 /* No reloc. */ -+#define R_PARISC_DIR32 1 /* Direct 32-bit reference. */ -+#define R_PARISC_DIR21L 2 /* Left 21 bits of eff. address. */ -+#define R_PARISC_DIR17R 3 /* Right 17 bits of eff. address. */ -+#define R_PARISC_DIR17F 4 /* 17 bits of eff. address. */ -+#define R_PARISC_DIR14R 6 /* Right 14 bits of eff. address. */ -+#define R_PARISC_PCREL32 9 /* 32-bit rel. address. */ -+#define R_PARISC_PCREL21L 10 /* Left 21 bits of rel. address. */ -+#define R_PARISC_PCREL17R 11 /* Right 17 bits of rel. address. */ -+#define R_PARISC_PCREL17F 12 /* 17 bits of rel. address. */ -+#define R_PARISC_PCREL14R 14 /* Right 14 bits of rel. address. */ -+#define R_PARISC_DPREL21L 18 /* Left 21 bits of rel. address. */ -+#define R_PARISC_DPREL14R 22 /* Right 14 bits of rel. address. */ -+#define R_PARISC_GPREL21L 26 /* GP-relative, left 21 bits. */ -+#define R_PARISC_GPREL14R 30 /* GP-relative, right 14 bits. */ -+#define R_PARISC_LTOFF21L 34 /* LT-relative, left 21 bits. */ -+#define R_PARISC_LTOFF14R 38 /* LT-relative, right 14 bits. */ -+#define R_PARISC_SECREL32 41 /* 32 bits section rel. address. */ -+#define R_PARISC_SEGBASE 48 /* No relocation, set segment base. */ -+#define R_PARISC_SEGREL32 49 /* 32 bits segment rel. address. */ -+#define R_PARISC_PLTOFF21L 50 /* PLT rel. address, left 21 bits. */ -+#define R_PARISC_PLTOFF14R 54 /* PLT rel. address, right 14 bits. */ -+#define R_PARISC_LTOFF_FPTR32 57 /* 32 bits LT-rel. function pointer. */ -+#define R_PARISC_LTOFF_FPTR21L 58 /* LT-rel. fct ptr, left 21 bits. */ -+#define R_PARISC_LTOFF_FPTR14R 62 /* LT-rel. fct ptr, right 14 bits. */ -+#define R_PARISC_FPTR64 64 /* 64 bits function address. */ -+#define R_PARISC_PLABEL32 65 /* 32 bits function address. */ -+#define R_PARISC_PCREL64 72 /* 64 bits PC-rel. address. */ -+#define R_PARISC_PCREL22F 74 /* 22 bits PC-rel. address. */ -+#define R_PARISC_PCREL14WR 75 /* PC-rel. address, right 14 bits. */ -+#define R_PARISC_PCREL14DR 76 /* PC rel. address, right 14 bits. */ -+#define R_PARISC_PCREL16F 77 /* 16 bits PC-rel. address. */ -+#define R_PARISC_PCREL16WF 78 /* 16 bits PC-rel. address. */ -+#define R_PARISC_PCREL16DF 79 /* 16 bits PC-rel. address. */ -+#define R_PARISC_DIR64 80 /* 64 bits of eff. address. */ -+#define R_PARISC_DIR14WR 83 /* 14 bits of eff. address. */ -+#define R_PARISC_DIR14DR 84 /* 14 bits of eff. address. */ -+#define R_PARISC_DIR16F 85 /* 16 bits of eff. address. */ -+#define R_PARISC_DIR16WF 86 /* 16 bits of eff. address. */ -+#define R_PARISC_DIR16DF 87 /* 16 bits of eff. address. */ -+#define R_PARISC_GPREL64 88 /* 64 bits of GP-rel. address. */ -+#define R_PARISC_GPREL14WR 91 /* GP-rel. address, right 14 bits. */ -+#define R_PARISC_GPREL14DR 92 /* GP-rel. address, right 14 bits. */ -+#define R_PARISC_GPREL16F 93 /* 16 bits GP-rel. address. */ -+#define R_PARISC_GPREL16WF 94 /* 16 bits GP-rel. address. */ -+#define R_PARISC_GPREL16DF 95 /* 16 bits GP-rel. address. */ -+#define R_PARISC_LTOFF64 96 /* 64 bits LT-rel. address. */ -+#define R_PARISC_LTOFF14WR 99 /* LT-rel. address, right 14 bits. */ -+#define R_PARISC_LTOFF14DR 100 /* LT-rel. address, right 14 bits. */ -+#define R_PARISC_LTOFF16F 101 /* 16 bits LT-rel. address. */ -+#define R_PARISC_LTOFF16WF 102 /* 16 bits LT-rel. address. */ -+#define R_PARISC_LTOFF16DF 103 /* 16 bits LT-rel. address. */ -+#define R_PARISC_SECREL64 104 /* 64 bits section rel. address. */ -+#define R_PARISC_SEGREL64 112 /* 64 bits segment rel. address. */ -+#define R_PARISC_PLTOFF14WR 115 /* PLT-rel. address, right 14 bits. */ -+#define R_PARISC_PLTOFF14DR 116 /* PLT-rel. address, right 14 bits. */ -+#define R_PARISC_PLTOFF16F 117 /* 16 bits LT-rel. address. */ -+#define R_PARISC_PLTOFF16WF 118 /* 16 bits PLT-rel. address. */ -+#define R_PARISC_PLTOFF16DF 119 /* 16 bits PLT-rel. address. */ -+#define R_PARISC_LTOFF_FPTR64 120 /* 64 bits LT-rel. function ptr. */ -+#define R_PARISC_LTOFF_FPTR14WR 123 /* LT-rel. fct. ptr., right 14 bits. */ -+#define R_PARISC_LTOFF_FPTR14DR 124 /* LT-rel. fct. ptr., right 14 bits. */ -+#define R_PARISC_LTOFF_FPTR16F 125 /* 16 bits LT-rel. function ptr. */ -+#define R_PARISC_LTOFF_FPTR16WF 126 /* 16 bits LT-rel. function ptr. */ -+#define R_PARISC_LTOFF_FPTR16DF 127 /* 16 bits LT-rel. function ptr. */ -+#define R_PARISC_LORESERVE 128 -+#define R_PARISC_COPY 128 /* Copy relocation. */ -+#define R_PARISC_IPLT 129 /* Dynamic reloc, imported PLT */ -+#define R_PARISC_EPLT 130 /* Dynamic reloc, exported PLT */ -+#define R_PARISC_TPREL32 153 /* 32 bits TP-rel. address. */ -+#define R_PARISC_TPREL21L 154 /* TP-rel. address, left 21 bits. */ -+#define R_PARISC_TPREL14R 158 /* TP-rel. address, right 14 bits. */ -+#define R_PARISC_LTOFF_TP21L 162 /* LT-TP-rel. address, left 21 bits. */ -+#define R_PARISC_LTOFF_TP14R 166 /* LT-TP-rel. address, right 14 bits.*/ -+#define R_PARISC_LTOFF_TP14F 167 /* 14 bits LT-TP-rel. address. */ -+#define R_PARISC_TPREL64 216 /* 64 bits TP-rel. address. */ -+#define R_PARISC_TPREL14WR 219 /* TP-rel. address, right 14 bits. */ -+#define R_PARISC_TPREL14DR 220 /* TP-rel. address, right 14 bits. */ -+#define R_PARISC_TPREL16F 221 /* 16 bits TP-rel. address. */ -+#define R_PARISC_TPREL16WF 222 /* 16 bits TP-rel. address. */ -+#define R_PARISC_TPREL16DF 223 /* 16 bits TP-rel. address. */ -+#define R_PARISC_LTOFF_TP64 224 /* 64 bits LT-TP-rel. address. */ -+#define R_PARISC_LTOFF_TP14WR 227 /* LT-TP-rel. address, right 14 bits.*/ -+#define R_PARISC_LTOFF_TP14DR 228 /* LT-TP-rel. address, right 14 bits.*/ -+#define R_PARISC_LTOFF_TP16F 229 /* 16 bits LT-TP-rel. address. */ -+#define R_PARISC_LTOFF_TP16WF 230 /* 16 bits LT-TP-rel. address. */ -+#define R_PARISC_LTOFF_TP16DF 231 /* 16 bits LT-TP-rel. address. */ -+#define R_PARISC_HIRESERVE 255 -+ -+/* Legal values for p_type field of Elf32_Phdr/Elf64_Phdr. */ -+ -+#define PT_HP_TLS (PT_LOOS + 0x0) -+#define PT_HP_CORE_NONE (PT_LOOS + 0x1) -+#define PT_HP_CORE_VERSION (PT_LOOS + 0x2) -+#define PT_HP_CORE_KERNEL (PT_LOOS + 0x3) -+#define PT_HP_CORE_COMM (PT_LOOS + 0x4) -+#define PT_HP_CORE_PROC (PT_LOOS + 0x5) -+#define PT_HP_CORE_LOADABLE (PT_LOOS + 0x6) -+#define PT_HP_CORE_STACK (PT_LOOS + 0x7) -+#define PT_HP_CORE_SHM (PT_LOOS + 0x8) -+#define PT_HP_CORE_MMF (PT_LOOS + 0x9) -+#define PT_HP_PARALLEL (PT_LOOS + 0x10) -+#define PT_HP_FASTBIND (PT_LOOS + 0x11) -+#define PT_HP_OPT_ANNOT (PT_LOOS + 0x12) -+#define PT_HP_HSL_ANNOT (PT_LOOS + 0x13) -+#define PT_HP_STACK (PT_LOOS + 0x14) -+ -+#define PT_PARISC_ARCHEXT 0x70000000 -+#define PT_PARISC_UNWIND 0x70000001 -+ -+/* Legal values for p_flags field of Elf32_Phdr/Elf64_Phdr. */ -+ -+#define PF_PARISC_SBP 0x08000000 -+ -+#define PF_HP_PAGE_SIZE 0x00100000 -+#define PF_HP_FAR_SHARED 0x00200000 -+#define PF_HP_NEAR_SHARED 0x00400000 -+#define PF_HP_CODE 0x01000000 -+#define PF_HP_MODIFY 0x02000000 -+#define PF_HP_LAZYSWAP 0x04000000 -+#define PF_HP_SBP 0x08000000 -+ -+ -+/* Alpha specific definitions. */ -+ -+/* Legal values for e_flags field of Elf64_Ehdr. */ -+ -+#define EF_ALPHA_32BIT 1 /* All addresses must be < 2GB. */ -+#define EF_ALPHA_CANRELAX 2 /* Relocations for relaxing exist. */ -+ -+/* Legal values for sh_type field of Elf64_Shdr. */ -+ -+/* These two are primerily concerned with ECOFF debugging info. */ -+#define SHT_ALPHA_DEBUG 0x70000001 -+#define SHT_ALPHA_REGINFO 0x70000002 -+ -+/* Legal values for sh_flags field of Elf64_Shdr. */ -+ -+#define SHF_ALPHA_GPREL 0x10000000 -+ -+/* Legal values for st_other field of Elf64_Sym. */ -+#define STO_ALPHA_NOPV 0x80 /* No PV required. */ -+#define STO_ALPHA_STD_GPLOAD 0x88 /* PV only used for initial ldgp. */ -+ -+/* Alpha relocs. */ -+ -+#define R_ALPHA_NONE 0 /* No reloc */ -+#define R_ALPHA_REFLONG 1 /* Direct 32 bit */ -+#define R_ALPHA_REFQUAD 2 /* Direct 64 bit */ -+#define R_ALPHA_GPREL32 3 /* GP relative 32 bit */ -+#define R_ALPHA_LITERAL 4 /* GP relative 16 bit w/optimization */ -+#define R_ALPHA_LITUSE 5 /* Optimization hint for LITERAL */ -+#define R_ALPHA_GPDISP 6 /* Add displacement to GP */ -+#define R_ALPHA_BRADDR 7 /* PC+4 relative 23 bit shifted */ -+#define R_ALPHA_HINT 8 /* PC+4 relative 16 bit shifted */ -+#define R_ALPHA_SREL16 9 /* PC relative 16 bit */ -+#define R_ALPHA_SREL32 10 /* PC relative 32 bit */ -+#define R_ALPHA_SREL64 11 /* PC relative 64 bit */ -+#define R_ALPHA_GPRELHIGH 17 /* GP relative 32 bit, high 16 bits */ -+#define R_ALPHA_GPRELLOW 18 /* GP relative 32 bit, low 16 bits */ -+#define R_ALPHA_GPREL16 19 /* GP relative 16 bit */ -+#define R_ALPHA_COPY 24 /* Copy symbol at runtime */ -+#define R_ALPHA_GLOB_DAT 25 /* Create GOT entry */ -+#define R_ALPHA_JMP_SLOT 26 /* Create PLT entry */ -+#define R_ALPHA_RELATIVE 27 /* Adjust by program base */ -+#define R_ALPHA_TLS_GD_HI 28 -+#define R_ALPHA_TLSGD 29 -+#define R_ALPHA_TLS_LDM 30 -+#define R_ALPHA_DTPMOD64 31 -+#define R_ALPHA_GOTDTPREL 32 -+#define R_ALPHA_DTPREL64 33 -+#define R_ALPHA_DTPRELHI 34 -+#define R_ALPHA_DTPRELLO 35 -+#define R_ALPHA_DTPREL16 36 -+#define R_ALPHA_GOTTPREL 37 -+#define R_ALPHA_TPREL64 38 -+#define R_ALPHA_TPRELHI 39 -+#define R_ALPHA_TPRELLO 40 -+#define R_ALPHA_TPREL16 41 -+/* Keep this the last entry. */ -+#define R_ALPHA_NUM 46 -+ -+/* Magic values of the LITUSE relocation addend. */ -+#define LITUSE_ALPHA_ADDR 0 -+#define LITUSE_ALPHA_BASE 1 -+#define LITUSE_ALPHA_BYTOFF 2 -+#define LITUSE_ALPHA_JSR 3 -+#define LITUSE_ALPHA_TLS_GD 4 -+#define LITUSE_ALPHA_TLS_LDM 5 -+ -+ -+/* PowerPC specific declarations */ -+ -+/* Values for Elf32/64_Ehdr.e_flags. */ -+#define EF_PPC_EMB 0x80000000 /* PowerPC embedded flag */ -+ -+/* Cygnus local bits below */ -+#define EF_PPC_RELOCATABLE 0x00010000 /* PowerPC -mrelocatable flag*/ -+#define EF_PPC_RELOCATABLE_LIB 0x00008000 /* PowerPC -mrelocatable-lib -+ flag */ -+ -+/* PowerPC relocations defined by the ABIs */ -+#define R_PPC_NONE 0 -+#define R_PPC_ADDR32 1 /* 32bit absolute address */ -+#define R_PPC_ADDR24 2 /* 26bit address, 2 bits ignored. */ -+#define R_PPC_ADDR16 3 /* 16bit absolute address */ -+#define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */ -+#define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */ -+#define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */ -+#define R_PPC_ADDR14 7 /* 16bit address, 2 bits ignored */ -+#define R_PPC_ADDR14_BRTAKEN 8 -+#define R_PPC_ADDR14_BRNTAKEN 9 -+#define R_PPC_REL24 10 /* PC relative 26 bit */ -+#define R_PPC_REL14 11 /* PC relative 16 bit */ -+#define R_PPC_REL14_BRTAKEN 12 -+#define R_PPC_REL14_BRNTAKEN 13 -+#define R_PPC_GOT16 14 -+#define R_PPC_GOT16_LO 15 -+#define R_PPC_GOT16_HI 16 -+#define R_PPC_GOT16_HA 17 -+#define R_PPC_PLTREL24 18 -+#define R_PPC_COPY 19 -+#define R_PPC_GLOB_DAT 20 -+#define R_PPC_JMP_SLOT 21 -+#define R_PPC_RELATIVE 22 -+#define R_PPC_LOCAL24PC 23 -+#define R_PPC_UADDR32 24 -+#define R_PPC_UADDR16 25 -+#define R_PPC_REL32 26 -+#define R_PPC_PLT32 27 -+#define R_PPC_PLTREL32 28 -+#define R_PPC_PLT16_LO 29 -+#define R_PPC_PLT16_HI 30 -+#define R_PPC_PLT16_HA 31 -+#define R_PPC_SDAREL16 32 -+#define R_PPC_SECTOFF 33 -+#define R_PPC_SECTOFF_LO 34 -+#define R_PPC_SECTOFF_HI 35 -+#define R_PPC_SECTOFF_HA 36 -+ -+/* PowerPC relocations defined for the TLS access ABI. */ -+#define R_PPC_TLS 67 /* none (sym+add)@tls */ -+#define R_PPC_DTPMOD32 68 /* word32 (sym+add)@dtpmod */ -+#define R_PPC_TPREL16 69 /* half16* (sym+add)@tprel */ -+#define R_PPC_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */ -+#define R_PPC_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */ -+#define R_PPC_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */ -+#define R_PPC_TPREL32 73 /* word32 (sym+add)@tprel */ -+#define R_PPC_DTPREL16 74 /* half16* (sym+add)@dtprel */ -+#define R_PPC_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */ -+#define R_PPC_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */ -+#define R_PPC_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */ -+#define R_PPC_DTPREL32 78 /* word32 (sym+add)@dtprel */ -+#define R_PPC_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */ -+#define R_PPC_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */ -+#define R_PPC_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */ -+#define R_PPC_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */ -+#define R_PPC_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */ -+#define R_PPC_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */ -+#define R_PPC_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */ -+#define R_PPC_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */ -+#define R_PPC_GOT_TPREL16 87 /* half16* (sym+add)@got@tprel */ -+#define R_PPC_GOT_TPREL16_LO 88 /* half16 (sym+add)@got@tprel@l */ -+#define R_PPC_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */ -+#define R_PPC_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */ -+#define R_PPC_GOT_DTPREL16 91 /* half16* (sym+add)@got@dtprel */ -+#define R_PPC_GOT_DTPREL16_LO 92 /* half16* (sym+add)@got@dtprel@l */ -+#define R_PPC_GOT_DTPREL16_HI 93 /* half16* (sym+add)@got@dtprel@h */ -+#define R_PPC_GOT_DTPREL16_HA 94 /* half16* (sym+add)@got@dtprel@ha */ -+ -+/* Keep this the last entry. */ -+#define R_PPC_NUM 95 -+ -+/* The remaining relocs are from the Embedded ELF ABI, and are not -+ in the SVR4 ELF ABI. */ -+#define R_PPC_EMB_NADDR32 101 -+#define R_PPC_EMB_NADDR16 102 -+#define R_PPC_EMB_NADDR16_LO 103 -+#define R_PPC_EMB_NADDR16_HI 104 -+#define R_PPC_EMB_NADDR16_HA 105 -+#define R_PPC_EMB_SDAI16 106 -+#define R_PPC_EMB_SDA2I16 107 -+#define R_PPC_EMB_SDA2REL 108 -+#define R_PPC_EMB_SDA21 109 /* 16 bit offset in SDA */ -+#define R_PPC_EMB_MRKREF 110 -+#define R_PPC_EMB_RELSEC16 111 -+#define R_PPC_EMB_RELST_LO 112 -+#define R_PPC_EMB_RELST_HI 113 -+#define R_PPC_EMB_RELST_HA 114 -+#define R_PPC_EMB_BIT_FLD 115 -+#define R_PPC_EMB_RELSDA 116 /* 16 bit relative offset in SDA */ -+ -+/* Diab tool relocations. */ -+#define R_PPC_DIAB_SDA21_LO 180 /* like EMB_SDA21, but lower 16 bit */ -+#define R_PPC_DIAB_SDA21_HI 181 /* like EMB_SDA21, but high 16 bit */ -+#define R_PPC_DIAB_SDA21_HA 182 /* like EMB_SDA21, adjusted high 16 */ -+#define R_PPC_DIAB_RELSDA_LO 183 /* like EMB_RELSDA, but lower 16 bit */ -+#define R_PPC_DIAB_RELSDA_HI 184 /* like EMB_RELSDA, but high 16 bit */ -+#define R_PPC_DIAB_RELSDA_HA 185 /* like EMB_RELSDA, adjusted high 16 */ -+ -+/* This is a phony reloc to handle any old fashioned TOC16 references -+ that may still be in object files. */ -+#define R_PPC_TOC16 255 -+ -+ -+/* PowerPC64 relocations defined by the ABIs */ -+#define R_PPC64_NONE R_PPC_NONE -+#define R_PPC64_ADDR32 R_PPC_ADDR32 /* 32bit absolute address */ -+#define R_PPC64_ADDR24 R_PPC_ADDR24 /* 26bit address, word aligned */ -+#define R_PPC64_ADDR16 R_PPC_ADDR16 /* 16bit absolute address */ -+#define R_PPC64_ADDR16_LO R_PPC_ADDR16_LO /* lower 16bits of address */ -+#define R_PPC64_ADDR16_HI R_PPC_ADDR16_HI /* high 16bits of address. */ -+#define R_PPC64_ADDR16_HA R_PPC_ADDR16_HA /* adjusted high 16bits. */ -+#define R_PPC64_ADDR14 R_PPC_ADDR14 /* 16bit address, word aligned */ -+#define R_PPC64_ADDR14_BRTAKEN R_PPC_ADDR14_BRTAKEN -+#define R_PPC64_ADDR14_BRNTAKEN R_PPC_ADDR14_BRNTAKEN -+#define R_PPC64_REL24 R_PPC_REL24 /* PC-rel. 26 bit, word aligned */ -+#define R_PPC64_REL14 R_PPC_REL14 /* PC relative 16 bit */ -+#define R_PPC64_REL14_BRTAKEN R_PPC_REL14_BRTAKEN -+#define R_PPC64_REL14_BRNTAKEN R_PPC_REL14_BRNTAKEN -+#define R_PPC64_GOT16 R_PPC_GOT16 -+#define R_PPC64_GOT16_LO R_PPC_GOT16_LO -+#define R_PPC64_GOT16_HI R_PPC_GOT16_HI -+#define R_PPC64_GOT16_HA R_PPC_GOT16_HA -+ -+#define R_PPC64_COPY R_PPC_COPY -+#define R_PPC64_GLOB_DAT R_PPC_GLOB_DAT -+#define R_PPC64_JMP_SLOT R_PPC_JMP_SLOT -+#define R_PPC64_RELATIVE R_PPC_RELATIVE -+ -+#define R_PPC64_UADDR32 R_PPC_UADDR32 -+#define R_PPC64_UADDR16 R_PPC_UADDR16 -+#define R_PPC64_REL32 R_PPC_REL32 -+#define R_PPC64_PLT32 R_PPC_PLT32 -+#define R_PPC64_PLTREL32 R_PPC_PLTREL32 -+#define R_PPC64_PLT16_LO R_PPC_PLT16_LO -+#define R_PPC64_PLT16_HI R_PPC_PLT16_HI -+#define R_PPC64_PLT16_HA R_PPC_PLT16_HA -+ -+#define R_PPC64_SECTOFF R_PPC_SECTOFF -+#define R_PPC64_SECTOFF_LO R_PPC_SECTOFF_LO -+#define R_PPC64_SECTOFF_HI R_PPC_SECTOFF_HI -+#define R_PPC64_SECTOFF_HA R_PPC_SECTOFF_HA -+#define R_PPC64_ADDR30 37 /* word30 (S + A - P) >> 2 */ -+#define R_PPC64_ADDR64 38 /* doubleword64 S + A */ -+#define R_PPC64_ADDR16_HIGHER 39 /* half16 #higher(S + A) */ -+#define R_PPC64_ADDR16_HIGHERA 40 /* half16 #highera(S + A) */ -+#define R_PPC64_ADDR16_HIGHEST 41 /* half16 #highest(S + A) */ -+#define R_PPC64_ADDR16_HIGHESTA 42 /* half16 #highesta(S + A) */ -+#define R_PPC64_UADDR64 43 /* doubleword64 S + A */ -+#define R_PPC64_REL64 44 /* doubleword64 S + A - P */ -+#define R_PPC64_PLT64 45 /* doubleword64 L + A */ -+#define R_PPC64_PLTREL64 46 /* doubleword64 L + A - P */ -+#define R_PPC64_TOC16 47 /* half16* S + A - .TOC */ -+#define R_PPC64_TOC16_LO 48 /* half16 #lo(S + A - .TOC.) */ -+#define R_PPC64_TOC16_HI 49 /* half16 #hi(S + A - .TOC.) */ -+#define R_PPC64_TOC16_HA 50 /* half16 #ha(S + A - .TOC.) */ -+#define R_PPC64_TOC 51 /* doubleword64 .TOC */ -+#define R_PPC64_PLTGOT16 52 /* half16* M + A */ -+#define R_PPC64_PLTGOT16_LO 53 /* half16 #lo(M + A) */ -+#define R_PPC64_PLTGOT16_HI 54 /* half16 #hi(M + A) */ -+#define R_PPC64_PLTGOT16_HA 55 /* half16 #ha(M + A) */ -+ -+#define R_PPC64_ADDR16_DS 56 /* half16ds* (S + A) >> 2 */ -+#define R_PPC64_ADDR16_LO_DS 57 /* half16ds #lo(S + A) >> 2 */ -+#define R_PPC64_GOT16_DS 58 /* half16ds* (G + A) >> 2 */ -+#define R_PPC64_GOT16_LO_DS 59 /* half16ds #lo(G + A) >> 2 */ -+#define R_PPC64_PLT16_LO_DS 60 /* half16ds #lo(L + A) >> 2 */ -+#define R_PPC64_SECTOFF_DS 61 /* half16ds* (R + A) >> 2 */ -+#define R_PPC64_SECTOFF_LO_DS 62 /* half16ds #lo(R + A) >> 2 */ -+#define R_PPC64_TOC16_DS 63 /* half16ds* (S + A - .TOC.) >> 2 */ -+#define R_PPC64_TOC16_LO_DS 64 /* half16ds #lo(S + A - .TOC.) >> 2 */ -+#define R_PPC64_PLTGOT16_DS 65 /* half16ds* (M + A) >> 2 */ -+#define R_PPC64_PLTGOT16_LO_DS 66 /* half16ds #lo(M + A) >> 2 */ -+ -+/* PowerPC64 relocations defined for the TLS access ABI. */ -+#define R_PPC64_TLS 67 /* none (sym+add)@tls */ -+#define R_PPC64_DTPMOD64 68 /* doubleword64 (sym+add)@dtpmod */ -+#define R_PPC64_TPREL16 69 /* half16* (sym+add)@tprel */ -+#define R_PPC64_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */ -+#define R_PPC64_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */ -+#define R_PPC64_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */ -+#define R_PPC64_TPREL64 73 /* doubleword64 (sym+add)@tprel */ -+#define R_PPC64_DTPREL16 74 /* half16* (sym+add)@dtprel */ -+#define R_PPC64_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */ -+#define R_PPC64_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */ -+#define R_PPC64_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */ -+#define R_PPC64_DTPREL64 78 /* doubleword64 (sym+add)@dtprel */ -+#define R_PPC64_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */ -+#define R_PPC64_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */ -+#define R_PPC64_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */ -+#define R_PPC64_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */ -+#define R_PPC64_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */ -+#define R_PPC64_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */ -+#define R_PPC64_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */ -+#define R_PPC64_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */ -+#define R_PPC64_GOT_TPREL16_DS 87 /* half16ds* (sym+add)@got@tprel */ -+#define R_PPC64_GOT_TPREL16_LO_DS 88 /* half16ds (sym+add)@got@tprel@l */ -+#define R_PPC64_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */ -+#define R_PPC64_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */ -+#define R_PPC64_GOT_DTPREL16_DS 91 /* half16ds* (sym+add)@got@dtprel */ -+#define R_PPC64_GOT_DTPREL16_LO_DS 92 /* half16ds (sym+add)@got@dtprel@l */ -+#define R_PPC64_GOT_DTPREL16_HI 93 /* half16 (sym+add)@got@dtprel@h */ -+#define R_PPC64_GOT_DTPREL16_HA 94 /* half16 (sym+add)@got@dtprel@ha */ -+#define R_PPC64_TPREL16_DS 95 /* half16ds* (sym+add)@tprel */ -+#define R_PPC64_TPREL16_LO_DS 96 /* half16ds (sym+add)@tprel@l */ -+#define R_PPC64_TPREL16_HIGHER 97 /* half16 (sym+add)@tprel@higher */ -+#define R_PPC64_TPREL16_HIGHERA 98 /* half16 (sym+add)@tprel@highera */ -+#define R_PPC64_TPREL16_HIGHEST 99 /* half16 (sym+add)@tprel@highest */ -+#define R_PPC64_TPREL16_HIGHESTA 100 /* half16 (sym+add)@tprel@highesta */ -+#define R_PPC64_DTPREL16_DS 101 /* half16ds* (sym+add)@dtprel */ -+#define R_PPC64_DTPREL16_LO_DS 102 /* half16ds (sym+add)@dtprel@l */ -+#define R_PPC64_DTPREL16_HIGHER 103 /* half16 (sym+add)@dtprel@higher */ -+#define R_PPC64_DTPREL16_HIGHERA 104 /* half16 (sym+add)@dtprel@highera */ -+#define R_PPC64_DTPREL16_HIGHEST 105 /* half16 (sym+add)@dtprel@highest */ -+#define R_PPC64_DTPREL16_HIGHESTA 106 /* half16 (sym+add)@dtprel@highesta */ -+ -+/* Keep this the last entry. */ -+#define R_PPC64_NUM 107 -+ -+/* PowerPC64 specific values for the Dyn d_tag field. */ -+#define DT_PPC64_GLINK (DT_LOPROC + 0) -+#define DT_PPC64_NUM 1 -+ -+ -+/* ARM specific declarations */ -+ -+/* Processor specific flags for the ELF header e_flags field. */ -+#define EF_ARM_RELEXEC 0x01 -+#define EF_ARM_HASENTRY 0x02 -+#define EF_ARM_INTERWORK 0x04 -+#define EF_ARM_APCS_26 0x08 -+#define EF_ARM_APCS_FLOAT 0x10 -+#define EF_ARM_PIC 0x20 -+#define EF_ARM_ALIGN8 0x40 /* 8-bit structure alignment is in use */ -+#define EF_ARM_NEW_ABI 0x80 -+#define EF_ARM_OLD_ABI 0x100 -+ -+/* Other constants defined in the ARM ELF spec. version B-01. */ -+/* NB. These conflict with values defined above. */ -+#define EF_ARM_SYMSARESORTED 0x04 -+#define EF_ARM_DYNSYMSUSESEGIDX 0x08 -+#define EF_ARM_MAPSYMSFIRST 0x10 -+#define EF_ARM_EABIMASK 0XFF000000 -+ -+#define EF_ARM_EABI_VERSION(flags) ((flags) & EF_ARM_EABIMASK) -+#define EF_ARM_EABI_UNKNOWN 0x00000000 -+#define EF_ARM_EABI_VER1 0x01000000 -+#define EF_ARM_EABI_VER2 0x02000000 -+ -+/* Additional symbol types for Thumb */ -+#define STT_ARM_TFUNC 0xd -+ -+/* ARM-specific values for sh_flags */ -+#define SHF_ARM_ENTRYSECT 0x10000000 /* Section contains an entry point */ -+#define SHF_ARM_COMDEF 0x80000000 /* Section may be multiply defined -+ in the input to a link step */ -+ -+/* ARM-specific program header flags */ -+#define PF_ARM_SB 0x10000000 /* Segment contains the location -+ addressed by the static base */ -+ -+/* ARM relocs. */ -+#define R_ARM_NONE 0 /* No reloc */ -+#define R_ARM_PC24 1 /* PC relative 26 bit branch */ -+#define R_ARM_ABS32 2 /* Direct 32 bit */ -+#define R_ARM_REL32 3 /* PC relative 32 bit */ -+#define R_ARM_PC13 4 -+#define R_ARM_ABS16 5 /* Direct 16 bit */ -+#define R_ARM_ABS12 6 /* Direct 12 bit */ -+#define R_ARM_THM_ABS5 7 -+#define R_ARM_ABS8 8 /* Direct 8 bit */ -+#define R_ARM_SBREL32 9 -+#define R_ARM_THM_PC22 10 -+#define R_ARM_THM_PC8 11 -+#define R_ARM_AMP_VCALL9 12 -+#define R_ARM_SWI24 13 -+#define R_ARM_THM_SWI8 14 -+#define R_ARM_XPC25 15 -+#define R_ARM_THM_XPC22 16 -+#define R_ARM_COPY 20 /* Copy symbol at runtime */ -+#define R_ARM_GLOB_DAT 21 /* Create GOT entry */ -+#define R_ARM_JUMP_SLOT 22 /* Create PLT entry */ -+#define R_ARM_RELATIVE 23 /* Adjust by program base */ -+#define R_ARM_GOTOFF 24 /* 32 bit offset to GOT */ -+#define R_ARM_GOTPC 25 /* 32 bit PC relative offset to GOT */ -+#define R_ARM_GOT32 26 /* 32 bit GOT entry */ -+#define R_ARM_PLT32 27 /* 32 bit PLT address */ -+#define R_ARM_ALU_PCREL_7_0 32 -+#define R_ARM_ALU_PCREL_15_8 33 -+#define R_ARM_ALU_PCREL_23_15 34 -+#define R_ARM_LDR_SBREL_11_0 35 -+#define R_ARM_ALU_SBREL_19_12 36 -+#define R_ARM_ALU_SBREL_27_20 37 -+#define R_ARM_GNU_VTENTRY 100 -+#define R_ARM_GNU_VTINHERIT 101 -+#define R_ARM_THM_PC11 102 /* thumb unconditional branch */ -+#define R_ARM_THM_PC9 103 /* thumb conditional branch */ -+#define R_ARM_RXPC25 249 -+#define R_ARM_RSBREL32 250 -+#define R_ARM_THM_RPC22 251 -+#define R_ARM_RREL32 252 -+#define R_ARM_RABS22 253 -+#define R_ARM_RPC24 254 -+#define R_ARM_RBASE 255 -+/* Keep this the last entry. */ -+#define R_ARM_NUM 256 -+ -+/* IA-64 specific declarations. */ -+ -+/* Processor specific flags for the Ehdr e_flags field. */ -+#define EF_IA_64_MASKOS 0x0000000f /* os-specific flags */ -+#define EF_IA_64_ABI64 0x00000010 /* 64-bit ABI */ -+#define EF_IA_64_ARCH 0xff000000 /* arch. version mask */ -+ -+/* Processor specific values for the Phdr p_type field. */ -+#define PT_IA_64_ARCHEXT (PT_LOPROC + 0) /* arch extension bits */ -+#define PT_IA_64_UNWIND (PT_LOPROC + 1) /* ia64 unwind bits */ -+ -+/* Processor specific flags for the Phdr p_flags field. */ -+#define PF_IA_64_NORECOV 0x80000000 /* spec insns w/o recovery */ -+ -+/* Processor specific values for the Shdr sh_type field. */ -+#define SHT_IA_64_EXT (SHT_LOPROC + 0) /* extension bits */ -+#define SHT_IA_64_UNWIND (SHT_LOPROC + 1) /* unwind bits */ -+ -+/* Processor specific flags for the Shdr sh_flags field. */ -+#define SHF_IA_64_SHORT 0x10000000 /* section near gp */ -+#define SHF_IA_64_NORECOV 0x20000000 /* spec insns w/o recovery */ -+ -+/* Processor specific values for the Dyn d_tag field. */ -+#define DT_IA_64_PLT_RESERVE (DT_LOPROC + 0) -+#define DT_IA_64_NUM 1 -+ -+/* IA-64 relocations. */ -+#define R_IA64_NONE 0x00 /* none */ -+#define R_IA64_IMM14 0x21 /* symbol + addend, add imm14 */ -+#define R_IA64_IMM22 0x22 /* symbol + addend, add imm22 */ -+#define R_IA64_IMM64 0x23 /* symbol + addend, mov imm64 */ -+#define R_IA64_DIR32MSB 0x24 /* symbol + addend, data4 MSB */ -+#define R_IA64_DIR32LSB 0x25 /* symbol + addend, data4 LSB */ -+#define R_IA64_DIR64MSB 0x26 /* symbol + addend, data8 MSB */ -+#define R_IA64_DIR64LSB 0x27 /* symbol + addend, data8 LSB */ -+#define R_IA64_GPREL22 0x2a /* @gprel(sym + add), add imm22 */ -+#define R_IA64_GPREL64I 0x2b /* @gprel(sym + add), mov imm64 */ -+#define R_IA64_GPREL32MSB 0x2c /* @gprel(sym + add), data4 MSB */ -+#define R_IA64_GPREL32LSB 0x2d /* @gprel(sym + add), data4 LSB */ -+#define R_IA64_GPREL64MSB 0x2e /* @gprel(sym + add), data8 MSB */ -+#define R_IA64_GPREL64LSB 0x2f /* @gprel(sym + add), data8 LSB */ -+#define R_IA64_LTOFF22 0x32 /* @ltoff(sym + add), add imm22 */ -+#define R_IA64_LTOFF64I 0x33 /* @ltoff(sym + add), mov imm64 */ -+#define R_IA64_PLTOFF22 0x3a /* @pltoff(sym + add), add imm22 */ -+#define R_IA64_PLTOFF64I 0x3b /* @pltoff(sym + add), mov imm64 */ -+#define R_IA64_PLTOFF64MSB 0x3e /* @pltoff(sym + add), data8 MSB */ -+#define R_IA64_PLTOFF64LSB 0x3f /* @pltoff(sym + add), data8 LSB */ -+#define R_IA64_FPTR64I 0x43 /* @fptr(sym + add), mov imm64 */ -+#define R_IA64_FPTR32MSB 0x44 /* @fptr(sym + add), data4 MSB */ -+#define R_IA64_FPTR32LSB 0x45 /* @fptr(sym + add), data4 LSB */ -+#define R_IA64_FPTR64MSB 0x46 /* @fptr(sym + add), data8 MSB */ -+#define R_IA64_FPTR64LSB 0x47 /* @fptr(sym + add), data8 LSB */ -+#define R_IA64_PCREL60B 0x48 /* @pcrel(sym + add), brl */ -+#define R_IA64_PCREL21B 0x49 /* @pcrel(sym + add), ptb, call */ -+#define R_IA64_PCREL21M 0x4a /* @pcrel(sym + add), chk.s */ -+#define R_IA64_PCREL21F 0x4b /* @pcrel(sym + add), fchkf */ -+#define R_IA64_PCREL32MSB 0x4c /* @pcrel(sym + add), data4 MSB */ -+#define R_IA64_PCREL32LSB 0x4d /* @pcrel(sym + add), data4 LSB */ -+#define R_IA64_PCREL64MSB 0x4e /* @pcrel(sym + add), data8 MSB */ -+#define R_IA64_PCREL64LSB 0x4f /* @pcrel(sym + add), data8 LSB */ -+#define R_IA64_LTOFF_FPTR22 0x52 /* @ltoff(@fptr(s+a)), imm22 */ -+#define R_IA64_LTOFF_FPTR64I 0x53 /* @ltoff(@fptr(s+a)), imm64 */ -+#define R_IA64_LTOFF_FPTR32MSB 0x54 /* @ltoff(@fptr(s+a)), data4 MSB */ -+#define R_IA64_LTOFF_FPTR32LSB 0x55 /* @ltoff(@fptr(s+a)), data4 LSB */ -+#define R_IA64_LTOFF_FPTR64MSB 0x56 /* @ltoff(@fptr(s+a)), data8 MSB */ -+#define R_IA64_LTOFF_FPTR64LSB 0x57 /* @ltoff(@fptr(s+a)), data8 LSB */ -+#define R_IA64_SEGREL32MSB 0x5c /* @segrel(sym + add), data4 MSB */ -+#define R_IA64_SEGREL32LSB 0x5d /* @segrel(sym + add), data4 LSB */ -+#define R_IA64_SEGREL64MSB 0x5e /* @segrel(sym + add), data8 MSB */ -+#define R_IA64_SEGREL64LSB 0x5f /* @segrel(sym + add), data8 LSB */ -+#define R_IA64_SECREL32MSB 0x64 /* @secrel(sym + add), data4 MSB */ -+#define R_IA64_SECREL32LSB 0x65 /* @secrel(sym + add), data4 LSB */ -+#define R_IA64_SECREL64MSB 0x66 /* @secrel(sym + add), data8 MSB */ -+#define R_IA64_SECREL64LSB 0x67 /* @secrel(sym + add), data8 LSB */ -+#define R_IA64_REL32MSB 0x6c /* data 4 + REL */ -+#define R_IA64_REL32LSB 0x6d /* data 4 + REL */ -+#define R_IA64_REL64MSB 0x6e /* data 8 + REL */ -+#define R_IA64_REL64LSB 0x6f /* data 8 + REL */ -+#define R_IA64_LTV32MSB 0x74 /* symbol + addend, data4 MSB */ -+#define R_IA64_LTV32LSB 0x75 /* symbol + addend, data4 LSB */ -+#define R_IA64_LTV64MSB 0x76 /* symbol + addend, data8 MSB */ -+#define R_IA64_LTV64LSB 0x77 /* symbol + addend, data8 LSB */ -+#define R_IA64_PCREL21BI 0x79 /* @pcrel(sym + add), 21bit inst */ -+#define R_IA64_PCREL22 0x7a /* @pcrel(sym + add), 22bit inst */ -+#define R_IA64_PCREL64I 0x7b /* @pcrel(sym + add), 64bit inst */ -+#define R_IA64_IPLTMSB 0x80 /* dynamic reloc, imported PLT, MSB */ -+#define R_IA64_IPLTLSB 0x81 /* dynamic reloc, imported PLT, LSB */ -+#define R_IA64_COPY 0x84 /* copy relocation */ -+#define R_IA64_SUB 0x85 /* Addend and symbol difference */ -+#define R_IA64_LTOFF22X 0x86 /* LTOFF22, relaxable. */ -+#define R_IA64_LDXMOV 0x87 /* Use of LTOFF22X. */ -+#define R_IA64_TPREL14 0x91 /* @tprel(sym + add), imm14 */ -+#define R_IA64_TPREL22 0x92 /* @tprel(sym + add), imm22 */ -+#define R_IA64_TPREL64I 0x93 /* @tprel(sym + add), imm64 */ -+#define R_IA64_TPREL64MSB 0x96 /* @tprel(sym + add), data8 MSB */ -+#define R_IA64_TPREL64LSB 0x97 /* @tprel(sym + add), data8 LSB */ -+#define R_IA64_LTOFF_TPREL22 0x9a /* @ltoff(@tprel(s+a)), imm2 */ -+#define R_IA64_DTPMOD64MSB 0xa6 /* @dtpmod(sym + add), data8 MSB */ -+#define R_IA64_DTPMOD64LSB 0xa7 /* @dtpmod(sym + add), data8 LSB */ -+#define R_IA64_LTOFF_DTPMOD22 0xaa /* @ltoff(@dtpmod(sym + add)), imm22 */ -+#define R_IA64_DTPREL14 0xb1 /* @dtprel(sym + add), imm14 */ -+#define R_IA64_DTPREL22 0xb2 /* @dtprel(sym + add), imm22 */ -+#define R_IA64_DTPREL64I 0xb3 /* @dtprel(sym + add), imm64 */ -+#define R_IA64_DTPREL32MSB 0xb4 /* @dtprel(sym + add), data4 MSB */ -+#define R_IA64_DTPREL32LSB 0xb5 /* @dtprel(sym + add), data4 LSB */ -+#define R_IA64_DTPREL64MSB 0xb6 /* @dtprel(sym + add), data8 MSB */ -+#define R_IA64_DTPREL64LSB 0xb7 /* @dtprel(sym + add), data8 LSB */ -+#define R_IA64_LTOFF_DTPREL22 0xba /* @ltoff(@dtprel(s+a)), imm22 */ -+ -+/* SH specific declarations */ -+ -+/* SH relocs. */ -+#define R_SH_NONE 0 -+#define R_SH_DIR32 1 -+#define R_SH_REL32 2 -+#define R_SH_DIR8WPN 3 -+#define R_SH_IND12W 4 -+#define R_SH_DIR8WPL 5 -+#define R_SH_DIR8WPZ 6 -+#define R_SH_DIR8BP 7 -+#define R_SH_DIR8W 8 -+#define R_SH_DIR8L 9 -+#define R_SH_SWITCH16 25 -+#define R_SH_SWITCH32 26 -+#define R_SH_USES 27 -+#define R_SH_COUNT 28 -+#define R_SH_ALIGN 29 -+#define R_SH_CODE 30 -+#define R_SH_DATA 31 -+#define R_SH_LABEL 32 -+#define R_SH_SWITCH8 33 -+#define R_SH_GNU_VTINHERIT 34 -+#define R_SH_GNU_VTENTRY 35 -+#define R_SH_TLS_GD_32 144 -+#define R_SH_TLS_LD_32 145 -+#define R_SH_TLS_LDO_32 146 -+#define R_SH_TLS_IE_32 147 -+#define R_SH_TLS_LE_32 148 -+#define R_SH_TLS_DTPMOD32 149 -+#define R_SH_TLS_DTPOFF32 150 -+#define R_SH_TLS_TPOFF32 151 -+#define R_SH_GOT32 160 -+#define R_SH_PLT32 161 -+#define R_SH_COPY 162 -+#define R_SH_GLOB_DAT 163 -+#define R_SH_JMP_SLOT 164 -+#define R_SH_RELATIVE 165 -+#define R_SH_GOTOFF 166 -+#define R_SH_GOTPC 167 -+/* Keep this the last entry. */ -+#define R_SH_NUM 256 -+ -+/* Additional s390 relocs */ -+ -+#define R_390_NONE 0 /* No reloc. */ -+#define R_390_8 1 /* Direct 8 bit. */ -+#define R_390_12 2 /* Direct 12 bit. */ -+#define R_390_16 3 /* Direct 16 bit. */ -+#define R_390_32 4 /* Direct 32 bit. */ -+#define R_390_PC32 5 /* PC relative 32 bit. */ -+#define R_390_GOT12 6 /* 12 bit GOT offset. */ -+#define R_390_GOT32 7 /* 32 bit GOT offset. */ -+#define R_390_PLT32 8 /* 32 bit PC relative PLT address. */ -+#define R_390_COPY 9 /* Copy symbol at runtime. */ -+#define R_390_GLOB_DAT 10 /* Create GOT entry. */ -+#define R_390_JMP_SLOT 11 /* Create PLT entry. */ -+#define R_390_RELATIVE 12 /* Adjust by program base. */ -+#define R_390_GOTOFF32 13 /* 32 bit offset to GOT. */ -+#define R_390_GOTPC 14 /* 32 bit PC relative offset to GOT. */ -+#define R_390_GOT16 15 /* 16 bit GOT offset. */ -+#define R_390_PC16 16 /* PC relative 16 bit. */ -+#define R_390_PC16DBL 17 /* PC relative 16 bit shifted by 1. */ -+#define R_390_PLT16DBL 18 /* 16 bit PC rel. PLT shifted by 1. */ -+#define R_390_PC32DBL 19 /* PC relative 32 bit shifted by 1. */ -+#define R_390_PLT32DBL 20 /* 32 bit PC rel. PLT shifted by 1. */ -+#define R_390_GOTPCDBL 21 /* 32 bit PC rel. GOT shifted by 1. */ -+#define R_390_64 22 /* Direct 64 bit. */ -+#define R_390_PC64 23 /* PC relative 64 bit. */ -+#define R_390_GOT64 24 /* 64 bit GOT offset. */ -+#define R_390_PLT64 25 /* 64 bit PC relative PLT address. */ -+#define R_390_GOTENT 26 /* 32 bit PC rel. to GOT entry >> 1. */ -+#define R_390_GOTOFF16 27 /* 16 bit offset to GOT. */ -+#define R_390_GOTOFF64 28 /* 64 bit offset to GOT. */ -+#define R_390_GOTPLT12 29 /* 12 bit offset to jump slot. */ -+#define R_390_GOTPLT16 30 /* 16 bit offset to jump slot. */ -+#define R_390_GOTPLT32 31 /* 32 bit offset to jump slot. */ -+#define R_390_GOTPLT64 32 /* 64 bit offset to jump slot. */ -+#define R_390_GOTPLTENT 33 /* 32 bit rel. offset to jump slot. */ -+#define R_390_PLTOFF16 34 /* 16 bit offset from GOT to PLT. */ -+#define R_390_PLTOFF32 35 /* 32 bit offset from GOT to PLT. */ -+#define R_390_PLTOFF64 36 /* 16 bit offset from GOT to PLT. */ -+#define R_390_TLS_LOAD 37 /* Tag for load insn in TLS code. */ -+#define R_390_TLS_GDCALL 38 /* Tag for function call in general -+ dynamic TLS code. */ -+#define R_390_TLS_LDCALL 39 /* Tag for function call in local -+ dynamic TLS code. */ -+#define R_390_TLS_GD32 40 /* Direct 32 bit for general dynamic -+ thread local data. */ -+#define R_390_TLS_GD64 41 /* Direct 64 bit for general dynamic -+ thread local data. */ -+#define R_390_TLS_GOTIE12 42 /* 12 bit GOT offset for static TLS -+ block offset. */ -+#define R_390_TLS_GOTIE32 43 /* 32 bit GOT offset for static TLS -+ block offset. */ -+#define R_390_TLS_GOTIE64 44 /* 64 bit GOT offset for static TLS -+ block offset. */ -+#define R_390_TLS_LDM32 45 /* Direct 32 bit for local dynamic -+ thread local data in LE code. */ -+#define R_390_TLS_LDM64 46 /* Direct 64 bit for local dynamic -+ thread local data in LE code. */ -+#define R_390_TLS_IE32 47 /* 32 bit address of GOT entry for -+ negated static TLS block offset. */ -+#define R_390_TLS_IE64 48 /* 64 bit address of GOT entry for -+ negated static TLS block offset. */ -+#define R_390_TLS_IEENT 49 /* 32 bit rel. offset to GOT entry for -+ negated static TLS block offset. */ -+#define R_390_TLS_LE32 50 /* 32 bit negated offset relative to -+ static TLS block. */ -+#define R_390_TLS_LE64 51 /* 64 bit negated offset relative to -+ static TLS block. */ -+#define R_390_TLS_LDO32 52 /* 32 bit offset relative to TLS -+ block. */ -+#define R_390_TLS_LDO64 53 /* 64 bit offset relative to TLS -+ block. */ -+#define R_390_TLS_DTPMOD 54 /* ID of module containing symbol. */ -+#define R_390_TLS_DTPOFF 55 /* Offset in TLS block. */ -+#define R_390_TLS_TPOFF 56 /* Negated offset in static TLS -+ block. */ -+ -+/* Keep this the last entry. */ -+#define R_390_NUM 57 -+ -+/* CRIS relocations. */ -+#define R_CRIS_NONE 0 -+#define R_CRIS_8 1 -+#define R_CRIS_16 2 -+#define R_CRIS_32 3 -+#define R_CRIS_8_PCREL 4 -+#define R_CRIS_16_PCREL 5 -+#define R_CRIS_32_PCREL 6 -+#define R_CRIS_GNU_VTINHERIT 7 -+#define R_CRIS_GNU_VTENTRY 8 -+#define R_CRIS_COPY 9 -+#define R_CRIS_GLOB_DAT 10 -+#define R_CRIS_JUMP_SLOT 11 -+#define R_CRIS_RELATIVE 12 -+#define R_CRIS_16_GOT 13 -+#define R_CRIS_32_GOT 14 -+#define R_CRIS_16_GOTPLT 15 -+#define R_CRIS_32_GOTPLT 16 -+#define R_CRIS_32_GOTREL 17 -+#define R_CRIS_32_PLT_GOTREL 18 -+#define R_CRIS_32_PLT_PCREL 19 -+ -+#define R_CRIS_NUM 20 -+ -+/* AMD x86-64 relocations. */ -+#define R_X86_64_NONE 0 /* No reloc */ -+#define R_X86_64_64 1 /* Direct 64 bit */ -+#define R_X86_64_PC32 2 /* PC relative 32 bit signed */ -+#define R_X86_64_GOT32 3 /* 32 bit GOT entry */ -+#define R_X86_64_PLT32 4 /* 32 bit PLT address */ -+#define R_X86_64_COPY 5 /* Copy symbol at runtime */ -+#define R_X86_64_GLOB_DAT 6 /* Create GOT entry */ -+#define R_X86_64_JUMP_SLOT 7 /* Create PLT entry */ -+#define R_X86_64_RELATIVE 8 /* Adjust by program base */ -+#define R_X86_64_GOTPCREL 9 /* 32 bit signed PC relative -+ offset to GOT */ -+#define R_X86_64_32 10 /* Direct 32 bit zero extended */ -+#define R_X86_64_32S 11 /* Direct 32 bit sign extended */ -+#define R_X86_64_16 12 /* Direct 16 bit zero extended */ -+#define R_X86_64_PC16 13 /* 16 bit sign extended pc relative */ -+#define R_X86_64_8 14 /* Direct 8 bit sign extended */ -+#define R_X86_64_PC8 15 /* 8 bit sign extended pc relative */ -+#define R_X86_64_DTPMOD64 16 /* ID of module containing symbol */ -+#define R_X86_64_DTPOFF64 17 /* Offset in module's TLS block */ -+#define R_X86_64_TPOFF64 18 /* Offset in initial TLS block */ -+#define R_X86_64_TLSGD 19 /* 32 bit signed PC relative offset -+ to two GOT entries for GD symbol */ -+#define R_X86_64_TLSLD 20 /* 32 bit signed PC relative offset -+ to two GOT entries for LD symbol */ -+#define R_X86_64_DTPOFF32 21 /* Offset in TLS block */ -+#define R_X86_64_GOTTPOFF 22 /* 32 bit signed PC relative offset -+ to GOT entry for IE symbol */ -+#define R_X86_64_TPOFF32 23 /* Offset in initial TLS block */ -+ -+#define R_X86_64_NUM 24 -+ -+__END_DECLS -+ -+#endif /* elf.h */ - - #include "elfconfig.h" - -@@ -195,3 +2641,4 @@ - void fatal(const char *fmt, ...); - void warn(const char *fmt, ...); - void merror(const char *fmt, ...); -+ -diff -Nur linux-2.6.36.orig/scripts/mod/sumversion.c linux-2.6.36/scripts/mod/sumversion.c ---- linux-2.6.36.orig/scripts/mod/sumversion.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/scripts/mod/sumversion.c 2010-11-28 18:33:24.000000000 +0100 -@@ -1,4 +1,4 @@ --#include -+/* #include */ - #ifdef __sun__ - #include - #else diff --git a/target/linux/patches/3.0.4/cris-etrax.patch b/target/linux/patches/3.0.4/cris-etrax.patch deleted file mode 100644 index a80d9a8b8..000000000 --- a/target/linux/patches/3.0.4/cris-etrax.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff -Nur linux-2.6.39.orig/arch/cris/arch-v32/drivers/i2c.h linux-2.6.39/arch/cris/arch-v32/drivers/i2c.h ---- linux-2.6.39.orig/arch/cris/arch-v32/drivers/i2c.h 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/arch/cris/arch-v32/drivers/i2c.h 2011-08-24 19:15:05.000000000 +0200 -@@ -2,7 +2,7 @@ - #include - - /* High level I2C actions */ --int __init i2c_init(void); -+static int __init i2c_init(void); - int i2c_write(unsigned char theSlave, void *data, size_t nbytes); - int i2c_read(unsigned char theSlave, void *data, size_t nbytes); - int i2c_writereg(unsigned char theSlave, unsigned char theReg, unsigned char theValue); diff --git a/target/linux/patches/3.0.4/defaults.patch b/target/linux/patches/3.0.4/defaults.patch deleted file mode 100644 index 58aae610b..000000000 --- a/target/linux/patches/3.0.4/defaults.patch +++ /dev/null @@ -1,22 +0,0 @@ -diff -Nur linux-3.0.4.orig/fs/Kconfig linux-3.0.4/fs/Kconfig ---- linux-3.0.4.orig/fs/Kconfig 2011-08-29 22:56:30.000000000 +0200 -+++ linux-3.0.4/fs/Kconfig 2011-10-15 22:08:44.000000000 +0200 -@@ -47,7 +47,7 @@ - def_bool n - - config EXPORTFS -- tristate -+ def_bool y - - config FILE_LOCKING - bool "Enable POSIX file locking API" if EXPERT -diff -Nur linux-3.0.4.orig/fs/notify/Kconfig linux-3.0.4/fs/notify/Kconfig ---- linux-3.0.4.orig/fs/notify/Kconfig 2011-08-29 22:56:30.000000000 +0200 -+++ linux-3.0.4/fs/notify/Kconfig 2011-10-15 22:02:00.000000000 +0200 -@@ -1,5 +1,5 @@ - config FSNOTIFY -- def_bool n -+ def_bool y - - source "fs/notify/dnotify/Kconfig" - source "fs/notify/inotify/Kconfig" diff --git a/target/linux/patches/3.0.4/fon2100.patch b/target/linux/patches/3.0.4/fon2100.patch deleted file mode 100644 index 038ff7020..000000000 --- a/target/linux/patches/3.0.4/fon2100.patch +++ /dev/null @@ -1,6279 +0,0 @@ -diff -Nur linux-2.6.39-rc7.orig/arch/mips/Kbuild.platforms linux-2.6.39-rc7/arch/mips/Kbuild.platforms ---- linux-2.6.39-rc7.orig/arch/mips/Kbuild.platforms 2011-05-10 04:33:54.000000000 +0200 -+++ linux-2.6.39-rc7/arch/mips/Kbuild.platforms 2011-05-15 21:34:57.000000000 +0200 -@@ -6,6 +6,7 @@ - platforms += bcm47xx - platforms += bcm63xx - platforms += cavium-octeon -+platforms += ar231x - platforms += cobalt - platforms += dec - platforms += emma -diff -Nur linux-2.6.39-rc7.orig/arch/mips/Kconfig linux-2.6.39-rc7/arch/mips/Kconfig ---- linux-2.6.39-rc7.orig/arch/mips/Kconfig 2011-05-10 04:33:54.000000000 +0200 -+++ linux-2.6.39-rc7/arch/mips/Kconfig 2011-05-16 12:11:11.000000000 +0200 -@@ -121,6 +121,21 @@ - help - Support for BCM63XX based boards - -+config ATHEROS_AR231X -+ bool "Atheros 231x/531x SoC support" -+ select CEVT_R4K -+ select CSRC_R4K -+ select DMA_NONCOHERENT -+ select IRQ_CPU -+ select SYS_HAS_CPU_MIPS32_R1 -+ select SYS_SUPPORTS_BIG_ENDIAN -+ select SYS_SUPPORTS_32BIT_KERNEL -+ select GENERIC_GPIO -+ select SYS_HAS_EARLY_PRINTK -+ select SYS_SUPPORTS_ZBOOT -+ help -+ Support for AR231x and AR531x based boards -+ - config MIPS_COBALT - bool "Cobalt Server" - select CEVT_R4K -@@ -738,6 +753,7 @@ - - endchoice - -+source "arch/mips/ar231x/Kconfig" - source "arch/mips/alchemy/Kconfig" - source "arch/mips/ath79/Kconfig" - source "arch/mips/bcm63xx/Kconfig" -diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/Kconfig linux-2.6.39-rc7/arch/mips/ar231x/Kconfig ---- linux-2.6.39-rc7.orig/arch/mips/ar231x/Kconfig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/ar231x/Kconfig 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,27 @@ -+config ATHEROS_AR5312 -+ bool "Atheros 5312/2312+ support" -+ depends on ATHEROS_AR231X -+ default y -+ -+config ATHEROS_AR2315 -+ bool "Atheros 2315+ support" -+ depends on ATHEROS_AR231X -+ select DMA_NONCOHERENT -+ select CEVT_R4K -+ select CSRC_R4K -+ select IRQ_CPU -+ select SYS_HAS_CPU_MIPS32_R1 -+ select SYS_SUPPORTS_32BIT_KERNEL -+ select SYS_SUPPORTS_BIG_ENDIAN -+ select GENERIC_GPIO -+ default y -+ -+config ATHEROS_AR2315_PCI -+ bool "PCI support" -+ depends on ATHEROS_AR2315 -+ select HW_HAS_PCI -+ select PCI -+ select USB_ARCH_HAS_HCD -+ select USB_ARCH_HAS_OHCI -+ select USB_ARCH_HAS_EHCI -+ default n -diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/Makefile linux-2.6.39-rc7/arch/mips/ar231x/Makefile ---- linux-2.6.39-rc7.orig/arch/mips/ar231x/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/ar231x/Makefile 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,17 @@ -+# -+# This file is subject to the terms and conditions of the GNU General Public -+# License. See the file "COPYING" in the main directory of this archive -+# for more details. -+# -+# Copyright (C) 2006 FON Technology, SL. -+# Copyright (C) 2006 Imre Kaloz -+# Copyright (C) 2006-2009 Felix Fietkau -+# -+ -+obj-y += board.o prom.o devices.o -+ -+obj-$(CONFIG_EARLY_PRINTK) += early_printk.o -+ -+obj-$(CONFIG_ATHEROS_AR5312) += ar5312.o -+obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o -+obj-$(CONFIG_ATHEROS_AR2315_PCI) += pci.o -diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/Platform linux-2.6.39-rc7/arch/mips/ar231x/Platform ---- linux-2.6.39-rc7.orig/arch/mips/ar231x/Platform 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/ar231x/Platform 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,6 @@ -+# -+# Atheros AR5312/AR2312 WiSoC -+# -+platform-$(CONFIG_ATHEROS_AR231X) += ar231x/ -+cflags-$(CONFIG_ATHEROS_AR231X) += -I$(srctree)/arch/mips/include/asm/mach-ar231x -+load-$(CONFIG_ATHEROS_AR231X) += 0xffffffff80041000 -diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/ar2315.c linux-2.6.39-rc7/arch/mips/ar231x/ar2315.c ---- linux-2.6.39-rc7.orig/arch/mips/ar231x/ar2315.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/ar231x/ar2315.c 2011-05-15 21:47:07.000000000 +0200 -@@ -0,0 +1,654 @@ -+/* -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. -+ * Copyright (C) 2006 FON Technology, SL. -+ * Copyright (C) 2006 Imre Kaloz -+ * Copyright (C) 2006 Felix Fietkau -+ */ -+ -+/* -+ * Platform devices for Atheros SoCs -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include "devices.h" -+#include "ar2315.h" -+ -+static u32 gpiointmask = 0, gpiointval = 0; -+ -+static inline void ar2315_gpio_irq(void) -+{ -+ u32 pend; -+ int bit = -1; -+ -+ /* only do one gpio interrupt at a time */ -+ pend = (ar231x_read_reg(AR2315_GPIO_DI) ^ gpiointval) & gpiointmask; -+ -+ if (pend) { -+ bit = fls(pend) - 1; -+ pend &= ~(1 << bit); -+ gpiointval ^= (1 << bit); -+ } -+ -+ if (!pend) -+ ar231x_write_reg(AR2315_ISR, AR2315_ISR_GPIO); -+ -+ /* Enable interrupt with edge detection */ -+ if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(bit)) != AR2315_GPIO_CR_I(bit)) -+ return; -+ -+ if (bit >= 0) -+ do_IRQ(AR531X_GPIO_IRQ_BASE + bit); -+} -+ -+#ifdef CONFIG_ATHEROS_AR2315_PCI -+static inline void pci_abort_irq(void) -+{ -+ ar231x_write_reg(AR2315_PCI_INT_STATUS, AR2315_PCI_ABORT_INT); -+} -+ -+static inline void pci_ack_irq(void) -+{ -+ ar231x_write_reg(AR2315_PCI_INT_STATUS, AR2315_PCI_EXT_INT); -+} -+ -+void ar2315_pci_irq(int irq) -+{ -+ if (ar231x_read_reg(AR2315_PCI_INT_STATUS) == AR2315_PCI_ABORT_INT) -+ pci_abort_irq(); -+ else { -+ do_IRQ(irq); -+ pci_ack_irq(); -+ } -+} -+#endif /* CONFIG_ATHEROS_AR2315_PCI */ -+ -+/* -+ * Called when an interrupt is received, this function -+ * determines exactly which interrupt it was, and it -+ * invokes the appropriate handler. -+ * -+ * Implicitly, we also define interrupt priority by -+ * choosing which to dispatch first. -+ */ -+static asmlinkage void -+ar2315_irq_dispatch(void) -+{ -+ int pending = read_c0_status() & read_c0_cause(); -+ -+ if (pending & CAUSEF_IP3) -+ do_IRQ(AR2315_IRQ_WLAN0_INTRS); -+ else if (pending & CAUSEF_IP4) -+ do_IRQ(AR2315_IRQ_ENET0_INTRS); -+#ifdef CONFIG_ATHEROS_AR2315_PCI -+ else if (pending & CAUSEF_IP5) -+ ar2315_pci_irq(AR2315_IRQ_LCBUS_PCI); -+#endif -+ else if (pending & CAUSEF_IP2) { -+ unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) & ar231x_read_reg(AR2315_IMR); -+ -+ if (misc_intr & AR2315_ISR_SPI) -+ do_IRQ(AR531X_MISC_IRQ_SPI); -+ else if (misc_intr & AR2315_ISR_TIMER) -+ do_IRQ(AR531X_MISC_IRQ_TIMER); -+ else if (misc_intr & AR2315_ISR_AHB) -+ do_IRQ(AR531X_MISC_IRQ_AHB_PROC); -+ else if (misc_intr & AR2315_ISR_GPIO) -+ ar2315_gpio_irq(); -+ else if (misc_intr & AR2315_ISR_UART0) -+ do_IRQ(AR531X_MISC_IRQ_UART0); -+ else if (misc_intr & AR2315_ISR_WD) -+ do_IRQ(AR531X_MISC_IRQ_WATCHDOG); -+ else -+ do_IRQ(AR531X_MISC_IRQ_NONE); -+ } else if (pending & CAUSEF_IP7) -+ do_IRQ(AR531X_IRQ_CPU_CLOCK); -+} -+ -+static void ar2315_set_gpiointmask(int gpio, int level) -+{ -+ u32 reg; -+ -+ reg = ar231x_read_reg(AR2315_GPIO_INT); -+ reg &= ~(AR2315_GPIO_INT_M | AR2315_GPIO_INT_LVL_M); -+ reg |= gpio | AR2315_GPIO_INT_LVL(level); -+ ar231x_write_reg(AR2315_GPIO_INT, reg); -+} -+ -+static void ar2315_gpio_intr_enable(struct irq_data *d) -+{ -+ unsigned int gpio = d->irq - AR531X_GPIO_IRQ_BASE; -+ -+ /* Enable interrupt with edge detection */ -+ if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(gpio)) != AR2315_GPIO_CR_I(gpio)) -+ return; -+ -+ gpiointmask |= (1 << gpio); -+ ar2315_set_gpiointmask(gpio, 3); -+} -+ -+static void ar2315_gpio_intr_disable(struct irq_data *d) -+{ -+ unsigned int gpio = d->irq - AR531X_GPIO_IRQ_BASE; -+ -+ /* Disable interrupt */ -+ gpiointmask &= ~(1 << gpio); -+ ar2315_set_gpiointmask(gpio, 0); -+} -+ -+static struct irq_chip ar2315_gpio_intr_controller = { -+ .name = "AR2315-GPIO", -+ .irq_ack = ar2315_gpio_intr_disable, -+ .irq_mask_ack = ar2315_gpio_intr_disable, -+ .irq_mask = ar2315_gpio_intr_disable, -+ .irq_unmask = ar2315_gpio_intr_enable, -+}; -+ -+static void -+ar2315_misc_intr_enable(struct irq_data *d) -+{ -+ unsigned int imr; -+ -+ imr = ar231x_read_reg(AR2315_IMR); -+ switch(d->irq) { -+ case AR531X_MISC_IRQ_SPI: -+ imr |= AR2315_ISR_SPI; -+ break; -+ case AR531X_MISC_IRQ_TIMER: -+ imr |= AR2315_ISR_TIMER; -+ break; -+ case AR531X_MISC_IRQ_AHB_PROC: -+ imr |= AR2315_ISR_AHB; -+ break; -+ case AR531X_MISC_IRQ_GPIO: -+ imr |= AR2315_ISR_GPIO; -+ break; -+ case AR531X_MISC_IRQ_UART0: -+ imr |= AR2315_ISR_UART0; -+ break; -+ case AR531X_MISC_IRQ_WATCHDOG: -+ imr |= AR2315_ISR_WD; -+ break; -+ default: -+ break; -+ } -+ ar231x_write_reg(AR2315_IMR, imr); -+} -+ -+static void -+ar2315_misc_intr_disable(struct irq_data *d) -+{ -+ unsigned int imr; -+ -+ imr = ar231x_read_reg(AR2315_IMR); -+ switch(d->irq) { -+ case AR531X_MISC_IRQ_SPI: -+ imr &= ~AR2315_ISR_SPI; -+ break; -+ case AR531X_MISC_IRQ_TIMER: -+ imr &= ~AR2315_ISR_TIMER; -+ break; -+ case AR531X_MISC_IRQ_AHB_PROC: -+ imr &= ~AR2315_ISR_AHB; -+ break; -+ case AR531X_MISC_IRQ_GPIO: -+ imr &= ~AR2315_ISR_GPIO; -+ break; -+ case AR531X_MISC_IRQ_UART0: -+ imr &= ~AR2315_ISR_UART0; -+ break; -+ case AR531X_MISC_IRQ_WATCHDOG: -+ imr &= ~AR2315_ISR_WD; -+ break; -+ default: -+ break; -+ } -+ ar231x_write_reg(AR2315_IMR, imr); -+} -+ -+ -+static struct irq_chip ar2315_misc_intr_controller = { -+ .name = "AR2315-MISC", -+ .irq_mask = ar2315_misc_intr_disable, -+ .irq_unmask = ar2315_misc_intr_enable, -+}; -+ -+static irqreturn_t ar2315_ahb_proc_handler(int cpl, void *dev_id) -+{ -+ ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET); -+ ar231x_read_reg(AR2315_AHB_ERR1); -+ -+ printk(KERN_ERR "AHB fatal error\n"); -+ machine_restart("AHB error"); /* Catastrophic failure */ -+ -+ return IRQ_HANDLED; -+} -+ -+static struct irqaction ar2315_ahb_proc_interrupt = { -+ .handler = ar2315_ahb_proc_handler, -+ .flags = IRQF_DISABLED, -+ .name = "ar2315_ahb_proc_interrupt", -+}; -+ -+static struct irqaction cascade = { -+ .handler = no_action, -+ .flags = IRQF_DISABLED, -+ .name = "cascade", -+}; -+ -+void -+ar2315_irq_init(void) -+{ -+ int i; -+ -+ if (!is_2315()) -+ return; -+ -+ ar231x_irq_dispatch = ar2315_irq_dispatch; -+ gpiointval = ar231x_read_reg(AR2315_GPIO_DI); -+ for (i = 0; i < AR531X_MISC_IRQ_COUNT; i++) { -+ int irq = AR531X_MISC_IRQ_BASE + i; -+ irq_set_chip_and_handler(irq, &ar2315_misc_intr_controller, -+ handle_level_irq); -+ } -+ for (i = 0; i < AR531X_GPIO_IRQ_COUNT; i++) { -+ int irq = AR531X_GPIO_IRQ_BASE + i; -+ irq_set_chip_and_handler(irq, &ar2315_gpio_intr_controller, -+ handle_level_irq); -+ } -+ setup_irq(AR531X_MISC_IRQ_GPIO, &cascade); -+ setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar2315_ahb_proc_interrupt); -+ setup_irq(AR2315_IRQ_MISC_INTRS, &cascade); -+} -+ -+const struct ar231x_gpiodev ar2315_gpiodev; -+ -+static u32 -+ar2315_gpio_get_output(void) -+{ -+ u32 reg; -+ reg = ar231x_read_reg(AR2315_GPIO_CR); -+ reg &= ar2315_gpiodev.valid_mask; -+ return reg; -+} -+ -+static u32 -+ar2315_gpio_set_output(u32 mask, u32 val) -+{ -+ u32 reg; -+ -+ reg = ar231x_read_reg(AR2315_GPIO_CR); -+ reg &= ~mask; -+ reg |= val; -+ ar231x_write_reg(AR2315_GPIO_CR, reg); -+ return reg; -+} -+ -+static u32 -+ar2315_gpio_get(void) -+{ -+ u32 reg; -+ reg = ar231x_read_reg(AR2315_GPIO_DI); -+ reg &= ar2315_gpiodev.valid_mask; -+ return reg; -+} -+ -+static u32 -+ar2315_gpio_set(u32 mask, u32 value) -+{ -+ u32 reg; -+ reg = ar231x_read_reg(AR2315_GPIO_DO); -+ reg &= ~mask; -+ reg |= value; -+ ar231x_write_reg(AR2315_GPIO_DO, reg); -+ return reg; -+} -+ -+const struct ar231x_gpiodev ar2315_gpiodev = { -+ .valid_mask = (1 << 22) - 1, -+ .get_output = ar2315_gpio_get_output, -+ .set_output = ar2315_gpio_set_output, -+ .get = ar2315_gpio_get, -+ .set = ar2315_gpio_set, -+}; -+ -+static struct ar231x_eth ar2315_eth_data = { -+ .reset_base = AR2315_RESET, -+ .reset_mac = AR2315_RESET_ENET0, -+ .reset_phy = AR2315_RESET_EPHY0, -+ .phy_base = KSEG1ADDR(AR2315_ENET0), -+ .config = &ar231x_board, -+}; -+ -+static struct resource ar2315_spiflash_res[] = { -+ { -+ .name = "flash_base", -+ .flags = IORESOURCE_MEM, -+ .start = KSEG1ADDR(AR2315_SPI_READ), -+ .end = KSEG1ADDR(AR2315_SPI_READ) + 0x1000000 - 1, -+ }, -+ { -+ .name = "flash_regs", -+ .flags = IORESOURCE_MEM, -+ .start = 0x11300000, -+ .end = 0x11300012, -+ }, -+}; -+ -+static struct platform_device ar2315_spiflash = { -+ .id = 0, -+ .name = "spiflash", -+ .resource = ar2315_spiflash_res, -+ .num_resources = ARRAY_SIZE(ar2315_spiflash_res) -+}; -+ -+static struct platform_device ar2315_wdt = { -+ .id = 0, -+ .name = "ar2315_wdt", -+}; -+ -+#define SPI_FLASH_CTL 0x00 -+#define SPI_FLASH_OPCODE 0x04 -+#define SPI_FLASH_DATA 0x08 -+ -+static inline u32 -+spiflash_read_reg(int reg) -+{ -+ return ar231x_read_reg(AR2315_SPI + reg); -+} -+ -+static inline void -+spiflash_write_reg(int reg, u32 data) -+{ -+ ar231x_write_reg(AR2315_SPI + reg, data); -+} -+ -+static u32 -+spiflash_wait_status(void) -+{ -+ u32 reg; -+ -+ do { -+ reg = spiflash_read_reg(SPI_FLASH_CTL); -+ } while (reg & SPI_CTL_BUSY); -+ -+ return reg; -+} -+ -+static u8 -+spiflash_probe(void) -+{ -+ u32 reg; -+ -+ reg = spiflash_wait_status(); -+ reg &= ~SPI_CTL_TX_RX_CNT_MASK; -+ reg |= (1 << 4) | 4 | SPI_CTL_START; -+ -+ spiflash_write_reg(SPI_FLASH_OPCODE, 0xab); -+ spiflash_write_reg(SPI_FLASH_CTL, reg); -+ -+ reg = spiflash_wait_status(); -+ reg = spiflash_read_reg(SPI_FLASH_DATA); -+ reg &= 0xff; -+ -+ return (u8) reg; -+} -+ -+ -+#define STM_8MBIT_SIGNATURE 0x13 -+#define STM_16MBIT_SIGNATURE 0x14 -+#define STM_32MBIT_SIGNATURE 0x15 -+#define STM_64MBIT_SIGNATURE 0x16 -+#define STM_128MBIT_SIGNATURE 0x17 -+ -+static u8 __init * -+ar2315_flash_limit(void) -+{ -+ u32 flash_size = 0; -+ -+ /* probe the flash chip size */ -+ switch(spiflash_probe()) { -+ case STM_8MBIT_SIGNATURE: -+ flash_size = 0x00100000; -+ break; -+ case STM_16MBIT_SIGNATURE: -+ flash_size = 0x00200000; -+ break; -+ case STM_32MBIT_SIGNATURE: -+ flash_size = 0x00400000; -+ break; -+ case STM_64MBIT_SIGNATURE: -+ flash_size = 0x00800000; -+ break; -+ case STM_128MBIT_SIGNATURE: -+ flash_size = 0x01000000; -+ break; -+ } -+ -+ ar2315_spiflash_res[0].end = ar2315_spiflash_res[0].start + -+ flash_size - 1; -+ return (u8 *) ar2315_spiflash_res[0].end + 1; -+} -+ -+#ifdef CONFIG_LEDS_GPIO -+static struct gpio_led ar2315_leds[6]; -+static struct gpio_led_platform_data ar2315_led_data = { -+ .leds = (void *) ar2315_leds, -+}; -+ -+static struct platform_device ar2315_gpio_leds = { -+ .name = "leds-gpio", -+ .id = -1, -+ .dev = { -+ .platform_data = (void *) &ar2315_led_data, -+ } -+}; -+ -+static void __init -+ar2315_init_gpio(void) -+{ -+ static char led_names[6][6]; -+ int i, led = 0; -+ -+ ar2315_led_data.num_leds = 0; -+ for(i = 1; i < 8; i++) -+ { -+ if((i == AR2315_RESET_GPIO) || -+ (i == ar231x_board.config->resetConfigGpio)) -+ continue; -+ -+ if(i == ar231x_board.config->sysLedGpio) -+ strcpy(led_names[led], "wlan"); -+ else -+ sprintf(led_names[led], "gpio%d", i); -+ -+ ar2315_leds[led].name = led_names[led]; -+ ar2315_leds[led].gpio = i; -+ ar2315_leds[led].active_low = 0; -+ led++; -+ } -+ ar2315_led_data.num_leds = led; -+ platform_device_register(&ar2315_gpio_leds); -+} -+#else -+static inline void ar2315_init_gpio(void) -+{ -+} -+#endif -+ -+int __init -+ar2315_init_devices(void) -+{ -+ if (!is_2315()) -+ return 0; -+ -+ /* Find board configuration */ -+ ar231x_find_config(ar2315_flash_limit()); -+ ar2315_eth_data.macaddr = ar231x_board.config->enet0_mac; -+ -+ ar2315_init_gpio(); -+ platform_device_register(&ar2315_wdt); -+ platform_device_register(&ar2315_spiflash); -+ ar231x_add_ethernet(0, KSEG1ADDR(AR2315_ENET0), AR2315_IRQ_ENET0_INTRS, -+ &ar2315_eth_data); -+ ar231x_add_wmac(0, AR2315_WLAN0, AR2315_IRQ_WLAN0_INTRS); -+ -+ return 0; -+} -+ -+static void -+ar2315_restart(char *command) -+{ -+ void (*mips_reset_vec)(void) = (void *) 0xbfc00000; -+ -+ local_irq_disable(); -+ -+ /* try reset the system via reset control */ -+ ar231x_write_reg(AR2315_COLD_RESET,AR2317_RESET_SYSTEM); -+ -+ /* Cold reset does not work on the AR2315/6, use the GPIO reset bits a workaround. -+ * give it some time to attempt a gpio based hardware reset -+ * (atheros reference design workaround) */ -+ gpio_direction_output(AR2315_RESET_GPIO, 0); -+ mdelay(100); -+ -+ /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic -+ * workaround. Attempt to jump to the mips reset location - -+ * the boot loader itself might be able to recover the system */ -+ mips_reset_vec(); -+} -+ -+ -+/* -+ * This table is indexed by bits 5..4 of the CLOCKCTL1 register -+ * to determine the predevisor value. -+ */ -+static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = { 1, 2, 4, 5 }; -+static int __initdata PLLC_DIVIDE_TABLE[5] = { 2, 3, 4, 6, 3 }; -+ -+static unsigned int __init -+ar2315_sys_clk(unsigned int clockCtl) -+{ -+ unsigned int pllcCtrl,cpuDiv; -+ unsigned int pllcOut,refdiv,fdiv,divby2; -+ unsigned int clkDiv; -+ -+ pllcCtrl = ar231x_read_reg(AR2315_PLLC_CTL); -+ refdiv = (pllcCtrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S; -+ refdiv = CLOCKCTL1_PREDIVIDE_TABLE[refdiv]; -+ fdiv = (pllcCtrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S; -+ divby2 = (pllcCtrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S; -+ divby2 += 1; -+ pllcOut = (40000000/refdiv)*(2*divby2)*fdiv; -+ -+ -+ /* clkm input selected */ -+ switch(clockCtl & CPUCLK_CLK_SEL_M) { -+ case 0: -+ case 1: -+ clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKM_DIV_M) >> PLLC_CLKM_DIV_S]; -+ break; -+ case 2: -+ clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKC_DIV_M) >> PLLC_CLKC_DIV_S]; -+ break; -+ default: -+ pllcOut = 40000000; -+ clkDiv = 1; -+ break; -+ } -+ cpuDiv = (clockCtl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S; -+ cpuDiv = cpuDiv * 2 ?: 1; -+ return (pllcOut/(clkDiv * cpuDiv)); -+} -+ -+static inline unsigned int -+ar2315_cpu_frequency(void) -+{ -+ return ar2315_sys_clk(ar231x_read_reg(AR2315_CPUCLK)); -+} -+ -+static inline unsigned int -+ar2315_apb_frequency(void) -+{ -+ return ar2315_sys_clk(ar231x_read_reg(AR2315_AMBACLK)); -+} -+ -+void __init -+ar2315_time_init(void) -+{ -+ if (!is_2315()) -+ return; -+ -+ mips_hpt_frequency = ar2315_cpu_frequency() / 2; -+} -+ -+void __init -+ar2315_prom_init(void) -+{ -+ u32 memsize, memcfg, devid; -+ -+ if (!is_2315()) -+ return; -+ -+ memcfg = ar231x_read_reg(AR2315_MEM_CFG); -+ memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S); -+ memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S); -+ memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S); -+ memsize <<= 3; -+ add_memory_region(0, memsize, BOOT_MEM_RAM); -+ -+ /* Detect the hardware based on the device ID */ -+ devid = ar231x_read_reg(AR2315_SREV) & AR2315_REV_CHIP; -+ switch(devid) { -+ case 0x90: -+ case 0x91: -+ ar231x_devtype = DEV_TYPE_AR2317; -+ break; -+ default: -+ ar231x_devtype = DEV_TYPE_AR2315; -+ break; -+ } -+ ar231x_gpiodev = &ar2315_gpiodev; -+ ar231x_board.devid = devid; -+} -+ -+void __init -+ar2315_plat_setup(void) -+{ -+ u32 config; -+ -+ if (!is_2315()) -+ return; -+ -+ /* Clear any lingering AHB errors */ -+ config = read_c0_config(); -+ write_c0_config(config & ~0x3); -+ ar231x_write_reg(AR2315_AHB_ERR0,AHB_ERROR_DET); -+ ar231x_read_reg(AR2315_AHB_ERR1); -+ ar231x_write_reg(AR2315_WDC, AR2315_WDC_IGNORE_EXPIRATION); -+ -+ _machine_restart = ar2315_restart; -+ ar231x_serial_setup(KSEG1ADDR(AR2315_UART0), ar2315_apb_frequency()); -+} -diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/ar2315.h linux-2.6.39-rc7/arch/mips/ar231x/ar2315.h ---- linux-2.6.39-rc7.orig/arch/mips/ar231x/ar2315.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/ar231x/ar2315.h 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,37 @@ -+#ifndef __AR2315_H -+#define __AR2315_H -+ -+#ifdef CONFIG_ATHEROS_AR2315 -+ -+extern void ar2315_irq_init(void); -+extern int ar2315_init_devices(void); -+extern void ar2315_prom_init(void); -+extern void ar2315_plat_setup(void); -+extern void ar2315_time_init(void); -+ -+#else -+ -+static inline void ar2315_irq_init(void) -+{ -+} -+ -+static inline int ar2315_init_devices(void) -+{ -+ return 0; -+} -+ -+static inline void ar2315_prom_init(void) -+{ -+} -+ -+static inline void ar2315_plat_setup(void) -+{ -+} -+ -+static inline void ar2315_time_init(void) -+{ -+} -+ -+#endif -+ -+#endif -diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/ar5312.c linux-2.6.39-rc7/arch/mips/ar231x/ar5312.c ---- linux-2.6.39-rc7.orig/arch/mips/ar231x/ar5312.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/ar231x/ar5312.c 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,538 @@ -+/* -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. -+ * Copyright (C) 2006 FON Technology, SL. -+ * Copyright (C) 2006 Imre Kaloz -+ * Copyright (C) 2006-2009 Felix Fietkau -+ */ -+ -+/* -+ * Platform devices for Atheros SoCs -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include "devices.h" -+#include "ar5312.h" -+ -+static void -+ar5312_misc_irq_dispatch(void) -+{ -+ unsigned int ar231x_misc_intrs = ar231x_read_reg(AR531X_ISR) & ar231x_read_reg(AR531X_IMR); -+ -+ if (ar231x_misc_intrs & AR531X_ISR_TIMER) { -+ do_IRQ(AR531X_MISC_IRQ_TIMER); -+ (void)ar231x_read_reg(AR531X_TIMER); -+ } else if (ar231x_misc_intrs & AR531X_ISR_AHBPROC) -+ do_IRQ(AR531X_MISC_IRQ_AHB_PROC); -+ else if ((ar231x_misc_intrs & AR531X_ISR_UART0)) -+ do_IRQ(AR531X_MISC_IRQ_UART0); -+ else if (ar231x_misc_intrs & AR531X_ISR_WD) -+ do_IRQ(AR531X_MISC_IRQ_WATCHDOG); -+ else -+ do_IRQ(AR531X_MISC_IRQ_NONE); -+} -+ -+static asmlinkage void -+ar5312_irq_dispatch(void) -+{ -+ int pending = read_c0_status() & read_c0_cause(); -+ -+ if (pending & CAUSEF_IP2) -+ do_IRQ(AR5312_IRQ_WLAN0_INTRS); -+ else if (pending & CAUSEF_IP3) -+ do_IRQ(AR5312_IRQ_ENET0_INTRS); -+ else if (pending & CAUSEF_IP4) -+ do_IRQ(AR5312_IRQ_ENET1_INTRS); -+ else if (pending & CAUSEF_IP5) -+ do_IRQ(AR5312_IRQ_WLAN1_INTRS); -+ else if (pending & CAUSEF_IP6) -+ ar5312_misc_irq_dispatch(); -+ else if (pending & CAUSEF_IP7) -+ do_IRQ(AR531X_IRQ_CPU_CLOCK); -+} -+ -+ -+/* Enable the specified AR531X_MISC_IRQ interrupt */ -+static void -+ar5312_misc_intr_enable(struct irq_data *d) -+{ -+ unsigned int imr; -+ -+ imr = ar231x_read_reg(AR531X_IMR); -+ imr |= (1 << (d->irq - AR531X_MISC_IRQ_BASE - 1)); -+ ar231x_write_reg(AR531X_IMR, imr); -+} -+ -+/* Disable the specified AR531X_MISC_IRQ interrupt */ -+static void -+ar5312_misc_intr_disable(struct irq_data *d) -+{ -+ unsigned int imr; -+ -+ imr = ar231x_read_reg(AR531X_IMR); -+ imr &= ~(1 << (d->irq - AR531X_MISC_IRQ_BASE - 1)); -+ ar231x_write_reg(AR531X_IMR, imr); -+ ar231x_read_reg(AR531X_IMR); /* flush write buffer */ -+} -+ -+static struct irq_chip ar5312_misc_intr_controller = { -+ .name = "AR5312-MISC", -+ .irq_mask = ar5312_misc_intr_disable, -+ .irq_unmask = ar5312_misc_intr_enable, -+}; -+ -+ -+static irqreturn_t ar5312_ahb_proc_handler(int cpl, void *dev_id) -+{ -+ u32 proc1 = ar231x_read_reg(AR531X_PROC1); -+ u32 procAddr = ar231x_read_reg(AR531X_PROCADDR); /* clears error state */ -+ u32 dma1 = ar231x_read_reg(AR531X_DMA1); -+ u32 dmaAddr = ar231x_read_reg(AR531X_DMAADDR); /* clears error state */ -+ -+ printk("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n", -+ procAddr, proc1, dmaAddr, dma1); -+ -+ machine_restart("AHB error"); /* Catastrophic failure */ -+ return IRQ_HANDLED; -+} -+ -+ -+static struct irqaction ar5312_ahb_proc_interrupt = { -+ .handler = ar5312_ahb_proc_handler, -+ .flags = IRQF_DISABLED, -+ .name = "ar5312_ahb_proc_interrupt", -+}; -+ -+ -+static struct irqaction cascade = { -+ .handler = no_action, -+ .flags = IRQF_DISABLED, -+ .name = "cascade", -+}; -+ -+void __init ar5312_irq_init(void) -+{ -+ int i; -+ -+ if (!is_5312()) -+ return; -+ -+ ar231x_irq_dispatch = ar5312_irq_dispatch; -+ for (i = 0; i < AR531X_MISC_IRQ_COUNT; i++) { -+ int irq = AR531X_MISC_IRQ_BASE + i; -+ irq_set_chip_and_handler(irq, &ar5312_misc_intr_controller, -+ handle_level_irq); -+ } -+ setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt); -+ setup_irq(AR5312_IRQ_MISC_INTRS, &cascade); -+} -+ -+const struct ar231x_gpiodev ar5312_gpiodev; -+ -+static u32 -+ar5312_gpio_get_output(void) -+{ -+ u32 reg; -+ reg = ~(ar231x_read_reg(AR531X_GPIO_CR)); -+ reg &= ar5312_gpiodev.valid_mask; -+ return reg; -+} -+ -+static u32 -+ar5312_gpio_set_output(u32 mask, u32 val) -+{ -+ u32 reg; -+ -+ reg = ar231x_read_reg(AR531X_GPIO_CR); -+ reg |= mask; -+ reg &= ~val; -+ ar231x_write_reg(AR531X_GPIO_CR, reg); -+ return reg; -+} -+ -+static u32 -+ar5312_gpio_get(void) -+{ -+ u32 reg; -+ reg = ar231x_read_reg(AR531X_GPIO_DI); -+ reg &= ar5312_gpiodev.valid_mask; -+ return reg; -+} -+ -+static u32 -+ar5312_gpio_set(u32 mask, u32 value) -+{ -+ u32 reg; -+ reg = ar231x_read_reg(AR531X_GPIO_DO); -+ reg &= ~mask; -+ reg |= value; -+ ar231x_write_reg(AR531X_GPIO_DO, reg); -+ return reg; -+} -+ -+const struct ar231x_gpiodev ar5312_gpiodev = { -+ .valid_mask = (1 << 8) - 1, -+ .get_output = ar5312_gpio_get_output, -+ .set_output = ar5312_gpio_set_output, -+ .get = ar5312_gpio_get, -+ .set = ar5312_gpio_set, -+}; -+ -+static struct physmap_flash_data ar5312_flash_data = { -+ .width = 2, -+}; -+ -+static struct resource ar5312_flash_resource = { -+ .start = AR531X_FLASH, -+ .end = AR531X_FLASH + 0x800000 - 1, -+ .flags = IORESOURCE_MEM, -+}; -+ -+static struct ar231x_eth ar5312_eth0_data = { -+ .reset_base = AR531X_RESET, -+ .reset_mac = AR531X_RESET_ENET0, -+ .reset_phy = AR531X_RESET_EPHY0, -+ .phy_base = KSEG1ADDR(AR531X_ENET0), -+ .config = &ar231x_board, -+}; -+ -+static struct ar231x_eth ar5312_eth1_data = { -+ .reset_base = AR531X_RESET, -+ .reset_mac = AR531X_RESET_ENET1, -+ .reset_phy = AR531X_RESET_EPHY1, -+ .phy_base = KSEG1ADDR(AR531X_ENET1), -+ .config = &ar231x_board, -+}; -+ -+static struct platform_device ar5312_physmap_flash = { -+ .name = "physmap-flash", -+ .id = 0, -+ .dev.platform_data = &ar5312_flash_data, -+ .resource = &ar5312_flash_resource, -+ .num_resources = 1, -+}; -+ -+#ifdef CONFIG_LEDS_GPIO -+static struct gpio_led ar5312_leds[] = { -+ { .name = "wlan", .gpio = 0, .active_low = 1, }, -+}; -+ -+static const struct gpio_led_platform_data ar5312_led_data = { -+ .num_leds = ARRAY_SIZE(ar5312_leds), -+ .leds = (void *) ar5312_leds, -+}; -+ -+static struct platform_device ar5312_gpio_leds = { -+ .name = "leds-gpio", -+ .id = -1, -+ .dev.platform_data = (void *) &ar5312_led_data, -+}; -+#endif -+ -+/* -+ * NB: This mapping size is larger than the actual flash size, -+ * but this shouldn't be a problem here, because the flash -+ * will simply be mapped multiple times. -+ */ -+static char __init *ar5312_flash_limit(void) -+{ -+ u32 ctl; -+ /* -+ * Configure flash bank 0. -+ * Assume 8M window size. Flash will be aliased if it's smaller -+ */ -+ ctl = FLASHCTL_E | -+ FLASHCTL_AC_8M | -+ FLASHCTL_RBLE | -+ (0x01 << FLASHCTL_IDCY_S) | -+ (0x07 << FLASHCTL_WST1_S) | -+ (0x07 << FLASHCTL_WST2_S) | -+ (ar231x_read_reg(AR531X_FLASHCTL0) & FLASHCTL_MW); -+ -+ ar231x_write_reg(AR531X_FLASHCTL0, ctl); -+ -+ /* Disable other flash banks */ -+ ar231x_write_reg(AR531X_FLASHCTL1, -+ ar231x_read_reg(AR531X_FLASHCTL1) & ~(FLASHCTL_E | FLASHCTL_AC)); -+ -+ ar231x_write_reg(AR531X_FLASHCTL2, -+ ar231x_read_reg(AR531X_FLASHCTL2) & ~(FLASHCTL_E | FLASHCTL_AC)); -+ -+ return (char *) KSEG1ADDR(AR531X_FLASH + 0x800000); -+} -+ -+int __init ar5312_init_devices(void) -+{ -+ struct ar231x_boarddata *config; -+ u32 fctl = 0; -+ const u8 *radio; -+ u8 *c; -+ -+ if (!is_5312()) -+ return 0; -+ -+ /* Locate board/radio config data */ -+ ar231x_find_config(ar5312_flash_limit()); -+ config = ar231x_board.config; -+ -+ -+ /* -+ * Chip IDs and hardware detection for some Atheros -+ * models are really broken! -+ * -+ * Atheros uses a disabled WMAC0 and Silicon ID of AR5312 -+ * as indication for AR2312, which is otherwise -+ * indistinguishable from the real AR5312. -+ */ -+ if (ar231x_board.radio) { -+ radio = ar231x_board.radio + AR531X_RADIO_MASK_OFF; -+ if ((*((const u32 *) radio) & AR531X_RADIO0_MASK) == 0) -+ config->flags |= BD_ISCASPER; -+ } else -+ radio = NULL; -+ -+ /* AR2313 has CPU minor rev. 10 */ -+ if ((current_cpu_data.processor_id & 0xff) == 0x0a) -+ ar231x_devtype = DEV_TYPE_AR2313; -+ -+ /* AR2312 shares the same Silicon ID as AR5312 */ -+ else if (config->flags & BD_ISCASPER) -+ ar231x_devtype = DEV_TYPE_AR2312; -+ -+ /* Everything else is probably AR5312 or compatible */ -+ else -+ ar231x_devtype = DEV_TYPE_AR5312; -+ -+ /* fixup flash width */ -+ fctl = ar231x_read_reg(AR531X_FLASHCTL) & FLASHCTL_MW; -+ switch (fctl) { -+ case FLASHCTL_MWx16: -+ ar5312_flash_data.width = 2; -+ break; -+ case FLASHCTL_MWx8: -+ default: -+ ar5312_flash_data.width = 1; -+ break; -+ } -+ -+ platform_device_register(&ar5312_physmap_flash); -+ -+#ifdef CONFIG_LEDS_GPIO -+ ar5312_leds[0].gpio = config->sysLedGpio; -+ platform_device_register(&ar5312_gpio_leds); -+#endif -+ -+ /* Fix up MAC addresses if necessary */ -+ if (!memcmp(config->enet0_mac, "\xff\xff\xff\xff\xff\xff", 6)) -+ memcpy(config->enet0_mac, config->enet1_mac, 6); -+ -+ /* If ENET0 and ENET1 have the same mac address, -+ * increment the one from ENET1 */ -+ if (memcmp(config->enet0_mac, config->enet1_mac, 6) == 0) { -+ c = config->enet1_mac + 5; -+ while ((c >= config->enet1_mac) && !(++(*c))) -+ c--; -+ } -+ -+ switch(ar231x_devtype) { -+ case DEV_TYPE_AR5312: -+ ar5312_eth0_data.macaddr = config->enet0_mac; -+ ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET0), -+ AR5312_IRQ_ENET0_INTRS, &ar5312_eth0_data); -+ -+ ar5312_eth1_data.macaddr = config->enet1_mac; -+ ar231x_add_ethernet(1, KSEG1ADDR(AR531X_ENET1), -+ AR5312_IRQ_ENET1_INTRS, &ar5312_eth1_data); -+ -+ if (!ar231x_board.radio) -+ return 0; -+ -+ if ((*((u32 *) radio) & AR531X_RADIO0_MASK) && -+ (config->flags & BD_WLAN0)) -+ ar231x_add_wmac(0, AR531X_WLAN0, -+ AR5312_IRQ_WLAN0_INTRS); -+ -+ break; -+ /* -+ * AR2312/3 ethernet uses the PHY of ENET0, but the MAC -+ * of ENET1. Atheros calls it 'twisted' for a reason :) -+ */ -+ case DEV_TYPE_AR2312: -+ case DEV_TYPE_AR2313: -+ ar5312_eth1_data.phy_base = ar5312_eth0_data.phy_base; -+ ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy; -+ ar5312_eth1_data.macaddr = config->enet0_mac; -+ ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET1), -+ AR5312_IRQ_ENET1_INTRS, &ar5312_eth1_data); -+ -+ if (!ar231x_board.radio) -+ return 0; -+ break; -+ default: -+ break; -+ } -+ -+ if ((*((u32 *) radio) & AR531X_RADIO1_MASK) && -+ (config->flags & BD_WLAN1)) -+ ar231x_add_wmac(1, AR531X_WLAN1, -+ AR5312_IRQ_WLAN1_INTRS); -+ -+ return 0; -+} -+ -+ -+static void ar5312_restart(char *command) -+{ -+ /* reset the system */ -+ local_irq_disable(); -+ while(1) { -+ ar231x_write_reg(AR531X_RESET, AR531X_RESET_SYSTEM); -+ } -+} -+ -+ -+/* -+ * This table is indexed by bits 5..4 of the CLOCKCTL1 register -+ * to determine the predevisor value. -+ */ -+static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = { 1, 2, 4, 5 }; -+ -+ -+static int __init -+ar5312_cpu_frequency(void) -+{ -+ unsigned int result; -+ unsigned int predivide_mask, predivide_shift; -+ unsigned int multiplier_mask, multiplier_shift; -+ unsigned int clockCtl1, preDivideSelect, preDivisor, multiplier; -+ unsigned int doubler_mask; -+ u16 devid; -+ -+ /* Trust the bootrom's idea of cpu frequency. */ -+ if ((result = ar231x_read_reg(AR5312_SCRATCH))) -+ return result; -+ -+ devid = ar231x_read_reg(AR531X_REV); -+ devid &= AR531X_REV_MAJ; -+ devid >>= AR531X_REV_MAJ_S; -+ if (devid == AR531X_REV_MAJ_AR2313) { -+ predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK; -+ predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT; -+ multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK; -+ multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT; -+ doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK; -+ } else { /* AR5312 and AR2312 */ -+ predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK; -+ predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT; -+ multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK; -+ multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT; -+ doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK; -+ } -+ -+ /* -+ * Clocking is derived from a fixed 40MHz input clock. -+ * -+ * cpuFreq = InputClock * MULT (where MULT is PLL multiplier) -+ * sysFreq = cpuFreq / 4 (used for APB clock, serial, -+ * flash, Timer, Watchdog Timer) -+ * -+ * cntFreq = cpuFreq / 2 (use for CPU count/compare) -+ * -+ * So, for example, with a PLL multiplier of 5, we have -+ * -+ * cpuFreq = 200MHz -+ * sysFreq = 50MHz -+ * cntFreq = 100MHz -+ * -+ * We compute the CPU frequency, based on PLL settings. -+ */ -+ -+ clockCtl1 = ar231x_read_reg(AR5312_CLOCKCTL1); -+ preDivideSelect = (clockCtl1 & predivide_mask) >> predivide_shift; -+ preDivisor = CLOCKCTL1_PREDIVIDE_TABLE[preDivideSelect]; -+ multiplier = (clockCtl1 & multiplier_mask) >> multiplier_shift; -+ -+ if (clockCtl1 & doubler_mask) { -+ multiplier = multiplier << 1; -+ } -+ return (40000000 / preDivisor) * multiplier; -+} -+ -+static inline int -+ar5312_sys_frequency(void) -+{ -+ return ar5312_cpu_frequency() / 4; -+} -+ -+void __init -+ar5312_time_init(void) -+{ -+ if (!is_5312()) -+ return; -+ -+ mips_hpt_frequency = ar5312_cpu_frequency() / 2; -+} -+ -+ -+void __init -+ar5312_prom_init(void) -+{ -+ u32 memsize, memcfg, bank0AC, bank1AC; -+ u32 devid; -+ -+ if (!is_5312()) -+ return; -+ -+ /* Detect memory size */ -+ memcfg = ar231x_read_reg(AR531X_MEM_CFG1); -+ bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S; -+ bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S; -+ memsize = (bank0AC ? (1 << (bank0AC+1)) : 0) -+ + (bank1AC ? (1 << (bank1AC+1)) : 0); -+ memsize <<= 20; -+ add_memory_region(0, memsize, BOOT_MEM_RAM); -+ -+ devid = ar231x_read_reg(AR531X_REV); -+ devid >>= AR531X_REV_WMAC_MIN_S; -+ devid &= AR531X_REV_CHIP; -+ ar231x_board.devid = (u16) devid; -+ ar231x_gpiodev = &ar5312_gpiodev; -+} -+ -+void __init -+ar5312_plat_setup(void) -+{ -+ if (!is_5312()) -+ return; -+ -+ /* Clear any lingering AHB errors */ -+ ar231x_read_reg(AR531X_PROCADDR); -+ ar231x_read_reg(AR531X_DMAADDR); -+ ar231x_write_reg(AR531X_WD_CTRL, AR531X_WD_CTRL_IGNORE_EXPIRATION); -+ -+ _machine_restart = ar5312_restart; -+ ar231x_serial_setup(KSEG1ADDR(AR531X_UART0), ar5312_sys_frequency()); -+} -+ -diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/ar5312.h linux-2.6.39-rc7/arch/mips/ar231x/ar5312.h ---- linux-2.6.39-rc7.orig/arch/mips/ar231x/ar5312.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/ar231x/ar5312.h 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,38 @@ -+#ifndef __AR5312_H -+#define __AR5312_H -+ -+#ifdef CONFIG_ATHEROS_AR5312 -+ -+extern void ar5312_irq_init(void); -+extern int ar5312_init_devices(void); -+extern void ar5312_prom_init(void); -+extern void ar5312_plat_setup(void); -+extern void ar5312_time_init(void); -+extern void ar5312_time_init(void); -+ -+#else -+ -+static inline void ar5312_irq_init(void) -+{ -+} -+ -+static inline int ar5312_init_devices(void) -+{ -+ return 0; -+} -+ -+static inline void ar5312_prom_init(void) -+{ -+} -+ -+static inline void ar5312_plat_setup(void) -+{ -+} -+ -+static inline void ar5312_time_init(void) -+{ -+} -+ -+#endif -+ -+#endif -diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/board.c linux-2.6.39-rc7/arch/mips/ar231x/board.c ---- linux-2.6.39-rc7.orig/arch/mips/ar231x/board.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/ar231x/board.c 2011-05-15 22:16:11.000000000 +0200 -@@ -0,0 +1,261 @@ -+/* -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. -+ * Copyright (C) 2006 FON Technology, SL. -+ * Copyright (C) 2006 Imre Kaloz -+ * Copyright (C) 2006-2009 Felix Fietkau -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include "devices.h" -+#include "ar5312.h" -+#include "ar2315.h" -+ -+void (*ar231x_irq_dispatch)(void); -+ -+static inline bool -+check_radio_magic(u8 *addr) -+{ -+ addr += 0x7a; /* offset for flash magic */ -+ if ((addr[0] == 0x5a) && (addr[1] == 0xa5)) { -+ return 1; -+ } -+ return 0; -+} -+ -+static inline bool -+check_board_data(u8 *flash_limit, u8 *addr, bool broken) -+{ -+ /* config magic found */ -+ if (*((u32 *)addr) == AR531X_BD_MAGIC) -+ return 1; -+ -+ if (!broken) -+ return 0; -+ -+ if (check_radio_magic(addr + 0xf8)) -+ ar231x_board.radio = addr + 0xf8; -+ if ((addr < flash_limit + 0x10000) && -+ check_radio_magic(addr + 0x10000)) -+ ar231x_board.radio = addr + 0x10000; -+ -+ if (ar231x_board.radio) { -+ /* broken board data detected, use radio data to find the offset, -+ * user will fix this */ -+ return 1; -+ } -+ return 0; -+} -+ -+static u8 * -+find_board_config(u8 *flash_limit, bool broken) -+{ -+ u8 *addr; -+ int found = 0; -+ -+ for (addr = flash_limit - 0x1000; -+ addr >= flash_limit - 0x30000; -+ addr -= 0x1000) { -+ -+ if (check_board_data(flash_limit, addr, broken)) { -+ found = 1; -+ break; -+ } -+ } -+ -+ if (!found) -+ addr = NULL; -+ -+ return addr; -+} -+ -+static u8 * -+find_radio_config(u8 *flash_limit, u8 *board_config) -+{ -+ int found; -+ u8 *radio_config; -+ -+ /* -+ * Now find the start of Radio Configuration data, using heuristics: -+ * Search forward from Board Configuration data by 0x1000 bytes -+ * at a time until we find non-0xffffffff. -+ */ -+ found = 0; -+ for (radio_config = board_config + 0x1000; -+ (radio_config < flash_limit); -+ radio_config += 0x1000) { -+ if ((*(u32 *)radio_config != 0xffffffff) && -+ check_radio_magic(radio_config)) { -+ found = 1; -+ break; -+ } -+ } -+ -+ /* AR2316 relocates radio config to new location */ -+ if (!found) { -+ for (radio_config = board_config + 0xf8; -+ (radio_config < flash_limit - 0x1000 + 0xf8); -+ radio_config += 0x1000) { -+ if ((*(u32 *)radio_config != 0xffffffff) && -+ check_radio_magic(radio_config)) { -+ found = 1; -+ break; -+ } -+ } -+ } -+ -+ if (!found) { -+ printk("Could not find Radio Configuration data\n"); -+ radio_config = 0; -+ } -+ -+ return (u8 *) radio_config; -+} -+ -+int __init -+ar231x_find_config(u8 *flash_limit) -+{ -+ struct ar231x_boarddata *config; -+ unsigned int rcfg_size; -+ int broken_boarddata = 0, i, tmp; -+ u8 *bcfg, *rcfg; -+ u8 *board_data; -+ u8 *radio_data; -+ u32 offset; -+ -+ ar231x_board.config = NULL; -+ ar231x_board.radio = NULL; -+ /* Copy the board and radio data to RAM, because accessing the mapped -+ * memory of the flash directly after booting is not safe */ -+ -+ /* Try to find valid board and radio data */ -+ bcfg = find_board_config(flash_limit, false); -+ -+ /* If that fails, try to at least find valid radio data */ -+ if (!bcfg) { -+ bcfg = find_board_config(flash_limit, true); -+ broken_boarddata = 1; -+ } -+ -+ if (!bcfg) { -+ printk(KERN_WARNING "WARNING: No board configuration data found!\n"); -+ return -ENODEV; -+ } -+ -+ board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL); -+ ar231x_board.config = (struct ar231x_boarddata *) board_data; -+ memcpy(board_data, bcfg, 0x100); -+ if (broken_boarddata) { -+ printk(KERN_WARNING "WARNING: broken board data detected\n"); -+ config = ar231x_board.config; -+ if (!memcmp(config->enet0_mac, "\x00\x00\x00\x00\x00\x00", 6)) { -+ printk(KERN_INFO "Fixing up empty mac addresses\n"); -+ config->resetConfigGpio = 0xffff; -+ config->sysLedGpio = 0xffff; -+ random_ether_addr(config->wlan0_mac); -+ config->wlan0_mac[0] &= ~0x06; -+ random_ether_addr(config->enet0_mac); -+ random_ether_addr(config->enet1_mac); -+ } -+ } -+ -+ -+ /* Radio config starts 0x100 bytes after board config, regardless -+ * of what the physical layout on the flash chip looks like */ -+ -+ if (ar231x_board.radio) -+ rcfg = (u8 *) ar231x_board.radio; -+ else -+ rcfg = find_radio_config(flash_limit, bcfg); -+ -+ if (!rcfg) -+ return -ENODEV; -+ -+ radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff); -+ ar231x_board.radio = radio_data; -+ offset = radio_data - board_data; -+ printk(KERN_INFO "Radio config found at offset 0x%x(0x%x)\n", rcfg - bcfg, offset); -+ rcfg_size = BOARD_CONFIG_BUFSZ - offset; -+ memcpy(radio_data, rcfg, rcfg_size); -+ -+ for (tmp = 0xff, i = 0; i < ETH_ALEN; i++) -+ tmp &= radio_data[i + 0x1d * 2]; -+ if (tmp == 0xff) { -+ u16 *eep = (u16 *)radio_data, *bcfgs = (u16 *)bcfg; -+ printk(KERN_INFO "Radio MAC is blank; using board-data\n"); -+ eep[0x1f] = bcfgs[0x30]; -+ eep[0x1e] = bcfgs[0x34]; -+ eep[0x1d] = bcfgs[0x32]; -+ } -+ -+ return 0; -+} -+ -+static void -+ar231x_halt(void) -+{ -+ local_irq_disable(); -+ while (1); -+} -+ -+void __init -+plat_mem_setup(void) -+{ -+ _machine_halt = ar231x_halt; -+ pm_power_off = ar231x_halt; -+ -+ ar5312_plat_setup(); -+ ar2315_plat_setup(); -+ -+ /* Disable data watchpoints */ -+ write_c0_watchlo0(0); -+} -+ -+ -+asmlinkage void -+plat_irq_dispatch(void) -+{ -+ ar231x_irq_dispatch(); -+} -+ -+void __init -+plat_time_init(void) -+{ -+ ar5312_time_init(); -+ ar2315_time_init(); -+} -+ -+unsigned int __cpuinit -+get_c0_compare_int(void) -+{ -+ return CP0_LEGACY_COMPARE_IRQ; -+} -+ -+void __init -+arch_init_irq(void) -+{ -+ clear_c0_status(ST0_IM); -+ mips_cpu_irq_init(); -+ -+ /* Initialize interrupt controllers */ -+ ar5312_irq_init(); -+ ar2315_irq_init(); -+} -+ -+ -diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/devices.c linux-2.6.39-rc7/arch/mips/ar231x/devices.c ---- linux-2.6.39-rc7.orig/arch/mips/ar231x/devices.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/ar231x/devices.c 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,175 @@ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "devices.h" -+#include "ar5312.h" -+#include "ar2315.h" -+ -+struct ar231x_board_config ar231x_board; -+int ar231x_devtype = DEV_TYPE_UNKNOWN; -+const struct ar231x_gpiodev *ar231x_gpiodev; -+EXPORT_SYMBOL(ar231x_gpiodev); -+ -+static struct resource ar231x_eth0_res[] = { -+ { -+ .name = "eth0_membase", -+ .flags = IORESOURCE_MEM, -+ }, -+ { -+ .name = "eth0_irq", -+ .flags = IORESOURCE_IRQ, -+ } -+}; -+ -+static struct resource ar231x_eth1_res[] = { -+ { -+ .name = "eth1_membase", -+ .flags = IORESOURCE_MEM, -+ }, -+ { -+ .name = "eth1_irq", -+ .flags = IORESOURCE_IRQ, -+ } -+}; -+ -+static struct platform_device ar231x_eth[] = { -+ { -+ .id = 0, -+ .name = "ar231x-eth", -+ .resource = ar231x_eth0_res, -+ .num_resources = ARRAY_SIZE(ar231x_eth0_res) -+ }, -+ { -+ .id = 1, -+ .name = "ar231x-eth", -+ .resource = ar231x_eth1_res, -+ .num_resources = ARRAY_SIZE(ar231x_eth1_res) -+ } -+}; -+ -+static struct resource ar231x_wmac0_res[] = { -+ { -+ .name = "wmac0_membase", -+ .flags = IORESOURCE_MEM, -+ }, -+ { -+ .name = "wmac0_irq", -+ .flags = IORESOURCE_IRQ, -+ } -+}; -+ -+static struct resource ar231x_wmac1_res[] = { -+ { -+ .name = "wmac1_membase", -+ .flags = IORESOURCE_MEM, -+ }, -+ { -+ .name = "wmac1_irq", -+ .flags = IORESOURCE_IRQ, -+ } -+}; -+ -+ -+static struct platform_device ar231x_wmac[] = { -+ { -+ .id = 0, -+ .name = "ar231x-wmac", -+ .resource = ar231x_wmac0_res, -+ .num_resources = ARRAY_SIZE(ar231x_wmac0_res), -+ .dev.platform_data = &ar231x_board, -+ }, -+ { -+ .id = 1, -+ .name = "ar231x-wmac", -+ .resource = ar231x_wmac1_res, -+ .num_resources = ARRAY_SIZE(ar231x_wmac1_res), -+ .dev.platform_data = &ar231x_board, -+ }, -+}; -+ -+static const char *devtype_strings[] = { -+ [DEV_TYPE_AR5312] = "Atheros AR5312", -+ [DEV_TYPE_AR2312] = "Atheros AR2312", -+ [DEV_TYPE_AR2313] = "Atheros AR2313", -+ [DEV_TYPE_AR2315] = "Atheros AR2315", -+ [DEV_TYPE_AR2316] = "Atheros AR2316", -+ [DEV_TYPE_AR2317] = "Atheros AR2317", -+ [DEV_TYPE_UNKNOWN] = "Atheros (unknown)", -+}; -+ -+const char *get_system_type(void) -+{ -+ if ((ar231x_devtype >= ARRAY_SIZE(devtype_strings)) || -+ !devtype_strings[ar231x_devtype]) -+ return devtype_strings[DEV_TYPE_UNKNOWN]; -+ return devtype_strings[ar231x_devtype]; -+} -+ -+ -+int __init -+ar231x_add_ethernet(int nr, u32 base, int irq, void *pdata) -+{ -+ struct resource *res; -+ -+ ar231x_eth[nr].dev.platform_data = pdata; -+ res = &ar231x_eth[nr].resource[0]; -+ res->start = base; -+ res->end = base + 0x2000 - 1; -+ res++; -+ res->start = irq; -+ res->end = irq; -+ return platform_device_register(&ar231x_eth[nr]); -+} -+ -+void __init -+ar231x_serial_setup(u32 mapbase, unsigned int uartclk) -+{ -+ struct uart_port s; -+ -+ memset(&s, 0, sizeof(s)); -+ -+ s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST; -+ s.iotype = UPIO_MEM; -+ s.irq = AR531X_MISC_IRQ_UART0; -+ s.regshift = 2; -+ s.mapbase = mapbase; -+ s.uartclk = uartclk; -+ s.membase = (void __iomem *)s.mapbase; -+ -+ early_serial_setup(&s); -+} -+ -+int __init -+ar231x_add_wmac(int nr, u32 base, int irq) -+{ -+ struct resource *res; -+ -+ ar231x_wmac[nr].dev.platform_data = &ar231x_board; -+ res = &ar231x_wmac[nr].resource[0]; -+ res->start = base; -+ res->end = base + 0x10000 - 1; -+ res++; -+ res->start = irq; -+ res->end = irq; -+ return platform_device_register(&ar231x_wmac[nr]); -+} -+ -+static int __init ar231x_register_devices(void) -+{ -+ static struct resource res = { -+ .start = 0xFFFFFFFF, -+ }; -+ -+ platform_device_register_simple("GPIODEV", 0, &res, 1); -+ ar5312_init_devices(); -+ ar2315_init_devices(); -+ -+ return 0; -+} -+ -+device_initcall(ar231x_register_devices); -diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/devices.h linux-2.6.39-rc7/arch/mips/ar231x/devices.h ---- linux-2.6.39-rc7.orig/arch/mips/ar231x/devices.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/ar231x/devices.h 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,37 @@ -+#ifndef __AR231X_DEVICES_H -+#define __AR231X_DEVICES_H -+ -+enum { -+ /* handled by ar5312.c */ -+ DEV_TYPE_AR2312, -+ DEV_TYPE_AR2313, -+ DEV_TYPE_AR5312, -+ -+ /* handled by ar2315.c */ -+ DEV_TYPE_AR2315, -+ DEV_TYPE_AR2316, -+ DEV_TYPE_AR2317, -+ -+ DEV_TYPE_UNKNOWN -+}; -+ -+extern int ar231x_devtype; -+extern struct ar231x_board_config ar231x_board; -+extern asmlinkage void (*ar231x_irq_dispatch)(void); -+ -+extern int ar231x_find_config(u8 *flash_limit); -+extern void ar231x_serial_setup(u32 mapbase, unsigned int uartclk); -+extern int ar231x_add_wmac(int nr, u32 base, int irq); -+extern int ar231x_add_ethernet(int nr, u32 base, int irq, void *pdata); -+ -+static inline bool is_2315(void) -+{ -+ return (current_cpu_data.cputype == CPU_4KEC); -+} -+ -+static inline bool is_5312(void) -+{ -+ return !is_2315(); -+} -+ -+#endif -diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/early_printk.c linux-2.6.39-rc7/arch/mips/ar231x/early_printk.c ---- linux-2.6.39-rc7.orig/arch/mips/ar231x/early_printk.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/ar231x/early_printk.c 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,44 @@ -+/* -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 2010 Gabor Juhos -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include "devices.h" -+ -+static inline void prom_uart_wr(void __iomem *base, unsigned reg, -+ unsigned char ch) -+{ -+ __raw_writeb(ch, base + 4 * reg); -+} -+ -+static inline unsigned char prom_uart_rr(void __iomem *base, unsigned reg) -+{ -+ return __raw_readb(base + 4 * reg); -+} -+ -+void prom_putchar(unsigned char ch) -+{ -+ static void __iomem *base; -+ -+ if (unlikely(base == NULL)) { -+ if (is_2315()) -+ base = (void __iomem *)(KSEG1ADDR(AR2315_UART0)); -+ else -+ base = (void __iomem *)(KSEG1ADDR(AR531X_UART0)); -+ } -+ -+ while ((prom_uart_rr(base, UART_LSR) & UART_LSR_THRE) == 0); -+ prom_uart_wr(base, UART_TX, ch); -+ while ((prom_uart_rr(base, UART_LSR) & UART_LSR_THRE) == 0); -+} -+ -diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/pci.c linux-2.6.39-rc7/arch/mips/ar231x/pci.c ---- linux-2.6.39-rc7.orig/arch/mips/ar231x/pci.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/ar231x/pci.c 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,230 @@ -+/* -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "devices.h" -+ -+#define AR531X_MEM_BASE 0x80800000UL -+#define AR531X_MEM_SIZE 0x00ffffffUL -+#define AR531X_IO_SIZE 0x00007fffUL -+ -+static unsigned long configspace; -+ -+static int config_access(int devfn, int where, int size, u32 *ptr, bool write) -+{ -+ unsigned long flags; -+ int func = PCI_FUNC(devfn); -+ int dev = PCI_SLOT(devfn); -+ u32 value = 0; -+ int err = 0; -+ u32 addr; -+ -+ if (((dev != 0) && (dev != 3)) || (func > 2)) -+ return PCIBIOS_DEVICE_NOT_FOUND; -+ -+ /* Select Configuration access */ -+ local_irq_save(flags); -+ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, 0, AR2315_PCIMISC_CFG_SEL); -+ mb(); -+ -+ addr = (u32) configspace + (1 << (13 + dev)) + (func << 8) + where; -+ if (size == 1) -+ addr ^= 0x3; -+ else if (size == 2) -+ addr ^= 0x2; -+ -+ if (write) { -+ value = *ptr; -+ if (size == 1) -+ err = put_dbe(value, (u8 *) addr); -+ else if (size == 2) -+ err = put_dbe(value, (u16 *) addr); -+ else if (size == 4) -+ err = put_dbe(value, (u32 *) addr); -+ } else { -+ if (size == 1) -+ err = get_dbe(value, (u8 *) addr); -+ else if (size == 2) -+ err = get_dbe(value, (u16 *) addr); -+ else if (size == 4) -+ err = get_dbe(value, (u32 *) addr); -+ if (err) -+ *ptr = 0xffffffff; -+ else -+ *ptr = value; -+ } -+ -+ /* Select Memory access */ -+ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_CFG_SEL, 0); -+ local_irq_restore(flags); -+ -+ return (err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL); -+} -+ -+static int ar231x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * value) -+{ -+ return config_access(devfn, where, size, value, 0); -+} -+ -+static int ar231x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value) -+{ -+ return config_access(devfn, where, size, &value, 1); -+} -+ -+struct pci_ops ar231x_pci_ops = { -+ .read = ar231x_pci_read, -+ .write = ar231x_pci_write, -+}; -+ -+static struct resource ar231x_mem_resource = { -+ .name = "AR531x PCI MEM", -+ .start = AR531X_MEM_BASE, -+ .end = AR531X_MEM_BASE + AR531X_MEM_SIZE - AR531X_IO_SIZE - 1 + 0x4000000, -+ .flags = IORESOURCE_MEM, -+}; -+ -+static struct resource ar231x_io_resource = { -+ .name = "AR531x PCI I/O", -+ .start = AR531X_MEM_BASE + AR531X_MEM_SIZE - AR531X_IO_SIZE, -+ .end = AR531X_MEM_BASE + AR531X_MEM_SIZE - 1, -+ .flags = IORESOURCE_IO, -+}; -+ -+struct pci_controller ar231x_pci_controller = { -+ .pci_ops = &ar231x_pci_ops, -+ .mem_resource = &ar231x_mem_resource, -+ .io_resource = &ar231x_io_resource, -+ .mem_offset = 0x00000000UL, -+ .io_offset = 0x00000000UL, -+}; -+ -+int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -+{ -+ return AR2315_IRQ_LCBUS_PCI; -+} -+ -+int pcibios_plat_dev_init(struct pci_dev *dev) -+{ -+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 5); -+ pci_write_config_word(dev, 0x40, 0); -+ -+ /* Clear any pending Abort or external Interrupts -+ * and enable interrupt processing */ -+ ar231x_mask_reg(AR2315_PCI_INTEN_REG, AR2315_PCI_INT_ENABLE, 0); -+ ar231x_write_reg(AR2315_PCI_INT_STATUS, (AR2315_PCI_ABORT_INT | AR2315_PCI_EXT_INT)); -+ ar231x_write_reg(AR2315_PCI_INT_MASK, (AR2315_PCI_ABORT_INT | AR2315_PCI_EXT_INT)); -+ ar231x_mask_reg(AR2315_PCI_INTEN_REG, 0, AR2315_PCI_INT_ENABLE); -+ -+ return 0; -+} -+ -+static void -+ar2315_pci_fixup(struct pci_dev *dev) -+{ -+ unsigned int devfn = dev->devfn; -+ -+ if (dev->bus->number != 0) -+ return; -+ -+ /* Only fix up the PCI host settings */ -+ if ((PCI_SLOT(devfn) != 3) || (PCI_FUNC(devfn) != 0)) -+ return; -+ -+ /* Fix up MBARs */ -+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, HOST_PCI_MBAR0); -+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, HOST_PCI_MBAR1); -+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, HOST_PCI_MBAR2); -+ pci_write_config_dword(dev, PCI_COMMAND, -+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL | -+ PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | -+ PCI_COMMAND_FAST_BACK); -+} -+DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, ar2315_pci_fixup); -+ -+static int __init -+ar2315_pci_init(void) -+{ -+ u32 reg; -+ -+ if (ar231x_devtype != DEV_TYPE_AR2315) -+ return -ENODEV; -+ -+ configspace = (unsigned long) ioremap_nocache(0x80000000, 1*1024*1024); /* Remap PCI config space */ -+ ar231x_pci_controller.io_map_base = -+ (unsigned long) ioremap_nocache(AR531X_MEM_BASE + AR531X_MEM_SIZE, AR531X_IO_SIZE); -+ set_io_port_base(ar231x_pci_controller.io_map_base); /* PCI I/O space */ -+ -+ reg = ar231x_mask_reg(AR2315_RESET, 0, AR2315_RESET_PCIDMA); -+ msleep(10); -+ -+ reg &= ~AR2315_RESET_PCIDMA; -+ ar231x_write_reg(AR2315_RESET, reg); -+ msleep(10); -+ -+ ar231x_mask_reg(AR2315_ENDIAN_CTL, 0, -+ AR2315_CONFIG_PCIAHB | AR2315_CONFIG_PCIAHB_BRIDGE); -+ -+ ar231x_write_reg(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM | -+ (AR2315_PCICLK_IN_FREQ_DIV_6 << AR2315_PCICLK_DIV_S)); -+ ar231x_mask_reg(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI); -+ ar231x_mask_reg(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK | AR2315_IF_MASK, -+ AR2315_IF_PCI | AR2315_IF_PCI_HOST | AR2315_IF_PCI_INTR | -+ (AR2315_IF_PCI_CLK_OUTPUT_CLK << AR2315_IF_PCI_CLK_SHIFT)); -+ -+ /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */ -+ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE, -+ AR2315_PCIRST_LOW); -+ msleep(100); -+ -+ /* Bring the PCI out of reset */ -+ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE, -+ AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8); -+ -+ ar231x_write_reg(AR2315_PCI_UNCACHE_CFG, -+ 0x1E | /* 1GB uncached */ -+ (1 << 5) | /* Enable uncached */ -+ (0x2 << 30) /* Base: 0x80000000 */ -+ ); -+ ar231x_read_reg(AR2315_PCI_UNCACHE_CFG); -+ -+ msleep(500); -+ -+ /* dirty hack - anyone with a datasheet that knows the memory map ? */ -+ ioport_resource.start = 0x10000000; -+ ioport_resource.end = 0xffffffff; -+ iomem_resource.start = 0x10000000; -+ iomem_resource.end = 0xffffffff; -+ -+ register_pci_controller(&ar231x_pci_controller); -+ -+ return 0; -+} -+ -+arch_initcall(ar2315_pci_init); -diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/prom.c linux-2.6.39-rc7/arch/mips/ar231x/prom.c ---- linux-2.6.39-rc7.orig/arch/mips/ar231x/prom.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/ar231x/prom.c 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,37 @@ -+/* -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright MontaVista Software Inc -+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. -+ * Copyright (C) 2006 FON Technology, SL. -+ * Copyright (C) 2006 Imre Kaloz -+ * Copyright (C) 2006 Felix Fietkau -+ */ -+ -+/* -+ * Prom setup file for ar531x -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include "ar5312.h" -+#include "ar2315.h" -+ -+void __init prom_init(void) -+{ -+ ar5312_prom_init(); -+ ar2315_prom_init(); -+} -+ -+void __init prom_free_prom_memory(void) -+{ -+} -diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/reset.c linux-2.6.39-rc7/arch/mips/ar231x/reset.c ---- linux-2.6.39-rc7.orig/arch/mips/ar231x/reset.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/ar231x/reset.c 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,161 @@ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "devices.h" -+ -+#define AR531X_RESET_GPIO_IRQ (AR531X_GPIO_IRQ(ar231x_board.config->resetConfigGpio)) -+ -+struct event_t { -+ struct work_struct wq; -+ int set; -+ unsigned long jiffies; -+}; -+ -+static struct timer_list rst_button_timer; -+static unsigned long seen; -+ -+struct sock *uevent_sock = NULL; -+EXPORT_SYMBOL_GPL(uevent_sock); -+extern u64 uevent_next_seqnum(void); -+ -+static int no_release_workaround = 1; -+module_param(no_release_workaround, int, 0); -+ -+static inline void -+add_msg(struct sk_buff *skb, char *msg) -+{ -+ char *scratch; -+ scratch = skb_put(skb, strlen(msg) + 1); -+ sprintf(scratch, msg); -+} -+ -+static void -+hotplug_button(struct work_struct *wq) -+{ -+ struct sk_buff *skb; -+ struct event_t *event; -+ size_t len; -+ char *scratch, *s; -+ char buf[128]; -+ -+ event = container_of(wq, struct event_t, wq); -+ if (!uevent_sock) -+ goto done; -+ -+ /* allocate message with the maximum possible size */ -+ s = event->set ? "pressed" : "released"; -+ len = strlen(s) + 2; -+ skb = alloc_skb(NLMSG_GOODSIZE, GFP_KERNEL); -+ if (!skb) -+ goto done; -+ -+ /* add header */ -+ scratch = skb_put(skb, len); -+ sprintf(scratch, "%s@",s); -+ -+ /* copy keys to our continuous event payload buffer */ -+ add_msg(skb, "HOME=/"); -+ add_msg(skb, "PATH=/sbin:/bin:/usr/sbin:/usr/bin"); -+ add_msg(skb, "SUBSYSTEM=button"); -+ add_msg(skb, "BUTTON=reset"); -+ add_msg(skb, (event->set ? "ACTION=pressed" : "ACTION=released")); -+ sprintf(buf, "SEEN=%ld", (event->jiffies - seen)/HZ); -+ add_msg(skb, buf); -+ snprintf(buf, 128, "SEQNUM=%llu", uevent_next_seqnum()); -+ add_msg(skb, buf); -+ -+ NETLINK_CB(skb).dst_group = 1; -+ netlink_broadcast(uevent_sock, skb, 0, 1, GFP_KERNEL); -+ -+done: -+ kfree(event); -+} -+ -+static void -+reset_button_poll(unsigned long unused) -+{ -+ struct event_t *event; -+ int gpio = ~0; -+ -+ if(!no_release_workaround) -+ return; -+ -+ gpio = ar231x_gpiodev->get(); -+ gpio &= (1 << (AR531X_RESET_GPIO_IRQ - AR531X_GPIO_IRQ_BASE)); -+ if(gpio) { -+ rst_button_timer.expires = jiffies + (HZ / 4); -+ add_timer(&rst_button_timer); -+ return; -+ } -+ -+ event = (struct event_t *) kzalloc(sizeof(struct event_t), GFP_ATOMIC); -+ if (!event) -+ return; -+ -+ event->set = 0; -+ event->jiffies = jiffies; -+ INIT_WORK(&event->wq, hotplug_button); -+ schedule_work(&event->wq); -+} -+ -+static irqreturn_t -+button_handler(int irq, void *dev_id) -+{ -+ static int pressed = 0; -+ struct event_t *event; -+ u32 gpio = ~0; -+ -+ event = (struct event_t *) kzalloc(sizeof(struct event_t), GFP_ATOMIC); -+ if (!event) -+ return IRQ_NONE; -+ -+ pressed = !pressed; -+ -+ gpio = ar231x_gpiodev->get() & (1 << (irq - AR531X_GPIO_IRQ_BASE)); -+ -+ event->set = gpio; -+ if(!event->set) -+ no_release_workaround = 0; -+ -+ event->jiffies = jiffies; -+ -+ INIT_WORK(&event->wq, hotplug_button); -+ schedule_work(&event->wq); -+ -+ seen = jiffies; -+ if(event->set && no_release_workaround) -+ mod_timer(&rst_button_timer, jiffies + (HZ / 4)); -+ -+ return IRQ_HANDLED; -+} -+ -+ -+static int __init -+ar231x_init_reset(void) -+{ -+ seen = jiffies; -+ -+ if (ar231x_board.config->resetConfigGpio == 0xffff) -+ return -ENODEV; -+ -+ init_timer(&rst_button_timer); -+ rst_button_timer.function = reset_button_poll; -+ rst_button_timer.expires = jiffies + HZ / 50; -+ add_timer(&rst_button_timer); -+ -+ request_irq(AR531X_RESET_GPIO_IRQ, &button_handler, IRQF_SAMPLE_RANDOM, "ar231x_reset", NULL); -+ -+ return 0; -+} -+ -+module_init(ar231x_init_reset); -diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar2315_regs.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar2315_regs.h ---- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar2315_regs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar2315_regs.h 2011-05-15 21:44:12.000000000 +0200 -@@ -0,0 +1,580 @@ -+/* -+ * Register definitions for AR2315+ -+ * -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. -+ * Copyright (C) 2006 FON Technology, SL. -+ * Copyright (C) 2006 Imre Kaloz -+ * Copyright (C) 2006-2008 Felix Fietkau -+ */ -+ -+#ifndef __AR2315_REG_H -+#define __AR2315_REG_H -+ -+/* -+ * IRQs -+ */ -+#define AR2315_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */ -+#define AR2315_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */ -+#define AR2315_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */ -+#define AR2315_IRQ_LCBUS_PCI MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */ -+#define AR2315_IRQ_WLAN0_POLL MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */ -+ -+/* -+ * Address map -+ */ -+#define AR2315_SPI_READ 0x08000000 /* SPI FLASH */ -+#define AR2315_WLAN0 0x10000000 /* Wireless MMR */ -+#define AR2315_PCI 0x10100000 /* PCI MMR */ -+#define AR2315_SDRAMCTL 0x10300000 /* SDRAM MMR */ -+#define AR2315_LOCAL 0x10400000 /* LOCAL BUS MMR */ -+#define AR2315_ENET0 0x10500000 /* ETHERNET MMR */ -+#define AR2315_DSLBASE 0x11000000 /* RESET CONTROL MMR */ -+#define AR2315_UART0 0x11100003 /* UART MMR */ -+#define AR2315_SPI 0x11300000 /* SPI FLASH MMR */ -+#define AR2315_PCIEXT 0x80000000 /* pci external */ -+ -+/* -+ * Reset Register -+ */ -+#define AR2315_COLD_RESET (AR2315_DSLBASE + 0x0000) -+ -+#define AR2315_RESET_COLD_AHB 0x00000001 -+#define AR2315_RESET_COLD_APB 0x00000002 -+#define AR2315_RESET_COLD_CPU 0x00000004 -+#define AR2315_RESET_COLD_CPUWARM 0x00000008 -+#define AR2315_RESET_SYSTEM (RESET_COLD_CPU | RESET_COLD_APB | RESET_COLD_AHB) /* full system */ -+#define AR2317_RESET_SYSTEM 0x00000010 -+ -+ -+#define AR2315_RESET (AR2315_DSLBASE + 0x0004) -+ -+#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001 /* warm reset WLAN0 MAC */ -+#define AR2315_RESET_WARM_WLAN0_BB 0x00000002 /* warm reset WLAN0 BaseBand */ -+#define AR2315_RESET_MPEGTS_RSVD 0x00000004 /* warm reset MPEG-TS */ -+#define AR2315_RESET_PCIDMA 0x00000008 /* warm reset PCI ahb/dma */ -+#define AR2315_RESET_MEMCTL 0x00000010 /* warm reset memory controller */ -+#define AR2315_RESET_LOCAL 0x00000020 /* warm reset local bus */ -+#define AR2315_RESET_I2C_RSVD 0x00000040 /* warm reset I2C bus */ -+#define AR2315_RESET_SPI 0x00000080 /* warm reset SPI interface */ -+#define AR2315_RESET_UART0 0x00000100 /* warm reset UART0 */ -+#define AR2315_RESET_IR_RSVD 0x00000200 /* warm reset IR interface */ -+#define AR2315_RESET_EPHY0 0x00000400 /* cold reset ENET0 phy */ -+#define AR2315_RESET_ENET0 0x00000800 /* cold reset ENET0 mac */ -+ -+/* -+ * AHB master arbitration control -+ */ -+#define AR2315_AHB_ARB_CTL (AR2315_DSLBASE + 0x0008) -+ -+#define AR2315_ARB_CPU 0x00000001 /* CPU, default */ -+#define AR2315_ARB_WLAN 0x00000002 /* WLAN */ -+#define AR2315_ARB_MPEGTS_RSVD 0x00000004 /* MPEG-TS */ -+#define AR2315_ARB_LOCAL 0x00000008 /* LOCAL */ -+#define AR2315_ARB_PCI 0x00000010 /* PCI */ -+#define AR2315_ARB_ETHERNET 0x00000020 /* Ethernet */ -+#define AR2315_ARB_RETRY 0x00000100 /* retry policy, debug only */ -+ -+/* -+ * Config Register -+ */ -+#define AR2315_ENDIAN_CTL (AR2315_DSLBASE + 0x000c) -+ -+#define AR2315_CONFIG_AHB 0x00000001 /* EC - AHB bridge endianess */ -+#define AR2315_CONFIG_WLAN 0x00000002 /* WLAN byteswap */ -+#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004 /* MPEG-TS byteswap */ -+#define AR2315_CONFIG_PCI 0x00000008 /* PCI byteswap */ -+#define AR2315_CONFIG_MEMCTL 0x00000010 /* Memory controller endianess */ -+#define AR2315_CONFIG_LOCAL 0x00000020 /* Local bus byteswap */ -+#define AR2315_CONFIG_ETHERNET 0x00000040 /* Ethernet byteswap */ -+ -+#define AR2315_CONFIG_MERGE 0x00000200 /* CPU write buffer merge */ -+#define AR2315_CONFIG_CPU 0x00000400 /* CPU big endian */ -+#define AR2315_CONFIG_PCIAHB 0x00000800 -+#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000 -+#define AR2315_CONFIG_SPI 0x00008000 /* SPI byteswap */ -+#define AR2315_CONFIG_CPU_DRAM 0x00010000 -+#define AR2315_CONFIG_CPU_PCI 0x00020000 -+#define AR2315_CONFIG_CPU_MMR 0x00040000 -+#define AR2315_CONFIG_BIG 0x00000400 -+ -+ -+/* -+ * NMI control -+ */ -+#define AR2315_NMI_CTL (AR2315_DSLBASE + 0x0010) -+ -+#define AR2315_NMI_EN 1 -+ -+/* -+ * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR531X 1.0). -+ */ -+#define AR2315_SREV (AR2315_DSLBASE + 0x0014) -+ -+#define AR2315_REV_MAJ 0x00f0 -+#define AR2315_REV_MAJ_S 4 -+#define AR2315_REV_MIN 0x000f -+#define AR2315_REV_MIN_S 0 -+#define AR2315_REV_CHIP (AR2315_REV_MAJ|AR2315_REV_MIN) -+ -+/* -+ * Interface Enable -+ */ -+#define AR2315_IF_CTL (AR2315_DSLBASE + 0x0018) -+ -+#define AR2315_IF_MASK 0x00000007 -+#define AR2315_IF_DISABLED 0 -+#define AR2315_IF_PCI 1 -+#define AR2315_IF_TS_LOCAL 2 -+#define AR2315_IF_ALL 3 /* only for emulation with separate pins */ -+#define AR2315_IF_LOCAL_HOST 0x00000008 -+#define AR2315_IF_PCI_HOST 0x00000010 -+#define AR2315_IF_PCI_INTR 0x00000020 -+#define AR2315_IF_PCI_CLK_MASK 0x00030000 -+#define AR2315_IF_PCI_CLK_INPUT 0 -+#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1 -+#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2 -+#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3 -+#define AR2315_IF_PCI_CLK_SHIFT 16 -+ -+/* -+ * APB Interrupt control -+ */ -+ -+#define AR2315_ISR (AR2315_DSLBASE + 0x0020) -+#define AR2315_IMR (AR2315_DSLBASE + 0x0024) -+#define AR2315_GISR (AR2315_DSLBASE + 0x0028) -+ -+#define AR2315_ISR_UART0 0x0001 /* high speed UART */ -+#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */ -+#define AR2315_ISR_SPI 0x0004 /* SPI bus */ -+#define AR2315_ISR_AHB 0x0008 /* AHB error */ -+#define AR2315_ISR_APB 0x0010 /* APB error */ -+#define AR2315_ISR_TIMER 0x0020 /* timer */ -+#define AR2315_ISR_GPIO 0x0040 /* GPIO */ -+#define AR2315_ISR_WD 0x0080 /* watchdog */ -+#define AR2315_ISR_IR_RSVD 0x0100 /* IR */ -+ -+#define AR2315_GISR_MISC 0x0001 -+#define AR2315_GISR_WLAN0 0x0002 -+#define AR2315_GISR_MPEGTS_RSVD 0x0004 -+#define AR2315_GISR_LOCALPCI 0x0008 -+#define AR2315_GISR_WMACPOLL 0x0010 -+#define AR2315_GISR_TIMER 0x0020 -+#define AR2315_GISR_ETHERNET 0x0040 -+ -+/* -+ * Interrupt routing from IO to the processor IP bits -+ * Define our inter mask and level -+ */ -+#define AR2315_INTR_MISCIO SR_IBIT3 -+#define AR2315_INTR_WLAN0 SR_IBIT4 -+#define AR2315_INTR_ENET0 SR_IBIT5 -+#define AR2315_INTR_LOCALPCI SR_IBIT6 -+#define AR2315_INTR_WMACPOLL SR_IBIT7 -+#define AR2315_INTR_COMPARE SR_IBIT8 -+ -+/* -+ * Timers -+ */ -+#define AR2315_TIMER (AR2315_DSLBASE + 0x0030) -+#define AR2315_RELOAD (AR2315_DSLBASE + 0x0034) -+#define AR2315_WD (AR2315_DSLBASE + 0x0038) -+#define AR2315_WDC (AR2315_DSLBASE + 0x003c) -+ -+#define AR2315_WDC_IGNORE_EXPIRATION 0x00000000 -+#define AR2315_WDC_NMI 0x00000001 /* NMI on watchdog */ -+#define AR2315_WDC_RESET 0x00000002 /* reset on watchdog */ -+ -+/* -+ * CPU Performance Counters -+ */ -+#define AR2315_PERFCNT0 (AR2315_DSLBASE + 0x0048) -+#define AR2315_PERFCNT1 (AR2315_DSLBASE + 0x004c) -+ -+#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */ -+#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */ -+#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */ -+#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */ -+#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */ -+#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */ -+#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */ -+ -+#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */ -+#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */ -+#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */ -+#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */ -+#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */ -+#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */ -+#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */ -+ -+/* -+ * AHB Error Reporting. -+ */ -+#define AR2315_AHB_ERR0 (AR2315_DSLBASE + 0x0050) /* error */ -+#define AR2315_AHB_ERR1 (AR2315_DSLBASE + 0x0054) /* haddr */ -+#define AR2315_AHB_ERR2 (AR2315_DSLBASE + 0x0058) /* hwdata */ -+#define AR2315_AHB_ERR3 (AR2315_DSLBASE + 0x005c) /* hrdata */ -+#define AR2315_AHB_ERR4 (AR2315_DSLBASE + 0x0060) /* status */ -+ -+#define AHB_ERROR_DET 1 /* AHB Error has been detected, */ -+ /* write 1 to clear all bits in ERR0 */ -+#define AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */ -+#define AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */ -+ -+#define AR2315_PROCERR_HMAST 0x0000000f -+#define AR2315_PROCERR_HMAST_DFLT 0 -+#define AR2315_PROCERR_HMAST_WMAC 1 -+#define AR2315_PROCERR_HMAST_ENET 2 -+#define AR2315_PROCERR_HMAST_PCIENDPT 3 -+#define AR2315_PROCERR_HMAST_LOCAL 4 -+#define AR2315_PROCERR_HMAST_CPU 5 -+#define AR2315_PROCERR_HMAST_PCITGT 6 -+ -+#define AR2315_PROCERR_HMAST_S 0 -+#define AR2315_PROCERR_HWRITE 0x00000010 -+#define AR2315_PROCERR_HSIZE 0x00000060 -+#define AR2315_PROCERR_HSIZE_S 5 -+#define AR2315_PROCERR_HTRANS 0x00000180 -+#define AR2315_PROCERR_HTRANS_S 7 -+#define AR2315_PROCERR_HBURST 0x00000e00 -+#define AR2315_PROCERR_HBURST_S 9 -+ -+/* -+ * Clock Control -+ */ -+#define AR2315_PLLC_CTL (AR2315_DSLBASE + 0x0064) -+#define AR2315_PLLV_CTL (AR2315_DSLBASE + 0x0068) -+#define AR2315_CPUCLK (AR2315_DSLBASE + 0x006c) -+#define AR2315_AMBACLK (AR2315_DSLBASE + 0x0070) -+#define AR2315_SYNCCLK (AR2315_DSLBASE + 0x0074) -+#define AR2315_DSL_SLEEP_CTL (AR2315_DSLBASE + 0x0080) -+#define AR2315_DSL_SLEEP_DUR (AR2315_DSLBASE + 0x0084) -+ -+/* PLLc Control fields */ -+#define PLLC_REF_DIV_M 0x00000003 -+#define PLLC_REF_DIV_S 0 -+#define PLLC_FDBACK_DIV_M 0x0000007C -+#define PLLC_FDBACK_DIV_S 2 -+#define PLLC_ADD_FDBACK_DIV_M 0x00000080 -+#define PLLC_ADD_FDBACK_DIV_S 7 -+#define PLLC_CLKC_DIV_M 0x0001c000 -+#define PLLC_CLKC_DIV_S 14 -+#define PLLC_CLKM_DIV_M 0x00700000 -+#define PLLC_CLKM_DIV_S 20 -+ -+/* CPU CLK Control fields */ -+#define CPUCLK_CLK_SEL_M 0x00000003 -+#define CPUCLK_CLK_SEL_S 0 -+#define CPUCLK_CLK_DIV_M 0x0000000c -+#define CPUCLK_CLK_DIV_S 2 -+ -+/* AMBA CLK Control fields */ -+#define AMBACLK_CLK_SEL_M 0x00000003 -+#define AMBACLK_CLK_SEL_S 0 -+#define AMBACLK_CLK_DIV_M 0x0000000c -+#define AMBACLK_CLK_DIV_S 2 -+ -+/* -+ * GPIO -+ */ -+#define AR2315_GPIO_DI (AR2315_DSLBASE + 0x0088) -+#define AR2315_GPIO_DO (AR2315_DSLBASE + 0x0090) -+#define AR2315_GPIO_CR (AR2315_DSLBASE + 0x0098) -+#define AR2315_GPIO_INT (AR2315_DSLBASE + 0x00a0) -+ -+#define AR2315_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */ -+#define AR2315_GPIO_CR_O(x) (1 << (x)) /* output */ -+#define AR2315_GPIO_CR_I(x) (0) /* input */ -+ -+#define AR2315_GPIO_INT_S(x) (x) /* interrupt enable */ -+#define AR2315_GPIO_INT_M (0x3F) /* mask for int */ -+#define AR2315_GPIO_INT_LVL(x) ((x) << 6) /* interrupt level */ -+#define AR2315_GPIO_INT_LVL_M ((0x3) << 6) /* mask for int level */ -+ -+#define AR2315_GPIO_INT_MAX_Y 1 /* Maximum value of Y for AR5313_GPIO_INT_* macros */ -+#define AR2315_GPIO_INT_LVL_OFF 0 /* Triggerring off */ -+#define AR2315_GPIO_INT_LVL_LOW 1 /* Low Level Triggered */ -+#define AR2315_GPIO_INT_LVL_HIGH 2 /* High Level Triggered */ -+#define AR2315_GPIO_INT_LVL_EDGE 3 /* Edge Triggered */ -+ -+#define AR2315_RESET_GPIO 5 -+#define AR2315_NUM_GPIO 22 -+ -+/* -+ * PCI Clock Control -+ */ -+#define AR2315_PCICLK (AR2315_DSLBASE + 0x00a4) -+ -+#define AR2315_PCICLK_INPUT_M 0x3 -+#define AR2315_PCICLK_INPUT_S 0 -+ -+#define AR2315_PCICLK_PLLC_CLKM 0 -+#define AR2315_PCICLK_PLLC_CLKM1 1 -+#define AR2315_PCICLK_PLLC_CLKC 2 -+#define AR2315_PCICLK_REF_CLK 3 -+ -+#define AR2315_PCICLK_DIV_M 0xc -+#define AR2315_PCICLK_DIV_S 2 -+ -+#define AR2315_PCICLK_IN_FREQ 0 -+#define AR2315_PCICLK_IN_FREQ_DIV_6 1 -+#define AR2315_PCICLK_IN_FREQ_DIV_8 2 -+#define AR2315_PCICLK_IN_FREQ_DIV_10 3 -+ -+/* -+ * Observation Control Register -+ */ -+#define AR2315_OCR (AR2315_DSLBASE + 0x00b0) -+#define OCR_GPIO0_IRIN 0x0040 -+#define OCR_GPIO1_IROUT 0x0080 -+#define OCR_GPIO3_RXCLR 0x0200 -+ -+/* -+ * General Clock Control -+ */ -+ -+#define AR2315_MISCCLK (AR2315_DSLBASE + 0x00b4) -+#define MISCCLK_PLLBYPASS_EN 0x00000001 -+#define MISCCLK_PROCREFCLK 0x00000002 -+ -+/* -+ * SDRAM Controller -+ * - No read or write buffers are included. -+ */ -+#define AR2315_MEM_CFG (AR2315_SDRAMCTL + 0x00) -+#define AR2315_MEM_CTRL (AR2315_SDRAMCTL + 0x0c) -+#define AR2315_MEM_REF (AR2315_SDRAMCTL + 0x10) -+ -+#define SDRAM_DATA_WIDTH_M 0x00006000 -+#define SDRAM_DATA_WIDTH_S 13 -+ -+#define SDRAM_COL_WIDTH_M 0x00001E00 -+#define SDRAM_COL_WIDTH_S 9 -+ -+#define SDRAM_ROW_WIDTH_M 0x000001E0 -+#define SDRAM_ROW_WIDTH_S 5 -+ -+#define SDRAM_BANKADDR_BITS_M 0x00000018 -+#define SDRAM_BANKADDR_BITS_S 3 -+ -+/* -+ * SPI Flash Interface Registers -+ */ -+ -+#define AR2315_SPI_CTL (AR2315_SPI + 0x00) -+#define AR2315_SPI_OPCODE (AR2315_SPI + 0x04) -+#define AR2315_SPI_DATA (AR2315_SPI + 0x08) -+ -+#define SPI_CTL_START 0x00000100 -+#define SPI_CTL_BUSY 0x00010000 -+#define SPI_CTL_TXCNT_MASK 0x0000000f -+#define SPI_CTL_RXCNT_MASK 0x000000f0 -+#define SPI_CTL_TX_RX_CNT_MASK 0x000000ff -+#define SPI_CTL_SIZE_MASK 0x00060000 -+ -+#define SPI_CTL_CLK_SEL_MASK 0x03000000 -+#define SPI_OPCODE_MASK 0x000000ff -+ -+/* -+ * PCI Bus Interface Registers -+ */ -+#define AR2315_PCI_1MS_REG (AR2315_PCI + 0x0008) -+#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */ -+ -+#define AR2315_PCI_MISC_CONFIG (AR2315_PCI + 0x000c) -+#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */ -+#define AR2315_PCIMISC_CFG_SEL 0x00000002 /* mem or config cycles */ -+#define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */ -+#define AR2315_PCIMISC_RST_MODE 0x00000030 -+#define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */ -+#define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */ -+#define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */ -+#define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */ -+#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */ -+#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */ -+#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */ -+#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache disable */ -+ -+#define AR2315_PCI_OUT_TSTAMP (AR2315_PCI + 0x0010) -+ -+#define AR2315_PCI_UNCACHE_CFG (AR2315_PCI + 0x0014) -+ -+#define AR2315_PCI_IN_EN (AR2315_PCI + 0x0100) -+#define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */ -+#define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */ -+#define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */ -+#define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */ -+ -+#define AR2315_PCI_IN_DIS (AR2315_PCI + 0x0104) -+#define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */ -+#define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */ -+#define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */ -+#define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */ -+ -+#define AR2315_PCI_IN_PTR (AR2315_PCI + 0x0200) -+ -+#define AR2315_PCI_OUT_EN (AR2315_PCI + 0x0400) -+#define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */ -+ -+#define AR2315_PCI_OUT_DIS (AR2315_PCI + 0x0404) -+#define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */ -+ -+#define AR2315_PCI_OUT_PTR (AR2315_PCI + 0x0408) -+ -+#define AR2315_PCI_INT_STATUS (AR2315_PCI + 0x0500) /* write one to clr */ -+#define AR2315_PCI_TXINT 0x00000001 /* Desc In Completed */ -+#define AR2315_PCI_TXOK 0x00000002 /* Desc In OK */ -+#define AR2315_PCI_TXERR 0x00000004 /* Desc In ERR */ -+#define AR2315_PCI_TXEOL 0x00000008 /* Desc In End-of-List */ -+#define AR2315_PCI_RXINT 0x00000010 /* Desc Out Completed */ -+#define AR2315_PCI_RXOK 0x00000020 /* Desc Out OK */ -+#define AR2315_PCI_RXERR 0x00000040 /* Desc Out ERR */ -+#define AR2315_PCI_RXEOL 0x00000080 /* Desc Out EOL */ -+#define AR2315_PCI_TXOOD 0x00000200 /* Desc In Out-of-Desc */ -+#define AR2315_PCI_MASK 0x0000FFFF /* Desc Mask */ -+#define AR2315_PCI_EXT_INT 0x02000000 -+#define AR2315_PCI_ABORT_INT 0x04000000 -+ -+#define AR2315_PCI_INT_MASK (AR2315_PCI + 0x0504) /* same as INT_STATUS */ -+ -+#define AR2315_PCI_INTEN_REG (AR2315_PCI + 0x0508) -+#define AR2315_PCI_INT_DISABLE 0x00 /* disable pci interrupts */ -+#define AR2315_PCI_INT_ENABLE 0x01 /* enable pci interrupts */ -+ -+#define AR2315_PCI_HOST_IN_EN (AR2315_PCI + 0x0800) -+#define AR2315_PCI_HOST_IN_DIS (AR2315_PCI + 0x0804) -+#define AR2315_PCI_HOST_IN_PTR (AR2315_PCI + 0x0810) -+#define AR2315_PCI_HOST_OUT_EN (AR2315_PCI + 0x0900) -+#define AR2315_PCI_HOST_OUT_DIS (AR2315_PCI + 0x0904) -+#define AR2315_PCI_HOST_OUT_PTR (AR2315_PCI + 0x0908) -+ -+ -+/* -+ * Local Bus Interface Registers -+ */ -+#define AR2315_LB_CONFIG (AR2315_LOCAL + 0x0000) -+#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */ -+#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */ -+#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */ -+#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */ -+#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */ -+#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */ -+#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */ -+#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */ -+#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */ -+#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */ -+#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */ -+#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */ -+#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */ -+#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */ -+#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */ -+#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */ -+#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */ -+#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */ -+#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */ -+#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */ -+#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */ -+#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */ -+#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */ -+#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */ -+#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */ -+ -+#define AR2315_LB_CLKSEL (AR2315_LOCAL + 0x0004) -+#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */ -+ -+#define AR2315_LB_1MS (AR2315_LOCAL + 0x0008) -+#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */ -+ -+#define AR2315_LB_MISCCFG (AR2315_LOCAL + 0x000C) -+#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */ -+#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */ -+#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */ -+#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */ -+#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */ -+#define AR2315_LBM_TIMEOUT_MASK 0x00FFFF80 -+#define AR2315_LBM_TIMEOUT_SHFT 7 -+#define AR2315_LBM_PORTMUX 0x07000000 -+ -+ -+#define AR2315_LB_RXTSOFF (AR2315_LOCAL + 0x0010) -+ -+#define AR2315_LB_TX_CHAIN_EN (AR2315_LOCAL + 0x0100) -+#define AR2315_LB_TXEN_0 0x01 -+#define AR2315_LB_TXEN_1 0x02 -+#define AR2315_LB_TXEN_2 0x04 -+#define AR2315_LB_TXEN_3 0x08 -+ -+#define AR2315_LB_TX_CHAIN_DIS (AR2315_LOCAL + 0x0104) -+#define AR2315_LB_TX_DESC_PTR (AR2315_LOCAL + 0x0200) -+ -+#define AR2315_LB_RX_CHAIN_EN (AR2315_LOCAL + 0x0400) -+#define AR2315_LB_RXEN 0x01 -+ -+#define AR2315_LB_RX_CHAIN_DIS (AR2315_LOCAL + 0x0404) -+#define AR2315_LB_RX_DESC_PTR (AR2315_LOCAL + 0x0408) -+ -+#define AR2315_LB_INT_STATUS (AR2315_LOCAL + 0x0500) -+#define AR2315_INT_TX_DESC 0x0001 -+#define AR2315_INT_TX_OK 0x0002 -+#define AR2315_INT_TX_ERR 0x0004 -+#define AR2315_INT_TX_EOF 0x0008 -+#define AR2315_INT_RX_DESC 0x0010 -+#define AR2315_INT_RX_OK 0x0020 -+#define AR2315_INT_RX_ERR 0x0040 -+#define AR2315_INT_RX_EOF 0x0080 -+#define AR2315_INT_TX_TRUNC 0x0100 -+#define AR2315_INT_TX_STARVE 0x0200 -+#define AR2315_INT_LB_TIMEOUT 0x0400 -+#define AR2315_INT_LB_ERR 0x0800 -+#define AR2315_INT_MBOX_WR 0x1000 -+#define AR2315_INT_MBOX_RD 0x2000 -+ -+/* Bit definitions for INT MASK are the same as INT_STATUS */ -+#define AR2315_LB_INT_MASK (AR2315_LOCAL + 0x0504) -+ -+#define AR2315_LB_INT_EN (AR2315_LOCAL + 0x0508) -+#define AR2315_LB_MBOX (AR2315_LOCAL + 0x0600) -+ -+/* -+ * IR Interface Registers -+ */ -+#define AR2315_IR_PKTDATA (AR2315_IR + 0x0000) -+ -+#define AR2315_IR_PKTLEN (AR2315_IR + 0x07fc) /* 0 - 63 */ -+ -+#define AR2315_IR_CONTROL (AR2315_IR + 0x0800) -+#define AR2315_IRCTL_TX 0x00000000 /* use as tranmitter */ -+#define AR2315_IRCTL_RX 0x00000001 /* use as receiver */ -+#define AR2315_IRCTL_SAMPLECLK_MASK 0x00003ffe /* Sample clk divisor mask */ -+#define AR2315_IRCTL_SAMPLECLK_SHFT 1 -+#define AR2315_IRCTL_OUTPUTCLK_MASK 0x03ffc000 /* Output clk divisor mask */ -+#define AR2315_IRCTL_OUTPUTCLK_SHFT 14 -+ -+#define AR2315_IR_STATUS (AR2315_IR + 0x0804) -+#define AR2315_IRSTS_RX 0x00000001 /* receive in progress */ -+#define AR2315_IRSTS_TX 0x00000002 /* transmit in progress */ -+ -+#define AR2315_IR_CONFIG (AR2315_IR + 0x0808) -+#define AR2315_IRCFG_INVIN 0x00000001 /* invert input polarity */ -+#define AR2315_IRCFG_INVOUT 0x00000002 /* invert output polarity */ -+#define AR2315_IRCFG_SEQ_START_WIN_SEL 0x00000004 /* 1 => 28, 0 => 7 */ -+#define AR2315_IRCFG_SEQ_START_THRESH 0x000000f0 /* */ -+#define AR2315_IRCFG_SEQ_END_UNIT_SEL 0x00000100 /* */ -+#define AR2315_IRCFG_SEQ_END_UNIT_THRESH 0x00007e00 /* */ -+#define AR2315_IRCFG_SEQ_END_WIN_SEL 0x00008000 /* */ -+#define AR2315_IRCFG_SEQ_END_WIN_THRESH 0x001f0000 /* */ -+#define AR2315_IRCFG_NUM_BACKOFF_WORDS 0x01e00000 /* */ -+ -+#define HOST_PCI_DEV_ID 3 -+#define HOST_PCI_MBAR0 0x10000000 -+#define HOST_PCI_MBAR1 0x20000000 -+#define HOST_PCI_MBAR2 0x30000000 -+ -+#define HOST_PCI_SDRAM_BASEADDR HOST_PCI_MBAR1 -+#define PCI_DEVICE_MEM_SPACE 0x800000 -+ -+#endif /* __AR2315_REG_H */ -diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar2315_spiflash.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar2315_spiflash.h ---- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar2315_spiflash.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar2315_spiflash.h 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,116 @@ -+/* -+ * SPI Flash Memory support header file. -+ * -+ * Copyright (c) 2005, Atheros Communications Inc. -+ * Copyright (C) 2006 FON Technology, SL. -+ * Copyright (C) 2006 Imre Kaloz -+ * Copyright (C) 2006-2009 Felix Fietkau -+ * -+ * This code is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ */ -+#ifndef __AR2315_SPIFLASH_H -+#define __AR2315_SPIFLASH_H -+ -+#define STM_PAGE_SIZE 256 -+ -+#define SFI_WRITE_BUFFER_SIZE 4 -+#define SFI_FLASH_ADDR_MASK 0x00ffffff -+ -+#define STM_8MBIT_SIGNATURE 0x13 -+#define STM_M25P80_BYTE_COUNT 1048576 -+#define STM_M25P80_SECTOR_COUNT 16 -+#define STM_M25P80_SECTOR_SIZE 0x10000 -+ -+#define STM_16MBIT_SIGNATURE 0x14 -+#define STM_M25P16_BYTE_COUNT 2097152 -+#define STM_M25P16_SECTOR_COUNT 32 -+#define STM_M25P16_SECTOR_SIZE 0x10000 -+ -+#define STM_32MBIT_SIGNATURE 0x15 -+#define STM_M25P32_BYTE_COUNT 4194304 -+#define STM_M25P32_SECTOR_COUNT 64 -+#define STM_M25P32_SECTOR_SIZE 0x10000 -+ -+#define STM_64MBIT_SIGNATURE 0x16 -+#define STM_M25P64_BYTE_COUNT 8388608 -+#define STM_M25P64_SECTOR_COUNT 128 -+#define STM_M25P64_SECTOR_SIZE 0x10000 -+ -+#define STM_128MBIT_SIGNATURE 0x17 -+#define STM_M25P128_BYTE_COUNT 16777216 -+#define STM_M25P128_SECTOR_COUNT 256 -+#define STM_M25P128_SECTOR_SIZE 0x10000 -+ -+#define STM_1MB_BYTE_COUNT STM_M25P80_BYTE_COUNT -+#define STM_1MB_SECTOR_COUNT STM_M25P80_SECTOR_COUNT -+#define STM_1MB_SECTOR_SIZE STM_M25P80_SECTOR_SIZE -+#define STM_2MB_BYTE_COUNT STM_M25P16_BYTE_COUNT -+#define STM_2MB_SECTOR_COUNT STM_M25P16_SECTOR_COUNT -+#define STM_2MB_SECTOR_SIZE STM_M25P16_SECTOR_SIZE -+#define STM_4MB_BYTE_COUNT STM_M25P32_BYTE_COUNT -+#define STM_4MB_SECTOR_COUNT STM_M25P32_SECTOR_COUNT -+#define STM_4MB_SECTOR_SIZE STM_M25P32_SECTOR_SIZE -+#define STM_8MB_BYTE_COUNT STM_M25P64_BYTE_COUNT -+#define STM_8MB_SECTOR_COUNT STM_M25P64_SECTOR_COUNT -+#define STM_8MB_SECTOR_SIZE STM_M25P64_SECTOR_SIZE -+#define STM_16MB_BYTE_COUNT STM_M25P128_BYTE_COUNT -+#define STM_16MB_SECTOR_COUNT STM_M25P128_SECTOR_COUNT -+#define STM_16MB_SECTOR_SIZE STM_M25P128_SECTOR_SIZE -+ -+/* -+ * ST Microelectronics Opcodes for Serial Flash -+ */ -+ -+#define STM_OP_WR_ENABLE 0x06 /* Write Enable */ -+#define STM_OP_WR_DISABLE 0x04 /* Write Disable */ -+#define STM_OP_RD_STATUS 0x05 /* Read Status */ -+#define STM_OP_WR_STATUS 0x01 /* Write Status */ -+#define STM_OP_RD_DATA 0x03 /* Read Data */ -+#define STM_OP_FAST_RD_DATA 0x0b /* Fast Read Data */ -+#define STM_OP_PAGE_PGRM 0x02 /* Page Program */ -+#define STM_OP_SECTOR_ERASE 0xd8 /* Sector Erase */ -+#define STM_OP_BULK_ERASE 0xc7 /* Bulk Erase */ -+#define STM_OP_DEEP_PWRDOWN 0xb9 /* Deep Power-Down Mode */ -+#define STM_OP_RD_SIG 0xab /* Read Electronic Signature */ -+ -+#define STM_STATUS_WIP 0x01 /* Write-In-Progress */ -+#define STM_STATUS_WEL 0x02 /* Write Enable Latch */ -+#define STM_STATUS_BP0 0x04 /* Block Protect 0 */ -+#define STM_STATUS_BP1 0x08 /* Block Protect 1 */ -+#define STM_STATUS_BP2 0x10 /* Block Protect 2 */ -+#define STM_STATUS_SRWD 0x80 /* Status Register Write Disable */ -+ -+/* -+ * SPI Flash Interface Registers -+ */ -+#define AR531XPLUS_SPI_READ 0x08000000 -+#define AR531XPLUS_SPI_MMR 0x11300000 -+#define AR531XPLUS_SPI_MMR_SIZE 12 -+ -+#define AR531XPLUS_SPI_CTL 0x00 -+#define AR531XPLUS_SPI_OPCODE 0x04 -+#define AR531XPLUS_SPI_DATA 0x08 -+ -+#define SPI_FLASH_READ AR531XPLUS_SPI_READ -+#define SPI_FLASH_MMR AR531XPLUS_SPI_MMR -+#define SPI_FLASH_MMR_SIZE AR531XPLUS_SPI_MMR_SIZE -+#define SPI_FLASH_CTL AR531XPLUS_SPI_CTL -+#define SPI_FLASH_OPCODE AR531XPLUS_SPI_OPCODE -+#define SPI_FLASH_DATA AR531XPLUS_SPI_DATA -+ -+#define SPI_CTL_START 0x00000100 -+#define SPI_CTL_BUSY 0x00010000 -+#define SPI_CTL_TXCNT_MASK 0x0000000f -+#define SPI_CTL_RXCNT_MASK 0x000000f0 -+#define SPI_CTL_TX_RX_CNT_MASK 0x000000ff -+#define SPI_CTL_SIZE_MASK 0x00060000 -+ -+#define SPI_CTL_CLK_SEL_MASK 0x03000000 -+#define SPI_OPCODE_MASK 0x000000ff -+ -+#define SPI_STATUS_WIP STM_STATUS_WIP -+ -+#endif -diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar231x.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar231x.h ---- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar231x.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar231x.h 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,54 @@ -+#ifndef __AR531X_H -+#define __AR531X_H -+ -+#define AR531X_MISC_IRQ_BASE 0x20 -+#define AR531X_GPIO_IRQ_BASE 0x30 -+ -+/* Software's idea of interrupts handled by "CPU Interrupt Controller" */ -+#define AR531X_IRQ_NONE MIPS_CPU_IRQ_BASE+0 -+#define AR531X_IRQ_CPU_CLOCK MIPS_CPU_IRQ_BASE+7 /* C0_CAUSE: 0x8000 */ -+ -+/* Miscellaneous interrupts, which share IP6 */ -+#define AR531X_MISC_IRQ_NONE AR531X_MISC_IRQ_BASE+0 -+#define AR531X_MISC_IRQ_TIMER AR531X_MISC_IRQ_BASE+1 -+#define AR531X_MISC_IRQ_AHB_PROC AR531X_MISC_IRQ_BASE+2 -+#define AR531X_MISC_IRQ_AHB_DMA AR531X_MISC_IRQ_BASE+3 -+#define AR531X_MISC_IRQ_GPIO AR531X_MISC_IRQ_BASE+4 -+#define AR531X_MISC_IRQ_UART0 AR531X_MISC_IRQ_BASE+5 -+#define AR531X_MISC_IRQ_UART0_DMA AR531X_MISC_IRQ_BASE+6 -+#define AR531X_MISC_IRQ_WATCHDOG AR531X_MISC_IRQ_BASE+7 -+#define AR531X_MISC_IRQ_LOCAL AR531X_MISC_IRQ_BASE+8 -+#define AR531X_MISC_IRQ_SPI AR531X_MISC_IRQ_BASE+9 -+#define AR531X_MISC_IRQ_COUNT 10 -+ -+/* GPIO Interrupts [0..7], share AR531X_MISC_IRQ_GPIO */ -+#define AR531X_GPIO_IRQ_NONE AR531X_GPIO_IRQ_BASE+0 -+#define AR531X_GPIO_IRQ(n) AR531X_GPIO_IRQ_BASE+n -+#define AR531X_GPIO_IRQ_COUNT 22 -+ -+static inline u32 -+ar231x_read_reg(u32 reg) -+{ -+ return __raw_readl((u32 *) KSEG1ADDR(reg)); -+} -+ -+static inline void -+ar231x_write_reg(u32 reg, u32 val) -+{ -+ __raw_writel(val, (u32 *) KSEG1ADDR(reg)); -+} -+ -+static inline u32 -+ar231x_mask_reg(u32 reg, u32 mask, u32 val) -+{ -+ u32 ret; -+ -+ ret = ar231x_read_reg(reg); -+ ret &= ~mask; -+ ret |= val; -+ ar231x_write_reg(reg, ret); -+ -+ return ret; -+} -+ -+#endif -diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar231x_platform.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar231x_platform.h ---- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar231x_platform.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar231x_platform.h 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,83 @@ -+#ifndef __AR531X_PLATFORM_H -+#define __AR531X_PLATFORM_H -+ -+/* -+ * This is board-specific data that is stored in a "fixed" location in flash. -+ * It is shared across operating systems, so it should not be changed lightly. -+ * The main reason we need it is in order to extract the ethernet MAC -+ * address(es). -+ */ -+struct ar231x_boarddata { -+ u32 magic; /* board data is valid */ -+#define AR531X_BD_MAGIC 0x35333131 /* "5311", for all 531x platforms */ -+ u16 cksum; /* checksum (starting with BD_REV 2) */ -+ u16 rev; /* revision of this struct */ -+#define BD_REV 4 -+ char boardName[64]; /* Name of board */ -+ u16 major; /* Board major number */ -+ u16 minor; /* Board minor number */ -+ u32 flags; /* Board configuration */ -+#define BD_ENET0 0x00000001 /* ENET0 is stuffed */ -+#define BD_ENET1 0x00000002 /* ENET1 is stuffed */ -+#define BD_UART1 0x00000004 /* UART1 is stuffed */ -+#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */ -+#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */ -+#define BD_SYSLED 0x00000020 /* System LED stuffed */ -+#define BD_EXTUARTCLK 0x00000040 /* External UART clock */ -+#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */ -+#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */ -+#define BD_WLAN0 0x00000200 /* Enable WLAN0 */ -+#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ memCap for testing */ -+#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */ -+#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */ -+#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */ -+#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */ -+#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */ -+#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */ -+#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */ -+ u16 resetConfigGpio; /* Reset factory GPIO pin */ -+ u16 sysLedGpio; /* System LED GPIO pin */ -+ -+ u32 cpuFreq; /* CPU core frequency in Hz */ -+ u32 sysFreq; /* System frequency in Hz */ -+ u32 cntFreq; /* Calculated C0_COUNT frequency */ -+ -+ u8 wlan0_mac[6]; -+ u8 enet0_mac[6]; -+ u8 enet1_mac[6]; -+ -+ u16 pciId; /* Pseudo PCIID for common code */ -+ u16 memCap; /* cap bank1 in MB */ -+ -+ /* version 3 */ -+ u8 wlan1_mac[6]; /* (ar5212) */ -+}; -+ -+#define BOARD_CONFIG_BUFSZ 0x1000 -+ -+/* -+ * Platform device information for the Wireless MAC -+ */ -+struct ar231x_board_config { -+ u16 devid; -+ -+ /* board config data */ -+ struct ar231x_boarddata *config; -+ -+ /* radio calibration data */ -+ const char *radio; -+}; -+ -+/* -+ * Platform device information for the Ethernet MAC -+ */ -+struct ar231x_eth { -+ u32 reset_base; -+ u32 reset_mac; -+ u32 reset_phy; -+ u32 phy_base; -+ struct ar231x_board_config *config; -+ char *macaddr; -+}; -+ -+#endif /* __AR531X_PLATFORM_H */ -diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar5312_regs.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar5312_regs.h ---- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar5312_regs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar5312_regs.h 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,236 @@ -+/* -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. -+ * Copyright (C) 2006 Imre Kaloz -+ * Copyright (C) 2006 Felix Fietkau -+ */ -+ -+#ifndef AR5312_H -+#define AR5312_H -+ -+#include -+ -+/* -+ * IRQs -+ */ -+ -+#define AR5312_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */ -+#define AR5312_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */ -+#define AR5312_IRQ_ENET1_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */ -+#define AR5312_IRQ_WLAN1_INTRS MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */ -+#define AR5312_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */ -+ -+ -+/* Address Map */ -+#define AR531X_WLAN0 0x18000000 -+#define AR531X_WLAN1 0x18500000 -+#define AR531X_ENET0 0x18100000 -+#define AR531X_ENET1 0x18200000 -+#define AR531X_SDRAMCTL 0x18300000 -+#define AR531X_FLASHCTL 0x18400000 -+#define AR531X_APBBASE 0x1c000000 -+#define AR531X_FLASH 0x1e000000 -+#define AR531X_UART0 0xbc000003 /* UART MMR */ -+ -+/* -+ * AR531X_NUM_ENET_MAC defines the number of ethernet MACs that -+ * should be considered available. The AR5312 supports 2 enet MACS, -+ * even though many reference boards only actually use 1 of them -+ * (i.e. Only MAC 0 is actually connected to an enet PHY or PHY switch. -+ * The AR2312 supports 1 enet MAC. -+ */ -+#define AR531X_NUM_ENET_MAC 2 -+ -+/* -+ * Need these defines to determine true number of ethernet MACs -+ */ -+#define AR5212_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */ -+#define AR5212_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */ -+#define AR5212_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */ -+#define AR531X_RADIO_MASK_OFF 0xc8 -+#define AR531X_RADIO0_MASK 0x0003 -+#define AR531X_RADIO1_MASK 0x000c -+#define AR531X_RADIO1_S 2 -+ -+/* -+ * AR531X_NUM_WMAC defines the number of Wireless MACs that\ -+ * should be considered available. -+ */ -+#define AR531X_NUM_WMAC 2 -+ -+/* Reset/Timer Block Address Map */ -+#define AR531X_RESETTMR (AR531X_APBBASE + 0x3000) -+#define AR531X_TIMER (AR531X_RESETTMR + 0x0000) /* countdown timer */ -+#define AR531X_WD_CTRL (AR531X_RESETTMR + 0x0008) /* watchdog cntrl */ -+#define AR531X_WD_TIMER (AR531X_RESETTMR + 0x000c) /* watchdog timer */ -+#define AR531X_ISR (AR531X_RESETTMR + 0x0010) /* Intr Status Reg */ -+#define AR531X_IMR (AR531X_RESETTMR + 0x0014) /* Intr Mask Reg */ -+#define AR531X_RESET (AR531X_RESETTMR + 0x0020) -+#define AR5312_CLOCKCTL1 (AR531X_RESETTMR + 0x0064) -+#define AR5312_SCRATCH (AR531X_RESETTMR + 0x006c) -+#define AR531X_PROCADDR (AR531X_RESETTMR + 0x0070) -+#define AR531X_PROC1 (AR531X_RESETTMR + 0x0074) -+#define AR531X_DMAADDR (AR531X_RESETTMR + 0x0078) -+#define AR531X_DMA1 (AR531X_RESETTMR + 0x007c) -+#define AR531X_ENABLE (AR531X_RESETTMR + 0x0080) /* interface enb */ -+#define AR531X_REV (AR531X_RESETTMR + 0x0090) /* revision */ -+ -+/* AR531X_WD_CTRL register bit field definitions */ -+#define AR531X_WD_CTRL_IGNORE_EXPIRATION 0x0000 -+#define AR531X_WD_CTRL_NMI 0x0001 -+#define AR531X_WD_CTRL_RESET 0x0002 -+ -+/* AR531X_ISR register bit field definitions */ -+#define AR531X_ISR_NONE 0x0000 -+#define AR531X_ISR_TIMER 0x0001 -+#define AR531X_ISR_AHBPROC 0x0002 -+#define AR531X_ISR_AHBDMA 0x0004 -+#define AR531X_ISR_GPIO 0x0008 -+#define AR531X_ISR_UART0 0x0010 -+#define AR531X_ISR_UART0DMA 0x0020 -+#define AR531X_ISR_WD 0x0040 -+#define AR531X_ISR_LOCAL 0x0080 -+ -+/* AR531X_RESET register bit field definitions */ -+#define AR531X_RESET_SYSTEM 0x00000001 /* cold reset full system */ -+#define AR531X_RESET_PROC 0x00000002 /* cold reset MIPS core */ -+#define AR531X_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */ -+#define AR531X_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */ -+#define AR531X_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */ -+#define AR531X_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */ -+#define AR531X_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */ -+#define AR531X_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */ -+#define AR531X_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */ -+#define AR531X_RESET_APB 0x00000400 /* cold reset APB (ar5312) */ -+#define AR531X_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */ -+#define AR531X_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */ -+#define AR531X_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */ -+#define AR531X_RESET_NMI 0x00010000 /* send an NMI to the processor */ -+#define AR531X_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */ -+#define AR531X_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */ -+#define AR531X_RESET_LOCAL_BUS 0x00080000 /* reset local bus */ -+#define AR531X_RESET_WDOG 0x00100000 /* last reset was a watchdog */ -+ -+#define AR531X_RESET_WMAC0_BITS \ -+ AR531X_RESET_WLAN0 |\ -+ AR531X_RESET_WARM_WLAN0_MAC |\ -+ AR531X_RESET_WARM_WLAN0_BB -+ -+#define AR531X_RESERT_WMAC1_BITS \ -+ AR531X_RESET_WLAN1 |\ -+ AR531X_RESET_WARM_WLAN1_MAC |\ -+ AR531X_RESET_WARM_WLAN1_BB -+ -+/* AR5312_CLOCKCTL1 register bit field definitions */ -+#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030 -+#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4 -+#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00 -+#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8 -+#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000 -+ -+/* Valid for AR5312 and AR2312 */ -+#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030 -+#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4 -+#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00 -+#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8 -+#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000 -+ -+/* Valid for AR2313 */ -+#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000 -+#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12 -+#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000 -+#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16 -+#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000 -+ -+ -+/* AR531X_ENABLE register bit field definitions */ -+#define AR531X_ENABLE_WLAN0 0x0001 -+#define AR531X_ENABLE_ENET0 0x0002 -+#define AR531X_ENABLE_ENET1 0x0004 -+#define AR531X_ENABLE_UART_AND_WLAN1_PIO 0x0008 /* UART, and WLAN1 PIOs */ -+#define AR531X_ENABLE_WLAN1_DMA 0x0010 /* WLAN1 DMAs */ -+#define AR531X_ENABLE_WLAN1 \ -+ (AR531X_ENABLE_UART_AND_WLAN1_PIO | AR531X_ENABLE_WLAN1_DMA) -+ -+/* AR531X_REV register bit field definitions */ -+#define AR531X_REV_WMAC_MAJ 0xf000 -+#define AR531X_REV_WMAC_MAJ_S 12 -+#define AR531X_REV_WMAC_MIN 0x0f00 -+#define AR531X_REV_WMAC_MIN_S 8 -+#define AR531X_REV_MAJ 0x00f0 -+#define AR531X_REV_MAJ_S 4 -+#define AR531X_REV_MIN 0x000f -+#define AR531X_REV_MIN_S 0 -+#define AR531X_REV_CHIP (AR531X_REV_MAJ|AR531X_REV_MIN) -+ -+/* Major revision numbers, bits 7..4 of Revision ID register */ -+#define AR531X_REV_MAJ_AR5312 0x4 -+#define AR531X_REV_MAJ_AR2313 0x5 -+ -+/* Minor revision numbers, bits 3..0 of Revision ID register */ -+#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */ -+#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */ -+ -+/* AR531X_FLASHCTL register bit field definitions */ -+#define FLASHCTL_IDCY 0x0000000f /* Idle cycle turn around time */ -+#define FLASHCTL_IDCY_S 0 -+#define FLASHCTL_WST1 0x000003e0 /* Wait state 1 */ -+#define FLASHCTL_WST1_S 5 -+#define FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */ -+#define FLASHCTL_WST2 0x0000f800 /* Wait state 2 */ -+#define FLASHCTL_WST2_S 11 -+#define FLASHCTL_AC 0x00070000 /* Flash address check (added) */ -+#define FLASHCTL_AC_S 16 -+#define FLASHCTL_AC_128K 0x00000000 -+#define FLASHCTL_AC_256K 0x00010000 -+#define FLASHCTL_AC_512K 0x00020000 -+#define FLASHCTL_AC_1M 0x00030000 -+#define FLASHCTL_AC_2M 0x00040000 -+#define FLASHCTL_AC_4M 0x00050000 -+#define FLASHCTL_AC_8M 0x00060000 -+#define FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */ -+#define FLASHCTL_E 0x00080000 /* Flash bank enable (added) */ -+#define FLASHCTL_BUSERR 0x01000000 /* Bus transfer error status flag */ -+#define FLASHCTL_WPERR 0x02000000 /* Write protect error status flag */ -+#define FLASHCTL_WP 0x04000000 /* Write protect */ -+#define FLASHCTL_BM 0x08000000 /* Burst mode */ -+#define FLASHCTL_MW 0x30000000 /* Memory width */ -+#define FLASHCTL_MWx8 0x00000000 /* Memory width x8 */ -+#define FLASHCTL_MWx16 0x10000000 /* Memory width x16 */ -+#define FLASHCTL_MWx32 0x20000000 /* Memory width x32 (not supported) */ -+#define FLASHCTL_ATNR 0x00000000 /* Access type == no retry */ -+#define FLASHCTL_ATR 0x80000000 /* Access type == retry every */ -+#define FLASHCTL_ATR4 0xc0000000 /* Access type == retry every 4 */ -+ -+/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */ -+#define AR531X_FLASHCTL0 (AR531X_FLASHCTL + 0x00) -+#define AR531X_FLASHCTL1 (AR531X_FLASHCTL + 0x04) -+#define AR531X_FLASHCTL2 (AR531X_FLASHCTL + 0x08) -+ -+/* ARM SDRAM Controller -- just enough to determine memory size */ -+#define AR531X_MEM_CFG1 (AR531X_SDRAMCTL + 0x04) -+#define MEM_CFG1_AC0 0x00000700 /* bank 0: SDRAM addr check (added) */ -+#define MEM_CFG1_AC0_S 8 -+#define MEM_CFG1_AC1 0x00007000 /* bank 1: SDRAM addr check (added) */ -+#define MEM_CFG1_AC1_S 12 -+ -+/* GPIO Address Map */ -+#define AR531X_GPIO (AR531X_APBBASE + 0x2000) -+#define AR531X_GPIO_DO (AR531X_GPIO + 0x00) /* output register */ -+#define AR531X_GPIO_DI (AR531X_GPIO + 0x04) /* intput register */ -+#define AR531X_GPIO_CR (AR531X_GPIO + 0x08) /* control register */ -+ -+/* GPIO Control Register bit field definitions */ -+#define AR531X_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */ -+#define AR531X_GPIO_CR_O(x) (0 << (x)) /* mask for output */ -+#define AR531X_GPIO_CR_I(x) (1 << (x)) /* mask for input */ -+#define AR531X_GPIO_CR_INT(x) (1 << ((x)+8)) /* mask for interrupt */ -+#define AR531X_GPIO_CR_UART(x) (1 << ((x)+16)) /* uart multiplex */ -+#define AR531X_NUM_GPIO 8 -+ -+ -+#endif -+ -diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h ---- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,84 @@ -+/* -+ * Atheros SoC specific CPU feature overrides -+ * -+ * Copyright (C) 2008 Gabor Juhos -+ * -+ * This file was derived from: include/asm-mips/cpu-features.h -+ * Copyright (C) 2003, 2004 Ralf Baechle -+ * Copyright (C) 2004 Maciej W. Rozycki -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ */ -+#ifndef __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H -+#define __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H -+ -+/* -+ * The ATHEROS SoCs have MIPS 4Kc/4KEc core. -+ */ -+#define cpu_has_tlb 1 -+#define cpu_has_4kex 1 -+#define cpu_has_3k_cache 0 -+#define cpu_has_4k_cache 1 -+#define cpu_has_tx39_cache 0 -+#define cpu_has_sb1_cache 0 -+#define cpu_has_fpu 0 -+#define cpu_has_32fpr 0 -+#define cpu_has_counter 1 -+/* #define cpu_has_watch ? */ -+/* #define cpu_has_divec ? */ -+/* #define cpu_has_vce ? */ -+/* #define cpu_has_cache_cdex_p ? */ -+/* #define cpu_has_cache_cdex_s ? */ -+/* #define cpu_has_prefetch ? */ -+/* #define cpu_has_mcheck ? */ -+#define cpu_has_ejtag 1 -+ -+#if !defined(CONFIG_ATHEROS_AR5312) -+# define cpu_has_llsc 1 -+#else -+/* -+ * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the -+ * ll/sc instructions. -+ */ -+# define cpu_has_llsc 0 -+#endif -+ -+#define cpu_has_mips16 0 -+#define cpu_has_mdmx 0 -+#define cpu_has_mips3d 0 -+#define cpu_has_smartmips 0 -+ -+/* #define cpu_has_vtag_icache ? */ -+/* #define cpu_has_dc_aliases ? */ -+/* #define cpu_has_ic_fills_f_dc ? */ -+/* #define cpu_has_pindexed_dcache ? */ -+ -+/* #define cpu_icache_snoops_remote_store ? */ -+ -+#define cpu_has_mips32r1 1 -+ -+#if !defined(CONFIG_ATHEROS_AR5312) -+# define cpu_has_mips32r2 1 -+#endif -+ -+#define cpu_has_mips64r1 0 -+#define cpu_has_mips64r2 0 -+ -+#define cpu_has_dsp 0 -+#define cpu_has_mipsmt 0 -+ -+/* #define cpu_has_nofpuex ? */ -+#define cpu_has_64bits 0 -+#define cpu_has_64bit_zero_reg 0 -+#define cpu_has_64bit_gp_regs 0 -+#define cpu_has_64bit_addresses 0 -+ -+/* #define cpu_has_inclusive_pcaches ? */ -+ -+/* #define cpu_dcache_line_size() ? */ -+/* #define cpu_icache_line_size() ? */ -+ -+#endif /* __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H */ -diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/dma-coherence.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/dma-coherence.h ---- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/dma-coherence.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/dma-coherence.h 2011-05-15 21:41:19.000000000 +0200 -@@ -0,0 +1,76 @@ -+/* -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 2006 Ralf Baechle -+ * Copyright (C) 2007 Felix Fietkau -+ * -+ */ -+#ifndef __ASM_MACH_GENERIC_DMA_COHERENCE_H -+#define __ASM_MACH_GENERIC_DMA_COHERENCE_H -+ -+#define PCI_DMA_OFFSET 0x20000000 -+ -+#include -+ -+static inline dma_addr_t ar231x_dev_offset(struct device *dev) -+{ -+#ifdef CONFIG_PCI -+ extern struct bus_type pci_bus_type; -+ -+ if (dev && dev->bus == &pci_bus_type) -+ return PCI_DMA_OFFSET; -+ else -+#endif -+ return 0; -+} -+ -+static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size) -+{ -+ return virt_to_phys(addr) + ar231x_dev_offset(dev); -+} -+ -+static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page) -+{ -+ return page_to_phys(page) + ar231x_dev_offset(dev); -+} -+ -+static inline unsigned long plat_dma_addr_to_phys(struct device *dev, -+ dma_addr_t dma_addr) -+{ -+ return dma_addr - ar231x_dev_offset(dev); -+} -+ -+static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, -+ size_t size, enum dma_data_direction direction) -+{ -+} -+ -+static inline int plat_dma_supported(struct device *dev, u64 mask) -+{ -+ return 1; -+} -+ -+static inline void plat_extra_sync_for_device(struct device *dev) -+{ -+ return; -+} -+ -+static inline int plat_dma_mapping_error(struct device *dev, -+ dma_addr_t dma_addr) -+{ -+ return 0; -+} -+ -+static inline int plat_device_is_coherent(struct device *dev) -+{ -+#ifdef CONFIG_DMA_COHERENT -+ return 1; -+#endif -+#ifdef CONFIG_DMA_NONCOHERENT -+ return 0; -+#endif -+} -+ -+#endif /* __ASM_MACH_GENERIC_DMA_COHERENCE_H */ -diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/gpio.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/gpio.h ---- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/gpio.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/gpio.h 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,84 @@ -+#ifndef _ATHEROS_GPIO_H_ -+#define _ATHEROS_GPIO_H_ -+ -+#include -+ -+struct ar231x_gpiodev { -+ u32 valid_mask; -+ u32 (*get_output)(void); -+ u32 (*set_output)(u32 mask, u32 val); -+ u32 (*get)(void); -+ u32 (*set)(u32 mask, u32 val); -+}; -+ -+extern const struct ar231x_gpiodev *ar231x_gpiodev; -+ -+/* -+ * Wrappers for the generic GPIO layer -+ */ -+ -+static inline int gpio_direction_input(unsigned gpio) { -+ u32 mask = 1 << gpio; -+ -+ if (!(ar231x_gpiodev->valid_mask & mask)) -+ return -ENXIO; -+ -+ ar231x_gpiodev->set_output(mask, 0); -+ return 0; -+} -+ -+static inline void gpio_set_value(unsigned gpio, int value) { -+ u32 mask = 1 << gpio; -+ -+ if (!(ar231x_gpiodev->valid_mask & mask)) -+ return; -+ -+ ar231x_gpiodev->set(mask, (!!value) * mask); -+} -+ -+static inline int gpio_direction_output(unsigned gpio, int value) { -+ u32 mask = 1 << gpio; -+ -+ if (!(ar231x_gpiodev->valid_mask & mask)) -+ return -ENXIO; -+ -+ ar231x_gpiodev->set_output(mask, mask); -+ ar231x_gpiodev->set(mask, (!!value) * mask); -+ return 0; -+} -+ -+/* Reads the gpio pin. Unchecked function */ -+static inline int gpio_get_value(unsigned gpio) { -+ u32 mask = 1 << gpio; -+ -+ if (!(ar231x_gpiodev->valid_mask & mask)) -+ return 0; -+ -+ return !!(ar231x_gpiodev->get() & mask); -+} -+ -+static inline int gpio_request(unsigned gpio, const char *label) { -+ return 0; -+} -+ -+static inline void gpio_free(unsigned gpio) { -+} -+ -+/* Returns IRQ to attach for gpio. Unchecked function */ -+static inline int gpio_to_irq(unsigned gpio) { -+ return AR531X_GPIO_IRQ(gpio); -+} -+ -+/* Returns gpio for IRQ attached. Unchecked function */ -+static inline int irq_to_gpio(unsigned irq) { -+ return (irq - (AR531X_GPIO_IRQ(0))); -+} -+ -+static inline int gpio_set_debounce(unsigned gpio, unsigned debounce) -+{ -+ return -ENOSYS; -+} -+ -+#include /* cansleep wrappers */ -+ -+#endif -diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/reset.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/reset.h ---- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/reset.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/reset.h 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,6 @@ -+#ifndef __AR531X_RESET_H -+#define __AR531X_RESET_H -+ -+void ar531x_disable_reset_button(void); -+ -+#endif /* __AR531X_RESET_H */ -diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/war.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/war.h ---- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/war.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/war.h 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,25 @@ -+/* -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 2008 Felix Fietkau -+ */ -+#ifndef __ASM_MIPS_MACH_ATHEROS_WAR_H -+#define __ASM_MIPS_MACH_ATHEROS_WAR_H -+ -+#define R4600_V1_INDEX_ICACHEOP_WAR 0 -+#define R4600_V1_HIT_CACHEOP_WAR 0 -+#define R4600_V2_HIT_CACHEOP_WAR 0 -+#define R5432_CP0_INTERRUPT_WAR 0 -+#define BCM1250_M3_WAR 0 -+#define SIBYTE_1956_WAR 0 -+#define MIPS4K_ICACHE_REFILL_WAR 0 -+#define MIPS_CACHE_SYNC_WAR 0 -+#define TX49XX_ICACHE_INDEX_INV_WAR 0 -+#define RM9000_CDEX_SMP_WAR 0 -+#define ICACHE_REFILLS_WORKAROUND_WAR 0 -+#define R10000_LLSC_WAR 0 -+#define MIPS34K_MISSED_ITLB_WAR 0 -+ -+#endif /* __ASM_MIPS_MACH_ATHEROS_WAR_H */ -diff -Nur linux-2.6.39-rc7.orig/arch/mips/kernel/cevt-r4k.c linux-2.6.39-rc7/arch/mips/kernel/cevt-r4k.c ---- linux-2.6.39-rc7.orig/arch/mips/kernel/cevt-r4k.c 2011-05-10 04:33:54.000000000 +0200 -+++ linux-2.6.39-rc7/arch/mips/kernel/cevt-r4k.c 2011-05-15 21:34:57.000000000 +0200 -@@ -168,20 +168,23 @@ - struct clock_event_device *cd; - unsigned int irq; - -- if (!cpu_has_counter || !mips_hpt_frequency) -- return -ENXIO; -- -- if (!c0_compare_int_usable()) -- return -ENXIO; -- - /* - * With vectored interrupts things are getting platform specific. - * get_c0_compare_int is a hook to allow a platform to return the - * interrupt number of it's liking. - */ - irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; -- if (get_c0_compare_int) -+ if (get_c0_compare_int) { - irq = get_c0_compare_int(); -+ if ((irq >= MIPS_CPU_IRQ_BASE) && (irq < MIPS_CPU_IRQ_BASE + 8)) -+ cp0_compare_irq = irq - MIPS_CPU_IRQ_BASE; -+ } -+ -+ if (!cpu_has_counter || !mips_hpt_frequency) -+ return -ENXIO; -+ -+ if (!c0_compare_int_usable()) -+ return -ENXIO; - - cd = &per_cpu(mips_clockevent_device, cpu); - -diff -Nur linux-2.6.39-rc7.orig/drivers/mtd/devices/Kconfig linux-2.6.39-rc7/drivers/mtd/devices/Kconfig ---- linux-2.6.39-rc7.orig/drivers/mtd/devices/Kconfig 2011-05-10 04:33:54.000000000 +0200 -+++ linux-2.6.39-rc7/drivers/mtd/devices/Kconfig 2011-05-15 21:34:57.000000000 +0200 -@@ -112,6 +112,10 @@ - Set up your spi devices with the right board-specific platform data, - if you want to specify device partitioning. - -+config MTD_AR2315 -+ tristate "Atheros AR2315+ SPI Flash support" -+ depends on ATHEROS_AR2315 -+ - config MTD_SLRAM - tristate "Uncached system RAM" - help -diff -Nur linux-2.6.39-rc7.orig/drivers/mtd/devices/Makefile linux-2.6.39-rc7/drivers/mtd/devices/Makefile ---- linux-2.6.39-rc7.orig/drivers/mtd/devices/Makefile 2011-05-10 04:33:54.000000000 +0200 -+++ linux-2.6.39-rc7/drivers/mtd/devices/Makefile 2011-05-15 21:34:57.000000000 +0200 -@@ -17,3 +17,4 @@ - obj-$(CONFIG_MTD_DATAFLASH) += mtd_dataflash.o - obj-$(CONFIG_MTD_M25P80) += m25p80.o - obj-$(CONFIG_MTD_SST25L) += sst25l.o -+obj-$(CONFIG_MTD_AR2315) += ar2315.o -diff -Nur linux-2.6.39-rc7.orig/drivers/mtd/devices/ar2315.c linux-2.6.39-rc7/drivers/mtd/devices/ar2315.c ---- linux-2.6.39-rc7.orig/drivers/mtd/devices/ar2315.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/drivers/mtd/devices/ar2315.c 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,517 @@ -+ -+/* -+ * MTD driver for the SPI Flash Memory support on Atheros AR2315 -+ * -+ * Copyright (c) 2005-2006 Atheros Communications Inc. -+ * Copyright (C) 2006-2007 FON Technology, SL. -+ * Copyright (C) 2006-2007 Imre Kaloz -+ * Copyright (C) 2006-2009 Felix Fietkau -+ * -+ * This code is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+ -+#define SPIFLASH "spiflash: " -+#define busy_wait(_priv, _condition, _wait) do { \ -+ while (_condition) { \ -+ spin_unlock_bh(&_priv->lock); \ -+ if (_wait > 1) \ -+ msleep(_wait); \ -+ else if ((_wait == 1) && need_resched()) \ -+ schedule(); \ -+ else \ -+ udelay(1); \ -+ spin_lock_bh(&_priv->lock); \ -+ } \ -+} while (0) -+ -+enum { -+ FLASH_NONE, -+ FLASH_1MB, -+ FLASH_2MB, -+ FLASH_4MB, -+ FLASH_8MB, -+ FLASH_16MB, -+}; -+ -+/* Flash configuration table */ -+struct flashconfig { -+ u32 byte_cnt; -+ u32 sector_cnt; -+ u32 sector_size; -+}; -+ -+const struct flashconfig flashconfig_tbl[] = { -+ [FLASH_NONE] = { 0, 0, 0}, -+ [FLASH_1MB] = { STM_1MB_BYTE_COUNT, STM_1MB_SECTOR_COUNT, STM_1MB_SECTOR_SIZE}, -+ [FLASH_2MB] = { STM_2MB_BYTE_COUNT, STM_2MB_SECTOR_COUNT, STM_2MB_SECTOR_SIZE}, -+ [FLASH_4MB] = { STM_4MB_BYTE_COUNT, STM_4MB_SECTOR_COUNT, STM_4MB_SECTOR_SIZE}, -+ [FLASH_8MB] = { STM_8MB_BYTE_COUNT, STM_8MB_SECTOR_COUNT, STM_8MB_SECTOR_SIZE}, -+ [FLASH_16MB] = { STM_16MB_BYTE_COUNT, STM_16MB_SECTOR_COUNT, STM_16MB_SECTOR_SIZE} -+}; -+ -+/* Mapping of generic opcodes to STM serial flash opcodes */ -+enum { -+ SPI_WRITE_ENABLE, -+ SPI_WRITE_DISABLE, -+ SPI_RD_STATUS, -+ SPI_WR_STATUS, -+ SPI_RD_DATA, -+ SPI_FAST_RD_DATA, -+ SPI_PAGE_PROGRAM, -+ SPI_SECTOR_ERASE, -+ SPI_BULK_ERASE, -+ SPI_DEEP_PWRDOWN, -+ SPI_RD_SIG, -+}; -+ -+struct opcodes { -+ __u16 code; -+ __s8 tx_cnt; -+ __s8 rx_cnt; -+}; -+const struct opcodes stm_opcodes[] = { -+ [SPI_WRITE_ENABLE] = {STM_OP_WR_ENABLE, 1, 0}, -+ [SPI_WRITE_DISABLE] = {STM_OP_WR_DISABLE, 1, 0}, -+ [SPI_RD_STATUS] = {STM_OP_RD_STATUS, 1, 1}, -+ [SPI_WR_STATUS] = {STM_OP_WR_STATUS, 1, 0}, -+ [SPI_RD_DATA] = {STM_OP_RD_DATA, 4, 4}, -+ [SPI_FAST_RD_DATA] = {STM_OP_FAST_RD_DATA, 5, 0}, -+ [SPI_PAGE_PROGRAM] = {STM_OP_PAGE_PGRM, 8, 0}, -+ [SPI_SECTOR_ERASE] = {STM_OP_SECTOR_ERASE, 4, 0}, -+ [SPI_BULK_ERASE] = {STM_OP_BULK_ERASE, 1, 0}, -+ [SPI_DEEP_PWRDOWN] = {STM_OP_DEEP_PWRDOWN, 1, 0}, -+ [SPI_RD_SIG] = {STM_OP_RD_SIG, 4, 1}, -+}; -+ -+/* Driver private data structure */ -+struct spiflash_priv { -+ struct mtd_info mtd; -+ void *readaddr; /* memory mapped data for read */ -+ void *mmraddr; /* memory mapped register space */ -+ wait_queue_head_t wq; -+ spinlock_t lock; -+ int state; -+}; -+ -+#define to_spiflash(_mtd) container_of(_mtd, struct spiflash_priv, mtd) -+ -+enum { -+ FL_READY, -+ FL_READING, -+ FL_ERASING, -+ FL_WRITING -+}; -+ -+/***************************************************************************************************/ -+ -+static u32 -+spiflash_read_reg(struct spiflash_priv *priv, int reg) -+{ -+ return ar231x_read_reg((u32) priv->mmraddr + reg); -+} -+ -+static void -+spiflash_write_reg(struct spiflash_priv *priv, int reg, u32 data) -+{ -+ ar231x_write_reg((u32) priv->mmraddr + reg, data); -+} -+ -+static u32 -+spiflash_wait_busy(struct spiflash_priv *priv) -+{ -+ u32 reg; -+ -+ busy_wait(priv, (reg = spiflash_read_reg(priv, SPI_FLASH_CTL)) & -+ SPI_CTL_BUSY, 0); -+ return reg; -+} -+ -+static u32 -+spiflash_sendcmd (struct spiflash_priv *priv, int opcode, u32 addr) -+{ -+ const struct opcodes *op; -+ u32 reg, mask; -+ -+ op = &stm_opcodes[opcode]; -+ reg = spiflash_wait_busy(priv); -+ spiflash_write_reg(priv, SPI_FLASH_OPCODE, -+ ((u32) op->code) | (addr << 8)); -+ -+ reg &= ~SPI_CTL_TX_RX_CNT_MASK; -+ reg |= SPI_CTL_START | op->tx_cnt | (op->rx_cnt << 4); -+ -+ spiflash_write_reg(priv, SPI_FLASH_CTL, reg); -+ spiflash_wait_busy(priv); -+ -+ if (!op->rx_cnt) -+ return 0; -+ -+ reg = spiflash_read_reg(priv, SPI_FLASH_DATA); -+ -+ switch (op->rx_cnt) { -+ case 1: -+ mask = 0x000000ff; -+ break; -+ case 2: -+ mask = 0x0000ffff; -+ break; -+ case 3: -+ mask = 0x00ffffff; -+ break; -+ default: -+ mask = 0xffffffff; -+ break; -+ } -+ reg &= mask; -+ -+ return reg; -+} -+ -+ -+/* -+ * Probe SPI flash device -+ * Function returns 0 for failure. -+ * and flashconfig_tbl array index for success. -+ */ -+static int -+spiflash_probe_chip (struct spiflash_priv *priv) -+{ -+ u32 sig; -+ int flash_size; -+ -+ /* Read the signature on the flash device */ -+ spin_lock_bh(&priv->lock); -+ sig = spiflash_sendcmd(priv, SPI_RD_SIG, 0); -+ spin_unlock_bh(&priv->lock); -+ -+ switch (sig) { -+ case STM_8MBIT_SIGNATURE: -+ flash_size = FLASH_1MB; -+ break; -+ case STM_16MBIT_SIGNATURE: -+ flash_size = FLASH_2MB; -+ break; -+ case STM_32MBIT_SIGNATURE: -+ flash_size = FLASH_4MB; -+ break; -+ case STM_64MBIT_SIGNATURE: -+ flash_size = FLASH_8MB; -+ break; -+ case STM_128MBIT_SIGNATURE: -+ flash_size = FLASH_16MB; -+ break; -+ default: -+ printk (KERN_WARNING SPIFLASH "Read of flash device signature failed!\n"); -+ return 0; -+ } -+ -+ return flash_size; -+} -+ -+ -+/* wait until the flash chip is ready and grab a lock */ -+static int spiflash_wait_ready(struct spiflash_priv *priv, int state) -+{ -+ DECLARE_WAITQUEUE(wait, current); -+ -+retry: -+ spin_lock_bh(&priv->lock); -+ if (priv->state != FL_READY) { -+ set_current_state(TASK_UNINTERRUPTIBLE); -+ add_wait_queue(&priv->wq, &wait); -+ spin_unlock_bh(&priv->lock); -+ schedule(); -+ remove_wait_queue(&priv->wq, &wait); -+ -+ if(signal_pending(current)) -+ return 0; -+ -+ goto retry; -+ } -+ priv->state = state; -+ -+ return 1; -+} -+ -+static inline void spiflash_done(struct spiflash_priv *priv) -+{ -+ priv->state = FL_READY; -+ spin_unlock_bh(&priv->lock); -+ wake_up(&priv->wq); -+} -+ -+static void -+spiflash_wait_complete(struct spiflash_priv *priv, unsigned int timeout) -+{ -+ busy_wait(priv, spiflash_sendcmd(priv, SPI_RD_STATUS, 0) & -+ SPI_STATUS_WIP, timeout); -+ spiflash_done(priv); -+} -+ -+ -+ -+static int -+spiflash_erase (struct mtd_info *mtd, struct erase_info *instr) -+{ -+ struct spiflash_priv *priv = to_spiflash(mtd); -+ const struct opcodes *op; -+ u32 temp, reg; -+ -+ if (instr->addr + instr->len > mtd->size) -+ return -EINVAL; -+ -+ if (!spiflash_wait_ready(priv, FL_ERASING)) -+ return -EINTR; -+ -+ spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0); -+ reg = spiflash_wait_busy(priv); -+ -+ op = &stm_opcodes[SPI_SECTOR_ERASE]; -+ temp = ((u32)instr->addr << 8) | (u32)(op->code); -+ spiflash_write_reg(priv, SPI_FLASH_OPCODE, temp); -+ -+ reg &= ~SPI_CTL_TX_RX_CNT_MASK; -+ reg |= op->tx_cnt | SPI_CTL_START; -+ spiflash_write_reg(priv, SPI_FLASH_CTL, reg); -+ -+ spiflash_wait_complete(priv, 20); -+ -+ instr->state = MTD_ERASE_DONE; -+ mtd_erase_callback(instr); -+ -+ return 0; -+} -+ -+static int -+spiflash_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf) -+{ -+ struct spiflash_priv *priv = to_spiflash(mtd); -+ u8 *read_addr; -+ -+ if (!len) -+ return 0; -+ -+ if (from + len > mtd->size) -+ return -EINVAL; -+ -+ *retlen = len; -+ -+ if (!spiflash_wait_ready(priv, FL_READING)) -+ return -EINTR; -+ -+ read_addr = (u8 *)(priv->readaddr + from); -+ memcpy_fromio(buf, read_addr, len); -+ spiflash_done(priv); -+ -+ return 0; -+} -+ -+static int -+spiflash_write (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u8 *buf) -+{ -+ struct spiflash_priv *priv = to_spiflash(mtd); -+ u32 opcode, bytes_left; -+ -+ *retlen = 0; -+ -+ if (!len) -+ return 0; -+ -+ if (to + len > mtd->size) -+ return -EINVAL; -+ -+ bytes_left = len; -+ -+ do { -+ u32 read_len, reg, page_offset, spi_data = 0; -+ -+ read_len = min(bytes_left, sizeof(u32)); -+ -+ /* 32-bit writes cannot span across a page boundary -+ * (256 bytes). This types of writes require two page -+ * program operations to handle it correctly. The STM part -+ * will write the overflow data to the beginning of the -+ * current page as opposed to the subsequent page. -+ */ -+ page_offset = (to & (STM_PAGE_SIZE - 1)) + read_len; -+ -+ if (page_offset > STM_PAGE_SIZE) -+ read_len -= (page_offset - STM_PAGE_SIZE); -+ -+ if (!spiflash_wait_ready(priv, FL_WRITING)) -+ return -EINTR; -+ -+ spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0); -+ spi_data = 0; -+ switch (read_len) { -+ case 4: -+ spi_data |= buf[3] << 24; -+ /* fall through */ -+ case 3: -+ spi_data |= buf[2] << 16; -+ /* fall through */ -+ case 2: -+ spi_data |= buf[1] << 8; -+ /* fall through */ -+ case 1: -+ spi_data |= buf[0] & 0xff; -+ break; -+ default: -+ break; -+ } -+ -+ spiflash_write_reg(priv, SPI_FLASH_DATA, spi_data); -+ opcode = stm_opcodes[SPI_PAGE_PROGRAM].code | -+ (to & 0x00ffffff) << 8; -+ spiflash_write_reg(priv, SPI_FLASH_OPCODE, opcode); -+ -+ reg = spiflash_read_reg(priv, SPI_FLASH_CTL); -+ reg &= ~SPI_CTL_TX_RX_CNT_MASK; -+ reg |= (read_len + 4) | SPI_CTL_START; -+ spiflash_write_reg(priv, SPI_FLASH_CTL, reg); -+ -+ spiflash_wait_complete(priv, 1); -+ -+ bytes_left -= read_len; -+ to += read_len; -+ buf += read_len; -+ -+ *retlen += read_len; -+ } while (bytes_left != 0); -+ -+ return 0; -+} -+ -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static const char *part_probe_types[] = { "cmdlinepart", "RedBoot", "MyLoader", NULL }; -+#endif -+ -+ -+static int -+spiflash_probe(struct platform_device *pdev) -+{ -+ struct spiflash_priv *priv; -+ struct mtd_partition *parts; -+ struct mtd_info *mtd; -+ int index, num_parts; -+ int result = 0; -+ -+ priv = kzalloc(sizeof(struct spiflash_priv), GFP_KERNEL); -+ spin_lock_init(&priv->lock); -+ init_waitqueue_head(&priv->wq); -+ priv->state = FL_READY; -+ mtd = &priv->mtd; -+ -+ priv->mmraddr = ioremap_nocache(SPI_FLASH_MMR, SPI_FLASH_MMR_SIZE); -+ if (!priv->mmraddr) { -+ printk(KERN_WARNING SPIFLASH "Failed to map flash device\n"); -+ goto error; -+ } -+ -+ index = spiflash_probe_chip(priv); -+ if (!index) { -+ printk (KERN_WARNING SPIFLASH "Found no serial flash device\n"); -+ goto error; -+ } -+ -+ priv->readaddr = ioremap_nocache(SPI_FLASH_READ, flashconfig_tbl[index].byte_cnt); -+ if (!priv->readaddr) { -+ printk (KERN_WARNING SPIFLASH "Failed to map flash device\n"); -+ goto error; -+ } -+ -+ platform_set_drvdata(pdev, priv); -+ mtd->name = "spiflash"; -+ mtd->type = MTD_NORFLASH; -+ mtd->flags = (MTD_CAP_NORFLASH|MTD_WRITEABLE); -+ mtd->size = flashconfig_tbl[index].byte_cnt; -+ mtd->erasesize = flashconfig_tbl[index].sector_size; -+ mtd->writesize = 1; -+ mtd->numeraseregions = 0; -+ mtd->eraseregions = NULL; -+ mtd->erase = spiflash_erase; -+ mtd->read = spiflash_read; -+ mtd->write = spiflash_write; -+ mtd->owner = THIS_MODULE; -+ -+#ifdef CONFIG_MTD_PARTITIONS -+ /* parse redboot partitions */ -+ num_parts = parse_mtd_partitions(mtd, part_probe_types, &parts, 0); -+ if (!num_parts) -+ goto error; -+ -+ result = add_mtd_partitions(mtd, parts, num_parts); -+#endif -+ -+ return result; -+ -+error: -+ if (priv->mmraddr) -+ iounmap(priv->mmraddr); -+ kfree(priv); -+ return -ENXIO; -+} -+ -+static int -+spiflash_remove (struct platform_device *pdev) -+{ -+ struct spiflash_priv *priv = platform_get_drvdata(pdev); -+ struct mtd_info *mtd = &priv->mtd; -+ -+ del_mtd_partitions(mtd); -+ iounmap(priv->mmraddr); -+ iounmap(priv->readaddr); -+ kfree(priv); -+ -+ return 0; -+} -+ -+struct platform_driver spiflash_driver = { -+ .driver.name = "spiflash", -+ .probe = spiflash_probe, -+ .remove = spiflash_remove, -+}; -+ -+int __init -+spiflash_init (void) -+{ -+ return platform_driver_register(&spiflash_driver); -+} -+ -+void __exit -+spiflash_exit (void) -+{ -+ return platform_driver_unregister(&spiflash_driver); -+} -+ -+module_init (spiflash_init); -+module_exit (spiflash_exit); -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("OpenWrt.org, Atheros Communications Inc"); -+MODULE_DESCRIPTION("MTD driver for SPI Flash on Atheros SOC"); -+ -diff -Nur linux-2.6.39-rc7.orig/drivers/mtd/redboot.c linux-2.6.39-rc7/drivers/mtd/redboot.c ---- linux-2.6.39-rc7.orig/drivers/mtd/redboot.c 2011-05-10 04:33:54.000000000 +0200 -+++ linux-2.6.39-rc7/drivers/mtd/redboot.c 2011-05-15 21:34:57.000000000 +0200 -@@ -55,6 +55,22 @@ - return 1; - } - -+static uint32_t mtd_get_offset_erasesize(struct mtd_info *mtd, uint64_t offset) -+{ -+ struct mtd_erase_region_info *regions = mtd->eraseregions; -+ int i; -+ -+ for (i = 0; i < mtd->numeraseregions; i++) { -+ if (regions[i].offset + -+ regions[i].numblocks * regions[i].erasesize <= offset) -+ continue; -+ -+ return regions[i].erasesize; -+ } -+ -+ return mtd->erasesize; -+} -+ - static int parse_redboot_partitions(struct mtd_info *master, - struct mtd_partition **pparts, - unsigned long fis_origin) -@@ -70,36 +86,38 @@ - int namelen = 0; - int nulllen = 0; - int numslots; -+ int first_slot; - unsigned long offset; - #ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED - static char nullstring[] = "unallocated"; - #endif - -+ buf = vmalloc(master->erasesize); -+ if (!buf) -+ return -ENOMEM; -+ -+ restart: - if ( directory < 0 ) { - offset = master->size + directory * master->erasesize; -- while (master->block_isbad && -+ while (master->block_isbad && - master->block_isbad(master, offset)) { - if (!offset) { - nogood: - printk(KERN_NOTICE "Failed to find a non-bad block to check for RedBoot partition table\n"); -+ vfree(buf); - return -EIO; - } - offset -= master->erasesize; - } - } else { - offset = directory * master->erasesize; -- while (master->block_isbad && -+ while (master->block_isbad && - master->block_isbad(master, offset)) { - offset += master->erasesize; - if (offset == master->size) - goto nogood; - } - } -- buf = vmalloc(master->erasesize); -- -- if (!buf) -- return -ENOMEM; -- - printk(KERN_NOTICE "Searching for RedBoot partition table in %s at offset 0x%lx\n", - master->name, offset); - -@@ -171,13 +189,21 @@ - } - if (i == numslots) { - /* Didn't find it */ -+ if (offset + master->erasesize < master->size) { -+ /* not at the end of the flash yet, maybe next block :) */ -+ directory++; -+ goto restart; -+ } - printk(KERN_NOTICE "No RedBoot partition table detected in %s\n", - master->name); - ret = 0; - goto out; - } - -- for (i = 0; i < numslots; i++) { -+ first_slot = (buf[i].flash_base & (master->erasesize - 1)) / -+ sizeof(struct fis_image_desc); -+ -+ for (i = first_slot; i < first_slot + numslots; i++) { - struct fis_list *new_fl, **prev; - - if (buf[i].name[0] == 0xff) { -diff -Nur linux-2.6.39-rc7.orig/drivers/net/Kconfig linux-2.6.39-rc7/drivers/net/Kconfig ---- linux-2.6.39-rc7.orig/drivers/net/Kconfig 2011-05-10 04:33:54.000000000 +0200 -+++ linux-2.6.39-rc7/drivers/net/Kconfig 2011-05-15 21:34:57.000000000 +0200 -@@ -251,6 +251,12 @@ - help - Select this if your platform comes with an external 93CX6 eeprom. - -+config AR231X_ETHERNET -+ tristate "AR231x Ethernet support" -+ depends on ATHEROS_AR231X -+ help -+ Support for the AR231x/531x ethernet controller -+ - config MACE - tristate "MACE (Power Mac ethernet) support" - depends on PPC_PMAC && PPC32 -diff -Nur linux-2.6.39-rc7.orig/drivers/net/Makefile linux-2.6.39-rc7/drivers/net/Makefile ---- linux-2.6.39-rc7.orig/drivers/net/Makefile 2011-05-10 04:33:54.000000000 +0200 -+++ linux-2.6.39-rc7/drivers/net/Makefile 2011-05-15 21:34:57.000000000 +0200 -@@ -226,6 +226,7 @@ - obj-$(CONFIG_KORINA) += korina.o - obj-$(CONFIG_MIPS_JAZZ_SONIC) += jazzsonic.o - obj-$(CONFIG_MIPS_AU1X00_ENET) += au1000_eth.o -+obj-$(CONFIG_AR231X_ETHERNET) += ar231x.o - obj-$(CONFIG_MIPS_SIM_NET) += mipsnet.o - obj-$(CONFIG_SGI_IOC3_ETH) += ioc3-eth.o - obj-$(CONFIG_DECLANCE) += declance.o -diff -Nur linux-2.6.39-rc7.orig/drivers/net/ar231x.c linux-2.6.39-rc7/drivers/net/ar231x.c ---- linux-2.6.39-rc7.orig/drivers/net/ar231x.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/drivers/net/ar231x.c 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,1293 @@ -+/* -+ * ar231x.c: Linux driver for the Atheros AR231x Ethernet device. -+ * -+ * Copyright (C) 2004 by Sameer Dekate -+ * Copyright (C) 2006 Imre Kaloz -+ * Copyright (C) 2006-2009 Felix Fietkau -+ * -+ * Thanks to Atheros for providing hardware and documentation -+ * enabling me to write this driver. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * Additional credits: -+ * This code is taken from John Taylor's Sibyte driver and then -+ * modified for the AR2313. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define AR2313_MTU 1692 -+#define AR2313_PRIOS 1 -+#define AR2313_QUEUES (2*AR2313_PRIOS) -+#define AR2313_DESCR_ENTRIES 64 -+ -+ -+#ifndef min -+#define min(a,b) (((a)<(b))?(a):(b)) -+#endif -+ -+#ifndef SMP_CACHE_BYTES -+#define SMP_CACHE_BYTES L1_CACHE_BYTES -+#endif -+ -+#define AR2313_MBOX_SET_BIT 0x8 -+ -+#include "ar231x.h" -+ -+/* -+ * New interrupt handler strategy: -+ * -+ * An old interrupt handler worked using the traditional method of -+ * replacing an skbuff with a new one when a packet arrives. However -+ * the rx rings do not need to contain a static number of buffer -+ * descriptors, thus it makes sense to move the memory allocation out -+ * of the main interrupt handler and do it in a bottom half handler -+ * and only allocate new buffers when the number of buffers in the -+ * ring is below a certain threshold. In order to avoid starving the -+ * NIC under heavy load it is however necessary to force allocation -+ * when hitting a minimum threshold. The strategy for alloction is as -+ * follows: -+ * -+ * RX_LOW_BUF_THRES - allocate buffers in the bottom half -+ * RX_PANIC_LOW_THRES - we are very low on buffers, allocate -+ * the buffers in the interrupt handler -+ * RX_RING_THRES - maximum number of buffers in the rx ring -+ * -+ * One advantagous side effect of this allocation approach is that the -+ * entire rx processing can be done without holding any spin lock -+ * since the rx rings and registers are totally independent of the tx -+ * ring and its registers. This of course includes the kmalloc's of -+ * new skb's. Thus start_xmit can run in parallel with rx processing -+ * and the memory allocation on SMP systems. -+ * -+ * Note that running the skb reallocation in a bottom half opens up -+ * another can of races which needs to be handled properly. In -+ * particular it can happen that the interrupt handler tries to run -+ * the reallocation while the bottom half is either running on another -+ * CPU or was interrupted on the same CPU. To get around this the -+ * driver uses bitops to prevent the reallocation routines from being -+ * reentered. -+ * -+ * TX handling can also be done without holding any spin lock, wheee -+ * this is fun! since tx_csm is only written to by the interrupt -+ * handler. -+ */ -+ -+/* -+ * Threshold values for RX buffer allocation - the low water marks for -+ * when to start refilling the rings are set to 75% of the ring -+ * sizes. It seems to make sense to refill the rings entirely from the -+ * intrrupt handler once it gets below the panic threshold, that way -+ * we don't risk that the refilling is moved to another CPU when the -+ * one running the interrupt handler just got the slab code hot in its -+ * cache. -+ */ -+#define RX_RING_SIZE AR2313_DESCR_ENTRIES -+#define RX_PANIC_THRES (RX_RING_SIZE/4) -+#define RX_LOW_THRES ((3*RX_RING_SIZE)/4) -+#define CRC_LEN 4 -+#define RX_OFFSET 2 -+ -+#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) -+#define VLAN_HDR 4 -+#else -+#define VLAN_HDR 0 -+#endif -+ -+#define AR2313_BUFSIZE (AR2313_MTU + VLAN_HDR + ETH_HLEN + CRC_LEN + RX_OFFSET) -+ -+#ifdef MODULE -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Sameer Dekate , Imre Kaloz , Felix Fietkau "); -+MODULE_DESCRIPTION("AR231x Ethernet driver"); -+#endif -+ -+#define virt_to_phys(x) ((u32)(x) & 0x1fffffff) -+ -+// prototypes -+static void ar231x_halt(struct net_device *dev); -+static void rx_tasklet_func(unsigned long data); -+static void rx_tasklet_cleanup(struct net_device *dev); -+static void ar231x_multicast_list(struct net_device *dev); -+static void ar231x_tx_timeout(struct net_device *dev); -+ -+static int ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum); -+static int ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, u16 value); -+static int ar231x_mdiobus_reset(struct mii_bus *bus); -+static int ar231x_mdiobus_probe (struct net_device *dev); -+static void ar231x_adjust_link(struct net_device *dev); -+ -+#ifndef ERR -+#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args) -+#endif -+ -+#ifdef CONFIG_NET_POLL_CONTROLLER -+static void -+ar231x_netpoll(struct net_device *dev) -+{ -+ unsigned long flags; -+ -+ local_irq_save(flags); -+ ar231x_interrupt(dev->irq, dev); -+ local_irq_restore(flags); -+} -+#endif -+ -+static const struct net_device_ops ar231x_ops = { -+ .ndo_open = ar231x_open, -+ .ndo_stop = ar231x_close, -+ .ndo_start_xmit = ar231x_start_xmit, -+ .ndo_set_multicast_list = ar231x_multicast_list, -+ .ndo_do_ioctl = ar231x_ioctl, -+ .ndo_change_mtu = eth_change_mtu, -+ .ndo_validate_addr = eth_validate_addr, -+ .ndo_set_mac_address = eth_mac_addr, -+ .ndo_tx_timeout = ar231x_tx_timeout, -+#ifdef CONFIG_NET_POLL_CONTROLLER -+ .ndo_poll_controller = ar231x_netpoll, -+#endif -+}; -+ -+int __init ar231x_probe(struct platform_device *pdev) -+{ -+ struct net_device *dev; -+ struct ar231x_private *sp; -+ struct resource *res; -+ unsigned long ar_eth_base; -+ char buf[64]; -+ -+ dev = alloc_etherdev(sizeof(struct ar231x_private)); -+ -+ if (dev == NULL) { -+ printk(KERN_ERR -+ "ar231x: Unable to allocate net_device structure!\n"); -+ return -ENOMEM; -+ } -+ -+ platform_set_drvdata(pdev, dev); -+ -+ sp = netdev_priv(dev); -+ sp->dev = dev; -+ sp->cfg = pdev->dev.platform_data; -+ -+ sprintf(buf, "eth%d_membase", pdev->id); -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, buf); -+ if (!res) -+ return -ENODEV; -+ -+ sp->link = 0; -+ ar_eth_base = res->start; -+ -+ sprintf(buf, "eth%d_irq", pdev->id); -+ dev->irq = platform_get_irq_byname(pdev, buf); -+ -+ spin_lock_init(&sp->lock); -+ -+ dev->features |= NETIF_F_HIGHDMA; -+ dev->netdev_ops = &ar231x_ops; -+ -+ tasklet_init(&sp->rx_tasklet, rx_tasklet_func, (unsigned long) dev); -+ tasklet_disable(&sp->rx_tasklet); -+ -+ sp->eth_regs = -+ ioremap_nocache(virt_to_phys(ar_eth_base), sizeof(*sp->eth_regs)); -+ if (!sp->eth_regs) { -+ printk("Can't remap eth registers\n"); -+ return (-ENXIO); -+ } -+ -+ /* -+ * When there's only one MAC, PHY regs are typically on ENET0, -+ * even though the MAC might be on ENET1. -+ * Needto remap PHY regs separately in this case -+ */ -+ if (virt_to_phys(ar_eth_base) == virt_to_phys(sp->phy_regs)) -+ sp->phy_regs = sp->eth_regs; -+ else { -+ sp->phy_regs = -+ ioremap_nocache(virt_to_phys(sp->cfg->phy_base), -+ sizeof(*sp->phy_regs)); -+ if (!sp->phy_regs) { -+ printk("Can't remap phy registers\n"); -+ return (-ENXIO); -+ } -+ } -+ -+ sp->dma_regs = -+ ioremap_nocache(virt_to_phys(ar_eth_base + 0x1000), -+ sizeof(*sp->dma_regs)); -+ dev->base_addr = (unsigned int) sp->dma_regs; -+ if (!sp->dma_regs) { -+ printk("Can't remap DMA registers\n"); -+ return (-ENXIO); -+ } -+ -+ sp->int_regs = ioremap_nocache(virt_to_phys(sp->cfg->reset_base), 4); -+ if (!sp->int_regs) { -+ printk("Can't remap INTERRUPT registers\n"); -+ return (-ENXIO); -+ } -+ -+ strncpy(sp->name, "Atheros AR231x", sizeof(sp->name) - 1); -+ sp->name[sizeof(sp->name) - 1] = '\0'; -+ memcpy(dev->dev_addr, sp->cfg->macaddr, 6); -+ -+ if (ar231x_init(dev)) { -+ /* -+ * ar231x_init() calls ar231x_init_cleanup() on error. -+ */ -+ kfree(dev); -+ return -ENODEV; -+ } -+ -+ if (register_netdev(dev)) { -+ printk("%s: register_netdev failed\n", __func__); -+ return -1; -+ } -+ -+ printk("%s: %s: %02x:%02x:%02x:%02x:%02x:%02x, irq %d\n", -+ dev->name, sp->name, -+ dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], -+ dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5], dev->irq); -+ -+ sp->mii_bus = mdiobus_alloc(); -+ if (sp->mii_bus == NULL) -+ return -1; -+ -+ sp->mii_bus->priv = dev; -+ sp->mii_bus->read = ar231x_mdiobus_read; -+ sp->mii_bus->write = ar231x_mdiobus_write; -+ sp->mii_bus->reset = ar231x_mdiobus_reset; -+ sp->mii_bus->name = "ar231x_eth_mii"; -+ snprintf(sp->mii_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id); -+ sp->mii_bus->irq = kmalloc(sizeof(int), GFP_KERNEL); -+ *sp->mii_bus->irq = PHY_POLL; -+ -+ mdiobus_register(sp->mii_bus); -+ -+ if (ar231x_mdiobus_probe(dev) != 0) { -+ printk(KERN_ERR "%s: mdiobus_probe failed\n", dev->name); -+ rx_tasklet_cleanup(dev); -+ ar231x_init_cleanup(dev); -+ unregister_netdev(dev); -+ kfree(dev); -+ return -ENODEV; -+ } -+ -+ /* start link poll timer */ -+ ar231x_setup_timer(dev); -+ -+ return 0; -+} -+ -+ -+static void ar231x_multicast_list(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ unsigned int filter; -+ -+ filter = sp->eth_regs->mac_control; -+ -+ if (dev->flags & IFF_PROMISC) -+ filter |= MAC_CONTROL_PR; -+ else -+ filter &= ~MAC_CONTROL_PR; -+ if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 0)) -+ filter |= MAC_CONTROL_PM; -+ else -+ filter &= ~MAC_CONTROL_PM; -+ -+ sp->eth_regs->mac_control = filter; -+} -+ -+static void rx_tasklet_cleanup(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ -+ /* -+ * Tasklet may be scheduled. Need to get it removed from the list -+ * since we're about to free the struct. -+ */ -+ -+ sp->unloading = 1; -+ tasklet_enable(&sp->rx_tasklet); -+ tasklet_kill(&sp->rx_tasklet); -+} -+ -+static int __devexit ar231x_remove(struct platform_device *pdev) -+{ -+ struct net_device *dev = platform_get_drvdata(pdev); -+ struct ar231x_private *sp = netdev_priv(dev); -+ rx_tasklet_cleanup(dev); -+ ar231x_init_cleanup(dev); -+ unregister_netdev(dev); -+ mdiobus_unregister(sp->mii_bus); -+ mdiobus_free(sp->mii_bus); -+ kfree(dev); -+ return 0; -+} -+ -+ -+/* -+ * Restart the AR2313 ethernet controller. -+ */ -+static int ar231x_restart(struct net_device *dev) -+{ -+ /* disable interrupts */ -+ disable_irq(dev->irq); -+ -+ /* stop mac */ -+ ar231x_halt(dev); -+ -+ /* initialize */ -+ ar231x_init(dev); -+ -+ /* enable interrupts */ -+ enable_irq(dev->irq); -+ -+ return 0; -+} -+ -+static struct platform_driver ar231x_driver = { -+ .driver.name = "ar231x-eth", -+ .probe = ar231x_probe, -+ .remove = __devexit_p(ar231x_remove), -+}; -+ -+int __init ar231x_module_init(void) -+{ -+ return platform_driver_register(&ar231x_driver); -+} -+ -+void __exit ar231x_module_cleanup(void) -+{ -+ platform_driver_unregister(&ar231x_driver); -+} -+ -+module_init(ar231x_module_init); -+module_exit(ar231x_module_cleanup); -+ -+ -+static void ar231x_free_descriptors(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ if (sp->rx_ring != NULL) { -+ kfree((void *) KSEG0ADDR(sp->rx_ring)); -+ sp->rx_ring = NULL; -+ sp->tx_ring = NULL; -+ } -+} -+ -+ -+static int ar231x_allocate_descriptors(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ int size; -+ int j; -+ ar231x_descr_t *space; -+ -+ if (sp->rx_ring != NULL) { -+ printk("%s: already done.\n", __FUNCTION__); -+ return 0; -+ } -+ -+ size = -+ (sizeof(ar231x_descr_t) * (AR2313_DESCR_ENTRIES * AR2313_QUEUES)); -+ space = kmalloc(size, GFP_KERNEL); -+ if (space == NULL) -+ return 1; -+ -+ /* invalidate caches */ -+ dma_cache_inv((unsigned int) space, size); -+ -+ /* now convert pointer to KSEG1 */ -+ space = (ar231x_descr_t *) KSEG1ADDR(space); -+ -+ memset((void *) space, 0, size); -+ -+ sp->rx_ring = space; -+ space += AR2313_DESCR_ENTRIES; -+ -+ sp->tx_ring = space; -+ space += AR2313_DESCR_ENTRIES; -+ -+ /* Initialize the transmit Descriptors */ -+ for (j = 0; j < AR2313_DESCR_ENTRIES; j++) { -+ ar231x_descr_t *td = &sp->tx_ring[j]; -+ td->status = 0; -+ td->devcs = DMA_TX1_CHAINED; -+ td->addr = 0; -+ td->descr = -+ virt_to_phys(&sp-> -+ tx_ring[(j + 1) & (AR2313_DESCR_ENTRIES - 1)]); -+ } -+ -+ return 0; -+} -+ -+ -+/* -+ * Generic cleanup handling data allocated during init. Used when the -+ * module is unloaded or if an error occurs during initialization -+ */ -+static void ar231x_init_cleanup(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ struct sk_buff *skb; -+ int j; -+ -+ ar231x_free_descriptors(dev); -+ -+ if (sp->eth_regs) -+ iounmap((void *) sp->eth_regs); -+ if (sp->dma_regs) -+ iounmap((void *) sp->dma_regs); -+ -+ if (sp->rx_skb) { -+ for (j = 0; j < AR2313_DESCR_ENTRIES; j++) { -+ skb = sp->rx_skb[j]; -+ if (skb) { -+ sp->rx_skb[j] = NULL; -+ dev_kfree_skb(skb); -+ } -+ } -+ kfree(sp->rx_skb); -+ sp->rx_skb = NULL; -+ } -+ -+ if (sp->tx_skb) { -+ for (j = 0; j < AR2313_DESCR_ENTRIES; j++) { -+ skb = sp->tx_skb[j]; -+ if (skb) { -+ sp->tx_skb[j] = NULL; -+ dev_kfree_skb(skb); -+ } -+ } -+ kfree(sp->tx_skb); -+ sp->tx_skb = NULL; -+ } -+} -+ -+static int ar231x_setup_timer(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ -+ init_timer(&sp->link_timer); -+ -+ sp->link_timer.function = ar231x_link_timer_fn; -+ sp->link_timer.data = (int) dev; -+ sp->link_timer.expires = jiffies + HZ; -+ -+ add_timer(&sp->link_timer); -+ return 0; -+ -+} -+ -+static void ar231x_link_timer_fn(unsigned long data) -+{ -+ struct net_device *dev = (struct net_device *) data; -+ struct ar231x_private *sp = netdev_priv(dev); -+ -+ // see if the link status changed -+ // This was needed to make sure we set the PHY to the -+ // autonegotiated value of half or full duplex. -+ ar231x_check_link(dev); -+ -+ // Loop faster when we don't have link. -+ // This was needed to speed up the AP bootstrap time. -+ if (sp->link == 0) { -+ mod_timer(&sp->link_timer, jiffies + HZ / 2); -+ } else { -+ mod_timer(&sp->link_timer, jiffies + LINK_TIMER); -+ } -+} -+ -+static void ar231x_check_link(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ u16 phyData; -+ -+ phyData = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_BMSR); -+ if (sp->phyData != phyData) { -+ if (phyData & BMSR_LSTATUS) { -+ /* link is present, ready link partner ability to deterine -+ duplexity */ -+ int duplex = 0; -+ u16 reg; -+ -+ sp->link = 1; -+ reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_BMCR); -+ if (reg & BMCR_ANENABLE) { -+ /* auto neg enabled */ -+ reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_LPA); -+ duplex = (reg & (LPA_100FULL | LPA_10FULL)) ? 1 : 0; -+ } else { -+ /* no auto neg, just read duplex config */ -+ duplex = (reg & BMCR_FULLDPLX) ? 1 : 0; -+ } -+ -+ printk(KERN_INFO "%s: Configuring MAC for %s duplex\n", -+ dev->name, (duplex) ? "full" : "half"); -+ -+ if (duplex) { -+ /* full duplex */ -+ sp->eth_regs->mac_control = -+ ((sp->eth_regs-> -+ mac_control | MAC_CONTROL_F) & ~MAC_CONTROL_DRO); -+ } else { -+ /* half duplex */ -+ sp->eth_regs->mac_control = -+ ((sp->eth_regs-> -+ mac_control | MAC_CONTROL_DRO) & ~MAC_CONTROL_F); -+ } -+ } else { -+ /* no link */ -+ sp->link = 0; -+ } -+ sp->phyData = phyData; -+ } -+} -+ -+static int ar231x_reset_reg(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ unsigned int ethsal, ethsah; -+ unsigned int flags; -+ -+ *sp->int_regs |= sp->cfg->reset_mac; -+ mdelay(10); -+ *sp->int_regs &= ~sp->cfg->reset_mac; -+ mdelay(10); -+ *sp->int_regs |= sp->cfg->reset_phy; -+ mdelay(10); -+ *sp->int_regs &= ~sp->cfg->reset_phy; -+ mdelay(10); -+ -+ sp->dma_regs->bus_mode = (DMA_BUS_MODE_SWR); -+ mdelay(10); -+ sp->dma_regs->bus_mode = -+ ((32 << DMA_BUS_MODE_PBL_SHIFT) | DMA_BUS_MODE_BLE); -+ -+ /* enable interrupts */ -+ sp->dma_regs->intr_ena = (DMA_STATUS_AIS | -+ DMA_STATUS_NIS | -+ DMA_STATUS_RI | -+ DMA_STATUS_TI | DMA_STATUS_FBE); -+ sp->dma_regs->xmt_base = virt_to_phys(sp->tx_ring); -+ sp->dma_regs->rcv_base = virt_to_phys(sp->rx_ring); -+ sp->dma_regs->control = -+ (DMA_CONTROL_SR | DMA_CONTROL_ST | DMA_CONTROL_SF); -+ -+ sp->eth_regs->flow_control = (FLOW_CONTROL_FCE); -+ sp->eth_regs->vlan_tag = (0x8100); -+ -+ /* Enable Ethernet Interface */ -+ flags = (MAC_CONTROL_TE | /* transmit enable */ -+ MAC_CONTROL_PM | /* pass mcast */ -+ MAC_CONTROL_F | /* full duplex */ -+ MAC_CONTROL_HBD); /* heart beat disabled */ -+ -+ if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */ -+ flags |= MAC_CONTROL_PR; -+ } -+ sp->eth_regs->mac_control = flags; -+ -+ /* Set all Ethernet station address registers to their initial values */ -+ ethsah = ((((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) | -+ (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF)); -+ -+ ethsal = ((((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) | -+ (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) | -+ (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) | -+ (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF)); -+ -+ sp->eth_regs->mac_addr[0] = ethsah; -+ sp->eth_regs->mac_addr[1] = ethsal; -+ -+ mdelay(10); -+ -+ return (0); -+} -+ -+ -+static int ar231x_init(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ int ecode = 0; -+ -+ /* -+ * Allocate descriptors -+ */ -+ if (ar231x_allocate_descriptors(dev)) { -+ printk("%s: %s: ar231x_allocate_descriptors failed\n", -+ dev->name, __FUNCTION__); -+ ecode = -EAGAIN; -+ goto init_error; -+ } -+ -+ /* -+ * Get the memory for the skb rings. -+ */ -+ if (sp->rx_skb == NULL) { -+ sp->rx_skb = -+ kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES, -+ GFP_KERNEL); -+ if (!(sp->rx_skb)) { -+ printk("%s: %s: rx_skb kmalloc failed\n", -+ dev->name, __FUNCTION__); -+ ecode = -EAGAIN; -+ goto init_error; -+ } -+ } -+ memset(sp->rx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES); -+ -+ if (sp->tx_skb == NULL) { -+ sp->tx_skb = -+ kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES, -+ GFP_KERNEL); -+ if (!(sp->tx_skb)) { -+ printk("%s: %s: tx_skb kmalloc failed\n", -+ dev->name, __FUNCTION__); -+ ecode = -EAGAIN; -+ goto init_error; -+ } -+ } -+ memset(sp->tx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES); -+ -+ /* -+ * Set tx_csm before we start receiving interrupts, otherwise -+ * the interrupt handler might think it is supposed to process -+ * tx ints before we are up and running, which may cause a null -+ * pointer access in the int handler. -+ */ -+ sp->rx_skbprd = 0; -+ sp->cur_rx = 0; -+ sp->tx_prd = 0; -+ sp->tx_csm = 0; -+ -+ /* -+ * Zero the stats before starting the interface -+ */ -+ memset(&dev->stats, 0, sizeof(dev->stats)); -+ -+ /* -+ * We load the ring here as there seem to be no way to tell the -+ * firmware to wipe the ring without re-initializing it. -+ */ -+ ar231x_load_rx_ring(dev, RX_RING_SIZE); -+ -+ /* -+ * Init hardware -+ */ -+ ar231x_reset_reg(dev); -+ -+ /* -+ * Get the IRQ -+ */ -+ ecode = -+ request_irq(dev->irq, &ar231x_interrupt, -+ IRQF_DISABLED | IRQF_SAMPLE_RANDOM, -+ dev->name, dev); -+ if (ecode) { -+ printk(KERN_WARNING "%s: %s: Requested IRQ %d is busy\n", -+ dev->name, __FUNCTION__, dev->irq); -+ goto init_error; -+ } -+ -+ -+ tasklet_enable(&sp->rx_tasklet); -+ -+ return 0; -+ -+ init_error: -+ ar231x_init_cleanup(dev); -+ return ecode; -+} -+ -+/* -+ * Load the rx ring. -+ * -+ * Loading rings is safe without holding the spin lock since this is -+ * done only before the device is enabled, thus no interrupts are -+ * generated and by the interrupt handler/tasklet handler. -+ */ -+static void ar231x_load_rx_ring(struct net_device *dev, int nr_bufs) -+{ -+ -+ struct ar231x_private *sp = netdev_priv(dev); -+ short i, idx; -+ -+ idx = sp->rx_skbprd; -+ -+ for (i = 0; i < nr_bufs; i++) { -+ struct sk_buff *skb; -+ ar231x_descr_t *rd; -+ -+ if (sp->rx_skb[idx]) -+ break; -+ -+ skb = netdev_alloc_skb(dev, AR2313_BUFSIZE); -+ if (!skb) { -+ printk("\n\n\n\n %s: No memory in system\n\n\n\n", -+ __FUNCTION__); -+ break; -+ } -+ -+ /* -+ * Make sure IP header starts on a fresh cache line. -+ */ -+ skb->dev = dev; -+ skb_reserve(skb, RX_OFFSET); -+ sp->rx_skb[idx] = skb; -+ -+ rd = (ar231x_descr_t *) & sp->rx_ring[idx]; -+ -+ /* initialize dma descriptor */ -+ rd->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) | -+ DMA_RX1_CHAINED); -+ rd->addr = virt_to_phys(skb->data); -+ rd->descr = -+ virt_to_phys(&sp-> -+ rx_ring[(idx + 1) & (AR2313_DESCR_ENTRIES - 1)]); -+ rd->status = DMA_RX_OWN; -+ -+ idx = DSC_NEXT(idx); -+ } -+ -+ if (i) -+ sp->rx_skbprd = idx; -+ -+ return; -+} -+ -+#define AR2313_MAX_PKTS_PER_CALL 64 -+ -+static int ar231x_rx_int(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ struct sk_buff *skb, *skb_new; -+ ar231x_descr_t *rxdesc; -+ unsigned int status; -+ u32 idx; -+ int pkts = 0; -+ int rval; -+ -+ idx = sp->cur_rx; -+ -+ /* process at most the entire ring and then wait for another interrupt -+ */ -+ while (1) { -+ -+ rxdesc = &sp->rx_ring[idx]; -+ status = rxdesc->status; -+ if (status & DMA_RX_OWN) { -+ /* SiByte owns descriptor or descr not yet filled in */ -+ rval = 0; -+ break; -+ } -+ -+ if (++pkts > AR2313_MAX_PKTS_PER_CALL) { -+ rval = 1; -+ break; -+ } -+ -+ if ((status & DMA_RX_ERROR) && !(status & DMA_RX_LONG)) { -+ dev->stats.rx_errors++; -+ dev->stats.rx_dropped++; -+ -+ /* add statistics counters */ -+ if (status & DMA_RX_ERR_CRC) -+ dev->stats.rx_crc_errors++; -+ if (status & DMA_RX_ERR_COL) -+ dev->stats.rx_over_errors++; -+ if (status & DMA_RX_ERR_LENGTH) -+ dev->stats.rx_length_errors++; -+ if (status & DMA_RX_ERR_RUNT) -+ dev->stats.rx_over_errors++; -+ if (status & DMA_RX_ERR_DESC) -+ dev->stats.rx_over_errors++; -+ -+ } else { -+ /* alloc new buffer. */ -+ skb_new = netdev_alloc_skb(dev, AR2313_BUFSIZE + RX_OFFSET); -+ if (skb_new != NULL) { -+ -+ skb = sp->rx_skb[idx]; -+ /* set skb */ -+ skb_put(skb, -+ ((status >> DMA_RX_LEN_SHIFT) & 0x3fff) - CRC_LEN); -+ -+ dev->stats.rx_bytes += skb->len; -+ skb->protocol = eth_type_trans(skb, dev); -+ /* pass the packet to upper layers */ -+ netif_rx(skb); -+ -+ skb_new->dev = dev; -+ /* 16 bit align */ -+ skb_reserve(skb_new, RX_OFFSET); -+ /* reset descriptor's curr_addr */ -+ rxdesc->addr = virt_to_phys(skb_new->data); -+ -+ dev->stats.rx_packets++; -+ sp->rx_skb[idx] = skb_new; -+ } else { -+ dev->stats.rx_dropped++; -+ } -+ } -+ -+ rxdesc->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) | -+ DMA_RX1_CHAINED); -+ rxdesc->status = DMA_RX_OWN; -+ -+ idx = DSC_NEXT(idx); -+ } -+ -+ sp->cur_rx = idx; -+ -+ return rval; -+} -+ -+ -+static void ar231x_tx_int(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ u32 idx; -+ struct sk_buff *skb; -+ ar231x_descr_t *txdesc; -+ unsigned int status = 0; -+ -+ idx = sp->tx_csm; -+ -+ while (idx != sp->tx_prd) { -+ txdesc = &sp->tx_ring[idx]; -+ -+ if ((status = txdesc->status) & DMA_TX_OWN) { -+ /* ar231x dma still owns descr */ -+ break; -+ } -+ /* done with this descriptor */ -+ dma_unmap_single(NULL, txdesc->addr, -+ txdesc->devcs & DMA_TX1_BSIZE_MASK, -+ DMA_TO_DEVICE); -+ txdesc->status = 0; -+ -+ if (status & DMA_TX_ERROR) { -+ dev->stats.tx_errors++; -+ dev->stats.tx_dropped++; -+ if (status & DMA_TX_ERR_UNDER) -+ dev->stats.tx_fifo_errors++; -+ if (status & DMA_TX_ERR_HB) -+ dev->stats.tx_heartbeat_errors++; -+ if (status & (DMA_TX_ERR_LOSS | DMA_TX_ERR_LINK)) -+ dev->stats.tx_carrier_errors++; -+ if (status & (DMA_TX_ERR_LATE | -+ DMA_TX_ERR_COL | -+ DMA_TX_ERR_JABBER | DMA_TX_ERR_DEFER)) -+ dev->stats.tx_aborted_errors++; -+ } else { -+ /* transmit OK */ -+ dev->stats.tx_packets++; -+ } -+ -+ skb = sp->tx_skb[idx]; -+ sp->tx_skb[idx] = NULL; -+ idx = DSC_NEXT(idx); -+ dev->stats.tx_bytes += skb->len; -+ dev_kfree_skb_irq(skb); -+ } -+ -+ sp->tx_csm = idx; -+ -+ return; -+} -+ -+ -+static void rx_tasklet_func(unsigned long data) -+{ -+ struct net_device *dev = (struct net_device *) data; -+ struct ar231x_private *sp = netdev_priv(dev); -+ -+ if (sp->unloading) { -+ return; -+ } -+ -+ if (ar231x_rx_int(dev)) { -+ tasklet_hi_schedule(&sp->rx_tasklet); -+ } else { -+ unsigned long flags; -+ spin_lock_irqsave(&sp->lock, flags); -+ sp->dma_regs->intr_ena |= DMA_STATUS_RI; -+ spin_unlock_irqrestore(&sp->lock, flags); -+ } -+} -+ -+static void rx_schedule(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ -+ sp->dma_regs->intr_ena &= ~DMA_STATUS_RI; -+ -+ tasklet_hi_schedule(&sp->rx_tasklet); -+} -+ -+static irqreturn_t ar231x_interrupt(int irq, void *dev_id) -+{ -+ struct net_device *dev = (struct net_device *) dev_id; -+ struct ar231x_private *sp = netdev_priv(dev); -+ unsigned int status, enabled; -+ -+ /* clear interrupt */ -+ /* -+ * Don't clear RI bit if currently disabled. -+ */ -+ status = sp->dma_regs->status; -+ enabled = sp->dma_regs->intr_ena; -+ sp->dma_regs->status = status & enabled; -+ -+ if (status & DMA_STATUS_NIS) { -+ /* normal status */ -+ /* -+ * Don't schedule rx processing if interrupt -+ * is already disabled. -+ */ -+ if (status & enabled & DMA_STATUS_RI) { -+ /* receive interrupt */ -+ rx_schedule(dev); -+ } -+ if (status & DMA_STATUS_TI) { -+ /* transmit interrupt */ -+ ar231x_tx_int(dev); -+ } -+ } -+ -+ /* abnormal status */ -+ if (status & (DMA_STATUS_FBE | DMA_STATUS_TPS)) { -+ ar231x_restart(dev); -+ } -+ return IRQ_HANDLED; -+} -+ -+ -+static int ar231x_open(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ unsigned int ethsal, ethsah; -+ -+ /* reset the hardware, in case the MAC address changed */ -+ ethsah = ((((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) | -+ (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF)); -+ -+ ethsal = ((((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) | -+ (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) | -+ (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) | -+ (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF)); -+ -+ sp->eth_regs->mac_addr[0] = ethsah; -+ sp->eth_regs->mac_addr[1] = ethsal; -+ -+ mdelay(10); -+ -+ dev->mtu = 1500; -+ netif_start_queue(dev); -+ -+ sp->eth_regs->mac_control |= MAC_CONTROL_RE; -+ -+ return 0; -+} -+ -+static void ar231x_tx_timeout(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ unsigned long flags; -+ -+ spin_lock_irqsave(&sp->lock, flags); -+ ar231x_restart(dev); -+ spin_unlock_irqrestore(&sp->lock, flags); -+} -+ -+static void ar231x_halt(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ int j; -+ -+ tasklet_disable(&sp->rx_tasklet); -+ -+ /* kill the MAC */ -+ sp->eth_regs->mac_control &= ~(MAC_CONTROL_RE | /* disable Receives */ -+ MAC_CONTROL_TE); /* disable Transmits */ -+ /* stop dma */ -+ sp->dma_regs->control = 0; -+ sp->dma_regs->bus_mode = DMA_BUS_MODE_SWR; -+ -+ /* place phy and MAC in reset */ -+ *sp->int_regs |= (sp->cfg->reset_mac | sp->cfg->reset_phy); -+ -+ /* free buffers on tx ring */ -+ for (j = 0; j < AR2313_DESCR_ENTRIES; j++) { -+ struct sk_buff *skb; -+ ar231x_descr_t *txdesc; -+ -+ txdesc = &sp->tx_ring[j]; -+ txdesc->descr = 0; -+ -+ skb = sp->tx_skb[j]; -+ if (skb) { -+ dev_kfree_skb(skb); -+ sp->tx_skb[j] = NULL; -+ } -+ } -+} -+ -+/* -+ * close should do nothing. Here's why. It's called when -+ * 'ifconfig bond0 down' is run. If it calls free_irq then -+ * the irq is gone forever ! When bond0 is made 'up' again, -+ * the ar231x_open () does not call request_irq (). Worse, -+ * the call to ar231x_halt() generates a WDOG reset due to -+ * the write to 'sp->int_regs' and the box reboots. -+ * Commenting this out is good since it allows the -+ * system to resume when bond0 is made up again. -+ */ -+static int ar231x_close(struct net_device *dev) -+{ -+#if 0 -+ /* -+ * Disable interrupts -+ */ -+ disable_irq(dev->irq); -+ -+ /* -+ * Without (or before) releasing irq and stopping hardware, this -+ * is an absolute non-sense, by the way. It will be reset instantly -+ * by the first irq. -+ */ -+ netif_stop_queue(dev); -+ -+ /* stop the MAC and DMA engines */ -+ ar231x_halt(dev); -+ -+ /* release the interrupt */ -+ free_irq(dev->irq, dev); -+ -+#endif -+ return 0; -+} -+ -+static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ ar231x_descr_t *td; -+ u32 idx; -+ -+ idx = sp->tx_prd; -+ td = &sp->tx_ring[idx]; -+ -+ if (td->status & DMA_TX_OWN) { -+ /* free skbuf and lie to the caller that we sent it out */ -+ dev->stats.tx_dropped++; -+ dev_kfree_skb(skb); -+ -+ /* restart transmitter in case locked */ -+ sp->dma_regs->xmt_poll = 0; -+ return 0; -+ } -+ -+ /* Setup the transmit descriptor. */ -+ td->devcs = ((skb->len << DMA_TX1_BSIZE_SHIFT) | -+ (DMA_TX1_LS | DMA_TX1_IC | DMA_TX1_CHAINED)); -+ td->addr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE); -+ td->status = DMA_TX_OWN; -+ -+ /* kick transmitter last */ -+ sp->dma_regs->xmt_poll = 0; -+ -+ sp->tx_skb[idx] = skb; -+ idx = DSC_NEXT(idx); -+ sp->tx_prd = idx; -+ -+ return 0; -+} -+ -+static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) -+{ -+ struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_data; -+ struct ar231x_private *sp = netdev_priv(dev); -+ int ret; -+ -+ switch (cmd) { -+ -+ case SIOCETHTOOL: -+ spin_lock_irq(&sp->lock); -+ ret = phy_ethtool_ioctl(sp->phy_dev, (void *) ifr->ifr_data); -+ spin_unlock_irq(&sp->lock); -+ return ret; -+ -+ case SIOCSIFHWADDR: -+ if (copy_from_user -+ (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr))) -+ return -EFAULT; -+ return 0; -+ -+ case SIOCGIFHWADDR: -+ if (copy_to_user -+ (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr))) -+ return -EFAULT; -+ return 0; -+ -+ case SIOCGMIIPHY: -+ case SIOCGMIIREG: -+ case SIOCSMIIREG: -+ return phy_mii_ioctl(sp->phy_dev, data, cmd); -+ -+ default: -+ break; -+ } -+ -+ return -EOPNOTSUPP; -+} -+ -+static void ar231x_adjust_link(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ unsigned int mc; -+ -+ if (!sp->phy_dev->link) -+ return; -+ -+ if (sp->phy_dev->duplex != sp->oldduplex) { -+ mc = readl(&sp->eth_regs->mac_control); -+ mc &= ~(MAC_CONTROL_F | MAC_CONTROL_DRO); -+ if (sp->phy_dev->duplex) -+ mc |= MAC_CONTROL_F; -+ else -+ mc |= MAC_CONTROL_DRO; -+ writel(mc, &sp->eth_regs->mac_control); -+ sp->oldduplex = sp->phy_dev->duplex; -+ } -+} -+ -+#define MII_ADDR(phy, reg) \ -+ ((reg << MII_ADDR_REG_SHIFT) | (phy << MII_ADDR_PHY_SHIFT)) -+ -+static int -+ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum) -+{ -+ struct net_device *const dev = bus->priv; -+ struct ar231x_private *sp = netdev_priv(dev); -+ volatile ETHERNET_STRUCT *ethernet = sp->phy_regs; -+ -+ ethernet->mii_addr = MII_ADDR(phy_addr, regnum); -+ while (ethernet->mii_addr & MII_ADDR_BUSY); -+ return (ethernet->mii_data >> MII_DATA_SHIFT); -+} -+ -+static int -+ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, -+ u16 value) -+{ -+ struct net_device *const dev = bus->priv; -+ struct ar231x_private *sp = netdev_priv(dev); -+ volatile ETHERNET_STRUCT *ethernet = sp->phy_regs; -+ -+ while (ethernet->mii_addr & MII_ADDR_BUSY); -+ ethernet->mii_data = value << MII_DATA_SHIFT; -+ ethernet->mii_addr = MII_ADDR(phy_addr, regnum) | MII_ADDR_WRITE; -+ -+ return 0; -+} -+ -+static int ar231x_mdiobus_reset(struct mii_bus *bus) -+{ -+ struct net_device *const dev = bus->priv; -+ -+ ar231x_reset_reg(dev); -+ -+ return 0; -+} -+ -+static int ar231x_mdiobus_probe (struct net_device *dev) -+{ -+ struct ar231x_private *const sp = netdev_priv(dev); -+ struct phy_device *phydev = NULL; -+ int phy_addr; -+ -+ /* find the first (lowest address) PHY on the current MAC's MII bus */ -+ for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) -+ if (sp->mii_bus->phy_map[phy_addr]) { -+ phydev = sp->mii_bus->phy_map[phy_addr]; -+ sp->phy = phy_addr; -+ break; /* break out with first one found */ -+ } -+ -+ if (!phydev) { -+ printk (KERN_ERR "ar231x: %s: no PHY found\n", dev->name); -+ return -1; -+ } -+ -+ /* now we are supposed to have a proper phydev, to attach to... */ -+ BUG_ON(!phydev); -+ BUG_ON(phydev->attached_dev); -+ -+ phydev = phy_connect(dev, dev_name(&phydev->dev), &ar231x_adjust_link, 0, -+ PHY_INTERFACE_MODE_MII); -+ -+ if (IS_ERR(phydev)) { -+ printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name); -+ return PTR_ERR(phydev); -+ } -+ -+ /* mask with MAC supported features */ -+ phydev->supported &= (SUPPORTED_10baseT_Half -+ | SUPPORTED_10baseT_Full -+ | SUPPORTED_100baseT_Half -+ | SUPPORTED_100baseT_Full -+ | SUPPORTED_Autoneg -+ /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */ -+ | SUPPORTED_MII -+ | SUPPORTED_TP); -+ -+ phydev->advertising = phydev->supported; -+ -+ sp->oldduplex = -1; -+ sp->phy_dev = phydev; -+ -+ printk(KERN_INFO "%s: attached PHY driver [%s] " -+ "(mii_bus:phy_addr=%s)\n", -+ dev->name, phydev->drv->name, dev_name(&phydev->dev)); -+ -+ return 0; -+} -+ -diff -Nur linux-2.6.39-rc7.orig/drivers/net/ar231x.h linux-2.6.39-rc7/drivers/net/ar231x.h ---- linux-2.6.39-rc7.orig/drivers/net/ar231x.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/drivers/net/ar231x.h 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,302 @@ -+/* -+ * ar231x.h: Linux driver for the Atheros AR231x Ethernet device. -+ * -+ * Copyright (C) 2004 by Sameer Dekate -+ * Copyright (C) 2006 Imre Kaloz -+ * Copyright (C) 2006-2009 Felix Fietkau -+ * -+ * Thanks to Atheros for providing hardware and documentation -+ * enabling me to write this driver. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ */ -+ -+#ifndef _AR2313_H_ -+#define _AR2313_H_ -+ -+#include -+#include -+#include -+#include -+ -+/* -+ * probe link timer - 5 secs -+ */ -+#define LINK_TIMER (5*HZ) -+ -+#define IS_DMA_TX_INT(X) (((X) & (DMA_STATUS_TI)) != 0) -+#define IS_DMA_RX_INT(X) (((X) & (DMA_STATUS_RI)) != 0) -+#define IS_DRIVER_OWNED(X) (((X) & (DMA_TX_OWN)) == 0) -+ -+#define AR2313_TX_TIMEOUT (HZ/4) -+ -+/* -+ * Rings -+ */ -+#define DSC_RING_ENTRIES_SIZE (AR2313_DESCR_ENTRIES * sizeof(struct desc)) -+#define DSC_NEXT(idx) ((idx + 1) & (AR2313_DESCR_ENTRIES - 1)) -+ -+#define AR2313_MBGET 2 -+#define AR2313_MBSET 3 -+#define AR2313_PCI_RECONFIG 4 -+#define AR2313_PCI_DUMP 5 -+#define AR2313_TEST_PANIC 6 -+#define AR2313_TEST_NULLPTR 7 -+#define AR2313_READ_DATA 8 -+#define AR2313_WRITE_DATA 9 -+#define AR2313_GET_VERSION 10 -+#define AR2313_TEST_HANG 11 -+#define AR2313_SYNC 12 -+ -+#define DMA_RX_ERR_CRC BIT(1) -+#define DMA_RX_ERR_DRIB BIT(2) -+#define DMA_RX_ERR_MII BIT(3) -+#define DMA_RX_EV2 BIT(5) -+#define DMA_RX_ERR_COL BIT(6) -+#define DMA_RX_LONG BIT(7) -+#define DMA_RX_LS BIT(8) /* last descriptor */ -+#define DMA_RX_FS BIT(9) /* first descriptor */ -+#define DMA_RX_MF BIT(10) /* multicast frame */ -+#define DMA_RX_ERR_RUNT BIT(11) /* runt frame */ -+#define DMA_RX_ERR_LENGTH BIT(12) /* length error */ -+#define DMA_RX_ERR_DESC BIT(14) /* descriptor error */ -+#define DMA_RX_ERROR BIT(15) /* error summary */ -+#define DMA_RX_LEN_MASK 0x3fff0000 -+#define DMA_RX_LEN_SHIFT 16 -+#define DMA_RX_FILT BIT(30) -+#define DMA_RX_OWN BIT(31) /* desc owned by DMA controller */ -+ -+#define DMA_RX1_BSIZE_MASK 0x000007ff -+#define DMA_RX1_BSIZE_SHIFT 0 -+#define DMA_RX1_CHAINED BIT(24) -+#define DMA_RX1_RER BIT(25) -+ -+#define DMA_TX_ERR_UNDER BIT(1) /* underflow error */ -+#define DMA_TX_ERR_DEFER BIT(2) /* excessive deferral */ -+#define DMA_TX_COL_MASK 0x78 -+#define DMA_TX_COL_SHIFT 3 -+#define DMA_TX_ERR_HB BIT(7) /* hearbeat failure */ -+#define DMA_TX_ERR_COL BIT(8) /* excessive collisions */ -+#define DMA_TX_ERR_LATE BIT(9) /* late collision */ -+#define DMA_TX_ERR_LINK BIT(10) /* no carrier */ -+#define DMA_TX_ERR_LOSS BIT(11) /* loss of carrier */ -+#define DMA_TX_ERR_JABBER BIT(14) /* transmit jabber timeout */ -+#define DMA_TX_ERROR BIT(15) /* frame aborted */ -+#define DMA_TX_OWN BIT(31) /* descr owned by DMA controller */ -+ -+#define DMA_TX1_BSIZE_MASK 0x000007ff -+#define DMA_TX1_BSIZE_SHIFT 0 -+#define DMA_TX1_CHAINED BIT(24) /* chained descriptors */ -+#define DMA_TX1_TER BIT(25) /* transmit end of ring */ -+#define DMA_TX1_FS BIT(29) /* first segment */ -+#define DMA_TX1_LS BIT(30) /* last segment */ -+#define DMA_TX1_IC BIT(31) /* interrupt on completion */ -+ -+#define RCVPKT_LENGTH(X) (X >> 16) /* Received pkt Length */ -+ -+#define MAC_CONTROL_RE BIT(2) /* receive enable */ -+#define MAC_CONTROL_TE BIT(3) /* transmit enable */ -+#define MAC_CONTROL_DC BIT(5) /* Deferral check */ -+#define MAC_CONTROL_ASTP BIT(8) /* Auto pad strip */ -+#define MAC_CONTROL_DRTY BIT(10) /* Disable retry */ -+#define MAC_CONTROL_DBF BIT(11) /* Disable bcast frames */ -+#define MAC_CONTROL_LCC BIT(12) /* late collision ctrl */ -+#define MAC_CONTROL_HP BIT(13) /* Hash Perfect filtering */ -+#define MAC_CONTROL_HASH BIT(14) /* Unicast hash filtering */ -+#define MAC_CONTROL_HO BIT(15) /* Hash only filtering */ -+#define MAC_CONTROL_PB BIT(16) /* Pass Bad frames */ -+#define MAC_CONTROL_IF BIT(17) /* Inverse filtering */ -+#define MAC_CONTROL_PR BIT(18) /* promiscuous mode (valid frames only) */ -+#define MAC_CONTROL_PM BIT(19) /* pass multicast */ -+#define MAC_CONTROL_F BIT(20) /* full-duplex */ -+#define MAC_CONTROL_DRO BIT(23) /* Disable Receive Own */ -+#define MAC_CONTROL_HBD BIT(28) /* heart-beat disabled (MUST BE SET) */ -+#define MAC_CONTROL_BLE BIT(30) /* big endian mode */ -+#define MAC_CONTROL_RA BIT(31) /* receive all (valid and invalid frames) */ -+ -+#define MII_ADDR_BUSY BIT(0) -+#define MII_ADDR_WRITE BIT(1) -+#define MII_ADDR_REG_SHIFT 6 -+#define MII_ADDR_PHY_SHIFT 11 -+#define MII_DATA_SHIFT 0 -+ -+#define FLOW_CONTROL_FCE BIT(1) -+ -+#define DMA_BUS_MODE_SWR BIT(0) /* software reset */ -+#define DMA_BUS_MODE_BLE BIT(7) /* big endian mode */ -+#define DMA_BUS_MODE_PBL_SHIFT 8 /* programmable burst length 32 */ -+#define DMA_BUS_MODE_DBO BIT(20) /* big-endian descriptors */ -+ -+#define DMA_STATUS_TI BIT(0) /* transmit interrupt */ -+#define DMA_STATUS_TPS BIT(1) /* transmit process stopped */ -+#define DMA_STATUS_TU BIT(2) /* transmit buffer unavailable */ -+#define DMA_STATUS_TJT BIT(3) /* transmit buffer timeout */ -+#define DMA_STATUS_UNF BIT(5) /* transmit underflow */ -+#define DMA_STATUS_RI BIT(6) /* receive interrupt */ -+#define DMA_STATUS_RU BIT(7) /* receive buffer unavailable */ -+#define DMA_STATUS_RPS BIT(8) /* receive process stopped */ -+#define DMA_STATUS_ETI BIT(10) /* early transmit interrupt */ -+#define DMA_STATUS_FBE BIT(13) /* fatal bus interrupt */ -+#define DMA_STATUS_ERI BIT(14) /* early receive interrupt */ -+#define DMA_STATUS_AIS BIT(15) /* abnormal interrupt summary */ -+#define DMA_STATUS_NIS BIT(16) /* normal interrupt summary */ -+#define DMA_STATUS_RS_SHIFT 17 /* receive process state */ -+#define DMA_STATUS_TS_SHIFT 20 /* transmit process state */ -+#define DMA_STATUS_EB_SHIFT 23 /* error bits */ -+ -+#define DMA_CONTROL_SR BIT(1) /* start receive */ -+#define DMA_CONTROL_ST BIT(13) /* start transmit */ -+#define DMA_CONTROL_SF BIT(21) /* store and forward */ -+ -+ -+typedef struct { -+ volatile unsigned int status; // OWN, Device control and status. -+ volatile unsigned int devcs; // pkt Control bits + Length -+ volatile unsigned int addr; // Current Address. -+ volatile unsigned int descr; // Next descriptor in chain. -+} ar231x_descr_t; -+ -+ -+ -+// -+// New Combo structure for Both Eth0 AND eth1 -+// -+typedef struct { -+ volatile unsigned int mac_control; /* 0x00 */ -+ volatile unsigned int mac_addr[2]; /* 0x04 - 0x08 */ -+ volatile unsigned int mcast_table[2]; /* 0x0c - 0x10 */ -+ volatile unsigned int mii_addr; /* 0x14 */ -+ volatile unsigned int mii_data; /* 0x18 */ -+ volatile unsigned int flow_control; /* 0x1c */ -+ volatile unsigned int vlan_tag; /* 0x20 */ -+ volatile unsigned int pad[7]; /* 0x24 - 0x3c */ -+ volatile unsigned int ucast_table[8]; /* 0x40-0x5c */ -+ -+} ETHERNET_STRUCT; -+ -+/******************************************************************** -+ * Interrupt controller -+ ********************************************************************/ -+ -+typedef struct { -+ volatile unsigned int wdog_control; /* 0x08 */ -+ volatile unsigned int wdog_timer; /* 0x0c */ -+ volatile unsigned int misc_status; /* 0x10 */ -+ volatile unsigned int misc_mask; /* 0x14 */ -+ volatile unsigned int global_status; /* 0x18 */ -+ volatile unsigned int reserved; /* 0x1c */ -+ volatile unsigned int reset_control; /* 0x20 */ -+} INTERRUPT; -+ -+/******************************************************************** -+ * DMA controller -+ ********************************************************************/ -+typedef struct { -+ volatile unsigned int bus_mode; /* 0x00 (CSR0) */ -+ volatile unsigned int xmt_poll; /* 0x04 (CSR1) */ -+ volatile unsigned int rcv_poll; /* 0x08 (CSR2) */ -+ volatile unsigned int rcv_base; /* 0x0c (CSR3) */ -+ volatile unsigned int xmt_base; /* 0x10 (CSR4) */ -+ volatile unsigned int status; /* 0x14 (CSR5) */ -+ volatile unsigned int control; /* 0x18 (CSR6) */ -+ volatile unsigned int intr_ena; /* 0x1c (CSR7) */ -+ volatile unsigned int rcv_missed; /* 0x20 (CSR8) */ -+ volatile unsigned int reserved[11]; /* 0x24-0x4c (CSR9-19) */ -+ volatile unsigned int cur_tx_buf_addr; /* 0x50 (CSR20) */ -+ volatile unsigned int cur_rx_buf_addr; /* 0x50 (CSR21) */ -+} DMA; -+ -+/* -+ * Struct private for the Sibyte. -+ * -+ * Elements are grouped so variables used by the tx handling goes -+ * together, and will go into the same cache lines etc. in order to -+ * avoid cache line contention between the rx and tx handling on SMP. -+ * -+ * Frequently accessed variables are put at the beginning of the -+ * struct to help the compiler generate better/shorter code. -+ */ -+struct ar231x_private { -+ struct net_device *dev; -+ int version; -+ u32 mb[2]; -+ -+ volatile ETHERNET_STRUCT *phy_regs; -+ volatile ETHERNET_STRUCT *eth_regs; -+ volatile DMA *dma_regs; -+ volatile u32 *int_regs; -+ struct ar231x_eth *cfg; -+ -+ spinlock_t lock; /* Serialise access to device */ -+ -+ /* -+ * RX and TX descriptors, must be adjacent -+ */ -+ ar231x_descr_t *rx_ring; -+ ar231x_descr_t *tx_ring; -+ -+ -+ struct sk_buff **rx_skb; -+ struct sk_buff **tx_skb; -+ -+ /* -+ * RX elements -+ */ -+ u32 rx_skbprd; -+ u32 cur_rx; -+ -+ /* -+ * TX elements -+ */ -+ u32 tx_prd; -+ u32 tx_csm; -+ -+ /* -+ * Misc elements -+ */ -+ char name[48]; -+ struct { -+ u32 address; -+ u32 length; -+ char *mapping; -+ } desc; -+ -+ -+ struct timer_list link_timer; -+ unsigned short phy; /* merlot phy = 1, samsung phy = 0x1f */ -+ unsigned short mac; -+ unsigned short link; /* 0 - link down, 1 - link up */ -+ u16 phyData; -+ -+ struct tasklet_struct rx_tasklet; -+ int unloading; -+ -+ struct phy_device *phy_dev; -+ struct mii_bus *mii_bus; -+ int oldduplex; -+}; -+ -+ -+/* -+ * Prototypes -+ */ -+static int ar231x_init(struct net_device *dev); -+#ifdef TX_TIMEOUT -+static void ar231x_tx_timeout(struct net_device *dev); -+#endif -+static int ar231x_restart(struct net_device *dev); -+static void ar231x_load_rx_ring(struct net_device *dev, int bufs); -+static irqreturn_t ar231x_interrupt(int irq, void *dev_id); -+static int ar231x_open(struct net_device *dev); -+static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev); -+static int ar231x_close(struct net_device *dev); -+static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr, -+ int cmd); -+static void ar231x_init_cleanup(struct net_device *dev); -+static int ar231x_setup_timer(struct net_device *dev); -+static void ar231x_link_timer_fn(unsigned long data); -+static void ar231x_check_link(struct net_device *dev); -+#endif /* _AR2313_H_ */ -diff -Nur linux-2.6.39-rc7.orig/drivers/watchdog/Kconfig linux-2.6.39-rc7/drivers/watchdog/Kconfig ---- linux-2.6.39-rc7.orig/drivers/watchdog/Kconfig 2011-05-10 04:33:54.000000000 +0200 -+++ linux-2.6.39-rc7/drivers/watchdog/Kconfig 2011-05-15 21:34:57.000000000 +0200 -@@ -990,6 +990,12 @@ - To compile this driver as a loadable module, choose M here. - The module will be called bcm63xx_wdt. - -+config ATHEROS_WDT -+ tristate "Atheros wisoc Watchdog Timer" -+ depends on ATHEROS_AR231X -+ help -+ Hardware driver for the Atheros wisoc Watchdog Timer. -+ - # PARISC Architecture - - # POWERPC Architecture -diff -Nur linux-2.6.39-rc7.orig/drivers/watchdog/Makefile linux-2.6.39-rc7/drivers/watchdog/Makefile ---- linux-2.6.39-rc7.orig/drivers/watchdog/Makefile 2011-05-10 04:33:54.000000000 +0200 -+++ linux-2.6.39-rc7/drivers/watchdog/Makefile 2011-05-15 21:34:57.000000000 +0200 -@@ -120,6 +120,7 @@ - obj-$(CONFIG_PNX833X_WDT) += pnx833x_wdt.o - obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o - obj-$(CONFIG_AR7_WDT) += ar7_wdt.o -+obj-$(CONFIG_ATHEROS_WDT) += ar2315-wtd.o - obj-$(CONFIG_TXX9_WDT) += txx9wdt.o - obj-$(CONFIG_OCTEON_WDT) += octeon-wdt.o - octeon-wdt-y := octeon-wdt-main.o octeon-wdt-nmi.o -diff -Nur linux-2.6.39-rc7.orig/drivers/watchdog/ar2315-wtd.c linux-2.6.39-rc7/drivers/watchdog/ar2315-wtd.c ---- linux-2.6.39-rc7.orig/drivers/watchdog/ar2315-wtd.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/drivers/watchdog/ar2315-wtd.c 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,200 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ * -+ * Copyright (C) 2008 John Crispin -+ * Based on EP93xx and ifxmips wdt driver -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define CLOCK_RATE 40000000 -+#define HEARTBEAT(x) (x < 1 || x > 90)?(20):(x) -+ -+static int wdt_timeout = 20; -+static int started = 0; -+static int in_use = 0; -+ -+static void -+ar2315_wdt_enable(void) -+{ -+ ar231x_write_reg(AR2315_WD, wdt_timeout * CLOCK_RATE); -+ ar231x_write_reg(AR2315_ISR, 0x80); -+} -+ -+static ssize_t -+ar2315_wdt_write(struct file *file, const char __user *data, size_t len, loff_t *ppos) -+{ -+ if(len) -+ ar2315_wdt_enable(); -+ return len; -+} -+ -+static int -+ar2315_wdt_open(struct inode *inode, struct file *file) -+{ -+ if(in_use) -+ return -EBUSY; -+ ar2315_wdt_enable(); -+ in_use = started = 1; -+ return nonseekable_open(inode, file); -+} -+ -+static int -+ar2315_wdt_release(struct inode *inode, struct file *file) -+{ -+ in_use = 0; -+ return 0; -+} -+ -+static irqreturn_t -+ar2315_wdt_interrupt(int irq, void *dev_id) -+{ -+ if(started) -+ { -+ printk(KERN_CRIT "watchdog expired, rebooting system\n"); -+ emergency_restart(); -+ } else { -+ ar231x_write_reg(AR2315_WDC, 0); -+ ar231x_write_reg(AR2315_WD, 0); -+ ar231x_write_reg(AR2315_ISR, 0x80); -+ } -+ return IRQ_HANDLED; -+} -+ -+static struct watchdog_info ident = { -+ .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, -+ .identity = "ar2315 Watchdog", -+}; -+ -+static int -+ar2315_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) -+{ -+ int new_wdt_timeout; -+ int ret = -ENOIOCTLCMD; -+ -+ switch(cmd) -+ { -+ case WDIOC_GETSUPPORT: -+ ret = copy_to_user((struct watchdog_info __user *)arg, &ident, sizeof(ident)) ? -EFAULT : 0; -+ break; -+ -+ case WDIOC_KEEPALIVE: -+ ar2315_wdt_enable(); -+ ret = 0; -+ break; -+ -+ case WDIOC_SETTIMEOUT: -+ if((ret = get_user(new_wdt_timeout, (int __user *)arg))) -+ break; -+ wdt_timeout = HEARTBEAT(new_wdt_timeout); -+ ar2315_wdt_enable(); -+ break; -+ -+ case WDIOC_GETTIMEOUT: -+ ret = put_user(wdt_timeout, (int __user *)arg); -+ break; -+ } -+ return ret; -+} -+ -+static struct file_operations ar2315_wdt_fops = { -+ .owner = THIS_MODULE, -+ .llseek = no_llseek, -+ .write = ar2315_wdt_write, -+ .unlocked_ioctl = ar2315_wdt_ioctl, -+ .open = ar2315_wdt_open, -+ .release = ar2315_wdt_release, -+}; -+ -+static struct miscdevice ar2315_wdt_miscdev = { -+ .minor = WATCHDOG_MINOR, -+ .name = "watchdog", -+ .fops = &ar2315_wdt_fops, -+}; -+ -+static int -+ar2315_wdt_probe(struct platform_device *dev) -+{ -+ int ret = 0; -+ -+ ar2315_wdt_enable(); -+ ret = request_irq(AR531X_MISC_IRQ_WATCHDOG, ar2315_wdt_interrupt, IRQF_DISABLED, "ar2315_wdt", NULL); -+ if(ret) -+ { -+ printk(KERN_ERR "ar2315wdt: failed to register inetrrupt\n"); -+ goto out; -+ } -+ -+ ret = misc_register(&ar2315_wdt_miscdev); -+ if(ret) -+ printk(KERN_ERR "ar2315wdt: failed to register miscdev\n"); -+ -+out: -+ return ret; -+} -+ -+static int -+ar2315_wdt_remove(struct platform_device *dev) -+{ -+ misc_deregister(&ar2315_wdt_miscdev); -+ free_irq(AR531X_MISC_IRQ_WATCHDOG, NULL); -+ return 0; -+} -+ -+static struct platform_driver ar2315_wdt_driver = { -+ .probe = ar2315_wdt_probe, -+ .remove = ar2315_wdt_remove, -+ .driver = { -+ .name = "ar2315_wdt", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init -+init_ar2315_wdt(void) -+{ -+ int ret = platform_driver_register(&ar2315_wdt_driver); -+ if(ret) -+ printk(KERN_INFO "ar2315_wdt: error registering platfom driver!"); -+ return ret; -+} -+ -+static void __exit -+exit_ar2315_wdt(void) -+{ -+ platform_driver_unregister(&ar2315_wdt_driver); -+} -+ -+module_init(init_ar2315_wdt); -+module_exit(exit_ar2315_wdt); diff --git a/target/linux/patches/3.0.4/gemalto.patch b/target/linux/patches/3.0.4/gemalto.patch deleted file mode 100644 index f3c223b5e..000000000 --- a/target/linux/patches/3.0.4/gemalto.patch +++ /dev/null @@ -1,11 +0,0 @@ -diff -Nur linux-2.6.36.orig/drivers/tty/serial/serial_cs.c linux-2.6.36/drivers/serial/serial_cs.c ---- linux-2.6.36.orig/drivers/tty/serial/serial_cs.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/drivers/tty/serial/serial_cs.c 2010-12-13 23:03:40.000000000 +0100 -@@ -794,6 +794,7 @@ - PCMCIA_DEVICE_MANF_CARD(0x0137, 0x0025), - PCMCIA_DEVICE_MANF_CARD(0x0137, 0x0045), - PCMCIA_DEVICE_MANF_CARD(0x0137, 0x0052), -+ PCMCIA_DEVICE_MANF_CARD(0x0157, 0x0100), /* Gemalto SCR */ - PCMCIA_DEVICE_MANF_CARD(0x016c, 0x0006), /* Psion 56K+Fax */ - PCMCIA_DEVICE_MANF_CARD(0x0200, 0x0001), /* MultiMobile */ - PCMCIA_DEVICE_PROD_ID134("ADV", "TECH", "COMpad-32/85", 0x67459937, 0x916d02ba, 0x8fbe92ae), diff --git a/target/linux/patches/3.0.4/mips-malta.patch b/target/linux/patches/3.0.4/mips-malta.patch deleted file mode 100644 index cc8789dca..000000000 --- a/target/linux/patches/3.0.4/mips-malta.patch +++ /dev/null @@ -1,135 +0,0 @@ -http://lkml.indiana.edu/hypermail/linux/kernel/1105.3/02199.html - -diff -Nur linux-2.6.39.orig/arch/mips/include/asm/smp-ops.h linux-2.6.39/arch/mips/include/asm/smp-ops.h ---- linux-2.6.39.orig/arch/mips/include/asm/smp-ops.h 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/arch/mips/include/asm/smp-ops.h 2011-08-29 04:39:03.360480881 +0200 -@@ -56,8 +56,43 @@ - - #endif /* !CONFIG_SMP */ - --extern struct plat_smp_ops up_smp_ops; --extern struct plat_smp_ops cmp_smp_ops; --extern struct plat_smp_ops vsmp_smp_ops; -+static inline int register_up_smp_ops(void) -+{ -+#ifdef CONFIG_SMP_UP -+ extern struct plat_smp_ops up_smp_ops; -+ -+ register_smp_ops(&up_smp_ops); -+ -+ return 0; -+#else -+ return -ENODEV; -+#endif -+} -+ -+static inline int register_cmp_smp_ops(void) -+{ -+#ifdef CONFIG_MIPS_CMP -+ extern struct plat_smp_ops cmp_smp_ops; -+ -+ register_smp_ops(&cmp_smp_ops); -+ -+ return 0; -+#else -+ return -ENODEV; -+#endif -+} -+ -+static inline int register_vsmp_smp_ops(void) -+{ -+#ifdef CONFIG_MIPS_MT_SMP -+ extern struct plat_smp_ops vsmp_smp_ops; -+ -+ register_smp_ops(&vsmp_smp_ops); -+ -+ return 0; -+#else -+ return -ENODEV; -+#endif -+} - - #endif /* __ASM_SMP_OPS_H */ -diff -Nur linux-2.6.39.orig/arch/mips/mipssim/sim_setup.c linux-2.6.39/arch/mips/mipssim/sim_setup.c ---- linux-2.6.39.orig/arch/mips/mipssim/sim_setup.c 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/arch/mips/mipssim/sim_setup.c 2011-08-29 04:39:03.390480572 +0200 -@@ -59,18 +59,17 @@ - - prom_meminit(); - --#ifdef CONFIG_MIPS_MT_SMP -- if (cpu_has_mipsmt) -- register_smp_ops(&vsmp_smp_ops); -- else -- register_smp_ops(&up_smp_ops); --#endif -+ if (cpu_has_mipsmt) { -+ if (!register_vsmp_smp_ops()) -+ return; -+ - #ifdef CONFIG_MIPS_MT_SMTC -- if (cpu_has_mipsmt) - register_smp_ops(&ssmtc_smp_ops); -- else -- register_smp_ops(&up_smp_ops); -+ return; - #endif -+ } -+ -+ register_up_smp_ops(); - } - - static void __init serial_init(void) -diff -Nur linux-2.6.39.orig/arch/mips/mti-malta/malta-init.c linux-2.6.39/arch/mips/mti-malta/malta-init.c ---- linux-2.6.39.orig/arch/mips/mti-malta/malta-init.c 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/arch/mips/mti-malta/malta-init.c 2011-08-29 04:39:03.700480601 +0200 -@@ -29,6 +29,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -358,15 +359,14 @@ - #ifdef CONFIG_SERIAL_8250_CONSOLE - console_config(); - #endif --#ifdef CONFIG_MIPS_CMP - /* Early detection of CMP support */ - if (gcmp_probe(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ)) -- register_smp_ops(&cmp_smp_ops); -- else --#endif --#ifdef CONFIG_MIPS_MT_SMP -- register_smp_ops(&vsmp_smp_ops); --#endif -+ if (!register_cmp_smp_ops()) -+ return; -+ -+ if (!register_vsmp_smp_ops()) -+ return; -+ - #ifdef CONFIG_MIPS_MT_SMTC - register_smp_ops(&msmtc_smp_ops); - #endif -diff -Nur linux-2.6.39.orig/arch/mips/pmc-sierra/msp71xx/msp_setup.c linux-2.6.39/arch/mips/pmc-sierra/msp71xx/msp_setup.c ---- linux-2.6.39.orig/arch/mips/pmc-sierra/msp71xx/msp_setup.c 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/arch/mips/pmc-sierra/msp71xx/msp_setup.c 2011-08-29 04:39:03.790480302 +0200 -@@ -228,13 +228,11 @@ - */ - msp_serial_setup(); - --#ifdef CONFIG_MIPS_MT_SMP -- register_smp_ops(&vsmp_smp_ops); --#endif -- -+ if (register_vsmp_smp_ops()) { - #ifdef CONFIG_MIPS_MT_SMTC -- register_smp_ops(&msp_smtc_smp_ops); -+ register_smp_ops(&msp_smtc_smp_ops); - #endif -+ } - - #ifdef CONFIG_PMCTWILED - /* diff --git a/target/linux/patches/3.0.4/mmc-host.patch b/target/linux/patches/3.0.4/mmc-host.patch deleted file mode 100644 index 3d0e37add..000000000 --- a/target/linux/patches/3.0.4/mmc-host.patch +++ /dev/null @@ -1,36 +0,0 @@ -diff -Nur linux-2.6.39-rc6.orig/drivers/mmc/host/Kconfig linux-2.6.39-rc6/drivers/mmc/host/Kconfig ---- linux-2.6.39-rc6.orig/drivers/mmc/host/Kconfig 2011-05-04 04:59:13.000000000 +0200 -+++ linux-2.6.39-rc6/drivers/mmc/host/Kconfig 2011-05-10 23:39:01.000000000 +0200 -@@ -253,13 +253,6 @@ - - If unsure, say N. - --choice -- prompt "Atmel SD/MMC Driver" -- depends on AVR32 || ARCH_AT91 -- default MMC_ATMELMCI if AVR32 -- help -- Choose which driver to use for the Atmel MCI Silicon -- - config MMC_AT91 - tristate "AT91 SD/MMC Card Interface support" - depends on ARCH_AT91 -@@ -268,18 +261,6 @@ - - If unsure, say N. - --config MMC_ATMELMCI -- tristate "Atmel Multimedia Card Interface support" -- depends on AVR32 || ARCH_AT91 -- help -- This selects the Atmel Multimedia Card Interface driver. If -- you have an AT32 (AVR32) or AT91 platform with a Multimedia -- Card slot, say Y or M here. -- -- If unsure, say N. -- --endchoice -- - config MMC_ATMELMCI_DMA - bool "Atmel MCI DMA support (EXPERIMENTAL)" - depends on MMC_ATMELMCI && (AVR32 || ARCH_AT91SAM9G45) && DMA_ENGINE && EXPERIMENTAL diff --git a/target/linux/patches/3.0.4/non-static.patch b/target/linux/patches/3.0.4/non-static.patch deleted file mode 100644 index a967703d0..000000000 --- a/target/linux/patches/3.0.4/non-static.patch +++ /dev/null @@ -1,33 +0,0 @@ -diff -Nur linux-2.6.39-rc6.orig/fs/namei.c linux-2.6.39-rc6/fs/namei.c ---- linux-2.6.39-rc6.orig/fs/namei.c 2011-05-04 04:59:13.000000000 +0200 -+++ linux-2.6.39-rc6/fs/namei.c 2011-05-05 11:30:14.000000000 +0200 -@@ -1769,7 +1769,7 @@ - * needs parent already locked. Doesn't follow mounts. - * SMP-safe. - */ --static struct dentry *lookup_hash(struct nameidata *nd) -+struct dentry *lookup_hash(struct nameidata *nd) - { - return __lookup_hash(&nd->last, nd->path.dentry, nd); - } -diff -Nur linux-2.6.39-rc6.orig/fs/splice.c linux-2.6.39-rc6/fs/splice.c ---- linux-2.6.39-rc6.orig/fs/splice.c 2011-05-04 04:59:13.000000000 +0200 -+++ linux-2.6.39-rc6/fs/splice.c 2011-05-05 11:31:04.000000000 +0200 -@@ -1081,7 +1081,7 @@ - /* - * Attempt to initiate a splice from pipe to file. - */ --static long do_splice_from(struct pipe_inode_info *pipe, struct file *out, -+long do_splice_from(struct pipe_inode_info *pipe, struct file *out, - loff_t *ppos, size_t len, unsigned int flags) - { - ssize_t (*splice_write)(struct pipe_inode_info *, struct file *, -@@ -1109,7 +1109,7 @@ - /* - * Attempt to initiate a splice from a file to a pipe. - */ --static long do_splice_to(struct file *in, loff_t *ppos, -+long do_splice_to(struct file *in, loff_t *ppos, - struct pipe_inode_info *pipe, size_t len, - unsigned int flags) - { diff --git a/target/linux/patches/3.0.4/ocf-20110720.patch b/target/linux/patches/3.0.4/ocf-20110720.patch deleted file mode 100644 index b5a257324..000000000 --- a/target/linux/patches/3.0.4/ocf-20110720.patch +++ /dev/null @@ -1,99170 +0,0 @@ -diff -Nur linux-3.0.4.orig/crypto/Kconfig linux-3.0.4/crypto/Kconfig ---- linux-3.0.4.orig/crypto/Kconfig 2011-08-29 22:56:30.000000000 +0200 -+++ linux-3.0.4/crypto/Kconfig 2011-10-17 04:36:27.356574299 +0200 -@@ -860,3 +860,6 @@ - source "drivers/crypto/Kconfig" - - endif # if CRYPTO -+ -+source "crypto/ocf/Kconfig" -+ -diff -Nur linux-3.0.4.orig/crypto/Kconfig.orig linux-3.0.4/crypto/Kconfig.orig ---- linux-3.0.4.orig/crypto/Kconfig.orig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/Kconfig.orig 2011-08-29 22:56:30.000000000 +0200 -@@ -0,0 +1,862 @@ -+# -+# Generic algorithms support -+# -+config XOR_BLOCKS -+ tristate -+ -+# -+# async_tx api: hardware offloaded memory transfer/transform support -+# -+source "crypto/async_tx/Kconfig" -+ -+# -+# Cryptographic API Configuration -+# -+menuconfig CRYPTO -+ tristate "Cryptographic API" -+ help -+ This option provides the core Cryptographic API. -+ -+if CRYPTO -+ -+comment "Crypto core or helper" -+ -+config CRYPTO_FIPS -+ bool "FIPS 200 compliance" -+ depends on CRYPTO_ANSI_CPRNG && !CRYPTO_MANAGER_DISABLE_TESTS -+ help -+ This options enables the fips boot option which is -+ required if you want to system to operate in a FIPS 200 -+ certification. You should say no unless you know what -+ this is. -+ -+config CRYPTO_ALGAPI -+ tristate -+ select CRYPTO_ALGAPI2 -+ help -+ This option provides the API for cryptographic algorithms. -+ -+config CRYPTO_ALGAPI2 -+ tristate -+ -+config CRYPTO_AEAD -+ tristate -+ select CRYPTO_AEAD2 -+ select CRYPTO_ALGAPI -+ -+config CRYPTO_AEAD2 -+ tristate -+ select CRYPTO_ALGAPI2 -+ -+config CRYPTO_BLKCIPHER -+ tristate -+ select CRYPTO_BLKCIPHER2 -+ select CRYPTO_ALGAPI -+ -+config CRYPTO_BLKCIPHER2 -+ tristate -+ select CRYPTO_ALGAPI2 -+ select CRYPTO_RNG2 -+ select CRYPTO_WORKQUEUE -+ -+config CRYPTO_HASH -+ tristate -+ select CRYPTO_HASH2 -+ select CRYPTO_ALGAPI -+ -+config CRYPTO_HASH2 -+ tristate -+ select CRYPTO_ALGAPI2 -+ -+config CRYPTO_RNG -+ tristate -+ select CRYPTO_RNG2 -+ select CRYPTO_ALGAPI -+ -+config CRYPTO_RNG2 -+ tristate -+ select CRYPTO_ALGAPI2 -+ -+config CRYPTO_PCOMP -+ tristate -+ select CRYPTO_PCOMP2 -+ select CRYPTO_ALGAPI -+ -+config CRYPTO_PCOMP2 -+ tristate -+ select CRYPTO_ALGAPI2 -+ -+config CRYPTO_MANAGER -+ tristate "Cryptographic algorithm manager" -+ select CRYPTO_MANAGER2 -+ help -+ Create default cryptographic template instantiations such as -+ cbc(aes). -+ -+config CRYPTO_MANAGER2 -+ def_tristate CRYPTO_MANAGER || (CRYPTO_MANAGER!=n && CRYPTO_ALGAPI=y) -+ select CRYPTO_AEAD2 -+ select CRYPTO_HASH2 -+ select CRYPTO_BLKCIPHER2 -+ select CRYPTO_PCOMP2 -+ -+config CRYPTO_MANAGER_DISABLE_TESTS -+ bool "Disable run-time self tests" -+ default y -+ depends on CRYPTO_MANAGER2 -+ help -+ Disable run-time self tests that normally take place at -+ algorithm registration. -+ -+config CRYPTO_GF128MUL -+ tristate "GF(2^128) multiplication functions (EXPERIMENTAL)" -+ help -+ Efficient table driven implementation of multiplications in the -+ field GF(2^128). This is needed by some cypher modes. This -+ option will be selected automatically if you select such a -+ cipher mode. Only select this option by hand if you expect to load -+ an external module that requires these functions. -+ -+config CRYPTO_NULL -+ tristate "Null algorithms" -+ select CRYPTO_ALGAPI -+ select CRYPTO_BLKCIPHER -+ select CRYPTO_HASH -+ help -+ These are 'Null' algorithms, used by IPsec, which do nothing. -+ -+config CRYPTO_PCRYPT -+ tristate "Parallel crypto engine (EXPERIMENTAL)" -+ depends on SMP && EXPERIMENTAL -+ select PADATA -+ select CRYPTO_MANAGER -+ select CRYPTO_AEAD -+ help -+ This converts an arbitrary crypto algorithm into a parallel -+ algorithm that executes in kernel threads. -+ -+config CRYPTO_WORKQUEUE -+ tristate -+ -+config CRYPTO_CRYPTD -+ tristate "Software async crypto daemon" -+ select CRYPTO_BLKCIPHER -+ select CRYPTO_HASH -+ select CRYPTO_MANAGER -+ select CRYPTO_WORKQUEUE -+ help -+ This is a generic software asynchronous crypto daemon that -+ converts an arbitrary synchronous software crypto algorithm -+ into an asynchronous algorithm that executes in a kernel thread. -+ -+config CRYPTO_AUTHENC -+ tristate "Authenc support" -+ select CRYPTO_AEAD -+ select CRYPTO_BLKCIPHER -+ select CRYPTO_MANAGER -+ select CRYPTO_HASH -+ help -+ Authenc: Combined mode wrapper for IPsec. -+ This is required for IPSec. -+ -+config CRYPTO_TEST -+ tristate "Testing module" -+ depends on m -+ select CRYPTO_MANAGER -+ help -+ Quick & dirty crypto test module. -+ -+comment "Authenticated Encryption with Associated Data" -+ -+config CRYPTO_CCM -+ tristate "CCM support" -+ select CRYPTO_CTR -+ select CRYPTO_AEAD -+ help -+ Support for Counter with CBC MAC. Required for IPsec. -+ -+config CRYPTO_GCM -+ tristate "GCM/GMAC support" -+ select CRYPTO_CTR -+ select CRYPTO_AEAD -+ select CRYPTO_GHASH -+ help -+ Support for Galois/Counter Mode (GCM) and Galois Message -+ Authentication Code (GMAC). Required for IPSec. -+ -+config CRYPTO_SEQIV -+ tristate "Sequence Number IV Generator" -+ select CRYPTO_AEAD -+ select CRYPTO_BLKCIPHER -+ select CRYPTO_RNG -+ help -+ This IV generator generates an IV based on a sequence number by -+ xoring it with a salt. This algorithm is mainly useful for CTR -+ -+comment "Block modes" -+ -+config CRYPTO_CBC -+ tristate "CBC support" -+ select CRYPTO_BLKCIPHER -+ select CRYPTO_MANAGER -+ help -+ CBC: Cipher Block Chaining mode -+ This block cipher algorithm is required for IPSec. -+ -+config CRYPTO_CTR -+ tristate "CTR support" -+ select CRYPTO_BLKCIPHER -+ select CRYPTO_SEQIV -+ select CRYPTO_MANAGER -+ help -+ CTR: Counter mode -+ This block cipher algorithm is required for IPSec. -+ -+config CRYPTO_CTS -+ tristate "CTS support" -+ select CRYPTO_BLKCIPHER -+ help -+ CTS: Cipher Text Stealing -+ This is the Cipher Text Stealing mode as described by -+ Section 8 of rfc2040 and referenced by rfc3962. -+ (rfc3962 includes errata information in its Appendix A) -+ This mode is required for Kerberos gss mechanism support -+ for AES encryption. -+ -+config CRYPTO_ECB -+ tristate "ECB support" -+ select CRYPTO_BLKCIPHER -+ select CRYPTO_MANAGER -+ help -+ ECB: Electronic CodeBook mode -+ This is the simplest block cipher algorithm. It simply encrypts -+ the input block by block. -+ -+config CRYPTO_LRW -+ tristate "LRW support (EXPERIMENTAL)" -+ depends on EXPERIMENTAL -+ select CRYPTO_BLKCIPHER -+ select CRYPTO_MANAGER -+ select CRYPTO_GF128MUL -+ help -+ LRW: Liskov Rivest Wagner, a tweakable, non malleable, non movable -+ narrow block cipher mode for dm-crypt. Use it with cipher -+ specification string aes-lrw-benbi, the key must be 256, 320 or 384. -+ The first 128, 192 or 256 bits in the key are used for AES and the -+ rest is used to tie each cipher block to its logical position. -+ -+config CRYPTO_PCBC -+ tristate "PCBC support" -+ select CRYPTO_BLKCIPHER -+ select CRYPTO_MANAGER -+ help -+ PCBC: Propagating Cipher Block Chaining mode -+ This block cipher algorithm is required for RxRPC. -+ -+config CRYPTO_XTS -+ tristate "XTS support (EXPERIMENTAL)" -+ depends on EXPERIMENTAL -+ select CRYPTO_BLKCIPHER -+ select CRYPTO_MANAGER -+ select CRYPTO_GF128MUL -+ help -+ XTS: IEEE1619/D16 narrow block cipher use with aes-xts-plain, -+ key size 256, 384 or 512 bits. This implementation currently -+ can't handle a sectorsize which is not a multiple of 16 bytes. -+ -+comment "Hash modes" -+ -+config CRYPTO_HMAC -+ tristate "HMAC support" -+ select CRYPTO_HASH -+ select CRYPTO_MANAGER -+ help -+ HMAC: Keyed-Hashing for Message Authentication (RFC2104). -+ This is required for IPSec. -+ -+config CRYPTO_XCBC -+ tristate "XCBC support" -+ depends on EXPERIMENTAL -+ select CRYPTO_HASH -+ select CRYPTO_MANAGER -+ help -+ XCBC: Keyed-Hashing with encryption algorithm -+ http://www.ietf.org/rfc/rfc3566.txt -+ http://csrc.nist.gov/encryption/modes/proposedmodes/ -+ xcbc-mac/xcbc-mac-spec.pdf -+ -+config CRYPTO_VMAC -+ tristate "VMAC support" -+ depends on EXPERIMENTAL -+ select CRYPTO_HASH -+ select CRYPTO_MANAGER -+ help -+ VMAC is a message authentication algorithm designed for -+ very high speed on 64-bit architectures. -+ -+ See also: -+ -+ -+comment "Digest" -+ -+config CRYPTO_CRC32C -+ tristate "CRC32c CRC algorithm" -+ select CRYPTO_HASH -+ help -+ Castagnoli, et al Cyclic Redundancy-Check Algorithm. Used -+ by iSCSI for header and data digests and by others. -+ See Castagnoli93. Module will be crc32c. -+ -+config CRYPTO_CRC32C_INTEL -+ tristate "CRC32c INTEL hardware acceleration" -+ depends on X86 -+ select CRYPTO_HASH -+ help -+ In Intel processor with SSE4.2 supported, the processor will -+ support CRC32C implementation using hardware accelerated CRC32 -+ instruction. This option will create 'crc32c-intel' module, -+ which will enable any routine to use the CRC32 instruction to -+ gain performance compared with software implementation. -+ Module will be crc32c-intel. -+ -+config CRYPTO_GHASH -+ tristate "GHASH digest algorithm" -+ select CRYPTO_SHASH -+ select CRYPTO_GF128MUL -+ help -+ GHASH is message digest algorithm for GCM (Galois/Counter Mode). -+ -+config CRYPTO_MD4 -+ tristate "MD4 digest algorithm" -+ select CRYPTO_HASH -+ help -+ MD4 message digest algorithm (RFC1320). -+ -+config CRYPTO_MD5 -+ tristate "MD5 digest algorithm" -+ select CRYPTO_HASH -+ help -+ MD5 message digest algorithm (RFC1321). -+ -+config CRYPTO_MICHAEL_MIC -+ tristate "Michael MIC keyed digest algorithm" -+ select CRYPTO_HASH -+ help -+ Michael MIC is used for message integrity protection in TKIP -+ (IEEE 802.11i). This algorithm is required for TKIP, but it -+ should not be used for other purposes because of the weakness -+ of the algorithm. -+ -+config CRYPTO_RMD128 -+ tristate "RIPEMD-128 digest algorithm" -+ select CRYPTO_HASH -+ help -+ RIPEMD-128 (ISO/IEC 10118-3:2004). -+ -+ RIPEMD-128 is a 128-bit cryptographic hash function. It should only -+ to be used as a secure replacement for RIPEMD. For other use cases -+ RIPEMD-160 should be used. -+ -+ Developed by Hans Dobbertin, Antoon Bosselaers and Bart Preneel. -+ See -+ -+config CRYPTO_RMD160 -+ tristate "RIPEMD-160 digest algorithm" -+ select CRYPTO_HASH -+ help -+ RIPEMD-160 (ISO/IEC 10118-3:2004). -+ -+ RIPEMD-160 is a 160-bit cryptographic hash function. It is intended -+ to be used as a secure replacement for the 128-bit hash functions -+ MD4, MD5 and it's predecessor RIPEMD -+ (not to be confused with RIPEMD-128). -+ -+ It's speed is comparable to SHA1 and there are no known attacks -+ against RIPEMD-160. -+ -+ Developed by Hans Dobbertin, Antoon Bosselaers and Bart Preneel. -+ See -+ -+config CRYPTO_RMD256 -+ tristate "RIPEMD-256 digest algorithm" -+ select CRYPTO_HASH -+ help -+ RIPEMD-256 is an optional extension of RIPEMD-128 with a -+ 256 bit hash. It is intended for applications that require -+ longer hash-results, without needing a larger security level -+ (than RIPEMD-128). -+ -+ Developed by Hans Dobbertin, Antoon Bosselaers and Bart Preneel. -+ See -+ -+config CRYPTO_RMD320 -+ tristate "RIPEMD-320 digest algorithm" -+ select CRYPTO_HASH -+ help -+ RIPEMD-320 is an optional extension of RIPEMD-160 with a -+ 320 bit hash. It is intended for applications that require -+ longer hash-results, without needing a larger security level -+ (than RIPEMD-160). -+ -+ Developed by Hans Dobbertin, Antoon Bosselaers and Bart Preneel. -+ See -+ -+config CRYPTO_SHA1 -+ tristate "SHA1 digest algorithm" -+ select CRYPTO_HASH -+ help -+ SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2). -+ -+config CRYPTO_SHA256 -+ tristate "SHA224 and SHA256 digest algorithm" -+ select CRYPTO_HASH -+ help -+ SHA256 secure hash standard (DFIPS 180-2). -+ -+ This version of SHA implements a 256 bit hash with 128 bits of -+ security against collision attacks. -+ -+ This code also includes SHA-224, a 224 bit hash with 112 bits -+ of security against collision attacks. -+ -+config CRYPTO_SHA512 -+ tristate "SHA384 and SHA512 digest algorithms" -+ select CRYPTO_HASH -+ help -+ SHA512 secure hash standard (DFIPS 180-2). -+ -+ This version of SHA implements a 512 bit hash with 256 bits of -+ security against collision attacks. -+ -+ This code also includes SHA-384, a 384 bit hash with 192 bits -+ of security against collision attacks. -+ -+config CRYPTO_TGR192 -+ tristate "Tiger digest algorithms" -+ select CRYPTO_HASH -+ help -+ Tiger hash algorithm 192, 160 and 128-bit hashes -+ -+ Tiger is a hash function optimized for 64-bit processors while -+ still having decent performance on 32-bit processors. -+ Tiger was developed by Ross Anderson and Eli Biham. -+ -+ See also: -+ . -+ -+config CRYPTO_WP512 -+ tristate "Whirlpool digest algorithms" -+ select CRYPTO_HASH -+ help -+ Whirlpool hash algorithm 512, 384 and 256-bit hashes -+ -+ Whirlpool-512 is part of the NESSIE cryptographic primitives. -+ Whirlpool will be part of the ISO/IEC 10118-3:2003(E) standard -+ -+ See also: -+ -+ -+config CRYPTO_GHASH_CLMUL_NI_INTEL -+ tristate "GHASH digest algorithm (CLMUL-NI accelerated)" -+ depends on (X86 || UML_X86) && 64BIT -+ select CRYPTO_SHASH -+ select CRYPTO_CRYPTD -+ help -+ GHASH is message digest algorithm for GCM (Galois/Counter Mode). -+ The implementation is accelerated by CLMUL-NI of Intel. -+ -+comment "Ciphers" -+ -+config CRYPTO_AES -+ tristate "AES cipher algorithms" -+ select CRYPTO_ALGAPI -+ help -+ AES cipher algorithms (FIPS-197). AES uses the Rijndael -+ algorithm. -+ -+ Rijndael appears to be consistently a very good performer in -+ both hardware and software across a wide range of computing -+ environments regardless of its use in feedback or non-feedback -+ modes. Its key setup time is excellent, and its key agility is -+ good. Rijndael's very low memory requirements make it very well -+ suited for restricted-space environments, in which it also -+ demonstrates excellent performance. Rijndael's operations are -+ among the easiest to defend against power and timing attacks. -+ -+ The AES specifies three key sizes: 128, 192 and 256 bits -+ -+ See for more information. -+ -+config CRYPTO_AES_586 -+ tristate "AES cipher algorithms (i586)" -+ depends on (X86 || UML_X86) && !64BIT -+ select CRYPTO_ALGAPI -+ select CRYPTO_AES -+ help -+ AES cipher algorithms (FIPS-197). AES uses the Rijndael -+ algorithm. -+ -+ Rijndael appears to be consistently a very good performer in -+ both hardware and software across a wide range of computing -+ environments regardless of its use in feedback or non-feedback -+ modes. Its key setup time is excellent, and its key agility is -+ good. Rijndael's very low memory requirements make it very well -+ suited for restricted-space environments, in which it also -+ demonstrates excellent performance. Rijndael's operations are -+ among the easiest to defend against power and timing attacks. -+ -+ The AES specifies three key sizes: 128, 192 and 256 bits -+ -+ See for more information. -+ -+config CRYPTO_AES_X86_64 -+ tristate "AES cipher algorithms (x86_64)" -+ depends on (X86 || UML_X86) && 64BIT -+ select CRYPTO_ALGAPI -+ select CRYPTO_AES -+ help -+ AES cipher algorithms (FIPS-197). AES uses the Rijndael -+ algorithm. -+ -+ Rijndael appears to be consistently a very good performer in -+ both hardware and software across a wide range of computing -+ environments regardless of its use in feedback or non-feedback -+ modes. Its key setup time is excellent, and its key agility is -+ good. Rijndael's very low memory requirements make it very well -+ suited for restricted-space environments, in which it also -+ demonstrates excellent performance. Rijndael's operations are -+ among the easiest to defend against power and timing attacks. -+ -+ The AES specifies three key sizes: 128, 192 and 256 bits -+ -+ See for more information. -+ -+config CRYPTO_AES_NI_INTEL -+ tristate "AES cipher algorithms (AES-NI)" -+ depends on (X86 || UML_X86) -+ select CRYPTO_AES_X86_64 if 64BIT -+ select CRYPTO_AES_586 if !64BIT -+ select CRYPTO_CRYPTD -+ select CRYPTO_ALGAPI -+ help -+ Use Intel AES-NI instructions for AES algorithm. -+ -+ AES cipher algorithms (FIPS-197). AES uses the Rijndael -+ algorithm. -+ -+ Rijndael appears to be consistently a very good performer in -+ both hardware and software across a wide range of computing -+ environments regardless of its use in feedback or non-feedback -+ modes. Its key setup time is excellent, and its key agility is -+ good. Rijndael's very low memory requirements make it very well -+ suited for restricted-space environments, in which it also -+ demonstrates excellent performance. Rijndael's operations are -+ among the easiest to defend against power and timing attacks. -+ -+ The AES specifies three key sizes: 128, 192 and 256 bits -+ -+ See for more information. -+ -+ In addition to AES cipher algorithm support, the acceleration -+ for some popular block cipher mode is supported too, including -+ ECB, CBC, LRW, PCBC, XTS. The 64 bit version has additional -+ acceleration for CTR. -+ -+config CRYPTO_ANUBIS -+ tristate "Anubis cipher algorithm" -+ select CRYPTO_ALGAPI -+ help -+ Anubis cipher algorithm. -+ -+ Anubis is a variable key length cipher which can use keys from -+ 128 bits to 320 bits in length. It was evaluated as a entrant -+ in the NESSIE competition. -+ -+ See also: -+ -+ -+ -+config CRYPTO_ARC4 -+ tristate "ARC4 cipher algorithm" -+ select CRYPTO_ALGAPI -+ help -+ ARC4 cipher algorithm. -+ -+ ARC4 is a stream cipher using keys ranging from 8 bits to 2048 -+ bits in length. This algorithm is required for driver-based -+ WEP, but it should not be for other purposes because of the -+ weakness of the algorithm. -+ -+config CRYPTO_BLOWFISH -+ tristate "Blowfish cipher algorithm" -+ select CRYPTO_ALGAPI -+ help -+ Blowfish cipher algorithm, by Bruce Schneier. -+ -+ This is a variable key length cipher which can use keys from 32 -+ bits to 448 bits in length. It's fast, simple and specifically -+ designed for use on "large microprocessors". -+ -+ See also: -+ -+ -+config CRYPTO_CAMELLIA -+ tristate "Camellia cipher algorithms" -+ depends on CRYPTO -+ select CRYPTO_ALGAPI -+ help -+ Camellia cipher algorithms module. -+ -+ Camellia is a symmetric key block cipher developed jointly -+ at NTT and Mitsubishi Electric Corporation. -+ -+ The Camellia specifies three key sizes: 128, 192 and 256 bits. -+ -+ See also: -+ -+ -+config CRYPTO_CAST5 -+ tristate "CAST5 (CAST-128) cipher algorithm" -+ select CRYPTO_ALGAPI -+ help -+ The CAST5 encryption algorithm (synonymous with CAST-128) is -+ described in RFC2144. -+ -+config CRYPTO_CAST6 -+ tristate "CAST6 (CAST-256) cipher algorithm" -+ select CRYPTO_ALGAPI -+ help -+ The CAST6 encryption algorithm (synonymous with CAST-256) is -+ described in RFC2612. -+ -+config CRYPTO_DES -+ tristate "DES and Triple DES EDE cipher algorithms" -+ select CRYPTO_ALGAPI -+ help -+ DES cipher algorithm (FIPS 46-2), and Triple DES EDE (FIPS 46-3). -+ -+config CRYPTO_FCRYPT -+ tristate "FCrypt cipher algorithm" -+ select CRYPTO_ALGAPI -+ select CRYPTO_BLKCIPHER -+ help -+ FCrypt algorithm used by RxRPC. -+ -+config CRYPTO_KHAZAD -+ tristate "Khazad cipher algorithm" -+ select CRYPTO_ALGAPI -+ help -+ Khazad cipher algorithm. -+ -+ Khazad was a finalist in the initial NESSIE competition. It is -+ an algorithm optimized for 64-bit processors with good performance -+ on 32-bit processors. Khazad uses an 128 bit key size. -+ -+ See also: -+ -+ -+config CRYPTO_SALSA20 -+ tristate "Salsa20 stream cipher algorithm (EXPERIMENTAL)" -+ depends on EXPERIMENTAL -+ select CRYPTO_BLKCIPHER -+ help -+ Salsa20 stream cipher algorithm. -+ -+ Salsa20 is a stream cipher submitted to eSTREAM, the ECRYPT -+ Stream Cipher Project. See -+ -+ The Salsa20 stream cipher algorithm is designed by Daniel J. -+ Bernstein . See -+ -+config CRYPTO_SALSA20_586 -+ tristate "Salsa20 stream cipher algorithm (i586) (EXPERIMENTAL)" -+ depends on (X86 || UML_X86) && !64BIT -+ depends on EXPERIMENTAL -+ select CRYPTO_BLKCIPHER -+ help -+ Salsa20 stream cipher algorithm. -+ -+ Salsa20 is a stream cipher submitted to eSTREAM, the ECRYPT -+ Stream Cipher Project. See -+ -+ The Salsa20 stream cipher algorithm is designed by Daniel J. -+ Bernstein . See -+ -+config CRYPTO_SALSA20_X86_64 -+ tristate "Salsa20 stream cipher algorithm (x86_64) (EXPERIMENTAL)" -+ depends on (X86 || UML_X86) && 64BIT -+ depends on EXPERIMENTAL -+ select CRYPTO_BLKCIPHER -+ help -+ Salsa20 stream cipher algorithm. -+ -+ Salsa20 is a stream cipher submitted to eSTREAM, the ECRYPT -+ Stream Cipher Project. See -+ -+ The Salsa20 stream cipher algorithm is designed by Daniel J. -+ Bernstein . See -+ -+config CRYPTO_SEED -+ tristate "SEED cipher algorithm" -+ select CRYPTO_ALGAPI -+ help -+ SEED cipher algorithm (RFC4269). -+ -+ SEED is a 128-bit symmetric key block cipher that has been -+ developed by KISA (Korea Information Security Agency) as a -+ national standard encryption algorithm of the Republic of Korea. -+ It is a 16 round block cipher with the key size of 128 bit. -+ -+ See also: -+ -+ -+config CRYPTO_SERPENT -+ tristate "Serpent cipher algorithm" -+ select CRYPTO_ALGAPI -+ help -+ Serpent cipher algorithm, by Anderson, Biham & Knudsen. -+ -+ Keys are allowed to be from 0 to 256 bits in length, in steps -+ of 8 bits. Also includes the 'Tnepres' algorithm, a reversed -+ variant of Serpent for compatibility with old kerneli.org code. -+ -+ See also: -+ -+ -+config CRYPTO_TEA -+ tristate "TEA, XTEA and XETA cipher algorithms" -+ select CRYPTO_ALGAPI -+ help -+ TEA cipher algorithm. -+ -+ Tiny Encryption Algorithm is a simple cipher that uses -+ many rounds for security. It is very fast and uses -+ little memory. -+ -+ Xtendend Tiny Encryption Algorithm is a modification to -+ the TEA algorithm to address a potential key weakness -+ in the TEA algorithm. -+ -+ Xtendend Encryption Tiny Algorithm is a mis-implementation -+ of the XTEA algorithm for compatibility purposes. -+ -+config CRYPTO_TWOFISH -+ tristate "Twofish cipher algorithm" -+ select CRYPTO_ALGAPI -+ select CRYPTO_TWOFISH_COMMON -+ help -+ Twofish cipher algorithm. -+ -+ Twofish was submitted as an AES (Advanced Encryption Standard) -+ candidate cipher by researchers at CounterPane Systems. It is a -+ 16 round block cipher supporting key sizes of 128, 192, and 256 -+ bits. -+ -+ See also: -+ -+ -+config CRYPTO_TWOFISH_COMMON -+ tristate -+ help -+ Common parts of the Twofish cipher algorithm shared by the -+ generic c and the assembler implementations. -+ -+config CRYPTO_TWOFISH_586 -+ tristate "Twofish cipher algorithms (i586)" -+ depends on (X86 || UML_X86) && !64BIT -+ select CRYPTO_ALGAPI -+ select CRYPTO_TWOFISH_COMMON -+ help -+ Twofish cipher algorithm. -+ -+ Twofish was submitted as an AES (Advanced Encryption Standard) -+ candidate cipher by researchers at CounterPane Systems. It is a -+ 16 round block cipher supporting key sizes of 128, 192, and 256 -+ bits. -+ -+ See also: -+ -+ -+config CRYPTO_TWOFISH_X86_64 -+ tristate "Twofish cipher algorithm (x86_64)" -+ depends on (X86 || UML_X86) && 64BIT -+ select CRYPTO_ALGAPI -+ select CRYPTO_TWOFISH_COMMON -+ help -+ Twofish cipher algorithm (x86_64). -+ -+ Twofish was submitted as an AES (Advanced Encryption Standard) -+ candidate cipher by researchers at CounterPane Systems. It is a -+ 16 round block cipher supporting key sizes of 128, 192, and 256 -+ bits. -+ -+ See also: -+ -+ -+comment "Compression" -+ -+config CRYPTO_DEFLATE -+ tristate "Deflate compression algorithm" -+ select CRYPTO_ALGAPI -+ select ZLIB_INFLATE -+ select ZLIB_DEFLATE -+ help -+ This is the Deflate algorithm (RFC1951), specified for use in -+ IPSec with the IPCOMP protocol (RFC3173, RFC2394). -+ -+ You will most probably want this if using IPSec. -+ -+config CRYPTO_ZLIB -+ tristate "Zlib compression algorithm" -+ select CRYPTO_PCOMP -+ select ZLIB_INFLATE -+ select ZLIB_DEFLATE -+ select NLATTR -+ help -+ This is the zlib algorithm. -+ -+config CRYPTO_LZO -+ tristate "LZO compression algorithm" -+ select CRYPTO_ALGAPI -+ select LZO_COMPRESS -+ select LZO_DECOMPRESS -+ help -+ This is the LZO algorithm. -+ -+comment "Random Number Generation" -+ -+config CRYPTO_ANSI_CPRNG -+ tristate "Pseudo Random Number Generation for Cryptographic modules" -+ default m -+ select CRYPTO_AES -+ select CRYPTO_RNG -+ help -+ This option enables the generic pseudo random number generator -+ for cryptographic modules. Uses the Algorithm specified in -+ ANSI X9.31 A.2.4. Note that this option must be enabled if -+ CRYPTO_FIPS is selected -+ -+config CRYPTO_USER_API -+ tristate -+ -+config CRYPTO_USER_API_HASH -+ tristate "User-space interface for hash algorithms" -+ depends on NET -+ select CRYPTO_HASH -+ select CRYPTO_USER_API -+ help -+ This option enables the user-spaces interface for hash -+ algorithms. -+ -+config CRYPTO_USER_API_SKCIPHER -+ tristate "User-space interface for symmetric key cipher algorithms" -+ depends on NET -+ select CRYPTO_BLKCIPHER -+ select CRYPTO_USER_API -+ help -+ This option enables the user-spaces interface for symmetric -+ key cipher algorithms. -+ -+source "drivers/crypto/Kconfig" -+ -+endif # if CRYPTO -diff -Nur linux-3.0.4.orig/crypto/Makefile linux-3.0.4/crypto/Makefile ---- linux-3.0.4.orig/crypto/Makefile 2011-08-29 22:56:30.000000000 +0200 -+++ linux-3.0.4/crypto/Makefile 2011-10-17 04:36:27.356574299 +0200 -@@ -89,6 +89,8 @@ - obj-$(CONFIG_CRYPTO_USER_API_HASH) += algif_hash.o - obj-$(CONFIG_CRYPTO_USER_API_SKCIPHER) += algif_skcipher.o - -+obj-$(CONFIG_OCF_OCF) += ocf/ -+ - # - # generic algorithms and the async_tx api - # -diff -Nur linux-3.0.4.orig/crypto/ocf/Config.in linux-3.0.4/crypto/ocf/Config.in ---- linux-3.0.4.orig/crypto/ocf/Config.in 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/Config.in 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,38 @@ -+############################################################################# -+ -+mainmenu_option next_comment -+comment 'OCF Configuration' -+tristate 'OCF (Open Cryptograhic Framework)' CONFIG_OCF_OCF -+dep_mbool ' enable fips RNG checks (fips check on RNG data before use)' \ -+ CONFIG_OCF_FIPS $CONFIG_OCF_OCF -+dep_mbool ' enable harvesting entropy for /dev/random' \ -+ CONFIG_OCF_RANDOMHARVEST $CONFIG_OCF_OCF -+dep_tristate ' cryptodev (user space support)' \ -+ CONFIG_OCF_CRYPTODEV $CONFIG_OCF_OCF -+dep_tristate ' cryptosoft (software crypto engine)' \ -+ CONFIG_OCF_CRYPTOSOFT $CONFIG_OCF_OCF -+dep_tristate ' safenet (HW crypto engine)' \ -+ CONFIG_OCF_SAFE $CONFIG_OCF_OCF -+dep_tristate ' IXP4xx (HW crypto engine)' \ -+ CONFIG_OCF_IXP4XX $CONFIG_OCF_OCF -+dep_mbool ' Enable IXP4xx HW to perform SHA1 and MD5 hashing (very slow)' \ -+ CONFIG_OCF_IXP4XX_SHA1_MD5 $CONFIG_OCF_IXP4XX -+dep_tristate ' hifn (HW crypto engine)' \ -+ CONFIG_OCF_HIFN $CONFIG_OCF_OCF -+dep_tristate ' talitos (HW crypto engine)' \ -+ CONFIG_OCF_TALITOS $CONFIG_OCF_OCF -+dep_tristate ' pasemi (HW crypto engine)' \ -+ CONFIG_OCF_PASEMI $CONFIG_OCF_OCF -+dep_tristate ' ep80579 (HW crypto engine)' \ -+ CONFIG_OCF_EP80579 $CONFIG_OCF_OCF -+dep_tristate ' Micronas c7108 (HW crypto engine)' \ -+ CONFIG_OCF_C7108 $CONFIG_OCF_OCF -+dep_tristate ' uBsec BCM5365 (HW crypto engine)' -+ CONFIG_OCF_UBSEC_SSB $CONFIG_OCF_OCF -+dep_tristate ' ocfnull (does no crypto)' \ -+ CONFIG_OCF_OCFNULL $CONFIG_OCF_OCF -+dep_tristate ' ocf-bench (HW crypto in-kernel benchmark)' \ -+ CONFIG_OCF_BENCH $CONFIG_OCF_OCF -+endmenu -+ -+############################################################################# -diff -Nur linux-3.0.4.orig/crypto/ocf/Kconfig linux-3.0.4/crypto/ocf/Kconfig ---- linux-3.0.4.orig/crypto/ocf/Kconfig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/Kconfig 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,125 @@ -+menu "OCF Configuration" -+ -+config OCF_OCF -+ tristate "OCF (Open Cryptograhic Framework)" -+ help -+ A linux port of the OpenBSD/FreeBSD crypto framework. -+ -+config OCF_RANDOMHARVEST -+ bool "crypto random --- harvest entropy for /dev/random" -+ depends on OCF_OCF -+ help -+ Includes code to harvest random numbers from devices that support it. -+ -+config OCF_FIPS -+ bool "enable fips RNG checks" -+ depends on OCF_OCF && OCF_RANDOMHARVEST -+ help -+ Run all RNG provided data through a fips check before -+ adding it /dev/random's entropy pool. -+ -+config OCF_CRYPTODEV -+ tristate "cryptodev (user space support)" -+ depends on OCF_OCF -+ help -+ The user space API to access crypto hardware. -+ -+config OCF_CRYPTOSOFT -+ tristate "cryptosoft (software crypto engine)" -+ depends on OCF_OCF -+ help -+ A software driver for the OCF framework that uses -+ the kernel CryptoAPI. -+ -+config OCF_SAFE -+ tristate "safenet (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ A driver for a number of the safenet Excel crypto accelerators. -+ Currently tested and working on the 1141 and 1741. -+ -+config OCF_IXP4XX -+ tristate "IXP4xx (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ XScale IXP4xx crypto accelerator driver. Requires the -+ Intel Access library. -+ -+config OCF_IXP4XX_SHA1_MD5 -+ bool "IXP4xx SHA1 and MD5 Hashing" -+ depends on OCF_IXP4XX -+ help -+ Allows the IXP4xx crypto accelerator to perform SHA1 and MD5 hashing. -+ Note: this is MUCH slower than using cryptosoft (software crypto engine). -+ -+config OCF_HIFN -+ tristate "hifn (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for various HIFN based crypto accelerators. -+ (7951, 7955, 7956, 7751, 7811) -+ -+config OCF_HIFNHIPP -+ tristate "Hifn HIPP (HW packet crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for various HIFN (HIPP) based crypto accelerators -+ (7855) -+ -+config OCF_TALITOS -+ tristate "talitos (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for Freescale's security engine (SEC/talitos). -+ -+config OCF_PASEMI -+ tristate "pasemi (HW crypto engine)" -+ depends on OCF_OCF && PPC_PASEMI -+ help -+ OCF driver for the PA Semi PWRficient DMA Engine -+ -+config OCF_EP80579 -+ tristate "ep80579 (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for the Intel EP80579 Integrated Processor Product Line. -+ -+config OCF_CRYPTOCTEON -+ tristate "cryptocteon (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for the Cavium OCTEON Processors. -+ -+config OCF_KIRKWOOD -+ tristate "kirkwood (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for the Marvell Kirkwood (88F6xxx) Processors. -+ -+config OCF_C7108 -+ tristate "Micronas 7108 (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for the Microna 7108 Cipher processors. -+ -+config OCF_UBSEC_SSB -+ tristate "uBsec BCM5365 (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for uBsec BCM5365 hardware crypto accelerator. -+ -+config OCF_OCFNULL -+ tristate "ocfnull (fake crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for measuring ipsec overheads (does no crypto) -+ -+config OCF_BENCH -+ tristate "ocf-bench (HW crypto in-kernel benchmark)" -+ depends on OCF_OCF -+ help -+ A very simple encryption test for the in-kernel interface -+ of OCF. Also includes code to benchmark the IXP Access library -+ for comparison. -+ -+endmenu -diff -Nur linux-3.0.4.orig/crypto/ocf/Makefile linux-3.0.4/crypto/ocf/Makefile ---- linux-3.0.4.orig/crypto/ocf/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/Makefile 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,145 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+OCF_OBJS = crypto.o criov.o -+ -+ifdef CONFIG_OCF_RANDOMHARVEST -+ OCF_OBJS += random.o -+endif -+ -+ifdef CONFIG_OCF_FIPS -+ OCF_OBJS += rndtest.o -+endif -+ -+# Add in autoconf.h to get #defines for CONFIG_xxx -+AUTOCONF_H=$(ROOTDIR)/modules/autoconf.h -+ifeq ($(AUTOCONF_H), $(wildcard $(AUTOCONF_H))) -+ EXTRA_CFLAGS += -include $(AUTOCONF_H) -+ export EXTRA_CFLAGS -+endif -+ -+ifndef obj -+ obj ?= . -+ _obj = subdir -+ mod-subdirs := safe hifn ixp4xx talitos ocfnull -+ export-objs += crypto.o criov.o random.o -+ list-multi += ocf.o -+ _slash := -+else -+ _obj = obj -+ _slash := / -+endif -+ -+EXTRA_CFLAGS += -I$(obj)/. -+ -+obj-$(CONFIG_OCF_OCF) += ocf.o -+obj-$(CONFIG_OCF_CRYPTODEV) += cryptodev.o -+obj-$(CONFIG_OCF_CRYPTOSOFT) += cryptosoft.o -+obj-$(CONFIG_OCF_BENCH) += ocf-bench.o -+ -+$(_obj)-$(CONFIG_OCF_SAFE) += safe$(_slash) -+$(_obj)-$(CONFIG_OCF_HIFN) += hifn$(_slash) -+$(_obj)-$(CONFIG_OCF_IXP4XX) += ixp4xx$(_slash) -+$(_obj)-$(CONFIG_OCF_TALITOS) += talitos$(_slash) -+$(_obj)-$(CONFIG_OCF_PASEMI) += pasemi$(_slash) -+$(_obj)-$(CONFIG_OCF_EP80579) += ep80579$(_slash) -+$(_obj)-$(CONFIG_OCF_CRYPTOCTEON) += cryptocteon$(_slash) -+$(_obj)-$(CONFIG_OCF_KIRKWOOD) += kirkwood$(_slash) -+$(_obj)-$(CONFIG_OCF_OCFNULL) += ocfnull$(_slash) -+$(_obj)-$(CONFIG_OCF_C7108) += c7108$(_slash) -+$(_obj)-$(CONFIG_OCF_UBSEC_SSB) += ubsec_ssb$(_slash) -+ -+ocf-objs := $(OCF_OBJS) -+ -+dummy: -+ @echo "Please consult the README for how to build OCF." -+ @echo "If you can't wait then the following should do it:" -+ @echo "" -+ @echo " make ocf_modules" -+ @echo " sudo make ocf_install" -+ @echo "" -+ @exit 1 -+ -+$(list-multi) dummy1: $(ocf-objs) -+ $(LD) -r -o $@ $(ocf-objs) -+ -+.PHONY: -+clean: -+ rm -f *.o *.ko .*.o.flags .*.ko.cmd .*.o.cmd .*.mod.o.cmd *.mod.c -+ rm -f */*.o */*.ko */.*.o.cmd */.*.ko.cmd */.*.mod.o.cmd */*.mod.c */.*.o.flags -+ rm -f */modules.order */modules.builtin modules.order modules.builtin -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -+# -+# targets to build easily on the current machine -+# -+ -+ocf_make: -+ make -C /lib/modules/$(shell uname -r)/build M=`pwd` $(OCF_TARGET) CONFIG_OCF_OCF=m -+ make -C /lib/modules/$(shell uname -r)/build M=`pwd` $(OCF_TARGET) CONFIG_OCF_OCF=m CONFIG_OCF_CRYPTOSOFT=m -+ -make -C /lib/modules/$(shell uname -r)/build M=`pwd` $(OCF_TARGET) CONFIG_OCF_OCF=m CONFIG_OCF_BENCH=m -+ -make -C /lib/modules/$(shell uname -r)/build M=`pwd` $(OCF_TARGET) CONFIG_OCF_OCF=m CONFIG_OCF_OCFNULL=m -+ -make -C /lib/modules/$(shell uname -r)/build M=`pwd` $(OCF_TARGET) CONFIG_OCF_OCF=m CONFIG_OCF_HIFN=m -+ -+ocf_modules: -+ $(MAKE) ocf_make OCF_TARGET=modules -+ -+ocf_install: -+ $(MAKE) ocf_make OCF_TARGET="modules modules_install" -+ depmod -+ mkdir -p /usr/include/crypto -+ cp cryptodev.h /usr/include/crypto/. -+ -+# -+# generate full kernel patches for 2.4 and 2.6 kernels to make patching -+# your kernel easier -+# -+ -+.PHONY: patch -+patch: -+ patchbase=.; \ -+ [ -d $$patchbase/patches ] || patchbase=..; \ -+ patch=ocf-linux-base.patch; \ -+ patch24=ocf-linux-24.patch; \ -+ patch26=ocf-linux-26.patch; \ -+ ( \ -+ find . -name Makefile; \ -+ find . -name Config.in; \ -+ find . -name Kconfig; \ -+ find . -name README; \ -+ find . -name '*.[ch]' | grep -v '.mod.c'; \ -+ ) | while read t; do \ -+ diff -Nau /dev/null $$t | sed 's?^+++ \./?+++ linux/crypto/ocf/?'; \ -+ done > $$patch; \ -+ cat $$patchbase/patches/linux-2.4.35-ocf.patch $$patch > $$patch24; \ -+ cat $$patchbase/patches/linux-2.6.38-ocf.patch $$patch > $$patch26; \ -+ -+# -+# this target probably does nothing for anyone but me - davidm -+# -+ -+.PHONY: release -+release: -+ REL=`date +%Y%m%d`; RELDIR=/tmp/ocf-linux-$$REL; \ -+ CURDIR=`pwd`; \ -+ rm -rf /tmp/ocf-linux-$$REL*; \ -+ mkdir -p $$RELDIR/ocf; \ -+ mkdir -p $$RELDIR/patches; \ -+ mkdir -p $$RELDIR/crypto-tools; \ -+ cp README* $$RELDIR/.; \ -+ cp patches/[!C]* $$RELDIR/patches/.; \ -+ cp tools/[!C]* $$RELDIR/crypto-tools/.; \ -+ cp -r [!C]* Config.in $$RELDIR/ocf/.; \ -+ rm -rf $$RELDIR/ocf/patches $$RELDIR/ocf/tools; \ -+ rm -f $$RELDIR/ocf/README*; \ -+ cp $$CURDIR/../../user/crypto-tools/[!C]* $$RELDIR/crypto-tools/.; \ -+ make -C $$RELDIR/crypto-tools clean; \ -+ make -C $$RELDIR/ocf clean; \ -+ find $$RELDIR/ocf -name CVS | xargs rm -rf; \ -+ cd $$RELDIR/..; \ -+ tar cvf ocf-linux-$$REL.tar ocf-linux-$$REL; \ -+ gzip -9 ocf-linux-$$REL.tar -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/c7108/Makefile linux-3.0.4/crypto/ocf/c7108/Makefile ---- linux-3.0.4.orig/crypto/ocf/c7108/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/c7108/Makefile 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,12 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+obj-$(CONFIG_OCF_C7108) += aes-7108.o -+ -+obj ?= . -+EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/c7108/aes-7108.c linux-3.0.4/crypto/ocf/c7108/aes-7108.c ---- linux-3.0.4.orig/crypto/ocf/c7108/aes-7108.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/c7108/aes-7108.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,839 @@ -+/* -+ * Copyright (C) 2006 Micronas USA -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored in part by the Defense Advanced Research Projects -+ * Agency (DARPA) and Air Force Research Laboratory, Air Force -+ * Materiel Command, USAF, under agreement number F30602-01-2-0537. -+ * -+ */ -+ -+//#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+//#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* Runtime mode */ -+static int c7108_crypto_mode = C7108_AES_CTRL_MODE_CTR; -+//static int c7108_crypto_mode = C7108_AES_CTRL_MODE_CBC; -+ -+static int32_t c7108_id = -1; -+static struct cipher_7108 **c7108_sessions = NULL; -+static u_int32_t c7108_sesnum = 0; -+static unsigned long iobar; -+ -+/* Crypto entry points */ -+static int c7108_process(void *, struct cryptop *, int); -+static int c7108_newsession(void *, u_int32_t *, struct cryptoini *); -+static int c7108_freesession(void *, u_int64_t); -+ -+/* Globals */ -+static int debug = 0; -+static spinlock_t csr_mutex; -+ -+/* Generic controller-based lock */ -+#define AES_LOCK()\ -+ spin_lock(&csr_mutex) -+#define AES_UNLOCK()\ -+ spin_unlock(&csr_mutex) -+ -+/* 7108 AES register access */ -+#define c7108_reg_wr8(a,d) iowrite8(d, (void*)(iobar+(a))) -+#define c7108_reg_wr16(a,d) iowrite16(d, (void*)(iobar+(a))) -+#define c7108_reg_wr32(a,d) iowrite32(d, (void*)(iobar+(a))) -+#define c7108_reg_rd8(a) ioread8((void*)(iobar+(a))) -+#define c7108_reg_rd16(a) ioread16((void*)(iobar+(a))) -+#define c7108_reg_rd32(a) ioread32((void*)(iobar+(a))) -+ -+static int -+c7108_xlate_key(int klen, u8* k8ptr, u32* k32ptr) -+{ -+ int i, nw=0; -+ nw = ((klen >= 256) ? 8 : (klen >= 192) ? 6 : 4); -+ for ( i = 0; i < nw; i++) { -+ k32ptr[i] = (k8ptr[i+3] << 24) | (k8ptr[i+2] << 16) | -+ (k8ptr[i+1] << 8) | k8ptr[i]; -+ -+ } -+ return 0; -+} -+ -+static int -+c7108_cache_key(int klen, u32* k32ptr, u8* k8ptr) -+{ -+ int i, nb=0; -+ u8* ptr = (u8*)k32ptr; -+ nb = ((klen >= 256) ? 32 : (klen >= 192) ? 24 : 16); -+ for ( i = 0; i < nb; i++) -+ k8ptr[i] = ptr[i]; -+ return 0; -+} -+ -+static int -+c7108_aes_setup_dma(u32 src, u32 dst, u32 len) -+{ -+ if (len < 16) { -+ printk("len < 16\n"); -+ return -10; -+ } -+ if (len % 16) { -+ printk("len not multiple of 16\n"); -+ return -11; -+ } -+ c7108_reg_wr16(C7108_AES_DMA_SRC0_LO, (u16) src); -+ c7108_reg_wr16(C7108_AES_DMA_SRC0_HI, (u16)((src & 0xffff0000) >> 16)); -+ c7108_reg_wr16(C7108_AES_DMA_DST0_LO, (u16) dst); -+ c7108_reg_wr16(C7108_AES_DMA_DST0_HI, (u16)((dst & 0xffff0000) >> 16)); -+ c7108_reg_wr16(C7108_AES_DMA_LEN, (u16) ((len / 16) - 1)); -+ -+ return 0; -+} -+ -+static int -+c7108_aes_set_hw_iv(u8 iv[16]) -+{ -+ c7108_reg_wr16(C7108_AES_IV0_LO, (u16) ((iv[1] << 8) | iv[0])); -+ c7108_reg_wr16(C7108_AES_IV0_HI, (u16) ((iv[3] << 8) | iv[2])); -+ c7108_reg_wr16(C7108_AES_IV1_LO, (u16) ((iv[5] << 8) | iv[4])); -+ c7108_reg_wr16(C7108_AES_IV1_HI, (u16) ((iv[7] << 8) | iv[6])); -+ c7108_reg_wr16(C7108_AES_IV2_LO, (u16) ((iv[9] << 8) | iv[8])); -+ c7108_reg_wr16(C7108_AES_IV2_HI, (u16) ((iv[11] << 8) | iv[10])); -+ c7108_reg_wr16(C7108_AES_IV3_LO, (u16) ((iv[13] << 8) | iv[12])); -+ c7108_reg_wr16(C7108_AES_IV3_HI, (u16) ((iv[15] << 8) | iv[14])); -+ -+ return 0; -+} -+ -+static void -+c7108_aes_read_dkey(u32 * dkey) -+{ -+ dkey[0] = (c7108_reg_rd16(C7108_AES_EKEY0_HI) << 16) | -+ c7108_reg_rd16(C7108_AES_EKEY0_LO); -+ dkey[1] = (c7108_reg_rd16(C7108_AES_EKEY1_HI) << 16) | -+ c7108_reg_rd16(C7108_AES_EKEY1_LO); -+ dkey[2] = (c7108_reg_rd16(C7108_AES_EKEY2_HI) << 16) | -+ c7108_reg_rd16(C7108_AES_EKEY2_LO); -+ dkey[3] = (c7108_reg_rd16(C7108_AES_EKEY3_HI) << 16) | -+ c7108_reg_rd16(C7108_AES_EKEY3_LO); -+ dkey[4] = (c7108_reg_rd16(C7108_AES_EKEY4_HI) << 16) | -+ c7108_reg_rd16(C7108_AES_EKEY4_LO); -+ dkey[5] = (c7108_reg_rd16(C7108_AES_EKEY5_HI) << 16) | -+ c7108_reg_rd16(C7108_AES_EKEY5_LO); -+ dkey[6] = (c7108_reg_rd16(C7108_AES_EKEY6_HI) << 16) | -+ c7108_reg_rd16(C7108_AES_EKEY6_LO); -+ dkey[7] = (c7108_reg_rd16(C7108_AES_EKEY7_HI) << 16) | -+ c7108_reg_rd16(C7108_AES_EKEY7_LO); -+} -+ -+static int -+c7108_aes_cipher(int op, -+ u32 dst, -+ u32 src, -+ u32 len, -+ int klen, -+ u16 mode, -+ u32 key[8], -+ u8 iv[16]) -+{ -+ int rv = 0, cnt=0; -+ u16 ctrl = 0, stat = 0; -+ -+ AES_LOCK(); -+ -+ /* Setup key length */ -+ if (klen == 128) { -+ ctrl |= C7108_AES_KEY_LEN_128; -+ } else if (klen == 192) { -+ ctrl |= C7108_AES_KEY_LEN_192; -+ } else if (klen == 256) { -+ ctrl |= C7108_AES_KEY_LEN_256; -+ } else { -+ AES_UNLOCK(); -+ return -3; -+ } -+ -+ /* Check opcode */ -+ if (C7108_AES_ENCRYPT == op) { -+ ctrl |= C7108_AES_ENCRYPT; -+ } else if (C7108_AES_DECRYPT == op) { -+ ctrl |= C7108_AES_DECRYPT; -+ } else { -+ AES_UNLOCK(); -+ return -4; -+ } -+ -+ /* check mode */ -+ if ( (mode != C7108_AES_CTRL_MODE_CBC) && -+ (mode != C7108_AES_CTRL_MODE_CFB) && -+ (mode != C7108_AES_CTRL_MODE_OFB) && -+ (mode != C7108_AES_CTRL_MODE_CTR) && -+ (mode != C7108_AES_CTRL_MODE_ECB) ) { -+ AES_UNLOCK(); -+ return -5; -+ } -+ -+ /* Now set mode */ -+ ctrl |= mode; -+ -+ /* For CFB, OFB, and CTR, neither backward key -+ * expansion nor key inversion is required. -+ */ -+ if ( (C7108_AES_DECRYPT == op) && -+ (C7108_AES_CTRL_MODE_CBC == mode || -+ C7108_AES_CTRL_MODE_ECB == mode ) ){ -+ -+ /* Program Key */ -+ c7108_reg_wr16(C7108_AES_KEY0_LO, (u16) key[4]); -+ c7108_reg_wr16(C7108_AES_KEY0_HI, (u16) (key[4] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY1_LO, (u16) key[5]); -+ c7108_reg_wr16(C7108_AES_KEY1_HI, (u16) (key[5] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY2_LO, (u16) key[6]); -+ c7108_reg_wr16(C7108_AES_KEY2_HI, (u16) (key[6] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY3_LO, (u16) key[7]); -+ c7108_reg_wr16(C7108_AES_KEY3_HI, (u16) (key[7] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY6_LO, (u16) key[2]); -+ c7108_reg_wr16(C7108_AES_KEY6_HI, (u16) (key[2] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY7_LO, (u16) key[3]); -+ c7108_reg_wr16(C7108_AES_KEY7_HI, (u16) (key[3] >> 16)); -+ -+ -+ if (192 == klen) { -+ c7108_reg_wr16(C7108_AES_KEY4_LO, (u16) key[7]); -+ c7108_reg_wr16(C7108_AES_KEY4_HI, (u16) (key[7] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY5_LO, (u16) key[7]); -+ c7108_reg_wr16(C7108_AES_KEY5_HI, (u16) (key[7] >> 16)); -+ -+ } else if (256 == klen) { -+ /* 256 */ -+ c7108_reg_wr16(C7108_AES_KEY4_LO, (u16) key[0]); -+ c7108_reg_wr16(C7108_AES_KEY4_HI, (u16) (key[0] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY5_LO, (u16) key[1]); -+ c7108_reg_wr16(C7108_AES_KEY5_HI, (u16) (key[1] >> 16)); -+ -+ } -+ -+ } else { -+ /* Program Key */ -+ c7108_reg_wr16(C7108_AES_KEY0_LO, (u16) key[0]); -+ c7108_reg_wr16(C7108_AES_KEY0_HI, (u16) (key[0] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY1_LO, (u16) key[1]); -+ c7108_reg_wr16(C7108_AES_KEY1_HI, (u16) (key[1] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY2_LO, (u16) key[2]); -+ c7108_reg_wr16(C7108_AES_KEY2_HI, (u16) (key[2] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY3_LO, (u16) key[3]); -+ c7108_reg_wr16(C7108_AES_KEY3_HI, (u16) (key[3] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY4_LO, (u16) key[4]); -+ c7108_reg_wr16(C7108_AES_KEY4_HI, (u16) (key[4] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY5_LO, (u16) key[5]); -+ c7108_reg_wr16(C7108_AES_KEY5_HI, (u16) (key[5] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY6_LO, (u16) key[6]); -+ c7108_reg_wr16(C7108_AES_KEY6_HI, (u16) (key[6] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY7_LO, (u16) key[7]); -+ c7108_reg_wr16(C7108_AES_KEY7_HI, (u16) (key[7] >> 16)); -+ -+ } -+ -+ /* Set IV always */ -+ c7108_aes_set_hw_iv(iv); -+ -+ /* Program DMA addresses */ -+ if ((rv = c7108_aes_setup_dma(src, dst, len)) < 0) { -+ AES_UNLOCK(); -+ return rv; -+ } -+ -+ -+ /* Start AES cipher */ -+ c7108_reg_wr16(C7108_AES_CTRL, ctrl | C7108_AES_GO); -+ -+ //printk("Ctrl: 0x%x\n", ctrl | C7108_AES_GO); -+ do { -+ /* TODO: interrupt mode */ -+ // printk("aes_stat=0x%x\n", stat); -+ //udelay(100); -+ } while ((cnt++ < 1000000) && -+ !((stat=c7108_reg_rd16(C7108_AES_CTRL))&C7108_AES_OP_DONE)); -+ -+ -+ if ((mode == C7108_AES_CTRL_MODE_ECB)|| -+ (mode == C7108_AES_CTRL_MODE_CBC)) { -+ /* Save out key when the lock is held ... */ -+ c7108_aes_read_dkey(key); -+ } -+ -+ AES_UNLOCK(); -+ return 0; -+ -+} -+ -+/* -+ * Generate a new crypto device session. -+ */ -+static int -+c7108_newsession(void *arg, u_int32_t *sid, struct cryptoini *cri) -+{ -+ struct cipher_7108 **swd; -+ u_int32_t i; -+ char *algo; -+ int mode, xfm_type; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid == NULL || cri == NULL) { -+ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ if (c7108_sessions) { -+ for (i = 1; i < c7108_sesnum; i++) -+ if (c7108_sessions[i] == NULL) -+ break; -+ } else -+ i = 1; /* NB: to silence compiler warning */ -+ -+ if (c7108_sessions == NULL || i == c7108_sesnum) { -+ if (c7108_sessions == NULL) { -+ i = 1; /* We leave c7108_sessions[0] empty */ -+ c7108_sesnum = CRYPTO_SW_SESSIONS; -+ } else -+ c7108_sesnum *= 2; -+ -+ swd = kmalloc(c7108_sesnum * sizeof(struct cipher_7108 *), -+ GFP_ATOMIC); -+ if (swd == NULL) { -+ /* Reset session number */ -+ if (c7108_sesnum == CRYPTO_SW_SESSIONS) -+ c7108_sesnum = 0; -+ else -+ c7108_sesnum /= 2; -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memset(swd, 0, c7108_sesnum * sizeof(struct cipher_7108 *)); -+ -+ /* Copy existing sessions */ -+ if (c7108_sessions) { -+ memcpy(swd, c7108_sessions, -+ (c7108_sesnum / 2) * sizeof(struct cipher_7108 *)); -+ kfree(c7108_sessions); -+ } -+ -+ c7108_sessions = swd; -+ -+ } -+ -+ swd = &c7108_sessions[i]; -+ *sid = i; -+ -+ while (cri) { -+ *swd = (struct cipher_7108 *) -+ kmalloc(sizeof(struct cipher_7108), GFP_ATOMIC); -+ if (*swd == NULL) { -+ c7108_freesession(NULL, i); -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memset(*swd, 0, sizeof(struct cipher_7108)); -+ -+ algo = NULL; -+ mode = 0; -+ xfm_type = HW_TYPE_CIPHER; -+ -+ switch (cri->cri_alg) { -+ -+ case CRYPTO_AES_CBC: -+ algo = "aes"; -+ mode = CRYPTO_TFM_MODE_CBC; -+ c7108_crypto_mode = C7108_AES_CTRL_MODE_CBC; -+ break; -+#if 0 -+ case CRYPTO_AES_CTR: -+ algo = "aes_ctr"; -+ mode = CRYPTO_TFM_MODE_CBC; -+ c7108_crypto_mode = C7108_AES_CTRL_MODE_CTR; -+ break; -+ case CRYPTO_AES_ECB: -+ algo = "aes_ecb"; -+ mode = CRYPTO_TFM_MODE_CBC; -+ c7108_crypto_mode = C7108_AES_CTRL_MODE_ECB; -+ break; -+ case CRYPTO_AES_OFB: -+ algo = "aes_ofb"; -+ mode = CRYPTO_TFM_MODE_CBC; -+ c7108_crypto_mode = C7108_AES_CTRL_MODE_OFB; -+ break; -+ case CRYPTO_AES_CFB: -+ algo = "aes_cfb"; -+ mode = CRYPTO_TFM_MODE_CBC; -+ c7108_crypto_mode = C7108_AES_CTRL_MODE_CFB; -+ break; -+#endif -+ default: -+ printk("unsupported crypto algorithm: %d\n", -+ cri->cri_alg); -+ return -EINVAL; -+ break; -+ } -+ -+ -+ if (!algo || !*algo) { -+ printk("cypher_7108_crypto: Unknown algo 0x%x\n", -+ cri->cri_alg); -+ c7108_freesession(NULL, i); -+ return EINVAL; -+ } -+ -+ if (xfm_type == HW_TYPE_CIPHER) { -+ if (debug) { -+ dprintk("%s key:", __FUNCTION__); -+ for (i = 0; i < (cri->cri_klen + 7) / 8; i++) -+ dprintk("%s0x%02x", (i % 8) ? " " : "\n ", -+ cri->cri_key[i]); -+ dprintk("\n"); -+ } -+ -+ } else if (xfm_type == SW_TYPE_HMAC || -+ xfm_type == SW_TYPE_HASH) { -+ printk("cypher_7108_crypto: HMAC unsupported!\n"); -+ return -EINVAL; -+ c7108_freesession(NULL, i); -+ } else { -+ printk("cypher_7108_crypto: " -+ "Unhandled xfm_type %d\n", xfm_type); -+ c7108_freesession(NULL, i); -+ return EINVAL; -+ } -+ -+ (*swd)->cri_alg = cri->cri_alg; -+ (*swd)->xfm_type = xfm_type; -+ -+ cri = cri->cri_next; -+ swd = &((*swd)->next); -+ } -+ return 0; -+} -+ -+/* -+ * Free a session. -+ */ -+static int -+c7108_freesession(void *arg, u_int64_t tid) -+{ -+ struct cipher_7108 *swd; -+ u_int32_t sid = CRYPTO_SESID2LID(tid); -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid > c7108_sesnum || c7108_sessions == NULL || -+ c7108_sessions[sid] == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return(EINVAL); -+ } -+ -+ /* Silently accept and return */ -+ if (sid == 0) -+ return(0); -+ -+ while ((swd = c7108_sessions[sid]) != NULL) { -+ c7108_sessions[sid] = swd->next; -+ kfree(swd); -+ } -+ return 0; -+} -+ -+/* -+ * Process a hardware request. -+ */ -+static int -+c7108_process(void *arg, struct cryptop *crp, int hint) -+{ -+ struct cryptodesc *crd; -+ struct cipher_7108 *sw; -+ u_int32_t lid; -+ int type; -+ u32 hwkey[8]; -+ -+#define SCATTERLIST_MAX 16 -+ struct scatterlist sg[SCATTERLIST_MAX]; -+ int sg_num, sg_len, skip; -+ struct sk_buff *skb = NULL; -+ struct uio *uiop = NULL; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ /* Sanity check */ -+ if (crp == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ crp->crp_etype = 0; -+ -+ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ lid = crp->crp_sid & 0xffffffff; -+ if (lid >= c7108_sesnum || lid == 0 || c7108_sessions == NULL || -+ c7108_sessions[lid] == NULL) { -+ crp->crp_etype = ENOENT; -+ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); -+ goto done; -+ } -+ -+ /* -+ * do some error checking outside of the loop for SKB and IOV -+ * processing this leaves us with valid skb or uiop pointers -+ * for later -+ */ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ skb = (struct sk_buff *) crp->crp_buf; -+ if (skb_shinfo(skb)->nr_frags >= SCATTERLIST_MAX) { -+ printk("%s,%d: %d nr_frags > SCATTERLIST_MAX", -+ __FILE__, __LINE__, -+ skb_shinfo(skb)->nr_frags); -+ goto done; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ uiop = (struct uio *) crp->crp_buf; -+ if (uiop->uio_iovcnt > SCATTERLIST_MAX) { -+ printk("%s,%d: %d uio_iovcnt > SCATTERLIST_MAX", -+ __FILE__, __LINE__, -+ uiop->uio_iovcnt); -+ goto done; -+ } -+ } -+ -+ /* Go through crypto descriptors, processing as we go */ -+ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { -+ /* -+ * Find the crypto context. -+ * -+ * XXX Note that the logic here prevents us from having -+ * XXX the same algorithm multiple times in a session -+ * XXX (or rather, we can but it won't give us the right -+ * XXX results). To do that, we'd need some way of differentiating -+ * XXX between the various instances of an algorithm (so we can -+ * XXX locate the correct crypto context). -+ */ -+ for (sw = c7108_sessions[lid]; -+ sw && sw->cri_alg != crd->crd_alg; -+ sw = sw->next) -+ ; -+ -+ /* No such context ? */ -+ if (sw == NULL) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ goto done; -+ } -+ -+ skip = crd->crd_skip; -+ -+ /* -+ * setup the SG list skip from the start of the buffer -+ */ -+ memset(sg, 0, sizeof(sg)); -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ int i, len; -+ type = CRYPTO_BUF_SKBUF; -+ -+ sg_num = 0; -+ sg_len = 0; -+ -+ if (skip < skb_headlen(skb)) { -+ //sg[sg_num].page = virt_to_page(skb->data + skip); -+ //sg[sg_num].offset = offset_in_page(skb->data + skip); -+ len = skb_headlen(skb) - skip; -+ if (len + sg_len > crd->crd_len) -+ len = crd->crd_len - sg_len; -+ //sg[sg_num].length = len; -+ sg_set_page(&sg[sg_num], virt_to_page(skb->data + skip), len, offset_in_page(skb->data + skip)); -+ sg_len += sg[sg_num].length; -+ sg_num++; -+ skip = 0; -+ } else -+ skip -= skb_headlen(skb); -+ -+ for (i = 0; sg_len < crd->crd_len && -+ i < skb_shinfo(skb)->nr_frags && -+ sg_num < SCATTERLIST_MAX; i++) { -+ if (skip < skb_shinfo(skb)->frags[i].size) { -+ //sg[sg_num].page = skb_shinfo(skb)->frags[i].page; -+ //sg[sg_num].offset = skb_shinfo(skb)->frags[i].page_offset + skip; -+ len = skb_shinfo(skb)->frags[i].size - skip; -+ if (len + sg_len > crd->crd_len) -+ len = crd->crd_len - sg_len; -+ //sg[sg_num].length = len; -+ sg_set_page(&sg[sg_num], skb_shinfo(skb)->frags[i].page, len, skb_shinfo(skb)->frags[i].page_offset + skip); -+ sg_len += sg[sg_num].length; -+ sg_num++; -+ skip = 0; -+ } else -+ skip -= skb_shinfo(skb)->frags[i].size; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ int len; -+ type = CRYPTO_BUF_IOV; -+ sg_len = 0; -+ for (sg_num = 0; sg_len < crd->crd_len && -+ sg_num < uiop->uio_iovcnt && -+ sg_num < SCATTERLIST_MAX; sg_num++) { -+ if (skip < uiop->uio_iov[sg_num].iov_len) { -+ //sg[sg_num].page = virt_to_page(uiop->uio_iov[sg_num].iov_base+skip); -+ //sg[sg_num].offset = offset_in_page(uiop->uio_iov[sg_num].iov_base+skip); -+ len = uiop->uio_iov[sg_num].iov_len - skip; -+ if (len + sg_len > crd->crd_len) -+ len = crd->crd_len - sg_len; -+ //sg[sg_num].length = len; -+ sg_set_page(&sg[sg_num], virt_to_page(uiop->uio_iov[sg_num].iov_base+skip), len, offset_in_page(uiop->uio_iov[sg_num].iov_base+skip)); -+ sg_len += sg[sg_num].length; -+ skip = 0; -+ } else -+ skip -= uiop->uio_iov[sg_num].iov_len; -+ } -+ } else { -+ type = CRYPTO_BUF_CONTIG; -+ //sg[0].page = virt_to_page(crp->crp_buf + skip); -+ //sg[0].offset = offset_in_page(crp->crp_buf + skip); -+ sg_len = (crp->crp_ilen - skip); -+ if (sg_len > crd->crd_len) -+ sg_len = crd->crd_len; -+ //sg[0].length = sg_len; -+ sg_set_page(&sg[0], virt_to_page(crp->crp_buf + skip), sg_len, offset_in_page(crp->crp_buf + skip)); -+ sg_num = 1; -+ } -+ -+ -+ switch (sw->xfm_type) { -+ -+ case HW_TYPE_CIPHER: { -+ -+ unsigned char iv[64]; -+ unsigned char *ivp = iv; -+ int i; -+ int ivsize = 16; /* fixed for AES */ -+ int blocksize = 16; /* fixed for AES */ -+ -+ if (sg_len < blocksize) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: EINVAL len %d < %d\n", -+ __FILE__, __LINE__, -+ sg_len, -+ blocksize); -+ goto done; -+ } -+ -+ if (ivsize > sizeof(iv)) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ goto done; -+ } -+ -+ if (crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ -+ -+ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { -+ ivp = crd->crd_iv; -+ } else { -+ get_random_bytes(ivp, ivsize); -+ } -+ /* -+ * do we have to copy the IV back to the buffer ? -+ */ -+ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { -+ crypto_copyback(crp->crp_buf, -+ crd->crd_inject, -+ ivsize, -+ (caddr_t)ivp); -+ } -+ -+ c7108_xlate_key(crd->crd_klen, -+ (u8*)crd->crd_key, (u32*)hwkey); -+ -+ /* Encrypt SG list */ -+ for (i = 0; i < sg_num; i++) { -+ sg[i].dma_address = -+ dma_map_single(NULL, -+ kmap(sg_page(&sg[i])) + sg[i].offset, sg_len, DMA_BIDIRECTIONAL); -+#if 0 -+ printk("sg[%d]:0x%08x, off 0x%08x " -+ "kmap 0x%08x phys 0x%08x\n", -+ i, sg[i].page, sg[i].offset, -+ kmap(sg[i].page) + sg[i].offset, -+ sg[i].dma_address); -+#endif -+ c7108_aes_cipher(C7108_AES_ENCRYPT, -+ sg[i].dma_address, -+ sg[i].dma_address, -+ sg_len, -+ crd->crd_klen, -+ c7108_crypto_mode, -+ hwkey, -+ ivp); -+ -+ if ((c7108_crypto_mode == C7108_AES_CTRL_MODE_CBC)|| -+ (c7108_crypto_mode == C7108_AES_CTRL_MODE_ECB)) { -+ /* Read back expanded key and cache it in key -+ * context. -+ * NOTE: for ECB/CBC modes only (not CTR, CFB, OFB) -+ * where you set the key once. -+ */ -+ c7108_cache_key(crd->crd_klen, -+ (u32*)hwkey, (u8*)crd->crd_key); -+#if 0 -+ printk("%s expanded key:", __FUNCTION__); -+ for (i = 0; i < (crd->crd_klen + 7) / 8; i++) -+ printk("%s0x%02x", (i % 8) ? " " : "\n ", -+ crd->crd_key[i]); -+ printk("\n"); -+#endif -+ } -+ } -+ } -+ else { /*decrypt */ -+ -+ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { -+ ivp = crd->crd_iv; -+ } else { -+ crypto_copydata(crp->crp_buf, crd->crd_inject, -+ ivsize, (caddr_t)ivp); -+ } -+ -+ c7108_xlate_key(crd->crd_klen, -+ (u8*)crd->crd_key, (u32*)hwkey); -+ -+ /* Decrypt SG list */ -+ for (i = 0; i < sg_num; i++) { -+ sg[i].dma_address = -+ dma_map_single(NULL, -+ kmap(sg_page(&sg[i])) + sg[i].offset, -+ sg_len, DMA_BIDIRECTIONAL); -+ -+#if 0 -+ printk("sg[%d]:0x%08x, off 0x%08x " -+ "kmap 0x%08x phys 0x%08x\n", -+ i, sg[i].page, sg[i].offset, -+ kmap(sg[i].page) + sg[i].offset, -+ sg[i].dma_address); -+#endif -+ c7108_aes_cipher(C7108_AES_DECRYPT, -+ sg[i].dma_address, -+ sg[i].dma_address, -+ sg_len, -+ crd->crd_klen, -+ c7108_crypto_mode, -+ hwkey, -+ ivp); -+ } -+ } -+ } break; -+ case SW_TYPE_HMAC: -+ case SW_TYPE_HASH: -+ crp->crp_etype = EINVAL; -+ goto done; -+ break; -+ -+ case SW_TYPE_COMP: -+ crp->crp_etype = EINVAL; -+ goto done; -+ break; -+ -+ default: -+ /* Unknown/unsupported algorithm */ -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ } -+ -+done: -+ crypto_done(crp); -+ return 0; -+} -+ -+static struct { -+ softc_device_decl sc_dev; -+} a7108dev; -+ -+static device_method_t a7108_methods = { -+/* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, c7108_newsession), -+ DEVMETHOD(cryptodev_freesession, c7108_freesession), -+ DEVMETHOD(cryptodev_process, c7108_process), -+ DEVMETHOD(cryptodev_kprocess, NULL) -+}; -+ -+static int -+cypher_7108_crypto_init(void) -+{ -+ dprintk("%s(%p)\n", __FUNCTION__, cypher_7108_crypto_init); -+ -+ iobar = (unsigned long)ioremap(CCU_AES_REG_BASE, 0x4000); -+ printk("7108: AES @ 0x%08x (0x%08x phys) %s mode\n", -+ iobar, CCU_AES_REG_BASE, -+ c7108_crypto_mode & C7108_AES_CTRL_MODE_CBC ? "CBC" : -+ c7108_crypto_mode & C7108_AES_CTRL_MODE_ECB ? "ECB" : -+ c7108_crypto_mode & C7108_AES_CTRL_MODE_CTR ? "CTR" : -+ c7108_crypto_mode & C7108_AES_CTRL_MODE_CFB ? "CFB" : -+ c7108_crypto_mode & C7108_AES_CTRL_MODE_OFB ? "OFB" : "???"); -+ csr_mutex = SPIN_LOCK_UNLOCKED; -+ -+ memset(&a7108dev, 0, sizeof(a7108dev)); -+ softc_device_init(&a7108dev, "aes7108", 0, a7108_methods); -+ -+ c7108_id = crypto_get_driverid(softc_get_device(&a7108dev), CRYPTOCAP_F_HARDWARE); -+ if (c7108_id < 0) -+ panic("7108: crypto device cannot initialize!"); -+ -+// crypto_register(c7108_id, CRYPTO_AES_CBC, 0, 0, c7108_newsession, c7108_freesession, c7108_process, NULL); -+ crypto_register(c7108_id, CRYPTO_AES_CBC, 0, 0); -+ -+ return(0); -+} -+ -+static void -+cypher_7108_crypto_exit(void) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ crypto_unregister_all(c7108_id); -+ c7108_id = -1; -+} -+ -+module_init(cypher_7108_crypto_init); -+module_exit(cypher_7108_crypto_exit); -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_DESCRIPTION("Cypher 7108 Crypto (OCF module for kernel crypto)"); -diff -Nur linux-3.0.4.orig/crypto/ocf/c7108/aes-7108.h linux-3.0.4/crypto/ocf/c7108/aes-7108.h ---- linux-3.0.4.orig/crypto/ocf/c7108/aes-7108.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/c7108/aes-7108.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,134 @@ -+/* -+ * Copyright (C) 2006 Micronas USA -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored in part by the Defense Advanced Research Projects -+ * Agency (DARPA) and Air Force Research Laboratory, Air Force -+ * Materiel Command, USAF, under agreement number F30602-01-2-0537. -+ * -+ */ -+ -+#ifndef __AES_7108_H__ -+#define __AES_7108_H__ -+ -+/* Cypher 7108 AES Controller Hardware */ -+#define CCU_REG_BASE 0x1b500000 -+#define CCU_AES_REG_BASE (CCU_REG_BASE + 0x100) -+#define C7108_AES_KEY0_LO (0x0000) -+#define C7108_AES_KEY0_HI (0x0004) -+#define C7108_AES_KEY1_LO (0x0008) -+#define C7108_AES_KEY1_HI (0x000c) -+#define C7108_AES_KEY2_LO (0x0010) -+#define C7108_AES_KEY2_HI (0x0014) -+#define C7108_AES_KEY3_LO (0x0018) -+#define C7108_AES_KEY3_HI (0x001c) -+#define C7108_AES_KEY4_LO (0x0020) -+#define C7108_AES_KEY4_HI (0x0024) -+#define C7108_AES_KEY5_LO (0x0028) -+#define C7108_AES_KEY5_HI (0x002c) -+#define C7108_AES_KEY6_LO (0x0030) -+#define C7108_AES_KEY6_HI (0x0034) -+#define C7108_AES_KEY7_LO (0x0038) -+#define C7108_AES_KEY7_HI (0x003c) -+#define C7108_AES_IV0_LO (0x0040) -+#define C7108_AES_IV0_HI (0x0044) -+#define C7108_AES_IV1_LO (0x0048) -+#define C7108_AES_IV1_HI (0x004c) -+#define C7108_AES_IV2_LO (0x0050) -+#define C7108_AES_IV2_HI (0x0054) -+#define C7108_AES_IV3_LO (0x0058) -+#define C7108_AES_IV3_HI (0x005c) -+ -+#define C7108_AES_DMA_SRC0_LO (0x0068) /* Bits 0:15 */ -+#define C7108_AES_DMA_SRC0_HI (0x006c) /* Bits 27:16 */ -+#define C7108_AES_DMA_DST0_LO (0x0070) /* Bits 0:15 */ -+#define C7108_AES_DMA_DST0_HI (0x0074) /* Bits 27:16 */ -+#define C7108_AES_DMA_LEN (0x0078) /*Bytes:(Count+1)x16 */ -+ -+/* AES/Copy engine control register */ -+#define C7108_AES_CTRL (0x007c) /* AES control */ -+#define C7108_AES_CTRL_RS (1<<0) /* Which set of src/dst to use */ -+ -+/* AES Cipher mode, controlled by setting Bits 2:0 */ -+#define C7108_AES_CTRL_MODE_CBC 0 -+#define C7108_AES_CTRL_MODE_CFB (1<<0) -+#define C7108_AES_CTRL_MODE_OFB (1<<1) -+#define C7108_AES_CTRL_MODE_CTR ((1<<0)|(1<<1)) -+#define C7108_AES_CTRL_MODE_ECB (1<<2) -+ -+/* AES Key length , Bits 5:4 */ -+#define C7108_AES_KEY_LEN_128 0 /* 00 */ -+#define C7108_AES_KEY_LEN_192 (1<<4) /* 01 */ -+#define C7108_AES_KEY_LEN_256 (1<<5) /* 10 */ -+ -+/* AES Operation (crypt/decrypt), Bit 3 */ -+#define C7108_AES_DECRYPT (1<<3) /* Clear for encrypt */ -+#define C7108_AES_ENCRYPT 0 -+#define C7108_AES_INTR (1<<13) /* Set on done trans from 0->1*/ -+#define C7108_AES_GO (1<<14) /* Run */ -+#define C7108_AES_OP_DONE (1<<15) /* Set when complete */ -+ -+ -+/* Expanded key registers */ -+#define C7108_AES_EKEY0_LO (0x0080) -+#define C7108_AES_EKEY0_HI (0x0084) -+#define C7108_AES_EKEY1_LO (0x0088) -+#define C7108_AES_EKEY1_HI (0x008c) -+#define C7108_AES_EKEY2_LO (0x0090) -+#define C7108_AES_EKEY2_HI (0x0094) -+#define C7108_AES_EKEY3_LO (0x0098) -+#define C7108_AES_EKEY3_HI (0x009c) -+#define C7108_AES_EKEY4_LO (0x00a0) -+#define C7108_AES_EKEY4_HI (0x00a4) -+#define C7108_AES_EKEY5_LO (0x00a8) -+#define C7108_AES_EKEY5_HI (0x00ac) -+#define C7108_AES_EKEY6_LO (0x00b0) -+#define C7108_AES_EKEY6_HI (0x00b4) -+#define C7108_AES_EKEY7_LO (0x00b8) -+#define C7108_AES_EKEY7_HI (0x00bc) -+#define C7108_AES_OK (0x00fc) /* Reset: "OK" */ -+ -+#define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK) -+ -+/* Software session entry */ -+ -+#define HW_TYPE_CIPHER 0 -+#define SW_TYPE_HMAC 1 -+#define SW_TYPE_AUTH2 2 -+#define SW_TYPE_HASH 3 -+#define SW_TYPE_COMP 4 -+ -+struct cipher_7108 { -+ int xfm_type; -+ int cri_alg; -+ union { -+ struct { -+ char sw_key[HMAC_BLOCK_LEN]; -+ int sw_klen; -+ int sw_authlen; -+ } hmac; -+ } u; -+ struct cipher_7108 *next; -+}; -+ -+ -+ -+#endif /* __C7108_AES_7108_H__ */ -diff -Nur linux-3.0.4.orig/crypto/ocf/criov.c linux-3.0.4/crypto/ocf/criov.c ---- linux-3.0.4.orig/crypto/ocf/criov.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/criov.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,216 @@ -+/* $OpenBSD: criov.c,v 1.9 2002/01/29 15:48:29 jason Exp $ */ -+ -+/* -+ * Linux port done by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * The license and original author are listed below. -+ * -+ * Copyright (c) 1999 Theo de Raadt -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+__FBSDID("$FreeBSD: src/sys/opencrypto/criov.c,v 1.5 2006/06/04 22:15:13 pjd Exp $"); -+ */ -+ -+#include -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+/* -+ * This macro is only for avoiding code duplication, as we need to skip -+ * given number of bytes in the same way in three functions below. -+ */ -+#define CUIO_SKIP() do { \ -+ KASSERT(off >= 0, ("%s: off %d < 0", __func__, off)); \ -+ KASSERT(len >= 0, ("%s: len %d < 0", __func__, len)); \ -+ while (off > 0) { \ -+ KASSERT(iol >= 0, ("%s: empty in skip", __func__)); \ -+ if (off < iov->iov_len) \ -+ break; \ -+ off -= iov->iov_len; \ -+ iol--; \ -+ iov++; \ -+ } \ -+} while (0) -+ -+void -+cuio_copydata(struct uio* uio, int off, int len, caddr_t cp) -+{ -+ struct iovec *iov = uio->uio_iov; -+ int iol = uio->uio_iovcnt; -+ unsigned count; -+ -+ CUIO_SKIP(); -+ while (len > 0) { -+ KASSERT(iol >= 0, ("%s: empty", __func__)); -+ count = min((int)(iov->iov_len - off), len); -+ memcpy(cp, ((caddr_t)iov->iov_base) + off, count); -+ len -= count; -+ cp += count; -+ off = 0; -+ iol--; -+ iov++; -+ } -+} -+ -+void -+cuio_copyback(struct uio* uio, int off, int len, caddr_t cp) -+{ -+ struct iovec *iov = uio->uio_iov; -+ int iol = uio->uio_iovcnt; -+ unsigned count; -+ -+ CUIO_SKIP(); -+ while (len > 0) { -+ KASSERT(iol >= 0, ("%s: empty", __func__)); -+ count = min((int)(iov->iov_len - off), len); -+ memcpy(((caddr_t)iov->iov_base) + off, cp, count); -+ len -= count; -+ cp += count; -+ off = 0; -+ iol--; -+ iov++; -+ } -+} -+ -+/* -+ * Return a pointer to iov/offset of location in iovec list. -+ */ -+struct iovec * -+cuio_getptr(struct uio *uio, int loc, int *off) -+{ -+ struct iovec *iov = uio->uio_iov; -+ int iol = uio->uio_iovcnt; -+ -+ while (loc >= 0) { -+ /* Normal end of search */ -+ if (loc < iov->iov_len) { -+ *off = loc; -+ return (iov); -+ } -+ -+ loc -= iov->iov_len; -+ if (iol == 0) { -+ if (loc == 0) { -+ /* Point at the end of valid data */ -+ *off = iov->iov_len; -+ return (iov); -+ } else -+ return (NULL); -+ } else { -+ iov++, iol--; -+ } -+ } -+ -+ return (NULL); -+} -+ -+EXPORT_SYMBOL(cuio_copyback); -+EXPORT_SYMBOL(cuio_copydata); -+EXPORT_SYMBOL(cuio_getptr); -+ -+ -+static void -+skb_copy_bits_back(struct sk_buff *skb, int offset, caddr_t cp, int len) -+{ -+ int i; -+ if (offset < skb_headlen(skb)) { -+ memcpy(skb->data + offset, cp, min_t(int, skb_headlen(skb), len)); -+ len -= skb_headlen(skb); -+ cp += skb_headlen(skb); -+ } -+ offset -= skb_headlen(skb); -+ for (i = 0; len > 0 && i < skb_shinfo(skb)->nr_frags; i++) { -+ if (offset < skb_shinfo(skb)->frags[i].size) { -+ memcpy(page_address(skb_shinfo(skb)->frags[i].page) + -+ skb_shinfo(skb)->frags[i].page_offset, -+ cp, min_t(int, skb_shinfo(skb)->frags[i].size, len)); -+ len -= skb_shinfo(skb)->frags[i].size; -+ cp += skb_shinfo(skb)->frags[i].size; -+ } -+ offset -= skb_shinfo(skb)->frags[i].size; -+ } -+} -+ -+void -+crypto_copyback(int flags, caddr_t buf, int off, int size, caddr_t in) -+{ -+ -+ if ((flags & CRYPTO_F_SKBUF) != 0) -+ skb_copy_bits_back((struct sk_buff *)buf, off, in, size); -+ else if ((flags & CRYPTO_F_IOV) != 0) -+ cuio_copyback((struct uio *)buf, off, size, in); -+ else -+ bcopy(in, buf + off, size); -+} -+ -+void -+crypto_copydata(int flags, caddr_t buf, int off, int size, caddr_t out) -+{ -+ -+ if ((flags & CRYPTO_F_SKBUF) != 0) -+ skb_copy_bits((struct sk_buff *)buf, off, out, size); -+ else if ((flags & CRYPTO_F_IOV) != 0) -+ cuio_copydata((struct uio *)buf, off, size, out); -+ else -+ bcopy(buf + off, out, size); -+} -+ -+int -+crypto_apply(int flags, caddr_t buf, int off, int len, -+ int (*f)(void *, void *, u_int), void *arg) -+{ -+#if 0 -+ int error; -+ -+ if ((flags & CRYPTO_F_SKBUF) != 0) -+ error = XXXXXX((struct mbuf *)buf, off, len, f, arg); -+ else if ((flags & CRYPTO_F_IOV) != 0) -+ error = cuio_apply((struct uio *)buf, off, len, f, arg); -+ else -+ error = (*f)(arg, buf + off, len); -+ return (error); -+#else -+ KASSERT(0, ("crypto_apply not implemented!\n")); -+#endif -+ return 0; -+} -+ -+EXPORT_SYMBOL(crypto_copyback); -+EXPORT_SYMBOL(crypto_copydata); -+EXPORT_SYMBOL(crypto_apply); -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/crypto.c linux-3.0.4/crypto/ocf/crypto.c ---- linux-3.0.4.orig/crypto/ocf/crypto.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/crypto.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,1766 @@ -+/*- -+ * Linux port done by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * The license and original author are listed below. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * Copyright (c) 2002-2006 Sam Leffler. All rights reserved. -+ * -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#if 0 -+#include -+__FBSDID("$FreeBSD: src/sys/opencrypto/crypto.c,v 1.27 2007/03/21 03:42:51 sam Exp $"); -+#endif -+ -+/* -+ * Cryptographic Subsystem. -+ * -+ * This code is derived from the Openbsd Cryptographic Framework (OCF) -+ * that has the copyright shown below. Very little of the original -+ * code remains. -+ */ -+/*- -+ * The author of this code is Angelos D. Keromytis (angelos@cis.upenn.edu) -+ * -+ * This code was written by Angelos D. Keromytis in Athens, Greece, in -+ * February 2000. Network Security Technologies Inc. (NSTI) kindly -+ * supported the development of this code. -+ * -+ * Copyright (c) 2000, 2001 Angelos D. Keromytis -+ * -+ * Permission to use, copy, and modify this software with or without fee -+ * is hereby granted, provided that this entire notice is included in -+ * all source code copies of any software which is or includes a copy or -+ * modification of this software. -+ * -+ * THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR -+ * IMPLIED WARRANTY. IN PARTICULAR, NONE OF THE AUTHORS MAKES ANY -+ * REPRESENTATION OR WARRANTY OF ANY KIND CONCERNING THE -+ * MERCHANTABILITY OF THIS SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR -+ * PURPOSE. -+ * -+__FBSDID("$FreeBSD: src/sys/opencrypto/crypto.c,v 1.16 2005/01/07 02:29:16 imp Exp $"); -+ */ -+ -+ -+#include -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,4) -+#include -+#endif -+#include -+ -+/* -+ * keep track of whether or not we have been initialised, a big -+ * issue if we are linked into the kernel and a driver gets started before -+ * us -+ */ -+static int crypto_initted = 0; -+ -+/* -+ * Crypto drivers register themselves by allocating a slot in the -+ * crypto_drivers table with crypto_get_driverid() and then registering -+ * each algorithm they support with crypto_register() and crypto_kregister(). -+ */ -+ -+/* -+ * lock on driver table -+ * we track its state as spin_is_locked does not do anything on non-SMP boxes -+ */ -+static spinlock_t crypto_drivers_lock; -+static int crypto_drivers_locked; /* for non-SMP boxes */ -+ -+#define CRYPTO_DRIVER_LOCK() \ -+ ({ \ -+ spin_lock_irqsave(&crypto_drivers_lock, d_flags); \ -+ crypto_drivers_locked = 1; \ -+ dprintk("%s,%d: DRIVER_LOCK()\n", __FILE__, __LINE__); \ -+ }) -+#define CRYPTO_DRIVER_UNLOCK() \ -+ ({ \ -+ dprintk("%s,%d: DRIVER_UNLOCK()\n", __FILE__, __LINE__); \ -+ crypto_drivers_locked = 0; \ -+ spin_unlock_irqrestore(&crypto_drivers_lock, d_flags); \ -+ }) -+#define CRYPTO_DRIVER_ASSERT() \ -+ ({ \ -+ if (!crypto_drivers_locked) { \ -+ dprintk("%s,%d: DRIVER_ASSERT!\n", __FILE__, __LINE__); \ -+ } \ -+ }) -+ -+/* -+ * Crypto device/driver capabilities structure. -+ * -+ * Synchronization: -+ * (d) - protected by CRYPTO_DRIVER_LOCK() -+ * (q) - protected by CRYPTO_Q_LOCK() -+ * Not tagged fields are read-only. -+ */ -+struct cryptocap { -+ device_t cc_dev; /* (d) device/driver */ -+ u_int32_t cc_sessions; /* (d) # of sessions */ -+ u_int32_t cc_koperations; /* (d) # os asym operations */ -+ /* -+ * Largest possible operator length (in bits) for each type of -+ * encryption algorithm. XXX not used -+ */ -+ u_int16_t cc_max_op_len[CRYPTO_ALGORITHM_MAX + 1]; -+ u_int8_t cc_alg[CRYPTO_ALGORITHM_MAX + 1]; -+ u_int8_t cc_kalg[CRK_ALGORITHM_MAX + 1]; -+ -+ int cc_flags; /* (d) flags */ -+#define CRYPTOCAP_F_CLEANUP 0x80000000 /* needs resource cleanup */ -+ int cc_qblocked; /* (q) symmetric q blocked */ -+ int cc_kqblocked; /* (q) asymmetric q blocked */ -+ -+ int cc_unqblocked; /* (q) symmetric q blocked */ -+ int cc_unkqblocked; /* (q) asymmetric q blocked */ -+}; -+static struct cryptocap *crypto_drivers = NULL; -+static int crypto_drivers_num = 0; -+ -+/* -+ * There are two queues for crypto requests; one for symmetric (e.g. -+ * cipher) operations and one for asymmetric (e.g. MOD)operations. -+ * A single mutex is used to lock access to both queues. We could -+ * have one per-queue but having one simplifies handling of block/unblock -+ * operations. -+ */ -+static LIST_HEAD(crp_q); /* crypto request queue */ -+static LIST_HEAD(crp_kq); /* asym request queue */ -+ -+static spinlock_t crypto_q_lock; -+ -+int crypto_all_qblocked = 0; /* protect with Q_LOCK */ -+module_param(crypto_all_qblocked, int, 0444); -+MODULE_PARM_DESC(crypto_all_qblocked, "Are all crypto queues blocked"); -+ -+int crypto_all_kqblocked = 0; /* protect with Q_LOCK */ -+module_param(crypto_all_kqblocked, int, 0444); -+MODULE_PARM_DESC(crypto_all_kqblocked, "Are all asym crypto queues blocked"); -+ -+#define CRYPTO_Q_LOCK() \ -+ ({ \ -+ spin_lock_irqsave(&crypto_q_lock, q_flags); \ -+ dprintk("%s,%d: Q_LOCK()\n", __FILE__, __LINE__); \ -+ }) -+#define CRYPTO_Q_UNLOCK() \ -+ ({ \ -+ dprintk("%s,%d: Q_UNLOCK()\n", __FILE__, __LINE__); \ -+ spin_unlock_irqrestore(&crypto_q_lock, q_flags); \ -+ }) -+ -+/* -+ * There are two queues for processing completed crypto requests; one -+ * for the symmetric and one for the asymmetric ops. We only need one -+ * but have two to avoid type futzing (cryptop vs. cryptkop). A single -+ * mutex is used to lock access to both queues. Note that this lock -+ * must be separate from the lock on request queues to insure driver -+ * callbacks don't generate lock order reversals. -+ */ -+static LIST_HEAD(crp_ret_q); /* callback queues */ -+static LIST_HEAD(crp_ret_kq); -+ -+static spinlock_t crypto_ret_q_lock; -+#define CRYPTO_RETQ_LOCK() \ -+ ({ \ -+ spin_lock_irqsave(&crypto_ret_q_lock, r_flags); \ -+ dprintk("%s,%d: RETQ_LOCK\n", __FILE__, __LINE__); \ -+ }) -+#define CRYPTO_RETQ_UNLOCK() \ -+ ({ \ -+ dprintk("%s,%d: RETQ_UNLOCK\n", __FILE__, __LINE__); \ -+ spin_unlock_irqrestore(&crypto_ret_q_lock, r_flags); \ -+ }) -+#define CRYPTO_RETQ_EMPTY() (list_empty(&crp_ret_q) && list_empty(&crp_ret_kq)) -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) -+static kmem_cache_t *cryptop_zone; -+static kmem_cache_t *cryptodesc_zone; -+#else -+static struct kmem_cache *cryptop_zone; -+static struct kmem_cache *cryptodesc_zone; -+#endif -+ -+#define debug crypto_debug -+int crypto_debug = 0; -+module_param(crypto_debug, int, 0644); -+MODULE_PARM_DESC(crypto_debug, "Enable debug"); -+EXPORT_SYMBOL(crypto_debug); -+ -+/* -+ * Maximum number of outstanding crypto requests before we start -+ * failing requests. We need this to prevent DOS when too many -+ * requests are arriving for us to keep up. Otherwise we will -+ * run the system out of memory. Since crypto is slow, we are -+ * usually the bottleneck that needs to say, enough is enough. -+ * -+ * We cannot print errors when this condition occurs, we are already too -+ * slow, printing anything will just kill us -+ */ -+ -+static int crypto_q_cnt = 0; -+module_param(crypto_q_cnt, int, 0444); -+MODULE_PARM_DESC(crypto_q_cnt, -+ "Current number of outstanding crypto requests"); -+ -+static int crypto_q_max = 1000; -+module_param(crypto_q_max, int, 0644); -+MODULE_PARM_DESC(crypto_q_max, -+ "Maximum number of outstanding crypto requests"); -+ -+#define bootverbose crypto_verbose -+static int crypto_verbose = 0; -+module_param(crypto_verbose, int, 0644); -+MODULE_PARM_DESC(crypto_verbose, -+ "Enable verbose crypto startup"); -+ -+int crypto_usercrypto = 1; /* userland may do crypto reqs */ -+module_param(crypto_usercrypto, int, 0644); -+MODULE_PARM_DESC(crypto_usercrypto, -+ "Enable/disable user-mode access to crypto support"); -+ -+int crypto_userasymcrypto = 1; /* userland may do asym crypto reqs */ -+module_param(crypto_userasymcrypto, int, 0644); -+MODULE_PARM_DESC(crypto_userasymcrypto, -+ "Enable/disable user-mode access to asymmetric crypto support"); -+ -+int crypto_devallowsoft = 0; /* only use hardware crypto */ -+module_param(crypto_devallowsoft, int, 0644); -+MODULE_PARM_DESC(crypto_devallowsoft, -+ "Enable/disable use of software crypto support"); -+ -+/* -+ * This parameter controls the maximum number of crypto operations to -+ * do consecutively in the crypto kernel thread before scheduling to allow -+ * other processes to run. Without it, it is possible to get into a -+ * situation where the crypto thread never allows any other processes to run. -+ * Default to 1000 which should be less than one second. -+ */ -+static int crypto_max_loopcount = 1000; -+module_param(crypto_max_loopcount, int, 0644); -+MODULE_PARM_DESC(crypto_max_loopcount, -+ "Maximum number of crypto ops to do before yielding to other processes"); -+ -+#ifndef CONFIG_NR_CPUS -+#define CONFIG_NR_CPUS 1 -+#endif -+ -+static struct task_struct *cryptoproc[CONFIG_NR_CPUS]; -+static struct task_struct *cryptoretproc[CONFIG_NR_CPUS]; -+static DECLARE_WAIT_QUEUE_HEAD(cryptoproc_wait); -+static DECLARE_WAIT_QUEUE_HEAD(cryptoretproc_wait); -+ -+static int crypto_proc(void *arg); -+static int crypto_ret_proc(void *arg); -+static int crypto_invoke(struct cryptocap *cap, struct cryptop *crp, int hint); -+static int crypto_kinvoke(struct cryptkop *krp, int flags); -+static void crypto_exit(void); -+static int crypto_init(void); -+ -+static struct cryptostats cryptostats; -+ -+static struct cryptocap * -+crypto_checkdriver(u_int32_t hid) -+{ -+ if (crypto_drivers == NULL) -+ return NULL; -+ return (hid >= crypto_drivers_num ? NULL : &crypto_drivers[hid]); -+} -+ -+/* -+ * Compare a driver's list of supported algorithms against another -+ * list; return non-zero if all algorithms are supported. -+ */ -+static int -+driver_suitable(const struct cryptocap *cap, const struct cryptoini *cri) -+{ -+ const struct cryptoini *cr; -+ -+ /* See if all the algorithms are supported. */ -+ for (cr = cri; cr; cr = cr->cri_next) -+ if (cap->cc_alg[cr->cri_alg] == 0) -+ return 0; -+ return 1; -+} -+ -+ -+/* -+ * Select a driver for a new session that supports the specified -+ * algorithms and, optionally, is constrained according to the flags. -+ * The algorithm we use here is pretty stupid; just use the -+ * first driver that supports all the algorithms we need. If there -+ * are multiple drivers we choose the driver with the fewest active -+ * sessions. We prefer hardware-backed drivers to software ones. -+ * -+ * XXX We need more smarts here (in real life too, but that's -+ * XXX another story altogether). -+ */ -+static struct cryptocap * -+crypto_select_driver(const struct cryptoini *cri, int flags) -+{ -+ struct cryptocap *cap, *best; -+ int match, hid; -+ -+ CRYPTO_DRIVER_ASSERT(); -+ -+ /* -+ * Look first for hardware crypto devices if permitted. -+ */ -+ if (flags & CRYPTOCAP_F_HARDWARE) -+ match = CRYPTOCAP_F_HARDWARE; -+ else -+ match = CRYPTOCAP_F_SOFTWARE; -+ best = NULL; -+again: -+ for (hid = 0; hid < crypto_drivers_num; hid++) { -+ cap = &crypto_drivers[hid]; -+ /* -+ * If it's not initialized, is in the process of -+ * going away, or is not appropriate (hardware -+ * or software based on match), then skip. -+ */ -+ if (cap->cc_dev == NULL || -+ (cap->cc_flags & CRYPTOCAP_F_CLEANUP) || -+ (cap->cc_flags & match) == 0) -+ continue; -+ -+ /* verify all the algorithms are supported. */ -+ if (driver_suitable(cap, cri)) { -+ if (best == NULL || -+ cap->cc_sessions < best->cc_sessions) -+ best = cap; -+ } -+ } -+ if (best != NULL) -+ return best; -+ if (match == CRYPTOCAP_F_HARDWARE && (flags & CRYPTOCAP_F_SOFTWARE)) { -+ /* sort of an Algol 68-style for loop */ -+ match = CRYPTOCAP_F_SOFTWARE; -+ goto again; -+ } -+ return best; -+} -+ -+/* -+ * Create a new session. The crid argument specifies a crypto -+ * driver to use or constraints on a driver to select (hardware -+ * only, software only, either). Whatever driver is selected -+ * must be capable of the requested crypto algorithms. -+ */ -+int -+crypto_newsession(u_int64_t *sid, struct cryptoini *cri, int crid) -+{ -+ struct cryptocap *cap; -+ u_int32_t hid, lid; -+ int err; -+ unsigned long d_flags; -+ -+ CRYPTO_DRIVER_LOCK(); -+ if ((crid & (CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE)) == 0) { -+ /* -+ * Use specified driver; verify it is capable. -+ */ -+ cap = crypto_checkdriver(crid); -+ if (cap != NULL && !driver_suitable(cap, cri)) -+ cap = NULL; -+ } else { -+ /* -+ * No requested driver; select based on crid flags. -+ */ -+ cap = crypto_select_driver(cri, crid); -+ /* -+ * if NULL then can't do everything in one session. -+ * XXX Fix this. We need to inject a "virtual" session -+ * XXX layer right about here. -+ */ -+ } -+ if (cap != NULL) { -+ /* Call the driver initialization routine. */ -+ hid = cap - crypto_drivers; -+ lid = hid; /* Pass the driver ID. */ -+ cap->cc_sessions++; -+ CRYPTO_DRIVER_UNLOCK(); -+ err = CRYPTODEV_NEWSESSION(cap->cc_dev, &lid, cri); -+ CRYPTO_DRIVER_LOCK(); -+ if (err == 0) { -+ (*sid) = (cap->cc_flags & 0xff000000) -+ | (hid & 0x00ffffff); -+ (*sid) <<= 32; -+ (*sid) |= (lid & 0xffffffff); -+ } else -+ cap->cc_sessions--; -+ } else -+ err = EINVAL; -+ CRYPTO_DRIVER_UNLOCK(); -+ return err; -+} -+ -+static void -+crypto_remove(struct cryptocap *cap) -+{ -+ CRYPTO_DRIVER_ASSERT(); -+ if (cap->cc_sessions == 0 && cap->cc_koperations == 0) -+ bzero(cap, sizeof(*cap)); -+} -+ -+/* -+ * Delete an existing session (or a reserved session on an unregistered -+ * driver). -+ */ -+int -+crypto_freesession(u_int64_t sid) -+{ -+ struct cryptocap *cap; -+ u_int32_t hid; -+ int err = 0; -+ unsigned long d_flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ CRYPTO_DRIVER_LOCK(); -+ -+ if (crypto_drivers == NULL) { -+ err = EINVAL; -+ goto done; -+ } -+ -+ /* Determine two IDs. */ -+ hid = CRYPTO_SESID2HID(sid); -+ -+ if (hid >= crypto_drivers_num) { -+ dprintk("%s - INVALID DRIVER NUM %d\n", __FUNCTION__, hid); -+ err = ENOENT; -+ goto done; -+ } -+ cap = &crypto_drivers[hid]; -+ -+ if (cap->cc_dev) { -+ CRYPTO_DRIVER_UNLOCK(); -+ /* Call the driver cleanup routine, if available, unlocked. */ -+ err = CRYPTODEV_FREESESSION(cap->cc_dev, sid); -+ CRYPTO_DRIVER_LOCK(); -+ } -+ -+ if (cap->cc_sessions) -+ cap->cc_sessions--; -+ -+ if (cap->cc_flags & CRYPTOCAP_F_CLEANUP) -+ crypto_remove(cap); -+ -+done: -+ CRYPTO_DRIVER_UNLOCK(); -+ return err; -+} -+ -+/* -+ * Return an unused driver id. Used by drivers prior to registering -+ * support for the algorithms they handle. -+ */ -+int32_t -+crypto_get_driverid(device_t dev, int flags) -+{ -+ struct cryptocap *newdrv; -+ int i; -+ unsigned long d_flags; -+ -+ if ((flags & (CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE)) == 0) { -+ printf("%s: no flags specified when registering driver\n", -+ device_get_nameunit(dev)); -+ return -1; -+ } -+ -+ CRYPTO_DRIVER_LOCK(); -+ -+ for (i = 0; i < crypto_drivers_num; i++) { -+ if (crypto_drivers[i].cc_dev == NULL && -+ (crypto_drivers[i].cc_flags & CRYPTOCAP_F_CLEANUP) == 0) { -+ break; -+ } -+ } -+ -+ /* Out of entries, allocate some more. */ -+ if (i == crypto_drivers_num) { -+ /* Be careful about wrap-around. */ -+ if (2 * crypto_drivers_num <= crypto_drivers_num) { -+ CRYPTO_DRIVER_UNLOCK(); -+ printk("crypto: driver count wraparound!\n"); -+ return -1; -+ } -+ -+ newdrv = kmalloc(2 * crypto_drivers_num * sizeof(struct cryptocap), -+ GFP_KERNEL); -+ if (newdrv == NULL) { -+ CRYPTO_DRIVER_UNLOCK(); -+ printk("crypto: no space to expand driver table!\n"); -+ return -1; -+ } -+ -+ memcpy(newdrv, crypto_drivers, -+ crypto_drivers_num * sizeof(struct cryptocap)); -+ memset(&newdrv[crypto_drivers_num], 0, -+ crypto_drivers_num * sizeof(struct cryptocap)); -+ -+ crypto_drivers_num *= 2; -+ -+ kfree(crypto_drivers); -+ crypto_drivers = newdrv; -+ } -+ -+ /* NB: state is zero'd on free */ -+ crypto_drivers[i].cc_sessions = 1; /* Mark */ -+ crypto_drivers[i].cc_dev = dev; -+ crypto_drivers[i].cc_flags = flags; -+ if (bootverbose) -+ printf("crypto: assign %s driver id %u, flags %u\n", -+ device_get_nameunit(dev), i, flags); -+ -+ CRYPTO_DRIVER_UNLOCK(); -+ -+ return i; -+} -+ -+/* -+ * Lookup a driver by name. We match against the full device -+ * name and unit, and against just the name. The latter gives -+ * us a simple widlcarding by device name. On success return the -+ * driver/hardware identifier; otherwise return -1. -+ */ -+int -+crypto_find_driver(const char *match) -+{ -+ int i, len = strlen(match); -+ unsigned long d_flags; -+ -+ CRYPTO_DRIVER_LOCK(); -+ for (i = 0; i < crypto_drivers_num; i++) { -+ device_t dev = crypto_drivers[i].cc_dev; -+ if (dev == NULL || -+ (crypto_drivers[i].cc_flags & CRYPTOCAP_F_CLEANUP)) -+ continue; -+ if (strncmp(match, device_get_nameunit(dev), len) == 0 || -+ strncmp(match, device_get_name(dev), len) == 0) -+ break; -+ } -+ CRYPTO_DRIVER_UNLOCK(); -+ return i < crypto_drivers_num ? i : -1; -+} -+ -+/* -+ * Return the device_t for the specified driver or NULL -+ * if the driver identifier is invalid. -+ */ -+device_t -+crypto_find_device_byhid(int hid) -+{ -+ struct cryptocap *cap = crypto_checkdriver(hid); -+ return cap != NULL ? cap->cc_dev : NULL; -+} -+ -+/* -+ * Return the device/driver capabilities. -+ */ -+int -+crypto_getcaps(int hid) -+{ -+ struct cryptocap *cap = crypto_checkdriver(hid); -+ return cap != NULL ? cap->cc_flags : 0; -+} -+ -+/* -+ * Register support for a key-related algorithm. This routine -+ * is called once for each algorithm supported a driver. -+ */ -+int -+crypto_kregister(u_int32_t driverid, int kalg, u_int32_t flags) -+{ -+ struct cryptocap *cap; -+ int err; -+ unsigned long d_flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ CRYPTO_DRIVER_LOCK(); -+ -+ cap = crypto_checkdriver(driverid); -+ if (cap != NULL && -+ (CRK_ALGORITM_MIN <= kalg && kalg <= CRK_ALGORITHM_MAX)) { -+ /* -+ * XXX Do some performance testing to determine placing. -+ * XXX We probably need an auxiliary data structure that -+ * XXX describes relative performances. -+ */ -+ -+ cap->cc_kalg[kalg] = flags | CRYPTO_ALG_FLAG_SUPPORTED; -+ if (bootverbose) -+ printf("crypto: %s registers key alg %u flags %u\n" -+ , device_get_nameunit(cap->cc_dev) -+ , kalg -+ , flags -+ ); -+ err = 0; -+ } else -+ err = EINVAL; -+ -+ CRYPTO_DRIVER_UNLOCK(); -+ return err; -+} -+ -+/* -+ * Register support for a non-key-related algorithm. This routine -+ * is called once for each such algorithm supported by a driver. -+ */ -+int -+crypto_register(u_int32_t driverid, int alg, u_int16_t maxoplen, -+ u_int32_t flags) -+{ -+ struct cryptocap *cap; -+ int err; -+ unsigned long d_flags; -+ -+ dprintk("%s(id=0x%x, alg=%d, maxoplen=%d, flags=0x%x)\n", __FUNCTION__, -+ driverid, alg, maxoplen, flags); -+ -+ CRYPTO_DRIVER_LOCK(); -+ -+ cap = crypto_checkdriver(driverid); -+ /* NB: algorithms are in the range [1..max] */ -+ if (cap != NULL && -+ (CRYPTO_ALGORITHM_MIN <= alg && alg <= CRYPTO_ALGORITHM_MAX)) { -+ /* -+ * XXX Do some performance testing to determine placing. -+ * XXX We probably need an auxiliary data structure that -+ * XXX describes relative performances. -+ */ -+ -+ cap->cc_alg[alg] = flags | CRYPTO_ALG_FLAG_SUPPORTED; -+ cap->cc_max_op_len[alg] = maxoplen; -+ if (bootverbose) -+ printf("crypto: %s registers alg %u flags %u maxoplen %u\n" -+ , device_get_nameunit(cap->cc_dev) -+ , alg -+ , flags -+ , maxoplen -+ ); -+ cap->cc_sessions = 0; /* Unmark */ -+ err = 0; -+ } else -+ err = EINVAL; -+ -+ CRYPTO_DRIVER_UNLOCK(); -+ return err; -+} -+ -+static void -+driver_finis(struct cryptocap *cap) -+{ -+ u_int32_t ses, kops; -+ -+ CRYPTO_DRIVER_ASSERT(); -+ -+ ses = cap->cc_sessions; -+ kops = cap->cc_koperations; -+ bzero(cap, sizeof(*cap)); -+ if (ses != 0 || kops != 0) { -+ /* -+ * If there are pending sessions, -+ * just mark as invalid. -+ */ -+ cap->cc_flags |= CRYPTOCAP_F_CLEANUP; -+ cap->cc_sessions = ses; -+ cap->cc_koperations = kops; -+ } -+} -+ -+/* -+ * Unregister a crypto driver. If there are pending sessions using it, -+ * leave enough information around so that subsequent calls using those -+ * sessions will correctly detect the driver has been unregistered and -+ * reroute requests. -+ */ -+int -+crypto_unregister(u_int32_t driverid, int alg) -+{ -+ struct cryptocap *cap; -+ int i, err; -+ unsigned long d_flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ CRYPTO_DRIVER_LOCK(); -+ -+ cap = crypto_checkdriver(driverid); -+ if (cap != NULL && -+ (CRYPTO_ALGORITHM_MIN <= alg && alg <= CRYPTO_ALGORITHM_MAX) && -+ cap->cc_alg[alg] != 0) { -+ cap->cc_alg[alg] = 0; -+ cap->cc_max_op_len[alg] = 0; -+ -+ /* Was this the last algorithm ? */ -+ for (i = 1; i <= CRYPTO_ALGORITHM_MAX; i++) -+ if (cap->cc_alg[i] != 0) -+ break; -+ -+ if (i == CRYPTO_ALGORITHM_MAX + 1) -+ driver_finis(cap); -+ err = 0; -+ } else -+ err = EINVAL; -+ CRYPTO_DRIVER_UNLOCK(); -+ return err; -+} -+ -+/* -+ * Unregister all algorithms associated with a crypto driver. -+ * If there are pending sessions using it, leave enough information -+ * around so that subsequent calls using those sessions will -+ * correctly detect the driver has been unregistered and reroute -+ * requests. -+ */ -+int -+crypto_unregister_all(u_int32_t driverid) -+{ -+ struct cryptocap *cap; -+ int err; -+ unsigned long d_flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ CRYPTO_DRIVER_LOCK(); -+ cap = crypto_checkdriver(driverid); -+ if (cap != NULL) { -+ driver_finis(cap); -+ err = 0; -+ } else -+ err = EINVAL; -+ CRYPTO_DRIVER_UNLOCK(); -+ -+ return err; -+} -+ -+/* -+ * Clear blockage on a driver. The what parameter indicates whether -+ * the driver is now ready for cryptop's and/or cryptokop's. -+ */ -+int -+crypto_unblock(u_int32_t driverid, int what) -+{ -+ struct cryptocap *cap; -+ int err; -+ unsigned long q_flags; -+ -+ CRYPTO_Q_LOCK(); -+ cap = crypto_checkdriver(driverid); -+ if (cap != NULL) { -+ if (what & CRYPTO_SYMQ) { -+ cap->cc_qblocked = 0; -+ cap->cc_unqblocked = 0; -+ crypto_all_qblocked = 0; -+ } -+ if (what & CRYPTO_ASYMQ) { -+ cap->cc_kqblocked = 0; -+ cap->cc_unkqblocked = 0; -+ crypto_all_kqblocked = 0; -+ } -+ wake_up_interruptible(&cryptoproc_wait); -+ err = 0; -+ } else -+ err = EINVAL; -+ CRYPTO_Q_UNLOCK(); //DAVIDM should this be a driver lock -+ -+ return err; -+} -+ -+/* -+ * Add a crypto request to a queue, to be processed by the kernel thread. -+ */ -+int -+crypto_dispatch(struct cryptop *crp) -+{ -+ struct cryptocap *cap; -+ int result = -1; -+ unsigned long q_flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ cryptostats.cs_ops++; -+ -+ CRYPTO_Q_LOCK(); -+ if (crypto_q_cnt >= crypto_q_max) { -+ cryptostats.cs_drops++; -+ CRYPTO_Q_UNLOCK(); -+ return ENOMEM; -+ } -+ crypto_q_cnt++; -+ -+ /* make sure we are starting a fresh run on this crp. */ -+ crp->crp_flags &= ~CRYPTO_F_DONE; -+ crp->crp_etype = 0; -+ -+ /* -+ * Caller marked the request to be processed immediately; dispatch -+ * it directly to the driver unless the driver is currently blocked. -+ */ -+ if ((crp->crp_flags & CRYPTO_F_BATCH) == 0) { -+ int hid = CRYPTO_SESID2HID(crp->crp_sid); -+ cap = crypto_checkdriver(hid); -+ /* Driver cannot disappear when there is an active session. */ -+ KASSERT(cap != NULL, ("%s: Driver disappeared.", __func__)); -+ if (!cap->cc_qblocked) { -+ crypto_all_qblocked = 0; -+ crypto_drivers[hid].cc_unqblocked = 1; -+ CRYPTO_Q_UNLOCK(); -+ result = crypto_invoke(cap, crp, 0); -+ CRYPTO_Q_LOCK(); -+ if (result == ERESTART) -+ if (crypto_drivers[hid].cc_unqblocked) -+ crypto_drivers[hid].cc_qblocked = 1; -+ crypto_drivers[hid].cc_unqblocked = 0; -+ } -+ } -+ if (result == ERESTART) { -+ /* -+ * The driver ran out of resources, mark the -+ * driver ``blocked'' for cryptop's and put -+ * the request back in the queue. It would -+ * best to put the request back where we got -+ * it but that's hard so for now we put it -+ * at the front. This should be ok; putting -+ * it at the end does not work. -+ */ -+ list_add(&crp->crp_next, &crp_q); -+ cryptostats.cs_blocks++; -+ result = 0; -+ } else if (result == -1) { -+ TAILQ_INSERT_TAIL(&crp_q, crp, crp_next); -+ result = 0; -+ } -+ wake_up_interruptible(&cryptoproc_wait); -+ CRYPTO_Q_UNLOCK(); -+ return result; -+} -+ -+/* -+ * Add an asymetric crypto request to a queue, -+ * to be processed by the kernel thread. -+ */ -+int -+crypto_kdispatch(struct cryptkop *krp) -+{ -+ int error; -+ unsigned long q_flags; -+ -+ cryptostats.cs_kops++; -+ -+ error = crypto_kinvoke(krp, krp->krp_crid); -+ if (error == ERESTART) { -+ CRYPTO_Q_LOCK(); -+ TAILQ_INSERT_TAIL(&crp_kq, krp, krp_next); -+ wake_up_interruptible(&cryptoproc_wait); -+ CRYPTO_Q_UNLOCK(); -+ error = 0; -+ } -+ return error; -+} -+ -+/* -+ * Verify a driver is suitable for the specified operation. -+ */ -+static __inline int -+kdriver_suitable(const struct cryptocap *cap, const struct cryptkop *krp) -+{ -+ return (cap->cc_kalg[krp->krp_op] & CRYPTO_ALG_FLAG_SUPPORTED) != 0; -+} -+ -+/* -+ * Select a driver for an asym operation. The driver must -+ * support the necessary algorithm. The caller can constrain -+ * which device is selected with the flags parameter. The -+ * algorithm we use here is pretty stupid; just use the first -+ * driver that supports the algorithms we need. If there are -+ * multiple suitable drivers we choose the driver with the -+ * fewest active operations. We prefer hardware-backed -+ * drivers to software ones when either may be used. -+ */ -+static struct cryptocap * -+crypto_select_kdriver(const struct cryptkop *krp, int flags) -+{ -+ struct cryptocap *cap, *best, *blocked; -+ int match, hid; -+ -+ CRYPTO_DRIVER_ASSERT(); -+ -+ /* -+ * Look first for hardware crypto devices if permitted. -+ */ -+ if (flags & CRYPTOCAP_F_HARDWARE) -+ match = CRYPTOCAP_F_HARDWARE; -+ else -+ match = CRYPTOCAP_F_SOFTWARE; -+ best = NULL; -+ blocked = NULL; -+again: -+ for (hid = 0; hid < crypto_drivers_num; hid++) { -+ cap = &crypto_drivers[hid]; -+ /* -+ * If it's not initialized, is in the process of -+ * going away, or is not appropriate (hardware -+ * or software based on match), then skip. -+ */ -+ if (cap->cc_dev == NULL || -+ (cap->cc_flags & CRYPTOCAP_F_CLEANUP) || -+ (cap->cc_flags & match) == 0) -+ continue; -+ -+ /* verify all the algorithms are supported. */ -+ if (kdriver_suitable(cap, krp)) { -+ if (best == NULL || -+ cap->cc_koperations < best->cc_koperations) -+ best = cap; -+ } -+ } -+ if (best != NULL) -+ return best; -+ if (match == CRYPTOCAP_F_HARDWARE && (flags & CRYPTOCAP_F_SOFTWARE)) { -+ /* sort of an Algol 68-style for loop */ -+ match = CRYPTOCAP_F_SOFTWARE; -+ goto again; -+ } -+ return best; -+} -+ -+/* -+ * Dispatch an assymetric crypto request. -+ */ -+static int -+crypto_kinvoke(struct cryptkop *krp, int crid) -+{ -+ struct cryptocap *cap = NULL; -+ int error; -+ unsigned long d_flags; -+ -+ KASSERT(krp != NULL, ("%s: krp == NULL", __func__)); -+ KASSERT(krp->krp_callback != NULL, -+ ("%s: krp->crp_callback == NULL", __func__)); -+ -+ CRYPTO_DRIVER_LOCK(); -+ if ((crid & (CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE)) == 0) { -+ cap = crypto_checkdriver(crid); -+ if (cap != NULL) { -+ /* -+ * Driver present, it must support the necessary -+ * algorithm and, if s/w drivers are excluded, -+ * it must be registered as hardware-backed. -+ */ -+ if (!kdriver_suitable(cap, krp) || -+ (!crypto_devallowsoft && -+ (cap->cc_flags & CRYPTOCAP_F_HARDWARE) == 0)) -+ cap = NULL; -+ } -+ } else { -+ /* -+ * No requested driver; select based on crid flags. -+ */ -+ if (!crypto_devallowsoft) /* NB: disallow s/w drivers */ -+ crid &= ~CRYPTOCAP_F_SOFTWARE; -+ cap = crypto_select_kdriver(krp, crid); -+ } -+ if (cap != NULL && !cap->cc_kqblocked) { -+ krp->krp_hid = cap - crypto_drivers; -+ cap->cc_koperations++; -+ CRYPTO_DRIVER_UNLOCK(); -+ error = CRYPTODEV_KPROCESS(cap->cc_dev, krp, 0); -+ CRYPTO_DRIVER_LOCK(); -+ if (error == ERESTART) { -+ cap->cc_koperations--; -+ CRYPTO_DRIVER_UNLOCK(); -+ return (error); -+ } -+ /* return the actual device used */ -+ krp->krp_crid = krp->krp_hid; -+ } else { -+ /* -+ * NB: cap is !NULL if device is blocked; in -+ * that case return ERESTART so the operation -+ * is resubmitted if possible. -+ */ -+ error = (cap == NULL) ? ENODEV : ERESTART; -+ } -+ CRYPTO_DRIVER_UNLOCK(); -+ -+ if (error) { -+ krp->krp_status = error; -+ crypto_kdone(krp); -+ } -+ return 0; -+} -+ -+ -+/* -+ * Dispatch a crypto request to the appropriate crypto devices. -+ */ -+static int -+crypto_invoke(struct cryptocap *cap, struct cryptop *crp, int hint) -+{ -+ KASSERT(crp != NULL, ("%s: crp == NULL", __func__)); -+ KASSERT(crp->crp_callback != NULL, -+ ("%s: crp->crp_callback == NULL", __func__)); -+ KASSERT(crp->crp_desc != NULL, ("%s: crp->crp_desc == NULL", __func__)); -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+#ifdef CRYPTO_TIMING -+ if (crypto_timing) -+ crypto_tstat(&cryptostats.cs_invoke, &crp->crp_tstamp); -+#endif -+ if (cap->cc_flags & CRYPTOCAP_F_CLEANUP) { -+ struct cryptodesc *crd; -+ u_int64_t nid; -+ -+ /* -+ * Driver has unregistered; migrate the session and return -+ * an error to the caller so they'll resubmit the op. -+ * -+ * XXX: What if there are more already queued requests for this -+ * session? -+ */ -+ crypto_freesession(crp->crp_sid); -+ -+ for (crd = crp->crp_desc; crd->crd_next; crd = crd->crd_next) -+ crd->CRD_INI.cri_next = &(crd->crd_next->CRD_INI); -+ -+ /* XXX propagate flags from initial session? */ -+ if (crypto_newsession(&nid, &(crp->crp_desc->CRD_INI), -+ CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE) == 0) -+ crp->crp_sid = nid; -+ -+ crp->crp_etype = EAGAIN; -+ crypto_done(crp); -+ return 0; -+ } else { -+ /* -+ * Invoke the driver to process the request. -+ */ -+ return CRYPTODEV_PROCESS(cap->cc_dev, crp, hint); -+ } -+} -+ -+/* -+ * Release a set of crypto descriptors. -+ */ -+void -+crypto_freereq(struct cryptop *crp) -+{ -+ struct cryptodesc *crd; -+ -+ if (crp == NULL) -+ return; -+ -+#ifdef DIAGNOSTIC -+ { -+ struct cryptop *crp2; -+ unsigned long q_flags; -+ -+ CRYPTO_Q_LOCK(); -+ TAILQ_FOREACH(crp2, &crp_q, crp_next) { -+ KASSERT(crp2 != crp, -+ ("Freeing cryptop from the crypto queue (%p).", -+ crp)); -+ } -+ CRYPTO_Q_UNLOCK(); -+ CRYPTO_RETQ_LOCK(); -+ TAILQ_FOREACH(crp2, &crp_ret_q, crp_next) { -+ KASSERT(crp2 != crp, -+ ("Freeing cryptop from the return queue (%p).", -+ crp)); -+ } -+ CRYPTO_RETQ_UNLOCK(); -+ } -+#endif -+ -+ while ((crd = crp->crp_desc) != NULL) { -+ crp->crp_desc = crd->crd_next; -+ kmem_cache_free(cryptodesc_zone, crd); -+ } -+ kmem_cache_free(cryptop_zone, crp); -+} -+ -+/* -+ * Acquire a set of crypto descriptors. -+ */ -+struct cryptop * -+crypto_getreq(int num) -+{ -+ struct cryptodesc *crd; -+ struct cryptop *crp; -+ -+ crp = kmem_cache_alloc(cryptop_zone, SLAB_ATOMIC); -+ if (crp != NULL) { -+ memset(crp, 0, sizeof(*crp)); -+ INIT_LIST_HEAD(&crp->crp_next); -+ init_waitqueue_head(&crp->crp_waitq); -+ while (num--) { -+ crd = kmem_cache_alloc(cryptodesc_zone, SLAB_ATOMIC); -+ if (crd == NULL) { -+ crypto_freereq(crp); -+ return NULL; -+ } -+ memset(crd, 0, sizeof(*crd)); -+ crd->crd_next = crp->crp_desc; -+ crp->crp_desc = crd; -+ } -+ } -+ return crp; -+} -+ -+/* -+ * Invoke the callback on behalf of the driver. -+ */ -+void -+crypto_done(struct cryptop *crp) -+{ -+ unsigned long q_flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if ((crp->crp_flags & CRYPTO_F_DONE) == 0) { -+ crp->crp_flags |= CRYPTO_F_DONE; -+ CRYPTO_Q_LOCK(); -+ crypto_q_cnt--; -+ CRYPTO_Q_UNLOCK(); -+ } else -+ printk("crypto: crypto_done op already done, flags 0x%x", -+ crp->crp_flags); -+ if (crp->crp_etype != 0) -+ cryptostats.cs_errs++; -+ /* -+ * CBIMM means unconditionally do the callback immediately; -+ * CBIFSYNC means do the callback immediately only if the -+ * operation was done synchronously. Both are used to avoid -+ * doing extraneous context switches; the latter is mostly -+ * used with the software crypto driver. -+ */ -+ if ((crp->crp_flags & CRYPTO_F_CBIMM) || -+ ((crp->crp_flags & CRYPTO_F_CBIFSYNC) && -+ (CRYPTO_SESID2CAPS(crp->crp_sid) & CRYPTOCAP_F_SYNC))) { -+ /* -+ * Do the callback directly. This is ok when the -+ * callback routine does very little (e.g. the -+ * /dev/crypto callback method just does a wakeup). -+ */ -+ crp->crp_callback(crp); -+ } else { -+ unsigned long r_flags; -+ /* -+ * Normal case; queue the callback for the thread. -+ */ -+ CRYPTO_RETQ_LOCK(); -+ wake_up_interruptible(&cryptoretproc_wait);/* shared wait channel */ -+ TAILQ_INSERT_TAIL(&crp_ret_q, crp, crp_next); -+ CRYPTO_RETQ_UNLOCK(); -+ } -+} -+ -+/* -+ * Invoke the callback on behalf of the driver. -+ */ -+void -+crypto_kdone(struct cryptkop *krp) -+{ -+ struct cryptocap *cap; -+ unsigned long d_flags; -+ -+ if ((krp->krp_flags & CRYPTO_KF_DONE) != 0) -+ printk("crypto: crypto_kdone op already done, flags 0x%x", -+ krp->krp_flags); -+ krp->krp_flags |= CRYPTO_KF_DONE; -+ if (krp->krp_status != 0) -+ cryptostats.cs_kerrs++; -+ -+ CRYPTO_DRIVER_LOCK(); -+ /* XXX: What if driver is loaded in the meantime? */ -+ if (krp->krp_hid < crypto_drivers_num) { -+ cap = &crypto_drivers[krp->krp_hid]; -+ cap->cc_koperations--; -+ KASSERT(cap->cc_koperations >= 0, ("cc_koperations < 0")); -+ if (cap->cc_flags & CRYPTOCAP_F_CLEANUP) -+ crypto_remove(cap); -+ } -+ CRYPTO_DRIVER_UNLOCK(); -+ -+ /* -+ * CBIMM means unconditionally do the callback immediately; -+ * This is used to avoid doing extraneous context switches -+ */ -+ if ((krp->krp_flags & CRYPTO_KF_CBIMM)) { -+ /* -+ * Do the callback directly. This is ok when the -+ * callback routine does very little (e.g. the -+ * /dev/crypto callback method just does a wakeup). -+ */ -+ krp->krp_callback(krp); -+ } else { -+ unsigned long r_flags; -+ /* -+ * Normal case; queue the callback for the thread. -+ */ -+ CRYPTO_RETQ_LOCK(); -+ wake_up_interruptible(&cryptoretproc_wait);/* shared wait channel */ -+ TAILQ_INSERT_TAIL(&crp_ret_kq, krp, krp_next); -+ CRYPTO_RETQ_UNLOCK(); -+ } -+} -+ -+int -+crypto_getfeat(int *featp) -+{ -+ int hid, kalg, feat = 0; -+ unsigned long d_flags; -+ -+ CRYPTO_DRIVER_LOCK(); -+ for (hid = 0; hid < crypto_drivers_num; hid++) { -+ const struct cryptocap *cap = &crypto_drivers[hid]; -+ -+ if ((cap->cc_flags & CRYPTOCAP_F_SOFTWARE) && -+ !crypto_devallowsoft) { -+ continue; -+ } -+ for (kalg = 0; kalg < CRK_ALGORITHM_MAX; kalg++) -+ if (cap->cc_kalg[kalg] & CRYPTO_ALG_FLAG_SUPPORTED) -+ feat |= 1 << kalg; -+ } -+ CRYPTO_DRIVER_UNLOCK(); -+ *featp = feat; -+ return (0); -+} -+ -+/* -+ * Crypto thread, dispatches crypto requests. -+ */ -+static int -+crypto_proc(void *arg) -+{ -+ struct cryptop *crp, *submit; -+ struct cryptkop *krp, *krpp; -+ struct cryptocap *cap; -+ u_int32_t hid; -+ int result, hint; -+ unsigned long q_flags; -+ int loopcount = 0; -+ -+ set_current_state(TASK_INTERRUPTIBLE); -+ -+ CRYPTO_Q_LOCK(); -+ for (;;) { -+ /* -+ * we need to make sure we don't get into a busy loop with nothing -+ * to do, the two crypto_all_*blocked vars help us find out when -+ * we are all full and can do nothing on any driver or Q. If so we -+ * wait for an unblock. -+ */ -+ crypto_all_qblocked = !list_empty(&crp_q); -+ -+ /* -+ * Find the first element in the queue that can be -+ * processed and look-ahead to see if multiple ops -+ * are ready for the same driver. -+ */ -+ submit = NULL; -+ hint = 0; -+ list_for_each_entry(crp, &crp_q, crp_next) { -+ hid = CRYPTO_SESID2HID(crp->crp_sid); -+ cap = crypto_checkdriver(hid); -+ /* -+ * Driver cannot disappear when there is an active -+ * session. -+ */ -+ KASSERT(cap != NULL, ("%s:%u Driver disappeared.", -+ __func__, __LINE__)); -+ if (cap == NULL || cap->cc_dev == NULL) { -+ /* Op needs to be migrated, process it. */ -+ if (submit == NULL) -+ submit = crp; -+ break; -+ } -+ if (!cap->cc_qblocked) { -+ if (submit != NULL) { -+ /* -+ * We stop on finding another op, -+ * regardless whether its for the same -+ * driver or not. We could keep -+ * searching the queue but it might be -+ * better to just use a per-driver -+ * queue instead. -+ */ -+ if (CRYPTO_SESID2HID(submit->crp_sid) == hid) -+ hint = CRYPTO_HINT_MORE; -+ break; -+ } else { -+ submit = crp; -+ if ((submit->crp_flags & CRYPTO_F_BATCH) == 0) -+ break; -+ /* keep scanning for more are q'd */ -+ } -+ } -+ } -+ if (submit != NULL) { -+ hid = CRYPTO_SESID2HID(submit->crp_sid); -+ crypto_all_qblocked = 0; -+ list_del(&submit->crp_next); -+ crypto_drivers[hid].cc_unqblocked = 1; -+ cap = crypto_checkdriver(hid); -+ CRYPTO_Q_UNLOCK(); -+ KASSERT(cap != NULL, ("%s:%u Driver disappeared.", -+ __func__, __LINE__)); -+ result = crypto_invoke(cap, submit, hint); -+ CRYPTO_Q_LOCK(); -+ if (result == ERESTART) { -+ /* -+ * The driver ran out of resources, mark the -+ * driver ``blocked'' for cryptop's and put -+ * the request back in the queue. It would -+ * best to put the request back where we got -+ * it but that's hard so for now we put it -+ * at the front. This should be ok; putting -+ * it at the end does not work. -+ */ -+ /* XXX validate sid again? */ -+ list_add(&submit->crp_next, &crp_q); -+ cryptostats.cs_blocks++; -+ if (crypto_drivers[hid].cc_unqblocked) -+ crypto_drivers[hid].cc_qblocked=0; -+ crypto_drivers[hid].cc_unqblocked=0; -+ } -+ crypto_drivers[hid].cc_unqblocked = 0; -+ } -+ -+ crypto_all_kqblocked = !list_empty(&crp_kq); -+ -+ /* As above, but for key ops */ -+ krp = NULL; -+ list_for_each_entry(krpp, &crp_kq, krp_next) { -+ cap = crypto_checkdriver(krpp->krp_hid); -+ if (cap == NULL || cap->cc_dev == NULL) { -+ /* -+ * Operation needs to be migrated, invalidate -+ * the assigned device so it will reselect a -+ * new one below. Propagate the original -+ * crid selection flags if supplied. -+ */ -+ krp->krp_hid = krp->krp_crid & -+ (CRYPTOCAP_F_SOFTWARE|CRYPTOCAP_F_HARDWARE); -+ if (krp->krp_hid == 0) -+ krp->krp_hid = -+ CRYPTOCAP_F_SOFTWARE|CRYPTOCAP_F_HARDWARE; -+ break; -+ } -+ if (!cap->cc_kqblocked) { -+ krp = krpp; -+ break; -+ } -+ } -+ if (krp != NULL) { -+ crypto_all_kqblocked = 0; -+ list_del(&krp->krp_next); -+ crypto_drivers[krp->krp_hid].cc_kqblocked = 1; -+ CRYPTO_Q_UNLOCK(); -+ result = crypto_kinvoke(krp, krp->krp_hid); -+ CRYPTO_Q_LOCK(); -+ if (result == ERESTART) { -+ /* -+ * The driver ran out of resources, mark the -+ * driver ``blocked'' for cryptkop's and put -+ * the request back in the queue. It would -+ * best to put the request back where we got -+ * it but that's hard so for now we put it -+ * at the front. This should be ok; putting -+ * it at the end does not work. -+ */ -+ /* XXX validate sid again? */ -+ list_add(&krp->krp_next, &crp_kq); -+ cryptostats.cs_kblocks++; -+ } else -+ crypto_drivers[krp->krp_hid].cc_kqblocked = 0; -+ } -+ -+ if (submit == NULL && krp == NULL) { -+ /* -+ * Nothing more to be processed. Sleep until we're -+ * woken because there are more ops to process. -+ * This happens either by submission or by a driver -+ * becoming unblocked and notifying us through -+ * crypto_unblock. Note that when we wakeup we -+ * start processing each queue again from the -+ * front. It's not clear that it's important to -+ * preserve this ordering since ops may finish -+ * out of order if dispatched to different devices -+ * and some become blocked while others do not. -+ */ -+ dprintk("%s - sleeping (qe=%d qb=%d kqe=%d kqb=%d)\n", -+ __FUNCTION__, -+ list_empty(&crp_q), crypto_all_qblocked, -+ list_empty(&crp_kq), crypto_all_kqblocked); -+ loopcount = 0; -+ CRYPTO_Q_UNLOCK(); -+ wait_event_interruptible(cryptoproc_wait, -+ !(list_empty(&crp_q) || crypto_all_qblocked) || -+ !(list_empty(&crp_kq) || crypto_all_kqblocked) || -+ kthread_should_stop()); -+ if (signal_pending (current)) { -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ spin_lock_irq(¤t->sigmask_lock); -+#endif -+ flush_signals(current); -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ spin_unlock_irq(¤t->sigmask_lock); -+#endif -+ } -+ CRYPTO_Q_LOCK(); -+ dprintk("%s - awake\n", __FUNCTION__); -+ if (kthread_should_stop()) -+ break; -+ cryptostats.cs_intrs++; -+ } else if (loopcount > crypto_max_loopcount) { -+ /* -+ * Give other processes a chance to run if we've -+ * been using the CPU exclusively for a while. -+ */ -+ loopcount = 0; -+ CRYPTO_Q_UNLOCK(); -+ schedule(); -+ CRYPTO_Q_LOCK(); -+ } -+ loopcount++; -+ } -+ CRYPTO_Q_UNLOCK(); -+ return 0; -+} -+ -+/* -+ * Crypto returns thread, does callbacks for processed crypto requests. -+ * Callbacks are done here, rather than in the crypto drivers, because -+ * callbacks typically are expensive and would slow interrupt handling. -+ */ -+static int -+crypto_ret_proc(void *arg) -+{ -+ struct cryptop *crpt; -+ struct cryptkop *krpt; -+ unsigned long r_flags; -+ -+ set_current_state(TASK_INTERRUPTIBLE); -+ -+ CRYPTO_RETQ_LOCK(); -+ for (;;) { -+ /* Harvest return q's for completed ops */ -+ crpt = NULL; -+ if (!list_empty(&crp_ret_q)) -+ crpt = list_entry(crp_ret_q.next, typeof(*crpt), crp_next); -+ if (crpt != NULL) -+ list_del(&crpt->crp_next); -+ -+ krpt = NULL; -+ if (!list_empty(&crp_ret_kq)) -+ krpt = list_entry(crp_ret_kq.next, typeof(*krpt), krp_next); -+ if (krpt != NULL) -+ list_del(&krpt->krp_next); -+ -+ if (crpt != NULL || krpt != NULL) { -+ CRYPTO_RETQ_UNLOCK(); -+ /* -+ * Run callbacks unlocked. -+ */ -+ if (crpt != NULL) -+ crpt->crp_callback(crpt); -+ if (krpt != NULL) -+ krpt->krp_callback(krpt); -+ CRYPTO_RETQ_LOCK(); -+ } else { -+ /* -+ * Nothing more to be processed. Sleep until we're -+ * woken because there are more returns to process. -+ */ -+ dprintk("%s - sleeping\n", __FUNCTION__); -+ CRYPTO_RETQ_UNLOCK(); -+ wait_event_interruptible(cryptoretproc_wait, -+ !list_empty(&crp_ret_q) || -+ !list_empty(&crp_ret_kq) || -+ kthread_should_stop()); -+ if (signal_pending (current)) { -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ spin_lock_irq(¤t->sigmask_lock); -+#endif -+ flush_signals(current); -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ spin_unlock_irq(¤t->sigmask_lock); -+#endif -+ } -+ CRYPTO_RETQ_LOCK(); -+ dprintk("%s - awake\n", __FUNCTION__); -+ if (kthread_should_stop()) { -+ dprintk("%s - EXITING!\n", __FUNCTION__); -+ break; -+ } -+ cryptostats.cs_rets++; -+ } -+ } -+ CRYPTO_RETQ_UNLOCK(); -+ return 0; -+} -+ -+ -+#if 0 /* should put this into /proc or something */ -+static void -+db_show_drivers(void) -+{ -+ int hid; -+ -+ db_printf("%12s %4s %4s %8s %2s %2s\n" -+ , "Device" -+ , "Ses" -+ , "Kops" -+ , "Flags" -+ , "QB" -+ , "KB" -+ ); -+ for (hid = 0; hid < crypto_drivers_num; hid++) { -+ const struct cryptocap *cap = &crypto_drivers[hid]; -+ if (cap->cc_dev == NULL) -+ continue; -+ db_printf("%-12s %4u %4u %08x %2u %2u\n" -+ , device_get_nameunit(cap->cc_dev) -+ , cap->cc_sessions -+ , cap->cc_koperations -+ , cap->cc_flags -+ , cap->cc_qblocked -+ , cap->cc_kqblocked -+ ); -+ } -+} -+ -+DB_SHOW_COMMAND(crypto, db_show_crypto) -+{ -+ struct cryptop *crp; -+ -+ db_show_drivers(); -+ db_printf("\n"); -+ -+ db_printf("%4s %8s %4s %4s %4s %4s %8s %8s\n", -+ "HID", "Caps", "Ilen", "Olen", "Etype", "Flags", -+ "Desc", "Callback"); -+ TAILQ_FOREACH(crp, &crp_q, crp_next) { -+ db_printf("%4u %08x %4u %4u %4u %04x %8p %8p\n" -+ , (int) CRYPTO_SESID2HID(crp->crp_sid) -+ , (int) CRYPTO_SESID2CAPS(crp->crp_sid) -+ , crp->crp_ilen, crp->crp_olen -+ , crp->crp_etype -+ , crp->crp_flags -+ , crp->crp_desc -+ , crp->crp_callback -+ ); -+ } -+ if (!TAILQ_EMPTY(&crp_ret_q)) { -+ db_printf("\n%4s %4s %4s %8s\n", -+ "HID", "Etype", "Flags", "Callback"); -+ TAILQ_FOREACH(crp, &crp_ret_q, crp_next) { -+ db_printf("%4u %4u %04x %8p\n" -+ , (int) CRYPTO_SESID2HID(crp->crp_sid) -+ , crp->crp_etype -+ , crp->crp_flags -+ , crp->crp_callback -+ ); -+ } -+ } -+} -+ -+DB_SHOW_COMMAND(kcrypto, db_show_kcrypto) -+{ -+ struct cryptkop *krp; -+ -+ db_show_drivers(); -+ db_printf("\n"); -+ -+ db_printf("%4s %5s %4s %4s %8s %4s %8s\n", -+ "Op", "Status", "#IP", "#OP", "CRID", "HID", "Callback"); -+ TAILQ_FOREACH(krp, &crp_kq, krp_next) { -+ db_printf("%4u %5u %4u %4u %08x %4u %8p\n" -+ , krp->krp_op -+ , krp->krp_status -+ , krp->krp_iparams, krp->krp_oparams -+ , krp->krp_crid, krp->krp_hid -+ , krp->krp_callback -+ ); -+ } -+ if (!TAILQ_EMPTY(&crp_ret_q)) { -+ db_printf("%4s %5s %8s %4s %8s\n", -+ "Op", "Status", "CRID", "HID", "Callback"); -+ TAILQ_FOREACH(krp, &crp_ret_kq, krp_next) { -+ db_printf("%4u %5u %08x %4u %8p\n" -+ , krp->krp_op -+ , krp->krp_status -+ , krp->krp_crid, krp->krp_hid -+ , krp->krp_callback -+ ); -+ } -+ } -+} -+#endif -+ -+ -+static int -+crypto_init(void) -+{ -+ int error; -+ unsigned long cpu; -+ -+ dprintk("%s(%p)\n", __FUNCTION__, (void *) crypto_init); -+ -+ if (crypto_initted) -+ return 0; -+ crypto_initted = 1; -+ -+ spin_lock_init(&crypto_drivers_lock); -+ spin_lock_init(&crypto_q_lock); -+ spin_lock_init(&crypto_ret_q_lock); -+ -+ cryptop_zone = kmem_cache_create("cryptop", sizeof(struct cryptop), -+ 0, SLAB_HWCACHE_ALIGN, NULL -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) -+ , NULL -+#endif -+ ); -+ -+ cryptodesc_zone = kmem_cache_create("cryptodesc", sizeof(struct cryptodesc), -+ 0, SLAB_HWCACHE_ALIGN, NULL -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) -+ , NULL -+#endif -+ ); -+ -+ if (cryptodesc_zone == NULL || cryptop_zone == NULL) { -+ printk("crypto: crypto_init cannot setup crypto zones\n"); -+ error = ENOMEM; -+ goto bad; -+ } -+ -+ crypto_drivers_num = CRYPTO_DRIVERS_INITIAL; -+ crypto_drivers = kmalloc(crypto_drivers_num * sizeof(struct cryptocap), -+ GFP_KERNEL); -+ if (crypto_drivers == NULL) { -+ printk("crypto: crypto_init cannot setup crypto drivers\n"); -+ error = ENOMEM; -+ goto bad; -+ } -+ -+ memset(crypto_drivers, 0, crypto_drivers_num * sizeof(struct cryptocap)); -+ -+ ocf_for_each_cpu(cpu) { -+ cryptoproc[cpu] = kthread_create(crypto_proc, (void *) cpu, -+ "ocf_%d", (int) cpu); -+ if (IS_ERR(cryptoproc[cpu])) { -+ error = PTR_ERR(cryptoproc[cpu]); -+ printk("crypto: crypto_init cannot start crypto thread; error %d", -+ error); -+ goto bad; -+ } -+ kthread_bind(cryptoproc[cpu], cpu); -+ wake_up_process(cryptoproc[cpu]); -+ -+ cryptoretproc[cpu] = kthread_create(crypto_ret_proc, (void *) cpu, -+ "ocf_ret_%d", (int) cpu); -+ if (IS_ERR(cryptoretproc[cpu])) { -+ error = PTR_ERR(cryptoretproc[cpu]); -+ printk("crypto: crypto_init cannot start cryptoret thread; error %d", -+ error); -+ goto bad; -+ } -+ kthread_bind(cryptoretproc[cpu], cpu); -+ wake_up_process(cryptoretproc[cpu]); -+ } -+ -+ return 0; -+bad: -+ crypto_exit(); -+ return error; -+} -+ -+ -+static void -+crypto_exit(void) -+{ -+ int cpu; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ /* -+ * Terminate any crypto threads. -+ */ -+ ocf_for_each_cpu(cpu) { -+ kthread_stop(cryptoproc[cpu]); -+ kthread_stop(cryptoretproc[cpu]); -+ } -+ -+ /* -+ * Reclaim dynamically allocated resources. -+ */ -+ if (crypto_drivers != NULL) -+ kfree(crypto_drivers); -+ -+ if (cryptodesc_zone != NULL) -+ kmem_cache_destroy(cryptodesc_zone); -+ if (cryptop_zone != NULL) -+ kmem_cache_destroy(cryptop_zone); -+} -+ -+ -+EXPORT_SYMBOL(crypto_newsession); -+EXPORT_SYMBOL(crypto_freesession); -+EXPORT_SYMBOL(crypto_get_driverid); -+EXPORT_SYMBOL(crypto_kregister); -+EXPORT_SYMBOL(crypto_register); -+EXPORT_SYMBOL(crypto_unregister); -+EXPORT_SYMBOL(crypto_unregister_all); -+EXPORT_SYMBOL(crypto_unblock); -+EXPORT_SYMBOL(crypto_dispatch); -+EXPORT_SYMBOL(crypto_kdispatch); -+EXPORT_SYMBOL(crypto_freereq); -+EXPORT_SYMBOL(crypto_getreq); -+EXPORT_SYMBOL(crypto_done); -+EXPORT_SYMBOL(crypto_kdone); -+EXPORT_SYMBOL(crypto_getfeat); -+EXPORT_SYMBOL(crypto_userasymcrypto); -+EXPORT_SYMBOL(crypto_getcaps); -+EXPORT_SYMBOL(crypto_find_driver); -+EXPORT_SYMBOL(crypto_find_device_byhid); -+ -+module_init(crypto_init); -+module_exit(crypto_exit); -+ -+MODULE_LICENSE("BSD"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("OCF (OpenBSD Cryptographic Framework)"); -diff -Nur linux-3.0.4.orig/crypto/ocf/cryptocteon/Makefile linux-3.0.4/crypto/ocf/cryptocteon/Makefile ---- linux-3.0.4.orig/crypto/ocf/cryptocteon/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/cryptocteon/Makefile 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,17 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+obj-$(CONFIG_OCF_CRYPTOCTEON) += cryptocteon.o -+ -+obj ?= . -+EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ -+ -+ifdef CONFIG_OCF_CRYPTOCTEON -+# you need the cavium crypto component installed -+EXTRA_CFLAGS += -I$(ROOTDIR)/prop/include -+endif -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/cryptocteon/README.txt linux-3.0.4/crypto/ocf/cryptocteon/README.txt ---- linux-3.0.4.orig/crypto/ocf/cryptocteon/README.txt 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/cryptocteon/README.txt 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,11 @@ -+ -+You will need the CRYPTO package installed to build this driver, and -+potentially the ADK. -+ -+cavium_crypto sourced from: -+ -+ adk/components/source/cavium_ipsec_kame/cavium_ipsec.c -+ -+and significantly modified to suit use with OCF. All original -+copyright/ownership headers retained. -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/cryptocteon/cavium_crypto.c linux-3.0.4/crypto/ocf/cryptocteon/cavium_crypto.c ---- linux-3.0.4.orig/crypto/ocf/cryptocteon/cavium_crypto.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/cryptocteon/cavium_crypto.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,2283 @@ -+/* -+ * Copyright (c) 2009 David McCullough -+ * -+ * Copyright (c) 2003-2007 Cavium Networks (support@cavium.com). All rights -+ * reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * 1. Redistributions of source code must retain the above copyright notice, -+ * this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright notice, -+ * this list of conditions and the following disclaimer in the documentation -+ * and/or other materials provided with the distribution. -+ * 3. All advertising materials mentioning features or use of this software -+ * must display the following acknowledgement: -+ * This product includes software developed by Cavium Networks -+ * 4. Cavium Networks' name may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * This Software, including technical data, may be subject to U.S. export -+ * control laws, including the U.S. Export Administration Act and its -+ * associated regulations, and may be subject to export or import regulations -+ * in other countries. You warrant that You will comply strictly in all -+ * respects with all such regulations and acknowledge that you have the -+ * responsibility to obtain licenses to export, re-export or import the -+ * Software. -+ * -+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" AND -+ * WITH ALL FAULTS AND CAVIUM MAKES NO PROMISES, REPRESENTATIONS OR WARRANTIES, -+ * EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO THE -+ * SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR -+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM -+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, -+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF -+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR -+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR -+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. -+*/ -+/****************************************************************************/ -+ -+#include -+#include -+#include "octeon-asm.h" -+ -+/****************************************************************************/ -+ -+extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *); -+extern void octeon_crypto_disable(struct octeon_cop2_state *, unsigned long); -+ -+#define SG_INIT(s, p, i, l) \ -+ { \ -+ (i) = 0; \ -+ (l) = (s)[0].length; \ -+ (p) = (typeof(p)) sg_virt((s)); \ -+ CVMX_PREFETCH0((p)); \ -+ } -+ -+#define SG_CONSUME(s, p, i, l) \ -+ { \ -+ (p)++; \ -+ (l) -= sizeof(*(p)); \ -+ if ((l) < 0) { \ -+ dprintk("%s, %d: l = %d\n", __FILE__, __LINE__, l); \ -+ } else if ((l) == 0) { \ -+ (i)++; \ -+ (l) = (s)[0].length; \ -+ (p) = (typeof(p)) sg_virt(s); \ -+ CVMX_PREFETCH0((p)); \ -+ } \ -+ } -+ -+#define ESP_HEADER_LENGTH 8 -+#define DES_CBC_IV_LENGTH 8 -+#define AES_CBC_IV_LENGTH 16 -+#define ESP_HMAC_LEN 12 -+ -+#define ESP_HEADER_LENGTH 8 -+#define DES_CBC_IV_LENGTH 8 -+ -+/****************************************************************************/ -+ -+#define CVM_LOAD_SHA_UNIT(dat, next) { \ -+ if (next == 0) { \ -+ next = 1; \ -+ CVMX_MT_HSH_DAT (dat, 0); \ -+ } else if (next == 1) { \ -+ next = 2; \ -+ CVMX_MT_HSH_DAT (dat, 1); \ -+ } else if (next == 2) { \ -+ next = 3; \ -+ CVMX_MT_HSH_DAT (dat, 2); \ -+ } else if (next == 3) { \ -+ next = 4; \ -+ CVMX_MT_HSH_DAT (dat, 3); \ -+ } else if (next == 4) { \ -+ next = 5; \ -+ CVMX_MT_HSH_DAT (dat, 4); \ -+ } else if (next == 5) { \ -+ next = 6; \ -+ CVMX_MT_HSH_DAT (dat, 5); \ -+ } else if (next == 6) { \ -+ next = 7; \ -+ CVMX_MT_HSH_DAT (dat, 6); \ -+ } else { \ -+ CVMX_MT_HSH_STARTSHA (dat); \ -+ next = 0; \ -+ } \ -+} -+ -+#define CVM_LOAD2_SHA_UNIT(dat1, dat2, next) { \ -+ if (next == 0) { \ -+ CVMX_MT_HSH_DAT (dat1, 0); \ -+ CVMX_MT_HSH_DAT (dat2, 1); \ -+ next = 2; \ -+ } else if (next == 1) { \ -+ CVMX_MT_HSH_DAT (dat1, 1); \ -+ CVMX_MT_HSH_DAT (dat2, 2); \ -+ next = 3; \ -+ } else if (next == 2) { \ -+ CVMX_MT_HSH_DAT (dat1, 2); \ -+ CVMX_MT_HSH_DAT (dat2, 3); \ -+ next = 4; \ -+ } else if (next == 3) { \ -+ CVMX_MT_HSH_DAT (dat1, 3); \ -+ CVMX_MT_HSH_DAT (dat2, 4); \ -+ next = 5; \ -+ } else if (next == 4) { \ -+ CVMX_MT_HSH_DAT (dat1, 4); \ -+ CVMX_MT_HSH_DAT (dat2, 5); \ -+ next = 6; \ -+ } else if (next == 5) { \ -+ CVMX_MT_HSH_DAT (dat1, 5); \ -+ CVMX_MT_HSH_DAT (dat2, 6); \ -+ next = 7; \ -+ } else if (next == 6) { \ -+ CVMX_MT_HSH_DAT (dat1, 6); \ -+ CVMX_MT_HSH_STARTSHA (dat2); \ -+ next = 0; \ -+ } else { \ -+ CVMX_MT_HSH_STARTSHA (dat1); \ -+ CVMX_MT_HSH_DAT (dat2, 0); \ -+ next = 1; \ -+ } \ -+} -+ -+/****************************************************************************/ -+ -+#define CVM_LOAD_MD5_UNIT(dat, next) { \ -+ if (next == 0) { \ -+ next = 1; \ -+ CVMX_MT_HSH_DAT (dat, 0); \ -+ } else if (next == 1) { \ -+ next = 2; \ -+ CVMX_MT_HSH_DAT (dat, 1); \ -+ } else if (next == 2) { \ -+ next = 3; \ -+ CVMX_MT_HSH_DAT (dat, 2); \ -+ } else if (next == 3) { \ -+ next = 4; \ -+ CVMX_MT_HSH_DAT (dat, 3); \ -+ } else if (next == 4) { \ -+ next = 5; \ -+ CVMX_MT_HSH_DAT (dat, 4); \ -+ } else if (next == 5) { \ -+ next = 6; \ -+ CVMX_MT_HSH_DAT (dat, 5); \ -+ } else if (next == 6) { \ -+ next = 7; \ -+ CVMX_MT_HSH_DAT (dat, 6); \ -+ } else { \ -+ CVMX_MT_HSH_STARTMD5 (dat); \ -+ next = 0; \ -+ } \ -+} -+ -+#define CVM_LOAD2_MD5_UNIT(dat1, dat2, next) { \ -+ if (next == 0) { \ -+ CVMX_MT_HSH_DAT (dat1, 0); \ -+ CVMX_MT_HSH_DAT (dat2, 1); \ -+ next = 2; \ -+ } else if (next == 1) { \ -+ CVMX_MT_HSH_DAT (dat1, 1); \ -+ CVMX_MT_HSH_DAT (dat2, 2); \ -+ next = 3; \ -+ } else if (next == 2) { \ -+ CVMX_MT_HSH_DAT (dat1, 2); \ -+ CVMX_MT_HSH_DAT (dat2, 3); \ -+ next = 4; \ -+ } else if (next == 3) { \ -+ CVMX_MT_HSH_DAT (dat1, 3); \ -+ CVMX_MT_HSH_DAT (dat2, 4); \ -+ next = 5; \ -+ } else if (next == 4) { \ -+ CVMX_MT_HSH_DAT (dat1, 4); \ -+ CVMX_MT_HSH_DAT (dat2, 5); \ -+ next = 6; \ -+ } else if (next == 5) { \ -+ CVMX_MT_HSH_DAT (dat1, 5); \ -+ CVMX_MT_HSH_DAT (dat2, 6); \ -+ next = 7; \ -+ } else if (next == 6) { \ -+ CVMX_MT_HSH_DAT (dat1, 6); \ -+ CVMX_MT_HSH_STARTMD5 (dat2); \ -+ next = 0; \ -+ } else { \ -+ CVMX_MT_HSH_STARTMD5 (dat1); \ -+ CVMX_MT_HSH_DAT (dat2, 0); \ -+ next = 1; \ -+ } \ -+} -+ -+/****************************************************************************/ -+ -+static inline uint64_t -+swap64(uint64_t a) -+{ -+ return ((a >> 56) | -+ (((a >> 48) & 0xfful) << 8) | -+ (((a >> 40) & 0xfful) << 16) | -+ (((a >> 32) & 0xfful) << 24) | -+ (((a >> 24) & 0xfful) << 32) | -+ (((a >> 16) & 0xfful) << 40) | -+ (((a >> 8) & 0xfful) << 48) | (((a >> 0) & 0xfful) << 56)); -+} -+ -+/****************************************************************************/ -+ -+void -+octo_calc_hash(__u8 auth, unsigned char *key, uint64_t *inner, uint64_t *outer) -+{ -+ uint8_t hash_key[64]; -+ uint64_t *key1; -+ register uint64_t xor1 = 0x3636363636363636ULL; -+ register uint64_t xor2 = 0x5c5c5c5c5c5c5c5cULL; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ memset(hash_key, 0, sizeof(hash_key)); -+ memcpy(hash_key, (uint8_t *) key, (auth ? 20 : 16)); -+ key1 = (uint64_t *) hash_key; -+ flags = octeon_crypto_enable(&state); -+ if (auth) { -+ CVMX_MT_HSH_IV(0x67452301EFCDAB89ULL, 0); -+ CVMX_MT_HSH_IV(0x98BADCFE10325476ULL, 1); -+ CVMX_MT_HSH_IV(0xC3D2E1F000000000ULL, 2); -+ } else { -+ CVMX_MT_HSH_IV(0x0123456789ABCDEFULL, 0); -+ CVMX_MT_HSH_IV(0xFEDCBA9876543210ULL, 1); -+ } -+ -+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 0); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 1); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 2); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 3); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 4); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 5); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 6); -+ key1++; -+ if (auth) -+ CVMX_MT_HSH_STARTSHA((*key1 ^ xor1)); -+ else -+ CVMX_MT_HSH_STARTMD5((*key1 ^ xor1)); -+ -+ CVMX_MF_HSH_IV(inner[0], 0); -+ CVMX_MF_HSH_IV(inner[1], 1); -+ if (auth) { -+ inner[2] = 0; -+ CVMX_MF_HSH_IV(((uint64_t *) inner)[2], 2); -+ } -+ -+ memset(hash_key, 0, sizeof(hash_key)); -+ memcpy(hash_key, (uint8_t *) key, (auth ? 20 : 16)); -+ key1 = (uint64_t *) hash_key; -+ if (auth) { -+ CVMX_MT_HSH_IV(0x67452301EFCDAB89ULL, 0); -+ CVMX_MT_HSH_IV(0x98BADCFE10325476ULL, 1); -+ CVMX_MT_HSH_IV(0xC3D2E1F000000000ULL, 2); -+ } else { -+ CVMX_MT_HSH_IV(0x0123456789ABCDEFULL, 0); -+ CVMX_MT_HSH_IV(0xFEDCBA9876543210ULL, 1); -+ } -+ -+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 0); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 1); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 2); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 3); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 4); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 5); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 6); -+ key1++; -+ if (auth) -+ CVMX_MT_HSH_STARTSHA((*key1 ^ xor2)); -+ else -+ CVMX_MT_HSH_STARTMD5((*key1 ^ xor2)); -+ -+ CVMX_MF_HSH_IV(outer[0], 0); -+ CVMX_MF_HSH_IV(outer[1], 1); -+ if (auth) { -+ outer[2] = 0; -+ CVMX_MF_HSH_IV(outer[2], 2); -+ } -+ octeon_crypto_disable(&state, flags); -+ return; -+} -+ -+/****************************************************************************/ -+/* DES functions */ -+ -+int -+octo_des_cbc_encrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ uint64_t *data; -+ int data_i, data_l; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x7) || (crypt_off + crypt_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load 3DES Key */ -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ if (od->octo_encklen == 24) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ } else if (od->octo_encklen == 8) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ -+ CVMX_MT_3DES_IV(* (uint64_t *) ivp); -+ -+ while (crypt_off > 0) { -+ SG_CONSUME(sg, data, data_i, data_l); -+ crypt_off -= 8; -+ } -+ -+ while (crypt_len > 0) { -+ CVMX_MT_3DES_ENC_CBC(*data); -+ CVMX_MF_3DES_RESULT(*data); -+ SG_CONSUME(sg, data, data_i, data_l); -+ crypt_len -= 8; -+ } -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+ -+int -+octo_des_cbc_decrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ uint64_t *data; -+ int data_i, data_l; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x7) || (crypt_off + crypt_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load 3DES Key */ -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ if (od->octo_encklen == 24) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ } else if (od->octo_encklen == 8) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ -+ CVMX_MT_3DES_IV(* (uint64_t *) ivp); -+ -+ while (crypt_off > 0) { -+ SG_CONSUME(sg, data, data_i, data_l); -+ crypt_off -= 8; -+ } -+ -+ while (crypt_len > 0) { -+ CVMX_MT_3DES_DEC_CBC(*data); -+ CVMX_MF_3DES_RESULT(*data); -+ SG_CONSUME(sg, data, data_i, data_l); -+ crypt_len -= 8; -+ } -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+/****************************************************************************/ -+/* AES functions */ -+ -+int -+octo_aes_cbc_encrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ uint64_t *data, *pdata; -+ int data_i, data_l; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x7) || (crypt_off + crypt_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load AES Key */ -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ -+ if (od->octo_encklen == 16) { -+ CVMX_MT_AES_KEY(0x0, 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 24) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 32) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); -+ -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); -+ -+ while (crypt_off > 0) { -+ SG_CONSUME(sg, data, data_i, data_l); -+ crypt_off -= 8; -+ } -+ -+ while (crypt_len > 0) { -+ pdata = data; -+ CVMX_MT_AES_ENC_CBC0(*data); -+ SG_CONSUME(sg, data, data_i, data_l); -+ CVMX_MT_AES_ENC_CBC1(*data); -+ CVMX_MF_AES_RESULT(*pdata, 0); -+ CVMX_MF_AES_RESULT(*data, 1); -+ SG_CONSUME(sg, data, data_i, data_l); -+ crypt_len -= 16; -+ } -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+ -+int -+octo_aes_cbc_decrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ uint64_t *data, *pdata; -+ int data_i, data_l; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x7) || (crypt_off + crypt_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load AES Key */ -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ -+ if (od->octo_encklen == 16) { -+ CVMX_MT_AES_KEY(0x0, 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 24) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 32) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); -+ -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); -+ -+ while (crypt_off > 0) { -+ SG_CONSUME(sg, data, data_i, data_l); -+ crypt_off -= 8; -+ } -+ -+ while (crypt_len > 0) { -+ pdata = data; -+ CVMX_MT_AES_DEC_CBC0(*data); -+ SG_CONSUME(sg, data, data_i, data_l); -+ CVMX_MT_AES_DEC_CBC1(*data); -+ CVMX_MF_AES_RESULT(*pdata, 0); -+ CVMX_MF_AES_RESULT(*data, 1); -+ SG_CONSUME(sg, data, data_i, data_l); -+ crypt_len -= 16; -+ } -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+/****************************************************************************/ -+/* MD5 */ -+ -+int -+octo_null_md5_encrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ uint64_t *data; -+ uint64_t tmp1, tmp2; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || -+ (auth_off & 0x7) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data, data_i, data_l); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* Load MD5 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ -+ while (auth_off > 0) { -+ SG_CONSUME(sg, data, data_i, data_l); -+ auth_off -= 8; -+ } -+ -+ while (auth_len > 0) { -+ CVM_LOAD_MD5_UNIT(*data, next); -+ auth_len -= 8; -+ SG_CONSUME(sg, data, data_i, data_l); -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_MD5_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVMX_ES64(tmp1, ((alen + 64) << 3)); -+ CVM_LOAD_MD5_UNIT(tmp1, next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_ES64(tmp1, ((64 + 16) << 3)); -+ CVMX_MT_HSH_STARTMD5(tmp1); -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data, data_i, data_l); -+ icv_off -= 8; -+ } -+ CVMX_MF_HSH_IV(*data, 0); -+ SG_CONSUME(sg, data, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *(uint32_t *)data = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+/****************************************************************************/ -+/* SHA1 */ -+ -+int -+octo_null_sha1_encrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ uint64_t *data; -+ uint64_t tmp1, tmp2, tmp3; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || -+ (auth_off & 0x7) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data, data_i, data_l); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* Load SHA1 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); -+ -+ while (auth_off > 0) { -+ SG_CONSUME(sg, data, data_i, data_l); -+ auth_off -= 8; -+ } -+ -+ while (auth_len > 0) { -+ CVM_LOAD_SHA_UNIT(*data, next); -+ auth_len -= 8; -+ SG_CONSUME(sg, data, data_i, data_l); -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_MD5_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ tmp3 = 0; -+ CVMX_MF_HSH_IV(tmp3, 2); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ tmp3 |= 0x0000000080000000; -+ CVMX_MT_HSH_DAT(tmp3, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data, data_i, data_l); -+ icv_off -= 8; -+ } -+ CVMX_MF_HSH_IV(*data, 0); -+ SG_CONSUME(sg, data, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *(uint32_t *)data = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+/****************************************************************************/ -+/* DES MD5 */ -+ -+int -+octo_des_cbc_md5_encrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ union { -+ uint32_t data32[2]; -+ uint64_t data64[1]; -+ } mydata; -+ uint64_t *data = &mydata.data64[0]; -+ uint32_t *data32; -+ uint64_t tmp1, tmp2; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || -+ (crypt_len & 0x7) || -+ (auth_len & 0x7) || -+ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data32, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load 3DES Key */ -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ if (od->octo_encklen == 24) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ } else if (od->octo_encklen == 8) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ -+ CVMX_MT_3DES_IV(* (uint64_t *) ivp); -+ -+ /* Load MD5 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ -+ while (crypt_off > 0 && auth_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ crypt_off -= 4; -+ auth_off -= 4; -+ } -+ -+ while (crypt_len > 0 || auth_len > 0) { -+ uint32_t *first = data32; -+ mydata.data32[0] = *first; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata.data32[1] = *data32; -+ if (crypt_off <= 0) { -+ if (crypt_len > 0) { -+ CVMX_MT_3DES_ENC_CBC(*data); -+ CVMX_MF_3DES_RESULT(*data); -+ crypt_len -= 8; -+ } -+ } else -+ crypt_off -= 8; -+ if (auth_off <= 0) { -+ if (auth_len > 0) { -+ CVM_LOAD_MD5_UNIT(*data, next); -+ auth_len -= 8; -+ } -+ } else -+ auth_off -= 8; -+ *first = mydata.data32[0]; -+ *data32 = mydata.data32[1]; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_MD5_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVMX_ES64(tmp1, ((alen + 64) << 3)); -+ CVM_LOAD_MD5_UNIT(tmp1, next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_ES64(tmp1, ((64 + 16) << 3)); -+ CVMX_MT_HSH_STARTMD5(tmp1); -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data32, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ icv_off -= 4; -+ } -+ CVMX_MF_HSH_IV(tmp1, 0); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ SG_CONSUME(sg, data32, data_i, data_l); -+ *data32 = (uint32_t) tmp1; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+int -+octo_des_cbc_md5_decrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ union { -+ uint32_t data32[2]; -+ uint64_t data64[1]; -+ } mydata; -+ uint64_t *data = &mydata.data64[0]; -+ uint32_t *data32; -+ uint64_t tmp1, tmp2; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || -+ (crypt_len & 0x7) || -+ (auth_len & 0x7) || -+ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data32, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load 3DES Key */ -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ if (od->octo_encklen == 24) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ } else if (od->octo_encklen == 8) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ -+ CVMX_MT_3DES_IV(* (uint64_t *) ivp); -+ -+ /* Load MD5 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ -+ while (crypt_off > 0 && auth_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ crypt_off -= 4; -+ auth_off -= 4; -+ } -+ -+ while (crypt_len > 0 || auth_len > 0) { -+ uint32_t *first = data32; -+ mydata.data32[0] = *first; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata.data32[1] = *data32; -+ if (auth_off <= 0) { -+ if (auth_len > 0) { -+ CVM_LOAD_MD5_UNIT(*data, next); -+ auth_len -= 8; -+ } -+ } else -+ auth_off -= 8; -+ if (crypt_off <= 0) { -+ if (crypt_len > 0) { -+ CVMX_MT_3DES_DEC_CBC(*data); -+ CVMX_MF_3DES_RESULT(*data); -+ crypt_len -= 8; -+ } -+ } else -+ crypt_off -= 8; -+ *first = mydata.data32[0]; -+ *data32 = mydata.data32[1]; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_MD5_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVMX_ES64(tmp1, ((alen + 64) << 3)); -+ CVM_LOAD_MD5_UNIT(tmp1, next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_ES64(tmp1, ((64 + 16) << 3)); -+ CVMX_MT_HSH_STARTMD5(tmp1); -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data32, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ icv_off -= 4; -+ } -+ CVMX_MF_HSH_IV(tmp1, 0); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ SG_CONSUME(sg, data32, data_i, data_l); -+ *data32 = (uint32_t) tmp1; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+/****************************************************************************/ -+/* DES SHA */ -+ -+int -+octo_des_cbc_sha1_encrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ union { -+ uint32_t data32[2]; -+ uint64_t data64[1]; -+ } mydata; -+ uint64_t *data = &mydata.data64[0]; -+ uint32_t *data32; -+ uint64_t tmp1, tmp2, tmp3; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || -+ (crypt_len & 0x7) || -+ (auth_len & 0x7) || -+ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data32, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load 3DES Key */ -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ if (od->octo_encklen == 24) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ } else if (od->octo_encklen == 8) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ -+ CVMX_MT_3DES_IV(* (uint64_t *) ivp); -+ -+ /* Load SHA1 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); -+ -+ while (crypt_off > 0 && auth_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ crypt_off -= 4; -+ auth_off -= 4; -+ } -+ -+ while (crypt_len > 0 || auth_len > 0) { -+ uint32_t *first = data32; -+ mydata.data32[0] = *first; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata.data32[1] = *data32; -+ if (crypt_off <= 0) { -+ if (crypt_len > 0) { -+ CVMX_MT_3DES_ENC_CBC(*data); -+ CVMX_MF_3DES_RESULT(*data); -+ crypt_len -= 8; -+ } -+ } else -+ crypt_off -= 8; -+ if (auth_off <= 0) { -+ if (auth_len > 0) { -+ CVM_LOAD_SHA_UNIT(*data, next); -+ auth_len -= 8; -+ } -+ } else -+ auth_off -= 8; -+ *first = mydata.data32[0]; -+ *data32 = mydata.data32[1]; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_SHA_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ tmp3 = 0; -+ CVMX_MF_HSH_IV(tmp3, 2); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ tmp3 |= 0x0000000080000000; -+ CVMX_MT_HSH_DAT(tmp3, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data32, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ icv_off -= 4; -+ } -+ CVMX_MF_HSH_IV(tmp1, 0); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ SG_CONSUME(sg, data32, data_i, data_l); -+ *data32 = (uint32_t) tmp1; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+int -+octo_des_cbc_sha1_decrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ union { -+ uint32_t data32[2]; -+ uint64_t data64[1]; -+ } mydata; -+ uint64_t *data = &mydata.data64[0]; -+ uint32_t *data32; -+ uint64_t tmp1, tmp2, tmp3; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || -+ (crypt_len & 0x7) || -+ (auth_len & 0x7) || -+ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data32, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load 3DES Key */ -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ if (od->octo_encklen == 24) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ } else if (od->octo_encklen == 8) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ -+ CVMX_MT_3DES_IV(* (uint64_t *) ivp); -+ -+ /* Load SHA1 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); -+ -+ while (crypt_off > 0 && auth_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ crypt_off -= 4; -+ auth_off -= 4; -+ } -+ -+ while (crypt_len > 0 || auth_len > 0) { -+ uint32_t *first = data32; -+ mydata.data32[0] = *first; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata.data32[1] = *data32; -+ if (auth_off <= 0) { -+ if (auth_len > 0) { -+ CVM_LOAD_SHA_UNIT(*data, next); -+ auth_len -= 8; -+ } -+ } else -+ auth_off -= 8; -+ if (crypt_off <= 0) { -+ if (crypt_len > 0) { -+ CVMX_MT_3DES_DEC_CBC(*data); -+ CVMX_MF_3DES_RESULT(*data); -+ crypt_len -= 8; -+ } -+ } else -+ crypt_off -= 8; -+ *first = mydata.data32[0]; -+ *data32 = mydata.data32[1]; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_SHA_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ tmp3 = 0; -+ CVMX_MF_HSH_IV(tmp3, 2); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ tmp3 |= 0x0000000080000000; -+ CVMX_MT_HSH_DAT(tmp3, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); -+ /* save the HMAC */ -+ SG_INIT(sg, data32, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ icv_off -= 4; -+ } -+ CVMX_MF_HSH_IV(tmp1, 0); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ SG_CONSUME(sg, data32, data_i, data_l); -+ *data32 = (uint32_t) tmp1; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+/****************************************************************************/ -+/* AES MD5 */ -+ -+int -+octo_aes_cbc_md5_encrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ union { -+ uint32_t data32[2]; -+ uint64_t data64[1]; -+ } mydata[2]; -+ uint64_t *pdata = &mydata[0].data64[0]; -+ uint64_t *data = &mydata[1].data64[0]; -+ uint32_t *data32; -+ uint64_t tmp1, tmp2; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || -+ (crypt_len & 0x7) || -+ (auth_len & 0x7) || -+ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data32, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load AES Key */ -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ -+ if (od->octo_encklen == 16) { -+ CVMX_MT_AES_KEY(0x0, 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 24) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 32) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); -+ -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); -+ -+ /* Load MD5 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ -+ while (crypt_off > 0 && auth_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ crypt_off -= 4; -+ auth_off -= 4; -+ } -+ -+ /* align auth and crypt */ -+ while (crypt_off > 0 && auth_len > 0) { -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVM_LOAD_MD5_UNIT(*pdata, next); -+ crypt_off -= 8; -+ auth_len -= 8; -+ } -+ -+ while (crypt_len > 0) { -+ uint32_t *pdata32[3]; -+ -+ pdata32[0] = data32; -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ -+ pdata32[1] = data32; -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ -+ pdata32[2] = data32; -+ mydata[1].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ -+ mydata[1].data32[1] = *data32; -+ -+ CVMX_MT_AES_ENC_CBC0(*pdata); -+ CVMX_MT_AES_ENC_CBC1(*data); -+ CVMX_MF_AES_RESULT(*pdata, 0); -+ CVMX_MF_AES_RESULT(*data, 1); -+ crypt_len -= 16; -+ -+ if (auth_len > 0) { -+ CVM_LOAD_MD5_UNIT(*pdata, next); -+ auth_len -= 8; -+ } -+ if (auth_len > 0) { -+ CVM_LOAD_MD5_UNIT(*data, next); -+ auth_len -= 8; -+ } -+ -+ *pdata32[0] = mydata[0].data32[0]; -+ *pdata32[1] = mydata[0].data32[1]; -+ *pdata32[2] = mydata[1].data32[0]; -+ *data32 = mydata[1].data32[1]; -+ -+ SG_CONSUME(sg, data32, data_i, data_l); -+ } -+ -+ /* finish any left over hashing */ -+ while (auth_len > 0) { -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVM_LOAD_MD5_UNIT(*pdata, next); -+ auth_len -= 8; -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_MD5_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVMX_ES64(tmp1, ((alen + 64) << 3)); -+ CVM_LOAD_MD5_UNIT(tmp1, next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_ES64(tmp1, ((64 + 16) << 3)); -+ CVMX_MT_HSH_STARTMD5(tmp1); -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data32, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ icv_off -= 4; -+ } -+ CVMX_MF_HSH_IV(tmp1, 0); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ SG_CONSUME(sg, data32, data_i, data_l); -+ *data32 = (uint32_t) tmp1; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+int -+octo_aes_cbc_md5_decrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ union { -+ uint32_t data32[2]; -+ uint64_t data64[1]; -+ } mydata[2]; -+ uint64_t *pdata = &mydata[0].data64[0]; -+ uint64_t *data = &mydata[1].data64[0]; -+ uint32_t *data32; -+ uint64_t tmp1, tmp2; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || -+ (crypt_len & 0x7) || -+ (auth_len & 0x7) || -+ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data32, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load AES Key */ -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ -+ if (od->octo_encklen == 16) { -+ CVMX_MT_AES_KEY(0x0, 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 24) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 32) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); -+ -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); -+ -+ /* Load MD5 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ -+ while (crypt_off > 0 && auth_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ crypt_off -= 4; -+ auth_off -= 4; -+ } -+ -+ /* align auth and crypt */ -+ while (crypt_off > 0 && auth_len > 0) { -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVM_LOAD_MD5_UNIT(*pdata, next); -+ crypt_off -= 8; -+ auth_len -= 8; -+ } -+ -+ while (crypt_len > 0) { -+ uint32_t *pdata32[3]; -+ -+ pdata32[0] = data32; -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ pdata32[1] = data32; -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ pdata32[2] = data32; -+ mydata[1].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[1].data32[1] = *data32; -+ -+ if (auth_len > 0) { -+ CVM_LOAD_MD5_UNIT(*pdata, next); -+ auth_len -= 8; -+ } -+ -+ if (auth_len > 0) { -+ CVM_LOAD_MD5_UNIT(*data, next); -+ auth_len -= 8; -+ } -+ -+ CVMX_MT_AES_DEC_CBC0(*pdata); -+ CVMX_MT_AES_DEC_CBC1(*data); -+ CVMX_MF_AES_RESULT(*pdata, 0); -+ CVMX_MF_AES_RESULT(*data, 1); -+ crypt_len -= 16; -+ -+ *pdata32[0] = mydata[0].data32[0]; -+ *pdata32[1] = mydata[0].data32[1]; -+ *pdata32[2] = mydata[1].data32[0]; -+ *data32 = mydata[1].data32[1]; -+ -+ SG_CONSUME(sg, data32, data_i, data_l); -+ } -+ -+ /* finish left over hash if any */ -+ while (auth_len > 0) { -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVM_LOAD_MD5_UNIT(*pdata, next); -+ auth_len -= 8; -+ } -+ -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_MD5_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVMX_ES64(tmp1, ((alen + 64) << 3)); -+ CVM_LOAD_MD5_UNIT(tmp1, next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_ES64(tmp1, ((64 + 16) << 3)); -+ CVMX_MT_HSH_STARTMD5(tmp1); -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data32, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ icv_off -= 4; -+ } -+ CVMX_MF_HSH_IV(tmp1, 0); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ SG_CONSUME(sg, data32, data_i, data_l); -+ *data32 = (uint32_t) tmp1; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+/****************************************************************************/ -+/* AES SHA1 */ -+ -+int -+octo_aes_cbc_sha1_encrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ union { -+ uint32_t data32[2]; -+ uint64_t data64[1]; -+ } mydata[2]; -+ uint64_t *pdata = &mydata[0].data64[0]; -+ uint64_t *data = &mydata[1].data64[0]; -+ uint32_t *data32; -+ uint64_t tmp1, tmp2, tmp3; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s(a_off=%d a_len=%d c_off=%d c_len=%d icv_off=%d)\n", -+ __FUNCTION__, auth_off, auth_len, crypt_off, crypt_len, icv_off); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || -+ (crypt_len & 0x7) || -+ (auth_len & 0x7) || -+ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data32, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load AES Key */ -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ -+ if (od->octo_encklen == 16) { -+ CVMX_MT_AES_KEY(0x0, 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 24) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 32) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); -+ -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); -+ -+ /* Load SHA IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); -+ -+ while (crypt_off > 0 && auth_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ crypt_off -= 4; -+ auth_off -= 4; -+ } -+ -+ /* align auth and crypt */ -+ while (crypt_off > 0 && auth_len > 0) { -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVM_LOAD_SHA_UNIT(*pdata, next); -+ crypt_off -= 8; -+ auth_len -= 8; -+ } -+ -+ while (crypt_len > 0) { -+ uint32_t *pdata32[3]; -+ -+ pdata32[0] = data32; -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ pdata32[1] = data32; -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ pdata32[2] = data32; -+ mydata[1].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[1].data32[1] = *data32; -+ -+ CVMX_MT_AES_ENC_CBC0(*pdata); -+ CVMX_MT_AES_ENC_CBC1(*data); -+ CVMX_MF_AES_RESULT(*pdata, 0); -+ CVMX_MF_AES_RESULT(*data, 1); -+ crypt_len -= 16; -+ -+ if (auth_len > 0) { -+ CVM_LOAD_SHA_UNIT(*pdata, next); -+ auth_len -= 8; -+ } -+ if (auth_len > 0) { -+ CVM_LOAD_SHA_UNIT(*data, next); -+ auth_len -= 8; -+ } -+ -+ *pdata32[0] = mydata[0].data32[0]; -+ *pdata32[1] = mydata[0].data32[1]; -+ *pdata32[2] = mydata[1].data32[0]; -+ *data32 = mydata[1].data32[1]; -+ -+ SG_CONSUME(sg, data32, data_i, data_l); -+ } -+ -+ /* finish and hashing */ -+ while (auth_len > 0) { -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVM_LOAD_SHA_UNIT(*pdata, next); -+ auth_len -= 8; -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_SHA_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ tmp3 = 0; -+ CVMX_MF_HSH_IV(tmp3, 2); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ tmp3 |= 0x0000000080000000; -+ CVMX_MT_HSH_DAT(tmp3, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_MD5_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data32, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ icv_off -= 4; -+ } -+ CVMX_MF_HSH_IV(tmp1, 0); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ SG_CONSUME(sg, data32, data_i, data_l); -+ *data32 = (uint32_t) tmp1; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+int -+octo_aes_cbc_sha1_decrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ union { -+ uint32_t data32[2]; -+ uint64_t data64[1]; -+ } mydata[2]; -+ uint64_t *pdata = &mydata[0].data64[0]; -+ uint64_t *data = &mydata[1].data64[0]; -+ uint32_t *data32; -+ uint64_t tmp1, tmp2, tmp3; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s(a_off=%d a_len=%d c_off=%d c_len=%d icv_off=%d)\n", -+ __FUNCTION__, auth_off, auth_len, crypt_off, crypt_len, icv_off); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || -+ (crypt_len & 0x7) || -+ (auth_len & 0x7) || -+ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data32, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load AES Key */ -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ -+ if (od->octo_encklen == 16) { -+ CVMX_MT_AES_KEY(0x0, 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 24) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 32) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); -+ -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); -+ -+ /* Load SHA1 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); -+ -+ while (crypt_off > 0 && auth_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ crypt_off -= 4; -+ auth_off -= 4; -+ } -+ -+ /* align auth and crypt */ -+ while (crypt_off > 0 && auth_len > 0) { -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVM_LOAD_SHA_UNIT(*pdata, next); -+ crypt_off -= 8; -+ auth_len -= 8; -+ } -+ -+ while (crypt_len > 0) { -+ uint32_t *pdata32[3]; -+ -+ pdata32[0] = data32; -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ pdata32[1] = data32; -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ pdata32[2] = data32; -+ mydata[1].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[1].data32[1] = *data32; -+ -+ if (auth_len > 0) { -+ CVM_LOAD_SHA_UNIT(*pdata, next); -+ auth_len -= 8; -+ } -+ if (auth_len > 0) { -+ CVM_LOAD_SHA_UNIT(*data, next); -+ auth_len -= 8; -+ } -+ -+ CVMX_MT_AES_DEC_CBC0(*pdata); -+ CVMX_MT_AES_DEC_CBC1(*data); -+ CVMX_MF_AES_RESULT(*pdata, 0); -+ CVMX_MF_AES_RESULT(*data, 1); -+ crypt_len -= 16; -+ -+ *pdata32[0] = mydata[0].data32[0]; -+ *pdata32[1] = mydata[0].data32[1]; -+ *pdata32[2] = mydata[1].data32[0]; -+ *data32 = mydata[1].data32[1]; -+ -+ SG_CONSUME(sg, data32, data_i, data_l); -+ } -+ -+ /* finish and leftover hashing */ -+ while (auth_len > 0) { -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVM_LOAD_SHA_UNIT(*pdata, next); -+ auth_len -= 8; -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_SHA_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ tmp3 = 0; -+ CVMX_MF_HSH_IV(tmp3, 2); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ tmp3 |= 0x0000000080000000; -+ CVMX_MT_HSH_DAT(tmp3, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_MD5_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data32, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ icv_off -= 4; -+ } -+ CVMX_MF_HSH_IV(tmp1, 0); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ SG_CONSUME(sg, data32, data_i, data_l); -+ *data32 = (uint32_t) tmp1; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+/****************************************************************************/ -diff -Nur linux-3.0.4.orig/crypto/ocf/cryptocteon/cryptocteon.c linux-3.0.4/crypto/ocf/cryptocteon/cryptocteon.c ---- linux-3.0.4.orig/crypto/ocf/cryptocteon/cryptocteon.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/cryptocteon/cryptocteon.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,575 @@ -+/* -+ * Octeon Crypto for OCF -+ * -+ * Written by David McCullough -+ * Copyright (C) 2009-2010 David McCullough -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ * --------------------------------------------------------------------------- -+ */ -+ -+#include -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+struct { -+ softc_device_decl sc_dev; -+} octo_softc; -+ -+#define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK) -+ -+struct octo_sess { -+ int octo_encalg; -+ #define MAX_CIPHER_KEYLEN 64 -+ char octo_enckey[MAX_CIPHER_KEYLEN]; -+ int octo_encklen; -+ -+ int octo_macalg; -+ #define MAX_HASH_KEYLEN 64 -+ char octo_mackey[MAX_HASH_KEYLEN]; -+ int octo_macklen; -+ int octo_mackey_set; -+ -+ int octo_mlen; -+ int octo_ivsize; -+ -+ int (*octo_encrypt)(struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp); -+ int (*octo_decrypt)(struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp); -+ -+ uint64_t octo_hminner[3]; -+ uint64_t octo_hmouter[3]; -+}; -+ -+int32_t octo_id = -1; -+module_param(octo_id, int, 0444); -+MODULE_PARM_DESC(octo_id, "Read-Only OCF ID for cryptocteon driver"); -+ -+static struct octo_sess **octo_sessions = NULL; -+static u_int32_t octo_sesnum = 0; -+ -+static int octo_process(device_t, struct cryptop *, int); -+static int octo_newsession(device_t, u_int32_t *, struct cryptoini *); -+static int octo_freesession(device_t, u_int64_t); -+ -+static device_method_t octo_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, octo_newsession), -+ DEVMETHOD(cryptodev_freesession,octo_freesession), -+ DEVMETHOD(cryptodev_process, octo_process), -+}; -+ -+#define debug octo_debug -+int octo_debug = 0; -+module_param(octo_debug, int, 0644); -+MODULE_PARM_DESC(octo_debug, "Enable debug"); -+ -+ -+#include "cavium_crypto.c" -+ -+ -+/* -+ * Generate a new octo session. We artifically limit it to a single -+ * hash/cipher or hash-cipher combo just to make it easier, most callers -+ * do not expect more than this anyway. -+ */ -+static int -+octo_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) -+{ -+ struct cryptoini *c, *encini = NULL, *macini = NULL; -+ struct octo_sess **ocd; -+ int i; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid == NULL || cri == NULL) { -+ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ /* -+ * To keep it simple, we only handle hash, cipher or hash/cipher in a -+ * session, you cannot currently do multiple ciphers/hashes in one -+ * session even though it would be possibel to code this driver to -+ * handle it. -+ */ -+ for (i = 0, c = cri; c && i < 2; i++) { -+ if (c->cri_alg == CRYPTO_MD5_HMAC || -+ c->cri_alg == CRYPTO_SHA1_HMAC || -+ c->cri_alg == CRYPTO_NULL_HMAC) { -+ if (macini) { -+ break; -+ } -+ macini = c; -+ } -+ if (c->cri_alg == CRYPTO_DES_CBC || -+ c->cri_alg == CRYPTO_3DES_CBC || -+ c->cri_alg == CRYPTO_AES_CBC || -+ c->cri_alg == CRYPTO_NULL_CBC) { -+ if (encini) { -+ break; -+ } -+ encini = c; -+ } -+ c = c->cri_next; -+ } -+ if (!macini && !encini) { -+ dprintk("%s,%d - EINVAL bad cipher/hash or combination\n", -+ __FILE__, __LINE__); -+ return EINVAL; -+ } -+ if (c) { -+ dprintk("%s,%d - EINVAL cannot handle chained cipher/hash combos\n", -+ __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ /* -+ * So we have something we can do, lets setup the session -+ */ -+ -+ if (octo_sessions) { -+ for (i = 1; i < octo_sesnum; i++) -+ if (octo_sessions[i] == NULL) -+ break; -+ } else -+ i = 1; /* NB: to silence compiler warning */ -+ -+ if (octo_sessions == NULL || i == octo_sesnum) { -+ if (octo_sessions == NULL) { -+ i = 1; /* We leave octo_sessions[0] empty */ -+ octo_sesnum = CRYPTO_SW_SESSIONS; -+ } else -+ octo_sesnum *= 2; -+ -+ ocd = kmalloc(octo_sesnum * sizeof(struct octo_sess *), SLAB_ATOMIC); -+ if (ocd == NULL) { -+ /* Reset session number */ -+ if (octo_sesnum == CRYPTO_SW_SESSIONS) -+ octo_sesnum = 0; -+ else -+ octo_sesnum /= 2; -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memset(ocd, 0, octo_sesnum * sizeof(struct octo_sess *)); -+ -+ /* Copy existing sessions */ -+ if (octo_sessions) { -+ memcpy(ocd, octo_sessions, -+ (octo_sesnum / 2) * sizeof(struct octo_sess *)); -+ kfree(octo_sessions); -+ } -+ -+ octo_sessions = ocd; -+ } -+ -+ ocd = &octo_sessions[i]; -+ *sid = i; -+ -+ -+ *ocd = (struct octo_sess *) kmalloc(sizeof(struct octo_sess), SLAB_ATOMIC); -+ if (*ocd == NULL) { -+ octo_freesession(NULL, i); -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memset(*ocd, 0, sizeof(struct octo_sess)); -+ -+ if (encini && encini->cri_key) { -+ (*ocd)->octo_encklen = (encini->cri_klen + 7) / 8; -+ memcpy((*ocd)->octo_enckey, encini->cri_key, (*ocd)->octo_encklen); -+ } -+ -+ if (macini && macini->cri_key) { -+ (*ocd)->octo_macklen = (macini->cri_klen + 7) / 8; -+ memcpy((*ocd)->octo_mackey, macini->cri_key, (*ocd)->octo_macklen); -+ } -+ -+ (*ocd)->octo_mlen = 0; -+ if (encini && encini->cri_mlen) -+ (*ocd)->octo_mlen = encini->cri_mlen; -+ else if (macini && macini->cri_mlen) -+ (*ocd)->octo_mlen = macini->cri_mlen; -+ else -+ (*ocd)->octo_mlen = 12; -+ -+ /* -+ * point c at the enc if it exists, otherwise the mac -+ */ -+ c = encini ? encini : macini; -+ -+ switch (c->cri_alg) { -+ case CRYPTO_DES_CBC: -+ case CRYPTO_3DES_CBC: -+ (*ocd)->octo_ivsize = 8; -+ switch (macini ? macini->cri_alg : -1) { -+ case CRYPTO_MD5_HMAC: -+ (*ocd)->octo_encrypt = octo_des_cbc_md5_encrypt; -+ (*ocd)->octo_decrypt = octo_des_cbc_md5_decrypt; -+ octo_calc_hash(0, macini->cri_key, (*ocd)->octo_hminner, -+ (*ocd)->octo_hmouter); -+ break; -+ case CRYPTO_SHA1_HMAC: -+ (*ocd)->octo_encrypt = octo_des_cbc_sha1_encrypt; -+ (*ocd)->octo_decrypt = octo_des_cbc_sha1_decrypt; -+ octo_calc_hash(1, macini->cri_key, (*ocd)->octo_hminner, -+ (*ocd)->octo_hmouter); -+ break; -+ case -1: -+ (*ocd)->octo_encrypt = octo_des_cbc_encrypt; -+ (*ocd)->octo_decrypt = octo_des_cbc_decrypt; -+ break; -+ default: -+ octo_freesession(NULL, i); -+ dprintk("%s,%d: EINVALn", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ break; -+ case CRYPTO_AES_CBC: -+ (*ocd)->octo_ivsize = 16; -+ switch (macini ? macini->cri_alg : -1) { -+ case CRYPTO_MD5_HMAC: -+ (*ocd)->octo_encrypt = octo_aes_cbc_md5_encrypt; -+ (*ocd)->octo_decrypt = octo_aes_cbc_md5_decrypt; -+ octo_calc_hash(0, macini->cri_key, (*ocd)->octo_hminner, -+ (*ocd)->octo_hmouter); -+ break; -+ case CRYPTO_SHA1_HMAC: -+ (*ocd)->octo_encrypt = octo_aes_cbc_sha1_encrypt; -+ (*ocd)->octo_decrypt = octo_aes_cbc_sha1_decrypt; -+ octo_calc_hash(1, macini->cri_key, (*ocd)->octo_hminner, -+ (*ocd)->octo_hmouter); -+ break; -+ case -1: -+ (*ocd)->octo_encrypt = octo_aes_cbc_encrypt; -+ (*ocd)->octo_decrypt = octo_aes_cbc_decrypt; -+ break; -+ default: -+ octo_freesession(NULL, i); -+ dprintk("%s,%d: EINVALn", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ break; -+ case CRYPTO_MD5_HMAC: -+ (*ocd)->octo_encrypt = octo_null_md5_encrypt; -+ (*ocd)->octo_decrypt = octo_null_md5_encrypt; /* encrypt == decrypt */ -+ octo_calc_hash(0, macini->cri_key, (*ocd)->octo_hminner, -+ (*ocd)->octo_hmouter); -+ break; -+ case CRYPTO_SHA1_HMAC: -+ (*ocd)->octo_encrypt = octo_null_sha1_encrypt; -+ (*ocd)->octo_decrypt = octo_null_sha1_encrypt; /* encrypt == decrypt */ -+ octo_calc_hash(1, macini->cri_key, (*ocd)->octo_hminner, -+ (*ocd)->octo_hmouter); -+ break; -+ default: -+ octo_freesession(NULL, i); -+ dprintk("%s,%d: EINVALn", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ (*ocd)->octo_encalg = encini ? encini->cri_alg : -1; -+ (*ocd)->octo_macalg = macini ? macini->cri_alg : -1; -+ -+ return 0; -+} -+ -+/* -+ * Free a session. -+ */ -+static int -+octo_freesession(device_t dev, u_int64_t tid) -+{ -+ u_int32_t sid = CRYPTO_SESID2LID(tid); -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid > octo_sesnum || octo_sessions == NULL || -+ octo_sessions[sid] == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return(EINVAL); -+ } -+ -+ /* Silently accept and return */ -+ if (sid == 0) -+ return(0); -+ -+ if (octo_sessions[sid]) -+ kfree(octo_sessions[sid]); -+ octo_sessions[sid] = NULL; -+ return 0; -+} -+ -+/* -+ * Process a request. -+ */ -+static int -+octo_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ struct cryptodesc *crd; -+ struct octo_sess *od; -+ u_int32_t lid; -+#define SCATTERLIST_MAX 16 -+ struct scatterlist sg[SCATTERLIST_MAX]; -+ int sg_num, sg_len; -+ struct sk_buff *skb = NULL; -+ struct uio *uiop = NULL; -+ struct cryptodesc *enccrd = NULL, *maccrd = NULL; -+ unsigned char *ivp = NULL; -+ unsigned char iv_data[HASH_MAX_LEN]; -+ int auth_off = 0, auth_len = 0, crypt_off = 0, crypt_len = 0, icv_off = 0; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ /* Sanity check */ -+ if (crp == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ crp->crp_etype = 0; -+ -+ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ lid = crp->crp_sid & 0xffffffff; -+ if (lid >= octo_sesnum || lid == 0 || octo_sessions == NULL || -+ octo_sessions[lid] == NULL) { -+ crp->crp_etype = ENOENT; -+ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); -+ goto done; -+ } -+ od = octo_sessions[lid]; -+ -+ /* -+ * do some error checking outside of the loop for SKB and IOV processing -+ * this leaves us with valid skb or uiop pointers for later -+ */ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ skb = (struct sk_buff *) crp->crp_buf; -+ if (skb_shinfo(skb)->nr_frags >= SCATTERLIST_MAX) { -+ printk("%s,%d: %d nr_frags > SCATTERLIST_MAX", __FILE__, __LINE__, -+ skb_shinfo(skb)->nr_frags); -+ goto done; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ uiop = (struct uio *) crp->crp_buf; -+ if (uiop->uio_iovcnt > SCATTERLIST_MAX) { -+ printk("%s,%d: %d uio_iovcnt > SCATTERLIST_MAX", __FILE__, __LINE__, -+ uiop->uio_iovcnt); -+ goto done; -+ } -+ } -+ -+ /* point our enccrd and maccrd appropriately */ -+ crd = crp->crp_desc; -+ if (crd->crd_alg == od->octo_encalg) enccrd = crd; -+ if (crd->crd_alg == od->octo_macalg) maccrd = crd; -+ crd = crd->crd_next; -+ if (crd) { -+ if (crd->crd_alg == od->octo_encalg) enccrd = crd; -+ if (crd->crd_alg == od->octo_macalg) maccrd = crd; -+ crd = crd->crd_next; -+ } -+ if (crd) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: ENOENT - descriptors do not match session\n", -+ __FILE__, __LINE__); -+ goto done; -+ } -+ -+ if (enccrd) { -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) { -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) -+ ivp = enccrd->crd_iv; -+ else -+ read_random((ivp = iv_data), od->octo_ivsize); -+ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ enccrd->crd_inject, od->octo_ivsize, ivp); -+ } else { -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) { -+ ivp = enccrd->crd_iv; -+ } else { -+ ivp = iv_data; -+ crypto_copydata(crp->crp_flags, crp->crp_buf, -+ enccrd->crd_inject, od->octo_ivsize, (caddr_t) ivp); -+ } -+ } -+ -+ if (maccrd) { -+ auth_off = maccrd->crd_skip; -+ auth_len = maccrd->crd_len; -+ icv_off = maccrd->crd_inject; -+ } -+ -+ crypt_off = enccrd->crd_skip; -+ crypt_len = enccrd->crd_len; -+ } else { /* if (maccrd) */ -+ auth_off = maccrd->crd_skip; -+ auth_len = maccrd->crd_len; -+ icv_off = maccrd->crd_inject; -+ } -+ -+ -+ /* -+ * setup the SG list to cover the buffer -+ */ -+ memset(sg, 0, sizeof(sg)); -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ int i, len; -+ -+ sg_num = 0; -+ sg_len = 0; -+ -+ len = skb_headlen(skb); -+ sg_set_page(&sg[sg_num], virt_to_page(skb->data), len, -+ offset_in_page(skb->data)); -+ sg_len += len; -+ sg_num++; -+ -+ for (i = 0; i < skb_shinfo(skb)->nr_frags && sg_num < SCATTERLIST_MAX; -+ i++) { -+ len = skb_shinfo(skb)->frags[i].size; -+ sg_set_page(&sg[sg_num], skb_shinfo(skb)->frags[i].page, -+ len, skb_shinfo(skb)->frags[i].page_offset); -+ sg_len += len; -+ sg_num++; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ int len; -+ -+ sg_len = 0; -+ for (sg_num = 0; sg_len < crp->crp_ilen && -+ sg_num < uiop->uio_iovcnt && -+ sg_num < SCATTERLIST_MAX; sg_num++) { -+ len = uiop->uio_iov[sg_num].iov_len; -+ sg_set_page(&sg[sg_num], -+ virt_to_page(uiop->uio_iov[sg_num].iov_base), len, -+ offset_in_page(uiop->uio_iov[sg_num].iov_base)); -+ sg_len += len; -+ } -+ } else { -+ sg_len = crp->crp_ilen; -+ sg_set_page(&sg[0], virt_to_page(crp->crp_buf), sg_len, -+ offset_in_page(crp->crp_buf)); -+ sg_num = 1; -+ } -+ -+ -+ /* -+ * setup a new explicit key -+ */ -+ if (enccrd) { -+ if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) { -+ od->octo_encklen = (enccrd->crd_klen + 7) / 8; -+ memcpy(od->octo_enckey, enccrd->crd_key, od->octo_encklen); -+ } -+ } -+ if (maccrd) { -+ if (maccrd->crd_flags & CRD_F_KEY_EXPLICIT) { -+ od->octo_macklen = (maccrd->crd_klen + 7) / 8; -+ memcpy(od->octo_mackey, maccrd->crd_key, od->octo_macklen); -+ od->octo_mackey_set = 0; -+ } -+ if (!od->octo_mackey_set) { -+ octo_calc_hash(maccrd->crd_alg == CRYPTO_MD5_HMAC ? 0 : 1, -+ maccrd->crd_key, od->octo_hminner, od->octo_hmouter); -+ od->octo_mackey_set = 1; -+ } -+ } -+ -+ -+ if (!enccrd || (enccrd->crd_flags & CRD_F_ENCRYPT)) -+ (*od->octo_encrypt)(od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ else -+ (*od->octo_decrypt)(od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ -+done: -+ crypto_done(crp); -+ return 0; -+} -+ -+static int -+cryptocteon_init(void) -+{ -+ dprintk("%s(%p)\n", __FUNCTION__, cryptocteon_init); -+ -+ softc_device_init(&octo_softc, "cryptocteon", 0, octo_methods); -+ -+ octo_id = crypto_get_driverid(softc_get_device(&octo_softc), -+ CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SYNC); -+ if (octo_id < 0) { -+ printk("Cryptocteon device cannot initialize!"); -+ return -ENODEV; -+ } -+ -+ crypto_register(octo_id, CRYPTO_MD5_HMAC, 0,0); -+ crypto_register(octo_id, CRYPTO_SHA1_HMAC, 0,0); -+ //crypto_register(octo_id, CRYPTO_MD5, 0,0); -+ //crypto_register(octo_id, CRYPTO_SHA1, 0,0); -+ crypto_register(octo_id, CRYPTO_DES_CBC, 0,0); -+ crypto_register(octo_id, CRYPTO_3DES_CBC, 0,0); -+ crypto_register(octo_id, CRYPTO_AES_CBC, 0,0); -+ -+ return(0); -+} -+ -+static void -+cryptocteon_exit(void) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ crypto_unregister_all(octo_id); -+ octo_id = -1; -+} -+ -+module_init(cryptocteon_init); -+module_exit(cryptocteon_exit); -+ -+MODULE_LICENSE("BSD"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("Cryptocteon (OCF module for Cavium OCTEON crypto)"); -diff -Nur linux-3.0.4.orig/crypto/ocf/cryptodev.c linux-3.0.4/crypto/ocf/cryptodev.c ---- linux-3.0.4.orig/crypto/ocf/cryptodev.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/cryptodev.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,1069 @@ -+/* $OpenBSD: cryptodev.c,v 1.52 2002/06/19 07:22:46 deraadt Exp $ */ -+ -+/*- -+ * Linux port done by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * The license and original author are listed below. -+ * -+ * Copyright (c) 2001 Theo de Raadt -+ * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored in part by the Defense Advanced Research Projects -+ * Agency (DARPA) and Air Force Research Laboratory, Air Force -+ * Materiel Command, USAF, under agreement number F30602-01-2-0537. -+ * -+__FBSDID("$FreeBSD: src/sys/opencrypto/cryptodev.c,v 1.34 2007/05/09 19:37:02 gnn Exp $"); -+ */ -+ -+#include -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+extern asmlinkage long sys_dup(unsigned int fildes); -+ -+#define debug cryptodev_debug -+int cryptodev_debug = 0; -+module_param(cryptodev_debug, int, 0644); -+MODULE_PARM_DESC(cryptodev_debug, "Enable cryptodev debug"); -+ -+struct csession_info { -+ u_int16_t blocksize; -+ u_int16_t minkey, maxkey; -+ -+ u_int16_t keysize; -+ /* u_int16_t hashsize; */ -+ u_int16_t authsize; -+ u_int16_t authkey; -+ /* u_int16_t ctxsize; */ -+}; -+ -+struct csession { -+ struct list_head list; -+ u_int64_t sid; -+ u_int32_t ses; -+ -+ wait_queue_head_t waitq; -+ -+ u_int32_t cipher; -+ -+ u_int32_t mac; -+ -+ caddr_t key; -+ int keylen; -+ u_char tmp_iv[EALG_MAX_BLOCK_LEN]; -+ -+ caddr_t mackey; -+ int mackeylen; -+ -+ struct csession_info info; -+ -+ struct iovec iovec; -+ struct uio uio; -+ int error; -+}; -+ -+struct fcrypt { -+ struct list_head csessions; -+ int sesn; -+}; -+ -+static struct csession *csefind(struct fcrypt *, u_int); -+static int csedelete(struct fcrypt *, struct csession *); -+static struct csession *cseadd(struct fcrypt *, struct csession *); -+static struct csession *csecreate(struct fcrypt *, u_int64_t, -+ struct cryptoini *crie, struct cryptoini *cria, struct csession_info *); -+static int csefree(struct csession *); -+ -+static int cryptodev_op(struct csession *, struct crypt_op *); -+static int cryptodev_key(struct crypt_kop *); -+static int cryptodev_find(struct crypt_find_op *); -+ -+static int cryptodev_cb(void *); -+static int cryptodev_open(struct inode *inode, struct file *filp); -+ -+/* -+ * Check a crypto identifier to see if it requested -+ * a valid crid and it's capabilities match. -+ */ -+static int -+checkcrid(int crid) -+{ -+ int hid = crid & ~(CRYPTOCAP_F_SOFTWARE | CRYPTOCAP_F_HARDWARE); -+ int typ = crid & (CRYPTOCAP_F_SOFTWARE | CRYPTOCAP_F_HARDWARE); -+ int caps = 0; -+ -+ /* if the user hasn't selected a driver, then just call newsession */ -+ if (hid == 0 && typ != 0) -+ return 0; -+ -+ caps = crypto_getcaps(hid); -+ -+ /* didn't find anything with capabilities */ -+ if (caps == 0) { -+ dprintk("%s: hid=%x typ=%x not matched\n", __FUNCTION__, hid, typ); -+ return EINVAL; -+ } -+ -+ /* the user didn't specify SW or HW, so the driver is ok */ -+ if (typ == 0) -+ return 0; -+ -+ /* if the type specified didn't match */ -+ if (typ != (caps & (CRYPTOCAP_F_SOFTWARE | CRYPTOCAP_F_HARDWARE))) { -+ dprintk("%s: hid=%x typ=%x caps=%x not matched\n", __FUNCTION__, -+ hid, typ, caps); -+ return EINVAL; -+ } -+ -+ return 0; -+} -+ -+static int -+cryptodev_op(struct csession *cse, struct crypt_op *cop) -+{ -+ struct cryptop *crp = NULL; -+ struct cryptodesc *crde = NULL, *crda = NULL; -+ int error = 0; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (cop->len > CRYPTO_MAX_DATA_LEN) { -+ dprintk("%s: %d > %d\n", __FUNCTION__, cop->len, CRYPTO_MAX_DATA_LEN); -+ return (E2BIG); -+ } -+ -+ if (cse->info.blocksize && (cop->len % cse->info.blocksize) != 0) { -+ dprintk("%s: blocksize=%d len=%d\n", __FUNCTION__, cse->info.blocksize, -+ cop->len); -+ return (EINVAL); -+ } -+ -+ cse->uio.uio_iov = &cse->iovec; -+ cse->uio.uio_iovcnt = 1; -+ cse->uio.uio_offset = 0; -+#if 0 -+ cse->uio.uio_resid = cop->len; -+ cse->uio.uio_segflg = UIO_SYSSPACE; -+ cse->uio.uio_rw = UIO_WRITE; -+ cse->uio.uio_td = td; -+#endif -+ cse->uio.uio_iov[0].iov_len = cop->len; -+ if (cse->info.authsize) -+ cse->uio.uio_iov[0].iov_len += cse->info.authsize; -+ cse->uio.uio_iov[0].iov_base = kmalloc(cse->uio.uio_iov[0].iov_len, -+ GFP_KERNEL); -+ -+ if (cse->uio.uio_iov[0].iov_base == NULL) { -+ dprintk("%s: iov_base kmalloc(%d) failed\n", __FUNCTION__, -+ (int)cse->uio.uio_iov[0].iov_len); -+ return (ENOMEM); -+ } -+ -+ crp = crypto_getreq((cse->info.blocksize != 0) + (cse->info.authsize != 0)); -+ if (crp == NULL) { -+ dprintk("%s: ENOMEM\n", __FUNCTION__); -+ error = ENOMEM; -+ goto bail; -+ } -+ -+ if (cse->info.authsize && cse->info.blocksize) { -+ if (cop->op == COP_ENCRYPT) { -+ crde = crp->crp_desc; -+ crda = crde->crd_next; -+ } else { -+ crda = crp->crp_desc; -+ crde = crda->crd_next; -+ } -+ } else if (cse->info.authsize) { -+ crda = crp->crp_desc; -+ } else if (cse->info.blocksize) { -+ crde = crp->crp_desc; -+ } else { -+ dprintk("%s: bad request\n", __FUNCTION__); -+ error = EINVAL; -+ goto bail; -+ } -+ -+ if ((error = copy_from_user(cse->uio.uio_iov[0].iov_base, cop->src, -+ cop->len))) { -+ dprintk("%s: bad copy\n", __FUNCTION__); -+ goto bail; -+ } -+ -+ if (crda) { -+ crda->crd_skip = 0; -+ crda->crd_len = cop->len; -+ crda->crd_inject = cop->len; -+ -+ crda->crd_alg = cse->mac; -+ crda->crd_key = cse->mackey; -+ crda->crd_klen = cse->mackeylen * 8; -+ } -+ -+ if (crde) { -+ if (cop->op == COP_ENCRYPT) -+ crde->crd_flags |= CRD_F_ENCRYPT; -+ else -+ crde->crd_flags &= ~CRD_F_ENCRYPT; -+ crde->crd_len = cop->len; -+ crde->crd_inject = 0; -+ -+ crde->crd_alg = cse->cipher; -+ crde->crd_key = cse->key; -+ crde->crd_klen = cse->keylen * 8; -+ } -+ -+ crp->crp_ilen = cse->uio.uio_iov[0].iov_len; -+ crp->crp_flags = CRYPTO_F_IOV | CRYPTO_F_CBIMM -+ | (cop->flags & COP_F_BATCH); -+ crp->crp_buf = (caddr_t)&cse->uio; -+ crp->crp_callback = (int (*) (struct cryptop *)) cryptodev_cb; -+ crp->crp_sid = cse->sid; -+ crp->crp_opaque = (void *)cse; -+ -+ if (cop->iv) { -+ if (crde == NULL) { -+ error = EINVAL; -+ dprintk("%s no crde\n", __FUNCTION__); -+ goto bail; -+ } -+ if (cse->cipher == CRYPTO_ARC4) { /* XXX use flag? */ -+ error = EINVAL; -+ dprintk("%s arc4 with IV\n", __FUNCTION__); -+ goto bail; -+ } -+ if ((error = copy_from_user(cse->tmp_iv, cop->iv, -+ cse->info.blocksize))) { -+ dprintk("%s bad iv copy\n", __FUNCTION__); -+ goto bail; -+ } -+ memcpy(crde->crd_iv, cse->tmp_iv, cse->info.blocksize); -+ crde->crd_flags |= CRD_F_IV_EXPLICIT | CRD_F_IV_PRESENT; -+ crde->crd_skip = 0; -+ } else if (cse->cipher == CRYPTO_ARC4) { /* XXX use flag? */ -+ crde->crd_skip = 0; -+ } else if (crde) { -+ crde->crd_flags |= CRD_F_IV_PRESENT; -+ crde->crd_skip = cse->info.blocksize; -+ crde->crd_len -= cse->info.blocksize; -+ } -+ -+ if (cop->mac && crda == NULL) { -+ error = EINVAL; -+ dprintk("%s no crda\n", __FUNCTION__); -+ goto bail; -+ } -+ -+ /* -+ * Let the dispatch run unlocked, then, interlock against the -+ * callback before checking if the operation completed and going -+ * to sleep. This insures drivers don't inherit our lock which -+ * results in a lock order reversal between crypto_dispatch forced -+ * entry and the crypto_done callback into us. -+ */ -+ error = crypto_dispatch(crp); -+ if (error) { -+ dprintk("%s error in crypto_dispatch\n", __FUNCTION__); -+ goto bail; -+ } -+ -+ dprintk("%s about to WAIT\n", __FUNCTION__); -+ /* -+ * we really need to wait for driver to complete to maintain -+ * state, luckily interrupts will be remembered -+ */ -+ do { -+ error = wait_event_interruptible(crp->crp_waitq, -+ ((crp->crp_flags & CRYPTO_F_DONE) != 0)); -+ /* -+ * we can't break out of this loop or we will leave behind -+ * a huge mess, however, staying here means if your driver -+ * is broken user applications can hang and not be killed. -+ * The solution, fix your driver :-) -+ */ -+ if (error) { -+ schedule(); -+ error = 0; -+ } -+ } while ((crp->crp_flags & CRYPTO_F_DONE) == 0); -+ dprintk("%s finished WAITING error=%d\n", __FUNCTION__, error); -+ -+ if (crp->crp_etype != 0) { -+ error = crp->crp_etype; -+ dprintk("%s error in crp processing\n", __FUNCTION__); -+ goto bail; -+ } -+ -+ if (cse->error) { -+ error = cse->error; -+ dprintk("%s error in cse processing\n", __FUNCTION__); -+ goto bail; -+ } -+ -+ if (cop->dst && (error = copy_to_user(cop->dst, -+ cse->uio.uio_iov[0].iov_base, cop->len))) { -+ dprintk("%s bad dst copy\n", __FUNCTION__); -+ goto bail; -+ } -+ -+ if (cop->mac && -+ (error=copy_to_user(cop->mac, -+ (caddr_t)cse->uio.uio_iov[0].iov_base + cop->len, -+ cse->info.authsize))) { -+ dprintk("%s bad mac copy\n", __FUNCTION__); -+ goto bail; -+ } -+ -+bail: -+ if (crp) -+ crypto_freereq(crp); -+ if (cse->uio.uio_iov[0].iov_base) -+ kfree(cse->uio.uio_iov[0].iov_base); -+ -+ return (error); -+} -+ -+static int -+cryptodev_cb(void *op) -+{ -+ struct cryptop *crp = (struct cryptop *) op; -+ struct csession *cse = (struct csession *)crp->crp_opaque; -+ int error; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ error = crp->crp_etype; -+ if (error == EAGAIN) { -+ crp->crp_flags &= ~CRYPTO_F_DONE; -+#ifdef NOTYET -+ /* -+ * DAVIDM I am fairly sure that we should turn this into a batch -+ * request to stop bad karma/lockup, revisit -+ */ -+ crp->crp_flags |= CRYPTO_F_BATCH; -+#endif -+ return crypto_dispatch(crp); -+ } -+ if (error != 0 || (crp->crp_flags & CRYPTO_F_DONE)) { -+ cse->error = error; -+ wake_up_interruptible(&crp->crp_waitq); -+ } -+ return (0); -+} -+ -+static int -+cryptodevkey_cb(void *op) -+{ -+ struct cryptkop *krp = (struct cryptkop *) op; -+ dprintk("%s()\n", __FUNCTION__); -+ wake_up_interruptible(&krp->krp_waitq); -+ return (0); -+} -+ -+static int -+cryptodev_key(struct crypt_kop *kop) -+{ -+ struct cryptkop *krp = NULL; -+ int error = EINVAL; -+ int in, out, size, i; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (kop->crk_iparams + kop->crk_oparams > CRK_MAXPARAM) { -+ dprintk("%s params too big\n", __FUNCTION__); -+ return (EFBIG); -+ } -+ -+ in = kop->crk_iparams; -+ out = kop->crk_oparams; -+ switch (kop->crk_op) { -+ case CRK_MOD_EXP: -+ if (in == 3 && out == 1) -+ break; -+ return (EINVAL); -+ case CRK_MOD_EXP_CRT: -+ if (in == 6 && out == 1) -+ break; -+ return (EINVAL); -+ case CRK_DSA_SIGN: -+ if (in == 5 && out == 2) -+ break; -+ return (EINVAL); -+ case CRK_DSA_VERIFY: -+ if (in == 7 && out == 0) -+ break; -+ return (EINVAL); -+ case CRK_DH_COMPUTE_KEY: -+ if (in == 3 && out == 1) -+ break; -+ return (EINVAL); -+ default: -+ return (EINVAL); -+ } -+ -+ krp = (struct cryptkop *)kmalloc(sizeof *krp, GFP_KERNEL); -+ if (!krp) -+ return (ENOMEM); -+ bzero(krp, sizeof *krp); -+ krp->krp_op = kop->crk_op; -+ krp->krp_status = kop->crk_status; -+ krp->krp_iparams = kop->crk_iparams; -+ krp->krp_oparams = kop->crk_oparams; -+ krp->krp_crid = kop->crk_crid; -+ krp->krp_status = 0; -+ krp->krp_flags = CRYPTO_KF_CBIMM; -+ krp->krp_callback = (int (*) (struct cryptkop *)) cryptodevkey_cb; -+ init_waitqueue_head(&krp->krp_waitq); -+ -+ for (i = 0; i < CRK_MAXPARAM; i++) -+ krp->krp_param[i].crp_nbits = kop->crk_param[i].crp_nbits; -+ for (i = 0; i < krp->krp_iparams + krp->krp_oparams; i++) { -+ size = (krp->krp_param[i].crp_nbits + 7) / 8; -+ if (size == 0) -+ continue; -+ krp->krp_param[i].crp_p = (caddr_t) kmalloc(size, GFP_KERNEL); -+ if (i >= krp->krp_iparams) -+ continue; -+ error = copy_from_user(krp->krp_param[i].crp_p, -+ kop->crk_param[i].crp_p, size); -+ if (error) -+ goto fail; -+ } -+ -+ error = crypto_kdispatch(krp); -+ if (error) -+ goto fail; -+ -+ do { -+ error = wait_event_interruptible(krp->krp_waitq, -+ ((krp->krp_flags & CRYPTO_KF_DONE) != 0)); -+ /* -+ * we can't break out of this loop or we will leave behind -+ * a huge mess, however, staying here means if your driver -+ * is broken user applications can hang and not be killed. -+ * The solution, fix your driver :-) -+ */ -+ if (error) { -+ schedule(); -+ error = 0; -+ } -+ } while ((krp->krp_flags & CRYPTO_KF_DONE) == 0); -+ -+ dprintk("%s finished WAITING error=%d\n", __FUNCTION__, error); -+ -+ kop->crk_crid = krp->krp_crid; /* device that did the work */ -+ if (krp->krp_status != 0) { -+ error = krp->krp_status; -+ goto fail; -+ } -+ -+ for (i = krp->krp_iparams; i < krp->krp_iparams + krp->krp_oparams; i++) { -+ size = (krp->krp_param[i].crp_nbits + 7) / 8; -+ if (size == 0) -+ continue; -+ error = copy_to_user(kop->crk_param[i].crp_p, krp->krp_param[i].crp_p, -+ size); -+ if (error) -+ goto fail; -+ } -+ -+fail: -+ if (krp) { -+ kop->crk_status = krp->krp_status; -+ for (i = 0; i < CRK_MAXPARAM; i++) { -+ if (krp->krp_param[i].crp_p) -+ kfree(krp->krp_param[i].crp_p); -+ } -+ kfree(krp); -+ } -+ return (error); -+} -+ -+static int -+cryptodev_find(struct crypt_find_op *find) -+{ -+ device_t dev; -+ -+ if (find->crid != -1) { -+ dev = crypto_find_device_byhid(find->crid); -+ if (dev == NULL) -+ return (ENOENT); -+ strlcpy(find->name, device_get_nameunit(dev), -+ sizeof(find->name)); -+ } else { -+ find->crid = crypto_find_driver(find->name); -+ if (find->crid == -1) -+ return (ENOENT); -+ } -+ return (0); -+} -+ -+static struct csession * -+csefind(struct fcrypt *fcr, u_int ses) -+{ -+ struct csession *cse; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ list_for_each_entry(cse, &fcr->csessions, list) -+ if (cse->ses == ses) -+ return (cse); -+ return (NULL); -+} -+ -+static int -+csedelete(struct fcrypt *fcr, struct csession *cse_del) -+{ -+ struct csession *cse; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ list_for_each_entry(cse, &fcr->csessions, list) { -+ if (cse == cse_del) { -+ list_del(&cse->list); -+ return (1); -+ } -+ } -+ return (0); -+} -+ -+static struct csession * -+cseadd(struct fcrypt *fcr, struct csession *cse) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ list_add_tail(&cse->list, &fcr->csessions); -+ cse->ses = fcr->sesn++; -+ return (cse); -+} -+ -+static struct csession * -+csecreate(struct fcrypt *fcr, u_int64_t sid, struct cryptoini *crie, -+ struct cryptoini *cria, struct csession_info *info) -+{ -+ struct csession *cse; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ cse = (struct csession *) kmalloc(sizeof(struct csession), GFP_KERNEL); -+ if (cse == NULL) -+ return NULL; -+ memset(cse, 0, sizeof(struct csession)); -+ -+ INIT_LIST_HEAD(&cse->list); -+ init_waitqueue_head(&cse->waitq); -+ -+ cse->key = crie->cri_key; -+ cse->keylen = crie->cri_klen/8; -+ cse->mackey = cria->cri_key; -+ cse->mackeylen = cria->cri_klen/8; -+ cse->sid = sid; -+ cse->cipher = crie->cri_alg; -+ cse->mac = cria->cri_alg; -+ cse->info = *info; -+ cseadd(fcr, cse); -+ return (cse); -+} -+ -+static int -+csefree(struct csession *cse) -+{ -+ int error; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ error = crypto_freesession(cse->sid); -+ if (cse->key) -+ kfree(cse->key); -+ if (cse->mackey) -+ kfree(cse->mackey); -+ kfree(cse); -+ return(error); -+} -+ -+static int -+cryptodev_ioctl( -+ struct inode *inode, -+ struct file *filp, -+ unsigned int cmd, -+ unsigned long arg) -+{ -+ struct cryptoini cria, crie; -+ struct fcrypt *fcr = filp->private_data; -+ struct csession *cse; -+ struct csession_info info; -+ struct session2_op sop; -+ struct crypt_op cop; -+ struct crypt_kop kop; -+ struct crypt_find_op fop; -+ u_int64_t sid; -+ u_int32_t ses = 0; -+ int feat, fd, error = 0, crid; -+ mm_segment_t fs; -+ -+ dprintk("%s(cmd=%x arg=%lx)\n", __FUNCTION__, cmd, arg); -+ -+ switch (cmd) { -+ -+ case CRIOGET: { -+ dprintk("%s(CRIOGET)\n", __FUNCTION__); -+ fs = get_fs(); -+ set_fs(get_ds()); -+ for (fd = 0; fd < files_fdtable(current->files)->max_fds; fd++) -+ if (files_fdtable(current->files)->fd[fd] == filp) -+ break; -+ fd = sys_dup(fd); -+ set_fs(fs); -+ put_user(fd, (int *) arg); -+ return IS_ERR_VALUE(fd) ? fd : 0; -+ } -+ -+#define CIOCGSESSSTR (cmd == CIOCGSESSION ? "CIOCGSESSION" : "CIOCGSESSION2") -+ case CIOCGSESSION: -+ case CIOCGSESSION2: -+ dprintk("%s(%s)\n", __FUNCTION__, CIOCGSESSSTR); -+ memset(&crie, 0, sizeof(crie)); -+ memset(&cria, 0, sizeof(cria)); -+ memset(&info, 0, sizeof(info)); -+ memset(&sop, 0, sizeof(sop)); -+ -+ if (copy_from_user(&sop, (void*)arg, (cmd == CIOCGSESSION) ? -+ sizeof(struct session_op) : sizeof(sop))) { -+ dprintk("%s(%s) - bad copy\n", __FUNCTION__, CIOCGSESSSTR); -+ error = EFAULT; -+ goto bail; -+ } -+ -+ switch (sop.cipher) { -+ case 0: -+ dprintk("%s(%s) - no cipher\n", __FUNCTION__, CIOCGSESSSTR); -+ break; -+ case CRYPTO_NULL_CBC: -+ info.blocksize = NULL_BLOCK_LEN; -+ info.minkey = NULL_MIN_KEY_LEN; -+ info.maxkey = NULL_MAX_KEY_LEN; -+ break; -+ case CRYPTO_DES_CBC: -+ info.blocksize = DES_BLOCK_LEN; -+ info.minkey = DES_MIN_KEY_LEN; -+ info.maxkey = DES_MAX_KEY_LEN; -+ break; -+ case CRYPTO_3DES_CBC: -+ info.blocksize = DES3_BLOCK_LEN; -+ info.minkey = DES3_MIN_KEY_LEN; -+ info.maxkey = DES3_MAX_KEY_LEN; -+ break; -+ case CRYPTO_BLF_CBC: -+ info.blocksize = BLOWFISH_BLOCK_LEN; -+ info.minkey = BLOWFISH_MIN_KEY_LEN; -+ info.maxkey = BLOWFISH_MAX_KEY_LEN; -+ break; -+ case CRYPTO_CAST_CBC: -+ info.blocksize = CAST128_BLOCK_LEN; -+ info.minkey = CAST128_MIN_KEY_LEN; -+ info.maxkey = CAST128_MAX_KEY_LEN; -+ break; -+ case CRYPTO_SKIPJACK_CBC: -+ info.blocksize = SKIPJACK_BLOCK_LEN; -+ info.minkey = SKIPJACK_MIN_KEY_LEN; -+ info.maxkey = SKIPJACK_MAX_KEY_LEN; -+ break; -+ case CRYPTO_AES_CBC: -+ info.blocksize = AES_BLOCK_LEN; -+ info.minkey = AES_MIN_KEY_LEN; -+ info.maxkey = AES_MAX_KEY_LEN; -+ break; -+ case CRYPTO_ARC4: -+ info.blocksize = ARC4_BLOCK_LEN; -+ info.minkey = ARC4_MIN_KEY_LEN; -+ info.maxkey = ARC4_MAX_KEY_LEN; -+ break; -+ case CRYPTO_CAMELLIA_CBC: -+ info.blocksize = CAMELLIA_BLOCK_LEN; -+ info.minkey = CAMELLIA_MIN_KEY_LEN; -+ info.maxkey = CAMELLIA_MAX_KEY_LEN; -+ break; -+ default: -+ dprintk("%s(%s) - bad cipher\n", __FUNCTION__, CIOCGSESSSTR); -+ error = EINVAL; -+ goto bail; -+ } -+ -+ switch (sop.mac) { -+ case 0: -+ dprintk("%s(%s) - no mac\n", __FUNCTION__, CIOCGSESSSTR); -+ break; -+ case CRYPTO_NULL_HMAC: -+ info.authsize = NULL_HASH_LEN; -+ break; -+ case CRYPTO_MD5: -+ info.authsize = MD5_HASH_LEN; -+ break; -+ case CRYPTO_SHA1: -+ info.authsize = SHA1_HASH_LEN; -+ break; -+ case CRYPTO_SHA2_256: -+ info.authsize = SHA2_256_HASH_LEN; -+ break; -+ case CRYPTO_SHA2_384: -+ info.authsize = SHA2_384_HASH_LEN; -+ break; -+ case CRYPTO_SHA2_512: -+ info.authsize = SHA2_512_HASH_LEN; -+ break; -+ case CRYPTO_RIPEMD160: -+ info.authsize = RIPEMD160_HASH_LEN; -+ break; -+ case CRYPTO_MD5_HMAC: -+ info.authsize = MD5_HASH_LEN; -+ info.authkey = 16; -+ break; -+ case CRYPTO_SHA1_HMAC: -+ info.authsize = SHA1_HASH_LEN; -+ info.authkey = 20; -+ break; -+ case CRYPTO_SHA2_256_HMAC: -+ info.authsize = SHA2_256_HASH_LEN; -+ info.authkey = 32; -+ break; -+ case CRYPTO_SHA2_384_HMAC: -+ info.authsize = SHA2_384_HASH_LEN; -+ info.authkey = 48; -+ break; -+ case CRYPTO_SHA2_512_HMAC: -+ info.authsize = SHA2_512_HASH_LEN; -+ info.authkey = 64; -+ break; -+ case CRYPTO_RIPEMD160_HMAC: -+ info.authsize = RIPEMD160_HASH_LEN; -+ info.authkey = 20; -+ break; -+ default: -+ dprintk("%s(%s) - bad mac\n", __FUNCTION__, CIOCGSESSSTR); -+ error = EINVAL; -+ goto bail; -+ } -+ -+ if (info.blocksize) { -+ crie.cri_alg = sop.cipher; -+ crie.cri_klen = sop.keylen * 8; -+ if ((info.maxkey && sop.keylen > info.maxkey) || -+ sop.keylen < info.minkey) { -+ dprintk("%s(%s) - bad key\n", __FUNCTION__, CIOCGSESSSTR); -+ error = EINVAL; -+ goto bail; -+ } -+ -+ crie.cri_key = (u_int8_t *) kmalloc(crie.cri_klen/8+1, GFP_KERNEL); -+ if (copy_from_user(crie.cri_key, sop.key, -+ crie.cri_klen/8)) { -+ dprintk("%s(%s) - bad copy\n", __FUNCTION__, CIOCGSESSSTR); -+ error = EFAULT; -+ goto bail; -+ } -+ if (info.authsize) -+ crie.cri_next = &cria; -+ } -+ -+ if (info.authsize) { -+ cria.cri_alg = sop.mac; -+ cria.cri_klen = sop.mackeylen * 8; -+ if (info.authkey && sop.mackeylen != info.authkey) { -+ dprintk("%s(%s) - mackeylen %d != %d\n", __FUNCTION__, -+ CIOCGSESSSTR, sop.mackeylen, info.authkey); -+ error = EINVAL; -+ goto bail; -+ } -+ -+ if (cria.cri_klen) { -+ cria.cri_key = (u_int8_t *) kmalloc(cria.cri_klen/8,GFP_KERNEL); -+ if (copy_from_user(cria.cri_key, sop.mackey, -+ cria.cri_klen / 8)) { -+ dprintk("%s(%s) - bad copy\n", __FUNCTION__, CIOCGSESSSTR); -+ error = EFAULT; -+ goto bail; -+ } -+ } -+ } -+ -+ /* NB: CIOGSESSION2 has the crid */ -+ if (cmd == CIOCGSESSION2) { -+ crid = sop.crid; -+ error = checkcrid(crid); -+ if (error) { -+ dprintk("%s(%s) - checkcrid %x\n", __FUNCTION__, -+ CIOCGSESSSTR, error); -+ goto bail; -+ } -+ } else { -+ /* allow either HW or SW to be used */ -+ crid = CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE; -+ } -+ error = crypto_newsession(&sid, (info.blocksize ? &crie : &cria), crid); -+ if (error) { -+ dprintk("%s(%s) - newsession %d\n",__FUNCTION__,CIOCGSESSSTR,error); -+ goto bail; -+ } -+ -+ cse = csecreate(fcr, sid, &crie, &cria, &info); -+ if (cse == NULL) { -+ crypto_freesession(sid); -+ error = EINVAL; -+ dprintk("%s(%s) - csecreate failed\n", __FUNCTION__, CIOCGSESSSTR); -+ goto bail; -+ } -+ sop.ses = cse->ses; -+ -+ if (cmd == CIOCGSESSION2) { -+ /* return hardware/driver id */ -+ sop.crid = CRYPTO_SESID2HID(cse->sid); -+ } -+ -+ if (copy_to_user((void*)arg, &sop, (cmd == CIOCGSESSION) ? -+ sizeof(struct session_op) : sizeof(sop))) { -+ dprintk("%s(%s) - bad copy\n", __FUNCTION__, CIOCGSESSSTR); -+ error = EFAULT; -+ } -+bail: -+ if (error) { -+ dprintk("%s(%s) - bail %d\n", __FUNCTION__, CIOCGSESSSTR, error); -+ if (crie.cri_key) -+ kfree(crie.cri_key); -+ if (cria.cri_key) -+ kfree(cria.cri_key); -+ } -+ break; -+ case CIOCFSESSION: -+ dprintk("%s(CIOCFSESSION)\n", __FUNCTION__); -+ get_user(ses, (uint32_t*)arg); -+ cse = csefind(fcr, ses); -+ if (cse == NULL) { -+ error = EINVAL; -+ dprintk("%s(CIOCFSESSION) - Fail %d\n", __FUNCTION__, error); -+ break; -+ } -+ csedelete(fcr, cse); -+ error = csefree(cse); -+ break; -+ case CIOCCRYPT: -+ dprintk("%s(CIOCCRYPT)\n", __FUNCTION__); -+ if(copy_from_user(&cop, (void*)arg, sizeof(cop))) { -+ dprintk("%s(CIOCCRYPT) - bad copy\n", __FUNCTION__); -+ error = EFAULT; -+ goto bail; -+ } -+ cse = csefind(fcr, cop.ses); -+ if (cse == NULL) { -+ error = EINVAL; -+ dprintk("%s(CIOCCRYPT) - Fail %d\n", __FUNCTION__, error); -+ break; -+ } -+ error = cryptodev_op(cse, &cop); -+ if(copy_to_user((void*)arg, &cop, sizeof(cop))) { -+ dprintk("%s(CIOCCRYPT) - bad return copy\n", __FUNCTION__); -+ error = EFAULT; -+ goto bail; -+ } -+ break; -+ case CIOCKEY: -+ case CIOCKEY2: -+ dprintk("%s(CIOCKEY)\n", __FUNCTION__); -+ if (!crypto_userasymcrypto) -+ return (EPERM); /* XXX compat? */ -+ if(copy_from_user(&kop, (void*)arg, sizeof(kop))) { -+ dprintk("%s(CIOCKEY) - bad copy\n", __FUNCTION__); -+ error = EFAULT; -+ goto bail; -+ } -+ if (cmd == CIOCKEY) { -+ /* NB: crypto core enforces s/w driver use */ -+ kop.crk_crid = -+ CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE; -+ } -+ error = cryptodev_key(&kop); -+ if(copy_to_user((void*)arg, &kop, sizeof(kop))) { -+ dprintk("%s(CIOCGKEY) - bad return copy\n", __FUNCTION__); -+ error = EFAULT; -+ goto bail; -+ } -+ break; -+ case CIOCASYMFEAT: -+ dprintk("%s(CIOCASYMFEAT)\n", __FUNCTION__); -+ if (!crypto_userasymcrypto) { -+ /* -+ * NB: if user asym crypto operations are -+ * not permitted return "no algorithms" -+ * so well-behaved applications will just -+ * fallback to doing them in software. -+ */ -+ feat = 0; -+ } else -+ error = crypto_getfeat(&feat); -+ if (!error) { -+ error = copy_to_user((void*)arg, &feat, sizeof(feat)); -+ } -+ break; -+ case CIOCFINDDEV: -+ if (copy_from_user(&fop, (void*)arg, sizeof(fop))) { -+ dprintk("%s(CIOCFINDDEV) - bad copy\n", __FUNCTION__); -+ error = EFAULT; -+ goto bail; -+ } -+ error = cryptodev_find(&fop); -+ if (copy_to_user((void*)arg, &fop, sizeof(fop))) { -+ dprintk("%s(CIOCFINDDEV) - bad return copy\n", __FUNCTION__); -+ error = EFAULT; -+ goto bail; -+ } -+ break; -+ default: -+ dprintk("%s(unknown ioctl 0x%x)\n", __FUNCTION__, cmd); -+ error = EINVAL; -+ break; -+ } -+ return(-error); -+} -+ -+#ifdef HAVE_UNLOCKED_IOCTL -+static long -+cryptodev_unlocked_ioctl( -+ struct file *filp, -+ unsigned int cmd, -+ unsigned long arg) -+{ -+ return cryptodev_ioctl(NULL, filp, cmd, arg); -+} -+#endif -+ -+static int -+cryptodev_open(struct inode *inode, struct file *filp) -+{ -+ struct fcrypt *fcr; -+ -+ dprintk("%s()\n", __FUNCTION__); -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35) -+ /* -+ * on 2.6.35 private_data points to a miscdevice structure, we override -+ * it, which is currently safe to do. -+ */ -+ if (filp->private_data) { -+ printk("cryptodev: Private data already exists - %p!\n", filp->private_data); -+ return(-ENODEV); -+ } -+#endif -+ -+ fcr = kmalloc(sizeof(*fcr), GFP_KERNEL); -+ if (!fcr) { -+ dprintk("%s() - malloc failed\n", __FUNCTION__); -+ return(-ENOMEM); -+ } -+ memset(fcr, 0, sizeof(*fcr)); -+ -+ INIT_LIST_HEAD(&fcr->csessions); -+ filp->private_data = fcr; -+ return(0); -+} -+ -+static int -+cryptodev_release(struct inode *inode, struct file *filp) -+{ -+ struct fcrypt *fcr = filp->private_data; -+ struct csession *cse, *tmp; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (!filp) { -+ printk("cryptodev: No private data on release\n"); -+ return(0); -+ } -+ -+ list_for_each_entry_safe(cse, tmp, &fcr->csessions, list) { -+ list_del(&cse->list); -+ (void)csefree(cse); -+ } -+ filp->private_data = NULL; -+ kfree(fcr); -+ return(0); -+} -+ -+static struct file_operations cryptodev_fops = { -+ .owner = THIS_MODULE, -+ .open = cryptodev_open, -+ .release = cryptodev_release, -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36) -+ .ioctl = cryptodev_ioctl, -+#endif -+#ifdef HAVE_UNLOCKED_IOCTL -+ .unlocked_ioctl = cryptodev_unlocked_ioctl, -+#endif -+}; -+ -+static struct miscdevice cryptodev = { -+ .minor = CRYPTODEV_MINOR, -+ .name = "crypto", -+ .fops = &cryptodev_fops, -+}; -+ -+static int __init -+cryptodev_init(void) -+{ -+ int rc; -+ -+ dprintk("%s(%p)\n", __FUNCTION__, cryptodev_init); -+ rc = misc_register(&cryptodev); -+ if (rc) { -+ printk(KERN_ERR "cryptodev: registration of /dev/crypto failed\n"); -+ return(rc); -+ } -+ -+ return(0); -+} -+ -+static void __exit -+cryptodev_exit(void) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ misc_deregister(&cryptodev); -+} -+ -+module_init(cryptodev_init); -+module_exit(cryptodev_exit); -+ -+MODULE_LICENSE("BSD"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("Cryptodev (user interface to OCF)"); -diff -Nur linux-3.0.4.orig/crypto/ocf/cryptodev.h linux-3.0.4/crypto/ocf/cryptodev.h ---- linux-3.0.4.orig/crypto/ocf/cryptodev.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/cryptodev.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,480 @@ -+/* $FreeBSD: src/sys/opencrypto/cryptodev.h,v 1.25 2007/05/09 19:37:02 gnn Exp $ */ -+/* $OpenBSD: cryptodev.h,v 1.31 2002/06/11 11:14:29 beck Exp $ */ -+ -+/*- -+ * Linux port done by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * The license and original author are listed below. -+ * -+ * The author of this code is Angelos D. Keromytis (angelos@cis.upenn.edu) -+ * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting -+ * -+ * This code was written by Angelos D. Keromytis in Athens, Greece, in -+ * February 2000. Network Security Technologies Inc. (NSTI) kindly -+ * supported the development of this code. -+ * -+ * Copyright (c) 2000 Angelos D. Keromytis -+ * -+ * Permission to use, copy, and modify this software with or without fee -+ * is hereby granted, provided that this entire notice is included in -+ * all source code copies of any software which is or includes a copy or -+ * modification of this software. -+ * -+ * THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR -+ * IMPLIED WARRANTY. IN PARTICULAR, NONE OF THE AUTHORS MAKES ANY -+ * REPRESENTATION OR WARRANTY OF ANY KIND CONCERNING THE -+ * MERCHANTABILITY OF THIS SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR -+ * PURPOSE. -+ * -+ * Copyright (c) 2001 Theo de Raadt -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored in part by the Defense Advanced Research Projects -+ * Agency (DARPA) and Air Force Research Laboratory, Air Force -+ * Materiel Command, USAF, under agreement number F30602-01-2-0537. -+ * -+ */ -+ -+#ifndef _CRYPTO_CRYPTO_H_ -+#define _CRYPTO_CRYPTO_H_ -+ -+/* Some initial values */ -+#define CRYPTO_DRIVERS_INITIAL 4 -+#define CRYPTO_SW_SESSIONS 32 -+ -+/* Hash values */ -+#define NULL_HASH_LEN 0 -+#define MD5_HASH_LEN 16 -+#define SHA1_HASH_LEN 20 -+#define RIPEMD160_HASH_LEN 20 -+#define SHA2_256_HASH_LEN 32 -+#define SHA2_384_HASH_LEN 48 -+#define SHA2_512_HASH_LEN 64 -+#define MD5_KPDK_HASH_LEN 16 -+#define SHA1_KPDK_HASH_LEN 20 -+/* Maximum hash algorithm result length */ -+#define HASH_MAX_LEN SHA2_512_HASH_LEN /* Keep this updated */ -+ -+/* HMAC values */ -+#define NULL_HMAC_BLOCK_LEN 1 -+#define MD5_HMAC_BLOCK_LEN 64 -+#define SHA1_HMAC_BLOCK_LEN 64 -+#define RIPEMD160_HMAC_BLOCK_LEN 64 -+#define SHA2_256_HMAC_BLOCK_LEN 64 -+#define SHA2_384_HMAC_BLOCK_LEN 128 -+#define SHA2_512_HMAC_BLOCK_LEN 128 -+/* Maximum HMAC block length */ -+#define HMAC_MAX_BLOCK_LEN SHA2_512_HMAC_BLOCK_LEN /* Keep this updated */ -+#define HMAC_IPAD_VAL 0x36 -+#define HMAC_OPAD_VAL 0x5C -+ -+/* Encryption algorithm block sizes */ -+#define NULL_BLOCK_LEN 1 -+#define DES_BLOCK_LEN 8 -+#define DES3_BLOCK_LEN 8 -+#define BLOWFISH_BLOCK_LEN 8 -+#define SKIPJACK_BLOCK_LEN 8 -+#define CAST128_BLOCK_LEN 8 -+#define RIJNDAEL128_BLOCK_LEN 16 -+#define AES_BLOCK_LEN RIJNDAEL128_BLOCK_LEN -+#define CAMELLIA_BLOCK_LEN 16 -+#define ARC4_BLOCK_LEN 1 -+#define EALG_MAX_BLOCK_LEN AES_BLOCK_LEN /* Keep this updated */ -+ -+/* Encryption algorithm min and max key sizes */ -+#define NULL_MIN_KEY_LEN 0 -+#define NULL_MAX_KEY_LEN 0 -+#define DES_MIN_KEY_LEN 8 -+#define DES_MAX_KEY_LEN 8 -+#define DES3_MIN_KEY_LEN 24 -+#define DES3_MAX_KEY_LEN 24 -+#define BLOWFISH_MIN_KEY_LEN 4 -+#define BLOWFISH_MAX_KEY_LEN 56 -+#define SKIPJACK_MIN_KEY_LEN 10 -+#define SKIPJACK_MAX_KEY_LEN 10 -+#define CAST128_MIN_KEY_LEN 5 -+#define CAST128_MAX_KEY_LEN 16 -+#define RIJNDAEL128_MIN_KEY_LEN 16 -+#define RIJNDAEL128_MAX_KEY_LEN 32 -+#define AES_MIN_KEY_LEN RIJNDAEL128_MIN_KEY_LEN -+#define AES_MAX_KEY_LEN RIJNDAEL128_MAX_KEY_LEN -+#define CAMELLIA_MIN_KEY_LEN 16 -+#define CAMELLIA_MAX_KEY_LEN 32 -+#define ARC4_MIN_KEY_LEN 1 -+#define ARC4_MAX_KEY_LEN 256 -+ -+/* Max size of data that can be processed */ -+#define CRYPTO_MAX_DATA_LEN 64*1024 - 1 -+ -+#define CRYPTO_ALGORITHM_MIN 1 -+#define CRYPTO_DES_CBC 1 -+#define CRYPTO_3DES_CBC 2 -+#define CRYPTO_BLF_CBC 3 -+#define CRYPTO_CAST_CBC 4 -+#define CRYPTO_SKIPJACK_CBC 5 -+#define CRYPTO_MD5_HMAC 6 -+#define CRYPTO_SHA1_HMAC 7 -+#define CRYPTO_RIPEMD160_HMAC 8 -+#define CRYPTO_MD5_KPDK 9 -+#define CRYPTO_SHA1_KPDK 10 -+#define CRYPTO_RIJNDAEL128_CBC 11 /* 128 bit blocksize */ -+#define CRYPTO_AES_CBC 11 /* 128 bit blocksize -- the same as above */ -+#define CRYPTO_ARC4 12 -+#define CRYPTO_MD5 13 -+#define CRYPTO_SHA1 14 -+#define CRYPTO_NULL_HMAC 15 -+#define CRYPTO_NULL_CBC 16 -+#define CRYPTO_DEFLATE_COMP 17 /* Deflate compression algorithm */ -+#define CRYPTO_SHA2_256_HMAC 18 -+#define CRYPTO_SHA2_384_HMAC 19 -+#define CRYPTO_SHA2_512_HMAC 20 -+#define CRYPTO_CAMELLIA_CBC 21 -+#define CRYPTO_SHA2_256 22 -+#define CRYPTO_SHA2_384 23 -+#define CRYPTO_SHA2_512 24 -+#define CRYPTO_RIPEMD160 25 -+#define CRYPTO_LZS_COMP 26 -+#define CRYPTO_ALGORITHM_MAX 26 /* Keep updated - see above */ -+ -+/* Algorithm flags */ -+#define CRYPTO_ALG_FLAG_SUPPORTED 0x01 /* Algorithm is supported */ -+#define CRYPTO_ALG_FLAG_RNG_ENABLE 0x02 /* Has HW RNG for DH/DSA */ -+#define CRYPTO_ALG_FLAG_DSA_SHA 0x04 /* Can do SHA on msg */ -+ -+/* -+ * Crypto driver/device flags. They can set in the crid -+ * parameter when creating a session or submitting a key -+ * op to affect the device/driver assigned. If neither -+ * of these are specified then the crid is assumed to hold -+ * the driver id of an existing (and suitable) device that -+ * must be used to satisfy the request. -+ */ -+#define CRYPTO_FLAG_HARDWARE 0x01000000 /* hardware accelerated */ -+#define CRYPTO_FLAG_SOFTWARE 0x02000000 /* software implementation */ -+ -+/* NB: deprecated */ -+struct session_op { -+ u_int32_t cipher; /* ie. CRYPTO_DES_CBC */ -+ u_int32_t mac; /* ie. CRYPTO_MD5_HMAC */ -+ -+ u_int32_t keylen; /* cipher key */ -+ caddr_t key; -+ int mackeylen; /* mac key */ -+ caddr_t mackey; -+ -+ u_int32_t ses; /* returns: session # */ -+}; -+ -+struct session2_op { -+ u_int32_t cipher; /* ie. CRYPTO_DES_CBC */ -+ u_int32_t mac; /* ie. CRYPTO_MD5_HMAC */ -+ -+ u_int32_t keylen; /* cipher key */ -+ caddr_t key; -+ int mackeylen; /* mac key */ -+ caddr_t mackey; -+ -+ u_int32_t ses; /* returns: session # */ -+ int crid; /* driver id + flags (rw) */ -+ int pad[4]; /* for future expansion */ -+}; -+ -+struct crypt_op { -+ u_int32_t ses; -+ u_int16_t op; /* i.e. COP_ENCRYPT */ -+#define COP_NONE 0 -+#define COP_ENCRYPT 1 -+#define COP_DECRYPT 2 -+ u_int16_t flags; -+#define COP_F_BATCH 0x0008 /* Batch op if possible */ -+ u_int len; -+ caddr_t src, dst; /* become iov[] inside kernel */ -+ caddr_t mac; /* must be big enough for chosen MAC */ -+ caddr_t iv; -+}; -+ -+/* -+ * Parameters for looking up a crypto driver/device by -+ * device name or by id. The latter are returned for -+ * created sessions (crid) and completed key operations. -+ */ -+struct crypt_find_op { -+ int crid; /* driver id + flags */ -+ char name[32]; /* device/driver name */ -+}; -+ -+/* bignum parameter, in packed bytes, ... */ -+struct crparam { -+ caddr_t crp_p; -+ u_int crp_nbits; -+}; -+ -+#define CRK_MAXPARAM 8 -+ -+struct crypt_kop { -+ u_int crk_op; /* ie. CRK_MOD_EXP or other */ -+ u_int crk_status; /* return status */ -+ u_short crk_iparams; /* # of input parameters */ -+ u_short crk_oparams; /* # of output parameters */ -+ u_int crk_crid; /* NB: only used by CIOCKEY2 (rw) */ -+ struct crparam crk_param[CRK_MAXPARAM]; -+}; -+#define CRK_ALGORITM_MIN 0 -+#define CRK_MOD_EXP 0 -+#define CRK_MOD_EXP_CRT 1 -+#define CRK_DSA_SIGN 2 -+#define CRK_DSA_VERIFY 3 -+#define CRK_DH_COMPUTE_KEY 4 -+#define CRK_ALGORITHM_MAX 4 /* Keep updated - see below */ -+ -+#define CRF_MOD_EXP (1 << CRK_MOD_EXP) -+#define CRF_MOD_EXP_CRT (1 << CRK_MOD_EXP_CRT) -+#define CRF_DSA_SIGN (1 << CRK_DSA_SIGN) -+#define CRF_DSA_VERIFY (1 << CRK_DSA_VERIFY) -+#define CRF_DH_COMPUTE_KEY (1 << CRK_DH_COMPUTE_KEY) -+ -+/* -+ * done against open of /dev/crypto, to get a cloned descriptor. -+ * Please use F_SETFD against the cloned descriptor. -+ */ -+#define CRIOGET _IOWR('c', 100, u_int32_t) -+#define CRIOASYMFEAT CIOCASYMFEAT -+#define CRIOFINDDEV CIOCFINDDEV -+ -+/* the following are done against the cloned descriptor */ -+#define CIOCGSESSION _IOWR('c', 101, struct session_op) -+#define CIOCFSESSION _IOW('c', 102, u_int32_t) -+#define CIOCCRYPT _IOWR('c', 103, struct crypt_op) -+#define CIOCKEY _IOWR('c', 104, struct crypt_kop) -+#define CIOCASYMFEAT _IOR('c', 105, u_int32_t) -+#define CIOCGSESSION2 _IOWR('c', 106, struct session2_op) -+#define CIOCKEY2 _IOWR('c', 107, struct crypt_kop) -+#define CIOCFINDDEV _IOWR('c', 108, struct crypt_find_op) -+ -+struct cryptotstat { -+ struct timespec acc; /* total accumulated time */ -+ struct timespec min; /* min time */ -+ struct timespec max; /* max time */ -+ u_int32_t count; /* number of observations */ -+}; -+ -+struct cryptostats { -+ u_int32_t cs_ops; /* symmetric crypto ops submitted */ -+ u_int32_t cs_errs; /* symmetric crypto ops that failed */ -+ u_int32_t cs_kops; /* asymetric/key ops submitted */ -+ u_int32_t cs_kerrs; /* asymetric/key ops that failed */ -+ u_int32_t cs_intrs; /* crypto swi thread activations */ -+ u_int32_t cs_rets; /* crypto return thread activations */ -+ u_int32_t cs_blocks; /* symmetric op driver block */ -+ u_int32_t cs_kblocks; /* symmetric op driver block */ -+ /* -+ * When CRYPTO_TIMING is defined at compile time and the -+ * sysctl debug.crypto is set to 1, the crypto system will -+ * accumulate statistics about how long it takes to process -+ * crypto requests at various points during processing. -+ */ -+ struct cryptotstat cs_invoke; /* crypto_dipsatch -> crypto_invoke */ -+ struct cryptotstat cs_done; /* crypto_invoke -> crypto_done */ -+ struct cryptotstat cs_cb; /* crypto_done -> callback */ -+ struct cryptotstat cs_finis; /* callback -> callback return */ -+ -+ u_int32_t cs_drops; /* crypto ops dropped due to congestion */ -+}; -+ -+#ifdef __KERNEL__ -+ -+/* Standard initialization structure beginning */ -+struct cryptoini { -+ int cri_alg; /* Algorithm to use */ -+ int cri_klen; /* Key length, in bits */ -+ int cri_mlen; /* Number of bytes we want from the -+ entire hash. 0 means all. */ -+ caddr_t cri_key; /* key to use */ -+ u_int8_t cri_iv[EALG_MAX_BLOCK_LEN]; /* IV to use */ -+ struct cryptoini *cri_next; -+}; -+ -+/* Describe boundaries of a single crypto operation */ -+struct cryptodesc { -+ int crd_skip; /* How many bytes to ignore from start */ -+ int crd_len; /* How many bytes to process */ -+ int crd_inject; /* Where to inject results, if applicable */ -+ int crd_flags; -+ -+#define CRD_F_ENCRYPT 0x01 /* Set when doing encryption */ -+#define CRD_F_IV_PRESENT 0x02 /* When encrypting, IV is already in -+ place, so don't copy. */ -+#define CRD_F_IV_EXPLICIT 0x04 /* IV explicitly provided */ -+#define CRD_F_DSA_SHA_NEEDED 0x08 /* Compute SHA-1 of buffer for DSA */ -+#define CRD_F_KEY_EXPLICIT 0x10 /* Key explicitly provided */ -+#define CRD_F_COMP 0x0f /* Set when doing compression */ -+ -+ struct cryptoini CRD_INI; /* Initialization/context data */ -+#define crd_iv CRD_INI.cri_iv -+#define crd_key CRD_INI.cri_key -+#define crd_alg CRD_INI.cri_alg -+#define crd_klen CRD_INI.cri_klen -+#define crd_mlen CRD_INI.cri_mlen -+ -+ struct cryptodesc *crd_next; -+}; -+ -+/* Structure describing complete operation */ -+struct cryptop { -+ struct list_head crp_next; -+ wait_queue_head_t crp_waitq; -+ -+ u_int64_t crp_sid; /* Session ID */ -+ int crp_ilen; /* Input data total length */ -+ int crp_olen; /* Result total length */ -+ -+ int crp_etype; /* -+ * Error type (zero means no error). -+ * All error codes except EAGAIN -+ * indicate possible data corruption (as in, -+ * the data have been touched). On all -+ * errors, the crp_sid may have changed -+ * (reset to a new one), so the caller -+ * should always check and use the new -+ * value on future requests. -+ */ -+ int crp_flags; -+ -+#define CRYPTO_F_SKBUF 0x0001 /* Input/output are skbuf chains */ -+#define CRYPTO_F_IOV 0x0002 /* Input/output are uio */ -+#define CRYPTO_F_REL 0x0004 /* Must return data in same place */ -+#define CRYPTO_F_BATCH 0x0008 /* Batch op if possible */ -+#define CRYPTO_F_CBIMM 0x0010 /* Do callback immediately */ -+#define CRYPTO_F_DONE 0x0020 /* Operation completed */ -+#define CRYPTO_F_CBIFSYNC 0x0040 /* Do CBIMM if op is synchronous */ -+ -+ caddr_t crp_buf; /* Data to be processed */ -+ caddr_t crp_opaque; /* Opaque pointer, passed along */ -+ struct cryptodesc *crp_desc; /* Linked list of processing descriptors */ -+ -+ int (*crp_callback)(struct cryptop *); /* Callback function */ -+}; -+ -+#define CRYPTO_BUF_CONTIG 0x0 -+#define CRYPTO_BUF_IOV 0x1 -+#define CRYPTO_BUF_SKBUF 0x2 -+ -+#define CRYPTO_OP_DECRYPT 0x0 -+#define CRYPTO_OP_ENCRYPT 0x1 -+ -+/* -+ * Hints passed to process methods. -+ */ -+#define CRYPTO_HINT_MORE 0x1 /* more ops coming shortly */ -+ -+struct cryptkop { -+ struct list_head krp_next; -+ wait_queue_head_t krp_waitq; -+ -+ int krp_flags; -+#define CRYPTO_KF_DONE 0x0001 /* Operation completed */ -+#define CRYPTO_KF_CBIMM 0x0002 /* Do callback immediately */ -+ -+ u_int krp_op; /* ie. CRK_MOD_EXP or other */ -+ u_int krp_status; /* return status */ -+ u_short krp_iparams; /* # of input parameters */ -+ u_short krp_oparams; /* # of output parameters */ -+ u_int krp_crid; /* desired device, etc. */ -+ u_int32_t krp_hid; -+ struct crparam krp_param[CRK_MAXPARAM]; /* kvm */ -+ int (*krp_callback)(struct cryptkop *); -+}; -+ -+#include -+ -+/* -+ * Session ids are 64 bits. The lower 32 bits contain a "local id" which -+ * is a driver-private session identifier. The upper 32 bits contain a -+ * "hardware id" used by the core crypto code to identify the driver and -+ * a copy of the driver's capabilities that can be used by client code to -+ * optimize operation. -+ */ -+#define CRYPTO_SESID2HID(_sid) (((_sid) >> 32) & 0x00ffffff) -+#define CRYPTO_SESID2CAPS(_sid) (((_sid) >> 32) & 0xff000000) -+#define CRYPTO_SESID2LID(_sid) (((u_int32_t) (_sid)) & 0xffffffff) -+ -+extern int crypto_newsession(u_int64_t *sid, struct cryptoini *cri, int hard); -+extern int crypto_freesession(u_int64_t sid); -+#define CRYPTOCAP_F_HARDWARE CRYPTO_FLAG_HARDWARE -+#define CRYPTOCAP_F_SOFTWARE CRYPTO_FLAG_SOFTWARE -+#define CRYPTOCAP_F_SYNC 0x04000000 /* operates synchronously */ -+extern int32_t crypto_get_driverid(device_t dev, int flags); -+extern int crypto_find_driver(const char *); -+extern device_t crypto_find_device_byhid(int hid); -+extern int crypto_getcaps(int hid); -+extern int crypto_register(u_int32_t driverid, int alg, u_int16_t maxoplen, -+ u_int32_t flags); -+extern int crypto_kregister(u_int32_t, int, u_int32_t); -+extern int crypto_unregister(u_int32_t driverid, int alg); -+extern int crypto_unregister_all(u_int32_t driverid); -+extern int crypto_dispatch(struct cryptop *crp); -+extern int crypto_kdispatch(struct cryptkop *); -+#define CRYPTO_SYMQ 0x1 -+#define CRYPTO_ASYMQ 0x2 -+extern int crypto_unblock(u_int32_t, int); -+extern void crypto_done(struct cryptop *crp); -+extern void crypto_kdone(struct cryptkop *); -+extern int crypto_getfeat(int *); -+ -+extern void crypto_freereq(struct cryptop *crp); -+extern struct cryptop *crypto_getreq(int num); -+ -+extern int crypto_usercrypto; /* userland may do crypto requests */ -+extern int crypto_userasymcrypto; /* userland may do asym crypto reqs */ -+extern int crypto_devallowsoft; /* only use hardware crypto */ -+ -+/* -+ * random number support, crypto_unregister_all will unregister -+ */ -+extern int crypto_rregister(u_int32_t driverid, -+ int (*read_random)(void *arg, u_int32_t *buf, int len), void *arg); -+extern int crypto_runregister_all(u_int32_t driverid); -+ -+/* -+ * Crypto-related utility routines used mainly by drivers. -+ * -+ * XXX these don't really belong here; but for now they're -+ * kept apart from the rest of the system. -+ */ -+struct uio; -+extern void cuio_copydata(struct uio* uio, int off, int len, caddr_t cp); -+extern void cuio_copyback(struct uio* uio, int off, int len, caddr_t cp); -+extern struct iovec *cuio_getptr(struct uio *uio, int loc, int *off); -+ -+extern void crypto_copyback(int flags, caddr_t buf, int off, int size, -+ caddr_t in); -+extern void crypto_copydata(int flags, caddr_t buf, int off, int size, -+ caddr_t out); -+extern int crypto_apply(int flags, caddr_t buf, int off, int len, -+ int (*f)(void *, void *, u_int), void *arg); -+ -+#endif /* __KERNEL__ */ -+#endif /* _CRYPTO_CRYPTO_H_ */ -diff -Nur linux-3.0.4.orig/crypto/ocf/cryptosoft.c linux-3.0.4/crypto/ocf/cryptosoft.c ---- linux-3.0.4.orig/crypto/ocf/cryptosoft.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/cryptosoft.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,1320 @@ -+/* -+ * An OCF module that uses the linux kernel cryptoapi, based on the -+ * original cryptosoft for BSD by Angelos D. Keromytis (angelos@cis.upenn.edu) -+ * but is mostly unrecognisable, -+ * -+ * Written by David McCullough -+ * Copyright (C) 2004-2011 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * ALTERNATIVELY, provided that this notice is retained in full, this product -+ * may be distributed under the terms of the GNU General Public License (GPL), -+ * in which case the provisions of the GPL apply INSTEAD OF those given above. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ * --------------------------------------------------------------------------- -+ */ -+ -+#include -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,10) -+#include -+#endif -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29) -+#include -+#endif -+ -+#include -+#include -+ -+struct { -+ softc_device_decl sc_dev; -+} swcr_softc; -+ -+#define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK) -+ -+#define SW_TYPE_CIPHER 0x01 -+#define SW_TYPE_HMAC 0x02 -+#define SW_TYPE_HASH 0x04 -+#define SW_TYPE_COMP 0x08 -+#define SW_TYPE_BLKCIPHER 0x10 -+#define SW_TYPE_ALG_MASK 0x1f -+ -+#define SW_TYPE_ASYNC 0x8000 -+ -+#define SW_TYPE_INUSE 0x10000000 -+ -+/* We change some of the above if we have an async interface */ -+ -+#define SW_TYPE_ALG_AMASK (SW_TYPE_ALG_MASK | SW_TYPE_ASYNC) -+ -+#define SW_TYPE_ABLKCIPHER (SW_TYPE_BLKCIPHER | SW_TYPE_ASYNC) -+#define SW_TYPE_AHASH (SW_TYPE_HASH | SW_TYPE_ASYNC) -+#define SW_TYPE_AHMAC (SW_TYPE_HMAC | SW_TYPE_ASYNC) -+ -+#define SCATTERLIST_MAX 16 -+ -+struct swcr_data { -+ struct work_struct workq; -+ int sw_type; -+ int sw_alg; -+ struct crypto_tfm *sw_tfm; -+ spinlock_t sw_tfm_lock; -+ union { -+ struct { -+ char *sw_key; -+ int sw_klen; -+ int sw_mlen; -+ } hmac; -+ void *sw_comp_buf; -+ } u; -+ struct swcr_data *sw_next; -+}; -+ -+struct swcr_req { -+ struct swcr_data *sw_head; -+ struct swcr_data *sw; -+ struct cryptop *crp; -+ struct cryptodesc *crd; -+ struct scatterlist sg[SCATTERLIST_MAX]; -+ unsigned char iv[EALG_MAX_BLOCK_LEN]; -+ char result[HASH_MAX_LEN]; -+ void *crypto_req; -+}; -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) -+static kmem_cache_t *swcr_req_cache; -+#else -+static struct kmem_cache *swcr_req_cache; -+#endif -+ -+#ifndef CRYPTO_TFM_MODE_CBC -+/* -+ * As of linux-2.6.21 this is no longer defined, and presumably no longer -+ * needed to be passed into the crypto core code. -+ */ -+#define CRYPTO_TFM_MODE_CBC 0 -+#define CRYPTO_TFM_MODE_ECB 0 -+#endif -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) -+ /* -+ * Linux 2.6.19 introduced a new Crypto API, setup macro's to convert new -+ * API into old API. -+ */ -+ -+ /* Symmetric/Block Cipher */ -+ struct blkcipher_desc -+ { -+ struct crypto_tfm *tfm; -+ void *info; -+ }; -+ #define ecb(X) #X , CRYPTO_TFM_MODE_ECB -+ #define cbc(X) #X , CRYPTO_TFM_MODE_CBC -+ #define crypto_has_blkcipher(X, Y, Z) crypto_alg_available(X, 0) -+ #define crypto_blkcipher_cast(X) X -+ #define crypto_blkcipher_tfm(X) X -+ #define crypto_alloc_blkcipher(X, Y, Z) crypto_alloc_tfm(X, mode) -+ #define crypto_blkcipher_ivsize(X) crypto_tfm_alg_ivsize(X) -+ #define crypto_blkcipher_blocksize(X) crypto_tfm_alg_blocksize(X) -+ #define crypto_blkcipher_setkey(X, Y, Z) crypto_cipher_setkey(X, Y, Z) -+ #define crypto_blkcipher_encrypt_iv(W, X, Y, Z) \ -+ crypto_cipher_encrypt_iv((W)->tfm, X, Y, Z, (u8 *)((W)->info)) -+ #define crypto_blkcipher_decrypt_iv(W, X, Y, Z) \ -+ crypto_cipher_decrypt_iv((W)->tfm, X, Y, Z, (u8 *)((W)->info)) -+ #define crypto_blkcipher_set_flags(x, y) /* nop */ -+ #define crypto_free_blkcipher(x) crypto_free_tfm(x) -+ #define crypto_free_comp crypto_free_tfm -+ #define crypto_free_hash crypto_free_tfm -+ -+ /* Hash/HMAC/Digest */ -+ struct hash_desc -+ { -+ struct crypto_tfm *tfm; -+ }; -+ #define hmac(X) #X , 0 -+ #define crypto_has_hash(X, Y, Z) crypto_alg_available(X, 0) -+ #define crypto_hash_cast(X) X -+ #define crypto_hash_tfm(X) X -+ #define crypto_alloc_hash(X, Y, Z) crypto_alloc_tfm(X, mode) -+ #define crypto_hash_digestsize(X) crypto_tfm_alg_digestsize(X) -+ #define crypto_hash_digest(W, X, Y, Z) \ -+ crypto_digest_digest((W)->tfm, X, sg_num, Z) -+ -+ /* Asymmetric Cipher */ -+ #define crypto_has_cipher(X, Y, Z) crypto_alg_available(X, 0) -+ -+ /* Compression */ -+ #define crypto_has_comp(X, Y, Z) crypto_alg_available(X, 0) -+ #define crypto_comp_tfm(X) X -+ #define crypto_comp_cast(X) X -+ #define crypto_alloc_comp(X, Y, Z) crypto_alloc_tfm(X, mode) -+ #define plain(X) #X , 0 -+#else -+ #define ecb(X) "ecb(" #X ")" , 0 -+ #define cbc(X) "cbc(" #X ")" , 0 -+ #define hmac(X) "hmac(" #X ")" , 0 -+ #define plain(X) #X , 0 -+#endif /* if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) */ -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22) -+/* no ablkcipher in older kernels */ -+#define crypto_alloc_ablkcipher(a,b,c) (NULL) -+#define crypto_ablkcipher_tfm(x) ((struct crypto_tfm *)(x)) -+#define crypto_ablkcipher_set_flags(a, b) /* nop */ -+#define crypto_ablkcipher_setkey(x, y, z) (-EINVAL) -+#define crypto_has_ablkcipher(a,b,c) (0) -+#else -+#define HAVE_ABLKCIPHER -+#endif -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,32) -+/* no ahash in older kernels */ -+#define crypto_ahash_tfm(x) ((struct crypto_tfm *)(x)) -+#define crypto_alloc_ahash(a,b,c) (NULL) -+#define crypto_ahash_digestsize(x) 0 -+#else -+#define HAVE_AHASH -+#endif -+ -+struct crypto_details { -+ char *alg_name; -+ int mode; -+ int sw_type; -+}; -+ -+static struct crypto_details crypto_details[] = { -+ [CRYPTO_DES_CBC] = { cbc(des), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_3DES_CBC] = { cbc(des3_ede), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_BLF_CBC] = { cbc(blowfish), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_CAST_CBC] = { cbc(cast5), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_SKIPJACK_CBC] = { cbc(skipjack), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_MD5_HMAC] = { hmac(md5), SW_TYPE_HMAC, }, -+ [CRYPTO_SHA1_HMAC] = { hmac(sha1), SW_TYPE_HMAC, }, -+ [CRYPTO_RIPEMD160_HMAC] = { hmac(ripemd160), SW_TYPE_HMAC, }, -+ [CRYPTO_MD5_KPDK] = { plain(md5-kpdk), SW_TYPE_HASH, }, -+ [CRYPTO_SHA1_KPDK] = { plain(sha1-kpdk), SW_TYPE_HASH, }, -+ [CRYPTO_AES_CBC] = { cbc(aes), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_ARC4] = { ecb(arc4), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_MD5] = { plain(md5), SW_TYPE_HASH, }, -+ [CRYPTO_SHA1] = { plain(sha1), SW_TYPE_HASH, }, -+ [CRYPTO_NULL_HMAC] = { hmac(digest_null), SW_TYPE_HMAC, }, -+ [CRYPTO_NULL_CBC] = { cbc(cipher_null), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_DEFLATE_COMP] = { plain(deflate), SW_TYPE_COMP, }, -+ [CRYPTO_SHA2_256_HMAC] = { hmac(sha256), SW_TYPE_HMAC, }, -+ [CRYPTO_SHA2_384_HMAC] = { hmac(sha384), SW_TYPE_HMAC, }, -+ [CRYPTO_SHA2_512_HMAC] = { hmac(sha512), SW_TYPE_HMAC, }, -+ [CRYPTO_CAMELLIA_CBC] = { cbc(camellia), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_SHA2_256] = { plain(sha256), SW_TYPE_HASH, }, -+ [CRYPTO_SHA2_384] = { plain(sha384), SW_TYPE_HASH, }, -+ [CRYPTO_SHA2_512] = { plain(sha512), SW_TYPE_HASH, }, -+ [CRYPTO_RIPEMD160] = { plain(ripemd160), SW_TYPE_HASH, }, -+}; -+ -+int32_t swcr_id = -1; -+module_param(swcr_id, int, 0444); -+MODULE_PARM_DESC(swcr_id, "Read-Only OCF ID for cryptosoft driver"); -+ -+int swcr_fail_if_compression_grows = 1; -+module_param(swcr_fail_if_compression_grows, int, 0644); -+MODULE_PARM_DESC(swcr_fail_if_compression_grows, -+ "Treat compression that results in more data as a failure"); -+ -+int swcr_no_ahash = 0; -+module_param(swcr_no_ahash, int, 0644); -+MODULE_PARM_DESC(swcr_no_ahash, -+ "Do not use async hash/hmac even if available"); -+ -+int swcr_no_ablk = 0; -+module_param(swcr_no_ablk, int, 0644); -+MODULE_PARM_DESC(swcr_no_ablk, -+ "Do not use async blk ciphers even if available"); -+ -+static struct swcr_data **swcr_sessions = NULL; -+static u_int32_t swcr_sesnum = 0; -+ -+static int swcr_process(device_t, struct cryptop *, int); -+static int swcr_newsession(device_t, u_int32_t *, struct cryptoini *); -+static int swcr_freesession(device_t, u_int64_t); -+ -+static device_method_t swcr_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, swcr_newsession), -+ DEVMETHOD(cryptodev_freesession,swcr_freesession), -+ DEVMETHOD(cryptodev_process, swcr_process), -+}; -+ -+#define debug swcr_debug -+int swcr_debug = 0; -+module_param(swcr_debug, int, 0644); -+MODULE_PARM_DESC(swcr_debug, "Enable debug"); -+ -+static void swcr_process_req(struct swcr_req *req); -+ -+/* -+ * somethings just need to be run with user context no matter whether -+ * the kernel compression libs use vmalloc/vfree for example. -+ */ -+ -+typedef struct { -+ struct work_struct wq; -+ void (*func)(void *arg); -+ void *arg; -+} execute_later_t; -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void -+doing_it_now(struct work_struct *wq) -+{ -+ execute_later_t *w = container_of(wq, execute_later_t, wq); -+ (w->func)(w->arg); -+ kfree(w); -+} -+#else -+static void -+doing_it_now(void *arg) -+{ -+ execute_later_t *w = (execute_later_t *) arg; -+ (w->func)(w->arg); -+ kfree(w); -+} -+#endif -+ -+static void -+execute_later(void (fn)(void *), void *arg) -+{ -+ execute_later_t *w; -+ -+ w = (execute_later_t *) kmalloc(sizeof(execute_later_t), SLAB_ATOMIC); -+ if (w) { -+ memset(w, '\0', sizeof(w)); -+ w->func = fn; -+ w->arg = arg; -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ INIT_WORK(&w->wq, doing_it_now); -+#else -+ INIT_WORK(&w->wq, doing_it_now, w); -+#endif -+ schedule_work(&w->wq); -+ } -+} -+ -+/* -+ * Generate a new software session. -+ */ -+static int -+swcr_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) -+{ -+ struct swcr_data **swd; -+ u_int32_t i; -+ int error; -+ char *algo; -+ int mode; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid == NULL || cri == NULL) { -+ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ if (swcr_sessions) { -+ for (i = 1; i < swcr_sesnum; i++) -+ if (swcr_sessions[i] == NULL) -+ break; -+ } else -+ i = 1; /* NB: to silence compiler warning */ -+ -+ if (swcr_sessions == NULL || i == swcr_sesnum) { -+ if (swcr_sessions == NULL) { -+ i = 1; /* We leave swcr_sessions[0] empty */ -+ swcr_sesnum = CRYPTO_SW_SESSIONS; -+ } else -+ swcr_sesnum *= 2; -+ -+ swd = kmalloc(swcr_sesnum * sizeof(struct swcr_data *), SLAB_ATOMIC); -+ if (swd == NULL) { -+ /* Reset session number */ -+ if (swcr_sesnum == CRYPTO_SW_SESSIONS) -+ swcr_sesnum = 0; -+ else -+ swcr_sesnum /= 2; -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memset(swd, 0, swcr_sesnum * sizeof(struct swcr_data *)); -+ -+ /* Copy existing sessions */ -+ if (swcr_sessions) { -+ memcpy(swd, swcr_sessions, -+ (swcr_sesnum / 2) * sizeof(struct swcr_data *)); -+ kfree(swcr_sessions); -+ } -+ -+ swcr_sessions = swd; -+ } -+ -+ swd = &swcr_sessions[i]; -+ *sid = i; -+ -+ while (cri) { -+ *swd = (struct swcr_data *) kmalloc(sizeof(struct swcr_data), -+ SLAB_ATOMIC); -+ if (*swd == NULL) { -+ swcr_freesession(NULL, i); -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memset(*swd, 0, sizeof(struct swcr_data)); -+ -+ if (cri->cri_alg < 0 || -+ cri->cri_alg>=sizeof(crypto_details)/sizeof(crypto_details[0])){ -+ printk("cryptosoft: Unknown algorithm 0x%x\n", cri->cri_alg); -+ swcr_freesession(NULL, i); -+ return EINVAL; -+ } -+ -+ algo = crypto_details[cri->cri_alg].alg_name; -+ if (!algo || !*algo) { -+ printk("cryptosoft: Unsupported algorithm 0x%x\n", cri->cri_alg); -+ swcr_freesession(NULL, i); -+ return EINVAL; -+ } -+ -+ mode = crypto_details[cri->cri_alg].mode; -+ (*swd)->sw_type = crypto_details[cri->cri_alg].sw_type; -+ (*swd)->sw_alg = cri->cri_alg; -+ -+ spin_lock_init(&(*swd)->sw_tfm_lock); -+ -+ /* Algorithm specific configuration */ -+ switch (cri->cri_alg) { -+ case CRYPTO_NULL_CBC: -+ cri->cri_klen = 0; /* make it work with crypto API */ -+ break; -+ default: -+ break; -+ } -+ -+ if ((*swd)->sw_type & SW_TYPE_BLKCIPHER) { -+ dprintk("%s crypto_alloc_*blkcipher(%s, 0x%x)\n", __FUNCTION__, -+ algo, mode); -+ -+ /* try async first */ -+ (*swd)->sw_tfm = swcr_no_ablk ? NULL : -+ crypto_ablkcipher_tfm(crypto_alloc_ablkcipher(algo, 0, 0)); -+ if ((*swd)->sw_tfm && !IS_ERR((*swd)->sw_tfm)) { -+ dprintk("%s %s cipher is async\n", __FUNCTION__, algo); -+ (*swd)->sw_type |= SW_TYPE_ASYNC; -+ } else { -+ (*swd)->sw_tfm = crypto_blkcipher_tfm( -+ crypto_alloc_blkcipher(algo, 0, CRYPTO_ALG_ASYNC)); -+ if ((*swd)->sw_tfm && !IS_ERR((*swd)->sw_tfm)) -+ dprintk("%s %s cipher is sync\n", __FUNCTION__, algo); -+ } -+ if (!(*swd)->sw_tfm || IS_ERR((*swd)->sw_tfm)) { -+ int err; -+ dprintk("cryptosoft: crypto_alloc_blkcipher failed(%s, 0x%x)\n", -+ algo,mode); -+ err = IS_ERR((*swd)->sw_tfm) ? -(PTR_ERR((*swd)->sw_tfm)) : EINVAL; -+ (*swd)->sw_tfm = NULL; /* ensure NULL */ -+ swcr_freesession(NULL, i); -+ return err; -+ } -+ -+ if (debug) { -+ dprintk("%s key:cri->cri_klen=%d,(cri->cri_klen + 7)/8=%d", -+ __FUNCTION__, cri->cri_klen, (cri->cri_klen + 7) / 8); -+ for (i = 0; i < (cri->cri_klen + 7) / 8; i++) -+ dprintk("%s0x%x", (i % 8) ? " " : "\n ", -+ cri->cri_key[i] & 0xff); -+ dprintk("\n"); -+ } -+ if ((*swd)->sw_type & SW_TYPE_ASYNC) { -+ /* OCF doesn't enforce keys */ -+ crypto_ablkcipher_set_flags( -+ __crypto_ablkcipher_cast((*swd)->sw_tfm), -+ CRYPTO_TFM_REQ_WEAK_KEY); -+ error = crypto_ablkcipher_setkey( -+ __crypto_ablkcipher_cast((*swd)->sw_tfm), -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ } else { -+ /* OCF doesn't enforce keys */ -+ crypto_blkcipher_set_flags( -+ crypto_blkcipher_cast((*swd)->sw_tfm), -+ CRYPTO_TFM_REQ_WEAK_KEY); -+ error = crypto_blkcipher_setkey( -+ crypto_blkcipher_cast((*swd)->sw_tfm), -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ } -+ if (error) { -+ printk("cryptosoft: setkey failed %d (crt_flags=0x%x)\n", error, -+ (*swd)->sw_tfm->crt_flags); -+ swcr_freesession(NULL, i); -+ return error; -+ } -+ } else if ((*swd)->sw_type & (SW_TYPE_HMAC | SW_TYPE_HASH)) { -+ dprintk("%s crypto_alloc_*hash(%s, 0x%x)\n", __FUNCTION__, -+ algo, mode); -+ -+ /* try async first */ -+ (*swd)->sw_tfm = swcr_no_ahash ? NULL : -+ crypto_ahash_tfm(crypto_alloc_ahash(algo, 0, 0)); -+ if ((*swd)->sw_tfm) { -+ dprintk("%s %s hash is async\n", __FUNCTION__, algo); -+ (*swd)->sw_type |= SW_TYPE_ASYNC; -+ } else { -+ dprintk("%s %s hash is sync\n", __FUNCTION__, algo); -+ (*swd)->sw_tfm = crypto_hash_tfm( -+ crypto_alloc_hash(algo, 0, CRYPTO_ALG_ASYNC)); -+ } -+ -+ if (!(*swd)->sw_tfm) { -+ dprintk("cryptosoft: crypto_alloc_hash failed(%s,0x%x)\n", -+ algo, mode); -+ swcr_freesession(NULL, i); -+ return EINVAL; -+ } -+ -+ (*swd)->u.hmac.sw_klen = (cri->cri_klen + 7) / 8; -+ (*swd)->u.hmac.sw_key = (char *)kmalloc((*swd)->u.hmac.sw_klen, -+ SLAB_ATOMIC); -+ if ((*swd)->u.hmac.sw_key == NULL) { -+ swcr_freesession(NULL, i); -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memcpy((*swd)->u.hmac.sw_key, cri->cri_key, (*swd)->u.hmac.sw_klen); -+ if (cri->cri_mlen) { -+ (*swd)->u.hmac.sw_mlen = cri->cri_mlen; -+ } else if ((*swd)->sw_type & SW_TYPE_ASYNC) { -+ (*swd)->u.hmac.sw_mlen = crypto_ahash_digestsize( -+ __crypto_ahash_cast((*swd)->sw_tfm)); -+ } else { -+ (*swd)->u.hmac.sw_mlen = crypto_hash_digestsize( -+ crypto_hash_cast((*swd)->sw_tfm)); -+ } -+ } else if ((*swd)->sw_type & SW_TYPE_COMP) { -+ (*swd)->sw_tfm = crypto_comp_tfm( -+ crypto_alloc_comp(algo, 0, CRYPTO_ALG_ASYNC)); -+ if (!(*swd)->sw_tfm) { -+ dprintk("cryptosoft: crypto_alloc_comp failed(%s,0x%x)\n", -+ algo, mode); -+ swcr_freesession(NULL, i); -+ return EINVAL; -+ } -+ (*swd)->u.sw_comp_buf = kmalloc(CRYPTO_MAX_DATA_LEN, SLAB_ATOMIC); -+ if ((*swd)->u.sw_comp_buf == NULL) { -+ swcr_freesession(NULL, i); -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ } else { -+ printk("cryptosoft: Unhandled sw_type %d\n", (*swd)->sw_type); -+ swcr_freesession(NULL, i); -+ return EINVAL; -+ } -+ -+ cri = cri->cri_next; -+ swd = &((*swd)->sw_next); -+ } -+ return 0; -+} -+ -+/* -+ * Free a session. -+ */ -+static int -+swcr_freesession(device_t dev, u_int64_t tid) -+{ -+ struct swcr_data *swd; -+ u_int32_t sid = CRYPTO_SESID2LID(tid); -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid > swcr_sesnum || swcr_sessions == NULL || -+ swcr_sessions[sid] == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return(EINVAL); -+ } -+ -+ /* Silently accept and return */ -+ if (sid == 0) -+ return(0); -+ -+ while ((swd = swcr_sessions[sid]) != NULL) { -+ swcr_sessions[sid] = swd->sw_next; -+ if (swd->sw_tfm) { -+ switch (swd->sw_type & SW_TYPE_ALG_AMASK) { -+#ifdef HAVE_AHASH -+ case SW_TYPE_AHMAC: -+ case SW_TYPE_AHASH: -+ crypto_free_ahash(__crypto_ahash_cast(swd->sw_tfm)); -+ break; -+#endif -+#ifdef HAVE_ABLKCIPHER -+ case SW_TYPE_ABLKCIPHER: -+ crypto_free_ablkcipher(__crypto_ablkcipher_cast(swd->sw_tfm)); -+ break; -+#endif -+ case SW_TYPE_BLKCIPHER: -+ crypto_free_blkcipher(crypto_blkcipher_cast(swd->sw_tfm)); -+ break; -+ case SW_TYPE_HMAC: -+ case SW_TYPE_HASH: -+ crypto_free_hash(crypto_hash_cast(swd->sw_tfm)); -+ break; -+ case SW_TYPE_COMP: -+ if (in_interrupt()) -+ execute_later((void (*)(void *))crypto_free_comp, (void *)crypto_comp_cast(swd->sw_tfm)); -+ else -+ crypto_free_comp(crypto_comp_cast(swd->sw_tfm)); -+ break; -+ default: -+ crypto_free_tfm(swd->sw_tfm); -+ break; -+ } -+ swd->sw_tfm = NULL; -+ } -+ if (swd->sw_type & SW_TYPE_COMP) { -+ if (swd->u.sw_comp_buf) -+ kfree(swd->u.sw_comp_buf); -+ } else { -+ if (swd->u.hmac.sw_key) -+ kfree(swd->u.hmac.sw_key); -+ } -+ kfree(swd); -+ } -+ return 0; -+} -+ -+static void swcr_process_req_complete(struct swcr_req *req) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (req->sw->sw_type & SW_TYPE_INUSE) { -+ unsigned long flags; -+ spin_lock_irqsave(&req->sw->sw_tfm_lock, flags); -+ req->sw->sw_type &= ~SW_TYPE_INUSE; -+ spin_unlock_irqrestore(&req->sw->sw_tfm_lock, flags); -+ } -+ -+ if (req->crp->crp_etype) -+ goto done; -+ -+ switch (req->sw->sw_type & SW_TYPE_ALG_AMASK) { -+#if defined(HAVE_AHASH) -+ case SW_TYPE_AHMAC: -+ case SW_TYPE_AHASH: -+ crypto_copyback(req->crp->crp_flags, req->crp->crp_buf, -+ req->crd->crd_inject, req->sw->u.hmac.sw_mlen, req->result); -+ ahash_request_free(req->crypto_req); -+ break; -+#endif -+#if defined(HAVE_ABLKCIPHER) -+ case SW_TYPE_ABLKCIPHER: -+ ablkcipher_request_free(req->crypto_req); -+ break; -+#endif -+ case SW_TYPE_CIPHER: -+ case SW_TYPE_HMAC: -+ case SW_TYPE_HASH: -+ case SW_TYPE_COMP: -+ case SW_TYPE_BLKCIPHER: -+ break; -+ default: -+ req->crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ req->crd = req->crd->crd_next; -+ if (req->crd) { -+ swcr_process_req(req); -+ return; -+ } -+ -+done: -+ dprintk("%s crypto_done %p\n", __FUNCTION__, req); -+ crypto_done(req->crp); -+ kmem_cache_free(swcr_req_cache, req); -+} -+ -+#if defined(HAVE_ABLKCIPHER) || defined(HAVE_AHASH) -+static void swcr_process_callback(struct crypto_async_request *creq, int err) -+{ -+ struct swcr_req *req = creq->data; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (err) { -+ if (err == -EINPROGRESS) -+ return; -+ dprintk("%s() fail %d\n", __FUNCTION__, -err); -+ req->crp->crp_etype = -err; -+ } -+ -+ swcr_process_req_complete(req); -+} -+#endif /* defined(HAVE_ABLKCIPHER) || defined(HAVE_AHASH) */ -+ -+ -+static void swcr_process_req(struct swcr_req *req) -+{ -+ struct swcr_data *sw; -+ struct cryptop *crp = req->crp; -+ struct cryptodesc *crd = req->crd; -+ struct sk_buff *skb = (struct sk_buff *) crp->crp_buf; -+ struct uio *uiop = (struct uio *) crp->crp_buf; -+ int sg_num, sg_len, skip; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ /* -+ * Find the crypto context. -+ * -+ * XXX Note that the logic here prevents us from having -+ * XXX the same algorithm multiple times in a session -+ * XXX (or rather, we can but it won't give us the right -+ * XXX results). To do that, we'd need some way of differentiating -+ * XXX between the various instances of an algorithm (so we can -+ * XXX locate the correct crypto context). -+ */ -+ for (sw = req->sw_head; sw && sw->sw_alg != crd->crd_alg; sw = sw->sw_next) -+ ; -+ -+ /* No such context ? */ -+ if (sw == NULL) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ goto done; -+ } -+ -+ /* -+ * for some types we need to ensure only one user as info is stored in -+ * the tfm during an operation that can get corrupted -+ */ -+ switch (sw->sw_type & SW_TYPE_ALG_AMASK) { -+#ifdef HAVE_AHASH -+ case SW_TYPE_AHMAC: -+ case SW_TYPE_AHASH: -+#endif -+ case SW_TYPE_HMAC: -+ case SW_TYPE_HASH: { -+ unsigned long flags; -+ spin_lock_irqsave(&sw->sw_tfm_lock, flags); -+ if (sw->sw_type & SW_TYPE_INUSE) { -+ spin_unlock_irqrestore(&sw->sw_tfm_lock, flags); -+ execute_later((void (*)(void *))swcr_process_req, (void *)req); -+ return; -+ } -+ sw->sw_type |= SW_TYPE_INUSE; -+ spin_unlock_irqrestore(&sw->sw_tfm_lock, flags); -+ } break; -+ } -+ -+ req->sw = sw; -+ skip = crd->crd_skip; -+ -+ /* -+ * setup the SG list skip from the start of the buffer -+ */ -+ memset(req->sg, 0, sizeof(req->sg)); -+ sg_init_table(req->sg, SCATTERLIST_MAX); -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ int i, len; -+ -+ sg_num = 0; -+ sg_len = 0; -+ -+ if (skip < skb_headlen(skb)) { -+ len = skb_headlen(skb) - skip; -+ if (len + sg_len > crd->crd_len) -+ len = crd->crd_len - sg_len; -+ sg_set_page(&req->sg[sg_num], -+ virt_to_page(skb->data + skip), len, -+ offset_in_page(skb->data + skip)); -+ sg_len += len; -+ sg_num++; -+ skip = 0; -+ } else -+ skip -= skb_headlen(skb); -+ -+ for (i = 0; sg_len < crd->crd_len && -+ i < skb_shinfo(skb)->nr_frags && -+ sg_num < SCATTERLIST_MAX; i++) { -+ if (skip < skb_shinfo(skb)->frags[i].size) { -+ len = skb_shinfo(skb)->frags[i].size - skip; -+ if (len + sg_len > crd->crd_len) -+ len = crd->crd_len - sg_len; -+ sg_set_page(&req->sg[sg_num], -+ skb_shinfo(skb)->frags[i].page, -+ len, -+ skb_shinfo(skb)->frags[i].page_offset + skip); -+ sg_len += len; -+ sg_num++; -+ skip = 0; -+ } else -+ skip -= skb_shinfo(skb)->frags[i].size; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ int len; -+ -+ sg_len = 0; -+ for (sg_num = 0; sg_len < crd->crd_len && -+ sg_num < uiop->uio_iovcnt && -+ sg_num < SCATTERLIST_MAX; sg_num++) { -+ if (skip <= uiop->uio_iov[sg_num].iov_len) { -+ len = uiop->uio_iov[sg_num].iov_len - skip; -+ if (len + sg_len > crd->crd_len) -+ len = crd->crd_len - sg_len; -+ sg_set_page(&req->sg[sg_num], -+ virt_to_page(uiop->uio_iov[sg_num].iov_base+skip), -+ len, -+ offset_in_page(uiop->uio_iov[sg_num].iov_base+skip)); -+ sg_len += len; -+ skip = 0; -+ } else -+ skip -= uiop->uio_iov[sg_num].iov_len; -+ } -+ } else { -+ sg_len = (crp->crp_ilen - skip); -+ if (sg_len > crd->crd_len) -+ sg_len = crd->crd_len; -+ sg_set_page(&req->sg[0], virt_to_page(crp->crp_buf + skip), -+ sg_len, offset_in_page(crp->crp_buf + skip)); -+ sg_num = 1; -+ } -+ -+ switch (sw->sw_type & SW_TYPE_ALG_AMASK) { -+ -+#ifdef HAVE_AHASH -+ case SW_TYPE_AHMAC: -+ case SW_TYPE_AHASH: -+ { -+ int ret; -+ -+ /* check we have room for the result */ -+ if (crp->crp_ilen - crd->crd_inject < sw->u.hmac.sw_mlen) { -+ dprintk("cryptosoft: EINVAL crp_ilen=%d, len=%d, inject=%d " -+ "digestsize=%d\n", crp->crp_ilen, crd->crd_skip + sg_len, -+ crd->crd_inject, sw->u.hmac.sw_mlen); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ req->crypto_req = -+ ahash_request_alloc(__crypto_ahash_cast(sw->sw_tfm),GFP_ATOMIC); -+ if (!req->crypto_req) { -+ crp->crp_etype = ENOMEM; -+ dprintk("%s,%d: ENOMEM ahash_request_alloc", __FILE__, __LINE__); -+ goto done; -+ } -+ -+ ahash_request_set_callback(req->crypto_req, -+ CRYPTO_TFM_REQ_MAY_BACKLOG, swcr_process_callback, req); -+ -+ memset(req->result, 0, sizeof(req->result)); -+ -+ if (sw->sw_type & SW_TYPE_AHMAC) -+ crypto_ahash_setkey(__crypto_ahash_cast(sw->sw_tfm), -+ sw->u.hmac.sw_key, sw->u.hmac.sw_klen); -+ ahash_request_set_crypt(req->crypto_req, req->sg, req->result, sg_len); -+ ret = crypto_ahash_digest(req->crypto_req); -+ switch (ret) { -+ case -EINPROGRESS: -+ case -EBUSY: -+ return; -+ default: -+ case 0: -+ dprintk("hash OP %s %d\n", ret ? "failed" : "success", ret); -+ crp->crp_etype = ret; -+ goto done; -+ } -+ } break; -+#endif /* HAVE_AHASH */ -+ -+#ifdef HAVE_ABLKCIPHER -+ case SW_TYPE_ABLKCIPHER: { -+ int ret; -+ unsigned char *ivp = req->iv; -+ int ivsize = -+ crypto_ablkcipher_ivsize(__crypto_ablkcipher_cast(sw->sw_tfm)); -+ -+ if (sg_len < crypto_ablkcipher_blocksize( -+ __crypto_ablkcipher_cast(sw->sw_tfm))) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: EINVAL len %d < %d\n", __FILE__, __LINE__, -+ sg_len, crypto_ablkcipher_blocksize( -+ __crypto_ablkcipher_cast(sw->sw_tfm))); -+ goto done; -+ } -+ -+ if (ivsize > sizeof(req->iv)) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ goto done; -+ } -+ -+ req->crypto_req = ablkcipher_request_alloc( -+ __crypto_ablkcipher_cast(sw->sw_tfm), GFP_ATOMIC); -+ if (!req->crypto_req) { -+ crp->crp_etype = ENOMEM; -+ dprintk("%s,%d: ENOMEM ablkcipher_request_alloc", -+ __FILE__, __LINE__); -+ goto done; -+ } -+ -+ ablkcipher_request_set_callback(req->crypto_req, -+ CRYPTO_TFM_REQ_MAY_BACKLOG, swcr_process_callback, req); -+ -+ if (crd->crd_flags & CRD_F_KEY_EXPLICIT) { -+ int i, error; -+ -+ if (debug) { -+ dprintk("%s key:", __FUNCTION__); -+ for (i = 0; i < (crd->crd_klen + 7) / 8; i++) -+ dprintk("%s0x%x", (i % 8) ? " " : "\n ", -+ crd->crd_key[i] & 0xff); -+ dprintk("\n"); -+ } -+ /* OCF doesn't enforce keys */ -+ crypto_ablkcipher_set_flags(__crypto_ablkcipher_cast(sw->sw_tfm), -+ CRYPTO_TFM_REQ_WEAK_KEY); -+ error = crypto_ablkcipher_setkey( -+ __crypto_ablkcipher_cast(sw->sw_tfm), crd->crd_key, -+ (crd->crd_klen + 7) / 8); -+ if (error) { -+ dprintk("cryptosoft: setkey failed %d (crt_flags=0x%x)\n", -+ error, sw->sw_tfm->crt_flags); -+ crp->crp_etype = -error; -+ } -+ } -+ -+ if (crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ -+ -+ if (crd->crd_flags & CRD_F_IV_EXPLICIT) -+ ivp = crd->crd_iv; -+ else -+ get_random_bytes(ivp, ivsize); -+ /* -+ * do we have to copy the IV back to the buffer ? -+ */ -+ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, ivsize, (caddr_t)ivp); -+ } -+ ablkcipher_request_set_crypt(req->crypto_req, req->sg, req->sg, -+ sg_len, ivp); -+ ret = crypto_ablkcipher_encrypt(req->crypto_req); -+ -+ } else { /*decrypt */ -+ -+ if (crd->crd_flags & CRD_F_IV_EXPLICIT) -+ ivp = crd->crd_iv; -+ else -+ crypto_copydata(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, ivsize, (caddr_t)ivp); -+ ablkcipher_request_set_crypt(req->crypto_req, req->sg, req->sg, -+ sg_len, ivp); -+ ret = crypto_ablkcipher_decrypt(req->crypto_req); -+ } -+ -+ switch (ret) { -+ case -EINPROGRESS: -+ case -EBUSY: -+ return; -+ default: -+ case 0: -+ dprintk("crypto OP %s %d\n", ret ? "failed" : "success", ret); -+ crp->crp_etype = ret; -+ goto done; -+ } -+ } break; -+#endif /* HAVE_ABLKCIPHER */ -+ -+ case SW_TYPE_BLKCIPHER: { -+ unsigned char iv[EALG_MAX_BLOCK_LEN]; -+ unsigned char *ivp = iv; -+ struct blkcipher_desc desc; -+ int ivsize = crypto_blkcipher_ivsize(crypto_blkcipher_cast(sw->sw_tfm)); -+ -+ if (sg_len < crypto_blkcipher_blocksize( -+ crypto_blkcipher_cast(sw->sw_tfm))) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: EINVAL len %d < %d\n", __FILE__, __LINE__, -+ sg_len, crypto_blkcipher_blocksize( -+ crypto_blkcipher_cast(sw->sw_tfm))); -+ goto done; -+ } -+ -+ if (ivsize > sizeof(iv)) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ goto done; -+ } -+ -+ if (crd->crd_flags & CRD_F_KEY_EXPLICIT) { -+ int i, error; -+ -+ if (debug) { -+ dprintk("%s key:", __FUNCTION__); -+ for (i = 0; i < (crd->crd_klen + 7) / 8; i++) -+ dprintk("%s0x%x", (i % 8) ? " " : "\n ", -+ crd->crd_key[i] & 0xff); -+ dprintk("\n"); -+ } -+ /* OCF doesn't enforce keys */ -+ crypto_blkcipher_set_flags(crypto_blkcipher_cast(sw->sw_tfm), -+ CRYPTO_TFM_REQ_WEAK_KEY); -+ error = crypto_blkcipher_setkey( -+ crypto_blkcipher_cast(sw->sw_tfm), crd->crd_key, -+ (crd->crd_klen + 7) / 8); -+ if (error) { -+ dprintk("cryptosoft: setkey failed %d (crt_flags=0x%x)\n", -+ error, sw->sw_tfm->crt_flags); -+ crp->crp_etype = -error; -+ } -+ } -+ -+ memset(&desc, 0, sizeof(desc)); -+ desc.tfm = crypto_blkcipher_cast(sw->sw_tfm); -+ -+ if (crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ -+ -+ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { -+ ivp = crd->crd_iv; -+ } else { -+ get_random_bytes(ivp, ivsize); -+ } -+ /* -+ * do we have to copy the IV back to the buffer ? -+ */ -+ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, ivsize, (caddr_t)ivp); -+ } -+ desc.info = ivp; -+ crypto_blkcipher_encrypt_iv(&desc, req->sg, req->sg, sg_len); -+ -+ } else { /*decrypt */ -+ -+ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { -+ ivp = crd->crd_iv; -+ } else { -+ crypto_copydata(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, ivsize, (caddr_t)ivp); -+ } -+ desc.info = ivp; -+ crypto_blkcipher_decrypt_iv(&desc, req->sg, req->sg, sg_len); -+ } -+ } break; -+ -+ case SW_TYPE_HMAC: -+ case SW_TYPE_HASH: -+ { -+ char result[HASH_MAX_LEN]; -+ struct hash_desc desc; -+ -+ /* check we have room for the result */ -+ if (crp->crp_ilen - crd->crd_inject < sw->u.hmac.sw_mlen) { -+ dprintk("cryptosoft: EINVAL crp_ilen=%d, len=%d, inject=%d " -+ "digestsize=%d\n", crp->crp_ilen, crd->crd_skip + sg_len, -+ crd->crd_inject, sw->u.hmac.sw_mlen); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ memset(&desc, 0, sizeof(desc)); -+ desc.tfm = crypto_hash_cast(sw->sw_tfm); -+ -+ memset(result, 0, sizeof(result)); -+ -+ if (sw->sw_type & SW_TYPE_HMAC) { -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) -+ crypto_hmac(sw->sw_tfm, sw->u.hmac.sw_key, &sw->u.hmac.sw_klen, -+ req->sg, sg_num, result); -+#else -+ crypto_hash_setkey(desc.tfm, sw->u.hmac.sw_key, -+ sw->u.hmac.sw_klen); -+ crypto_hash_digest(&desc, req->sg, sg_len, result); -+#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) */ -+ -+ } else { /* SW_TYPE_HASH */ -+ crypto_hash_digest(&desc, req->sg, sg_len, result); -+ } -+ -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, sw->u.hmac.sw_mlen, result); -+ } -+ break; -+ -+ case SW_TYPE_COMP: { -+ void *ibuf = NULL; -+ void *obuf = sw->u.sw_comp_buf; -+ int ilen = sg_len, olen = CRYPTO_MAX_DATA_LEN; -+ int ret = 0; -+ -+ /* -+ * we need to use an additional copy if there is more than one -+ * input chunk since the kernel comp routines do not handle -+ * SG yet. Otherwise we just use the input buffer as is. -+ * Rather than allocate another buffer we just split the tmp -+ * buffer we already have. -+ * Perhaps we should just use zlib directly ? -+ */ -+ if (sg_num > 1) { -+ int blk; -+ -+ ibuf = obuf; -+ for (blk = 0; blk < sg_num; blk++) { -+ memcpy(obuf, sg_virt(&req->sg[blk]), -+ req->sg[blk].length); -+ obuf += req->sg[blk].length; -+ } -+ olen -= sg_len; -+ } else -+ ibuf = sg_virt(&req->sg[0]); -+ -+ if (crd->crd_flags & CRD_F_ENCRYPT) { /* compress */ -+ ret = crypto_comp_compress(crypto_comp_cast(sw->sw_tfm), -+ ibuf, ilen, obuf, &olen); -+ if (!ret && olen > crd->crd_len) { -+ dprintk("cryptosoft: ERANGE compress %d into %d\n", -+ crd->crd_len, olen); -+ if (swcr_fail_if_compression_grows) -+ ret = ERANGE; -+ } -+ } else { /* decompress */ -+ ret = crypto_comp_decompress(crypto_comp_cast(sw->sw_tfm), -+ ibuf, ilen, obuf, &olen); -+ if (!ret && (olen + crd->crd_inject) > crp->crp_olen) { -+ dprintk("cryptosoft: ETOOSMALL decompress %d into %d, " -+ "space for %d,at offset %d\n", -+ crd->crd_len, olen, crp->crp_olen, crd->crd_inject); -+ ret = ETOOSMALL; -+ } -+ } -+ if (ret) -+ dprintk("%s,%d: ret = %d\n", __FILE__, __LINE__, ret); -+ -+ /* -+ * on success copy result back, -+ * linux crpyto API returns -errno, we need to fix that -+ */ -+ crp->crp_etype = ret < 0 ? -ret : ret; -+ if (ret == 0) { -+ /* copy back the result and return it's size */ -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, olen, obuf); -+ crp->crp_olen = olen; -+ } -+ } break; -+ -+ default: -+ /* Unknown/unsupported algorithm */ -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+done: -+ swcr_process_req_complete(req); -+} -+ -+ -+/* -+ * Process a crypto request. -+ */ -+static int -+swcr_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ struct swcr_req *req = NULL; -+ u_int32_t lid; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ /* Sanity check */ -+ if (crp == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ crp->crp_etype = 0; -+ -+ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ lid = crp->crp_sid & 0xffffffff; -+ if (lid >= swcr_sesnum || lid == 0 || swcr_sessions == NULL || -+ swcr_sessions[lid] == NULL) { -+ crp->crp_etype = ENOENT; -+ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); -+ goto done; -+ } -+ -+ /* -+ * do some error checking outside of the loop for SKB and IOV processing -+ * this leaves us with valid skb or uiop pointers for later -+ */ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ struct sk_buff *skb = (struct sk_buff *) crp->crp_buf; -+ if (skb_shinfo(skb)->nr_frags >= SCATTERLIST_MAX) { -+ printk("%s,%d: %d nr_frags > SCATTERLIST_MAX", __FILE__, __LINE__, -+ skb_shinfo(skb)->nr_frags); -+ goto done; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ struct uio *uiop = (struct uio *) crp->crp_buf; -+ if (uiop->uio_iovcnt > SCATTERLIST_MAX) { -+ printk("%s,%d: %d uio_iovcnt > SCATTERLIST_MAX", __FILE__, __LINE__, -+ uiop->uio_iovcnt); -+ goto done; -+ } -+ } -+ -+ /* -+ * setup a new request ready for queuing -+ */ -+ req = kmem_cache_alloc(swcr_req_cache, SLAB_ATOMIC); -+ if (req == NULL) { -+ dprintk("%s,%d: ENOMEM\n", __FILE__, __LINE__); -+ crp->crp_etype = ENOMEM; -+ goto done; -+ } -+ memset(req, 0, sizeof(*req)); -+ -+ req->sw_head = swcr_sessions[lid]; -+ req->crp = crp; -+ req->crd = crp->crp_desc; -+ -+ swcr_process_req(req); -+ return 0; -+ -+done: -+ crypto_done(crp); -+ if (req) -+ kmem_cache_free(swcr_req_cache, req); -+ return 0; -+} -+ -+ -+static int -+cryptosoft_init(void) -+{ -+ int i, sw_type, mode; -+ char *algo; -+ -+ dprintk("%s(%p)\n", __FUNCTION__, cryptosoft_init); -+ -+ swcr_req_cache = kmem_cache_create("cryptosoft_req", -+ sizeof(struct swcr_req), 0, SLAB_HWCACHE_ALIGN, NULL -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) -+ , NULL -+#endif -+ ); -+ if (!swcr_req_cache) { -+ printk("cryptosoft: failed to create request cache\n"); -+ return -ENOENT; -+ } -+ -+ softc_device_init(&swcr_softc, "cryptosoft", 0, swcr_methods); -+ -+ swcr_id = crypto_get_driverid(softc_get_device(&swcr_softc), -+ CRYPTOCAP_F_SOFTWARE | CRYPTOCAP_F_SYNC); -+ if (swcr_id < 0) { -+ printk("cryptosoft: Software crypto device cannot initialize!"); -+ return -ENODEV; -+ } -+ -+#define REGISTER(alg) \ -+ crypto_register(swcr_id, alg, 0,0) -+ -+ for (i = 0; i < sizeof(crypto_details)/sizeof(crypto_details[0]); i++) { -+ int found; -+ -+ algo = crypto_details[i].alg_name; -+ if (!algo || !*algo) { -+ dprintk("%s:Algorithm %d not supported\n", __FUNCTION__, i); -+ continue; -+ } -+ -+ mode = crypto_details[i].mode; -+ sw_type = crypto_details[i].sw_type; -+ -+ found = 0; -+ switch (sw_type & SW_TYPE_ALG_MASK) { -+ case SW_TYPE_CIPHER: -+ found = crypto_has_cipher(algo, 0, CRYPTO_ALG_ASYNC); -+ break; -+ case SW_TYPE_HMAC: -+ found = crypto_has_hash(algo, 0, swcr_no_ahash?CRYPTO_ALG_ASYNC:0); -+ break; -+ case SW_TYPE_HASH: -+ found = crypto_has_hash(algo, 0, swcr_no_ahash?CRYPTO_ALG_ASYNC:0); -+ break; -+ case SW_TYPE_COMP: -+ found = crypto_has_comp(algo, 0, CRYPTO_ALG_ASYNC); -+ break; -+ case SW_TYPE_BLKCIPHER: -+ found = crypto_has_blkcipher(algo, 0, CRYPTO_ALG_ASYNC); -+ if (!found && !swcr_no_ablk) -+ found = crypto_has_ablkcipher(algo, 0, 0); -+ break; -+ } -+ if (found) { -+ REGISTER(i); -+ } else { -+ dprintk("%s:Algorithm Type %d not supported (algorithm %d:'%s')\n", -+ __FUNCTION__, sw_type, i, algo); -+ } -+ } -+ return 0; -+} -+ -+static void -+cryptosoft_exit(void) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ crypto_unregister_all(swcr_id); -+ swcr_id = -1; -+ kmem_cache_destroy(swcr_req_cache); -+} -+ -+late_initcall(cryptosoft_init); -+module_exit(cryptosoft_exit); -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("Cryptosoft (OCF module for kernel crypto)"); -diff -Nur linux-3.0.4.orig/crypto/ocf/ep80579/Makefile linux-3.0.4/crypto/ocf/ep80579/Makefile ---- linux-3.0.4.orig/crypto/ocf/ep80579/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/ep80579/Makefile 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,119 @@ -+######################################################################### -+# -+# Targets supported -+# all - builds everything and installs -+# install - identical to all -+# depend - build dependencies -+# clean - clears derived objects except the .depend files -+# distclean- clears all derived objects and the .depend file -+# -+# @par -+# This file is provided under a dual BSD/GPLv2 license. When using or -+# redistributing this file, you may do so under either license. -+# -+# GPL LICENSE SUMMARY -+# -+# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+# -+# This program is free software; you can redistribute it and/or modify -+# it under the terms of version 2 of the GNU General Public License as -+# published by the Free Software Foundation. -+# -+# This program is distributed in the hope that it will be useful, but -+# WITHOUT ANY WARRANTY; without even the implied warranty of -+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+# General Public License for more details. -+# -+# You should have received a copy of the GNU General Public License -+# along with this program; if not, write to the Free Software -+# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. -+# The full GNU General Public License is included in this distribution -+# in the file called LICENSE.GPL. -+# -+# Contact Information: -+# Intel Corporation -+# -+# BSD LICENSE -+# -+# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+# All rights reserved. -+# -+# Redistribution and use in source and binary forms, with or without -+# modification, are permitted provided that the following conditions -+# are met: -+# -+# * Redistributions of source code must retain the above copyright -+# notice, this list of conditions and the following disclaimer. -+# * Redistributions in binary form must reproduce the above copyright -+# notice, this list of conditions and the following disclaimer in -+# the documentation and/or other materials provided with the -+# distribution. -+# * Neither the name of Intel Corporation nor the names of its -+# contributors may be used to endorse or promote products derived -+# from this software without specific prior written permission. -+# -+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+# -+# -+# version: Security.L.1.0.2-229 -+############################################################################ -+ -+ -+####################Common variables and definitions######################## -+ -+ifndef ICP_ROOT -+$(warning ICP_ROOT is undefined. Please set the path to EP80579 release package directory \ -+ "-> setenv ICP_ROOT ") -+all fastdep: -+ : -+else -+ -+ifndef KERNEL_SOURCE_ROOT -+$(error KERNEL_SOURCE_ROOT is undefined. Please set the path to the kernel source directory \ -+ "-> setenv KERNEL_SOURCE_ROOT ") -+endif -+ -+# Ensure The ENV_DIR environmental var is defined. -+ifndef ICP_ENV_DIR -+$(error ICP_ENV_DIR is undefined. Please set the path to EP80579 driver environment.mk file \ -+ "-> setenv ICP_ENV_DIR ") -+endif -+ -+#Add your project environment Makefile -+include ${ICP_ENV_DIR}/environment.mk -+ -+#include the makefile with all the default and common Make variable definitions -+include ${ICP_BUILDSYSTEM_PATH}/build_files/common.mk -+ -+#Add the name for the executable, Library or Module output definitions -+OUTPUT_NAME= icp_ocf -+ -+# List of Source Files to be compiled -+SOURCES= icp_common.c icp_sym.c icp_asym.c icp_ocf_linux.c -+ -+#common includes between all supported OSes -+INCLUDES= -I ${ICP_API_DIR} -I${ICP_LAC_API} \ -+-I${ICP_OCF_SRC_DIR} -+ -+# The location of the os level makefile needs to be changed. -+include ${ICP_ENV_DIR}/${ICP_OS}_${ICP_OS_LEVEL}.mk -+ -+# On the line directly below list the outputs you wish to build for, -+# e.g "lib_static lib_shared exe module" as shown below -+install: module -+ -+###################Include rules makefiles######################## -+include ${ICP_BUILDSYSTEM_PATH}/build_files/rules.mk -+###################End of Rules inclusion######################### -+ -+endif -diff -Nur linux-3.0.4.orig/crypto/ocf/ep80579/environment.mk linux-3.0.4/crypto/ocf/ep80579/environment.mk ---- linux-3.0.4.orig/crypto/ocf/ep80579/environment.mk 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/ep80579/environment.mk 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,78 @@ -+ ########################################################################### -+ # -+# This file is provided under a dual BSD/GPLv2 license. When using or -+# redistributing this file, you may do so under either license. -+# -+# GPL LICENSE SUMMARY -+# -+# Copyright(c) 2007,2008 Intel Corporation. All rights reserved. -+# -+# This program is free software; you can redistribute it and/or modify -+# it under the terms of version 2 of the GNU General Public License as -+# published by the Free Software Foundation. -+# -+# This program is distributed in the hope that it will be useful, but -+# WITHOUT ANY WARRANTY; without even the implied warranty of -+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+# General Public License for more details. -+# -+# You should have received a copy of the GNU General Public License -+# along with this program; if not, write to the Free Software -+# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. -+# The full GNU General Public License is included in this distribution -+# in the file called LICENSE.GPL. -+# -+# Contact Information: -+# Intel Corporation -+# -+# BSD LICENSE -+# -+# Copyright(c) 2007,2008 Intel Corporation. All rights reserved. -+# All rights reserved. -+# -+# Redistribution and use in source and binary forms, with or without -+# modification, are permitted provided that the following conditions -+# are met: -+# -+# * Redistributions of source code must retain the above copyright -+# notice, this list of conditions and the following disclaimer. -+# * Redistributions in binary form must reproduce the above copyright -+# notice, this list of conditions and the following disclaimer in -+# the documentation and/or other materials provided with the -+# distribution. -+# * Neither the name of Intel Corporation nor the names of its -+# contributors may be used to endorse or promote products derived -+# from this software without specific prior written permission. -+# -+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+# -+# -+# version: Security.L.1.0.130 -+ # -+ ########################################################################### -+ -+ -+ICP_LAC_API=$(ICP_ROOT)/Acceleration/include/lac -+ICP_BTR_API=$(ICP_ROOT)/Acceleration/include/btr -+ICP_API_DIR=$(ICP_ROOT)/Acceleration/include -+ICP_OCF_SHIM_DIR?=$(KERNEL_SOURCE_ROOT)/crypto/ocf/ -+ifeq ($(wildcard $(ICP_OCF_SHIM_DIR)),) -+ICP_OCF_SHIM_DIR?=$(ROOTDIR)/modules/ocf/ -+endif -+ -+ICP_OS_LEVEL?=kernel_space -+ -+ICP_OS?=linux_2.6 -+ -+ICP_CORE?=ia -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/ep80579/icp_asym.c linux-3.0.4/crypto/ocf/ep80579/icp_asym.c ---- linux-3.0.4.orig/crypto/ocf/ep80579/icp_asym.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/ep80579/icp_asym.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,1334 @@ -+/*************************************************************************** -+ * -+ * This file is provided under a dual BSD/GPLv2 license. When using or -+ * redistributing this file, you may do so under either license. -+ * -+ * GPL LICENSE SUMMARY -+ * -+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of version 2 of the GNU General Public License as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. -+ * The full GNU General Public License is included in this distribution -+ * in the file called LICENSE.GPL. -+ * -+ * Contact Information: -+ * Intel Corporation -+ * -+ * BSD LICENSE -+ * -+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * * Neither the name of Intel Corporation nor the names of its -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * -+ * version: Security.L.1.0.2-229 -+ * -+ ***************************************************************************/ -+ -+#include "icp_ocf.h" -+ -+/*The following define values (containing the word 'INDEX') are used to find -+the index of each input buffer of the crypto_kop struct (see OCF cryptodev.h). -+These values were found through analysis of the OCF OpenSSL patch. If the -+calling program uses different input buffer positions, these defines will have -+to be changed.*/ -+ -+/*DIFFIE HELLMAN buffer index values*/ -+#define ICP_DH_KRP_PARAM_PRIME_INDEX (0) -+#define ICP_DH_KRP_PARAM_BASE_INDEX (1) -+#define ICP_DH_KRP_PARAM_PRIVATE_VALUE_INDEX (2) -+#define ICP_DH_KRP_PARAM_RESULT_INDEX (3) -+ -+/*MOD EXP buffer index values*/ -+#define ICP_MOD_EXP_KRP_PARAM_BASE_INDEX (0) -+#define ICP_MOD_EXP_KRP_PARAM_EXPONENT_INDEX (1) -+#define ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX (2) -+#define ICP_MOD_EXP_KRP_PARAM_RESULT_INDEX (3) -+ -+/*MOD EXP CRT buffer index values*/ -+#define ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_P_INDEX (0) -+#define ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_Q_INDEX (1) -+#define ICP_MOD_EXP_CRT_KRP_PARAM_I_INDEX (2) -+#define ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DP_INDEX (3) -+#define ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DQ_INDEX (4) -+#define ICP_MOD_EXP_CRT_KRP_PARAM_COEFF_QINV_INDEX (5) -+#define ICP_MOD_EXP_CRT_KRP_PARAM_RESULT_INDEX (6) -+ -+/*DSA sign buffer index values*/ -+#define ICP_DSA_SIGN_KRP_PARAM_DGST_INDEX (0) -+#define ICP_DSA_SIGN_KRP_PARAM_PRIME_P_INDEX (1) -+#define ICP_DSA_SIGN_KRP_PARAM_PRIME_Q_INDEX (2) -+#define ICP_DSA_SIGN_KRP_PARAM_G_INDEX (3) -+#define ICP_DSA_SIGN_KRP_PARAM_X_INDEX (4) -+#define ICP_DSA_SIGN_KRP_PARAM_R_RESULT_INDEX (5) -+#define ICP_DSA_SIGN_KRP_PARAM_S_RESULT_INDEX (6) -+ -+/*DSA verify buffer index values*/ -+#define ICP_DSA_VERIFY_KRP_PARAM_DGST_INDEX (0) -+#define ICP_DSA_VERIFY_KRP_PARAM_PRIME_P_INDEX (1) -+#define ICP_DSA_VERIFY_KRP_PARAM_PRIME_Q_INDEX (2) -+#define ICP_DSA_VERIFY_KRP_PARAM_G_INDEX (3) -+#define ICP_DSA_VERIFY_KRP_PARAM_PUBKEY_INDEX (4) -+#define ICP_DSA_VERIFY_KRP_PARAM_SIG_R_INDEX (5) -+#define ICP_DSA_VERIFY_KRP_PARAM_SIG_S_INDEX (6) -+ -+/*DSA sign prime Q vs random number K size check values*/ -+#define DONT_RUN_LESS_THAN_CHECK (0) -+#define FAIL_A_IS_GREATER_THAN_B (1) -+#define FAIL_A_IS_EQUAL_TO_B (1) -+#define SUCCESS_A_IS_LESS_THAN_B (0) -+#define DSA_SIGN_RAND_GEN_VAL_CHECK_MAX_ITERATIONS (500) -+ -+/* We need to set a cryptokp success value just in case it is set or allocated -+ and not set to zero outside of this module */ -+#define CRYPTO_OP_SUCCESS (0) -+ -+/*Function to compute Diffie Hellman (DH) phase 1 or phase 2 key values*/ -+static int icp_ocfDrvDHComputeKey(struct cryptkop *krp); -+ -+/*Function to compute a Modular Exponentiation (Mod Exp)*/ -+static int icp_ocfDrvModExp(struct cryptkop *krp); -+ -+/*Function to compute a Mod Exp using the Chinease Remainder Theorem*/ -+static int icp_ocfDrvModExpCRT(struct cryptkop *krp); -+ -+/*Helper function to compute whether the first big number argument is less than -+ the second big number argument */ -+static int -+icp_ocfDrvCheckALessThanB(CpaFlatBuffer * pK, CpaFlatBuffer * pQ, int *doCheck); -+ -+/*Function to sign an input with DSA R and S keys*/ -+static int icp_ocfDrvDsaSign(struct cryptkop *krp); -+ -+/*Function to Verify a DSA buffer signature*/ -+static int icp_ocfDrvDsaVerify(struct cryptkop *krp); -+ -+/*Callback function for DH operation*/ -+static void -+icp_ocfDrvDhP1CallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, CpaFlatBuffer * pLocalOctetStringPV); -+ -+/*Callback function for ME operation*/ -+static void -+icp_ocfDrvModExpCallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, CpaFlatBuffer * pResult); -+ -+/*Callback function for ME CRT operation*/ -+static void -+icp_ocfDrvModExpCRTCallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, CpaFlatBuffer * pOutputData); -+ -+/*Callback function for DSA sign operation*/ -+static void -+icp_ocfDrvDsaRSSignCallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, -+ CpaBoolean protocolStatus, -+ CpaFlatBuffer * pR, CpaFlatBuffer * pS); -+ -+/*Callback function for DSA Verify operation*/ -+static void -+icp_ocfDrvDsaVerifyCallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, CpaBoolean verifyStatus); -+ -+/* Name : icp_ocfDrvPkeProcess -+ * -+ * Description : This function will choose which PKE process to follow -+ * based on the input arguments -+ */ -+int icp_ocfDrvPkeProcess(icp_device_t dev, struct cryptkop *krp, int hint) -+{ -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ -+ if (NULL == krp) { -+ DPRINTK("%s(): Invalid input parameters, cryptkop = %p\n", -+ __FUNCTION__, krp); -+ return EINVAL; -+ } -+ -+ if (CPA_TRUE == icp_atomic_read(&icp_ocfDrvIsExiting)) { -+ krp->krp_status = ECANCELED; -+ return ECANCELED; -+ } -+ -+ switch (krp->krp_op) { -+ case CRK_DH_COMPUTE_KEY: -+ DPRINTK("%s() doing DH_COMPUTE_KEY\n", __FUNCTION__); -+ lacStatus = icp_ocfDrvDHComputeKey(krp); -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): icp_ocfDrvDHComputeKey failed " -+ "(%d).\n", __FUNCTION__, lacStatus); -+ krp->krp_status = ECANCELED; -+ return ECANCELED; -+ } -+ -+ break; -+ -+ case CRK_MOD_EXP: -+ DPRINTK("%s() doing MOD_EXP \n", __FUNCTION__); -+ lacStatus = icp_ocfDrvModExp(krp); -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): icp_ocfDrvModExp failed (%d).\n", -+ __FUNCTION__, lacStatus); -+ krp->krp_status = ECANCELED; -+ return ECANCELED; -+ } -+ -+ break; -+ -+ case CRK_MOD_EXP_CRT: -+ DPRINTK("%s() doing MOD_EXP_CRT \n", __FUNCTION__); -+ lacStatus = icp_ocfDrvModExpCRT(krp); -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): icp_ocfDrvModExpCRT " -+ "failed (%d).\n", __FUNCTION__, lacStatus); -+ krp->krp_status = ECANCELED; -+ return ECANCELED; -+ } -+ -+ break; -+ -+ case CRK_DSA_SIGN: -+ DPRINTK("%s() doing DSA_SIGN \n", __FUNCTION__); -+ lacStatus = icp_ocfDrvDsaSign(krp); -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): icp_ocfDrvDsaSign " -+ "failed (%d).\n", __FUNCTION__, lacStatus); -+ krp->krp_status = ECANCELED; -+ return ECANCELED; -+ } -+ -+ break; -+ -+ case CRK_DSA_VERIFY: -+ DPRINTK("%s() doing DSA_VERIFY \n", __FUNCTION__); -+ lacStatus = icp_ocfDrvDsaVerify(krp); -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): icp_ocfDrvDsaVerify " -+ "failed (%d).\n", __FUNCTION__, lacStatus); -+ krp->krp_status = ECANCELED; -+ return ECANCELED; -+ } -+ -+ break; -+ -+ default: -+ EPRINTK("%s(): Asymettric function not " -+ "supported (%d).\n", __FUNCTION__, krp->krp_op); -+ krp->krp_status = EOPNOTSUPP; -+ return EOPNOTSUPP; -+ } -+ -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+} -+ -+/* Name : icp_ocfDrvSwapBytes -+ * -+ * Description : This function is used to swap the byte order of a buffer. -+ * It has been seen that in general we are passed little endian byte order -+ * buffers, but LAC only accepts big endian byte order buffers. -+ */ -+static void inline icp_ocfDrvSwapBytes(u_int8_t * num, u_int32_t buff_len_bytes) -+{ -+ -+ int i; -+ u_int8_t *end_ptr; -+ u_int8_t hold_val; -+ -+ end_ptr = num + (buff_len_bytes - 1); -+ buff_len_bytes = buff_len_bytes >> 1; -+ for (i = 0; i < buff_len_bytes; i++) { -+ hold_val = *num; -+ *num = *end_ptr; -+ num++; -+ *end_ptr = hold_val; -+ end_ptr--; -+ } -+} -+ -+/* Name : icp_ocfDrvDHComputeKey -+ * -+ * Description : This function will map Diffie Hellman calls from OCF -+ * to the LAC API. OCF uses this function for Diffie Hellman Phase1 and -+ * Phase2. LAC has a separate Diffie Hellman Phase2 call, however both phases -+ * break down to a modular exponentiation. -+ */ -+static int icp_ocfDrvDHComputeKey(struct cryptkop *krp) -+{ -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ void *callbackTag = NULL; -+ CpaCyDhPhase1KeyGenOpData *pPhase1OpData = NULL; -+ CpaFlatBuffer *pLocalOctetStringPV = NULL; -+ uint32_t dh_prime_len_bytes = 0, dh_prime_len_bits = 0; -+ -+ /* Input checks - check prime is a multiple of 8 bits to allow for -+ allocation later */ -+ dh_prime_len_bits = -+ (krp->krp_param[ICP_DH_KRP_PARAM_PRIME_INDEX].crp_nbits); -+ -+ /* LAC can reject prime lengths based on prime key sizes, we just -+ need to make sure we can allocate space for the base and -+ exponent buffers correctly */ -+ if ((dh_prime_len_bits % NUM_BITS_IN_BYTE) != 0) { -+ APRINTK("%s(): Warning Prime number buffer size is not a " -+ "multiple of 8 bits\n", __FUNCTION__); -+ } -+ -+ /* Result storage space should be the same size as the prime as this -+ value can take up the same amount of storage space */ -+ if (dh_prime_len_bits != -+ krp->krp_param[ICP_DH_KRP_PARAM_RESULT_INDEX].crp_nbits) { -+ DPRINTK("%s(): Return Buffer must be the same size " -+ "as the Prime buffer\n", __FUNCTION__); -+ krp->krp_status = EINVAL; -+ return EINVAL; -+ } -+ /* Switch to size in bytes */ -+ BITS_TO_BYTES(dh_prime_len_bytes, dh_prime_len_bits); -+ -+ callbackTag = krp; -+ -+/*All allocations are set to ICP_M_NOWAIT due to the possibility of getting -+called in interrupt context*/ -+ pPhase1OpData = icp_kmem_cache_zalloc(drvDH_zone, ICP_M_NOWAIT); -+ if (NULL == pPhase1OpData) { -+ APRINTK("%s():Failed to get memory for key gen data\n", -+ __FUNCTION__); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ pLocalOctetStringPV = -+ icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); -+ if (NULL == pLocalOctetStringPV) { -+ APRINTK("%s():Failed to get memory for pLocalOctetStringPV\n", -+ __FUNCTION__); -+ ICP_CACHE_FREE(drvDH_zone, pPhase1OpData); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ /* Link parameters */ -+ pPhase1OpData->primeP.pData = -+ krp->krp_param[ICP_DH_KRP_PARAM_PRIME_INDEX].crp_p; -+ -+ pPhase1OpData->primeP.dataLenInBytes = dh_prime_len_bytes; -+ -+ icp_ocfDrvSwapBytes(pPhase1OpData->primeP.pData, dh_prime_len_bytes); -+ -+ pPhase1OpData->baseG.pData = -+ krp->krp_param[ICP_DH_KRP_PARAM_BASE_INDEX].crp_p; -+ -+ BITS_TO_BYTES(pPhase1OpData->baseG.dataLenInBytes, -+ krp->krp_param[ICP_DH_KRP_PARAM_BASE_INDEX].crp_nbits); -+ -+ icp_ocfDrvSwapBytes(pPhase1OpData->baseG.pData, -+ pPhase1OpData->baseG.dataLenInBytes); -+ -+ pPhase1OpData->privateValueX.pData = -+ krp->krp_param[ICP_DH_KRP_PARAM_PRIVATE_VALUE_INDEX].crp_p; -+ -+ BITS_TO_BYTES(pPhase1OpData->privateValueX.dataLenInBytes, -+ krp->krp_param[ICP_DH_KRP_PARAM_PRIVATE_VALUE_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(pPhase1OpData->privateValueX.pData, -+ pPhase1OpData->privateValueX.dataLenInBytes); -+ -+ /* Output parameters */ -+ pLocalOctetStringPV->pData = -+ krp->krp_param[ICP_DH_KRP_PARAM_RESULT_INDEX].crp_p; -+ -+ BITS_TO_BYTES(pLocalOctetStringPV->dataLenInBytes, -+ krp->krp_param[ICP_DH_KRP_PARAM_RESULT_INDEX].crp_nbits); -+ -+ lacStatus = cpaCyDhKeyGenPhase1(CPA_INSTANCE_HANDLE_SINGLE, -+ icp_ocfDrvDhP1CallBack, -+ callbackTag, pPhase1OpData, -+ pLocalOctetStringPV); -+ -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): DH Phase 1 Key Gen failed (%d).\n", -+ __FUNCTION__, lacStatus); -+ icp_ocfDrvFreeFlatBuffer(pLocalOctetStringPV); -+ ICP_CACHE_FREE(drvDH_zone, pPhase1OpData); -+ } -+ -+ return lacStatus; -+} -+ -+/* Name : icp_ocfDrvModExp -+ * -+ * Description : This function will map ordinary Modular Exponentiation calls -+ * from OCF to the LAC API. -+ * -+ */ -+static int icp_ocfDrvModExp(struct cryptkop *krp) -+{ -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ void *callbackTag = NULL; -+ CpaCyLnModExpOpData *pModExpOpData = NULL; -+ CpaFlatBuffer *pResult = NULL; -+ -+ if ((krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX].crp_nbits % -+ NUM_BITS_IN_BYTE) != 0) { -+ DPRINTK("%s(): Warning - modulus buffer size (%d) is not a " -+ "multiple of 8 bits\n", __FUNCTION__, -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX]. -+ crp_nbits); -+ } -+ -+ /* Result storage space should be the same size as the prime as this -+ value can take up the same amount of storage space */ -+ if (krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX].crp_nbits > -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_RESULT_INDEX].crp_nbits) { -+ APRINTK("%s(): Return Buffer size must be the same or" -+ " greater than the Modulus buffer\n", __FUNCTION__); -+ krp->krp_status = EINVAL; -+ return EINVAL; -+ } -+ -+ callbackTag = krp; -+ -+ pModExpOpData = icp_kmem_cache_zalloc(drvLnModExp_zone, ICP_M_NOWAIT); -+ if (NULL == pModExpOpData) { -+ APRINTK("%s():Failed to get memory for key gen data\n", -+ __FUNCTION__); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ pResult = icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); -+ if (NULL == pResult) { -+ APRINTK("%s():Failed to get memory for ModExp result\n", -+ __FUNCTION__); -+ ICP_CACHE_FREE(drvLnModExp_zone, pModExpOpData); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ /* Link parameters */ -+ pModExpOpData->modulus.pData = -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX].crp_p; -+ BITS_TO_BYTES(pModExpOpData->modulus.dataLenInBytes, -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(pModExpOpData->modulus.pData, -+ pModExpOpData->modulus.dataLenInBytes); -+ -+ DPRINTK("%s : base (%d)\n", __FUNCTION__, krp-> -+ krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX].crp_nbits); -+ pModExpOpData->base.pData = -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX].crp_p; -+ BITS_TO_BYTES(pModExpOpData->base.dataLenInBytes, -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX]. -+ crp_nbits); -+ icp_ocfDrvSwapBytes(pModExpOpData->base.pData, -+ pModExpOpData->base.dataLenInBytes); -+ -+ pModExpOpData->exponent.pData = -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_EXPONENT_INDEX].crp_p; -+ BITS_TO_BYTES(pModExpOpData->exponent.dataLenInBytes, -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_EXPONENT_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(pModExpOpData->exponent.pData, -+ pModExpOpData->exponent.dataLenInBytes); -+ /* Output parameters */ -+ pResult->pData = -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_RESULT_INDEX].crp_p, -+ BITS_TO_BYTES(pResult->dataLenInBytes, -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_RESULT_INDEX]. -+ crp_nbits); -+ -+ lacStatus = cpaCyLnModExp(CPA_INSTANCE_HANDLE_SINGLE, -+ icp_ocfDrvModExpCallBack, -+ callbackTag, pModExpOpData, pResult); -+ -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): Mod Exp Operation failed (%d).\n", -+ __FUNCTION__, lacStatus); -+ krp->krp_status = ECANCELED; -+ icp_ocfDrvFreeFlatBuffer(pResult); -+ ICP_CACHE_FREE(drvLnModExp_zone, pModExpOpData); -+ } -+ -+ return lacStatus; -+} -+ -+/* Name : icp_ocfDrvModExpCRT -+ * -+ * Description : This function will map ordinary Modular Exponentiation Chinese -+ * Remainder Theorem implementaion calls from OCF to the LAC API. -+ * -+ * Note : Mod Exp CRT for this driver is accelerated through LAC RSA type 2 -+ * decrypt operation. Therefore P and Q input values must always be prime -+ * numbers. Although basic primality checks are done in LAC, it is up to the -+ * user to do any correct prime number checking before passing the inputs. -+ */ -+static int icp_ocfDrvModExpCRT(struct cryptkop *krp) -+{ -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ CpaCyRsaDecryptOpData *rsaDecryptOpData = NULL; -+ void *callbackTag = NULL; -+ CpaFlatBuffer *pOutputData = NULL; -+ -+ /*Parameter input checks are all done by LAC, no need to repeat -+ them here. */ -+ callbackTag = krp; -+ -+ rsaDecryptOpData = -+ icp_kmem_cache_zalloc(drvRSADecrypt_zone, ICP_M_NOWAIT); -+ if (NULL == rsaDecryptOpData) { -+ APRINTK("%s():Failed to get memory" -+ " for MOD EXP CRT Op data struct\n", __FUNCTION__); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ rsaDecryptOpData->pRecipientPrivateKey -+ = icp_kmem_cache_zalloc(drvRSAPrivateKey_zone, ICP_M_NOWAIT); -+ if (NULL == rsaDecryptOpData->pRecipientPrivateKey) { -+ APRINTK("%s():Failed to get memory for MOD EXP CRT" -+ " private key values struct\n", __FUNCTION__); -+ ICP_CACHE_FREE(drvRSADecrypt_zone, rsaDecryptOpData); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ version = CPA_CY_RSA_VERSION_TWO_PRIME; -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRepType = CPA_CY_RSA_PRIVATE_KEY_REP_TYPE_2; -+ -+ pOutputData = icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); -+ if (NULL == pOutputData) { -+ APRINTK("%s():Failed to get memory" -+ " for MOD EXP CRT output data\n", __FUNCTION__); -+ ICP_CACHE_FREE(drvRSAPrivateKey_zone, -+ rsaDecryptOpData->pRecipientPrivateKey); -+ ICP_CACHE_FREE(drvRSADecrypt_zone, rsaDecryptOpData); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ version = CPA_CY_RSA_VERSION_TWO_PRIME; -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRepType = CPA_CY_RSA_PRIVATE_KEY_REP_TYPE_2; -+ -+ /* Link parameters */ -+ rsaDecryptOpData->inputData.pData = -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_I_INDEX].crp_p; -+ BITS_TO_BYTES(rsaDecryptOpData->inputData.dataLenInBytes, -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_I_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(rsaDecryptOpData->inputData.pData, -+ rsaDecryptOpData->inputData.dataLenInBytes); -+ -+ rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2.prime1P.pData = -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_P_INDEX].crp_p; -+ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2. -+ prime1P.dataLenInBytes, -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_P_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.prime1P.pData, -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.prime1P.dataLenInBytes); -+ -+ rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2.prime2Q.pData = -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_Q_INDEX].crp_p; -+ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2. -+ prime2Q.dataLenInBytes, -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_Q_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.prime2Q.pData, -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.prime2Q.dataLenInBytes); -+ -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.exponent1Dp.pData = -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DP_INDEX].crp_p; -+ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2. -+ exponent1Dp.dataLenInBytes, -+ krp-> -+ krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DP_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.exponent1Dp.pData, -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.exponent1Dp.dataLenInBytes); -+ -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.exponent2Dq.pData = -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DQ_INDEX].crp_p; -+ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.exponent2Dq.dataLenInBytes, -+ krp-> -+ krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DQ_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.exponent2Dq.pData, -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.exponent2Dq.dataLenInBytes); -+ -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.coefficientQInv.pData = -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_COEFF_QINV_INDEX].crp_p; -+ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.coefficientQInv.dataLenInBytes, -+ krp-> -+ krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_COEFF_QINV_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.coefficientQInv.pData, -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.coefficientQInv.dataLenInBytes); -+ -+ /* Output Parameter */ -+ pOutputData->pData = -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_RESULT_INDEX].crp_p; -+ BITS_TO_BYTES(pOutputData->dataLenInBytes, -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_RESULT_INDEX]. -+ crp_nbits); -+ -+ lacStatus = cpaCyRsaDecrypt(CPA_INSTANCE_HANDLE_SINGLE, -+ icp_ocfDrvModExpCRTCallBack, -+ callbackTag, rsaDecryptOpData, pOutputData); -+ -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): Mod Exp CRT Operation failed (%d).\n", -+ __FUNCTION__, lacStatus); -+ krp->krp_status = ECANCELED; -+ icp_ocfDrvFreeFlatBuffer(pOutputData); -+ ICP_CACHE_FREE(drvRSAPrivateKey_zone, -+ rsaDecryptOpData->pRecipientPrivateKey); -+ ICP_CACHE_FREE(drvRSADecrypt_zone, rsaDecryptOpData); -+ } -+ -+ return lacStatus; -+} -+ -+/* Name : icp_ocfDrvCheckALessThanB -+ * -+ * Description : This function will check whether the first argument is less -+ * than the second. It is used to check whether the DSA RS sign Random K -+ * value is less than the Prime Q value (as defined in the specification) -+ * -+ */ -+static int -+icp_ocfDrvCheckALessThanB(CpaFlatBuffer * pK, CpaFlatBuffer * pQ, int *doCheck) -+{ -+ -+ uint8_t *MSB_K = pK->pData; -+ uint8_t *MSB_Q = pQ->pData; -+ uint32_t buffer_lengths_in_bytes = pQ->dataLenInBytes; -+ -+ if (DONT_RUN_LESS_THAN_CHECK == *doCheck) { -+ return FAIL_A_IS_GREATER_THAN_B; -+ } -+ -+/*Check MSBs -+if A == B, check next MSB -+if A > B, return A_IS_GREATER_THAN_B -+if A < B, return A_IS_LESS_THAN_B (success) -+*/ -+ while (*MSB_K == *MSB_Q) { -+ MSB_K++; -+ MSB_Q++; -+ -+ buffer_lengths_in_bytes--; -+ if (0 == buffer_lengths_in_bytes) { -+ DPRINTK("%s() Buffers have equal value!!\n", -+ __FUNCTION__); -+ return FAIL_A_IS_EQUAL_TO_B; -+ } -+ -+ } -+ -+ if (*MSB_K < *MSB_Q) { -+ return SUCCESS_A_IS_LESS_THAN_B; -+ } else { -+ return FAIL_A_IS_GREATER_THAN_B; -+ } -+ -+} -+ -+/* Name : icp_ocfDrvDsaSign -+ * -+ * Description : This function will map DSA RS Sign from OCF to the LAC API. -+ * -+ * NOTE: From looking at OCF patch to OpenSSL and even the number of input -+ * parameters, OCF expects us to generate the random seed value. This value -+ * is generated and passed to LAC, however the number is discared in the -+ * callback and not returned to the user. -+ */ -+static int icp_ocfDrvDsaSign(struct cryptkop *krp) -+{ -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ CpaCyDsaRSSignOpData *dsaRsSignOpData = NULL; -+ void *callbackTag = NULL; -+ CpaCyRandGenOpData randGenOpData; -+ int primeQSizeInBytes = 0; -+ int doCheck = 0; -+ CpaFlatBuffer randData; -+ CpaBoolean protocolStatus = CPA_FALSE; -+ CpaFlatBuffer *pR = NULL; -+ CpaFlatBuffer *pS = NULL; -+ -+ callbackTag = krp; -+ -+ BITS_TO_BYTES(primeQSizeInBytes, -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_Q_INDEX]. -+ crp_nbits); -+ -+ if (DSA_RS_SIGN_PRIMEQ_SIZE_IN_BYTES != primeQSizeInBytes) { -+ APRINTK("%s(): DSA PRIME Q size not equal to the " -+ "FIPS defined 20bytes, = %d\n", -+ __FUNCTION__, primeQSizeInBytes); -+ krp->krp_status = EDOM; -+ return EDOM; -+ } -+ -+ dsaRsSignOpData = -+ icp_kmem_cache_zalloc(drvDSARSSign_zone, ICP_M_NOWAIT); -+ if (NULL == dsaRsSignOpData) { -+ APRINTK("%s():Failed to get memory" -+ " for DSA RS Sign Op data struct\n", __FUNCTION__); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ dsaRsSignOpData->K.pData = -+ icp_kmem_cache_alloc(drvDSARSSignKValue_zone, ICP_M_NOWAIT); -+ -+ if (NULL == dsaRsSignOpData->K.pData) { -+ APRINTK("%s():Failed to get memory" -+ " for DSA RS Sign Op Random value\n", __FUNCTION__); -+ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ pR = icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); -+ if (NULL == pR) { -+ APRINTK("%s():Failed to get memory" -+ " for DSA signature R\n", __FUNCTION__); -+ ICP_CACHE_FREE(drvDSARSSignKValue_zone, -+ dsaRsSignOpData->K.pData); -+ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ pS = icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); -+ if (NULL == pS) { -+ APRINTK("%s():Failed to get memory" -+ " for DSA signature S\n", __FUNCTION__); -+ icp_ocfDrvFreeFlatBuffer(pR); -+ ICP_CACHE_FREE(drvDSARSSignKValue_zone, -+ dsaRsSignOpData->K.pData); -+ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ /*link prime number parameter for ease of processing */ -+ dsaRsSignOpData->P.pData = -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_P_INDEX].crp_p; -+ BITS_TO_BYTES(dsaRsSignOpData->P.dataLenInBytes, -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_P_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(dsaRsSignOpData->P.pData, -+ dsaRsSignOpData->P.dataLenInBytes); -+ -+ dsaRsSignOpData->Q.pData = -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_Q_INDEX].crp_p; -+ BITS_TO_BYTES(dsaRsSignOpData->Q.dataLenInBytes, -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_Q_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(dsaRsSignOpData->Q.pData, -+ dsaRsSignOpData->Q.dataLenInBytes); -+ -+ /*generate random number with equal buffer size to Prime value Q, -+ but value less than Q */ -+ dsaRsSignOpData->K.dataLenInBytes = dsaRsSignOpData->Q.dataLenInBytes; -+ -+ randGenOpData.generateBits = CPA_TRUE; -+ randGenOpData.lenInBytes = dsaRsSignOpData->K.dataLenInBytes; -+ -+ icp_ocfDrvPtrAndLenToFlatBuffer(dsaRsSignOpData->K.pData, -+ dsaRsSignOpData->K.dataLenInBytes, -+ &randData); -+ -+ doCheck = 0; -+ while (icp_ocfDrvCheckALessThanB(&(dsaRsSignOpData->K), -+ &(dsaRsSignOpData->Q), &doCheck)) { -+ -+ if (CPA_STATUS_SUCCESS -+ != cpaCyRandGen(CPA_INSTANCE_HANDLE_SINGLE, -+ NULL, NULL, &randGenOpData, &randData)) { -+ APRINTK("%s(): ERROR - Failed to generate DSA RS Sign K" -+ "value\n", __FUNCTION__); -+ icp_ocfDrvFreeFlatBuffer(pS); -+ icp_ocfDrvFreeFlatBuffer(pR); -+ ICP_CACHE_FREE(drvDSARSSignKValue_zone, -+ dsaRsSignOpData->K.pData); -+ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); -+ krp->krp_status = EAGAIN; -+ return EAGAIN; -+ } -+ -+ doCheck++; -+ if (DSA_SIGN_RAND_GEN_VAL_CHECK_MAX_ITERATIONS == doCheck) { -+ APRINTK("%s(): ERROR - Failed to find DSA RS Sign K " -+ "value less than Q value\n", __FUNCTION__); -+ icp_ocfDrvFreeFlatBuffer(pS); -+ icp_ocfDrvFreeFlatBuffer(pR); -+ ICP_CACHE_FREE(drvDSARSSignKValue_zone, -+ dsaRsSignOpData->K.pData); -+ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); -+ krp->krp_status = EAGAIN; -+ return EAGAIN; -+ } -+ -+ } -+ /*Rand Data - no need to swap bytes for pK */ -+ -+ /* Link parameters */ -+ dsaRsSignOpData->G.pData = -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_G_INDEX].crp_p; -+ BITS_TO_BYTES(dsaRsSignOpData->G.dataLenInBytes, -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_G_INDEX].crp_nbits); -+ -+ icp_ocfDrvSwapBytes(dsaRsSignOpData->G.pData, -+ dsaRsSignOpData->G.dataLenInBytes); -+ -+ dsaRsSignOpData->X.pData = -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_X_INDEX].crp_p; -+ BITS_TO_BYTES(dsaRsSignOpData->X.dataLenInBytes, -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_X_INDEX].crp_nbits); -+ icp_ocfDrvSwapBytes(dsaRsSignOpData->X.pData, -+ dsaRsSignOpData->X.dataLenInBytes); -+ -+ /*OpenSSL dgst parameter is left in big endian byte order, -+ therefore no byte swap is required */ -+ dsaRsSignOpData->M.pData = -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_DGST_INDEX].crp_p; -+ BITS_TO_BYTES(dsaRsSignOpData->M.dataLenInBytes, -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_DGST_INDEX]. -+ crp_nbits); -+ -+ /* Output Parameters */ -+ pS->pData = krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_S_RESULT_INDEX].crp_p; -+ BITS_TO_BYTES(pS->dataLenInBytes, -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_S_RESULT_INDEX]. -+ crp_nbits); -+ -+ pR->pData = krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_R_RESULT_INDEX].crp_p; -+ BITS_TO_BYTES(pR->dataLenInBytes, -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_R_RESULT_INDEX]. -+ crp_nbits); -+ -+ lacStatus = cpaCyDsaSignRS(CPA_INSTANCE_HANDLE_SINGLE, -+ icp_ocfDrvDsaRSSignCallBack, -+ callbackTag, dsaRsSignOpData, -+ &protocolStatus, pR, pS); -+ -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): DSA RS Sign Operation failed (%d).\n", -+ __FUNCTION__, lacStatus); -+ krp->krp_status = ECANCELED; -+ icp_ocfDrvFreeFlatBuffer(pS); -+ icp_ocfDrvFreeFlatBuffer(pR); -+ ICP_CACHE_FREE(drvDSARSSignKValue_zone, -+ dsaRsSignOpData->K.pData); -+ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); -+ } -+ -+ return lacStatus; -+} -+ -+/* Name : icp_ocfDrvDsaVerify -+ * -+ * Description : This function will map DSA RS Verify from OCF to the LAC API. -+ * -+ */ -+static int icp_ocfDrvDsaVerify(struct cryptkop *krp) -+{ -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ CpaCyDsaVerifyOpData *dsaVerifyOpData = NULL; -+ void *callbackTag = NULL; -+ CpaBoolean verifyStatus = CPA_FALSE; -+ -+ callbackTag = krp; -+ -+ dsaVerifyOpData = -+ icp_kmem_cache_zalloc(drvDSAVerify_zone, ICP_M_NOWAIT); -+ if (NULL == dsaVerifyOpData) { -+ APRINTK("%s():Failed to get memory" -+ " for DSA Verify Op data struct\n", __FUNCTION__); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ /* Link parameters */ -+ dsaVerifyOpData->P.pData = -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PRIME_P_INDEX].crp_p; -+ BITS_TO_BYTES(dsaVerifyOpData->P.dataLenInBytes, -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PRIME_P_INDEX]. -+ crp_nbits); -+ icp_ocfDrvSwapBytes(dsaVerifyOpData->P.pData, -+ dsaVerifyOpData->P.dataLenInBytes); -+ -+ dsaVerifyOpData->Q.pData = -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PRIME_Q_INDEX].crp_p; -+ BITS_TO_BYTES(dsaVerifyOpData->Q.dataLenInBytes, -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PRIME_Q_INDEX]. -+ crp_nbits); -+ icp_ocfDrvSwapBytes(dsaVerifyOpData->Q.pData, -+ dsaVerifyOpData->Q.dataLenInBytes); -+ -+ dsaVerifyOpData->G.pData = -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_G_INDEX].crp_p; -+ BITS_TO_BYTES(dsaVerifyOpData->G.dataLenInBytes, -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_G_INDEX]. -+ crp_nbits); -+ icp_ocfDrvSwapBytes(dsaVerifyOpData->G.pData, -+ dsaVerifyOpData->G.dataLenInBytes); -+ -+ dsaVerifyOpData->Y.pData = -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PUBKEY_INDEX].crp_p; -+ BITS_TO_BYTES(dsaVerifyOpData->Y.dataLenInBytes, -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PUBKEY_INDEX]. -+ crp_nbits); -+ icp_ocfDrvSwapBytes(dsaVerifyOpData->Y.pData, -+ dsaVerifyOpData->Y.dataLenInBytes); -+ -+ /*OpenSSL dgst parameter is left in big endian byte order, -+ therefore no byte swap is required */ -+ dsaVerifyOpData->M.pData = -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_DGST_INDEX].crp_p; -+ BITS_TO_BYTES(dsaVerifyOpData->M.dataLenInBytes, -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_DGST_INDEX]. -+ crp_nbits); -+ -+ dsaVerifyOpData->R.pData = -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_SIG_R_INDEX].crp_p; -+ BITS_TO_BYTES(dsaVerifyOpData->R.dataLenInBytes, -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_SIG_R_INDEX]. -+ crp_nbits); -+ icp_ocfDrvSwapBytes(dsaVerifyOpData->R.pData, -+ dsaVerifyOpData->R.dataLenInBytes); -+ -+ dsaVerifyOpData->S.pData = -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_SIG_S_INDEX].crp_p; -+ BITS_TO_BYTES(dsaVerifyOpData->S.dataLenInBytes, -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_SIG_S_INDEX]. -+ crp_nbits); -+ icp_ocfDrvSwapBytes(dsaVerifyOpData->S.pData, -+ dsaVerifyOpData->S.dataLenInBytes); -+ -+ lacStatus = cpaCyDsaVerify(CPA_INSTANCE_HANDLE_SINGLE, -+ icp_ocfDrvDsaVerifyCallBack, -+ callbackTag, dsaVerifyOpData, &verifyStatus); -+ -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): DSA Verify Operation failed (%d).\n", -+ __FUNCTION__, lacStatus); -+ ICP_CACHE_FREE(drvDSAVerify_zone, dsaVerifyOpData); -+ krp->krp_status = ECANCELED; -+ } -+ -+ return lacStatus; -+} -+ -+/* Name : icp_ocfDrvDhP1Callback -+ * -+ * Description : When this function returns it signifies that the LAC -+ * component has completed the DH operation. -+ */ -+static void -+icp_ocfDrvDhP1CallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, CpaFlatBuffer * pLocalOctetStringPV) -+{ -+ struct cryptkop *krp = NULL; -+ CpaCyDhPhase1KeyGenOpData *pPhase1OpData = NULL; -+ -+ if (NULL == callbackTag) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "callbackTag data is NULL\n", __FUNCTION__); -+ return; -+ } -+ krp = (struct cryptkop *)callbackTag; -+ -+ if (NULL == pOpData) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "Operation Data is NULL\n", __FUNCTION__); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ pPhase1OpData = (CpaCyDhPhase1KeyGenOpData *) pOpData; -+ -+ if (NULL == pLocalOctetStringPV) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "pLocalOctetStringPV Data is NULL\n", __FUNCTION__); -+ memset(pPhase1OpData, 0, sizeof(CpaCyDhPhase1KeyGenOpData)); -+ ICP_CACHE_FREE(drvDH_zone, pPhase1OpData); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ -+ if (CPA_STATUS_SUCCESS == status) { -+ krp->krp_status = CRYPTO_OP_SUCCESS; -+ } else { -+ APRINTK("%s(): Diffie Hellman Phase1 Key Gen failed - " -+ "Operation Status = %d\n", __FUNCTION__, status); -+ krp->krp_status = ECANCELED; -+ } -+ -+ icp_ocfDrvSwapBytes(pLocalOctetStringPV->pData, -+ pLocalOctetStringPV->dataLenInBytes); -+ -+ icp_ocfDrvFreeFlatBuffer(pLocalOctetStringPV); -+ memset(pPhase1OpData, 0, sizeof(CpaCyDhPhase1KeyGenOpData)); -+ ICP_CACHE_FREE(drvDH_zone, pPhase1OpData); -+ -+ crypto_kdone(krp); -+ -+ return; -+} -+ -+/* Name : icp_ocfDrvModExpCallBack -+ * -+ * Description : When this function returns it signifies that the LAC -+ * component has completed the Mod Exp operation. -+ */ -+static void -+icp_ocfDrvModExpCallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpdata, CpaFlatBuffer * pResult) -+{ -+ struct cryptkop *krp = NULL; -+ CpaCyLnModExpOpData *pLnModExpOpData = NULL; -+ -+ if (NULL == callbackTag) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "callbackTag data is NULL\n", __FUNCTION__); -+ return; -+ } -+ krp = (struct cryptkop *)callbackTag; -+ -+ if (NULL == pOpdata) { -+ DPRINTK("%s(): Invalid Mod Exp input parameters - " -+ "Operation Data is NULL\n", __FUNCTION__); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ pLnModExpOpData = (CpaCyLnModExpOpData *) pOpdata; -+ -+ if (NULL == pResult) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "pResult data is NULL\n", __FUNCTION__); -+ krp->krp_status = ECANCELED; -+ memset(pLnModExpOpData, 0, sizeof(CpaCyLnModExpOpData)); -+ ICP_CACHE_FREE(drvLnModExp_zone, pLnModExpOpData); -+ crypto_kdone(krp); -+ return; -+ } -+ -+ if (CPA_STATUS_SUCCESS == status) { -+ krp->krp_status = CRYPTO_OP_SUCCESS; -+ } else { -+ APRINTK("%s(): LAC Mod Exp Operation failed - " -+ "Operation Status = %d\n", __FUNCTION__, status); -+ krp->krp_status = ECANCELED; -+ } -+ -+ icp_ocfDrvSwapBytes(pResult->pData, pResult->dataLenInBytes); -+ -+ /*switch base size value back to original */ -+ if (pLnModExpOpData->base.pData == -+ (uint8_t *) & (krp-> -+ krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX]. -+ crp_nbits)) { -+ *((uint32_t *) pLnModExpOpData->base.pData) = -+ ntohl(*((uint32_t *) pLnModExpOpData->base.pData)); -+ } -+ icp_ocfDrvFreeFlatBuffer(pResult); -+ memset(pLnModExpOpData, 0, sizeof(CpaCyLnModExpOpData)); -+ ICP_CACHE_FREE(drvLnModExp_zone, pLnModExpOpData); -+ -+ crypto_kdone(krp); -+ -+ return; -+ -+} -+ -+/* Name : icp_ocfDrvModExpCRTCallBack -+ * -+ * Description : When this function returns it signifies that the LAC -+ * component has completed the Mod Exp CRT operation. -+ */ -+static void -+icp_ocfDrvModExpCRTCallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, CpaFlatBuffer * pOutputData) -+{ -+ struct cryptkop *krp = NULL; -+ CpaCyRsaDecryptOpData *pDecryptData = NULL; -+ -+ if (NULL == callbackTag) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "callbackTag data is NULL\n", __FUNCTION__); -+ return; -+ } -+ -+ krp = (struct cryptkop *)callbackTag; -+ -+ if (NULL == pOpData) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "Operation Data is NULL\n", __FUNCTION__); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ pDecryptData = (CpaCyRsaDecryptOpData *) pOpData; -+ -+ if (NULL == pOutputData) { -+ DPRINTK("%s(): Invalid input parameter - " -+ "pOutputData is NULL\n", __FUNCTION__); -+ memset(pDecryptData->pRecipientPrivateKey, 0, -+ sizeof(CpaCyRsaPrivateKey)); -+ ICP_CACHE_FREE(drvRSAPrivateKey_zone, -+ pDecryptData->pRecipientPrivateKey); -+ memset(pDecryptData, 0, sizeof(CpaCyRsaDecryptOpData)); -+ ICP_CACHE_FREE(drvRSADecrypt_zone, pDecryptData); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ -+ if (CPA_STATUS_SUCCESS == status) { -+ krp->krp_status = CRYPTO_OP_SUCCESS; -+ } else { -+ APRINTK("%s(): LAC Mod Exp CRT operation failed - " -+ "Operation Status = %d\n", __FUNCTION__, status); -+ krp->krp_status = ECANCELED; -+ } -+ -+ icp_ocfDrvSwapBytes(pOutputData->pData, pOutputData->dataLenInBytes); -+ -+ icp_ocfDrvFreeFlatBuffer(pOutputData); -+ memset(pDecryptData->pRecipientPrivateKey, 0, -+ sizeof(CpaCyRsaPrivateKey)); -+ ICP_CACHE_FREE(drvRSAPrivateKey_zone, -+ pDecryptData->pRecipientPrivateKey); -+ memset(pDecryptData, 0, sizeof(CpaCyRsaDecryptOpData)); -+ ICP_CACHE_FREE(drvRSADecrypt_zone, pDecryptData); -+ -+ crypto_kdone(krp); -+ -+ return; -+} -+ -+/* Name : icp_ocfDrvDsaRSSignCallBack -+ * -+ * Description : When this function returns it signifies that the LAC -+ * component has completed the DSA RS sign operation. -+ */ -+static void -+icp_ocfDrvDsaRSSignCallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, -+ CpaBoolean protocolStatus, -+ CpaFlatBuffer * pR, CpaFlatBuffer * pS) -+{ -+ struct cryptkop *krp = NULL; -+ CpaCyDsaRSSignOpData *pSignData = NULL; -+ -+ if (NULL == callbackTag) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "callbackTag data is NULL\n", __FUNCTION__); -+ return; -+ } -+ -+ krp = (struct cryptkop *)callbackTag; -+ -+ if (NULL == pOpData) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "Operation Data is NULL\n", __FUNCTION__); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ pSignData = (CpaCyDsaRSSignOpData *) pOpData; -+ -+ if (NULL == pR) { -+ DPRINTK("%s(): Invalid input parameter - " -+ "pR sign is NULL\n", __FUNCTION__); -+ icp_ocfDrvFreeFlatBuffer(pS); -+ ICP_CACHE_FREE(drvDSARSSign_zone, pSignData); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ -+ if (NULL == pS) { -+ DPRINTK("%s(): Invalid input parameter - " -+ "pS sign is NULL\n", __FUNCTION__); -+ icp_ocfDrvFreeFlatBuffer(pR); -+ ICP_CACHE_FREE(drvDSARSSign_zone, pSignData); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ -+ if (CPA_STATUS_SUCCESS != status) { -+ APRINTK("%s(): LAC DSA RS Sign operation failed - " -+ "Operation Status = %d\n", __FUNCTION__, status); -+ krp->krp_status = ECANCELED; -+ } else { -+ krp->krp_status = CRYPTO_OP_SUCCESS; -+ -+ if (CPA_TRUE != protocolStatus) { -+ DPRINTK("%s(): LAC DSA RS Sign operation failed due " -+ "to protocol error\n", __FUNCTION__); -+ krp->krp_status = EIO; -+ } -+ } -+ -+ /* Swap bytes only when the callback status is successful and -+ protocolStatus is set to true */ -+ if (CPA_STATUS_SUCCESS == status && CPA_TRUE == protocolStatus) { -+ icp_ocfDrvSwapBytes(pR->pData, pR->dataLenInBytes); -+ icp_ocfDrvSwapBytes(pS->pData, pS->dataLenInBytes); -+ } -+ -+ icp_ocfDrvFreeFlatBuffer(pR); -+ icp_ocfDrvFreeFlatBuffer(pS); -+ memset(pSignData->K.pData, 0, pSignData->K.dataLenInBytes); -+ ICP_CACHE_FREE(drvDSARSSignKValue_zone, pSignData->K.pData); -+ memset(pSignData, 0, sizeof(CpaCyDsaRSSignOpData)); -+ ICP_CACHE_FREE(drvDSARSSign_zone, pSignData); -+ crypto_kdone(krp); -+ -+ return; -+} -+ -+/* Name : icp_ocfDrvDsaVerifyCallback -+ * -+ * Description : When this function returns it signifies that the LAC -+ * component has completed the DSA Verify operation. -+ */ -+static void -+icp_ocfDrvDsaVerifyCallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, CpaBoolean verifyStatus) -+{ -+ -+ struct cryptkop *krp = NULL; -+ CpaCyDsaVerifyOpData *pVerData = NULL; -+ -+ if (NULL == callbackTag) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "callbackTag data is NULL\n", __FUNCTION__); -+ return; -+ } -+ -+ krp = (struct cryptkop *)callbackTag; -+ -+ if (NULL == pOpData) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "Operation Data is NULL\n", __FUNCTION__); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ pVerData = (CpaCyDsaVerifyOpData *) pOpData; -+ -+ if (CPA_STATUS_SUCCESS != status) { -+ APRINTK("%s(): LAC DSA Verify operation failed - " -+ "Operation Status = %d\n", __FUNCTION__, status); -+ krp->krp_status = ECANCELED; -+ } else { -+ krp->krp_status = CRYPTO_OP_SUCCESS; -+ -+ if (CPA_TRUE != verifyStatus) { -+ DPRINTK("%s(): DSA signature invalid\n", __FUNCTION__); -+ krp->krp_status = EIO; -+ } -+ } -+ -+ /* Swap bytes only when the callback status is successful and -+ verifyStatus is set to true */ -+ /*Just swapping back the key values for now. Possibly all -+ swapped buffers need to be reverted */ -+ if (CPA_STATUS_SUCCESS == status && CPA_TRUE == verifyStatus) { -+ icp_ocfDrvSwapBytes(pVerData->R.pData, -+ pVerData->R.dataLenInBytes); -+ icp_ocfDrvSwapBytes(pVerData->S.pData, -+ pVerData->S.dataLenInBytes); -+ } -+ -+ memset(pVerData, 0, sizeof(CpaCyDsaVerifyOpData)); -+ ICP_CACHE_FREE(drvDSAVerify_zone, pVerData); -+ crypto_kdone(krp); -+ -+ return; -+} -diff -Nur linux-3.0.4.orig/crypto/ocf/ep80579/icp_common.c linux-3.0.4/crypto/ocf/ep80579/icp_common.c ---- linux-3.0.4.orig/crypto/ocf/ep80579/icp_common.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/ep80579/icp_common.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,773 @@ -+/************************************************************************* -+ * -+ * This file is provided under a dual BSD/GPLv2 license. When using or -+ * redistributing this file, you may do so under either license. -+ * -+ * GPL LICENSE SUMMARY -+ * -+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of version 2 of the GNU General Public License as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. -+ * The full GNU General Public License is included in this distribution -+ * in the file called LICENSE.GPL. -+ * -+ * Contact Information: -+ * Intel Corporation -+ * -+ * BSD LICENSE -+ * -+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * * Neither the name of Intel Corporation nor the names of its -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * -+ * version: Security.L.1.0.2-229 -+ * -+ ***************************************************************************/ -+ -+/* -+ * An OCF module that uses Intel® QuickAssist Integrated Accelerator to do the -+ * crypto. -+ * -+ * This driver requires the ICP Access Library that is available from Intel in -+ * order to operate. -+ */ -+ -+#include "icp_ocf.h" -+ -+#define ICP_OCF_COMP_NAME "ICP_OCF" -+#define ICP_OCF_VER_MAIN (2) -+#define ICP_OCF_VER_MJR (1) -+#define ICP_OCF_VER_MNR (0) -+ -+#define MAX_DEREG_RETRIES (100) -+#define DEFAULT_DEREG_RETRIES (10) -+#define DEFAULT_DEREG_DELAY_IN_JIFFIES (10) -+ -+/* This defines the maximum number of sessions possible between OCF -+ and the OCF EP80579 Driver. If set to zero, there is no limit. */ -+#define DEFAULT_OCF_TO_DRV_MAX_SESSION_COUNT (0) -+#define NUM_SUPPORTED_CAPABILITIES (21) -+ -+/*Slab zone names*/ -+#define ICP_SESSION_DATA_NAME "icp_ocf.SesDat" -+#define ICP_OP_DATA_NAME "icp_ocf.OpDat" -+#define ICP_DH_NAME "icp_ocf.DH" -+#define ICP_MODEXP_NAME "icp_ocf.ModExp" -+#define ICP_RSA_DECRYPT_NAME "icp_ocf.RSAdec" -+#define ICP_RSA_PKEY_NAME "icp_ocf.RSApk" -+#define ICP_DSA_SIGN_NAME "icp_ocf.DSAsg" -+#define ICP_DSA_VER_NAME "icp_ocf.DSAver" -+#define ICP_RAND_VAL_NAME "icp_ocf.DSArnd" -+#define ICP_FLAT_BUFF_NAME "icp_ocf.FB" -+ -+/*Slabs zones*/ -+icp_kmem_cache drvSessionData_zone = NULL; -+icp_kmem_cache drvOpData_zone = NULL; -+icp_kmem_cache drvDH_zone = NULL; -+icp_kmem_cache drvLnModExp_zone = NULL; -+icp_kmem_cache drvRSADecrypt_zone = NULL; -+icp_kmem_cache drvRSAPrivateKey_zone = NULL; -+icp_kmem_cache drvDSARSSign_zone = NULL; -+icp_kmem_cache drvDSARSSignKValue_zone = NULL; -+icp_kmem_cache drvDSAVerify_zone = NULL; -+ -+/*Slab zones for flatbuffers and bufferlist*/ -+icp_kmem_cache drvFlatBuffer_zone = NULL; -+ -+static inline int icp_cache_null_check(void) -+{ -+ return (drvSessionData_zone && drvOpData_zone -+ && drvDH_zone && drvLnModExp_zone && drvRSADecrypt_zone -+ && drvRSAPrivateKey_zone && drvDSARSSign_zone -+ && drvDSARSSign_zone && drvDSARSSignKValue_zone -+ && drvDSAVerify_zone && drvFlatBuffer_zone); -+} -+ -+/*Function to free all allocated slab caches before exiting the module*/ -+static void icp_ocfDrvFreeCaches(void); -+ -+int32_t icp_ocfDrvDriverId = INVALID_DRIVER_ID; -+ -+/* Module parameter - gives the number of times LAC deregistration shall be -+ re-tried */ -+int num_dereg_retries = DEFAULT_DEREG_RETRIES; -+ -+/* Module parameter - gives the delay time in jiffies before a LAC session -+ shall be attempted to be deregistered again */ -+int dereg_retry_delay_in_jiffies = DEFAULT_DEREG_DELAY_IN_JIFFIES; -+ -+/* Module parameter - gives the maximum number of sessions possible between -+ OCF and the OCF EP80579 Driver. If set to zero, there is no limit.*/ -+int max_sessions = DEFAULT_OCF_TO_DRV_MAX_SESSION_COUNT; -+ -+/* This is set when the module is removed from the system, no further -+ processing can take place if this is set */ -+icp_atomic_t icp_ocfDrvIsExiting = ICP_ATOMIC_INIT(0); -+ -+/* This is used to show how many lac sessions were not deregistered*/ -+icp_atomic_t lac_session_failed_dereg_count = ICP_ATOMIC_INIT(0); -+ -+/* This is used to track the number of registered sessions between OCF and -+ * and the OCF EP80579 driver, when max_session is set to value other than -+ * zero. This ensures that the max_session set for the OCF and the driver -+ * is equal to the LAC registered sessions */ -+icp_atomic_t num_ocf_to_drv_registered_sessions = ICP_ATOMIC_INIT(0); -+ -+/* Head of linked list used to store session data */ -+icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead; -+icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead_FreeMemList; -+ -+icp_spinlock_t icp_ocfDrvSymSessInfoListSpinlock; -+ -+/*Below pointer is only used in linux, FreeBSD uses the name to -+create its own variable name*/ -+icp_workqueue *icp_ocfDrvFreeLacSessionWorkQ = NULL; -+ICP_WORKQUEUE_DEFINE_THREAD(icp_ocfDrvFreeLacSessionWorkQ); -+ -+struct icp_drvBuffListInfo defBuffListInfo; -+ -+/* Name : icp_ocfDrvInit -+ * -+ * Description : This function will register all the symmetric and asymmetric -+ * functionality that will be accelerated by the hardware. It will also -+ * get a unique driver ID from the OCF and initialise all slab caches -+ */ -+ICP_MODULE_INIT_FUNC(icp_ocfDrvInit) -+{ -+ int ocfStatus = 0; -+ -+ IPRINTK("=== %s ver %d.%d.%d ===\n", ICP_OCF_COMP_NAME, -+ ICP_OCF_VER_MAIN, ICP_OCF_VER_MJR, ICP_OCF_VER_MNR); -+ -+ if (MAX_DEREG_RETRIES < num_dereg_retries) { -+ EPRINTK("Session deregistration retry count set to greater " -+ "than %d", MAX_DEREG_RETRIES); -+ icp_module_return_code(EINVAL); -+ } -+ -+ /* Initialize and Start the Cryptographic component */ -+ if (CPA_STATUS_SUCCESS != -+ cpaCyStartInstance(CPA_INSTANCE_HANDLE_SINGLE)) { -+ EPRINTK("Failed to initialize and start the instance " -+ "of the Cryptographic component.\n"); -+ return icp_module_return_code(EINVAL); -+ } -+ -+ icp_spin_lock_init(&icp_ocfDrvSymSessInfoListSpinlock); -+ -+ /* Set the default size of BufferList to allocate */ -+ memset(&defBuffListInfo, 0, sizeof(struct icp_drvBuffListInfo)); -+ if (ICP_OCF_DRV_STATUS_SUCCESS != -+ icp_ocfDrvBufferListMemInfo(ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS, -+ &defBuffListInfo)) { -+ EPRINTK("Failed to get bufferlist memory info.\n"); -+ return icp_module_return_code(ENOMEM); -+ } -+ -+ /*Register OCF EP80579 Driver with OCF */ -+ icp_ocfDrvDriverId = ICP_CRYPTO_GET_DRIVERID(); -+ -+ if (icp_ocfDrvDriverId < 0) { -+ EPRINTK("%s : ICP driver failed to register with OCF!\n", -+ __FUNCTION__); -+ return icp_module_return_code(ENODEV); -+ } -+ -+ /*Create all the slab caches used by the OCF EP80579 Driver */ -+ drvSessionData_zone = -+ ICP_CACHE_CREATE(ICP_SESSION_DATA_NAME, struct icp_drvSessionData); -+ -+ /* -+ * Allocation of the OpData includes the allocation space for meta data. -+ * The memory after the opData structure is reserved for this meta data. -+ */ -+ drvOpData_zone = -+ icp_kmem_cache_create(ICP_OP_DATA_NAME, -+ sizeof(struct icp_drvOpData) + -+ defBuffListInfo.metaSize, -+ ICP_KERNEL_CACHE_ALIGN, -+ ICP_KERNEL_CACHE_NOINIT); -+ -+ drvDH_zone = ICP_CACHE_CREATE(ICP_DH_NAME, CpaCyDhPhase1KeyGenOpData); -+ -+ drvLnModExp_zone = -+ ICP_CACHE_CREATE(ICP_MODEXP_NAME, CpaCyLnModExpOpData); -+ -+ drvRSADecrypt_zone = -+ ICP_CACHE_CREATE(ICP_RSA_DECRYPT_NAME, CpaCyRsaDecryptOpData); -+ -+ drvRSAPrivateKey_zone = -+ ICP_CACHE_CREATE(ICP_RSA_PKEY_NAME, CpaCyRsaPrivateKey); -+ -+ drvDSARSSign_zone = -+ ICP_CACHE_CREATE(ICP_DSA_SIGN_NAME, CpaCyDsaRSSignOpData); -+ -+ /*too awkward to use a macro here */ -+ drvDSARSSignKValue_zone = -+ ICP_CACHE_CREATE(ICP_RAND_VAL_NAME, -+ DSA_RS_SIGN_PRIMEQ_SIZE_IN_BYTES); -+ -+ drvDSAVerify_zone = -+ ICP_CACHE_CREATE(ICP_DSA_VER_NAME, CpaCyDsaVerifyOpData); -+ -+ drvFlatBuffer_zone = -+ ICP_CACHE_CREATE(ICP_FLAT_BUFF_NAME, CpaFlatBuffer); -+ -+ if (0 == icp_cache_null_check()) { -+ icp_ocfDrvFreeCaches(); -+ EPRINTK("%s() line %d: Not enough memory!\n", -+ __FUNCTION__, __LINE__); -+ return ENOMEM; -+ } -+ -+ /* Register the ICP symmetric crypto support. */ -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_NULL_CBC, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_DES_CBC, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_3DES_CBC, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_AES_CBC, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_ARC4, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_MD5, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_MD5_HMAC, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA1, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA1_HMAC, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_256, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_256_HMAC, -+ ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_384, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_384_HMAC, -+ ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_512, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_512_HMAC, -+ ocfStatus); -+ -+ /* Register the ICP asymmetric algorithm support */ -+ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_DH_COMPUTE_KEY, -+ ocfStatus); -+ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_MOD_EXP, ocfStatus); -+ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_MOD_EXP_CRT, ocfStatus); -+ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_DSA_SIGN, ocfStatus); -+ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_DSA_VERIFY, ocfStatus); -+ -+ /* Register the ICP random number generator support */ -+ ICP_REG_RAND_WITH_OCF(icp_ocfDrvDriverId, -+ icp_ocfDrvReadRandom, NULL, ocfStatus); -+ -+ if (OCF_ZERO_FUNCTIONALITY_REGISTERED == ocfStatus) { -+ DPRINTK("%s: Failed to register any device capabilities\n", -+ __FUNCTION__); -+ icp_ocfDrvFreeCaches(); -+ icp_ocfDrvDriverId = INVALID_DRIVER_ID; -+ return icp_module_return_code(ECANCELED); -+ } -+ -+ DPRINTK("%s: Registered %d of %d device capabilities\n", -+ __FUNCTION__, ocfStatus, NUM_SUPPORTED_CAPABILITIES); -+ -+ /*Session data linked list used during module exit */ -+ ICP_INIT_LIST_HEAD(&icp_ocfDrvGlobalSymListHead); -+ ICP_INIT_LIST_HEAD(&icp_ocfDrvGlobalSymListHead_FreeMemList); -+ -+ ICP_WORKQUEUE_CREATE(icp_ocfDrvFreeLacSessionWorkQ, "icpwq"); -+ if (ICP_WORKQUEUE_NULL_CHECK(icp_ocfDrvFreeLacSessionWorkQ)) { -+ EPRINTK("%s: Failed to create single " -+ "thread workqueue\n", __FUNCTION__); -+ icp_ocfDrvFreeCaches(); -+ icp_ocfDrvDriverId = INVALID_DRIVER_ID; -+ return icp_module_return_code(ENOMEM); -+ } -+ -+ return icp_module_return_code(0); -+} -+ -+/* Name : icp_ocfDrvExit -+ * -+ * Description : This function will deregister all the symmetric sessions -+ * registered with the LAC component. It will also deregister all symmetric -+ * and asymmetric functionality that can be accelerated by the hardware via OCF -+ * and random number generation if it is enabled. -+ */ -+ICP_MODULE_EXIT_FUNC(icp_ocfDrvExit) -+{ -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ struct icp_drvSessionData *sessionData = NULL; -+ struct icp_drvSessionData *tempSessionData = NULL; -+ int i, remaining_delay_time_in_jiffies = 0; -+ -+ /* For FreeBSD the invariant macro below makes function to return */ -+ /* with EBUSY value in the case of any session which has been regi- */ -+ /* stered with LAC not being deregistered. */ -+ /* The Linux implementation is empty since it is purely to compensate */ -+ /* for a limitation of the FreeBSD 7.1 Opencrypto framework. */ -+ -+ ICP_MODULE_EXIT_INV(); -+ -+ /* There is a possibility of a process or new session command being */ -+ /* sent before this variable is incremented. The aim of this variable */ -+ /* is to stop a loop of calls creating a deadlock situation which */ -+ /* would prevent the driver from exiting. */ -+ icp_atomic_set(&icp_ocfDrvIsExiting, 1); -+ -+ /*Existing sessions will be routed to another driver after these calls */ -+ crypto_unregister_all(icp_ocfDrvDriverId); -+ crypto_runregister_all(icp_ocfDrvDriverId); -+ -+ if (ICP_WORKQUEUE_NULL_CHECK(icp_ocfDrvFreeLacSessionWorkQ)) { -+ DPRINTK("%s: workqueue already " -+ "destroyed, therefore module exit " -+ " function already called. Exiting.\n", __FUNCTION__); -+ return ICP_MODULE_EXIT_FUNC_RETURN_VAL; -+ } -+ /*If any sessions are waiting to be deregistered, do that. This also -+ flushes the work queue */ -+ ICP_WORKQUEUE_DESTROY(icp_ocfDrvFreeLacSessionWorkQ); -+ -+ /*ENTER CRITICAL SECTION */ -+ icp_spin_lockbh_lock(&icp_ocfDrvSymSessInfoListSpinlock); -+ -+ ICP_LIST_FOR_EACH_ENTRY_SAFE(tempSessionData, sessionData, -+ &icp_ocfDrvGlobalSymListHead, listNode) { -+ for (i = 0; i < num_dereg_retries; i++) { -+ /*No harm if bad input - LAC will handle error cases */ -+ if (ICP_SESSION_RUNNING == tempSessionData->inUse) { -+ lacStatus = -+ cpaCySymRemoveSession -+ (CPA_INSTANCE_HANDLE_SINGLE, -+ tempSessionData->sessHandle); -+ if (CPA_STATUS_SUCCESS == lacStatus) { -+ /* Succesfully deregistered */ -+ break; -+ } else if (CPA_STATUS_RETRY != lacStatus) { -+ icp_atomic_inc -+ (&lac_session_failed_dereg_count); -+ break; -+ } -+ -+ /*schedule_timout returns the time left for completion if -+ * this task is set to TASK_INTERRUPTIBLE */ -+ remaining_delay_time_in_jiffies = -+ dereg_retry_delay_in_jiffies; -+ while (0 > remaining_delay_time_in_jiffies) { -+ remaining_delay_time_in_jiffies = -+ icp_schedule_timeout -+ (&icp_ocfDrvSymSessInfoListSpinlock, -+ remaining_delay_time_in_jiffies); -+ } -+ -+ DPRINTK -+ ("%s(): Retry %d to deregistrate the session\n", -+ __FUNCTION__, i); -+ } -+ } -+ -+ /*remove from current list */ -+ ICP_LIST_DEL(tempSessionData, listNode); -+ /*add to free mem linked list */ -+ ICP_LIST_ADD(tempSessionData, -+ &icp_ocfDrvGlobalSymListHead_FreeMemList, -+ listNode); -+ -+ } -+ -+ /*EXIT CRITICAL SECTION */ -+ icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock); -+ -+ /*set back to initial values */ -+ sessionData = NULL; -+ /*still have a reference in our list! */ -+ tempSessionData = NULL; -+ /*free memory */ -+ -+ ICP_LIST_FOR_EACH_ENTRY_SAFE(tempSessionData, sessionData, -+ &icp_ocfDrvGlobalSymListHead_FreeMemList, -+ listNode) { -+ -+ ICP_LIST_DEL(tempSessionData, listNode); -+ /* Free allocated CpaCySymSessionCtx */ -+ if (NULL != tempSessionData->sessHandle) { -+ icp_kfree(tempSessionData->sessHandle); -+ } -+ memset(tempSessionData, 0, sizeof(struct icp_drvSessionData)); -+ ICP_CACHE_FREE(drvSessionData_zone, tempSessionData); -+ } -+ -+ if (0 != icp_atomic_read(&lac_session_failed_dereg_count)) { -+ DPRINTK("%s(): %d LAC sessions were not deregistered " -+ "correctly. This is not a clean exit! \n", -+ __FUNCTION__, -+ icp_atomic_read(&lac_session_failed_dereg_count)); -+ } -+ -+ icp_ocfDrvFreeCaches(); -+ icp_ocfDrvDriverId = INVALID_DRIVER_ID; -+ -+ icp_spin_lock_destroy(&icp_ocfDrvSymSessInfoListSpinlock); -+ -+ /* Shutdown the Cryptographic component */ -+ lacStatus = cpaCyStopInstance(CPA_INSTANCE_HANDLE_SINGLE); -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ DPRINTK("%s(): Failed to stop instance of the " -+ "Cryptographic component.(status == %d)\n", -+ __FUNCTION__, lacStatus); -+ } -+ -+ return ICP_MODULE_EXIT_FUNC_RETURN_VAL; -+} -+ -+/* Name : icp_ocfDrvFreeCaches -+ * -+ * Description : This function deregisters all slab caches -+ */ -+static void icp_ocfDrvFreeCaches(void) -+{ -+ icp_atomic_set(&icp_ocfDrvIsExiting, 1); -+ -+ /*Sym Zones */ -+ ICP_CACHE_DESTROY(drvSessionData_zone); -+ ICP_CACHE_DESTROY(drvOpData_zone); -+ -+ /*Asym zones */ -+ ICP_CACHE_DESTROY(drvDH_zone); -+ ICP_CACHE_DESTROY(drvLnModExp_zone); -+ ICP_CACHE_DESTROY(drvRSADecrypt_zone); -+ ICP_CACHE_DESTROY(drvRSAPrivateKey_zone); -+ ICP_CACHE_DESTROY(drvDSARSSignKValue_zone); -+ ICP_CACHE_DESTROY(drvDSARSSign_zone); -+ ICP_CACHE_DESTROY(drvDSAVerify_zone); -+ -+ /*FlatBuffer and BufferList Zones */ -+ ICP_CACHE_DESTROY(drvFlatBuffer_zone); -+ -+} -+ -+/* Name : icp_ocfDrvDeregRetry -+ * -+ * Description : This function will try to farm the session deregistration -+ * off to a work queue. If it fails, nothing more can be done and it -+ * returns an error -+ */ -+int icp_ocfDrvDeregRetry(CpaCySymSessionCtx sessionToDeregister) -+{ -+ struct icp_ocfDrvFreeLacSession *workstore = NULL; -+ -+ DPRINTK("%s(): Retry - Deregistering session (%p)\n", -+ __FUNCTION__, sessionToDeregister); -+ -+ /*make sure the session is not available to be allocated during this -+ process */ -+ icp_atomic_inc(&lac_session_failed_dereg_count); -+ -+ /*Farm off to work queue */ -+ workstore = -+ icp_kmalloc(sizeof(struct icp_ocfDrvFreeLacSession), ICP_M_NOWAIT); -+ if (NULL == workstore) { -+ DPRINTK("%s(): unable to free session - no memory available " -+ "for work queue\n", __FUNCTION__); -+ return ENOMEM; -+ } -+ -+ workstore->sessionToDeregister = sessionToDeregister; -+ -+ icp_init_work(&(workstore->work), -+ icp_ocfDrvDeferedFreeLacSessionTaskFn, workstore); -+ -+ ICP_WORKQUEUE_ENQUEUE(icp_ocfDrvFreeLacSessionWorkQ, -+ &(workstore->work)); -+ -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+ -+} -+ -+/* Name : icp_ocfDrvDeferedFreeLacSessionProcess -+ * -+ * Description : This function will retry (module input parameter) -+ * 'num_dereg_retries' times to deregister any symmetric session that recieves a -+ * CPA_STATUS_RETRY message from the LAC component. This function is run in -+ * Thread context because it is called from a worker thread -+ */ -+void icp_ocfDrvDeferedFreeLacSessionProcess(void *arg) -+{ -+ struct icp_ocfDrvFreeLacSession *workstore = NULL; -+ CpaCySymSessionCtx sessionToDeregister = NULL; -+ int i = 0; -+ int remaining_delay_time_in_jiffies = 0; -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ -+ workstore = (struct icp_ocfDrvFreeLacSession *)arg; -+ if (NULL == workstore) { -+ DPRINTK("%s() function called with null parameter \n", -+ __FUNCTION__); -+ return; -+ } -+ -+ sessionToDeregister = workstore->sessionToDeregister; -+ icp_kfree(workstore); -+ -+ /*if exiting, give deregistration one more blast only */ -+ if (icp_atomic_read(&icp_ocfDrvIsExiting) == CPA_TRUE) { -+ lacStatus = cpaCySymRemoveSession(CPA_INSTANCE_HANDLE_SINGLE, -+ sessionToDeregister); -+ -+ if (lacStatus != CPA_STATUS_SUCCESS) { -+ DPRINTK("%s() Failed to Dereg LAC session %p " -+ "during module exit\n", __FUNCTION__, -+ sessionToDeregister); -+ return; -+ } -+ -+ icp_atomic_dec(&lac_session_failed_dereg_count); -+ return; -+ } -+ -+ for (i = 0; i <= num_dereg_retries; i++) { -+ lacStatus = cpaCySymRemoveSession(CPA_INSTANCE_HANDLE_SINGLE, -+ sessionToDeregister); -+ -+ if (lacStatus == CPA_STATUS_SUCCESS) { -+ icp_atomic_dec(&lac_session_failed_dereg_count); -+ return; -+ } -+ if (lacStatus != CPA_STATUS_RETRY) { -+ DPRINTK("%s() Failed to deregister session - lacStatus " -+ " = %d", __FUNCTION__, lacStatus); -+ break; -+ } -+ -+ /*schedule_timout returns the time left for completion if this -+ task is set to TASK_INTERRUPTIBLE */ -+ remaining_delay_time_in_jiffies = dereg_retry_delay_in_jiffies; -+ while (0 < remaining_delay_time_in_jiffies) { -+ remaining_delay_time_in_jiffies = -+ icp_schedule_timeout(NULL, -+ remaining_delay_time_in_jiffies); -+ } -+ -+ } -+ -+ DPRINTK("%s(): Unable to deregister session\n", __FUNCTION__); -+ DPRINTK("%s(): Number of unavailable LAC sessions = %d\n", __FUNCTION__, -+ icp_atomic_read(&lac_session_failed_dereg_count)); -+} -+ -+/* Name : icp_ocfDrvPtrAndLenToFlatBuffer -+ * -+ * Description : This function converts a "pointer and length" buffer -+ * structure to Fredericksburg Flat Buffer (CpaFlatBuffer) format. -+ * -+ * This function assumes that the data passed in are valid. -+ */ -+inline void -+icp_ocfDrvPtrAndLenToFlatBuffer(void *pData, uint32_t len, -+ CpaFlatBuffer * pFlatBuffer) -+{ -+ pFlatBuffer->pData = pData; -+ pFlatBuffer->dataLenInBytes = len; -+} -+ -+/* Name : icp_ocfDrvPtrAndLenToBufferList -+ * -+ * Description : This function converts a "pointer and length" buffer -+ * structure to Fredericksburg Scatter/Gather Buffer (CpaBufferList) format. -+ * -+ * This function assumes that the data passed in are valid. -+ */ -+inline void -+icp_ocfDrvPtrAndLenToBufferList(void *pDataIn, uint32_t length, -+ CpaBufferList * pBufferList) -+{ -+ pBufferList->numBuffers = 1; -+ pBufferList->pBuffers->pData = pDataIn; -+ pBufferList->pBuffers->dataLenInBytes = length; -+} -+ -+/* Name : icp_ocfDrvBufferListToPtrAndLen -+ * -+ * Description : This function converts Fredericksburg Scatter/Gather Buffer -+ * (CpaBufferList) format to a "pointer and length" buffer structure. -+ * -+ * This function assumes that the data passed in are valid. -+ */ -+inline void -+icp_ocfDrvBufferListToPtrAndLen(CpaBufferList * pBufferList, -+ void **ppDataOut, uint32_t * pLength) -+{ -+ *ppDataOut = pBufferList->pBuffers->pData; -+ *pLength = pBufferList->pBuffers->dataLenInBytes; -+} -+ -+/* Name : icp_ocfDrvBufferListMemInfo -+ * -+ * Description : This function will set the number of flat buffers in -+ * bufferlist, the size of memory to allocate for the pPrivateMetaData -+ * member of the CpaBufferList. -+ */ -+int -+icp_ocfDrvBufferListMemInfo(uint16_t numBuffers, -+ struct icp_drvBuffListInfo *buffListInfo) -+{ -+ buffListInfo->numBuffers = numBuffers; -+ -+ if (CPA_STATUS_SUCCESS != -+ cpaCyBufferListGetMetaSize(CPA_INSTANCE_HANDLE_SINGLE, -+ buffListInfo->numBuffers, -+ &(buffListInfo->metaSize))) { -+ EPRINTK("%s() Failed to get buffer list meta size.\n", -+ __FUNCTION__); -+ return ICP_OCF_DRV_STATUS_FAIL; -+ } -+ -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+} -+ -+/* Name : icp_ocfDrvFreeFlatBuffer -+ * -+ * Description : This function will deallocate flat buffer. -+ */ -+inline void icp_ocfDrvFreeFlatBuffer(CpaFlatBuffer * pFlatBuffer) -+{ -+ if (pFlatBuffer != NULL) { -+ memset(pFlatBuffer, 0, sizeof(CpaFlatBuffer)); -+ ICP_CACHE_FREE(drvFlatBuffer_zone, pFlatBuffer); -+ } -+} -+ -+/* Name : icp_ocfDrvAllocMetaData -+ * -+ * Description : This function will allocate memory for the -+ * pPrivateMetaData member of CpaBufferList. -+ */ -+inline int -+icp_ocfDrvAllocMetaData(CpaBufferList * pBufferList, -+ struct icp_drvOpData *pOpData) -+{ -+ Cpa32U metaSize = 0; -+ -+ if (pBufferList->numBuffers <= ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) { -+ uint8_t *pOpDataStartAddr = (uint8_t *) pOpData; -+ -+ if (0 == defBuffListInfo.metaSize) { -+ pBufferList->pPrivateMetaData = NULL; -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+ } -+ /* -+ * The meta data allocation has been included as part of the -+ * op data. It has been pre-allocated in memory just after the -+ * icp_drvOpData structure. -+ */ -+ pBufferList->pPrivateMetaData = (void *)(pOpDataStartAddr + -+ sizeof(struct -+ icp_drvOpData)); -+ } else { -+ if (CPA_STATUS_SUCCESS != -+ cpaCyBufferListGetMetaSize(CPA_INSTANCE_HANDLE_SINGLE, -+ pBufferList->numBuffers, -+ &metaSize)) { -+ EPRINTK("%s() Failed to get buffer list meta size.\n", -+ __FUNCTION__); -+ return ICP_OCF_DRV_STATUS_FAIL; -+ } -+ -+ if (0 == metaSize) { -+ pBufferList->pPrivateMetaData = NULL; -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+ } -+ -+ pBufferList->pPrivateMetaData = -+ icp_kmalloc(metaSize, ICP_M_NOWAIT); -+ } -+ if (NULL == pBufferList->pPrivateMetaData) { -+ EPRINTK("%s() Failed to allocate pPrivateMetaData.\n", -+ __FUNCTION__); -+ return ICP_OCF_DRV_STATUS_FAIL; -+ } -+ -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+} -+ -+/* Name : icp_ocfDrvFreeMetaData -+ * -+ * Description : This function will deallocate pPrivateMetaData memory. -+ */ -+inline void icp_ocfDrvFreeMetaData(CpaBufferList * pBufferList) -+{ -+ if (NULL == pBufferList->pPrivateMetaData) { -+ return; -+ } -+ -+ /* -+ * Only free the meta data if the BufferList has more than -+ * ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS number of buffers. -+ * Otherwise, the meta data shall be freed when the icp_drvOpData is -+ * freed. -+ */ -+ if (ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS < pBufferList->numBuffers) { -+ icp_kfree(pBufferList->pPrivateMetaData); -+ } -+} -+ -+/* Module declaration, init and exit functions */ -+ICP_DECLARE_MODULE(icp_ocf, icp_ocfDrvInit, icp_ocfDrvExit); -+ICP_MODULE_DESCRIPTION("OCF Driver for Intel Quick Assist crypto acceleration"); -+ICP_MODULE_VERSION(icp_ocf, ICP_OCF_VER_MJR); -+ICP_MODULE_LICENSE("Dual BSD/GPL"); -+ICP_MODULE_AUTHOR("Intel"); -+ -+/* Module parameters */ -+ICP_MODULE_PARAM_INT(icp_ocf, num_dereg_retries, -+ "Number of times to retry LAC Sym Session Deregistration. " -+ "Default 10, Max 100"); -+ICP_MODULE_PARAM_INT(icp_ocf, dereg_retry_delay_in_jiffies, "Delay in jiffies " -+ "(added to a schedule() function call) before a LAC Sym " -+ "Session Dereg is retried. Default 10"); -+ICP_MODULE_PARAM_INT(icp_ocf, max_sessions, -+ "This sets the maximum number of sessions " -+ "between OCF and this driver. If this value is set to zero," -+ "max session count checking is disabled. Default is zero(0)"); -+ -+/* Module dependencies */ -+#define MODULE_MIN_VER 1 -+#define CRYPTO_MAX_VER 3 -+#define LAC_MAX_VER 2 -+ -+ICP_MODULE_DEPEND(icp_ocf, crypto, MODULE_MIN_VER, MODULE_MIN_VER, -+ CRYPTO_MAX_VER); -+ICP_MODULE_DEPEND(icp_ocf, cryptodev, MODULE_MIN_VER, MODULE_MIN_VER, -+ CRYPTO_MAX_VER); -+ICP_MODULE_DEPEND(icp_ocf, icp_crypto, MODULE_MIN_VER, MODULE_MIN_VER, -+ LAC_MAX_VER); -diff -Nur linux-3.0.4.orig/crypto/ocf/ep80579/icp_ocf.h linux-3.0.4/crypto/ocf/ep80579/icp_ocf.h ---- linux-3.0.4.orig/crypto/ocf/ep80579/icp_ocf.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/ep80579/icp_ocf.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,376 @@ -+/*************************************************************************** -+ * -+ * This file is provided under a dual BSD/GPLv2 license. When using or -+ * redistributing this file, you may do so under either license. -+ * -+ * GPL LICENSE SUMMARY -+ * -+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of version 2 of the GNU General Public License as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. -+ * The full GNU General Public License is included in this distribution -+ * in the file called LICENSE.GPL. -+ * -+ * Contact Information: -+ * Intel Corporation -+ * -+ * BSD LICENSE -+ * -+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * * Neither the name of Intel Corporation nor the names of its -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * -+ * version: Security.L.1.0.2-229 -+ * -+ ***************************************************************************/ -+ -+/* -+ * OCF driver header file for the Intel ICP processor. -+ */ -+ -+#ifndef ICP_OCF_H_ -+#define ICP_OCF_H_ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "icp_os.h" -+ -+#define NUM_BITS_IN_BYTE (8) -+#define NUM_BITS_IN_BYTE_MINUS_ONE (NUM_BITS_IN_BYTE -1) -+#define INVALID_DRIVER_ID (-1) -+#define RETURN_RAND_NUM_GEN_FAILED (-1) -+ -+/*This is the max block cipher initialisation vector*/ -+#define MAX_IV_LEN_IN_BYTES (20) -+/*This is used to check whether the OCF to this driver session limit has -+ been disabled*/ -+#define NO_OCF_TO_DRV_MAX_SESSIONS (0) -+ -+/*OCF values mapped here*/ -+#define ICP_SHA1_DIGEST_SIZE_IN_BYTES (SHA1_HASH_LEN) -+#define ICP_SHA256_DIGEST_SIZE_IN_BYTES (SHA2_256_HASH_LEN) -+#define ICP_SHA384_DIGEST_SIZE_IN_BYTES (SHA2_384_HASH_LEN) -+#define ICP_SHA512_DIGEST_SIZE_IN_BYTES (SHA2_512_HASH_LEN) -+#define ICP_MD5_DIGEST_SIZE_IN_BYTES (MD5_HASH_LEN) -+#define ARC4_COUNTER_LEN (ARC4_BLOCK_LEN) -+ -+#define OCF_REGISTRATION_STATUS_SUCCESS (0) -+#define OCF_ZERO_FUNCTIONALITY_REGISTERED (0) -+#define ICP_OCF_DRV_NO_CRYPTO_PROCESS_ERROR (0) -+#define ICP_OCF_DRV_STATUS_SUCCESS (0) -+#define ICP_OCF_DRV_STATUS_FAIL (1) -+ -+/*Turn on/off debug options*/ -+#define ICP_OCF_PRINT_DEBUG_MESSAGES (0) -+#define ICP_OCF_PRINT_KERN_ALERT (1) -+#define ICP_OCF_PRINT_KERN_ERRS (1) -+ -+#if ICP_OCF_PRINT_DEBUG_MESSAGES == 1 -+#define DPRINTK(args...) \ -+{ \ -+ ICP_IPRINTK(args); \ -+} -+ -+#else //ICP_OCF_PRINT_DEBUG_MESSAGES == 1 -+ -+#define DPRINTK(args...) -+ -+#endif //ICP_OCF_PRINT_DEBUG_MESSAGES == 1 -+ -+#if ICP_OCF_PRINT_KERN_ALERT == 1 -+#define APRINTK(args...) \ -+{ \ -+ ICP_APRINTK(args); \ -+} -+ -+#else //ICP_OCF_PRINT_KERN_ALERT == 1 -+ -+#define APRINTK(args...) -+ -+#endif //ICP_OCF_PRINT_KERN_ALERT == 1 -+ -+#if ICP_OCF_PRINT_KERN_ERRS == 1 -+#define EPRINTK(args...) \ -+{ \ -+ ICP_EPRINTK(args); \ -+} -+ -+#else //ICP_OCF_PRINT_KERN_ERRS == 1 -+ -+#define EPRINTK(args...) -+ -+#endif //ICP_OCF_PRINT_KERN_ERRS == 1 -+ -+#define IPRINTK(args...) \ -+{ \ -+ ICP_IPRINTK(args); \ -+} -+ -+/*DSA Prime Q size in bytes (as defined in the standard) */ -+#define DSA_RS_SIGN_PRIMEQ_SIZE_IN_BYTES (20) -+ -+#define BITS_TO_BYTES(bytes, bits) \ -+ bytes = (bits + NUM_BITS_IN_BYTE_MINUS_ONE) / NUM_BITS_IN_BYTE -+ -+typedef enum { -+ ICP_OCF_DRV_ALG_CIPHER = 0, -+ ICP_OCF_DRV_ALG_HASH -+} icp_ocf_drv_alg_type_t; -+ -+typedef ICP_LIST_HEAD(icp_drvSessionListHead_s, -+ icp_drvSessionData) icp_drvSessionListHead_t; -+ -+/*Values used to derisk chances of performs being called against -+deregistered sessions (for which the slab page has been reclaimed) -+This is not a fix - since page frames are reclaimed from a slab, one cannot -+rely on that memory not being re-used by another app.*/ -+typedef enum { -+ ICP_SESSION_INITIALISED = 0x5C5C5C, -+ ICP_SESSION_RUNNING = 0x005C00, -+ ICP_SESSION_DEREGISTERED = 0xC5C5C5 -+} usage_derisk; -+ -+/* This struct is required for deferred session -+ deregistration as a work queue function can -+ only have one argument*/ -+struct icp_ocfDrvFreeLacSession { -+ CpaCySymSessionCtx sessionToDeregister; -+ icp_workstruct work; -+}; -+ -+/* -+This is the OCF<->OCF_DRV session object: -+ -+1.listNode -+ The first member is a listNode. These session objects are added to a linked -+ list in order to make it easier to remove them all at session exit time. -+ -+2.inUse -+ The second member is used to give the session object state and derisk the -+ possibility of OCF batch calls executing against a deregistered session (as -+ described above). -+ -+3.sessHandle -+ The third member is a LAC<->OCF_DRV session handle (initialised with the first -+ perform request for that session). -+ -+4.lacSessCtx -+ The fourth is the LAC session context. All the parameters for this structure -+ are only known when the first perform request for this session occurs. That is -+ why the OCF EP80579 Driver only registers a new LAC session at perform time -+*/ -+struct icp_drvSessionData { -+ ICP_LIST_ENTRY(icp_drvSessionData) listNode; -+ usage_derisk inUse; -+ CpaCySymSessionCtx sessHandle; -+ CpaCySymSessionSetupData lacSessCtx; -+}; -+ -+/* These are all defined in icp_common.c */ -+extern icp_atomic_t lac_session_failed_dereg_count; -+extern icp_atomic_t icp_ocfDrvIsExiting; -+extern icp_atomic_t num_ocf_to_drv_registered_sessions; -+ -+extern int32_t icp_ocfDrvDriverId; -+ -+extern icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead; -+extern icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead_FreeMemList; -+extern icp_workqueue *icp_ocfDrvFreeLacSessionWorkQ; -+extern icp_spinlock_t icp_ocfDrvSymSessInfoListSpinlock; -+ -+/*Slab zones for symettric functionality, instantiated in icp_common.c*/ -+extern icp_kmem_cache drvSessionData_zone; -+extern icp_kmem_cache drvOpData_zone; -+ -+/*Slabs zones for asymettric functionality, instantiated in icp_common.c*/ -+extern icp_kmem_cache drvDH_zone; -+extern icp_kmem_cache drvLnModExp_zone; -+extern icp_kmem_cache drvRSADecrypt_zone; -+extern icp_kmem_cache drvRSAPrivateKey_zone; -+extern icp_kmem_cache drvDSARSSign_zone; -+extern icp_kmem_cache drvDSARSSignKValue_zone; -+extern icp_kmem_cache drvDSAVerify_zone; -+ -+/* Module parameters defined in icp_cpmmon.c*/ -+ -+/* Module parameters - gives the number of times LAC deregistration shall be -+ re-tried */ -+extern int num_dereg_retries; -+ -+/* Module parameter - gives the delay time in jiffies before a LAC session -+ shall be attempted to be deregistered again */ -+extern int dereg_retry_delay_in_jiffies; -+ -+/* Module parameter - gives the maximum number of sessions possible between -+ OCF and the OCF EP80579 Driver. If set to zero, there is no limit.*/ -+extern int max_sessions; -+ -+/*Slab zones for flatbuffers and bufferlist*/ -+extern icp_kmem_cache drvFlatBuffer_zone; -+ -+#define ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS (16) -+ -+struct icp_drvBuffListInfo { -+ Cpa16U numBuffers; -+ Cpa32U metaSize; -+ Cpa32U metaOffset; -+ Cpa32U buffListSize; -+}; -+ -+extern struct icp_drvBuffListInfo defBuffListInfo; -+ -+/* This struct is used to keep a reference to the relevant node in the list -+ of sessionData structs, to the buffer type required by OCF and to the OCF -+ provided crp struct that needs to be returned. All this info is needed in -+ the callback function.*/ -+struct icp_drvOpData { -+ CpaCySymOpData lacOpData; -+ uint32_t digestSizeInBytes; -+ struct cryptop *crp; -+ uint8_t bufferType; -+ uint8_t ivData[MAX_IV_LEN_IN_BYTES]; -+ uint16_t numBufferListArray; -+ CpaBufferList srcBuffer; -+ CpaFlatBuffer bufferListArray[ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS]; -+ CpaBoolean verifyResult; -+}; -+ -+/* Create a new session between OCF and this driver*/ -+int icp_ocfDrvNewSession(icp_device_t dev, uint32_t * sild, -+ struct cryptoini *cri); -+ -+/* Free a session between this driver and the Quick Assist Framework*/ -+int icp_ocfDrvFreeLACSession(icp_device_t dev, uint64_t sid); -+ -+/* Defer freeing a Quick Assist session*/ -+void icp_ocfDrvDeferedFreeLacSessionProcess(void *arg); -+ -+/* Process OCF cryptographic request for a symmetric algorithm*/ -+int icp_ocfDrvSymProcess(icp_device_t dev, struct cryptop *crp, int hint); -+ -+/* Process OCF cryptographic request for an asymmetric algorithm*/ -+int icp_ocfDrvPkeProcess(icp_device_t dev, struct cryptkop *krp, int hint); -+ -+/* Populate a buffer with random data*/ -+int icp_ocfDrvReadRandom(void *arg, uint32_t * buf, int maxwords); -+ -+/* Retry Quick Assist session deregistration*/ -+int icp_ocfDrvDeregRetry(CpaCySymSessionCtx sessionToDeregister); -+ -+/* Convert an OS scatter gather list to a CPA buffer list*/ -+int icp_ocfDrvPacketBuffToBufferList(icp_packet_buffer_t * pPacketBuffer, -+ CpaBufferList * bufferList); -+ -+/* Convert a CPA buffer list to an OS scatter gather list*/ -+int icp_ocfDrvBufferListToPacketBuff(CpaBufferList * bufferList, -+ icp_packet_buffer_t ** pPacketBuffer); -+ -+/* Get the number of buffers in an OS scatter gather list*/ -+uint16_t icp_ocfDrvGetPacketBuffFrags(icp_packet_buffer_t * pPacketBuffer); -+ -+/* Convert a single OS buffer to a CPA Flat Buffer*/ -+void icp_ocfDrvSinglePacketBuffToFlatBuffer(icp_packet_buffer_t * pPacketBuffer, -+ CpaFlatBuffer * pFlatBuffer); -+ -+/* Add pointer and length to a CPA Flat Buffer structure*/ -+void icp_ocfDrvPtrAndLenToFlatBuffer(void *pData, uint32_t len, -+ CpaFlatBuffer * pFlatBuffer); -+ -+/* Convert pointer and length values to a CPA buffer list*/ -+void icp_ocfDrvPtrAndLenToBufferList(void *pDataIn, uint32_t length, -+ CpaBufferList * pBufferList); -+ -+/* Convert a CPA buffer list to pointer and length values*/ -+void icp_ocfDrvBufferListToPtrAndLen(CpaBufferList * pBufferList, -+ void **ppDataOut, uint32_t * pLength); -+ -+/* Set the number of flat buffers in bufferlist and the size of memory -+ to allocate for the pPrivateMetaData member of the CpaBufferList.*/ -+int icp_ocfDrvBufferListMemInfo(uint16_t numBuffers, -+ struct icp_drvBuffListInfo *buffListInfo); -+ -+/* Find pointer position of the digest within an OS scatter gather list*/ -+uint8_t *icp_ocfDrvPacketBufferDigestPointerFind(struct icp_drvOpData -+ *drvOpData, -+ int offsetInBytes, -+ uint32_t digestSizeInBytes); -+ -+/*This top level function is used to find a pointer to where a digest is -+ stored/needs to be inserted. */ -+uint8_t *icp_ocfDrvDigestPointerFind(struct icp_drvOpData *drvOpData, -+ struct cryptodesc *crp_desc); -+ -+/* Free a CPA flat buffer*/ -+void icp_ocfDrvFreeFlatBuffer(CpaFlatBuffer * pFlatBuffer); -+ -+/* This function will allocate memory for the pPrivateMetaData -+ member of CpaBufferList. */ -+int icp_ocfDrvAllocMetaData(CpaBufferList * pBufferList, -+ struct icp_drvOpData *pOpData); -+ -+/* Free data allocated for the pPrivateMetaData -+ member of CpaBufferList.*/ -+void icp_ocfDrvFreeMetaData(CpaBufferList * pBufferList); -+ -+#define ICP_CACHE_CREATE(cache_ID, cache_name) \ -+ icp_kmem_cache_create(cache_ID, sizeof(cache_name),ICP_KERNEL_CACHE_ALIGN,\ -+ ICP_KERNEL_CACHE_NOINIT) -+ -+#define ICP_CACHE_FREE(args...) \ -+ icp_kmem_cache_free (args) -+ -+#define ICP_CACHE_DESTROY(slab_zone)\ -+{\ -+ if(NULL != slab_zone){\ -+ icp_kmem_cache_destroy(slab_zone);\ -+ slab_zone = NULL;\ -+ }\ -+} -+ -+#endif -+/* ICP_OCF_H_ */ -diff -Nur linux-3.0.4.orig/crypto/ocf/ep80579/icp_sym.c linux-3.0.4/crypto/ocf/ep80579/icp_sym.c ---- linux-3.0.4.orig/crypto/ocf/ep80579/icp_sym.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/ep80579/icp_sym.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,1153 @@ -+/*************************************************************************** -+ * -+ * This file is provided under a dual BSD/GPLv2 license. When using or -+ * redistributing this file, you may do so under either license. -+ * -+ * GPL LICENSE SUMMARY -+ * -+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of version 2 of the GNU General Public License as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. -+ * The full GNU General Public License is included in this distribution -+ * in the file called LICENSE.GPL. -+ * -+ * Contact Information: -+ * Intel Corporation -+ * -+ * BSD LICENSE -+ * -+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * * Neither the name of Intel Corporation nor the names of its -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * -+ * version: Security.L.1.0.2-229 -+ * -+ ***************************************************************************/ -+/* -+ * An OCF module that uses the API for Intel® QuickAssist Technology to do the -+ * cryptography. -+ * -+ * This driver requires the ICP Access Library that is available from Intel in -+ * order to operate. -+ */ -+ -+#include "icp_ocf.h" -+ -+/*This is the call back function for all symmetric cryptographic processes. -+ Its main functionality is to free driver crypto operation structure and to -+ call back to OCF*/ -+static void -+icp_ocfDrvSymCallBack(void *callbackTag, -+ CpaStatus status, -+ const CpaCySymOp operationType, -+ void *pOpData, -+ CpaBufferList * pDstBuffer, CpaBoolean verifyResult); -+ -+/*This function is used to extract crypto processing information from the OCF -+ inputs, so as that it may be passed onto LAC*/ -+static int -+icp_ocfDrvProcessDataSetup(struct icp_drvOpData *drvOpData, -+ struct cryptodesc *crp_desc); -+ -+/*This function checks whether the crp_desc argument pertains to a digest or a -+ cipher operation*/ -+static int icp_ocfDrvAlgCheck(struct cryptodesc *crp_desc); -+ -+/*This function copies all the passed in session context information and stores -+ it in a LAC context structure*/ -+static int -+icp_ocfDrvAlgorithmSetup(struct cryptoini *cri, -+ CpaCySymSessionSetupData * lacSessCtx); -+ -+/*This function is used to free an OCF->OCF_DRV session object*/ -+static void icp_ocfDrvFreeOCFSession(struct icp_drvSessionData *sessionData); -+ -+/*max IOV buffs supported in a UIO structure*/ -+#define NUM_IOV_SUPPORTED (1) -+ -+/* Name : icp_ocfDrvSymCallBack -+ * -+ * Description : When this function returns it signifies that the LAC -+ * component has completed the relevant symmetric operation. -+ * -+ * Notes : The callbackTag is a pointer to an icp_drvOpData. This memory -+ * object was passed to LAC for the cryptographic processing and contains all -+ * the relevant information for cleaning up buffer handles etc. so that the -+ * OCF EP80579 Driver portion of this crypto operation can be fully completed. -+ */ -+static void -+icp_ocfDrvSymCallBack(void *callbackTag, -+ CpaStatus status, -+ const CpaCySymOp operationType, -+ void *pOpData, -+ CpaBufferList * pDstBuffer, CpaBoolean verifyResult) -+{ -+ struct cryptop *crp = NULL; -+ struct icp_drvOpData *temp_drvOpData = -+ (struct icp_drvOpData *)callbackTag; -+ uint64_t *tempBasePtr = NULL; -+ uint32_t tempLen = 0; -+ -+ if (NULL == temp_drvOpData) { -+ DPRINTK("%s(): The callback from the LAC component" -+ " has failed due to Null userOpaque data" -+ "(status == %d).\n", __FUNCTION__, status); -+ DPRINTK("%s(): Unable to call OCF back! \n", __FUNCTION__); -+ return; -+ } -+ -+ crp = temp_drvOpData->crp; -+ crp->crp_etype = ICP_OCF_DRV_NO_CRYPTO_PROCESS_ERROR; -+ -+ if (NULL == pOpData) { -+ DPRINTK("%s(): The callback from the LAC component" -+ " has failed due to Null Symmetric Op data" -+ "(status == %d).\n", __FUNCTION__, status); -+ crp->crp_etype = ECANCELED; -+ crypto_done(crp); -+ return; -+ } -+ -+ if (NULL == pDstBuffer) { -+ DPRINTK("%s(): The callback from the LAC component" -+ " has failed due to Null Dst Bufferlist data" -+ "(status == %d).\n", __FUNCTION__, status); -+ crp->crp_etype = ECANCELED; -+ crypto_done(crp); -+ return; -+ } -+ -+ if (CPA_STATUS_SUCCESS == status) { -+ -+ if (temp_drvOpData->bufferType == ICP_CRYPTO_F_PACKET_BUF) { -+ if (ICP_OCF_DRV_STATUS_SUCCESS != -+ icp_ocfDrvBufferListToPacketBuff(pDstBuffer, -+ (icp_packet_buffer_t -+ **) -+ & (crp->crp_buf))) { -+ EPRINTK("%s(): BufferList to SkBuff " -+ "conversion error.\n", __FUNCTION__); -+ crp->crp_etype = EPERM; -+ } -+ } else { -+ icp_ocfDrvBufferListToPtrAndLen(pDstBuffer, -+ (void **)&tempBasePtr, -+ &tempLen); -+ crp->crp_olen = (int)tempLen; -+ } -+ -+ } else { -+ DPRINTK("%s(): The callback from the LAC component has failed" -+ "(status == %d).\n", __FUNCTION__, status); -+ -+ crp->crp_etype = ECANCELED; -+ } -+ -+ if (temp_drvOpData->numBufferListArray > -+ ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) { -+ icp_kfree(pDstBuffer->pBuffers); -+ } -+ icp_ocfDrvFreeMetaData(pDstBuffer); -+ ICP_CACHE_FREE(drvOpData_zone, temp_drvOpData); -+ -+ /* Invoke the OCF callback function */ -+ crypto_done(crp); -+ -+ return; -+} -+ -+/* Name : icp_ocfDrvNewSession -+ * -+ * Description : This function will create a new Driver<->OCF session -+ * -+ * Notes : LAC session registration happens during the first perform call. -+ * That is the first time we know all information about a given session. -+ */ -+int icp_ocfDrvNewSession(icp_device_t dev, uint32_t * sid, -+ struct cryptoini *cri) -+{ -+ struct icp_drvSessionData *sessionData = NULL; -+ uint32_t delete_session = 0; -+ -+ /* The SID passed in should be our driver ID. We can return the */ -+ /* local ID (LID) which is a unique identifier which we can use */ -+ /* to differentiate between the encrypt/decrypt LAC session handles */ -+ if (NULL == sid) { -+ EPRINTK("%s(): Invalid input parameters - NULL sid.\n", -+ __FUNCTION__); -+ return EINVAL; -+ } -+ -+ if (NULL == cri) { -+ EPRINTK("%s(): Invalid input parameters - NULL cryptoini.\n", -+ __FUNCTION__); -+ return EINVAL; -+ } -+ -+ if (icp_ocfDrvDriverId != *sid) { -+ EPRINTK("%s(): Invalid input parameters - bad driver ID\n", -+ __FUNCTION__); -+ EPRINTK("\t sid = 0x08%p \n \t cri = 0x08%p \n", sid, cri); -+ return EINVAL; -+ } -+ -+ sessionData = icp_kmem_cache_zalloc(drvSessionData_zone, ICP_M_NOWAIT); -+ if (NULL == sessionData) { -+ DPRINTK("%s():No memory for Session Data\n", __FUNCTION__); -+ return ENOMEM; -+ } -+ -+ /*ENTER CRITICAL SECTION */ -+ icp_spin_lockbh_lock(&icp_ocfDrvSymSessInfoListSpinlock); -+ /*put this check in the spinlock so no new sessions can be added to the -+ linked list when we are exiting */ -+ if (CPA_TRUE == icp_atomic_read(&icp_ocfDrvIsExiting)) { -+ delete_session++; -+ -+ } else if (NO_OCF_TO_DRV_MAX_SESSIONS != max_sessions) { -+ if (icp_atomic_read(&num_ocf_to_drv_registered_sessions) >= -+ (max_sessions - -+ icp_atomic_read(&lac_session_failed_dereg_count))) { -+ delete_session++; -+ } else { -+ icp_atomic_inc(&num_ocf_to_drv_registered_sessions); -+ /* Add to session data linked list */ -+ ICP_LIST_ADD(sessionData, &icp_ocfDrvGlobalSymListHead, -+ listNode); -+ } -+ -+ } else if (NO_OCF_TO_DRV_MAX_SESSIONS == max_sessions) { -+ ICP_LIST_ADD(sessionData, &icp_ocfDrvGlobalSymListHead, -+ listNode); -+ } -+ -+ sessionData->inUse = ICP_SESSION_INITIALISED; -+ -+ /*EXIT CRITICAL SECTION */ -+ icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock); -+ -+ if (delete_session) { -+ DPRINTK("%s():No Session handles available\n", __FUNCTION__); -+ ICP_CACHE_FREE(drvSessionData_zone, sessionData); -+ return EPERM; -+ } -+ -+ if (ICP_OCF_DRV_STATUS_SUCCESS != -+ icp_ocfDrvAlgorithmSetup(cri, &(sessionData->lacSessCtx))) { -+ DPRINTK("%s():algorithm not supported\n", __FUNCTION__); -+ icp_ocfDrvFreeOCFSession(sessionData); -+ return EINVAL; -+ } -+ -+ if (cri->cri_next) { -+ if (cri->cri_next->cri_next != NULL) { -+ DPRINTK("%s():only two chained algorithms supported\n", -+ __FUNCTION__); -+ icp_ocfDrvFreeOCFSession(sessionData); -+ return EPERM; -+ } -+ -+ if (ICP_OCF_DRV_STATUS_SUCCESS != -+ icp_ocfDrvAlgorithmSetup(cri->cri_next, -+ &(sessionData->lacSessCtx))) { -+ DPRINTK("%s():second algorithm not supported\n", -+ __FUNCTION__); -+ icp_ocfDrvFreeOCFSession(sessionData); -+ return EINVAL; -+ } -+ -+ sessionData->lacSessCtx.symOperation = -+ CPA_CY_SYM_OP_ALGORITHM_CHAINING; -+ } -+ -+ *sid = (uint32_t) sessionData; -+ -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+} -+ -+/* Name : icp_ocfDrvAlgorithmSetup -+ * -+ * Description : This function builds the session context data from the -+ * information supplied through OCF. Algorithm chain order and whether the -+ * session is Encrypt/Decrypt can only be found out at perform time however, so -+ * the session is registered with LAC at that time. -+ */ -+static int -+icp_ocfDrvAlgorithmSetup(struct cryptoini *cri, -+ CpaCySymSessionSetupData * lacSessCtx) -+{ -+ -+ lacSessCtx->sessionPriority = CPA_CY_PRIORITY_NORMAL; -+ -+ switch (cri->cri_alg) { -+ -+ case CRYPTO_NULL_CBC: -+ DPRINTK("%s(): NULL CBC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; -+ lacSessCtx->cipherSetupData.cipherAlgorithm = -+ CPA_CY_SYM_CIPHER_NULL; -+ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; -+ break; -+ -+ case CRYPTO_DES_CBC: -+ DPRINTK("%s(): DES CBC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; -+ lacSessCtx->cipherSetupData.cipherAlgorithm = -+ CPA_CY_SYM_CIPHER_DES_CBC; -+ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; -+ break; -+ -+ case CRYPTO_3DES_CBC: -+ DPRINTK("%s(): 3DES CBC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; -+ lacSessCtx->cipherSetupData.cipherAlgorithm = -+ CPA_CY_SYM_CIPHER_3DES_CBC; -+ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; -+ break; -+ -+ case CRYPTO_AES_CBC: -+ DPRINTK("%s(): AES CBC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; -+ lacSessCtx->cipherSetupData.cipherAlgorithm = -+ CPA_CY_SYM_CIPHER_AES_CBC; -+ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; -+ break; -+ -+ case CRYPTO_ARC4: -+ DPRINTK("%s(): ARC4\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; -+ lacSessCtx->cipherSetupData.cipherAlgorithm = -+ CPA_CY_SYM_CIPHER_ARC4; -+ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; -+ break; -+ -+ case CRYPTO_SHA1: -+ DPRINTK("%s(): SHA1\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_SHA1; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_SHA1_DIGEST_SIZE_IN_BYTES); -+ -+ break; -+ -+ case CRYPTO_SHA1_HMAC: -+ DPRINTK("%s(): SHA1_HMAC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_SHA1; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_SHA1_DIGEST_SIZE_IN_BYTES); -+ lacSessCtx->hashSetupData.authModeSetupData.authKey = -+ cri->cri_key; -+ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; -+ -+ break; -+ -+ case CRYPTO_SHA2_256: -+ DPRINTK("%s(): SHA256\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = -+ CPA_CY_SYM_HASH_SHA256; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_SHA256_DIGEST_SIZE_IN_BYTES); -+ -+ break; -+ -+ case CRYPTO_SHA2_256_HMAC: -+ DPRINTK("%s(): SHA256_HMAC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = -+ CPA_CY_SYM_HASH_SHA256; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_SHA256_DIGEST_SIZE_IN_BYTES); -+ lacSessCtx->hashSetupData.authModeSetupData.authKey = -+ cri->cri_key; -+ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; -+ -+ break; -+ -+ case CRYPTO_SHA2_384: -+ DPRINTK("%s(): SHA384\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = -+ CPA_CY_SYM_HASH_SHA384; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_SHA384_DIGEST_SIZE_IN_BYTES); -+ -+ break; -+ -+ case CRYPTO_SHA2_384_HMAC: -+ DPRINTK("%s(): SHA384_HMAC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = -+ CPA_CY_SYM_HASH_SHA384; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_SHA384_DIGEST_SIZE_IN_BYTES); -+ lacSessCtx->hashSetupData.authModeSetupData.authKey = -+ cri->cri_key; -+ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; -+ -+ break; -+ -+ case CRYPTO_SHA2_512: -+ DPRINTK("%s(): SHA512\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = -+ CPA_CY_SYM_HASH_SHA512; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_SHA512_DIGEST_SIZE_IN_BYTES); -+ -+ break; -+ -+ case CRYPTO_SHA2_512_HMAC: -+ DPRINTK("%s(): SHA512_HMAC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = -+ CPA_CY_SYM_HASH_SHA512; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_SHA512_DIGEST_SIZE_IN_BYTES); -+ lacSessCtx->hashSetupData.authModeSetupData.authKey = -+ cri->cri_key; -+ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; -+ -+ break; -+ -+ case CRYPTO_MD5: -+ DPRINTK("%s(): MD5\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_MD5; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_MD5_DIGEST_SIZE_IN_BYTES); -+ -+ break; -+ -+ case CRYPTO_MD5_HMAC: -+ DPRINTK("%s(): MD5_HMAC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_MD5; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_MD5_DIGEST_SIZE_IN_BYTES); -+ lacSessCtx->hashSetupData.authModeSetupData.authKey = -+ cri->cri_key; -+ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; -+ -+ break; -+ -+ default: -+ DPRINTK("%s(): ALG Setup FAIL\n", __FUNCTION__); -+ return ICP_OCF_DRV_STATUS_FAIL; -+ } -+ -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+} -+ -+/* Name : icp_ocfDrvFreeOCFSession -+ * -+ * Description : This function deletes all existing Session data representing -+ * the Cryptographic session established between OCF and this driver. This -+ * also includes freeing the memory allocated for the session context. The -+ * session object is also removed from the session linked list. -+ */ -+static void icp_ocfDrvFreeOCFSession(struct icp_drvSessionData *sessionData) -+{ -+ -+ sessionData->inUse = ICP_SESSION_DEREGISTERED; -+ -+ /*ENTER CRITICAL SECTION */ -+ icp_spin_lockbh_lock(&icp_ocfDrvSymSessInfoListSpinlock); -+ -+ if (CPA_TRUE == icp_atomic_read(&icp_ocfDrvIsExiting)) { -+ /*If the Driver is exiting, allow that process to -+ handle any deletions */ -+ /*EXIT CRITICAL SECTION */ -+ icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock); -+ return; -+ } -+ -+ icp_atomic_dec(&num_ocf_to_drv_registered_sessions); -+ -+ ICP_LIST_DEL(sessionData, listNode); -+ -+ /*EXIT CRITICAL SECTION */ -+ icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock); -+ -+ if (NULL != sessionData->sessHandle) { -+ icp_kfree(sessionData->sessHandle); -+ } -+ ICP_CACHE_FREE(drvSessionData_zone, sessionData); -+} -+ -+/* Name : icp_ocfDrvFreeLACSession -+ * -+ * Description : This attempts to deregister a LAC session. If it fails, the -+ * deregistation retry function is called. -+ */ -+int icp_ocfDrvFreeLACSession(icp_device_t dev, uint64_t sid) -+{ -+ CpaCySymSessionCtx sessionToDeregister = NULL; -+ struct icp_drvSessionData *sessionData = NULL; -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ int retval = 0; -+ -+ sessionData = (struct icp_drvSessionData *)CRYPTO_SESID2LID(sid); -+ if (NULL == sessionData) { -+ EPRINTK("%s(): OCF Free session called with Null Session ID.\n", -+ __FUNCTION__); -+ return EINVAL; -+ } -+ -+ sessionToDeregister = sessionData->sessHandle; -+ -+ if ((ICP_SESSION_INITIALISED != sessionData->inUse) && -+ (ICP_SESSION_RUNNING != sessionData->inUse) && -+ (ICP_SESSION_DEREGISTERED != sessionData->inUse)) { -+ DPRINTK("%s() Session not initialised.\n", __FUNCTION__); -+ return EINVAL; -+ } -+ -+ if (ICP_SESSION_RUNNING == sessionData->inUse) { -+ lacStatus = cpaCySymRemoveSession(CPA_INSTANCE_HANDLE_SINGLE, -+ sessionToDeregister); -+ if (CPA_STATUS_RETRY == lacStatus) { -+ if (ICP_OCF_DRV_STATUS_SUCCESS != -+ icp_ocfDrvDeregRetry(&sessionToDeregister)) { -+ /* the retry function increments the -+ dereg failed count */ -+ DPRINTK("%s(): LAC failed to deregister the " -+ "session. (localSessionId= %p)\n", -+ __FUNCTION__, sessionToDeregister); -+ retval = EPERM; -+ } -+ -+ } else if (CPA_STATUS_SUCCESS != lacStatus) { -+ DPRINTK("%s(): LAC failed to deregister the session. " -+ "localSessionId= %p, lacStatus = %d\n", -+ __FUNCTION__, sessionToDeregister, lacStatus); -+ icp_atomic_inc(&lac_session_failed_dereg_count); -+ retval = EPERM; -+ } -+ } else { -+ DPRINTK("%s() Session not registered with LAC.\n", -+ __FUNCTION__); -+ } -+ -+ icp_ocfDrvFreeOCFSession(sessionData); -+ return retval; -+ -+} -+ -+/* Name : icp_ocfDrvAlgCheck -+ * -+ * Description : This function checks whether the cryptodesc argument pertains -+ * to a sym or hash function -+ */ -+static int icp_ocfDrvAlgCheck(struct cryptodesc *crp_desc) -+{ -+ -+ if (crp_desc->crd_alg == CRYPTO_3DES_CBC || -+ crp_desc->crd_alg == CRYPTO_AES_CBC || -+ crp_desc->crd_alg == CRYPTO_DES_CBC || -+ crp_desc->crd_alg == CRYPTO_NULL_CBC || -+ crp_desc->crd_alg == CRYPTO_ARC4) { -+ return ICP_OCF_DRV_ALG_CIPHER; -+ } -+ -+ return ICP_OCF_DRV_ALG_HASH; -+} -+ -+/* Name : icp_ocfDrvSymProcess -+ * -+ * Description : This function will map symmetric functionality calls from OCF -+ * to the LAC API. It will also allocate memory to store the session context. -+ * -+ * Notes: If it is the first perform call for a given session, then a LAC -+ * session is registered. After the session is registered, no checks as -+ * to whether session paramaters have changed (e.g. alg chain order) are -+ * done. -+ */ -+int icp_ocfDrvSymProcess(icp_device_t dev, struct cryptop *crp, int hint) -+{ -+ struct icp_drvSessionData *sessionData = NULL; -+ struct icp_drvOpData *drvOpData = NULL; -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ Cpa32U sessionCtxSizeInBytes = 0; -+ -+ if (NULL == crp) { -+ DPRINTK("%s(): Invalid input parameters, cryptop is NULL\n", -+ __FUNCTION__); -+ return EINVAL; -+ } -+ -+ if (NULL == crp->crp_desc) { -+ DPRINTK("%s(): Invalid input parameters, no crp_desc attached " -+ "to crp\n", __FUNCTION__); -+ crp->crp_etype = EINVAL; -+ return EINVAL; -+ } -+ -+ if (NULL == crp->crp_buf) { -+ DPRINTK("%s(): Invalid input parameters, no buffer attached " -+ "to crp\n", __FUNCTION__); -+ crp->crp_etype = EINVAL; -+ return EINVAL; -+ } -+ -+ if (CPA_TRUE == icp_atomic_read(&icp_ocfDrvIsExiting)) { -+ crp->crp_etype = EFAULT; -+ return EFAULT; -+ } -+ -+ sessionData = (struct icp_drvSessionData *) -+ (CRYPTO_SESID2LID(crp->crp_sid)); -+ if (NULL == sessionData) { -+ DPRINTK("%s(): Invalid input parameters, Null Session ID \n", -+ __FUNCTION__); -+ crp->crp_etype = EINVAL; -+ return EINVAL; -+ } -+ -+/*If we get a request against a deregisted session, cancel operation*/ -+ if (ICP_SESSION_DEREGISTERED == sessionData->inUse) { -+ DPRINTK("%s(): Session ID %d was deregistered \n", -+ __FUNCTION__, (int)(CRYPTO_SESID2LID(crp->crp_sid))); -+ crp->crp_etype = EFAULT; -+ return EFAULT; -+ } -+ -+/*If none of the session states are set, then the session structure was either -+ not initialised properly or we are reading from a freed memory area (possible -+ due to OCF batch mode not removing queued requests against deregistered -+ sessions*/ -+ if (ICP_SESSION_INITIALISED != sessionData->inUse && -+ ICP_SESSION_RUNNING != sessionData->inUse) { -+ DPRINTK("%s(): Session - ID %d - not properly initialised or " -+ "memory freed back to the kernel \n", -+ __FUNCTION__, (int)(CRYPTO_SESID2LID(crp->crp_sid))); -+ crp->crp_etype = EINVAL; -+ return EINVAL; -+ } -+ -+ /*For the below checks, remember error checking is already done in LAC. -+ We're not validating inputs subsequent to registration */ -+ if (sessionData->inUse == ICP_SESSION_INITIALISED) { -+ DPRINTK("%s(): Initialising session\n", __FUNCTION__); -+ -+ if (NULL != crp->crp_desc->crd_next) { -+ if (ICP_OCF_DRV_ALG_CIPHER == -+ icp_ocfDrvAlgCheck(crp->crp_desc)) { -+ -+ sessionData->lacSessCtx.algChainOrder = -+ CPA_CY_SYM_ALG_CHAIN_ORDER_CIPHER_THEN_HASH; -+ -+ if (crp->crp_desc->crd_flags & CRD_F_ENCRYPT) { -+ sessionData->lacSessCtx.cipherSetupData. -+ cipherDirection = -+ CPA_CY_SYM_CIPHER_DIRECTION_ENCRYPT; -+ } else { -+ sessionData->lacSessCtx.cipherSetupData. -+ cipherDirection = -+ CPA_CY_SYM_CIPHER_DIRECTION_DECRYPT; -+ } -+ } else { -+ sessionData->lacSessCtx.algChainOrder = -+ CPA_CY_SYM_ALG_CHAIN_ORDER_HASH_THEN_CIPHER; -+ -+ if (crp->crp_desc->crd_next->crd_flags & -+ CRD_F_ENCRYPT) { -+ sessionData->lacSessCtx.cipherSetupData. -+ cipherDirection = -+ CPA_CY_SYM_CIPHER_DIRECTION_ENCRYPT; -+ } else { -+ sessionData->lacSessCtx.cipherSetupData. -+ cipherDirection = -+ CPA_CY_SYM_CIPHER_DIRECTION_DECRYPT; -+ } -+ -+ } -+ -+ } else if (ICP_OCF_DRV_ALG_CIPHER == -+ icp_ocfDrvAlgCheck(crp->crp_desc)) { -+ if (crp->crp_desc->crd_flags & CRD_F_ENCRYPT) { -+ sessionData->lacSessCtx.cipherSetupData. -+ cipherDirection = -+ CPA_CY_SYM_CIPHER_DIRECTION_ENCRYPT; -+ } else { -+ sessionData->lacSessCtx.cipherSetupData. -+ cipherDirection = -+ CPA_CY_SYM_CIPHER_DIRECTION_DECRYPT; -+ } -+ -+ } -+ -+ /*No action required for standalone Auth here */ -+ -+ /* Allocate memory for SymSessionCtx before the Session Registration */ -+ lacStatus = -+ cpaCySymSessionCtxGetSize(CPA_INSTANCE_HANDLE_SINGLE, -+ &(sessionData->lacSessCtx), -+ &sessionCtxSizeInBytes); -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): cpaCySymSessionCtxGetSize failed - %d\n", -+ __FUNCTION__, lacStatus); -+ crp->crp_etype = EINVAL; -+ return EINVAL; -+ } -+ sessionData->sessHandle = -+ icp_kmalloc(sessionCtxSizeInBytes, ICP_M_NOWAIT); -+ if (NULL == sessionData->sessHandle) { -+ EPRINTK -+ ("%s(): Failed to get memory for SymSessionCtx\n", -+ __FUNCTION__); -+ crp->crp_etype = ENOMEM; -+ return ENOMEM; -+ } -+ -+ lacStatus = cpaCySymInitSession(CPA_INSTANCE_HANDLE_SINGLE, -+ icp_ocfDrvSymCallBack, -+ &(sessionData->lacSessCtx), -+ sessionData->sessHandle); -+ -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): cpaCySymInitSession failed -%d \n", -+ __FUNCTION__, lacStatus); -+ crp->crp_etype = EFAULT; -+ return EFAULT; -+ } -+ -+ sessionData->inUse = ICP_SESSION_RUNNING; -+ } -+ -+ drvOpData = icp_kmem_cache_zalloc(drvOpData_zone, ICP_M_NOWAIT); -+ if (NULL == drvOpData) { -+ EPRINTK("%s():Failed to get memory for drvOpData\n", -+ __FUNCTION__); -+ crp->crp_etype = ENOMEM; -+ return ENOMEM; -+ } -+ -+ drvOpData->lacOpData.pSessionCtx = sessionData->sessHandle; -+ drvOpData->digestSizeInBytes = sessionData->lacSessCtx.hashSetupData. -+ digestResultLenInBytes; -+ drvOpData->crp = crp; -+ -+ /* Set the default buffer list array memory allocation */ -+ drvOpData->srcBuffer.pBuffers = drvOpData->bufferListArray; -+ drvOpData->numBufferListArray = ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS; -+ -+ if (ICP_OCF_DRV_STATUS_SUCCESS != -+ icp_ocfDrvProcessDataSetup(drvOpData, drvOpData->crp->crp_desc)) { -+ crp->crp_etype = EINVAL; -+ goto err; -+ } -+ -+ if (drvOpData->crp->crp_desc->crd_next != NULL) { -+ if (icp_ocfDrvProcessDataSetup(drvOpData, drvOpData->crp-> -+ crp_desc->crd_next)) { -+ crp->crp_etype = EINVAL; -+ goto err; -+ } -+ -+ } -+ -+ /* -+ * Allocate buffer list array memory if the data fragment is more than -+ * the default number (ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) and not -+ * calculated already -+ */ -+ if (crp->crp_flags & ICP_CRYPTO_F_PACKET_BUF) { -+ if (NULL == drvOpData->lacOpData.pDigestResult) { -+ drvOpData->numBufferListArray = -+ icp_ocfDrvGetPacketBuffFrags((icp_packet_buffer_t *) -+ crp->crp_buf); -+ } -+ -+ if (ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS < -+ drvOpData->numBufferListArray) { -+ DPRINTK("%s() numBufferListArray more than default\n", -+ __FUNCTION__); -+ drvOpData->srcBuffer.pBuffers = NULL; -+ drvOpData->srcBuffer.pBuffers = -+ icp_kmalloc(drvOpData->numBufferListArray * -+ sizeof(CpaFlatBuffer), ICP_M_NOWAIT); -+ if (NULL == drvOpData->srcBuffer.pBuffers) { -+ EPRINTK("%s() Failed to get memory for " -+ "pBuffers\n", __FUNCTION__); -+ ICP_CACHE_FREE(drvOpData_zone, drvOpData); -+ crp->crp_etype = ENOMEM; -+ return ENOMEM; -+ } -+ } -+ } -+ -+ /* -+ * Check the type of buffer structure we got and convert it into -+ * CpaBufferList format. -+ */ -+ if (crp->crp_flags & ICP_CRYPTO_F_PACKET_BUF) { -+ if (ICP_OCF_DRV_STATUS_SUCCESS != -+ icp_ocfDrvPacketBuffToBufferList((icp_packet_buffer_t *) -+ crp->crp_buf, -+ &(drvOpData->srcBuffer))) { -+ EPRINTK("%s():Failed to translate from packet buffer " -+ "to bufferlist\n", __FUNCTION__); -+ crp->crp_etype = EINVAL; -+ goto err; -+ } -+ -+ drvOpData->bufferType = ICP_CRYPTO_F_PACKET_BUF; -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ /* OCF only supports IOV of one entry. */ -+ if (NUM_IOV_SUPPORTED == -+ ((struct uio *)(crp->crp_buf))->uio_iovcnt) { -+ -+ icp_ocfDrvPtrAndLenToBufferList(((struct uio *)(crp-> -+ crp_buf))-> -+ uio_iov[0].iov_base, -+ ((struct uio *)(crp-> -+ crp_buf))-> -+ uio_iov[0].iov_len, -+ &(drvOpData-> -+ srcBuffer)); -+ -+ drvOpData->bufferType = CRYPTO_F_IOV; -+ -+ } else { -+ DPRINTK("%s():Unable to handle IOVs with lengths of " -+ "greater than one!\n", __FUNCTION__); -+ crp->crp_etype = EINVAL; -+ goto err; -+ } -+ -+ } else { -+ icp_ocfDrvPtrAndLenToBufferList(crp->crp_buf, -+ crp->crp_ilen, -+ &(drvOpData->srcBuffer)); -+ -+ drvOpData->bufferType = CRYPTO_BUF_CONTIG; -+ } -+ -+ /* Allocate srcBuffer's private meta data */ -+ if (ICP_OCF_DRV_STATUS_SUCCESS != -+ icp_ocfDrvAllocMetaData(&(drvOpData->srcBuffer), drvOpData)) { -+ EPRINTK("%s() icp_ocfDrvAllocMetaData failed\n", __FUNCTION__); -+ memset(&(drvOpData->lacOpData), 0, sizeof(CpaCySymOpData)); -+ crp->crp_etype = EINVAL; -+ goto err; -+ } -+ -+ /* Perform "in-place" crypto operation */ -+ lacStatus = cpaCySymPerformOp(CPA_INSTANCE_HANDLE_SINGLE, -+ (void *)drvOpData, -+ &(drvOpData->lacOpData), -+ &(drvOpData->srcBuffer), -+ &(drvOpData->srcBuffer), -+ &(drvOpData->verifyResult)); -+ if (CPA_STATUS_RETRY == lacStatus) { -+ DPRINTK("%s(): cpaCySymPerformOp retry, lacStatus = %d\n", -+ __FUNCTION__, lacStatus); -+ memset(&(drvOpData->lacOpData), 0, sizeof(CpaCySymOpData)); -+ crp->crp_etype = ERESTART; -+ goto err; -+ } -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): cpaCySymPerformOp failed, lacStatus = %d\n", -+ __FUNCTION__, lacStatus); -+ memset(&(drvOpData->lacOpData), 0, sizeof(CpaCySymOpData)); -+ crp->crp_etype = EINVAL; -+ goto err; -+ } -+ -+ return 0; //OCF success status value -+ -+ err: -+ if (drvOpData->numBufferListArray > ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) { -+ icp_kfree(drvOpData->srcBuffer.pBuffers); -+ } -+ icp_ocfDrvFreeMetaData(&(drvOpData->srcBuffer)); -+ ICP_CACHE_FREE(drvOpData_zone, drvOpData); -+ -+ return crp->crp_etype; -+} -+ -+/* Name : icp_ocfDrvProcessDataSetup -+ * -+ * Description : This function will setup all the cryptographic operation data -+ * that is required by LAC to execute the operation. -+ */ -+static int icp_ocfDrvProcessDataSetup(struct icp_drvOpData *drvOpData, -+ struct cryptodesc *crp_desc) -+{ -+ CpaCyRandGenOpData randGenOpData; -+ CpaFlatBuffer randData; -+ -+ drvOpData->lacOpData.packetType = CPA_CY_SYM_PACKET_TYPE_FULL; -+ -+ /* Convert from the cryptop to the ICP LAC crypto parameters */ -+ switch (crp_desc->crd_alg) { -+ case CRYPTO_NULL_CBC: -+ drvOpData->lacOpData. -+ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; -+ drvOpData->lacOpData. -+ messageLenToCipherInBytes = crp_desc->crd_len; -+ drvOpData->verifyResult = CPA_FALSE; -+ drvOpData->lacOpData.ivLenInBytes = NULL_BLOCK_LEN; -+ break; -+ case CRYPTO_DES_CBC: -+ drvOpData->lacOpData. -+ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; -+ drvOpData->lacOpData. -+ messageLenToCipherInBytes = crp_desc->crd_len; -+ drvOpData->verifyResult = CPA_FALSE; -+ drvOpData->lacOpData.ivLenInBytes = DES_BLOCK_LEN; -+ break; -+ case CRYPTO_3DES_CBC: -+ drvOpData->lacOpData. -+ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; -+ drvOpData->lacOpData. -+ messageLenToCipherInBytes = crp_desc->crd_len; -+ drvOpData->verifyResult = CPA_FALSE; -+ drvOpData->lacOpData.ivLenInBytes = DES3_BLOCK_LEN; -+ break; -+ case CRYPTO_ARC4: -+ drvOpData->lacOpData. -+ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; -+ drvOpData->lacOpData. -+ messageLenToCipherInBytes = crp_desc->crd_len; -+ drvOpData->verifyResult = CPA_FALSE; -+ drvOpData->lacOpData.ivLenInBytes = ARC4_COUNTER_LEN; -+ break; -+ case CRYPTO_AES_CBC: -+ drvOpData->lacOpData. -+ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; -+ drvOpData->lacOpData. -+ messageLenToCipherInBytes = crp_desc->crd_len; -+ drvOpData->verifyResult = CPA_FALSE; -+ drvOpData->lacOpData.ivLenInBytes = RIJNDAEL128_BLOCK_LEN; -+ break; -+ case CRYPTO_SHA1: -+ case CRYPTO_SHA1_HMAC: -+ case CRYPTO_SHA2_256: -+ case CRYPTO_SHA2_256_HMAC: -+ case CRYPTO_SHA2_384: -+ case CRYPTO_SHA2_384_HMAC: -+ case CRYPTO_SHA2_512: -+ case CRYPTO_SHA2_512_HMAC: -+ case CRYPTO_MD5: -+ case CRYPTO_MD5_HMAC: -+ drvOpData->lacOpData. -+ hashStartSrcOffsetInBytes = crp_desc->crd_skip; -+ drvOpData->lacOpData. -+ messageLenToHashInBytes = crp_desc->crd_len; -+ drvOpData->lacOpData. -+ pDigestResult = -+ icp_ocfDrvDigestPointerFind(drvOpData, crp_desc); -+ -+ if (NULL == drvOpData->lacOpData.pDigestResult) { -+ DPRINTK("%s(): ERROR - could not calculate " -+ "Digest Result memory address\n", __FUNCTION__); -+ return ICP_OCF_DRV_STATUS_FAIL; -+ } -+ -+ drvOpData->lacOpData.digestVerify = CPA_FALSE; -+ break; -+ default: -+ DPRINTK("%s(): Crypto process error - algorithm not " -+ "found \n", __FUNCTION__); -+ return ICP_OCF_DRV_STATUS_FAIL; -+ } -+ -+ /* Figure out what the IV is supposed to be */ -+ if ((crp_desc->crd_alg == CRYPTO_DES_CBC) || -+ (crp_desc->crd_alg == CRYPTO_3DES_CBC) || -+ (crp_desc->crd_alg == CRYPTO_AES_CBC)) { -+ /*ARC4 doesn't use an IV */ -+ if (crp_desc->crd_flags & CRD_F_IV_EXPLICIT) { -+ /* Explicit IV provided to OCF */ -+ drvOpData->lacOpData.pIv = crp_desc->crd_iv; -+ } else { -+ /* IV is not explicitly provided to OCF */ -+ -+ /* Point the LAC OP Data IV pointer to our allocated -+ storage location for this session. */ -+ drvOpData->lacOpData.pIv = drvOpData->ivData; -+ -+ if ((crp_desc->crd_flags & CRD_F_ENCRYPT) && -+ ((crp_desc->crd_flags & CRD_F_IV_PRESENT) == 0)) { -+ -+ /* Encrypting - need to create IV */ -+ randGenOpData.generateBits = CPA_TRUE; -+ randGenOpData.lenInBytes = MAX_IV_LEN_IN_BYTES; -+ -+ icp_ocfDrvPtrAndLenToFlatBuffer((Cpa8U *) -+ drvOpData-> -+ ivData, -+ MAX_IV_LEN_IN_BYTES, -+ &randData); -+ -+ if (CPA_STATUS_SUCCESS != -+ cpaCyRandGen(CPA_INSTANCE_HANDLE_SINGLE, -+ NULL, NULL, -+ &randGenOpData, &randData)) { -+ DPRINTK("%s(): ERROR - Failed to" -+ " generate" -+ " Initialisation Vector\n", -+ __FUNCTION__); -+ return ICP_OCF_DRV_STATUS_FAIL; -+ } -+ -+ crypto_copyback(drvOpData->crp-> -+ crp_flags, -+ drvOpData->crp->crp_buf, -+ crp_desc->crd_inject, -+ drvOpData->lacOpData. -+ ivLenInBytes, -+ (caddr_t) (drvOpData->lacOpData. -+ pIv)); -+ } else { -+ /* Reading IV from buffer */ -+ crypto_copydata(drvOpData->crp-> -+ crp_flags, -+ drvOpData->crp->crp_buf, -+ crp_desc->crd_inject, -+ drvOpData->lacOpData. -+ ivLenInBytes, -+ (caddr_t) (drvOpData->lacOpData. -+ pIv)); -+ } -+ -+ } -+ -+ } -+ -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+} -+ -+/* Name : icp_ocfDrvDigestPointerFind -+ * -+ * Description : This function is used to find the memory address of where the -+ * digest information shall be stored in. Input buffer types are an skbuff, iov -+ * or flat buffer. The address is found using the buffer data start address and -+ * an offset. -+ * -+ * Note: In the case of a linux skbuff, the digest address may exist within -+ * a memory space linked to from the start buffer. These linked memory spaces -+ * must be traversed by the data length offset in order to find the digest start -+ * address. Whether there is enough space for the digest must also be checked. -+ */ -+uint8_t *icp_ocfDrvDigestPointerFind(struct icp_drvOpData * drvOpData, -+ struct cryptodesc * crp_desc) -+{ -+ -+ int offsetInBytes = crp_desc->crd_inject; -+ uint32_t digestSizeInBytes = drvOpData->digestSizeInBytes; -+ uint8_t *flat_buffer_base = NULL; -+ int flat_buffer_length = 0; -+ -+ if (drvOpData->crp->crp_flags & ICP_CRYPTO_F_PACKET_BUF) { -+ -+ return icp_ocfDrvPacketBufferDigestPointerFind(drvOpData, -+ offsetInBytes, -+ digestSizeInBytes); -+ -+ } else { -+ /* IOV or flat buffer */ -+ if (drvOpData->crp->crp_flags & CRYPTO_F_IOV) { -+ /*single IOV check has already been done */ -+ flat_buffer_base = ((struct uio *) -+ (drvOpData->crp->crp_buf))-> -+ uio_iov[0].iov_base; -+ flat_buffer_length = ((struct uio *) -+ (drvOpData->crp->crp_buf))-> -+ uio_iov[0].iov_len; -+ } else { -+ flat_buffer_base = (uint8_t *) drvOpData->crp->crp_buf; -+ flat_buffer_length = drvOpData->crp->crp_ilen; -+ } -+ -+ if (flat_buffer_length < (offsetInBytes + digestSizeInBytes)) { -+ DPRINTK("%s() Not enough space for Digest " -+ "(IOV/Flat Buffer) \n", __FUNCTION__); -+ return NULL; -+ } else { -+ return (uint8_t *) (flat_buffer_base + offsetInBytes); -+ } -+ } -+ DPRINTK("%s() Should not reach this point\n", __FUNCTION__); -+ return NULL; -+} -diff -Nur linux-3.0.4.orig/crypto/ocf/ep80579/linux_2.6_kernel_space.mk linux-3.0.4/crypto/ocf/ep80579/linux_2.6_kernel_space.mk ---- linux-3.0.4.orig/crypto/ocf/ep80579/linux_2.6_kernel_space.mk 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/ep80579/linux_2.6_kernel_space.mk 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,69 @@ -+################### -+# @par -+# This file is provided under a dual BSD/GPLv2 license. When using or -+# redistributing this file, you may do so under either license. -+# -+# GPL LICENSE SUMMARY -+# -+# Copyright(c) 2007,2008 Intel Corporation. All rights reserved. -+# -+# This program is free software; you can redistribute it and/or modify -+# it under the terms of version 2 of the GNU General Public License as -+# published by the Free Software Foundation. -+# -+# This program is distributed in the hope that it will be useful, but -+# WITHOUT ANY WARRANTY; without even the implied warranty of -+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+# General Public License for more details. -+# -+# You should have received a copy of the GNU General Public License -+# along with this program; if not, write to the Free Software -+# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. -+# The full GNU General Public License is included in this distribution -+# in the file called LICENSE.GPL. -+# -+# Contact Information: -+# Intel Corporation -+# -+# BSD LICENSE -+# -+# Copyright(c) 2007,2008 Intel Corporation. All rights reserved. -+# All rights reserved. -+# -+# Redistribution and use in source and binary forms, with or without -+# modification, are permitted provided that the following conditions -+# are met: -+# -+# * Redistributions of source code must retain the above copyright -+# notice, this list of conditions and the following disclaimer. -+# * Redistributions in binary form must reproduce the above copyright -+# notice, this list of conditions and the following disclaimer in -+# the documentation and/or other materials provided with the -+# distribution. -+# * Neither the name of Intel Corporation nor the names of its -+# contributors may be used to endorse or promote products derived -+# from this software without specific prior written permission. -+# -+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+# -+# -+# version: Security.L.1.0.130 -+################### -+ -+#specific include directories in kernel space -+INCLUDES+=#e.g. -I$(OSAL_DIR)/include \ -+ -+#Extra Flags Specific in kernel space e.g. include path or debug flags etc. e.g to add an include path EXTRA_CFLAGS += -I$(src)/../include -+EXTRA_CFLAGS += $(INCLUDES) -O2 -Wall -+EXTRA_LDFLAGS +=-whole-archive -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/hifn/Makefile linux-3.0.4/crypto/ocf/hifn/Makefile ---- linux-3.0.4.orig/crypto/ocf/hifn/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/hifn/Makefile 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,13 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+obj-$(CONFIG_OCF_HIFN) += hifn7751.o -+obj-$(CONFIG_OCF_HIFNHIPP) += hifnHIPP.o -+ -+obj ?= . -+EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/hifn/hifn7751.c linux-3.0.4/crypto/ocf/hifn/hifn7751.c ---- linux-3.0.4.orig/crypto/ocf/hifn/hifn7751.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/hifn/hifn7751.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,2954 @@ -+/* $OpenBSD: hifn7751.c,v 1.120 2002/05/17 00:33:34 deraadt Exp $ */ -+ -+/*- -+ * Invertex AEON / Hifn 7751 driver -+ * Copyright (c) 1999 Invertex Inc. All rights reserved. -+ * Copyright (c) 1999 Theo de Raadt -+ * Copyright (c) 2000-2001 Network Security Technologies, Inc. -+ * http://www.netsec.net -+ * Copyright (c) 2003 Hifn Inc. -+ * -+ * This driver is based on a previous driver by Invertex, for which they -+ * requested: Please send any comments, feedback, bug-fixes, or feature -+ * requests to software@invertex.com. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored in part by the Defense Advanced Research Projects -+ * Agency (DARPA) and Air Force Research Laboratory, Air Force -+ * Materiel Command, USAF, under agreement number F30602-01-2-0537. -+ * -+ * -+__FBSDID("$FreeBSD: src/sys/dev/hifn/hifn7751.c,v 1.40 2007/03/21 03:42:49 sam Exp $"); -+ */ -+ -+/* -+ * Driver for various Hifn encryption processors. -+ */ -+#include -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+ -+#if 1 -+#define DPRINTF(a...) if (hifn_debug) { \ -+ printk("%s: ", sc ? \ -+ device_get_nameunit(sc->sc_dev) : "hifn"); \ -+ printk(a); \ -+ } else -+#else -+#define DPRINTF(a...) -+#endif -+ -+static inline int -+pci_get_revid(struct pci_dev *dev) -+{ -+ u8 rid = 0; -+ pci_read_config_byte(dev, PCI_REVISION_ID, &rid); -+ return rid; -+} -+ -+static struct hifn_stats hifnstats; -+ -+#define debug hifn_debug -+int hifn_debug = 0; -+module_param(hifn_debug, int, 0644); -+MODULE_PARM_DESC(hifn_debug, "Enable debug"); -+ -+int hifn_maxbatch = 1; -+module_param(hifn_maxbatch, int, 0644); -+MODULE_PARM_DESC(hifn_maxbatch, "max ops to batch w/o interrupt"); -+ -+int hifn_cache_linesize = 0x10; -+module_param(hifn_cache_linesize, int, 0444); -+MODULE_PARM_DESC(hifn_cache_linesize, "PCI config cache line size"); -+ -+#ifdef MODULE_PARM -+char *hifn_pllconfig = NULL; -+MODULE_PARM(hifn_pllconfig, "s"); -+#else -+char hifn_pllconfig[32]; /* This setting is RO after loading */ -+module_param_string(hifn_pllconfig, hifn_pllconfig, 32, 0444); -+#endif -+MODULE_PARM_DESC(hifn_pllconfig, "PLL config, ie., pci66, ext33, ..."); -+ -+#ifdef HIFN_VULCANDEV -+#include -+#include -+ -+static struct cdevsw vulcanpk_cdevsw; /* forward declaration */ -+#endif -+ -+/* -+ * Prototypes and count for the pci_device structure -+ */ -+static int hifn_probe(struct pci_dev *dev, const struct pci_device_id *ent); -+static void hifn_remove(struct pci_dev *dev); -+ -+static int hifn_newsession(device_t, u_int32_t *, struct cryptoini *); -+static int hifn_freesession(device_t, u_int64_t); -+static int hifn_process(device_t, struct cryptop *, int); -+ -+static device_method_t hifn_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, hifn_newsession), -+ DEVMETHOD(cryptodev_freesession,hifn_freesession), -+ DEVMETHOD(cryptodev_process, hifn_process), -+}; -+ -+static void hifn_reset_board(struct hifn_softc *, int); -+static void hifn_reset_puc(struct hifn_softc *); -+static void hifn_puc_wait(struct hifn_softc *); -+static int hifn_enable_crypto(struct hifn_softc *); -+static void hifn_set_retry(struct hifn_softc *sc); -+static void hifn_init_dma(struct hifn_softc *); -+static void hifn_init_pci_registers(struct hifn_softc *); -+static int hifn_sramsize(struct hifn_softc *); -+static int hifn_dramsize(struct hifn_softc *); -+static int hifn_ramtype(struct hifn_softc *); -+static void hifn_sessions(struct hifn_softc *); -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) -+static irqreturn_t hifn_intr(int irq, void *arg); -+#else -+static irqreturn_t hifn_intr(int irq, void *arg, struct pt_regs *regs); -+#endif -+static u_int hifn_write_command(struct hifn_command *, u_int8_t *); -+static u_int32_t hifn_next_signature(u_int32_t a, u_int cnt); -+static void hifn_callback(struct hifn_softc *, struct hifn_command *, u_int8_t *); -+static int hifn_crypto(struct hifn_softc *, struct hifn_command *, struct cryptop *, int); -+static int hifn_readramaddr(struct hifn_softc *, int, u_int8_t *); -+static int hifn_writeramaddr(struct hifn_softc *, int, u_int8_t *); -+static int hifn_dmamap_load_src(struct hifn_softc *, struct hifn_command *); -+static int hifn_dmamap_load_dst(struct hifn_softc *, struct hifn_command *); -+static int hifn_init_pubrng(struct hifn_softc *); -+static void hifn_tick(unsigned long arg); -+static void hifn_abort(struct hifn_softc *); -+static void hifn_alloc_slot(struct hifn_softc *, int *, int *, int *, int *); -+ -+static void hifn_write_reg_0(struct hifn_softc *, bus_size_t, u_int32_t); -+static void hifn_write_reg_1(struct hifn_softc *, bus_size_t, u_int32_t); -+ -+#ifdef CONFIG_OCF_RANDOMHARVEST -+static int hifn_read_random(void *arg, u_int32_t *buf, int len); -+#endif -+ -+#define HIFN_MAX_CHIPS 8 -+static struct hifn_softc *hifn_chip_idx[HIFN_MAX_CHIPS]; -+ -+static __inline u_int32_t -+READ_REG_0(struct hifn_softc *sc, bus_size_t reg) -+{ -+ u_int32_t v = readl(sc->sc_bar0 + reg); -+ sc->sc_bar0_lastreg = (bus_size_t) -1; -+ return (v); -+} -+#define WRITE_REG_0(sc, reg, val) hifn_write_reg_0(sc, reg, val) -+ -+static __inline u_int32_t -+READ_REG_1(struct hifn_softc *sc, bus_size_t reg) -+{ -+ u_int32_t v = readl(sc->sc_bar1 + reg); -+ sc->sc_bar1_lastreg = (bus_size_t) -1; -+ return (v); -+} -+#define WRITE_REG_1(sc, reg, val) hifn_write_reg_1(sc, reg, val) -+ -+/* -+ * map in a given buffer (great on some arches :-) -+ */ -+ -+static int -+pci_map_uio(struct hifn_softc *sc, struct hifn_operand *buf, struct uio *uio) -+{ -+ struct iovec *iov = uio->uio_iov; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ buf->mapsize = 0; -+ for (buf->nsegs = 0; buf->nsegs < uio->uio_iovcnt; ) { -+ buf->segs[buf->nsegs].ds_addr = pci_map_single(sc->sc_pcidev, -+ iov->iov_base, iov->iov_len, -+ PCI_DMA_BIDIRECTIONAL); -+ buf->segs[buf->nsegs].ds_len = iov->iov_len; -+ buf->mapsize += iov->iov_len; -+ iov++; -+ buf->nsegs++; -+ } -+ /* identify this buffer by the first segment */ -+ buf->map = (void *) buf->segs[0].ds_addr; -+ return(0); -+} -+ -+/* -+ * map in a given sk_buff -+ */ -+ -+static int -+pci_map_skb(struct hifn_softc *sc,struct hifn_operand *buf,struct sk_buff *skb) -+{ -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ buf->mapsize = 0; -+ -+ buf->segs[0].ds_addr = pci_map_single(sc->sc_pcidev, -+ skb->data, skb_headlen(skb), PCI_DMA_BIDIRECTIONAL); -+ buf->segs[0].ds_len = skb_headlen(skb); -+ buf->mapsize += buf->segs[0].ds_len; -+ -+ buf->nsegs = 1; -+ -+ for (i = 0; i < skb_shinfo(skb)->nr_frags; ) { -+ buf->segs[buf->nsegs].ds_len = skb_shinfo(skb)->frags[i].size; -+ buf->segs[buf->nsegs].ds_addr = pci_map_single(sc->sc_pcidev, -+ page_address(skb_shinfo(skb)->frags[i].page) + -+ skb_shinfo(skb)->frags[i].page_offset, -+ buf->segs[buf->nsegs].ds_len, PCI_DMA_BIDIRECTIONAL); -+ buf->mapsize += buf->segs[buf->nsegs].ds_len; -+ buf->nsegs++; -+ } -+ -+ /* identify this buffer by the first segment */ -+ buf->map = (void *) buf->segs[0].ds_addr; -+ return(0); -+} -+ -+/* -+ * map in a given contiguous buffer -+ */ -+ -+static int -+pci_map_buf(struct hifn_softc *sc,struct hifn_operand *buf, void *b, int len) -+{ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ buf->mapsize = 0; -+ buf->segs[0].ds_addr = pci_map_single(sc->sc_pcidev, -+ b, len, PCI_DMA_BIDIRECTIONAL); -+ buf->segs[0].ds_len = len; -+ buf->mapsize += buf->segs[0].ds_len; -+ buf->nsegs = 1; -+ -+ /* identify this buffer by the first segment */ -+ buf->map = (void *) buf->segs[0].ds_addr; -+ return(0); -+} -+ -+#if 0 /* not needed at this time */ -+static void -+pci_sync_iov(struct hifn_softc *sc, struct hifn_operand *buf) -+{ -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ for (i = 0; i < buf->nsegs; i++) -+ pci_dma_sync_single_for_cpu(sc->sc_pcidev, buf->segs[i].ds_addr, -+ buf->segs[i].ds_len, PCI_DMA_BIDIRECTIONAL); -+} -+#endif -+ -+static void -+pci_unmap_buf(struct hifn_softc *sc, struct hifn_operand *buf) -+{ -+ int i; -+ DPRINTF("%s()\n", __FUNCTION__); -+ for (i = 0; i < buf->nsegs; i++) { -+ pci_unmap_single(sc->sc_pcidev, buf->segs[i].ds_addr, -+ buf->segs[i].ds_len, PCI_DMA_BIDIRECTIONAL); -+ buf->segs[i].ds_addr = 0; -+ buf->segs[i].ds_len = 0; -+ } -+ buf->nsegs = 0; -+ buf->mapsize = 0; -+ buf->map = 0; -+} -+ -+static const char* -+hifn_partname(struct hifn_softc *sc) -+{ -+ /* XXX sprintf numbers when not decoded */ -+ switch (pci_get_vendor(sc->sc_pcidev)) { -+ case PCI_VENDOR_HIFN: -+ switch (pci_get_device(sc->sc_pcidev)) { -+ case PCI_PRODUCT_HIFN_6500: return "Hifn 6500"; -+ case PCI_PRODUCT_HIFN_7751: return "Hifn 7751"; -+ case PCI_PRODUCT_HIFN_7811: return "Hifn 7811"; -+ case PCI_PRODUCT_HIFN_7951: return "Hifn 7951"; -+ case PCI_PRODUCT_HIFN_7955: return "Hifn 7955"; -+ case PCI_PRODUCT_HIFN_7956: return "Hifn 7956"; -+ } -+ return "Hifn unknown-part"; -+ case PCI_VENDOR_INVERTEX: -+ switch (pci_get_device(sc->sc_pcidev)) { -+ case PCI_PRODUCT_INVERTEX_AEON: return "Invertex AEON"; -+ } -+ return "Invertex unknown-part"; -+ case PCI_VENDOR_NETSEC: -+ switch (pci_get_device(sc->sc_pcidev)) { -+ case PCI_PRODUCT_NETSEC_7751: return "NetSec 7751"; -+ } -+ return "NetSec unknown-part"; -+ } -+ return "Unknown-vendor unknown-part"; -+} -+ -+static u_int -+checkmaxmin(struct pci_dev *dev, const char *what, u_int v, u_int min, u_int max) -+{ -+ struct hifn_softc *sc = pci_get_drvdata(dev); -+ if (v > max) { -+ device_printf(sc->sc_dev, "Warning, %s %u out of range, " -+ "using max %u\n", what, v, max); -+ v = max; -+ } else if (v < min) { -+ device_printf(sc->sc_dev, "Warning, %s %u out of range, " -+ "using min %u\n", what, v, min); -+ v = min; -+ } -+ return v; -+} -+ -+/* -+ * Select PLL configuration for 795x parts. This is complicated in -+ * that we cannot determine the optimal parameters without user input. -+ * The reference clock is derived from an external clock through a -+ * multiplier. The external clock is either the host bus (i.e. PCI) -+ * or an external clock generator. When using the PCI bus we assume -+ * the clock is either 33 or 66 MHz; for an external source we cannot -+ * tell the speed. -+ * -+ * PLL configuration is done with a string: "pci" for PCI bus, or "ext" -+ * for an external source, followed by the frequency. We calculate -+ * the appropriate multiplier and PLL register contents accordingly. -+ * When no configuration is given we default to "pci66" since that -+ * always will allow the card to work. If a card is using the PCI -+ * bus clock and in a 33MHz slot then it will be operating at half -+ * speed until the correct information is provided. -+ * -+ * We use a default setting of "ext66" because according to Mike Ham -+ * of HiFn, almost every board in existence has an external crystal -+ * populated at 66Mhz. Using PCI can be a problem on modern motherboards, -+ * because PCI33 can have clocks from 0 to 33Mhz, and some have -+ * non-PCI-compliant spread-spectrum clocks, which can confuse the pll. -+ */ -+static void -+hifn_getpllconfig(struct pci_dev *dev, u_int *pll) -+{ -+ const char *pllspec = hifn_pllconfig; -+ u_int freq, mul, fl, fh; -+ u_int32_t pllconfig; -+ char *nxt; -+ -+ if (pllspec == NULL) -+ pllspec = "ext66"; -+ fl = 33, fh = 66; -+ pllconfig = 0; -+ if (strncmp(pllspec, "ext", 3) == 0) { -+ pllspec += 3; -+ pllconfig |= HIFN_PLL_REF_SEL; -+ switch (pci_get_device(dev)) { -+ case PCI_PRODUCT_HIFN_7955: -+ case PCI_PRODUCT_HIFN_7956: -+ fl = 20, fh = 100; -+ break; -+#ifdef notyet -+ case PCI_PRODUCT_HIFN_7954: -+ fl = 20, fh = 66; -+ break; -+#endif -+ } -+ } else if (strncmp(pllspec, "pci", 3) == 0) -+ pllspec += 3; -+ freq = strtoul(pllspec, &nxt, 10); -+ if (nxt == pllspec) -+ freq = 66; -+ else -+ freq = checkmaxmin(dev, "frequency", freq, fl, fh); -+ /* -+ * Calculate multiplier. We target a Fck of 266 MHz, -+ * allowing only even values, possibly rounded down. -+ * Multipliers > 8 must set the charge pump current. -+ */ -+ mul = checkmaxmin(dev, "PLL divisor", (266 / freq) &~ 1, 2, 12); -+ pllconfig |= (mul / 2 - 1) << HIFN_PLL_ND_SHIFT; -+ if (mul > 8) -+ pllconfig |= HIFN_PLL_IS; -+ *pll = pllconfig; -+} -+ -+/* -+ * Attach an interface that successfully probed. -+ */ -+static int -+hifn_probe(struct pci_dev *dev, const struct pci_device_id *ent) -+{ -+ struct hifn_softc *sc = NULL; -+ char rbase; -+ u_int16_t ena, rev; -+ int rseg, rc; -+ unsigned long mem_start, mem_len; -+ static int num_chips = 0; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (pci_enable_device(dev) < 0) -+ return(-ENODEV); -+ -+ if (pci_set_mwi(dev)) -+ return(-ENODEV); -+ -+ if (!dev->irq) { -+ printk("hifn: found device with no IRQ assigned. check BIOS settings!"); -+ pci_disable_device(dev); -+ return(-ENODEV); -+ } -+ -+ sc = (struct hifn_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); -+ if (!sc) -+ return(-ENOMEM); -+ memset(sc, 0, sizeof(*sc)); -+ -+ softc_device_init(sc, "hifn", num_chips, hifn_methods); -+ -+ sc->sc_pcidev = dev; -+ sc->sc_irq = -1; -+ sc->sc_cid = -1; -+ sc->sc_num = num_chips++; -+ if (sc->sc_num < HIFN_MAX_CHIPS) -+ hifn_chip_idx[sc->sc_num] = sc; -+ -+ pci_set_drvdata(sc->sc_pcidev, sc); -+ -+ spin_lock_init(&sc->sc_mtx); -+ -+ /* XXX handle power management */ -+ -+ /* -+ * The 7951 and 795x have a random number generator and -+ * public key support; note this. -+ */ -+ if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && -+ (pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 || -+ pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 || -+ pci_get_device(dev) == PCI_PRODUCT_HIFN_7956)) -+ sc->sc_flags = HIFN_HAS_RNG | HIFN_HAS_PUBLIC; -+ /* -+ * The 7811 has a random number generator and -+ * we also note it's identity 'cuz of some quirks. -+ */ -+ if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && -+ pci_get_device(dev) == PCI_PRODUCT_HIFN_7811) -+ sc->sc_flags |= HIFN_IS_7811 | HIFN_HAS_RNG; -+ -+ /* -+ * The 795x parts support AES. -+ */ -+ if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && -+ (pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 || -+ pci_get_device(dev) == PCI_PRODUCT_HIFN_7956)) { -+ sc->sc_flags |= HIFN_IS_7956 | HIFN_HAS_AES; -+ /* -+ * Select PLL configuration. This depends on the -+ * bus and board design and must be manually configured -+ * if the default setting is unacceptable. -+ */ -+ hifn_getpllconfig(dev, &sc->sc_pllconfig); -+ } -+ -+ /* -+ * Setup PCI resources. Note that we record the bus -+ * tag and handle for each register mapping, this is -+ * used by the READ_REG_0, WRITE_REG_0, READ_REG_1, -+ * and WRITE_REG_1 macros throughout the driver. -+ */ -+ mem_start = pci_resource_start(sc->sc_pcidev, 0); -+ mem_len = pci_resource_len(sc->sc_pcidev, 0); -+ sc->sc_bar0 = (ocf_iomem_t) ioremap(mem_start, mem_len); -+ if (!sc->sc_bar0) { -+ device_printf(sc->sc_dev, "cannot map bar%d register space\n", 0); -+ goto fail; -+ } -+ sc->sc_bar0_lastreg = (bus_size_t) -1; -+ -+ mem_start = pci_resource_start(sc->sc_pcidev, 1); -+ mem_len = pci_resource_len(sc->sc_pcidev, 1); -+ sc->sc_bar1 = (ocf_iomem_t) ioremap(mem_start, mem_len); -+ if (!sc->sc_bar1) { -+ device_printf(sc->sc_dev, "cannot map bar%d register space\n", 1); -+ goto fail; -+ } -+ sc->sc_bar1_lastreg = (bus_size_t) -1; -+ -+ /* fix up the bus size */ -+ if (pci_set_dma_mask(dev, DMA_32BIT_MASK)) { -+ device_printf(sc->sc_dev, "No usable DMA configuration, aborting.\n"); -+ goto fail; -+ } -+ if (pci_set_consistent_dma_mask(dev, DMA_32BIT_MASK)) { -+ device_printf(sc->sc_dev, -+ "No usable consistent DMA configuration, aborting.\n"); -+ goto fail; -+ } -+ -+ hifn_set_retry(sc); -+ -+ /* -+ * Setup the area where the Hifn DMA's descriptors -+ * and associated data structures. -+ */ -+ sc->sc_dma = (struct hifn_dma *) pci_alloc_consistent(dev, -+ sizeof(*sc->sc_dma), -+ &sc->sc_dma_physaddr); -+ if (!sc->sc_dma) { -+ device_printf(sc->sc_dev, "cannot alloc sc_dma\n"); -+ goto fail; -+ } -+ bzero(sc->sc_dma, sizeof(*sc->sc_dma)); -+ -+ /* -+ * Reset the board and do the ``secret handshake'' -+ * to enable the crypto support. Then complete the -+ * initialization procedure by setting up the interrupt -+ * and hooking in to the system crypto support so we'll -+ * get used for system services like the crypto device, -+ * IPsec, RNG device, etc. -+ */ -+ hifn_reset_board(sc, 0); -+ -+ if (hifn_enable_crypto(sc) != 0) { -+ device_printf(sc->sc_dev, "crypto enabling failed\n"); -+ goto fail; -+ } -+ hifn_reset_puc(sc); -+ -+ hifn_init_dma(sc); -+ hifn_init_pci_registers(sc); -+ -+ pci_set_master(sc->sc_pcidev); -+ -+ /* XXX can't dynamically determine ram type for 795x; force dram */ -+ if (sc->sc_flags & HIFN_IS_7956) -+ sc->sc_drammodel = 1; -+ else if (hifn_ramtype(sc)) -+ goto fail; -+ -+ if (sc->sc_drammodel == 0) -+ hifn_sramsize(sc); -+ else -+ hifn_dramsize(sc); -+ -+ /* -+ * Workaround for NetSec 7751 rev A: half ram size because two -+ * of the address lines were left floating -+ */ -+ if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC && -+ pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751 && -+ pci_get_revid(dev) == 0x61) /*XXX???*/ -+ sc->sc_ramsize >>= 1; -+ -+ /* -+ * Arrange the interrupt line. -+ */ -+ rc = request_irq(dev->irq, hifn_intr, IRQF_SHARED, "hifn", sc); -+ if (rc) { -+ device_printf(sc->sc_dev, "could not map interrupt: %d\n", rc); -+ goto fail; -+ } -+ sc->sc_irq = dev->irq; -+ -+ hifn_sessions(sc); -+ -+ /* -+ * NB: Keep only the low 16 bits; this masks the chip id -+ * from the 7951. -+ */ -+ rev = READ_REG_1(sc, HIFN_1_REVID) & 0xffff; -+ -+ rseg = sc->sc_ramsize / 1024; -+ rbase = 'K'; -+ if (sc->sc_ramsize >= (1024 * 1024)) { -+ rbase = 'M'; -+ rseg /= 1024; -+ } -+ device_printf(sc->sc_dev, "%s, rev %u, %d%cB %cram", -+ hifn_partname(sc), rev, -+ rseg, rbase, sc->sc_drammodel ? 'd' : 's'); -+ if (sc->sc_flags & HIFN_IS_7956) -+ printf(", pll=0x%x<%s clk, %ux mult>", -+ sc->sc_pllconfig, -+ sc->sc_pllconfig & HIFN_PLL_REF_SEL ? "ext" : "pci", -+ 2 + 2*((sc->sc_pllconfig & HIFN_PLL_ND) >> 11)); -+ printf("\n"); -+ -+ sc->sc_cid = crypto_get_driverid(softc_get_device(sc),CRYPTOCAP_F_HARDWARE); -+ if (sc->sc_cid < 0) { -+ device_printf(sc->sc_dev, "could not get crypto driver id\n"); -+ goto fail; -+ } -+ -+ WRITE_REG_0(sc, HIFN_0_PUCNFG, -+ READ_REG_0(sc, HIFN_0_PUCNFG) | HIFN_PUCNFG_CHIPID); -+ ena = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; -+ -+ switch (ena) { -+ case HIFN_PUSTAT_ENA_2: -+ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0); -+ if (sc->sc_flags & HIFN_HAS_AES) -+ crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); -+ /*FALLTHROUGH*/ -+ case HIFN_PUSTAT_ENA_1: -+ crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); -+ break; -+ } -+ -+ if (sc->sc_flags & (HIFN_HAS_PUBLIC | HIFN_HAS_RNG)) -+ hifn_init_pubrng(sc); -+ -+ init_timer(&sc->sc_tickto); -+ sc->sc_tickto.function = hifn_tick; -+ sc->sc_tickto.data = (unsigned long) sc->sc_num; -+ mod_timer(&sc->sc_tickto, jiffies + HZ); -+ -+ return (0); -+ -+fail: -+ if (sc->sc_cid >= 0) -+ crypto_unregister_all(sc->sc_cid); -+ if (sc->sc_irq != -1) -+ free_irq(sc->sc_irq, sc); -+ if (sc->sc_dma) { -+ /* Turn off DMA polling */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | -+ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); -+ -+ pci_free_consistent(sc->sc_pcidev, -+ sizeof(*sc->sc_dma), -+ sc->sc_dma, sc->sc_dma_physaddr); -+ } -+ kfree(sc); -+ return (-ENXIO); -+} -+ -+/* -+ * Detach an interface that successfully probed. -+ */ -+static void -+hifn_remove(struct pci_dev *dev) -+{ -+ struct hifn_softc *sc = pci_get_drvdata(dev); -+ unsigned long l_flags; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ KASSERT(sc != NULL, ("hifn_detach: null software carrier!")); -+ -+ /* disable interrupts */ -+ HIFN_LOCK(sc); -+ WRITE_REG_1(sc, HIFN_1_DMA_IER, 0); -+ HIFN_UNLOCK(sc); -+ -+ /*XXX other resources */ -+ del_timer_sync(&sc->sc_tickto); -+ -+ /* Turn off DMA polling */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | -+ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); -+ -+ crypto_unregister_all(sc->sc_cid); -+ -+ free_irq(sc->sc_irq, sc); -+ -+ pci_free_consistent(sc->sc_pcidev, sizeof(*sc->sc_dma), -+ sc->sc_dma, sc->sc_dma_physaddr); -+} -+ -+ -+static int -+hifn_init_pubrng(struct hifn_softc *sc) -+{ -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if ((sc->sc_flags & HIFN_IS_7811) == 0) { -+ /* Reset 7951 public key/rng engine */ -+ WRITE_REG_1(sc, HIFN_1_PUB_RESET, -+ READ_REG_1(sc, HIFN_1_PUB_RESET) | HIFN_PUBRST_RESET); -+ -+ for (i = 0; i < 100; i++) { -+ DELAY(1000); -+ if ((READ_REG_1(sc, HIFN_1_PUB_RESET) & -+ HIFN_PUBRST_RESET) == 0) -+ break; -+ } -+ -+ if (i == 100) { -+ device_printf(sc->sc_dev, "public key init failed\n"); -+ return (1); -+ } -+ } -+ -+ /* Enable the rng, if available */ -+#ifdef CONFIG_OCF_RANDOMHARVEST -+ if (sc->sc_flags & HIFN_HAS_RNG) { -+ if (sc->sc_flags & HIFN_IS_7811) { -+ u_int32_t r; -+ r = READ_REG_1(sc, HIFN_1_7811_RNGENA); -+ if (r & HIFN_7811_RNGENA_ENA) { -+ r &= ~HIFN_7811_RNGENA_ENA; -+ WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); -+ } -+ WRITE_REG_1(sc, HIFN_1_7811_RNGCFG, -+ HIFN_7811_RNGCFG_DEFL); -+ r |= HIFN_7811_RNGENA_ENA; -+ WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); -+ } else -+ WRITE_REG_1(sc, HIFN_1_RNG_CONFIG, -+ READ_REG_1(sc, HIFN_1_RNG_CONFIG) | -+ HIFN_RNGCFG_ENA); -+ -+ sc->sc_rngfirst = 1; -+ crypto_rregister(sc->sc_cid, hifn_read_random, sc); -+ } -+#endif -+ -+ /* Enable public key engine, if available */ -+ if (sc->sc_flags & HIFN_HAS_PUBLIC) { -+ WRITE_REG_1(sc, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE); -+ sc->sc_dmaier |= HIFN_DMAIER_PUBDONE; -+ WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); -+#ifdef HIFN_VULCANDEV -+ sc->sc_pkdev = make_dev(&vulcanpk_cdevsw, 0, -+ UID_ROOT, GID_WHEEL, 0666, -+ "vulcanpk"); -+ sc->sc_pkdev->si_drv1 = sc; -+#endif -+ } -+ -+ return (0); -+} -+ -+#ifdef CONFIG_OCF_RANDOMHARVEST -+static int -+hifn_read_random(void *arg, u_int32_t *buf, int len) -+{ -+ struct hifn_softc *sc = (struct hifn_softc *) arg; -+ u_int32_t sts; -+ int i, rc = 0; -+ -+ if (len <= 0) -+ return rc; -+ -+ if (sc->sc_flags & HIFN_IS_7811) { -+ /* ONLY VALID ON 7811!!!! */ -+ for (i = 0; i < 5; i++) { -+ sts = READ_REG_1(sc, HIFN_1_7811_RNGSTS); -+ if (sts & HIFN_7811_RNGSTS_UFL) { -+ device_printf(sc->sc_dev, -+ "RNG underflow: disabling\n"); -+ /* DAVIDM perhaps return -1 */ -+ break; -+ } -+ if ((sts & HIFN_7811_RNGSTS_RDY) == 0) -+ break; -+ -+ /* -+ * There are at least two words in the RNG FIFO -+ * at this point. -+ */ -+ if (rc < len) -+ buf[rc++] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); -+ if (rc < len) -+ buf[rc++] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); -+ } -+ } else -+ buf[rc++] = READ_REG_1(sc, HIFN_1_RNG_DATA); -+ -+ /* NB: discard first data read */ -+ if (sc->sc_rngfirst) { -+ sc->sc_rngfirst = 0; -+ rc = 0; -+ } -+ -+ return(rc); -+} -+#endif /* CONFIG_OCF_RANDOMHARVEST */ -+ -+static void -+hifn_puc_wait(struct hifn_softc *sc) -+{ -+ int i; -+ int reg = HIFN_0_PUCTRL; -+ -+ if (sc->sc_flags & HIFN_IS_7956) { -+ reg = HIFN_0_PUCTRL2; -+ } -+ -+ for (i = 5000; i > 0; i--) { -+ DELAY(1); -+ if (!(READ_REG_0(sc, reg) & HIFN_PUCTRL_RESET)) -+ break; -+ } -+ if (!i) -+ device_printf(sc->sc_dev, "proc unit did not reset(0x%x)\n", -+ READ_REG_0(sc, HIFN_0_PUCTRL)); -+} -+ -+/* -+ * Reset the processing unit. -+ */ -+static void -+hifn_reset_puc(struct hifn_softc *sc) -+{ -+ /* Reset processing unit */ -+ int reg = HIFN_0_PUCTRL; -+ -+ if (sc->sc_flags & HIFN_IS_7956) { -+ reg = HIFN_0_PUCTRL2; -+ } -+ WRITE_REG_0(sc, reg, HIFN_PUCTRL_DMAENA); -+ -+ hifn_puc_wait(sc); -+} -+ -+/* -+ * Set the Retry and TRDY registers; note that we set them to -+ * zero because the 7811 locks up when forced to retry (section -+ * 3.6 of "Specification Update SU-0014-04". Not clear if we -+ * should do this for all Hifn parts, but it doesn't seem to hurt. -+ */ -+static void -+hifn_set_retry(struct hifn_softc *sc) -+{ -+ DPRINTF("%s()\n", __FUNCTION__); -+ /* NB: RETRY only responds to 8-bit reads/writes */ -+ pci_write_config_byte(sc->sc_pcidev, HIFN_RETRY_TIMEOUT, 0); -+ pci_write_config_byte(sc->sc_pcidev, HIFN_TRDY_TIMEOUT, 0); -+ /* piggy back the cache line setting here */ -+ pci_write_config_byte(sc->sc_pcidev, PCI_CACHE_LINE_SIZE, hifn_cache_linesize); -+} -+ -+/* -+ * Resets the board. Values in the regesters are left as is -+ * from the reset (i.e. initial values are assigned elsewhere). -+ */ -+static void -+hifn_reset_board(struct hifn_softc *sc, int full) -+{ -+ u_int32_t reg; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ /* -+ * Set polling in the DMA configuration register to zero. 0x7 avoids -+ * resetting the board and zeros out the other fields. -+ */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | -+ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); -+ -+ /* -+ * Now that polling has been disabled, we have to wait 1 ms -+ * before resetting the board. -+ */ -+ DELAY(1000); -+ -+ /* Reset the DMA unit */ -+ if (full) { -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE); -+ DELAY(1000); -+ } else { -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, -+ HIFN_DMACNFG_MODE | HIFN_DMACNFG_MSTRESET); -+ hifn_reset_puc(sc); -+ } -+ -+ KASSERT(sc->sc_dma != NULL, ("hifn_reset_board: null DMA tag!")); -+ bzero(sc->sc_dma, sizeof(*sc->sc_dma)); -+ -+ /* Bring dma unit out of reset */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | -+ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); -+ -+ hifn_puc_wait(sc); -+ hifn_set_retry(sc); -+ -+ if (sc->sc_flags & HIFN_IS_7811) { -+ for (reg = 0; reg < 1000; reg++) { -+ if (READ_REG_1(sc, HIFN_1_7811_MIPSRST) & -+ HIFN_MIPSRST_CRAMINIT) -+ break; -+ DELAY(1000); -+ } -+ if (reg == 1000) -+ device_printf(sc->sc_dev, ": cram init timeout\n"); -+ } else { -+ /* set up DMA configuration register #2 */ -+ /* turn off all PK and BAR0 swaps */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG2, -+ (3 << HIFN_DMACNFG2_INIT_WRITE_BURST_SHIFT)| -+ (3 << HIFN_DMACNFG2_INIT_READ_BURST_SHIFT)| -+ (2 << HIFN_DMACNFG2_TGT_WRITE_BURST_SHIFT)| -+ (2 << HIFN_DMACNFG2_TGT_READ_BURST_SHIFT)); -+ } -+} -+ -+static u_int32_t -+hifn_next_signature(u_int32_t a, u_int cnt) -+{ -+ int i; -+ u_int32_t v; -+ -+ for (i = 0; i < cnt; i++) { -+ -+ /* get the parity */ -+ v = a & 0x80080125; -+ v ^= v >> 16; -+ v ^= v >> 8; -+ v ^= v >> 4; -+ v ^= v >> 2; -+ v ^= v >> 1; -+ -+ a = (v & 1) ^ (a << 1); -+ } -+ -+ return a; -+} -+ -+ -+/* -+ * Checks to see if crypto is already enabled. If crypto isn't enable, -+ * "hifn_enable_crypto" is called to enable it. The check is important, -+ * as enabling crypto twice will lock the board. -+ */ -+static int -+hifn_enable_crypto(struct hifn_softc *sc) -+{ -+ u_int32_t dmacfg, ramcfg, encl, addr, i; -+ char offtbl[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00 }; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ ramcfg = READ_REG_0(sc, HIFN_0_PUCNFG); -+ dmacfg = READ_REG_1(sc, HIFN_1_DMA_CNFG); -+ -+ /* -+ * The RAM config register's encrypt level bit needs to be set before -+ * every read performed on the encryption level register. -+ */ -+ WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); -+ -+ encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; -+ -+ /* -+ * Make sure we don't re-unlock. Two unlocks kills chip until the -+ * next reboot. -+ */ -+ if (encl == HIFN_PUSTAT_ENA_1 || encl == HIFN_PUSTAT_ENA_2) { -+#ifdef HIFN_DEBUG -+ if (hifn_debug) -+ device_printf(sc->sc_dev, -+ "Strong crypto already enabled!\n"); -+#endif -+ goto report; -+ } -+ -+ if (encl != 0 && encl != HIFN_PUSTAT_ENA_0) { -+#ifdef HIFN_DEBUG -+ if (hifn_debug) -+ device_printf(sc->sc_dev, -+ "Unknown encryption level 0x%x\n", encl); -+#endif -+ return 1; -+ } -+ -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_UNLOCK | -+ HIFN_DMACNFG_MSTRESET | HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); -+ DELAY(1000); -+ addr = READ_REG_1(sc, HIFN_UNLOCK_SECRET1); -+ DELAY(1000); -+ WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, 0); -+ DELAY(1000); -+ -+ for (i = 0; i <= 12; i++) { -+ addr = hifn_next_signature(addr, offtbl[i] + 0x101); -+ WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, addr); -+ -+ DELAY(1000); -+ } -+ -+ WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); -+ encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; -+ -+#ifdef HIFN_DEBUG -+ if (hifn_debug) { -+ if (encl != HIFN_PUSTAT_ENA_1 && encl != HIFN_PUSTAT_ENA_2) -+ device_printf(sc->sc_dev, "Engine is permanently " -+ "locked until next system reset!\n"); -+ else -+ device_printf(sc->sc_dev, "Engine enabled " -+ "successfully!\n"); -+ } -+#endif -+ -+report: -+ WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg); -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, dmacfg); -+ -+ switch (encl) { -+ case HIFN_PUSTAT_ENA_1: -+ case HIFN_PUSTAT_ENA_2: -+ break; -+ case HIFN_PUSTAT_ENA_0: -+ default: -+ device_printf(sc->sc_dev, "disabled\n"); -+ break; -+ } -+ -+ return 0; -+} -+ -+/* -+ * Give initial values to the registers listed in the "Register Space" -+ * section of the HIFN Software Development reference manual. -+ */ -+static void -+hifn_init_pci_registers(struct hifn_softc *sc) -+{ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ /* write fixed values needed by the Initialization registers */ -+ WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA); -+ WRITE_REG_0(sc, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD); -+ WRITE_REG_0(sc, HIFN_0_PUIER, HIFN_PUIER_DSTOVER); -+ -+ /* write all 4 ring address registers */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CRAR, sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, cmdr[0])); -+ WRITE_REG_1(sc, HIFN_1_DMA_SRAR, sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, srcr[0])); -+ WRITE_REG_1(sc, HIFN_1_DMA_DRAR, sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, dstr[0])); -+ WRITE_REG_1(sc, HIFN_1_DMA_RRAR, sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, resr[0])); -+ -+ DELAY(2000); -+ -+ /* write status register */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CSR, -+ HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS | -+ HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS | -+ HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST | -+ HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER | -+ HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST | -+ HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER | -+ HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST | -+ HIFN_DMACSR_S_WAIT | -+ HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST | -+ HIFN_DMACSR_C_WAIT | -+ HIFN_DMACSR_ENGINE | -+ ((sc->sc_flags & HIFN_HAS_PUBLIC) ? -+ HIFN_DMACSR_PUBDONE : 0) | -+ ((sc->sc_flags & HIFN_IS_7811) ? -+ HIFN_DMACSR_ILLW | HIFN_DMACSR_ILLR : 0)); -+ -+ sc->sc_d_busy = sc->sc_r_busy = sc->sc_s_busy = sc->sc_c_busy = 0; -+ sc->sc_dmaier |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT | -+ HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER | -+ HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT | -+ ((sc->sc_flags & HIFN_IS_7811) ? -+ HIFN_DMAIER_ILLW | HIFN_DMAIER_ILLR : 0); -+ sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; -+ WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); -+ -+ -+ if (sc->sc_flags & HIFN_IS_7956) { -+ u_int32_t pll; -+ -+ WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING | -+ HIFN_PUCNFG_TCALLPHASES | -+ HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32); -+ -+ /* turn off the clocks and insure bypass is set */ -+ pll = READ_REG_1(sc, HIFN_1_PLL); -+ pll = (pll &~ (HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL)) -+ | HIFN_PLL_BP | HIFN_PLL_MBSET; -+ WRITE_REG_1(sc, HIFN_1_PLL, pll); -+ DELAY(10*1000); /* 10ms */ -+ -+ /* change configuration */ -+ pll = (pll &~ HIFN_PLL_CONFIG) | sc->sc_pllconfig; -+ WRITE_REG_1(sc, HIFN_1_PLL, pll); -+ DELAY(10*1000); /* 10ms */ -+ -+ /* disable bypass */ -+ pll &= ~HIFN_PLL_BP; -+ WRITE_REG_1(sc, HIFN_1_PLL, pll); -+ /* enable clocks with new configuration */ -+ pll |= HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL; -+ WRITE_REG_1(sc, HIFN_1_PLL, pll); -+ } else { -+ WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING | -+ HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES | -+ HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 | -+ (sc->sc_drammodel ? HIFN_PUCNFG_DRAM : HIFN_PUCNFG_SRAM)); -+ } -+ -+ WRITE_REG_0(sc, HIFN_0_PUISR, HIFN_PUISR_DSTOVER); -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | -+ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST | -+ ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) | -+ ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL)); -+} -+ -+/* -+ * The maximum number of sessions supported by the card -+ * is dependent on the amount of context ram, which -+ * encryption algorithms are enabled, and how compression -+ * is configured. This should be configured before this -+ * routine is called. -+ */ -+static void -+hifn_sessions(struct hifn_softc *sc) -+{ -+ u_int32_t pucnfg; -+ int ctxsize; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ pucnfg = READ_REG_0(sc, HIFN_0_PUCNFG); -+ -+ if (pucnfg & HIFN_PUCNFG_COMPSING) { -+ if (pucnfg & HIFN_PUCNFG_ENCCNFG) -+ ctxsize = 128; -+ else -+ ctxsize = 512; -+ /* -+ * 7955/7956 has internal context memory of 32K -+ */ -+ if (sc->sc_flags & HIFN_IS_7956) -+ sc->sc_maxses = 32768 / ctxsize; -+ else -+ sc->sc_maxses = 1 + -+ ((sc->sc_ramsize - 32768) / ctxsize); -+ } else -+ sc->sc_maxses = sc->sc_ramsize / 16384; -+ -+ if (sc->sc_maxses > 2048) -+ sc->sc_maxses = 2048; -+} -+ -+/* -+ * Determine ram type (sram or dram). Board should be just out of a reset -+ * state when this is called. -+ */ -+static int -+hifn_ramtype(struct hifn_softc *sc) -+{ -+ u_int8_t data[8], dataexpect[8]; -+ int i; -+ -+ for (i = 0; i < sizeof(data); i++) -+ data[i] = dataexpect[i] = 0x55; -+ if (hifn_writeramaddr(sc, 0, data)) -+ return (-1); -+ if (hifn_readramaddr(sc, 0, data)) -+ return (-1); -+ if (bcmp(data, dataexpect, sizeof(data)) != 0) { -+ sc->sc_drammodel = 1; -+ return (0); -+ } -+ -+ for (i = 0; i < sizeof(data); i++) -+ data[i] = dataexpect[i] = 0xaa; -+ if (hifn_writeramaddr(sc, 0, data)) -+ return (-1); -+ if (hifn_readramaddr(sc, 0, data)) -+ return (-1); -+ if (bcmp(data, dataexpect, sizeof(data)) != 0) { -+ sc->sc_drammodel = 1; -+ return (0); -+ } -+ -+ return (0); -+} -+ -+#define HIFN_SRAM_MAX (32 << 20) -+#define HIFN_SRAM_STEP_SIZE 16384 -+#define HIFN_SRAM_GRANULARITY (HIFN_SRAM_MAX / HIFN_SRAM_STEP_SIZE) -+ -+static int -+hifn_sramsize(struct hifn_softc *sc) -+{ -+ u_int32_t a; -+ u_int8_t data[8]; -+ u_int8_t dataexpect[sizeof(data)]; -+ int32_t i; -+ -+ for (i = 0; i < sizeof(data); i++) -+ data[i] = dataexpect[i] = i ^ 0x5a; -+ -+ for (i = HIFN_SRAM_GRANULARITY - 1; i >= 0; i--) { -+ a = i * HIFN_SRAM_STEP_SIZE; -+ bcopy(&i, data, sizeof(i)); -+ hifn_writeramaddr(sc, a, data); -+ } -+ -+ for (i = 0; i < HIFN_SRAM_GRANULARITY; i++) { -+ a = i * HIFN_SRAM_STEP_SIZE; -+ bcopy(&i, dataexpect, sizeof(i)); -+ if (hifn_readramaddr(sc, a, data) < 0) -+ return (0); -+ if (bcmp(data, dataexpect, sizeof(data)) != 0) -+ return (0); -+ sc->sc_ramsize = a + HIFN_SRAM_STEP_SIZE; -+ } -+ -+ return (0); -+} -+ -+/* -+ * XXX For dram boards, one should really try all of the -+ * HIFN_PUCNFG_DSZ_*'s. This just assumes that PUCNFG -+ * is already set up correctly. -+ */ -+static int -+hifn_dramsize(struct hifn_softc *sc) -+{ -+ u_int32_t cnfg; -+ -+ if (sc->sc_flags & HIFN_IS_7956) { -+ /* -+ * 7955/7956 have a fixed internal ram of only 32K. -+ */ -+ sc->sc_ramsize = 32768; -+ } else { -+ cnfg = READ_REG_0(sc, HIFN_0_PUCNFG) & -+ HIFN_PUCNFG_DRAMMASK; -+ sc->sc_ramsize = 1 << ((cnfg >> 13) + 18); -+ } -+ return (0); -+} -+ -+static void -+hifn_alloc_slot(struct hifn_softc *sc, int *cmdp, int *srcp, int *dstp, int *resp) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (dma->cmdi == HIFN_D_CMD_RSIZE) { -+ dma->cmdi = 0; -+ dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); -+ wmb(); -+ dma->cmdr[HIFN_D_CMD_RSIZE].l |= htole32(HIFN_D_VALID); -+ HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, -+ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); -+ } -+ *cmdp = dma->cmdi++; -+ dma->cmdk = dma->cmdi; -+ -+ if (dma->srci == HIFN_D_SRC_RSIZE) { -+ dma->srci = 0; -+ dma->srcr[HIFN_D_SRC_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); -+ wmb(); -+ dma->srcr[HIFN_D_SRC_RSIZE].l |= htole32(HIFN_D_VALID); -+ HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, -+ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); -+ } -+ *srcp = dma->srci++; -+ dma->srck = dma->srci; -+ -+ if (dma->dsti == HIFN_D_DST_RSIZE) { -+ dma->dsti = 0; -+ dma->dstr[HIFN_D_DST_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); -+ wmb(); -+ dma->dstr[HIFN_D_DST_RSIZE].l |= htole32(HIFN_D_VALID); -+ HIFN_DSTR_SYNC(sc, HIFN_D_DST_RSIZE, -+ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); -+ } -+ *dstp = dma->dsti++; -+ dma->dstk = dma->dsti; -+ -+ if (dma->resi == HIFN_D_RES_RSIZE) { -+ dma->resi = 0; -+ dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); -+ wmb(); -+ dma->resr[HIFN_D_RES_RSIZE].l |= htole32(HIFN_D_VALID); -+ HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, -+ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); -+ } -+ *resp = dma->resi++; -+ dma->resk = dma->resi; -+} -+ -+static int -+hifn_writeramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ hifn_base_command_t wc; -+ const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; -+ int r, cmdi, resi, srci, dsti; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ wc.masks = htole16(3 << 13); -+ wc.session_num = htole16(addr >> 14); -+ wc.total_source_count = htole16(8); -+ wc.total_dest_count = htole16(addr & 0x3fff); -+ -+ hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); -+ -+ WRITE_REG_1(sc, HIFN_1_DMA_CSR, -+ HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | -+ HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); -+ -+ /* build write command */ -+ bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); -+ *(hifn_base_command_t *)dma->command_bufs[cmdi] = wc; -+ bcopy(data, &dma->test_src, sizeof(dma->test_src)); -+ -+ dma->srcr[srci].p = htole32(sc->sc_dma_physaddr -+ + offsetof(struct hifn_dma, test_src)); -+ dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr -+ + offsetof(struct hifn_dma, test_dst)); -+ -+ dma->cmdr[cmdi].l = htole32(16 | masks); -+ dma->srcr[srci].l = htole32(8 | masks); -+ dma->dstr[dsti].l = htole32(4 | masks); -+ dma->resr[resi].l = htole32(4 | masks); -+ -+ for (r = 10000; r >= 0; r--) { -+ DELAY(10); -+ if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) -+ break; -+ } -+ if (r == 0) { -+ device_printf(sc->sc_dev, "writeramaddr -- " -+ "result[%d](addr %d) still valid\n", resi, addr); -+ r = -1; -+ return (-1); -+ } else -+ r = 0; -+ -+ WRITE_REG_1(sc, HIFN_1_DMA_CSR, -+ HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | -+ HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); -+ -+ return (r); -+} -+ -+static int -+hifn_readramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ hifn_base_command_t rc; -+ const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; -+ int r, cmdi, srci, dsti, resi; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ rc.masks = htole16(2 << 13); -+ rc.session_num = htole16(addr >> 14); -+ rc.total_source_count = htole16(addr & 0x3fff); -+ rc.total_dest_count = htole16(8); -+ -+ hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); -+ -+ WRITE_REG_1(sc, HIFN_1_DMA_CSR, -+ HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | -+ HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); -+ -+ bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); -+ *(hifn_base_command_t *)dma->command_bufs[cmdi] = rc; -+ -+ dma->srcr[srci].p = htole32(sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, test_src)); -+ dma->test_src = 0; -+ dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, test_dst)); -+ dma->test_dst = 0; -+ dma->cmdr[cmdi].l = htole32(8 | masks); -+ dma->srcr[srci].l = htole32(8 | masks); -+ dma->dstr[dsti].l = htole32(8 | masks); -+ dma->resr[resi].l = htole32(HIFN_MAX_RESULT | masks); -+ -+ for (r = 10000; r >= 0; r--) { -+ DELAY(10); -+ if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) -+ break; -+ } -+ if (r == 0) { -+ device_printf(sc->sc_dev, "readramaddr -- " -+ "result[%d](addr %d) still valid\n", resi, addr); -+ r = -1; -+ } else { -+ r = 0; -+ bcopy(&dma->test_dst, data, sizeof(dma->test_dst)); -+ } -+ -+ WRITE_REG_1(sc, HIFN_1_DMA_CSR, -+ HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | -+ HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); -+ -+ return (r); -+} -+ -+/* -+ * Initialize the descriptor rings. -+ */ -+static void -+hifn_init_dma(struct hifn_softc *sc) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ hifn_set_retry(sc); -+ -+ /* initialize static pointer values */ -+ for (i = 0; i < HIFN_D_CMD_RSIZE; i++) -+ dma->cmdr[i].p = htole32(sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, command_bufs[i][0])); -+ for (i = 0; i < HIFN_D_RES_RSIZE; i++) -+ dma->resr[i].p = htole32(sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, result_bufs[i][0])); -+ -+ dma->cmdr[HIFN_D_CMD_RSIZE].p = -+ htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, cmdr[0])); -+ dma->srcr[HIFN_D_SRC_RSIZE].p = -+ htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, srcr[0])); -+ dma->dstr[HIFN_D_DST_RSIZE].p = -+ htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, dstr[0])); -+ dma->resr[HIFN_D_RES_RSIZE].p = -+ htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, resr[0])); -+ -+ dma->cmdu = dma->srcu = dma->dstu = dma->resu = 0; -+ dma->cmdi = dma->srci = dma->dsti = dma->resi = 0; -+ dma->cmdk = dma->srck = dma->dstk = dma->resk = 0; -+} -+ -+/* -+ * Writes out the raw command buffer space. Returns the -+ * command buffer size. -+ */ -+static u_int -+hifn_write_command(struct hifn_command *cmd, u_int8_t *buf) -+{ -+ struct hifn_softc *sc = NULL; -+ u_int8_t *buf_pos; -+ hifn_base_command_t *base_cmd; -+ hifn_mac_command_t *mac_cmd; -+ hifn_crypt_command_t *cry_cmd; -+ int using_mac, using_crypt, len, ivlen; -+ u_int32_t dlen, slen; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ buf_pos = buf; -+ using_mac = cmd->base_masks & HIFN_BASE_CMD_MAC; -+ using_crypt = cmd->base_masks & HIFN_BASE_CMD_CRYPT; -+ -+ base_cmd = (hifn_base_command_t *)buf_pos; -+ base_cmd->masks = htole16(cmd->base_masks); -+ slen = cmd->src_mapsize; -+ if (cmd->sloplen) -+ dlen = cmd->dst_mapsize - cmd->sloplen + sizeof(u_int32_t); -+ else -+ dlen = cmd->dst_mapsize; -+ base_cmd->total_source_count = htole16(slen & HIFN_BASE_CMD_LENMASK_LO); -+ base_cmd->total_dest_count = htole16(dlen & HIFN_BASE_CMD_LENMASK_LO); -+ dlen >>= 16; -+ slen >>= 16; -+ base_cmd->session_num = htole16( -+ ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) | -+ ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M)); -+ buf_pos += sizeof(hifn_base_command_t); -+ -+ if (using_mac) { -+ mac_cmd = (hifn_mac_command_t *)buf_pos; -+ dlen = cmd->maccrd->crd_len; -+ mac_cmd->source_count = htole16(dlen & 0xffff); -+ dlen >>= 16; -+ mac_cmd->masks = htole16(cmd->mac_masks | -+ ((dlen << HIFN_MAC_CMD_SRCLEN_S) & HIFN_MAC_CMD_SRCLEN_M)); -+ mac_cmd->header_skip = htole16(cmd->maccrd->crd_skip); -+ mac_cmd->reserved = 0; -+ buf_pos += sizeof(hifn_mac_command_t); -+ } -+ -+ if (using_crypt) { -+ cry_cmd = (hifn_crypt_command_t *)buf_pos; -+ dlen = cmd->enccrd->crd_len; -+ cry_cmd->source_count = htole16(dlen & 0xffff); -+ dlen >>= 16; -+ cry_cmd->masks = htole16(cmd->cry_masks | -+ ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) & HIFN_CRYPT_CMD_SRCLEN_M)); -+ cry_cmd->header_skip = htole16(cmd->enccrd->crd_skip); -+ cry_cmd->reserved = 0; -+ buf_pos += sizeof(hifn_crypt_command_t); -+ } -+ -+ if (using_mac && cmd->mac_masks & HIFN_MAC_CMD_NEW_KEY) { -+ bcopy(cmd->mac, buf_pos, HIFN_MAC_KEY_LENGTH); -+ buf_pos += HIFN_MAC_KEY_LENGTH; -+ } -+ -+ if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_KEY) { -+ switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) { -+ case HIFN_CRYPT_CMD_ALG_3DES: -+ bcopy(cmd->ck, buf_pos, HIFN_3DES_KEY_LENGTH); -+ buf_pos += HIFN_3DES_KEY_LENGTH; -+ break; -+ case HIFN_CRYPT_CMD_ALG_DES: -+ bcopy(cmd->ck, buf_pos, HIFN_DES_KEY_LENGTH); -+ buf_pos += HIFN_DES_KEY_LENGTH; -+ break; -+ case HIFN_CRYPT_CMD_ALG_RC4: -+ len = 256; -+ do { -+ int clen; -+ -+ clen = MIN(cmd->cklen, len); -+ bcopy(cmd->ck, buf_pos, clen); -+ len -= clen; -+ buf_pos += clen; -+ } while (len > 0); -+ bzero(buf_pos, 4); -+ buf_pos += 4; -+ break; -+ case HIFN_CRYPT_CMD_ALG_AES: -+ /* -+ * AES keys are variable 128, 192 and -+ * 256 bits (16, 24 and 32 bytes). -+ */ -+ bcopy(cmd->ck, buf_pos, cmd->cklen); -+ buf_pos += cmd->cklen; -+ break; -+ } -+ } -+ -+ if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_IV) { -+ switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) { -+ case HIFN_CRYPT_CMD_ALG_AES: -+ ivlen = HIFN_AES_IV_LENGTH; -+ break; -+ default: -+ ivlen = HIFN_IV_LENGTH; -+ break; -+ } -+ bcopy(cmd->iv, buf_pos, ivlen); -+ buf_pos += ivlen; -+ } -+ -+ if ((cmd->base_masks & (HIFN_BASE_CMD_MAC|HIFN_BASE_CMD_CRYPT)) == 0) { -+ bzero(buf_pos, 8); -+ buf_pos += 8; -+ } -+ -+ return (buf_pos - buf); -+} -+ -+static int -+hifn_dmamap_aligned(struct hifn_operand *op) -+{ -+ struct hifn_softc *sc = NULL; -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ for (i = 0; i < op->nsegs; i++) { -+ if (op->segs[i].ds_addr & 3) -+ return (0); -+ if ((i != (op->nsegs - 1)) && (op->segs[i].ds_len & 3)) -+ return (0); -+ } -+ return (1); -+} -+ -+static __inline int -+hifn_dmamap_dstwrap(struct hifn_softc *sc, int idx) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ -+ if (++idx == HIFN_D_DST_RSIZE) { -+ dma->dstr[idx].l = htole32(HIFN_D_VALID | HIFN_D_JUMP | -+ HIFN_D_MASKDONEIRQ); -+ HIFN_DSTR_SYNC(sc, idx, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ idx = 0; -+ } -+ return (idx); -+} -+ -+static int -+hifn_dmamap_load_dst(struct hifn_softc *sc, struct hifn_command *cmd) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ struct hifn_operand *dst = &cmd->dst; -+ u_int32_t p, l; -+ int idx, used = 0, i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ idx = dma->dsti; -+ for (i = 0; i < dst->nsegs - 1; i++) { -+ dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); -+ dma->dstr[idx].l = htole32(HIFN_D_MASKDONEIRQ | dst->segs[i].ds_len); -+ wmb(); -+ dma->dstr[idx].l |= htole32(HIFN_D_VALID); -+ HIFN_DSTR_SYNC(sc, idx, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ used++; -+ -+ idx = hifn_dmamap_dstwrap(sc, idx); -+ } -+ -+ if (cmd->sloplen == 0) { -+ p = dst->segs[i].ds_addr; -+ l = HIFN_D_MASKDONEIRQ | HIFN_D_LAST | -+ dst->segs[i].ds_len; -+ } else { -+ p = sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, slop[cmd->slopidx]); -+ l = HIFN_D_MASKDONEIRQ | HIFN_D_LAST | -+ sizeof(u_int32_t); -+ -+ if ((dst->segs[i].ds_len - cmd->sloplen) != 0) { -+ dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); -+ dma->dstr[idx].l = htole32(HIFN_D_MASKDONEIRQ | -+ (dst->segs[i].ds_len - cmd->sloplen)); -+ wmb(); -+ dma->dstr[idx].l |= htole32(HIFN_D_VALID); -+ HIFN_DSTR_SYNC(sc, idx, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ used++; -+ -+ idx = hifn_dmamap_dstwrap(sc, idx); -+ } -+ } -+ dma->dstr[idx].p = htole32(p); -+ dma->dstr[idx].l = htole32(l); -+ wmb(); -+ dma->dstr[idx].l |= htole32(HIFN_D_VALID); -+ HIFN_DSTR_SYNC(sc, idx, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ used++; -+ -+ idx = hifn_dmamap_dstwrap(sc, idx); -+ -+ dma->dsti = idx; -+ dma->dstu += used; -+ return (idx); -+} -+ -+static __inline int -+hifn_dmamap_srcwrap(struct hifn_softc *sc, int idx) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ -+ if (++idx == HIFN_D_SRC_RSIZE) { -+ dma->srcr[idx].l = htole32(HIFN_D_VALID | -+ HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); -+ HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, -+ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); -+ idx = 0; -+ } -+ return (idx); -+} -+ -+static int -+hifn_dmamap_load_src(struct hifn_softc *sc, struct hifn_command *cmd) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ struct hifn_operand *src = &cmd->src; -+ int idx, i; -+ u_int32_t last = 0; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ idx = dma->srci; -+ for (i = 0; i < src->nsegs; i++) { -+ if (i == src->nsegs - 1) -+ last = HIFN_D_LAST; -+ -+ dma->srcr[idx].p = htole32(src->segs[i].ds_addr); -+ dma->srcr[idx].l = htole32(src->segs[i].ds_len | -+ HIFN_D_MASKDONEIRQ | last); -+ wmb(); -+ dma->srcr[idx].l |= htole32(HIFN_D_VALID); -+ HIFN_SRCR_SYNC(sc, idx, -+ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); -+ -+ idx = hifn_dmamap_srcwrap(sc, idx); -+ } -+ dma->srci = idx; -+ dma->srcu += src->nsegs; -+ return (idx); -+} -+ -+ -+static int -+hifn_crypto( -+ struct hifn_softc *sc, -+ struct hifn_command *cmd, -+ struct cryptop *crp, -+ int hint) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ u_int32_t cmdlen, csr; -+ int cmdi, resi, err = 0; -+ unsigned long l_flags; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ /* -+ * need 1 cmd, and 1 res -+ * -+ * NB: check this first since it's easy. -+ */ -+ HIFN_LOCK(sc); -+ if ((dma->cmdu + 1) > HIFN_D_CMD_RSIZE || -+ (dma->resu + 1) > HIFN_D_RES_RSIZE) { -+#ifdef HIFN_DEBUG -+ if (hifn_debug) { -+ device_printf(sc->sc_dev, -+ "cmd/result exhaustion, cmdu %u resu %u\n", -+ dma->cmdu, dma->resu); -+ } -+#endif -+ hifnstats.hst_nomem_cr++; -+ sc->sc_needwakeup |= CRYPTO_SYMQ; -+ HIFN_UNLOCK(sc); -+ return (ERESTART); -+ } -+ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ if (pci_map_skb(sc, &cmd->src, cmd->src_skb)) { -+ hifnstats.hst_nomem_load++; -+ err = ENOMEM; -+ goto err_srcmap1; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ if (pci_map_uio(sc, &cmd->src, cmd->src_io)) { -+ hifnstats.hst_nomem_load++; -+ err = ENOMEM; -+ goto err_srcmap1; -+ } -+ } else { -+ if (pci_map_buf(sc, &cmd->src, cmd->src_buf, crp->crp_ilen)) { -+ hifnstats.hst_nomem_load++; -+ err = ENOMEM; -+ goto err_srcmap1; -+ } -+ } -+ -+ if (hifn_dmamap_aligned(&cmd->src)) { -+ cmd->sloplen = cmd->src_mapsize & 3; -+ cmd->dst = cmd->src; -+ } else { -+ if (crp->crp_flags & CRYPTO_F_IOV) { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ err = EINVAL; -+ goto err_srcmap; -+ } else if (crp->crp_flags & CRYPTO_F_SKBUF) { -+#ifdef NOTYET -+ int totlen, len; -+ struct mbuf *m, *m0, *mlast; -+ -+ KASSERT(cmd->dst_m == cmd->src_m, -+ ("hifn_crypto: dst_m initialized improperly")); -+ hifnstats.hst_unaligned++; -+ /* -+ * Source is not aligned on a longword boundary. -+ * Copy the data to insure alignment. If we fail -+ * to allocate mbufs or clusters while doing this -+ * we return ERESTART so the operation is requeued -+ * at the crypto later, but only if there are -+ * ops already posted to the hardware; otherwise we -+ * have no guarantee that we'll be re-entered. -+ */ -+ totlen = cmd->src_mapsize; -+ if (cmd->src_m->m_flags & M_PKTHDR) { -+ len = MHLEN; -+ MGETHDR(m0, M_DONTWAIT, MT_DATA); -+ if (m0 && !m_dup_pkthdr(m0, cmd->src_m, M_DONTWAIT)) { -+ m_free(m0); -+ m0 = NULL; -+ } -+ } else { -+ len = MLEN; -+ MGET(m0, M_DONTWAIT, MT_DATA); -+ } -+ if (m0 == NULL) { -+ hifnstats.hst_nomem_mbuf++; -+ err = dma->cmdu ? ERESTART : ENOMEM; -+ goto err_srcmap; -+ } -+ if (totlen >= MINCLSIZE) { -+ MCLGET(m0, M_DONTWAIT); -+ if ((m0->m_flags & M_EXT) == 0) { -+ hifnstats.hst_nomem_mcl++; -+ err = dma->cmdu ? ERESTART : ENOMEM; -+ m_freem(m0); -+ goto err_srcmap; -+ } -+ len = MCLBYTES; -+ } -+ totlen -= len; -+ m0->m_pkthdr.len = m0->m_len = len; -+ mlast = m0; -+ -+ while (totlen > 0) { -+ MGET(m, M_DONTWAIT, MT_DATA); -+ if (m == NULL) { -+ hifnstats.hst_nomem_mbuf++; -+ err = dma->cmdu ? ERESTART : ENOMEM; -+ m_freem(m0); -+ goto err_srcmap; -+ } -+ len = MLEN; -+ if (totlen >= MINCLSIZE) { -+ MCLGET(m, M_DONTWAIT); -+ if ((m->m_flags & M_EXT) == 0) { -+ hifnstats.hst_nomem_mcl++; -+ err = dma->cmdu ? ERESTART : ENOMEM; -+ mlast->m_next = m; -+ m_freem(m0); -+ goto err_srcmap; -+ } -+ len = MCLBYTES; -+ } -+ -+ m->m_len = len; -+ m0->m_pkthdr.len += len; -+ totlen -= len; -+ -+ mlast->m_next = m; -+ mlast = m; -+ } -+ cmd->dst_m = m0; -+#else -+ device_printf(sc->sc_dev, -+ "%s,%d: CRYPTO_F_SKBUF unaligned not implemented\n", -+ __FILE__, __LINE__); -+ err = EINVAL; -+ goto err_srcmap; -+#endif -+ } else { -+ device_printf(sc->sc_dev, -+ "%s,%d: unaligned contig buffers not implemented\n", -+ __FILE__, __LINE__); -+ err = EINVAL; -+ goto err_srcmap; -+ } -+ } -+ -+ if (cmd->dst_map == NULL) { -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ if (pci_map_skb(sc, &cmd->dst, cmd->dst_skb)) { -+ hifnstats.hst_nomem_map++; -+ err = ENOMEM; -+ goto err_dstmap1; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ if (pci_map_uio(sc, &cmd->dst, cmd->dst_io)) { -+ hifnstats.hst_nomem_load++; -+ err = ENOMEM; -+ goto err_dstmap1; -+ } -+ } else { -+ if (pci_map_buf(sc, &cmd->dst, cmd->dst_buf, crp->crp_ilen)) { -+ hifnstats.hst_nomem_load++; -+ err = ENOMEM; -+ goto err_dstmap1; -+ } -+ } -+ } -+ -+#ifdef HIFN_DEBUG -+ if (hifn_debug) { -+ device_printf(sc->sc_dev, -+ "Entering cmd: stat %8x ien %8x u %d/%d/%d/%d n %d/%d\n", -+ READ_REG_1(sc, HIFN_1_DMA_CSR), -+ READ_REG_1(sc, HIFN_1_DMA_IER), -+ dma->cmdu, dma->srcu, dma->dstu, dma->resu, -+ cmd->src_nsegs, cmd->dst_nsegs); -+ } -+#endif -+ -+#if 0 -+ if (cmd->src_map == cmd->dst_map) { -+ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, -+ BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); -+ } else { -+ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, -+ BUS_DMASYNC_PREWRITE); -+ bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, -+ BUS_DMASYNC_PREREAD); -+ } -+#endif -+ -+ /* -+ * need N src, and N dst -+ */ -+ if ((dma->srcu + cmd->src_nsegs) > HIFN_D_SRC_RSIZE || -+ (dma->dstu + cmd->dst_nsegs + 1) > HIFN_D_DST_RSIZE) { -+#ifdef HIFN_DEBUG -+ if (hifn_debug) { -+ device_printf(sc->sc_dev, -+ "src/dst exhaustion, srcu %u+%u dstu %u+%u\n", -+ dma->srcu, cmd->src_nsegs, -+ dma->dstu, cmd->dst_nsegs); -+ } -+#endif -+ hifnstats.hst_nomem_sd++; -+ err = ERESTART; -+ goto err_dstmap; -+ } -+ -+ if (dma->cmdi == HIFN_D_CMD_RSIZE) { -+ dma->cmdi = 0; -+ dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); -+ wmb(); -+ dma->cmdr[HIFN_D_CMD_RSIZE].l |= htole32(HIFN_D_VALID); -+ HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, -+ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); -+ } -+ cmdi = dma->cmdi++; -+ cmdlen = hifn_write_command(cmd, dma->command_bufs[cmdi]); -+ HIFN_CMD_SYNC(sc, cmdi, BUS_DMASYNC_PREWRITE); -+ -+ /* .p for command/result already set */ -+ dma->cmdr[cmdi].l = htole32(cmdlen | HIFN_D_LAST | -+ HIFN_D_MASKDONEIRQ); -+ wmb(); -+ dma->cmdr[cmdi].l |= htole32(HIFN_D_VALID); -+ HIFN_CMDR_SYNC(sc, cmdi, -+ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); -+ dma->cmdu++; -+ -+ /* -+ * We don't worry about missing an interrupt (which a "command wait" -+ * interrupt salvages us from), unless there is more than one command -+ * in the queue. -+ */ -+ if (dma->cmdu > 1) { -+ sc->sc_dmaier |= HIFN_DMAIER_C_WAIT; -+ WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); -+ } -+ -+ hifnstats.hst_ipackets++; -+ hifnstats.hst_ibytes += cmd->src_mapsize; -+ -+ hifn_dmamap_load_src(sc, cmd); -+ -+ /* -+ * Unlike other descriptors, we don't mask done interrupt from -+ * result descriptor. -+ */ -+#ifdef HIFN_DEBUG -+ if (hifn_debug) -+ device_printf(sc->sc_dev, "load res\n"); -+#endif -+ if (dma->resi == HIFN_D_RES_RSIZE) { -+ dma->resi = 0; -+ dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); -+ wmb(); -+ dma->resr[HIFN_D_RES_RSIZE].l |= htole32(HIFN_D_VALID); -+ HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ } -+ resi = dma->resi++; -+ KASSERT(dma->hifn_commands[resi] == NULL, -+ ("hifn_crypto: command slot %u busy", resi)); -+ dma->hifn_commands[resi] = cmd; -+ HIFN_RES_SYNC(sc, resi, BUS_DMASYNC_PREREAD); -+ if ((hint & CRYPTO_HINT_MORE) && sc->sc_curbatch < hifn_maxbatch) { -+ dma->resr[resi].l = htole32(HIFN_MAX_RESULT | -+ HIFN_D_LAST | HIFN_D_MASKDONEIRQ); -+ wmb(); -+ dma->resr[resi].l |= htole32(HIFN_D_VALID); -+ sc->sc_curbatch++; -+ if (sc->sc_curbatch > hifnstats.hst_maxbatch) -+ hifnstats.hst_maxbatch = sc->sc_curbatch; -+ hifnstats.hst_totbatch++; -+ } else { -+ dma->resr[resi].l = htole32(HIFN_MAX_RESULT | HIFN_D_LAST); -+ wmb(); -+ dma->resr[resi].l |= htole32(HIFN_D_VALID); -+ sc->sc_curbatch = 0; -+ } -+ HIFN_RESR_SYNC(sc, resi, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ dma->resu++; -+ -+ if (cmd->sloplen) -+ cmd->slopidx = resi; -+ -+ hifn_dmamap_load_dst(sc, cmd); -+ -+ csr = 0; -+ if (sc->sc_c_busy == 0) { -+ csr |= HIFN_DMACSR_C_CTRL_ENA; -+ sc->sc_c_busy = 1; -+ } -+ if (sc->sc_s_busy == 0) { -+ csr |= HIFN_DMACSR_S_CTRL_ENA; -+ sc->sc_s_busy = 1; -+ } -+ if (sc->sc_r_busy == 0) { -+ csr |= HIFN_DMACSR_R_CTRL_ENA; -+ sc->sc_r_busy = 1; -+ } -+ if (sc->sc_d_busy == 0) { -+ csr |= HIFN_DMACSR_D_CTRL_ENA; -+ sc->sc_d_busy = 1; -+ } -+ if (csr) -+ WRITE_REG_1(sc, HIFN_1_DMA_CSR, csr); -+ -+#ifdef HIFN_DEBUG -+ if (hifn_debug) { -+ device_printf(sc->sc_dev, "command: stat %8x ier %8x\n", -+ READ_REG_1(sc, HIFN_1_DMA_CSR), -+ READ_REG_1(sc, HIFN_1_DMA_IER)); -+ } -+#endif -+ -+ sc->sc_active = 5; -+ HIFN_UNLOCK(sc); -+ KASSERT(err == 0, ("hifn_crypto: success with error %u", err)); -+ return (err); /* success */ -+ -+err_dstmap: -+ if (cmd->src_map != cmd->dst_map) -+ pci_unmap_buf(sc, &cmd->dst); -+err_dstmap1: -+err_srcmap: -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ if (cmd->src_skb != cmd->dst_skb) -+#ifdef NOTYET -+ m_freem(cmd->dst_m); -+#else -+ device_printf(sc->sc_dev, -+ "%s,%d: CRYPTO_F_SKBUF src != dst not implemented\n", -+ __FILE__, __LINE__); -+#endif -+ } -+ pci_unmap_buf(sc, &cmd->src); -+err_srcmap1: -+ HIFN_UNLOCK(sc); -+ return (err); -+} -+ -+static void -+hifn_tick(unsigned long arg) -+{ -+ struct hifn_softc *sc; -+ unsigned long l_flags; -+ -+ if (arg >= HIFN_MAX_CHIPS) -+ return; -+ sc = hifn_chip_idx[arg]; -+ if (!sc) -+ return; -+ -+ HIFN_LOCK(sc); -+ if (sc->sc_active == 0) { -+ struct hifn_dma *dma = sc->sc_dma; -+ u_int32_t r = 0; -+ -+ if (dma->cmdu == 0 && sc->sc_c_busy) { -+ sc->sc_c_busy = 0; -+ r |= HIFN_DMACSR_C_CTRL_DIS; -+ } -+ if (dma->srcu == 0 && sc->sc_s_busy) { -+ sc->sc_s_busy = 0; -+ r |= HIFN_DMACSR_S_CTRL_DIS; -+ } -+ if (dma->dstu == 0 && sc->sc_d_busy) { -+ sc->sc_d_busy = 0; -+ r |= HIFN_DMACSR_D_CTRL_DIS; -+ } -+ if (dma->resu == 0 && sc->sc_r_busy) { -+ sc->sc_r_busy = 0; -+ r |= HIFN_DMACSR_R_CTRL_DIS; -+ } -+ if (r) -+ WRITE_REG_1(sc, HIFN_1_DMA_CSR, r); -+ } else -+ sc->sc_active--; -+ HIFN_UNLOCK(sc); -+ mod_timer(&sc->sc_tickto, jiffies + HZ); -+} -+ -+static irqreturn_t -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) -+hifn_intr(int irq, void *arg) -+#else -+hifn_intr(int irq, void *arg, struct pt_regs *regs) -+#endif -+{ -+ struct hifn_softc *sc = arg; -+ struct hifn_dma *dma; -+ u_int32_t dmacsr, restart; -+ int i, u; -+ unsigned long l_flags; -+ -+ dmacsr = READ_REG_1(sc, HIFN_1_DMA_CSR); -+ -+ /* Nothing in the DMA unit interrupted */ -+ if ((dmacsr & sc->sc_dmaier) == 0) -+ return IRQ_NONE; -+ -+ HIFN_LOCK(sc); -+ -+ dma = sc->sc_dma; -+ -+#ifdef HIFN_DEBUG -+ if (hifn_debug) { -+ device_printf(sc->sc_dev, -+ "irq: stat %08x ien %08x damier %08x i %d/%d/%d/%d k %d/%d/%d/%d u %d/%d/%d/%d\n", -+ dmacsr, READ_REG_1(sc, HIFN_1_DMA_IER), sc->sc_dmaier, -+ dma->cmdi, dma->srci, dma->dsti, dma->resi, -+ dma->cmdk, dma->srck, dma->dstk, dma->resk, -+ dma->cmdu, dma->srcu, dma->dstu, dma->resu); -+ } -+#endif -+ -+ WRITE_REG_1(sc, HIFN_1_DMA_CSR, dmacsr & sc->sc_dmaier); -+ -+ if ((sc->sc_flags & HIFN_HAS_PUBLIC) && -+ (dmacsr & HIFN_DMACSR_PUBDONE)) -+ WRITE_REG_1(sc, HIFN_1_PUB_STATUS, -+ READ_REG_1(sc, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE); -+ -+ restart = dmacsr & (HIFN_DMACSR_D_OVER | HIFN_DMACSR_R_OVER); -+ if (restart) -+ device_printf(sc->sc_dev, "overrun %x\n", dmacsr); -+ -+ if (sc->sc_flags & HIFN_IS_7811) { -+ if (dmacsr & HIFN_DMACSR_ILLR) -+ device_printf(sc->sc_dev, "illegal read\n"); -+ if (dmacsr & HIFN_DMACSR_ILLW) -+ device_printf(sc->sc_dev, "illegal write\n"); -+ } -+ -+ restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT | -+ HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT); -+ if (restart) { -+ device_printf(sc->sc_dev, "abort, resetting.\n"); -+ hifnstats.hst_abort++; -+ hifn_abort(sc); -+ HIFN_UNLOCK(sc); -+ return IRQ_HANDLED; -+ } -+ -+ if ((dmacsr & HIFN_DMACSR_C_WAIT) && (dma->cmdu == 0)) { -+ /* -+ * If no slots to process and we receive a "waiting on -+ * command" interrupt, we disable the "waiting on command" -+ * (by clearing it). -+ */ -+ sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; -+ WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); -+ } -+ -+ /* clear the rings */ -+ i = dma->resk; u = dma->resu; -+ while (u != 0) { -+ HIFN_RESR_SYNC(sc, i, -+ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); -+ if (dma->resr[i].l & htole32(HIFN_D_VALID)) { -+ HIFN_RESR_SYNC(sc, i, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ break; -+ } -+ -+ if (i != HIFN_D_RES_RSIZE) { -+ struct hifn_command *cmd; -+ u_int8_t *macbuf = NULL; -+ -+ HIFN_RES_SYNC(sc, i, BUS_DMASYNC_POSTREAD); -+ cmd = dma->hifn_commands[i]; -+ KASSERT(cmd != NULL, -+ ("hifn_intr: null command slot %u", i)); -+ dma->hifn_commands[i] = NULL; -+ -+ if (cmd->base_masks & HIFN_BASE_CMD_MAC) { -+ macbuf = dma->result_bufs[i]; -+ macbuf += 12; -+ } -+ -+ hifn_callback(sc, cmd, macbuf); -+ hifnstats.hst_opackets++; -+ u--; -+ } -+ -+ if (++i == (HIFN_D_RES_RSIZE + 1)) -+ i = 0; -+ } -+ dma->resk = i; dma->resu = u; -+ -+ i = dma->srck; u = dma->srcu; -+ while (u != 0) { -+ if (i == HIFN_D_SRC_RSIZE) -+ i = 0; -+ HIFN_SRCR_SYNC(sc, i, -+ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); -+ if (dma->srcr[i].l & htole32(HIFN_D_VALID)) { -+ HIFN_SRCR_SYNC(sc, i, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ break; -+ } -+ i++, u--; -+ } -+ dma->srck = i; dma->srcu = u; -+ -+ i = dma->cmdk; u = dma->cmdu; -+ while (u != 0) { -+ HIFN_CMDR_SYNC(sc, i, -+ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); -+ if (dma->cmdr[i].l & htole32(HIFN_D_VALID)) { -+ HIFN_CMDR_SYNC(sc, i, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ break; -+ } -+ if (i != HIFN_D_CMD_RSIZE) { -+ u--; -+ HIFN_CMD_SYNC(sc, i, BUS_DMASYNC_POSTWRITE); -+ } -+ if (++i == (HIFN_D_CMD_RSIZE + 1)) -+ i = 0; -+ } -+ dma->cmdk = i; dma->cmdu = u; -+ -+ HIFN_UNLOCK(sc); -+ -+ if (sc->sc_needwakeup) { /* XXX check high watermark */ -+ int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); -+#ifdef HIFN_DEBUG -+ if (hifn_debug) -+ device_printf(sc->sc_dev, -+ "wakeup crypto (%x) u %d/%d/%d/%d\n", -+ sc->sc_needwakeup, -+ dma->cmdu, dma->srcu, dma->dstu, dma->resu); -+#endif -+ sc->sc_needwakeup &= ~wakeup; -+ crypto_unblock(sc->sc_cid, wakeup); -+ } -+ -+ return IRQ_HANDLED; -+} -+ -+/* -+ * Allocate a new 'session' and return an encoded session id. 'sidp' -+ * contains our registration id, and should contain an encoded session -+ * id on successful allocation. -+ */ -+static int -+hifn_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) -+{ -+ struct hifn_softc *sc = device_get_softc(dev); -+ struct cryptoini *c; -+ int mac = 0, cry = 0, sesn; -+ struct hifn_session *ses = NULL; -+ unsigned long l_flags; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ KASSERT(sc != NULL, ("hifn_newsession: null softc")); -+ if (sidp == NULL || cri == NULL || sc == NULL) { -+ DPRINTF("%s,%d: %s - EINVAL\n", __FILE__, __LINE__, __FUNCTION__); -+ return (EINVAL); -+ } -+ -+ HIFN_LOCK(sc); -+ if (sc->sc_sessions == NULL) { -+ ses = sc->sc_sessions = (struct hifn_session *)kmalloc(sizeof(*ses), -+ SLAB_ATOMIC); -+ if (ses == NULL) { -+ HIFN_UNLOCK(sc); -+ return (ENOMEM); -+ } -+ sesn = 0; -+ sc->sc_nsessions = 1; -+ } else { -+ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { -+ if (!sc->sc_sessions[sesn].hs_used) { -+ ses = &sc->sc_sessions[sesn]; -+ break; -+ } -+ } -+ -+ if (ses == NULL) { -+ sesn = sc->sc_nsessions; -+ ses = (struct hifn_session *)kmalloc((sesn + 1) * sizeof(*ses), -+ SLAB_ATOMIC); -+ if (ses == NULL) { -+ HIFN_UNLOCK(sc); -+ return (ENOMEM); -+ } -+ bcopy(sc->sc_sessions, ses, sesn * sizeof(*ses)); -+ bzero(sc->sc_sessions, sesn * sizeof(*ses)); -+ kfree(sc->sc_sessions); -+ sc->sc_sessions = ses; -+ ses = &sc->sc_sessions[sesn]; -+ sc->sc_nsessions++; -+ } -+ } -+ HIFN_UNLOCK(sc); -+ -+ bzero(ses, sizeof(*ses)); -+ ses->hs_used = 1; -+ -+ for (c = cri; c != NULL; c = c->cri_next) { -+ switch (c->cri_alg) { -+ case CRYPTO_MD5: -+ case CRYPTO_SHA1: -+ case CRYPTO_MD5_HMAC: -+ case CRYPTO_SHA1_HMAC: -+ if (mac) { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ return (EINVAL); -+ } -+ mac = 1; -+ ses->hs_mlen = c->cri_mlen; -+ if (ses->hs_mlen == 0) { -+ switch (c->cri_alg) { -+ case CRYPTO_MD5: -+ case CRYPTO_MD5_HMAC: -+ ses->hs_mlen = 16; -+ break; -+ case CRYPTO_SHA1: -+ case CRYPTO_SHA1_HMAC: -+ ses->hs_mlen = 20; -+ break; -+ } -+ } -+ break; -+ case CRYPTO_DES_CBC: -+ case CRYPTO_3DES_CBC: -+ case CRYPTO_AES_CBC: -+ case CRYPTO_ARC4: -+ if (cry) { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ return (EINVAL); -+ } -+ cry = 1; -+ break; -+ default: -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ return (EINVAL); -+ } -+ } -+ if (mac == 0 && cry == 0) { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ return (EINVAL); -+ } -+ -+ *sidp = HIFN_SID(device_get_unit(sc->sc_dev), sesn); -+ -+ return (0); -+} -+ -+/* -+ * Deallocate a session. -+ * XXX this routine should run a zero'd mac/encrypt key into context ram. -+ * XXX to blow away any keys already stored there. -+ */ -+static int -+hifn_freesession(device_t dev, u_int64_t tid) -+{ -+ struct hifn_softc *sc = device_get_softc(dev); -+ int session, error; -+ u_int32_t sid = CRYPTO_SESID2LID(tid); -+ unsigned long l_flags; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ KASSERT(sc != NULL, ("hifn_freesession: null softc")); -+ if (sc == NULL) { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ return (EINVAL); -+ } -+ -+ HIFN_LOCK(sc); -+ session = HIFN_SESSION(sid); -+ if (session < sc->sc_nsessions) { -+ bzero(&sc->sc_sessions[session], sizeof(struct hifn_session)); -+ error = 0; -+ } else { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ error = EINVAL; -+ } -+ HIFN_UNLOCK(sc); -+ -+ return (error); -+} -+ -+static int -+hifn_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ struct hifn_softc *sc = device_get_softc(dev); -+ struct hifn_command *cmd = NULL; -+ int session, err, ivlen; -+ struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (crp == NULL || crp->crp_callback == NULL) { -+ hifnstats.hst_invalid++; -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ return (EINVAL); -+ } -+ session = HIFN_SESSION(crp->crp_sid); -+ -+ if (sc == NULL || session >= sc->sc_nsessions) { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ err = EINVAL; -+ goto errout; -+ } -+ -+ cmd = kmalloc(sizeof(struct hifn_command), SLAB_ATOMIC); -+ if (cmd == NULL) { -+ hifnstats.hst_nomem++; -+ err = ENOMEM; -+ goto errout; -+ } -+ memset(cmd, 0, sizeof(*cmd)); -+ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ cmd->src_skb = (struct sk_buff *)crp->crp_buf; -+ cmd->dst_skb = (struct sk_buff *)crp->crp_buf; -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ cmd->src_io = (struct uio *)crp->crp_buf; -+ cmd->dst_io = (struct uio *)crp->crp_buf; -+ } else { -+ cmd->src_buf = crp->crp_buf; -+ cmd->dst_buf = crp->crp_buf; -+ } -+ -+ crd1 = crp->crp_desc; -+ if (crd1 == NULL) { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ err = EINVAL; -+ goto errout; -+ } -+ crd2 = crd1->crd_next; -+ -+ if (crd2 == NULL) { -+ if (crd1->crd_alg == CRYPTO_MD5_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1 || -+ crd1->crd_alg == CRYPTO_MD5) { -+ maccrd = crd1; -+ enccrd = NULL; -+ } else if (crd1->crd_alg == CRYPTO_DES_CBC || -+ crd1->crd_alg == CRYPTO_3DES_CBC || -+ crd1->crd_alg == CRYPTO_AES_CBC || -+ crd1->crd_alg == CRYPTO_ARC4) { -+ if ((crd1->crd_flags & CRD_F_ENCRYPT) == 0) -+ cmd->base_masks |= HIFN_BASE_CMD_DECODE; -+ maccrd = NULL; -+ enccrd = crd1; -+ } else { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ err = EINVAL; -+ goto errout; -+ } -+ } else { -+ if ((crd1->crd_alg == CRYPTO_MD5_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1_HMAC || -+ crd1->crd_alg == CRYPTO_MD5 || -+ crd1->crd_alg == CRYPTO_SHA1) && -+ (crd2->crd_alg == CRYPTO_DES_CBC || -+ crd2->crd_alg == CRYPTO_3DES_CBC || -+ crd2->crd_alg == CRYPTO_AES_CBC || -+ crd2->crd_alg == CRYPTO_ARC4) && -+ ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { -+ cmd->base_masks = HIFN_BASE_CMD_DECODE; -+ maccrd = crd1; -+ enccrd = crd2; -+ } else if ((crd1->crd_alg == CRYPTO_DES_CBC || -+ crd1->crd_alg == CRYPTO_ARC4 || -+ crd1->crd_alg == CRYPTO_3DES_CBC || -+ crd1->crd_alg == CRYPTO_AES_CBC) && -+ (crd2->crd_alg == CRYPTO_MD5_HMAC || -+ crd2->crd_alg == CRYPTO_SHA1_HMAC || -+ crd2->crd_alg == CRYPTO_MD5 || -+ crd2->crd_alg == CRYPTO_SHA1) && -+ (crd1->crd_flags & CRD_F_ENCRYPT)) { -+ enccrd = crd1; -+ maccrd = crd2; -+ } else { -+ /* -+ * We cannot order the 7751 as requested -+ */ -+ DPRINTF("%s,%d: %s %d,%d,%d - EINVAL\n",__FILE__,__LINE__,__FUNCTION__, crd1->crd_alg, crd2->crd_alg, crd1->crd_flags & CRD_F_ENCRYPT); -+ err = EINVAL; -+ goto errout; -+ } -+ } -+ -+ if (enccrd) { -+ cmd->enccrd = enccrd; -+ cmd->base_masks |= HIFN_BASE_CMD_CRYPT; -+ switch (enccrd->crd_alg) { -+ case CRYPTO_ARC4: -+ cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_RC4; -+ break; -+ case CRYPTO_DES_CBC: -+ cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_DES | -+ HIFN_CRYPT_CMD_MODE_CBC | -+ HIFN_CRYPT_CMD_NEW_IV; -+ break; -+ case CRYPTO_3DES_CBC: -+ cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_3DES | -+ HIFN_CRYPT_CMD_MODE_CBC | -+ HIFN_CRYPT_CMD_NEW_IV; -+ break; -+ case CRYPTO_AES_CBC: -+ cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_AES | -+ HIFN_CRYPT_CMD_MODE_CBC | -+ HIFN_CRYPT_CMD_NEW_IV; -+ break; -+ default: -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ err = EINVAL; -+ goto errout; -+ } -+ if (enccrd->crd_alg != CRYPTO_ARC4) { -+ ivlen = ((enccrd->crd_alg == CRYPTO_AES_CBC) ? -+ HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH); -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) { -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) -+ bcopy(enccrd->crd_iv, cmd->iv, ivlen); -+ else -+ read_random(cmd->iv, ivlen); -+ -+ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) -+ == 0) { -+ crypto_copyback(crp->crp_flags, -+ crp->crp_buf, enccrd->crd_inject, -+ ivlen, cmd->iv); -+ } -+ } else { -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) -+ bcopy(enccrd->crd_iv, cmd->iv, ivlen); -+ else { -+ crypto_copydata(crp->crp_flags, -+ crp->crp_buf, enccrd->crd_inject, -+ ivlen, cmd->iv); -+ } -+ } -+ } -+ -+ if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) -+ cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY; -+ cmd->ck = enccrd->crd_key; -+ cmd->cklen = enccrd->crd_klen >> 3; -+ cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY; -+ -+ /* -+ * Need to specify the size for the AES key in the masks. -+ */ -+ if ((cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) == -+ HIFN_CRYPT_CMD_ALG_AES) { -+ switch (cmd->cklen) { -+ case 16: -+ cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_128; -+ break; -+ case 24: -+ cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_192; -+ break; -+ case 32: -+ cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_256; -+ break; -+ default: -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ err = EINVAL; -+ goto errout; -+ } -+ } -+ } -+ -+ if (maccrd) { -+ cmd->maccrd = maccrd; -+ cmd->base_masks |= HIFN_BASE_CMD_MAC; -+ -+ switch (maccrd->crd_alg) { -+ case CRYPTO_MD5: -+ cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | -+ HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | -+ HIFN_MAC_CMD_POS_IPSEC; -+ break; -+ case CRYPTO_MD5_HMAC: -+ cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | -+ HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | -+ HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; -+ break; -+ case CRYPTO_SHA1: -+ cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | -+ HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | -+ HIFN_MAC_CMD_POS_IPSEC; -+ break; -+ case CRYPTO_SHA1_HMAC: -+ cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | -+ HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | -+ HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; -+ break; -+ } -+ -+ if (maccrd->crd_alg == CRYPTO_SHA1_HMAC || -+ maccrd->crd_alg == CRYPTO_MD5_HMAC) { -+ cmd->mac_masks |= HIFN_MAC_CMD_NEW_KEY; -+ bcopy(maccrd->crd_key, cmd->mac, maccrd->crd_klen >> 3); -+ bzero(cmd->mac + (maccrd->crd_klen >> 3), -+ HIFN_MAC_KEY_LENGTH - (maccrd->crd_klen >> 3)); -+ } -+ } -+ -+ cmd->crp = crp; -+ cmd->session_num = session; -+ cmd->softc = sc; -+ -+ err = hifn_crypto(sc, cmd, crp, hint); -+ if (!err) { -+ return 0; -+ } else if (err == ERESTART) { -+ /* -+ * There weren't enough resources to dispatch the request -+ * to the part. Notify the caller so they'll requeue this -+ * request and resubmit it again soon. -+ */ -+#ifdef HIFN_DEBUG -+ if (hifn_debug) -+ device_printf(sc->sc_dev, "requeue request\n"); -+#endif -+ kfree(cmd); -+ sc->sc_needwakeup |= CRYPTO_SYMQ; -+ return (err); -+ } -+ -+errout: -+ if (cmd != NULL) -+ kfree(cmd); -+ if (err == EINVAL) -+ hifnstats.hst_invalid++; -+ else -+ hifnstats.hst_nomem++; -+ crp->crp_etype = err; -+ crypto_done(crp); -+ return (err); -+} -+ -+static void -+hifn_abort(struct hifn_softc *sc) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ struct hifn_command *cmd; -+ struct cryptop *crp; -+ int i, u; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ i = dma->resk; u = dma->resu; -+ while (u != 0) { -+ cmd = dma->hifn_commands[i]; -+ KASSERT(cmd != NULL, ("hifn_abort: null command slot %u", i)); -+ dma->hifn_commands[i] = NULL; -+ crp = cmd->crp; -+ -+ if ((dma->resr[i].l & htole32(HIFN_D_VALID)) == 0) { -+ /* Salvage what we can. */ -+ u_int8_t *macbuf; -+ -+ if (cmd->base_masks & HIFN_BASE_CMD_MAC) { -+ macbuf = dma->result_bufs[i]; -+ macbuf += 12; -+ } else -+ macbuf = NULL; -+ hifnstats.hst_opackets++; -+ hifn_callback(sc, cmd, macbuf); -+ } else { -+#if 0 -+ if (cmd->src_map == cmd->dst_map) { -+ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, -+ BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); -+ } else { -+ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, -+ BUS_DMASYNC_POSTWRITE); -+ bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, -+ BUS_DMASYNC_POSTREAD); -+ } -+#endif -+ -+ if (cmd->src_skb != cmd->dst_skb) { -+#ifdef NOTYET -+ m_freem(cmd->src_m); -+ crp->crp_buf = (caddr_t)cmd->dst_m; -+#else -+ device_printf(sc->sc_dev, -+ "%s,%d: CRYPTO_F_SKBUF src != dst not implemented\n", -+ __FILE__, __LINE__); -+#endif -+ } -+ -+ /* non-shared buffers cannot be restarted */ -+ if (cmd->src_map != cmd->dst_map) { -+ /* -+ * XXX should be EAGAIN, delayed until -+ * after the reset. -+ */ -+ crp->crp_etype = ENOMEM; -+ pci_unmap_buf(sc, &cmd->dst); -+ } else -+ crp->crp_etype = ENOMEM; -+ -+ pci_unmap_buf(sc, &cmd->src); -+ -+ kfree(cmd); -+ if (crp->crp_etype != EAGAIN) -+ crypto_done(crp); -+ } -+ -+ if (++i == HIFN_D_RES_RSIZE) -+ i = 0; -+ u--; -+ } -+ dma->resk = i; dma->resu = u; -+ -+ hifn_reset_board(sc, 1); -+ hifn_init_dma(sc); -+ hifn_init_pci_registers(sc); -+} -+ -+static void -+hifn_callback(struct hifn_softc *sc, struct hifn_command *cmd, u_int8_t *macbuf) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ struct cryptop *crp = cmd->crp; -+ struct cryptodesc *crd; -+ int i, u; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+#if 0 -+ if (cmd->src_map == cmd->dst_map) { -+ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, -+ BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); -+ } else { -+ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, -+ BUS_DMASYNC_POSTWRITE); -+ bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, -+ BUS_DMASYNC_POSTREAD); -+ } -+#endif -+ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ if (cmd->src_skb != cmd->dst_skb) { -+#ifdef NOTYET -+ crp->crp_buf = (caddr_t)cmd->dst_m; -+ totlen = cmd->src_mapsize; -+ for (m = cmd->dst_m; m != NULL; m = m->m_next) { -+ if (totlen < m->m_len) { -+ m->m_len = totlen; -+ totlen = 0; -+ } else -+ totlen -= m->m_len; -+ } -+ cmd->dst_m->m_pkthdr.len = cmd->src_m->m_pkthdr.len; -+ m_freem(cmd->src_m); -+#else -+ device_printf(sc->sc_dev, -+ "%s,%d: CRYPTO_F_SKBUF src != dst not implemented\n", -+ __FILE__, __LINE__); -+#endif -+ } -+ } -+ -+ if (cmd->sloplen != 0) { -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ cmd->src_mapsize - cmd->sloplen, cmd->sloplen, -+ (caddr_t)&dma->slop[cmd->slopidx]); -+ } -+ -+ i = dma->dstk; u = dma->dstu; -+ while (u != 0) { -+ if (i == HIFN_D_DST_RSIZE) -+ i = 0; -+#if 0 -+ bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, -+ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); -+#endif -+ if (dma->dstr[i].l & htole32(HIFN_D_VALID)) { -+#if 0 -+ bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+#endif -+ break; -+ } -+ i++, u--; -+ } -+ dma->dstk = i; dma->dstu = u; -+ -+ hifnstats.hst_obytes += cmd->dst_mapsize; -+ -+ if (macbuf != NULL) { -+ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { -+ int len; -+ -+ if (crd->crd_alg != CRYPTO_MD5 && -+ crd->crd_alg != CRYPTO_SHA1 && -+ crd->crd_alg != CRYPTO_MD5_HMAC && -+ crd->crd_alg != CRYPTO_SHA1_HMAC) { -+ continue; -+ } -+ len = cmd->softc->sc_sessions[cmd->session_num].hs_mlen; -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, len, macbuf); -+ break; -+ } -+ } -+ -+ if (cmd->src_map != cmd->dst_map) -+ pci_unmap_buf(sc, &cmd->dst); -+ pci_unmap_buf(sc, &cmd->src); -+ kfree(cmd); -+ crypto_done(crp); -+} -+ -+/* -+ * 7811 PB3 rev/2 parts lock-up on burst writes to Group 0 -+ * and Group 1 registers; avoid conditions that could create -+ * burst writes by doing a read in between the writes. -+ * -+ * NB: The read we interpose is always to the same register; -+ * we do this because reading from an arbitrary (e.g. last) -+ * register may not always work. -+ */ -+static void -+hifn_write_reg_0(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) -+{ -+ if (sc->sc_flags & HIFN_IS_7811) { -+ if (sc->sc_bar0_lastreg == reg - 4) -+ readl(sc->sc_bar0 + HIFN_0_PUCNFG); -+ sc->sc_bar0_lastreg = reg; -+ } -+ writel(val, sc->sc_bar0 + reg); -+} -+ -+static void -+hifn_write_reg_1(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) -+{ -+ if (sc->sc_flags & HIFN_IS_7811) { -+ if (sc->sc_bar1_lastreg == reg - 4) -+ readl(sc->sc_bar1 + HIFN_1_REVID); -+ sc->sc_bar1_lastreg = reg; -+ } -+ writel(val, sc->sc_bar1 + reg); -+} -+ -+ -+static struct pci_device_id hifn_pci_tbl[] = { -+ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7951, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7955, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7956, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ { PCI_VENDOR_NETSEC, PCI_PRODUCT_NETSEC_7751, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ { PCI_VENDOR_INVERTEX, PCI_PRODUCT_INVERTEX_AEON, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7811, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ /* -+ * Other vendors share this PCI ID as well, such as -+ * http://www.powercrypt.com, and obviously they also -+ * use the same key. -+ */ -+ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7751, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ { 0, 0, 0, 0, 0, 0, } -+}; -+MODULE_DEVICE_TABLE(pci, hifn_pci_tbl); -+ -+static struct pci_driver hifn_driver = { -+ .name = "hifn", -+ .id_table = hifn_pci_tbl, -+ .probe = hifn_probe, -+ .remove = hifn_remove, -+ /* add PM stuff here one day */ -+}; -+ -+static int __init hifn_init (void) -+{ -+ struct hifn_softc *sc = NULL; -+ int rc; -+ -+ DPRINTF("%s(%p)\n", __FUNCTION__, hifn_init); -+ -+ rc = pci_register_driver(&hifn_driver); -+ pci_register_driver_compat(&hifn_driver, rc); -+ -+ return rc; -+} -+ -+static void __exit hifn_exit (void) -+{ -+ pci_unregister_driver(&hifn_driver); -+} -+ -+module_init(hifn_init); -+module_exit(hifn_exit); -+ -+MODULE_LICENSE("BSD"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("OCF driver for hifn PCI crypto devices"); -diff -Nur linux-3.0.4.orig/crypto/ocf/hifn/hifn7751reg.h linux-3.0.4/crypto/ocf/hifn/hifn7751reg.h ---- linux-3.0.4.orig/crypto/ocf/hifn/hifn7751reg.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/hifn/hifn7751reg.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,540 @@ -+/* $FreeBSD: src/sys/dev/hifn/hifn7751reg.h,v 1.7 2007/03/21 03:42:49 sam Exp $ */ -+/* $OpenBSD: hifn7751reg.h,v 1.35 2002/04/08 17:49:42 jason Exp $ */ -+ -+/*- -+ * Invertex AEON / Hifn 7751 driver -+ * Copyright (c) 1999 Invertex Inc. All rights reserved. -+ * Copyright (c) 1999 Theo de Raadt -+ * Copyright (c) 2000-2001 Network Security Technologies, Inc. -+ * http://www.netsec.net -+ * -+ * Please send any comments, feedback, bug-fixes, or feature requests to -+ * software@invertex.com. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored in part by the Defense Advanced Research Projects -+ * Agency (DARPA) and Air Force Research Laboratory, Air Force -+ * Materiel Command, USAF, under agreement number F30602-01-2-0537. -+ * -+ */ -+#ifndef __HIFN_H__ -+#define __HIFN_H__ -+ -+/* -+ * Some PCI configuration space offset defines. The names were made -+ * identical to the names used by the Linux kernel. -+ */ -+#define HIFN_BAR0 PCIR_BAR(0) /* PUC register map */ -+#define HIFN_BAR1 PCIR_BAR(1) /* DMA register map */ -+#define HIFN_TRDY_TIMEOUT 0x40 -+#define HIFN_RETRY_TIMEOUT 0x41 -+ -+/* -+ * PCI vendor and device identifiers -+ * (the names are preserved from their OpenBSD source). -+ */ -+#define PCI_VENDOR_HIFN 0x13a3 /* Hifn */ -+#define PCI_PRODUCT_HIFN_7751 0x0005 /* 7751 */ -+#define PCI_PRODUCT_HIFN_6500 0x0006 /* 6500 */ -+#define PCI_PRODUCT_HIFN_7811 0x0007 /* 7811 */ -+#define PCI_PRODUCT_HIFN_7855 0x001f /* 7855 */ -+#define PCI_PRODUCT_HIFN_7951 0x0012 /* 7951 */ -+#define PCI_PRODUCT_HIFN_7955 0x0020 /* 7954/7955 */ -+#define PCI_PRODUCT_HIFN_7956 0x001d /* 7956 */ -+ -+#define PCI_VENDOR_INVERTEX 0x14e1 /* Invertex */ -+#define PCI_PRODUCT_INVERTEX_AEON 0x0005 /* AEON */ -+ -+#define PCI_VENDOR_NETSEC 0x1660 /* NetSec */ -+#define PCI_PRODUCT_NETSEC_7751 0x7751 /* 7751 */ -+ -+/* -+ * The values below should multiple of 4 -- and be large enough to handle -+ * any command the driver implements. -+ * -+ * MAX_COMMAND = base command + mac command + encrypt command + -+ * mac-key + rc4-key -+ * MAX_RESULT = base result + mac result + mac + encrypt result -+ * -+ * -+ */ -+#define HIFN_MAX_COMMAND (8 + 8 + 8 + 64 + 260) -+#define HIFN_MAX_RESULT (8 + 4 + 20 + 4) -+ -+/* -+ * hifn_desc_t -+ * -+ * Holds an individual descriptor for any of the rings. -+ */ -+typedef struct hifn_desc { -+ volatile u_int32_t l; /* length and status bits */ -+ volatile u_int32_t p; -+} hifn_desc_t; -+ -+/* -+ * Masks for the "length" field of struct hifn_desc. -+ */ -+#define HIFN_D_LENGTH 0x0000ffff /* length bit mask */ -+#define HIFN_D_MASKDONEIRQ 0x02000000 /* mask the done interrupt */ -+#define HIFN_D_DESTOVER 0x04000000 /* destination overflow */ -+#define HIFN_D_OVER 0x08000000 /* overflow */ -+#define HIFN_D_LAST 0x20000000 /* last descriptor in chain */ -+#define HIFN_D_JUMP 0x40000000 /* jump descriptor */ -+#define HIFN_D_VALID 0x80000000 /* valid bit */ -+ -+ -+/* -+ * Processing Unit Registers (offset from BASEREG0) -+ */ -+#define HIFN_0_PUDATA 0x00 /* Processing Unit Data */ -+#define HIFN_0_PUCTRL 0x04 /* Processing Unit Control */ -+#define HIFN_0_PUISR 0x08 /* Processing Unit Interrupt Status */ -+#define HIFN_0_PUCNFG 0x0c /* Processing Unit Configuration */ -+#define HIFN_0_PUIER 0x10 /* Processing Unit Interrupt Enable */ -+#define HIFN_0_PUSTAT 0x14 /* Processing Unit Status/Chip ID */ -+#define HIFN_0_FIFOSTAT 0x18 /* FIFO Status */ -+#define HIFN_0_FIFOCNFG 0x1c /* FIFO Configuration */ -+#define HIFN_0_PUCTRL2 0x28 /* Processing Unit Control (2nd map) */ -+#define HIFN_0_MUTE1 0x80 -+#define HIFN_0_MUTE2 0x90 -+#define HIFN_0_SPACESIZE 0x100 /* Register space size */ -+ -+/* Processing Unit Control Register (HIFN_0_PUCTRL) */ -+#define HIFN_PUCTRL_CLRSRCFIFO 0x0010 /* clear source fifo */ -+#define HIFN_PUCTRL_STOP 0x0008 /* stop pu */ -+#define HIFN_PUCTRL_LOCKRAM 0x0004 /* lock ram */ -+#define HIFN_PUCTRL_DMAENA 0x0002 /* enable dma */ -+#define HIFN_PUCTRL_RESET 0x0001 /* Reset processing unit */ -+ -+/* Processing Unit Interrupt Status Register (HIFN_0_PUISR) */ -+#define HIFN_PUISR_CMDINVAL 0x8000 /* Invalid command interrupt */ -+#define HIFN_PUISR_DATAERR 0x4000 /* Data error interrupt */ -+#define HIFN_PUISR_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ -+#define HIFN_PUISR_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ -+#define HIFN_PUISR_DSTOVER 0x0200 /* Destination overrun interrupt */ -+#define HIFN_PUISR_SRCCMD 0x0080 /* Source command interrupt */ -+#define HIFN_PUISR_SRCCTX 0x0040 /* Source context interrupt */ -+#define HIFN_PUISR_SRCDATA 0x0020 /* Source data interrupt */ -+#define HIFN_PUISR_DSTDATA 0x0010 /* Destination data interrupt */ -+#define HIFN_PUISR_DSTRESULT 0x0004 /* Destination result interrupt */ -+ -+/* Processing Unit Configuration Register (HIFN_0_PUCNFG) */ -+#define HIFN_PUCNFG_DRAMMASK 0xe000 /* DRAM size mask */ -+#define HIFN_PUCNFG_DSZ_256K 0x0000 /* 256k dram */ -+#define HIFN_PUCNFG_DSZ_512K 0x2000 /* 512k dram */ -+#define HIFN_PUCNFG_DSZ_1M 0x4000 /* 1m dram */ -+#define HIFN_PUCNFG_DSZ_2M 0x6000 /* 2m dram */ -+#define HIFN_PUCNFG_DSZ_4M 0x8000 /* 4m dram */ -+#define HIFN_PUCNFG_DSZ_8M 0xa000 /* 8m dram */ -+#define HIFN_PUNCFG_DSZ_16M 0xc000 /* 16m dram */ -+#define HIFN_PUCNFG_DSZ_32M 0xe000 /* 32m dram */ -+#define HIFN_PUCNFG_DRAMREFRESH 0x1800 /* DRAM refresh rate mask */ -+#define HIFN_PUCNFG_DRFR_512 0x0000 /* 512 divisor of ECLK */ -+#define HIFN_PUCNFG_DRFR_256 0x0800 /* 256 divisor of ECLK */ -+#define HIFN_PUCNFG_DRFR_128 0x1000 /* 128 divisor of ECLK */ -+#define HIFN_PUCNFG_TCALLPHASES 0x0200 /* your guess is as good as mine... */ -+#define HIFN_PUCNFG_TCDRVTOTEM 0x0100 /* your guess is as good as mine... */ -+#define HIFN_PUCNFG_BIGENDIAN 0x0080 /* DMA big endian mode */ -+#define HIFN_PUCNFG_BUS32 0x0040 /* Bus width 32bits */ -+#define HIFN_PUCNFG_BUS16 0x0000 /* Bus width 16 bits */ -+#define HIFN_PUCNFG_CHIPID 0x0020 /* Allow chipid from PUSTAT */ -+#define HIFN_PUCNFG_DRAM 0x0010 /* Context RAM is DRAM */ -+#define HIFN_PUCNFG_SRAM 0x0000 /* Context RAM is SRAM */ -+#define HIFN_PUCNFG_COMPSING 0x0004 /* Enable single compression context */ -+#define HIFN_PUCNFG_ENCCNFG 0x0002 /* Encryption configuration */ -+ -+/* Processing Unit Interrupt Enable Register (HIFN_0_PUIER) */ -+#define HIFN_PUIER_CMDINVAL 0x8000 /* Invalid command interrupt */ -+#define HIFN_PUIER_DATAERR 0x4000 /* Data error interrupt */ -+#define HIFN_PUIER_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ -+#define HIFN_PUIER_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ -+#define HIFN_PUIER_DSTOVER 0x0200 /* Destination overrun interrupt */ -+#define HIFN_PUIER_SRCCMD 0x0080 /* Source command interrupt */ -+#define HIFN_PUIER_SRCCTX 0x0040 /* Source context interrupt */ -+#define HIFN_PUIER_SRCDATA 0x0020 /* Source data interrupt */ -+#define HIFN_PUIER_DSTDATA 0x0010 /* Destination data interrupt */ -+#define HIFN_PUIER_DSTRESULT 0x0004 /* Destination result interrupt */ -+ -+/* Processing Unit Status Register/Chip ID (HIFN_0_PUSTAT) */ -+#define HIFN_PUSTAT_CMDINVAL 0x8000 /* Invalid command interrupt */ -+#define HIFN_PUSTAT_DATAERR 0x4000 /* Data error interrupt */ -+#define HIFN_PUSTAT_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ -+#define HIFN_PUSTAT_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ -+#define HIFN_PUSTAT_DSTOVER 0x0200 /* Destination overrun interrupt */ -+#define HIFN_PUSTAT_SRCCMD 0x0080 /* Source command interrupt */ -+#define HIFN_PUSTAT_SRCCTX 0x0040 /* Source context interrupt */ -+#define HIFN_PUSTAT_SRCDATA 0x0020 /* Source data interrupt */ -+#define HIFN_PUSTAT_DSTDATA 0x0010 /* Destination data interrupt */ -+#define HIFN_PUSTAT_DSTRESULT 0x0004 /* Destination result interrupt */ -+#define HIFN_PUSTAT_CHIPREV 0x00ff /* Chip revision mask */ -+#define HIFN_PUSTAT_CHIPENA 0xff00 /* Chip enabled mask */ -+#define HIFN_PUSTAT_ENA_2 0x1100 /* Level 2 enabled */ -+#define HIFN_PUSTAT_ENA_1 0x1000 /* Level 1 enabled */ -+#define HIFN_PUSTAT_ENA_0 0x3000 /* Level 0 enabled */ -+#define HIFN_PUSTAT_REV_2 0x0020 /* 7751 PT6/2 */ -+#define HIFN_PUSTAT_REV_3 0x0030 /* 7751 PT6/3 */ -+ -+/* FIFO Status Register (HIFN_0_FIFOSTAT) */ -+#define HIFN_FIFOSTAT_SRC 0x7f00 /* Source FIFO available */ -+#define HIFN_FIFOSTAT_DST 0x007f /* Destination FIFO available */ -+ -+/* FIFO Configuration Register (HIFN_0_FIFOCNFG) */ -+#define HIFN_FIFOCNFG_THRESHOLD 0x0400 /* must be written as this value */ -+ -+/* -+ * DMA Interface Registers (offset from BASEREG1) -+ */ -+#define HIFN_1_DMA_CRAR 0x0c /* DMA Command Ring Address */ -+#define HIFN_1_DMA_SRAR 0x1c /* DMA Source Ring Address */ -+#define HIFN_1_DMA_RRAR 0x2c /* DMA Result Ring Address */ -+#define HIFN_1_DMA_DRAR 0x3c /* DMA Destination Ring Address */ -+#define HIFN_1_DMA_CSR 0x40 /* DMA Status and Control */ -+#define HIFN_1_DMA_IER 0x44 /* DMA Interrupt Enable */ -+#define HIFN_1_DMA_CNFG 0x48 /* DMA Configuration */ -+#define HIFN_1_PLL 0x4c /* 7955/7956: PLL config */ -+#define HIFN_1_7811_RNGENA 0x60 /* 7811: rng enable */ -+#define HIFN_1_7811_RNGCFG 0x64 /* 7811: rng config */ -+#define HIFN_1_7811_RNGDAT 0x68 /* 7811: rng data */ -+#define HIFN_1_7811_RNGSTS 0x6c /* 7811: rng status */ -+#define HIFN_1_DMA_CNFG2 0x6c /* 7955/7956: dma config #2 */ -+#define HIFN_1_7811_MIPSRST 0x94 /* 7811: MIPS reset */ -+#define HIFN_1_REVID 0x98 /* Revision ID */ -+ -+#define HIFN_1_PUB_RESET 0x204 /* Public/RNG Reset */ -+#define HIFN_1_PUB_BASE 0x300 /* Public Base Address */ -+#define HIFN_1_PUB_OPLEN 0x304 /* 7951-compat Public Operand Length */ -+#define HIFN_1_PUB_OP 0x308 /* 7951-compat Public Operand */ -+#define HIFN_1_PUB_STATUS 0x30c /* 7951-compat Public Status */ -+#define HIFN_1_PUB_IEN 0x310 /* Public Interrupt enable */ -+#define HIFN_1_RNG_CONFIG 0x314 /* RNG config */ -+#define HIFN_1_RNG_DATA 0x318 /* RNG data */ -+#define HIFN_1_PUB_MODE 0x320 /* PK mode */ -+#define HIFN_1_PUB_FIFO_OPLEN 0x380 /* first element of oplen fifo */ -+#define HIFN_1_PUB_FIFO_OP 0x384 /* first element of op fifo */ -+#define HIFN_1_PUB_MEM 0x400 /* start of Public key memory */ -+#define HIFN_1_PUB_MEMEND 0xbff /* end of Public key memory */ -+ -+/* DMA Status and Control Register (HIFN_1_DMA_CSR) */ -+#define HIFN_DMACSR_D_CTRLMASK 0xc0000000 /* Destinition Ring Control */ -+#define HIFN_DMACSR_D_CTRL_NOP 0x00000000 /* Dest. Control: no-op */ -+#define HIFN_DMACSR_D_CTRL_DIS 0x40000000 /* Dest. Control: disable */ -+#define HIFN_DMACSR_D_CTRL_ENA 0x80000000 /* Dest. Control: enable */ -+#define HIFN_DMACSR_D_ABORT 0x20000000 /* Destinition Ring PCIAbort */ -+#define HIFN_DMACSR_D_DONE 0x10000000 /* Destinition Ring Done */ -+#define HIFN_DMACSR_D_LAST 0x08000000 /* Destinition Ring Last */ -+#define HIFN_DMACSR_D_WAIT 0x04000000 /* Destinition Ring Waiting */ -+#define HIFN_DMACSR_D_OVER 0x02000000 /* Destinition Ring Overflow */ -+#define HIFN_DMACSR_R_CTRL 0x00c00000 /* Result Ring Control */ -+#define HIFN_DMACSR_R_CTRL_NOP 0x00000000 /* Result Control: no-op */ -+#define HIFN_DMACSR_R_CTRL_DIS 0x00400000 /* Result Control: disable */ -+#define HIFN_DMACSR_R_CTRL_ENA 0x00800000 /* Result Control: enable */ -+#define HIFN_DMACSR_R_ABORT 0x00200000 /* Result Ring PCI Abort */ -+#define HIFN_DMACSR_R_DONE 0x00100000 /* Result Ring Done */ -+#define HIFN_DMACSR_R_LAST 0x00080000 /* Result Ring Last */ -+#define HIFN_DMACSR_R_WAIT 0x00040000 /* Result Ring Waiting */ -+#define HIFN_DMACSR_R_OVER 0x00020000 /* Result Ring Overflow */ -+#define HIFN_DMACSR_S_CTRL 0x0000c000 /* Source Ring Control */ -+#define HIFN_DMACSR_S_CTRL_NOP 0x00000000 /* Source Control: no-op */ -+#define HIFN_DMACSR_S_CTRL_DIS 0x00004000 /* Source Control: disable */ -+#define HIFN_DMACSR_S_CTRL_ENA 0x00008000 /* Source Control: enable */ -+#define HIFN_DMACSR_S_ABORT 0x00002000 /* Source Ring PCI Abort */ -+#define HIFN_DMACSR_S_DONE 0x00001000 /* Source Ring Done */ -+#define HIFN_DMACSR_S_LAST 0x00000800 /* Source Ring Last */ -+#define HIFN_DMACSR_S_WAIT 0x00000400 /* Source Ring Waiting */ -+#define HIFN_DMACSR_ILLW 0x00000200 /* Illegal write (7811 only) */ -+#define HIFN_DMACSR_ILLR 0x00000100 /* Illegal read (7811 only) */ -+#define HIFN_DMACSR_C_CTRL 0x000000c0 /* Command Ring Control */ -+#define HIFN_DMACSR_C_CTRL_NOP 0x00000000 /* Command Control: no-op */ -+#define HIFN_DMACSR_C_CTRL_DIS 0x00000040 /* Command Control: disable */ -+#define HIFN_DMACSR_C_CTRL_ENA 0x00000080 /* Command Control: enable */ -+#define HIFN_DMACSR_C_ABORT 0x00000020 /* Command Ring PCI Abort */ -+#define HIFN_DMACSR_C_DONE 0x00000010 /* Command Ring Done */ -+#define HIFN_DMACSR_C_LAST 0x00000008 /* Command Ring Last */ -+#define HIFN_DMACSR_C_WAIT 0x00000004 /* Command Ring Waiting */ -+#define HIFN_DMACSR_PUBDONE 0x00000002 /* Public op done (7951 only) */ -+#define HIFN_DMACSR_ENGINE 0x00000001 /* Command Ring Engine IRQ */ -+ -+/* DMA Interrupt Enable Register (HIFN_1_DMA_IER) */ -+#define HIFN_DMAIER_D_ABORT 0x20000000 /* Destination Ring PCIAbort */ -+#define HIFN_DMAIER_D_DONE 0x10000000 /* Destination Ring Done */ -+#define HIFN_DMAIER_D_LAST 0x08000000 /* Destination Ring Last */ -+#define HIFN_DMAIER_D_WAIT 0x04000000 /* Destination Ring Waiting */ -+#define HIFN_DMAIER_D_OVER 0x02000000 /* Destination Ring Overflow */ -+#define HIFN_DMAIER_R_ABORT 0x00200000 /* Result Ring PCI Abort */ -+#define HIFN_DMAIER_R_DONE 0x00100000 /* Result Ring Done */ -+#define HIFN_DMAIER_R_LAST 0x00080000 /* Result Ring Last */ -+#define HIFN_DMAIER_R_WAIT 0x00040000 /* Result Ring Waiting */ -+#define HIFN_DMAIER_R_OVER 0x00020000 /* Result Ring Overflow */ -+#define HIFN_DMAIER_S_ABORT 0x00002000 /* Source Ring PCI Abort */ -+#define HIFN_DMAIER_S_DONE 0x00001000 /* Source Ring Done */ -+#define HIFN_DMAIER_S_LAST 0x00000800 /* Source Ring Last */ -+#define HIFN_DMAIER_S_WAIT 0x00000400 /* Source Ring Waiting */ -+#define HIFN_DMAIER_ILLW 0x00000200 /* Illegal write (7811 only) */ -+#define HIFN_DMAIER_ILLR 0x00000100 /* Illegal read (7811 only) */ -+#define HIFN_DMAIER_C_ABORT 0x00000020 /* Command Ring PCI Abort */ -+#define HIFN_DMAIER_C_DONE 0x00000010 /* Command Ring Done */ -+#define HIFN_DMAIER_C_LAST 0x00000008 /* Command Ring Last */ -+#define HIFN_DMAIER_C_WAIT 0x00000004 /* Command Ring Waiting */ -+#define HIFN_DMAIER_PUBDONE 0x00000002 /* public op done (7951 only) */ -+#define HIFN_DMAIER_ENGINE 0x00000001 /* Engine IRQ */ -+ -+/* DMA Configuration Register (HIFN_1_DMA_CNFG) */ -+#define HIFN_DMACNFG_BIGENDIAN 0x10000000 /* big endian mode */ -+#define HIFN_DMACNFG_POLLFREQ 0x00ff0000 /* Poll frequency mask */ -+#define HIFN_DMACNFG_UNLOCK 0x00000800 -+#define HIFN_DMACNFG_POLLINVAL 0x00000700 /* Invalid Poll Scalar */ -+#define HIFN_DMACNFG_LAST 0x00000010 /* Host control LAST bit */ -+#define HIFN_DMACNFG_MODE 0x00000004 /* DMA mode */ -+#define HIFN_DMACNFG_DMARESET 0x00000002 /* DMA Reset # */ -+#define HIFN_DMACNFG_MSTRESET 0x00000001 /* Master Reset # */ -+ -+/* DMA Configuration Register (HIFN_1_DMA_CNFG2) */ -+#define HIFN_DMACNFG2_PKSWAP32 (1 << 19) /* swap the OPLEN/OP reg */ -+#define HIFN_DMACNFG2_PKSWAP8 (1 << 18) /* swap the bits of OPLEN/OP */ -+#define HIFN_DMACNFG2_BAR0_SWAP32 (1<<17) /* swap the bytes of BAR0 */ -+#define HIFN_DMACNFG2_BAR1_SWAP8 (1<<16) /* swap the bits of BAR0 */ -+#define HIFN_DMACNFG2_INIT_WRITE_BURST_SHIFT 12 -+#define HIFN_DMACNFG2_INIT_READ_BURST_SHIFT 8 -+#define HIFN_DMACNFG2_TGT_WRITE_BURST_SHIFT 4 -+#define HIFN_DMACNFG2_TGT_READ_BURST_SHIFT 0 -+ -+/* 7811 RNG Enable Register (HIFN_1_7811_RNGENA) */ -+#define HIFN_7811_RNGENA_ENA 0x00000001 /* enable RNG */ -+ -+/* 7811 RNG Config Register (HIFN_1_7811_RNGCFG) */ -+#define HIFN_7811_RNGCFG_PRE1 0x00000f00 /* first prescalar */ -+#define HIFN_7811_RNGCFG_OPRE 0x00000080 /* output prescalar */ -+#define HIFN_7811_RNGCFG_DEFL 0x00000f80 /* 2 words/ 1/100 sec */ -+ -+/* 7811 RNG Status Register (HIFN_1_7811_RNGSTS) */ -+#define HIFN_7811_RNGSTS_RDY 0x00004000 /* two numbers in FIFO */ -+#define HIFN_7811_RNGSTS_UFL 0x00001000 /* rng underflow */ -+ -+/* 7811 MIPS Reset Register (HIFN_1_7811_MIPSRST) */ -+#define HIFN_MIPSRST_BAR2SIZE 0xffff0000 /* sdram size */ -+#define HIFN_MIPSRST_GPRAMINIT 0x00008000 /* gpram can be accessed */ -+#define HIFN_MIPSRST_CRAMINIT 0x00004000 /* ctxram can be accessed */ -+#define HIFN_MIPSRST_LED2 0x00000400 /* external LED2 */ -+#define HIFN_MIPSRST_LED1 0x00000200 /* external LED1 */ -+#define HIFN_MIPSRST_LED0 0x00000100 /* external LED0 */ -+#define HIFN_MIPSRST_MIPSDIS 0x00000004 /* disable MIPS */ -+#define HIFN_MIPSRST_MIPSRST 0x00000002 /* warm reset MIPS */ -+#define HIFN_MIPSRST_MIPSCOLD 0x00000001 /* cold reset MIPS */ -+ -+/* Public key reset register (HIFN_1_PUB_RESET) */ -+#define HIFN_PUBRST_RESET 0x00000001 /* reset public/rng unit */ -+ -+/* Public operation register (HIFN_1_PUB_OP) */ -+#define HIFN_PUBOP_AOFFSET 0x0000003e /* A offset */ -+#define HIFN_PUBOP_BOFFSET 0x00000fc0 /* B offset */ -+#define HIFN_PUBOP_MOFFSET 0x0003f000 /* M offset */ -+#define HIFN_PUBOP_OP_MASK 0x003c0000 /* Opcode: */ -+#define HIFN_PUBOP_OP_NOP 0x00000000 /* NOP */ -+#define HIFN_PUBOP_OP_ADD 0x00040000 /* ADD */ -+#define HIFN_PUBOP_OP_ADDC 0x00080000 /* ADD w/carry */ -+#define HIFN_PUBOP_OP_SUB 0x000c0000 /* SUB */ -+#define HIFN_PUBOP_OP_SUBC 0x00100000 /* SUB w/carry */ -+#define HIFN_PUBOP_OP_MODADD 0x00140000 /* Modular ADD */ -+#define HIFN_PUBOP_OP_MODSUB 0x00180000 /* Modular SUB */ -+#define HIFN_PUBOP_OP_INCA 0x001c0000 /* INC A */ -+#define HIFN_PUBOP_OP_DECA 0x00200000 /* DEC A */ -+#define HIFN_PUBOP_OP_MULT 0x00240000 /* MULT */ -+#define HIFN_PUBOP_OP_MODMULT 0x00280000 /* Modular MULT */ -+#define HIFN_PUBOP_OP_MODRED 0x002c0000 /* Modular Red */ -+#define HIFN_PUBOP_OP_MODEXP 0x00300000 /* Modular Exp */ -+ -+/* Public operand length register (HIFN_1_PUB_OPLEN) */ -+#define HIFN_PUBOPLEN_MODLEN 0x0000007f -+#define HIFN_PUBOPLEN_EXPLEN 0x0003ff80 -+#define HIFN_PUBOPLEN_REDLEN 0x003c0000 -+ -+/* Public status register (HIFN_1_PUB_STATUS) */ -+#define HIFN_PUBSTS_DONE 0x00000001 /* operation done */ -+#define HIFN_PUBSTS_CARRY 0x00000002 /* carry */ -+#define HIFN_PUBSTS_FIFO_EMPTY 0x00000100 /* fifo empty */ -+#define HIFN_PUBSTS_FIFO_FULL 0x00000200 /* fifo full */ -+#define HIFN_PUBSTS_FIFO_OVFL 0x00000400 /* fifo overflow */ -+#define HIFN_PUBSTS_FIFO_WRITE 0x000f0000 /* fifo write */ -+#define HIFN_PUBSTS_FIFO_READ 0x0f000000 /* fifo read */ -+ -+/* Public interrupt enable register (HIFN_1_PUB_IEN) */ -+#define HIFN_PUBIEN_DONE 0x00000001 /* operation done interrupt */ -+ -+/* Random number generator config register (HIFN_1_RNG_CONFIG) */ -+#define HIFN_RNGCFG_ENA 0x00000001 /* enable rng */ -+ -+/* -+ * Register offsets in register set 1 -+ */ -+ -+#define HIFN_UNLOCK_SECRET1 0xf4 -+#define HIFN_UNLOCK_SECRET2 0xfc -+ -+/* -+ * PLL config register -+ * -+ * This register is present only on 7954/7955/7956 parts. It must be -+ * programmed according to the bus interface method used by the h/w. -+ * Note that the parts require a stable clock. Since the PCI clock -+ * may vary the reference clock must usually be used. To avoid -+ * overclocking the core logic, setup must be done carefully, refer -+ * to the driver for details. The exact multiplier required varies -+ * by part and system configuration; refer to the Hifn documentation. -+ */ -+#define HIFN_PLL_REF_SEL 0x00000001 /* REF/HBI clk selection */ -+#define HIFN_PLL_BP 0x00000002 /* bypass (used during setup) */ -+/* bit 2 reserved */ -+#define HIFN_PLL_PK_CLK_SEL 0x00000008 /* public key clk select */ -+#define HIFN_PLL_PE_CLK_SEL 0x00000010 /* packet engine clk select */ -+/* bits 5-9 reserved */ -+#define HIFN_PLL_MBSET 0x00000400 /* must be set to 1 */ -+#define HIFN_PLL_ND 0x00003800 /* Fpll_ref multiplier select */ -+#define HIFN_PLL_ND_SHIFT 11 -+#define HIFN_PLL_ND_2 0x00000000 /* 2x */ -+#define HIFN_PLL_ND_4 0x00000800 /* 4x */ -+#define HIFN_PLL_ND_6 0x00001000 /* 6x */ -+#define HIFN_PLL_ND_8 0x00001800 /* 8x */ -+#define HIFN_PLL_ND_10 0x00002000 /* 10x */ -+#define HIFN_PLL_ND_12 0x00002800 /* 12x */ -+/* bits 14-15 reserved */ -+#define HIFN_PLL_IS 0x00010000 /* charge pump current select */ -+/* bits 17-31 reserved */ -+ -+/* -+ * Board configuration specifies only these bits. -+ */ -+#define HIFN_PLL_CONFIG (HIFN_PLL_IS|HIFN_PLL_ND|HIFN_PLL_REF_SEL) -+ -+/* -+ * Public Key Engine Mode Register -+ */ -+#define HIFN_PKMODE_HOSTINVERT (1 << 0) /* HOST INVERT */ -+#define HIFN_PKMODE_ENHANCED (1 << 1) /* Enable enhanced mode */ -+ -+ -+/********************************************************************* -+ * Structs for board commands -+ * -+ *********************************************************************/ -+ -+/* -+ * Structure to help build up the command data structure. -+ */ -+typedef struct hifn_base_command { -+ volatile u_int16_t masks; -+ volatile u_int16_t session_num; -+ volatile u_int16_t total_source_count; -+ volatile u_int16_t total_dest_count; -+} hifn_base_command_t; -+ -+#define HIFN_BASE_CMD_MAC 0x0400 -+#define HIFN_BASE_CMD_CRYPT 0x0800 -+#define HIFN_BASE_CMD_DECODE 0x2000 -+#define HIFN_BASE_CMD_SRCLEN_M 0xc000 -+#define HIFN_BASE_CMD_SRCLEN_S 14 -+#define HIFN_BASE_CMD_DSTLEN_M 0x3000 -+#define HIFN_BASE_CMD_DSTLEN_S 12 -+#define HIFN_BASE_CMD_LENMASK_HI 0x30000 -+#define HIFN_BASE_CMD_LENMASK_LO 0x0ffff -+ -+/* -+ * Structure to help build up the command data structure. -+ */ -+typedef struct hifn_crypt_command { -+ volatile u_int16_t masks; -+ volatile u_int16_t header_skip; -+ volatile u_int16_t source_count; -+ volatile u_int16_t reserved; -+} hifn_crypt_command_t; -+ -+#define HIFN_CRYPT_CMD_ALG_MASK 0x0003 /* algorithm: */ -+#define HIFN_CRYPT_CMD_ALG_DES 0x0000 /* DES */ -+#define HIFN_CRYPT_CMD_ALG_3DES 0x0001 /* 3DES */ -+#define HIFN_CRYPT_CMD_ALG_RC4 0x0002 /* RC4 */ -+#define HIFN_CRYPT_CMD_ALG_AES 0x0003 /* AES */ -+#define HIFN_CRYPT_CMD_MODE_MASK 0x0018 /* Encrypt mode: */ -+#define HIFN_CRYPT_CMD_MODE_ECB 0x0000 /* ECB */ -+#define HIFN_CRYPT_CMD_MODE_CBC 0x0008 /* CBC */ -+#define HIFN_CRYPT_CMD_MODE_CFB 0x0010 /* CFB */ -+#define HIFN_CRYPT_CMD_MODE_OFB 0x0018 /* OFB */ -+#define HIFN_CRYPT_CMD_CLR_CTX 0x0040 /* clear context */ -+#define HIFN_CRYPT_CMD_NEW_KEY 0x0800 /* expect new key */ -+#define HIFN_CRYPT_CMD_NEW_IV 0x1000 /* expect new iv */ -+ -+#define HIFN_CRYPT_CMD_SRCLEN_M 0xc000 -+#define HIFN_CRYPT_CMD_SRCLEN_S 14 -+ -+#define HIFN_CRYPT_CMD_KSZ_MASK 0x0600 /* AES key size: */ -+#define HIFN_CRYPT_CMD_KSZ_128 0x0000 /* 128 bit */ -+#define HIFN_CRYPT_CMD_KSZ_192 0x0200 /* 192 bit */ -+#define HIFN_CRYPT_CMD_KSZ_256 0x0400 /* 256 bit */ -+ -+/* -+ * Structure to help build up the command data structure. -+ */ -+typedef struct hifn_mac_command { -+ volatile u_int16_t masks; -+ volatile u_int16_t header_skip; -+ volatile u_int16_t source_count; -+ volatile u_int16_t reserved; -+} hifn_mac_command_t; -+ -+#define HIFN_MAC_CMD_ALG_MASK 0x0001 -+#define HIFN_MAC_CMD_ALG_SHA1 0x0000 -+#define HIFN_MAC_CMD_ALG_MD5 0x0001 -+#define HIFN_MAC_CMD_MODE_MASK 0x000c -+#define HIFN_MAC_CMD_MODE_HMAC 0x0000 -+#define HIFN_MAC_CMD_MODE_SSL_MAC 0x0004 -+#define HIFN_MAC_CMD_MODE_HASH 0x0008 -+#define HIFN_MAC_CMD_MODE_FULL 0x0004 -+#define HIFN_MAC_CMD_TRUNC 0x0010 -+#define HIFN_MAC_CMD_RESULT 0x0020 -+#define HIFN_MAC_CMD_APPEND 0x0040 -+#define HIFN_MAC_CMD_SRCLEN_M 0xc000 -+#define HIFN_MAC_CMD_SRCLEN_S 14 -+ -+/* -+ * MAC POS IPsec initiates authentication after encryption on encodes -+ * and before decryption on decodes. -+ */ -+#define HIFN_MAC_CMD_POS_IPSEC 0x0200 -+#define HIFN_MAC_CMD_NEW_KEY 0x0800 -+ -+/* -+ * The poll frequency and poll scalar defines are unshifted values used -+ * to set fields in the DMA Configuration Register. -+ */ -+#ifndef HIFN_POLL_FREQUENCY -+#define HIFN_POLL_FREQUENCY 0x1 -+#endif -+ -+#ifndef HIFN_POLL_SCALAR -+#define HIFN_POLL_SCALAR 0x0 -+#endif -+ -+#define HIFN_MAX_SEGLEN 0xffff /* maximum dma segment len */ -+#define HIFN_MAX_DMALEN 0x3ffff /* maximum dma length */ -+#endif /* __HIFN_H__ */ -diff -Nur linux-3.0.4.orig/crypto/ocf/hifn/hifn7751var.h linux-3.0.4/crypto/ocf/hifn/hifn7751var.h ---- linux-3.0.4.orig/crypto/ocf/hifn/hifn7751var.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/hifn/hifn7751var.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,368 @@ -+/* $FreeBSD: src/sys/dev/hifn/hifn7751var.h,v 1.9 2007/03/21 03:42:49 sam Exp $ */ -+/* $OpenBSD: hifn7751var.h,v 1.42 2002/04/08 17:49:42 jason Exp $ */ -+ -+/*- -+ * Invertex AEON / Hifn 7751 driver -+ * Copyright (c) 1999 Invertex Inc. All rights reserved. -+ * Copyright (c) 1999 Theo de Raadt -+ * Copyright (c) 2000-2001 Network Security Technologies, Inc. -+ * http://www.netsec.net -+ * -+ * Please send any comments, feedback, bug-fixes, or feature requests to -+ * software@invertex.com. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored in part by the Defense Advanced Research Projects -+ * Agency (DARPA) and Air Force Research Laboratory, Air Force -+ * Materiel Command, USAF, under agreement number F30602-01-2-0537. -+ * -+ */ -+ -+#ifndef __HIFN7751VAR_H__ -+#define __HIFN7751VAR_H__ -+ -+#ifdef __KERNEL__ -+ -+/* -+ * Some configurable values for the driver. By default command+result -+ * descriptor rings are the same size. The src+dst descriptor rings -+ * are sized at 3.5x the number of potential commands. Slower parts -+ * (e.g. 7951) tend to run out of src descriptors; faster parts (7811) -+ * src+cmd/result descriptors. It's not clear that increasing the size -+ * of the descriptor rings helps performance significantly as other -+ * factors tend to come into play (e.g. copying misaligned packets). -+ */ -+#define HIFN_D_CMD_RSIZE 24 /* command descriptors */ -+#define HIFN_D_SRC_RSIZE ((HIFN_D_CMD_RSIZE * 7) / 2) /* source descriptors */ -+#define HIFN_D_RES_RSIZE HIFN_D_CMD_RSIZE /* result descriptors */ -+#define HIFN_D_DST_RSIZE HIFN_D_SRC_RSIZE /* destination descriptors */ -+ -+/* -+ * Length values for cryptography -+ */ -+#define HIFN_DES_KEY_LENGTH 8 -+#define HIFN_3DES_KEY_LENGTH 24 -+#define HIFN_MAX_CRYPT_KEY_LENGTH HIFN_3DES_KEY_LENGTH -+#define HIFN_IV_LENGTH 8 -+#define HIFN_AES_IV_LENGTH 16 -+#define HIFN_MAX_IV_LENGTH HIFN_AES_IV_LENGTH -+ -+/* -+ * Length values for authentication -+ */ -+#define HIFN_MAC_KEY_LENGTH 64 -+#define HIFN_MD5_LENGTH 16 -+#define HIFN_SHA1_LENGTH 20 -+#define HIFN_MAC_TRUNC_LENGTH 12 -+ -+#define MAX_SCATTER 64 -+ -+/* -+ * Data structure to hold all 4 rings and any other ring related data. -+ */ -+struct hifn_dma { -+ /* -+ * Descriptor rings. We add +1 to the size to accomidate the -+ * jump descriptor. -+ */ -+ struct hifn_desc cmdr[HIFN_D_CMD_RSIZE+1]; -+ struct hifn_desc srcr[HIFN_D_SRC_RSIZE+1]; -+ struct hifn_desc dstr[HIFN_D_DST_RSIZE+1]; -+ struct hifn_desc resr[HIFN_D_RES_RSIZE+1]; -+ -+ struct hifn_command *hifn_commands[HIFN_D_RES_RSIZE]; -+ -+ u_char command_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_COMMAND]; -+ u_char result_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_RESULT]; -+ u_int32_t slop[HIFN_D_CMD_RSIZE]; -+ -+ u_int64_t test_src, test_dst; -+ -+ /* -+ * Our current positions for insertion and removal from the desriptor -+ * rings. -+ */ -+ int cmdi, srci, dsti, resi; -+ volatile int cmdu, srcu, dstu, resu; -+ int cmdk, srck, dstk, resk; -+}; -+ -+struct hifn_session { -+ int hs_used; -+ int hs_mlen; -+}; -+ -+#define HIFN_RING_SYNC(sc, r, i, f) \ -+ /* DAVIDM bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, (f)) */ -+ -+#define HIFN_CMDR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), cmdr, (i), (f)) -+#define HIFN_RESR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), resr, (i), (f)) -+#define HIFN_SRCR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), srcr, (i), (f)) -+#define HIFN_DSTR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), dstr, (i), (f)) -+ -+#define HIFN_CMD_SYNC(sc, i, f) \ -+ /* DAVIDM bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, (f)) */ -+ -+#define HIFN_RES_SYNC(sc, i, f) \ -+ /* DAVIDM bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, (f)) */ -+ -+typedef int bus_size_t; -+ -+/* -+ * Holds data specific to a single HIFN board. -+ */ -+struct hifn_softc { -+ softc_device_decl sc_dev; -+ -+ struct pci_dev *sc_pcidev; /* PCI device pointer */ -+ spinlock_t sc_mtx; /* per-instance lock */ -+ -+ int sc_num; /* for multiple devs */ -+ -+ ocf_iomem_t sc_bar0; -+ bus_size_t sc_bar0_lastreg;/* bar0 last reg written */ -+ ocf_iomem_t sc_bar1; -+ bus_size_t sc_bar1_lastreg;/* bar1 last reg written */ -+ -+ int sc_irq; -+ -+ u_int32_t sc_dmaier; -+ u_int32_t sc_drammodel; /* 1=dram, 0=sram */ -+ u_int32_t sc_pllconfig; /* 7954/7955/7956 PLL config */ -+ -+ struct hifn_dma *sc_dma; -+ dma_addr_t sc_dma_physaddr;/* physical address of sc_dma */ -+ -+ int sc_dmansegs; -+ int32_t sc_cid; -+ int sc_maxses; -+ int sc_nsessions; -+ struct hifn_session *sc_sessions; -+ int sc_ramsize; -+ int sc_flags; -+#define HIFN_HAS_RNG 0x1 /* includes random number generator */ -+#define HIFN_HAS_PUBLIC 0x2 /* includes public key support */ -+#define HIFN_HAS_AES 0x4 /* includes AES support */ -+#define HIFN_IS_7811 0x8 /* Hifn 7811 part */ -+#define HIFN_IS_7956 0x10 /* Hifn 7956/7955 don't have SDRAM */ -+ -+ struct timer_list sc_tickto; /* for managing DMA */ -+ -+ int sc_rngfirst; -+ int sc_rnghz; /* RNG polling frequency */ -+ -+ int sc_c_busy; /* command ring busy */ -+ int sc_s_busy; /* source data ring busy */ -+ int sc_d_busy; /* destination data ring busy */ -+ int sc_r_busy; /* result ring busy */ -+ int sc_active; /* for initial countdown */ -+ int sc_needwakeup; /* ops q'd wating on resources */ -+ int sc_curbatch; /* # ops submitted w/o int */ -+ int sc_suspended; -+#ifdef HIFN_VULCANDEV -+ struct cdev *sc_pkdev; -+#endif -+}; -+ -+#define HIFN_LOCK(_sc) spin_lock_irqsave(&(_sc)->sc_mtx, l_flags) -+#define HIFN_UNLOCK(_sc) spin_unlock_irqrestore(&(_sc)->sc_mtx, l_flags) -+ -+/* -+ * hifn_command_t -+ * -+ * This is the control structure used to pass commands to hifn_encrypt(). -+ * -+ * flags -+ * ----- -+ * Flags is the bitwise "or" values for command configuration. A single -+ * encrypt direction needs to be set: -+ * -+ * HIFN_ENCODE or HIFN_DECODE -+ * -+ * To use cryptography, a single crypto algorithm must be included: -+ * -+ * HIFN_CRYPT_3DES or HIFN_CRYPT_DES -+ * -+ * To use authentication is used, a single MAC algorithm must be included: -+ * -+ * HIFN_MAC_MD5 or HIFN_MAC_SHA1 -+ * -+ * By default MD5 uses a 16 byte hash and SHA-1 uses a 20 byte hash. -+ * If the value below is set, hash values are truncated or assumed -+ * truncated to 12 bytes: -+ * -+ * HIFN_MAC_TRUNC -+ * -+ * Keys for encryption and authentication can be sent as part of a command, -+ * or the last key value used with a particular session can be retrieved -+ * and used again if either of these flags are not specified. -+ * -+ * HIFN_CRYPT_NEW_KEY, HIFN_MAC_NEW_KEY -+ * -+ * session_num -+ * ----------- -+ * A number between 0 and 2048 (for DRAM models) or a number between -+ * 0 and 768 (for SRAM models). Those who don't want to use session -+ * numbers should leave value at zero and send a new crypt key and/or -+ * new MAC key on every command. If you use session numbers and -+ * don't send a key with a command, the last key sent for that same -+ * session number will be used. -+ * -+ * Warning: Using session numbers and multiboard at the same time -+ * is currently broken. -+ * -+ * mbuf -+ * ---- -+ * Either fill in the mbuf pointer and npa=0 or -+ * fill packp[] and packl[] and set npa to > 0 -+ * -+ * mac_header_skip -+ * --------------- -+ * The number of bytes of the source_buf that are skipped over before -+ * authentication begins. This must be a number between 0 and 2^16-1 -+ * and can be used by IPsec implementers to skip over IP headers. -+ * *** Value ignored if authentication not used *** -+ * -+ * crypt_header_skip -+ * ----------------- -+ * The number of bytes of the source_buf that are skipped over before -+ * the cryptographic operation begins. This must be a number between 0 -+ * and 2^16-1. For IPsec, this number will always be 8 bytes larger -+ * than the auth_header_skip (to skip over the ESP header). -+ * *** Value ignored if cryptography not used *** -+ * -+ */ -+struct hifn_operand { -+ union { -+ struct sk_buff *skb; -+ struct uio *io; -+ unsigned char *buf; -+ } u; -+ void *map; -+ bus_size_t mapsize; -+ int nsegs; -+ struct { -+ dma_addr_t ds_addr; -+ int ds_len; -+ } segs[MAX_SCATTER]; -+}; -+ -+struct hifn_command { -+ u_int16_t session_num; -+ u_int16_t base_masks, cry_masks, mac_masks; -+ u_int8_t iv[HIFN_MAX_IV_LENGTH], *ck, mac[HIFN_MAC_KEY_LENGTH]; -+ int cklen; -+ int sloplen, slopidx; -+ -+ struct hifn_operand src; -+ struct hifn_operand dst; -+ -+ struct hifn_softc *softc; -+ struct cryptop *crp; -+ struct cryptodesc *enccrd, *maccrd; -+}; -+ -+#define src_skb src.u.skb -+#define src_io src.u.io -+#define src_map src.map -+#define src_mapsize src.mapsize -+#define src_segs src.segs -+#define src_nsegs src.nsegs -+#define src_buf src.u.buf -+ -+#define dst_skb dst.u.skb -+#define dst_io dst.u.io -+#define dst_map dst.map -+#define dst_mapsize dst.mapsize -+#define dst_segs dst.segs -+#define dst_nsegs dst.nsegs -+#define dst_buf dst.u.buf -+ -+/* -+ * Return values for hifn_crypto() -+ */ -+#define HIFN_CRYPTO_SUCCESS 0 -+#define HIFN_CRYPTO_BAD_INPUT (-1) -+#define HIFN_CRYPTO_RINGS_FULL (-2) -+ -+/************************************************************************** -+ * -+ * Function: hifn_crypto -+ * -+ * Purpose: Called by external drivers to begin an encryption on the -+ * HIFN board. -+ * -+ * Blocking/Non-blocking Issues -+ * ============================ -+ * The driver cannot block in hifn_crypto (no calls to tsleep) currently. -+ * hifn_crypto() returns HIFN_CRYPTO_RINGS_FULL if there is not enough -+ * room in any of the rings for the request to proceed. -+ * -+ * Return Values -+ * ============= -+ * 0 for success, negative values on error -+ * -+ * Defines for negative error codes are: -+ * -+ * HIFN_CRYPTO_BAD_INPUT : The passed in command had invalid settings. -+ * HIFN_CRYPTO_RINGS_FULL : All DMA rings were full and non-blocking -+ * behaviour was requested. -+ * -+ *************************************************************************/ -+ -+/* -+ * Convert back and forth from 'sid' to 'card' and 'session' -+ */ -+#define HIFN_CARD(sid) (((sid) & 0xf0000000) >> 28) -+#define HIFN_SESSION(sid) ((sid) & 0x000007ff) -+#define HIFN_SID(crd,ses) (((crd) << 28) | ((ses) & 0x7ff)) -+ -+#endif /* _KERNEL */ -+ -+struct hifn_stats { -+ u_int64_t hst_ibytes; -+ u_int64_t hst_obytes; -+ u_int32_t hst_ipackets; -+ u_int32_t hst_opackets; -+ u_int32_t hst_invalid; -+ u_int32_t hst_nomem; /* malloc or one of hst_nomem_* */ -+ u_int32_t hst_abort; -+ u_int32_t hst_noirq; /* IRQ for no reason */ -+ u_int32_t hst_totbatch; /* ops submitted w/o interrupt */ -+ u_int32_t hst_maxbatch; /* max ops submitted together */ -+ u_int32_t hst_unaligned; /* unaligned src caused copy */ -+ /* -+ * The following divides hst_nomem into more specific buckets. -+ */ -+ u_int32_t hst_nomem_map; /* bus_dmamap_create failed */ -+ u_int32_t hst_nomem_load; /* bus_dmamap_load_* failed */ -+ u_int32_t hst_nomem_mbuf; /* MGET* failed */ -+ u_int32_t hst_nomem_mcl; /* MCLGET* failed */ -+ u_int32_t hst_nomem_cr; /* out of command/result descriptor */ -+ u_int32_t hst_nomem_sd; /* out of src/dst descriptors */ -+}; -+ -+#endif /* __HIFN7751VAR_H__ */ -diff -Nur linux-3.0.4.orig/crypto/ocf/hifn/hifnHIPP.c linux-3.0.4/crypto/ocf/hifn/hifnHIPP.c ---- linux-3.0.4.orig/crypto/ocf/hifn/hifnHIPP.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/hifn/hifnHIPP.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,420 @@ -+/*- -+ * Driver for Hifn HIPP-I/II chipset -+ * Copyright (c) 2006 Michael Richardson -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored by Hifn Inc. -+ * -+ */ -+ -+/* -+ * Driver for various Hifn encryption processors. -+ */ -+#include -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "hifnHIPPreg.h" -+#include "hifnHIPPvar.h" -+ -+#if 1 -+#define DPRINTF(a...) if (hipp_debug) { \ -+ printk("%s: ", sc ? \ -+ device_get_nameunit(sc->sc_dev) : "hifn"); \ -+ printk(a); \ -+ } else -+#else -+#define DPRINTF(a...) -+#endif -+ -+typedef int bus_size_t; -+ -+static inline int -+pci_get_revid(struct pci_dev *dev) -+{ -+ u8 rid = 0; -+ pci_read_config_byte(dev, PCI_REVISION_ID, &rid); -+ return rid; -+} -+ -+#define debug hipp_debug -+int hipp_debug = 0; -+module_param(hipp_debug, int, 0644); -+MODULE_PARM_DESC(hipp_debug, "Enable debug"); -+ -+int hipp_maxbatch = 1; -+module_param(hipp_maxbatch, int, 0644); -+MODULE_PARM_DESC(hipp_maxbatch, "max ops to batch w/o interrupt"); -+ -+static int hipp_probe(struct pci_dev *dev, const struct pci_device_id *ent); -+static void hipp_remove(struct pci_dev *dev); -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) -+static irqreturn_t hipp_intr(int irq, void *arg); -+#else -+static irqreturn_t hipp_intr(int irq, void *arg, struct pt_regs *regs); -+#endif -+ -+static int hipp_num_chips = 0; -+static struct hipp_softc *hipp_chip_idx[HIPP_MAX_CHIPS]; -+ -+static int hipp_newsession(device_t, u_int32_t *, struct cryptoini *); -+static int hipp_freesession(device_t, u_int64_t); -+static int hipp_process(device_t, struct cryptop *, int); -+ -+static device_method_t hipp_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, hipp_newsession), -+ DEVMETHOD(cryptodev_freesession,hipp_freesession), -+ DEVMETHOD(cryptodev_process, hipp_process), -+}; -+ -+static __inline u_int32_t -+READ_REG(struct hipp_softc *sc, unsigned int barno, bus_size_t reg) -+{ -+ u_int32_t v = readl(sc->sc_bar[barno] + reg); -+ //sc->sc_bar0_lastreg = (bus_size_t) -1; -+ return (v); -+} -+static __inline void -+WRITE_REG(struct hipp_softc *sc, unsigned int barno, bus_size_t reg, u_int32_t val) -+{ -+ writel(val, sc->sc_bar[barno] + reg); -+} -+ -+#define READ_REG_0(sc, reg) READ_REG(sc, 0, reg) -+#define WRITE_REG_0(sc, reg, val) WRITE_REG(sc,0, reg, val) -+#define READ_REG_1(sc, reg) READ_REG(sc, 1, reg) -+#define WRITE_REG_1(sc, reg, val) WRITE_REG(sc,1, reg, val) -+ -+static int -+hipp_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) -+{ -+ return EINVAL; -+} -+ -+static int -+hipp_freesession(device_t dev, u_int64_t tid) -+{ -+ return EINVAL; -+} -+ -+static int -+hipp_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ return EINVAL; -+} -+ -+static const char* -+hipp_partname(struct hipp_softc *sc, char buf[128], size_t blen) -+{ -+ char *n = NULL; -+ -+ switch (pci_get_vendor(sc->sc_pcidev)) { -+ case PCI_VENDOR_HIFN: -+ switch (pci_get_device(sc->sc_pcidev)) { -+ case PCI_PRODUCT_HIFN_7855: n = "Hifn 7855"; -+ case PCI_PRODUCT_HIFN_8155: n = "Hifn 8155"; -+ case PCI_PRODUCT_HIFN_6500: n = "Hifn 6500"; -+ } -+ } -+ -+ if(n==NULL) { -+ snprintf(buf, blen, "VID=%02x,PID=%02x", -+ pci_get_vendor(sc->sc_pcidev), -+ pci_get_device(sc->sc_pcidev)); -+ } else { -+ buf[0]='\0'; -+ strncat(buf, n, blen); -+ } -+ return buf; -+} -+ -+struct hipp_fs_entry { -+ struct attribute attr; -+ /* other stuff */ -+}; -+ -+ -+static ssize_t -+cryptoid_show(struct device *dev, -+ struct device_attribute *attr, -+ char *buf) -+{ -+ struct hipp_softc *sc; -+ -+ sc = pci_get_drvdata(to_pci_dev (dev)); -+ return sprintf (buf, "%d\n", sc->sc_cid); -+} -+ -+struct device_attribute hipp_dev_cryptoid = __ATTR_RO(cryptoid); -+ -+/* -+ * Attach an interface that successfully probed. -+ */ -+static int -+hipp_probe(struct pci_dev *dev, const struct pci_device_id *ent) -+{ -+ struct hipp_softc *sc = NULL; -+ int i; -+ //char rbase; -+ //u_int16_t ena; -+ int rev; -+ //int rseg; -+ int rc; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (pci_enable_device(dev) < 0) -+ return(-ENODEV); -+ -+ if (pci_set_mwi(dev)) -+ return(-ENODEV); -+ -+ if (!dev->irq) { -+ printk("hifn: found device with no IRQ assigned. check BIOS settings!"); -+ pci_disable_device(dev); -+ return(-ENODEV); -+ } -+ -+ sc = (struct hipp_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); -+ if (!sc) -+ return(-ENOMEM); -+ memset(sc, 0, sizeof(*sc)); -+ -+ softc_device_init(sc, "hifn-hipp", hipp_num_chips, hipp_methods); -+ -+ sc->sc_pcidev = dev; -+ sc->sc_irq = -1; -+ sc->sc_cid = -1; -+ sc->sc_num = hipp_num_chips++; -+ -+ if (sc->sc_num < HIPP_MAX_CHIPS) -+ hipp_chip_idx[sc->sc_num] = sc; -+ -+ pci_set_drvdata(sc->sc_pcidev, sc); -+ -+ spin_lock_init(&sc->sc_mtx); -+ -+ /* -+ * Setup PCI resources. -+ * The READ_REG_0, WRITE_REG_0, READ_REG_1, -+ * and WRITE_REG_1 macros throughout the driver are used -+ * to permit better debugging. -+ */ -+ for(i=0; i<4; i++) { -+ unsigned long mem_start, mem_len; -+ mem_start = pci_resource_start(sc->sc_pcidev, i); -+ mem_len = pci_resource_len(sc->sc_pcidev, i); -+ sc->sc_barphy[i] = (caddr_t)mem_start; -+ sc->sc_bar[i] = (ocf_iomem_t) ioremap(mem_start, mem_len); -+ if (!sc->sc_bar[i]) { -+ device_printf(sc->sc_dev, "cannot map bar%d register space\n", i); -+ goto fail; -+ } -+ } -+ -+ //hipp_reset_board(sc, 0); -+ pci_set_master(sc->sc_pcidev); -+ -+ /* -+ * Arrange the interrupt line. -+ */ -+ rc = request_irq(dev->irq, hipp_intr, IRQF_SHARED, "hifn", sc); -+ if (rc) { -+ device_printf(sc->sc_dev, "could not map interrupt: %d\n", rc); -+ goto fail; -+ } -+ sc->sc_irq = dev->irq; -+ -+ rev = READ_REG_1(sc, HIPP_1_REVID) & 0xffff; -+ -+ { -+ char b[32]; -+ device_printf(sc->sc_dev, "%s, rev %u", -+ hipp_partname(sc, b, sizeof(b)), rev); -+ } -+ -+#if 0 -+ if (sc->sc_flags & HIFN_IS_7956) -+ printf(", pll=0x%x<%s clk, %ux mult>", -+ sc->sc_pllconfig, -+ sc->sc_pllconfig & HIFN_PLL_REF_SEL ? "ext" : "pci", -+ 2 + 2*((sc->sc_pllconfig & HIFN_PLL_ND) >> 11)); -+#endif -+ printf("\n"); -+ -+ sc->sc_cid = crypto_get_driverid(softc_get_device(sc),CRYPTOCAP_F_HARDWARE); -+ if (sc->sc_cid < 0) { -+ device_printf(sc->sc_dev, "could not get crypto driver id\n"); -+ goto fail; -+ } -+ -+#if 0 /* cannot work with a non-GPL module */ -+ /* make a sysfs entry to let the world know what entry we got */ -+ sysfs_create_file(&sc->sc_pcidev->dev.kobj, &hipp_dev_cryptoid.attr); -+#endif -+ -+#if 0 -+ init_timer(&sc->sc_tickto); -+ sc->sc_tickto.function = hifn_tick; -+ sc->sc_tickto.data = (unsigned long) sc->sc_num; -+ mod_timer(&sc->sc_tickto, jiffies + HZ); -+#endif -+ -+#if 0 /* no code here yet ?? */ -+ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); -+#endif -+ -+ return (0); -+ -+fail: -+ if (sc->sc_cid >= 0) -+ crypto_unregister_all(sc->sc_cid); -+ if (sc->sc_irq != -1) -+ free_irq(sc->sc_irq, sc); -+ -+#if 0 -+ if (sc->sc_dma) { -+ /* Turn off DMA polling */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | -+ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); -+ -+ pci_free_consistent(sc->sc_pcidev, -+ sizeof(*sc->sc_dma), -+ sc->sc_dma, sc->sc_dma_physaddr); -+ } -+#endif -+ kfree(sc); -+ return (-ENXIO); -+} -+ -+/* -+ * Detach an interface that successfully probed. -+ */ -+static void -+hipp_remove(struct pci_dev *dev) -+{ -+ struct hipp_softc *sc = pci_get_drvdata(dev); -+ unsigned long l_flags; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ /* disable interrupts */ -+ HIPP_LOCK(sc); -+ -+#if 0 -+ WRITE_REG_1(sc, HIFN_1_DMA_IER, 0); -+ HIFN_UNLOCK(sc); -+ -+ /*XXX other resources */ -+ del_timer_sync(&sc->sc_tickto); -+ -+ /* Turn off DMA polling */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | -+ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); -+#endif -+ -+ crypto_unregister_all(sc->sc_cid); -+ -+ free_irq(sc->sc_irq, sc); -+ -+#if 0 -+ pci_free_consistent(sc->sc_pcidev, sizeof(*sc->sc_dma), -+ sc->sc_dma, sc->sc_dma_physaddr); -+#endif -+} -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) -+static irqreturn_t hipp_intr(int irq, void *arg) -+#else -+static irqreturn_t hipp_intr(int irq, void *arg, struct pt_regs *regs) -+#endif -+{ -+ struct hipp_softc *sc = arg; -+ -+ sc = sc; /* shut up compiler */ -+ -+ return IRQ_HANDLED; -+} -+ -+static struct pci_device_id hipp_pci_tbl[] = { -+ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7855, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_8155, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+}; -+MODULE_DEVICE_TABLE(pci, hipp_pci_tbl); -+ -+static struct pci_driver hipp_driver = { -+ .name = "hipp", -+ .id_table = hipp_pci_tbl, -+ .probe = hipp_probe, -+ .remove = hipp_remove, -+ /* add PM stuff here one day */ -+}; -+ -+static int __init hipp_init (void) -+{ -+ struct hipp_softc *sc = NULL; -+ int rc; -+ -+ DPRINTF("%s(%p)\n", __FUNCTION__, hipp_init); -+ -+ rc = pci_register_driver(&hipp_driver); -+ pci_register_driver_compat(&hipp_driver, rc); -+ -+ return rc; -+} -+ -+static void __exit hipp_exit (void) -+{ -+ pci_unregister_driver(&hipp_driver); -+} -+ -+module_init(hipp_init); -+module_exit(hipp_exit); -+ -+MODULE_LICENSE("BSD"); -+MODULE_AUTHOR("Michael Richardson "); -+MODULE_DESCRIPTION("OCF driver for hifn HIPP-I/II PCI crypto devices"); -diff -Nur linux-3.0.4.orig/crypto/ocf/hifn/hifnHIPPreg.h linux-3.0.4/crypto/ocf/hifn/hifnHIPPreg.h ---- linux-3.0.4.orig/crypto/ocf/hifn/hifnHIPPreg.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/hifn/hifnHIPPreg.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,46 @@ -+/*- -+ * Hifn HIPP-I/HIPP-II (7855/8155) driver. -+ * Copyright (c) 2006 Michael Richardson -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored by Hifn inc. -+ * -+ */ -+ -+#ifndef __HIFNHIPP_H__ -+#define __HIFNHIPP_H__ -+ -+/* -+ * PCI vendor and device identifiers -+ */ -+#define PCI_VENDOR_HIFN 0x13a3 /* Hifn */ -+#define PCI_PRODUCT_HIFN_6500 0x0006 /* 6500 */ -+#define PCI_PRODUCT_HIFN_7855 0x001f /* 7855 */ -+#define PCI_PRODUCT_HIFN_8155 0x999 /* XXX 8155 */ -+ -+#define HIPP_1_REVID 0x01 /* BOGUS */ -+ -+#endif /* __HIPP_H__ */ -diff -Nur linux-3.0.4.orig/crypto/ocf/hifn/hifnHIPPvar.h linux-3.0.4/crypto/ocf/hifn/hifnHIPPvar.h ---- linux-3.0.4.orig/crypto/ocf/hifn/hifnHIPPvar.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/hifn/hifnHIPPvar.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,93 @@ -+/* -+ * Hifn HIPP-I/HIPP-II (7855/8155) driver. -+ * Copyright (c) 2006 Michael Richardson * -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored by Hifn inc. -+ * -+ */ -+ -+#ifndef __HIFNHIPPVAR_H__ -+#define __HIFNHIPPVAR_H__ -+ -+#define HIPP_MAX_CHIPS 8 -+ -+/* -+ * Holds data specific to a single Hifn HIPP-I board. -+ */ -+struct hipp_softc { -+ softc_device_decl sc_dev; -+ -+ struct pci_dev *sc_pcidev; /* device backpointer */ -+ ocf_iomem_t sc_bar[5]; -+ caddr_t sc_barphy[5]; /* physical address */ -+ int sc_num; /* for multiple devs */ -+ spinlock_t sc_mtx; /* per-instance lock */ -+ int32_t sc_cid; -+ int sc_irq; -+ -+#if 0 -+ -+ u_int32_t sc_dmaier; -+ u_int32_t sc_drammodel; /* 1=dram, 0=sram */ -+ u_int32_t sc_pllconfig; /* 7954/7955/7956 PLL config */ -+ -+ struct hifn_dma *sc_dma; -+ dma_addr_t sc_dma_physaddr;/* physical address of sc_dma */ -+ -+ int sc_dmansegs; -+ int sc_maxses; -+ int sc_nsessions; -+ struct hifn_session *sc_sessions; -+ int sc_ramsize; -+ int sc_flags; -+#define HIFN_HAS_RNG 0x1 /* includes random number generator */ -+#define HIFN_HAS_PUBLIC 0x2 /* includes public key support */ -+#define HIFN_HAS_AES 0x4 /* includes AES support */ -+#define HIFN_IS_7811 0x8 /* Hifn 7811 part */ -+#define HIFN_IS_7956 0x10 /* Hifn 7956/7955 don't have SDRAM */ -+ -+ struct timer_list sc_tickto; /* for managing DMA */ -+ -+ int sc_rngfirst; -+ int sc_rnghz; /* RNG polling frequency */ -+ -+ int sc_c_busy; /* command ring busy */ -+ int sc_s_busy; /* source data ring busy */ -+ int sc_d_busy; /* destination data ring busy */ -+ int sc_r_busy; /* result ring busy */ -+ int sc_active; /* for initial countdown */ -+ int sc_needwakeup; /* ops q'd wating on resources */ -+ int sc_curbatch; /* # ops submitted w/o int */ -+ int sc_suspended; -+ struct miscdevice sc_miscdev; -+#endif -+}; -+ -+#define HIPP_LOCK(_sc) spin_lock_irqsave(&(_sc)->sc_mtx, l_flags) -+#define HIPP_UNLOCK(_sc) spin_unlock_irqrestore(&(_sc)->sc_mtx, l_flags) -+ -+#endif /* __HIFNHIPPVAR_H__ */ -diff -Nur linux-3.0.4.orig/crypto/ocf/ixp4xx/.#ixp4xx.c.1.46 linux-3.0.4/crypto/ocf/ixp4xx/.#ixp4xx.c.1.46 ---- linux-3.0.4.orig/crypto/ocf/ixp4xx/.#ixp4xx.c.1.46 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/ixp4xx/.#ixp4xx.c.1.46 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,1323 @@ -+/* -+ * An OCF module that uses Intels IXP CryptACC API to do the crypto. -+ * This driver requires the IXP400 Access Library that is available -+ * from Intel in order to operate (or compile). -+ * -+ * Written by David McCullough -+ * Copyright (C) 2006-2007 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * ALTERNATIVELY, provided that this notice is retained in full, this product -+ * may be distributed under the terms of the GNU General Public License (GPL), -+ * in which case the provisions of the GPL apply INSTEAD OF those given above. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ */ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#ifndef IX_MBUF_PRIV -+#define IX_MBUF_PRIV(x) ((x)->priv) -+#endif -+ -+struct ixp_data; -+ -+struct ixp_q { -+ struct list_head ixp_q_list; -+ struct ixp_data *ixp_q_data; -+ struct cryptop *ixp_q_crp; -+ struct cryptodesc *ixp_q_ccrd; -+ struct cryptodesc *ixp_q_acrd; -+ IX_MBUF ixp_q_mbuf; -+ UINT8 *ixp_hash_dest; /* Location for hash in client buffer */ -+ UINT8 *ixp_hash_src; /* Location of hash in internal buffer */ -+ unsigned char ixp_q_iv_data[IX_CRYPTO_ACC_MAX_CIPHER_IV_LENGTH]; -+ unsigned char *ixp_q_iv; -+}; -+ -+struct ixp_data { -+ int ixp_registered; /* is the context registered */ -+ int ixp_crd_flags; /* detect direction changes */ -+ -+ int ixp_cipher_alg; -+ int ixp_auth_alg; -+ -+ UINT32 ixp_ctx_id; -+ UINT32 ixp_hash_key_id; /* used when hashing */ -+ IxCryptoAccCtx ixp_ctx; -+ IX_MBUF ixp_pri_mbuf; -+ IX_MBUF ixp_sec_mbuf; -+ -+ struct work_struct ixp_pending_work; -+ struct work_struct ixp_registration_work; -+ struct list_head ixp_q; /* unprocessed requests */ -+}; -+ -+#ifdef __ixp46X -+ -+#define MAX_IOP_SIZE 64 /* words */ -+#define MAX_OOP_SIZE 128 -+ -+#define MAX_PARAMS 3 -+ -+struct ixp_pkq { -+ struct list_head pkq_list; -+ struct cryptkop *pkq_krp; -+ -+ IxCryptoAccPkeEauInOperands pkq_op; -+ IxCryptoAccPkeEauOpResult pkq_result; -+ -+ UINT32 pkq_ibuf0[MAX_IOP_SIZE]; -+ UINT32 pkq_ibuf1[MAX_IOP_SIZE]; -+ UINT32 pkq_ibuf2[MAX_IOP_SIZE]; -+ UINT32 pkq_obuf[MAX_OOP_SIZE]; -+}; -+ -+static LIST_HEAD(ixp_pkq); /* current PK wait list */ -+static struct ixp_pkq *ixp_pk_cur; -+static spinlock_t ixp_pkq_lock; -+ -+#endif /* __ixp46X */ -+ -+static int ixp_blocked = 0; -+ -+static int32_t ixp_id = -1; -+static struct ixp_data **ixp_sessions = NULL; -+static u_int32_t ixp_sesnum = 0; -+ -+static int ixp_process(device_t, struct cryptop *, int); -+static int ixp_newsession(device_t, u_int32_t *, struct cryptoini *); -+static int ixp_freesession(device_t, u_int64_t); -+#ifdef __ixp46X -+static int ixp_kprocess(device_t, struct cryptkop *krp, int hint); -+#endif -+ -+static struct kmem_cache *qcache; -+ -+#define debug ixp_debug -+static int ixp_debug = 0; -+module_param(ixp_debug, int, 0644); -+MODULE_PARM_DESC(ixp_debug, "Enable debug"); -+ -+static int ixp_init_crypto = 1; -+module_param(ixp_init_crypto, int, 0444); /* RO after load/boot */ -+MODULE_PARM_DESC(ixp_init_crypto, "Call ixCryptoAccInit (default is 1)"); -+ -+static void ixp_process_pending(void *arg); -+static void ixp_registration(void *arg); -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void ixp_process_pending_wq(struct work_struct *work); -+static void ixp_registration_wq(struct work_struct *work); -+#endif -+ -+/* -+ * dummy device structure -+ */ -+ -+static struct { -+ softc_device_decl sc_dev; -+} ixpdev; -+ -+static device_method_t ixp_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, ixp_newsession), -+ DEVMETHOD(cryptodev_freesession,ixp_freesession), -+ DEVMETHOD(cryptodev_process, ixp_process), -+#ifdef __ixp46X -+ DEVMETHOD(cryptodev_kprocess, ixp_kprocess), -+#endif -+}; -+ -+/* -+ * Generate a new software session. -+ */ -+static int -+ixp_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) -+{ -+ struct ixp_data *ixp; -+ u_int32_t i; -+#define AUTH_LEN(cri, def) \ -+ (cri->cri_mlen ? cri->cri_mlen : (def)) -+ -+ dprintk("%s():alg %d\n", __FUNCTION__,cri->cri_alg); -+ if (sid == NULL || cri == NULL) { -+ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ if (ixp_sessions) { -+ for (i = 1; i < ixp_sesnum; i++) -+ if (ixp_sessions[i] == NULL) -+ break; -+ } else -+ i = 1; /* NB: to silence compiler warning */ -+ -+ if (ixp_sessions == NULL || i == ixp_sesnum) { -+ struct ixp_data **ixpd; -+ -+ if (ixp_sessions == NULL) { -+ i = 1; /* We leave ixp_sessions[0] empty */ -+ ixp_sesnum = CRYPTO_SW_SESSIONS; -+ } else -+ ixp_sesnum *= 2; -+ -+ ixpd = kmalloc(ixp_sesnum * sizeof(struct ixp_data *), SLAB_ATOMIC); -+ if (ixpd == NULL) { -+ /* Reset session number */ -+ if (ixp_sesnum == CRYPTO_SW_SESSIONS) -+ ixp_sesnum = 0; -+ else -+ ixp_sesnum /= 2; -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memset(ixpd, 0, ixp_sesnum * sizeof(struct ixp_data *)); -+ -+ /* Copy existing sessions */ -+ if (ixp_sessions) { -+ memcpy(ixpd, ixp_sessions, -+ (ixp_sesnum / 2) * sizeof(struct ixp_data *)); -+ kfree(ixp_sessions); -+ } -+ -+ ixp_sessions = ixpd; -+ } -+ -+ ixp_sessions[i] = (struct ixp_data *) kmalloc(sizeof(struct ixp_data), -+ SLAB_ATOMIC); -+ if (ixp_sessions[i] == NULL) { -+ ixp_freesession(NULL, i); -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ -+ *sid = i; -+ -+ ixp = ixp_sessions[i]; -+ memset(ixp, 0, sizeof(*ixp)); -+ -+ ixp->ixp_cipher_alg = -1; -+ ixp->ixp_auth_alg = -1; -+ ixp->ixp_ctx_id = -1; -+ INIT_LIST_HEAD(&ixp->ixp_q); -+ -+ ixp->ixp_ctx.useDifferentSrcAndDestMbufs = 0; -+ -+ while (cri) { -+ switch (cri->cri_alg) { -+ case CRYPTO_DES_CBC: -+ ixp->ixp_cipher_alg = cri->cri_alg; -+ ixp->ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_DES; -+ ixp->ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; -+ ixp->ixp_ctx.cipherCtx.cipherKeyLen = (cri->cri_klen + 7) / 8; -+ ixp->ixp_ctx.cipherCtx.cipherBlockLen = IX_CRYPTO_ACC_DES_BLOCK_64; -+ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen = -+ IX_CRYPTO_ACC_DES_IV_64; -+ memcpy(ixp->ixp_ctx.cipherCtx.key.cipherKey, -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ break; -+ -+ case CRYPTO_3DES_CBC: -+ ixp->ixp_cipher_alg = cri->cri_alg; -+ ixp->ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_3DES; -+ ixp->ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; -+ ixp->ixp_ctx.cipherCtx.cipherKeyLen = (cri->cri_klen + 7) / 8; -+ ixp->ixp_ctx.cipherCtx.cipherBlockLen = IX_CRYPTO_ACC_DES_BLOCK_64; -+ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen = -+ IX_CRYPTO_ACC_DES_IV_64; -+ memcpy(ixp->ixp_ctx.cipherCtx.key.cipherKey, -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ break; -+ -+ case CRYPTO_RIJNDAEL128_CBC: -+ ixp->ixp_cipher_alg = cri->cri_alg; -+ ixp->ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_AES; -+ ixp->ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; -+ ixp->ixp_ctx.cipherCtx.cipherKeyLen = (cri->cri_klen + 7) / 8; -+ ixp->ixp_ctx.cipherCtx.cipherBlockLen = 16; -+ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen = 16; -+ memcpy(ixp->ixp_ctx.cipherCtx.key.cipherKey, -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ break; -+ -+ case CRYPTO_MD5: -+ case CRYPTO_MD5_HMAC: -+ ixp->ixp_auth_alg = cri->cri_alg; -+ ixp->ixp_ctx.authCtx.authAlgo = IX_CRYPTO_ACC_AUTH_MD5; -+ ixp->ixp_ctx.authCtx.authDigestLen = AUTH_LEN(cri, MD5_HASH_LEN); -+ ixp->ixp_ctx.authCtx.aadLen = 0; -+ /* Only MD5_HMAC needs a key */ -+ if (cri->cri_alg == CRYPTO_MD5_HMAC) { -+ ixp->ixp_ctx.authCtx.authKeyLen = (cri->cri_klen + 7) / 8; -+ if (ixp->ixp_ctx.authCtx.authKeyLen > -+ sizeof(ixp->ixp_ctx.authCtx.key.authKey)) { -+ printk( -+ "ixp4xx: Invalid key length for MD5_HMAC - %d bits\n", -+ cri->cri_klen); -+ ixp_freesession(NULL, i); -+ return EINVAL; -+ } -+ memcpy(ixp->ixp_ctx.authCtx.key.authKey, -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ } -+ break; -+ -+ case CRYPTO_SHA1: -+ case CRYPTO_SHA1_HMAC: -+ ixp->ixp_auth_alg = cri->cri_alg; -+ ixp->ixp_ctx.authCtx.authAlgo = IX_CRYPTO_ACC_AUTH_SHA1; -+ ixp->ixp_ctx.authCtx.authDigestLen = AUTH_LEN(cri, SHA1_HASH_LEN); -+ ixp->ixp_ctx.authCtx.aadLen = 0; -+ /* Only SHA1_HMAC needs a key */ -+ if (cri->cri_alg == CRYPTO_SHA1_HMAC) { -+ ixp->ixp_ctx.authCtx.authKeyLen = (cri->cri_klen + 7) / 8; -+ if (ixp->ixp_ctx.authCtx.authKeyLen > -+ sizeof(ixp->ixp_ctx.authCtx.key.authKey)) { -+ printk( -+ "ixp4xx: Invalid key length for SHA1_HMAC - %d bits\n", -+ cri->cri_klen); -+ ixp_freesession(NULL, i); -+ return EINVAL; -+ } -+ memcpy(ixp->ixp_ctx.authCtx.key.authKey, -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ } -+ break; -+ -+ default: -+ printk("ixp: unknown algo 0x%x\n", cri->cri_alg); -+ ixp_freesession(NULL, i); -+ return EINVAL; -+ } -+ cri = cri->cri_next; -+ } -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ INIT_WORK(&ixp->ixp_pending_work, ixp_process_pending_wq); -+ INIT_WORK(&ixp->ixp_registration_work, ixp_registration_wq); -+#else -+ INIT_WORK(&ixp->ixp_pending_work, ixp_process_pending, ixp); -+ INIT_WORK(&ixp->ixp_registration_work, ixp_registration, ixp); -+#endif -+ -+ return 0; -+} -+ -+ -+/* -+ * Free a session. -+ */ -+static int -+ixp_freesession(device_t dev, u_int64_t tid) -+{ -+ u_int32_t sid = CRYPTO_SESID2LID(tid); -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid > ixp_sesnum || ixp_sessions == NULL || -+ ixp_sessions[sid] == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ /* Silently accept and return */ -+ if (sid == 0) -+ return 0; -+ -+ if (ixp_sessions[sid]) { -+ if (ixp_sessions[sid]->ixp_ctx_id != -1) { -+ ixCryptoAccCtxUnregister(ixp_sessions[sid]->ixp_ctx_id); -+ ixp_sessions[sid]->ixp_ctx_id = -1; -+ } -+ -+ flush_scheduled_work(); -+ -+ kfree(ixp_sessions[sid]); -+ } -+ ixp_sessions[sid] = NULL; -+ if (ixp_blocked) { -+ ixp_blocked = 0; -+ crypto_unblock(ixp_id, CRYPTO_SYMQ); -+ } -+ return 0; -+} -+ -+ -+/* -+ * callback for when hash processing is complete -+ */ -+ -+static void -+ixp_hash_perform_cb( -+ UINT32 hash_key_id, -+ IX_MBUF *bufp, -+ IxCryptoAccStatus status) -+{ -+ struct ixp_q *q; -+ -+ dprintk("%s(%u, %p, 0x%x)\n", __FUNCTION__, hash_key_id, bufp, status); -+ -+ if (bufp == NULL) { -+ printk("ixp: NULL buf in %s\n", __FUNCTION__); -+ return; -+ } -+ -+ q = IX_MBUF_PRIV(bufp); -+ if (q == NULL) { -+ printk("ixp: NULL priv in %s\n", __FUNCTION__); -+ return; -+ } -+ -+ if (status == IX_CRYPTO_ACC_STATUS_SUCCESS) { -+ /* On success, need to copy hash back into original client buffer */ -+ memcpy(q->ixp_hash_dest, q->ixp_hash_src, -+ (q->ixp_q_data->ixp_auth_alg == CRYPTO_SHA1) ? -+ SHA1_HASH_LEN : MD5_HASH_LEN); -+ } -+ else { -+ printk("ixp: hash perform failed status=%d\n", status); -+ q->ixp_q_crp->crp_etype = EINVAL; -+ } -+ -+ /* Free internal buffer used for hashing */ -+ kfree(IX_MBUF_MDATA(&q->ixp_q_mbuf)); -+ -+ crypto_done(q->ixp_q_crp); -+ kmem_cache_free(qcache, q); -+} -+ -+/* -+ * setup a request and perform it -+ */ -+static void -+ixp_q_process(struct ixp_q *q) -+{ -+ IxCryptoAccStatus status; -+ struct ixp_data *ixp = q->ixp_q_data; -+ int auth_off = 0; -+ int auth_len = 0; -+ int crypt_off = 0; -+ int crypt_len = 0; -+ int icv_off = 0; -+ char *crypt_func; -+ -+ dprintk("%s(%p)\n", __FUNCTION__, q); -+ -+ if (q->ixp_q_ccrd) { -+ if (q->ixp_q_ccrd->crd_flags & CRD_F_IV_EXPLICIT) { -+ q->ixp_q_iv = q->ixp_q_ccrd->crd_iv; -+ } else { -+ q->ixp_q_iv = q->ixp_q_iv_data; -+ crypto_copydata(q->ixp_q_crp->crp_flags, q->ixp_q_crp->crp_buf, -+ q->ixp_q_ccrd->crd_inject, -+ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen, -+ (caddr_t) q->ixp_q_iv); -+ } -+ -+ if (q->ixp_q_acrd) { -+ auth_off = q->ixp_q_acrd->crd_skip; -+ auth_len = q->ixp_q_acrd->crd_len; -+ icv_off = q->ixp_q_acrd->crd_inject; -+ } -+ -+ crypt_off = q->ixp_q_ccrd->crd_skip; -+ crypt_len = q->ixp_q_ccrd->crd_len; -+ } else { /* if (q->ixp_q_acrd) */ -+ auth_off = q->ixp_q_acrd->crd_skip; -+ auth_len = q->ixp_q_acrd->crd_len; -+ icv_off = q->ixp_q_acrd->crd_inject; -+ } -+ -+ if (q->ixp_q_crp->crp_flags & CRYPTO_F_SKBUF) { -+ struct sk_buff *skb = (struct sk_buff *) q->ixp_q_crp->crp_buf; -+ if (skb_shinfo(skb)->nr_frags) { -+ /* -+ * DAVIDM fix this limitation one day by using -+ * a buffer pool and chaining, it is not currently -+ * needed for current user/kernel space acceleration -+ */ -+ printk("ixp: Cannot handle fragmented skb's yet !\n"); -+ q->ixp_q_crp->crp_etype = ENOENT; -+ goto done; -+ } -+ IX_MBUF_MLEN(&q->ixp_q_mbuf) = -+ IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = skb->len; -+ IX_MBUF_MDATA(&q->ixp_q_mbuf) = skb->data; -+ } else if (q->ixp_q_crp->crp_flags & CRYPTO_F_IOV) { -+ struct uio *uiop = (struct uio *) q->ixp_q_crp->crp_buf; -+ if (uiop->uio_iovcnt != 1) { -+ /* -+ * DAVIDM fix this limitation one day by using -+ * a buffer pool and chaining, it is not currently -+ * needed for current user/kernel space acceleration -+ */ -+ printk("ixp: Cannot handle more than 1 iovec yet !\n"); -+ q->ixp_q_crp->crp_etype = ENOENT; -+ goto done; -+ } -+ IX_MBUF_MLEN(&q->ixp_q_mbuf) = -+ IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = uiop->uio_iov[0].iov_len; -+ IX_MBUF_MDATA(&q->ixp_q_mbuf) = uiop->uio_iov[0].iov_base; -+ } else /* contig buffer */ { -+ IX_MBUF_MLEN(&q->ixp_q_mbuf) = -+ IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = q->ixp_q_crp->crp_ilen; -+ IX_MBUF_MDATA(&q->ixp_q_mbuf) = q->ixp_q_crp->crp_buf; -+ } -+ -+ IX_MBUF_PRIV(&q->ixp_q_mbuf) = q; -+ -+ if (ixp->ixp_auth_alg == CRYPTO_SHA1 || ixp->ixp_auth_alg == CRYPTO_MD5) { -+ /* -+ * For SHA1 and MD5 hash, need to create an internal buffer that is big -+ * enough to hold the original data + the appropriate padding for the -+ * hash algorithm. -+ */ -+ UINT8 *tbuf = NULL; -+ -+ IX_MBUF_MLEN(&q->ixp_q_mbuf) = IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = -+ ((IX_MBUF_MLEN(&q->ixp_q_mbuf) * 8) + 72 + 511) / 8; -+ tbuf = kmalloc(IX_MBUF_MLEN(&q->ixp_q_mbuf), SLAB_ATOMIC); -+ -+ if (IX_MBUF_MDATA(&q->ixp_q_mbuf) == NULL) { -+ printk("ixp: kmalloc(%u, SLAB_ATOMIC) failed\n", -+ IX_MBUF_MLEN(&q->ixp_q_mbuf)); -+ q->ixp_q_crp->crp_etype = ENOMEM; -+ goto done; -+ } -+ memcpy(tbuf, &(IX_MBUF_MDATA(&q->ixp_q_mbuf))[auth_off], auth_len); -+ -+ /* Set location in client buffer to copy hash into */ -+ q->ixp_hash_dest = -+ &(IX_MBUF_MDATA(&q->ixp_q_mbuf))[auth_off + auth_len]; -+ -+ IX_MBUF_MDATA(&q->ixp_q_mbuf) = tbuf; -+ -+ /* Set location in internal buffer for where hash starts */ -+ q->ixp_hash_src = &(IX_MBUF_MDATA(&q->ixp_q_mbuf))[auth_len]; -+ -+ crypt_func = "ixCryptoAccHashPerform"; -+ status = ixCryptoAccHashPerform(ixp->ixp_ctx.authCtx.authAlgo, -+ &q->ixp_q_mbuf, ixp_hash_perform_cb, 0, auth_len, auth_len, -+ &ixp->ixp_hash_key_id); -+ } -+ else { -+ crypt_func = "ixCryptoAccAuthCryptPerform"; -+ status = ixCryptoAccAuthCryptPerform(ixp->ixp_ctx_id, &q->ixp_q_mbuf, -+ NULL, auth_off, auth_len, crypt_off, crypt_len, icv_off, -+ q->ixp_q_iv); -+ } -+ -+ if (IX_CRYPTO_ACC_STATUS_QUEUE_FULL == status) { -+ q->ixp_q_crp->crp_etype = ENOMEM; -+ goto done; -+ } -+ -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS != status) { -+ printk("ixp: %s failed %u\n", crypt_func, status); -+ q->ixp_q_crp->crp_etype = EINVAL; -+ } -+ -+done: -+ crypto_done(q->ixp_q_crp); -+ kmem_cache_free(qcache, q); -+} -+ -+ -+/* -+ * because we cannot process the Q from the Register callback -+ * we do it here on a task Q. -+ */ -+ -+static void -+ixp_process_pending(void *arg) -+{ -+ struct ixp_data *ixp = arg; -+ struct ixp_q *q = NULL; -+ -+ dprintk("%s(%p)\n", __FUNCTION__, arg); -+ -+ if (!ixp) -+ return; -+ -+ while (!list_empty(&ixp->ixp_q)) { -+ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); -+ list_del(&q->ixp_q_list); -+ ixp_q_process(q); -+ } -+} -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void -+ixp_process_pending_wq(struct work_struct *work) -+{ -+ struct ixp_data *ixp = container_of(work, struct ixp_data, -+ ixp_pending_work); -+ ixp_process_pending(ixp); -+} -+#endif -+ -+/* -+ * callback for when context registration is complete -+ */ -+ -+static void -+ixp_register_cb(UINT32 ctx_id, IX_MBUF *bufp, IxCryptoAccStatus status) -+{ -+ int i; -+ struct ixp_data *ixp; -+ struct ixp_q *q; -+ -+ dprintk("%s(%d, %p, %d)\n", __FUNCTION__, ctx_id, bufp, status); -+ -+ /* -+ * free any buffer passed in to this routine -+ */ -+ if (bufp) { -+ IX_MBUF_MLEN(bufp) = IX_MBUF_PKT_LEN(bufp) = 0; -+ kfree(IX_MBUF_MDATA(bufp)); -+ IX_MBUF_MDATA(bufp) = NULL; -+ } -+ -+ for (i = 0; i < ixp_sesnum; i++) { -+ ixp = ixp_sessions[i]; -+ if (ixp && ixp->ixp_ctx_id == ctx_id) -+ break; -+ } -+ if (i >= ixp_sesnum) { -+ printk("ixp: invalid context id %d\n", ctx_id); -+ return; -+ } -+ -+ if (IX_CRYPTO_ACC_STATUS_WAIT == status) { -+ /* this is normal to free the first of two buffers */ -+ dprintk("ixp: register not finished yet.\n"); -+ return; -+ } -+ -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS != status) { -+ printk("ixp: register failed 0x%x\n", status); -+ while (!list_empty(&ixp->ixp_q)) { -+ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); -+ list_del(&q->ixp_q_list); -+ q->ixp_q_crp->crp_etype = EINVAL; -+ crypto_done(q->ixp_q_crp); -+ kmem_cache_free(qcache, q); -+ } -+ return; -+ } -+ -+ /* -+ * we are now registered, we cannot start processing the Q here -+ * or we get strange errors with AES (DES/3DES seem to be ok). -+ */ -+ ixp->ixp_registered = 1; -+ schedule_work(&ixp->ixp_pending_work); -+} -+ -+ -+/* -+ * callback for when data processing is complete -+ */ -+ -+static void -+ixp_perform_cb( -+ UINT32 ctx_id, -+ IX_MBUF *sbufp, -+ IX_MBUF *dbufp, -+ IxCryptoAccStatus status) -+{ -+ struct ixp_q *q; -+ -+ dprintk("%s(%d, %p, %p, 0x%x)\n", __FUNCTION__, ctx_id, sbufp, -+ dbufp, status); -+ -+ if (sbufp == NULL) { -+ printk("ixp: NULL sbuf in ixp_perform_cb\n"); -+ return; -+ } -+ -+ q = IX_MBUF_PRIV(sbufp); -+ if (q == NULL) { -+ printk("ixp: NULL priv in ixp_perform_cb\n"); -+ return; -+ } -+ -+ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { -+ printk("ixp: perform failed status=%d\n", status); -+ q->ixp_q_crp->crp_etype = EINVAL; -+ } -+ -+ crypto_done(q->ixp_q_crp); -+ kmem_cache_free(qcache, q); -+} -+ -+ -+/* -+ * registration is not callable at IRQ time, so we defer -+ * to a task queue, this routines completes the registration for us -+ * when the task queue runs -+ * -+ * Unfortunately this means we cannot tell OCF that the driver is blocked, -+ * we do that on the next request. -+ */ -+ -+static void -+ixp_registration(void *arg) -+{ -+ struct ixp_data *ixp = arg; -+ struct ixp_q *q = NULL; -+ IX_MBUF *pri = NULL, *sec = NULL; -+ int status = IX_CRYPTO_ACC_STATUS_SUCCESS; -+ -+ if (!ixp) { -+ printk("ixp: ixp_registration with no arg\n"); -+ return; -+ } -+ -+ if (ixp->ixp_ctx_id != -1) { -+ ixCryptoAccCtxUnregister(ixp->ixp_ctx_id); -+ ixp->ixp_ctx_id = -1; -+ } -+ -+ if (list_empty(&ixp->ixp_q)) { -+ printk("ixp: ixp_registration with no Q\n"); -+ return; -+ } -+ -+ /* -+ * setup the primary and secondary buffers -+ */ -+ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); -+ if (q->ixp_q_acrd) { -+ pri = &ixp->ixp_pri_mbuf; -+ sec = &ixp->ixp_sec_mbuf; -+ IX_MBUF_MLEN(pri) = IX_MBUF_PKT_LEN(pri) = 128; -+ IX_MBUF_MDATA(pri) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); -+ IX_MBUF_MLEN(sec) = IX_MBUF_PKT_LEN(sec) = 128; -+ IX_MBUF_MDATA(sec) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); -+ } -+ -+ /* Only need to register if a crypt op or HMAC op */ -+ if (!(ixp->ixp_auth_alg == CRYPTO_SHA1 || -+ ixp->ixp_auth_alg == CRYPTO_MD5)) { -+ status = ixCryptoAccCtxRegister( -+ &ixp->ixp_ctx, -+ pri, sec, -+ ixp_register_cb, -+ ixp_perform_cb, -+ &ixp->ixp_ctx_id); -+ } -+ else { -+ /* Otherwise we start processing pending q */ -+ schedule_work(&ixp->ixp_pending_work); -+ } -+ -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) -+ return; -+ -+ if (IX_CRYPTO_ACC_STATUS_EXCEED_MAX_TUNNELS == status) { -+ printk("ixp: ixCryptoAccCtxRegister failed (out of tunnels)\n"); -+ ixp_blocked = 1; -+ /* perhaps we should return EGAIN on queued ops ? */ -+ return; -+ } -+ -+ printk("ixp: ixCryptoAccCtxRegister failed %d\n", status); -+ ixp->ixp_ctx_id = -1; -+ -+ /* -+ * everything waiting is toasted -+ */ -+ while (!list_empty(&ixp->ixp_q)) { -+ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); -+ list_del(&q->ixp_q_list); -+ q->ixp_q_crp->crp_etype = ENOENT; -+ crypto_done(q->ixp_q_crp); -+ kmem_cache_free(qcache, q); -+ } -+} -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void -+ixp_registration_wq(struct work_struct *work) -+{ -+ struct ixp_data *ixp = container_of(work, struct ixp_data, -+ ixp_registration_work); -+ ixp_registration(ixp); -+} -+#endif -+ -+/* -+ * Process a request. -+ */ -+static int -+ixp_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ struct ixp_data *ixp; -+ unsigned int lid; -+ struct ixp_q *q = NULL; -+ int status; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ /* Sanity check */ -+ if (crp == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ crp->crp_etype = 0; -+ -+ if (ixp_blocked) -+ return ERESTART; -+ -+ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ /* -+ * find the session we are using -+ */ -+ -+ lid = crp->crp_sid & 0xffffffff; -+ if (lid >= ixp_sesnum || lid == 0 || ixp_sessions == NULL || -+ ixp_sessions[lid] == NULL) { -+ crp->crp_etype = ENOENT; -+ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); -+ goto done; -+ } -+ ixp = ixp_sessions[lid]; -+ -+ /* -+ * setup a new request ready for queuing -+ */ -+ q = kmem_cache_alloc(qcache, SLAB_ATOMIC); -+ if (q == NULL) { -+ dprintk("%s,%d: ENOMEM\n", __FILE__, __LINE__); -+ crp->crp_etype = ENOMEM; -+ goto done; -+ } -+ /* -+ * save some cycles by only zeroing the important bits -+ */ -+ memset(&q->ixp_q_mbuf, 0, sizeof(q->ixp_q_mbuf)); -+ q->ixp_q_ccrd = NULL; -+ q->ixp_q_acrd = NULL; -+ q->ixp_q_crp = crp; -+ q->ixp_q_data = ixp; -+ -+ /* -+ * point the cipher and auth descriptors appropriately -+ * check that we have something to do -+ */ -+ if (crp->crp_desc->crd_alg == ixp->ixp_cipher_alg) -+ q->ixp_q_ccrd = crp->crp_desc; -+ else if (crp->crp_desc->crd_alg == ixp->ixp_auth_alg) -+ q->ixp_q_acrd = crp->crp_desc; -+ else { -+ crp->crp_etype = ENOENT; -+ dprintk("%s,%d: bad desc match: ENOENT\n", __FILE__, __LINE__); -+ goto done; -+ } -+ if (crp->crp_desc->crd_next) { -+ if (crp->crp_desc->crd_next->crd_alg == ixp->ixp_cipher_alg) -+ q->ixp_q_ccrd = crp->crp_desc->crd_next; -+ else if (crp->crp_desc->crd_next->crd_alg == ixp->ixp_auth_alg) -+ q->ixp_q_acrd = crp->crp_desc->crd_next; -+ else { -+ crp->crp_etype = ENOENT; -+ dprintk("%s,%d: bad desc match: ENOENT\n", __FILE__, __LINE__); -+ goto done; -+ } -+ } -+ -+ /* -+ * If there is a direction change for this context then we mark it as -+ * unregistered and re-register is for the new direction. This is not -+ * a very expensive operation and currently only tends to happen when -+ * user-space application are doing benchmarks -+ * -+ * DM - we should be checking for pending requests before unregistering. -+ */ -+ if (q->ixp_q_ccrd && ixp->ixp_registered && -+ ixp->ixp_crd_flags != (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT)) { -+ dprintk("%s - detected direction change on session\n", __FUNCTION__); -+ ixp->ixp_registered = 0; -+ } -+ -+ /* -+ * if we are registered, call straight into the perform code -+ */ -+ if (ixp->ixp_registered) { -+ ixp_q_process(q); -+ return 0; -+ } -+ -+ /* -+ * the only part of the context not set in newsession is the direction -+ * dependent parts -+ */ -+ if (q->ixp_q_ccrd) { -+ ixp->ixp_crd_flags = (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT); -+ if (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT) { -+ ixp->ixp_ctx.operation = q->ixp_q_acrd ? -+ IX_CRYPTO_ACC_OP_ENCRYPT_AUTH : IX_CRYPTO_ACC_OP_ENCRYPT; -+ } else { -+ ixp->ixp_ctx.operation = q->ixp_q_acrd ? -+ IX_CRYPTO_ACC_OP_AUTH_DECRYPT : IX_CRYPTO_ACC_OP_DECRYPT; -+ } -+ } else { -+ /* q->ixp_q_acrd must be set if we are here */ -+ ixp->ixp_ctx.operation = IX_CRYPTO_ACC_OP_AUTH_CALC; -+ } -+ -+ status = list_empty(&ixp->ixp_q); -+ list_add_tail(&q->ixp_q_list, &ixp->ixp_q); -+ if (status) -+ schedule_work(&ixp->ixp_registration_work); -+ return 0; -+ -+done: -+ if (q) -+ kmem_cache_free(qcache, q); -+ crypto_done(crp); -+ return 0; -+} -+ -+ -+#ifdef __ixp46X -+/* -+ * key processing support for the ixp465 -+ */ -+ -+ -+/* -+ * copy a BN (LE) into a buffer (BE) an fill out the op appropriately -+ * assume zeroed and only copy bits that are significant -+ */ -+ -+static int -+ixp_copy_ibuf(struct crparam *p, IxCryptoAccPkeEauOperand *op, UINT32 *buf) -+{ -+ unsigned char *src = (unsigned char *) p->crp_p; -+ unsigned char *dst; -+ int len, bits = p->crp_nbits; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (bits > MAX_IOP_SIZE * sizeof(UINT32) * 8) { -+ dprintk("%s - ibuf too big (%d > %d)\n", __FUNCTION__, -+ bits, MAX_IOP_SIZE * sizeof(UINT32) * 8); -+ return -1; -+ } -+ -+ len = (bits + 31) / 32; /* the number UINT32's needed */ -+ -+ dst = (unsigned char *) &buf[len]; -+ dst--; -+ -+ while (bits > 0) { -+ *dst-- = *src++; -+ bits -= 8; -+ } -+ -+#if 0 /* no need to zero remaining bits as it is done during request alloc */ -+ while (dst > (unsigned char *) buf) -+ *dst-- = '\0'; -+#endif -+ -+ op->pData = buf; -+ op->dataLen = len; -+ return 0; -+} -+ -+/* -+ * copy out the result, be as forgiving as we can about small output buffers -+ */ -+ -+static int -+ixp_copy_obuf(struct crparam *p, IxCryptoAccPkeEauOpResult *op, UINT32 *buf) -+{ -+ unsigned char *dst = (unsigned char *) p->crp_p; -+ unsigned char *src = (unsigned char *) buf; -+ int len, z, bits = p->crp_nbits; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ len = op->dataLen * sizeof(UINT32); -+ -+ /* skip leading zeroes to be small buffer friendly */ -+ z = 0; -+ while (z < len && src[z] == '\0') -+ z++; -+ -+ src += len; -+ src--; -+ len -= z; -+ -+ while (len > 0 && bits > 0) { -+ *dst++ = *src--; -+ len--; -+ bits -= 8; -+ } -+ -+ while (bits > 0) { -+ *dst++ = '\0'; -+ bits -= 8; -+ } -+ -+ if (len > 0) { -+ dprintk("%s - obuf is %d (z=%d, ob=%d) bytes too small\n", -+ __FUNCTION__, len, z, p->crp_nbits / 8); -+ return -1; -+ } -+ -+ return 0; -+} -+ -+ -+/* -+ * the parameter offsets for exp_mod -+ */ -+ -+#define IXP_PARAM_BASE 0 -+#define IXP_PARAM_EXP 1 -+#define IXP_PARAM_MOD 2 -+#define IXP_PARAM_RES 3 -+ -+/* -+ * key processing complete callback, is also used to start processing -+ * by passing a NULL for pResult -+ */ -+ -+static void -+ixp_kperform_cb( -+ IxCryptoAccPkeEauOperation operation, -+ IxCryptoAccPkeEauOpResult *pResult, -+ BOOL carryOrBorrow, -+ IxCryptoAccStatus status) -+{ -+ struct ixp_pkq *q, *tmp; -+ unsigned long flags; -+ -+ dprintk("%s(0x%x, %p, %d, 0x%x)\n", __FUNCTION__, operation, pResult, -+ carryOrBorrow, status); -+ -+ /* handle a completed request */ -+ if (pResult) { -+ if (ixp_pk_cur && &ixp_pk_cur->pkq_result == pResult) { -+ q = ixp_pk_cur; -+ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { -+ dprintk("%s() - op failed 0x%x\n", __FUNCTION__, status); -+ q->pkq_krp->krp_status = ERANGE; /* could do better */ -+ } else { -+ /* copy out the result */ -+ if (ixp_copy_obuf(&q->pkq_krp->krp_param[IXP_PARAM_RES], -+ &q->pkq_result, q->pkq_obuf)) -+ q->pkq_krp->krp_status = ERANGE; -+ } -+ crypto_kdone(q->pkq_krp); -+ kfree(q); -+ ixp_pk_cur = NULL; -+ } else -+ printk("%s - callback with invalid result pointer\n", __FUNCTION__); -+ } -+ -+ spin_lock_irqsave(&ixp_pkq_lock, flags); -+ if (ixp_pk_cur || list_empty(&ixp_pkq)) { -+ spin_unlock_irqrestore(&ixp_pkq_lock, flags); -+ return; -+ } -+ -+ list_for_each_entry_safe(q, tmp, &ixp_pkq, pkq_list) { -+ -+ list_del(&q->pkq_list); -+ ixp_pk_cur = q; -+ -+ spin_unlock_irqrestore(&ixp_pkq_lock, flags); -+ -+ status = ixCryptoAccPkeEauPerform( -+ IX_CRYPTO_ACC_OP_EAU_MOD_EXP, -+ &q->pkq_op, -+ ixp_kperform_cb, -+ &q->pkq_result); -+ -+ if (status == IX_CRYPTO_ACC_STATUS_SUCCESS) { -+ dprintk("%s() - ixCryptoAccPkeEauPerform SUCCESS\n", __FUNCTION__); -+ return; /* callback will return here for callback */ -+ } else if (status == IX_CRYPTO_ACC_STATUS_RETRY) { -+ printk("%s() - ixCryptoAccPkeEauPerform RETRY\n", __FUNCTION__); -+ } else { -+ printk("%s() - ixCryptoAccPkeEauPerform failed %d\n", -+ __FUNCTION__, status); -+ } -+ q->pkq_krp->krp_status = ERANGE; /* could do better */ -+ crypto_kdone(q->pkq_krp); -+ kfree(q); -+ spin_lock_irqsave(&ixp_pkq_lock, flags); -+ } -+ spin_unlock_irqrestore(&ixp_pkq_lock, flags); -+} -+ -+ -+static int -+ixp_kprocess(device_t dev, struct cryptkop *krp, int hint) -+{ -+ struct ixp_pkq *q; -+ int rc = 0; -+ unsigned long flags; -+ -+ dprintk("%s l1=%d l2=%d l3=%d l4=%d\n", __FUNCTION__, -+ krp->krp_param[IXP_PARAM_BASE].crp_nbits, -+ krp->krp_param[IXP_PARAM_EXP].crp_nbits, -+ krp->krp_param[IXP_PARAM_MOD].crp_nbits, -+ krp->krp_param[IXP_PARAM_RES].crp_nbits); -+ -+ -+ if (krp->krp_op != CRK_MOD_EXP) { -+ krp->krp_status = EOPNOTSUPP; -+ goto err; -+ } -+ -+ q = (struct ixp_pkq *) kmalloc(sizeof(*q), GFP_KERNEL); -+ if (q == NULL) { -+ krp->krp_status = ENOMEM; -+ goto err; -+ } -+ -+ /* -+ * The PKE engine does not appear to zero the output buffer -+ * appropriately, so we need to do it all here. -+ */ -+ memset(q, 0, sizeof(*q)); -+ -+ q->pkq_krp = krp; -+ INIT_LIST_HEAD(&q->pkq_list); -+ -+ if (ixp_copy_ibuf(&krp->krp_param[IXP_PARAM_BASE], &q->pkq_op.modExpOpr.M, -+ q->pkq_ibuf0)) -+ rc = 1; -+ if (!rc && ixp_copy_ibuf(&krp->krp_param[IXP_PARAM_EXP], -+ &q->pkq_op.modExpOpr.e, q->pkq_ibuf1)) -+ rc = 2; -+ if (!rc && ixp_copy_ibuf(&krp->krp_param[IXP_PARAM_MOD], -+ &q->pkq_op.modExpOpr.N, q->pkq_ibuf2)) -+ rc = 3; -+ -+ if (rc) { -+ kfree(q); -+ krp->krp_status = ERANGE; -+ goto err; -+ } -+ -+ q->pkq_result.pData = q->pkq_obuf; -+ q->pkq_result.dataLen = -+ (krp->krp_param[IXP_PARAM_RES].crp_nbits + 31) / 32; -+ -+ spin_lock_irqsave(&ixp_pkq_lock, flags); -+ list_add_tail(&q->pkq_list, &ixp_pkq); -+ spin_unlock_irqrestore(&ixp_pkq_lock, flags); -+ -+ if (!ixp_pk_cur) -+ ixp_kperform_cb(0, NULL, 0, 0); -+ return (0); -+ -+err: -+ crypto_kdone(krp); -+ return (0); -+} -+ -+ -+ -+#ifdef CONFIG_OCF_RANDOMHARVEST -+/* -+ * We run the random number generator output through SHA so that it -+ * is FIPS compliant. -+ */ -+ -+static volatile int sha_done = 0; -+static unsigned char sha_digest[20]; -+ -+static void -+ixp_hash_cb(UINT8 *digest, IxCryptoAccStatus status) -+{ -+ dprintk("%s(%p, %d)\n", __FUNCTION__, digest, status); -+ if (sha_digest != digest) -+ printk("digest error\n"); -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) -+ sha_done = 1; -+ else -+ sha_done = -status; -+} -+ -+static int -+ixp_read_random(void *arg, u_int32_t *buf, int maxwords) -+{ -+ IxCryptoAccStatus status; -+ int i, n, rc; -+ -+ dprintk("%s(%p, %d)\n", __FUNCTION__, buf, maxwords); -+ memset(buf, 0, maxwords * sizeof(*buf)); -+ status = ixCryptoAccPkePseudoRandomNumberGet(maxwords, buf); -+ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { -+ dprintk("%s: ixCryptoAccPkePseudoRandomNumberGet failed %d\n", -+ __FUNCTION__, status); -+ return 0; -+ } -+ -+ /* -+ * run the random data through SHA to make it look more random -+ */ -+ -+ n = sizeof(sha_digest); /* process digest bytes at a time */ -+ -+ rc = 0; -+ for (i = 0; i < maxwords; i += n / sizeof(*buf)) { -+ if ((maxwords - i) * sizeof(*buf) < n) -+ n = (maxwords - i) * sizeof(*buf); -+ sha_done = 0; -+ status = ixCryptoAccPkeHashPerform(IX_CRYPTO_ACC_AUTH_SHA1, -+ (UINT8 *) &buf[i], n, ixp_hash_cb, sha_digest); -+ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { -+ dprintk("ixCryptoAccPkeHashPerform failed %d\n", status); -+ return -EIO; -+ } -+ while (!sha_done) -+ schedule(); -+ if (sha_done < 0) { -+ dprintk("ixCryptoAccPkeHashPerform failed CB %d\n", -sha_done); -+ return 0; -+ } -+ memcpy(&buf[i], sha_digest, n); -+ rc += n / sizeof(*buf);; -+ } -+ -+ return rc; -+} -+#endif /* CONFIG_OCF_RANDOMHARVEST */ -+ -+#endif /* __ixp46X */ -+ -+ -+ -+/* -+ * our driver startup and shutdown routines -+ */ -+ -+static int -+ixp_init(void) -+{ -+ dprintk("%s(%p)\n", __FUNCTION__, ixp_init); -+ -+ if (ixp_init_crypto && ixCryptoAccInit() != IX_CRYPTO_ACC_STATUS_SUCCESS) -+ printk("ixCryptoAccInit failed, assuming already initialised!\n"); -+ -+ qcache = kmem_cache_create("ixp4xx_q", sizeof(struct ixp_q), 0, -+ SLAB_HWCACHE_ALIGN, NULL -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) -+ , NULL -+#endif -+ ); -+ if (!qcache) { -+ printk("failed to create Qcache\n"); -+ return -ENOENT; -+ } -+ -+ memset(&ixpdev, 0, sizeof(ixpdev)); -+ softc_device_init(&ixpdev, "ixp4xx", 0, ixp_methods); -+ -+ ixp_id = crypto_get_driverid(softc_get_device(&ixpdev), -+ CRYPTOCAP_F_HARDWARE); -+ if (ixp_id < 0) -+ panic("IXP/OCF crypto device cannot initialize!"); -+ -+#define REGISTER(alg) \ -+ crypto_register(ixp_id,alg,0,0) -+ -+ REGISTER(CRYPTO_DES_CBC); -+ REGISTER(CRYPTO_3DES_CBC); -+ REGISTER(CRYPTO_RIJNDAEL128_CBC); -+#ifdef CONFIG_OCF_IXP4XX_SHA1_MD5 -+ REGISTER(CRYPTO_MD5); -+ REGISTER(CRYPTO_SHA1); -+#endif -+ REGISTER(CRYPTO_MD5_HMAC); -+ REGISTER(CRYPTO_SHA1_HMAC); -+#undef REGISTER -+ -+#ifdef __ixp46X -+ spin_lock_init(&ixp_pkq_lock); -+ /* -+ * we do not enable the go fast options here as they can potentially -+ * allow timing based attacks -+ * -+ * http://www.openssl.org/news/secadv_20030219.txt -+ */ -+ ixCryptoAccPkeEauExpConfig(0, 0); -+ crypto_kregister(ixp_id, CRK_MOD_EXP, 0); -+#ifdef CONFIG_OCF_RANDOMHARVEST -+ crypto_rregister(ixp_id, ixp_read_random, NULL); -+#endif -+#endif -+ -+ return 0; -+} -+ -+static void -+ixp_exit(void) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ crypto_unregister_all(ixp_id); -+ ixp_id = -1; -+ kmem_cache_destroy(qcache); -+ qcache = NULL; -+} -+ -+module_init(ixp_init); -+module_exit(ixp_exit); -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("ixp (OCF module for IXP4xx crypto)"); -diff -Nur linux-3.0.4.orig/crypto/ocf/ixp4xx/Makefile linux-3.0.4/crypto/ocf/ixp4xx/Makefile ---- linux-3.0.4.orig/crypto/ocf/ixp4xx/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/ixp4xx/Makefile 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,104 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+# -+# You will need to point this at your Intel ixp425 includes, this portion -+# of the Makefile only really works under SGLinux with the appropriate libs -+# installed. They can be downloaded from http://www.snapgear.org/ -+# -+ifeq ($(CONFIG_CPU_IXP46X),y) -+IXPLATFORM = ixp46X -+else -+ifeq ($(CONFIG_CPU_IXP43X),y) -+IXPLATFORM = ixp43X -+else -+IXPLATFORM = ixp42X -+endif -+endif -+ -+ifdef CONFIG_IXP400_LIB_2_4 -+IX_XSCALE_SW = $(ROOTDIR)/modules/ixp425/ixp400-2.4/ixp400_xscale_sw -+OSAL_DIR = $(ROOTDIR)/modules/ixp425/ixp400-2.4/ixp_osal -+endif -+ifdef CONFIG_IXP400_LIB_2_1 -+IX_XSCALE_SW = $(ROOTDIR)/modules/ixp425/ixp400-2.1/ixp400_xscale_sw -+OSAL_DIR = $(ROOTDIR)/modules/ixp425/ixp400-2.1/ixp_osal -+endif -+ifdef CONFIG_IXP400_LIB_2_0 -+IX_XSCALE_SW = $(ROOTDIR)/modules/ixp425/ixp400-2.0/ixp400_xscale_sw -+OSAL_DIR = $(ROOTDIR)/modules/ixp425/ixp400-2.0/ixp_osal -+endif -+ifdef IX_XSCALE_SW -+ifdef CONFIG_IXP400_LIB_2_4 -+IXP_CFLAGS = \ -+ -I$(ROOTDIR)/. \ -+ -I$(IX_XSCALE_SW)/src/include \ -+ -I$(OSAL_DIR)/common/include/ \ -+ -I$(OSAL_DIR)/common/include/modules/ \ -+ -I$(OSAL_DIR)/common/include/modules/ddk/ \ -+ -I$(OSAL_DIR)/common/include/modules/bufferMgt/ \ -+ -I$(OSAL_DIR)/common/include/modules/ioMem/ \ -+ -I$(OSAL_DIR)/common/os/linux/include/ \ -+ -I$(OSAL_DIR)/common/os/linux/include/core/ \ -+ -I$(OSAL_DIR)/common/os/linux/include/modules/ \ -+ -I$(OSAL_DIR)/common/os/linux/include/modules/ddk/ \ -+ -I$(OSAL_DIR)/common/os/linux/include/modules/bufferMgt/ \ -+ -I$(OSAL_DIR)/common/os/linux/include/modules/ioMem/ \ -+ -I$(OSAL_DIR)/platforms/$(IXPLATFORM)/include/ \ -+ -I$(OSAL_DIR)/platforms/$(IXPLATFORM)/os/linux/include/ \ -+ -DENABLE_IOMEM -DENABLE_BUFFERMGT -DENABLE_DDK \ -+ -DUSE_IXP4XX_CRYPTO -+else -+IXP_CFLAGS = \ -+ -I$(ROOTDIR)/. \ -+ -I$(IX_XSCALE_SW)/src/include \ -+ -I$(OSAL_DIR)/ \ -+ -I$(OSAL_DIR)/os/linux/include/ \ -+ -I$(OSAL_DIR)/os/linux/include/modules/ \ -+ -I$(OSAL_DIR)/os/linux/include/modules/ioMem/ \ -+ -I$(OSAL_DIR)/os/linux/include/modules/bufferMgt/ \ -+ -I$(OSAL_DIR)/os/linux/include/core/ \ -+ -I$(OSAL_DIR)/os/linux/include/platforms/ \ -+ -I$(OSAL_DIR)/os/linux/include/platforms/ixp400/ \ -+ -I$(OSAL_DIR)/os/linux/include/platforms/ixp400/ixp425 \ -+ -I$(OSAL_DIR)/os/linux/include/platforms/ixp400/ixp465 \ -+ -I$(OSAL_DIR)/os/linux/include/core/ \ -+ -I$(OSAL_DIR)/include/ \ -+ -I$(OSAL_DIR)/include/modules/ \ -+ -I$(OSAL_DIR)/include/modules/bufferMgt/ \ -+ -I$(OSAL_DIR)/include/modules/ioMem/ \ -+ -I$(OSAL_DIR)/include/platforms/ \ -+ -I$(OSAL_DIR)/include/platforms/ixp400/ \ -+ -DUSE_IXP4XX_CRYPTO -+endif -+endif -+ifdef CONFIG_IXP400_LIB_1_4 -+IXP_CFLAGS = \ -+ -I$(ROOTDIR)/. \ -+ -I$(ROOTDIR)/modules/ixp425/ixp400-1.4/ixp400_xscale_sw/src/include \ -+ -I$(ROOTDIR)/modules/ixp425/ixp400-1.4/ixp400_xscale_sw/src/linux \ -+ -DUSE_IXP4XX_CRYPTO -+endif -+ifndef IXPDIR -+IXPDIR = ixp-version-is-not-supported -+endif -+ -+ifeq ($(CONFIG_CPU_IXP46X),y) -+IXP_CFLAGS += -D__ixp46X -+else -+ifeq ($(CONFIG_CPU_IXP43X),y) -+IXP_CFLAGS += -D__ixp43X -+else -+IXP_CFLAGS += -D__ixp42X -+endif -+endif -+ -+obj-$(CONFIG_OCF_IXP4XX) += ixp4xx.o -+ -+obj ?= . -+EXTRA_CFLAGS += $(IXP_CFLAGS) -I$(obj)/.. -I$(obj)/. -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/ixp4xx/ixp4xx.c linux-3.0.4/crypto/ocf/ixp4xx/ixp4xx.c ---- linux-3.0.4.orig/crypto/ocf/ixp4xx/ixp4xx.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/ixp4xx/ixp4xx.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,1339 @@ -+/* -+ * An OCF module that uses Intels IXP CryptACC API to do the crypto. -+ * This driver requires the IXP400 Access Library that is available -+ * from Intel in order to operate (or compile). -+ * -+ * Written by David McCullough -+ * Copyright (C) 2006-2011 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * ALTERNATIVELY, provided that this notice is retained in full, this product -+ * may be distributed under the terms of the GNU General Public License (GPL), -+ * in which case the provisions of the GPL apply INSTEAD OF those given above. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ */ -+ -+#include -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#ifndef IX_MBUF_PRIV -+#define IX_MBUF_PRIV(x) ((x)->priv) -+#endif -+ -+struct ixp_data; -+ -+struct ixp_q { -+ struct list_head ixp_q_list; -+ struct ixp_data *ixp_q_data; -+ struct cryptop *ixp_q_crp; -+ struct cryptodesc *ixp_q_ccrd; -+ struct cryptodesc *ixp_q_acrd; -+ IX_MBUF ixp_q_mbuf; -+ UINT8 *ixp_hash_dest; /* Location for hash in client buffer */ -+ UINT8 *ixp_hash_src; /* Location of hash in internal buffer */ -+ unsigned char ixp_q_iv_data[IX_CRYPTO_ACC_MAX_CIPHER_IV_LENGTH]; -+ unsigned char *ixp_q_iv; -+}; -+ -+struct ixp_data { -+ int ixp_registered; /* is the context registered */ -+ int ixp_crd_flags; /* detect direction changes */ -+ -+ int ixp_cipher_alg; -+ int ixp_auth_alg; -+ -+ UINT32 ixp_ctx_id; -+ UINT32 ixp_hash_key_id; /* used when hashing */ -+ IxCryptoAccCtx ixp_ctx; -+ IX_MBUF ixp_pri_mbuf; -+ IX_MBUF ixp_sec_mbuf; -+ -+ struct work_struct ixp_pending_work; -+ struct work_struct ixp_registration_work; -+ struct list_head ixp_q; /* unprocessed requests */ -+}; -+ -+#ifdef __ixp46X -+ -+#define MAX_IOP_SIZE 64 /* words */ -+#define MAX_OOP_SIZE 128 -+ -+#define MAX_PARAMS 3 -+ -+struct ixp_pkq { -+ struct list_head pkq_list; -+ struct cryptkop *pkq_krp; -+ -+ IxCryptoAccPkeEauInOperands pkq_op; -+ IxCryptoAccPkeEauOpResult pkq_result; -+ -+ UINT32 pkq_ibuf0[MAX_IOP_SIZE]; -+ UINT32 pkq_ibuf1[MAX_IOP_SIZE]; -+ UINT32 pkq_ibuf2[MAX_IOP_SIZE]; -+ UINT32 pkq_obuf[MAX_OOP_SIZE]; -+}; -+ -+static LIST_HEAD(ixp_pkq); /* current PK wait list */ -+static struct ixp_pkq *ixp_pk_cur; -+static spinlock_t ixp_pkq_lock; -+ -+#endif /* __ixp46X */ -+ -+static int ixp_blocked = 0; -+ -+static int32_t ixp_id = -1; -+static struct ixp_data **ixp_sessions = NULL; -+static u_int32_t ixp_sesnum = 0; -+ -+static int ixp_process(device_t, struct cryptop *, int); -+static int ixp_newsession(device_t, u_int32_t *, struct cryptoini *); -+static int ixp_freesession(device_t, u_int64_t); -+#ifdef __ixp46X -+static int ixp_kprocess(device_t, struct cryptkop *krp, int hint); -+#endif -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) -+static kmem_cache_t *qcache; -+#else -+static struct kmem_cache *qcache; -+#endif -+ -+#define debug ixp_debug -+static int ixp_debug = 0; -+module_param(ixp_debug, int, 0644); -+MODULE_PARM_DESC(ixp_debug, "Enable debug"); -+ -+static int ixp_init_crypto = 1; -+module_param(ixp_init_crypto, int, 0444); /* RO after load/boot */ -+MODULE_PARM_DESC(ixp_init_crypto, "Call ixCryptoAccInit (default is 1)"); -+ -+static void ixp_process_pending(void *arg); -+static void ixp_registration(void *arg); -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void ixp_process_pending_wq(struct work_struct *work); -+static void ixp_registration_wq(struct work_struct *work); -+#endif -+ -+/* -+ * dummy device structure -+ */ -+ -+static struct { -+ softc_device_decl sc_dev; -+} ixpdev; -+ -+static device_method_t ixp_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, ixp_newsession), -+ DEVMETHOD(cryptodev_freesession,ixp_freesession), -+ DEVMETHOD(cryptodev_process, ixp_process), -+#ifdef __ixp46X -+ DEVMETHOD(cryptodev_kprocess, ixp_kprocess), -+#endif -+}; -+ -+/* -+ * Generate a new software session. -+ */ -+static int -+ixp_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) -+{ -+ struct ixp_data *ixp; -+ u_int32_t i; -+#define AUTH_LEN(cri, def) \ -+ (cri->cri_mlen ? cri->cri_mlen : (def)) -+ -+ dprintk("%s():alg %d\n", __FUNCTION__,cri->cri_alg); -+ if (sid == NULL || cri == NULL) { -+ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ if (ixp_sessions) { -+ for (i = 1; i < ixp_sesnum; i++) -+ if (ixp_sessions[i] == NULL) -+ break; -+ } else -+ i = 1; /* NB: to silence compiler warning */ -+ -+ if (ixp_sessions == NULL || i == ixp_sesnum) { -+ struct ixp_data **ixpd; -+ -+ if (ixp_sessions == NULL) { -+ i = 1; /* We leave ixp_sessions[0] empty */ -+ ixp_sesnum = CRYPTO_SW_SESSIONS; -+ } else -+ ixp_sesnum *= 2; -+ -+ ixpd = kmalloc(ixp_sesnum * sizeof(struct ixp_data *), SLAB_ATOMIC); -+ if (ixpd == NULL) { -+ /* Reset session number */ -+ if (ixp_sesnum == CRYPTO_SW_SESSIONS) -+ ixp_sesnum = 0; -+ else -+ ixp_sesnum /= 2; -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memset(ixpd, 0, ixp_sesnum * sizeof(struct ixp_data *)); -+ -+ /* Copy existing sessions */ -+ if (ixp_sessions) { -+ memcpy(ixpd, ixp_sessions, -+ (ixp_sesnum / 2) * sizeof(struct ixp_data *)); -+ kfree(ixp_sessions); -+ } -+ -+ ixp_sessions = ixpd; -+ } -+ -+ ixp_sessions[i] = (struct ixp_data *) kmalloc(sizeof(struct ixp_data), -+ SLAB_ATOMIC); -+ if (ixp_sessions[i] == NULL) { -+ ixp_freesession(NULL, i); -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ -+ *sid = i; -+ -+ ixp = ixp_sessions[i]; -+ memset(ixp, 0, sizeof(*ixp)); -+ -+ ixp->ixp_cipher_alg = -1; -+ ixp->ixp_auth_alg = -1; -+ ixp->ixp_ctx_id = -1; -+ INIT_LIST_HEAD(&ixp->ixp_q); -+ -+ ixp->ixp_ctx.useDifferentSrcAndDestMbufs = 0; -+ -+ while (cri) { -+ switch (cri->cri_alg) { -+ case CRYPTO_DES_CBC: -+ ixp->ixp_cipher_alg = cri->cri_alg; -+ ixp->ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_DES; -+ ixp->ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; -+ ixp->ixp_ctx.cipherCtx.cipherKeyLen = (cri->cri_klen + 7) / 8; -+ ixp->ixp_ctx.cipherCtx.cipherBlockLen = IX_CRYPTO_ACC_DES_BLOCK_64; -+ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen = -+ IX_CRYPTO_ACC_DES_IV_64; -+ memcpy(ixp->ixp_ctx.cipherCtx.key.cipherKey, -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ break; -+ -+ case CRYPTO_3DES_CBC: -+ ixp->ixp_cipher_alg = cri->cri_alg; -+ ixp->ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_3DES; -+ ixp->ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; -+ ixp->ixp_ctx.cipherCtx.cipherKeyLen = (cri->cri_klen + 7) / 8; -+ ixp->ixp_ctx.cipherCtx.cipherBlockLen = IX_CRYPTO_ACC_DES_BLOCK_64; -+ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen = -+ IX_CRYPTO_ACC_DES_IV_64; -+ memcpy(ixp->ixp_ctx.cipherCtx.key.cipherKey, -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ break; -+ -+ case CRYPTO_RIJNDAEL128_CBC: -+ ixp->ixp_cipher_alg = cri->cri_alg; -+ ixp->ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_AES; -+ ixp->ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; -+ ixp->ixp_ctx.cipherCtx.cipherKeyLen = (cri->cri_klen + 7) / 8; -+ ixp->ixp_ctx.cipherCtx.cipherBlockLen = 16; -+ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen = 16; -+ memcpy(ixp->ixp_ctx.cipherCtx.key.cipherKey, -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ break; -+ -+ case CRYPTO_MD5: -+ case CRYPTO_MD5_HMAC: -+ ixp->ixp_auth_alg = cri->cri_alg; -+ ixp->ixp_ctx.authCtx.authAlgo = IX_CRYPTO_ACC_AUTH_MD5; -+ ixp->ixp_ctx.authCtx.authDigestLen = AUTH_LEN(cri, MD5_HASH_LEN); -+ ixp->ixp_ctx.authCtx.aadLen = 0; -+ /* Only MD5_HMAC needs a key */ -+ if (cri->cri_alg == CRYPTO_MD5_HMAC) { -+ ixp->ixp_ctx.authCtx.authKeyLen = (cri->cri_klen + 7) / 8; -+ if (ixp->ixp_ctx.authCtx.authKeyLen > -+ sizeof(ixp->ixp_ctx.authCtx.key.authKey)) { -+ printk( -+ "ixp4xx: Invalid key length for MD5_HMAC - %d bits\n", -+ cri->cri_klen); -+ ixp_freesession(NULL, i); -+ return EINVAL; -+ } -+ memcpy(ixp->ixp_ctx.authCtx.key.authKey, -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ } -+ break; -+ -+ case CRYPTO_SHA1: -+ case CRYPTO_SHA1_HMAC: -+ ixp->ixp_auth_alg = cri->cri_alg; -+ ixp->ixp_ctx.authCtx.authAlgo = IX_CRYPTO_ACC_AUTH_SHA1; -+ ixp->ixp_ctx.authCtx.authDigestLen = AUTH_LEN(cri, SHA1_HASH_LEN); -+ ixp->ixp_ctx.authCtx.aadLen = 0; -+ /* Only SHA1_HMAC needs a key */ -+ if (cri->cri_alg == CRYPTO_SHA1_HMAC) { -+ ixp->ixp_ctx.authCtx.authKeyLen = (cri->cri_klen + 7) / 8; -+ if (ixp->ixp_ctx.authCtx.authKeyLen > -+ sizeof(ixp->ixp_ctx.authCtx.key.authKey)) { -+ printk( -+ "ixp4xx: Invalid key length for SHA1_HMAC - %d bits\n", -+ cri->cri_klen); -+ ixp_freesession(NULL, i); -+ return EINVAL; -+ } -+ memcpy(ixp->ixp_ctx.authCtx.key.authKey, -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ } -+ break; -+ -+ default: -+ printk("ixp: unknown algo 0x%x\n", cri->cri_alg); -+ ixp_freesession(NULL, i); -+ return EINVAL; -+ } -+ cri = cri->cri_next; -+ } -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ INIT_WORK(&ixp->ixp_pending_work, ixp_process_pending_wq); -+ INIT_WORK(&ixp->ixp_registration_work, ixp_registration_wq); -+#else -+ INIT_WORK(&ixp->ixp_pending_work, ixp_process_pending, ixp); -+ INIT_WORK(&ixp->ixp_registration_work, ixp_registration, ixp); -+#endif -+ -+ return 0; -+} -+ -+ -+/* -+ * Free a session. -+ */ -+static int -+ixp_freesession(device_t dev, u_int64_t tid) -+{ -+ u_int32_t sid = CRYPTO_SESID2LID(tid); -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid > ixp_sesnum || ixp_sessions == NULL || -+ ixp_sessions[sid] == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ /* Silently accept and return */ -+ if (sid == 0) -+ return 0; -+ -+ if (ixp_sessions[sid]) { -+ if (ixp_sessions[sid]->ixp_ctx_id != -1) { -+ ixCryptoAccCtxUnregister(ixp_sessions[sid]->ixp_ctx_id); -+ ixp_sessions[sid]->ixp_ctx_id = -1; -+ } -+ kfree(ixp_sessions[sid]); -+ } -+ ixp_sessions[sid] = NULL; -+ if (ixp_blocked) { -+ ixp_blocked = 0; -+ crypto_unblock(ixp_id, CRYPTO_SYMQ); -+ } -+ return 0; -+} -+ -+ -+/* -+ * callback for when hash processing is complete -+ */ -+ -+static void -+ixp_hash_perform_cb( -+ UINT32 hash_key_id, -+ IX_MBUF *bufp, -+ IxCryptoAccStatus status) -+{ -+ struct ixp_q *q; -+ -+ dprintk("%s(%u, %p, 0x%x)\n", __FUNCTION__, hash_key_id, bufp, status); -+ -+ if (bufp == NULL) { -+ printk("ixp: NULL buf in %s\n", __FUNCTION__); -+ return; -+ } -+ -+ q = IX_MBUF_PRIV(bufp); -+ if (q == NULL) { -+ printk("ixp: NULL priv in %s\n", __FUNCTION__); -+ return; -+ } -+ -+ if (status == IX_CRYPTO_ACC_STATUS_SUCCESS) { -+ /* On success, need to copy hash back into original client buffer */ -+ memcpy(q->ixp_hash_dest, q->ixp_hash_src, -+ (q->ixp_q_data->ixp_auth_alg == CRYPTO_SHA1) ? -+ SHA1_HASH_LEN : MD5_HASH_LEN); -+ } -+ else { -+ printk("ixp: hash perform failed status=%d\n", status); -+ q->ixp_q_crp->crp_etype = EINVAL; -+ } -+ -+ /* Free internal buffer used for hashing */ -+ kfree(IX_MBUF_MDATA(&q->ixp_q_mbuf)); -+ -+ crypto_done(q->ixp_q_crp); -+ kmem_cache_free(qcache, q); -+} -+ -+/* -+ * setup a request and perform it -+ */ -+static void -+ixp_q_process(struct ixp_q *q) -+{ -+ IxCryptoAccStatus status; -+ struct ixp_data *ixp = q->ixp_q_data; -+ int auth_off = 0; -+ int auth_len = 0; -+ int crypt_off = 0; -+ int crypt_len = 0; -+ int icv_off = 0; -+ char *crypt_func; -+ -+ dprintk("%s(%p)\n", __FUNCTION__, q); -+ -+ if (q->ixp_q_ccrd) { -+ if (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT) { -+ if (q->ixp_q_ccrd->crd_flags & CRD_F_IV_EXPLICIT) { -+ q->ixp_q_iv = q->ixp_q_ccrd->crd_iv; -+ } else { -+ q->ixp_q_iv = q->ixp_q_iv_data; -+ read_random(q->ixp_q_iv, ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen); -+ } -+ if ((q->ixp_q_ccrd->crd_flags & CRD_F_IV_PRESENT) == 0) -+ crypto_copyback(q->ixp_q_crp->crp_flags, q->ixp_q_crp->crp_buf, -+ q->ixp_q_ccrd->crd_inject, -+ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen, -+ (caddr_t) q->ixp_q_iv); -+ } else { -+ if (q->ixp_q_ccrd->crd_flags & CRD_F_IV_EXPLICIT) -+ q->ixp_q_iv = q->ixp_q_ccrd->crd_iv; -+ else { -+ q->ixp_q_iv = q->ixp_q_iv_data; -+ crypto_copydata(q->ixp_q_crp->crp_flags, q->ixp_q_crp->crp_buf, -+ q->ixp_q_ccrd->crd_inject, -+ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen, -+ (caddr_t) q->ixp_q_iv); -+ } -+ } -+ -+ if (q->ixp_q_acrd) { -+ auth_off = q->ixp_q_acrd->crd_skip; -+ auth_len = q->ixp_q_acrd->crd_len; -+ icv_off = q->ixp_q_acrd->crd_inject; -+ } -+ -+ crypt_off = q->ixp_q_ccrd->crd_skip; -+ crypt_len = q->ixp_q_ccrd->crd_len; -+ } else { /* if (q->ixp_q_acrd) */ -+ auth_off = q->ixp_q_acrd->crd_skip; -+ auth_len = q->ixp_q_acrd->crd_len; -+ icv_off = q->ixp_q_acrd->crd_inject; -+ } -+ -+ if (q->ixp_q_crp->crp_flags & CRYPTO_F_SKBUF) { -+ struct sk_buff *skb = (struct sk_buff *) q->ixp_q_crp->crp_buf; -+ if (skb_shinfo(skb)->nr_frags) { -+ /* -+ * DAVIDM fix this limitation one day by using -+ * a buffer pool and chaining, it is not currently -+ * needed for current user/kernel space acceleration -+ */ -+ printk("ixp: Cannot handle fragmented skb's yet !\n"); -+ q->ixp_q_crp->crp_etype = ENOENT; -+ goto done; -+ } -+ IX_MBUF_MLEN(&q->ixp_q_mbuf) = -+ IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = skb->len; -+ IX_MBUF_MDATA(&q->ixp_q_mbuf) = skb->data; -+ } else if (q->ixp_q_crp->crp_flags & CRYPTO_F_IOV) { -+ struct uio *uiop = (struct uio *) q->ixp_q_crp->crp_buf; -+ if (uiop->uio_iovcnt != 1) { -+ /* -+ * DAVIDM fix this limitation one day by using -+ * a buffer pool and chaining, it is not currently -+ * needed for current user/kernel space acceleration -+ */ -+ printk("ixp: Cannot handle more than 1 iovec yet !\n"); -+ q->ixp_q_crp->crp_etype = ENOENT; -+ goto done; -+ } -+ IX_MBUF_MLEN(&q->ixp_q_mbuf) = -+ IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = uiop->uio_iov[0].iov_len; -+ IX_MBUF_MDATA(&q->ixp_q_mbuf) = uiop->uio_iov[0].iov_base; -+ } else /* contig buffer */ { -+ IX_MBUF_MLEN(&q->ixp_q_mbuf) = -+ IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = q->ixp_q_crp->crp_ilen; -+ IX_MBUF_MDATA(&q->ixp_q_mbuf) = q->ixp_q_crp->crp_buf; -+ } -+ -+ IX_MBUF_PRIV(&q->ixp_q_mbuf) = q; -+ -+ if (ixp->ixp_auth_alg == CRYPTO_SHA1 || ixp->ixp_auth_alg == CRYPTO_MD5) { -+ /* -+ * For SHA1 and MD5 hash, need to create an internal buffer that is big -+ * enough to hold the original data + the appropriate padding for the -+ * hash algorithm. -+ */ -+ UINT8 *tbuf = NULL; -+ -+ IX_MBUF_MLEN(&q->ixp_q_mbuf) = IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = -+ ((IX_MBUF_MLEN(&q->ixp_q_mbuf) * 8) + 72 + 511) / 8; -+ tbuf = kmalloc(IX_MBUF_MLEN(&q->ixp_q_mbuf), SLAB_ATOMIC); -+ -+ if (IX_MBUF_MDATA(&q->ixp_q_mbuf) == NULL) { -+ printk("ixp: kmalloc(%u, SLAB_ATOMIC) failed\n", -+ IX_MBUF_MLEN(&q->ixp_q_mbuf)); -+ q->ixp_q_crp->crp_etype = ENOMEM; -+ goto done; -+ } -+ memcpy(tbuf, &(IX_MBUF_MDATA(&q->ixp_q_mbuf))[auth_off], auth_len); -+ -+ /* Set location in client buffer to copy hash into */ -+ q->ixp_hash_dest = -+ &(IX_MBUF_MDATA(&q->ixp_q_mbuf))[auth_off + auth_len]; -+ -+ IX_MBUF_MDATA(&q->ixp_q_mbuf) = tbuf; -+ -+ /* Set location in internal buffer for where hash starts */ -+ q->ixp_hash_src = &(IX_MBUF_MDATA(&q->ixp_q_mbuf))[auth_len]; -+ -+ crypt_func = "ixCryptoAccHashPerform"; -+ status = ixCryptoAccHashPerform(ixp->ixp_ctx.authCtx.authAlgo, -+ &q->ixp_q_mbuf, ixp_hash_perform_cb, 0, auth_len, auth_len, -+ &ixp->ixp_hash_key_id); -+ } -+ else { -+ crypt_func = "ixCryptoAccAuthCryptPerform"; -+ status = ixCryptoAccAuthCryptPerform(ixp->ixp_ctx_id, &q->ixp_q_mbuf, -+ NULL, auth_off, auth_len, crypt_off, crypt_len, icv_off, -+ q->ixp_q_iv); -+ } -+ -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) -+ return; -+ -+ if (IX_CRYPTO_ACC_STATUS_QUEUE_FULL == status) { -+ q->ixp_q_crp->crp_etype = ENOMEM; -+ goto done; -+ } -+ -+ printk("ixp: %s failed %u\n", crypt_func, status); -+ q->ixp_q_crp->crp_etype = EINVAL; -+ -+done: -+ crypto_done(q->ixp_q_crp); -+ kmem_cache_free(qcache, q); -+} -+ -+ -+/* -+ * because we cannot process the Q from the Register callback -+ * we do it here on a task Q. -+ */ -+ -+static void -+ixp_process_pending(void *arg) -+{ -+ struct ixp_data *ixp = arg; -+ struct ixp_q *q = NULL; -+ -+ dprintk("%s(%p)\n", __FUNCTION__, arg); -+ -+ if (!ixp) -+ return; -+ -+ while (!list_empty(&ixp->ixp_q)) { -+ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); -+ list_del(&q->ixp_q_list); -+ ixp_q_process(q); -+ } -+} -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void -+ixp_process_pending_wq(struct work_struct *work) -+{ -+ struct ixp_data *ixp = container_of(work, struct ixp_data, ixp_pending_work); -+ ixp_process_pending(ixp); -+} -+#endif -+ -+/* -+ * callback for when context registration is complete -+ */ -+ -+static void -+ixp_register_cb(UINT32 ctx_id, IX_MBUF *bufp, IxCryptoAccStatus status) -+{ -+ int i; -+ struct ixp_data *ixp; -+ struct ixp_q *q; -+ -+ dprintk("%s(%d, %p, %d)\n", __FUNCTION__, ctx_id, bufp, status); -+ -+ /* -+ * free any buffer passed in to this routine -+ */ -+ if (bufp) { -+ IX_MBUF_MLEN(bufp) = IX_MBUF_PKT_LEN(bufp) = 0; -+ kfree(IX_MBUF_MDATA(bufp)); -+ IX_MBUF_MDATA(bufp) = NULL; -+ } -+ -+ for (i = 0; i < ixp_sesnum; i++) { -+ ixp = ixp_sessions[i]; -+ if (ixp && ixp->ixp_ctx_id == ctx_id) -+ break; -+ } -+ if (i >= ixp_sesnum) { -+ printk("ixp: invalid context id %d\n", ctx_id); -+ return; -+ } -+ -+ if (IX_CRYPTO_ACC_STATUS_WAIT == status) { -+ /* this is normal to free the first of two buffers */ -+ dprintk("ixp: register not finished yet.\n"); -+ return; -+ } -+ -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS != status) { -+ printk("ixp: register failed 0x%x\n", status); -+ while (!list_empty(&ixp->ixp_q)) { -+ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); -+ list_del(&q->ixp_q_list); -+ q->ixp_q_crp->crp_etype = EINVAL; -+ crypto_done(q->ixp_q_crp); -+ kmem_cache_free(qcache, q); -+ } -+ return; -+ } -+ -+ /* -+ * we are now registered, we cannot start processing the Q here -+ * or we get strange errors with AES (DES/3DES seem to be ok). -+ */ -+ ixp->ixp_registered = 1; -+ schedule_work(&ixp->ixp_pending_work); -+} -+ -+ -+/* -+ * callback for when data processing is complete -+ */ -+ -+static void -+ixp_perform_cb( -+ UINT32 ctx_id, -+ IX_MBUF *sbufp, -+ IX_MBUF *dbufp, -+ IxCryptoAccStatus status) -+{ -+ struct ixp_q *q; -+ -+ dprintk("%s(%d, %p, %p, 0x%x)\n", __FUNCTION__, ctx_id, sbufp, -+ dbufp, status); -+ -+ if (sbufp == NULL) { -+ printk("ixp: NULL sbuf in ixp_perform_cb\n"); -+ return; -+ } -+ -+ q = IX_MBUF_PRIV(sbufp); -+ if (q == NULL) { -+ printk("ixp: NULL priv in ixp_perform_cb\n"); -+ return; -+ } -+ -+ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { -+ printk("ixp: perform failed status=%d\n", status); -+ q->ixp_q_crp->crp_etype = EINVAL; -+ } -+ -+ crypto_done(q->ixp_q_crp); -+ kmem_cache_free(qcache, q); -+} -+ -+ -+/* -+ * registration is not callable at IRQ time, so we defer -+ * to a task queue, this routines completes the registration for us -+ * when the task queue runs -+ * -+ * Unfortunately this means we cannot tell OCF that the driver is blocked, -+ * we do that on the next request. -+ */ -+ -+static void -+ixp_registration(void *arg) -+{ -+ struct ixp_data *ixp = arg; -+ struct ixp_q *q = NULL; -+ IX_MBUF *pri = NULL, *sec = NULL; -+ int status = IX_CRYPTO_ACC_STATUS_SUCCESS; -+ -+ if (!ixp) { -+ printk("ixp: ixp_registration with no arg\n"); -+ return; -+ } -+ -+ if (ixp->ixp_ctx_id != -1) { -+ ixCryptoAccCtxUnregister(ixp->ixp_ctx_id); -+ ixp->ixp_ctx_id = -1; -+ } -+ -+ if (list_empty(&ixp->ixp_q)) { -+ printk("ixp: ixp_registration with no Q\n"); -+ return; -+ } -+ -+ /* -+ * setup the primary and secondary buffers -+ */ -+ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); -+ if (q->ixp_q_acrd) { -+ pri = &ixp->ixp_pri_mbuf; -+ sec = &ixp->ixp_sec_mbuf; -+ IX_MBUF_MLEN(pri) = IX_MBUF_PKT_LEN(pri) = 128; -+ IX_MBUF_MDATA(pri) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); -+ IX_MBUF_MLEN(sec) = IX_MBUF_PKT_LEN(sec) = 128; -+ IX_MBUF_MDATA(sec) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); -+ } -+ -+ /* Only need to register if a crypt op or HMAC op */ -+ if (!(ixp->ixp_auth_alg == CRYPTO_SHA1 || -+ ixp->ixp_auth_alg == CRYPTO_MD5)) { -+ status = ixCryptoAccCtxRegister( -+ &ixp->ixp_ctx, -+ pri, sec, -+ ixp_register_cb, -+ ixp_perform_cb, -+ &ixp->ixp_ctx_id); -+ } -+ else { -+ /* Otherwise we start processing pending q */ -+ schedule_work(&ixp->ixp_pending_work); -+ } -+ -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) -+ return; -+ -+ if (IX_CRYPTO_ACC_STATUS_EXCEED_MAX_TUNNELS == status) { -+ printk("ixp: ixCryptoAccCtxRegister failed (out of tunnels)\n"); -+ ixp_blocked = 1; -+ /* perhaps we should return EGAIN on queued ops ? */ -+ return; -+ } -+ -+ printk("ixp: ixCryptoAccCtxRegister failed %d\n", status); -+ ixp->ixp_ctx_id = -1; -+ -+ /* -+ * everything waiting is toasted -+ */ -+ while (!list_empty(&ixp->ixp_q)) { -+ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); -+ list_del(&q->ixp_q_list); -+ q->ixp_q_crp->crp_etype = ENOENT; -+ crypto_done(q->ixp_q_crp); -+ kmem_cache_free(qcache, q); -+ } -+} -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void -+ixp_registration_wq(struct work_struct *work) -+{ -+ struct ixp_data *ixp = container_of(work, struct ixp_data, -+ ixp_registration_work); -+ ixp_registration(ixp); -+} -+#endif -+ -+/* -+ * Process a request. -+ */ -+static int -+ixp_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ struct ixp_data *ixp; -+ unsigned int lid; -+ struct ixp_q *q = NULL; -+ int status; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ /* Sanity check */ -+ if (crp == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ crp->crp_etype = 0; -+ -+ if (ixp_blocked) -+ return ERESTART; -+ -+ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ /* -+ * find the session we are using -+ */ -+ -+ lid = crp->crp_sid & 0xffffffff; -+ if (lid >= ixp_sesnum || lid == 0 || ixp_sessions == NULL || -+ ixp_sessions[lid] == NULL) { -+ crp->crp_etype = ENOENT; -+ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); -+ goto done; -+ } -+ ixp = ixp_sessions[lid]; -+ -+ /* -+ * setup a new request ready for queuing -+ */ -+ q = kmem_cache_alloc(qcache, SLAB_ATOMIC); -+ if (q == NULL) { -+ dprintk("%s,%d: ENOMEM\n", __FILE__, __LINE__); -+ crp->crp_etype = ENOMEM; -+ goto done; -+ } -+ /* -+ * save some cycles by only zeroing the important bits -+ */ -+ memset(&q->ixp_q_mbuf, 0, sizeof(q->ixp_q_mbuf)); -+ q->ixp_q_ccrd = NULL; -+ q->ixp_q_acrd = NULL; -+ q->ixp_q_crp = crp; -+ q->ixp_q_data = ixp; -+ -+ /* -+ * point the cipher and auth descriptors appropriately -+ * check that we have something to do -+ */ -+ if (crp->crp_desc->crd_alg == ixp->ixp_cipher_alg) -+ q->ixp_q_ccrd = crp->crp_desc; -+ else if (crp->crp_desc->crd_alg == ixp->ixp_auth_alg) -+ q->ixp_q_acrd = crp->crp_desc; -+ else { -+ crp->crp_etype = ENOENT; -+ dprintk("%s,%d: bad desc match: ENOENT\n", __FILE__, __LINE__); -+ goto done; -+ } -+ if (crp->crp_desc->crd_next) { -+ if (crp->crp_desc->crd_next->crd_alg == ixp->ixp_cipher_alg) -+ q->ixp_q_ccrd = crp->crp_desc->crd_next; -+ else if (crp->crp_desc->crd_next->crd_alg == ixp->ixp_auth_alg) -+ q->ixp_q_acrd = crp->crp_desc->crd_next; -+ else { -+ crp->crp_etype = ENOENT; -+ dprintk("%s,%d: bad desc match: ENOENT\n", __FILE__, __LINE__); -+ goto done; -+ } -+ } -+ -+ /* -+ * If there is a direction change for this context then we mark it as -+ * unregistered and re-register is for the new direction. This is not -+ * a very expensive operation and currently only tends to happen when -+ * user-space application are doing benchmarks -+ * -+ * DM - we should be checking for pending requests before unregistering. -+ */ -+ if (q->ixp_q_ccrd && ixp->ixp_registered && -+ ixp->ixp_crd_flags != (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT)) { -+ dprintk("%s - detected direction change on session\n", __FUNCTION__); -+ ixp->ixp_registered = 0; -+ } -+ -+ /* -+ * if we are registered, call straight into the perform code -+ */ -+ if (ixp->ixp_registered) { -+ ixp_q_process(q); -+ return 0; -+ } -+ -+ /* -+ * the only part of the context not set in newsession is the direction -+ * dependent parts -+ */ -+ if (q->ixp_q_ccrd) { -+ ixp->ixp_crd_flags = (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT); -+ if (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT) { -+ ixp->ixp_ctx.operation = q->ixp_q_acrd ? -+ IX_CRYPTO_ACC_OP_ENCRYPT_AUTH : IX_CRYPTO_ACC_OP_ENCRYPT; -+ } else { -+ ixp->ixp_ctx.operation = q->ixp_q_acrd ? -+ IX_CRYPTO_ACC_OP_AUTH_DECRYPT : IX_CRYPTO_ACC_OP_DECRYPT; -+ } -+ } else { -+ /* q->ixp_q_acrd must be set if we are here */ -+ ixp->ixp_ctx.operation = IX_CRYPTO_ACC_OP_AUTH_CALC; -+ } -+ -+ status = list_empty(&ixp->ixp_q); -+ list_add_tail(&q->ixp_q_list, &ixp->ixp_q); -+ if (status) -+ schedule_work(&ixp->ixp_registration_work); -+ return 0; -+ -+done: -+ if (q) -+ kmem_cache_free(qcache, q); -+ crypto_done(crp); -+ return 0; -+} -+ -+ -+#ifdef __ixp46X -+/* -+ * key processing support for the ixp465 -+ */ -+ -+ -+/* -+ * copy a BN (LE) into a buffer (BE) an fill out the op appropriately -+ * assume zeroed and only copy bits that are significant -+ */ -+ -+static int -+ixp_copy_ibuf(struct crparam *p, IxCryptoAccPkeEauOperand *op, UINT32 *buf) -+{ -+ unsigned char *src = (unsigned char *) p->crp_p; -+ unsigned char *dst; -+ int len, bits = p->crp_nbits; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (bits > MAX_IOP_SIZE * sizeof(UINT32) * 8) { -+ dprintk("%s - ibuf too big (%d > %d)\n", __FUNCTION__, -+ bits, MAX_IOP_SIZE * sizeof(UINT32) * 8); -+ return -1; -+ } -+ -+ len = (bits + 31) / 32; /* the number UINT32's needed */ -+ -+ dst = (unsigned char *) &buf[len]; -+ dst--; -+ -+ while (bits > 0) { -+ *dst-- = *src++; -+ bits -= 8; -+ } -+ -+#if 0 /* no need to zero remaining bits as it is done during request alloc */ -+ while (dst > (unsigned char *) buf) -+ *dst-- = '\0'; -+#endif -+ -+ op->pData = buf; -+ op->dataLen = len; -+ return 0; -+} -+ -+/* -+ * copy out the result, be as forgiving as we can about small output buffers -+ */ -+ -+static int -+ixp_copy_obuf(struct crparam *p, IxCryptoAccPkeEauOpResult *op, UINT32 *buf) -+{ -+ unsigned char *dst = (unsigned char *) p->crp_p; -+ unsigned char *src = (unsigned char *) buf; -+ int len, z, bits = p->crp_nbits; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ len = op->dataLen * sizeof(UINT32); -+ -+ /* skip leading zeroes to be small buffer friendly */ -+ z = 0; -+ while (z < len && src[z] == '\0') -+ z++; -+ -+ src += len; -+ src--; -+ len -= z; -+ -+ while (len > 0 && bits > 0) { -+ *dst++ = *src--; -+ len--; -+ bits -= 8; -+ } -+ -+ while (bits > 0) { -+ *dst++ = '\0'; -+ bits -= 8; -+ } -+ -+ if (len > 0) { -+ dprintk("%s - obuf is %d (z=%d, ob=%d) bytes too small\n", -+ __FUNCTION__, len, z, p->crp_nbits / 8); -+ return -1; -+ } -+ -+ return 0; -+} -+ -+ -+/* -+ * the parameter offsets for exp_mod -+ */ -+ -+#define IXP_PARAM_BASE 0 -+#define IXP_PARAM_EXP 1 -+#define IXP_PARAM_MOD 2 -+#define IXP_PARAM_RES 3 -+ -+/* -+ * key processing complete callback, is also used to start processing -+ * by passing a NULL for pResult -+ */ -+ -+static void -+ixp_kperform_cb( -+ IxCryptoAccPkeEauOperation operation, -+ IxCryptoAccPkeEauOpResult *pResult, -+ BOOL carryOrBorrow, -+ IxCryptoAccStatus status) -+{ -+ struct ixp_pkq *q, *tmp; -+ unsigned long flags; -+ -+ dprintk("%s(0x%x, %p, %d, 0x%x)\n", __FUNCTION__, operation, pResult, -+ carryOrBorrow, status); -+ -+ /* handle a completed request */ -+ if (pResult) { -+ if (ixp_pk_cur && &ixp_pk_cur->pkq_result == pResult) { -+ q = ixp_pk_cur; -+ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { -+ dprintk("%s() - op failed 0x%x\n", __FUNCTION__, status); -+ q->pkq_krp->krp_status = ERANGE; /* could do better */ -+ } else { -+ /* copy out the result */ -+ if (ixp_copy_obuf(&q->pkq_krp->krp_param[IXP_PARAM_RES], -+ &q->pkq_result, q->pkq_obuf)) -+ q->pkq_krp->krp_status = ERANGE; -+ } -+ crypto_kdone(q->pkq_krp); -+ kfree(q); -+ ixp_pk_cur = NULL; -+ } else -+ printk("%s - callback with invalid result pointer\n", __FUNCTION__); -+ } -+ -+ spin_lock_irqsave(&ixp_pkq_lock, flags); -+ if (ixp_pk_cur || list_empty(&ixp_pkq)) { -+ spin_unlock_irqrestore(&ixp_pkq_lock, flags); -+ return; -+ } -+ -+ list_for_each_entry_safe(q, tmp, &ixp_pkq, pkq_list) { -+ -+ list_del(&q->pkq_list); -+ ixp_pk_cur = q; -+ -+ spin_unlock_irqrestore(&ixp_pkq_lock, flags); -+ -+ status = ixCryptoAccPkeEauPerform( -+ IX_CRYPTO_ACC_OP_EAU_MOD_EXP, -+ &q->pkq_op, -+ ixp_kperform_cb, -+ &q->pkq_result); -+ -+ if (status == IX_CRYPTO_ACC_STATUS_SUCCESS) { -+ dprintk("%s() - ixCryptoAccPkeEauPerform SUCCESS\n", __FUNCTION__); -+ return; /* callback will return here for callback */ -+ } else if (status == IX_CRYPTO_ACC_STATUS_RETRY) { -+ printk("%s() - ixCryptoAccPkeEauPerform RETRY\n", __FUNCTION__); -+ } else { -+ printk("%s() - ixCryptoAccPkeEauPerform failed %d\n", -+ __FUNCTION__, status); -+ } -+ q->pkq_krp->krp_status = ERANGE; /* could do better */ -+ crypto_kdone(q->pkq_krp); -+ kfree(q); -+ spin_lock_irqsave(&ixp_pkq_lock, flags); -+ } -+ spin_unlock_irqrestore(&ixp_pkq_lock, flags); -+} -+ -+ -+static int -+ixp_kprocess(device_t dev, struct cryptkop *krp, int hint) -+{ -+ struct ixp_pkq *q; -+ int rc = 0; -+ unsigned long flags; -+ -+ dprintk("%s l1=%d l2=%d l3=%d l4=%d\n", __FUNCTION__, -+ krp->krp_param[IXP_PARAM_BASE].crp_nbits, -+ krp->krp_param[IXP_PARAM_EXP].crp_nbits, -+ krp->krp_param[IXP_PARAM_MOD].crp_nbits, -+ krp->krp_param[IXP_PARAM_RES].crp_nbits); -+ -+ -+ if (krp->krp_op != CRK_MOD_EXP) { -+ krp->krp_status = EOPNOTSUPP; -+ goto err; -+ } -+ -+ q = (struct ixp_pkq *) kmalloc(sizeof(*q), GFP_KERNEL); -+ if (q == NULL) { -+ krp->krp_status = ENOMEM; -+ goto err; -+ } -+ -+ /* -+ * The PKE engine does not appear to zero the output buffer -+ * appropriately, so we need to do it all here. -+ */ -+ memset(q, 0, sizeof(*q)); -+ -+ q->pkq_krp = krp; -+ INIT_LIST_HEAD(&q->pkq_list); -+ -+ if (ixp_copy_ibuf(&krp->krp_param[IXP_PARAM_BASE], &q->pkq_op.modExpOpr.M, -+ q->pkq_ibuf0)) -+ rc = 1; -+ if (!rc && ixp_copy_ibuf(&krp->krp_param[IXP_PARAM_EXP], -+ &q->pkq_op.modExpOpr.e, q->pkq_ibuf1)) -+ rc = 2; -+ if (!rc && ixp_copy_ibuf(&krp->krp_param[IXP_PARAM_MOD], -+ &q->pkq_op.modExpOpr.N, q->pkq_ibuf2)) -+ rc = 3; -+ -+ if (rc) { -+ kfree(q); -+ krp->krp_status = ERANGE; -+ goto err; -+ } -+ -+ q->pkq_result.pData = q->pkq_obuf; -+ q->pkq_result.dataLen = -+ (krp->krp_param[IXP_PARAM_RES].crp_nbits + 31) / 32; -+ -+ spin_lock_irqsave(&ixp_pkq_lock, flags); -+ list_add_tail(&q->pkq_list, &ixp_pkq); -+ spin_unlock_irqrestore(&ixp_pkq_lock, flags); -+ -+ if (!ixp_pk_cur) -+ ixp_kperform_cb(0, NULL, 0, 0); -+ return (0); -+ -+err: -+ crypto_kdone(krp); -+ return (0); -+} -+ -+ -+ -+#ifdef CONFIG_OCF_RANDOMHARVEST -+/* -+ * We run the random number generator output through SHA so that it -+ * is FIPS compliant. -+ */ -+ -+static volatile int sha_done = 0; -+static unsigned char sha_digest[20]; -+ -+static void -+ixp_hash_cb(UINT8 *digest, IxCryptoAccStatus status) -+{ -+ dprintk("%s(%p, %d)\n", __FUNCTION__, digest, status); -+ if (sha_digest != digest) -+ printk("digest error\n"); -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) -+ sha_done = 1; -+ else -+ sha_done = -status; -+} -+ -+static int -+ixp_read_random(void *arg, u_int32_t *buf, int maxwords) -+{ -+ IxCryptoAccStatus status; -+ int i, n, rc; -+ -+ dprintk("%s(%p, %d)\n", __FUNCTION__, buf, maxwords); -+ memset(buf, 0, maxwords * sizeof(*buf)); -+ status = ixCryptoAccPkePseudoRandomNumberGet(maxwords, buf); -+ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { -+ dprintk("%s: ixCryptoAccPkePseudoRandomNumberGet failed %d\n", -+ __FUNCTION__, status); -+ return 0; -+ } -+ -+ /* -+ * run the random data through SHA to make it look more random -+ */ -+ -+ n = sizeof(sha_digest); /* process digest bytes at a time */ -+ -+ rc = 0; -+ for (i = 0; i < maxwords; i += n / sizeof(*buf)) { -+ if ((maxwords - i) * sizeof(*buf) < n) -+ n = (maxwords - i) * sizeof(*buf); -+ sha_done = 0; -+ status = ixCryptoAccPkeHashPerform(IX_CRYPTO_ACC_AUTH_SHA1, -+ (UINT8 *) &buf[i], n, ixp_hash_cb, sha_digest); -+ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { -+ dprintk("ixCryptoAccPkeHashPerform failed %d\n", status); -+ return -EIO; -+ } -+ while (!sha_done) -+ schedule(); -+ if (sha_done < 0) { -+ dprintk("ixCryptoAccPkeHashPerform failed CB %d\n", -sha_done); -+ return 0; -+ } -+ memcpy(&buf[i], sha_digest, n); -+ rc += n / sizeof(*buf);; -+ } -+ -+ return rc; -+} -+#endif /* CONFIG_OCF_RANDOMHARVEST */ -+ -+#endif /* __ixp46X */ -+ -+ -+ -+/* -+ * our driver startup and shutdown routines -+ */ -+ -+static int -+ixp_init(void) -+{ -+ dprintk("%s(%p)\n", __FUNCTION__, ixp_init); -+ -+ if (ixp_init_crypto && ixCryptoAccInit() != IX_CRYPTO_ACC_STATUS_SUCCESS) -+ printk("ixCryptoAccInit failed, assuming already initialised!\n"); -+ -+ qcache = kmem_cache_create("ixp4xx_q", sizeof(struct ixp_q), 0, -+ SLAB_HWCACHE_ALIGN, NULL -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) -+ , NULL -+#endif -+ ); -+ if (!qcache) { -+ printk("failed to create Qcache\n"); -+ return -ENOENT; -+ } -+ -+ memset(&ixpdev, 0, sizeof(ixpdev)); -+ softc_device_init(&ixpdev, "ixp4xx", 0, ixp_methods); -+ -+ ixp_id = crypto_get_driverid(softc_get_device(&ixpdev), -+ CRYPTOCAP_F_HARDWARE); -+ if (ixp_id < 0) -+ panic("IXP/OCF crypto device cannot initialize!"); -+ -+#define REGISTER(alg) \ -+ crypto_register(ixp_id,alg,0,0) -+ -+ REGISTER(CRYPTO_DES_CBC); -+ REGISTER(CRYPTO_3DES_CBC); -+ REGISTER(CRYPTO_RIJNDAEL128_CBC); -+#ifdef CONFIG_OCF_IXP4XX_SHA1_MD5 -+ REGISTER(CRYPTO_MD5); -+ REGISTER(CRYPTO_SHA1); -+#endif -+ REGISTER(CRYPTO_MD5_HMAC); -+ REGISTER(CRYPTO_SHA1_HMAC); -+#undef REGISTER -+ -+#ifdef __ixp46X -+ spin_lock_init(&ixp_pkq_lock); -+ /* -+ * we do not enable the go fast options here as they can potentially -+ * allow timing based attacks -+ * -+ * http://www.openssl.org/news/secadv_20030219.txt -+ */ -+ ixCryptoAccPkeEauExpConfig(0, 0); -+ crypto_kregister(ixp_id, CRK_MOD_EXP, 0); -+#ifdef CONFIG_OCF_RANDOMHARVEST -+ crypto_rregister(ixp_id, ixp_read_random, NULL); -+#endif -+#endif -+ -+ return 0; -+} -+ -+static void -+ixp_exit(void) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ crypto_unregister_all(ixp_id); -+ ixp_id = -1; -+ kmem_cache_destroy(qcache); -+ qcache = NULL; -+} -+ -+module_init(ixp_init); -+module_exit(ixp_exit); -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("ixp (OCF module for IXP4xx crypto)"); -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/Makefile linux-3.0.4/crypto/ocf/kirkwood/Makefile ---- linux-3.0.4.orig/crypto/ocf/kirkwood/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/Makefile 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,19 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+obj-$(CONFIG_OCF_KIRKWOOD) += mv_cesa.o -+ -+mv_cesa-y := cesa/mvCesa.o cesa/mvLru.o cesa/mvMD5.o cesa/mvSHA1.o cesa/AES/mvAesAlg.o cesa/AES/mvAesApi.o cesa/mvCesaDebug.o cesa_ocf_drv.o -+ -+# Extra objects required by the CESA driver -+mv_cesa-y += mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.o mvHal/kw_family/boardEnv/mvBoardEnvLib.o mvHal/mv_hal/twsi/mvTwsi.o mvHal/kw_family/ctrlEnv/sys/mvCpuIf.o mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.o mvHal/kw_family/ctrlEnv/sys/mvSysDram.o mvHal/linux_oss/mvOs.o mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.o mvHal/mv_hal/gpp/mvGpp.o mvHal/kw_family/ctrlEnv/sys/mvSysPex.o mvHal/mv_hal/pex/mvPex.o mvHal/kw_family/boardEnv/mvBoardEnvSpec.o mvHal/common/mvCommon.o mvHal/common/mvDebug.o mvHal/kw_family/ctrlEnv/sys/mvSysCesa.o -+ -+ifdef src -+EXTRA_CFLAGS += -I$(src)/.. -I$(src)/cesa -I$(src)/mvHal -I$(src)/mvHal/common -I$(src)/mvHal/kw_family -I$(src)/mvHal/mv_hal -I$(src)/mvHal/linux_oss -I$(src) -+endif -+ -+EXTRA_CFLAGS += -DMV_LINUX -DMV_CPU_LE -DMV_ARM -DMV_INCLUDE_CESA -DMV_INCLUDE_PEX -DMV_CACHE_COHERENCY=3 -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/AES/mvAes.h linux-3.0.4/crypto/ocf/kirkwood/cesa/AES/mvAes.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/AES/mvAes.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/cesa/AES/mvAes.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,62 @@ -+/* mvAes.h v2.0 August '99 -+ * Reference ANSI C code -+ */ -+ -+/* AES Cipher header file for ANSI C Submissions -+ Lawrence E. Bassham III -+ Computer Security Division -+ National Institute of Standards and Technology -+ -+ April 15, 1998 -+ -+ This sample is to assist implementers developing to the Cryptographic -+API Profile for AES Candidate Algorithm Submissions. Please consult this -+document as a cross-reference. -+ -+ ANY CHANGES, WHERE APPROPRIATE, TO INFORMATION PROVIDED IN THIS FILE -+MUST BE DOCUMENTED. CHANGES ARE ONLY APPROPRIATE WHERE SPECIFIED WITH -+THE STRING "CHANGE POSSIBLE". FUNCTION CALLS AND THEIR PARAMETERS CANNOT -+BE CHANGED. STRUCTURES CAN BE ALTERED TO ALLOW IMPLEMENTERS TO INCLUDE -+IMPLEMENTATION SPECIFIC INFORMATION. -+*/ -+ -+/* Includes: -+ Standard include files -+*/ -+ -+#include "mvOs.h" -+ -+ -+/* Error Codes - CHANGE POSSIBLE: inclusion of additional error codes */ -+ -+/* Key direction is invalid, e.g., unknown value */ -+#define AES_BAD_KEY_DIR -1 -+ -+/* Key material not of correct length */ -+#define AES_BAD_KEY_MAT -2 -+ -+/* Key passed is not valid */ -+#define AES_BAD_KEY_INSTANCE -3 -+ -+/* Params struct passed to cipherInit invalid */ -+#define AES_BAD_CIPHER_MODE -4 -+ -+/* Cipher in wrong state (e.g., not initialized) */ -+#define AES_BAD_CIPHER_STATE -5 -+ -+#define AES_BAD_CIPHER_INSTANCE -7 -+ -+ -+/* Function protoypes */ -+/* CHANGED: makeKey(): parameter blockLen added -+ this parameter is absolutely necessary if you want to -+ setup the round keys in a variable block length setting -+ cipherInit(): parameter blockLen added (for obvious reasons) -+ */ -+int aesMakeKey(MV_U8 *expandedKey, MV_U8 *keyMaterial, int keyLen, int blockLen); -+int aesBlockEncrypt128(MV_U8 mode, MV_U8 *IV, MV_U8 *expandedKey, int keyLen, -+ MV_U32 *plain, int numBlocks, MV_U32 *cipher); -+int aesBlockDecrypt128(MV_U8 mode, MV_U8 *IV, MV_U8 *expandedKey, int keyLen, -+ MV_U32 *plain, int numBlocks, MV_U32 *cipher); -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.c linux-3.0.4/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,317 @@ -+/* rijndael-alg-ref.c v2.0 August '99 -+ * Reference ANSI C code -+ * authors: Paulo Barreto -+ * Vincent Rijmen, K.U.Leuven -+ * -+ * This code is placed in the public domain. -+ */ -+ -+#include "mvOs.h" -+ -+#include "mvAesAlg.h" -+ -+#include "mvAesBoxes.dat" -+ -+ -+MV_U8 mul1(MV_U8 aa, MV_U8 bb); -+void KeyAddition(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC], MV_U8 BC); -+void ShiftRow128Enc(MV_U8 a[4][MAXBC]); -+void ShiftRow128Dec(MV_U8 a[4][MAXBC]); -+void Substitution(MV_U8 a[4][MAXBC], MV_U8 box[256]); -+void MixColumn(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC]); -+void InvMixColumn(MV_U8 a[4][MAXBC]); -+ -+ -+#define mul(aa, bb) (mask[bb] & Alogtable[aa + Logtable[bb]]) -+ -+MV_U8 mul1(MV_U8 aa, MV_U8 bb) -+{ -+ return mask[bb] & Alogtable[aa + Logtable[bb]]; -+} -+ -+ -+void KeyAddition(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC], MV_U8 BC) -+{ -+ /* Exor corresponding text input and round key input bytes -+ */ -+ ((MV_U32*)(&(a[0][0])))[0] ^= ((MV_U32*)(&(rk[0][0])))[0]; -+ ((MV_U32*)(&(a[1][0])))[0] ^= ((MV_U32*)(&(rk[1][0])))[0]; -+ ((MV_U32*)(&(a[2][0])))[0] ^= ((MV_U32*)(&(rk[2][0])))[0]; -+ ((MV_U32*)(&(a[3][0])))[0] ^= ((MV_U32*)(&(rk[3][0])))[0]; -+ -+} -+ -+void ShiftRow128Enc(MV_U8 a[4][MAXBC]) { -+ /* Row 0 remains unchanged -+ * The other three rows are shifted a variable amount -+ */ -+ MV_U8 tmp[MAXBC]; -+ -+ tmp[0] = a[1][1]; -+ tmp[1] = a[1][2]; -+ tmp[2] = a[1][3]; -+ tmp[3] = a[1][0]; -+ -+ ((MV_U32*)(&(a[1][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; -+ /* -+ a[1][0] = tmp[0]; -+ a[1][1] = tmp[1]; -+ a[1][2] = tmp[2]; -+ a[1][3] = tmp[3]; -+ */ -+ tmp[0] = a[2][2]; -+ tmp[1] = a[2][3]; -+ tmp[2] = a[2][0]; -+ tmp[3] = a[2][1]; -+ -+ ((MV_U32*)(&(a[2][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; -+ /* -+ a[2][0] = tmp[0]; -+ a[2][1] = tmp[1]; -+ a[2][2] = tmp[2]; -+ a[2][3] = tmp[3]; -+ */ -+ tmp[0] = a[3][3]; -+ tmp[1] = a[3][0]; -+ tmp[2] = a[3][1]; -+ tmp[3] = a[3][2]; -+ -+ ((MV_U32*)(&(a[3][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; -+ /* -+ a[3][0] = tmp[0]; -+ a[3][1] = tmp[1]; -+ a[3][2] = tmp[2]; -+ a[3][3] = tmp[3]; -+ */ -+} -+ -+void ShiftRow128Dec(MV_U8 a[4][MAXBC]) { -+ /* Row 0 remains unchanged -+ * The other three rows are shifted a variable amount -+ */ -+ MV_U8 tmp[MAXBC]; -+ -+ tmp[0] = a[1][3]; -+ tmp[1] = a[1][0]; -+ tmp[2] = a[1][1]; -+ tmp[3] = a[1][2]; -+ -+ ((MV_U32*)(&(a[1][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; -+ /* -+ a[1][0] = tmp[0]; -+ a[1][1] = tmp[1]; -+ a[1][2] = tmp[2]; -+ a[1][3] = tmp[3]; -+ */ -+ -+ tmp[0] = a[2][2]; -+ tmp[1] = a[2][3]; -+ tmp[2] = a[2][0]; -+ tmp[3] = a[2][1]; -+ -+ ((MV_U32*)(&(a[2][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; -+ /* -+ a[2][0] = tmp[0]; -+ a[2][1] = tmp[1]; -+ a[2][2] = tmp[2]; -+ a[2][3] = tmp[3]; -+ */ -+ -+ tmp[0] = a[3][1]; -+ tmp[1] = a[3][2]; -+ tmp[2] = a[3][3]; -+ tmp[3] = a[3][0]; -+ -+ ((MV_U32*)(&(a[3][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; -+ /* -+ a[3][0] = tmp[0]; -+ a[3][1] = tmp[1]; -+ a[3][2] = tmp[2]; -+ a[3][3] = tmp[3]; -+ */ -+} -+ -+void Substitution(MV_U8 a[4][MAXBC], MV_U8 box[256]) { -+ /* Replace every byte of the input by the byte at that place -+ * in the nonlinear S-box -+ */ -+ int i, j; -+ -+ for(i = 0; i < 4; i++) -+ for(j = 0; j < 4; j++) a[i][j] = box[a[i][j]] ; -+} -+ -+void MixColumn(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC]) { -+ /* Mix the four bytes of every column in a linear way -+ */ -+ MV_U8 b[4][MAXBC]; -+ int i, j; -+ -+ for(j = 0; j < 4; j++){ -+ b[0][j] = mul(25,a[0][j]) ^ mul(1,a[1][j]) ^ a[2][j] ^ a[3][j]; -+ b[1][j] = mul(25,a[1][j]) ^ mul(1,a[2][j]) ^ a[3][j] ^ a[0][j]; -+ b[2][j] = mul(25,a[2][j]) ^ mul(1,a[3][j]) ^ a[0][j] ^ a[1][j]; -+ b[3][j] = mul(25,a[3][j]) ^ mul(1,a[0][j]) ^ a[1][j] ^ a[2][j]; -+ } -+ for(i = 0; i < 4; i++) -+ /*for(j = 0; j < BC; j++) a[i][j] = b[i][j];*/ -+ ((MV_U32*)(&(a[i][0])))[0] = ((MV_U32*)(&(b[i][0])))[0] ^ ((MV_U32*)(&(rk[i][0])))[0];; -+} -+ -+void InvMixColumn(MV_U8 a[4][MAXBC]) { -+ /* Mix the four bytes of every column in a linear way -+ * This is the opposite operation of Mixcolumn -+ */ -+ MV_U8 b[4][MAXBC]; -+ int i, j; -+ -+ for(j = 0; j < 4; j++){ -+ b[0][j] = mul(223,a[0][j]) ^ mul(104,a[1][j]) ^ mul(238,a[2][j]) ^ mul(199,a[3][j]); -+ b[1][j] = mul(223,a[1][j]) ^ mul(104,a[2][j]) ^ mul(238,a[3][j]) ^ mul(199,a[0][j]); -+ b[2][j] = mul(223,a[2][j]) ^ mul(104,a[3][j]) ^ mul(238,a[0][j]) ^ mul(199,a[1][j]); -+ b[3][j] = mul(223,a[3][j]) ^ mul(104,a[0][j]) ^ mul(238,a[1][j]) ^ mul(199,a[2][j]); -+ } -+ for(i = 0; i < 4; i++) -+ /*for(j = 0; j < BC; j++) a[i][j] = b[i][j];*/ -+ ((MV_U32*)(&(a[i][0])))[0] = ((MV_U32*)(&(b[i][0])))[0]; -+} -+ -+int rijndaelKeySched (MV_U8 k[4][MAXKC], int keyBits, int blockBits, MV_U8 W[MAXROUNDS+1][4][MAXBC]) -+{ -+ /* Calculate the necessary round keys -+ * The number of calculations depends on keyBits and blockBits -+ */ -+ int KC, BC, ROUNDS; -+ int i, j, t, rconpointer = 0; -+ MV_U8 tk[4][MAXKC]; -+ -+ switch (keyBits) { -+ case 128: KC = 4; break; -+ case 192: KC = 6; break; -+ case 256: KC = 8; break; -+ default : return (-1); -+ } -+ -+ switch (blockBits) { -+ case 128: BC = 4; break; -+ case 192: BC = 6; break; -+ case 256: BC = 8; break; -+ default : return (-2); -+ } -+ -+ switch (keyBits >= blockBits ? keyBits : blockBits) { -+ case 128: ROUNDS = 10; break; -+ case 192: ROUNDS = 12; break; -+ case 256: ROUNDS = 14; break; -+ default : return (-3); /* this cannot happen */ -+ } -+ -+ -+ for(j = 0; j < KC; j++) -+ for(i = 0; i < 4; i++) -+ tk[i][j] = k[i][j]; -+ t = 0; -+ /* copy values into round key array */ -+ for(j = 0; (j < KC) && (t < (ROUNDS+1)*BC); j++, t++) -+ for(i = 0; i < 4; i++) W[t / BC][i][t % BC] = tk[i][j]; -+ -+ while (t < (ROUNDS+1)*BC) { /* while not enough round key material calculated */ -+ /* calculate new values */ -+ for(i = 0; i < 4; i++) -+ tk[i][0] ^= S[tk[(i+1)%4][KC-1]]; -+ tk[0][0] ^= rcon[rconpointer++]; -+ -+ if (KC != 8) -+ for(j = 1; j < KC; j++) -+ for(i = 0; i < 4; i++) tk[i][j] ^= tk[i][j-1]; -+ else { -+ for(j = 1; j < KC/2; j++) -+ for(i = 0; i < 4; i++) tk[i][j] ^= tk[i][j-1]; -+ for(i = 0; i < 4; i++) tk[i][KC/2] ^= S[tk[i][KC/2 - 1]]; -+ for(j = KC/2 + 1; j < KC; j++) -+ for(i = 0; i < 4; i++) tk[i][j] ^= tk[i][j-1]; -+ } -+ /* copy values into round key array */ -+ for(j = 0; (j < KC) && (t < (ROUNDS+1)*BC); j++, t++) -+ for(i = 0; i < 4; i++) W[t / BC][i][t % BC] = tk[i][j]; -+ } -+ -+ return 0; -+} -+ -+ -+ -+int rijndaelEncrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds) -+{ -+ /* Encryption of one block. -+ */ -+ int r, BC, ROUNDS; -+ -+ BC = 4; -+ ROUNDS = rounds; -+ -+ /* begin with a key addition -+ */ -+ -+ KeyAddition(a,rk[0],BC); -+ -+ /* ROUNDS-1 ordinary rounds -+ */ -+ for(r = 1; r < ROUNDS; r++) { -+ Substitution(a,S); -+ ShiftRow128Enc(a); -+ MixColumn(a, rk[r]); -+ /*KeyAddition(a,rk[r],BC);*/ -+ } -+ -+ /* Last round is special: there is no MixColumn -+ */ -+ Substitution(a,S); -+ ShiftRow128Enc(a); -+ KeyAddition(a,rk[ROUNDS],BC); -+ -+ return 0; -+} -+ -+ -+int rijndaelDecrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds) -+{ -+ int r, BC, ROUNDS; -+ -+ BC = 4; -+ ROUNDS = rounds; -+ -+ /* To decrypt: apply the inverse operations of the encrypt routine, -+ * in opposite order -+ * -+ * (KeyAddition is an involution: it 's equal to its inverse) -+ * (the inverse of Substitution with table S is Substitution with the inverse table of S) -+ * (the inverse of Shiftrow is Shiftrow over a suitable distance) -+ */ -+ -+ /* First the special round: -+ * without InvMixColumn -+ * with extra KeyAddition -+ */ -+ KeyAddition(a,rk[ROUNDS],BC); -+ ShiftRow128Dec(a); -+ Substitution(a,Si); -+ -+ /* ROUNDS-1 ordinary rounds -+ */ -+ for(r = ROUNDS-1; r > 0; r--) { -+ KeyAddition(a,rk[r],BC); -+ InvMixColumn(a); -+ ShiftRow128Dec(a); -+ Substitution(a,Si); -+ -+ } -+ -+ /* End with the extra key addition -+ */ -+ -+ KeyAddition(a,rk[0],BC); -+ -+ return 0; -+} -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.h linux-3.0.4/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,19 @@ -+/* rijndael-alg-ref.h v2.0 August '99 -+ * Reference ANSI C code -+ * authors: Paulo Barreto -+ * Vincent Rijmen, K.U.Leuven -+ */ -+#ifndef __RIJNDAEL_ALG_H -+#define __RIJNDAEL_ALG_H -+ -+#define MAXBC (128/32) -+#define MAXKC (256/32) -+#define MAXROUNDS 14 -+ -+ -+int rijndaelKeySched (MV_U8 k[4][MAXKC], int keyBits, int blockBits, MV_U8 rk[MAXROUNDS+1][4][MAXBC]); -+ -+int rijndaelEncrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds); -+int rijndaelDecrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds); -+ -+#endif /* __RIJNDAEL_ALG_H */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/AES/mvAesApi.c linux-3.0.4/crypto/ocf/kirkwood/cesa/AES/mvAesApi.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/AES/mvAesApi.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/cesa/AES/mvAesApi.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,312 @@ -+/* rijndael-api-ref.c v2.1 April 2000 -+ * Reference ANSI C code -+ * authors: v2.0 Paulo Barreto -+ * Vincent Rijmen, K.U.Leuven -+ * v2.1 Vincent Rijmen, K.U.Leuven -+ * -+ * This code is placed in the public domain. -+ */ -+#include "mvOs.h" -+ -+#include "mvAes.h" -+#include "mvAesAlg.h" -+ -+ -+/* Defines: -+ Add any additional defines you need -+*/ -+ -+#define MODE_ECB 1 /* Are we ciphering in ECB mode? */ -+#define MODE_CBC 2 /* Are we ciphering in CBC mode? */ -+#define MODE_CFB1 3 /* Are we ciphering in 1-bit CFB mode? */ -+ -+ -+int aesMakeKey(MV_U8 *expandedKey, MV_U8 *keyMaterial, int keyLen, int blockLen) -+{ -+ MV_U8 W[MAXROUNDS+1][4][MAXBC]; -+ MV_U8 k[4][MAXKC]; -+ MV_U8 j; -+ int i, rounds, KC; -+ -+ if (expandedKey == NULL) -+ { -+ return AES_BAD_KEY_INSTANCE; -+ } -+ -+ if (!((keyLen == 128) || (keyLen == 192) || (keyLen == 256))) -+ { -+ return AES_BAD_KEY_MAT; -+ } -+ -+ if (keyMaterial == NULL) -+ { -+ return AES_BAD_KEY_MAT; -+ } -+ -+ /* initialize key schedule: */ -+ for(i=0; i= 3) -+MV_U32 cesaChainLength = 0; -+int chainReqNum = 0; -+MV_U32 chainIndex = 0; -+MV_CESA_REQ* pNextActiveChain = 0; -+MV_CESA_REQ* pEndCurrChain = 0; -+MV_BOOL isFirstReq = MV_TRUE; -+#endif -+ -+static INLINE MV_U8* mvCesaSramAddrGet(void) -+{ -+#ifdef MV_CESA_NO_SRAM -+ return (MV_U8*)cesaSramVirtPtr; -+#else -+ return (MV_U8*)cesaCryptEngBase; -+#endif /* MV_CESA_NO_SRAM */ -+} -+ -+static INLINE MV_ULONG mvCesaSramVirtToPhys(void* pDev, MV_U8* pSramVirt) -+{ -+#ifdef MV_CESA_NO_SRAM -+ return (MV_ULONG)mvOsIoVirtToPhy(NULL, pSramVirt); -+#else -+ return (MV_ULONG)pSramVirt; -+#endif /* MV_CESA_NO_SRAM */ -+} -+ -+/* Internal Function prototypes */ -+ -+static INLINE void mvCesaSramDescrBuild(MV_U32 config, int frag, -+ int cryptoOffset, int ivOffset, int cryptoLength, -+ int macOffset, int digestOffset, int macLength, int macTotalLen, -+ MV_CESA_REQ *pCesaReq, MV_DMA_DESC* pDmaDesc); -+ -+static INLINE void mvCesaSramSaUpdate(short sid, MV_DMA_DESC *pDmaDesc); -+ -+static INLINE int mvCesaDmaCopyPrepare(MV_CESA_MBUF* pMbuf, MV_U8* pSramBuf, -+ MV_DMA_DESC* pDmaDesc, MV_BOOL isToMbuf, -+ int offset, int copySize, MV_BOOL skipFlush); -+ -+static void mvCesaHmacIvGet(MV_CESA_MAC_MODE macMode, unsigned char key[], int keyLength, -+ unsigned char innerIV[], unsigned char outerIV[]); -+ -+static MV_STATUS mvCesaFragAuthComplete(MV_CESA_REQ* pReq, MV_CESA_SA* pSA, -+ int macDataSize); -+ -+static MV_CESA_COMMAND* mvCesaCtrModeInit(void); -+ -+static MV_STATUS mvCesaCtrModePrepare(MV_CESA_COMMAND *pCtrModeCmd, MV_CESA_COMMAND *pCmd); -+static MV_STATUS mvCesaCtrModeComplete(MV_CESA_COMMAND *pOrgCmd, MV_CESA_COMMAND *pCmd); -+static void mvCesaCtrModeFinish(MV_CESA_COMMAND *pCmd); -+ -+static INLINE MV_STATUS mvCesaReqProcess(MV_CESA_REQ* pReq); -+static MV_STATUS mvCesaFragReqProcess(MV_CESA_REQ* pReq, MV_U8 frag); -+ -+static INLINE MV_STATUS mvCesaParamCheck(MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, MV_U8* pFixOffset); -+static INLINE MV_STATUS mvCesaFragParamCheck(MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd); -+ -+static INLINE void mvCesaFragSizeFind(MV_CESA_SA* pSA, MV_CESA_REQ* pReq, -+ int cryptoOffset, int macOffset, -+ int* pCopySize, int* pCryptoDataSize, int* pMacDataSize); -+static MV_STATUS mvCesaMbufCacheUnmap(MV_CESA_MBUF* pMbuf, int offset, int size); -+ -+ -+/* Go to the next request in the request queue */ -+static INLINE MV_CESA_REQ* MV_CESA_REQ_NEXT_PTR(MV_CESA_REQ* pReq) -+{ -+ if(pReq == pCesaReqLast) -+ return pCesaReqFirst; -+ -+ return pReq+1; -+} -+ -+#if (MV_CESA_VERSION >= 3) -+/* Go to the previous request in the request queue */ -+static INLINE MV_CESA_REQ* MV_CESA_REQ_PREV_PTR(MV_CESA_REQ* pReq) -+{ -+ if(pReq == pCesaReqFirst) -+ return pCesaReqLast; -+ -+ return pReq-1; -+} -+ -+#endif -+ -+ -+static INLINE void mvCesaReqProcessStart(MV_CESA_REQ* pReq) -+{ -+ int frag; -+ -+#if (MV_CESA_VERSION >= 3) -+ pReq->state = MV_CESA_CHAIN; -+#else -+ pReq->state = MV_CESA_PROCESS; -+#endif -+ cesaStats.startCount++; -+ -+ if(pReq->fragMode == MV_CESA_FRAG_NONE) -+ { -+ frag = 0; -+ } -+ else -+ { -+ frag = pReq->frags.nextFrag; -+ pReq->frags.nextFrag++; -+ } -+#if (MV_CESA_VERSION >= 2) -+ /* Enable TDMA engine */ -+ MV_REG_WRITE(MV_CESA_TDMA_CURR_DESC_PTR_REG, 0); -+ MV_REG_WRITE(MV_CESA_TDMA_NEXT_DESC_PTR_REG, -+ (MV_U32)mvCesaVirtToPhys(&pReq->dmaDescBuf, pReq->dma[frag].pDmaFirst)); -+#else -+ /* Enable IDMA engine */ -+ MV_REG_WRITE(IDMA_CURR_DESC_PTR_REG(0), 0); -+ MV_REG_WRITE(IDMA_NEXT_DESC_PTR_REG(0), -+ (MV_U32)mvCesaVirtToPhys(&pReq->dmaDescBuf, pReq->dma[frag].pDmaFirst)); -+#endif /* MV_CESA_VERSION >= 2 */ -+ -+#if defined(MV_BRIDGE_SYNC_REORDER) -+ mvOsBridgeReorderWA(); -+#endif -+ -+ /* Start Accelerator */ -+ MV_REG_WRITE(MV_CESA_CMD_REG, MV_CESA_CMD_CHAN_ENABLE_MASK); -+} -+ -+ -+/******************************************************************************* -+* mvCesaHalInit - Initialize the CESA driver -+* -+* DESCRIPTION: -+* This function initialize the CESA driver. -+* 1) Session database -+* 2) Request queue -+* 4) DMA descriptor lists - one list per request. Each list -+* has MV_CESA_MAX_DMA_DESC descriptors. -+* -+* INPUT: -+* numOfSession - maximum number of supported sessions -+* queueDepth - number of elements in the request queue. -+* pSramBase - virtual address of Sram -+* osHandle - A handle used by the OS to allocate memory for the -+* module (Passed to the OS Services layer) -+* -+* RETURN: -+* MV_OK - Success -+* MV_NO_RESOURCE - Fail, can't allocate resources: -+* Session database, request queue, -+* DMA descriptors list, LRU cache database. -+* MV_NOT_ALIGNED - Sram base address is not 8 byte aligned. -+* -+*******************************************************************************/ -+MV_STATUS mvCesaHalInit (int numOfSession, int queueDepth, char* pSramBase, MV_U32 cryptEngBase, -+ void *osHandle) -+{ -+ int i, req; -+ MV_U32 descOffsetReg, configReg; -+ MV_CESA_SRAM_SA *pSramSA; -+ -+ -+ mvOsPrintf("mvCesaInit: sessions=%d, queue=%d, pSram=%p\n", -+ numOfSession, queueDepth, pSramBase); -+ -+ cesaOsHandle = osHandle; -+ /* Create Session database */ -+ pCesaSAD = mvOsMalloc(sizeof(MV_CESA_SA)*numOfSession); -+ if(pCesaSAD == NULL) -+ { -+ mvOsPrintf("mvCesaInit: Can't allocate %u bytes for %d SAs\n", -+ sizeof(MV_CESA_SA)*numOfSession, numOfSession); -+ mvCesaFinish(); -+ return MV_NO_RESOURCE; -+ } -+ memset(pCesaSAD, 0, sizeof(MV_CESA_SA)*numOfSession); -+ cesaMaxSA = numOfSession; -+ -+ /* Allocate imag of sramSA in the DRAM */ -+ cesaSramSaBuf.bufSize = sizeof(MV_CESA_SRAM_SA)*numOfSession + -+ CPU_D_CACHE_LINE_SIZE; -+ -+ cesaSramSaBuf.bufVirtPtr = mvOsIoCachedMalloc(osHandle,cesaSramSaBuf.bufSize, -+ &cesaSramSaBuf.bufPhysAddr, -+ &cesaSramSaBuf.memHandle); -+ -+ if(cesaSramSaBuf.bufVirtPtr == NULL) -+ { -+ mvOsPrintf("mvCesaInit: Can't allocate %d bytes for sramSA structures\n", -+ cesaSramSaBuf.bufSize); -+ mvCesaFinish(); -+ return MV_NO_RESOURCE; -+ } -+ memset(cesaSramSaBuf.bufVirtPtr, 0, cesaSramSaBuf.bufSize); -+ pSramSA = (MV_CESA_SRAM_SA*)MV_ALIGN_UP((MV_ULONG)cesaSramSaBuf.bufVirtPtr, -+ CPU_D_CACHE_LINE_SIZE); -+ for(i=0; i= 3) -+ cesaChainLength = MAX_CESA_CHAIN_LENGTH; -+#endif -+ /* pSramBase must be 8 byte aligned */ -+ if( MV_IS_NOT_ALIGN((MV_ULONG)pSramBase, 8) ) -+ { -+ mvOsPrintf("mvCesaInit: pSramBase (%p) must be 8 byte aligned\n", -+ pSramBase); -+ mvCesaFinish(); -+ return MV_NOT_ALIGNED; -+ } -+ cesaSramVirtPtr = (MV_CESA_SRAM_MAP*)pSramBase; -+ -+ cesaCryptEngBase = cryptEngBase; -+ -+ /*memset(cesaSramVirtPtr, 0, sizeof(MV_CESA_SRAM_MAP));*/ -+ -+ /* Clear registers */ -+ MV_REG_WRITE( MV_CESA_CFG_REG, 0); -+ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); -+ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, 0); -+ -+ /* Initialize DMA descriptor lists for all requests in Request queue */ -+ descOffsetReg = configReg = 0; -+ for(req=0; reqcesaDescBuf.bufSize = sizeof(MV_CESA_DESC)*MV_CESA_MAX_REQ_FRAGS + -+ CPU_D_CACHE_LINE_SIZE; -+ -+ pReq->cesaDescBuf.bufVirtPtr = -+ mvOsIoCachedMalloc(osHandle,pReq->cesaDescBuf.bufSize, -+ &pReq->cesaDescBuf.bufPhysAddr, -+ &pReq->cesaDescBuf.memHandle); -+ -+ if(pReq->cesaDescBuf.bufVirtPtr == NULL) -+ { -+ mvOsPrintf("mvCesaInit: req=%d, Can't allocate %d bytes for CESA descriptors\n", -+ req, pReq->cesaDescBuf.bufSize); -+ mvCesaFinish(); -+ return MV_NO_RESOURCE; -+ } -+ memset(pReq->cesaDescBuf.bufVirtPtr, 0, pReq->cesaDescBuf.bufSize); -+ pReq->pCesaDesc = (MV_CESA_DESC*)MV_ALIGN_UP((MV_ULONG)pReq->cesaDescBuf.bufVirtPtr, -+ CPU_D_CACHE_LINE_SIZE); -+ -+ pReq->dmaDescBuf.bufSize = sizeof(MV_DMA_DESC)*MV_CESA_MAX_DMA_DESC*MV_CESA_MAX_REQ_FRAGS + -+ CPU_D_CACHE_LINE_SIZE; -+ -+ pReq->dmaDescBuf.bufVirtPtr = -+ mvOsIoCachedMalloc(osHandle,pReq->dmaDescBuf.bufSize, -+ &pReq->dmaDescBuf.bufPhysAddr, -+ &pReq->dmaDescBuf.memHandle); -+ -+ if(pReq->dmaDescBuf.bufVirtPtr == NULL) -+ { -+ mvOsPrintf("mvCesaInit: req=%d, Can't allocate %d bytes for DMA descriptor list\n", -+ req, pReq->dmaDescBuf.bufSize); -+ mvCesaFinish(); -+ return MV_NO_RESOURCE; -+ } -+ memset(pReq->dmaDescBuf.bufVirtPtr, 0, pReq->dmaDescBuf.bufSize); -+ pDmaDesc = (MV_DMA_DESC*)MV_ALIGN_UP((MV_ULONG)pReq->dmaDescBuf.bufVirtPtr, -+ CPU_D_CACHE_LINE_SIZE); -+ -+ for(frag=0; fragdma[frag]; -+ -+ pDma->pDmaFirst = pDmaDesc; -+ pDma->pDmaLast = NULL; -+ -+ for(i=0; ipDmaFirst[i].phyNextDescPtr = -+ MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, &pDmaDesc[i+1])); -+ } -+ pDma->pDmaFirst[i].phyNextDescPtr = 0; -+ mvOsCacheFlush(NULL, &pDma->pDmaFirst[0], MV_CESA_MAX_DMA_DESC*sizeof(MV_DMA_DESC)); -+ -+ pDmaDesc += MV_CESA_MAX_DMA_DESC; -+ } -+ } -+ /*mvCesaCryptoIvSet(NULL, MV_CESA_MAX_IV_LENGTH);*/ -+ descOffsetReg = (MV_U16)((MV_U8*)&cesaSramVirtPtr->desc - mvCesaSramAddrGet()); -+ MV_REG_WRITE(MV_CESA_CHAN_DESC_OFFSET_REG, descOffsetReg); -+ -+ configReg |= (MV_CESA_CFG_WAIT_DMA_MASK | MV_CESA_CFG_ACT_DMA_MASK); -+#if (MV_CESA_VERSION >= 3) -+ configReg |= MV_CESA_CFG_CHAIN_MODE_MASK; -+#endif -+ -+#if (MV_CESA_VERSION >= 2) -+ /* Initialize TDMA engine */ -+ MV_REG_WRITE(MV_CESA_TDMA_CTRL_REG, MV_CESA_TDMA_CTRL_VALUE); -+ MV_REG_WRITE(MV_CESA_TDMA_BYTE_COUNT_REG, 0); -+ MV_REG_WRITE(MV_CESA_TDMA_CURR_DESC_PTR_REG, 0); -+#else -+ /* Initialize IDMA #0 engine */ -+ MV_REG_WRITE(IDMA_CTRL_LOW_REG(0), 0); -+ MV_REG_WRITE(IDMA_BYTE_COUNT_REG(0), 0); -+ MV_REG_WRITE(IDMA_CURR_DESC_PTR_REG(0), 0); -+ MV_REG_WRITE(IDMA_CTRL_HIGH_REG(0), ICCHR_ENDIAN_LITTLE -+#ifdef MV_CPU_LE -+ | ICCHR_DESC_BYTE_SWAP_EN -+#endif -+ ); -+ /* Clear Cause Byte of IDMA channel to be used */ -+ MV_REG_WRITE( IDMA_CAUSE_REG, ~ICICR_CAUSE_MASK_ALL(0)); -+ MV_REG_WRITE(IDMA_CTRL_LOW_REG(0), MV_CESA_IDMA_CTRL_LOW_VALUE); -+#endif /* (MV_CESA_VERSION >= 2) */ -+ -+ /* Set CESA configuration registers */ -+ MV_REG_WRITE( MV_CESA_CFG_REG, configReg); -+ mvCesaDebugStatsClear(); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaFinish - Shutdown the CESA driver -+* -+* DESCRIPTION: -+* This function shutdown the CESA driver and free all allocted resources. -+* -+* INPUT: None -+* -+* RETURN: -+* MV_OK - Success -+* Other - Fail -+* -+*******************************************************************************/ -+MV_STATUS mvCesaFinish (void) -+{ -+ int req; -+ MV_CESA_REQ* pReq; -+ -+ mvOsPrintf("mvCesaFinish: \n"); -+ -+ cesaSramVirtPtr = NULL; -+ -+ /* Free all resources: DMA list, etc. */ -+ for(req=0; reqdmaDescBuf.bufVirtPtr != NULL) -+ { -+ mvOsIoCachedFree(cesaOsHandle,pReq->dmaDescBuf.bufSize, -+ pReq->dmaDescBuf.bufPhysAddr, -+ pReq->dmaDescBuf.bufVirtPtr, -+ pReq->dmaDescBuf.memHandle); -+ } -+ if(pReq->cesaDescBuf.bufVirtPtr != NULL) -+ { -+ mvOsIoCachedFree(cesaOsHandle,pReq->cesaDescBuf.bufSize, -+ pReq->cesaDescBuf.bufPhysAddr, -+ pReq->cesaDescBuf.bufVirtPtr, -+ pReq->cesaDescBuf.memHandle); -+ } -+ } -+#if (MV_CESA_VERSION < 2) -+ MV_REG_WRITE(IDMA_CTRL_LOW_REG(0), 0); -+#endif /* (MV_CESA_VERSION < 2) */ -+ -+ /* Free request queue */ -+ if(pCesaReqFirst != NULL) -+ { -+ mvOsFree(pCesaReqFirst); -+ pCesaReqFirst = pCesaReqLast = NULL; -+ pCesaReqEmpty = pCesaReqProcess = NULL; -+ cesaQueueDepth = cesaReqResources = 0; -+ } -+ /* Free SA database */ -+ if(pCesaSAD != NULL) -+ { -+ mvOsFree(pCesaSAD); -+ pCesaSAD = NULL; -+ cesaMaxSA = 0; -+ } -+ MV_REG_WRITE( MV_CESA_CFG_REG, 0); -+ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); -+ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, 0); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaCryptoIvSet - Set IV value for Crypto algorithm working in CBC mode -+* -+* DESCRIPTION: -+* This function set IV value using by Crypto algorithms in CBC mode. -+* Each channel has its own IV value. -+* This function gets IV value from the caller. If no IV value passed from -+* the caller or only part of IV passed, the function will init the rest part -+* of IV value (or the whole IV) by random value. -+* -+* INPUT: -+* MV_U8* pIV - Pointer to IV value supplied by user. If pIV==NULL -+* the function will generate random IV value. -+* int ivSize - size (in bytes) of IV provided by user. If ivSize is -+* smaller than maximum IV size, the function will complete -+* IV by random value. -+* -+* RETURN: -+* MV_OK - Success -+* Other - Fail -+* -+*******************************************************************************/ -+MV_STATUS mvCesaCryptoIvSet(MV_U8* pIV, int ivSize) -+{ -+ MV_U8* pSramIV; -+#if defined(MV646xx) -+ mvOsPrintf("mvCesaCryptoIvSet: ERR. shouldn't use this call on MV64660\n"); -+#endif -+ pSramIV = cesaSramVirtPtr->cryptoIV; -+ if(ivSize > MV_CESA_MAX_IV_LENGTH) -+ { -+ mvOsPrintf("mvCesaCryptoIvSet: ivSize (%d) is too large\n", ivSize); -+ ivSize = MV_CESA_MAX_IV_LENGTH; -+ } -+ if(pIV != NULL) -+ { -+ memcpy(pSramIV, pIV, ivSize); -+ ivSize = MV_CESA_MAX_IV_LENGTH - ivSize; -+ pSramIV += ivSize; -+ } -+ -+ while(ivSize > 0) -+ { -+ int size, mv_random = mvOsRand(); -+ -+ size = MV_MIN(ivSize, sizeof(mv_random)); -+ memcpy(pSramIV, (void*)&mv_random, size); -+ -+ pSramIV += size; -+ ivSize -= size; -+ } -+/* -+ mvOsCacheFlush(NULL, cesaSramVirtPtr->cryptoIV, -+ MV_CESA_MAX_IV_LENGTH); -+ mvOsCacheInvalidate(NULL, cesaSramVirtPtr->cryptoIV, -+ MV_CESA_MAX_IV_LENGTH); -+*/ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaSessionOpen - Open new uni-directional crypto session -+* -+* DESCRIPTION: -+* This function open new session. -+* -+* INPUT: -+* MV_CESA_OPEN_SESSION *pSession - pointer to new session input parameters -+* -+* OUTPUT: -+* short *pSid - session ID, should be used for all future -+* requests over this session. -+* -+* RETURN: -+* MV_OK - Session opend successfully. -+* MV_FULL - All sessions are in use, no free place in -+* SA database. -+* MV_BAD_PARAM - One of session input parameters is invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvCesaSessionOpen(MV_CESA_OPEN_SESSION *pSession, short* pSid) -+{ -+ short sid; -+ MV_U32 config = 0; -+ int digestSize; -+ -+ cesaStats.openedCount++; -+ -+ /* Find free entry in SAD */ -+ for(sid=0; sidoperation >= MV_CESA_MAX_OPERATION) -+ { -+ mvOsPrintf("mvCesaSessionOpen: Unexpected operation %d\n", -+ pSession->operation); -+ return MV_BAD_PARAM; -+ } -+ config |= (pSession->operation << MV_CESA_OPERATION_OFFSET); -+ -+ if( (pSession->direction != MV_CESA_DIR_ENCODE) && -+ (pSession->direction != MV_CESA_DIR_DECODE) ) -+ { -+ mvOsPrintf("mvCesaSessionOpen: Unexpected direction %d\n", -+ pSession->direction); -+ return MV_BAD_PARAM; -+ } -+ config |= (pSession->direction << MV_CESA_DIRECTION_BIT); -+ /* Clear SA entry */ -+ /* memset(&pCesaSAD[sid], 0, sizeof(pCesaSAD[sid])); */ -+ -+ /* Check AUTH parameters and update SA entry */ -+ if(pSession->operation != MV_CESA_CRYPTO_ONLY) -+ { -+ /* For HMAC (MD5 and SHA1) - Maximum Key size is 64 bytes */ -+ if( (pSession->macMode == MV_CESA_MAC_HMAC_MD5) || -+ (pSession->macMode == MV_CESA_MAC_HMAC_SHA1) ) -+ { -+ if(pSession->macKeyLength > MV_CESA_MAX_MAC_KEY_LENGTH) -+ { -+ mvOsPrintf("mvCesaSessionOpen: macKeyLength %d is too large\n", -+ pSession->macKeyLength); -+ return MV_BAD_PARAM; -+ } -+ mvCesaHmacIvGet(pSession->macMode, pSession->macKey, pSession->macKeyLength, -+ pCesaSAD[sid].pSramSA->macInnerIV, -+ pCesaSAD[sid].pSramSA->macOuterIV); -+ pCesaSAD[sid].macKeyLength = pSession->macKeyLength; -+ } -+ switch(pSession->macMode) -+ { -+ case MV_CESA_MAC_MD5: -+ case MV_CESA_MAC_HMAC_MD5: -+ digestSize = MV_CESA_MD5_DIGEST_SIZE; -+ break; -+ -+ case MV_CESA_MAC_SHA1: -+ case MV_CESA_MAC_HMAC_SHA1: -+ digestSize = MV_CESA_SHA1_DIGEST_SIZE; -+ break; -+ -+ default: -+ mvOsPrintf("mvCesaSessionOpen: Unexpected macMode %d\n", -+ pSession->macMode); -+ return MV_BAD_PARAM; -+ } -+ config |= (pSession->macMode << MV_CESA_MAC_MODE_OFFSET); -+ -+ /* Supported digest sizes: MD5 - 16 bytes (128 bits), */ -+ /* SHA1 - 20 bytes (160 bits) or 12 bytes (96 bits) for both */ -+ if( (pSession->digestSize != digestSize) && (pSession->digestSize != 12)) -+ { -+ mvOsPrintf("mvCesaSessionOpen: Unexpected digest size %d\n", -+ pSession->digestSize); -+ mvOsPrintf("\t Valid values [bytes]: MD5-16, SHA1-20, Both-12\n"); -+ return MV_BAD_PARAM; -+ } -+ pCesaSAD[sid].digestSize = pSession->digestSize; -+ -+ if(pCesaSAD[sid].digestSize == 12) -+ { -+ /* Set MV_CESA_MAC_DIGEST_SIZE_BIT if digest size is 96 bits */ -+ config |= (MV_CESA_MAC_DIGEST_96B << MV_CESA_MAC_DIGEST_SIZE_BIT); -+ } -+ } -+ -+ /* Check CRYPTO parameters and update SA entry */ -+ if(pSession->operation != MV_CESA_MAC_ONLY) -+ { -+ switch(pSession->cryptoAlgorithm) -+ { -+ case MV_CESA_CRYPTO_DES: -+ pCesaSAD[sid].cryptoKeyLength = MV_CESA_DES_KEY_LENGTH; -+ pCesaSAD[sid].cryptoBlockSize = MV_CESA_DES_BLOCK_SIZE; -+ break; -+ -+ case MV_CESA_CRYPTO_3DES: -+ pCesaSAD[sid].cryptoKeyLength = MV_CESA_3DES_KEY_LENGTH; -+ pCesaSAD[sid].cryptoBlockSize = MV_CESA_DES_BLOCK_SIZE; -+ /* Only EDE mode is supported */ -+ config |= (MV_CESA_CRYPTO_3DES_EDE << -+ MV_CESA_CRYPTO_3DES_MODE_BIT); -+ break; -+ -+ case MV_CESA_CRYPTO_AES: -+ switch(pSession->cryptoKeyLength) -+ { -+ case 16: -+ pCesaSAD[sid].cryptoKeyLength = MV_CESA_AES_128_KEY_LENGTH; -+ config |= (MV_CESA_CRYPTO_AES_KEY_128 << -+ MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET); -+ break; -+ -+ case 24: -+ pCesaSAD[sid].cryptoKeyLength = MV_CESA_AES_192_KEY_LENGTH; -+ config |= (MV_CESA_CRYPTO_AES_KEY_192 << -+ MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET); -+ break; -+ -+ case 32: -+ default: -+ pCesaSAD[sid].cryptoKeyLength = MV_CESA_AES_256_KEY_LENGTH; -+ config |= (MV_CESA_CRYPTO_AES_KEY_256 << -+ MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET); -+ break; -+ } -+ pCesaSAD[sid].cryptoBlockSize = MV_CESA_AES_BLOCK_SIZE; -+ break; -+ -+ default: -+ mvOsPrintf("mvCesaSessionOpen: Unexpected cryptoAlgorithm %d\n", -+ pSession->cryptoAlgorithm); -+ return MV_BAD_PARAM; -+ } -+ config |= (pSession->cryptoAlgorithm << MV_CESA_CRYPTO_ALG_OFFSET); -+ -+ if(pSession->cryptoKeyLength != pCesaSAD[sid].cryptoKeyLength) -+ { -+ mvOsPrintf("cesaSessionOpen: Wrong CryptoKeySize %d != %d\n", -+ pSession->cryptoKeyLength, pCesaSAD[sid].cryptoKeyLength); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Copy Crypto key */ -+ if( (pSession->cryptoAlgorithm == MV_CESA_CRYPTO_AES) && -+ (pSession->direction == MV_CESA_DIR_DECODE)) -+ { -+ /* Crypto Key for AES decode is computed from original key material */ -+ /* and depend on cryptoKeyLength (128/192/256 bits) */ -+ aesMakeKey(pCesaSAD[sid].pSramSA->cryptoKey, pSession->cryptoKey, -+ pSession->cryptoKeyLength*8, MV_CESA_AES_BLOCK_SIZE*8); -+ } -+ else -+ { -+ /*panic("mvCesaSessionOpen2");*/ -+ memcpy(pCesaSAD[sid].pSramSA->cryptoKey, pSession->cryptoKey, -+ pCesaSAD[sid].cryptoKeyLength); -+ -+ } -+ -+ switch(pSession->cryptoMode) -+ { -+ case MV_CESA_CRYPTO_ECB: -+ pCesaSAD[sid].cryptoIvSize = 0; -+ break; -+ -+ case MV_CESA_CRYPTO_CBC: -+ pCesaSAD[sid].cryptoIvSize = pCesaSAD[sid].cryptoBlockSize; -+ break; -+ -+ case MV_CESA_CRYPTO_CTR: -+ /* Supported only for AES algorithm */ -+ if(pSession->cryptoAlgorithm != MV_CESA_CRYPTO_AES) -+ { -+ mvOsPrintf("mvCesaSessionOpen: CRYPTO CTR mode supported for AES only\n"); -+ return MV_BAD_PARAM; -+ } -+ pCesaSAD[sid].cryptoIvSize = 0; -+ pCesaSAD[sid].ctrMode = 1; -+ /* Replace to ECB mode for HW */ -+ pSession->cryptoMode = MV_CESA_CRYPTO_ECB; -+ break; -+ -+ default: -+ mvOsPrintf("mvCesaSessionOpen: Unexpected cryptoMode %d\n", -+ pSession->cryptoMode); -+ return MV_BAD_PARAM; -+ } -+ -+ config |= (pSession->cryptoMode << MV_CESA_CRYPTO_MODE_BIT); -+ } -+ pCesaSAD[sid].config = config; -+ -+ mvOsCacheFlush(NULL, pCesaSAD[sid].pSramSA, sizeof(MV_CESA_SRAM_SA)); -+ if(pSid != NULL) -+ *pSid = sid; -+ -+ pCesaSAD[sid].valid = 1; -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaSessionClose - Close active crypto session -+* -+* DESCRIPTION: -+* This function closes existing session -+* -+* INPUT: -+* short sid - Unique identifier of the session to be closed -+* -+* RETURN: -+* MV_OK - Session closed successfully. -+* MV_BAD_PARAM - Session identifier is out of valid range. -+* MV_NOT_FOUND - There is no active session with such ID. -+* -+*******************************************************************************/ -+MV_STATUS mvCesaSessionClose(short sid) -+{ -+ cesaStats.closedCount++; -+ -+ if(sid >= cesaMaxSA) -+ { -+ mvOsPrintf("CESA Error: sid (%d) is too big\n", sid); -+ return MV_BAD_PARAM; -+ } -+ if(pCesaSAD[sid].valid == 0) -+ { -+ mvOsPrintf("CESA Warning: Session (sid=%d) is invalid\n", sid); -+ return MV_NOT_FOUND; -+ } -+ if(cesaLastSid == sid) -+ cesaLastSid = -1; -+ -+ pCesaSAD[sid].valid = 0; -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaAction - Perform crypto operation -+* -+* DESCRIPTION: -+* This function set new CESA request FIFO queue for further HW processing. -+* The function checks request parameters before set new request to the queue. -+* If one of the CESA channels is ready for processing the request will be -+* passed to HW. When request processing is finished the CESA interrupt will -+* be generated by HW. The caller should call mvCesaReadyGet() function to -+* complete request processing and get result. -+* -+* INPUT: -+* MV_CESA_COMMAND *pCmd - pointer to new CESA request. -+* It includes pointers to Source and Destination -+* buffers, session identifier get from -+* mvCesaSessionOpen() function, pointer to caller -+* private data and all needed crypto parameters. -+* -+* RETURN: -+* MV_OK - request successfully added to request queue -+* and will be processed. -+* MV_NO_MORE - request successfully added to request queue and will -+* be processed, but request queue became Full and next -+* request will not be accepted. -+* MV_NO_RESOURCE - request queue is FULL and the request can not -+* be processed. -+* MV_OUT_OF_CPU_MEM - memory allocation needed for request processing is -+* failed. Request can not be processed. -+* MV_NOT_ALLOWED - This mixed request (CRYPTO+MAC) can not be processed -+* as one request and should be splitted for two requests: -+* CRYPTO_ONLY and MAC_ONLY. -+* MV_BAD_PARAM - One of the request parameters is out of valid range. -+* The request can not be processed. -+* -+*******************************************************************************/ -+MV_STATUS mvCesaAction (MV_CESA_COMMAND *pCmd) -+{ -+ MV_STATUS status; -+ MV_CESA_REQ* pReq = pCesaReqEmpty; -+ int sid = pCmd->sessionId; -+ MV_CESA_SA* pSA = &pCesaSAD[sid]; -+#if (MV_CESA_VERSION >= 3) -+ MV_CESA_REQ* pFromReq; -+ MV_CESA_REQ* pToReq; -+#endif -+ cesaStats.reqCount++; -+ -+ /* Check that the request queue is not FULL */ -+ if(cesaReqResources == 0) -+ return MV_NO_RESOURCE; -+ -+ if( (sid >= cesaMaxSA) || (!pSA->valid) ) -+ { -+ mvOsPrintf("CESA Action Error: Session sid=%d is INVALID\n", sid); -+ return MV_BAD_PARAM; -+ } -+ pSA->count++; -+ -+ if(pSA->ctrMode) -+ { -+ /* AES in CTR mode can't be mixed with Authentication */ -+ if( (pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ mvOsPrintf("mvCesaAction : CRYPTO CTR mode can't be mixed with AUTH\n"); -+ return MV_NOT_ALLOWED; -+ } -+ /* All other request parameters should not be checked because key stream */ -+ /* (not user data) processed by AES HW engine */ -+ pReq->pOrgCmd = pCmd; -+ /* Allocate temporary pCmd structure for Key stream */ -+ pCmd = mvCesaCtrModeInit(); -+ if(pCmd == NULL) -+ return MV_OUT_OF_CPU_MEM; -+ -+ /* Prepare Key stream */ -+ mvCesaCtrModePrepare(pCmd, pReq->pOrgCmd); -+ pReq->fixOffset = 0; -+ } -+ else -+ { -+ /* Check request parameters and calculae fixOffset */ -+ status = mvCesaParamCheck(pSA, pCmd, &pReq->fixOffset); -+ if(status != MV_OK) -+ { -+ return status; -+ } -+ } -+ pReq->pCmd = pCmd; -+ -+ /* Check if the packet need fragmentation */ -+ if(pCmd->pSrc->mbufSize <= sizeof(cesaSramVirtPtr->buf) ) -+ { -+ /* request size is smaller than single buffer size */ -+ pReq->fragMode = MV_CESA_FRAG_NONE; -+ -+ /* Prepare NOT fragmented packets */ -+ status = mvCesaReqProcess(pReq); -+ if(status != MV_OK) -+ { -+ mvOsPrintf("CesaReady: ReqProcess error: pReq=%p, status=0x%x\n", -+ pReq, status); -+ } -+#if (MV_CESA_VERSION >= 3) -+ pReq->frags.numFrag = 1; -+#endif -+ } -+ else -+ { -+ MV_U8 frag = 0; -+ -+ /* request size is larger than buffer size - needs fragmentation */ -+ -+ /* Check restrictions for processing fragmented packets */ -+ status = mvCesaFragParamCheck(pSA, pCmd); -+ if(status != MV_OK) -+ return status; -+ -+ pReq->fragMode = MV_CESA_FRAG_FIRST; -+ pReq->frags.nextFrag = 0; -+ -+ /* Prepare Process Fragmented packets */ -+ while(pReq->fragMode != MV_CESA_FRAG_LAST) -+ { -+ if(frag >= MV_CESA_MAX_REQ_FRAGS) -+ { -+ mvOsPrintf("mvCesaAction Error: Too large request frag=%d\n", frag); -+ return MV_OUT_OF_CPU_MEM; -+ } -+ status = mvCesaFragReqProcess(pReq, frag); -+ if(status == MV_OK) { -+#if (MV_CESA_VERSION >= 3) -+ if(frag) { -+ pReq->dma[frag-1].pDmaLast->phyNextDescPtr = -+ MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, pReq->dma[frag].pDmaFirst)); -+ mvOsCacheFlush(NULL, pReq->dma[frag-1].pDmaLast, sizeof(MV_DMA_DESC)); -+ } -+#endif -+ frag++; -+ } -+ } -+ pReq->frags.numFrag = frag; -+#if (MV_CESA_VERSION >= 3) -+ if(chainReqNum) { -+ chainReqNum += pReq->frags.numFrag; -+ if(chainReqNum >= MAX_CESA_CHAIN_LENGTH) -+ chainReqNum = MAX_CESA_CHAIN_LENGTH; -+ } -+#endif -+ } -+ -+ pReq->state = MV_CESA_PENDING; -+ -+ pCesaReqEmpty = MV_CESA_REQ_NEXT_PTR(pReq); -+ cesaReqResources -= 1; -+ -+/* #ifdef CESA_DEBUG */ -+ if( (cesaQueueDepth - cesaReqResources) > cesaStats.maxReqCount) -+ cesaStats.maxReqCount = (cesaQueueDepth - cesaReqResources); -+/* #endif CESA_DEBUG */ -+ -+ cesaLastSid = sid; -+ -+#if (MV_CESA_VERSION >= 3) -+ /* Are we within chain bounderies and follows the first request ? */ -+ if((chainReqNum > 0) && (chainReqNum < MAX_CESA_CHAIN_LENGTH)) { -+ if(chainIndex) { -+ pFromReq = MV_CESA_REQ_PREV_PTR(pReq); -+ pToReq = pReq; -+ pReq->state = MV_CESA_CHAIN; -+ /* assume concatenating is possible */ -+ pFromReq->dma[pFromReq->frags.numFrag-1].pDmaLast->phyNextDescPtr = -+ MV_32BIT_LE(mvCesaVirtToPhys(&pToReq->dmaDescBuf, pToReq->dma[0].pDmaFirst)); -+ mvOsCacheFlush(NULL, pFromReq->dma[pFromReq->frags.numFrag-1].pDmaLast, sizeof(MV_DMA_DESC)); -+ -+ /* align active & next pointers */ -+ if(pNextActiveChain->state != MV_CESA_PENDING) -+ pEndCurrChain = pNextActiveChain = MV_CESA_REQ_NEXT_PTR(pReq); -+ } -+ else { /* we have only one chain, start new one */ -+ chainReqNum = 0; -+ chainIndex++; -+ /* align active & next pointers */ -+ if(pNextActiveChain->state != MV_CESA_PENDING) -+ pEndCurrChain = pNextActiveChain = pReq; -+ } -+ } -+ else { -+ /* In case we concatenate full chain */ -+ if(chainReqNum == MAX_CESA_CHAIN_LENGTH) { -+ chainIndex++; -+ if(pNextActiveChain->state != MV_CESA_PENDING) -+ pEndCurrChain = pNextActiveChain = pReq; -+ chainReqNum = 0; -+ } -+ -+ pReq = pCesaReqProcess; -+ if(pReq->state == MV_CESA_PENDING) { -+ pNextActiveChain = pReq; -+ pEndCurrChain = MV_CESA_REQ_NEXT_PTR(pReq); -+ /* Start Process new request */ -+ mvCesaReqProcessStart(pReq); -+ } -+ } -+ -+ chainReqNum++; -+ -+ if((chainIndex < MAX_CESA_CHAIN_LENGTH) && (chainReqNum > cesaStats.maxChainUsage)) -+ cesaStats.maxChainUsage = chainReqNum; -+ -+#else -+ -+ /* Check status of CESA channels and process requests if possible */ -+ pReq = pCesaReqProcess; -+ if(pReq->state == MV_CESA_PENDING) -+ { -+ /* Start Process new request */ -+ mvCesaReqProcessStart(pReq); -+ } -+#endif -+ /* If request queue became FULL - return MV_NO_MORE */ -+ if(cesaReqResources == 0) -+ return MV_NO_MORE; -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvCesaReadyGet - Get crypto request that processing is finished -+* -+* DESCRIPTION: -+* This function complete request processing and return ready request to -+* caller. To don't miss interrupts the caller must call this function -+* while MV_OK or MV_TERMINATE values returned. -+* -+* INPUT: -+* MV_U32 chanMap - map of CESA channels finished thier job -+* accordingly with CESA Cause register. -+* MV_CESA_RESULT* pResult - pointer to structure contains information -+* about ready request. It includes pointer to -+* user private structure "pReqPrv", session identifier -+* for this request "sessionId" and return code. -+* Return code set to MV_FAIL if calculated digest value -+* on decode direction is different than digest value -+* in the packet. -+* -+* RETURN: -+* MV_OK - Success, ready request is returned. -+* MV_NOT_READY - Next request is not ready yet. New interrupt will -+* be generated for futher request processing. -+* MV_EMPTY - There is no more request for processing. -+* MV_BUSY - Fragmented request is not ready yet. -+* MV_TERMINATE - Call this function once more to complete processing -+* of fragmented request. -+* -+*******************************************************************************/ -+MV_STATUS mvCesaReadyGet(MV_CESA_RESULT* pResult) -+{ -+ MV_STATUS status, readyStatus = MV_NOT_READY; -+ MV_U32 statusReg; -+ MV_CESA_REQ* pReq; -+ MV_CESA_SA* pSA; -+ -+#if (MV_CESA_VERSION >= 3) -+ if(isFirstReq == MV_TRUE) { -+ if(chainIndex == 0) -+ chainReqNum = 0; -+ -+ isFirstReq = MV_FALSE; -+ -+ if(pNextActiveChain->state == MV_CESA_PENDING) { -+ /* Start request Process */ -+ mvCesaReqProcessStart(pNextActiveChain); -+ pEndCurrChain = pNextActiveChain; -+ if(chainIndex > 0) -+ chainIndex--; -+ /* Update pNextActiveChain to next chain head */ -+ while(pNextActiveChain->state == MV_CESA_CHAIN) -+ pNextActiveChain = MV_CESA_REQ_NEXT_PTR(pNextActiveChain); -+ } -+ } -+ -+ /* Check if there are more processed requests - can we remove pEndCurrChain ??? */ -+ if(pCesaReqProcess == pEndCurrChain) { -+ isFirstReq = MV_TRUE; -+ pEndCurrChain = pNextActiveChain; -+#else -+ if(pCesaReqProcess->state != MV_CESA_PROCESS) { -+#endif -+ return MV_EMPTY; -+ } -+ -+#ifdef CESA_DEBUG -+ statusReg = MV_REG_READ(MV_CESA_STATUS_REG); -+ if( statusReg & MV_CESA_STATUS_ACTIVE_MASK ) -+ { -+ mvOsPrintf("mvCesaReadyGet: Not Ready, Status = 0x%x\n", statusReg); -+ cesaStats.notReadyCount++; -+ return MV_NOT_READY; -+ } -+#endif /* CESA_DEBUG */ -+ -+ cesaStats.readyCount++; -+ -+ pReq = pCesaReqProcess; -+ pSA = &pCesaSAD[pReq->pCmd->sessionId]; -+ -+ pResult->retCode = MV_OK; -+ if(pReq->fragMode != MV_CESA_FRAG_NONE) -+ { -+ MV_U8* pNewDigest; -+ int frag; -+#if (MV_CESA_VERSION >= 3) -+ pReq->frags.nextFrag = 1; -+ while(pReq->frags.nextFrag <= pReq->frags.numFrag) { -+#endif -+ frag = (pReq->frags.nextFrag - 1); -+ -+ /* Restore DMA descriptor list */ -+ pReq->dma[frag].pDmaLast->phyNextDescPtr = -+ MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, &pReq->dma[frag].pDmaLast[1])); -+ pReq->dma[frag].pDmaLast = NULL; -+ -+ /* Special processing for finished fragmented request */ -+ if(pReq->frags.nextFrag >= pReq->frags.numFrag) -+ { -+ mvCesaMbufCacheUnmap(pReq->pCmd->pDst, 0, pReq->pCmd->pDst->mbufSize); -+ -+ /* Fragmented packet is ready */ -+ if( (pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ int macDataSize = pReq->pCmd->macLength - pReq->frags.macSize; -+ -+ if(macDataSize != 0) -+ { -+ /* Calculate all other blocks by SW */ -+ mvCesaFragAuthComplete(pReq, pSA, macDataSize); -+ } -+ -+ /* Copy new digest from SRAM to the Destination buffer */ -+ pNewDigest = cesaSramVirtPtr->buf + pReq->frags.newDigestOffset; -+ status = mvCesaCopyToMbuf(pNewDigest, pReq->pCmd->pDst, -+ pReq->pCmd->digestOffset, pSA->digestSize); -+ -+ /* For decryption: Compare new digest value with original one */ -+ if((pSA->config & MV_CESA_DIRECTION_MASK) == -+ (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) -+ { -+ if( memcmp(pNewDigest, pReq->frags.orgDigest, pSA->digestSize) != 0) -+ { -+/* -+ mvOsPrintf("Digest error: chan=%d, newDigest=%p, orgDigest=%p, status = 0x%x\n", -+ chan, pNewDigest, pReq->frags.orgDigest, MV_REG_READ(MV_CESA_STATUS_REG)); -+*/ -+ /* Signiture verification is failed */ -+ pResult->retCode = MV_FAIL; -+ } -+ } -+ } -+ readyStatus = MV_OK; -+ } -+#if (MV_CESA_VERSION >= 3) -+ pReq->frags.nextFrag++; -+ } -+#endif -+ } -+ else -+ { -+ mvCesaMbufCacheUnmap(pReq->pCmd->pDst, 0, pReq->pCmd->pDst->mbufSize); -+ -+ /* Restore DMA descriptor list */ -+ pReq->dma[0].pDmaLast->phyNextDescPtr = -+ MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, &pReq->dma[0].pDmaLast[1])); -+ pReq->dma[0].pDmaLast = NULL; -+ if( ((pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) && -+ ((pSA->config & MV_CESA_DIRECTION_MASK) == -+ (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) ) -+ { -+ /* For AUTH on decode : Check Digest result in Status register */ -+ statusReg = MV_REG_READ(MV_CESA_STATUS_REG); -+ if(statusReg & MV_CESA_STATUS_DIGEST_ERR_MASK) -+ { -+/* -+ mvOsPrintf("Digest error: chan=%d, status = 0x%x\n", -+ chan, statusReg); -+*/ -+ /* Signiture verification is failed */ -+ pResult->retCode = MV_FAIL; -+ } -+ } -+ readyStatus = MV_OK; -+ } -+ -+ if(readyStatus == MV_OK) -+ { -+ /* If Request is ready - Prepare pResult structure */ -+ pResult->pReqPrv = pReq->pCmd->pReqPrv; -+ pResult->sessionId = pReq->pCmd->sessionId; -+ -+ pReq->state = MV_CESA_IDLE; -+ pCesaReqProcess = MV_CESA_REQ_NEXT_PTR(pReq); -+ cesaReqResources++; -+ -+ if(pSA->ctrMode) -+ { -+ /* For AES CTR mode - complete processing and free allocated resources */ -+ mvCesaCtrModeComplete(pReq->pOrgCmd, pReq->pCmd); -+ mvCesaCtrModeFinish(pReq->pCmd); -+ pReq->pOrgCmd = NULL; -+ } -+ } -+ -+#if (MV_CESA_VERSION < 3) -+ if(pCesaReqProcess->state == MV_CESA_PROCESS) -+ { -+ /* Start request Process */ -+ mvCesaReqProcessStart(pCesaReqProcess); -+ if(readyStatus == MV_NOT_READY) -+ readyStatus = MV_BUSY; -+ } -+ else if(pCesaReqProcess != pCesaReqEmpty) -+ { -+ /* Start process new request from the queue */ -+ mvCesaReqProcessStart(pCesaReqProcess); -+ } -+#endif -+ return readyStatus; -+} -+ -+/***************** Functions to work with CESA_MBUF structure ******************/ -+ -+/******************************************************************************* -+* mvCesaMbufOffset - Locate offset in the Mbuf structure -+* -+* DESCRIPTION: -+* This function locates offset inside Multi-Bufeer structure. -+* It get fragment number and place in the fragment where the offset -+* is located. -+* -+* -+* INPUT: -+* MV_CESA_MBUF* pMbuf - Pointer to multi-buffer structure -+* int offset - Offset from the beginning of the data presented by -+* the Mbuf structure. -+* -+* OUTPUT: -+* int* pBufOffset - Offset from the beginning of the fragment where -+* the offset is located. -+* -+* RETURN: -+* int - Number of fragment, where the offset is located\ -+* -+*******************************************************************************/ -+int mvCesaMbufOffset(MV_CESA_MBUF* pMbuf, int offset, int* pBufOffset) -+{ -+ int frag = 0; -+ -+ while(offset > 0) -+ { -+ if(frag >= pMbuf->numFrags) -+ { -+ mvOsPrintf("mvCesaMbufOffset: Error: frag (%d) > numFrags (%d)\n", -+ frag, pMbuf->numFrags); -+ return MV_INVALID; -+ } -+ if(offset < pMbuf->pFrags[frag].bufSize) -+ { -+ break; -+ } -+ offset -= pMbuf->pFrags[frag].bufSize; -+ frag++; -+ } -+ if(pBufOffset != NULL) -+ *pBufOffset = offset; -+ -+ return frag; -+} -+ -+/******************************************************************************* -+* mvCesaCopyFromMbuf - Copy data from the Mbuf structure to continuous buffer -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_U8* pDstBuf - Pointer to continuous buffer, where data is -+* copied to. -+* MV_CESA_MBUF* pSrcMbuf - Pointer to multi-buffer structure where data is -+* copied from. -+* int offset - Offset in the Mbuf structure where located first -+* byte of data should be copied. -+* int size - Size of data should be copied -+* -+* RETURN: -+* MV_OK - Success, all data is copied successfully. -+* MV_OUT_OF_RANGE - Failed, offset is out of Multi-buffer data range. -+* No data is copied. -+* MV_EMPTY - Multi-buffer structure has not enough data to copy -+* Data from the offset to end of Mbuf data is copied. -+* -+*******************************************************************************/ -+MV_STATUS mvCesaCopyFromMbuf(MV_U8* pDstBuf, MV_CESA_MBUF* pSrcMbuf, -+ int offset, int size) -+{ -+ int frag, fragOffset, bufSize; -+ MV_U8* pBuf; -+ -+ if(size == 0) -+ return MV_OK; -+ -+ frag = mvCesaMbufOffset(pSrcMbuf, offset, &fragOffset); -+ if(frag == MV_INVALID) -+ { -+ mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); -+ return MV_OUT_OF_RANGE; -+ } -+ -+ bufSize = pSrcMbuf->pFrags[frag].bufSize - fragOffset; -+ pBuf = pSrcMbuf->pFrags[frag].bufVirtPtr + fragOffset; -+ while(MV_TRUE) -+ { -+ if(size <= bufSize) -+ { -+ memcpy(pDstBuf, pBuf, size); -+ return MV_OK; -+ } -+ memcpy(pDstBuf, pBuf, bufSize); -+ size -= bufSize; -+ frag++; -+ pDstBuf += bufSize; -+ if(frag >= pSrcMbuf->numFrags) -+ break; -+ -+ bufSize = pSrcMbuf->pFrags[frag].bufSize; -+ pBuf = pSrcMbuf->pFrags[frag].bufVirtPtr; -+ } -+ mvOsPrintf("mvCesaCopyFromMbuf: Mbuf is EMPTY - %d bytes isn't copied\n", -+ size); -+ return MV_EMPTY; -+} -+ -+/******************************************************************************* -+* mvCesaCopyToMbuf - Copy data from continuous buffer to the Mbuf structure -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_U8* pSrcBuf - Pointer to continuous buffer, where data is -+* copied from. -+* MV_CESA_MBUF* pDstMbuf - Pointer to multi-buffer structure where data is -+* copied to. -+* int offset - Offset in the Mbuf structure where located first -+* byte of data should be copied. -+* int size - Size of data should be copied -+* -+* RETURN: -+* MV_OK - Success, all data is copied successfully. -+* MV_OUT_OF_RANGE - Failed, offset is out of Multi-buffer data range. -+* No data is copied. -+* MV_FULL - Multi-buffer structure has not enough place to copy -+* all data. Data from the offset to end of Mbuf data -+* is copied. -+* -+*******************************************************************************/ -+MV_STATUS mvCesaCopyToMbuf(MV_U8* pSrcBuf, MV_CESA_MBUF* pDstMbuf, -+ int offset, int size) -+{ -+ int frag, fragOffset, bufSize; -+ MV_U8* pBuf; -+ -+ if(size == 0) -+ return MV_OK; -+ -+ frag = mvCesaMbufOffset(pDstMbuf, offset, &fragOffset); -+ if(frag == MV_INVALID) -+ { -+ mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); -+ return MV_OUT_OF_RANGE; -+ } -+ -+ bufSize = pDstMbuf->pFrags[frag].bufSize - fragOffset; -+ pBuf = pDstMbuf->pFrags[frag].bufVirtPtr + fragOffset; -+ while(MV_TRUE) -+ { -+ if(size <= bufSize) -+ { -+ memcpy(pBuf, pSrcBuf, size); -+ return MV_OK; -+ } -+ memcpy(pBuf, pSrcBuf, bufSize); -+ size -= bufSize; -+ frag++; -+ pSrcBuf += bufSize; -+ if(frag >= pDstMbuf->numFrags) -+ break; -+ -+ bufSize = pDstMbuf->pFrags[frag].bufSize; -+ pBuf = pDstMbuf->pFrags[frag].bufVirtPtr; -+ } -+ mvOsPrintf("mvCesaCopyToMbuf: Mbuf is FULL - %d bytes isn't copied\n", -+ size); -+ return MV_FULL; -+} -+ -+/******************************************************************************* -+* mvCesaMbufCopy - Copy data from one Mbuf structure to the other Mbuf structure -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* -+* MV_CESA_MBUF* pDstMbuf - Pointer to multi-buffer structure where data is -+* copied to. -+* int dstMbufOffset - Offset in the dstMbuf structure where first byte -+* of data should be copied to. -+* MV_CESA_MBUF* pSrcMbuf - Pointer to multi-buffer structure where data is -+* copied from. -+* int srcMbufOffset - Offset in the srcMbuf structure where first byte -+* of data should be copied from. -+* int size - Size of data should be copied -+* -+* RETURN: -+* MV_OK - Success, all data is copied successfully. -+* MV_OUT_OF_RANGE - Failed, srcMbufOffset or dstMbufOffset is out of -+* srcMbuf or dstMbuf structure correspondently. -+* No data is copied. -+* MV_BAD_SIZE - srcMbuf or dstMbuf structure is too small to copy -+* all data. Partial data is copied -+* -+*******************************************************************************/ -+MV_STATUS mvCesaMbufCopy(MV_CESA_MBUF* pMbufDst, int dstMbufOffset, -+ MV_CESA_MBUF* pMbufSrc, int srcMbufOffset, int size) -+{ -+ int srcFrag, dstFrag, srcSize, dstSize, srcOffset, dstOffset; -+ int copySize; -+ MV_U8 *pSrc, *pDst; -+ -+ if(size == 0) -+ return MV_OK; -+ -+ srcFrag = mvCesaMbufOffset(pMbufSrc, srcMbufOffset, &srcOffset); -+ if(srcFrag == MV_INVALID) -+ { -+ mvOsPrintf("CESA srcMbuf Error: offset (%d) out of range\n", srcMbufOffset); -+ return MV_OUT_OF_RANGE; -+ } -+ pSrc = pMbufSrc->pFrags[srcFrag].bufVirtPtr + srcOffset; -+ srcSize = pMbufSrc->pFrags[srcFrag].bufSize - srcOffset; -+ -+ dstFrag = mvCesaMbufOffset(pMbufDst, dstMbufOffset, &dstOffset); -+ if(dstFrag == MV_INVALID) -+ { -+ mvOsPrintf("CESA dstMbuf Error: offset (%d) out of range\n", dstMbufOffset); -+ return MV_OUT_OF_RANGE; -+ } -+ pDst = pMbufDst->pFrags[dstFrag].bufVirtPtr + dstOffset; -+ dstSize = pMbufDst->pFrags[dstFrag].bufSize - dstOffset; -+ -+ while(size > 0) -+ { -+ copySize = MV_MIN(srcSize, dstSize); -+ if(size <= copySize) -+ { -+ memcpy(pDst, pSrc, size); -+ return MV_OK; -+ } -+ memcpy(pDst, pSrc, copySize); -+ size -= copySize; -+ srcSize -= copySize; -+ dstSize -= copySize; -+ -+ if(srcSize == 0) -+ { -+ srcFrag++; -+ if(srcFrag >= pMbufSrc->numFrags) -+ break; -+ -+ pSrc = pMbufSrc->pFrags[srcFrag].bufVirtPtr; -+ srcSize = pMbufSrc->pFrags[srcFrag].bufSize; -+ } -+ -+ if(dstSize == 0) -+ { -+ dstFrag++; -+ if(dstFrag >= pMbufDst->numFrags) -+ break; -+ -+ pDst = pMbufDst->pFrags[dstFrag].bufVirtPtr; -+ dstSize = pMbufDst->pFrags[dstFrag].bufSize; -+ } -+ } -+ mvOsPrintf("mvCesaMbufCopy: BAD size - %d bytes isn't copied\n", -+ size); -+ -+ return MV_BAD_SIZE; -+} -+ -+static MV_STATUS mvCesaMbufCacheUnmap(MV_CESA_MBUF* pMbuf, int offset, int size) -+{ -+ int frag, fragOffset, bufSize; -+ MV_U8* pBuf; -+ -+ if(size == 0) -+ return MV_OK; -+ -+ frag = mvCesaMbufOffset(pMbuf, offset, &fragOffset); -+ if(frag == MV_INVALID) -+ { -+ mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); -+ return MV_OUT_OF_RANGE; -+ } -+ -+ bufSize = pMbuf->pFrags[frag].bufSize - fragOffset; -+ pBuf = pMbuf->pFrags[frag].bufVirtPtr + fragOffset; -+ while(MV_TRUE) -+ { -+ if(size <= bufSize) -+ { -+ mvOsCacheUnmap(NULL, mvOsIoVirtToPhy(NULL, pBuf), size); -+ return MV_OK; -+ } -+ -+ mvOsCacheUnmap(NULL, mvOsIoVirtToPhy(NULL, pBuf), bufSize); -+ size -= bufSize; -+ frag++; -+ if(frag >= pMbuf->numFrags) -+ break; -+ -+ bufSize = pMbuf->pFrags[frag].bufSize; -+ pBuf = pMbuf->pFrags[frag].bufVirtPtr; -+ } -+ mvOsPrintf("%s: Mbuf is FULL - %d bytes isn't Unmapped\n", -+ __FUNCTION__, size); -+ return MV_FULL; -+} -+ -+ -+/*************************************** Local Functions ******************************/ -+ -+/******************************************************************************* -+* mvCesaFragReqProcess - Process fragmented request -+* -+* DESCRIPTION: -+* This function processes a fragment of fragmented request (First, Middle or Last) -+* -+* -+* INPUT: -+* MV_CESA_REQ* pReq - Pointer to the request in the request queue. -+* -+* RETURN: -+* MV_OK - The fragment is successfully passed to HW for processing. -+* MV_TERMINATE - Means, that HW finished its work on this packet and no more -+* interrupts will be generated for this request. -+* Function mvCesaReadyGet() must be called to complete request -+* processing and get request result. -+* -+*******************************************************************************/ -+static MV_STATUS mvCesaFragReqProcess(MV_CESA_REQ* pReq, MV_U8 frag) -+{ -+ int i, copySize, cryptoDataSize, macDataSize, sid; -+ int cryptoIvOffset, digestOffset; -+ MV_U32 config; -+ MV_CESA_COMMAND* pCmd = pReq->pCmd; -+ MV_CESA_SA* pSA; -+ MV_CESA_MBUF* pMbuf; -+ MV_DMA_DESC* pDmaDesc = pReq->dma[frag].pDmaFirst; -+ MV_U8* pSramBuf = cesaSramVirtPtr->buf; -+ int macTotalLen = 0; -+ int fixOffset, cryptoOffset, macOffset; -+ -+ cesaStats.fragCount++; -+ -+ sid = pReq->pCmd->sessionId; -+ -+ pSA = &pCesaSAD[sid]; -+ -+ cryptoIvOffset = digestOffset = 0; -+ i = macDataSize = 0; -+ cryptoDataSize = 0; -+ -+ /* First fragment processing */ -+ if(pReq->fragMode == MV_CESA_FRAG_FIRST) -+ { -+ /* pReq->frags monitors processing of fragmented request between fragments */ -+ pReq->frags.bufOffset = 0; -+ pReq->frags.cryptoSize = 0; -+ pReq->frags.macSize = 0; -+ -+ config = pSA->config | (MV_CESA_FRAG_FIRST << MV_CESA_FRAG_MODE_OFFSET); -+ -+ /* fixOffset can be not equal to zero only for FIRST fragment */ -+ fixOffset = pReq->fixOffset; -+ /* For FIRST fragment crypto and mac offsets are taken from pCmd */ -+ cryptoOffset = pCmd->cryptoOffset; -+ macOffset = pCmd->macOffset; -+ -+ copySize = sizeof(cesaSramVirtPtr->buf) - pReq->fixOffset; -+ -+ /* Find fragment size: Must meet all requirements for CRYPTO and MAC -+ * cryptoDataSize - size of data will be encrypted/decrypted in this fragment -+ * macDataSize - size of data will be signed/verified in this fragment -+ * copySize - size of data will be copied from srcMbuf to SRAM and -+ * back to dstMbuf for this fragment -+ */ -+ mvCesaFragSizeFind(pSA, pReq, cryptoOffset, macOffset, -+ ©Size, &cryptoDataSize, &macDataSize); -+ -+ if( (pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) -+ { -+ /* CryptoIV special processing */ -+ if( (pSA->config & MV_CESA_CRYPTO_MODE_MASK) == -+ (MV_CESA_CRYPTO_CBC << MV_CESA_CRYPTO_MODE_BIT) ) -+ { -+ /* In CBC mode for encode direction when IV from user */ -+ if( (pCmd->ivFromUser) && -+ ((pSA->config & MV_CESA_DIRECTION_MASK) == -+ (MV_CESA_DIR_ENCODE << MV_CESA_DIRECTION_BIT)) ) -+ { -+ -+ /* For Crypto Encode in CBC mode HW always takes IV from SRAM IVPointer, -+ * (not from IVBufPointer). So when ivFromUser==1, we should copy IV from user place -+ * in the buffer to SRAM IVPointer -+ */ -+ i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->cryptoIV, &pDmaDesc[i], -+ MV_FALSE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); -+ } -+ -+ /* Special processing when IV is not located in the first fragment */ -+ if(pCmd->ivOffset > (copySize - pSA->cryptoIvSize)) -+ { -+ /* Prepare dummy place for cryptoIV in SRAM */ -+ cryptoIvOffset = cesaSramVirtPtr->tempCryptoIV - mvCesaSramAddrGet(); -+ -+ /* For Decryption: Copy IV value from pCmd->ivOffset to Special SRAM place */ -+ if((pSA->config & MV_CESA_DIRECTION_MASK) == -+ (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) -+ { -+ i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->tempCryptoIV, &pDmaDesc[i], -+ MV_FALSE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); -+ } -+ else -+ { -+ /* For Encryption when IV is NOT from User: */ -+ /* Copy IV from SRAM to buffer (pCmd->ivOffset) */ -+ if(pCmd->ivFromUser == 0) -+ { -+ /* copy IV value from cryptoIV to Buffer (pCmd->ivOffset) */ -+ i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->cryptoIV, &pDmaDesc[i], -+ MV_TRUE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); -+ } -+ } -+ } -+ else -+ { -+ cryptoIvOffset = pCmd->ivOffset; -+ } -+ } -+ } -+ -+ if( (pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ /* MAC digest special processing on Decode direction */ -+ if((pSA->config & MV_CESA_DIRECTION_MASK) == -+ (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) -+ { -+ /* Save digest from pCmd->digestOffset */ -+ mvCesaCopyFromMbuf(pReq->frags.orgDigest, -+ pCmd->pSrc, pCmd->digestOffset, pSA->digestSize); -+ -+ /* If pCmd->digestOffset is not located on the first */ -+ if(pCmd->digestOffset > (copySize - pSA->digestSize)) -+ { -+ MV_U8 digestZero[MV_CESA_MAX_DIGEST_SIZE]; -+ -+ /* Set zeros to pCmd->digestOffset (DRAM) */ -+ memset(digestZero, 0, MV_CESA_MAX_DIGEST_SIZE); -+ mvCesaCopyToMbuf(digestZero, pCmd->pSrc, pCmd->digestOffset, pSA->digestSize); -+ -+ /* Prepare dummy place for digest in SRAM */ -+ digestOffset = cesaSramVirtPtr->tempDigest - mvCesaSramAddrGet(); -+ } -+ else -+ { -+ digestOffset = pCmd->digestOffset; -+ } -+ } -+ } -+ /* Update SA in SRAM */ -+ if(cesaLastSid != sid) -+ { -+ mvCesaSramSaUpdate(sid, &pDmaDesc[i]); -+ i++; -+ } -+ -+ pReq->fragMode = MV_CESA_FRAG_MIDDLE; -+ } -+ else -+ { -+ /* Continue fragment */ -+ fixOffset = 0; -+ cryptoOffset = 0; -+ macOffset = 0; -+ if( (pCmd->pSrc->mbufSize - pReq->frags.bufOffset) <= sizeof(cesaSramVirtPtr->buf)) -+ { -+ /* Last fragment */ -+ config = pSA->config | (MV_CESA_FRAG_LAST << MV_CESA_FRAG_MODE_OFFSET); -+ pReq->fragMode = MV_CESA_FRAG_LAST; -+ copySize = pCmd->pSrc->mbufSize - pReq->frags.bufOffset; -+ -+ if( (pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ macDataSize = pCmd->macLength - pReq->frags.macSize; -+ -+ /* If pCmd->digestOffset is not located on last fragment */ -+ if(pCmd->digestOffset < pReq->frags.bufOffset) -+ { -+ /* Prepare dummy place for digest in SRAM */ -+ digestOffset = cesaSramVirtPtr->tempDigest - mvCesaSramAddrGet(); -+ } -+ else -+ { -+ digestOffset = pCmd->digestOffset - pReq->frags.bufOffset; -+ } -+ pReq->frags.newDigestOffset = digestOffset; -+ macTotalLen = pCmd->macLength; -+ -+ /* HW can't calculate the Digest correctly for fragmented packets -+ * in the following cases: -+ * - MV88F5182 || -+ * - MV88F5181L when total macLength more that 16 Kbytes || -+ * - total macLength more that 64 Kbytes -+ */ -+ if( (mvCtrlModelGet() == MV_5182_DEV_ID) || -+ ( (mvCtrlModelGet() == MV_5181_DEV_ID) && -+ (mvCtrlRevGet() >= MV_5181L_A0_REV) && -+ (pCmd->macLength >= (1 << 14)) ) ) -+ { -+ return MV_TERMINATE; -+ } -+ } -+ if( (pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ cryptoDataSize = pCmd->cryptoLength - pReq->frags.cryptoSize; -+ } -+ -+ /* cryptoIvOffset - don't care */ -+ } -+ else -+ { -+ /* WA for MV88F5182 SHA1 and MD5 fragmentation mode */ -+ if( (mvCtrlModelGet() == MV_5182_DEV_ID) && -+ (((pSA->config & MV_CESA_MAC_MODE_MASK) == -+ (MV_CESA_MAC_MD5 << MV_CESA_MAC_MODE_OFFSET)) || -+ ((pSA->config & MV_CESA_MAC_MODE_MASK) == -+ (MV_CESA_MAC_SHA1 << MV_CESA_MAC_MODE_OFFSET))) ) -+ { -+ pReq->frags.newDigestOffset = cesaSramVirtPtr->tempDigest - mvCesaSramAddrGet(); -+ pReq->fragMode = MV_CESA_FRAG_LAST; -+ -+ return MV_TERMINATE; -+ } -+ /* Middle fragment */ -+ config = pSA->config | (MV_CESA_FRAG_MIDDLE << MV_CESA_FRAG_MODE_OFFSET); -+ copySize = sizeof(cesaSramVirtPtr->buf); -+ /* digestOffset and cryptoIvOffset - don't care */ -+ -+ /* Find fragment size */ -+ mvCesaFragSizeFind(pSA, pReq, cryptoOffset, macOffset, -+ ©Size, &cryptoDataSize, &macDataSize); -+ } -+ } -+ /********* Prepare DMA descriptors to copy from pSrc to SRAM *********/ -+ pMbuf = pCmd->pSrc; -+ i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], -+ MV_FALSE, pReq->frags.bufOffset, copySize, pCmd->skipFlush); -+ -+ /* Prepare CESA descriptor to copy from DRAM to SRAM by DMA */ -+ mvCesaSramDescrBuild(config, frag, -+ cryptoOffset + fixOffset, cryptoIvOffset + fixOffset, -+ cryptoDataSize, macOffset + fixOffset, -+ digestOffset + fixOffset, macDataSize, macTotalLen, -+ pReq, &pDmaDesc[i]); -+ i++; -+ -+ /* Add special descriptor Ownership for CPU */ -+ pDmaDesc[i].byteCnt = 0; -+ pDmaDesc[i].phySrcAdd = 0; -+ pDmaDesc[i].phyDestAdd = 0; -+ i++; -+ -+ /********* Prepare DMA descriptors to copy from SRAM to pDst *********/ -+ pMbuf = pCmd->pDst; -+ i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], -+ MV_TRUE, pReq->frags.bufOffset, copySize, pCmd->skipFlush); -+ -+ /* Next field of Last DMA descriptor must be NULL */ -+ pDmaDesc[i-1].phyNextDescPtr = 0; -+ pReq->dma[frag].pDmaLast = &pDmaDesc[i-1]; -+ mvOsCacheFlush(NULL, pReq->dma[frag].pDmaFirst, -+ i*sizeof(MV_DMA_DESC)); -+ -+ /*mvCesaDebugDescriptor(&cesaSramVirtPtr->desc[frag]);*/ -+ -+ pReq->frags.bufOffset += copySize; -+ pReq->frags.cryptoSize += cryptoDataSize; -+ pReq->frags.macSize += macDataSize; -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvCesaReqProcess - Process regular (Non-fragmented) request -+* -+* DESCRIPTION: -+* This function processes the whole (not fragmented) request -+* -+* INPUT: -+* MV_CESA_REQ* pReq - Pointer to the request in the request queue. -+* -+* RETURN: -+* MV_OK - The request is successfully passed to HW for processing. -+* Other - Failure. The request will not be processed -+* -+*******************************************************************************/ -+static MV_STATUS mvCesaReqProcess(MV_CESA_REQ* pReq) -+{ -+ MV_CESA_MBUF *pMbuf; -+ MV_DMA_DESC *pDmaDesc; -+ MV_U8 *pSramBuf; -+ int sid, i, fixOffset; -+ MV_CESA_SA *pSA; -+ MV_CESA_COMMAND *pCmd = pReq->pCmd; -+ -+ cesaStats.procCount++; -+ -+ sid = pCmd->sessionId; -+ pSA = &pCesaSAD[sid]; -+ pDmaDesc = pReq->dma[0].pDmaFirst; -+ pSramBuf = cesaSramVirtPtr->buf; -+ fixOffset = pReq->fixOffset; -+ -+/* -+ mvOsPrintf("mvCesaReqProcess: sid=%d, pSA=%p, pDmaDesc=%p, pSramBuf=%p\n", -+ sid, pSA, pDmaDesc, pSramBuf); -+*/ -+ i = 0; -+ -+ /* Crypto IV Special processing in CBC mode for Encryption direction */ -+ if( ((pSA->config & MV_CESA_OPERATION_MASK) != (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) && -+ ((pSA->config & MV_CESA_CRYPTO_MODE_MASK) == (MV_CESA_CRYPTO_CBC << MV_CESA_CRYPTO_MODE_BIT)) && -+ ((pSA->config & MV_CESA_DIRECTION_MASK) == (MV_CESA_DIR_ENCODE << MV_CESA_DIRECTION_BIT)) && -+ (pCmd->ivFromUser) ) -+ { -+ /* For Crypto Encode in CBC mode HW always takes IV from SRAM IVPointer, -+ * (not from IVBufPointer). So when ivFromUser==1, we should copy IV from user place -+ * in the buffer to SRAM IVPointer -+ */ -+ i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->cryptoIV, &pDmaDesc[i], -+ MV_FALSE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); -+ } -+ -+ /* Update SA in SRAM */ -+ if(cesaLastSid != sid) -+ { -+ mvCesaSramSaUpdate(sid, &pDmaDesc[i]); -+ i++; -+ } -+ -+ /********* Prepare DMA descriptors to copy from pSrc to SRAM *********/ -+ pMbuf = pCmd->pSrc; -+ i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], -+ MV_FALSE, 0, pMbuf->mbufSize, pCmd->skipFlush); -+ -+ /* Prepare Security Accelerator descriptor to SRAM words 0 - 7 */ -+ mvCesaSramDescrBuild(pSA->config, 0, pCmd->cryptoOffset + fixOffset, -+ pCmd->ivOffset + fixOffset, pCmd->cryptoLength, -+ pCmd->macOffset + fixOffset, pCmd->digestOffset + fixOffset, -+ pCmd->macLength, pCmd->macLength, pReq, &pDmaDesc[i]); -+ i++; -+ -+ /* Add special descriptor Ownership for CPU */ -+ pDmaDesc[i].byteCnt = 0; -+ pDmaDesc[i].phySrcAdd = 0; -+ pDmaDesc[i].phyDestAdd = 0; -+ i++; -+ -+ /********* Prepare DMA descriptors to copy from SRAM to pDst *********/ -+ pMbuf = pCmd->pDst; -+ i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], -+ MV_TRUE, 0, pMbuf->mbufSize, pCmd->skipFlush); -+ -+ /* Next field of Last DMA descriptor must be NULL */ -+ pDmaDesc[i-1].phyNextDescPtr = 0; -+ pReq->dma[0].pDmaLast = &pDmaDesc[i-1]; -+ mvOsCacheFlush(NULL, pReq->dma[0].pDmaFirst, i*sizeof(MV_DMA_DESC)); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvCesaSramDescrBuild - Set CESA descriptor in SRAM -+* -+* DESCRIPTION: -+* This function builds CESA descriptor in SRAM from all Command parameters -+* -+* -+* INPUT: -+* int chan - CESA channel uses the descriptor -+* MV_U32 config - 32 bits of WORD_0 in CESA descriptor structure -+* int cryptoOffset - Offset from the beginning of SRAM buffer where -+* data for encryption/decription is started. -+* int ivOffset - Offset of crypto IV from the SRAM base. Valid only -+* for first fragment. -+* int cryptoLength - Size (in bytes) of data for encryption/descryption -+* operation on this fragment. -+* int macOffset - Offset from the beginning of SRAM buffer where -+* data for Authentication is started -+* int digestOffset - Offset from the beginning of SRAM buffer where -+* digest is located. Valid for first and last fragments. -+* int macLength - Size (in bytes) of data for Authentication -+* operation on this fragment. -+* int macTotalLen - Toatl size (in bytes) of data for Authentication -+* operation on the whole request (packet). Valid for -+* last fragment only. -+* -+* RETURN: None -+* -+*******************************************************************************/ -+static void mvCesaSramDescrBuild(MV_U32 config, int frag, -+ int cryptoOffset, int ivOffset, int cryptoLength, -+ int macOffset, int digestOffset, int macLength, -+ int macTotalLen, MV_CESA_REQ* pReq, MV_DMA_DESC* pDmaDesc) -+{ -+ MV_CESA_DESC* pCesaDesc = &pReq->pCesaDesc[frag]; -+ MV_CESA_DESC* pSramDesc = pSramDesc = &cesaSramVirtPtr->desc; -+ MV_U16 sramBufOffset = (MV_U16)((MV_U8*)cesaSramVirtPtr->buf - mvCesaSramAddrGet()); -+ -+ pCesaDesc->config = MV_32BIT_LE(config); -+ -+ if( (config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ /* word 1 */ -+ pCesaDesc->cryptoSrcOffset = MV_16BIT_LE(sramBufOffset + cryptoOffset); -+ pCesaDesc->cryptoDstOffset = MV_16BIT_LE(sramBufOffset + cryptoOffset); -+ /* word 2 */ -+ pCesaDesc->cryptoDataLen = MV_16BIT_LE(cryptoLength); -+ /* word 3 */ -+ pCesaDesc->cryptoKeyOffset = MV_16BIT_LE((MV_U16)(cesaSramVirtPtr->sramSA.cryptoKey - -+ mvCesaSramAddrGet())); -+ /* word 4 */ -+ pCesaDesc->cryptoIvOffset = MV_16BIT_LE((MV_U16)(cesaSramVirtPtr->cryptoIV - -+ mvCesaSramAddrGet())); -+ pCesaDesc->cryptoIvBufOffset = MV_16BIT_LE(sramBufOffset + ivOffset); -+ } -+ -+ if( (config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ /* word 5 */ -+ pCesaDesc->macSrcOffset = MV_16BIT_LE(sramBufOffset + macOffset); -+ pCesaDesc->macTotalLen = MV_16BIT_LE(macTotalLen); -+ -+ /* word 6 */ -+ pCesaDesc->macDigestOffset = MV_16BIT_LE(sramBufOffset + digestOffset); -+ pCesaDesc->macDataLen = MV_16BIT_LE(macLength); -+ -+ /* word 7 */ -+ pCesaDesc->macInnerIvOffset = MV_16BIT_LE((MV_U16)(cesaSramVirtPtr->sramSA.macInnerIV - -+ mvCesaSramAddrGet())); -+ pCesaDesc->macOuterIvOffset = MV_16BIT_LE((MV_U16)(cesaSramVirtPtr->sramSA.macOuterIV - -+ mvCesaSramAddrGet())); -+ } -+ /* Prepare DMA descriptor to CESA descriptor from DRAM to SRAM */ -+ pDmaDesc->phySrcAdd = MV_32BIT_LE(mvCesaVirtToPhys(&pReq->cesaDescBuf, pCesaDesc)); -+ pDmaDesc->phyDestAdd = MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (MV_U8*)pSramDesc)); -+ pDmaDesc->byteCnt = MV_32BIT_LE(sizeof(MV_CESA_DESC) | BIT31); -+ -+ /* flush Source buffer */ -+ mvOsCacheFlush(NULL, pCesaDesc, sizeof(MV_CESA_DESC)); -+} -+ -+/******************************************************************************* -+* mvCesaSramSaUpdate - Move required SA information to SRAM if needed. -+* -+* DESCRIPTION: -+* Copy to SRAM values of the required SA. -+* -+* -+* INPUT: -+* short sid - Session ID needs SRAM Cache update -+* MV_DMA_DESC *pDmaDesc - Pointer to DMA descriptor used to -+* copy SA values from DRAM to SRAM. -+* -+* RETURN: -+* MV_OK - Cache entry for this SA copied to SRAM. -+* MV_NO_CHANGE - Cache entry for this SA already exist in SRAM -+* -+*******************************************************************************/ -+static INLINE void mvCesaSramSaUpdate(short sid, MV_DMA_DESC *pDmaDesc) -+{ -+ MV_CESA_SA *pSA = &pCesaSAD[sid]; -+ -+ /* Prepare DMA descriptor to Copy CACHE_SA from SA database in DRAM to SRAM */ -+ pDmaDesc->byteCnt = MV_32BIT_LE(sizeof(MV_CESA_SRAM_SA) | BIT31); -+ pDmaDesc->phySrcAdd = MV_32BIT_LE(mvCesaVirtToPhys(&cesaSramSaBuf, pSA->pSramSA)); -+ pDmaDesc->phyDestAdd = -+ MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (MV_U8*)&cesaSramVirtPtr->sramSA)); -+ -+ /* Source buffer is already flushed during OpenSession*/ -+ /*mvOsCacheFlush(NULL, &pSA->sramSA, sizeof(MV_CESA_SRAM_SA));*/ -+} -+ -+/******************************************************************************* -+* mvCesaDmaCopyPrepare - prepare DMA descriptor list to copy data presented by -+* Mbuf structure from DRAM to SRAM -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_CESA_MBUF* pMbuf - pointer to Mbuf structure contains request -+* data in DRAM -+* MV_U8* pSramBuf - pointer to buffer in SRAM where data should -+* be copied to. -+* MV_DMA_DESC* pDmaDesc - pointer to first DMA descriptor for this copy. -+* The function set number of DMA descriptors needed -+* to copy the copySize bytes from Mbuf. -+* MV_BOOL isToMbuf - Copy direction. -+* MV_TRUE means copy from SRAM buffer to Mbuf in DRAM. -+* MV_FALSE means copy from Mbuf in DRAM to SRAM buffer. -+* int offset - Offset in the Mbuf structure that copy should be -+* started from. -+* int copySize - Size of data should be copied. -+* -+* RETURN: -+* int - number of DMA descriptors used for the copy. -+* -+*******************************************************************************/ -+#ifndef MV_NETBSD -+static INLINE int mvCesaDmaCopyPrepare(MV_CESA_MBUF* pMbuf, MV_U8* pSramBuf, -+ MV_DMA_DESC* pDmaDesc, MV_BOOL isToMbuf, -+ int offset, int copySize, MV_BOOL skipFlush) -+{ -+ int bufOffset, bufSize, size, frag, i; -+ MV_U8* pBuf; -+ -+ i = 0; -+ -+ /* Calculate start place for copy: fragment number and offset in the fragment */ -+ frag = mvCesaMbufOffset(pMbuf, offset, &bufOffset); -+ bufSize = pMbuf->pFrags[frag].bufSize - bufOffset; -+ pBuf = pMbuf->pFrags[frag].bufVirtPtr + bufOffset; -+ -+ /* Size accumulate total copy size */ -+ size = 0; -+ -+ /* Create DMA lists to copy mBuf from pSrc to SRAM */ -+ while(size < copySize) -+ { -+ /* Find copy size for each DMA descriptor */ -+ bufSize = MV_MIN(bufSize, (copySize - size)); -+ pDmaDesc[i].byteCnt = MV_32BIT_LE(bufSize | BIT31); -+ if(isToMbuf) -+ { -+ pDmaDesc[i].phyDestAdd = MV_32BIT_LE(mvOsIoVirtToPhy(NULL, pBuf)); -+ pDmaDesc[i].phySrcAdd = -+ MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (pSramBuf + size))); -+ /* invalidate the buffer */ -+ if(skipFlush == MV_FALSE) -+ mvOsCacheInvalidate(NULL, pBuf, bufSize); -+ } -+ else -+ { -+ pDmaDesc[i].phySrcAdd = MV_32BIT_LE(mvOsIoVirtToPhy(NULL, pBuf)); -+ pDmaDesc[i].phyDestAdd = -+ MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (pSramBuf + size))); -+ /* flush the buffer */ -+ if(skipFlush == MV_FALSE) -+ mvOsCacheFlush(NULL, pBuf, bufSize); -+ } -+ -+ /* Count number of used DMA descriptors */ -+ i++; -+ size += bufSize; -+ -+ /* go to next fragment in the Mbuf */ -+ frag++; -+ pBuf = pMbuf->pFrags[frag].bufVirtPtr; -+ bufSize = pMbuf->pFrags[frag].bufSize; -+ } -+ return i; -+} -+#else /* MV_NETBSD */ -+static int mvCesaDmaCopyPrepare(MV_CESA_MBUF* pMbuf, MV_U8* pSramBuf, -+ MV_DMA_DESC* pDmaDesc, MV_BOOL isToMbuf, -+ int offset, int copySize, MV_BOOL skipFlush) -+{ -+ int bufOffset, bufSize, thisSize, size, frag, i; -+ MV_ULONG bufPhys, sramPhys; -+ MV_U8* pBuf; -+ -+ /* -+ * Calculate start place for copy: fragment number and offset in -+ * the fragment -+ */ -+ frag = mvCesaMbufOffset(pMbuf, offset, &bufOffset); -+ -+ /* -+ * Get SRAM physical address only once. We can update it in-place -+ * as we build the descriptor chain. -+ */ -+ sramPhys = mvCesaSramVirtToPhys(NULL, pSramBuf); -+ -+ /* -+ * 'size' accumulates total copy size, 'i' counts desccriptors. -+ */ -+ size = i = 0; -+ -+ /* Create DMA lists to copy mBuf from pSrc to SRAM */ -+ while (size < copySize) { -+ /* -+ * Calculate # of bytes to copy from the current fragment, -+ * and the pointer to the start of data -+ */ -+ bufSize = pMbuf->pFrags[frag].bufSize - bufOffset; -+ pBuf = pMbuf->pFrags[frag].bufVirtPtr + bufOffset; -+ bufOffset = 0; /* First frag may be non-zero */ -+ frag++; -+ -+ /* -+ * As long as there is data in the current fragment... -+ */ -+ while (bufSize > 0) { -+ /* -+ * Ensure we don't cross an MMU page boundary. -+ * XXX: This is NetBSD-specific, but it is a -+ * quick and dirty way to fix the problem. -+ * A true HAL would rely on the OS-specific -+ * driver to do this... -+ */ -+ thisSize = PAGE_SIZE - -+ (((MV_ULONG)pBuf) & (PAGE_SIZE - 1)); -+ thisSize = MV_MIN(bufSize, thisSize); -+ /* -+ * Make sure we don't copy more than requested -+ */ -+ if (thisSize > (copySize - size)) { -+ thisSize = copySize - size; -+ bufSize = 0; -+ } -+ -+ /* -+ * Physicall address of this fragment -+ */ -+ bufPhys = MV_32BIT_LE(mvOsIoVirtToPhy(NULL, pBuf)); -+ -+ /* -+ * Set up the descriptor -+ */ -+ pDmaDesc[i].byteCnt = MV_32BIT_LE(thisSize | BIT31); -+ if(isToMbuf) { -+ pDmaDesc[i].phyDestAdd = bufPhys; -+ pDmaDesc[i].phySrcAdd = MV_32BIT_LE(sramPhys); -+ /* invalidate the buffer */ -+ if(skipFlush == MV_FALSE) -+ mvOsCacheInvalidate(NULL, pBuf, thisSize); -+ } else { -+ pDmaDesc[i].phySrcAdd = bufPhys; -+ pDmaDesc[i].phyDestAdd = MV_32BIT_LE(sramPhys); -+ /* flush the buffer */ -+ if(skipFlush == MV_FALSE) -+ mvOsCacheFlush(NULL, pBuf, thisSize); -+ } -+ -+ pDmaDesc[i].phyNextDescPtr = -+ MV_32BIT_LE(mvOsIoVirtToPhy(NULL,(&pDmaDesc[i+1]))); -+ -+ /* flush the DMA desc */ -+ mvOsCacheFlush(NULL, &pDmaDesc[i], sizeof(MV_DMA_DESC)); -+ -+ /* Update state */ -+ bufSize -= thisSize; -+ sramPhys += thisSize; -+ pBuf += thisSize; -+ size += thisSize; -+ i++; -+ } -+ } -+ -+ return i; -+} -+#endif /* MV_NETBSD */ -+/******************************************************************************* -+* mvCesaHmacIvGet - Calculate Inner and Outter values from HMAC key -+* -+* DESCRIPTION: -+* This function calculate Inner and Outer values used for HMAC algorithm. -+* This operation allows improve performance fro the whole HMAC processing. -+* -+* INPUT: -+* MV_CESA_MAC_MODE macMode - Authentication mode: HMAC_MD5 or HMAC_SHA1. -+* unsigned char key[] - Pointer to HMAC key. -+* int keyLength - Size of HMAC key (maximum 64 bytes) -+* -+* OUTPUT: -+* unsigned char innerIV[] - HASH(key^inner) -+* unsigned char outerIV[] - HASH(key^outter) -+* -+* RETURN: None -+* -+*******************************************************************************/ -+static void mvCesaHmacIvGet(MV_CESA_MAC_MODE macMode, unsigned char key[], int keyLength, -+ unsigned char innerIV[], unsigned char outerIV[]) -+{ -+ unsigned char inner[MV_CESA_MAX_MAC_KEY_LENGTH]; -+ unsigned char outer[MV_CESA_MAX_MAC_KEY_LENGTH]; -+ int i, digestSize = 0; -+#if defined(MV_CPU_LE) || defined(MV_PPC) -+ MV_U32 swapped32, val32, *pVal32; -+#endif -+ for(i=0; ipFrags[frag].bufVirtPtr + fragOffset; -+ size = pMbuf->pFrags[frag].bufSize - fragOffset; -+ -+ /* Complete Inner part */ -+ while(macLeftSize > 0) -+ { -+ if(macLeftSize <= size) -+ { -+ mvSHA1Update(&ctx, pData, macLeftSize); -+ break; -+ } -+ mvSHA1Update(&ctx, pData, size); -+ macLeftSize -= size; -+ frag++; -+ pData = pMbuf->pFrags[frag].bufVirtPtr; -+ size = pMbuf->pFrags[frag].bufSize; -+ } -+ mvSHA1Final(pDigest, &ctx); -+/* -+ mvOsPrintf("mvCesaFragSha1Complete: pOuterIV=%p, macLeftSize=%d, macTotalSize=%d\n", -+ pOuterIV, macLeftSize, macTotalSize); -+ mvDebugMemDump(pDigest, MV_CESA_SHA1_DIGEST_SIZE, 1); -+*/ -+ -+ if(pOuterIV != NULL) -+ { -+ /* If HMAC - Complete Outer part */ -+ for(i=0; ipFrags[frag].bufVirtPtr + fragOffset; -+ size = pMbuf->pFrags[frag].bufSize - fragOffset; -+ -+ /* Complete Inner part */ -+ while(macLeftSize > 0) -+ { -+ if(macLeftSize <= size) -+ { -+ mvMD5Update(&ctx, pData, macLeftSize); -+ break; -+ } -+ mvMD5Update(&ctx, pData, size); -+ macLeftSize -= size; -+ frag++; -+ pData = pMbuf->pFrags[frag].bufVirtPtr; -+ size = pMbuf->pFrags[frag].bufSize; -+ } -+ mvMD5Final(pDigest, &ctx); -+ -+/* -+ mvOsPrintf("mvCesaFragMd5Complete: pOuterIV=%p, macLeftSize=%d, macTotalSize=%d\n", -+ pOuterIV, macLeftSize, macTotalSize); -+ mvDebugMemDump(pDigest, MV_CESA_MD5_DIGEST_SIZE, 1); -+*/ -+ if(pOuterIV != NULL) -+ { -+ /* Complete Outer part */ -+ for(i=0; ipCmd; -+ MV_U8* pDigest; -+ MV_CESA_MAC_MODE macMode; -+ MV_U8* pOuterIV = NULL; -+ -+ /* Copy data from Source fragment to Destination */ -+ if(pCmd->pSrc != pCmd->pDst) -+ { -+ mvCesaMbufCopy(pCmd->pDst, pReq->frags.bufOffset, -+ pCmd->pSrc, pReq->frags.bufOffset, macDataSize); -+ } -+ -+/* -+ mvCesaCopyFromMbuf(cesaSramVirtPtr->buf[0], pCmd->pSrc, pReq->frags.bufOffset, macDataSize); -+ mvCesaCopyToMbuf(cesaSramVirtPtr->buf[0], pCmd->pDst, pReq->frags.bufOffset, macDataSize); -+*/ -+ pDigest = (mvCesaSramAddrGet() + pReq->frags.newDigestOffset); -+ -+ macMode = (pSA->config & MV_CESA_MAC_MODE_MASK) >> MV_CESA_MAC_MODE_OFFSET; -+/* -+ mvOsPrintf("macDataSize=%d, macLength=%d, digestOffset=%d, macMode=%d\n", -+ macDataSize, pCmd->macLength, pCmd->digestOffset, macMode); -+*/ -+ switch(macMode) -+ { -+ case MV_CESA_MAC_HMAC_MD5: -+ pOuterIV = pSA->pSramSA->macOuterIV; -+ -+ case MV_CESA_MAC_MD5: -+ mvCesaFragMd5Complete(pCmd->pDst, pReq->frags.bufOffset, pOuterIV, -+ macDataSize, pCmd->macLength, pDigest); -+ break; -+ -+ case MV_CESA_MAC_HMAC_SHA1: -+ pOuterIV = pSA->pSramSA->macOuterIV; -+ -+ case MV_CESA_MAC_SHA1: -+ mvCesaFragSha1Complete(pCmd->pDst, pReq->frags.bufOffset, pOuterIV, -+ macDataSize, pCmd->macLength, pDigest); -+ break; -+ -+ default: -+ mvOsPrintf("mvCesaFragAuthComplete: Unexpected macMode %d\n", macMode); -+ return MV_BAD_PARAM; -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaCtrModeInit - -+* -+* DESCRIPTION: -+* -+* -+* INPUT: NONE -+* -+* -+* RETURN: -+* MV_CESA_COMMAND* -+* -+*******************************************************************************/ -+static MV_CESA_COMMAND* mvCesaCtrModeInit(void) -+{ -+ MV_CESA_MBUF *pMbuf; -+ MV_U8 *pBuf; -+ MV_CESA_COMMAND *pCmd; -+ -+ pBuf = mvOsMalloc(sizeof(MV_CESA_COMMAND) + -+ sizeof(MV_CESA_MBUF) + sizeof(MV_BUF_INFO) + 100); -+ if(pBuf == NULL) -+ { -+ mvOsPrintf("mvCesaSessionOpen: Can't allocate %u bytes for CTR Mode\n", -+ sizeof(MV_CESA_COMMAND) + sizeof(MV_CESA_MBUF) + sizeof(MV_BUF_INFO) ); -+ return NULL; -+ } -+ pCmd = (MV_CESA_COMMAND*)pBuf; -+ pBuf += sizeof(MV_CESA_COMMAND); -+ -+ pMbuf = (MV_CESA_MBUF*)pBuf; -+ pBuf += sizeof(MV_CESA_MBUF); -+ -+ pMbuf->pFrags = (MV_BUF_INFO*)pBuf; -+ -+ pMbuf->numFrags = 1; -+ pCmd->pSrc = pMbuf; -+ pCmd->pDst = pMbuf; -+/* -+ mvOsPrintf("CtrModeInit: pCmd=%p, pSrc=%p, pDst=%p, pFrags=%p\n", -+ pCmd, pCmd->pSrc, pCmd->pDst, -+ pMbuf->pFrags); -+*/ -+ return pCmd; -+} -+ -+/******************************************************************************* -+* mvCesaCtrModePrepare - -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_CESA_COMMAND *pCtrModeCmd, MV_CESA_COMMAND *pCmd -+* -+* RETURN: -+* MV_STATUS -+* -+*******************************************************************************/ -+static MV_STATUS mvCesaCtrModePrepare(MV_CESA_COMMAND *pCtrModeCmd, MV_CESA_COMMAND *pCmd) -+{ -+ MV_CESA_MBUF *pMbuf; -+ MV_U8 *pBuf, *pIV; -+ MV_U32 counter, *pCounter; -+ int cryptoSize = MV_ALIGN_UP(pCmd->cryptoLength, MV_CESA_AES_BLOCK_SIZE); -+/* -+ mvOsPrintf("CtrModePrepare: pCmd=%p, pCtrSrc=%p, pCtrDst=%p, pOrgCmd=%p, pOrgSrc=%p, pOrgDst=%p\n", -+ pCmd, pCmd->pSrc, pCmd->pDst, -+ pCtrModeCmd, pCtrModeCmd->pSrc, pCtrModeCmd->pDst); -+*/ -+ pMbuf = pCtrModeCmd->pSrc; -+ -+ /* Allocate buffer for Key stream */ -+ pBuf = mvOsIoCachedMalloc(cesaOsHandle,cryptoSize, -+ &pMbuf->pFrags[0].bufPhysAddr, -+ &pMbuf->pFrags[0].memHandle); -+ if(pBuf == NULL) -+ { -+ mvOsPrintf("mvCesaCtrModePrepare: Can't allocate %d bytes\n", cryptoSize); -+ return MV_OUT_OF_CPU_MEM; -+ } -+ memset(pBuf, 0, cryptoSize); -+ mvOsCacheFlush(NULL, pBuf, cryptoSize); -+ -+ pMbuf->pFrags[0].bufVirtPtr = pBuf; -+ pMbuf->mbufSize = cryptoSize; -+ pMbuf->pFrags[0].bufSize = cryptoSize; -+ -+ pCtrModeCmd->pReqPrv = pCmd->pReqPrv; -+ pCtrModeCmd->sessionId = pCmd->sessionId; -+ -+ /* ivFromUser and ivOffset are don't care */ -+ pCtrModeCmd->cryptoOffset = 0; -+ pCtrModeCmd->cryptoLength = cryptoSize; -+ -+ /* digestOffset, macOffset and macLength are don't care */ -+ -+ mvCesaCopyFromMbuf(pBuf, pCmd->pSrc, pCmd->ivOffset, MV_CESA_AES_BLOCK_SIZE); -+ pCounter = (MV_U32*)(pBuf + (MV_CESA_AES_BLOCK_SIZE - sizeof(counter))); -+ counter = *pCounter; -+ counter = MV_32BIT_BE(counter); -+ pIV = pBuf; -+ cryptoSize -= MV_CESA_AES_BLOCK_SIZE; -+ -+ /* fill key stream */ -+ while(cryptoSize > 0) -+ { -+ pBuf += MV_CESA_AES_BLOCK_SIZE; -+ memcpy(pBuf, pIV, MV_CESA_AES_BLOCK_SIZE - sizeof(counter)); -+ pCounter = (MV_U32*)(pBuf + (MV_CESA_AES_BLOCK_SIZE - sizeof(counter))); -+ counter++; -+ *pCounter = MV_32BIT_BE(counter); -+ cryptoSize -= MV_CESA_AES_BLOCK_SIZE; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaCtrModeComplete - -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_CESA_COMMAND *pOrgCmd, MV_CESA_COMMAND *pCmd -+* -+* RETURN: -+* MV_STATUS -+* -+*******************************************************************************/ -+static MV_STATUS mvCesaCtrModeComplete(MV_CESA_COMMAND *pOrgCmd, MV_CESA_COMMAND *pCmd) -+{ -+ int srcFrag, dstFrag, srcOffset, dstOffset, keyOffset, srcSize, dstSize; -+ int cryptoSize = pCmd->cryptoLength; -+ MV_U8 *pSrc, *pDst, *pKey; -+ MV_STATUS status = MV_OK; -+/* -+ mvOsPrintf("CtrModeComplete: pCmd=%p, pCtrSrc=%p, pCtrDst=%p, pOrgCmd=%p, pOrgSrc=%p, pOrgDst=%p\n", -+ pCmd, pCmd->pSrc, pCmd->pDst, -+ pOrgCmd, pOrgCmd->pSrc, pOrgCmd->pDst); -+*/ -+ /* XOR source data with key stream to destination data */ -+ pKey = pCmd->pDst->pFrags[0].bufVirtPtr; -+ keyOffset = 0; -+ -+ if( (pOrgCmd->pSrc != pOrgCmd->pDst) && -+ (pOrgCmd->cryptoOffset > 0) ) -+ { -+ /* Copy Prefix from source buffer to destination buffer */ -+ -+ status = mvCesaMbufCopy(pOrgCmd->pDst, 0, -+ pOrgCmd->pSrc, 0, pOrgCmd->cryptoOffset); -+/* -+ status = mvCesaCopyFromMbuf(tempBuf, pOrgCmd->pSrc, -+ 0, pOrgCmd->cryptoOffset); -+ status = mvCesaCopyToMbuf(tempBuf, pOrgCmd->pDst, -+ 0, pOrgCmd->cryptoOffset); -+*/ -+ } -+ -+ srcFrag = mvCesaMbufOffset(pOrgCmd->pSrc, pOrgCmd->cryptoOffset, &srcOffset); -+ pSrc = pOrgCmd->pSrc->pFrags[srcFrag].bufVirtPtr; -+ srcSize = pOrgCmd->pSrc->pFrags[srcFrag].bufSize; -+ -+ dstFrag = mvCesaMbufOffset(pOrgCmd->pDst, pOrgCmd->cryptoOffset, &dstOffset); -+ pDst = pOrgCmd->pDst->pFrags[dstFrag].bufVirtPtr; -+ dstSize = pOrgCmd->pDst->pFrags[dstFrag].bufSize; -+ -+ while(cryptoSize > 0) -+ { -+ pDst[dstOffset] = (pSrc[srcOffset] ^ pKey[keyOffset]); -+ -+ cryptoSize--; -+ dstOffset++; -+ srcOffset++; -+ keyOffset++; -+ -+ if(srcOffset >= srcSize) -+ { -+ srcFrag++; -+ srcOffset = 0; -+ pSrc = pOrgCmd->pSrc->pFrags[srcFrag].bufVirtPtr; -+ srcSize = pOrgCmd->pSrc->pFrags[srcFrag].bufSize; -+ } -+ -+ if(dstOffset >= dstSize) -+ { -+ dstFrag++; -+ dstOffset = 0; -+ pDst = pOrgCmd->pDst->pFrags[dstFrag].bufVirtPtr; -+ dstSize = pOrgCmd->pDst->pFrags[dstFrag].bufSize; -+ } -+ } -+ -+ if(pOrgCmd->pSrc != pOrgCmd->pDst) -+ { -+ /* Copy Suffix from source buffer to destination buffer */ -+ srcOffset = pOrgCmd->cryptoOffset + pOrgCmd->cryptoLength; -+ -+ if( (pOrgCmd->pDst->mbufSize - srcOffset) > 0) -+ { -+ status = mvCesaMbufCopy(pOrgCmd->pDst, srcOffset, -+ pOrgCmd->pSrc, srcOffset, -+ pOrgCmd->pDst->mbufSize - srcOffset); -+ } -+ -+/* -+ status = mvCesaCopyFromMbuf(tempBuf, pOrgCmd->pSrc, -+ srcOffset, pOrgCmd->pSrc->mbufSize - srcOffset); -+ status = mvCesaCopyToMbuf(tempBuf, pOrgCmd->pDst, -+ srcOffset, pOrgCmd->pDst->mbufSize - srcOffset); -+*/ -+ } -+ -+ /* Free buffer used for Key stream */ -+ mvOsIoCachedFree(cesaOsHandle,pCmd->pDst->pFrags[0].bufSize, -+ pCmd->pDst->pFrags[0].bufPhysAddr, -+ pCmd->pDst->pFrags[0].bufVirtPtr, -+ pCmd->pDst->pFrags[0].memHandle); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaCtrModeFinish - -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_CESA_COMMAND* pCmd -+* -+* RETURN: -+* MV_STATUS -+* -+*******************************************************************************/ -+static void mvCesaCtrModeFinish(MV_CESA_COMMAND* pCmd) -+{ -+ mvOsFree(pCmd); -+} -+ -+/******************************************************************************* -+* mvCesaParamCheck - -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, MV_U8* pFixOffset -+* -+* RETURN: -+* MV_STATUS -+* -+*******************************************************************************/ -+static MV_STATUS mvCesaParamCheck(MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, -+ MV_U8* pFixOffset) -+{ -+ MV_U8 fixOffset = 0xFF; -+ -+ /* Check AUTH operation parameters */ -+ if( ((pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET)) ) -+ { -+ /* MAC offset should be at least 4 byte aligned */ -+ if( MV_IS_NOT_ALIGN(pCmd->macOffset, 4) ) -+ { -+ mvOsPrintf("mvCesaAction: macOffset %d must be 4 byte aligned\n", -+ pCmd->macOffset); -+ return MV_BAD_PARAM; -+ } -+ /* Digest offset must be 4 byte aligned */ -+ if( MV_IS_NOT_ALIGN(pCmd->digestOffset, 4) ) -+ { -+ mvOsPrintf("mvCesaAction: digestOffset %d must be 4 byte aligned\n", -+ pCmd->digestOffset); -+ return MV_BAD_PARAM; -+ } -+ /* In addition all offsets should be the same alignment: 8 or 4 */ -+ if(fixOffset == 0xFF) -+ { -+ fixOffset = (pCmd->macOffset % 8); -+ } -+ else -+ { -+ if( (pCmd->macOffset % 8) != fixOffset) -+ { -+ mvOsPrintf("mvCesaAction: macOffset %d mod 8 must be equal %d\n", -+ pCmd->macOffset, fixOffset); -+ return MV_BAD_PARAM; -+ } -+ } -+ if( (pCmd->digestOffset % 8) != fixOffset) -+ { -+ mvOsPrintf("mvCesaAction: digestOffset %d mod 8 must be equal %d\n", -+ pCmd->digestOffset, fixOffset); -+ return MV_BAD_PARAM; -+ } -+ } -+ /* Check CRYPTO operation parameters */ -+ if( ((pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) ) -+ { -+ /* CryptoOffset should be at least 4 byte aligned */ -+ if( MV_IS_NOT_ALIGN(pCmd->cryptoOffset, 4) ) -+ { -+ mvOsPrintf("CesaAction: cryptoOffset=%d must be 4 byte aligned\n", -+ pCmd->cryptoOffset); -+ return MV_BAD_PARAM; -+ } -+ /* cryptoLength should be the whole number of blocks */ -+ if( MV_IS_NOT_ALIGN(pCmd->cryptoLength, pSA->cryptoBlockSize) ) -+ { -+ mvOsPrintf("mvCesaAction: cryptoLength=%d must be %d byte aligned\n", -+ pCmd->cryptoLength, pSA->cryptoBlockSize); -+ return MV_BAD_PARAM; -+ } -+ if(fixOffset == 0xFF) -+ { -+ fixOffset = (pCmd->cryptoOffset % 8); -+ } -+ else -+ { -+ /* In addition all offsets should be the same alignment: 8 or 4 */ -+ if( (pCmd->cryptoOffset % 8) != fixOffset) -+ { -+ mvOsPrintf("mvCesaAction: cryptoOffset %d mod 8 must be equal %d \n", -+ pCmd->cryptoOffset, fixOffset); -+ return MV_BAD_PARAM; -+ } -+ } -+ -+ /* check for CBC mode */ -+ if(pSA->cryptoIvSize > 0) -+ { -+ /* cryptoIV must not be part of CryptoLength */ -+ if( ((pCmd->ivOffset + pSA->cryptoIvSize) > pCmd->cryptoOffset) && -+ (pCmd->ivOffset < (pCmd->cryptoOffset + pCmd->cryptoLength)) ) -+ { -+ mvOsPrintf("mvCesaFragParamCheck: cryptoIvOffset (%d) is part of cryptoLength (%d+%d)\n", -+ pCmd->ivOffset, pCmd->macOffset, pCmd->macLength); -+ return MV_BAD_PARAM; -+ } -+ -+ /* ivOffset must be 4 byte aligned */ -+ if( MV_IS_NOT_ALIGN(pCmd->ivOffset, 4) ) -+ { -+ mvOsPrintf("CesaAction: ivOffset=%d must be 4 byte aligned\n", -+ pCmd->ivOffset); -+ return MV_BAD_PARAM; -+ } -+ /* In addition all offsets should be the same alignment: 8 or 4 */ -+ if( (pCmd->ivOffset % 8) != fixOffset) -+ { -+ mvOsPrintf("mvCesaAction: ivOffset %d mod 8 must be %d\n", -+ pCmd->ivOffset, fixOffset); -+ return MV_BAD_PARAM; -+ } -+ } -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaFragParamCheck - -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd -+* -+* RETURN: -+* MV_STATUS -+* -+*******************************************************************************/ -+static MV_STATUS mvCesaFragParamCheck(MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd) -+{ -+ int offset; -+ -+ if( ((pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET)) ) -+ { -+ /* macOffset must be less that SRAM buffer size */ -+ if(pCmd->macOffset > (sizeof(cesaSramVirtPtr->buf) - MV_CESA_AUTH_BLOCK_SIZE)) -+ { -+ mvOsPrintf("mvCesaFragParamCheck: macOffset is too large (%d)\n", -+ pCmd->macOffset); -+ return MV_BAD_PARAM; -+ } -+ /* macOffset+macSize must be more than mbufSize - SRAM buffer size */ -+ if( ((pCmd->macOffset + pCmd->macLength) > pCmd->pSrc->mbufSize) || -+ ((pCmd->pSrc->mbufSize - (pCmd->macOffset + pCmd->macLength)) >= -+ sizeof(cesaSramVirtPtr->buf)) ) -+ { -+ mvOsPrintf("mvCesaFragParamCheck: macLength is too large (%d), mbufSize=%d\n", -+ pCmd->macLength, pCmd->pSrc->mbufSize); -+ return MV_BAD_PARAM; -+ } -+ } -+ -+ if( ((pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) ) -+ { -+ /* cryptoOffset must be less that SRAM buffer size */ -+ /* 4 for possible fixOffset */ -+ if( (pCmd->cryptoOffset + 4) > (sizeof(cesaSramVirtPtr->buf) - pSA->cryptoBlockSize)) -+ { -+ mvOsPrintf("mvCesaFragParamCheck: cryptoOffset is too large (%d)\n", -+ pCmd->cryptoOffset); -+ return MV_BAD_PARAM; -+ } -+ -+ /* cryptoOffset+cryptoSize must be more than mbufSize - SRAM buffer size */ -+ if( ((pCmd->cryptoOffset + pCmd->cryptoLength) > pCmd->pSrc->mbufSize) || -+ ((pCmd->pSrc->mbufSize - (pCmd->cryptoOffset + pCmd->cryptoLength)) >= -+ (sizeof(cesaSramVirtPtr->buf) - pSA->cryptoBlockSize)) ) -+ { -+ mvOsPrintf("mvCesaFragParamCheck: cryptoLength is too large (%d), mbufSize=%d\n", -+ pCmd->cryptoLength, pCmd->pSrc->mbufSize); -+ return MV_BAD_PARAM; -+ } -+ } -+ -+ /* When MAC_THEN_CRYPTO or CRYPTO_THEN_MAC */ -+ if( ((pSA->config & MV_CESA_OPERATION_MASK) == -+ (MV_CESA_MAC_THEN_CRYPTO << MV_CESA_OPERATION_OFFSET)) || -+ ((pSA->config & MV_CESA_OPERATION_MASK) == -+ (MV_CESA_CRYPTO_THEN_MAC << MV_CESA_OPERATION_OFFSET)) ) -+ { -+ if( (mvCtrlModelGet() == MV_5182_DEV_ID) || -+ ( (mvCtrlModelGet() == MV_5181_DEV_ID) && -+ (mvCtrlRevGet() >= MV_5181L_A0_REV) && -+ (pCmd->macLength >= (1 << 14)) ) ) -+ { -+ return MV_NOT_ALLOWED; -+ } -+ -+ /* abs(cryptoOffset-macOffset) must be aligned cryptoBlockSize */ -+ if(pCmd->cryptoOffset > pCmd->macOffset) -+ { -+ offset = pCmd->cryptoOffset - pCmd->macOffset; -+ } -+ else -+ { -+ offset = pCmd->macOffset - pCmd->cryptoOffset; -+ } -+ -+ if( MV_IS_NOT_ALIGN(offset, pSA->cryptoBlockSize) ) -+ { -+/* -+ mvOsPrintf("mvCesaFragParamCheck: (cryptoOffset - macOffset) must be %d byte aligned\n", -+ pSA->cryptoBlockSize); -+*/ -+ return MV_NOT_ALLOWED; -+ } -+ /* Digest must not be part of CryptoLength */ -+ if( ((pCmd->digestOffset + pSA->digestSize) > pCmd->cryptoOffset) && -+ (pCmd->digestOffset < (pCmd->cryptoOffset + pCmd->cryptoLength)) ) -+ { -+/* -+ mvOsPrintf("mvCesaFragParamCheck: digestOffset (%d) is part of cryptoLength (%d+%d)\n", -+ pCmd->digestOffset, pCmd->cryptoOffset, pCmd->cryptoLength); -+*/ -+ return MV_NOT_ALLOWED; -+ } -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaFragSizeFind - -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, -+* int cryptoOffset, int macOffset, -+* -+* OUTPUT: -+* int* pCopySize, int* pCryptoDataSize, int* pMacDataSize -+* -+* RETURN: -+* MV_STATUS -+* -+*******************************************************************************/ -+static void mvCesaFragSizeFind(MV_CESA_SA* pSA, MV_CESA_REQ* pReq, -+ int cryptoOffset, int macOffset, -+ int* pCopySize, int* pCryptoDataSize, int* pMacDataSize) -+{ -+ MV_CESA_COMMAND *pCmd = pReq->pCmd; -+ int cryptoDataSize, macDataSize, copySize; -+ -+ cryptoDataSize = macDataSize = 0; -+ copySize = *pCopySize; -+ -+ if( (pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ cryptoDataSize = MV_MIN( (copySize - cryptoOffset), -+ (pCmd->cryptoLength - (pReq->frags.cryptoSize + 1)) ); -+ -+ /* cryptoSize for each fragment must be the whole number of blocksSize */ -+ if( MV_IS_NOT_ALIGN(cryptoDataSize, pSA->cryptoBlockSize) ) -+ { -+ cryptoDataSize = MV_ALIGN_DOWN(cryptoDataSize, pSA->cryptoBlockSize); -+ copySize = cryptoOffset + cryptoDataSize; -+ } -+ } -+ if( (pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ macDataSize = MV_MIN( (copySize - macOffset), -+ (pCmd->macLength - (pReq->frags.macSize + 1))); -+ -+ /* macSize for each fragment (except last) must be the whole number of blocksSize */ -+ if( MV_IS_NOT_ALIGN(macDataSize, MV_CESA_AUTH_BLOCK_SIZE) ) -+ { -+ macDataSize = MV_ALIGN_DOWN(macDataSize, MV_CESA_AUTH_BLOCK_SIZE); -+ copySize = macOffset + macDataSize; -+ } -+ cryptoDataSize = copySize - cryptoOffset; -+ } -+ *pCopySize = copySize; -+ -+ if(pCryptoDataSize != NULL) -+ *pCryptoDataSize = cryptoDataSize; -+ -+ if(pMacDataSize != NULL) -+ *pMacDataSize = macDataSize; -+} -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvCesa.h linux-3.0.4/crypto/ocf/kirkwood/cesa/mvCesa.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvCesa.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/cesa/mvCesa.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,412 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+/******************************************************************************* -+* mvCesa.h - Header File for Cryptographic Engines and Security Accelerator -+* -+* DESCRIPTION: -+* This header file contains macros typedefs and function declaration for -+* the Marvell Cryptographic Engines and Security Accelerator. -+* -+*******************************************************************************/ -+ -+#ifndef __mvCesa_h__ -+#define __mvCesa_h__ -+ -+#include "mvOs.h" -+#include "mvCommon.h" -+#include "mvDebug.h" -+ -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+ -+#include "cesa/mvMD5.h" -+#include "cesa/mvSHA1.h" -+ -+#include "cesa/mvCesa.h" -+#include "cesa/AES/mvAes.h" -+#include "mvSysHwConfig.h" -+ -+#ifdef MV_INCLUDE_IDMA -+#include "idma/mvIdma.h" -+#include "idma/mvIdmaRegs.h" -+#else -+/* Redefine MV_DMA_DESC structure */ -+typedef struct _mvDmaDesc -+{ -+ MV_U32 byteCnt; /* The total number of bytes to transfer */ -+ MV_U32 phySrcAdd; /* The physical source address */ -+ MV_U32 phyDestAdd; /* The physical destination address */ -+ MV_U32 phyNextDescPtr; /* If we are using chain mode DMA transfer, */ -+ /* then this pointer should point to the */ -+ /* physical address of the next descriptor, */ -+ /* otherwise it should be NULL. */ -+}MV_DMA_DESC; -+#endif /* MV_INCLUDE_IDMA */ -+ -+#include "cesa/mvCesaRegs.h" -+ -+#define MV_CESA_AUTH_BLOCK_SIZE 64 /* bytes */ -+ -+#define MV_CESA_MD5_DIGEST_SIZE 16 /* bytes */ -+#define MV_CESA_SHA1_DIGEST_SIZE 20 /* bytes */ -+ -+#define MV_CESA_MAX_DIGEST_SIZE MV_CESA_SHA1_DIGEST_SIZE -+ -+#define MV_CESA_DES_KEY_LENGTH 8 /* bytes = 64 bits */ -+#define MV_CESA_3DES_KEY_LENGTH 24 /* bytes = 192 bits */ -+#define MV_CESA_AES_128_KEY_LENGTH 16 /* bytes = 128 bits */ -+#define MV_CESA_AES_192_KEY_LENGTH 24 /* bytes = 192 bits */ -+#define MV_CESA_AES_256_KEY_LENGTH 32 /* bytes = 256 bits */ -+ -+#define MV_CESA_MAX_CRYPTO_KEY_LENGTH MV_CESA_AES_256_KEY_LENGTH -+ -+#define MV_CESA_DES_BLOCK_SIZE 8 /* bytes = 64 bits */ -+#define MV_CESA_3DES_BLOCK_SIZE 8 /* bytes = 64 bits */ -+ -+#define MV_CESA_AES_BLOCK_SIZE 16 /* bytes = 128 bits */ -+ -+#define MV_CESA_MAX_IV_LENGTH MV_CESA_AES_BLOCK_SIZE -+ -+#define MV_CESA_MAX_MAC_KEY_LENGTH 64 /* bytes */ -+ -+typedef struct -+{ -+ MV_U8 cryptoKey[MV_CESA_MAX_CRYPTO_KEY_LENGTH]; -+ MV_U8 macKey[MV_CESA_MAX_MAC_KEY_LENGTH]; -+ MV_CESA_OPERATION operation; -+ MV_CESA_DIRECTION direction; -+ MV_CESA_CRYPTO_ALG cryptoAlgorithm; -+ MV_CESA_CRYPTO_MODE cryptoMode; -+ MV_U8 cryptoKeyLength; -+ MV_CESA_MAC_MODE macMode; -+ MV_U8 macKeyLength; -+ MV_U8 digestSize; -+ -+} MV_CESA_OPEN_SESSION; -+ -+typedef struct -+{ -+ MV_BUF_INFO *pFrags; -+ MV_U16 numFrags; -+ MV_U16 mbufSize; -+ -+} MV_CESA_MBUF; -+ -+typedef struct -+{ -+ void* pReqPrv; /* instead of reqId */ -+ MV_U32 retCode; -+ MV_16 sessionId; -+ -+} MV_CESA_RESULT; -+ -+typedef void (*MV_CESA_CALLBACK) (MV_CESA_RESULT* pResult); -+ -+ -+typedef struct -+{ -+ void* pReqPrv; /* instead of reqId */ -+ MV_CESA_MBUF* pSrc; -+ MV_CESA_MBUF* pDst; -+ MV_CESA_CALLBACK* pFuncCB; -+ MV_16 sessionId; -+ MV_U16 ivFromUser; -+ MV_U16 ivOffset; -+ MV_U16 cryptoOffset; -+ MV_U16 cryptoLength; -+ MV_U16 digestOffset; -+ MV_U16 macOffset; -+ MV_U16 macLength; -+ MV_BOOL skipFlush; -+} MV_CESA_COMMAND; -+ -+ -+ -+MV_STATUS mvCesaHalInit (int numOfSession, int queueDepth, char* pSramBase, MV_U32 cryptEngBase, void *osHandle); -+MV_STATUS mvCesaFinish (void); -+MV_STATUS mvCesaSessionOpen(MV_CESA_OPEN_SESSION *pSession, short* pSid); -+MV_STATUS mvCesaSessionClose(short sid); -+MV_STATUS mvCesaCryptoIvSet(MV_U8* pIV, int ivSize); -+ -+MV_STATUS mvCesaAction (MV_CESA_COMMAND* pCmd); -+ -+MV_U32 mvCesaInProcessGet(void); -+MV_STATUS mvCesaReadyDispatch(void); -+MV_STATUS mvCesaReadyGet(MV_CESA_RESULT* pResult); -+MV_BOOL mvCesaIsReady(void); -+ -+int mvCesaMbufOffset(MV_CESA_MBUF* pMbuf, int offset, int* pBufOffset); -+MV_STATUS mvCesaCopyFromMbuf(MV_U8* pDst, MV_CESA_MBUF* pSrcMbuf, -+ int offset, int size); -+MV_STATUS mvCesaCopyToMbuf(MV_U8* pSrc, MV_CESA_MBUF* pDstMbuf, -+ int offset, int size); -+MV_STATUS mvCesaMbufCopy(MV_CESA_MBUF* pMbufDst, int dstMbufOffset, -+ MV_CESA_MBUF* pMbufSrc, int srcMbufOffset, int size); -+ -+/********** Debug functions ********/ -+ -+void mvCesaDebugMbuf(const char* str, MV_CESA_MBUF *pMbuf, int offset, int size); -+void mvCesaDebugSA(short sid, int mode); -+void mvCesaDebugStats(void); -+void mvCesaDebugStatsClear(void); -+void mvCesaDebugRegs(void); -+void mvCesaDebugStatus(void); -+void mvCesaDebugQueue(int mode); -+void mvCesaDebugSram(int mode); -+void mvCesaDebugSAD(int mode); -+ -+ -+/******** CESA Private definitions ********/ -+#if (MV_CESA_VERSION >= 2) -+#if (MV_CACHE_COHERENCY == MV_CACHE_COHER_SW) -+#define MV_CESA_TDMA_CTRL_VALUE MV_CESA_TDMA_DST_BURST_MASK(MV_CESA_TDMA_BURST_128B) \ -+ | MV_CESA_TDMA_SRC_BURST_MASK(MV_CESA_TDMA_BURST_128B) \ -+ | MV_CESA_TDMA_OUTSTAND_READ_EN_MASK \ -+ | MV_CESA_TDMA_NO_BYTE_SWAP_MASK \ -+ | MV_CESA_TDMA_ENABLE_MASK -+#else -+#define MV_CESA_TDMA_CTRL_VALUE MV_CESA_TDMA_DST_BURST_MASK(MV_CESA_TDMA_BURST_32B) \ -+ | MV_CESA_TDMA_SRC_BURST_MASK(MV_CESA_TDMA_BURST_128B) \ -+ /*| MV_CESA_TDMA_OUTSTAND_READ_EN_MASK */\ -+ | MV_CESA_TDMA_ENABLE_MASK -+ -+#endif -+#else -+#define MV_CESA_IDMA_CTRL_LOW_VALUE ICCLR_DST_BURST_LIM_128BYTE \ -+ | ICCLR_SRC_BURST_LIM_128BYTE \ -+ | ICCLR_INT_MODE_MASK \ -+ | ICCLR_BLOCK_MODE \ -+ | ICCLR_CHAN_ENABLE \ -+ | ICCLR_DESC_MODE_16M -+#endif /* MV_CESA_VERSION >= 2 */ -+ -+#define MV_CESA_MAX_PKT_SIZE (64 * 1024) -+#define MV_CESA_MAX_MBUF_FRAGS 20 -+ -+#define MV_CESA_MAX_REQ_FRAGS ( (MV_CESA_MAX_PKT_SIZE / MV_CESA_MAX_BUF_SIZE) + 1) -+ -+#define MV_CESA_MAX_DMA_DESC (MV_CESA_MAX_MBUF_FRAGS*2 + 5) -+ -+#define MAX_CESA_CHAIN_LENGTH 20 -+ -+typedef enum -+{ -+ MV_CESA_IDLE = 0, -+ MV_CESA_PENDING, -+ MV_CESA_PROCESS, -+ MV_CESA_READY, -+#if (MV_CESA_VERSION >= 3) -+ MV_CESA_CHAIN, -+#endif -+} MV_CESA_STATE; -+ -+ -+/* Session database */ -+ -+/* Map of Key materials of the session in SRAM. -+ * Each field must be 8 byte aligned -+ * Total size: 32 + 24 + 24 = 80 bytes -+ */ -+typedef struct -+{ -+ MV_U8 cryptoKey[MV_CESA_MAX_CRYPTO_KEY_LENGTH]; -+ MV_U8 macInnerIV[MV_CESA_MAX_DIGEST_SIZE]; -+ MV_U8 reservedInner[4]; -+ MV_U8 macOuterIV[MV_CESA_MAX_DIGEST_SIZE]; -+ MV_U8 reservedOuter[4]; -+ -+} MV_CESA_SRAM_SA; -+ -+typedef struct -+{ -+ MV_CESA_SRAM_SA* pSramSA; -+ MV_U32 config; -+ MV_U8 cryptoKeyLength; -+ MV_U8 cryptoIvSize; -+ MV_U8 cryptoBlockSize; -+ MV_U8 digestSize; -+ MV_U8 macKeyLength; -+ MV_U8 valid; -+ MV_U8 ctrMode; -+ MV_U32 count; -+ -+} MV_CESA_SA; -+ -+/* DMA list management */ -+typedef struct -+{ -+ MV_DMA_DESC* pDmaFirst; -+ MV_DMA_DESC* pDmaLast; -+ -+} MV_CESA_DMA; -+ -+ -+typedef struct -+{ -+ MV_U8 numFrag; -+ MV_U8 nextFrag; -+ int bufOffset; -+ int cryptoSize; -+ int macSize; -+ int newDigestOffset; -+ MV_U8 orgDigest[MV_CESA_MAX_DIGEST_SIZE]; -+ -+} MV_CESA_FRAGS; -+ -+/* Request queue */ -+typedef struct -+{ -+ MV_U8 state; -+ MV_U8 fragMode; -+ MV_U8 fixOffset; -+ MV_CESA_COMMAND* pCmd; -+ MV_CESA_COMMAND* pOrgCmd; -+ MV_BUF_INFO dmaDescBuf; -+ MV_CESA_DMA dma[MV_CESA_MAX_REQ_FRAGS]; -+ MV_BUF_INFO cesaDescBuf; -+ MV_CESA_DESC* pCesaDesc; -+ MV_CESA_FRAGS frags; -+ -+ -+} MV_CESA_REQ; -+ -+ -+/* SRAM map */ -+/* Total SRAM size calculation */ -+/* SRAM size = -+ * MV_CESA_MAX_BUF_SIZE + -+ * sizeof(MV_CESA_DESC) + -+ * MV_CESA_MAX_IV_LENGTH + -+ * MV_CESA_MAX_IV_LENGTH + -+ * MV_CESA_MAX_DIGEST_SIZE + -+ * sizeof(MV_CESA_SRAM_SA) -+ * = 1600 + 32 + 16 + 16 + 24 + 80 + 280 (reserved) = 2048 bytes -+ * = 3200 + 32 + 16 + 16 + 24 + 80 + 728 (reserved) = 4096 bytes -+ */ -+typedef struct -+{ -+ MV_U8 buf[MV_CESA_MAX_BUF_SIZE]; -+ MV_CESA_DESC desc; -+ MV_U8 cryptoIV[MV_CESA_MAX_IV_LENGTH]; -+ MV_U8 tempCryptoIV[MV_CESA_MAX_IV_LENGTH]; -+ MV_U8 tempDigest[MV_CESA_MAX_DIGEST_SIZE+4]; -+ MV_CESA_SRAM_SA sramSA; -+ -+} MV_CESA_SRAM_MAP; -+ -+ -+typedef struct -+{ -+ MV_U32 openedCount; -+ MV_U32 closedCount; -+ MV_U32 fragCount; -+ MV_U32 reqCount; -+ MV_U32 maxReqCount; -+ MV_U32 procCount; -+ MV_U32 readyCount; -+ MV_U32 notReadyCount; -+ MV_U32 startCount; -+#if (MV_CESA_VERSION >= 3) -+ MV_U32 maxChainUsage; -+#endif -+ -+} MV_CESA_STATS; -+ -+ -+/* External variables */ -+ -+extern MV_CESA_STATS cesaStats; -+extern MV_CESA_FRAGS cesaFrags; -+ -+extern MV_BUF_INFO cesaSramSaBuf; -+ -+extern MV_CESA_SA* pCesaSAD; -+extern MV_U16 cesaMaxSA; -+ -+extern MV_CESA_REQ* pCesaReqFirst; -+extern MV_CESA_REQ* pCesaReqLast; -+extern MV_CESA_REQ* pCesaReqEmpty; -+extern MV_CESA_REQ* pCesaReqProcess; -+extern int cesaQueueDepth; -+extern int cesaReqResources; -+#if (MV_CESA_VERSION>= 3) -+extern MV_U32 cesaChainLength; -+#endif -+ -+extern MV_CESA_SRAM_MAP* cesaSramVirtPtr; -+extern MV_U32 cesaSramPhysAddr; -+ -+static INLINE MV_ULONG mvCesaVirtToPhys(MV_BUF_INFO* pBufInfo, void* pVirt) -+{ -+ return (pBufInfo->bufPhysAddr + ((MV_U8*)pVirt - pBufInfo->bufVirtPtr)); -+} -+ -+/* Additional DEBUG functions */ -+void mvCesaDebugSramSA(MV_CESA_SRAM_SA* pSramSA, int mode); -+void mvCesaDebugCmd(MV_CESA_COMMAND* pCmd, int mode); -+void mvCesaDebugDescriptor(MV_CESA_DESC* pDesc); -+ -+ -+ -+#endif /* __mvCesa_h__ */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvCesaDebug.c linux-3.0.4/crypto/ocf/kirkwood/cesa/mvCesaDebug.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvCesaDebug.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/cesa/mvCesaDebug.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,484 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "mvOs.h" -+#include "mvDebug.h" -+ -+#include "cesa/mvMD5.h" -+#include "cesa/mvSHA1.h" -+ -+#include "cesa/mvCesa.h" -+#include "cesa/mvCesaRegs.h" -+#include "cesa/AES/mvAes.h" -+ -+static const char* mvCesaDebugStateStr(MV_CESA_STATE state) -+{ -+ switch(state) -+ { -+ case MV_CESA_IDLE: -+ return "Idle"; -+ -+ case MV_CESA_PENDING: -+ return "Pend"; -+ -+ case MV_CESA_PROCESS: -+ return "Proc"; -+ -+ case MV_CESA_READY: -+ return "Ready"; -+ -+ default: -+ break; -+ } -+ return "Unknown"; -+} -+ -+static const char* mvCesaDebugOperStr(MV_CESA_OPERATION oper) -+{ -+ switch(oper) -+ { -+ case MV_CESA_MAC_ONLY: -+ return "MacOnly"; -+ -+ case MV_CESA_CRYPTO_ONLY: -+ return "CryptoOnly"; -+ -+ case MV_CESA_MAC_THEN_CRYPTO: -+ return "MacCrypto"; -+ -+ case MV_CESA_CRYPTO_THEN_MAC: -+ return "CryptoMac"; -+ -+ default: -+ break; -+ } -+ return "Null"; -+} -+ -+static const char* mvCesaDebugCryptoAlgStr(MV_CESA_CRYPTO_ALG cryptoAlg) -+{ -+ switch(cryptoAlg) -+ { -+ case MV_CESA_CRYPTO_DES: -+ return "DES"; -+ -+ case MV_CESA_CRYPTO_3DES: -+ return "3DES"; -+ -+ case MV_CESA_CRYPTO_AES: -+ return "AES"; -+ -+ default: -+ break; -+ } -+ return "Null"; -+} -+ -+static const char* mvCesaDebugMacModeStr(MV_CESA_MAC_MODE macMode) -+{ -+ switch(macMode) -+ { -+ case MV_CESA_MAC_MD5: -+ return "MD5"; -+ -+ case MV_CESA_MAC_SHA1: -+ return "SHA1"; -+ -+ case MV_CESA_MAC_HMAC_MD5: -+ return "HMAC-MD5"; -+ -+ case MV_CESA_MAC_HMAC_SHA1: -+ return "HMAC_SHA1"; -+ -+ default: -+ break; -+ } -+ return "Null"; -+} -+ -+void mvCesaDebugCmd(MV_CESA_COMMAND* pCmd, int mode) -+{ -+ mvOsPrintf("pCmd=%p, pReqPrv=%p, pSrc=%p, pDst=%p, pCB=%p, sid=%d\n", -+ pCmd, pCmd->pReqPrv, pCmd->pSrc, pCmd->pDst, -+ pCmd->pFuncCB, pCmd->sessionId); -+ mvOsPrintf("isUser=%d, ivOffs=%d, crOffs=%d, crLen=%d, digest=%d, macOffs=%d, macLen=%d\n", -+ pCmd->ivFromUser, pCmd->ivOffset, pCmd->cryptoOffset, pCmd->cryptoLength, -+ pCmd->digestOffset, pCmd->macOffset, pCmd->macLength); -+} -+ -+/* no need to use in tool */ -+void mvCesaDebugMbuf(const char* str, MV_CESA_MBUF *pMbuf, int offset, int size) -+{ -+ int frag, len, fragOffset; -+ -+ if(str != NULL) -+ mvOsPrintf("%s: pMbuf=%p, numFrags=%d, mbufSize=%d\n", -+ str, pMbuf, pMbuf->numFrags, pMbuf->mbufSize); -+ -+ frag = mvCesaMbufOffset(pMbuf, offset, &fragOffset); -+ if(frag == MV_INVALID) -+ { -+ mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); -+ return; -+ } -+ -+ for(; fragnumFrags; frag++) -+ { -+ mvOsPrintf("#%2d. bufVirt=%p, bufSize=%d\n", -+ frag, pMbuf->pFrags[frag].bufVirtPtr, -+ pMbuf->pFrags[frag].bufSize); -+ if(size > 0) -+ { -+ len = MV_MIN(pMbuf->pFrags[frag].bufSize, size); -+ mvDebugMemDump(pMbuf->pFrags[frag].bufVirtPtr+fragOffset, len, 1); -+ size -= len; -+ fragOffset = 0; -+ } -+ } -+} -+ -+void mvCesaDebugRegs(void) -+{ -+ mvOsPrintf("\t CESA Registers:\n"); -+ -+ mvOsPrintf("MV_CESA_CMD_REG : 0x%X = 0x%08x\n", -+ MV_CESA_CMD_REG, -+ MV_REG_READ( MV_CESA_CMD_REG ) ); -+ -+ mvOsPrintf("MV_CESA_CHAN_DESC_OFFSET_REG : 0x%X = 0x%08x\n", -+ MV_CESA_CHAN_DESC_OFFSET_REG, -+ MV_REG_READ(MV_CESA_CHAN_DESC_OFFSET_REG) ); -+ -+ mvOsPrintf("MV_CESA_CFG_REG : 0x%X = 0x%08x\n", -+ MV_CESA_CFG_REG, -+ MV_REG_READ( MV_CESA_CFG_REG ) ); -+ -+ mvOsPrintf("MV_CESA_STATUS_REG : 0x%X = 0x%08x\n", -+ MV_CESA_STATUS_REG, -+ MV_REG_READ( MV_CESA_STATUS_REG ) ); -+ -+ mvOsPrintf("MV_CESA_ISR_CAUSE_REG : 0x%X = 0x%08x\n", -+ MV_CESA_ISR_CAUSE_REG, -+ MV_REG_READ( MV_CESA_ISR_CAUSE_REG ) ); -+ -+ mvOsPrintf("MV_CESA_ISR_MASK_REG : 0x%X = 0x%08x\n", -+ MV_CESA_ISR_MASK_REG, -+ MV_REG_READ( MV_CESA_ISR_MASK_REG ) ); -+#if (MV_CESA_VERSION >= 2) -+ mvOsPrintf("MV_CESA_TDMA_CTRL_REG : 0x%X = 0x%08x\n", -+ MV_CESA_TDMA_CTRL_REG, -+ MV_REG_READ( MV_CESA_TDMA_CTRL_REG ) ); -+ -+ mvOsPrintf("MV_CESA_TDMA_BYTE_COUNT_REG : 0x%X = 0x%08x\n", -+ MV_CESA_TDMA_BYTE_COUNT_REG, -+ MV_REG_READ( MV_CESA_TDMA_BYTE_COUNT_REG ) ); -+ -+ mvOsPrintf("MV_CESA_TDMA_SRC_ADDR_REG : 0x%X = 0x%08x\n", -+ MV_CESA_TDMA_SRC_ADDR_REG, -+ MV_REG_READ( MV_CESA_TDMA_SRC_ADDR_REG ) ); -+ -+ mvOsPrintf("MV_CESA_TDMA_DST_ADDR_REG : 0x%X = 0x%08x\n", -+ MV_CESA_TDMA_DST_ADDR_REG, -+ MV_REG_READ( MV_CESA_TDMA_DST_ADDR_REG ) ); -+ -+ mvOsPrintf("MV_CESA_TDMA_NEXT_DESC_PTR_REG : 0x%X = 0x%08x\n", -+ MV_CESA_TDMA_NEXT_DESC_PTR_REG, -+ MV_REG_READ( MV_CESA_TDMA_NEXT_DESC_PTR_REG ) ); -+ -+ mvOsPrintf("MV_CESA_TDMA_CURR_DESC_PTR_REG : 0x%X = 0x%08x\n", -+ MV_CESA_TDMA_CURR_DESC_PTR_REG, -+ MV_REG_READ( MV_CESA_TDMA_CURR_DESC_PTR_REG ) ); -+ -+ mvOsPrintf("MV_CESA_TDMA_ERROR_CAUSE_REG : 0x%X = 0x%08x\n", -+ MV_CESA_TDMA_ERROR_CAUSE_REG, -+ MV_REG_READ( MV_CESA_TDMA_ERROR_CAUSE_REG ) ); -+ -+ mvOsPrintf("MV_CESA_TDMA_ERROR_MASK_REG : 0x%X = 0x%08x\n", -+ MV_CESA_TDMA_ERROR_MASK_REG, -+ MV_REG_READ( MV_CESA_TDMA_ERROR_CAUSE_REG ) ); -+ -+#endif -+} -+ -+void mvCesaDebugStatus(void) -+{ -+ mvOsPrintf("\n\t CESA Status\n\n"); -+ -+ mvOsPrintf("pReqQ=%p, qDepth=%d, reqSize=%ld bytes, qRes=%d, ", -+ pCesaReqFirst, cesaQueueDepth, sizeof(MV_CESA_REQ), -+ cesaReqResources); -+#if (MV_CESA_VERSION >= 3) -+ mvOsPrintf("chainLength=%u\n",cesaChainLength); -+#else -+ mvOsPrintf("\n"); -+#endif -+ -+ mvOsPrintf("pSAD=%p, maxSA=%d, sizeSA=%ld bytes\n", -+ pCesaSAD, cesaMaxSA, sizeof(MV_CESA_SA)); -+ -+ mvOsPrintf("\n"); -+ -+ mvCesaDebugRegs(); -+ mvCesaDebugStats(); -+ mvCesaDebugStatsClear(); -+} -+ -+void mvCesaDebugDescriptor(MV_CESA_DESC* pDesc) -+{ -+ mvOsPrintf("config=0x%08x, crSrcOffs=0x%04x, crDstOffs=0x%04x\n", -+ pDesc->config, pDesc->cryptoSrcOffset, pDesc->cryptoDstOffset); -+ -+ mvOsPrintf("crLen=0x%04x, crKeyOffs=0x%04x, ivOffs=0x%04x, ivBufOffs=0x%04x\n", -+ pDesc->cryptoDataLen, pDesc->cryptoKeyOffset, -+ pDesc->cryptoIvOffset, pDesc->cryptoIvBufOffset); -+ -+ mvOsPrintf("macSrc=0x%04x, digest=0x%04x, macLen=0x%04x, inIv=0x%04x, outIv=0x%04x\n", -+ pDesc->macSrcOffset, pDesc->macDigestOffset, pDesc->macDataLen, -+ pDesc->macInnerIvOffset, pDesc->macOuterIvOffset); -+} -+ -+void mvCesaDebugQueue(int mode) -+{ -+ mvOsPrintf("\n\t CESA Request Queue:\n\n"); -+ -+ mvOsPrintf("pFirstReq=%p, pLastReq=%p, qDepth=%d, reqSize=%ld bytes\n", -+ pCesaReqFirst, pCesaReqLast, cesaQueueDepth, sizeof(MV_CESA_REQ)); -+ -+ mvOsPrintf("pEmpty=%p, pProcess=%p, qResources=%d\n", -+ pCesaReqEmpty, pCesaReqProcess, -+ cesaReqResources); -+ -+ if(mode != 0) -+ { -+ int count = 0; -+ MV_CESA_REQ* pReq = pCesaReqFirst; -+ -+ for(count=0; countstate), -+ pReq->fragMode, pReq->pCmd, pReq->dma[0].pDmaFirst, &pReq->pCesaDesc[0]); -+ if(pReq->fragMode != MV_CESA_FRAG_NONE) -+ { -+ int frag; -+ -+ mvOsPrintf("pFrags=%p, num=%d, next=%d, bufOffset=%d, cryptoSize=%d, macSize=%d\n", -+ &pReq->frags, pReq->frags.numFrag, pReq->frags.nextFrag, -+ pReq->frags.bufOffset, pReq->frags.cryptoSize, pReq->frags.macSize); -+ for(frag=0; fragfrags.numFrag; frag++) -+ { -+ mvOsPrintf("#%d: pDmaFirst=%p, pDesc=%p\n", frag, -+ pReq->dma[frag].pDmaFirst, &pReq->pCesaDesc[frag]); -+ } -+ } -+ if(mode > 1) -+ { -+ /* Print out Command */ -+ mvCesaDebugCmd(pReq->pCmd, mode); -+ -+ /* Print out Descriptor */ -+ mvCesaDebugDescriptor(&pReq->pCesaDesc[0]); -+ } -+ pReq++; -+ } -+ } -+} -+ -+ -+void mvCesaDebugSramSA(MV_CESA_SRAM_SA* pSramSA, int mode) -+{ -+ if(pSramSA == NULL) -+ { -+ mvOsPrintf("cesaSramSA: Unexpected pSramSA=%p\n", pSramSA); -+ return; -+ } -+ mvOsPrintf("pSramSA=%p, sizeSramSA=%ld bytes\n", -+ pSramSA, sizeof(MV_CESA_SRAM_SA)); -+ -+ if(mode != 0) -+ { -+ mvOsPrintf("cryptoKey=%p, maxCryptoKey=%d bytes\n", -+ pSramSA->cryptoKey, MV_CESA_MAX_CRYPTO_KEY_LENGTH); -+ mvDebugMemDump(pSramSA->cryptoKey, MV_CESA_MAX_CRYPTO_KEY_LENGTH, 1); -+ -+ mvOsPrintf("macInnerIV=%p, maxInnerIV=%d bytes\n", -+ pSramSA->macInnerIV, MV_CESA_MAX_DIGEST_SIZE); -+ mvDebugMemDump(pSramSA->macInnerIV, MV_CESA_MAX_DIGEST_SIZE, 1); -+ -+ mvOsPrintf("macOuterIV=%p, maxOuterIV=%d bytes\n", -+ pSramSA->macOuterIV, MV_CESA_MAX_DIGEST_SIZE); -+ mvDebugMemDump(pSramSA->macOuterIV, MV_CESA_MAX_DIGEST_SIZE, 1); -+ } -+} -+ -+void mvCesaDebugSA(short sid, int mode) -+{ -+ MV_CESA_OPERATION oper; -+ MV_CESA_DIRECTION dir; -+ MV_CESA_CRYPTO_ALG cryptoAlg; -+ MV_CESA_CRYPTO_MODE cryptoMode; -+ MV_CESA_MAC_MODE macMode; -+ MV_CESA_SA* pSA = &pCesaSAD[sid]; -+ -+ if( (pSA->valid) || ((pSA->count != 0) && (mode > 0)) || (mode >= 2) ) -+ { -+ mvOsPrintf("\n\nCESA SA Entry #%d (%p) - %s (count=%d)\n", -+ sid, pSA, -+ pSA->valid ? "Valid" : "Invalid", pSA->count); -+ -+ oper = (pSA->config & MV_CESA_OPERATION_MASK) >> MV_CESA_OPERATION_OFFSET; -+ dir = (pSA->config & MV_CESA_DIRECTION_MASK) >> MV_CESA_DIRECTION_BIT; -+ mvOsPrintf("%s - %s ", mvCesaDebugOperStr(oper), -+ (dir == MV_CESA_DIR_ENCODE) ? "Encode" : "Decode"); -+ if(oper != MV_CESA_MAC_ONLY) -+ { -+ cryptoAlg = (pSA->config & MV_CESA_CRYPTO_ALG_MASK) >> MV_CESA_CRYPTO_ALG_OFFSET; -+ cryptoMode = (pSA->config & MV_CESA_CRYPTO_MODE_MASK) >> MV_CESA_CRYPTO_MODE_BIT; -+ mvOsPrintf("- %s - %s ", mvCesaDebugCryptoAlgStr(cryptoAlg), -+ (cryptoMode == MV_CESA_CRYPTO_ECB) ? "ECB" : "CBC"); -+ } -+ if(oper != MV_CESA_CRYPTO_ONLY) -+ { -+ macMode = (pSA->config & MV_CESA_MAC_MODE_MASK) >> MV_CESA_MAC_MODE_OFFSET; -+ mvOsPrintf("- %s ", mvCesaDebugMacModeStr(macMode)); -+ } -+ mvOsPrintf("\n"); -+ -+ if(mode > 0) -+ { -+ mvOsPrintf("config=0x%08x, cryptoKeySize=%d, digestSize=%d\n", -+ pCesaSAD[sid].config, pCesaSAD[sid].cryptoKeyLength, -+ pCesaSAD[sid].digestSize); -+ -+ mvCesaDebugSramSA(pCesaSAD[sid].pSramSA, mode); -+ } -+ } -+} -+ -+ -+/**/ -+void mvCesaDebugSram(int mode) -+{ -+ mvOsPrintf("\n\t SRAM contents: size=%ld, pVirt=%p\n\n", -+ sizeof(MV_CESA_SRAM_MAP), cesaSramVirtPtr); -+ -+ mvOsPrintf("\n\t Sram buffer: size=%d, pVirt=%p\n", -+ MV_CESA_MAX_BUF_SIZE, cesaSramVirtPtr->buf); -+ if(mode != 0) -+ mvDebugMemDump(cesaSramVirtPtr->buf, 64, 1); -+ -+ mvOsPrintf("\n"); -+ mvOsPrintf("\n\t Sram descriptor: size=%ld, pVirt=%p\n", -+ sizeof(MV_CESA_DESC), &cesaSramVirtPtr->desc); -+ if(mode != 0) -+ { -+ mvOsPrintf("\n"); -+ mvCesaDebugDescriptor(&cesaSramVirtPtr->desc); -+ } -+ mvOsPrintf("\n\t Sram IV: size=%d, pVirt=%p\n", -+ MV_CESA_MAX_IV_LENGTH, &cesaSramVirtPtr->cryptoIV); -+ if(mode != 0) -+ { -+ mvOsPrintf("\n"); -+ mvDebugMemDump(cesaSramVirtPtr->cryptoIV, MV_CESA_MAX_IV_LENGTH, 1); -+ } -+ mvOsPrintf("\n"); -+ mvCesaDebugSramSA(&cesaSramVirtPtr->sramSA, 0); -+} -+ -+void mvCesaDebugSAD(int mode) -+{ -+ int sid; -+ -+ mvOsPrintf("\n\t Cesa SAD status: pSAD=%p, maxSA=%d\n", -+ pCesaSAD, cesaMaxSA); -+ -+ for(sid=0; sid= 3) -+ mvOsPrintf("maxChainUsage=%u\n",cesaStats.maxChainUsage); -+#endif -+ mvOsPrintf("\n"); -+ mvOsPrintf("proc=%u, ready=%u, notReady=%u\n", -+ cesaStats.procCount, cesaStats.readyCount, cesaStats.notReadyCount); -+} -+ -+void mvCesaDebugStatsClear(void) -+{ -+ memset(&cesaStats, 0, sizeof(cesaStats)); -+} -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvCesaRegs.h linux-3.0.4/crypto/ocf/kirkwood/cesa/mvCesaRegs.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvCesaRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/cesa/mvCesaRegs.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,357 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __mvCesaRegs_h__ -+#define __mvCesaRegs_h__ -+ -+#include "mvTypes.h" -+ -+typedef struct -+{ -+ /* word 0 */ -+ MV_U32 config; -+ /* word 1 */ -+ MV_U16 cryptoSrcOffset; -+ MV_U16 cryptoDstOffset; -+ /* word 2 */ -+ MV_U16 cryptoDataLen; -+ MV_U16 reserved1; -+ /* word 3 */ -+ MV_U16 cryptoKeyOffset; -+ MV_U16 reserved2; -+ /* word 4 */ -+ MV_U16 cryptoIvOffset; -+ MV_U16 cryptoIvBufOffset; -+ /* word 5 */ -+ MV_U16 macSrcOffset; -+ MV_U16 macTotalLen; -+ /* word 6 */ -+ MV_U16 macDigestOffset; -+ MV_U16 macDataLen; -+ /* word 7 */ -+ MV_U16 macInnerIvOffset; -+ MV_U16 macOuterIvOffset; -+ -+} MV_CESA_DESC; -+ -+/* operation */ -+typedef enum -+{ -+ MV_CESA_MAC_ONLY = 0, -+ MV_CESA_CRYPTO_ONLY = 1, -+ MV_CESA_MAC_THEN_CRYPTO = 2, -+ MV_CESA_CRYPTO_THEN_MAC = 3, -+ -+ MV_CESA_MAX_OPERATION -+ -+} MV_CESA_OPERATION; -+ -+#define MV_CESA_OPERATION_OFFSET 0 -+#define MV_CESA_OPERATION_MASK (0x3 << MV_CESA_OPERATION_OFFSET) -+ -+/* mac algorithm */ -+typedef enum -+{ -+ MV_CESA_MAC_NULL = 0, -+ MV_CESA_MAC_MD5 = 4, -+ MV_CESA_MAC_SHA1 = 5, -+ MV_CESA_MAC_HMAC_MD5 = 6, -+ MV_CESA_MAC_HMAC_SHA1 = 7, -+ -+} MV_CESA_MAC_MODE; -+ -+#define MV_CESA_MAC_MODE_OFFSET 4 -+#define MV_CESA_MAC_MODE_MASK (0x7 << MV_CESA_MAC_MODE_OFFSET) -+ -+typedef enum -+{ -+ MV_CESA_MAC_DIGEST_FULL = 0, -+ MV_CESA_MAC_DIGEST_96B = 1, -+ -+} MV_CESA_MAC_DIGEST_SIZE; -+ -+#define MV_CESA_MAC_DIGEST_SIZE_BIT 7 -+#define MV_CESA_MAC_DIGEST_SIZE_MASK (1 << MV_CESA_MAC_DIGEST_SIZE_BIT) -+ -+ -+typedef enum -+{ -+ MV_CESA_CRYPTO_NULL = 0, -+ MV_CESA_CRYPTO_DES = 1, -+ MV_CESA_CRYPTO_3DES = 2, -+ MV_CESA_CRYPTO_AES = 3, -+ -+} MV_CESA_CRYPTO_ALG; -+ -+#define MV_CESA_CRYPTO_ALG_OFFSET 8 -+#define MV_CESA_CRYPTO_ALG_MASK (0x3 << MV_CESA_CRYPTO_ALG_OFFSET) -+ -+ -+/* direction */ -+typedef enum -+{ -+ MV_CESA_DIR_ENCODE = 0, -+ MV_CESA_DIR_DECODE = 1, -+ -+} MV_CESA_DIRECTION; -+ -+#define MV_CESA_DIRECTION_BIT 12 -+#define MV_CESA_DIRECTION_MASK (1 << MV_CESA_DIRECTION_BIT) -+ -+/* crypto IV mode */ -+typedef enum -+{ -+ MV_CESA_CRYPTO_ECB = 0, -+ MV_CESA_CRYPTO_CBC = 1, -+ -+ /* NO HW Support */ -+ MV_CESA_CRYPTO_CTR = 10, -+ -+} MV_CESA_CRYPTO_MODE; -+ -+#define MV_CESA_CRYPTO_MODE_BIT 16 -+#define MV_CESA_CRYPTO_MODE_MASK (1 << MV_CESA_CRYPTO_MODE_BIT) -+ -+/* 3DES mode */ -+typedef enum -+{ -+ MV_CESA_CRYPTO_3DES_EEE = 0, -+ MV_CESA_CRYPTO_3DES_EDE = 1, -+ -+} MV_CESA_CRYPTO_3DES_MODE; -+ -+#define MV_CESA_CRYPTO_3DES_MODE_BIT 20 -+#define MV_CESA_CRYPTO_3DES_MODE_MASK (1 << MV_CESA_CRYPTO_3DES_MODE_BIT) -+ -+ -+/* AES Key Length */ -+typedef enum -+{ -+ MV_CESA_CRYPTO_AES_KEY_128 = 0, -+ MV_CESA_CRYPTO_AES_KEY_192 = 1, -+ MV_CESA_CRYPTO_AES_KEY_256 = 2, -+ -+} MV_CESA_CRYPTO_AES_KEY_LEN; -+ -+#define MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET 24 -+#define MV_CESA_CRYPTO_AES_KEY_LEN_MASK (0x3 << MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET) -+ -+/* Fragmentation mode */ -+typedef enum -+{ -+ MV_CESA_FRAG_NONE = 0, -+ MV_CESA_FRAG_FIRST = 1, -+ MV_CESA_FRAG_LAST = 2, -+ MV_CESA_FRAG_MIDDLE = 3, -+ -+} MV_CESA_FRAG_MODE; -+ -+#define MV_CESA_FRAG_MODE_OFFSET 30 -+#define MV_CESA_FRAG_MODE_MASK (0x3 << MV_CESA_FRAG_MODE_OFFSET) -+/*---------------------------------------------------------------------------*/ -+ -+/********** Security Accelerator Command Register **************/ -+#define MV_CESA_CMD_REG (MV_CESA_REG_BASE + 0xE00) -+ -+#define MV_CESA_CMD_CHAN_ENABLE_BIT 0 -+#define MV_CESA_CMD_CHAN_ENABLE_MASK (1 << MV_CESA_CMD_CHAN_ENABLE_BIT) -+ -+#define MV_CESA_CMD_CHAN_DISABLE_BIT 2 -+#define MV_CESA_CMD_CHAN_DISABLE_MASK (1 << MV_CESA_CMD_CHAN_DISABLE_BIT) -+ -+/********** Security Accelerator Descriptor Pointers Register **********/ -+#define MV_CESA_CHAN_DESC_OFFSET_REG (MV_CESA_REG_BASE + 0xE04) -+ -+/********** Security Accelerator Configuration Register **********/ -+#define MV_CESA_CFG_REG (MV_CESA_REG_BASE + 0xE08) -+ -+#define MV_CESA_CFG_STOP_DIGEST_ERR_BIT 0 -+#define MV_CESA_CFG_STOP_DIGEST_ERR_MASK (1 << MV_CESA_CFG_STOP_DIGEST_ERR_BIT) -+ -+#define MV_CESA_CFG_WAIT_DMA_BIT 7 -+#define MV_CESA_CFG_WAIT_DMA_MASK (1 << MV_CESA_CFG_WAIT_DMA_BIT) -+ -+#define MV_CESA_CFG_ACT_DMA_BIT 9 -+#define MV_CESA_CFG_ACT_DMA_MASK (1 << MV_CESA_CFG_ACT_DMA_BIT) -+ -+#define MV_CESA_CFG_CHAIN_MODE_BIT 11 -+#define MV_CESA_CFG_CHAIN_MODE_MASK (1 << MV_CESA_CFG_CHAIN_MODE_BIT) -+ -+/********** Security Accelerator Status Register ***********/ -+#define MV_CESA_STATUS_REG (MV_CESA_REG_BASE + 0xE0C) -+ -+#define MV_CESA_STATUS_ACTIVE_BIT 0 -+#define MV_CESA_STATUS_ACTIVE_MASK (1 << MV_CESA_STATUS_ACTIVE_BIT) -+ -+#define MV_CESA_STATUS_DIGEST_ERR_BIT 8 -+#define MV_CESA_STATUS_DIGEST_ERR_MASK (1 << MV_CESA_STATUS_DIGEST_ERR_BIT) -+ -+ -+/* Cryptographic Engines and Security Accelerator Interrupt Cause Register */ -+#define MV_CESA_ISR_CAUSE_REG (MV_CESA_REG_BASE + 0xE20) -+ -+/* Cryptographic Engines and Security Accelerator Interrupt Mask Register */ -+#define MV_CESA_ISR_MASK_REG (MV_CESA_REG_BASE + 0xE24) -+ -+#define MV_CESA_CAUSE_AUTH_MASK (1 << 0) -+#define MV_CESA_CAUSE_DES_MASK (1 << 1) -+#define MV_CESA_CAUSE_AES_ENCR_MASK (1 << 2) -+#define MV_CESA_CAUSE_AES_DECR_MASK (1 << 3) -+#define MV_CESA_CAUSE_DES_ALL_MASK (1 << 4) -+ -+#define MV_CESA_CAUSE_ACC_BIT 5 -+#define MV_CESA_CAUSE_ACC_MASK (1 << MV_CESA_CAUSE_ACC_BIT) -+ -+#define MV_CESA_CAUSE_ACC_DMA_BIT 7 -+#define MV_CESA_CAUSE_ACC_DMA_MASK (1 << MV_CESA_CAUSE_ACC_DMA_BIT) -+#define MV_CESA_CAUSE_ACC_DMA_ALL_MASK (3 << MV_CESA_CAUSE_ACC_DMA_BIT) -+ -+#define MV_CESA_CAUSE_DMA_COMPL_BIT 9 -+#define MV_CESA_CAUSE_DMA_COMPL_MASK (1 << MV_CESA_CAUSE_DMA_COMPL_BIT) -+ -+#define MV_CESA_CAUSE_DMA_OWN_ERR_BIT 10 -+#define MV_CESA_CAUSE_DMA_OWN_ERR_MASK (1 < MV_CESA_CAUSE_DMA_OWN_ERR_BIT) -+ -+#define MV_CESA_CAUSE_DMA_CHAIN_PKT_BIT 11 -+#define MV_CESA_CAUSE_DMA_CHAIN_PKT_MASK (1 < MV_CESA_CAUSE_DMA_CHAIN_PKT_BIT) -+ -+ -+#define MV_CESA_AUTH_DATA_IN_REG (MV_CESA_REG_BASE + 0xd38) -+#define MV_CESA_AUTH_BIT_COUNT_LOW_REG (MV_CESA_REG_BASE + 0xd20) -+#define MV_CESA_AUTH_BIT_COUNT_HIGH_REG (MV_CESA_REG_BASE + 0xd24) -+ -+#define MV_CESA_AUTH_INIT_VAL_DIGEST_REG(i) (MV_CESA_REG_BASE + 0xd00 + (i<<2)) -+ -+#define MV_CESA_AUTH_INIT_VAL_DIGEST_A_REG (MV_CESA_REG_BASE + 0xd00) -+#define MV_CESA_AUTH_INIT_VAL_DIGEST_B_REG (MV_CESA_REG_BASE + 0xd04) -+#define MV_CESA_AUTH_INIT_VAL_DIGEST_C_REG (MV_CESA_REG_BASE + 0xd08) -+#define MV_CESA_AUTH_INIT_VAL_DIGEST_D_REG (MV_CESA_REG_BASE + 0xd0c) -+#define MV_CESA_AUTH_INIT_VAL_DIGEST_E_REG (MV_CESA_REG_BASE + 0xd10) -+#define MV_CESA_AUTH_COMMAND_REG (MV_CESA_REG_BASE + 0xd18) -+ -+#define MV_CESA_AUTH_ALGORITHM_BIT 0 -+#define MV_CESA_AUTH_ALGORITHM_MD5 (0< -+wait_queue_head_t cesaTest_waitq; -+spinlock_t cesaLock; -+ -+#define CESA_TEST_LOCK(flags) spin_lock_irqsave( &cesaLock, flags) -+#define CESA_TEST_UNLOCK(flags) spin_unlock_irqrestore( &cesaLock, flags); -+ -+#define CESA_TEST_WAIT_INIT() init_waitqueue_head(&cesaTest_waitq) -+#define CESA_TEST_WAKE_UP() wake_up(&cesaTest_waitq) -+#define CESA_TEST_WAIT(cond, ms) wait_event_timeout(cesaTest_waitq, (cond), msecs_to_jiffies(ms)) -+ -+#define CESA_TEST_TICK_GET() jiffies -+#define CESA_TEST_TICK_TO_MS(tick) jiffies_to_msecs(tick) -+ -+#elif defined(MV_NETBSD) -+ -+#include -+#include -+static int cesaLock; -+ -+#define CESA_TEST_LOCK(flags) flags = splnet() -+#define CESA_TEST_UNLOCK(flags) splx(flags) -+ -+#define CESA_TEST_WAIT_INIT() /* nothing */ -+#define CESA_TEST_WAKE_UP() wakeup(&cesaLock) -+#define CESA_TEST_WAIT(cond, ms) \ -+do { \ -+ while (!(cond)) \ -+ tsleep(&cesaLock, PWAIT, "cesatest",mstohz(ms)); \ -+} while (/*CONSTCOND*/0) -+ -+#define CESA_TEST_TICK_GET() hardclock_ticks -+#define CESA_TEST_TICK_TO_MS(tick) ((1000/hz)*(tick)) -+ -+#define request_irq(i,h,t,n,a) \ -+ !mv_intr_establish((i),IPL_NET,(int(*)(void *))(h),(a)) -+ -+#else -+#error "Only Linux, VxWorks, or NetBSD OS are supported" -+#endif -+ -+#include "mvDebug.h" -+ -+#include "mvSysHwConfig.h" -+#include "boardEnv/mvBoardEnvLib.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+#include "cntmr/mvCntmr.h" -+#include "cesa/mvCesa.h" -+#include "cesa/mvCesaRegs.h" -+#include "cesa/mvMD5.h" -+#include "cesa/mvSHA1.h" -+ -+#if defined(CONFIG_MV646xx) -+#include "marvell_pic.h" -+#endif -+ -+#define MV_CESA_USE_TIMER_ID 0 -+#define CESA_DEF_BUF_SIZE 1500 -+#define CESA_DEF_BUF_NUM 1 -+#define CESA_DEF_SESSION_NUM 32 -+ -+#define CESA_DEF_ITER_NUM 100 -+ -+#define CESA_DEF_REQ_SIZE 256 -+ -+ -+/* CESA Tests Debug */ -+#undef CESA_TEST_DEBUG -+ -+#ifdef CESA_TEST_DEBUG -+ -+# define CESA_TEST_DEBUG_PRINT(msg) mvOsPrintf msg -+# define CESA_TEST_DEBUG_CODE(code) code -+ -+typedef struct -+{ -+ int type; /* 0 - isrEmpty, 1 - cesaReadyGet, 2 - cesaAction */ -+ MV_U32 timeStamp; -+ MV_U32 cause; -+ MV_U32 realCause; -+ MV_U32 dmaCause; -+ int resources; -+ MV_CESA_REQ* pReqReady; -+ MV_CESA_REQ* pReqEmpty; -+ MV_CESA_REQ* pReqProcess; -+} MV_CESA_TEST_TRACE; -+ -+#define MV_CESA_TEST_TRACE_SIZE 25 -+ -+static int cesaTestTraceIdx = 0; -+static MV_CESA_TEST_TRACE cesaTestTrace[MV_CESA_TEST_TRACE_SIZE]; -+ -+static void cesaTestTraceAdd(int type, MV_U32 cause) -+{ -+ cesaTestTrace[cesaTestTraceIdx].type = type; -+ cesaTestTrace[cesaTestTraceIdx].cause = cause; -+ cesaTestTrace[cesaTestTraceIdx].realCause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); -+ cesaTestTrace[cesaTestTraceIdx].dmaCause = MV_REG_READ(IDMA_CAUSE_REG); -+ cesaTestTrace[cesaTestTraceIdx].resources = cesaReqResources; -+ cesaTestTrace[cesaTestTraceIdx].pReqReady = pCesaReqReady; -+ cesaTestTrace[cesaTestTraceIdx].pReqEmpty = pCesaReqEmpty; -+ cesaTestTrace[cesaTestTraceIdx].pReqProcess = pCesaReqProcess; -+ cesaTestTrace[cesaTestTraceIdx].timeStamp = mvCntmrRead(MV_CESA_USE_TIMER_ID); -+ cesaTestTraceIdx++; -+ if(cesaTestTraceIdx == MV_CESA_TEST_TRACE_SIZE) -+ cesaTestTraceIdx = 0; -+} -+ -+#else -+ -+# define CESA_TEST_DEBUG_PRINT(msg) -+# define CESA_TEST_DEBUG_CODE(code) -+ -+#endif /* CESA_TEST_DEBUG */ -+ -+int cesaExpReqId=0; -+int cesaCbIter=0; -+ -+int cesaIdx; -+int cesaIteration; -+int cesaRateSize; -+int cesaReqSize; -+unsigned long cesaTaskId; -+int cesaBufNum; -+int cesaBufSize; -+int cesaCheckOffset; -+int cesaCheckSize; -+int cesaCheckMode; -+int cesaTestIdx; -+int cesaCaseIdx; -+ -+ -+MV_U32 cesaTestIsrCount = 0; -+MV_U32 cesaTestIsrMissCount = 0; -+ -+MV_U32 cesaCryptoError = 0; -+MV_U32 cesaReqIdError = 0; -+MV_U32 cesaError = 0; -+ -+char* cesaHexBuffer = NULL; -+ -+char* cesaBinBuffer = NULL; -+char* cesaExpBinBuffer = NULL; -+ -+char* cesaInputHexStr = NULL; -+char* cesaOutputHexStr = NULL; -+ -+MV_BUF_INFO cesaReqBufs[CESA_DEF_REQ_SIZE]; -+ -+MV_CESA_COMMAND* cesaCmdRing; -+MV_CESA_RESULT cesaResult; -+ -+int cesaTestFull = 0; -+ -+MV_BOOL cesaIsReady = MV_FALSE; -+MV_U32 cesaCycles = 0; -+MV_U32 cesaBeginTicks = 0; -+MV_U32 cesaEndTicks = 0; -+MV_U32 cesaRate = 0; -+MV_U32 cesaRateAfterDot = 0; -+ -+void *cesaTestOSHandle = NULL; -+ -+enum -+{ -+ CESA_FAST_CHECK_MODE = 0, -+ CESA_FULL_CHECK_MODE, -+ CESA_NULL_CHECK_MODE, -+ CESA_SHOW_CHECK_MODE, -+ CESA_SW_SHOW_CHECK_MODE, -+ CESA_SW_NULL_CHECK_MODE, -+ -+ CESA_MAX_CHECK_MODE -+}; -+ -+enum -+{ -+ DES_TEST_TYPE = 0, -+ TRIPLE_DES_TEST_TYPE = 1, -+ AES_TEST_TYPE = 2, -+ MD5_TEST_TYPE = 3, -+ SHA_TEST_TYPE = 4, -+ COMBINED_TEST_TYPE = 5, -+ -+ MAX_TEST_TYPE -+}; -+ -+/* Tests data base */ -+typedef struct -+{ -+ short sid; -+ char cryptoAlgorithm; /* DES/3DES/AES */ -+ char cryptoMode; /* ECB or CBC */ -+ char macAlgorithm; /* MD5 / SHA1 */ -+ char operation; /* CRYPTO/HMAC/CRYPTO+HMAC/HMAC+CRYPTO */ -+ char direction; /* ENCODE(SIGN)/DECODE(VERIFY) */ -+ unsigned char* pCryptoKey; -+ int cryptoKeySize; -+ unsigned char* pMacKey; -+ int macKeySize; -+ const char* name; -+ -+} MV_CESA_TEST_SESSION; -+ -+typedef struct -+{ -+ MV_CESA_TEST_SESSION* pSessions; -+ int numSessions; -+ -+} MV_CESA_TEST_DB_ENTRY; -+ -+typedef struct -+{ -+ char* plainHexStr; -+ char* cipherHexStr; -+ unsigned char* pCryptoIV; -+ int cryptoLength; -+ int macLength; -+ int digestOffset; -+ -+} MV_CESA_TEST_CASE; -+ -+typedef struct -+{ -+ int size; -+ const char* outputHexStr; -+ -+} MV_CESA_SIZE_TEST; -+ -+static unsigned char cryptoKey1[] = {0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, -+ 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, -+ 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef}; -+ -+static unsigned char cryptoKey7[] = {0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef}; -+static unsigned char iv1[] = {0x12, 0x34, 0x56, 0x78, 0x90, 0xab, 0xcd, 0xef}; -+ -+ -+static unsigned char cryptoKey2[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, -+ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F}; -+ -+static unsigned char cryptoKey3[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, -+ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, -+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17}; -+ -+static unsigned char cryptoKey4[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, -+ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, -+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, -+ 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f}; -+ -+static unsigned char cryptoKey5[] = {0x56, 0xe4, 0x7a, 0x38, 0xc5, 0x59, 0x89, 0x74, -+ 0xbc, 0x46, 0x90, 0x3d, 0xba, 0x29, 0x03, 0x49}; -+ -+ -+static unsigned char key3des1[] = {0x01, 0x23, 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF, -+ 0x23, 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF, 0x01, -+ 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF, 0x01, 0x23}; -+ -+/* Input ASCII string: The quick brown fox jump */ -+static char plain3des1[] = "54686520717566636B2062726F776E20666F78206A756D70"; -+static char cipher3des1[] = "A826FD8CE53B855FCCE21C8112256FE668D5C05DD9B6B900"; -+ -+static unsigned char key3des2[] = {0x62, 0x7f, 0x46, 0x0e, 0x08, 0x10, 0x4a, 0x10, -+ 0x43, 0xcd, 0x26, 0x5d, 0x58, 0x40, 0xea, 0xf1, -+ 0x31, 0x3e, 0xdf, 0x97, 0xdf, 0x2a, 0x8a, 0x8c}; -+ -+static unsigned char iv3des2[] = {0x8e, 0x29, 0xf7, 0x5e, 0xa7, 0x7e, 0x54, 0x75}; -+ -+static char plain3des2[] = "326a494cd33fe756"; -+ -+static char cipher3desCbc2[] = "8e29f75ea77e5475" -+ "b22b8d66de970692"; -+ -+static unsigned char key3des3[] = {0x37, 0xae, 0x5e, 0xbf, 0x46, 0xdf, 0xf2, 0xdc, -+ 0x07, 0x54, 0xb9, 0x4f, 0x31, 0xcb, 0xb3, 0x85, -+ 0x5e, 0x7f, 0xd3, 0x6d, 0xc8, 0x70, 0xbf, 0xae}; -+ -+static unsigned char iv3des3[] = {0x3d, 0x1d, 0xe3, 0xcc, 0x13, 0x2e, 0x3b, 0x65}; -+ -+static char plain3des3[] = "84401f78fe6c10876d8ea23094ea5309"; -+ -+static char cipher3desCbc3[] = "3d1de3cc132e3b65" -+ "7b1f7c7e3b1c948ebd04a75ffba7d2f5"; -+ -+static unsigned char iv5[] = {0x8c, 0xe8, 0x2e, 0xef, 0xbe, 0xa0, 0xda, 0x3c, -+ 0x44, 0x69, 0x9e, 0xd7, 0xdb, 0x51, 0xb7, 0xd9}; -+ -+static unsigned char aesCtrKey[] = {0x76, 0x91, 0xBE, 0x03, 0x5E, 0x50, 0x20, 0xA8, -+ 0xAC, 0x6E, 0x61, 0x85, 0x29, 0xF9, 0xA0, 0xDC}; -+ -+static unsigned char mdKey1[] = {0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, -+ 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b}; -+ -+static unsigned char mdKey2[] = {0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -+ 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa}; -+ -+static unsigned char shaKey1[] = {0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, -+ 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, -+ 0x0b, 0x0b, 0x0b, 0x0b}; -+ -+static unsigned char shaKey2[] = {0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -+ 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -+ 0xaa, 0xaa, 0xaa, 0xaa}; -+ -+static unsigned char mdKey4[] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10}; -+ -+static unsigned char shaKey4[] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10, -+ 0x11, 0x12, 0x13, 0x14}; -+ -+ -+static MV_CESA_TEST_SESSION desTestSessions[] = -+{ -+/*000*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey7, sizeof(cryptoKey7)/sizeof(cryptoKey7[0]), -+ NULL, 0, -+ "DES ECB encode", -+ }, -+/*001*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_DECODE, -+ cryptoKey7, sizeof(cryptoKey7)/sizeof(cryptoKey7[0]), -+ NULL, 0, -+ "DES ECB decode", -+ }, -+/*002*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey7, sizeof(cryptoKey7)/sizeof(cryptoKey7[0]), -+ NULL, 0, -+ "DES CBC encode" -+ }, -+/*003*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_DECODE, -+ cryptoKey7, sizeof(cryptoKey7)/sizeof(cryptoKey7[0]), -+ NULL, 0, -+ "DES CBC decode" -+ }, -+/*004*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, NULL, 0, -+ "NULL Crypto Algorithm encode" -+ }, -+}; -+ -+ -+static MV_CESA_TEST_SESSION tripleDesTestSessions[] = -+{ -+/*100*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ NULL, 0, -+ "3DES ECB encode", -+ }, -+/*101*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_DECODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ NULL, 0, -+ "3DES ECB decode", -+ }, -+/*102*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ NULL, 0, -+ "3DES CBC encode" -+ }, -+/*103*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_DECODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ NULL, 0, -+ "3DES CBC decode" -+ }, -+/*104*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ key3des1, sizeof(key3des1), -+ NULL, 0, -+ "3DES ECB encode" -+ }, -+/*105*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ key3des2, sizeof(key3des2), -+ NULL, 0, -+ "3DES ECB encode" -+ }, -+/*106*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ key3des3, sizeof(key3des3), -+ NULL, 0, -+ "3DES ECB encode" -+ }, -+}; -+ -+ -+static MV_CESA_TEST_SESSION aesTestSessions[] = -+{ -+/*200*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey2, sizeof(cryptoKey2)/sizeof(cryptoKey2[0]), -+ NULL, 0, -+ "AES-128 ECB encode" -+ }, -+/*201*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_DECODE, -+ cryptoKey2, sizeof(cryptoKey2)/sizeof(cryptoKey2[0]), -+ NULL, 0, -+ "AES-128 ECB decode" -+ }, -+/*202*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey5, sizeof(cryptoKey5)/sizeof(cryptoKey5[0]), -+ NULL, 0, -+ "AES-128 CBC encode" -+ }, -+/*203*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_DECODE, -+ cryptoKey5, sizeof(cryptoKey5)/sizeof(cryptoKey5[0]), -+ NULL, 0, -+ "AES-128 CBC decode" -+ }, -+/*204*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey3, sizeof(cryptoKey3)/sizeof(cryptoKey3[0]), -+ NULL, 0, -+ "AES-192 ECB encode" -+ }, -+/*205*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_DECODE, -+ cryptoKey3, sizeof(cryptoKey3)/sizeof(cryptoKey3[0]), -+ NULL, 0, -+ "AES-192 ECB decode" -+ }, -+/*206*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey4, sizeof(cryptoKey4)/sizeof(cryptoKey4[0]), -+ NULL, 0, -+ "AES-256 ECB encode" -+ }, -+/*207*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_DECODE, -+ cryptoKey4, sizeof(cryptoKey4)/sizeof(cryptoKey4[0]), -+ NULL, 0, -+ "AES-256 ECB decode" -+ }, -+/*208*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CTR, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ aesCtrKey, sizeof(aesCtrKey)/sizeof(aesCtrKey[0]), -+ NULL, 0, -+ "AES-128 CTR encode" -+ }, -+}; -+ -+ -+static MV_CESA_TEST_SESSION md5TestSessions[] = -+{ -+/*300*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, -+ mdKey1, sizeof(mdKey1), -+ "HMAC-MD5 Generate Signature" -+ }, -+/*301*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_DECODE, -+ NULL, 0, -+ mdKey1, sizeof(mdKey1), -+ "HMAC-MD5 Verify Signature" -+ }, -+/*302*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, -+ mdKey2, sizeof(mdKey2), -+ "HMAC-MD5 Generate Signature" -+ }, -+/*303*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_DECODE, -+ NULL, 0, -+ mdKey2, sizeof(mdKey2), -+ "HMAC-MD5 Verify Signature" -+ }, -+/*304*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, -+ mdKey4, sizeof(mdKey4), -+ "HMAC-MD5 Generate Signature" -+ }, -+/*305*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_MD5, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, -+ NULL, 0, -+ "HASH-MD5 Generate Signature" -+ }, -+}; -+ -+ -+static MV_CESA_TEST_SESSION shaTestSessions[] = -+{ -+/*400*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, -+ shaKey1, sizeof(shaKey1), -+ "HMAC-SHA1 Generate Signature" -+ }, -+/*401*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_DECODE, -+ NULL, 0, -+ shaKey1, sizeof(shaKey1), -+ "HMAC-SHA1 Verify Signature" -+ }, -+/*402*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, -+ shaKey2, sizeof(shaKey2), -+ "HMAC-SHA1 Generate Signature" -+ }, -+/*403*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_DECODE, -+ NULL, 0, -+ shaKey2, sizeof(shaKey2), -+ "HMAC-SHA1 Verify Signature" -+ }, -+/*404*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, -+ shaKey4, sizeof(shaKey4), -+ "HMAC-SHA1 Generate Signature" -+ }, -+/*405*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_SHA1, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, -+ NULL, 0, -+ "HASH-SHA1 Generate Signature" -+ }, -+}; -+ -+static MV_CESA_TEST_SESSION combinedTestSessions[] = -+{ -+/*500*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey1, MV_CESA_DES_KEY_LENGTH, -+ mdKey4, sizeof(mdKey4), -+ "DES + MD5 encode" -+ }, -+/*501*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey1, MV_CESA_DES_KEY_LENGTH, -+ shaKey4, sizeof(shaKey4), -+ "DES + SHA1 encode" -+ }, -+/*502*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ mdKey4, sizeof(mdKey4), -+ "3DES + MD5 encode" -+ }, -+/*503*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ shaKey4, sizeof(shaKey4), -+ "3DES + SHA1 encode" -+ }, -+/*504*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ mdKey4, sizeof(mdKey4), -+ "3DES CBC + MD5 encode" -+ }, -+/*505*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ shaKey4, sizeof(shaKey4), -+ "3DES CBC + SHA1 encode" -+ }, -+/*506*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey5, sizeof(cryptoKey5)/sizeof(cryptoKey5[0]), -+ mdKey4, sizeof(mdKey4), -+ "AES-128 CBC + MD5 encode" -+ }, -+/*507*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey5, sizeof(cryptoKey5)/sizeof(cryptoKey5[0]), -+ shaKey4, sizeof(shaKey4), -+ "AES-128 CBC + SHA1 encode" -+ }, -+/*508*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_THEN_CRYPTO, -+ MV_CESA_DIR_DECODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ mdKey4, sizeof(mdKey4), -+ "HMAC-MD5 + 3DES decode" -+ }, -+}; -+ -+ -+static MV_CESA_TEST_DB_ENTRY cesaTestsDB[MAX_TEST_TYPE+1] = -+{ -+ { desTestSessions, sizeof(desTestSessions)/sizeof(desTestSessions[0]) }, -+ { tripleDesTestSessions, sizeof(tripleDesTestSessions)/sizeof(tripleDesTestSessions[0]) }, -+ { aesTestSessions, sizeof(aesTestSessions)/sizeof(aesTestSessions[0]) }, -+ { md5TestSessions, sizeof(md5TestSessions)/sizeof(md5TestSessions[0]) }, -+ { shaTestSessions, sizeof(shaTestSessions)/sizeof(shaTestSessions[0]) }, -+ { combinedTestSessions, sizeof(combinedTestSessions)/sizeof(combinedTestSessions[0]) }, -+ { NULL, 0 } -+}; -+ -+ -+char cesaNullPlainHexText[] = "000000000000000000000000000000000000000000000000"; -+ -+char cesaPlainAsciiText[] = "Now is the time for all "; -+char cesaPlainHexEbc[] = "4e6f77206973207468652074696d6520666f7220616c6c20"; -+char cesaCipherHexEcb[] = "3fa40e8a984d48156a271787ab8883f9893d51ec4b563b53"; -+char cesaPlainHexCbc[] = "1234567890abcdef4e6f77206973207468652074696d6520666f7220616c6c20"; -+char cesaCipherHexCbc[] = "1234567890abcdefe5c7cdde872bf27c43e934008c389c0f683788499a7c05f6"; -+ -+char cesaAesPlainHexEcb[] = "000102030405060708090a0b0c0d0e0f"; -+char cesaAes128cipherHexEcb[] = "0a940bb5416ef045f1c39458c653ea5a"; -+char cesaAes192cipherHexEcb[] = "0060bffe46834bb8da5cf9a61ff220ae"; -+char cesaAes256cipherHexEcb[] = "5a6e045708fb7196f02e553d02c3a692"; -+ -+char cesaAsciiStr1[] = "Hi There"; -+char cesaDataHexStr1[] = "4869205468657265"; -+char cesaHmacMd5digestHex1[] = "9294727a3638bb1c13f48ef8158bfc9d"; -+char cesaHmacSha1digestHex1[] = "b617318655057264e28bc0b6fb378c8ef146be00"; -+char cesaDataAndMd5digest1[] = "48692054686572659294727a3638bb1c13f48ef8158bfc9d"; -+char cesaDataAndSha1digest1[] = "4869205468657265b617318655057264e28bc0b6fb378c8ef146be00"; -+ -+char cesaAesPlainText[] = "a0a1a2a3a4a5a6a7a8a9aaabacadaeaf" -+ "b0b1b2b3b4b5b6b7b8b9babbbcbdbebf" -+ "c0c1c2c3c4c5c6c7c8c9cacbcccdcecf" -+ "d0d1d2d3d4d5d6d7d8d9dadbdcdddedf"; -+ -+char cesaAes128CipherCbc[] = "c30e32ffedc0774e6aff6af0869f71aa" -+ "0f3af07a9a31a9c684db207eb0ef8e4e" -+ "35907aa632c3ffdf868bb7b29d3d46ad" -+ "83ce9f9a102ee99d49a53e87f4c3da55"; -+ -+char cesaAesIvPlainText[] = "8ce82eefbea0da3c44699ed7db51b7d9" -+ "a0a1a2a3a4a5a6a7a8a9aaabacadaeaf" -+ "b0b1b2b3b4b5b6b7b8b9babbbcbdbebf" -+ "c0c1c2c3c4c5c6c7c8c9cacbcccdcecf" -+ "d0d1d2d3d4d5d6d7d8d9dadbdcdddedf"; -+ -+char cesaAes128IvCipherCbc[] = "8ce82eefbea0da3c44699ed7db51b7d9" -+ "c30e32ffedc0774e6aff6af0869f71aa" -+ "0f3af07a9a31a9c684db207eb0ef8e4e" -+ "35907aa632c3ffdf868bb7b29d3d46ad" -+ "83ce9f9a102ee99d49a53e87f4c3da55"; -+ -+char cesaAesCtrPlain[] = "00E0017B27777F3F4A1786F000000001" -+ "000102030405060708090A0B0C0D0E0F" -+ "101112131415161718191A1B1C1D1E1F" -+ "20212223"; -+ -+char cesaAesCtrCipher[] = "00E0017B27777F3F4A1786F000000001" -+ "C1CF48A89F2FFDD9CF4652E9EFDB72D7" -+ "4540A42BDE6D7836D59A5CEAAEF31053" -+ "25B2072F"; -+ -+ -+ -+/* Input cesaHmacHex3 is '0xdd' repeated 50 times */ -+char cesaHmacMd5digestHex3[] = "56be34521d144c88dbb8c733f0e8b3f6"; -+char cesaHmacSha1digestHex3[] = "125d7342b9ac11cd91a39af48aa17b4f63f175d3"; -+char cesaDataHexStr3[50*2+1] = ""; -+char cesaDataAndMd5digest3[sizeof(cesaDataHexStr3)+sizeof(cesaHmacMd5digestHex3)+8*2+1] = ""; -+char cesaDataAndSha1digest3[sizeof(cesaDataHexStr3)+sizeof(cesaHmacSha1digestHex3)+8*2+1] = ""; -+ -+/* Ascii string is "abc" */ -+char hashHexStr3[] = "616263"; -+char hashMd5digest3[] = "900150983cd24fb0d6963f7d28e17f72"; -+char hashSha1digest3[] = "a9993e364706816aba3e25717850c26c9cd0d89d"; -+ -+char hashHexStr80[] = "31323334353637383930" -+ "31323334353637383930" -+ "31323334353637383930" -+ "31323334353637383930" -+ "31323334353637383930" -+ "31323334353637383930" -+ "31323334353637383930" -+ "31323334353637383930"; -+ -+char hashMd5digest80[] = "57edf4a22be3c955ac49da2e2107b67a"; -+ -+char tripleDesThenMd5digest80[] = "b7726a03aad490bd6c5a452a89a1b271"; -+char tripleDesThenSha1digest80[] = "b2ddeaca91030eab5b95a234ef2c0f6e738ff883"; -+ -+char cbc3desThenMd5digest80[] = "6f463057e1a90e0e91ae505b527bcec0"; -+char cbc3desThenSha1digest80[] = "1b002ed050be743aa98860cf35659646bb8efcc0"; -+ -+char cbcAes128ThenMd5digest80[] = "6b6e863ac5a71d15e3e9b1c86c9ba05f"; -+char cbcAes128ThenSha1digest80[] = "13558472d1fc1c90dffec6e5136c7203452d509b"; -+ -+ -+static MV_CESA_TEST_CASE cesaTestCases[] = -+{ -+ /* plainHexStr cipherHexStr IV crypto mac digest */ -+ /* Length Length Offset */ -+ /*0*/ { NULL, NULL, NULL, 0, 0, -1 }, -+ /*1*/ { cesaPlainHexEbc, cesaCipherHexEcb, NULL, 24, 0, -1 }, -+ /*2*/ { cesaPlainHexCbc, cesaCipherHexCbc, NULL, 24, 0, -1 }, -+ /*3*/ { cesaAesPlainHexEcb, cesaAes128cipherHexEcb, NULL, 16, 0, -1 }, -+ /*4*/ { cesaAesPlainHexEcb, cesaAes192cipherHexEcb, NULL, 16, 0, -1 }, -+ /*5*/ { cesaAesPlainHexEcb, cesaAes256cipherHexEcb, NULL, 16, 0, -1 }, -+ /*6*/ { cesaDataHexStr1, cesaHmacMd5digestHex1, NULL, 0, 8, -1 }, -+ /*7*/ { NULL, cesaDataAndMd5digest1, NULL, 0, 8, -1 }, -+ /*8*/ { cesaDataHexStr3, cesaHmacMd5digestHex3, NULL, 0, 50, -1 }, -+ /*9*/ { NULL, cesaDataAndMd5digest3, NULL, 0, 50, -1 }, -+/*10*/ { cesaAesPlainText, cesaAes128IvCipherCbc, iv5, 64, 0, -1 }, -+/*11*/ { cesaDataHexStr1, cesaHmacSha1digestHex1, NULL, 0, 8, -1 }, -+/*12*/ { NULL, cesaDataAndSha1digest1, NULL, 0, 8, -1 }, -+/*13*/ { cesaDataHexStr3, cesaHmacSha1digestHex3, NULL, 0, 50, -1 }, -+/*14*/ { NULL, cesaDataAndSha1digest3, NULL, 0, 50, -1 }, -+/*15*/ { hashHexStr3, hashMd5digest3, NULL, 0, 3, -1 }, -+/*16*/ { hashHexStr3, hashSha1digest3, NULL, 0, 3, -1 }, -+/*17*/ { hashHexStr80, tripleDesThenMd5digest80, NULL, 80, 80, -1 }, -+/*18*/ { hashHexStr80, tripleDesThenSha1digest80, NULL, 80, 80, -1 }, -+/*19*/ { hashHexStr80, cbc3desThenMd5digest80, iv1, 80, 80, -1 }, -+/*20*/ { hashHexStr80, cbc3desThenSha1digest80, iv1, 80, 80, -1 }, -+/*21*/ { hashHexStr80, cbcAes128ThenMd5digest80, iv5, 80, 80, -1 }, -+/*22*/ { hashHexStr80, cbcAes128ThenSha1digest80, iv5, 80, 80, -1 }, -+/*23*/ { cesaAesCtrPlain, cesaAesCtrCipher, NULL, 36, 0, -1 }, -+/*24*/ { cesaAesIvPlainText, cesaAes128IvCipherCbc, NULL, 64, 0, -1 }, -+/*25*/ { plain3des1, cipher3des1, NULL, 0, 0, -1 }, -+/*26*/ { plain3des2, cipher3desCbc2, iv3des2,0, 0, -1 }, -+/*27*/ { plain3des3, cipher3desCbc3, iv3des3,0, 0, -1 }, -+}; -+ -+ -+/* Key = 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -+ * 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa -+ * Input 0xdd repeated "size" times -+ */ -+static MV_CESA_SIZE_TEST mdMultiSizeTest302[] = -+{ -+ { 80, "7a031a640c14a4872814930b1ef3a5b2" }, -+ { 512, "5488e6c5a14dc72a79f28312ca5b939b" }, -+ { 1000, "d00814f586a8b78a05724239d2531821" }, -+ { 1001, "bf07df7b7f49d3f5b5ecacd4e9e63281" }, -+ { 1002, "1ed4a1a802e87817a819d4e37bb4d0f7" }, -+ { 1003, "5972ab64a4f265ee371dac2f2f137f90" }, -+ { 1004, "71f95e7ec3aa7df2548e90898abdb28e" }, -+ { 1005, "e082790b4857fcfc266e92e59e608814" }, -+ { 1006, "9500f02fd8ac7fde8b10e4fece9a920d" }, -+ { 1336, "e42edcce57d0b75b01aa09d71427948b" }, -+ { 1344, "bb5454ada0deb49ba0a97ffd60f57071" }, -+ { 1399, "0f44d793e744b24d53f44f295082ee8c" }, -+ { 1400, "359de8a03a9b707928c6c60e0e8d79f1" }, -+ { 1401, "e913858b484cbe2b384099ea88d8855b" }, -+ { 1402, "d9848a164af53620e0540c1d7d87629e" }, -+ { 1403, "0c9ee1c2c9ef45e9b625c26cbaf3e822" }, -+ { 1404, "12edd4f609416e3c936170360561b064" }, -+ { 1405, "7fc912718a05446395345009132bf562" }, -+ { 1406, "882f17425e579ff0d85a91a59f308aa0" }, -+ { 1407, "005cae408630a2fb5db82ad9db7e59da" }, -+ { 1408, "64655f8b404b3fea7a3e3e609bc5088f" }, -+ { 1409, "4a145284a7f74e01b6bb1a0ec6a0dd80" }, -+ { 2048, "67caf64475650732def374ebb8bde3fd" }, -+ { 2049, "6c84f11f472825f7e6cd125c2981884b" }, -+ { 2050, "8999586754a73a99efbe4dbad2816d41" }, -+ { 2051, "ba6946b610e098d286bc81091659dfff" }, -+ { 2052, "d0afa01c92d4d13def2b024f36faed83" }, -+ { 3072, "61d8beac61806afa2585d74a9a0e6974" }, -+ { 3074, "f6501a28dcc24d1e4770505c51a87ed3" }, -+ { 3075, "ea4a6929be67e33e61ff475369248b73" }, -+ { 4048, "aa8c4d68f282a07e7385acdfa69f4bed" }, -+ { 4052, "afb5ed2c0e1d430ea59e59ed5ed6b18a" }, -+ { 4058, "9e8553f9bdd43aebe0bd729f0e600c99" }, -+ { 6144, "f628f3e5d183fe5cdd3a5abee39cf872" }, -+ { 6150, "89a3efcea9a2f25f919168ad4a1fd292" }, -+ { 6400, "cdd176b7fb747873efa4da5e32bdf88f" }, -+ { 6528, "b1d707b027354aca152c45ee559ccd3f" }, -+ { 8192, "c600ea4429ac47f9941f09182166e51a" }, -+ {16384, "16e8754bfbeb4c649218422792267a37" }, -+ {18432, "0fd0607521b0aa8b52219cfbe215f63e" }, -+ { 0, NULL }, -+}; -+ -+/* Key = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ */ -+static MV_CESA_SIZE_TEST mdMultiSizeTest304[] = -+{ -+ { 80, "a456c4723fee6068530af5a2afa71627" }, -+ { 512, "f85c2a2344f5de68b432208ad13e5794" }, -+ { 1000, "35464d6821fd4a293a41eb84e274c8c5" }, -+ { 1001, "c08eedbdce60cceb54bc2d732bb32c8b" }, -+ { 1002, "5664f71800c011cc311cb6943339c1b8" }, -+ { 1003, "779c723b044c585dc7802b13e8501bdc" }, -+ { 1004, "55e500766a2c307bc5c5fdd15e4cacd4" }, -+ { 1005, "d5f978954f5c38529d1679d2b714f068" }, -+ { 1006, "cd3efc827ce628b7281b72172693abf9" }, -+ { 1336, "6f04479910785878ae6335b8d1e87edf" }, -+ { 1344, "b6d27b50c2bce1ba2a8e1b5cc4324368" }, -+ { 1399, "65f70a1d4c86e5eaeb0704c8a7816795" }, -+ { 1400, "3394b5adc4cb3ff98843ca260a44a88a" }, -+ { 1401, "3a06f3582033a66a4e57e0603ce94e74" }, -+ { 1402, "e4d97f5ed51edc48abfa46eeb5c31752" }, -+ { 1403, "3d05e40b080ee3bedf293cb87b7140e7" }, -+ { 1404, "8cf294fc3cd153ab18dccb2a52cbf244" }, -+ { 1405, "d1487bd42f6edd9b4dab316631159221" }, -+ { 1406, "0527123b6bf6936cf5d369dc18c6c70f" }, -+ { 1407, "3224a06639db70212a0cd1ae1fcc570a" }, -+ { 1408, "a9e13335612c0356f5e2c27086e86c43" }, -+ { 1409, "a86d1f37d1ed8a3552e9a4f04dceea98" }, -+ { 2048, "396905c9b961cd0f6152abfb69c4449c" }, -+ { 2049, "49f39bff85d9dcf059fadb89efc4a70f" }, -+ { 2050, "3a2b4823bc4d0415656550226a63e34a" }, -+ { 2051, "dec60580d406c782540f398ad0bcc7e0" }, -+ { 2052, "32f76610a14310309eb748fe025081bf" }, -+ { 3072, "45edc1a42bf9d708a621076b63b774da" }, -+ { 3074, "9be1b333fe7c0c9f835fb369dc45f778" }, -+ { 3075, "8c06fcac7bd0e7b7a17fd6508c09a549" }, -+ { 4048, "0ddaef848184bf0ad98507a10f1e90e4" }, -+ { 4052, "81976bcaeb274223983996c137875cb8" }, -+ { 4058, "0b0a7a1c82bc7cbc64d8b7cd2dc2bb22" }, -+ { 6144, "1c24056f52725ede2dff0d7f9fc9855f" }, -+ { 6150, "b7f4b65681c4e43ee68ca466ca9ca4ec" }, -+ { 6400, "443bbaab9f7331ddd4bf11b659cd43c8" }, -+ { 6528, "216f44f23047cfee03a7a64f88f9a995" }, -+ { 8192, "ac7a993b2cad54879dba1bde63e39097" }, -+ { 8320, "55ed7be9682d6c0025b3221a62088d08" }, -+ {16384, "c6c722087653b62007aea668277175e5" }, -+ {18432, "f1faca8e907872c809e14ffbd85792d6" }, -+ { 0, NULL }, -+}; -+ -+/* HASH-MD5 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ * repeated "size" times -+ */ -+static MV_CESA_SIZE_TEST mdMultiSizeTest305[] = -+{ -+ { 80, "57edf4a22be3c955ac49da2e2107b67a" }, -+ { 512, "c729ae8f0736cc377a9767a660eaa04e" }, -+ { 1000, "f1257a8659eb92d36fe14c6bf3852a6a" }, -+ { 1001, "f8a46fe8ea04fdc8c7de0e84042d3878" }, -+ { 1002, "da188dd67bff87d58aa3c02af2d0cc0f" }, -+ { 1003, "961753017feee04c9b93a8e51658a829" }, -+ { 1004, "dd68c4338608dcc87807a711636bf2af" }, -+ { 1005, "e338d567d3ce66bf69ada29658a8759b" }, -+ { 1006, "443c9811e8b92599b0b149e8d7ec700a" }, -+ { 1336, "89a98511706008ba4cbd0b4a24fa5646" }, -+ { 1344, "335a919805f370b9e402a62c6fe01739" }, -+ { 1399, "5d18d0eddcd84212fe28d812b5e80e3b" }, -+ { 1400, "6b695c240d2dffd0dffc99459ca76db6" }, -+ { 1401, "49590f61298a76719bc93a57a30136f5" }, -+ { 1402, "94c2999fa3ef1910a683d69b2b8476f2" }, -+ { 1403, "37073a02ab00ecba2645c57c228860db" }, -+ { 1404, "1bcd06994fce28b624f0c5fdc2dcdd2b" }, -+ { 1405, "11b93671a64c95079e8cf9e7cddc8b3d" }, -+ { 1406, "4b6695772a4c66313fa4871017d05f36" }, -+ { 1407, "d1539b97fbfda1c075624e958de19c5b" }, -+ { 1408, "b801b9b69920907cd018e8063092ede9" }, -+ { 1409, "b765f1406cfe78e238273ed01bbcaf7e" }, -+ { 2048, "1d7e2c64ac29e2b3fb4c272844ed31f5" }, -+ { 2049, "71d38fac49c6b1f4478d8d88447bcdd0" }, -+ { 2050, "141c34a5592b1bebfa731e0b23d0cdba" }, -+ { 2051, "c5e1853f21c59f5d6039bd13d4b380d8" }, -+ { 2052, "dd44a0d128b63d4b5cccd967906472d7" }, -+ { 3072, "37d158e33b21390822739d13db7b87fe" }, -+ { 3074, "aef3b209d01d39d0597fe03634bbf441" }, -+ { 3075, "335ffb428eabf210bada96d74d5a4012" }, -+ { 4048, "2434c2b43d798d2819487a886261fc64" }, -+ { 4052, "ac2fa84a8a33065b2e92e36432e861f8" }, -+ { 4058, "856781f85616c341c3533d090c1e1e84" }, -+ { 6144, "e5d134c652c18bf19833e115f7a82e9b" }, -+ { 6150, "a09a353be7795fac2401dac5601872e6" }, -+ { 6400, "08b9033ac6a1821398f50af75a2dbc83" }, -+ { 6528, "3d47aa193a8540c091e7e02f779e6751" }, -+ { 8192, "d3164e710c0626f6f395b38f20141cb7" }, -+ { 8320, "b727589d9183ff4e8491dd24466974a3" }, -+ {16384, "3f54d970793d2274d5b20d10a69938ac" }, -+ {18432, "f558511dcf81985b7a1bb57fad970531" }, -+ { 0, NULL }, -+}; -+ -+ -+/* Key = 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -+ * 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa -+ * 0xaa, 0xaa, 0xaa, 0xaa -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ */ -+static MV_CESA_SIZE_TEST shaMultiSizeTest402[] = -+{ -+ { 80, "e812f370e659705a1649940d1f78cd7af18affd3" }, -+ { 512, "e547f886b2c15d995ed76a8a924cb408c8080f66" }, -+ { 1000, "239443194409f1a5342ecde1a092c8f3a3ed790a" }, -+ { 1001, "f278ab9a102850a9f48dc4e9e6822afe2d0c52b5" }, -+ { 1002, "8bcc667df5ab6ece988b3af361d09747c77f4e72" }, -+ { 1003, "0fae6046c7dc1d3e356b25af836f6077a363f338" }, -+ { 1004, "0ea48401cc92ae6bc92ae76685269cb0167fbe1a" }, -+ { 1005, "ecbcd7c879b295bafcd8766cbeac58cc371e31d1" }, -+ { 1006, "eb4a4a3d07d1e9a15e6f1ab8a9c47f243e27324c" }, -+ { 1336, "f5950ee1d77c10e9011d2149699c9366fe52529c" }, -+ { 1344, "b04263604a63c351b0b3b9cf1785b4bdba6c8838" }, -+ { 1399, "8cb1cff61d5b784045974a2fc69386e3b8d24218" }, -+ { 1400, "9bb2f3fcbeddb2b90f0be797cd647334a2816d51" }, -+ { 1401, "23ae462a7a0cb440f7445791079a5d75a535dd33" }, -+ { 1402, "832974b524a4d3f9cc2f45a3cabf5ccef65cd2aa" }, -+ { 1403, "d1c683742fe404c3c20d5704a5430e7832a7ec95" }, -+ { 1404, "867c79042e64f310628e219d8b85594cd0c7adc3" }, -+ { 1405, "c9d81d49d13d94358f56ccfd61af02b36c69f7c3" }, -+ { 1406, "0df43daab2786172f9b8d07d61f14a070cf1287a" }, -+ { 1407, "0fd8f3ad7f169534b274d4c66bbddd89f759e391" }, -+ { 1408, "3987511182b18473a564436003139b808fa46343" }, -+ { 1409, "ef667e063c9e9f539a8987a8d0bd3066ee85d901" }, -+ { 2048, "921109c99f3fedaca21727156d5f2b4460175327" }, -+ { 2049, "47188600dd165eb45f27c27196d3c46f4f042c1b" }, -+ { 2050, "8831939904009338de10e7fa670847041387807d" }, -+ { 2051, "2f8ebb5db2997d614e767be1050366f3641e7520" }, -+ { 2052, "669e51cd730dae158d3bef8adba075bd95a0d011" }, -+ { 3072, "cfee66cfd83abc8451af3c96c6b35a41cc6c55f5" }, -+ { 3074, "216ea26f02976a261b7d21a4dd3085157bedfabd" }, -+ { 3075, "bd612ebba021fd8e012b14c3bd60c8c5161fabc0" }, -+ { 4048, "c2564c1fdf2d5e9d7dde7aace2643428e90662e8" }, -+ { 4052, "91ce61fe924b445dfe7b5a1dcd10a27caec16df6" }, -+ { 4058, "db2a9be5ee8124f091c7ebd699266c5de223c164" }, -+ { 6144, "855109903feae2ba3a7a05a326b8a171116eb368" }, -+ { 6150, "37520bb3a668294d9c7b073e7e3daf8fee248a78" }, -+ { 6400, "60a353c841b6d2b1a05890349dad2fa33c7536b7" }, -+ { 6528, "9e53a43a69bb42d7c8522ca8bd632e421d5edb36" }, -+ { 8192, "a918cb0da862eaea0a33ee0efea50243e6b4927c" }, -+ { 8320, "29a5dcf55d1db29cd113fcf0572ae414f1c71329" }, -+ {16384, "6fb27966138e0c8d5a0d65ace817ebd53633cee1" }, -+ {18432, "ca09900d891c7c9ae2a559b10f63a217003341c1" }, -+ { 0, NULL }, -+}; -+ -+/* Key = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 -+ * 0x11, 0x12, 0x13, 0x14 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ */ -+static MV_CESA_SIZE_TEST shaMultiSizeTest404[] = -+{ -+ { 80, "beaf20a34b06a87558d156c0949bc3957d40222e" }, -+ { 512, "3353955358d886bc2940a3c7f337ff7dafb59c7b" }, -+ { 1000, "8737a542c5e9b2b6244b757ebb69d5bd602a829f" }, -+ { 1001, "fd9e7582d8a5d3c9fe3b923e4e6a41b07a1eb4d4" }, -+ { 1002, "a146d14a6fc3c274ff600568f4d75b977989e00d" }, -+ { 1003, "be22601bbc027ddef2dec97d30b3dc424fd803c5" }, -+ { 1004, "3e71fe99b2fe2b7bfdf4dbf0c7f3da25d7ea35e7" }, -+ { 1005, "2c422735d7295408fddd76f5e8a83a2a8da13df3" }, -+ { 1006, "6d875319049314b61855101a647b9ba3313428e6" }, -+ { 1336, "c1631ea80bad9dc43a180712461b65a0598c711c" }, -+ { 1344, "816069bf91d34581005746e2e0283d0f9c7b7605" }, -+ { 1399, "4e139866dc61cfcb8b67ca2ebd637b3a538593af" }, -+ { 1400, "ff2a0f8dd2b02c5417910f6f55d33a78e081a723" }, -+ { 1401, "ab00c12be62336964cbce31ae97fe2a0002984d5" }, -+ { 1402, "61349e7f999f3a1acc56c3e9a5060a9c4a7b05b6" }, -+ { 1403, "3edbc0f61e435bc1317fa27d840076093fb79353" }, -+ { 1404, "d052c6dfdbe63d45dab23ef9893e2aa4636aca1e" }, -+ { 1405, "0cc16b7388d67bf0add15a31e6e6c753cfae4987" }, -+ { 1406, "c96ba7eaad74253c38c22101b558d2850b1d1b90" }, -+ { 1407, "3445428a40d2c6556e7c55797ad8d323b61a48d9" }, -+ { 1408, "8d6444f937a09317c89834187b8ea9b8d3a8c56b" }, -+ { 1409, "c700acd3ecd19014ea2bdb4d42510c467e088475" }, -+ { 2048, "ee27d2a0cb77470c2f496212dfd68b5bb7b04e4b" }, -+ { 2049, "683762d7a02983b26a6d046e6451d9cd82c25932" }, -+ { 2050, "0fd20f1d55a9ee18363c2a6fd54aa13aee69992f" }, -+ { 2051, "86c267d8cc4bc8d59090e4f8b303da960fd228b7" }, -+ { 2052, "452395ae05b3ec503eea34f86fc0832485ad97c1" }, -+ { 3072, "75198e3cfd0b9bcff2dabdf8e38e6fdaa33ca49a" }, -+ { 3074, "4e24785ef080141ce4aab4675986d9acea624d7c" }, -+ { 3075, "3a20c5978dd637ec0e809bf84f0d9ccf30bc65bf" }, -+ { 4048, "3c32da256be7a7554922bf5fed51b0d2d09e59ad" }, -+ { 4052, "fff898426ea16e54325ae391a32c6c9bce4c23c0" }, -+ { 4058, "c800b9e562e1c91e1310116341a3c91d37f848ec" }, -+ { 6144, "d91d509d0cc4376c2d05bf9a5097717a373530e6" }, -+ { 6150, "d957030e0f13c5df07d9eec298542d8f94a07f12" }, -+ { 6400, "bb745313c3d7dc17b3f955e5534ad500a1082613" }, -+ { 6528, "77905f80d9ca82080bbb3e5654896dabfcfd1bdb" }, -+ { 8192, "5237fd9a81830c974396f99f32047586612ff3c0" }, -+ { 8320, "57668e28d5f2dba0839518a11db0f6af3d7e08bf" }, -+ {16384, "62e093fde467f0748087beea32e9af97d5c61241" }, -+ {18432, "845fb33130c7d6ea554fd5aacb9c50cf7ccb5929" }, -+ { 0, NULL }, -+}; -+ -+/* HASH-SHA1 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ * repeated "size" times -+ */ -+static MV_CESA_SIZE_TEST shaMultiSizeTest405[] = -+{ -+ { 80, "50abf5706a150990a08b2c5ea40fa0e585554732" }, -+ { 512, "f14516a08948fa27917a974d219741a697ba0087" }, -+ { 1000, "0bd18c378d5788817eb4f1e5dc07d867efa5cbf4" }, -+ { 1001, "ca29b85c35db1b8aef83c977893a11159d1b7aa2" }, -+ { 1002, "d83bc973eaaedb8a31437994dabbb3304b0be086" }, -+ { 1003, "2cf7bbef0acd6c00536b5c58ca470df9a3a90b6c" }, -+ { 1004, "e4375d09b1223385a8a393066f8209acfd936a80" }, -+ { 1005, "1029b38043e027745d019ce1d2d68e3d8b9d8f99" }, -+ { 1006, "deea16dcebbd8ac137e2b984deb639b9fb5e9680" }, -+ { 1336, "ea031b065fff63dcfb6a41956e4777520cdbc55d" }, -+ { 1344, "b52096c6445e6c0a8355995c70dc36ae186c863c" }, -+ { 1399, "cde2f6f8379870db4b32cf17471dc828a8dbff2b" }, -+ { 1400, "e53ff664064bc09fe5054c650806bd42d8179518" }, -+ { 1401, "d1156db5ddafcace64cdb510ff0d4af9b9a8ad64" }, -+ { 1402, "34ede0e9a909dd84a2ae291539105c0507b958e1" }, -+ { 1403, "a772ca3536da77e6ad3251e4f9e1234a4d7b87c0" }, -+ { 1404, "29740fd2b04e7a8bfd32242db6233156ad699948" }, -+ { 1405, "65b17397495b70ce4865dad93bf991b74c97cce1" }, -+ { 1406, "a7ee89cd0754061fdb91af7ea6abad2c69d542e3" }, -+ { 1407, "3eebf82f7420188e23d328b7ce93580b279a5715" }, -+ { 1408, "e08d3363a8b9a490dfb3a4c453452b8f114deeec" }, -+ { 1409, "95d74df739181a4ff30b8c39e28793a36598e924" }, -+ { 2048, "aa40262509c2abf84aab0197f83187fc90056d91" }, -+ { 2049, "7dec28ef105bc313bade8d9a7cdeac58b99de5ea" }, -+ { 2050, "d2e30f77ec81197de20f56588a156094ecb88450" }, -+ { 2051, "6b22ccc874833e96551a39da0c0edcaa0d969d92" }, -+ { 2052, "f843141e57875cd669af58744bc60aa9ea59549c" }, -+ { 3072, "09c5fedeaa62c132e673cc3c608a00142273d086" }, -+ { 3074, "b09e95eea9c7b1b007a58accec488301901a7f3d" }, -+ { 3075, "e6226b77b4ada287a8c9bbcf4ed71eec5ce632dc" }, -+ { 4048, "e99394894f855821951ddddf5bfc628547435f5c" }, -+ { 4052, "32d2f1af38be9cfba6cd03d55a254d0b3e1eb382" }, -+ { 4058, "d906552a4f2aca3a22e1fecccbcd183d7289d0ef" }, -+ { 6144, "2e7f62d35a860988e1224dc0543204af19316041" }, -+ { 6150, "d6b89698ee133df46fec9d552fadc328aa5a1b51" }, -+ { 6400, "dff50e90c46853988fa3a4b4ce5dda6945aae976" }, -+ { 6528, "9e63ec0430b96db02d38bc78357a2f63de2ab7f8" }, -+ { 8192, "971eb71ed60394d5ab5abb12e88420bdd41b5992" }, -+ { 8320, "91606a31b46afeaac965cecf87297e791b211013" }, -+ {16384, "547f830a5ec1f5f170ce818f156b1002cabc7569" }, -+ {18432, "f16f272787f3b8d539652e4dc315af6ab4fda0ef" }, -+ { 0, NULL }, -+}; -+ -+/* CryptoKey = 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef; -+ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ * Note: only sizes aligned to 3DES block size (8 bytes) allowed -+ */ -+static MV_CESA_SIZE_TEST tripleDesMdMultiSizeTest502[] = -+{ -+ { 64, "9586962a2aaaef28803dec2e17807a7f" }, -+ { 80, "b7726a03aad490bd6c5a452a89a1b271" }, -+ { 352, "f1ed9563aecc3c0d2766eb2bed3b4e4c" }, -+ { 512, "0f9decb11ab40fe86f4d4d9397bc020e" }, -+ { 1000, "3ba69deac12cab8ff9dff7dbd9669927" }, -+ { 1336, "6cf47bf1e80e03e2c1d0945bc50d37d2" }, -+ { 1344, "4be388dab21ceb3fa1b8d302e9b821f7" }, -+ { 1400, "a58b79fb21dd9bfc6ec93e3b99fb0ef1" }, -+ { 1408, "8bc97379fc2ac3237effcdd4f7a86528" }, -+ { 2048, "1339f03ab3076f25a20bc4cba16eb5bf" }, -+ { 3072, "731204d2d90c4b36ae41f5e1fb874288" }, -+ { 4048, "c028d998cfda5642547b7e1ed5ea16e4" }, -+ { 6144, "b1b19cd910cc51bd22992f1e59f1e068" }, -+ { 6400, "44e4613496ba622deb0e7cb768135a2f" }, -+ { 6528, "3b06b0a86f8db9cd67f9448dfcf10549" }, -+ { 8192, "d581780b7163138a0f412be681457d82" }, -+ {16384, "03b8ac05527faaf1bed03df149c65ccf" }, -+ {18432, "677c8a86a41dab6c5d81b85b8fb10ff6" }, -+ { 0, NULL }, -+}; -+ -+ -+/* CryptoKey = 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef; -+ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 -+ * 0x11, 0x12, 0x13, 0x14 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ * Note: only sizes aligned to 3DES block size (8 bytes) allowed -+ */ -+static MV_CESA_SIZE_TEST tripleDesShaMultiSizeTest503[] = -+{ -+ { 64, "44a1e9bcbfc1429630d9ea68b7a48b0427a684f2" }, -+ { 80, "b2ddeaca91030eab5b95a234ef2c0f6e738ff883" }, -+ { 352, "4b91864c7ff629bdff75d9726421f76705452aaf" }, -+ { 512, "6dd37faceeb2aa98ba74f4242ed6734a4d546af5" }, -+ { 1000, "463661c30300be512a9df40904f0757cde5f1141" }, -+ { 1336, "b931f831d9034fe59c65176400b039fe9c1f44a5" }, -+ { 1344, "af8866b1cd4a4887d6185bfe72470ffdfb3648e1" }, -+ { 1400, "49c6caf07296d5e31d2504d088bc5b20c3ee7cdb" }, -+ { 1408, "fcae8deedbc6ebf0763575dc7e9de075b448a0f4" }, -+ { 2048, "edece5012146c1faa0dd10f50b183ba5d2af58ac" }, -+ { 3072, "5b83625adb43a488b8d64fecf39bb766818547b7" }, -+ { 4048, "d2c533678d26c970293af60f14c8279dc708bfc9" }, -+ { 6144, "b8f67af4f991b08b725f969b049ebf813bfacc5c" }, -+ { 6400, "d9a6c7f746ac7a60ef2edbed2841cf851c25cfb0" }, -+ { 6528, "376792b8c8d18161d15579fb7829e6e3a27e9946" }, -+ { 8192, "d890eabdca195b34ef8724b28360cffa92ae5655" }, -+ {16384, "a167ee52639ec7bf19aee9c6e8f76667c14134b9" }, -+ {18432, "e4396ab56f67296b220985a12078f4a0e365d2cc" }, -+ { 0, NULL }, -+}; -+ -+/* CryptoKey = 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef -+ * IV = 0x12345678, 0x90abcdef -+ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ * Note: only sizes aligned to 3DES block size (8 bytes) allowed -+ */ -+static MV_CESA_SIZE_TEST cbc3desMdMultiSizeTest504[] = -+{ -+ { 64, "8d10e00802460ede0058c139ba48bd2d" }, -+ { 80, "6f463057e1a90e0e91ae505b527bcec0" }, -+ { 352, "4938d48bdf86aece2c6851e7c6079788" }, -+ { 512, "516705d59f3cf810ebf2a13a23a7d42e" }, -+ { 1000, "a5a000ee5c830e67ddc6a2d2e5644b31" }, -+ { 1336, "44af60087b74ed07950088efbe3b126a" }, -+ { 1344, "1f5b39e0577920af731dabbfcf6dfc2a" }, -+ { 1400, "6804ea640e29b9cd39e08bc37dbce734" }, -+ { 1408, "4fb436624b02516fc9d1535466574bf9" }, -+ { 2048, "c909b0985c423d8d86719f701e9e83db" }, -+ { 3072, "cfe0bc34ef97213ee3d3f8b10122db21" }, -+ { 4048, "03ea10b5ae4ddeb20aed6af373082ed1" }, -+ { 6144, "b9a0ff4f87fc14b3c2dc6f0ed0998fdf" }, -+ { 6400, "6995f85d9d4985dd99e974ec7dda9dd6" }, -+ { 6528, "bbbb548ce2fa3d58467f6a6a5168a0e6" }, -+ { 8192, "afe101fbe745bb449ae4f50d10801456" }, -+ {16384, "9741706d0b1c923340c4660ff97cacdf" }, -+ {18432, "b0217becb73cb8f61fd79c7ce9d023fb" }, -+ { 0, NULL }, -+}; -+ -+ -+/* CryptoKey = 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef; -+ * IV = 0x12345678, 0x90abcdef -+ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 -+ * 0x11, 0x12, 0x13, 0x14 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ * Note: only sizes aligned to 3DES block size (8 bytes) allowed -+ */ -+static MV_CESA_SIZE_TEST cbc3desShaMultiSizeTest505[] = -+{ -+ { 64, "409187e5bdb0be4a7754ca3747f7433dc4f01b98" }, -+ { 80, "1b002ed050be743aa98860cf35659646bb8efcc0" }, -+ { 352, "6cbf7ebe50fa4fa6eecc19eca23f9eae553ccfff" }, -+ { 512, "cfb5253fb4bf72b743320c30c7e48c54965853b0" }, -+ { 1000, "95e04e1ca2937e7c5a9aba9e42d2bcdb8a7af21f" }, -+ { 1336, "3b5c1f5eee5837ebf67b83ae01405542d77a6627" }, -+ { 1344, "2b3d42ab25615437f98a1ee310b81d07a02badc2" }, -+ { 1400, "7f8687df7c1af44e4baf3c934b6cca5ab6bc993e" }, -+ { 1408, "473a581c5f04f7527d50793c845471ac87e86430" }, -+ { 2048, "e41d20cae7ebe34e6e828ed62b1e5734019037bb" }, -+ { 3072, "275664afd7a561d804e6b0d204e53939cde653ae" }, -+ { 4048, "0d220cc5b34aeeb46bbbd637dde6290b5a8285a3" }, -+ { 6144, "cb393ddcc8b1c206060625b7d822ef9839e67bc5" }, -+ { 6400, "dd3317e2a627fc04800f74a4b05bfda00fab0347" }, -+ { 6528, "8a74c3b2441ab3f5a7e08895cc432566219a7c41" }, -+ { 8192, "b8e6ef3a549ed0e005bd5b8b1a5fe6689e9711a7" }, -+ {16384, "55f59404008276cdac0e2ba0d193af2d40eac5ce" }, -+ {18432, "86ae6c4fc72369a54cce39938e2d0296cd9c6ec5" }, -+ { 0, NULL }, -+}; -+ -+ -+/* CryptoKey = 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef -+ * IV = 0x12345678, 0x90abcdef -+ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ * Note: only sizes aligned to AES block size (16 bytes) allowed -+ */ -+static MV_CESA_SIZE_TEST cbcAes128md5multiSizeTest506[] = -+{ -+ { 16, "7ca4c2ba866751598720c5c4aa0d6786" }, -+ { 64, "7dba7fb988e80da609b1fea7254bced8" }, -+ { 80, "6b6e863ac5a71d15e3e9b1c86c9ba05f" }, -+ { 352, "a1ceb9c2e3021002400d525187a9f38c" }, -+ { 512, "596c055c1c55db748379223164075641" }, -+ { 1008, "f920989c02f3b3603f53c99d89492377" }, -+ { 1344, "2e496b73759d77ed32ea222dbd2e7b41" }, -+ { 1408, "7178c046b3a8d772efdb6a71c4991ea4" }, -+ { 2048, "a917f0099c69eb94079a8421714b6aad" }, -+ { 3072, "693cd5033d7f5391d3c958519fa9e934" }, -+ { 4048, "139dca91bcff65b3c40771749052906b" }, -+ { 6144, "428d9cef6df4fb70a6e9b6bbe4819e55" }, -+ { 6400, "9c0b909e76daa811e12b1fc17000a0c4" }, -+ { 6528, "ad876f6297186a7be1f1b907ed860eda" }, -+ { 8192, "479cbbaca37dd3191ea1f3e8134a0ef4" }, -+ {16384, "60fda559c74f91df538100c9842f2f15" }, -+ {18432, "4a3eb1cba1fa45f3981270953f720c42" }, -+ { 0, NULL }, -+}; -+ -+ -+/* CryptoKey = 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef; -+ * IV = 0x12345678, 0x90abcdef -+ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 -+ * 0x11, 0x12, 0x13, 0x14 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ * Note: only sizes aligned to AES block size (16 bytes) allowed -+ */ -+static MV_CESA_SIZE_TEST cbcAes128sha1multiSizeTest507[] = -+{ -+ { 16, "9aa8dc1c45f0946daf78057fa978759c625c1fee" }, -+ { 64, "9f588fc1ede851e5f8b20256abc9979465ae2189" }, -+ { 80, "13558472d1fc1c90dffec6e5136c7203452d509b" }, -+ { 352, "6b93518e006cfaa1f7adb24615e7291fb0a27e06" }, -+ { 512, "096874951a77fbbf333e49d80c096ee2016e09bd" }, -+ { 1008, "696fc203c2e4b5ae0ec5d1db3f623c490bc6dbac" }, -+ { 1344, "79bf77509935ccd3528caaac6a5eb6481f74029b" }, -+ { 1408, "627f9462b95fc188e8cfa7eec15119bdc5d4fcf1" }, -+ { 2048, "3d50d0c005feba92fe41502d609fced9c882b4d1" }, -+ { 3072, "758807e5b983e3a91c06fb218fe0f73f77111e94" }, -+ { 4048, "ca90e85242e33f005da3504416a52098d0d31fb2" }, -+ { 6144, "8044c1d4fd06642dfc46990b4f18b61ef1e972cf" }, -+ { 6400, "166f1f4ea57409f04feba9fb1e39af0e00bd6f43" }, -+ { 6528, "0389016a39485d6e330f8b4215ddf718b404f7e9" }, -+ { 8192, "6df7ee2a8b61d6f7f860ce8dbf778f0c2a5b508b" }, -+ {16384, "a70a6d8dfa1f91ded621c3dbaed34162bc48783f" }, -+ {18432, "8dfad627922ce15df1eed10bdbed49244efa57db" }, -+ { 0, NULL }, -+}; -+ -+ -+void cesaTestPrintStatus(void); -+ -+ -+/*------------------------- LOCAL FUNCTIONs ---------------------------------*/ -+MV_STATUS testCmd(int sid, int iter, MV_CESA_COMMAND* pCmd, -+ MV_CESA_TEST_SESSION* pTestSession, MV_U8* pIV, int ivSize); -+MV_STATUS testClose(int idx); -+MV_STATUS testOpen(int idx); -+void close_session(int sid); -+void cesaTestCheckReady(const MV_CESA_RESULT *r); -+void cesaCheckReady(MV_CESA_RESULT* r); -+void printTestResults(int idx, MV_STATUS status, int checkMode); -+void cesaLastResult(void); -+void cesaTestPrintReq(int req, int offset, int size); -+ -+void cesaTestPrintStatus(void); -+void cesaTestPrintSession(int idx); -+void sizeTest(int testIdx, int iter, int checkMode); -+void multiTest(int iter, int reqSize, int checkMode); -+void oneTest(int testIdx, int caseIdx,int iter, int reqSize, int checkMode); -+void multiSizeTest(int idx, int iter, int checkMode, char* inputData); -+void cesaTest(int iter, int reqSize, int checkMode); -+void cesaOneTest(int testIdx, int caseIdx,int iter, int reqSize, int checkMode); -+void combiTest(int iter, int reqSize, int checkMode); -+void shaTest(int iter, int reqSize, int checkMode); -+void mdTest(int iter, int reqSize, int checkMode); -+void aesTest(int iter, int reqSize, int checkMode); -+void tripleDesTest(int iter, int reqSize, int checkMode); -+void desTest(int iter, int reqSize, int checkMode); -+void cesaTestStop(void); -+MV_STATUS testRun(int idx, int caseIdx, int iter,int reqSize, int checkMode); -+void cesaTestStart(int bufNum, int bufSize); -+ -+ -+static MV_U32 getRate(MV_U32* remainder) -+{ -+ MV_U32 kBits, milliSec, rate; -+ -+ milliSec = 0; -+ if( (cesaEndTicks - cesaBeginTicks) > 0) -+ { -+ milliSec = CESA_TEST_TICK_TO_MS(cesaEndTicks - cesaBeginTicks); -+ } -+ if(milliSec == 0) -+ { -+ if(remainder != NULL) -+ *remainder = 0; -+ return 0; -+ } -+ -+ kBits = (cesaIteration*cesaRateSize*8)/1000; -+ rate = kBits/milliSec; -+ if(remainder != NULL) -+ *remainder = ((kBits % milliSec)*10)/milliSec; -+ -+ return rate; -+} -+ -+static char* extractMbuf(MV_CESA_MBUF *pMbuf, -+ int offset, int size, char* hexStr) -+{ -+ mvCesaCopyFromMbuf((MV_U8*)cesaBinBuffer, pMbuf, offset, size); -+ mvBinToHex((const MV_U8*)cesaBinBuffer, hexStr, size); -+ -+ return hexStr; -+} -+ -+static MV_BOOL cesaCheckMbuf(MV_CESA_MBUF *pMbuf, -+ const char* hexString, int offset, -+ int checkSize) -+{ -+ MV_BOOL isFailed = MV_FALSE; -+ MV_STATUS status; -+ int size = strlen(hexString)/2; -+ int checkedSize = 0; -+/* -+ mvOsPrintf("cesaCheckMbuf: pMbuf=%p, offset=%d, checkSize=%d, mBufSize=%d\n", -+ pMbuf, offset, checkSize, pMbuf->mbufSize); -+*/ -+ if(pMbuf->mbufSize < (checkSize + offset)) -+ { -+ mvOsPrintf("checkSize (%d) is too large: offset=%d, mbufSize=%d\n", -+ checkSize, offset, pMbuf->mbufSize); -+ return MV_TRUE; -+ } -+ status = mvCesaCopyFromMbuf((MV_U8*)cesaBinBuffer, pMbuf, offset, checkSize); -+ if(status != MV_OK) -+ { -+ mvOsPrintf("CesaTest: Can't copy %d bytes from Mbuf=%p to checkBuf=%p\n", -+ checkSize, pMbuf, cesaBinBuffer); -+ return MV_TRUE; -+ } -+/* -+ mvDebugMemDump(cesaBinBuffer, size, 1); -+*/ -+ mvHexToBin(hexString, (MV_U8*)cesaExpBinBuffer, size); -+ -+ /* Compare buffers */ -+ while(checkSize > checkedSize) -+ { -+ size = MV_MIN(size, (checkSize - checkedSize)); -+ if(memcmp(cesaExpBinBuffer, &cesaBinBuffer[checkedSize], size) != 0) -+ { -+ mvOsPrintf("CheckMbuf failed: checkSize=%d, size=%d, checkedSize=%d\n", -+ checkSize, size, checkedSize); -+ mvDebugMemDump(&cesaBinBuffer[checkedSize], size, 1); -+ mvDebugMemDump(cesaExpBinBuffer, size, 1); -+ -+ isFailed = MV_TRUE; -+ break; -+ } -+ checkedSize += size; -+ } -+ -+ return isFailed; -+} -+ -+static MV_STATUS cesaSetMbuf(MV_CESA_MBUF *pMbuf, -+ const char* hexString, -+ int offset, int reqSize) -+{ -+ MV_STATUS status = MV_OK; -+ int copySize, size = strlen(hexString)/2; -+ -+ mvHexToBin(hexString, (MV_U8*)cesaBinBuffer, size); -+ -+ copySize = 0; -+ while(reqSize > copySize) -+ { -+ size = MV_MIN(size, (reqSize - copySize)); -+ -+ status = mvCesaCopyToMbuf((MV_U8*)cesaBinBuffer, pMbuf, offset+copySize, size); -+ if(status != MV_OK) -+ { -+ mvOsPrintf("cesaSetMbuf Error: Copy %d of %d bytes to MBuf\n", -+ copySize, reqSize); -+ break; -+ } -+ copySize += size; -+ } -+ pMbuf->mbufSize = offset+copySize; -+ return status; -+} -+ -+static MV_CESA_TEST_SESSION* getTestSessionDb(int idx, int* pTestIdx) -+{ -+ int testIdx, dbIdx = idx/100; -+ -+ if(dbIdx > MAX_TEST_TYPE) -+ { -+ mvOsPrintf("Wrong index %d - No such test type\n", idx); -+ return NULL; -+ } -+ testIdx = idx % 100; -+ -+ if(testIdx >= cesaTestsDB[dbIdx].numSessions) -+ { -+ mvOsPrintf("Wrong index %d - No such test\n", idx); -+ return NULL; -+ } -+ if(pTestIdx != NULL) -+ *pTestIdx = testIdx; -+ -+ return cesaTestsDB[dbIdx].pSessions; -+} -+ -+/* Debug */ -+void cesaTestPrintReq(int req, int offset, int size) -+{ -+ MV_CESA_MBUF* pMbuf; -+ -+ mvOsPrintf("cesaTestPrintReq: req=%d, offset=%d, size=%d\n", -+ req, offset, size); -+ mvDebugMemDump(cesaCmdRing, 128, 4); -+ -+ pMbuf = cesaCmdRing[req].pSrc; -+ mvCesaDebugMbuf("src", pMbuf, offset,size); -+ pMbuf = cesaCmdRing[req].pDst; -+ mvCesaDebugMbuf("dst", pMbuf, offset, size); -+ -+ cesaTestPrintStatus(); -+} -+ -+void cesaLastResult(void) -+{ -+ mvOsPrintf("Last Result: ReqId = %d, SessionId = %d, rc = (%d)\n", -+ (MV_U32)cesaResult.pReqPrv, cesaResult.sessionId, -+ cesaResult.retCode); -+} -+ -+void printTestResults(int idx, MV_STATUS status, int checkMode) -+{ -+ int testIdx; -+ MV_CESA_TEST_SESSION* pTestSessions = getTestSessionDb(idx, &testIdx); -+ -+ if(pTestSessions == NULL) -+ return; -+ -+ mvOsPrintf("%-35s %4dx%-4d : ", pTestSessions[testIdx].name, -+ cesaIteration, cesaReqSize); -+ if( (status == MV_OK) && -+ (cesaCryptoError == 0) && -+ (cesaError == 0) && -+ (cesaReqIdError == 0) ) -+ { -+ mvOsPrintf("Passed, Rate=%3u.%u Mbps (%5u cpp)\n", -+ cesaRate, cesaRateAfterDot, cesaEndTicks - cesaBeginTicks); -+ } -+ else -+ { -+ mvOsPrintf("Failed, Status = 0x%x\n", status); -+ if(cesaCryptoError > 0) -+ mvOsPrintf("cryptoError : %d\n", cesaCryptoError); -+ if(cesaReqIdError > 0) -+ mvOsPrintf("reqIdError : %d\n", cesaReqIdError); -+ if(cesaError > 0) -+ mvOsPrintf("cesaError : %d\n", cesaError); -+ } -+ if(cesaTestIsrMissCount > 0) -+ mvOsPrintf("cesaIsrMissed : %d\n", cesaTestIsrMissCount); -+} -+ -+void cesaCheckReady(MV_CESA_RESULT* r) -+{ -+ int reqId; -+ MV_CESA_MBUF *pMbuf; -+ MV_BOOL isFailed; -+ -+ cesaResult = *r; -+ reqId = (int)cesaResult.pReqPrv; -+ pMbuf = cesaCmdRing[reqId].pDst; -+ -+/* -+ mvOsPrintf("cesaCheckReady: reqId=%d, checkOffset=%d, checkSize=%d\n", -+ reqId, cesaCheckOffset, cesaCheckSize); -+*/ -+ /* Check expected reqId */ -+ if(reqId != cesaExpReqId) -+ { -+ cesaReqIdError++; -+/* -+ mvOsPrintf("CESA reqId Error: cbIter=%d (%d), reqId=%d, expReqId=%d\n", -+ cesaCbIter, cesaIteration, reqId, cesaExpReqId); -+*/ -+ } -+ else -+ { -+ if( (cesaCheckMode == CESA_FULL_CHECK_MODE) || -+ (cesaCheckMode == CESA_FAST_CHECK_MODE) ) -+ { -+ if(cesaResult.retCode != MV_OK) -+ { -+ cesaError++; -+ -+ mvOsPrintf("CESA Error: cbIter=%d (%d), reqId=%d, rc=%d\n", -+ cesaCbIter, cesaIteration, reqId, cesaResult.retCode); -+ } -+ else -+ { -+ if( (cesaCheckSize > 0) && (cesaOutputHexStr != NULL) ) -+ { -+ /* Check expected output */ -+ -+ isFailed = cesaCheckMbuf(pMbuf, cesaOutputHexStr, cesaCheckOffset, cesaCheckSize); -+ if(isFailed) -+ { -+ mvOsPrintf("CESA Crypto Error: cbIter=%d (%d), reqId=%d\n", -+ cesaCbIter, cesaIteration, reqId); -+ -+ CESA_TEST_DEBUG_PRINT(("Error: reqId=%d, reqSize=%d, checkOffset=%d, checkSize=%d\n", -+ reqId, cesaReqSize, cesaCheckOffset, cesaCheckSize)); -+ -+ CESA_TEST_DEBUG_PRINT(("Output str: %s\n", cesaOutputHexStr)); -+ -+ CESA_TEST_DEBUG_CODE( mvCesaDebugMbuf("error", pMbuf, 0, cesaCheckOffset+cesaCheckSize) ); -+ -+ cesaCryptoError++; -+ } -+ } -+ } -+ } -+ } -+ if(cesaCheckMode == CESA_SHOW_CHECK_MODE) -+ { -+ extractMbuf(pMbuf, cesaCheckOffset, cesaCheckSize, cesaHexBuffer); -+ mvOsPrintf("%4d, %s\n", cesaCheckOffset, cesaHexBuffer); -+ } -+ -+ cesaCbIter++; -+ if(cesaCbIter >= cesaIteration) -+ { -+ cesaCbIter = 0; -+ cesaExpReqId = 0; -+ cesaIsReady = MV_TRUE; -+ -+ cesaEndTicks = CESA_TEST_TICK_GET(); -+ cesaRate = getRate(&cesaRateAfterDot); -+ } -+ else -+ { -+ cesaExpReqId = reqId + 1; -+ if(cesaExpReqId == CESA_DEF_REQ_SIZE) -+ cesaExpReqId = 0; -+ } -+} -+ -+ -+#ifdef MV_NETBSD -+static int cesaTestReadyIsr(void *arg) -+#else -+#ifdef __KERNEL__ -+static irqreturn_t cesaTestReadyIsr( int irq , void *dev_id) -+#endif -+#ifdef MV_VXWORKS -+void cesaTestReadyIsr(void) -+#endif -+#endif -+{ -+ MV_U32 cause; -+ MV_STATUS status; -+ MV_CESA_RESULT result; -+ -+ cesaTestIsrCount++; -+ /* Clear cause register */ -+ cause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); -+ if( (cause & MV_CESA_CAUSE_ACC_DMA_ALL_MASK) == 0) -+ { -+ mvOsPrintf("cesaTestReadyIsr: cause=0x%x\n", cause); -+#ifdef MV_NETBSD -+ return 0; -+#else -+#ifdef __KERNEL__ -+ return 1; -+#else -+ return; -+#endif -+#endif -+ } -+ -+ MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); -+ -+ while(MV_TRUE) -+ { -+ /* Get Ready requests */ -+ status = mvCesaReadyGet(&result); -+ if(status == MV_OK) -+ cesaCheckReady(&result); -+ -+ break; -+ } -+ if( (cesaTestFull == 1) && (status != MV_BUSY) ) -+ { -+ cesaTestFull = 0; -+ CESA_TEST_WAKE_UP(); -+ } -+ -+#ifdef __KERNEL__ -+ return 1; -+#endif -+} -+ -+void -+cesaTestCheckReady(const MV_CESA_RESULT *r) -+{ -+ MV_CESA_RESULT result = *r; -+ -+ cesaCheckReady(&result); -+ -+ if (cesaTestFull == 1) { -+ cesaTestFull = 0; -+ CESA_TEST_WAKE_UP(); -+ } -+} -+ -+static INLINE int open_session(MV_CESA_OPEN_SESSION* pOs) -+{ -+ MV_U16 sid; -+ MV_STATUS status; -+ -+ status = mvCesaSessionOpen(pOs, (short*)&sid); -+ if(status != MV_OK) -+ { -+ mvOsPrintf("CesaTest: Can't open new session - status = 0x%x\n", -+ status); -+ return -1; -+ } -+ -+ return (int)sid; -+} -+ -+void close_session(int sid) -+{ -+ MV_STATUS status; -+ -+ status = mvCesaSessionClose(sid); -+ if(status != MV_OK) -+ { -+ mvOsPrintf("CesaTest: Can't close session %d - status = 0x%x\n", -+ sid, status); -+ } -+} -+ -+MV_STATUS testOpen(int idx) -+{ -+ MV_CESA_OPEN_SESSION os; -+ int sid, i, testIdx; -+ MV_CESA_TEST_SESSION* pTestSession; -+ MV_U16 digestSize = 0; -+ -+ pTestSession = getTestSessionDb(idx, &testIdx); -+ if(pTestSession == NULL) -+ { -+ mvOsPrintf("Test %d is not exist\n", idx); -+ return MV_BAD_PARAM; -+ } -+ pTestSession = &pTestSession[testIdx]; -+ -+ if(pTestSession->sid != -1) -+ { -+ mvOsPrintf("Session for test %d already created: sid=%d\n", -+ idx, pTestSession->sid); -+ return MV_OK; -+ } -+ -+ os.cryptoAlgorithm = pTestSession->cryptoAlgorithm; -+ os.macMode = pTestSession->macAlgorithm; -+ switch(os.macMode) -+ { -+ case MV_CESA_MAC_MD5: -+ case MV_CESA_MAC_HMAC_MD5: -+ digestSize = MV_CESA_MD5_DIGEST_SIZE; -+ break; -+ -+ case MV_CESA_MAC_SHA1: -+ case MV_CESA_MAC_HMAC_SHA1: -+ digestSize = MV_CESA_SHA1_DIGEST_SIZE; -+ break; -+ -+ case MV_CESA_MAC_NULL: -+ digestSize = 0; -+ } -+ os.cryptoMode = pTestSession->cryptoMode; -+ os.direction = pTestSession->direction; -+ os.operation = pTestSession->operation; -+ -+ for(i=0; icryptoKeySize; i++) -+ os.cryptoKey[i] = pTestSession->pCryptoKey[i]; -+ -+ os.cryptoKeyLength = pTestSession->cryptoKeySize; -+ -+ for(i=0; imacKeySize; i++) -+ os.macKey[i] = pTestSession->pMacKey[i]; -+ -+ os.macKeyLength = pTestSession->macKeySize; -+ os.digestSize = digestSize; -+ -+ sid = open_session(&os); -+ if(sid == -1) -+ { -+ mvOsPrintf("Can't open session for test %d: rc=0x%x\n", -+ idx, cesaResult.retCode); -+ return cesaResult.retCode; -+ } -+ CESA_TEST_DEBUG_PRINT(("Opened session: sid = %d\n", sid)); -+ pTestSession->sid = sid; -+ return MV_OK; -+} -+ -+MV_STATUS testClose(int idx) -+{ -+ int testIdx; -+ MV_CESA_TEST_SESSION* pTestSession; -+ -+ pTestSession = getTestSessionDb(idx, &testIdx); -+ if(pTestSession == NULL) -+ { -+ mvOsPrintf("Test %d is not exist\n", idx); -+ return MV_BAD_PARAM; -+ } -+ pTestSession = &pTestSession[testIdx]; -+ -+ if(pTestSession->sid == -1) -+ { -+ mvOsPrintf("Test session %d is not opened\n", idx); -+ return MV_NO_SUCH; -+ } -+ -+ close_session(pTestSession->sid); -+ pTestSession->sid = -1; -+ -+ return MV_OK; -+} -+ -+MV_STATUS testCmd(int sid, int iter, MV_CESA_COMMAND* pCmd, -+ MV_CESA_TEST_SESSION* pTestSession, MV_U8* pIV, int ivSize) -+{ -+ int cmdReqId = 0; -+ int i; -+ MV_STATUS rc = MV_OK; -+ char ivZeroHex[] = "0000"; -+ -+ if(iter == 0) -+ iter = CESA_DEF_ITER_NUM; -+ -+ if(pCmd == NULL) -+ { -+ mvOsPrintf("testCmd failed: pCmd=NULL\n"); -+ return MV_BAD_PARAM; -+ } -+ pCmd->sessionId = sid; -+ -+ cesaCryptoError = 0; -+ cesaReqIdError = 0; -+ cesaError = 0; -+ cesaTestIsrMissCount = 0; -+ cesaIsReady = MV_FALSE; -+ cesaIteration = iter; -+ -+ if(cesaInputHexStr == NULL) -+ cesaInputHexStr = cesaPlainHexEbc; -+ -+ for(i=0; ipSrc = (MV_CESA_MBUF*)(cesaCmdRing[i].pSrc); -+ if(pIV != NULL) -+ { -+ /* If IV from SA - set IV in Source buffer to zeros */ -+ cesaSetMbuf(pCmd->pSrc, ivZeroHex, 0, pCmd->cryptoOffset); -+ cesaSetMbuf(pCmd->pSrc, cesaInputHexStr, pCmd->cryptoOffset, -+ (cesaReqSize - pCmd->cryptoOffset)); -+ } -+ else -+ { -+ cesaSetMbuf(pCmd->pSrc, cesaInputHexStr, 0, cesaReqSize); -+ } -+ pCmd->pDst = (MV_CESA_MBUF*)(cesaCmdRing[i].pDst); -+ cesaSetMbuf(pCmd->pDst, cesaNullPlainHexText, 0, cesaReqSize); -+ -+ memcpy(&cesaCmdRing[i], pCmd, sizeof(*pCmd)); -+ } -+ -+ if(cesaCheckMode == CESA_SW_SHOW_CHECK_MODE) -+ { -+ MV_U8 pDigest[MV_CESA_MAX_DIGEST_SIZE]; -+ -+ if(pTestSession->macAlgorithm == MV_CESA_MAC_MD5) -+ { -+ mvMD5(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, pDigest); -+ mvOsPrintf("SW HASH_MD5: reqSize=%d, macLength=%d\n", -+ cesaReqSize, pCmd->macLength); -+ mvDebugMemDump(pDigest, MV_CESA_MD5_DIGEST_SIZE, 1); -+ return MV_OK; -+ } -+ if(pTestSession->macAlgorithm == MV_CESA_MAC_SHA1) -+ { -+ mvSHA1(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, pDigest); -+ mvOsPrintf("SW HASH_SHA1: reqSize=%d, macLength=%d\n", -+ cesaReqSize, pCmd->macLength); -+ mvDebugMemDump(pDigest, MV_CESA_SHA1_DIGEST_SIZE, 1); -+ return MV_OK; -+ } -+ } -+ -+ cesaBeginTicks = CESA_TEST_TICK_GET(); -+ CESA_TEST_DEBUG_CODE( memset(cesaTestTrace, 0, sizeof(cesaTestTrace)); -+ cesaTestTraceIdx = 0; -+ ); -+ -+ if(cesaCheckMode == CESA_SW_NULL_CHECK_MODE) -+ { -+ volatile MV_U8 pDigest[MV_CESA_MAX_DIGEST_SIZE]; -+ -+ for(i=0; imacAlgorithm == MV_CESA_MAC_MD5) -+ { -+ mvMD5(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, (unsigned char*)pDigest); -+ } -+ if(pTestSession->macAlgorithm == MV_CESA_MAC_SHA1) -+ { -+ mvSHA1(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, (MV_U8 *)pDigest); -+ } -+ } -+ cesaEndTicks = CESA_TEST_TICK_GET(); -+ cesaRate = getRate(&cesaRateAfterDot); -+ cesaIsReady = MV_TRUE; -+ -+ return MV_OK; -+ } -+ -+ /*cesaTestIsrCount = 0;*/ -+ /*mvCesaDebugStatsClear();*/ -+ -+#ifndef MV_NETBSD -+ MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); -+#endif -+ -+ for(i=0; ipReqPrv = (void*)cmdReqId; -+ -+ CESA_TEST_LOCK(flags); -+ -+ rc = mvCesaAction(pCmd); -+ if(rc == MV_NO_RESOURCE) -+ cesaTestFull = 1; -+ -+ CESA_TEST_UNLOCK(flags); -+ -+ if(rc == MV_NO_RESOURCE) -+ { -+ CESA_TEST_LOCK(flags); -+ CESA_TEST_WAIT( (cesaTestFull == 0), 100); -+ CESA_TEST_UNLOCK(flags); -+ if(cesaTestFull == 1) -+ { -+ mvOsPrintf("CESA Test timeout: i=%d, iter=%d, cesaTestFull=%d\n", -+ i, iter, cesaTestFull); -+ cesaTestFull = 0; -+ return MV_TIMEOUT; -+ } -+ -+ CESA_TEST_LOCK(flags); -+ -+ rc = mvCesaAction(pCmd); -+ -+ CESA_TEST_UNLOCK(flags); -+ } -+ if( (rc != MV_OK) && (rc != MV_NO_MORE) ) -+ { -+ mvOsPrintf("mvCesaAction failed: rc=%d\n", rc); -+ return rc; -+ } -+ -+ cmdReqId++; -+ if(cmdReqId >= CESA_DEF_REQ_SIZE) -+ cmdReqId = 0; -+ -+#ifdef MV_LINUX -+ /* Reschedule each 16 requests */ -+ if( (i & 0xF) == 0) -+ schedule(); -+#endif -+ } -+ return MV_OK; -+} -+ -+void cesaTestStart(int bufNum, int bufSize) -+{ -+ int i, j, idx; -+ MV_CESA_MBUF *pMbufSrc, *pMbufDst; -+ MV_BUF_INFO *pFragsSrc, *pFragsDst; -+ char *pBuf; -+#ifndef MV_NETBSD -+ int numOfSessions, queueDepth; -+ char *pSram; -+ MV_STATUS status; -+ MV_CPU_DEC_WIN addrDecWin; -+#endif -+ -+ cesaCmdRing = mvOsMalloc(sizeof(MV_CESA_COMMAND) * CESA_DEF_REQ_SIZE); -+ if(cesaCmdRing == NULL) -+ { -+ mvOsPrintf("testStart: Can't allocate %ld bytes of memory\n", -+ sizeof(MV_CESA_COMMAND) * CESA_DEF_REQ_SIZE); -+ return; -+ } -+ memset(cesaCmdRing, 0, sizeof(MV_CESA_COMMAND) * CESA_DEF_REQ_SIZE); -+ -+ if(bufNum == 0) -+ bufNum = CESA_DEF_BUF_NUM; -+ -+ if(bufSize == 0) -+ bufSize = CESA_DEF_BUF_SIZE; -+ -+ cesaBufNum = bufNum; -+ cesaBufSize = bufSize; -+ mvOsPrintf("CESA test started: bufNum = %d, bufSize = %d\n", -+ bufNum, bufSize); -+ -+ cesaHexBuffer = mvOsMalloc(2*bufNum*bufSize); -+ if(cesaHexBuffer == NULL) -+ { -+ mvOsPrintf("testStart: Can't malloc %d bytes for cesaHexBuffer.\n", -+ 2*bufNum*bufSize); -+ return; -+ } -+ memset(cesaHexBuffer, 0, (2*bufNum*bufSize)); -+ -+ cesaBinBuffer = mvOsMalloc(bufNum*bufSize); -+ if(cesaBinBuffer == NULL) -+ { -+ mvOsPrintf("testStart: Can't malloc %d bytes for cesaBinBuffer\n", -+ bufNum*bufSize); -+ return; -+ } -+ memset(cesaBinBuffer, 0, (bufNum*bufSize)); -+ -+ cesaExpBinBuffer = mvOsMalloc(bufNum*bufSize); -+ if(cesaExpBinBuffer == NULL) -+ { -+ mvOsPrintf("testStart: Can't malloc %d bytes for cesaExpBinBuffer\n", -+ bufNum*bufSize); -+ return; -+ } -+ memset(cesaExpBinBuffer, 0, (bufNum*bufSize)); -+ -+ CESA_TEST_WAIT_INIT(); -+ -+ pMbufSrc = mvOsMalloc(sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); -+ pFragsSrc = mvOsMalloc(sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); -+ -+ pMbufDst = mvOsMalloc(sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); -+ pFragsDst = mvOsMalloc(sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); -+ -+ if( (pMbufSrc == NULL) || (pFragsSrc == NULL) || -+ (pMbufDst == NULL) || (pFragsDst == NULL) ) -+ { -+ mvOsPrintf("testStart: Can't malloc Src and Dst pMbuf and pFrags structures.\n"); -+ /* !!!! Dima cesaTestCleanup();*/ -+ return; -+ } -+ -+ memset(pMbufSrc, 0, sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); -+ memset(pFragsSrc, 0, sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); -+ -+ memset(pMbufDst, 0, sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); -+ memset(pFragsDst, 0, sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); -+ -+ mvOsPrintf("Cesa Test Start: pMbufSrc=%p, pFragsSrc=%p, pMbufDst=%p, pFragsDst=%p\n", -+ pMbufSrc, pFragsSrc, pMbufDst, pFragsDst); -+ -+ idx = 0; -+ for(i=0; ipFrags = &pFragsSrc[idx]; -+ cesaCmdRing[i].pSrc->numFrags = bufNum; -+ cesaCmdRing[i].pSrc->mbufSize = 0; -+ -+ cesaCmdRing[i].pDst = &pMbufDst[i]; -+ cesaCmdRing[i].pDst->pFrags = &pFragsDst[idx]; -+ cesaCmdRing[i].pDst->numFrags = bufNum; -+ cesaCmdRing[i].pDst->mbufSize = 0; -+ -+ for(j=0; jpFrags[j].bufVirtPtr = (MV_U8*)pBuf; -+ cesaCmdRing[i].pSrc->pFrags[j].bufSize = bufSize; -+ pBuf += bufSize; -+ cesaCmdRing[i].pDst->pFrags[j].bufVirtPtr = (MV_U8*)pBuf; -+ cesaCmdRing[i].pDst->pFrags[j].bufSize = bufSize; -+ pBuf += bufSize; -+ } -+ idx += bufNum; -+ } -+ -+#ifndef MV_NETBSD -+ if (mvCpuIfTargetWinGet(CRYPT_ENG, &addrDecWin) == MV_OK) -+ pSram = (char*)addrDecWin.addrWin.baseLow; -+ else -+ { -+ mvOsPrintf("mvCesaInit: ERR. mvCpuIfTargetWinGet failed\n"); -+ return; -+ } -+ -+#ifdef MV_CESA_NO_SRAM -+ pSram = mvOsMalloc(4*1024+8); -+ if(pSram == NULL) -+ { -+ mvOsPrintf("CesaTest: can't allocate %d bytes for SRAM simulation\n", -+ 4*1024+8); -+ /* !!!! Dima cesaTestCleanup();*/ -+ return; -+ } -+ pSram = (MV_U8*)MV_ALIGN_UP((MV_U32)pSram, 8); -+#endif /* MV_CESA_NO_SRAM */ -+ -+ numOfSessions = CESA_DEF_SESSION_NUM; -+ queueDepth = CESA_DEF_REQ_SIZE - MV_CESA_MAX_CHAN; -+ -+ status = mvCesaInit(numOfSessions, queueDepth, pSram, NULL); -+ if(status != MV_OK) -+ { -+ mvOsPrintf("mvCesaInit is Failed: status = 0x%x\n", status); -+ /* !!!! Dima cesaTestCleanup();*/ -+ return; -+ } -+#endif /* !MV_NETBSD */ -+ -+ /* Prepare data for tests */ -+ for(i=0; i<50; i++) -+ strcat((char*)cesaDataHexStr3, "dd"); -+ -+ strcpy((char*)cesaDataAndMd5digest3, cesaDataHexStr3); -+ strcpy((char*)cesaDataAndSha1digest3, cesaDataHexStr3); -+ -+ /* Digest must be 8 byte aligned */ -+ for(; i<56; i++) -+ { -+ strcat((char*)cesaDataAndMd5digest3, "00"); -+ strcat((char*)cesaDataAndSha1digest3, "00"); -+ } -+ strcat((char*)cesaDataAndMd5digest3, cesaHmacMd5digestHex3); -+ strcat((char*)cesaDataAndSha1digest3, cesaHmacSha1digestHex3); -+ -+#ifndef MV_NETBSD -+ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); -+ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, MV_CESA_CAUSE_ACC_DMA_MASK); -+#endif -+ -+#ifdef MV_VXWORKS -+ { -+ MV_STATUS status; -+ -+ status = intConnect((VOIDFUNCPTR *)INT_LVL_CESA, cesaTestReadyIsr, (int)NULL); -+ if (status != OK) -+ { -+ mvOsPrintf("CESA: Can't connect CESA (%d) interrupt, status=0x%x \n", -+ INT_LVL_CESA, status); -+ /* !!!! Dima cesaTestCleanup();*/ -+ return; -+ } -+ cesaSemId = semMCreate(SEM_Q_PRIORITY | SEM_INVERSION_SAFE | SEM_DELETE_SAFE); -+ if(cesaSemId == NULL) -+ { -+ mvOsPrintf("cesaTestStart: Can't create semaphore\n"); -+ return; -+ } -+ intEnable(INT_LVL_CESA); -+ } -+#endif /* MV_VXWORKS */ -+ -+#if !defined(MV_NETBSD) && defined(__KERNEL__) -+ if( request_irq(CESA_IRQ, cesaTestReadyIsr, (SA_INTERRUPT) , "cesa_test", NULL ) ) -+ { -+ mvOsPrintf( "cannot assign irq\n" ); -+ /* !!!! Dima cesaTestCleanup();*/ -+ return; -+ } -+ spin_lock_init( &cesaLock ); -+#endif -+} -+ -+MV_STATUS testRun(int idx, int caseIdx, int iter, -+ int reqSize, int checkMode) -+{ -+ int testIdx, count, sid, digestSize; -+ int blockSize; -+ MV_CESA_TEST_SESSION* pTestSession; -+ MV_CESA_COMMAND cmd; -+ MV_STATUS status; -+ -+ memset(&cmd, 0, sizeof(cmd)); -+ -+ pTestSession = getTestSessionDb(idx, &testIdx); -+ if(pTestSession == NULL) -+ { -+ mvOsPrintf("Test %d is not exist\n", idx); -+ return MV_BAD_PARAM; -+ } -+ pTestSession = &pTestSession[testIdx]; -+ -+ sid = pTestSession->sid; -+ if(sid == -1) -+ { -+ mvOsPrintf("Test %d is not opened\n", idx); -+ return MV_BAD_STATE; -+ } -+ switch(pTestSession->cryptoAlgorithm) -+ { -+ case MV_CESA_CRYPTO_DES: -+ case MV_CESA_CRYPTO_3DES: -+ blockSize = MV_CESA_DES_BLOCK_SIZE; -+ break; -+ -+ case MV_CESA_CRYPTO_AES: -+ blockSize = MV_CESA_AES_BLOCK_SIZE; -+ break; -+ -+ case MV_CESA_CRYPTO_NULL: -+ blockSize = 0; -+ break; -+ -+ default: -+ mvOsPrintf("cesaTestRun: Bad CryptoAlgorithm=%d\n", -+ pTestSession->cryptoAlgorithm); -+ return MV_BAD_PARAM; -+ } -+ switch(pTestSession->macAlgorithm) -+ { -+ case MV_CESA_MAC_MD5: -+ case MV_CESA_MAC_HMAC_MD5: -+ digestSize = MV_CESA_MD5_DIGEST_SIZE; -+ break; -+ -+ case MV_CESA_MAC_SHA1: -+ case MV_CESA_MAC_HMAC_SHA1: -+ digestSize = MV_CESA_SHA1_DIGEST_SIZE; -+ break; -+ default: -+ digestSize = 0; -+ } -+ -+ if(iter == 0) -+ iter = CESA_DEF_ITER_NUM; -+ -+ if(pTestSession->direction == MV_CESA_DIR_ENCODE) -+ { -+ cesaOutputHexStr = cesaTestCases[caseIdx].cipherHexStr; -+ cesaInputHexStr = cesaTestCases[caseIdx].plainHexStr; -+ } -+ else -+ { -+ cesaOutputHexStr = cesaTestCases[caseIdx].plainHexStr; -+ cesaInputHexStr = cesaTestCases[caseIdx].cipherHexStr; -+ } -+ -+ cmd.sessionId = sid; -+ if(checkMode == CESA_FAST_CHECK_MODE) -+ { -+ cmd.cryptoLength = cesaTestCases[caseIdx].cryptoLength; -+ cmd.macLength = cesaTestCases[caseIdx].macLength; -+ } -+ else -+ { -+ cmd.cryptoLength = reqSize; -+ cmd.macLength = reqSize; -+ } -+ cesaRateSize = cmd.cryptoLength; -+ cesaReqSize = cmd.cryptoLength; -+ cmd.cryptoOffset = 0; -+ if(pTestSession->operation != MV_CESA_MAC_ONLY) -+ { -+ if( (pTestSession->cryptoMode == MV_CESA_CRYPTO_CBC) || -+ (pTestSession->cryptoMode == MV_CESA_CRYPTO_CTR) ) -+ { -+ cmd.ivOffset = 0; -+ cmd.cryptoOffset = blockSize; -+ if(cesaTestCases[caseIdx].pCryptoIV == NULL) -+ { -+ cmd.ivFromUser = 1; -+ } -+ else -+ { -+ cmd.ivFromUser = 0; -+ mvCesaCryptoIvSet(cesaTestCases[caseIdx].pCryptoIV, blockSize); -+ } -+ cesaReqSize = cmd.cryptoOffset + cmd.cryptoLength; -+ } -+ } -+ -+/* -+ mvOsPrintf("ivFromUser=%d, cryptoLength=%d, cesaReqSize=%d, cryptoOffset=%d\n", -+ cmd.ivFromUser, cmd.cryptoLength, cesaReqSize, cmd.cryptoOffset); -+*/ -+ if(pTestSession->operation != MV_CESA_CRYPTO_ONLY) -+ { -+ cmd.macOffset = cmd.cryptoOffset; -+ -+ if(cesaTestCases[caseIdx].digestOffset == -1) -+ { -+ cmd.digestOffset = cmd.macOffset + cmd.macLength; -+ cmd.digestOffset = MV_ALIGN_UP(cmd.digestOffset, 8); -+ } -+ else -+ { -+ cmd.digestOffset = cesaTestCases[caseIdx].digestOffset; -+ } -+ if( (cmd.digestOffset + digestSize) > cesaReqSize) -+ cesaReqSize = cmd.digestOffset + digestSize; -+ } -+ -+ cesaCheckMode = checkMode; -+ -+ if(checkMode == CESA_NULL_CHECK_MODE) -+ { -+ cesaCheckSize = 0; -+ cesaCheckOffset = 0; -+ } -+ else -+ { -+ if(pTestSession->operation == MV_CESA_CRYPTO_ONLY) -+ { -+ cesaCheckOffset = 0; -+ cesaCheckSize = cmd.cryptoLength; -+ } -+ else -+ { -+ cesaCheckSize = digestSize; -+ cesaCheckOffset = cmd.digestOffset; -+ } -+ } -+/* -+ mvOsPrintf("reqSize=%d, checkSize=%d, checkOffset=%d, checkMode=%d\n", -+ cesaReqSize, cesaCheckSize, cesaCheckOffset, cesaCheckMode); -+ -+ mvOsPrintf("blockSize=%d, ivOffset=%d, ivFromUser=%d, crOffset=%d, crLength=%d\n", -+ blockSize, cmd.ivOffset, cmd.ivFromUser, -+ cmd.cryptoOffset, cmd.cryptoLength); -+ -+ mvOsPrintf("macOffset=%d, digestOffset=%d, macLength=%d\n", -+ cmd.macOffset, cmd.digestOffset, cmd.macLength); -+*/ -+ status = testCmd(sid, iter, &cmd, pTestSession, -+ cesaTestCases[caseIdx].pCryptoIV, blockSize); -+ -+ if(status != MV_OK) -+ return status; -+ -+ /* Wait when all callbacks is received */ -+ count = 0; -+ while(cesaIsReady == MV_FALSE) -+ { -+ mvOsSleep(10); -+ count++; -+ if(count > 100) -+ { -+ mvOsPrintf("testRun: Timeout occured\n"); -+ return MV_TIMEOUT; -+ } -+ } -+ -+ return MV_OK; -+} -+ -+ -+void cesaTestStop(void) -+{ -+ MV_CESA_MBUF *pMbufSrc, *pMbufDst; -+ MV_BUF_INFO *pFragsSrc, *pFragsDst; -+ int i; -+ -+ /* Release all allocated memories */ -+ pMbufSrc = (MV_CESA_MBUF*)(cesaCmdRing[0].pSrc); -+ pFragsSrc = cesaCmdRing[0].pSrc->pFrags; -+ -+ pMbufDst = (MV_CESA_MBUF*)(cesaCmdRing[0].pDst); -+ pFragsDst = cesaCmdRing[0].pDst->pFrags; -+ -+ mvOsFree(pMbufSrc); -+ mvOsFree(pMbufDst); -+ mvOsFree(pFragsSrc); -+ mvOsFree(pFragsDst); -+ -+ for(i=0; i 0) -+ cryptoError++; -+ if(cesaReqIdError > 0) -+ reqIdError++; -+ -+ testClose(idx); -+ } -+ } -+ if(cryptoError > 0) -+ mvOsPrintf("cryptoError : %d\n", cryptoError); -+ if(reqIdError > 0) -+ mvOsPrintf("reqIdError : %d\n", reqIdError); -+ -+ if(openErrors > 0) -+ { -+ mvOsPrintf("Open Errors = %d\n", openErrors); -+ for(i=0; i<100; i++) -+ { -+ if(openErrDisp[i] != 0) -+ mvOsPrintf("Error %d - occurs %d times\n", i, openErrDisp[i]); -+ } -+ } -+} -+ -+ -+void loopback_test(int idx, int iter, int size, char* pPlainData) -+{ -+} -+ -+ -+#if defined(MV_VXWORKS) -+int testMode = 0; -+unsigned __TASKCONV cesaTask(void* args) -+{ -+ int reqSize = cesaReqSize; -+ -+ if(testMode == 0) -+ { -+ cesaOneTest(cesaTestIdx, cesaCaseIdx, cesaIteration, -+ reqSize, cesaCheckMode); -+ } -+ else -+ { -+ if(testMode == 1) -+ { -+ cesaTest(cesaIteration, reqSize, cesaCheckMode); -+ combiTest(cesaIteration, reqSize, cesaCheckMode); -+ } -+ else -+ { -+ multiSizeTest(cesaIdx, cesaIteration, cesaCheckMode, NULL); -+ } -+ } -+ return 0; -+} -+ -+void oneTest(int testIdx, int caseIdx, -+ int iter, int reqSize, int checkMode) -+{ -+ long rc; -+ -+ cesaIteration = iter; -+ cesaReqSize = cesaRateSize = reqSize; -+ cesaCheckMode = checkMode; -+ testMode = 0; -+ cesaTestIdx = testIdx; -+ cesaCaseIdx = caseIdx; -+ rc = mvOsTaskCreate("CESA_T", 100, 4*1024, cesaTask, NULL, &cesaTaskId); -+ if (rc != MV_OK) -+ { -+ mvOsPrintf("hMW: Can't create CESA multiCmd test task, rc = %ld\n", rc); -+ } -+} -+ -+void multiTest(int iter, int reqSize, int checkMode) -+{ -+ long rc; -+ -+ cesaIteration = iter; -+ cesaCheckMode = checkMode; -+ cesaReqSize = reqSize; -+ testMode = 1; -+ rc = mvOsTaskCreate("CESA_T", 100, 4*1024, cesaTask, NULL, &cesaTaskId); -+ if (rc != MV_OK) -+ { -+ mvOsPrintf("hMW: Can't create CESA multiCmd test task, rc = %ld\n", rc); -+ } -+} -+ -+void sizeTest(int testIdx, int iter, int checkMode) -+{ -+ long rc; -+ -+ cesaIteration = iter; -+ cesaCheckMode = checkMode; -+ testMode = 2; -+ cesaIdx = testIdx; -+ rc = mvOsTaskCreate("CESA_T", 100, 4*1024, cesaTask, NULL, &cesaTaskId); -+ if (rc != MV_OK) -+ { -+ mvOsPrintf("hMW: Can't create CESA test task, rc = %ld\n", rc); -+ } -+} -+ -+#endif /* MV_VXWORKS */ -+ -+extern void mvCesaDebugSA(short sid, int mode); -+void cesaTestPrintSession(int idx) -+{ -+ int testIdx; -+ MV_CESA_TEST_SESSION* pTestSession; -+ -+ pTestSession = getTestSessionDb(idx, &testIdx); -+ if(pTestSession == NULL) -+ { -+ mvOsPrintf("Test %d is not exist\n", idx); -+ return; -+ } -+ pTestSession = &pTestSession[testIdx]; -+ -+ if(pTestSession->sid == -1) -+ { -+ mvOsPrintf("Test session %d is not opened\n", idx); -+ return; -+ } -+ -+ mvCesaDebugSA(pTestSession->sid, 1); -+} -+ -+void cesaTestPrintStatus(void) -+{ -+ mvOsPrintf("\n\t Cesa Test Status\n\n"); -+ -+ mvOsPrintf("isrCount=%d\n", -+ cesaTestIsrCount); -+ -+#ifdef CESA_TEST_DEBUG -+ { -+ int i, j; -+ j = cesaTestTraceIdx; -+ mvOsPrintf("No Type Cause rCause iCause Res Time pReady pProc pEmpty\n"); -+ for(i=0; itable = mvOsMalloc(numOfEntries*sizeof(MV_LRU_ENTRY)); -+ if(pLruCache->table == NULL) -+ { -+ mvOsFree(pLruCache); -+ return NULL; -+ } -+ memset(pLruCache->table, 0, numOfEntries*sizeof(MV_LRU_ENTRY)); -+ pLruCache->tableSize = numOfEntries; -+ -+ for(i=0; itable[i].next = i+1; -+ pLruCache->table[i].prev = i-1; -+ } -+ pLruCache->least = 0; -+ pLruCache->most = numOfEntries-1; -+ -+ return pLruCache; -+} -+ -+void mvLruCacheFinish(MV_LRU_CACHE* pLruCache) -+{ -+ mvOsFree(pLruCache->table); -+ mvOsFree(pLruCache); -+} -+ -+/* Update LRU cache database after using cache Index */ -+void mvLruCacheIdxUpdate(MV_LRU_CACHE* pLruHndl, int cacheIdx) -+{ -+ int prev, next; -+ -+ if(cacheIdx == pLruHndl->most) -+ return; -+ -+ next = pLruHndl->table[cacheIdx].next; -+ if(cacheIdx == pLruHndl->least) -+ { -+ pLruHndl->least = next; -+ } -+ else -+ { -+ prev = pLruHndl->table[cacheIdx].prev; -+ -+ pLruHndl->table[next].prev = prev; -+ pLruHndl->table[prev].next = next; -+ } -+ -+ pLruHndl->table[pLruHndl->most].next = cacheIdx; -+ pLruHndl->table[cacheIdx].prev = pLruHndl->most; -+ pLruHndl->most = cacheIdx; -+} -+ -+/* Delete LRU cache entry */ -+void mvLruCacheIdxDelete(MV_LRU_CACHE* pLruHndl, int cacheIdx) -+{ -+ int prev, next; -+ -+ if(cacheIdx == pLruHndl->least) -+ return; -+ -+ prev = pLruHndl->table[cacheIdx].prev; -+ if(cacheIdx == pLruHndl->most) -+ { -+ pLruHndl->most = prev; -+ } -+ else -+ { -+ next = pLruHndl->table[cacheIdx].next; -+ -+ pLruHndl->table[next].prev = prev; -+ pLruHndl->table[prev].next = next; -+ } -+ pLruHndl->table[pLruHndl->least].prev = cacheIdx; -+ pLruHndl->table[cacheIdx].next = pLruHndl->least; -+ pLruHndl->least = cacheIdx; -+} -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvLru.h linux-3.0.4/crypto/ocf/kirkwood/cesa/mvLru.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvLru.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/cesa/mvLru.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,112 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+/******************************************************************************* -+* mvLru.h - Header File for Least Recently Used Cache algorithm -+* -+* DESCRIPTION: -+* This header file contains macros typedefs and function declaration for -+* the Least Recently Used Cache algorithm. -+* -+*******************************************************************************/ -+ -+#ifndef __mvLru_h__ -+#define __mvLru_h__ -+ -+ -+typedef struct -+{ -+ int next; -+ int prev; -+} MV_LRU_ENTRY; -+ -+typedef struct -+{ -+ int least; -+ int most; -+ MV_LRU_ENTRY* table; -+ int tableSize; -+ -+}MV_LRU_CACHE; -+ -+ -+/* Find Cache index for replacement LRU */ -+static INLINE int mvLruCacheIdxFind(MV_LRU_CACHE* pLruHndl) -+{ -+ return pLruHndl->least; -+} -+ -+/* Init LRU cache module */ -+MV_LRU_CACHE* mvLruCacheInit(int numOfEntries); -+ -+/* Finish LRU cache module */ -+void mvLruCacheFinish(MV_LRU_CACHE* pLruHndl); -+ -+/* Update LRU cache database after using cache Index */ -+void mvLruCacheIdxUpdate(MV_LRU_CACHE* pLruHndl, int cacheIdx); -+ -+/* Delete LRU cache entry */ -+void mvLruCacheIdxDelete(MV_LRU_CACHE* pLruHndl, int cacheIdx); -+ -+ -+#endif /* __mvLru_h__ */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvMD5.c linux-3.0.4/crypto/ocf/kirkwood/cesa/mvMD5.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvMD5.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/cesa/mvMD5.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,349 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "mvOs.h" -+#include "mvMD5.h" -+ -+static void mvMD5Transform(MV_U32 buf[4], MV_U32 const in[MV_MD5_MAC_LEN]); -+ -+#ifdef MV_CPU_LE -+#define mvByteReverse(buf, len) /* Nothing */ -+#else -+static void mvByteReverse(unsigned char *buf, unsigned longs); -+ -+/* -+ * Note: this code is harmless on little-endian machines. -+ */ -+static void mvByteReverse(unsigned char *buf, unsigned longs) -+{ -+ MV_U32 t; -+ -+ do -+ { -+ t = (MV_U32) ((unsigned) buf[3] << 8 | buf[2]) << 16 | -+ ((unsigned) buf[1] << 8 | buf[0]); -+ *(MV_U32 *) buf = t; -+ buf += 4; -+ } while (--longs); -+} -+#endif -+ -+/* -+ * Start MD5 accumulation. Set bit count to 0 and buffer to mysterious -+ * initialization constants. -+ */ -+void mvMD5Init(MV_MD5_CONTEXT *ctx) -+{ -+ ctx->buf[0] = 0x67452301; -+ ctx->buf[1] = 0xefcdab89; -+ ctx->buf[2] = 0x98badcfe; -+ ctx->buf[3] = 0x10325476; -+ -+ ctx->bits[0] = 0; -+ ctx->bits[1] = 0; -+} -+ -+/* -+ * Update context to reflect the concatenation of another buffer full -+ * of bytes. -+ */ -+void mvMD5Update(MV_MD5_CONTEXT *ctx, unsigned char const *buf, unsigned len) -+{ -+ MV_U32 t; -+ -+ /* Update bitcount */ -+ -+ t = ctx->bits[0]; -+ if ((ctx->bits[0] = t + ((MV_U32) len << 3)) < t) -+ ctx->bits[1]++; /* Carry from low to high */ -+ ctx->bits[1] += len >> 29; -+ -+ t = (t >> 3) & 0x3f; /* Bytes already in shsInfo->data */ -+ -+ /* Handle any leading odd-sized chunks */ -+ -+ if (t) -+ { -+ unsigned char *p = (unsigned char *) ctx->in + t; -+ -+ t = 64 - t; -+ if (len < t) -+ { -+ memcpy(p, buf, len); -+ return; -+ } -+ memcpy(p, buf, t); -+ mvByteReverse(ctx->in, MV_MD5_MAC_LEN); -+ mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in); -+ buf += t; -+ len -= t; -+ } -+ /* Process data in 64-byte chunks */ -+ -+ while (len >= 64) -+ { -+ memcpy(ctx->in, buf, 64); -+ mvByteReverse(ctx->in, MV_MD5_MAC_LEN); -+ mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in); -+ buf += 64; -+ len -= 64; -+ } -+ -+ /* Handle any remaining bytes of data. */ -+ -+ memcpy(ctx->in, buf, len); -+} -+ -+/* -+ * Final wrapup - pad to 64-byte boundary with the bit pattern -+ * 1 0* (64-bit count of bits processed, MSB-first) -+ */ -+void mvMD5Final(unsigned char digest[MV_MD5_MAC_LEN], MV_MD5_CONTEXT *ctx) -+{ -+ unsigned count; -+ unsigned char *p; -+ -+ /* Compute number of bytes mod 64 */ -+ count = (ctx->bits[0] >> 3) & 0x3F; -+ -+ /* Set the first char of padding to 0x80. This is safe since there is -+ always at least one byte free */ -+ p = ctx->in + count; -+ *p++ = 0x80; -+ -+ /* Bytes of padding needed to make 64 bytes */ -+ count = 64 - 1 - count; -+ -+ /* Pad out to 56 mod 64 */ -+ if (count < 8) -+ { -+ /* Two lots of padding: Pad the first block to 64 bytes */ -+ memset(p, 0, count); -+ mvByteReverse(ctx->in, MV_MD5_MAC_LEN); -+ mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in); -+ -+ /* Now fill the next block with 56 bytes */ -+ memset(ctx->in, 0, 56); -+ } -+ else -+ { -+ /* Pad block to 56 bytes */ -+ memset(p, 0, count - 8); -+ } -+ mvByteReverse(ctx->in, 14); -+ -+ /* Append length in bits and transform */ -+ ((MV_U32 *) ctx->in)[14] = ctx->bits[0]; -+ ((MV_U32 *) ctx->in)[15] = ctx->bits[1]; -+ -+ mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in); -+ mvByteReverse((unsigned char *) ctx->buf, 4); -+ memcpy(digest, ctx->buf, MV_MD5_MAC_LEN); -+ memset(ctx, 0, sizeof(ctx)); /* In case it's sensitive */ -+} -+ -+/* The four core functions - F1 is optimized somewhat */ -+ -+/* #define F1(x, y, z) (x & y | ~x & z) */ -+#define F1(x, y, z) (z ^ (x & (y ^ z))) -+#define F2(x, y, z) F1(z, x, y) -+#define F3(x, y, z) (x ^ y ^ z) -+#define F4(x, y, z) (y ^ (x | ~z)) -+ -+/* This is the central step in the MD5 algorithm. */ -+#define MD5STEP(f, w, x, y, z, data, s) \ -+ ( w += f(x, y, z) + data, w = w<>(32-s), w += x ) -+ -+/* -+ * The core of the MD5 algorithm, this alters an existing MD5 hash to -+ * reflect the addition of 16 longwords of new data. MD5Update blocks -+ * the data and converts bytes into longwords for this routine. -+ */ -+static void mvMD5Transform(MV_U32 buf[4], MV_U32 const in[MV_MD5_MAC_LEN]) -+{ -+ register MV_U32 a, b, c, d; -+ -+ a = buf[0]; -+ b = buf[1]; -+ c = buf[2]; -+ d = buf[3]; -+ -+ MD5STEP(F1, a, b, c, d, in[0] + 0xd76aa478, 7); -+ MD5STEP(F1, d, a, b, c, in[1] + 0xe8c7b756, 12); -+ MD5STEP(F1, c, d, a, b, in[2] + 0x242070db, 17); -+ MD5STEP(F1, b, c, d, a, in[3] + 0xc1bdceee, 22); -+ MD5STEP(F1, a, b, c, d, in[4] + 0xf57c0faf, 7); -+ MD5STEP(F1, d, a, b, c, in[5] + 0x4787c62a, 12); -+ MD5STEP(F1, c, d, a, b, in[6] + 0xa8304613, 17); -+ MD5STEP(F1, b, c, d, a, in[7] + 0xfd469501, 22); -+ MD5STEP(F1, a, b, c, d, in[8] + 0x698098d8, 7); -+ MD5STEP(F1, d, a, b, c, in[9] + 0x8b44f7af, 12); -+ MD5STEP(F1, c, d, a, b, in[10] + 0xffff5bb1, 17); -+ MD5STEP(F1, b, c, d, a, in[11] + 0x895cd7be, 22); -+ MD5STEP(F1, a, b, c, d, in[12] + 0x6b901122, 7); -+ MD5STEP(F1, d, a, b, c, in[13] + 0xfd987193, 12); -+ MD5STEP(F1, c, d, a, b, in[14] + 0xa679438e, 17); -+ MD5STEP(F1, b, c, d, a, in[15] + 0x49b40821, 22); -+ -+ MD5STEP(F2, a, b, c, d, in[1] + 0xf61e2562, 5); -+ MD5STEP(F2, d, a, b, c, in[6] + 0xc040b340, 9); -+ MD5STEP(F2, c, d, a, b, in[11] + 0x265e5a51, 14); -+ MD5STEP(F2, b, c, d, a, in[0] + 0xe9b6c7aa, 20); -+ MD5STEP(F2, a, b, c, d, in[5] + 0xd62f105d, 5); -+ MD5STEP(F2, d, a, b, c, in[10] + 0x02441453, 9); -+ MD5STEP(F2, c, d, a, b, in[15] + 0xd8a1e681, 14); -+ MD5STEP(F2, b, c, d, a, in[4] + 0xe7d3fbc8, 20); -+ MD5STEP(F2, a, b, c, d, in[9] + 0x21e1cde6, 5); -+ MD5STEP(F2, d, a, b, c, in[14] + 0xc33707d6, 9); -+ MD5STEP(F2, c, d, a, b, in[3] + 0xf4d50d87, 14); -+ MD5STEP(F2, b, c, d, a, in[8] + 0x455a14ed, 20); -+ MD5STEP(F2, a, b, c, d, in[13] + 0xa9e3e905, 5); -+ MD5STEP(F2, d, a, b, c, in[2] + 0xfcefa3f8, 9); -+ MD5STEP(F2, c, d, a, b, in[7] + 0x676f02d9, 14); -+ MD5STEP(F2, b, c, d, a, in[12] + 0x8d2a4c8a, 20); -+ -+ MD5STEP(F3, a, b, c, d, in[5] + 0xfffa3942, 4); -+ MD5STEP(F3, d, a, b, c, in[8] + 0x8771f681, 11); -+ MD5STEP(F3, c, d, a, b, in[11] + 0x6d9d6122, 16); -+ MD5STEP(F3, b, c, d, a, in[14] + 0xfde5380c, 23); -+ MD5STEP(F3, a, b, c, d, in[1] + 0xa4beea44, 4); -+ MD5STEP(F3, d, a, b, c, in[4] + 0x4bdecfa9, 11); -+ MD5STEP(F3, c, d, a, b, in[7] + 0xf6bb4b60, 16); -+ MD5STEP(F3, b, c, d, a, in[10] + 0xbebfbc70, 23); -+ MD5STEP(F3, a, b, c, d, in[13] + 0x289b7ec6, 4); -+ MD5STEP(F3, d, a, b, c, in[0] + 0xeaa127fa, 11); -+ MD5STEP(F3, c, d, a, b, in[3] + 0xd4ef3085, 16); -+ MD5STEP(F3, b, c, d, a, in[6] + 0x04881d05, 23); -+ MD5STEP(F3, a, b, c, d, in[9] + 0xd9d4d039, 4); -+ MD5STEP(F3, d, a, b, c, in[12] + 0xe6db99e5, 11); -+ MD5STEP(F3, c, d, a, b, in[15] + 0x1fa27cf8, 16); -+ MD5STEP(F3, b, c, d, a, in[2] + 0xc4ac5665, 23); -+ -+ MD5STEP(F4, a, b, c, d, in[0] + 0xf4292244, 6); -+ MD5STEP(F4, d, a, b, c, in[7] + 0x432aff97, 10); -+ MD5STEP(F4, c, d, a, b, in[14] + 0xab9423a7, 15); -+ MD5STEP(F4, b, c, d, a, in[5] + 0xfc93a039, 21); -+ MD5STEP(F4, a, b, c, d, in[12] + 0x655b59c3, 6); -+ MD5STEP(F4, d, a, b, c, in[3] + 0x8f0ccc92, 10); -+ MD5STEP(F4, c, d, a, b, in[10] + 0xffeff47d, 15); -+ MD5STEP(F4, b, c, d, a, in[1] + 0x85845dd1, 21); -+ MD5STEP(F4, a, b, c, d, in[8] + 0x6fa87e4f, 6); -+ MD5STEP(F4, d, a, b, c, in[15] + 0xfe2ce6e0, 10); -+ MD5STEP(F4, c, d, a, b, in[6] + 0xa3014314, 15); -+ MD5STEP(F4, b, c, d, a, in[13] + 0x4e0811a1, 21); -+ MD5STEP(F4, a, b, c, d, in[4] + 0xf7537e82, 6); -+ MD5STEP(F4, d, a, b, c, in[11] + 0xbd3af235, 10); -+ MD5STEP(F4, c, d, a, b, in[2] + 0x2ad7d2bb, 15); -+ MD5STEP(F4, b, c, d, a, in[9] + 0xeb86d391, 21); -+ -+ buf[0] += a; -+ buf[1] += b; -+ buf[2] += c; -+ buf[3] += d; -+} -+ -+void mvMD5(unsigned char const *buf, unsigned len, unsigned char* digest) -+{ -+ MV_MD5_CONTEXT ctx; -+ -+ mvMD5Init(&ctx); -+ mvMD5Update(&ctx, buf, len); -+ mvMD5Final(digest, &ctx); -+} -+ -+ -+void mvHmacMd5(unsigned char const* text, int text_len, -+ unsigned char const* key, int key_len, -+ unsigned char* digest) -+{ -+ int i; -+ MV_MD5_CONTEXT ctx; -+ unsigned char k_ipad[64+1]; /* inner padding - key XORd with ipad */ -+ unsigned char k_opad[64+1]; /* outer padding - key XORd with opad */ -+ -+ /* start out by storing key in pads */ -+ memset(k_ipad, 0, 64); -+ memcpy(k_ipad, key, key_len); -+ memset(k_opad, 0, 64); -+ memcpy(k_opad, key, key_len); -+ -+ /* XOR key with ipad and opad values */ -+ for (i=0; i<64; i++) -+ { -+ k_ipad[i] ^= 0x36; -+ k_opad[i] ^= 0x5c; -+ } -+ -+ /* perform inner MD5 */ -+ mvMD5Init(&ctx); /* init ctx for 1st pass */ -+ mvMD5Update(&ctx, k_ipad, 64); /* start with inner pad */ -+ mvMD5Update(&ctx, text, text_len); /* then text of datagram */ -+ mvMD5Final(digest, &ctx); /* finish up 1st pass */ -+ -+ /* perform outer MD5 */ -+ mvMD5Init(&ctx); /* init ctx for 2nd pass */ -+ mvMD5Update(&ctx, k_opad, 64); /* start with outer pad */ -+ mvMD5Update(&ctx, digest, 16); /* then results of 1st hash */ -+ mvMD5Final(digest, &ctx); /* finish up 2nd pass */ -+} -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvMD5.h linux-3.0.4/crypto/ocf/kirkwood/cesa/mvMD5.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvMD5.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/cesa/mvMD5.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,93 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __mvMD5_h__ -+#define __mvMD5_h__ -+ -+#include "mvMD5.h" -+ -+#define MV_MD5_MAC_LEN 16 -+ -+ -+typedef struct -+{ -+ MV_U32 buf[4]; -+ MV_U32 bits[2]; -+ MV_U8 in[64]; -+ -+} MV_MD5_CONTEXT; -+ -+void mvMD5Init(MV_MD5_CONTEXT *context); -+void mvMD5Update(MV_MD5_CONTEXT *context, unsigned char const *buf, -+ unsigned len); -+void mvMD5Final(unsigned char digest[16], MV_MD5_CONTEXT *context); -+ -+void mvMD5(unsigned char const *buf, unsigned len, unsigned char* digest); -+ -+void mvHmacMd5(unsigned char const* text, int text_len, -+ unsigned char const* key, int key_len, -+ unsigned char* digest); -+ -+ -+#endif /* __mvMD5_h__ */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvSHA1.c linux-3.0.4/crypto/ocf/kirkwood/cesa/mvSHA1.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvSHA1.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/cesa/mvSHA1.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,239 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "mvOs.h" -+#include "mvSHA1.h" -+ -+#define SHA1HANDSOFF -+ -+typedef union -+{ -+ MV_U8 c[64]; -+ MV_U32 l[16]; -+ -+} CHAR64LONG16; -+ -+static void mvSHA1Transform(MV_U32 state[5], const MV_U8 *buffer); -+ -+#define rol(value, bits) (((value) << (bits)) | ((value) >> (32 - (bits)))) -+ -+ -+#ifdef MV_CPU_LE -+#define blk0(i) (block->l[i] = (rol(block->l[i], 24) & 0xFF00FF00) | \ -+ (rol(block->l[i], 8) & 0x00FF00FF)) -+#else -+#define blk0(i) block->l[i] -+#endif -+#define blk(i) (block->l[i & 15] = rol(block->l[(i + 13) & 15] ^ \ -+ block->l[(i + 8) & 15] ^ block->l[(i + 2) & 15] ^ block->l[i & 15], 1)) -+ -+/* (R0+R1), R2, R3, R4 are the different operations used in SHA1 */ -+#define R0(v,w,x,y,z,i) \ -+ z += ((w & (x ^ y)) ^ y) + blk0(i) + 0x5A827999 + rol(v, 5); \ -+ w = rol(w, 30); -+#define R1(v,w,x,y,z,i) \ -+ z += ((w & (x ^ y)) ^ y) + blk(i) + 0x5A827999 + rol(v, 5); \ -+ w = rol(w, 30); -+#define R2(v,w,x,y,z,i) \ -+ z += (w ^ x ^ y) + blk(i) + 0x6ED9EBA1 + rol(v, 5); w = rol(w, 30); -+#define R3(v,w,x,y,z,i) \ -+ z += (((w | x) & y) | (w & x)) + blk(i) + 0x8F1BBCDC + rol(v, 5); \ -+ w = rol(w, 30); -+#define R4(v,w,x,y,z,i) \ -+ z += (w ^ x ^ y) + blk(i) + 0xCA62C1D6 + rol(v, 5); \ -+ w=rol(w, 30); -+ -+/* Hash a single 512-bit block. This is the core of the algorithm. */ -+static void mvSHA1Transform(MV_U32 state[5], const MV_U8 *buffer) -+{ -+ MV_U32 a, b, c, d, e; -+ CHAR64LONG16* block; -+ -+#ifdef SHA1HANDSOFF -+ static MV_U32 workspace[16]; -+ -+ block = (CHAR64LONG16 *) workspace; -+ memcpy(block, buffer, 64); -+#else -+ block = (CHAR64LONG16 *) buffer; -+#endif -+ /* Copy context->state[] to working vars */ -+ a = state[0]; -+ b = state[1]; -+ c = state[2]; -+ d = state[3]; -+ e = state[4]; -+ /* 4 rounds of 20 operations each. Loop unrolled. */ -+ R0(a,b,c,d,e, 0); R0(e,a,b,c,d, 1); R0(d,e,a,b,c, 2); R0(c,d,e,a,b, 3); -+ R0(b,c,d,e,a, 4); R0(a,b,c,d,e, 5); R0(e,a,b,c,d, 6); R0(d,e,a,b,c, 7); -+ R0(c,d,e,a,b, 8); R0(b,c,d,e,a, 9); R0(a,b,c,d,e,10); R0(e,a,b,c,d,11); -+ R0(d,e,a,b,c,12); R0(c,d,e,a,b,13); R0(b,c,d,e,a,14); R0(a,b,c,d,e,15); -+ R1(e,a,b,c,d,16); R1(d,e,a,b,c,17); R1(c,d,e,a,b,18); R1(b,c,d,e,a,19); -+ R2(a,b,c,d,e,20); R2(e,a,b,c,d,21); R2(d,e,a,b,c,22); R2(c,d,e,a,b,23); -+ R2(b,c,d,e,a,24); R2(a,b,c,d,e,25); R2(e,a,b,c,d,26); R2(d,e,a,b,c,27); -+ R2(c,d,e,a,b,28); R2(b,c,d,e,a,29); R2(a,b,c,d,e,30); R2(e,a,b,c,d,31); -+ R2(d,e,a,b,c,32); R2(c,d,e,a,b,33); R2(b,c,d,e,a,34); R2(a,b,c,d,e,35); -+ R2(e,a,b,c,d,36); R2(d,e,a,b,c,37); R2(c,d,e,a,b,38); R2(b,c,d,e,a,39); -+ R3(a,b,c,d,e,40); R3(e,a,b,c,d,41); R3(d,e,a,b,c,42); R3(c,d,e,a,b,43); -+ R3(b,c,d,e,a,44); R3(a,b,c,d,e,45); R3(e,a,b,c,d,46); R3(d,e,a,b,c,47); -+ R3(c,d,e,a,b,48); R3(b,c,d,e,a,49); R3(a,b,c,d,e,50); R3(e,a,b,c,d,51); -+ R3(d,e,a,b,c,52); R3(c,d,e,a,b,53); R3(b,c,d,e,a,54); R3(a,b,c,d,e,55); -+ R3(e,a,b,c,d,56); R3(d,e,a,b,c,57); R3(c,d,e,a,b,58); R3(b,c,d,e,a,59); -+ R4(a,b,c,d,e,60); R4(e,a,b,c,d,61); R4(d,e,a,b,c,62); R4(c,d,e,a,b,63); -+ R4(b,c,d,e,a,64); R4(a,b,c,d,e,65); R4(e,a,b,c,d,66); R4(d,e,a,b,c,67); -+ R4(c,d,e,a,b,68); R4(b,c,d,e,a,69); R4(a,b,c,d,e,70); R4(e,a,b,c,d,71); -+ R4(d,e,a,b,c,72); R4(c,d,e,a,b,73); R4(b,c,d,e,a,74); R4(a,b,c,d,e,75); -+ R4(e,a,b,c,d,76); R4(d,e,a,b,c,77); R4(c,d,e,a,b,78); R4(b,c,d,e,a,79); -+ /* Add the working vars back into context.state[] */ -+ state[0] += a; -+ state[1] += b; -+ state[2] += c; -+ state[3] += d; -+ state[4] += e; -+ /* Wipe variables */ -+ a = b = c = d = e = 0; -+} -+ -+void mvSHA1Init(MV_SHA1_CTX* context) -+{ -+ /* SHA1 initialization constants */ -+ context->state[0] = 0x67452301; -+ context->state[1] = 0xEFCDAB89; -+ context->state[2] = 0x98BADCFE; -+ context->state[3] = 0x10325476; -+ context->state[4] = 0xC3D2E1F0; -+ context->count[0] = context->count[1] = 0; -+} -+ -+ -+/* Run your data through this. */ -+void mvSHA1Update(MV_SHA1_CTX *context, MV_U8 const *data, -+ unsigned int len) -+{ -+ MV_U32 i, j; -+ -+ j = (context->count[0] >> 3) & 63; -+ if ((context->count[0] += len << 3) < (len << 3)) -+ context->count[1]++; -+ context->count[1] += (len >> 29); -+ if ((j + len) > 63) -+ { -+ memcpy(&context->buffer[j], data, (i = 64-j)); -+ mvSHA1Transform(context->state, context->buffer); -+ for ( ; i + 63 < len; i += 64) -+ { -+ mvSHA1Transform(context->state, &data[i]); -+ } -+ j = 0; -+ } -+ else -+ { -+ i = 0; -+ } -+ memcpy(&context->buffer[j], &data[i], len - i); -+} -+ -+void mvSHA1Final(MV_U8* digest, MV_SHA1_CTX* context) -+{ -+ MV_U32 i; -+ MV_U8 finalcount[8]; -+ -+ for (i = 0; i < 8; i++) -+ { -+ finalcount[i] = (unsigned char)((context->count[(i >= 4 ? 0 : 1)] >> -+ ((3-(i & 3)) * 8) ) & 255); /* Endian independent */ -+ } -+ mvSHA1Update(context, (const unsigned char *) "\200", 1); -+ while ((context->count[0] & 504) != 448) -+ { -+ mvSHA1Update(context, (const unsigned char *) "\0", 1); -+ } -+ mvSHA1Update(context, finalcount, 8); /* Should cause a mvSHA1Transform() -+ */ -+ for (i = 0; i < 20; i++) -+ { -+ digest[i] = (unsigned char) -+ ((context->state[i >> 2] >> ((3 - (i & 3)) * 8)) & 255); -+ } -+ /* Wipe variables */ -+ i = 0; -+ memset(context->buffer, 0, 64); -+ memset(context->state, 0, 20); -+ memset(context->count, 0, 8); -+ memset(finalcount, 0, 8); -+ -+#ifdef SHA1HANDSOFF /* make SHA1Transform overwrite it's own static vars */ -+ mvSHA1Transform(context->state, context->buffer); -+#endif -+} -+ -+ -+void mvSHA1(MV_U8 const *buf, unsigned int len, MV_U8* digest) -+{ -+ MV_SHA1_CTX ctx; -+ -+ mvSHA1Init(&ctx); -+ mvSHA1Update(&ctx, buf, len); -+ mvSHA1Final(digest, &ctx); -+} -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvSHA1.h linux-3.0.4/crypto/ocf/kirkwood/cesa/mvSHA1.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvSHA1.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/cesa/mvSHA1.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,88 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __mvSHA1_h__ -+#define __mvSHA1_h__ -+ -+#include "mvSHA1.h" -+ -+#define MV_SHA1_MAC_LEN 20 -+ -+ -+typedef struct -+{ -+ MV_U32 state[5]; -+ MV_U32 count[2]; -+ MV_U8 buffer[64]; -+ -+} MV_SHA1_CTX; -+ -+void mvSHA1Init(MV_SHA1_CTX *context); -+void mvSHA1Update(MV_SHA1_CTX *context, MV_U8 const *buf, unsigned int len); -+void mvSHA1Final(MV_U8* digest, MV_SHA1_CTX *context); -+ -+void mvSHA1(MV_U8 const *buf, unsigned int len, MV_U8* digest); -+ -+ -+#endif /* __mvSHA1_h__ */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa_ocf_drv.c linux-3.0.4/crypto/ocf/kirkwood/cesa_ocf_drv.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa_ocf_drv.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/cesa_ocf_drv.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,1297 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+*******************************************************************************/ -+ -+#include -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "ctrlEnv/sys/mvSysCesa.h" -+#include "cesa/mvCesa.h" /* moved here before cryptodev.h due to include dependencies */ -+#include -+#include -+#include -+#include -+#include "mvDebug.h" -+ -+#include "cesa/mvMD5.h" -+#include "cesa/mvSHA1.h" -+ -+#include "cesa/mvCesaRegs.h" -+#include "cesa/AES/mvAes.h" -+#include "cesa/mvLru.h" -+ -+#undef RT_DEBUG -+#ifdef RT_DEBUG -+static int debug = 1; -+module_param(debug, int, 1); -+MODULE_PARM_DESC(debug, "Enable debug"); -+#undef dprintk -+#define dprintk(a...) if (debug) { printk(a); } else -+#else -+static int debug = 0; -+#undef dprintk -+#define dprintk(a...) -+#endif -+ -+ -+/* TDMA Regs */ -+#define WINDOW_BASE(i) 0xA00 + (i << 3) -+#define WINDOW_CTRL(i) 0xA04 + (i << 3) -+ -+/* interrupt handling */ -+#undef CESA_OCF_POLLING -+#undef CESA_OCF_TASKLET -+ -+#if defined(CESA_OCF_POLLING) && defined(CESA_OCF_TASKLET) -+#error "don't use both tasklet and polling mode" -+#endif -+ -+extern int cesaReqResources; -+/* support for spliting action into 2 actions */ -+#define CESA_OCF_SPLIT -+ -+/* general defines */ -+#define CESA_OCF_MAX_SES 128 -+#define CESA_Q_SIZE 64 -+ -+ -+/* data structures */ -+struct cesa_ocf_data { -+ int cipher_alg; -+ int auth_alg; -+ int encrypt_tn_auth; -+#define auth_tn_decrypt encrypt_tn_auth -+ int ivlen; -+ int digestlen; -+ short sid_encrypt; -+ short sid_decrypt; -+ /* fragment workaround sessions */ -+ short frag_wa_encrypt; -+ short frag_wa_decrypt; -+ short frag_wa_auth; -+}; -+ -+/* CESA device data */ -+struct cesa_dev { -+ void __iomem *sram; -+ void __iomem *reg; -+ struct mv_cesa_platform_data *plat_data; -+ int irq; -+}; -+ -+#define DIGEST_BUF_SIZE 32 -+struct cesa_ocf_process { -+ MV_CESA_COMMAND cesa_cmd; -+ MV_CESA_MBUF cesa_mbuf; -+ MV_BUF_INFO cesa_bufs[MV_CESA_MAX_MBUF_FRAGS]; -+ char digest[DIGEST_BUF_SIZE]; -+ int digest_len; -+ struct cryptop *crp; -+ int need_cb; -+}; -+ -+/* global variables */ -+static int32_t cesa_ocf_id = -1; -+static struct cesa_ocf_data *cesa_ocf_sessions[CESA_OCF_MAX_SES]; -+static spinlock_t cesa_lock; -+static struct cesa_dev cesa_device; -+ -+/* static APIs */ -+static int cesa_ocf_process (device_t, struct cryptop *, int); -+static int cesa_ocf_newsession (device_t, u_int32_t *, struct cryptoini *); -+static int cesa_ocf_freesession (device_t, u_int64_t); -+static void cesa_callback (unsigned long); -+static irqreturn_t cesa_interrupt_handler (int, void *); -+#ifdef CESA_OCF_POLLING -+static void cesa_interrupt_polling(void); -+#endif -+#ifdef CESA_OCF_TASKLET -+static struct tasklet_struct cesa_ocf_tasklet; -+#endif -+ -+static struct timeval tt_start; -+static struct timeval tt_end; -+ -+/* -+ * dummy device structure -+ */ -+ -+static struct { -+ softc_device_decl sc_dev; -+} mv_cesa_dev; -+ -+static device_method_t mv_cesa_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, cesa_ocf_newsession), -+ DEVMETHOD(cryptodev_freesession,cesa_ocf_freesession), -+ DEVMETHOD(cryptodev_process, cesa_ocf_process), -+ DEVMETHOD(cryptodev_kprocess, NULL), -+}; -+ -+ -+ -+/* Add debug Trace */ -+#undef CESA_OCF_TRACE_DEBUG -+#ifdef CESA_OCF_TRACE_DEBUG -+ -+#define MV_CESA_USE_TIMER_ID 0 -+ -+typedef struct -+{ -+ int type; /* 0 - isrEmpty, 1 - cesaReadyGet, 2 - cesaAction */ -+ MV_U32 timeStamp; -+ MV_U32 cause; -+ MV_U32 realCause; -+ MV_U32 dmaCause; -+ int resources; -+ MV_CESA_REQ* pReqReady; -+ MV_CESA_REQ* pReqEmpty; -+ MV_CESA_REQ* pReqProcess; -+} MV_CESA_TEST_TRACE; -+ -+#define MV_CESA_TEST_TRACE_SIZE 50 -+ -+static int cesaTestTraceIdx = 0; -+static MV_CESA_TEST_TRACE cesaTestTrace[MV_CESA_TEST_TRACE_SIZE]; -+ -+static void cesaTestTraceAdd(int type) -+{ -+ cesaTestTrace[cesaTestTraceIdx].type = type; -+ cesaTestTrace[cesaTestTraceIdx].realCause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); -+ //cesaTestTrace[cesaTestTraceIdx].idmaCause = MV_REG_READ(IDMA_CAUSE_REG); -+ cesaTestTrace[cesaTestTraceIdx].resources = cesaReqResources; -+ cesaTestTrace[cesaTestTraceIdx].pReqReady = pCesaReqReady; -+ cesaTestTrace[cesaTestTraceIdx].pReqEmpty = pCesaReqEmpty; -+ cesaTestTrace[cesaTestTraceIdx].pReqProcess = pCesaReqProcess; -+ cesaTestTrace[cesaTestTraceIdx].timeStamp = mvCntmrRead(MV_CESA_USE_TIMER_ID); -+ cesaTestTraceIdx++; -+ if(cesaTestTraceIdx == MV_CESA_TEST_TRACE_SIZE) -+ cesaTestTraceIdx = 0; -+} -+ -+#else /* CESA_OCF_TRACE_DEBUG */ -+ -+#define cesaTestTraceAdd(x) -+ -+#endif /* CESA_OCF_TRACE_DEBUG */ -+ -+unsigned int -+get_usec(unsigned int start) -+{ -+ if(start) { -+ do_gettimeofday (&tt_start); -+ return 0; -+ } -+ else { -+ do_gettimeofday (&tt_end); -+ tt_end.tv_sec -= tt_start.tv_sec; -+ tt_end.tv_usec -= tt_start.tv_usec; -+ if (tt_end.tv_usec < 0) { -+ tt_end.tv_usec += 1000 * 1000; -+ tt_end.tv_sec -= 1; -+ } -+ } -+ printk("time taken is %d\n", (unsigned int)(tt_end.tv_usec + tt_end.tv_sec * 1000000)); -+ return (tt_end.tv_usec + tt_end.tv_sec * 1000000); -+} -+ -+#ifdef RT_DEBUG -+/* -+ * check that the crp action match the current session -+ */ -+static int -+ocf_check_action(struct cryptop *crp, struct cesa_ocf_data *cesa_ocf_cur_ses) { -+ int count = 0; -+ int encrypt = 0, decrypt = 0, auth = 0; -+ struct cryptodesc *crd; -+ -+ /* Go through crypto descriptors, processing as we go */ -+ for (crd = crp->crp_desc; crd; crd = crd->crd_next, count++) { -+ if(count > 2) { -+ printk("%s,%d: session mode is not supported.\n", __FILE__, __LINE__); -+ return 1; -+ } -+ -+ /* Encryption /Decryption */ -+ if(crd->crd_alg == cesa_ocf_cur_ses->cipher_alg) { -+ /* check that the action is compatible with session */ -+ if(encrypt || decrypt) { -+ printk("%s,%d: session mode is not supported.\n", __FILE__, __LINE__); -+ return 1; -+ } -+ -+ if(crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ -+ if( (count == 2) && (cesa_ocf_cur_ses->encrypt_tn_auth) ) { -+ printk("%s,%d: sequence isn't supported by this session.\n", __FILE__, __LINE__); -+ return 1; -+ } -+ encrypt++; -+ } -+ else { /* decrypt */ -+ if( (count == 2) && !(cesa_ocf_cur_ses->auth_tn_decrypt) ) { -+ printk("%s,%d: sequence isn't supported by this session.\n", __FILE__, __LINE__); -+ return 1; -+ } -+ decrypt++; -+ } -+ -+ } -+ /* Authentication */ -+ else if(crd->crd_alg == cesa_ocf_cur_ses->auth_alg) { -+ /* check that the action is compatible with session */ -+ if(auth) { -+ printk("%s,%d: session mode is not supported.\n", __FILE__, __LINE__); -+ return 1; -+ } -+ if( (count == 2) && (decrypt) && (cesa_ocf_cur_ses->auth_tn_decrypt)) { -+ printk("%s,%d: sequence isn't supported by this session.\n", __FILE__, __LINE__); -+ return 1; -+ } -+ if( (count == 2) && (encrypt) && !(cesa_ocf_cur_ses->encrypt_tn_auth)) { -+ printk("%s,%d: sequence isn't supported by this session.\n", __FILE__, __LINE__); -+ return 1; -+ } -+ auth++; -+ } -+ else { -+ printk("%s,%d: Alg isn't supported by this session.\n", __FILE__, __LINE__); -+ return 1; -+ } -+ } -+ return 0; -+ -+} -+#endif -+ -+/* -+ * Process a request. -+ */ -+static int -+cesa_ocf_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ struct cesa_ocf_process *cesa_ocf_cmd = NULL; -+ struct cesa_ocf_process *cesa_ocf_cmd_wa = NULL; -+ MV_CESA_COMMAND *cesa_cmd; -+ struct cryptodesc *crd; -+ struct cesa_ocf_data *cesa_ocf_cur_ses; -+ int sid = 0, temp_len = 0, i; -+ int encrypt = 0, decrypt = 0, auth = 0; -+ int status; -+ struct sk_buff *skb = NULL; -+ struct uio *uiop = NULL; -+ unsigned char *ivp; -+ MV_BUF_INFO *p_buf_info; -+ MV_CESA_MBUF *p_mbuf_info; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if( cesaReqResources <= 1 ) { -+ dprintk("%s,%d: ERESTART\n", __FILE__, __LINE__); -+ return ERESTART; -+ } -+ -+#ifdef RT_DEBUG -+ /* Sanity check */ -+ if (crp == NULL) { -+ printk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ if (crp->crp_desc == NULL || crp->crp_buf == NULL ) { -+ printk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ return EINVAL; -+ } -+ -+ sid = crp->crp_sid & 0xffffffff; -+ if ((sid >= CESA_OCF_MAX_SES) || (cesa_ocf_sessions[sid] == NULL)) { -+ crp->crp_etype = ENOENT; -+ printk("%s,%d: ENOENT session %d \n", __FILE__, __LINE__, sid); -+ return EINVAL; -+ } -+#endif -+ -+ sid = crp->crp_sid & 0xffffffff; -+ crp->crp_etype = 0; -+ cesa_ocf_cur_ses = cesa_ocf_sessions[sid]; -+ -+#ifdef RT_DEBUG -+ if(ocf_check_action(crp, cesa_ocf_cur_ses)){ -+ goto p_error; -+ } -+#endif -+ -+ /* malloc a new cesa process */ -+ cesa_ocf_cmd = kmalloc(sizeof(struct cesa_ocf_process), GFP_ATOMIC); -+ -+ if (cesa_ocf_cmd == NULL) { -+ printk("%s,%d: ENOBUFS \n", __FILE__, __LINE__); -+ goto p_error; -+ } -+ memset(cesa_ocf_cmd, 0, sizeof(struct cesa_ocf_process)); -+ -+ /* init cesa_process */ -+ cesa_ocf_cmd->crp = crp; -+ /* always call callback */ -+ cesa_ocf_cmd->need_cb = 1; -+ -+ /* init cesa_cmd for usage of the HALs */ -+ cesa_cmd = &cesa_ocf_cmd->cesa_cmd; -+ cesa_cmd->pReqPrv = (void *)cesa_ocf_cmd; -+ cesa_cmd->sessionId = cesa_ocf_cur_ses->sid_encrypt; /* defualt use encrypt */ -+ -+ /* prepare src buffer */ -+ /* we send the entire buffer to the HAL, even if only part of it should be encrypt/auth. */ -+ /* if not using seesions for both encrypt and auth, then it will be wiser to to copy only */ -+ /* from skip to crd_len. */ -+ p_buf_info = cesa_ocf_cmd->cesa_bufs; -+ p_mbuf_info = &cesa_ocf_cmd->cesa_mbuf; -+ -+ p_buf_info += 2; /* save 2 first buffers for IV and digest - -+ we won't append them to the end since, they -+ might be places in an unaligned addresses. */ -+ -+ p_mbuf_info->pFrags = p_buf_info; -+ temp_len = 0; -+ -+ /* handle SKB */ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ -+ dprintk("%s,%d: handle SKB.\n", __FILE__, __LINE__); -+ skb = (struct sk_buff *) crp->crp_buf; -+ -+ if (skb_shinfo(skb)->nr_frags >= (MV_CESA_MAX_MBUF_FRAGS - 1)) { -+ printk("%s,%d: %d nr_frags > MV_CESA_MAX_MBUF_FRAGS", __FILE__, __LINE__, skb_shinfo(skb)->nr_frags); -+ goto p_error; -+ } -+ -+ p_mbuf_info->mbufSize = skb->len; -+ temp_len = skb->len; -+ /* first skb fragment */ -+ p_buf_info->bufSize = skb_headlen(skb); -+ p_buf_info->bufVirtPtr = skb->data; -+ p_buf_info++; -+ -+ /* now handle all other skb fragments */ -+ for ( i = 0; i < skb_shinfo(skb)->nr_frags; i++ ) { -+ skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; -+ p_buf_info->bufSize = frag->size; -+ p_buf_info->bufVirtPtr = page_address(frag->page) + frag->page_offset; -+ p_buf_info++; -+ } -+ p_mbuf_info->numFrags = skb_shinfo(skb)->nr_frags + 1; -+ } -+ /* handle UIO */ -+ else if(crp->crp_flags & CRYPTO_F_IOV) { -+ -+ dprintk("%s,%d: handle UIO.\n", __FILE__, __LINE__); -+ uiop = (struct uio *) crp->crp_buf; -+ -+ if (uiop->uio_iovcnt > (MV_CESA_MAX_MBUF_FRAGS - 1)) { -+ printk("%s,%d: %d uio_iovcnt > MV_CESA_MAX_MBUF_FRAGS \n", __FILE__, __LINE__, uiop->uio_iovcnt); -+ goto p_error; -+ } -+ -+ p_mbuf_info->mbufSize = crp->crp_ilen; -+ p_mbuf_info->numFrags = uiop->uio_iovcnt; -+ for(i = 0; i < uiop->uio_iovcnt; i++) { -+ p_buf_info->bufVirtPtr = uiop->uio_iov[i].iov_base; -+ p_buf_info->bufSize = uiop->uio_iov[i].iov_len; -+ temp_len += p_buf_info->bufSize; -+ dprintk("%s,%d: buf %x-> addr %x, size %x \n" -+ , __FILE__, __LINE__, i, (unsigned int)p_buf_info->bufVirtPtr, p_buf_info->bufSize); -+ p_buf_info++; -+ } -+ -+ } -+ /* handle CONTIG */ -+ else { -+ dprintk("%s,%d: handle CONTIG.\n", __FILE__, __LINE__); -+ p_mbuf_info->numFrags = 1; -+ p_mbuf_info->mbufSize = crp->crp_ilen; -+ p_buf_info->bufVirtPtr = crp->crp_buf; -+ p_buf_info->bufSize = crp->crp_ilen; -+ temp_len = crp->crp_ilen; -+ p_buf_info++; -+ } -+ -+ /* Support up to 64K why? cause! */ -+ if(crp->crp_ilen > 64*1024) { -+ printk("%s,%d: buf too big %x \n", __FILE__, __LINE__, crp->crp_ilen); -+ goto p_error; -+ } -+ -+ if( temp_len != crp->crp_ilen ) { -+ printk("%s,%d: warning size don't match.(%x %x) \n", __FILE__, __LINE__, temp_len, crp->crp_ilen); -+ } -+ -+ cesa_cmd->pSrc = p_mbuf_info; -+ cesa_cmd->pDst = p_mbuf_info; -+ -+ /* restore p_buf_info to point to first available buf */ -+ p_buf_info = cesa_ocf_cmd->cesa_bufs; -+ p_buf_info += 1; -+ -+ -+ /* Go through crypto descriptors, processing as we go */ -+ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { -+ -+ /* Encryption /Decryption */ -+ if(crd->crd_alg == cesa_ocf_cur_ses->cipher_alg) { -+ -+ dprintk("%s,%d: cipher", __FILE__, __LINE__); -+ -+ cesa_cmd->cryptoOffset = crd->crd_skip; -+ cesa_cmd->cryptoLength = crd->crd_len; -+ -+ if(crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ -+ dprintk(" encrypt \n"); -+ encrypt++; -+ -+ /* handle IV */ -+ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { /* IV from USER */ -+ dprintk("%s,%d: IV from USER (offset %x) \n", __FILE__, __LINE__, crd->crd_inject); -+ cesa_cmd->ivFromUser = 1; -+ ivp = crd->crd_iv; -+ -+ /* -+ * do we have to copy the IV back to the buffer ? -+ */ -+ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { -+ dprintk("%s,%d: copy the IV back to the buffer\n", __FILE__, __LINE__); -+ cesa_cmd->ivOffset = crd->crd_inject; -+ crypto_copyback(crp->crp_flags, crp->crp_buf, crd->crd_inject, cesa_ocf_cur_ses->ivlen, ivp); -+ } -+ else { -+ dprintk("%s,%d: don't copy the IV back to the buffer \n", __FILE__, __LINE__); -+ p_mbuf_info->numFrags++; -+ p_mbuf_info->mbufSize += cesa_ocf_cur_ses->ivlen; -+ p_mbuf_info->pFrags = p_buf_info; -+ -+ p_buf_info->bufVirtPtr = ivp; -+ p_buf_info->bufSize = cesa_ocf_cur_ses->ivlen; -+ p_buf_info--; -+ -+ /* offsets */ -+ cesa_cmd->ivOffset = 0; -+ cesa_cmd->cryptoOffset += cesa_ocf_cur_ses->ivlen; -+ if(auth) { -+ cesa_cmd->macOffset += cesa_ocf_cur_ses->ivlen; -+ cesa_cmd->digestOffset += cesa_ocf_cur_ses->ivlen; -+ } -+ } -+ } -+ else { /* random IV */ -+ dprintk("%s,%d: random IV \n", __FILE__, __LINE__); -+ cesa_cmd->ivFromUser = 0; -+ -+ /* -+ * do we have to copy the IV back to the buffer ? -+ */ -+ /* in this mode the HAL will always copy the IV */ -+ /* given by the session to the ivOffset */ -+ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { -+ cesa_cmd->ivOffset = crd->crd_inject; -+ } -+ else { -+ /* if IV isn't copy, then how will the user know which IV did we use??? */ -+ printk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ goto p_error; -+ } -+ } -+ } -+ else { /* decrypt */ -+ dprintk(" decrypt \n"); -+ decrypt++; -+ cesa_cmd->sessionId = cesa_ocf_cur_ses->sid_decrypt; -+ -+ /* handle IV */ -+ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { -+ dprintk("%s,%d: IV from USER \n", __FILE__, __LINE__); -+ /* append the IV buf to the mbuf */ -+ cesa_cmd->ivFromUser = 1; -+ p_mbuf_info->numFrags++; -+ p_mbuf_info->mbufSize += cesa_ocf_cur_ses->ivlen; -+ p_mbuf_info->pFrags = p_buf_info; -+ -+ p_buf_info->bufVirtPtr = crd->crd_iv; -+ p_buf_info->bufSize = cesa_ocf_cur_ses->ivlen; -+ p_buf_info--; -+ -+ /* offsets */ -+ cesa_cmd->ivOffset = 0; -+ cesa_cmd->cryptoOffset += cesa_ocf_cur_ses->ivlen; -+ if(auth) { -+ cesa_cmd->macOffset += cesa_ocf_cur_ses->ivlen; -+ cesa_cmd->digestOffset += cesa_ocf_cur_ses->ivlen; -+ } -+ } -+ else { -+ dprintk("%s,%d: IV inside the buffer \n", __FILE__, __LINE__); -+ cesa_cmd->ivFromUser = 0; -+ cesa_cmd->ivOffset = crd->crd_inject; -+ } -+ } -+ -+ } -+ /* Authentication */ -+ else if(crd->crd_alg == cesa_ocf_cur_ses->auth_alg) { -+ dprintk("%s,%d: Authentication \n", __FILE__, __LINE__); -+ auth++; -+ cesa_cmd->macOffset = crd->crd_skip; -+ cesa_cmd->macLength = crd->crd_len; -+ -+ /* digest + mac */ -+ cesa_cmd->digestOffset = crd->crd_inject; -+ } -+ else { -+ printk("%s,%d: Alg isn't supported by this session.\n", __FILE__, __LINE__); -+ goto p_error; -+ } -+ } -+ -+ dprintk("\n"); -+ dprintk("%s,%d: Sending Action: \n", __FILE__, __LINE__); -+ dprintk("%s,%d: IV from user: %d. IV offset %x \n", __FILE__, __LINE__, cesa_cmd->ivFromUser, cesa_cmd->ivOffset); -+ dprintk("%s,%d: crypt offset %x len %x \n", __FILE__, __LINE__, cesa_cmd->cryptoOffset, cesa_cmd->cryptoLength); -+ dprintk("%s,%d: Auth offset %x len %x \n", __FILE__, __LINE__, cesa_cmd->macOffset, cesa_cmd->macLength); -+ dprintk("%s,%d: set digest in offset %x . \n", __FILE__, __LINE__, cesa_cmd->digestOffset); -+ if(debug) { -+ mvCesaDebugMbuf("SRC BUFFER", cesa_cmd->pSrc, 0, cesa_cmd->pSrc->mbufSize); -+ } -+ -+ -+ /* send action to HAL */ -+ spin_lock_irqsave(&cesa_lock, flags); -+ status = mvCesaAction(cesa_cmd); -+ spin_unlock_irqrestore(&cesa_lock, flags); -+ -+ /* action not allowed */ -+ if(status == MV_NOT_ALLOWED) { -+#ifdef CESA_OCF_SPLIT -+ /* if both encrypt and auth try to split */ -+ if(auth && (encrypt || decrypt)) { -+ MV_CESA_COMMAND *cesa_cmd_wa; -+ -+ /* malloc a new cesa process and init it */ -+ cesa_ocf_cmd_wa = kmalloc(sizeof(struct cesa_ocf_process), GFP_ATOMIC); -+ -+ if (cesa_ocf_cmd_wa == NULL) { -+ printk("%s,%d: ENOBUFS \n", __FILE__, __LINE__); -+ goto p_error; -+ } -+ memcpy(cesa_ocf_cmd_wa, cesa_ocf_cmd, sizeof(struct cesa_ocf_process)); -+ cesa_cmd_wa = &cesa_ocf_cmd_wa->cesa_cmd; -+ cesa_cmd_wa->pReqPrv = (void *)cesa_ocf_cmd_wa; -+ cesa_ocf_cmd_wa->need_cb = 0; -+ -+ /* break requests to two operation, first operation completion won't call callback */ -+ if((decrypt) && (cesa_ocf_cur_ses->auth_tn_decrypt)) { -+ cesa_cmd_wa->sessionId = cesa_ocf_cur_ses->frag_wa_auth; -+ cesa_cmd->sessionId = cesa_ocf_cur_ses->frag_wa_decrypt; -+ } -+ else if((decrypt) && !(cesa_ocf_cur_ses->auth_tn_decrypt)) { -+ cesa_cmd_wa->sessionId = cesa_ocf_cur_ses->frag_wa_decrypt; -+ cesa_cmd->sessionId = cesa_ocf_cur_ses->frag_wa_auth; -+ } -+ else if((encrypt) && (cesa_ocf_cur_ses->encrypt_tn_auth)) { -+ cesa_cmd_wa->sessionId = cesa_ocf_cur_ses->frag_wa_encrypt; -+ cesa_cmd->sessionId = cesa_ocf_cur_ses->frag_wa_auth; -+ } -+ else if((encrypt) && !(cesa_ocf_cur_ses->encrypt_tn_auth)){ -+ cesa_cmd_wa->sessionId = cesa_ocf_cur_ses->frag_wa_auth; -+ cesa_cmd->sessionId = cesa_ocf_cur_ses->frag_wa_encrypt; -+ } -+ else { -+ printk("%s,%d: Unsupporterd fragment wa mode \n", __FILE__, __LINE__); -+ goto p_error; -+ } -+ -+ /* send the 2 actions to the HAL */ -+ spin_lock_irqsave(&cesa_lock, flags); -+ status = mvCesaAction(cesa_cmd_wa); -+ spin_unlock_irqrestore(&cesa_lock, flags); -+ -+ if((status != MV_NO_MORE) && (status != MV_OK)) { -+ printk("%s,%d: cesa action failed, status = 0x%x\n", __FILE__, __LINE__, status); -+ goto p_error; -+ } -+ spin_lock_irqsave(&cesa_lock, flags); -+ status = mvCesaAction(cesa_cmd); -+ spin_unlock_irqrestore(&cesa_lock, flags); -+ -+ } -+ /* action not allowed and can't split */ -+ else -+#endif -+ { -+ goto p_error; -+ } -+ } -+ -+ /* Hal Q is full, send again. This should never happen */ -+ if(status == MV_NO_RESOURCE) { -+ printk("%s,%d: cesa no more resources \n", __FILE__, __LINE__); -+ if(cesa_ocf_cmd) -+ kfree(cesa_ocf_cmd); -+ if(cesa_ocf_cmd_wa) -+ kfree(cesa_ocf_cmd_wa); -+ return ERESTART; -+ } -+ else if((status != MV_NO_MORE) && (status != MV_OK)) { -+ printk("%s,%d: cesa action failed, status = 0x%x\n", __FILE__, __LINE__, status); -+ goto p_error; -+ } -+ -+ -+#ifdef CESA_OCF_POLLING -+ cesa_interrupt_polling(); -+#endif -+ cesaTestTraceAdd(5); -+ -+ return 0; -+p_error: -+ crp->crp_etype = EINVAL; -+ if(cesa_ocf_cmd) -+ kfree(cesa_ocf_cmd); -+ if(cesa_ocf_cmd_wa) -+ kfree(cesa_ocf_cmd_wa); -+ return EINVAL; -+} -+ -+/* -+ * cesa callback. -+ */ -+static void -+cesa_callback(unsigned long dummy) -+{ -+ struct cesa_ocf_process *cesa_ocf_cmd = NULL; -+ struct cryptop *crp = NULL; -+ MV_CESA_RESULT result[MV_CESA_MAX_CHAN]; -+ int res_idx = 0,i; -+ MV_STATUS status; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+#ifdef CESA_OCF_TASKLET -+ disable_irq(cesa_device.irq); -+#endif -+ while(MV_TRUE) { -+ -+ /* Get Ready requests */ -+ spin_lock(&cesa_lock); -+ status = mvCesaReadyGet(&result[res_idx]); -+ spin_unlock(&cesa_lock); -+ -+ cesaTestTraceAdd(2); -+ -+ if(status != MV_OK) { -+#ifdef CESA_OCF_POLLING -+ if(status == MV_BUSY) { /* Fragment */ -+ cesa_interrupt_polling(); -+ return; -+ } -+#endif -+ break; -+ } -+ res_idx++; -+ break; -+ } -+ -+ for(i = 0; i < res_idx; i++) { -+ -+ if(!result[i].pReqPrv) { -+ printk("%s,%d: warning private is NULL\n", __FILE__, __LINE__); -+ break; -+ } -+ -+ cesa_ocf_cmd = result[i].pReqPrv; -+ crp = cesa_ocf_cmd->crp; -+ -+ // ignore HMAC error. -+ //if(result->retCode) -+ // crp->crp_etype = EIO; -+ -+#if defined(CESA_OCF_POLLING) -+ if(!cesa_ocf_cmd->need_cb){ -+ cesa_interrupt_polling(); -+ } -+#endif -+ if(cesa_ocf_cmd->need_cb) { -+ if(debug) { -+ mvCesaDebugMbuf("DST BUFFER", cesa_ocf_cmd->cesa_cmd.pDst, 0, cesa_ocf_cmd->cesa_cmd.pDst->mbufSize); -+ } -+ crypto_done(crp); -+ } -+ kfree(cesa_ocf_cmd); -+ } -+#ifdef CESA_OCF_TASKLET -+ enable_irq(cesa_device.irq); -+#endif -+ -+ cesaTestTraceAdd(3); -+ -+ return; -+} -+ -+#ifdef CESA_OCF_POLLING -+static void -+cesa_interrupt_polling(void) -+{ -+ u32 cause; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ /* Read cause register */ -+ do { -+ cause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); -+ cause &= MV_CESA_CAUSE_ACC_DMA_ALL_MASK; -+ -+ } while (cause == 0); -+ -+ /* clear interrupts */ -+ MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); -+ -+ cesa_callback(0); -+ -+ return; -+} -+ -+#endif -+ -+/* -+ * cesa Interrupt polling routine. -+ */ -+static irqreturn_t -+cesa_interrupt_handler(int irq, void *arg) -+{ -+ u32 cause; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ cesaTestTraceAdd(0); -+ -+ /* Read cause register */ -+ cause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); -+ -+ if( (cause & MV_CESA_CAUSE_ACC_DMA_ALL_MASK) == 0) -+ { -+ /* Empty interrupt */ -+ dprintk("%s,%d: cesaTestReadyIsr: cause=0x%x\n", __FILE__, __LINE__, cause); -+ return IRQ_HANDLED; -+ } -+ -+ /* clear interrupts */ -+ MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); -+ -+ cesaTestTraceAdd(1); -+#ifdef CESA_OCF_TASKLET -+ tasklet_hi_schedule(&cesa_ocf_tasklet); -+#else -+ cesa_callback(0); -+#endif -+ return IRQ_HANDLED; -+} -+ -+/* -+ * Open a session. -+ */ -+static int -+/*cesa_ocf_newsession(void *arg, u_int32_t *sid, struct cryptoini *cri)*/ -+cesa_ocf_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) -+{ -+ u32 status = 0, i; -+ u32 count = 0, auth = 0, encrypt =0; -+ struct cesa_ocf_data *cesa_ocf_cur_ses; -+ MV_CESA_OPEN_SESSION cesa_session; -+ MV_CESA_OPEN_SESSION *cesa_ses = &cesa_session; -+ -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid == NULL || cri == NULL) { -+ printk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ /* leave first empty like in other implementations */ -+ for (i = 1; i < CESA_OCF_MAX_SES; i++) { -+ if (cesa_ocf_sessions[i] == NULL) -+ break; -+ } -+ -+ if(i >= CESA_OCF_MAX_SES) { -+ printk("%s,%d: no more sessions \n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ cesa_ocf_sessions[i] = (struct cesa_ocf_data *) kmalloc(sizeof(struct cesa_ocf_data), GFP_ATOMIC); -+ if (cesa_ocf_sessions[i] == NULL) { -+ cesa_ocf_freesession(NULL, i); -+ printk("%s,%d: ENOBUFS \n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ dprintk("%s,%d: new session %d \n", __FILE__, __LINE__, i); -+ -+ *sid = i; -+ cesa_ocf_cur_ses = cesa_ocf_sessions[i]; -+ memset(cesa_ocf_cur_ses, 0, sizeof(struct cesa_ocf_data)); -+ cesa_ocf_cur_ses->sid_encrypt = -1; -+ cesa_ocf_cur_ses->sid_decrypt = -1; -+ cesa_ocf_cur_ses->frag_wa_encrypt = -1; -+ cesa_ocf_cur_ses->frag_wa_decrypt = -1; -+ cesa_ocf_cur_ses->frag_wa_auth = -1; -+ -+ /* init the session */ -+ memset(cesa_ses, 0, sizeof(MV_CESA_OPEN_SESSION)); -+ count = 1; -+ while (cri) { -+ if(count > 2) { -+ printk("%s,%d: don't support more then 2 operations\n", __FILE__, __LINE__); -+ goto error; -+ } -+ switch (cri->cri_alg) { -+ case CRYPTO_AES_CBC: -+ dprintk("%s,%d: (%d) AES CBC \n", __FILE__, __LINE__, count); -+ cesa_ocf_cur_ses->cipher_alg = cri->cri_alg; -+ cesa_ocf_cur_ses->ivlen = MV_CESA_AES_BLOCK_SIZE; -+ cesa_ses->cryptoAlgorithm = MV_CESA_CRYPTO_AES; -+ cesa_ses->cryptoMode = MV_CESA_CRYPTO_CBC; -+ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { -+ printk("%s,%d: CRYPTO key too long.\n", __FILE__, __LINE__); -+ goto error; -+ } -+ memcpy(cesa_ses->cryptoKey, cri->cri_key, cri->cri_klen/8); -+ dprintk("%s,%d: key length %d \n", __FILE__, __LINE__, cri->cri_klen/8); -+ cesa_ses->cryptoKeyLength = cri->cri_klen/8; -+ encrypt += count; -+ break; -+ case CRYPTO_3DES_CBC: -+ dprintk("%s,%d: (%d) 3DES CBC \n", __FILE__, __LINE__, count); -+ cesa_ocf_cur_ses->cipher_alg = cri->cri_alg; -+ cesa_ocf_cur_ses->ivlen = MV_CESA_3DES_BLOCK_SIZE; -+ cesa_ses->cryptoAlgorithm = MV_CESA_CRYPTO_3DES; -+ cesa_ses->cryptoMode = MV_CESA_CRYPTO_CBC; -+ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { -+ printk("%s,%d: CRYPTO key too long.\n", __FILE__, __LINE__); -+ goto error; -+ } -+ memcpy(cesa_ses->cryptoKey, cri->cri_key, cri->cri_klen/8); -+ cesa_ses->cryptoKeyLength = cri->cri_klen/8; -+ encrypt += count; -+ break; -+ case CRYPTO_DES_CBC: -+ dprintk("%s,%d: (%d) DES CBC \n", __FILE__, __LINE__, count); -+ cesa_ocf_cur_ses->cipher_alg = cri->cri_alg; -+ cesa_ocf_cur_ses->ivlen = MV_CESA_DES_BLOCK_SIZE; -+ cesa_ses->cryptoAlgorithm = MV_CESA_CRYPTO_DES; -+ cesa_ses->cryptoMode = MV_CESA_CRYPTO_CBC; -+ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { -+ printk("%s,%d: CRYPTO key too long.\n", __FILE__, __LINE__); -+ goto error; -+ } -+ memcpy(cesa_ses->cryptoKey, cri->cri_key, cri->cri_klen/8); -+ cesa_ses->cryptoKeyLength = cri->cri_klen/8; -+ encrypt += count; -+ break; -+ case CRYPTO_MD5: -+ case CRYPTO_MD5_HMAC: -+ dprintk("%s,%d: (%d) %sMD5 CBC \n", __FILE__, __LINE__, count, (cri->cri_alg != CRYPTO_MD5)? "H-":" "); -+ cesa_ocf_cur_ses->auth_alg = cri->cri_alg; -+ cesa_ocf_cur_ses->digestlen = (cri->cri_alg == CRYPTO_MD5)? MV_CESA_MD5_DIGEST_SIZE : 12; -+ cesa_ses->macMode = (cri->cri_alg == CRYPTO_MD5)? MV_CESA_MAC_MD5 : MV_CESA_MAC_HMAC_MD5; -+ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { -+ printk("%s,%d: MAC key too long. \n", __FILE__, __LINE__); -+ goto error; -+ } -+ cesa_ses->macKeyLength = cri->cri_klen/8; -+ memcpy(cesa_ses->macKey, cri->cri_key, cri->cri_klen/8); -+ cesa_ses->digestSize = cesa_ocf_cur_ses->digestlen; -+ auth += count; -+ break; -+ case CRYPTO_SHA1: -+ case CRYPTO_SHA1_HMAC: -+ dprintk("%s,%d: (%d) %sSHA1 CBC \n", __FILE__, __LINE__, count, (cri->cri_alg != CRYPTO_SHA1)? "H-":" "); -+ cesa_ocf_cur_ses->auth_alg = cri->cri_alg; -+ cesa_ocf_cur_ses->digestlen = (cri->cri_alg == CRYPTO_SHA1)? MV_CESA_SHA1_DIGEST_SIZE : 12; -+ cesa_ses->macMode = (cri->cri_alg == CRYPTO_SHA1)? MV_CESA_MAC_SHA1 : MV_CESA_MAC_HMAC_SHA1; -+ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { -+ printk("%s,%d: MAC key too long. \n", __FILE__, __LINE__); -+ goto error; -+ } -+ cesa_ses->macKeyLength = cri->cri_klen/8; -+ memcpy(cesa_ses->macKey, cri->cri_key, cri->cri_klen/8); -+ cesa_ses->digestSize = cesa_ocf_cur_ses->digestlen; -+ auth += count; -+ break; -+ default: -+ printk("%s,%d: unknown algo 0x%x\n", __FILE__, __LINE__, cri->cri_alg); -+ goto error; -+ } -+ cri = cri->cri_next; -+ count++; -+ } -+ -+ if((encrypt > 2) || (auth > 2)) { -+ printk("%s,%d: session mode is not supported.\n", __FILE__, __LINE__); -+ goto error; -+ } -+ /* create new sessions in HAL */ -+ if(encrypt) { -+ cesa_ses->operation = MV_CESA_CRYPTO_ONLY; -+ /* encrypt session */ -+ if(auth == 1) { -+ cesa_ses->operation = MV_CESA_MAC_THEN_CRYPTO; -+ } -+ else if(auth == 2) { -+ cesa_ses->operation = MV_CESA_CRYPTO_THEN_MAC; -+ cesa_ocf_cur_ses->encrypt_tn_auth = 1; -+ } -+ else { -+ cesa_ses->operation = MV_CESA_CRYPTO_ONLY; -+ } -+ cesa_ses->direction = MV_CESA_DIR_ENCODE; -+ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->sid_encrypt); -+ if(status != MV_OK) { -+ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); -+ goto error; -+ } -+ /* decrypt session */ -+ if( cesa_ses->operation == MV_CESA_MAC_THEN_CRYPTO ) { -+ cesa_ses->operation = MV_CESA_CRYPTO_THEN_MAC; -+ } -+ else if( cesa_ses->operation == MV_CESA_CRYPTO_THEN_MAC ) { -+ cesa_ses->operation = MV_CESA_MAC_THEN_CRYPTO; -+ } -+ cesa_ses->direction = MV_CESA_DIR_DECODE; -+ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->sid_decrypt); -+ if(status != MV_OK) { -+ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); -+ goto error; -+ } -+ -+ /* preapre one action sessions for case we will need to split an action */ -+#ifdef CESA_OCF_SPLIT -+ if(( cesa_ses->operation == MV_CESA_MAC_THEN_CRYPTO ) || -+ ( cesa_ses->operation == MV_CESA_CRYPTO_THEN_MAC )) { -+ /* open one session for encode and one for decode */ -+ cesa_ses->operation = MV_CESA_CRYPTO_ONLY; -+ cesa_ses->direction = MV_CESA_DIR_ENCODE; -+ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->frag_wa_encrypt); -+ if(status != MV_OK) { -+ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); -+ goto error; -+ } -+ -+ cesa_ses->direction = MV_CESA_DIR_DECODE; -+ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->frag_wa_decrypt); -+ if(status != MV_OK) { -+ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); -+ goto error; -+ } -+ /* open one session for auth */ -+ cesa_ses->operation = MV_CESA_MAC_ONLY; -+ cesa_ses->direction = MV_CESA_DIR_ENCODE; -+ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->frag_wa_auth); -+ if(status != MV_OK) { -+ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); -+ goto error; -+ } -+ } -+#endif -+ } -+ else { /* only auth */ -+ cesa_ses->operation = MV_CESA_MAC_ONLY; -+ cesa_ses->direction = MV_CESA_DIR_ENCODE; -+ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->sid_encrypt); -+ if(status != MV_OK) { -+ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); -+ goto error; -+ } -+ } -+ -+ return 0; -+error: -+ cesa_ocf_freesession(NULL, *sid); -+ return EINVAL; -+ -+} -+ -+ -+/* -+ * Free a session. -+ */ -+static int -+cesa_ocf_freesession(device_t dev, u_int64_t tid) -+{ -+ struct cesa_ocf_data *cesa_ocf_cur_ses; -+ u_int32_t sid = CRYPTO_SESID2LID(tid); -+ //unsigned long flags; -+ -+ dprintk("%s() %d \n", __FUNCTION__, sid); -+ if ( (sid >= CESA_OCF_MAX_SES) || (cesa_ocf_sessions[sid] == NULL) ) { -+ printk("%s,%d: EINVAL can't free session %d \n", __FILE__, __LINE__, sid); -+ return(EINVAL); -+ } -+ -+ /* Silently accept and return */ -+ if (sid == 0) -+ return(0); -+ -+ /* release session from HAL */ -+ cesa_ocf_cur_ses = cesa_ocf_sessions[sid]; -+ if (cesa_ocf_cur_ses->sid_encrypt != -1) { -+ mvCesaSessionClose(cesa_ocf_cur_ses->sid_encrypt); -+ } -+ if (cesa_ocf_cur_ses->sid_decrypt != -1) { -+ mvCesaSessionClose(cesa_ocf_cur_ses->sid_decrypt); -+ } -+ if (cesa_ocf_cur_ses->frag_wa_encrypt != -1) { -+ mvCesaSessionClose(cesa_ocf_cur_ses->frag_wa_encrypt); -+ } -+ if (cesa_ocf_cur_ses->frag_wa_decrypt != -1) { -+ mvCesaSessionClose(cesa_ocf_cur_ses->frag_wa_decrypt); -+ } -+ if (cesa_ocf_cur_ses->frag_wa_auth != -1) { -+ mvCesaSessionClose(cesa_ocf_cur_ses->frag_wa_auth); -+ } -+ -+ kfree(cesa_ocf_cur_ses); -+ cesa_ocf_sessions[sid] = NULL; -+ -+ return 0; -+} -+ -+ -+/* TDMA Window setup */ -+ -+static void __init -+setup_tdma_mbus_windows(struct cesa_dev *dev) -+{ -+ int i; -+ -+ for (i = 0; i < 4; i++) { -+ writel(0, dev->reg + WINDOW_BASE(i)); -+ writel(0, dev->reg + WINDOW_CTRL(i)); -+ } -+ -+ for (i = 0; i < dev->plat_data->dram->num_cs; i++) { -+ struct mbus_dram_window *cs = dev->plat_data->dram->cs + i; -+ writel( -+ ((cs->size - 1) & 0xffff0000) | -+ (cs->mbus_attr << 8) | -+ (dev->plat_data->dram->mbus_dram_target_id << 4) | 1, -+ dev->reg + WINDOW_CTRL(i) -+ ); -+ writel(cs->base, dev->reg + WINDOW_BASE(i)); -+ } -+} -+ -+/* -+ * our driver startup and shutdown routines -+ */ -+static int -+mv_cesa_ocf_init(struct platform_device *pdev) -+{ -+#if defined(CONFIG_MV78200) || defined(CONFIG_MV632X) -+ if (MV_FALSE == mvSocUnitIsMappedToThisCpu(CESA)) -+ { -+ dprintk("CESA is not mapped to this CPU\n"); -+ return -ENODEV; -+ } -+#endif -+ -+ dprintk("%s\n", __FUNCTION__); -+ memset(&mv_cesa_dev, 0, sizeof(mv_cesa_dev)); -+ softc_device_init(&mv_cesa_dev, "MV CESA", 0, mv_cesa_methods); -+ cesa_ocf_id = crypto_get_driverid(softc_get_device(&mv_cesa_dev),CRYPTOCAP_F_HARDWARE); -+ -+ if (cesa_ocf_id < 0) -+ panic("MV CESA crypto device cannot initialize!"); -+ -+ dprintk("%s,%d: cesa ocf device id is %d \n", __FILE__, __LINE__, cesa_ocf_id); -+ -+ /* CESA unit is auto power on off */ -+#if 0 -+ if (MV_FALSE == mvCtrlPwrClckGet(CESA_UNIT_ID,0)) -+ { -+ printk("\nWarning CESA %d is Powered Off\n",0); -+ return EINVAL; -+ } -+#endif -+ -+ memset(&cesa_device, 0, sizeof(struct cesa_dev)); -+ /* Get the IRQ, and crypto memory regions */ -+ { -+ struct resource *res; -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram"); -+ -+ if (!res) -+ return -ENXIO; -+ -+ cesa_device.sram = ioremap(res->start, res->end - res->start + 1); -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); -+ -+ if (!res) { -+ iounmap(cesa_device.sram); -+ return -ENXIO; -+ } -+ cesa_device.reg = ioremap(res->start, res->end - res->start + 1); -+ cesa_device.irq = platform_get_irq(pdev, 0); -+ cesa_device.plat_data = pdev->dev.platform_data; -+ setup_tdma_mbus_windows(&cesa_device); -+ -+ } -+ -+ -+ if( MV_OK != mvCesaInit(CESA_OCF_MAX_SES*5, CESA_Q_SIZE, cesa_device.reg, -+ NULL) ) { -+ printk("%s,%d: mvCesaInit Failed. \n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ /* clear and unmask Int */ -+ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); -+#ifndef CESA_OCF_POLLING -+ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, MV_CESA_CAUSE_ACC_DMA_MASK); -+#endif -+#ifdef CESA_OCF_TASKLET -+ tasklet_init(&cesa_ocf_tasklet, cesa_callback, (unsigned int) 0); -+#endif -+ /* register interrupt */ -+ if( request_irq( cesa_device.irq, cesa_interrupt_handler, -+ (IRQF_DISABLED) , "cesa", &cesa_ocf_id) < 0) { -+ printk("%s,%d: cannot assign irq %x\n", __FILE__, __LINE__, cesa_device.reg); -+ return EINVAL; -+ } -+ -+ -+ memset(cesa_ocf_sessions, 0, sizeof(struct cesa_ocf_data *) * CESA_OCF_MAX_SES); -+ -+#define REGISTER(alg) \ -+ crypto_register(cesa_ocf_id, alg, 0,0) -+ REGISTER(CRYPTO_AES_CBC); -+ REGISTER(CRYPTO_DES_CBC); -+ REGISTER(CRYPTO_3DES_CBC); -+ REGISTER(CRYPTO_MD5); -+ REGISTER(CRYPTO_MD5_HMAC); -+ REGISTER(CRYPTO_SHA1); -+ REGISTER(CRYPTO_SHA1_HMAC); -+#undef REGISTER -+ -+ return 0; -+} -+ -+static void -+mv_cesa_ocf_exit(struct platform_device *pdev) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ crypto_unregister_all(cesa_ocf_id); -+ cesa_ocf_id = -1; -+ iounmap(cesa_device.reg); -+ iounmap(cesa_device.sram); -+ free_irq(cesa_device.irq, NULL); -+ -+ /* mask and clear Int */ -+ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, 0); -+ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); -+ -+ -+ if( MV_OK != mvCesaFinish() ) { -+ printk("%s,%d: mvCesaFinish Failed. \n", __FILE__, __LINE__); -+ return; -+ } -+} -+ -+ -+void cesa_ocf_debug(void) -+{ -+ -+#ifdef CESA_OCF_TRACE_DEBUG -+ { -+ int i, j; -+ j = cesaTestTraceIdx; -+ mvOsPrintf("No Type rCause iCause Proc Isr Res Time pReady pProc pEmpty\n"); -+ for(i=0; i= _1G) -+ { -+ mvOsOutput("%3dGB ", size / _1G); -+ size %= _1G; -+ if(size) -+ mvOsOutput("+"); -+ } -+ if(size >= _1M ) -+ { -+ mvOsOutput("%3dMB ", size / _1M); -+ size %= _1M; -+ if(size) -+ mvOsOutput("+"); -+ } -+ if(size >= _1K) -+ { -+ mvOsOutput("%3dKB ", size / _1K); -+ size %= _1K; -+ if(size) -+ mvOsOutput("+"); -+ } -+ if(size > 0) -+ { -+ mvOsOutput("%3dB ", size); -+ } -+} -+ -+/******************************************************************************* -+* mvHexToBin - Convert hex to binary -+* -+* DESCRIPTION: -+* This function Convert hex to binary. -+* -+* INPUT: -+* pHexStr - hex buffer pointer. -+* size - Size to convert. -+* -+* OUTPUT: -+* pBin - Binary buffer pointer. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvHexToBin(const char* pHexStr, MV_U8* pBin, int size) -+{ -+ int j, i; -+ char tmp[3]; -+ MV_U8 byte; -+ -+ for(j=0, i=0; j> 1; -+ result++; -+ } -+ return result; -+} -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvCommon.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvCommon.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvCommon.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvCommon.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,308 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+ -+#ifndef __INCmvCommonh -+#define __INCmvCommonh -+ -+#include "mvTypes.h" -+ -+/* Swap tool */ -+ -+/* 16bit nibble swap. For example 0x1234 -> 0x2143 */ -+#define MV_NIBBLE_SWAP_16BIT(X) (((X&0xf) << 4) | \ -+ ((X&0xf0) >> 4) | \ -+ ((X&0xf00) << 4) | \ -+ ((X&0xf000) >> 4)) -+ -+/* 32bit nibble swap. For example 0x12345678 -> 0x21436587 */ -+#define MV_NIBBLE_SWAP_32BIT(X) (((X&0xf) << 4) | \ -+ ((X&0xf0) >> 4) | \ -+ ((X&0xf00) << 4) | \ -+ ((X&0xf000) >> 4) | \ -+ ((X&0xf0000) << 4) | \ -+ ((X&0xf00000) >> 4) | \ -+ ((X&0xf000000) << 4) | \ -+ ((X&0xf0000000) >> 4)) -+ -+/* 16bit byte swap. For example 0x1122 -> 0x2211 */ -+#define MV_BYTE_SWAP_16BIT(X) ((((X)&0xff)<<8) | (((X)&0xff00)>>8)) -+ -+/* 32bit byte swap. For example 0x11223344 -> 0x44332211 */ -+#define MV_BYTE_SWAP_32BIT(X) ((((X)&0xff)<<24) | \ -+ (((X)&0xff00)<<8) | \ -+ (((X)&0xff0000)>>8) | \ -+ (((X)&0xff000000)>>24)) -+ -+/* 64bit byte swap. For example 0x11223344.55667788 -> 0x88776655.44332211 */ -+#define MV_BYTE_SWAP_64BIT(X) ((l64) ((((X)&0xffULL)<<56) | \ -+ (((X)&0xff00ULL)<<40) | \ -+ (((X)&0xff0000ULL)<<24) | \ -+ (((X)&0xff000000ULL)<<8) | \ -+ (((X)&0xff00000000ULL)>>8) | \ -+ (((X)&0xff0000000000ULL)>>24) | \ -+ (((X)&0xff000000000000ULL)>>40) | \ -+ (((X)&0xff00000000000000ULL)>>56))) -+ -+/* Endianess macros. */ -+#if defined(MV_CPU_LE) -+ #define MV_16BIT_LE(X) (X) -+ #define MV_32BIT_LE(X) (X) -+ #define MV_64BIT_LE(X) (X) -+ #define MV_16BIT_BE(X) MV_BYTE_SWAP_16BIT(X) -+ #define MV_32BIT_BE(X) MV_BYTE_SWAP_32BIT(X) -+ #define MV_64BIT_BE(X) MV_BYTE_SWAP_64BIT(X) -+#elif defined(MV_CPU_BE) -+ #define MV_16BIT_LE(X) MV_BYTE_SWAP_16BIT(X) -+ #define MV_32BIT_LE(X) MV_BYTE_SWAP_32BIT(X) -+ #define MV_64BIT_LE(X) MV_BYTE_SWAP_64BIT(X) -+ #define MV_16BIT_BE(X) (X) -+ #define MV_32BIT_BE(X) (X) -+ #define MV_64BIT_BE(X) (X) -+#else -+ #error "CPU endianess isn't defined!\n" -+#endif -+ -+ -+/* Bit field definitions */ -+#define NO_BIT 0x00000000 -+#define BIT0 0x00000001 -+#define BIT1 0x00000002 -+#define BIT2 0x00000004 -+#define BIT3 0x00000008 -+#define BIT4 0x00000010 -+#define BIT5 0x00000020 -+#define BIT6 0x00000040 -+#define BIT7 0x00000080 -+#define BIT8 0x00000100 -+#define BIT9 0x00000200 -+#define BIT10 0x00000400 -+#define BIT11 0x00000800 -+#define BIT12 0x00001000 -+#define BIT13 0x00002000 -+#define BIT14 0x00004000 -+#define BIT15 0x00008000 -+#define BIT16 0x00010000 -+#define BIT17 0x00020000 -+#define BIT18 0x00040000 -+#define BIT19 0x00080000 -+#define BIT20 0x00100000 -+#define BIT21 0x00200000 -+#define BIT22 0x00400000 -+#define BIT23 0x00800000 -+#define BIT24 0x01000000 -+#define BIT25 0x02000000 -+#define BIT26 0x04000000 -+#define BIT27 0x08000000 -+#define BIT28 0x10000000 -+#define BIT29 0x20000000 -+#define BIT30 0x40000000 -+#define BIT31 0x80000000 -+ -+/* Handy sizes */ -+#define _1K 0x00000400 -+#define _2K 0x00000800 -+#define _4K 0x00001000 -+#define _8K 0x00002000 -+#define _16K 0x00004000 -+#define _32K 0x00008000 -+#define _64K 0x00010000 -+#define _128K 0x00020000 -+#define _256K 0x00040000 -+#define _512K 0x00080000 -+ -+#define _1M 0x00100000 -+#define _2M 0x00200000 -+#define _4M 0x00400000 -+#define _8M 0x00800000 -+#define _16M 0x01000000 -+#define _32M 0x02000000 -+#define _64M 0x04000000 -+#define _128M 0x08000000 -+#define _256M 0x10000000 -+#define _512M 0x20000000 -+ -+#define _1G 0x40000000 -+#define _2G 0x80000000 -+ -+/* Tclock and Sys clock define */ -+#define _100MHz 100000000 -+#define _125MHz 125000000 -+#define _133MHz 133333334 -+#define _150MHz 150000000 -+#define _160MHz 160000000 -+#define _166MHz 166666667 -+#define _175MHz 175000000 -+#define _178MHz 178000000 -+#define _183MHz 183333334 -+#define _187MHz 187000000 -+#define _192MHz 192000000 -+#define _194MHz 194000000 -+#define _200MHz 200000000 -+#define _233MHz 233333334 -+#define _250MHz 250000000 -+#define _266MHz 266666667 -+#define _300MHz 300000000 -+ -+/* For better address window table readability */ -+#define EN MV_TRUE -+#define DIS MV_FALSE -+#define N_A -1 /* Not applicable */ -+ -+/* Cache configuration options for memory (DRAM, SRAM, ... ) */ -+ -+/* Memory uncached, HW or SW cache coherency is not needed */ -+#define MV_UNCACHED 0 -+/* Memory cached, HW cache coherency supported in WriteThrough mode */ -+#define MV_CACHE_COHER_HW_WT 1 -+/* Memory cached, HW cache coherency supported in WriteBack mode */ -+#define MV_CACHE_COHER_HW_WB 2 -+/* Memory cached, No HW cache coherency, Cache coherency must be in SW */ -+#define MV_CACHE_COHER_SW 3 -+ -+ -+/* Macro for testing aligment. Positive if number is NOT aligned */ -+#define MV_IS_NOT_ALIGN(number, align) ((number) & ((align) - 1)) -+ -+/* Macro for alignment up. For example, MV_ALIGN_UP(0x0330, 0x20) = 0x0340 */ -+#define MV_ALIGN_UP(number, align) \ -+(((number) & ((align) - 1)) ? (((number) + (align)) & ~((align)-1)) : (number)) -+ -+/* Macro for alignment down. For example, MV_ALIGN_UP(0x0330, 0x20) = 0x0320 */ -+#define MV_ALIGN_DOWN(number, align) ((number) & ~((align)-1)) -+ -+/* This macro returns absolute value */ -+#define MV_ABS(number) (((int)(number) < 0) ? -(int)(number) : (int)(number)) -+ -+ -+/* Bit fields manipulation macros */ -+ -+/* An integer word which its 'x' bit is set */ -+#define MV_BIT_MASK(bitNum) (1 << (bitNum) ) -+ -+/* Checks wheter bit 'x' in integer word is set */ -+#define MV_BIT_CHECK(word, bitNum) ( (word) & MV_BIT_MASK(bitNum) ) -+ -+/* Clear (reset) bit 'x' in integer word (RMW - Read-Modify-Write) */ -+#define MV_BIT_CLEAR(word, bitNum) ( (word) &= ~(MV_BIT_MASK(bitNum)) ) -+ -+/* Set bit 'x' in integer word (RMW) */ -+#define MV_BIT_SET(word, bitNum) ( (word) |= MV_BIT_MASK(bitNum) ) -+ -+/* Invert bit 'x' in integer word (RMW) */ -+#define MV_BIT_INV(word, bitNum) ( (word) ^= MV_BIT_MASK(bitNum) ) -+ -+/* Get the min between 'a' or 'b' */ -+#define MV_MIN(a,b) (((a) < (b)) ? (a) : (b)) -+ -+/* Get the max between 'a' or 'b' */ -+#define MV_MAX(a,b) (((a) < (b)) ? (b) : (a)) -+ -+/* Temporary */ -+#define mvOsDivide(num, div) \ -+({ \ -+ int i=0, rem=(num); \ -+ \ -+ while(rem >= (div)) \ -+ { \ -+ rem -= (div); \ -+ i++; \ -+ } \ -+ (i); \ -+}) -+ -+/* Temporary */ -+#define mvOsReminder(num, div) \ -+({ \ -+ int rem = (num); \ -+ \ -+ while(rem >= (div)) \ -+ rem -= (div); \ -+ (rem); \ -+}) -+ -+#define MV_IP_QUAD(ipAddr) ((ipAddr >> 24) & 0xFF), ((ipAddr >> 16) & 0xFF), \ -+ ((ipAddr >> 8) & 0xFF), ((ipAddr >> 0) & 0xFF) -+ -+#define MV_IS_POWER_OF_2(num) ((num != 0) && ((num & (num - 1)) == 0)) -+ -+#ifndef MV_ASMLANGUAGE -+/* mvCommon API list */ -+ -+MV_VOID mvHexToBin(const char* pHexStr, MV_U8* pBin, int size); -+void mvAsciiToHex(const char* asciiStr, char* hexStr); -+void mvBinToHex(const MV_U8* bin, char* hexStr, int size); -+void mvBinToAscii(const MV_U8* bin, char* asciiStr, int size); -+ -+MV_STATUS mvMacStrToHex(const char* macStr, MV_U8* macHex); -+MV_STATUS mvMacHexToStr(MV_U8* macHex, char* macStr); -+void mvSizePrint(MV_U32); -+ -+MV_U32 mvLog2(MV_U32 num); -+ -+#endif /* MV_ASMLANGUAGE */ -+ -+ -+#endif /* __INCmvCommonh */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvCompVer.txt linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvCompVer.txt ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvCompVer.txt 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvCompVer.txt 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,4 @@ -+Global HAL Version: FEROCEON_HAL_3_1_7 -+Unit HAL Version: 3.1.4 -+Description: This component includes an implementation of the unit HAL drivers -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvDebug.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvDebug.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvDebug.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvDebug.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,326 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+ -+/* includes */ -+#include "mvOs.h" -+#include "mv802_3.h" -+#include "mvCommon.h" -+#include "mvDebug.h" -+ -+/* Global variables effect on behave MV_DEBUG_PRINT and MV_DEBUG_CODE macros -+ * mvDebug - map of bits (one for each module) bit=1 means enable -+ * debug code and messages for this module -+ * mvModuleDebug - array of 32 bits varables one for each module -+ */ -+MV_U32 mvDebug = 0; -+MV_U32 mvDebugModules[MV_MODULE_MAX]; -+ -+/* Init mvModuleDebug array to default values */ -+void mvDebugInit(void) -+{ -+ int bit; -+ -+ mvDebug = 0; -+ for(bit=0; bit 0) -+ { -+ mvOsPrintf("%08x: ", memAddr); -+ i = 0; -+ /* 32 bytes in the line */ -+ while(i < 32) -+ { -+ if(memAddr >= (MV_U32)addr) -+ { -+ switch(access) -+ { -+ case 1: -+ if( memAddr == CPU_PHY_MEM(memAddr) ) -+ { -+ mvOsPrintf("%02x ", MV_MEMIO8_READ(memAddr)); -+ } -+ else -+ { -+ mvOsPrintf("%02x ", *((MV_U8*)memAddr)); -+ } -+ break; -+ -+ case 2: -+ if( memAddr == CPU_PHY_MEM(memAddr) ) -+ { -+ mvOsPrintf("%04x ", MV_MEMIO16_READ(memAddr)); -+ } -+ else -+ { -+ mvOsPrintf("%04x ", *((MV_U16*)memAddr)); -+ } -+ break; -+ -+ case 4: -+ if( memAddr == CPU_PHY_MEM(memAddr) ) -+ { -+ mvOsPrintf("%08x ", MV_MEMIO32_READ(memAddr)); -+ } -+ else -+ { -+ mvOsPrintf("%08x ", *((MV_U32*)memAddr)); -+ } -+ break; -+ } -+ } -+ else -+ { -+ for(j=0; j<(access*2+1); j++) -+ mvOsPrintf(" "); -+ } -+ i += access; -+ memAddr += access; -+ size -= access; -+ if(size <= 0) -+ break; -+ } -+ mvOsPrintf("\n"); -+ } -+} -+ -+void mvDebugPrintBufInfo(BUF_INFO* pBufInfo, int size, int access) -+{ -+ if(pBufInfo == NULL) -+ { -+ mvOsPrintf("\n!!! pBufInfo = NULL\n"); -+ return; -+ } -+ mvOsPrintf("\n*** pBufInfo=0x%x, cmdSts=0x%08x, pBuf=0x%x, bufSize=%d\n", -+ (unsigned int)pBufInfo, -+ (unsigned int)pBufInfo->cmdSts, -+ (unsigned int)pBufInfo->pBuff, -+ (unsigned int)pBufInfo->bufSize); -+ mvOsPrintf("pData=0x%x, byteCnt=%d, pNext=0x%x, uInfo1=0x%x, uInfo2=0x%x\n", -+ (unsigned int)pBufInfo->pData, -+ (unsigned int)pBufInfo->byteCnt, -+ (unsigned int)pBufInfo->pNextBufInfo, -+ (unsigned int)pBufInfo->userInfo1, -+ (unsigned int)pBufInfo->userInfo2); -+ if(pBufInfo->pData != NULL) -+ { -+ if(size > pBufInfo->byteCnt) -+ size = pBufInfo->byteCnt; -+ mvDebugMemDump(pBufInfo->pData, size, access); -+ } -+} -+ -+void mvDebugPrintPktInfo(MV_PKT_INFO* pPktInfo, int size, int access) -+{ -+ int frag, len; -+ -+ if(pPktInfo == NULL) -+ { -+ mvOsPrintf("\n!!! pPktInfo = NULL\n"); -+ return; -+ } -+ mvOsPrintf("\npPkt=%p, stat=0x%08x, numFr=%d, size=%d, pFr=%p, osInfo=0x%lx\n", -+ pPktInfo, pPktInfo->status, pPktInfo->numFrags, pPktInfo->pktSize, -+ pPktInfo->pFrags, pPktInfo->osInfo); -+ -+ for(frag=0; fragnumFrags; frag++) -+ { -+ mvOsPrintf("#%2d. bufVirt=%p, bufSize=%d\n", -+ frag, pPktInfo->pFrags[frag].bufVirtPtr, -+ pPktInfo->pFrags[frag].bufSize); -+ if(size > 0) -+ { -+ len = MV_MIN((int)pPktInfo->pFrags[frag].bufSize, size); -+ mvDebugMemDump(pPktInfo->pFrags[frag].bufVirtPtr, len, access); -+ size -= len; -+ } -+ } -+ -+} -+ -+void mvDebugPrintIpAddr(MV_U32 ipAddr) -+{ -+ mvOsPrintf("%d.%d.%d.%d", ((ipAddr >> 24) & 0xFF), ((ipAddr >> 16) & 0xFF), -+ ((ipAddr >> 8) & 0xFF), ((ipAddr >> 0) & 0xFF)); -+} -+ -+void mvDebugPrintMacAddr(const MV_U8* pMacAddr) -+{ -+ int i; -+ -+ mvOsPrintf("%02x", (unsigned int)pMacAddr[0]); -+ for(i=1; ibegin = 0; -+ pTimeEntry->count = count; -+ pTimeEntry->end = 0; -+ pTimeEntry->left = pTimeEntry->count; -+ pTimeEntry->total = 0; -+ pTimeEntry->min = 0xFFFFFFFF; -+ pTimeEntry->max = 0x0; -+ strncpy(pTimeEntry->name, pName, sizeof(pTimeEntry->name)-1); -+ pTimeEntry->name[sizeof(pTimeEntry->name)-1] = '\0'; -+} -+ -+/* Print out MV_DEBUG_TIMES entry */ -+void mvDebugPrintTimeEntry(MV_DEBUG_TIMES* pTimeEntry, MV_BOOL isTitle) -+{ -+ int num; -+ -+ if(isTitle == MV_TRUE) -+ mvOsPrintf("Event NumOfEvents TotalTime Average Min Max\n"); -+ -+ num = pTimeEntry->count-pTimeEntry->left; -+ if(num > 0) -+ { -+ mvOsPrintf("%-11s %6u 0x%08lx %6lu %6lu %6lu\n", -+ pTimeEntry->name, num, pTimeEntry->total, pTimeEntry->total/num, -+ pTimeEntry->min, pTimeEntry->max); -+ } -+} -+ -+/* Update MV_DEBUG_TIMES entry */ -+void mvDebugUpdateTimeEntry(MV_DEBUG_TIMES* pTimeEntry) -+{ -+ MV_U32 delta; -+ -+ if(pTimeEntry->left > 0) -+ { -+ if(pTimeEntry->end <= pTimeEntry->begin) -+ { -+ delta = pTimeEntry->begin - pTimeEntry->end; -+ } -+ else -+ { -+ delta = ((MV_U32)0x10000 - pTimeEntry->end) + pTimeEntry->begin; -+ } -+ pTimeEntry->total += delta; -+ -+ if(delta < pTimeEntry->min) -+ pTimeEntry->min = delta; -+ -+ if(delta > pTimeEntry->max) -+ pTimeEntry->max = delta; -+ -+ pTimeEntry->left--; -+ } -+} -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvDebug.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvDebug.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvDebug.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvDebug.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,178 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+ -+#ifndef __INCmvDebugh -+#define __INCmvDebugh -+ -+/* includes */ -+#include "mvTypes.h" -+ -+typedef enum -+{ -+ MV_MODULE_INVALID = -1, -+ MV_MODULE_ETH = 0, -+ MV_MODULE_IDMA, -+ MV_MODULE_XOR, -+ MV_MODULE_TWASI, -+ MV_MODULE_MGI, -+ MV_MODULE_USB, -+ MV_MODULE_CESA, -+ -+ MV_MODULE_MAX -+}MV_MODULE_ID; -+ -+/* Define generic flags useful for most of modules */ -+#define MV_DEBUG_FLAG_ALL (0) -+#define MV_DEBUG_FLAG_INIT (1 << 0) -+#define MV_DEBUG_FLAG_RX (1 << 1) -+#define MV_DEBUG_FLAG_TX (1 << 2) -+#define MV_DEBUG_FLAG_ERR (1 << 3) -+#define MV_DEBUG_FLAG_TRACE (1 << 4) -+#define MV_DEBUG_FLAG_DUMP (1 << 5) -+#define MV_DEBUG_FLAG_CACHE (1 << 6) -+#define MV_DEBUG_FLAG_IOCTL (1 << 7) -+#define MV_DEBUG_FLAG_STATS (1 << 8) -+ -+extern MV_U32 mvDebug; -+extern MV_U32 mvDebugModules[MV_MODULE_MAX]; -+ -+#ifdef MV_DEBUG -+# define MV_DEBUG_PRINT(module, flags, msg) mvOsPrintf msg -+# define MV_DEBUG_CODE(module, flags, code) code -+#elif defined(MV_RT_DEBUG) -+# define MV_DEBUG_PRINT(module, flags, msg) \ -+ if( (mvDebug & (1<<(module))) && \ -+ ((mvDebugModules[(module)] & (flags)) == (flags)) ) \ -+ mvOsPrintf msg -+# define MV_DEBUG_CODE(module, flags, code) \ -+ if( (mvDebug & (1<<(module))) && \ -+ ((mvDebugModules[(module)] & (flags)) == (flags)) ) \ -+ code -+#else -+# define MV_DEBUG_PRINT(module, flags, msg) -+# define MV_DEBUG_CODE(module, flags, code) -+#endif -+ -+ -+ -+/* typedefs */ -+ -+/* time measurement structure used to check how much time pass between -+ * two points -+ */ -+typedef struct { -+ char name[20]; /* name of the entry */ -+ unsigned long begin; /* time measured on begin point */ -+ unsigned long end; /* time measured on end point */ -+ unsigned long total; /* Accumulated time */ -+ unsigned long left; /* The rest measurement actions */ -+ unsigned long count; /* Maximum measurement actions */ -+ unsigned long min; /* Minimum time from begin to end */ -+ unsigned long max; /* Maximum time from begin to end */ -+} MV_DEBUG_TIMES; -+ -+ -+/* mvDebug.h API list */ -+ -+/****** Error Recording ******/ -+ -+/* Dump memory in specific format: -+ * address: X1X1X1X1 X2X2X2X2 ... X8X8X8X8 -+ */ -+void mvDebugMemDump(void* addr, int size, int access); -+ -+void mvDebugPrintBufInfo(BUF_INFO* pBufInfo, int size, int access); -+ -+void mvDebugPrintPktInfo(MV_PKT_INFO* pPktInfo, int size, int access); -+ -+void mvDebugPrintIpAddr(MV_U32 ipAddr); -+ -+void mvDebugPrintMacAddr(const MV_U8* pMacAddr); -+ -+/**** There are three functions deals with MV_DEBUG_TIMES structure ****/ -+ -+/* Reset MV_DEBUG_TIMES entry */ -+void mvDebugResetTimeEntry(MV_DEBUG_TIMES* pTimeEntry, int count, char* name); -+ -+/* Update MV_DEBUG_TIMES entry */ -+void mvDebugUpdateTimeEntry(MV_DEBUG_TIMES* pTimeEntry); -+ -+/* Print out MV_DEBUG_TIMES entry */ -+void mvDebugPrintTimeEntry(MV_DEBUG_TIMES* pTimeEntry, MV_BOOL isTitle); -+ -+ -+/******** General ***********/ -+ -+/* Change value of mvDebugPrint global variable */ -+ -+void mvDebugInit(void); -+void mvDebugModuleEnable(MV_MODULE_ID module, MV_BOOL isEnable); -+void mvDebugModuleSetFlags(MV_MODULE_ID module, MV_U32 flags); -+void mvDebugModuleClearFlags(MV_MODULE_ID module, MV_U32 flags); -+ -+ -+#endif /* __INCmvDebug.h */ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,225 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvDeviceIdh -+#define __INCmvDeviceIdh -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* defines */ -+#define MARVELL_VEN_ID 0x11ab -+ -+/* Disco-3 */ -+#define MV64460_DEV_ID 0x6480 -+#define MV64460B_DEV_ID 0x6485 -+#define MV64430_DEV_ID 0x6420 -+ -+/* Disco-5 */ -+#define MV64560_DEV_ID 0x6450 -+ -+/* Disco-6 */ -+#define MV64660_DEV_ID 0x6460 -+ -+/* Orion */ -+#define MV_1181_DEV_ID 0x1181 -+#define MV_5181_DEV_ID 0x5181 -+#define MV_5281_DEV_ID 0x5281 -+#define MV_5182_DEV_ID 0x5182 -+#define MV_8660_DEV_ID 0x8660 -+#define MV_5180_DEV_ID 0x5180 -+#define MV_5082_DEV_ID 0x5082 -+#define MV_1281_DEV_ID 0x1281 -+#define MV_6082_DEV_ID 0x6082 -+#define MV_6183_DEV_ID 0x6183 -+#define MV_6183L_DEV_ID 0x6083 -+ -+#define MV_5281_D0_REV 0x4 -+#define MV_5281_D0_ID ((MV_5281_DEV_ID << 16) | MV_5281_D0_REV) -+#define MV_5281_D0_NAME "88F5281 D0" -+ -+#define MV_5281_D1_REV 0x5 -+#define MV_5281_D1_ID ((MV_5281_DEV_ID << 16) | MV_5281_D1_REV) -+#define MV_5281_D1_NAME "88F5281 D1" -+ -+#define MV_5281_D2_REV 0x6 -+#define MV_5281_D2_ID ((MV_5281_DEV_ID << 16) | MV_5281_D2_REV) -+#define MV_5281_D2_NAME "88F5281 D2" -+ -+ -+#define MV_5181L_A0_REV 0x8 /* need for PCIE Er */ -+#define MV_5181_A1_REV 0x1 /* for USB Er ..*/ -+#define MV_5181_B0_REV 0x2 -+#define MV_5181_B1_REV 0x3 -+#define MV_5182_A1_REV 0x1 -+#define MV_5180N_B1_REV 0x3 -+#define MV_5181L_A0_ID ((MV_5181_DEV_ID << 16) | MV_5181L_A0_REV) -+ -+ -+ -+/* kw */ -+#define MV_6281_DEV_ID 0x6281 -+#define MV_6192_DEV_ID 0x6192 -+#define MV_6190_DEV_ID 0x6190 -+#define MV_6180_DEV_ID 0x6180 -+ -+#define MV_6281_A0_REV 0x2 -+#define MV_6281_A0_ID ((MV_6281_DEV_ID << 16) | MV_6281_A0_REV) -+#define MV_6281_A0_NAME "88F6281 A0" -+ -+#define MV_6192_A0_REV 0x2 -+#define MV_6192_A0_ID ((MV_6192_DEV_ID << 16) | MV_6192_A0_REV) -+#define MV_6192_A0_NAME "88F6192 A0" -+ -+#define MV_6190_A0_REV 0x2 -+#define MV_6190_A0_ID ((MV_6190_DEV_ID << 16) | MV_6190_A0_REV) -+#define MV_6190_A0_NAME "88F6190 A0" -+ -+#define MV_6180_A0_REV 0x2 -+#define MV_6180_A0_ID ((MV_6180_DEV_ID << 16) | MV_6180_A0_REV) -+#define MV_6180_A0_NAME "88F6180 A0" -+ -+#define MV_6281_A1_REV 0x3 -+#define MV_6281_A1_ID ((MV_6281_DEV_ID << 16) | MV_6281_A1_REV) -+#define MV_6281_A1_NAME "88F6281 A1" -+ -+#define MV_6192_A1_REV 0x3 -+#define MV_6192_A1_ID ((MV_6192_DEV_ID << 16) | MV_6192_A1_REV) -+#define MV_6192_A1_NAME "88F6192 A1" -+ -+#define MV_6190_A1_REV 0x3 -+#define MV_6190_A1_ID ((MV_6190_DEV_ID << 16) | MV_6190_A1_REV) -+#define MV_6190_A1_NAME "88F6190 A1" -+ -+#define MV_6180_A1_REV 0x3 -+#define MV_6180_A1_ID ((MV_6180_DEV_ID << 16) | MV_6180_A1_REV) -+#define MV_6180_A1_NAME "88F6180 A1" -+ -+#define MV_88F6XXX_A0_REV 0x2 -+#define MV_88F6XXX_A1_REV 0x3 -+/* Disco-Duo */ -+#define MV_78XX0_ZY_DEV_ID 0x6381 -+#define MV_78XX0_ZY_NAME "MV78X00" -+ -+#define MV_78XX0_Z0_REV 0x1 -+#define MV_78XX0_Z0_ID ((MV_78XX0_ZY_DEV_ID << 16) | MV_78XX0_Z0_REV) -+#define MV_78XX0_Z0_NAME "78X00 Z0" -+ -+#define MV_78XX0_Y0_REV 0x2 -+#define MV_78XX0_Y0_ID ((MV_78XX0_ZY_DEV_ID << 16) | MV_78XX0_Y0_REV) -+#define MV_78XX0_Y0_NAME "78X00 Y0" -+ -+#define MV_78XX0_DEV_ID 0x7800 -+#define MV_78XX0_NAME "MV78X00" -+ -+#define MV_76100_DEV_ID 0x7610 -+#define MV_78200_DEV_ID 0x7820 -+#define MV_78100_DEV_ID 0x7810 -+#define MV_78XX0_A0_REV 0x1 -+#define MV_78XX0_A1_REV 0x2 -+ -+#define MV_76100_NAME "MV76100" -+#define MV_78100_NAME "MV78100" -+#define MV_78200_NAME "MV78200" -+ -+#define MV_76100_A0_ID ((MV_76100_DEV_ID << 16) | MV_78XX0_A0_REV) -+#define MV_78100_A0_ID ((MV_78100_DEV_ID << 16) | MV_78XX0_A0_REV) -+#define MV_78200_A0_ID ((MV_78200_DEV_ID << 16) | MV_78XX0_A0_REV) -+ -+#define MV_76100_A1_ID ((MV_76100_DEV_ID << 16) | MV_78XX0_A1_REV) -+#define MV_78100_A1_ID ((MV_78100_DEV_ID << 16) | MV_78XX0_A1_REV) -+#define MV_78200_A1_ID ((MV_78200_DEV_ID << 16) | MV_78XX0_A1_REV) -+ -+#define MV_76100_A0_NAME "MV76100 A0" -+#define MV_78100_A0_NAME "MV78100 A0" -+#define MV_78200_A0_NAME "MV78200 A0" -+#define MV_78XX0_A0_NAME "MV78XX0 A0" -+ -+#define MV_76100_A1_NAME "MV76100 A1" -+#define MV_78100_A1_NAME "MV78100 A1" -+#define MV_78200_A1_NAME "MV78200 A1" -+#define MV_78XX0_A1_NAME "MV78XX0 A1" -+ -+/*MV88F632X family*/ -+#define MV_6321_DEV_ID 0x6321 -+#define MV_6322_DEV_ID 0x6322 -+#define MV_6323_DEV_ID 0x6323 -+ -+#define MV_6321_NAME "88F6321" -+#define MV_6322_NAME "88F6322" -+#define MV_6323_NAME "88F6323" -+ -+#define MV_632X_A1_REV 0x2 -+ -+#define MV_6321_A1_ID ((MV_6321_DEV_ID << 16) | MV_632X_A1_REV) -+#define MV_6322_A1_ID ((MV_6322_DEV_ID << 16) | MV_632X_A1_REV) -+#define MV_6323_A1_ID ((MV_6323_DEV_ID << 16) | MV_632X_A1_REV) -+ -+#define MV_6321_A1_NAME "88F6321 A1" -+#define MV_6322_A1_NAME "88F6322 A1" -+#define MV_6323_A1_NAME "88F6323 A1" -+ -+ -+#endif /* __INCmvDeviceIdh */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvHalVer.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvHalVer.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvHalVer.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvHalVer.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,73 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvHalVerh -+#define __INCmvHalVerh -+ -+/* Defines */ -+#define MV_HAL_VERSION "FEROCEON_HAL_3_1_7" -+#define MV_RELEASE_BASELINE "SoCandControllers_FEROCEON_RELEASE_7_9_2009_KW_4_3_4_DD_2_1_4_6183_1_1_4" -+ -+#endif /* __INCmvHalVerh */ -\ No newline at end of file -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvStack.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvStack.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvStack.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvStack.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,100 @@ -+/******************************************************************************* -+* Copyright 2003, Marvell Semiconductor Israel LTD. * -+* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL. * -+* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT * -+* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE * -+* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL. * -+* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED, * -+* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE. * -+* * -+* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, * -+* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL * -+* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K. * -+* (MJKK), MARVELL SEMICONDUCTOR ISRAEL LTD (MSIL). * -+******************************************************************************** -+* mvQueue.c -+* -+* FILENAME: $Workfile: mvStack.c $ -+* REVISION: $Revision: 1.1 $ -+* LAST UPDATE: $Modtime: $ -+* -+* DESCRIPTION: -+* This file implements simple Stack LIFO functionality. -+*******************************************************************************/ -+ -+/* includes */ -+#include "mvOs.h" -+#include "mvTypes.h" -+#include "mvDebug.h" -+#include "mvStack.h" -+ -+/* defines */ -+ -+ -+/* Public functions */ -+ -+ -+/* Purpose: Create new stack -+ * Inputs: -+ * - MV_U32 noOfElements - maximum number of elements in the stack. -+ * Each element 4 bytes size -+ * Return: void* - pointer to created stack. -+ */ -+void* mvStackCreate(int numOfElements) -+{ -+ MV_STACK* pStack; -+ MV_U32* pStackElements; -+ -+ pStack = (MV_STACK*)mvOsMalloc(sizeof(MV_STACK)); -+ pStackElements = (MV_U32*)mvOsMalloc(numOfElements*sizeof(MV_U32)); -+ if( (pStack == NULL) || (pStackElements == NULL) ) -+ { -+ mvOsPrintf("mvStack: Can't create new stack\n"); -+ return NULL; -+ } -+ memset(pStackElements, 0, numOfElements*sizeof(MV_U32)); -+ pStack->numOfElements = numOfElements; -+ pStack->stackIdx = 0; -+ pStack->stackElements = pStackElements; -+ -+ return pStack; -+} -+ -+/* Purpose: Delete existing stack -+ * Inputs: -+ * - void* stackHndl - Stack handle as returned by "mvStackCreate()" function -+ * -+ * Return: MV_STATUS MV_NOT_FOUND - Failure. StackHandle is not valid. -+ * MV_OK - Success. -+ */ -+MV_STATUS mvStackDelete(void* stackHndl) -+{ -+ MV_STACK* pStack = (MV_STACK*)stackHndl; -+ -+ if( (pStack == NULL) || (pStack->stackElements == NULL) ) -+ return MV_NOT_FOUND; -+ -+ mvOsFree(pStack->stackElements); -+ mvOsFree(pStack); -+ -+ return MV_OK; -+} -+ -+ -+/* PrintOut status of the stack */ -+void mvStackStatus(void* stackHndl, MV_BOOL isPrintElements) -+{ -+ int i; -+ MV_STACK* pStack = (MV_STACK*)stackHndl; -+ -+ mvOsPrintf("StackHandle=%p, pElements=%p, numElements=%d, stackIdx=%d\n", -+ stackHndl, pStack->stackElements, pStack->numOfElements, -+ pStack->stackIdx); -+ if(isPrintElements == MV_TRUE) -+ { -+ for(i=0; istackIdx; i++) -+ { -+ mvOsPrintf("%3d. Value=0x%x\n", i, pStack->stackElements[i]); -+ } -+ } -+} -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvStack.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvStack.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvStack.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvStack.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,140 @@ -+/******************************************************************************* -+* Copyright 2003, Marvell Semiconductor Israel LTD. * -+* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL. * -+* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT * -+* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE * -+* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL. * -+* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED, * -+* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE. * -+* * -+* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, * -+* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL * -+* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K. * -+* (MJKK), MARVELL SEMICONDUCTOR ISRAEL LTD (MSIL). * -+******************************************************************************** -+* mvStack.h - Header File for : -+* -+* FILENAME: $Workfile: mvStack.h $ -+* REVISION: $Revision: 1.1 $ -+* LAST UPDATE: $Modtime: $ -+* -+* DESCRIPTION: -+* This file defines simple Stack (LIFO) functionality. -+* -+*******************************************************************************/ -+ -+#ifndef __mvStack_h__ -+#define __mvStack_h__ -+ -+ -+/* includes */ -+#include "mvTypes.h" -+ -+ -+/* defines */ -+ -+ -+/* typedefs */ -+/* Data structure describes general purpose Stack */ -+typedef struct -+{ -+ int stackIdx; -+ int numOfElements; -+ MV_U32* stackElements; -+} MV_STACK; -+ -+static INLINE MV_BOOL mvStackIsFull(void* stackHndl) -+{ -+ MV_STACK* pStack = (MV_STACK*)stackHndl; -+ -+ if(pStack->stackIdx == pStack->numOfElements) -+ return MV_TRUE; -+ -+ return MV_FALSE; -+} -+ -+static INLINE MV_BOOL mvStackIsEmpty(void* stackHndl) -+{ -+ MV_STACK* pStack = (MV_STACK*)stackHndl; -+ -+ if(pStack->stackIdx == 0) -+ return MV_TRUE; -+ -+ return MV_FALSE; -+} -+/* Purpose: Push new element to stack -+ * Inputs: -+ * - void* stackHndl - Stack handle as returned by "mvStackCreate()" function. -+ * - MV_U32 value - New element. -+ * -+ * Return: MV_STATUS MV_FULL - Failure. Stack is full. -+ * MV_OK - Success. Element is put to stack. -+ */ -+static INLINE void mvStackPush(void* stackHndl, MV_U32 value) -+{ -+ MV_STACK* pStack = (MV_STACK*)stackHndl; -+ -+#ifdef MV_RT_DEBUG -+ if(pStack->stackIdx == pStack->numOfElements) -+ { -+ mvOsPrintf("mvStackPush: Stack is FULL\n"); -+ return; -+ } -+#endif /* MV_RT_DEBUG */ -+ -+ pStack->stackElements[pStack->stackIdx] = value; -+ pStack->stackIdx++; -+} -+ -+/* Purpose: Pop element from the top of stack and copy it to "pValue" -+ * Inputs: -+ * - void* stackHndl - Stack handle as returned by "mvStackCreate()" function. -+ * - MV_U32 value - Element in the top of stack. -+ * -+ * Return: MV_STATUS MV_EMPTY - Failure. Stack is empty. -+ * MV_OK - Success. Element is removed from the stack and -+ * copied to pValue argument -+ */ -+static INLINE MV_U32 mvStackPop(void* stackHndl) -+{ -+ MV_STACK* pStack = (MV_STACK*)stackHndl; -+ -+#ifdef MV_RT_DEBUG -+ if(pStack->stackIdx == 0) -+ { -+ mvOsPrintf("mvStackPop: Stack is EMPTY\n"); -+ return 0; -+ } -+#endif /* MV_RT_DEBUG */ -+ -+ pStack->stackIdx--; -+ return pStack->stackElements[pStack->stackIdx]; -+} -+ -+static INLINE int mvStackIndex(void* stackHndl) -+{ -+ MV_STACK* pStack = (MV_STACK*)stackHndl; -+ -+ return pStack->stackIdx; -+} -+ -+static INLINE int mvStackFreeElements(void* stackHndl) -+{ -+ MV_STACK* pStack = (MV_STACK*)stackHndl; -+ -+ return (pStack->numOfElements - pStack->stackIdx); -+} -+ -+/* mvStack.h API list */ -+ -+/* Create new Stack */ -+void* mvStackCreate(int numOfElements); -+ -+/* Delete existing stack */ -+MV_STATUS mvStackDelete(void* stackHndl); -+ -+/* Print status of the stack */ -+void mvStackStatus(void* stackHndl, MV_BOOL isPrintElements); -+ -+#endif /* __mvStack_h__ */ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvTypes.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvTypes.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvTypes.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvTypes.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,245 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvTypesh -+#define __INCmvTypesh -+ -+/* Defines */ -+ -+/* The following is a list of Marvell status */ -+#define MV_ERROR (-1) -+#define MV_OK (0x00) /* Operation succeeded */ -+#define MV_FAIL (0x01) /* Operation failed */ -+#define MV_BAD_VALUE (0x02) /* Illegal value (general) */ -+#define MV_OUT_OF_RANGE (0x03) /* The value is out of range */ -+#define MV_BAD_PARAM (0x04) /* Illegal parameter in function called */ -+#define MV_BAD_PTR (0x05) /* Illegal pointer value */ -+#define MV_BAD_SIZE (0x06) /* Illegal size */ -+#define MV_BAD_STATE (0x07) /* Illegal state of state machine */ -+#define MV_SET_ERROR (0x08) /* Set operation failed */ -+#define MV_GET_ERROR (0x09) /* Get operation failed */ -+#define MV_CREATE_ERROR (0x0A) /* Fail while creating an item */ -+#define MV_NOT_FOUND (0x0B) /* Item not found */ -+#define MV_NO_MORE (0x0C) /* No more items found */ -+#define MV_NO_SUCH (0x0D) /* No such item */ -+#define MV_TIMEOUT (0x0E) /* Time Out */ -+#define MV_NO_CHANGE (0x0F) /* Parameter(s) is already in this value */ -+#define MV_NOT_SUPPORTED (0x10) /* This request is not support */ -+#define MV_NOT_IMPLEMENTED (0x11) /* Request supported but not implemented */ -+#define MV_NOT_INITIALIZED (0x12) /* The item is not initialized */ -+#define MV_NO_RESOURCE (0x13) /* Resource not available (memory ...) */ -+#define MV_FULL (0x14) /* Item is full (Queue or table etc...) */ -+#define MV_EMPTY (0x15) /* Item is empty (Queue or table etc...) */ -+#define MV_INIT_ERROR (0x16) /* Error occured while INIT process */ -+#define MV_HW_ERROR (0x17) /* Hardware error */ -+#define MV_TX_ERROR (0x18) /* Transmit operation not succeeded */ -+#define MV_RX_ERROR (0x19) /* Recieve operation not succeeded */ -+#define MV_NOT_READY (0x1A) /* The other side is not ready yet */ -+#define MV_ALREADY_EXIST (0x1B) /* Tried to create existing item */ -+#define MV_OUT_OF_CPU_MEM (0x1C) /* Cpu memory allocation failed. */ -+#define MV_NOT_STARTED (0x1D) /* Not started yet */ -+#define MV_BUSY (0x1E) /* Item is busy. */ -+#define MV_TERMINATE (0x1F) /* Item terminates it's work. */ -+#define MV_NOT_ALIGNED (0x20) /* Wrong alignment */ -+#define MV_NOT_ALLOWED (0x21) /* Operation NOT allowed */ -+#define MV_WRITE_PROTECT (0x22) /* Write protected */ -+ -+ -+#define MV_INVALID (int)(-1) -+ -+#define MV_FALSE 0 -+#define MV_TRUE (!(MV_FALSE)) -+ -+ -+#ifndef NULL -+#define NULL ((void*)0) -+#endif -+ -+ -+#ifndef MV_ASMLANGUAGE -+/* typedefs */ -+ -+typedef char MV_8; -+typedef unsigned char MV_U8; -+ -+typedef int MV_32; -+typedef unsigned int MV_U32; -+ -+typedef short MV_16; -+typedef unsigned short MV_U16; -+ -+#ifdef MV_PPC64 -+typedef long MV_64; -+typedef unsigned long MV_U64; -+#else -+typedef long long MV_64; -+typedef unsigned long long MV_U64; -+#endif -+ -+typedef long MV_LONG; /* 32/64 */ -+typedef unsigned long MV_ULONG; /* 32/64 */ -+ -+typedef int MV_STATUS; -+typedef int MV_BOOL; -+typedef void MV_VOID; -+typedef float MV_FLOAT; -+ -+typedef int (*MV_FUNCPTR) (void); /* ptr to function returning int */ -+typedef void (*MV_VOIDFUNCPTR) (void); /* ptr to function returning void */ -+typedef double (*MV_DBLFUNCPTR) (void); /* ptr to function returning double*/ -+typedef float (*MV_FLTFUNCPTR) (void); /* ptr to function returning float */ -+ -+typedef MV_U32 MV_KHZ; -+typedef MV_U32 MV_MHZ; -+typedef MV_U32 MV_HZ; -+ -+ -+/* This enumerator describes the set of commands that can be applied on */ -+/* an engine (e.g. IDMA, XOR). Appling a comman depends on the current */ -+/* status (see MV_STATE enumerator) */ -+/* Start can be applied only when status is IDLE */ -+/* Stop can be applied only when status is IDLE, ACTIVE or PAUSED */ -+/* Pause can be applied only when status is ACTIVE */ -+/* Restart can be applied only when status is PAUSED */ -+typedef enum _mvCommand -+{ -+ MV_START, /* Start */ -+ MV_STOP, /* Stop */ -+ MV_PAUSE, /* Pause */ -+ MV_RESTART /* Restart */ -+} MV_COMMAND; -+ -+/* This enumerator describes the set of state conditions. */ -+/* Moving from one state to other is stricted. */ -+typedef enum _mvState -+{ -+ MV_IDLE, -+ MV_ACTIVE, -+ MV_PAUSED, -+ MV_UNDEFINED_STATE -+} MV_STATE; -+ -+ -+/* This structure describes address space window. Window base can be */ -+/* 64 bit, window size up to 4GB */ -+typedef struct _mvAddrWin -+{ -+ MV_U32 baseLow; /* 32bit base low */ -+ MV_U32 baseHigh; /* 32bit base high */ -+ MV_U32 size; /* 32bit size */ -+}MV_ADDR_WIN; -+ -+/* This binary enumerator describes protection attribute status */ -+typedef enum _mvProtRight -+{ -+ ALLOWED, /* Protection attribute allowed */ -+ FORBIDDEN /* Protection attribute forbidden */ -+}MV_PROT_RIGHT; -+ -+/* Unified struct for Rx and Tx packet operations. The user is required to */ -+/* be familier only with Tx/Rx descriptor command status. */ -+typedef struct _bufInfo -+{ -+ MV_U32 cmdSts; /* Tx/Rx command status */ -+ MV_U16 byteCnt; /* Size of valid data in the buffer */ -+ MV_U16 bufSize; /* Total size of the buffer */ -+ MV_U8 *pBuff; /* Pointer to Buffer */ -+ MV_U8 *pData; /* Pointer to data in the Buffer */ -+ MV_U32 userInfo1; /* Tx/Rx attached user information 1 */ -+ MV_U32 userInfo2; /* Tx/Rx attached user information 2 */ -+ struct _bufInfo *pNextBufInfo; /* Next buffer in packet */ -+} BUF_INFO; -+ -+/* This structure contains information describing one of buffers -+ * (fragments) they are built Ethernet packet. -+ */ -+typedef struct -+{ -+ MV_U8* bufVirtPtr; -+ MV_ULONG bufPhysAddr; -+ MV_U32 bufSize; -+ MV_U32 dataSize; -+ MV_U32 memHandle; -+ MV_32 bufAddrShift; -+} MV_BUF_INFO; -+ -+/* This structure contains information describing Ethernet packet. -+ * The packet can be divided for few buffers (fragments) -+ */ -+typedef struct -+{ -+ MV_ULONG osInfo; -+ MV_BUF_INFO *pFrags; -+ MV_U32 status; -+ MV_U16 pktSize; -+ MV_U16 numFrags; -+ MV_U32 ownerId; -+ MV_U32 fragIP; -+} MV_PKT_INFO; -+ -+#endif /* MV_ASMLANGUAGE */ -+ -+#endif /* __INCmvTypesh */ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/dbg-trace.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/dbg-trace.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/dbg-trace.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/dbg-trace.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,110 @@ -+#include -+#include -+#include -+#include "dbg-trace.h" -+ -+#define TRACE_ARR_LEN 800 -+#define STR_LEN 128 -+struct trace { -+ struct timeval tv; -+ char str[STR_LEN]; -+ unsigned int callback_val1; -+ unsigned int callback_val2; -+ char valid; -+}; -+static unsigned int (*trc_callback1) (unsigned char) = NULL; -+static unsigned int (*trc_callback2) (unsigned char) = NULL; -+static unsigned char trc_param1 = 0; -+static unsigned char trc_param2 = 0; -+struct trace *trc_arr; -+static int trc_index; -+static int trc_active = 0; -+ -+void TRC_START() -+{ -+ trc_active = 1; -+} -+ -+void TRC_STOP() -+{ -+ trc_active = 0; -+} -+ -+void TRC_INIT(void *callback1, void *callback2, unsigned char callback1_param, unsigned char callback2_param) -+{ -+ printk("Marvell debug tracing is on\n"); -+ trc_arr = (struct trace *)kmalloc(TRACE_ARR_LEN*sizeof(struct trace),GFP_KERNEL); -+ if(trc_arr == NULL) -+ { -+ printk("Can't allocate Debug Trace buffer\n"); -+ return; -+ } -+ memset(trc_arr,0,TRACE_ARR_LEN*sizeof(struct trace)); -+ trc_index = 0; -+ trc_callback1 = callback1; -+ trc_callback2 = callback2; -+ trc_param1 = callback1_param; -+ trc_param2 = callback2_param; -+} -+void TRC_REC(char *fmt,...) -+{ -+ va_list args; -+ struct trace *trc = &trc_arr[trc_index]; -+ -+ if(trc_active == 0) -+ return; -+ -+ do_gettimeofday(&trc->tv); -+ if(trc_callback1) -+ trc->callback_val1 = trc_callback1(trc_param1); -+ if(trc_callback2) -+ trc->callback_val2 = trc_callback2(trc_param2); -+ va_start(args, fmt); -+ vsprintf(trc->str,fmt,args); -+ va_end(args); -+ trc->valid = 1; -+ if((++trc_index) == TRACE_ARR_LEN) { -+ trc_index = 0; -+ } -+} -+void TRC_OUTPUT(void) -+{ -+ int i,j; -+ struct trace *p; -+ printk("\n\nTrace %d items\n",TRACE_ARR_LEN); -+ for(i=0,j=trc_index; ivalid) { -+ unsigned long uoffs; -+ struct trace *plast; -+ if(p == &trc_arr[0]) -+ plast = &trc_arr[TRACE_ARR_LEN-1]; -+ else -+ plast = p-1; -+ if(p->tv.tv_sec == ((plast)->tv.tv_sec)) -+ uoffs = (p->tv.tv_usec - ((plast)->tv.tv_usec)); -+ else -+ uoffs = (1000000 - ((plast)->tv.tv_usec)) + -+ ((p->tv.tv_sec - ((plast)->tv.tv_sec) - 1) * 1000000) + -+ p->tv.tv_usec; -+ printk("%03d: [+%ld usec]", j, (unsigned long)uoffs); -+ if(trc_callback1) -+ printk("[%u]",p->callback_val1); -+ if(trc_callback2) -+ printk("[%u]",p->callback_val2); -+ printk(": %s",p->str); -+ } -+ p->valid = 0; -+ } -+ memset(trc_arr,0,TRACE_ARR_LEN*sizeof(struct trace)); -+ trc_index = 0; -+} -+void TRC_RELEASE(void) -+{ -+ kfree(trc_arr); -+ trc_index = 0; -+} -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/dbg-trace.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/dbg-trace.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/dbg-trace.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/dbg-trace.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,24 @@ -+ -+#ifndef _MV_DBG_TRCE_H_ -+#define _MV_DBG_TRCE_H_ -+ -+#ifdef CONFIG_MV_DBG_TRACE -+void TRC_INIT(void *callback1, void *callback2, -+ unsigned char callback1_param, unsigned char callback2_param); -+void TRC_REC(char *fmt,...); -+void TRC_OUTPUT(void); -+void TRC_RELEASE(void); -+void TRC_START(void); -+void TRC_STOP(void); -+ -+#else -+#define TRC_INIT(x1,x2,x3,x4) -+#define TRC_REC(X...) -+#define TRC_OUTPUT() -+#define TRC_RELEASE() -+#define TRC_START() -+#define TRC_STOP() -+#endif -+ -+ -+#endif -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,2513 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "boardEnv/mvBoardEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+#include "cpu/mvCpu.h" -+#include "cntmr/mvCntmr.h" -+#include "gpp/mvGpp.h" -+#include "twsi/mvTwsi.h" -+#include "pex/mvPex.h" -+#include "device/mvDevice.h" -+#include "eth/gbe/mvEthRegs.h" -+ -+/* defines */ -+/* #define MV_DEBUG */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+extern MV_CPU_ARM_CLK _cpuARMDDRCLK[]; -+ -+#define CODE_IN_ROM MV_FALSE -+#define CODE_IN_RAM MV_TRUE -+ -+extern MV_BOARD_INFO* boardInfoTbl[]; -+#define BOARD_INFO(boardId) boardInfoTbl[boardId - BOARD_ID_BASE] -+ -+/* Locals */ -+static MV_DEV_CS_INFO* boardGetDevEntry(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); -+ -+MV_U32 tClkRate = -1; -+ -+ -+/******************************************************************************* -+* mvBoardEnvInit - Init board -+* -+* DESCRIPTION: -+* In this function the board environment take care of device bank -+* initialization. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvBoardEnvInit(MV_VOID) -+{ -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardEnvInit:Board unknown.\n"); -+ return; -+ -+ } -+ -+ /* Set GPP Out value */ -+ MV_REG_WRITE(GPP_DATA_OUT_REG(0), BOARD_INFO(boardId)->gppOutValLow); -+ MV_REG_WRITE(GPP_DATA_OUT_REG(1), BOARD_INFO(boardId)->gppOutValHigh); -+ -+ /* set GPP polarity */ -+ mvGppPolaritySet(0, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValLow); -+ mvGppPolaritySet(1, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValHigh); -+ -+ /* Workaround for Erratum FE-MISC-70*/ -+ if(mvCtrlRevGet()==MV_88F6XXX_A0_REV) -+ { -+ BOARD_INFO(boardId)->gppOutEnValLow &= 0xfffffffd; -+ BOARD_INFO(boardId)->gppOutEnValLow |= (BOARD_INFO(boardId)->gppOutEnValHigh) & 0x00000002; -+ } /*End of WA*/ -+ -+ /* Set GPP Out Enable*/ -+ mvGppTypeSet(0, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValLow); -+ mvGppTypeSet(1, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValHigh); -+ -+ /* Nand CE */ -+ MV_REG_BIT_SET(NAND_CTRL_REG, NAND_ACTCEBOOT_BIT); -+} -+ -+/******************************************************************************* -+* mvBoardModelGet - Get Board model -+* -+* DESCRIPTION: -+* This function returns 16bit describing board model. -+* Board model is constructed of one byte major and minor numbers in the -+* following manner: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* String describing board model. -+* -+*******************************************************************************/ -+MV_U16 mvBoardModelGet(MV_VOID) -+{ -+ return (mvBoardIdGet() >> 16); -+} -+ -+/******************************************************************************* -+* mbBoardRevlGet - Get Board revision -+* -+* DESCRIPTION: -+* This function returns a 32bit describing the board revision. -+* Board revision is constructed of 4bytes. 2bytes describes major number -+* and the other 2bytes describes minor munber. -+* For example for board revision 3.4 the function will return -+* 0x00030004. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* String describing board model. -+* -+*******************************************************************************/ -+MV_U16 mvBoardRevGet(MV_VOID) -+{ -+ return (mvBoardIdGet() & 0xFFFF); -+} -+ -+/******************************************************************************* -+* mvBoardNameGet - Get Board name -+* -+* DESCRIPTION: -+* This function returns a string describing the board model and revision. -+* String is extracted from board I2C EEPROM. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* pNameBuff - Buffer to contain board name string. Minimum size 32 chars. -+* -+* RETURN: -+* -+* MV_ERROR if informantion can not be read. -+*******************************************************************************/ -+MV_STATUS mvBoardNameGet(char *pNameBuff) -+{ -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsSPrintf (pNameBuff, "Board unknown.\n"); -+ return MV_ERROR; -+ -+ } -+ -+ mvOsSPrintf (pNameBuff, "%s",BOARD_INFO(boardId)->boardName); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvBoardIsPortInSgmii - -+* -+* DESCRIPTION: -+* This routine returns MV_TRUE for port number works in SGMII or MV_FALSE -+* For all other options. -+* -+* INPUT: -+* ethPortNum - Ethernet port number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE - port in SGMII. -+* MV_FALSE - other. -+* -+*******************************************************************************/ -+MV_BOOL mvBoardIsPortInSgmii(MV_U32 ethPortNum) -+{ -+ MV_BOOL ethPortSgmiiSupport[BOARD_ETH_PORT_NUM] = MV_ETH_PORT_SGMII; -+ -+ if(ethPortNum >= BOARD_ETH_PORT_NUM) -+ { -+ mvOsPrintf ("Invalid portNo=%d\n", ethPortNum); -+ return MV_FALSE; -+ } -+ return ethPortSgmiiSupport[ethPortNum]; -+} -+ -+/******************************************************************************* -+* mvBoardIsPortInGmii - -+* -+* DESCRIPTION: -+* This routine returns MV_TRUE for port number works in GMII or MV_FALSE -+* For all other options. -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE - port in GMII. -+* MV_FALSE - other. -+* -+*******************************************************************************/ -+MV_BOOL mvBoardIsPortInGmii(MV_VOID) -+{ -+ MV_U32 devClassId, devClass = 0; -+ if (mvBoardMppGroupTypeGet(devClass) == MV_BOARD_AUTO) -+ { -+ /* Get MPP module ID */ -+ devClassId = mvBoarModuleTypeGet(devClass); -+ if (MV_BOARD_MODULE_GMII_ID == devClassId) -+ return MV_TRUE; -+ } -+ else if (mvBoardMppGroupTypeGet(devClass) == MV_BOARD_GMII) -+ return MV_TRUE; -+ -+ return MV_FALSE; -+} -+/******************************************************************************* -+* mvBoardPhyAddrGet - Get the phy address -+* -+* DESCRIPTION: -+* This routine returns the Phy address of a given ethernet port. -+* -+* INPUT: -+* ethPortNum - Ethernet port number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit describing Phy address, -1 if the port number is wrong. -+* -+*******************************************************************************/ -+MV_32 mvBoardPhyAddrGet(MV_U32 ethPortNum) -+{ -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardPhyAddrGet: Board unknown.\n"); -+ return MV_ERROR; -+ } -+ -+ return BOARD_INFO(boardId)->pBoardMacInfo[ethPortNum].boardEthSmiAddr; -+} -+ -+/******************************************************************************* -+* mvBoardMacSpeedGet - Get the Mac speed -+* -+* DESCRIPTION: -+* This routine returns the Mac speed if pre define of a given ethernet port. -+* -+* INPUT: -+* ethPortNum - Ethernet port number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BOARD_MAC_SPEED, -1 if the port number is wrong. -+* -+*******************************************************************************/ -+MV_BOARD_MAC_SPEED mvBoardMacSpeedGet(MV_U32 ethPortNum) -+{ -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardMacSpeedGet: Board unknown.\n"); -+ return MV_ERROR; -+ } -+ -+ return BOARD_INFO(boardId)->pBoardMacInfo[ethPortNum].boardMacSpeed; -+} -+ -+/******************************************************************************* -+* mvBoardLinkStatusIrqGet - Get the IRQ number for the link status indication -+* -+* DESCRIPTION: -+* This routine returns the IRQ number for the link status indication. -+* -+* INPUT: -+* ethPortNum - Ethernet port number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* the number of the IRQ for the link status indication, -1 if the port -+* number is wrong or if not relevant. -+* -+*******************************************************************************/ -+MV_32 mvBoardLinkStatusIrqGet(MV_U32 ethPortNum) -+{ -+ MV_U32 boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardLinkStatusIrqGet: Board unknown.\n"); -+ return MV_ERROR; -+ } -+ -+ return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].linkStatusIrq; -+} -+ -+/******************************************************************************* -+* mvBoardSwitchPortGet - Get the mapping between the board connector and the -+* Ethernet Switch port -+* -+* DESCRIPTION: -+* This routine returns the matching Switch port. -+* -+* INPUT: -+* ethPortNum - Ethernet port number. -+* boardPortNum - logical number of the connector on the board -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* the matching Switch port, -1 if the port number is wrong or if not relevant. -+* -+*******************************************************************************/ -+MV_32 mvBoardSwitchPortGet(MV_U32 ethPortNum, MV_U8 boardPortNum) -+{ -+ MV_U32 boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardSwitchPortGet: Board unknown.\n"); -+ return MV_ERROR; -+ } -+ if (boardPortNum >= BOARD_ETH_SWITCH_PORT_NUM) -+ { -+ mvOsPrintf("mvBoardSwitchPortGet: Illegal board port number.\n"); -+ return MV_ERROR; -+ } -+ -+ return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].qdPort[boardPortNum]; -+} -+ -+/******************************************************************************* -+* mvBoardSwitchCpuPortGet - Get the the Ethernet Switch CPU port -+* -+* DESCRIPTION: -+* This routine returns the Switch CPU port. -+* -+* INPUT: -+* ethPortNum - Ethernet port number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* the Switch CPU port, -1 if the port number is wrong or if not relevant. -+* -+*******************************************************************************/ -+MV_32 mvBoardSwitchCpuPortGet(MV_U32 ethPortNum) -+{ -+ MV_U32 boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardSwitchCpuPortGet: Board unknown.\n"); -+ return MV_ERROR; -+ } -+ -+ return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].qdCpuPort; -+} -+ -+/******************************************************************************* -+* mvBoardIsSwitchConnected - Get switch connection status -+* DESCRIPTION: -+* This routine returns port's connection status -+* -+* INPUT: -+* ethPortNum - Ethernet port number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 1 - if ethPortNum is connected to switch, 0 otherwise -+* -+*******************************************************************************/ -+MV_32 mvBoardIsSwitchConnected(MV_U32 ethPortNum) -+{ -+ MV_U32 boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardIsSwitchConnected: Board unknown.\n"); -+ return MV_ERROR; -+ } -+ -+ if(ethPortNum >= BOARD_INFO(boardId)->numBoardMacInfo) -+ { -+ mvOsPrintf("mvBoardIsSwitchConnected: Illegal port number(%u)\n", ethPortNum); -+ return MV_ERROR; -+ } -+ -+ if((MV_32)(BOARD_INFO(boardId)->pSwitchInfo)) -+ return (MV_32)(BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].switchOnPort == ethPortNum); -+ else -+ return 0; -+} -+/******************************************************************************* -+* mvBoardSmiScanModeGet - Get Switch SMI scan mode -+* -+* DESCRIPTION: -+* This routine returns Switch SMI scan mode. -+* -+* INPUT: -+* ethPortNum - Ethernet port number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 1 for SMI_MANUAL_MODE, -1 if the port number is wrong or if not relevant. -+* -+*******************************************************************************/ -+MV_32 mvBoardSmiScanModeGet(MV_U32 ethPortNum) -+{ -+ MV_U32 boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardSmiScanModeGet: Board unknown.\n"); -+ return MV_ERROR; -+ } -+ -+ return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].smiScanMode; -+} -+/******************************************************************************* -+* mvBoardSpecInitGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: Return MV_TRUE and parameters in case board need spesific phy init, -+* otherwise return MV_FALSE. -+* -+* -+*******************************************************************************/ -+ -+MV_BOOL mvBoardSpecInitGet(MV_U32* regOff, MV_U32* data) -+{ -+ return MV_FALSE; -+} -+ -+/******************************************************************************* -+* mvBoardTclkGet - Get the board Tclk (Controller clock) -+* -+* DESCRIPTION: -+* This routine extract the controller core clock. -+* This function uses the controller counters to make identification. -+* Note: In order to avoid interference, make sure task context switch -+* and interrupts will not occure during this function operation -+* -+* INPUT: -+* countNum - Counter number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit clock cycles in Hertz. -+* -+*******************************************************************************/ -+MV_U32 mvBoardTclkGet(MV_VOID) -+{ -+ if(mvCtrlModelGet()==MV_6281_DEV_ID) -+ { -+#if defined(TCLK_AUTO_DETECT) -+ MV_U32 tmpTClkRate = MV_BOARD_TCLK_166MHZ; -+ -+ tmpTClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ tmpTClkRate &= MSAR_TCLCK_MASK; -+ -+ switch (tmpTClkRate) -+ { -+ case MSAR_TCLCK_166: -+ return MV_BOARD_TCLK_166MHZ; -+ break; -+ case MSAR_TCLCK_200: -+ return MV_BOARD_TCLK_200MHZ; -+ break; -+ } -+#else -+ return MV_BOARD_TCLK_200MHZ; -+#endif -+ } -+ -+ return MV_BOARD_TCLK_166MHZ; -+ -+} -+/******************************************************************************* -+* mvBoardSysClkGet - Get the board SysClk (CPU bus clock) -+* -+* DESCRIPTION: -+* This routine extract the CPU bus clock. -+* -+* INPUT: -+* countNum - Counter number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit clock cycles in Hertz. -+* -+*******************************************************************************/ -+static MV_U32 mvBoard6180SysClkGet(MV_VOID) -+{ -+ MV_U32 sysClkRate=0; -+ MV_CPU_ARM_CLK _cpu6180_ddr_l2_CLK[] = MV_CPU6180_DDR_L2_CLCK_TBL; -+ -+ sysClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ sysClkRate = sysClkRate & MSAR_CPUCLCK_MASK_6180; -+ sysClkRate = sysClkRate >> MSAR_CPUCLCK_OFFS_6180; -+ -+ sysClkRate = _cpu6180_ddr_l2_CLK[sysClkRate].ddrClk; -+ -+ return sysClkRate; -+ -+} -+ -+MV_U32 mvBoardSysClkGet(MV_VOID) -+{ -+#ifdef SYSCLK_AUTO_DETECT -+ MV_U32 sysClkRate, tmp, pClkRate, indexDdrRtio; -+ MV_U32 cpuCLK[] = MV_CPU_CLCK_TBL; -+ MV_U32 ddrRtio[][2] = MV_DDR_CLCK_RTIO_TBL; -+ -+ if(mvCtrlModelGet() == MV_6180_DEV_ID) -+ return mvBoard6180SysClkGet(); -+ -+ tmp = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ pClkRate = MSAR_CPUCLCK_EXTRACT(tmp); -+ pClkRate = cpuCLK[pClkRate]; -+ -+ indexDdrRtio = tmp & MSAR_DDRCLCK_RTIO_MASK; -+ indexDdrRtio = indexDdrRtio >> MSAR_DDRCLCK_RTIO_OFFS; -+ if(ddrRtio[indexDdrRtio][0] != 0) -+ sysClkRate = ((pClkRate * ddrRtio[indexDdrRtio][1]) / ddrRtio[indexDdrRtio][0]); -+ else -+ sysClkRate = 0; -+ return sysClkRate; -+#else -+ return MV_BOARD_DEFAULT_SYSCLK; -+#endif -+} -+ -+ -+/******************************************************************************* -+* mvBoardPexBridgeIntPinGet - Get PEX to PCI bridge interrupt pin number -+* -+* DESCRIPTION: -+* Multi-ported PCI Express bridges that is implemented on the board -+* collapse interrupts across multiple conventional PCI/PCI-X buses. -+* A dual-headed PCI Express bridge would map (or "swizzle") the -+* interrupts per the following table (in accordance with the respective -+* logical PCI/PCI-X bridge's Device Number), collapse the INTA#-INTD# -+* signals from its two logical PCI/PCI-X bridges, collapse the -+* INTA#-INTD# signals from any internal sources, and convert the -+* signals to in-band PCI Express messages. 10 -+* This function returns the upstream interrupt as it was converted by -+* the bridge, according to board configuration and the following table: -+* PCI dev num -+* Interrupt pin 7, 8, 9 -+* A -> A D C -+* B -> B A D -+* C -> C B A -+* D -> D C B -+* -+* -+* INPUT: -+* devNum - PCI/PCIX device number. -+* intPin - PCI Int pin -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Int pin connected to the Interrupt controller -+* -+*******************************************************************************/ -+MV_U32 mvBoardPexBridgeIntPinGet(MV_U32 devNum, MV_U32 intPin) -+{ -+ MV_U32 realIntPin = ((intPin + (3 - (devNum % 4))) %4 ); -+ -+ if (realIntPin == 0) return 4; -+ else return realIntPin; -+ -+} -+ -+/******************************************************************************* -+* mvBoardDebugLedNumGet - Get number of debug Leds -+* -+* DESCRIPTION: -+* INPUT: -+* boardId -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_U32 mvBoardDebugLedNumGet(MV_U32 boardId) -+{ -+ return BOARD_INFO(boardId)->activeLedsNumber; -+} -+ -+/******************************************************************************* -+* mvBoardDebugLeg - Set the board debug Leds -+* -+* DESCRIPTION: turn on/off status leds. -+* Note: assume MPP leds are part of group 0 only. -+* -+* INPUT: -+* hexNum - Number to be displied in hex by Leds. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvBoardDebugLed(MV_U32 hexNum) -+{ -+ MV_U32 val = 0,totalMask, currentBitMask = 1,i; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (BOARD_INFO(boardId)->pLedGppPin == NULL) -+ return; -+ -+ totalMask = (1 << BOARD_INFO(boardId)->activeLedsNumber) -1; -+ hexNum &= totalMask; -+ totalMask = 0; -+ -+ for (i = 0 ; i < BOARD_INFO(boardId)->activeLedsNumber ; i++) -+ { -+ if (hexNum & currentBitMask) -+ { -+ val |= (1 << BOARD_INFO(boardId)->pLedGppPin[i]); -+ } -+ -+ totalMask |= (1 << BOARD_INFO(boardId)->pLedGppPin[i]); -+ -+ currentBitMask = (currentBitMask << 1); -+ } -+ -+ if (BOARD_INFO(boardId)->ledsPolarity) -+ { -+ mvGppValueSet(0, totalMask, val); -+ } -+ else -+ { -+ mvGppValueSet(0, totalMask, ~val); -+ } -+} -+ -+ -+/******************************************************************************* -+* mvBoarGpioPinGet - mvBoarGpioPinGet -+* -+* DESCRIPTION: -+* -+* INPUT: -+* class - MV_BOARD_GPP_CLASS enum. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* GPIO pin number. The function return -1 for bad parameters. -+* -+*******************************************************************************/ -+MV_32 mvBoarGpioPinNumGet(MV_BOARD_GPP_CLASS class, MV_U32 index) -+{ -+ MV_U32 boardId, i; -+ MV_U32 indexFound = 0; -+ -+ boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardRTCGpioPinGet:Board unknown.\n"); -+ return MV_ERROR; -+ -+ } -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardGppInfo; i++) -+ if (BOARD_INFO(boardId)->pBoardGppInfo[i].devClass == class) { -+ if (indexFound == index) -+ return (MV_U32)BOARD_INFO(boardId)->pBoardGppInfo[i].gppPinNum; -+ else -+ indexFound++; -+ -+ } -+ -+ return MV_ERROR; -+} -+ -+ -+/******************************************************************************* -+* mvBoardRTCGpioPinGet - mvBoardRTCGpioPinGet -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* GPIO pin number. The function return -1 for bad parameters. -+* -+*******************************************************************************/ -+MV_32 mvBoardRTCGpioPinGet(MV_VOID) -+{ -+ return mvBoarGpioPinNumGet(BOARD_GPP_RTC, 0); -+} -+ -+ -+/******************************************************************************* -+* mvBoardReset - mvBoardReset -+* -+* DESCRIPTION: -+* Reset the board -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None -+* -+*******************************************************************************/ -+MV_VOID mvBoardReset(MV_VOID) -+{ -+ MV_32 resetPin; -+ -+ /* Get gpp reset pin if define */ -+ resetPin = mvBoardResetGpioPinGet(); -+ if (resetPin != MV_ERROR) -+ { -+ MV_REG_BIT_RESET( GPP_DATA_OUT_REG(0) ,(1 << resetPin)); -+ MV_REG_BIT_RESET( GPP_DATA_OUT_EN_REG(0) ,(1 << resetPin)); -+ -+ } -+ else -+ { -+ /* No gpp reset pin was found, try to reset ussing -+ system reset out */ -+ MV_REG_BIT_SET( CPU_RSTOUTN_MASK_REG , BIT2); -+ MV_REG_BIT_SET( CPU_SYS_SOFT_RST_REG , BIT0); -+ } -+} -+ -+/******************************************************************************* -+* mvBoardResetGpioPinGet - mvBoardResetGpioPinGet -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* GPIO pin number. The function return -1 for bad parameters. -+* -+*******************************************************************************/ -+MV_32 mvBoardResetGpioPinGet(MV_VOID) -+{ -+ return mvBoarGpioPinNumGet(BOARD_GPP_RESET, 0); -+} -+/******************************************************************************* -+* mvBoardSDIOGpioPinGet - mvBoardSDIOGpioPinGet -+* -+* DESCRIPTION: -+* used for hotswap detection -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* GPIO pin number. The function return -1 for bad parameters. -+* -+*******************************************************************************/ -+MV_32 mvBoardSDIOGpioPinGet(MV_VOID) -+{ -+ return mvBoarGpioPinNumGet(BOARD_GPP_SDIO_DETECT, 0); -+} -+ -+/******************************************************************************* -+* mvBoardUSBVbusGpioPinGet - return Vbus input GPP -+* -+* DESCRIPTION: -+* -+* INPUT: -+* int devNo. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* GPIO pin number. The function return -1 for bad parameters. -+* -+*******************************************************************************/ -+MV_32 mvBoardUSBVbusGpioPinGet(MV_32 devId) -+{ -+ return mvBoarGpioPinNumGet(BOARD_GPP_USB_VBUS, devId); -+} -+ -+/******************************************************************************* -+* mvBoardUSBVbusEnGpioPinGet - return Vbus Enable output GPP -+* -+* DESCRIPTION: -+* -+* INPUT: -+* int devNo. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* GPIO pin number. The function return -1 for bad parameters. -+* -+*******************************************************************************/ -+MV_32 mvBoardUSBVbusEnGpioPinGet(MV_32 devId) -+{ -+ return mvBoarGpioPinNumGet(BOARD_GPP_USB_VBUS_EN, devId); -+} -+ -+ -+/******************************************************************************* -+* mvBoardGpioIntMaskGet - Get GPIO mask for interrupt pins -+* -+* DESCRIPTION: -+* This function returns a 32-bit mask of GPP pins that connected to -+* interrupt generating sources on board. -+* For example if UART channel A is hardwired to GPP pin 8 and -+* UART channel B is hardwired to GPP pin 4 the fuinction will return -+* the value 0x000000110 -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* See description. The function return -1 if board is not identified. -+* -+*******************************************************************************/ -+MV_32 mvBoardGpioIntMaskLowGet(MV_VOID) -+{ -+ MV_U32 boardId; -+ -+ boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardGpioIntMaskGet:Board unknown.\n"); -+ return MV_ERROR; -+ -+ } -+ -+ return BOARD_INFO(boardId)->intsGppMaskLow; -+} -+MV_32 mvBoardGpioIntMaskHighGet(MV_VOID) -+{ -+ MV_U32 boardId; -+ -+ boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardGpioIntMaskGet:Board unknown.\n"); -+ return MV_ERROR; -+ -+ } -+ -+ return BOARD_INFO(boardId)->intsGppMaskHigh; -+} -+ -+ -+/******************************************************************************* -+* mvBoardMppGet - Get board dependent MPP register value -+* -+* DESCRIPTION: -+* MPP settings are derived from board design. -+* MPP group consist of 8 MPPs. An MPP group represent MPP -+* control register. -+* This function retrieves board dependend MPP register value. -+* -+* INPUT: -+* mppGroupNum - MPP group number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit value describing MPP control register value. -+* -+*******************************************************************************/ -+MV_32 mvBoardMppGet(MV_U32 mppGroupNum) -+{ -+ MV_U32 boardId; -+ -+ boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardMppGet:Board unknown.\n"); -+ return MV_ERROR; -+ -+ } -+ -+ return BOARD_INFO(boardId)->pBoardMppConfigValue[0].mppGroup[mppGroupNum]; -+} -+ -+ -+/******************************************************************************* -+* mvBoardMppGroupId - If MPP group type is AUTO then identify it using twsi -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_VOID mvBoardMppGroupIdUpdate(MV_VOID) -+{ -+ -+ MV_BOARD_MPP_GROUP_CLASS devClass; -+ MV_BOARD_MODULE_ID_CLASS devClassId; -+ MV_BOARD_MPP_TYPE_CLASS mppGroupType; -+ MV_U32 devId; -+ MV_U32 maxMppGrp = 1; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ maxMppGrp = MV_6281_MPP_MAX_MODULE; -+ break; -+ case MV_6192_DEV_ID: -+ maxMppGrp = MV_6192_MPP_MAX_MODULE; -+ break; -+ case MV_6190_DEV_ID: -+ maxMppGrp = MV_6190_MPP_MAX_MODULE; -+ break; -+ case MV_6180_DEV_ID: -+ maxMppGrp = MV_6180_MPP_MAX_MODULE; -+ break; -+ } -+ -+ for (devClass = 0; devClass < maxMppGrp; devClass++) -+ { -+ /* If MPP group can be defined by the module connected to it */ -+ if (mvBoardMppGroupTypeGet(devClass) == MV_BOARD_AUTO) -+ { -+ /* Get MPP module ID */ -+ devClassId = mvBoarModuleTypeGet(devClass); -+ if (MV_ERROR != devClassId) -+ { -+ switch(devClassId) -+ { -+ case MV_BOARD_MODULE_TDM_ID: -+ case MV_BOARD_MODULE_TDM_5CHAN_ID: -+ mppGroupType = MV_BOARD_TDM; -+ break; -+ case MV_BOARD_MODULE_AUDIO_ID: -+ mppGroupType = MV_BOARD_AUDIO; -+ break; -+ case MV_BOARD_MODULE_RGMII_ID: -+ mppGroupType = MV_BOARD_RGMII; -+ break; -+ case MV_BOARD_MODULE_GMII_ID: -+ mppGroupType = MV_BOARD_GMII; -+ break; -+ case MV_BOARD_MODULE_TS_ID: -+ mppGroupType = MV_BOARD_TS; -+ break; -+ case MV_BOARD_MODULE_MII_ID: -+ mppGroupType = MV_BOARD_MII; -+ break; -+ default: -+ mppGroupType = MV_BOARD_OTHER; -+ break; -+ } -+ } -+ else -+ /* The module bay is empty */ -+ mppGroupType = MV_BOARD_OTHER; -+ -+ /* Update MPP group type */ -+ mvBoardMppGroupTypeSet(devClass, mppGroupType); -+ } -+ -+ /* Update MPP output voltage for RGMII 1.8V. Set port to GMII for GMII module */ -+ if ((mvBoardMppGroupTypeGet(devClass) == MV_BOARD_RGMII)) -+ MV_REG_BIT_SET(MPP_OUTPUT_DRIVE_REG,MPP_1_8_RGMII1_OUTPUT_DRIVE | MPP_1_8_RGMII0_OUTPUT_DRIVE); -+ else -+ { -+ if ((mvBoardMppGroupTypeGet(devClass) == MV_BOARD_GMII)) -+ { -+ MV_REG_BIT_RESET(MPP_OUTPUT_DRIVE_REG, BIT7 | BIT15); -+ MV_REG_BIT_RESET(ETH_PORT_SERIAL_CTRL_1_REG(0),BIT3); -+ MV_REG_BIT_RESET(ETH_PORT_SERIAL_CTRL_1_REG(1),BIT3); -+ } -+ else if ((mvBoardMppGroupTypeGet(devClass) == MV_BOARD_MII)) -+ { -+ /* Assumption that the MDC & MDIO should be 3.3V */ -+ MV_REG_BIT_RESET(MPP_OUTPUT_DRIVE_REG, BIT7 | BIT15); -+ /* Assumption that only ETH1 can be MII when using modules on DB */ -+ MV_REG_BIT_RESET(ETH_PORT_SERIAL_CTRL_1_REG(1),BIT3); -+ } -+ } -+ } -+} -+ -+/******************************************************************************* -+* mvBoardMppGroupTypeGet -+* -+* DESCRIPTION: -+* -+* INPUT: -+* mppGroupClass - MPP group number 0 for MPP[35:20] or 1 for MPP[49:36]. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_BOARD_MPP_TYPE_CLASS mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass) -+{ -+ MV_U32 boardId; -+ -+ boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardMppGet:Board unknown.\n"); -+ return MV_ERROR; -+ -+ } -+ -+ if (mppGroupClass == MV_BOARD_MPP_GROUP_1) -+ return BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup1; -+ else -+ return BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup2; -+} -+ -+/******************************************************************************* -+* mvBoardMppGroupTypeSet -+* -+* DESCRIPTION: -+* -+* INPUT: -+* mppGroupClass - MPP group number 0 for MPP[35:20] or 1 for MPP[49:36]. -+* mppGroupType - MPP group type for MPP[35:20] or for MPP[49:36]. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_VOID mvBoardMppGroupTypeSet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass, -+ MV_BOARD_MPP_TYPE_CLASS mppGroupType) -+{ -+ MV_U32 boardId; -+ -+ boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardMppGet:Board unknown.\n"); -+ } -+ -+ if (mppGroupClass == MV_BOARD_MPP_GROUP_1) -+ BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup1 = mppGroupType; -+ else -+ BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup2 = mppGroupType; -+ -+} -+ -+/******************************************************************************* -+* mvBoardMppMuxSet - Update MPP mux -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_VOID mvBoardMppMuxSet(MV_VOID) -+{ -+ -+ MV_BOARD_MPP_GROUP_CLASS devClass; -+ MV_BOARD_MPP_TYPE_CLASS mppGroupType; -+ MV_U32 devId; -+ MV_U8 muxVal = 0xf; -+ MV_U32 maxMppGrp = 1; -+ MV_TWSI_SLAVE twsiSlave; -+ MV_TWSI_ADDR slave; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ maxMppGrp = MV_6281_MPP_MAX_MODULE; -+ break; -+ case MV_6192_DEV_ID: -+ maxMppGrp = MV_6192_MPP_MAX_MODULE; -+ break; -+ case MV_6190_DEV_ID: -+ maxMppGrp = MV_6190_MPP_MAX_MODULE; -+ break; -+ case MV_6180_DEV_ID: -+ maxMppGrp = MV_6180_MPP_MAX_MODULE; -+ break; -+ } -+ -+ for (devClass = 0; devClass < maxMppGrp; devClass++) -+ { -+ mppGroupType = mvBoardMppGroupTypeGet(devClass); -+ -+ switch(mppGroupType) -+ { -+ case MV_BOARD_TDM: -+ muxVal &= ~(devClass ? (0x2 << (devClass * 2)):0x0); -+ break; -+ case MV_BOARD_AUDIO: -+ muxVal &= ~(devClass ? 0x7 : 0x0); /*old Z0 value 0xd:0x0*/ -+ break; -+ case MV_BOARD_TS: -+ muxVal &= ~(devClass ? (0x2 << (devClass * 2)):0x0); -+ break; -+ default: -+ muxVal |= (devClass ? 0xf : 0); -+ break; -+ } -+ } -+ -+ /* TWSI init */ -+ slave.type = ADDR7_BIT; -+ slave.address = 0; -+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); -+ -+ /* Read MPP module ID */ -+ DB(mvOsPrintf("Board: twsi exp set\n")); -+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(MV_BOARD_MUX_I2C_ADDR_ENTRY); -+ twsiSlave.slaveAddr.type = mvBoardTwsiExpAddrTypeGet(MV_BOARD_MUX_I2C_ADDR_ENTRY); -+ twsiSlave.validOffset = MV_TRUE; -+ /* Offset is the first command after the address which indicate the register number to be read -+ in next operation */ -+ twsiSlave.offset = 2; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ -+ -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) -+ { -+ DB(mvOsPrintf("Board: twsi exp out val fail\n")); -+ return; -+ } -+ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); -+ -+ /* Change twsi exp to output */ -+ twsiSlave.offset = 6; -+ muxVal = 0; -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) -+ { -+ DB(mvOsPrintf("Board: twsi exp change to out fail\n")); -+ return; -+ } -+ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); -+ -+} -+ -+/******************************************************************************* -+* mvBoardTdmMppSet - set MPPs in TDM module -+* -+* DESCRIPTION: -+* -+* INPUT: type of second telephony device -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_VOID mvBoardTdmMppSet(MV_32 chType) -+{ -+ -+ MV_BOARD_MPP_GROUP_CLASS devClass; -+ MV_BOARD_MPP_TYPE_CLASS mppGroupType; -+ MV_U32 devId; -+ MV_U8 muxVal = 1; -+ MV_U8 muxValMask = 1; -+ MV_U8 twsiVal; -+ MV_U32 maxMppGrp = 1; -+ MV_TWSI_SLAVE twsiSlave; -+ MV_TWSI_ADDR slave; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ maxMppGrp = MV_6281_MPP_MAX_MODULE; -+ break; -+ case MV_6192_DEV_ID: -+ maxMppGrp = MV_6192_MPP_MAX_MODULE; -+ break; -+ case MV_6190_DEV_ID: -+ maxMppGrp = MV_6190_MPP_MAX_MODULE; -+ break; -+ case MV_6180_DEV_ID: -+ maxMppGrp = MV_6180_MPP_MAX_MODULE; -+ break; -+ } -+ -+ for (devClass = 0; devClass < maxMppGrp; devClass++) -+ { -+ mppGroupType = mvBoardMppGroupTypeGet(devClass); -+ if(mppGroupType == MV_BOARD_TDM) -+ break; -+ } -+ -+ if(devClass == maxMppGrp) -+ return; /* TDM module not found */ -+ -+ /* TWSI init */ -+ slave.type = ADDR7_BIT; -+ slave.address = 0; -+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); -+ -+ /* Read MPP module ID */ -+ DB(mvOsPrintf("Board: twsi exp set\n")); -+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(devClass); -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ /* Offset is the first command after the address which indicate the register number to be read -+ in next operation */ -+ twsiSlave.offset = 3; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ if(mvBoardIdGet() == RD_88F6281A_ID) -+ { -+ muxVal = 0xc; -+ muxValMask = 0xf3; -+ } -+ -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ muxVal = (twsiVal & muxValMask) | muxVal; -+ -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) -+ { -+ mvOsPrintf("Board: twsi exp out val fail\n"); -+ return; -+ } -+ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); -+ -+ /* Change twsi exp to output */ -+ twsiSlave.offset = 7; -+ muxVal = 0xfe; -+ if(mvBoardIdGet() == RD_88F6281A_ID) -+ muxVal = 0xf3; -+ -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ muxVal = (twsiVal & muxVal); -+ -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) -+ { -+ mvOsPrintf("Board: twsi exp change to out fail\n"); -+ return; -+ } -+ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); -+ /* reset the line to 0 */ -+ twsiSlave.offset = 3; -+ muxVal = 0; -+ muxValMask = 1; -+ -+ if(mvBoardIdGet() == RD_88F6281A_ID) { -+ muxVal = 0x0; -+ muxValMask = 0xf3; -+ } -+ -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ muxVal = (twsiVal & muxValMask) | muxVal; -+ -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) -+ { -+ mvOsPrintf("Board: twsi exp out val fail\n"); -+ return; -+ } -+ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); -+ -+ mvOsDelay(20); -+ -+ /* set the line to 1 */ -+ twsiSlave.offset = 3; -+ muxVal = 1; -+ muxValMask = 1; -+ -+ if(mvBoardIdGet() == RD_88F6281A_ID) -+ { -+ muxVal = 0xc; -+ muxValMask = 0xf3; -+ if(chType) /* FXS - issue reset properly */ -+ { -+ MV_REG_BIT_SET(GPP_DATA_OUT_REG(1), MV_GPP12); -+ mvOsDelay(50); -+ MV_REG_BIT_RESET(GPP_DATA_OUT_REG(1), MV_GPP12); -+ } -+ else /* FXO - issue reset via TDM_CODEC_RST*/ -+ { -+ /* change MPP44 type to TDM_CODEC_RST(0x2) */ -+ MV_REG_WRITE(MPP_CONTROL_REG5, ((MV_REG_READ(MPP_CONTROL_REG5) & 0xFFF0FFFF) | BIT17)); -+ } -+ } -+ -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ muxVal = (twsiVal & muxValMask) | muxVal; -+ -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) -+ { -+ mvOsPrintf("Board: twsi exp out val fail\n"); -+ return; -+ } -+ -+ /* TBD - 5 channels */ -+#if defined(MV_TDM_5CHANNELS) -+ /* change MPP38 type to GPIO(0x0) & polarity for TDM_STROBE */ -+ MV_REG_WRITE(MPP_CONTROL_REG4, (MV_REG_READ(MPP_CONTROL_REG4) & 0xF0FFFFFF)); -+ mvGppPolaritySet(1, MV_GPP6, 0); -+ -+ twsiSlave.offset = 6; -+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(2); -+ -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ muxVal = (twsiVal & ~BIT2); -+ -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) -+ { -+ mvOsPrintf("Board: twsi exp change to out fail\n"); -+ return; -+ } -+ -+ -+ twsiSlave.offset = 2; -+ -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ muxVal = (twsiVal & ~BIT2); -+ -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) -+ { -+ mvOsPrintf("Board: twsi exp change to out fail\n"); -+ return; -+ } -+#endif -+ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); -+ -+ -+} -+/******************************************************************************* -+* mvBoardVoiceConnModeGet - return SLIC/DAA connection & interrupt modes -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+ -+MV_VOID mvBoardVoiceConnModeGet(MV_32* connMode, MV_32* irqMode) -+{ -+ switch(mvBoardIdGet()) -+ { -+ case RD_88F6281A_ID: -+ *connMode = DAISY_CHAIN_MODE; -+ *irqMode = INTERRUPT_TO_TDM; -+ break; -+ case DB_88F6281A_BP_ID: -+ *connMode = DUAL_CHIP_SELECT_MODE; -+ *irqMode = INTERRUPT_TO_TDM; -+ break; -+ case RD_88F6192A_ID: -+ *connMode = DUAL_CHIP_SELECT_MODE; -+ *irqMode = INTERRUPT_TO_TDM; -+ break; -+ case DB_88F6192A_BP_ID: -+ *connMode = DUAL_CHIP_SELECT_MODE; -+ *irqMode = INTERRUPT_TO_TDM; -+ break; -+ default: -+ *connMode = *irqMode = -1; -+ mvOsPrintf("mvBoardVoiceAssembleModeGet: TDM not supported(boardId=0x%x)\n",mvBoardIdGet()); -+ } -+ return; -+ -+} -+ -+/******************************************************************************* -+* mvBoardMppModuleTypePrint - print module detect -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_VOID mvBoardMppModuleTypePrint(MV_VOID) -+{ -+ -+ MV_BOARD_MPP_GROUP_CLASS devClass; -+ MV_BOARD_MPP_TYPE_CLASS mppGroupType; -+ MV_U32 devId; -+ MV_U32 maxMppGrp = 1; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ maxMppGrp = MV_6281_MPP_MAX_MODULE; -+ break; -+ case MV_6192_DEV_ID: -+ maxMppGrp = MV_6192_MPP_MAX_MODULE; -+ break; -+ case MV_6190_DEV_ID: -+ maxMppGrp = MV_6190_MPP_MAX_MODULE; -+ break; -+ case MV_6180_DEV_ID: -+ maxMppGrp = MV_6180_MPP_MAX_MODULE; -+ break; -+ } -+ -+ for (devClass = 0; devClass < maxMppGrp; devClass++) -+ { -+ mppGroupType = mvBoardMppGroupTypeGet(devClass); -+ -+ switch(mppGroupType) -+ { -+ case MV_BOARD_TDM: -+ if(devId != MV_6190_DEV_ID) -+ mvOsPrintf("Module %d is TDM\n", devClass); -+ break; -+ case MV_BOARD_AUDIO: -+ if(devId != MV_6190_DEV_ID) -+ mvOsPrintf("Module %d is AUDIO\n", devClass); -+ break; -+ case MV_BOARD_RGMII: -+ if(devId != MV_6190_DEV_ID) -+ mvOsPrintf("Module %d is RGMII\n", devClass); -+ break; -+ case MV_BOARD_GMII: -+ if(devId != MV_6190_DEV_ID) -+ mvOsPrintf("Module %d is GMII\n", devClass); -+ break; -+ case MV_BOARD_TS: -+ if(devId != MV_6190_DEV_ID) -+ mvOsPrintf("Module %d is TS\n", devClass); -+ break; -+ default: -+ break; -+ } -+ } -+} -+ -+/* Board devices API managments */ -+ -+/******************************************************************************* -+* mvBoardGetDeviceNumber - Get number of device of some type on the board -+* -+* DESCRIPTION: -+* -+* INPUT: -+* devType - The device type ( Flash,RTC , etc .. ) -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* If the device is found on the board the then the functions returns the -+* number of those devices else the function returns 0 -+* -+* -+*******************************************************************************/ -+MV_32 mvBoardGetDevicesNumber(MV_BOARD_DEV_CLASS devClass) -+{ -+ MV_U32 foundIndex=0,devNum; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardGetDeviceNumber:Board unknown.\n"); -+ return 0xFFFFFFFF; -+ -+ } -+ -+ for (devNum = START_DEV_CS; devNum < BOARD_INFO(boardId)->numBoardDeviceIf; devNum++) -+ { -+ if (BOARD_INFO(boardId)->pDevCsInfo[devNum].devClass == devClass) -+ { -+ foundIndex++; -+ } -+ } -+ -+ return foundIndex; -+ -+} -+ -+/******************************************************************************* -+* mvBoardGetDeviceBaseAddr - Get base address of a device existing on the board -+* -+* DESCRIPTION: -+* -+* INPUT: -+* devIndex - The device sequential number on the board -+* devType - The device type ( Flash,RTC , etc .. ) -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* If the device is found on the board the then the functions returns the -+* Base address else the function returns 0xffffffff -+* -+* -+*******************************************************************************/ -+MV_32 mvBoardGetDeviceBaseAddr(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) -+{ -+ MV_DEV_CS_INFO* devEntry; -+ devEntry = boardGetDevEntry(devNum,devClass); -+ if (devEntry != NULL) -+ { -+ return mvCpuIfTargetWinBaseLowGet(DEV_TO_TARGET(devEntry->deviceCS)); -+ -+ } -+ -+ return 0xFFFFFFFF; -+} -+ -+/******************************************************************************* -+* mvBoardGetDeviceBusWidth - Get Bus width of a device existing on the board -+* -+* DESCRIPTION: -+* -+* INPUT: -+* devIndex - The device sequential number on the board -+* devType - The device type ( Flash,RTC , etc .. ) -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* If the device is found on the board the then the functions returns the -+* Bus width else the function returns 0xffffffff -+* -+* -+*******************************************************************************/ -+MV_32 mvBoardGetDeviceBusWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) -+{ -+ MV_DEV_CS_INFO* devEntry; -+ -+ devEntry = boardGetDevEntry(devNum,devClass); -+ if (devEntry != NULL) -+ { -+ return 8; -+ } -+ -+ return 0xFFFFFFFF; -+ -+} -+ -+/******************************************************************************* -+* mvBoardGetDeviceWidth - Get dev width of a device existing on the board -+* -+* DESCRIPTION: -+* -+* INPUT: -+* devIndex - The device sequential number on the board -+* devType - The device type ( Flash,RTC , etc .. ) -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* If the device is found on the board the then the functions returns the -+* dev width else the function returns 0xffffffff -+* -+* -+*******************************************************************************/ -+MV_32 mvBoardGetDeviceWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) -+{ -+ MV_DEV_CS_INFO* devEntry; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("Board unknown.\n"); -+ return 0xFFFFFFFF; -+ } -+ -+ devEntry = boardGetDevEntry(devNum,devClass); -+ if (devEntry != NULL) -+ return devEntry->devWidth; -+ -+ return MV_ERROR; -+ -+} -+ -+/******************************************************************************* -+* mvBoardGetDeviceWinSize - Get the window size of a device existing on the board -+* -+* DESCRIPTION: -+* -+* INPUT: -+* devIndex - The device sequential number on the board -+* devType - The device type ( Flash,RTC , etc .. ) -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* If the device is found on the board the then the functions returns the -+* window size else the function returns 0xffffffff -+* -+* -+*******************************************************************************/ -+MV_32 mvBoardGetDeviceWinSize(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) -+{ -+ MV_DEV_CS_INFO* devEntry; -+ MV_U32 boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("Board unknown.\n"); -+ return 0xFFFFFFFF; -+ } -+ -+ devEntry = boardGetDevEntry(devNum,devClass); -+ if (devEntry != NULL) -+ { -+ return mvCpuIfTargetWinSizeGet(DEV_TO_TARGET(devEntry->deviceCS)); -+ } -+ -+ return 0xFFFFFFFF; -+} -+ -+ -+/******************************************************************************* -+* boardGetDevEntry - returns the entry pointer of a device on the board -+* -+* DESCRIPTION: -+* -+* INPUT: -+* devIndex - The device sequential number on the board -+* devType - The device type ( Flash,RTC , etc .. ) -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* If the device is found on the board the then the functions returns the -+* dev number else the function returns 0x0 -+* -+* -+*******************************************************************************/ -+static MV_DEV_CS_INFO* boardGetDevEntry(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) -+{ -+ MV_U32 foundIndex=0,devIndex; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("boardGetDevEntry: Board unknown.\n"); -+ return NULL; -+ -+ } -+ -+ for (devIndex = START_DEV_CS; devIndex < BOARD_INFO(boardId)->numBoardDeviceIf; devIndex++) -+ { -+ /* TBR */ -+ /*if (BOARD_INFO(boardId)->pDevCsInfo[devIndex].deviceCS == MV_BOOTDEVICE_INDEX) -+ continue;*/ -+ -+ if (BOARD_INFO(boardId)->pDevCsInfo[devIndex].devClass == devClass) -+ { -+ if (foundIndex == devNum) -+ { -+ return &(BOARD_INFO(boardId)->pDevCsInfo[devIndex]); -+ } -+ foundIndex++; -+ } -+ } -+ -+ /* device not found */ -+ return NULL; -+} -+ -+/* Get device CS number */ -+ -+MV_U32 boardGetDevCSNum(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) -+{ -+ MV_DEV_CS_INFO* devEntry; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("Board unknown.\n"); -+ return 0xFFFFFFFF; -+ -+ } -+ -+ -+ devEntry = boardGetDevEntry(devNum,devClass); -+ if (devEntry != NULL) -+ return devEntry->deviceCS; -+ -+ return 0xFFFFFFFF; -+ -+} -+ -+/******************************************************************************* -+* mvBoardRtcTwsiAddrTypeGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_U8 mvBoardRtcTwsiAddrTypeGet() -+{ -+ int i; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) -+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_RTC) -+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; -+ return (MV_ERROR); -+} -+ -+/******************************************************************************* -+* mvBoardRtcTwsiAddrGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_U8 mvBoardRtcTwsiAddrGet() -+{ -+ int i; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) -+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_RTC) -+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; -+ return (0xFF); -+} -+ -+/******************************************************************************* -+* mvBoardA2DTwsiAddrTypeGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_U8 mvBoardA2DTwsiAddrTypeGet() -+{ -+ int i; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) -+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_AUDIO_DEC) -+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; -+ return (MV_ERROR); -+} -+ -+/******************************************************************************* -+* mvBoardA2DTwsiAddrGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_U8 mvBoardA2DTwsiAddrGet() -+{ -+ int i; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) -+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_AUDIO_DEC) -+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; -+ return (0xFF); -+} -+ -+/******************************************************************************* -+* mvBoardTwsiExpAddrTypeGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_U8 mvBoardTwsiExpAddrTypeGet(MV_U32 index) -+{ -+ int i; -+ MV_U32 indexFound = 0; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) -+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_EXP) -+ { -+ if (indexFound == index) -+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; -+ else -+ indexFound++; -+ } -+ -+ return (MV_ERROR); -+} -+ -+/******************************************************************************* -+* mvBoardTwsiExpAddrGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_U8 mvBoardTwsiExpAddrGet(MV_U32 index) -+{ -+ int i; -+ MV_U32 indexFound = 0; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) -+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_EXP) -+ { -+ if (indexFound == index) -+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; -+ else -+ indexFound++; -+ } -+ -+ return (0xFF); -+} -+ -+ -+/******************************************************************************* -+* mvBoardTwsiSatRAddrTypeGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_U8 mvBoardTwsiSatRAddrTypeGet(MV_U32 index) -+{ -+ int i; -+ MV_U32 indexFound = 0; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) -+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_SATR) -+ { -+ if (indexFound == index) -+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; -+ else -+ indexFound++; -+ } -+ -+ return (MV_ERROR); -+} -+ -+/******************************************************************************* -+* mvBoardTwsiSatRAddrGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_U8 mvBoardTwsiSatRAddrGet(MV_U32 index) -+{ -+ int i; -+ MV_U32 indexFound = 0; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) -+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_SATR) -+ { -+ if (indexFound == index) -+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; -+ else -+ indexFound++; -+ } -+ -+ return (0xFF); -+} -+ -+/******************************************************************************* -+* mvBoardNandWidthGet - -+* -+* DESCRIPTION: Get the width of the first NAND device in byte. -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: 1, 2, 4 or MV_ERROR -+* -+* -+*******************************************************************************/ -+/* */ -+MV_32 mvBoardNandWidthGet(void) -+{ -+ MV_U32 devNum; -+ MV_U32 devWidth; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (devNum = START_DEV_CS; devNum < BOARD_INFO(boardId)->numBoardDeviceIf; devNum++) -+ { -+ devWidth = mvBoardGetDeviceWidth(devNum, BOARD_DEV_NAND_FLASH); -+ if (devWidth != MV_ERROR) -+ return (devWidth / 8); -+ } -+ -+ /* NAND wasn't found */ -+ return MV_ERROR; -+} -+ -+MV_U32 gBoardId = -1; -+ -+/******************************************************************************* -+* mvBoardIdGet - Get Board model -+* -+* DESCRIPTION: -+* This function returns board ID. -+* Board ID is 32bit word constructed of board model (16bit) and -+* board revision (16bit) in the following way: 0xMMMMRRRR. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit board ID number, '-1' if board is undefined. -+* -+*******************************************************************************/ -+MV_U32 mvBoardIdGet(MV_VOID) -+{ -+ MV_U32 tmpBoardId = -1; -+ -+ if(gBoardId == -1) -+ { -+ #if defined(DB_88F6281A) -+ tmpBoardId = DB_88F6281A_BP_ID; -+ #elif defined(RD_88F6281A) -+ tmpBoardId = RD_88F6281A_ID; -+ #elif defined(DB_88F6192A) -+ tmpBoardId = DB_88F6192A_BP_ID; -+ #elif defined(DB_88F6190A) -+ tmpBoardId = DB_88F6190A_BP_ID; -+ #elif defined(RD_88F6192A) -+ tmpBoardId = RD_88F6192A_ID; -+ #elif defined(RD_88F6190A) -+ tmpBoardId = RD_88F6190A_ID; -+ #elif defined(DB_88F6180A) -+ tmpBoardId = DB_88F6180A_BP_ID; -+ #elif defined(RD_88F6281A_PCAC) -+ tmpBoardId = RD_88F6281A_PCAC_ID; -+ #elif defined(RD_88F6281A_SHEEVA_PLUG) -+ tmpBoardId = SHEEVA_PLUG_ID; -+ #elif defined(DB_CUSTOMER) -+ tmpBoardId = DB_CUSTOMER_ID; -+ #endif -+ gBoardId = tmpBoardId; -+ } -+ -+ return gBoardId; -+} -+ -+ -+/******************************************************************************* -+* mvBoarModuleTypeGet - mvBoarModuleTypeGet -+* -+* DESCRIPTION: -+* -+* INPUT: -+* group num - MV_BOARD_MPP_GROUP_CLASS enum -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* module num - MV_BOARD_MODULE_CLASS enum -+* -+*******************************************************************************/ -+MV_BOARD_MODULE_ID_CLASS mvBoarModuleTypeGet(MV_BOARD_MPP_GROUP_CLASS devClass) -+{ -+ MV_TWSI_SLAVE twsiSlave; -+ MV_TWSI_ADDR slave; -+ MV_U8 data; -+ -+ /* TWSI init */ -+ slave.type = ADDR7_BIT; -+ slave.address = 0; -+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); -+ -+ /* Read MPP module ID */ -+ DB(mvOsPrintf("Board: Read MPP module ID\n")); -+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(devClass); -+ twsiSlave.slaveAddr.type = mvBoardTwsiExpAddrTypeGet(devClass); -+ twsiSlave.validOffset = MV_TRUE; -+ /* Offset is the first command after the address which indicate the register number to be read -+ in next operation */ -+ twsiSlave.offset = 0; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ -+ -+ if( MV_OK != mvTwsiRead (0, &twsiSlave, &data, 1) ) -+ { -+ DB(mvOsPrintf("Board: Read MPP module ID fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: Read MPP module ID succeded\n")); -+ -+ return data; -+} -+ -+/******************************************************************************* -+* mvBoarTwsiSatRGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* device num - one of three devices -+* reg num - 0 or 1 -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* reg value -+* -+*******************************************************************************/ -+MV_U8 mvBoarTwsiSatRGet(MV_U8 devNum, MV_U8 regNum) -+{ -+ MV_TWSI_SLAVE twsiSlave; -+ MV_TWSI_ADDR slave; -+ MV_U8 data; -+ -+ /* TWSI init */ -+ slave.type = ADDR7_BIT; -+ slave.address = 0; -+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); -+ -+ /* Read MPP module ID */ -+ DB(mvOsPrintf("Board: Read S@R device read\n")); -+ twsiSlave.slaveAddr.address = mvBoardTwsiSatRAddrGet(devNum); -+ twsiSlave.slaveAddr.type = mvBoardTwsiSatRAddrTypeGet(devNum); -+ twsiSlave.validOffset = MV_TRUE; -+ /* Use offset as command */ -+ twsiSlave.offset = regNum; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ if( MV_OK != mvTwsiRead (0, &twsiSlave, &data, 1) ) -+ { -+ DB(mvOsPrintf("Board: Read S@R fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: Read S@R succeded\n")); -+ -+ return data; -+} -+ -+/******************************************************************************* -+* mvBoarTwsiSatRSet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* devNum - one of three devices -+* regNum - 0 or 1 -+* regVal - value -+* -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* reg value -+* -+*******************************************************************************/ -+MV_STATUS mvBoarTwsiSatRSet(MV_U8 devNum, MV_U8 regNum, MV_U8 regVal) -+{ -+ MV_TWSI_SLAVE twsiSlave; -+ MV_TWSI_ADDR slave; -+ -+ /* TWSI init */ -+ slave.type = ADDR7_BIT; -+ slave.address = 0; -+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); -+ -+ /* Read MPP module ID */ -+ twsiSlave.slaveAddr.address = mvBoardTwsiSatRAddrGet(devNum); -+ twsiSlave.slaveAddr.type = mvBoardTwsiSatRAddrTypeGet(devNum); -+ twsiSlave.validOffset = MV_TRUE; -+ DB(mvOsPrintf("Board: Write S@R device addr %x, type %x, data %x\n", twsiSlave.slaveAddr.address,\ -+ twsiSlave.slaveAddr.type, regVal)); -+ /* Use offset as command */ -+ twsiSlave.offset = regNum; -+ twsiSlave.moreThen256 = MV_FALSE; -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, ®Val, 1) ) -+ { -+ DB(mvOsPrintf("Board: Write S@R fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: Write S@R succeded\n")); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvBoardSlicGpioPinGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_32 mvBoardSlicGpioPinGet(MV_U32 slicNum) -+{ -+ MV_U32 boardId; -+ boardId = mvBoardIdGet(); -+ -+ switch (boardId) -+ { -+ case DB_88F6281A_BP_ID: -+ case RD_88F6281A_ID: -+ default: -+ return MV_ERROR; -+ break; -+ -+ } -+} -+ -+/******************************************************************************* -+* mvBoardFanPowerControl - Turn on/off the fan power control on the RD-6281A -+* -+* DESCRIPTION: -+* -+* INPUT: -+* mode - MV_TRUE = on ; MV_FALSE = off -+* -+* OUTPUT: -+* MV_STATUS - MV_OK , MV_ERROR. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_STATUS mvBoardFanPowerControl(MV_BOOL mode) -+{ -+ -+ MV_U8 val = 1, twsiVal; -+ MV_TWSI_SLAVE twsiSlave; -+ MV_TWSI_ADDR slave; -+ -+ if(mvBoardIdGet() != RD_88F6281A_ID) -+ return MV_ERROR; -+ -+ /* TWSI init */ -+ slave.type = ADDR7_BIT; -+ slave.address = 0; -+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); -+ -+ /* Read MPP module ID */ -+ DB(mvOsPrintf("Board: twsi exp set\n")); -+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(1); -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ /* Offset is the first command after the address which indicate the register number to be read -+ in next operation */ -+ twsiSlave.offset = 3; -+ twsiSlave.moreThen256 = MV_FALSE; -+ if(mode == MV_TRUE) -+ val = 0x1; -+ else -+ val = 0; -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ val = (twsiVal & 0xfe) | val; -+ -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) -+ { -+ DB(mvOsPrintf("Board: twsi exp out val fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); -+ -+ /* Change twsi exp to output */ -+ twsiSlave.offset = 7; -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ val = (twsiVal & 0xfe); -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) -+ { -+ DB(mvOsPrintf("Board: twsi exp change to out fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvBoardHDDPowerControl - Turn on/off the HDD power control on the RD-6281A -+* -+* DESCRIPTION: -+* -+* INPUT: -+* mode - MV_TRUE = on ; MV_FALSE = off -+* -+* OUTPUT: -+* MV_STATUS - MV_OK , MV_ERROR. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_STATUS mvBoardHDDPowerControl(MV_BOOL mode) -+{ -+ -+ MV_U8 val = 1, twsiVal; -+ MV_TWSI_SLAVE twsiSlave; -+ MV_TWSI_ADDR slave; -+ -+ if(mvBoardIdGet() != RD_88F6281A_ID) -+ return MV_ERROR; -+ -+ /* TWSI init */ -+ slave.type = ADDR7_BIT; -+ slave.address = 0; -+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); -+ -+ /* Read MPP module ID */ -+ DB(mvOsPrintf("Board: twsi exp set\n")); -+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(1); -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ /* Offset is the first command after the address which indicate the register number to be read -+ in next operation */ -+ twsiSlave.offset = 3; -+ twsiSlave.moreThen256 = MV_FALSE; -+ if(mode == MV_TRUE) -+ val = 0x2; -+ else -+ val = 0; -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ val = (twsiVal & 0xfd) | val; -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) -+ { -+ DB(mvOsPrintf("Board: twsi exp out val fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); -+ -+ /* Change twsi exp to output */ -+ twsiSlave.offset = 7; -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ val = (twsiVal & 0xfd); -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) -+ { -+ DB(mvOsPrintf("Board: twsi exp change to out fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvBoardSDioWPControl - Turn on/off the SDIO WP on the RD-6281A -+* -+* DESCRIPTION: -+* -+* INPUT: -+* mode - MV_TRUE = on ; MV_FALSE = off -+* -+* OUTPUT: -+* MV_STATUS - MV_OK , MV_ERROR. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_STATUS mvBoardSDioWPControl(MV_BOOL mode) -+{ -+ -+ MV_U8 val = 1, twsiVal; -+ MV_TWSI_SLAVE twsiSlave; -+ MV_TWSI_ADDR slave; -+ -+ if(mvBoardIdGet() != RD_88F6281A_ID) -+ return MV_ERROR; -+ -+ /* TWSI init */ -+ slave.type = ADDR7_BIT; -+ slave.address = 0; -+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); -+ -+ /* Read MPP module ID */ -+ DB(mvOsPrintf("Board: twsi exp set\n")); -+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(0); -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ /* Offset is the first command after the address which indicate the register number to be read -+ in next operation */ -+ twsiSlave.offset = 3; -+ twsiSlave.moreThen256 = MV_FALSE; -+ if(mode == MV_TRUE) -+ val = 0x10; -+ else -+ val = 0; -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ val = (twsiVal & 0xef) | val; -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) -+ { -+ DB(mvOsPrintf("Board: twsi exp out val fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); -+ -+ /* Change twsi exp to output */ -+ twsiSlave.offset = 7; -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ val = (twsiVal & 0xef); -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) -+ { -+ DB(mvOsPrintf("Board: twsi exp change to out fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); -+ return MV_OK; -+} -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,376 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#ifndef __INCmvBoardEnvLibh -+#define __INCmvBoardEnvLibh -+ -+/* defines */ -+/* The below constant macros defines the board I2C EEPROM data offsets */ -+ -+ -+ -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "mvSysHwConfig.h" -+#include "boardEnv/mvBoardEnvSpec.h" -+ -+ -+/* DUART stuff for Tclk detection only */ -+#define DUART_BAUD_RATE 115200 -+#define MAX_CLOCK_MARGINE 5000000 /* Maximum detected clock margine */ -+ -+/* Voice devices assembly modes */ -+#define DAISY_CHAIN_MODE 1 -+#define DUAL_CHIP_SELECT_MODE 0 -+#define INTERRUPT_TO_MPP 1 -+#define INTERRUPT_TO_TDM 0 -+ -+ -+#define BOARD_ETH_PORT_NUM MV_ETH_MAX_PORTS -+#define BOARD_ETH_SWITCH_PORT_NUM 5 -+ -+#define MV_BOARD_MAX_USB_IF 1 -+#define MV_BOARD_MAX_MPP 7 -+#define MV_BOARD_NAME_LEN 0x20 -+ -+typedef struct _boardData -+{ -+ MV_U32 magic; -+ MV_U16 boardId; -+ MV_U8 boardVer; -+ MV_U8 boardRev; -+ MV_U32 reserved1; -+ MV_U32 reserved2; -+ -+}BOARD_DATA; -+ -+typedef enum _devBoardMppGroupClass -+{ -+ MV_BOARD_MPP_GROUP_1, -+ MV_BOARD_MPP_GROUP_2, -+ MV_BOARD_MAX_MPP_GROUP -+}MV_BOARD_MPP_GROUP_CLASS; -+ -+typedef enum _devBoardMppTypeClass -+{ -+ MV_BOARD_AUTO, -+ MV_BOARD_TDM, -+ MV_BOARD_AUDIO, -+ MV_BOARD_RGMII, -+ MV_BOARD_GMII, -+ MV_BOARD_TS, -+ MV_BOARD_MII, -+ MV_BOARD_OTHER -+}MV_BOARD_MPP_TYPE_CLASS; -+ -+typedef enum _devBoardModuleIdClass -+{ -+ MV_BOARD_MODULE_TDM_ID = 1, -+ MV_BOARD_MODULE_AUDIO_ID, -+ MV_BOARD_MODULE_RGMII_ID, -+ MV_BOARD_MODULE_GMII_ID, -+ MV_BOARD_MODULE_TS_ID, -+ MV_BOARD_MODULE_MII_ID, -+ MV_BOARD_MODULE_TDM_5CHAN_ID, -+ MV_BOARD_MODULE_OTHER_ID -+}MV_BOARD_MODULE_ID_CLASS; -+ -+typedef struct _boardMppTypeInfo -+{ -+ MV_BOARD_MPP_TYPE_CLASS boardMppGroup1; -+ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2; -+ -+}MV_BOARD_MPP_TYPE_INFO; -+ -+ -+typedef enum _devBoardClass -+{ -+ BOARD_DEV_NOR_FLASH, -+ BOARD_DEV_NAND_FLASH, -+ BOARD_DEV_SEVEN_SEG, -+ BOARD_DEV_FPGA, -+ BOARD_DEV_SRAM, -+ BOARD_DEV_SPI_FLASH, -+ BOARD_DEV_OTHER, -+}MV_BOARD_DEV_CLASS; -+ -+typedef enum _devTwsiBoardClass -+{ -+ BOARD_TWSI_RTC, -+ BOARD_DEV_TWSI_EXP, -+ BOARD_DEV_TWSI_SATR, -+ BOARD_TWSI_AUDIO_DEC, -+ BOARD_TWSI_OTHER -+}MV_BOARD_TWSI_CLASS; -+ -+typedef enum _devGppBoardClass -+{ -+ BOARD_GPP_RTC, -+ BOARD_GPP_MV_SWITCH, -+ BOARD_GPP_USB_VBUS, -+ BOARD_GPP_USB_VBUS_EN, -+ BOARD_GPP_USB_OC, -+ BOARD_GPP_USB_HOST_DEVICE, -+ BOARD_GPP_REF_CLCK, -+ BOARD_GPP_VOIP_SLIC, -+ BOARD_GPP_LIFELINE, -+ BOARD_GPP_BUTTON, -+ BOARD_GPP_TS_BUTTON_C, -+ BOARD_GPP_TS_BUTTON_U, -+ BOARD_GPP_TS_BUTTON_D, -+ BOARD_GPP_TS_BUTTON_L, -+ BOARD_GPP_TS_BUTTON_R, -+ BOARD_GPP_POWER_BUTTON, -+ BOARD_GPP_RESTOR_BUTTON, -+ BOARD_GPP_WPS_BUTTON, -+ BOARD_GPP_HDD0_POWER, -+ BOARD_GPP_HDD1_POWER, -+ BOARD_GPP_FAN_POWER, -+ BOARD_GPP_RESET, -+ BOARD_GPP_POWER_ON_LED, -+ BOARD_GPP_HDD_POWER, -+ BOARD_GPP_SDIO_POWER, -+ BOARD_GPP_SDIO_DETECT, -+ BOARD_GPP_SDIO_WP, -+ BOARD_GPP_SWITCH_PHY_INT, -+ BOARD_GPP_TSU_DIRCTION, -+ BOARD_GPP_OTHER -+}MV_BOARD_GPP_CLASS; -+ -+ -+typedef struct _devCsInfo -+{ -+ MV_U8 deviceCS; -+ MV_U32 params; -+ MV_U32 devClass; /* MV_BOARD_DEV_CLASS */ -+ MV_U8 devWidth; -+ -+}MV_DEV_CS_INFO; -+ -+ -+#define MV_BOARD_PHY_FORCE_10MB 0x0 -+#define MV_BOARD_PHY_FORCE_100MB 0x1 -+#define MV_BOARD_PHY_FORCE_1000MB 0x2 -+#define MV_BOARD_PHY_SPEED_AUTO 0x3 -+ -+typedef struct _boardSwitchInfo -+{ -+ MV_32 linkStatusIrq; -+ MV_32 qdPort[BOARD_ETH_SWITCH_PORT_NUM]; -+ MV_32 qdCpuPort; -+ MV_32 smiScanMode; /* 1 for SMI_MANUAL_MODE, 0 otherwise */ -+ MV_32 switchOnPort; -+ -+}MV_BOARD_SWITCH_INFO; -+ -+typedef struct _boardLedInfo -+{ -+ MV_U8 activeLedsNumber; -+ MV_U8 ledsPolarity; /* '0' or '1' to turn on led */ -+ MV_U8* gppPinNum; /* Pointer to GPP values */ -+ -+}MV_BOARD_LED_INFO; -+ -+typedef struct _boardGppInfo -+{ -+ MV_BOARD_GPP_CLASS devClass; -+ MV_U8 gppPinNum; -+ -+}MV_BOARD_GPP_INFO; -+ -+ -+typedef struct _boardTwsiInfo -+{ -+ MV_BOARD_TWSI_CLASS devClass; -+ MV_U8 twsiDevAddr; -+ MV_U8 twsiDevAddrType; -+ -+}MV_BOARD_TWSI_INFO; -+ -+ -+typedef enum _boardMacSpeed -+{ -+ BOARD_MAC_SPEED_10M, -+ BOARD_MAC_SPEED_100M, -+ BOARD_MAC_SPEED_1000M, -+ BOARD_MAC_SPEED_AUTO, -+ -+}MV_BOARD_MAC_SPEED; -+ -+typedef struct _boardMacInfo -+{ -+ MV_BOARD_MAC_SPEED boardMacSpeed; -+ MV_U8 boardEthSmiAddr; -+ -+}MV_BOARD_MAC_INFO; -+ -+typedef struct _boardMppInfo -+{ -+ MV_U32 mppGroup[MV_BOARD_MAX_MPP]; -+ -+}MV_BOARD_MPP_INFO; -+ -+typedef struct _boardInfo -+{ -+ char boardName[MV_BOARD_NAME_LEN]; -+ MV_U8 numBoardMppTypeValue; -+ MV_BOARD_MPP_TYPE_INFO* pBoardMppTypeValue; -+ MV_U8 numBoardMppConfigValue; -+ MV_BOARD_MPP_INFO* pBoardMppConfigValue; -+ MV_U32 intsGppMaskLow; -+ MV_U32 intsGppMaskHigh; -+ MV_U8 numBoardDeviceIf; -+ MV_DEV_CS_INFO* pDevCsInfo; -+ MV_U8 numBoardTwsiDev; -+ MV_BOARD_TWSI_INFO* pBoardTwsiDev; -+ MV_U8 numBoardMacInfo; -+ MV_BOARD_MAC_INFO* pBoardMacInfo; -+ MV_U8 numBoardGppInfo; -+ MV_BOARD_GPP_INFO* pBoardGppInfo; -+ MV_U8 activeLedsNumber; -+ MV_U8* pLedGppPin; -+ MV_U8 ledsPolarity; /* '0' or '1' to turn on led */ -+ /* GPP values */ -+ MV_U32 gppOutEnValLow; -+ MV_U32 gppOutEnValHigh; -+ MV_U32 gppOutValLow; -+ MV_U32 gppOutValHigh; -+ MV_U32 gppPolarityValLow; -+ MV_U32 gppPolarityValHigh; -+ -+ /* Switch Configuration */ -+ MV_BOARD_SWITCH_INFO* pSwitchInfo; -+}MV_BOARD_INFO; -+ -+ -+ -+MV_VOID mvBoardEnvInit(MV_VOID); -+MV_U32 mvBoardIdGet(MV_VOID); -+MV_U16 mvBoardModelGet(MV_VOID); -+MV_U16 mvBoardRevGet(MV_VOID); -+MV_STATUS mvBoardNameGet(char *pNameBuff); -+MV_32 mvBoardPhyAddrGet(MV_U32 ethPortNum); -+MV_BOARD_MAC_SPEED mvBoardMacSpeedGet(MV_U32 ethPortNum); -+MV_32 mvBoardLinkStatusIrqGet(MV_U32 ethPortNum); -+MV_32 mvBoardSwitchPortGet(MV_U32 ethPortNum, MV_U8 boardPortNum); -+MV_32 mvBoardSwitchCpuPortGet(MV_U32 ethPortNum); -+MV_32 mvBoardIsSwitchConnected(MV_U32 ethPortNum); -+MV_32 mvBoardSmiScanModeGet(MV_U32 ethPortNum); -+MV_BOOL mvBoardIsPortInSgmii(MV_U32 ethPortNum); -+MV_BOOL mvBoardIsPortInGmii(MV_VOID); -+MV_U32 mvBoardTclkGet(MV_VOID); -+MV_U32 mvBoardSysClkGet(MV_VOID); -+MV_U32 mvBoardDebugLedNumGet(MV_U32 boardId); -+MV_VOID mvBoardDebugLed(MV_U32 hexNum); -+MV_32 mvBoardMppGet(MV_U32 mppGroupNum); -+ -+MV_U8 mvBoardRtcTwsiAddrTypeGet(MV_VOID); -+MV_U8 mvBoardRtcTwsiAddrGet(MV_VOID); -+ -+MV_U8 mvBoardA2DTwsiAddrTypeGet(MV_VOID); -+MV_U8 mvBoardA2DTwsiAddrGet(MV_VOID); -+ -+MV_U8 mvBoardTwsiExpAddrGet(MV_U32 index); -+MV_U8 mvBoardTwsiSatRAddrTypeGet(MV_U32 index); -+MV_U8 mvBoardTwsiSatRAddrGet(MV_U32 index); -+MV_U8 mvBoardTwsiExpAddrTypeGet(MV_U32 index); -+MV_BOARD_MODULE_ID_CLASS mvBoarModuleTypeGet(MV_BOARD_MPP_GROUP_CLASS devClass); -+MV_BOARD_MPP_TYPE_CLASS mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass); -+MV_VOID mvBoardMppGroupTypeSet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass, -+ MV_BOARD_MPP_TYPE_CLASS mppGroupType); -+MV_VOID mvBoardMppGroupIdUpdate(MV_VOID); -+MV_VOID mvBoardMppMuxSet(MV_VOID); -+MV_VOID mvBoardTdmMppSet(MV_32 chType); -+MV_VOID mvBoardVoiceConnModeGet(MV_32* connMode, MV_32* irqMode); -+ -+MV_VOID mvBoardMppModuleTypePrint(MV_VOID); -+MV_VOID mvBoardReset(MV_VOID); -+MV_U8 mvBoarTwsiSatRGet(MV_U8 devNum, MV_U8 regNum); -+MV_STATUS mvBoarTwsiSatRSet(MV_U8 devNum, MV_U8 regNum, MV_U8 regVal); -+MV_BOOL mvBoardSpecInitGet(MV_U32* regOff, MV_U32* data); -+/* Board devices API managments */ -+MV_32 mvBoardGetDevicesNumber(MV_BOARD_DEV_CLASS devClass); -+MV_32 mvBoardGetDeviceBaseAddr(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); -+MV_32 mvBoardGetDeviceBusWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); -+MV_32 mvBoardGetDeviceWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); -+MV_32 mvBoardGetDeviceWinSize(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); -+MV_U32 boardGetDevCSNum(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); -+ -+/* Gpio Pin Connections API */ -+MV_32 mvBoardUSBVbusGpioPinGet(int devId); -+MV_32 mvBoardUSBVbusEnGpioPinGet(int devId); -+MV_U32 mvBoardPexBridgeIntPinGet(MV_U32 devNum, MV_U32 intPin); -+ -+MV_32 mvBoardResetGpioPinGet(MV_VOID); -+MV_32 mvBoardRTCGpioPinGet(MV_VOID); -+MV_32 mvBoardGpioIntMaskLowGet(MV_VOID); -+MV_32 mvBoardGpioIntMaskHighGet(MV_VOID); -+MV_32 mvBoardSlicGpioPinGet(MV_U32 slicNum); -+ -+MV_32 mvBoardSDIOGpioPinGet(MV_VOID); -+MV_STATUS mvBoardSDioWPControl(MV_BOOL mode); -+MV_32 mvBoarGpioPinNumGet(MV_BOARD_GPP_CLASS class, MV_U32 index); -+ -+MV_32 mvBoardNandWidthGet(void); -+MV_STATUS mvBoardFanPowerControl(MV_BOOL mode); -+MV_STATUS mvBoardHDDPowerControl(MV_BOOL mode); -+#endif /* __INCmvBoardEnvLibh */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,848 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#include "mvCommon.h" -+#include "mvBoardEnvLib.h" -+#include "mvBoardEnvSpec.h" -+#include "twsi/mvTwsi.h" -+ -+#define DB_88F6281A_BOARD_PCI_IF_NUM 0x0 -+#define DB_88F6281A_BOARD_TWSI_DEF_NUM 0x7 -+#define DB_88F6281A_BOARD_MAC_INFO_NUM 0x2 -+#define DB_88F6281A_BOARD_GPP_INFO_NUM 0x3 -+#define DB_88F6281A_BOARD_MPP_CONFIG_NUM 0x1 -+#define DB_88F6281A_BOARD_MPP_GROUP_TYPE_NUM 0x1 -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ #define DB_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1 -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ #define DB_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x2 -+#else -+ #define DB_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1 -+#endif -+#define DB_88F6281A_BOARD_DEBUG_LED_NUM 0x0 -+ -+ -+MV_BOARD_TWSI_INFO db88f6281AInfoBoardTwsiDev[] = -+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ -+ { -+ {BOARD_DEV_TWSI_EXP, 0x20, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_EXP, 0x21, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_SATR, 0x4D, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_SATR, 0x4E, ADDR7_BIT}, -+ {BOARD_TWSI_AUDIO_DEC, 0x4A, ADDR7_BIT} -+ }; -+ -+MV_BOARD_MAC_INFO db88f6281AInfoBoardMacInfo[] = -+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ -+ { -+ {BOARD_MAC_SPEED_AUTO, 0x8}, -+ {BOARD_MAC_SPEED_AUTO, 0x9} -+ }; -+ -+MV_BOARD_MPP_TYPE_INFO db88f6281AInfoBoardMppTypeInfo[] = -+ /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, -+ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ -+ {{MV_BOARD_AUTO, MV_BOARD_AUTO} -+ }; -+ -+MV_BOARD_GPP_INFO db88f6281AInfoBoardGppInfo[] = -+ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ -+ { -+ {BOARD_GPP_TSU_DIRCTION, 33} -+ /*muxed with TDM/Audio module via IOexpender -+ {BOARD_GPP_SDIO_DETECT, 38}, -+ {BOARD_GPP_USB_VBUS, 49}*/ -+ }; -+ -+MV_DEV_CS_INFO db88f6281AInfoBoardDeCsInfo[] = -+ /*{deviceCS, params, devType, devWidth}*/ -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ { -+ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ -+ {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ -+ }; -+#else -+ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ -+#endif -+ -+MV_BOARD_MPP_INFO db88f6281AInfoBoardMppConfigValue[] = -+ {{{ -+ DB_88F6281A_MPP0_7, -+ DB_88F6281A_MPP8_15, -+ DB_88F6281A_MPP16_23, -+ DB_88F6281A_MPP24_31, -+ DB_88F6281A_MPP32_39, -+ DB_88F6281A_MPP40_47, -+ DB_88F6281A_MPP48_55 -+ }}}; -+ -+ -+MV_BOARD_INFO db88f6281AInfo = { -+ "DB-88F6281A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ -+ DB_88F6281A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ -+ db88f6281AInfoBoardMppTypeInfo, -+ DB_88F6281A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ db88f6281AInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ 0, /* intsGppMaskHigh */ -+ DB_88F6281A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ db88f6281AInfoBoardDeCsInfo, -+ DB_88F6281A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ db88f6281AInfoBoardTwsiDev, -+ DB_88F6281A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ db88f6281AInfoBoardMacInfo, -+ DB_88F6281A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ db88f6281AInfoBoardGppInfo, -+ DB_88F6281A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ NULL, -+ 0, /* ledsPolarity */ -+ DB_88F6281A_OE_LOW, /* gppOutEnLow */ -+ DB_88F6281A_OE_HIGH, /* gppOutEnHigh */ -+ DB_88F6281A_OE_VAL_LOW, /* gppOutValLow */ -+ DB_88F6281A_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ BIT6, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+ -+#define RD_88F6281A_BOARD_PCI_IF_NUM 0x0 -+#define RD_88F6281A_BOARD_TWSI_DEF_NUM 0x2 -+#define RD_88F6281A_BOARD_MAC_INFO_NUM 0x2 -+#define RD_88F6281A_BOARD_GPP_INFO_NUM 0x5 -+#define RD_88F6281A_BOARD_MPP_GROUP_TYPE_NUM 0x1 -+#define RD_88F6281A_BOARD_MPP_CONFIG_NUM 0x1 -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ #define RD_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1 -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ #define RD_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x2 -+#else -+ #define RD_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1 -+#endif -+#define RD_88F6281A_BOARD_DEBUG_LED_NUM 0x0 -+ -+MV_BOARD_MAC_INFO rd88f6281AInfoBoardMacInfo[] = -+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ -+ {{BOARD_MAC_SPEED_1000M, 0xa}, -+ {BOARD_MAC_SPEED_AUTO, 0xb} -+ }; -+ -+MV_BOARD_SWITCH_INFO rd88f6281AInfoBoardSwitchInfo[] = -+ /* MV_32 linkStatusIrq, {MV_32 qdPort0, MV_32 qdPort1, MV_32 qdPort2, MV_32 qdPort3, MV_32 qdPort4}, -+ MV_32 qdCpuPort, MV_32 smiScanMode, MV_32 switchOnPort} */ -+ {{38, {0, 1, 2, 3, -1}, 5, 2, 0}, -+ {-1, {-1}, -1, -1, -1}}; -+ -+MV_BOARD_TWSI_INFO rd88f6281AInfoBoardTwsiDev[] = -+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ -+ { -+ {BOARD_DEV_TWSI_EXP, 0xFF, ADDR7_BIT}, /* dummy entry to align with modules indexes */ -+ {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT} -+ }; -+ -+MV_BOARD_MPP_TYPE_INFO rd88f6281AInfoBoardMppTypeInfo[] = -+ {{MV_BOARD_RGMII, MV_BOARD_TDM} -+ }; -+ -+MV_DEV_CS_INFO rd88f6281AInfoBoardDeCsInfo[] = -+ /*{deviceCS, params, devType, devWidth}*/ -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ { -+ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ -+ {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ -+ }; -+#else -+ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ -+#endif -+ -+MV_BOARD_GPP_INFO rd88f6281AInfoBoardGppInfo[] = -+ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ -+ {{BOARD_GPP_SDIO_DETECT, 28}, -+ {BOARD_GPP_USB_OC, 29}, -+ {BOARD_GPP_WPS_BUTTON, 35}, -+ {BOARD_GPP_MV_SWITCH, 38}, -+ {BOARD_GPP_USB_VBUS, 49} -+ }; -+ -+MV_BOARD_MPP_INFO rd88f6281AInfoBoardMppConfigValue[] = -+ {{{ -+ RD_88F6281A_MPP0_7, -+ RD_88F6281A_MPP8_15, -+ RD_88F6281A_MPP16_23, -+ RD_88F6281A_MPP24_31, -+ RD_88F6281A_MPP32_39, -+ RD_88F6281A_MPP40_47, -+ RD_88F6281A_MPP48_55 -+ }}}; -+ -+MV_BOARD_INFO rd88f6281AInfo = { -+ "RD-88F6281A", /* boardName[MAX_BOARD_NAME_LEN] */ -+ RD_88F6281A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ -+ rd88f6281AInfoBoardMppTypeInfo, -+ RD_88F6281A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ rd88f6281AInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ (1 << 3), /* intsGppMaskHigh */ -+ RD_88F6281A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ rd88f6281AInfoBoardDeCsInfo, -+ RD_88F6281A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ rd88f6281AInfoBoardTwsiDev, -+ RD_88F6281A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ rd88f6281AInfoBoardMacInfo, -+ RD_88F6281A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ rd88f6281AInfoBoardGppInfo, -+ RD_88F6281A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ NULL, -+ 0, /* ledsPolarity */ -+ RD_88F6281A_OE_LOW, /* gppOutEnLow */ -+ RD_88F6281A_OE_HIGH, /* gppOutEnHigh */ -+ RD_88F6281A_OE_VAL_LOW, /* gppOutValLow */ -+ RD_88F6281A_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ BIT6, /* gppPolarityValHigh */ -+ rd88f6281AInfoBoardSwitchInfo /* pSwitchInfo */ -+}; -+ -+ -+#define DB_88F6192A_BOARD_PCI_IF_NUM 0x0 -+#define DB_88F6192A_BOARD_TWSI_DEF_NUM 0x7 -+#define DB_88F6192A_BOARD_MAC_INFO_NUM 0x2 -+#define DB_88F6192A_BOARD_GPP_INFO_NUM 0x3 -+#define DB_88F6192A_BOARD_MPP_GROUP_TYPE_NUM 0x1 -+#define DB_88F6192A_BOARD_MPP_CONFIG_NUM 0x1 -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ #define DB_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x1 -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ #define DB_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x2 -+#else -+ #define DB_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x1 -+#endif -+#define DB_88F6192A_BOARD_DEBUG_LED_NUM 0x0 -+ -+MV_BOARD_TWSI_INFO db88f6192AInfoBoardTwsiDev[] = -+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ -+ { -+ {BOARD_DEV_TWSI_EXP, 0x20, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_EXP, 0x21, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_SATR, 0x4D, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_SATR, 0x4E, ADDR7_BIT}, -+ {BOARD_TWSI_AUDIO_DEC, 0x4A, ADDR7_BIT} -+ }; -+ -+MV_BOARD_MAC_INFO db88f6192AInfoBoardMacInfo[] = -+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ -+ { -+ {BOARD_MAC_SPEED_AUTO, 0x8}, -+ {BOARD_MAC_SPEED_AUTO, 0x9} -+ }; -+ -+MV_BOARD_MPP_TYPE_INFO db88f6192AInfoBoardMppTypeInfo[] = -+ /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, -+ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ -+ {{MV_BOARD_AUTO, MV_BOARD_OTHER} -+ }; -+ -+MV_DEV_CS_INFO db88f6192AInfoBoardDeCsInfo[] = -+ /*{deviceCS, params, devType, devWidth}*/ -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ { -+ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ -+ {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ -+ }; -+#else -+ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ -+#endif -+ -+MV_BOARD_GPP_INFO db88f6192AInfoBoardGppInfo[] = -+ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ -+ { -+ {BOARD_GPP_SDIO_WP, 20}, -+ {BOARD_GPP_USB_VBUS, 22}, -+ {BOARD_GPP_SDIO_DETECT, 23}, -+ }; -+ -+MV_BOARD_MPP_INFO db88f6192AInfoBoardMppConfigValue[] = -+ {{{ -+ DB_88F6192A_MPP0_7, -+ DB_88F6192A_MPP8_15, -+ DB_88F6192A_MPP16_23, -+ DB_88F6192A_MPP24_31, -+ DB_88F6192A_MPP32_35 -+ }}}; -+ -+MV_BOARD_INFO db88f6192AInfo = { -+ "DB-88F6192A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ -+ DB_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ -+ db88f6192AInfoBoardMppTypeInfo, -+ DB_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ db88f6192AInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ (1 << 3), /* intsGppMaskHigh */ -+ DB_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ db88f6192AInfoBoardDeCsInfo, -+ DB_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ db88f6192AInfoBoardTwsiDev, -+ DB_88F6192A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ db88f6192AInfoBoardMacInfo, -+ DB_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ db88f6192AInfoBoardGppInfo, -+ DB_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ NULL, -+ 0, /* ledsPolarity */ -+ DB_88F6192A_OE_LOW, /* gppOutEnLow */ -+ DB_88F6192A_OE_HIGH, /* gppOutEnHigh */ -+ DB_88F6192A_OE_VAL_LOW, /* gppOutValLow */ -+ DB_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ 0, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+#define DB_88F6190A_BOARD_MAC_INFO_NUM 0x1 -+ -+MV_BOARD_INFO db88f6190AInfo = { -+ "DB-88F6190A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ -+ DB_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ -+ db88f6192AInfoBoardMppTypeInfo, -+ DB_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ db88f6192AInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ (1 << 3), /* intsGppMaskHigh */ -+ DB_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ db88f6192AInfoBoardDeCsInfo, -+ DB_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ db88f6192AInfoBoardTwsiDev, -+ DB_88F6190A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ db88f6192AInfoBoardMacInfo, -+ DB_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ db88f6192AInfoBoardGppInfo, -+ DB_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ NULL, -+ 0, /* ledsPolarity */ -+ DB_88F6192A_OE_LOW, /* gppOutEnLow */ -+ DB_88F6192A_OE_HIGH, /* gppOutEnHigh */ -+ DB_88F6192A_OE_VAL_LOW, /* gppOutValLow */ -+ DB_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ 0, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+#define RD_88F6192A_BOARD_PCI_IF_NUM 0x0 -+#define RD_88F6192A_BOARD_TWSI_DEF_NUM 0x0 -+#define RD_88F6192A_BOARD_MAC_INFO_NUM 0x1 -+#define RD_88F6192A_BOARD_GPP_INFO_NUM 0xE -+#define RD_88F6192A_BOARD_MPP_GROUP_TYPE_NUM 0x1 -+#define RD_88F6192A_BOARD_MPP_CONFIG_NUM 0x1 -+#define RD_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x1 -+#define RD_88F6192A_BOARD_DEBUG_LED_NUM 0x3 -+ -+MV_U8 rd88f6192AInfoBoardDebugLedIf[] = -+ {17, 28, 29}; -+ -+MV_BOARD_MAC_INFO rd88f6192AInfoBoardMacInfo[] = -+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ -+ {{BOARD_MAC_SPEED_AUTO, 0x8} -+ }; -+ -+MV_BOARD_MPP_TYPE_INFO rd88f6192AInfoBoardMppTypeInfo[] = -+ /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, -+ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ -+ {{MV_BOARD_OTHER, MV_BOARD_OTHER} -+ }; -+ -+MV_DEV_CS_INFO rd88f6192AInfoBoardDeCsInfo[] = -+ /*{deviceCS, params, devType, devWidth}*/ -+ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ -+ -+MV_BOARD_GPP_INFO rd88f6192AInfoBoardGppInfo[] = -+ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ -+ { -+ {BOARD_GPP_USB_VBUS_EN, 10}, -+ {BOARD_GPP_USB_HOST_DEVICE, 11}, -+ {BOARD_GPP_RESET, 14}, -+ {BOARD_GPP_POWER_ON_LED, 15}, -+ {BOARD_GPP_HDD_POWER, 16}, -+ {BOARD_GPP_WPS_BUTTON, 24}, -+ {BOARD_GPP_TS_BUTTON_C, 25}, -+ {BOARD_GPP_USB_VBUS, 26}, -+ {BOARD_GPP_USB_OC, 27}, -+ {BOARD_GPP_TS_BUTTON_U, 30}, -+ {BOARD_GPP_TS_BUTTON_R, 31}, -+ {BOARD_GPP_TS_BUTTON_L, 32}, -+ {BOARD_GPP_TS_BUTTON_D, 34}, -+ {BOARD_GPP_FAN_POWER, 35} -+ }; -+ -+MV_BOARD_MPP_INFO rd88f6192AInfoBoardMppConfigValue[] = -+ {{{ -+ RD_88F6192A_MPP0_7, -+ RD_88F6192A_MPP8_15, -+ RD_88F6192A_MPP16_23, -+ RD_88F6192A_MPP24_31, -+ RD_88F6192A_MPP32_35 -+ }}}; -+ -+MV_BOARD_INFO rd88f6192AInfo = { -+ "RD-88F6192A-NAS", /* boardName[MAX_BOARD_NAME_LEN] */ -+ RD_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ -+ rd88f6192AInfoBoardMppTypeInfo, -+ RD_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ rd88f6192AInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ (1 << 3), /* intsGppMaskHigh */ -+ RD_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ rd88f6192AInfoBoardDeCsInfo, -+ RD_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ NULL, -+ RD_88F6192A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ rd88f6192AInfoBoardMacInfo, -+ RD_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ rd88f6192AInfoBoardGppInfo, -+ RD_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ rd88f6192AInfoBoardDebugLedIf, -+ 0, /* ledsPolarity */ -+ RD_88F6192A_OE_LOW, /* gppOutEnLow */ -+ RD_88F6192A_OE_HIGH, /* gppOutEnHigh */ -+ RD_88F6192A_OE_VAL_LOW, /* gppOutValLow */ -+ RD_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ 0, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+MV_BOARD_INFO rd88f6190AInfo = { -+ "RD-88F6190A-NAS", /* boardName[MAX_BOARD_NAME_LEN] */ -+ RD_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ -+ rd88f6192AInfoBoardMppTypeInfo, -+ RD_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ rd88f6192AInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ (1 << 3), /* intsGppMaskHigh */ -+ RD_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ rd88f6192AInfoBoardDeCsInfo, -+ RD_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ NULL, -+ RD_88F6192A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ rd88f6192AInfoBoardMacInfo, -+ RD_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ rd88f6192AInfoBoardGppInfo, -+ RD_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ rd88f6192AInfoBoardDebugLedIf, -+ 0, /* ledsPolarity */ -+ RD_88F6192A_OE_LOW, /* gppOutEnLow */ -+ RD_88F6192A_OE_HIGH, /* gppOutEnHigh */ -+ RD_88F6192A_OE_VAL_LOW, /* gppOutValLow */ -+ RD_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ 0, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+#define DB_88F6180A_BOARD_PCI_IF_NUM 0x0 -+#define DB_88F6180A_BOARD_TWSI_DEF_NUM 0x5 -+#define DB_88F6180A_BOARD_MAC_INFO_NUM 0x1 -+#define DB_88F6180A_BOARD_GPP_INFO_NUM 0x0 -+#define DB_88F6180A_BOARD_MPP_GROUP_TYPE_NUM 0x2 -+#define DB_88F6180A_BOARD_MPP_CONFIG_NUM 0x1 -+#define DB_88F6180A_BOARD_DEVICE_CONFIG_NUM 0x1 -+#define DB_88F6180A_BOARD_DEBUG_LED_NUM 0x0 -+ -+MV_BOARD_TWSI_INFO db88f6180AInfoBoardTwsiDev[] = -+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ -+ { -+ {BOARD_DEV_TWSI_EXP, 0x20, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_EXP, 0x21, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, -+ {BOARD_TWSI_AUDIO_DEC, 0x4A, ADDR7_BIT} -+ }; -+ -+MV_BOARD_MAC_INFO db88f6180AInfoBoardMacInfo[] = -+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ -+ {{BOARD_MAC_SPEED_AUTO, 0x8} -+ }; -+ -+MV_BOARD_GPP_INFO db88f6180AInfoBoardGppInfo[] = -+ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ -+ { -+ /* Muxed with TDM/Audio module via IOexpender -+ {BOARD_GPP_USB_VBUS, 6} */ -+ }; -+ -+MV_BOARD_MPP_TYPE_INFO db88f6180AInfoBoardMppTypeInfo[] = -+ /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, -+ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ -+ {{MV_BOARD_OTHER, MV_BOARD_AUTO} -+ }; -+ -+MV_DEV_CS_INFO db88f6180AInfoBoardDeCsInfo[] = -+ /*{deviceCS, params, devType, devWidth}*/ -+#if defined(MV_NAND_BOOT) -+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ -+#else -+ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ -+#endif -+ -+MV_BOARD_MPP_INFO db88f6180AInfoBoardMppConfigValue[] = -+ {{{ -+ DB_88F6180A_MPP0_7, -+ DB_88F6180A_MPP8_15, -+ DB_88F6180A_MPP16_23, -+ DB_88F6180A_MPP24_31, -+ DB_88F6180A_MPP32_39, -+ DB_88F6180A_MPP40_44 -+ }}}; -+ -+MV_BOARD_INFO db88f6180AInfo = { -+ "DB-88F6180A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ -+ DB_88F6180A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ -+ db88f6180AInfoBoardMppTypeInfo, -+ DB_88F6180A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ db88f6180AInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ 0, /* intsGppMaskHigh */ -+ DB_88F6180A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ db88f6180AInfoBoardDeCsInfo, -+ DB_88F6180A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ db88f6180AInfoBoardTwsiDev, -+ DB_88F6180A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ db88f6180AInfoBoardMacInfo, -+ DB_88F6180A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ NULL, -+ DB_88F6180A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ NULL, -+ 0, /* ledsPolarity */ -+ DB_88F6180A_OE_LOW, /* gppOutEnLow */ -+ DB_88F6180A_OE_HIGH, /* gppOutEnHigh */ -+ DB_88F6180A_OE_VAL_LOW, /* gppOutValLow */ -+ DB_88F6180A_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ 0, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+ -+#define RD_88F6281A_PCAC_BOARD_PCI_IF_NUM 0x0 -+#define RD_88F6281A_PCAC_BOARD_TWSI_DEF_NUM 0x1 -+#define RD_88F6281A_PCAC_BOARD_MAC_INFO_NUM 0x1 -+#define RD_88F6281A_PCAC_BOARD_GPP_INFO_NUM 0x0 -+#define RD_88F6281A_PCAC_BOARD_MPP_GROUP_TYPE_NUM 0x1 -+#define RD_88F6281A_PCAC_BOARD_MPP_CONFIG_NUM 0x1 -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ #define RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM 0x1 -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ #define RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM 0x2 -+#else -+ #define RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM 0x1 -+#endif -+#define RD_88F6281A_PCAC_BOARD_DEBUG_LED_NUM 0x4 -+ -+MV_U8 rd88f6281APcacInfoBoardDebugLedIf[] = -+ {38, 39, 40, 41}; -+ -+MV_BOARD_MAC_INFO rd88f6281APcacInfoBoardMacInfo[] = -+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ -+ {{BOARD_MAC_SPEED_AUTO, 0x8} -+ }; -+ -+MV_BOARD_TWSI_INFO rd88f6281APcacInfoBoardTwsiDev[] = -+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ -+ { -+ {BOARD_TWSI_OTHER, 0xa7, ADDR7_BIT} -+ }; -+ -+MV_BOARD_MPP_TYPE_INFO rd88f6281APcacInfoBoardMppTypeInfo[] = -+ {{MV_BOARD_OTHER, MV_BOARD_OTHER} -+ }; -+ -+MV_DEV_CS_INFO rd88f6281APcacInfoBoardDeCsInfo[] = -+ /*{deviceCS, params, devType, devWidth}*/ -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ { -+ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ -+ {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ -+ }; -+#else -+ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ -+#endif -+ -+MV_BOARD_MPP_INFO rd88f6281APcacInfoBoardMppConfigValue[] = -+ {{{ -+ RD_88F6281A_PCAC_MPP0_7, -+ RD_88F6281A_PCAC_MPP8_15, -+ RD_88F6281A_PCAC_MPP16_23, -+ RD_88F6281A_PCAC_MPP24_31, -+ RD_88F6281A_PCAC_MPP32_39, -+ RD_88F6281A_PCAC_MPP40_47, -+ RD_88F6281A_PCAC_MPP48_55 -+ }}}; -+ -+MV_BOARD_INFO rd88f6281APcacInfo = { -+ "RD-88F6281A-PCAC", /* boardName[MAX_BOARD_NAME_LEN] */ -+ RD_88F6281A_PCAC_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ -+ rd88f6281APcacInfoBoardMppTypeInfo, -+ RD_88F6281A_PCAC_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ rd88f6281APcacInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ (1 << 3), /* intsGppMaskHigh */ -+ RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ rd88f6281APcacInfoBoardDeCsInfo, -+ RD_88F6281A_PCAC_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ rd88f6281APcacInfoBoardTwsiDev, -+ RD_88F6281A_PCAC_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ rd88f6281APcacInfoBoardMacInfo, -+ RD_88F6281A_PCAC_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ 0, -+ RD_88F6281A_PCAC_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ NULL, -+ 0, /* ledsPolarity */ -+ RD_88F6281A_PCAC_OE_LOW, /* gppOutEnLow */ -+ RD_88F6281A_PCAC_OE_HIGH, /* gppOutEnHigh */ -+ RD_88F6281A_PCAC_OE_VAL_LOW, /* gppOutValLow */ -+ RD_88F6281A_PCAC_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ 0, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+ -+/* 6281 Sheeva Plug*/ -+ -+#define SHEEVA_PLUG_BOARD_PCI_IF_NUM 0x0 -+#define SHEEVA_PLUG_BOARD_TWSI_DEF_NUM 0x0 -+#define SHEEVA_PLUG_BOARD_MAC_INFO_NUM 0x1 -+#define SHEEVA_PLUG_BOARD_GPP_INFO_NUM 0x0 -+#define SHEEVA_PLUG_BOARD_MPP_GROUP_TYPE_NUN 0x1 -+#define SHEEVA_PLUG_BOARD_MPP_CONFIG_NUM 0x1 -+#define SHEEVA_PLUG_BOARD_DEVICE_CONFIG_NUM 0x1 -+#define SHEEVA_PLUG_BOARD_DEBUG_LED_NUM 0x1 -+ -+MV_U8 sheevaPlugInfoBoardDebugLedIf[] = -+ {49}; -+ -+MV_BOARD_MAC_INFO sheevaPlugInfoBoardMacInfo[] = -+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ -+ {{BOARD_MAC_SPEED_AUTO, 0x0}}; -+ -+MV_BOARD_TWSI_INFO sheevaPlugInfoBoardTwsiDev[] = -+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ -+ {{BOARD_TWSI_OTHER, 0x0, ADDR7_BIT}}; -+ -+MV_BOARD_MPP_TYPE_INFO sheevaPlugInfoBoardMppTypeInfo[] = -+ {{MV_BOARD_OTHER, MV_BOARD_OTHER} -+ }; -+ -+MV_DEV_CS_INFO sheevaPlugInfoBoardDeCsInfo[] = -+ /*{deviceCS, params, devType, devWidth}*/ -+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ -+ -+MV_BOARD_MPP_INFO sheevaPlugInfoBoardMppConfigValue[] = -+ {{{ -+ RD_SHEEVA_PLUG_MPP0_7, -+ RD_SHEEVA_PLUG_MPP8_15, -+ RD_SHEEVA_PLUG_MPP16_23, -+ RD_SHEEVA_PLUG_MPP24_31, -+ RD_SHEEVA_PLUG_MPP32_39, -+ RD_SHEEVA_PLUG_MPP40_47, -+ RD_SHEEVA_PLUG_MPP48_55 -+ }}}; -+ -+MV_BOARD_INFO sheevaPlugInfo = { -+ "SHEEVA PLUG", /* boardName[MAX_BOARD_NAME_LEN] */ -+ SHEEVA_PLUG_BOARD_MPP_GROUP_TYPE_NUN, /* numBoardMppGroupType */ -+ sheevaPlugInfoBoardMppTypeInfo, -+ SHEEVA_PLUG_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ sheevaPlugInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ 0, /* intsGppMaskHigh */ -+ SHEEVA_PLUG_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ sheevaPlugInfoBoardDeCsInfo, -+ SHEEVA_PLUG_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ sheevaPlugInfoBoardTwsiDev, -+ SHEEVA_PLUG_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ sheevaPlugInfoBoardMacInfo, -+ SHEEVA_PLUG_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ 0, -+ SHEEVA_PLUG_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ sheevaPlugInfoBoardDebugLedIf, -+ 0, /* ledsPolarity */ -+ RD_SHEEVA_PLUG_OE_LOW, /* gppOutEnLow */ -+ RD_SHEEVA_PLUG_OE_HIGH, /* gppOutEnHigh */ -+ RD_SHEEVA_PLUG_OE_VAL_LOW, /* gppOutValLow */ -+ RD_SHEEVA_PLUG_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ 0, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+/* Customer specific board place holder*/ -+ -+#define DB_CUSTOMER_BOARD_PCI_IF_NUM 0x0 -+#define DB_CUSTOMER_BOARD_TWSI_DEF_NUM 0x0 -+#define DB_CUSTOMER_BOARD_MAC_INFO_NUM 0x0 -+#define DB_CUSTOMER_BOARD_GPP_INFO_NUM 0x0 -+#define DB_CUSTOMER_BOARD_MPP_GROUP_TYPE_NUN 0x0 -+#define DB_CUSTOMER_BOARD_MPP_CONFIG_NUM 0x0 -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ #define DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM 0x0 -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ #define DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM 0x0 -+#else -+ #define DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM 0x0 -+#endif -+#define DB_CUSTOMER_BOARD_DEBUG_LED_NUM 0x0 -+ -+MV_U8 dbCustomerInfoBoardDebugLedIf[] = -+ {0}; -+ -+MV_BOARD_MAC_INFO dbCustomerInfoBoardMacInfo[] = -+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ -+ {{BOARD_MAC_SPEED_AUTO, 0x0}}; -+ -+MV_BOARD_TWSI_INFO dbCustomerInfoBoardTwsiDev[] = -+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ -+ {{BOARD_TWSI_OTHER, 0x0, ADDR7_BIT}}; -+ -+MV_BOARD_MPP_TYPE_INFO dbCustomerInfoBoardMppTypeInfo[] = -+ {{MV_BOARD_OTHER, MV_BOARD_OTHER} -+ }; -+ -+MV_DEV_CS_INFO dbCustomerInfoBoardDeCsInfo[] = -+ /*{deviceCS, params, devType, devWidth}*/ -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ { -+ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ -+ {2, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ -+ }; -+#else -+ {{2, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ -+#endif -+ -+MV_BOARD_MPP_INFO dbCustomerInfoBoardMppConfigValue[] = -+ {{{ -+ DB_CUSTOMER_MPP0_7, -+ DB_CUSTOMER_MPP8_15, -+ DB_CUSTOMER_MPP16_23, -+ DB_CUSTOMER_MPP24_31, -+ DB_CUSTOMER_MPP32_39, -+ DB_CUSTOMER_MPP40_47, -+ DB_CUSTOMER_MPP48_55 -+ }}}; -+ -+MV_BOARD_INFO dbCustomerInfo = { -+ "DB-CUSTOMER", /* boardName[MAX_BOARD_NAME_LEN] */ -+ DB_CUSTOMER_BOARD_MPP_GROUP_TYPE_NUN, /* numBoardMppGroupType */ -+ dbCustomerInfoBoardMppTypeInfo, -+ DB_CUSTOMER_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ dbCustomerInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ 0, /* intsGppMaskHigh */ -+ DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ dbCustomerInfoBoardDeCsInfo, -+ DB_CUSTOMER_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ dbCustomerInfoBoardTwsiDev, -+ DB_CUSTOMER_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ dbCustomerInfoBoardMacInfo, -+ DB_CUSTOMER_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ 0, -+ DB_CUSTOMER_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ NULL, -+ 0, /* ledsPolarity */ -+ DB_CUSTOMER_OE_LOW, /* gppOutEnLow */ -+ DB_CUSTOMER_OE_HIGH, /* gppOutEnHigh */ -+ DB_CUSTOMER_OE_VAL_LOW, /* gppOutValLow */ -+ DB_CUSTOMER_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ 0, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+MV_BOARD_INFO* boardInfoTbl[] = { -+ &db88f6281AInfo, -+ &rd88f6281AInfo, -+ &db88f6192AInfo, -+ &rd88f6192AInfo, -+ &db88f6180AInfo, -+ &db88f6190AInfo, -+ &rd88f6190AInfo, -+ &rd88f6281APcacInfo, -+ &dbCustomerInfo, -+ &sheevaPlugInfo -+ }; -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,262 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvBoardEnvSpech -+#define __INCmvBoardEnvSpech -+ -+#include "mvSysHwConfig.h" -+ -+ -+/* For future use */ -+#define BD_ID_DATA_START_OFFS 0x0 -+#define BD_DETECT_SEQ_OFFS 0x0 -+#define BD_SYS_NUM_OFFS 0x4 -+#define BD_NAME_OFFS 0x8 -+ -+/* I2C bus addresses */ -+#define MV_BOARD_CTRL_I2C_ADDR 0x0 /* Controller slave addr */ -+#define MV_BOARD_CTRL_I2C_ADDR_TYPE ADDR7_BIT -+#define MV_BOARD_DIMM0_I2C_ADDR 0x56 -+#define MV_BOARD_DIMM0_I2C_ADDR_TYPE ADDR7_BIT -+#define MV_BOARD_DIMM1_I2C_ADDR 0x54 -+#define MV_BOARD_DIMM1_I2C_ADDR_TYPE ADDR7_BIT -+#define MV_BOARD_EEPROM_I2C_ADDR 0x51 -+#define MV_BOARD_EEPROM_I2C_ADDR_TYPE ADDR7_BIT -+#define MV_BOARD_MAIN_EEPROM_I2C_ADDR 0x50 -+#define MV_BOARD_MAIN_EEPROM_I2C_ADDR_TYPE ADDR7_BIT -+#define MV_BOARD_MUX_I2C_ADDR_ENTRY 0x2 -+#define MV_BOARD_DIMM_I2C_CHANNEL 0x0 -+ -+#define BOOT_FLASH_INDEX 0 -+#define MAIN_FLASH_INDEX 1 -+ -+#define BOARD_ETH_START_PORT_NUM 0 -+ -+/* Supported clocks */ -+#define MV_BOARD_TCLK_100MHZ 100000000 -+#define MV_BOARD_TCLK_125MHZ 125000000 -+#define MV_BOARD_TCLK_133MHZ 133333333 -+#define MV_BOARD_TCLK_150MHZ 150000000 -+#define MV_BOARD_TCLK_166MHZ 166666667 -+#define MV_BOARD_TCLK_200MHZ 200000000 -+ -+#define MV_BOARD_SYSCLK_100MHZ 100000000 -+#define MV_BOARD_SYSCLK_125MHZ 125000000 -+#define MV_BOARD_SYSCLK_133MHZ 133333333 -+#define MV_BOARD_SYSCLK_150MHZ 150000000 -+#define MV_BOARD_SYSCLK_166MHZ 166666667 -+#define MV_BOARD_SYSCLK_200MHZ 200000000 -+#define MV_BOARD_SYSCLK_233MHZ 233333333 -+#define MV_BOARD_SYSCLK_250MHZ 250000000 -+#define MV_BOARD_SYSCLK_267MHZ 266666667 -+#define MV_BOARD_SYSCLK_300MHZ 300000000 -+#define MV_BOARD_SYSCLK_333MHZ 333333334 -+#define MV_BOARD_SYSCLK_400MHZ 400000000 -+ -+#define MV_BOARD_REFCLK_25MHZ 25000000 -+ -+/* Board specific */ -+/* =============================== */ -+ -+/* boards ID numbers */ -+ -+#define BOARD_ID_BASE 0x0 -+ -+/* New board ID numbers */ -+#define DB_88F6281A_BP_ID (BOARD_ID_BASE) -+#define DB_88F6281_BP_MLL_ID 1680 -+#define RD_88F6281A_ID (BOARD_ID_BASE+0x1) -+#define RD_88F6281_MLL_ID 1682 -+#define DB_88F6192A_BP_ID (BOARD_ID_BASE+0x2) -+#define RD_88F6192A_ID (BOARD_ID_BASE+0x3) -+#define RD_88F6192_MLL_ID 1681 -+#define DB_88F6180A_BP_ID (BOARD_ID_BASE+0x4) -+#define DB_88F6190A_BP_ID (BOARD_ID_BASE+0x5) -+#define RD_88F6190A_ID (BOARD_ID_BASE+0x6) -+#define RD_88F6281A_PCAC_ID (BOARD_ID_BASE+0x7) -+#define DB_CUSTOMER_ID (BOARD_ID_BASE+0x8) -+#define SHEEVA_PLUG_ID (BOARD_ID_BASE+0x9) -+#define MV_MAX_BOARD_ID (SHEEVA_PLUG_ID + 1) -+ -+/* DB-88F6281A-BP */ -+#if defined(MV_NAND) -+ #define DB_88F6281A_MPP0_7 0x21111111 -+#else -+ #define DB_88F6281A_MPP0_7 0x21112220 -+#endif -+#define DB_88F6281A_MPP8_15 0x11113311 -+#define DB_88F6281A_MPP16_23 0x00551111 -+#define DB_88F6281A_MPP24_31 0x00000000 -+#define DB_88F6281A_MPP32_39 0x00000000 -+#define DB_88F6281A_MPP40_47 0x00000000 -+#define DB_88F6281A_MPP48_55 0x00000000 -+#define DB_88F6281A_OE_LOW 0x0 -+#if defined(MV_TDM_5CHANNELS) -+ #define DB_88F6281A_OE_HIGH (BIT6) -+#else -+#define DB_88F6281A_OE_HIGH 0x0 -+#endif -+#define DB_88F6281A_OE_VAL_LOW 0x0 -+#define DB_88F6281A_OE_VAL_HIGH 0x0 -+ -+/* RD-88F6281A */ -+#if defined(MV_NAND) -+ #define RD_88F6281A_MPP0_7 0x21111111 -+#else -+ #define RD_88F6281A_MPP0_7 0x21112220 -+#endif -+#define RD_88F6281A_MPP8_15 0x11113311 -+#define RD_88F6281A_MPP16_23 0x33331111 -+#define RD_88F6281A_MPP24_31 0x33003333 -+#define RD_88F6281A_MPP32_39 0x20440533 -+#define RD_88F6281A_MPP40_47 0x22202222 -+#define RD_88F6281A_MPP48_55 0x00000002 -+#define RD_88F6281A_OE_LOW (BIT28 | BIT29) -+#define RD_88F6281A_OE_HIGH (BIT3 | BIT6 | BIT17) -+#define RD_88F6281A_OE_VAL_LOW 0x0 -+#define RD_88F6281A_OE_VAL_HIGH 0x0 -+ -+/* DB-88F6192A-BP */ -+#if defined(MV_NAND) -+ #define DB_88F6192A_MPP0_7 0x21111111 -+#else -+ #define DB_88F6192A_MPP0_7 0x21112220 -+#endif -+#define DB_88F6192A_MPP8_15 0x11113311 -+#define DB_88F6192A_MPP16_23 0x00501111 -+#define DB_88F6192A_MPP24_31 0x00000000 -+#define DB_88F6192A_MPP32_35 0x00000000 -+#define DB_88F6192A_OE_LOW (BIT22 | BIT23) -+#define DB_88F6192A_OE_HIGH 0x0 -+#define DB_88F6192A_OE_VAL_LOW 0x0 -+#define DB_88F6192A_OE_VAL_HIGH 0x0 -+ -+/* RD-88F6192A */ -+#define RD_88F6192A_MPP0_7 0x01222222 -+#define RD_88F6192A_MPP8_15 0x00000011 -+#define RD_88F6192A_MPP16_23 0x05550000 -+#define RD_88F6192A_MPP24_31 0x0 -+#define RD_88F6192A_MPP32_35 0x0 -+#define RD_88F6192A_OE_LOW (BIT11 | BIT14 | BIT24 | BIT25 | BIT26 | BIT27 | BIT30 | BIT31) -+#define RD_88F6192A_OE_HIGH (BIT0 | BIT2) -+#define RD_88F6192A_OE_VAL_LOW 0x18400 -+#define RD_88F6192A_OE_VAL_HIGH 0x8 -+ -+/* DB-88F6180A-BP */ -+#if defined(MV_NAND) -+ #define DB_88F6180A_MPP0_7 0x21111111 -+#else -+ #define DB_88F6180A_MPP0_7 0x01112222 -+#endif -+#define DB_88F6180A_MPP8_15 0x11113311 -+#define DB_88F6180A_MPP16_23 0x00001111 -+#define DB_88F6180A_MPP24_31 0x0 -+#define DB_88F6180A_MPP32_39 0x4444c000 -+#define DB_88F6180A_MPP40_44 0x00044444 -+#define DB_88F6180A_OE_LOW 0x0 -+#define DB_88F6180A_OE_HIGH 0x0 -+#define DB_88F6180A_OE_VAL_LOW 0x0 -+#define DB_88F6180A_OE_VAL_HIGH 0x0 -+ -+/* RD-88F6281A_PCAC */ -+#define RD_88F6281A_PCAC_MPP0_7 0x21111111 -+#define RD_88F6281A_PCAC_MPP8_15 0x00003311 -+#define RD_88F6281A_PCAC_MPP16_23 0x00001100 -+#define RD_88F6281A_PCAC_MPP24_31 0x00000000 -+#define RD_88F6281A_PCAC_MPP32_39 0x00000000 -+#define RD_88F6281A_PCAC_MPP40_47 0x00000000 -+#define RD_88F6281A_PCAC_MPP48_55 0x00000000 -+#define RD_88F6281A_PCAC_OE_LOW 0x0 -+#define RD_88F6281A_PCAC_OE_HIGH 0x0 -+#define RD_88F6281A_PCAC_OE_VAL_LOW 0x0 -+#define RD_88F6281A_PCAC_OE_VAL_HIGH 0x0 -+ -+/* SHEEVA PLUG */ -+#define RD_SHEEVA_PLUG_MPP0_7 0x01111111 -+#define RD_SHEEVA_PLUG_MPP8_15 0x11113322 -+#define RD_SHEEVA_PLUG_MPP16_23 0x00001111 -+#define RD_SHEEVA_PLUG_MPP24_31 0x00100000 -+#define RD_SHEEVA_PLUG_MPP32_39 0x00000000 -+#define RD_SHEEVA_PLUG_MPP40_47 0x00000000 -+#define RD_SHEEVA_PLUG_MPP48_55 0x00000000 -+#define RD_SHEEVA_PLUG_OE_LOW 0x0 -+#define RD_SHEEVA_PLUG_OE_HIGH 0x0 -+#define RD_SHEEVA_PLUG_OE_VAL_LOW (BIT29) -+#define RD_SHEEVA_PLUG_OE_VAL_HIGH ((~(BIT17 | BIT16 | BIT15)) | BIT14) -+ -+/* DB-CUSTOMER */ -+#define DB_CUSTOMER_MPP0_7 0x21111111 -+#define DB_CUSTOMER_MPP8_15 0x00003311 -+#define DB_CUSTOMER_MPP16_23 0x00001100 -+#define DB_CUSTOMER_MPP24_31 0x00000000 -+#define DB_CUSTOMER_MPP32_39 0x00000000 -+#define DB_CUSTOMER_MPP40_47 0x00000000 -+#define DB_CUSTOMER_MPP48_55 0x00000000 -+#define DB_CUSTOMER_OE_LOW 0x0 -+#define DB_CUSTOMER_OE_HIGH (~((BIT6) | (BIT7) | (BIT8) | (BIT9))) -+#define DB_CUSTOMER_OE_VAL_LOW 0x0 -+#define DB_CUSTOMER_OE_VAL_HIGH 0x0 -+ -+#endif /* __INCmvBoardEnvSpech */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,320 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#include "cpu/mvCpu.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvRegs.h" -+#include "ctrlEnv/sys/mvCpuIfRegs.h" -+ -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+/* locals */ -+ -+/******************************************************************************* -+* mvCpuPclkGet - Get the CPU pClk (pipe clock) -+* -+* DESCRIPTION: -+* This routine extract the CPU core clock. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit clock cycles in MHertz. -+* -+*******************************************************************************/ -+/* 6180 have different clk reset sampling */ -+ -+static MV_U32 mvCpu6180PclkGet(MV_VOID) -+{ -+ MV_U32 tmpPClkRate=0; -+ MV_CPU_ARM_CLK cpu6180_ddr_l2_CLK[] = MV_CPU6180_DDR_L2_CLCK_TBL; -+ -+ tmpPClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ tmpPClkRate = tmpPClkRate & MSAR_CPUCLCK_MASK_6180; -+ tmpPClkRate = tmpPClkRate >> MSAR_CPUCLCK_OFFS_6180; -+ -+ tmpPClkRate = cpu6180_ddr_l2_CLK[tmpPClkRate].cpuClk; -+ -+ return tmpPClkRate; -+} -+ -+ -+MV_U32 mvCpuPclkGet(MV_VOID) -+{ -+#if defined(PCLCK_AUTO_DETECT) -+ MV_U32 tmpPClkRate=0; -+ MV_U32 cpuCLK[] = MV_CPU_CLCK_TBL; -+ -+ if(mvCtrlModelGet() == MV_6180_DEV_ID) -+ return mvCpu6180PclkGet(); -+ -+ tmpPClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ tmpPClkRate = MSAR_CPUCLCK_EXTRACT(tmpPClkRate); -+ tmpPClkRate = cpuCLK[tmpPClkRate]; -+ -+ return tmpPClkRate; -+#else -+ return MV_DEFAULT_PCLK -+#endif -+} -+ -+/******************************************************************************* -+* mvCpuL2ClkGet - Get the CPU L2 (CPU bus clock) -+* -+* DESCRIPTION: -+* This routine extract the CPU L2 clock. -+* -+* RETURN: -+* 32bit clock cycles in Hertz. -+* -+*******************************************************************************/ -+static MV_U32 mvCpu6180L2ClkGet(MV_VOID) -+{ -+ MV_U32 L2ClkRate=0; -+ MV_CPU_ARM_CLK _cpu6180_ddr_l2_CLK[] = MV_CPU6180_DDR_L2_CLCK_TBL; -+ -+ L2ClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ L2ClkRate = L2ClkRate & MSAR_CPUCLCK_MASK_6180; -+ L2ClkRate = L2ClkRate >> MSAR_CPUCLCK_OFFS_6180; -+ -+ L2ClkRate = _cpu6180_ddr_l2_CLK[L2ClkRate].l2Clk; -+ -+ return L2ClkRate; -+ -+} -+ -+MV_U32 mvCpuL2ClkGet(MV_VOID) -+{ -+#ifdef L2CLK_AUTO_DETECT -+ MV_U32 L2ClkRate, tmp, pClkRate, indexL2Rtio; -+ MV_U32 L2Rtio[][2] = MV_L2_CLCK_RTIO_TBL; -+ -+ if(mvCtrlModelGet() == MV_6180_DEV_ID) -+ return mvCpu6180L2ClkGet(); -+ -+ pClkRate = mvCpuPclkGet(); -+ -+ tmp = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ indexL2Rtio = MSAR_L2CLCK_EXTRACT(tmp); -+ -+ L2ClkRate = ((pClkRate * L2Rtio[indexL2Rtio][1]) / L2Rtio[indexL2Rtio][0]); -+ -+ return L2ClkRate; -+#else -+ return MV_BOARD_DEFAULT_L2CLK; -+#endif -+} -+ -+ -+/******************************************************************************* -+* mvCpuNameGet - Get CPU name -+* -+* DESCRIPTION: -+* This function returns a string describing the CPU model and revision. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* pNameBuff - Buffer to contain board name string. Minimum size 32 chars. -+* -+* RETURN: -+* None. -+*******************************************************************************/ -+MV_VOID mvCpuNameGet(char *pNameBuff) -+{ -+ MV_U32 cpuModel; -+ -+ cpuModel = mvOsCpuPartGet(); -+ -+ /* The CPU module is indicated in the Processor Version Register (PVR) */ -+ switch(cpuModel) -+ { -+ case CPU_PART_MRVL131: -+ mvOsSPrintf(pNameBuff, "%s (Rev %d)", "Marvell Feroceon",mvOsCpuRevGet()); -+ break; -+ case CPU_PART_ARM926: -+ mvOsSPrintf(pNameBuff, "%s (Rev %d)", "ARM926",mvOsCpuRevGet()); -+ break; -+ case CPU_PART_ARM946: -+ mvOsSPrintf(pNameBuff, "%s (Rev %d)", "ARM946",mvOsCpuRevGet()); -+ break; -+ default: -+ mvOsSPrintf(pNameBuff,"??? (0x%04x) (Rev %d)",cpuModel,mvOsCpuRevGet()); -+ break; -+ } /* switch */ -+ -+ return; -+} -+ -+ -+#define MV_PROC_STR_SIZE 50 -+ -+static void mvCpuIfGetL2EccMode(MV_8 *buf) -+{ -+ MV_U32 regVal = MV_REG_READ(CPU_L2_CONFIG_REG); -+ if (regVal & BIT2) -+ mvOsSPrintf(buf, "L2 ECC Enabled"); -+ else -+ mvOsSPrintf(buf, "L2 ECC Disabled"); -+} -+ -+static void mvCpuIfGetL2Mode(MV_8 *buf) -+{ -+ MV_U32 regVal = 0; -+ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ -+ if (regVal & BIT22) -+ mvOsSPrintf(buf, "L2 Enabled"); -+ else -+ mvOsSPrintf(buf, "L2 Disabled"); -+} -+ -+static void mvCpuIfGetL2PrefetchMode(MV_8 *buf) -+{ -+ MV_U32 regVal = 0; -+ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ -+ if (regVal & BIT24) -+ mvOsSPrintf(buf, "L2 Prefetch Disabled"); -+ else -+ mvOsSPrintf(buf, "L2 Prefetch Enabled"); -+} -+ -+static void mvCpuIfGetWriteAllocMode(MV_8 *buf) -+{ -+ MV_U32 regVal = 0; -+ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ -+ if (regVal & BIT28) -+ mvOsSPrintf(buf, "Write Allocate Enabled"); -+ else -+ mvOsSPrintf(buf, "Write Allocate Disabled"); -+} -+ -+static void mvCpuIfGetCpuStreamMode(MV_8 *buf) -+{ -+ MV_U32 regVal = 0; -+ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ -+ if (regVal & BIT29) -+ mvOsSPrintf(buf, "CPU Streaming Enabled"); -+ else -+ mvOsSPrintf(buf, "CPU Streaming Disabled"); -+} -+ -+static void mvCpuIfPrintCpuRegs(void) -+{ -+ MV_U32 regVal = 0; -+ -+ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ -+ mvOsPrintf("Extra Feature Reg = 0x%x\n",regVal); -+ -+ __asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (regVal)); /* Read Control register */ -+ mvOsPrintf("Control Reg = 0x%x\n",regVal); -+ -+ __asm volatile ("mrc p15, 0, %0, c0, c0, 0" : "=r" (regVal)); /* Read ID Code register */ -+ mvOsPrintf("ID Code Reg = 0x%x\n",regVal); -+ -+ __asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=r" (regVal)); /* Read Cache Type register */ -+ mvOsPrintf("Cache Type Reg = 0x%x\n",regVal); -+ -+} -+ -+MV_U32 mvCpuIfPrintSystemConfig(MV_8 *buffer, MV_U32 index) -+{ -+ MV_U32 count = 0; -+ -+ MV_8 L2_ECC_str[MV_PROC_STR_SIZE]; -+ MV_8 L2_En_str[MV_PROC_STR_SIZE]; -+ MV_8 L2_Prefetch_str[MV_PROC_STR_SIZE]; -+ MV_8 Write_Alloc_str[MV_PROC_STR_SIZE]; -+ MV_8 Cpu_Stream_str[MV_PROC_STR_SIZE]; -+ -+ mvCpuIfGetL2Mode(L2_En_str); -+ mvCpuIfGetL2EccMode(L2_ECC_str); -+ mvCpuIfGetL2PrefetchMode(L2_Prefetch_str); -+ mvCpuIfGetWriteAllocMode(Write_Alloc_str); -+ mvCpuIfGetCpuStreamMode(Cpu_Stream_str); -+ mvCpuIfPrintCpuRegs(); -+ -+ count += mvOsSPrintf(buffer + count + index, "%s\n", L2_En_str); -+ count += mvOsSPrintf(buffer + count + index, "%s\n", L2_ECC_str); -+ count += mvOsSPrintf(buffer + count + index, "%s\n", L2_Prefetch_str); -+ count += mvOsSPrintf(buffer + count + index, "%s\n", Write_Alloc_str); -+ count += mvOsSPrintf(buffer + count + index, "%s\n", Cpu_Stream_str); -+ return count; -+} -+ -+MV_U32 whoAmI(MV_VOID) -+{ -+ return 0; -+} -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,99 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvCpuh -+#define __INCmvCpuh -+ -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+ -+/* defines */ -+#define CPU_PART_MRVL131 0x131 -+#define CPU_PART_ARM926 0x926 -+#define CPU_PART_ARM946 0x946 -+#define MV_CPU_ARM_CLK_ELM_SIZE 12 -+#define MV_CPU_ARM_CLK_RATIO_OFF 8 -+#define MV_CPU_ARM_CLK_DDR_OFF 4 -+ -+#ifndef MV_ASMLANGUAGE -+typedef struct _mvCpuArmClk -+{ -+ MV_U32 cpuClk; /* CPU clock in MHz */ -+ MV_U32 ddrClk; /* DDR clock in MHz */ -+ MV_U32 l2Clk; /* CPU DDR clock ratio */ -+ -+}MV_CPU_ARM_CLK; -+ -+MV_U32 mvCpuPclkGet(MV_VOID); -+MV_VOID mvCpuNameGet(char *pNameBuff); -+MV_U32 mvCpuL2ClkGet(MV_VOID); -+MV_U32 mvCpuIfPrintSystemConfig(MV_8 *buffer, MV_U32 index); -+MV_U32 whoAmI(MV_VOID); -+ -+#endif /* MV_ASMLANGUAGE */ -+ -+ -+#endif /* __INCmvCpuh */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,296 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+/******************************************************************************* -+* mvCtrlEnvAddrDec.h - Marvell controller address decode library -+* -+* DESCRIPTION: -+* -+* DEPENDENCIES: -+* None. -+* -+*******************************************************************************/ -+ -+/* includes */ -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+#include "ctrlEnv/sys/mvAhbToMbusRegs.h" -+#include "ddr2/mvDramIfRegs.h" -+#include "pex/mvPexRegs.h" -+ -+#define MV_DEBUG -+ -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+/* Default Attributes array */ -+MV_TARGET_ATTRIB mvTargetDefaultsArray[] = TARGETS_DEF_ARRAY; -+extern MV_TARGET *sampleAtResetTargetArray; -+/* Dram\AHBToMbus\PEX share regsiter */ -+ -+#define CTRL_DEC_BASE_OFFS 16 -+#define CTRL_DEC_BASE_MASK (0xffff << CTRL_DEC_BASE_OFFS) -+#define CTRL_DEC_BASE_ALIGNMENT 0x10000 -+ -+#define CTRL_DEC_SIZE_OFFS 16 -+#define CTRL_DEC_SIZE_MASK (0xffff << CTRL_DEC_SIZE_OFFS) -+#define CTRL_DEC_SIZE_ALIGNMENT 0x10000 -+ -+#define CTRL_DEC_WIN_EN BIT0 -+ -+ -+ -+/******************************************************************************* -+* mvCtrlAddrDecToReg - Get address decode register format values -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_STATUS mvCtrlAddrDecToReg(MV_ADDR_WIN *pAddrDecWin, MV_DEC_REGS *pAddrDecRegs) -+{ -+ -+ MV_U32 baseToReg=0 , sizeToReg=0; -+ -+ /* BaseLow[31:16] => base register [31:16] */ -+ baseToReg = pAddrDecWin->baseLow & CTRL_DEC_BASE_MASK; -+ -+ /* Write to address decode Base Address Register */ -+ pAddrDecRegs->baseReg &= ~CTRL_DEC_BASE_MASK; -+ pAddrDecRegs->baseReg |= baseToReg; -+ -+ /* Get size register value according to window size */ -+ sizeToReg = ctrlSizeToReg(pAddrDecWin->size, CTRL_DEC_SIZE_ALIGNMENT); -+ -+ /* Size parameter validity check. */ -+ if (-1 == sizeToReg) -+ { -+ return MV_BAD_PARAM; -+ } -+ -+ /* set size */ -+ pAddrDecRegs->sizeReg &= ~CTRL_DEC_SIZE_MASK; -+ pAddrDecRegs->sizeReg |= (sizeToReg << CTRL_DEC_SIZE_OFFS); -+ -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvCtrlRegToAddrDec - Extract address decode struct from registers. -+* -+* DESCRIPTION: -+* This function extract address decode struct from address decode -+* registers given as parameters. -+* -+* INPUT: -+* pAddrDecRegs - Address decode register struct. -+* -+* OUTPUT: -+* pAddrDecWin - Target window data structure. -+* -+* RETURN: -+* MV_BAD_PARAM if address decode registers data is invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvCtrlRegToAddrDec(MV_DEC_REGS *pAddrDecRegs, MV_ADDR_WIN *pAddrDecWin) -+{ -+ MV_U32 sizeRegVal; -+ -+ sizeRegVal = (pAddrDecRegs->sizeReg & CTRL_DEC_SIZE_MASK) >> -+ CTRL_DEC_SIZE_OFFS; -+ -+ pAddrDecWin->size = ctrlRegToSize(sizeRegVal, CTRL_DEC_SIZE_ALIGNMENT); -+ -+ -+ /* Extract base address */ -+ /* Base register [31:16] ==> baseLow[31:16] */ -+ pAddrDecWin->baseLow = pAddrDecRegs->baseReg & CTRL_DEC_BASE_MASK; -+ -+ pAddrDecWin->baseHigh = 0; -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvCtrlAttribGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+* -+*******************************************************************************/ -+ -+MV_STATUS mvCtrlAttribGet(MV_TARGET target, -+ MV_TARGET_ATTRIB *targetAttrib) -+{ -+ -+ targetAttrib->attrib = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].attrib; -+ targetAttrib->targetId = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId; -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvCtrlGetAttrib - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_TARGET mvCtrlTargetGet(MV_TARGET_ATTRIB *targetAttrib) -+{ -+ MV_TARGET target; -+ MV_TARGET x; -+ for (target = SDRAM_CS0; target < MAX_TARGETS ; target ++) -+ { -+ x = MV_CHANGE_BOOT_CS(target); -+ if ((mvTargetDefaultsArray[x].attrib == targetAttrib->attrib) && -+ (mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId == targetAttrib->targetId)) -+ { -+ /* found it */ -+ break; -+ } -+ } -+ -+ return target; -+} -+ -+MV_STATUS mvCtrlAddrDecToParams(MV_DEC_WIN *pAddrDecWin, -+ MV_DEC_WIN_PARAMS *pWinParam) -+{ -+ MV_U32 baseToReg=0, sizeToReg=0; -+ -+ /* BaseLow[31:16] => base register [31:16] */ -+ baseToReg = pAddrDecWin->addrWin.baseLow & CTRL_DEC_BASE_MASK; -+ -+ /* Write to address decode Base Address Register */ -+ pWinParam->baseAddr &= ~CTRL_DEC_BASE_MASK; -+ pWinParam->baseAddr |= baseToReg; -+ -+ /* Get size register value according to window size */ -+ sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, CTRL_DEC_SIZE_ALIGNMENT); -+ -+ /* Size parameter validity check. */ -+ if (-1 == sizeToReg) -+ { -+ mvOsPrintf("mvCtrlAddrDecToParams: ERR. ctrlSizeToReg failed.\n"); -+ return MV_BAD_PARAM; -+ } -+ pWinParam->size = sizeToReg; -+ -+ pWinParam->attrib = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(pAddrDecWin->target)].attrib; -+ pWinParam->targetId = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(pAddrDecWin->target)].targetId; -+ -+ return MV_OK; -+} -+ -+MV_STATUS mvCtrlParamsToAddrDec(MV_DEC_WIN_PARAMS *pWinParam, -+ MV_DEC_WIN *pAddrDecWin) -+{ -+ MV_TARGET_ATTRIB targetAttrib; -+ -+ pAddrDecWin->addrWin.baseLow = pWinParam->baseAddr; -+ -+ /* Upper 32bit address base is supported under PCI High Address remap */ -+ pAddrDecWin->addrWin.baseHigh = 0; -+ -+ /* Prepare sizeReg to ctrlRegToSize function */ -+ pAddrDecWin->addrWin.size = ctrlRegToSize(pWinParam->size, CTRL_DEC_SIZE_ALIGNMENT); -+ -+ if (-1 == pAddrDecWin->addrWin.size) -+ { -+ DB(mvOsPrintf("mvCtrlParamsToAddrDec: ERR. ctrlRegToSize failed.\n")); -+ return MV_BAD_PARAM; -+ } -+ targetAttrib.targetId = pWinParam->targetId; -+ targetAttrib.attrib = pWinParam->attrib; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ return MV_OK; -+} -+ -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,203 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvCtrlEnvAddrDech -+#define __INCmvCtrlEnvAddrDech -+ -+/* includes */ -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvRegs.h" -+ -+ -+/* defines */ -+/* DUnit attributes */ -+#define ATMWCR_WIN_DUNIT_CS0_OFFS 0 -+#define ATMWCR_WIN_DUNIT_CS0_MASK BIT0 -+#define ATMWCR_WIN_DUNIT_CS0_REQ (0 << ATMWCR_WIN_DUNIT_CS0_OFFS) -+ -+#define ATMWCR_WIN_DUNIT_CS1_OFFS 1 -+#define ATMWCR_WIN_DUNIT_CS1_MASK BIT1 -+#define ATMWCR_WIN_DUNIT_CS1_REQ (0 << ATMWCR_WIN_DUNIT_CS1_OFFS) -+ -+#define ATMWCR_WIN_DUNIT_CS2_OFFS 2 -+#define ATMWCR_WIN_DUNIT_CS2_MASK BIT2 -+#define ATMWCR_WIN_DUNIT_CS2_REQ (0 << ATMWCR_WIN_DUNIT_CS2_OFFS) -+ -+#define ATMWCR_WIN_DUNIT_CS3_OFFS 3 -+#define ATMWCR_WIN_DUNIT_CS3_MASK BIT3 -+#define ATMWCR_WIN_DUNIT_CS3_REQ (0 << ATMWCR_WIN_DUNIT_CS3_OFFS) -+ -+/* RUnit (Device) attributes */ -+#define ATMWCR_WIN_RUNIT_DEVCS0_OFFS 0 -+#define ATMWCR_WIN_RUNIT_DEVCS0_MASK BIT0 -+#define ATMWCR_WIN_RUNIT_DEVCS0_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS0_OFFS) -+ -+#define ATMWCR_WIN_RUNIT_DEVCS1_OFFS 1 -+#define ATMWCR_WIN_RUNIT_DEVCS1_MASK BIT1 -+#define ATMWCR_WIN_RUNIT_DEVCS1_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS1_OFFS) -+ -+#define ATMWCR_WIN_RUNIT_DEVCS2_OFFS 2 -+#define ATMWCR_WIN_RUNIT_DEVCS2_MASK BIT2 -+#define ATMWCR_WIN_RUNIT_DEVCS2_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS2_OFFS) -+ -+#define ATMWCR_WIN_RUNIT_BOOTCS_OFFS 4 -+#define ATMWCR_WIN_RUNIT_BOOTCS_MASK BIT4 -+#define ATMWCR_WIN_RUNIT_BOOTCS_REQ (0 << ATMWCR_WIN_RUNIT_BOOTCS_OFFS) -+ -+/* LMaster (PCI) attributes */ -+#define ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS 0 -+#define ATMWCR_WIN_LUNIT_BYTE_SWP_MASK BIT0 -+#define ATMWCR_WIN_LUNIT_BYTE_SWP (0 << ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS) -+#define ATMWCR_WIN_LUNIT_BYTE_NO_SWP (1 << ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS) -+ -+ -+#define ATMWCR_WIN_LUNIT_WORD_SWP_OFFS 1 -+#define ATMWCR_WIN_LUNIT_WORD_SWP_MASK BIT1 -+#define ATMWCR_WIN_LUNIT_WORD_SWP (0 << ATMWCR_WIN_LUNIT_WORD_SWP_OFFS) -+#define ATMWCR_WIN_LUNIT_WORD_NO_SWP (1 << ATMWCR_WIN_LUNIT_WORD_SWP_OFFS) -+ -+#define ATMWCR_WIN_LUNIT_NO_SNOOP BIT2 -+ -+#define ATMWCR_WIN_LUNIT_TYPE_OFFS 3 -+#define ATMWCR_WIN_LUNIT_TYPE_MASK BIT3 -+#define ATMWCR_WIN_LUNIT_TYPE_IO (0 << ATMWCR_WIN_LUNIT_TYPE_OFFS) -+#define ATMWCR_WIN_LUNIT_TYPE_MEM (1 << ATMWCR_WIN_LUNIT_TYPE_OFFS) -+ -+#define ATMWCR_WIN_LUNIT_FORCE64_OFFS 4 -+#define ATMWCR_WIN_LUNIT_FORCE64_MASK BIT4 -+#define ATMWCR_WIN_LUNIT_FORCE64 (0 << ATMWCR_WIN_LUNIT_FORCE64_OFFS) -+ -+#define ATMWCR_WIN_LUNIT_ORDERING_OFFS 6 -+#define ATMWCR_WIN_LUNIT_ORDERING_MASK BIT6 -+#define ATMWCR_WIN_LUNIT_ORDERING (1 << ATMWCR_WIN_LUNIT_FORCE64_OFFS) -+ -+/* PEX Attributes */ -+#define ATMWCR_WIN_PEX_TYPE_OFFS 3 -+#define ATMWCR_WIN_PEX_TYPE_MASK BIT3 -+#define ATMWCR_WIN_PEX_TYPE_IO (0 << ATMWCR_WIN_PEX_TYPE_OFFS) -+#define ATMWCR_WIN_PEX_TYPE_MEM (1 << ATMWCR_WIN_PEX_TYPE_OFFS) -+ -+/* typedefs */ -+ -+/* Unsupported attributes for address decode: */ -+/* 2) PCI0/1_REQ64n control */ -+ -+typedef struct _mvDecRegs -+{ -+ MV_U32 baseReg; -+ MV_U32 baseRegHigh; -+ MV_U32 sizeReg; -+ -+}MV_DEC_REGS; -+ -+typedef struct _mvTargetAttrib -+{ -+ MV_U8 attrib; /* chip select attributes */ -+ MV_TARGET_ID targetId; /* Target Id of this MV_TARGET */ -+ -+}MV_TARGET_ATTRIB; -+ -+ -+/* This structure describes address decode window */ -+typedef struct _mvDecWin -+{ -+ MV_TARGET target; /* Target for addr decode window */ -+ MV_ADDR_WIN addrWin; /* Address window of target */ -+ MV_BOOL enable; /* Window enable/disable */ -+}MV_DEC_WIN; -+ -+typedef struct _mvDecWinParams -+{ -+ MV_TARGET_ID targetId; /* Target ID field */ -+ MV_U8 attrib; /* Attribute field */ -+ MV_U32 baseAddr; /* Base address in register format */ -+ MV_U32 size; /* Size in register format */ -+}MV_DEC_WIN_PARAMS; -+ -+ -+/* mvCtrlEnvAddrDec API list */ -+ -+MV_STATUS mvCtrlAddrDecToReg(MV_ADDR_WIN *pAddrDecWin, -+ MV_DEC_REGS *pAddrDecRegs); -+ -+MV_STATUS mvCtrlRegToAddrDec(MV_DEC_REGS *pAddrDecRegs, -+ MV_ADDR_WIN *pAddrDecWin); -+ -+MV_STATUS mvCtrlAttribGet(MV_TARGET target, -+ MV_TARGET_ATTRIB *targetAttrib); -+ -+MV_TARGET mvCtrlTargetGet(MV_TARGET_ATTRIB *targetAttrib); -+ -+ -+MV_STATUS mvCtrlAddrDecToParams(MV_DEC_WIN *pAddrDecWin, -+ MV_DEC_WIN_PARAMS *pWinParam); -+ -+MV_STATUS mvCtrlParamsToAddrDec(MV_DEC_WIN_PARAMS *pWinParam, -+ MV_DEC_WIN *pAddrDecWin); -+ -+ -+ -+ -+#endif /* __INCmvCtrlEnvAddrDech */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,98 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvCtrlEnvAsmh -+#define __INCmvCtrlEnvAsmh -+#include "pex/mvPexRegs.h" -+ -+#define CHIP_BOND_REG 0x10034 -+#define PCKG_OPT_MASK_AS #3 -+#define PXCCARI_REVID_MASK_AS #PXCCARI_REVID_MASK -+ -+/* Read device ID into toReg bits 15:0 from 0xd0000000 */ -+/* defines */ -+#define MV_DV_CTRL_MODEL_GET_ASM(toReg, tmpReg) \ -+ MV_DV_REG_READ_ASM(toReg, tmpReg, CHIP_BOND_REG);\ -+ and toReg, toReg, PCKG_OPT_MASK_AS /* Mask for package ID */ -+ -+/* Read device ID into toReg bits 15:0 from 0xf1000000*/ -+#define MV_CTRL_MODEL_GET_ASM(toReg, tmpReg) \ -+ MV_REG_READ_ASM(toReg, tmpReg, CHIP_BOND_REG);\ -+ and toReg, toReg, PCKG_OPT_MASK_AS /* Mask for package ID */ -+ -+/* Read Revision into toReg bits 7:0 0xd0000000*/ -+#define MV_DV_CTRL_REV_GET_ASM(toReg, tmpReg) \ -+ /* Read device revision */ \ -+ MV_DV_REG_READ_ASM(toReg, tmpReg, PEX_CFG_DIRECT_ACCESS(0,PEX_CLASS_CODE_AND_REVISION_ID));\ -+ and toReg, toReg, PXCCARI_REVID_MASK_AS /* Mask for calss ID */ -+ -+/* Read Revision into toReg bits 7:0 0xf1000000*/ -+#define MV_CTRL_REV_GET_ASM(toReg, tmpReg) \ -+ /* Read device revision */ \ -+ MV_REG_READ_ASM(toReg, tmpReg, PEX_CFG_DIRECT_ACCESS(0,PEX_CLASS_CODE_AND_REVISION_ID));\ -+ and toReg, toReg, PXCCARI_REVID_MASK_AS /* Mask for calss ID */ -+ -+ -+#endif /* __INCmvCtrlEnvAsmh */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,1825 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+/* includes */ -+#include "mvCommon.h" -+#include "mvCtrlEnvLib.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+ -+#if defined(MV_INCLUDE_PEX) -+#include "pex/mvPex.h" -+#include "ctrlEnv/sys/mvSysPex.h" -+#endif -+ -+#if defined(MV_INCLUDE_GIG_ETH) -+#include "ctrlEnv/sys/mvSysGbe.h" -+#endif -+ -+#if defined(MV_INCLUDE_XOR) -+#include "ctrlEnv/sys/mvSysXor.h" -+#endif -+ -+#if defined(MV_INCLUDE_SATA) -+#include "ctrlEnv/sys/mvSysSata.h" -+#endif -+ -+#if defined(MV_INCLUDE_USB) -+#include "ctrlEnv/sys/mvSysUsb.h" -+#endif -+ -+#if defined(MV_INCLUDE_AUDIO) -+#include "ctrlEnv/sys/mvSysAudio.h" -+#endif -+ -+#if defined(MV_INCLUDE_CESA) -+#include "ctrlEnv/sys/mvSysCesa.h" -+#endif -+ -+#if defined(MV_INCLUDE_TS) -+#include "ctrlEnv/sys/mvSysTs.h" -+#endif -+ -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+/******************************************************************************* -+* mvCtrlEnvInit - Initialize Marvell controller environment. -+* -+* DESCRIPTION: -+* This function get environment information and initialize controller -+* internal/external environment. For example -+* 1) MPP settings according to board MPP macros. -+* NOTE: It is the user responsibility to shut down all DMA channels -+* in device and disable controller sub units interrupts during -+* boot process. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvCtrlEnvInit(MV_VOID) -+{ -+ MV_U32 mppGroup; -+ MV_U32 devId; -+ MV_U32 boardId; -+ MV_U32 i; -+ MV_U32 maxMppGrp = 1; -+ MV_U32 mppVal = 0; -+ MV_U32 bootVal = 0; -+ MV_U32 mppGroupType = 0; -+ MV_U32 mppGroup1[][3] = MPP_GROUP_1_TYPE; -+ MV_U32 mppGroup2[][3] = MPP_GROUP_2_TYPE; -+ -+ devId = mvCtrlModelGet(); -+ boardId= mvBoardIdGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ maxMppGrp = MV_6281_MPP_MAX_GROUP; -+ break; -+ case MV_6192_DEV_ID: -+ maxMppGrp = MV_6192_MPP_MAX_GROUP; -+ break; -+ case MV_6190_DEV_ID: -+ maxMppGrp = MV_6190_MPP_MAX_GROUP; -+ break; -+ case MV_6180_DEV_ID: -+ maxMppGrp = MV_6180_MPP_MAX_GROUP; -+ break; -+ } -+ -+ /* MPP Init */ -+ /* We split mpp init to 3 phases: -+ * 1. We init mpp[19:0] from the board info. mpp[23:20] will be over write -+ * in phase 2. -+ * 2. We detect the mpp group type and according the mpp values [35:20]. -+ * 3. We detect the mpp group type and according the mpp values [49:36]. -+ */ -+ /* Mpp phase 1 mpp[19:0] */ -+ /* Read MPP group from board level and assign to MPP register */ -+ for (mppGroup = 0; mppGroup < 3; mppGroup++) -+ { -+ mppVal = mvBoardMppGet(mppGroup); -+ if (mppGroup == 0) -+ { -+ bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); -+ if (mvCtrlIsBootFromSPI()) -+ { -+ mppVal &= ~0xffff; -+ bootVal &= 0xffff; -+ mppVal |= bootVal; -+ } -+ else if (mvCtrlIsBootFromSPIUseNAND()) -+ { -+ mppVal &= ~0xf0000000; -+ bootVal &= 0xf0000000; -+ mppVal |= bootVal; -+ } -+ else if (mvCtrlIsBootFromNAND()) -+ { -+ mppVal &= ~0xffffff; -+ bootVal &= 0xffffff; -+ mppVal |= bootVal; -+ } -+ } -+ -+ if (mppGroup == 2) -+ { -+ bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); -+ if (mvCtrlIsBootFromNAND()) -+ { -+ mppVal &= ~0xff00; -+ bootVal &= 0xff00; -+ mppVal |= bootVal; -+ } -+ } -+ -+ MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal); -+ } -+ -+ /* Identify MPPs group */ -+ mvBoardMppGroupIdUpdate(); -+ -+ /* Update MPPs mux relevent only on Marvell DB */ -+ if ((boardId == DB_88F6281A_BP_ID) || -+ (boardId == DB_88F6180A_BP_ID)) -+ mvBoardMppMuxSet(); -+ -+ mppGroupType = mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_1); -+ -+ /* Mpp phase 2 */ -+ /* Read MPP group from board level and assign to MPP register */ -+ if (devId != MV_6180_DEV_ID) -+ { -+ i = 0; -+ for (mppGroup = 2; mppGroup < 5; mppGroup++) -+ { -+ if ((mppGroupType == MV_BOARD_OTHER) || -+ (boardId == RD_88F6281A_ID) || -+ (boardId == RD_88F6192A_ID) || -+ (boardId == RD_88F6190A_ID) || -+ (boardId == RD_88F6281A_PCAC_ID) || -+ (boardId == SHEEVA_PLUG_ID)) -+ mppVal = mvBoardMppGet(mppGroup); -+ else -+ { -+ mppVal = mppGroup1[mppGroupType][i]; -+ i++; -+ } -+ -+ /* Group 2 is shared mpp[23:16] */ -+ if (mppGroup == 2) -+ { -+ bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); -+ mppVal &= ~0xffff; -+ bootVal &= 0xffff; -+ mppVal |= bootVal; -+ } -+ -+ MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal); -+ } -+ } -+ -+ if ((devId == MV_6192_DEV_ID) || (devId == MV_6190_DEV_ID)) -+ return MV_OK; -+ -+ /* Mpp phase 3 */ -+ mppGroupType = mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_2); -+ /* Read MPP group from board level and assign to MPP register */ -+ i = 0; -+ for (mppGroup = 4; mppGroup < 7; mppGroup++) -+ { -+ if ((mppGroupType == MV_BOARD_OTHER) || -+ (boardId == RD_88F6281A_ID) || -+ (boardId == RD_88F6281A_PCAC_ID) || -+ (boardId == SHEEVA_PLUG_ID)) -+ mppVal = mvBoardMppGet(mppGroup); -+ else -+ { -+ mppVal = mppGroup2[mppGroupType][i]; -+ i++; -+ } -+ -+ /* Group 4 is shared mpp[35:32] */ -+ if (mppGroup == 4) -+ { -+ bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); -+ mppVal &= ~0xffff; -+ bootVal &= 0xffff; -+ mppVal |= bootVal; -+ } -+ -+ MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal); -+ } -+ /* Update SSCG configuration register*/ -+ if(mvBoardIdGet() == DB_88F6281A_BP_ID || mvBoardIdGet() == DB_88F6192A_BP_ID || -+ mvBoardIdGet() == DB_88F6190A_BP_ID || mvBoardIdGet() == DB_88F6180A_BP_ID) -+ MV_REG_WRITE(0x100d8, 0x53); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCtrlMppRegGet - return reg address of mpp group -+* -+* DESCRIPTION: -+* -+* INPUT: -+* mppGroup - MPP group. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_U32 - Register address. -+* -+*******************************************************************************/ -+MV_U32 mvCtrlMppRegGet(MV_U32 mppGroup) -+{ -+ MV_U32 ret; -+ -+ switch(mppGroup){ -+ case (0): ret = MPP_CONTROL_REG0; -+ break; -+ case (1): ret = MPP_CONTROL_REG1; -+ break; -+ case (2): ret = MPP_CONTROL_REG2; -+ break; -+ case (3): ret = MPP_CONTROL_REG3; -+ break; -+ case (4): ret = MPP_CONTROL_REG4; -+ break; -+ case (5): ret = MPP_CONTROL_REG5; -+ break; -+ case (6): ret = MPP_CONTROL_REG6; -+ break; -+ default: ret = MPP_CONTROL_REG0; -+ break; -+ } -+ return ret; -+} -+#if defined(MV_INCLUDE_PEX) -+/******************************************************************************* -+* mvCtrlPexMaxIfGet - Get Marvell controller number of PEX interfaces. -+* -+* DESCRIPTION: -+* This function returns Marvell controller number of PEX interfaces. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Marvell controller number of PEX interfaces. If controller -+* ID is undefined the function returns '0'. -+* -+*******************************************************************************/ -+MV_U32 mvCtrlPexMaxIfGet(MV_VOID) -+{ -+ -+ return MV_PEX_MAX_IF; -+} -+#endif -+ -+#if defined(MV_INCLUDE_GIG_ETH) -+/******************************************************************************* -+* mvCtrlEthMaxPortGet - Get Marvell controller number of etherent ports. -+* -+* DESCRIPTION: -+* This function returns Marvell controller number of etherent port. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Marvell controller number of etherent port. -+* -+*******************************************************************************/ -+MV_U32 mvCtrlEthMaxPortGet(MV_VOID) -+{ -+ MV_U32 devId; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ return MV_6281_ETH_MAX_PORTS; -+ break; -+ case MV_6192_DEV_ID: -+ return MV_6192_ETH_MAX_PORTS; -+ break; -+ case MV_6190_DEV_ID: -+ return MV_6190_ETH_MAX_PORTS; -+ break; -+ case MV_6180_DEV_ID: -+ return MV_6180_ETH_MAX_PORTS; -+ break; -+ } -+ return 0; -+ -+} -+#endif -+ -+#if defined(MV_INCLUDE_XOR) -+/******************************************************************************* -+* mvCtrlXorMaxChanGet - Get Marvell controller number of XOR channels. -+* -+* DESCRIPTION: -+* This function returns Marvell controller number of XOR channels. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Marvell controller number of XOR channels. -+* -+*******************************************************************************/ -+MV_U32 mvCtrlXorMaxChanGet(MV_VOID) -+{ -+ return MV_XOR_MAX_CHAN; -+} -+#endif -+ -+#if defined(MV_INCLUDE_USB) -+/******************************************************************************* -+* mvCtrlUsbHostMaxGet - Get number of Marvell Usb controllers -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* returns number of Marvell USB controllers. -+* -+*******************************************************************************/ -+MV_U32 mvCtrlUsbMaxGet(void) -+{ -+ return MV_USB_MAX_PORTS; -+} -+#endif -+ -+ -+#if defined(MV_INCLUDE_NAND) -+/******************************************************************************* -+* mvCtrlNandSupport - Return if this controller has integrated NAND flash support -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if NAND is supported and MV_FALSE otherwise -+* -+*******************************************************************************/ -+MV_U32 mvCtrlNandSupport(MV_VOID) -+{ -+ MV_U32 devId; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ return MV_6281_NAND; -+ break; -+ case MV_6192_DEV_ID: -+ return MV_6192_NAND; -+ break; -+ case MV_6190_DEV_ID: -+ return MV_6190_NAND; -+ break; -+ case MV_6180_DEV_ID: -+ return MV_6180_NAND; -+ break; -+ } -+ return 0; -+ -+} -+#endif -+ -+#if defined(MV_INCLUDE_SDIO) -+/******************************************************************************* -+* mvCtrlSdioSupport - Return if this controller has integrated SDIO flash support -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if SDIO is supported and MV_FALSE otherwise -+* -+*******************************************************************************/ -+MV_U32 mvCtrlSdioSupport(MV_VOID) -+{ -+ MV_U32 devId; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ return MV_6281_SDIO; -+ break; -+ case MV_6192_DEV_ID: -+ return MV_6192_SDIO; -+ break; -+ case MV_6190_DEV_ID: -+ return MV_6190_SDIO; -+ break; -+ case MV_6180_DEV_ID: -+ return MV_6180_SDIO; -+ break; -+ } -+ return 0; -+ -+} -+#endif -+ -+#if defined(MV_INCLUDE_TS) -+/******************************************************************************* -+* mvCtrlTsSupport - Return if this controller has integrated TS flash support -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if TS is supported and MV_FALSE otherwise -+* -+*******************************************************************************/ -+MV_U32 mvCtrlTsSupport(MV_VOID) -+{ -+ MV_U32 devId; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ return MV_6281_TS; -+ break; -+ case MV_6192_DEV_ID: -+ return MV_6192_TS; -+ break; -+ case MV_6190_DEV_ID: -+ return MV_6190_TS; -+ break; -+ case MV_6180_DEV_ID: -+ return MV_6180_TS; -+ break; -+ } -+ return 0; -+} -+#endif -+ -+#if defined(MV_INCLUDE_AUDIO) -+/******************************************************************************* -+* mvCtrlAudioSupport - Return if this controller has integrated AUDIO flash support -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if AUDIO is supported and MV_FALSE otherwise -+* -+*******************************************************************************/ -+MV_U32 mvCtrlAudioSupport(MV_VOID) -+{ -+ MV_U32 devId; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ return MV_6281_AUDIO; -+ break; -+ case MV_6192_DEV_ID: -+ return MV_6192_AUDIO; -+ break; -+ case MV_6190_DEV_ID: -+ return MV_6190_AUDIO; -+ break; -+ case MV_6180_DEV_ID: -+ return MV_6180_AUDIO; -+ break; -+ } -+ return 0; -+ -+} -+#endif -+ -+#if defined(MV_INCLUDE_TDM) -+/******************************************************************************* -+* mvCtrlTdmSupport - Return if this controller has integrated TDM flash support -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if TDM is supported and MV_FALSE otherwise -+* -+*******************************************************************************/ -+MV_U32 mvCtrlTdmSupport(MV_VOID) -+{ -+ MV_U32 devId; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ return MV_6281_TDM; -+ break; -+ case MV_6192_DEV_ID: -+ return MV_6192_TDM; -+ break; -+ case MV_6190_DEV_ID: -+ return MV_6190_TDM; -+ break; -+ case MV_6180_DEV_ID: -+ return MV_6180_TDM; -+ break; -+ } -+ return 0; -+ -+} -+#endif -+ -+/******************************************************************************* -+* mvCtrlModelGet - Get Marvell controller device model (Id) -+* -+* DESCRIPTION: -+* This function returns 16bit describing the device model (ID) as defined -+* in PCI Device and Vendor ID configuration register offset 0x0. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 16bit desscribing Marvell controller ID -+* -+*******************************************************************************/ -+MV_U16 mvCtrlModelGet(MV_VOID) -+{ -+ MV_U32 devId; -+ -+ devId = MV_REG_READ(CHIP_BOND_REG); -+ devId &= PCKG_OPT_MASK; -+ -+ switch(devId){ -+ case 2: -+ return MV_6281_DEV_ID; -+ break; -+ case 1: -+ if (((MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0,PEX_DEVICE_AND_VENDOR_ID))& 0xffff0000) >> 16) -+ == MV_6190_DEV_ID) -+ return MV_6190_DEV_ID; -+ else -+ return MV_6192_DEV_ID; -+ break; -+ case 0: -+ return MV_6180_DEV_ID; -+ break; -+ } -+ -+ return 0; -+} -+/******************************************************************************* -+* mvCtrlRevGet - Get Marvell controller device revision number -+* -+* DESCRIPTION: -+* This function returns 8bit describing the device revision as defined -+* in PCI Express Class Code and Revision ID Register. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 8bit desscribing Marvell controller revision number -+* -+*******************************************************************************/ -+MV_U8 mvCtrlRevGet(MV_VOID) -+{ -+ MV_U8 revNum; -+#if defined(MV_INCLUDE_CLK_PWR_CNTRL) -+ /* Check pex power state */ -+ MV_U32 pexPower; -+ pexPower = mvCtrlPwrClckGet(PEX_UNIT_ID,0); -+ if (pexPower == MV_FALSE) -+ mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_TRUE); -+#endif -+ revNum = (MV_U8)MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0,PCI_CLASS_CODE_AND_REVISION_ID)); -+#if defined(MV_INCLUDE_CLK_PWR_CNTRL) -+ /* Return to power off state */ -+ if (pexPower == MV_FALSE) -+ mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_FALSE); -+#endif -+ return ((revNum & PCCRIR_REVID_MASK) >> PCCRIR_REVID_OFFS); -+} -+ -+/******************************************************************************* -+* mvCtrlNameGet - Get Marvell controller name -+* -+* DESCRIPTION: -+* This function returns a string describing the device model and revision. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* pNameBuff - Buffer to contain device name string. Minimum size 30 chars. -+* -+* RETURN: -+* -+* MV_ERROR if informantion can not be read. -+*******************************************************************************/ -+MV_STATUS mvCtrlNameGet(char *pNameBuff) -+{ -+ mvOsSPrintf (pNameBuff, "%s%x Rev %d", SOC_NAME_PREFIX, -+ mvCtrlModelGet(), mvCtrlRevGet()); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCtrlModelRevGet - Get Controller Model (Device ID) and Revision -+* -+* DESCRIPTION: -+* This function returns 32bit value describing both Device ID and Revision -+* as defined in PCI Express Device and Vendor ID Register and device revision -+* as defined in PCI Express Class Code and Revision ID Register. -+ -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit describing both controller device ID and revision number -+* -+*******************************************************************************/ -+MV_U32 mvCtrlModelRevGet(MV_VOID) -+{ -+ return ((mvCtrlModelGet() << 16) | mvCtrlRevGet()); -+} -+ -+/******************************************************************************* -+* mvCtrlModelRevNameGet - Get Marvell controller name -+* -+* DESCRIPTION: -+* This function returns a string describing the device model and revision. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* pNameBuff - Buffer to contain device name string. Minimum size 30 chars. -+* -+* RETURN: -+* -+* MV_ERROR if informantion can not be read. -+*******************************************************************************/ -+ -+MV_STATUS mvCtrlModelRevNameGet(char *pNameBuff) -+{ -+ -+ switch (mvCtrlModelRevGet()) -+ { -+ case MV_6281_A0_ID: -+ mvOsSPrintf (pNameBuff, "%s",MV_6281_A0_NAME); -+ break; -+ case MV_6192_A0_ID: -+ mvOsSPrintf (pNameBuff, "%s",MV_6192_A0_NAME); -+ break; -+ case MV_6180_A0_ID: -+ mvOsSPrintf (pNameBuff, "%s",MV_6180_A0_NAME); -+ break; -+ case MV_6190_A0_ID: -+ mvOsSPrintf (pNameBuff, "%s",MV_6190_A0_NAME); -+ break; -+ case MV_6281_A1_ID: -+ mvOsSPrintf (pNameBuff, "%s",MV_6281_A1_NAME); -+ break; -+ case MV_6192_A1_ID: -+ mvOsSPrintf (pNameBuff, "%s",MV_6192_A1_NAME); -+ break; -+ case MV_6180_A1_ID: -+ mvOsSPrintf (pNameBuff, "%s",MV_6180_A1_NAME); -+ break; -+ case MV_6190_A1_ID: -+ mvOsSPrintf (pNameBuff, "%s",MV_6190_A1_NAME); -+ break; -+ default: -+ mvCtrlNameGet(pNameBuff); -+ break; -+ } -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* ctrlWinOverlapTest - Test address windows for overlaping. -+* -+* DESCRIPTION: -+* This function checks the given two address windows for overlaping. -+* -+* INPUT: -+* pAddrWin1 - Address window 1. -+* pAddrWin2 - Address window 2. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* MV_TRUE if address window overlaps, MV_FALSE otherwise. -+*******************************************************************************/ -+MV_STATUS ctrlWinOverlapTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2) -+{ -+ MV_U32 winBase1, winBase2; -+ MV_U32 winTop1, winTop2; -+ -+ /* check if we have overflow than 4G*/ -+ if (((0xffffffff - pAddrWin1->baseLow) < pAddrWin1->size-1)|| -+ ((0xffffffff - pAddrWin2->baseLow) < pAddrWin2->size-1)) -+ { -+ return MV_TRUE; -+ } -+ -+ winBase1 = pAddrWin1->baseLow; -+ winBase2 = pAddrWin2->baseLow; -+ winTop1 = winBase1 + pAddrWin1->size-1; -+ winTop2 = winBase2 + pAddrWin2->size-1; -+ -+ -+ if (((winBase1 <= winTop2 ) && ( winTop2 <= winTop1)) || -+ ((winBase1 <= winBase2) && (winBase2 <= winTop1))) -+ { -+ return MV_TRUE; -+ } -+ else -+ { -+ return MV_FALSE; -+ } -+} -+ -+/******************************************************************************* -+* ctrlWinWithinWinTest - Test address windows for overlaping. -+* -+* DESCRIPTION: -+* This function checks the given win1 boundries is within -+* win2 boundries. -+* -+* INPUT: -+* pAddrWin1 - Address window 1. -+* pAddrWin2 - Address window 2. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* MV_TRUE if found win1 inside win2, MV_FALSE otherwise. -+*******************************************************************************/ -+MV_STATUS ctrlWinWithinWinTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2) -+{ -+ MV_U32 winBase1, winBase2; -+ MV_U32 winTop1, winTop2; -+ -+ winBase1 = pAddrWin1->baseLow; -+ winBase2 = pAddrWin2->baseLow; -+ winTop1 = winBase1 + pAddrWin1->size -1; -+ winTop2 = winBase2 + pAddrWin2->size -1; -+ -+ if (((winBase1 >= winBase2 ) && ( winBase1 <= winTop2)) || -+ ((winTop1 >= winBase2) && (winTop1 <= winTop2))) -+ { -+ return MV_TRUE; -+ } -+ else -+ { -+ return MV_FALSE; -+ } -+} -+ -+static const char* cntrlName[] = TARGETS_NAME_ARRAY; -+ -+/******************************************************************************* -+* mvCtrlTargetNameGet - Get Marvell controller target name -+* -+* DESCRIPTION: -+* This function convert the trget enumeration to string. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Target name (const MV_8 *) -+*******************************************************************************/ -+const MV_8* mvCtrlTargetNameGet( MV_TARGET target ) -+{ -+ -+ if (target >= MAX_TARGETS) -+ { -+ return "target unknown"; -+ } -+ -+ return cntrlName[target]; -+} -+ -+/******************************************************************************* -+* mvCtrlAddrDecShow - Print the Controller units address decode map. -+* -+* DESCRIPTION: -+* This function the Controller units address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvCtrlAddrDecShow(MV_VOID) -+{ -+ mvCpuIfAddDecShow(); -+ mvAhbToMbusAddDecShow(); -+#if defined(MV_INCLUDE_PEX) -+ mvPexAddrDecShow(); -+#endif -+#if defined(MV_INCLUDE_USB) -+ mvUsbAddrDecShow(); -+#endif -+#if defined(MV_INCLUDE_GIG_ETH) -+ mvEthAddrDecShow(); -+#endif -+#if defined(MV_INCLUDE_XOR) -+ mvXorAddrDecShow(); -+#endif -+#if defined(MV_INCLUDE_SATA) -+ mvSataAddrDecShow(); -+#endif -+#if defined(MV_INCLUDE_AUDIO) -+ mvAudioAddrDecShow(); -+#endif -+#if defined(MV_INCLUDE_TS) -+ mvTsuAddrDecShow(); -+#endif -+} -+ -+/******************************************************************************* -+* ctrlSizeToReg - Extract size value for register assignment. -+* -+* DESCRIPTION: -+* Address decode size parameter must be programed from LSB to MSB as -+* sequence of 1's followed by sequence of 0's. The number of 1's -+* specifies the size of the window in 64 KB granularity (e.g. a -+* value of 0x00ff specifies 256x64k = 16 MB). -+* This function extract the size value from the size parameter according -+* to given aligment paramter. For example for size 0x1000000 (16MB) and -+* aligment 0x10000 (64KB) the function will return 0x00FF. -+* -+* INPUT: -+* size - Size. -+* alignment - Size alignment. Note that alignment must be power of 2! -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit describing size register value correspond to size parameter. -+* If value is '-1' size parameter or aligment are invalid. -+*******************************************************************************/ -+MV_U32 ctrlSizeToReg(MV_U32 size, MV_U32 alignment) -+{ -+ MV_U32 retVal; -+ -+ /* Check size parameter alignment */ -+ if ((0 == size) || (MV_IS_NOT_ALIGN(size, alignment))) -+ { -+ DB(mvOsPrintf("ctrlSizeToReg: ERR. Size is zero or not aligned.\n")); -+ return -1; -+ } -+ -+ /* Take out the "alignment" portion out of the size parameter */ -+ alignment--; /* Now the alignmet is a sequance of '1' (e.g. 0xffff) */ -+ /* and size is 0x1000000 (16MB) for example */ -+ while(alignment & 1) /* Check that alignmet LSB is set */ -+ { -+ size = (size >> 1); /* If LSB is set, move 'size' one bit to right */ -+ alignment = (alignment >> 1); -+ } -+ -+ /* If after the alignment first '0' was met we still have '1' in */ -+ /* it then aligment is invalid (not power of 2) */ -+ if (alignment) -+ { -+ DB(mvOsPrintf("ctrlSizeToReg: ERR. Alignment parameter 0x%x invalid.\n", -+ (MV_U32)alignment)); -+ return -1; -+ } -+ -+ /* Now the size is shifted right according to aligment: 0x0100 */ -+ size--; /* Now the size is a sequance of '1': 0x00ff */ -+ -+ retVal = size ; -+ -+ /* Check that LSB to MSB is sequence of 1's followed by sequence of 0's */ -+ while(size & 1) /* Check that LSB is set */ -+ { -+ size = (size >> 1); /* If LSB is set, move one bit to the right */ -+ } -+ -+ if (size) /* Sequance of 1's is over. Check that we have no other 1's */ -+ { -+ DB(mvOsPrintf("ctrlSizeToReg: ERR. Size parameter 0x%x invalid.\n", -+ size)); -+ return -1; -+ } -+ -+ return retVal; -+ -+} -+ -+/******************************************************************************* -+* ctrlRegToSize - Extract size value from register value. -+* -+* DESCRIPTION: -+* This function extract a size value from the register size parameter -+* according to given aligment paramter. For example for register size -+* value 0xff and aligment 0x10000 the function will return 0x01000000. -+* -+* INPUT: -+* regSize - Size as in register format. See ctrlSizeToReg. -+* alignment - Size alignment. Note that alignment must be power of 2! -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit describing size. -+* If value is '-1' size parameter or aligment are invalid. -+*******************************************************************************/ -+MV_U32 ctrlRegToSize(MV_U32 regSize, MV_U32 alignment) -+{ -+ MV_U32 temp; -+ -+ /* Check that LSB to MSB is sequence of 1's followed by sequence of 0's */ -+ temp = regSize; /* Now the size is a sequance of '1': 0x00ff */ -+ -+ while(temp & 1) /* Check that LSB is set */ -+ { -+ temp = (temp >> 1); /* If LSB is set, move one bit to the right */ -+ } -+ -+ if (temp) /* Sequance of 1's is over. Check that we have no other 1's */ -+ { -+ DB(mvOsPrintf("ctrlRegToSize: ERR. Size parameter 0x%x invalid.\n", -+ regSize)); -+ return -1; -+ } -+ -+ -+ /* Check that aligment is a power of two */ -+ temp = alignment - 1;/* Now the alignmet is a sequance of '1' (0xffff) */ -+ -+ while(temp & 1) /* Check that alignmet LSB is set */ -+ { -+ temp = (temp >> 1); /* If LSB is set, move 'size' one bit to right */ -+ } -+ -+ /* If after the 'temp' first '0' was met we still have '1' in 'temp' */ -+ /* then 'temp' is invalid (not power of 2) */ -+ if (temp) -+ { -+ DB(mvOsPrintf("ctrlSizeToReg: ERR. Alignment parameter 0x%x invalid.\n", -+ alignment)); -+ return -1; -+ } -+ -+ regSize++; /* Now the size is 0x0100 */ -+ -+ /* Add in the "alignment" portion to the register size parameter */ -+ alignment--; /* Now the alignmet is a sequance of '1' (e.g. 0xffff) */ -+ -+ while(alignment & 1) /* Check that alignmet LSB is set */ -+ { -+ regSize = (regSize << 1); /* LSB is set, move 'size' one bit left */ -+ alignment = (alignment >> 1); -+ } -+ -+ return regSize; -+} -+ -+ -+/******************************************************************************* -+* ctrlSizeRegRoundUp - Round up given size -+* -+* DESCRIPTION: -+* This function round up a given size to a size that fits the -+* restrictions of size format given an aligment parameter. -+* to given aligment paramter. For example for size parameter 0xa1000 and -+* aligment 0x1000 the function will return 0xFF000. -+* -+* INPUT: -+* size - Size. -+* alignment - Size alignment. Note that alignment must be power of 2! -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit describing size value correspond to size in register. -+*******************************************************************************/ -+MV_U32 ctrlSizeRegRoundUp(MV_U32 size, MV_U32 alignment) -+{ -+ MV_U32 msbBit = 0; -+ MV_U32 retSize; -+ -+ /* Check if size parameter is already comply with restriction */ -+ if (!(-1 == ctrlSizeToReg(size, alignment))) -+ { -+ return size; -+ } -+ -+ while(size) -+ { -+ size = (size >> 1); -+ msbBit++; -+ } -+ -+ retSize = (1 << msbBit); -+ -+ if (retSize < alignment) -+ { -+ return alignment; -+ } -+ else -+ { -+ return retSize; -+ } -+} -+/******************************************************************************* -+* mvCtrlSysRstLengthCounterGet - Return number of milliseconds the reset button -+* was pressed and clear counter -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: number of milliseconds the reset button was pressed -+*******************************************************************************/ -+MV_U32 mvCtrlSysRstLengthCounterGet(MV_VOID) -+{ -+ static volatile MV_U32 Count = 0; -+ -+ if(!Count) { -+ Count = (MV_REG_READ(SYSRST_LENGTH_COUNTER_REG) & SLCR_COUNT_MASK); -+ Count = (Count / (MV_BOARD_REFCLK_25MHZ / 1000)); -+ /* clear counter for next boot */ -+ MV_REG_BIT_SET(SYSRST_LENGTH_COUNTER_REG, SLCR_CLR_MASK); -+ } -+ -+ DB(mvOsPrintf("mvCtrlSysRstLengthCounterGet: Reset button was pressed for %u milliseconds\n", Count)); -+ -+ return Count; -+} -+ -+MV_BOOL mvCtrlIsBootFromSPI(MV_VOID) -+{ -+ MV_U32 satr = 0; -+ satr = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ if(mvCtrlModelGet() == MV_6180_DEV_ID) -+ { -+ if (MSAR_BOOT_MODE_6180(satr) == MSAR_BOOT_SPI_WITH_BOOTROM_6180) -+ return MV_TRUE; -+ else -+ return MV_FALSE; -+ } -+ satr = satr & MSAR_BOOT_MODE_MASK; -+ if (satr == MSAR_BOOT_SPI_WITH_BOOTROM) -+ return MV_TRUE; -+ else -+ return MV_FALSE; -+} -+ -+MV_BOOL mvCtrlIsBootFromSPIUseNAND(MV_VOID) -+{ -+ MV_U32 satr = 0; -+ if(mvCtrlModelGet() == MV_6180_DEV_ID) -+ return MV_FALSE; -+ satr = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ satr = satr & MSAR_BOOT_MODE_MASK; -+ -+ if (satr == MSAR_BOOT_SPI_USE_NAND_WITH_BOOTROM) -+ return MV_TRUE; -+ else -+ return MV_FALSE; -+} -+ -+MV_BOOL mvCtrlIsBootFromNAND(MV_VOID) -+{ -+ MV_U32 satr = 0; -+ satr = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ if(mvCtrlModelGet() == MV_6180_DEV_ID) -+ { -+ if (MSAR_BOOT_MODE_6180(satr) == MSAR_BOOT_NAND_WITH_BOOTROM_6180) -+ return MV_TRUE; -+ else -+ return MV_FALSE; -+ } -+ satr = satr & MSAR_BOOT_MODE_MASK; -+ if ((satr == MSAR_BOOT_NAND_WITH_BOOTROM)) -+ return MV_TRUE; -+ else -+ return MV_FALSE; -+} -+ -+#if defined(MV_INCLUDE_CLK_PWR_CNTRL) -+/******************************************************************************* -+* mvCtrlPwrSaveOn - Set Power save mode -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+*******************************************************************************/ -+MV_VOID mvCtrlPwrSaveOn(MV_VOID) -+{ -+ unsigned long old,temp; -+ /* Disable int */ -+ __asm__ __volatile__("mrs %0, cpsr\n" -+ "orr %1, %0, #0xc0\n" -+ "msr cpsr_c, %1" -+ : "=r" (old), "=r" (temp) -+ : -+ : "memory"); -+ -+ /* Set SoC in power save */ -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, BIT11); -+ /* Wait for int */ -+ __asm__ __volatile__("mcr p15, 0, r0, c7, c0, 4"); -+ -+ /* Enabled int */ -+ __asm__ __volatile__("msr cpsr_c, %0" -+ : -+ : "r" (old) -+ : "memory"); -+} -+ -+ -+ -+/******************************************************************************* -+* mvCtrlPwrSaveOff - Go out of power save mode -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+*******************************************************************************/ -+MV_VOID mvCtrlPwrSaveOff(MV_VOID) -+{ -+ unsigned long old,temp; -+ /* Disable int */ -+ __asm__ __volatile__("mrs %0, cpsr\n" -+ "orr %1, %0, #0xc0\n" -+ "msr cpsr_c, %1" -+ : "=r" (old), "=r" (temp) -+ : -+ : "memory"); -+ -+ /* Set SoC in power save */ -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, BIT11); -+ /* Wait for int */ -+ __asm__ __volatile__("mcr p15, 0, r0, c7, c0, 4"); -+ -+ /* Enabled int */ -+ __asm__ __volatile__("msr cpsr_c, %0" -+ : -+ : "r" (old) -+ : "memory"); -+} -+ -+/******************************************************************************* -+* mvCtrlPwrClckSet - Set Power State for specific Unit -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+*******************************************************************************/ -+MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) -+{ -+ switch (unitId) -+ { -+#if defined(MV_INCLUDE_PEX) -+ case PEX_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_PEXSTOPCLOCK_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_PEXSTOPCLOCK_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_GIG_ETH) -+ case ETH_GIG_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_GESTOPCLOCK_MASK(index)); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_GESTOPCLOCK_MASK(index)); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_INTEG_SATA) -+ case SATA_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SATASTOPCLOCK_MASK(index)); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SATASTOPCLOCK_MASK(index)); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_CESA) -+ case CESA_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SESTOPCLOCK_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SESTOPCLOCK_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_USB) -+ case USB_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_USBSTOPCLOCK_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_USBSTOPCLOCK_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_AUDIO) -+ case AUDIO_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_AUDIOSTOPCLOCK_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_AUDIOSTOPCLOCK_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_TS) -+ case TS_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_TSSTOPCLOCK_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_TSSTOPCLOCK_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_SDIO) -+ case SDIO_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SDIOSTOPCLOCK_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SDIOSTOPCLOCK_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_TDM) -+ case TDM_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_TDMSTOPCLOCK_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_TDMSTOPCLOCK_MASK); -+ } -+ break; -+#endif -+ -+ default: -+ -+ break; -+ -+ } -+} -+ -+/******************************************************************************* -+* mvCtrlPwrClckGet - Get Power State of specific Unit -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+******************************************************************************/ -+MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index) -+{ -+ MV_U32 reg = MV_REG_READ(POWER_MNG_CTRL_REG); -+ MV_BOOL state = MV_TRUE; -+ -+ switch (unitId) -+ { -+#if defined(MV_INCLUDE_PEX) -+ case PEX_UNIT_ID: -+ if ((reg & PMC_PEXSTOPCLOCK_MASK) == PMC_PEXSTOPCLOCK_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ -+ break; -+#endif -+#if defined(MV_INCLUDE_GIG_ETH) -+ case ETH_GIG_UNIT_ID: -+ if ((reg & PMC_GESTOPCLOCK_MASK(index)) == PMC_GESTOPCLOCK_STOP(index)) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_SATA) -+ case SATA_UNIT_ID: -+ if ((reg & PMC_SATASTOPCLOCK_MASK(index)) == PMC_SATASTOPCLOCK_STOP(index)) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_CESA) -+ case CESA_UNIT_ID: -+ if ((reg & PMC_SESTOPCLOCK_MASK) == PMC_SESTOPCLOCK_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_USB) -+ case USB_UNIT_ID: -+ if ((reg & PMC_USBSTOPCLOCK_MASK) == PMC_USBSTOPCLOCK_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_AUDIO) -+ case AUDIO_UNIT_ID: -+ if ((reg & PMC_AUDIOSTOPCLOCK_MASK) == PMC_AUDIOSTOPCLOCK_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_TS) -+ case TS_UNIT_ID: -+ if ((reg & PMC_TSSTOPCLOCK_MASK) == PMC_TSSTOPCLOCK_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_SDIO) -+ case SDIO_UNIT_ID: -+ if ((reg & PMC_SDIOSTOPCLOCK_MASK)== PMC_SDIOSTOPCLOCK_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_TDM) -+ case TDM_UNIT_ID: -+ if ((reg & PMC_TDMSTOPCLOCK_MASK) == PMC_TDMSTOPCLOCK_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+ -+ default: -+ state = MV_TRUE; -+ break; -+ } -+ -+ -+ return state; -+} -+/******************************************************************************* -+* mvCtrlPwrMemSet - Set Power State for memory on specific Unit -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+*******************************************************************************/ -+MV_VOID mvCtrlPwrMemSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) -+{ -+ switch (unitId) -+ { -+#if defined(MV_INCLUDE_PEX) -+ case PEX_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_PEXSTOPMEM_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_PEXSTOPMEM_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_GIG_ETH) -+ case ETH_GIG_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_GESTOPMEM_MASK(index)); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_GESTOPMEM_MASK(index)); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_INTEG_SATA) -+ case SATA_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_SATASTOPMEM_MASK(index)); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_SATASTOPMEM_MASK(index)); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_CESA) -+ case CESA_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_SESTOPMEM_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_SESTOPMEM_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_USB) -+ case USB_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_USBSTOPMEM_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_USBSTOPMEM_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_AUDIO) -+ case AUDIO_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_AUDIOSTOPMEM_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_AUDIOSTOPMEM_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_XOR) -+ case XOR_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_XORSTOPMEM_MASK(index)); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_XORSTOPMEM_MASK(index)); -+ } -+ break; -+#endif -+ default: -+ -+ break; -+ -+ } -+} -+ -+/******************************************************************************* -+* mvCtrlPwrMemGet - Get Power State of memory on specific Unit -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+******************************************************************************/ -+MV_BOOL mvCtrlPwrMemGet(MV_UNIT_ID unitId, MV_U32 index) -+{ -+ MV_U32 reg = MV_REG_READ(POWER_MNG_MEM_CTRL_REG); -+ MV_BOOL state = MV_TRUE; -+ -+ switch (unitId) -+ { -+#if defined(MV_INCLUDE_PEX) -+ case PEX_UNIT_ID: -+ if ((reg & PMC_PEXSTOPMEM_MASK) == PMC_PEXSTOPMEM_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ -+ break; -+#endif -+#if defined(MV_INCLUDE_GIG_ETH) -+ case ETH_GIG_UNIT_ID: -+ if ((reg & PMC_GESTOPMEM_MASK(index)) == PMC_GESTOPMEM_STOP(index)) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_SATA) -+ case SATA_UNIT_ID: -+ if ((reg & PMC_SATASTOPMEM_MASK(index)) == PMC_SATASTOPMEM_STOP(index)) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_CESA) -+ case CESA_UNIT_ID: -+ if ((reg & PMC_SESTOPMEM_MASK) == PMC_SESTOPMEM_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_USB) -+ case USB_UNIT_ID: -+ if ((reg & PMC_USBSTOPMEM_MASK) == PMC_USBSTOPMEM_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_AUDIO) -+ case AUDIO_UNIT_ID: -+ if ((reg & PMC_AUDIOSTOPMEM_MASK) == PMC_AUDIOSTOPMEM_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_XOR) -+ case XOR_UNIT_ID: -+ if ((reg & PMC_XORSTOPMEM_MASK(index)) == PMC_XORSTOPMEM_STOP(index)) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+ -+ default: -+ state = MV_TRUE; -+ break; -+ } -+ -+ -+ return state; -+} -+#else -+MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) {return;} -+MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index) {return MV_TRUE;} -+#endif /* #if defined(MV_INCLUDE_CLK_PWR_CNTRL) */ -+ -+ -+/******************************************************************************* -+* mvMPPConfigToSPI - Change MPP[3:0] configuration to SPI mode -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+******************************************************************************/ -+MV_VOID mvMPPConfigToSPI(MV_VOID) -+{ -+ MV_U32 mppVal = 0; -+ MV_U32 bootVal = 0; -+ -+ if(!mvCtrlIsBootFromSPIUseNAND()) -+ return; -+ mppVal = 0x00002220; /* Set MPP [3:1] to SPI mode */ -+ bootVal = MV_REG_READ(mvCtrlMppRegGet(0)); -+ bootVal &= 0xffff000f; -+ mppVal |= bootVal; -+ -+ MV_REG_WRITE(mvCtrlMppRegGet(0), mppVal); -+} -+ -+ -+/******************************************************************************* -+* mvMPPConfigToDefault - Change MPP[7:0] configuration to default configuration -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+******************************************************************************/ -+MV_VOID mvMPPConfigToDefault(MV_VOID) -+{ -+ MV_U32 mppVal = 0; -+ MV_U32 bootVal = 0; -+ -+ if(!mvCtrlIsBootFromSPIUseNAND()) -+ return; -+ mppVal = mvBoardMppGet(0); -+ bootVal = MV_REG_READ(mvCtrlMppRegGet(0)); -+ mppVal &= ~0xffff000f; -+ bootVal &= 0xffff000f; -+ mppVal |= bootVal; -+ -+ MV_REG_WRITE(mvCtrlMppRegGet(0), mppVal); -+} -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,185 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvCtrlEnvLibh -+#define __INCmvCtrlEnvLibh -+ -+/* includes */ -+#include "mvSysHwConfig.h" -+#include "mvCommon.h" -+#include "mvTypes.h" -+#include "mvOs.h" -+#include "boardEnv/mvBoardEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+#include "ctrlEnv/mvCtrlEnvRegs.h" -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+ -+ -+/* typedefs */ -+ -+/* This enumerator describes the possible HW cache coherency policies the */ -+/* controllers supports. */ -+typedef enum _mvCachePolicy -+{ -+ NO_COHERENCY, /* No HW cache coherency support */ -+ WT_COHERENCY, /* HW cache coherency supported in Write Through policy */ -+ WB_COHERENCY /* HW cache coherency supported in Write Back policy */ -+}MV_CACHE_POLICY; -+ -+ -+/* The swapping is referred to a 64-bit words (as this is the controller */ -+/* internal data path width). This enumerator describes the possible */ -+/* data swap types. Below is an example of the data 0x0011223344556677 */ -+typedef enum _mvSwapType -+{ -+ MV_BYTE_SWAP, /* Byte Swap 77 66 55 44 33 22 11 00 */ -+ MV_NO_SWAP, /* No swapping 00 11 22 33 44 55 66 77 */ -+ MV_BYTE_WORD_SWAP, /* Both byte and word swap 33 22 11 00 77 66 55 44 */ -+ MV_WORD_SWAP, /* Word swap 44 55 66 77 00 11 22 33 */ -+ SWAP_TYPE_MAX /* Delimiter for this enumerator */ -+}MV_SWAP_TYPE; -+ -+/* This structure describes access rights for Access protection windows */ -+/* that can be found in IDMA, XOR, Ethernet and MPSC units. */ -+/* Note that the permission enumerator coresponds to its register format. */ -+/* For example, Read only premission is presented as "1" in register field. */ -+typedef enum _mvAccessRights -+{ -+ NO_ACCESS_ALLOWED = 0, /* No access allowed */ -+ READ_ONLY = 1, /* Read only permission */ -+ ACC_RESERVED = 2, /* Reserved access right */ -+ FULL_ACCESS = 3, /* Read and Write permission */ -+ MAX_ACC_RIGHTS -+}MV_ACCESS_RIGHTS; -+ -+ -+/* mcspLib.h API list */ -+ -+MV_STATUS mvCtrlEnvInit(MV_VOID); -+MV_U32 mvCtrlMppRegGet(MV_U32 mppGroup); -+ -+#if defined(MV_INCLUDE_PEX) -+MV_U32 mvCtrlPexMaxIfGet(MV_VOID); -+#else -+#define mvCtrlPexMaxIfGet() (0) -+#endif -+ -+#define mvCtrlPciIfMaxIfGet() (0) -+ -+#if defined(MV_INCLUDE_GIG_ETH) -+MV_U32 mvCtrlEthMaxPortGet(MV_VOID); -+#endif -+#if defined(MV_INCLUDE_XOR) -+MV_U32 mvCtrlXorMaxChanGet(MV_VOID); -+#endif -+#if defined(MV_INCLUDE_USB) -+MV_U32 mvCtrlUsbMaxGet(MV_VOID); -+#endif -+#if defined(MV_INCLUDE_NAND) -+MV_U32 mvCtrlNandSupport(MV_VOID); -+#endif -+#if defined(MV_INCLUDE_SDIO) -+MV_U32 mvCtrlSdioSupport(MV_VOID); -+#endif -+#if defined(MV_INCLUDE_TS) -+MV_U32 mvCtrlTsSupport(MV_VOID); -+#endif -+#if defined(MV_INCLUDE_AUDIO) -+MV_U32 mvCtrlAudioSupport(MV_VOID); -+#endif -+#if defined(MV_INCLUDE_TDM) -+MV_U32 mvCtrlTdmSupport(MV_VOID); -+#endif -+ -+MV_U16 mvCtrlModelGet(MV_VOID); -+MV_U8 mvCtrlRevGet(MV_VOID); -+MV_STATUS mvCtrlNameGet(char *pNameBuff); -+MV_U32 mvCtrlModelRevGet(MV_VOID); -+MV_STATUS mvCtrlModelRevNameGet(char *pNameBuff); -+MV_VOID mvCtrlAddrDecShow(MV_VOID); -+const MV_8* mvCtrlTargetNameGet(MV_TARGET target); -+MV_U32 ctrlSizeToReg(MV_U32 size, MV_U32 alignment); -+MV_U32 ctrlRegToSize(MV_U32 regSize, MV_U32 alignment); -+MV_U32 ctrlSizeRegRoundUp(MV_U32 size, MV_U32 alignment); -+MV_U32 mvCtrlSysRstLengthCounterGet(MV_VOID); -+MV_STATUS ctrlWinOverlapTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2); -+MV_STATUS ctrlWinWithinWinTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2); -+ -+MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable); -+MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index); -+MV_VOID mvCtrlPwrMemSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable); -+MV_BOOL mvCtrlIsBootFromSPI(MV_VOID); -+MV_BOOL mvCtrlIsBootFromSPIUseNAND(MV_VOID); -+MV_BOOL mvCtrlIsBootFromNAND(MV_VOID); -+#if defined(MV_INCLUDE_CLK_PWR_CNTRL) -+MV_VOID mvCtrlPwrSaveOn(MV_VOID); -+MV_VOID mvCtrlPwrSaveOff(MV_VOID); -+#endif -+MV_BOOL mvCtrlPwrMemGet(MV_UNIT_ID unitId, MV_U32 index); -+MV_VOID mvMPPConfigToSPI(MV_VOID); -+MV_VOID mvMPPConfigToDefault(MV_VOID); -+ -+ -+#endif /* __INCmvCtrlEnvLibh */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,419 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvCtrlEnvRegsh -+#define __INCmvCtrlEnvRegsh -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* CV Support */ -+#define PEX0_MEM0 PEX0_MEM -+#define PCI0_MEM0 PEX0_MEM -+ -+/* Controller revision info */ -+#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 -+#define PCCRIR_REVID_OFFS 0 /* Revision ID */ -+#define PCCRIR_REVID_MASK (0xff << PCCRIR_REVID_OFFS) -+ -+/* Controler environment registers offsets */ -+ -+/* Power Managment Control */ -+#define POWER_MNG_MEM_CTRL_REG 0x20118 -+ -+#define PMC_GESTOPMEM_OFFS(port) ((port)? 13 : 0) -+#define PMC_GESTOPMEM_MASK(port) (1 << PMC_GESTOPMEM_OFFS(port)) -+#define PMC_GESTOPMEM_EN(port) (0 << PMC_GESTOPMEM_OFFS(port)) -+#define PMC_GESTOPMEM_STOP(port) (1 << PMC_GESTOPMEM_OFFS(port)) -+ -+#define PMC_PEXSTOPMEM_OFFS 1 -+#define PMC_PEXSTOPMEM_MASK (1 << PMC_PEXSTOPMEM_OFFS) -+#define PMC_PEXSTOPMEM_EN (0 << PMC_PEXSTOPMEM_OFFS) -+#define PMC_PEXSTOPMEM_STOP (1 << PMC_PEXSTOPMEM_OFFS) -+ -+#define PMC_USBSTOPMEM_OFFS 2 -+#define PMC_USBSTOPMEM_MASK (1 << PMC_USBSTOPMEM_OFFS) -+#define PMC_USBSTOPMEM_EN (0 << PMC_USBSTOPMEM_OFFS) -+#define PMC_USBSTOPMEM_STOP (1 << PMC_USBSTOPMEM_OFFS) -+ -+#define PMC_DUNITSTOPMEM_OFFS 3 -+#define PMC_DUNITSTOPMEM_MASK (1 << PMC_DUNITSTOPMEM_OFFS) -+#define PMC_DUNITSTOPMEM_EN (0 << PMC_DUNITSTOPMEM_OFFS) -+#define PMC_DUNITSTOPMEM_STOP (1 << PMC_DUNITSTOPMEM_OFFS) -+ -+#define PMC_RUNITSTOPMEM_OFFS 4 -+#define PMC_RUNITSTOPMEM_MASK (1 << PMC_RUNITSTOPMEM_OFFS) -+#define PMC_RUNITSTOPMEM_EN (0 << PMC_RUNITSTOPMEM_OFFS) -+#define PMC_RUNITSTOPMEM_STOP (1 << PMC_RUNITSTOPMEM_OFFS) -+ -+#define PMC_XORSTOPMEM_OFFS(port) (5+(port*2)) -+#define PMC_XORSTOPMEM_MASK(port) (1 << PMC_XORSTOPMEM_OFFS(port)) -+#define PMC_XORSTOPMEM_EN(port) (0 << PMC_XORSTOPMEM_OFFS(port)) -+#define PMC_XORSTOPMEM_STOP(port) (1 << PMC_XORSTOPMEM_OFFS(port)) -+ -+#define PMC_SATASTOPMEM_OFFS(port) (6+(port*5)) -+#define PMC_SATASTOPMEM_MASK(port) (1 << PMC_SATASTOPMEM_OFFS(port)) -+#define PMC_SATASTOPMEM_EN(port) (0 << PMC_SATASTOPMEM_OFFS(port)) -+#define PMC_SATASTOPMEM_STOP(port) (1 << PMC_SATASTOPMEM_OFFS(port)) -+ -+#define PMC_SESTOPMEM_OFFS 8 -+#define PMC_SESTOPMEM_MASK (1 << PMC_SESTOPMEM_OFFS) -+#define PMC_SESTOPMEM_EN (0 << PMC_SESTOPMEM_OFFS) -+#define PMC_SESTOPMEM_STOP (1 << PMC_SESTOPMEM_OFFS) -+ -+#define PMC_AUDIOSTOPMEM_OFFS 9 -+#define PMC_AUDIOSTOPMEM_MASK (1 << PMC_AUDIOSTOPMEM_OFFS) -+#define PMC_AUDIOSTOPMEM_EN (0 << PMC_AUDIOSTOPMEM_OFFS) -+#define PMC_AUDIOSTOPMEM_STOP (1 << PMC_AUDIOSTOPMEM_OFFS) -+ -+#define POWER_MNG_CTRL_REG 0x2011C -+ -+#define PMC_GESTOPCLOCK_OFFS(port) ((port)? 19 : 0) -+#define PMC_GESTOPCLOCK_MASK(port) (1 << PMC_GESTOPCLOCK_OFFS(port)) -+#define PMC_GESTOPCLOCK_EN(port) (1 << PMC_GESTOPCLOCK_OFFS(port)) -+#define PMC_GESTOPCLOCK_STOP(port) (0 << PMC_GESTOPCLOCK_OFFS(port)) -+ -+#define PMC_PEXPHYSTOPCLOCK_OFFS 1 -+#define PMC_PEXPHYSTOPCLOCK_MASK (1 << PMC_PEXPHYSTOPCLOCK_OFFS) -+#define PMC_PEXPHYSTOPCLOCK_EN (1 << PMC_PEXPHYSTOPCLOCK_OFFS) -+#define PMC_PEXPHYSTOPCLOCK_STOP (0 << PMC_PEXPHYSTOPCLOCK_OFFS) -+ -+#define PMC_PEXSTOPCLOCK_OFFS 2 -+#define PMC_PEXSTOPCLOCK_MASK (1 << PMC_PEXSTOPCLOCK_OFFS) -+#define PMC_PEXSTOPCLOCK_EN (1 << PMC_PEXSTOPCLOCK_OFFS) -+#define PMC_PEXSTOPCLOCK_STOP (0 << PMC_PEXSTOPCLOCK_OFFS) -+ -+#define PMC_USBSTOPCLOCK_OFFS 3 -+#define PMC_USBSTOPCLOCK_MASK (1 << PMC_USBSTOPCLOCK_OFFS) -+#define PMC_USBSTOPCLOCK_EN (1 << PMC_USBSTOPCLOCK_OFFS) -+#define PMC_USBSTOPCLOCK_STOP (0 << PMC_USBSTOPCLOCK_OFFS) -+ -+#define PMC_SDIOSTOPCLOCK_OFFS 4 -+#define PMC_SDIOSTOPCLOCK_MASK (1 << PMC_SDIOSTOPCLOCK_OFFS) -+#define PMC_SDIOSTOPCLOCK_EN (1 << PMC_SDIOSTOPCLOCK_OFFS) -+#define PMC_SDIOSTOPCLOCK_STOP (0 << PMC_SDIOSTOPCLOCK_OFFS) -+ -+#define PMC_TSSTOPCLOCK_OFFS 5 -+#define PMC_TSSTOPCLOCK_MASK (1 << PMC_TSSTOPCLOCK_OFFS) -+#define PMC_TSSTOPCLOCK_EN (1 << PMC_TSSTOPCLOCK_OFFS) -+#define PMC_TSSTOPCLOCK_STOP (0 << PMC_TSSTOPCLOCK_OFFS) -+ -+#define PMC_AUDIOSTOPCLOCK_OFFS 9 -+#define PMC_AUDIOSTOPCLOCK_MASK (1 << PMC_AUDIOSTOPCLOCK_OFFS) -+#define PMC_AUDIOSTOPCLOCK_EN (1 << PMC_AUDIOSTOPCLOCK_OFFS) -+#define PMC_AUDIOSTOPCLOCK_STOP (0 << PMC_AUDIOSTOPCLOCK_OFFS) -+ -+#define PMC_POWERSAVE_OFFS 11 -+#define PMC_POWERSAVE_MASK (1 << PMC_POWERSAVE_OFFS) -+#define PMC_POWERSAVE_EN (1 << PMC_POWERSAVE_OFFS) -+#define PMC_POWERSAVE_STOP (0 << PMC_POWERSAVE_OFFS) -+ -+ -+ -+ -+#define PMC_SATASTOPCLOCK_OFFS(port) (14+(port)) -+#define PMC_SATASTOPCLOCK_MASK(port) (1 << PMC_SATASTOPCLOCK_OFFS(port)) -+#define PMC_SATASTOPCLOCK_EN(port) (1 << PMC_SATASTOPCLOCK_OFFS(port)) -+#define PMC_SATASTOPCLOCK_STOP(port) (0 << PMC_SATASTOPCLOCK_OFFS(port)) -+ -+#define PMC_SESTOPCLOCK_OFFS 17 -+#define PMC_SESTOPCLOCK_MASK (1 << PMC_SESTOPCLOCK_OFFS) -+#define PMC_SESTOPCLOCK_EN (1 << PMC_SESTOPCLOCK_OFFS) -+#define PMC_SESTOPCLOCK_STOP (0 << PMC_SESTOPCLOCK_OFFS) -+ -+#define PMC_TDMSTOPCLOCK_OFFS 20 -+#define PMC_TDMSTOPCLOCK_MASK (1 << PMC_TDMSTOPCLOCK_OFFS) -+#define PMC_TDMSTOPCLOCK_EN (1 << PMC_TDMSTOPCLOCK_OFFS) -+#define PMC_TDMSTOPCLOCK_STOP (0 << PMC_TDMSTOPCLOCK_OFFS) -+ -+ -+/* Controler environment registers offsets */ -+#define MPP_CONTROL_REG0 0x10000 -+#define MPP_CONTROL_REG1 0x10004 -+#define MPP_CONTROL_REG2 0x10008 -+#define MPP_CONTROL_REG3 0x1000C -+#define MPP_CONTROL_REG4 0x10010 -+#define MPP_CONTROL_REG5 0x10014 -+#define MPP_CONTROL_REG6 0x10018 -+#define MPP_SAMPLE_AT_RESET 0x10030 -+#define CHIP_BOND_REG 0x10034 -+#define SYSRST_LENGTH_COUNTER_REG 0x10050 -+#define SLCR_COUNT_OFFS 0 -+#define SLCR_COUNT_MASK (0x1FFFFFFF << SLCR_COUNT_OFFS) -+#define SLCR_CLR_OFFS 31 -+#define SLCR_CLR_MASK (1 << SLCR_CLR_OFFS) -+#define PCKG_OPT_MASK 0x3 -+#define MPP_OUTPUT_DRIVE_REG 0x100E0 -+#define MPP_RGMII0_OUTPUT_DRIVE_OFFS 7 -+#define MPP_3_3_RGMII0_OUTPUT_DRIVE (0x0 << MPP_RGMII0_OUTPUT_DRIVE_OFFS) -+#define MPP_1_8_RGMII0_OUTPUT_DRIVE (0x1 << MPP_RGMII0_OUTPUT_DRIVE_OFFS) -+#define MPP_RGMII1_OUTPUT_DRIVE_OFFS 15 -+#define MPP_3_3_RGMII1_OUTPUT_DRIVE (0x0 << MPP_RGMII1_OUTPUT_DRIVE_OFFS) -+#define MPP_1_8_RGMII1_OUTPUT_DRIVE (0x1 << MPP_RGMII1_OUTPUT_DRIVE_OFFS) -+ -+#define MSAR_BOOT_MODE_OFFS 12 -+#define MSAR_BOOT_MODE_MASK (0x7 << MSAR_BOOT_MODE_OFFS) -+#define MSAR_BOOT_NAND_WITH_BOOTROM (0x5 << MSAR_BOOT_MODE_OFFS) -+#define MSAR_BOOT_SPI_WITH_BOOTROM (0x4 << MSAR_BOOT_MODE_OFFS) -+#define MSAR_BOOT_SPI_USE_NAND_WITH_BOOTROM (0x2 << MSAR_BOOT_MODE_OFFS) -+ -+#define MSAR_BOOT_MODE_6180(X) (((X & 0x3000) >> 12) | \ -+ ((X & 0x2) << 1)) -+#define MSAR_BOOT_SPI_WITH_BOOTROM_6180 0x1 -+#define MSAR_BOOT_NAND_WITH_BOOTROM_6180 0x5 -+ -+#define MSAR_TCLCK_OFFS 21 -+#define MSAR_TCLCK_MASK (0x1 << MSAR_TCLCK_OFFS) -+#define MSAR_TCLCK_166 (0x1 << MSAR_TCLCK_OFFS) -+#define MSAR_TCLCK_200 (0x0 << MSAR_TCLCK_OFFS) -+ -+ -+#define MSAR_CPUCLCK_EXTRACT(X) (((X & 0x2) >> 1) | ((X & 0x400000) >> 21) | \ -+ ((X & 0x18) >> 1)) -+ -+#define MSAR_CPUCLCK_OFFS_6180 2 -+#define MSAR_CPUCLCK_MASK_6180 (0x7 << MSAR_CPUCLCK_OFFS_6180) -+ -+#define MSAR_DDRCLCK_RTIO_OFFS 5 -+#define MSAR_DDRCLCK_RTIO_MASK (0xF << MSAR_DDRCLCK_RTIO_OFFS) -+ -+#define MSAR_L2CLCK_EXTRACT(X) (((X & 0x600) >> 9) | ((X & 0x80000) >> 17)) -+ -+#ifndef MV_ASMLANGUAGE -+/* CPU clock for 6281,6192 0->Resereved */ -+#define MV_CPU_CLCK_TBL { 0, 0, 0, 0, \ -+ 600000000, 0, 800000000, 1000000000, \ -+ 0, 1200000000, 0, 0, \ -+ 1500000000, 0, 0, 0} -+ -+/* DDR clock RATIO for 6281,6192 {0,0}->Reserved */ -+#define MV_DDR_CLCK_RTIO_TBL {\ -+ {0, 0}, {0, 0}, {2, 1}, {0, 0}, \ -+ {3, 1}, {0, 0}, {4, 1}, {9, 2}, \ -+ {5, 1}, {6, 1}, {0, 0}, {0, 0}, \ -+ {0, 0}, {0, 0}, {0, 0}, {0, 0} \ -+} -+ -+/* L2 clock RATIO for 6281,6192 {1,1}->Reserved */ -+#define MV_L2_CLCK_RTIO_TBL {\ -+ {0, 0}, {2, 1}, {0, 0}, {3, 1}, \ -+ {0, 0}, {0, 0}, {0, 0}, {0, 0} \ -+} -+ -+/* 6180 have different clk reset sampling */ -+/* ARM CPU, DDR, L2 clock for 6180 {0,0,0}->Reserved */ -+#define MV_CPU6180_DDR_L2_CLCK_TBL { \ -+ {0, 0, 0 },\ -+ {0, 0, 0 },\ -+ {0, 0, 0 },\ -+ {0, 0, 0 },\ -+ {0, 0, 0 },\ -+ {600000000, 200000000, 300000000 },\ -+ {800000000, 200000000, 400000000 },\ -+ {0, 0, 0 }\ -+} -+ -+ -+ -+/* These macros help units to identify a target Mbus Arbiter group */ -+#define MV_TARGET_IS_DRAM(target) \ -+ ((target >= SDRAM_CS0) && (target <= SDRAM_CS3)) -+ -+#define MV_TARGET_IS_PEX0(target) \ -+ ((target >= PEX0_MEM) && (target <= PEX0_IO)) -+ -+#define MV_TARGET_IS_PEX1(target) 0 -+ -+#define MV_TARGET_IS_PEX(target) (MV_TARGET_IS_PEX0(target) || MV_TARGET_IS_PEX1(target)) -+ -+#define MV_TARGET_IS_DEVICE(target) \ -+ ((target >= DEVICE_CS0) && (target <= DEVICE_CS3)) -+ -+#define MV_PCI_DRAM_BAR_TO_DRAM_TARGET(bar) 0 -+ -+#define MV_TARGET_IS_AS_BOOT(target) ((target) == (sampleAtResetTargetArray[ \ -+ (mvCtrlModelGet() == MV_6180_DEV_ID)? MSAR_BOOT_MODE_6180 \ -+ (MV_REG_READ(MPP_SAMPLE_AT_RESET)):((MV_REG_READ(MPP_SAMPLE_AT_RESET)\ -+ & MSAR_BOOT_MODE_MASK) >> MSAR_BOOT_MODE_OFFS)])) -+ -+ -+#define MV_CHANGE_BOOT_CS(target) (((target) == DEV_BOOCS)?\ -+ sampleAtResetTargetArray[(mvCtrlModelGet() == MV_6180_DEV_ID)? \ -+ MSAR_BOOT_MODE_6180(MV_REG_READ(MPP_SAMPLE_AT_RESET)): \ -+ ((MV_REG_READ(MPP_SAMPLE_AT_RESET) & MSAR_BOOT_MODE_MASK)\ -+ >> MSAR_BOOT_MODE_OFFS)]:(target)) -+ -+#define TCLK_TO_COUNTER_RATIO 1 /* counters running in Tclk */ -+ -+#define BOOT_TARGETS_NAME_ARRAY { \ -+ TBL_TERM, \ -+ TBL_TERM, \ -+ BOOT_ROM_CS, \ -+ TBL_TERM, \ -+ BOOT_ROM_CS, \ -+ BOOT_ROM_CS, \ -+ TBL_TERM, \ -+ TBL_TERM \ -+} -+ -+#define BOOT_TARGETS_NAME_ARRAY_6180 { \ -+ TBL_TERM, \ -+ BOOT_ROM_CS, \ -+ TBL_TERM, \ -+ TBL_TERM, \ -+ TBL_TERM, \ -+ BOOT_ROM_CS, \ -+ TBL_TERM, \ -+ TBL_TERM \ -+} -+ -+ -+/* For old competability */ -+#define DEVICE_CS0 NFLASH_CS -+#define DEVICE_CS1 SPI_CS -+#define DEVICE_CS2 BOOT_ROM_CS -+#define DEVICE_CS3 DEV_BOOCS -+#define MV_BOOTDEVICE_INDEX 0 -+ -+#define START_DEV_CS DEV_CS0 -+#define DEV_TO_TARGET(dev) ((dev) + DEVICE_CS0) -+ -+#define PCI_IF0_MEM0 PEX0_MEM -+#define PCI_IF0_IO PEX0_IO -+ -+ -+/* This enumerator defines the Marvell controller target ID */ -+typedef enum _mvTargetId -+{ -+ DRAM_TARGET_ID = 0 , /* Port 0 -> DRAM interface */ -+ DEV_TARGET_ID = 1, /* Port 1 -> Nand/SPI */ -+ PEX0_TARGET_ID = 4 , /* Port 4 -> PCI Express0 */ -+ CRYPT_TARGET_ID = 3 , /* Port 3 --> Crypto Engine */ -+ SAGE_TARGET_ID = 12 , /* Port 12 -> SAGE Unit */ -+ MAX_TARGETS_ID -+}MV_TARGET_ID; -+ -+ -+/* This enumerator described the possible Controller paripheral targets. */ -+/* Controller peripherals are designated memory/IO address spaces that the */ -+/* controller can access. They are also refered as "targets" */ -+typedef enum _mvTarget -+{ -+ TBL_TERM = -1, /* none valid target, used as targets list terminator*/ -+ SDRAM_CS0, /* SDRAM chip select 0 */ -+ SDRAM_CS1, /* SDRAM chip select 1 */ -+ SDRAM_CS2, /* SDRAM chip select 2 */ -+ SDRAM_CS3, /* SDRAM chip select 3 */ -+ PEX0_MEM, /* PCI Express 0 Memory */ -+ PEX0_IO, /* PCI Express 0 IO */ -+ INTER_REGS, /* Internal registers */ -+ NFLASH_CS, /* NFLASH_CS */ -+ SPI_CS, /* SPI_CS */ -+ BOOT_ROM_CS, /* BOOT_ROM_CS */ -+ DEV_BOOCS, /* DEV_BOOCS */ -+ CRYPT_ENG, /* Crypto Engine */ -+#ifdef MV_INCLUDE_SAGE -+ SAGE_UNIT, /* SAGE Unit */ -+#endif -+ MAX_TARGETS -+ -+}MV_TARGET; -+ -+#define TARGETS_DEF_ARRAY { \ -+ {0x0E, DRAM_TARGET_ID }, /* SDRAM_CS0 */ \ -+ {0x0D, DRAM_TARGET_ID }, /* SDRAM_CS1 */ \ -+ {0x0B, DRAM_TARGET_ID }, /* SDRAM_CS0 */ \ -+ {0x07, DRAM_TARGET_ID }, /* SDRAM_CS1 */ \ -+ {0xE8, PEX0_TARGET_ID }, /* PEX0_MEM */ \ -+ {0xE0, PEX0_TARGET_ID }, /* PEX0_IO */ \ -+ {0xFF, 0xFF }, /* INTER_REGS */ \ -+ {0x2F, DEV_TARGET_ID }, /* NFLASH_CS */ \ -+ {0x1E, DEV_TARGET_ID }, /* SPI_CS */ \ -+ {0x1D, DEV_TARGET_ID }, /* BOOT_ROM_CS */ \ -+ {0x1E, DEV_TARGET_ID }, /* DEV_BOOCS */ \ -+ {0x01, CRYPT_TARGET_ID}, /* CRYPT_ENG */ \ -+ {0x00, SAGE_TARGET_ID } \ -+} -+ -+ -+#define TARGETS_NAME_ARRAY { \ -+ "SDRAM_CS0", /* SDRAM_CS0 */ \ -+ "SDRAM_CS1", /* SDRAM_CS1 */ \ -+ "SDRAM_CS2", /* SDRAM_CS2 */ \ -+ "SDRAM_CS3", /* SDRAM_CS3 */ \ -+ "PEX0_MEM", /* PEX0_MEM */ \ -+ "PEX0_IO", /* PEX0_IO */ \ -+ "INTER_REGS", /* INTER_REGS */ \ -+ "NFLASH_CS", /* NFLASH_CS */ \ -+ "SPI_CS", /* SPI_CS */ \ -+ "BOOT_ROM_CS", /* BOOT_ROM_CS */ \ -+ "DEV_BOOTCS", /* DEV_BOOCS */ \ -+ "CRYPT_ENG", /* CRYPT_ENG */ \ -+ "SAGE_UNIT" /* SAGE_UNIT */ \ -+} -+#endif /* MV_ASMLANGUAGE */ -+ -+ -+#endif -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,257 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvCtrlEnvSpech -+#define __INCmvCtrlEnvSpech -+ -+#include "mvDeviceId.h" -+#include "mvSysHwConfig.h" -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+#define MV_ARM_SOC -+#define SOC_NAME_PREFIX "MV88F" -+ -+ -+/* units base and port numbers */ -+#ifdef MV_ASMLANGUAGE -+#define XOR_UNIT_BASE(unit) 0x60800 -+#else -+#define MV_XOR_REG_BASE 0x60000 -+#define XOR_UNIT_BASE(unit) ((unit)? 0x60900:0x60800) -+#endif -+ -+#define TDM_REG_BASE 0xD0000 -+#define USB_REG_BASE(dev) 0x50000 -+#define AUDIO_REG_BASE 0xA0000 -+#define SATA_REG_BASE 0x80000 -+#define MV_CESA_REG_BASE 0x3D000 -+#define MV_CESA_TDMA_REG_BASE 0x30000 -+#define MV_SDIO_REG_BASE 0x90000 -+#define MV_ETH_REG_BASE(port) (((port) == 0) ? 0x72000 : 0x76000) -+#define MV_UART_CHAN_BASE(chanNum) (0x12000 + (chanNum * 0x100)) -+#define DRAM_BASE 0x0 -+#define CNTMR_BASE 0x20300 -+#define TWSI_SLAVE_BASE(chanNum) 0x11000 -+#define PEX_IF_BASE(pexIf) 0x40000 -+#define MPP_REG_BASE 0x10000 -+#define TSU_GLOBAL_REG_BASE 0xB4000 -+#define MAX_AHB_TO_MBUS_REG_BASE 0x20000 -+ -+#define INTER_REGS_SIZE _1M -+/* This define describes the TWSI interrupt bit and location */ -+#define TWSI_CPU_MAIN_INT_CAUSE_REG 0x20200 -+#define TWSI0_CPU_MAIN_INT_BIT (1<<29) -+#define TWSI_SPEED 100000 -+ -+#define MV_GPP_MAX_GROUP 2 -+#define MV_CNTMR_MAX_COUNTER 2 -+#define MV_UART_MAX_CHAN 2 -+#define MV_XOR_MAX_UNIT 2 -+#define MV_XOR_MAX_CHAN 4 /* total channels for all units together*/ -+#define MV_XOR_MAX_CHAN_PER_UNIT 2 /* channels for units */ -+#define MV_SATA_MAX_CHAN 2 -+ -+#define MV_6281_MPP_MAX_MODULE 2 -+#define MV_6192_MPP_MAX_MODULE 1 -+#define MV_6190_MPP_MAX_MODULE 1 -+#define MV_6180_MPP_MAX_MODULE 2 -+#define MV_6281_MPP_MAX_GROUP 7 -+#define MV_6192_MPP_MAX_GROUP 4 -+#define MV_6190_MPP_MAX_GROUP 4 -+#define MV_6180_MPP_MAX_GROUP 3 -+ -+#define MV_DRAM_MAX_CS 4 -+ -+/* This define describes the maximum number of supported PCI\PCIX Interfaces*/ -+#define MV_PCI_MAX_IF 0 -+#define MV_PCI_START_IF 0 -+ -+/* This define describes the maximum number of supported PEX Interfaces */ -+#define MV_INCLUDE_PEX0 -+#define MV_DISABLE_PEX_DEVICE_BAR -+#define MV_PEX_MAX_IF 1 -+#define MV_PEX_START_IF MV_PCI_MAX_IF -+ -+/* This define describes the maximum number of supported PCI Interfaces */ -+#define MV_PCI_IF_MAX_IF (MV_PEX_MAX_IF+MV_PCI_MAX_IF) -+ -+#define MV_ETH_MAX_PORTS 2 -+#define MV_6281_ETH_MAX_PORTS 2 -+#define MV_6192_ETH_MAX_PORTS 2 -+#define MV_6190_ETH_MAX_PORTS 1 -+#define MV_6180_ETH_MAX_PORTS 1 -+ -+#define MV_IDMA_MAX_CHAN 0 -+ -+#define MV_USB_MAX_PORTS 1 -+ -+#define MV_USB_VERSION 1 -+ -+ -+#define MV_6281_NAND 1 -+#define MV_6192_NAND 1 -+#define MV_6190_NAND 1 -+#define MV_6180_NAND 0 -+ -+#define MV_6281_SDIO 1 -+#define MV_6192_SDIO 1 -+#define MV_6190_SDIO 1 -+#define MV_6180_SDIO 1 -+ -+#define MV_6281_TS 1 -+#define MV_6192_TS 1 -+#define MV_6190_TS 0 -+#define MV_6180_TS 0 -+ -+#define MV_6281_AUDIO 1 -+#define MV_6192_AUDIO 1 -+#define MV_6190_AUDIO 0 -+#define MV_6180_AUDIO 1 -+ -+#define MV_6281_TDM 1 -+#define MV_6192_TDM 1 -+#define MV_6190_TDM 0 -+#define MV_6180_TDM 0 -+ -+#define MV_DEVICE_MAX_CS 4 -+ -+/* Others */ -+#define PEX_HOST_BUS_NUM(pciIf) (pciIf) -+#define PEX_HOST_DEV_NUM(pciIf) 0 -+ -+#define PCI_IO(pciIf) (PEX0_IO) -+#define PCI_MEM(pciIf, memNum) (PEX0_MEM0) -+/* CESA version #2: One channel, 2KB SRAM, TDMA */ -+#if defined(MV_CESA_CHAIN_MODE_SUPPORT) -+ #define MV_CESA_VERSION 3 -+#else -+#define MV_CESA_VERSION 2 -+#endif -+#define MV_CESA_SRAM_SIZE 2*1024 -+/* This define describes the maximum number of supported Ethernet ports */ -+#define MV_ETH_VERSION 4 -+#define MV_ETH_MAX_RXQ 8 -+#define MV_ETH_MAX_TXQ 8 -+#define MV_ETH_PORT_SGMII { MV_FALSE, MV_FALSE } -+/* This define describes the the support of USB */ -+#define MV_USB_VERSION 1 -+ -+#define MV_INCLUDE_SDRAM_CS0 -+#define MV_INCLUDE_SDRAM_CS1 -+#define MV_INCLUDE_SDRAM_CS2 -+#define MV_INCLUDE_SDRAM_CS3 -+ -+#define MV_INCLUDE_DEVICE_CS0 -+#define MV_INCLUDE_DEVICE_CS1 -+#define MV_INCLUDE_DEVICE_CS2 -+#define MV_INCLUDE_DEVICE_CS3 -+ -+#define MPP_GROUP_1_TYPE {\ -+ {0, 0, 0}, /* Reserved for AUTO */ \ -+ {0x22220000, 0x22222222, 0x2222}, /* TDM */ \ -+ {0x44440000, 0x00044444, 0x0000}, /* AUDIO */ \ -+ {0x33330000, 0x33003333, 0x0033}, /* RGMII */ \ -+ {0x33330000, 0x03333333, 0x0033}, /* GMII */ \ -+ {0x11110000, 0x11111111, 0x0001}, /* TS */ \ -+ {0x33330000, 0x33333333, 0x3333} /* MII */ \ -+} -+ -+#define MPP_GROUP_2_TYPE {\ -+ {0, 0, 0}, /* Reserved for AUTO */ \ -+ {0x22220000, 0x22222222, 0x22}, /* TDM */ \ -+ {0x44440000, 0x00044444, 0x0}, /* AUDIO */ \ -+ {0, 0, 0}, /* N_A */ \ -+ {0, 0, 0}, /* N_A */ \ -+ {0x11110000, 0x11111111, 0x01} /* TS */ \ -+} -+ -+#ifndef MV_ASMLANGUAGE -+ -+/* This enumerator defines the Marvell Units ID */ -+typedef enum _mvUnitId -+{ -+ DRAM_UNIT_ID, -+ PEX_UNIT_ID, -+ ETH_GIG_UNIT_ID, -+ USB_UNIT_ID, -+ IDMA_UNIT_ID, -+ XOR_UNIT_ID, -+ SATA_UNIT_ID, -+ TDM_UNIT_ID, -+ UART_UNIT_ID, -+ CESA_UNIT_ID, -+ SPI_UNIT_ID, -+ AUDIO_UNIT_ID, -+ SDIO_UNIT_ID, -+ TS_UNIT_ID, -+ MAX_UNITS_ID -+ -+}MV_UNIT_ID; -+ -+#endif -+ -+#endif /* __INCmvCtrlEnvSpech */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,1048 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+/* includes */ -+#include "ctrlEnv/sys/mvAhbToMbus.h" -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+ -+#undef MV_DEBUG -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+/* typedefs */ -+ -+ -+/* CPU address remap registers offsets are inconsecutive. This struct */ -+/* describes address remap register offsets */ -+typedef struct _ahbToMbusRemapRegOffs -+{ -+ MV_U32 lowRegOffs; /* Low 32-bit remap register offset */ -+ MV_U32 highRegOffs; /* High 32 bit remap register offset */ -+}AHB_TO_MBUS_REMAP_REG_OFFS; -+ -+/* locals */ -+static MV_STATUS ahbToMbusRemapRegOffsGet (MV_U32 winNum, -+ AHB_TO_MBUS_REMAP_REG_OFFS *pRemapRegs); -+ -+/******************************************************************************* -+* mvAhbToMbusInit - Initialize Ahb To Mbus Address Map ! -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK laways. -+* -+*******************************************************************************/ -+MV_STATUS mvAhbToMbusInit(void) -+{ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvAhbToMbusWinSet - Set CPU-to-peripheral winNum address window -+* -+* DESCRIPTION: -+* This function sets -+* address window, also known as address decode window. -+* A new address decode window is set for specified winNum address window. -+* If address decode window parameter structure enables the window, -+* the routine will also enable the winNum window, allowing CPU to access -+* the winNum window. -+* -+* INPUT: -+* winNum - Windows number. -+* pAddrDecWin - CPU winNum window data structure. -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_OK if CPU winNum window was set correctly, MV_ERROR in case of -+* address window overlapps with other active CPU winNum window or -+* trying to assign 36bit base address while CPU does not support that. -+* The function returns MV_NOT_SUPPORTED, if the winNum is unsupported. -+* -+*******************************************************************************/ -+MV_STATUS mvAhbToMbusWinSet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin) -+{ -+ MV_TARGET_ATTRIB targetAttribs; -+ MV_DEC_REGS decRegs; -+ -+ /* Parameter checking */ -+ if (winNum >= MAX_AHB_TO_MBUS_WINS) -+ { -+ mvOsPrintf("mvAhbToMbusWinSet: ERR. Invalid winNum %d\n", winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ -+ /* read base register*/ -+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum)); -+ } -+ else -+ { -+ decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_INTEREG_REG); -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvAhbToMbusWinSet:Error setting AHB to MBUS window %d to "\ -+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, -+ mvCtrlTargetNameGet(pAddrDecWin->target), -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ /* read control register*/ -+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ decRegs.sizeReg = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum)); -+ } -+ -+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) -+ { -+ mvOsPrintf("mvAhbToMbusWinSet:mvCtrlAddrDecToReg Failed\n"); -+ return MV_ERROR; -+ } -+ -+ /* enable\Disable */ -+ if (MV_TRUE == pAddrDecWin->enable) -+ { -+ decRegs.sizeReg |= ATMWCR_WIN_ENABLE; -+ } -+ else -+ { -+ decRegs.sizeReg &= ~ATMWCR_WIN_ENABLE; -+ } -+ -+ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); -+ -+ /* set attributes */ -+ decRegs.sizeReg &= ~ATMWCR_WIN_ATTR_MASK; -+ decRegs.sizeReg |= targetAttribs.attrib << ATMWCR_WIN_ATTR_OFFS; -+ /* set target ID */ -+ decRegs.sizeReg &= ~ATMWCR_WIN_TARGET_MASK; -+ decRegs.sizeReg |= targetAttribs.targetId << ATMWCR_WIN_TARGET_OFFS; -+ -+#if !defined(MV_RUN_FROM_FLASH) -+ /* To be on the safe side we disable the window before writing the */ -+ /* new values. */ -+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ mvAhbToMbusWinEnable(winNum,MV_FALSE); -+ } -+#endif -+ -+ /* 3) Write to address decode Base Address Register */ -+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum), decRegs.baseReg); -+ } -+ else -+ { -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_INTEREG_REG, decRegs.baseReg); -+ } -+ -+ -+ /* Internal register space have no size */ -+ /* register. Do not perform size register assigment for those targets */ -+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ /* Write to address decode Size Register */ -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), decRegs.sizeReg); -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvAhbToMbusWinGet - Get CPU-to-peripheral winNum address window -+* -+* DESCRIPTION: -+* Get the CPU peripheral winNum address window. -+* -+* INPUT: -+* winNum - Peripheral winNum enumerator -+* -+* OUTPUT: -+* pAddrDecWin - CPU winNum window information data structure. -+* -+* RETURN: -+* MV_OK if winNum exist, MV_ERROR otherwise. -+* -+*******************************************************************************/ -+MV_STATUS mvAhbToMbusWinGet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin) -+{ -+ MV_DEC_REGS decRegs; -+ MV_TARGET_ATTRIB targetAttrib; -+ -+ -+ /* Parameter checking */ -+ if (winNum >= MAX_AHB_TO_MBUS_WINS) -+ { -+ mvOsPrintf("mvAhbToMbusWinGet: ERR. Invalid winNum %d\n", winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ -+ /* Internal register space size have no size register*/ -+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ decRegs.sizeReg = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum)); -+ } -+ else -+ { -+ decRegs.sizeReg = 0; -+ } -+ -+ -+ /* Read base and size */ -+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum)); -+ } -+ else -+ { -+ decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_INTEREG_REG); -+ } -+ -+ -+ -+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) -+ { -+ mvOsPrintf("mvAhbToMbusWinGet: mvCtrlRegToAddrDec Failed \n"); -+ return MV_ERROR; -+ } -+ -+ if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ pAddrDecWin->addrWin.size = INTER_REGS_SIZE; -+ pAddrDecWin->target = INTER_REGS; -+ pAddrDecWin->enable = MV_TRUE; -+ -+ return MV_OK; -+ } -+ -+ -+ if (decRegs.sizeReg & ATMWCR_WIN_ENABLE) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ -+ } -+ -+ -+ -+ if (-1 == pAddrDecWin->addrWin.size) -+ { -+ return MV_ERROR; -+ } -+ -+ /* attrib and targetId */ -+ targetAttrib.attrib = (decRegs.sizeReg & ATMWCR_WIN_ATTR_MASK) >> -+ ATMWCR_WIN_ATTR_OFFS; -+ targetAttrib.targetId = (decRegs.sizeReg & ATMWCR_WIN_TARGET_MASK) >> -+ ATMWCR_WIN_TARGET_OFFS; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvAhbToMbusWinTargetGet - Get Window number associated with target -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_U32 mvAhbToMbusWinTargetGet(MV_TARGET target) -+{ -+ MV_AHB_TO_MBUS_DEC_WIN decWin; -+ MV_U32 winNum; -+ -+ /* Check parameters */ -+ if (target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetGet: target %d is Illigal\n", target); -+ return 0xffffffff; -+ } -+ -+ if (INTER_REGS == target) -+ { -+ return MV_AHB_TO_MBUS_INTREG_WIN; -+ } -+ -+ for (winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS ; winNum++) -+ { -+ if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) -+ continue; -+ -+ if (mvAhbToMbusWinGet(winNum,&decWin) != MV_OK) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetGet: mvAhbToMbusWinGet fail\n"); -+ return 0xffffffff; -+ -+ } -+ -+ if (decWin.enable == MV_TRUE) -+ { -+ if (decWin.target == target) -+ { -+ return winNum; -+ } -+ -+ } -+ -+ } -+ -+ return 0xFFFFFFFF; -+ -+ -+} -+ -+/******************************************************************************* -+* mvAhbToMbusWinAvailGet - Get First Available window number. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_U32 mvAhbToMbusWinAvailGet(MV_VOID) -+{ -+ MV_AHB_TO_MBUS_DEC_WIN decWin; -+ MV_U32 winNum; -+ -+ for (winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS ; winNum++) -+ { -+ if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) -+ continue; -+ -+ if (mvAhbToMbusWinGet(winNum,&decWin) != MV_OK) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetGet: mvAhbToMbusWinGet fail\n"); -+ return 0xffffffff; -+ -+ } -+ -+ if (decWin.enable == MV_FALSE) -+ { -+ return winNum; -+ } -+ -+ } -+ -+ return 0xFFFFFFFF; -+} -+ -+ -+/******************************************************************************* -+* mvAhbToMbusWinEnable - Enable/disable a CPU address decode window -+* -+* DESCRIPTION: -+* This function enable/disable a CPU address decode window. -+* if parameter 'enable' == MV_TRUE the routine will enable the -+* window, thus enabling CPU accesses (before enabling the window it is -+* tested for overlapping). Otherwise, the window will be disabled. -+* -+* INPUT: -+* winNum - Peripheral winNum enumerator. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_ERROR if protection window number was wrong, or the window -+* overlapps other winNum window. -+* -+*******************************************************************************/ -+MV_STATUS mvAhbToMbusWinEnable(MV_U32 winNum, MV_BOOL enable) -+{ -+ -+ /* Parameter checking */ -+ if (winNum >= MAX_AHB_TO_MBUS_WINS) -+ { -+ mvOsPrintf("mvAhbToMbusWinEnable: ERR. Invalid winNum %d\n", winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ /* Internal registers bar can't be disable or enabled */ -+ if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ return (enable ? MV_OK : MV_ERROR); -+ } -+ -+ if (enable == MV_TRUE) -+ { -+ /* enable the window */ -+ MV_REG_BIT_SET(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ATMWCR_WIN_ENABLE); -+ } -+ else -+ { /* Disable address decode winNum window */ -+ MV_REG_BIT_RESET(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ATMWCR_WIN_ENABLE); -+ } -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvAhbToMbusWinRemap - Set CPU remap register for address windows. -+* -+* DESCRIPTION: -+* After a CPU address hits one of PCI address decode windows there is an -+* option to remap the address to a different one. For example, CPU -+* executes a read from PCI winNum window address 0x1200.0000. This -+* can be modified so the address on the PCI bus would be 0x1400.0000 -+* Using the PCI address remap mechanism. -+* -+* INPUT: -+* winNum - Peripheral winNum enumerator. Must be a PCI winNum. -+* pAddrDecWin - CPU winNum window information data structure. -+* Note that caller has to fill in the base field only. The -+* size field is ignored. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR if winNum is not a PCI one, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_U32 mvAhbToMbusWinRemap(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 baseAddr; -+ AHB_TO_MBUS_REMAP_REG_OFFS remapRegOffs; -+ -+ MV_U32 effectiveBaseAddress=0, -+ baseAddrValue=0,windowSizeValue=0; -+ -+ -+ /* Get registers offsets of given winNum */ -+ if (MV_NO_SUCH == ahbToMbusRemapRegOffsGet(winNum, &remapRegOffs)) -+ { -+ return 0xffffffff; -+ } -+ -+ /* 1) Set address remap low */ -+ baseAddr = pAddrWin->baseLow; -+ -+ /* Check base address aligment */ -+ /* -+ if (MV_IS_NOT_ALIGN(baseAddr, ATMWRLR_REMAP_LOW_ALIGNMENT)) -+ { -+ mvOsPrintf("mvAhbToMbusPciRemap: Warning. Target base 0x%x unaligned\n", -+ baseAddr); -+ return MV_ERROR; -+ } -+ */ -+ -+ /* BaseLow[31:16] => base register [31:16] */ -+ baseAddr = baseAddr & ATMWRLR_REMAP_LOW_MASK; -+ -+ MV_REG_WRITE(remapRegOffs.lowRegOffs, baseAddr); -+ -+ MV_REG_WRITE(remapRegOffs.highRegOffs, pAddrWin->baseHigh); -+ -+ -+ baseAddrValue = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum)); -+ windowSizeValue = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum)); -+ -+ baseAddrValue &= ATMWBR_BASE_MASK; -+ windowSizeValue &=ATMWCR_WIN_SIZE_MASK; -+ -+ /* Start calculating the effective Base Address */ -+ effectiveBaseAddress = baseAddrValue ; -+ -+ /* The effective base address will be combined from the chopped (if any) -+ remap value (according to the size value and remap mechanism) and the -+ window's base address */ -+ effectiveBaseAddress |= (((windowSizeValue) | 0xffff) & pAddrWin->baseLow); -+ /* If the effectiveBaseAddress exceed the window boundaries return an -+ invalid value. */ -+ -+ if (effectiveBaseAddress > (baseAddrValue + (windowSizeValue | 0xffff))) -+ { -+ mvOsPrintf("mvAhbToMbusPciRemap: Error\n"); -+ return 0xffffffff; -+ } -+ -+ return effectiveBaseAddress; -+ -+ -+} -+/******************************************************************************* -+* mvAhbToMbusWinTargetSwap - Swap AhbToMbus windows between targets -+* -+* DESCRIPTION: -+* -+* INPUT: -+* target1 - CPU Interface target 1 -+* target2 - CPU Interface target 2 -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR if targets are illigal, or if one of the targets is not -+* associated to a valid window . -+* MV_OK otherwise. -+* -+*******************************************************************************/ -+ -+ -+MV_STATUS mvAhbToMbusWinTargetSwap(MV_TARGET target1,MV_TARGET target2) -+{ -+ MV_U32 winNum1,winNum2; -+ MV_AHB_TO_MBUS_DEC_WIN winDec1,winDec2,winDecTemp; -+ AHB_TO_MBUS_REMAP_REG_OFFS remapRegs1,remapRegs2; -+ MV_U32 remapBaseLow1=0,remapBaseLow2=0; -+ MV_U32 remapBaseHigh1=0,remapBaseHigh2=0; -+ -+ -+ /* Check parameters */ -+ if (target1 >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d is Illigal\n", target1); -+ return MV_ERROR; -+ } -+ -+ if (target2 >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d is Illigal\n", target1); -+ return MV_ERROR; -+ } -+ -+ -+ /* get window associated with this target */ -+ winNum1 = mvAhbToMbusWinTargetGet(target1); -+ -+ if (winNum1 == 0xffffffff) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d has illigal win %d\n", -+ target1,winNum1); -+ return MV_ERROR; -+ -+ } -+ -+ /* get window associated with this target */ -+ winNum2 = mvAhbToMbusWinTargetGet(target2); -+ -+ if (winNum2 == 0xffffffff) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d has illigal win %d\n", -+ target2,winNum2); -+ return MV_ERROR; -+ -+ } -+ -+ /* now Get original values of both Windows */ -+ if (MV_OK != mvAhbToMbusWinGet(winNum1,&winDec1)) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetSwap: mvAhbToMbusWinGet failed win %d\n", -+ winNum1); -+ return MV_ERROR; -+ -+ } -+ if (MV_OK != mvAhbToMbusWinGet(winNum2,&winDec2)) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetSwap: mvAhbToMbusWinGet failed win %d\n", -+ winNum2); -+ return MV_ERROR; -+ -+ } -+ -+ -+ /* disable both windows */ -+ if (MV_OK != mvAhbToMbusWinEnable(winNum1,MV_FALSE)) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetSwap: failed to enable window %d\n", -+ winNum1); -+ return MV_ERROR; -+ -+ } -+ if (MV_OK != mvAhbToMbusWinEnable(winNum2,MV_FALSE)) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetSwap: failed to enable windo %d\n", -+ winNum2); -+ return MV_ERROR; -+ -+ } -+ -+ -+ /* now swap targets */ -+ -+ /* first save winDec2 values */ -+ winDecTemp.addrWin.baseHigh = winDec2.addrWin.baseHigh; -+ winDecTemp.addrWin.baseLow = winDec2.addrWin.baseLow; -+ winDecTemp.addrWin.size = winDec2.addrWin.size; -+ winDecTemp.enable = winDec2.enable; -+ winDecTemp.target = winDec2.target; -+ -+ /* winDec2 = winDec1 */ -+ winDec2.addrWin.baseHigh = winDec1.addrWin.baseHigh; -+ winDec2.addrWin.baseLow = winDec1.addrWin.baseLow; -+ winDec2.addrWin.size = winDec1.addrWin.size; -+ winDec2.enable = winDec1.enable; -+ winDec2.target = winDec1.target; -+ -+ -+ /* winDec1 = winDecTemp */ -+ winDec1.addrWin.baseHigh = winDecTemp.addrWin.baseHigh; -+ winDec1.addrWin.baseLow = winDecTemp.addrWin.baseLow; -+ winDec1.addrWin.size = winDecTemp.addrWin.size; -+ winDec1.enable = winDecTemp.enable; -+ winDec1.target = winDecTemp.target; -+ -+ -+ /* now set the new values */ -+ -+ -+ mvAhbToMbusWinSet(winNum1,&winDec1); -+ mvAhbToMbusWinSet(winNum2,&winDec2); -+ -+ -+ -+ -+ -+ /* now we will treat the remap windows if exist */ -+ -+ -+ /* now check if one or both windows has a remap window -+ as well after the swap ! */ -+ -+ /* if a window had a remap value differnt than the base value -+ before the swap , then after the swap the remap value will be -+ equal to the base value unless both windows has a remap windows*/ -+ -+ /* first get old values */ -+ if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum1,&remapRegs1)) -+ { -+ remapBaseLow1 = MV_REG_READ(remapRegs1.lowRegOffs); -+ remapBaseHigh1 = MV_REG_READ(remapRegs1.highRegOffs); -+ -+ } -+ if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2,&remapRegs2)) -+ { -+ remapBaseLow2 = MV_REG_READ(remapRegs2.lowRegOffs); -+ remapBaseHigh2 = MV_REG_READ(remapRegs2.highRegOffs); -+ -+ -+ } -+ -+ /* now do the swap */ -+ if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum1,&remapRegs1)) -+ { -+ if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2,&remapRegs2)) -+ { -+ /* Two windows has a remap !!! so swap */ -+ -+ MV_REG_WRITE(remapRegs2.highRegOffs,remapBaseHigh1); -+ MV_REG_WRITE(remapRegs2.lowRegOffs,remapBaseLow1); -+ -+ MV_REG_WRITE(remapRegs1.highRegOffs,remapBaseHigh2); -+ MV_REG_WRITE(remapRegs1.lowRegOffs,remapBaseLow2); -+ -+ -+ -+ } -+ else -+ { -+ /* remap == base */ -+ MV_REG_WRITE(remapRegs1.highRegOffs,winDec1.addrWin.baseHigh); -+ MV_REG_WRITE(remapRegs1.lowRegOffs,winDec1.addrWin.baseLow); -+ -+ } -+ -+ } -+ else if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2,&remapRegs2)) -+ { -+ /* remap == base */ -+ MV_REG_WRITE(remapRegs2.highRegOffs,winDec2.addrWin.baseHigh); -+ MV_REG_WRITE(remapRegs2.lowRegOffs,winDec2.addrWin.baseLow); -+ -+ } -+ -+ -+ -+ return MV_OK; -+ -+ -+} -+ -+ -+ -+#if defined(MV_88F1181) -+ -+/******************************************************************************* -+* mvAhbToMbusXbarCtrlSet - Set The CPU master Xbar arbitration. -+* -+* DESCRIPTION: -+* This function sets CPU Mbus Arbiter -+* -+* INPUT: -+* pPizzaArbArray - A priority Structure describing 16 "pizza slices". At -+* each clock cycle, the crossbar arbiter samples all -+* requests and gives the bus to the next agent according -+* to the "pizza". -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_ERROR if paramers to function invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvMbusArbSet(MV_MBUS_ARB_TARGET *pPizzaArbArray) -+{ -+ MV_U32 sliceNum; -+ MV_U32 xbarCtrl = 0; -+ MV_MBUS_ARB_TARGET xbarTarget; -+ -+ /* 1) Set crossbar control low register */ -+ for (sliceNum = 0; sliceNum < MRLR_SLICE_NUM; sliceNum++) -+ { -+ xbarTarget = pPizzaArbArray[sliceNum]; -+ -+ /* sliceNum parameter check */ -+ if (xbarTarget > MAX_MBUS_ARB_TARGETS) -+ { -+ mvOsPrintf("mvAhbToMbusXbarCtrlSet: ERR. Can't set Target %d\n", -+ xbarTarget); -+ return MV_ERROR; -+ } -+ xbarCtrl |= (xbarTarget << MRLR_LOW_ARB_OFFS(sliceNum)); -+ } -+ /* Write to crossbar control low register */ -+ MV_REG_WRITE(MBUS_ARBITER_LOW_REG, xbarCtrl); -+ -+ xbarCtrl = 0; -+ -+ /* 2) Set crossbar control high register */ -+ for (sliceNum = MRLR_SLICE_NUM; -+ sliceNum < MRLR_SLICE_NUM+MRHR_SLICE_NUM; -+ sliceNum++) -+ { -+ -+ xbarTarget = pPizzaArbArray[sliceNum]; -+ -+ /* sliceNum parameter check */ -+ if (xbarTarget > MAX_MBUS_ARB_TARGETS) -+ { -+ mvOsPrintf("mvAhbToMbusXbarCtrlSet: ERR. Can't set Target %d\n", -+ xbarTarget); -+ return MV_ERROR; -+ } -+ xbarCtrl |= (xbarTarget << MRHR_HIGH_ARB_OFFS(sliceNum)); -+ } -+ /* Write to crossbar control high register */ -+ MV_REG_WRITE(MBUS_ARBITER_HIGH_REG, xbarCtrl); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvMbusArbCtrlSet - Set MBus Arbiter control register -+* -+* DESCRIPTION: -+* -+* INPUT: -+* ctrl - pointer to MV_MBUS_ARB_CTRL register -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_ERROR if paramers to function invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvMbusArbCtrlSet(MV_MBUS_ARB_CTRL *ctrl) -+{ -+ -+ if (ctrl->highPrio == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(MBUS_ARBITER_CTRL_REG, MACR_ARB_ARM_TOP); -+ } -+ else -+ { -+ MV_REG_BIT_SET(MBUS_ARBITER_CTRL_REG, MACR_ARB_ARM_TOP); -+ } -+ -+ if (ctrl->fixedRoundRobin == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(MBUS_ARBITER_CTRL_REG, MACR_ARB_TARGET_FIXED); -+ } -+ else -+ { -+ MV_REG_BIT_SET(MBUS_ARBITER_CTRL_REG, MACR_ARB_TARGET_FIXED); -+ } -+ -+ if (ctrl->starvEn == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(MBUS_ARBITER_CTRL_REG, MACR_ARB_REQ_CTRL_EN); -+ } -+ else -+ { -+ MV_REG_BIT_SET(MBUS_ARBITER_CTRL_REG, MACR_ARB_REQ_CTRL_EN); -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvMbusArbCtrlGet - Get MBus Arbiter control register -+* -+* DESCRIPTION: -+* -+* INPUT: -+* ctrl - pointer to MV_MBUS_ARB_CTRL register -+* -+* OUTPUT: -+* ctrl - pointer to MV_MBUS_ARB_CTRL register -+* -+* RETURN: -+* MV_ERROR if paramers to function invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvMbusArbCtrlGet(MV_MBUS_ARB_CTRL *ctrl) -+{ -+ -+ MV_U32 ctrlReg = MV_REG_READ(MBUS_ARBITER_CTRL_REG); -+ -+ if (ctrlReg & MACR_ARB_ARM_TOP) -+ { -+ ctrl->highPrio = MV_TRUE; -+ } -+ else -+ { -+ ctrl->highPrio = MV_FALSE; -+ } -+ -+ if (ctrlReg & MACR_ARB_TARGET_FIXED) -+ { -+ ctrl->fixedRoundRobin = MV_TRUE; -+ } -+ else -+ { -+ ctrl->fixedRoundRobin = MV_FALSE; -+ } -+ -+ if (ctrlReg & MACR_ARB_REQ_CTRL_EN) -+ { -+ ctrl->starvEn = MV_TRUE; -+ } -+ else -+ { -+ ctrl->starvEn = MV_FALSE; -+ } -+ -+ -+ return MV_OK; -+} -+ -+#endif /* #if defined(MV_88F1181) */ -+ -+ -+ -+/******************************************************************************* -+* ahbToMbusRemapRegOffsGet - Get CPU address remap register offsets -+* -+* DESCRIPTION: -+* CPU to PCI address remap registers offsets are inconsecutive. -+* This function returns PCI address remap registers offsets. -+* -+* INPUT: -+* winNum - Address decode window number. See MV_U32 enumerator. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR if winNum is not a PCI one. -+* -+*******************************************************************************/ -+static MV_STATUS ahbToMbusRemapRegOffsGet(MV_U32 winNum, -+ AHB_TO_MBUS_REMAP_REG_OFFS *pRemapRegs) -+{ -+ switch (winNum) -+ { -+ case 0: -+ case 1: -+ pRemapRegs->lowRegOffs = AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum); -+ pRemapRegs->highRegOffs = AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum); -+ break; -+ case 2: -+ case 3: -+ if((mvCtrlModelGet() == MV_5281_DEV_ID) || -+ (mvCtrlModelGet() == MV_1281_DEV_ID) || -+ (mvCtrlModelGet() == MV_6183_DEV_ID) || -+ (mvCtrlModelGet() == MV_6183L_DEV_ID)) -+ { -+ pRemapRegs->lowRegOffs = AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum); -+ pRemapRegs->highRegOffs = AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum); -+ break; -+ } -+ else -+ { -+ pRemapRegs->lowRegOffs = 0; -+ pRemapRegs->highRegOffs = 0; -+ -+ DB(mvOsPrintf("ahbToMbusRemapRegOffsGet: ERR. Invalid winNum %d\n", -+ winNum)); -+ return MV_NO_SUCH; -+ } -+ default: -+ { -+ pRemapRegs->lowRegOffs = 0; -+ pRemapRegs->highRegOffs = 0; -+ -+ DB(mvOsPrintf("ahbToMbusRemapRegOffsGet: ERR. Invalid winNum %d\n", -+ winNum)); -+ return MV_NO_SUCH; -+ } -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvAhbToMbusAddDecShow - Print the AHB to MBus bridge address decode map. -+* -+* DESCRIPTION: -+* This function print the CPU address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvAhbToMbusAddDecShow(MV_VOID) -+{ -+ MV_AHB_TO_MBUS_DEC_WIN win; -+ MV_U32 winNum; -+ mvOsOutput( "\n" ); -+ mvOsOutput( "AHB To MBUS Bridge:\n" ); -+ mvOsOutput( "-------------------\n" ); -+ -+ for( winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS; winNum++ ) -+ { -+ memset( &win, 0, sizeof(MV_AHB_TO_MBUS_DEC_WIN) ); -+ -+ mvOsOutput( "win%d - ", winNum ); -+ -+ if( mvAhbToMbusWinGet( winNum, &win ) == MV_OK ) -+ { -+ if( win.enable ) -+ { -+ mvOsOutput( "%s base %08x, ", -+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); -+ mvOsOutput( "...." ); -+ mvSizePrint( win.addrWin.size ); -+ -+ mvOsOutput( "\n" ); -+ -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ } -+ } -+ -+} -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,130 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvAhbToMbush -+#define __INCmvAhbToMbush -+ -+/* includes */ -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/sys/mvAhbToMbusRegs.h" -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+ -+/* defines */ -+ -+#if defined(MV_88F1181) -+/* This enumerator defines the Marvell controller possible MBUS arbiter */ -+/* target ports. It is used to define crossbar priority scheame (pizza) */ -+typedef enum _mvMBusArbTargetId -+{ -+ DRAM_MBUS_ARB_TARGET = 0, /* Port 0 -> DRAM interface */ -+ TWSI_MBUS_ARB_TARGET = 1, /* Port 1 -> TWSI */ -+ ARM_MBUS_ARB_TARGET = 2, /* Port 2 -> ARM */ -+ PEX1_MBUS_ARB_TARGET = 3, /* Port 3 -> PCI Express 1 */ -+ PEX0_MBUS_ARB_TARGET = 4, /* Port 4 -> PCI Express0 */ -+ MAX_MBUS_ARB_TARGETS -+}MV_MBUS_ARB_TARGET; -+ -+typedef struct _mvMBusArbCtrl -+{ -+ MV_BOOL starvEn; -+ MV_BOOL highPrio; -+ MV_BOOL fixedRoundRobin; -+ -+}MV_MBUS_ARB_CTRL; -+ -+#endif /* #if defined(MV_88F1181) */ -+ -+typedef struct _mvAhbtoMbusDecWin -+{ -+ MV_TARGET target; -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+}MV_AHB_TO_MBUS_DEC_WIN; -+ -+/* mvAhbToMbus.h API list */ -+ -+MV_STATUS mvAhbToMbusInit(MV_VOID); -+MV_STATUS mvAhbToMbusWinSet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin); -+MV_STATUS mvAhbToMbusWinGet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin); -+MV_STATUS mvAhbToMbusWinEnable(MV_U32 winNum,MV_BOOL enable); -+MV_U32 mvAhbToMbusWinRemap(MV_U32 winNum, MV_ADDR_WIN *pAddrDecWin); -+MV_U32 mvAhbToMbusWinTargetGet(MV_TARGET target); -+MV_U32 mvAhbToMbusWinAvailGet(MV_VOID); -+MV_STATUS mvAhbToMbusWinTargetSwap(MV_TARGET target1,MV_TARGET target2); -+ -+#if defined(MV_88F1181) -+ -+MV_STATUS mvMbusArbSet(MV_MBUS_ARB_TARGET *pPizzaArbArray); -+MV_STATUS mvMbusArbCtrlSet(MV_MBUS_ARB_CTRL *ctrl); -+MV_STATUS mvMbusArbCtrlGet(MV_MBUS_ARB_CTRL *ctrl); -+ -+#endif /* #if defined(MV_88F1181) */ -+ -+ -+MV_VOID mvAhbToMbusAddDecShow(MV_VOID); -+ -+ -+#endif /* __INCmvAhbToMbush */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,143 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvAhbToMbusRegsh -+#define __INCmvAhbToMbusRegsh -+ -+/******************************/ -+/* ARM Address Map Registers */ -+/******************************/ -+ -+#define MAX_AHB_TO_MBUS_WINS 9 -+#define MV_AHB_TO_MBUS_INTREG_WIN 8 -+ -+ -+#define AHB_TO_MBUS_WIN_CTRL_REG(winNum) (0x20000 + (winNum)*0x10) -+#define AHB_TO_MBUS_WIN_BASE_REG(winNum) (0x20004 + (winNum)*0x10) -+#define AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum) (0x20008 + (winNum)*0x10) -+#define AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum) (0x2000C + (winNum)*0x10) -+#define AHB_TO_MBUS_WIN_INTEREG_REG 0x20080 -+ -+/* Window Control Register */ -+/* AHB_TO_MBUS_WIN_CTRL_REG (ATMWCR)*/ -+#define ATMWCR_WIN_ENABLE BIT0 /* Window Enable */ -+ -+#define ATMWCR_WIN_TARGET_OFFS 4 /* The target interface associated -+ with this window*/ -+#define ATMWCR_WIN_TARGET_MASK (0xf << ATMWCR_WIN_TARGET_OFFS) -+ -+#define ATMWCR_WIN_ATTR_OFFS 8 /* The target interface attributes -+ Associated with this window */ -+#define ATMWCR_WIN_ATTR_MASK (0xff << ATMWCR_WIN_ATTR_OFFS) -+ -+ -+/* -+Used with the Base register to set the address window size and location -+Must be programed from LSB to MSB as sequence of 1’s followed -+by sequence of 0’s. The number of 1’s specifies the size of the window -+in 64 KB granularity (e.g. a value of 0x00FF specifies 256 = 16 MB). -+ -+NOTE: A value of 0x0 specifies 64KB size. -+*/ -+#define ATMWCR_WIN_SIZE_OFFS 16 /* Window Size */ -+#define ATMWCR_WIN_SIZE_MASK (0xffff << ATMWCR_WIN_SIZE_OFFS) -+#define ATMWCR_WIN_SIZE_ALIGNMENT 0x10000 -+ -+/* Window Base Register */ -+/* AHB_TO_MBUS_WIN_BASE_REG (ATMWBR) */ -+ -+/* -+Used with the size field to set the address window size and location. -+Corresponds to transaction address[31:16] -+*/ -+#define ATMWBR_BASE_OFFS 16 /* Base Address */ -+#define ATMWBR_BASE_MASK (0xffff << ATMWBR_BASE_OFFS) -+#define ATMWBR_BASE_ALIGNMENT 0x10000 -+ -+/* Window Remap Low Register */ -+/* AHB_TO_MBUS_WIN_REMAP_LOW_REG (ATMWRLR) */ -+ -+/* -+Used with the size field to specifies address bits[31:0] to be driven to -+the target interface.: -+target_addr[31:16] = (addr[31:16] & size[15:0]) | (remap[31:16] & ~size[15:0]) -+*/ -+#define ATMWRLR_REMAP_LOW_OFFS 16 /* Remap Address */ -+#define ATMWRLR_REMAP_LOW_MASK (0xffff << ATMWRLR_REMAP_LOW_OFFS) -+#define ATMWRLR_REMAP_LOW_ALIGNMENT 0x10000 -+ -+/* Window Remap High Register */ -+/* AHB_TO_MBUS_WIN_REMAP_HIGH_REG (ATMWRHR) */ -+ -+/* -+Specifies address bits[63:32] to be driven to the target interface. -+target_addr[63:32] = (RemapHigh[31:0] -+*/ -+#define ATMWRHR_REMAP_HIGH_OFFS 0 /* Remap Address */ -+#define ATMWRHR_REMAP_HIGH_MASK (0xffffffff << ATMWRHR_REMAP_HIGH_OFFS) -+ -+ -+#endif /* __INCmvAhbToMbusRegsh */ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,1036 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+/* includes */ -+#include "ctrlEnv/sys/mvCpuIf.h" -+#include "ctrlEnv/sys/mvAhbToMbusRegs.h" -+#include "cpu/mvCpu.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "mvSysHwConfig.h" -+#include "mvSysDram.h" -+ -+/*#define MV_DEBUG*/ -+/* defines */ -+ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+/* locals */ -+/* static functions */ -+static MV_BOOL cpuTargetWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin); -+ -+MV_TARGET * sampleAtResetTargetArray; -+MV_TARGET sampleAtResetTargetArrayP[] = BOOT_TARGETS_NAME_ARRAY; -+MV_TARGET sampleAtResetTargetArray6180P[] = BOOT_TARGETS_NAME_ARRAY_6180; -+/******************************************************************************* -+* mvCpuIfInit - Initialize Controller CPU interface -+* -+* DESCRIPTION: -+* This function initialize Controller CPU interface: -+* 1. Set CPU interface configuration registers. -+* 2. Set CPU master Pizza arbiter control according to static -+* configuration described in configuration file. -+* 3. Opens CPU address decode windows. DRAM windows are assumed to be -+* already set (auto detection). -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvCpuIfInit(MV_CPU_DEC_WIN *cpuAddrWinMap) -+{ -+ MV_U32 regVal; -+ MV_TARGET target; -+ MV_ADDR_WIN addrWin; -+ -+ if (cpuAddrWinMap == NULL) -+ { -+ DB(mvOsPrintf("mvCpuIfInit:ERR. cpuAddrWinMap == NULL\n")); -+ return MV_ERROR; -+ } -+ -+ /*Initialize the boot target array according to device type*/ -+ if(mvCtrlModelGet() == MV_6180_DEV_ID) -+ sampleAtResetTargetArray = sampleAtResetTargetArray6180P; -+ else -+ sampleAtResetTargetArray = sampleAtResetTargetArrayP; -+ -+ /* Set ARM Configuration register */ -+ regVal = MV_REG_READ(CPU_CONFIG_REG); -+ regVal &= ~CPU_CONFIG_DEFAULT_MASK; -+ regVal |= CPU_CONFIG_DEFAULT; -+ MV_REG_WRITE(CPU_CONFIG_REG,regVal); -+ -+ /* First disable all CPU target windows */ -+ for (target = 0; cpuAddrWinMap[target].enable != TBL_TERM; target++) -+ { -+ if ((MV_TARGET_IS_DRAM(target))||(target == INTER_REGS)) -+ { -+ continue; -+ } -+ -+#if defined(MV_MEM_OVER_PCI_WA) || defined(MV_UART_OVER_PCI_WA) -+ /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ -+ if (MV_TARGET_IS_PCI(target)) -+ { -+ continue; -+ } -+#endif -+ -+#if defined(MV_MEM_OVER_PEX_WA) || defined(MV_UART_OVER_PEX_WA) -+ /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ -+ if (MV_TARGET_IS_PEX(target)) -+ { -+ continue; -+ } -+#endif -+#if defined(MV_RUN_FROM_FLASH) -+ /* Don't disable the boot device. */ -+ if (target == DEV_BOOCS) -+ { -+ continue; -+ } -+#endif /* MV_RUN_FROM_FLASH */ -+ mvCpuIfTargetWinEnable(MV_CHANGE_BOOT_CS(target),MV_FALSE); -+ } -+ -+#if defined(MV_RUN_FROM_FLASH) -+ /* Resize the bootcs windows before other windows, because this */ -+ /* window is enabled and will cause an overlap if not resized. */ -+ target = DEV_BOOCS; -+ -+ if (MV_OK != mvCpuIfTargetWinSet(target, &cpuAddrWinMap[target])) -+ { -+ DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinSet fail\n")); -+ return MV_ERROR; -+ } -+ -+ addrWin.baseLow = cpuAddrWinMap[target].addrWin.baseLow; -+ addrWin.baseHigh = cpuAddrWinMap[target].addrWin.baseHigh; -+ if (0xffffffff == mvAhbToMbusWinRemap(cpuAddrWinMap[target].winNum ,&addrWin)) -+ { -+ DB(mvOsPrintf("mvCpuIfInit:WARN. mvAhbToMbusWinRemap can't remap winNum=%d\n", -+ cpuAddrWinMap[target].winNum)); -+ } -+ -+#endif /* MV_RUN_FROM_FLASH */ -+ -+ /* Go through all targets in user table until table terminator */ -+ for (target = 0; cpuAddrWinMap[target].enable != TBL_TERM; target++) -+ { -+ -+#if defined(MV_RUN_FROM_FLASH) -+ if (target == DEV_BOOCS) -+ { -+ continue; -+ } -+#endif /* MV_RUN_FROM_FLASH */ -+ -+ /* if DRAM auto sizing is used do not initialized DRAM target windows, */ -+ /* assuming this already has been done earlier. */ -+#ifdef MV_DRAM_AUTO_SIZE -+ if (MV_TARGET_IS_DRAM(target)) -+ { -+ continue; -+ } -+#endif -+ -+#if defined(MV_MEM_OVER_PCI_WA) || defined(MV_UART_OVER_PCI_WA) -+ /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ -+ if (MV_TARGET_IS_PCI(target)) -+ { -+ continue; -+ } -+#endif -+ -+#if defined(MV_MEM_OVER_PEX_WA) || defined(MV_UART_OVER_PEX_WA) -+ /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ -+ if (MV_TARGET_IS_PEX(target)) -+ { -+ continue; -+ } -+#endif -+ /* If the target attribute is the same as the boot device attribute */ -+ /* then it's stays disable */ -+ if (MV_TARGET_IS_AS_BOOT(target)) -+ { -+ continue; -+ } -+ -+ if((0 == cpuAddrWinMap[target].addrWin.size) || -+ (DIS == cpuAddrWinMap[target].enable)) -+ -+ { -+ if (MV_OK != mvCpuIfTargetWinEnable(target, MV_FALSE)) -+ { -+ DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinEnable fail\n")); -+ return MV_ERROR; -+ } -+ -+ } -+ else -+ { -+ if (MV_OK != mvCpuIfTargetWinSet(target, &cpuAddrWinMap[target])) -+ { -+ DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinSet fail\n")); -+ return MV_ERROR; -+ } -+ -+ addrWin.baseLow = cpuAddrWinMap[target].addrWin.baseLow; -+ addrWin.baseHigh = cpuAddrWinMap[target].addrWin.baseHigh; -+ if (0xffffffff == mvAhbToMbusWinRemap(cpuAddrWinMap[target].winNum ,&addrWin)) -+ { -+ DB(mvOsPrintf("mvCpuIfInit:WARN. mvAhbToMbusWinRemap can't remap winNum=%d\n", -+ cpuAddrWinMap[target].winNum)); -+ } -+ -+ -+ } -+ } -+ -+ return MV_OK; -+ -+ -+} -+ -+ -+/******************************************************************************* -+* mvCpuIfTargetWinSet - Set CPU-to-peripheral target address window -+* -+* DESCRIPTION: -+* This function sets a peripheral target (e.g. SDRAM bank0, PCI0_MEM0) -+* address window, also known as address decode window. -+* A new address decode window is set for specified target address window. -+* If address decode window parameter structure enables the window, -+* the routine will also enable the target window, allowing CPU to access -+* the target window. -+* -+* INPUT: -+* target - Peripheral target enumerator. -+* pAddrDecWin - CPU target window data structure. -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_OK if CPU target window was set correctly, MV_ERROR in case of -+* address window overlapps with other active CPU target window or -+* trying to assign 36bit base address while CPU does not support that. -+* The function returns MV_NOT_SUPPORTED, if the target is unsupported. -+* -+*******************************************************************************/ -+MV_STATUS mvCpuIfTargetWinSet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin) -+{ -+ MV_AHB_TO_MBUS_DEC_WIN decWin; -+ MV_U32 existingWinNum; -+ MV_DRAM_DEC_WIN addrDecWin; -+ -+ target = MV_CHANGE_BOOT_CS(target); -+ -+ /* Check parameters */ -+ if (target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvCpuIfTargetWinSet: target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ /* 2) Check if the requested window overlaps with current windows */ -+ if (MV_TRUE == cpuTargetWinOverlap(target, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("mvCpuIfTargetWinSet: ERR. Target %d overlap\n", target); -+ return MV_BAD_PARAM; -+ } -+ -+ if (MV_TARGET_IS_DRAM(target)) -+ { -+ /* copy relevant data to MV_DRAM_DEC_WIN structure */ -+ addrDecWin.addrWin.baseHigh = pAddrDecWin->addrWin.baseHigh; -+ addrDecWin.addrWin.baseLow = pAddrDecWin->addrWin.baseLow; -+ addrDecWin.addrWin.size = pAddrDecWin->addrWin.size; -+ addrDecWin.enable = pAddrDecWin->enable; -+ -+ -+ if (mvDramIfWinSet(target,&addrDecWin) != MV_OK); -+ { -+ mvOsPrintf("mvCpuIfTargetWinSet: mvDramIfWinSet Failed\n"); -+ return MV_ERROR; -+ } -+ -+ } -+ else -+ { -+ /* copy relevant data to MV_AHB_TO_MBUS_DEC_WIN structure */ -+ decWin.addrWin.baseLow = pAddrDecWin->addrWin.baseLow; -+ decWin.addrWin.baseHigh = pAddrDecWin->addrWin.baseHigh; -+ decWin.addrWin.size = pAddrDecWin->addrWin.size; -+ decWin.enable = pAddrDecWin->enable; -+ decWin.target = target; -+ -+ existingWinNum = mvAhbToMbusWinTargetGet(target); -+ -+ /* check if there is already another Window configured -+ for this target */ -+ if ((existingWinNum < MAX_AHB_TO_MBUS_WINS )&& -+ (existingWinNum != pAddrDecWin->winNum)) -+ { -+ /* if we want to enable the new winow number -+ passed by the user , then the old one should -+ be disabled */ -+ if (MV_TRUE == pAddrDecWin->enable) -+ { -+ /* be sure it is disabled */ -+ mvAhbToMbusWinEnable(existingWinNum , MV_FALSE); -+ } -+ } -+ -+ if (mvAhbToMbusWinSet(pAddrDecWin->winNum,&decWin) != MV_OK) -+ { -+ mvOsPrintf("mvCpuIfTargetWinSet: mvAhbToMbusWinSet Failed\n"); -+ return MV_ERROR; -+ } -+ -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCpuIfTargetWinGet - Get CPU-to-peripheral target address window -+* -+* DESCRIPTION: -+* Get the CPU peripheral target address window. -+* -+* INPUT: -+* target - Peripheral target enumerator -+* -+* OUTPUT: -+* pAddrDecWin - CPU target window information data structure. -+* -+* RETURN: -+* MV_OK if target exist, MV_ERROR otherwise. -+* -+*******************************************************************************/ -+MV_STATUS mvCpuIfTargetWinGet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin) -+{ -+ -+ MV_U32 winNum=0xffffffff; -+ MV_AHB_TO_MBUS_DEC_WIN decWin; -+ MV_DRAM_DEC_WIN addrDecWin; -+ -+ target = MV_CHANGE_BOOT_CS(target); -+ -+ /* Check parameters */ -+ if (target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvCpuIfTargetWinGet: target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ if (MV_TARGET_IS_DRAM(target)) -+ { -+ if (mvDramIfWinGet(target,&addrDecWin) != MV_OK) -+ { -+ mvOsPrintf("mvCpuIfTargetWinGet: Failed to get window target %d\n", -+ target); -+ return MV_ERROR; -+ } -+ -+ /* copy relevant data to MV_CPU_DEC_WIN structure */ -+ pAddrDecWin->addrWin.baseLow = addrDecWin.addrWin.baseLow; -+ pAddrDecWin->addrWin.baseHigh = addrDecWin.addrWin.baseHigh; -+ pAddrDecWin->addrWin.size = addrDecWin.addrWin.size; -+ pAddrDecWin->enable = addrDecWin.enable; -+ pAddrDecWin->winNum = 0xffffffff; -+ -+ } -+ else -+ { -+ /* get the Window number associated with this target */ -+ -+ winNum = mvAhbToMbusWinTargetGet(target); -+ if (winNum >= MAX_AHB_TO_MBUS_WINS) -+ { -+ return MV_NO_SUCH; -+ -+ } -+ -+ if (mvAhbToMbusWinGet(winNum , &decWin) != MV_OK) -+ { -+ mvOsPrintf("%s: mvAhbToMbusWinGet Failed at winNum = %d\n", -+ __FUNCTION__, winNum); -+ return MV_ERROR; -+ -+ } -+ -+ /* copy relevant data to MV_CPU_DEC_WIN structure */ -+ pAddrDecWin->addrWin.baseLow = decWin.addrWin.baseLow; -+ pAddrDecWin->addrWin.baseHigh = decWin.addrWin.baseHigh; -+ pAddrDecWin->addrWin.size = decWin.addrWin.size; -+ pAddrDecWin->enable = decWin.enable; -+ pAddrDecWin->winNum = winNum; -+ -+ } -+ -+ -+ -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvCpuIfTargetWinEnable - Enable/disable a CPU address decode window -+* -+* DESCRIPTION: -+* This function enable/disable a CPU address decode window. -+* if parameter 'enable' == MV_TRUE the routine will enable the -+* window, thus enabling CPU accesses (before enabling the window it is -+* tested for overlapping). Otherwise, the window will be disabled. -+* -+* INPUT: -+* target - Peripheral target enumerator. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_ERROR if protection window number was wrong, or the window -+* overlapps other target window. -+* -+*******************************************************************************/ -+MV_STATUS mvCpuIfTargetWinEnable(MV_TARGET target,MV_BOOL enable) -+{ -+ MV_U32 winNum, temp; -+ MV_CPU_DEC_WIN addrDecWin; -+ -+ target = MV_CHANGE_BOOT_CS(target); -+ -+ /* Check parameters */ -+ if (target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvCpuIfTargetWinEnable: target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ /* get the window and check if it exist */ -+ temp = mvCpuIfTargetWinGet(target, &addrDecWin); -+ if (MV_NO_SUCH == temp) -+ { -+ return (enable? MV_ERROR: MV_OK); -+ } -+ else if( MV_OK != temp) -+ { -+ mvOsPrintf("%s: ERR. Getting target %d failed.\n",__FUNCTION__, target); -+ return MV_ERROR; -+ } -+ -+ -+ /* check overlap */ -+ -+ if (MV_TRUE == enable) -+ { -+ if (MV_TRUE == cpuTargetWinOverlap(target, &addrDecWin.addrWin)) -+ { -+ DB(mvOsPrintf("%s: ERR. Target %d overlap\n",__FUNCTION__, target)); -+ return MV_ERROR; -+ } -+ -+ } -+ -+ -+ if (MV_TARGET_IS_DRAM(target)) -+ { -+ if (mvDramIfWinEnable(target , enable) != MV_OK) -+ { -+ mvOsPrintf("mvCpuIfTargetWinGet: mvDramIfWinEnable Failed at \n"); -+ return MV_ERROR; -+ -+ } -+ -+ } -+ else -+ { -+ /* get the Window number associated with this target */ -+ -+ winNum = mvAhbToMbusWinTargetGet(target); -+ -+ if (winNum >= MAX_AHB_TO_MBUS_WINS) -+ { -+ return (enable? MV_ERROR: MV_OK); -+ } -+ -+ if (mvAhbToMbusWinEnable(winNum , enable) != MV_OK) -+ { -+ mvOsPrintf("mvCpuIfTargetWinGet: Failed to enable window = %d\n", -+ winNum); -+ return MV_ERROR; -+ -+ } -+ -+ } -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvCpuIfTargetWinSizeGet - Get CPU target address window size -+* -+* DESCRIPTION: -+* Get the size of CPU-to-peripheral target window. -+* -+* INPUT: -+* target - Peripheral target enumerator -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit size. Function also returns '0' if window is closed. -+* Function returns 0xFFFFFFFF in case of an error. -+* -+*******************************************************************************/ -+MV_U32 mvCpuIfTargetWinSizeGet(MV_TARGET target) -+{ -+ MV_CPU_DEC_WIN addrDecWin; -+ -+ target = MV_CHANGE_BOOT_CS(target); -+ -+ /* Check parameters */ -+ if (target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvCpuIfTargetWinSizeGet: target %d is Illigal\n", target); -+ return 0; -+ } -+ -+ /* Get the winNum window */ -+ if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) -+ { -+ mvOsPrintf("mvCpuIfTargetWinSizeGet:ERR. Getting target %d failed.\n", -+ target); -+ return 0; -+ } -+ -+ /* Check if window is enabled */ -+ if (addrDecWin.enable == MV_TRUE) -+ { -+ return (addrDecWin.addrWin.size); -+ } -+ else -+ { -+ return 0; /* Window disabled. return 0 */ -+ } -+} -+ -+/******************************************************************************* -+* mvCpuIfTargetWinBaseLowGet - Get CPU target address window base low -+* -+* DESCRIPTION: -+* CPU-to-peripheral target address window base is constructed of -+* two parts: Low and high. -+* This function gets the CPU peripheral target low base address. -+* -+* INPUT: -+* target - Peripheral target enumerator -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit low base address. -+* -+*******************************************************************************/ -+MV_U32 mvCpuIfTargetWinBaseLowGet(MV_TARGET target) -+{ -+ MV_CPU_DEC_WIN addrDecWin; -+ -+ target = MV_CHANGE_BOOT_CS(target); -+ -+ /* Check parameters */ -+ if (target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvCpuIfTargetWinBaseLowGet: target %d is Illigal\n", target); -+ return 0xffffffff; -+ } -+ -+ /* Get the target window */ -+ if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) -+ { -+ mvOsPrintf("mvCpuIfTargetWinBaseLowGet:ERR. Getting target %d failed.\n", -+ target); -+ return 0xffffffff; -+ } -+ -+ if (MV_FALSE == addrDecWin.enable) -+ { -+ return 0xffffffff; -+ } -+ return (addrDecWin.addrWin.baseLow); -+} -+ -+/******************************************************************************* -+* mvCpuIfTargetWinBaseHighGet - Get CPU target address window base high -+* -+* DESCRIPTION: -+* CPU-to-peripheral target address window base is constructed of -+* two parts: Low and high. -+* This function gets the CPU peripheral target high base address. -+* -+* INPUT: -+* target - Peripheral target enumerator -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit high base address. -+* -+*******************************************************************************/ -+MV_U32 mvCpuIfTargetWinBaseHighGet(MV_TARGET target) -+{ -+ MV_CPU_DEC_WIN addrDecWin; -+ -+ target = MV_CHANGE_BOOT_CS(target); -+ -+ /* Check parameters */ -+ if (target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvCpuIfTargetWinBaseLowGet: target %d is Illigal\n", target); -+ return 0xffffffff; -+ } -+ -+ /* Get the target window */ -+ if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) -+ { -+ mvOsPrintf("mvCpuIfTargetWinBaseHighGet:ERR. Getting target %d failed.\n", -+ target); -+ return 0xffffffff; -+ } -+ -+ if (MV_FALSE == addrDecWin.enable) -+ { -+ return 0; -+ } -+ -+ return (addrDecWin.addrWin.baseHigh); -+} -+ -+#if defined(MV_INCLUDE_PEX) -+/******************************************************************************* -+* mvCpuIfPexRemap - Set CPU remap register for address windows. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* pexTarget - Peripheral target enumerator. Must be a PEX target. -+* pAddrDecWin - CPU target window information data structure. -+* Note that caller has to fill in the base field only. The -+* size field is ignored. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR if target is not a PEX one, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_U32 mvCpuIfPexRemap(MV_TARGET pexTarget, MV_ADDR_WIN *pAddrDecWin) -+{ -+ MV_U32 winNum; -+ -+ /* Check parameters */ -+ -+ if (mvCtrlPexMaxIfGet() > 1) -+ { -+ if ((!MV_TARGET_IS_PEX1(pexTarget))&&(!MV_TARGET_IS_PEX0(pexTarget))) -+ { -+ mvOsPrintf("mvCpuIfPexRemap: target %d is Illigal\n",pexTarget); -+ return 0xffffffff; -+ } -+ -+ } -+ else -+ { -+ if (!MV_TARGET_IS_PEX0(pexTarget)) -+ { -+ mvOsPrintf("mvCpuIfPexRemap: target %d is Illigal\n",pexTarget); -+ return 0xffffffff; -+ } -+ -+ } -+ -+ /* get the Window number associated with this target */ -+ winNum = mvAhbToMbusWinTargetGet(pexTarget); -+ -+ if (winNum >= MAX_AHB_TO_MBUS_WINS) -+ { -+ mvOsPrintf("mvCpuIfPexRemap: mvAhbToMbusWinTargetGet Failed\n"); -+ return 0xffffffff; -+ -+ } -+ -+ return mvAhbToMbusWinRemap(winNum , pAddrDecWin); -+} -+ -+#endif -+ -+#if defined(MV_INCLUDE_PCI) -+/******************************************************************************* -+* mvCpuIfPciRemap - Set CPU remap register for address windows. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* pciTarget - Peripheral target enumerator. Must be a PCI target. -+* pAddrDecWin - CPU target window information data structure. -+* Note that caller has to fill in the base field only. The -+* size field is ignored. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR if target is not a PCI one, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_U32 mvCpuIfPciRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin) -+{ -+ MV_U32 winNum; -+ -+ /* Check parameters */ -+ if (!MV_TARGET_IS_PCI(pciTarget)) -+ { -+ mvOsPrintf("mvCpuIfPciRemap: target %d is Illigal\n",pciTarget); -+ return 0xffffffff; -+ } -+ -+ /* get the Window number associated with this target */ -+ winNum = mvAhbToMbusWinTargetGet(pciTarget); -+ -+ if (winNum >= MAX_AHB_TO_MBUS_WINS) -+ { -+ mvOsPrintf("mvCpuIfPciRemap: mvAhbToMbusWinTargetGet Failed\n"); -+ return 0xffffffff; -+ -+ } -+ -+ return mvAhbToMbusWinRemap(winNum , pAddrDecWin); -+} -+#endif /* MV_INCLUDE_PCI */ -+ -+ -+/******************************************************************************* -+* mvCpuIfPciIfRemap - Set CPU remap register for address windows. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* pciTarget - Peripheral target enumerator. Must be a PCI target. -+* pAddrDecWin - CPU target window information data structure. -+* Note that caller has to fill in the base field only. The -+* size field is ignored. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR if target is not a PCI one, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_U32 mvCpuIfPciIfRemap(MV_TARGET pciIfTarget, MV_ADDR_WIN *pAddrDecWin) -+{ -+#if defined(MV_INCLUDE_PEX) -+ if (MV_TARGET_IS_PEX(pciIfTarget)) -+ { -+ return mvCpuIfPexRemap(pciIfTarget,pAddrDecWin); -+ } -+#endif -+#if defined(MV_INCLUDE_PCI) -+ -+ if (MV_TARGET_IS_PCI(pciIfTarget)) -+ { -+ return mvCpuIfPciRemap(pciIfTarget,pAddrDecWin); -+ } -+#endif -+ return 0; -+} -+ -+ -+ -+/******************************************************************************* -+* mvCpuIfTargetOfBaseAddressGet - Get the target according to base address -+* -+* DESCRIPTION: -+* -+* INPUT: -+* baseAddress - base address to be checked -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* the target number that baseAddress belongs to or MAX_TARGETS is not -+* found -+* -+*******************************************************************************/ -+ -+MV_TARGET mvCpuIfTargetOfBaseAddressGet(MV_U32 baseAddress) -+{ -+ MV_CPU_DEC_WIN win; -+ MV_U32 target; -+ -+ for( target = 0; target < MAX_TARGETS; target++ ) -+ { -+ if( mvCpuIfTargetWinGet( target, &win ) == MV_OK ) -+ { -+ if( win.enable ) -+ { -+ if ((baseAddress >= win.addrWin.baseLow) && -+ (baseAddress < win.addrWin.baseLow + win.addrWin.size)) break; -+ } -+ } -+ else return MAX_TARGETS; -+ -+ } -+ -+ return target; -+} -+/******************************************************************************* -+* cpuTargetWinOverlap - Detect CPU address decode windows overlapping -+* -+* DESCRIPTION: -+* An unpredicted behaviur is expected in case CPU address decode -+* windows overlapps. -+* This function detects CPU address decode windows overlapping of a -+* specified target. The function does not check the target itself for -+* overlapping. The function also skipps disabled address decode windows. -+* -+* INPUT: -+* target - Peripheral target enumerator. -+* pAddrDecWin - An address decode window struct. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlaps current address -+* decode map, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+static MV_BOOL cpuTargetWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 targetNum; -+ MV_CPU_DEC_WIN addrDecWin; -+ MV_STATUS status; -+ -+ -+ for(targetNum = 0; targetNum < MAX_TARGETS; targetNum++) -+ { -+#if defined(MV_RUN_FROM_FLASH) -+ if(MV_TARGET_IS_AS_BOOT(target)) -+ { -+ if (MV_CHANGE_BOOT_CS(targetNum) == target) -+ continue; -+ } -+#endif /* MV_RUN_FROM_FLASH */ -+ -+ /* don't check our target or illegal targets */ -+ if (targetNum == target) -+ { -+ continue; -+ } -+ -+ /* Get window parameters */ -+ status = mvCpuIfTargetWinGet(targetNum, &addrDecWin); -+ if(MV_NO_SUCH == status) -+ { -+ continue; -+ } -+ if(MV_OK != status) -+ { -+ DB(mvOsPrintf("cpuTargetWinOverlap: ERR. TargetWinGet failed\n")); -+ return MV_TRUE; -+ } -+ -+ /* Do not check disabled windows */ -+ if (MV_FALSE == addrDecWin.enable) -+ { -+ continue; -+ } -+ -+ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) -+ { -+ DB(mvOsPrintf( -+ "cpuTargetWinOverlap: Required target %d overlap current %d\n", -+ target, targetNum)); -+ return MV_TRUE; -+ } -+ } -+ -+ return MV_FALSE; -+ -+} -+ -+/******************************************************************************* -+* mvCpuIfAddDecShow - Print the CPU address decode map. -+* -+* DESCRIPTION: -+* This function print the CPU address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvCpuIfAddDecShow(MV_VOID) -+{ -+ MV_CPU_DEC_WIN win; -+ MV_U32 target; -+ mvOsOutput( "\n" ); -+ mvOsOutput( "CPU Interface\n" ); -+ mvOsOutput( "-------------\n" ); -+ -+ for( target = 0; target < MAX_TARGETS; target++ ) -+ { -+ -+ memset( &win, 0, sizeof(MV_CPU_DEC_WIN) ); -+ -+ mvOsOutput( "%s ",mvCtrlTargetNameGet(target)); -+ mvOsOutput( "...." ); -+ -+ if( mvCpuIfTargetWinGet( target, &win ) == MV_OK ) -+ { -+ if( win.enable ) -+ { -+ mvOsOutput( "base %08x, ", win.addrWin.baseLow ); -+ mvSizePrint( win.addrWin.size ); -+ mvOsOutput( "\n" ); -+ -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ } -+ else if( mvCpuIfTargetWinGet( target, &win ) == MV_NO_SUCH ) -+ { -+ mvOsOutput( "no such\n" ); -+ } -+ } -+} -+ -+/******************************************************************************* -+* mvCpuIfEnablePex - Enable PCI Express. -+* -+* DESCRIPTION: -+* This function Enable PCI Express. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* pexType - MV_PEX_ROOT_COMPLEX - root complex device -+* MV_PEX_END_POINT - end point device -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+#if defined(MV_INCLUDE_PEX) -+MV_VOID mvCpuIfEnablePex(MV_U32 pexIf, MV_PEX_TYPE pexType) -+{ -+ /* Set pex mode incase S@R not exist */ -+ if( pexType == MV_PEX_END_POINT) -+ { -+ MV_REG_BIT_RESET(PEX_CTRL_REG(pexIf),PXCR_DEV_TYPE_CTRL_MASK); -+ /* Change pex mode in capability reg */ -+ MV_REG_BIT_RESET(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_CAPABILITY_REG), BIT22); -+ MV_REG_BIT_SET(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_CAPABILITY_REG), BIT20); -+ -+ } -+ else -+ { -+ MV_REG_BIT_SET(PEX_CTRL_REG(pexIf),PXCR_DEV_TYPE_CTRL_MASK); -+ } -+ -+ /* CPU config register Pex enable */ -+ MV_REG_BIT_SET(CPU_CTRL_STAT_REG,CCSR_PCI_ACCESS_MASK); -+} -+#endif -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,120 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvCpuIfh -+#define __INCmvCpuIfh -+ -+/* includes */ -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/sys/mvCpuIfRegs.h" -+#include "ctrlEnv/sys/mvAhbToMbus.h" -+#include "ddr2/mvDramIf.h" -+#include "ctrlEnv/sys/mvSysDram.h" -+#if defined(MV_INCLUDE_PEX) -+#include "pex/mvPex.h" -+#endif -+ -+/* defines */ -+ -+/* typedefs */ -+/* This structure describes CPU interface address decode window */ -+typedef struct _mvCpuIfDecWin -+{ -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_U32 winNum; /* Window Number in the AHB To Mbus bridge */ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+}MV_CPU_DEC_WIN; -+ -+ -+ -+/* mvCpuIfLib.h API list */ -+ -+/* mvCpuIfLib.h API list */ -+ -+MV_STATUS mvCpuIfInit(MV_CPU_DEC_WIN *cpuAddrWinMap); -+MV_STATUS mvCpuIfTargetWinSet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin); -+MV_STATUS mvCpuIfTargetWinGet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin); -+MV_STATUS mvCpuIfTargetWinEnable(MV_TARGET target,MV_BOOL enable); -+MV_U32 mvCpuIfTargetWinSizeGet(MV_TARGET target); -+MV_U32 mvCpuIfTargetWinBaseLowGet(MV_TARGET target); -+MV_U32 mvCpuIfTargetWinBaseHighGet(MV_TARGET target); -+MV_TARGET mvCpuIfTargetOfBaseAddressGet(MV_U32 baseAddress); -+#if defined(MV_INCLUDE_PEX) -+MV_U32 mvCpuIfPexRemap(MV_TARGET pexTarget, MV_ADDR_WIN *pAddrDecWin); -+MV_VOID mvCpuIfEnablePex(MV_U32 pexIf, MV_PEX_TYPE pexType); -+#endif -+#if defined(MV_INCLUDE_PCI) -+MV_U32 mvCpuIfPciRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin); -+#endif -+MV_U32 mvCpuIfPciIfRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin); -+ -+MV_VOID mvCpuIfAddDecShow(MV_VOID); -+ -+#if defined(MV88F6281) -+MV_STATUS mvCpuIfBridgeReorderWAInit(void); -+#endif -+ -+#endif /* __INCmvCpuIfh */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfInit.S linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfInit.S ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfInit.S 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfInit.S 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,163 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#define MV_ASMLANGUAGE -+#include "mvOsAsm.h" -+#include "mvDeviceId.h" -+#include "mvCtrlEnvRegs.h" -+#include "mvCpuIfRegs.h" -+#include "mvCtrlEnvAsm.h" -+ -+ -+/******************************************************************************* -+* mvCpuIfPreInit - Make early initialization of CPU interface. -+* -+* DESCRIPTION: -+* The function will initialize the CPU interface parameters that must -+* be initialize before any BUS activity towards the DDR interface, -+* which means it must be executed from ROM. Because of that, the function -+* is implemented in assembly code. -+* The function configure the following CPU config register parameters: -+* 1) CPU2MbusLTickDrv -+* 2) CPU2MbusLTickSample. -+* NOTE: This function must be called AFTER the internal register -+* base is modified to INTER_REGS_BASE. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+* r11 holds return function address. -+*******************************************************************************/ -+#define MV88F6281_PCKG_OPT 2 -+#define MV88F6192_PCKG_OPT 1 -+#define MV88F6180_PCKG_OPT 0 -+ -+ .globl _mvCpuIfPreInit -+_mvCpuIfPreInit: -+ -+ mov r11, LR /* Save link register */ -+ -+ /* Read device ID */ -+ MV_CTRL_MODEL_GET_ASM(r4, r5); -+ -+ /* goto calcConfigReg if device is 6281 */ -+ ldr r5, =MV88F6281_PCKG_OPT -+ cmp r4, r5 -+ beq calcConfigReg -+ -+ /* goto calcConfigReg if device is 6192/6190 */ -+ ldr r5, =MV88F6192_PCKG_OPT -+ cmp r4, r5 -+ beq calcConfigReg -+ -+ /* Else 6180 */ -+ /* Get the "sample on reset" register */ -+ MV_REG_READ_ASM (r4, r5, MPP_SAMPLE_AT_RESET) -+ ldr r5, =MSAR_CPUCLCK_MASK_6180 -+ and r5, r4, r5 -+ mov r5, r5, lsr #MSAR_CPUCLCK_OFFS_6180 -+ -+ ldr r4, =CPU_2_MBUSL_DDR_CLK_1x3 -+ cmp r5, #CPU_2_DDR_CLK_1x3_1 -+ beq setConfigReg -+ -+ ldr r4, =CPU_2_MBUSL_DDR_CLK_1x4 -+ cmp r5, #CPU_2_DDR_CLK_1x4_1 -+ beq setConfigReg -+ b setConfigReg -+ -+calcConfigReg: -+ /* Get the "sample on reset" register */ -+ MV_REG_READ_ASM (r4, r5, MPP_SAMPLE_AT_RESET) -+ ldr r5, =MSAR_DDRCLCK_RTIO_MASK -+ and r5, r4, r5 -+ mov r5, r5, lsr #MSAR_DDRCLCK_RTIO_OFFS -+ -+ ldr r4, =CPU_2_MBUSL_DDR_CLK_1x3 -+ cmp r5, #CPU_2_DDR_CLK_1x3 -+ beq setConfigReg -+ -+ ldr r4, =CPU_2_MBUSL_DDR_CLK_1x4 -+ cmp r5, #CPU_2_DDR_CLK_1x4 -+ beq setConfigReg -+ -+ /* Else */ -+ ldr r4, =0 -+ -+setConfigReg: -+ /* Read CPU Config register */ -+ MV_REG_READ_ASM (r7, r5, CPU_CONFIG_REG) -+ ldr r5, =~(CCR_CPU_2_MBUSL_TICK_DRV_MASK | CCR_CPU_2_MBUSL_TICK_SMPL_MASK) -+ and r7, r7, r5 /* Clear register fields */ -+ orr r7, r7, r4 /* Set the values according to the findings */ -+ MV_REG_WRITE_ASM (r7, r5, CPU_CONFIG_REG) -+ -+done: -+ mov PC, r11 /* r11 is saved link register */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,304 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvCpuIfRegsh -+#define __INCmvCpuIfRegsh -+ -+/****************************************/ -+/* ARM Control and Status Registers Map */ -+/****************************************/ -+ -+#define CPU_CONFIG_REG 0x20100 -+#define CPU_CTRL_STAT_REG 0x20104 -+#define CPU_RSTOUTN_MASK_REG 0x20108 -+#define CPU_SYS_SOFT_RST_REG 0x2010C -+#define CPU_AHB_MBUS_CAUSE_INT_REG 0x20110 -+#define CPU_AHB_MBUS_MASK_INT_REG 0x20114 -+#define CPU_FTDLL_CONFIG_REG 0x20120 -+#define CPU_L2_CONFIG_REG 0x20128 -+ -+ -+ -+/* ARM Configuration register */ -+/* CPU_CONFIG_REG (CCR) */ -+ -+ -+/* Reset vector location */ -+#define CCR_VEC_INIT_LOC_OFFS 1 -+#define CCR_VEC_INIT_LOC_MASK BIT1 -+/* reset at 0x00000000 */ -+#define CCR_VEC_INIT_LOC_0000 (0 << CCR_VEC_INIT_LOC_OFFS) -+/* reset at 0xFFFF0000 */ -+#define CCR_VEC_INIT_LOC_FF00 (1 << CCR_VEC_INIT_LOC_OFFS) -+ -+ -+#define CCR_AHB_ERROR_PROP_OFFS 2 -+#define CCR_AHB_ERROR_PROP_MASK BIT2 -+/* Erros are not propogated to AHB */ -+#define CCR_AHB_ERROR_PROP_NO_INDICATE (0 << CCR_AHB_ERROR_PROP_OFFS) -+/* Erros are propogated to AHB */ -+#define CCR_AHB_ERROR_PROP_INDICATE (1 << CCR_AHB_ERROR_PROP_OFFS) -+ -+ -+#define CCR_ENDIAN_INIT_OFFS 3 -+#define CCR_ENDIAN_INIT_MASK BIT3 -+#define CCR_ENDIAN_INIT_LITTLE (0 << CCR_ENDIAN_INIT_OFFS) -+#define CCR_ENDIAN_INIT_BIG (1 << CCR_ENDIAN_INIT_OFFS) -+ -+ -+#define CCR_INCR_EN_OFFS 4 -+#define CCR_INCR_EN_MASK BIT4 -+#define CCR_INCR_EN BIT4 -+ -+ -+#define CCR_NCB_BLOCKING_OFFS 5 -+#define CCR_NCB_BLOCKING_MASK (1 << CCR_NCB_BLOCKING_OFFS) -+#define CCR_NCB_BLOCKING_NON (0 << CCR_NCB_BLOCKING_OFFS) -+#define CCR_NCB_BLOCKING_EN (1 << CCR_NCB_BLOCKING_OFFS) -+ -+#define CCR_CPU_2_MBUSL_TICK_DRV_OFFS 8 -+#define CCR_CPU_2_MBUSL_TICK_DRV_MASK (0xF << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) -+#define CCR_CPU_2_MBUSL_TICK_SMPL_OFFS 12 -+#define CCR_CPU_2_MBUSL_TICK_SMPL_MASK (0xF << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS) -+#define CCR_ICACH_PREF_BUF_ENABLE BIT16 -+#define CCR_DCACH_PREF_BUF_ENABLE BIT17 -+ -+/* Ratio options for CPU to DDR for 6281/6192/6190 */ -+#define CPU_2_DDR_CLK_1x3 4 -+#define CPU_2_DDR_CLK_1x4 6 -+ -+/* Ratio options for CPU to DDR for 6281 only */ -+#define CPU_2_DDR_CLK_2x9 7 -+#define CPU_2_DDR_CLK_1x5 8 -+#define CPU_2_DDR_CLK_1x6 9 -+ -+/* Ratio options for CPU to DDR for 6180 only */ -+#define CPU_2_DDR_CLK_1x3_1 0x5 -+#define CPU_2_DDR_CLK_1x4_1 0x6 -+ -+/* Default values for CPU to Mbus-L DDR Interface Tick Driver and */ -+/* CPU to Mbus-L Tick Sample fields in CPU config register */ -+ -+#define TICK_DRV_1x1 0 -+#define TICK_DRV_1x2 0 -+#define TICK_DRV_1x3 1 -+#define TICK_DRV_1x4 2 -+#define TICK_SMPL_1x1 0 -+#define TICK_SMPL_1x2 1 -+#define TICK_SMPL_1x3 0 -+#define TICK_SMPL_1x4 0 -+ -+#define CPU_2_MBUSL_DDR_CLK_1x2 \ -+ ((TICK_DRV_1x2 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \ -+ (TICK_SMPL_1x2 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS)) -+#define CPU_2_MBUSL_DDR_CLK_1x3 \ -+ ((TICK_DRV_1x3 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \ -+ (TICK_SMPL_1x3 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS)) -+#define CPU_2_MBUSL_DDR_CLK_1x4 \ -+ ((TICK_DRV_1x4 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \ -+ (TICK_SMPL_1x4 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS)) -+ -+/* ARM Control and Status register */ -+/* CPU_CTRL_STAT_REG (CCSR) */ -+ -+ -+/* -+This is used to block PCI express\PCI from access Socrates/Feroceon GP -+while ARM boot is still in progress -+*/ -+ -+#define CCSR_PCI_ACCESS_OFFS 0 -+#define CCSR_PCI_ACCESS_MASK BIT0 -+#define CCSR_PCI_ACCESS_ENABLE (0 << CCSR_PCI_ACCESS_OFFS) -+#define CCSR_PCI_ACCESS_DISBALE (1 << CCSR_PCI_ACCESS_OFFS) -+ -+#define CCSR_ARM_RESET BIT1 -+#define CCSR_SELF_INT BIT2 -+#define CCSR_BIG_ENDIAN BIT15 -+ -+ -+/* RSTOUTn Mask Register */ -+/* CPU_RSTOUTN_MASK_REG (CRMR) */ -+ -+#define CRMR_PEX_RST_OUT_OFFS 0 -+#define CRMR_PEX_RST_OUT_MASK BIT0 -+#define CRMR_PEX_RST_OUT_ENABLE (1 << CRMR_PEX_RST_OUT_OFFS) -+#define CRMR_PEX_RST_OUT_DISABLE (0 << CRMR_PEX_RST_OUT_OFFS) -+ -+#define CRMR_WD_RST_OUT_OFFS 1 -+#define CRMR_WD_RST_OUT_MASK BIT1 -+#define CRMR_WD_RST_OUT_ENABLE (1 << CRMR_WD_RST_OUT_OFFS) -+#define CRMR_WD_RST_OUT_DISBALE (0 << CRMR_WD_RST_OUT_OFFS) -+ -+#define CRMR_SOFT_RST_OUT_OFFS 2 -+#define CRMR_SOFT_RST_OUT_MASK BIT2 -+#define CRMR_SOFT_RST_OUT_ENABLE (1 << CRMR_SOFT_RST_OUT_OFFS) -+#define CRMR_SOFT_RST_OUT_DISBALE (0 << CRMR_SOFT_RST_OUT_OFFS) -+ -+/* System Software Reset Register */ -+/* CPU_SYS_SOFT_RST_REG (CSSRR) */ -+ -+#define CSSRR_SYSTEM_SOFT_RST BIT0 -+ -+/* AHB to Mbus Bridge Interrupt Cause Register*/ -+/* CPU_AHB_MBUS_CAUSE_INT_REG (CAMCIR) */ -+ -+#define CAMCIR_ARM_SELF_INT BIT0 -+#define CAMCIR_ARM_TIMER0_INT_REQ BIT1 -+#define CAMCIR_ARM_TIMER1_INT_REQ BIT2 -+#define CAMCIR_ARM_WD_TIMER_INT_REQ BIT3 -+ -+ -+/* AHB to Mbus Bridge Interrupt Mask Register*/ -+/* CPU_AHB_MBUS_MASK_INT_REG (CAMMIR) */ -+ -+#define CAMCIR_ARM_SELF_INT_OFFS 0 -+#define CAMCIR_ARM_SELF_INT_MASK BIT0 -+#define CAMCIR_ARM_SELF_INT_EN (1 << CAMCIR_ARM_SELF_INT_OFFS) -+#define CAMCIR_ARM_SELF_INT_DIS (0 << CAMCIR_ARM_SELF_INT_OFFS) -+ -+ -+#define CAMCIR_ARM_TIMER0_INT_REQ_OFFS 1 -+#define CAMCIR_ARM_TIMER0_INT_REQ_MASK BIT1 -+#define CAMCIR_ARM_TIMER0_INT_REQ_EN (1 << CAMCIR_ARM_TIMER0_INT_REQ_OFFS) -+#define CAMCIR_ARM_TIMER0_INT_REQ_DIS (0 << CAMCIR_ARM_TIMER0_INT_REQ_OFFS) -+ -+#define CAMCIR_ARM_TIMER1_INT_REQ_OFFS 2 -+#define CAMCIR_ARM_TIMER1_INT_REQ_MASK BIT2 -+#define CAMCIR_ARM_TIMER1_INT_REQ_EN (1 << CAMCIR_ARM_TIMER1_INT_REQ_OFFS) -+#define CAMCIR_ARM_TIMER1_INT_REQ_DIS (0 << CAMCIR_ARM_TIMER1_INT_REQ_OFFS) -+ -+#define CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS 3 -+#define CAMCIR_ARM_WD_TIMER_INT_REQ_MASK BIT3 -+#define CAMCIR_ARM_WD_TIMER_INT_REQ_EN (1 << CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS) -+#define CAMCIR_ARM_WD_TIMER_INT_REQ_DIS (0 << CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS) -+ -+/* CPU FTDLL Config register (CFCR) fields */ -+#define CFCR_FTDLL_ICACHE_TAG_OFFS 0 -+#define CFCR_FTDLL_ICACHE_TAG_MASK (0x7F << CFCR_FTDLL_ICACHE_TAG_OFFS) -+#define CFCR_FTDLL_DCACHE_TAG_OFFS 8 -+#define CFCR_FTDLL_DCACHE_TAG_MASK (0x7F << CFCR_FTDLL_DCACHE_TAG_OFFS) -+#define CFCR_FTDLL_OVERWRITE_ENABLE (1 << 15) -+/* For Orion 2 D2 only */ -+#define CFCR_MRVL_CPU_ID_OFFS 16 -+#define CFCR_MRVL_CPU_ID_MASK (0x1 << CFCR_MRVL_CPU_ID_OFFS) -+#define CFCR_ARM_CPU_ID (0x0 << CFCR_MRVL_CPU_ID_OFFS) -+#define CFCR_MRVL_CPU_ID (0x1 << CFCR_MRVL_CPU_ID_OFFS) -+#define CFCR_VFP_SUB_ARC_NUM_OFFS 7 -+#define CFCR_VFP_SUB_ARC_NUM_MASK (0x1 << CFCR_VFP_SUB_ARC_NUM_OFFS) -+#define CFCR_VFP_SUB_ARC_NUM_1 (0x0 << CFCR_VFP_SUB_ARC_NUM_OFFS) -+#define CFCR_VFP_SUB_ARC_NUM_2 (0x1 << CFCR_VFP_SUB_ARC_NUM_OFFS) -+ -+/* CPU_L2_CONFIG_REG fields */ -+#ifdef MV_CPU_LE -+#define CL2CR_L2_ECC_EN_OFFS 2 -+#define CL2CR_L2_WT_MODE_OFFS 4 -+#else -+#define CL2CR_L2_ECC_EN_OFFS 26 -+#define CL2CR_L2_WT_MODE_OFFS 28 -+#endif -+ -+#define CL2CR_L2_ECC_EN_MASK (1 << CL2CR_L2_ECC_EN_OFFS) -+#define CL2CR_L2_WT_MODE_MASK (1 << CL2CR_L2_WT_MODE_OFFS) -+ -+/*******************************************/ -+/* Main Interrupt Controller Registers Map */ -+/*******************************************/ -+ -+#define CPU_MAIN_INT_CAUSE_REG 0x20200 -+#define CPU_MAIN_IRQ_MASK_REG 0x20204 -+#define CPU_MAIN_FIQ_MASK_REG 0x20208 -+#define CPU_ENPOINT_MASK_REG 0x2020C -+#define CPU_MAIN_INT_CAUSE_HIGH_REG 0x20210 -+#define CPU_MAIN_IRQ_MASK_HIGH_REG 0x20214 -+#define CPU_MAIN_FIQ_MASK_HIGH_REG 0x20218 -+#define CPU_ENPOINT_MASK_HIGH_REG 0x2021C -+ -+ -+/*******************************************/ -+/* ARM Doorbell Registers Map */ -+/*******************************************/ -+ -+#define CPU_HOST_TO_ARM_DRBL_REG 0x20400 -+#define CPU_HOST_TO_ARM_MASK_REG 0x20404 -+#define CPU_ARM_TO_HOST_DRBL_REG 0x20408 -+#define CPU_ARM_TO_HOST_MASK_REG 0x2040C -+ -+ -+ -+/* CPU control register map */ -+/* Set bits means value is about to change according to new value */ -+#define CPU_CONFIG_DEFAULT_MASK (CCR_VEC_INIT_LOC_MASK | CCR_AHB_ERROR_PROP_MASK) -+ -+#define CPU_CONFIG_DEFAULT (CCR_VEC_INIT_LOC_FF00) -+ -+/* CPU Control and status defaults */ -+#define CPU_CTRL_STAT_DEFAULT_MASK (CCSR_PCI_ACCESS_MASK) -+ -+ -+#define CPU_CTRL_STAT_DEFAULT (CCSR_PCI_ACCESS_ENABLE) -+ -+#endif /* __INCmvCpuIfRegsh */ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,324 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#include "mvSysAudio.h" -+ -+/******************************************************************************* -+* mvAudioWinSet - Set AUDIO target address window -+* -+* DESCRIPTION: -+* This function sets a peripheral target (e.g. SDRAM bank0, PCI_MEM0) -+* address window, also known as address decode window. -+* After setting this target window, the AUDIO will be able to access the -+* target within the address window. -+* -+* INPUT: -+* winNum - AUDIO target address decode window number. -+* pAddrDecWin - AUDIO target window data structure. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR if address window overlapps with other address decode windows. -+* MV_BAD_PARAM if base address is invalid parameter or target is -+* unknown. -+* -+*******************************************************************************/ -+MV_STATUS mvAudioWinSet(MV_U32 winNum, MV_AUDIO_DEC_WIN *pAddrDecWin) -+{ -+ MV_TARGET_ATTRIB targetAttribs; -+ MV_DEC_REGS decRegs; -+ -+ /* Parameter checking */ -+ if (winNum >= MV_AUDIO_MAX_ADDR_DECODE_WIN) -+ { -+ mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvAudioWinSet:Error setting AUDIO window %d to "\ -+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, -+ mvCtrlTargetNameGet(pAddrDecWin->target), -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ decRegs.baseReg = 0; -+ decRegs.sizeReg = 0; -+ -+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) -+ { -+ mvOsPrintf("%s: mvCtrlAddrDecToReg Failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); -+ -+ /* set attributes */ -+ decRegs.sizeReg &= ~MV_AUDIO_WIN_ATTR_MASK; -+ decRegs.sizeReg |= (targetAttribs.attrib << MV_AUDIO_WIN_ATTR_OFFSET); -+ -+ /* set target ID */ -+ decRegs.sizeReg &= ~MV_AUDIO_WIN_TARGET_MASK; -+ decRegs.sizeReg |= (targetAttribs.targetId << MV_AUDIO_WIN_TARGET_OFFSET); -+ -+ if (pAddrDecWin->enable == MV_TRUE) -+ { -+ decRegs.sizeReg |= MV_AUDIO_WIN_ENABLE_MASK; -+ } -+ else -+ { -+ decRegs.sizeReg &= ~MV_AUDIO_WIN_ENABLE_MASK; -+ } -+ -+ MV_REG_WRITE( MV_AUDIO_WIN_CTRL_REG(winNum), decRegs.sizeReg); -+ MV_REG_WRITE( MV_AUDIO_WIN_BASE_REG(winNum), decRegs.baseReg); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvAudioWinGet - Get AUDIO peripheral target address window. -+* -+* DESCRIPTION: -+* Get AUDIO peripheral target address window. -+* -+* INPUT: -+* winNum - AUDIO target address decode window number. -+* -+* OUTPUT: -+* pAddrDecWin - AUDIO target window data structure. -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvAudioWinGet(MV_U32 winNum, MV_AUDIO_DEC_WIN *pAddrDecWin) -+{ -+ MV_DEC_REGS decRegs; -+ MV_TARGET_ATTRIB targetAttrib; -+ -+ /* Parameter checking */ -+ if (winNum >= MV_AUDIO_MAX_ADDR_DECODE_WIN) -+ { -+ mvOsPrintf("%s : ERR. Invalid winNum %d\n", -+ __FUNCTION__, winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ decRegs.baseReg = MV_REG_READ( MV_AUDIO_WIN_BASE_REG(winNum) ); -+ decRegs.sizeReg = MV_REG_READ( MV_AUDIO_WIN_CTRL_REG(winNum) ); -+ -+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs, &pAddrDecWin->addrWin) ) -+ { -+ mvOsPrintf("%s: mvCtrlRegToAddrDec Failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ /* attrib and targetId */ -+ targetAttrib.attrib = (decRegs.sizeReg & MV_AUDIO_WIN_ATTR_MASK) >> -+ MV_AUDIO_WIN_ATTR_OFFSET; -+ targetAttrib.targetId = (decRegs.sizeReg & MV_AUDIO_WIN_TARGET_MASK) >> -+ MV_AUDIO_WIN_TARGET_OFFSET; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ /* Check if window is enabled */ -+ if(decRegs.sizeReg & MV_AUDIO_WIN_ENABLE_MASK) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ } -+ return MV_OK; -+} -+/******************************************************************************* -+* mvAudioAddrDecShow - Print the AUDIO address decode map. -+* -+* DESCRIPTION: -+* This function print the AUDIO address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvAudioAddrDecShow(MV_VOID) -+{ -+ -+ MV_AUDIO_DEC_WIN win; -+ int i; -+ -+ if (MV_FALSE == mvCtrlPwrClckGet(AUDIO_UNIT_ID, 0)) -+ return; -+ -+ -+ mvOsOutput( "\n" ); -+ mvOsOutput( "AUDIO:\n" ); -+ mvOsOutput( "----\n" ); -+ -+ for( i = 0; i < MV_AUDIO_MAX_ADDR_DECODE_WIN; i++ ) -+ { -+ memset( &win, 0, sizeof(MV_AUDIO_DEC_WIN) ); -+ -+ mvOsOutput( "win%d - ", i ); -+ -+ if( mvAudioWinGet( i, &win ) == MV_OK ) -+ { -+ if( win.enable ) -+ { -+ mvOsOutput( "%s base %08x, ", -+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); -+ mvOsOutput( "...." ); -+ -+ mvSizePrint( win.addrWin.size ); -+ -+ mvOsOutput( "\n" ); -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ } -+ } -+} -+ -+ -+/******************************************************************************* -+* mvAudioWinInit - Initialize the integrated AUDIO target address window. -+* -+* DESCRIPTION: -+* Initialize the AUDIO peripheral target address window. -+* -+* INPUT: -+* -+* -+* OUTPUT: -+* -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvAudioInit(MV_VOID) -+{ -+ int winNum; -+ MV_AUDIO_DEC_WIN audioWin; -+ MV_CPU_DEC_WIN cpuAddrDecWin; -+ MV_U32 status; -+ -+ mvAudioHalInit(); -+ -+ /* Initiate Audio address decode */ -+ -+ /* First disable all address decode windows */ -+ for(winNum = 0; winNum < MV_AUDIO_MAX_ADDR_DECODE_WIN; winNum++) -+ { -+ MV_U32 regVal = MV_REG_READ(MV_AUDIO_WIN_CTRL_REG(winNum)); -+ regVal &= ~MV_AUDIO_WIN_ENABLE_MASK; -+ MV_REG_WRITE(MV_AUDIO_WIN_CTRL_REG(winNum), regVal); -+ } -+ -+ for(winNum = 0; winNum < MV_AUDIO_MAX_ADDR_DECODE_WIN; winNum++) -+ { -+ -+ /* We will set the Window to DRAM_CS0 in default */ -+ /* first get attributes from CPU If */ -+ status = mvCpuIfTargetWinGet(SDRAM_CS0, -+ &cpuAddrDecWin); -+ -+ if (MV_OK != status) -+ { -+ mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ if (cpuAddrDecWin.enable == MV_TRUE) -+ { -+ audioWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; -+ audioWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; -+ audioWin.addrWin.size = cpuAddrDecWin.addrWin.size; -+ audioWin.enable = MV_TRUE; -+ audioWin.target = SDRAM_CS0; -+ -+ if(MV_OK != mvAudioWinSet(winNum, &audioWin)) -+ { -+ return MV_ERROR; -+ } -+ } -+ } -+ -+ return MV_OK; -+} -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,123 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#ifndef __INCMVSysAudioH -+#define __INCMVSysAudioH -+ -+#include "mvCommon.h" -+#include "audio/mvAudio.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+ -+/***********************************/ -+/* Audio Address Decoding registers*/ -+/***********************************/ -+ -+#define MV_AUDIO_MAX_ADDR_DECODE_WIN 2 -+#define MV_AUDIO_RECORD_WIN_NUM 0 -+#define MV_AUDIO_PLAYBACK_WIN_NUM 1 -+ -+#define MV_AUDIO_WIN_CTRL_REG(win) (AUDIO_REG_BASE + 0xA04 + ((win)<<3)) -+#define MV_AUDIO_WIN_BASE_REG(win) (AUDIO_REG_BASE + 0xA00 + ((win)<<3)) -+ -+#define MV_AUDIO_RECORD_WIN_CTRL_REG MV_AUDIO_WIN_CTRL_REG(MV_AUDIO_RECORD_WIN_NUM) -+#define MV_AUDIO_RECORD_WIN_BASE_REG MV_AUDIO_WIN_BASE_REG(MV_AUDIO_RECORD_WIN_NUM) -+#define MV_AUDIO_PLAYBACK_WIN_CTRL_REG MV_AUDIO_WIN_CTRL_REG(MV_AUDIO_PLAYBACK_WIN_NUM) -+#define MV_AUDIO_PLAYBACK_WIN_BASE_REG MV_AUDIO_WIN_BASE_REG(MV_AUDIO_PLAYBACK_WIN_NUM) -+ -+ -+/* BITs in Windows 0-3 Control and Base Registers */ -+#define MV_AUDIO_WIN_ENABLE_BIT 0 -+#define MV_AUDIO_WIN_ENABLE_MASK (1<= 2) -+MV_TARGET tdmaAddrDecPrioTable[] = -+{ -+#if defined(MV_INCLUDE_SDRAM_CS0) -+ SDRAM_CS0, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS1) -+ SDRAM_CS1, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS2) -+ SDRAM_CS2, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS3) -+ SDRAM_CS3, -+#endif -+#if defined(MV_INCLUDE_PEX) -+ PEX0_MEM, -+#endif -+ -+ TBL_TERM -+}; -+ -+/******************************************************************************* -+* mvCesaWinGet - Get TDMA target address window. -+* -+* DESCRIPTION: -+* Get TDMA target address window. -+* -+* INPUT: -+* winNum - TDMA target address decode window number. -+* -+* OUTPUT: -+* pDecWin - TDMA target window data structure. -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+static MV_STATUS mvCesaWinGet(MV_U32 winNum, MV_DEC_WIN *pDecWin) -+{ -+ MV_DEC_WIN_PARAMS winParam; -+ MV_U32 sizeReg, baseReg; -+ -+ /* Parameter checking */ -+ if (winNum >= MV_CESA_TDMA_ADDR_DEC_WIN) -+ { -+ mvOsPrintf("%s : ERR. Invalid winNum %d\n", -+ __FUNCTION__, winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ baseReg = MV_REG_READ( MV_CESA_TDMA_BASE_ADDR_REG(winNum) ); -+ sizeReg = MV_REG_READ( MV_CESA_TDMA_WIN_CTRL_REG(winNum) ); -+ -+ /* Check if window is enabled */ -+ if(sizeReg & MV_CESA_TDMA_WIN_ENABLE_MASK) -+ { -+ pDecWin->enable = MV_TRUE; -+ -+ /* Extract window parameters from registers */ -+ winParam.targetId = (sizeReg & MV_CESA_TDMA_WIN_TARGET_MASK) >> MV_CESA_TDMA_WIN_TARGET_OFFSET; -+ winParam.attrib = (sizeReg & MV_CESA_TDMA_WIN_ATTR_MASK) >> MV_CESA_TDMA_WIN_ATTR_OFFSET; -+ winParam.size = (sizeReg & MV_CESA_TDMA_WIN_SIZE_MASK) >> MV_CESA_TDMA_WIN_SIZE_OFFSET; -+ winParam.baseAddr = (baseReg & MV_CESA_TDMA_WIN_BASE_MASK); -+ -+ /* Translate the decode window parameters to address decode struct */ -+ if (MV_OK != mvCtrlParamsToAddrDec(&winParam, pDecWin)) -+ { -+ mvOsPrintf("Failed to translate register parameters to CESA address" \ -+ " decode window structure\n"); -+ return MV_ERROR; -+ } -+ } -+ else -+ { -+ pDecWin->enable = MV_FALSE; -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* cesaWinOverlapDetect - Detect CESA TDMA address windows overlapping -+* -+* DESCRIPTION: -+* An unpredicted behaviur is expected in case TDMA address decode -+* windows overlapps. -+* This function detects TDMA address decode windows overlapping of a -+* specified window. The function does not check the window itself for -+* overlapping. The function also skipps disabled address decode windows. -+* -+* INPUT: -+* winNum - address decode window number. -+* pAddrDecWin - An address decode window struct. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE - if the given address window overlap current address -+* decode map, -+* MV_FALSE - otherwise, MV_ERROR if reading invalid data -+* from registers. -+* -+*******************************************************************************/ -+static MV_STATUS cesaWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 winNumIndex; -+ MV_DEC_WIN addrDecWin; -+ -+ for(winNumIndex=0; winNumIndex= MV_CESA_TDMA_ADDR_DEC_WIN) -+ { -+ mvOsPrintf("mvCesaTdmaWinSet: ERR. Invalid win num %d\n",winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlapps with current windows */ -+ if (MV_TRUE == cesaWinOverlapDetect(winNum, &pDecWin->addrWin)) -+ { -+ mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); -+ return MV_ERROR; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pDecWin->addrWin.baseLow, pDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvCesaTdmaWinSet: Error setting CESA TDMA window %d to "\ -+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, -+ mvCtrlTargetNameGet(pDecWin->target), -+ pDecWin->addrWin.baseLow, -+ pDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ if(MV_OK != mvCtrlAddrDecToParams(pDecWin, &winParams)) -+ { -+ mvOsPrintf("%s: mvCtrlAddrDecToParams Failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ /* set Size, Attributes and TargetID */ -+ sizeReg = (((winParams.targetId << MV_CESA_TDMA_WIN_TARGET_OFFSET) & MV_CESA_TDMA_WIN_TARGET_MASK) | -+ ((winParams.attrib << MV_CESA_TDMA_WIN_ATTR_OFFSET) & MV_CESA_TDMA_WIN_ATTR_MASK) | -+ ((winParams.size << MV_CESA_TDMA_WIN_SIZE_OFFSET) & MV_CESA_TDMA_WIN_SIZE_MASK)); -+ -+ if (pDecWin->enable == MV_TRUE) -+ { -+ sizeReg |= MV_CESA_TDMA_WIN_ENABLE_MASK; -+ } -+ else -+ { -+ sizeReg &= ~MV_CESA_TDMA_WIN_ENABLE_MASK; -+ } -+ -+ /* Update Base value */ -+ baseReg = (winParams.baseAddr & MV_CESA_TDMA_WIN_BASE_MASK); -+ -+ MV_REG_WRITE( MV_CESA_TDMA_WIN_CTRL_REG(winNum), sizeReg); -+ MV_REG_WRITE( MV_CESA_TDMA_BASE_ADDR_REG(winNum), baseReg); -+ -+ return MV_OK; -+} -+ -+ -+static MV_STATUS mvCesaTdmaAddrDecInit (void) -+{ -+ MV_U32 winNum; -+ MV_STATUS status; -+ MV_CPU_DEC_WIN cpuAddrDecWin; -+ MV_DEC_WIN cesaWin; -+ MV_U32 winPrioIndex = 0; -+ -+ /* First disable all address decode windows */ -+ for(winNum=0; winNum= 2 */ -+ -+ -+ -+ -+MV_STATUS mvCesaInit (int numOfSession, int queueDepth, char* pSramBase, void *osHandle) -+{ -+ MV_U32 cesaCryptEngBase; -+ MV_CPU_DEC_WIN addrDecWin; -+ -+ if(sizeof(MV_CESA_SRAM_MAP) > MV_CESA_SRAM_SIZE) -+ { -+ mvOsPrintf("mvCesaInit: Wrong SRAM map - %ld > %d\n", -+ sizeof(MV_CESA_SRAM_MAP), MV_CESA_SRAM_SIZE); -+ return MV_FAIL; -+ } -+#if 0 -+ if (mvCpuIfTargetWinGet(CRYPT_ENG, &addrDecWin) == MV_OK) -+ cesaCryptEngBase = addrDecWin.addrWin.baseLow; -+ else -+ { -+ mvOsPrintf("mvCesaInit: ERR. mvCpuIfTargetWinGet failed\n"); -+ return MV_ERROR; -+ } -+#else -+ cesaCryptEngBase = (MV_U32)pSramBase; -+#endif -+ -+#if 0 /* Already done in the platform init */ -+#if (MV_CESA_VERSION >= 2) -+ mvCesaTdmaAddrDecInit(); -+#endif /* MV_CESA_VERSION >= 2 */ -+#endif -+ return mvCesaHalInit(numOfSession, queueDepth, pSramBase, cesaCryptEngBase, -+ osHandle); -+ -+} -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,100 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __mvSysCesa_h__ -+#define __mvSysCesa_h__ -+ -+ -+#include "mvCommon.h" -+#include "cesa/mvCesa.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+ -+/***************************** TDMA Registers *************************************/ -+ -+#define MV_CESA_TDMA_ADDR_DEC_WIN 4 -+ -+#define MV_CESA_TDMA_BASE_ADDR_REG(win) (MV_CESA_TDMA_REG_BASE + 0xa00 + (win<<3)) -+ -+#define MV_CESA_TDMA_WIN_CTRL_REG(win) (MV_CESA_TDMA_REG_BASE + 0xa04 + (win<<3)) -+ -+#define MV_CESA_TDMA_WIN_ENABLE_BIT 0 -+#define MV_CESA_TDMA_WIN_ENABLE_MASK (1 << MV_CESA_TDMA_WIN_ENABLE_BIT) -+ -+#define MV_CESA_TDMA_WIN_TARGET_OFFSET 4 -+#define MV_CESA_TDMA_WIN_TARGET_MASK (0xf << MV_CESA_TDMA_WIN_TARGET_OFFSET) -+ -+#define MV_CESA_TDMA_WIN_ATTR_OFFSET 8 -+#define MV_CESA_TDMA_WIN_ATTR_MASK (0xff << MV_CESA_TDMA_WIN_ATTR_OFFSET) -+ -+#define MV_CESA_TDMA_WIN_SIZE_OFFSET 16 -+#define MV_CESA_TDMA_WIN_SIZE_MASK (0xFFFF << MV_CESA_TDMA_WIN_SIZE_OFFSET) -+ -+#define MV_CESA_TDMA_WIN_BASE_OFFSET 16 -+#define MV_CESA_TDMA_WIN_BASE_MASK (0xFFFF << MV_CESA_TDMA_WIN_BASE_OFFSET) -+ -+ -+MV_STATUS mvCesaInit (int numOfSession, int queueDepth, char* pSramBase, void *osHandle); -+ -+#endif -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,348 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+/* includes */ -+ -+#include "ddr2/mvDramIf.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+#include "ctrlEnv/sys/mvSysDram.h" -+ -+/* #define MV_DEBUG */ -+#ifdef MV_DEBUG -+#define DB(x) x -+#else -+#define DB(x) -+#endif -+ -+static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin); -+ -+/******************************************************************************* -+* mvDramIfWinSet - Set DRAM interface address decode window -+* -+* DESCRIPTION: -+* This function sets DRAM interface address decode window. -+* -+* INPUT: -+* target - System target. Use only SDRAM targets. -+* pAddrDecWin - SDRAM address window structure. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK -+* otherwise. -+*******************************************************************************/ -+MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) -+{ -+ MV_U32 baseReg=0,sizeReg=0; -+ MV_U32 baseToReg=0 , sizeToReg=0; -+ -+ /* Check parameters */ -+ if (!MV_TARGET_IS_DRAM(target)) -+ { -+ mvOsPrintf("mvDramIfWinSet: target %d is not SDRAM\n", target); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlaps with current enabled windows */ -+ if (MV_TRUE == sdramIfWinOverlap(target, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("mvDramIfWinSet: ERR. Target %d overlaps\n", target); -+ return MV_BAD_PARAM; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvDramIfWinSet:Error setting DRAM interface window %d."\ -+ "\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ target, -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ /* read base register*/ -+ baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(0,target)); -+ -+ /* read size register */ -+ sizeReg = MV_REG_READ(SDRAM_SIZE_REG(0,target)); -+ -+ /* BaseLow[31:16] => base register [31:16] */ -+ baseToReg = pAddrDecWin->addrWin.baseLow & SCBAR_BASE_MASK; -+ -+ /* Write to address decode Base Address Register */ -+ baseReg &= ~SCBAR_BASE_MASK; -+ baseReg |= baseToReg; -+ -+ /* Translate the given window size to register format */ -+ sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, SCSR_SIZE_ALIGNMENT); -+ -+ /* Size parameter validity check. */ -+ if (-1 == sizeToReg) -+ { -+ mvOsPrintf("mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n",target); -+ return MV_BAD_PARAM; -+ } -+ -+ /* set size */ -+ sizeReg &= ~SCSR_SIZE_MASK; -+ /* Size is located at upper 16 bits */ -+ sizeReg |= (sizeToReg << SCSR_SIZE_OFFS); -+ -+ /* enable/Disable */ -+ if (MV_TRUE == pAddrDecWin->enable) -+ { -+ sizeReg |= SCSR_WIN_EN; -+ } -+ else -+ { -+ sizeReg &= ~SCSR_WIN_EN; -+ } -+ -+ /* 3) Write to address decode Base Address Register */ -+ MV_REG_WRITE(SDRAM_BASE_ADDR_REG(0,target), baseReg); -+ -+ /* Write to address decode Size Register */ -+ MV_REG_WRITE(SDRAM_SIZE_REG(0,target), sizeReg); -+ -+ return MV_OK; -+} -+/******************************************************************************* -+* mvDramIfWinGet - Get DRAM interface address decode window -+* -+* DESCRIPTION: -+* This function gets DRAM interface address decode window. -+* -+* INPUT: -+* target - System target. Use only SDRAM targets. -+* -+* OUTPUT: -+* pAddrDecWin - SDRAM address window structure. -+* -+* RETURN: -+* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK -+* otherwise. -+*******************************************************************************/ -+MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) -+{ -+ MV_U32 baseReg,sizeReg; -+ MV_U32 sizeRegVal; -+ /* Check parameters */ -+ if (!MV_TARGET_IS_DRAM(target)) -+ { -+ mvOsPrintf("mvDramIfWinGet: target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ /* Read base and size registers */ -+ sizeReg = MV_REG_READ(SDRAM_SIZE_REG(0,target)); -+ baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(0,target)); -+ -+ sizeRegVal = (sizeReg & SCSR_SIZE_MASK) >> SCSR_SIZE_OFFS; -+ -+ pAddrDecWin->addrWin.size = ctrlRegToSize(sizeRegVal, -+ SCSR_SIZE_ALIGNMENT); -+ -+ /* Check if ctrlRegToSize returned OK */ -+ if (-1 == pAddrDecWin->addrWin.size) -+ { -+ mvOsPrintf("mvDramIfWinGet: size of target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ /* Extract base address */ -+ /* Base register [31:16] ==> baseLow[31:16] */ -+ pAddrDecWin->addrWin.baseLow = baseReg & SCBAR_BASE_MASK; -+ -+ pAddrDecWin->addrWin.baseHigh = 0; -+ -+ -+ if (sizeReg & SCSR_WIN_EN) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ } -+ -+ return MV_OK; -+} -+/******************************************************************************* -+* mvDramIfWinEnable - Enable/Disable SDRAM address decode window -+* -+* DESCRIPTION: -+* This function enable/Disable SDRAM address decode window. -+* -+* INPUT: -+* target - System target. Use only SDRAM targets. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR in case function parameter are invalid, MV_OK otherewise. -+* -+*******************************************************************************/ -+MV_STATUS mvDramIfWinEnable(MV_TARGET target, MV_BOOL enable) -+{ -+ MV_DRAM_DEC_WIN addrDecWin; -+ -+ /* Check parameters */ -+ if (!MV_TARGET_IS_DRAM(target)) -+ { -+ mvOsPrintf("mvDramIfWinEnable: target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ if (enable == MV_TRUE) -+ { /* First check for overlap with other enabled windows */ -+ if (MV_OK != mvDramIfWinGet(target, &addrDecWin)) -+ { -+ mvOsPrintf("mvDramIfWinEnable:ERR. Getting target %d failed.\n", -+ target); -+ return MV_ERROR; -+ } -+ /* Check for overlapping */ -+ if (MV_FALSE == sdramIfWinOverlap(target, &(addrDecWin.addrWin))) -+ { -+ /* No Overlap. Enable address decode winNum window */ -+ MV_REG_BIT_SET(SDRAM_SIZE_REG(0,target), SCSR_WIN_EN); -+ } -+ else -+ { /* Overlap detected */ -+ mvOsPrintf("mvDramIfWinEnable: ERR. Target %d overlap detect\n", -+ target); -+ return MV_ERROR; -+ } -+ } -+ else -+ { /* Disable address decode winNum window */ -+ MV_REG_BIT_RESET(SDRAM_SIZE_REG(0, target), SCSR_WIN_EN); -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* sdramIfWinOverlap - Check if an address window overlap an SDRAM address window -+* -+* DESCRIPTION: -+* This function scan each SDRAM address decode window to test if it -+* overlapps the given address windoow -+* -+* INPUT: -+* target - SDRAM target where the function skips checking. -+* pAddrDecWin - The tested address window for overlapping with -+* SDRAM windows. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlaps any enabled address -+* decode map, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_TARGET targetNum; -+ MV_DRAM_DEC_WIN addrDecWin; -+ -+ for(targetNum = SDRAM_CS0; targetNum < MV_DRAM_MAX_CS ; targetNum++) -+ { -+ /* don't check our winNum or illegal targets */ -+ if (targetNum == target) -+ { -+ continue; -+ } -+ -+ /* Get window parameters */ -+ if (MV_OK != mvDramIfWinGet(targetNum, &addrDecWin)) -+ { -+ mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); -+ return MV_ERROR; -+ } -+ -+ /* Do not check disabled windows */ -+ if (MV_FALSE == addrDecWin.enable) -+ { -+ continue; -+ } -+ -+ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) -+ { -+ mvOsPrintf( -+ "sdramIfWinOverlap: Required target %d overlap winNum %d\n", -+ target, targetNum); -+ return MV_TRUE; -+ } -+ } -+ -+ return MV_FALSE; -+} -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,80 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __sysDram -+#define __sysDram -+ -+/* This structure describes CPU interface address decode window */ -+typedef struct _mvDramIfDecWin -+{ -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+}MV_DRAM_DEC_WIN; -+ -+MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); -+MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); -+MV_STATUS mvDramIfWinEnable(MV_TARGET target, MV_BOOL enable); -+ -+#endif -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,658 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#include "ctrlEnv/sys/mvSysGbe.h" -+ -+ -+ -+typedef struct _mvEthDecWin -+{ -+ MV_TARGET target; -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+}MV_ETH_DEC_WIN; -+ -+MV_TARGET ethAddrDecPrioTap[] = -+{ -+#if defined(MV_INCLUDE_SDRAM_CS0) -+ SDRAM_CS0, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS1) -+ SDRAM_CS1, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS2) -+ SDRAM_CS2, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS3) -+ SDRAM_CS3, -+#endif -+#if defined(MV_INCLUDE_DEVICE_CS0) -+ DEVICE_CS0, -+#endif -+#if defined(MV_INCLUDE_DEVICE_CS1) -+ DEVICE_CS1, -+#endif -+#if defined(MV_INCLUDE_DEVICE_CS2) -+ DEVICE_CS2, -+#endif -+#if defined(MV_INCLUDE_DEVICE_CS3) -+ DEVICE_CS3, -+#endif -+#if defined(MV_INCLUDE_PEX) -+ PEX0_IO, -+#endif -+ TBL_TERM -+}; -+ -+static MV_STATUS ethWinOverlapDetect(int port, MV_U32 winNum, MV_ADDR_WIN *pAddrWin); -+static MV_STATUS mvEthWinSet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin); -+static MV_STATUS mvEthWinGet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin); -+ -+ -+/******************************************************************************* -+* mvEthWinInit - Initialize ETH address decode windows -+* -+* DESCRIPTION: -+* This function initialize ETH window decode unit. It set the -+* default address decode windows of the unit. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR if setting fail. -+*******************************************************************************/ -+/* Configure EthDrv memory map registes. */ -+MV_STATUS mvEthWinInit (int port) -+{ -+ MV_U32 winNum, status, winPrioIndex=0, i, regVal=0; -+ MV_ETH_DEC_WIN ethWin; -+ MV_CPU_DEC_WIN cpuAddrDecWin; -+ static MV_U32 accessProtReg = 0; -+ -+#if (MV_ETH_VERSION <= 1) -+ static MV_BOOL isFirst = MV_TRUE; -+ -+ if(isFirst == MV_FALSE) -+ { -+ MV_REG_WRITE(ETH_ACCESS_PROTECT_REG(port), accessProtReg); -+ return MV_OK; -+ } -+ isFirst = MV_FALSE; -+#endif /* MV_GIGA_ETH_VERSION */ -+ -+ /* Initiate Ethernet address decode */ -+ -+ /* First disable all address decode windows */ -+ for(winNum=0; winNum= ETH_MAX_DECODE_WIN) -+ { -+ mvOsPrintf("mvEthWinSet: ERR. Invalid win num %d\n",winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlapps with current windows */ -+ if (MV_TRUE == ethWinOverlapDetect(port, winNum, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("mvEthWinSet: ERR. Window %d overlap\n", winNum); -+ return MV_ERROR; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvEthWinSet: Error setting Ethernet window %d to "\ -+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, -+ mvCtrlTargetNameGet(pAddrDecWin->target), -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ -+ decRegs.baseReg = MV_REG_READ(ETH_WIN_BASE_REG(port, winNum)); -+ decRegs.sizeReg = MV_REG_READ(ETH_WIN_SIZE_REG(port, winNum)); -+ -+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) -+ { -+ mvOsPrintf("mvEthWinSet:mvCtrlAddrDecToReg Failed\n"); -+ return MV_ERROR; -+ } -+ -+ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); -+ -+ /* set attributes */ -+ decRegs.baseReg &= ~ETH_WIN_ATTR_MASK; -+ decRegs.baseReg |= targetAttribs.attrib << ETH_WIN_ATTR_OFFS; -+ /* set target ID */ -+ decRegs.baseReg &= ~ETH_WIN_TARGET_MASK; -+ decRegs.baseReg |= targetAttribs.targetId << ETH_WIN_TARGET_OFFS; -+ -+ /* for the safe side we disable the window before writing the new -+ values */ -+ mvEthWinEnable(port, winNum, MV_FALSE); -+ MV_REG_WRITE(ETH_WIN_BASE_REG(port, winNum), decRegs.baseReg); -+ -+ /* Write to address decode Size Register */ -+ MV_REG_WRITE(ETH_WIN_SIZE_REG(port, winNum), decRegs.sizeReg); -+ -+ /* Enable address decode target window */ -+ if (pAddrDecWin->enable == MV_TRUE) -+ { -+ mvEthWinEnable(port, winNum, MV_TRUE); -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvETHWinGet - Get dma peripheral target address window. -+* -+* DESCRIPTION: -+* Get ETH peripheral target address window. -+* -+* INPUT: -+* winNum - ETH to target address decode window number. -+* -+* OUTPUT: -+* pAddrDecWin - ETH target window data structure. -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvEthWinGet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin) -+{ -+ MV_DEC_REGS decRegs; -+ MV_TARGET_ATTRIB targetAttrib; -+ -+ /* Parameter checking */ -+ if (winNum >= ETH_MAX_DECODE_WIN) -+ { -+ mvOsPrintf("mvEthWinGet: ERR. Invalid winNum %d\n", winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ decRegs.baseReg = MV_REG_READ(ETH_WIN_BASE_REG(port, winNum)); -+ decRegs.sizeReg = MV_REG_READ(ETH_WIN_SIZE_REG(port, winNum)); -+ -+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) -+ { -+ mvOsPrintf("mvAhbToMbusWinGet: mvCtrlRegToAddrDec Failed \n"); -+ return MV_ERROR; -+ } -+ -+ /* attrib and targetId */ -+ targetAttrib.attrib = -+ (decRegs.baseReg & ETH_WIN_ATTR_MASK) >> ETH_WIN_ATTR_OFFS; -+ targetAttrib.targetId = -+ (decRegs.baseReg & ETH_WIN_TARGET_MASK) >> ETH_WIN_TARGET_OFFS; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ /* Check if window is enabled */ -+ if (~(MV_REG_READ(ETH_BASE_ADDR_ENABLE_REG(port))) & (1 << winNum) ) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthWinEnable - Enable/disable a ETH to target address window -+* -+* DESCRIPTION: -+* This function enable/disable a ETH to target address window. -+* According to parameter 'enable' the routine will enable the -+* window, thus enabling ETH accesses (before enabling the window it is -+* tested for overlapping). Otherwise, the window will be disabled. -+* -+* INPUT: -+* winNum - ETH to target address decode window number. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_ERROR if decode window number was wrong or enabled window overlapps. -+* -+*******************************************************************************/ -+MV_STATUS mvEthWinEnable(int port, MV_U32 winNum,MV_BOOL enable) -+{ -+ MV_ETH_DEC_WIN addrDecWin; -+ -+ /* Parameter checking */ -+ if (winNum >= ETH_MAX_DECODE_WIN) -+ { -+ mvOsPrintf("mvEthTargetWinEnable:ERR. Invalid winNum%d\n",winNum); -+ return MV_ERROR; -+ } -+ -+ if (enable == MV_TRUE) -+ { /* First check for overlap with other enabled windows */ -+ /* Get current window */ -+ if (MV_OK != mvEthWinGet(port, winNum, &addrDecWin)) -+ { -+ mvOsPrintf("mvEthTargetWinEnable:ERR. targetWinGet fail\n"); -+ return MV_ERROR; -+ } -+ /* Check for overlapping */ -+ if (MV_FALSE == ethWinOverlapDetect(port, winNum, &(addrDecWin.addrWin))) -+ { -+ /* No Overlap. Enable address decode target window */ -+ MV_REG_BIT_RESET(ETH_BASE_ADDR_ENABLE_REG(port), (1 << winNum)); -+ } -+ else -+ { /* Overlap detected */ -+ mvOsPrintf("mvEthTargetWinEnable:ERR. Overlap detected\n"); -+ return MV_ERROR; -+ } -+ } -+ else -+ { /* Disable address decode target window */ -+ MV_REG_BIT_SET(ETH_BASE_ADDR_ENABLE_REG(port), (1 << winNum)); -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthWinTargetGet - Get Window number associated with target -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+* window number -+* -+*******************************************************************************/ -+MV_U32 mvEthWinTargetGet(int port, MV_TARGET target) -+{ -+ MV_ETH_DEC_WIN decWin; -+ MV_U32 winNum; -+ -+ /* Check parameters */ -+ if (target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetGet: target %d is Illigal\n", target); -+ return 0xffffffff; -+ } -+ -+ for (winNum=0; winNum= mvCtrlEthMaxPortGet()) -+ { -+ mvOsPrintf("mvEthProtWinSet:ERR. Invalid port number %d\n", portNo); -+ return MV_ERROR; -+ } -+ -+ if (winNum >= ETH_MAX_DECODE_WIN) -+ { -+ mvOsPrintf("mvEthProtWinSet:ERR. Invalid winNum%d\n",winNum); -+ return MV_ERROR; -+ } -+ -+ if((access == ACC_RESERVED) || (access >= MAX_ACC_RIGHTS)) -+ { -+ mvOsPrintf("mvEthProtWinSet:ERR. Inv access param %d\n", access); -+ return MV_ERROR; -+ } -+ /* Read current protection register */ -+ protReg = MV_REG_READ(ETH_ACCESS_PROTECT_REG(portNo)); -+ -+ /* Clear protection window field */ -+ protReg &= ~(ETH_PROT_WIN_MASK(winNum)); -+ -+ /* Set new protection field value */ -+ protReg |= (access << (ETH_PROT_WIN_OFFS(winNum))); -+ -+ /* Write protection register back */ -+ MV_REG_WRITE(ETH_ACCESS_PROTECT_REG(portNo), protReg); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* ethWinOverlapDetect - Detect ETH address windows overlapping -+* -+* DESCRIPTION: -+* An unpredicted behaviur is expected in case ETH address decode -+* windows overlapps. -+* This function detects ETH address decode windows overlapping of a -+* specified window. The function does not check the window itself for -+* overlapping. The function also skipps disabled address decode windows. -+* -+* INPUT: -+* winNum - address decode window number. -+* pAddrDecWin - An address decode window struct. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data -+* from registers. -+* -+*******************************************************************************/ -+static MV_STATUS ethWinOverlapDetect(int port, MV_U32 winNum, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 baseAddrEnableReg; -+ MV_U32 winNumIndex; -+ MV_ETH_DEC_WIN addrDecWin; -+ -+ /* Read base address enable register. Do not check disabled windows */ -+ baseAddrEnableReg = MV_REG_READ(ETH_BASE_ADDR_ENABLE_REG(port)); -+ -+ for (winNumIndex=0; winNumIndex= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexInit: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Enabled CPU access to PCI-Express */ -+ mvCpuIfEnablePex(pexIf, pexType); -+ -+ /* Start with bars */ -+ /* First disable all PEX bars*/ -+ for (bar = 0; bar < PEX_MAX_BARS; bar++) -+ { -+ if (PEX_INTER_REGS_BAR != bar) -+ { -+ if (MV_OK != mvPexBarEnable(pexIf, bar, MV_FALSE)) -+ { -+ mvOsPrintf("mvPexInit:mvPexBarEnable bar =%d failed \n",bar); -+ return MV_ERROR; -+ } -+ -+ } -+ -+ } -+ -+ /* and disable all PEX target windows */ -+ for (winNum = 0; winNum < PEX_MAX_TARGET_WIN - 2; winNum++) -+ { -+ if (MV_OK != mvPexTargetWinEnable(pexIf, winNum, MV_FALSE)) -+ { -+ mvOsPrintf("mvPexInit:mvPexTargetWinEnable winNum =%d failed \n", -+ winNum); -+ return MV_ERROR; -+ -+ } -+ } -+ -+ /* Now, go through all bars*/ -+ -+ -+ -+/******************************************************************************/ -+/* Internal registers bar */ -+/******************************************************************************/ -+ bar = PEX_INTER_REGS_BAR; -+ -+ /* we only open the bar , no need to open windows for this bar */ -+ -+ /* first get the CS attribute from the CPU Interface */ -+ if (MV_OK !=mvCpuIfTargetWinGet(INTER_REGS,&addrDecWin)) -+ { -+ mvOsPrintf("mvPexInit: ERR. mvCpuIfTargetWinGet failed target =%d\n",INTER_REGS); -+ return MV_ERROR; -+ } -+ -+ pexBar.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; -+ pexBar.addrWin.baseLow = addrDecWin.addrWin.baseLow; -+ pexBar.addrWin.size = addrDecWin.addrWin.size; -+ pexBar.enable = MV_TRUE; -+ -+ if (MV_OK != mvPexBarSet(pexIf, bar, &pexBar)) -+ { -+ mvOsPrintf("mvPexInit: ERR. mvPexBarSet %d failed\n", bar); -+ return MV_ERROR; -+ } -+ -+/******************************************************************************/ -+/* DRAM bar */ -+/******************************************************************************/ -+ -+ bar = PEX_DRAM_BAR; -+ -+ pexBar.addrWin.size = 0; -+ -+ for (target = SDRAM_CS0;target < MV_DRAM_MAX_CS; target++ ) -+ { -+ -+ status = mvCpuIfTargetWinGet(target,&addrDecWin); -+ -+ if((MV_NO_SUCH == status)&&(target != SDRAM_CS0)) -+ { -+ continue; -+ } -+ -+ /* first get attributes from CPU If */ -+ if (MV_OK != status) -+ { -+ mvOsPrintf("mvPexInit: ERR. mvCpuIfTargetWinGet failed target =%d\n",target); -+ return MV_ERROR; -+ } -+ if (addrDecWin.enable == MV_TRUE) -+ { -+ /* the base is the base of DRAM CS0 always */ -+ if (SDRAM_CS0 == target ) -+ { -+ pexBar.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; -+ pexBar.addrWin.baseLow = addrDecWin.addrWin.baseLow; -+ -+ } -+ -+ /* increment the bar size to be the sum of the size of all -+ DRAM chips selecs */ -+ pexBar.addrWin.size += addrDecWin.addrWin.size; -+ -+ /* set a Pex window for this target ! -+ DRAM CS always will have a Pex Window , and is not a -+ part of the priority table */ -+ pexWin.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; -+ pexWin.addrWin.baseLow = addrDecWin.addrWin.baseLow; -+ pexWin.addrWin.size = addrDecWin.addrWin.size; -+ -+ /* we disable the windows at first because we are not -+ sure that it is witihin bar boundries */ -+ pexWin.enable =MV_FALSE; -+ pexWin.target = target; -+ pexWin.targetBar = bar; -+ -+ if (MV_OK != mvPexTargetWinSet(pexIf,pexCurrWin++,&pexWin)) -+ { -+ mvOsPrintf("mvPexInit: ERR. mvPexTargetWinSet failed\n"); -+ return MV_ERROR; -+ } -+ } -+ } -+ -+ /* check if the size of the bar is illeggal */ -+ if (-1 == ctrlSizeToReg(pexBar.addrWin.size, PXBCR_BAR_SIZE_ALIGNMENT)) -+ { -+ /* try to get a good size */ -+ pexBar.addrWin.size = ctrlSizeRegRoundUp(pexBar.addrWin.size, -+ PXBCR_BAR_SIZE_ALIGNMENT); -+ } -+ -+ /* check if the size and base are valid */ -+ if (MV_TRUE == pexBarOverlapDetect(pexIf,bar,&pexBar.addrWin)) -+ { -+ mvOsPrintf("mvPexInit:Warning :Bar %d size is illigal\n",bar); -+ mvOsPrintf("it will be disabled\n"); -+ mvOsPrintf("please check Pex and CPU windows configuration\n"); -+ } -+ else -+ { -+ pexBar.enable = MV_TRUE; -+ -+ /* configure the bar */ -+ if (MV_OK != mvPexBarSet(pexIf, bar, &pexBar)) -+ { -+ mvOsPrintf("mvPexInit: ERR. mvPexBarSet %d failed\n", bar); -+ return MV_ERROR; -+ } -+ -+ /* after the bar was configured then we enable the Pex windows*/ -+ for (winNum = 0;winNum < pexCurrWin ;winNum++) -+ { -+ if (MV_OK != mvPexTargetWinEnable(pexIf, winNum, MV_TRUE)) -+ { -+ mvOsPrintf("mvPexInit: Can't enable window =%d\n",winNum); -+ return MV_ERROR; -+ } -+ -+ } -+ } -+ -+/******************************************************************************/ -+/* DEVICE bar */ -+/******************************************************************************/ -+ -+/* Open the Device BAR for non linux only */ -+#ifndef MV_DISABLE_PEX_DEVICE_BAR -+ -+ /* then device bar*/ -+ bar = PEX_DEVICE_BAR; -+ -+ /* save the starting window */ -+ pexStartWindow = pexCurrWin; -+ pexBar.addrWin.size = 0; -+ pexBar.addrWin.baseLow = 0xffffffff; -+ pexBar.addrWin.baseHigh = 0; -+ maxBase = 0; -+ -+ for (target = DEV_TO_TARGET(START_DEV_CS);target < DEV_TO_TARGET(MV_DEV_MAX_CS); target++ ) -+ { -+ status = mvCpuIfTargetWinGet(target,&addrDecWin); -+ -+ if (MV_NO_SUCH == status) -+ { -+ continue; -+ } -+ -+ if (MV_OK != status) -+ { -+ mvOsPrintf("mvPexInit: ERR. mvCpuIfTargetWinGet failed target =%d\n",target); -+ return MV_ERROR; -+ } -+ -+ if (addrDecWin.enable == MV_TRUE) -+ { -+ /* get the minimum base */ -+ if (addrDecWin.addrWin.baseLow < pexBar.addrWin.baseLow) -+ { -+ pexBar.addrWin.baseLow = addrDecWin.addrWin.baseLow; -+ } -+ -+ /* get the maximum base */ -+ if (addrDecWin.addrWin.baseLow > maxBase) -+ { -+ maxBase = addrDecWin.addrWin.baseLow; -+ sizeOfMaxBase = addrDecWin.addrWin.size; -+ } -+ -+ /* search in the priority table for this target */ -+ for (winIndex = 0; pexDevBarPrioTable[winIndex] != TBL_TERM; -+ winIndex++) -+ { -+ if (pexDevBarPrioTable[winIndex] != target) -+ { -+ continue; -+ } -+ else if (pexDevBarPrioTable[winIndex] == target) -+ { -+ /*found it */ -+ -+ /* if the index of this target in the prio table is valid -+ then we set the Pex window for this target, a valid index is -+ an index that is lower than the number of the windows that -+ was not configured yet */ -+ -+ /* we subtract 2 always because the default and expantion -+ rom windows are always configured */ -+ if ( pexCurrWin < PEX_MAX_TARGET_WIN - 2) -+ { -+ /* set a Pex window for this target ! */ -+ pexWin.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; -+ pexWin.addrWin.baseLow = addrDecWin.addrWin.baseLow; -+ pexWin.addrWin.size = addrDecWin.addrWin.size; -+ -+ /* we disable the windows at first because we are not -+ sure that it is witihin bar boundries */ -+ pexWin.enable = MV_FALSE; -+ pexWin.target = target; -+ pexWin.targetBar = bar; -+ -+ if (MV_OK != mvPexTargetWinSet(pexIf,pexCurrWin++, -+ &pexWin)) -+ { -+ mvOsPrintf("mvPexInit: ERR. Window Set failed\n"); -+ return MV_ERROR; -+ } -+ } -+ } -+ } -+ } -+ } -+ -+ pexBar.addrWin.size = maxBase - pexBar.addrWin.baseLow + sizeOfMaxBase; -+ pexBar.enable = MV_TRUE; -+ -+ /* check if the size of the bar is illegal */ -+ if (-1 == ctrlSizeToReg(pexBar.addrWin.size, PXBCR_BAR_SIZE_ALIGNMENT)) -+ { -+ /* try to get a good size */ -+ pexBar.addrWin.size = ctrlSizeRegRoundUp(pexBar.addrWin.size, -+ PXBCR_BAR_SIZE_ALIGNMENT); -+ } -+ -+ /* check if the size and base are valid */ -+ if (MV_TRUE == pexBarOverlapDetect(pexIf,bar,&pexBar.addrWin)) -+ { -+ mvOsPrintf("mvPexInit:Warning :Bar %d size is illigal\n",bar); -+ mvOsPrintf("it will be disabled\n"); -+ mvOsPrintf("please check Pex and CPU windows configuration\n"); -+ } -+ else -+ { -+ if (MV_OK != mvPexBarSet(pexIf, bar, &pexBar)) -+ { -+ mvOsPrintf("mvPexInit: ERR. mvPexBarSet %d failed\n", bar); -+ return MV_ERROR; -+ } -+ -+ /* now enable the windows */ -+ for (winNum = pexStartWindow; winNum < pexCurrWin ; winNum++) -+ { -+ if (MV_OK != mvPexTargetWinEnable(pexIf, winNum, MV_TRUE)) -+ { -+ mvOsPrintf("mvPexInit:mvPexTargetWinEnable winNum =%d failed \n", -+ winNum); -+ return MV_ERROR; -+ } -+ } -+ } -+ -+#endif -+ -+ return mvPexHalInit(pexIf, pexType); -+ -+} -+ -+/******************************************************************************* -+* mvPexTargetWinSet - Set PEX to peripheral target address window BAR -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_OK if PEX BAR target window was set correctly, -+* MV_BAD_PARAM on bad params -+* MV_ERROR otherwise -+* (e.g. address window overlapps with other active PEX target window). -+* -+*******************************************************************************/ -+MV_STATUS mvPexTargetWinSet(MV_U32 pexIf, MV_U32 winNum, -+ MV_PEX_DEC_WIN *pAddrDecWin) -+{ -+ -+ MV_DEC_REGS decRegs; -+ PEX_WIN_REG_INFO winRegInfo; -+ MV_TARGET_ATTRIB targetAttribs; -+ -+ /* Parameter checking */ -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexTargetWinSet: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ -+ if (winNum >= PEX_MAX_TARGET_WIN) -+ { -+ mvOsPrintf("mvPexTargetWinSet: ERR. Invalid PEX winNum %d\n", winNum); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ /* get the pex Window registers offsets */ -+ pexWinRegInfoGet(pexIf,winNum,&winRegInfo); -+ -+ -+ if (MV_TRUE == pAddrDecWin->enable) -+ { -+ -+ /* 2) Check if the requested window overlaps with current windows */ -+ if (MV_TRUE == pexWinOverlapDetect(pexIf,winNum, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("mvPexTargetWinSet: ERR. Target %d overlap\n", winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* 2) Check if the requested window overlaps with current windows */ -+ if (MV_FALSE == pexIsWinWithinBar(pexIf,&pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("mvPexTargetWinSet: Win %d should be in bar boundries\n", -+ winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ } -+ -+ -+ -+ /* read base register*/ -+ -+ if (winRegInfo.baseLowRegOffs) -+ { -+ decRegs.baseReg = MV_REG_READ(winRegInfo.baseLowRegOffs); -+ } -+ else -+ { -+ decRegs.baseReg = 0; -+ } -+ -+ if (winRegInfo.sizeRegOffs) -+ { -+ decRegs.sizeReg = MV_REG_READ(winRegInfo.sizeRegOffs); -+ } -+ else -+ { -+ decRegs.sizeReg =0; -+ } -+ -+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) -+ { -+ mvOsPrintf("mvPexTargetWinSet:mvCtrlAddrDecToReg Failed\n"); -+ return MV_ERROR; -+ } -+ -+ /* enable\Disable */ -+ if (MV_TRUE == pAddrDecWin->enable) -+ { -+ decRegs.sizeReg |= PXWCR_WIN_EN; -+ } -+ else -+ { -+ decRegs.sizeReg &= ~PXWCR_WIN_EN; -+ } -+ -+ -+ /* clear bit location */ -+ decRegs.sizeReg &= ~PXWCR_WIN_BAR_MAP_MASK; -+ -+ /* set bar Mapping */ -+ if (pAddrDecWin->targetBar == 1) -+ { -+ decRegs.sizeReg |= PXWCR_WIN_BAR_MAP_BAR1; -+ } -+ else if (pAddrDecWin->targetBar == 2) -+ { -+ decRegs.sizeReg |= PXWCR_WIN_BAR_MAP_BAR2; -+ } -+ -+ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); -+ -+ /* set attributes */ -+ decRegs.sizeReg &= ~PXWCR_ATTRIB_MASK; -+ decRegs.sizeReg |= targetAttribs.attrib << PXWCR_ATTRIB_OFFS; -+ /* set target ID */ -+ decRegs.sizeReg &= ~PXWCR_TARGET_MASK; -+ decRegs.sizeReg |= targetAttribs.targetId << PXWCR_TARGET_OFFS; -+ -+ -+ /* 3) Write to address decode Base Address Register */ -+ -+ if (winRegInfo.baseLowRegOffs) -+ { -+ MV_REG_WRITE(winRegInfo.baseLowRegOffs, decRegs.baseReg); -+ } -+ -+ /* write size reg */ -+ if (winRegInfo.sizeRegOffs) -+ { -+ if ((MV_PEX_WIN_DEFAULT == winNum)|| -+ (MV_PEX_WIN_EXP_ROM == winNum)) -+ { -+ /* clear size because there is no size field*/ -+ decRegs.sizeReg &= ~PXWCR_SIZE_MASK; -+ -+ /* clear enable because there is no enable field*/ -+ decRegs.sizeReg &= ~PXWCR_WIN_EN; -+ -+ } -+ -+ MV_REG_WRITE(winRegInfo.sizeRegOffs, decRegs.sizeReg); -+ } -+ -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvPexTargetWinGet - Get PEX to peripheral target address window -+* -+* DESCRIPTION: -+* Get the PEX to peripheral target address window BAR. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* bar - BAR to be accessed by slave. -+* -+* OUTPUT: -+* pAddrBarWin - PEX target window information data structure. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexTargetWinGet(MV_U32 pexIf, MV_U32 winNum, -+ MV_PEX_DEC_WIN *pAddrDecWin) -+{ -+ MV_TARGET_ATTRIB targetAttrib; -+ MV_DEC_REGS decRegs; -+ -+ PEX_WIN_REG_INFO winRegInfo; -+ -+ /* Parameter checking */ -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexTargetWinGet: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ -+ if (winNum >= PEX_MAX_TARGET_WIN) -+ { -+ mvOsPrintf("mvPexTargetWinGet: ERR. Invalid PEX winNum %d\n", winNum); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ /* get the pex Window registers offsets */ -+ pexWinRegInfoGet(pexIf,winNum,&winRegInfo); -+ -+ /* read base register*/ -+ if (winRegInfo.baseLowRegOffs) -+ { -+ decRegs.baseReg = MV_REG_READ(winRegInfo.baseLowRegOffs); -+ } -+ else -+ { -+ decRegs.baseReg = 0; -+ } -+ -+ /* read size reg */ -+ if (winRegInfo.sizeRegOffs) -+ { -+ decRegs.sizeReg = MV_REG_READ(winRegInfo.sizeRegOffs); -+ } -+ else -+ { -+ decRegs.sizeReg =0; -+ } -+ -+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) -+ { -+ mvOsPrintf("mvPexTargetWinGet: mvCtrlRegToAddrDec Failed \n"); -+ return MV_ERROR; -+ -+ } -+ -+ if (decRegs.sizeReg & PXWCR_WIN_EN) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ -+ } -+ -+ -+ #if 0 -+ if (-1 == pAddrDecWin->addrWin.size) -+ { -+ return MV_ERROR; -+ } -+ #endif -+ -+ -+ /* get target bar */ -+ if ((decRegs.sizeReg & PXWCR_WIN_BAR_MAP_MASK) == PXWCR_WIN_BAR_MAP_BAR1 ) -+ { -+ pAddrDecWin->targetBar = 1; -+ } -+ else if ((decRegs.sizeReg & PXWCR_WIN_BAR_MAP_MASK) == -+ PXWCR_WIN_BAR_MAP_BAR2 ) -+ { -+ pAddrDecWin->targetBar = 2; -+ } -+ -+ /* attrib and targetId */ -+ pAddrDecWin->attrib = (decRegs.sizeReg & PXWCR_ATTRIB_MASK) >> -+ PXWCR_ATTRIB_OFFS; -+ pAddrDecWin->targetId = (decRegs.sizeReg & PXWCR_TARGET_MASK) >> -+ PXWCR_TARGET_OFFS; -+ -+ targetAttrib.attrib = pAddrDecWin->attrib; -+ targetAttrib.targetId = pAddrDecWin->targetId; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ return MV_OK; -+ -+} -+ -+ -+/******************************************************************************* -+* mvPexTargetWinEnable - Enable/disable a PEX BAR window -+* -+* DESCRIPTION: -+* This function enable/disable a PEX BAR window. -+* if parameter 'enable' == MV_TRUE the routine will enable the -+* window, thus enabling PEX accesses for that BAR (before enabling the -+* window it is tested for overlapping). Otherwise, the window will -+* be disabled. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* bar - BAR to be accessed by slave. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexTargetWinEnable(MV_U32 pexIf,MV_U32 winNum, MV_BOOL enable) -+{ -+ PEX_WIN_REG_INFO winRegInfo; -+ MV_PEX_DEC_WIN addrDecWin; -+ -+ /* Parameter checking */ -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexTargetWinEnable: ERR. Invalid PEX If %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ -+ if (winNum >= PEX_MAX_TARGET_WIN) -+ { -+ mvOsPrintf("mvPexTargetWinEnable ERR. Invalid PEX winNum %d\n", winNum); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ -+ /* get the pex Window registers offsets */ -+ pexWinRegInfoGet(pexIf,winNum,&winRegInfo); -+ -+ -+ /* if the address windows is disabled , we only disable the appropriare -+ pex window and ignore other settings */ -+ -+ if (MV_FALSE == enable) -+ { -+ -+ /* this is not relevant to default and expantion rom -+ windows */ -+ if (winRegInfo.sizeRegOffs) -+ { -+ if ((MV_PEX_WIN_DEFAULT != winNum)&& -+ (MV_PEX_WIN_EXP_ROM != winNum)) -+ { -+ MV_REG_BIT_RESET(winRegInfo.sizeRegOffs, PXWCR_WIN_EN); -+ } -+ } -+ -+ } -+ else -+ { -+ if (MV_OK != mvPexTargetWinGet(pexIf,winNum, &addrDecWin)) -+ { -+ mvOsPrintf("mvPexTargetWinEnable: mvPexTargetWinGet Failed\n"); -+ return MV_ERROR; -+ } -+ -+ /* Check if the requested window overlaps with current windows */ -+ if (MV_TRUE == pexWinOverlapDetect(pexIf,winNum, &addrDecWin.addrWin)) -+ { -+ mvOsPrintf("mvPexTargetWinEnable: ERR. Target %d overlap\n", winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ if (MV_FALSE == pexIsWinWithinBar(pexIf,&addrDecWin.addrWin)) -+ { -+ mvOsPrintf("mvPexTargetWinEnable: Win %d should be in bar boundries\n", -+ winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ -+ /* this is not relevant to default and expantion rom -+ windows */ -+ if (winRegInfo.sizeRegOffs) -+ { -+ if ((MV_PEX_WIN_DEFAULT != winNum)&& -+ (MV_PEX_WIN_EXP_ROM != winNum)) -+ { -+ MV_REG_BIT_SET(winRegInfo.sizeRegOffs, PXWCR_WIN_EN); -+ } -+ } -+ -+ -+ } -+ -+ return MV_OK; -+ -+} -+ -+ -+ -+/******************************************************************************* -+* mvPexTargetWinRemap - Set PEX to target address window remap. -+* -+* DESCRIPTION: -+* The PEX interface supports remap of the BAR original address window. -+* For each BAR it is possible to define a remap address. For example -+* an address 0x12345678 that hits BAR 0x10 (SDRAM CS[0]) will be modified -+* according to remap register but will also be targeted to the -+* SDRAM CS[0]. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* bar - Peripheral target enumerator accessed by slave. -+* pAddrWin - Address window to be checked. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexTargetWinRemap(MV_U32 pexIf, MV_U32 winNum, -+ MV_PEX_REMAP_WIN *pAddrWin) -+{ -+ -+ PEX_WIN_REG_INFO winRegInfo; -+ -+ /* Parameter checking */ -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX interface num %d\n", -+ pexIf); -+ return MV_BAD_PARAM; -+ } -+ if (MV_PEX_WIN_DEFAULT == winNum) -+ { -+ mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX win num %d\n", -+ winNum); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ if (MV_IS_NOT_ALIGN(pAddrWin->addrWin.baseLow, PXWRR_REMAP_ALIGNMENT)) -+ { -+ mvOsPrintf("mvPexTargetWinRemap: Error remap PEX interface %d win %d."\ -+ "\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ pexIf, -+ winNum, -+ pAddrWin->addrWin.baseLow, -+ pAddrWin->addrWin.size); -+ -+ return MV_ERROR; -+ } -+ -+ pexWinRegInfoGet(pexIf, winNum, &winRegInfo); -+ -+ /* Set remap low register value */ -+ MV_REG_WRITE(winRegInfo.remapLowRegOffs, pAddrWin->addrWin.baseLow); -+ -+ /* Skip base high settings if the BAR has only base low (32-bit) */ -+ if (0 != winRegInfo.remapHighRegOffs) -+ { -+ MV_REG_WRITE(winRegInfo.remapHighRegOffs, pAddrWin->addrWin.baseHigh); -+ } -+ -+ -+ if (pAddrWin->enable == MV_TRUE) -+ { -+ MV_REG_BIT_SET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvPexTargetWinRemapEnable - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+ -+MV_STATUS mvPexTargetWinRemapEnable(MV_U32 pexIf, MV_U32 winNum, -+ MV_BOOL enable) -+{ -+ PEX_WIN_REG_INFO winRegInfo; -+ -+ /* Parameter checking */ -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX interface num %d\n", -+ pexIf); -+ return MV_BAD_PARAM; -+ } -+ if (MV_PEX_WIN_DEFAULT == winNum) -+ { -+ mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX win num %d\n", -+ winNum); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ -+ pexWinRegInfoGet(pexIf, winNum, &winRegInfo); -+ -+ if (enable == MV_TRUE) -+ { -+ MV_REG_BIT_SET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); -+ } -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvPexBarSet - Set PEX bar address and size -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexBarSet(MV_U32 pexIf, -+ MV_U32 barNum, -+ MV_PEX_BAR *pAddrWin) -+{ -+ MV_U32 regBaseLow; -+ MV_U32 regSize,sizeToReg; -+ -+ -+ /* check parameters */ -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexBarSet: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ -+ if(barNum >= PEX_MAX_BARS) -+ { -+ mvOsPrintf("mvPexBarSet: ERR. Invalid bar number %d\n", barNum); -+ return MV_BAD_PARAM; -+ } -+ -+ -+ if (pAddrWin->addrWin.size == 0) -+ { -+ mvOsPrintf("mvPexBarSet: Size zero is Illigal\n" ); -+ return MV_BAD_PARAM; -+ } -+ -+ -+ /* Check if the window complies with PEX spec */ -+ if (MV_TRUE != pexBarIsValid(pAddrWin->addrWin.baseLow, -+ pAddrWin->addrWin.size)) -+ { -+ mvOsPrintf("mvPexBarSet: ERR. Target %d window invalid\n", barNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* 2) Check if the requested bar overlaps with current bars */ -+ if (MV_TRUE == pexBarOverlapDetect(pexIf,barNum, &pAddrWin->addrWin)) -+ { -+ mvOsPrintf("mvPexBarSet: ERR. Target %d overlap\n", barNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Get size register value according to window size */ -+ sizeToReg = ctrlSizeToReg(pAddrWin->addrWin.size, PXBCR_BAR_SIZE_ALIGNMENT); -+ -+ /* Read bar size */ -+ if (PEX_INTER_REGS_BAR != barNum) /* internal registers have no size */ -+ { -+ regSize = MV_REG_READ(PEX_BAR_CTRL_REG(pexIf,barNum)); -+ -+ /* Size parameter validity check. */ -+ if (-1 == sizeToReg) -+ { -+ mvOsPrintf("mvPexBarSet: ERR. Target BAR %d size invalid.\n",barNum); -+ return MV_BAD_PARAM; -+ } -+ -+ regSize &= ~PXBCR_BAR_SIZE_MASK; -+ regSize |= (sizeToReg << PXBCR_BAR_SIZE_OFFS) ; -+ -+ MV_REG_WRITE(PEX_BAR_CTRL_REG(pexIf,barNum),regSize); -+ -+ } -+ -+ /* set size */ -+ -+ -+ -+ /* Read base address low */ -+ regBaseLow = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, -+ PEX_MV_BAR_BASE(barNum))); -+ -+ /* clear current base */ -+ if (PEX_INTER_REGS_BAR == barNum) -+ { -+ regBaseLow &= ~PXBIR_BASE_MASK; -+ regBaseLow |= (pAddrWin->addrWin.baseLow & PXBIR_BASE_MASK); -+ } -+ else -+ { -+ regBaseLow &= ~PXBR_BASE_MASK; -+ regBaseLow |= (pAddrWin->addrWin.baseLow & PXBR_BASE_MASK); -+ } -+ -+ /* if we had a previous value that contain the bar type (MeM\IO), we want to -+ restore it */ -+ regBaseLow |= PEX_BAR_DEFAULT_ATTRIB; -+ -+ -+ -+ /* write base low */ -+ MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE(barNum)), -+ regBaseLow); -+ -+ if (pAddrWin->addrWin.baseHigh != 0) -+ { -+ /* Read base address high */ -+ MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE_HIGH(barNum)), -+ pAddrWin->addrWin.baseHigh); -+ -+ } -+ -+ /* lastly enable the Bar */ -+ if (pAddrWin->enable == MV_TRUE) -+ { -+ if (PEX_INTER_REGS_BAR != barNum) /* internal registers -+ are enabled always */ -+ { -+ MV_REG_BIT_SET(PEX_BAR_CTRL_REG(pexIf,barNum),PXBCR_BAR_EN); -+ } -+ } -+ else if (MV_FALSE == pAddrWin->enable) -+ { -+ if (PEX_INTER_REGS_BAR != barNum) /* internal registers -+ are enabled always */ -+ { -+ MV_REG_BIT_RESET(PEX_BAR_CTRL_REG(pexIf,barNum),PXBCR_BAR_EN); -+ } -+ -+ } -+ -+ -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPexBarGet - Get PEX bar address and size -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+ -+MV_STATUS mvPexBarGet(MV_U32 pexIf, -+ MV_U32 barNum, -+ MV_PEX_BAR *pAddrWin) -+{ -+ /* check parameters */ -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexBarGet: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ -+ if(barNum >= PEX_MAX_BARS) -+ { -+ mvOsPrintf("mvPexBarGet: ERR. Invalid bar number %d\n", barNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* read base low */ -+ pAddrWin->addrWin.baseLow = -+ MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE(barNum))); -+ -+ -+ if (PEX_INTER_REGS_BAR == barNum) -+ { -+ pAddrWin->addrWin.baseLow &= PXBIR_BASE_MASK; -+ } -+ else -+ { -+ pAddrWin->addrWin.baseLow &= PXBR_BASE_MASK; -+ } -+ -+ -+ /* read base high */ -+ pAddrWin->addrWin.baseHigh = -+ MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE_HIGH(barNum))); -+ -+ -+ /* Read bar size */ -+ if (PEX_INTER_REGS_BAR != barNum) /* internal registers have no size */ -+ { -+ pAddrWin->addrWin.size = MV_REG_READ(PEX_BAR_CTRL_REG(pexIf,barNum)); -+ -+ /* check if enable or not */ -+ if (pAddrWin->addrWin.size & PXBCR_BAR_EN) -+ { -+ pAddrWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrWin->enable = MV_FALSE; -+ } -+ -+ /* now get the size */ -+ pAddrWin->addrWin.size &= PXBCR_BAR_SIZE_MASK; -+ pAddrWin->addrWin.size >>= PXBCR_BAR_SIZE_OFFS; -+ -+ pAddrWin->addrWin.size = ctrlRegToSize(pAddrWin->addrWin.size, -+ PXBCR_BAR_SIZE_ALIGNMENT); -+ -+ } -+ else /* PEX_INTER_REGS_BAR */ -+ { -+ pAddrWin->addrWin.size = INTER_REGS_SIZE; -+ pAddrWin->enable = MV_TRUE; -+ } -+ -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvPexBarEnable - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+ -+ -+MV_STATUS mvPexBarEnable(MV_U32 pexIf, MV_U32 barNum, MV_BOOL enable) -+{ -+ -+ MV_PEX_BAR pexBar; -+ -+ /* check parameters */ -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexBarEnable: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ -+ -+ if(barNum >= PEX_MAX_BARS) -+ { -+ mvOsPrintf("mvPexBarEnable: ERR. Invalid bar number %d\n", barNum); -+ return MV_BAD_PARAM; -+ } -+ -+ if (PEX_INTER_REGS_BAR == barNum) -+ { -+ if (MV_TRUE == enable) -+ { -+ return MV_OK; -+ } -+ else -+ { -+ return MV_ERROR; -+ } -+ } -+ -+ -+ if (MV_FALSE == enable) -+ { -+ /* disable bar and quit */ -+ MV_REG_BIT_RESET(PEX_BAR_CTRL_REG(pexIf,barNum),PXBCR_BAR_EN); -+ return MV_OK; -+ } -+ -+ /* else */ -+ -+ if (mvPexBarGet(pexIf,barNum,&pexBar) != MV_OK) -+ { -+ mvOsPrintf("mvPexBarEnable: mvPexBarGet Failed\n"); -+ return MV_ERROR; -+ -+ } -+ -+ if (MV_TRUE == pexBar.enable) -+ { -+ /* it is already enabled !!! */ -+ return MV_OK; -+ } -+ -+ /* else enable the bar*/ -+ -+ pexBar.enable = MV_TRUE; -+ -+ if (mvPexBarSet(pexIf,barNum,&pexBar) != MV_OK) -+ { -+ mvOsPrintf("mvPexBarEnable: mvPexBarSet Failed\n"); -+ return MV_ERROR; -+ -+ } -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* pexWinOverlapDetect - Detect address windows overlapping -+* -+* DESCRIPTION: -+* This function detects address window overlapping of a given address -+* window in PEX BARs. -+* -+* INPUT: -+* pAddrWin - Address window to be checked. -+* bar - BAR to be accessed by slave. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+static MV_BOOL pexWinOverlapDetect(MV_U32 pexIf, -+ MV_U32 winNum, -+ MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 win; -+ MV_PEX_DEC_WIN addrDecWin; -+ -+ -+ for(win = 0; win < PEX_MAX_TARGET_WIN -2 ; win++) -+ { -+ /* don't check our target or illegal targets */ -+ if (winNum == win) -+ { -+ continue; -+ } -+ -+ /* Get window parameters */ -+ if (MV_OK != mvPexTargetWinGet(pexIf, win, &addrDecWin)) -+ { -+ mvOsPrintf("pexWinOverlapDetect: ERR. TargetWinGet failed win=%x\n", -+ win); -+ return MV_ERROR; -+ } -+ -+ /* Do not check disabled windows */ -+ if (MV_FALSE == addrDecWin.enable) -+ { -+ continue; -+ } -+ -+ -+ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) -+ { -+ mvOsPrintf("pexWinOverlapDetect: winNum %d overlap current %d\n", -+ winNum, win); -+ return MV_TRUE; -+ } -+ } -+ -+ return MV_FALSE; -+} -+ -+/******************************************************************************* -+* pexIsWinWithinBar - Detect if address is within PEX bar boundries -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+static MV_BOOL pexIsWinWithinBar(MV_U32 pexIf, -+ MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 bar; -+ MV_PEX_BAR addrDecWin; -+ -+ for(bar = 0; bar < PEX_MAX_BARS; bar++) -+ { -+ -+ /* Get window parameters */ -+ if (MV_OK != mvPexBarGet(pexIf, bar, &addrDecWin)) -+ { -+ mvOsPrintf("pexIsWinWithinBar: ERR. mvPexBarGet failed\n"); -+ return MV_ERROR; -+ } -+ -+ /* Do not check disabled bars */ -+ if (MV_FALSE == addrDecWin.enable) -+ { -+ continue; -+ } -+ -+ -+ if(MV_TRUE == ctrlWinWithinWinTest(pAddrWin, &addrDecWin.addrWin)) -+ { -+ return MV_TRUE; -+ } -+ } -+ -+ return MV_FALSE; -+ -+} -+ -+/******************************************************************************* -+* pexBarOverlapDetect - Detect address windows overlapping -+* -+* DESCRIPTION: -+* This function detects address window overlapping of a given address -+* window in PEX BARs. -+* -+* INPUT: -+* pAddrWin - Address window to be checked. -+* bar - BAR to be accessed by slave. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+static MV_BOOL pexBarOverlapDetect(MV_U32 pexIf, -+ MV_U32 barNum, -+ MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 bar; -+ MV_PEX_BAR barDecWin; -+ -+ -+ for(bar = 0; bar < PEX_MAX_BARS; bar++) -+ { -+ /* don't check our target or illegal targets */ -+ if (barNum == bar) -+ { -+ continue; -+ } -+ -+ /* Get window parameters */ -+ if (MV_OK != mvPexBarGet(pexIf, bar, &barDecWin)) -+ { -+ mvOsPrintf("pexBarOverlapDetect: ERR. TargetWinGet failed\n"); -+ return MV_ERROR; -+ } -+ -+ /* don'nt check disabled bars */ -+ if (barDecWin.enable == MV_FALSE) -+ { -+ continue; -+ } -+ -+ -+ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &barDecWin.addrWin)) -+ { -+ mvOsPrintf("pexBarOverlapDetect: winNum %d overlap current %d\n", -+ barNum, bar); -+ return MV_TRUE; -+ } -+ } -+ -+ return MV_FALSE; -+} -+ -+/******************************************************************************* -+* pexBarIsValid - Check if the given address window is valid -+* -+* DESCRIPTION: -+* PEX spec restrict BAR base to be aligned to BAR size. -+* This function checks if the given address window is valid. -+* -+* INPUT: -+* baseLow - 32bit low base address. -+* size - Window size. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the address window is valid, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+static MV_STATUS pexBarIsValid(MV_U32 baseLow, MV_U32 size) -+{ -+ -+ /* PCI spec restrict BAR base to be aligned to BAR size */ -+ if(MV_IS_NOT_ALIGN(baseLow, size)) -+ { -+ return MV_ERROR; -+ } -+ else -+ { -+ return MV_TRUE; -+ } -+ -+ return MV_TRUE; -+} -+ -+/******************************************************************************* -+* pexBarRegInfoGet - Get BAR register information -+* -+* DESCRIPTION: -+* PEX BARs registers offsets are inconsecutive. -+* This function gets a PEX BAR register information like register offsets -+* and function location of the BAR. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* bar - The PEX BAR in question. -+* -+* OUTPUT: -+* pBarRegInfo - BAR register info struct. -+* -+* RETURN: -+* MV_BAD_PARAM when bad parameters ,MV_ERROR on error ,othewise MV_OK -+* -+*******************************************************************************/ -+static MV_STATUS pexWinRegInfoGet(MV_U32 pexIf, -+ MV_U32 winNum, -+ PEX_WIN_REG_INFO *pWinRegInfo) -+{ -+ -+ if ((winNum >= 0)&&(winNum <=3)) -+ { -+ pWinRegInfo->baseLowRegOffs = PEX_WIN0_3_BASE_REG(pexIf,winNum); -+ pWinRegInfo->baseHighRegOffs = 0; -+ pWinRegInfo->sizeRegOffs = PEX_WIN0_3_CTRL_REG(pexIf,winNum); -+ pWinRegInfo->remapLowRegOffs = PEX_WIN0_3_REMAP_REG(pexIf,winNum); -+ pWinRegInfo->remapHighRegOffs = 0; -+ } -+ else if ((winNum >= 4)&&(winNum <=5)) -+ { -+ pWinRegInfo->baseLowRegOffs = PEX_WIN4_5_BASE_REG(pexIf,winNum); -+ pWinRegInfo->baseHighRegOffs = 0; -+ pWinRegInfo->sizeRegOffs = PEX_WIN4_5_CTRL_REG(pexIf,winNum); -+ pWinRegInfo->remapLowRegOffs = PEX_WIN4_5_REMAP_REG(pexIf,winNum); -+ pWinRegInfo->remapHighRegOffs = PEX_WIN4_5_REMAP_HIGH_REG(pexIf,winNum); -+ -+ } -+ else if (MV_PEX_WIN_DEFAULT == winNum) -+ { -+ pWinRegInfo->baseLowRegOffs = 0; -+ pWinRegInfo->baseHighRegOffs = 0; -+ pWinRegInfo->sizeRegOffs = PEX_WIN_DEFAULT_CTRL_REG(pexIf); -+ pWinRegInfo->remapLowRegOffs = 0; -+ pWinRegInfo->remapHighRegOffs = 0; -+ } -+ else if (MV_PEX_WIN_EXP_ROM == winNum) -+ { -+ pWinRegInfo->baseLowRegOffs = 0; -+ pWinRegInfo->baseHighRegOffs = 0; -+ pWinRegInfo->sizeRegOffs = PEX_WIN_EXP_ROM_CTRL_REG(pexIf); -+ pWinRegInfo->remapLowRegOffs = PEX_WIN_EXP_ROM_REMAP_REG(pexIf); -+ pWinRegInfo->remapHighRegOffs = 0; -+ -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* pexBarNameGet - Get the string name of PEX BAR. -+* -+* DESCRIPTION: -+* This function get the string name of PEX BAR. -+* -+* INPUT: -+* bar - PEX bar number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* pointer to the string name of PEX BAR. -+* -+*******************************************************************************/ -+const MV_8* pexBarNameGet( MV_U32 bar ) -+{ -+ switch( bar ) -+ { -+ case PEX_INTER_REGS_BAR: -+ return "Internal Regs Bar0...."; -+ case PEX_DRAM_BAR: -+ return "DRAM Bar1............."; -+ case PEX_DEVICE_BAR: -+ return "Devices Bar2.........."; -+ default: -+ return "Bar unknown"; -+ } -+} -+/******************************************************************************* -+* mvPexAddrDecShow - Print the PEX address decode map (BARs and windows). -+* -+* DESCRIPTION: -+* This function print the PEX address decode map (BARs and windows). -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvPexAddrDecShow(MV_VOID) -+{ -+ MV_PEX_BAR pexBar; -+ MV_PEX_DEC_WIN win; -+ MV_U32 pexIf; -+ MV_U32 bar,winNum; -+ -+ for( pexIf = 0; pexIf < mvCtrlPexMaxIfGet(); pexIf++ ) -+ { -+ if (MV_FALSE == mvCtrlPwrClckGet(PEX_UNIT_ID, pexIf)) continue; -+ mvOsOutput( "\n" ); -+ mvOsOutput( "PEX%d:\n", pexIf ); -+ mvOsOutput( "-----\n" ); -+ -+ mvOsOutput( "\nPex Bars \n\n"); -+ -+ for( bar = 0; bar < PEX_MAX_BARS; bar++ ) -+ { -+ memset( &pexBar, 0, sizeof(MV_PEX_BAR) ); -+ -+ mvOsOutput( "%s ", pexBarNameGet(bar) ); -+ -+ if( mvPexBarGet( pexIf, bar, &pexBar ) == MV_OK ) -+ { -+ if( pexBar.enable ) -+ { -+ mvOsOutput( "base %08x, ", pexBar.addrWin.baseLow ); -+ mvSizePrint( pexBar.addrWin.size ); -+ mvOsOutput( "\n" ); -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ } -+ } -+ mvOsOutput( "\nPex Decode Windows\n\n"); -+ -+ for( winNum = 0; winNum < PEX_MAX_TARGET_WIN - 2; winNum++) -+ { -+ memset( &win, 0,sizeof(MV_PEX_DEC_WIN) ); -+ -+ mvOsOutput( "win%d - ", winNum ); -+ -+ if ( mvPexTargetWinGet(pexIf,winNum,&win) == MV_OK) -+ { -+ if (win.enable) -+ { -+ mvOsOutput( "%s base %08x, ", -+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); -+ mvOsOutput( "...." ); -+ mvSizePrint( win.addrWin.size ); -+ -+ mvOsOutput( "\n" ); -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ -+ -+ } -+ } -+ -+ memset( &win, 0,sizeof(MV_PEX_DEC_WIN) ); -+ -+ mvOsOutput( "default win - " ); -+ -+ if ( mvPexTargetWinGet(pexIf, MV_PEX_WIN_DEFAULT, &win) == MV_OK) -+ { -+ mvOsOutput( "%s ", -+ mvCtrlTargetNameGet(win.target) ); -+ mvOsOutput( "\n" ); -+ } -+ memset( &win, 0,sizeof(MV_PEX_DEC_WIN) ); -+ -+ mvOsOutput( "Expansion ROM - " ); -+ -+ if ( mvPexTargetWinGet(pexIf, MV_PEX_WIN_EXP_ROM, &win) == MV_OK) -+ { -+ mvOsOutput( "%s ", -+ mvCtrlTargetNameGet(win.target) ); -+ mvOsOutput( "\n" ); -+ } -+ -+ } -+} -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,348 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCSysPEXH -+#define __INCSysPEXH -+ -+#include "mvCommon.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+ -+/* 4KB granularity */ -+#define MINIMUM_WINDOW_SIZE 0x1000 -+#define MINIMUM_BAR_SIZE 0x1000 -+#define MINIMUM_BAR_SIZE_MASK 0xFFFFF000 -+#define BAR_SIZE_OFFS 12 -+#define BAR_SIZE_MASK (0xFFFFF << BAR_SIZE_OFFS) -+ -+ -+ -+#define MV_PEX_WIN_DEFAULT 6 -+#define MV_PEX_WIN_EXP_ROM 7 -+#define PEX_MAX_TARGET_WIN 8 -+ -+ -+#define PEX_MAX_BARS 3 -+#define PEX_INTER_REGS_BAR 0 -+#define PEX_DRAM_BAR 1 -+#define PEX_DEVICE_BAR 2 -+ -+/*************************************/ -+/* PCI Express BAR Control Registers */ -+/*************************************/ -+#define PEX_BAR_CTRL_REG(pexIf,bar) (0x41804 + (bar-1)*4- (pexIf)*0x10000) -+#define PEX_EXP_ROM_BAR_CTRL_REG(pexIf) (0x4180C - (pexIf)*0x10000) -+ -+ -+/* PCI Express BAR Control Register */ -+/* PEX_BAR_CTRL_REG (PXBCR) */ -+ -+#define PXBCR_BAR_EN BIT0 -+#define PXBCR_BAR_SIZE_OFFS 16 -+#define PXBCR_BAR_SIZE_MASK (0xffff << PXBCR_BAR_SIZE_OFFS) -+#define PXBCR_BAR_SIZE_ALIGNMENT 0x10000 -+ -+ -+ -+/* PCI Express Expansion ROM BAR Control Register */ -+/* PEX_EXP_ROM_BAR_CTRL_REG (PXERBCR) */ -+ -+#define PXERBCR_EXPROM_EN BIT0 -+#define PXERBCR_EXPROMSZ_OFFS 19 -+#define PXERBCR_EXPROMSZ_MASK (0xf << PXERBCR_EXPROMSZ_OFFS) -+#define PXERBCR_EXPROMSZ_512KB (0x0 << PXERBCR_EXPROMSZ_OFFS) -+#define PXERBCR_EXPROMSZ_1024KB (0x1 << PXERBCR_EXPROMSZ_OFFS) -+#define PXERBCR_EXPROMSZ_2048KB (0x3 << PXERBCR_EXPROMSZ_OFFS) -+#define PXERBCR_EXPROMSZ_4096KB (0x7 << PXERBCR_EXPROMSZ_OFFS) -+ -+/************************************************/ -+/* PCI Express Address Window Control Registers */ -+/************************************************/ -+#define PEX_WIN0_3_CTRL_REG(pexIf,winNum) \ -+ (0x41820 + (winNum) * 0x10 - (pexIf) * 0x10000) -+#define PEX_WIN0_3_BASE_REG(pexIf,winNum) \ -+ (0x41824 + (winNum) * 0x10 - (pexIf) * 0x10000) -+#define PEX_WIN0_3_REMAP_REG(pexIf,winNum) \ -+ (0x4182C + (winNum) * 0x10 - (pexIf) * 0x10000) -+#define PEX_WIN4_5_CTRL_REG(pexIf,winNum) \ -+ (0x41860 + (winNum - 4) * 0x20 - (pexIf) * 0x10000) -+#define PEX_WIN4_5_BASE_REG(pexIf,winNum) \ -+ (0x41864 + (winNum - 4) * 0x20 - (pexIf) * 0x10000) -+#define PEX_WIN4_5_REMAP_REG(pexIf,winNum) \ -+ (0x4186C + (winNum - 4) * 0x20 - (pexIf) * 0x10000) -+#define PEX_WIN4_5_REMAP_HIGH_REG(pexIf,winNum) \ -+ (0x41870 + (winNum - 4) * 0x20 - (pexIf) * 0x10000) -+ -+#define PEX_WIN_DEFAULT_CTRL_REG(pexIf) (0x418B0 - (pexIf) * 0x10000) -+#define PEX_WIN_EXP_ROM_CTRL_REG(pexIf) (0x418C0 - (pexIf) * 0x10000) -+#define PEX_WIN_EXP_ROM_REMAP_REG(pexIf) (0x418C4 - (pexIf) * 0x10000) -+ -+/* PCI Express Window Control Register */ -+/* PEX_WIN_CTRL_REG (PXWCR) */ -+ -+#define PXWCR_WIN_EN BIT0 /* Window Enable.*/ -+ -+#define PXWCR_WIN_BAR_MAP_OFFS 1 /* Mapping to BAR.*/ -+#define PXWCR_WIN_BAR_MAP_MASK BIT1 -+#define PXWCR_WIN_BAR_MAP_BAR1 (0 << PXWCR_WIN_BAR_MAP_OFFS) -+#define PXWCR_WIN_BAR_MAP_BAR2 (1 << PXWCR_WIN_BAR_MAP_OFFS) -+ -+#define PXWCR_TARGET_OFFS 4 /*Unit ID */ -+#define PXWCR_TARGET_MASK (0xf << PXWCR_TARGET_OFFS) -+ -+#define PXWCR_ATTRIB_OFFS 8 /* target attributes */ -+#define PXWCR_ATTRIB_MASK (0xff << PXWCR_ATTRIB_OFFS) -+ -+#define PXWCR_SIZE_OFFS 16 /* size */ -+#define PXWCR_SIZE_MASK (0xffff << PXWCR_SIZE_OFFS) -+#define PXWCR_SIZE_ALIGNMENT 0x10000 -+ -+/* PCI Express Window Base Register */ -+/* PEX_WIN_BASE_REG (PXWBR)*/ -+ -+#define PXWBR_BASE_OFFS 16 /* address[31:16] */ -+#define PXWBR_BASE_MASK (0xffff << PXWBR_BASE_OFFS) -+#define PXWBR_BASE_ALIGNMENT 0x10000 -+ -+/* PCI Express Window Remap Register */ -+/* PEX_WIN_REMAP_REG (PXWRR)*/ -+ -+#define PXWRR_REMAP_EN BIT0 -+#define PXWRR_REMAP_OFFS 16 -+#define PXWRR_REMAP_MASK (0xffff << PXWRR_REMAP_OFFS) -+#define PXWRR_REMAP_ALIGNMENT 0x10000 -+ -+/* PCI Express Window Remap (High) Register */ -+/* PEX_WIN_REMAP_HIGH_REG (PXWRHR)*/ -+ -+#define PXWRHR_REMAP_HIGH_OFFS 0 -+#define PXWRHR_REMAP_HIGH_MASK (0xffffffff << PXWRHR_REMAP_HIGH_OFFS) -+ -+/* PCI Express Default Window Control Register */ -+/* PEX_WIN_DEFAULT_CTRL_REG (PXWDCR) */ -+ -+#define PXWDCR_TARGET_OFFS 4 /*Unit ID */ -+#define PXWDCR_TARGET_MASK (0xf << PXWDCR_TARGET_OFFS) -+#define PXWDCR_ATTRIB_OFFS 8 /* target attributes */ -+#define PXWDCR_ATTRIB_MASK (0xff << PXWDCR_ATTRIB_OFFS) -+ -+/* PCI Express Expansion ROM Window Control Register */ -+/* PEX_WIN_EXP_ROM_CTRL_REG (PXWERCR)*/ -+ -+#define PXWERCR_TARGET_OFFS 4 /*Unit ID */ -+#define PXWERCR_TARGET_MASK (0xf << PXWERCR_TARGET_OFFS) -+#define PXWERCR_ATTRIB_OFFS 8 /* target attributes */ -+#define PXWERCR_ATTRIB_MASK (0xff << PXWERCR_ATTRIB_OFFS) -+ -+/* PCI Express Expansion ROM Window Remap Register */ -+/* PEX_WIN_EXP_ROM_REMAP_REG (PXWERRR)*/ -+ -+#define PXWERRR_REMAP_EN BIT0 -+#define PXWERRR_REMAP_OFFS 16 -+#define PXWERRR_REMAP_MASK (0xffff << PXWERRR_REMAP_OFFS) -+#define PXWERRR_REMAP_ALIGNMENT 0x10000 -+ -+ -+ -+/*PEX_MEMORY_BAR_BASE_ADDR(barNum) (PXMBBA)*/ -+/* PCI Express BAR0 Internal Register*/ -+/*PEX BAR0_INTER_REG (PXBIR)*/ -+ -+#define PXBIR_IOSPACE BIT0 /* Memory Space Indicator */ -+ -+#define PXBIR_TYPE_OFFS 1 /* BAR Type/Init Val. */ -+#define PXBIR_TYPE_MASK (0x3 << PXBIR_TYPE_OFFS) -+#define PXBIR_TYPE_32BIT_ADDR (0x0 << PXBIR_TYPE_OFFS) -+#define PXBIR_TYPE_64BIT_ADDR (0x2 << PXBIR_TYPE_OFFS) -+ -+#define PXBIR_PREFETCH_EN BIT3 /* Prefetch Enable */ -+ -+#define PXBIR_BASE_OFFS 20 /* Base address. Address bits [31:20] */ -+#define PXBIR_BASE_MASK (0xfff << PXBIR_BASE_OFFS) -+#define PXBIR_BASE_ALIGNMET (1 << PXBIR_BASE_OFFS) -+ -+ -+/* PCI Express BAR0 Internal (High) Register*/ -+/*PEX BAR0_INTER_REG_HIGH (PXBIRH)*/ -+ -+#define PXBIRH_BASE_OFFS 0 /* Base address. Bits [63:32] */ -+#define PXBIRH_BASE_MASK (0xffffffff << PBBHR_BASE_OFFS) -+ -+ -+#define PEX_BAR_DEFAULT_ATTRIB 0xc /* Memory - Prefetch - 64 bit address */ -+#define PEX_BAR0_DEFAULT_ATTRIB PEX_BAR_DEFAULT_ATTRIB -+#define PEX_BAR1_DEFAULT_ATTRIB PEX_BAR_DEFAULT_ATTRIB -+#define PEX_BAR2_DEFAULT_ATTRIB PEX_BAR_DEFAULT_ATTRIB -+ -+ -+/* PCI Express BAR1 Register */ -+/* PCI Express BAR2 Register*/ -+/*PEX BAR1_REG (PXBR)*/ -+/*PEX BAR2_REG (PXBR)*/ -+ -+#define PXBR_IOSPACE BIT0 /* Memory Space Indicator */ -+ -+#define PXBR_TYPE_OFFS 1 /* BAR Type/Init Val. */ -+#define PXBR_TYPE_MASK (0x3 << PXBR_TYPE_OFFS) -+#define PXBR_TYPE_32BIT_ADDR (0x0 << PXBR_TYPE_OFFS) -+#define PXBR_TYPE_64BIT_ADDR (0x2 << PXBR_TYPE_OFFS) -+ -+#define PXBR_PREFETCH_EN BIT3 /* Prefetch Enable */ -+ -+#define PXBR_BASE_OFFS 16 /* Base address. Address bits [31:16] */ -+#define PXBR_BASE_MASK (0xffff << PXBR_BASE_OFFS) -+#define PXBR_BASE_ALIGNMET (1 << PXBR_BASE_OFFS) -+ -+ -+/* PCI Express BAR1 (High) Register*/ -+/* PCI Express BAR2 (High) Register*/ -+/*PEX BAR1_REG_HIGH (PXBRH)*/ -+/*PEX BAR2_REG_HIGH (PXBRH)*/ -+ -+#define PXBRH_BASE_OFFS 0 /* Base address. Address bits [63:32] */ -+#define PXBRH_BASE_MASK (0xffffffff << PXBRH_BASE_OFFS) -+ -+/* PCI Express Expansion ROM BAR Register*/ -+/*PEX_EXPANSION_ROM_BASE_ADDR_REG (PXERBAR)*/ -+ -+#define PXERBAR_EXPROMEN BIT0 /* Expansion ROM Enable */ -+ -+#define PXERBAR_BASE_512K_OFFS 19 /* Expansion ROM Base Address */ -+#define PXERBAR_BASE_512K_MASK (0x1fff << PXERBAR_BASE_512K_OFFS) -+ -+#define PXERBAR_BASE_1MB_OFFS 20 /* Expansion ROM Base Address */ -+#define PXERBAR_BASE_1MB_MASK (0xfff << PXERBAR_BASE_1MB_OFFS) -+ -+#define PXERBAR_BASE_2MB_OFFS 21 /* Expansion ROM Base Address */ -+#define PXERBAR_BASE_2MB_MASK (0x7ff << PXERBAR_BASE_2MB_OFFS) -+ -+#define PXERBAR_BASE_4MB_OFFS 22 /* Expansion ROM Base Address */ -+#define PXERBAR_BASE_4MB_MASK (0x3ff << PXERBAR_BASE_4MB_OFFS) -+ -+/* PEX Bar attributes */ -+typedef struct _mvPexBar -+{ -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+}MV_PEX_BAR; -+ -+/* PEX Remap Window attributes */ -+typedef struct _mvPexRemapWin -+{ -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+}MV_PEX_REMAP_WIN; -+ -+/* PEX Remap Window attributes */ -+typedef struct _mvPexDecWin -+{ -+ MV_TARGET target; -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_U32 targetBar; -+ MV_U8 attrib; /* chip select attributes */ -+ MV_TARGET_ID targetId; /* Target Id of this MV_TARGET */ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+}MV_PEX_DEC_WIN; -+ -+/* Global Functions prototypes */ -+/* mvPexHalInit - Initialize PEX interfaces*/ -+MV_STATUS mvPexInit(MV_U32 pexIf, MV_PEX_TYPE pexType); -+ -+ -+/* mvPexTargetWinSet - Set PEX to peripheral target address window BAR*/ -+MV_STATUS mvPexTargetWinSet(MV_U32 pexIf, MV_U32 winNum, -+ MV_PEX_DEC_WIN *pAddrDecWin); -+ -+/* mvPexTargetWinGet - Get PEX to peripheral target address window*/ -+MV_STATUS mvPexTargetWinGet(MV_U32 pexIf, MV_U32 winNum, -+ MV_PEX_DEC_WIN *pAddrDecWin); -+ -+/* mvPexTargetWinEnable - Enable/disable a PEX BAR window*/ -+MV_STATUS mvPexTargetWinEnable(MV_U32 pexIf,MV_U32 winNum, MV_BOOL enable); -+ -+/* mvPexTargetWinRemap - Set PEX to target address window remap.*/ -+MV_STATUS mvPexTargetWinRemap(MV_U32 pexIf, MV_U32 winNum, -+ MV_PEX_REMAP_WIN *pAddrWin); -+ -+/* mvPexTargetWinRemapEnable -enable\disable a PEX Window remap.*/ -+MV_STATUS mvPexTargetWinRemapEnable(MV_U32 pexIf, MV_U32 winNum, -+ MV_BOOL enable); -+ -+/* mvPexBarSet - Set PEX bar address and size */ -+MV_STATUS mvPexBarSet(MV_U32 pexIf, MV_U32 barNum, MV_PEX_BAR *addrWin); -+ -+/* mvPexBarGet - Get PEX bar address and size */ -+MV_STATUS mvPexBarGet(MV_U32 pexIf, MV_U32 barNum, MV_PEX_BAR *addrWin); -+ -+/* mvPexBarEnable - enable\disable a PEX bar*/ -+MV_STATUS mvPexBarEnable(MV_U32 pexIf, MV_U32 barNum, MV_BOOL enable); -+ -+/* mvPexAddrDecShow - Display address decode windows attributes */ -+MV_VOID mvPexAddrDecShow(MV_VOID); -+ -+#endif -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,430 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#include "mvTypes.h" -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "cpu/mvCpu.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+#include "sata/CoreDriver/mvRegs.h" -+#include "ctrlEnv/sys/mvSysSata.h" -+ -+MV_TARGET sataAddrDecPrioTab[] = -+{ -+#if defined(MV_INCLUDE_SDRAM_CS0) -+ SDRAM_CS0, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS1) -+ SDRAM_CS1, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS2) -+ SDRAM_CS2, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS3) -+ SDRAM_CS3, -+#endif -+#if defined(MV_INCLUDE_PEX) -+ PEX0_MEM, -+#endif -+ TBL_TERM -+}; -+ -+ -+/******************************************************************************* -+* sataWinOverlapDetect - Detect SATA address windows overlapping -+* -+* DESCRIPTION: -+* An unpredicted behaviur is expected in case SATA address decode -+* windows overlapps. -+* This function detects SATA address decode windows overlapping of a -+* specified window. The function does not check the window itself for -+* overlapping. The function also skipps disabled address decode windows. -+* -+* INPUT: -+* winNum - address decode window number. -+* pAddrDecWin - An address decode window struct. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data -+* from registers. -+* -+*******************************************************************************/ -+static MV_STATUS sataWinOverlapDetect(int dev, MV_U32 winNum, -+ MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 winNumIndex; -+ MV_SATA_DEC_WIN addrDecWin; -+ -+ for(winNumIndex=0; winNumIndex= MV_SATA_MAX_ADDR_DECODE_WIN) -+ { -+ mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlapps with current windows */ -+ if (MV_TRUE == sataWinOverlapDetect(dev, winNum, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); -+ return MV_ERROR; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvSataWinSet:Error setting SATA window %d to "\ -+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, -+ mvCtrlTargetNameGet(pAddrDecWin->target), -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ decRegs.baseReg = 0; -+ decRegs.sizeReg = 0; -+ -+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) -+ { -+ mvOsPrintf("%s: mvCtrlAddrDecToReg Failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); -+ -+ /* set attributes */ -+ decRegs.sizeReg &= ~MV_SATA_WIN_ATTR_MASK; -+ decRegs.sizeReg |= (targetAttribs.attrib << MV_SATA_WIN_ATTR_OFFSET); -+ -+ /* set target ID */ -+ decRegs.sizeReg &= ~MV_SATA_WIN_TARGET_MASK; -+ decRegs.sizeReg |= (targetAttribs.targetId << MV_SATA_WIN_TARGET_OFFSET); -+ -+ if (pAddrDecWin->enable == MV_TRUE) -+ { -+ decRegs.sizeReg |= MV_SATA_WIN_ENABLE_MASK; -+ } -+ else -+ { -+ decRegs.sizeReg &= ~MV_SATA_WIN_ENABLE_MASK; -+ } -+ -+ MV_REG_WRITE( MV_SATA_WIN_CTRL_REG(dev, winNum), decRegs.sizeReg); -+ MV_REG_WRITE( MV_SATA_WIN_BASE_REG(dev, winNum), decRegs.baseReg); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSataWinGet - Get SATA peripheral target address window. -+* -+* DESCRIPTION: -+* Get SATA peripheral target address window. -+* -+* INPUT: -+* winNum - SATA target address decode window number. -+* -+* OUTPUT: -+* pAddrDecWin - SATA target window data structure. -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvSataWinGet(int dev, MV_U32 winNum, MV_SATA_DEC_WIN *pAddrDecWin) -+{ -+ MV_DEC_REGS decRegs; -+ MV_TARGET_ATTRIB targetAttrib; -+ -+ /* Parameter checking */ -+ if (winNum >= MV_SATA_MAX_ADDR_DECODE_WIN) -+ { -+ mvOsPrintf("%s (dev=%d): ERR. Invalid winNum %d\n", -+ __FUNCTION__, dev, winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ decRegs.baseReg = MV_REG_READ( MV_SATA_WIN_BASE_REG(dev, winNum) ); -+ decRegs.sizeReg = MV_REG_READ( MV_SATA_WIN_CTRL_REG(dev, winNum) ); -+ -+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs, &pAddrDecWin->addrWin) ) -+ { -+ mvOsPrintf("%s: mvCtrlRegToAddrDec Failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ /* attrib and targetId */ -+ targetAttrib.attrib = (decRegs.sizeReg & MV_SATA_WIN_ATTR_MASK) >> -+ MV_SATA_WIN_ATTR_OFFSET; -+ targetAttrib.targetId = (decRegs.sizeReg & MV_SATA_WIN_TARGET_MASK) >> -+ MV_SATA_WIN_TARGET_OFFSET; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ /* Check if window is enabled */ -+ if(decRegs.sizeReg & MV_SATA_WIN_ENABLE_MASK) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ } -+ return MV_OK; -+} -+/******************************************************************************* -+* mvSataAddrDecShow - Print the SATA address decode map. -+* -+* DESCRIPTION: -+* This function print the SATA address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvSataAddrDecShow(MV_VOID) -+{ -+ -+ MV_SATA_DEC_WIN win; -+ int i,j; -+ -+ -+ -+ for( j = 0; j < MV_SATA_MAX_CHAN; j++ ) -+ { -+ if (MV_FALSE == mvCtrlPwrClckGet(SATA_UNIT_ID, j)) -+ return; -+ -+ mvOsOutput( "\n" ); -+ mvOsOutput( "SATA %d:\n", j ); -+ mvOsOutput( "----\n" ); -+ -+ for( i = 0; i < MV_SATA_MAX_ADDR_DECODE_WIN; i++ ) -+ { -+ memset( &win, 0, sizeof(MV_SATA_DEC_WIN) ); -+ -+ mvOsOutput( "win%d - ", i ); -+ -+ if( mvSataWinGet(j, i, &win ) == MV_OK ) -+ { -+ if( win.enable ) -+ { -+ mvOsOutput( "%s base %08x, ", -+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); -+ mvOsOutput( "...." ); -+ -+ mvSizePrint( win.addrWin.size ); -+ -+ mvOsOutput( "\n" ); -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ } -+ } -+ } -+} -+ -+ -+/******************************************************************************* -+* mvSataWinInit - Initialize the integrated SATA target address window. -+* -+* DESCRIPTION: -+* Initialize the SATA peripheral target address window. -+* -+* INPUT: -+* -+* -+* OUTPUT: -+* -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvSataWinInit(MV_VOID) -+{ -+ int winNum; -+ MV_SATA_DEC_WIN sataWin; -+ MV_CPU_DEC_WIN cpuAddrDecWin; -+ MV_U32 status, winPrioIndex = 0; -+ -+ /* Initiate Sata address decode */ -+ -+ /* First disable all address decode windows */ -+ for(winNum = 0; winNum < MV_SATA_MAX_ADDR_DECODE_WIN; winNum++) -+ { -+ MV_U32 regVal = MV_REG_READ(MV_SATA_WIN_CTRL_REG(0, winNum)); -+ regVal &= ~MV_SATA_WIN_ENABLE_MASK; -+ MV_REG_WRITE(MV_SATA_WIN_CTRL_REG(0, winNum), regVal); -+ } -+ -+ winNum = 0; -+ while( (sataAddrDecPrioTab[winPrioIndex] != TBL_TERM) && -+ (winNum < MV_SATA_MAX_ADDR_DECODE_WIN) ) -+ { -+ /* first get attributes from CPU If */ -+ status = mvCpuIfTargetWinGet(sataAddrDecPrioTab[winPrioIndex], -+ &cpuAddrDecWin); -+ -+ if(MV_NO_SUCH == status) -+ { -+ winPrioIndex++; -+ continue; -+ } -+ if (MV_OK != status) -+ { -+ mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ if (cpuAddrDecWin.enable == MV_TRUE) -+ { -+ sataWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; -+ sataWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; -+ sataWin.addrWin.size = cpuAddrDecWin.addrWin.size; -+ sataWin.enable = MV_TRUE; -+ sataWin.target = sataAddrDecPrioTab[winPrioIndex]; -+ -+ if(MV_OK != mvSataWinSet(0/*dev*/, winNum, &sataWin)) -+ { -+ return MV_ERROR; -+ } -+ winNum++; -+ } -+ winPrioIndex++; -+ } -+ return MV_OK; -+} -+ -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,128 @@ -+ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#ifndef __INCMVSysSataAddrDech -+#define __INCMVSysSataAddrDech -+ -+#include "mvCommon.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+ -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+typedef struct _mvSataDecWin -+{ -+ MV_TARGET target; -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+} MV_SATA_DEC_WIN; -+ -+ -+#define MV_SATA_MAX_ADDR_DECODE_WIN 4 -+ -+#define MV_SATA_WIN_CTRL_REG(dev, win) (SATA_REG_BASE + 0x30 + ((win)<<4)) -+#define MV_SATA_WIN_BASE_REG(dev, win) (SATA_REG_BASE + 0x34 + ((win)<<4)) -+ -+/* BITs in Bridge Interrupt Cause and Mask registers */ -+#define MV_SATA_ADDR_DECODE_ERROR_BIT 0 -+#define MV_SATA_ADDR_DECODE_ERROR_MASK (1<= MV_SDMMC_MAX_ADDR_DECODE_WIN) -+ { -+ mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlapps with current windows */ -+ if (MV_TRUE == sdmmcWinOverlapDetect(dev, winNum, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); -+ return MV_ERROR; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvSdmmcWinSet:Error setting SDMMC window %d to "\ -+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, -+ mvCtrlTargetNameGet(pAddrDecWin->target), -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ decRegs.baseReg = 0; -+ decRegs.sizeReg = 0; -+ -+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) -+ { -+ mvOsPrintf("%s: mvCtrlAddrDecToReg Failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); -+ -+ /* set attributes */ -+ decRegs.sizeReg &= ~MV_SDMMC_WIN_ATTR_MASK; -+ decRegs.sizeReg |= (targetAttribs.attrib << MV_SDMMC_WIN_ATTR_OFFSET); -+ -+ /* set target ID */ -+ decRegs.sizeReg &= ~MV_SDMMC_WIN_TARGET_MASK; -+ decRegs.sizeReg |= (targetAttribs.targetId << MV_SDMMC_WIN_TARGET_OFFSET); -+ -+ if (pAddrDecWin->enable == MV_TRUE) -+ { -+ decRegs.sizeReg |= MV_SDMMC_WIN_ENABLE_MASK; -+ } -+ else -+ { -+ decRegs.sizeReg &= ~MV_SDMMC_WIN_ENABLE_MASK; -+ } -+ -+ MV_REG_WRITE( MV_SDMMC_WIN_CTRL_REG(dev, winNum), decRegs.sizeReg); -+ MV_REG_WRITE( MV_SDMMC_WIN_BASE_REG(dev, winNum), decRegs.baseReg); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSdmmcWinGet - Get SDMMC peripheral target address window. -+* -+* DESCRIPTION: -+* Get SDMMC peripheral target address window. -+* -+* INPUT: -+* winNum - SDMMC target address decode window number. -+*d -+* OUTPUT: -+* pAddrDecWin - SDMMC target window data structure. -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvSdmmcWinGet(int dev, MV_U32 winNum, MV_SDMMC_DEC_WIN *pAddrDecWin) -+{ -+ MV_DEC_REGS decRegs; -+ MV_TARGET_ATTRIB targetAttrib; -+ -+ /* Parameter checking */ -+ if (winNum >= MV_SDMMC_MAX_ADDR_DECODE_WIN) -+ { -+ mvOsPrintf("%s (dev=%d): ERR. Invalid winNum %d\n", -+ __FUNCTION__, dev, winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ decRegs.baseReg = MV_REG_READ( MV_SDMMC_WIN_BASE_REG(dev, winNum) ); -+ decRegs.sizeReg = MV_REG_READ( MV_SDMMC_WIN_CTRL_REG(dev, winNum) ); -+ -+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs, &pAddrDecWin->addrWin) ) -+ { -+ mvOsPrintf("%s: mvCtrlRegToAddrDec Failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ /* attrib and targetId */ -+ targetAttrib.attrib = (decRegs.sizeReg & MV_SDMMC_WIN_ATTR_MASK) >> -+ MV_SDMMC_WIN_ATTR_OFFSET; -+ targetAttrib.targetId = (decRegs.sizeReg & MV_SDMMC_WIN_TARGET_MASK) >> -+ MV_SDMMC_WIN_TARGET_OFFSET; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ /* Check if window is enabled */ -+ if(decRegs.sizeReg & MV_SDMMC_WIN_ENABLE_MASK) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ } -+ return MV_OK; -+} -+/******************************************************************************* -+* mvSdmmcAddrDecShow - Print the SDMMC address decode map. -+* -+* DESCRIPTION: -+* This function print the SDMMC address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvSdmmcAddrDecShow(MV_VOID) -+{ -+ -+ MV_SDMMC_DEC_WIN win; -+ int i,j=0; -+ -+ -+ -+ if (MV_FALSE == mvCtrlPwrClckGet(SDIO_UNIT_ID, 0)) -+ return; -+ -+ mvOsOutput( "\n" ); -+ mvOsOutput( "SDMMC %d:\n", j ); -+ mvOsOutput( "----\n" ); -+ -+ for( i = 0; i < MV_SDMMC_MAX_ADDR_DECODE_WIN; i++ ) -+ { -+ memset( &win, 0, sizeof(MV_SDMMC_DEC_WIN) ); -+ -+ mvOsOutput( "win%d - ", i ); -+ -+ if( mvSdmmcWinGet(j, i, &win ) == MV_OK ) -+ { -+ if( win.enable ) -+ { -+ mvOsOutput( "%s base %08x, ", -+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); -+ mvOsOutput( "...." ); -+ -+ mvSizePrint( win.addrWin.size ); -+ -+ mvOsOutput( "\n" ); -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ } -+ } -+} -+ -+ -+/******************************************************************************* -+* mvSdmmcWinInit - Initialize the integrated SDMMC target address window. -+* -+* DESCRIPTION: -+* Initialize the SDMMC peripheral target address window. -+* -+* INPUT: -+* -+* -+* OUTPUT: -+* -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvSdmmcWinInit(MV_VOID) -+{ -+ int winNum; -+ MV_SDMMC_DEC_WIN sdmmcWin; -+ MV_CPU_DEC_WIN cpuAddrDecWin; -+ MV_U32 status, winPrioIndex = 0; -+ -+ /* Initiate Sdmmc address decode */ -+ -+ /* First disable all address decode windows */ -+ for(winNum = 0; winNum < MV_SDMMC_MAX_ADDR_DECODE_WIN; winNum++) -+ { -+ MV_U32 regVal = MV_REG_READ(MV_SDMMC_WIN_CTRL_REG(0, winNum)); -+ regVal &= ~MV_SDMMC_WIN_ENABLE_MASK; -+ MV_REG_WRITE(MV_SDMMC_WIN_CTRL_REG(0, winNum), regVal); -+ } -+ -+ winNum = 0; -+ while( (sdmmcAddrDecPrioTab[winPrioIndex] != TBL_TERM) && -+ (winNum < MV_SDMMC_MAX_ADDR_DECODE_WIN) ) -+ { -+ /* first get attributes from CPU If */ -+ status = mvCpuIfTargetWinGet(sdmmcAddrDecPrioTab[winPrioIndex], -+ &cpuAddrDecWin); -+ -+ if(MV_NO_SUCH == status) -+ { -+ winPrioIndex++; -+ continue; -+ } -+ if (MV_OK != status) -+ { -+ mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ if (cpuAddrDecWin.enable == MV_TRUE) -+ { -+ sdmmcWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; -+ sdmmcWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; -+ sdmmcWin.addrWin.size = cpuAddrDecWin.addrWin.size; -+ sdmmcWin.enable = MV_TRUE; -+ sdmmcWin.target = sdmmcAddrDecPrioTab[winPrioIndex]; -+ -+ if(MV_OK != mvSdmmcWinSet(0/*dev*/, winNum, &sdmmcWin)) -+ { -+ return MV_ERROR; -+ } -+ winNum++; -+ } -+ winPrioIndex++; -+ } -+ return MV_OK; -+} -+ -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,125 @@ -+ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#ifndef __INCMVSysSdmmcAddrDech -+#define __INCMVSysSdmmcAddrDech -+ -+#include "mvCommon.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+ -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+typedef struct _mvSdmmcDecWin -+{ -+ MV_TARGET target; -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+} MV_SDMMC_DEC_WIN; -+ -+ -+#define MV_SDMMC_MAX_ADDR_DECODE_WIN 4 -+ -+#define MV_SDMMC_WIN_CTRL_REG(dev, win) (MV_SDIO_REG_BASE + 0x108 + ((win)<<3)) -+#define MV_SDMMC_WIN_BASE_REG(dev, win) (MV_SDIO_REG_BASE + 0x10c + ((win)<<3)) -+ -+ -+/* BITs in Windows 0-3 Control and Base Registers */ -+#define MV_SDMMC_WIN_ENABLE_BIT 0 -+#define MV_SDMMC_WIN_ENABLE_MASK (1<= TDM_MBUS_MAX_WIN) -+ { -+ mvOsPrintf("mvTdmWinSet: ERR. Invalid win num %d\n",winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlapps with current windows */ -+ if (MV_TRUE == tdmWinOverlapDetect(winNum, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("mvTdmWinSet: ERR. Window %d overlap\n", winNum); -+ return MV_ERROR; -+ } -+ -+ /* check if address is aligned to the size */ -+ if (MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvTdmWinSet: Error setting TDM window %d to "\ -+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, -+ mvCtrlTargetNameGet(pAddrDecWin->target), -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ decRegs.baseReg = MV_REG_READ(TDM_WIN_BASE_REG(winNum)); -+ decRegs.sizeReg = (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_SIZE_MASK) >> TDM_WIN_SIZE_OFFS; -+ -+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) -+ { -+ mvOsPrintf("mvTdmWinSet: mvCtrlAddrDecToReg Failed\n"); -+ return MV_ERROR; -+ } -+ -+ mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); -+ -+ /* for the safe side we disable the window before writing the new -+ values */ -+ mvTdmWinEnable(winNum, MV_FALSE); -+ -+ ctrlReg |= (targetAttribs.attrib << TDM_WIN_ATTRIB_OFFS); -+ ctrlReg |= (targetAttribs.targetId << TDM_WIN_TARGET_OFFS); -+ ctrlReg |= (decRegs.sizeReg & TDM_WIN_SIZE_MASK); -+ -+ /* Write to address base and control registers */ -+ MV_REG_WRITE(TDM_WIN_BASE_REG(winNum), decRegs.baseReg); -+ MV_REG_WRITE(TDM_WIN_CTRL_REG(winNum), ctrlReg); -+ /* Enable address decode target window */ -+ if (pAddrDecWin->enable == MV_TRUE) -+ { -+ mvTdmWinEnable(winNum, MV_TRUE); -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvTdmWinGet - Get peripheral target address window. -+* -+* DESCRIPTION: -+* Get TDM peripheral target address window. -+* -+* INPUT: -+* winNum - TDM to target address decode window number. -+* -+* OUTPUT: -+* pAddrDecWin - TDM target window data structure. -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+ -+MV_STATUS mvTdmWinGet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin) -+{ -+ -+ MV_DEC_REGS decRegs; -+ MV_TARGET_ATTRIB targetAttrib; -+ -+ /* Parameter checking */ -+ if (winNum >= TDM_MBUS_MAX_WIN) -+ { -+ mvOsPrintf("mvTdmWinGet: ERR. Invalid winNum %d\n", winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ decRegs.baseReg = MV_REG_READ(TDM_WIN_BASE_REG(winNum)); -+ decRegs.sizeReg = (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_SIZE_MASK) >> TDM_WIN_SIZE_OFFS; -+ -+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) -+ { -+ mvOsPrintf("mvTdmWinGet: mvCtrlRegToAddrDec Failed \n"); -+ return MV_ERROR; -+ } -+ -+ /* attrib and targetId */ -+ targetAttrib.attrib = -+ (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ATTRIB_MASK) >> TDM_WIN_ATTRIB_OFFS; -+ targetAttrib.targetId = -+ (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_TARGET_MASK) >> TDM_WIN_TARGET_OFFS; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ /* Check if window is enabled */ -+ if (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ENABLE_MASK) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvTdmWinEnable - Enable/disable a TDM to target address window -+* -+* DESCRIPTION: -+* This function enable/disable a TDM to target address window. -+* According to parameter 'enable' the routine will enable the -+* window, thus enabling TDM accesses (before enabling the window it is -+* tested for overlapping). Otherwise, the window will be disabled. -+* -+* INPUT: -+* winNum - TDM to target address decode window number. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_ERROR if decode window number was wrong or enabled window overlapps. -+* -+*******************************************************************************/ -+MV_STATUS mvTdmWinEnable(int winNum, MV_BOOL enable) -+{ -+ MV_TDM_DEC_WIN addrDecWin; -+ -+ if (MV_TRUE == enable) -+ { -+ if (winNum >= TDM_MBUS_MAX_WIN) -+ { -+ mvOsPrintf("mvTdmWinEnable:ERR. Invalid winNum%d\n",winNum); -+ return MV_ERROR; -+ } -+ -+ /* First check for overlap with other enabled windows */ -+ /* Get current window */ -+ if (MV_OK != mvTdmWinGet(winNum, &addrDecWin)) -+ { -+ mvOsPrintf("mvTdmWinEnable:ERR. targetWinGet fail\n"); -+ return MV_ERROR; -+ } -+ /* Check for overlapping */ -+ if (MV_FALSE == tdmWinOverlapDetect(winNum, &(addrDecWin.addrWin))) -+ { -+ /* No Overlap. Enable address decode target window */ -+ MV_REG_BIT_SET(TDM_WIN_CTRL_REG(winNum), TDM_WIN_ENABLE_MASK); -+ } -+ else -+ { /* Overlap detected */ -+ mvOsPrintf("mvTdmWinEnable:ERR. Overlap detected\n"); -+ return MV_ERROR; -+ } -+ } -+ else -+ { -+ MV_REG_BIT_RESET(TDM_WIN_CTRL_REG(winNum), TDM_WIN_ENABLE_MASK); -+ } -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* tdmWinOverlapDetect - Detect TDM address windows overlapping -+* -+* DESCRIPTION: -+* An unpredicted behaviour is expected in case TDM address decode -+* windows overlapps. -+* This function detects TDM address decode windows overlapping of a -+* specified window. The function does not check the window itself for -+* overlapping. The function also skipps disabled address decode windows. -+* -+* INPUT: -+* winNum - address decode window number. -+* pAddrDecWin - An address decode window struct. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data -+* from registers. -+* -+*******************************************************************************/ -+static MV_STATUS tdmWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 winNumIndex; -+ MV_TDM_DEC_WIN addrDecWin; -+ -+ for (winNumIndex = 0; winNumIndex < TDM_MBUS_MAX_WIN; winNumIndex++) -+ { -+ /* Do not check window itself */ -+ if (winNumIndex == winNum) -+ { -+ continue; -+ } -+ /* Do not check disabled windows */ -+ if (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ENABLE_MASK) -+ { -+ /* Get window parameters */ -+ if (MV_OK != mvTdmWinGet(winNumIndex, &addrDecWin)) -+ { -+ DB(mvOsPrintf("dmaWinOverlapDetect: ERR. TargetWinGet failed\n")); -+ return MV_ERROR; -+ } -+ -+ if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin))) -+ { -+ return MV_TRUE; -+ } -+ } -+ } -+ return MV_FALSE; -+} -+ -+/******************************************************************************* -+* mvTdmAddrDecShow - Print the TDM address decode map. -+* -+* DESCRIPTION: -+* This function print the TDM address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvTdmAddrDecShow(MV_VOID) -+{ -+ MV_TDM_DEC_WIN win; -+ int i; -+ -+ mvOsOutput( "\n" ); -+ mvOsOutput( "TDM:\n" ); -+ mvOsOutput( "----\n" ); -+ -+ for( i = 0; i < TDM_MBUS_MAX_WIN; i++ ) -+ { -+ memset( &win, 0, sizeof(MV_TDM_DEC_WIN) ); -+ -+ mvOsOutput( "win%d - ", i ); -+ -+ if (mvTdmWinGet(i, &win ) == MV_OK ) -+ { -+ if( win.enable ) -+ { -+ mvOsOutput( "%s base %08x, ", -+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow); -+ mvOsOutput( "...." ); -+ mvSizePrint( win.addrWin.size ); -+ mvOsOutput( "\n" ); -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ } -+ } -+} -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,106 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvSysTdmh -+#define __INCmvSysTdmh -+ -+#include "ctrlEnv/sys/mvCpuIf.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+ -+typedef struct _mvTdmDecWin -+{ -+ MV_TARGET target; -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+} MV_TDM_DEC_WIN; -+ -+MV_STATUS mvTdmWinInit(MV_VOID); -+MV_STATUS mvTdmWinSet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin); -+MV_STATUS mvTdmWinGet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin); -+MV_STATUS mvTdmWinEnable(int winNum, MV_BOOL enable); -+MV_VOID mvTdmAddrDecShow(MV_VOID); -+ -+ -+#define TDM_MBUS_MAX_WIN 4 -+#define TDM_WIN_CTRL_REG(win) ((TDM_REG_BASE + 0x4030) + (win<<4)) -+#define TDM_WIN_BASE_REG(win) ((TDM_REG_BASE +0x4034) + (win<<4)) -+ -+/* TDM_WIN_CTRL_REG bits */ -+#define TDM_WIN_ENABLE_OFFS 0 -+#define TDM_WIN_ENABLE_MASK (1<= TSU_MAX_DECODE_WIN) -+ { -+ mvOsPrintf("mvTsuWinSet: ERR. Invalid win num %d\n",winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlapps with current windows */ -+ if(MV_TRUE == tsuWinOverlapDetect(winNum, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("mvTsuWinSet: ERR. Window %d overlap\n", winNum); -+ return MV_ERROR; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow,pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvTsuWinSet: Error setting TSU window %d to target " -+ "%s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, mvCtrlTargetNameGet(pAddrDecWin->target), -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ decRegs.baseReg = MV_REG_READ(MV_TSU_WIN_BASE_REG(winNum)); -+ decRegs.sizeReg = MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNum)); -+ -+ if(MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) -+ { -+ mvOsPrintf("mvTsuWinSet: mvCtrlAddrDecToReg Failed\n"); -+ return MV_ERROR; -+ } -+ -+ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); -+ -+ /* set attributes */ -+ decRegs.sizeReg &= ~TSU_WIN_CTRL_ATTR_MASK; -+ decRegs.sizeReg |= targetAttribs.attrib << TSU_WIN_CTRL_ATTR_OFFS; -+ /* set target ID */ -+ decRegs.sizeReg &= ~TSU_WIN_CTRL_TARGET_MASK; -+ decRegs.sizeReg |= targetAttribs.targetId << TSU_WIN_CTRL_TARGET_OFFS; -+ -+ /* for the safe side we disable the window before writing the new */ -+ /* values */ -+ mvTsuWinEnable(winNum, MV_FALSE); -+ MV_REG_WRITE(MV_TSU_WIN_CTRL_REG(winNum),decRegs.sizeReg); -+ -+ /* Write to address decode Size Register */ -+ MV_REG_WRITE(MV_TSU_WIN_BASE_REG(winNum), decRegs.baseReg); -+ -+ /* Enable address decode target window */ -+ if(pAddrDecWin->enable == MV_TRUE) -+ { -+ mvTsuWinEnable(winNum,MV_TRUE); -+ } -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvTsuWinGet -+* -+* DESCRIPTION: -+* Get TSU peripheral target address window. -+* -+* INPUT: -+* winNum - TSU to target address decode window number. -+* -+* OUTPUT: -+* pAddrDecWin - TSU target window data structure. -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvTsuWinGet(MV_U32 winNum, MV_TSU_DEC_WIN *pAddrDecWin) -+{ -+ MV_DEC_REGS decRegs; -+ MV_TARGET_ATTRIB targetAttrib; -+ -+ /* Parameter checking */ -+ if(winNum >= TSU_MAX_DECODE_WIN) -+ { -+ mvOsPrintf("mvTsuWinGet: ERR. Invalid winNum %d\n", winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ decRegs.baseReg = MV_REG_READ(MV_TSU_WIN_BASE_REG(winNum)); -+ decRegs.sizeReg = MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNum)); -+ -+ if(MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) -+ { -+ mvOsPrintf("mvTsuWinGet: mvCtrlRegToAddrDec Failed \n"); -+ return MV_ERROR; -+ } -+ -+ /* attrib and targetId */ -+ targetAttrib.attrib = -+ (decRegs.sizeReg & TSU_WIN_CTRL_ATTR_MASK) >> TSU_WIN_CTRL_ATTR_OFFS; -+ targetAttrib.targetId = -+ (decRegs.sizeReg & TSU_WIN_CTRL_TARGET_MASK) >> TSU_WIN_CTRL_TARGET_OFFS; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ /* Check if window is enabled */ -+ if((MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNum)) & TSU_WIN_CTRL_EN_MASK)) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ } -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvTsuWinEnable -+* -+* DESCRIPTION: -+* This function enable/disable a TSU to target address window. -+* According to parameter 'enable' the routine will enable the -+* window, thus enabling TSU accesses (before enabling the window it is -+* tested for overlapping). Otherwise, the window will be disabled. -+* -+* INPUT: -+* winNum - TSU to target address decode window number. -+* enable - Enable / disable parameter. -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_ERROR if decode window number was wrong or enabled window overlapps. -+* -+*******************************************************************************/ -+MV_STATUS mvTsuWinEnable(MV_U32 winNum,MV_BOOL enable) -+{ -+ MV_TSU_DEC_WIN addrDecWin; -+ -+ /* Parameter checking */ -+ if(winNum >= TSU_MAX_DECODE_WIN) -+ { -+ mvOsPrintf("mvTsuWinEnable: ERR. Invalid winNum%d\n",winNum); -+ return MV_ERROR; -+ } -+ -+ if(enable == MV_TRUE) -+ { -+ /* First check for overlap with other enabled windows */ -+ /* Get current window. */ -+ if(MV_OK != mvTsuWinGet(winNum,&addrDecWin)) -+ { -+ mvOsPrintf("mvTsuWinEnable: ERR. targetWinGet fail\n"); -+ return MV_ERROR; -+ } -+ /* Check for overlapping. */ -+ if(MV_FALSE == tsuWinOverlapDetect(winNum,&(addrDecWin.addrWin))) -+ { -+ /* No Overlap. Enable address decode target window */ -+ MV_REG_BIT_SET(MV_TSU_WIN_CTRL_REG(winNum), -+ TSU_WIN_CTRL_EN_MASK); -+ } -+ else -+ { -+ /* Overlap detected */ -+ mvOsPrintf("mvTsuWinEnable: ERR. Overlap detected\n"); -+ return MV_ERROR; -+ } -+ } -+ else -+ { -+ /* Disable address decode target window */ -+ MV_REG_BIT_RESET(MV_TSU_WIN_CTRL_REG(winNum), -+ TSU_WIN_CTRL_EN_MASK); -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvTsuWinTargetGet -+* -+* DESCRIPTION: -+* Get Window number associated with target -+* -+* INPUT: -+* target - Target ID to get the window number for. -+* OUTPUT: -+* -+* RETURN: -+* window number or 0xFFFFFFFF on error. -+* -+*******************************************************************************/ -+MV_U32 mvTsuWinTargetGet(MV_TARGET target) -+{ -+ MV_TSU_DEC_WIN decWin; -+ MV_U32 winNum; -+ -+ /* Check parameters */ -+ if(target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvTsuWinTargetGet: target %d is Illigal\n", target); -+ return 0xffffffff; -+ } -+ -+ for(winNum = 0; winNum < TSU_MAX_DECODE_WIN; winNum++) -+ { -+ if(mvTsuWinGet(winNum,&decWin) != MV_OK) -+ { -+ mvOsPrintf("mvTsuWinGet: window returned error\n"); -+ return 0xffffffff; -+ } -+ -+ if (decWin.enable == MV_TRUE) -+ { -+ if(decWin.target == target) -+ { -+ return winNum; -+ } -+ } -+ } -+ return 0xFFFFFFFF; -+} -+ -+ -+/******************************************************************************* -+* tsuWinOverlapDetect -+* -+* DESCRIPTION: -+* Detect TSU address windows overlapping -+* An unpredicted behaviur is expected in case TSU address decode -+* windows overlapps. -+* This function detects TSU address decode windows overlapping of a -+* specified window. The function does not check the window itself for -+* overlapping. The function also skipps disabled address decode windows. -+* -+* INPUT: -+* winNum - address decode window number. -+* pAddrDecWin - An address decode window struct. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data -+* from registers. -+* -+*******************************************************************************/ -+static MV_STATUS tsuWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 ctrlReg; -+ MV_U32 winNumIndex; -+ MV_TSU_DEC_WIN addrDecWin; -+ -+ for(winNumIndex = 0; winNumIndex < TSU_MAX_DECODE_WIN; winNumIndex++) -+ { -+ /* Do not check window itself */ -+ if(winNumIndex == winNum) -+ { -+ continue; -+ } -+ -+ /* Do not check disabled windows */ -+ ctrlReg = MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNumIndex)); -+ if((ctrlReg & TSU_WIN_CTRL_EN_MASK) == 0) -+ { -+ continue; -+ } -+ -+ /* Get window parameters */ -+ if (MV_OK != mvTsuWinGet(winNumIndex, &addrDecWin)) -+ { -+ mvOsPrintf("tsuWinOverlapDetect: ERR. mvTsuWinGet failed\n"); -+ return MV_ERROR; -+ } -+ -+ if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin))) -+ { -+ return MV_TRUE; -+ } -+ } -+ return MV_FALSE; -+} -+ -+ -+/******************************************************************************* -+* mvTsuAddrDecShow -+* -+* DESCRIPTION: -+* Print the TSU address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+void mvTsuAddrDecShow(void) -+{ -+ MV_TSU_DEC_WIN win; -+ int i; -+ -+ if (MV_FALSE == mvCtrlPwrClckGet(TS_UNIT_ID, 0)) -+ return; -+ -+ mvOsOutput( "\n" ); -+ mvOsOutput( "TSU:\n"); -+ mvOsOutput( "----\n" ); -+ -+ for(i = 0; i < TSU_MAX_DECODE_WIN; i++) -+ { -+ memset(&win, 0, sizeof(TSU_MAX_DECODE_WIN)); -+ mvOsOutput( "win%d - ", i ); -+ -+ if(mvTsuWinGet(i, &win ) == MV_OK ) -+ { -+ if(win.enable == MV_TRUE) -+ { -+ mvOsOutput("%s base %08x, ", -+ mvCtrlTargetNameGet(win.target), -+ win.addrWin.baseLow); -+ mvOsOutput( "...." ); -+ mvSizePrint(win.addrWin.size ); -+ mvOsOutput( "\n" ); -+ } -+ else -+ { -+ mvOsOutput( "disable\n" ); -+ } -+ } -+ } -+ return; -+} -+ -+ -+/******************************************************************************* -+* mvTsuInit -+* -+* DESCRIPTION: -+* Initialize the TSU unit, and get unit out of reset. -+* -+* INPUT: -+* coreClock - The core clock at which the TSU should operate. -+* mode - The mode on configure the unit into (serial/parallel). -+* memHandle - Memory handle used for memory allocations. -+* OUTPUT: -+* None. -+* RETURN: -+* MV_OK - on success, -+* -+*******************************************************************************/ -+MV_STATUS mvTsuInit(MV_TSU_CORE_CLOCK coreClock, MV_TSU_PORTS_MODE mode, -+ void *osHandle) -+{ -+ MV_STATUS status; -+ -+ status = mvTsuWinInit(); -+ if(status == MV_OK) -+ status = mvTsuHalInit(coreClock,mode,osHandle); -+ -+ return status; -+} -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,110 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvSysTsh -+#define __INCmvSysTsh -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* includes */ -+#include "ts/mvTsu.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+ -+#define TSU_MAX_DECODE_WIN 4 -+ -+ -+/*******************************************/ -+/* TSU Windows Registers */ -+/*******************************************/ -+#define MV_TSU_WIN_CTRL_REG(win) (TSU_GLOBAL_REG_BASE +0x30 + 0x10 * win) -+#define MV_TSU_WIN_BASE_REG(win) (TSU_GLOBAL_REG_BASE +0x34 + 0x10 * win) -+ -+/* TSU windows control register. */ -+#define TSU_WIN_CTRL_EN_MASK (0x1 << 0) -+#define TSU_WIN_CTRL_TARGET_OFFS 4 -+#define TSU_WIN_CTRL_TARGET_MASK (0xF << TSU_WIN_CTRL_TARGET_OFFS) -+#define TSU_WIN_CTRL_ATTR_OFFS 8 -+#define TSU_WIN_CTRL_ATTR_MASK (0xFF << TSU_WIN_CTRL_ATTR_OFFS) -+#define TSU_WIN_CTRL_SIZE_OFFS 16 -+#define TSU_WIN_CTRL_SIZE_MASK (0xFFFF << TSU_WIN_CTRL_SIZE_OFFS) -+ -+/* TSU windows base register. */ -+#define TSU_WIN_BASE_OFFS 16 -+#define TSU_WIN_BASE_MASK (0xFFFF << TSU_WIN_BASE_OFFS) -+ -+MV_STATUS mvTsuWinInit(void); -+ -+void mvTsuAddrDecShow(void); -+MV_STATUS mvTsuInit(MV_TSU_CORE_CLOCK coreClock, MV_TSU_PORTS_MODE mode, -+ void *osHandle); -+ -+#ifdef __cplusplus -+} -+#endif /* __cplusplus */ -+ -+#endif /* __INCmvTsh */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,497 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "ctrlEnv/sys/mvSysUsb.h" -+ -+MV_TARGET usbAddrDecPrioTab[] = -+{ -+#if defined(MV_INCLUDE_SDRAM_CS0) -+ SDRAM_CS0, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS1) -+ SDRAM_CS1, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS2) -+ SDRAM_CS2, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS3) -+ SDRAM_CS3, -+#endif -+#if defined(MV_INCLUDE_CESA) && defined(USB_UNDERRUN_WA) -+ CRYPT_ENG, -+#endif -+#if defined(MV_INCLUDE_PEX) -+ PEX0_MEM, -+#endif -+ TBL_TERM -+}; -+ -+ -+ -+MV_STATUS mvUsbInit(int dev, MV_BOOL isHost) -+{ -+ MV_STATUS status; -+ -+ status = mvUsbWinInit(dev); -+ if(status != MV_OK) -+ return status; -+ -+ return mvUsbHalInit(dev, isHost); -+} -+ -+ -+/******************************************************************************* -+* usbWinOverlapDetect - Detect USB address windows overlapping -+* -+* DESCRIPTION: -+* An unpredicted behaviur is expected in case USB address decode -+* windows overlapps. -+* This function detects USB address decode windows overlapping of a -+* specified window. The function does not check the window itself for -+* overlapping. The function also skipps disabled address decode windows. -+* -+* INPUT: -+* winNum - address decode window number. -+* pAddrDecWin - An address decode window struct. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data -+* from registers. -+* -+*******************************************************************************/ -+static MV_STATUS usbWinOverlapDetect(int dev, MV_U32 winNum, -+ MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 winNumIndex; -+ MV_DEC_WIN addrDecWin; -+ -+ for(winNumIndex=0; winNumIndex= MV_USB_MAX_ADDR_DECODE_WIN) -+ { -+ mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlapps with current windows */ -+ if (MV_TRUE == usbWinOverlapDetect(dev, winNum, &pDecWin->addrWin)) -+ { -+ mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); -+ return MV_ERROR; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pDecWin->addrWin.baseLow, pDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvUsbWinSet:Error setting USB window %d to "\ -+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, -+ mvCtrlTargetNameGet(pDecWin->target), -+ pDecWin->addrWin.baseLow, -+ pDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ if(MV_OK != mvCtrlAddrDecToParams(pDecWin, &winParams)) -+ { -+ mvOsPrintf("%s: mvCtrlAddrDecToParams Failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ /* set Size, Attributes and TargetID */ -+ sizeReg = (((winParams.targetId << MV_USB_WIN_TARGET_OFFSET) & MV_USB_WIN_TARGET_MASK) | -+ ((winParams.attrib << MV_USB_WIN_ATTR_OFFSET) & MV_USB_WIN_ATTR_MASK) | -+ ((winParams.size << MV_USB_WIN_SIZE_OFFSET) & MV_USB_WIN_SIZE_MASK)); -+ -+#if defined(MV645xx) || defined(MV646xx) -+ /* If window is DRAM with HW cache coherency, make sure bit2 is set */ -+ sizeReg &= ~MV_USB_WIN_BURST_WR_LIMIT_MASK; -+ -+ if((MV_TARGET_IS_DRAM(pDecWin->target)) && -+ (pDecWin->addrWinAttr.cachePolicy != NO_COHERENCY)) -+ { -+ sizeReg |= MV_USB_WIN_BURST_WR_32BIT_LIMIT; -+ } -+ else -+ { -+ sizeReg |= MV_USB_WIN_BURST_WR_NO_LIMIT; -+ } -+#endif /* MV645xx || MV646xx */ -+ -+ if (pDecWin->enable == MV_TRUE) -+ { -+ sizeReg |= MV_USB_WIN_ENABLE_MASK; -+ } -+ else -+ { -+ sizeReg &= ~MV_USB_WIN_ENABLE_MASK; -+ } -+ -+ /* Update Base value */ -+ baseReg = (winParams.baseAddr & MV_USB_WIN_BASE_MASK); -+ -+ MV_REG_WRITE( MV_USB_WIN_CTRL_REG(dev, winNum), sizeReg); -+ MV_REG_WRITE( MV_USB_WIN_BASE_REG(dev, winNum), baseReg); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvUsbWinGet - Get USB peripheral target address window. -+* -+* DESCRIPTION: -+* Get USB peripheral target address window. -+* -+* INPUT: -+* winNum - USB target address decode window number. -+* -+* OUTPUT: -+* pDecWin - USB target window data structure. -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvUsbWinGet(int dev, MV_U32 winNum, MV_DEC_WIN *pDecWin) -+{ -+ MV_DEC_WIN_PARAMS winParam; -+ MV_U32 sizeReg, baseReg; -+ -+ /* Parameter checking */ -+ if (winNum >= MV_USB_MAX_ADDR_DECODE_WIN) -+ { -+ mvOsPrintf("%s (dev=%d): ERR. Invalid winNum %d\n", -+ __FUNCTION__, dev, winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ baseReg = MV_REG_READ( MV_USB_WIN_BASE_REG(dev, winNum) ); -+ sizeReg = MV_REG_READ( MV_USB_WIN_CTRL_REG(dev, winNum) ); -+ -+ /* Check if window is enabled */ -+ if(sizeReg & MV_USB_WIN_ENABLE_MASK) -+ { -+ pDecWin->enable = MV_TRUE; -+ -+ /* Extract window parameters from registers */ -+ winParam.targetId = (sizeReg & MV_USB_WIN_TARGET_MASK) >> MV_USB_WIN_TARGET_OFFSET; -+ winParam.attrib = (sizeReg & MV_USB_WIN_ATTR_MASK) >> MV_USB_WIN_ATTR_OFFSET; -+ winParam.size = (sizeReg & MV_USB_WIN_SIZE_MASK) >> MV_USB_WIN_SIZE_OFFSET; -+ winParam.baseAddr = (baseReg & MV_USB_WIN_BASE_MASK); -+ -+ /* Translate the decode window parameters to address decode struct */ -+ if (MV_OK != mvCtrlParamsToAddrDec(&winParam, pDecWin)) -+ { -+ mvOsPrintf("Failed to translate register parameters to USB address" \ -+ " decode window structure\n"); -+ return MV_ERROR; -+ } -+ } -+ else -+ { -+ pDecWin->enable = MV_FALSE; -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvUsbWinInit - -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvUsbWinInit(int dev) -+{ -+ MV_STATUS status; -+ MV_DEC_WIN usbWin; -+ MV_CPU_DEC_WIN cpuAddrDecWin; -+ int winNum; -+ MV_U32 winPrioIndex = 0; -+ -+ /* First disable all address decode windows */ -+ for(winNum = 0; winNum < MV_USB_MAX_ADDR_DECODE_WIN; winNum++) -+ { -+ MV_REG_BIT_RESET(MV_USB_WIN_CTRL_REG(dev, winNum), MV_USB_WIN_ENABLE_MASK); -+ } -+ -+ /* Go through all windows in user table until table terminator */ -+ winNum = 0; -+ while( (usbAddrDecPrioTab[winPrioIndex] != TBL_TERM) && -+ (winNum < MV_USB_MAX_ADDR_DECODE_WIN) ) -+ { -+ /* first get attributes from CPU If */ -+ status = mvCpuIfTargetWinGet(usbAddrDecPrioTab[winPrioIndex], -+ &cpuAddrDecWin); -+ -+ if(MV_NO_SUCH == status) -+ { -+ winPrioIndex++; -+ continue; -+ } -+ if (MV_OK != status) -+ { -+ mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ if (cpuAddrDecWin.enable == MV_TRUE) -+ { -+ usbWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; -+ usbWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; -+ usbWin.addrWin.size = cpuAddrDecWin.addrWin.size; -+ usbWin.enable = MV_TRUE; -+ usbWin.target = usbAddrDecPrioTab[winPrioIndex]; -+ -+#if defined(MV645xx) || defined(MV646xx) -+ /* Get the default attributes for that target window */ -+ mvCtrlDefAttribGet(usbWin.target, &usbWin.addrWinAttr); -+#endif /* MV645xx || MV646xx */ -+ -+ if(MV_OK != mvUsbWinSet(dev, winNum, &usbWin)) -+ { -+ return MV_ERROR; -+ } -+ winNum++; -+ } -+ winPrioIndex++; -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvUsbAddrDecShow - Print the USB address decode map. -+* -+* DESCRIPTION: -+* This function print the USB address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvUsbAddrDecShow(MV_VOID) -+{ -+ MV_DEC_WIN addrDecWin; -+ int i, winNum; -+ -+ mvOsOutput( "\n" ); -+ mvOsOutput( "USB:\n" ); -+ mvOsOutput( "----\n" ); -+ -+ for(i=0; i= XOR_MAX_ADDR_DEC_WIN) -+ { -+ DB(mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum)); -+ return MV_BAD_PARAM; -+ } -+ if (pAddrDecWin == NULL) -+ { -+ DB(mvOsPrintf("%s: ERR. pAddrDecWin is NULL pointer\n", __FUNCTION__ )); -+ return MV_BAD_PTR; -+ } -+ /* Check if the requested window overlaps with current windows */ -+ if (MV_TRUE == xorWinOverlapDetect(unit, winNum, &pAddrDecWin->addrWin)) -+ { -+ DB(mvOsPrintf("%s: ERR. Window %d overlap\n",__FUNCTION__,winNum)); -+ return MV_ERROR; -+ } -+ -+ xorDecRegs.baseReg = MV_REG_READ(XOR_BASE_ADDR_REG(unit,winNum)); -+ xorDecRegs.sizeReg = MV_REG_READ(XOR_SIZE_MASK_REG(unit,winNum)); -+ -+ /* Get Base Address and size registers values */ -+ if(MV_OK != mvCtrlAddrDecToReg(&pAddrDecWin->addrWin, &xorDecRegs)) -+ { -+ DB(mvOsPrintf("%s: ERR. Invalid addr dec window\n",__FUNCTION__)); -+ return MV_BAD_PARAM; -+ } -+ -+ -+ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); -+ -+ /* set attributes */ -+ xorDecRegs.baseReg &= ~XEBARX_ATTR_MASK; -+ xorDecRegs.baseReg |= targetAttribs.attrib << XEBARX_ATTR_OFFS; -+ /* set target ID */ -+ xorDecRegs.baseReg &= ~XEBARX_TARGET_MASK; -+ xorDecRegs.baseReg |= targetAttribs.targetId << XEBARX_TARGET_OFFS; -+ -+ -+ /* Write to address decode Base Address Register */ -+ MV_REG_WRITE(XOR_BASE_ADDR_REG(unit,winNum), xorDecRegs.baseReg); -+ -+ /* Write to Size Register */ -+ MV_REG_WRITE(XOR_SIZE_MASK_REG(unit,winNum), xorDecRegs.sizeReg); -+ -+ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) -+ { -+ if (pAddrDecWin->enable) -+ { -+ MV_REG_BIT_SET(XOR_WINDOW_CTRL_REG(unit,chan), -+ XEXWCR_WIN_EN_MASK(winNum)); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(XOR_WINDOW_CTRL_REG(unit,chan), -+ XEXWCR_WIN_EN_MASK(winNum)); -+ } -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvXorTargetWinGet - Get xor peripheral target address window. -+* -+* DESCRIPTION: -+* Get xor peripheral target address window. -+* -+* INPUT: -+* winNum - One of the possible XOR memory decode windows. -+* -+* OUTPUT: -+* base - Window base address. -+* size - Window size. -+* enable - window enable/disable. -+* -+* RETURN: -+* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_STATUS mvXorTargetWinGet(MV_U32 unit,MV_U32 winNum, MV_XOR_DEC_WIN *pAddrDecWin) -+{ -+ MV_DEC_REGS xorDecRegs; -+ MV_TARGET_ATTRIB targetAttrib; -+ MV_U32 chan=0,chanWinEn; -+ -+ /* Parameter checking */ -+ if (winNum >= XOR_MAX_ADDR_DEC_WIN) -+ { -+ DB(mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__ , winNum)); -+ return MV_ERROR; -+ } -+ -+ if (NULL == pAddrDecWin) -+ { -+ DB(mvOsPrintf("%s: ERR. pAddrDecWin is NULL pointer\n", __FUNCTION__ )); -+ return MV_BAD_PTR; -+ } -+ -+ chanWinEn = MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,0)) & XEXWCR_WIN_EN_MASK(winNum); -+ -+ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) /* we should scan here all channels per unit */ -+ { -+ /* Check if enable bit is equal for all channels */ -+ if ((MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,chan)) & -+ XEXWCR_WIN_EN_MASK(winNum)) != chanWinEn) -+ { -+ mvOsPrintf("%s: ERR. Window enable field must be equal in " -+ "all channels(chan=%d)\n",__FUNCTION__, chan); -+ return MV_ERROR; -+ } -+ } -+ -+ -+ -+ xorDecRegs.baseReg = MV_REG_READ(XOR_BASE_ADDR_REG(unit,winNum)); -+ xorDecRegs.sizeReg = MV_REG_READ(XOR_SIZE_MASK_REG(unit,winNum)); -+ -+ if (MV_OK != mvCtrlRegToAddrDec(&xorDecRegs, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("%s: ERR. mvCtrlRegToAddrDec failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ /* attrib and targetId */ -+ targetAttrib.attrib = -+ (xorDecRegs.baseReg & XEBARX_ATTR_MASK) >> XEBARX_ATTR_OFFS; -+ targetAttrib.targetId = -+ (xorDecRegs.baseReg & XEBARX_TARGET_MASK) >> XEBARX_TARGET_OFFS; -+ -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ if(chanWinEn) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else pAddrDecWin->enable = MV_FALSE; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvXorTargetWinEnable - Enable/disable a Xor address decode window -+* -+* DESCRIPTION: -+* This function enable/disable a XOR address decode window. -+* if parameter 'enable' == MV_TRUE the routine will enable the -+* window, thus enabling XOR accesses (before enabling the window it is -+* tested for overlapping). Otherwise, the window will be disabled. -+* -+* INPUT: -+* winNum - Decode window number. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_STATUS mvXorTargetWinEnable(MV_U32 unit,MV_U32 winNum, MV_BOOL enable) -+{ -+ MV_XOR_DEC_WIN addrDecWin; -+ MV_U32 chan; -+ -+ /* Parameter checking */ -+ if (winNum >= XOR_MAX_ADDR_DEC_WIN) -+ { -+ DB(mvOsPrintf("%s: ERR. Invalid winNum%d\n", __FUNCTION__, winNum)); -+ return MV_ERROR; -+ } -+ -+ if (enable == MV_TRUE) -+ { -+ /* Get current window */ -+ if (MV_OK != mvXorTargetWinGet(unit,winNum, &addrDecWin)) -+ { -+ DB(mvOsPrintf("%s: ERR. targetWinGet fail\n", __FUNCTION__)); -+ return MV_ERROR; -+ } -+ -+ /* Check for overlapping */ -+ if (MV_TRUE == xorWinOverlapDetect(unit,winNum, &(addrDecWin.addrWin))) -+ { -+ /* Overlap detected */ -+ DB(mvOsPrintf("%s: ERR. Overlap detected\n", __FUNCTION__)); -+ return MV_ERROR; -+ } -+ -+ /* No Overlap. Enable address decode target window */ -+ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) -+ { -+ MV_REG_BIT_SET(XOR_WINDOW_CTRL_REG(unit,chan), -+ XEXWCR_WIN_EN_MASK(winNum)); -+ } -+ -+ } -+ else -+ { -+ /* Disable address decode target window */ -+ -+ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) -+ { -+ MV_REG_BIT_RESET(XOR_WINDOW_CTRL_REG(unit,chan), -+ XEXWCR_WIN_EN_MASK(winNum)); -+ } -+ -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvXorSetProtWinSet - Configure access attributes of a XOR engine -+* to one of the XOR memory windows. -+* -+* DESCRIPTION: -+* Each engine can be configured with access attributes for each of the -+* memory spaces. This function sets access attributes -+* to a given window for the given engine -+* -+* INPUTS: -+* chan - One of the possible engines. -+* winNum - One of the possible XOR memory spaces. -+* access - Protection access rights. -+* write - Write rights. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_STATUS mvXorProtWinSet (MV_U32 unit,MV_U32 chan, MV_U32 winNum, MV_BOOL access, -+ MV_BOOL write) -+{ -+ MV_U32 temp; -+ -+ /* Parameter checking */ -+ if (chan >= MV_XOR_MAX_CHAN_PER_UNIT) -+ { -+ DB(mvOsPrintf("%s: ERR. Invalid chan num %d\n", __FUNCTION__ , chan)); -+ return MV_BAD_PARAM; -+ } -+ if (winNum >= XOR_MAX_ADDR_DEC_WIN) -+ { -+ DB(mvOsPrintf("%s: ERR. Invalid win num %d\n", __FUNCTION__, winNum)); -+ return MV_BAD_PARAM; -+ } -+ -+ temp = MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,chan)) & -+ (~XEXWCR_WIN_ACC_MASK(winNum)); -+ -+ /* if access is disable */ -+ if (!access) -+ { -+ /* disable access */ -+ temp |= XEXWCR_WIN_ACC_NO_ACC(winNum); -+ } -+ /* if access is enable */ -+ else -+ { -+ /* if write is enable */ -+ if (write) -+ { -+ /* enable write */ -+ temp |= XEXWCR_WIN_ACC_RW(winNum); -+ } -+ /* if write is disable */ -+ else -+ { -+ /* disable write */ -+ temp |= XEXWCR_WIN_ACC_RO(winNum); -+ } -+ } -+ MV_REG_WRITE(XOR_WINDOW_CTRL_REG(unit,chan),temp); -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvXorPciRemap - Set XOR remap register for PCI address windows. -+* -+* DESCRIPTION: -+* only Windows 0-3 can be remapped. -+* -+* INPUT: -+* winNum - window number -+* pAddrDecWin - pointer to address space window structure -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_STATUS mvXorPciRemap(MV_U32 unit,MV_U32 winNum, MV_U32 addrHigh) -+{ -+ /* Parameter checking */ -+ if (winNum >= XOR_MAX_REMAP_WIN) -+ { -+ DB(mvOsPrintf("%s: ERR. Invalid win num %d\n", __FUNCTION__, winNum)); -+ return MV_BAD_PARAM; -+ } -+ -+ MV_REG_WRITE(XOR_HIGH_ADDR_REMAP_REG(unit,winNum), addrHigh); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* xorWinOverlapDetect - Detect XOR address windows overlaping -+* -+* DESCRIPTION: -+* An unpredicted behaviour is expected in case XOR address decode -+* windows overlaps. -+* This function detects XOR address decode windows overlaping of a -+* specified window. The function does not check the window itself for -+* overlaping. The function also skipps disabled address decode windows. -+* -+* INPUT: -+* winNum - address decode window number. -+* pAddrDecWin - An address decode window struct. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data -+* from registers. -+* -+*******************************************************************************/ -+static MV_STATUS xorWinOverlapDetect(MV_U32 unit,MV_U32 winNum, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 baseAddrEnableReg; -+ MV_U32 winNumIndex,chan; -+ MV_XOR_DEC_WIN addrDecWin; -+ -+ if (pAddrWin == NULL) -+ { -+ DB(mvOsPrintf("%s: ERR. pAddrWin is NULL pointer\n", __FUNCTION__ )); -+ return MV_BAD_PTR; -+ } -+ -+ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) -+ { -+ /* Read base address enable register. Do not check disabled windows */ -+ baseAddrEnableReg = MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,chan)); -+ -+ for (winNumIndex = 0; winNumIndex < XOR_MAX_ADDR_DEC_WIN; winNumIndex++) -+ { -+ /* Do not check window itself */ -+ if (winNumIndex == winNum) -+ { -+ continue; -+ } -+ -+ /* Do not check disabled windows */ -+ if ((baseAddrEnableReg & XEXWCR_WIN_EN_MASK(winNumIndex)) == 0) -+ { -+ continue; -+ } -+ -+ /* Get window parameters */ -+ if (MV_OK != mvXorTargetWinGet(unit,winNumIndex, &addrDecWin)) -+ { -+ DB(mvOsPrintf("%s: ERR. TargetWinGet failed\n", __FUNCTION__ )); -+ return MV_ERROR; -+ } -+ -+ if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin))) -+ { -+ return MV_TRUE; -+ } -+ } -+ } -+ -+ return MV_FALSE; -+} -+ -+static MV_VOID mvXorAddrDecShowUnit(MV_U32 unit) -+{ -+ MV_XOR_DEC_WIN win; -+ int i; -+ -+ mvOsOutput( "\n" ); -+ mvOsOutput( "XOR %d:\n", unit ); -+ mvOsOutput( "----\n" ); -+ -+ for( i = 0; i < XOR_MAX_ADDR_DEC_WIN; i++ ) -+ { -+ memset( &win, 0, sizeof(MV_XOR_DEC_WIN) ); -+ -+ mvOsOutput( "win%d - ", i ); -+ -+ if( mvXorTargetWinGet(unit, i, &win ) == MV_OK ) -+ { -+ if( win.enable ) -+ { -+ mvOsOutput( "%s base %x, ", -+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); -+ -+ mvSizePrint( win.addrWin.size ); -+ -+ mvOsOutput( "\n" ); -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ } -+ } -+} -+ -+/******************************************************************************* -+* mvXorAddrDecShow - Print the XOR address decode map. -+* -+* DESCRIPTION: -+* This function print the XOR address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvXorAddrDecShow(MV_VOID) -+{ -+ int i; -+ -+ for( i = 0; i < MV_XOR_MAX_UNIT; i++ ) -+ mvXorAddrDecShowUnit(i); -+ -+} -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,140 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCMVSysXorh -+#define __INCMVSysXorh -+ -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+#include "ctrlEnv/sys/mvCpuIf.h" -+ -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+ -+#define XOR_MAX_ADDR_DEC_WIN 8 /* Maximum address decode windows */ -+#define XOR_MAX_REMAP_WIN 4 /* Maximum address arbiter windows */ -+ -+/* XOR Engine Address Decoding Register Map */ -+#define XOR_WINDOW_CTRL_REG(unit,chan) (XOR_UNIT_BASE(unit)+(0x240 + ((chan) * 4))) -+#define XOR_BASE_ADDR_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x250 + ((winNum) * 4))) -+#define XOR_SIZE_MASK_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x270 + ((winNum) * 4))) -+#define XOR_HIGH_ADDR_REMAP_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x290 + ((winNum) * 4))) -+ -+/* XOR Engine [0..1] Window Control Registers (XExWCR) */ -+#define XEXWCR_WIN_EN_OFFS(winNum) (winNum) -+#define XEXWCR_WIN_EN_MASK(winNum) (1 << (XEXWCR_WIN_EN_OFFS(winNum))) -+#define XEXWCR_WIN_EN_ENABLE(winNum) (1 << (XEXWCR_WIN_EN_OFFS(winNum))) -+#define XEXWCR_WIN_EN_DISABLE(winNum) (0 << (XEXWCR_WIN_EN_OFFS(winNum))) -+ -+#define XEXWCR_WIN_ACC_OFFS(winNum) ((2 * winNum) + 16) -+#define XEXWCR_WIN_ACC_MASK(winNum) (3 << (XEXWCR_WIN_ACC_OFFS(winNum))) -+#define XEXWCR_WIN_ACC_NO_ACC(winNum) (0 << (XEXWCR_WIN_ACC_OFFS(winNum))) -+#define XEXWCR_WIN_ACC_RO(winNum) (1 << (XEXWCR_WIN_ACC_OFFS(winNum))) -+#define XEXWCR_WIN_ACC_RW(winNum) (3 << (XEXWCR_WIN_ACC_OFFS(winNum))) -+ -+/* XOR Engine Base Address Registers (XEBARx) */ -+#define XEBARX_TARGET_OFFS (0) -+#define XEBARX_TARGET_MASK (0xF << XEBARX_TARGET_OFFS) -+#define XEBARX_ATTR_OFFS (8) -+#define XEBARX_ATTR_MASK (0xFF << XEBARX_ATTR_OFFS) -+#define XEBARX_BASE_OFFS (16) -+#define XEBARX_BASE_MASK (0xFFFF << XEBARX_BASE_OFFS) -+ -+/* XOR Engine Size Mask Registers (XESMRx) */ -+#define XESMRX_SIZE_MASK_OFFS (16) -+#define XESMRX_SIZE_MASK_MASK (0xFFFF << XESMRX_SIZE_MASK_OFFS) -+ -+/* XOR Engine High Address Remap Register (XEHARRx1) */ -+#define XEHARRX_REMAP_OFFS (0) -+#define XEHARRX_REMAP_MASK (0xFFFFFFFF << XEHARRX_REMAP_OFFS) -+ -+typedef struct _mvXorDecWin -+{ -+ MV_TARGET target; -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+}MV_XOR_DEC_WIN; -+ -+MV_STATUS mvXorInit (MV_VOID); -+MV_STATUS mvXorTargetWinSet(MV_U32 unit, MV_U32 winNum, -+ MV_XOR_DEC_WIN *pAddrDecWin); -+MV_STATUS mvXorTargetWinGet(MV_U32 unit, MV_U32 winNum, -+ MV_XOR_DEC_WIN *pAddrDecWin); -+MV_STATUS mvXorTargetWinEnable(MV_U32 unit, -+ MV_U32 winNum, MV_BOOL enable); -+MV_STATUS mvXorProtWinSet (MV_U32 unit,MV_U32 chan, MV_U32 winNum, MV_BOOL access, -+ MV_BOOL write); -+MV_STATUS mvXorPciRemap(MV_U32 unit, MV_U32 winNum, MV_U32 addrHigh); -+ -+MV_VOID mvXorAddrDecShow(MV_VOID); -+ -+#ifdef __cplusplus -+} -+#endif -+ -+#endif -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,75 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "device/mvDevice.h" -+ -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,74 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvDeviceH -+#define __INCmvDeviceH -+ -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+#include "device/mvDeviceRegs.h" -+ -+ -+#endif /* #ifndef __INCmvDeviceH */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDeviceRegs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDeviceRegs.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDeviceRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDeviceRegs.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,101 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvDeviceRegsH -+#define __INCmvDeviceRegsH -+ -+#ifndef MV_ASMLANGUAGE -+#include "ctrlEnv/mvCtrlEnvLib.h" -+/* This enumerator describes the Marvell controller possible devices that */ -+/* can be connected to its device interface. */ -+typedef enum _mvDevice -+{ -+#if defined(MV_INCLUDE_DEVICE_CS0) -+ DEV_CS0 = 0, /* Device connected to dev CS[0] */ -+#endif -+#if defined(MV_INCLUDE_DEVICE_CS1) -+ DEV_CS1 = 1, /* Device connected to dev CS[1] */ -+#endif -+#if defined(MV_INCLUDE_DEVICE_CS2) -+ DEV_CS2 = 2, /* Device connected to dev CS[2] */ -+#endif -+#if defined(MV_INCLUDE_DEVICE_CS3) -+ DEV_CS3 = 3, /* Device connected to dev CS[2] */ -+#endif -+#if defined(MV_INCLUDE_DEVICE_CS4) -+ DEV_CS4 = 4, /* Device connected to BOOT dev */ -+#endif -+ MV_DEV_MAX_CS = MV_DEVICE_MAX_CS -+}MV_DEVICE; -+ -+ -+#endif /* MV_ASMLANGUAGE */ -+ -+ -+#define NAND_CTRL_REG 0x10470 -+ -+#define NAND_ACTCEBOOT_BIT BIT1 -+ -+ -+#endif /* #ifndef __INCmvDeviceRegsH */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/mvCompVer.txt linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/mvCompVer.txt ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/mvCompVer.txt 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/mvCompVer.txt 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,4 @@ -+Global HAL Version: FEROCEON_HAL_3_1_7 -+Unit HAL Version: 3.1.5 -+Description: This component includes an implementation of the unit HAL drivers -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,211 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+*******************************************************************************/ -+/******************************************************************************* -+* mvOsCpuArchLib.c - Marvell CPU architecture library -+* -+* DESCRIPTION: -+* This library introduce Marvell API for OS dependent CPU architecture -+* APIs. This library introduce single CPU architecture services APKI -+* cross OS. -+* -+* DEPENDENCIES: -+* None. -+* -+*******************************************************************************/ -+ -+/* includes */ -+#include -+#include "mvOs.h" -+ -+static MV_U32 read_p15_c0 (void); -+ -+/* defines */ -+#define ARM_ID_REVISION_OFFS 0 -+#define ARM_ID_REVISION_MASK (0xf << ARM_ID_REVISION_OFFS) -+ -+#define ARM_ID_PART_NUM_OFFS 4 -+#define ARM_ID_PART_NUM_MASK (0xfff << ARM_ID_PART_NUM_OFFS) -+ -+#define ARM_ID_ARCH_OFFS 16 -+#define ARM_ID_ARCH_MASK (0xf << ARM_ID_ARCH_OFFS) -+ -+#define ARM_ID_VAR_OFFS 20 -+#define ARM_ID_VAR_MASK (0xf << ARM_ID_VAR_OFFS) -+ -+#define ARM_ID_ASCII_OFFS 24 -+#define ARM_ID_ASCII_MASK (0xff << ARM_ID_ASCII_OFFS) -+ -+ -+ -+void* mvOsIoCachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, -+ MV_U32 *memHandle) -+{ -+ void *p = kmalloc( size, GFP_KERNEL ); -+ *pPhyAddr = pci_map_single( osHandle, p, 0, PCI_DMA_BIDIRECTIONAL ); -+ return p; -+} -+void* mvOsIoUncachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, -+ MV_U32 *memHandle) -+{ -+ return pci_alloc_consistent( osHandle, size, (dma_addr_t *)pPhyAddr ); -+} -+ -+void mvOsIoUncachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, -+ MV_U32 memHandle) -+{ -+ return pci_free_consistent( osHandle, size, pVirtAddr, (dma_addr_t)phyAddr ); -+} -+ -+void mvOsIoCachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, -+ MV_U32 memHandle ) -+{ -+ return kfree( pVirtAddr ); -+} -+ -+int mvOsRand(void) -+{ -+ int rand; -+ get_random_bytes(&rand, sizeof(rand) ); -+ return rand; -+} -+ -+/******************************************************************************* -+* mvOsCpuVerGet() - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit CPU Revision -+* -+*******************************************************************************/ -+MV_U32 mvOsCpuRevGet( MV_VOID ) -+{ -+ return ((read_p15_c0() & ARM_ID_REVISION_MASK ) >> ARM_ID_REVISION_OFFS); -+} -+/******************************************************************************* -+* mvOsCpuPartGet() - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit CPU Part number -+* -+*******************************************************************************/ -+MV_U32 mvOsCpuPartGet( MV_VOID ) -+{ -+ return ((read_p15_c0() & ARM_ID_PART_NUM_MASK ) >> ARM_ID_PART_NUM_OFFS); -+} -+/******************************************************************************* -+* mvOsCpuArchGet() - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit CPU Architicture number -+* -+*******************************************************************************/ -+MV_U32 mvOsCpuArchGet( MV_VOID ) -+{ -+ return ((read_p15_c0() & ARM_ID_ARCH_MASK ) >> ARM_ID_ARCH_OFFS); -+} -+/******************************************************************************* -+* mvOsCpuVarGet() - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit CPU Variant number -+* -+*******************************************************************************/ -+MV_U32 mvOsCpuVarGet( MV_VOID ) -+{ -+ return ((read_p15_c0() & ARM_ID_VAR_MASK ) >> ARM_ID_VAR_OFFS); -+} -+/******************************************************************************* -+* mvOsCpuAsciiGet() - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit CPU Variant number -+* -+*******************************************************************************/ -+MV_U32 mvOsCpuAsciiGet( MV_VOID ) -+{ -+ return ((read_p15_c0() & ARM_ID_ASCII_MASK ) >> ARM_ID_ASCII_OFFS); -+} -+ -+ -+ -+/* -+static unsigned long read_p15_c0 (void) -+*/ -+/* read co-processor 15, register #0 (ID register) */ -+static MV_U32 read_p15_c0 (void) -+{ -+ MV_U32 value; -+ -+ __asm__ __volatile__( -+ "mrc p15, 0, %0, c0, c0, 0 @ read control reg\n" -+ : "=r" (value) -+ : -+ : "memory"); -+ -+ return value; -+} -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,423 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+*******************************************************************************/ -+#ifndef _MV_OS_LNX_H_ -+#define _MV_OS_LNX_H_ -+ -+ -+#ifdef __KERNEL__ -+/* for kernel space */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "dbg-trace.h" -+ -+extern void mv_early_printk(char *fmt,...); -+ -+#define MV_ASM __asm__ __volatile__ -+#define INLINE inline -+#define MV_TRC_REC TRC_REC -+#define mvOsPrintf printk -+#define mvOsEarlyPrintf mv_early_printk -+#define mvOsOutput printk -+#define mvOsSPrintf sprintf -+#define mvOsMalloc(_size_) kmalloc(_size_,GFP_ATOMIC) -+#define mvOsFree kfree -+#define mvOsMemcpy memcpy -+#define mvOsSleep(_mils_) mdelay(_mils_) -+#define mvOsTaskLock() -+#define mvOsTaskUnlock() -+#define strtol simple_strtoul -+#define mvOsDelay(x) mdelay(x) -+#define mvOsUDelay(x) udelay(x) -+#define mvCopyFromOs copy_from_user -+#define mvCopyToOs copy_to_user -+ -+ -+#include "mvTypes.h" -+#include "mvCommon.h" -+ -+#ifdef MV_NDEBUG -+#define mvOsAssert(cond) -+#else -+#define mvOsAssert(cond) { do { if(!(cond)) { BUG(); } }while(0); } -+#endif /* MV_NDEBUG */ -+ -+#else /* __KERNEL__ */ -+ -+/* for user space applications */ -+#include -+#include -+#include -+#include -+ -+#define INLINE inline -+#define mvOsPrintf printf -+#define mvOsOutput printf -+#define mvOsMalloc(_size_) malloc(_size_) -+#define mvOsFree free -+#define mvOsAssert(cond) assert(cond) -+ -+#endif /* __KERNEL__ */ -+#define mvOsIoVirtToPhy(pDev, pVirtAddr) \ -+ pci_map_single( (pDev), (pVirtAddr), 0, PCI_DMA_BIDIRECTIONAL ) -+ -+#define mvOsCacheClear(pDev, p, size ) \ -+ pci_map_single( (pDev), (p), (size), PCI_DMA_BIDIRECTIONAL) -+ -+#define mvOsCacheFlush(pDev, p, size ) \ -+ pci_map_single( (pDev), (p), (size), PCI_DMA_TODEVICE) -+ -+#define mvOsCacheInvalidate(pDev, p, size) \ -+ pci_map_single( (pDev), (p), (size), PCI_DMA_FROMDEVICE ) -+ -+#define mvOsCacheUnmap(pDev, phys, size) \ -+ pci_unmap_single( (pDev), (dma_addr_t)(phys), (size), PCI_DMA_FROMDEVICE ) -+ -+ -+#define CPU_PHY_MEM(x) (MV_U32)x -+#define CPU_MEMIO_CACHED_ADDR(x) (void*)x -+#define CPU_MEMIO_UNCACHED_ADDR(x) (void*)x -+ -+ -+/* CPU architecture dependent 32, 16, 8 bit read/write IO addresses */ -+#define MV_MEMIO32_WRITE(addr, data) \ -+ ((*((volatile unsigned int*)(addr))) = ((unsigned int)(data))) -+ -+#define MV_MEMIO32_READ(addr) \ -+ ((*((volatile unsigned int*)(addr)))) -+ -+#define MV_MEMIO16_WRITE(addr, data) \ -+ ((*((volatile unsigned short*)(addr))) = ((unsigned short)(data))) -+ -+#define MV_MEMIO16_READ(addr) \ -+ ((*((volatile unsigned short*)(addr)))) -+ -+#define MV_MEMIO8_WRITE(addr, data) \ -+ ((*((volatile unsigned char*)(addr))) = ((unsigned char)(data))) -+ -+#define MV_MEMIO8_READ(addr) \ -+ ((*((volatile unsigned char*)(addr)))) -+ -+ -+/* No Fast Swap implementation (in assembler) for ARM */ -+#define MV_32BIT_LE_FAST(val) MV_32BIT_LE(val) -+#define MV_16BIT_LE_FAST(val) MV_16BIT_LE(val) -+#define MV_32BIT_BE_FAST(val) MV_32BIT_BE(val) -+#define MV_16BIT_BE_FAST(val) MV_16BIT_BE(val) -+ -+/* 32 and 16 bit read/write in big/little endian mode */ -+ -+/* 16bit write in little endian mode */ -+#define MV_MEMIO_LE16_WRITE(addr, data) \ -+ MV_MEMIO16_WRITE(addr, MV_16BIT_LE_FAST(data)) -+ -+/* 16bit read in little endian mode */ -+static __inline MV_U16 MV_MEMIO_LE16_READ(MV_U32 addr) -+{ -+ MV_U16 data; -+ -+ data= (MV_U16)MV_MEMIO16_READ(addr); -+ -+ return (MV_U16)MV_16BIT_LE_FAST(data); -+} -+ -+/* 32bit write in little endian mode */ -+#define MV_MEMIO_LE32_WRITE(addr, data) \ -+ MV_MEMIO32_WRITE(addr, MV_32BIT_LE_FAST(data)) -+ -+/* 32bit read in little endian mode */ -+static __inline MV_U32 MV_MEMIO_LE32_READ(MV_U32 addr) -+{ -+ MV_U32 data; -+ -+ data= (MV_U32)MV_MEMIO32_READ(addr); -+ -+ return (MV_U32)MV_32BIT_LE_FAST(data); -+} -+ -+static __inline void mvOsBCopy(char* srcAddr, char* dstAddr, int byteCount) -+{ -+ while(byteCount != 0) -+ { -+ *dstAddr = *srcAddr; -+ dstAddr++; -+ srcAddr++; -+ byteCount--; -+ } -+} -+ -+static INLINE MV_U64 mvOsDivMod64(MV_U64 divided, MV_U64 divisor, MV_U64* modulu) -+{ -+ MV_U64 division = 0; -+ -+ if(divisor == 1) -+ return divided; -+ -+ while(divided >= divisor) -+ { -+ division++; -+ divided -= divisor; -+ } -+ if (modulu != NULL) -+ *modulu = divided; -+ -+ return division; -+} -+ -+#if defined(MV_BRIDGE_SYNC_REORDER) -+extern MV_U32 *mvUncachedParam; -+ -+static __inline void mvOsBridgeReorderWA(void) -+{ -+ volatile MV_U32 val = 0; -+ -+ val = mvUncachedParam[0]; -+} -+#endif -+ -+ -+/* Flash APIs */ -+#define MV_FL_8_READ MV_MEMIO8_READ -+#define MV_FL_16_READ MV_MEMIO_LE16_READ -+#define MV_FL_32_READ MV_MEMIO_LE32_READ -+#define MV_FL_8_DATA_READ MV_MEMIO8_READ -+#define MV_FL_16_DATA_READ MV_MEMIO16_READ -+#define MV_FL_32_DATA_READ MV_MEMIO32_READ -+#define MV_FL_8_WRITE MV_MEMIO8_WRITE -+#define MV_FL_16_WRITE MV_MEMIO_LE16_WRITE -+#define MV_FL_32_WRITE MV_MEMIO_LE32_WRITE -+#define MV_FL_8_DATA_WRITE MV_MEMIO8_WRITE -+#define MV_FL_16_DATA_WRITE MV_MEMIO16_WRITE -+#define MV_FL_32_DATA_WRITE MV_MEMIO32_WRITE -+ -+ -+/* CPU cache information */ -+#define CPU_I_CACHE_LINE_SIZE 32 /* 2do: replace 32 with linux core macro */ -+#define CPU_D_CACHE_LINE_SIZE 32 /* 2do: replace 32 with linux core macro */ -+ -+#ifdef CONFIG_L2_CACHE_ENABLE -+/* Data cache flush one line */ -+#define mvOsCacheLineFlushInv(handle, addr) \ -+{ \ -+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c14, 1" : : "r" (addr));\ -+ __asm__ __volatile__ ("mcr p15, 1, %0, c15, c10, 1" : : "r" (addr));\ -+ __asm__ __volatile__ ("mcr p15, 0, r0, c7, c10, 4"); \ -+} -+ -+#else -+ -+/* Data cache flush one line */ -+#define mvOsCacheLineFlushInv(handle, addr) \ -+{ \ -+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c14, 1" : : "r" (addr));\ -+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" : : "r" (addr)); \ -+} -+#endif -+ -+#ifdef CONFIG_L2_CACHE_ENABLE -+#define mvOsCacheLineInv(handle,addr) \ -+{ \ -+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c6, 1" : : "r" (addr)); \ -+ __asm__ __volatile__ ("mcr p15, 1, %0, c15, c11, 1" : : "r" (addr)); \ -+} -+#else -+#define mvOsCacheLineInv(handle,addr) \ -+{ \ -+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c6, 1" : : "r" (addr)); \ -+} -+#endif -+ -+#ifdef CONFIG_L2_CACHE_ENABLE -+/* Data cache flush one line */ -+#define mvOsCacheLineFlush(handle, addr) \ -+{ \ -+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 1" : : "r" (addr));\ -+ __asm__ __volatile__ ("mcr p15, 1, %0, c15, c9, 1" : : "r" (addr));\ -+ __asm__ __volatile__ ("mcr p15, 0, r0, c7, c10, 4"); \ -+} -+ -+#else -+/* Data cache flush one line */ -+#define mvOsCacheLineFlush(handle, addr) \ -+{ \ -+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 1" : : "r" (addr));\ -+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" : : "r" (addr)); \ -+} -+#endif -+ -+static __inline void mvOsPrefetch(const void *ptr) -+{ -+#ifdef CONFIG_USE_DSP -+ __asm__ __volatile__( -+ "pld\t%0" -+ : -+ : "o" (*(char *)ptr) -+ : "cc"); -+#else -+ return; -+#endif -+} -+ -+ -+/* Flush CPU pipe */ -+#define CPU_PIPE_FLUSH -+ -+ -+ -+ -+ -+/* register manipulations */ -+ -+/****************************************************************************** -+* This debug function enable the write of each register that u-boot access to -+* to an array in the DRAM, the function record only MV_REG_WRITE access. -+* The function could not be operate when booting from flash. -+* In order to print the array we use the printreg command. -+******************************************************************************/ -+/* #define REG_DEBUG */ -+#if defined(REG_DEBUG) -+extern int reg_arry[2048][2]; -+extern int reg_arry_index; -+#endif -+ -+/* Marvell controller register read/write macros */ -+#define MV_REG_VALUE(offset) \ -+ (MV_MEMIO32_READ((INTER_REGS_BASE | (offset)))) -+ -+#define MV_REG_READ(offset) \ -+ (MV_MEMIO_LE32_READ(INTER_REGS_BASE | (offset))) -+ -+#if defined(REG_DEBUG) -+#define MV_REG_WRITE(offset, val) \ -+ MV_MEMIO_LE32_WRITE((INTER_REGS_BASE | (offset)), (val)); \ -+ { \ -+ reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\ -+ reg_arry[reg_arry_index][1] = (val);\ -+ reg_arry_index++;\ -+ } -+#else -+#define MV_REG_WRITE(offset, val) \ -+ MV_MEMIO_LE32_WRITE((INTER_REGS_BASE | (offset)), (val)); -+#endif -+ -+#define MV_REG_BYTE_READ(offset) \ -+ (MV_MEMIO8_READ((INTER_REGS_BASE | (offset)))) -+ -+#if defined(REG_DEBUG) -+#define MV_REG_BYTE_WRITE(offset, val) \ -+ MV_MEMIO8_WRITE((INTER_REGS_BASE | (offset)), (val)); \ -+ { \ -+ reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\ -+ reg_arry[reg_arry_index][1] = (val);\ -+ reg_arry_index++;\ -+ } -+#else -+#define MV_REG_BYTE_WRITE(offset, val) \ -+ MV_MEMIO8_WRITE((INTER_REGS_BASE | (offset)), (val)) -+#endif -+ -+#if defined(REG_DEBUG) -+#define MV_REG_BIT_SET(offset, bitMask) \ -+ (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ -+ (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) | \ -+ MV_32BIT_LE_FAST(bitMask)))); \ -+ { \ -+ reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\ -+ reg_arry[reg_arry_index][1] = (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)));\ -+ reg_arry_index++;\ -+ } -+#else -+#define MV_REG_BIT_SET(offset, bitMask) \ -+ (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ -+ (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) | \ -+ MV_32BIT_LE_FAST(bitMask)))) -+#endif -+ -+#if defined(REG_DEBUG) -+#define MV_REG_BIT_RESET(offset,bitMask) \ -+ (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ -+ (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) & \ -+ MV_32BIT_LE_FAST(~bitMask)))); \ -+ { \ -+ reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\ -+ reg_arry[reg_arry_index][1] = (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)));\ -+ reg_arry_index++;\ -+ } -+#else -+#define MV_REG_BIT_RESET(offset,bitMask) \ -+ (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ -+ (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) & \ -+ MV_32BIT_LE_FAST(~bitMask)))) -+#endif -+ -+ -+ -+/* ARM architecture APIs */ -+MV_U32 mvOsCpuRevGet (MV_VOID); -+MV_U32 mvOsCpuPartGet (MV_VOID); -+MV_U32 mvOsCpuArchGet (MV_VOID); -+MV_U32 mvOsCpuVarGet (MV_VOID); -+MV_U32 mvOsCpuAsciiGet (MV_VOID); -+ -+/* Other APIs */ -+void* mvOsIoCachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, MV_U32 *memHandle); -+void* mvOsIoUncachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, MV_U32 *memHandle ); -+void mvOsIoUncachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, MV_U32 memHandle ); -+void mvOsIoCachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, MV_U32 memHandle ); -+int mvOsRand(void); -+ -+#endif /* _MV_OS_LNX_H_ */ -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOsSata.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/linux_oss/mvOsSata.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOsSata.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/linux_oss/mvOsSata.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,158 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+*******************************************************************************/ -+/******************************************************************************* -+* mvOsLinux.h - O.S. interface header file for Linux -+* -+* DESCRIPTION: -+* This header file contains OS dependent definition under Linux -+* -+* DEPENDENCIES: -+* Linux kernel header files. -+* -+* FILE REVISION NUMBER: -+* $Revision: 1.1 $ -+*******************************************************************************/ -+ -+#ifndef __INCmvOsLinuxh -+#define __INCmvOsLinuxh -+ -+/* Includes */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include "mvOs.h" -+ -+ -+/* Definitions */ -+#define MV_DEFAULT_QUEUE_DEPTH 2 -+#define MV_SATA_SUPPORT_EDMA_SINGLE_DATA_REGION -+#define MV_SATA_SUPPORT_GEN2E_128_QUEUE_LEN -+ -+#ifdef CONFIG_MV88F6082 -+ #define MV_SATA_OVERRIDE_SW_QUEUE_SIZE -+ #define MV_SATA_REQUESTED_SW_QUEUE_SIZE 2 -+ #undef MV_SATA_SUPPORT_GEN2E_128_QUEUE_LEN -+#endif -+ -+/* System dependent macro for flushing CPU write cache */ -+#if defined (MV_BRIDGE_SYNC_REORDER) -+#define MV_CPU_WRITE_BUFFER_FLUSH() do { \ -+ wmb(); \ -+ mvOsBridgeReorderWA(); \ -+ } while (0) -+#else -+#define MV_CPU_WRITE_BUFFER_FLUSH() wmb() -+#endif /* CONFIG_MV78XX0 */ -+ -+/* System dependent little endian from / to CPU conversions */ -+#define MV_CPU_TO_LE16(x) cpu_to_le16(x) -+#define MV_CPU_TO_LE32(x) cpu_to_le32(x) -+ -+#define MV_LE16_TO_CPU(x) le16_to_cpu(x) -+#define MV_LE32_TO_CPU(x) le32_to_cpu(x) -+ -+#ifdef __BIG_ENDIAN_BITFIELD -+#define MV_BIG_ENDIAN_BITFIELD -+#endif -+ -+/* System dependent register read / write in byte/word/dword variants */ -+#define MV_REG_WRITE_BYTE(base, offset, val) writeb(val, base + offset) -+#define MV_REG_WRITE_WORD(base, offset, val) writew(val, base + offset) -+#define MV_REG_WRITE_DWORD(base, offset, val) writel(val, base + offset) -+#define MV_REG_READ_BYTE(base, offset) readb(base + offset) -+#define MV_REG_READ_WORD(base, offset) readw(base + offset) -+#define MV_REG_READ_DWORD(base, offset) readl(base + offset) -+ -+ -+/* Typedefs */ -+ -+/* System dependant typedefs */ -+typedef void *MV_VOID_PTR; -+typedef u32 *MV_U32_PTR; -+typedef u16 *MV_U16_PTR; -+typedef u8 *MV_U8_PTR; -+typedef char *MV_CHAR_PTR; -+typedef void *MV_BUS_ADDR_T; -+typedef unsigned long MV_CPU_FLAGS; -+ -+ -+/* Structures */ -+/* System dependent structure */ -+typedef struct mvOsSemaphore -+{ -+ int notUsed; -+} MV_OS_SEMAPHORE; -+ -+ -+/* Functions (User implemented)*/ -+ -+/* Semaphore init, take and release */ -+#define mvOsSemInit(x) MV_TRUE -+#define mvOsSemTake(x) -+#define mvOsSemRelease(x) -+ -+/* Interrupt masking and unmasking functions */ -+MV_CPU_FLAGS mvOsSaveFlagsAndMaskCPUInterrupts(MV_VOID); -+MV_VOID mvOsRestoreFlags(MV_CPU_FLAGS); -+ -+/* Delay function in micro seconds resolution */ -+void mvMicroSecondsDelay(MV_VOID_PTR, MV_U32); -+ -+/* Typedefs */ -+typedef enum mvBoolean -+{ -+ MV_SFALSE, MV_STRUE -+} MV_BOOLEAN; -+ -+/* System logging function */ -+#include "mvLog.h" -+/* Enable READ/WRITE Long SCSI command only when driver is compiled for debugging */ -+#ifdef MV_LOGGER -+#define MV_SATA_SUPPORT_READ_WRITE_LONG -+#endif -+ -+#define MV_IAL_LOG_ID 3 -+ -+#endif /* __INCmvOsLinuxh */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mvSysHwConfig.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mvSysHwConfig.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mvSysHwConfig.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mvSysHwConfig.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,375 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+ -+*******************************************************************************/ -+/******************************************************************************* -+* mvSysHwCfg.h - Marvell system HW configuration file -+* -+* DESCRIPTION: -+* None. -+* -+* DEPENDENCIES: -+* None. -+* -+*******************************************************************************/ -+ -+#ifndef __INCmvSysHwConfigh -+#define __INCmvSysHwConfigh -+ -+#include "../../../../include/linux/autoconf.h" -+ -+#define CONFIG_MARVELL 1 -+ -+/* includes */ -+#define _1K 0x00000400 -+#define _4K 0x00001000 -+#define _8K 0x00002000 -+#define _16K 0x00004000 -+#define _32K 0x00008000 -+#define _64K 0x00010000 -+#define _128K 0x00020000 -+#define _256K 0x00040000 -+#define _512K 0x00080000 -+ -+#define _1M 0x00100000 -+#define _2M 0x00200000 -+#define _4M 0x00400000 -+#define _8M 0x00800000 -+#define _16M 0x01000000 -+#define _32M 0x02000000 -+#define _64M 0x04000000 -+#define _128M 0x08000000 -+#define _256M 0x10000000 -+#define _512M 0x20000000 -+ -+#define _1G 0x40000000 -+#define _2G 0x80000000 -+ -+/****************************************/ -+/* Soc supporeted Units definitions */ -+/****************************************/ -+ -+#ifdef CONFIG_MV_INCLUDE_PEX -+#define MV_INCLUDE_PEX -+#endif -+#ifdef CONFIG_MV_INCLUDE_TWSI -+#define MV_INCLUDE_TWSI -+#endif -+#ifdef CONFIG_MV_INCLUDE_CESA -+#define MV_INCLUDE_CESA -+#endif -+#ifdef CONFIG_MV_INCLUDE_GIG_ETH -+#define MV_INCLUDE_GIG_ETH -+#endif -+#ifdef CONFIG_MV_INCLUDE_INTEG_SATA -+#define MV_INCLUDE_INTEG_SATA -+#define MV_INCLUDE_SATA -+#endif -+#ifdef CONFIG_MV_INCLUDE_USB -+#define MV_INCLUDE_USB -+#define MV_USB_VOLTAGE_FIX -+#endif -+#ifdef CONFIG_MV_INCLUDE_NAND -+#define MV_INCLUDE_NAND -+#endif -+#ifdef CONFIG_MV_INCLUDE_TDM -+#define MV_INCLUDE_TDM -+#endif -+#ifdef CONFIG_MV_INCLUDE_XOR -+#define MV_INCLUDE_XOR -+#endif -+#ifdef CONFIG_MV_INCLUDE_TWSI -+#define MV_INCLUDE_TWSI -+#endif -+#ifdef CONFIG_MV_INCLUDE_UART -+#define MV_INCLUDE_UART -+#endif -+#ifdef CONFIG_MV_INCLUDE_SPI -+#define MV_INCLUDE_SPI -+#endif -+#ifdef CONFIG_MV_INCLUDE_SFLASH_MTD -+#define MV_INCLUDE_SFLASH_MTD -+#endif -+#ifdef CONFIG_MV_INCLUDE_AUDIO -+#define MV_INCLUDE_AUDIO -+#endif -+#ifdef CONFIG_MV_INCLUDE_TS -+#define MV_INCLUDE_TS -+#endif -+#ifdef CONFIG_MV_INCLUDE_SDIO -+#define MV_INCLUDE_SDIO -+#endif -+ -+ -+/* NAND flash stuff */ -+#ifdef CONFIG_MV_NAND_BOOT -+#define MV_NAND_BOOT -+#endif -+#ifdef CONFIG_MV_NAND -+#define MV_NAND -+#endif -+ -+/* SPI flash stuff */ -+#ifdef CONFIG_MV_SPI_BOOT -+#define MV_SPI_BOOT -+#endif -+ -+ -+/****************************************************************/ -+/************* General configuration ********************/ -+/****************************************************************/ -+ -+/* Enable Clock Power Control */ -+#define MV_INCLUDE_CLK_PWR_CNTRL -+ -+/* Disable the DEVICE BAR in the PEX */ -+#define MV_DISABLE_PEX_DEVICE_BAR -+ -+/* Allow the usage of early printings during initialization */ -+#define MV_INCLUDE_EARLY_PRINTK -+ -+/****************************************************************/ -+/************* NFP configuration ********************************/ -+/****************************************************************/ -+#define MV_NFP_SEC_Q_SIZE 64 -+#define MV_NFP_SEC_REQ_Q_SIZE 1000 -+ -+ -+ -+/****************************************************************/ -+/************* CESA configuration ********************/ -+/****************************************************************/ -+ -+#ifdef MV_INCLUDE_CESA -+ -+#define MV_CESA_MAX_CHAN 4 -+ -+/* Use 2K of SRAM */ -+#define MV_CESA_MAX_BUF_SIZE 1600 -+ -+#endif /* MV_INCLUDE_CESA */ -+ -+#if defined(CONFIG_MV_INCLUDE_GIG_ETH) -+ -+#ifdef CONFIG_MV_NFP_STATS -+#define MV_FP_STATISTICS -+#else -+#undef MV_FP_STATISTICS -+#endif -+/* Default configuration for SKB_REUSE: 0 - Disabled, 1 - Enabled */ -+#define MV_ETH_SKB_REUSE_DEFAULT 1 -+/* Default configuration for TX_EN workaround: 0 - Disabled, 1 - Enabled */ -+#define MV_ETH_TX_EN_DEFAULT 0 -+ -+/* un-comment if you want to perform tx_done from within the poll function */ -+/* #define ETH_TX_DONE_ISR */ -+ -+/* put descriptors in uncached memory */ -+/* #define ETH_DESCR_UNCACHED */ -+ -+/* Descriptors location: DRAM/internal-SRAM */ -+#define ETH_DESCR_IN_SDRAM -+#undef ETH_DESCR_IN_SRAM /* No integrated SRAM in 88Fxx81 devices */ -+ -+#if defined(ETH_DESCR_IN_SRAM) -+#if defined(ETH_DESCR_UNCACHED) -+ #define ETH_DESCR_CONFIG_STR "Uncached descriptors in integrated SRAM" -+#else -+ #define ETH_DESCR_CONFIG_STR "Cached descriptors in integrated SRAM" -+#endif -+#elif defined(ETH_DESCR_IN_SDRAM) -+#if defined(ETH_DESCR_UNCACHED) -+ #define ETH_DESCR_CONFIG_STR "Uncached descriptors in DRAM" -+#else -+ #define ETH_DESCR_CONFIG_STR "Cached descriptors in DRAM" -+#endif -+#else -+ #error "Ethernet descriptors location undefined" -+#endif /* ETH_DESCR_IN_SRAM or ETH_DESCR_IN_SDRAM*/ -+ -+/* SW Sync-Barrier: not relevant for 88fxx81*/ -+/* Reasnable to define this macro when descriptors in SRAM and buffers in DRAM */ -+/* In RX the CPU theoretically might see himself as the descriptor owner, */ -+/* although the buffer hadn't been written to DRAM yet. Performance cost. */ -+/* #define INCLUDE_SYNC_BARR */ -+ -+/* Buffers cache coherency method (buffers in DRAM) */ -+#ifndef MV_CACHE_COHER_SW -+/* Taken from mvCommon.h */ -+/* Memory uncached, HW or SW cache coherency is not needed */ -+#define MV_UNCACHED 0 -+/* Memory cached, HW cache coherency supported in WriteThrough mode */ -+#define MV_CACHE_COHER_HW_WT 1 -+/* Memory cached, HW cache coherency supported in WriteBack mode */ -+#define MV_CACHE_COHER_HW_WB 2 -+/* Memory cached, No HW cache coherency, Cache coherency must be in SW */ -+#define MV_CACHE_COHER_SW 3 -+ -+#endif -+ -+/* DRAM cache coherency configuration */ -+#define MV_CACHE_COHERENCY MV_CACHE_COHER_SW -+ -+ -+#define ETHER_DRAM_COHER MV_CACHE_COHER_SW /* No HW coherency in 88Fxx81 devices */ -+ -+#if (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WB) -+ #define ETH_SDRAM_CONFIG_STR "DRAM HW cache coherency (write-back)" -+#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WT) -+ #define ETH_SDRAM_CONFIG_STR "DRAM HW cache coherency (write-through)" -+#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) -+ #define ETH_SDRAM_CONFIG_STR "DRAM SW cache-coherency" -+#elif (ETHER_DRAM_COHER == MV_UNCACHED) -+# define ETH_SDRAM_CONFIG_STR "DRAM uncached" -+#else -+ #error "Ethernet-DRAM undefined" -+#endif /* ETHER_DRAM_COHER */ -+ -+ -+/****************************************************************/ -+/************* Ethernet driver configuration ********************/ -+/****************************************************************/ -+ -+/* port's default queueus */ -+#define ETH_DEF_TXQ 0 -+#define ETH_DEF_RXQ 0 -+ -+#define MV_ETH_RX_Q_NUM CONFIG_MV_ETH_RX_Q_NUM -+#define MV_ETH_TX_Q_NUM CONFIG_MV_ETH_TX_Q_NUM -+ -+/* interrupt coalescing setting */ -+#define ETH_TX_COAL 200 -+#define ETH_RX_COAL 200 -+ -+/* Checksum offloading */ -+#define TX_CSUM_OFFLOAD -+#define RX_CSUM_OFFLOAD -+ -+#endif /* CONFIG_MV_INCLUDE_GIG_ETH */ -+ -+/****************************************************************/ -+/*************** Telephony configuration ************************/ -+/****************************************************************/ -+#if defined(CONFIG_MV_TDM_LINEAR_MODE) -+ #define MV_TDM_LINEAR_MODE -+#elif defined(CONFIG_MV_TDM_ULAW_MODE) -+ #define MV_TDM_ULAW_MODE -+#endif -+ -+#if defined(CONFIG_MV_TDM_5CHANNELS) -+ #define MV_TDM_5CHANNELS -+#endif -+ -+#if defined(CONFIG_MV_TDM_USE_EXTERNAL_PCLK_SOURCE) -+ #define MV_TDM_USE_EXTERNAL_PCLK_SOURCE -+#endif -+ -+/* We use the following registers to store DRAM interface pre configuration */ -+/* auto-detection results */ -+/* IMPORTANT: We are using mask register for that purpose. Before writing */ -+/* to units mask register, make sure main maks register is set to disable */ -+/* all interrupts. */ -+#define DRAM_BUF_REG0 0x30810 /* sdram bank 0 size */ -+#define DRAM_BUF_REG1 0x30820 /* sdram config */ -+#define DRAM_BUF_REG2 0x30830 /* sdram mode */ -+#define DRAM_BUF_REG3 0x308c4 /* dunit control low */ -+#define DRAM_BUF_REG4 0x60a90 /* sdram address control */ -+#define DRAM_BUF_REG5 0x60a94 /* sdram timing control low */ -+#define DRAM_BUF_REG6 0x60a98 /* sdram timing control high */ -+#define DRAM_BUF_REG7 0x60a9c /* sdram ODT control low */ -+#define DRAM_BUF_REG8 0x60b90 /* sdram ODT control high */ -+#define DRAM_BUF_REG9 0x60b94 /* sdram Dunit ODT control */ -+#define DRAM_BUF_REG10 0x60b98 /* sdram Extended Mode */ -+#define DRAM_BUF_REG11 0x60b9c /* sdram Ddr2 Time Low Reg */ -+#define DRAM_BUF_REG12 0x60a00 /* sdram Ddr2 Time High Reg */ -+#define DRAM_BUF_REG13 0x60a04 /* dunit Ctrl High */ -+#define DRAM_BUF_REG14 0x60b00 /* sdram second DIMM exist */ -+ -+/* Following the pre-configuration registers default values restored after */ -+/* auto-detection is done */ -+#define DRAM_BUF_REG_DV 0 -+ -+/* System Mapping */ -+#define SDRAM_CS0_BASE 0x00000000 -+#define SDRAM_CS0_SIZE _256M -+ -+#define SDRAM_CS1_BASE 0x10000000 -+#define SDRAM_CS1_SIZE _256M -+ -+#define SDRAM_CS2_BASE 0x20000000 -+#define SDRAM_CS2_SIZE _256M -+ -+#define SDRAM_CS3_BASE 0x30000000 -+#define SDRAM_CS3_SIZE _256M -+ -+/* PEX */ -+#define PEX0_MEM_BASE 0xe8000000 -+#define PEX0_MEM_SIZE _128M -+ -+#define PEX0_IO_BASE 0xf2000000 -+#define PEX0_IO_SIZE _1M -+ -+/* Device Chip Selects */ -+#define NFLASH_CS_BASE 0xfa000000 -+#define NFLASH_CS_SIZE _2M -+ -+#define SPI_CS_BASE 0xf4000000 -+#define SPI_CS_SIZE _16M -+ -+#define CRYPT_ENG_BASE 0xf0000000 -+#define CRYPT_ENG_SIZE _2M -+ -+#define BOOTDEV_CS_BASE 0xff800000 -+#define BOOTDEV_CS_SIZE _8M -+ -+/* CS2 - BOOTROM */ -+#define DEVICE_CS2_BASE 0xff900000 -+#define DEVICE_CS2_SIZE _1M -+ -+/* PEX Work arround */ -+/* the target we will use for the workarround */ -+#define PEX_CONFIG_RW_WA_TARGET PEX0_MEM -+/*a flag that indicates if we are going to use the -+size and base of the target we using for the workarround -+window */ -+#define PEX_CONFIG_RW_WA_USE_ORIGINAL_WIN_VALUES 1 -+/* if the above flag is 0 then the following values -+will be used for the workarround window base and size, -+otherwise the following defines will be ignored */ -+#define PEX_CONFIG_RW_WA_BASE 0xF3000000 -+#define PEX_CONFIG_RW_WA_SIZE _16M -+ -+/* Internal registers: size is defined in Controllerenvironment */ -+#define INTER_REGS_BASE 0xFEE00000 -+ -+/* DRAM detection stuff */ -+#define MV_DRAM_AUTO_SIZE -+ -+/* Board clock detection */ -+#define TCLK_AUTO_DETECT /* Use Tclk auto detection */ -+#define SYSCLK_AUTO_DETECT /* Use SysClk auto detection */ -+#define PCLCK_AUTO_DETECT /* Use PClk auto detection */ -+#define L2CLK_AUTO_DETECT /* Use L2Clk auto detection */ -+ -+/* PEX-PCI\PCI-PCI Bridge*/ -+#define PCI0_IF_PTP 0 /* Bridge exist on pciIf0*/ -+ -+ -+ -+#endif /* __INCmvSysHwConfigh */ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,376 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "mvCntmr.h" -+#include "cpu/mvCpu.h" -+ -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+extern unsigned int whoAmI(void); -+ -+/******************************************************************************* -+* mvCntmrLoad - -+* -+* DESCRIPTION: -+* Load an init Value to a given counter/timer -+* -+* INPUT: -+* countNum - counter number -+* value - value to be loaded -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess -+*******************************************************************************/ -+MV_STATUS mvCntmrLoad(MV_U32 countNum, MV_U32 value) -+{ -+ if (countNum >= MV_CNTMR_MAX_COUNTER ) -+ { -+ -+ mvOsPrintf(("mvCntmrLoad: Err. Illigal counter number \n")); -+ return MV_BAD_PARAM;; -+ -+ } -+ -+ MV_REG_WRITE(CNTMR_RELOAD_REG(countNum),value); -+ MV_REG_WRITE(CNTMR_VAL_REG(countNum),value); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCntmrRead - -+* -+* DESCRIPTION: -+* Returns the value of the given Counter/Timer -+* -+* INPUT: -+* countNum - counter number -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_U32 counter value -+*******************************************************************************/ -+MV_U32 mvCntmrRead(MV_U32 countNum) -+{ -+ return MV_REG_READ(CNTMR_VAL_REG(countNum)); -+} -+ -+/******************************************************************************* -+* mvCntmrWrite - -+* -+* DESCRIPTION: -+* Returns the value of the given Counter/Timer -+* -+* INPUT: -+* countNum - counter number -+* countVal - value to write -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None -+*******************************************************************************/ -+void mvCntmrWrite(MV_U32 countNum,MV_U32 countVal) -+{ -+ MV_REG_WRITE(CNTMR_VAL_REG(countNum),countVal); -+} -+ -+/******************************************************************************* -+* mvCntmrCtrlSet - -+* -+* DESCRIPTION: -+* Set the Control to a given counter/timer -+* -+* INPUT: -+* countNum - counter number -+* pCtrl - pointer to MV_CNTMR_CTRL structure -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess -+*******************************************************************************/ -+MV_STATUS mvCntmrCtrlSet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl) -+{ -+ MV_U32 cntmrCtrl; -+ -+ if (countNum >= MV_CNTMR_MAX_COUNTER ) -+ { -+ -+ DB(mvOsPrintf(("mvCntmrCtrlSet: Err. Illigal counter number \n"))); -+ return MV_BAD_PARAM;; -+ -+ } -+ -+ /* read control register */ -+ cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG); -+ -+ -+ if (pCtrl->enable) /* enable counter\timer */ -+ { -+ cntmrCtrl |= CTCR_ARM_TIMER_EN(countNum); -+ } -+ else /* disable counter\timer */ -+ { -+ cntmrCtrl &= ~CTCR_ARM_TIMER_EN(countNum); -+ } -+ -+ if ( pCtrl->autoEnable ) /* Auto mode */ -+ { -+ cntmrCtrl |= CTCR_ARM_TIMER_AUTO_EN(countNum); -+ -+ } -+ else /* no auto mode */ -+ { -+ cntmrCtrl &= ~CTCR_ARM_TIMER_AUTO_EN(countNum); -+ } -+ -+ MV_REG_WRITE(CNTMR_CTRL_REG,cntmrCtrl); -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvCntmrCtrlGet - -+* -+* DESCRIPTION: -+* Get the Control value of a given counter/timer -+* -+* INPUT: -+* countNum - counter number -+* pCtrl - pointer to MV_CNTMR_CTRL structure -+* -+* OUTPUT: -+* Counter\Timer control value -+* -+* RETURN: -+* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess -+*******************************************************************************/ -+MV_STATUS mvCntmrCtrlGet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl) -+{ -+ MV_U32 cntmrCtrl; -+ -+ if (countNum >= MV_CNTMR_MAX_COUNTER ) -+ { -+ DB(mvOsPrintf(("mvCntmrCtrlGet: Err. Illigal counter number \n"))); -+ return MV_BAD_PARAM;; -+ } -+ -+ /* read control register */ -+ cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG); -+ -+ /* enable counter\timer */ -+ if (cntmrCtrl & CTCR_ARM_TIMER_EN(countNum)) -+ { -+ pCtrl->enable = MV_TRUE; -+ } -+ else -+ { -+ pCtrl->enable = MV_FALSE; -+ } -+ -+ /* counter mode */ -+ if (cntmrCtrl & CTCR_ARM_TIMER_AUTO_EN(countNum)) -+ { -+ pCtrl->autoEnable = MV_TRUE; -+ } -+ else -+ { -+ pCtrl->autoEnable = MV_FALSE; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCntmrEnable - -+* -+* DESCRIPTION: -+* Set the Enable-Bit to logic '1' ==> starting the counter -+* -+* INPUT: -+* countNum - counter number -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess -+*******************************************************************************/ -+MV_STATUS mvCntmrEnable(MV_U32 countNum) -+{ -+ MV_U32 cntmrCtrl; -+ -+ if (countNum >= MV_CNTMR_MAX_COUNTER ) -+ { -+ -+ DB(mvOsPrintf(("mvCntmrEnable: Err. Illigal counter number \n"))); -+ return MV_BAD_PARAM;; -+ -+ } -+ -+ /* read control register */ -+ cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG); -+ -+ /* enable counter\timer */ -+ cntmrCtrl |= CTCR_ARM_TIMER_EN(countNum); -+ -+ -+ MV_REG_WRITE(CNTMR_CTRL_REG,cntmrCtrl); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCntmrDisable - -+* -+* DESCRIPTION: -+* Stop the counter/timer running, and returns its Value -+* -+* INPUT: -+* countNum - counter number -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_U32 counter\timer value -+*******************************************************************************/ -+MV_STATUS mvCntmrDisable(MV_U32 countNum) -+{ -+ MV_U32 cntmrCtrl; -+ -+ if (countNum >= MV_CNTMR_MAX_COUNTER ) -+ { -+ -+ DB(mvOsPrintf(("mvCntmrDisable: Err. Illigal counter number \n"))); -+ return MV_BAD_PARAM;; -+ -+ } -+ -+ /* read control register */ -+ cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG); -+ -+ /* disable counter\timer */ -+ cntmrCtrl &= ~CTCR_ARM_TIMER_EN(countNum); -+ -+ MV_REG_WRITE(CNTMR_CTRL_REG,cntmrCtrl); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCntmrStart - -+* -+* DESCRIPTION: -+* Combined all the sub-operations above to one function: Load,setMode,Enable -+* -+* INPUT: -+* countNum - counter number -+* value - value of the counter\timer to be set -+* pCtrl - pointer to MV_CNTMR_CTRL structure -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess -+*******************************************************************************/ -+MV_STATUS mvCntmrStart(MV_U32 countNum, MV_U32 value, -+ MV_CNTMR_CTRL *pCtrl) -+{ -+ -+ if (countNum >= MV_CNTMR_MAX_COUNTER ) -+ { -+ -+ mvOsPrintf(("mvCntmrDisable: Err. Illigal counter number \n")); -+ return MV_BAD_PARAM;; -+ -+ } -+ -+ /* load value onto counter\timer */ -+ mvCntmrLoad(countNum,value); -+ -+ /* set the counter to load in the first time */ -+ mvCntmrWrite(countNum,value); -+ -+ /* set control for timer \ cunter and enable */ -+ mvCntmrCtrlSet(countNum,pCtrl); -+ -+ return MV_OK; -+} -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,121 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvTmrWtdgh -+#define __INCmvTmrWtdgh -+ -+/* includes */ -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "cntmr/mvCntmrRegs.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+ -+ -+/* This enumerator describe counters\watchdog numbers */ -+typedef enum _mvCntmrID -+{ -+ TIMER0 = 0, -+ TIMER1, -+ WATCHDOG, -+ TIMER2, -+ TIMER3, -+}MV_CNTMR_ID; -+ -+ -+/* Counter / Timer control structure */ -+typedef struct _mvCntmrCtrl -+{ -+ MV_BOOL enable; /* enable */ -+ MV_BOOL autoEnable; /* counter/Timer */ -+}MV_CNTMR_CTRL; -+ -+ -+/* Functions */ -+ -+/* Load an init Value to a given counter/timer */ -+MV_STATUS mvCntmrLoad(MV_U32 countNum, MV_U32 value); -+ -+/* Returns the value of the given Counter/Timer */ -+MV_U32 mvCntmrRead(MV_U32 countNum); -+ -+/* Write a value of the given Counter/Timer */ -+void mvCntmrWrite(MV_U32 countNum,MV_U32 countVal); -+ -+/* Set the Control to a given counter/timer */ -+MV_STATUS mvCntmrCtrlSet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl); -+ -+/* Get the value of a given counter/timer */ -+MV_STATUS mvCntmrCtrlGet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl); -+ -+/* Set the Enable-Bit to logic '1' ==> starting the counter. */ -+MV_STATUS mvCntmrEnable(MV_U32 countNum); -+ -+/* Stop the counter/timer running, and returns its Value. */ -+MV_STATUS mvCntmrDisable(MV_U32 countNum); -+ -+/* Combined all the sub-operations above to one function: Load,setMode,Enable */ -+MV_STATUS mvCntmrStart(MV_U32 countNum, MV_U32 value, -+ MV_CNTMR_CTRL *pCtrl); -+ -+#endif /* __INCmvTmrWtdgh */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmrRegs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmrRegs.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmrRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmrRegs.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,121 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvTmrwtdgRegsh -+#define __INCmvTmrwtdgRegsh -+ -+/*******************************************/ -+/* ARM Timers Registers Map */ -+/*******************************************/ -+ -+#define CNTMR_RELOAD_REG(tmrNum) (CNTMR_BASE + 0x10 + (tmrNum)*8 + \ -+ (((tmrNum) <= 3)?0:8)) -+#define CNTMR_VAL_REG(tmrNum) (CNTMR_BASE + 0x14 + (tmrNum)*8 + \ -+ (((tmrNum) <= 3)?0:8)) -+#define CNTMR_CTRL_REG (CNTMR_BASE) -+ -+/*For MV78XX0*/ -+#define CNTMR_CAUSE_REG (CPU_AHB_MBUS_CAUSE_INT_REG(whoAmI())) -+#define CNTMR_MASK_REG (CPU_AHB_MBUS_MASK_INT_REG(whoAmI())) -+ -+/* ARM Timers Registers Map */ -+/*******************************************/ -+ -+ -+/* ARM Timers Control Register */ -+/* CPU_TIMERS_CTRL_REG (CTCR) */ -+ -+#define TIMER0_NUM 0 -+#define TIMER1_NUM 1 -+#define WATCHDOG_NUM 2 -+#define TIMER2_NUM 3 -+#define TIMER3_NUM 4 -+ -+#define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2) -+#define CTCR_ARM_TIMER_EN_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS) -+#define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr)) -+#define CTCR_ARM_TIMER_DIS(cntr) (0 << CTCR_ARM_TIMER_EN_OFFS(cntr)) -+ -+#define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1) -+#define CTCR_ARM_TIMER_AUTO_MASK(cntr) BIT1 -+#define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) -+#define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) -+ -+ -+/* ARM Timer\Watchdog Reload Register */ -+/* CNTMR_RELOAD_REG (TRR) */ -+ -+#define TRG_ARM_TIMER_REL_OFFS 0 -+#define TRG_ARM_TIMER_REL_MASK 0xffffffff -+ -+/* ARM Timer\Watchdog Register */ -+/* CNTMR_VAL_REG (TVRG) */ -+ -+#define TVR_ARM_TIMER_OFFS 0 -+#define TVR_ARM_TIMER_MASK 0xffffffff -+#define TVR_ARM_TIMER_MAX 0xffffffff -+ -+ -+ -+#endif /* __INCmvTmrwtdgRegsh */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCompVer.txt linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCompVer.txt ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCompVer.txt 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCompVer.txt 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,4 @@ -+Global HAL Version: FEROCEON_HAL_3_1_7 -+Unit HAL Version: 3.1.3 -+Description: This component includes an implementation of the unit HAL drivers -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,207 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include "mvOs.h" -+#include "mvCpuCntrs.h" -+ -+ -+const static MV_CPU_CNTRS_OPS mvCpuCntrsOpsTbl[MV_CPU_CNTRS_NUM][MV_CPU_CNTRS_OPS_NUM] = -+{ -+ /*0*/ -+ { -+ MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_DCACHE_READ_HIT, MV_CPU_CNTRS_DCACHE_READ_MISS, -+ MV_CPU_CNTRS_DCACHE_WRITE_HIT, MV_CPU_CNTRS_DCACHE_WRITE_MISS, MV_CPU_CNTRS_INSTRUCTIONS, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, -+ MV_CPU_CNTRS_MMU_READ_LATENCY, MV_CPU_CNTRS_ICACHE_READ_LATENCY, MV_CPU_CNTRS_WB_WRITE_LATENCY, -+ MV_CPU_CNTRS_LDM_STM_HOLD, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, -+ MV_CPU_CNTRS_DATA_WRITE_ACCESS, MV_CPU_CNTRS_DATA_READ_ACCESS, MV_CPU_CNTRS_INVALID, -+ MV_CPU_CNTRS_BRANCH_PREDICT_COUNT, -+ }, -+ /*1*/ -+ { -+ MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_ICACHE_READ_MISS, MV_CPU_CNTRS_DCACHE_READ_MISS, -+ MV_CPU_CNTRS_DCACHE_WRITE_MISS, MV_CPU_CNTRS_ITLB_MISS, MV_CPU_CNTRS_SINGLE_ISSUE, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BRANCH_RETIRED, MV_CPU_CNTRS_INVALID, -+ MV_CPU_CNTRS_MMU_READ_BEAT, MV_CPU_CNTRS_ICACHE_READ_LATENCY, MV_CPU_CNTRS_WB_WRITE_BEAT, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_IS_HOLD, MV_CPU_CNTRS_DATA_READ_ACCESS, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, -+ MV_CPU_CNTRS_INVALID, -+ }, -+ /*2*/ -+ { -+ MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DCACHE_ACCESS, -+ MV_CPU_CNTRS_DTLB_MISS, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BRANCH_PREDICT_MISS, MV_CPU_CNTRS_WB_WRITE_BEAT, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DCACHE_READ_LATENCY, MV_CPU_CNTRS_DCACHE_WRITE_LATENCY, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BIU_SIMULT_ACCESS, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, -+ MV_CPU_CNTRS_INVALID, -+ }, -+ /*3*/ -+ { -+ MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_DCACHE_READ_MISS, MV_CPU_CNTRS_DCACHE_WRITE_MISS, -+ MV_CPU_CNTRS_TLB_MISS, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BRANCH_TAKEN, MV_CPU_CNTRS_WB_FULL_CYCLES, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DCACHE_READ_BEAT, MV_CPU_CNTRS_DCACHE_WRITE_BEAT, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BIU_ANY_ACCESS, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DATA_WRITE_ACCESS, -+ MV_CPU_CNTRS_INVALID, -+ } -+}; -+ -+MV_CPU_CNTRS_ENTRY mvCpuCntrsTbl[MV_CPU_CNTRS_NUM]; -+ -+MV_CPU_CNTRS_EVENT* mvCpuCntrsEventTbl[128]; -+ -+void mvCpuCntrsReset(void) -+{ -+ MV_U32 reg = 0; -+ -+ MV_ASM ("mcr p15, 0, %0, c15, c13, 0" : : "r" (reg)); -+ MV_ASM ("mcr p15, 0, %0, c15, c13, 1" : : "r" (reg)); -+ MV_ASM ("mcr p15, 0, %0, c15, c13, 2" : : "r" (reg)); -+ MV_ASM ("mcr p15, 0, %0, c15, c13, 3" : : "r" (reg)); -+ MV_ASM ("mcr p15, 0, %0, c15, c13, 4" : : "r" (reg)); -+ MV_ASM ("mcr p15, 0, %0, c15, c13, 5" : : "r" (reg)); -+ MV_ASM ("mcr p15, 0, %0, c15, c13, 6" : : "r" (reg)); -+ MV_ASM ("mcr p15, 0, %0, c15, c13, 7" : : "r" (reg)); -+} -+ -+void program_counter(int counter, int op) -+{ -+ MV_U32 reg = (1 << op) | 0x1; /*enable*/ -+ -+ switch(counter) -+ { -+ case 0: -+ __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 0" : : "r" (reg)); -+ return; -+ -+ case 1: -+ __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 1" : : "r" (reg)); -+ return; -+ -+ case 2: -+ __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 2" : : "r" (reg)); -+ return; -+ -+ case 3: -+ __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 3" : : "r" (reg)); -+ return; -+ -+ default: -+ mvOsPrintf("error in program_counter: bad counter number (%d)\n", counter); -+ } -+ return; -+} -+ -+void mvCpuCntrsEventClear(MV_CPU_CNTRS_EVENT* pEvent) -+{ -+ int i; -+ -+ for(i=0; icounters_sum[i] = 0; -+ } -+ pEvent->num_of_measurements = 0; -+} -+ -+ -+MV_CPU_CNTRS_EVENT* mvCpuCntrsEventCreate(char* name, MV_U32 print_threshold) -+{ -+ int i; -+ MV_CPU_CNTRS_EVENT* event = mvOsMalloc(sizeof(MV_CPU_CNTRS_EVENT)); -+ -+ if(event) -+ { -+ strncpy(event->name, name, sizeof(event->name)); -+ event->num_of_measurements = 0; -+ event->avg_sample_count = print_threshold; -+ for(i=0; icounters_before[i] = 0; -+ event->counters_after[i] = 0; -+ event->counters_sum[i] = 0; -+ } -+ } -+ return event; -+} -+ -+void mvCpuCntrsEventDelete(MV_CPU_CNTRS_EVENT* event) -+{ -+ if(event != NULL) -+ mvOsFree(event); -+} -+ -+ -+MV_STATUS mvCpuCntrsProgram(int counter, MV_CPU_CNTRS_OPS op, -+ char* name, MV_U32 overhead) -+{ -+ int i; -+ -+ /* Find required operations */ -+ for(i=0; inum_of_measurements < pEvent->avg_sample_count) -+ return; -+ -+ mvOsPrintf("%16s: ", pEvent->name); -+ for(i=0; icounters_sum[i], -+ pEvent->num_of_measurements, NULL); -+ if(counters_avg >= mvCpuCntrsTbl[i].overhead) -+ counters_avg -= mvCpuCntrsTbl[i].overhead; -+ else -+ counters_avg = 0; -+ -+ mvOsPrintf("%s=%5llu, ", mvCpuCntrsTbl[i].name, counters_avg); -+ } -+ mvOsPrintf("\n"); -+ mvCpuCntrsEventClear(pEvent); -+ mvCpuCntrsReset(); -+} -+ -+void mvCpuCntrsStatus(void) -+{ -+ int i; -+ -+ for(i=0; icounters_before[i] = mvCpuCntrsRead(i); -+#else -+ pEvent->counters_before[1] = mvCpuCntrsRead(1); -+ pEvent->counters_before[3] = mvCpuCntrsRead(3); -+ pEvent->counters_before[0] = mvCpuCntrsRead(0); -+ pEvent->counters_before[2] = mvCpuCntrsRead(2); -+#endif -+} -+ -+static INLINE void mvCpuCntrsReadAfter(MV_CPU_CNTRS_EVENT* pEvent) -+{ -+ int i; -+ -+#if 0 -+ /* order is important - we want to measure the cycle count first here! */ -+ for(i=0; icounters_after[i] = mvCpuCntrsRead(i); -+#else -+ pEvent->counters_after[2] = mvCpuCntrsRead(2); -+ pEvent->counters_after[0] = mvCpuCntrsRead(0); -+ pEvent->counters_after[3] = mvCpuCntrsRead(3); -+ pEvent->counters_after[1] = mvCpuCntrsRead(1); -+#endif -+ -+ for(i=0; icounters_sum[i] += (pEvent->counters_after[i] - pEvent->counters_before[i]); -+ } -+ pEvent->num_of_measurements++; -+} -+ -+ -+#ifdef CONFIG_MV_CPU_PERF_CNTRS -+ -+#define MV_CPU_CNTRS_READ(counter) mvCpuCntrsRead(counter) -+ -+#define MV_CPU_CNTRS_START(event) mvCpuCntrsReadBefore(event) -+ -+#define MV_CPU_CNTRS_STOP(event) mvCpuCntrsReadAfter(event) -+ -+#define MV_CPU_CNTRS_SHOW(event) mvCpuCntrsShow(event) -+ -+#else -+ -+#define MV_CPU_CNTRS_READ(counter) -+#define MV_CPU_CNTRS_START(event) -+#define MV_CPU_CNTRS_STOP(event) -+#define MV_CPU_CNTRS_SHOW(event) -+ -+#endif /* CONFIG_MV_CPU_PERF_CNTRS */ -+ -+ -+#endif /* __mvCpuCntrs_h__ */ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,143 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include "mvOs.h" -+#include "mvCpuL2Cntrs.h" -+ -+ -+ -+MV_CPU_L2_CNTRS_ENTRY mvCpuL2CntrsTbl[MV_CPU_L2_CNTRS_NUM]; -+ -+MV_CPU_L2_CNTRS_EVENT* mvCpuL2CntrsEventTbl[128]; -+ -+void mvCpuL2CntrsReset(void) -+{ -+ MV_U32 reg = 0; -+ -+ MV_ASM ("mcr p15, 6, %0, c15, c13, 0" : : "r" (reg)); -+ MV_ASM ("mcr p15, 6, %0, c15, c13, 1" : : "r" (reg)); -+ MV_ASM ("mcr p15, 6, %0, c15, c13, 2" : : "r" (reg)); -+ MV_ASM ("mcr p15, 6, %0, c15, c13, 3" : : "r" (reg)); -+} -+ -+static void mvCpuL2CntrConfig(int counter, int op) -+{ -+ MV_U32 reg = (1 << op) | 0x1; /*enable*/ -+ -+ switch(counter) -+ { -+ case 0: -+ MV_ASM ("mcr p15, 6, %0, c15, c12, 0" : : "r" (reg)); -+ return; -+ -+ case 1: -+ MV_ASM ("mcr p15, 6, %0, c15, c12, 1" : : "r" (reg)); -+ return; -+ -+ default: -+ mvOsPrintf("mvCpuL2CntrConfig: bad counter number (%d)\n", counter); -+ } -+ return; -+} -+ -+void mvCpuL2CntrsEventClear(MV_CPU_L2_CNTRS_EVENT* pEvent) -+{ -+ int i; -+ -+ for(i=0; icounters_sum[i] = 0; -+ } -+ pEvent->num_of_measurements = 0; -+} -+ -+ -+MV_CPU_L2_CNTRS_EVENT* mvCpuL2CntrsEventCreate(char* name, MV_U32 print_threshold) -+{ -+ int i; -+ MV_CPU_L2_CNTRS_EVENT* event = mvOsMalloc(sizeof(MV_CPU_L2_CNTRS_EVENT)); -+ -+ if(event) -+ { -+ strncpy(event->name, name, sizeof(event->name)); -+ event->num_of_measurements = 0; -+ event->avg_sample_count = print_threshold; -+ for(i=0; icounters_before[i] = 0; -+ event->counters_after[i] = 0; -+ event->counters_sum[i] = 0; -+ } -+ } -+ return event; -+} -+ -+void mvCpuL2CntrsEventDelete(MV_CPU_L2_CNTRS_EVENT* event) -+{ -+ if(event != NULL) -+ mvOsFree(event); -+} -+ -+ -+MV_STATUS mvCpuL2CntrsProgram(int counter, MV_CPU_L2_CNTRS_OPS op, -+ char* name, MV_U32 overhead) -+{ -+ strncpy(mvCpuL2CntrsTbl[counter].name, name, sizeof(mvCpuL2CntrsTbl[counter].name)); -+ mvCpuL2CntrsTbl[counter].operation = op; -+ mvCpuL2CntrsTbl[counter].opIdx = op; -+ mvCpuL2CntrsTbl[counter].overhead = overhead; -+ mvCpuL2CntrConfig(counter, op); -+ mvOsPrintf("CPU L2 Counter %d: operation=%d, overhead=%d\n", -+ counter, op, overhead); -+ return MV_OK; -+} -+ -+void mvCpuL2CntrsShow(MV_CPU_L2_CNTRS_EVENT* pEvent) -+{ -+ int i; -+ MV_U64 counters_avg; -+ -+ if(pEvent->num_of_measurements < pEvent->avg_sample_count) -+ return; -+ -+ mvOsPrintf("%16s: ", pEvent->name); -+ for(i=0; icounters_sum[i], -+ pEvent->num_of_measurements, NULL); -+ -+ if(counters_avg >= mvCpuL2CntrsTbl[i].overhead) -+ counters_avg -= mvCpuL2CntrsTbl[i].overhead; -+ else -+ counters_avg = 0; -+ -+ mvOsPrintf("%s=%5llu, ", mvCpuL2CntrsTbl[i].name, counters_avg); -+ } -+ mvOsPrintf("\n"); -+ mvCpuL2CntrsEventClear(pEvent); -+ mvCpuL2CntrsReset(); -+} -+ -+void mvCpuL2CntrsStatus(void) -+{ -+ int i; -+ -+ for(i=0; icounters_before[i] = mvCpuL2CntrsRead(i); -+} -+ -+static INLINE void mvCpuL2CntrsReadAfter(MV_CPU_L2_CNTRS_EVENT* pEvent) -+{ -+ int i; -+ -+ for(i=0; icounters_after[i] = mvCpuL2CntrsRead(i); -+ pEvent->counters_sum[i] += (pEvent->counters_after[i] - pEvent->counters_before[i]); -+ } -+ pEvent->num_of_measurements++; -+} -+ -+ -+#ifdef CONFIG_MV_CPU_L2_PERF_CNTRS -+ -+#define MV_CPU_L2_CNTRS_READ(counter) mvCpuL2CntrsRead(counter) -+ -+#define MV_CPU_L2_CNTRS_START(event) mvCpuL2CntrsReadBefore(event) -+ -+#define MV_CPU_L2_CNTRS_STOP(event) mvCpuL2CntrsReadAfter(event) -+ -+#define MV_CPU_L2_CNTRS_SHOW(event) mvCpuL2CntrsShow(event) -+ -+#else -+ -+#define MV_CPU_L2_CNTRS_READ(counter) -+#define MV_CPU_L2_CNTRS_START(event) -+#define MV_CPU_L2_CNTRS_STOP(event) -+#define MV_CPU_L2_CNTRS_SHOW(event) -+ -+#endif /* CONFIG_MV_CPU_L2_PERF_CNTRS */ -+ -+ -+#endif /* __mvCpuL2Cntrs_h__ */ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvCompVer.txt linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvCompVer.txt ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvCompVer.txt 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvCompVer.txt 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,4 @@ -+Global HAL Version: FEROCEON_HAL_3_1_7 -+Unit HAL Version: 3.1.3 -+Description: This component includes an implementation of the unit HAL drivers -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,1479 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "ddr1_2/mvDram.h" -+#include "boardEnv/mvBoardEnvLib.h" -+ -+#undef MV_DEBUG -+#ifdef MV_DEBUG -+#define DB(x) x -+#else -+#define DB(x) -+#endif -+ -+static MV_VOID cpyDimm2BankInfo(MV_DIMM_INFO *pDimmInfo, -+ MV_DRAM_BANK_INFO *pBankInfo); -+static MV_U32 cas2ps(MV_U8 spd_byte); -+/******************************************************************************* -+* mvDramBankGet - Get the DRAM bank paramters. -+* -+* DESCRIPTION: -+* This function retrieves DRAM bank parameters as described in -+* DRAM_BANK_INFO struct to the controller DRAM unit. In case the board -+* has its DRAM on DIMMs it will use its EEPROM to extract SPD data -+* from it. Otherwise, if the DRAM is soldered on board, the function -+* should insert its bank information into MV_DRAM_BANK_INFO struct. -+* -+* INPUT: -+* bankNum - Board DRAM bank number. -+* -+* OUTPUT: -+* pBankInfo - DRAM bank information struct. -+* -+* RETURN: -+* MV_FAIL - Bank parameters could not be read. -+* -+*******************************************************************************/ -+MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo) -+{ -+ MV_DIMM_INFO dimmInfo; -+ -+ DB(mvOsPrintf("Dram: mvDramBankInfoGet bank %d\n", bankNum)); -+ /* zero pBankInfo structure */ -+ memset(pBankInfo, 0, sizeof(*pBankInfo)); -+ -+ if((NULL == pBankInfo) || (bankNum >= MV_DRAM_MAX_CS )) -+ { -+ DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); -+ return MV_BAD_PARAM; -+ } -+ if( MV_OK != dimmSpdGet((MV_U32)(bankNum/2), &dimmInfo)) -+ { -+ DB(mvOsPrintf("Dram: ERR dimmSpdGet failed to get dimm info \n")); -+ return MV_FAIL; -+ } -+ if((dimmInfo.numOfModuleBanks == 1) && ((bankNum % 2) == 1)) -+ { -+ DB(mvOsPrintf("Dram: ERR dimmSpdGet. Can't find DIMM bank 2 \n")); -+ return MV_FAIL; -+ } -+ -+ /* convert Dimm info to Bank info */ -+ cpyDimm2BankInfo(&dimmInfo, pBankInfo); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* cpyDimm2BankInfo - Convert a Dimm info struct into a bank info struct. -+* -+* DESCRIPTION: -+* Convert a Dimm info struct into a bank info struct. -+* -+* INPUT: -+* pDimmInfo - DIMM information structure. -+* -+* OUTPUT: -+* pBankInfo - DRAM bank information struct. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+static MV_VOID cpyDimm2BankInfo(MV_DIMM_INFO *pDimmInfo, -+ MV_DRAM_BANK_INFO *pBankInfo) -+{ -+ pBankInfo->memoryType = pDimmInfo->memoryType; -+ -+ /* DIMM dimensions */ -+ pBankInfo->numOfRowAddr = pDimmInfo->numOfRowAddr; -+ pBankInfo->numOfColAddr = pDimmInfo->numOfColAddr; -+ pBankInfo->dataWidth = pDimmInfo->dataWidth; -+ pBankInfo->errorCheckType = pDimmInfo->errorCheckType; -+ pBankInfo->sdramWidth = pDimmInfo->sdramWidth; -+ pBankInfo->errorCheckDataWidth = pDimmInfo->errorCheckDataWidth; -+ pBankInfo->numOfBanksOnEachDevice = pDimmInfo->numOfBanksOnEachDevice; -+ pBankInfo->suportedCasLatencies = pDimmInfo->suportedCasLatencies; -+ pBankInfo->refreshInterval = pDimmInfo->refreshInterval; -+ -+ /* DIMM timing parameters */ -+ pBankInfo->minCycleTimeAtMaxCasLatPs = pDimmInfo->minCycleTimeAtMaxCasLatPs; -+ pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps = -+ pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps; -+ pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps = -+ pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps; -+ -+ pBankInfo->minRowPrechargeTime = pDimmInfo->minRowPrechargeTime; -+ pBankInfo->minRowActiveToRowActive = pDimmInfo->minRowActiveToRowActive; -+ pBankInfo->minRasToCasDelay = pDimmInfo->minRasToCasDelay; -+ pBankInfo->minRasPulseWidth = pDimmInfo->minRasPulseWidth; -+ pBankInfo->minWriteRecoveryTime = pDimmInfo->minWriteRecoveryTime; -+ pBankInfo->minWriteToReadCmdDelay = pDimmInfo->minWriteToReadCmdDelay; -+ pBankInfo->minReadToPrechCmdDelay = pDimmInfo->minReadToPrechCmdDelay; -+ pBankInfo->minRefreshToActiveCmd = pDimmInfo->minRefreshToActiveCmd; -+ -+ /* Parameters calculated from the extracted DIMM information */ -+ pBankInfo->size = pDimmInfo->size/pDimmInfo->numOfModuleBanks; -+ pBankInfo->deviceDensity = pDimmInfo->deviceDensity; -+ pBankInfo->numberOfDevices = pDimmInfo->numberOfDevices / -+ pDimmInfo->numOfModuleBanks; -+ -+ /* DIMM attributes (MV_TRUE for yes) */ -+ -+ if ((pDimmInfo->memoryType == MEM_TYPE_SDRAM) || -+ (pDimmInfo->memoryType == MEM_TYPE_DDR1) ) -+ { -+ if (pDimmInfo->dimmAttributes & BIT1) -+ pBankInfo->registeredAddrAndControlInputs = MV_TRUE; -+ else -+ pBankInfo->registeredAddrAndControlInputs = MV_FALSE; -+ } -+ else /* pDimmInfo->memoryType == MEM_TYPE_DDR2 */ -+ { -+ if (pDimmInfo->dimmTypeInfo & (BIT0 | BIT4)) -+ pBankInfo->registeredAddrAndControlInputs = MV_TRUE; -+ else -+ pBankInfo->registeredAddrAndControlInputs = MV_FALSE; -+ } -+ -+ return; -+} -+ -+/******************************************************************************* -+* dimmSpdCpy - Cpy SPD parameters from dimm 0 to dimm 1. -+* -+* DESCRIPTION: -+* Read the DIMM SPD parameters from dimm 0 into dimm 1 SPD. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+MV_STATUS dimmSpdCpy(MV_VOID) -+{ -+ MV_U32 i; -+ MV_U32 spdChecksum; -+ -+ MV_TWSI_SLAVE twsiSlave; -+ MV_U8 data[SPD_SIZE]; -+ -+ /* zero dimmInfo structure */ -+ memset(data, 0, SPD_SIZE); -+ -+ /* read the dimm eeprom */ -+ DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); -+ twsiSlave.slaveAddr.address = MV_BOARD_DIMM0_I2C_ADDR; -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ twsiSlave.offset = 0; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, -+ &twsiSlave, data, SPD_SIZE) ) -+ { -+ DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 0\n")); -+ return MV_FAIL; -+ } -+ DB(puts("DRAM: Reading dimm info succeded.\n")); -+ -+ /* calculate SPD checksum */ -+ spdChecksum = 0; -+ -+ for(i = 0 ; i <= 62 ; i++) -+ { -+ spdChecksum += data[i]; -+ } -+ -+ if ((spdChecksum & 0xff) != data[63]) -+ { -+ DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", -+ (MV_U32)(spdChecksum & 0xff), data[63])); -+ } -+ else -+ { -+ DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); -+ } -+ -+ /* copy the SPD content 1:1 into the DIMM 1 SPD */ -+ twsiSlave.slaveAddr.address = MV_BOARD_DIMM1_I2C_ADDR; -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ twsiSlave.offset = 0; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ for(i = 0 ; i < SPD_SIZE ; i++) -+ { -+ twsiSlave.offset = i; -+ if( MV_OK != mvTwsiWrite (MV_BOARD_DIMM_I2C_CHANNEL, -+ &twsiSlave, &data[i], 1) ) -+ { -+ mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 1 byte %d \n",i); -+ return MV_FAIL; -+ } -+ mvOsDelay(5); -+ } -+ -+ DB(puts("DRAM: Reading dimm info succeded.\n")); -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* dimmSpdGet - Get the SPD parameters. -+* -+* DESCRIPTION: -+* Read the DIMM SPD parameters into given struct parameter. -+* -+* INPUT: -+* dimmNum - DIMM number. See MV_BOARD_DIMM_NUM enumerator. -+* -+* OUTPUT: -+* pDimmInfo - DIMM information structure. -+* -+* RETURN: -+* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo) -+{ -+ MV_U32 i; -+ MV_U32 density = 1; -+ MV_U32 spdChecksum; -+ -+ MV_TWSI_SLAVE twsiSlave; -+ MV_U8 data[SPD_SIZE]; -+ -+ if((NULL == pDimmInfo)|| (dimmNum >= MAX_DIMM_NUM)) -+ { -+ DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); -+ return MV_BAD_PARAM; -+ } -+ -+ /* zero dimmInfo structure */ -+ memset(data, 0, SPD_SIZE); -+ -+ /* read the dimm eeprom */ -+ DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); -+ twsiSlave.slaveAddr.address = (dimmNum == 0) ? -+ MV_BOARD_DIMM0_I2C_ADDR : MV_BOARD_DIMM1_I2C_ADDR; -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ twsiSlave.offset = 0; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, -+ &twsiSlave, data, SPD_SIZE) ) -+ { -+ DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum %d \n", dimmNum)); -+ return MV_FAIL; -+ } -+ DB(puts("DRAM: Reading dimm info succeded.\n")); -+ -+ /* calculate SPD checksum */ -+ spdChecksum = 0; -+ -+ for(i = 0 ; i <= 62 ; i++) -+ { -+ spdChecksum += data[i]; -+ } -+ -+ if ((spdChecksum & 0xff) != data[63]) -+ { -+ DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", -+ (MV_U32)(spdChecksum & 0xff), data[63])); -+ } -+ else -+ { -+ DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); -+ } -+ -+ /* copy the SPD content 1:1 into the dimmInfo structure*/ -+ for(i = 0 ; i < SPD_SIZE ; i++) -+ { -+ pDimmInfo->spdRawData[i] = data[i]; -+ DB(mvOsPrintf("SPD-EEPROM Byte %3d = %3x (%3d)\n",i, data[i], data[i])); -+ } -+ -+ DB(mvOsPrintf("DRAM SPD Information:\n")); -+ -+ /* Memory type (DDR / SDRAM) */ -+ switch (data[DIMM_MEM_TYPE]) -+ { -+ case (DIMM_MEM_TYPE_SDRAM): -+ pDimmInfo->memoryType = MEM_TYPE_SDRAM; -+ DB(mvOsPrintf("DRAM Memeory type SDRAM\n")); -+ break; -+ case (DIMM_MEM_TYPE_DDR1): -+ pDimmInfo->memoryType = MEM_TYPE_DDR1; -+ DB(mvOsPrintf("DRAM Memeory type DDR1\n")); -+ break; -+ case (DIMM_MEM_TYPE_DDR2): -+ pDimmInfo->memoryType = MEM_TYPE_DDR2; -+ DB(mvOsPrintf("DRAM Memeory type DDR2\n")); -+ break; -+ default: -+ mvOsPrintf("ERROR: Undefined memory type!\n"); -+ return MV_ERROR; -+ } -+ -+ -+ /* Number Of Row Addresses */ -+ pDimmInfo->numOfRowAddr = data[DIMM_ROW_NUM]; -+ DB(mvOsPrintf("DRAM numOfRowAddr[3] %d\n",pDimmInfo->numOfRowAddr)); -+ -+ /* Number Of Column Addresses */ -+ pDimmInfo->numOfColAddr = data[DIMM_COL_NUM]; -+ DB(mvOsPrintf("DRAM numOfColAddr[4] %d\n",pDimmInfo->numOfColAddr)); -+ -+ /* Number Of Module Banks */ -+ pDimmInfo->numOfModuleBanks = data[DIMM_MODULE_BANK_NUM]; -+ DB(mvOsPrintf("DRAM numOfModuleBanks[5] 0x%x\n", -+ pDimmInfo->numOfModuleBanks)); -+ -+ /* Number of module banks encoded differently for DDR2 */ -+ if (pDimmInfo->memoryType == MEM_TYPE_DDR2) -+ pDimmInfo->numOfModuleBanks = (pDimmInfo->numOfModuleBanks & 0x7)+1; -+ -+ /* Data Width */ -+ pDimmInfo->dataWidth = data[DIMM_DATA_WIDTH]; -+ DB(mvOsPrintf("DRAM dataWidth[6] 0x%x\n", pDimmInfo->dataWidth)); -+ -+ /* Minimum Cycle Time At Max CasLatancy */ -+ pDimmInfo->minCycleTimeAtMaxCasLatPs = cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS]); -+ -+ /* Error Check Type */ -+ pDimmInfo->errorCheckType = data[DIMM_ERR_CHECK_TYPE]; -+ DB(mvOsPrintf("DRAM errorCheckType[11] 0x%x\n", -+ pDimmInfo->errorCheckType)); -+ -+ /* Refresh Interval */ -+ pDimmInfo->refreshInterval = data[DIMM_REFRESH_INTERVAL]; -+ DB(mvOsPrintf("DRAM refreshInterval[12] 0x%x\n", -+ pDimmInfo->refreshInterval)); -+ -+ /* Sdram Width */ -+ pDimmInfo->sdramWidth = data[DIMM_SDRAM_WIDTH]; -+ DB(mvOsPrintf("DRAM sdramWidth[13] 0x%x\n",pDimmInfo->sdramWidth)); -+ -+ /* Error Check Data Width */ -+ pDimmInfo->errorCheckDataWidth = data[DIMM_ERR_CHECK_DATA_WIDTH]; -+ DB(mvOsPrintf("DRAM errorCheckDataWidth[14] 0x%x\n", -+ pDimmInfo->errorCheckDataWidth)); -+ -+ /* Burst Length Supported */ -+ /* SDRAM/DDR1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * -+ *********************************************************/ -+ /* DDR2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * -+ *********************************************************/ -+ -+ pDimmInfo->burstLengthSupported = data[DIMM_BURST_LEN_SUP]; -+ DB(mvOsPrintf("DRAM burstLengthSupported[16] 0x%x\n", -+ pDimmInfo->burstLengthSupported)); -+ -+ /* Number Of Banks On Each Device */ -+ pDimmInfo->numOfBanksOnEachDevice = data[DIMM_DEV_BANK_NUM]; -+ DB(mvOsPrintf("DRAM numOfBanksOnEachDevice[17] 0x%x\n", -+ pDimmInfo->numOfBanksOnEachDevice)); -+ -+ /* Suported Cas Latencies */ -+ -+ /* SDRAM: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * -+ ********************************************************/ -+ -+ /* DDR 1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * -+ *********************************************************/ -+ -+ /* DDR 2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * -+ *********************************************************/ -+ -+ pDimmInfo->suportedCasLatencies = data[DIMM_SUP_CAL]; -+ DB(mvOsPrintf("DRAM suportedCasLatencies[18] 0x%x\n", -+ pDimmInfo->suportedCasLatencies)); -+ -+ /* For DDR2 only, get the DIMM type information */ -+ if (pDimmInfo->memoryType == MEM_TYPE_DDR2) -+ { -+ pDimmInfo->dimmTypeInfo = data[DIMM_DDR2_TYPE_INFORMATION]; -+ DB(mvOsPrintf("DRAM dimmTypeInfo[20] (DDR2) 0x%x\n", -+ pDimmInfo->dimmTypeInfo)); -+ } -+ -+ /* SDRAM Modules Attributes */ -+ pDimmInfo->dimmAttributes = data[DIMM_BUF_ADDR_CONT_IN]; -+ DB(mvOsPrintf("DRAM dimmAttributes[21] 0x%x\n", -+ pDimmInfo->dimmAttributes)); -+ -+ /* Minimum Cycle Time At Max CasLatancy Minus 1*/ -+ pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps = -+ cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS1]); -+ -+ /* Minimum Cycle Time At Max CasLatancy Minus 2*/ -+ pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps = -+ cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS2]); -+ -+ pDimmInfo->minRowPrechargeTime = data[DIMM_MIN_ROW_PRECHARGE_TIME]; -+ DB(mvOsPrintf("DRAM minRowPrechargeTime[27] 0x%x\n", -+ pDimmInfo->minRowPrechargeTime)); -+ pDimmInfo->minRowActiveToRowActive = data[DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE]; -+ DB(mvOsPrintf("DRAM minRowActiveToRowActive[28] 0x%x\n", -+ pDimmInfo->minRowActiveToRowActive)); -+ pDimmInfo->minRasToCasDelay = data[DIMM_MIN_RAS_TO_CAS_DELAY]; -+ DB(mvOsPrintf("DRAM minRasToCasDelay[29] 0x%x\n", -+ pDimmInfo->minRasToCasDelay)); -+ pDimmInfo->minRasPulseWidth = data[DIMM_MIN_RAS_PULSE_WIDTH]; -+ DB(mvOsPrintf("DRAM minRasPulseWidth[30] 0x%x\n", -+ pDimmInfo->minRasPulseWidth)); -+ -+ /* DIMM Bank Density */ -+ pDimmInfo->dimmBankDensity = data[DIMM_BANK_DENSITY]; -+ DB(mvOsPrintf("DRAM dimmBankDensity[31] 0x%x\n", -+ pDimmInfo->dimmBankDensity)); -+ -+ /* Only DDR2 includes Write Recovery Time field. Other SDRAM ignore */ -+ pDimmInfo->minWriteRecoveryTime = data[DIMM_MIN_WRITE_RECOVERY_TIME]; -+ DB(mvOsPrintf("DRAM minWriteRecoveryTime[36] 0x%x\n", -+ pDimmInfo->minWriteRecoveryTime)); -+ -+ /* Only DDR2 includes Internal Write To Read Command Delay field. */ -+ pDimmInfo->minWriteToReadCmdDelay = data[DIMM_MIN_WRITE_TO_READ_CMD_DELAY]; -+ DB(mvOsPrintf("DRAM minWriteToReadCmdDelay[37] 0x%x\n", -+ pDimmInfo->minWriteToReadCmdDelay)); -+ -+ /* Only DDR2 includes Internal Read To Precharge Command Delay field. */ -+ pDimmInfo->minReadToPrechCmdDelay = data[DIMM_MIN_READ_TO_PRECH_CMD_DELAY]; -+ DB(mvOsPrintf("DRAM minReadToPrechCmdDelay[38] 0x%x\n", -+ pDimmInfo->minReadToPrechCmdDelay)); -+ -+ /* Only DDR2 includes Minimum Refresh to Activate/Refresh Command field */ -+ pDimmInfo->minRefreshToActiveCmd = data[DIMM_MIN_REFRESH_TO_ACTIVATE_CMD]; -+ DB(mvOsPrintf("DRAM minRefreshToActiveCmd[42] 0x%x\n", -+ pDimmInfo->minRefreshToActiveCmd)); -+ -+ /* calculating the sdram density. Representing device density from */ -+ /* bit 20 to allow representation of 4GB and above. */ -+ /* For example, if density is 512Mbit 0x20000000, will be represent in */ -+ /* deviceDensity by 0x20000000 >> 16 --> 0x00000200. Another example */ -+ /* is density 8GB 0x200000000 >> 16 --> 0x00002000. */ -+ density = (1 << ((pDimmInfo->numOfRowAddr + pDimmInfo->numOfColAddr) - 20)); -+ pDimmInfo->deviceDensity = density * -+ pDimmInfo->numOfBanksOnEachDevice * -+ pDimmInfo->sdramWidth; -+ DB(mvOsPrintf("DRAM deviceDensity %d\n",pDimmInfo->deviceDensity)); -+ -+ /* Number of devices includeing Error correction */ -+ pDimmInfo->numberOfDevices = (pDimmInfo->dataWidth/pDimmInfo->sdramWidth) * -+ pDimmInfo->numOfModuleBanks; -+ DB(mvOsPrintf("DRAM numberOfDevices %d\n", -+ pDimmInfo->numberOfDevices)); -+ -+ pDimmInfo->size = 0; -+ -+ /* Note that pDimmInfo->size is in MB units */ -+ if (pDimmInfo->memoryType == MEM_TYPE_SDRAM) -+ { -+ if (pDimmInfo->dimmBankDensity & BIT0) -+ pDimmInfo->size += 1024; /* Equal to 1GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT1) -+ pDimmInfo->size += 8; /* Equal to 8MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT2) -+ pDimmInfo->size += 16; /* Equal to 16MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT3) -+ pDimmInfo->size += 32; /* Equal to 32MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT4) -+ pDimmInfo->size += 64; /* Equal to 64MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT5) -+ pDimmInfo->size += 128; /* Equal to 128MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT6) -+ pDimmInfo->size += 256; /* Equal to 256MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT7) -+ pDimmInfo->size += 512; /* Equal to 512MB */ -+ } -+ else if (pDimmInfo->memoryType == MEM_TYPE_DDR1) -+ { -+ if (pDimmInfo->dimmBankDensity & BIT0) -+ pDimmInfo->size += 1024; /* Equal to 1GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT1) -+ pDimmInfo->size += 2048; /* Equal to 2GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT2) -+ pDimmInfo->size += 16; /* Equal to 16MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT3) -+ pDimmInfo->size += 32; /* Equal to 32MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT4) -+ pDimmInfo->size += 64; /* Equal to 64MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT5) -+ pDimmInfo->size += 128; /* Equal to 128MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT6) -+ pDimmInfo->size += 256; /* Equal to 256MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT7) -+ pDimmInfo->size += 512; /* Equal to 512MB */ -+ } -+ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ -+ { -+ if (pDimmInfo->dimmBankDensity & BIT0) -+ pDimmInfo->size += 1024; /* Equal to 1GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT1) -+ pDimmInfo->size += 2048; /* Equal to 2GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT2) -+ pDimmInfo->size += 4096; /* Equal to 4GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT3) -+ pDimmInfo->size += 8192; /* Equal to 8GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT4) -+ pDimmInfo->size += 16384; /* Equal to 16GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT5) -+ pDimmInfo->size += 128; /* Equal to 128MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT6) -+ pDimmInfo->size += 256; /* Equal to 256MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT7) -+ pDimmInfo->size += 512; /* Equal to 512MB */ -+ } -+ -+ pDimmInfo->size *= pDimmInfo->numOfModuleBanks; -+ -+ DB(mvOsPrintf("Dram: dimm size %dMB \n",pDimmInfo->size)); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* dimmSpdPrint - Print the SPD parameters. -+* -+* DESCRIPTION: -+* Print the Dimm SPD parameters. -+* -+* INPUT: -+* pDimmInfo - DIMM information structure. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID dimmSpdPrint(MV_U32 dimmNum) -+{ -+ MV_DIMM_INFO dimmInfo; -+ MV_U32 i, temp = 0; -+ MV_U32 k, maskLeftOfPoint = 0, maskRightOfPoint = 0; -+ MV_U32 rightOfPoint = 0,leftOfPoint = 0, div, time_tmp, shift; -+ MV_U32 busClkPs; -+ MV_U8 trp_clocks=0, trcd_clocks, tras_clocks, trrd_clocks, -+ temp_buf[40], *spdRawData; -+ -+ busClkPs = 1000000000 / (mvBoardSysClkGet() / 100); /* in 10 ps units */ -+ -+ spdRawData = dimmInfo.spdRawData; -+ -+ if(MV_OK != dimmSpdGet(dimmNum, &dimmInfo)) -+ { -+ mvOsOutput("ERROR: Could not read SPD information!\n"); -+ return; -+ } -+ -+ /* find Manufactura of Dimm Module */ -+ mvOsOutput("\nManufacturer's JEDEC ID Code: "); -+ for(i = 0 ; i < DIMM_MODULE_MANU_SIZE ; i++) -+ { -+ mvOsOutput("%x",spdRawData[DIMM_MODULE_MANU_OFFS + i]); -+ } -+ mvOsOutput("\n"); -+ -+ /* Manufacturer's Specific Data */ -+ for(i = 0 ; i < DIMM_MODULE_ID_SIZE ; i++) -+ { -+ temp_buf[i] = spdRawData[DIMM_MODULE_ID_OFFS + i]; -+ } -+ mvOsOutput("Manufacturer's Specific Data: %s\n", temp_buf); -+ -+ /* Module Part Number */ -+ for(i = 0 ; i < DIMM_MODULE_VEN_SIZE ; i++) -+ { -+ temp_buf[i] = spdRawData[DIMM_MODULE_VEN_OFFS + i]; -+ } -+ mvOsOutput("Module Part Number: %s\n", temp_buf); -+ -+ /* Module Serial Number */ -+ for(i = 0; i < sizeof(MV_U32); i++) -+ { -+ temp |= spdRawData[95+i] << 8*i; -+ } -+ mvOsOutput("DIMM Serial No. %ld (%lx)\n", (long)temp, -+ (long)temp); -+ -+ /* find Manufac-Data of Dimm Module */ -+ mvOsOutput("Manufactoring Date: Year 20%d%d/ ww %d%d\n", -+ ((spdRawData[93] & 0xf0) >> 4), (spdRawData[93] & 0xf), -+ ((spdRawData[94] & 0xf0) >> 4), (spdRawData[94] & 0xf)); -+ /* find modul_revision of Dimm Module */ -+ mvOsOutput("Module Revision: %d.%d\n", -+ spdRawData[91], spdRawData[92]); -+ -+ /* find manufac_place of Dimm Module */ -+ mvOsOutput("manufac_place: %d\n", spdRawData[72]); -+ -+ /* go over the first 35 I2C data bytes */ -+ for(i = 2 ; i <= 35 ; i++) -+ switch(i) -+ { -+ case 2: /* Memory type (DDR1/2 / SDRAM) */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ mvOsOutput("Dram Type is: SDRAM\n"); -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ mvOsOutput("Dram Type is: SDRAM DDR1\n"); -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) -+ mvOsOutput("Dram Type is: SDRAM DDR2\n"); -+ else -+ mvOsOutput("Dram Type unknown\n"); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 3: /* Number Of Row Addresses */ -+ mvOsOutput("Module Number of row addresses: %d\n", -+ dimmInfo.numOfRowAddr); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 4: /* Number Of Column Addresses */ -+ mvOsOutput("Module Number of col addresses: %d\n", -+ dimmInfo.numOfColAddr); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 5: /* Number Of Module Banks */ -+ mvOsOutput("Number of Banks on Mod.: %d\n", -+ dimmInfo.numOfModuleBanks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 6: /* Data Width */ -+ mvOsOutput("Module Data Width: %d bit\n", -+ dimmInfo.dataWidth); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 8: /* Voltage Interface */ -+ switch(spdRawData[i]) -+ { -+ case 0x0: -+ mvOsOutput("Module is TTL_5V_TOLERANT\n"); -+ break; -+ case 0x1: -+ mvOsOutput("Module is LVTTL\n"); -+ break; -+ case 0x2: -+ mvOsOutput("Module is HSTL_1_5V\n"); -+ break; -+ case 0x3: -+ mvOsOutput("Module is SSTL_3_3V\n"); -+ break; -+ case 0x4: -+ mvOsOutput("Module is SSTL_2_5V\n"); -+ break; -+ case 0x5: -+ if (dimmInfo.memoryType != MEM_TYPE_SDRAM) -+ { -+ mvOsOutput("Module is SSTL_1_8V\n"); -+ break; -+ } -+ default: -+ mvOsOutput("Module is VOLTAGE_UNKNOWN\n"); -+ break; -+ } -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 9: /* Minimum Cycle Time At Max CasLatancy */ -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ rightOfPoint = (spdRawData[i] & 0x0f) * 10; -+ -+ /* DDR2 addition of right of point */ -+ if ((spdRawData[i] & 0x0f) == 0xA) -+ { -+ rightOfPoint = 25; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xB) -+ { -+ rightOfPoint = 33; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xC) -+ { -+ rightOfPoint = 66; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xD) -+ { -+ rightOfPoint = 75; -+ } -+ mvOsOutput("Minimum Cycle Time At Max CL: %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 10: /* Clock To Data Out */ -+ div = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 10:100; -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / div; -+ rightOfPoint = time_tmp % div; -+ mvOsOutput("Clock To Data Out: %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 11: /* Error Check Type */ -+ mvOsOutput("Error Check Type (0=NONE): %d\n", -+ dimmInfo.errorCheckType); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 12: /* Refresh Interval */ -+ mvOsOutput("Refresh Rate: %x\n", -+ dimmInfo.refreshInterval); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 13: /* Sdram Width */ -+ mvOsOutput("Sdram Width: %d bits\n", -+ dimmInfo.sdramWidth); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 14: /* Error Check Data Width */ -+ mvOsOutput("Error Check Data Width: %d bits\n", -+ dimmInfo.errorCheckDataWidth); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 15: /* Minimum Clock Delay is unsupported */ -+ if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || -+ (dimmInfo.memoryType == MEM_TYPE_DDR1)) -+ { -+ mvOsOutput("Minimum Clk Delay back to back: %d\n", -+ spdRawData[i]); -+ } -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 16: /* Burst Length Supported */ -+ /* SDRAM/DDR1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * -+ *********************************************************/ -+ /* DDR2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * -+ *********************************************************/ -+ mvOsOutput("Burst Length Supported: "); -+ if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || -+ (dimmInfo.memoryType == MEM_TYPE_DDR1)) -+ { -+ if (dimmInfo.burstLengthSupported & BIT0) -+ mvOsOutput("1, "); -+ if (dimmInfo.burstLengthSupported & BIT1) -+ mvOsOutput("2, "); -+ } -+ if (dimmInfo.burstLengthSupported & BIT2) -+ mvOsOutput("4, "); -+ if (dimmInfo.burstLengthSupported & BIT3) -+ mvOsOutput("8, "); -+ -+ mvOsOutput(" Bit \n"); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 17: /* Number Of Banks On Each Device */ -+ mvOsOutput("Number Of Banks On Each Chip: %d\n", -+ dimmInfo.numOfBanksOnEachDevice); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 18: /* Suported Cas Latencies */ -+ -+ /* SDRAM: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * -+ ********************************************************/ -+ -+ /* DDR 1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * -+ *********************************************************/ -+ -+ /* DDR 2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * -+ *********************************************************/ -+ -+ mvOsOutput("Suported Cas Latencies: (CL) "); -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ for (k = 0; k <=7; k++) -+ { -+ if (dimmInfo.suportedCasLatencies & (1 << k)) -+ mvOsOutput("%d, ", k+1); -+ } -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ { -+ if (dimmInfo.suportedCasLatencies & BIT0) -+ mvOsOutput("1, "); -+ if (dimmInfo.suportedCasLatencies & BIT1) -+ mvOsOutput("1.5, "); -+ if (dimmInfo.suportedCasLatencies & BIT2) -+ mvOsOutput("2, "); -+ if (dimmInfo.suportedCasLatencies & BIT3) -+ mvOsOutput("2.5, "); -+ if (dimmInfo.suportedCasLatencies & BIT4) -+ mvOsOutput("3, "); -+ if (dimmInfo.suportedCasLatencies & BIT5) -+ mvOsOutput("3.5, "); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) -+ { -+ if (dimmInfo.suportedCasLatencies & BIT2) -+ mvOsOutput("2, "); -+ if (dimmInfo.suportedCasLatencies & BIT3) -+ mvOsOutput("3, "); -+ if (dimmInfo.suportedCasLatencies & BIT4) -+ mvOsOutput("4, "); -+ if (dimmInfo.suportedCasLatencies & BIT5) -+ mvOsOutput("5, "); -+ } -+ else -+ mvOsOutput("?.?, "); -+ mvOsOutput("\n"); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 20: /* DDR2 DIMM type info */ -+ if (dimmInfo.memoryType == MEM_TYPE_DDR2) -+ { -+ if (dimmInfo.dimmTypeInfo & (BIT0 | BIT4)) -+ mvOsOutput("Registered DIMM (RDIMM)\n"); -+ else if (dimmInfo.dimmTypeInfo & (BIT1 | BIT5)) -+ mvOsOutput("Unbuffered DIMM (UDIMM)\n"); -+ else -+ mvOsOutput("Unknown DIMM type.\n"); -+ } -+ -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 21: /* SDRAM Modules Attributes */ -+ mvOsOutput("\nModule Attributes (SPD Byte 21): \n"); -+ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ if (dimmInfo.dimmAttributes & BIT0) -+ mvOsOutput(" Buffered Addr/Control Input: Yes\n"); -+ else -+ mvOsOutput(" Buffered Addr/Control Input: No\n"); -+ -+ if (dimmInfo.dimmAttributes & BIT1) -+ mvOsOutput(" Registered Addr/Control Input: Yes\n"); -+ else -+ mvOsOutput(" Registered Addr/Control Input: No\n"); -+ -+ if (dimmInfo.dimmAttributes & BIT2) -+ mvOsOutput(" On-Card PLL (clock): Yes \n"); -+ else -+ mvOsOutput(" On-Card PLL (clock): No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT3) -+ mvOsOutput(" Bufferd DQMB Input: Yes \n"); -+ else -+ mvOsOutput(" Bufferd DQMB Inputs: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT4) -+ mvOsOutput(" Registered DQMB Inputs: Yes \n"); -+ else -+ mvOsOutput(" Registered DQMB Inputs: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT5) -+ mvOsOutput(" Differential Clock Input: Yes \n"); -+ else -+ mvOsOutput(" Differential Clock Input: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT6) -+ mvOsOutput(" redundant Row Addressing: Yes \n"); -+ else -+ mvOsOutput(" redundant Row Addressing: No \n"); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ { -+ if (dimmInfo.dimmAttributes & BIT0) -+ mvOsOutput(" Buffered Addr/Control Input: Yes\n"); -+ else -+ mvOsOutput(" Buffered Addr/Control Input: No\n"); -+ -+ if (dimmInfo.dimmAttributes & BIT1) -+ mvOsOutput(" Registered Addr/Control Input: Yes\n"); -+ else -+ mvOsOutput(" Registered Addr/Control Input: No\n"); -+ -+ if (dimmInfo.dimmAttributes & BIT2) -+ mvOsOutput(" On-Card PLL (clock): Yes \n"); -+ else -+ mvOsOutput(" On-Card PLL (clock): No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT3) -+ mvOsOutput(" FET Switch On-Card Enabled: Yes \n"); -+ else -+ mvOsOutput(" FET Switch On-Card Enabled: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT4) -+ mvOsOutput(" FET Switch External Enabled: Yes \n"); -+ else -+ mvOsOutput(" FET Switch External Enabled: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT5) -+ mvOsOutput(" Differential Clock Input: Yes \n"); -+ else -+ mvOsOutput(" Differential Clock Input: No \n"); -+ } -+ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ -+ { -+ mvOsOutput(" Number of Active Registers on the DIMM: %d\n", -+ (dimmInfo.dimmAttributes & 0x3) + 1); -+ -+ mvOsOutput(" Number of PLLs on the DIMM: %d\n", -+ ((dimmInfo.dimmAttributes) >> 2) & 0x3); -+ -+ if (dimmInfo.dimmAttributes & BIT4) -+ mvOsOutput(" FET Switch External Enabled: Yes \n"); -+ else -+ mvOsOutput(" FET Switch External Enabled: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT6) -+ mvOsOutput(" Analysis probe installed: Yes \n"); -+ else -+ mvOsOutput(" Analysis probe installed: No \n"); -+ } -+ -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 22: /* Suported AutoPreCharge */ -+ mvOsOutput("\nModul Attributes (SPD Byte 22): \n"); -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ if ( spdRawData[i] & BIT0 ) -+ mvOsOutput(" Early Ras Precharge: Yes \n"); -+ else -+ mvOsOutput(" Early Ras Precharge: No \n"); -+ -+ if ( spdRawData[i] & BIT1 ) -+ mvOsOutput(" AutoPreCharge: Yes \n"); -+ else -+ mvOsOutput(" AutoPreCharge: No \n"); -+ -+ if ( spdRawData[i] & BIT2 ) -+ mvOsOutput(" Precharge All: Yes \n"); -+ else -+ mvOsOutput(" Precharge All: No \n"); -+ -+ if ( spdRawData[i] & BIT3 ) -+ mvOsOutput(" Write 1/ReadBurst: Yes \n"); -+ else -+ mvOsOutput(" Write 1/ReadBurst: No \n"); -+ -+ if ( spdRawData[i] & BIT4 ) -+ mvOsOutput(" lower VCC tolerance: 5%%\n"); -+ else -+ mvOsOutput(" lower VCC tolerance: 10%%\n"); -+ -+ if ( spdRawData[i] & BIT5 ) -+ mvOsOutput(" upper VCC tolerance: 5%%\n"); -+ else -+ mvOsOutput(" upper VCC tolerance: 10%%\n"); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ { -+ if ( spdRawData[i] & BIT0 ) -+ mvOsOutput(" Supports Weak Driver: Yes \n"); -+ else -+ mvOsOutput(" Supports Weak Driver: No \n"); -+ -+ if ( !(spdRawData[i] & BIT4) ) -+ mvOsOutput(" lower VCC tolerance: 0.2V\n"); -+ -+ if ( !(spdRawData[i] & BIT5) ) -+ mvOsOutput(" upper VCC tolerance: 0.2V\n"); -+ -+ if ( spdRawData[i] & BIT6 ) -+ mvOsOutput(" Concurrent Auto Preharge: Yes \n"); -+ else -+ mvOsOutput(" Concurrent Auto Preharge: No \n"); -+ -+ if ( spdRawData[i] & BIT7 ) -+ mvOsOutput(" Supports Fast AP: Yes \n"); -+ else -+ mvOsOutput(" Supports Fast AP: No \n"); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) -+ { -+ if ( spdRawData[i] & BIT0 ) -+ mvOsOutput(" Supports Weak Driver: Yes \n"); -+ else -+ mvOsOutput(" Supports Weak Driver: No \n"); -+ } -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 23: -+ /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */ -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ rightOfPoint = (spdRawData[i] & 0x0f) * 10; -+ -+ /* DDR2 addition of right of point */ -+ if ((spdRawData[i] & 0x0f) == 0xA) -+ { -+ rightOfPoint = 25; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xB) -+ { -+ rightOfPoint = 33; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xC) -+ { -+ rightOfPoint = 66; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xD) -+ { -+ rightOfPoint = 75; -+ } -+ -+ mvOsOutput("Minimum Cycle Time At 2nd highest CasLatancy" -+ "(0 = Not supported): %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint ); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 24: /* Clock To Data Out 2nd highest Cas Latency Value*/ -+ div = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? 10:100; -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / div; -+ rightOfPoint = time_tmp % div; -+ mvOsOutput("Clock To Data Out (2nd CL value): %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 25: -+ /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ leftOfPoint = (spdRawData[i] & 0xfc) >> 2; -+ rightOfPoint = (spdRawData[i] & 0x3) * 25; -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ rightOfPoint = (spdRawData[i] & 0x0f) * 10; -+ -+ /* DDR2 addition of right of point */ -+ if ((spdRawData[i] & 0x0f) == 0xA) -+ { -+ rightOfPoint = 25; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xB) -+ { -+ rightOfPoint = 33; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xC) -+ { -+ rightOfPoint = 66; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xD) -+ { -+ rightOfPoint = 75; -+ } -+ } -+ mvOsOutput("Minimum Cycle Time At 3rd highest CasLatancy" -+ "(0 = Not supported): %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint ); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 26: /* Clock To Data Out 3rd highest Cas Latency Value*/ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ leftOfPoint = (spdRawData[i] & 0xfc) >> 2; -+ rightOfPoint = (spdRawData[i] & 0x3) * 25; -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = 0; -+ rightOfPoint = time_tmp; -+ } -+ mvOsOutput("Clock To Data Out (3rd CL value): %d.%2d[ns]\n", -+ leftOfPoint, rightOfPoint ); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 27: /* Minimum Row Precharge Time */ -+ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; -+ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0xff : 0xfc; -+ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0x00 : 0x03; -+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); -+ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; -+ temp = ((leftOfPoint*100) + rightOfPoint);/* in 10ps Intervals*/ -+ trp_clocks = (temp + (busClkPs-1)) / busClkPs; -+ mvOsOutput("Minimum Row Precharge Time [ns]: %d.%d = " -+ "in Clk cycles %d\n", -+ leftOfPoint, rightOfPoint, trp_clocks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 28: /* Minimum Row Active to Row Active Time */ -+ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; -+ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0xff : 0xfc; -+ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0x00 : 0x03; -+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); -+ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; -+ temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ -+ trrd_clocks = (temp + (busClkPs-1)) / busClkPs; -+ mvOsOutput("Minimum Row Active -To- Row Active Delay [ns]: " -+ "%d.%d = in Clk cycles %d\n", -+ leftOfPoint, rightOfPoint, trp_clocks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 29: /* Minimum Ras-To-Cas Delay */ -+ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; -+ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0xff : 0xfc; -+ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0x00 : 0x03; -+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); -+ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; -+ temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ -+ trcd_clocks = (temp + (busClkPs-1) )/ busClkPs; -+ mvOsOutput("Minimum Ras-To-Cas Delay [ns]: %d.%d = " -+ "in Clk cycles %d\n", -+ leftOfPoint, rightOfPoint, trp_clocks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 30: /* Minimum Ras Pulse Width */ -+ tras_clocks = (cas2ps(spdRawData[i])+(busClkPs-1)) / busClkPs; -+ mvOsOutput("Minimum Ras Pulse Width [ns]: %d = " -+ "in Clk cycles %d\n", spdRawData[i], tras_clocks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 31: /* Module Bank Density */ -+ mvOsOutput("Module Bank Density (more than 1= Multisize-Module):"); -+ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ if (dimmInfo.dimmBankDensity & BIT0) -+ mvOsOutput("1GB, "); -+ if (dimmInfo.dimmBankDensity & BIT1) -+ mvOsOutput("8MB, "); -+ if (dimmInfo.dimmBankDensity & BIT2) -+ mvOsOutput("16MB, "); -+ if (dimmInfo.dimmBankDensity & BIT3) -+ mvOsOutput("32MB, "); -+ if (dimmInfo.dimmBankDensity & BIT4) -+ mvOsOutput("64MB, "); -+ if (dimmInfo.dimmBankDensity & BIT5) -+ mvOsOutput("128MB, "); -+ if (dimmInfo.dimmBankDensity & BIT6) -+ mvOsOutput("256MB, "); -+ if (dimmInfo.dimmBankDensity & BIT7) -+ mvOsOutput("512MB, "); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ { -+ if (dimmInfo.dimmBankDensity & BIT0) -+ mvOsOutput("1GB, "); -+ if (dimmInfo.dimmBankDensity & BIT1) -+ mvOsOutput("2GB, "); -+ if (dimmInfo.dimmBankDensity & BIT2) -+ mvOsOutput("16MB, "); -+ if (dimmInfo.dimmBankDensity & BIT3) -+ mvOsOutput("32MB, "); -+ if (dimmInfo.dimmBankDensity & BIT4) -+ mvOsOutput("64MB, "); -+ if (dimmInfo.dimmBankDensity & BIT5) -+ mvOsOutput("128MB, "); -+ if (dimmInfo.dimmBankDensity & BIT6) -+ mvOsOutput("256MB, "); -+ if (dimmInfo.dimmBankDensity & BIT7) -+ mvOsOutput("512MB, "); -+ } -+ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ -+ { -+ if (dimmInfo.dimmBankDensity & BIT0) -+ mvOsOutput("1GB, "); -+ if (dimmInfo.dimmBankDensity & BIT1) -+ mvOsOutput("2GB, "); -+ if (dimmInfo.dimmBankDensity & BIT2) -+ mvOsOutput("4GB, "); -+ if (dimmInfo.dimmBankDensity & BIT3) -+ mvOsOutput("8GB, "); -+ if (dimmInfo.dimmBankDensity & BIT4) -+ mvOsOutput("16GB, "); -+ if (dimmInfo.dimmBankDensity & BIT5) -+ mvOsOutput("128MB, "); -+ if (dimmInfo.dimmBankDensity & BIT6) -+ mvOsOutput("256MB, "); -+ if (dimmInfo.dimmBankDensity & BIT7) -+ mvOsOutput("512MB, "); -+ } -+ mvOsOutput("\n"); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 32: /* Address And Command Setup Time (measured in ns/1000) */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ rightOfPoint = (spdRawData[i] & 0x0f); -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ if(leftOfPoint > 7) -+ { -+ leftOfPoint *= -1; -+ } -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / 100; -+ rightOfPoint = time_tmp % 100; -+ } -+ mvOsOutput("Address And Command Setup Time [ns]: %d.%d\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 33: /* Address And Command Hold Time */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ rightOfPoint = (spdRawData[i] & 0x0f); -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ if(leftOfPoint > 7) -+ { -+ leftOfPoint *= -1; -+ } -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / 100; -+ rightOfPoint = time_tmp % 100; -+ } -+ mvOsOutput("Address And Command Hold Time [ns]: %d.%d\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 34: /* Data Input Setup Time */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ rightOfPoint = (spdRawData[i] & 0x0f); -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ if(leftOfPoint > 7) -+ { -+ leftOfPoint *= -1; -+ } -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / 100; -+ rightOfPoint = time_tmp % 100; -+ } -+ mvOsOutput("Data Input Setup Time [ns]: %d.%d\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 35: /* Data Input Hold Time */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ rightOfPoint = (spdRawData[i] & 0x0f); -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ if(leftOfPoint > 7) -+ { -+ leftOfPoint *= -1; -+ } -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / 100; -+ rightOfPoint = time_tmp % 100; -+ } -+ mvOsOutput("Data Input Hold Time [ns]: %d.%d\n\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 36: /* Relevant for DDR2 only: Write Recovery Time */ -+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> 2); -+ rightOfPoint = (spdRawData[i] & maskRightOfPoint) * 25; -+ mvOsOutput("Write Recovery Time [ns]: %d.%d\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ } -+ -+} -+ -+ -+/* -+ * translate ns.ns/10 coding of SPD timing values -+ * into ps unit values -+ */ -+/******************************************************************************* -+* cas2ps - Translate x.y ns parameter to pico-seconds values -+* -+* DESCRIPTION: -+* This function translates x.y nano seconds to its value in pico seconds. -+* For example 3.75ns will return 3750. -+* -+* INPUT: -+* spd_byte - DIMM SPD byte. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* value in pico seconds. -+* -+*******************************************************************************/ -+static MV_U32 cas2ps(MV_U8 spd_byte) -+{ -+ MV_U32 ns, ns10; -+ -+ /* isolate upper nibble */ -+ ns = (spd_byte >> 4) & 0x0F; -+ /* isolate lower nibble */ -+ ns10 = (spd_byte & 0x0F); -+ -+ if( ns10 < 10 ) { -+ ns10 *= 10; -+ } -+ else if( ns10 == 10 ) -+ ns10 = 25; -+ else if( ns10 == 11 ) -+ ns10 = 33; -+ else if( ns10 == 12 ) -+ ns10 = 66; -+ else if( ns10 == 13 ) -+ ns10 = 75; -+ else -+ { -+ mvOsOutput("cas2ps Err. unsupported cycle time.\n"); -+ } -+ -+ return (ns*1000 + ns10*10); -+} -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,191 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvDram -+#define __INCmvDram -+ -+#include "ddr1_2/mvDramIf.h" -+#include "twsi/mvTwsi.h" -+ -+#define MAX_DIMM_NUM 2 -+#define SPD_SIZE 128 -+ -+/* Dimm spd offsets */ -+#define DIMM_MEM_TYPE 2 -+#define DIMM_ROW_NUM 3 -+#define DIMM_COL_NUM 4 -+#define DIMM_MODULE_BANK_NUM 5 -+#define DIMM_DATA_WIDTH 6 -+#define DIMM_VOLT_IF 8 -+#define DIMM_MIN_CC_AT_MAX_CAS 9 -+#define DIMM_ERR_CHECK_TYPE 11 -+#define DIMM_REFRESH_INTERVAL 12 -+#define DIMM_SDRAM_WIDTH 13 -+#define DIMM_ERR_CHECK_DATA_WIDTH 14 -+#define DIMM_MIN_CLK_DEL 15 -+#define DIMM_BURST_LEN_SUP 16 -+#define DIMM_DEV_BANK_NUM 17 -+#define DIMM_SUP_CAL 18 -+#define DIMM_DDR2_TYPE_INFORMATION 20 /* DDR2 only */ -+#define DIMM_BUF_ADDR_CONT_IN 21 -+#define DIMM_MIN_CC_AT_MAX_CAS_MINUS1 23 -+#define DIMM_MIN_CC_AT_MAX_CAS_MINUS2 25 -+#define DIMM_MIN_ROW_PRECHARGE_TIME 27 -+#define DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE 28 -+#define DIMM_MIN_RAS_TO_CAS_DELAY 29 -+#define DIMM_MIN_RAS_PULSE_WIDTH 30 -+#define DIMM_BANK_DENSITY 31 -+#define DIMM_MIN_WRITE_RECOVERY_TIME 36 -+#define DIMM_MIN_WRITE_TO_READ_CMD_DELAY 37 -+#define DIMM_MIN_READ_TO_PRECH_CMD_DELAY 38 -+#define DIMM_MIN_REFRESH_TO_ACTIVATE_CMD 42 -+ -+/* Dimm Memory Type values */ -+#define DIMM_MEM_TYPE_SDRAM 0x4 -+#define DIMM_MEM_TYPE_DDR1 0x7 -+#define DIMM_MEM_TYPE_DDR2 0x8 -+ -+#define DIMM_MODULE_MANU_OFFS 64 -+#define DIMM_MODULE_MANU_SIZE 8 -+#define DIMM_MODULE_VEN_OFFS 73 -+#define DIMM_MODULE_VEN_SIZE 25 -+#define DIMM_MODULE_ID_OFFS 99 -+#define DIMM_MODULE_ID_SIZE 18 -+ -+/* enumeration for voltage levels. */ -+typedef enum _mvDimmVoltageIf -+{ -+ TTL_5V_TOLERANT, -+ LVTTL, -+ HSTL_1_5V, -+ SSTL_3_3V, -+ SSTL_2_5V, -+ VOLTAGE_UNKNOWN, -+} MV_DIMM_VOLTAGE_IF; -+ -+ -+/* enumaration for SDRAM CAS Latencies. */ -+typedef enum _mvDimmSdramCas -+{ -+ SD_CL_1 =1, -+ SD_CL_2, -+ SD_CL_3, -+ SD_CL_4, -+ SD_CL_5, -+ SD_CL_6, -+ SD_CL_7, -+ SD_FAULT -+}MV_DIMM_SDRAM_CAS; -+ -+ -+/* DIMM information structure */ -+typedef struct _mvDimmInfo -+{ -+ MV_MEMORY_TYPE memoryType; /* DDR or SDRAM */ -+ -+ MV_U8 spdRawData[SPD_SIZE]; /* Content of SPD-EEPROM copied 1:1 */ -+ -+ /* DIMM dimensions */ -+ MV_U32 numOfRowAddr; -+ MV_U32 numOfColAddr; -+ MV_U32 numOfModuleBanks; -+ MV_U32 dataWidth; -+ MV_U32 errorCheckType; /* ECC , PARITY..*/ -+ MV_U32 sdramWidth; /* 4,8,16 or 32 */ -+ MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ -+ MV_U32 burstLengthSupported; -+ MV_U32 numOfBanksOnEachDevice; -+ MV_U32 suportedCasLatencies; -+ MV_U32 refreshInterval; -+ MV_U32 dimmBankDensity; -+ MV_U32 dimmTypeInfo; /* DDR2 only */ -+ MV_U32 dimmAttributes; -+ -+ /* DIMM timing parameters */ -+ MV_U32 minCycleTimeAtMaxCasLatPs; -+ MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; -+ MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; -+ MV_U32 minRowPrechargeTime; -+ MV_U32 minRowActiveToRowActive; -+ MV_U32 minRasToCasDelay; -+ MV_U32 minRasPulseWidth; -+ MV_U32 minWriteRecoveryTime; /* DDR2 only */ -+ MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ -+ MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ -+ MV_U32 minRefreshToActiveCmd; /* DDR2 only */ -+ -+ /* Parameters calculated from the extracted DIMM information */ -+ MV_U32 size; /* 16,64,128,256 or 512 MByte in MB units */ -+ MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit in MB units */ -+ MV_U32 numberOfDevices; -+ -+} MV_DIMM_INFO; -+ -+ -+MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo); -+MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo); -+MV_VOID dimmSpdPrint(MV_U32 dimmNum); -+MV_STATUS dimmSpdCpy(MV_VOID); -+ -+#endif /* __INCmvDram */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,1599 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+/* includes */ -+#include "ddr1_2/mvDramIf.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+ -+ -+ -+#ifdef MV_DEBUG -+#define DB(x) x -+#else -+#define DB(x) -+#endif -+ -+/* DRAM bank presence encoding */ -+#define BANK_PRESENT_CS0 0x1 -+#define BANK_PRESENT_CS0_CS1 0x3 -+#define BANK_PRESENT_CS0_CS2 0x5 -+#define BANK_PRESENT_CS0_CS1_CS2 0x7 -+#define BANK_PRESENT_CS0_CS2_CS3 0xd -+#define BANK_PRESENT_CS0_CS2_CS3_CS4 0xf -+ -+/* locals */ -+static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin); -+#if defined(MV_INC_BOARD_DDIM) -+static void sdramDDr2OdtConfig(MV_DRAM_BANK_INFO *pBankInfo); -+static MV_U32 dunitCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas); -+static MV_U32 sdramModeRegCalc(MV_U32 minCas); -+static MV_U32 sdramExtModeRegCalc(MV_DRAM_BANK_INFO *pBankInfo); -+static MV_U32 sdramAddrCtrlRegCalc(MV_DRAM_BANK_INFO *pBankInfo); -+static MV_U32 sdramConfigRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk); -+static MV_U32 minCasCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk, -+ MV_U32 forcedCl); -+static MV_U32 sdramTimeCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, -+ MV_U32 minCas, MV_U32 busClk); -+static MV_U32 sdramTimeCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, -+ MV_U32 busClk); -+ -+/******************************************************************************* -+* mvDramIfDetect - Prepare DRAM interface configuration values. -+* -+* DESCRIPTION: -+* This function implements the full DRAM detection and timing -+* configuration for best system performance. -+* Since this routine runs from a ROM device (Boot Flash), its stack -+* resides on RAM, that might be the system DRAM. Changing DRAM -+* configuration values while keeping vital data in DRAM is risky. That -+* is why the function does not preform the configuration setting but -+* prepare those in predefined 32bit registers (in this case IDMA -+* registers are used) for other routine to perform the settings. -+* The function will call for board DRAM SPD information for each DRAM -+* chip select. The function will then analyze those SPD parameters of -+* all DRAM banks in order to decide on DRAM configuration compatible -+* for all DRAM banks. -+* The function will set the CPU DRAM address decode registers. -+* Note: This routine prepares values that will overide configuration of -+* mvDramBasicAsmInit(). -+* -+* INPUT: -+* forcedCl - Forced CAL Latency. If equal to zero, do not force. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvDramIfDetect(MV_U32 forcedCl) -+{ -+ MV_U32 retVal = MV_OK; /* return value */ -+ MV_DRAM_BANK_INFO bankInfo[MV_DRAM_MAX_CS]; -+ MV_U32 busClk, size, base = 0, i, temp, deviceW, dimmW; -+ MV_U8 minCas; -+ MV_DRAM_DEC_WIN dramDecWin; -+ -+ dramDecWin.addrWin.baseHigh = 0; -+ -+ busClk = mvBoardSysClkGet(); -+ -+ if (0 == busClk) -+ { -+ mvOsPrintf("Dram: ERR. Can't detect system clock! \n"); -+ return MV_ERROR; -+ } -+ -+ /* Close DRAM banks except bank 0 (in case code is excecuting from it...) */ -+#if defined(MV_INCLUDE_SDRAM_CS1) -+ for(i= SDRAM_CS1; i < MV_DRAM_MAX_CS; i++) -+ mvCpuIfTargetWinEnable(i, MV_FALSE); -+#endif -+ -+ /* we will use bank 0 as the representative of the all the DRAM banks, */ -+ /* since bank 0 must exist. */ -+ for(i = 0; i < MV_DRAM_MAX_CS; i++) -+ { -+ /* if Bank exist */ -+ if(MV_OK == mvDramBankInfoGet(i, &bankInfo[i])) -+ { -+ /* check it isn't SDRAM */ -+ if(bankInfo[i].memoryType == MEM_TYPE_SDRAM) -+ { -+ mvOsPrintf("Dram: ERR. SDRAM type not supported !!!\n"); -+ return MV_ERROR; -+ } -+ /* All banks must support registry in order to activate it */ -+ if(bankInfo[i].registeredAddrAndControlInputs != -+ bankInfo[0].registeredAddrAndControlInputs) -+ { -+ mvOsPrintf("Dram: ERR. different Registered settings !!!\n"); -+ return MV_ERROR; -+ } -+ -+ /* Init the CPU window decode */ -+ /* Note that the size in Bank info is in MB units */ -+ /* Note that the Dimm width might be different then the device DRAM width */ -+ temp = MV_REG_READ(SDRAM_CONFIG_REG); -+ -+ deviceW = ((temp & SDRAM_DWIDTH_MASK) == SDRAM_DWIDTH_16BIT )? 16 : 32; -+ dimmW = bankInfo[0].dataWidth - (bankInfo[0].dataWidth % 16); -+ size = ((bankInfo[i].size << 20) / (dimmW/deviceW)); -+ -+ /* We can not change DRAM window settings while excecuting */ -+ /* code from it. That is why we skip the DRAM CS[0], saving */ -+ /* it to the ROM configuration routine */ -+ if(i == SDRAM_CS0) -+ { -+ MV_U32 sizeToReg; -+ -+ /* Translate the given window size to register format */ -+ sizeToReg = ctrlSizeToReg(size, SCSR_SIZE_ALIGNMENT); -+ -+ /* Size parameter validity check. */ -+ if (-1 == sizeToReg) -+ { -+ mvOsPrintf("mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n" -+ ,i); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Size is located at upper 16 bits */ -+ sizeToReg <<= SCSR_SIZE_OFFS; -+ -+ /* enable it */ -+ sizeToReg |= SCSR_WIN_EN; -+ -+ MV_REG_WRITE(DRAM_BUF_REG0, sizeToReg); -+ } -+ else -+ { -+ dramDecWin.addrWin.baseLow = base; -+ dramDecWin.addrWin.size = size; -+ dramDecWin.enable = MV_TRUE; -+ -+ if (MV_OK != mvDramIfWinSet(SDRAM_CS0 + i, &dramDecWin)) -+ { -+ mvOsPrintf("Dram: ERR. Fail to set bank %d!!!\n", -+ SDRAM_CS0 + i); -+ return MV_ERROR; -+ } -+ } -+ -+ base += size; -+ -+ /* update the suportedCasLatencies mask */ -+ bankInfo[0].suportedCasLatencies &= bankInfo[i].suportedCasLatencies; -+ -+ } -+ else -+ { -+ if( i == 0 ) /* bank 0 doesn't exist */ -+ { -+ mvOsPrintf("Dram: ERR. Fail to detect bank 0 !!!\n"); -+ return MV_ERROR; -+ } -+ else -+ { -+ DB(mvOsPrintf("Dram: Could not find bank %d\n", i)); -+ bankInfo[i].size = 0; /* Mark this bank as non exist */ -+ } -+ } -+ } -+ -+ /* calculate minimum CAS */ -+ minCas = minCasCalc(&bankInfo[0], busClk, forcedCl); -+ if (0 == minCas) -+ { -+ mvOsOutput("Dram: Warn: Could not find CAS compatible to SysClk %dMhz\n", -+ (busClk / 1000000)); -+ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ minCas = DDR2_CL_4; /* Continue with this CAS */ -+ mvOsPrintf("Set default CAS latency 4\n"); -+ } -+ else -+ { -+ minCas = DDR1_CL_3; /* Continue with this CAS */ -+ mvOsPrintf("Set default CAS latency 3\n"); -+ } -+ } -+ -+ /* calc SDRAM_CONFIG_REG and save it to temp register */ -+ temp = sdramConfigRegCalc(&bankInfo[0], busClk); -+ if(-1 == temp) -+ { -+ mvOsPrintf("Dram: ERR. sdramConfigRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG1, temp); -+ -+ /* calc SDRAM_MODE_REG and save it to temp register */ -+ temp = sdramModeRegCalc(minCas); -+ if(-1 == temp) -+ { -+ mvOsPrintf("Dram: ERR. sdramModeRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG2, temp); -+ -+ /* calc SDRAM_EXTENDED_MODE_REG and save it to temp register */ -+ temp = sdramExtModeRegCalc(&bankInfo[0]); -+ if(-1 == temp) -+ { -+ mvOsPrintf("Dram: ERR. sdramModeRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG10, temp); -+ -+ /* calc D_UNIT_CONTROL_LOW and save it to temp register */ -+ temp = dunitCtrlLowRegCalc(&bankInfo[0], minCas); -+ if(-1 == temp) -+ { -+ mvOsPrintf("Dram: ERR. dunitCtrlLowRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG3, temp); -+ -+ /* calc SDRAM_ADDR_CTRL_REG and save it to temp register */ -+ temp = sdramAddrCtrlRegCalc(&bankInfo[0]); -+ if(-1 == temp) -+ { -+ mvOsPrintf("Dram: ERR. sdramAddrCtrlRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG4, temp); -+ -+ /* calc SDRAM_TIMING_CTRL_LOW_REG and save it to temp register */ -+ temp = sdramTimeCtrlLowRegCalc(&bankInfo[0], minCas, busClk); -+ if(-1 == temp) -+ { -+ mvOsPrintf("Dram: ERR. sdramTimeCtrlLowRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG5, temp); -+ -+ /* calc SDRAM_TIMING_CTRL_HIGH_REG and save it to temp register */ -+ temp = sdramTimeCtrlHighRegCalc(&bankInfo[0], busClk); -+ if(-1 == temp) -+ { -+ mvOsPrintf("Dram: ERR. sdramTimeCtrlHighRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG6, temp); -+ -+ /* Config DDR2 On Die Termination (ODT) registers */ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ sdramDDr2OdtConfig(bankInfo); -+ } -+ -+ /* Note that DDR SDRAM Address/Control and Data pad calibration */ -+ /* settings is done in mvSdramIfConfig.s */ -+ -+ return retVal; -+} -+ -+/******************************************************************************* -+* minCasCalc - Calculate the Minimum CAS latency which can be used. -+* -+* DESCRIPTION: -+* Calculate the minimum CAS latency that can be used, base on the DRAM -+* parameters and the SDRAM bus Clock freq. -+* -+* INPUT: -+* busClk - the DRAM bus Clock. -+* pBankInfo - bank info parameters. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* The minimum CAS Latency. The function returns 0 if max CAS latency -+* supported by banks is incompatible with system bus clock frequancy. -+* -+*******************************************************************************/ -+static MV_U32 minCasCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk, -+ MV_U32 forcedCl) -+{ -+ MV_U32 count = 1, j; -+ MV_U32 busClkPs = 1000000000 / (busClk / 1000); /* in ps units */ -+ MV_U32 startBit, stopBit; -+ -+ /* DDR 1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * -+ *********************************************************/ -+ -+ /* DDR 2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * -+ *********************************************************/ -+ -+ -+ /* If we are asked to use the forced CAL */ -+ if (forcedCl) -+ { -+ mvOsPrintf("DRAM: Using forced CL %d.%d\n", (forcedCl / 10), -+ (forcedCl % 10)); -+ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ if (forcedCl == 30) -+ pBankInfo->suportedCasLatencies = 0x08; -+ else if (forcedCl == 40) -+ pBankInfo->suportedCasLatencies = 0x10; -+ else -+ { -+ mvOsPrintf("Forced CL %d.%d not supported. Set default CL 4\n", -+ (forcedCl / 10), (forcedCl % 10)); -+ pBankInfo->suportedCasLatencies = 0x10; -+ } -+ } -+ else -+ { -+ if (forcedCl == 15) -+ pBankInfo->suportedCasLatencies = 0x02; -+ else if (forcedCl == 20) -+ pBankInfo->suportedCasLatencies = 0x04; -+ else if (forcedCl == 25) -+ pBankInfo->suportedCasLatencies = 0x08; -+ else if (forcedCl == 30) -+ pBankInfo->suportedCasLatencies = 0x10; -+ else if (forcedCl == 40) -+ pBankInfo->suportedCasLatencies = 0x40; -+ else -+ { -+ mvOsPrintf("Forced CL %d.%d not supported. Set default CL 3\n", -+ (forcedCl / 10), (forcedCl % 10)); -+ pBankInfo->suportedCasLatencies = 0x10; -+ } -+ } -+ -+ return pBankInfo->suportedCasLatencies; -+ } -+ -+ /* go over the supported cas mask from Max Cas down and check if the */ -+ /* SysClk stands in its time requirments. */ -+ -+ -+ DB(mvOsPrintf("Dram: minCasCalc supported mask = %x busClkPs = %x \n", -+ pBankInfo->suportedCasLatencies,busClkPs )); -+ for(j = 7; j > 0; j--) -+ { -+ if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) -+ { -+ /* Reset the bits for CL incompatible for the sysClk */ -+ switch (count) -+ { -+ case 1: -+ if (pBankInfo->minCycleTimeAtMaxCasLatPs > busClkPs) -+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ case 2: -+ if (pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps > busClkPs) -+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ case 3: -+ if (pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps > busClkPs) -+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ default: -+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); -+ break; -+ } -+ } -+ } -+ -+ DB(mvOsPrintf("Dram: minCasCalc support = %x (after SysCC calc)\n", -+ pBankInfo->suportedCasLatencies )); -+ -+ /* SDRAM DDR1 controller supports CL 1.5 to 3.5 */ -+ /* SDRAM DDR2 controller supports CL 3 to 5 */ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ startBit = 3; /* DDR2 support CL start with CL3 (bit 3) */ -+ stopBit = 5; /* DDR2 support CL stops with CL5 (bit 5) */ -+ } -+ else -+ { -+ startBit = 1; /* DDR1 support CL start with CL1.5 (bit 3) */ -+ stopBit = 4; /* DDR1 support CL stops with CL3 (bit 4) */ -+ } -+ -+ for(j = startBit; j <= stopBit ; j++) -+ { -+ if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) -+ { -+ DB(mvOsPrintf("Dram: minCasCalc choose CAS %x \n",(BIT0 << j))); -+ return (BIT0 << j); -+ } -+ } -+ -+ return 0; -+} -+ -+/******************************************************************************* -+* sdramConfigRegCalc - Calculate sdram config register -+* -+* DESCRIPTION: Calculate sdram config register optimized value based -+* on the bank info parameters. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram config reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramConfigRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) -+{ -+ MV_U32 sdramConfig = 0; -+ MV_U32 refreshPeriod; -+ -+ busClk /= 1000000; /* we work with busClk in MHz */ -+ -+ sdramConfig = MV_REG_READ(SDRAM_CONFIG_REG); -+ -+ /* figure out the memory refresh internal */ -+ switch (pBankInfo->refreshInterval & 0xf) -+ { -+ case 0x0: /* refresh period is 15.625 usec */ -+ refreshPeriod = 15625; -+ break; -+ case 0x1: /* refresh period is 3.9 usec */ -+ refreshPeriod = 3900; -+ break; -+ case 0x2: /* refresh period is 7.8 usec */ -+ refreshPeriod = 7800; -+ break; -+ case 0x3: /* refresh period is 31.3 usec */ -+ refreshPeriod = 31300; -+ break; -+ case 0x4: /* refresh period is 62.5 usec */ -+ refreshPeriod = 62500; -+ break; -+ case 0x5: /* refresh period is 125 usec */ -+ refreshPeriod = 125000; -+ break; -+ default: /* refresh period undefined */ -+ mvOsPrintf("Dram: ERR. DRAM refresh period is unknown!\n"); -+ return -1; -+ } -+ -+ /* Now the refreshPeriod is in register format value */ -+ refreshPeriod = (busClk * refreshPeriod) / 1000; -+ -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc calculated refresh interval %0x\n", -+ refreshPeriod)); -+ -+ /* make sure the refresh value is only 14 bits */ -+ if(refreshPeriod > SDRAM_REFRESH_MAX) -+ { -+ refreshPeriod = SDRAM_REFRESH_MAX; -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc adjusted refresh interval %0x\n", -+ refreshPeriod)); -+ } -+ -+ /* Clear the refresh field */ -+ sdramConfig &= ~SDRAM_REFRESH_MASK; -+ -+ /* Set new value to refresh field */ -+ sdramConfig |= (refreshPeriod & SDRAM_REFRESH_MASK); -+ -+ /* registered DRAM ? */ -+ if ( pBankInfo->registeredAddrAndControlInputs ) -+ { -+ /* it's registered DRAM, so set the reg. DRAM bit */ -+ sdramConfig |= SDRAM_REGISTERED; -+ mvOsPrintf("DRAM Attribute: Registered address and control inputs.\n"); -+ } -+ -+ /* set DDR SDRAM devices configuration */ -+ sdramConfig &= ~SDRAM_DCFG_MASK; /* Clear Dcfg field */ -+ -+ switch (pBankInfo->sdramWidth) -+ { -+ case 8: /* memory is x8 */ -+ sdramConfig |= SDRAM_DCFG_X8_DEV; -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc SDRAM device width x8\n")); -+ break; -+ case 16: -+ sdramConfig |= SDRAM_DCFG_X16_DEV; -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc SDRAM device width x16\n")); -+ break; -+ default: /* memory width unsupported */ -+ mvOsPrintf("Dram: ERR. DRAM chip width is unknown!\n"); -+ return -1; -+ } -+ -+ /* Set static default settings */ -+ sdramConfig |= SDRAM_CONFIG_DV; -+ -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc set sdramConfig to 0x%x\n", -+ sdramConfig)); -+ -+ return sdramConfig; -+} -+ -+/******************************************************************************* -+* sdramModeRegCalc - Calculate sdram mode register -+* -+* DESCRIPTION: Calculate sdram mode register optimized value based -+* on the bank info parameters and the minCas. -+* -+* INPUT: -+* minCas - minimum CAS supported. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram mode reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramModeRegCalc(MV_U32 minCas) -+{ -+ MV_U32 sdramMode; -+ -+ sdramMode = MV_REG_READ(SDRAM_MODE_REG); -+ -+ /* Clear CAS Latency field */ -+ sdramMode &= ~SDRAM_CL_MASK; -+ -+ mvOsPrintf("DRAM CAS Latency "); -+ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ switch (minCas) -+ { -+ case DDR2_CL_3: -+ sdramMode |= SDRAM_DDR2_CL_3; -+ mvOsPrintf("3.\n"); -+ break; -+ case DDR2_CL_4: -+ sdramMode |= SDRAM_DDR2_CL_4; -+ mvOsPrintf("4.\n"); -+ break; -+ case DDR2_CL_5: -+ sdramMode |= SDRAM_DDR2_CL_5; -+ mvOsPrintf("5.\n"); -+ break; -+ default: -+ mvOsPrintf("\nsdramModeRegCalc ERROR: Max. CL out of range\n"); -+ return -1; -+ } -+ sdramMode |= DDR2_MODE_REG_DV; -+ } -+ else /* DDR1 */ -+ { -+ switch (minCas) -+ { -+ case DDR1_CL_1_5: -+ sdramMode |= SDRAM_DDR1_CL_1_5; -+ mvOsPrintf("1.5\n"); -+ break; -+ case DDR1_CL_2: -+ sdramMode |= SDRAM_DDR1_CL_2; -+ mvOsPrintf("2\n"); -+ break; -+ case DDR1_CL_2_5: -+ sdramMode |= SDRAM_DDR1_CL_2_5; -+ mvOsPrintf("2.5\n"); -+ break; -+ case DDR1_CL_3: -+ sdramMode |= SDRAM_DDR1_CL_3; -+ mvOsPrintf("3\n"); -+ break; -+ case DDR1_CL_4: -+ sdramMode |= SDRAM_DDR1_CL_4; -+ mvOsPrintf("4\n"); -+ break; -+ default: -+ mvOsPrintf("\nsdramModeRegCalc ERROR: Max. CL out of range\n"); -+ return -1; -+ } -+ sdramMode |= DDR1_MODE_REG_DV; -+ } -+ -+ DB(mvOsPrintf("nsdramModeRegCalc register 0x%x\n", sdramMode )); -+ -+ return sdramMode; -+} -+ -+/******************************************************************************* -+* sdramExtModeRegCalc - Calculate sdram Extended mode register -+* -+* DESCRIPTION: -+* Return sdram Extended mode register value based -+* on the bank info parameters and bank presence. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram Extended mode reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramExtModeRegCalc(MV_DRAM_BANK_INFO *pBankInfo) -+{ -+ MV_U32 populateBanks = 0; -+ int bankNum; -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ /* Represent the populate banks in binary form */ -+ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ if (0 != pBankInfo[bankNum].size) -+ { -+ populateBanks |= (1 << bankNum); -+ } -+ } -+ -+ switch(populateBanks) -+ { -+ case(BANK_PRESENT_CS0): -+ return DDR_SDRAM_EXT_MODE_CS0_DV; -+ -+ case(BANK_PRESENT_CS0_CS1): -+ return DDR_SDRAM_EXT_MODE_CS0_DV; -+ -+ case(BANK_PRESENT_CS0_CS2): -+ return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; -+ -+ case(BANK_PRESENT_CS0_CS1_CS2): -+ return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; -+ -+ case(BANK_PRESENT_CS0_CS2_CS3): -+ return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; -+ -+ case(BANK_PRESENT_CS0_CS2_CS3_CS4): -+ return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; -+ -+ default: -+ mvOsPrintf("sdramExtModeRegCalc: Invalid DRAM bank presence\n"); -+ return -1; -+ } -+ } -+ return 0; -+} -+ -+/******************************************************************************* -+* dunitCtrlLowRegCalc - Calculate sdram dunit control low register -+* -+* DESCRIPTION: Calculate sdram dunit control low register optimized value based -+* on the bank info parameters and the minCas. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* minCas - minimum CAS supported. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram dunit control low reg value. -+* -+*******************************************************************************/ -+static MV_U32 dunitCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas) -+{ -+ MV_U32 dunitCtrlLow; -+ -+ dunitCtrlLow = MV_REG_READ(SDRAM_DUNIT_CTRL_REG); -+ -+ /* Clear StBurstDel field */ -+ dunitCtrlLow &= ~SDRAM_ST_BURST_DEL_MASK; -+ -+#ifdef MV_88W8660 -+ /* Clear address/control output timing field */ -+ dunitCtrlLow &= ~SDRAM_CTRL_POS_RISE; -+#endif /* MV_88W8660 */ -+ -+ DB(mvOsPrintf("Dram: dunitCtrlLowRegCalc\n")); -+ -+ /* For proper sample of read data set the Dunit Control register's */ -+ /* stBurstDel bits [27:24] */ -+ /********-********-********-********-********-********* -+ * CL=1.5 | CL=2 | CL=2.5 | CL=3 | CL=4 | CL=5 * -+ *********-********-********-********-********-********* -+Not Reg. * 0011 | 0011 | 0100 | 0100 | 0101 | TBD * -+ *********-********-********-********-********-********* -+Registered * 0100 | 0100 | 0101 | 0101 | 0110 | TBD * -+ *********-********-********-********-********-*********/ -+ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ switch (minCas) -+ { -+ case DDR2_CL_3: -+ /* registerd DDR SDRAM? */ -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; -+ else -+ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; -+ break; -+ case DDR2_CL_4: -+ /* registerd DDR SDRAM? */ -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ dunitCtrlLow |= 0x6 << SDRAM_ST_BURST_DEL_OFFS; -+ else -+ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; -+ break; -+ default: -+ mvOsPrintf("Dram: dunitCtrlLowRegCalc Max. CL out of range %d\n", -+ minCas); -+ return -1; -+ } -+ } -+ else /* DDR1 */ -+ { -+ switch (minCas) -+ { -+ case DDR1_CL_1_5: -+ /* registerd DDR SDRAM? */ -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; -+ else -+ dunitCtrlLow |= 0x3 << SDRAM_ST_BURST_DEL_OFFS; -+ break; -+ case DDR1_CL_2: -+ /* registerd DDR SDRAM? */ -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; -+ else -+ dunitCtrlLow |= 0x3 << SDRAM_ST_BURST_DEL_OFFS; -+ break; -+ case DDR1_CL_2_5: -+ /* registerd DDR SDRAM? */ -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; -+ else -+ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; -+ break; -+ case DDR1_CL_3: -+ /* registerd DDR SDRAM? */ -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; -+ else -+ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; -+ break; -+ case DDR1_CL_4: -+ /* registerd DDR SDRAM? */ -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ dunitCtrlLow |= 0x6 << SDRAM_ST_BURST_DEL_OFFS; -+ else -+ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; -+ break; -+ default: -+ mvOsPrintf("Dram: dunitCtrlLowRegCalc Max. CL out of range %d\n", -+ minCas); -+ return -1; -+ } -+ -+ } -+ DB(mvOsPrintf("Dram: Reg dunit control low = %x\n", dunitCtrlLow )); -+ -+ return dunitCtrlLow; -+} -+ -+/******************************************************************************* -+* sdramAddrCtrlRegCalc - Calculate sdram address control register -+* -+* DESCRIPTION: Calculate sdram address control register optimized value based -+* on the bank info parameters and the minCas. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram address control reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramAddrCtrlRegCalc(MV_DRAM_BANK_INFO *pBankInfo) -+{ -+ MV_U32 addrCtrl = 0; -+ -+ /* Set Address Control register static configuration bits */ -+ addrCtrl = MV_REG_READ(SDRAM_ADDR_CTRL_REG); -+ -+ /* Set address control default value */ -+ addrCtrl |= SDRAM_ADDR_CTRL_DV; -+ -+ /* Clear DSize field */ -+ addrCtrl &= ~SDRAM_DSIZE_MASK; -+ -+ /* Note that density is in MB units */ -+ switch (pBankInfo->deviceDensity) -+ { -+ case 128: /* 128 Mbit */ -+ DB(mvOsPrintf("DRAM Device Density 128Mbit\n")); -+ addrCtrl |= SDRAM_DSIZE_128Mb; -+ break; -+ case 256: /* 256 Mbit */ -+ DB(mvOsPrintf("DRAM Device Density 256Mbit\n")); -+ addrCtrl |= SDRAM_DSIZE_256Mb; -+ break; -+ case 512: /* 512 Mbit */ -+ DB(mvOsPrintf("DRAM Device Density 512Mbit\n")); -+ addrCtrl |= SDRAM_DSIZE_512Mb; -+ break; -+ default: -+ mvOsPrintf("Dram: sdramAddrCtrl unsupported RAM-Device size %d\n", -+ pBankInfo->deviceDensity); -+ return -1; -+ } -+ -+ /* SDRAM address control */ -+ DB(mvOsPrintf("Dram: setting sdram address control with: %x \n", addrCtrl)); -+ -+ return addrCtrl; -+} -+ -+/******************************************************************************* -+* sdramTimeCtrlLowRegCalc - Calculate sdram timing control low register -+* -+* DESCRIPTION: -+* This function calculates sdram timing control low register -+* optimized value based on the bank info parameters and the minCas. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* busClk - Bus clock -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram timinf control low reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramTimeCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, -+ MV_U32 minCas, MV_U32 busClk) -+{ -+ MV_U32 tRp = 0; -+ MV_U32 tRrd = 0; -+ MV_U32 tRcd = 0; -+ MV_U32 tRas = 0; -+ MV_U32 tWr = 0; -+ MV_U32 tWtr = 0; -+ MV_U32 tRtp = 0; -+ -+ MV_U32 bankNum; -+ -+ busClk = busClk / 1000000; /* In MHz */ -+ -+ /* Scan all DRAM banks to find maximum timing values */ -+ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ tRp = MV_MAX(tRp, pBankInfo[bankNum].minRowPrechargeTime); -+ tRrd = MV_MAX(tRrd, pBankInfo[bankNum].minRowActiveToRowActive); -+ tRcd = MV_MAX(tRcd, pBankInfo[bankNum].minRasToCasDelay); -+ tRas = MV_MAX(tRas, pBankInfo[bankNum].minRasPulseWidth); -+ } -+ -+ /* Extract timing (in ns) from SPD value. We ignore the tenth ns part. */ -+ /* by shifting the data two bits right. */ -+ tRp = tRp >> 2; /* For example 0x50 -> 20ns */ -+ tRrd = tRrd >> 2; -+ tRcd = tRcd >> 2; -+ -+ /* Extract clock cycles from time parameter. We need to round up */ -+ tRp = ((busClk * tRp) / 1000) + (((busClk * tRp) % 1000) ? 1 : 0); -+ /* Micron work around for 133MHz */ -+ if (busClk == 133) -+ tRp += 1; -+ DB(mvOsPrintf("Dram Timing Low: tRp = %d ", tRp)); -+ tRrd = ((busClk * tRrd) / 1000) + (((busClk * tRrd) % 1000) ? 1 : 0); -+ /* JEDEC min reqeirments tRrd = 2 */ -+ if (tRrd < 2) -+ tRrd = 2; -+ DB(mvOsPrintf("tRrd = %d ", tRrd)); -+ tRcd = ((busClk * tRcd) / 1000) + (((busClk * tRcd) % 1000) ? 1 : 0); -+ DB(mvOsPrintf("tRcd = %d ", tRcd)); -+ tRas = ((busClk * tRas) / 1000) + (((busClk * tRas) % 1000) ? 1 : 0); -+ DB(mvOsPrintf("tRas = %d ", tRas)); -+ -+ /* tWr and tWtr is different for DDR1 and DDR2. tRtp is only for DDR2 */ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ /* Scan all DRAM banks to find maximum timing values */ -+ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ tWr = MV_MAX(tWr, pBankInfo[bankNum].minWriteRecoveryTime); -+ tWtr = MV_MAX(tWtr, pBankInfo[bankNum].minWriteToReadCmdDelay); -+ tRtp = MV_MAX(tRtp, pBankInfo[bankNum].minReadToPrechCmdDelay); -+ } -+ -+ /* Extract timing (in ns) from SPD value. We ignore the tenth ns */ -+ /* part by shifting the data two bits right. */ -+ tWr = tWr >> 2; /* For example 0x50 -> 20ns */ -+ tWtr = tWtr >> 2; -+ tRtp = tRtp >> 2; -+ -+ /* Extract clock cycles from time parameter. We need to round up */ -+ tWr = ((busClk * tWr) / 1000) + (((busClk * tWr) % 1000) ? 1 : 0); -+ DB(mvOsPrintf("tWr = %d ", tWr)); -+ tWtr = ((busClk * tWtr) / 1000) + (((busClk * tWtr) % 1000) ? 1 : 0); -+ /* JEDEC min reqeirments tWtr = 2 */ -+ if (tWtr < 2) -+ tWtr = 2; -+ DB(mvOsPrintf("tWtr = %d ", tWtr)); -+ tRtp = ((busClk * tRtp) / 1000) + (((busClk * tRtp) % 1000) ? 1 : 0); -+ /* JEDEC min reqeirments tRtp = 2 */ -+ if (tRtp < 2) -+ tRtp = 2; -+ DB(mvOsPrintf("tRtp = %d ", tRtp)); -+ } -+ else -+ { -+ tWr = ((busClk*SDRAM_TWR) / 1000) + (((busClk*SDRAM_TWR) % 1000)?1:0); -+ -+ if ((200 == busClk) || ((100 == busClk) && (DDR1_CL_1_5 == minCas))) -+ { -+ tWtr = 2; -+ } -+ else -+ { -+ tWtr = 1; -+ } -+ -+ tRtp = 2; /* Must be set to 0x1 (two cycles) when using DDR1 */ -+ } -+ -+ DB(mvOsPrintf("tWtr = %d\n", tWtr)); -+ -+ /* Note: value of 0 in register means one cycle, 1 means two and so on */ -+ return (((tRp - 1) << SDRAM_TRP_OFFS) | -+ ((tRrd - 1) << SDRAM_TRRD_OFFS) | -+ ((tRcd - 1) << SDRAM_TRCD_OFFS) | -+ ((tRas - 1) << SDRAM_TRAS_OFFS) | -+ ((tWr - 1) << SDRAM_TWR_OFFS) | -+ ((tWtr - 1) << SDRAM_TWTR_OFFS) | -+ ((tRtp - 1) << SDRAM_TRTP_OFFS)); -+} -+ -+/******************************************************************************* -+* sdramTimeCtrlHighRegCalc - Calculate sdram timing control high register -+* -+* DESCRIPTION: -+* This function calculates sdram timing control high register -+* optimized value based on the bank info parameters and the bus clock. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* busClk - Bus clock -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram timinf control high reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramTimeCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, -+ MV_U32 busClk) -+{ -+ MV_U32 tRfc; -+ MV_U32 timeNs = 0; -+ int bankNum; -+ MV_U32 sdramTw2wCyc = 0; -+ -+ busClk = busClk / 1000000; /* In MHz */ -+ -+ /* tRfc is different for DDR1 and DDR2. */ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ MV_U32 bankNum; -+ -+ /* Scan all DRAM banks to find maximum timing values */ -+ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ timeNs = MV_MAX(timeNs, pBankInfo[bankNum].minRefreshToActiveCmd); -+ } -+ else -+ { -+ if (pBankInfo[0].deviceDensity == _1G) -+ { -+ timeNs = SDRAM_TRFC_1G; -+ } -+ else -+ { -+ if (200 == busClk) -+ { -+ timeNs = SDRAM_TRFC_64_512M_AT_200MHZ; -+ } -+ else -+ { -+ timeNs = SDRAM_TRFC_64_512M; -+ } -+ } -+ } -+ -+ tRfc = ((busClk * timeNs) / 1000) + (((busClk * timeNs) % 1000) ? 1 : 0); -+ -+ DB(mvOsPrintf("Dram Timing High: tRfc = %d\n", tRfc)); -+ -+ -+ /* Represent the populate banks in binary form */ -+ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ if (0 != pBankInfo[bankNum].size) -+ sdramTw2wCyc++; -+ } -+ -+ /* If we have more the 1 bank then we need the TW2W in 1 for ODT switch */ -+ if (sdramTw2wCyc > 1) -+ sdramTw2wCyc = 1; -+ else -+ sdramTw2wCyc = 0; -+ -+ /* Note: value of 0 in register means one cycle, 1 means two and so on */ -+ return ((((tRfc - 1) & SDRAM_TRFC_MASK) << SDRAM_TRFC_OFFS) | -+ ((SDRAM_TR2R_CYC - 1) << SDRAM_TR2R_OFFS) | -+ ((SDRAM_TR2WW2R_CYC - 1) << SDRAM_TR2W_W2R_OFFS) | -+ (((tRfc - 1) >> 4) << SDRAM_TRFC_EXT_OFFS) | -+ (sdramTw2wCyc << SDRAM_TW2W_OFFS)); -+ -+} -+ -+/******************************************************************************* -+* sdramDDr2OdtConfig - Set DRAM DDR2 On Die Termination registers. -+* -+* DESCRIPTION: -+* This function config DDR2 On Die Termination (ODT) registers. -+* ODT configuration is done according to DIMM presence: -+* -+* Presence Ctrl Low Ctrl High Dunit Ctrl Ext Mode -+* CS0 0x84210000 0x00000000 0x0000780F 0x00000440 -+* CS0+CS1 0x84210000 0x00000000 0x0000780F 0x00000440 -+* CS0+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 -+* CS0+CS1+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 -+* CS0+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 -+* CS0+CS1+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 -+* -+* INPUT: -+* pBankInfo - bank info parameters. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* None -+*******************************************************************************/ -+static void sdramDDr2OdtConfig(MV_DRAM_BANK_INFO *pBankInfo) -+{ -+ MV_U32 populateBanks = 0; -+ MV_U32 odtCtrlLow, odtCtrlHigh, dunitOdtCtrl; -+ int bankNum; -+ -+ /* Represent the populate banks in binary form */ -+ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ if (0 != pBankInfo[bankNum].size) -+ { -+ populateBanks |= (1 << bankNum); -+ } -+ } -+ -+ switch(populateBanks) -+ { -+ case(BANK_PRESENT_CS0): -+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_DV; -+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_DV; -+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_DV; -+ break; -+ case(BANK_PRESENT_CS0_CS1): -+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_DV; -+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_DV; -+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_DV; -+ break; -+ case(BANK_PRESENT_CS0_CS2): -+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; -+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; -+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; -+ break; -+ case(BANK_PRESENT_CS0_CS1_CS2): -+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; -+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; -+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; -+ break; -+ case(BANK_PRESENT_CS0_CS2_CS3): -+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; -+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; -+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; -+ break; -+ case(BANK_PRESENT_CS0_CS2_CS3_CS4): -+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; -+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; -+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; -+ break; -+ default: -+ mvOsPrintf("sdramDDr2OdtConfig: Invalid DRAM bank presence\n"); -+ return; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG7, odtCtrlLow); -+ MV_REG_WRITE(DRAM_BUF_REG8, odtCtrlHigh); -+ MV_REG_WRITE(DRAM_BUF_REG9, dunitOdtCtrl); -+ return; -+} -+#endif /* defined(MV_INC_BOARD_DDIM) */ -+ -+/******************************************************************************* -+* mvDramIfWinSet - Set DRAM interface address decode window -+* -+* DESCRIPTION: -+* This function sets DRAM interface address decode window. -+* -+* INPUT: -+* target - System target. Use only SDRAM targets. -+* pAddrDecWin - SDRAM address window structure. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK -+* otherwise. -+*******************************************************************************/ -+MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) -+{ -+ MV_U32 baseReg=0,sizeReg=0; -+ MV_U32 baseToReg=0 , sizeToReg=0; -+ -+ /* Check parameters */ -+ if (!MV_TARGET_IS_DRAM(target)) -+ { -+ mvOsPrintf("mvDramIfWinSet: target %d is not SDRAM\n", target); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlaps with current enabled windows */ -+ if (MV_TRUE == sdramIfWinOverlap(target, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("mvDramIfWinSet: ERR. Target %d overlaps\n", target); -+ return MV_BAD_PARAM; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvDramIfWinSet:Error setting DRAM interface window %d."\ -+ "\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ target, -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ /* read base register*/ -+ baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(target)); -+ -+ /* read size register */ -+ sizeReg = MV_REG_READ(SDRAM_SIZE_REG(target)); -+ -+ /* BaseLow[31:16] => base register [31:16] */ -+ baseToReg = pAddrDecWin->addrWin.baseLow & SCBAR_BASE_MASK; -+ -+ /* Write to address decode Base Address Register */ -+ baseReg &= ~SCBAR_BASE_MASK; -+ baseReg |= baseToReg; -+ -+ /* Translate the given window size to register format */ -+ sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, SCSR_SIZE_ALIGNMENT); -+ -+ /* Size parameter validity check. */ -+ if (-1 == sizeToReg) -+ { -+ mvOsPrintf("mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n",target); -+ return MV_BAD_PARAM; -+ } -+ -+ /* set size */ -+ sizeReg &= ~SCSR_SIZE_MASK; -+ /* Size is located at upper 16 bits */ -+ sizeReg |= (sizeToReg << SCSR_SIZE_OFFS); -+ -+ /* enable/Disable */ -+ if (MV_TRUE == pAddrDecWin->enable) -+ { -+ sizeReg |= SCSR_WIN_EN; -+ } -+ else -+ { -+ sizeReg &= ~SCSR_WIN_EN; -+ } -+ -+ /* 3) Write to address decode Base Address Register */ -+ MV_REG_WRITE(SDRAM_BASE_ADDR_REG(target), baseReg); -+ -+ /* Write to address decode Size Register */ -+ MV_REG_WRITE(SDRAM_SIZE_REG(target), sizeReg); -+ -+ return MV_OK; -+} -+/******************************************************************************* -+* mvDramIfWinGet - Get DRAM interface address decode window -+* -+* DESCRIPTION: -+* This function gets DRAM interface address decode window. -+* -+* INPUT: -+* target - System target. Use only SDRAM targets. -+* -+* OUTPUT: -+* pAddrDecWin - SDRAM address window structure. -+* -+* RETURN: -+* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK -+* otherwise. -+*******************************************************************************/ -+MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) -+{ -+ MV_U32 baseReg,sizeReg; -+ MV_U32 sizeRegVal; -+ -+ /* Check parameters */ -+ if (!MV_TARGET_IS_DRAM(target)) -+ { -+ mvOsPrintf("mvDramIfWinGet: target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ /* Read base and size registers */ -+ sizeReg = MV_REG_READ(SDRAM_SIZE_REG(target)); -+ baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(target)); -+ -+ sizeRegVal = (sizeReg & SCSR_SIZE_MASK) >> SCSR_SIZE_OFFS; -+ -+ pAddrDecWin->addrWin.size = ctrlRegToSize(sizeRegVal, -+ SCSR_SIZE_ALIGNMENT); -+ -+ /* Check if ctrlRegToSize returned OK */ -+ if (-1 == pAddrDecWin->addrWin.size) -+ { -+ mvOsPrintf("mvDramIfWinGet: size of target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ /* Extract base address */ -+ /* Base register [31:16] ==> baseLow[31:16] */ -+ pAddrDecWin->addrWin.baseLow = baseReg & SCBAR_BASE_MASK; -+ -+ pAddrDecWin->addrWin.baseHigh = 0; -+ -+ -+ if (sizeReg & SCSR_WIN_EN) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ } -+ -+ return MV_OK; -+} -+/******************************************************************************* -+* mvDramIfWinEnable - Enable/Disable SDRAM address decode window -+* -+* DESCRIPTION: -+* This function enable/Disable SDRAM address decode window. -+* -+* INPUT: -+* target - System target. Use only SDRAM targets. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR in case function parameter are invalid, MV_OK otherewise. -+* -+*******************************************************************************/ -+MV_STATUS mvDramIfWinEnable(MV_TARGET target,MV_BOOL enable) -+{ -+ MV_DRAM_DEC_WIN addrDecWin; -+ -+ /* Check parameters */ -+ if (!MV_TARGET_IS_DRAM(target)) -+ { -+ mvOsPrintf("mvDramIfWinEnable: target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ if (enable == MV_TRUE) -+ { /* First check for overlap with other enabled windows */ -+ if (MV_OK != mvDramIfWinGet(target, &addrDecWin)) -+ { -+ mvOsPrintf("mvDramIfWinEnable:ERR. Getting target %d failed.\n", -+ target); -+ return MV_ERROR; -+ } -+ /* Check for overlapping */ -+ if (MV_FALSE == sdramIfWinOverlap(target, &(addrDecWin.addrWin))) -+ { -+ /* No Overlap. Enable address decode winNum window */ -+ MV_REG_BIT_SET(SDRAM_SIZE_REG(target), SCSR_WIN_EN); -+ } -+ else -+ { /* Overlap detected */ -+ mvOsPrintf("mvDramIfWinEnable: ERR. Target %d overlap detect\n", -+ target); -+ return MV_ERROR; -+ } -+ } -+ else -+ { /* Disable address decode winNum window */ -+ MV_REG_BIT_RESET(SDRAM_SIZE_REG(target), SCSR_WIN_EN); -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* sdramIfWinOverlap - Check if an address window overlap an SDRAM address window -+* -+* DESCRIPTION: -+* This function scan each SDRAM address decode window to test if it -+* overlapps the given address windoow -+* -+* INPUT: -+* target - SDRAM target where the function skips checking. -+* pAddrDecWin - The tested address window for overlapping with -+* SDRAM windows. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlaps any enabled address -+* decode map, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_TARGET targetNum; -+ MV_DRAM_DEC_WIN addrDecWin; -+ -+ for(targetNum = SDRAM_CS0; targetNum < MV_DRAM_MAX_CS ; targetNum++) -+ { -+ /* don't check our winNum or illegal targets */ -+ if (targetNum == target) -+ { -+ continue; -+ } -+ -+ /* Get window parameters */ -+ if (MV_OK != mvDramIfWinGet(targetNum, &addrDecWin)) -+ { -+ mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); -+ return MV_ERROR; -+ } -+ -+ /* Do not check disabled windows */ -+ if (MV_FALSE == addrDecWin.enable) -+ { -+ continue; -+ } -+ -+ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) -+ { -+ mvOsPrintf( -+ "sdramIfWinOverlap: Required target %d overlap winNum %d\n", -+ target, targetNum); -+ return MV_TRUE; -+ } -+ } -+ -+ return MV_FALSE; -+} -+ -+/******************************************************************************* -+* mvDramIfBankSizeGet - Get DRAM interface bank size. -+* -+* DESCRIPTION: -+* This function returns the size of a given DRAM bank. -+* -+* INPUT: -+* bankNum - Bank number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* DRAM bank size. If bank is disabled the function return '0'. In case -+* or paramter is invalid, the function returns -1. -+* -+*******************************************************************************/ -+MV_32 mvDramIfBankSizeGet(MV_U32 bankNum) -+{ -+ MV_DRAM_DEC_WIN addrDecWin; -+ -+ /* Check parameters */ -+ if (!MV_TARGET_IS_DRAM(bankNum)) -+ { -+ mvOsPrintf("mvDramIfBankBaseGet: bankNum %d is invalid\n", bankNum); -+ return -1; -+ } -+ /* Get window parameters */ -+ if (MV_OK != mvDramIfWinGet(bankNum, &addrDecWin)) -+ { -+ mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); -+ return -1; -+ } -+ -+ if (MV_TRUE == addrDecWin.enable) -+ { -+ return addrDecWin.addrWin.size; -+ } -+ else -+ { -+ return 0; -+ } -+} -+ -+ -+/******************************************************************************* -+* mvDramIfSizeGet - Get DRAM interface total size. -+* -+* DESCRIPTION: -+* This function get the DRAM total size. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* DRAM total size. In case or paramter is invalid, the function -+* returns -1. -+* -+*******************************************************************************/ -+MV_32 mvDramIfSizeGet(MV_VOID) -+{ -+ MV_U32 totalSize = 0, bankSize = 0, bankNum; -+ -+ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ bankSize = mvDramIfBankSizeGet(bankNum); -+ -+ if (-1 == bankSize) -+ { -+ mvOsPrintf("Dram: mvDramIfSizeGet error with bank %d \n",bankNum); -+ return -1; -+ } -+ else -+ { -+ totalSize += bankSize; -+ } -+ } -+ -+ DB(mvOsPrintf("Dram: Total DRAM size is 0x%x \n",totalSize)); -+ -+ return totalSize; -+} -+ -+/******************************************************************************* -+* mvDramIfBankBaseGet - Get DRAM interface bank base. -+* -+* DESCRIPTION: -+* This function returns the 32 bit base address of a given DRAM bank. -+* -+* INPUT: -+* bankNum - Bank number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* DRAM bank size. If bank is disabled or paramter is invalid, the -+* function returns -1. -+* -+*******************************************************************************/ -+MV_32 mvDramIfBankBaseGet(MV_U32 bankNum) -+{ -+ MV_DRAM_DEC_WIN addrDecWin; -+ -+ /* Check parameters */ -+ if (!MV_TARGET_IS_DRAM(bankNum)) -+ { -+ mvOsPrintf("mvDramIfBankBaseGet: bankNum %d is invalid\n", bankNum); -+ return -1; -+ } -+ /* Get window parameters */ -+ if (MV_OK != mvDramIfWinGet(bankNum, &addrDecWin)) -+ { -+ mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); -+ return -1; -+ } -+ -+ if (MV_TRUE == addrDecWin.enable) -+ { -+ return addrDecWin.addrWin.baseLow; -+ } -+ else -+ { -+ return -1; -+ } -+} -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,179 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvDramIfh -+#define __INCmvDramIfh -+ -+/* includes */ -+#include "ddr1_2/mvDramIfRegs.h" -+#include "ddr1_2/mvDramIfConfig.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+ -+/* defines */ -+/* DRAM Timing parameters */ -+#define SDRAM_TWR 15 /* ns tWr */ -+#define SDRAM_TRFC_64_512M_AT_200MHZ 70 /* ns tRfc for dens 64-512 @ 200MHz */ -+#define SDRAM_TRFC_64_512M 75 /* ns tRfc for dens 64-512 */ -+#define SDRAM_TRFC_1G 120 /* ns tRfc for dens 1GB */ -+#define SDRAM_TR2R_CYC 1 /* cycle for tR2r */ -+#define SDRAM_TR2WW2R_CYC 1 /* cycle for tR2wW2r */ -+ -+/* typedefs */ -+ -+/* enumeration for memory types */ -+typedef enum _mvMemoryType -+{ -+ MEM_TYPE_SDRAM, -+ MEM_TYPE_DDR1, -+ MEM_TYPE_DDR2 -+}MV_MEMORY_TYPE; -+ -+/* enumeration for DDR1 supported CAS Latencies */ -+typedef enum _mvDimmDdr1Cas -+{ -+ DDR1_CL_1_5 = 0x02, -+ DDR1_CL_2 = 0x04, -+ DDR1_CL_2_5 = 0x08, -+ DDR1_CL_3 = 0x10, -+ DDR1_CL_4 = 0x40, -+ DDR1_CL_FAULT -+} MV_DIMM_DDR1_CAS; -+ -+/* enumeration for DDR2 supported CAS Latencies */ -+typedef enum _mvDimmDdr2Cas -+{ -+ DDR2_CL_3 = 0x08, -+ DDR2_CL_4 = 0x10, -+ DDR2_CL_5 = 0x20, -+ DDR2_CL_FAULT -+} MV_DIMM_DDR2_CAS; -+ -+ -+typedef struct _mvDramBankInfo -+{ -+ MV_MEMORY_TYPE memoryType; /* DDR1, DDR2 or SDRAM */ -+ -+ /* DIMM dimensions */ -+ MV_U32 numOfRowAddr; -+ MV_U32 numOfColAddr; -+ MV_U32 dataWidth; -+ MV_U32 errorCheckType; /* ECC , PARITY..*/ -+ MV_U32 sdramWidth; /* 4,8,16 or 32 */ -+ MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ -+ MV_U32 burstLengthSupported; -+ MV_U32 numOfBanksOnEachDevice; -+ MV_U32 suportedCasLatencies; -+ MV_U32 refreshInterval; -+ -+ /* DIMM timing parameters */ -+ MV_U32 minCycleTimeAtMaxCasLatPs; -+ MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; -+ MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; -+ MV_U32 minRowPrechargeTime; -+ MV_U32 minRowActiveToRowActive; -+ MV_U32 minRasToCasDelay; -+ MV_U32 minRasPulseWidth; -+ MV_U32 minWriteRecoveryTime; /* DDR2 only */ -+ MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ -+ MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ -+ MV_U32 minRefreshToActiveCmd; /* DDR2 only */ -+ -+ /* Parameters calculated from the extracted DIMM information */ -+ MV_U32 size; -+ MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit */ -+ MV_U32 numberOfDevices; -+ -+ /* DIMM attributes (MV_TRUE for yes) */ -+ MV_BOOL registeredAddrAndControlInputs; -+ -+}MV_DRAM_BANK_INFO; -+ -+/* This structure describes CPU interface address decode window */ -+typedef struct _mvDramIfDecWin -+{ -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+}MV_DRAM_DEC_WIN; -+ -+#include "ddr1_2/mvDram.h" -+ -+/* mvDramIf.h API list */ -+MV_VOID mvDramIfBasicAsmInit(MV_VOID); -+MV_STATUS mvDramIfDetect(MV_U32 forcedCl); -+MV_VOID _mvDramIfConfig(MV_VOID); -+ -+MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); -+MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); -+MV_STATUS mvDramIfWinEnable(MV_TARGET target,MV_BOOL enable); -+MV_32 mvDramIfBankSizeGet(MV_U32 bankNum); -+MV_32 mvDramIfBankBaseGet(MV_U32 bankNum); -+MV_32 mvDramIfSizeGet(MV_VOID); -+ -+#if 0 -+MV_STATUS mvDramIfMbusCtrlSet(MV_XBAR_TARGET *pPizzaArbArray); -+MV_STATUS mvDramIfMbusToutSet(MV_U32 timeout, MV_BOOL enable); -+#endif -+ -+#endif /* __INCmvDramIfh */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfBasicInit.S linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfBasicInit.S ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfBasicInit.S 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfBasicInit.S 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,988 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#define MV_ASMLANGUAGE -+#include "mvSysHwConfig.h" -+#include "mvOsAsm.h" -+#include "mvBoardEnvSpec.h" -+#include "mvCpuIfRegs.h" -+#include "mvDramIfConfig.h" -+#include "mvDramIfRegs.h" -+#include "pex/mvPexRegs.h" -+#include "pci/mvPciRegs.h" -+#include "mvCtrlEnvSpec.h" -+#include "mvCtrlEnvAsm.h" -+#include "cpu/mvCpuArm.h" -+#include "mvCommon.h" -+ -+/* defines */ -+ -+#if !defined(MV_INC_BOARD_DDIM) -+.globl dramBoot1 -+dramBoot1: -+ .word 0 -+ -+/****************************************************************************** -+* -+* -+* -+* -+*******************************************************************************/ -+#if defined(DB_PRPMC) || defined(DB_PEX_PCI) || defined(DB_MNG) -+ -+/* PEX_PCI and PRPMC boards 256 MB*/ -+#define STATIC_SDRAM0_BANK0_SIZE 0x0fff0001 -+#define STATIC_SDRAM_CONFIG 0x03248400 -+#define STATIC_SDRAM_MODE 0x62 -+#define STATIC_DUNIT_CTRL_LOW 0x4041000 -+#define STATIC_SDRAM_ADDR_CTRL 0x00000020 -+#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220 -+#define STATIC_SDRAM_TIME_CTRL_HI 0x0000030F -+#define STATIC_SDRAM_ODT_CTRL_LOW 0x0 -+#define STATIC_SDRAM_ODT_CTRL_HI 0x0 -+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0 -+#define STATIC_SDRAM_EXT_MODE 0x0 -+ -+#elif defined(DB_FPGA) -+ -+/* FPGA DC boards 256 MB*/ -+#define STATIC_SDRAM0_BANK0_SIZE 0x0fff0001 -+#define STATIC_SDRAM_CONFIG 0x03208400 /* 32bit */ -+#define STATIC_SDRAM_MODE 0x22 -+#define STATIC_DUNIT_CTRL_LOW 0x03041000 -+#define STATIC_SDRAM_ADDR_CTRL 0x00000020 -+#define STATIC_SDRAM_TIME_CTRL_LOW 0x11112220 -+#define STATIC_SDRAM_TIME_CTRL_HI 0x0000000D -+#define STATIC_SDRAM_ODT_CTRL_LOW 0x0 -+#define STATIC_SDRAM_ODT_CTRL_HI 0x0 -+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0 -+#define STATIC_SDRAM_EXT_MODE 0x1 -+ -+#elif defined(RD_88F6183GP) || defined(DB_CUSTOMER) -+ -+/* Customer 1 DDR2 2 devices 512Mbit by 16 bit */ -+#define STATIC_SDRAM0_BANK0_SIZE 0x07ff0001 -+#define STATIC_SDRAM_CONFIG 0x03158400 -+#define STATIC_SDRAM_MODE 0x452 -+#define STATIC_DUNIT_CTRL_LOW 0x06041000 -+#define STATIC_SDRAM_ADDR_CTRL 0x00000020 -+#define STATIC_SDRAM_TIME_CTRL_LOW 0x11912220 -+#define STATIC_SDRAM_TIME_CTRL_HI 0x00000502 -+#define STATIC_SDRAM_ODT_CTRL_LOW 0x00010000 -+#define STATIC_SDRAM_ODT_CTRL_HI 0x00000002 -+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x00000601 -+#define STATIC_SDRAM_EXT_MODE 0x00000440 -+ -+ -+#elif defined(RD_88F6183AP) -+ -+/* DDR2 1 devices 512Mbit by 16 bit */ -+#define STATIC_SDRAM0_BANK0_SIZE 0x03ff0001 -+#define STATIC_SDRAM_CONFIG 0x1f154400 -+#define STATIC_SDRAM_MODE 0x432 -+#define STATIC_DUNIT_CTRL_LOW 0x04041000 -+#define STATIC_SDRAM_ADDR_CTRL 0x00000020 -+#define STATIC_SDRAM_TIME_CTRL_LOW 0x11912220 -+#define STATIC_SDRAM_TIME_CTRL_HI 0x00000502 -+#define STATIC_SDRAM_ODT_CTRL_LOW 0x00010000 -+#define STATIC_SDRAM_ODT_CTRL_HI 0x00000002 -+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x00000601 -+#define STATIC_SDRAM_EXT_MODE 0x00000440 -+ -+/* 6082L MARVELL DIMM */ -+#elif defined(DB_88F6082LBP) -+#define STATIC_SDRAM0_BANK0_SIZE 0x07ff0001 -+#define STATIC_SDRAM_CONFIG 0x7f158400 -+#define STATIC_SDRAM_MODE 0x432 -+#define STATIC_DUNIT_CTRL_LOW 0x04041040 -+#define STATIC_SDRAM_ADDR_CTRL 0x00000020 -+#define STATIC_SDRAM_TIME_CTRL_LOW 0x11612220 -+#define STATIC_SDRAM_TIME_CTRL_HI 0x00000501 -+#define STATIC_SDRAM_ODT_CTRL_LOW 0x00010000 -+#define STATIC_SDRAM_ODT_CTRL_HI 0x00000002 -+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x00000a01 -+#define STATIC_SDRAM_EXT_MODE 0x00000440 -+ -+#elif defined(RD_88W8660_AP82S) -+ -+/* Shark RD */ -+ -+#if defined(MV_DRAM_32M) -+#define STATIC_SDRAM0_BANK0_SIZE 0x01ff0001 -+#define STATIC_SDRAM_ADDR_CTRL 0x00000010 -+#elif defined(MV_DRAM_16M) -+ -+#define STATIC_SDRAM0_BANK0_SIZE 0x00ff0001 -+#define STATIC_SDRAM_ADDR_CTRL 0x00000000 -+ -+#else -+#error "NO DDR size selected" -+#endif -+ -+#define STATIC_SDRAM_CONFIG 0x03144400 -+#define STATIC_SDRAM_MODE 0x62 -+#define STATIC_DUNIT_CTRL_LOW 0x4041000 -+ -+#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220 -+#define STATIC_SDRAM_TIME_CTRL_HI 0x0000040b -+#define STATIC_SDRAM_ODT_CTRL_LOW 0x0 -+#define STATIC_SDRAM_ODT_CTRL_HI 0x0 -+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0 -+#define STATIC_SDRAM_EXT_MODE 0x0 -+ -+#elif defined(RD_88W8660) -+ -+/* Shark RD */ -+#define STATIC_SDRAM0_BANK0_SIZE 0x03ff0001 -+#define STATIC_SDRAM_CONFIG 0x03144400 -+#define STATIC_SDRAM_MODE 0x62 -+#define STATIC_DUNIT_CTRL_LOW 0x4041000 -+#define STATIC_SDRAM_ADDR_CTRL 0x00000010 -+#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220 -+#define STATIC_SDRAM_TIME_CTRL_HI 0x0000040b -+#define STATIC_SDRAM_ODT_CTRL_LOW 0x0 -+#define STATIC_SDRAM_ODT_CTRL_HI 0x0 -+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0 -+#define STATIC_SDRAM_EXT_MODE 0x0 -+ -+#else /* NAS */ -+ -+ -+#if defined(RD_88F5182) -+ -+#if defined(MV_88F5082) -+#define STATIC_SDRAM0_BANK0_SIZE 0x3ff0001 -+#define STATIC_SDRAM_ADDR_CTRL 0x20 -+#else -+#define STATIC_SDRAM0_BANK0_SIZE 0x7ff0001 -+#define STATIC_SDRAM_ADDR_CTRL 0x20 -+#endif -+ -+#elif defined(RD_88F5182_3) -+ -+#if defined(MV_88F5082) -+#define STATIC_SDRAM0_BANK0_SIZE 0x3ff0001 -+#define STATIC_SDRAM_ADDR_CTRL 0x20 -+#else -+#define STATIC_SDRAM0_BANK0_SIZE 0x7ff0001 -+#define STATIC_SDRAM_ADDR_CTRL 0x20 -+#endif -+ -+#else -+ -+#define STATIC_SDRAM0_BANK0_SIZE 0x1ff0001 -+#define STATIC_SDRAM_ADDR_CTRL 0x0 -+ -+#endif -+ -+#if defined(MV_88F5082) -+#define STATIC_SDRAM_CONFIG 0x3144400 -+#else -+#define STATIC_SDRAM_CONFIG 0x3148400 -+#endif -+#define STATIC_SDRAM_MODE 0x62 -+#define STATIC_DUNIT_CTRL_LOW 0x4041000 -+#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220 -+#define STATIC_SDRAM_TIME_CTRL_HI 0x40c -+#define STATIC_SDRAM_ODT_CTRL_LOW 0x0 -+#define STATIC_SDRAM_ODT_CTRL_HI 0x0 -+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0 -+#define STATIC_SDRAM_EXT_MODE 0x0 -+ -+#endif -+ -+ .globl _mvDramIfStaticInit -+_mvDramIfStaticInit: -+ -+ mov r11, LR /* Save link register */ -+ mov r10, r2 -+ -+ /* If we boot from NAND jump to DRAM sddress */ -+ -+ mov r5, #1 -+ ldr r6, =dramBoot1 -+ str r5, [r6] /* We started executing from DRAM */ -+ -+ ldr r6, dramBoot1 -+ cmp r6, #0 -+ bne 1f -+ -+ -+ /* set all dram windows to 0 */ -+ mov r6, #0 -+ MV_REG_WRITE_ASM(r6, r5, 0x1504) -+ MV_REG_WRITE_ASM(r6, r5, 0x150c) -+ MV_REG_WRITE_ASM(r6, r5, 0x1514) -+ MV_REG_WRITE_ASM(r6, r5, 0x151c) -+ -+ /* set all dram configuration in temp registers */ -+ ldr r6, = STATIC_SDRAM0_BANK0_SIZE -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG0) -+ ldr r6, = STATIC_SDRAM_CONFIG -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG1) -+ ldr r6, = STATIC_SDRAM_MODE -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG2) -+ ldr r6, = STATIC_DUNIT_CTRL_LOW -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG3) -+ ldr r6, = STATIC_SDRAM_ADDR_CTRL -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG4) -+ ldr r6, = STATIC_SDRAM_TIME_CTRL_LOW -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG5) -+ ldr r6, = STATIC_SDRAM_TIME_CTRL_HI -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG6) -+ ldr r6, = STATIC_SDRAM_ODT_CTRL_LOW -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG7) -+ ldr r6, = STATIC_SDRAM_ODT_CTRL_HI -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG8) -+ ldr r6, = STATIC_SDRAM_DUNIT_ODT_CTRL -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG9) -+ ldr r6, = STATIC_SDRAM_EXT_MODE -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG10) -+ -+ mov sp, #0 -+ bl _mvDramIfConfig -+1: -+ mov r2, r10 -+ mov PC, r11 /* r11 is saved link register */ -+ -+#else /* #if !defined(MV_INC_BOARD_DDIM) */ -+ -+.globl dramBoot1 -+dramBoot1: -+ .word 0 -+ -+/******************************************************************************* -+* mvDramIfBasicInit - Basic initialization of DRAM interface -+* -+* DESCRIPTION: -+* The function will initialize the DRAM for basic usage. The function -+* will use the TWSI assembly API to extract DIMM parameters according -+* to which DRAM interface will be initialized. -+* The function referes to the following DRAM parameters: -+* 1) DIMM is registered or not. -+* 2) DIMM width detection. -+* 3) DIMM density. -+* -+* INPUT: -+* r3 - required size for initial DRAM. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+* Note: -+* r4 holds I2C EEPROM address -+* r5 holds SDRAM register base address -+* r7 holds returned values -+* r8 holds SDRAM various configuration registers value. -+* r11 holds return function address. -+*******************************************************************************/ -+/* Setting the offsets of the I2C registers */ -+#define NUM_OF_ROWS_OFFSET 3 -+#define NUM_OF_COLS_OFFSET 4 -+#define NUM_OF_RANKS 5 -+#define SDRAM_WIDTH_OFFSET 13 -+#define NUM_OF_BANKS_OFFSET 17 -+#define SUPPORTED_CL_OFFSET 18 -+#define DIMM_TYPE_INFO_OFFSET 20 /* DDR2 only */ -+#define SDRAM_MODULES_ATTR_OFFSET 21 -+ -+#define DRAM_DEV_DENSITY_128M 0x080 -+#define DRAM_DEV_DENSITY_256M 0x100 -+#define DRAM_DEV_DENSITY_512M 0x200 -+ .globl _mvDramIfBasicInit -+ .extern _i2cInit -+ -+_mvDramIfBasicInit: -+ -+ mov r11, LR /* Save link register */ -+ -+ mov r5, #1 -+ ldr r8, =dramBoot1 -+ str r5, [r8] /* We started executing from DRAM */ -+ -+ /* If we boot from NAND jump to DRAM sddress */ -+ ldr r8, dramBoot1 -+ cmp r8, #0 -+ movne pc, r11 -+ -+ -+ -+ bl _i2cInit /* Initialize TWSI master */ -+ -+ /* Get default SDRAM Config values */ -+ MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG) -+ bic r8, r8, #SDRAM_DCFG_MASK -+ -+ -+ /* Read device ID */ -+ MV_CTRL_MODEL_GET_ASM(r4, r5); -+ -+ /* Return if OrionN */ -+ ldr r5, =MV_5180_DEV_ID -+ cmp r4, r5 -+ beq cat_through_end -+ -+ /* Return if Orion1 */ -+ ldr r5, =MV_5181_DEV_ID -+ cmp r4, r5 -+ beq cat_through_end -+ -+ /* Return if Nas */ -+ ldr r5, =MV_5182_DEV_ID -+ cmp r4, r5 -+ beq cat_through_end -+ -+ /* Return if Shark */ -+ ldr r5, =MV_8660_DEV_ID -+ cmp r4, r5 -+ beq cat_through_end -+ -+ /* goto calcConfigReg if bigger than Orion2*/ -+ ldr r5, =MV_5281_DEV_ID -+ cmp r4, r5 -+ bne cat_through -+ -+cat_through: -+ /* set cat through - for better performance - in orion2 b0 and higher*/ -+ orr r8, r8, #SDRAM_CATTHR_EN -+ -+cat_through_end: -+ -+ -+ /* Get registered/non registered info from DIMM */ -+ bl _is_Registered -+ beq nonRegistered -+ -+setRegistered: -+ orr r8, r8, #SDRAM_REGISTERED /* Set registered bit(17) */ -+ -+nonRegistered: -+ /* Get SDRAM width */ -+ bl _get_width -+ -+ orr r6, r8, #SDRAM_DCFG_X16_DEV /* x16 devices */ -+ cmp r7, #16 -+ beq setConfigReg -+ -+ orr r6, r8, #SDRAM_DCFG_X8_DEV /* x8 devices */ -+ cmp r7, #8 -+ beq setConfigReg -+ -+ /* This is an error. return */ -+ b exit_ddrAutoConfig -+ -+setConfigReg: -+ mov r8, r6 -+ ldr r6, =SDRAM_CONFIG_DV -+ orr r8, r8, r6 /* Add default settings */ -+ mov r6, r8 /* Do not swap r8 content */ -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_CONFIG_REG) -+ -+ /* Set maximum CL supported by DIMM */ -+ bl _get_CAL -+ -+ /* r7 is DIMM supported CAS (e.g: 3 --> 0x1C) */ -+ clz r6, r7 -+ rsb r6, r6, #31 /* r6 = the bit number of MAX CAS supported */ -+ -+ /* Check the DDR version */ -+ tst r8, #SDRAM_DTYPE_DDR2 -+ bne casDdr2 -+ -+casDdr1: -+ ldr r7, =3 /* stBurstDel field value */ -+ ldr r8, =0x52 /* Assuming MAX CL = 1.5 */ -+ cmp r6, #1 /* If CL = 1.5 break */ -+ beq setModeReg -+ -+ ldr r7, =3 /* stBurstDel field value */ -+ ldr r8, =0x22 /* Assuming MAX CL = 2 */ -+ cmp r6, #2 /* If CL = 2 break */ -+ beq setModeReg -+ -+ ldr r7, =4 /* stBurstDel field value */ -+ ldr r8, =0x62 /* Assuming MAX CL = 2.5 */ -+ cmp r6, #3 /* If CL = 2.5 break */ -+ beq setModeReg -+ -+ ldr r7, =4 /* stBurstDel field value */ -+ ldr r8, =0x32 /* Assuming MAX CL = 3 */ -+ cmp r6, #4 /* If CL = 3 break */ -+ beq setModeReg -+ -+ ldr r7, =5 /* stBurstDel field value */ -+ ldr r8, =0x42 /* Assuming MAX CL = 4 */ -+ cmp r6, #6 /* If CL = 4 break */ -+ b setModeReg -+ -+ b exit_ddrAutoConfig /* This is an error !! */ -+ -+casDdr2: -+ ldr r7, =4 /* stBurstDel field value */ -+ ldr r8, =0x32 /* Assuming MAX CL = 3 */ -+ cmp r6, #3 /* If CL = 3 break */ -+ beq casDdr2Cont -+ -+ ldr r7, =5 /* stBurstDel field value */ -+ ldr r8, =0x42 /* Assuming MAX CL = 4 */ -+ cmp r6, #4 /* If CL = 4 break */ -+ beq casDdr2Cont -+ -+ /* CL 5 currently unsupported. We use CL 4 instead */ -+ ldr r7, =5 /* stBurstDel field value */ -+ ldr r8, =0x42 /* Assuming MAX CL = 5 */ -+ cmp r6, #5 /* If CL = 5 break */ -+ beq casDdr2Cont -+ -+ b exit_ddrAutoConfig /* This is an error !! */ -+casDdr2Cont: -+ /* Write recovery for auto-precharge relevant only in DDR2 */ -+ orr r8, r8, #0x400 /* Default value */ -+ -+setModeReg: -+ /* The CPU must not attempt to change the SDRAM Mode register setting */ -+ /* prior to DRAM controller completion of the DRAM initialization */ -+ /* sequence. To guarantee this restriction, it is recommended that */ -+ /* the CPU sets the SDRAM Operation register to NOP command, performs */ -+ /* read polling until the register is back in Normal operation value, */ -+ /* and then sets SDRAM Mode register to it's new value. */ -+ -+ /* write 'nop' to SDRAM operation */ -+ mov r6, #0x5 /* 'NOP' command */ -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG) -+ -+ /* poll SDRAM operation. Make sure its back to normal operation */ -+_sdramOpPoll1: -+ ldr r6, [r5] -+ cmp r6, #0 /* '0' = Normal SDRAM Mode */ -+ bne _sdramOpPoll1 -+ -+ /* Now its safe to write new value to SDRAM Mode register */ -+ MV_REG_WRITE_ASM (r8, r5, SDRAM_MODE_REG) -+ -+ /* Make the Dunit write the DRAM its new mode */ -+ mov r6, #0x3 /* Mode Register Set command */ -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG) -+ -+ /* poll SDRAM operation. Make sure its back to normal operation */ -+_sdramOpPoll2: -+ ldr r6, [r5] -+ cmp r6, #0 /* '0' = Normal SDRAM Mode */ -+ bne _sdramOpPoll2 -+ -+ /* Set Dunit control register according to max CL detected */ -+ /* If we use registered DIMM, add 1 to stBurstDel */ -+ MV_REG_READ_ASM (r6, r5, SDRAM_CONFIG_REG) -+ tst r6, #SDRAM_REGISTERED -+ beq setDunitReg -+ add r7, r7, #1 -+ -+setDunitReg: -+ ldr r6, =SDRAM_DUNIT_CTRL_LOW_DV -+ orr r6, r6, r7, LSL #SDRAM_ST_BURST_DEL_OFFS -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) -+ -+ -+ /* DIMM density configuration*/ -+ /* Density = (1 << (rowNum + colNum)) * dramWidth * dramBankNum */ -+Density: -+ bl _getDensity -+ mov r8, r7 -+ mov r8, r8, LSR #20 /* Move density 20 bits to the right */ -+ /* For example 0x10000000 --> 0x1000 */ -+ -+ mov r6, #0x00 -+ cmp r8, #DRAM_DEV_DENSITY_128M -+ beq densCont -+ -+ mov r6, #0x10 -+ cmp r8, #DRAM_DEV_DENSITY_256M -+ beq densCont -+ -+ mov r6, #0x20 -+ cmp r8, #DRAM_DEV_DENSITY_512M -+ beq densCont -+ -+ /* This is an error. return */ -+ b exit_ddrAutoConfig -+ -+densCont: -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_REG) -+ -+ /* Config DDR2 registers (Extended mode, ODTs and pad calibration) */ -+ MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG) -+ tst r8, #SDRAM_DTYPE_DDR2 -+ beq _extModeODTEnd -+ -+ -+ /* Set DDR Extended Mode register for working with CS[0] */ -+ /* write 'nop' to SDRAM operation */ -+ mov r6, #0x5 /* 'NOP' command */ -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG) -+ -+ /* poll SDRAM operation. Make sure its back to normal operation */ -+_sdramOpPoll3: -+ ldr r6, [r5] -+ cmp r6, #0 /* '0' = Normal SDRAM Mode */ -+ bne _sdramOpPoll3 -+ -+ /* Now its safe to write new value to SDRAM Extended Mode register */ -+ ldr r6, =DDR_SDRAM_EXT_MODE_CS0_DV -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_EXTENDED_MODE_REG) -+ -+ /* Make the Dunit write the DRAM its new extended mode */ -+ mov r6, #0x4 /* Extended Mode Register Set command */ -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG) -+ -+ /* poll SDRAM operation. Make sure its back to normal operation */ -+_sdramOpPoll4: -+ ldr r6, [r5] -+ cmp r6, #0 /* '0' = Normal SDRAM Mode */ -+ bne _sdramOpPoll4 -+ -+ /* ODT configuration is done for single bank CS[0] only */ -+ /* Config DDR2 On Die Termination (ODT) registers */ -+ ldr r6, =DDR2_ODT_CTRL_LOW_CS0_DV -+ MV_REG_WRITE_ASM (r6, r5, DDR2_SDRAM_ODT_CTRL_LOW_REG) -+ -+ ldr r6, =DDR2_ODT_CTRL_HIGH_CS0_DV -+ MV_REG_WRITE_ASM (r6, r5, DDR2_SDRAM_ODT_CTRL_HIGH_REG) -+ -+ ldr r6, =DDR2_DUNIT_ODT_CTRL_CS0_DV -+ MV_REG_WRITE_ASM (r6, r5, DDR2_DUNIT_ODT_CONTROL_REG) -+ -+ -+ /* we will check what device we are running and perform -+ Initialization according to device value */ -+ -+_extModeODTEnd: -+ -+ /* Implement Guideline (GL# MEM-2) P_CAL Automatic Calibration */ -+ /* Does Not Work for Address/Control and Data Pads. */ -+ /* Relevant for: 88F5181-A1/B0 and 88F5281-A0 */ -+ -+ /* Read device ID */ -+ MV_CTRL_MODEL_GET_ASM(r6, r5); -+ /* Read device revision */ -+ MV_CTRL_REV_GET_ASM(r8, r5); -+ -+ /* Continue if OrionN */ -+ ldr r5, =MV_5180_DEV_ID -+ cmp r6, r5 -+ bne 1f -+ b glMem2End -+1: -+ -+ /* Continue if Orion1 and device revision B1 */ -+ ldr r5, =MV_5181_DEV_ID -+ cmp r6, r5 -+ bne 1f -+ -+ cmp r8, #MV_5181_B1_REV -+ bge glMem2End -+ b glMem2Start -+1: -+ -+ /* Orion NAS */ -+ ldr r5, =MV_5182_DEV_ID -+ cmp r6, r5 -+ beq glMem2Start -+ -+ /* Orion Shark */ -+ ldr r5, =MV_8660_DEV_ID -+ cmp r6, r5 -+ beq glMem2Start -+ -+ b glMem2End -+ -+glMem2Start: -+ -+ /* DDR SDRAM Address/Control Pads Calibration */ -+ MV_REG_READ_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) -+ -+ /* Set Bit [31] to make the register writable */ -+ orr r8, r6, #SDRAM_WR_EN -+ -+ MV_REG_WRITE_ASM (r8, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) -+ -+ bic r6, r6, #SDRAM_WR_EN /* Make register read-only */ -+ bic r6, r6, #SDRAM_TUNE_EN /* Disable auto calibration */ -+ bic r6, r6, #SDRAM_DRVN_MASK /* Clear r5[5:0] */ -+ bic r6, r6, #SDRAM_DRVP_MASK /* Clear r5[11:6] */ -+ -+ /* Get the final N locked value of driving strength [22:17] */ -+ mov r5, r6 -+ mov r5, r5, LSL #9 -+ mov r5, r5, LSR #26 /* r5[5:0] = r6[22:17] */ -+ orr r5, r5, r5, LSL #6 /* r5[11:6] = r5[5:0] */ -+ -+ /* Write to both bits [5:0] and bits [11:6] */ -+ orr r6, r6, r5 -+ -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) -+ -+ -+ /* DDR SDRAM Data Pads Calibration */ -+ MV_REG_READ_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG) -+ -+ /* Set Bit [31] to make the register writable */ -+ orr r8, r6, #SDRAM_WR_EN -+ -+ MV_REG_WRITE_ASM (r8, r5, SDRAM_DATA_PADS_CAL_REG) -+ -+ bic r6, r6, #SDRAM_WR_EN /* Make register read-only */ -+ bic r6, r6, #SDRAM_TUNE_EN /* Disable auto calibration */ -+ bic r6, r6, #SDRAM_DRVN_MASK /* Clear r5[5:0] */ -+ bic r6, r6, #SDRAM_DRVP_MASK /* Clear r5[11:6] */ -+ -+ /* Get the final N locked value of driving strength [22:17] */ -+ mov r5, r6 -+ mov r5, r5, LSL #9 -+ mov r5, r5, LSR #26 -+ orr r5, r5, r5, LSL #6 /* r5[5:0] = r6[22:17] */ -+ -+ /* Write to both bits [5:0] and bits [11:6] */ -+ orr r6, r6, r5 -+ -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG) -+ -+glMem2End: -+ /* Implement Guideline (GL# MEM-3) Drive Strength Value */ -+ /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */ -+ -+ /* Get SDRAM Config value */ -+ MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG) -+ -+ /* Get DIMM type */ -+ tst r8, #SDRAM_DTYPE_DDR2 -+ beq ddr1StrengthVal -+ -+ddr2StrengthVal: -+ ldr r4, =DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV -+ ldr r8, =DDR2_DATA_PAD_STRENGTH_TYPICAL_DV -+ b setDrvStrength -+ddr1StrengthVal: -+ ldr r4, =DDR1_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV -+ ldr r8, =DDR1_DATA_PAD_STRENGTH_TYPICAL_DV -+ -+setDrvStrength: -+ /* DDR SDRAM Address/Control Pads Calibration */ -+ MV_REG_READ_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) -+ -+ orr r6, r6, #SDRAM_WR_EN /* Make register writeable */ -+ -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) -+ HTOLL(r6,r5) -+ -+ bic r6, r6, #SDRAM_WR_EN /* Make register read-only */ -+ bic r6, r6, #SDRAM_PRE_DRIVER_STRENGTH_MASK -+ orr r6, r4, r6 /* Set default value for DDR */ -+ -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) -+ -+ -+ /* DDR SDRAM Data Pads Calibration */ -+ MV_REG_READ_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG) -+ -+ orr r6, r6, #SDRAM_WR_EN /* Make register writeable */ -+ -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG) -+ HTOLL(r6,r5) -+ -+ bic r6, r6, #SDRAM_WR_EN /* Make register read-only */ -+ bic r6, r6, #SDRAM_PRE_DRIVER_STRENGTH_MASK -+ orr r6, r8, r6 /* Set default value for DDR */ -+ -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG) -+ -+ -+ /* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */ -+ /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */ -+ /* Get the "sample on reset" register for the DDR frequancy */ -+ -+#if defined(MV_RUN_FROM_FLASH) -+ /* Calc the absolute address of the _cpuARMDDRCLK[] in the boot flash */ -+ ldr r7, = _cpuARMDDRCLK -+ ldr r4, =_start -+ ldr r4, [r4] -+ sub r7, r7, r4 -+ ldr r4, = Lrom_start_of_data -+ ldr r4, [r4] -+ add r7, r4, r7 -+#else -+ /* Calc the absolute address of the _cpuARMDDRCLK[] in the boot flash */ -+ ldr r7, = _cpuARMDDRCLK -+ ldr r4, =_start -+ sub r7, r7, r4 -+ add r7, r7, #CFG_MONITOR_BASE -+#endif -+ /* Get the "sample on reset" register for the DDR frequancy */ -+ MV_REG_READ_ASM (r4, r5, MPP_SAMPLE_AT_RESET) -+ ldr r5, =MSAR_ARMDDRCLCK_MASK -+ and r5, r4, r5 -+#if 0 /* YOTAM TO BE FIX */ -+ mov r5, r5, LSR #MSAR_ARMDDRCLCK_OFFS -+#endif -+ -+ /* Read device ID */ -+ MV_CTRL_MODEL_GET_ASM(r6, r8); -+ -+ /* Continue if TC90 */ -+ ldr r8, =MV_1281_DEV_ID -+ cmp r6, r6 -+ beq armClkMsb -+ -+ /* Continue if Orion2 */ -+ ldr r8, =MV_5281_DEV_ID -+ cmp r6, r8 -+#if 0 /* YOTAM TO BE FIX */ -+ bne 1f -+#endif -+ -+armClkMsb: -+#if 0 /* YOTAM TO BE FIX */ -+ tst r4, #MSAR_ARMDDRCLCK_H_MASK -+ beq 1f -+ orr r5, r5, #BIT4 -+1: -+ ldr r4, =MV_CPU_ARM_CLK_ELM_SIZE -+ mul r5, r4, r5 -+ add r7, r7, r5 -+ add r7, r7, #MV_CPU_ARM_CLK_DDR_OFF -+ ldr r5, [r7] -+#endif -+ -+ /* Get SDRAM Config value */ -+ MV_REG_READ_ASM (r8, r4, SDRAM_CONFIG_REG) -+ -+ /* Get DIMM type */ -+ tst r8, #SDRAM_DTYPE_DDR2 -+ beq ddr1FtdllVal -+ -+ddr2FtdllVal: -+ ldr r4, =FTDLL_DDR2_250MHZ -+ ldr r7, =_250MHz -+ cmp r5, r7 -+ beq setFtdllReg -+ ldr r4, =FTDLL_DDR2_200MHZ -+ ldr r7, =_200MHz -+ cmp r5, r7 -+ beq setFtdllReg -+ ldr r4, =FTDLL_DDR2_166MHZ -+ ldr r7, =_166MHz -+ cmp r5, r7 -+ beq setFtdllReg -+ ldr r4, =FTDLL_DDR2_133MHZ -+ b setFtdllReg -+ -+ddr1FtdllVal: -+ ldr r4, =FTDLL_DDR1_200MHZ -+ ldr r7, =_200MHz -+ cmp r5, r7 -+ beq setFtdllReg -+ ldr r4, =FTDLL_DDR1_166MHZ -+ ldr r7, =_166MHz -+ cmp r5, r7 -+ beq setFtdllReg -+ ldr r4, =FTDLL_DDR1_133MHZ -+ ldr r7, =_133MHz -+ cmp r5, r7 -+ beq setFtdllReg -+ ldr r4, =0 -+ -+setFtdllReg: -+ -+#if !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L) -+ MV_REG_READ_ASM (r8, r5, SDRAM_FTDLL_CONFIG_REG) -+ orr r8, r8, r4 -+ MV_REG_WRITE_ASM (r8, r5, SDRAM_FTDLL_CONFIG_REG) -+ bic r8, r8, #1 -+ MV_REG_WRITE_ASM (r8, r5, SDRAM_FTDLL_CONFIG_REG) -+#endif /* !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L)*/ -+ -+ -+setTimingReg: -+ /* Set default Timing parameters */ -+ MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG) -+ tst r8, #SDRAM_DTYPE_DDR2 -+ bne ddr2TimeParam -+ -+ddr1TimeParam: -+ ldr r6, =DDR1_TIMING_LOW_DV -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_LOW_REG) -+ ldr r6, =DDR1_TIMING_HIGH_DV -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_HIGH_REG) -+ b timeParamDone -+ -+ddr2TimeParam: -+ ldr r6, =DDR2_TIMING_LOW_DV -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_LOW_REG) -+ ldr r6, =DDR2_TIMING_HIGH_DV -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_HIGH_REG) -+ -+timeParamDone: -+ /* Open CS[0] window to requested size and enable it. Disable other */ -+ /* windows */ -+ ldr r6, =SCBAR_BASE_MASK -+ sub r3, r3, #1 -+ and r3, r3, r6 -+ orr r3, r3, #1 /* Enable bank */ -+ MV_REG_WRITE_ASM (r3, r5, SDRAM_SIZE_REG(0)) -+ ldr r6, =0 -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(1)) -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(2)) -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(3)) -+ -+exit_ddrAutoConfig: -+ mov PC, r11 /* r11 is saved link register */ -+ -+ -+/***************************************************************************************/ -+/* r4 holds I2C EEPROM address -+ * r7 holds I2C EEPROM offset parameter for i2cRead and its --> returned value -+ * r8 holds SDRAM various configuration registers value. -+ * r13 holds Link register -+ */ -+/**************************/ -+_getDensity: -+ mov r13, LR /* Save link register */ -+ -+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ -+ mov r7, #NUM_OF_ROWS_OFFSET /* offset 3 */ -+ bl _i2cRead -+ mov r8, r7 /* r8 save number of rows */ -+ -+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ -+ mov r7, #NUM_OF_COLS_OFFSET /* offset 4 */ -+ bl _i2cRead -+ add r8, r8, r7 /* r8 = number of rows + number of col */ -+ -+ mov r7, #0x1 -+ mov r8, r7, LSL r8 /* r8 = (1 << r8) */ -+ -+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ -+ mov r7, #SDRAM_WIDTH_OFFSET /* offset 13 */ -+ bl _i2cRead -+ mul r8, r7, r8 -+ -+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ -+ mov r7, #NUM_OF_BANKS_OFFSET /* offset 17 */ -+ bl _i2cRead -+ mul r7, r8, r7 -+ -+ mov PC, r13 -+ -+/**************************/ -+_get_width: -+ mov r13, LR /* Save link register */ -+ -+ /* Get SDRAM width (SPD offset 13) */ -+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ -+ mov r7, #SDRAM_WIDTH_OFFSET -+ bl _i2cRead /* result in r7 */ -+ -+ mov PC, r13 -+ -+/**************************/ -+_get_CAL: -+ mov r13, LR /* Save link register */ -+ -+ /* Set maximum CL supported by DIMM */ -+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ -+ mov r7, #SUPPORTED_CL_OFFSET /* offset 18 */ -+ bl _i2cRead -+ -+ mov PC, r13 -+ -+/**************************/ -+/* R8 - sdram configuration register. -+ * Return value in flag if no-registered then Z-flag is set -+ */ -+_is_Registered: -+ mov r13, LR /* Save link register */ -+ -+ /* Get registered/non registered info from DIMM */ -+ tst r8, #SDRAM_DTYPE_DDR2 -+ bne regDdr2 -+ -+regDdr1: -+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ -+ mov r7, #SDRAM_MODULES_ATTR_OFFSET -+ bl _i2cRead /* result in r7 */ -+ tst r7, #0x2 -+ b exit -+regDdr2: -+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ -+ mov r7, #DIMM_TYPE_INFO_OFFSET -+ bl _i2cRead /* result in r7 */ -+ tst r7, #0x11 /* DIMM type = regular RDIMM (0x01) */ -+ /* or Mini-RDIMM (0x10) */ -+exit: -+ mov PC, r13 -+ -+ -+#endif -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.S linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.S ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.S 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.S 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,668 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+/******************************************************************************* -+* mvDramIfBasicAsm.s -+* -+* DESCRIPTION: -+* Memory full detection and best timing configuration is done in -+* C code. C runtime environment requires a stack. This module API -+* initialize DRAM interface chip select 0 for basic functionality for -+* the use of stack. -+* The module API assumes DRAM information is stored in I2C EEPROM reside -+* in a given I2C address MV_BOARD_DIMM0_I2C_ADDR. The I2C EEPROM -+* internal data structure is assumed to be orgenzied in common DRAM -+* vendor SPD structure. -+* NOTE: DFCDL values are assumed to be already initialized prior to -+* this module API activity. -+* -+* -+* DEPENDENCIES: -+* None. -+* -+*******************************************************************************/ -+ -+/* includes */ -+#define MV_ASMLANGUAGE -+#include "mvOsAsm.h" -+#include "mvSysHwConfig.h" -+#include "mvDramIfRegs.h" -+#include "mvDramIfConfig.h" -+#include "mvCpuIfRegs.h" -+#include "pex/mvPexRegs.h" -+#include "pci/mvPciRegs.h" -+#include "mvCtrlEnvSpec.h" -+#include "mvCtrlEnvAsm.h" -+#include "cpu/mvCpuArm.h" -+#include "mvCommon.h" -+ -+/* defines */ -+ -+/* locals */ -+.data -+.globl _mvDramIfConfig -+ -+.text -+ -+/******************************************************************************* -+* _mvDramIfConfig - Basic DRAM interface initialization. -+* -+* DESCRIPTION: -+* The function will initialize the following DRAM parameters using the -+* values prepared by mvDramIfDetect routine. Values are located -+* in predefined registers. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+ -+_mvDramIfConfig: -+ -+ /* Save register on stack */ -+ cmp sp, #0 -+ beq no_stack_s -+save_on_stack: -+ stmdb sp!, {r1, r2, r3, r4, r7, r11} -+no_stack_s: -+ -+ /* 1) Write to SDRAM coniguration register */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG1) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + SDRAM_CONFIG_REG) -+ str r4, [r1] -+ -+ /* 2) Write Dunit control low register */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG3) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + SDRAM_DUNIT_CTRL_REG) -+ str r4, [r1] -+ -+ /* 3) Write SDRAM address control register */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG4) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + SDRAM_ADDR_CTRL_REG) -+ str r4, [r1] -+ -+ /* 4) Write SDRAM bank 0 size register */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG0) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + SDRAM_SIZE_REG(0)) -+ str r4, [r1] -+ -+ /* 5) Write SDRAM open pages control register */ -+ ldr r1, =(INTER_REGS_BASE + SDRAM_OPEN_PAGE_CTRL_REG) -+ ldr r4, =SDRAM_OPEN_PAGES_CTRL_REG_DV -+ str r4, [r1] -+ -+ /* 6) Write SDRAM timing Low register */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG5) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_LOW_REG) -+ str r4, [r1] -+ -+ /* 7) Write SDRAM timing High register */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG6) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_HIGH_REG) -+ str r4, [r1] -+ -+ /* 8) Write SDRAM mode register */ -+ /* The CPU must not attempt to change the SDRAM Mode register setting */ -+ /* prior to DRAM controller completion of the DRAM initialization */ -+ /* sequence. To guarantee this restriction, it is recommended that */ -+ /* the CPU sets the SDRAM Operation register to NOP command, performs */ -+ /* read polling until the register is back in Normal operation value, */ -+ /* and then sets SDRAM Mode register to it’s new value. */ -+ -+ /* 8.1 write 'nop' to SDRAM operation */ -+ mov r4, #0x5 /* 'NOP' command */ -+ MV_REG_WRITE_ASM(r4, r1, SDRAM_OPERATION_REG) -+ -+ /* 8.2 poll SDRAM operation. Make sure its back to normal operation */ -+_sdramOpPoll1: -+ ldr r4, [r1] -+ cmp r4, #0 /* '0' = Normal SDRAM Mode */ -+ bne _sdramOpPoll1 -+ -+ /* 8.3 Now its safe to write new value to SDRAM Mode register */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG2) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + SDRAM_MODE_REG) -+ str r4, [r1] -+ -+ /* 8.4 Make the Dunit write the DRAM its new mode */ -+ mov r4, #0x3 /* Mode Register Set command */ -+ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) -+ -+ /* 8.5 poll SDRAM operation. Make sure its back to normal operation */ -+_sdramOpPoll2: -+ ldr r4, [r1] -+ cmp r4, #0 /* '0' = Normal SDRAM Mode */ -+ bne _sdramOpPoll2 -+ -+#ifndef DB_FPGA -+ /* Config DDR2 registers (Extended mode, ODTs and pad calibration) */ -+ MV_REG_READ_ASM (r4, r1, SDRAM_CONFIG_REG) -+ tst r4, #SDRAM_DTYPE_DDR2 -+ beq _extModeODTEnd -+#endif /* DB_FPGA */ -+ -+ /* 9) Write SDRAM Extended mode register This operation should be */ -+ /* done for each memory bank */ -+ /* write 'nop' to SDRAM operation */ -+ mov r4, #0x5 /* 'NOP' command */ -+ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) -+ -+ /* poll SDRAM operation. Make sure its back to normal operation */ -+_sdramOpPoll3: -+ ldr r4, [r1] -+ cmp r4, #0 /* '0' = Normal SDRAM Mode */ -+ bne _sdramOpPoll3 -+ -+ /* Now its safe to write new value to SDRAM Extended Mode register */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG10) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + SDRAM_EXTENDED_MODE_REG) -+ str r4, [r1] -+ -+ /* Go over each of the Banks */ -+ ldr r3, =0 /* r3 = DRAM bank Num */ -+ -+extModeLoop: -+ /* Set the SDRAM Operation Control to each of the DRAM banks */ -+ mov r2, r3 /* Do not swap the bank counter value */ -+ MV_REG_WRITE_ASM (r2, r1, SDRAM_OPERATION_CTRL_REG) -+ -+ /* Make the Dunit write the DRAM its new mode */ -+ mov r4, #0x4 /* Extended Mode Register Set command */ -+ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) -+ -+ /* poll SDRAM operation. Make sure its back to normal operation */ -+_sdramOpPoll4: -+ ldr r4, [r1] -+ cmp r4, #0 /* '0' = Normal SDRAM Mode */ -+ bne _sdramOpPoll4 -+#ifndef DB_FPGA -+ add r3, r3, #1 -+ cmp r3, #4 /* 4 = Number of banks */ -+ bne extModeLoop -+ -+extModeEnd: -+ /* Config DDR2 On Die Termination (ODT) registers */ -+ /* Write SDRAM DDR2 ODT control low register */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG7) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_LOW_REG) -+ str r4, [r1] -+ -+ /* Write SDRAM DDR2 ODT control high register */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG8) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_HIGH_REG) -+ str r4, [r1] -+ -+ /* Write SDRAM DDR2 Dunit ODT control register */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG9) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + DDR2_DUNIT_ODT_CONTROL_REG) -+ str r4, [r1] -+ -+#endif /* DB_FPGA */ -+_extModeODTEnd: -+#ifndef DB_FPGA -+ /* Implement Guideline (GL# MEM-2) P_CAL Automatic Calibration */ -+ /* Does Not Work for Address/Control and Data Pads. */ -+ /* Relevant for: 88F5181-A1/B0 and 88F5281-A0 */ -+ -+ /* Read device ID */ -+ MV_CTRL_MODEL_GET_ASM(r3, r1); -+ /* Read device revision */ -+ MV_CTRL_REV_GET_ASM(r2, r1); -+ -+ /* Continue if OrionN */ -+ ldr r1, =MV_5180_DEV_ID -+ cmp r3, r1 -+ bne 1f -+ b glMem2End -+1: -+ /* Continue if Orion1 and device revision B1 */ -+ ldr r1, =MV_5181_DEV_ID -+ cmp r3, r1 -+ bne 1f -+ -+ cmp r2, #MV_5181_B1_REV -+ bge glMem2End -+ b glMem2Start -+1: -+ -+ /* Orion NAS */ -+ ldr r1, =MV_5182_DEV_ID -+ cmp r3, r1 -+ beq glMem2Start -+ -+ /* Orion NAS */ -+ ldr r1, =MV_5082_DEV_ID -+ cmp r3, r1 -+ beq glMem2Start -+ -+ /* Orion Shark */ -+ ldr r1, =MV_8660_DEV_ID -+ cmp r3, r1 -+ beq glMem2Start -+ -+ b glMem2End -+ -+glMem2Start: -+ -+ /* DDR SDRAM Address/Control Pads Calibration */ -+ MV_REG_READ_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) -+ -+ /* Set Bit [31] to make the register writable */ -+ orr r2, r3, #SDRAM_WR_EN -+ -+ MV_REG_WRITE_ASM (r2, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) -+ -+ bic r3, r3, #SDRAM_WR_EN /* Make register read-only */ -+ bic r3, r3, #SDRAM_TUNE_EN /* Disable auto calibration */ -+ bic r3, r3, #SDRAM_DRVN_MASK /* Clear r1[5:0] */ -+ bic r3, r3, #SDRAM_DRVP_MASK /* Clear r1[11:6] */ -+ -+ /* Get the final N locked value of driving strength [22:17] */ -+ mov r1, r3 -+ mov r1, r1, LSL #9 -+ mov r1, r1, LSR #26 /* r1[5:0] = r3[22:17] */ -+ orr r1, r1, r1, LSL #6 /* r1[11:6] = r1[5:0] */ -+ -+ /* Write to both bits [5:0] and bits [11:6] */ -+ orr r3, r3, r1 -+ -+ MV_REG_WRITE_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) -+ -+ -+ /* DDR SDRAM Data Pads Calibration */ -+ MV_REG_READ_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG) -+ -+ /* Set Bit [31] to make the register writable */ -+ orr r2, r3, #SDRAM_WR_EN -+ -+ MV_REG_WRITE_ASM (r2, r1, SDRAM_DATA_PADS_CAL_REG) -+ -+ bic r3, r3, #SDRAM_WR_EN /* Make register read-only */ -+ bic r3, r3, #SDRAM_TUNE_EN /* Disable auto calibration */ -+ bic r3, r3, #SDRAM_DRVN_MASK /* Clear r1[5:0] */ -+ bic r3, r3, #SDRAM_DRVP_MASK /* Clear r1[11:6] */ -+ -+ /* Get the final N locked value of driving strength [22:17] */ -+ mov r1, r3 -+ mov r1, r1, LSL #9 -+ mov r1, r1, LSR #26 -+ orr r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17] */ -+ -+ /* Write to both bits [5:0] and bits [11:6] */ -+ orr r3, r3, r1 -+ -+ MV_REG_WRITE_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG) -+ -+glMem2End: -+ -+ -+ /* Implement Guideline (GL# MEM-3) Drive Strength Value */ -+ /* Relevant for: 88F5181-A1/B0/B1, 88F5281-A0/B0/C/D, 88F5182, */ -+ /* 88F5082, 88F5181L, 88F6082/L, 88F6183, 88F6183L */ -+ -+ /* Get SDRAM Config value */ -+ MV_REG_READ_ASM (r2, r1, SDRAM_CONFIG_REG) -+ -+ /* Get DIMM type */ -+ tst r2, #SDRAM_DTYPE_DDR2 -+ beq ddr1StrengthVal -+ -+ddr2StrengthVal: -+ ldr r4, =DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV -+ ldr r2, =DDR2_DATA_PAD_STRENGTH_TYPICAL_DV -+ b setDrvStrength -+ddr1StrengthVal: -+ ldr r4, =DDR1_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV -+ ldr r2, =DDR1_DATA_PAD_STRENGTH_TYPICAL_DV -+ -+setDrvStrength: -+ /* DDR SDRAM Address/Control Pads Calibration */ -+ MV_REG_READ_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) -+ -+ orr r3, r3, #SDRAM_WR_EN /* Make register writeable */ -+ -+ MV_REG_WRITE_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) -+ HTOLL(r3,r1) -+ -+ bic r3, r3, #SDRAM_WR_EN /* Make register read-only */ -+ bic r3, r3, #SDRAM_PRE_DRIVER_STRENGTH_MASK -+ orr r3, r4, r3 /* Set default value for DDR */ -+ -+ MV_REG_WRITE_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) -+ -+ -+ /* DDR SDRAM Data Pads Calibration */ -+ MV_REG_READ_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG) -+ -+ orr r3, r3, #SDRAM_WR_EN /* Make register writeable */ -+ -+ MV_REG_WRITE_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG) -+ HTOLL(r3,r1) -+ -+ bic r3, r3, #SDRAM_WR_EN /* Make register read-only */ -+ bic r3, r3, #SDRAM_PRE_DRIVER_STRENGTH_MASK -+ orr r3, r2, r3 /* Set default value for DDR */ -+ -+ MV_REG_WRITE_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG) -+ -+#if !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L) -+ /* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */ -+ /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0/C/D, 88F5182 */ -+ /* 88F5082, 88F5181L, 88F6082/L */ -+ -+ /* Calc the absolute address of the _cpuARMDDRCLK[] in the boot flash */ -+ ldr r7, = _cpuARMDDRCLK -+ ldr r4, =_start -+ sub r7, r7, r4 -+ add r7, r7, #CFG_MONITOR_BASE -+ -+ /* Get the "sample on reset" register for the DDR frequancy */ -+ MV_REG_READ_ASM (r4, r1, MPP_SAMPLE_AT_RESET) -+ ldr r1, =MSAR_ARMDDRCLCK_MASK -+ and r1, r4, r1 -+#if 0 /* YOTAM TO BE FIX */ -+ mov r1, r1, LSR #MSAR_ARMDDRCLCK_OFFS -+#endif -+ -+ /* Read device ID */ -+ MV_CTRL_MODEL_GET_ASM(r3, r2); -+ -+ /* Continue if TC90 */ -+ ldr r2, =MV_1281_DEV_ID -+ cmp r3, r2 -+ beq armClkMsb -+ -+ /* Continue if Orion2 */ -+ ldr r2, =MV_5281_DEV_ID -+ cmp r3, r2 -+#if 0 /* YOTAM TO BE FIX */ -+ bne 1f -+#endif -+ -+armClkMsb: -+#if 0 /* YOTAM TO BE FIX */ -+ tst r4, #MSAR_ARMDDRCLCK_H_MASK -+ beq 1f -+ orr r1, r1, #BIT4 -+1: -+ ldr r4, =MV_CPU_ARM_CLK_ELM_SIZE -+ mul r1, r4, r1 -+ add r7, r7, r1 -+ add r7, r7, #MV_CPU_ARM_CLK_DDR_OFF -+ ldr r1, [r7] -+#endif -+ -+ /* Get SDRAM Config value */ -+ MV_REG_READ_ASM (r2, r4, SDRAM_CONFIG_REG) -+ -+ /* Get DIMM type */ -+ tst r2, #SDRAM_DTYPE_DDR2 -+ beq ddr1FtdllVal -+ -+ddr2FtdllVal: -+ ldr r2, =MV_5281_DEV_ID -+ cmp r3, r2 -+ bne 2f -+ MV_CTRL_REV_GET_ASM(r3, r2) -+ cmp r3, #MV_5281_D0_REV -+ beq orin2_d0_ddr2_ftdll_val -+ cmp r3, #MV_5281_D1_REV -+ beq orin2_d1_ddr2_ftdll_val -+ cmp r3, #MV_5281_D2_REV -+ beq orin2_d1_ddr2_ftdll_val -+ b ddr2_default_val -+ -+/* Set Orion 2 D1 ftdll values for DDR2 */ -+orin2_d1_ddr2_ftdll_val: -+ ldr r4, =FTDLL_DDR2_250MHZ_5281_D1 -+ ldr r7, =_250MHz -+ cmp r1, r7 -+ beq setFtdllReg -+ ldr r4, =FTDLL_DDR2_200MHZ_5281_D1 -+ ldr r7, =_200MHz -+ cmp r1, r7 -+ beq setFtdllReg -+ ldr r4, =FTDLL_DDR2_166MHZ_5281_D0 -+ ldr r7, =_166MHz -+ cmp r1, r7 -+ beq setFtdllReg -+ b ddr2_default_val -+ -+/* Set Orion 2 D0 ftdll values for DDR2 */ -+orin2_d0_ddr2_ftdll_val: -+ ldr r4, =FTDLL_DDR2_250MHZ_5281_D0 -+ ldr r7, =_250MHz -+ cmp r1, r7 -+ beq setFtdllReg -+ ldr r4, =FTDLL_DDR2_200MHZ_5281_D0 -+ ldr r7, =_200MHz -+ cmp r1, r7 -+ beq setFtdllReg -+ ldr r4, =FTDLL_DDR2_166MHZ_5281_D0 -+ ldr r7, =_166MHz -+ cmp r1, r7 -+ beq setFtdllReg -+ b ddr2_default_val -+2: -+ ldr r2, =MV_5182_DEV_ID -+ cmp r3, r2 -+ bne 3f -+ -+/* Set Orion nas ftdll values for DDR2 */ -+orin_nas_ftdll_val: -+ ldr r4, =FTDLL_DDR2_166MHZ_5182 -+ ldr r7, =_166MHz -+ cmp r1, r7 -+ beq setFtdllReg -+ -+/* default values for all other devices */ -+3: -+ddr2_default_val: -+ ldr r4, =FTDLL_DDR2_250MHZ -+ ldr r7, =_250MHz -+ cmp r1, r7 -+ beq setFtdllReg -+ ldr r4, =FTDLL_DDR2_200MHZ -+ ldr r7, =_200MHz -+ cmp r1, r7 -+ beq setFtdllReg -+ ldr r4, =FTDLL_DDR2_166MHZ -+ ldr r7, =_166MHz -+ cmp r1, r7 -+ beq setFtdllReg -+ ldr r4, =FTDLL_DDR2_133MHZ -+ ldr r7, =_133MHz -+ cmp r1, r7 -+ beq setFtdllReg -+ ldr r4, =0 -+ b setFtdllReg -+ -+ddr1FtdllVal: -+ ldr r2, =MV_5281_DEV_ID -+ cmp r3, r2 -+ bne 2f -+ MV_CTRL_REV_GET_ASM(r3, r2) -+ cmp r3, #MV_5281_D0_REV -+ bge orin2_ddr1_ftdll_val -+ b ddr1_default_val -+ -+/* Set Orion 2 D0 and above ftdll values for DDR1 */ -+orin2_ddr1_ftdll_val: -+ ldr r4, =FTDLL_DDR1_200MHZ_5281_D0 -+ ldr r7, =_200MHz -+ cmp r1, r7 -+ beq setFtdllReg -+ ldr r4, =FTDLL_DDR1_166MHZ_5281_D0 -+ ldr r7, =_166MHz -+ cmp r1, r7 -+ beq setFtdllReg -+ b ddr1_default_val -+2: -+ ldr r2, =MV_5181_DEV_ID -+ cmp r3, r2 -+ bne 3f -+ MV_CTRL_REV_GET_ASM(r3, r2) -+ cmp r3, #MV_5181_B1_REV -+ bge orin1_ddr1_ftdll_val -+ b ddr1_default_val -+ -+/* Set Orion 1 ftdll values for DDR1 */ -+orin1_ddr1_ftdll_val: -+ ldr r4, =FTDLL_DDR1_166MHZ_5181_B1 -+ ldr r7, =_166MHz -+ cmp r1, r7 -+ beq setFtdllReg -+3: -+ddr1_default_val: -+ ldr r4, =FTDLL_DDR1_133MHZ -+ ldr r7, =_133MHz -+ cmp r1, r7 -+ beq setFtdllReg -+ -+ ldr r4, =FTDLL_DDR1_166MHZ -+ ldr r7, =_166MHz -+ cmp r1, r7 -+ beq setFtdllReg -+ -+ ldr r4, =FTDLL_DDR1_200MHZ -+ ldr r7, =_200MHz -+ cmp r1, r7 -+ beq setFtdllReg -+ -+ ldr r4, =0 -+ -+setFtdllReg: -+ -+ MV_REG_WRITE_ASM (r4, r1, SDRAM_FTDLL_CONFIG_REG) -+ HTOLL(r4,r1) -+ bic r4, r4, #1 -+ MV_REG_WRITE_ASM (r4, r1, SDRAM_FTDLL_CONFIG_REG) -+ -+#endif /* !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L) */ -+#endif /* DB_FPGA */ -+ -+restoreTmpRegs: -+ /* Restore the registers we used to save the DDR detect values */ -+ -+ ldr r4, =DRAM_BUF_REG0_DV -+ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG0) -+ -+ ldr r4, =DRAM_BUF_REG1_DV -+ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG1) -+ -+ ldr r4, =DRAM_BUF_REG2_DV -+ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG2) -+ -+ ldr r4, =DRAM_BUF_REG3_DV -+ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG3) -+ -+ ldr r4, =DRAM_BUF_REG4_DV -+ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG4) -+ -+ ldr r4, =DRAM_BUF_REG5_DV -+ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG5) -+ -+ ldr r4, =DRAM_BUF_REG6_DV -+ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG6) -+ -+ ldr r4, =DRAM_BUF_REG7_DV -+ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG7) -+ -+ ldr r4, =DRAM_BUF_REG8_DV -+ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG8) -+ -+ ldr r4, =DRAM_BUF_REG9_DV -+ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG9) -+ -+ ldr r4, =DRAM_BUF_REG10_DV -+ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG10) -+ -+ -+ /* Restore registers */ -+ /* Save register on stack */ -+ cmp sp, #0 -+ beq no_stack_l -+load_from_stack: -+ ldmia sp!, {r1, r2, r3, r4, r7, r11} -+no_stack_l: -+ -+ mov pc, lr -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,192 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvDramIfConfigh -+#define __INCmvDramIfConfigh -+ -+/* includes */ -+ -+/* defines */ -+ -+/* registers defaults values */ -+ -+#define SDRAM_CONFIG_DV \ -+ (SDRAM_PERR_WRITE | \ -+ SDRAM_SRMODE | \ -+ SDRAM_SRCLK_GATED) -+ -+#define SDRAM_DUNIT_CTRL_LOW_DV \ -+ (SDRAM_CTRL_POS_RISE | \ -+ SDRAM_CLK1DRV_NORMAL | \ -+ SDRAM_LOCKEN_ENABLE) -+ -+#define SDRAM_ADDR_CTRL_DV 0 -+ -+#define SDRAM_TIMING_CTRL_LOW_REG_DV \ -+ ((0x2 << SDRAM_TRCD_OFFS) | \ -+ (0x2 << SDRAM_TRP_OFFS) | \ -+ (0x1 << SDRAM_TWR_OFFS) | \ -+ (0x0 << SDRAM_TWTR_OFFS) | \ -+ (0x5 << SDRAM_TRAS_OFFS) | \ -+ (0x1 << SDRAM_TRRD_OFFS)) -+/* TRFC 0x27, TW2W 0x1 */ -+#define SDRAM_TIMING_CTRL_HIGH_REG_DV (( 0x7 << SDRAM_TRFC_OFFS ) |\ -+ ( 0x2 << SDRAM_TRFC_EXT_OFFS) |\ -+ ( 0x1 << SDRAM_TW2W_OFFS)) -+ -+#define SDRAM_OPEN_PAGES_CTRL_REG_DV SDRAM_OPEN_PAGE_EN -+ -+/* DDR2 ODT default register values */ -+ -+/* Presence Ctrl Low Ctrl High Dunit Ctrl Ext Mode */ -+/* CS0 0x84210000 0x00000000 0x0000780F 0x00000440 */ -+/* CS0+CS1 0x84210000 0x00000000 0x0000780F 0x00000440 */ -+/* CS0+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -+/* CS0+CS1+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -+/* CS0+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -+/* CS0+CS1+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -+ -+#define DDR2_ODT_CTRL_LOW_CS0_DV 0x84210000 -+#define DDR2_ODT_CTRL_HIGH_CS0_DV 0x00000000 -+#define DDR2_DUNIT_ODT_CTRL_CS0_DV 0x0000780F -+#define DDR_SDRAM_EXT_MODE_CS0_DV 0x00000440 -+ -+#define DDR2_ODT_CTRL_LOW_CS0_CS2_DV 0x030C030C -+#define DDR2_ODT_CTRL_HIGH_CS0_CS2_DV 0x00000000 -+#define DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV 0x0000740F -+#define DDR_SDRAM_EXT_MODE_CS0_CS2_DV 0x00000404 -+ -+ -+/* DDR SDRAM Adderss/Control and Data Pads Calibration default values */ -+#define DDR1_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \ -+ (1 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) -+#define DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \ -+ (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) -+ -+ -+#define DDR1_DATA_PAD_STRENGTH_TYPICAL_DV \ -+ (1 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) -+#define DDR2_DATA_PAD_STRENGTH_TYPICAL_DV \ -+ (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) -+ -+/* DDR SDRAM Mode Register default value */ -+#define DDR1_MODE_REG_DV 0x00000000 -+#define DDR2_MODE_REG_DV 0x00000400 -+ -+/* DDR SDRAM Timing parameter default values */ -+#define DDR1_TIMING_LOW_DV 0x11602220 -+#define DDR1_TIMING_HIGH_DV 0x0000000d -+ -+#define DDR2_TIMING_LOW_DV 0x11812220 -+#define DDR2_TIMING_HIGH_DV 0x0000030f -+ -+/* For Guideline (GL# MEM-4) DQS Reference Delay Tuning */ -+#define FTDLL_DDR1_166MHZ ((0x1 << 0) | \ -+ (0x7F<< 12) | \ -+ (0x1 << 22)) -+ -+#define FTDLL_DDR1_133MHZ FTDLL_DDR1_166MHZ -+ -+#define FTDLL_DDR1_200MHZ ((0x1 << 0) | \ -+ (0x1 << 12) | \ -+ (0x3 << 14) | \ -+ (0x1 << 18) | \ -+ (0x1 << 22)) -+ -+ -+#define FTDLL_DDR2_166MHZ ((0x1 << 0) | \ -+ (0x1 << 12) | \ -+ (0x1 << 14) | \ -+ (0x1 << 16) | \ -+ (0x1 << 19) | \ -+ (0xF << 20)) -+ -+#define FTDLL_DDR2_133MHZ FTDLL_DDR2_166MHZ -+ -+#define FTDLL_DDR2_200MHZ ((0x1 << 0) | \ -+ (0x1 << 12) | \ -+ (0x1 << 14) | \ -+ (0x1 << 16) | \ -+ (0x1 << 19) | \ -+ (0xF << 20)) -+ -+#define FTDLL_DDR2_250MHZ 0x445001 -+ -+/* Orion 1 B1 and above */ -+#define FTDLL_DDR1_166MHZ_5181_B1 0x45D001 -+ -+/* Orion nas */ -+#define FTDLL_DDR2_166MHZ_5182 0x597001 -+ -+/* Orion 2 D0 and above */ -+#define FTDLL_DDR1_166MHZ_5281_D0 0x8D0001 -+#define FTDLL_DDR1_200MHZ_5281_D0 0x8D0001 -+#define FTDLL_DDR2_166MHZ_5281_D0 0x485001 -+#define FTDLL_DDR2_200MHZ_5281_D0 0x485001 -+#define FTDLL_DDR2_250MHZ_5281_D0 0x445001 -+#define FTDLL_DDR2_200MHZ_5281_D1 0x995001 -+#define FTDLL_DDR2_250MHZ_5281_D1 0x984801 -+ -+#endif /* __INCmvDramIfh */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,306 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvDramIfRegsh -+#define __INCmvDramIfRegsh -+ -+ -+/* DDR SDRAM Controller Address Decode Registers */ -+/* SDRAM CSn Base Address Register (SCBAR) */ -+#define SDRAM_BASE_ADDR_REG(csNum) (0x1500 + (csNum * 8)) -+#define SCBAR_BASE_OFFS 16 -+#define SCBAR_BASE_MASK (0xffff << SCBAR_BASE_OFFS) -+#define SCBAR_BASE_ALIGNMENT 0x10000 -+ -+/* SDRAM CSn Size Register (SCSR) */ -+#define SDRAM_SIZE_REG(csNum) (0x1504 + (csNum * 8)) -+#define SCSR_WIN_EN BIT0 -+#define SCSR_SIZE_OFFS 16 -+#define SCSR_SIZE_MASK (0xffff << SCSR_SIZE_OFFS) -+#define SCSR_SIZE_ALIGNMENT 0x10000 -+ -+/* configuration register */ -+#define SDRAM_CONFIG_REG 0x1400 -+#define SDRAM_REFRESH_OFFS 0 -+#define SDRAM_REFRESH_MAX 0x3000 -+#define SDRAM_REFRESH_MASK (SDRAM_REFRESH_MAX << SDRAM_REFRESH_OFFS) -+#define SDRAM_DWIDTH_OFFS 14 -+#define SDRAM_DWIDTH_MASK (3 << SDRAM_DWIDTH_OFFS) -+#define SDRAM_DWIDTH_16BIT (1 << SDRAM_DWIDTH_OFFS) -+#define SDRAM_DWIDTH_32BIT (2 << SDRAM_DWIDTH_OFFS) -+#define SDRAM_DTYPE_OFFS 16 -+#define SDRAM_DTYPE_MASK (1 << SDRAM_DTYPE_OFFS) -+#define SDRAM_DTYPE_DDR1 (0 << SDRAM_DTYPE_OFFS) -+#define SDRAM_DTYPE_DDR2 (1 << SDRAM_DTYPE_OFFS) -+#define SDRAM_REGISTERED (1 << 17) -+#define SDRAM_PERR_OFFS 18 -+#define SDRAM_PERR_MASK (1 << SDRAM_PERR_OFFS) -+#define SDRAM_PERR_NO_WRITE (0 << SDRAM_PERR_OFFS) -+#define SDRAM_PERR_WRITE (1 << SDRAM_PERR_OFFS) -+#define SDRAM_DCFG_OFFS 20 -+#define SDRAM_DCFG_MASK (0x3 << SDRAM_DCFG_OFFS) -+#define SDRAM_DCFG_X16_DEV (1 << SDRAM_DCFG_OFFS) -+#define SDRAM_DCFG_X8_DEV (2 << SDRAM_DCFG_OFFS) -+#define SDRAM_SRMODE (1 << 24) -+#define SDRAM_SRCLK_OFFS 25 -+#define SDRAM_SRCLK_MASK (1 << SDRAM_SRCLK_OFFS) -+#define SDRAM_SRCLK_KEPT (0 << SDRAM_SRCLK_OFFS) -+#define SDRAM_SRCLK_GATED (1 << SDRAM_SRCLK_OFFS) -+#define SDRAM_CATTH_OFFS 26 -+#define SDRAM_CATTHR_EN (1 << SDRAM_CATTH_OFFS) -+ -+ -+/* dunit control register */ -+#define SDRAM_DUNIT_CTRL_REG 0x1404 -+#define SDRAM_CTRL_POS_OFFS 6 -+#define SDRAM_CTRL_POS_FALL (0 << SDRAM_CTRL_POS_OFFS) -+#define SDRAM_CTRL_POS_RISE (1 << SDRAM_CTRL_POS_OFFS) -+#define SDRAM_CLK1DRV_OFFS 12 -+#define SDRAM_CLK1DRV_MASK (1 << SDRAM_CLK1DRV_OFFS) -+#define SDRAM_CLK1DRV_HIGH_Z (0 << SDRAM_CLK1DRV_OFFS) -+#define SDRAM_CLK1DRV_NORMAL (1 << SDRAM_CLK1DRV_OFFS) -+#define SDRAM_LOCKEN_OFFS 18 -+#define SDRAM_LOCKEN_MASK (1 << SDRAM_LOCKEN_OFFS) -+#define SDRAM_LOCKEN_DISABLE (0 << SDRAM_LOCKEN_OFFS) -+#define SDRAM_LOCKEN_ENABLE (1 << SDRAM_LOCKEN_OFFS) -+#define SDRAM_ST_BURST_DEL_OFFS 24 -+#define SDRAM_ST_BURST_DEL_MAX 0xf -+#define SDRAM_ST_BURST_DEL_MASK (SDRAM_ST_BURST_DEL_MAX< busClkPs) -+ { -+ mvOsOutput("Dram: ERR. Bank %d doesn't support memory clock!!!\n", i); -+ return MV_ERROR; -+ } -+ -+ /* All banks must support registry in order to activate it */ -+ if(bankInfo[i].registeredAddrAndControlInputs != -+ bankInfo[0].registeredAddrAndControlInputs) -+ { -+ mvOsOutput("Dram: ERR. different Registered settings !!!\n"); -+ return MV_ERROR; -+ } -+ -+ /* All banks must support same ECC mode */ -+ if(bankInfo[i].errorCheckType != -+ bankInfo[0].errorCheckType) -+ { -+ mvOsOutput("Dram: ERR. different ECC settings !!!\n"); -+ return MV_ERROR; -+ } -+ -+ } -+ else -+ { -+ if( i == 0 ) /* bank 0 doesn't exist */ -+ { -+ mvOsOutput("Dram: ERR. Fail to detect bank 0 !!!\n"); -+ return MV_ERROR; -+ } -+ else -+ { -+ DB(mvOsPrintf("Dram: Could not find bank %d\n", i)); -+ bankInfo[i].size = 0; /* Mark this bank as non exist */ -+ } -+ } -+ } -+ -+#ifdef MV_INCLUDE_SDRAM_CS2 -+ if (bankInfo[SDRAM_CS0].size < bankInfo[SDRAM_CS2].size) -+ { -+ MV_DRAM_CS_order[0] = SDRAM_CS2; -+ MV_DRAM_CS_order[1] = SDRAM_CS3; -+ MV_DRAM_CS_order[2] = SDRAM_CS0; -+ MV_DRAM_CS_order[3] = SDRAM_CS1; -+ DRAM_CS_Order[0] = SDRAM_CS2; -+ DRAM_CS_Order[1] = SDRAM_CS3; -+ DRAM_CS_Order[2] = SDRAM_CS0; -+ DRAM_CS_Order[3] = SDRAM_CS1; -+ -+ } -+ else -+#endif -+ { -+ MV_DRAM_CS_order[0] = SDRAM_CS0; -+ MV_DRAM_CS_order[1] = SDRAM_CS1; -+ DRAM_CS_Order[0] = SDRAM_CS0; -+ DRAM_CS_Order[1] = SDRAM_CS1; -+#ifdef MV_INCLUDE_SDRAM_CS2 -+ MV_DRAM_CS_order[2] = SDRAM_CS2; -+ MV_DRAM_CS_order[3] = SDRAM_CS3; -+ DRAM_CS_Order[2] = SDRAM_CS2; -+ DRAM_CS_Order[3] = SDRAM_CS3; -+#endif -+ } -+ -+ for(j = 0; j < MV_DRAM_MAX_CS; j++) -+ { -+ i = MV_DRAM_CS_order[j]; -+ -+ if (0 == bankInfo[i].size) -+ continue; -+ -+ /* Init the CPU window decode */ -+ /* Note that the Dimm width might be different then the device DRAM width */ -+#ifdef MV78XX0 -+ temp = MV_REG_READ(SDRAM_CONFIG_REG); -+ deviceW = ((temp & SDRAM_DWIDTH_MASK) == SDRAM_DWIDTH_32BIT )? 32 : 64; -+#else -+ deviceW = 16 /* KW family */; -+#endif -+ dimmW = bankInfo[0].dataWidth - (bankInfo[0].dataWidth % 16); -+ size = ((bankInfo[i].size << 20) / (dimmW/deviceW)); -+ -+ /* We can not change DRAM window settings while excecuting */ -+ /* code from it. That is why we skip the DRAM CS[0], saving */ -+ /* it to the ROM configuration routine */ -+ -+ numOfAllDevices += bankInfo[i].numberOfDevices; -+ if (i == MV_DRAM_CS_order[0]) -+ { -+ MV_U32 sizeToReg; -+ /* Translate the given window size to register format */ -+ sizeToReg = ctrlSizeToReg(size, SCSR_SIZE_ALIGNMENT); -+ /* Size parameter validity check. */ -+ if (-1 == sizeToReg) -+ { -+ mvOsOutput("DRAM: mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n" -+ ,i); -+ return MV_BAD_PARAM; -+ } -+ -+ DB(mvOsPrintf("Dram: Bank 0 Size - %x\n",sizeToReg);) -+ sizeToReg = (sizeToReg << SCSR_SIZE_OFFS); -+ sizeToReg |= SCSR_WIN_EN; -+ MV_REG_WRITE(DRAM_BUF_REG0, sizeToReg); -+ } -+ else -+ { -+ dramDecWin.addrWin.baseLow = base; -+ dramDecWin.addrWin.size = size; -+ dramDecWin.enable = MV_TRUE; -+ DB(mvOsPrintf("Dram: Enable window %d base 0x%x, size=0x%x\n",i, base, size)); -+ -+ /* Check if the DRAM size is more then 3GByte */ -+ if (base < 0xC0000000) -+ { -+ DB(mvOsPrintf("Dram: Enable window %d base 0x%x, size=0x%x\n",i, base, size)); -+ if (MV_OK != mvCpuIfTargetWinSet(i, &dramDecWin)) -+ { -+ mvOsPrintf("Dram: ERR. Fail to set bank %d!!!\n", SDRAM_CS0 + i); -+ return MV_ERROR; -+ } -+ } -+ } -+ -+ base += size; -+ -+ /* update the suportedCasLatencies mask */ -+ bankInfo[0].suportedCasLatencies &= bankInfo[i].suportedCasLatencies; -+ } -+ -+ /* calculate minimum CAS */ -+ minCas = minCasCalc(&bankInfo[0], &bankInfo[2], busClk, forcedCl); -+ if (0 == minCas) -+ { -+ mvOsOutput("Dram: Warn: Could not find CAS compatible to SysClk %dMhz\n", -+ (busClk / 1000000)); -+ -+ minCas = DDR2_CL_4; /* Continue with this CAS */ -+ mvOsOutput("Set default CAS latency 4\n"); -+ } -+ -+ /* calc SDRAM_CONFIG_REG and save it to temp register */ -+ temp = sdramConfigRegCalc(&bankInfo[0],&bankInfo[2], busClk); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. sdramConfigRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ -+ /* check if ECC is enabled by the user */ -+ if(eccDisable) -+ { -+ /* turn off ECC*/ -+ temp &= ~BIT18; -+ } -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG1, temp); -+ -+ /* calc SDRAM_MODE_REG and save it to temp register */ -+ temp = sdramModeRegCalc(minCas); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. sdramModeRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: sdramModeRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG2, temp); -+ -+ /* calc SDRAM_EXTENDED_MODE_REG and save it to temp register */ -+ temp = sdramExtModeRegCalc(&bankInfo[0], busClk); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. sdramExtModeRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: sdramExtModeRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG10, temp); -+ -+ /* calc D_UNIT_CONTROL_LOW and save it to temp register */ -+ TTMode = MV_FALSE; -+ DB(mvOsPrintf("Dram: numOfAllDevices = %x\n",numOfAllDevices);) -+ if( (numOfAllDevices > 9) && (bankInfo[0].registeredAddrAndControlInputs == MV_FALSE) ) -+ { -+ if ( ( (numOfAllDevices > 9) && (busClk > MV_BOARD_SYSCLK_200MHZ) ) || -+ (numOfAllDevices > 18) ) -+ { -+ mvOsOutput("Enable 2T "); -+ TTMode = MV_TRUE; -+ } -+ } -+ -+ temp = dunitCtrlLowRegCalc(&bankInfo[0], minCas, busClk, TTMode ); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. dunitCtrlLowRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: dunitCtrlLowRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG3, temp); -+ -+ /* calc D_UNIT_CONTROL_HIGH and save it to temp register */ -+ temp = dunitCtrlHighRegCalc(&bankInfo[0], busClk); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. dunitCtrlHighRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: dunitCtrlHighRegCalc - %x\n",temp);) -+ /* check if ECC is enabled by the user */ -+ if(eccDisable) -+ { -+ /* turn off sample stage if no ecc */ -+ temp &= ~SDRAM__D2P_EN;; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG13, temp); -+ -+ /* calc SDRAM_ADDR_CTRL_REG and save it to temp register */ -+ temp = sdramAddrCtrlRegCalc(&bankInfo[0],&bankInfo[2]); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. sdramAddrCtrlRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: sdramAddrCtrlRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG4, temp); -+ -+ /* calc SDRAM_TIMING_CTRL_LOW_REG and save it to temp register */ -+ temp = sdramTimeCtrlLowRegCalc(&bankInfo[0], minCas, busClk); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. sdramTimeCtrlLowRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: sdramTimeCtrlLowRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG5, temp); -+ -+ /* calc SDRAM_TIMING_CTRL_HIGH_REG and save it to temp register */ -+ temp = sdramTimeCtrlHighRegCalc(&bankInfo[0], busClk); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. sdramTimeCtrlHighRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: sdramTimeCtrlHighRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG6, temp); -+ -+ sdramDDr2OdtConfig(bankInfo); -+ -+ /* calc DDR2_SDRAM_TIMING_LOW_REG and save it to temp register */ -+ temp = sdramDdr2TimeLoRegCalc(minCas); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. sdramDdr2TimeLoRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: sdramDdr2TimeLoRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG11, temp); -+ -+ /* calc DDR2_SDRAM_TIMING_HIGH_REG and save it to temp register */ -+ temp = sdramDdr2TimeHiRegCalc(minCas); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. sdramDdr2TimeHiRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: sdramDdr2TimeHiRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG12, temp); -+#endif -+ -+ /* Note that DDR SDRAM Address/Control and Data pad calibration */ -+ /* settings is done in mvSdramIfConfig.s */ -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvDramIfBankBaseGet - Get DRAM interface bank base. -+* -+* DESCRIPTION: -+* This function returns the 32 bit base address of a given DRAM bank. -+* -+* INPUT: -+* bankNum - Bank number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* DRAM bank size. If bank is disabled or paramter is invalid, the -+* function returns -1. -+* -+*******************************************************************************/ -+MV_U32 mvDramIfBankBaseGet(MV_U32 bankNum) -+{ -+ DB(mvOsPrintf("Dram: mvDramIfBankBaseGet Bank %d base addr is %x \n", -+ bankNum, mvCpuIfTargetWinBaseLowGet(SDRAM_CS0 + bankNum))); -+ return mvCpuIfTargetWinBaseLowGet(SDRAM_CS0 + bankNum); -+} -+ -+/******************************************************************************* -+* mvDramIfBankSizeGet - Get DRAM interface bank size. -+* -+* DESCRIPTION: -+* This function returns the size of a given DRAM bank. -+* -+* INPUT: -+* bankNum - Bank number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* DRAM bank size. If bank is disabled the function return '0'. In case -+* or paramter is invalid, the function returns -1. -+* -+*******************************************************************************/ -+MV_U32 mvDramIfBankSizeGet(MV_U32 bankNum) -+{ -+ DB(mvOsPrintf("Dram: mvDramIfBankSizeGet Bank %d size is %x \n", -+ bankNum, mvCpuIfTargetWinSizeGet(SDRAM_CS0 + bankNum))); -+ return mvCpuIfTargetWinSizeGet(SDRAM_CS0 + bankNum); -+} -+ -+ -+/******************************************************************************* -+* mvDramIfSizeGet - Get DRAM interface total size. -+* -+* DESCRIPTION: -+* This function get the DRAM total size. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* DRAM total size. In case or paramter is invalid, the function -+* returns -1. -+* -+*******************************************************************************/ -+MV_U32 mvDramIfSizeGet(MV_VOID) -+{ -+ MV_U32 size = 0, i; -+ -+ for(i = 0; i < MV_DRAM_MAX_CS; i++) -+ size += mvDramIfBankSizeGet(i); -+ -+ DB(mvOsPrintf("Dram: mvDramIfSizeGet size is %x \n",size)); -+ return size; -+} -+ -+/******************************************************************************* -+* mvDramIfSingleBitErrThresholdSet - Set single bit ECC threshold. -+* -+* DESCRIPTION: -+* The ECC single bit error threshold is the number of single bit -+* errors to happen before the Dunit generates an interrupt. -+* This function set single bit ECC threshold. -+* -+* INPUT: -+* threshold - threshold. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM if threshold is to big, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_STATUS mvDramIfSingleBitErrThresholdSet(MV_U32 threshold) -+{ -+ MV_U32 regVal; -+ -+ if (threshold > SECR_THRECC_MAX) -+ { -+ return MV_BAD_PARAM; -+ } -+ -+ regVal = MV_REG_READ(SDRAM_ECC_CONTROL_REG); -+ regVal &= ~SECR_THRECC_MASK; -+ regVal |= ((SECR_THRECC(threshold) & SECR_THRECC_MASK)); -+ MV_REG_WRITE(SDRAM_ECC_CONTROL_REG, regVal); -+ -+ return MV_OK; -+} -+ -+#ifndef MV_STATIC_DRAM_ON_BOARD -+/******************************************************************************* -+* minCasCalc - Calculate the Minimum CAS latency which can be used. -+* -+* DESCRIPTION: -+* Calculate the minimum CAS latency that can be used, base on the DRAM -+* parameters and the SDRAM bus Clock freq. -+* -+* INPUT: -+* busClk - the DRAM bus Clock. -+* pBankInfo - bank info parameters. -+* forcedCl - Forced CAS Latency multiplied by 10. If equal to zero, do not force. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* The minimum CAS Latency. The function returns 0 if max CAS latency -+* supported by banks is incompatible with system bus clock frequancy. -+* -+*******************************************************************************/ -+ -+static MV_U32 minCasCalc(MV_DRAM_BANK_INFO *pBankInfo,MV_DRAM_BANK_INFO *pBankInfo2, MV_U32 busClk, MV_U32 forcedCl) -+{ -+ MV_U32 count = 1, j; -+ MV_U32 busClkPs = 1000000000 / (busClk / 1000); /* in ps units */ -+ MV_U32 startBit, stopBit; -+ MV_U32 minCas0 = 0, minCas2 = 0; -+ -+ -+ /* DDR 2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * -+ Disco VI= * TBD | TBD | 5 | 4 | 3 | TBD | TBD | TBD * -+ Disco Duo= * TBD | 6 | 5 | 4 | 3 | TBD | TBD | TBD * -+ *********************************************************/ -+ -+ -+ /* If we are asked to use the forced CAL we change the suported CAL to be forcedCl only */ -+ if (forcedCl) -+ { -+ mvOsOutput("DRAM: Using forced CL %d.%d\n", (forcedCl / 10), (forcedCl % 10)); -+ -+ if (forcedCl == 30) -+ pBankInfo->suportedCasLatencies = 0x08; -+ else if (forcedCl == 40) -+ pBankInfo->suportedCasLatencies = 0x10; -+ else if (forcedCl == 50) -+ pBankInfo->suportedCasLatencies = 0x20; -+ else if (forcedCl == 60) -+ pBankInfo->suportedCasLatencies = 0x40; -+ else -+ { -+ mvOsPrintf("Forced CL %d.%d not supported. Set default CL 4\n", -+ (forcedCl / 10), (forcedCl % 10)); -+ pBankInfo->suportedCasLatencies = 0x10; -+ } -+ -+ return pBankInfo->suportedCasLatencies; -+ } -+ -+ /* go over the supported cas mask from Max Cas down and check if the */ -+ /* SysClk stands in its time requirments. */ -+ -+ DB(mvOsPrintf("Dram: minCasCalc supported mask = %x busClkPs = %x \n", -+ pBankInfo->suportedCasLatencies,busClkPs )); -+ count = 1; -+ for(j = 7; j > 0; j--) -+ { -+ if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) -+ { -+ /* Reset the bits for CL incompatible for the sysClk */ -+ switch (count) -+ { -+ case 1: -+ if (pBankInfo->minCycleTimeAtMaxCasLatPs > busClkPs) -+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ case 2: -+ if (pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps > busClkPs) -+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ case 3: -+ if (pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps > busClkPs) -+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ default: -+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); -+ break; -+ } -+ } -+ } -+ -+ DB(mvOsPrintf("Dram: minCasCalc support = %x (after SysCC calc)\n", -+ pBankInfo->suportedCasLatencies )); -+ -+ count = 1; -+ DB(mvOsPrintf("Dram2: minCasCalc supported mask = %x busClkPs = %x \n", -+ pBankInfo2->suportedCasLatencies,busClkPs )); -+ for(j = 7; j > 0; j--) -+ { -+ if((pBankInfo2->suportedCasLatencies >> j) & BIT0 ) -+ { -+ /* Reset the bits for CL incompatible for the sysClk */ -+ switch (count) -+ { -+ case 1: -+ if (pBankInfo2->minCycleTimeAtMaxCasLatPs > busClkPs) -+ pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ case 2: -+ if (pBankInfo2->minCycleTimeAtMaxCasLatMinus1Ps > busClkPs) -+ pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ case 3: -+ if (pBankInfo2->minCycleTimeAtMaxCasLatMinus2Ps > busClkPs) -+ pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ default: -+ pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); -+ break; -+ } -+ } -+ } -+ -+ DB(mvOsPrintf("Dram2: minCasCalc support = %x (after SysCC calc)\n", -+ pBankInfo2->suportedCasLatencies )); -+ -+ startBit = 3; /* DDR2 support CL start with CL3 (bit 3) */ -+ stopBit = 6; /* DDR2 support CL stops with CL6 (bit 6) */ -+ -+ for(j = startBit; j <= stopBit ; j++) -+ { -+ if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) -+ { -+ DB(mvOsPrintf("Dram: minCasCalc choose CAS %x \n",(BIT0 << j))); -+ minCas0 = (BIT0 << j); -+ break; -+ } -+ } -+ -+ for(j = startBit; j <= stopBit ; j++) -+ { -+ if((pBankInfo2->suportedCasLatencies >> j) & BIT0 ) -+ { -+ DB(mvOsPrintf("Dram: minCasCalc choose CAS %x \n",(BIT0 << j))); -+ minCas2 = (BIT0 << j); -+ break; -+ } -+ } -+ -+ if (minCas2 > minCas0) -+ return minCas2; -+ else -+ return minCas0; -+ -+ return 0; -+} -+ -+/******************************************************************************* -+* sdramConfigRegCalc - Calculate sdram config register -+* -+* DESCRIPTION: Calculate sdram config register optimized value based -+* on the bank info parameters. -+* -+* INPUT: -+* busClk - the DRAM bus Clock. -+* pBankInfo - sdram bank parameters -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram config reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramConfigRegCalc(MV_DRAM_BANK_INFO *pBankInfo,MV_DRAM_BANK_INFO *pBankInfo2, MV_U32 busClk) -+{ -+ MV_U32 sdramConfig = 0; -+ MV_U32 refreshPeriod; -+ -+ busClk /= 1000000; /* we work with busClk in MHz */ -+ -+ sdramConfig = MV_REG_READ(SDRAM_CONFIG_REG); -+ -+ /* figure out the memory refresh internal */ -+ switch (pBankInfo->refreshInterval & 0xf) -+ { -+ case 0x0: /* refresh period is 15.625 usec */ -+ refreshPeriod = 15625; -+ break; -+ case 0x1: /* refresh period is 3.9 usec */ -+ refreshPeriod = 3900; -+ break; -+ case 0x2: /* refresh period is 7.8 usec */ -+ refreshPeriod = 7800; -+ break; -+ case 0x3: /* refresh period is 31.3 usec */ -+ refreshPeriod = 31300; -+ break; -+ case 0x4: /* refresh period is 62.5 usec */ -+ refreshPeriod = 62500; -+ break; -+ case 0x5: /* refresh period is 125 usec */ -+ refreshPeriod = 125000; -+ break; -+ default: /* refresh period undefined */ -+ mvOsPrintf("Dram: ERR. DRAM refresh period is unknown!\n"); -+ return -1; -+ } -+ -+ /* Now the refreshPeriod is in register format value */ -+ refreshPeriod = (busClk * refreshPeriod) / 1000; -+ -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc calculated refresh interval %0x\n", -+ refreshPeriod)); -+ -+ /* make sure the refresh value is only 14 bits */ -+ if(refreshPeriod > SDRAM_REFRESH_MAX) -+ { -+ refreshPeriod = SDRAM_REFRESH_MAX; -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc adjusted refresh interval %0x\n", -+ refreshPeriod)); -+ } -+ -+ /* Clear the refresh field */ -+ sdramConfig &= ~SDRAM_REFRESH_MASK; -+ -+ /* Set new value to refresh field */ -+ sdramConfig |= (refreshPeriod & SDRAM_REFRESH_MASK); -+ -+ /* registered DRAM ? */ -+ if ( pBankInfo->registeredAddrAndControlInputs ) -+ { -+ /* it's registered DRAM, so set the reg. DRAM bit */ -+ sdramConfig |= SDRAM_REGISTERED; -+ DB(mvOsPrintf("DRAM Attribute: Registered address and control inputs.\n");) -+ } -+ -+ /* ECC and IERR support */ -+ sdramConfig &= ~SDRAM_ECC_MASK; /* Clear ECC field */ -+ sdramConfig &= ~SDRAM_IERR_MASK; /* Clear IErr field */ -+ -+ if ( pBankInfo->errorCheckType ) -+ { -+ sdramConfig |= SDRAM_ECC_EN; -+ sdramConfig |= SDRAM_IERR_REPORTE; -+ DB(mvOsPrintf("Dram: mvDramIfDetect Enabling ECC\n")); -+ } -+ else -+ { -+ sdramConfig |= SDRAM_ECC_DIS; -+ sdramConfig |= SDRAM_IERR_IGNORE; -+ DB(mvOsPrintf("Dram: mvDramIfDetect Disabling ECC!\n")); -+ } -+ /* Set static default settings */ -+ sdramConfig |= SDRAM_CONFIG_DV; -+ -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc set sdramConfig to 0x%x\n", -+ sdramConfig)); -+ -+ return sdramConfig; -+} -+ -+/******************************************************************************* -+* sdramModeRegCalc - Calculate sdram mode register -+* -+* DESCRIPTION: Calculate sdram mode register optimized value based -+* on the bank info parameters and the minCas. -+* -+* INPUT: -+* minCas - minimum CAS supported. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram mode reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramModeRegCalc(MV_U32 minCas) -+{ -+ MV_U32 sdramMode; -+ -+ sdramMode = MV_REG_READ(SDRAM_MODE_REG); -+ -+ /* Clear CAS Latency field */ -+ sdramMode &= ~SDRAM_CL_MASK; -+ -+ DB(mvOsPrintf("DRAM CAS Latency ");) -+ -+ switch (minCas) -+ { -+ case DDR2_CL_3: -+ sdramMode |= SDRAM_DDR2_CL_3; -+ DB(mvOsPrintf("3.\n");) -+ break; -+ case DDR2_CL_4: -+ sdramMode |= SDRAM_DDR2_CL_4; -+ DB(mvOsPrintf("4.\n");) -+ break; -+ case DDR2_CL_5: -+ sdramMode |= SDRAM_DDR2_CL_5; -+ DB(mvOsPrintf("5.\n");) -+ break; -+ case DDR2_CL_6: -+ sdramMode |= SDRAM_DDR2_CL_6; -+ DB(mvOsPrintf("6.\n");) -+ break; -+ default: -+ mvOsOutput("\nsdramModeRegCalc ERROR: Max. CL out of range\n"); -+ return -1; -+ } -+ -+ DB(mvOsPrintf("\nsdramModeRegCalc register 0x%x\n", sdramMode )); -+ -+ return sdramMode; -+} -+/******************************************************************************* -+* sdramExtModeRegCalc - Calculate sdram Extended mode register -+* -+* DESCRIPTION: -+* Return sdram Extended mode register value based -+* on the bank info parameters and bank presence. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* busClk - DRAM frequency -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram Extended mode reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramExtModeRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) -+{ -+ MV_U32 populateBanks = 0; -+ int bankNum; -+ -+ /* Represent the populate banks in binary form */ -+ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ if (0 != pBankInfo[bankNum].size) -+ { -+ populateBanks |= (1 << bankNum); -+ } -+ } -+ -+ switch(populateBanks) -+ { -+ case(BANK_PRESENT_CS0): -+ case(BANK_PRESENT_CS0_CS1): -+ return DDR_SDRAM_EXT_MODE_CS0_CS1_DV; -+ -+ case(BANK_PRESENT_CS0_CS2): -+ case(BANK_PRESENT_CS0_CS1_CS2): -+ case(BANK_PRESENT_CS0_CS2_CS3): -+ case(BANK_PRESENT_CS0_CS2_CS3_CS4): -+ if (busClk >= MV_BOARD_SYSCLK_267MHZ) -+ return DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV; -+ else -+ return DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV; -+ -+ default: -+ mvOsOutput("sdramExtModeRegCalc: Invalid DRAM bank presence\n"); -+ return -1; -+ } -+ return 0; -+} -+ -+/******************************************************************************* -+* dunitCtrlLowRegCalc - Calculate sdram dunit control low register -+* -+* DESCRIPTION: Calculate sdram dunit control low register optimized value based -+* on the bank info parameters and the minCas. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* minCas - minimum CAS supported. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram dunit control low reg value. -+* -+*******************************************************************************/ -+static MV_U32 dunitCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas, MV_U32 busClk, MV_STATUS TTMode) -+{ -+ MV_U32 dunitCtrlLow, cl; -+ MV_U32 sbOutR[4]={3,5,7,9} ; -+ MV_U32 sbOutU[4]={1,3,5,7} ; -+ -+ dunitCtrlLow = MV_REG_READ(SDRAM_DUNIT_CTRL_REG); -+ -+ DB(mvOsPrintf("Dram: dunitCtrlLowRegCalc\n")); -+ -+ /* Clear StBurstOutDel field */ -+ dunitCtrlLow &= ~SDRAM_SB_OUT_MASK; -+ -+ /* Clear StBurstInDel field */ -+ dunitCtrlLow &= ~SDRAM_SB_IN_MASK; -+ -+ /* Clear CtrlPos field */ -+ dunitCtrlLow &= ~SDRAM_CTRL_POS_MASK; -+ -+ /* Clear 2T field */ -+ dunitCtrlLow &= ~SDRAM_2T_MASK; -+ if (TTMode == MV_TRUE) -+ { -+ dunitCtrlLow |= SDRAM_2T_MODE; -+ } -+ -+ /* For proper sample of read data set the Dunit Control register's */ -+ /* stBurstInDel bits [27:24] */ -+ /* 200MHz - 267MHz None reg = CL + 1 */ -+ /* 200MHz - 267MHz reg = CL + 2 */ -+ /* > 267MHz None reg = CL + 2 */ -+ /* > 267MHz reg = CL + 3 */ -+ -+ /* For proper sample of read data set the Dunit Control register's */ -+ /* stBurstOutDel bits [23:20] */ -+ /********-********-********-********- -+ * CL=3 | CL=4 | CL=5 | CL=6 | -+ *********-********-********-********- -+ Not Reg. * 0001 | 0011 | 0101 | 0111 | -+ *********-********-********-********- -+ Registered * 0011 | 0101 | 0111 | 1001 | -+ *********-********-********-********/ -+ -+ /* Set Dunit Control low default value */ -+ dunitCtrlLow |= SDRAM_DUNIT_CTRL_LOW_DDR2_DV; -+ -+ switch (minCas) -+ { -+ case DDR2_CL_3: cl = 3; break; -+ case DDR2_CL_4: cl = 4; break; -+ case DDR2_CL_5: cl = 5; break; -+ case DDR2_CL_6: cl = 6; break; -+ default: -+ mvOsOutput("Dram: dunitCtrlLowRegCalc Max. CL out of range %d\n", minCas); -+ return -1; -+ } -+ -+ /* registerd DDR SDRAM? */ -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ { -+ dunitCtrlLow |= (sbOutR[cl-3]) << SDRAM_SB_OUT_DEL_OFFS; -+ } -+ else -+ { -+ dunitCtrlLow |= (sbOutU[cl-3]) << SDRAM_SB_OUT_DEL_OFFS; -+ } -+ -+ DB(mvOsPrintf("\n\ndunitCtrlLowRegCalc: CL = %d, frequencies=%d\n", cl, busClk)); -+ -+ if (busClk <= MV_BOARD_SYSCLK_267MHZ) -+ { -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ cl = cl + 2; -+ else -+ cl = cl + 1; -+ } -+ else -+ { -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ cl = cl + 3; -+ else -+ cl = cl + 2; -+ } -+ -+ DB(mvOsPrintf("dunitCtrlLowRegCalc: SDRAM_SB_IN_DEL_OFFS = %d \n", cl)); -+ dunitCtrlLow |= cl << SDRAM_SB_IN_DEL_OFFS; -+ -+ DB(mvOsPrintf("Dram: Reg dunit control low = %x\n", dunitCtrlLow )); -+ -+ return dunitCtrlLow; -+} -+ -+/******************************************************************************* -+* dunitCtrlHighRegCalc - Calculate sdram dunit control high register -+* -+* DESCRIPTION: Calculate sdram dunit control high register optimized value based -+* on the bus clock. -+* -+* INPUT: -+* busClk - DRAM frequency. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram dunit control high reg value. -+* -+*******************************************************************************/ -+static MV_U32 dunitCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) -+{ -+ MV_U32 dunitCtrlHigh; -+ dunitCtrlHigh = MV_REG_READ(SDRAM_DUNIT_CTRL_HI_REG); -+ if(busClk > MV_BOARD_SYSCLK_300MHZ) -+ dunitCtrlHigh |= SDRAM__P2D_EN; -+ else -+ dunitCtrlHigh &= ~SDRAM__P2D_EN; -+ -+ if(busClk > MV_BOARD_SYSCLK_267MHZ) -+ dunitCtrlHigh |= (SDRAM__WR_MESH_DELAY_EN | SDRAM__PUP_ZERO_SKEW_EN | SDRAM__ADD_HALF_FCC_EN); -+ -+ /* If ECC support we turn on D2P sample */ -+ dunitCtrlHigh &= ~SDRAM__D2P_EN; /* Clear D2P bit */ -+ if (( pBankInfo->errorCheckType ) && (busClk > MV_BOARD_SYSCLK_267MHZ)) -+ dunitCtrlHigh |= SDRAM__D2P_EN; -+ -+ return dunitCtrlHigh; -+} -+ -+/******************************************************************************* -+* sdramAddrCtrlRegCalc - Calculate sdram address control register -+* -+* DESCRIPTION: Calculate sdram address control register optimized value based -+* on the bank info parameters and the minCas. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram address control reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramAddrCtrlRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_DRAM_BANK_INFO *pBankInfoDIMM1) -+{ -+ MV_U32 addrCtrl = 0; -+ -+ if (pBankInfoDIMM1->size) -+ { -+ switch (pBankInfoDIMM1->sdramWidth) -+ { -+ case 4: /* memory is x4 */ -+ mvOsOutput("sdramAddrCtrlRegCalc: Error - x4 not supported!\n"); -+ return -1; -+ break; -+ case 8: /* memory is x8 */ -+ addrCtrl |= SDRAM_ADDRSEL_X8(2) | SDRAM_ADDRSEL_X8(3); -+ DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device DIMM2 width x8\n")); -+ break; -+ case 16: -+ addrCtrl |= SDRAM_ADDRSEL_X16(2) | SDRAM_ADDRSEL_X16(3); -+ DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device DIMM2 width x16\n")); -+ break; -+ default: /* memory width unsupported */ -+ mvOsOutput("sdramAddrCtrlRegCalc: ERR. DRAM chip width is unknown!\n"); -+ return -1; -+ } -+ } -+ -+ switch (pBankInfo->sdramWidth) -+ { -+ case 4: /* memory is x4 */ -+ mvOsOutput("sdramAddrCtrlRegCalc: Error - x4 not supported!\n"); -+ return -1; -+ break; -+ case 8: /* memory is x8 */ -+ addrCtrl |= SDRAM_ADDRSEL_X8(0) | SDRAM_ADDRSEL_X8(1); -+ DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device width x8\n")); -+ break; -+ case 16: -+ addrCtrl |= SDRAM_ADDRSEL_X16(0) | SDRAM_ADDRSEL_X16(1); -+ DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device width x16\n")); -+ break; -+ default: /* memory width unsupported */ -+ mvOsOutput("sdramAddrCtrlRegCalc: ERR. DRAM chip width is unknown!\n"); -+ return -1; -+ } -+ -+ /* Note that density is in MB units */ -+ switch (pBankInfo->deviceDensity) -+ { -+ case 256: /* 256 Mbit */ -+ DB(mvOsPrintf("DRAM Device Density 256Mbit\n")); -+ addrCtrl |= SDRAM_DSIZE_256Mb(0) | SDRAM_DSIZE_256Mb(1); -+ break; -+ case 512: /* 512 Mbit */ -+ DB(mvOsPrintf("DRAM Device Density 512Mbit\n")); -+ addrCtrl |= SDRAM_DSIZE_512Mb(0) | SDRAM_DSIZE_512Mb(1); -+ break; -+ case 1024: /* 1 Gbit */ -+ DB(mvOsPrintf("DRAM Device Density 1Gbit\n")); -+ addrCtrl |= SDRAM_DSIZE_1Gb(0) | SDRAM_DSIZE_1Gb(1); -+ break; -+ case 2048: /* 2 Gbit */ -+ DB(mvOsPrintf("DRAM Device Density 2Gbit\n")); -+ addrCtrl |= SDRAM_DSIZE_2Gb(0) | SDRAM_DSIZE_2Gb(1); -+ break; -+ default: -+ mvOsOutput("Dram: sdramAddrCtrl unsupported RAM-Device size %d\n", -+ pBankInfo->deviceDensity); -+ return -1; -+ } -+ -+ if (pBankInfoDIMM1->size) -+ { -+ switch (pBankInfoDIMM1->deviceDensity) -+ { -+ case 256: /* 256 Mbit */ -+ DB(mvOsPrintf("DIMM2: DRAM Device Density 256Mbit\n")); -+ addrCtrl |= SDRAM_DSIZE_256Mb(2) | SDRAM_DSIZE_256Mb(3); -+ break; -+ case 512: /* 512 Mbit */ -+ DB(mvOsPrintf("DIMM2: DRAM Device Density 512Mbit\n")); -+ addrCtrl |= SDRAM_DSIZE_512Mb(2) | SDRAM_DSIZE_512Mb(3); -+ break; -+ case 1024: /* 1 Gbit */ -+ DB(mvOsPrintf("DIMM2: DRAM Device Density 1Gbit\n")); -+ addrCtrl |= SDRAM_DSIZE_1Gb(2) | SDRAM_DSIZE_1Gb(3); -+ break; -+ case 2048: /* 2 Gbit */ -+ DB(mvOsPrintf("DIMM2: DRAM Device Density 2Gbit\n")); -+ addrCtrl |= SDRAM_DSIZE_2Gb(2) | SDRAM_DSIZE_2Gb(3); -+ break; -+ default: -+ mvOsOutput("DIMM2: Dram: sdramAddrCtrl unsupported RAM-Device size %d\n", -+ pBankInfoDIMM1->deviceDensity); -+ return -1; -+ } -+ } -+ /* SDRAM address control */ -+ DB(mvOsPrintf("Dram: setting sdram address control with: %x \n", addrCtrl)); -+ -+ return addrCtrl; -+} -+ -+/******************************************************************************* -+* sdramTimeCtrlLowRegCalc - Calculate sdram timing control low register -+* -+* DESCRIPTION: -+* This function calculates sdram timing control low register -+* optimized value based on the bank info parameters and the minCas. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* minCas - minimum CAS supported. -+* busClk - Bus clock -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram timing control low reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramTimeCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas, MV_U32 busClk) -+{ -+ MV_U32 tRp = 0; -+ MV_U32 tRrd = 0; -+ MV_U32 tRcd = 0; -+ MV_U32 tRas = 0; -+ MV_U32 tWr = 0; -+ MV_U32 tWtr = 0; -+ MV_U32 tRtp = 0; -+ MV_U32 timeCtrlLow = 0; -+ -+ MV_U32 bankNum; -+ -+ busClk = busClk / 1000000; /* In MHz */ -+ -+ /* Scan all DRAM banks to find maximum timing values */ -+ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ tRp = MV_MAX(tRp, pBankInfo[bankNum].minRowPrechargeTime); -+ tRrd = MV_MAX(tRrd, pBankInfo[bankNum].minRowActiveToRowActive); -+ tRcd = MV_MAX(tRcd, pBankInfo[bankNum].minRasToCasDelay); -+ tRas = MV_MAX(tRas, pBankInfo[bankNum].minRasPulseWidth); -+ } -+ -+ /* Extract timing (in ns) from SPD value. We ignore the tenth ns part. */ -+ /* by shifting the data two bits right. */ -+ tRp = tRp >> 2; /* For example 0x50 -> 20ns */ -+ tRrd = tRrd >> 2; -+ tRcd = tRcd >> 2; -+ -+ /* Extract clock cycles from time parameter. We need to round up */ -+ tRp = ((busClk * tRp) / 1000) + (((busClk * tRp) % 1000) ? 1 : 0); -+ DB(mvOsPrintf("Dram Timing Low: tRp = %d ", tRp)); -+ tRrd = ((busClk * tRrd) / 1000) + (((busClk * tRrd) % 1000) ? 1 : 0); -+ /* JEDEC min reqeirments tRrd = 2 */ -+ if (tRrd < 2) -+ tRrd = 2; -+ DB(mvOsPrintf("tRrd = %d ", tRrd)); -+ tRcd = ((busClk * tRcd) / 1000) + (((busClk * tRcd) % 1000) ? 1 : 0); -+ DB(mvOsPrintf("tRcd = %d ", tRcd)); -+ tRas = ((busClk * tRas) / 1000) + (((busClk * tRas) % 1000) ? 1 : 0); -+ DB(mvOsPrintf("tRas = %d ", tRas)); -+ -+ /* tWr and tWtr is different for DDR1 and DDR2. tRtp is only for DDR2 */ -+ /* Scan all DRAM banks to find maximum timing values */ -+ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ tWr = MV_MAX(tWr, pBankInfo[bankNum].minWriteRecoveryTime); -+ tWtr = MV_MAX(tWtr, pBankInfo[bankNum].minWriteToReadCmdDelay); -+ tRtp = MV_MAX(tRtp, pBankInfo[bankNum].minReadToPrechCmdDelay); -+ } -+ -+ /* Extract timing (in ns) from SPD value. We ignore the tenth ns */ -+ /* part by shifting the data two bits right. */ -+ tWr = tWr >> 2; /* For example 0x50 -> 20ns */ -+ tWtr = tWtr >> 2; -+ tRtp = tRtp >> 2; -+ /* Extract clock cycles from time parameter. We need to round up */ -+ tWr = ((busClk * tWr) / 1000) + (((busClk * tWr) % 1000) ? 1 : 0); -+ DB(mvOsPrintf("tWr = %d ", tWr)); -+ tWtr = ((busClk * tWtr) / 1000) + (((busClk * tWtr) % 1000) ? 1 : 0); -+ /* JEDEC min reqeirments tWtr = 2 */ -+ if (tWtr < 2) -+ tWtr = 2; -+ DB(mvOsPrintf("tWtr = %d ", tWtr)); -+ tRtp = ((busClk * tRtp) / 1000) + (((busClk * tRtp) % 1000) ? 1 : 0); -+ /* JEDEC min reqeirments tRtp = 2 */ -+ if (tRtp < 2) -+ tRtp = 2; -+ DB(mvOsPrintf("tRtp = %d ", tRtp)); -+ -+ /* Note: value of 0 in register means one cycle, 1 means two and so on */ -+ timeCtrlLow = (((tRp - 1) << SDRAM_TRP_OFFS) | -+ ((tRrd - 1) << SDRAM_TRRD_OFFS) | -+ ((tRcd - 1) << SDRAM_TRCD_OFFS) | -+ (((tRas - 1) << SDRAM_TRAS_OFFS) & SDRAM_TRAS_MASK)| -+ ((tWr - 1) << SDRAM_TWR_OFFS) | -+ ((tWtr - 1) << SDRAM_TWTR_OFFS) | -+ ((tRtp - 1) << SDRAM_TRTP_OFFS)); -+ -+ /* Check extended tRas bit */ -+ if ((tRas - 1) & BIT4) -+ timeCtrlLow |= (1 << SDRAM_EXT_TRAS_OFFS); -+ -+ return timeCtrlLow; -+} -+ -+/******************************************************************************* -+* sdramTimeCtrlHighRegCalc - Calculate sdram timing control high register -+* -+* DESCRIPTION: -+* This function calculates sdram timing control high register -+* optimized value based on the bank info parameters and the bus clock. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* busClk - Bus clock -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram timing control high reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramTimeCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) -+{ -+ MV_U32 tRfc; -+ MV_U32 timingHigh; -+ MV_U32 timeNs = 0; -+ MV_U32 bankNum; -+ -+ busClk = busClk / 1000000; /* In MHz */ -+ -+ /* Set DDR timing high register static configuration bits */ -+ timingHigh = MV_REG_READ(SDRAM_TIMING_CTRL_HIGH_REG); -+ -+ /* Set DDR timing high register default value */ -+ timingHigh |= SDRAM_TIMING_CTRL_HIGH_REG_DV; -+ -+ /* Clear tRfc field */ -+ timingHigh &= ~SDRAM_TRFC_MASK; -+ -+ /* Scan all DRAM banks to find maximum timing values */ -+ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ timeNs = MV_MAX(timeNs, pBankInfo[bankNum].minRefreshToActiveCmd); -+ DB(mvOsPrintf("Dram: Timing High: minRefreshToActiveCmd = %d\n", -+ pBankInfo[bankNum].minRefreshToActiveCmd)); -+ } -+ if(busClk >= 333 && mvCtrlModelGet() == MV_78XX0_A1_REV) -+ { -+ timingHigh |= 0x1 << SDRAM_TR2W_W2R_OFFS; -+ } -+ -+ tRfc = ((busClk * timeNs) / 1000) + (((busClk * timeNs) % 1000) ? 1 : 0); -+ /* Note: value of 0 in register means one cycle, 1 means two and so on */ -+ DB(mvOsPrintf("Dram: Timing High: tRfc = %d\n", tRfc)); -+ timingHigh |= (((tRfc - 1) & SDRAM_TRFC_MASK) << SDRAM_TRFC_OFFS); -+ DB(mvOsPrintf("Dram: Timing High: tRfc = %d\n", tRfc)); -+ -+ /* SDRAM timing high */ -+ DB(mvOsPrintf("Dram: setting timing high with: %x \n", timingHigh)); -+ -+ return timingHigh; -+} -+/******************************************************************************* -+* sdramDDr2OdtConfig - Set DRAM DDR2 On Die Termination registers. -+* -+* DESCRIPTION: -+* This function config DDR2 On Die Termination (ODT) registers. -+* -+* INPUT: -+* pBankInfo - bank info parameters. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* None -+*******************************************************************************/ -+static void sdramDDr2OdtConfig(MV_DRAM_BANK_INFO *pBankInfo) -+{ -+ MV_U32 populateBanks = 0; -+ MV_U32 odtCtrlLow, odtCtrlHigh, dunitOdtCtrl; -+ int bankNum; -+ -+ /* Represent the populate banks in binary form */ -+ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ if (0 != pBankInfo[bankNum].size) -+ { -+ populateBanks |= (1 << bankNum); -+ } -+ } -+ -+ switch(populateBanks) -+ { -+ case(BANK_PRESENT_CS0): -+ case(BANK_PRESENT_CS0_CS1): -+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS1_DV; -+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS1_DV; -+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV; -+ break; -+ case(BANK_PRESENT_CS0_CS2): -+ case(BANK_PRESENT_CS0_CS1_CS2): -+ case(BANK_PRESENT_CS0_CS2_CS3): -+ case(BANK_PRESENT_CS0_CS2_CS3_CS4): -+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV; -+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS1_CS2_CS3_DV; -+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV; -+ break; -+ default: -+ DB(mvOsPrintf("sdramDDr2OdtConfig: Invalid DRAM bank presence\n")); -+ return; -+ } -+ /* DDR2 SDRAM ODT ctrl low */ -+ DB(mvOsPrintf("Dram: DDR2 setting ODT ctrl low with: %x \n", odtCtrlLow)); -+ MV_REG_WRITE(DRAM_BUF_REG7, odtCtrlLow); -+ -+ /* DDR2 SDRAM ODT ctrl high */ -+ DB(mvOsPrintf("Dram: DDR2 setting ODT ctrl high with: %x \n", odtCtrlHigh)); -+ MV_REG_WRITE(DRAM_BUF_REG8, odtCtrlHigh); -+ -+ /* DDR2 DUNIT ODT ctrl */ -+ if ( ((mvCtrlModelGet() == MV_78XX0_DEV_ID) && (mvCtrlRevGet() == MV_78XX0_Y0_REV)) || -+ (mvCtrlModelGet() == MV_76100_DEV_ID) || -+ (mvCtrlModelGet() == MV_78100_DEV_ID) || -+ (mvCtrlModelGet() == MV_78200_DEV_ID) ) -+ dunitOdtCtrl &= ~(BIT9|BIT8); /* Clear ODT always on */ -+ -+ DB(mvOsPrintf("DUNIT: DDR2 setting ODT ctrl with: %x \n", dunitOdtCtrl)); -+ MV_REG_WRITE(DRAM_BUF_REG9, dunitOdtCtrl); -+ return; -+} -+/******************************************************************************* -+* sdramDdr2TimeLoRegCalc - Set DDR2 DRAM Timing Low registers. -+* -+* DESCRIPTION: -+* This function config DDR2 DRAM Timing low registers. -+* -+* INPUT: -+* minCas - minimum CAS supported. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* DDR2 sdram timing low reg value. -+*******************************************************************************/ -+static MV_U32 sdramDdr2TimeLoRegCalc(MV_U32 minCas) -+{ -+ MV_U8 cl = -1; -+ MV_U32 ddr2TimeLoReg; -+ -+ /* read and clear the feilds we are going to set */ -+ ddr2TimeLoReg = MV_REG_READ(SDRAM_DDR2_TIMING_LO_REG); -+ ddr2TimeLoReg &= ~(SD2TLR_TODT_ON_RD_MASK | -+ SD2TLR_TODT_OFF_RD_MASK | -+ SD2TLR_TODT_ON_CTRL_RD_MASK | -+ SD2TLR_TODT_OFF_CTRL_RD_MASK); -+ -+ if( minCas == DDR2_CL_3 ) -+ { -+ cl = 3; -+ } -+ else if( minCas == DDR2_CL_4 ) -+ { -+ cl = 4; -+ } -+ else if( minCas == DDR2_CL_5 ) -+ { -+ cl = 5; -+ } -+ else if( minCas == DDR2_CL_6 ) -+ { -+ cl = 6; -+ } -+ else -+ { -+ DB(mvOsPrintf("sdramDdr2TimeLoRegCalc: CAS latency %d unsupported. using CAS latency 4\n", -+ minCas)); -+ cl = 4; -+ } -+ -+ ddr2TimeLoReg |= ((cl-3) << SD2TLR_TODT_ON_RD_OFFS); -+ ddr2TimeLoReg |= ( cl << SD2TLR_TODT_OFF_RD_OFFS); -+ ddr2TimeLoReg |= ( cl << SD2TLR_TODT_ON_CTRL_RD_OFFS); -+ ddr2TimeLoReg |= ((cl+3) << SD2TLR_TODT_OFF_CTRL_RD_OFFS); -+ -+ /* DDR2 SDRAM timing low */ -+ DB(mvOsPrintf("Dram: DDR2 setting timing low with: %x \n", ddr2TimeLoReg)); -+ -+ return ddr2TimeLoReg; -+} -+ -+/******************************************************************************* -+* sdramDdr2TimeHiRegCalc - Set DDR2 DRAM Timing High registers. -+* -+* DESCRIPTION: -+* This function config DDR2 DRAM Timing high registers. -+* -+* INPUT: -+* minCas - minimum CAS supported. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* DDR2 sdram timing high reg value. -+*******************************************************************************/ -+static MV_U32 sdramDdr2TimeHiRegCalc(MV_U32 minCas) -+{ -+ MV_U8 cl = -1; -+ MV_U32 ddr2TimeHiReg; -+ -+ /* read and clear the feilds we are going to set */ -+ ddr2TimeHiReg = MV_REG_READ(SDRAM_DDR2_TIMING_HI_REG); -+ ddr2TimeHiReg &= ~(SD2THR_TODT_ON_WR_MASK | -+ SD2THR_TODT_OFF_WR_MASK | -+ SD2THR_TODT_ON_CTRL_WR_MASK | -+ SD2THR_TODT_OFF_CTRL_WR_MASK); -+ -+ if( minCas == DDR2_CL_3 ) -+ { -+ cl = 3; -+ } -+ else if( minCas == DDR2_CL_4 ) -+ { -+ cl = 4; -+ } -+ else if( minCas == DDR2_CL_5 ) -+ { -+ cl = 5; -+ } -+ else if( minCas == DDR2_CL_6 ) -+ { -+ cl = 6; -+ } -+ else -+ { -+ mvOsOutput("sdramDdr2TimeHiRegCalc: CAS latency %d unsupported. using CAS latency 4\n", -+ minCas); -+ cl = 4; -+ } -+ -+ ddr2TimeHiReg |= ((cl-3) << SD2THR_TODT_ON_WR_OFFS); -+ ddr2TimeHiReg |= ( cl << SD2THR_TODT_OFF_WR_OFFS); -+ ddr2TimeHiReg |= ( cl << SD2THR_TODT_ON_CTRL_WR_OFFS); -+ ddr2TimeHiReg |= ((cl+3) << SD2THR_TODT_OFF_CTRL_WR_OFFS); -+ -+ /* DDR2 SDRAM timin high */ -+ DB(mvOsPrintf("Dram: DDR2 setting timing high with: %x \n", ddr2TimeHiReg)); -+ -+ return ddr2TimeHiReg; -+} -+#endif -+ -+/******************************************************************************* -+* mvDramIfCalGet - Get CAS Latency -+* -+* DESCRIPTION: -+* This function get the CAS Latency. -+* -+* INPUT: -+* None -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* CAS latency times 10 (to avoid using floating point). -+* -+*******************************************************************************/ -+MV_U32 mvDramIfCalGet(void) -+{ -+ MV_U32 sdramCasLat, casLatMask; -+ -+ casLatMask = (MV_REG_READ(SDRAM_MODE_REG) & SDRAM_CL_MASK); -+ -+ switch (casLatMask) -+ { -+ case SDRAM_DDR2_CL_3: -+ sdramCasLat = 30; -+ break; -+ case SDRAM_DDR2_CL_4: -+ sdramCasLat = 40; -+ break; -+ case SDRAM_DDR2_CL_5: -+ sdramCasLat = 50; -+ break; -+ case SDRAM_DDR2_CL_6: -+ sdramCasLat = 60; -+ break; -+ default: -+ mvOsOutput("mvDramIfCalGet: Err, unknown DDR2 CAL\n"); -+ return -1; -+ } -+ -+ return sdramCasLat; -+} -+ -+ -+/******************************************************************************* -+* mvDramIfSelfRefreshSet - Put the dram in self refresh mode - -+* -+* DESCRIPTION: -+* add support in power management. -+* -+* -+* INPUT: -+* None -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* None -+* -+*******************************************************************************/ -+ -+MV_VOID mvDramIfSelfRefreshSet() -+{ -+ MV_U32 operReg; -+ -+ operReg = MV_REG_READ(SDRAM_OPERATION_REG); -+ MV_REG_WRITE(SDRAM_OPERATION_REG ,operReg |SDRAM_CMD_SLF_RFRSH); -+ /* Read until register is reset to 0 */ -+ while(MV_REG_READ(SDRAM_OPERATION_REG)); -+} -+/******************************************************************************* -+* mvDramIfDimGetSPDversion - return DIMM SPD version. -+* -+* DESCRIPTION: -+* This function prints the DRAM controller information. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+static void mvDramIfDimGetSPDversion(MV_U32 *pMajor, MV_U32 *pMinor, MV_U32 bankNum) -+{ -+ MV_DIMM_INFO dimmInfo; -+ if (bankNum >= MV_DRAM_MAX_CS ) -+ { -+ DB(mvOsPrintf("Dram: mvDramIfDimGetSPDversion bad params \n")); -+ return ; -+ } -+ memset(&dimmInfo,0,sizeof(dimmInfo)); -+ if ( MV_OK != dimmSpdGet((MV_U32)(bankNum/2), &dimmInfo)) -+ { -+ DB(mvOsPrintf("Dram: ERR dimmSpdGet failed to get dimm info \n")); -+ return ; -+ } -+ *pMajor = dimmInfo.spdRawData[DIMM_SPD_VERSION]/10; -+ *pMinor = dimmInfo.spdRawData[DIMM_SPD_VERSION]%10; -+} -+/******************************************************************************* -+* mvDramIfShow - Show DRAM controller information. -+* -+* DESCRIPTION: -+* This function prints the DRAM controller information. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+void mvDramIfShow(void) -+{ -+ int i, sdramCasLat, sdramCsSize; -+ MV_U32 Major=0, Minor=0; -+ -+ mvOsOutput("DRAM Controller info:\n"); -+ -+ mvOsOutput("Total DRAM "); -+ mvSizePrint(mvDramIfSizeGet()); -+ mvOsOutput("\n"); -+ -+ for(i = 0; i < MV_DRAM_MAX_CS; i++) -+ { -+ sdramCsSize = mvDramIfBankSizeGet(i); -+ if (sdramCsSize) -+ { -+ if (0 == (i & 1)) -+ { -+ mvDramIfDimGetSPDversion(&Major, &Minor,i); -+ mvOsOutput("DIMM %d version %d.%d\n", i/2, Major, Minor); -+ } -+ mvOsOutput("\tDRAM CS[%d] ", i); -+ mvSizePrint(sdramCsSize); -+ mvOsOutput("\n"); -+ } -+ } -+ sdramCasLat = mvDramIfCalGet(); -+ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_ECC_EN) -+ { -+ mvOsOutput("ECC enabled, "); -+ } -+ else -+ { -+ mvOsOutput("ECC Disabled, "); -+ } -+ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_REGISTERED) -+ { -+ mvOsOutput("Registered DIMM\n"); -+ } -+ else -+ { -+ mvOsOutput("Non registered DIMM\n"); -+ } -+ -+ mvOsOutput("Configured CAS Latency %d.%d\n", sdramCasLat/10, sdramCasLat%10); -+} -+/******************************************************************************* -+* mvDramIfGetFirstCS - find the DRAM bank on the lower address -+* -+* -+* DESCRIPTION: -+* This function return the fisrt CS on address 0 -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* SDRAM_CS0 or SDRAM_CS2 -+* -+*******************************************************************************/ -+MV_U32 mvDramIfGetFirstCS(void) -+{ -+ MV_DRAM_BANK_INFO bankInfo[MV_DRAM_MAX_CS]; -+ -+ if (DRAM_CS_Order[0] == N_A) -+ { -+ mvDramBankInfoGet(SDRAM_CS0, &bankInfo[SDRAM_CS0]); -+#ifdef MV_INCLUDE_SDRAM_CS2 -+ mvDramBankInfoGet(SDRAM_CS2, &bankInfo[SDRAM_CS2]); -+#endif -+ -+#ifdef MV_INCLUDE_SDRAM_CS2 -+ if (bankInfo[SDRAM_CS0].size < bankInfo[SDRAM_CS2].size) -+ { -+ DRAM_CS_Order[0] = SDRAM_CS2; -+ DRAM_CS_Order[1] = SDRAM_CS3; -+ DRAM_CS_Order[2] = SDRAM_CS0; -+ DRAM_CS_Order[3] = SDRAM_CS1; -+ -+ return SDRAM_CS2; -+ } -+#endif -+ DRAM_CS_Order[0] = SDRAM_CS0; -+ DRAM_CS_Order[1] = SDRAM_CS1; -+#ifdef MV_INCLUDE_SDRAM_CS2 -+ DRAM_CS_Order[2] = SDRAM_CS2; -+ DRAM_CS_Order[3] = SDRAM_CS3; -+#endif -+ return SDRAM_CS0; -+ } -+ return DRAM_CS_Order[0]; -+} -+/******************************************************************************* -+* mvDramIfGetCSorder - -+* -+* -+* DESCRIPTION: -+* This function return the fisrt CS on address 0 -+* -+* INPUT: -+* CS number. -+* -+* OUTPUT: -+* CS order. -+* -+* RETURN: -+* SDRAM_CS0 or SDRAM_CS2 -+* -+* NOTE: mvDramIfGetFirstCS must be caled before this subroutine -+*******************************************************************************/ -+MV_U32 mvDramIfGetCSorder(MV_U32 csOrder ) -+{ -+ return DRAM_CS_Order[csOrder]; -+} -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,172 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvDramIfh -+#define __INCmvDramIfh -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* includes */ -+#include "ddr2/mvDramIfRegs.h" -+#include "ddr2/mvDramIfConfig.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+ -+/* defines */ -+/* DRAM Timing parameters */ -+#define SDRAM_TWR 15 /* ns tWr */ -+#define SDRAM_TRFC_64_512M_AT_200MHZ 70 /* ns tRfc for dens 64-512 @ 200MHz */ -+#define SDRAM_TRFC_64_512M 75 /* ns tRfc for dens 64-512 */ -+#define SDRAM_TRFC_1G 120 /* ns tRfc for dens 1GB */ -+#define SDRAM_TR2R_CYC 1 /* cycle for tR2r */ -+ -+#define CAL_AUTO_DETECT 0 /* Do not force CAS latancy (mvDramIfDetect) */ -+#define ECC_DISABLE 1 /* Force ECC to Disable */ -+#define ECC_ENABLE 0 /* Force ECC to ENABLE */ -+/* typedefs */ -+ -+/* enumeration for memory types */ -+typedef enum _mvMemoryType -+{ -+ MEM_TYPE_SDRAM, -+ MEM_TYPE_DDR1, -+ MEM_TYPE_DDR2 -+}MV_MEMORY_TYPE; -+ -+/* enumeration for DDR2 supported CAS Latencies */ -+typedef enum _mvDimmDdr2Cas -+{ -+ DDR2_CL_3 = 0x08, -+ DDR2_CL_4 = 0x10, -+ DDR2_CL_5 = 0x20, -+ DDR2_CL_6 = 0x40, -+ DDR2_CL_FAULT -+} MV_DIMM_DDR2_CAS; -+ -+ -+typedef struct _mvDramBankInfo -+{ -+ MV_MEMORY_TYPE memoryType; /* DDR1, DDR2 or SDRAM */ -+ -+ /* DIMM dimensions */ -+ MV_U32 numOfRowAddr; -+ MV_U32 numOfColAddr; -+ MV_U32 dataWidth; -+ MV_U32 errorCheckType; /* ECC , PARITY..*/ -+ MV_U32 sdramWidth; /* 4,8,16 or 32 */ -+ MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ -+ MV_U32 burstLengthSupported; -+ MV_U32 numOfBanksOnEachDevice; -+ MV_U32 suportedCasLatencies; -+ MV_U32 refreshInterval; -+ -+ /* DIMM timing parameters */ -+ MV_U32 minCycleTimeAtMaxCasLatPs; -+ MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; -+ MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; -+ MV_U32 minRowPrechargeTime; -+ MV_U32 minRowActiveToRowActive; -+ MV_U32 minRasToCasDelay; -+ MV_U32 minRasPulseWidth; -+ MV_U32 minWriteRecoveryTime; /* DDR2 only */ -+ MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ -+ MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ -+ MV_U32 minRefreshToActiveCmd; /* DDR2 only */ -+ -+ /* Parameters calculated from the extracted DIMM information */ -+ MV_U32 size; -+ MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit */ -+ MV_U32 numberOfDevices; -+ -+ /* DIMM attributes (MV_TRUE for yes) */ -+ MV_BOOL registeredAddrAndControlInputs; -+ MV_BOOL registeredDQMBinputs; -+ -+}MV_DRAM_BANK_INFO; -+ -+#include "ddr2/spd/mvSpd.h" -+ -+/* mvDramIf.h API list */ -+MV_VOID mvDramIfBasicAsmInit(MV_VOID); -+MV_STATUS mvDramIfDetect(MV_U32 forcedCl, MV_BOOL eccDisable); -+MV_VOID _mvDramIfConfig(int entryNum); -+ -+MV_U32 mvDramIfBankSizeGet(MV_U32 bankNum); -+MV_U32 mvDramIfBankBaseGet(MV_U32 bankNum); -+MV_U32 mvDramIfSizeGet(MV_VOID); -+MV_U32 mvDramIfCalGet(void); -+MV_STATUS mvDramIfSingleBitErrThresholdSet(MV_U32 threshold); -+MV_VOID mvDramIfSelfRefreshSet(void); -+void mvDramIfShow(void); -+MV_U32 mvDramIfGetFirstCS(void); -+MV_U32 mvDramIfGetCSorder(MV_U32 csOrder ); -+MV_U32 mvDramCsSizeGet(MV_U32 csNum); -+ -+#ifdef __cplusplus -+} -+#endif /* __cplusplus */ -+ -+#endif /* __INCmvDramIfh */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfBasicInit.S linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfBasicInit.S ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfBasicInit.S 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfBasicInit.S 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,986 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#define _ASMLANGUAGE -+#define MV_ASMLANGUAGE -+#include "mvSysHwConfig.h" -+#include "mvOsAsm.h" -+#include "boardEnv/mvBoardEnvSpec.h" -+#include "ctrlEnv/sys/mvCpuIfRegs.h" -+#include "mvDramIfConfig.h" -+#include "mvDramIfRegs.h" -+#include "pex/mvPexRegs.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+#include "ctrlEnv/mvCtrlEnvAsm.h" -+#include "mvCommon.h" -+ -+/* defines */ -+ -+#if defined(MV_STATIC_DRAM_ON_BOARD) -+.globl dramBoot1 -+dramBoot1: -+ .word 0 -+ -+/****************************************************************************** -+* -+* -+* -+* -+*******************************************************************************/ -+#if defined(DB_MV78XX0) || defined(DB_MV88F632X) -+/* DDR2 boards 512MB 333MHz */ -+#define STATIC_SDRAM0_BANK0_SIZE 0x1ffffff1 /* 0x1504 */ -+#define STATIC_SDRAM_CONFIG 0x43048C30 /* 0x1400 */ -+#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */ -+#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */ -+#define STATIC_DUNIT_CTRL_HI 0x0000FFFF /* 0x1424 */ -+#define STATIC_SDRAM_ADDR_CTRL 0x00000088 /* 0x1410 */ -+#define STATIC_SDRAM_TIME_CTRL_LOW 0x22125441 /* 0x1408 */ -+#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A29 /* 0x140c */ -+#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */ -+#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ -+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000E80F /* 0x149c */ -+#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */ -+#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ -+#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ -+ -+#elif defined(RD_MV78XX0_AMC) -+/* On board DDR2 512MB 400MHz CL5 */ -+#define STATIC_SDRAM0_BANK0_SIZE 0x1ffffff1 /* 0x1504 */ -+#define STATIC_SDRAM_CONFIG 0x43008C30 /* 0x1400 */ -+#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */ -+#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */ -+#define STATIC_DUNIT_CTRL_HI 0x0000F07F /* 0x1424 */ -+#define STATIC_SDRAM_ADDR_CTRL 0x000000DD /* 0x1410 */ -+#define STATIC_SDRAM_TIME_CTRL_LOW 0x23135441 /* 0x1408 */ -+#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A32 /* 0x140c */ -+#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */ -+#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ -+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000EB0F /* 0x149c */ -+#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */ -+#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ -+#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ -+ -+#elif defined(RD_MV78XX0_H3C) -+/* DDR2 boards 512MB 333MHz */ -+#define STATIC_SDRAM0_BANK0_SIZE 0x1ffffff1 /* 0x1504 */ -+#define STATIC_SDRAM_CONFIG 0x43048a25 /* 0x1400 */ -+#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */ -+#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */ -+#define STATIC_DUNIT_CTRL_HI 0x0000F07F /* 0x1424 */ -+#define STATIC_SDRAM_ADDR_CTRL 0x00000088 /* 0x1410 */ -+#define STATIC_SDRAM_TIME_CTRL_LOW 0x2202444e /* 0x1408 */ -+#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A22 /* 0x140c */ -+#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */ -+#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ -+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000EB0F /* 0x149c */ -+#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */ -+#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ -+#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ -+ -+#elif defined(RD_MV78XX0_PCAC) -+/* DDR2 boards 256MB 200MHz */ -+#define STATIC_SDRAM0_BANK0_SIZE 0x0ffffff1 /* 0x1504 */ -+#define STATIC_SDRAM_CONFIG 0x43000a25 /* 0x1400 */ -+#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */ -+#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */ -+#define STATIC_DUNIT_CTRL_HI 0x0000F07F /* 0x1424 */ -+#define STATIC_SDRAM_ADDR_CTRL 0x000000DD /* 0x1410 */ -+#define STATIC_SDRAM_TIME_CTRL_LOW 0x2202444e /* 0x1408 */ -+#define STATIC_SDRAM_TIME_CTRL_HI 0x00000822 /* 0x140c */ -+#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */ -+#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ -+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000EB0F /* 0x149c */ -+#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */ -+#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ -+#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ -+ -+#else -+/* DDR2 MV88F6281 boards 256MB 400MHz */ -+#define STATIC_SDRAM0_BANK0_SIZE 0x0FFFFFF1 /* 0x1504 */ -+#define STATIC_SDRAM_CONFIG 0x43000c30 /* 0x1400 */ -+#define STATIC_SDRAM_MODE 0x00000C52 /* 0x141c */ -+#define STATIC_DUNIT_CTRL_LOW 0x39543000 /* 0x1404 */ -+#define STATIC_DUNIT_CTRL_HI 0x0000F1FF /* 0x1424 */ -+#define STATIC_SDRAM_ADDR_CTRL 0x000000cc /* 0x1410 */ -+#define STATIC_SDRAM_TIME_CTRL_LOW 0x22125451 /* 0x1408 */ -+#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A33 /* 0x140c */ -+#define STATIC_SDRAM_ODT_CTRL_LOW 0x003C0000 /* 0x1494 */ -+#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ -+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000F80F /* 0x149c */ -+#define STATIC_SDRAM_EXT_MODE 0x00000042 /* 0x1420 */ -+#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ -+#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ -+#endif /* MV78XX0 */ -+ -+ .globl _mvDramIfStaticInit -+_mvDramIfStaticInit: -+ -+ mov r11, LR /* Save link register */ -+ mov r10, r2 -+ -+#ifdef MV78XX0 -+ MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) -+ orr r6, r6, #BIT4 /* Enable 2T mode */ -+ bic r6, r6, #BIT6 /* clear ctrlPos */ -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) -+#endif -+ -+ /*DDR SDRAM Initialization Control */ -+ ldr r6, =DSICR_INIT_EN -+ MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) -+2: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) -+ and r6, r6, #DSICR_INIT_EN -+ cmp r6, #0 -+ bne 2b -+ -+ /* If we boot from NAND jump to DRAM address */ -+ mov r5, #1 -+ ldr r6, =dramBoot1 -+ str r5, [r6] /* We started executing from DRAM */ -+ -+ ldr r6, dramBoot1 -+ cmp r6, #0 -+ bne 1f -+ -+ /* set all dram windows to 0 */ -+ mov r6, #0 -+ MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,0)) -+ MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,1)) -+ MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,2)) -+ MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,3)) -+ ldr r6, = STATIC_SDRAM0_BANK0_SIZE -+ MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,0)) -+ -+ -+ /* set all dram configuration in temp registers */ -+ ldr r6, = STATIC_SDRAM0_BANK0_SIZE -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG0) -+ ldr r6, = STATIC_SDRAM_CONFIG -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG1) -+ ldr r6, = STATIC_SDRAM_MODE -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG2) -+ ldr r6, = STATIC_DUNIT_CTRL_LOW -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG3) -+ ldr r6, = STATIC_SDRAM_ADDR_CTRL -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG4) -+ ldr r6, = STATIC_SDRAM_TIME_CTRL_LOW -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG5) -+ ldr r6, = STATIC_SDRAM_TIME_CTRL_HI -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG6) -+ ldr r6, = STATIC_SDRAM_ODT_CTRL_LOW -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG7) -+ ldr r6, = STATIC_SDRAM_ODT_CTRL_HI -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG8) -+ ldr r6, = STATIC_SDRAM_DUNIT_ODT_CTRL -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG9) -+ ldr r6, = STATIC_SDRAM_EXT_MODE -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG10) -+ ldr r6, = STATIC_SDRAM_DDR2_TIMING_LO -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG11) -+ ldr r6, = STATIC_SDRAM_DDR2_TIMING_HI -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG12) -+#ifndef MV_NAND_BOOT -+ ldr r6, = STATIC_DUNIT_CTRL_HI -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG13) -+#endif -+ -+ ldr sp,=0 -+ bl _mvDramIfConfig -+ ldr r0, =0 -+#ifdef MV78XX0 -+ bl _mvDramIfEccMemInit -+#endif -+1: -+ mov r2, r10 -+ mov PC, r11 /* r11 is saved link register */ -+ -+#else /* #if defined(MV_STATIC_DRAM_ON_BOARD) */ -+ -+.globl dramBoot1 -+dramBoot1: -+ .word 0 -+ -+/******************************************************************************* -+* mvDramIfBasicInit - Basic initialization of DRAM interface -+* -+* DESCRIPTION: -+* The function will initialize the DRAM for basic usage. The function -+* will use the TWSI assembly API to extract DIMM parameters according -+* to which DRAM interface will be initialized. -+* The function referes to the following DRAM parameters: -+* 1) DIMM is registered or not. -+* 2) DIMM width detection. -+* 3) DIMM density. -+* -+* INPUT: -+* r3 - required size for initial DRAM. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+* Note: -+* r4 holds I2C EEPROM address -+* r5 holds SDRAM register base address -+* r7 holds returned values -+* r8 holds SDRAM various configuration registers value. -+* r11 holds return function address. -+*******************************************************************************/ -+/* Setting the offsets of the I2C registers */ -+#define DIMM_TYPE_OFFSET 2 -+#define NUM_OF_ROWS_OFFSET 3 -+#define NUM_OF_COLS_OFFSET 4 -+#define NUM_OF_RANKS 5 -+#define DIMM_CONFIG_TYPE 11 -+#define SDRAM_WIDTH_OFFSET 13 -+#define NUM_OF_BANKS_OFFSET 17 -+#define SUPPORTED_CL_OFFSET 18 -+#define DIMM_TYPE_INFO_OFFSET 20 /* DDR2 only */ -+#define SDRAM_MODULES_ATTR_OFFSET 21 -+#define RANK_SIZE_OFFSET 31 -+ -+#define DRAM_DEV_DENSITY_128M 128 -+#define DRAM_DEV_DENSITY_256M 256 -+#define DRAM_DEV_DENSITY_512M 512 -+#define DRAM_DEV_DENSITY_1G 1024 -+#define DRAM_DEV_DENSITY_2G 2048 -+ -+#define DRAM_RANK_DENSITY_128M 0x20 -+#define DRAM_RANK_DENSITY_256M 0x40 -+#define DRAM_RANK_DENSITY_512M 0x80 -+#define DRAM_RANK_DENSITY_1G 0x1 -+#define DRAM_RANK_DENSITY_2G 0x2 -+ -+ .globl _mvDramIfBasicInit -+ .extern _i2cInit -+_mvDramIfBasicInit: -+ -+ mov r11, LR /* Save link register */ -+ -+ /* Set Dunit high control register */ -+ MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_HI_REG) -+ orr r6, r6, #BIT7 /* SDRAM__D2P_EN */ -+ orr r6, r6, #BIT8 /* SDRAM__P2D_EN */ -+#ifdef MV78XX0 -+ orr r6, r6, #BIT9 /* SDRAM__ADD_HALF_FCC_EN */ -+ orr r6, r6, #BIT10 /* SDRAM__PUP_ZERO_SKEW_EN */ -+ orr r6, r6, #BIT11 /* SDRAM__WR_MASH_DELAY_EN */ -+#endif -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_HI_REG) -+ -+#ifdef MV78XX0 -+ MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) -+ orr r6, r6, #BIT4 /* Enable 2T mode */ -+ bic r6, r6, #BIT6 /* clear ctrlPos */ -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) -+#endif -+ -+ /*DDR SDRAM Initialization Control */ -+ ldr r6, =DSICR_INIT_EN -+ MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) -+2: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) -+ and r6, r6, #DSICR_INIT_EN -+ cmp r6, #0 -+ bne 2b -+ -+ mov r5, #1 -+ ldr r8, =dramBoot1 -+ str r5, [r8] /* We started executing from DRAM */ -+ -+ /* If we boot from NAND jump to DRAM address */ -+ ldr r8, dramBoot1 -+ cmp r8, #0 -+ movne pc, r11 -+ -+ bl _i2cInit /* Initialize TWSI master */ -+ -+ /* Check if we have more then 1 dimm */ -+ ldr r6, =0 -+ MV_REG_WRITE_ASM (r6, r1, DRAM_BUF_REG14) -+#ifdef MV78XX0 -+ bl _is_Second_Dimm_Exist -+ beq single_dimm -+ ldr r6, =1 -+ MV_REG_WRITE_ASM (r6, r1, DRAM_BUF_REG14) -+single_dimm: -+ bl _i2cInit /* Initialize TWSI master */ -+#endif -+ -+ /* Get default SDRAM Config values */ -+ MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG) -+ -+ /* Get registered/non registered info from DIMM */ -+ bl _is_Registered -+ beq nonRegistered -+ -+setRegistered: -+ orr r8, r8, #SDRAM_REGISTERED /* Set registered bit(17) */ -+nonRegistered: -+#ifdef MV78XX0 -+ /* Get ECC/non ECC info from DIMM */ -+ bl _is_Ecc -+ beq setConfigReg -+ -+setEcc: -+ orr r8, r8, #SDRAM_ECC_EN /* Set ecc bit(18) */ -+#endif -+setConfigReg: -+ MV_REG_WRITE_ASM (r8, r5, DRAM_BUF_REG1) -+ -+ /* Set maximum CL supported by DIMM */ -+ bl _get_CAL -+ -+ /* r7 is DIMM supported CAS (e.g: 3 --> 0x1C) */ -+ clz r6, r7 -+ rsb r6, r6, #31 /* r6 = the bit number of MAX CAS supported */ -+ -+casDdr2: -+ ldr r7, =0x41 /* stBurstInDel|stBurstOutDel field value */ -+ ldr r3, =0x53 /* stBurstInDel|stBurstOutDel registered value*/ -+ ldr r8, =0x32 /* Assuming MAX CL = 3 */ -+ cmp r6, #3 /* If CL = 3 break */ -+ beq casDdr2Cont -+ -+ ldr r7, =0x53 /* stBurstInDel|stBurstOutDel field value */ -+ ldr r3, =0x65 /* stBurstInDel|stBurstOutDel registered value*/ -+ ldr r8, =0x42 /* Assuming MAX CL = 4 */ -+ cmp r6, #4 /* If CL = 4 break */ -+ beq casDdr2Cont -+ -+ ldr r7, =0x65 /* stBurstInDel|stBurstOutDel field value */ -+ ldr r3, =0x77 /* stBurstInDel|stBurstOutDel registered value*/ -+ ldr r8, =0x52 /* Assuming MAX CL = 5 */ -+ cmp r6, #5 /* If CL = 5 break */ -+ beq casDdr2Cont -+ -+ ldr r7, =0x77 /* stBurstInDel|stBurstOutDel field value */ -+ ldr r3, =0x89 /* stBurstInDel|stBurstOutDel registered value*/ -+ ldr r8, =0x62 /* Assuming MAX CL = 6 */ -+ cmp r6, #6 /* If CL = 5 break */ -+ beq casDdr2Cont -+ -+ /* This is an error. return */ -+ b exit_ddrAutoConfig /* This is an error !! */ -+casDdr2Cont: -+ -+ /* Get default SDRAM Mode values */ -+ MV_REG_READ_ASM (r6, r5, SDRAM_MODE_REG) -+ bic r6, r6, #(BIT6 | BIT5 | BIT4) /* Clear CL filed */ -+ orr r6, r6, r8 -+ MV_REG_WRITE_ASM (r6, r5, DRAM_BUF_REG2) -+ -+ /* Set Dunit control register according to max CL detected */ -+ MV_REG_READ_ASM (r6, r5, DRAM_BUF_REG1) -+ tst r6, #SDRAM_REGISTERED -+ beq setDunitReg -+ mov r7, r3 -+ -+setDunitReg: -+#ifdef MV78XX0 -+ /* Set SDRAM Extended Mode register for double DIMM */ -+ /* Check DRAM frequency for more then 267MHz set ODT Rtt to 50ohm */ -+ -+ MV_REG_READ_ASM (r4, r5, CPU_RESET_SAMPLE_L_REG) -+ ldr r5, =MSAR_SYSCLCK_MASK -+ and r4, r4, r5 -+ ldr r5, =MSAR_SYSCLCK_333 -+ cmp r4, r5 -+ ble Clock333 -+ add r7, r7, #0x10 -+Clock333: -+#endif -+ -+ MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) -+ bic r6, r6, #(0xff << 20) /* Clear SBout and SBin */ -+ orr r6, r6, #BIT4 /* Enable 2T mode */ -+ bic r6, r6, #BIT6 /* clear ctrlPos */ -+ orr r6, r6, r7, LSL #20 -+ MV_REG_WRITE_ASM (r6, r5, DRAM_BUF_REG3) -+ -+ /* Set Dunit high control register */ -+ MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_HI_REG) -+ orr r6, r6, #BIT7 /* SDRAM__D2P_EN */ -+ orr r6, r6, #BIT8 /* SDRAM__P2D_EN */ -+#ifdef MV78XX0 -+ orr r6, r6, #BIT9 /* SDRAM__ADD_HALF_FCC_EN */ -+ orr r6, r6, #BIT10 /* SDRAM__PUP_ZERO_SKEW_EN */ -+ orr r6, r6, #BIT11 /* SDRAM__WR_MASH_DELAY_EN */ -+#endif -+ MV_REG_WRITE_ASM (r6, r5, DRAM_BUF_REG13) -+ -+ /* DIMM density configuration*/ -+ /* Density = (1 << (rowNum + colNum)) * dramWidth * dramBankNum */ -+Density: -+ /* Get bank 0 and 1 density */ -+ ldr r6, =0 -+ bl _getDensity -+ -+ mov r8, r7 -+ mov r8, r8, LSR #20 /* Move density 20 bits to the right */ -+ /* For example 0x10000000 --> 0x1000 */ -+ -+ mov r3, #(SDRAM_DSIZE_256Mb(0) | SDRAM_DSIZE_256Mb(1)) -+ cmp r8, #DRAM_DEV_DENSITY_256M -+ beq get_bank_2_density -+ -+ mov r3, #(SDRAM_DSIZE_512Mb(0) | SDRAM_DSIZE_512Mb(1)) -+ cmp r8, #DRAM_DEV_DENSITY_512M -+ beq get_bank_2_density -+ -+ mov r3, #(SDRAM_DSIZE_1Gb(0) | SDRAM_DSIZE_1Gb(1)) -+ cmp r8, #DRAM_DEV_DENSITY_1G -+ beq get_bank_2_density -+ -+ mov r3, #(SDRAM_DSIZE_2Gb(0) | SDRAM_DSIZE_2Gb(1)) -+ cmp r8, #DRAM_DEV_DENSITY_2G -+ beq get_bank_2_density -+ -+ /* This is an error. return */ -+ b exit_ddrAutoConfig -+ -+get_bank_2_density: -+ /* Check for second dimm */ -+ MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14) -+ cmp r6, #1 -+ bne get_width -+ -+ /* Get bank 2 and 3 density */ -+ ldr r6, =2 -+ bl _getDensity -+ -+ mov r8, r7 -+ mov r8, r8, LSR #20 /* Move density 20 bits to the right */ -+ /* For example 0x10000000 --> 0x1000 */ -+ -+ orr r3, r3, #(SDRAM_DSIZE_256Mb(2) | SDRAM_DSIZE_256Mb(3)) -+ cmp r8, #DRAM_DEV_DENSITY_256M -+ beq get_width -+ -+ and r3, r3, #~(SDRAM_DSIZE_MASK(2) | SDRAM_DSIZE_MASK(3)) -+ orr r3, r3, #(SDRAM_DSIZE_512Mb(2) | SDRAM_DSIZE_512Mb(3)) -+ cmp r8, #DRAM_DEV_DENSITY_512M -+ beq get_width -+ -+ and r3, r3, #~(SDRAM_DSIZE_MASK(2) | SDRAM_DSIZE_MASK(3)) -+ orr r3, r3, #(SDRAM_DSIZE_1Gb(2) | SDRAM_DSIZE_1Gb(3)) -+ cmp r8, #DRAM_DEV_DENSITY_1G -+ beq get_width -+ -+ and r3, r3, #~(SDRAM_DSIZE_MASK(2) | SDRAM_DSIZE_MASK(3)) -+ orr r3, r3, #(SDRAM_DSIZE_2Gb(2) | SDRAM_DSIZE_2Gb(3)) -+ cmp r8, #DRAM_DEV_DENSITY_2G -+ beq get_width -+ -+ /* This is an error. return */ -+ b exit_ddrAutoConfig -+ -+ /* Get SDRAM width */ -+get_width: -+ /* Get bank 0 and 1 width */ -+ ldr r6, =0 -+ bl _get_width -+ -+ cmp r7, #8 /* x8 devices */ -+ beq get_bank_2_width -+ -+ orr r3, r3, #(SDRAM_ADDRSEL_X16(0) | SDRAM_ADDRSEL_X16(1)) /* x16 devices */ -+ cmp r7, #16 -+ beq get_bank_2_width -+ -+ /* This is an error. return */ -+ b exit_ddrAutoConfig -+ -+get_bank_2_width: -+ /* Check for second dimm */ -+ MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14) -+ cmp r6, #1 -+ bne densCont -+ -+ /* Get bank 2 and 3 width */ -+ ldr r6, =2 -+ bl _get_width -+ -+ cmp r7, #8 /* x8 devices */ -+ beq densCont -+ -+ orr r3, r3, #(SDRAM_ADDRSEL_X16(2) | SDRAM_ADDRSEL_X16(3)) /* x16 devices */ -+ cmp r7, #16 -+ beq densCont -+ -+ /* This is an error. return */ -+ b exit_ddrAutoConfig -+ -+densCont: -+ MV_REG_WRITE_ASM (r3, r5, DRAM_BUF_REG4) -+ -+ /* Set SDRAM timing control low register */ -+ ldr r4, =SDRAM_TIMING_CTRL_LOW_REG_DEFAULT -+ /* MV_REG_READ_ASM (r4, r5, SDRAM_TIMING_CTRL_LOW_REG) */ -+ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG5) -+ -+ /* Set SDRAM timing control high register */ -+ ldr r6, =SDRAM_TIMING_CTRL_HIGH_REG_DEFAULT -+ -+ MV_REG_READ_ASM (r4, r5, CPU_RESET_SAMPLE_L_REG) -+ ldr r5, =MSAR_SYSCLCK_MASK -+ and r4, r4, r5 -+ ldr r5, =MSAR_SYSCLCK_333 -+ cmp r4, r5 -+ blt timingHighClock333 -+ orr r6, r6, #BIT9 -+ -+timingHighClock333: -+ /* MV_REG_READ_ASM (r6, r5, SDRAM_TIMING_CTRL_HIGH_REG) */ -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG6) -+ -+ /* Check for second dimm */ -+ MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14) -+ cmp r6, #1 -+ bne single_dimm_odt -+ -+ /* Set SDRAM ODT control low register for double DIMM*/ -+ ldr r4, =DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV -+ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG7) -+ -+ /* Set DUNIT ODT control register for double DIMM */ -+ ldr r4, =DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV -+ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG9) -+ -+#ifdef MV78XX0 -+ /* Set SDRAM Extended Mode register for double DIMM */ -+ /* Check DRAM frequency for more then 267MHz set ODT Rtt to 50ohm */ -+ -+ MV_REG_READ_ASM (r4, r5, CPU_RESET_SAMPLE_L_REG) -+ ldr r5, =MSAR_SYSCLCK_MASK -+ and r4, r4, r5 -+ ldr r5, =MSAR_SYSCLCK_267 -+ cmp r4, r5 -+ beq slow_dram_clock_rtt -+ ldr r5, =MSAR_SYSCLCK_300 -+ cmp r4, r5 -+ beq slow_dram_clock_rtt -+ ldr r5, =MSAR_SYSCLCK_333 -+ cmp r4, r5 -+ beq fast_dram_clock_rtt -+ ldr r5, =MSAR_SYSCLCK_400 -+ cmp r4, r5 -+ beq fast_dram_clock_rtt -+ -+ b slow_dram_clock_rtt -+ -+fast_dram_clock_rtt: -+ ldr r4, =DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV -+ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG10) -+ b odt_config_end -+#endif -+slow_dram_clock_rtt: -+ ldr r4, =DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV -+ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG10) -+ b odt_config_end -+ -+single_dimm_odt: -+ /* Set SDRAM ODT control low register */ -+ ldr r4, =DDR2_ODT_CTRL_LOW_CS0_CS1_DV -+ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG7) -+ -+ /* Set DUNIT ODT control register */ -+ ldr r4, =DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV -+ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG9) -+ -+ /* Set SDRAM Extended Mode register */ -+ ldr r4, =DDR_SDRAM_EXT_MODE_CS0_CS1_DV -+ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG10) -+ -+odt_config_end: -+ /* SDRAM ODT control high register is left as default */ -+ MV_REG_READ_ASM (r4, r5, DDR2_SDRAM_ODT_CTRL_HIGH_REG) -+ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG8) -+ -+ /*Read CL and set the DDR2 registers accordingly */ -+ MV_REG_READ_ASM (r6, r5, DRAM_BUF_REG2) -+ and r6, r6, #SDRAM_CL_MASK -+ mov r4, r6 -+ orr r4, r4, r6, LSL #4 -+ orr r4, r4, r6, LSL #8 -+ orr r4, r4, r6, LSL #12 -+ mov r5, #0x30000 -+ add r4, r4, r5 -+ sub r4, r4, #0x30 -+ /* Set SDRAM Ddr2 Timing Low register */ -+ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG11) -+ -+ /* Set SDRAM Ddr2 Timing High register */ -+ mov r4, r4, LSR #4 -+ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG12) -+ -+timeParamDone: -+ /* Close all windows */ -+ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) -+ and r6, r6,#~SCSR_SIZE_MASK -+ and r6, r6,#~1 -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) -+ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,1)) -+ and r6, r6,#~SCSR_SIZE_MASK -+ and r6, r6,#~1 -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,1)) -+ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) -+ and r6, r6,#~SCSR_SIZE_MASK -+ and r6, r6,#~1 -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) -+ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,3)) -+ and r6, r6,#~SCSR_SIZE_MASK -+ and r6, r6,#~1 -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,3)) -+ -+ /* Set sdram bank 0 size and enable it */ -+ ldr r6, =0 -+ bl _mvDramIfGetDimmSizeFromSpd -+#ifdef MV78XX0 -+ /* Check DRAM width */ -+ MV_REG_READ_ASM (r4, r5, SDRAM_CONFIG_REG) -+ ldr r5, =SDRAM_DWIDTH_MASK -+ and r4, r4, r5 -+ ldr r5, =SDRAM_DWIDTH_64BIT -+ cmp r4, r5 -+ beq dram_64bit_width -+ /* Utilize only 32bit width */ -+ mov r8, r8, LSR #1 -+#else -+ /* Utilize only 16bit width */ -+ mov r8, r8, LSR #2 -+#endif -+dram_64bit_width: -+ /* Update first dimm size return value R8 */ -+ MV_REG_READ_ASM (r5, r6, SDRAM_SIZE_REG(0,0)) -+ ldr r6, =~SCSR_SIZE_MASK -+ and r5, r5, r6 -+ orr r5, r5, r8 -+ MV_REG_WRITE_ASM(r5, r8, SDRAM_SIZE_REG(0,0)) -+ -+ /* Clear bank 2 size */ -+ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) -+ and r6, r6,#~SCSR_SIZE_MASK -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) -+ -+ /* Check for second dimm */ -+ MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14) -+ cmp r6, #1 -+ bne defualt_order -+ -+ /* Set sdram bank 2 size */ -+ ldr r6, =2 -+ bl _mvDramIfGetDimmSizeFromSpd -+#ifdef MV78XX0 -+ /* Check DRAM width */ -+ MV_REG_READ_ASM (r4, r5, SDRAM_CONFIG_REG) -+ ldr r5, =SDRAM_DWIDTH_MASK -+ and r4, r4, r5 -+ ldr r5, =SDRAM_DWIDTH_64BIT -+ cmp r4, r5 -+ beq dram_64bit_width2 -+ /* Utilize only 32bit width */ -+ mov r8, r8, LSR #1 -+#else -+ /* Utilize only 16bit width */ -+ mov r8, r8, LSR #2 -+#endif -+dram_64bit_width2: -+ /* Update first dimm size return value R8 */ -+ MV_REG_READ_ASM (r5, r6, SDRAM_SIZE_REG(0,2)) -+ ldr r6, =~SCSR_SIZE_MASK -+ and r5, r5, r6 -+ orr r5, r5, r8 -+ MV_REG_WRITE_ASM(r5, r8, SDRAM_SIZE_REG(0,2)) -+ -+ /* Close windows 1 and 3 */ -+ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,1)) -+ and r6, r6,#~1 -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,1)) -+ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,3)) -+ and r6, r6,#~1 -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,3)) -+ -+ /* Check dimm size for setting dram bank order */ -+ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) -+ MV_REG_READ_ASM (r4, r5, SDRAM_SIZE_REG(0,2)) -+ and r6, r6,#SCSR_SIZE_MASK -+ and r4, r4,#SCSR_SIZE_MASK -+ cmp r6, r4 -+ bge defualt_order -+ -+ /* Bank 2 is biger then bank 0 */ -+ ldr r6,=0 -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_BASE_ADDR_REG(0,2)) -+ -+ /* Open win 2 */ -+ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) -+ orr r6, r6,#1 -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) -+ -+ ldr sp,=0 -+ bl _mvDramIfConfig -+#ifdef MV78XX0 -+ /* Init ECC on CS 2 */ -+ ldr r0, =2 -+ bl _mvDramIfEccMemInit -+#endif -+ mov PC, r11 /* r11 is saved link register */ -+ -+defualt_order: -+ -+ /* Open win 0 */ -+ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) -+ orr r6, r6,#1 -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) -+ -+ ldr sp,=0 -+ bl _mvDramIfConfig -+#ifdef MV78XX0 -+ /* Init ECC on CS 0 */ -+ ldr r0, =0 -+ bl _mvDramIfEccMemInit -+#endif -+exit_ddrAutoConfig: -+ mov PC, r11 /* r11 is saved link register */ -+ -+ -+/***************************************************************************************/ -+/* r4 holds I2C EEPROM address -+ * r7 holds I2C EEPROM offset parameter for i2cRead and its --> returned value -+ * r8 holds SDRAM various configuration registers value. -+ * r13 holds Link register -+ */ -+/**************************/ -+_getDensity: -+ mov r13, LR /* Save link register */ -+ -+ /* Read SPD rank size from DIMM0 */ -+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ -+ -+ cmp r6, #0 -+ beq 1f -+ -+ /* Read SPD rank size from DIMM1 */ -+ mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM1 */ -+ -+1: -+ mov r7, #NUM_OF_ROWS_OFFSET /* offset 3 */ -+ bl _i2cRead -+ mov r8, r7 /* r8 save number of rows */ -+ -+ mov r7, #NUM_OF_COLS_OFFSET /* offset 4 */ -+ bl _i2cRead -+ add r8, r8, r7 /* r8 = number of rows + number of col */ -+ -+ mov r7, #0x1 -+ mov r8, r7, LSL r8 /* r8 = (1 << r8) */ -+ -+ mov r7, #SDRAM_WIDTH_OFFSET /* offset 13 */ -+ bl _i2cRead -+ mul r8, r7, r8 -+ -+ mov r7, #NUM_OF_BANKS_OFFSET /* offset 17 */ -+ bl _i2cRead -+ mul r7, r8, r7 -+ -+ mov PC, r13 -+ -+/**************************/ -+_get_width: -+ mov r13, LR /* Save link register */ -+ -+ /* Read SPD rank size from DIMM0 */ -+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ -+ -+ cmp r6, #0 -+ beq 1f -+ -+ /* Read SPD rank size from DIMM1 */ -+ mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM1 */ -+ -+1: -+ /* Get SDRAM width (SPD offset 13) */ -+ mov r7, #SDRAM_WIDTH_OFFSET -+ bl _i2cRead /* result in r7 */ -+ -+ mov PC, r13 -+ -+/**************************/ -+_get_CAL: -+ mov r13, LR /* Save link register */ -+ -+ /* Set maximum CL supported by DIMM */ -+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ -+ mov r7, #SUPPORTED_CL_OFFSET /* offset 18 */ -+ bl _i2cRead -+ -+ mov PC, r13 -+ -+/**************************/ -+/* R8 - sdram configuration register. -+ * Return value in flag if no-registered then Z-flag is set -+ */ -+_is_Registered: -+ mov r13, LR /* Save link register */ -+#if defined(MV645xx) -+ /* Get registered/non registered info from DIMM */ -+ tst r8, #SDRAM_DTYPE_DDR2 -+ bne regDdr2 -+ -+regDdr1: -+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ -+ mov r7, #SDRAM_MODULES_ATTR_OFFSET -+ bl _i2cRead /* result in r7 */ -+ -+ tst r7, #0x2 -+ b exit -+#endif -+regDdr2: -+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ -+ mov r7, #DIMM_TYPE_INFO_OFFSET -+ bl _i2cRead /* result in r7 */ -+ -+ tst r7, #0x11 /* DIMM type = regular RDIMM (0x01) */ -+ /* or Mini-RDIMM (0x10) */ -+exit: -+ mov PC, r13 -+ -+ -+/**************************/ -+/* Return value in flag if no-Ecc then Z-flag is set */ -+_is_Ecc: -+ mov r13, LR /* Save link register */ -+ -+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ -+ mov r7, #DIMM_CONFIG_TYPE -+ bl _i2cRead /* result in r7 */ -+ -+ tst r7, #0x2 /* bit 1 -> Data ECC */ -+ mov PC, r13 -+ -+/**************************/ -+/* Return value in flag if no second DIMM then Z-flag is set */ -+_is_Second_Dimm_Exist: -+ mov r13, LR /* Save link register */ -+ -+ mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM0 */ -+ mov r7, #DIMM_TYPE_OFFSET -+ bl _i2cRead /* result in r7 */ -+ -+ tst r7, #0x8 /* bit3 is '1' -> DDR 2 */ -+ mov PC, r13 -+ -+/******************************************************************************* -+* _mvDramIfGetDimmSizeFromSpd - read bank 0 dram's size -+* -+* DESCRIPTION: -+* The function will read the bank 0 dram size(SPD version 1.0 and above ) -+* -+* INPUT: -+* r6 - dram bank number. -+* -+* OUTPUT: -+* none -+*/ -+_mvDramIfGetDimmSizeFromSpd: -+ -+ mov r13, LR /* Save link register */ -+ -+ /* Read SPD rank size from DIMM0 */ -+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ -+ -+ cmp r6, #0 -+ beq 1f -+ -+ /* Read SPD rank size from DIMM1 */ -+ mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM1 */ -+ -+1: -+ mov r7, #RANK_SIZE_OFFSET /* offset 31 */ -+ bl _i2cRead -+ -+pass_read: -+ ldr r8, =(0x7 << SCSR_SIZE_OFFS) -+ cmp r7, #DRAM_RANK_DENSITY_128M -+ beq endDimmSize -+ -+ ldr r8, =(0xf << SCSR_SIZE_OFFS) -+ cmp r7, #DRAM_RANK_DENSITY_256M -+ beq endDimmSize -+ -+ ldr r8, =(0x1f << SCSR_SIZE_OFFS) -+ cmp r7, #DRAM_RANK_DENSITY_512M -+ beq endDimmSize -+ -+ ldr r8, =(0x3f << SCSR_SIZE_OFFS) -+ cmp r7, #DRAM_RANK_DENSITY_1G -+ beq endDimmSize -+ -+ ldr r8, =(0x7f << SCSR_SIZE_OFFS) /* DRAM_RANK_DENSITY_2G */ -+endDimmSize: -+ mov PC, r13 -+#endif -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.S linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.S ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.S 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.S 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,528 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+/******************************************************************************* -+* mvDramIfBasicAsm.s -+* -+* DESCRIPTION: -+* Memory full detection and best timing configuration is done in -+* C code. C runtime environment requires a stack. This module API -+* initialize DRAM interface chip select 0 for basic functionality for -+* the use of stack. -+* The module API assumes DRAM information is stored in I2C EEPROM reside -+* in a given I2C address MV_BOARD_DIMM0_I2C_ADDR. The I2C EEPROM -+* internal data structure is assumed to be orgenzied in common DRAM -+* vendor SPD structure. -+* NOTE: DFCDL values are assumed to be already initialized prior to -+* this module API activity. -+* -+* -+* DEPENDENCIES: -+* None. -+* -+*******************************************************************************/ -+ -+/* includes */ -+#define _ASMLANGUAGE -+#define MV_ASMLANGUAGE -+#include "mvOsAsm.h" -+#include "mvSysHwConfig.h" -+#include "mvDramIfRegs.h" -+#include "mvDramIfConfig.h" -+#include "ctrlEnv/sys/mvCpuIfRegs.h" -+#include "pex/mvPexRegs.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+#include "mvCommon.h" -+ -+/* defines */ -+ -+/* locals */ -+.data -+.globl _mvDramIfConfig -+.text -+.globl _mvDramIfMemInit -+ -+/******************************************************************************* -+* _mvDramIfConfig - Basic DRAM interface initialization. -+* -+* DESCRIPTION: -+* The function will initialize the following DRAM parameters using the -+* values prepared by mvDramIfDetect routine. Values are located -+* in predefined registers. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+ -+_mvDramIfConfig: -+ -+ /* Save register on stack */ -+ cmp sp, #0 -+ beq no_stack_s -+save_on_stack: -+ stmdb sp!, {r1, r2, r3, r4} -+no_stack_s: -+ -+ /* Dunit FTDLL Configuration Register */ -+ /* 0) Write to SDRAM FTDLL coniguration register */ -+ ldr r4, = SDRAM_FTDLL_REG_DEFAULT_LEFT; -+ ldr r1, =(INTER_REGS_BASE + SDRAM_FTDLL_CONFIG_LEFT_REG) -+ str r4, [r1] -+ ldr r4, = SDRAM_FTDLL_REG_DEFAULT_RIGHT; -+ ldr r1, =(INTER_REGS_BASE + SDRAM_FTDLL_CONFIG_RIGHT_REG) -+ str r4, [r1] -+ ldr r4, = SDRAM_FTDLL_REG_DEFAULT_UP; -+ ldr r1, =(INTER_REGS_BASE + SDRAM_FTDLL_CONFIG_UP_REG) -+ str r4, [r1] -+ -+ /* 1) Write to SDRAM coniguration register */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG1) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + SDRAM_CONFIG_REG) -+ str r4, [r1] -+ -+ /* 2) Write Dunit control low register */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG3) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + SDRAM_DUNIT_CTRL_REG) -+ str r4, [r1] -+ -+ /* 2) Write Dunit control high register */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG13) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + SDRAM_DUNIT_CTRL_HI_REG) -+ str r4, [r1] -+ -+ /* 3) Write SDRAM address control register */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG4) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + SDRAM_ADDR_CTRL_REG) -+ str r4, [r1] -+#if defined(MV_STATIC_DRAM_ON_BOARD) -+ /* 4) Write SDRAM bank 0 size register */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG0) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + SDRAM_SIZE_REG(0,0)) -+ str r4, [r1] -+#endif -+ -+ /* 5) Write SDRAM open pages control register */ -+ ldr r1, =(INTER_REGS_BASE + SDRAM_OPEN_PAGE_CTRL_REG) -+ ldr r4, =SDRAM_OPEN_PAGES_CTRL_REG_DV -+ str r4, [r1] -+ -+ /* 6) Write SDRAM timing Low register */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG5) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_LOW_REG) -+ str r4, [r1] -+ -+ /* 7) Write SDRAM timing High register */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG6) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_HIGH_REG) -+ str r4, [r1] -+ -+ /* Config DDR2 On Die Termination (ODT) registers */ -+ /* Write SDRAM DDR2 ODT control low register */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG7) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_LOW_REG) -+ str r4, [r1] -+ -+ /* Write SDRAM DDR2 ODT control high register */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG8) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_HIGH_REG) -+ str r4, [r1] -+ -+ /* Write SDRAM DDR2 Dunit ODT control register */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG9) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + DDR2_DUNIT_ODT_CONTROL_REG) -+ str r4, [r1] -+ -+ /* Write DDR2 SDRAM timing Low register */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG11) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + SDRAM_DDR2_TIMING_LO_REG) -+ str r4, [r1] -+ -+ /* Write DDR2 SDRAM timing High register */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG12) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + SDRAM_DDR2_TIMING_HI_REG) -+ str r4, [r1] -+ -+ /* 8) Write SDRAM mode register */ -+ /* The CPU must not attempt to change the SDRAM Mode register setting */ -+ /* prior to DRAM controller completion of the DRAM initialization */ -+ /* sequence. To guarantee this restriction, it is recommended that */ -+ /* the CPU sets the SDRAM Operation register to NOP command, performs */ -+ /* read polling until the register is back in Normal operation value, */ -+ /* and then sets SDRAM Mode register to its new value. */ -+ -+ /* 8.1 write 'nop' to SDRAM operation */ -+ mov r4, #0x5 /* 'NOP' command */ -+ MV_REG_WRITE_ASM(r4, r1, SDRAM_OPERATION_REG) -+ -+ /* 8.2 poll SDRAM operation. Make sure its back to normal operation */ -+_sdramOpPoll1: -+ ldr r4, [r1] -+ cmp r4, #0 /* '0' = Normal SDRAM Mode */ -+ bne _sdramOpPoll1 -+ -+ /* 8.3 Now its safe to write new value to SDRAM Mode register */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG2) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + SDRAM_MODE_REG) -+ str r4, [r1] -+ -+ /* 8.4 Make the Dunit write the DRAM its new mode */ -+ mov r4, #0x3 /* Mode Register Set command */ -+ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) -+ -+ /* 8.5 poll SDRAM operation. Make sure its back to normal operation */ -+_sdramOpPoll2: -+ ldr r4, [r1] -+ cmp r4, #0 /* '0' = Normal SDRAM Mode */ -+ bne _sdramOpPoll2 -+ -+ /* Now its safe to write new value to SDRAM Extended Mode regist */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG10) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + SDRAM_EXTENDED_MODE_REG) -+ str r4, [r1] -+ -+ /* 9) Write SDRAM Extended mode register This operation should be */ -+ /* done for each memory bank */ -+ /* write 'nop' to SDRAM operation */ -+ mov r4, #0x5 /* 'NOP' command */ -+ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) -+ -+ /* poll SDRAM operation. Make sure its back to normal operation */ -+_sdramOpPoll3: -+ ldr r4, [r1] -+ cmp r4, #0 /* '0' = Normal SDRAM Mode */ -+ bne _sdramOpPoll3 -+ /* Go over each of the Banks */ -+ ldr r3, =0 /* r3 = DRAM bank Num */ -+ -+extModeLoop: -+ /* Set the SDRAM Operation Control to each of the DRAM banks */ -+ mov r4, r3 /* Do not swap the bank counter value */ -+ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_CTRL_REG) -+ -+ /* Make the Dunit write the DRAM its new mode */ -+ mov r4, #0x4 /* Extended Mode Register Set command */ -+ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) -+ -+ /* poll SDRAM operation. Make sure its back to normal operation */ -+_sdramOpPoll4: -+ ldr r4, [r1] -+ cmp r4, #0 /* '0' = Normal SDRAM Mode */ -+ bne _sdramOpPoll4 -+ -+ add r3, r3, #1 -+ cmp r3, #4 /* 4 = Number of banks */ -+ bne extModeLoop -+ -+extModeEnd: -+cmp sp, #0 -+ beq no_stack_l -+ mov r1, LR /* Save link register */ -+#if defined(MV78XX0) -+ bl _mvDramIfMemInit -+#endif -+ mov LR,r1 /* restore link register */ -+load_from_stack: -+ /* Restore registers */ -+ ldmia sp!, {r1, r2, r3, r4} -+no_stack_l: -+ -+ mov pc, lr -+ -+ -+/******************************************************************************* -+* _mvDramIfEccMemInit - Basic DRAM ECC initialization. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+#define XOR_CHAN0 0 /* XOR channel 0 used for memory initialization */ -+#define XOR_UNIT0 0 /* XOR unit 0 used for memory initialization */ -+#define XOR_ADDR_DEC_WIN0 0 /* Enable DRAM access using XOR decode window 0 */ -+/* XOR engine register offsets macros */ -+#define XOR_CONFIG_REG(chan) (XOR_UNIT_BASE(0) + 0x10 + ((chan) * 4)) -+#define XOR_ACTIVATION_REG(chan) (XOR_UNIT_BASE(0) + 0x20 + ((chan) * 4)) -+#define XOR_CAUSE_REG (XOR_UNIT_BASE(0) + 0x30) -+#define XOR_ERROR_CAUSE_REG (XOR_UNIT_BASE(0) + 0x50) -+#define XOR_ERROR_ADDR_REG (XOR_UNIT_BASE(0) + 0x60) -+#define XOR_INIT_VAL_LOW_REG (XOR_UNIT_BASE(0) + 0x2E0) -+#define XOR_INIT_VAL_HIGH_REG (XOR_UNIT_BASE(0) + 0x2E4) -+#define XOR_DST_PTR_REG(chan) (XOR_UNIT_BASE(0) + 0x2B0 + ((chan) * 4)) -+#define XOR_BLOCK_SIZE_REG(chan) (XOR_UNIT_BASE(0) + 0x2C0 + ((chan) * 4)) -+ -+/* XOR Engine Address Decoding Register Map */ -+#define XOR_WINDOW_CTRL_REG(unit,chan) (XOR_UNIT_BASE(unit)+(0x240 + ((chan) * 4))) -+#define XOR_BASE_ADDR_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x250 + ((winNum) * 4))) -+#define XOR_SIZE_MASK_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x270 + ((winNum) * 4))) -+ -+.globl _mvDramIfEccMemInit -+/******************************************************************************* -+* _mvDramIfEccMemInit - mem init for dram cs -+* -+* DESCRIPTION: -+* This function will clean the cs by ussing the XOR mem init. -+* -+* INPUT: -+* r0 - dram bank number. -+* -+* OUTPUT: -+* none -+*/ -+_mvDramIfEccMemInit: -+ -+ /* Save register on stack */ -+ cmp sp, #0 -+ beq no_stack_s1 -+save_on_stack1: -+ stmdb sp!, {r0,r1, r2, r3, r4, r5, r6} -+no_stack_s1: -+ -+ ldr r1, = 0 -+ -+ /* Disable all XOR address decode windows to avoid possible overlap */ -+ MV_REG_WRITE_ASM (r1, r5, (XOR_WINDOW_CTRL_REG(XOR_UNIT0,XOR_CHAN0))) -+ -+ /* Init r5 to first XOR_SIZE_MASK_REG */ -+ mov r5, r0, LSL #3 -+ add r5, r5,#0x1500 -+ add r5, r5,#0x04 -+ add r5, r5,#(INTER_REGS_BASE) -+ ldr r6, [r5] -+ HTOLL(r6,r5) -+ MV_REG_WRITE_ASM (r6, r5, XOR_SIZE_MASK_REG(XOR_UNIT0,XOR_ADDR_DEC_WIN0)) -+ -+ mov r5, r0, LSL #3 -+ add r5, r5,#0x1500 -+ add r5, r5,#(INTER_REGS_BASE) -+ ldr r6, [r5] -+ /* Update destination & size */ -+ MV_REG_WRITE_ASM(r6, r5, XOR_DST_PTR_REG(XOR_CHAN0)) -+ HTOLL(r6,r5) -+ /* Init r6 to first XOR_BASE_ADDR_REG */ -+ ldr r4, = 0xf -+ ldr r5, = 0x1 -+ mov r5, r5, LSL r0 -+ bic r4, r4, r5 -+ mov r4, r4, LSL #8 -+ -+ orr r6, r6, r4 -+ MV_REG_WRITE_ASM (r6, r5, XOR_BASE_ADDR_REG(XOR_UNIT0,XOR_ADDR_DEC_WIN0)) -+ -+ ldr r6, = 0xff0001 -+ MV_REG_WRITE_ASM (r6, r5, XOR_WINDOW_CTRL_REG(XOR_UNIT0,XOR_CHAN0)) -+ -+ /* Configure XOR engine for memory init function. */ -+ MV_REG_READ_ASM (r6, r5, XOR_CONFIG_REG(XOR_CHAN0)) -+ and r6, r6, #~0x7 /* Clear operation mode field */ -+ orr r6, r6, #0x4 /* Set operation to memory init */ -+ MV_REG_WRITE_ASM(r6, r5, XOR_CONFIG_REG(XOR_CHAN0)) -+ -+ /* Set initVal in the XOR Engine Initial Value Registers */ -+ ldr r6, = 0xfeedfeed -+ MV_REG_WRITE_ASM(r6, r5, XOR_INIT_VAL_LOW_REG) -+ ldr r6, = 0xfeedfeed -+ MV_REG_WRITE_ASM(r6, r5, XOR_INIT_VAL_HIGH_REG) -+ -+ /* Set block size using DRAM bank size */ -+ -+ mov r5, r0, LSL #3 -+ add r5, r5,#0x1500 -+ add r5, r5,#0x04 -+ add r5, r5,#(INTER_REGS_BASE) -+ -+ ldr r6, [r5] -+ HTOLL(r6,r5) -+ and r6, r6, #SCSR_SIZE_MASK -+ mov r5, r6, LSR #SCSR_SIZE_OFFS -+ add r5, r5, #1 -+ mov r6, r5, LSL #SCSR_SIZE_OFFS -+ MV_REG_WRITE_ASM(r6, r5, XOR_BLOCK_SIZE_REG(XOR_CHAN0)) -+ -+ /* Clean interrupt cause*/ -+ MV_REG_WRITE_ASM(r1, r5, XOR_CAUSE_REG) -+ -+ /* Clean error interrupt cause*/ -+ MV_REG_READ_ASM(r6, r5, XOR_ERROR_CAUSE_REG) -+ MV_REG_READ_ASM(r6, r5, XOR_ERROR_ADDR_REG) -+ -+ /* Start transfer */ -+ MV_REG_READ_ASM (r6, r5, XOR_ACTIVATION_REG(XOR_CHAN0)) -+ orr r6, r6, #0x1 /* Preform start command */ -+ MV_REG_WRITE_ASM(r6, r5, XOR_ACTIVATION_REG(XOR_CHAN0)) -+ -+ /* Wait for engine to finish */ -+waitForComplete: -+ MV_REG_READ_ASM(r6, r5, XOR_CAUSE_REG) -+ and r6, r6, #2 -+ cmp r6, #0 -+ beq waitForComplete -+ -+ /* Clear all error report registers */ -+ MV_REG_WRITE_ASM(r1, r5, SDRAM_SINGLE_BIT_ERR_CNTR_REG) -+ MV_REG_WRITE_ASM(r1, r5, SDRAM_DOUBLE_BIT_ERR_CNTR_REG) -+ -+ MV_REG_WRITE_ASM(r1, r5, SDRAM_ERROR_CAUSE_REG) -+ -+ cmp sp, #0 -+ beq no_stack_l1 -+load_from_stack1: -+ ldmia sp!, {r0, r1, r2, r3, r4, r5, r6} -+no_stack_l1: -+ mov pc, lr -+ -+ -+/******************************************************************************* -+* mvDramIfMemInit - Use XOR to clear all memory. -+* -+* DESCRIPTION: -+* Use assembler function _mvDramIfEccMemInit to fill all memory with FEADFEAD pattern. -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+#if defined(MV78XX0) -+ -+_mvDramIfMemInit: -+ stmdb sp!, {r0,r1, r2, r3, r4, r5, r6} -+ mov r6, LR /* Save link register */ -+ /* Check if dram bank 0 has to be init for ECC */ -+ MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,0)) -+ and r3, r0, #SCSR_WIN_EN -+ cmp r3, #0 -+ beq no_bank_0 -+ MV_REG_READ_ASM(r0, r5, SDRAM_BASE_ADDR_REG(0,0)) -+ cmp r0, #0 -+ beq no_bank_0 -+ mov r0,#0 -+ bl _mvDramIfEccMemInit -+ -+no_bank_0: -+ /* Check if dram bank 1 has to be init for ECC */ -+ MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,1)) -+ and r0, r0, #SCSR_WIN_EN -+ cmp r0, #0 -+ beq no_bank_1 -+ mov r0,#1 -+ bl _mvDramIfEccMemInit -+no_bank_1: -+ /* Check if dram bank 2 has to be init for ECC */ -+ MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,2)) -+ and r0, r0, #SCSR_WIN_EN -+ cmp r0, #0 -+ beq no_bank_2 -+ MV_REG_READ_ASM(r0, r5, SDRAM_BASE_ADDR_REG(0,2)) -+ cmp r0, #0 -+ beq no_bank_2 -+ mov r0,#2 -+ bl _mvDramIfEccMemInit -+ -+no_bank_2: -+ /* Check if dram bank 3 has to be init for ECC */ -+ MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,3)) -+ and r0, r0, #SCSR_WIN_EN -+ cmp r0, #0 -+ beq no_bank_3 -+ mov r0,#3 -+ bl _mvDramIfEccMemInit -+no_bank_3: -+ mov LR ,r6 /* restore link register */ -+ ldmia sp!, {r0, r1, r2, r3, r4, r5, r6} -+ mov pc, lr -+#endif -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,157 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvDramIfConfigh -+#define __INCmvDramIfConfigh -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* includes */ -+ -+/* defines */ -+ -+/* registers defaults values */ -+ -+#define SDRAM_CONFIG_DV (SDRAM_SRMODE_DRAM | BIT25 | BIT30) -+ -+#define SDRAM_DUNIT_CTRL_LOW_DDR2_DV \ -+ (SDRAM_SRCLK_KEPT | \ -+ SDRAM_CLK1DRV_NORMAL | \ -+ (BIT28 | BIT29)) -+ -+#define SDRAM_ADDR_CTRL_DV 2 -+ -+#define SDRAM_TIMING_CTRL_LOW_REG_DV \ -+ ((0x2 << SDRAM_TRCD_OFFS) | \ -+ (0x2 << SDRAM_TRP_OFFS) | \ -+ (0x1 << SDRAM_TWR_OFFS) | \ -+ (0x0 << SDRAM_TWTR_OFFS) | \ -+ (0x5 << SDRAM_TRAS_OFFS) | \ -+ (0x1 << SDRAM_TRRD_OFFS)) -+ -+/* Note: value of 0 in register means one cycle, 1 means two and so on */ -+#define SDRAM_TIMING_CTRL_HIGH_REG_DV \ -+ ((0x0 << SDRAM_TR2R_OFFS) | \ -+ (0x0 << SDRAM_TR2W_W2R_OFFS) | \ -+ (0x1 << SDRAM_TW2W_OFFS)) -+ -+#define SDRAM_OPEN_PAGES_CTRL_REG_DV SDRAM_OPEN_PAGE_EN -+ -+/* Presence Ctrl Low Ctrl High Dunit Ctrl Ext Mode */ -+/* CS0 0x84210000 0x00000000 0x0000780F 0x00000440 */ -+/* CS0+CS1 0x84210000 0x00000000 0x0000780F 0x00000440 */ -+/* CS0+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -+/* CS0+CS1+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -+/* CS0+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -+/* CS0+CS1+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -+ -+#define DDR2_ODT_CTRL_LOW_CS0_CS1_DV 0x84210000 -+#define DDR2_ODT_CTRL_HIGH_CS0_CS1_DV 0x00000000 -+#define DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV 0x0000E80F -+#ifdef MV78XX0 -+#define DDR_SDRAM_EXT_MODE_CS0_CS1_DV 0x00000040 -+#else -+#define DDR_SDRAM_EXT_MODE_CS0_CS1_DV 0x00000440 -+#endif -+ -+#define DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV 0x030C030C -+#define DDR2_ODT_CTRL_HIGH_CS0_CS1_CS2_CS3_DV 0x00000000 -+#define DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV 0x0000F40F -+#ifdef MV78XX0 -+#define DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV 0x00000004 -+#define DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV 0x00000044 -+#else -+#define DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV 0x00000404 -+#define DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV 0x00000444 -+#endif -+ -+/* DDR SDRAM Adderss/Control and Data Pads Calibration default values */ -+#define DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \ -+ (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) -+ -+#define DDR2_DATA_PAD_STRENGTH_TYPICAL_DV \ -+ (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) -+ -+/* DDR SDRAM Mode Register default value */ -+#define DDR2_MODE_REG_DV (SDRAM_BURST_LEN_4 | SDRAM_WR_3_CYC) -+/* DDR SDRAM Timing parameter default values */ -+#define SDRAM_TIMING_CTRL_LOW_REG_DEFAULT 0x33136552 -+#define SDRAM_TRFC_DEFAULT_VALUE 0x34 -+#define SDRAM_TRFC_DEFAULT SDRAM_TRFC_DEFAULT_VALUE -+#define SDRAM_TW2W_DEFALT (0x1 << SDRAM_TW2W_OFFS) -+ -+#define SDRAM_TIMING_CTRL_HIGH_REG_DEFAULT (SDRAM_TRFC_DEFAULT | SDRAM_TW2W_DEFALT) -+ -+#define SDRAM_FTDLL_REG_DEFAULT_LEFT 0x88C800 -+#define SDRAM_FTDLL_REG_DEFAULT_RIGHT 0x88C800 -+#define SDRAM_FTDLL_REG_DEFAULT_UP 0x88C800 -+ -+#ifdef __cplusplus -+} -+#endif /* __cplusplus */ -+ -+#endif /* __INCmvDramIfh */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,423 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvDramIfRegsh -+#define __INCmvDramIfRegsh -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* DDR SDRAM Controller Address Decode Registers */ -+ /* SDRAM CSn Base Address Register (SCBAR) */ -+#define SDRAM_BASE_ADDR_REG(cpu,csNum) (0x1500 + ((csNum) * 8) + ((cpu) * 0x70)) -+#define SCBAR_BASE_OFFS 16 -+#define SCBAR_BASE_MASK (0xffff << SCBAR_BASE_OFFS) -+#define SCBAR_BASE_ALIGNMENT 0x10000 -+ -+/* SDRAM CSn Size Register (SCSR) */ -+#define SDRAM_SIZE_REG(cpu,csNum) (0x1504 + ((csNum) * 8) + ((cpu) * 0x70)) -+#define SCSR_SIZE_OFFS 24 -+#define SCSR_SIZE_MASK (0xff << SCSR_SIZE_OFFS) -+#define SCSR_SIZE_ALIGNMENT 0x1000000 -+#define SCSR_WIN_EN BIT0 -+ -+/* configuration register */ -+#define SDRAM_CONFIG_REG (DRAM_BASE + 0x1400) -+#define SDRAM_REFRESH_OFFS 0 -+#define SDRAM_REFRESH_MAX 0x3FFF -+#define SDRAM_REFRESH_MASK (SDRAM_REFRESH_MAX << SDRAM_REFRESH_OFFS) -+#define SDRAM_DWIDTH_OFFS 15 -+#define SDRAM_DWIDTH_MASK (1 << SDRAM_DWIDTH_OFFS) -+#define SDRAM_DWIDTH_32BIT (0 << SDRAM_DWIDTH_OFFS) -+#define SDRAM_DWIDTH_64BIT (1 << SDRAM_DWIDTH_OFFS) -+#define SDRAM_REGISTERED (1 << 17) -+#define SDRAM_ECC_OFFS 18 -+#define SDRAM_ECC_MASK (1 << SDRAM_ECC_OFFS) -+#define SDRAM_ECC_DIS (0 << SDRAM_ECC_OFFS) -+#define SDRAM_ECC_EN (1 << SDRAM_ECC_OFFS) -+#define SDRAM_IERR_OFFS 19 -+#define SDRAM_IERR_MASK (1 << SDRAM_IERR_OFFS) -+#define SDRAM_IERR_REPORTE (0 << SDRAM_IERR_OFFS) -+#define SDRAM_IERR_IGNORE (1 << SDRAM_IERR_OFFS) -+#define SDRAM_SRMODE_OFFS 24 -+#define SDRAM_SRMODE_MASK (1 << SDRAM_SRMODE_OFFS) -+#define SDRAM_SRMODE_POWER (0 << SDRAM_SRMODE_OFFS) -+#define SDRAM_SRMODE_DRAM (1 << SDRAM_SRMODE_OFFS) -+ -+/* dunit control low register */ -+#define SDRAM_DUNIT_CTRL_REG (DRAM_BASE + 0x1404) -+#define SDRAM_2T_OFFS 4 -+#define SDRAM_2T_MASK (1 << SDRAM_2T_OFFS) -+#define SDRAM_2T_MODE (1 << SDRAM_2T_OFFS) -+ -+#define SDRAM_SRCLK_OFFS 5 -+#define SDRAM_SRCLK_MASK (1 << SDRAM_SRCLK_OFFS) -+#define SDRAM_SRCLK_KEPT (0 << SDRAM_SRCLK_OFFS) -+#define SDRAM_SRCLK_GATED (1 << SDRAM_SRCLK_OFFS) -+#define SDRAM_CTRL_POS_OFFS 6 -+#define SDRAM_CTRL_POS_MASK (1 << SDRAM_CTRL_POS_OFFS) -+#define SDRAM_CTRL_POS_FALL (0 << SDRAM_CTRL_POS_OFFS) -+#define SDRAM_CTRL_POS_RISE (1 << SDRAM_CTRL_POS_OFFS) -+#define SDRAM_CLK1DRV_OFFS 12 -+#define SDRAM_CLK1DRV_MASK (1 << SDRAM_CLK1DRV_OFFS) -+#define SDRAM_CLK1DRV_HIGH_Z (0 << SDRAM_CLK1DRV_OFFS) -+#define SDRAM_CLK1DRV_NORMAL (1 << SDRAM_CLK1DRV_OFFS) -+#define SDRAM_CLK2DRV_OFFS 13 -+#define SDRAM_CLK2DRV_MASK (1 << SDRAM_CLK2DRV_OFFS) -+#define SDRAM_CLK2DRV_HIGH_Z (0 << SDRAM_CLK2DRV_OFFS) -+#define SDRAM_CLK2DRV_NORMAL (1 << SDRAM_CLK2DRV_OFFS) -+#define SDRAM_SB_OUT_DEL_OFFS 20 -+#define SDRAM_SB_OUT_DEL_MAX 0xf -+#define SDRAM_SB_OUT_MASK (SDRAM_SB_OUT_DEL_MAX<= MV_DRAM_MAX_CS )) -+ { -+ DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); -+ return MV_BAD_PARAM; -+ } -+ memset(pBankInfo, 0, sizeof(*pBankInfo)); -+ -+ if ( MV_OK != dimmSpdGet((MV_U32)(bankNum/2), &dimmInfo)) -+ { -+ DB(mvOsPrintf("Dram: ERR dimmSpdGet failed to get dimm info \n")); -+ return MV_FAIL; -+ } -+ if ((dimmInfo.numOfModuleBanks == 1) && ((bankNum % 2) == 1)) -+ { -+ DB(mvOsPrintf("Dram: ERR dimmSpdGet. Can't find DIMM bank 2 \n")); -+ return MV_FAIL; -+ } -+ /* convert Dimm info to Bank info */ -+ cpyDimm2BankInfo(&dimmInfo, pBankInfo); -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* cpyDimm2BankInfo - Convert a Dimm info struct into a bank info struct. -+* -+* DESCRIPTION: -+* Convert a Dimm info struct into a bank info struct. -+* -+* INPUT: -+* pDimmInfo - DIMM information structure. -+* -+* OUTPUT: -+* pBankInfo - DRAM bank information struct. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+static MV_VOID cpyDimm2BankInfo(MV_DIMM_INFO *pDimmInfo, -+ MV_DRAM_BANK_INFO *pBankInfo) -+{ -+ pBankInfo->memoryType = pDimmInfo->memoryType; -+ -+ /* DIMM dimensions */ -+ pBankInfo->numOfRowAddr = pDimmInfo->numOfRowAddr; -+ pBankInfo->numOfColAddr = pDimmInfo->numOfColAddr; -+ pBankInfo->dataWidth = pDimmInfo->dataWidth; -+ pBankInfo->errorCheckType = pDimmInfo->errorCheckType; -+ pBankInfo->sdramWidth = pDimmInfo->sdramWidth; -+ pBankInfo->errorCheckDataWidth = pDimmInfo->errorCheckDataWidth; -+ pBankInfo->numOfBanksOnEachDevice = pDimmInfo->numOfBanksOnEachDevice; -+ pBankInfo->suportedCasLatencies = pDimmInfo->suportedCasLatencies; -+ pBankInfo->refreshInterval = pDimmInfo->refreshInterval; -+ -+ /* DIMM timing parameters */ -+ pBankInfo->minCycleTimeAtMaxCasLatPs = pDimmInfo->minCycleTimeAtMaxCasLatPs; -+ pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps = -+ pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps; -+ pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps = -+ pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps; -+ -+ pBankInfo->minRowPrechargeTime = pDimmInfo->minRowPrechargeTime; -+ pBankInfo->minRowActiveToRowActive = pDimmInfo->minRowActiveToRowActive; -+ pBankInfo->minRasToCasDelay = pDimmInfo->minRasToCasDelay; -+ pBankInfo->minRasPulseWidth = pDimmInfo->minRasPulseWidth; -+ pBankInfo->minWriteRecoveryTime = pDimmInfo->minWriteRecoveryTime; -+ pBankInfo->minWriteToReadCmdDelay = pDimmInfo->minWriteToReadCmdDelay; -+ pBankInfo->minReadToPrechCmdDelay = pDimmInfo->minReadToPrechCmdDelay; -+ pBankInfo->minRefreshToActiveCmd = pDimmInfo->minRefreshToActiveCmd; -+ -+ /* Parameters calculated from the extracted DIMM information */ -+ pBankInfo->size = pDimmInfo->size/pDimmInfo->numOfModuleBanks; -+ pBankInfo->deviceDensity = pDimmInfo->deviceDensity; -+ pBankInfo->numberOfDevices = pDimmInfo->numberOfDevices / -+ pDimmInfo->numOfModuleBanks; -+ -+ /* DIMM attributes (MV_TRUE for yes) */ -+ -+ if ((pDimmInfo->memoryType == MEM_TYPE_SDRAM) || -+ (pDimmInfo->memoryType == MEM_TYPE_DDR1) ) -+ { -+ if (pDimmInfo->dimmAttributes & BIT1) -+ pBankInfo->registeredAddrAndControlInputs = MV_TRUE; -+ else -+ pBankInfo->registeredAddrAndControlInputs = MV_FALSE; -+ } -+ else /* pDimmInfo->memoryType == MEM_TYPE_DDR2 */ -+ { -+ if (pDimmInfo->dimmTypeInfo & (BIT0 | BIT4)) -+ pBankInfo->registeredAddrAndControlInputs = MV_TRUE; -+ else -+ pBankInfo->registeredAddrAndControlInputs = MV_FALSE; -+ } -+ -+ return; -+} -+/******************************************************************************* -+* dimmSpdCpy - Cpy SPD parameters from dimm 0 to dimm 1. -+* -+* DESCRIPTION: -+* Read the DIMM SPD parameters from dimm 0 into dimm 1 SPD. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+MV_STATUS dimmSpdCpy(MV_VOID) -+{ -+ MV_U32 i; -+ MV_U32 spdChecksum; -+ -+ MV_TWSI_SLAVE twsiSlave; -+ MV_U8 data[SPD_SIZE]; -+ -+ /* zero dimmInfo structure */ -+ memset(data, 0, SPD_SIZE); -+ -+ /* read the dimm eeprom */ -+ DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); -+ twsiSlave.slaveAddr.address = MV_BOARD_DIMM0_I2C_ADDR; -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ twsiSlave.offset = 0; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, &twsiSlave, data, SPD_SIZE) ) -+ { -+ DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 0\n")); -+ return MV_FAIL; -+ } -+ DB(puts("DRAM: Reading dimm info succeded.\n")); -+ -+ /* calculate SPD checksum */ -+ spdChecksum = 0; -+ -+ for(i = 0 ; i <= 62 ; i++) -+ { -+ spdChecksum += data[i]; -+ } -+ -+ if ((spdChecksum & 0xff) != data[63]) -+ { -+ DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", -+ (MV_U32)(spdChecksum & 0xff), data[63])); -+ } -+ else -+ { -+ DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); -+ } -+ -+ /* copy the SPD content 1:1 into the DIMM 1 SPD */ -+ twsiSlave.slaveAddr.address = MV_BOARD_DIMM1_I2C_ADDR; -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ twsiSlave.offset = 0; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ for(i = 0 ; i < SPD_SIZE ; i++) -+ { -+ twsiSlave.offset = i; -+ if( MV_OK != mvTwsiWrite (MV_BOARD_DIMM_I2C_CHANNEL, &twsiSlave, &data[i], 1) ) -+ { -+ mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 1 byte %d \n",i); -+ return MV_FAIL; -+ } -+ mvOsDelay(5); -+ } -+ -+ DB(puts("DRAM: Reading dimm info succeded.\n")); -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* dimmSpdGet - Get the SPD parameters. -+* -+* DESCRIPTION: -+* Read the DIMM SPD parameters into given struct parameter. -+* -+* INPUT: -+* dimmNum - DIMM number. See MV_BOARD_DIMM_NUM enumerator. -+* -+* OUTPUT: -+* pDimmInfo - DIMM information structure. -+* -+* RETURN: -+* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo) -+{ -+ MV_U32 i; -+ MV_U32 density = 1; -+ MV_U32 spdChecksum; -+ -+ MV_TWSI_SLAVE twsiSlave; -+ MV_U8 data[SPD_SIZE]; -+ -+ if((NULL == pDimmInfo)|| (dimmNum >= MAX_DIMM_NUM)) -+ { -+ DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); -+ return MV_BAD_PARAM; -+ } -+ -+ /* zero dimmInfo structure */ -+ memset(data, 0, SPD_SIZE); -+ -+ /* read the dimm eeprom */ -+ DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); -+ twsiSlave.slaveAddr.address = (dimmNum == 0) ? -+ MV_BOARD_DIMM0_I2C_ADDR : MV_BOARD_DIMM1_I2C_ADDR; -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ twsiSlave.offset = 0; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, &twsiSlave, data, SPD_SIZE) ) -+ { -+ DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum %d \n", dimmNum)); -+ return MV_FAIL; -+ } -+ DB(puts("DRAM: Reading dimm info succeded.\n")); -+ -+ /* calculate SPD checksum */ -+ spdChecksum = 0; -+ -+ for(i = 0 ; i <= 62 ; i++) -+ { -+ spdChecksum += data[i]; -+ } -+ -+ if ((spdChecksum & 0xff) != data[63]) -+ { -+ DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", -+ (MV_U32)(spdChecksum & 0xff), data[63])); -+ } -+ else -+ { -+ DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); -+ } -+ -+ /* copy the SPD content 1:1 into the dimmInfo structure*/ -+ for(i = 0 ; i < SPD_SIZE ; i++) -+ { -+ pDimmInfo->spdRawData[i] = data[i]; -+ DB(mvOsPrintf("SPD-EEPROM Byte %3d = %3x (%3d)\n",i, data[i], data[i])); -+ } -+ -+ DB(mvOsPrintf("DRAM SPD Information:\n")); -+ -+ /* Memory type (DDR / SDRAM) */ -+ switch (data[DIMM_MEM_TYPE]) -+ { -+ case (DIMM_MEM_TYPE_SDRAM): -+ pDimmInfo->memoryType = MEM_TYPE_SDRAM; -+ DB(mvOsPrintf("DRAM Memeory type SDRAM\n")); -+ break; -+ case (DIMM_MEM_TYPE_DDR1): -+ pDimmInfo->memoryType = MEM_TYPE_DDR1; -+ DB(mvOsPrintf("DRAM Memeory type DDR1\n")); -+ break; -+ case (DIMM_MEM_TYPE_DDR2): -+ pDimmInfo->memoryType = MEM_TYPE_DDR2; -+ DB(mvOsPrintf("DRAM Memeory type DDR2\n")); -+ break; -+ default: -+ mvOsPrintf("ERROR: Undefined memory type!\n"); -+ return MV_ERROR; -+ } -+ -+ -+ /* Number Of Row Addresses */ -+ pDimmInfo->numOfRowAddr = data[DIMM_ROW_NUM]; -+ DB(mvOsPrintf("DRAM numOfRowAddr[3] %d\n",pDimmInfo->numOfRowAddr)); -+ -+ /* Number Of Column Addresses */ -+ pDimmInfo->numOfColAddr = data[DIMM_COL_NUM]; -+ DB(mvOsPrintf("DRAM numOfColAddr[4] %d\n",pDimmInfo->numOfColAddr)); -+ -+ /* Number Of Module Banks */ -+ pDimmInfo->numOfModuleBanks = data[DIMM_MODULE_BANK_NUM]; -+ DB(mvOsPrintf("DRAM numOfModuleBanks[5] 0x%x\n", -+ pDimmInfo->numOfModuleBanks)); -+ -+ /* Number of module banks encoded differently for DDR2 */ -+ if (pDimmInfo->memoryType == MEM_TYPE_DDR2) -+ pDimmInfo->numOfModuleBanks = (pDimmInfo->numOfModuleBanks & 0x7)+1; -+ -+ /* Data Width */ -+ pDimmInfo->dataWidth = data[DIMM_DATA_WIDTH]; -+ DB(mvOsPrintf("DRAM dataWidth[6] 0x%x\n", pDimmInfo->dataWidth)); -+ -+ /* Minimum Cycle Time At Max CasLatancy */ -+ pDimmInfo->minCycleTimeAtMaxCasLatPs = cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS]); -+ -+ /* Error Check Type */ -+ pDimmInfo->errorCheckType = data[DIMM_ERR_CHECK_TYPE]; -+ DB(mvOsPrintf("DRAM errorCheckType[11] 0x%x\n", -+ pDimmInfo->errorCheckType)); -+ -+ /* Refresh Interval */ -+ pDimmInfo->refreshInterval = data[DIMM_REFRESH_INTERVAL]; -+ DB(mvOsPrintf("DRAM refreshInterval[12] 0x%x\n", -+ pDimmInfo->refreshInterval)); -+ -+ /* Sdram Width */ -+ pDimmInfo->sdramWidth = data[DIMM_SDRAM_WIDTH]; -+ DB(mvOsPrintf("DRAM sdramWidth[13] 0x%x\n",pDimmInfo->sdramWidth)); -+ -+ /* Error Check Data Width */ -+ pDimmInfo->errorCheckDataWidth = data[DIMM_ERR_CHECK_DATA_WIDTH]; -+ DB(mvOsPrintf("DRAM errorCheckDataWidth[14] 0x%x\n", -+ pDimmInfo->errorCheckDataWidth)); -+ -+ /* Burst Length Supported */ -+ /* SDRAM/DDR1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * -+ *********************************************************/ -+ /* DDR2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * -+ *********************************************************/ -+ -+ pDimmInfo->burstLengthSupported = data[DIMM_BURST_LEN_SUP]; -+ DB(mvOsPrintf("DRAM burstLengthSupported[16] 0x%x\n", -+ pDimmInfo->burstLengthSupported)); -+ -+ /* Number Of Banks On Each Device */ -+ pDimmInfo->numOfBanksOnEachDevice = data[DIMM_DEV_BANK_NUM]; -+ DB(mvOsPrintf("DRAM numOfBanksOnEachDevice[17] 0x%x\n", -+ pDimmInfo->numOfBanksOnEachDevice)); -+ -+ /* Suported Cas Latencies */ -+ -+ /* SDRAM: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * -+ ********************************************************/ -+ -+ /* DDR 1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * -+ *********************************************************/ -+ -+ /* DDR 2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * -+ *********************************************************/ -+ -+ pDimmInfo->suportedCasLatencies = data[DIMM_SUP_CAL]; -+ DB(mvOsPrintf("DRAM suportedCasLatencies[18] 0x%x\n", -+ pDimmInfo->suportedCasLatencies)); -+ -+ /* For DDR2 only, get the DIMM type information */ -+ if (pDimmInfo->memoryType == MEM_TYPE_DDR2) -+ { -+ pDimmInfo->dimmTypeInfo = data[DIMM_DDR2_TYPE_INFORMATION]; -+ DB(mvOsPrintf("DRAM dimmTypeInfo[20] (DDR2) 0x%x\n", -+ pDimmInfo->dimmTypeInfo)); -+ } -+ -+ /* SDRAM Modules Attributes */ -+ pDimmInfo->dimmAttributes = data[DIMM_BUF_ADDR_CONT_IN]; -+ DB(mvOsPrintf("DRAM dimmAttributes[21] 0x%x\n", -+ pDimmInfo->dimmAttributes)); -+ -+ /* Minimum Cycle Time At Max CasLatancy Minus 1*/ -+ pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps = -+ cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS1]); -+ -+ /* Minimum Cycle Time At Max CasLatancy Minus 2*/ -+ pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps = -+ cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS2]); -+ -+ pDimmInfo->minRowPrechargeTime = data[DIMM_MIN_ROW_PRECHARGE_TIME]; -+ DB(mvOsPrintf("DRAM minRowPrechargeTime[27] 0x%x\n", -+ pDimmInfo->minRowPrechargeTime)); -+ pDimmInfo->minRowActiveToRowActive = data[DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE]; -+ DB(mvOsPrintf("DRAM minRowActiveToRowActive[28] 0x%x\n", -+ pDimmInfo->minRowActiveToRowActive)); -+ pDimmInfo->minRasToCasDelay = data[DIMM_MIN_RAS_TO_CAS_DELAY]; -+ DB(mvOsPrintf("DRAM minRasToCasDelay[29] 0x%x\n", -+ pDimmInfo->minRasToCasDelay)); -+ pDimmInfo->minRasPulseWidth = data[DIMM_MIN_RAS_PULSE_WIDTH]; -+ DB(mvOsPrintf("DRAM minRasPulseWidth[30] 0x%x\n", -+ pDimmInfo->minRasPulseWidth)); -+ -+ /* DIMM Bank Density */ -+ pDimmInfo->dimmBankDensity = data[DIMM_BANK_DENSITY]; -+ DB(mvOsPrintf("DRAM dimmBankDensity[31] 0x%x\n", -+ pDimmInfo->dimmBankDensity)); -+ -+ /* Only DDR2 includes Write Recovery Time field. Other SDRAM ignore */ -+ pDimmInfo->minWriteRecoveryTime = data[DIMM_MIN_WRITE_RECOVERY_TIME]; -+ DB(mvOsPrintf("DRAM minWriteRecoveryTime[36] 0x%x\n", -+ pDimmInfo->minWriteRecoveryTime)); -+ -+ /* Only DDR2 includes Internal Write To Read Command Delay field. */ -+ pDimmInfo->minWriteToReadCmdDelay = data[DIMM_MIN_WRITE_TO_READ_CMD_DELAY]; -+ DB(mvOsPrintf("DRAM minWriteToReadCmdDelay[37] 0x%x\n", -+ pDimmInfo->minWriteToReadCmdDelay)); -+ -+ /* Only DDR2 includes Internal Read To Precharge Command Delay field. */ -+ pDimmInfo->minReadToPrechCmdDelay = data[DIMM_MIN_READ_TO_PRECH_CMD_DELAY]; -+ DB(mvOsPrintf("DRAM minReadToPrechCmdDelay[38] 0x%x\n", -+ pDimmInfo->minReadToPrechCmdDelay)); -+ -+ /* Only DDR2 includes Minimum Refresh to Activate/Refresh Command field */ -+ pDimmInfo->minRefreshToActiveCmd = data[DIMM_MIN_REFRESH_TO_ACTIVATE_CMD]; -+ DB(mvOsPrintf("DRAM minRefreshToActiveCmd[42] 0x%x\n", -+ pDimmInfo->minRefreshToActiveCmd)); -+ -+ /* calculating the sdram density. Representing device density from */ -+ /* bit 20 to allow representation of 4GB and above. */ -+ /* For example, if density is 512Mbit 0x20000000, will be represent in */ -+ /* deviceDensity by 0x20000000 >> 16 --> 0x00000200. Another example */ -+ /* is density 8GB 0x200000000 >> 16 --> 0x00002000. */ -+ density = (1 << ((pDimmInfo->numOfRowAddr + pDimmInfo->numOfColAddr) - 20)); -+ pDimmInfo->deviceDensity = density * -+ pDimmInfo->numOfBanksOnEachDevice * -+ pDimmInfo->sdramWidth; -+ DB(mvOsPrintf("DRAM deviceDensity %d\n",pDimmInfo->deviceDensity)); -+ -+ /* Number of devices includeing Error correction */ -+ pDimmInfo->numberOfDevices = (pDimmInfo->dataWidth/pDimmInfo->sdramWidth) * -+ pDimmInfo->numOfModuleBanks; -+ DB(mvOsPrintf("DRAM numberOfDevices %d\n", -+ pDimmInfo->numberOfDevices)); -+ -+ pDimmInfo->size = 0; -+ -+ /* Note that pDimmInfo->size is in MB units */ -+ if (pDimmInfo->memoryType == MEM_TYPE_SDRAM) -+ { -+ if (pDimmInfo->dimmBankDensity & BIT0) -+ pDimmInfo->size += 1024; /* Equal to 1GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT1) -+ pDimmInfo->size += 8; /* Equal to 8MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT2) -+ pDimmInfo->size += 16; /* Equal to 16MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT3) -+ pDimmInfo->size += 32; /* Equal to 32MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT4) -+ pDimmInfo->size += 64; /* Equal to 64MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT5) -+ pDimmInfo->size += 128; /* Equal to 128MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT6) -+ pDimmInfo->size += 256; /* Equal to 256MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT7) -+ pDimmInfo->size += 512; /* Equal to 512MB */ -+ } -+ else if (pDimmInfo->memoryType == MEM_TYPE_DDR1) -+ { -+ if (pDimmInfo->dimmBankDensity & BIT0) -+ pDimmInfo->size += 1024; /* Equal to 1GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT1) -+ pDimmInfo->size += 2048; /* Equal to 2GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT2) -+ pDimmInfo->size += 16; /* Equal to 16MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT3) -+ pDimmInfo->size += 32; /* Equal to 32MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT4) -+ pDimmInfo->size += 64; /* Equal to 64MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT5) -+ pDimmInfo->size += 128; /* Equal to 128MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT6) -+ pDimmInfo->size += 256; /* Equal to 256MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT7) -+ pDimmInfo->size += 512; /* Equal to 512MB */ -+ } -+ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ -+ { -+ if (pDimmInfo->dimmBankDensity & BIT0) -+ pDimmInfo->size += 1024; /* Equal to 1GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT1) -+ pDimmInfo->size += 2048; /* Equal to 2GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT2) -+ pDimmInfo->size += 4096; /* Equal to 4GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT3) -+ pDimmInfo->size += 8192; /* Equal to 8GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT4) -+ pDimmInfo->size += 16384; /* Equal to 16GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT5) -+ pDimmInfo->size += 128; /* Equal to 128MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT6) -+ pDimmInfo->size += 256; /* Equal to 256MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT7) -+ pDimmInfo->size += 512; /* Equal to 512MB */ -+ } -+ -+ pDimmInfo->size *= pDimmInfo->numOfModuleBanks; -+ -+ DB(mvOsPrintf("Dram: dimm size %dMB \n",pDimmInfo->size)); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* dimmSpdPrint - Print the SPD parameters. -+* -+* DESCRIPTION: -+* Print the Dimm SPD parameters. -+* -+* INPUT: -+* pDimmInfo - DIMM information structure. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID dimmSpdPrint(MV_U32 dimmNum) -+{ -+ MV_DIMM_INFO dimmInfo; -+ MV_U32 i, temp = 0; -+ MV_U32 k, maskLeftOfPoint = 0, maskRightOfPoint = 0; -+ MV_U32 rightOfPoint = 0,leftOfPoint = 0, div, time_tmp, shift; -+ MV_U32 busClkPs; -+ MV_U8 trp_clocks=0, trcd_clocks, tras_clocks, trrd_clocks, -+ temp_buf[40], *spdRawData; -+ -+ busClkPs = 1000000000 / (mvBoardSysClkGet() / 100); /* in 10 ps units */ -+ -+ spdRawData = dimmInfo.spdRawData; -+ -+ if(MV_OK != dimmSpdGet(dimmNum, &dimmInfo)) -+ { -+ mvOsOutput("ERROR: Could not read SPD information!\n"); -+ return; -+ } -+ -+ /* find Manufactura of Dimm Module */ -+ mvOsOutput("\nManufacturer's JEDEC ID Code: "); -+ for(i = 0 ; i < DIMM_MODULE_MANU_SIZE ; i++) -+ { -+ mvOsOutput("%x",spdRawData[DIMM_MODULE_MANU_OFFS + i]); -+ } -+ mvOsOutput("\n"); -+ -+ /* Manufacturer's Specific Data */ -+ for(i = 0 ; i < DIMM_MODULE_ID_SIZE ; i++) -+ { -+ temp_buf[i] = spdRawData[DIMM_MODULE_ID_OFFS + i]; -+ } -+ mvOsOutput("Manufacturer's Specific Data: %s\n", temp_buf); -+ -+ /* Module Part Number */ -+ for(i = 0 ; i < DIMM_MODULE_VEN_SIZE ; i++) -+ { -+ temp_buf[i] = spdRawData[DIMM_MODULE_VEN_OFFS + i]; -+ } -+ mvOsOutput("Module Part Number: %s\n", temp_buf); -+ -+ /* Module Serial Number */ -+ for(i = 0; i < sizeof(MV_U32); i++) -+ { -+ temp |= spdRawData[95+i] << 8*i; -+ } -+ mvOsOutput("DIMM Serial No. %ld (%lx)\n", (long)temp, -+ (long)temp); -+ -+ /* find Manufac-Data of Dimm Module */ -+ mvOsOutput("Manufactoring Date: Year 20%d%d/ ww %d%d\n", -+ ((spdRawData[93] & 0xf0) >> 4), (spdRawData[93] & 0xf), -+ ((spdRawData[94] & 0xf0) >> 4), (spdRawData[94] & 0xf)); -+ /* find modul_revision of Dimm Module */ -+ mvOsOutput("Module Revision: %d.%d\n", -+ spdRawData[62]/10, spdRawData[62]%10); -+ -+ /* find manufac_place of Dimm Module */ -+ mvOsOutput("manufac_place: %d\n", spdRawData[72]); -+ -+ /* go over the first 35 I2C data bytes */ -+ for(i = 2 ; i <= 35 ; i++) -+ switch(i) -+ { -+ case 2: /* Memory type (DDR1/2 / SDRAM) */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ mvOsOutput("Dram Type is: SDRAM\n"); -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ mvOsOutput("Dram Type is: SDRAM DDR1\n"); -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) -+ mvOsOutput("Dram Type is: SDRAM DDR2\n"); -+ else -+ mvOsOutput("Dram Type unknown\n"); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 3: /* Number Of Row Addresses */ -+ mvOsOutput("Module Number of row addresses: %d\n", -+ dimmInfo.numOfRowAddr); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 4: /* Number Of Column Addresses */ -+ mvOsOutput("Module Number of col addresses: %d\n", -+ dimmInfo.numOfColAddr); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 5: /* Number Of Module Banks */ -+ mvOsOutput("Number of Banks on Mod.: %d\n", -+ dimmInfo.numOfModuleBanks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 6: /* Data Width */ -+ mvOsOutput("Module Data Width: %d bit\n", -+ dimmInfo.dataWidth); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 8: /* Voltage Interface */ -+ switch(spdRawData[i]) -+ { -+ case 0x0: -+ mvOsOutput("Module is TTL_5V_TOLERANT\n"); -+ break; -+ case 0x1: -+ mvOsOutput("Module is LVTTL\n"); -+ break; -+ case 0x2: -+ mvOsOutput("Module is HSTL_1_5V\n"); -+ break; -+ case 0x3: -+ mvOsOutput("Module is SSTL_3_3V\n"); -+ break; -+ case 0x4: -+ mvOsOutput("Module is SSTL_2_5V\n"); -+ break; -+ case 0x5: -+ if (dimmInfo.memoryType != MEM_TYPE_SDRAM) -+ { -+ mvOsOutput("Module is SSTL_1_8V\n"); -+ break; -+ } -+ default: -+ mvOsOutput("Module is VOLTAGE_UNKNOWN\n"); -+ break; -+ } -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 9: /* Minimum Cycle Time At Max CasLatancy */ -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ rightOfPoint = (spdRawData[i] & 0x0f) * 10; -+ -+ /* DDR2 addition of right of point */ -+ if ((spdRawData[i] & 0x0f) == 0xA) -+ { -+ rightOfPoint = 25; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xB) -+ { -+ rightOfPoint = 33; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xC) -+ { -+ rightOfPoint = 66; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xD) -+ { -+ rightOfPoint = 75; -+ } -+ mvOsOutput("Minimum Cycle Time At Max CL: %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 10: /* Clock To Data Out */ -+ div = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 10:100; -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / div; -+ rightOfPoint = time_tmp % div; -+ mvOsOutput("Clock To Data Out: %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 11: /* Error Check Type */ -+ mvOsOutput("Error Check Type (0=NONE): %d\n", -+ dimmInfo.errorCheckType); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 12: /* Refresh Interval */ -+ mvOsOutput("Refresh Rate: %x\n", -+ dimmInfo.refreshInterval); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 13: /* Sdram Width */ -+ mvOsOutput("Sdram Width: %d bits\n", -+ dimmInfo.sdramWidth); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 14: /* Error Check Data Width */ -+ mvOsOutput("Error Check Data Width: %d bits\n", -+ dimmInfo.errorCheckDataWidth); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 15: /* Minimum Clock Delay is unsupported */ -+ if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || -+ (dimmInfo.memoryType == MEM_TYPE_DDR1)) -+ { -+ mvOsOutput("Minimum Clk Delay back to back: %d\n", -+ spdRawData[i]); -+ } -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 16: /* Burst Length Supported */ -+ /* SDRAM/DDR1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * -+ *********************************************************/ -+ /* DDR2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * -+ *********************************************************/ -+ mvOsOutput("Burst Length Supported: "); -+ if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || -+ (dimmInfo.memoryType == MEM_TYPE_DDR1)) -+ { -+ if (dimmInfo.burstLengthSupported & BIT0) -+ mvOsOutput("1, "); -+ if (dimmInfo.burstLengthSupported & BIT1) -+ mvOsOutput("2, "); -+ } -+ if (dimmInfo.burstLengthSupported & BIT2) -+ mvOsOutput("4, "); -+ if (dimmInfo.burstLengthSupported & BIT3) -+ mvOsOutput("8, "); -+ -+ mvOsOutput(" Bit \n"); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 17: /* Number Of Banks On Each Device */ -+ mvOsOutput("Number Of Banks On Each Chip: %d\n", -+ dimmInfo.numOfBanksOnEachDevice); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 18: /* Suported Cas Latencies */ -+ -+ /* SDRAM: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * -+ ********************************************************/ -+ -+ /* DDR 1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * -+ *********************************************************/ -+ -+ /* DDR 2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * -+ *********************************************************/ -+ -+ mvOsOutput("Suported Cas Latencies: (CL) "); -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ for (k = 0; k <=7; k++) -+ { -+ if (dimmInfo.suportedCasLatencies & (1 << k)) -+ mvOsOutput("%d, ", k+1); -+ } -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ { -+ if (dimmInfo.suportedCasLatencies & BIT0) -+ mvOsOutput("1, "); -+ if (dimmInfo.suportedCasLatencies & BIT1) -+ mvOsOutput("1.5, "); -+ if (dimmInfo.suportedCasLatencies & BIT2) -+ mvOsOutput("2, "); -+ if (dimmInfo.suportedCasLatencies & BIT3) -+ mvOsOutput("2.5, "); -+ if (dimmInfo.suportedCasLatencies & BIT4) -+ mvOsOutput("3, "); -+ if (dimmInfo.suportedCasLatencies & BIT5) -+ mvOsOutput("3.5, "); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) -+ { -+ if (dimmInfo.suportedCasLatencies & BIT2) -+ mvOsOutput("2, "); -+ if (dimmInfo.suportedCasLatencies & BIT3) -+ mvOsOutput("3, "); -+ if (dimmInfo.suportedCasLatencies & BIT4) -+ mvOsOutput("4, "); -+ if (dimmInfo.suportedCasLatencies & BIT5) -+ mvOsOutput("5, "); -+ } -+ else -+ mvOsOutput("?.?, "); -+ mvOsOutput("\n"); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 20: /* DDR2 DIMM type info */ -+ if (dimmInfo.memoryType == MEM_TYPE_DDR2) -+ { -+ if (dimmInfo.dimmTypeInfo & (BIT0 | BIT4)) -+ mvOsOutput("Registered DIMM (RDIMM)\n"); -+ else if (dimmInfo.dimmTypeInfo & (BIT1 | BIT5)) -+ mvOsOutput("Unbuffered DIMM (UDIMM)\n"); -+ else -+ mvOsOutput("Unknown DIMM type.\n"); -+ } -+ -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 21: /* SDRAM Modules Attributes */ -+ mvOsOutput("\nModule Attributes (SPD Byte 21): \n"); -+ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ if (dimmInfo.dimmAttributes & BIT0) -+ mvOsOutput(" Buffered Addr/Control Input: Yes\n"); -+ else -+ mvOsOutput(" Buffered Addr/Control Input: No\n"); -+ -+ if (dimmInfo.dimmAttributes & BIT1) -+ mvOsOutput(" Registered Addr/Control Input: Yes\n"); -+ else -+ mvOsOutput(" Registered Addr/Control Input: No\n"); -+ -+ if (dimmInfo.dimmAttributes & BIT2) -+ mvOsOutput(" On-Card PLL (clock): Yes \n"); -+ else -+ mvOsOutput(" On-Card PLL (clock): No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT3) -+ mvOsOutput(" Bufferd DQMB Input: Yes \n"); -+ else -+ mvOsOutput(" Bufferd DQMB Inputs: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT4) -+ mvOsOutput(" Registered DQMB Inputs: Yes \n"); -+ else -+ mvOsOutput(" Registered DQMB Inputs: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT5) -+ mvOsOutput(" Differential Clock Input: Yes \n"); -+ else -+ mvOsOutput(" Differential Clock Input: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT6) -+ mvOsOutput(" redundant Row Addressing: Yes \n"); -+ else -+ mvOsOutput(" redundant Row Addressing: No \n"); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ { -+ if (dimmInfo.dimmAttributes & BIT0) -+ mvOsOutput(" Buffered Addr/Control Input: Yes\n"); -+ else -+ mvOsOutput(" Buffered Addr/Control Input: No\n"); -+ -+ if (dimmInfo.dimmAttributes & BIT1) -+ mvOsOutput(" Registered Addr/Control Input: Yes\n"); -+ else -+ mvOsOutput(" Registered Addr/Control Input: No\n"); -+ -+ if (dimmInfo.dimmAttributes & BIT2) -+ mvOsOutput(" On-Card PLL (clock): Yes \n"); -+ else -+ mvOsOutput(" On-Card PLL (clock): No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT3) -+ mvOsOutput(" FET Switch On-Card Enabled: Yes \n"); -+ else -+ mvOsOutput(" FET Switch On-Card Enabled: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT4) -+ mvOsOutput(" FET Switch External Enabled: Yes \n"); -+ else -+ mvOsOutput(" FET Switch External Enabled: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT5) -+ mvOsOutput(" Differential Clock Input: Yes \n"); -+ else -+ mvOsOutput(" Differential Clock Input: No \n"); -+ } -+ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ -+ { -+ mvOsOutput(" Number of Active Registers on the DIMM: %d\n", -+ (dimmInfo.dimmAttributes & 0x3) + 1); -+ -+ mvOsOutput(" Number of PLLs on the DIMM: %d\n", -+ ((dimmInfo.dimmAttributes) >> 2) & 0x3); -+ -+ if (dimmInfo.dimmAttributes & BIT4) -+ mvOsOutput(" FET Switch External Enabled: Yes \n"); -+ else -+ mvOsOutput(" FET Switch External Enabled: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT6) -+ mvOsOutput(" Analysis probe installed: Yes \n"); -+ else -+ mvOsOutput(" Analysis probe installed: No \n"); -+ } -+ -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 22: /* Suported AutoPreCharge */ -+ mvOsOutput("\nModul Attributes (SPD Byte 22): \n"); -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ if ( spdRawData[i] & BIT0 ) -+ mvOsOutput(" Early Ras Precharge: Yes \n"); -+ else -+ mvOsOutput(" Early Ras Precharge: No \n"); -+ -+ if ( spdRawData[i] & BIT1 ) -+ mvOsOutput(" AutoPreCharge: Yes \n"); -+ else -+ mvOsOutput(" AutoPreCharge: No \n"); -+ -+ if ( spdRawData[i] & BIT2 ) -+ mvOsOutput(" Precharge All: Yes \n"); -+ else -+ mvOsOutput(" Precharge All: No \n"); -+ -+ if ( spdRawData[i] & BIT3 ) -+ mvOsOutput(" Write 1/ReadBurst: Yes \n"); -+ else -+ mvOsOutput(" Write 1/ReadBurst: No \n"); -+ -+ if ( spdRawData[i] & BIT4 ) -+ mvOsOutput(" lower VCC tolerance: 5%%\n"); -+ else -+ mvOsOutput(" lower VCC tolerance: 10%%\n"); -+ -+ if ( spdRawData[i] & BIT5 ) -+ mvOsOutput(" upper VCC tolerance: 5%%\n"); -+ else -+ mvOsOutput(" upper VCC tolerance: 10%%\n"); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ { -+ if ( spdRawData[i] & BIT0 ) -+ mvOsOutput(" Supports Weak Driver: Yes \n"); -+ else -+ mvOsOutput(" Supports Weak Driver: No \n"); -+ -+ if ( !(spdRawData[i] & BIT4) ) -+ mvOsOutput(" lower VCC tolerance: 0.2V\n"); -+ -+ if ( !(spdRawData[i] & BIT5) ) -+ mvOsOutput(" upper VCC tolerance: 0.2V\n"); -+ -+ if ( spdRawData[i] & BIT6 ) -+ mvOsOutput(" Concurrent Auto Preharge: Yes \n"); -+ else -+ mvOsOutput(" Concurrent Auto Preharge: No \n"); -+ -+ if ( spdRawData[i] & BIT7 ) -+ mvOsOutput(" Supports Fast AP: Yes \n"); -+ else -+ mvOsOutput(" Supports Fast AP: No \n"); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) -+ { -+ if ( spdRawData[i] & BIT0 ) -+ mvOsOutput(" Supports Weak Driver: Yes \n"); -+ else -+ mvOsOutput(" Supports Weak Driver: No \n"); -+ } -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 23: -+ /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */ -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ rightOfPoint = (spdRawData[i] & 0x0f) * 10; -+ -+ /* DDR2 addition of right of point */ -+ if ((spdRawData[i] & 0x0f) == 0xA) -+ { -+ rightOfPoint = 25; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xB) -+ { -+ rightOfPoint = 33; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xC) -+ { -+ rightOfPoint = 66; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xD) -+ { -+ rightOfPoint = 75; -+ } -+ -+ mvOsOutput("Minimum Cycle Time At 2nd highest CasLatancy" -+ "(0 = Not supported): %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint ); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 24: /* Clock To Data Out 2nd highest Cas Latency Value*/ -+ div = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? 10:100; -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / div; -+ rightOfPoint = time_tmp % div; -+ mvOsOutput("Clock To Data Out (2nd CL value): %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 25: -+ /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ leftOfPoint = (spdRawData[i] & 0xfc) >> 2; -+ rightOfPoint = (spdRawData[i] & 0x3) * 25; -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ rightOfPoint = (spdRawData[i] & 0x0f) * 10; -+ -+ /* DDR2 addition of right of point */ -+ if ((spdRawData[i] & 0x0f) == 0xA) -+ { -+ rightOfPoint = 25; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xB) -+ { -+ rightOfPoint = 33; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xC) -+ { -+ rightOfPoint = 66; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xD) -+ { -+ rightOfPoint = 75; -+ } -+ } -+ mvOsOutput("Minimum Cycle Time At 3rd highest CasLatancy" -+ "(0 = Not supported): %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint ); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 26: /* Clock To Data Out 3rd highest Cas Latency Value*/ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ leftOfPoint = (spdRawData[i] & 0xfc) >> 2; -+ rightOfPoint = (spdRawData[i] & 0x3) * 25; -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = 0; -+ rightOfPoint = time_tmp; -+ } -+ mvOsOutput("Clock To Data Out (3rd CL value): %d.%2d[ns]\n", -+ leftOfPoint, rightOfPoint ); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 27: /* Minimum Row Precharge Time */ -+ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; -+ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0xff : 0xfc; -+ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0x00 : 0x03; -+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); -+ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; -+ temp = ((leftOfPoint*100) + rightOfPoint);/* in 10ps Intervals*/ -+ trp_clocks = (temp + (busClkPs-1)) / busClkPs; -+ mvOsOutput("Minimum Row Precharge Time [ns]: %d.%d = " -+ "in Clk cycles %d\n", -+ leftOfPoint, rightOfPoint, trp_clocks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 28: /* Minimum Row Active to Row Active Time */ -+ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; -+ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0xff : 0xfc; -+ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0x00 : 0x03; -+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); -+ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; -+ temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ -+ trrd_clocks = (temp + (busClkPs-1)) / busClkPs; -+ mvOsOutput("Minimum Row Active -To- Row Active Delay [ns]: " -+ "%d.%d = in Clk cycles %d\n", -+ leftOfPoint, rightOfPoint, trp_clocks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 29: /* Minimum Ras-To-Cas Delay */ -+ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; -+ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0xff : 0xfc; -+ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0x00 : 0x03; -+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); -+ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; -+ temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ -+ trcd_clocks = (temp + (busClkPs-1) )/ busClkPs; -+ mvOsOutput("Minimum Ras-To-Cas Delay [ns]: %d.%d = " -+ "in Clk cycles %d\n", -+ leftOfPoint, rightOfPoint, trp_clocks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 30: /* Minimum Ras Pulse Width */ -+ tras_clocks = (cas2ps(spdRawData[i])+(busClkPs-1)) / busClkPs; -+ mvOsOutput("Minimum Ras Pulse Width [ns]: %d = " -+ "in Clk cycles %d\n", spdRawData[i], tras_clocks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 31: /* Module Bank Density */ -+ mvOsOutput("Module Bank Density (more than 1= Multisize-Module):"); -+ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ if (dimmInfo.dimmBankDensity & BIT0) -+ mvOsOutput("1GB, "); -+ if (dimmInfo.dimmBankDensity & BIT1) -+ mvOsOutput("8MB, "); -+ if (dimmInfo.dimmBankDensity & BIT2) -+ mvOsOutput("16MB, "); -+ if (dimmInfo.dimmBankDensity & BIT3) -+ mvOsOutput("32MB, "); -+ if (dimmInfo.dimmBankDensity & BIT4) -+ mvOsOutput("64MB, "); -+ if (dimmInfo.dimmBankDensity & BIT5) -+ mvOsOutput("128MB, "); -+ if (dimmInfo.dimmBankDensity & BIT6) -+ mvOsOutput("256MB, "); -+ if (dimmInfo.dimmBankDensity & BIT7) -+ mvOsOutput("512MB, "); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ { -+ if (dimmInfo.dimmBankDensity & BIT0) -+ mvOsOutput("1GB, "); -+ if (dimmInfo.dimmBankDensity & BIT1) -+ mvOsOutput("2GB, "); -+ if (dimmInfo.dimmBankDensity & BIT2) -+ mvOsOutput("16MB, "); -+ if (dimmInfo.dimmBankDensity & BIT3) -+ mvOsOutput("32MB, "); -+ if (dimmInfo.dimmBankDensity & BIT4) -+ mvOsOutput("64MB, "); -+ if (dimmInfo.dimmBankDensity & BIT5) -+ mvOsOutput("128MB, "); -+ if (dimmInfo.dimmBankDensity & BIT6) -+ mvOsOutput("256MB, "); -+ if (dimmInfo.dimmBankDensity & BIT7) -+ mvOsOutput("512MB, "); -+ } -+ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ -+ { -+ if (dimmInfo.dimmBankDensity & BIT0) -+ mvOsOutput("1GB, "); -+ if (dimmInfo.dimmBankDensity & BIT1) -+ mvOsOutput("2GB, "); -+ if (dimmInfo.dimmBankDensity & BIT2) -+ mvOsOutput("4GB, "); -+ if (dimmInfo.dimmBankDensity & BIT3) -+ mvOsOutput("8GB, "); -+ if (dimmInfo.dimmBankDensity & BIT4) -+ mvOsOutput("16GB, "); -+ if (dimmInfo.dimmBankDensity & BIT5) -+ mvOsOutput("128MB, "); -+ if (dimmInfo.dimmBankDensity & BIT6) -+ mvOsOutput("256MB, "); -+ if (dimmInfo.dimmBankDensity & BIT7) -+ mvOsOutput("512MB, "); -+ } -+ mvOsOutput("\n"); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 32: /* Address And Command Setup Time (measured in ns/1000) */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ rightOfPoint = (spdRawData[i] & 0x0f); -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ if(leftOfPoint > 7) -+ { -+ leftOfPoint *= -1; -+ } -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / 100; -+ rightOfPoint = time_tmp % 100; -+ } -+ mvOsOutput("Address And Command Setup Time [ns]: %d.%d\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 33: /* Address And Command Hold Time */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ rightOfPoint = (spdRawData[i] & 0x0f); -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ if(leftOfPoint > 7) -+ { -+ leftOfPoint *= -1; -+ } -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / 100; -+ rightOfPoint = time_tmp % 100; -+ } -+ mvOsOutput("Address And Command Hold Time [ns]: %d.%d\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 34: /* Data Input Setup Time */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ rightOfPoint = (spdRawData[i] & 0x0f); -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ if(leftOfPoint > 7) -+ { -+ leftOfPoint *= -1; -+ } -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / 100; -+ rightOfPoint = time_tmp % 100; -+ } -+ mvOsOutput("Data Input Setup Time [ns]: %d.%d\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 35: /* Data Input Hold Time */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ rightOfPoint = (spdRawData[i] & 0x0f); -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ if(leftOfPoint > 7) -+ { -+ leftOfPoint *= -1; -+ } -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / 100; -+ rightOfPoint = time_tmp % 100; -+ } -+ mvOsOutput("Data Input Hold Time [ns]: %d.%d\n\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 36: /* Relevant for DDR2 only: Write Recovery Time */ -+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> 2); -+ rightOfPoint = (spdRawData[i] & maskRightOfPoint) * 25; -+ mvOsOutput("Write Recovery Time [ns]: %d.%d\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ } -+ -+} -+ -+ -+/* -+ * translate ns.ns/10 coding of SPD timing values -+ * into ps unit values -+ */ -+/******************************************************************************* -+* cas2ps - Translate x.y ns parameter to pico-seconds values -+* -+* DESCRIPTION: -+* This function translates x.y nano seconds to its value in pico seconds. -+* For example 3.75ns will return 3750. -+* -+* INPUT: -+* spd_byte - DIMM SPD byte. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* value in pico seconds. -+* -+*******************************************************************************/ -+static MV_U32 cas2ps(MV_U8 spd_byte) -+{ -+ MV_U32 ns, ns10; -+ -+ /* isolate upper nibble */ -+ ns = (spd_byte >> 4) & 0x0F; -+ /* isolate lower nibble */ -+ ns10 = (spd_byte & 0x0F); -+ -+ if( ns10 < 10 ) { -+ ns10 *= 10; -+ } -+ else if( ns10 == 10 ) -+ ns10 = 25; -+ else if( ns10 == 11 ) -+ ns10 = 33; -+ else if( ns10 == 12 ) -+ ns10 = 66; -+ else if( ns10 == 13 ) -+ ns10 = 75; -+ else -+ { -+ mvOsOutput("cas2ps Err. unsupported cycle time.\n"); -+ } -+ -+ return (ns*1000 + ns10*10); -+} -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,192 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvDram -+#define __INCmvDram -+ -+#include "ddr2/mvDramIf.h" -+#include "twsi/mvTwsi.h" -+ -+#define MAX_DIMM_NUM 2 -+#define SPD_SIZE 128 -+ -+/* Dimm spd offsets */ -+#define DIMM_MEM_TYPE 2 -+#define DIMM_ROW_NUM 3 -+#define DIMM_COL_NUM 4 -+#define DIMM_MODULE_BANK_NUM 5 -+#define DIMM_DATA_WIDTH 6 -+#define DIMM_VOLT_IF 8 -+#define DIMM_MIN_CC_AT_MAX_CAS 9 -+#define DIMM_ERR_CHECK_TYPE 11 -+#define DIMM_REFRESH_INTERVAL 12 -+#define DIMM_SDRAM_WIDTH 13 -+#define DIMM_ERR_CHECK_DATA_WIDTH 14 -+#define DIMM_MIN_CLK_DEL 15 -+#define DIMM_BURST_LEN_SUP 16 -+#define DIMM_DEV_BANK_NUM 17 -+#define DIMM_SUP_CAL 18 -+#define DIMM_DDR2_TYPE_INFORMATION 20 /* DDR2 only */ -+#define DIMM_BUF_ADDR_CONT_IN 21 -+#define DIMM_MIN_CC_AT_MAX_CAS_MINUS1 23 -+#define DIMM_MIN_CC_AT_MAX_CAS_MINUS2 25 -+#define DIMM_MIN_ROW_PRECHARGE_TIME 27 -+#define DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE 28 -+#define DIMM_MIN_RAS_TO_CAS_DELAY 29 -+#define DIMM_MIN_RAS_PULSE_WIDTH 30 -+#define DIMM_BANK_DENSITY 31 -+#define DIMM_MIN_WRITE_RECOVERY_TIME 36 -+#define DIMM_MIN_WRITE_TO_READ_CMD_DELAY 37 -+#define DIMM_MIN_READ_TO_PRECH_CMD_DELAY 38 -+#define DIMM_MIN_REFRESH_TO_ACTIVATE_CMD 42 -+#define DIMM_SPD_VERSION 62 -+ -+/* Dimm Memory Type values */ -+#define DIMM_MEM_TYPE_SDRAM 0x4 -+#define DIMM_MEM_TYPE_DDR1 0x7 -+#define DIMM_MEM_TYPE_DDR2 0x8 -+ -+#define DIMM_MODULE_MANU_OFFS 64 -+#define DIMM_MODULE_MANU_SIZE 8 -+#define DIMM_MODULE_VEN_OFFS 73 -+#define DIMM_MODULE_VEN_SIZE 25 -+#define DIMM_MODULE_ID_OFFS 99 -+#define DIMM_MODULE_ID_SIZE 18 -+ -+/* enumeration for voltage levels. */ -+typedef enum _mvDimmVoltageIf -+{ -+ TTL_5V_TOLERANT, -+ LVTTL, -+ HSTL_1_5V, -+ SSTL_3_3V, -+ SSTL_2_5V, -+ VOLTAGE_UNKNOWN, -+} MV_DIMM_VOLTAGE_IF; -+ -+ -+/* enumaration for SDRAM CAS Latencies. */ -+typedef enum _mvDimmSdramCas -+{ -+ SD_CL_1 =1, -+ SD_CL_2, -+ SD_CL_3, -+ SD_CL_4, -+ SD_CL_5, -+ SD_CL_6, -+ SD_CL_7, -+ SD_FAULT -+}MV_DIMM_SDRAM_CAS; -+ -+ -+/* DIMM information structure */ -+typedef struct _mvDimmInfo -+{ -+ MV_MEMORY_TYPE memoryType; /* DDR or SDRAM */ -+ -+ MV_U8 spdRawData[SPD_SIZE]; /* Content of SPD-EEPROM copied 1:1 */ -+ -+ /* DIMM dimensions */ -+ MV_U32 numOfRowAddr; -+ MV_U32 numOfColAddr; -+ MV_U32 numOfModuleBanks; -+ MV_U32 dataWidth; -+ MV_U32 errorCheckType; /* ECC , PARITY..*/ -+ MV_U32 sdramWidth; /* 4,8,16 or 32 */ -+ MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ -+ MV_U32 burstLengthSupported; -+ MV_U32 numOfBanksOnEachDevice; -+ MV_U32 suportedCasLatencies; -+ MV_U32 refreshInterval; -+ MV_U32 dimmBankDensity; -+ MV_U32 dimmTypeInfo; /* DDR2 only */ -+ MV_U32 dimmAttributes; -+ -+ /* DIMM timing parameters */ -+ MV_U32 minCycleTimeAtMaxCasLatPs; -+ MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; -+ MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; -+ MV_U32 minRowPrechargeTime; -+ MV_U32 minRowActiveToRowActive; -+ MV_U32 minRasToCasDelay; -+ MV_U32 minRasPulseWidth; -+ MV_U32 minWriteRecoveryTime; /* DDR2 only */ -+ MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ -+ MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ -+ MV_U32 minRefreshToActiveCmd; /* DDR2 only */ -+ -+ /* Parameters calculated from the extracted DIMM information */ -+ MV_U32 size; /* 16,64,128,256 or 512 MByte in MB units */ -+ MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit in MB units */ -+ MV_U32 numberOfDevices; -+ -+} MV_DIMM_INFO; -+ -+ -+MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo); -+MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo); -+MV_VOID dimmSpdPrint(MV_U32 dimmNum); -+MV_STATUS dimmSpdCpy(MV_VOID); -+ -+#endif /* __INCmvDram */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEth.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEth.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEth.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEth.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,2952 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+/******************************************************************************* -+* mvEth.c - Marvell's Gigabit Ethernet controller low level driver -+* -+* DESCRIPTION: -+* This file introduce OS independent APIs to Marvell's Gigabit Ethernet -+* controller. This Gigabit Ethernet Controller driver API controls -+* 1) Operations (i.e. port Init, Finish, Up, Down, PhyReset etc'). -+* 2) Data flow (i.e. port Send, Receive etc'). -+* 3) MAC Filtering functions (ethSetMcastAddr, ethSetRxFilterMode, etc.) -+* 4) MIB counters support (ethReadMibCounter) -+* 5) Debug functions (ethPortRegs, ethPortCounters, ethPortQueues, etc.) -+* Each Gigabit Ethernet port is controlled via ETH_PORT_CTRL struct. -+* This struct includes configuration information as well as driver -+* internal data needed for its operations. -+* -+* Supported Features: -+* - OS independent. All required OS services are implemented via external -+* OS dependent components (like osLayer or ethOsg) -+* - The user is free from Rx/Tx queue managing. -+* - Simple Gigabit Ethernet port operation API. -+* - Simple Gigabit Ethernet port data flow API. -+* - Data flow and operation API support per queue functionality. -+* - Support cached descriptors for better performance. -+* - PHY access and control API. -+* - Port Configuration API. -+* - Full control over Special and Other Multicast MAC tables. -+* -+*******************************************************************************/ -+/* includes */ -+#include "mvTypes.h" -+#include "mv802_3.h" -+#include "mvDebug.h" -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "eth-phy/mvEthPhy.h" -+#include "eth/mvEth.h" -+#include "eth/gbe/mvEthGbe.h" -+#include "cpu/mvCpu.h" -+ -+#ifdef INCLUDE_SYNC_BARR -+#include "sys/mvCpuIf.h" -+#endif -+ -+#ifdef MV_RT_DEBUG -+# define ETH_DEBUG -+#endif -+ -+ -+/* locals */ -+MV_BOOL ethDescInSram; -+MV_BOOL ethDescSwCoher; -+ -+/* This array holds the control structure of each port */ -+ETH_PORT_CTRL* ethPortCtrl[MV_ETH_MAX_PORTS]; -+ -+/* Ethernet Port Local routines */ -+ -+static void ethInitRxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue); -+ -+static void ethInitTxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue); -+ -+static void ethSetUcastTable(int portNo, int queue); -+ -+static MV_BOOL ethSetUcastAddr (int ethPortNum, MV_U8 lastNibble, int queue); -+static MV_BOOL ethSetSpecialMcastAddr(int ethPortNum, MV_U8 lastByte, int queue); -+static MV_BOOL ethSetOtherMcastAddr(int ethPortNum, MV_U8 crc8, int queue); -+ -+static void ethFreeDescrMemory(ETH_PORT_CTRL* pEthPortCtrl, MV_BUF_INFO* pDescBuf); -+static MV_U8* ethAllocDescrMemory(ETH_PORT_CTRL* pEthPortCtrl, int size, -+ MV_ULONG* pPhysAddr, MV_U32 *memHandle); -+ -+static MV_U32 mvEthMruGet(MV_U32 maxRxPktSize); -+ -+static void mvEthPortSgmiiConfig(int port); -+ -+ -+ -+/******************************************************************************/ -+/* EthDrv Initialization functions */ -+/******************************************************************************/ -+ -+/******************************************************************************* -+* mvEthHalInit - Initialize the Giga Ethernet unit -+* -+* DESCRIPTION: -+* This function initialize the Giga Ethernet unit. -+* 1) Configure Address decode windows of the unit -+* 2) Set registers to HW default values. -+* 3) Clear and Disable interrupts -+* -+* INPUT: NONE -+* -+* RETURN: NONE -+* -+* NOTE: this function is called once in the boot process. -+*******************************************************************************/ -+void mvEthHalInit(void) -+{ -+ int port; -+ -+ /* Init static data structures */ -+ for (port=0; port 0) -+ { -+ isSram = MV_TRUE; -+ #if (INTEG_SRAM_COHER == MV_CACHE_COHER_SW) -+ isSwCoher = MV_TRUE; -+ #else -+ isSwCoher = MV_FALSE; -+ #endif -+ } -+#endif /* ETH_DESCR_IN_SRAM */ -+ -+ if(pIsSram != NULL) -+ *pIsSram = isSram; -+ -+ if(pIsSwCoher != NULL) -+ *pIsSwCoher = isSwCoher; -+} -+ -+ -+ -+/******************************************************************************/ -+/* Port Initialization functions */ -+/******************************************************************************/ -+ -+/******************************************************************************* -+* mvEthPortInit - Initialize the Ethernet port driver -+* -+* DESCRIPTION: -+* This function initialize the ethernet port. -+* 1) Allocate and initialize internal port Control structure. -+* 2) Create RX and TX descriptor rings for default RX and TX queues -+* 3) Disable RX and TX operations, clear cause registers and -+* mask all interrupts. -+* 4) Set all registers to default values and clean all MAC tables. -+* -+* INPUT: -+* int portNo - Ethernet port number -+* ETH_PORT_INIT *pEthPortInit - Ethernet port init structure -+* -+* RETURN: -+* void* - ethernet port handler, that should be passed to the most other -+* functions dealing with this port. -+* -+* NOTE: This function is called once per port when loading the eth module. -+*******************************************************************************/ -+void* mvEthPortInit(int portNo, MV_ETH_PORT_INIT *pEthPortInit) -+{ -+ int queue, descSize; -+ ETH_PORT_CTRL* pPortCtrl; -+ -+ /* Check validity of parameters */ -+ if( (portNo >= (int)mvCtrlEthMaxPortGet()) || -+ (pEthPortInit->rxDefQ >= MV_ETH_RX_Q_NUM) || -+ (pEthPortInit->maxRxPktSize < 1518) ) -+ { -+ mvOsPrintf("EthPort #%d: Bad initialization parameters\n", portNo); -+ return NULL; -+ } -+ if( (pEthPortInit->rxDescrNum[pEthPortInit->rxDefQ]) == 0) -+ { -+ mvOsPrintf("EthPort #%d: rxDefQ (%d) must be created\n", -+ portNo, pEthPortInit->rxDefQ); -+ return NULL; -+ } -+ -+ pPortCtrl = (ETH_PORT_CTRL*)mvOsMalloc( sizeof(ETH_PORT_CTRL) ); -+ if(pPortCtrl == NULL) -+ { -+ mvOsPrintf("EthDrv: Can't allocate %dB for port #%d control structure!\n", -+ (int)sizeof(ETH_PORT_CTRL), portNo); -+ return NULL; -+ } -+ -+ memset(pPortCtrl, 0, sizeof(ETH_PORT_CTRL) ); -+ ethPortCtrl[portNo] = pPortCtrl; -+ -+ pPortCtrl->portState = MV_UNDEFINED_STATE; -+ -+ pPortCtrl->portNo = portNo; -+ -+ pPortCtrl->osHandle = pEthPortInit->osHandle; -+ -+ /* Copy Configuration parameters */ -+ pPortCtrl->portConfig.maxRxPktSize = pEthPortInit->maxRxPktSize; -+ pPortCtrl->portConfig.rxDefQ = pEthPortInit->rxDefQ; -+ pPortCtrl->portConfig.ejpMode = 0; -+ -+ for( queue=0; queuerxQueueConfig[queue].descrNum = pEthPortInit->rxDescrNum[queue]; -+ } -+ for( queue=0; queuetxQueueConfig[queue].descrNum = pEthPortInit->txDescrNum[queue]; -+ } -+ -+ mvEthPortDisable(pPortCtrl); -+ -+ /* Set the board information regarding PHY address */ -+ mvEthPhyAddrSet(pPortCtrl, mvBoardPhyAddrGet(portNo) ); -+ -+ /* Create all requested RX queues */ -+ for(queue=0; queuerxQueueConfig[queue].descrNum == 0) -+ continue; -+ -+ /* Allocate memory for RX descriptors */ -+ descSize = ((pPortCtrl->rxQueueConfig[queue].descrNum * ETH_RX_DESC_ALIGNED_SIZE) + -+ CPU_D_CACHE_LINE_SIZE); -+ -+ pPortCtrl->rxQueue[queue].descBuf.bufVirtPtr = -+ ethAllocDescrMemory(pPortCtrl, descSize, -+ &pPortCtrl->rxQueue[queue].descBuf.bufPhysAddr, -+ &pPortCtrl->rxQueue[queue].descBuf.memHandle); -+ pPortCtrl->rxQueue[queue].descBuf.bufSize = descSize; -+ if(pPortCtrl->rxQueue[queue].descBuf.bufVirtPtr == NULL) -+ { -+ mvOsPrintf("EthPort #%d, rxQ=%d: Can't allocate %d bytes in %s for %d RX descr\n", -+ pPortCtrl->portNo, queue, descSize, -+ ethDescInSram ? "SRAM" : "DRAM", -+ pPortCtrl->rxQueueConfig[queue].descrNum); -+ return NULL; -+ } -+ -+ ethInitRxDescRing(pPortCtrl, queue); -+ } -+ /* Create TX queues */ -+ for(queue=0; queuetxQueueConfig[queue].descrNum == 0) -+ continue; -+ -+ /* Allocate memory for TX descriptors */ -+ descSize = ((pPortCtrl->txQueueConfig[queue].descrNum * ETH_TX_DESC_ALIGNED_SIZE) + -+ CPU_D_CACHE_LINE_SIZE); -+ -+ pPortCtrl->txQueue[queue].descBuf.bufVirtPtr = -+ ethAllocDescrMemory(pPortCtrl, descSize, -+ &pPortCtrl->txQueue[queue].descBuf.bufPhysAddr, -+ &pPortCtrl->txQueue[queue].descBuf.memHandle); -+ pPortCtrl->txQueue[queue].descBuf.bufSize = descSize; -+ if(pPortCtrl->txQueue[queue].descBuf.bufVirtPtr == NULL) -+ { -+ mvOsPrintf("EthPort #%d, txQ=%d: Can't allocate %d bytes in %s for %d TX descr\n", -+ pPortCtrl->portNo, queue, descSize, ethDescInSram ? "SRAM" : "DRAM", -+ pPortCtrl->txQueueConfig[queue].descrNum); -+ return NULL; -+ } -+ -+ ethInitTxDescRing(pPortCtrl, queue); -+ } -+ mvEthDefaultsSet(pPortCtrl); -+ -+ pPortCtrl->portState = MV_IDLE; -+ return pPortCtrl; -+} -+ -+/******************************************************************************* -+* ethPortFinish - Finish the Ethernet port driver -+* -+* DESCRIPTION: -+* This function finish the ethernet port. -+* 1) Down ethernet port if needed. -+* 2) Delete RX and TX descriptor rings for all created RX and TX queues -+* 3) Free internal port Control structure. -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet port handler -+* -+* RETURN: NONE. -+* -+*******************************************************************************/ -+void mvEthPortFinish(void* pPortHndl) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ int queue, portNo = pPortCtrl->portNo; -+ -+ if(pPortCtrl->portState == MV_ACTIVE) -+ { -+ mvOsPrintf("ethPort #%d: Warning !!! Finish port in Active state\n", -+ portNo); -+ mvEthPortDisable(pPortHndl); -+ } -+ -+ /* Free all allocated RX queues */ -+ for(queue=0; queuerxQueue[queue].descBuf); -+ } -+ -+ /* Free all allocated TX queues */ -+ for(queue=0; queuetxQueue[queue].descBuf); -+ } -+ -+ /* Free port control structure */ -+ mvOsFree(pPortCtrl); -+ -+ ethPortCtrl[portNo] = NULL; -+} -+ -+/******************************************************************************* -+* mvEthDefaultsSet - Set defaults to the ethernet port -+* -+* DESCRIPTION: -+* This function set default values to the ethernet port. -+* 1) Clear Cause registers and Mask all interrupts -+* 2) Clear all MAC tables -+* 3) Set defaults to all registers -+* 4) Reset all created RX and TX descriptors ring -+* 5) Reset PHY -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet port handler -+* -+* RETURN: MV_STATUS -+* MV_OK - Success, Others - Failure -+* NOTE: -+* This function update all the port configuration except those set -+* Initialy by the OsGlue by MV_ETH_PORT_INIT. -+* This function can be called after portDown to return the port setting -+* to defaults. -+*******************************************************************************/ -+MV_STATUS mvEthDefaultsSet(void* pPortHndl) -+{ -+ int ethPortNo, queue; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ MV_U32 txPrio; -+ MV_U32 portCfgReg, portCfgExtReg, portSerialCtrlReg, portSerialCtrl1Reg, portSdmaCfgReg; -+ MV_BOARD_MAC_SPEED boardMacCfg; -+ -+ ethPortNo = pPortCtrl->portNo; -+ -+ /* Clear Cause registers */ -+ MV_REG_WRITE(ETH_INTR_CAUSE_REG(ethPortNo),0); -+ MV_REG_WRITE(ETH_INTR_CAUSE_EXT_REG(ethPortNo),0); -+ -+ /* Mask all interrupts */ -+ MV_REG_WRITE(ETH_INTR_MASK_REG(ethPortNo),0); -+ MV_REG_WRITE(ETH_INTR_MASK_EXT_REG(ethPortNo),0); -+ -+ portCfgReg = PORT_CONFIG_VALUE; -+ portCfgExtReg = PORT_CONFIG_EXTEND_VALUE; -+ -+ boardMacCfg = mvBoardMacSpeedGet(ethPortNo); -+ -+ if(boardMacCfg == BOARD_MAC_SPEED_100M) -+ { -+ portSerialCtrlReg = PORT_SERIAL_CONTROL_100MB_FORCE_VALUE; -+ } -+ else if(boardMacCfg == BOARD_MAC_SPEED_1000M) -+ { -+ portSerialCtrlReg = PORT_SERIAL_CONTROL_1000MB_FORCE_VALUE; -+ } -+ else -+ { -+ portSerialCtrlReg = PORT_SERIAL_CONTROL_VALUE; -+ } -+ -+ /* build PORT_SDMA_CONFIG_REG */ -+ portSdmaCfgReg = ETH_TX_INTR_COAL_MASK(0); -+ portSdmaCfgReg |= ETH_TX_BURST_SIZE_MASK(ETH_BURST_SIZE_16_64BIT_VALUE); -+ -+#if ( (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WB) || \ -+ (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WT) ) -+ /* some devices have restricted RX burst size when using HW coherency */ -+ portSdmaCfgReg |= ETH_RX_BURST_SIZE_MASK(ETH_BURST_SIZE_4_64BIT_VALUE); -+#else -+ portSdmaCfgReg |= ETH_RX_BURST_SIZE_MASK(ETH_BURST_SIZE_16_64BIT_VALUE); -+#endif -+ -+#if defined(MV_CPU_BE) -+ /* big endian */ -+# if defined(MV_ARM) -+ portSdmaCfgReg |= (ETH_RX_NO_DATA_SWAP_MASK | -+ ETH_TX_NO_DATA_SWAP_MASK | -+ ETH_DESC_SWAP_MASK); -+# elif defined(MV_PPC) -+ portSdmaCfgReg |= (ETH_RX_DATA_SWAP_MASK | -+ ETH_TX_DATA_SWAP_MASK | -+ ETH_NO_DESC_SWAP_MASK); -+# else -+# error "Giga Ethernet Swap policy is not defined for the CPU_ARCH" -+# endif /* MV_ARM / MV_PPC */ -+ -+#else /* MV_CPU_LE */ -+ /* little endian */ -+ portSdmaCfgReg |= (ETH_RX_NO_DATA_SWAP_MASK | -+ ETH_TX_NO_DATA_SWAP_MASK | -+ ETH_NO_DESC_SWAP_MASK); -+#endif /* MV_CPU_BE / MV_CPU_LE */ -+ -+ pPortCtrl->portRxQueueCmdReg = 0; -+ pPortCtrl->portTxQueueCmdReg = 0; -+ -+#if (MV_ETH_VERSION >= 4) -+ if(pPortCtrl->portConfig.ejpMode == MV_TRUE) -+ { -+ MV_REG_WRITE(ETH_TXQ_CMD_1_REG(ethPortNo), ETH_TX_EJP_ENABLE_MASK); -+ } -+ else -+ { -+ MV_REG_WRITE(ETH_TXQ_CMD_1_REG(ethPortNo), 0) -+ } -+#endif /* (MV_ETH_VERSION >= 4) */ -+ -+ ethSetUcastTable(ethPortNo, -1); -+ mvEthSetSpecialMcastTable(ethPortNo, -1); -+ mvEthSetOtherMcastTable(ethPortNo, -1); -+ -+ portSerialCtrlReg &= ~ETH_MAX_RX_PACKET_SIZE_MASK; -+ -+ portSerialCtrlReg |= mvEthMruGet(pPortCtrl->portConfig.maxRxPktSize); -+ -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNo), portSerialCtrlReg); -+ -+ /* Update value of PortConfig register accordingly with all RxQueue types */ -+ pPortCtrl->portConfig.rxArpQ = pPortCtrl->portConfig.rxDefQ; -+ pPortCtrl->portConfig.rxBpduQ = pPortCtrl->portConfig.rxDefQ; -+ pPortCtrl->portConfig.rxTcpQ = pPortCtrl->portConfig.rxDefQ; -+ pPortCtrl->portConfig.rxUdpQ = pPortCtrl->portConfig.rxDefQ; -+ -+ portCfgReg &= ~ETH_DEF_RX_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_QUEUE_MASK(pPortCtrl->portConfig.rxDefQ); -+ -+ portCfgReg &= ~ETH_DEF_RX_ARP_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_ARP_QUEUE_MASK(pPortCtrl->portConfig.rxArpQ); -+ -+ portCfgReg &= ~ETH_DEF_RX_BPDU_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_BPDU_QUEUE_MASK(pPortCtrl->portConfig.rxBpduQ); -+ -+ portCfgReg &= ~ETH_DEF_RX_TCP_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_TCP_QUEUE_MASK(pPortCtrl->portConfig.rxTcpQ); -+ -+ portCfgReg &= ~ETH_DEF_RX_UDP_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_UDP_QUEUE_MASK(pPortCtrl->portConfig.rxUdpQ); -+ -+ /* Assignment of Tx CTRP of given queue */ -+ txPrio = 0; -+ -+ for(queue=0; queuetxQueue[queue]; -+ -+ if(pQueueCtrl->pFirstDescr != NULL) -+ { -+ ethResetTxDescRing(pPortCtrl, queue); -+ -+ MV_REG_WRITE(ETH_TXQ_TOKEN_COUNT_REG(ethPortNo, queue), -+ 0x3fffffff); -+ MV_REG_WRITE(ETH_TXQ_TOKEN_CFG_REG(ethPortNo, queue), -+ 0x03ffffff); -+ } -+ else -+ { -+ MV_REG_WRITE(ETH_TXQ_TOKEN_COUNT_REG(ethPortNo, queue), 0x0); -+ MV_REG_WRITE(ETH_TXQ_TOKEN_CFG_REG(ethPortNo, queue), 0x0); -+ } -+ } -+ -+ /* Assignment of Rx CRDP of given queue */ -+ for(queue=0; queueportNo; -+ -+ if( (pPortCtrl->portState != MV_ACTIVE) && -+ (pPortCtrl->portState != MV_PAUSED) ) -+ { -+ mvOsPrintf("ethDrv port%d: Unexpected port state %d\n", -+ ethPortNo, pPortCtrl->portState); -+ return MV_BAD_STATE; -+ } -+ -+ ethPortNo = pPortCtrl->portNo; -+ -+ /* Enable port RX. */ -+ MV_REG_WRITE(ETH_RX_QUEUE_COMMAND_REG(ethPortNo), pPortCtrl->portRxQueueCmdReg); -+ -+ /* Enable port TX. */ -+ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(ethPortNo)) = pPortCtrl->portTxQueueCmdReg; -+ -+ pPortCtrl->portState = MV_ACTIVE; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* ethPortDown - Stop the Ethernet port activity. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet port handler -+* -+* RETURN: MV_STATUS -+* MV_OK - Success, Others - Failure. -+* -+* NOTE : used for port link down. -+*******************************************************************************/ -+MV_STATUS mvEthPortDown(void* pEthPortHndl) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ int ethPortNum = pPortCtrl->portNo; -+ unsigned int regData; -+ volatile int uDelay, mDelay; -+ -+ /* Stop Rx port activity. Check port Rx activity. */ -+ regData = (MV_REG_READ(ETH_RX_QUEUE_COMMAND_REG(ethPortNum))) & ETH_RXQ_ENABLE_MASK; -+ if(regData != 0) -+ { -+ /* Issue stop command for active channels only */ -+ MV_REG_WRITE(ETH_RX_QUEUE_COMMAND_REG(ethPortNum), (regData << ETH_RXQ_DISABLE_OFFSET)); -+ } -+ -+ /* Stop Tx port activity. Check port Tx activity. */ -+ regData = (MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(ethPortNum))) & ETH_TXQ_ENABLE_MASK; -+ if(regData != 0) -+ { -+ /* Issue stop command for active channels only */ -+ MV_REG_WRITE(ETH_TX_QUEUE_COMMAND_REG(ethPortNum), -+ (regData << ETH_TXQ_DISABLE_OFFSET) ); -+ } -+ -+ /* Force link down */ -+/* -+ regData = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNum)); -+ regData &= ~(ETH_DO_NOT_FORCE_LINK_FAIL_MASK); -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNum), regData); -+*/ -+ /* Wait for all Rx activity to terminate. */ -+ mDelay = 0; -+ do -+ { -+ if(mDelay >= RX_DISABLE_TIMEOUT_MSEC) -+ { -+ mvOsPrintf("ethPort_%d: TIMEOUT for RX stopped !!! rxQueueCmd - 0x08%x\n", -+ ethPortNum, regData); -+ break; -+ } -+ mvOsDelay(1); -+ mDelay++; -+ -+ /* Check port RX Command register that all Rx queues are stopped */ -+ regData = MV_REG_READ(ETH_RX_QUEUE_COMMAND_REG(ethPortNum)); -+ } -+ while(regData & 0xFF); -+ -+ /* Wait for all Tx activity to terminate. */ -+ mDelay = 0; -+ do -+ { -+ if(mDelay >= TX_DISABLE_TIMEOUT_MSEC) -+ { -+ mvOsPrintf("ethPort_%d: TIMEOUT for TX stoped !!! txQueueCmd - 0x08%x\n", -+ ethPortNum, regData); -+ break; -+ } -+ mvOsDelay(1); -+ mDelay++; -+ -+ /* Check port TX Command register that all Tx queues are stopped */ -+ regData = MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(ethPortNum)); -+ } -+ while(regData & 0xFF); -+ -+ /* Double check to Verify that TX FIFO is Empty */ -+ mDelay = 0; -+ while(MV_TRUE) -+ { -+ do -+ { -+ if(mDelay >= TX_FIFO_EMPTY_TIMEOUT_MSEC) -+ { -+ mvOsPrintf("\n ethPort_%d: TIMEOUT for TX FIFO empty !!! portStatus - 0x08%x\n", -+ ethPortNum, regData); -+ break; -+ } -+ mvOsDelay(1); -+ mDelay++; -+ -+ regData = MV_REG_READ(ETH_PORT_STATUS_REG(ethPortNum)); -+ } -+ while( ((regData & ETH_TX_FIFO_EMPTY_MASK) == 0) || -+ ((regData & ETH_TX_IN_PROGRESS_MASK) != 0) ); -+ -+ if(mDelay >= TX_FIFO_EMPTY_TIMEOUT_MSEC) -+ break; -+ -+ /* Double check */ -+ regData = MV_REG_READ(ETH_PORT_STATUS_REG(ethPortNum)); -+ if( ((regData & ETH_TX_FIFO_EMPTY_MASK) != 0) && -+ ((regData & ETH_TX_IN_PROGRESS_MASK) == 0) ) -+ { -+ break; -+ } -+ else -+ mvOsPrintf("ethPort_%d: TX FIFO Empty double check failed. %d msec, portStatus=0x%x\n", -+ ethPortNum, mDelay, regData); -+ } -+ -+ /* Do NOT force link down */ -+/* -+ regData = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNum)); -+ regData |= (ETH_DO_NOT_FORCE_LINK_FAIL_MASK); -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNum), regData); -+*/ -+ /* Wait about 2500 tclk cycles */ -+ uDelay = (PORT_DISABLE_WAIT_TCLOCKS/(mvBoardTclkGet()/1000000)); -+ mvOsUDelay(uDelay); -+ -+ pPortCtrl->portState = MV_PAUSED; -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* ethPortEnable - Enable the Ethernet port and Start RX and TX. -+* -+* DESCRIPTION: -+* This routine enable the Ethernet port and Rx and Tx activity: -+* -+* Note: Each Rx and Tx queue descriptor's list must be initialized prior -+* to calling this function (use etherInitTxDescRing for Tx queues and -+* etherInitRxDescRing for Rx queues). -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet port handler -+* -+* RETURN: MV_STATUS -+* MV_OK - Success, Others - Failure. -+* -+* NOTE: main usage is to enable the port after ifconfig up. -+*******************************************************************************/ -+MV_STATUS mvEthPortEnable(void* pEthPortHndl) -+{ -+ int ethPortNo; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ MV_U32 portSerialCtrlReg; -+ -+ ethPortNo = pPortCtrl->portNo; -+ -+ /* Enable port */ -+ portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNo)); -+ portSerialCtrlReg |= (ETH_DO_NOT_FORCE_LINK_FAIL_MASK | ETH_PORT_ENABLE_MASK); -+ -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNo), portSerialCtrlReg); -+ -+ mvEthMibCountersClear(pEthPortHndl); -+ -+ pPortCtrl->portState = MV_PAUSED; -+ -+ /* If Link is UP, Start RX and TX traffic */ -+ if( MV_REG_READ( ETH_PORT_STATUS_REG(ethPortNo) ) & ETH_LINK_UP_MASK) -+ return( mvEthPortUp(pEthPortHndl) ); -+ -+ return MV_NOT_READY; -+} -+ -+ -+/******************************************************************************* -+* mvEthPortDisable - Stop RX and TX activities and Disable the Ethernet port. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet port handler -+* -+* RETURN: MV_STATUS -+* MV_OK - Success, Others - Failure. -+* -+* NOTE: main usage is to disable the port after ifconfig down. -+*******************************************************************************/ -+MV_STATUS mvEthPortDisable(void* pEthPortHndl) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ int ethPortNum = pPortCtrl->portNo; -+ unsigned int regData; -+ volatile int mvDelay; -+ -+ if(pPortCtrl->portState == MV_ACTIVE) -+ { -+ /* Stop RX and TX activities */ -+ mvEthPortDown(pEthPortHndl); -+ } -+ -+ /* Reset the Enable bit in the Serial Control Register */ -+ regData = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNum)); -+ regData &= ~(ETH_PORT_ENABLE_MASK); -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNum), regData); -+ -+ /* Wait about 2500 tclk cycles */ -+ mvDelay = (PORT_DISABLE_WAIT_TCLOCKS*(mvCpuPclkGet()/mvBoardTclkGet())); -+ for(mvDelay; mvDelay>0; mvDelay--); -+ -+ pPortCtrl->portState = MV_IDLE; -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthPortForceTxDone - Get next buffer from TX queue in spite of buffer ownership. -+* -+* DESCRIPTION: -+* This routine used to free buffers attached to the Tx ring and should -+* be called only when Giga Ethernet port is Down -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet Port handler. -+* int txQueue - Number of TX queue. -+* -+* OUTPUT: -+* MV_PKT_INFO *pPktInfo - Pointer to packet was sent. -+* -+* RETURN: -+* MV_EMPTY - There is no more buffers in this queue. -+* MV_OK - Buffer detached from the queue and pPktInfo structure -+* filled with relevant information. -+* -+*******************************************************************************/ -+MV_PKT_INFO* mvEthPortForceTxDone(void* pEthPortHndl, int txQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ MV_PKT_INFO* pPktInfo; -+ ETH_TX_DESC* pTxDesc; -+ int port = pPortCtrl->portNo; -+ -+ pQueueCtrl = &pPortCtrl->txQueue[txQueue]; -+ -+ while( (pQueueCtrl->pUsedDescr != pQueueCtrl->pCurrentDescr) || -+ (pQueueCtrl->resource == 0) ) -+ { -+ /* Free next descriptor */ -+ pQueueCtrl->resource++; -+ pTxDesc = (ETH_TX_DESC*)pQueueCtrl->pUsedDescr; -+ -+ /* pPktInfo is available only in descriptors which are last descriptors */ -+ pPktInfo = (MV_PKT_INFO*)pTxDesc->returnInfo; -+ if (pPktInfo) -+ pPktInfo->status = pTxDesc->cmdSts; -+ -+ pTxDesc->cmdSts = 0x0; -+ pTxDesc->returnInfo = 0x0; -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxDesc); -+ -+ pQueueCtrl->pUsedDescr = TX_NEXT_DESC_PTR(pTxDesc, pQueueCtrl); -+ -+ if (pPktInfo) -+ if (pPktInfo->status & ETH_TX_LAST_DESC_MASK) -+ return pPktInfo; -+ } -+ MV_REG_WRITE( ETH_TX_CUR_DESC_PTR_REG(port, txQueue), -+ (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); -+ return NULL; -+} -+ -+ -+ -+/******************************************************************************* -+* mvEthPortForceRx - Get next buffer from RX queue in spite of buffer ownership. -+* -+* DESCRIPTION: -+* This routine used to free buffers attached to the Rx ring and should -+* be called only when Giga Ethernet port is Down -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet Port handler. -+* int rxQueue - Number of Rx queue. -+* -+* OUTPUT: -+* MV_PKT_INFO *pPktInfo - Pointer to received packet. -+* -+* RETURN: -+* MV_EMPTY - There is no more buffers in this queue. -+* MV_OK - Buffer detached from the queue and pBufInfo structure -+* filled with relevant information. -+* -+*******************************************************************************/ -+MV_PKT_INFO* mvEthPortForceRx(void* pEthPortHndl, int rxQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ ETH_RX_DESC* pRxDesc; -+ MV_PKT_INFO* pPktInfo; -+ int port = pPortCtrl->portNo; -+ -+ pQueueCtrl = &pPortCtrl->rxQueue[rxQueue]; -+ -+ if(pQueueCtrl->resource == 0) -+ { -+ MV_REG_WRITE( ETH_RX_CUR_DESC_PTR_REG(port, rxQueue), -+ (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); -+ -+ return NULL; -+ } -+ /* Free next descriptor */ -+ pQueueCtrl->resource--; -+ pRxDesc = (ETH_RX_DESC*)pQueueCtrl->pCurrentDescr; -+ pPktInfo = (MV_PKT_INFO*)pRxDesc->returnInfo; -+ -+ pPktInfo->status = pRxDesc->cmdSts; -+ pRxDesc->cmdSts = 0x0; -+ pRxDesc->returnInfo = 0x0; -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxDesc); -+ -+ pQueueCtrl->pCurrentDescr = RX_NEXT_DESC_PTR(pRxDesc, pQueueCtrl); -+ return pPktInfo; -+} -+ -+ -+/******************************************************************************/ -+/* Port Configuration functions */ -+/******************************************************************************/ -+/******************************************************************************* -+* mvEthMruGet - Get MRU configuration for Max Rx packet size. -+* -+* INPUT: -+* MV_U32 maxRxPktSize - max packet size. -+* -+* RETURN: MV_U32 - MRU configuration. -+* -+*******************************************************************************/ -+static MV_U32 mvEthMruGet(MV_U32 maxRxPktSize) -+{ -+ MV_U32 portSerialCtrlReg = 0; -+ -+ if(maxRxPktSize > 9192) -+ portSerialCtrlReg |= ETH_MAX_RX_PACKET_9700BYTE; -+ else if(maxRxPktSize > 9022) -+ portSerialCtrlReg |= ETH_MAX_RX_PACKET_9192BYTE; -+ else if(maxRxPktSize > 1552) -+ portSerialCtrlReg |= ETH_MAX_RX_PACKET_9022BYTE; -+ else if(maxRxPktSize > 1522) -+ portSerialCtrlReg |= ETH_MAX_RX_PACKET_1552BYTE; -+ else if(maxRxPktSize > 1518) -+ portSerialCtrlReg |= ETH_MAX_RX_PACKET_1522BYTE; -+ else -+ portSerialCtrlReg |= ETH_MAX_RX_PACKET_1518BYTE; -+ -+ return portSerialCtrlReg; -+} -+ -+/******************************************************************************* -+* mvEthRxCoalSet - Sets coalescing interrupt mechanism on RX path -+* -+* DESCRIPTION: -+* This routine sets the RX coalescing interrupt mechanism parameter. -+* This parameter is a timeout counter, that counts in 64 tClk -+* chunks, that when timeout event occurs a maskable interrupt occurs. -+* The parameter is calculated using the tCLK frequency of the -+* MV-64xxx chip, and the required number is in micro seconds. -+* -+* INPUT: -+* void* pPortHndl - Ethernet Port handler. -+* MV_U32 uSec - Number of micro seconds between -+* RX interrupts -+* -+* RETURN: -+* None. -+* -+* COMMENT: -+* 1 sec - TCLK_RATE clocks -+* 1 uSec - TCLK_RATE / 1,000,000 clocks -+* -+* Register Value for N micro seconds - ((N * ( (TCLK_RATE / 1,000,000)) / 64) -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_U32 mvEthRxCoalSet (void* pPortHndl, MV_U32 uSec) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ MV_U32 coal = ((uSec * (mvBoardTclkGet() / 1000000)) / 64); -+ MV_U32 portSdmaCfgReg; -+ -+ portSdmaCfgReg = MV_REG_READ(ETH_SDMA_CONFIG_REG(pPortCtrl->portNo)); -+ portSdmaCfgReg &= ~ETH_RX_INTR_COAL_ALL_MASK; -+ -+ portSdmaCfgReg |= ETH_RX_INTR_COAL_MASK(coal); -+ -+#if (MV_ETH_VERSION >= 2) -+ /* Set additional bit if needed ETH_RX_INTR_COAL_MSB_BIT (25) */ -+ if(ETH_RX_INTR_COAL_MASK(coal) > ETH_RX_INTR_COAL_ALL_MASK) -+ portSdmaCfgReg |= ETH_RX_INTR_COAL_MSB_MASK; -+#endif /* MV_ETH_VERSION >= 2 */ -+ -+ MV_REG_WRITE (ETH_SDMA_CONFIG_REG(pPortCtrl->portNo), portSdmaCfgReg); -+ return coal; -+} -+ -+/******************************************************************************* -+* mvEthTxCoalSet - Sets coalescing interrupt mechanism on TX path -+* -+* DESCRIPTION: -+* This routine sets the TX coalescing interrupt mechanism parameter. -+* This parameter is a timeout counter, that counts in 64 tClk -+* chunks, that when timeout event occurs a maskable interrupt -+* occurs. -+* The parameter is calculated using the tCLK frequency of the -+* MV-64xxx chip, and the required number is in micro seconds. -+* -+* INPUT: -+* void* pPortHndl - Ethernet Port handler. -+* MV_U32 uSec - Number of micro seconds between -+* RX interrupts -+* -+* RETURN: -+* None. -+* -+* COMMENT: -+* 1 sec - TCLK_RATE clocks -+* 1 uSec - TCLK_RATE / 1,000,000 clocks -+* -+* Register Value for N micro seconds - ((N * ( (TCLK_RATE / 1,000,000)) / 64) -+* -+*******************************************************************************/ -+MV_U32 mvEthTxCoalSet(void* pPortHndl, MV_U32 uSec) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ MV_U32 coal = ((uSec * (mvBoardTclkGet() / 1000000)) / 64); -+ MV_U32 regVal; -+ -+ regVal = MV_REG_READ(ETH_TX_FIFO_URGENT_THRESH_REG(pPortCtrl->portNo)); -+ regVal &= ~ETH_TX_INTR_COAL_ALL_MASK; -+ regVal |= ETH_TX_INTR_COAL_MASK(coal); -+ -+ /* Set TX Coalescing mechanism */ -+ MV_REG_WRITE (ETH_TX_FIFO_URGENT_THRESH_REG(pPortCtrl->portNo), regVal); -+ return coal; -+} -+ -+/******************************************************************************* -+* mvEthCoalGet - Gets RX and TX coalescing values in micro seconds -+* -+* DESCRIPTION: -+* This routine gets the RX and TX coalescing interrupt values. -+* The parameter is calculated using the tCLK frequency of the -+* MV-64xxx chip, and the returned numbers are in micro seconds. -+* -+* INPUTs: -+* void* pPortHndl - Ethernet Port handler. -+* -+* OUTPUTs: -+* MV_U32* pRxCoal - Number of micro seconds between RX interrupts -+* MV_U32* pTxCoal - Number of micro seconds between TX interrupts -+* -+* RETURN: -+* MV_STATUS MV_OK - success -+* Others - failure. -+* -+* COMMENT: -+* 1 sec - TCLK_RATE clocks -+* 1 uSec - TCLK_RATE / 1,000,000 clocks -+* -+* Register Value for N micro seconds - ((N * ( (TCLK_RATE / 1,000,000)) / 64) -+* -+*******************************************************************************/ -+MV_STATUS mvEthCoalGet(void* pPortHndl, MV_U32* pRxCoal, MV_U32* pTxCoal) -+{ -+ MV_U32 regVal, coal, usec; -+ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ -+ /* get TX Coalescing */ -+ regVal = MV_REG_READ (ETH_TX_FIFO_URGENT_THRESH_REG(pPortCtrl->portNo)); -+ coal = ((regVal & ETH_TX_INTR_COAL_ALL_MASK) >> ETH_TX_INTR_COAL_OFFSET); -+ -+ usec = (coal * 64) / (mvBoardTclkGet() / 1000000); -+ if(pTxCoal != NULL) -+ *pTxCoal = usec; -+ -+ /* Get RX Coalescing */ -+ regVal = MV_REG_READ(ETH_SDMA_CONFIG_REG(pPortCtrl->portNo)); -+ coal = ((regVal & ETH_RX_INTR_COAL_ALL_MASK) >> ETH_RX_INTR_COAL_OFFSET); -+ -+#if (MV_ETH_VERSION >= 2) -+ if(regVal & ETH_RX_INTR_COAL_MSB_MASK) -+ { -+ /* Add MSB */ -+ coal |= (ETH_RX_INTR_COAL_ALL_MASK + 1); -+ } -+#endif /* MV_ETH_VERSION >= 2 */ -+ -+ usec = (coal * 64) / (mvBoardTclkGet() / 1000000); -+ if(pRxCoal != NULL) -+ *pRxCoal = usec; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthMaxRxSizeSet - -+* -+* DESCRIPTION: -+* Change maximum receive size of the port. This configuration will take place -+* after next call of ethPortSetDefaults() function. -+* -+* INPUT: -+* -+* RETURN: -+*******************************************************************************/ -+MV_STATUS mvEthMaxRxSizeSet(void* pPortHndl, int maxRxSize) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ MV_U32 portSerialCtrlReg; -+ -+ if((maxRxSize < 1518) || (maxRxSize & ~ETH_RX_BUFFER_MASK)) -+ return MV_BAD_PARAM; -+ -+ pPortCtrl->portConfig.maxRxPktSize = maxRxSize; -+ -+ portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(pPortCtrl->portNo)); -+ portSerialCtrlReg &= ~ETH_MAX_RX_PACKET_SIZE_MASK; -+ portSerialCtrlReg |= mvEthMruGet(pPortCtrl->portConfig.maxRxPktSize); -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(pPortCtrl->portNo), portSerialCtrlReg); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************/ -+/* MAC Filtering functions */ -+/******************************************************************************/ -+ -+/******************************************************************************* -+* mvEthRxFilterModeSet - Configure Fitering mode of Ethernet port -+* -+* DESCRIPTION: -+* This routine used to free buffers attached to the Rx ring and should -+* be called only when Giga Ethernet port is Down -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet Port handler. -+* MV_BOOL isPromisc - Promiscous mode -+* MV_TRUE - accept all Broadcast, Multicast -+* and Unicast packets -+* MV_FALSE - accept all Broadcast, -+* specially added Multicast and -+* single Unicast packets -+* -+* RETURN: MV_STATUS MV_OK - Success, Other - Failure -+* -+*******************************************************************************/ -+MV_STATUS mvEthRxFilterModeSet(void* pEthPortHndl, MV_BOOL isPromisc) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ int queue; -+ MV_U32 portCfgReg; -+ -+ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); -+ /* Set / Clear UPM bit in port configuration register */ -+ if(isPromisc) -+ { -+ /* Accept all multicast packets to RX default queue */ -+ queue = pPortCtrl->portConfig.rxDefQ; -+ portCfgReg |= ETH_UNICAST_PROMISCUOUS_MODE_MASK; -+ memset(pPortCtrl->mcastCount, 1, sizeof(pPortCtrl->mcastCount)); -+ MV_REG_WRITE(ETH_MAC_ADDR_LOW_REG(pPortCtrl->portNo),0xFFFF); -+ MV_REG_WRITE(ETH_MAC_ADDR_HIGH_REG(pPortCtrl->portNo),0xFFFFFFFF); -+ } -+ else -+ { -+ /* Reject all Multicast addresses */ -+ queue = -1; -+ portCfgReg &= ~ETH_UNICAST_PROMISCUOUS_MODE_MASK; -+ /* Clear all mcastCount */ -+ memset(pPortCtrl->mcastCount, 0, sizeof(pPortCtrl->mcastCount)); -+ } -+ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); -+ -+ /* Set Special Multicast and Other Multicast tables */ -+ mvEthSetSpecialMcastTable(pPortCtrl->portNo, queue); -+ mvEthSetOtherMcastTable(pPortCtrl->portNo, queue); -+ ethSetUcastTable(pPortCtrl->portNo, queue); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthMacAddrSet - This function Set the port Unicast address. -+* -+* DESCRIPTION: -+* This function Set the port Ethernet MAC address. This address -+* will be used to send Pause frames if enabled. Packets with this -+* address will be accepted and dispatched to default RX queue -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet port handler. -+* char* pAddr - Address to be set -+* -+* RETURN: MV_STATUS -+* MV_OK - Success, Other - Faulure -+* -+*******************************************************************************/ -+MV_STATUS mvEthMacAddrSet(void* pPortHndl, unsigned char *pAddr, int queue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ unsigned int macH; -+ unsigned int macL; -+ -+ if(queue >= MV_ETH_RX_Q_NUM) -+ { -+ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", queue); -+ return MV_BAD_PARAM; -+ } -+ -+ if(queue != -1) -+ { -+ macL = (pAddr[4] << 8) | (pAddr[5]); -+ macH = (pAddr[0] << 24)| (pAddr[1] << 16) | -+ (pAddr[2] << 8) | (pAddr[3] << 0); -+ -+ MV_REG_WRITE(ETH_MAC_ADDR_LOW_REG(pPortCtrl->portNo), macL); -+ MV_REG_WRITE(ETH_MAC_ADDR_HIGH_REG(pPortCtrl->portNo), macH); -+ } -+ -+ /* Accept frames of this address */ -+ ethSetUcastAddr(pPortCtrl->portNo, pAddr[5], queue); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthMacAddrGet - This function returns the port Unicast address. -+* -+* DESCRIPTION: -+* This function returns the port Ethernet MAC address. -+* -+* INPUT: -+* int portNo - Ethernet port number. -+* char* pAddr - Pointer where address will be written to -+* -+* RETURN: MV_STATUS -+* MV_OK - Success, Other - Faulure -+* -+*******************************************************************************/ -+MV_STATUS mvEthMacAddrGet(int portNo, unsigned char *pAddr) -+{ -+ unsigned int macH; -+ unsigned int macL; -+ -+ if(pAddr == NULL) -+ { -+ mvOsPrintf("mvEthMacAddrGet: NULL pointer.\n"); -+ return MV_BAD_PARAM; -+ } -+ -+ macH = MV_REG_READ(ETH_MAC_ADDR_HIGH_REG(portNo)); -+ macL = MV_REG_READ(ETH_MAC_ADDR_LOW_REG(portNo)); -+ pAddr[0] = (macH >> 24) & 0xff; -+ pAddr[1] = (macH >> 16) & 0xff; -+ pAddr[2] = (macH >> 8) & 0xff; -+ pAddr[3] = macH & 0xff; -+ pAddr[4] = (macL >> 8) & 0xff; -+ pAddr[5] = macL & 0xff; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthMcastCrc8Get - Calculate CRC8 of MAC address. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* MV_U8* pAddr - Address to calculate CRC-8 -+* -+* RETURN: MV_U8 - CRC-8 of this MAC address -+* -+*******************************************************************************/ -+MV_U8 mvEthMcastCrc8Get(MV_U8* pAddr) -+{ -+ unsigned int macH; -+ unsigned int macL; -+ int macArray[48]; -+ int crc[8]; -+ int i; -+ unsigned char crcResult = 0; -+ -+ /* Calculate CRC-8 out of the given address */ -+ macH = (pAddr[0] << 8) | (pAddr[1]); -+ macL = (pAddr[2] << 24)| (pAddr[3] << 16) | -+ (pAddr[4] << 8) | (pAddr[5] << 0); -+ -+ for(i=0; i<32; i++) -+ macArray[i] = (macL >> i) & 0x1; -+ -+ for(i=32; i<48; i++) -+ macArray[i] = (macH >> (i - 32)) & 0x1; -+ -+ crc[0] = macArray[45] ^ macArray[43] ^ macArray[40] ^ macArray[39] ^ -+ macArray[35] ^ macArray[34] ^ macArray[31] ^ macArray[30] ^ -+ macArray[28] ^ macArray[23] ^ macArray[21] ^ macArray[19] ^ -+ macArray[18] ^ macArray[16] ^ macArray[14] ^ macArray[12] ^ -+ macArray[8] ^ macArray[7] ^ macArray[6] ^ macArray[0]; -+ -+ crc[1] = macArray[46] ^ macArray[45] ^ macArray[44] ^ macArray[43] ^ -+ macArray[41] ^ macArray[39] ^ macArray[36] ^ macArray[34] ^ -+ macArray[32] ^ macArray[30] ^ macArray[29] ^ macArray[28] ^ -+ macArray[24] ^ macArray[23] ^ macArray[22] ^ macArray[21] ^ -+ macArray[20] ^ macArray[18] ^ macArray[17] ^ macArray[16] ^ -+ macArray[15] ^ macArray[14] ^ macArray[13] ^ macArray[12] ^ -+ macArray[9] ^ macArray[6] ^ macArray[1] ^ macArray[0]; -+ -+ crc[2] = macArray[47] ^ macArray[46] ^ macArray[44] ^ macArray[43] ^ -+ macArray[42] ^ macArray[39] ^ macArray[37] ^ macArray[34] ^ -+ macArray[33] ^ macArray[29] ^ macArray[28] ^ macArray[25] ^ -+ macArray[24] ^ macArray[22] ^ macArray[17] ^ macArray[15] ^ -+ macArray[13] ^ macArray[12] ^ macArray[10] ^ macArray[8] ^ -+ macArray[6] ^ macArray[2] ^ macArray[1] ^ macArray[0]; -+ -+ crc[3] = macArray[47] ^ macArray[45] ^ macArray[44] ^ macArray[43] ^ -+ macArray[40] ^ macArray[38] ^ macArray[35] ^ macArray[34] ^ -+ macArray[30] ^ macArray[29] ^ macArray[26] ^ macArray[25] ^ -+ macArray[23] ^ macArray[18] ^ macArray[16] ^ macArray[14] ^ -+ macArray[13] ^ macArray[11] ^ macArray[9] ^ macArray[7] ^ -+ macArray[3] ^ macArray[2] ^ macArray[1]; -+ -+ crc[4] = macArray[46] ^ macArray[45] ^ macArray[44] ^ macArray[41] ^ -+ macArray[39] ^ macArray[36] ^ macArray[35] ^ macArray[31] ^ -+ macArray[30] ^ macArray[27] ^ macArray[26] ^ macArray[24] ^ -+ macArray[19] ^ macArray[17] ^ macArray[15] ^ macArray[14] ^ -+ macArray[12] ^ macArray[10] ^ macArray[8] ^ macArray[4] ^ -+ macArray[3] ^ macArray[2]; -+ -+ crc[5] = macArray[47] ^ macArray[46] ^ macArray[45] ^ macArray[42] ^ -+ macArray[40] ^ macArray[37] ^ macArray[36] ^ macArray[32] ^ -+ macArray[31] ^ macArray[28] ^ macArray[27] ^ macArray[25] ^ -+ macArray[20] ^ macArray[18] ^ macArray[16] ^ macArray[15] ^ -+ macArray[13] ^ macArray[11] ^ macArray[9] ^ macArray[5] ^ -+ macArray[4] ^ macArray[3]; -+ -+ crc[6] = macArray[47] ^ macArray[46] ^ macArray[43] ^ macArray[41] ^ -+ macArray[38] ^ macArray[37] ^ macArray[33] ^ macArray[32] ^ -+ macArray[29] ^ macArray[28] ^ macArray[26] ^ macArray[21] ^ -+ macArray[19] ^ macArray[17] ^ macArray[16] ^ macArray[14] ^ -+ macArray[12] ^ macArray[10] ^ macArray[6] ^ macArray[5] ^ -+ macArray[4]; -+ -+ crc[7] = macArray[47] ^ macArray[44] ^ macArray[42] ^ macArray[39] ^ -+ macArray[38] ^ macArray[34] ^ macArray[33] ^ macArray[30] ^ -+ macArray[29] ^ macArray[27] ^ macArray[22] ^ macArray[20] ^ -+ macArray[18] ^ macArray[17] ^ macArray[15] ^ macArray[13] ^ -+ macArray[11] ^ macArray[7] ^ macArray[6] ^ macArray[5]; -+ -+ for(i=0; i<8; i++) -+ crcResult = crcResult | (crc[i] << i); -+ -+ return crcResult; -+} -+/******************************************************************************* -+* mvEthMcastAddrSet - Multicast address settings. -+* -+* DESCRIPTION: -+* This API controls the MV device MAC multicast support. -+* The MV device supports multicast using two tables: -+* 1) Special Multicast Table for MAC addresses of the form -+* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). -+* The MAC DA[7:0] bits are used as a pointer to the Special Multicast -+* Table entries in the DA-Filter table. -+* In this case, the function calls ethPortSmcAddr() routine to set the -+* Special Multicast Table. -+* 2) Other Multicast Table for multicast of another type. A CRC-8bit -+* is used as an index to the Other Multicast Table entries in the -+* DA-Filter table. -+* In this case, the function calculates the CRC-8bit value and calls -+* ethPortOmcAddr() routine to set the Other Multicast Table. -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet port handler. -+* MV_U8* pAddr - Address to be set -+* int queue - RX queue to capture all packets with this -+* Multicast MAC address. -+* -1 means delete this Multicast address. -+* -+* RETURN: MV_STATUS -+* MV_TRUE - Success, Other - Failure -+* -+*******************************************************************************/ -+MV_STATUS mvEthMcastAddrSet(void* pPortHndl, MV_U8 *pAddr, int queue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ unsigned char crcResult = 0; -+ -+ if(queue >= MV_ETH_RX_Q_NUM) -+ { -+ mvOsPrintf("ethPort %d: RX queue #%d is out of range\n", -+ pPortCtrl->portNo, queue); -+ return MV_BAD_PARAM; -+ } -+ -+ if((pAddr[0] == 0x01) && -+ (pAddr[1] == 0x00) && -+ (pAddr[2] == 0x5E) && -+ (pAddr[3] == 0x00) && -+ (pAddr[4] == 0x00)) -+ { -+ ethSetSpecialMcastAddr(pPortCtrl->portNo, pAddr[5], queue); -+ } -+ else -+ { -+ crcResult = mvEthMcastCrc8Get(pAddr); -+ -+ /* Check Add counter for this CRC value */ -+ if(queue == -1) -+ { -+ if(pPortCtrl->mcastCount[crcResult] == 0) -+ { -+ mvOsPrintf("ethPort #%d: No valid Mcast for crc8=0x%02x\n", -+ pPortCtrl->portNo, (unsigned)crcResult); -+ return MV_NO_SUCH; -+ } -+ -+ pPortCtrl->mcastCount[crcResult]--; -+ if(pPortCtrl->mcastCount[crcResult] != 0) -+ { -+ mvOsPrintf("ethPort #%d: After delete there are %d valid Mcast for crc8=0x%02x\n", -+ pPortCtrl->portNo, pPortCtrl->mcastCount[crcResult], -+ (unsigned)crcResult); -+ return MV_NO_CHANGE; -+ } -+ } -+ else -+ { -+ pPortCtrl->mcastCount[crcResult]++; -+ if(pPortCtrl->mcastCount[crcResult] > 1) -+ { -+ mvOsPrintf("ethPort #%d: Valid Mcast for crc8=0x%02x already exists\n", -+ pPortCtrl->portNo, (unsigned)crcResult); -+ return MV_NO_CHANGE; -+ } -+ } -+ ethSetOtherMcastAddr(pPortCtrl->portNo, crcResult, queue); -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* ethSetUcastTable - Unicast address settings. -+* -+* DESCRIPTION: -+* Set all entries in the Unicast MAC Table queue==-1 means reject all -+* INPUT: -+* -+* RETURN: -+* -+*******************************************************************************/ -+static void ethSetUcastTable(int portNo, int queue) -+{ -+ int offset; -+ MV_U32 regValue; -+ -+ if(queue == -1) -+ { -+ regValue = 0; -+ } -+ else -+ { -+ regValue = (((0x01 | (queue<<1)) << 0) | -+ ((0x01 | (queue<<1)) << 8) | -+ ((0x01 | (queue<<1)) << 16) | -+ ((0x01 | (queue<<1)) << 24)); -+ } -+ -+ for (offset=0; offset<=0xC; offset+=4) -+ MV_REG_WRITE((ETH_DA_FILTER_UCAST_BASE(portNo) + offset), regValue); -+} -+ -+/******************************************************************************* -+* mvEthSetSpecialMcastTable - Special Multicast address settings. -+* -+* DESCRIPTION: -+* Set all entries to the Special Multicast MAC Table. queue==-1 means reject all -+* INPUT: -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_VOID mvEthSetSpecialMcastTable(int portNo, int queue) -+{ -+ int offset; -+ MV_U32 regValue; -+ -+ if(queue == -1) -+ { -+ regValue = 0; -+ } -+ else -+ { -+ regValue = (((0x01 | (queue<<1)) << 0) | -+ ((0x01 | (queue<<1)) << 8) | -+ ((0x01 | (queue<<1)) << 16) | -+ ((0x01 | (queue<<1)) << 24)); -+ } -+ -+ for (offset=0; offset<=0xFC; offset+=4) -+ { -+ MV_REG_WRITE((ETH_DA_FILTER_SPEC_MCAST_BASE(portNo) + -+ offset), regValue); -+ } -+} -+ -+/******************************************************************************* -+* mvEthSetOtherMcastTable - Other Multicast address settings. -+* -+* DESCRIPTION: -+* Set all entries to the Other Multicast MAC Table. queue==-1 means reject all -+* INPUT: -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_VOID mvEthSetOtherMcastTable(int portNo, int queue) -+{ -+ int offset; -+ MV_U32 regValue; -+ -+ if(queue == -1) -+ { -+ regValue = 0; -+ } -+ else -+ { -+ regValue = (((0x01 | (queue<<1)) << 0) | -+ ((0x01 | (queue<<1)) << 8) | -+ ((0x01 | (queue<<1)) << 16) | -+ ((0x01 | (queue<<1)) << 24)); -+ } -+ -+ for (offset=0; offset<=0xFC; offset+=4) -+ { -+ MV_REG_WRITE((ETH_DA_FILTER_OTH_MCAST_BASE(portNo) + -+ offset), regValue); -+ } -+} -+ -+/******************************************************************************* -+* ethSetUcastAddr - This function Set the port unicast address table -+* -+* DESCRIPTION: -+* This function locates the proper entry in the Unicast table for the -+* specified MAC nibble and sets its properties according to function -+* parameters. -+* -+* INPUT: -+* int ethPortNum - Port number. -+* MV_U8 lastNibble - Unicast MAC Address last nibble. -+* int queue - Rx queue number for this MAC address. -+* value "-1" means remove address -+* -+* OUTPUT: -+* This function add/removes MAC addresses from the port unicast address -+* table. -+* -+* RETURN: -+* MV_TRUE is output succeeded. -+* MV_FALSE if option parameter is invalid. -+* -+*******************************************************************************/ -+static MV_BOOL ethSetUcastAddr(int portNo, MV_U8 lastNibble, int queue) -+{ -+ unsigned int unicastReg; -+ unsigned int tblOffset; -+ unsigned int regOffset; -+ -+ /* Locate the Unicast table entry */ -+ lastNibble = (0xf & lastNibble); -+ tblOffset = (lastNibble / 4) * 4; /* Register offset from unicast table base*/ -+ regOffset = lastNibble % 4; /* Entry offset within the above register */ -+ -+ -+ unicastReg = MV_REG_READ( (ETH_DA_FILTER_UCAST_BASE(portNo) + -+ tblOffset)); -+ -+ -+ if(queue == -1) -+ { -+ /* Clear accepts frame bit at specified unicast DA table entry */ -+ unicastReg &= ~(0xFF << (8*regOffset)); -+ } -+ else -+ { -+ unicastReg &= ~(0xFF << (8*regOffset)); -+ unicastReg |= ((0x01 | (queue<<1)) << (8*regOffset)); -+ } -+ MV_REG_WRITE( (ETH_DA_FILTER_UCAST_BASE(portNo) + tblOffset), -+ unicastReg); -+ -+ return MV_TRUE; -+} -+ -+/******************************************************************************* -+* ethSetSpecialMcastAddr - Special Multicast address settings. -+* -+* DESCRIPTION: -+* This routine controls the MV device special MAC multicast support. -+* The Special Multicast Table for MAC addresses supports MAC of the form -+* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). -+* The MAC DA[7:0] bits are used as a pointer to the Special Multicast -+* Table entries in the DA-Filter table. -+* This function set the Special Multicast Table appropriate entry -+* according to the argument given. -+* -+* INPUT: -+* int ethPortNum Port number. -+* unsigned char mcByte Multicast addr last byte (MAC DA[7:0] bits). -+* int queue Rx queue number for this MAC address. -+* int option 0 = Add, 1 = remove address. -+* -+* OUTPUT: -+* See description. -+* -+* RETURN: -+* MV_TRUE is output succeeded. -+* MV_FALSE if option parameter is invalid. -+* -+*******************************************************************************/ -+static MV_BOOL ethSetSpecialMcastAddr(int ethPortNum, MV_U8 lastByte, int queue) -+{ -+ unsigned int smcTableReg; -+ unsigned int tblOffset; -+ unsigned int regOffset; -+ -+ /* Locate the SMC table entry */ -+ tblOffset = (lastByte / 4); /* Register offset from SMC table base */ -+ regOffset = lastByte % 4; /* Entry offset within the above register */ -+ -+ smcTableReg = MV_REG_READ((ETH_DA_FILTER_SPEC_MCAST_BASE(ethPortNum) + tblOffset*4)); -+ -+ if(queue == -1) -+ { -+ /* Clear accepts frame bit at specified Special DA table entry */ -+ smcTableReg &= ~(0xFF << (8 * regOffset)); -+ } -+ else -+ { -+ smcTableReg &= ~(0xFF << (8 * regOffset)); -+ smcTableReg |= ((0x01 | (queue<<1)) << (8 * regOffset)); -+ } -+ MV_REG_WRITE((ETH_DA_FILTER_SPEC_MCAST_BASE(ethPortNum) + -+ tblOffset*4), smcTableReg); -+ -+ return MV_TRUE; -+} -+ -+/******************************************************************************* -+* ethSetOtherMcastAddr - Multicast address settings. -+* -+* DESCRIPTION: -+* This routine controls the MV device Other MAC multicast support. -+* The Other Multicast Table is used for multicast of another type. -+* A CRC-8bit is used as an index to the Other Multicast Table entries -+* in the DA-Filter table. -+* The function gets the CRC-8bit value from the calling routine and -+* set the Other Multicast Table appropriate entry according to the -+* CRC-8 argument given. -+* -+* INPUT: -+* int ethPortNum Port number. -+* MV_U8 crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1). -+* int queue Rx queue number for this MAC address. -+* -+* OUTPUT: -+* See description. -+* -+* RETURN: -+* MV_TRUE is output succeeded. -+* MV_FALSE if option parameter is invalid. -+* -+*******************************************************************************/ -+static MV_BOOL ethSetOtherMcastAddr(int ethPortNum, MV_U8 crc8, int queue) -+{ -+ unsigned int omcTableReg; -+ unsigned int tblOffset; -+ unsigned int regOffset; -+ -+ /* Locate the OMC table entry */ -+ tblOffset = (crc8 / 4) * 4; /* Register offset from OMC table base */ -+ regOffset = crc8 % 4; /* Entry offset within the above register */ -+ -+ omcTableReg = MV_REG_READ( -+ (ETH_DA_FILTER_OTH_MCAST_BASE(ethPortNum) + tblOffset)); -+ -+ if(queue == -1) -+ { -+ /* Clear accepts frame bit at specified Other DA table entry */ -+ omcTableReg &= ~(0xFF << (8 * regOffset)); -+ } -+ else -+ { -+ omcTableReg &= ~(0xFF << (8 * regOffset)); -+ omcTableReg |= ((0x01 | (queue<<1)) << (8 * regOffset)); -+ } -+ -+ MV_REG_WRITE((ETH_DA_FILTER_OTH_MCAST_BASE(ethPortNum) + tblOffset), -+ omcTableReg); -+ -+ return MV_TRUE; -+} -+ -+ -+/******************************************************************************/ -+/* MIB Counters functions */ -+/******************************************************************************/ -+ -+ -+/******************************************************************************* -+* mvEthMibCounterRead - Read a MIB counter -+* -+* DESCRIPTION: -+* This function reads a MIB counter of a specific ethernet port. -+* NOTE - Read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW or -+* ETH_MIB_GOOD_OCTETS_SENT_LOW counters will return 64 bits value, -+* so pHigh32 pointer should not be NULL in this case. -+* -+* INPUT: -+* int ethPortNum - Ethernet Port number. -+* unsigned int mibOffset - MIB counter offset. -+* -+* OUTPUT: -+* MV_U32* pHigh32 - pointer to place where 32 most significant bits -+* of the counter will be stored. -+* -+* RETURN: -+* 32 low sgnificant bits of MIB counter value. -+* -+*******************************************************************************/ -+MV_U32 mvEthMibCounterRead(void* pPortHandle, unsigned int mibOffset, -+ MV_U32* pHigh32) -+{ -+ int portNo; -+ MV_U32 valLow32, valHigh32; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ -+ portNo = pPortCtrl->portNo; -+ -+ valLow32 = MV_REG_READ(ETH_MIB_COUNTERS_BASE(portNo) + mibOffset); -+ -+ /* Implement FEr ETH. Erroneous Value when Reading the Upper 32-bits */ -+ /* of a 64-bit MIB Counter. */ -+ if( (mibOffset == ETH_MIB_GOOD_OCTETS_RECEIVED_LOW) || -+ (mibOffset == ETH_MIB_GOOD_OCTETS_SENT_LOW) ) -+ { -+ valHigh32 = MV_REG_READ(ETH_MIB_COUNTERS_BASE(portNo) + mibOffset + 4); -+ if(pHigh32 != NULL) -+ *pHigh32 = valHigh32; -+ } -+ return valLow32; -+} -+ -+/******************************************************************************* -+* mvEthMibCountersClear - Clear all MIB counters -+* -+* DESCRIPTION: -+* This function clears all MIB counters -+* -+* INPUT: -+* int ethPortNum - Ethernet Port number. -+* -+* -+* RETURN: void -+* -+*******************************************************************************/ -+void mvEthMibCountersClear(void* pPortHandle) -+{ -+ int i, portNo; -+ unsigned int dummy; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ -+ portNo = pPortCtrl->portNo; -+ -+ /* Perform dummy reads from MIB counters */ -+ for(i=ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i 0xFF) -+ { -+ mvOsPrintf("eth_%d: tos=0x%x is out of range\n", pPortCtrl->portNo, tos); -+ return -1; -+ } -+ regIdx = mvOsDivide(tos>>2, 10); -+ regOffs = mvOsReminder(tos>>2, 10); -+ -+ regValue = MV_REG_READ(ETH_DIFF_SERV_PRIO_REG(pPortCtrl->portNo, regIdx) ); -+ rxq = (regValue >> (regOffs*3)); -+ rxq &= 0x7; -+ -+ return rxq; -+} -+ -+/******************************************************************************* -+* mvEthTosToRxqSet - Map packets with special TOS value to special RX queue -+* -+* DESCRIPTION: -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* int tos - TOS value in the IP header of the packet -+* int rxq - RX Queue for packets with the configured TOS value -+* Negative value (-1) means no special processing for these packets, -+* so they will be processed as regular packets. -+* -+* RETURN: MV_STATUS -+*******************************************************************************/ -+MV_STATUS mvEthTosToRxqSet(void* pPortHandle, int tos, int rxq) -+{ -+ MV_U32 regValue; -+ int regIdx, regOffs; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ -+ if( (rxq < 0) || (rxq >= MV_ETH_RX_Q_NUM) ) -+ { -+ mvOsPrintf("eth_%d: RX queue #%d is out of range\n", pPortCtrl->portNo, rxq); -+ return MV_BAD_PARAM; -+ } -+ if(tos > 0xFF) -+ { -+ mvOsPrintf("eth_%d: tos=0x%x is out of range\n", pPortCtrl->portNo, tos); -+ return MV_BAD_PARAM; -+ } -+ regIdx = mvOsDivide(tos>>2, 10); -+ regOffs = mvOsReminder(tos>>2, 10); -+ -+ regValue = MV_REG_READ(ETH_DIFF_SERV_PRIO_REG(pPortCtrl->portNo, regIdx) ); -+ regValue &= ~(0x7 << (regOffs*3)); -+ regValue |= (rxq << (regOffs*3)); -+ -+ MV_REG_WRITE(ETH_DIFF_SERV_PRIO_REG(pPortCtrl->portNo, regIdx), regValue); -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthVlanPrioRxQueue - Configure RX queue to capture VLAN tagged packets with -+* special priority bits [0-2] -+* -+* DESCRIPTION: -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* int bpduQueue - Special queue to capture VLAN tagged packets with special -+* priority. -+* Negative value (-1) means no special processing for these packets, -+* so they will be processed as regular packets. -+* -+* RETURN: MV_STATUS -+* MV_OK - Success -+* MV_FAIL - Failed. -+* -+*******************************************************************************/ -+MV_STATUS mvEthVlanPrioRxQueue(void* pPortHandle, int vlanPrio, int vlanPrioQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ MV_U32 vlanPrioReg; -+ -+ if(vlanPrioQueue >= MV_ETH_RX_Q_NUM) -+ { -+ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", vlanPrioQueue); -+ return MV_BAD_PARAM; -+ } -+ if(vlanPrio >= 8) -+ { -+ mvOsPrintf("ethDrv: vlanPrio=%d is out of range\n", vlanPrio); -+ return MV_BAD_PARAM; -+ } -+ -+ vlanPrioReg = MV_REG_READ(ETH_VLAN_TAG_TO_PRIO_REG(pPortCtrl->portNo)); -+ vlanPrioReg &= ~(0x7 << (vlanPrio*3)); -+ vlanPrioReg |= (vlanPrioQueue << (vlanPrio*3)); -+ MV_REG_WRITE(ETH_VLAN_TAG_TO_PRIO_REG(pPortCtrl->portNo), vlanPrioReg); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvEthBpduRxQueue - Configure RX queue to capture BPDU packets. -+* -+* DESCRIPTION: -+* This function defines processing of BPDU packets. -+* BPDU packets can be accepted and captured to one of RX queues -+* or can be processing as regular Multicast packets. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* int bpduQueue - Special queue to capture BPDU packets (DA is equal to -+* 01-80-C2-00-00-00 through 01-80-C2-00-00-FF, -+* except for the Flow-Control Pause packets). -+* Negative value (-1) means no special processing for BPDU, -+* packets so they will be processed as regular Multicast packets. -+* -+* RETURN: MV_STATUS -+* MV_OK - Success -+* MV_FAIL - Failed. -+* -+*******************************************************************************/ -+MV_STATUS mvEthBpduRxQueue(void* pPortHandle, int bpduQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ MV_U32 portCfgReg; -+ MV_U32 portCfgExtReg; -+ -+ if(bpduQueue >= MV_ETH_RX_Q_NUM) -+ { -+ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", bpduQueue); -+ return MV_BAD_PARAM; -+ } -+ -+ portCfgExtReg = MV_REG_READ(ETH_PORT_CONFIG_EXTEND_REG(pPortCtrl->portNo)); -+ -+ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); -+ if(bpduQueue >= 0) -+ { -+ pPortCtrl->portConfig.rxBpduQ = bpduQueue; -+ -+ portCfgReg &= ~ETH_DEF_RX_BPDU_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_BPDU_QUEUE_MASK(pPortCtrl->portConfig.rxBpduQ); -+ -+ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); -+ -+ portCfgExtReg |= ETH_CAPTURE_SPAN_BPDU_ENABLE_MASK; -+ } -+ else -+ { -+ pPortCtrl->portConfig.rxBpduQ = -1; -+ /* no special processing for BPDU packets */ -+ portCfgExtReg &= (~ETH_CAPTURE_SPAN_BPDU_ENABLE_MASK); -+ } -+ -+ MV_REG_WRITE(ETH_PORT_CONFIG_EXTEND_REG(pPortCtrl->portNo), portCfgExtReg); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvEthArpRxQueue - Configure RX queue to capture ARP packets. -+* -+* DESCRIPTION: -+* This function defines processing of ARP (type=0x0806) packets. -+* ARP packets can be accepted and captured to one of RX queues -+* or can be processed as other Broadcast packets. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* int arpQueue - Special queue to capture ARP packets (type=0x806). -+* Negative value (-1) means discard ARP packets -+* -+* RETURN: MV_STATUS -+* MV_OK - Success -+* MV_FAIL - Failed. -+* -+*******************************************************************************/ -+MV_STATUS mvEthArpRxQueue(void* pPortHandle, int arpQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ MV_U32 portCfgReg; -+ -+ if(arpQueue >= MV_ETH_RX_Q_NUM) -+ { -+ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", arpQueue); -+ return MV_BAD_PARAM; -+ } -+ -+ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); -+ -+ if(arpQueue >= 0) -+ { -+ pPortCtrl->portConfig.rxArpQ = arpQueue; -+ portCfgReg &= ~ETH_DEF_RX_ARP_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_ARP_QUEUE_MASK(pPortCtrl->portConfig.rxArpQ); -+ -+ portCfgReg &= (~ETH_REJECT_ARP_BCAST_MASK); -+ } -+ else -+ { -+ pPortCtrl->portConfig.rxArpQ = -1; -+ portCfgReg |= ETH_REJECT_ARP_BCAST_MASK; -+ } -+ -+ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvEthTcpRxQueue - Configure RX queue to capture TCP packets. -+* -+* DESCRIPTION: -+* This function defines processing of TCP packets. -+* TCP packets can be accepted and captured to one of RX queues -+* or can be processed as regular Unicast packets. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* int tcpQueue - Special queue to capture TCP packets. Value "-1" -+* means no special processing for TCP packets, -+* so they will be processed as regular -+* -+* RETURN: MV_STATUS -+* MV_OK - Success -+* MV_FAIL - Failed. -+* -+*******************************************************************************/ -+MV_STATUS mvEthTcpRxQueue(void* pPortHandle, int tcpQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ MV_U32 portCfgReg; -+ -+ if(tcpQueue >= MV_ETH_RX_Q_NUM) -+ { -+ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", tcpQueue); -+ return MV_BAD_PARAM; -+ } -+ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); -+ -+ if(tcpQueue >= 0) -+ { -+ pPortCtrl->portConfig.rxTcpQ = tcpQueue; -+ portCfgReg &= ~ETH_DEF_RX_TCP_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_TCP_QUEUE_MASK(pPortCtrl->portConfig.rxTcpQ); -+ -+ portCfgReg |= ETH_CAPTURE_TCP_FRAMES_ENABLE_MASK; -+ } -+ else -+ { -+ pPortCtrl->portConfig.rxTcpQ = -1; -+ portCfgReg &= (~ETH_CAPTURE_TCP_FRAMES_ENABLE_MASK); -+ } -+ -+ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvEthUdpRxQueue - Configure RX queue to capture UDP packets. -+* -+* DESCRIPTION: -+* This function defines processing of UDP packets. -+* TCP packets can be accepted and captured to one of RX queues -+* or can be processed as regular Unicast packets. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* int udpQueue - Special queue to capture UDP packets. Value "-1" -+* means no special processing for UDP packets, -+* so they will be processed as regular -+* -+* RETURN: MV_STATUS -+* MV_OK - Success -+* MV_FAIL - Failed. -+* -+*******************************************************************************/ -+MV_STATUS mvEthUdpRxQueue(void* pPortHandle, int udpQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ MV_U32 portCfgReg; -+ -+ if(udpQueue >= MV_ETH_RX_Q_NUM) -+ { -+ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", udpQueue); -+ return MV_BAD_PARAM; -+ } -+ -+ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); -+ -+ if(udpQueue >= 0) -+ { -+ pPortCtrl->portConfig.rxUdpQ = udpQueue; -+ portCfgReg &= ~ETH_DEF_RX_UDP_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_UDP_QUEUE_MASK(pPortCtrl->portConfig.rxUdpQ); -+ -+ portCfgReg |= ETH_CAPTURE_UDP_FRAMES_ENABLE_MASK; -+ } -+ else -+ { -+ pPortCtrl->portConfig.rxUdpQ = -1; -+ portCfgReg &= ~ETH_CAPTURE_UDP_FRAMES_ENABLE_MASK; -+ } -+ -+ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************/ -+/* Speed, Duplex, FlowControl routines */ -+/******************************************************************************/ -+ -+/******************************************************************************* -+* mvEthSpeedDuplexSet - Set Speed and Duplex of the port. -+* -+* DESCRIPTION: -+* This function configure the port to work with desirable Duplex and Speed. -+* Changing of these parameters are allowed only when port is disabled. -+* This function disable the port if was enabled, change duplex and speed -+* and, enable the port back if needed. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* ETH_PORT_SPEED speed - Speed of the port. -+* ETH_PORT_SPEED duplex - Duplex of the port. -+* -+* RETURN: MV_STATUS -+* MV_OK - Success -+* MV_OUT_OF_RANGE - Failed. Port is out of valid range -+* MV_NOT_FOUND - Failed. Port is not initialized. -+* MV_BAD_PARAM - Input parameters (speed/duplex) in conflict. -+* MV_BAD_VALUE - Value of one of input parameters (speed, duplex) -+* is not valid -+* -+*******************************************************************************/ -+MV_STATUS mvEthSpeedDuplexSet(void* pPortHandle, MV_ETH_PORT_SPEED speed, -+ MV_ETH_PORT_DUPLEX duplex) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ int port = pPortCtrl->portNo; -+ MV_U32 portSerialCtrlReg; -+ -+ if( (port < 0) || (port >= (int)mvCtrlEthMaxPortGet()) ) -+ return MV_OUT_OF_RANGE; -+ -+ pPortCtrl = ethPortCtrl[port]; -+ if(pPortCtrl == NULL) -+ return MV_NOT_FOUND; -+ -+ /* Check validity */ -+ if( (speed == MV_ETH_SPEED_1000) && (duplex == MV_ETH_DUPLEX_HALF) ) -+ return MV_BAD_PARAM; -+ -+ portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port)); -+ /* Set Speed */ -+ switch(speed) -+ { -+ case MV_ETH_SPEED_AN: -+ portSerialCtrlReg &= ~ETH_DISABLE_SPEED_AUTO_NEG_MASK; -+ break; -+ -+ case MV_ETH_SPEED_10: -+ portSerialCtrlReg |= ETH_DISABLE_SPEED_AUTO_NEG_MASK; -+ portSerialCtrlReg &= ~ETH_SET_GMII_SPEED_1000_MASK; -+ portSerialCtrlReg &= ~ETH_SET_MII_SPEED_100_MASK; -+ break; -+ -+ case MV_ETH_SPEED_100: -+ portSerialCtrlReg |= ETH_DISABLE_SPEED_AUTO_NEG_MASK; -+ portSerialCtrlReg &= ~ETH_SET_GMII_SPEED_1000_MASK; -+ portSerialCtrlReg |= ETH_SET_MII_SPEED_100_MASK; -+ break; -+ -+ case MV_ETH_SPEED_1000: -+ portSerialCtrlReg |= ETH_DISABLE_SPEED_AUTO_NEG_MASK; -+ portSerialCtrlReg |= ETH_SET_GMII_SPEED_1000_MASK; -+ break; -+ -+ default: -+ mvOsPrintf("ethDrv: Unexpected Speed value %d\n", speed); -+ return MV_BAD_VALUE; -+ } -+ /* Set duplex */ -+ switch(duplex) -+ { -+ case MV_ETH_DUPLEX_AN: -+ portSerialCtrlReg &= ~ETH_DISABLE_DUPLEX_AUTO_NEG_MASK; -+ break; -+ -+ case MV_ETH_DUPLEX_HALF: -+ portSerialCtrlReg |= ETH_DISABLE_DUPLEX_AUTO_NEG_MASK; -+ portSerialCtrlReg &= ~ETH_SET_FULL_DUPLEX_MASK; -+ break; -+ -+ case MV_ETH_DUPLEX_FULL: -+ portSerialCtrlReg |= ETH_DISABLE_DUPLEX_AUTO_NEG_MASK; -+ portSerialCtrlReg |= ETH_SET_FULL_DUPLEX_MASK; -+ break; -+ -+ default: -+ mvOsPrintf("ethDrv: Unexpected Duplex value %d\n", duplex); -+ return MV_BAD_VALUE; -+ } -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(port), portSerialCtrlReg); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthFlowCtrlSet - Set Flow Control of the port. -+* -+* DESCRIPTION: -+* This function configure the port to work with desirable Duplex and -+* Speed. Changing of these parameters are allowed only when port is -+* disabled. This function disable the port if was enabled, change -+* duplex and speed and, enable the port back if needed. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* MV_ETH_PORT_FC flowControl - Flow control of the port. -+* -+* RETURN: MV_STATUS -+* MV_OK - Success -+* MV_OUT_OF_RANGE - Failed. Port is out of valid range -+* MV_NOT_FOUND - Failed. Port is not initialized. -+* MV_BAD_VALUE - Value flowControl parameters is not valid -+* -+*******************************************************************************/ -+MV_STATUS mvEthFlowCtrlSet(void* pPortHandle, MV_ETH_PORT_FC flowControl) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ int port = pPortCtrl->portNo; -+ MV_U32 portSerialCtrlReg; -+ -+ if( (port < 0) || (port >= (int)mvCtrlEthMaxPortGet() ) ) -+ return MV_OUT_OF_RANGE; -+ -+ pPortCtrl = ethPortCtrl[port]; -+ if(pPortCtrl == NULL) -+ return MV_NOT_FOUND; -+ -+ portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port)); -+ switch(flowControl) -+ { -+ case MV_ETH_FC_AN_ADV_DIS: -+ portSerialCtrlReg &= ~ETH_DISABLE_FC_AUTO_NEG_MASK; -+ portSerialCtrlReg &= ~ETH_ADVERTISE_SYM_FC_MASK; -+ break; -+ -+ case MV_ETH_FC_AN_ADV_SYM: -+ portSerialCtrlReg &= ~ETH_DISABLE_FC_AUTO_NEG_MASK; -+ portSerialCtrlReg |= ETH_ADVERTISE_SYM_FC_MASK; -+ break; -+ -+ case MV_ETH_FC_DISABLE: -+ portSerialCtrlReg |= ETH_DISABLE_FC_AUTO_NEG_MASK; -+ portSerialCtrlReg &= ~ETH_SET_FLOW_CTRL_MASK; -+ break; -+ -+ case MV_ETH_FC_ENABLE: -+ portSerialCtrlReg |= ETH_DISABLE_FC_AUTO_NEG_MASK; -+ portSerialCtrlReg |= ETH_SET_FLOW_CTRL_MASK; -+ break; -+ -+ default: -+ mvOsPrintf("ethDrv: Unexpected FlowControl value %d\n", flowControl); -+ return MV_BAD_VALUE; -+ } -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(port), portSerialCtrlReg); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthHeaderModeSet - Set port header mode. -+* -+* DESCRIPTION: -+* This function configures the port to work in Marvell-Header mode. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* MV_ETH_HEADER_MODE headerMode - The header mode to set the port in. -+* -+* RETURN: MV_STATUS -+* MV_OK - Success -+* MV_NOT_SUPPORTED- Feature not supported. -+* MV_OUT_OF_RANGE - Failed. Port is out of valid range -+* MV_NOT_FOUND - Failed. Port is not initialized. -+* MV_BAD_VALUE - Value of headerMode or numRxQueue parameter is not valid. -+* -+*******************************************************************************/ -+MV_STATUS mvEthHeaderModeSet(void* pPortHandle, MV_ETH_HEADER_MODE headerMode) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ int port = pPortCtrl->portNo; -+ MV_U32 mvHeaderReg; -+ MV_U32 numRxQ = MV_ETH_RX_Q_NUM; -+ -+ if((port < 0) || (port >= mvCtrlEthMaxPortGet())) -+ return MV_OUT_OF_RANGE; -+ -+ pPortCtrl = ethPortCtrl[port]; -+ if(pPortCtrl == NULL) -+ return MV_NOT_FOUND; -+ -+ mvHeaderReg = MV_REG_READ(ETH_PORT_MARVELL_HEADER_REG(port)); -+ /* Disable header mode. */ -+ mvHeaderReg &= ~ETH_MVHDR_EN_MASK; -+ -+ if(headerMode != MV_ETH_DISABLE_HEADER_MODE) -+ { -+ /* Enable Header mode. */ -+ mvHeaderReg |= ETH_MVHDR_EN_MASK; -+ -+ /* Clear DA-Prefix & MHMask fields.*/ -+ mvHeaderReg &= ~(ETH_MVHDR_DAPREFIX_MASK | ETH_MVHDR_MHMASK_MASK); -+ -+ if(numRxQ > 1) -+ { -+ switch (headerMode) -+ { -+ case(MV_ETH_ENABLE_HEADER_MODE_PRI_2_1): -+ mvHeaderReg |= ETH_MVHDR_DAPREFIX_PRI_1_2; -+ break; -+ case(MV_ETH_ENABLE_HEADER_MODE_PRI_DBNUM): -+ mvHeaderReg |= ETH_MVHDR_DAPREFIX_DBNUM_PRI; -+ break; -+ case(MV_ETH_ENABLE_HEADER_MODE_PRI_SPID): -+ mvHeaderReg |= ETH_MVHDR_DAPREFIX_SPID_PRI; -+ break; -+ default: -+ break; -+ } -+ -+ switch (numRxQ) -+ { -+ case (4): -+ mvHeaderReg |= ETH_MVHDR_MHMASK_4_QUEUE; -+ break; -+ case (8): -+ mvHeaderReg |= ETH_MVHDR_MHMASK_8_QUEUE; -+ break; -+ default: -+ break; -+ } -+ } -+ } -+ -+ MV_REG_WRITE(ETH_PORT_MARVELL_HEADER_REG(port), mvHeaderReg); -+ -+ return MV_OK; -+} -+ -+#if (MV_ETH_VERSION >= 4) -+/******************************************************************************* -+* mvEthEjpModeSet - Enable / Disable EJP policy for TX. -+* -+* DESCRIPTION: -+* This function -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* MV_BOOL TRUE - enable EJP mode -+* FALSE - disable EJP mode -+* -+* OUTPUT: MV_STATUS -+* MV_OK - Success -+* Other - Failure -+* -+* RETURN: None. -+* -+*******************************************************************************/ -+MV_STATUS mvEthEjpModeSet(void* pPortHandle, int mode) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ int port = pPortCtrl->portNo; -+ -+ if((port < 0) || (port >= mvCtrlEthMaxPortGet())) -+ return MV_OUT_OF_RANGE; -+ -+ pPortCtrl = ethPortCtrl[port]; -+ if(pPortCtrl == NULL) -+ return MV_NOT_FOUND; -+ -+ pPortCtrl->portConfig.ejpMode = mode; -+ if(mode) -+ { -+ /* EJP enabled */ -+ MV_REG_WRITE(ETH_TXQ_CMD_1_REG(port), ETH_TX_EJP_ENABLE_MASK); -+ } -+ else -+ { -+ /* EJP disabled */ -+ MV_REG_WRITE(ETH_TXQ_CMD_1_REG(port), 0); -+ } -+ mvOsPrintf("eth_%d: EJP %s - ETH_TXQ_CMD_1_REG: 0x%x = 0x%08x\n", -+ port, mode ? "Enabled" : "Disabled", ETH_TXQ_CMD_1_REG(port), -+ MV_REG_READ(ETH_TXQ_CMD_1_REG(port))); -+ -+ return MV_OK; -+} -+#endif /* MV_ETH_VERSION >= 4 */ -+ -+/******************************************************************************* -+* mvEthStatusGet - Get major properties of the port . -+* -+* DESCRIPTION: -+* This function get major properties of the port (link, speed, duplex, -+* flowControl, etc) and return them using the single structure. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* -+* OUTPUT: -+* MV_ETH_PORT_STATUS* pStatus - Pointer to structure, were port status -+* will be placed. -+* -+* RETURN: None. -+* -+*******************************************************************************/ -+void mvEthStatusGet(void* pPortHandle, MV_ETH_PORT_STATUS* pStatus) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ int port = pPortCtrl->portNo; -+ -+ MV_U32 regValue; -+ -+ regValue = MV_REG_READ( ETH_PORT_STATUS_REG(port) ); -+ -+ if(regValue & ETH_GMII_SPEED_1000_MASK) -+ pStatus->speed = MV_ETH_SPEED_1000; -+ else if(regValue & ETH_MII_SPEED_100_MASK) -+ pStatus->speed = MV_ETH_SPEED_100; -+ else -+ pStatus->speed = MV_ETH_SPEED_10; -+ -+ if(regValue & ETH_LINK_UP_MASK) -+ pStatus->isLinkUp = MV_TRUE; -+ else -+ pStatus->isLinkUp = MV_FALSE; -+ -+ if(regValue & ETH_FULL_DUPLEX_MASK) -+ pStatus->duplex = MV_ETH_DUPLEX_FULL; -+ else -+ pStatus->duplex = MV_ETH_DUPLEX_HALF; -+ -+ -+ if(regValue & ETH_ENABLE_RCV_FLOW_CTRL_MASK) -+ pStatus->flowControl = MV_ETH_FC_ENABLE; -+ else -+ pStatus->flowControl = MV_ETH_FC_DISABLE; -+} -+ -+ -+/******************************************************************************/ -+/* PHY Control Functions */ -+/******************************************************************************/ -+ -+ -+/******************************************************************************* -+* mvEthPhyAddrSet - Set the ethernet port PHY address. -+* -+* DESCRIPTION: -+* This routine set the ethernet port PHY address according to given -+* parameter. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* int phyAddr - PHY address -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+void mvEthPhyAddrSet(void* pPortHandle, int phyAddr) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ int port = pPortCtrl->portNo; -+ unsigned int regData; -+ -+ regData = MV_REG_READ(ETH_PHY_ADDR_REG(port)); -+ -+ regData &= ~ETH_PHY_ADDR_MASK; -+ regData |= phyAddr; -+ -+ MV_REG_WRITE(ETH_PHY_ADDR_REG(port), regData); -+ -+ return; -+} -+ -+/******************************************************************************* -+* mvEthPhyAddrGet - Get the ethernet port PHY address. -+* -+* DESCRIPTION: -+* This routine returns the given ethernet port PHY address. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* -+* -+* RETURN: int - PHY address. -+* -+*******************************************************************************/ -+int mvEthPhyAddrGet(void* pPortHandle) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ int port = pPortCtrl->portNo; -+ unsigned int regData; -+ -+ regData = MV_REG_READ(ETH_PHY_ADDR_REG(port)); -+ -+ return ((regData >> (5 * port)) & 0x1f); -+} -+ -+/******************************************************************************/ -+/* Descriptor handling Functions */ -+/******************************************************************************/ -+ -+/******************************************************************************* -+* etherInitRxDescRing - Curve a Rx chain desc list and buffer in memory. -+* -+* DESCRIPTION: -+* This function prepares a Rx chained list of descriptors and packet -+* buffers in a form of a ring. The routine must be called after port -+* initialization routine and before port start routine. -+* The Ethernet SDMA engine uses CPU bus addresses to access the various -+* devices in the system (i.e. DRAM). This function uses the ethernet -+* struct 'virtual to physical' routine (set by the user) to set the ring -+* with physical addresses. -+* -+* INPUT: -+* ETH_QUEUE_CTRL *pEthPortCtrl Ethernet Port Control srtuct. -+* int rxQueue Number of Rx queue. -+* int rxDescNum Number of Rx descriptors -+* MV_U8* rxDescBaseAddr Rx descriptors memory area base addr. -+* -+* OUTPUT: -+* The routine updates the Ethernet port control struct with information -+* regarding the Rx descriptors and buffers. -+* -+* RETURN: None -+* -+*******************************************************************************/ -+static void ethInitRxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue) -+{ -+ ETH_RX_DESC *pRxDescBase, *pRxDesc, *pRxPrevDesc; -+ int ix, rxDescNum = pPortCtrl->rxQueueConfig[queue].descrNum; -+ ETH_QUEUE_CTRL *pQueueCtrl = &pPortCtrl->rxQueue[queue]; -+ -+ /* Make sure descriptor address is cache line size aligned */ -+ pRxDescBase = (ETH_RX_DESC*)MV_ALIGN_UP((MV_ULONG)pQueueCtrl->descBuf.bufVirtPtr, -+ CPU_D_CACHE_LINE_SIZE); -+ -+ pRxDesc = (ETH_RX_DESC*)pRxDescBase; -+ pRxPrevDesc = pRxDesc; -+ -+ /* initialize the Rx descriptors ring */ -+ for (ix=0; ixbufSize = 0x0; -+ pRxDesc->byteCnt = 0x0; -+ pRxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; -+ pRxDesc->bufPtr = 0x0; -+ pRxDesc->returnInfo = 0x0; -+ pRxPrevDesc = pRxDesc; -+ if(ix == (rxDescNum-1)) -+ { -+ /* Closing Rx descriptors ring */ -+ pRxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pRxDescBase); -+ } -+ else -+ { -+ pRxDesc = (ETH_RX_DESC*)((MV_ULONG)pRxDesc + ETH_RX_DESC_ALIGNED_SIZE); -+ pRxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pRxDesc); -+ } -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxPrevDesc); -+ } -+ -+ pQueueCtrl->pCurrentDescr = pRxDescBase; -+ pQueueCtrl->pUsedDescr = pRxDescBase; -+ -+ pQueueCtrl->pFirstDescr = pRxDescBase; -+ pQueueCtrl->pLastDescr = pRxDesc; -+ pQueueCtrl->resource = 0; -+} -+ -+void ethResetRxDescRing(void* pPortHndl, int queue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->rxQueue[queue]; -+ ETH_RX_DESC* pRxDesc = (ETH_RX_DESC*)pQueueCtrl->pFirstDescr; -+ -+ pQueueCtrl->resource = 0; -+ if(pQueueCtrl->pFirstDescr != NULL) -+ { -+ while(MV_TRUE) -+ { -+ pRxDesc->bufSize = 0x0; -+ pRxDesc->byteCnt = 0x0; -+ pRxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; -+ pRxDesc->bufPtr = 0x0; -+ pRxDesc->returnInfo = 0x0; -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxDesc); -+ if( (void*)pRxDesc == pQueueCtrl->pLastDescr) -+ break; -+ pRxDesc = RX_NEXT_DESC_PTR(pRxDesc, pQueueCtrl); -+ } -+ pQueueCtrl->pCurrentDescr = pQueueCtrl->pFirstDescr; -+ pQueueCtrl->pUsedDescr = pQueueCtrl->pFirstDescr; -+ -+ /* Update RX Command register */ -+ pPortCtrl->portRxQueueCmdReg |= (1 << queue); -+ -+ /* update HW */ -+ MV_REG_WRITE( ETH_RX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), -+ (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); -+ } -+ else -+ { -+ /* Update RX Command register */ -+ pPortCtrl->portRxQueueCmdReg &= ~(1 << queue); -+ -+ /* update HW */ -+ MV_REG_WRITE( ETH_RX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), 0); -+ } -+} -+ -+/******************************************************************************* -+* etherInitTxDescRing - Curve a Tx chain desc list and buffer in memory. -+* -+* DESCRIPTION: -+* This function prepares a Tx chained list of descriptors and packet -+* buffers in a form of a ring. The routine must be called after port -+* initialization routine and before port start routine. -+* The Ethernet SDMA engine uses CPU bus addresses to access the various -+* devices in the system (i.e. DRAM). This function uses the ethernet -+* struct 'virtual to physical' routine (set by the user) to set the ring -+* with physical addresses. -+* -+* INPUT: -+* ETH_PORT_CTRL *pEthPortCtrl Ethernet Port Control srtuct. -+* int txQueue Number of Tx queue. -+* int txDescNum Number of Tx descriptors -+* int txBuffSize Size of Tx buffer -+* MV_U8* pTxDescBase Tx descriptors memory area base addr. -+* -+* OUTPUT: -+* The routine updates the Ethernet port control struct with information -+* regarding the Tx descriptors and buffers. -+* -+* RETURN: None. -+* -+*******************************************************************************/ -+static void ethInitTxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue) -+{ -+ ETH_TX_DESC *pTxDescBase, *pTxDesc, *pTxPrevDesc; -+ int ix, txDescNum = pPortCtrl->txQueueConfig[queue].descrNum; -+ ETH_QUEUE_CTRL *pQueueCtrl = &pPortCtrl->txQueue[queue]; -+ -+ /* Make sure descriptor address is cache line size aligned */ -+ pTxDescBase = (ETH_TX_DESC*)MV_ALIGN_UP((MV_ULONG)pQueueCtrl->descBuf.bufVirtPtr, -+ CPU_D_CACHE_LINE_SIZE); -+ -+ pTxDesc = (ETH_TX_DESC*)pTxDescBase; -+ pTxPrevDesc = pTxDesc; -+ -+ /* initialize the Tx descriptors ring */ -+ for (ix=0; ixbyteCnt = 0x0000; -+ pTxDesc->L4iChk = 0x0000; -+ pTxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; -+ pTxDesc->bufPtr = 0x0; -+ pTxDesc->returnInfo = 0x0; -+ -+ pTxPrevDesc = pTxDesc; -+ -+ if(ix == (txDescNum-1)) -+ { -+ /* Closing Tx descriptors ring */ -+ pTxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pTxDescBase); -+ } -+ else -+ { -+ pTxDesc = (ETH_TX_DESC*)((MV_ULONG)pTxDesc + ETH_TX_DESC_ALIGNED_SIZE); -+ pTxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pTxDesc); -+ } -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxPrevDesc); -+ } -+ -+ pQueueCtrl->pCurrentDescr = pTxDescBase; -+ pQueueCtrl->pUsedDescr = pTxDescBase; -+ -+ pQueueCtrl->pFirstDescr = pTxDescBase; -+ pQueueCtrl->pLastDescr = pTxDesc; -+ /* Leave one TX descriptor out of use */ -+ pQueueCtrl->resource = txDescNum - 1; -+} -+ -+void ethResetTxDescRing(void* pPortHndl, int queue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->txQueue[queue]; -+ ETH_TX_DESC* pTxDesc = (ETH_TX_DESC*)pQueueCtrl->pFirstDescr; -+ -+ pQueueCtrl->resource = 0; -+ if(pQueueCtrl->pFirstDescr != NULL) -+ { -+ while(MV_TRUE) -+ { -+ pTxDesc->byteCnt = 0x0000; -+ pTxDesc->L4iChk = 0x0000; -+ pTxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; -+ pTxDesc->bufPtr = 0x0; -+ pTxDesc->returnInfo = 0x0; -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxDesc); -+ pQueueCtrl->resource++; -+ if( (void*)pTxDesc == pQueueCtrl->pLastDescr) -+ break; -+ pTxDesc = TX_NEXT_DESC_PTR(pTxDesc, pQueueCtrl); -+ } -+ /* Leave one TX descriptor out of use */ -+ pQueueCtrl->resource--; -+ pQueueCtrl->pCurrentDescr = pQueueCtrl->pFirstDescr; -+ pQueueCtrl->pUsedDescr = pQueueCtrl->pFirstDescr; -+ -+ /* Update TX Command register */ -+ pPortCtrl->portTxQueueCmdReg |= MV_32BIT_LE_FAST(1 << queue); -+ /* update HW */ -+ MV_REG_WRITE( ETH_TX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), -+ (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); -+ } -+ else -+ { -+ /* Update TX Command register */ -+ pPortCtrl->portTxQueueCmdReg &= MV_32BIT_LE_FAST(~(1 << queue)); -+ /* update HW */ -+ MV_REG_WRITE( ETH_TX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), 0 ); -+ } -+} -+ -+/******************************************************************************* -+* ethAllocDescrMemory - Free memory allocated for RX and TX descriptors. -+* -+* DESCRIPTION: -+* This function allocates memory for RX and TX descriptors. -+* - If ETH_DESCR_IN_SRAM defined, allocate memory from SRAM. -+* - If ETH_DESCR_IN_SDRAM defined, allocate memory in SDRAM. -+* -+* INPUT: -+* int size - size of memory should be allocated. -+* -+* RETURN: None -+* -+*******************************************************************************/ -+static MV_U8* ethAllocDescrMemory(ETH_PORT_CTRL* pPortCtrl, int descSize, -+ MV_ULONG* pPhysAddr, MV_U32 *memHandle) -+{ -+ MV_U8* pVirt; -+ -+#if defined(ETH_DESCR_IN_SRAM) -+ if(ethDescInSram == MV_TRUE) -+ pVirt = (char*)mvSramMalloc(descSize, pPhysAddr); -+ else -+#endif /* ETH_DESCR_IN_SRAM */ -+ { -+#ifdef ETH_DESCR_UNCACHED -+ pVirt = (MV_U8*)mvOsIoUncachedMalloc(pPortCtrl->osHandle, descSize, -+ pPhysAddr,memHandle); -+#else -+ pVirt = (MV_U8*)mvOsIoCachedMalloc(pPortCtrl->osHandle, descSize, -+ pPhysAddr, memHandle); -+#endif /* ETH_DESCR_UNCACHED */ -+ } -+ memset(pVirt, 0, descSize); -+ -+ return pVirt; -+} -+ -+/******************************************************************************* -+* ethFreeDescrMemory - Free memory allocated for RX and TX descriptors. -+* -+* DESCRIPTION: -+* This function frees memory allocated for RX and TX descriptors. -+* - If ETH_DESCR_IN_SRAM defined, free memory using gtSramFree() function. -+* - If ETH_DESCR_IN_SDRAM defined, free memory using mvOsFree() function. -+* -+* INPUT: -+* void* pVirtAddr - virtual pointer to memory allocated for RX and TX -+* desriptors. -+* -+* RETURN: None -+* -+*******************************************************************************/ -+void ethFreeDescrMemory(ETH_PORT_CTRL* pPortCtrl, MV_BUF_INFO* pDescBuf) -+{ -+ if( (pDescBuf == NULL) || (pDescBuf->bufVirtPtr == NULL) ) -+ return; -+ -+#if defined(ETH_DESCR_IN_SRAM) -+ if( ethDescInSram ) -+ { -+ mvSramFree(pDescBuf->bufSize, pDescBuf->bufPhysAddr, pDescBuf->bufVirtPtr); -+ return; -+ } -+#endif /* ETH_DESCR_IN_SRAM */ -+ -+#ifdef ETH_DESCR_UNCACHED -+ mvOsIoUncachedFree(pPortCtrl->osHandle, pDescBuf->bufSize, pDescBuf->bufPhysAddr, -+ pDescBuf->bufVirtPtr,pDescBuf->memHandle); -+#else -+ mvOsIoCachedFree(pPortCtrl->osHandle, pDescBuf->bufSize, pDescBuf->bufPhysAddr, -+ pDescBuf->bufVirtPtr,pDescBuf->memHandle); -+#endif /* ETH_DESCR_UNCACHED */ -+} -+ -+/******************************************************************************/ -+/* Other Functions */ -+/******************************************************************************/ -+ -+void mvEthPortPowerUp(int port) -+{ -+ MV_U32 regVal; -+ -+ /* MAC Cause register should be cleared */ -+ MV_REG_WRITE(ETH_UNIT_INTR_CAUSE_REG(port), 0); -+ -+ if (mvBoardIsPortInSgmii(port)) -+ mvEthPortSgmiiConfig(port); -+ -+ /* Cancel Port Reset */ -+ regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)); -+ regVal &= (~ETH_PORT_RESET_MASK); -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal); -+ while( (MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)) & ETH_PORT_RESET_MASK) != 0); -+} -+ -+void mvEthPortPowerDown(int port) -+{ -+ MV_U32 regVal; -+ -+ /* Port must be DISABLED */ -+ regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port)); -+ if( (regVal & ETH_PORT_ENABLE_MASK) != 0) -+ { -+ mvOsPrintf("ethPort #%d: PowerDown - port must be Disabled (PSC=0x%x)\n", -+ port, regVal); -+ return; -+ } -+ -+ /* Port Reset (Read after write the register as a precaution) */ -+ regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)); -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal | ETH_PORT_RESET_MASK); -+ while((MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)) & ETH_PORT_RESET_MASK) == 0); -+} -+ -+static void mvEthPortSgmiiConfig(int port) -+{ -+ MV_U32 regVal; -+ -+ regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)); -+ -+ regVal |= (ETH_SGMII_MODE_MASK /*| ETH_INBAND_AUTO_NEG_ENABLE_MASK */); -+ regVal &= (~ETH_INBAND_AUTO_NEG_BYPASS_MASK); -+ -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal); -+} -+ -+ -+ -+ -+ -+ -+ -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,748 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+/******************************************************************************* -+* mvEthDebug.c - Source file for user friendly debug functions -+* -+* DESCRIPTION: -+* -+* DEPENDENCIES: -+* None. -+* -+*******************************************************************************/ -+ -+#include "mvOs.h" -+#include "mvCommon.h" -+#include "mvTypes.h" -+#include "mv802_3.h" -+#include "mvDebug.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "eth-phy/mvEthPhy.h" -+#include "eth/mvEth.h" -+#include "eth/gbe/mvEthDebug.h" -+ -+/* #define mvOsPrintf printf */ -+ -+void mvEthPortShow(void* pHndl); -+void mvEthQueuesShow(void* pHndl, int rxQueue, int txQueue, int mode); -+ -+/******************************************************************************/ -+/* Debug functions */ -+/******************************************************************************/ -+void ethRxCoal(int port, int usec) -+{ -+ void* pHndl; -+ -+ pHndl = mvEthPortHndlGet(port); -+ if(pHndl != NULL) -+ { -+ mvEthRxCoalSet(pHndl, usec); -+ } -+} -+ -+void ethTxCoal(int port, int usec) -+{ -+ void* pHndl; -+ -+ pHndl = mvEthPortHndlGet(port); -+ if(pHndl != NULL) -+ { -+ mvEthTxCoalSet(pHndl, usec); -+ } -+} -+ -+#if (MV_ETH_VERSION >= 4) -+void ethEjpModeSet(int port, int mode) -+{ -+ void* pHndl; -+ -+ pHndl = mvEthPortHndlGet(port); -+ if(pHndl != NULL) -+ { -+ mvEthEjpModeSet(pHndl, mode); -+ } -+} -+#endif /* (MV_ETH_VERSION >= 4) */ -+ -+void ethBpduRxQ(int port, int bpduQueue) -+{ -+ void* pHndl; -+ -+ pHndl = mvEthPortHndlGet(port); -+ if(pHndl != NULL) -+ { -+ mvEthBpduRxQueue(pHndl, bpduQueue); -+ } -+} -+ -+void ethArpRxQ(int port, int arpQueue) -+{ -+ void* pHndl; -+ -+ pHndl = mvEthPortHndlGet(port); -+ if(pHndl != NULL) -+ { -+ mvEthArpRxQueue(pHndl, arpQueue); -+ } -+} -+ -+void ethTcpRxQ(int port, int tcpQueue) -+{ -+ void* pHndl; -+ -+ pHndl = mvEthPortHndlGet(port); -+ if(pHndl != NULL) -+ { -+ mvEthTcpRxQueue(pHndl, tcpQueue); -+ } -+} -+ -+void ethUdpRxQ(int port, int udpQueue) -+{ -+ void* pHndl; -+ -+ pHndl = mvEthPortHndlGet(port); -+ if(pHndl != NULL) -+ { -+ mvEthUdpRxQueue(pHndl, udpQueue); -+ } -+} -+ -+void ethTxPolicyRegs(int port) -+{ -+ int queue; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)mvEthPortHndlGet(port); -+ -+ if(pPortCtrl == NULL) -+ { -+ return; -+ } -+ mvOsPrintf("Port #%d TX Policy: EJP=%d, TXQs: ", -+ port, pPortCtrl->portConfig.ejpMode); -+ for(queue=0; queuetxQueueConfig[queue].descrNum > 0) -+ mvOsPrintf("%d, ", queue); -+ } -+ mvOsPrintf("\n"); -+ -+ mvOsPrintf("\n\t TX policy Port #%d configuration registers\n", port); -+ -+ mvOsPrintf("ETH_TX_QUEUE_COMMAND_REG : 0x%X = 0x%08x\n", -+ ETH_TX_QUEUE_COMMAND_REG(port), -+ MV_REG_READ( ETH_TX_QUEUE_COMMAND_REG(port) ) ); -+ -+ mvOsPrintf("ETH_TX_FIXED_PRIO_CFG_REG : 0x%X = 0x%08x\n", -+ ETH_TX_FIXED_PRIO_CFG_REG(port), -+ MV_REG_READ( ETH_TX_FIXED_PRIO_CFG_REG(port) ) ); -+ -+ mvOsPrintf("ETH_TX_TOKEN_RATE_CFG_REG : 0x%X = 0x%08x\n", -+ ETH_TX_TOKEN_RATE_CFG_REG(port), -+ MV_REG_READ( ETH_TX_TOKEN_RATE_CFG_REG(port) ) ); -+ -+ mvOsPrintf("ETH_MAX_TRANSMIT_UNIT_REG : 0x%X = 0x%08x\n", -+ ETH_MAX_TRANSMIT_UNIT_REG(port), -+ MV_REG_READ( ETH_MAX_TRANSMIT_UNIT_REG(port) ) ); -+ -+ mvOsPrintf("ETH_TX_TOKEN_BUCKET_SIZE_REG : 0x%X = 0x%08x\n", -+ ETH_TX_TOKEN_BUCKET_SIZE_REG(port), -+ MV_REG_READ( ETH_TX_TOKEN_BUCKET_SIZE_REG(port) ) ); -+ -+ mvOsPrintf("ETH_TX_TOKEN_BUCKET_COUNT_REG : 0x%X = 0x%08x\n", -+ ETH_TX_TOKEN_BUCKET_COUNT_REG(port), -+ MV_REG_READ( ETH_TX_TOKEN_BUCKET_COUNT_REG(port) ) ); -+ -+ for(queue=0; queue> 24) & 0xff), ((macH >> 16) & 0xff), -+ ((macH >> 8) & 0xff), (macH & 0xff), -+ ((macL >> 8) & 0xff), (macL & 0xff) ); -+ -+ for (i=0; i<4; i++) -+ { -+ unicastReg = MV_REG_READ( (ETH_DA_FILTER_UCAST_BASE(port) + i*4)); -+ for(j=0; j<4; j++) -+ { -+ MV_U8 macEntry = (unicastReg >> (8*j)) & 0xFF; -+ -+ mvOsPrintf("%X: %8s, Q = %d\n", i*4+j, -+ (macEntry & BIT0) ? "Accept" : "Reject", (macEntry >> 1) & 0x7); -+ } -+ } -+} -+ -+void ethMcastAdd(int port, char* macStr, int queue) -+{ -+ void* pHndl; -+ MV_U8 macAddr[MV_MAC_ADDR_SIZE]; -+ -+ pHndl = mvEthPortHndlGet(port); -+ if(pHndl != NULL) -+ { -+ mvMacStrToHex(macStr, macAddr); -+ mvEthMcastAddrSet(pHndl, macAddr, queue); -+ } -+} -+ -+void ethPortMcast(int port) -+{ -+ int tblIdx, regIdx; -+ MV_U32 regVal; -+ -+ mvOsPrintf("\n\t Port #%d Special (IP) Multicast table: 01:00:5E:00:00:XX\n\n", -+ port); -+ -+ for(tblIdx=0; tblIdx<(256/4); tblIdx++) -+ { -+ regVal = MV_REG_READ((ETH_DA_FILTER_SPEC_MCAST_BASE(port) + tblIdx*4)); -+ for(regIdx=0; regIdx<4; regIdx++) -+ { -+ if((regVal & (0x01 << (regIdx*8))) != 0) -+ { -+ mvOsPrintf("0x%02X: Accepted, rxQ = %d\n", -+ tblIdx*4+regIdx, ((regVal >> (regIdx*8+1)) & 0x07)); -+ } -+ } -+ } -+ mvOsPrintf("\n\t Port #%d Other Multicast table\n\n", port); -+ for(tblIdx=0; tblIdx<(256/4); tblIdx++) -+ { -+ regVal = MV_REG_READ((ETH_DA_FILTER_OTH_MCAST_BASE(port) + tblIdx*4)); -+ for(regIdx=0; regIdx<4; regIdx++) -+ { -+ if((regVal & (0x01 << (regIdx*8))) != 0) -+ { -+ mvOsPrintf("Crc8=0x%02X: Accepted, rxQ = %d\n", -+ tblIdx*4+regIdx, ((regVal >> (regIdx*8+1)) & 0x07)); -+ } -+ } -+ } -+} -+ -+ -+/* Print status of Ethernet port */ -+void mvEthPortShow(void* pHndl) -+{ -+ MV_U32 regValue, rxCoal, txCoal; -+ int speed, queue, port; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pHndl; -+ -+ port = pPortCtrl->portNo; -+ -+ regValue = MV_REG_READ( ETH_PORT_STATUS_REG(port) ); -+ -+ mvOsPrintf("\n\t ethGiga #%d port Status: 0x%04x = 0x%08x\n\n", -+ port, ETH_PORT_STATUS_REG(port), regValue); -+ -+ mvOsPrintf("descInSram=%d, descSwCoher=%d\n", -+ ethDescInSram, ethDescSwCoher); -+ -+ if(regValue & ETH_GMII_SPEED_1000_MASK) -+ speed = 1000; -+ else if(regValue & ETH_MII_SPEED_100_MASK) -+ speed = 100; -+ else -+ speed = 10; -+ -+ mvEthCoalGet(pPortCtrl, &rxCoal, &txCoal); -+ -+ /* Link, Speed, Duplex, FlowControl */ -+ mvOsPrintf("Link=%s, Speed=%d, Duplex=%s, RxFlowControl=%s", -+ (regValue & ETH_LINK_UP_MASK) ? "UP" : "DOWN", -+ speed, -+ (regValue & ETH_FULL_DUPLEX_MASK) ? "FULL" : "HALF", -+ (regValue & ETH_ENABLE_RCV_FLOW_CTRL_MASK) ? "ENABLE" : "DISABLE"); -+ -+ mvOsPrintf("\n"); -+ -+ mvOsPrintf("RxCoal = %d usec, TxCoal = %d usec\n", -+ rxCoal, txCoal); -+ -+ mvOsPrintf("rxDefQ=%d, arpQ=%d, bpduQ=%d, tcpQ=%d, udpQ=%d\n\n", -+ pPortCtrl->portConfig.rxDefQ, pPortCtrl->portConfig.rxArpQ, -+ pPortCtrl->portConfig.rxBpduQ, -+ pPortCtrl->portConfig.rxTcpQ, pPortCtrl->portConfig.rxUdpQ); -+ -+ /* Print all RX and TX queues */ -+ for(queue=0; queuerxQueue[queue].pFirstDescr, -+ mvEthRxResourceGet(pPortCtrl, queue) ); -+ } -+ mvOsPrintf("\n"); -+ for(queue=0; queuetxQueue[queue].pFirstDescr, -+ mvEthTxResourceGet(pPortCtrl, queue) ); -+ } -+} -+ -+/* Print RX and TX queue of the Ethernet port */ -+void mvEthQueuesShow(void* pHndl, int rxQueue, int txQueue, int mode) -+{ -+ ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL*)pHndl; -+ ETH_QUEUE_CTRL *pQueueCtrl; -+ MV_U32 regValue; -+ ETH_RX_DESC *pRxDescr; -+ ETH_TX_DESC *pTxDescr; -+ int i, port = pPortCtrl->portNo; -+ -+ if( (rxQueue >=0) && (rxQueue < MV_ETH_RX_Q_NUM) ) -+ { -+ pQueueCtrl = &(pPortCtrl->rxQueue[rxQueue]); -+ mvOsPrintf("Port #%d, RX Queue #%d\n\n", port, rxQueue); -+ -+ mvOsPrintf("CURR_RX_DESC_PTR : 0x%X = 0x%08x\n", -+ ETH_RX_CUR_DESC_PTR_REG(port, rxQueue), -+ MV_REG_READ( ETH_RX_CUR_DESC_PTR_REG(port, rxQueue))); -+ -+ -+ if(pQueueCtrl->pFirstDescr != NULL) -+ { -+ mvOsPrintf("pFirstDescr=0x%lx, pLastDescr=0x%lx, numOfResources=%d\n", -+ (MV_ULONG)pQueueCtrl->pFirstDescr, (MV_ULONG)pQueueCtrl->pLastDescr, -+ pQueueCtrl->resource); -+ mvOsPrintf("pCurrDescr: 0x%lx, pUsedDescr: 0x%lx\n", -+ (MV_ULONG)pQueueCtrl->pCurrentDescr, -+ (MV_ULONG)pQueueCtrl->pUsedDescr); -+ -+ if(mode == 1) -+ { -+ pRxDescr = (ETH_RX_DESC*)pQueueCtrl->pFirstDescr; -+ i = 0; -+ do -+ { -+ mvOsPrintf("%3d. desc=%08x (%08x), cmd=%08x, data=%4d, buf=%4d, buf=%08x, pkt=%lx, os=%lx\n", -+ i, (MV_U32)pRxDescr, (MV_U32)ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pRxDescr), -+ pRxDescr->cmdSts, pRxDescr->byteCnt, (MV_U32)pRxDescr->bufSize, -+ (unsigned int)pRxDescr->bufPtr, (MV_ULONG)pRxDescr->returnInfo, -+ ((MV_PKT_INFO*)pRxDescr->returnInfo)->osInfo); -+ -+ ETH_DESCR_INV(pPortCtrl, pRxDescr); -+ pRxDescr = RX_NEXT_DESC_PTR(pRxDescr, pQueueCtrl); -+ i++; -+ } while (pRxDescr != pQueueCtrl->pFirstDescr); -+ } -+ } -+ else -+ mvOsPrintf("RX Queue #%d is NOT CREATED\n", rxQueue); -+ } -+ -+ if( (txQueue >=0) && (txQueue < MV_ETH_TX_Q_NUM) ) -+ { -+ pQueueCtrl = &(pPortCtrl->txQueue[txQueue]); -+ mvOsPrintf("Port #%d, TX Queue #%d\n\n", port, txQueue); -+ -+ regValue = MV_REG_READ( ETH_TX_CUR_DESC_PTR_REG(port, txQueue)); -+ mvOsPrintf("CURR_TX_DESC_PTR : 0x%X = 0x%08x\n", -+ ETH_TX_CUR_DESC_PTR_REG(port, txQueue), regValue); -+ -+ if(pQueueCtrl->pFirstDescr != NULL) -+ { -+ mvOsPrintf("pFirstDescr=0x%lx, pLastDescr=0x%lx, numOfResources=%d\n", -+ (MV_ULONG)pQueueCtrl->pFirstDescr, -+ (MV_ULONG)pQueueCtrl->pLastDescr, -+ pQueueCtrl->resource); -+ mvOsPrintf("pCurrDescr: 0x%lx, pUsedDescr: 0x%lx\n", -+ (MV_ULONG)pQueueCtrl->pCurrentDescr, -+ (MV_ULONG)pQueueCtrl->pUsedDescr); -+ -+ if(mode == 1) -+ { -+ pTxDescr = (ETH_TX_DESC*)pQueueCtrl->pFirstDescr; -+ i = 0; -+ do -+ { -+ mvOsPrintf("%3d. desc=%08x (%08x), cmd=%08x, data=%4d, buf=%08x, pkt=%lx, os=%lx\n", -+ i, (MV_U32)pTxDescr, (MV_U32)ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pTxDescr), -+ pTxDescr->cmdSts, pTxDescr->byteCnt, -+ (MV_U32)pTxDescr->bufPtr, (MV_ULONG)pTxDescr->returnInfo, -+ pTxDescr->returnInfo ? (((MV_PKT_INFO*)pTxDescr->returnInfo)->osInfo) : 0x0); -+ -+ ETH_DESCR_INV(pPortCtrl, pTxDescr); -+ pTxDescr = TX_NEXT_DESC_PTR(pTxDescr, pQueueCtrl); -+ i++; -+ } while (pTxDescr != pQueueCtrl->pFirstDescr); -+ } -+ } -+ else -+ mvOsPrintf("TX Queue #%d is NOT CREATED\n", txQueue); -+ } -+} -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,146 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#ifndef __MV_ETH_DEBUG_H__ -+#define __MV_ETH_DEBUG_H__ -+ -+#if 0 -+/* -+ ** Externs -+ */ -+void ethBpduRxQ(int port, int bpduQueue); -+void ethArpRxQ(int port, int bpduQueue); -+void ethTcpRxQ(int port, int bpduQueue); -+void ethUdpRxQ(int port, int bpduQueue); -+void ethMcastAdd(int port, char* macStr, int queue); -+ -+#ifdef INCLUDE_MULTI_QUEUE -+void ethRxPolicy( int port); -+void ethTxPolicy( int port); -+void ethTxPolDA(int port, char* macStr, int txQ, char* headerHexStr); -+void ethRxPolMode(int port, MV_ETH_PRIO_MODE prioMode); -+void ethRxPolQ(int port, int rxQueue, int rxQuota); -+#endif /* INCLUDE_MULTI_QUEUE */ -+ -+void print_egiga_stat(void *sc, unsigned int port); -+void ethPortStatus (int port); -+void ethPortQueues( int port, int rxQueue, int txQueue, int mode); -+void ethPortMcast(int port); -+void ethPortRegs(int port); -+void ethPortCounters(int port); -+void ethPortRmonCounters(int port); -+void ethRxCoal(int port, int usec); -+void ethTxCoal(int port, int usec); -+ -+void ethRegs(int port); -+void ethClearCounters(int port); -+void ethUcastSet(int port, char* macStr, int queue); -+void ethPortUcastShow(int port); -+ -+#ifdef CONFIG_MV_ETH_HEADER -+void run_com_header(const char *buffer); -+#endif -+ -+#ifdef INCLUDE_MULTI_QUEUE -+void ethRxPolMode(int port, MV_ETH_PRIO_MODE prioMode); -+void ethRxPolQ(int port, int queue, int quota); -+void ethRxPolicy(int port); -+void ethTxPolDef(int port, int txQ, char* headerHexStr); -+void ethTxPolDA(int port, char* macStr, int txQ, char* headerHexStr); -+void ethTxPolicy(int port); -+#endif /* INCLUDE_MULTI_QUEUE */ -+ -+#if (MV_ETH_VERSION >= 4) -+void ethEjpModeSet(int port, int mode) -+#endif -+#endif /* 0 */ -+ -+ -+ -+ -+void ethRxCoal(int port, int usec); -+void ethTxCoal(int port, int usec); -+#if (MV_ETH_VERSION >= 4) -+void ethEjpModeSet(int port, int mode); -+#endif /* (MV_ETH_VERSION >= 4) */ -+ -+void ethBpduRxQ(int port, int bpduQueue); -+void ethArpRxQ(int port, int arpQueue); -+void ethTcpRxQ(int port, int tcpQueue); -+void ethUdpRxQ(int port, int udpQueue); -+void ethTxPolicyRegs(int port); -+void ethPortRegs(int port); -+void ethRegs(int port); -+void ethClearCounters(int port); -+void ethPortCounters(int port); -+void ethPortRmonCounters(int port); -+void ethPortStatus(int port); -+void ethPortQueues(int port, int rxQueue, int txQueue, int mode); -+void ethUcastSet(int port, char* macStr, int queue); -+void ethPortUcastShow(int port); -+void ethMcastAdd(int port, char* macStr, int queue); -+void ethPortMcast(int port); -+void mvEthPortShow(void* pHndl); -+void mvEthQueuesShow(void* pHndl, int rxQueue, int txQueue, int mode); -+ -+#endif -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthGbe.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthGbe.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthGbe.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthGbe.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,751 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+/******************************************************************************* -+* mvEth.h - Header File for : Marvell Gigabit Ethernet Controller -+* -+* DESCRIPTION: -+* This header file contains macros typedefs and function declaration specific to -+* the Marvell Gigabit Ethernet Controller. -+* -+* DEPENDENCIES: -+* None. -+* -+*******************************************************************************/ -+ -+#ifndef __mvEthGbe_h__ -+#define __mvEthGbe_h__ -+ -+extern MV_BOOL ethDescInSram; -+extern MV_BOOL ethDescSwCoher; -+extern ETH_PORT_CTRL* ethPortCtrl[]; -+ -+static INLINE MV_ULONG ethDescVirtToPhy(ETH_QUEUE_CTRL* pQueueCtrl, MV_U8* pDesc) -+{ -+#if defined (ETH_DESCR_IN_SRAM) -+ if( ethDescInSram ) -+ return mvSramVirtToPhy(pDesc); -+ else -+#endif /* ETH_DESCR_IN_SRAM */ -+ return (pQueueCtrl->descBuf.bufPhysAddr + (pDesc - pQueueCtrl->descBuf.bufVirtPtr)); -+} -+/* Return port handler */ -+#define mvEthPortHndlGet(port) ethPortCtrl[port] -+ -+/* Used as WA for HW/SW race on TX */ -+static INLINE int mvEthPortTxEnable(void* pPortHndl, int queue, int max_deep) -+{ -+ int deep = 0; -+ MV_U32 txCurrReg, txEnReg; -+ ETH_TX_DESC* pTxLastDesc; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ -+ txEnReg = MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)); -+ if( (txEnReg & MV_32BIT_LE_FAST(ETH_TXQ_ENABLE_MASK)) == 0) -+ { -+ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) = pPortCtrl->portTxQueueCmdReg; -+ return 0; -+ } -+ -+ pQueueCtrl = &pPortCtrl->txQueue[queue]; -+ pTxLastDesc = pQueueCtrl->pCurrentDescr; -+ txCurrReg = MV_REG_READ(ETH_TX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue)); -+ if(ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pTxLastDesc) == txCurrReg) -+ { -+ /* All descriptors are processed, no chance for race */ -+ return 0; -+ } -+ -+ /* Check distance betwee HW and SW location: */ -+ /* If distance between HW and SW pointers is less than max_deep descriptors */ -+ /* Race condition is possible, so wait end of TX and restart TXQ */ -+ while(deep < max_deep) -+ { -+ pTxLastDesc = TX_PREV_DESC_PTR(pTxLastDesc, pQueueCtrl); -+ if(ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pTxLastDesc) == txCurrReg) -+ { -+ int count = 0; -+ -+ while( (txEnReg & MV_32BIT_LE_FAST(ETH_TXQ_ENABLE_MASK)) != 0) -+ { -+ count++; -+ if(count > 10000) -+ { -+ mvOsPrintf("mvEthPortTxEnable: timeout - TXQ_CMD=0x%08x\n", -+ MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) ); -+ break; -+ } -+ txEnReg = MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)); -+ } -+ -+ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) = pPortCtrl->portTxQueueCmdReg; -+ return count; -+ } -+ deep++; -+ } -+ /* Distance between HW and SW pointers is more than max_deep descriptors, */ -+ /* So NO race condition - do nothing */ -+ return -1; -+} -+ -+ -+/* defines */ -+#define ETH_CSUM_MIN_BYTE_COUNT 72 -+ -+/* Tailgate and Kirwood have only 2K TX FIFO */ -+#if (MV_ETH_VERSION == 2) || (MV_ETH_VERSION == 4) -+#define ETH_CSUM_MAX_BYTE_COUNT 1600 -+#else -+#define ETH_CSUM_MAX_BYTE_COUNT 9*1024 -+#endif /* MV_ETH_VERSION */ -+ -+#define ETH_MV_HEADER_SIZE 2 -+#define ETH_MV_TX_EN -+ -+/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */ -+#define MIN_TX_BUFF_LOAD 8 -+#define TX_BUF_OFFSET_IN_DESC (ETH_TX_DESC_ALIGNED_SIZE - MIN_TX_BUFF_LOAD) -+ -+/* Default port configuration value */ -+#define PORT_CONFIG_VALUE \ -+ ETH_DEF_RX_QUEUE_MASK(0) | \ -+ ETH_DEF_RX_ARP_QUEUE_MASK(0) | \ -+ ETH_DEF_RX_TCP_QUEUE_MASK(0) | \ -+ ETH_DEF_RX_UDP_QUEUE_MASK(0) | \ -+ ETH_DEF_RX_BPDU_QUEUE_MASK(0) | \ -+ ETH_RX_CHECKSUM_WITH_PSEUDO_HDR -+ -+/* Default port extend configuration value */ -+#define PORT_CONFIG_EXTEND_VALUE 0 -+ -+#define PORT_SERIAL_CONTROL_VALUE \ -+ ETH_DISABLE_FC_AUTO_NEG_MASK | \ -+ BIT9 | \ -+ ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ -+ ETH_MAX_RX_PACKET_1552BYTE | \ -+ ETH_SET_FULL_DUPLEX_MASK -+ -+#define PORT_SERIAL_CONTROL_100MB_FORCE_VALUE \ -+ ETH_FORCE_LINK_PASS_MASK | \ -+ ETH_DISABLE_DUPLEX_AUTO_NEG_MASK | \ -+ ETH_DISABLE_FC_AUTO_NEG_MASK | \ -+ BIT9 | \ -+ ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ -+ ETH_DISABLE_SPEED_AUTO_NEG_MASK | \ -+ ETH_SET_FULL_DUPLEX_MASK | \ -+ ETH_SET_MII_SPEED_100_MASK | \ -+ ETH_MAX_RX_PACKET_1552BYTE -+ -+ -+#define PORT_SERIAL_CONTROL_1000MB_FORCE_VALUE \ -+ ETH_FORCE_LINK_PASS_MASK | \ -+ ETH_DISABLE_DUPLEX_AUTO_NEG_MASK | \ -+ ETH_DISABLE_FC_AUTO_NEG_MASK | \ -+ BIT9 | \ -+ ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ -+ ETH_DISABLE_SPEED_AUTO_NEG_MASK | \ -+ ETH_SET_FULL_DUPLEX_MASK | \ -+ ETH_SET_GMII_SPEED_1000_MASK | \ -+ ETH_MAX_RX_PACKET_1552BYTE -+ -+#define PORT_SERIAL_CONTROL_SGMII_IBAN_VALUE \ -+ ETH_DISABLE_FC_AUTO_NEG_MASK | \ -+ BIT9 | \ -+ ETH_IN_BAND_AN_EN_MASK | \ -+ ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ -+ ETH_MAX_RX_PACKET_1552BYTE -+ -+/* Function headers: */ -+MV_VOID mvEthSetSpecialMcastTable(int portNo, int queue); -+MV_STATUS mvEthArpRxQueue(void* pPortHandle, int arpQueue); -+MV_STATUS mvEthUdpRxQueue(void* pPortHandle, int udpQueue); -+MV_STATUS mvEthTcpRxQueue(void* pPortHandle, int tcpQueue); -+MV_STATUS mvEthMacAddrGet(int portNo, unsigned char *pAddr); -+MV_VOID mvEthSetOtherMcastTable(int portNo, int queue); -+MV_STATUS mvEthHeaderModeSet(void* pPortHandle, MV_ETH_HEADER_MODE headerMode); -+/* Interrupt Coalesting functions */ -+MV_U32 mvEthRxCoalSet(void* pPortHndl, MV_U32 uSec); -+MV_U32 mvEthTxCoalSet(void* pPortHndl, MV_U32 uSec); -+MV_STATUS mvEthCoalGet(void* pPortHndl, MV_U32* pRxCoal, MV_U32* pTxCoal); -+ -+/******************************************************************************/ -+/* Data Flow functions */ -+/******************************************************************************/ -+static INLINE void mvEthPortTxRestart(void* pPortHndl) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ -+ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) = pPortCtrl->portTxQueueCmdReg; -+} -+ -+/* Get number of Free resources in specific TX queue */ -+static INLINE int mvEthTxResourceGet(void* pPortHndl, int txQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ -+ return (pPortCtrl->txQueue[txQueue].resource); -+} -+ -+/* Get number of Free resources in specific RX queue */ -+static INLINE int mvEthRxResourceGet(void* pPortHndl, int rxQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ -+ return (pPortCtrl->rxQueue[rxQueue].resource); -+} -+ -+static INLINE int mvEthTxQueueIsFull(void* pPortHndl, int txQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ -+ if(pPortCtrl->txQueue[txQueue].resource == 0) -+ return MV_TRUE; -+ -+ return MV_FALSE; -+} -+ -+/* Get number of Free resources in specific RX queue */ -+static INLINE int mvEthRxQueueIsFull(void* pPortHndl, int rxQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->rxQueue[rxQueue]; -+ -+ if( (pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) && -+ (pQueueCtrl->resource != 0) ) -+ return MV_TRUE; -+ -+ return MV_FALSE; -+} -+ -+static INLINE int mvEthTxQueueIsEmpty(void* pPortHndl, int txQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->txQueue[txQueue]; -+ -+ if( (pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) && -+ (pQueueCtrl->resource != 0) ) -+ { -+ return MV_TRUE; -+ } -+ return MV_FALSE; -+} -+ -+/* Get number of Free resources in specific RX queue */ -+static INLINE int mvEthRxQueueIsEmpty(void* pPortHndl, int rxQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ -+ if(pPortCtrl->rxQueue[rxQueue].resource == 0) -+ return MV_TRUE; -+ -+ return MV_FALSE; -+} -+ -+/******************************************************************************* -+* mvEthPortTx - Send an Ethernet packet -+* -+* DESCRIPTION: -+* This routine send a given packet described by pPktInfo parameter. -+* Single buffer only. -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet Port handler. -+* int txQueue - Number of Tx queue. -+* MV_PKT_INFO *pPktInfo - User packet to send. -+* -+* RETURN: -+* MV_NO_RESOURCE - No enough resources to send this packet. -+* MV_ERROR - Unexpected Fatal error. -+* MV_OK - Packet send successfully. -+* -+*******************************************************************************/ -+static INLINE MV_STATUS mvEthPortTx(void* pEthPortHndl, int txQueue, MV_PKT_INFO* pPktInfo) -+{ -+ ETH_TX_DESC* pTxCurrDesc; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ int portNo; -+ MV_BUF_INFO* pBufInfo = pPktInfo->pFrags; -+ -+#ifdef ETH_DEBUG -+ if(pPortCtrl->portState != MV_ACTIVE) -+ return MV_BAD_STATE; -+#endif /* ETH_DEBUG */ -+ -+ portNo = pPortCtrl->portNo; -+ pQueueCtrl = &pPortCtrl->txQueue[txQueue]; -+ -+ /* Get the Tx Desc ring indexes */ -+ pTxCurrDesc = pQueueCtrl->pCurrentDescr; -+ -+ /* Check if there is enough resources to send the packet */ -+ if(pQueueCtrl->resource == 0) -+ return MV_NO_RESOURCE; -+ -+ pTxCurrDesc->byteCnt = pBufInfo->dataSize; -+ -+ /* Flash Buffer */ -+ if(pPktInfo->pktSize != 0) -+ { -+#ifdef MV_NETBSD -+ pTxCurrDesc->bufPtr = pBufInfo->bufPhysAddr; -+ ETH_PACKET_CACHE_FLUSH(pBufInfo->bufVirtPtr, pPktInfo->pktSize); -+#else -+ pTxCurrDesc->bufPtr = ETH_PACKET_CACHE_FLUSH(pBufInfo->bufVirtPtr, pPktInfo->pktSize); -+#endif -+ pPktInfo->pktSize = 0; -+ } -+ else -+ pTxCurrDesc->bufPtr = pBufInfo->bufPhysAddr; -+ -+ pTxCurrDesc->returnInfo = (MV_ULONG)pPktInfo; -+ -+ /* There is only one buffer in the packet */ -+ /* The OSG might set some bits for checksum offload, so add them to first descriptor */ -+ pTxCurrDesc->cmdSts = pPktInfo->status | -+ ETH_BUFFER_OWNED_BY_DMA | -+ ETH_TX_GENERATE_CRC_MASK | -+ ETH_TX_ENABLE_INTERRUPT_MASK | -+ ETH_TX_ZERO_PADDING_MASK | -+ ETH_TX_FIRST_DESC_MASK | -+ ETH_TX_LAST_DESC_MASK; -+ -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); -+ -+ pQueueCtrl->resource--; -+ pQueueCtrl->pCurrentDescr = TX_NEXT_DESC_PTR(pTxCurrDesc, pQueueCtrl); -+ -+ /* Apply send command */ -+ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(portNo)) = pPortCtrl->portTxQueueCmdReg; -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvEthPortSgTx - Send an Ethernet packet -+* -+* DESCRIPTION: -+* This routine send a given packet described by pBufInfo parameter. It -+* supports transmitting of a packet spaned over multiple buffers. -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet Port handler. -+* int txQueue - Number of Tx queue. -+* MV_PKT_INFO *pPktInfo - User packet to send. -+* -+* RETURN: -+* MV_NO_RESOURCE - No enough resources to send this packet. -+* MV_ERROR - Unexpected Fatal error. -+* MV_OK - Packet send successfully. -+* -+*******************************************************************************/ -+static INLINE MV_STATUS mvEthPortSgTx(void* pEthPortHndl, int txQueue, MV_PKT_INFO* pPktInfo) -+{ -+ ETH_TX_DESC* pTxFirstDesc; -+ ETH_TX_DESC* pTxCurrDesc; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ int portNo, bufCount; -+ MV_BUF_INFO* pBufInfo = pPktInfo->pFrags; -+ MV_U8* pTxBuf; -+ -+#ifdef ETH_DEBUG -+ if(pPortCtrl->portState != MV_ACTIVE) -+ return MV_BAD_STATE; -+#endif /* ETH_DEBUG */ -+ -+ portNo = pPortCtrl->portNo; -+ pQueueCtrl = &pPortCtrl->txQueue[txQueue]; -+ -+ /* Get the Tx Desc ring indexes */ -+ pTxCurrDesc = pQueueCtrl->pCurrentDescr; -+ -+ /* Check if there is enough resources to send the packet */ -+ if(pQueueCtrl->resource < pPktInfo->numFrags) -+ return MV_NO_RESOURCE; -+ -+ /* Remember first desc */ -+ pTxFirstDesc = pTxCurrDesc; -+ -+ bufCount = 0; -+ while(MV_TRUE) -+ { -+ if(pBufInfo[bufCount].dataSize <= MIN_TX_BUFF_LOAD) -+ { -+ /* Buffers with a payload smaller than MIN_TX_BUFF_LOAD (8 bytes) must be aligned */ -+ /* to 64-bit boundary. Two options here: */ -+ /* 1) Usually, copy the payload to the reserved 8 bytes inside descriptor. */ -+ /* 2) In the Half duplex workaround, the reserved 8 bytes inside descriptor are used */ -+ /* as a pointer to the aligned buffer, copy the small payload to this buffer. */ -+ pTxBuf = ((MV_U8*)pTxCurrDesc)+TX_BUF_OFFSET_IN_DESC; -+ mvOsBCopy(pBufInfo[bufCount].bufVirtPtr, pTxBuf, pBufInfo[bufCount].dataSize); -+ pTxCurrDesc->bufPtr = ethDescVirtToPhy(pQueueCtrl, pTxBuf); -+ } -+ else -+ { -+ /* Flash Buffer */ -+#ifdef MV_NETBSD -+ pTxCurrDesc->bufPtr = pBufInfo[bufCount].bufPhysAddr; -+ ETH_PACKET_CACHE_FLUSH(pBufInfo[bufCount].bufVirtPtr, pBufInfo[bufCount].dataSize); -+#else -+ pTxCurrDesc->bufPtr = ETH_PACKET_CACHE_FLUSH(pBufInfo[bufCount].bufVirtPtr, pBufInfo[bufCount].dataSize); -+#endif -+ } -+ -+ pTxCurrDesc->byteCnt = pBufInfo[bufCount].dataSize; -+ bufCount++; -+ -+ if(bufCount >= pPktInfo->numFrags) -+ break; -+ -+ if(bufCount > 1) -+ { -+ /* There is middle buffer of the packet Not First and Not Last */ -+ pTxCurrDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA; -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); -+ } -+ /* Go to next descriptor and next buffer */ -+ pTxCurrDesc = TX_NEXT_DESC_PTR(pTxCurrDesc, pQueueCtrl); -+ } -+ /* Set last desc with DMA ownership and interrupt enable. */ -+ pTxCurrDesc->returnInfo = (MV_ULONG)pPktInfo; -+ if(bufCount == 1) -+ { -+ /* There is only one buffer in the packet */ -+ /* The OSG might set some bits for checksum offload, so add them to first descriptor */ -+ pTxCurrDesc->cmdSts = pPktInfo->status | -+ ETH_BUFFER_OWNED_BY_DMA | -+ ETH_TX_GENERATE_CRC_MASK | -+ ETH_TX_ENABLE_INTERRUPT_MASK | -+ ETH_TX_ZERO_PADDING_MASK | -+ ETH_TX_FIRST_DESC_MASK | -+ ETH_TX_LAST_DESC_MASK; -+ -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); -+ } -+ else -+ { -+ /* Last but not First */ -+ pTxCurrDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA | -+ ETH_TX_ENABLE_INTERRUPT_MASK | -+ ETH_TX_ZERO_PADDING_MASK | -+ ETH_TX_LAST_DESC_MASK; -+ -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); -+ -+ /* Update First when more than one buffer in the packet */ -+ /* The OSG might set some bits for checksum offload, so add them to first descriptor */ -+ pTxFirstDesc->cmdSts = pPktInfo->status | -+ ETH_BUFFER_OWNED_BY_DMA | -+ ETH_TX_GENERATE_CRC_MASK | -+ ETH_TX_FIRST_DESC_MASK; -+ -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxFirstDesc); -+ } -+ /* Update txQueue state */ -+ pQueueCtrl->resource -= bufCount; -+ pQueueCtrl->pCurrentDescr = TX_NEXT_DESC_PTR(pTxCurrDesc, pQueueCtrl); -+ -+ /* Apply send command */ -+ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(portNo)) = pPortCtrl->portTxQueueCmdReg; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthPortTxDone - Free all used Tx descriptors and mBlks. -+* -+* DESCRIPTION: -+* This routine returns the transmitted packet information to the caller. -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet Port handler. -+* int txQueue - Number of Tx queue. -+* -+* OUTPUT: -+* MV_PKT_INFO *pPktInfo - Pointer to packet was sent. -+* -+* RETURN: -+* MV_NOT_FOUND - No transmitted packets to return. Transmit in progress. -+* MV_EMPTY - No transmitted packets to return. TX Queue is empty. -+* MV_ERROR - Unexpected Fatal error. -+* MV_OK - There is transmitted packet in the queue, -+* 'pPktInfo' filled with relevant information. -+* -+*******************************************************************************/ -+static INLINE MV_PKT_INFO* mvEthPortTxDone(void* pEthPortHndl, int txQueue) -+{ -+ ETH_TX_DESC* pTxCurrDesc; -+ ETH_TX_DESC* pTxUsedDesc; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ MV_PKT_INFO* pPktInfo; -+ MV_U32 commandStatus; -+ -+ pQueueCtrl = &pPortCtrl->txQueue[txQueue]; -+ -+ pTxUsedDesc = pQueueCtrl->pUsedDescr; -+ pTxCurrDesc = pQueueCtrl->pCurrentDescr; -+ -+ while(MV_TRUE) -+ { -+ /* No more used descriptors */ -+ commandStatus = pTxUsedDesc->cmdSts; -+ if (commandStatus & (ETH_BUFFER_OWNED_BY_DMA)) -+ { -+ ETH_DESCR_INV(pPortCtrl, pTxUsedDesc); -+ return NULL; -+ } -+ if( (pTxUsedDesc == pTxCurrDesc) && -+ (pQueueCtrl->resource != 0) ) -+ { -+ return NULL; -+ } -+ pQueueCtrl->resource++; -+ pQueueCtrl->pUsedDescr = TX_NEXT_DESC_PTR(pTxUsedDesc, pQueueCtrl); -+ if(commandStatus & (ETH_TX_LAST_DESC_MASK)) -+ { -+ pPktInfo = (MV_PKT_INFO*)pTxUsedDesc->returnInfo; -+ pPktInfo->status = commandStatus; -+ return pPktInfo; -+ } -+ pTxUsedDesc = pQueueCtrl->pUsedDescr; -+ } -+} -+ -+/******************************************************************************* -+* mvEthPortRx - Get new received packets from Rx queue. -+* -+* DESCRIPTION: -+* This routine returns the received data to the caller. There is no -+* data copying during routine operation. All information is returned -+* using pointer to packet information struct passed from the caller. -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet Port handler. -+* int rxQueue - Number of Rx queue. -+* -+* OUTPUT: -+* MV_PKT_INFO *pPktInfo - Pointer to received packet. -+* -+* RETURN: -+* MV_NO_RESOURCE - No free resources in RX queue. -+* MV_ERROR - Unexpected Fatal error. -+* MV_OK - New packet received and 'pBufInfo' structure filled -+* with relevant information. -+* -+*******************************************************************************/ -+static INLINE MV_PKT_INFO* mvEthPortRx(void* pEthPortHndl, int rxQueue) -+{ -+ ETH_RX_DESC *pRxCurrDesc; -+ MV_U32 commandStatus; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ MV_PKT_INFO* pPktInfo; -+ -+ pQueueCtrl = &(pPortCtrl->rxQueue[rxQueue]); -+ -+ /* Check resources */ -+ if(pQueueCtrl->resource == 0) -+ { -+ mvOsPrintf("ethPortRx: no more resources\n"); -+ return NULL; -+ } -+ while(MV_TRUE) -+ { -+ /* Get the Rx Desc ring 'curr and 'used' indexes */ -+ pRxCurrDesc = pQueueCtrl->pCurrentDescr; -+ -+ commandStatus = pRxCurrDesc->cmdSts; -+ if (commandStatus & (ETH_BUFFER_OWNED_BY_DMA)) -+ { -+ /* Nothing to receive... */ -+ ETH_DESCR_INV(pPortCtrl, pRxCurrDesc); -+ return NULL; -+ } -+ -+ /* Valid RX only if FIRST and LAST bits are set */ -+ if( (commandStatus & (ETH_RX_LAST_DESC_MASK | ETH_RX_FIRST_DESC_MASK)) == -+ (ETH_RX_LAST_DESC_MASK | ETH_RX_FIRST_DESC_MASK) ) -+ { -+ pPktInfo = (MV_PKT_INFO*)pRxCurrDesc->returnInfo; -+ pPktInfo->pFrags->dataSize = pRxCurrDesc->byteCnt - 4; -+ pPktInfo->status = commandStatus; -+ pPktInfo->fragIP = pRxCurrDesc->bufSize & ETH_RX_IP_FRAGMENTED_FRAME_MASK; -+ -+ pQueueCtrl->resource--; -+ /* Update 'curr' in data structure */ -+ pQueueCtrl->pCurrentDescr = RX_NEXT_DESC_PTR(pRxCurrDesc, pQueueCtrl); -+ -+#ifdef INCLUDE_SYNC_BARR -+ mvCpuIfSyncBarr(DRAM_TARGET); -+#endif -+ return pPktInfo; -+ } -+ else -+ { -+ ETH_RX_DESC* pRxUsedDesc = pQueueCtrl->pUsedDescr; -+ -+#ifdef ETH_DEBUG -+ mvOsPrintf("ethDrv: Unexpected Jumbo frame: " -+ "status=0x%08x, byteCnt=%d, pData=0x%x\n", -+ commandStatus, pRxCurrDesc->byteCnt, pRxCurrDesc->bufPtr); -+#endif /* ETH_DEBUG */ -+ -+ /* move buffer from pCurrentDescr position to pUsedDescr position */ -+ pRxUsedDesc->bufPtr = pRxCurrDesc->bufPtr; -+ pRxUsedDesc->returnInfo = pRxCurrDesc->returnInfo; -+ pRxUsedDesc->bufSize = pRxCurrDesc->bufSize & ETH_RX_BUFFER_MASK; -+ -+ /* Return the descriptor to DMA ownership */ -+ pRxUsedDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA | -+ ETH_RX_ENABLE_INTERRUPT_MASK; -+ -+ /* Flush descriptor and CPU pipe */ -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxUsedDesc); -+ -+ /* Move the used descriptor pointer to the next descriptor */ -+ pQueueCtrl->pUsedDescr = RX_NEXT_DESC_PTR(pRxUsedDesc, pQueueCtrl); -+ pQueueCtrl->pCurrentDescr = RX_NEXT_DESC_PTR(pRxCurrDesc, pQueueCtrl); -+ } -+ } -+} -+ -+/******************************************************************************* -+* mvEthPortRxDone - Returns a Rx buffer back to the Rx ring. -+* -+* DESCRIPTION: -+* This routine returns a Rx buffer back to the Rx ring. -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet Port handler. -+* int rxQueue - Number of Rx queue. -+* MV_PKT_INFO *pPktInfo - Pointer to received packet. -+* -+* RETURN: -+* MV_ERROR - Unexpected Fatal error. -+* MV_OUT_OF_RANGE - RX queue is already FULL, so this buffer can't be -+* returned to this queue. -+* MV_FULL - Buffer returned successfully and RX queue became full. -+* More buffers should not be returned at the time. -+* MV_OK - Buffer returned successfully and there are more free -+* places in the queue. -+* -+*******************************************************************************/ -+static INLINE MV_STATUS mvEthPortRxDone(void* pEthPortHndl, int rxQueue, MV_PKT_INFO *pPktInfo) -+{ -+ ETH_RX_DESC* pRxUsedDesc; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ -+ pQueueCtrl = &pPortCtrl->rxQueue[rxQueue]; -+ -+ /* Get 'used' Rx descriptor */ -+ pRxUsedDesc = pQueueCtrl->pUsedDescr; -+ -+ /* Check that ring is not FULL */ -+ if( (pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) && -+ (pQueueCtrl->resource != 0) ) -+ { -+ mvOsPrintf("%s %d: out of range Error resource=%d, curr=%p, used=%p\n", -+ __FUNCTION__, pPortCtrl->portNo, pQueueCtrl->resource, -+ pQueueCtrl->pCurrentDescr, pQueueCtrl->pUsedDescr); -+ return MV_OUT_OF_RANGE; -+ } -+ -+ pRxUsedDesc->bufPtr = pPktInfo->pFrags->bufPhysAddr; -+ pRxUsedDesc->returnInfo = (MV_ULONG)pPktInfo; -+ pRxUsedDesc->bufSize = pPktInfo->pFrags->bufSize & ETH_RX_BUFFER_MASK; -+ -+ /* Invalidate data buffer accordingly with pktSize */ -+ if(pPktInfo->pktSize != 0) -+ { -+ ETH_PACKET_CACHE_INVALIDATE(pPktInfo->pFrags->bufVirtPtr, pPktInfo->pktSize); -+ pPktInfo->pktSize = 0; -+ } -+ -+ /* Return the descriptor to DMA ownership */ -+ pRxUsedDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT_MASK; -+ -+ /* Flush descriptor and CPU pipe */ -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxUsedDesc); -+ -+ pQueueCtrl->resource++; -+ -+ /* Move the used descriptor pointer to the next descriptor */ -+ pQueueCtrl->pUsedDescr = RX_NEXT_DESC_PTR(pRxUsedDesc, pQueueCtrl); -+ -+ /* If ring became Full return MV_FULL */ -+ if(pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) -+ return MV_FULL; -+ -+ return MV_OK; -+} -+ -+ -+#endif /* __mvEthGbe_h__ */ -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,700 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvEthRegsh -+#define __INCmvEthRegsh -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+ -+/****************************************/ -+/* Ethernet Unit Registers */ -+/****************************************/ -+#define ETH_REG_BASE MV_ETH_REG_BASE -+ -+#define ETH_PHY_ADDR_REG(port) (ETH_REG_BASE(port) + 0x000) -+#define ETH_SMI_REG(port) (ETH_REG_BASE(port) + 0x004) -+#define ETH_UNIT_DEF_ADDR_REG(port) (ETH_REG_BASE(port) + 0x008) -+#define ETH_UNIT_DEF_ID_REG(port) (ETH_REG_BASE(port) + 0x00c) -+#define ETH_UNIT_RESERVED(port) (ETH_REG_BASE(port) + 0x014) -+#define ETH_UNIT_INTR_CAUSE_REG(port) (ETH_REG_BASE(port) + 0x080) -+#define ETH_UNIT_INTR_MASK_REG(port) (ETH_REG_BASE(port) + 0x084) -+ -+ -+#define ETH_UNIT_ERROR_ADDR_REG(port) (ETH_REG_BASE(port) + 0x094) -+#define ETH_UNIT_INT_ADDR_ERROR_REG(port) (ETH_REG_BASE(port) + 0x098) -+#define ETH_UNIT_CONTROL_REG(port) (ETH_REG_BASE(port) + 0x0B0) -+ -+#define ETH_PORT_CONFIG_REG(port) (ETH_REG_BASE(port) + 0x400) -+#define ETH_PORT_CONFIG_EXTEND_REG(port) (ETH_REG_BASE(port) + 0x404) -+#define ETH_MII_SERIAL_PARAM_REG(port) (ETH_REG_BASE(port) + 0x408) -+#define ETH_GMII_SERIAL_PARAM_REG(port) (ETH_REG_BASE(port) + 0x40c) -+#define ETH_VLAN_ETHER_TYPE_REG(port) (ETH_REG_BASE(port) + 0x410) -+#define ETH_MAC_ADDR_LOW_REG(port) (ETH_REG_BASE(port) + 0x414) -+#define ETH_MAC_ADDR_HIGH_REG(port) (ETH_REG_BASE(port) + 0x418) -+#define ETH_SDMA_CONFIG_REG(port) (ETH_REG_BASE(port) + 0x41c) -+#define ETH_DIFF_SERV_PRIO_REG(port, code) (ETH_REG_BASE(port) + 0x420 + ((code)<<2)) -+#define ETH_PORT_SERIAL_CTRL_REG(port) (ETH_REG_BASE(port) + 0x43c) -+#define ETH_VLAN_TAG_TO_PRIO_REG(port) (ETH_REG_BASE(port) + 0x440) -+#define ETH_PORT_STATUS_REG(port) (ETH_REG_BASE(port) + 0x444) -+ -+#define ETH_RX_QUEUE_COMMAND_REG(port) (ETH_REG_BASE(port) + 0x680) -+#define ETH_TX_QUEUE_COMMAND_REG(port) (ETH_REG_BASE(port) + 0x448) -+ -+#define ETH_PORT_SERIAL_CTRL_1_REG(port) (ETH_REG_BASE(port) + 0x44c) -+#define ETH_PORT_STATUS_1_REG(port) (ETH_REG_BASE(port) + 0x450) -+#define ETH_PORT_MARVELL_HEADER_REG(port) (ETH_REG_BASE(port) + 0x454) -+#define ETH_PORT_FIFO_PARAMS_REG(port) (ETH_REG_BASE(port) + 0x458) -+#define ETH_MAX_TOKEN_BUCKET_SIZE_REG(port) (ETH_REG_BASE(port) + 0x45c) -+#define ETH_INTR_CAUSE_REG(port) (ETH_REG_BASE(port) + 0x460) -+#define ETH_INTR_CAUSE_EXT_REG(port) (ETH_REG_BASE(port) + 0x464) -+#define ETH_INTR_MASK_REG(port) (ETH_REG_BASE(port) + 0x468) -+#define ETH_INTR_MASK_EXT_REG(port) (ETH_REG_BASE(port) + 0x46c) -+#define ETH_TX_FIFO_URGENT_THRESH_REG(port) (ETH_REG_BASE(port) + 0x474) -+#define ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (ETH_REG_BASE(port) + 0x47c) -+#define ETH_RX_DISCARD_PKTS_CNTR_REG(port) (ETH_REG_BASE(port) + 0x484) -+#define ETH_RX_OVERRUN_PKTS_CNTR_REG(port) (ETH_REG_BASE(port) + 0x488) -+#define ETH_INTERNAL_ADDR_ERROR_REG(port) (ETH_REG_BASE(port) + 0x494) -+#define ETH_TX_FIXED_PRIO_CFG_REG(port) (ETH_REG_BASE(port) + 0x4dc) -+#define ETH_TX_TOKEN_RATE_CFG_REG(port) (ETH_REG_BASE(port) + 0x4e0) -+#define ETH_TX_QUEUE_COMMAND1_REG(port) (ETH_REG_BASE(port) + 0x4e4) -+#define ETH_MAX_TRANSMIT_UNIT_REG(port) (ETH_REG_BASE(port) + 0x4e8) -+#define ETH_TX_TOKEN_BUCKET_SIZE_REG(port) (ETH_REG_BASE(port) + 0x4ec) -+#define ETH_TX_TOKEN_BUCKET_COUNT_REG(port) (ETH_REG_BASE(port) + 0x780) -+#define ETH_RX_DESCR_STAT_CMD_REG(port, q) (ETH_REG_BASE(port) + 0x600 + ((q)<<4)) -+#define ETH_RX_BYTE_COUNT_REG(port, q) (ETH_REG_BASE(port) + 0x604 + ((q)<<4)) -+#define ETH_RX_BUF_PTR_REG(port, q) (ETH_REG_BASE(port) + 0x608 + ((q)<<4)) -+#define ETH_RX_CUR_DESC_PTR_REG(port, q) (ETH_REG_BASE(port) + 0x60c + ((q)<<4)) -+#define ETH_TX_CUR_DESC_PTR_REG(port, q) (ETH_REG_BASE(port) + 0x6c0 + ((q)<<2)) -+ -+#define ETH_TXQ_TOKEN_COUNT_REG(port, q) (ETH_REG_BASE(port) + 0x700 + ((q)<<4)) -+#define ETH_TXQ_TOKEN_CFG_REG(port, q) (ETH_REG_BASE(port) + 0x704 + ((q)<<4)) -+#define ETH_TXQ_ARBITER_CFG_REG(port, q) (ETH_REG_BASE(port) + 0x708 + ((q)<<4)) -+ -+#if (MV_ETH_VERSION >= 4) -+#define ETH_TXQ_CMD_1_REG(port) (ETH_REG_BASE(port) + 0x4E4) -+#define ETH_EJP_TX_HI_IPG_REG(port) (ETH_REG_BASE(port) + 0x7A8) -+#define ETH_EJP_TX_LO_IPG_REG(port) (ETH_REG_BASE(port) + 0x7B8) -+#define ETH_EJP_HI_TKN_LO_PKT_REG(port) (ETH_REG_BASE(port) + 0x7C0) -+#define ETH_EJP_HI_TKN_ASYNC_PKT_REG(port) (ETH_REG_BASE(port) + 0x7C4) -+#define ETH_EJP_LO_TKN_ASYNC_PKT_REG(port) (ETH_REG_BASE(port) + 0x7C8) -+#define ETH_EJP_TX_SPEED_REG(port) (ETH_REG_BASE(port) + 0x7D0) -+#endif /* MV_ETH_VERSION >= 4 */ -+ -+#define ETH_MIB_COUNTERS_BASE(port) (ETH_REG_BASE(port) + 0x1000) -+#define ETH_DA_FILTER_SPEC_MCAST_BASE(port) (ETH_REG_BASE(port) + 0x1400) -+#define ETH_DA_FILTER_OTH_MCAST_BASE(port) (ETH_REG_BASE(port) + 0x1500) -+#define ETH_DA_FILTER_UCAST_BASE(port) (ETH_REG_BASE(port) + 0x1600) -+ -+/* Phy address register definitions */ -+#define ETH_PHY_ADDR_OFFS 0 -+#define ETH_PHY_ADDR_MASK (0x1f <= 4) -+#define ETH_TX_EJP_RESET_BIT 0 -+#define ETH_TX_EJP_RESET_MASK (1 << ETH_TX_EJP_RESET_BIT) -+ -+#define ETH_TX_EJP_ENABLE_BIT 2 -+#define ETH_TX_EJP_ENABLE_MASK (1 << ETH_TX_EJP_ENABLE_BIT) -+ -+#define ETH_TX_LEGACY_WRR_BIT 3 -+#define ETH_TX_LEGACY_WRR_MASK (1 << ETH_TX_LEGACY_WRR_BIT) -+#endif /* (MV_ETH_VERSION >= 4) */ -+ -+/***** BITs of Ethernet Port Status reg (PSR) *****/ -+#define ETH_LINK_UP_BIT 1 -+#define ETH_LINK_UP_MASK (1<= 4) -+MV_STATUS mvEthEjpModeSet(void* pPortHandle, int mode); -+#endif /* (MV_ETH_VERSION >= 4) */ -+ -+void mvEthStatusGet(void* pPortHandle, MV_ETH_PORT_STATUS* pStatus); -+ -+/* Marvell Header control */ -+MV_STATUS mvEthHeaderModeSet(void* pPortHandle, MV_ETH_HEADER_MODE headerMode); -+ -+/* PHY routines */ -+void mvEthPhyAddrSet(void* pPortHandle, int phyAddr); -+int mvEthPhyAddrGet(void* pPortHandle); -+ -+/* Power management routines */ -+void mvEthPortPowerDown(int port); -+void mvEthPortPowerUp(int port); -+ -+/******************** ETH PRIVATE ************************/ -+ -+/*#define UNCACHED_TX_BUFFERS*/ -+/*#define UNCACHED_RX_BUFFERS*/ -+ -+ -+/* Port attributes */ -+/* Size of a Tx/Rx descriptor used in chain list data structure */ -+#define ETH_RX_DESC_ALIGNED_SIZE 32 -+#define ETH_TX_DESC_ALIGNED_SIZE 32 -+ -+#define TX_DISABLE_TIMEOUT_MSEC 1000 -+#define RX_DISABLE_TIMEOUT_MSEC 1000 -+#define TX_FIFO_EMPTY_TIMEOUT_MSEC 10000 -+#define PORT_DISABLE_WAIT_TCLOCKS 5000 -+ -+/* Macros that save access to desc in order to find next desc pointer */ -+#define RX_NEXT_DESC_PTR(pRxDescr, pQueueCtrl) \ -+ ((pRxDescr) == (pQueueCtrl)->pLastDescr) ? \ -+ (ETH_RX_DESC*)((pQueueCtrl)->pFirstDescr) : \ -+ (ETH_RX_DESC*)(((MV_ULONG)(pRxDescr)) + ETH_RX_DESC_ALIGNED_SIZE) -+ -+#define TX_NEXT_DESC_PTR(pTxDescr, pQueueCtrl) \ -+ ((pTxDescr) == (pQueueCtrl)->pLastDescr) ? \ -+ (ETH_TX_DESC*)((pQueueCtrl)->pFirstDescr) : \ -+ (ETH_TX_DESC*)(((MV_ULONG)(pTxDescr)) + ETH_TX_DESC_ALIGNED_SIZE) -+ -+#define RX_PREV_DESC_PTR(pRxDescr, pQueueCtrl) \ -+ ((pRxDescr) == (pQueueCtrl)->pFirstDescr) ? \ -+ (ETH_RX_DESC*)((pQueueCtrl)->pLastDescr) : \ -+ (ETH_RX_DESC*)(((MV_ULONG)(pRxDescr)) - ETH_RX_DESC_ALIGNED_SIZE) -+ -+#define TX_PREV_DESC_PTR(pTxDescr, pQueueCtrl) \ -+ ((pTxDescr) == (pQueueCtrl)->pFirstDescr) ? \ -+ (ETH_TX_DESC*)((pQueueCtrl)->pLastDescr) : \ -+ (ETH_TX_DESC*)(((MV_ULONG)(pTxDescr)) - ETH_TX_DESC_ALIGNED_SIZE) -+ -+ -+/* Queue specific information */ -+typedef struct -+{ -+ void* pFirstDescr; -+ void* pLastDescr; -+ void* pCurrentDescr; -+ void* pUsedDescr; -+ int resource; -+ MV_BUF_INFO descBuf; -+} ETH_QUEUE_CTRL; -+ -+ -+/* Ethernet port specific infomation */ -+typedef struct _ethPortCtrl -+{ -+ int portNo; -+ ETH_QUEUE_CTRL rxQueue[MV_ETH_RX_Q_NUM]; /* Rx ring resource */ -+ ETH_QUEUE_CTRL txQueue[MV_ETH_TX_Q_NUM]; /* Tx ring resource */ -+ -+ MV_ETH_PORT_CFG portConfig; -+ MV_ETH_RX_Q_CFG rxQueueConfig[MV_ETH_RX_Q_NUM]; -+ MV_ETH_TX_Q_CFG txQueueConfig[MV_ETH_TX_Q_NUM]; -+ -+ /* Register images - For DP */ -+ MV_U32 portTxQueueCmdReg; /* Port active Tx queues summary */ -+ MV_U32 portRxQueueCmdReg; /* Port active Rx queues summary */ -+ -+ MV_STATE portState; -+ -+ MV_U8 mcastCount[256]; -+ MV_U32* hashPtr; -+ void *osHandle; -+} ETH_PORT_CTRL; -+ -+/************** MACROs ****************/ -+ -+/* MACROs to Flush / Invalidate TX / RX Buffers */ -+#if (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) && !defined(UNCACHED_TX_BUFFERS) -+# define ETH_PACKET_CACHE_FLUSH(pAddr, size) \ -+ mvOsCacheClear(NULL, (pAddr), (size)); \ -+ /*CPU_PIPE_FLUSH;*/ -+#else -+# define ETH_PACKET_CACHE_FLUSH(pAddr, size) \ -+ mvOsIoVirtToPhy(NULL, (pAddr)); -+#endif /* ETHER_DRAM_COHER == MV_CACHE_COHER_SW */ -+ -+#if ( (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) && !defined(UNCACHED_RX_BUFFERS) ) -+# define ETH_PACKET_CACHE_INVALIDATE(pAddr, size) \ -+ mvOsCacheInvalidate (NULL, (pAddr), (size)); \ -+ /*CPU_PIPE_FLUSH;*/ -+#else -+# define ETH_PACKET_CACHE_INVALIDATE(pAddr, size) -+#endif /* ETHER_DRAM_COHER == MV_CACHE_COHER_SW && !UNCACHED_RX_BUFFERS */ -+ -+#ifdef ETH_DESCR_UNCACHED -+ -+#define ETH_DESCR_FLUSH_INV(pPortCtrl, pDescr) -+#define ETH_DESCR_INV(pPortCtrl, pDescr) -+ -+#else -+ -+#define ETH_DESCR_FLUSH_INV(pPortCtrl, pDescr) \ -+ mvOsCacheLineFlushInv(pPortCtrl->osHandle, (MV_ULONG)(pDescr)) -+ -+#define ETH_DESCR_INV(pPortCtrl, pDescr) \ -+ mvOsCacheLineInv(pPortCtrl->osHandle, (MV_ULONG)(pDescr)) -+ -+#endif /* ETH_DESCR_UNCACHED */ -+ -+#include "eth/gbe/mvEthGbe.h" -+ -+#endif /* __mvEth_h__ */ -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvCompVer.txt linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvCompVer.txt ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvCompVer.txt 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvCompVer.txt 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,4 @@ -+Global HAL Version: FEROCEON_HAL_3_1_7 -+Unit HAL Version: 3.1.4 -+Description: This component includes an implementation of the unit HAL drivers -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,362 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "gpp/mvGpp.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+static MV_VOID gppRegSet(MV_U32 group, MV_U32 regOffs,MV_U32 mask,MV_U32 value); -+ -+/******************************************************************************* -+* mvGppTypeSet - Enable a GPP (OUT) pin -+* -+* DESCRIPTION: -+* -+* INPUT: -+* group - GPP group number -+* mask - 32bit mask value. Each set bit in the mask means that the type -+* of corresponding GPP will be set. Other GPPs are ignored. -+* value - 32bit value that describes GPP type per pin. -+* -+* OUTPUT: -+* None. -+* -+* EXAMPLE: -+* Set GPP8 to input and GPP15 to output. -+* mvGppTypeSet(0, (GPP8 | GPP15), -+* ((MV_GPP_IN & GPP8) | (MV_GPP_OUT & GPP15)) ); -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvGppTypeSet(MV_U32 group, MV_U32 mask, MV_U32 value) -+{ -+ if (group >= MV_GPP_MAX_GROUP) -+ { -+ DB(mvOsPrintf("mvGppTypeSet: ERR. invalid group number \n")); -+ return MV_BAD_PARAM; -+ } -+ -+ gppRegSet(group, GPP_DATA_OUT_EN_REG(group), mask, value); -+ -+ /* Workaround for Erratum FE-MISC-70*/ -+ if(mvCtrlRevGet()==MV_88F6XXX_A0_REV && (group == 1)) -+ { -+ mask &= 0x2; -+ gppRegSet(0, GPP_DATA_OUT_EN_REG(0), mask, value); -+ } /*End of WA*/ -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvGppBlinkEn - Set a GPP (IN) Pin list to blink every ~100ms -+* -+* DESCRIPTION: -+* -+* INPUT: -+* group - GPP group number -+* mask - 32bit mask value. Each set bit in the mask means that the type -+* of corresponding GPP will be set. Other GPPs are ignored. -+* value - 32bit value that describes GPP blink per pin. -+* -+* OUTPUT: -+* None. -+* -+* EXAMPLE: -+* Set GPP8 to be static and GPP15 to be blinking. -+* mvGppBlinkEn(0, (GPP8 | GPP15), -+* ((MV_GPP_OUT_STATIC & GPP8) | (MV_GPP_OUT_BLINK & GPP15)) ); -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvGppBlinkEn(MV_U32 group, MV_U32 mask, MV_U32 value) -+{ -+ if (group >= MV_GPP_MAX_GROUP) -+ { -+ DB(mvOsPrintf("mvGppBlinkEn: ERR. invalid group number \n")); -+ return MV_BAD_PARAM; -+ } -+ -+ gppRegSet(group, GPP_BLINK_EN_REG(group), mask, value); -+ -+ return MV_OK; -+ -+} -+/******************************************************************************* -+* mvGppPolaritySet - Set a GPP (IN) Pin list Polarity mode -+* -+* DESCRIPTION: -+* -+* INPUT: -+* group - GPP group number -+* mask - 32bit mask value. Each set bit in the mask means that the type -+* of corresponding GPP will be set. Other GPPs are ignored. -+* value - 32bit value that describes GPP polarity per pin. -+* -+* OUTPUT: -+* None. -+* -+* EXAMPLE: -+* Set GPP8 to the actual pin value and GPP15 to be inverted. -+* mvGppPolaritySet(0, (GPP8 | GPP15), -+* ((MV_GPP_IN_ORIGIN & GPP8) | (MV_GPP_IN_INVERT & GPP15)) ); -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvGppPolaritySet(MV_U32 group, MV_U32 mask, MV_U32 value) -+{ -+ if (group >= MV_GPP_MAX_GROUP) -+ { -+ DB(mvOsPrintf("mvGppPolaritySet: ERR. invalid group number \n")); -+ return MV_BAD_PARAM; -+ } -+ -+ gppRegSet(group, GPP_DATA_IN_POL_REG(group), mask, value); -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvGppPolarityGet - Get a value of relevant bits from GPP Polarity register. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* group - GPP group number -+* mask - 32bit mask value. Each set bit in the mask means that the -+* returned value is valid for it. -+* -+* OUTPUT: -+* None. -+* -+* EXAMPLE: -+* Get GPP8 and GPP15 value. -+* mvGppPolarityGet(0, (GPP8 | GPP15)); -+* -+* RETURN: -+* 32bit value that describes GPP polatity mode per pin. -+* -+*******************************************************************************/ -+MV_U32 mvGppPolarityGet(MV_U32 group, MV_U32 mask) -+{ -+ MV_U32 regVal; -+ -+ if (group >= MV_GPP_MAX_GROUP) -+ { -+ DB(mvOsPrintf("mvGppActiveSet: Error invalid group number \n")); -+ return MV_ERROR; -+ } -+ regVal = MV_REG_READ(GPP_DATA_IN_POL_REG(group)); -+ -+ return (regVal & mask); -+} -+ -+/******************************************************************************* -+* mvGppValueGet - Get a GPP Pin list value. -+* -+* DESCRIPTION: -+* This function get GPP value. -+* -+* INPUT: -+* group - GPP group number -+* mask - 32bit mask value. Each set bit in the mask means that the -+* returned value is valid for it. -+* -+* OUTPUT: -+* None. -+* -+* EXAMPLE: -+* Get GPP8 and GPP15 value. -+* mvGppValueGet(0, (GPP8 | GPP15)); -+* -+* RETURN: -+* 32bit value that describes GPP activity mode per pin. -+* -+*******************************************************************************/ -+MV_U32 mvGppValueGet(MV_U32 group, MV_U32 mask) -+{ -+ MV_U32 gppData; -+ -+ gppData = MV_REG_READ(GPP_DATA_IN_REG(group)); -+ -+ gppData &= mask; -+ -+ return gppData; -+ -+} -+ -+/******************************************************************************* -+* mvGppValueSet - Set a GPP Pin list value. -+* -+* DESCRIPTION: -+* This function set value for given GPP pin list. -+* -+* INPUT: -+* group - GPP group number -+* mask - 32bit mask value. Each set bit in the mask means that the -+* value of corresponding GPP will be set accordingly. Other GPP -+* are not affected. -+* value - 32bit value that describes GPP value per pin. -+* -+* OUTPUT: -+* None. -+* -+* EXAMPLE: -+* Set GPP8 value of '0' and GPP15 value of '1'. -+* mvGppActiveSet(0, (GPP8 | GPP15), ((0 & GPP8) | (GPP15)) ); -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvGppValueSet (MV_U32 group, MV_U32 mask, MV_U32 value) -+{ -+ MV_U32 outEnable, tmp; -+ MV_U32 i; -+ -+ if (group >= MV_GPP_MAX_GROUP) -+ { -+ DB(mvOsPrintf("mvGppValueSet: Error invalid group number \n")); -+ return MV_BAD_PARAM; -+ } -+ -+ /* verify that the gpp pin is configured as output */ -+ /* Note that in the register out enabled -> bit = '0'. */ -+ outEnable = ~MV_REG_READ(GPP_DATA_OUT_EN_REG(group)); -+ -+ /* Workaround for Erratum FE-MISC-70*/ -+ if(mvCtrlRevGet()==MV_88F6XXX_A0_REV && (group == 1)) -+ { -+ tmp = ~MV_REG_READ(GPP_DATA_OUT_EN_REG(0)); -+ outEnable &= 0xfffffffd; -+ outEnable |= (tmp & 0x2); -+ } /*End of WA*/ -+ -+ for (i = 0 ; i < 32 ;i++) -+ { -+ if (((mask & (1 << i)) & (outEnable & (1 << i))) != (mask & (1 << i))) -+ { -+ mvOsPrintf("mvGppValueSet: Err. An attempt to set output "\ -+ "value to GPP %d in input mode.\n", i); -+ return MV_ERROR; -+ } -+ } -+ -+ gppRegSet(group, GPP_DATA_OUT_REG(group), mask, value); -+ -+ return MV_OK; -+ -+} -+/******************************************************************************* -+* gppRegSet - Set a specific GPP pin on a specific GPP register -+* -+* DESCRIPTION: -+* This function set a specific GPP pin on a specific GPP register -+* -+* INPUT: -+* regOffs - GPP Register offset -+* group - GPP group number -+* mask - 32bit mask value. Each set bit in the mask means that the -+* value of corresponding GPP will be set accordingly. Other GPP -+* are not affected. -+* value - 32bit value that describes GPP value per pin. -+* -+* OUTPUT: -+* None. -+* -+* EXAMPLE: -+* Set GPP8 value of '0' and GPP15 value of '1'. -+* mvGppActiveSet(0, (GPP8 | GPP15), ((0 & GPP8) | (1 & GPP15)) ); -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+static MV_VOID gppRegSet (MV_U32 group, MV_U32 regOffs,MV_U32 mask,MV_U32 value) -+{ -+ MV_U32 gppData; -+ -+ gppData = MV_REG_READ(regOffs); -+ -+ gppData &= ~mask; -+ -+ gppData |= (value & mask); -+ -+ MV_REG_WRITE(regOffs, gppData); -+} -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,118 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvGppH -+#define __INCmvGppH -+ -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+#include "gpp/mvGppRegs.h" -+ -+/* These macros describes the GPP type. Each of the GPPs pins can */ -+/* be assigned to act as a general purpose input or output pin. */ -+#define MV_GPP_IN 0xFFFFFFFF /* GPP input */ -+#define MV_GPP_OUT 0 /* GPP output */ -+ -+ -+/* These macros describes the GPP Out Enable. */ -+#define MV_GPP_OUT_DIS 0xFFFFFFFF /* Out pin disabled*/ -+#define MV_GPP_OUT_EN 0 /* Out pin enabled*/ -+ -+/* These macros describes the GPP Out Blinking. */ -+/* When set and the corresponding bit in GPIO Data Out Enable Control */ -+/* Register is enabled, the GPIO pin blinks every ~100 ms (a period of */ -+/* 2^24 TCLK clocks). */ -+#define MV_GPP_OUT_BLINK 0xFFFFFFFF /* Out pin blinking*/ -+#define MV_GPP_OUT_STATIC 0 /* Out pin static*/ -+ -+ -+/* These macros describes the GPP Polarity. */ -+/* When set to 1 GPIO Data In Register reflects the inverted value of the */ -+/* corresponding pin. */ -+ -+#define MV_GPP_IN_INVERT 0xFFFFFFFF /* Inverted value is got*/ -+#define MV_GPP_IN_ORIGIN 0 /* original value is got*/ -+ -+/* mvGppTypeSet - Set PP pin mode (IN or OUT) */ -+MV_STATUS mvGppTypeSet(MV_U32 group, MV_U32 mask, MV_U32 value); -+ -+/* mvGppBlinkEn - Set a GPP (IN) Pin list to blink every ~100ms */ -+MV_STATUS mvGppBlinkEn(MV_U32 group, MV_U32 mask, MV_U32 value); -+ -+/* mvGppPolaritySet - Set a GPP (IN) Pin list Polarity mode. */ -+MV_STATUS mvGppPolaritySet(MV_U32 group, MV_U32 mask, MV_U32 value); -+ -+/* mvGppPolarityGet - Get the Polarity of a GPP Pin */ -+MV_U32 mvGppPolarityGet(MV_U32 group, MV_U32 mask); -+ -+/* mvGppValueGet - Get a GPP Pin list value.*/ -+MV_U32 mvGppValueGet(MV_U32 group, MV_U32 mask); -+ -+ -+/* mvGppValueSet - Set a GPP Pin list value. */ -+MV_STATUS mvGppValueSet (MV_U32 group, MV_U32 mask, MV_U32 value); -+ -+#endif /* #ifndef __INCmvGppH */ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGppRegs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGppRegs.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGppRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGppRegs.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,116 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvGppRegsH -+#define __INCmvGppRegsH -+ -+#define MV_GPP0 BIT0 -+#define MV_GPP1 BIT1 -+#define MV_GPP2 BIT2 -+#define MV_GPP3 BIT3 -+#define MV_GPP4 BIT4 -+#define MV_GPP5 BIT5 -+#define MV_GPP6 BIT6 -+#define MV_GPP7 BIT7 -+#define MV_GPP8 BIT8 -+#define MV_GPP9 BIT9 -+#define MV_GPP10 BIT10 -+#define MV_GPP11 BIT11 -+#define MV_GPP12 BIT12 -+#define MV_GPP13 BIT13 -+#define MV_GPP14 BIT14 -+#define MV_GPP15 BIT15 -+#define MV_GPP16 BIT16 -+#define MV_GPP17 BIT17 -+#define MV_GPP18 BIT18 -+#define MV_GPP19 BIT19 -+#define MV_GPP20 BIT20 -+#define MV_GPP21 BIT21 -+#define MV_GPP22 BIT22 -+#define MV_GPP23 BIT23 -+#define MV_GPP24 BIT24 -+#define MV_GPP25 BIT25 -+#define MV_GPP26 BIT26 -+#define MV_GPP27 BIT27 -+#define MV_GPP28 BIT28 -+#define MV_GPP29 BIT29 -+#define MV_GPP30 BIT30 -+#define MV_GPP31 BIT31 -+ -+ -+/* registers offsets */ -+ -+#define GPP_DATA_OUT_REG(grp) ((grp == 0) ? 0x10100 : 0x10140) -+#define GPP_DATA_OUT_EN_REG(grp) ((grp == 0) ? 0x10104 : 0x10144) -+#define GPP_BLINK_EN_REG(grp) ((grp == 0) ? 0x10108 : 0x10148) -+#define GPP_DATA_IN_POL_REG(grp) ((grp == 0) ? 0x1010C : 0x1014c) -+#define GPP_DATA_IN_REG(grp) ((grp == 0) ? 0x10110 : 0x10150) -+#define GPP_INT_CAUSE_REG(grp) ((grp == 0) ? 0x10114 : 0x10154) -+#define GPP_INT_MASK_REG(grp) ((grp == 0) ? 0x10118 : 0x10158) -+#define GPP_INT_LVL_REG(grp) ((grp == 0) ? 0x1011c : 0x1015c) -+ -+#define GPP_DATA_OUT_SET_REG 0x10120 -+#define GPP_DATA_OUT_CLEAR_REG 0x10124 -+ -+#endif /* #ifndef __INCmvGppRegsH */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvCompVer.txt linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvCompVer.txt ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvCompVer.txt 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvCompVer.txt 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,4 @@ -+Global HAL Version: FEROCEON_HAL_3_1_7 -+Unit HAL Version: 3.1.2 -+Description: This component includes an implementation of the unit HAL drivers -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,1047 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#include "pci/mvPci.h" -+ -+#include "ctrlEnv/mvCtrlEnvLib.h" -+ -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+ -+ -+MV_VOID mvPciHalInit(MV_U32 pciIf, MV_PCI_MOD pciIfmod) -+{ -+ if (MV_PCI_MOD_HOST == pciIfmod) -+ { -+ -+ mvPciLocalBusNumSet(pciIf, PCI_HOST_BUS_NUM(pciIf)); -+ mvPciLocalDevNumSet(pciIf, PCI_HOST_DEV_NUM(pciIf)); -+ -+ /* Local device master Enable */ -+ mvPciMasterEnable(pciIf, MV_TRUE); -+ -+ /* Local device slave Enable */ -+ mvPciSlaveEnable(pciIf, mvPciLocalBusNumGet(pciIf), -+ mvPciLocalDevNumGet(pciIf), MV_TRUE); -+ } -+ /* enable CPU-2-PCI ordering */ -+ MV_REG_BIT_SET(PCI_CMD_REG(0), PCR_CPU_TO_PCI_ORDER_EN); -+} -+ -+/******************************************************************************* -+* mvPciCommandSet - Set PCI comman register value. -+* -+* DESCRIPTION: -+* This function sets a given PCI interface with its command register -+* value. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* command - 32bit value to be written to comamnd register. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM if pciIf is not in range otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciCommandSet(MV_U32 pciIf, MV_U32 command) -+{ -+ MV_U32 locBusNum, locDevNum, regVal; -+ -+ locBusNum = mvPciLocalBusNumGet(pciIf); -+ locDevNum = mvPciLocalDevNumGet(pciIf); -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciCommandSet: ERR. Invalid PCI IF num %d\n", pciIf); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Set command register */ -+ MV_REG_WRITE(PCI_CMD_REG(pciIf), command); -+ -+ /* Upodate device max outstanding split tarnsaction */ -+ if ((command & PCR_CPU_TO_PCI_ORDER_EN) && -+ (command & PCR_PCI_TO_CPU_ORDER_EN)) -+ { -+ /* Read PCI-X command register */ -+ regVal = mvPciConfigRead (pciIf, locBusNum, locDevNum, 0, PCIX_COMMAND); -+ -+ /* clear bits 22:20 */ -+ regVal &= 0xff8fffff; -+ -+ /* set reset value */ -+ regVal |= (0x3 << 20); -+ -+ /* Write back the value */ -+ mvPciConfigWrite (pciIf, locBusNum, locDevNum, 0, PCIX_COMMAND, regVal); -+ } -+ -+ return MV_OK; -+ -+ -+} -+ -+ -+/******************************************************************************* -+* mvPciModeGet - Get PCI interface mode. -+* -+* DESCRIPTION: -+* This function returns the given PCI interface mode. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* -+* OUTPUT: -+* pPciMode - Pointer to PCI mode structure. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciModeGet(MV_U32 pciIf, MV_PCI_MODE *pPciMode) -+{ -+ MV_U32 pciMode; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciModeGet: ERR. Invalid PCI interface %d\n", pciIf); -+ return MV_BAD_PARAM; -+ } -+ if (NULL == pPciMode) -+ { -+ mvOsPrintf("mvPciModeGet: ERR. pPciMode = NULL \n"); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Read pci mode register */ -+ pciMode = MV_REG_READ(PCI_MODE_REG(pciIf)); -+ -+ switch (pciMode & PMR_PCI_MODE_MASK) -+ { -+ case PMR_PCI_MODE_CONV: -+ pPciMode->pciType = MV_PCI_CONV; -+ -+ if (MV_REG_READ(PCI_DLL_CTRL_REG(pciIf)) & PDC_DLL_EN) -+ { -+ pPciMode->pciSpeed = 66000000; /* 66MHZ */ -+ } -+ else -+ { -+ pPciMode->pciSpeed = 33000000; /* 33MHZ */ -+ } -+ -+ break; -+ -+ case PMR_PCI_MODE_PCIX_66MHZ: -+ pPciMode->pciType = MV_PCIX; -+ pPciMode->pciSpeed = 66000000; /* 66MHZ */ -+ break; -+ -+ case PMR_PCI_MODE_PCIX_100MHZ: -+ pPciMode->pciType = MV_PCIX; -+ pPciMode->pciSpeed = 100000000; /* 100MHZ */ -+ break; -+ -+ case PMR_PCI_MODE_PCIX_133MHZ: -+ pPciMode->pciType = MV_PCIX; -+ pPciMode->pciSpeed = 133000000; /* 133MHZ */ -+ break; -+ -+ default: -+ { -+ mvOsPrintf("mvPciModeGet: ERR. Non existing mode !!\n"); -+ return MV_ERROR; -+ } -+ } -+ -+ switch (pciMode & PMR_PCI_64_MASK) -+ { -+ case PMR_PCI_64_64BIT: -+ pPciMode->pciWidth = MV_PCI_64; -+ break; -+ -+ case PMR_PCI_64_32BIT: -+ pPciMode->pciWidth = MV_PCI_32; -+ break; -+ -+ default: -+ { -+ mvOsPrintf("mvPciModeGet: ERR. Non existing mode !!\n"); -+ return MV_ERROR; -+ } -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvPciRetrySet - Set PCI retry counters -+* -+* DESCRIPTION: -+* This function specifies the number of times the PCI controller -+* retries a transaction before it quits. -+* Applies to the PCI Master when acting as a requester. -+* Applies to the PCI slave when acting as a completer (PCI-X mode). -+* A 0x00 value means a "retry forever". -+* -+* INPUT: -+* pciIf - PCI interface number. -+* counter - Number of times PCI controller retry. Use counter value -+* up to PRR_RETRY_CNTR_MAX. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciRetrySet(MV_U32 pciIf, MV_U32 counter) -+{ -+ MV_U32 pciRetry; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciRetrySet: ERR. Invalid PCI interface %d\n", pciIf); -+ return MV_BAD_PARAM; -+ } -+ -+ if (counter >= PRR_RETRY_CNTR_MAX) -+ { -+ mvOsPrintf("mvPciRetrySet: ERR. Invalid counter: %d\n", counter); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ /* Reading PCI retry register */ -+ pciRetry = MV_REG_READ(PCI_RETRY_REG(pciIf)); -+ -+ pciRetry &= ~PRR_RETRY_CNTR_MASK; -+ -+ pciRetry |= (counter << PRR_RETRY_CNTR_OFFS); -+ -+ /* write new value */ -+ MV_REG_WRITE(PCI_RETRY_REG(pciIf), pciRetry); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPciDiscardTimerSet - Set PCI discard timer -+* -+* DESCRIPTION: -+* This function set PCI discard timer. -+* In conventional PCI mode: -+* Specifies the number of PCLK cycles the PCI slave keeps a non-accessed -+* read buffers (non-completed delayed read) before invalidate the buffer. -+* Set to '0' to disable the timer. The PCI slave waits for delayed -+* read completion forever. -+* In PCI-X mode: -+* Specifies the number of PCLK cycles the PCI master waits for split -+* completion transaction, before it invalidates the pre-allocated read -+* buffer. -+* Set to '0' to disable the timer. The PCI master waits for split -+* completion forever. -+* NOTE: Must be set to a number greater than MV_PCI_MAX_DISCARD_CLK, -+* unless using the "wait for ever" setting 0x0. -+* NOTE: Must not be updated while there are pending read requests. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* pClkCycles - Number of PCI clock cycles. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciDiscardTimerSet(MV_U32 pciIf, MV_U32 pClkCycles) -+{ -+ MV_U32 pciDiscardTimer; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciDiscardTimerSet: ERR. Invalid PCI interface %d\n", -+ pciIf); -+ return MV_BAD_PARAM; -+ } -+ -+ if (pClkCycles >= PDTR_TIMER_MIN) -+ { -+ mvOsPrintf("mvPciDiscardTimerSet: ERR. Invalid Clk value: %d\n", -+ pClkCycles); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ /* Read PCI Discard Timer */ -+ pciDiscardTimer = MV_REG_READ(PCI_DISCARD_TIMER_REG(pciIf)); -+ -+ pciDiscardTimer &= ~PDTR_TIMER_MASK; -+ -+ pciDiscardTimer |= (pClkCycles << PDTR_TIMER_OFFS); -+ -+ /* Write new value */ -+ MV_REG_WRITE(PCI_DISCARD_TIMER_REG(pciIf), pciDiscardTimer); -+ -+ return MV_OK; -+ -+} -+ -+/* PCI Arbiter routines */ -+ -+/******************************************************************************* -+* mvPciArbEnable - PCI arbiter enable/disable -+* -+* DESCRIPTION: -+* This fuction enable/disables a given PCI interface arbiter. -+* NOTE: Arbiter setting can not be changed while in work. It should only -+* be set once. -+* INPUT: -+* pciIf - PCI interface number. -+* enable - Enable/disable parameter. If enable = MV_TRUE then enable. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvPciArbEnable(MV_U32 pciIf, MV_BOOL enable) -+{ -+ MV_U32 regVal; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciArbEnable: ERR. Invalid PCI interface %d\n", pciIf); -+ return MV_ERROR; -+ } -+ -+ /* Set PCI Arbiter Control register according to default configuration */ -+ regVal = MV_REG_READ(PCI_ARBITER_CTRL_REG(pciIf)); -+ -+ /* Make sure arbiter disabled before changing its values */ -+ MV_REG_BIT_RESET(PCI_ARBITER_CTRL_REG(pciIf), PACR_ARB_ENABLE); -+ -+ regVal &= ~PCI_ARBITER_CTRL_DEFAULT_MASK; -+ -+ regVal |= PCI_ARBITER_CTRL_DEFAULT; /* Set default configuration */ -+ -+ if (MV_TRUE == enable) -+ { -+ regVal |= PACR_ARB_ENABLE; -+ } -+ else -+ { -+ regVal &= ~PACR_ARB_ENABLE; -+ } -+ -+ /* Write to register */ -+ MV_REG_WRITE(PCI_ARBITER_CTRL_REG(pciIf), regVal); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPciArbParkDis - Disable arbiter parking on agent -+* -+* DESCRIPTION: -+* This function disables the PCI arbiter from parking on the given agent -+* list. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* pciAgentMask - When a bit in the mask is set to '1', parking on -+* the associated PCI master is disabled. Mask bit -+* refers to bit 0 - 6. For example disable parking on PCI -+* agent 3 set pciAgentMask 0x4 (bit 3 is set). -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvPciArbParkDis(MV_U32 pciIf, MV_U32 pciAgentMask) -+{ -+ MV_U32 pciArbiterCtrl; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciArbParkDis: ERR. Invalid PCI interface %d\n", pciIf); -+ return MV_ERROR; -+ } -+ -+ /* Reading Arbiter Control register */ -+ pciArbiterCtrl = MV_REG_READ(PCI_ARBITER_CTRL_REG(pciIf)); -+ -+ /* Arbiter must be disabled before changing parking */ -+ MV_REG_BIT_RESET(PCI_ARBITER_CTRL_REG(pciIf), PACR_ARB_ENABLE); -+ -+ /* do the change */ -+ pciArbiterCtrl &= ~PACR_PARK_DIS_MASK; -+ pciArbiterCtrl |= (pciAgentMask << PACR_PARK_DIS_OFFS); -+ -+ /* writing new value ( if th earbiter was enabled before the change */ -+ /* here it will be reenabled */ -+ MV_REG_WRITE(PCI_ARBITER_CTRL_REG(pciIf), pciArbiterCtrl); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPciArbBrokDetectSet - Set PCI arbiter broken detection -+* -+* DESCRIPTION: -+* This function sets the maximum number of cycles that the arbiter -+* waits for a PCI master to respond to its grant assertion. If a -+* PCI agent fails to respond within this time, the PCI arbiter aborts -+* the transaction and performs a new arbitration cycle. -+* NOTE: Value must be greater than '1' for conventional PCI and -+* greater than '5' for PCI-X. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* pClkCycles - Number of PCI clock cycles. If equal to '0' the broken -+* master detection is disabled. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciArbBrokDetectSet(MV_U32 pciIf, MV_U32 pClkCycles) -+{ -+ MV_U32 pciArbiterCtrl; -+ MV_U32 pciMode; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciArbBrokDetectSet: ERR. Invalid PCI interface %d\n", -+ pciIf); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Checking PCI mode and if pClkCycles is legal value */ -+ pciMode = MV_REG_READ(PCI_MODE_REG(pciIf)); -+ pciMode &= PMR_PCI_MODE_MASK; -+ -+ if (PMR_PCI_MODE_CONV == pciMode) -+ { -+ if (pClkCycles < PACR_BROKEN_VAL_CONV_MIN) -+ return MV_ERROR; -+ } -+ else -+ { -+ if (pClkCycles < PACR_BROKEN_VAL_PCIX_MIN) -+ return MV_ERROR; -+ } -+ -+ pClkCycles <<= PACR_BROKEN_VAL_OFFS; -+ -+ /* Reading Arbiter Control register */ -+ pciArbiterCtrl = MV_REG_READ(PCI_ARBITER_CTRL_REG(pciIf)); -+ pciArbiterCtrl &= ~PACR_BROKEN_VAL_MASK; -+ pciArbiterCtrl |= pClkCycles; -+ -+ /* Arbiter must be disabled before changing broken detection */ -+ MV_REG_BIT_RESET(PCI_ARBITER_CTRL_REG(pciIf), PACR_ARB_ENABLE); -+ -+ /* writing new value ( if th earbiter was enabled before the change */ -+ /* here it will be reenabled */ -+ -+ MV_REG_WRITE(PCI_ARBITER_CTRL_REG(pciIf), pciArbiterCtrl); -+ -+ return MV_OK; -+} -+ -+/* PCI configuration space read write */ -+ -+/******************************************************************************* -+* mvPciConfigRead - Read from configuration space -+* -+* DESCRIPTION: -+* This function performs a 32 bit read from PCI configuration space. -+* It supports both type 0 and type 1 of Configuration Transactions -+* (local and over bridge). In order to read from local bus segment, use -+* bus number retrieved from mvPciLocalBusNumGet(). Other bus numbers -+* will result configuration transaction of type 1 (over bridge). -+* -+* INPUT: -+* pciIf - PCI interface number. -+* bus - PCI segment bus number. -+* dev - PCI device number. -+* func - Function number. -+* regOffs - Register offset. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit register data, 0xffffffff on error -+* -+*******************************************************************************/ -+MV_U32 mvPciConfigRead (MV_U32 pciIf, MV_U32 bus, MV_U32 dev, MV_U32 func, -+ MV_U32 regOff) -+{ -+ MV_U32 pciData = 0; -+ -+ /* Parameter checking */ -+ if (PCI_DEFAULT_IF != pciIf) -+ { -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciConfigRead: ERR. Invalid PCI interface %d\n",pciIf); -+ return 0xFFFFFFFF; -+ } -+ } -+ -+ if (dev >= MAX_PCI_DEVICES) -+ { -+ DB(mvOsPrintf("mvPciConfigRead: ERR. device number illigal %d\n", dev)); -+ return 0xFFFFFFFF; -+ } -+ -+ if (func >= MAX_PCI_FUNCS) -+ { -+ DB(mvOsPrintf("mvPciConfigRead: ERR. function number illigal %d\n", func)); -+ return 0xFFFFFFFF; -+ } -+ -+ if (bus >= MAX_PCI_BUSSES) -+ { -+ DB(mvOsPrintf("mvPciConfigRead: ERR. bus number illigal %d\n", bus)); -+ return MV_ERROR; -+ } -+ -+ -+ /* Creating PCI address to be passed */ -+ pciData |= (bus << PCAR_BUS_NUM_OFFS); -+ pciData |= (dev << PCAR_DEVICE_NUM_OFFS); -+ pciData |= (func << PCAR_FUNC_NUM_OFFS); -+ pciData |= (regOff & PCAR_REG_NUM_MASK); -+ -+ pciData |= PCAR_CONFIG_EN; -+ -+ /* Write the address to the PCI configuration address register */ -+ MV_REG_WRITE(PCI_CONFIG_ADDR_REG(pciIf), pciData); -+ -+ /* In order to let the PCI controller absorbed the address of the read */ -+ /* transaction we perform a validity check that the address was written */ -+ if(pciData != MV_REG_READ(PCI_CONFIG_ADDR_REG(pciIf))) -+ { -+ return MV_ERROR; -+ } -+ /* Read the Data returned in the PCI Data register */ -+ pciData = MV_REG_READ(PCI_CONFIG_DATA_REG(pciIf)); -+ -+ return pciData; -+} -+ -+/******************************************************************************* -+* mvPciConfigWrite - Write to configuration space -+* -+* DESCRIPTION: -+* This function performs a 32 bit write to PCI configuration space. -+* It supports both type 0 and type 1 of Configuration Transactions -+* (local and over bridge). In order to write to local bus segment, use -+* bus number retrieved from mvPciLocalBusNumGet(). Other bus numbers -+* will result configuration transaction of type 1 (over bridge). -+* -+* INPUT: -+* pciIf - PCI interface number. -+* bus - PCI segment bus number. -+* dev - PCI device number. -+* func - Function number. -+* regOffs - Register offset. -+* data - 32bit data. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciConfigWrite(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data) -+{ -+ MV_U32 pciData = 0; -+ -+ /* Parameter checking */ -+ if (PCI_DEFAULT_IF != pciIf) -+ { -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciConfigWrite: ERR. Invalid PCI interface %d\n", -+ pciIf); -+ return 0xFFFFFFFF; -+ } -+ } -+ -+ if (dev >= MAX_PCI_DEVICES) -+ { -+ mvOsPrintf("mvPciConfigWrite: ERR. device number illigal %d\n",dev); -+ return MV_BAD_PARAM; -+ } -+ -+ if (func >= MAX_PCI_FUNCS) -+ { -+ mvOsPrintf("mvPciConfigWrite: ERR. function number illigal %d\n", func); -+ return MV_ERROR; -+ } -+ -+ if (bus >= MAX_PCI_BUSSES) -+ { -+ mvOsPrintf("mvPciConfigWrite: ERR. bus number illigal %d\n", bus); -+ return MV_ERROR; -+ } -+ -+ /* Creating PCI address to be passed */ -+ pciData |= (bus << PCAR_BUS_NUM_OFFS); -+ pciData |= (dev << PCAR_DEVICE_NUM_OFFS); -+ pciData |= (func << PCAR_FUNC_NUM_OFFS); -+ pciData |= (regOff & PCAR_REG_NUM_MASK); -+ -+ pciData |= PCAR_CONFIG_EN; -+ -+ /* Write the address to the PCI configuration address register */ -+ MV_REG_WRITE(PCI_CONFIG_ADDR_REG(pciIf), pciData); -+ -+ /* In order to let the PCI controller absorbed the address of the read */ -+ /* transaction we perform a validity check that the address was written */ -+ if(pciData != MV_REG_READ(PCI_CONFIG_ADDR_REG(pciIf))) -+ { -+ return MV_ERROR; -+ } -+ -+ /* Write the Data passed to the PCI Data register */ -+ MV_REG_WRITE(PCI_CONFIG_DATA_REG(pciIf), data); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvPciMasterEnable - Enable/disale PCI interface master transactions. -+* -+* DESCRIPTION: -+* This function performs read modified write to PCI command status -+* (offset 0x4) to set/reset bit 2. After this bit is set, the PCI -+* master is allowed to gain ownership on the bus, otherwise it is -+* incapable to do so. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciMasterEnable(MV_U32 pciIf, MV_BOOL enable) -+{ -+ MV_U32 pciCommandStatus; -+ MV_U32 RegOffs; -+ MV_U32 localBus; -+ MV_U32 localDev; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciMasterEnable: ERR. Invalid PCI interface %d\n", pciIf); -+ return MV_ERROR; -+ } -+ -+ localBus = mvPciLocalBusNumGet(pciIf); -+ localDev = mvPciLocalDevNumGet(pciIf); -+ -+ RegOffs = PCI_STATUS_AND_COMMAND; -+ -+ pciCommandStatus = mvPciConfigRead(pciIf, localBus, localDev, 0, RegOffs); -+ -+ if (MV_TRUE == enable) -+ { -+ pciCommandStatus |= PSCR_MASTER_EN; -+ } -+ else -+ { -+ pciCommandStatus &= ~PSCR_MASTER_EN; -+ } -+ -+ mvPciConfigWrite(pciIf, localBus, localDev, 0, RegOffs, pciCommandStatus); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPciSlaveEnable - Enable/disale PCI interface slave transactions. -+* -+* DESCRIPTION: -+* This function performs read modified write to PCI command status -+* (offset 0x4) to set/reset bit 0 and 1. After those bits are set, -+* the PCI slave is allowed to respond to PCI IO space access (bit 0) -+* and PCI memory space access (bit 1). -+* -+* INPUT: -+* pciIf - PCI interface number. -+* dev - PCI device number. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciSlaveEnable(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, MV_BOOL enable) -+{ -+ MV_U32 pciCommandStatus; -+ MV_U32 RegOffs; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciSlaveEnable: ERR. Invalid PCI interface %d\n", pciIf); -+ return MV_BAD_PARAM; -+ } -+ if (dev >= MAX_PCI_DEVICES) -+ { -+ mvOsPrintf("mvPciLocalDevNumSet: ERR. device number illigal %d\n", dev); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ RegOffs = PCI_STATUS_AND_COMMAND; -+ -+ pciCommandStatus=mvPciConfigRead(pciIf, bus, dev, 0, RegOffs); -+ -+ if (MV_TRUE == enable) -+ { -+ pciCommandStatus |= (PSCR_IO_EN | PSCR_MEM_EN); -+ } -+ else -+ { -+ pciCommandStatus &= ~(PSCR_IO_EN | PSCR_MEM_EN); -+ } -+ -+ mvPciConfigWrite(pciIf, bus, dev, 0, RegOffs, pciCommandStatus); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvPciLocalBusNumSet - Set PCI interface local bus number. -+* -+* DESCRIPTION: -+* This function sets given PCI interface its local bus number. -+* Note: In case the PCI interface is PCI-X, the information is read-only. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* busNum - Bus number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_NOT_ALLOWED in case PCI interface is PCI-X. -+* MV_BAD_PARAM on bad parameters , -+* otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciLocalBusNumSet(MV_U32 pciIf, MV_U32 busNum) -+{ -+ MV_U32 pciP2PConfig; -+ MV_PCI_MODE pciMode; -+ MV_U32 localBus; -+ MV_U32 localDev; -+ -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciLocalBusNumSet: ERR. Invalid PCI interface %d\n",pciIf); -+ return MV_BAD_PARAM; -+ } -+ if (busNum >= MAX_PCI_BUSSES) -+ { -+ mvOsPrintf("mvPciLocalBusNumSet: ERR. bus number illigal %d\n", busNum); -+ return MV_ERROR; -+ -+ } -+ -+ localBus = mvPciLocalBusNumGet(pciIf); -+ localDev = mvPciLocalDevNumGet(pciIf); -+ -+ -+ /* PCI interface mode */ -+ mvPciModeGet(pciIf, &pciMode); -+ -+ /* if PCI type is PCI-X then it is not allowed to change the dev number */ -+ if (MV_PCIX == pciMode.pciType) -+ { -+ pciP2PConfig = mvPciConfigRead(pciIf, localBus, localDev, 0, PCIX_STATUS ); -+ -+ pciP2PConfig &= ~PXS_BN_MASK; -+ -+ pciP2PConfig |= (busNum << PXS_BN_OFFS) & PXS_BN_MASK; -+ -+ mvPciConfigWrite(pciIf, localBus, localDev, 0, PCIX_STATUS,pciP2PConfig ); -+ -+ } -+ else -+ { -+ pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); -+ -+ pciP2PConfig &= ~PPCR_BUS_NUM_MASK; -+ -+ pciP2PConfig |= (busNum << PPCR_BUS_NUM_OFFS) & PPCR_BUS_NUM_MASK; -+ -+ MV_REG_WRITE(PCI_P2P_CONFIG_REG(pciIf), pciP2PConfig); -+ -+ } -+ -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPciLocalBusNumGet - Get PCI interface local bus number. -+* -+* DESCRIPTION: -+* This function gets the local bus number of a given PCI interface. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Local bus number.0xffffffff on Error -+* -+*******************************************************************************/ -+MV_U32 mvPciLocalBusNumGet(MV_U32 pciIf) -+{ -+ MV_U32 pciP2PConfig; -+ -+ /* Parameter checking */ -+ if (PCI_DEFAULT_IF != pciIf) -+ { -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciLocalBusNumGet: ERR. Invalid PCI interface %d\n", -+ pciIf); -+ return 0xFFFFFFFF; -+ } -+ } -+ -+ pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); -+ pciP2PConfig &= PPCR_BUS_NUM_MASK; -+ return (pciP2PConfig >> PPCR_BUS_NUM_OFFS); -+} -+ -+ -+/******************************************************************************* -+* mvPciLocalDevNumSet - Set PCI interface local device number. -+* -+* DESCRIPTION: -+* This function sets given PCI interface its local device number. -+* Note: In case the PCI interface is PCI-X, the information is read-only. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* devNum - Device number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_NOT_ALLOWED in case PCI interface is PCI-X. MV_BAD_PARAM on bad parameters , -+* otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciLocalDevNumSet(MV_U32 pciIf, MV_U32 devNum) -+{ -+ MV_U32 pciP2PConfig; -+ MV_PCI_MODE pciMode; -+ MV_U32 localBus; -+ MV_U32 localDev; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciLocalDevNumSet: ERR. Invalid PCI interface %d\n",pciIf); -+ return MV_BAD_PARAM; -+ } -+ if (devNum >= MAX_PCI_DEVICES) -+ { -+ mvOsPrintf("mvPciLocalDevNumSet: ERR. device number illigal %d\n", -+ devNum); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ localBus = mvPciLocalBusNumGet(pciIf); -+ localDev = mvPciLocalDevNumGet(pciIf); -+ -+ /* PCI interface mode */ -+ mvPciModeGet(pciIf, &pciMode); -+ -+ /* if PCI type is PCIX then it is not allowed to change the dev number */ -+ if (MV_PCIX == pciMode.pciType) -+ { -+ pciP2PConfig = mvPciConfigRead(pciIf, localBus, localDev, 0, PCIX_STATUS ); -+ -+ pciP2PConfig &= ~PXS_DN_MASK; -+ -+ pciP2PConfig |= (devNum << PXS_DN_OFFS) & PXS_DN_MASK; -+ -+ mvPciConfigWrite(pciIf,localBus, localDev, 0, PCIX_STATUS,pciP2PConfig ); -+ } -+ else -+ { -+ pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); -+ -+ pciP2PConfig &= ~PPCR_DEV_NUM_MASK; -+ -+ pciP2PConfig |= (devNum << PPCR_DEV_NUM_OFFS) & PPCR_DEV_NUM_MASK; -+ -+ MV_REG_WRITE(PCI_P2P_CONFIG_REG(pciIf), pciP2PConfig); -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvPciLocalDevNumGet - Get PCI interface local device number. -+* -+* DESCRIPTION: -+* This function gets the local device number of a given PCI interface. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Local device number. 0xffffffff on Error -+* -+*******************************************************************************/ -+MV_U32 mvPciLocalDevNumGet(MV_U32 pciIf) -+{ -+ MV_U32 pciP2PConfig; -+ -+ /* Parameter checking */ -+ -+ if (PCI_DEFAULT_IF != pciIf) -+ { -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciLocalDevNumGet: ERR. Invalid PCI interface %d\n", -+ pciIf); -+ return 0xFFFFFFFF; -+ } -+ } -+ -+ pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); -+ -+ pciP2PConfig &= PPCR_DEV_NUM_MASK; -+ -+ return (pciP2PConfig >> PPCR_DEV_NUM_OFFS); -+} -+ -+ -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,185 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCPCIH -+#define __INCPCIH -+ -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+#include "pci/mvPciRegs.h" -+ -+ -+/* NOTE not supported in this driver: -+ -+ Built In Self Test (BIST) -+ Vital Product Data (VPD) -+ Message Signaled Interrupt (MSI) -+ Power Management -+ Compact PCI Hot Swap -+ Header retarget -+ -+Registers not supported: -+1) PCI DLL Status and Control (PCI0 0x1D20, PCI1 0x1DA0) -+2) PCI/MPP Pads Calibration (CI0/MPP[31:16] 0x1D1C, PCI1/MPP[15:0] 0X1D9C) -+*/ -+ -+/* defines */ -+/* The number of supported PCI interfaces depend on Marvell controller */ -+/* device number. This device number ID is located on the PCI unit */ -+/* configuration header. This creates a loop where calling PCI */ -+/* configuration read/write routine results a call to get PCI configuration */ -+/* information etc. This macro defines a default PCI interface. This PCI */ -+/* interface is sure to exist. */ -+#define PCI_DEFAULT_IF 0 -+ -+ -+/* typedefs */ -+/* The Marvell controller supports both conventional PCI and PCI-X. */ -+/* This enumeration describes the PCI type. */ -+typedef enum _mvPciType -+{ -+ MV_PCI_CONV, /* Conventional PCI */ -+ MV_PCIX /* PCI-X */ -+}MV_PCI_TYPE; -+ -+typedef enum _mvPciMod -+{ -+ MV_PCI_MOD_HOST, -+ MV_PCI_MOD_DEVICE -+}MV_PCI_MOD; -+ -+ -+/* The Marvell controller supports both PCI width of 32 and 64 bit. */ -+/* This enumerator describes PCI width */ -+typedef enum _mvPciWidth -+{ -+ MV_PCI_32, /* PCI width 32bit */ -+ MV_PCI_64 /* PCI width 64bit */ -+}MV_PCI_WIDTH; -+ -+/* This structure describes the PCI unit configured type, speed and width. */ -+typedef struct _mvPciMode -+{ -+ MV_PCI_TYPE pciType; /* PCI type */ -+ MV_U32 pciSpeed; /* Assuming PCI base clock on board is 33MHz */ -+ MV_PCI_WIDTH pciWidth; /* PCI bus width */ -+}MV_PCI_MODE; -+ -+/* mvPciInit - Initialize PCI interfaces*/ -+MV_VOID mvPciHalInit(MV_U32 pciIf, MV_PCI_MOD pciIfmod); -+ -+/* mvPciCommandSet - Set PCI comman register value.*/ -+MV_STATUS mvPciCommandSet(MV_U32 pciIf, MV_U32 command); -+ -+/* mvPciModeGet - Get PCI interface mode.*/ -+MV_STATUS mvPciModeGet(MV_U32 pciIf, MV_PCI_MODE *pPciMode); -+ -+/* mvPciRetrySet - Set PCI retry counters*/ -+MV_STATUS mvPciRetrySet(MV_U32 pciIf, MV_U32 counter); -+ -+/* mvPciDiscardTimerSet - Set PCI discard timer*/ -+MV_STATUS mvPciDiscardTimerSet(MV_U32 pciIf, MV_U32 pClkCycles); -+ -+/* mvPciArbEnable - PCI arbiter enable/disable*/ -+MV_STATUS mvPciArbEnable(MV_U32 pciIf, MV_BOOL enable); -+ -+/* mvPciArbParkDis - Disable arbiter parking on agent */ -+MV_STATUS mvPciArbParkDis(MV_U32 pciIf, MV_U32 pciAgentMask); -+ -+/* mvPciArbBrokDetectSet - Set PCI arbiter broken detection */ -+MV_STATUS mvPciArbBrokDetectSet(MV_U32 pciIf, MV_U32 pClkCycles); -+ -+/* mvPciConfigRead - Read from configuration space */ -+MV_U32 mvPciConfigRead (MV_U32 pciIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func,MV_U32 regOff); -+ -+/* mvPciConfigWrite - Write to configuration space */ -+MV_STATUS mvPciConfigWrite(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data); -+ -+/* mvPciMasterEnable - Enable/disale PCI interface master transactions.*/ -+MV_STATUS mvPciMasterEnable(MV_U32 pciIf, MV_BOOL enable); -+ -+/* mvPciSlaveEnable - Enable/disale PCI interface slave transactions.*/ -+MV_STATUS mvPciSlaveEnable(MV_U32 pciIf, MV_U32 bus, MV_U32 dev,MV_BOOL enable); -+ -+/* mvPciLocalBusNumSet - Set PCI interface local bus number.*/ -+MV_STATUS mvPciLocalBusNumSet(MV_U32 pciIf, MV_U32 busNum); -+ -+/* mvPciLocalBusNumGet - Get PCI interface local bus number.*/ -+MV_U32 mvPciLocalBusNumGet(MV_U32 pciIf); -+ -+/* mvPciLocalDevNumSet - Set PCI interface local device number.*/ -+MV_STATUS mvPciLocalDevNumSet(MV_U32 pciIf, MV_U32 devNum); -+ -+/* mvPciLocalDevNumGet - Get PCI interface local device number.*/ -+MV_U32 mvPciLocalDevNumGet(MV_U32 pciIf); -+ -+ -+#endif /* #ifndef __INCPCIH */ -+ -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,411 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCPCIREGSH -+#define __INCPCIREGSH -+ -+ -+#include "pci-if/mvPciIfRegs.h" -+/* defines */ -+#define MAX_PCI_DEVICES 32 -+#define MAX_PCI_FUNCS 8 -+#define MAX_PCI_BUSSES 128 -+ -+/* enumerators */ -+ -+/* This enumerator described the possible PCI slave targets. */ -+/* PCI slave targets are designated memory/IO address spaces that the */ -+/* PCI slave targets can access. They are also refered as "targets" */ -+/* this enumeratoe order is determined by the content of : -+ PCI_BASE_ADDR_ENABLE_REG */ -+ -+ -+/* registers offsetes defines */ -+ -+ -+ -+/*************************/ -+/* PCI control registers */ -+/*************************/ -+/* maen : should add new registers */ -+#define PCI_CMD_REG(pciIf) (0x30c00 + ((pciIf) * 0x80)) -+#define PCI_MODE_REG(pciIf) (0x30d00 + ((pciIf) * 0x80)) -+#define PCI_RETRY_REG(pciIf) (0x30c04 + ((pciIf) * 0x80)) -+#define PCI_DISCARD_TIMER_REG(pciIf) (0x30d04 + ((pciIf) * 0x80)) -+#define PCI_ARBITER_CTRL_REG(pciIf) (0x31d00 + ((pciIf) * 0x80)) -+#define PCI_P2P_CONFIG_REG(pciIf) (0x31d14 + ((pciIf) * 0x80)) -+#define PCI_ACCESS_CTRL_BASEL_REG(pciIf, targetWin) \ -+ (0x31e00 + ((pciIf) * 0x80) + ((targetWin) * 0x10)) -+#define PCI_ACCESS_CTRL_BASEH_REG(pciIf, targetWin) \ -+ (0x31e04 + ((pciIf) * 0x80) + ((targetWin) * 0x10)) -+#define PCI_ACCESS_CTRL_SIZE_REG(pciIf, targetWin) \ -+ (0x31e08 + ((pciIf) * 0x80) + ((targetWin) * 0x10)) -+ -+#define PCI_DLL_CTRL_REG(pciIf) (0x31d20 + ((pciIf) * 0x80)) -+ -+/* PCI Dll Control (PDC)*/ -+#define PDC_DLL_EN BIT0 -+ -+ -+/* PCI Command Register (PCR) */ -+#define PCR_MASTER_BYTE_SWAP_EN BIT0 -+#define PCR_MASTER_WR_COMBINE_EN BIT4 -+#define PCR_MASTER_RD_COMBINE_EN BIT5 -+#define PCR_MASTER_WR_TRIG_WHOLE BIT6 -+#define PCR_MASTER_RD_TRIG_WHOLE BIT7 -+#define PCR_MASTER_MEM_RD_LINE_EN BIT8 -+#define PCR_MASTER_MEM_RD_MULT_EN BIT9 -+#define PCR_MASTER_WORD_SWAP_EN BIT10 -+#define PCR_SLAVE_WORD_SWAP_EN BIT11 -+#define PCR_NS_ACCORDING_RCV_TRANS BIT14 -+#define PCR_MASTER_PCIX_REQ64N_EN BIT15 -+#define PCR_SLAVE_BYTE_SWAP_EN BIT16 -+#define PCR_MASTER_DAC_EN BIT17 -+#define PCR_MASTER_M64_ALLIGN BIT18 -+#define PCR_ERRORS_PROPAGATION_EN BIT19 -+#define PCR_SLAVE_SWAP_ENABLE BIT20 -+#define PCR_MASTER_SWAP_ENABLE BIT21 -+#define PCR_MASTER_INT_SWAP_EN BIT22 -+#define PCR_LOOP_BACK_ENABLE BIT23 -+#define PCR_SLAVE_INTREG_SWAP_OFFS 24 -+#define PCR_SLAVE_INTREG_SWAP_MASK 0x3 -+#define PCR_SLAVE_INTREG_BYTE_SWAP \ -+ (MV_BYTE_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) -+#define PCR_SLAVE_INTREG_NO_SWAP \ -+ (MV_NO_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) -+#define PCR_SLAVE_INTREG_BYTE_WORD \ -+ (MV_BYTE_WORD_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) -+#define PCR_SLAVE_INTREG_WORD_SWAP \ -+ (MV_WORD_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) -+#define PCR_RESET_REASSERTION_EN BIT26 -+#define PCR_PCI_TO_CPU_REG_ORDER_EN BIT28 -+#define PCR_CPU_TO_PCI_ORDER_EN BIT29 -+#define PCR_PCI_TO_CPU_ORDER_EN BIT30 -+ -+/* PCI Mode Register (PMR) */ -+#define PMR_PCI_ID_OFFS 0 /* PCI Interface ID */ -+#define PMR_PCI_ID_MASK (0x1 << PMR_PCI_ID_OFFS) -+#define PMR_PCI_ID_PCI(pciNum) ((pciNum) << PCI_MODE_PCIID_OFFS) -+ -+#define PMR_PCI_64_OFFS 2 /* 64-bit PCI Interface */ -+#define PMR_PCI_64_MASK (0x1 << PMR_PCI_64_OFFS) -+#define PMR_PCI_64_64BIT (0x1 << PMR_PCI_64_OFFS) -+#define PMR_PCI_64_32BIT (0x0 << PMR_PCI_64_OFFS) -+ -+#define PMR_PCI_MODE_OFFS 4 /* PCI interface mode of operation */ -+#define PMR_PCI_MODE_MASK (0x3 << PMR_PCI_MODE_OFFS) -+#define PMR_PCI_MODE_CONV (0x0 << PMR_PCI_MODE_OFFS) -+#define PMR_PCI_MODE_PCIX_66MHZ (0x1 << PMR_PCI_MODE_OFFS) -+#define PMR_PCI_MODE_PCIX_100MHZ (0x2 << PMR_PCI_MODE_OFFS) -+#define PMR_PCI_MODE_PCIX_133MHZ (0x3 << PMR_PCI_MODE_OFFS) -+ -+#define PMR_EXP_ROM_SUPPORT BIT8 /* Expansion ROM Active */ -+ -+#define PMR_PCI_RESET_OFFS 31 /* PCI Interface Reset Indication */ -+#define PMR_PCI_RESET_MASK (0x1 << PMR_PCI_RESET_OFFS) -+#define PMR_PCI_RESET_PCIXRST (0x0 << PMR_PCI_RESET_OFFS) -+ -+ -+/* PCI Retry Register (PRR) */ -+#define PRR_RETRY_CNTR_OFFS 16 /* Retry Counter */ -+#define PRR_RETRY_CNTR_MAX 0xff -+#define PRR_RETRY_CNTR_MASK (PRR_RETRY_CNTR_MAX << PRR_RETRY_CNTR_OFFS) -+ -+ -+/* PCI Discard Timer Register (PDTR) */ -+#define PDTR_TIMER_OFFS 0 /* Timer */ -+#define PDTR_TIMER_MAX 0xffff -+#define PDTR_TIMER_MIN 0x7F -+#define PDTR_TIMER_MASK (PDTR_TIMER_MAX << PDTR_TIMER_OFFS) -+ -+ -+/* PCI Arbiter Control Register (PACR) */ -+#define PACR_BROKEN_DETECT_EN BIT1 /* Broken Detection Enable */ -+ -+#define PACR_BROKEN_VAL_OFFS 3 /* Broken Value */ -+#define PACR_BROKEN_VAL_MASK (0xf << PACR_BROKEN_VAL_OFFS) -+#define PACR_BROKEN_VAL_CONV_MIN 0x2 -+#define PACR_BROKEN_VAL_PCIX_MIN 0x6 -+ -+#define PACR_PARK_DIS_OFFS 14 /* Parking Disable */ -+#define PACR_PARK_DIS_MAX_AGENT 0x3f -+#define PACR_PARK_DIS_MASK (PACR_PARK_DIS_MAX_AGENT<= MV_PCI_START_IF)&&(pciIf < MV_PCI_MAX_IF + MV_PCI_START_IF)) -+ { -+ return PCI_IF_TYPE_CONVEN_PCIX; -+ } -+ else if ((pciIf >= MV_PEX_START_IF) && -+ (pciIf < MV_PEX_MAX_IF + MV_PEX_START_IF)) -+ { -+ return PCI_IF_TYPE_PEX; -+ -+ } -+ else -+ { -+ mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf); -+ } -+ -+ return 0xffffffff; -+ -+} -+ -+/******************************************************************************* -+* mvPciIfTypeGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+ -+MV_U32 mvPciRealIfNumGet(MV_U32 pciIf) -+{ -+ -+ PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf); -+ -+ if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType) -+ { -+ return (pciIf - MV_PCI_START_IF); -+ } -+ else if (PCI_IF_TYPE_PEX == pciIfType) -+ { -+ return (pciIf - MV_PEX_START_IF); -+ -+ } -+ else -+ { -+ mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf); -+ } -+ -+ return 0xffffffff; -+ -+} -+ -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,134 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCPCIIFH -+#define __INCPCIIFH -+ -+#include "mvSysHwConfig.h" -+#include "pci-if/mvPciIfRegs.h" -+#if defined(MV_INCLUDE_PEX) -+#include "pex/mvPex.h" -+#endif -+#if defined(MV_INCLUDE_PCI) -+#include "pci/mvPci.h" -+#endif -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+ -+typedef enum _mvPCIIfType -+{ -+ PCI_IF_TYPE_CONVEN_PCIX, -+ PCI_IF_TYPE_PEX -+ -+}PCI_IF_TYPE; -+ -+typedef enum _mvPCIIfMode -+{ -+ PCI_IF_MODE_HOST, -+ PCI_IF_MODE_DEVICE -+}PCI_IF_MODE; -+ -+ -+/* Global Functions prototypes */ -+ -+/* mvPciIfInit - Initialize PCI interfaces*/ -+MV_STATUS mvPciIfInit(MV_U32 pciIf, PCI_IF_MODE pciIfmode); -+ -+/* mvPciIfConfigRead - Read from configuration space */ -+MV_U32 mvPciIfConfigRead (MV_U32 pciIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func,MV_U32 regOff); -+ -+/* mvPciIfConfigWrite - Write to configuration space */ -+MV_STATUS mvPciIfConfigWrite(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data); -+ -+/* mvPciIfMasterEnable - Enable/disale PCI interface master transactions.*/ -+MV_STATUS mvPciIfMasterEnable(MV_U32 pciIf, MV_BOOL enable); -+ -+/* mvPciIfSlaveEnable - Enable/disale PCI interface slave transactions.*/ -+MV_STATUS mvPciIfSlaveEnable(MV_U32 pciIf,MV_U32 bus, MV_U32 dev, -+ MV_BOOL enable); -+ -+/* mvPciIfLocalBusNumSet - Set PCI interface local bus number.*/ -+MV_STATUS mvPciIfLocalBusNumSet(MV_U32 pciIf, MV_U32 busNum); -+ -+/* mvPciIfLocalBusNumGet - Get PCI interface local bus number.*/ -+MV_U32 mvPciIfLocalBusNumGet(MV_U32 pciIf); -+ -+/* mvPciIfLocalDevNumSet - Set PCI interface local device number.*/ -+MV_STATUS mvPciIfLocalDevNumSet(MV_U32 pciIf, MV_U32 devNum); -+ -+/* mvPciIfLocalDevNumGet - Get PCI interface local device number.*/ -+MV_U32 mvPciIfLocalDevNumGet(MV_U32 pciIf); -+ -+/* mvPciIfTypeGet - Get PCI If type*/ -+PCI_IF_TYPE mvPciIfTypeGet(MV_U32 pciIf); -+ -+MV_U32 mvPciRealIfNumGet(MV_U32 pciIf); -+ -+/* mvPciIfAddrDecShow - Display address decode windows attributes */ -+MV_VOID mvPciIfAddrDecShow(MV_VOID); -+ -+#endif /* #ifndef __INCPCIIFH */ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,245 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCPCIIFREGSH -+#define __INCPCIIFREGSH -+ -+ -+/* defines */ -+#define MAX_PCI_DEVICES 32 -+#define MAX_PCI_FUNCS 8 -+#define MAX_PCI_BUSSES 128 -+ -+/***************************************/ -+/* PCI Configuration registers */ -+/***************************************/ -+ -+/*********************************************/ -+/* PCI Configuration, Function 0, Registers */ -+/*********************************************/ -+ -+ -+/* Standard registers */ -+#define PCI_DEVICE_AND_VENDOR_ID 0x000 -+#define PCI_STATUS_AND_COMMAND 0x004 -+#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 -+#define PCI_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE 0x00C -+#define PCI_MEMORY_BAR_BASE_ADDR(barNum) (0x010 + ((barNum) << 2)) -+#define PCI_SUBSYS_ID_AND_SUBSYS_VENDOR_ID 0x02C -+#define PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030 -+#define PCI_CAPABILTY_LIST_POINTER 0x034 -+#define PCI_INTERRUPT_PIN_AND_LINE 0x03C -+ -+ -+/* PCI Device and Vendor ID Register (PDVIR) */ -+#define PDVIR_VEN_ID_OFFS 0 /* Vendor ID */ -+#define PDVIR_VEN_ID_MASK (0xffff << PDVIR_VEN_ID_OFFS) -+ -+#define PDVIR_DEV_ID_OFFS 16 /* Device ID */ -+#define PDVIR_DEV_ID_MASK (0xffff << PDVIR_DEV_ID_OFFS) -+ -+/* PCI Status and Command Register (PSCR) */ -+#define PSCR_IO_EN BIT0 /* IO Enable */ -+#define PSCR_MEM_EN BIT1 /* Memory Enable */ -+#define PSCR_MASTER_EN BIT2 /* Master Enable */ -+#define PSCR_SPECIAL_EN BIT3 /* Special Cycle Enable */ -+#define PSCR_MEM_WRI_INV BIT4 /* Memory Write and Invalidate Enable */ -+#define PSCR_VGA BIT5 /* VGA Palette Snoops */ -+#define PSCR_PERR_EN BIT6 /* Parity Errors Respond Enable */ -+#define PSCR_ADDR_STEP BIT7 /* Address Stepping Enable (Wait Cycle En)*/ -+#define PSCR_SERR_EN BIT8 /* Ability to assert SERR# line */ -+#define PSCR_FAST_BTB_EN BIT9 /* generate fast back-to-back transactions*/ -+#define PSCR_CAP_LIST BIT20 /* Capability List Support */ -+#define PSCR_66MHZ_EN BIT21 /* 66 MHz Capable */ -+#define PSCR_UDF_EN BIT22 /* User definable features */ -+#define PSCR_TAR_FAST_BB BIT23 /* fast back-to-back transactions capable */ -+#define PSCR_DATA_PERR BIT24 /* Data Parity reported */ -+ -+#define PSCR_DEVSEL_TIM_OFFS 25 /* DEVSEL timing */ -+#define PSCR_DEVSEL_TIM_MASK (0x3 << PSCR_DEVSEL_TIM_OFFS) -+#define PSCR_DEVSEL_TIM_FAST (0x0 << PSCR_DEVSEL_TIM_OFFS) -+#define PSCR_DEVSEL_TIM_MED (0x1 << PSCR_DEVSEL_TIM_OFFS) -+#define PSCR_DEVSEL_TIM_SLOW (0x2 << PSCR_DEVSEL_TIM_OFFS) -+ -+#define PSCR_SLAVE_TABORT BIT27 /* Signalled Target Abort */ -+#define PSCR_MASTER_TABORT BIT28 /* Recieved Target Abort */ -+#define PSCR_MABORT BIT29 /* Recieved Master Abort */ -+#define PSCR_SYSERR BIT30 /* Signalled system error */ -+#define PSCR_DET_PARERR BIT31 /* Detect Parity Error */ -+ -+/* PCI configuration register offset=0x08 fields -+ (PCI_CLASS_CODE_AND_REVISION_ID)(PCCRI) */ -+ -+#define PCCRIR_REVID_OFFS 0 /* Revision ID */ -+#define PCCRIR_REVID_MASK (0xff << PCCRIR_REVID_OFFS) -+ -+#define PCCRIR_FULL_CLASS_OFFS 8 /* Full Class Code */ -+#define PCCRIR_FULL_CLASS_MASK (0xffffff << PCCRIR_FULL_CLASS_OFFS) -+ -+#define PCCRIR_PROGIF_OFFS 8 /* Prog .I/F*/ -+#define PCCRIR_PROGIF_MASK (0xff << PCCRIR_PROGIF_OFFS) -+ -+#define PCCRIR_SUB_CLASS_OFFS 16 /* Sub Class*/ -+#define PCCRIR_SUB_CLASS_MASK (0xff << PCCRIR_SUB_CLASS_OFFS) -+ -+#define PCCRIR_BASE_CLASS_OFFS 24 /* Base Class*/ -+#define PCCRIR_BASE_CLASS_MASK (0xff << PCCRIR_BASE_CLASS_OFFS) -+ -+/* PCI configuration register offset=0x0C fields -+ (PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE)(PBHTLTCL) */ -+ -+#define PBHTLTCLR_CACHELINE_OFFS 0 /* Specifies the cache line size */ -+#define PBHTLTCLR_CACHELINE_MASK (0xff << PBHTLTCLR_CACHELINE_OFFS) -+ -+#define PBHTLTCLR_LATTIMER_OFFS 8 /* latency timer */ -+#define PBHTLTCLR_LATTIMER_MASK (0xff << PBHTLTCLR_LATTIMER_OFFS) -+ -+#define PBHTLTCLR_HEADTYPE_FULL_OFFS 16 /* Full Header Type */ -+#define PBHTLTCLR_HEADTYPE_FULL_MASK (0xff << PBHTLTCLR_HEADTYPE_FULL_OFFS) -+ -+#define PBHTLTCLR_MULTI_FUNC BIT23 /* Multi/Single function */ -+ -+#define PBHTLTCLR_HEADER_OFFS 16 /* Header type */ -+#define PBHTLTCLR_HEADER_MASK (0x7f << PBHTLTCLR_HEADER_OFFS) -+#define PBHTLTCLR_HEADER_STANDARD (0x0 << PBHTLTCLR_HEADER_OFFS) -+#define PBHTLTCLR_HEADER_PCI2PCI_BRIDGE (0x1 << PBHTLTCLR_HEADER_OFFS) -+ -+ -+#define PBHTLTCLR_BISTCOMP_OFFS 24 /* BIST Completion Code */ -+#define PBHTLTCLR_BISTCOMP_MASK (0xf << PBHTLTCLR_BISTCOMP_OFFS) -+ -+#define PBHTLTCLR_BISTACT BIT30 /* BIST Activate bit */ -+#define PBHTLTCLR_BISTCAP BIT31 /* BIST Capable Bit */ -+ -+ -+/* PCI Bar Base Low Register (PBBLR) */ -+#define PBBLR_IOSPACE BIT0 /* Memory Space Indicator */ -+ -+#define PBBLR_TYPE_OFFS 1 /* BAR Type/Init Val. */ -+#define PBBLR_TYPE_MASK (0x3 << PBBLR_TYPE_OFFS) -+#define PBBLR_TYPE_32BIT_ADDR (0x0 << PBBLR_TYPE_OFFS) -+#define PBBLR_TYPE_64BIT_ADDR (0x2 << PBBLR_TYPE_OFFS) -+ -+#define PBBLR_PREFETCH_EN BIT3 /* Prefetch Enable */ -+ -+ -+#define PBBLR_MEM_BASE_OFFS 4 /* Memory Bar Base address. Corresponds to -+ address bits [31:4] */ -+#define PBBLR_MEM_BASE_MASK (0xfffffff << PBBLR_MEM_BASE_OFFS) -+ -+#define PBBLR_IO_BASE_OFFS 2 /* IO Bar Base address. Corresponds to -+ address bits [31:2] */ -+#define PBBLR_IO_BASE_MASK (0x3fffffff << PBBLR_IO_BASE_OFFS) -+ -+ -+#define PBBLR_BASE_OFFS 12 /* Base address. Address bits [31:12] */ -+#define PBBLR_BASE_MASK (0xfffff << PBBLR_BASE_OFFS) -+#define PBBLR_BASE_ALIGNMET (1 << PBBLR_BASE_OFFS) -+ -+ -+/* PCI Bar Base High Fegister (PBBHR) */ -+#define PBBHR_BASE_OFFS 0 /* Base address. Address bits [31:12] */ -+#define PBBHR_BASE_MASK (0xffffffff << PBBHR_BASE_OFFS) -+ -+ -+/* PCI configuration register offset=0x2C fields -+ (PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID)(PSISVI) */ -+ -+#define PSISVIR_VENID_OFFS 0 /* Subsystem Manufacturer Vendor ID Number */ -+#define PSISVIR_VENID_MASK (0xffff << PSISVIR_VENID_OFFS) -+ -+#define PSISVIR_DEVID_OFFS 16 /* Subsystem Device ID Number */ -+#define PSISVIR_DEVID_MASK (0xffff << PSISVIR_DEVID_OFFS) -+ -+/* PCI configuration register offset=0x30 fields -+ (PCI_EXPANSION_ROM_BASE_ADDR_REG)(PERBA) */ -+ -+#define PERBAR_EXPROMEN BIT0 /* Expansion ROM Enable */ -+ -+#define PERBAR_BASE_OFFS 12 /* Expansion ROM Base Address */ -+#define PERBAR_BASE_MASK (0xfffff << PERBAR_BASE_OFFS) -+ -+/* PCI configuration register offset=0x34 fields -+ (PCI_CAPABILTY_LIST_POINTER)(PCLP) */ -+ -+#define PCLPR_CAPPTR_OFFS 0 /* Capability List Pointer */ -+#define PCLPR_CAPPTR_MASK (0xff << PCLPR_CAPPTR_OFFS) -+ -+/* PCI configuration register offset=0x3C fields -+ (PCI_INTERRUPT_PIN_AND_LINE)(PIPL) */ -+ -+#define PIPLR_INTLINE_OFFS 0 /* Interrupt line (IRQ) */ -+#define PIPLR_INTLINE_MASK (0xff << PIPLR_INTLINE_OFFS) -+ -+#define PIPLR_INTPIN_OFFS 8 /* interrupt pin (A,B,C,D) */ -+#define PIPLR_INTPIN_MASK (0xff << PIPLR_INTPIN_OFFS) -+ -+#define PIPLR_MINGRANT_OFFS 16 /* Minimum Grant on 250 nano seconds units */ -+#define PIPLR_MINGRANT_MASK (0xff << PIPLR_MINGRANT_OFFS) -+ -+#define PIPLR_MAXLATEN_OFFS 24 /* Maximum latency on 250 nano seconds units */ -+#define PIPLR_MAXLATEN_MASK (0xff << PIPLR_MAXLATEN_OFFS) -+ -+#endif /* #ifndef __INCPCIIFREGSH */ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,1006 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+/* includes */ -+#include "mvPciUtils.h" -+ -+#include "ctrlEnv/mvCtrlEnvLib.h" -+ -+/* #define MV_DEBUG */ -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+ #define mvOsPrintf printf -+#else -+ #define DB(x) -+#endif -+ -+/* -+This module only support scanning of Header type 00h of pci devices -+There is no suppotr for Header type 01h of pci devices ( PCI bridges ) -+*/ -+ -+ -+static MV_STATUS pciDetectDevice(MV_U32 pciIf, -+ MV_U32 bus, -+ MV_U32 dev, -+ MV_U32 func, -+ MV_PCI_DEVICE *pPciAgent); -+ -+static MV_U32 pciDetectDeviceBars(MV_U32 pciIf, -+ MV_U32 bus, -+ MV_U32 dev, -+ MV_U32 func, -+ MV_PCI_DEVICE *pPciAgent); -+ -+ -+ -+ -+ -+ -+/******************************************************************************* -+* mvPciScan - Scan a PCI interface bus -+* -+* DESCRIPTION: -+* Performs a full scan on a PCI interface and returns all possible details -+* on the agents found on the bus. -+* -+* INPUT: -+* pciIf - PCI Interface -+* pPciAgents - Pointer to an Array of the pci agents to be detected -+* pPciAgentsNum - pPciAgents array maximum number of elements -+* -+* OUTPUT: -+* pPciAgents - Array of the pci agents detected on the bus -+* pPciAgentsNum - Number of pci agents detected on the bus -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+ -+MV_STATUS mvPciScan(MV_U32 pciIf, -+ MV_PCI_DEVICE *pPciAgents, -+ MV_U32 *pPciAgentsNum) -+{ -+ -+ MV_U32 devIndex,funcIndex=0,busIndex=0,detectedDevNum=0; -+ MV_U32 localBus=mvPciIfLocalBusNumGet(pciIf); -+ MV_PCI_DEVICE *pPciDevice; -+ MV_PCI_DEVICE *pMainDevice; -+ -+ DB(mvOsPrintf("mvPciScan: PCI interface num %d\n", pciIf)); -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPexMaxIfGet()) -+ { -+ DB(mvOsPrintf("mvPciScan: ERR. Invalid PCI interface num %d\n", pciIf)); -+ return MV_BAD_PARAM; -+ } -+ if (NULL == pPciAgents) -+ { -+ DB(mvOsPrintf("mvPciScan: ERR. pPciAgents=NULL \n")); -+ return MV_BAD_PARAM; -+ } -+ if (NULL == pPciAgentsNum) -+ { -+ DB(mvOsPrintf("mvPciScan: ERR. pPciAgentsNum=NULL \n")); -+ return MV_BAD_PARAM; -+ } -+ -+ -+ DB(mvOsPrintf("mvPciScan: PCI interface num %d mvPciMasterEnable\n", pciIf)); -+ /* Master enable the MV PCI master */ -+ if (MV_OK != mvPciIfMasterEnable(pciIf,MV_TRUE)) -+ { -+ DB(mvOsPrintf("mvPciScan: ERR. mvPciMasterEnable failed \n")); -+ return MV_ERROR; -+ -+ } -+ -+ DB(mvOsPrintf("mvPciScan: PCI interface num scan%d\n", pciIf)); -+ -+ /* go through all busses */ -+ for (busIndex=localBus ; busIndex < MAX_PCI_BUSSES ; busIndex++) -+ { -+ /* go through all possible devices on the local bus */ -+ for (devIndex=0 ; devIndex < MAX_PCI_DEVICES ; devIndex++) -+ { -+ /* always start with function equal to zero */ -+ funcIndex=0; -+ -+ pPciDevice=&pPciAgents[detectedDevNum]; -+ DB(mvOsPrintf("mvPciScan: PCI interface num scan%d:%d\n", busIndex, devIndex)); -+ -+ if (MV_ERROR == pciDetectDevice(pciIf, -+ busIndex, -+ devIndex, -+ funcIndex, -+ pPciDevice)) -+ { -+ /* no device detected , try the next address */ -+ continue; -+ } -+ -+ /* We are here ! means we have detected a device*/ -+ /* always we start with only one function per device */ -+ pMainDevice = pPciDevice; -+ pPciDevice->funtionsNum = 1; -+ -+ -+ /* move on */ -+ detectedDevNum++; -+ -+ -+ /* check if we have no more room for a new device */ -+ if (detectedDevNum == *pPciAgentsNum) -+ { -+ DB(mvOsPrintf("mvPciScan: ERR. array passed too small \n")); -+ return MV_ERROR; -+ } -+ -+ /* check the detected device if it is a multi functional device then -+ scan all device functions*/ -+ if (pPciDevice->isMultiFunction == MV_TRUE) -+ { -+ /* start with function number 1 because we have already detected -+ function 0 */ -+ for (funcIndex=1; funcIndexfuntionsNum++; -+ detectedDevNum++; -+ -+ /* check if we have no more room for a new device */ -+ if (detectedDevNum == *pPciAgentsNum) -+ { -+ DB(mvOsPrintf("mvPciScan: ERR. Array too small\n")); -+ return MV_ERROR; -+ } -+ -+ -+ } -+ } -+ -+ } -+ -+ } -+ -+ /* return the number of devices actually detected on the bus ! */ -+ *pPciAgentsNum = detectedDevNum; -+ -+ return MV_OK; -+ -+} -+ -+ -+/******************************************************************************* -+* pciDetectDevice - Detect a pci device parameters -+* -+* DESCRIPTION: -+* This function detect if a pci agent exist on certain address ! -+* and if exists then it fills all possible information on the -+* agent -+* -+* INPUT: -+* pciIf - PCI Interface -+* bus - Bus number -+* dev - Device number -+* func - Function number -+* -+* -+* -+* OUTPUT: -+* pPciAgent - pointer to the pci agent filled with its information -+* -+* RETURN: -+* MV_ERROR if no device , MV_OK otherwise -+* -+*******************************************************************************/ -+ -+static MV_STATUS pciDetectDevice(MV_U32 pciIf, -+ MV_U32 bus, -+ MV_U32 dev, -+ MV_U32 func, -+ MV_PCI_DEVICE *pPciAgent) -+{ -+ MV_U32 pciData; -+ -+ /* no Parameters checking ! because it is static function and it is assumed -+ that all parameters were checked in the calling function */ -+ -+ -+ /* Try read the PCI Vendor ID and Device ID */ -+ -+ /* We will scan only ourselves and the PCI slots that exist on the -+ board, because we may have a case that we have one slot that has -+ a Cardbus connector, and because CardBus answers all IDsels we want -+ to scan only this slot and ourseleves. -+ -+ */ -+ #if defined(MV_INCLUDE_PCI) -+ if ((PCI_IF_TYPE_CONVEN_PCIX == mvPciIfTypeGet(pciIf)) && -+ (DB_88F5181_DDR1_PRPMC != mvBoardIdGet()) && -+ (DB_88F5181_DDR1_PEXPCI != mvBoardIdGet()) && -+ (DB_88F5181_DDR1_MNG != mvBoardIdGet())) -+ { -+ -+ if (mvBoardIsOurPciSlot(bus, dev) == MV_FALSE) -+ { -+ return MV_ERROR; -+ } -+ } -+ #endif /* defined(MV_INCLUDE_PCI) */ -+ -+ pciData = mvPciIfConfigRead(pciIf, bus,dev,func, PCI_DEVICE_AND_VENDOR_ID); -+ -+ if (PCI_ERROR_CODE == pciData) -+ { -+ /* no device exist */ -+ return MV_ERROR; -+ } -+ -+ /* we are here ! means a device is detected */ -+ -+ /* fill basic information */ -+ pPciAgent->busNumber=bus; -+ pPciAgent->deviceNum=dev; -+ pPciAgent->function=func; -+ -+ /* Fill the PCI Vendor ID and Device ID */ -+ -+ pPciAgent->venID = (pciData & PDVIR_VEN_ID_MASK) >> PDVIR_VEN_ID_OFFS; -+ pPciAgent->deviceID = (pciData & PDVIR_DEV_ID_MASK) >> PDVIR_DEV_ID_OFFS; -+ -+ /* Read Status and command */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_STATUS_AND_COMMAND); -+ -+ -+ /* Fill related Status and Command information*/ -+ -+ if (pciData & PSCR_TAR_FAST_BB) -+ { -+ pPciAgent->isFastB2BCapable = MV_TRUE; -+ } -+ else -+ { -+ pPciAgent->isFastB2BCapable = MV_FALSE; -+ } -+ -+ if (pciData & PSCR_CAP_LIST) -+ { -+ pPciAgent->isCapListSupport=MV_TRUE; -+ } -+ else -+ { -+ pPciAgent->isCapListSupport=MV_FALSE; -+ } -+ -+ if (pciData & PSCR_66MHZ_EN) -+ { -+ pPciAgent->is66MHZCapable=MV_TRUE; -+ } -+ else -+ { -+ pPciAgent->is66MHZCapable=MV_FALSE; -+ } -+ -+ /* Read Class Code and Revision */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_CLASS_CODE_AND_REVISION_ID); -+ -+ -+ pPciAgent->baseClassCode = -+ (pciData & PCCRIR_BASE_CLASS_MASK) >> PCCRIR_BASE_CLASS_OFFS; -+ -+ pPciAgent->subClassCode = -+ (pciData & PCCRIR_SUB_CLASS_MASK) >> PCCRIR_SUB_CLASS_OFFS; -+ -+ pPciAgent->progIf = -+ (pciData & PCCRIR_PROGIF_MASK) >> PCCRIR_PROGIF_OFFS; -+ -+ pPciAgent->revisionID = -+ (pciData & PCCRIR_REVID_MASK) >> PCCRIR_REVID_OFFS; -+ -+ /* Read PCI_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE); -+ -+ -+ -+ pPciAgent->pciCacheLine= -+ (pciData & PBHTLTCLR_CACHELINE_MASK ) >> PBHTLTCLR_CACHELINE_OFFS; -+ pPciAgent->pciLatencyTimer= -+ (pciData & PBHTLTCLR_LATTIMER_MASK) >> PBHTLTCLR_LATTIMER_OFFS; -+ -+ switch (pciData & PBHTLTCLR_HEADER_MASK) -+ { -+ case PBHTLTCLR_HEADER_STANDARD: -+ -+ pPciAgent->pciHeader=MV_PCI_STANDARD; -+ break; -+ case PBHTLTCLR_HEADER_PCI2PCI_BRIDGE: -+ -+ pPciAgent->pciHeader=MV_PCI_PCI2PCI_BRIDGE; -+ break; -+ -+ } -+ -+ if (pciData & PBHTLTCLR_MULTI_FUNC) -+ { -+ pPciAgent->isMultiFunction=MV_TRUE; -+ } -+ else -+ { -+ pPciAgent->isMultiFunction=MV_FALSE; -+ } -+ -+ if (pciData & PBHTLTCLR_BISTCAP) -+ { -+ pPciAgent->isBISTCapable=MV_TRUE; -+ } -+ else -+ { -+ pPciAgent->isBISTCapable=MV_FALSE; -+ } -+ -+ -+ /* read this device pci bars */ -+ -+ pciDetectDeviceBars(pciIf, -+ bus,dev,func, -+ pPciAgent); -+ -+ -+ /* check if we are bridge*/ -+ if ((pPciAgent->baseClassCode == PCI_BRIDGE_CLASS)&& -+ (pPciAgent->subClassCode == P2P_BRIDGE_SUB_CLASS_CODE)) -+ { -+ -+ /* Read P2P_BUSSES_NUM */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ P2P_BUSSES_NUM); -+ -+ pPciAgent->p2pPrimBusNum = -+ (pciData & PBM_PRIME_BUS_NUM_MASK) >> PBM_PRIME_BUS_NUM_OFFS; -+ -+ pPciAgent->p2pSecBusNum = -+ (pciData & PBM_SEC_BUS_NUM_MASK) >> PBM_SEC_BUS_NUM_OFFS; -+ -+ pPciAgent->p2pSubBusNum = -+ (pciData & PBM_SUB_BUS_NUM_MASK) >> PBM_SUB_BUS_NUM_OFFS; -+ -+ pPciAgent->p2pSecLatencyTimer = -+ (pciData & PBM_SEC_LAT_TMR_MASK) >> PBM_SEC_LAT_TMR_OFFS; -+ -+ /* Read P2P_IO_BASE_LIMIT_SEC_STATUS */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ P2P_IO_BASE_LIMIT_SEC_STATUS); -+ -+ pPciAgent->p2pSecStatus = -+ (pciData & PIBLSS_SEC_STATUS_MASK) >> PIBLSS_SEC_STATUS_OFFS; -+ -+ -+ pPciAgent->p2pIObase = -+ (pciData & PIBLSS_IO_BASE_MASK) << PIBLSS_IO_LIMIT_OFFS; -+ -+ /* clear low address (should be zero)*/ -+ pPciAgent->p2pIObase &= PIBLSS_HIGH_ADDR_MASK; -+ -+ pPciAgent->p2pIOLimit = -+ (pciData & PIBLSS_IO_LIMIT_MASK); -+ -+ /* fill low address with 0xfff */ -+ pPciAgent->p2pIOLimit |= PIBLSS_LOW_ADDR_MASK; -+ -+ -+ switch ((pciData & PIBLSS_ADD_CAP_MASK) >> PIBLSS_ADD_CAP_OFFS) -+ { -+ case PIBLSS_ADD_CAP_16BIT: -+ -+ pPciAgent->bIO32 = MV_FALSE; -+ -+ break; -+ case PIBLSS_ADD_CAP_32BIT: -+ -+ pPciAgent->bIO32 = MV_TRUE; -+ -+ /* Read P2P_IO_BASE_LIMIT_UPPER_16 */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ P2P_IO_BASE_LIMIT_UPPER_16); -+ -+ pPciAgent->p2pIObase |= -+ (pciData & PRBU_IO_UPP_BASE_MASK) << PRBU_IO_UPP_LIMIT_OFFS; -+ -+ -+ pPciAgent->p2pIOLimit |= -+ (pciData & PRBU_IO_UPP_LIMIT_MASK); -+ -+ break; -+ -+ } -+ -+ -+ /* Read P2P_MEM_BASE_LIMIT */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ P2P_MEM_BASE_LIMIT); -+ -+ pPciAgent->p2pMemBase = -+ (pciData & PMBL_MEM_BASE_MASK) << PMBL_MEM_LIMIT_OFFS; -+ -+ /* clear low address */ -+ pPciAgent->p2pMemBase &= PMBL_HIGH_ADDR_MASK; -+ -+ pPciAgent->p2pMemLimit = -+ (pciData & PMBL_MEM_LIMIT_MASK); -+ -+ /* add 0xfffff */ -+ pPciAgent->p2pMemLimit |= PMBL_LOW_ADDR_MASK; -+ -+ -+ /* Read P2P_PREF_MEM_BASE_LIMIT */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ P2P_PREF_MEM_BASE_LIMIT); -+ -+ -+ pPciAgent->p2pPrefMemBase = -+ (pciData & PRMBL_PREF_MEM_BASE_MASK) << PRMBL_PREF_MEM_LIMIT_OFFS; -+ -+ /* get high address only */ -+ pPciAgent->p2pPrefMemBase &= PRMBL_HIGH_ADDR_MASK; -+ -+ -+ -+ pPciAgent->p2pPrefMemLimit = -+ (pciData & PRMBL_PREF_MEM_LIMIT_MASK); -+ -+ /* add 0xfffff */ -+ pPciAgent->p2pPrefMemLimit |= PRMBL_LOW_ADDR_MASK; -+ -+ switch (pciData & PRMBL_ADD_CAP_MASK) -+ { -+ case PRMBL_ADD_CAP_32BIT: -+ -+ pPciAgent->bPrefMem64 = MV_FALSE; -+ -+ /* Read P2P_PREF_BASE_UPPER_32 */ -+ pPciAgent->p2pPrefBaseUpper32Bits = 0; -+ -+ /* Read P2P_PREF_LIMIT_UPPER_32 */ -+ pPciAgent->p2pPrefLimitUpper32Bits = 0; -+ -+ break; -+ case PRMBL_ADD_CAP_64BIT: -+ -+ pPciAgent->bPrefMem64 = MV_TRUE; -+ -+ /* Read P2P_PREF_BASE_UPPER_32 */ -+ pPciAgent->p2pPrefBaseUpper32Bits = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ P2P_PREF_BASE_UPPER_32); -+ -+ /* Read P2P_PREF_LIMIT_UPPER_32 */ -+ pPciAgent->p2pPrefLimitUpper32Bits = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ P2P_PREF_LIMIT_UPPER_32); -+ -+ break; -+ -+ } -+ -+ } -+ else /* no bridge */ -+ { -+ /* Read PCI_SUBSYS_ID_AND_SUBSYS_VENDOR_ID */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_SUBSYS_ID_AND_SUBSYS_VENDOR_ID); -+ -+ -+ pPciAgent->subSysVenID = -+ (pciData & PSISVIR_VENID_MASK) >> PSISVIR_VENID_OFFS; -+ pPciAgent->subSysID = -+ (pciData & PSISVIR_DEVID_MASK) >> PSISVIR_DEVID_OFFS; -+ -+ -+ /* Read PCI_EXPANSION_ROM_BASE_ADDR_REG */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_EXPANSION_ROM_BASE_ADDR_REG); -+ -+ -+ if (pciData & PERBAR_EXPROMEN) -+ { -+ pPciAgent->isExpRom = MV_TRUE; -+ } -+ else -+ { -+ pPciAgent->isExpRom = MV_FALSE; -+ } -+ -+ pPciAgent->expRomAddr = -+ (pciData & PERBAR_BASE_MASK) >> PERBAR_BASE_OFFS; -+ -+ } -+ -+ -+ if (MV_TRUE == pPciAgent->isCapListSupport) -+ { -+ /* Read PCI_CAPABILTY_LIST_POINTER */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_CAPABILTY_LIST_POINTER); -+ -+ pPciAgent->capListPointer = -+ (pciData & PCLPR_CAPPTR_MASK) >> PCLPR_CAPPTR_OFFS; -+ -+ } -+ -+ /* Read PCI_INTERRUPT_PIN_AND_LINE */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_INTERRUPT_PIN_AND_LINE); -+ -+ -+ pPciAgent->irqLine= -+ (pciData & PIPLR_INTLINE_MASK) >> PIPLR_INTLINE_OFFS; -+ -+ pPciAgent->intPin= -+ (MV_PCI_INT_PIN)(pciData & PIPLR_INTPIN_MASK) >> PIPLR_INTPIN_OFFS; -+ -+ pPciAgent->minGrant= -+ (pciData & PIPLR_MINGRANT_MASK) >> PIPLR_MINGRANT_OFFS; -+ pPciAgent->maxLatency= -+ (pciData & PIPLR_MAXLATEN_MASK) >> PIPLR_MAXLATEN_OFFS; -+ -+ mvPciClassNameGet(pPciAgent->baseClassCode, -+ (MV_8 *)pPciAgent->type); -+ -+ return MV_OK; -+ -+ -+} -+ -+/******************************************************************************* -+* pciDetectDeviceBars - Detect a pci device bars -+* -+* DESCRIPTION: -+* This function detects all pci agent bars -+* -+* INPUT: -+* pciIf - PCI Interface -+* bus - Bus number -+* dev - Device number -+* func - Function number -+* -+* -+* -+* OUTPUT: -+* pPciAgent - pointer to the pci agent filled with its information -+* -+* RETURN: -+* detected bars number -+* -+*******************************************************************************/ -+static MV_U32 pciDetectDeviceBars(MV_U32 pciIf, -+ MV_U32 bus, -+ MV_U32 dev, -+ MV_U32 func, -+ MV_PCI_DEVICE *pPciAgent) -+{ -+ MV_U32 pciData,barIndex,detectedBar=0; -+ MV_U32 tmpBaseHigh=0,tmpBaseLow=0; -+ MV_U32 pciMaxBars=0; -+ -+ pPciAgent->barsNum=0; -+ -+ /* check if we are bridge*/ -+ if ((pPciAgent->baseClassCode == PCI_BRIDGE_CLASS)&& -+ (pPciAgent->subClassCode == P2P_BRIDGE_SUB_CLASS_CODE)) -+ { -+ pciMaxBars = 2; -+ } -+ else /* no bridge */ -+ { -+ pciMaxBars = 6; -+ } -+ -+ /* read this device pci bars */ -+ for (barIndex = 0 ; barIndex < pciMaxBars ; barIndex++ ) -+ { -+ /* Read PCI_MEMORY_BAR_BASE_ADDR */ -+ tmpBaseLow = pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex)); -+ -+ pPciAgent->pciBar[detectedBar].barOffset = -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex); -+ -+ /* check if the bar is 32bit or 64bit bar */ -+ switch (pciData & PBBLR_TYPE_MASK) -+ { -+ case PBBLR_TYPE_32BIT_ADDR: -+ pPciAgent->pciBar[detectedBar].barType = PCI_32BIT_BAR; -+ break; -+ case PBBLR_TYPE_64BIT_ADDR: -+ pPciAgent->pciBar[detectedBar].barType = PCI_64BIT_BAR; -+ break; -+ -+ } -+ -+ /* check if it is memory or IO bar */ -+ if (pciData & PBBLR_IOSPACE) -+ { -+ pPciAgent->pciBar[detectedBar].barMapping=PCI_IO_BAR; -+ } -+ else -+ { -+ pPciAgent->pciBar[detectedBar].barMapping=PCI_MEMORY_BAR; -+ } -+ -+ /* if it is memory bar then check if it is prefetchable */ -+ if (PCI_MEMORY_BAR == pPciAgent->pciBar[detectedBar].barMapping) -+ { -+ if (pciData & PBBLR_PREFETCH_EN) -+ { -+ pPciAgent->pciBar[detectedBar].isPrefetchable = MV_TRUE; -+ } -+ else -+ { -+ pPciAgent->pciBar[detectedBar].isPrefetchable = MV_FALSE; -+ } -+ -+ pPciAgent->pciBar[detectedBar].barBaseLow = -+ pciData & PBBLR_MEM_BASE_MASK; -+ -+ -+ } -+ else /* IO Bar */ -+ { -+ pPciAgent->pciBar[detectedBar].barBaseLow = -+ pciData & PBBLR_IO_BASE_MASK; -+ -+ } -+ -+ pPciAgent->pciBar[detectedBar].barBaseHigh=0; -+ -+ if (PCI_64BIT_BAR == pPciAgent->pciBar[detectedBar].barType) -+ { -+ barIndex++; -+ -+ tmpBaseHigh = pPciAgent->pciBar[detectedBar].barBaseHigh = -+ mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex)); -+ -+ -+ } -+ -+ /* calculating full base address (64bit) */ -+ pPciAgent->pciBar[detectedBar].barBaseAddr = -+ (MV_U64)pPciAgent->pciBar[detectedBar].barBaseHigh; -+ -+ pPciAgent->pciBar[detectedBar].barBaseAddr <<= 32; -+ -+ pPciAgent->pciBar[detectedBar].barBaseAddr |= -+ (MV_U64)pPciAgent->pciBar[detectedBar].barBaseLow; -+ -+ -+ -+ /* get the sizes of the the bar */ -+ -+ pPciAgent->pciBar[detectedBar].barSizeHigh=0; -+ -+ if ((PCI_64BIT_BAR == pPciAgent->pciBar[detectedBar].barType) && -+ (PCI_MEMORY_BAR == pPciAgent->pciBar[detectedBar].barMapping)) -+ -+ { -+ /* write oxffffffff to the bar to get the size */ -+ /* start with sizelow ( original value was saved in tmpBaseLow ) */ -+ mvPciIfConfigWrite(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex-1), -+ 0xffffffff); -+ -+ /* read size */ -+ pPciAgent->pciBar[detectedBar].barSizeLow = -+ mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex-1)); -+ -+ -+ -+ /* restore original value */ -+ mvPciIfConfigWrite(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex-1), -+ tmpBaseLow); -+ -+ -+ /* now do the same for BaseHigh */ -+ -+ /* write oxffffffff to the bar to get the size */ -+ mvPciIfConfigWrite(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex), -+ 0xffffffff); -+ -+ /* read size */ -+ pPciAgent->pciBar[detectedBar].barSizeHigh = -+ mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex)); -+ -+ /* restore original value */ -+ mvPciIfConfigWrite(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex), -+ tmpBaseHigh); -+ -+ if ((0 == pPciAgent->pciBar[detectedBar].barSizeLow)&& -+ (0 == pPciAgent->pciBar[detectedBar].barSizeHigh)) -+ { -+ /* this bar is not applicable for this device, -+ ignore all previous settings and check the next bar*/ -+ -+ /* we though this was a 64bit bar , and it seems this -+ was wrong ! so decrement barIndex */ -+ barIndex--; -+ continue; -+ } -+ -+ /* calculate the full 64 bit size */ -+ -+ if (0 != pPciAgent->pciBar[detectedBar].barSizeHigh) -+ { -+ pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_MEM_BASE_MASK; -+ -+ pPciAgent->pciBar[detectedBar].barSizeLow = -+ ~pPciAgent->pciBar[detectedBar].barSizeLow + 1; -+ -+ pPciAgent->pciBar[detectedBar].barSizeHigh = 0; -+ -+ } -+ else -+ { -+ -+ pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_MEM_BASE_MASK; -+ -+ pPciAgent->pciBar[detectedBar].barSizeLow = -+ ~pPciAgent->pciBar[detectedBar].barSizeLow + 1; -+ -+ pPciAgent->pciBar[detectedBar].barSizeHigh = 0; -+ -+ } -+ -+ -+ -+ } -+ else /* 32bit bar */ -+ { -+ /* write oxffffffff to the bar to get the size */ -+ mvPciIfConfigWrite(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex), -+ 0xffffffff); -+ -+ /* read size */ -+ pPciAgent->pciBar[detectedBar].barSizeLow = -+ mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex)); -+ -+ if (0 == pPciAgent->pciBar[detectedBar].barSizeLow) -+ { -+ /* this bar is not applicable for this device, -+ ignore all previous settings and check the next bar*/ -+ continue; -+ } -+ -+ -+ /* restore original value */ -+ mvPciIfConfigWrite(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex), -+ tmpBaseLow); -+ -+ /* calculate size low */ -+ -+ if (PCI_MEMORY_BAR == pPciAgent->pciBar[detectedBar].barMapping) -+ { -+ pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_MEM_BASE_MASK; -+ } -+ else -+ { -+ pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_IO_BASE_MASK; -+ } -+ -+ pPciAgent->pciBar[detectedBar].barSizeLow = -+ ~pPciAgent->pciBar[detectedBar].barSizeLow + 1; -+ -+ pPciAgent->pciBar[detectedBar].barSizeHigh = 0; -+ pPciAgent->pciBar[detectedBar].barSize = -+ (MV_U64)pPciAgent->pciBar[detectedBar].barSizeLow; -+ -+ -+ } -+ -+ /* we are here ! this means we have already detected a bar for -+ this device , now move on */ -+ -+ detectedBar++; -+ pPciAgent->barsNum++; -+ } -+ -+ return detectedBar; -+} -+ -+ -+/******************************************************************************* -+* mvPciClassNameGet - get PCI class name -+* -+* DESCRIPTION: -+* This function returns the PCI class name -+* -+* INPUT: -+* baseClassCode - Base Class Code. -+* -+* OUTPUT: -+* pType - the class name -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciClassNameGet(MV_U32 baseClassCode, MV_8 *pType) -+{ -+ -+ switch(baseClassCode) -+ { -+ case 0x0: -+ strcpy(pType,"Old generation device"); -+ break; -+ case 0x1: -+ strcpy(pType,"Mass storage controller"); -+ break; -+ case 0x2: -+ strcpy(pType,"Network controller"); -+ break; -+ case 0x3: -+ strcpy(pType,"Display controller"); -+ break; -+ case 0x4: -+ strcpy(pType,"Multimedia device"); -+ break; -+ case 0x5: -+ strcpy(pType,"Memory controller"); -+ break; -+ case 0x6: -+ strcpy(pType,"Bridge Device"); -+ break; -+ case 0x7: -+ strcpy(pType,"Simple Communication controllers"); -+ break; -+ case 0x8: -+ strcpy(pType,"Base system peripherals"); -+ break; -+ case 0x9: -+ strcpy(pType,"Input Devices"); -+ break; -+ case 0xa: -+ strcpy(pType,"Docking stations"); -+ break; -+ case 0xb: -+ strcpy(pType,"Processors"); -+ break; -+ case 0xc: -+ strcpy(pType,"Serial bus controllers"); -+ break; -+ case 0xd: -+ strcpy(pType,"Wireless controllers"); -+ break; -+ case 0xe: -+ strcpy(pType,"Intelligent I/O controllers"); -+ break; -+ case 0xf: -+ strcpy(pType,"Satellite communication controllers"); -+ break; -+ case 0x10: -+ strcpy(pType,"Encryption/Decryption controllers"); -+ break; -+ case 0x11: -+ strcpy(pType,"Data acquisition and signal processing controllers"); -+ break; -+ default: -+ strcpy(pType,"Unknown device"); -+ break; -+ } -+ -+ return MV_OK; -+ -+} -+ -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,323 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvPciUtilsh -+#define __INCmvPciUtilsh -+ -+/* -+This module only support scanning of Header type 00h of pci devices -+There is no suppotr for Header type 01h of pci devices ( PCI bridges ) -+*/ -+ -+/* includes */ -+#include "mvSysHwConfig.h" -+#include "pci-if/mvPciIf.h" -+#include "pci/mvPciRegs.h" -+ -+ -+ -+/* PCI base address low bar mask */ -+#define PCI_ERROR_CODE 0xffffffff -+ -+#define PCI_BRIDGE_CLASS 0x6 -+#define P2P_BRIDGE_SUB_CLASS_CODE 0x4 -+ -+ -+#define P2P_BUSSES_NUM 0x18 -+#define P2P_IO_BASE_LIMIT_SEC_STATUS 0x1C -+#define P2P_MEM_BASE_LIMIT 0x20 -+#define P2P_PREF_MEM_BASE_LIMIT 0x24 -+#define P2P_PREF_BASE_UPPER_32 0x28 -+#define P2P_PREF_LIMIT_UPPER_32 0x2C -+#define P2P_IO_BASE_LIMIT_UPPER_16 0x30 -+#define P2P_EXP_ROM 0x38 -+ -+/* P2P_BUSSES_NUM (PBM) */ -+ -+#define PBM_PRIME_BUS_NUM_OFFS 0 -+#define PBM_PRIME_BUS_NUM_MASK (0xff << PBM_PRIME_BUS_NUM_OFFS) -+ -+#define PBM_SEC_BUS_NUM_OFFS 8 -+#define PBM_SEC_BUS_NUM_MASK (0xff << PBM_SEC_BUS_NUM_OFFS) -+ -+#define PBM_SUB_BUS_NUM_OFFS 16 -+#define PBM_SUB_BUS_NUM_MASK (0xff << PBM_SUB_BUS_NUM_OFFS) -+ -+#define PBM_SEC_LAT_TMR_OFFS 24 -+#define PBM_SEC_LAT_TMR_MASK (0xff << PBM_SEC_LAT_TMR_OFFS) -+ -+/* P2P_IO_BASE_LIMIT_SEC_STATUS (PIBLSS) */ -+ -+#define PIBLSS_IO_BASE_OFFS 0 -+#define PIBLSS_IO_BASE_MASK (0xff << PIBLSS_IO_BASE_OFFS) -+ -+#define PIBLSS_ADD_CAP_OFFS 0 -+#define PIBLSS_ADD_CAP_MASK (0x3 << PIBLSS_ADD_CAP_OFFS) -+#define PIBLSS_ADD_CAP_16BIT (0x0 << PIBLSS_ADD_CAP_OFFS) -+#define PIBLSS_ADD_CAP_32BIT (0x1 << PIBLSS_ADD_CAP_OFFS) -+ -+#define PIBLSS_LOW_ADDR_OFFS 0 -+#define PIBLSS_LOW_ADDR_MASK (0xFFF << PIBLSS_LOW_ADDR_OFFS) -+ -+#define PIBLSS_HIGH_ADDR_OFFS 12 -+#define PIBLSS_HIGH_ADDR_MASK (0xF << PIBLSS_HIGH_ADDR_OFFS) -+ -+#define PIBLSS_IO_LIMIT_OFFS 8 -+#define PIBLSS_IO_LIMIT_MASK (0xff << PIBLSS_IO_LIMIT_OFFS) -+ -+#define PIBLSS_SEC_STATUS_OFFS 16 -+#define PIBLSS_SEC_STATUS_MASK (0xffff << PIBLSS_SEC_STATUS_OFFS) -+ -+ -+/* P2P_MEM_BASE_LIMIT (PMBL)*/ -+ -+#define PMBL_MEM_BASE_OFFS 0 -+#define PMBL_MEM_BASE_MASK (0xffff << PMBL_MEM_BASE_OFFS) -+ -+#define PMBL_MEM_LIMIT_OFFS 16 -+#define PMBL_MEM_LIMIT_MASK (0xffff << PMBL_MEM_LIMIT_OFFS) -+ -+ -+#define PMBL_LOW_ADDR_OFFS 0 -+#define PMBL_LOW_ADDR_MASK (0xFFFFF << PMBL_LOW_ADDR_OFFS) -+ -+#define PMBL_HIGH_ADDR_OFFS 20 -+#define PMBL_HIGH_ADDR_MASK (0xFFF << PMBL_HIGH_ADDR_OFFS) -+ -+ -+/* P2P_PREF_MEM_BASE_LIMIT (PRMBL) */ -+ -+#define PRMBL_PREF_MEM_BASE_OFFS 0 -+#define PRMBL_PREF_MEM_BASE_MASK (0xffff << PRMBL_PREF_MEM_BASE_OFFS) -+ -+#define PRMBL_PREF_MEM_LIMIT_OFFS 16 -+#define PRMBL_PREF_MEM_LIMIT_MASK (0xffff<= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexModeGet: ERR. Invalid PEX interface %d\n",pexIf); -+ return MV_ERROR; -+ } -+ } -+ -+ pexData = MV_REG_READ(PEX_CTRL_REG(pexIf)); -+ -+ switch (pexData & PXCR_DEV_TYPE_CTRL_MASK) -+ { -+ case PXCR_DEV_TYPE_CTRL_CMPLX: -+ pexMode->pexType = MV_PEX_ROOT_COMPLEX; -+ break; -+ case PXCR_DEV_TYPE_CTRL_POINT: -+ pexMode->pexType = MV_PEX_END_POINT; -+ break; -+ -+ } -+ -+ /* Check if we have link */ -+ if (MV_REG_READ(PEX_STATUS_REG(pexIf)) & PXSR_DL_DOWN) -+ { -+ pexMode->pexLinkUp = MV_FALSE; -+ -+ /* If there is no link, the auto negotiation data is worthless */ -+ pexMode->pexWidth = MV_PEX_WITDH_INVALID; -+ } -+ else -+ { -+ pexMode->pexLinkUp = MV_TRUE; -+ -+ /* We have link. The link width is now valid */ -+ pexData = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG)); -+ pexMode->pexWidth = ((pexData & PXLCSR_NEG_LNK_WDTH_MASK) >> -+ PXLCSR_NEG_LNK_WDTH_OFFS); -+ } -+ -+ return MV_OK; -+} -+ -+ -+/* PEX configuration space read write */ -+ -+/******************************************************************************* -+* mvPexConfigRead - Read from configuration space -+* -+* DESCRIPTION: -+* This function performs a 32 bit read from PEX configuration space. -+* It supports both type 0 and type 1 of Configuration Transactions -+* (local and over bridge). In order to read from local bus segment, use -+* bus number retrieved from mvPexLocalBusNumGet(). Other bus numbers -+* will result configuration transaction of type 1 (over bridge). -+* -+* INPUT: -+* pexIf - PEX interface number. -+* bus - PEX segment bus number. -+* dev - PEX device number. -+* func - Function number. -+* regOffs - Register offset. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit register data, 0xffffffff on error -+* -+*******************************************************************************/ -+MV_U32 mvPexConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, -+ MV_U32 regOff) -+{ -+#if defined(PCIE_VIRTUAL_BRIDGE_SUPPORT) -+ return mvPexVrtBrgConfigRead (pexIf, bus, dev, func, regOff); -+} -+ -+MV_U32 mvPexHwConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, -+ MV_U32 regOff) -+{ -+#endif -+ MV_U32 pexData = 0; -+ MV_U32 localDev,localBus; -+ -+ /* Parameter checking */ -+ if (PEX_DEFAULT_IF != pexIf) -+ { -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexConfigRead: ERR. Invalid PEX interface %d\n",pexIf); -+ return 0xFFFFFFFF; -+ } -+ } -+ -+ if (dev >= MAX_PEX_DEVICES) -+ { -+ DB(mvOsPrintf("mvPexConfigRead: ERR. device number illigal %d\n", dev)); -+ return 0xFFFFFFFF; -+ } -+ -+ if (func >= MAX_PEX_FUNCS) -+ { -+ DB(mvOsPrintf("mvPexConfigRead: ERR. function num illigal %d\n", func)); -+ return 0xFFFFFFFF; -+ } -+ -+ if (bus >= MAX_PEX_BUSSES) -+ { -+ DB(mvOsPrintf("mvPexConfigRead: ERR. bus number illigal %d\n", bus)); -+ return MV_ERROR; -+ } -+ -+ DB(mvOsPrintf("mvPexConfigRead: pexIf %d, bus %d, dev %d, func %d, regOff 0x%x\n", -+ pexIf, bus, dev, func, regOff)); -+ -+ localDev = mvPexLocalDevNumGet(pexIf); -+ localBus = mvPexLocalBusNumGet(pexIf); -+ -+ /* Speed up the process. In case on no link, return MV_ERROR */ -+ if ((dev != localDev) || (bus != localBus)) -+ { -+ pexData = MV_REG_READ(PEX_STATUS_REG(pexIf)); -+ -+ if ((pexData & PXSR_DL_DOWN)) -+ { -+ return MV_ERROR; -+ } -+ } -+ -+ /* in PCI Express we have only one device number */ -+ /* and this number is the first number we encounter -+ else that the localDev*/ -+ /* spec pex define return on config read/write on any device */ -+ if (bus == localBus) -+ { -+ if (localDev == 0) -+ { -+ /* if local dev is 0 then the first number we encounter -+ after 0 is 1 */ -+ if ((dev != 1)&&(dev != localDev)) -+ { -+ return MV_ERROR; -+ } -+ } -+ else -+ { -+ /* if local dev is not 0 then the first number we encounter -+ is 0 */ -+ -+ if ((dev != 0)&&(dev != localDev)) -+ { -+ return MV_ERROR; -+ } -+ } -+ if(func != 0 ) /* i.e bridge */ -+ { -+ return MV_ERROR; -+ } -+ } -+ -+ -+ /* Creating PEX address to be passed */ -+ pexData = (bus << PXCAR_BUS_NUM_OFFS); -+ pexData |= (dev << PXCAR_DEVICE_NUM_OFFS); -+ pexData |= (func << PXCAR_FUNC_NUM_OFFS); -+ pexData |= (regOff & PXCAR_REG_NUM_MASK); /* lgacy register space */ -+ /* extended register space */ -+ pexData |=(((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >> -+ PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS); -+ -+ pexData |= PXCAR_CONFIG_EN; -+ -+ /* Write the address to the PEX configuration address register */ -+ MV_REG_WRITE(PEX_CFG_ADDR_REG(pexIf), pexData); -+ -+ DB(mvOsPrintf("mvPexConfigRead:address pexData=%x ",pexData)); -+ -+ -+ /* In order to let the PEX controller absorbed the address of the read */ -+ /* transaction we perform a validity check that the address was written */ -+ if(pexData != MV_REG_READ(PEX_CFG_ADDR_REG(pexIf))) -+ { -+ return MV_ERROR; -+ } -+ -+ /* cleaning Master Abort */ -+ MV_REG_BIT_SET(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_STATUS_AND_COMMAND), -+ PXSAC_MABORT); -+#if 0 -+ /* Guideline (GL# PCI Express-1) Erroneous Read Data on Configuration */ -+ /* This guideline is relevant for all devices except of the following devices: -+ 88F5281-BO and above, 88F5181L-A0 and above, 88F1281 A0 and above -+ 88F6183 A0 and above, 88F6183L */ -+ if ( ( (dev != localDev) || (bus != localBus) ) && -+ ( -+ !(MV_5281_DEV_ID == mvCtrlModelGet())&& -+ !((MV_5181_DEV_ID == mvCtrlModelGet())&& (mvCtrlRevGet() >= MV_5181L_A0_REV))&& -+ !(MV_1281_DEV_ID == mvCtrlModelGet())&& -+ !(MV_6183_DEV_ID == mvCtrlModelGet())&& -+ !(MV_6183L_DEV_ID == mvCtrlModelGet())&& -+ !(MV_6281_DEV_ID == mvCtrlModelGet())&& -+ !(MV_6192_DEV_ID == mvCtrlModelGet())&& -+ !(MV_6190_DEV_ID == mvCtrlModelGet())&& -+ !(MV_6180_DEV_ID == mvCtrlModelGet())&& -+ !(MV_78XX0_DEV_ID == mvCtrlModelGet()) -+ )) -+ { -+ -+ /* PCI-Express configuration read work-around */ -+ -+ /* we will use one of the Punit (AHBToMbus) windows to access the xbar -+ and read the data from there */ -+ /* -+ Need to configure the 2 free Punit (AHB to MBus bridge) -+ address decoding windows: -+ Configure the flash Window to handle Configuration space requests -+ for PEX0/1: -+ 1. write 0x7931/0x7941 to the flash window and the size, -+ 79-xbar attr (pci cfg), 3/4-xbar target (pex0/1), 1-WinEn -+ 2. write base to flash window -+ -+ Configuration transactions from the CPU should write/read the data -+ to/from address of the form: -+ addr[31:28] = 0x5 (for PEX0) or 0x6 (for PEX1) -+ addr[27:24] = extended register number -+ addr[23:16] = bus number -+ addr[15:11] = device number -+ addr[10:8] = function number -+ addr[7:0] = register number -+ */ -+ -+ #include "ctrlEnv/sys/mvAhbToMbus.h" -+ { -+ MV_U32 winNum; -+ MV_AHB_TO_MBUS_DEC_WIN originWin; -+ MV_U32 pciAddr=0; -+ MV_U32 remapLow=0,remapHigh=0; -+ -+ /* -+ We will use DEV_CS2\Flash window for this workarround -+ */ -+ -+ winNum = mvAhbToMbusWinTargetGet(PEX_CONFIG_RW_WA_TARGET); -+ -+ /* save remap values if exist */ -+ if ((1 == winNum)||(0 == winNum)) -+ { -+ remapLow = MV_REG_READ(AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum)); -+ remapHigh = MV_REG_READ(AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum)); -+ -+ } -+ -+ -+ /* save the original window values */ -+ mvAhbToMbusWinGet(winNum,&originWin); -+ -+ if (PEX_CONFIG_RW_WA_USE_ORIGINAL_WIN_VALUES) -+ { -+ /* set the window as xbar window */ -+ if (pexIf) -+ { -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), -+ (0x7931 | (((originWin.addrWin.size >> 16)-1) ) << 16)); -+ } -+ else -+ { -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), -+ (0x7941 | (((originWin.addrWin.size >> 16)-1) ) << 16)); -+ } -+ -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum), -+ originWin.addrWin.baseLow); -+ -+ /*pciAddr = originWin.addrWin.baseLow;*/ -+ pciAddr = (MV_U32)CPU_MEMIO_UNCACHED_ADDR( -+ (MV_U32)originWin.addrWin.baseLow); -+ -+ } -+ else -+ { -+ /* set the window as xbar window */ -+ if (pexIf) -+ { -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), -+ (0x7931 | (((PEX_CONFIG_RW_WA_SIZE >> 16)-1) ) << 16)); -+ } -+ else -+ { -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), -+ (0x7941 | (((PEX_CONFIG_RW_WA_SIZE >> 16)-1) ) << 16)); -+ } -+ -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum), -+ PEX_CONFIG_RW_WA_BASE); -+ -+ pciAddr = (MV_U32)CPU_MEMIO_UNCACHED_ADDR(PEX_CONFIG_RW_WA_BASE); -+ } -+ -+ -+ /* remap should be as base */ -+ if ((1 == winNum)||(0 == winNum)) -+ { -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum),pciAddr); -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum),0); -+ -+ } -+ -+ /* extended register space */ -+ pciAddr |= (bus << 16); -+ pciAddr |= (dev << 11); -+ pciAddr |= (func << 8); -+ pciAddr |= (regOff & PXCAR_REG_NUM_MASK); /* lgacy register space */ -+ -+ pexData = *(MV_U32*)pciAddr; -+ pexData = MV_32BIT_LE(pexData); /* Data always in LE */ -+ -+ /* restore the original window values */ -+ mvAhbToMbusWinSet(winNum,&originWin); -+ -+ /* restore original remap values*/ -+ if ((1 == winNum)||(0 == winNum)) -+ { -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum),remapLow); -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum),remapHigh); -+ -+ } -+ } -+ } -+ else -+#endif -+ { -+ /* Read the Data returned in the PEX Data register */ -+ pexData = MV_REG_READ(PEX_CFG_DATA_REG(pexIf)); -+ -+ } -+ -+ DB(mvOsPrintf("mvPexConfigRead: got : %x \n",pexData)); -+ -+ return pexData; -+ -+} -+ -+/******************************************************************************* -+* mvPexConfigWrite - Write to configuration space -+* -+* DESCRIPTION: -+* This function performs a 32 bit write to PEX configuration space. -+* It supports both type 0 and type 1 of Configuration Transactions -+* (local and over bridge). In order to write to local bus segment, use -+* bus number retrieved from mvPexLocalBusNumGet(). Other bus numbers -+* will result configuration transaction of type 1 (over bridge). -+* -+* INPUT: -+* pexIf - PEX interface number. -+* bus - PEX segment bus number. -+* dev - PEX device number. -+* func - Function number. -+* regOffs - Register offset. -+* data - 32bit data. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data) -+{ -+#if defined(PCIE_VIRTUAL_BRIDGE_SUPPORT) -+ return mvPexVrtBrgConfigWrite (pexIf, bus, dev, func, regOff, data); -+} -+ -+MV_STATUS mvPexHwConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data) -+{ -+#endif -+ MV_U32 pexData = 0; -+ MV_U32 localDev,localBus; -+ -+ /* Parameter checking */ -+ if (PEX_DEFAULT_IF != pexIf) -+ { -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexConfigWrite: ERR. Invalid PEX interface %d\n", -+ pexIf); -+ return MV_ERROR; -+ } -+ } -+ -+ if (dev >= MAX_PEX_DEVICES) -+ { -+ mvOsPrintf("mvPexConfigWrite: ERR. device number illigal %d\n",dev); -+ return MV_BAD_PARAM; -+ } -+ -+ if (func >= MAX_PEX_FUNCS) -+ { -+ mvOsPrintf("mvPexConfigWrite: ERR. function number illigal %d\n", func); -+ return MV_ERROR; -+ } -+ -+ if (bus >= MAX_PEX_BUSSES) -+ { -+ mvOsPrintf("mvPexConfigWrite: ERR. bus number illigal %d\n", bus); -+ return MV_ERROR; -+ } -+ -+ -+ -+ localDev = mvPexLocalDevNumGet(pexIf); -+ localBus = mvPexLocalBusNumGet(pexIf); -+ -+ -+ /* in PCI Express we have only one device number other than ourselves*/ -+ /* and this number is the first number we encounter -+ else than the localDev that can be any valid dev number*/ -+ /* pex spec define return on config read/write on any device */ -+ if (bus == localBus) -+ { -+ -+ if (localDev == 0) -+ { -+ /* if local dev is 0 then the first number we encounter -+ after 0 is 1 */ -+ if ((dev != 1)&&(dev != localDev)) -+ { -+ return MV_ERROR; -+ } -+ -+ } -+ else -+ { -+ /* if local dev is not 0 then the first number we encounter -+ is 0 */ -+ -+ if ((dev != 0)&&(dev != localDev)) -+ { -+ return MV_ERROR; -+ } -+ } -+ -+ -+ } -+ -+ /* if we are not accessing ourselves , then check the link */ -+ if ((dev != localDev) || (bus != localBus) ) -+ { -+ /* workarround */ -+ /* when no link return MV_ERROR */ -+ -+ pexData = MV_REG_READ(PEX_STATUS_REG(pexIf)); -+ -+ if ((pexData & PXSR_DL_DOWN)) -+ { -+ return MV_ERROR; -+ } -+ -+ } -+ -+ pexData =0; -+ -+ /* Creating PEX address to be passed */ -+ pexData |= (bus << PXCAR_BUS_NUM_OFFS); -+ pexData |= (dev << PXCAR_DEVICE_NUM_OFFS); -+ pexData |= (func << PXCAR_FUNC_NUM_OFFS); -+ pexData |= (regOff & PXCAR_REG_NUM_MASK); /* lgacy register space */ -+ /* extended register space */ -+ pexData |=(((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >> -+ PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS); -+ pexData |= PXCAR_CONFIG_EN; -+ -+ DB(mvOsPrintf("mvPexConfigWrite: If=%x bus=%x func=%x dev=%x regOff=%x data=%x \n", -+ pexIf,bus,func,dev,regOff,data,pexData) ); -+ -+ /* Write the address to the PEX configuration address register */ -+ MV_REG_WRITE(PEX_CFG_ADDR_REG(pexIf), pexData); -+ -+ /* Clear CPU pipe. Important where CPU can perform OOO execution */ -+ CPU_PIPE_FLUSH; -+ -+ /* In order to let the PEX controller absorbed the address of the read */ -+ /* transaction we perform a validity check that the address was written */ -+ if(pexData != MV_REG_READ(PEX_CFG_ADDR_REG(pexIf))) -+ { -+ return MV_ERROR; -+ } -+ -+ /* Write the Data passed to the PEX Data register */ -+ MV_REG_WRITE(PEX_CFG_DATA_REG(pexIf), data); -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvPexMasterEnable - Enable/disale PEX interface master transactions. -+* -+* DESCRIPTION: -+* This function performs read modified write to PEX command status -+* (offset 0x4) to set/reset bit 2. After this bit is set, the PEX -+* master is allowed to gain ownership on the bus, otherwise it is -+* incapable to do so. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexMasterEnable(MV_U32 pexIf, MV_BOOL enable) -+{ -+ MV_U32 pexCommandStatus; -+ MV_U32 localBus; -+ MV_U32 localDev; -+ -+ /* Parameter checking */ -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexMasterEnable: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_ERROR; -+ } -+ -+ localBus = mvPexLocalBusNumGet(pexIf); -+ localDev = mvPexLocalDevNumGet(pexIf); -+ -+ pexCommandStatus = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, -+ PEX_STATUS_AND_COMMAND)); -+ -+ -+ if (MV_TRUE == enable) -+ { -+ pexCommandStatus |= PXSAC_MASTER_EN; -+ } -+ else -+ { -+ pexCommandStatus &= ~PXSAC_MASTER_EN; -+ } -+ -+ -+ MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_STATUS_AND_COMMAND), -+ pexCommandStatus); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPexSlaveEnable - Enable/disale PEX interface slave transactions. -+* -+* DESCRIPTION: -+* This function performs read modified write to PEX command status -+* (offset 0x4) to set/reset bit 0 and 1. After those bits are set, -+* the PEX slave is allowed to respond to PEX IO space access (bit 0) -+* and PEX memory space access (bit 1). -+* -+* INPUT: -+* pexIf - PEX interface number. -+* dev - PEX device number. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexSlaveEnable(MV_U32 pexIf, MV_U32 bus,MV_U32 dev, MV_BOOL enable) -+{ -+ MV_U32 pexCommandStatus; -+ MV_U32 RegOffs; -+ -+ /* Parameter checking */ -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexSlaveEnable: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ if (dev >= MAX_PEX_DEVICES) -+ { -+ mvOsPrintf("mvPexLocalDevNumSet: ERR. device number illigal %d\n", dev); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ -+ RegOffs = PEX_STATUS_AND_COMMAND; -+ -+ pexCommandStatus = mvPexConfigRead(pexIf, bus, dev, 0, RegOffs); -+ -+ if (MV_TRUE == enable) -+ { -+ pexCommandStatus |= (PXSAC_IO_EN | PXSAC_MEM_EN); -+ } -+ else -+ { -+ pexCommandStatus &= ~(PXSAC_IO_EN | PXSAC_MEM_EN); -+ } -+ -+ mvPexConfigWrite(pexIf, bus, dev, 0, RegOffs, pexCommandStatus); -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvPexLocalBusNumSet - Set PEX interface local bus number. -+* -+* DESCRIPTION: -+* This function sets given PEX interface its local bus number. -+* Note: In case the PEX interface is PEX-X, the information is read-only. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* busNum - Bus number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_NOT_ALLOWED in case PEX interface is PEX-X. -+* MV_BAD_PARAM on bad parameters , -+* otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexLocalBusNumSet(MV_U32 pexIf, MV_U32 busNum) -+{ -+ MV_U32 pexStatus; -+ MV_U32 localBus; -+ MV_U32 localDev; -+ -+ -+ /* Parameter checking */ -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexLocalBusNumSet: ERR. Invalid PEX interface %d\n",pexIf); -+ return MV_BAD_PARAM; -+ } -+ if (busNum >= MAX_PEX_BUSSES) -+ { -+ mvOsPrintf("mvPexLocalBusNumSet: ERR. bus number illigal %d\n", busNum); -+ return MV_ERROR; -+ -+ } -+ -+ localBus = mvPexLocalBusNumGet(pexIf); -+ localDev = mvPexLocalDevNumGet(pexIf); -+ -+ -+ -+ pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); -+ -+ pexStatus &= ~PXSR_PEX_BUS_NUM_MASK; -+ -+ pexStatus |= (busNum << PXSR_PEX_BUS_NUM_OFFS) & PXSR_PEX_BUS_NUM_MASK; -+ -+ MV_REG_WRITE(PEX_STATUS_REG(pexIf), pexStatus); -+ -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPexLocalBusNumGet - Get PEX interface local bus number. -+* -+* DESCRIPTION: -+* This function gets the local bus number of a given PEX interface. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Local bus number.0xffffffff on Error -+* -+*******************************************************************************/ -+MV_U32 mvPexLocalBusNumGet(MV_U32 pexIf) -+{ -+ MV_U32 pexStatus; -+ -+ /* Parameter checking */ -+ if (PEX_DEFAULT_IF != pexIf) -+ { -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexLocalBusNumGet: ERR. Invalid PEX interface %d\n",pexIf); -+ return 0xFFFFFFFF; -+ } -+ } -+ -+ -+ pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); -+ -+ pexStatus &= PXSR_PEX_BUS_NUM_MASK; -+ -+ return (pexStatus >> PXSR_PEX_BUS_NUM_OFFS); -+ -+} -+ -+ -+/******************************************************************************* -+* mvPexLocalDevNumSet - Set PEX interface local device number. -+* -+* DESCRIPTION: -+* This function sets given PEX interface its local device number. -+* Note: In case the PEX interface is PEX-X, the information is read-only. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* devNum - Device number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_NOT_ALLOWED in case PEX interface is PEX-X. -+* MV_BAD_PARAM on bad parameters , -+* otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexLocalDevNumSet(MV_U32 pexIf, MV_U32 devNum) -+{ -+ MV_U32 pexStatus; -+ MV_U32 localBus; -+ MV_U32 localDev; -+ -+ /* Parameter checking */ -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexLocalDevNumSet: ERR. Invalid PEX interface %d\n",pexIf); -+ return MV_BAD_PARAM; -+ } -+ if (devNum >= MAX_PEX_DEVICES) -+ { -+ mvOsPrintf("mvPexLocalDevNumSet: ERR. device number illigal %d\n", -+ devNum); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ localBus = mvPexLocalBusNumGet(pexIf); -+ localDev = mvPexLocalDevNumGet(pexIf); -+ -+ -+ pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); -+ -+ pexStatus &= ~PXSR_PEX_DEV_NUM_MASK; -+ -+ pexStatus |= (devNum << PXSR_PEX_DEV_NUM_OFFS) & PXSR_PEX_DEV_NUM_MASK; -+ -+ MV_REG_WRITE(PEX_STATUS_REG(pexIf), pexStatus); -+ -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvPexLocalDevNumGet - Get PEX interface local device number. -+* -+* DESCRIPTION: -+* This function gets the local device number of a given PEX interface. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Local device number. 0xffffffff on Error -+* -+*******************************************************************************/ -+MV_U32 mvPexLocalDevNumGet(MV_U32 pexIf) -+{ -+ MV_U32 pexStatus; -+ -+ /* Parameter checking */ -+ -+ if (PEX_DEFAULT_IF != pexIf) -+ { -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexLocalDevNumGet: ERR. Invalid PEX interface %d\n", -+ pexIf); -+ return 0xFFFFFFFF; -+ } -+ } -+ -+ pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); -+ -+ pexStatus &= PXSR_PEX_DEV_NUM_MASK; -+ -+ return (pexStatus >> PXSR_PEX_DEV_NUM_OFFS); -+} -+ -+MV_VOID mvPexPhyRegRead(MV_U32 pexIf, MV_U32 regOffset, MV_U16 *value) -+{ -+ -+ MV_U32 regAddr; -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexPhyRegRead: ERR. Invalid PEX interface %d\n", pexIf); -+ return; -+ } -+ regAddr = (BIT31 | ((regOffset & 0x3fff) << 16)); -+ MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexIf), regAddr); -+ *value = MV_REG_READ(PEX_PHY_ACCESS_REG(pexIf)); -+} -+ -+ -+MV_VOID mvPexPhyRegWrite(MV_U32 pexIf, MV_U32 regOffset, MV_U16 value) -+{ -+ -+ MV_U32 regAddr; -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexPhyRegWrite: ERR. Invalid PEX interface %d\n", pexIf); -+ return; -+ } -+ regAddr = (((regOffset & 0x3fff) << 16) | value); -+ MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexIf), regAddr); -+} -+ -+/******************************************************************************* -+* mvPexActiveStateLinkPMEnable -+* -+* DESCRIPTION: -+* Enable Active Link State Power Management -+* -+* INPUT: -+* pexIf - PEX interface number. -+* enable - MV_TRUE to enable ASPM, MV_FALSE to disable. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* MV_OK on success , MV_ERROR otherwise -+* -+*******************************************************************************/ -+MV_STATUS mvPexActiveStateLinkPMEnable(MV_U32 pexIf, MV_BOOL enable) -+{ -+ MV_U32 reg; -+ -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexActiveStateLinkPMEnable: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_ERROR; -+ } -+ -+ reg = MV_REG_READ(PEX_PWR_MNG_EXT_REG(pexIf)) & ~PXPMER_L1_ASPM_EN_MASK; -+ if(enable == MV_TRUE) -+ reg |= PXPMER_L1_ASPM_EN_MASK; -+ MV_REG_WRITE(PEX_PWR_MNG_EXT_REG(pexIf), reg); -+ -+ /* Enable / Disable L0/1 entry */ -+ reg = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG)) -+ & ~PXLCSR_ASPM_CNT_MASK; -+ if(enable == MV_TRUE) -+ reg |= PXLCSR_ASPM_CNT_L0S_L1S_ENT_SUPP; -+ MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG), reg); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPexForceX1 -+* -+* DESCRIPTION: -+* shut down lanes 1-3 if recognize that attached to an x1 end-point -+* INPUT: -+* pexIf - PEX interface number. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* MV_OK on success , MV_ERROR otherwise -+* -+*******************************************************************************/ -+MV_U32 mvPexForceX1(MV_U32 pexIf) -+{ -+ MV_U32 regData = 0; -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexForceX1: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ -+ regData = MV_REG_READ(PEX_CTRL_REG(pexIf)) & ~(PXCR_CONF_LINK_MASK) ; -+ regData |= PXCR_CONF_LINK_X1; -+ -+ MV_REG_WRITE(PEX_CTRL_REG(pexIf), regData); -+ return MV_OK; -+} -+ -+MV_BOOL mvPexIsPowerUp(MV_U32 pexIf) -+{ -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexIsPowerUp: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_FALSE; -+ } -+ return mvCtrlPwrClckGet(PEX_UNIT_ID, pexIf); -+} -+ -+ -+MV_VOID mvPexPowerDown(MV_U32 pexIf) -+{ -+ if ( (mvCtrlModelGet() == MV_78XX0_DEV_ID) || -+ (mvCtrlModelGet() == MV_76100_DEV_ID) || -+ (mvCtrlModelGet() == MV_78100_DEV_ID) || -+ (mvCtrlModelGet() == MV_78200_DEV_ID) ) -+ { -+ mvCtrlPwrClckSet(PEX_UNIT_ID, pexIf, MV_FALSE); -+ } -+ else -+ { -+ MV_REG_WRITE((0x41B00 -(pexIf)*0x10000), 0x20800087); -+ } -+} -+ -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,168 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCPEXH -+#define __INCPEXH -+ -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "pex/mvPexRegs.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+ -+ -+ -+/* NOTE not supported in this driver:*/ -+ -+ -+/* defines */ -+/* The number of supported PEX interfaces depend on Marvell controller */ -+/* device number. This device number ID is located on the PEX unit */ -+/* configuration header. This creates a loop where calling PEX */ -+/* configuration read/write routine results a call to get PEX configuration */ -+/* information etc. This macro defines a default PEX interface. This PEX */ -+/* interface is sure to exist. */ -+#define PEX_DEFAULT_IF 0 -+ -+ -+/* typedefs */ -+/* The Marvell controller supports both root complex and end point devices */ -+/* This enumeration describes the PEX type. */ -+typedef enum _mvPexType -+{ -+ MV_PEX_ROOT_COMPLEX, /* root complex device */ -+ MV_PEX_END_POINT /* end point device */ -+}MV_PEX_TYPE; -+ -+typedef enum _mvPexWidth -+{ -+ MV_PEX_WITDH_X1 = 1, -+ MV_PEX_WITDH_X2, -+ MV_PEX_WITDH_X3, -+ MV_PEX_WITDH_X4, -+ MV_PEX_WITDH_INVALID -+}MV_PEX_WIDTH; -+ -+/* PEX Bar attributes */ -+typedef struct _mvPexMode -+{ -+ MV_PEX_TYPE pexType; -+ MV_PEX_WIDTH pexWidth; -+ MV_BOOL pexLinkUp; -+}MV_PEX_MODE; -+ -+ -+ -+/* Global Functions prototypes */ -+/* mvPexInit - Initialize PEX interfaces*/ -+MV_STATUS mvPexHalInit(MV_U32 pexIf, MV_PEX_TYPE pexType); -+ -+/* mvPexModeGet - Get Pex If mode */ -+MV_U32 mvPexModeGet(MV_U32 pexIf,MV_PEX_MODE *pexMode); -+ -+/* mvPexConfigRead - Read from configuration space */ -+MV_U32 mvPexConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func,MV_U32 regOff); -+ -+/* mvPexConfigWrite - Write to configuration space */ -+MV_STATUS mvPexConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data); -+ -+/* mvPexMasterEnable - Enable/disale PEX interface master transactions.*/ -+MV_STATUS mvPexMasterEnable(MV_U32 pexIf, MV_BOOL enable); -+ -+/* mvPexSlaveEnable - Enable/disale PEX interface slave transactions.*/ -+MV_STATUS mvPexSlaveEnable(MV_U32 pexIf, MV_U32 bus,MV_U32 dev, MV_BOOL enable); -+ -+/* mvPexLocalBusNumSet - Set PEX interface local bus number.*/ -+MV_STATUS mvPexLocalBusNumSet(MV_U32 pexIf, MV_U32 busNum); -+ -+/* mvPexLocalBusNumGet - Get PEX interface local bus number.*/ -+MV_U32 mvPexLocalBusNumGet(MV_U32 pexIf); -+ -+/* mvPexLocalDevNumSet - Set PEX interface local device number.*/ -+MV_STATUS mvPexLocalDevNumSet(MV_U32 pexIf, MV_U32 devNum); -+ -+/* mvPexLocalDevNumGet - Get PEX interface local device number.*/ -+MV_U32 mvPexLocalDevNumGet(MV_U32 pexIf); -+/* mvPexForceX1 - Force PEX interface to X1 mode. */ -+MV_U32 mvPexForceX1(MV_U32 pexIf); -+ -+/* mvPexIsPowerUp - Is PEX interface Power up? */ -+MV_BOOL mvPexIsPowerUp(MV_U32 pexIf); -+ -+/* mvPexPowerDown - Power Down */ -+MV_VOID mvPexPowerDown(MV_U32 pexIf); -+ -+/* mvPexPowerUp - Power Up */ -+MV_VOID mvPexPowerUp(MV_U32 pexIf); -+ -+/* mvPexPhyRegRead - Pex phy read */ -+MV_VOID mvPexPhyRegRead(MV_U32 pexIf, MV_U32 regOffset, MV_U16 *value); -+ -+/* mvPexPhyRegWrite - Pex phy write */ -+MV_VOID mvPexPhyRegWrite(MV_U32 pexIf, MV_U32 regOffset, MV_U16 value); -+ -+MV_STATUS mvPexActiveStateLinkPMEnable(MV_U32 pexIf, MV_BOOL enable); -+ -+#endif /* #ifndef __INCPEXH */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,751 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCPEXREGSH -+#define __INCPEXREGSH -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* defines */ -+#define MAX_PEX_DEVICES 32 -+#define MAX_PEX_FUNCS 8 -+#define MAX_PEX_BUSSES 256 -+ -+ -+ -+/*********************************************************/ -+/* PCI Express Configuration Cycles Generation Registers */ -+/*********************************************************/ -+ -+#define PEX_CFG_ADDR_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x18F8) -+#define PEX_CFG_DATA_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x18FC) -+#define PEX_PHY_ACCESS_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1B00) -+/* PCI Express Configuration Address Register */ -+/* PEX_CFG_ADDR_REG (PXCAR)*/ -+ -+#define PXCAR_REG_NUM_OFFS 2 -+#define PXCAR_REG_NUM_MAX 0x3F -+#define PXCAR_REG_NUM_MASK (PXCAR_REG_NUM_MAX << PXCAR_REG_NUM_OFFS) -+#define PXCAR_FUNC_NUM_OFFS 8 -+#define PXCAR_FUNC_NUM_MAX 0x7 -+#define PXCAR_FUNC_NUM_MASK (PXCAR_FUNC_NUM_MAX << PXCAR_FUNC_NUM_OFFS) -+#define PXCAR_DEVICE_NUM_OFFS 11 -+#define PXCAR_DEVICE_NUM_MAX 0x1F -+#define PXCAR_DEVICE_NUM_MASK (PXCAR_DEVICE_NUM_MAX << PXCAR_DEVICE_NUM_OFFS) -+#define PXCAR_BUS_NUM_OFFS 16 -+#define PXCAR_BUS_NUM_MAX 0xFF -+#define PXCAR_BUS_NUM_MASK (PXCAR_BUS_NUM_MAX << PXCAR_BUS_NUM_OFFS) -+#define PXCAR_EXT_REG_NUM_OFFS 24 -+#define PXCAR_EXT_REG_NUM_MAX 0xF -+ -+/* in pci express register address is now the legacy register address (8 bits) -+with the new extended register address (more 4 bits) , below is the mask of -+the upper 4 bits of the full register address */ -+ -+#define PXCAR_REAL_EXT_REG_NUM_OFFS 8 -+#define PXCAR_EXT_REG_NUM_MASK (PXCAR_EXT_REG_NUM_MAX << PXCAR_EXT_REG_NUM_OFFS) -+#define PXCAR_CONFIG_EN BIT31 -+ -+#define PXCAR_REAL_EXT_REG_NUM_OFFS 8 -+#define PXCAR_REAL_EXT_REG_NUM_MASK (0xF << PXCAR_REAL_EXT_REG_NUM_OFFS) -+ -+/* The traditional PCI spec defined 6-bit field to describe register offset.*/ -+/* The new PCI Express extend the register offset by an extra 4-bits. */ -+/* The below macro assign 10-bit register offset into the apprpreate */ -+/* fields in the CFG_ADDR_REG */ -+#define PXCAR_REG_OFFS_SET(regOffs) \ -+ ( (regOff & PXCAR_REG_NUM_MASK) | \ -+ ( ((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >> PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS) ) -+ -+/***********************************/ -+/* PCI Express Interrupt registers */ -+/***********************************/ -+#define PEX_CAUSE_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1900) -+#define PEX_MASK_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1910) -+ -+#define PXICR_TX_REQ_IN_DLDOWN_ERR BIT0 /* Transmit request while field */ -+ /* of the PCI Express */ -+/* PCI Express Interrupt Cause */ -+/* PEX_INT_CAUSE_REG (PXICR)*/ -+/* PEX_INT_MASK_REG*/ -+/* -+NOTE:All bits except bits[27:24] are Read/Write Clear only. A cause bit sets -+upon an error event occurrence. A write of 0 clears the bit. A write of 1 has -+no affect. Bits[24:27} are set and cleared upon reception of interrupt -+emulation messages. -+ -+Mask bit per cause bit. If a bit is set to 1, the corresponding event is -+enabled. Mask does not affect setting of the Interrupt Cause register bits; -+it only affects the assertion of the interrupt .*/ -+ -+ -+#define PXICR_MDIS_CAUSE BIT1 /* Attempt to generate PCI transaction -+ while master is disabled */ -+#define PXICR_ERR_WRTO_REG_CAUSE BIT3 /* Erroneous write attempt to -+ PCI Express internal register*/ -+#define PXICR_HIT_DFLT_WIN_ERR BIT4 /* Hit Default Window Error */ -+#define PXICR_RX_RAM_PAR_ERR BIT6 /* Rx RAM Parity Error */ -+#define PXICR_TX_RAM_PAR_ERR BIT7 /* Tx RAM Parity Error */ -+#define PXICR_COR_ERR_DET BIT8 /* Correctable Error Detected*/ -+#define PXICR_NF_ERR_DET BIT9 /* Non-Fatal Error Detected*/ -+#define PXICR_FERR_DET BIT10 /* Fatal Error Detected*/ -+#define PXICR_DSTATE_CHANGE BIT11 /* Dstate Change Indication*/ -+#define PXICR_BIST BIT12 /* PCI-Express BIST activated*/ -+#define PXICR_FLW_CTRL_PROT BIT14 /* Flow Control Protocol Error */ -+ -+#define PXICR_RCV_UR_CA_ERR BIT15 /* Received UR or CA status. */ -+#define PXICR_RCV_ERR_FATAL BIT16 /* Received ERR_FATAL message.*/ -+#define PXICR_RCV_ERR_NON_FATAL BIT17 /* Received ERR_NONFATAL message*/ -+#define PXICR_RCV_ERR_COR BIT18 /* Received ERR_COR message.*/ -+#define PXICR_RCV_CRS BIT19 /* Received CRS completion status*/ -+#define PXICR_SLV_HOT_RESET BIT20 /* Received Hot Reset Indication*/ -+#define PXICR_SLV_DIS_LINK BIT21 /* Slave Disable Link Indication*/ -+#define PXICR_SLV_LB BIT22 /* Slave Loopback Indication*/ -+#define PXICR_LINK_FAIL BIT23 /* Link Failure indication.*/ -+#define PXICR_RCV_INTA BIT24 /* IntA status.*/ -+#define PXICR_RCV_INTB BIT25 /* IntB status.*/ -+#define PXICR_RCV_INTC BIT26 /* IntC status.*/ -+#define PXICR_RCV_INTD BIT27 /* IntD status.*/ -+#define PXICR_RCV_PM_PME BIT28 /* Received PM_PME message. */ -+ -+ -+/********************************************/ -+/* PCI Express Control and Status Registers */ -+/********************************************/ -+#define PEX_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A00) -+#define PEX_STATUS_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A04) -+#define PEX_COMPLT_TMEOUT_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A10) -+#define PEX_PWR_MNG_EXT_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A18) -+#define PEX_FLOW_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A20) -+#define PEX_ACK_TMR_4X_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A30) -+#define PEX_ACK_TMR_1X_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A40) -+#define PEX_TL_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1AB0) -+ -+ -+#define PEX_RAM_PARITY_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A50) -+/* PCI Express Control Register */ -+/* PEX_CTRL_REG (PXCR) */ -+ -+#define PXCR_CONF_LINK_OFFS 0 -+#define PXCR_CONF_LINK_MASK (1 << PXCR_CONF_LINK_OFFS) -+#define PXCR_CONF_LINK_X4 (0 << PXCR_CONF_LINK_OFFS) -+#define PXCR_CONF_LINK_X1 (1 << PXCR_CONF_LINK_OFFS) -+#define PXCR_DEV_TYPE_CTRL_OFFS 1 /*PCI ExpressDevice Type Control*/ -+#define PXCR_DEV_TYPE_CTRL_MASK BIT1 -+#define PXCR_DEV_TYPE_CTRL_CMPLX (1 << PXCR_DEV_TYPE_CTRL_OFFS) -+#define PXCR_DEV_TYPE_CTRL_POINT (0 << PXCR_DEV_TYPE_CTRL_OFFS) -+#define PXCR_CFG_MAP_TO_MEM_EN BIT2 /* Configuration Header Mapping -+ to Memory Space Enable */ -+ -+#define PXCR_CFG_MAP_TO_MEM_EN BIT2 /* Configuration Header Mapping -+ to Memory Space Enable*/ -+ -+#define PXCR_RSRV1_OFFS 5 -+#define PXCR_RSRV1_MASK (0x7 << PXCR_RSRV1_OFFS) -+#define PXCR_RSRV1_VAL (0x0 << PXCR_RSRV1_OFFS) -+ -+#define PXCR_CONF_MAX_OUTSTND_OFFS 8 /*Maximum outstanding NP requests as a master*/ -+#define PXCR_CONF_MAX_OUTSTND_MASK (0x3 << PXCR_CONF_MAX_OUTSTND_OFFS) -+ -+ -+#define PXCR_CONF_NFTS_OFFS 16 /*number of FTS Ordered-Sets*/ -+#define PXCR_CONF_NFTS_MASK (0xff << PXCR_CONF_NFTS_OFFS) -+ -+#define PXCR_CONF_MSTR_HOT_RESET BIT24 /*Master Hot-Reset.*/ -+#define PXCR_CONF_MSTR_LB BIT26 /* Master Loopback */ -+#define PXCR_CONF_MSTR_DIS_SCRMB BIT27 /* Master Disable Scrambling*/ -+#define PXCR_CONF_DIRECT_DIS_SCRMB BIT28 /* Direct Disable Scrambling*/ -+ -+/* PCI Express Status Register */ -+/* PEX_STATUS_REG (PXSR) */ -+ -+#define PXSR_DL_DOWN BIT0 /* DL_Down indication.*/ -+ -+#define PXSR_PEX_BUS_NUM_OFFS 8 /* Bus Number Indication */ -+#define PXSR_PEX_BUS_NUM_MASK (0xff << PXSR_PEX_BUS_NUM_OFFS) -+ -+#define PXSR_PEX_DEV_NUM_OFFS 16 /* Device Number Indication */ -+#define PXSR_PEX_DEV_NUM_MASK (0x1f << PXSR_PEX_DEV_NUM_OFFS) -+ -+#define PXSR_PEX_SLV_HOT_RESET BIT24 /* Slave Hot Reset Indication*/ -+#define PXSR_PEX_SLV_DIS_LINK BIT25 /* Slave Disable Link Indication*/ -+#define PXSR_PEX_SLV_LB BIT26 /* Slave Loopback Indication*/ -+#define PXSR_PEX_SLV_DIS_SCRMB BIT27 /* Slave Disable Scrambling Indication*/ -+ -+ -+/* PCI Express Completion Timeout Register */ -+/* PEX_COMPLT_TMEOUT_REG (PXCTR)*/ -+ -+#define PXCTR_CMP_TO_THRSHLD_OFFS 0 /* Completion Timeout Threshold */ -+#define PXCTR_CMP_TO_THRSHLD_MASK (0xffff << PXCTR_CMP_TO_THRSHLD_OFFS) -+ -+/* PCI Express Power Management Extended Register */ -+/* PEX_PWR_MNG_EXT_REG (PXPMER) */ -+ -+#define PXPMER_L1_ASPM_EN_OFFS 1 -+#define PXPMER_L1_ASPM_EN_MASK (0x1 << PXPMER_L1_ASPM_EN_OFFS) -+ -+/* PCI Express Flow Control Register */ -+/* PEX_FLOW_CTRL_REG (PXFCR)*/ -+ -+#define PXFCR_PH_INIT_FC_OFFS 0 /*Posted Headers Flow Control Credit -+ Initial Value.*/ -+#define PXFCR_PH_INIT_FC_MASK (0xff << PXFCR_PH_INIT_FC_OFFS) -+ -+ -+#define PXFCR_NPH_INIT_FC_OFFS 8 /* Classified Non-Posted Headers -+ Flow Control Credit Initial Value*/ -+#define PXFCR_NPH_INIT_FC_MASK (0xff << PXFCR_NPH_INIT_FC_OFFS) -+ -+#define PXFCR_CH_INIT_FC_OFFS 16 /* Completion Headers Flow Control -+ Credit Initial Value Infinite*/ -+ -+#define PXFCR_CH_INIT_FC_MASK (0xff << PXFCR_CH_INIT_FC_OFFS) -+ -+#define PXFCR_FC_UPDATE_TO_OFFS 24 /* Flow Control Update Timeout */ -+#define PXFCR_FC_UPDATE_TO_MASK (0xff << PXFCR_FC_UPDATE_TO_OFFS) -+ -+/* PCI Express Acknowledge Timers (4X) Register */ -+/* PEX_ACK_TMR_4X_REG (PXAT4R) */ -+#define PXAT1R_ACK_LAT_TOX4_OFFS 0 /* Ack Latency Timer Timeout Value */ -+#define PXAT1R_ACK_LAT_TOX4_MASK (0xffff << PXAT4R_ACK_LAT_TOX1_OFFS) -+#define PXAT1R_ACK_RPLY_TOX4_OFFS 16 /* Ack Replay Timer Timeout Value */ -+#define PXAT1R_ACK_RPLY_TOX4_MASK (0xffff << PXAT1R_ACK_RPLY_TOX1_OFFS) -+ -+/* PCI Express Acknowledge Timers (1X) Register */ -+/* PEX_ACK_TMR_1X_REG (PXAT1R) */ -+ -+#define PXAT1R_ACK_LAT_TOX1_OFFS 0 /* Acknowledge Latency Timer Timeout -+ Value for 1X Link*/ -+#define PXAT1R_ACK_LAT_TOX1_MASK (0xffff << PXAT1R_ACK_LAT_TOX1_OFFS) -+ -+#define PXAT1R_ACK_RPLY_TOX1_OFFS 16 /* Acknowledge Replay Timer Timeout -+ Value for 1X*/ -+#define PXAT1R_ACK_RPLY_TOX1_MASK (0xffff << PXAT1R_ACK_RPLY_TOX1_OFFS) -+ -+ -+/* PCI Express TL Control Register */ -+/* PEX_TL_CTRL_REG (PXTCR) */ -+ -+#define PXTCR_TX_CMP_BUFF_NO_OFFS 8 /*Number of completion buffers in Tx*/ -+#define PXTCR_TX_CMP_BUFF_NO_MASK (0xf << PXTCR_TX_CMP_BUFF_NO_OFFS) -+ -+/* PCI Express Debug MAC Control Register */ -+/* PEX_DEBUG_MAC_CTRL_REG (PXDMCR) */ -+ -+#define PXDMCR_LINKUP BIT4 -+ -+ -+ -+/**********************************************/ -+/* PCI Express Configuration Header Registers */ -+/**********************************************/ -+#define PEX_CFG_DIRECT_ACCESS(pexIf,cfgReg) ((PEX_IF_BASE(pexIf)) + (cfgReg)) -+ -+#define PEX_DEVICE_AND_VENDOR_ID 0x000 -+#define PEX_STATUS_AND_COMMAND 0x004 -+#define PEX_CLASS_CODE_AND_REVISION_ID 0x008 -+#define PEX_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE 0x00C -+#define PEX_MEMORY_BAR_BASE_ADDR(barNum) (0x010 + ((barNum) << 2)) -+#define PEX_MV_BAR_BASE(barNum) (0x010 + (barNum) * 8) -+#define PEX_MV_BAR_BASE_HIGH(barNum) (0x014 + (barNum) * 8) -+#define PEX_BAR0_INTER_REG 0x010 -+#define PEX_BAR0_INTER_REG_HIGH 0x014 -+#define PEX_BAR1_REG 0x018 -+#define PEX_BAR1_REG_HIGH 0x01C -+#define PEX_BAR2_REG 0x020 -+#define PEX_BAR2_REG_HIGH 0x024 -+ -+#define PEX_SUBSYS_ID_AND_SUBSYS_VENDOR_ID 0x02C -+#define PEX_EXPANSION_ROM_BASE_ADDR_REG 0x030 -+#define PEX_CAPABILTY_LIST_POINTER 0x034 -+#define PEX_INTERRUPT_PIN_AND_LINE 0x03C -+ -+/* capability list */ -+#define PEX_POWER_MNG_CAPABILITY 0x040 -+#define PEX_POWER_MNG_STATUS_CONTROL 0x044 -+ -+#define PEX_MSI_MESSAGE_CONTROL 0x050 -+#define PEX_MSI_MESSAGE_ADDR 0x054 -+#define PEX_MSI_MESSAGE_HIGH_ADDR 0x058 -+#define PEX_MSI_MESSAGE_DATA 0x05C -+ -+#define PEX_CAPABILITY_REG 0x60 -+#define PEX_DEV_CAPABILITY_REG 0x64 -+#define PEX_DEV_CTRL_STAT_REG 0x68 -+#define PEX_LINK_CAPABILITY_REG 0x6C -+#define PEX_LINK_CTRL_STAT_REG 0x70 -+ -+#define PEX_ADV_ERR_RPRT_HDR_TRGT_REG 0x100 -+#define PEX_UNCORRECT_ERR_STAT_REG 0x104 -+#define PEX_UNCORRECT_ERR_MASK_REG 0x108 -+#define PEX_UNCORRECT_ERR_SERVITY_REG 0x10C -+#define PEX_CORRECT_ERR_STAT_REG 0x110 -+#define PEX_CORRECT_ERR_MASK_REG 0x114 -+#define PEX_ADV_ERR_CAPABILITY_CTRL_REG 0x118 -+#define PEX_HDR_LOG_FIRST_DWORD_REG 0x11C -+#define PEX_HDR_LOG_SECOND_DWORD_REG 0x120 -+#define PEX_HDR_LOG_THIRD_DWORD_REG 0x124 -+#define PEX_HDR_LOG_FOURTH_DWORD_REG 0x128 -+ -+ -+ -+/* PCI Express Device and Vendor ID Register*/ -+/*PEX_DEVICE_AND_VENDOR_ID (PXDAVI)*/ -+ -+#define PXDAVI_VEN_ID_OFFS 0 /* Vendor ID */ -+#define PXDAVI_VEN_ID_MASK (0xffff << PXDAVI_VEN_ID_OFFS) -+ -+#define PXDAVI_DEV_ID_OFFS 16 /* Device ID */ -+#define PXDAVI_DEV_ID_MASK (0xffff << PXDAVI_DEV_ID_OFFS) -+ -+ -+/* PCI Express Command and Status Register*/ -+/*PEX_STATUS_AND_COMMAND (PXSAC)*/ -+ -+#define PXSAC_IO_EN BIT0 /* IO Enable */ -+#define PXSAC_MEM_EN BIT1 /* Memory Enable */ -+#define PXSAC_MASTER_EN BIT2 /* Master Enable */ -+#define PXSAC_PERR_EN BIT6 /* Parity Errors Respond Enable */ -+#define PXSAC_SERR_EN BIT8 /* Ability to assert SERR# line */ -+#define PXSAC_INT_DIS BIT10 /* Interrupt Disable */ -+#define PXSAC_INT_STAT BIT19 /* Interrupt Status */ -+#define PXSAC_CAP_LIST BIT20 /* Capability List Support */ -+#define PXSAC_MAS_DATA_PERR BIT24 /* Master Data Parity Error */ -+#define PXSAC_SLAVE_TABORT BIT27 /* Signalled Target Abort */ -+#define PXSAC_RT_ABORT BIT28 /* Recieved Target Abort */ -+#define PXSAC_MABORT BIT29 /* Recieved Master Abort */ -+#define PXSAC_SYSERR BIT30 /* Signalled system error */ -+#define PXSAC_DET_PARERR BIT31 /* Detect Parity Error */ -+ -+ -+/* PCI Express Class Code and Revision ID Register*/ -+/*PEX_CLASS_CODE_AND_REVISION_ID (PXCCARI)*/ -+ -+#define PXCCARI_REVID_OFFS 0 /* Revision ID */ -+#define PXCCARI_REVID_MASK (0xff << PXCCARI_REVID_OFFS) -+ -+#define PXCCARI_FULL_CLASS_OFFS 8 /* Full Class Code */ -+#define PXCCARI_FULL_CLASS_MASK (0xffffff << PXCCARI_FULL_CLASS_OFFS) -+ -+#define PXCCARI_PROGIF_OFFS 8 /* Prog .I/F*/ -+#define PXCCARI_PROGIF_MASK (0xff << PXCCARI_PROGIF_OFFS) -+ -+#define PXCCARI_SUB_CLASS_OFFS 16 /* Sub Class*/ -+#define PXCCARI_SUB_CLASS_MASK (0xff << PXCCARI_SUB_CLASS_OFFS) -+ -+#define PXCCARI_BASE_CLASS_OFFS 24 /* Base Class*/ -+#define PXCCARI_BASE_CLASS_MASK (0xff << PXCCARI_BASE_CLASS_OFFS) -+ -+ -+/* PCI Express BIST, Header Type and Cache Line Size Register*/ -+/*PEX_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE (PXBHTLTCL)*/ -+ -+#define PXBHTLTCL_CACHELINE_OFFS 0 /* Specifies the cache line size */ -+#define PXBHTLTCL_CACHELINE_MASK (0xff << PXBHTLTCL_CACHELINE_OFFS) -+ -+#define PXBHTLTCL_HEADTYPE_FULL_OFFS 16 /* Full Header Type */ -+#define PXBHTLTCL_HEADTYPE_FULL_MASK (0xff << PXBHTLTCL_HEADTYPE_FULL_OFFS) -+ -+#define PXBHTLTCL_MULTI_FUNC BIT23 /* Multi/Single function */ -+ -+#define PXBHTLTCL_HEADER_OFFS 16 /* Header type */ -+#define PXBHTLTCL_HEADER_MASK (0x7f << PXBHTLTCL_HEADER_OFFS) -+#define PXBHTLTCL_HEADER_STANDARD (0x0 << PXBHTLTCL_HEADER_OFFS) -+#define PXBHTLTCL_HEADER_PCI2PCI_BRIDGE (0x1 << PXBHTLTCL_HEADER_OFFS) -+ -+ -+#define PXBHTLTCL_BISTCOMP_OFFS 24 /* BIST Completion Code */ -+#define PXBHTLTCL_BISTCOMP_MASK (0xf << PXBHTLTCL_BISTCOMP_OFFS) -+ -+#define PXBHTLTCL_BISTACT BIT30 /* BIST Activate bit */ -+#define PXBHTLTCL_BISTCAP BIT31 /* BIST Capable Bit */ -+#define PXBHTLTCL_BISTCAP_OFFS 31 -+#define PXBHTLTCL_BISTCAP_MASK BIT31 -+#define PXBHTLTCL_BISTCAP_VAL 0 -+ -+ -+/* PCI Express Subsystem Device and Vendor ID */ -+/*PEX_SUBSYS_ID_AND_SUBSYS_VENDOR_ID (PXSIASVI)*/ -+ -+#define PXSIASVI_VENID_OFFS 0 /* Subsystem Manufacturer Vendor ID Number */ -+#define PXSIASVI_VENID_MASK (0xffff << PXSIASVI_VENID_OFFS) -+ -+#define PXSIASVI_DEVID_OFFS 16 /* Subsystem Device ID Number */ -+#define PXSIASVI_DEVID_MASK (0xffff << PXSIASVI_DEVID_OFFS) -+ -+ -+/* PCI Express Capability List Pointer Register*/ -+/*PEX_CAPABILTY_LIST_POINTER (PXCLP)*/ -+ -+#define PXCLP_CAPPTR_OFFS 0 /* Capability List Pointer */ -+#define PXCLP_CAPPTR_MASK (0xff << PXCLP_CAPPTR_OFFS) -+ -+/* PCI Express Interrupt Pin and Line Register */ -+/*PEX_INTERRUPT_PIN_AND_LINE (PXIPAL)*/ -+ -+#define PXIPAL_INTLINE_OFFS 0 /* Interrupt line (IRQ) */ -+#define PXIPAL_INTLINE_MASK (0xff << PXIPAL_INTLINE_OFFS) -+ -+#define PXIPAL_INTPIN_OFFS 8 /* interrupt pin (A,B,C,D) */ -+#define PXIPAL_INTPIN_MASK (0xff << PXIPAL_INTPIN_OFFS) -+ -+ -+/* PCI Express Power Management Capability Header Register*/ -+/*PEX_POWER_MNG_CAPABILITY (PXPMC)*/ -+ -+#define PXPMC_CAP_ID_OFFS 0 /* Capability ID */ -+#define PXPMC_CAP_ID_MASK (0xff << PXPMC_CAP_ID_OFFS) -+ -+#define PXPMC_NEXT_PTR_OFFS 8 /* Next Item Pointer */ -+#define PXPMC_NEXT_PTR_MASK (0xff << PXPMC_NEXT_PTR_OFFS) -+ -+#define PXPMC_PMC_VER_OFFS 16 /* PCI Power Management Capability Version*/ -+#define PXPMC_PMC_VER_MASK (0x7 << PXPMC_PMC_VER_OFFS) -+ -+#define PXPMC_DSI BIT21/* Device Specific Initialization */ -+ -+#define PXPMC_AUX_CUR_OFFS 22 /* Auxiliary Current Requirements */ -+#define PXPMC_AUX_CUR_MASK (0x7 << PXPMC_AUX_CUR_OFFS) -+ -+#define PXPMC_D1_SUP BIT25 /* D1 Power Management support*/ -+ -+#define PXPMC_D2_SUP BIT26 /* D2 Power Management support*/ -+ -+#define PXPMC_PME_SUP_OFFS 27 /* PM Event generation support*/ -+#define PXPMC_PME_SUP_MASK (0x1f << PXPMC_PME_SUP_OFFS) -+ -+/* PCI Express Power Management Control and Status Register*/ -+/*PEX_POWER_MNG_STATUS_CONTROL (PXPMSC)*/ -+ -+#define PXPMSC_PM_STATE_OFFS 0 /* Power State */ -+#define PXPMSC_PM_STATE_MASK (0x3 << PXPMSC_PM_STATE_OFFS) -+#define PXPMSC_PM_STATE_D0 (0x0 << PXPMSC_PM_STATE_OFFS) -+#define PXPMSC_PM_STATE_D1 (0x1 << PXPMSC_PM_STATE_OFFS) -+#define PXPMSC_PM_STATE_D2 (0x2 << PXPMSC_PM_STATE_OFFS) -+#define PXPMSC_PM_STATE_D3 (0x3 << PXPMSC_PM_STATE_OFFS) -+ -+#define PXPMSC_PME_EN BIT8/* PM_PME Message Generation Enable */ -+ -+#define PXPMSC_PM_DATA_SEL_OFFS 9 /* Data Select*/ -+#define PXPMSC_PM_DATA_SEL_MASK (0xf << PXPMSC_PM_DATA_SEL_OFFS) -+ -+#define PXPMSC_PM_DATA_SCALE_OFFS 13 /* Data Scale */ -+#define PXPMSC_PM_DATA_SCALE_MASK (0x3 << PXPMSC_PM_DATA_SCALE_OFFS) -+ -+#define PXPMSC_PME_STAT BIT15/* PME Status */ -+ -+#define PXPMSC_PM_DATA_OFFS 24 /* State Data */ -+#define PXPMSC_PM_DATA_MASK (0xff << PXPMSC_PM_DATA_OFFS) -+ -+ -+/* PCI Express MSI Message Control Register*/ -+/*PEX_MSI_MESSAGE_CONTROL (PXMMC)*/ -+ -+#define PXMMC_CAP_ID_OFFS 0 /* Capability ID */ -+#define PXMMC_CAP_ID_MASK (0xff << PXMMC_CAP_ID_OFFS) -+ -+#define PXMMC_NEXT_PTR_OFFS 8 /* Next Item Pointer */ -+#define PXMMC_NEXT_PTR_MASK (0xff << PXMMC_NEXT_PTR_OFFS) -+ -+#define PXMMC_MSI_EN BIT18 /* MSI Enable */ -+ -+#define PXMMC_MULTI_CAP_OFFS 17 /* Multiple Message Capable */ -+#define PXMMC_MULTI_CAP_MASK (0x7 << PXMMC_MULTI_CAP_OFFS) -+ -+#define PXMMC_MULTI_EN_OFFS 20 /* Multiple Messages Enable */ -+#define PXMMC_MULTI_EN_MASK (0x7 << PXMMC_MULTI_EN_OFFS) -+ -+#define PXMMC_ADDR64 BIT23 /* 64-bit Addressing Capable */ -+ -+ -+/* PCI Express MSI Message Address Register*/ -+/*PEX_MSI_MESSAGE_ADDR (PXMMA)*/ -+ -+#define PXMMA_MSI_ADDR_OFFS 2 /* Message Address corresponds to -+ Address[31:2] of the MSI MWr TLP*/ -+#define PXMMA_MSI_ADDR_MASK (0x3fffffff << PXMMA_MSI_ADDR_OFFS) -+ -+ -+/* PCI Express MSI Message Address (High) Register */ -+/*PEX_MSI_MESSAGE_HIGH_ADDR (PXMMHA)*/ -+ -+#define PXMMA_MSI_ADDR_H_OFFS 0 /* Message Upper Address corresponds to -+ Address[63:32] of the MSI MWr TLP*/ -+#define PXMMA_MSI_ADDR_H_MASK (0xffffffff << PXMMA_MSI_ADDR_H_OFFS ) -+ -+ -+/* PCI Express MSI Message Data Register*/ -+/*PEX_MSI_MESSAGE_DATA (PXMMD)*/ -+ -+#define PXMMD_MSI_DATA_OFFS 0 /* Message Data */ -+#define PXMMD_MSI_DATA_MASK (0xffff << PXMMD_MSI_DATA_OFFS ) -+ -+ -+/* PCI Express Capability Register*/ -+/*PEX_CAPABILITY_REG (PXCR)*/ -+ -+#define PXCR_CAP_ID_OFFS 0 /* Capability ID*/ -+#define PXCR_CAP_ID_MASK (0xff << PXCR_CAP_ID_OFFS) -+ -+#define PXCR_NEXT_PTR_OFFS 8 /* Next Item Pointer*/ -+#define PXCR_NEXT_PTR_MASK (0xff << PXCR_NEXT_PTR_OFFS) -+ -+#define PXCR_CAP_VER_OFFS 16 /* Capability Version*/ -+#define PXCR_CAP_VER_MASK (0xf << PXCR_CAP_VER_OFFS) -+ -+#define PXCR_DEV_TYPE_OFFS 20 /* Device/Port Type*/ -+#define PXCR_DEV_TYPE_MASK (0xf << PXCR_DEV_TYPE_OFFS) -+ -+#define PXCR_SLOT_IMP BIT24 /* Slot Implemented*/ -+ -+#define PXCR_INT_MSG_NUM_OFFS 25 /* Interrupt Message Number*/ -+#define PXCR_INT_MSG_NUM_MASK (0x1f << PXCR_INT_MSG_NUM_OFFS) -+ -+ -+/* PCI Express Device Capabilities Register */ -+/*PEX_DEV_CAPABILITY_REG (PXDCR)*/ -+ -+#define PXDCR_MAX_PLD_SIZE_SUP_OFFS 0 /* Maximum Payload Size Supported*/ -+#define PXDCR_MAX_PLD_SIZE_SUP_MASK (0x7 << PXDCR_MAX_PLD_SIZE_SUP_OFFS) -+ -+#define PXDCR_EP_L0S_ACC_LAT_OFFS 6/* Endpoint L0s Acceptable Latency*/ -+#define PXDCR_EP_L0S_ACC_LAT_MASK (0x7 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+#define PXDCR_EP_L0S_ACC_LAT_64NS_LESS (0x0 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+#define PXDCR_EP_L0S_ACC_LAT_64NS_128NS (0x1 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+#define PXDCR_EP_L0S_ACC_LAT_128NS_256NS (0x2 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+#define PXDCR_EP_L0S_ACC_LAT_256NS_512NS (0x3 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+#define PXDCR_EP_L0S_ACC_LAT_512NS_1US (0x4 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+#define PXDCR_EP_L0S_ACC_LAT_1US_2US (0x5 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+#define PXDCR_EP_L0S_ACC_LAT_2US_4US (0x6 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+#define PXDCR_EP_L0S_ACC_LAT_4US_MORE (0x7 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+ -+#define PXDCR_EP_L1_ACC_LAT_OFFS 9 /* Endpoint L1 Acceptable Latency*/ -+#define PXDCR_EP_L1_ACC_LAT_MASK (0x7 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXDCR_EP_L1_ACC_LAT_64NS_LESS (0x0 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXDCR_EP_L1_ACC_LAT_64NS_128NS (0x1 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXDCR_EP_L1_ACC_LAT_128NS_256NS (0x2 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXDCR_EP_L1_ACC_LAT_256NS_512NS (0x3 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXDCR_EP_L1_ACC_LAT_512NS_1US (0x4 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXDCR_EP_L1_ACC_LAT_1US_2US (0x5 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXDCR_EP_L1_ACC_LAT_2US_4US (0x6 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXDCR_EP_L1_ACC_LAT_4US_MORE (0x7 << PXDCR_EP_L1_ACC_LAT_OFFS) -+ -+ -+#define PXDCR_ATT_BUT_PRS_OFFS 12 /* Attention Button Present*/ -+#define PXDCR_ATT_BUT_PRS_MASK BIT12 -+#define PXDCR_ATT_BUT_PRS_IMPLEMENTED BIT12 -+ -+#define PXDCR_ATT_IND_PRS_OFFS 13 /* Attention Indicator Present*/ -+#define PXDCR_ATT_IND_PRS_MASK BIT13 -+#define PXDCR_ATT_IND_PRS_IMPLEMENTED BIT13 -+ -+#define PXDCR_PWR_IND_PRS_OFFS 14/* Power Indicator Present*/ -+#define PXDCR_PWR_IND_PRS_MASK BIT14 -+#define PXDCR_PWR_IND_PRS_IMPLEMENTED BIT14 -+ -+#define PXDCR_CAP_SPL_VAL_OFFS 18 /*Captured Slot Power Limit -+ Value*/ -+#define PXDCR_CAP_SPL_VAL_MASK (0xff << PXDCR_CAP_SPL_VAL_OFFS) -+ -+#define PXDCR_CAP_SP_LSCL_OFFS 26 /* Captured Slot Power Limit -+ Scale */ -+#define PXDCR_CAP_SP_LSCL_MASK (0x3 << PXDCR_CAP_SP_LSCL_OFFS) -+ -+/* PCI Express Device Control Status Register */ -+/*PEX_DEV_CTRL_STAT_REG (PXDCSR)*/ -+ -+#define PXDCSR_COR_ERR_REP_EN BIT0 /* Correctable Error Reporting Enable*/ -+#define PXDCSR_NF_ERR_REP_EN BIT1 /* Non-Fatal Error Reporting Enable*/ -+#define PXDCSR_F_ERR_REP_EN BIT2 /* Fatal Error Reporting Enable*/ -+#define PXDCSR_UR_REP_EN BIT3 /* Unsupported Request (UR) -+ Reporting Enable*/ -+#define PXDCSR_EN_RO BIT4 /* Enable Relaxed Ordering*/ -+ -+#define PXDCSR_MAX_PLD_SZ_OFFS 5 /* Maximum Payload Size*/ -+#define PXDCSR_MAX_PLD_SZ_MASK (0x7 << PXDCSR_MAX_PLD_SZ_OFFS) -+#define PXDCSR_MAX_PLD_SZ_128B (0x0 << PXDCSR_MAX_PLD_SZ_OFFS) -+#define PXDCSR_EN_NS BIT11 /* Enable No Snoop*/ -+ -+#define PXDCSR_MAX_RD_RQ_SZ_OFFS 12 /* Maximum Read Request Size*/ -+#define PXDCSR_MAX_RD_RQ_SZ_MASK (0x7 << PXDCSR_MAX_RD_RQ_SZ_OFFS) -+#define PXDCSR_MAX_RD_RQ_SZ_128B (0x0 << PXDCSR_MAX_RD_RQ_SZ_OFFS) -+#define PXDCSR_MAX_RD_RQ_SZ_256B (0x1 << PXDCSR_MAX_RD_RQ_SZ_OFFS) -+#define PXDCSR_MAX_RD_RQ_SZ_512B (0x2 << PXDCSR_MAX_RD_RQ_SZ_OFFS) -+#define PXDCSR_MAX_RD_RQ_SZ_1KB (0x3 << PXDCSR_MAX_RD_RQ_SZ_OFFS) -+#define PXDCSR_MAX_RD_RQ_SZ_2KB (0x4 << PXDCSR_MAX_RD_RQ_SZ_OFFS) -+#define PXDCSR_MAX_RD_RQ_SZ_4KB (0x5 << PXDCSR_MAX_RD_RQ_SZ_OFFS) -+ -+#define PXDCSR_COR_ERR_DET BIT16 /* Correctable Error Detected*/ -+#define PXDCSR_NF_ERR_DET BIT17 /* Non-Fatal Error Detected.*/ -+#define PXDCSR_F_ERR_DET BIT18 /* Fatal Error Detected.*/ -+#define PXDCSR_UR_DET BIT19 /* Unsupported Request Detected */ -+#define PXDCSR_AUX_PWR_DET BIT20 /* Reserved*/ -+ -+#define PXDCSR_TRANS_PEND_OFFS 21 /* Transactions Pending*/ -+#define PXDCSR_TRANS_PEND_MASK BIT21 -+#define PXDCSR_TRANS_PEND_NOT_COMPLETED (0x1 << PXDCSR_TRANS_PEND_OFFS) -+ -+ -+/* PCI Express Link Capabilities Register*/ -+/*PEX_LINK_CAPABILITY_REG (PXLCR)*/ -+ -+#define PXLCR_MAX_LINK_SPD_OFFS 0 /* Maximum Link Speed*/ -+#define PXLCR_MAX_LINK_SPD_MASK (0xf << PXLCR_MAX_LINK_SPD_OFFS) -+ -+#define PXLCR_MAX_LNK_WDTH_OFFS 3 /* Maximum Link Width*/ -+#define PXLCR_MAX_LNK_WDTH_MASK (0x3f << PXLCR_MAX_LNK_WDTH_OFFS) -+ -+#define PXLCR_ASPM_SUP_OFFS 10 /* Active State Link PM Support*/ -+#define PXLCR_ASPM_SUP_MASK (0x3 << PXLCR_ASPM_SUP_OFFS) -+ -+#define PXLCR_L0S_EXT_LAT_OFFS 12 /* L0s Exit Latency*/ -+#define PXLCR_L0S_EXT_LAT_MASK (0x7 << PXLCR_L0S_EXT_LAT_OFFS) -+#define PXLCR_L0S_EXT_LAT_64NS_LESS (0x0 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXLCR_L0S_EXT_LAT_64NS_128NS (0x1 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXLCR_L0S_EXT_LAT_128NS_256NS (0x2 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXLCR_L0S_EXT_LAT_256NS_512NS (0x3 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXLCR_L0S_EXT_LAT_512NS_1US (0x4 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXLCR_L0S_EXT_LAT_1US_2US (0x5 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXLCR_L0S_EXT_LAT_2US_4US (0x6 << PXDCR_EP_L1_ACC_LAT_OFFS) -+ -+#define PXLCR_POR_TNUM_OFFS 24 /* Port Number */ -+#define PXLCR_POR_TNUM_MASK (0xff << PXLCR_POR_TNUM_OFFS) -+ -+/* PCI Express Link Control Status Register */ -+/*PEX_LINK_CTRL_STAT_REG (PXLCSR)*/ -+ -+#define PXLCSR_ASPM_CNT_OFFS 0 /* Active State Link PM Control */ -+#define PXLCSR_ASPM_CNT_MASK (0x3 << PXLCSR_ASPM_CNT_OFFS) -+#define PXLCSR_ASPM_CNT_DISABLED (0x0 << PXLCSR_ASPM_CNT_OFFS) -+#define PXLCSR_ASPM_CNT_L0S_ENT_SUPP (0x1 << PXLCSR_ASPM_CNT_OFFS) -+#define PXLCSR_ASPM_CNT_L1S_ENT_SUPP (0x2 << PXLCSR_ASPM_CNT_OFFS) -+#define PXLCSR_ASPM_CNT_L0S_L1S_ENT_SUPP (0x3 << PXLCSR_ASPM_CNT_OFFS) -+ -+#define PXLCSR_RCB_OFFS 3 /* Read Completion Boundary */ -+#define PXLCSR_RCB_MASK BIT3 -+#define PXLCSR_RCB_64B (0 << PXLCSR_RCB_OFFS) -+#define PXLCSR_RCB_128B (1 << PXLCSR_RCB_OFFS) -+ -+#define PXLCSR_LNK_DIS BIT4 /* Link Disable */ -+#define PXLCSR_RETRN_LNK BIT5 /* Retrain Link */ -+#define PXLCSR_CMN_CLK_CFG BIT6 /* Common Clock Configuration */ -+#define PXLCSR_EXTD_SNC BIT7 /* Extended Sync */ -+ -+#define PXLCSR_LNK_SPD_OFFS 16 /* Link Speed */ -+#define PXLCSR_LNK_SPD_MASK (0xf << PXLCSR_LNK_SPD_OFFS) -+ -+#define PXLCSR_NEG_LNK_WDTH_OFFS 20 /* Negotiated Link Width */ -+#define PXLCSR_NEG_LNK_WDTH_MASK (0x3f << PXLCSR_NEG_LNK_WDTH_OFFS) -+#define PXLCSR_NEG_LNK_WDTH_X1 (0x1 << PXLCSR_NEG_LNK_WDTH_OFFS) -+ -+#define PXLCSR_LNK_TRN BIT27 /* Link Training */ -+ -+#define PXLCSR_SLT_CLK_CFG_OFFS 28 /* Slot Clock Configuration */ -+#define PXLCSR_SLT_CLK_CFG_MASK BIT28 -+#define PXLCSR_SLT_CLK_CFG_INDPNT (0x0 << PXLCSR_SLT_CLK_CFG_OFFS) -+#define PXLCSR_SLT_CLK_CFG_REF (0x1 << PXLCSR_SLT_CLK_CFG_OFFS) -+ -+/* PCI Express Advanced Error Report Header Register */ -+/*PEX_ADV_ERR_RPRT_HDR_TRGT_REG (PXAERHTR)*/ -+ -+/* PCI Express Uncorrectable Error Status Register*/ -+/*PEX_UNCORRECT_ERR_STAT_REG (PXUESR)*/ -+ -+/* PCI Express Uncorrectable Error Mask Register */ -+/*PEX_UNCORRECT_ERR_MASK_REG (PXUEMR)*/ -+ -+/* PCI Express Uncorrectable Error Severity Register */ -+/*PEX_UNCORRECT_ERR_SERVITY_REG (PXUESR)*/ -+ -+/* PCI Express Correctable Error Status Register */ -+/*PEX_CORRECT_ERR_STAT_REG (PXCESR)*/ -+ -+/* PCI Express Correctable Error Mask Register */ -+/*PEX_CORRECT_ERR_MASK_REG (PXCEMR)*/ -+ -+/* PCI Express Advanced Error Capability and Control Register*/ -+/*PEX_ADV_ERR_CAPABILITY_CTRL_REG (PXAECCR)*/ -+ -+/* PCI Express Header Log First DWORD Register*/ -+/*PEX_HDR_LOG_FIRST_DWORD_REG (PXHLFDR)*/ -+ -+/* PCI Express Header Log Second DWORD Register*/ -+/*PEX_HDR_LOG_SECOND_DWORD_REG (PXHLSDR)*/ -+ -+/* PCI Express Header Log Third DWORD Register*/ -+/*PEX_HDR_LOG_THIRD_DWORD_REG (PXHLTDR)*/ -+ -+/* PCI Express Header Log Fourth DWORD Register*/ -+/*PEX_HDR_LOG_FOURTH_DWORD_REG (PXHLFDR)*/ -+ -+#ifdef __cplusplus -+} -+#endif /* __cplusplus */ -+ -+#endif /* #ifndef __INCPEXREGSH */ -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,313 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "mvPex.h" -+ -+//#define MV_DEBUG -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+/* locals */ -+typedef struct -+{ -+ MV_U32 data; -+ MV_U32 mask; -+}PEX_HEADER_DATA; -+ -+/* local function forwad decleration */ -+MV_U32 mvPexHwConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, -+ MV_U32 regOff); -+MV_STATUS mvPexHwConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data); -+void resetPexConfig(MV_U32 pexIf, MV_U32 bus, MV_U32 dev); -+ -+ -+PEX_HEADER_DATA configHdr[16] = -+{ -+{0x888811ab, 0x00000000}, /*[device ID, vendor ID] */ -+{0x00100007, 0x0000ffff}, /*[status register, command register] */ -+{0x0604000e, 0x00000000}, /*[programming interface, sub class code, class code, revision ID] */ -+{0x00010008, 0x00000000}, /*[BIST, header type, latency time, cache line] */ -+{0x00000000, 0x00000000}, /*[base address 0] */ -+{0x00000000, 0x00000000}, /*[base address 1] */ -+{0x00000000, 0x00ffffff}, /*[secondary latency timersubordinate bus number, secondary bus number, primary bus number] */ -+{0x0000f101, 0x00000000}, /*[secondary status ,IO limit, IO base] */ -+{0x9ff0a000, 0x00000000}, /*[memory limit, memory base] */ -+{0x0001fff1, 0x00000000}, /*[prefetch memory limit, prefetch memory base] */ -+{0xffffffff, 0x00000000}, /*[prefetch memory base upper] */ -+{0x00000000, 0x00000000}, /*[prefetch memory limit upper] */ -+{0xeffff000, 0x00000000}, /*[IO limit upper 16 bits, IO base upper 16 bits] */ -+{0x00000000, 0x00000000}, /*[reserved, capability pointer] */ -+{0x00000000, 0x00000000}, /*[expansion ROM base address] */ -+{0x00000000, 0x000000FF}, /*[bridge control, interrupt pin, interrupt line] */ -+}; -+ -+ -+#define HEADER_WRITE(data, offset) configHdr[offset/4].data = ((configHdr[offset/4].data & ~configHdr[offset/4].mask) | \ -+ (data & configHdr[offset/4].mask)) -+#define HEADER_READ(offset) configHdr[offset/4].data -+ -+/******************************************************************************* -+* mvVrtBrgPexInit - Initialize PEX interfaces -+* -+* DESCRIPTION: -+* -+* This function is responsible of intialization of the Pex Interface , It -+* configure the Pex Bars and Windows in the following manner: -+* -+* Assumptions : -+* Bar0 is always internal registers bar -+* Bar1 is always the DRAM bar -+* Bar2 is always the Device bar -+* -+* 1) Sets the Internal registers bar base by obtaining the base from -+* the CPU Interface -+* 2) Sets the DRAM bar base and size by getting the base and size from -+* the CPU Interface when the size is the sum of all enabled DRAM -+* chip selects and the base is the base of CS0 . -+* 3) Sets the Device bar base and size by getting these values from the -+* CPU Interface when the base is the base of the lowest base of the -+* Device chip selects, and the -+* -+* -+* INPUT: -+* -+* pexIf - PEX interface number. -+* -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK if function success otherwise MV_ERROR or MV_BAD_PARAM -+* -+*******************************************************************************/ -+MV_STATUS mvPexVrtBrgInit(MV_U32 pexIf) -+{ -+ /* reset PEX tree to recover previous U-boot/Boot configurations */ -+ MV_U32 localBus = mvPexLocalBusNumGet(pexIf); -+ -+ -+ resetPexConfig(pexIf, localBus, 1); -+ return MV_OK; -+} -+ -+ -+MV_U32 mvPexVrtBrgConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, -+ MV_U32 regOff) -+{ -+ -+ MV_U32 localBus = mvPexLocalBusNumGet(pexIf); -+ MV_U32 localDev = mvPexLocalDevNumGet(pexIf); -+ MV_U32 val; -+ if(bus == localBus) -+ { -+ if(dev > 1) -+ { -+/* on the local device allow only device #0 & #1 */ -+ return 0xffffffff; -+ } -+ else -+ if (dev == localDev) -+ { -+ /* read the memory controller registers */ -+ return mvPexHwConfigRead (pexIf, bus, dev, func, regOff); -+ } -+ else -+ { -+ /* access the virtual brg header */ -+ return HEADER_READ(regOff); -+ } -+ } -+ else -+ if(bus == (localBus + 1)) -+ { -+ /* access the device behind the virtual bridge */ -+ if((dev == localDev) || (dev > 1)) -+ { -+ return 0xffffffff; -+ } -+ else -+ { -+ /* access the device behind the virtual bridge, in this case -+ * change the bus number to the local bus number in order to -+ * generate type 0 config cycle -+ */ -+ mvPexLocalBusNumSet(pexIf, bus); -+ mvPexLocalDevNumSet(pexIf, 1); -+ val = mvPexHwConfigRead (pexIf, bus, 0, func, regOff); -+ mvPexLocalBusNumSet(pexIf, localBus); -+ mvPexLocalDevNumSet(pexIf, localDev); -+ return val; -+ } -+ } -+ /* for all other devices use the HW function to get the -+ * requested registers -+ */ -+ mvPexLocalDevNumSet(pexIf, 1); -+ val = mvPexHwConfigRead (pexIf, bus, dev, func, regOff); -+ mvPexLocalDevNumSet(pexIf, localDev); -+ return val; -+} -+ -+ -+MV_STATUS mvPexVrtBrgConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data) -+{ -+ MV_U32 localBus = mvPexLocalBusNumGet(pexIf); -+ MV_U32 localDev = mvPexLocalDevNumGet(pexIf); -+ MV_STATUS status; -+ -+ if(bus == localBus) -+ { -+ if(dev > 1) -+ { -+ /* on the local device allow only device #0 & #1 */ -+ return MV_ERROR; -+ } -+ else -+ if (dev == localDev) -+ { -+ /* read the memory controller registers */ -+ return mvPexHwConfigWrite (pexIf, bus, dev, func, regOff, data); -+ } -+ else -+ { -+ /* access the virtual brg header */ -+ HEADER_WRITE(data, regOff); -+ return MV_OK; -+ } -+ } -+ else -+ if(bus == (localBus + 1)) -+ { -+ /* access the device behind the virtual bridge */ -+ if((dev == localDev) || (dev > 1)) -+ { -+ return MV_ERROR; -+ } -+ else -+ { -+ /* access the device behind the virtual bridge, in this case -+ * change the bus number to the local bus number in order to -+ * generate type 0 config cycle -+ */ -+ //return mvPexHwConfigWrite (pexIf, localBus, dev, func, regOff, data); -+ mvPexLocalBusNumSet(pexIf, bus); -+ mvPexLocalDevNumSet(pexIf, 1); -+ status = mvPexHwConfigWrite (pexIf, bus, 0, func, regOff, data); -+ mvPexLocalBusNumSet(pexIf, localBus); -+ mvPexLocalDevNumSet(pexIf, localDev); -+ return status; -+ -+ } -+ } -+ /* for all other devices use the HW function to get the -+ * requested registers -+ */ -+ mvPexLocalDevNumSet(pexIf, 1); -+ status = mvPexHwConfigWrite (pexIf, bus, dev, func, regOff, data); -+ mvPexLocalDevNumSet(pexIf, localDev); -+ return status; -+} -+ -+ -+ -+ -+void resetPexConfig(MV_U32 pexIf, MV_U32 bus, MV_U32 dev) -+{ -+ MV_U32 tData; -+ MV_U32 i; -+ -+ /* restore the PEX configuration to initialization state */ -+ /* in case PEX P2P call recursive and reset config */ -+ tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x0); -+ if(tData != 0xffffffff) -+ { -+ /* agent had been found - check whether P2P */ -+ tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x8); -+ if((tData & 0xffff0000) == 0x06040000) -+ {/* P2P */ -+ /* get the sec bus and the subordinate */ -+ MV_U32 secBus; -+ tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x18); -+ secBus = ((tData >> 8) & 0xff); -+ /* now scan on sec bus */ -+ for(i = 0;i < 0xff;i++) -+ { -+ resetPexConfig(pexIf, secBus, i); -+ } -+ /* now reset this device */ -+ DB(mvOsPrintf("Reset bus %d dev %d\n", bus, dev)); -+ mvPexHwConfigWrite(pexIf, bus, dev, 0x0, 0x18, 0x0); -+ DB(mvOsPrintf("Reset bus %d dev %d\n", bus, dev)); -+ } -+ } -+} -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,82 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCVRTBRGPEXH -+#define __INCVRTBRGPEXH -+ -+ -+/* Global Functions prototypes */ -+/* mvPexInit - Initialize PEX interfaces*/ -+MV_STATUS mvPexVrtBrgInit(MV_U32 pexIf); -+ -+/* mvPexConfigRead - Read from configuration space */ -+MV_U32 mvPexVrtBrgConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func,MV_U32 regOff); -+ -+/* mvPexConfigWrite - Write to configuration space */ -+MV_STATUS mvPexVrtBrgConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data); -+ -+ -+#endif /* #ifndef __INCPEXH */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvCompVer.txt linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvCompVer.txt ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvCompVer.txt 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvCompVer.txt 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,4 @@ -+Global HAL Version: FEROCEON_HAL_3_1_7 -+Unit HAL Version: 3.1.3 -+Description: This component includes an implementation of the unit HAL drivers -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,1522 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#include "mvOs.h" -+#include "sflash/mvSFlash.h" -+#include "sflash/mvSFlashSpec.h" -+#include "spi/mvSpi.h" -+#include "spi/mvSpiCmnd.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+ -+/*#define MV_DEBUG*/ -+#ifdef MV_DEBUG -+#define DB(x) x -+#else -+#define DB(x) -+#endif -+ -+/* Globals */ -+static MV_SFLASH_DEVICE_PARAMS sflash[] = { -+ /* ST M25P32 SPI flash, 4MB, 64 sectors of 64K each */ -+ { -+ MV_M25P_WREN_CMND_OPCD, -+ MV_M25P_WRDI_CMND_OPCD, -+ MV_M25P_RDID_CMND_OPCD, -+ MV_M25P_RDSR_CMND_OPCD, -+ MV_M25P_WRSR_CMND_OPCD, -+ MV_M25P_READ_CMND_OPCD, -+ MV_M25P_FAST_RD_CMND_OPCD, -+ MV_M25P_PP_CMND_OPCD, -+ MV_M25P_SE_CMND_OPCD, -+ MV_M25P_BE_CMND_OPCD, -+ MV_M25P_RES_CMND_OPCD, -+ MV_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */ -+ MV_M25P32_SECTOR_SIZE, -+ MV_M25P32_SECTOR_NUMBER, -+ MV_M25P_PAGE_SIZE, -+ "ST M25P32", -+ MV_M25PXXX_ST_MANF_ID, -+ MV_M25P32_DEVICE_ID, -+ MV_M25P32_MAX_SPI_FREQ, -+ MV_M25P32_MAX_FAST_SPI_FREQ, -+ MV_M25P32_FAST_READ_DUMMY_BYTES -+ }, -+ /* ST M25P64 SPI flash, 8MB, 128 sectors of 64K each */ -+ { -+ MV_M25P_WREN_CMND_OPCD, -+ MV_M25P_WRDI_CMND_OPCD, -+ MV_M25P_RDID_CMND_OPCD, -+ MV_M25P_RDSR_CMND_OPCD, -+ MV_M25P_WRSR_CMND_OPCD, -+ MV_M25P_READ_CMND_OPCD, -+ MV_M25P_FAST_RD_CMND_OPCD, -+ MV_M25P_PP_CMND_OPCD, -+ MV_M25P_SE_CMND_OPCD, -+ MV_M25P_BE_CMND_OPCD, -+ MV_M25P_RES_CMND_OPCD, -+ MV_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */ -+ MV_M25P64_SECTOR_SIZE, -+ MV_M25P64_SECTOR_NUMBER, -+ MV_M25P_PAGE_SIZE, -+ "ST M25P64", -+ MV_M25PXXX_ST_MANF_ID, -+ MV_M25P64_DEVICE_ID, -+ MV_M25P64_MAX_SPI_FREQ, -+ MV_M25P64_MAX_FAST_SPI_FREQ, -+ MV_M25P64_FAST_READ_DUMMY_BYTES -+ }, -+ /* ST M25P128 SPI flash, 16MB, 64 sectors of 256K each */ -+ { -+ MV_M25P_WREN_CMND_OPCD, -+ MV_M25P_WRDI_CMND_OPCD, -+ MV_M25P_RDID_CMND_OPCD, -+ MV_M25P_RDSR_CMND_OPCD, -+ MV_M25P_WRSR_CMND_OPCD, -+ MV_M25P_READ_CMND_OPCD, -+ MV_M25P_FAST_RD_CMND_OPCD, -+ MV_M25P_PP_CMND_OPCD, -+ MV_M25P_SE_CMND_OPCD, -+ MV_M25P_BE_CMND_OPCD, -+ MV_M25P_RES_CMND_OPCD, -+ MV_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */ -+ MV_M25P128_SECTOR_SIZE, -+ MV_M25P128_SECTOR_NUMBER, -+ MV_M25P_PAGE_SIZE, -+ "ST M25P128", -+ MV_M25PXXX_ST_MANF_ID, -+ MV_M25P128_DEVICE_ID, -+ MV_M25P128_MAX_SPI_FREQ, -+ MV_M25P128_MAX_FAST_SPI_FREQ, -+ MV_M25P128_FAST_READ_DUMMY_BYTES -+ }, -+ /* Macronix MXIC MX25L6405 SPI flash, 8MB, 128 sectors of 64K each */ -+ { -+ MV_MX25L_WREN_CMND_OPCD, -+ MV_MX25L_WRDI_CMND_OPCD, -+ MV_MX25L_RDID_CMND_OPCD, -+ MV_MX25L_RDSR_CMND_OPCD, -+ MV_MX25L_WRSR_CMND_OPCD, -+ MV_MX25L_READ_CMND_OPCD, -+ MV_MX25L_FAST_RD_CMND_OPCD, -+ MV_MX25L_PP_CMND_OPCD, -+ MV_MX25L_SE_CMND_OPCD, -+ MV_MX25L_BE_CMND_OPCD, -+ MV_MX25L_RES_CMND_OPCD, -+ MV_MX25L_DP_CMND_OPCD, -+ MV_MX25L6405_SECTOR_SIZE, -+ MV_MX25L6405_SECTOR_NUMBER, -+ MV_MXIC_PAGE_SIZE, -+ "MXIC MX25L6405", -+ MV_MXIC_MANF_ID, -+ MV_MX25L6405_DEVICE_ID, -+ MV_MX25L6405_MAX_SPI_FREQ, -+ MV_MX25L6405_MAX_FAST_SPI_FREQ, -+ MV_MX25L6405_FAST_READ_DUMMY_BYTES -+ }, -+ /* SPANSION S25FL128P SPI flash, 16MB, 64 sectors of 256K each */ -+ { -+ MV_S25FL_WREN_CMND_OPCD, -+ MV_S25FL_WRDI_CMND_OPCD, -+ MV_S25FL_RDID_CMND_OPCD, -+ MV_S25FL_RDSR_CMND_OPCD, -+ MV_S25FL_WRSR_CMND_OPCD, -+ MV_S25FL_READ_CMND_OPCD, -+ MV_S25FL_FAST_RD_CMND_OPCD, -+ MV_S25FL_PP_CMND_OPCD, -+ MV_S25FL_SE_CMND_OPCD, -+ MV_S25FL_BE_CMND_OPCD, -+ MV_S25FL_RES_CMND_OPCD, -+ MV_S25FL_DP_CMND_OPCD, -+ MV_S25FL128_SECTOR_SIZE, -+ MV_S25FL128_SECTOR_NUMBER, -+ MV_S25FL_PAGE_SIZE, -+ "SPANSION S25FL128", -+ MV_SPANSION_MANF_ID, -+ MV_S25FL128_DEVICE_ID, -+ MV_S25FL128_MAX_SPI_FREQ, -+ MV_M25P128_MAX_FAST_SPI_FREQ, -+ MV_M25P128_FAST_READ_DUMMY_BYTES -+ } -+}; -+ -+/* Static Functions */ -+static MV_STATUS mvWriteEnable (MV_SFLASH_INFO * pFlinfo); -+static MV_STATUS mvStatusRegGet (MV_SFLASH_INFO * pFlinfo, MV_U8 * pStatReg); -+static MV_STATUS mvStatusRegSet (MV_SFLASH_INFO * pFlinfo, MV_U8 sr); -+static MV_STATUS mvWaitOnWipClear(MV_SFLASH_INFO * pFlinfo); -+static MV_STATUS mvSFlashPageWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, \ -+ MV_U8* pPageBuff, MV_U32 buffSize); -+static MV_STATUS mvSFlashWithDefaultsIdGet (MV_SFLASH_INFO * pFlinfo, \ -+ MV_U8* manId, MV_U16* devId); -+ -+/******************************************************************************* -+* mvWriteEnable - serialize the write enable sequence -+* -+* DESCRIPTION: -+* transmit the sequence for write enable -+* -+********************************************************************************/ -+static MV_STATUS mvWriteEnable(MV_SFLASH_INFO * pFlinfo) -+{ -+ MV_U8 cmd[MV_SFLASH_WREN_CMND_LENGTH]; -+ -+ -+ cmd[0] = sflash[pFlinfo->index].opcdWREN; -+ -+ return mvSpiWriteThenRead(cmd, MV_SFLASH_WREN_CMND_LENGTH, NULL, 0, 0); -+} -+ -+/******************************************************************************* -+* mvStatusRegGet - Retrieve the value of the status register -+* -+* DESCRIPTION: -+* perform the RDSR sequence to get the 8bit status register -+* -+********************************************************************************/ -+static MV_STATUS mvStatusRegGet(MV_SFLASH_INFO * pFlinfo, MV_U8 * pStatReg) -+{ -+ MV_STATUS ret; -+ MV_U8 cmd[MV_SFLASH_RDSR_CMND_LENGTH]; -+ MV_U8 sr[MV_SFLASH_RDSR_REPLY_LENGTH]; -+ -+ -+ -+ -+ cmd[0] = sflash[pFlinfo->index].opcdRDSR; -+ -+ if ((ret = mvSpiWriteThenRead(cmd, MV_SFLASH_RDSR_CMND_LENGTH, sr, -+ MV_SFLASH_RDSR_REPLY_LENGTH,0)) != MV_OK) -+ return ret; -+ -+ *pStatReg = sr[0]; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvWaitOnWipClear - Block waiting for the WIP (write in progress) to be cleared -+* -+* DESCRIPTION: -+* Block waiting for the WIP (write in progress) to be cleared -+* -+********************************************************************************/ -+static MV_STATUS mvWaitOnWipClear(MV_SFLASH_INFO * pFlinfo) -+{ -+ MV_STATUS ret; -+ MV_U32 i; -+ MV_U8 stat; -+ -+ for (i=0; iindex].opcdWRSR; -+ cmd[1] = sr; -+ -+ if ((ret = mvSpiWriteThenRead(cmd, MV_SFLASH_WRSR_CMND_LENGTH, NULL, 0, 0)) != MV_OK) -+ return ret; -+ -+ if ((ret = mvWaitOnWipClear(pFlinfo)) != MV_OK) -+ return ret; -+ -+ mvOsDelay(1); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSFlashPageWr - Write up to 256 Bytes in the same page -+* -+* DESCRIPTION: -+* Write a buffer up to the page size in length provided that the whole address -+* range is within the same page (alligned to page bounderies) -+* -+*******************************************************************************/ -+static MV_STATUS mvSFlashPageWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, -+ MV_U8* pPageBuff, MV_U32 buffSize) -+{ -+ MV_STATUS ret; -+ MV_U8 cmd[MV_SFLASH_PP_CMND_LENGTH]; -+ -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invalid parameter device index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* check that we do not cross the page bounderies */ -+ if (((offset & (sflash[pFlinfo->index].pageSize - 1)) + buffSize) > -+ sflash[pFlinfo->index].pageSize) -+ { -+ DB(mvOsPrintf("%s WARNING: Page allignment problem!\n", __FUNCTION__);) -+ return MV_OUT_OF_RANGE; -+ } -+ -+ /* Issue the Write enable command prior the page program command */ -+ if ((ret = mvWriteEnable(pFlinfo)) != MV_OK) -+ return ret; -+ -+ cmd[0] = sflash[pFlinfo->index].opcdPP; -+ cmd[1] = ((offset >> 16) & 0xFF); -+ cmd[2] = ((offset >> 8) & 0xFF); -+ cmd[3] = (offset & 0xFF); -+ -+ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_PP_CMND_LENGTH, pPageBuff, buffSize)) != MV_OK) -+ return ret; -+ -+ if ((ret = mvWaitOnWipClear(pFlinfo)) != MV_OK) -+ return ret; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSFlashWithDefaultsIdGet - Try to read the manufacturer and Device IDs from -+* the device using the default RDID opcode and the default WREN opcode. -+* -+* DESCRIPTION: -+* This is used to detect a generic device that uses the default opcodes -+* for the WREN and RDID. -+* -+********************************************************************************/ -+static MV_STATUS mvSFlashWithDefaultsIdGet (MV_SFLASH_INFO * pFlinfo, MV_U8* manId, MV_U16* devId) -+{ -+ MV_STATUS ret; -+ MV_U8 cmdRDID[MV_SFLASH_RDID_CMND_LENGTH]; -+ MV_U8 id[MV_SFLASH_RDID_REPLY_LENGTH]; -+ -+ -+ -+ /* Use the default RDID opcode to read the IDs */ -+ cmdRDID[0] = MV_SFLASH_DEFAULT_RDID_OPCD; /* unknown model try default */ -+ if ((ret = mvSpiWriteThenRead(cmdRDID, MV_SFLASH_RDID_CMND_LENGTH, id, MV_SFLASH_RDID_REPLY_LENGTH, 0)) != MV_OK) -+ return ret; -+ -+ *manId = id[0]; -+ *devId = 0; -+ *devId |= (id[1] << 8); -+ *devId |= id[2]; -+ -+ return MV_OK; -+} -+ -+/* -+##################################################################################### -+##################################################################################### -+*/ -+ -+/******************************************************************************* -+* mvSFlashInit - Initialize the serial flash device -+* -+* DESCRIPTION: -+* Perform the neccessary initialization and configuration -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* pFlinfo->baseAddr: base address in fast mode. -+* pFlinfo->index: Index of the flash in the sflash tabel. If the SPI -+* flash device does not support read Id command with -+* the standard opcode, then the user should supply this -+* as an input to skip the autodetection process!!!! -+* -+* OUTPUT: -+* pFlinfo: pointer to the Flash information structure after detection -+* pFlinfo->manufacturerId: Manufacturer ID -+* pFlinfo->deviceId: Device ID -+* pFlinfo->sectorSize: size of the sector (all sectors are the same). -+* pFlinfo->sectorNumber: number of sectors. -+* pFlinfo->pageSize: size of the page. -+* pFlinfo->index: Index of the detected flash in the sflash tabel -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashInit (MV_SFLASH_INFO * pFlinfo) -+{ -+ MV_STATUS ret; -+ MV_U8 manf; -+ MV_U16 dev; -+ MV_U32 indx; -+ MV_BOOL detectFlag = MV_FALSE; -+ -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Initialize the SPI interface with low frequency to make sure that the read ID succeeds */ -+ if ((ret = mvSpiInit(MV_SFLASH_BASIC_SPI_FREQ)) != MV_OK) -+ { -+ mvOsPrintf("%s ERROR: Failed to initialize the SPI interface!\n", __FUNCTION__); -+ return ret; -+ } -+ -+ /* First try to read the Manufacturer and Device IDs */ -+ if ((ret = mvSFlashIdGet(pFlinfo, &manf, &dev)) != MV_OK) -+ { -+ mvOsPrintf("%s ERROR: Failed to get the SFlash ID!\n", __FUNCTION__); -+ return ret; -+ } -+ -+ /* loop over the whole table and look for the appropriate SFLASH */ -+ for (indx=0; indxmanufacturerId = manf; -+ pFlinfo->deviceId = dev; -+ pFlinfo->index = indx; -+ detectFlag = MV_TRUE; -+ } -+ } -+ -+ if(!detectFlag) -+ { -+ mvOsPrintf("%s ERROR: Unknown SPI flash device!\n", __FUNCTION__); -+ return MV_FAIL; -+ } -+ -+ /* fill the info based on the model detected */ -+ pFlinfo->sectorSize = sflash[pFlinfo->index].sectorSize; -+ pFlinfo->sectorNumber = sflash[pFlinfo->index].sectorNumber; -+ pFlinfo->pageSize = sflash[pFlinfo->index].pageSize; -+ -+ /* Set the SPI frequency to the MAX allowed for the device for best performance */ -+ if ((ret = mvSpiBaudRateSet(sflash[pFlinfo->index].spiMaxFreq)) != MV_OK) -+ { -+ mvOsPrintf("%s ERROR: Failed to set the SPI frequency!\n", __FUNCTION__); -+ return ret; -+ } -+ -+ /* As default lock the SR */ -+ if ((ret = mvSFlashStatRegLock(pFlinfo, MV_TRUE)) != MV_OK) -+ return ret; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSFlashSectorErase - Erasse a single sector of the serial flash -+* -+* DESCRIPTION: -+* Issue the erase sector command and address -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* secNumber: sector Number to erase (0 -> (sectorNumber-1)) -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashSectorErase (MV_SFLASH_INFO * pFlinfo, MV_U32 secNumber) -+{ -+ MV_STATUS ret; -+ MV_U8 cmd[MV_SFLASH_SE_CMND_LENGTH]; -+ -+ MV_U32 secAddr = (secNumber * pFlinfo->sectorSize); -+#if 0 -+ MV_U32 i; -+ MV_U32 * pW = (MV_U32*) (secAddr + pFlinfo->baseAddr); -+ MV_U32 erasedWord = 0xFFFFFFFF; -+ MV_U32 wordsPerSector = (pFlinfo->sectorSize / sizeof(MV_U32)); -+ MV_BOOL eraseNeeded = MV_FALSE; -+#endif -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* check that the sector number is valid */ -+ if (secNumber >= pFlinfo->sectorNumber) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter sector number!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* we don't want to access SPI in direct mode from in-direct API, -+ becasue of timing issue between CS asserts. */ -+#if 0 -+ /* First compare to FF and check if erase is needed */ -+ for (i=0; iindex].opcdSE; -+ cmd[1] = ((secAddr >> 16) & 0xFF); -+ cmd[2] = ((secAddr >> 8) & 0xFF); -+ cmd[3] = (secAddr & 0xFF); -+ -+ /* Issue the Write enable command prior the sector erase command */ -+ if ((ret = mvWriteEnable(pFlinfo)) != MV_OK) -+ return ret; -+ -+ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_SE_CMND_LENGTH, NULL, 0)) != MV_OK) -+ return ret; -+ -+ if ((ret = mvWaitOnWipClear(pFlinfo)) != MV_OK) -+ return ret; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSFlashChipErase - Erasse the whole serial flash -+* -+* DESCRIPTION: -+* Issue the bulk (chip) erase command -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashChipErase (MV_SFLASH_INFO * pFlinfo) -+{ -+ MV_STATUS ret; -+ MV_U8 cmd[MV_SFLASH_BE_CMND_LENGTH]; -+ -+ -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ cmd[0] = sflash[pFlinfo->index].opcdBE; -+ -+ /* Issue the Write enable command prior the Bulk erase command */ -+ if ((ret = mvWriteEnable(pFlinfo)) != MV_OK) -+ return ret; -+ -+ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_BE_CMND_LENGTH, NULL, 0)) != MV_OK) -+ return ret; -+ -+ if ((ret = mvWaitOnChipEraseDone(pFlinfo)) != MV_OK) -+ return ret; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSFlashBlockRd - Read from the serial flash -+* -+* DESCRIPTION: -+* Issue the read command and address then perfom the needed read -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* offset: byte offset with the flash to start reading from -+* pReadBuff: pointer to the buffer to read the data in -+* buffSize: size of the buffer to read. -+* -+* OUTPUT: -+* pReadBuff: pointer to the buffer containing the read data -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, -+ MV_U8* pReadBuff, MV_U32 buffSize) -+{ -+ MV_U8 cmd[MV_SFLASH_READ_CMND_LENGTH]; -+ -+ -+ /* check for NULL pointer */ -+ if ((pFlinfo == NULL) || (pReadBuff == NULL)) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ cmd[0] = sflash[pFlinfo->index].opcdREAD; -+ cmd[1] = ((offset >> 16) & 0xFF); -+ cmd[2] = ((offset >> 8) & 0xFF); -+ cmd[3] = (offset & 0xFF); -+ -+ return mvSpiWriteThenRead(cmd, MV_SFLASH_READ_CMND_LENGTH, pReadBuff, buffSize, 0); -+} -+ -+/******************************************************************************* -+* mvSFlashFastBlockRd - Fast read from the serial flash -+* -+* DESCRIPTION: -+* Issue the fast read command and address then perfom the needed read -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* offset: byte offset with the flash to start reading from -+* pReadBuff: pointer to the buffer to read the data in -+* buffSize: size of the buffer to read. -+* -+* OUTPUT: -+* pReadBuff: pointer to the buffer containing the read data -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashFastBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, -+ MV_U8* pReadBuff, MV_U32 buffSize) -+{ -+ MV_U8 cmd[MV_SFLASH_READ_CMND_LENGTH]; -+ MV_STATUS ret; -+ -+ /* check for NULL pointer */ -+ if ((pFlinfo == NULL) || (pReadBuff == NULL)) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* Set the SPI frequency to the MAX allowed for fast-read operations */ -+ mvOsPrintf("Setting freq to %d.\n",sflash[pFlinfo->index].spiMaxFastFreq); -+ if ((ret = mvSpiBaudRateSet(sflash[pFlinfo->index].spiMaxFastFreq)) != MV_OK) -+ { -+ mvOsPrintf("%s ERROR: Failed to set the SPI fast frequency!\n", __FUNCTION__); -+ return ret; -+ } -+ -+ cmd[0] = sflash[pFlinfo->index].opcdFSTRD; -+ cmd[1] = ((offset >> 16) & 0xFF); -+ cmd[2] = ((offset >> 8) & 0xFF); -+ cmd[3] = (offset & 0xFF); -+ -+ -+ ret = mvSpiWriteThenRead(cmd, MV_SFLASH_READ_CMND_LENGTH, pReadBuff, buffSize, -+ sflash[pFlinfo->index].spiFastRdDummyBytes); -+ -+ /* Reset the SPI frequency to the MAX allowed for the device for best performance */ -+ if ((ret = mvSpiBaudRateSet(sflash[pFlinfo->index].spiMaxFreq)) != MV_OK) -+ { -+ mvOsPrintf("%s ERROR: Failed to set the SPI frequency!\n", __FUNCTION__); -+ return ret; -+ } -+ -+ return ret; -+} -+ -+ -+/******************************************************************************* -+* mvSFlashBlockWr - Write a buffer with any size -+* -+* DESCRIPTION: -+* write regardless of the page boundaries and size limit per Page -+* program command -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* offset: byte offset within the flash region -+* pWriteBuff: pointer to the buffer holding the data to program -+* buffSize: size of the buffer to write -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashBlockWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, -+ MV_U8* pWriteBuff, MV_U32 buffSize) -+{ -+ MV_STATUS ret; -+ MV_U32 data2write = buffSize; -+ MV_U32 preAllOffset = (offset & MV_SFLASH_PAGE_ALLIGN_MASK(MV_M25P_PAGE_SIZE)); -+ MV_U32 preAllSz = (preAllOffset ? (MV_M25P_PAGE_SIZE - preAllOffset) : 0); -+ MV_U32 writeOffset = offset; -+ -+ /* check for NULL pointer */ -+#ifndef CONFIG_MARVELL -+ if(NULL == pWriteBuff) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+#endif -+ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* check that the buffer size does not exceed the flash size */ -+ if ((offset + buffSize) > mvSFlashSizeGet(pFlinfo)) -+ { -+ DB(mvOsPrintf("%s WARNING: Write exceeds flash size!\n", __FUNCTION__);) -+ return MV_OUT_OF_RANGE; -+ } -+ -+ /* check if the total block size is less than the first chunk remainder */ -+ if (data2write < preAllSz) -+ preAllSz = data2write; -+ -+ /* check if programing does not start at a 64byte alligned offset */ -+ if (preAllSz) -+ { -+ if ((ret = mvSFlashPageWr(pFlinfo, writeOffset, pWriteBuff, preAllSz)) != MV_OK) -+ return ret; -+ -+ /* increment pointers and counters */ -+ writeOffset += preAllSz; -+ data2write -= preAllSz; -+ pWriteBuff += preAllSz; -+ } -+ -+ /* program the data that fits in complete page chunks */ -+ while (data2write >= sflash[pFlinfo->index].pageSize) -+ { -+ if ((ret = mvSFlashPageWr(pFlinfo, writeOffset, pWriteBuff, sflash[pFlinfo->index].pageSize)) != MV_OK) -+ return ret; -+ -+ /* increment pointers and counters */ -+ writeOffset += sflash[pFlinfo->index].pageSize; -+ data2write -= sflash[pFlinfo->index].pageSize; -+ pWriteBuff += sflash[pFlinfo->index].pageSize; -+ } -+ -+ /* program the last partial chunk */ -+ if (data2write) -+ { -+ if ((ret = mvSFlashPageWr(pFlinfo, writeOffset, pWriteBuff, data2write)) != MV_OK) -+ return ret; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSFlashIdGet - Get the manufacturer and device IDs. -+* -+* DESCRIPTION: -+* Get the Manufacturer and device IDs from the serial flash through -+* writing the RDID command then reading 3 bytes of data. In case that -+* this command was called for the first time in order to detect the -+* manufacturer and device IDs, then the default RDID opcode will be used -+* unless the device index is indicated by the user (in case the SPI flash -+* does not use the default RDID opcode). -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* pManId: pointer to the 8bit variable to hold the manufacturing ID -+* pDevId: pointer to the 16bit variable to hold the device ID -+* -+* OUTPUT: -+* pManId: pointer to the 8bit variable holding the manufacturing ID -+* pDevId: pointer to the 16bit variable holding the device ID -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashIdGet (MV_SFLASH_INFO * pFlinfo, MV_U8* pManId, MV_U16* pDevId) -+{ -+ MV_STATUS ret; -+ MV_U8 cmd[MV_SFLASH_RDID_CMND_LENGTH]; -+ MV_U8 id[MV_SFLASH_RDID_REPLY_LENGTH]; -+ -+ -+ -+ /* check for NULL pointer */ -+ if ((pFlinfo == NULL) || (pManId == NULL) || (pDevId == NULL)) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ return mvSFlashWithDefaultsIdGet(pFlinfo, pManId, pDevId); -+ else -+ cmd[0] = sflash[pFlinfo->index].opcdRDID; -+ -+ if ((ret = mvSpiWriteThenRead(cmd, MV_SFLASH_RDID_CMND_LENGTH, id, MV_SFLASH_RDID_REPLY_LENGTH, 0)) != MV_OK) -+ return ret; -+ -+ *pManId = id[0]; -+ *pDevId = 0; -+ *pDevId |= (id[1] << 8); -+ *pDevId |= id[2]; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSFlashWpRegionSet - Set the Write-Protected region -+* -+* DESCRIPTION: -+* Set the Write-Protected region -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* wpRegion: which region will be protected -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashWpRegionSet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION wpRegion) -+{ -+ MV_U8 wpMask; -+ -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the chip is an ST flash; then WP supports only 3 bits */ -+ if (pFlinfo->manufacturerId == MV_M25PXXX_ST_MANF_ID) -+ { -+ switch (wpRegion) -+ { -+ case MV_WP_NONE: -+ wpMask = MV_M25P_STATUS_BP_NONE; -+ break; -+ -+ case MV_WP_UPR_1OF128: -+ DB(mvOsPrintf("%s WARNING: Invaild option for this flash chip!\n", __FUNCTION__);) -+ return MV_NOT_SUPPORTED; -+ -+ case MV_WP_UPR_1OF64: -+ wpMask = MV_M25P_STATUS_BP_1_OF_64; -+ break; -+ -+ case MV_WP_UPR_1OF32: -+ wpMask = MV_M25P_STATUS_BP_1_OF_32; -+ break; -+ -+ case MV_WP_UPR_1OF16: -+ wpMask = MV_M25P_STATUS_BP_1_OF_16; -+ break; -+ -+ case MV_WP_UPR_1OF8: -+ wpMask = MV_M25P_STATUS_BP_1_OF_8; -+ break; -+ -+ case MV_WP_UPR_1OF4: -+ wpMask = MV_M25P_STATUS_BP_1_OF_4; -+ break; -+ -+ case MV_WP_UPR_1OF2: -+ wpMask = MV_M25P_STATUS_BP_1_OF_2; -+ break; -+ -+ case MV_WP_ALL: -+ wpMask = MV_M25P_STATUS_BP_ALL; -+ break; -+ -+ default: -+ DB(mvOsPrintf("%s WARNING: Invaild parameter WP region!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ } -+ /* check if the manufacturer is MXIC then the WP is 4bits */ -+ else if (pFlinfo->manufacturerId == MV_MXIC_MANF_ID) -+ { -+ switch (wpRegion) -+ { -+ case MV_WP_NONE: -+ wpMask = MV_MX25L_STATUS_BP_NONE; -+ break; -+ -+ case MV_WP_UPR_1OF128: -+ wpMask = MV_MX25L_STATUS_BP_1_OF_128; -+ break; -+ -+ case MV_WP_UPR_1OF64: -+ wpMask = MV_MX25L_STATUS_BP_1_OF_64; -+ break; -+ -+ case MV_WP_UPR_1OF32: -+ wpMask = MV_MX25L_STATUS_BP_1_OF_32; -+ break; -+ -+ case MV_WP_UPR_1OF16: -+ wpMask = MV_MX25L_STATUS_BP_1_OF_16; -+ break; -+ -+ case MV_WP_UPR_1OF8: -+ wpMask = MV_MX25L_STATUS_BP_1_OF_8; -+ break; -+ -+ case MV_WP_UPR_1OF4: -+ wpMask = MV_MX25L_STATUS_BP_1_OF_4; -+ break; -+ -+ case MV_WP_UPR_1OF2: -+ wpMask = MV_MX25L_STATUS_BP_1_OF_2; -+ break; -+ -+ case MV_WP_ALL: -+ wpMask = MV_MX25L_STATUS_BP_ALL; -+ break; -+ -+ default: -+ DB(mvOsPrintf("%s WARNING: Invaild parameter WP region!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ } -+ /* check if the manufacturer is SPANSION then the WP is 4bits */ -+ else if (pFlinfo->manufacturerId == MV_SPANSION_MANF_ID) -+ { -+ switch (wpRegion) -+ { -+ case MV_WP_NONE: -+ wpMask = MV_S25FL_STATUS_BP_NONE; -+ break; -+ -+ case MV_WP_UPR_1OF128: -+ DB(mvOsPrintf("%s WARNING: Invaild option for this flash chip!\n", __FUNCTION__);) -+ return MV_NOT_SUPPORTED; -+ -+ case MV_WP_UPR_1OF64: -+ wpMask = MV_S25FL_STATUS_BP_1_OF_64; -+ break; -+ -+ case MV_WP_UPR_1OF32: -+ wpMask = MV_S25FL_STATUS_BP_1_OF_32; -+ break; -+ -+ case MV_WP_UPR_1OF16: -+ wpMask = MV_S25FL_STATUS_BP_1_OF_16; -+ break; -+ -+ case MV_WP_UPR_1OF8: -+ wpMask = MV_S25FL_STATUS_BP_1_OF_8; -+ break; -+ -+ case MV_WP_UPR_1OF4: -+ wpMask = MV_S25FL_STATUS_BP_1_OF_4; -+ break; -+ -+ case MV_WP_UPR_1OF2: -+ wpMask = MV_S25FL_STATUS_BP_1_OF_2; -+ break; -+ -+ case MV_WP_ALL: -+ wpMask = MV_S25FL_STATUS_BP_ALL; -+ break; -+ -+ -+ default: -+ DB(mvOsPrintf("%s WARNING: Invaild parameter WP region!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ } -+ else -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter Manufacturer ID!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* Verify that the SRWD bit is always set - register is s/w locked */ -+ wpMask |= MV_SFLASH_STATUS_REG_SRWD_MASK; -+ -+ return mvStatusRegSet(pFlinfo, wpMask); -+} -+ -+/******************************************************************************* -+* mvSFlashWpRegionGet - Get the Write-Protected region configured -+* -+* DESCRIPTION: -+* Get from the chip the Write-Protected region configured -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* pWpRegion: pointer to the variable to return the WP region in -+* -+* OUTPUT: -+* wpRegion: pointer to the variable holding the WP region configured -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashWpRegionGet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION * pWpRegion) -+{ -+ MV_STATUS ret; -+ MV_U8 reg; -+ -+ /* check for NULL pointer */ -+ if ((pFlinfo == NULL) || (pWpRegion == NULL)) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ if ((ret = mvStatusRegGet(pFlinfo, ®)) != MV_OK) -+ return ret; -+ -+ /* Check if the chip is an ST flash; then WP supports only 3 bits */ -+ if (pFlinfo->manufacturerId == MV_M25PXXX_ST_MANF_ID) -+ { -+ switch ((reg & MV_M25P_STATUS_REG_WP_MASK)) -+ { -+ case MV_M25P_STATUS_BP_NONE: -+ *pWpRegion = MV_WP_NONE; -+ break; -+ -+ case MV_M25P_STATUS_BP_1_OF_64: -+ *pWpRegion = MV_WP_UPR_1OF64; -+ break; -+ -+ case MV_M25P_STATUS_BP_1_OF_32: -+ *pWpRegion = MV_WP_UPR_1OF32; -+ break; -+ -+ case MV_M25P_STATUS_BP_1_OF_16: -+ *pWpRegion = MV_WP_UPR_1OF16; -+ break; -+ -+ case MV_M25P_STATUS_BP_1_OF_8: -+ *pWpRegion = MV_WP_UPR_1OF8; -+ break; -+ -+ case MV_M25P_STATUS_BP_1_OF_4: -+ *pWpRegion = MV_WP_UPR_1OF4; -+ break; -+ -+ case MV_M25P_STATUS_BP_1_OF_2: -+ *pWpRegion = MV_WP_UPR_1OF2; -+ break; -+ -+ case MV_M25P_STATUS_BP_ALL: -+ *pWpRegion = MV_WP_ALL; -+ break; -+ -+ default: -+ DB(mvOsPrintf("%s WARNING: Unidentified WP region in h/w!\n", __FUNCTION__);) -+ return MV_BAD_VALUE; -+ } -+ } -+ /* check if the manufacturer is MXIC then the WP is 4bits */ -+ else if (pFlinfo->manufacturerId == MV_MXIC_MANF_ID) -+ { -+ switch ((reg & MV_MX25L_STATUS_REG_WP_MASK)) -+ { -+ case MV_MX25L_STATUS_BP_NONE: -+ *pWpRegion = MV_WP_NONE; -+ break; -+ -+ case MV_MX25L_STATUS_BP_1_OF_128: -+ *pWpRegion = MV_WP_UPR_1OF128; -+ break; -+ -+ case MV_MX25L_STATUS_BP_1_OF_64: -+ *pWpRegion = MV_WP_UPR_1OF64; -+ break; -+ -+ case MV_MX25L_STATUS_BP_1_OF_32: -+ *pWpRegion = MV_WP_UPR_1OF32; -+ break; -+ -+ case MV_MX25L_STATUS_BP_1_OF_16: -+ *pWpRegion = MV_WP_UPR_1OF16; -+ break; -+ -+ case MV_MX25L_STATUS_BP_1_OF_8: -+ *pWpRegion = MV_WP_UPR_1OF8; -+ break; -+ -+ case MV_MX25L_STATUS_BP_1_OF_4: -+ *pWpRegion = MV_WP_UPR_1OF4; -+ break; -+ -+ case MV_MX25L_STATUS_BP_1_OF_2: -+ *pWpRegion = MV_WP_UPR_1OF2; -+ break; -+ -+ case MV_MX25L_STATUS_BP_ALL: -+ *pWpRegion = MV_WP_ALL; -+ break; -+ -+ default: -+ DB(mvOsPrintf("%s WARNING: Unidentified WP region in h/w!\n", __FUNCTION__);) -+ return MV_BAD_VALUE; -+ } -+ } -+ /* Check if the chip is an SPANSION flash; then WP supports only 3 bits */ -+ else if (pFlinfo->manufacturerId == MV_SPANSION_MANF_ID) -+ { -+ switch ((reg & MV_S25FL_STATUS_REG_WP_MASK)) -+ { -+ case MV_S25FL_STATUS_BP_NONE: -+ *pWpRegion = MV_WP_NONE; -+ break; -+ -+ case MV_S25FL_STATUS_BP_1_OF_64: -+ *pWpRegion = MV_WP_UPR_1OF64; -+ break; -+ -+ case MV_S25FL_STATUS_BP_1_OF_32: -+ *pWpRegion = MV_WP_UPR_1OF32; -+ break; -+ -+ case MV_S25FL_STATUS_BP_1_OF_16: -+ *pWpRegion = MV_WP_UPR_1OF16; -+ break; -+ -+ case MV_S25FL_STATUS_BP_1_OF_8: -+ *pWpRegion = MV_WP_UPR_1OF8; -+ break; -+ -+ case MV_S25FL_STATUS_BP_1_OF_4: -+ *pWpRegion = MV_WP_UPR_1OF4; -+ break; -+ -+ case MV_S25FL_STATUS_BP_1_OF_2: -+ *pWpRegion = MV_WP_UPR_1OF2; -+ break; -+ -+ case MV_S25FL_STATUS_BP_ALL: -+ *pWpRegion = MV_WP_ALL; -+ break; -+ -+ default: -+ DB(mvOsPrintf("%s WARNING: Unidentified WP region in h/w!\n", __FUNCTION__);) -+ return MV_BAD_VALUE; -+ } -+ } -+ else -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter Manufacturer ID!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSFlashStatRegLock - Lock the status register for writing - W/Vpp -+* pin should be low to take effect -+* -+* DESCRIPTION: -+* Lock the access to the Status Register for writing. This will -+* cause the flash to enter the hardware protection mode if the W/Vpp -+* is low. If the W/Vpp is hi, the chip will be in soft protection mode, but -+* the register will continue to be writable if WREN sequence was used. -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* srLock: enable/disable (MV_TRUE/MV_FALSE) status registor lock mechanism -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashStatRegLock (MV_SFLASH_INFO * pFlinfo, MV_BOOL srLock) -+{ -+ MV_STATUS ret; -+ MV_U8 reg; -+ -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ if ((ret = mvStatusRegGet(pFlinfo, ®)) != MV_OK) -+ return ret; -+ -+ if (srLock) -+ reg |= MV_SFLASH_STATUS_REG_SRWD_MASK; -+ else -+ reg &= ~MV_SFLASH_STATUS_REG_SRWD_MASK; -+ -+ return mvStatusRegSet(pFlinfo, reg); -+} -+ -+/******************************************************************************* -+* mvSFlashSizeGet - Get the size of the SPI flash -+* -+* DESCRIPTION: -+* based on the sector number and size of each sector calculate the total -+* size of the flash memory. -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Size of the flash in bytes. -+* -+* -+*******************************************************************************/ -+MV_U32 mvSFlashSizeGet (MV_SFLASH_INFO * pFlinfo) -+{ -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return 0; -+ } -+ -+ return (pFlinfo->sectorSize * pFlinfo->sectorNumber); -+} -+ -+/******************************************************************************* -+* mvSFlashPowerSaveEnter - Cause the falsh device to go into power save mode -+* -+* DESCRIPTION: -+* Enter a special power save mode. -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Size of the flash in bytes. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashPowerSaveEnter(MV_SFLASH_INFO * pFlinfo) -+{ -+ MV_STATUS ret; -+ MV_U8 cmd[MV_SFLASH_DP_CMND_LENGTH]; -+ -+ -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return 0; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* check that power save mode is supported in the specific device */ -+ if (sflash[pFlinfo->index].opcdPwrSave == MV_SFLASH_NO_SPECIFIC_OPCD) -+ { -+ DB(mvOsPrintf("%s WARNING: Power save not supported for this device!\n", __FUNCTION__);) -+ return MV_NOT_SUPPORTED; -+ } -+ -+ cmd[0] = sflash[pFlinfo->index].opcdPwrSave; -+ -+ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_DP_CMND_LENGTH, NULL, 0)) != MV_OK) -+ return ret; -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvSFlashPowerSaveExit - Cause the falsh device to exit the power save mode -+* -+* DESCRIPTION: -+* Exit the deep power save mode. -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Size of the flash in bytes. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashPowerSaveExit (MV_SFLASH_INFO * pFlinfo) -+{ -+ MV_STATUS ret; -+ MV_U8 cmd[MV_SFLASH_RES_CMND_LENGTH]; -+ -+ -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return 0; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* check that power save mode is supported in the specific device */ -+ if (sflash[pFlinfo->index].opcdRES == MV_SFLASH_NO_SPECIFIC_OPCD) -+ { -+ DB(mvOsPrintf("%s WARNING: Read Electronic Signature not supported for this device!\n", __FUNCTION__);) -+ return MV_NOT_SUPPORTED; -+ } -+ -+ cmd[0] = sflash[pFlinfo->index].opcdRES; -+ -+ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_RES_CMND_LENGTH, NULL, 0)) != MV_OK) -+ return ret; -+ -+ /* add the delay needed for the device to wake up */ -+ mvOsDelay(MV_MXIC_DP_EXIT_DELAY); /* 30 ms */ -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvSFlashModelGet - Retreive the string with the device manufacturer and model -+* -+* DESCRIPTION: -+* Retreive the string with the device manufacturer and model -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* pointer to the string indicating the device manufacturer and model -+* -+* -+*******************************************************************************/ -+const MV_8 * mvSFlashModelGet (MV_SFLASH_INFO * pFlinfo) -+{ -+ static const MV_8 * unknModel = (const MV_8 *)"Unknown"; -+ -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return 0; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return unknModel; -+ } -+ -+ return sflash[pFlinfo->index].deviceModel; -+} -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,166 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvSFlashH -+#define __INCmvSFlashH -+ -+#include "mvTypes.h" -+ -+/* MCAROS */ -+#define MV_SFLASH_PAGE_ALLIGN_MASK(pgSz) (pgSz-1) -+#define MV_ARRAY_SIZE(a) ((sizeof(a)) / (sizeof(a[0]))) -+ -+/* Constants */ -+#define MV_INVALID_DEVICE_NUMBER 0xFFFFFFFF -+/* 10 MHz is the minimum possible SPI frequency when tclk is set 200MHz*/ -+#define MV_SFLASH_BASIC_SPI_FREQ 10000000 -+/* enumerations */ -+typedef enum -+{ -+ MV_WP_NONE, /* Unprotect the whole chip */ -+ MV_WP_UPR_1OF128, /* Write protect the upper 1/128 part */ -+ MV_WP_UPR_1OF64, /* Write protect the upper 1/64 part */ -+ MV_WP_UPR_1OF32, /* Write protect the upper 1/32 part */ -+ MV_WP_UPR_1OF16, /* Write protect the upper 1/16 part */ -+ MV_WP_UPR_1OF8, /* Write protect the upper 1/8 part */ -+ MV_WP_UPR_1OF4, /* Write protect the upper 1/4 part */ -+ MV_WP_UPR_1OF2, /* Write protect the upper 1/2 part */ -+ MV_WP_ALL /* Write protect the whole chip */ -+} MV_SFLASH_WP_REGION; -+ -+/* Type Definitions */ -+typedef struct -+{ -+ MV_U8 opcdWREN; /* Write enable opcode */ -+ MV_U8 opcdWRDI; /* Write disable opcode */ -+ MV_U8 opcdRDID; /* Read ID opcode */ -+ MV_U8 opcdRDSR; /* Read Status Register opcode */ -+ MV_U8 opcdWRSR; /* Write Status register opcode */ -+ MV_U8 opcdREAD; /* Read opcode */ -+ MV_U8 opcdFSTRD; /* Fast Read opcode */ -+ MV_U8 opcdPP; /* Page program opcode */ -+ MV_U8 opcdSE; /* Sector erase opcode */ -+ MV_U8 opcdBE; /* Bulk erase opcode */ -+ MV_U8 opcdRES; /* Read electronic signature */ -+ MV_U8 opcdPwrSave; /* Go into power save mode */ -+ MV_U32 sectorSize; /* Size of each sector */ -+ MV_U32 sectorNumber; /* Number of sectors */ -+ MV_U32 pageSize; /* size of each page */ -+ const char * deviceModel; /* string with the device model */ -+ MV_U32 manufacturerId; /* The manufacturer ID */ -+ MV_U32 deviceId; /* Device ID */ -+ MV_U32 spiMaxFreq; /* The MAX frequency that can be used with the device */ -+ MV_U32 spiMaxFastFreq; /* The MAX frequency that can be used with the device for fast reads */ -+ MV_U32 spiFastRdDummyBytes; /* Number of dumy bytes to read before real data when working in fast read mode. */ -+} MV_SFLASH_DEVICE_PARAMS; -+ -+typedef struct -+{ -+ MV_U32 baseAddr; /* Flash Base Address used in fast mode */ -+ MV_U8 manufacturerId; /* Manufacturer ID */ -+ MV_U16 deviceId; /* Device ID */ -+ MV_U32 sectorSize; /* Size of each sector - all the same */ -+ MV_U32 sectorNumber; /* Number of sectors */ -+ MV_U32 pageSize; /* Page size - affect allignment */ -+ MV_U32 index; /* index of the device in the sflash table (internal parameter) */ -+} MV_SFLASH_INFO; -+ -+/* Function Prototypes */ -+/* Init */ -+MV_STATUS mvSFlashInit (MV_SFLASH_INFO * pFlinfo); -+ -+/* erase */ -+MV_STATUS mvSFlashSectorErase (MV_SFLASH_INFO * pFlinfo, MV_U32 secNumber); -+MV_STATUS mvSFlashChipErase (MV_SFLASH_INFO * pFlinfo); -+ -+/* Read */ -+MV_STATUS mvSFlashBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, -+ MV_U8* pReadBuff, MV_U32 buffSize); -+MV_STATUS mvSFlashFastBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, -+ MV_U8* pReadBuff, MV_U32 buffSize); -+ -+/* write regardless of the page boundaries and size limit per Page program command */ -+MV_STATUS mvSFlashBlockWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, -+ MV_U8* pWriteBuff, MV_U32 buffSize); -+/* Get IDs */ -+MV_STATUS mvSFlashIdGet (MV_SFLASH_INFO * pFlinfo, MV_U8* pManId, MV_U16* pDevId); -+ -+/* Set and Get the Write Protection region - if the Status register is not locked */ -+MV_STATUS mvSFlashWpRegionSet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION wpRegion); -+MV_STATUS mvSFlashWpRegionGet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION * pWpRegion); -+ -+/* Lock the status register for writing - W/Vpp pin should be low to take effect */ -+MV_STATUS mvSFlashStatRegLock (MV_SFLASH_INFO * pFlinfo, MV_BOOL srLock); -+ -+/* Get the regions sizes */ -+MV_U32 mvSFlashSizeGet (MV_SFLASH_INFO * pFlinfo); -+ -+/* Cause the falsh device to go into power save mode */ -+MV_STATUS mvSFlashPowerSaveEnter(MV_SFLASH_INFO * pFlinfo); -+MV_STATUS mvSFlashPowerSaveExit (MV_SFLASH_INFO * pFlinfo); -+ -+/* Retreive the string with the device manufacturer and model */ -+const MV_8 * mvSFlashModelGet (MV_SFLASH_INFO * pFlinfo); -+ -+#endif /* __INCmvSFlashH */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlashSpec.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlashSpec.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlashSpec.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlashSpec.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,233 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvSFlashSpecH -+#define __INCmvSFlashSpecH -+ -+/* Constants */ -+#define MV_SFLASH_READ_CMND_LENGTH 4 /* 1B opcode + 3B address */ -+#define MV_SFLASH_SE_CMND_LENGTH 4 /* 1B opcode + 3B address */ -+#define MV_SFLASH_BE_CMND_LENGTH 1 /* 1B opcode */ -+#define MV_SFLASH_PP_CMND_LENGTH 4 /* 1B opcode + 3B address */ -+#define MV_SFLASH_WREN_CMND_LENGTH 1 /* 1B opcode */ -+#define MV_SFLASH_WRDI_CMND_LENGTH 1 /* 1B opcode */ -+#define MV_SFLASH_RDID_CMND_LENGTH 1 /* 1B opcode */ -+#define MV_SFLASH_RDID_REPLY_LENGTH 3 /* 1B manf ID and 2B device ID */ -+#define MV_SFLASH_RDSR_CMND_LENGTH 1 /* 1B opcode */ -+#define MV_SFLASH_RDSR_REPLY_LENGTH 1 /* 1B status */ -+#define MV_SFLASH_WRSR_CMND_LENGTH 2 /* 1B opcode + 1B status value */ -+#define MV_SFLASH_DP_CMND_LENGTH 1 /* 1B opcode */ -+#define MV_SFLASH_RES_CMND_LENGTH 1 /* 1B opcode */ -+ -+/* Status Register Bit Masks */ -+#define MV_SFLASH_STATUS_REG_WIP_OFFSET 0 /* bit 0; write in progress */ -+#define MV_SFLASH_STATUS_REG_WP_OFFSET 2 /* bit 2-4; write protect option */ -+#define MV_SFLASH_STATUS_REG_SRWD_OFFSET 7 /* bit 7; lock status register write */ -+#define MV_SFLASH_STATUS_REG_WIP_MASK (0x1 << MV_SFLASH_STATUS_REG_WIP_OFFSET) -+#define MV_SFLASH_STATUS_REG_SRWD_MASK (0x1 << MV_SFLASH_STATUS_REG_SRWD_OFFSET) -+ -+#define MV_SFLASH_MAX_WAIT_LOOP 1000000 -+#define MV_SFLASH_CHIP_ERASE_MAX_WAIT_LOOP 0x50000000 -+ -+#define MV_SFLASH_DEFAULT_RDID_OPCD 0x9F /* Default Read ID */ -+#define MV_SFLASH_DEFAULT_WREN_OPCD 0x06 /* Default Write Enable */ -+#define MV_SFLASH_NO_SPECIFIC_OPCD 0x00 -+ -+/********************************/ -+/* ST M25Pxxx Device Specific */ -+/********************************/ -+ -+/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ -+#define MV_M25PXXX_ST_MANF_ID 0x20 -+#define MV_M25P32_DEVICE_ID 0x2016 -+#define MV_M25P32_MAX_SPI_FREQ 20000000 /* 20MHz */ -+#define MV_M25P32_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ -+#define MV_M25P32_FAST_READ_DUMMY_BYTES 1 -+#define MV_M25P64_DEVICE_ID 0x2017 -+#define MV_M25P64_MAX_SPI_FREQ 20000000 /* 20MHz */ -+#define MV_M25P64_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ -+#define MV_M25P64_FAST_READ_DUMMY_BYTES 1 -+#define MV_M25P128_DEVICE_ID 0x2018 -+#define MV_M25P128_MAX_SPI_FREQ 20000000 /* 20MHz */ -+#define MV_M25P128_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ -+#define MV_M25P128_FAST_READ_DUMMY_BYTES 1 -+ -+ -+/* Sector Sizes and population per device model*/ -+#define MV_M25P32_SECTOR_SIZE 0x10000 /* 64K */ -+#define MV_M25P64_SECTOR_SIZE 0x10000 /* 64K */ -+#define MV_M25P128_SECTOR_SIZE 0x40000 /* 256K */ -+#define MV_M25P32_SECTOR_NUMBER 64 -+#define MV_M25P64_SECTOR_NUMBER 128 -+#define MV_M25P128_SECTOR_NUMBER 64 -+#define MV_M25P_PAGE_SIZE 0x100 /* 256 byte */ -+ -+#define MV_M25P_WREN_CMND_OPCD 0x06 /* Write Enable */ -+#define MV_M25P_WRDI_CMND_OPCD 0x04 /* Write Disable */ -+#define MV_M25P_RDID_CMND_OPCD 0x9F /* Read ID */ -+#define MV_M25P_RDSR_CMND_OPCD 0x05 /* Read Status Register */ -+#define MV_M25P_WRSR_CMND_OPCD 0x01 /* Write Status Register */ -+#define MV_M25P_READ_CMND_OPCD 0x03 /* Sequential Read */ -+#define MV_M25P_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ -+#define MV_M25P_PP_CMND_OPCD 0x02 /* Page Program */ -+#define MV_M25P_SE_CMND_OPCD 0xD8 /* Sector Erase */ -+#define MV_M25P_BE_CMND_OPCD 0xC7 /* Bulk Erase */ -+#define MV_M25P_RES_CMND_OPCD 0xAB /* Read Electronic Signature */ -+ -+/* Status Register Write Protect Bit Masks - 3bits */ -+#define MV_M25P_STATUS_REG_WP_MASK (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_M25P_STATUS_BP_NONE (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_M25P_STATUS_BP_1_OF_64 (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_M25P_STATUS_BP_1_OF_32 (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_M25P_STATUS_BP_1_OF_16 (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_M25P_STATUS_BP_1_OF_8 (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_M25P_STATUS_BP_1_OF_4 (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_M25P_STATUS_BP_1_OF_2 (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_M25P_STATUS_BP_ALL (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+ -+/************************************/ -+/* MXIC MX25L6405 Device Specific */ -+/************************************/ -+ -+/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ -+#define MV_MXIC_MANF_ID 0xC2 -+#define MV_MX25L6405_DEVICE_ID 0x2017 -+#define MV_MX25L6405_MAX_SPI_FREQ 20000000 /* 20MHz */ -+#define MV_MX25L6405_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ -+#define MV_MX25L6405_FAST_READ_DUMMY_BYTES 1 -+#define MV_MXIC_DP_EXIT_DELAY 30 /* 30 ms */ -+ -+/* Sector Sizes and population per device model*/ -+#define MV_MX25L6405_SECTOR_SIZE 0x10000 /* 64K */ -+#define MV_MX25L6405_SECTOR_NUMBER 128 -+#define MV_MXIC_PAGE_SIZE 0x100 /* 256 byte */ -+ -+#define MV_MX25L_WREN_CMND_OPCD 0x06 /* Write Enable */ -+#define MV_MX25L_WRDI_CMND_OPCD 0x04 /* Write Disable */ -+#define MV_MX25L_RDID_CMND_OPCD 0x9F /* Read ID */ -+#define MV_MX25L_RDSR_CMND_OPCD 0x05 /* Read Status Register */ -+#define MV_MX25L_WRSR_CMND_OPCD 0x01 /* Write Status Register */ -+#define MV_MX25L_READ_CMND_OPCD 0x03 /* Sequential Read */ -+#define MV_MX25L_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ -+#define MV_MX25L_PP_CMND_OPCD 0x02 /* Page Program */ -+#define MV_MX25L_SE_CMND_OPCD 0xD8 /* Sector Erase */ -+#define MV_MX25L_BE_CMND_OPCD 0xC7 /* Bulk Erase */ -+#define MV_MX25L_DP_CMND_OPCD 0xB9 /* Deep Power Down */ -+#define MV_MX25L_RES_CMND_OPCD 0xAB /* Read Electronic Signature */ -+ -+/* Status Register Write Protect Bit Masks - 4bits */ -+#define MV_MX25L_STATUS_REG_WP_MASK (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_NONE (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_1_OF_128 (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_1_OF_64 (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_1_OF_32 (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_1_OF_16 (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_1_OF_8 (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_1_OF_4 (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_1_OF_2 (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_ALL (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) -+ -+/************************************/ -+/* SPANSION S25FL128P Device Specific */ -+/************************************/ -+ -+/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ -+#define MV_SPANSION_MANF_ID 0x01 -+#define MV_S25FL128_DEVICE_ID 0x2018 -+#define MV_S25FL128_MAX_SPI_FREQ 33000000 /* 33MHz */ -+#define MV_S25FL128_MAX_FAST_SPI_FREQ 104000000 /* 104MHz */ -+#define MV_S25FL128_FAST_READ_DUMMY_BYTES 1 -+ -+/* Sector Sizes and population per device model*/ -+#define MV_S25FL128_SECTOR_SIZE 0x40000 /* 256K */ -+#define MV_S25FL128_SECTOR_NUMBER 64 -+#define MV_S25FL_PAGE_SIZE 0x100 /* 256 byte */ -+ -+#define MV_S25FL_WREN_CMND_OPCD 0x06 /* Write Enable */ -+#define MV_S25FL_WRDI_CMND_OPCD 0x04 /* Write Disable */ -+#define MV_S25FL_RDID_CMND_OPCD 0x9F /* Read ID */ -+#define MV_S25FL_RDSR_CMND_OPCD 0x05 /* Read Status Register */ -+#define MV_S25FL_WRSR_CMND_OPCD 0x01 /* Write Status Register */ -+#define MV_S25FL_READ_CMND_OPCD 0x03 /* Sequential Read */ -+#define MV_S25FL_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ -+#define MV_S25FL_PP_CMND_OPCD 0x02 /* Page Program */ -+#define MV_S25FL_SE_CMND_OPCD 0xD8 /* Sector Erase */ -+#define MV_S25FL_BE_CMND_OPCD 0xC7 /* Bulk Erase */ -+#define MV_S25FL_DP_CMND_OPCD 0xB9 /* Deep Power Down */ -+#define MV_S25FL_RES_CMND_OPCD 0xAB /* Read Electronic Signature */ -+ -+/* Status Register Write Protect Bit Masks - 4bits */ -+#define MV_S25FL_STATUS_REG_WP_MASK (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_NONE (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_1_OF_128 (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_1_OF_64 (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_1_OF_32 (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_1_OF_16 (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_1_OF_8 (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_1_OF_4 (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_1_OF_2 (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_ALL (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) -+ -+#endif /* __INCmvSFlashSpecH */ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvCompVer.txt linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvCompVer.txt ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvCompVer.txt 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvCompVer.txt 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,4 @@ -+Global HAL Version: FEROCEON_HAL_3_1_7 -+Unit HAL Version: 3.1.3 -+Description: This component includes an implementation of the unit HAL drivers -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,576 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "spi/mvSpi.h" -+#include "spi/mvSpiSpec.h" -+ -+#include "ctrlEnv/mvCtrlEnvLib.h" -+ -+/* #define MV_DEBUG */ -+#ifdef MV_DEBUG -+#define DB(x) x -+#define mvOsPrintf printf -+#else -+#define DB(x) -+#endif -+ -+ -+/******************************************************************************* -+* mvSpi16bitDataTxRx - Transmt and receive data -+* -+* DESCRIPTION: -+* Tx data and block waiting for data to be transmitted -+* -+********************************************************************************/ -+static MV_STATUS mvSpi16bitDataTxRx (MV_U16 txData, MV_U16 * pRxData) -+{ -+ MV_U32 i; -+ MV_BOOL ready = MV_FALSE; -+ -+ /* First clear the bit in the interrupt cause register */ -+ MV_REG_WRITE(MV_SPI_INT_CAUSE_REG, 0x0); -+ -+ /* Transmit data */ -+ MV_REG_WRITE(MV_SPI_DATA_OUT_REG, MV_16BIT_LE(txData)); -+ -+ /* wait with timeout for memory ready */ -+ for (i=0; i> 8) & 0xFF); -+ -+#elif defined(MV_CPU_BE) -+ -+ /* perform the data write to the buffer in two stages with 8bit each */ -+ MV_U8 * bptr = (MV_U8 *)pRxData; -+ MV_U16 data = MV_16BIT_LE(MV_REG_READ(MV_SPI_DATA_IN_REG)); -+ *bptr = ((data >> 8) & 0xFF); -+ ++bptr; -+ *bptr = (data & 0xFF); -+ -+#else -+ #error "CPU endianess isn't defined!\n" -+#endif -+ -+ } -+ else -+ *pRxData = MV_16BIT_LE(MV_REG_READ(MV_SPI_DATA_IN_REG)); -+ } -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvSpi8bitDataTxRx - Transmt and receive data (8bits) -+* -+* DESCRIPTION: -+* Tx data and block waiting for data to be transmitted -+* -+********************************************************************************/ -+static MV_STATUS mvSpi8bitDataTxRx (MV_U8 txData, MV_U8 * pRxData) -+{ -+ MV_U32 i; -+ MV_BOOL ready = MV_FALSE; -+ -+ /* First clear the bit in the interrupt cause register */ -+ MV_REG_WRITE(MV_SPI_INT_CAUSE_REG, 0x0); -+ -+ /* Transmit data */ -+ MV_REG_WRITE(MV_SPI_DATA_OUT_REG, txData); -+ -+ /* wait with timeout for memory ready */ -+ for (i=0; i serialBaudRate) -+ continue; -+ -+ /* check for exact fit */ -+ if ((cpuClk / preScale[i]) == serialBaudRate) -+ { -+ bestPrescaleIndx = i; -+ break; -+ } -+ -+ /* check if this is better than the previous one */ -+ if ((serialBaudRate - (cpuClk / preScale[i])) < minBaudOffset) -+ { -+ minBaudOffset = (serialBaudRate - (cpuClk / preScale[i])); -+ bestPrescaleIndx = i; -+ } -+ } -+ -+ if (bestPrescaleIndx > 14) -+ { -+ mvOsPrintf("%s ERROR: SPI baud rate prescale error!\n", __FUNCTION__); -+ return MV_OUT_OF_RANGE; -+ } -+ -+ /* configure the Prescale */ -+ tempReg = MV_REG_READ(MV_SPI_IF_CONFIG_REG); -+ tempReg = ((tempReg & ~MV_SPI_CLK_PRESCALE_MASK) | (bestPrescaleIndx + 0x12)); -+ MV_REG_WRITE(MV_SPI_IF_CONFIG_REG, tempReg); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSpiCsAssert - Assert the Chip Select pin indicating a new transfer -+* -+* DESCRIPTION: -+* Assert The chip select - used to select an external SPI device -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Success or Error code. -+* -+********************************************************************************/ -+MV_VOID mvSpiCsAssert(MV_VOID) -+{ -+ /* For devices in which the SPI is muxed on the MPP with other interfaces*/ -+ mvMPPConfigToSPI(); -+ mvOsUDelay(1); -+ MV_REG_BIT_SET(MV_SPI_IF_CTRL_REG, MV_SPI_CS_ENABLE_MASK); -+} -+ -+/******************************************************************************* -+* mvSpiCsDeassert - DeAssert the Chip Select pin indicating the end of a -+* SPI transfer sequence -+* -+* DESCRIPTION: -+* DeAssert the chip select pin -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Success or Error code. -+* -+********************************************************************************/ -+MV_VOID mvSpiCsDeassert(MV_VOID) -+{ -+ MV_REG_BIT_RESET(MV_SPI_IF_CTRL_REG, MV_SPI_CS_ENABLE_MASK); -+ -+ /* For devices in which the SPI is muxed on the MPP with other interfaces*/ -+ mvMPPConfigToDefault(); -+} -+ -+/******************************************************************************* -+* mvSpiRead - Read a buffer over the SPI interface -+* -+* DESCRIPTION: -+* Receive (read) a buffer over the SPI interface in 16bit chunks. If the -+* buffer size is odd, then the last chunk will be 8bits. Chip select is not -+* handled at this level. -+* -+* INPUT: -+* pRxBuff: Pointer to the buffer to hold the received data -+* buffSize: length of the pRxBuff -+* -+* OUTPUT: -+* pRxBuff: Pointer to the buffer with the received data -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSpiRead (MV_U8* pRxBuff, MV_U32 buffSize) -+{ -+ MV_STATUS ret; -+ MV_U32 bytesLeft = buffSize; -+ MV_U16* rxPtr = (MV_U16*)pRxBuff; -+ -+ /* check for null parameters */ -+ if (pRxBuff == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check that the buffer pointer and the buffer size are 16bit aligned */ -+ if ((((MV_U32)buffSize & 1) == 0) && (((MV_U32)pRxBuff & 1) == 0)) -+ { -+ /* Verify that the SPI mode is in 16bit mode */ -+ MV_REG_BIT_SET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); -+ -+ /* TX/RX as long we have complete 16bit chunks */ -+ while (bytesLeft >= MV_SPI_16_BIT_CHUNK_SIZE) -+ { -+ /* Transmitted and wait for the transfer to be completed */ -+ if ((ret = mvSpi16bitDataTxRx(MV_SPI_DUMMY_WRITE_16BITS, rxPtr)) != MV_OK) -+ return ret; -+ -+ /* increment the pointers */ -+ rxPtr++; -+ bytesLeft -= MV_SPI_16_BIT_CHUNK_SIZE; -+ } -+ -+ } -+ else -+ { -+ /* Verify that the SPI mode is in 8bit mode */ -+ MV_REG_BIT_RESET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); -+ -+ /* TX/RX in 8bit chanks */ -+ while (bytesLeft > 0) -+ { -+ /* Transmitted and wait for the transfer to be completed */ -+ if ((ret = mvSpi8bitDataTxRx(MV_SPI_DUMMY_WRITE_8BITS, pRxBuff)) != MV_OK) -+ return ret; -+ /* increment the pointers */ -+ pRxBuff++; -+ bytesLeft--; -+ } -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSpiWrite - Transmit a buffer over the SPI interface -+* -+* DESCRIPTION: -+* Transmit a buffer over the SPI interface in 16bit chunks. If the -+* buffer size is odd, then the last chunk will be 8bits. No chip select -+* action is taken. -+* -+* INPUT: -+* pTxBuff: Pointer to the buffer holding the TX data -+* buffSize: length of the pTxBuff -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSpiWrite(MV_U8* pTxBuff, MV_U32 buffSize) -+{ -+ MV_STATUS ret; -+ MV_U32 bytesLeft = buffSize; -+ MV_U16* txPtr = (MV_U16*)pTxBuff; -+ -+ /* check for null parameters */ -+ if (pTxBuff == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check that the buffer pointer and the buffer size are 16bit aligned */ -+ if ((((MV_U32)buffSize & 1) == 0) && (((MV_U32)pTxBuff & 1) == 0)) -+ { -+ /* Verify that the SPI mode is in 16bit mode */ -+ MV_REG_BIT_SET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); -+ -+ /* TX/RX as long we have complete 16bit chunks */ -+ while (bytesLeft >= MV_SPI_16_BIT_CHUNK_SIZE) -+ { -+ /* Transmitted and wait for the transfer to be completed */ -+ if ((ret = mvSpi16bitDataTxRx(*txPtr, NULL)) != MV_OK) -+ return ret; -+ -+ /* increment the pointers */ -+ txPtr++; -+ bytesLeft -= MV_SPI_16_BIT_CHUNK_SIZE; -+ } -+ } -+ else -+ { -+ -+ /* Verify that the SPI mode is in 8bit mode */ -+ MV_REG_BIT_RESET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); -+ -+ /* TX/RX in 8bit chanks */ -+ while (bytesLeft > 0) -+ { -+ /* Transmitted and wait for the transfer to be completed */ -+ if ((ret = mvSpi8bitDataTxRx(*pTxBuff, NULL)) != MV_OK) -+ return ret; -+ -+ /* increment the pointers */ -+ pTxBuff++; -+ bytesLeft--; -+ } -+ } -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvSpiReadWrite - Read and Write a buffer simultanuosely -+* -+* DESCRIPTION: -+* Transmit and receive a buffer over the SPI in 16bit chunks. If the -+* buffer size is odd, then the last chunk will be 8bits. The SPI chip -+* select is not handled implicitely. -+* -+* INPUT: -+* pRxBuff: Pointer to the buffer to write the RX info in -+* pTxBuff: Pointer to the buffer holding the TX info -+* buffSize: length of both the pTxBuff and pRxBuff -+* -+* OUTPUT: -+* pRxBuff: Pointer of the buffer holding the RX data -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSpiReadWrite(MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize) -+{ -+ MV_STATUS ret; -+ MV_U32 bytesLeft = buffSize; -+ MV_U16* txPtr = (MV_U16*)pTxBuff; -+ MV_U16* rxPtr = (MV_U16*)pRxBuff; -+ -+ /* check for null parameters */ -+ if ((pRxBuff == NULL) || (pTxBuff == NULL)) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check that the buffer pointer and the buffer size are 16bit aligned */ -+ if ((((MV_U32)buffSize & 1) == 0) && (((MV_U32)pTxBuff & 1) == 0) && (((MV_U32)pRxBuff & 1) == 0)) -+ { -+ /* Verify that the SPI mode is in 16bit mode */ -+ MV_REG_BIT_SET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); -+ -+ /* TX/RX as long we have complete 16bit chunks */ -+ while (bytesLeft >= MV_SPI_16_BIT_CHUNK_SIZE) -+ { -+ /* Transmitted and wait for the transfer to be completed */ -+ if ((ret = mvSpi16bitDataTxRx(*txPtr, rxPtr)) != MV_OK) -+ return ret; -+ -+ /* increment the pointers */ -+ txPtr++; -+ rxPtr++; -+ bytesLeft -= MV_SPI_16_BIT_CHUNK_SIZE; -+ } -+ } -+ else -+ { -+ /* Verify that the SPI mode is in 8bit mode */ -+ MV_REG_BIT_RESET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); -+ -+ /* TX/RX in 8bit chanks */ -+ while (bytesLeft > 0) -+ { -+ /* Transmitted and wait for the transfer to be completed */ -+ if ( (ret = mvSpi8bitDataTxRx(*pTxBuff, pRxBuff) ) != MV_OK) -+ return ret; -+ pRxBuff++; -+ pTxBuff++; -+ bytesLeft--; -+ } -+ } -+ -+ return MV_OK; -+} -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,94 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvSpihH -+#define __INCmvSpihH -+ -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+ -+/* Function Prototypes */ -+/* Init */ -+MV_STATUS mvSpiInit (MV_U32 serialBaudRate); -+ -+/* Set the Frequency of the Spi clock */ -+MV_STATUS mvSpiBaudRateSet(MV_U32 serialBaudRate); -+ -+/* Assert the SPI chip select */ -+MV_VOID mvSpiCsAssert (MV_VOID); -+ -+/* De-assert the SPI chip select */ -+MV_VOID mvSpiCsDeassert (MV_VOID); -+ -+/* Simultanuous Read and write */ -+MV_STATUS mvSpiReadWrite (MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize); -+ -+/* serialize a buffer on the TX line - Rx is ignored */ -+MV_STATUS mvSpiWrite (MV_U8* pTxBuff, MV_U32 buffSize); -+ -+/* read from the RX line by writing dummy values to the TX line */ -+MV_STATUS mvSpiRead (MV_U8* pRxBuff, MV_U32 buffSize); -+ -+#endif /* __INCmvSpihH */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,249 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "spi/mvSpi.h" -+#include "spi/mvSpiSpec.h" -+ -+/*#define MV_DEBUG*/ -+#ifdef MV_DEBUG -+#define DB(x) x -+#else -+#define DB(x) -+#endif -+ -+ -+/******************************************************************************* -+* mvSpiReadAndWrite - Read and Write a buffer simultanuousely -+* -+* DESCRIPTION: -+* Transmit and receive a buffer over the SPI in 16bit chunks. If the -+* buffer size is odd, then the last chunk will be 8bits. -+* -+* INPUT: -+* pRxBuff: Pointer to the buffer to write the RX info in -+* pTxBuff: Pointer to the buffer holding the TX info -+* buffSize: length of both the pTxBuff and pRxBuff -+* -+* OUTPUT: -+* pRxBuff: Pointer of the buffer holding the RX data -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSpiReadAndWrite(MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize) -+{ -+ MV_STATUS ret; -+ -+ /* check for null parameters */ -+ if ((pRxBuff == NULL) || (pTxBuff == NULL) || (buffSize == 0)) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* First assert the chip select */ -+ mvSpiCsAssert(); -+ -+ ret = mvSpiReadWrite(pRxBuff, pTxBuff, buffSize); -+ -+ /* Finally deassert the chip select */ -+ mvSpiCsDeassert(); -+ -+ return ret; -+} -+ -+/******************************************************************************* -+* mvSpiWriteThenWrite - Serialize a command followed by the data over the TX line -+* -+* DESCRIPTION: -+* Assert the chip select line. Transmit the command buffer followed by -+* the data buffer. Then deassert the CS line. -+* -+* INPUT: -+* pCmndBuff: Pointer to the command buffer to transmit -+* cmndSize: length of the command size -+* pTxDataBuff: Pointer to the data buffer to transmit -+* txDataSize: length of the data buffer -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSpiWriteThenWrite (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pTxDataBuff, -+ MV_U32 txDataSize) -+{ -+ MV_STATUS ret = MV_OK, tempRet; -+ -+ /* check for null parameters */ -+#ifndef CONFIG_MARVELL -+ if(NULL == pTxDataBuff) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+#endif -+ -+ if (pCmndBuff == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* First assert the chip select */ -+ mvSpiCsAssert(); -+ -+ /* first write the command */ -+ if ((cmndSize) && (pCmndBuff != NULL)) -+ { -+ if ((tempRet = mvSpiWrite(pCmndBuff, cmndSize)) != MV_OK) -+ ret = tempRet; -+ } -+ -+ /* Then write the data buffer */ -+#ifndef CONFIG_MARVELL -+ if (txDataSize) -+#else -+ if ((txDataSize) && (pTxDataBuff != NULL)) -+#endif -+ { -+ if ((tempRet = mvSpiWrite(pTxDataBuff, txDataSize)) != MV_OK) -+ ret = tempRet; -+ } -+ -+ /* Finally deassert the chip select */ -+ mvSpiCsDeassert(); -+ -+ return ret; -+} -+ -+/******************************************************************************* -+* mvSpiWriteThenRead - Serialize a command then read a data buffer -+* -+* DESCRIPTION: -+* Assert the chip select line. Transmit the command buffer then read -+* the data buffer. Then deassert the CS line. -+* -+* INPUT: -+* pCmndBuff: Pointer to the command buffer to transmit -+* cmndSize: length of the command size -+* pRxDataBuff: Pointer to the buffer to read the data in -+* txDataSize: length of the data buffer -+* -+* OUTPUT: -+* pRxDataBuff: Pointer to the buffer holding the data -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSpiWriteThenRead (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pRxDataBuff, -+ MV_U32 rxDataSize,MV_U32 dummyBytesToRead) -+{ -+ MV_STATUS ret = MV_OK, tempRet; -+ MV_U8 dummyByte; -+ -+ /* check for null parameters */ -+ if ((pCmndBuff == NULL) && (pRxDataBuff == NULL)) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* First assert the chip select */ -+ mvSpiCsAssert(); -+ -+ /* first write the command */ -+ if ((cmndSize) && (pCmndBuff != NULL)) -+ { -+ if ((tempRet = mvSpiWrite(pCmndBuff, cmndSize)) != MV_OK) -+ ret = tempRet; -+ } -+ -+ /* Read dummy bytes before real data. */ -+ while(dummyBytesToRead) -+ { -+ mvSpiRead(&dummyByte,1); -+ dummyBytesToRead--; -+ } -+ -+ /* Then write the data buffer */ -+ if ((rxDataSize) && (pRxDataBuff != NULL)) -+ { -+ if ((tempRet = mvSpiRead(pRxDataBuff, rxDataSize)) != MV_OK) -+ ret = tempRet; -+ } -+ -+ /* Finally deassert the chip select */ -+ mvSpiCsDeassert(); -+ -+ return ret; -+} -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,82 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvSpiCmndhH -+#define __INCmvSpiCmndhH -+ -+#include "mvTypes.h" -+ -+/* Function Prototypes */ -+ -+/* Simultanuous Read and write */ -+MV_STATUS mvSpiReadAndWrite (MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize); -+ -+/* write command - write a command and then write data */ -+MV_STATUS mvSpiWriteThenWrite (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pTxDataBuff, MV_U32 txDataSize); -+ -+/* read command - write a command and then read data by writing dummy data */ -+MV_STATUS mvSpiWriteThenRead (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pRxDataBuff, -+ MV_U32 rxDataSize,MV_U32 dummyBytesToRead); -+ -+#endif /* __INCmvSpiCmndhH */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiSpec.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiSpec.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiSpec.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiSpec.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,98 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvSpiSpecH -+#define __INCmvSpiSpecH -+ -+/* Constants */ -+#define MV_SPI_WAIT_RDY_MAX_LOOP 100000 -+#define MV_SPI_16_BIT_CHUNK_SIZE 2 -+#define MV_SPI_DUMMY_WRITE_16BITS 0xFFFF -+#define MV_SPI_DUMMY_WRITE_8BITS 0xFF -+ -+/* Marvell Flash Device Controller Registers */ -+#define MV_SPI_CTRLR_OFST 0x10600 -+#define MV_SPI_IF_CTRL_REG (MV_SPI_CTRLR_OFST + 0x00) -+#define MV_SPI_IF_CONFIG_REG (MV_SPI_CTRLR_OFST + 0x04) -+#define MV_SPI_DATA_OUT_REG (MV_SPI_CTRLR_OFST + 0x08) -+#define MV_SPI_DATA_IN_REG (MV_SPI_CTRLR_OFST + 0x0c) -+#define MV_SPI_INT_CAUSE_REG (MV_SPI_CTRLR_OFST + 0x10) -+#define MV_SPI_INT_CAUSE_MASK_REG (MV_SPI_CTRLR_OFST + 0x14) -+ -+/* Serial Memory Interface Control Register Masks */ -+#define MV_SPI_CS_ENABLE_OFFSET 0 /* bit 0 */ -+#define MV_SPI_MEMORY_READY_OFFSET 1 /* bit 1 */ -+#define MV_SPI_CS_ENABLE_MASK (0x1 << MV_SPI_CS_ENABLE_OFFSET) -+#define MV_SPI_MEMORY_READY_MASK (0x1 << MV_SPI_MEMORY_READY_OFFSET) -+ -+/* Serial Memory Interface Configuration Register Masks */ -+#define MV_SPI_CLK_PRESCALE_OFFSET 0 /* bit 0-4 */ -+#define MV_SPI_BYTE_LENGTH_OFFSET 5 /* bit 5 */ -+#define MV_SPI_ADDRESS_BURST_LENGTH_OFFSET 8 /* bit 8-9 */ -+#define MV_SPI_CLK_PRESCALE_MASK (0x1F << MV_SPI_CLK_PRESCALE_OFFSET) -+#define MV_SPI_BYTE_LENGTH_MASK (0x1 << MV_SPI_BYTE_LENGTH_OFFSET) -+#define MV_SPI_ADDRESS_BURST_LENGTH_MASK (0x3 << MV_SPI_ADDRESS_BURST_LENGTH_OFFSET) -+ -+#endif /* __INCmvSpiSpecH */ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvCompVer.txt linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvCompVer.txt ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvCompVer.txt 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvCompVer.txt 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,4 @@ -+Global HAL Version: FEROCEON_HAL_3_1_7 -+Unit HAL Version: 3.1.5 -+Description: This component includes an implementation of the unit HAL drivers -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,1023 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#include "mvTwsi.h" -+#include "mvTwsiSpec.h" -+#include "cpu/mvCpu.h" -+ -+ -+/*#define MV_DEBUG*/ -+#ifdef MV_DEBUG -+#define DB(x) x -+#else -+#define DB(x) -+#endif -+ -+static MV_VOID twsiIntFlgClr(MV_U8 chanNum); -+static MV_BOOL twsiMainIntGet(MV_U8 chanNum); -+static MV_VOID twsiAckBitSet(MV_U8 chanNum); -+static MV_U32 twsiStsGet(MV_U8 chanNum); -+static MV_VOID twsiReset(MV_U8 chanNum); -+static MV_STATUS twsiAddr7BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command); -+static MV_STATUS twsiAddr10BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command); -+static MV_STATUS twsiDataTransmit(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize); -+static MV_STATUS twsiDataReceive(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize); -+static MV_STATUS twsiTargetOffsSet(MV_U8 chanNum, MV_U32 offset,MV_BOOL moreThen256); -+ -+ -+static MV_BOOL twsiTimeoutChk(MV_U32 timeout, const MV_8 *pString) -+{ -+ if(timeout >= TWSI_TIMEOUT_VALUE) -+ { -+ DB(mvOsPrintf("%s",pString)); -+ return MV_TRUE; -+ } -+ return MV_FALSE; -+ -+} -+/******************************************************************************* -+* mvTwsiStartBitSet - Set start bit on the bus -+* -+* DESCRIPTION: -+* This routine sets the start bit on the TWSI bus. -+* The routine first checks for interrupt flag condition, then it sets -+* the start bit in the TWSI Control register. -+* If the interrupt flag condition check previously was set, the function -+* will clear it. -+* The function then wait for the start bit to be cleared by the HW. -+* Then it waits for the interrupt flag to be set and eventually, the -+* TWSI status is checked to be 0x8 or 0x10(repeated start bit). -+* -+* INPUT: -+* chanNum - TWSI channel. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK is start bit was set successfuly on the bus. -+* MV_FAIL if interrupt flag was set before setting start bit. -+* -+*******************************************************************************/ -+MV_STATUS mvTwsiStartBitSet(MV_U8 chanNum) -+{ -+ MV_BOOL isIntFlag = MV_FALSE; -+ MV_U32 timeout, temp; -+ -+ DB(mvOsPrintf("TWSI: mvTwsiStartBitSet \n")); -+ /* check Int flag */ -+ if(twsiMainIntGet(chanNum)) -+ isIntFlag = MV_TRUE; -+ /* set start Bit */ -+ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); -+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp | TWSI_CONTROL_START_BIT); -+ -+ /* in case that the int flag was set before i.e. repeated start bit */ -+ if(isIntFlag){ -+ DB(mvOsPrintf("TWSI: mvTwsiStartBitSet repeated start Bit\n")); -+ twsiIntFlgClr(chanNum); -+ } -+ -+ /* wait for interrupt */ -+ timeout = 0; -+ while(!twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: mvTwsiStartBitSet ERROR - Start Clear bit TimeOut .\n")) -+ return MV_TIMEOUT; -+ -+ -+ /* check that start bit went down */ -+ if((MV_REG_READ(TWSI_CONTROL_REG(chanNum)) & TWSI_CONTROL_START_BIT) != 0) -+ { -+ mvOsPrintf("TWSI: mvTwsiStartBitSet ERROR - start bit didn't went down\n"); -+ return MV_FAIL; -+ } -+ -+ /* check the status */ -+ temp = twsiStsGet(chanNum); -+ if(( temp != TWSI_START_CON_TRA ) && ( temp != TWSI_REPEATED_START_CON_TRA )) -+ { -+ mvOsPrintf("TWSI: mvTwsiStartBitSet ERROR - status %x after Set Start Bit. \n",temp); -+ return MV_FAIL; -+ } -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvTwsiStopBitSet - Set stop bit on the bus -+* -+* DESCRIPTION: -+* This routine set the stop bit on the TWSI bus. -+* The function then wait for the stop bit to be cleared by the HW. -+* Finally the function checks for status of 0xF8. -+* -+* INPUT: -+* chanNum - TWSI channel -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE is stop bit was set successfuly on the bus. -+* -+*******************************************************************************/ -+MV_STATUS mvTwsiStopBitSet(MV_U8 chanNum) -+{ -+ MV_U32 timeout, temp; -+ -+ /* Generate stop bit */ -+ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); -+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp | TWSI_CONTROL_STOP_BIT); -+ -+ twsiIntFlgClr(chanNum); -+ -+ /* wait for stop bit to come down */ -+ timeout = 0; -+ while( ((MV_REG_READ(TWSI_CONTROL_REG(chanNum)) & TWSI_CONTROL_STOP_BIT) != 0) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: mvTwsiStopBitSet ERROR - Stop bit TimeOut .\n")) -+ return MV_TIMEOUT; -+ -+ /* check that the stop bit went down */ -+ if((MV_REG_READ(TWSI_CONTROL_REG(chanNum)) & TWSI_CONTROL_STOP_BIT) != 0) -+ { -+ mvOsPrintf("TWSI: mvTwsiStopBitSet ERROR - stop bit didn't went down. \n"); -+ return MV_FAIL; -+ } -+ -+ /* check the status */ -+ temp = twsiStsGet(chanNum); -+ if( temp != TWSI_NO_REL_STS_INT_FLAG_IS_KEPT_0){ -+ mvOsPrintf("TWSI: mvTwsiStopBitSet ERROR - status %x after Stop Bit. \n", temp); -+ return MV_FAIL; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* twsiMainIntGet - Get twsi bit from main Interrupt cause. -+* -+* DESCRIPTION: -+* This routine returns the twsi interrupt flag value. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE is interrupt flag is set, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+static MV_BOOL twsiMainIntGet(MV_U8 chanNum) -+{ -+ MV_U32 temp; -+ -+ /* get the int flag bit */ -+ -+ temp = MV_REG_READ(TWSI_CPU_MAIN_INT_CAUSE_REG); -+ if (temp & (TWSI0_CPU_MAIN_INT_BIT << chanNum)) -+ return MV_TRUE; -+ -+ return MV_FALSE; -+} -+/******************************************************************************* -+* twsiIntFlgClr - Clear Interrupt flag. -+* -+* DESCRIPTION: -+* This routine clears the interrupt flag. It does NOT poll the interrupt -+* to make sure the clear. After clearing the interrupt, it waits for at -+* least 1 miliseconds. -+* -+* INPUT: -+* chanNum - TWSI channel -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+static MV_VOID twsiIntFlgClr(MV_U8 chanNum) -+{ -+ MV_U32 temp; -+ -+ /* wait for 1 mili to prevent TWSI register write after write problems */ -+ mvOsDelay(1); -+ /* clear the int flag bit */ -+ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); -+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum),temp & ~(TWSI_CONTROL_INT_FLAG_SET)); -+ -+ /* wait for 1 mili sec for the clear to take effect */ -+ mvOsDelay(1); -+ -+ return; -+} -+ -+ -+/******************************************************************************* -+* twsiAckBitSet - Set acknowledge bit on the bus -+* -+* DESCRIPTION: -+* This routine set the acknowledge bit on the TWSI bus. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+static MV_VOID twsiAckBitSet(MV_U8 chanNum) -+{ -+ MV_U32 temp; -+ -+ /*Set the Ack bit */ -+ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); -+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp | TWSI_CONTROL_ACK); -+ -+ /* Add delay of 1ms */ -+ mvOsDelay(1); -+ return; -+} -+ -+ -+/******************************************************************************* -+* twsiInit - Initialize TWSI interface -+* -+* DESCRIPTION: -+* This routine: -+* -Reset the TWSI. -+* -Initialize the TWSI clock baud rate according to given frequancy -+* parameter based on Tclk frequancy and enables TWSI slave. -+* -Set the ack bit. -+* -Assign the TWSI slave address according to the TWSI address Type. -+* -+* -+* INPUT: -+* chanNum - TWSI channel -+* frequancy - TWSI frequancy in KHz. (up to 100KHZ) -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Actual frequancy. -+* -+*******************************************************************************/ -+MV_U32 mvTwsiInit(MV_U8 chanNum, MV_HZ frequancy, MV_U32 Tclk, MV_TWSI_ADDR *pTwsiAddr, MV_BOOL generalCallEnable) -+{ -+ MV_U32 n,m,freq,margin,minMargin = 0xffffffff; -+ MV_U32 power; -+ MV_U32 actualFreq = 0,actualN = 0,actualM = 0,val; -+ -+ if(frequancy > 100000) -+ { -+ mvOsPrintf("Warning TWSI frequancy is too high, please use up tp 100Khz. \n"); -+ } -+ -+ DB(mvOsPrintf("TWSI: mvTwsiInit - Tclk = %d freq = %d\n",Tclk,frequancy)); -+ /* Calucalte N and M for the TWSI clock baud rate */ -+ for(n = 0 ; n < 8 ; n++) -+ { -+ for(m = 0 ; m < 16 ; m++) -+ { -+ power = 2 << n; /* power = 2^(n+1) */ -+ freq = Tclk/(10*(m+1)*power); -+ margin = MV_ABS(frequancy - freq); -+ if(margin < minMargin) -+ { -+ minMargin = margin; -+ actualFreq = freq; -+ actualN = n; -+ actualM = m; -+ } -+ } -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiInit - actN %d actM %d actFreq %d\n",actualN , actualM, actualFreq)); -+ /* Reset the TWSI logic */ -+ twsiReset(chanNum); -+ -+ /* Set the baud rate */ -+ val = ((actualM<< TWSI_BAUD_RATE_M_OFFS) | actualN << TWSI_BAUD_RATE_N_OFFS); -+ MV_REG_WRITE(TWSI_STATUS_BAUDE_RATE_REG(chanNum),val); -+ -+ /* Enable the TWSI and slave */ -+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), TWSI_CONTROL_ENA | TWSI_CONTROL_ACK); -+ -+ /* set the TWSI slave address */ -+ if( pTwsiAddr->type == ADDR10_BIT )/* 10 Bit deviceAddress */ -+ { -+ /* writing the 2 most significant bits of the 10 bit address*/ -+ val = ((pTwsiAddr->address & TWSI_SLAVE_ADDR_10BIT_MASK) >> TWSI_SLAVE_ADDR_10BIT_OFFS ); -+ /* bits 7:3 must be 0x11110 */ -+ val |= TWSI_SLAVE_ADDR_10BIT_CONST; -+ /* set GCE bit */ -+ if(generalCallEnable) -+ val |= TWSI_SLAVE_ADDR_GCE_ENA; -+ /* write slave address */ -+ MV_REG_WRITE(TWSI_SLAVE_ADDR_REG(chanNum),val); -+ -+ /* writing the 8 least significant bits of the 10 bit address*/ -+ val = (pTwsiAddr->address << TWSI_EXTENDED_SLAVE_OFFS) & TWSI_EXTENDED_SLAVE_MASK; -+ MV_REG_WRITE(TWSI_EXTENDED_SLAVE_ADDR_REG(chanNum), val); -+ } -+ else /*7 bit address*/ -+ { -+ /* set the 7 Bits address */ -+ MV_REG_WRITE(TWSI_EXTENDED_SLAVE_ADDR_REG(chanNum),0x0); -+ val = (pTwsiAddr->address << TWSI_SLAVE_ADDR_7BIT_OFFS) & TWSI_SLAVE_ADDR_7BIT_MASK; -+ MV_REG_WRITE(TWSI_SLAVE_ADDR_REG(chanNum), val); -+ } -+ -+ /* unmask twsi int */ -+ val = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); -+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), val | TWSI_CONTROL_INT_ENA); -+ /* Add delay of 1ms */ -+ mvOsDelay(1); -+ -+ return actualFreq; -+} -+ -+ -+/******************************************************************************* -+* twsiStsGet - Get the TWSI status value. -+* -+* DESCRIPTION: -+* This routine returns the TWSI status value. -+* -+* INPUT: -+* chanNum - TWSI channel -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_U32 - the TWSI status. -+* -+*******************************************************************************/ -+static MV_U32 twsiStsGet(MV_U8 chanNum) -+{ -+ return MV_REG_READ(TWSI_STATUS_BAUDE_RATE_REG(chanNum)); -+ -+} -+ -+/******************************************************************************* -+* twsiReset - Reset the TWSI. -+* -+* DESCRIPTION: -+* Resets the TWSI logic and sets all TWSI registers to their reset values. -+* -+* INPUT: -+* chanNum - TWSI channel -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None -+* -+*******************************************************************************/ -+static MV_VOID twsiReset(MV_U8 chanNum) -+{ -+ /* Reset the TWSI logic */ -+ MV_REG_WRITE(TWSI_SOFT_RESET_REG(chanNum),0); -+ -+ /* wait for 2 mili sec */ -+ mvOsDelay(2); -+ -+ return; -+} -+ -+ -+ -+ -+/******************************* POLICY ****************************************/ -+ -+ -+ -+/******************************************************************************* -+* mvTwsiAddrSet - Set address on TWSI bus. -+* -+* DESCRIPTION: -+* This function Set address (7 or 10 Bit address) on the Twsi Bus. -+* -+* INPUT: -+* chanNum - TWSI channel -+* pTwsiAddr - twsi address. -+* command - read / write . -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK - if setting the address completed succesfully. -+* MV_FAIL otherwmise. -+* -+*******************************************************************************/ -+MV_STATUS mvTwsiAddrSet(MV_U8 chanNum, MV_TWSI_ADDR *pTwsiAddr, MV_TWSI_CMD command) -+{ -+ DB(mvOsPrintf("TWSI: mvTwsiAddr7BitSet addr %x , type %d, cmd is %s\n",pTwsiAddr->address,\ -+ pTwsiAddr->type, ((command==MV_TWSI_WRITE)?"Write":"Read") )); -+ /* 10 Bit address */ -+ if(pTwsiAddr->type == ADDR10_BIT) -+ { -+ return twsiAddr10BitSet(chanNum, pTwsiAddr->address,command); -+ } -+ /* 7 Bit address */ -+ else -+ { -+ return twsiAddr7BitSet(chanNum, pTwsiAddr->address,command); -+ } -+ -+} -+ -+/******************************************************************************* -+* twsiAddr10BitSet - Set 10 Bit address on TWSI bus. -+* -+* DESCRIPTION: -+* There are two address phases: -+* 1) Write '11110' to data register bits [7:3] and 10-bit address MSB -+* (bits [9:8]) to data register bits [2:1] plus a write(0) or read(1) bit -+* to the Data register. Then it clears interrupt flag which drive -+* the address on the TWSI bus. The function then waits for interrupt -+* flag to be active and status 0x18 (write) or 0x40 (read) to be set. -+* 2) write the rest of 10-bit address to data register and clears -+* interrupt flag which drive the address on the TWSI bus. The -+* function then waits for interrupt flag to be active and status -+* 0xD0 (write) or 0xE0 (read) to be set. -+* -+* INPUT: -+* chanNum - TWSI channel -+* deviceAddress - twsi address. -+* command - read / write . -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK - if setting the address completed succesfully. -+* MV_FAIL otherwmise. -+* -+*******************************************************************************/ -+static MV_STATUS twsiAddr10BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command) -+{ -+ MV_U32 val,timeout; -+ -+ /* writing the 2 most significant bits of the 10 bit address*/ -+ val = ((deviceAddress & TWSI_DATA_ADDR_10BIT_MASK) >> TWSI_DATA_ADDR_10BIT_OFFS ); -+ /* bits 7:3 must be 0x11110 */ -+ val |= TWSI_DATA_ADDR_10BIT_CONST; -+ /* set command */ -+ val |= command; -+ MV_REG_WRITE(TWSI_DATA_REG(chanNum), val); -+ /* WA add a delay */ -+ mvOsDelay(1); -+ -+ /* clear Int flag */ -+ twsiIntFlgClr(chanNum); -+ -+ /* wait for Int to be Set */ -+ timeout = 0; -+ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiAddr10BitSet ERROR - 1st addr (10Bit) Int TimeOut.\n")) -+ return MV_TIMEOUT; -+ -+ /* check the status */ -+ val = twsiStsGet(chanNum); -+ if(( (val != TWSI_AD_PLS_RD_BIT_TRA_ACK_REC) && (command == MV_TWSI_READ ) ) || -+ ( (val != TWSI_AD_PLS_WR_BIT_TRA_ACK_REC) && (command == MV_TWSI_WRITE) )) -+ { -+ mvOsPrintf("TWSI: twsiAddr10BitSet ERROR - status %x 1st addr (10 Bit) in %s mode.\n"\ -+ ,val, ((command==MV_TWSI_WRITE)?"Write":"Read") ); -+ return MV_FAIL; -+ } -+ -+ /* set 8 LSB of the address */ -+ val = (deviceAddress << TWSI_DATA_ADDR_7BIT_OFFS) & TWSI_DATA_ADDR_7BIT_MASK; -+ MV_REG_WRITE(TWSI_DATA_REG(chanNum), val); -+ -+ /* clear Int flag */ -+ twsiIntFlgClr(chanNum); -+ -+ /* wait for Int to be Set */ -+ timeout = 0; -+ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiAddr10BitSet ERROR - 2nd (10 Bit) Int TimOut.\n")) -+ return MV_TIMEOUT; -+ -+ /* check the status */ -+ val = twsiStsGet(chanNum); -+ if(( (val != TWSI_SEC_AD_PLS_RD_BIT_TRA_ACK_REC) && (command == MV_TWSI_READ ) ) || -+ ( (val != TWSI_SEC_AD_PLS_WR_BIT_TRA_ACK_REC) && (command == MV_TWSI_WRITE) )) -+ { -+ mvOsPrintf("TWSI: twsiAddr10BitSet ERROR - status %x 2nd addr(10 Bit) in %s mode.\n"\ -+ ,val, ((command==MV_TWSI_WRITE)?"Write":"Read") ); -+ return MV_FAIL; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* twsiAddr7BitSet - Set 7 Bit address on TWSI bus. -+* -+* DESCRIPTION: -+* This function writes 7 bit address plus a write or read bit to the -+* Data register. Then it clears interrupt flag which drive the address on -+* the TWSI bus. The function then waits for interrupt flag to be active -+* and status 0x18 (write) or 0x40 (read) to be set. -+* -+* INPUT: -+* chanNum - TWSI channel -+* deviceAddress - twsi address. -+* command - read / write . -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK - if setting the address completed succesfully. -+* MV_FAIL otherwmise. -+* -+*******************************************************************************/ -+static MV_STATUS twsiAddr7BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command) -+{ -+ MV_U32 val,timeout; -+ -+ /* set the address */ -+ val = (deviceAddress << TWSI_DATA_ADDR_7BIT_OFFS) & TWSI_DATA_ADDR_7BIT_MASK; -+ /* set command */ -+ val |= command; -+ MV_REG_WRITE(TWSI_DATA_REG(chanNum), val); -+ /* WA add a delay */ -+ mvOsDelay(1); -+ -+ /* clear Int flag */ -+ twsiIntFlgClr(chanNum); -+ -+ /* wait for Int to be Set */ -+ timeout = 0; -+ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiAddr7BitSet ERROR - Addr (7 Bit) int TimeOut.\n")) -+ return MV_TIMEOUT; -+ -+ /* check the status */ -+ val = twsiStsGet(chanNum); -+ if(( (val != TWSI_AD_PLS_RD_BIT_TRA_ACK_REC) && (command == MV_TWSI_READ ) ) || -+ ( (val != TWSI_AD_PLS_WR_BIT_TRA_ACK_REC) && (command == MV_TWSI_WRITE) )) -+ { -+ /* only in debug, since in boot we try to read the SPD of both DRAM, and we don't -+ want error messeges in case DIMM doesn't exist. */ -+ DB(mvOsPrintf("TWSI: twsiAddr7BitSet ERROR - status %x addr (7 Bit) in %s mode.\n"\ -+ ,val,((command==MV_TWSI_WRITE)?"Write":"Read") )); -+ return MV_FAIL; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* twsiDataWrite - Trnasmit a data block over TWSI bus. -+* -+* DESCRIPTION: -+* This function writes a given data block to TWSI bus in 8 bit granularity. -+* first The function waits for interrupt flag to be active then -+* For each 8-bit data: -+* The function writes data to data register. It then clears -+* interrupt flag which drives the data on the TWSI bus. -+* The function then waits for interrupt flag to be active and status -+* 0x28 to be set. -+* -+* -+* INPUT: -+* chanNum - TWSI channel -+* pBlock - Data block. -+* blockSize - number of chars in pBlock. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK - if transmiting the block completed succesfully, -+* MV_BAD_PARAM - if pBlock is NULL, -+* MV_FAIL otherwmise. -+* -+*******************************************************************************/ -+static MV_STATUS twsiDataTransmit(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize) -+{ -+ MV_U32 timeout, temp, blockSizeWr = blockSize; -+ -+ if(NULL == pBlock) -+ return MV_BAD_PARAM; -+ -+ /* wait for Int to be Set */ -+ timeout = 0; -+ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataTransmit ERROR - Read Data Int TimeOut.\n")) -+ return MV_TIMEOUT; -+ -+ while(blockSizeWr) -+ { -+ /* write the data*/ -+ MV_REG_WRITE(TWSI_DATA_REG(chanNum),(MV_U32)*pBlock); -+ DB(mvOsPrintf("TWSI: twsiDataTransmit place = %d write %x \n",\ -+ blockSize - blockSizeWr, *pBlock)); -+ pBlock++; -+ blockSizeWr--; -+ -+ twsiIntFlgClr(chanNum); -+ -+ /* wait for Int to be Set */ -+ timeout = 0; -+ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataTransmit ERROR - Read Data Int TimeOut.\n")) -+ return MV_TIMEOUT; -+ -+ /* check the status */ -+ temp = twsiStsGet(chanNum); -+ if(temp != TWSI_M_TRAN_DATA_BYTE_ACK_REC) -+ { -+ mvOsPrintf("TWSI: twsiDataTransmit ERROR - status %x in write trans\n",temp); -+ return MV_FAIL; -+ } -+ -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* twsiDataReceive - Receive data block from TWSI bus. -+* -+* DESCRIPTION: -+* This function receive data block from TWSI bus in 8bit granularity -+* into pBlock buffer. -+* first The function waits for interrupt flag to be active then -+* For each 8-bit data: -+* It clears the interrupt flag which allows the next data to be -+* received from TWSI bus. -+* The function waits for interrupt flag to be active, -+* and status reg is 0x50. -+* Then the function reads data from data register, and copies it to -+* the given buffer. -+* -+* INPUT: -+* chanNum - TWSI channel -+* blockSize - number of bytes to read. -+* -+* OUTPUT: -+* pBlock - Data block. -+* -+* RETURN: -+* MV_OK - if receive transaction completed succesfully, -+* MV_BAD_PARAM - if pBlock is NULL, -+* MV_FAIL otherwmise. -+* -+*******************************************************************************/ -+static MV_STATUS twsiDataReceive(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize) -+{ -+ MV_U32 timeout, temp, blockSizeRd = blockSize; -+ if(NULL == pBlock) -+ return MV_BAD_PARAM; -+ -+ /* wait for Int to be Set */ -+ timeout = 0; -+ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataReceive ERROR - Read Data int Time out .\n")) -+ return MV_TIMEOUT; -+ -+ while(blockSizeRd) -+ { -+ if(blockSizeRd == 1) -+ { -+ /* clear ack and Int flag */ -+ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); -+ temp &= ~(TWSI_CONTROL_ACK); -+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp); -+ } -+ twsiIntFlgClr(chanNum); -+ /* wait for Int to be Set */ -+ timeout = 0; -+ while( (!twsiMainIntGet(chanNum)) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataReceive ERROR - Read Data Int Time out .\n")) -+ return MV_TIMEOUT; -+ -+ /* check the status */ -+ temp = twsiStsGet(chanNum); -+ if((temp != TWSI_M_REC_RD_DATA_ACK_TRA) && (blockSizeRd !=1)) -+ { -+ mvOsPrintf("TWSI: twsiDataReceive ERROR - status %x in read trans \n",temp); -+ return MV_FAIL; -+ } -+ else if((temp != TWSI_M_REC_RD_DATA_ACK_NOT_TRA) && (blockSizeRd ==1)) -+ { -+ mvOsPrintf("TWSI: twsiDataReceive ERROR - status %x in Rd Terminate\n",temp); -+ return MV_FAIL; -+ } -+ -+ /* read the data*/ -+ *pBlock = (MV_U8)MV_REG_READ(TWSI_DATA_REG(chanNum)); -+ DB(mvOsPrintf("TWSI: twsiDataReceive place %d read %x \n",\ -+ blockSize - blockSizeRd,*pBlock)); -+ pBlock++; -+ blockSizeRd--; -+ } -+ -+ return MV_OK; -+} -+ -+ -+ -+/******************************************************************************* -+* twsiTargetOffsSet - Set TWST target offset on TWSI bus. -+* -+* DESCRIPTION: -+* The function support TWSI targets that have inside address space (for -+* example EEPROMs). The function: -+* 1) Convert the given offset into pBlock and size. -+* in case the offset should be set to a TWSI slave which support -+* more then 256 bytes offset, the offset setting will be done -+* in 2 transactions. -+* 2) Use twsiDataTransmit to place those on the bus. -+* -+* INPUT: -+* chanNum - TWSI channel -+* offset - offset to be set on the EEPROM device. -+* moreThen256 - whether the EEPROM device support more then 256 byte offset. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK - if setting the offset completed succesfully. -+* MV_FAIL otherwmise. -+* -+*******************************************************************************/ -+static MV_STATUS twsiTargetOffsSet(MV_U8 chanNum, MV_U32 offset, MV_BOOL moreThen256) -+{ -+ MV_U8 offBlock[2]; -+ MV_U32 offSize; -+ -+ if(moreThen256 == MV_TRUE) -+ { -+ offBlock[0] = (offset >> 8) & 0xff; -+ offBlock[1] = offset & 0xff; -+ offSize = 2; -+ } -+ else -+ { -+ offBlock[0] = offset & 0xff; -+ offSize = 1; -+ } -+ DB(mvOsPrintf("TWSI: twsiTargetOffsSet offSize = %x addr1 = %x addr2 = %x\n",\ -+ offSize,offBlock[0],offBlock[1])); -+ return twsiDataTransmit(chanNum, offBlock, offSize); -+ -+} -+ -+/******************************************************************************* -+* mvTwsiRead - Read data block from a TWSI Slave. -+* -+* DESCRIPTION: -+* The function calls the following functions: -+* -) mvTwsiStartBitSet(); -+* if(EEPROM device) -+* -) mvTwsiAddrSet(w); -+* -) twsiTargetOffsSet(); -+* -) mvTwsiStartBitSet(); -+* -) mvTwsiAddrSet(r); -+* -) twsiDataReceive(); -+* -) mvTwsiStopBitSet(); -+* -+* INPUT: -+* chanNum - TWSI channel -+* pTwsiSlave - Twsi Slave structure. -+* blockSize - number of bytes to read. -+* -+* OUTPUT: -+* pBlock - Data block. -+* -+* RETURN: -+* MV_OK - if EEPROM read transaction completed succesfully, -+* MV_BAD_PARAM - if pBlock is NULL, -+* MV_FAIL otherwmise. -+* -+*******************************************************************************/ -+MV_STATUS mvTwsiRead(MV_U8 chanNum, MV_TWSI_SLAVE *pTwsiSlave, MV_U8 *pBlock, MV_U32 blockSize) -+{ -+ if((NULL == pBlock) || (NULL == pTwsiSlave)) -+ return MV_BAD_PARAM; -+ if(MV_OK != mvTwsiStartBitSet(chanNum)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ -+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiStartBitSet\n")); -+ -+ /* in case offset exsist (i.e. eeprom ) */ -+ if(MV_TRUE == pTwsiSlave->validOffset) -+ { -+ if(MV_OK != mvTwsiAddrSet(chanNum, &(pTwsiSlave->slaveAddr), MV_TWSI_WRITE)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiAddrSet\n")); -+ if(MV_OK != twsiTargetOffsSet(chanNum, pTwsiSlave->offset, pTwsiSlave->moreThen256)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after twsiTargetOffsSet\n")); -+ if(MV_OK != mvTwsiStartBitSet(chanNum)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiStartBitSet\n")); -+ } -+ if(MV_OK != mvTwsiAddrSet(chanNum, &(pTwsiSlave->slaveAddr), MV_TWSI_READ)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiAddrSet\n")); -+ if(MV_OK != twsiDataReceive(chanNum, pBlock, blockSize)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after twsiDataReceive\n")); -+ -+ if(MV_OK != mvTwsiStopBitSet(chanNum)) -+ { -+ return MV_FAIL; -+ } -+ -+ twsiAckBitSet(chanNum); -+ -+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiStopBitSet\n")); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvTwsiWrite - Write data block to a TWSI Slave. -+* -+* DESCRIPTION: -+* The function calls the following functions: -+* -) mvTwsiStartBitSet(); -+* -) mvTwsiAddrSet(); -+* -)if(EEPROM device) -+* -) twsiTargetOffsSet(); -+* -) twsiDataTransmit(); -+* -) mvTwsiStopBitSet(); -+* -+* INPUT: -+* chanNum - TWSI channel -+* eepromAddress - eeprom address. -+* blockSize - number of bytes to write. -+* pBlock - Data block. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* MV_OK - if EEPROM read transaction completed succesfully. -+* MV_BAD_PARAM - if pBlock is NULL, -+* MV_FAIL otherwmise. -+* -+* NOTE: Part of the EEPROM, required that the offset will be aligned to the -+* max write burst supported. -+*******************************************************************************/ -+MV_STATUS mvTwsiWrite(MV_U8 chanNum, MV_TWSI_SLAVE *pTwsiSlave, MV_U8 *pBlock, MV_U32 blockSize) -+{ -+ if((NULL == pBlock) || (NULL == pTwsiSlave)) -+ return MV_BAD_PARAM; -+ -+ if(MV_OK != mvTwsiStartBitSet(chanNum)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ -+ DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after mvTwsiStartBitSet\n")); -+ if(MV_OK != mvTwsiAddrSet(chanNum, &(pTwsiSlave->slaveAddr), MV_TWSI_WRITE)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI :mvTwsiEepromWrite after mvTwsiAddrSet\n")); -+ -+ /* in case offset exsist (i.e. eeprom ) */ -+ if(MV_TRUE == pTwsiSlave->validOffset) -+ { -+ if(MV_OK != twsiTargetOffsSet(chanNum, pTwsiSlave->offset, pTwsiSlave->moreThen256)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after twsiTargetOffsSet\n")); -+ } -+ if(MV_OK != twsiDataTransmit(chanNum, pBlock, blockSize)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after twsiDataTransmit\n")); -+ if(MV_OK != mvTwsiStopBitSet(chanNum)) -+ { -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after mvTwsiStopBitSet\n")); -+ -+ return MV_OK; -+} -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,121 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#ifndef __INCmvTwsiH -+#define __INCmvTwsiH -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* need to update this includes */ -+#include "twsi/mvTwsiSpec.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+ -+ -+/* The TWSI interface supports both 7-bit and 10-bit addressing. */ -+/* This enumerator describes addressing type. */ -+typedef enum _mvTwsiAddrType -+{ -+ ADDR7_BIT, /* 7 bit address */ -+ ADDR10_BIT /* 10 bit address */ -+}MV_TWSI_ADDR_TYPE; -+ -+/* This structure describes TWSI address. */ -+typedef struct _mvTwsiAddr -+{ -+ MV_U32 address; /* address */ -+ MV_TWSI_ADDR_TYPE type; /* Address type */ -+}MV_TWSI_ADDR; -+ -+/* This structure describes a TWSI slave. */ -+typedef struct _mvTwsiSlave -+{ -+ MV_TWSI_ADDR slaveAddr; -+ MV_BOOL validOffset; /* whether the slave has offset (i.e. Eeprom etc.) */ -+ MV_U32 offset; /* offset in the slave. */ -+ MV_BOOL moreThen256; /* whether the ofset is bigger then 256 */ -+}MV_TWSI_SLAVE; -+ -+/* This enumerator describes TWSI protocol commands. */ -+typedef enum _mvTwsiCmd -+{ -+ MV_TWSI_WRITE, /* TWSI write command - 0 according to spec */ -+ MV_TWSI_READ /* TWSI read command - 1 according to spec */ -+}MV_TWSI_CMD; -+ -+MV_STATUS mvTwsiStartBitSet(MV_U8 chanNum); -+MV_STATUS mvTwsiStopBitSet(MV_U8 chanNum); -+MV_STATUS mvTwsiAddrSet(MV_U8 chanNum, MV_TWSI_ADDR *twsiAddr, MV_TWSI_CMD command); -+ -+MV_U32 mvTwsiInit(MV_U8 chanNum, MV_KHZ frequancy, MV_U32 Tclk, MV_TWSI_ADDR *twsiAddr, MV_BOOL generalCallEnable); -+MV_STATUS mvTwsiRead (MV_U8 chanNum, MV_TWSI_SLAVE *twsiSlave, MV_U8 *pBlock, MV_U32 blockSize); -+MV_STATUS mvTwsiWrite(MV_U8 chanNum, MV_TWSI_SLAVE *twsiSlave, MV_U8 *pBlock, MV_U32 blockSize); -+ -+ -+#ifdef __cplusplus -+} -+#endif /* __cplusplus */ -+ -+#endif /* __INCmvTwsiH */ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiEeprom.S linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiEeprom.S ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiEeprom.S 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiEeprom.S 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,457 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+/* includes */ -+#define MV_ASMLANGUAGE -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+#include "boardEnv/mvBoardEnvSpec.h" -+#include "mvOsAsm.h" -+#include "mvTwsiSpec.h" -+#include "mvSysHwConfig.h" -+#include "ctrlEnv/sys/mvCpuIfRegs.h" -+#include "mvCommon.h" -+ -+#define I2C_CH MV_BOARD_DIMM_I2C_CHANNEL -+ -+/* defines */ -+/* defines */ -+ -+ -+ .data -+ .global _i2cInit -+ .global _i2cRead -+ -+ .text -+ -+/******************************************************************************* -+* _i2cInit - Initialize TWSI interface -+* -+* DESCRIPTION: -+* The function performs TWSI interface initialization. It resets the -+* TWSI state machine and initialize its clock to 100KHz assuming Tclock -+* of 133MHz. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+_i2cInit: -+ mov r9, LR /* Save link register */ -+ mov r0, #0 /* Make sure r0 is zero */ -+ -+ /* Reset the i2c Mechanism first */ -+ MV_REG_WRITE_ASM (r0, r1, TWSI_SOFT_RESET_REG(I2C_CH)) -+ -+ bl _twsiDelay -+ bl _twsiDelay -+ -+ /* Initializing the I2C mechanism. Assuming Tclock frequency */ -+ /* of 166MHz. The I2C frequency in that case will be 100KHz. */ -+ /* For this settings, M = 9 and N = 3. Set the baud-rate with the */ -+ /* value of 0x2b (freq of ==> 100KHz */ -+ /* see spec for more details about the calculation of this value) */ -+ mov r6, #(9 << 3 | 3) -+ MV_REG_WRITE_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) -+ -+ /* Enable the I2C master */ -+ /* Enable TWSI interrupt in main mask reg */ -+ mov r6, #0xC4 -+ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) -+ -+ /* Let the slow TWSI machine get used to the idea that it is enabled */ -+ bl _twsiDelay -+ -+ -+ mov PC, r9 /* r9 is saved link register */ -+ -+/******************************************************************************* -+* _twsiDelay - Perform delay. -+* -+* DESCRIPTION: -+* The function performs a delay to enable TWSI logic to stable. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+_twsiDelay: -+ mov r10, #0x100000 /*was 0x400*/ -+ -+_twsiDelayLoop: -+ subs r10, r10, #1 -+ bne _twsiDelayLoop -+ -+ mov PC, LR -+ -+/******************************************************************************* -+* _i2cRead - Read byte from I2C EEPROM device. -+* -+* DESCRIPTION: -+* The function returns a byte from I2C EEPROM device. -+* The EEPROM device is 7-bit address type. -+* -+* INPUT: -+* r4 has the DIMM0 base address with shift 1 bit to the left -+* r7 has the EEPROM offset -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* r4 returns '0' if address can not be read. -+* r7 has byte value in case read is successful. -+* -+*******************************************************************************/ -+_i2cRead: -+ mov r9, LR /* Save link register */ -+ -+ /* Transmit the device address and desired offset within the EEPROM. */ -+ -+ /* Generate Start Bit */ -+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) -+ orr r6, r6, #TWSI_CONTROL_START_BIT -+ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) -+ -+ /* Wait for the interrupt flag (bit3) to be set */ -+ mov r10, #0x50000 -+loop_1: -+ subs r10, r10, #1 -+ beq loop_1_timeout -+#ifdef MV78XX0 -+ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) -+ tst r6, #BIT2 -+#else -+ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) -+ tst r6, #BIT5 -+#endif -+ beq loop_1 -+ -+loop_1_timeout: -+ -+ /* Wait for the start bit to be reset by HW */ -+ mov r10, #0x50000 -+loop_2: -+ subs r10, r10, #1 -+ beq loop_2_timeout -+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) -+ tst r6, #TWSI_CONTROL_START_BIT -+ bne loop_2 -+ -+loop_2_timeout: -+ -+ /* Wait for the status TWSI_START_CONDITION_TRA = 0x8 */ -+ mov r10, #0x50000 -+loop_3: -+ subs r10, r10, #1 -+ beq loop_3_timeout -+ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) -+ cmp r6, #0x08 -+ bne loop_3 -+ -+loop_3_timeout: -+ -+ /* writing the address of (DIMM0/1 << 1) with write indication */ -+ mov r6, r4, LSL #1 /* Write operation address bit 0 must be 0 */ -+ MV_REG_WRITE_ASM (r6, r1, TWSI_DATA_REG(I2C_CH)) -+ -+ bl _twsiDelay -+ /* Clear the interrupt flag */ -+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) -+ bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET -+ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) -+ bl _twsiDelay -+ -+ /* Waiting for the interrupt flag to be set which means that the -+ address has been transmitted */ -+loop_4: -+#ifdef MV78XX0 -+ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) -+ tst r6, #BIT2 -+#else -+ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) -+ tst r6, #BIT5 -+#endif -+ beq loop_4 /* if tst = 0, then the bit is not set yet */ -+ -+ /* Wait for status TWSI_ADDR_PLUS_WRITE_BIT_TRA_ACK_REC = 0x18 */ -+ mov r10, #0x50000 /* Set r10 to 0x50000 =~ 328,000 */ -+ -+loop_5: -+ subs r10, r10, #1 /* timeout count down */ -+ bne testStatus -+ mov r4, #0 /* r4 = 0 -> operation failed */ -+ b exit_i2cRead /* Exit if timeout (No DIMM) */ -+ -+testStatus: -+ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) -+ cmp r6, #0x18 -+ bne loop_5 -+ -+ -+ /* check if the offset is bigger than 256 byte*/ -+ tst r7, #0x80000000 -+ bne great_than_256 -+ -+ /* Write the offset to be read from the DIMM EEPROM */ -+ MV_REG_WRITE_ASM (r7, r1, TWSI_DATA_REG(I2C_CH)) -+ -+ b after_offset -+ -+great_than_256: -+ mov r10, r7, LSR #8 -+ and r10, r10, #0xff -+ /* Write the offset0 to be read from the EEPROM */ -+ MV_REG_WRITE_ASM (r10, r1, TWSI_DATA_REG(I2C_CH)) -+ -+ /* Clear the interrupt flag ==> signaling that the address can now -+ be transmited */ -+ -+ bl _twsiDelay -+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) -+ bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET -+ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) -+ bl _twsiDelay -+ -+ /* Wait for the interrupt to be set again ==> address has transmited */ -+loop_6_1: -+#ifdef MV78XX0 -+ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) -+ tst r6, #BIT2 -+#else -+ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) -+ tst r6, #BIT5 -+#endif -+ beq loop_6_1 -+ -+ /* Wait for status TWSI_MAS_TRAN_DATA_BYTE_ACK_REC = 0x28 */ -+loop_7_1: -+ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) -+ cmp r6, #0x28 -+ bne loop_7_1 -+ -+ -+ mov r10, r7 -+ and r10, r10, #0xff -+ /* Write the offset1 to be read from the EEPROM */ -+ MV_REG_WRITE_ASM (r10, r1, TWSI_DATA_REG(I2C_CH)) -+ -+ -+ -+after_offset: -+ -+ /* Clear the interrupt flag ==> signaling that the address can now -+ be transmited */ -+ -+ bl _twsiDelay -+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) -+ bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET -+ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) -+ bl _twsiDelay -+ -+ /* Wait for the interrupt to be set again ==> address has transmited */ -+loop_6: -+#ifdef MV78XX0 -+ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) -+ tst r6, #BIT2 -+#else -+ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) -+ tst r6, #BIT5 -+#endif -+ beq loop_6 -+ -+ /* Wait for status TWSI_MAS_TRAN_DATA_BYTE_ACK_REC = 0x28 */ -+loop_7: -+ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) -+ cmp r6, #0x28 -+ bne loop_7 -+ -+ /* Retransmit the device address with read indication to get the data */ -+ -+ /* generate a repeated start bit */ -+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) -+ orr r6, r6, #TWSI_CONTROL_START_BIT -+ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) -+ -+ -+ /* Clear the interrupt flag ==> the start bit will be transmitted. */ -+ bl _twsiDelay -+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) -+ bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET -+ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) -+ bl _twsiDelay -+ -+ /* Wait for the interrupt flag (bit3) to be set */ -+loop_9: -+#ifdef MV78XX0 -+ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) -+ tst r6, #BIT2 -+#else -+ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) -+ tst r6, #BIT5 -+#endif -+ beq loop_9 -+ -+ /* Wait for the start bit to be reset by HW */ -+loop_8: -+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) -+ tst r6, #TWSI_CONTROL_START_BIT -+ bne loop_8 -+ -+ /* Wait for status TWSI_REPEATED_START_CONDITION_TRA = 0x10 */ -+loop_10: -+ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) -+ cmp r6, #0x10 -+ bne loop_10 -+ -+ /* Writing the address of (DIMM0<<1) with read indication (bit0 is 1) */ -+ mov r6, r4, LSL #1 -+ orr r6, r6, #1 /* Read operation address bit 0 must be 1 */ -+ MV_REG_WRITE_ASM (r6, r1, TWSI_DATA_REG(I2C_CH)) -+ -+ /* Clear the interrupt flag ==> the address will be transmitted */ -+ bl _twsiDelay -+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) -+ bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET -+ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) -+ bl _twsiDelay -+ -+ /* Wait for the interrupt flag (bit3) to be set as a result of -+ transmitting the address. */ -+loop_11: -+#ifdef MV78XX0 -+ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) -+ tst r6, #BIT2 -+#else -+ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) -+ tst r6, #BIT5 -+#endif -+ beq loop_11 -+ -+ /* Wait for status TWSI_ADDR_PLUS_READ_BIT_TRA_ACK_REC = 0x40 */ -+loop_12: -+ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) -+ cmp r6, #0x40 -+ bne loop_12 -+ -+ /* Clear the interrupt flag and the Acknoledge bit */ -+ bl _twsiDelay -+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) -+ bic r6, r6, #(TWSI_CONTROL_INT_FLAG_SET | TWSI_CONTROL_ACK) -+ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) -+ bl _twsiDelay -+ -+ /* Wait for the interrupt flag (bit3) to be set */ -+loop_14: -+#ifdef MV78XX0 -+ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) -+ tst r6, #BIT2 -+#else -+ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) -+ tst r6, #BIT5 -+#endif -+ beq loop_14 -+ -+ /* Wait for status TWSI_MAS_REC_READ_DATA_ACK_NOT_TRA = 0x58 */ -+loop_15: -+ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) -+ cmp r6, #0x58 -+ bne loop_15 -+ -+ /* Store the data in r7. */ -+ MV_REG_READ_ASM (r7, r1, TWSI_DATA_REG(I2C_CH)) -+ -+ /* Generate stop bit */ -+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) -+ orr r6, r6, #TWSI_CONTROL_STOP_BIT -+ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) -+ -+ -+ /* Clear the interrupt flag */ -+ bl _twsiDelay -+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) -+ bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET -+ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) -+ bl _twsiDelay -+ -+ /* Wait for the stop bit to be reset by HW */ -+loop_16: -+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) -+ tst r6, #TWSI_CONTROL_INT_FLAG_SET -+ bne loop_16 -+ -+exit_i2cRead: -+ mov PC, r9 /* r9 is saved link register */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiSpec.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiSpec.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiSpec.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiSpec.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,160 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+/****************************************/ -+/* TWSI Registers */ -+/****************************************/ -+#ifndef __INCmvTwsiSpech -+#define __INCmvTwsiSpech -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* defines */ -+#define TWSI_SLAVE_ADDR_REG(chanNum) (TWSI_SLAVE_BASE(chanNum)+ 0x00) -+ -+#define TWSI_SLAVE_ADDR_GCE_ENA BIT0 -+#define TWSI_SLAVE_ADDR_7BIT_OFFS 0x1 -+#define TWSI_SLAVE_ADDR_7BIT_MASK (0xFF << TWSI_SLAVE_ADDR_7BIT_OFFS) -+#define TWSI_SLAVE_ADDR_10BIT_OFFS 0x7 -+#define TWSI_SLAVE_ADDR_10BIT_MASK 0x300 -+#define TWSI_SLAVE_ADDR_10BIT_CONST 0xF0 -+ -+ -+#define TWSI_EXTENDED_SLAVE_ADDR_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x10) -+#define TWSI_EXTENDED_SLAVE_OFFS 0 -+#define TWSI_EXTENDED_SLAVE_MASK (0xFF << TWSI_EXTENDED_SLAVE_OFFS) -+ -+ -+#define TWSI_DATA_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x04) -+#define TWSI_DATA_COMMAND_OFFS 0x0 -+#define TWSI_DATA_COMMAND_MASK (0x1 << TWSI_DATA_COMMAND_OFFS) -+#define TWSI_DATA_COMMAND_WR (0x1 << TWSI_DATA_COMMAND_OFFS) -+#define TWSI_DATA_COMMAND_RD (0x0 << TWSI_DATA_COMMAND_OFFS) -+#define TWSI_DATA_ADDR_7BIT_OFFS 0x1 -+#define TWSI_DATA_ADDR_7BIT_MASK (0xFF << TWSI_DATA_ADDR_7BIT_OFFS) -+#define TWSI_DATA_ADDR_10BIT_OFFS 0x7 -+#define TWSI_DATA_ADDR_10BIT_MASK 0x300 -+#define TWSI_DATA_ADDR_10BIT_CONST 0xF0 -+ -+ -+#define TWSI_CONTROL_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x08) -+#define TWSI_CONTROL_ACK BIT2 -+#define TWSI_CONTROL_INT_FLAG_SET BIT3 -+#define TWSI_CONTROL_STOP_BIT BIT4 -+#define TWSI_CONTROL_START_BIT BIT5 -+#define TWSI_CONTROL_ENA BIT6 -+#define TWSI_CONTROL_INT_ENA BIT7 -+ -+ -+#define TWSI_STATUS_BAUDE_RATE_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x0c) -+#define TWSI_BAUD_RATE_N_OFFS 0 -+#define TWSI_BAUD_RATE_N_MASK (0x7 << TWSI_BAUD_RATE_N_OFFS) -+#define TWSI_BAUD_RATE_M_OFFS 3 -+#define TWSI_BAUD_RATE_M_MASK (0xF << TWSI_BAUD_RATE_M_OFFS) -+ -+#define TWSI_SOFT_RESET_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x1c) -+ -+/* defines */ -+#define TWSI_TIMEOUT_VALUE 0x500 -+ -+/* TWSI status codes */ -+#define TWSI_BUS_ERROR 0x00 -+#define TWSI_START_CON_TRA 0x08 -+#define TWSI_REPEATED_START_CON_TRA 0x10 -+#define TWSI_AD_PLS_WR_BIT_TRA_ACK_REC 0x18 -+#define TWSI_AD_PLS_WR_BIT_TRA_ACK_NOT_REC 0x20 -+#define TWSI_M_TRAN_DATA_BYTE_ACK_REC 0x28 -+#define TWSI_M_TRAN_DATA_BYTE_ACK_NOT_REC 0x30 -+#define TWSI_M_LOST_ARB_DUR_AD_OR_DATA_TRA 0x38 -+#define TWSI_AD_PLS_RD_BIT_TRA_ACK_REC 0x40 -+#define TWSI_AD_PLS_RD_BIT_TRA_ACK_NOT_REC 0x48 -+#define TWSI_M_REC_RD_DATA_ACK_TRA 0x50 -+#define TWSI_M_REC_RD_DATA_ACK_NOT_TRA 0x58 -+#define TWSI_SLA_REC_AD_PLS_WR_BIT_ACK_TRA 0x60 -+#define TWSI_M_LOST_ARB_DUR_AD_TRA_AD_IS_TRGT_TO_SLA_ACK_TRA_W 0x68 -+#define TWSI_GNL_CALL_REC_ACK_TRA 0x70 -+#define TWSI_M_LOST_ARB_DUR_AD_TRA_GNL_CALL_AD_REC_ACK_TRA 0x78 -+#define TWSI_SLA_REC_WR_DATA_AF_REC_SLA_AD_ACK_TRAN 0x80 -+#define TWSI_SLA_REC_WR_DATA_AF_REC_SLA_AD_ACK_NOT_TRAN 0x88 -+#define TWSI_SLA_REC_WR_DATA_AF_REC_GNL_CALL_ACK_TRAN 0x90 -+#define TWSI_SLA_REC_WR_DATA_AF_REC_GNL_CALL_ACK_NOT_TRAN 0x98 -+#define TWSI_SLA_REC_STOP_OR_REPEATED_STRT_CON 0xA0 -+#define TWSI_SLA_REC_AD_PLS_RD_BIT_ACK_TRA 0xA8 -+#define TWSI_M_LOST_ARB_DUR_AD_TRA_AD_IS_TRGT_TO_SLA_ACK_TRA_R 0xB0 -+#define TWSI_SLA_TRA_RD_DATA_ACK_REC 0xB8 -+#define TWSI_SLA_TRA_RD_DATA_ACK_NOT_REC 0xC0 -+#define TWSI_SLA_TRA_LAST_RD_DATA_ACK_REC 0xC8 -+#define TWSI_SEC_AD_PLS_WR_BIT_TRA_ACK_REC 0xD0 -+#define TWSI_SEC_AD_PLS_WR_BIT_TRA_ACK_NOT_REC 0xD8 -+#define TWSI_SEC_AD_PLS_RD_BIT_TRA_ACK_REC 0xE0 -+#define TWSI_SEC_AD_PLS_RD_BIT_TRA_ACK_NOT_REC 0xE8 -+#define TWSI_NO_REL_STS_INT_FLAG_IS_KEPT_0 0xF8 -+ -+ -+#ifdef __cplusplus -+} -+#endif /* __cplusplus */ -+ -+#endif /* __INCmvTwsiSpech */ -diff -Nur linux-3.0.4.orig/crypto/ocf/ocf-bench.c linux-3.0.4/crypto/ocf/ocf-bench.c ---- linux-3.0.4.orig/crypto/ocf/ocf-bench.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/ocf-bench.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,514 @@ -+/* -+ * A loadable module that benchmarks the OCF crypto speed from kernel space. -+ * -+ * Copyright (C) 2004-2010 David McCullough -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * ALTERNATIVELY, provided that this notice is retained in full, this product -+ * may be distributed under the terms of the GNU General Public License (GPL), -+ * in which case the provisions of the GPL apply INSTEAD OF those given above. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ */ -+ -+ -+#include -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#ifdef I_HAVE_AN_XSCALE_WITH_INTEL_SDK -+#define BENCH_IXP_ACCESS_LIB 1 -+#endif -+#ifdef BENCH_IXP_ACCESS_LIB -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#endif -+ -+/* -+ * support for access lib version 1.4 -+ */ -+#ifndef IX_MBUF_PRIV -+#define IX_MBUF_PRIV(x) ((x)->priv) -+#endif -+ -+/* -+ * the number of simultaneously active requests -+ */ -+static int request_q_len = 40; -+module_param(request_q_len, int, 0); -+MODULE_PARM_DESC(request_q_len, "Number of outstanding requests"); -+ -+/* -+ * how many requests we want to have processed -+ */ -+static int request_num = 1024; -+module_param(request_num, int, 0); -+MODULE_PARM_DESC(request_num, "run for at least this many requests"); -+ -+/* -+ * the size of each request -+ */ -+static int request_size = 1488; -+module_param(request_size, int, 0); -+MODULE_PARM_DESC(request_size, "size of each request"); -+ -+/* -+ * OCF batching of requests -+ */ -+static int request_batch = 1; -+module_param(request_batch, int, 0); -+MODULE_PARM_DESC(request_batch, "enable OCF request batching"); -+ -+/* -+ * OCF immediate callback on completion -+ */ -+static int request_cbimm = 1; -+module_param(request_cbimm, int, 0); -+MODULE_PARM_DESC(request_cbimm, "enable OCF immediate callback on completion"); -+ -+/* -+ * a structure for each request -+ */ -+typedef struct { -+ struct work_struct work; -+#ifdef BENCH_IXP_ACCESS_LIB -+ IX_MBUF mbuf; -+#endif -+ unsigned char *buffer; -+} request_t; -+ -+static request_t *requests; -+ -+static spinlock_t ocfbench_counter_lock; -+static int outstanding; -+static int total; -+ -+/*************************************************************************/ -+/* -+ * OCF benchmark routines -+ */ -+ -+static uint64_t ocf_cryptoid; -+static unsigned long jstart, jstop; -+ -+static int ocf_init(void); -+static int ocf_cb(struct cryptop *crp); -+static void ocf_request(void *arg); -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void ocf_request_wq(struct work_struct *work); -+#endif -+ -+static int -+ocf_init(void) -+{ -+ int error; -+ struct cryptoini crie, cria; -+ struct cryptodesc crda, crde; -+ -+ memset(&crie, 0, sizeof(crie)); -+ memset(&cria, 0, sizeof(cria)); -+ memset(&crde, 0, sizeof(crde)); -+ memset(&crda, 0, sizeof(crda)); -+ -+ cria.cri_alg = CRYPTO_SHA1_HMAC; -+ cria.cri_klen = 20 * 8; -+ cria.cri_key = "0123456789abcdefghij"; -+ -+ //crie.cri_alg = CRYPTO_3DES_CBC; -+ crie.cri_alg = CRYPTO_AES_CBC; -+ crie.cri_klen = 24 * 8; -+ crie.cri_key = "0123456789abcdefghijklmn"; -+ -+ crie.cri_next = &cria; -+ -+ error = crypto_newsession(&ocf_cryptoid, &crie, -+ CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE); -+ if (error) { -+ printk("crypto_newsession failed %d\n", error); -+ return -1; -+ } -+ return 0; -+} -+ -+static int -+ocf_cb(struct cryptop *crp) -+{ -+ request_t *r = (request_t *) crp->crp_opaque; -+ unsigned long flags; -+ -+ if (crp->crp_etype) -+ printk("Error in OCF processing: %d\n", crp->crp_etype); -+ crypto_freereq(crp); -+ crp = NULL; -+ -+ /* do all requests but take at least 1 second */ -+ spin_lock_irqsave(&ocfbench_counter_lock, flags); -+ total++; -+ if (total > request_num && jstart + HZ < jiffies) { -+ outstanding--; -+ spin_unlock_irqrestore(&ocfbench_counter_lock, flags); -+ return 0; -+ } -+ spin_unlock_irqrestore(&ocfbench_counter_lock, flags); -+ -+ schedule_work(&r->work); -+ return 0; -+} -+ -+ -+static void -+ocf_request(void *arg) -+{ -+ request_t *r = arg; -+ struct cryptop *crp = crypto_getreq(2); -+ struct cryptodesc *crde, *crda; -+ unsigned long flags; -+ -+ if (!crp) { -+ spin_lock_irqsave(&ocfbench_counter_lock, flags); -+ outstanding--; -+ spin_unlock_irqrestore(&ocfbench_counter_lock, flags); -+ return; -+ } -+ -+ crde = crp->crp_desc; -+ crda = crde->crd_next; -+ -+ crda->crd_skip = 0; -+ crda->crd_flags = 0; -+ crda->crd_len = request_size; -+ crda->crd_inject = request_size; -+ crda->crd_alg = CRYPTO_SHA1_HMAC; -+ crda->crd_key = "0123456789abcdefghij"; -+ crda->crd_klen = 20 * 8; -+ -+ crde->crd_skip = 0; -+ crde->crd_flags = CRD_F_IV_EXPLICIT | CRD_F_ENCRYPT; -+ crde->crd_len = request_size; -+ crde->crd_inject = request_size; -+ //crde->crd_alg = CRYPTO_3DES_CBC; -+ crde->crd_alg = CRYPTO_AES_CBC; -+ crde->crd_key = "0123456789abcdefghijklmn"; -+ crde->crd_klen = 24 * 8; -+ -+ crp->crp_ilen = request_size + 64; -+ crp->crp_flags = 0; -+ if (request_batch) -+ crp->crp_flags |= CRYPTO_F_BATCH; -+ if (request_cbimm) -+ crp->crp_flags |= CRYPTO_F_CBIMM; -+ crp->crp_buf = (caddr_t) r->buffer; -+ crp->crp_callback = ocf_cb; -+ crp->crp_sid = ocf_cryptoid; -+ crp->crp_opaque = (caddr_t) r; -+ crypto_dispatch(crp); -+} -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void -+ocf_request_wq(struct work_struct *work) -+{ -+ request_t *r = container_of(work, request_t, work); -+ ocf_request(r); -+} -+#endif -+ -+static void -+ocf_done(void) -+{ -+ crypto_freesession(ocf_cryptoid); -+} -+ -+/*************************************************************************/ -+#ifdef BENCH_IXP_ACCESS_LIB -+/*************************************************************************/ -+/* -+ * CryptoAcc benchmark routines -+ */ -+ -+static IxCryptoAccCtx ixp_ctx; -+static UINT32 ixp_ctx_id; -+static IX_MBUF ixp_pri; -+static IX_MBUF ixp_sec; -+static int ixp_registered = 0; -+ -+static void ixp_register_cb(UINT32 ctx_id, IX_MBUF *bufp, -+ IxCryptoAccStatus status); -+static void ixp_perform_cb(UINT32 ctx_id, IX_MBUF *sbufp, IX_MBUF *dbufp, -+ IxCryptoAccStatus status); -+static void ixp_request(void *arg); -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void ixp_request_wq(struct work_struct *work); -+#endif -+ -+static int -+ixp_init(void) -+{ -+ IxCryptoAccStatus status; -+ -+ ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_3DES; -+ ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; -+ ixp_ctx.cipherCtx.cipherKeyLen = 24; -+ ixp_ctx.cipherCtx.cipherBlockLen = IX_CRYPTO_ACC_DES_BLOCK_64; -+ ixp_ctx.cipherCtx.cipherInitialVectorLen = IX_CRYPTO_ACC_DES_IV_64; -+ memcpy(ixp_ctx.cipherCtx.key.cipherKey, "0123456789abcdefghijklmn", 24); -+ -+ ixp_ctx.authCtx.authAlgo = IX_CRYPTO_ACC_AUTH_SHA1; -+ ixp_ctx.authCtx.authDigestLen = 12; -+ ixp_ctx.authCtx.aadLen = 0; -+ ixp_ctx.authCtx.authKeyLen = 20; -+ memcpy(ixp_ctx.authCtx.key.authKey, "0123456789abcdefghij", 20); -+ -+ ixp_ctx.useDifferentSrcAndDestMbufs = 0; -+ ixp_ctx.operation = IX_CRYPTO_ACC_OP_ENCRYPT_AUTH ; -+ -+ IX_MBUF_MLEN(&ixp_pri) = IX_MBUF_PKT_LEN(&ixp_pri) = 128; -+ IX_MBUF_MDATA(&ixp_pri) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); -+ IX_MBUF_MLEN(&ixp_sec) = IX_MBUF_PKT_LEN(&ixp_sec) = 128; -+ IX_MBUF_MDATA(&ixp_sec) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); -+ -+ status = ixCryptoAccCtxRegister(&ixp_ctx, &ixp_pri, &ixp_sec, -+ ixp_register_cb, ixp_perform_cb, &ixp_ctx_id); -+ -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) { -+ while (!ixp_registered) -+ schedule(); -+ return ixp_registered < 0 ? -1 : 0; -+ } -+ -+ printk("ixp: ixCryptoAccCtxRegister failed %d\n", status); -+ return -1; -+} -+ -+static void -+ixp_register_cb(UINT32 ctx_id, IX_MBUF *bufp, IxCryptoAccStatus status) -+{ -+ if (bufp) { -+ IX_MBUF_MLEN(bufp) = IX_MBUF_PKT_LEN(bufp) = 0; -+ kfree(IX_MBUF_MDATA(bufp)); -+ IX_MBUF_MDATA(bufp) = NULL; -+ } -+ -+ if (IX_CRYPTO_ACC_STATUS_WAIT == status) -+ return; -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) -+ ixp_registered = 1; -+ else -+ ixp_registered = -1; -+} -+ -+static void -+ixp_perform_cb( -+ UINT32 ctx_id, -+ IX_MBUF *sbufp, -+ IX_MBUF *dbufp, -+ IxCryptoAccStatus status) -+{ -+ request_t *r = NULL; -+ unsigned long flags; -+ -+ /* do all requests but take at least 1 second */ -+ spin_lock_irqsave(&ocfbench_counter_lock, flags); -+ total++; -+ if (total > request_num && jstart + HZ < jiffies) { -+ outstanding--; -+ spin_unlock_irqrestore(&ocfbench_counter_lock, flags); -+ return; -+ } -+ -+ if (!sbufp || !(r = IX_MBUF_PRIV(sbufp))) { -+ printk("crappo %p %p\n", sbufp, r); -+ outstanding--; -+ spin_unlock_irqrestore(&ocfbench_counter_lock, flags); -+ return; -+ } -+ spin_unlock_irqrestore(&ocfbench_counter_lock, flags); -+ -+ schedule_work(&r->work); -+} -+ -+static void -+ixp_request(void *arg) -+{ -+ request_t *r = arg; -+ IxCryptoAccStatus status; -+ unsigned long flags; -+ -+ memset(&r->mbuf, 0, sizeof(r->mbuf)); -+ IX_MBUF_MLEN(&r->mbuf) = IX_MBUF_PKT_LEN(&r->mbuf) = request_size + 64; -+ IX_MBUF_MDATA(&r->mbuf) = r->buffer; -+ IX_MBUF_PRIV(&r->mbuf) = r; -+ status = ixCryptoAccAuthCryptPerform(ixp_ctx_id, &r->mbuf, NULL, -+ 0, request_size, 0, request_size, request_size, r->buffer); -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS != status) { -+ printk("status1 = %d\n", status); -+ spin_lock_irqsave(&ocfbench_counter_lock, flags); -+ outstanding--; -+ spin_unlock_irqrestore(&ocfbench_counter_lock, flags); -+ return; -+ } -+ return; -+} -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void -+ixp_request_wq(struct work_struct *work) -+{ -+ request_t *r = container_of(work, request_t, work); -+ ixp_request(r); -+} -+#endif -+ -+static void -+ixp_done(void) -+{ -+ /* we should free the session here but I am lazy :-) */ -+} -+ -+/*************************************************************************/ -+#endif /* BENCH_IXP_ACCESS_LIB */ -+/*************************************************************************/ -+ -+int -+ocfbench_init(void) -+{ -+ int i; -+ unsigned long mbps; -+ unsigned long flags; -+ -+ printk("Crypto Speed tests\n"); -+ -+ requests = kmalloc(sizeof(request_t) * request_q_len, GFP_KERNEL); -+ if (!requests) { -+ printk("malloc failed\n"); -+ return -EINVAL; -+ } -+ -+ for (i = 0; i < request_q_len; i++) { -+ /* +64 for return data */ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ INIT_WORK(&requests[i].work, ocf_request_wq); -+#else -+ INIT_WORK(&requests[i].work, ocf_request, &requests[i]); -+#endif -+ requests[i].buffer = kmalloc(request_size + 128, GFP_DMA); -+ if (!requests[i].buffer) { -+ printk("malloc failed\n"); -+ return -EINVAL; -+ } -+ memset(requests[i].buffer, '0' + i, request_size + 128); -+ } -+ -+ /* -+ * OCF benchmark -+ */ -+ printk("OCF: testing ...\n"); -+ if (ocf_init() == -1) -+ return -EINVAL; -+ -+ spin_lock_init(&ocfbench_counter_lock); -+ total = outstanding = 0; -+ jstart = jiffies; -+ for (i = 0; i < request_q_len; i++) { -+ spin_lock_irqsave(&ocfbench_counter_lock, flags); -+ outstanding++; -+ spin_unlock_irqrestore(&ocfbench_counter_lock, flags); -+ ocf_request(&requests[i]); -+ } -+ while (outstanding > 0) -+ schedule(); -+ jstop = jiffies; -+ -+ mbps = 0; -+ if (jstop > jstart) { -+ mbps = (unsigned long) total * (unsigned long) request_size * 8; -+ mbps /= ((jstop - jstart) * 1000) / HZ; -+ } -+ printk("OCF: %d requests of %d bytes in %d jiffies (%d.%03d Mbps)\n", -+ total, request_size, (int)(jstop - jstart), -+ ((int)mbps) / 1000, ((int)mbps) % 1000); -+ ocf_done(); -+ -+#ifdef BENCH_IXP_ACCESS_LIB -+ /* -+ * IXP benchmark -+ */ -+ printk("IXP: testing ...\n"); -+ ixp_init(); -+ total = outstanding = 0; -+ jstart = jiffies; -+ for (i = 0; i < request_q_len; i++) { -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ INIT_WORK(&requests[i].work, ixp_request_wq); -+#else -+ INIT_WORK(&requests[i].work, ixp_request, &requests[i]); -+#endif -+ spin_lock_irqsave(&ocfbench_counter_lock, flags); -+ outstanding++; -+ spin_unlock_irqrestore(&ocfbench_counter_lock, flags); -+ ixp_request(&requests[i]); -+ } -+ while (outstanding > 0) -+ schedule(); -+ jstop = jiffies; -+ -+ mbps = 0; -+ if (jstop > jstart) { -+ mbps = (unsigned long) total * (unsigned long) request_size * 8; -+ mbps /= ((jstop - jstart) * 1000) / HZ; -+ } -+ printk("IXP: %d requests of %d bytes in %d jiffies (%d.%03d Mbps)\n", -+ total, request_size, jstop - jstart, -+ ((int)mbps) / 1000, ((int)mbps) % 1000); -+ ixp_done(); -+#endif /* BENCH_IXP_ACCESS_LIB */ -+ -+ for (i = 0; i < request_q_len; i++) -+ kfree(requests[i].buffer); -+ kfree(requests); -+ return -EINVAL; /* always fail to load so it can be re-run quickly ;-) */ -+} -+ -+static void __exit ocfbench_exit(void) -+{ -+} -+ -+module_init(ocfbench_init); -+module_exit(ocfbench_exit); -+ -+MODULE_LICENSE("BSD"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("Benchmark various in-kernel crypto speeds"); -diff -Nur linux-3.0.4.orig/crypto/ocf/ocf-compat.h linux-3.0.4/crypto/ocf/ocf-compat.h ---- linux-3.0.4.orig/crypto/ocf/ocf-compat.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/ocf-compat.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,365 @@ -+#ifndef _BSD_COMPAT_H_ -+#define _BSD_COMPAT_H_ 1 -+/****************************************************************************/ -+/* -+ * Provide compat routines for older linux kernels and BSD kernels -+ * -+ * Written by David McCullough -+ * Copyright (C) 2010 David McCullough -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * ALTERNATIVELY, provided that this notice is retained in full, this file -+ * may be distributed under the terms of the GNU General Public License (GPL), -+ * in which case the provisions of the GPL apply INSTEAD OF those given above. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ */ -+/****************************************************************************/ -+#ifdef __KERNEL__ -+#include -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) -+#include -+#endif -+ -+/* -+ * fake some BSD driver interface stuff specifically for OCF use -+ */ -+ -+typedef struct ocf_device *device_t; -+ -+typedef struct { -+ int (*cryptodev_newsession)(device_t dev, u_int32_t *sidp, struct cryptoini *cri); -+ int (*cryptodev_freesession)(device_t dev, u_int64_t tid); -+ int (*cryptodev_process)(device_t dev, struct cryptop *crp, int hint); -+ int (*cryptodev_kprocess)(device_t dev, struct cryptkop *krp, int hint); -+} device_method_t; -+#define DEVMETHOD(id, func) id: func -+ -+struct ocf_device { -+ char name[32]; /* the driver name */ -+ char nameunit[32]; /* the driver name + HW instance */ -+ int unit; -+ device_method_t methods; -+ void *softc; -+}; -+ -+#define CRYPTODEV_NEWSESSION(dev, sid, cri) \ -+ ((*(dev)->methods.cryptodev_newsession)(dev,sid,cri)) -+#define CRYPTODEV_FREESESSION(dev, sid) \ -+ ((*(dev)->methods.cryptodev_freesession)(dev, sid)) -+#define CRYPTODEV_PROCESS(dev, crp, hint) \ -+ ((*(dev)->methods.cryptodev_process)(dev, crp, hint)) -+#define CRYPTODEV_KPROCESS(dev, krp, hint) \ -+ ((*(dev)->methods.cryptodev_kprocess)(dev, krp, hint)) -+ -+#define device_get_name(dev) ((dev)->name) -+#define device_get_nameunit(dev) ((dev)->nameunit) -+#define device_get_unit(dev) ((dev)->unit) -+#define device_get_softc(dev) ((dev)->softc) -+ -+#define softc_device_decl \ -+ struct ocf_device _device; \ -+ device_t -+ -+#define softc_device_init(_sc, _name, _unit, _methods) \ -+ if (1) {\ -+ strncpy((_sc)->_device.name, _name, sizeof((_sc)->_device.name) - 1); \ -+ snprintf((_sc)->_device.nameunit, sizeof((_sc)->_device.name), "%s%d", _name, _unit); \ -+ (_sc)->_device.unit = _unit; \ -+ (_sc)->_device.methods = _methods; \ -+ (_sc)->_device.softc = (void *) _sc; \ -+ *(device_t *)((softc_get_device(_sc))+1) = &(_sc)->_device; \ -+ } else -+ -+#define softc_get_device(_sc) (&(_sc)->_device) -+ -+/* -+ * iomem support for 2.4 and 2.6 kernels -+ */ -+#include -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+#define ocf_iomem_t unsigned long -+ -+/* -+ * implement simple workqueue like support for older kernels -+ */ -+ -+#include -+ -+#define work_struct tq_struct -+ -+#define INIT_WORK(wp, fp, ap) \ -+ do { \ -+ (wp)->sync = 0; \ -+ (wp)->routine = (fp); \ -+ (wp)->data = (ap); \ -+ } while (0) -+ -+#define schedule_work(wp) \ -+ do { \ -+ queue_task((wp), &tq_immediate); \ -+ mark_bh(IMMEDIATE_BH); \ -+ } while (0) -+ -+#define flush_scheduled_work() run_task_queue(&tq_immediate) -+ -+#else -+#define ocf_iomem_t void __iomem * -+ -+#include -+ -+#endif -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26) -+#include -+#elif LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) -+#define files_fdtable(files) (files) -+#endif -+ -+#ifdef MODULE_PARM -+#undef module_param /* just in case */ -+#define module_param(a,b,c) MODULE_PARM(a,"i") -+#endif -+ -+#define bzero(s,l) memset(s,0,l) -+#define bcopy(s,d,l) memcpy(d,s,l) -+#define bcmp(x, y, l) memcmp(x,y,l) -+ -+#define MIN(x,y) ((x) < (y) ? (x) : (y)) -+ -+#define device_printf(dev, a...) ({ \ -+ printk("%s: ", device_get_nameunit(dev)); printk(a); \ -+ }) -+ -+#undef printf -+#define printf(fmt...) printk(fmt) -+ -+#define KASSERT(c,p) if (!(c)) { printk p ; } else -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+#define ocf_daemonize(str) \ -+ daemonize(); \ -+ spin_lock_irq(¤t->sigmask_lock); \ -+ sigemptyset(¤t->blocked); \ -+ recalc_sigpending(current); \ -+ spin_unlock_irq(¤t->sigmask_lock); \ -+ sprintf(current->comm, str); -+#else -+#define ocf_daemonize(str) daemonize(str); -+#endif -+ -+#define TAILQ_INSERT_TAIL(q,d,m) list_add_tail(&(d)->m, (q)) -+#define TAILQ_EMPTY(q) list_empty(q) -+#define TAILQ_FOREACH(v, q, m) list_for_each_entry(v, q, m) -+ -+#define read_random(p,l) get_random_bytes(p,l) -+ -+#define DELAY(x) ((x) > 2000 ? mdelay((x)/1000) : udelay(x)) -+#define strtoul simple_strtoul -+ -+#define pci_get_vendor(dev) ((dev)->vendor) -+#define pci_get_device(dev) ((dev)->device) -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+#define pci_set_consistent_dma_mask(dev, mask) (0) -+#endif -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10) -+#define pci_dma_sync_single_for_cpu pci_dma_sync_single -+#endif -+ -+#ifndef DMA_32BIT_MASK -+#define DMA_32BIT_MASK 0x00000000ffffffffULL -+#endif -+ -+#ifndef htole32 -+#define htole32(x) cpu_to_le32(x) -+#endif -+#ifndef htobe32 -+#define htobe32(x) cpu_to_be32(x) -+#endif -+#ifndef htole16 -+#define htole16(x) cpu_to_le16(x) -+#endif -+#ifndef htobe16 -+#define htobe16(x) cpu_to_be16(x) -+#endif -+ -+/* older kernels don't have these */ -+ -+#include -+#if !defined(IRQ_NONE) && !defined(IRQ_RETVAL) -+#define IRQ_NONE -+#define IRQ_HANDLED -+#define IRQ_WAKE_THREAD -+#define IRQ_RETVAL -+#define irqreturn_t void -+typedef irqreturn_t (*irq_handler_t)(int irq, void *arg, struct pt_regs *regs); -+#endif -+#ifndef IRQF_SHARED -+#define IRQF_SHARED SA_SHIRQ -+#endif -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) -+# define strlcpy(dest,src,len) \ -+ ({strncpy(dest,src,(len)-1); ((char *)dest)[(len)-1] = '\0'; }) -+#endif -+ -+#ifndef MAX_ERRNO -+#define MAX_ERRNO 4095 -+#endif -+#ifndef IS_ERR_VALUE -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,5) -+#include -+#endif -+#ifndef IS_ERR_VALUE -+#define IS_ERR_VALUE(x) ((unsigned long)(x) >= (unsigned long)-MAX_ERRNO) -+#endif -+#endif -+ -+/* -+ * common debug for all -+ */ -+#if 1 -+#define dprintk(a...) do { if (debug) printk(a); } while(0) -+#else -+#define dprintk(a...) -+#endif -+ -+#ifndef SLAB_ATOMIC -+/* Changed in 2.6.20, must use GFP_ATOMIC now */ -+#define SLAB_ATOMIC GFP_ATOMIC -+#endif -+ -+/* -+ * need some additional support for older kernels */ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,2) -+#define pci_register_driver_compat(driver, rc) \ -+ do { \ -+ if ((rc) > 0) { \ -+ (rc) = 0; \ -+ } else if (rc == 0) { \ -+ (rc) = -ENODEV; \ -+ } else { \ -+ pci_unregister_driver(driver); \ -+ } \ -+ } while (0) -+#elif LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10) -+#define pci_register_driver_compat(driver,rc) ((rc) = (rc) < 0 ? (rc) : 0) -+#else -+#define pci_register_driver_compat(driver,rc) -+#endif -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) -+ -+#include -+#include -+ -+static inline void sg_set_page(struct scatterlist *sg, struct page *page, -+ unsigned int len, unsigned int offset) -+{ -+ sg->page = page; -+ sg->offset = offset; -+ sg->length = len; -+} -+ -+static inline void *sg_virt(struct scatterlist *sg) -+{ -+ return page_address(sg->page) + sg->offset; -+} -+ -+#define sg_init_table(sg, n) -+ -+#endif -+ -+#ifndef late_initcall -+#define late_initcall(init) module_init(init) -+#endif -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,4) || !defined(CONFIG_SMP) -+#define ocf_for_each_cpu(cpu) for ((cpu) = 0; (cpu) == 0; (cpu)++) -+#else -+#define ocf_for_each_cpu(cpu) for_each_present_cpu(cpu) -+#endif -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) -+#include -+#define kill_proc(p,s,v) send_sig(s,find_task_by_vpid(p),0) -+#endif -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,4) -+ -+struct ocf_thread { -+ struct task_struct *task; -+ int (*func)(void *arg); -+ void *arg; -+}; -+ -+/* thread startup helper func */ -+static inline int ocf_run_thread(void *arg) -+{ -+ struct ocf_thread *t = (struct ocf_thread *) arg; -+ if (!t) -+ return -1; /* very bad */ -+ t->task = current; -+ daemonize(); -+ spin_lock_irq(¤t->sigmask_lock); -+ sigemptyset(¤t->blocked); -+ recalc_sigpending(current); -+ spin_unlock_irq(¤t->sigmask_lock); -+ return (*t->func)(t->arg); -+} -+ -+#define kthread_create(f,a,fmt...) \ -+ ({ \ -+ struct ocf_thread t; \ -+ pid_t p; \ -+ t.task = NULL; \ -+ t.func = (f); \ -+ t.arg = (a); \ -+ p = kernel_thread(ocf_run_thread, &t, CLONE_FS|CLONE_FILES); \ -+ while (p != (pid_t) -1 && t.task == NULL) \ -+ schedule(); \ -+ if (t.task) \ -+ snprintf(t.task->comm, sizeof(t.task->comm), fmt); \ -+ (t.task); \ -+ }) -+ -+#define kthread_bind(t,cpu) /**/ -+ -+#define kthread_should_stop() (strcmp(current->comm, "stopping") == 0) -+ -+#define kthread_stop(t) \ -+ ({ \ -+ strcpy((t)->comm, "stopping"); \ -+ kill_proc((t)->pid, SIGTERM, 1); \ -+ do { \ -+ schedule(); \ -+ } while (kill_proc((t)->pid, SIGTERM, 1) == 0); \ -+ }) -+ -+#else -+#include -+#endif -+ -+#endif /* __KERNEL__ */ -+ -+/****************************************************************************/ -+#endif /* _BSD_COMPAT_H_ */ -diff -Nur linux-3.0.4.orig/crypto/ocf/ocfnull/Makefile linux-3.0.4/crypto/ocf/ocfnull/Makefile ---- linux-3.0.4.orig/crypto/ocf/ocfnull/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/ocfnull/Makefile 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,12 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+obj-$(CONFIG_OCF_OCFNULL) += ocfnull.o -+ -+obj ?= . -+EXTRA_CFLAGS += -I$(obj)/.. -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/ocfnull/ocfnull.c linux-3.0.4/crypto/ocf/ocfnull/ocfnull.c ---- linux-3.0.4.orig/crypto/ocf/ocfnull/ocfnull.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/ocfnull/ocfnull.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,204 @@ -+/* -+ * An OCF module for determining the cost of crypto versus the cost of -+ * IPSec processing outside of OCF. This modules gives us the effect of -+ * zero cost encryption, of course you will need to run it at both ends -+ * since it does no crypto at all. -+ * -+ * Written by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * ALTERNATIVELY, provided that this notice is retained in full, this product -+ * may be distributed under the terms of the GNU General Public License (GPL), -+ * in which case the provisions of the GPL apply INSTEAD OF those given above. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ */ -+ -+#include -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+static int32_t null_id = -1; -+static u_int32_t null_sesnum = 0; -+ -+static int null_process(device_t, struct cryptop *, int); -+static int null_newsession(device_t, u_int32_t *, struct cryptoini *); -+static int null_freesession(device_t, u_int64_t); -+ -+#define debug ocfnull_debug -+int ocfnull_debug = 0; -+module_param(ocfnull_debug, int, 0644); -+MODULE_PARM_DESC(ocfnull_debug, "Enable debug"); -+ -+/* -+ * dummy device structure -+ */ -+ -+static struct { -+ softc_device_decl sc_dev; -+} nulldev; -+ -+static device_method_t null_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, null_newsession), -+ DEVMETHOD(cryptodev_freesession,null_freesession), -+ DEVMETHOD(cryptodev_process, null_process), -+}; -+ -+/* -+ * Generate a new software session. -+ */ -+static int -+null_newsession(device_t arg, u_int32_t *sid, struct cryptoini *cri) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid == NULL || cri == NULL) { -+ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ if (null_sesnum == 0) -+ null_sesnum++; -+ *sid = null_sesnum++; -+ return 0; -+} -+ -+ -+/* -+ * Free a session. -+ */ -+static int -+null_freesession(device_t arg, u_int64_t tid) -+{ -+ u_int32_t sid = CRYPTO_SESID2LID(tid); -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid > null_sesnum) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ /* Silently accept and return */ -+ if (sid == 0) -+ return 0; -+ return 0; -+} -+ -+ -+/* -+ * Process a request. -+ */ -+static int -+null_process(device_t arg, struct cryptop *crp, int hint) -+{ -+ unsigned int lid; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ /* Sanity check */ -+ if (crp == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ crp->crp_etype = 0; -+ -+ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ /* -+ * find the session we are using -+ */ -+ -+ lid = crp->crp_sid & 0xffffffff; -+ if (lid >= null_sesnum || lid == 0) { -+ crp->crp_etype = ENOENT; -+ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); -+ goto done; -+ } -+ -+done: -+ crypto_done(crp); -+ return 0; -+} -+ -+ -+/* -+ * our driver startup and shutdown routines -+ */ -+ -+static int -+null_init(void) -+{ -+ dprintk("%s(%p)\n", __FUNCTION__, null_init); -+ -+ memset(&nulldev, 0, sizeof(nulldev)); -+ softc_device_init(&nulldev, "ocfnull", 0, null_methods); -+ -+ null_id = crypto_get_driverid(softc_get_device(&nulldev), -+ CRYPTOCAP_F_HARDWARE); -+ if (null_id < 0) -+ panic("ocfnull: crypto device cannot initialize!"); -+ -+#define REGISTER(alg) \ -+ crypto_register(null_id,alg,0,0) -+ REGISTER(CRYPTO_DES_CBC); -+ REGISTER(CRYPTO_3DES_CBC); -+ REGISTER(CRYPTO_RIJNDAEL128_CBC); -+ REGISTER(CRYPTO_MD5); -+ REGISTER(CRYPTO_SHA1); -+ REGISTER(CRYPTO_MD5_HMAC); -+ REGISTER(CRYPTO_SHA1_HMAC); -+#undef REGISTER -+ -+ return 0; -+} -+ -+static void -+null_exit(void) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ crypto_unregister_all(null_id); -+ null_id = -1; -+} -+ -+module_init(null_init); -+module_exit(null_exit); -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("ocfnull - claims a lot but does nothing"); -diff -Nur linux-3.0.4.orig/crypto/ocf/pasemi/Makefile linux-3.0.4/crypto/ocf/pasemi/Makefile ---- linux-3.0.4.orig/crypto/ocf/pasemi/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/pasemi/Makefile 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,12 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+obj-$(CONFIG_OCF_PASEMI) += pasemi.o -+ -+obj ?= . -+EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/pasemi/pasemi.c linux-3.0.4/crypto/ocf/pasemi/pasemi.c ---- linux-3.0.4.orig/crypto/ocf/pasemi/pasemi.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/pasemi/pasemi.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,1007 @@ -+/* -+ * Copyright (C) 2007 PA Semi, Inc -+ * -+ * Driver for the PA Semi PWRficient DMA Crypto Engine -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "pasemi_fnu.h" -+ -+#define DRV_NAME "pasemi" -+ -+#define TIMER_INTERVAL 1000 -+ -+static void __devexit pasemi_dma_remove(struct pci_dev *pdev); -+static struct pasdma_status volatile * dma_status; -+ -+static int debug; -+module_param(debug, int, 0644); -+MODULE_PARM_DESC(debug, "Enable debug"); -+ -+static void pasemi_desc_start(struct pasemi_desc *desc, u64 hdr) -+{ -+ desc->postop = 0; -+ desc->quad[0] = hdr; -+ desc->quad_cnt = 1; -+ desc->size = 1; -+} -+ -+static void pasemi_desc_build(struct pasemi_desc *desc, u64 val) -+{ -+ desc->quad[desc->quad_cnt++] = val; -+ desc->size = (desc->quad_cnt + 1) / 2; -+} -+ -+static void pasemi_desc_hdr(struct pasemi_desc *desc, u64 hdr) -+{ -+ desc->quad[0] |= hdr; -+} -+ -+static int pasemi_desc_size(struct pasemi_desc *desc) -+{ -+ return desc->size; -+} -+ -+static void pasemi_ring_add_desc( -+ struct pasemi_fnu_txring *ring, -+ struct pasemi_desc *desc, -+ struct cryptop *crp) { -+ int i; -+ int ring_index = 2 * (ring->next_to_fill & (TX_RING_SIZE-1)); -+ -+ TX_DESC_INFO(ring, ring->next_to_fill).desc_size = desc->size; -+ TX_DESC_INFO(ring, ring->next_to_fill).desc_postop = desc->postop; -+ TX_DESC_INFO(ring, ring->next_to_fill).cf_crp = crp; -+ -+ for (i = 0; i < desc->quad_cnt; i += 2) { -+ ring_index = 2 * (ring->next_to_fill & (TX_RING_SIZE-1)); -+ ring->desc[ring_index] = desc->quad[i]; -+ ring->desc[ring_index + 1] = desc->quad[i + 1]; -+ ring->next_to_fill++; -+ } -+ -+ if (desc->quad_cnt & 1) -+ ring->desc[ring_index + 1] = 0; -+} -+ -+static void pasemi_ring_incr(struct pasemi_softc *sc, int chan_index, int incr) -+{ -+ out_le32(sc->dma_regs + PAS_DMA_TXCHAN_INCR(sc->base_chan + chan_index), -+ incr); -+} -+ -+/* -+ * Generate a new software session. -+ */ -+static int -+pasemi_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) -+{ -+ struct cryptoini *c, *encini = NULL, *macini = NULL; -+ struct pasemi_softc *sc = device_get_softc(dev); -+ struct pasemi_session *ses = NULL, **sespp; -+ int sesn, blksz = 0; -+ u64 ccmd = 0; -+ unsigned long flags; -+ struct pasemi_desc init_desc; -+ struct pasemi_fnu_txring *txring; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ if (sidp == NULL || cri == NULL || sc == NULL) { -+ DPRINTF("%s,%d - EINVAL\n", __FILE__, __LINE__); -+ return -EINVAL; -+ } -+ for (c = cri; c != NULL; c = c->cri_next) { -+ if (ALG_IS_SIG(c->cri_alg)) { -+ if (macini) -+ return -EINVAL; -+ macini = c; -+ } else if (ALG_IS_CIPHER(c->cri_alg)) { -+ if (encini) -+ return -EINVAL; -+ encini = c; -+ } else { -+ DPRINTF("UNKNOWN c->cri_alg %d\n", c->cri_alg); -+ return -EINVAL; -+ } -+ } -+ if (encini == NULL && macini == NULL) -+ return -EINVAL; -+ if (encini) { -+ /* validate key length */ -+ switch (encini->cri_alg) { -+ case CRYPTO_DES_CBC: -+ if (encini->cri_klen != 64) -+ return -EINVAL; -+ ccmd = DMA_CALGO_DES; -+ break; -+ case CRYPTO_3DES_CBC: -+ if (encini->cri_klen != 192) -+ return -EINVAL; -+ ccmd = DMA_CALGO_3DES; -+ break; -+ case CRYPTO_AES_CBC: -+ if (encini->cri_klen != 128 && -+ encini->cri_klen != 192 && -+ encini->cri_klen != 256) -+ return -EINVAL; -+ ccmd = DMA_CALGO_AES; -+ break; -+ case CRYPTO_ARC4: -+ if (encini->cri_klen != 128) -+ return -EINVAL; -+ ccmd = DMA_CALGO_ARC; -+ break; -+ default: -+ DPRINTF("UNKNOWN encini->cri_alg %d\n", -+ encini->cri_alg); -+ return -EINVAL; -+ } -+ } -+ -+ if (macini) { -+ switch (macini->cri_alg) { -+ case CRYPTO_MD5: -+ case CRYPTO_MD5_HMAC: -+ blksz = 16; -+ break; -+ case CRYPTO_SHA1: -+ case CRYPTO_SHA1_HMAC: -+ blksz = 20; -+ break; -+ default: -+ DPRINTF("UNKNOWN macini->cri_alg %d\n", -+ macini->cri_alg); -+ return -EINVAL; -+ } -+ if (((macini->cri_klen + 7) / 8) > blksz) { -+ DPRINTF("key length %d bigger than blksize %d not supported\n", -+ ((macini->cri_klen + 7) / 8), blksz); -+ return -EINVAL; -+ } -+ } -+ -+ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { -+ if (sc->sc_sessions[sesn] == NULL) { -+ sc->sc_sessions[sesn] = (struct pasemi_session *) -+ kzalloc(sizeof(struct pasemi_session), GFP_ATOMIC); -+ ses = sc->sc_sessions[sesn]; -+ break; -+ } else if (sc->sc_sessions[sesn]->used == 0) { -+ ses = sc->sc_sessions[sesn]; -+ break; -+ } -+ } -+ -+ if (ses == NULL) { -+ sespp = (struct pasemi_session **) -+ kzalloc(sc->sc_nsessions * 2 * -+ sizeof(struct pasemi_session *), GFP_ATOMIC); -+ if (sespp == NULL) -+ return -ENOMEM; -+ memcpy(sespp, sc->sc_sessions, -+ sc->sc_nsessions * sizeof(struct pasemi_session *)); -+ kfree(sc->sc_sessions); -+ sc->sc_sessions = sespp; -+ sesn = sc->sc_nsessions; -+ ses = sc->sc_sessions[sesn] = (struct pasemi_session *) -+ kzalloc(sizeof(struct pasemi_session), GFP_ATOMIC); -+ if (ses == NULL) -+ return -ENOMEM; -+ sc->sc_nsessions *= 2; -+ } -+ -+ ses->used = 1; -+ -+ ses->dma_addr = pci_map_single(sc->dma_pdev, (void *) ses->civ, -+ sizeof(struct pasemi_session), DMA_TO_DEVICE); -+ -+ /* enter the channel scheduler */ -+ spin_lock_irqsave(&sc->sc_chnlock, flags); -+ -+ /* ARC4 has to be processed by the even channel */ -+ if (encini && (encini->cri_alg == CRYPTO_ARC4)) -+ ses->chan = sc->sc_lastchn & ~1; -+ else -+ ses->chan = sc->sc_lastchn; -+ sc->sc_lastchn = (sc->sc_lastchn + 1) % sc->sc_num_channels; -+ -+ spin_unlock_irqrestore(&sc->sc_chnlock, flags); -+ -+ txring = &sc->tx[ses->chan]; -+ -+ if (encini) { -+ ses->ccmd = ccmd; -+ ses->keysz = (encini->cri_klen - 63) / 64; -+ memcpy(ses->key, encini->cri_key, (ses->keysz + 1) * 8); -+ -+ pasemi_desc_start(&init_desc, -+ XCT_CTRL_HDR(ses->chan, (encini && macini) ? 0x68 : 0x40, DMA_FN_CIV0)); -+ pasemi_desc_build(&init_desc, -+ XCT_FUN_SRC_PTR((encini && macini) ? 0x68 : 0x40, ses->dma_addr)); -+ } -+ if (macini) { -+ if (macini->cri_alg == CRYPTO_MD5_HMAC || -+ macini->cri_alg == CRYPTO_SHA1_HMAC) -+ memcpy(ses->hkey, macini->cri_key, blksz); -+ else { -+ /* Load initialization constants(RFC 1321, 3174) */ -+ ses->hiv[0] = 0x67452301efcdab89ULL; -+ ses->hiv[1] = 0x98badcfe10325476ULL; -+ ses->hiv[2] = 0xc3d2e1f000000000ULL; -+ } -+ ses->hseq = 0ULL; -+ } -+ -+ spin_lock_irqsave(&txring->fill_lock, flags); -+ -+ if (((txring->next_to_fill + pasemi_desc_size(&init_desc)) - -+ txring->next_to_clean) > TX_RING_SIZE) { -+ spin_unlock_irqrestore(&txring->fill_lock, flags); -+ return ERESTART; -+ } -+ -+ if (encini) { -+ pasemi_ring_add_desc(txring, &init_desc, NULL); -+ pasemi_ring_incr(sc, ses->chan, -+ pasemi_desc_size(&init_desc)); -+ } -+ -+ txring->sesn = sesn; -+ spin_unlock_irqrestore(&txring->fill_lock, flags); -+ -+ *sidp = PASEMI_SID(sesn); -+ return 0; -+} -+ -+/* -+ * Deallocate a session. -+ */ -+static int -+pasemi_freesession(device_t dev, u_int64_t tid) -+{ -+ struct pasemi_softc *sc = device_get_softc(dev); -+ int session; -+ u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (sc == NULL) -+ return -EINVAL; -+ session = PASEMI_SESSION(sid); -+ if (session >= sc->sc_nsessions || !sc->sc_sessions[session]) -+ return -EINVAL; -+ -+ pci_unmap_single(sc->dma_pdev, -+ sc->sc_sessions[session]->dma_addr, -+ sizeof(struct pasemi_session), DMA_TO_DEVICE); -+ memset(sc->sc_sessions[session], 0, -+ sizeof(struct pasemi_session)); -+ -+ return 0; -+} -+ -+static int -+pasemi_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ -+ int err = 0, ivsize, srclen = 0, reinit = 0, reinit_size = 0, chsel; -+ struct pasemi_softc *sc = device_get_softc(dev); -+ struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; -+ caddr_t ivp; -+ struct pasemi_desc init_desc, work_desc; -+ struct pasemi_session *ses; -+ struct sk_buff *skb; -+ struct uio *uiop; -+ unsigned long flags; -+ struct pasemi_fnu_txring *txring; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (crp == NULL || crp->crp_callback == NULL || sc == NULL) -+ return -EINVAL; -+ -+ crp->crp_etype = 0; -+ if (PASEMI_SESSION(crp->crp_sid) >= sc->sc_nsessions) -+ return -EINVAL; -+ -+ ses = sc->sc_sessions[PASEMI_SESSION(crp->crp_sid)]; -+ -+ crd1 = crp->crp_desc; -+ if (crd1 == NULL) { -+ err = -EINVAL; -+ goto errout; -+ } -+ crd2 = crd1->crd_next; -+ -+ if (ALG_IS_SIG(crd1->crd_alg)) { -+ maccrd = crd1; -+ if (crd2 == NULL) -+ enccrd = NULL; -+ else if (ALG_IS_CIPHER(crd2->crd_alg) && -+ (crd2->crd_flags & CRD_F_ENCRYPT) == 0) -+ enccrd = crd2; -+ else -+ goto erralg; -+ } else if (ALG_IS_CIPHER(crd1->crd_alg)) { -+ enccrd = crd1; -+ if (crd2 == NULL) -+ maccrd = NULL; -+ else if (ALG_IS_SIG(crd2->crd_alg) && -+ (crd1->crd_flags & CRD_F_ENCRYPT)) -+ maccrd = crd2; -+ else -+ goto erralg; -+ } else -+ goto erralg; -+ -+ chsel = ses->chan; -+ -+ txring = &sc->tx[chsel]; -+ -+ if (enccrd && !maccrd) { -+ if (enccrd->crd_alg == CRYPTO_ARC4) -+ reinit = 1; -+ reinit_size = 0x40; -+ srclen = crp->crp_ilen; -+ -+ pasemi_desc_start(&work_desc, XCT_FUN_O | XCT_FUN_I -+ | XCT_FUN_FUN(chsel)); -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) -+ pasemi_desc_hdr(&work_desc, XCT_FUN_CRM_ENC); -+ else -+ pasemi_desc_hdr(&work_desc, XCT_FUN_CRM_DEC); -+ } else if (enccrd && maccrd) { -+ if (enccrd->crd_alg == CRYPTO_ARC4) -+ reinit = 1; -+ reinit_size = 0x68; -+ -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) { -+ /* Encrypt -> Authenticate */ -+ pasemi_desc_start(&work_desc, XCT_FUN_O | XCT_FUN_I | XCT_FUN_CRM_ENC_SIG -+ | XCT_FUN_A | XCT_FUN_FUN(chsel)); -+ srclen = maccrd->crd_skip + maccrd->crd_len; -+ } else { -+ /* Authenticate -> Decrypt */ -+ pasemi_desc_start(&work_desc, XCT_FUN_O | XCT_FUN_I | XCT_FUN_CRM_SIG_DEC -+ | XCT_FUN_24BRES | XCT_FUN_FUN(chsel)); -+ pasemi_desc_build(&work_desc, 0); -+ pasemi_desc_build(&work_desc, 0); -+ pasemi_desc_build(&work_desc, 0); -+ work_desc.postop = PASEMI_CHECK_SIG; -+ srclen = crp->crp_ilen; -+ } -+ -+ pasemi_desc_hdr(&work_desc, XCT_FUN_SHL(maccrd->crd_skip / 4)); -+ pasemi_desc_hdr(&work_desc, XCT_FUN_CHL(enccrd->crd_skip - maccrd->crd_skip)); -+ } else if (!enccrd && maccrd) { -+ srclen = maccrd->crd_len; -+ -+ pasemi_desc_start(&init_desc, -+ XCT_CTRL_HDR(chsel, 0x58, DMA_FN_HKEY0)); -+ pasemi_desc_build(&init_desc, -+ XCT_FUN_SRC_PTR(0x58, ((struct pasemi_session *)ses->dma_addr)->hkey)); -+ -+ pasemi_desc_start(&work_desc, XCT_FUN_O | XCT_FUN_I | XCT_FUN_CRM_SIG -+ | XCT_FUN_A | XCT_FUN_FUN(chsel)); -+ } -+ -+ if (enccrd) { -+ switch (enccrd->crd_alg) { -+ case CRYPTO_3DES_CBC: -+ pasemi_desc_hdr(&work_desc, XCT_FUN_ALG_3DES | -+ XCT_FUN_BCM_CBC); -+ ivsize = sizeof(u64); -+ break; -+ case CRYPTO_DES_CBC: -+ pasemi_desc_hdr(&work_desc, XCT_FUN_ALG_DES | -+ XCT_FUN_BCM_CBC); -+ ivsize = sizeof(u64); -+ break; -+ case CRYPTO_AES_CBC: -+ pasemi_desc_hdr(&work_desc, XCT_FUN_ALG_AES | -+ XCT_FUN_BCM_CBC); -+ ivsize = 2 * sizeof(u64); -+ break; -+ case CRYPTO_ARC4: -+ pasemi_desc_hdr(&work_desc, XCT_FUN_ALG_ARC); -+ ivsize = 0; -+ break; -+ default: -+ printk(DRV_NAME ": unimplemented enccrd->crd_alg %d\n", -+ enccrd->crd_alg); -+ err = -EINVAL; -+ goto errout; -+ } -+ -+ ivp = (ivsize == sizeof(u64)) ? (caddr_t) &ses->civ[1] : (caddr_t) &ses->civ[0]; -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) { -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) -+ memcpy(ivp, enccrd->crd_iv, ivsize); -+ else -+ read_random(ivp, ivsize); -+ /* If IV is not present in the buffer already, it has to be copied there */ -+ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ enccrd->crd_inject, ivsize, ivp); -+ } else { -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) -+ /* IV is provided expicitly in descriptor */ -+ memcpy(ivp, enccrd->crd_iv, ivsize); -+ else -+ /* IV is provided in the packet */ -+ crypto_copydata(crp->crp_flags, crp->crp_buf, -+ enccrd->crd_inject, ivsize, -+ ivp); -+ } -+ } -+ -+ if (maccrd) { -+ switch (maccrd->crd_alg) { -+ case CRYPTO_MD5: -+ pasemi_desc_hdr(&work_desc, XCT_FUN_SIG_MD5 | -+ XCT_FUN_HSZ((crp->crp_ilen - maccrd->crd_inject) / 4)); -+ break; -+ case CRYPTO_SHA1: -+ pasemi_desc_hdr(&work_desc, XCT_FUN_SIG_SHA1 | -+ XCT_FUN_HSZ((crp->crp_ilen - maccrd->crd_inject) / 4)); -+ break; -+ case CRYPTO_MD5_HMAC: -+ pasemi_desc_hdr(&work_desc, XCT_FUN_SIG_HMAC_MD5 | -+ XCT_FUN_HSZ((crp->crp_ilen - maccrd->crd_inject) / 4)); -+ break; -+ case CRYPTO_SHA1_HMAC: -+ pasemi_desc_hdr(&work_desc, XCT_FUN_SIG_HMAC_SHA1 | -+ XCT_FUN_HSZ((crp->crp_ilen - maccrd->crd_inject) / 4)); -+ break; -+ default: -+ printk(DRV_NAME ": unimplemented maccrd->crd_alg %d\n", -+ maccrd->crd_alg); -+ err = -EINVAL; -+ goto errout; -+ } -+ } -+ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ /* using SKB buffers */ -+ skb = (struct sk_buff *)crp->crp_buf; -+ if (skb_shinfo(skb)->nr_frags) { -+ printk(DRV_NAME ": skb frags unimplemented\n"); -+ err = -EINVAL; -+ goto errout; -+ } -+ pasemi_desc_build( -+ &work_desc, -+ XCT_FUN_DST_PTR(skb->len, pci_map_single( -+ sc->dma_pdev, skb->data, -+ skb->len, DMA_TO_DEVICE))); -+ pasemi_desc_build( -+ &work_desc, -+ XCT_FUN_SRC_PTR( -+ srclen, pci_map_single( -+ sc->dma_pdev, skb->data, -+ srclen, DMA_TO_DEVICE))); -+ pasemi_desc_hdr(&work_desc, XCT_FUN_LLEN(srclen)); -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ /* using IOV buffers */ -+ uiop = (struct uio *)crp->crp_buf; -+ if (uiop->uio_iovcnt > 1) { -+ printk(DRV_NAME ": iov frags unimplemented\n"); -+ err = -EINVAL; -+ goto errout; -+ } -+ -+ /* crp_olen is never set; always use crp_ilen */ -+ pasemi_desc_build( -+ &work_desc, -+ XCT_FUN_DST_PTR(crp->crp_ilen, pci_map_single( -+ sc->dma_pdev, -+ uiop->uio_iov->iov_base, -+ crp->crp_ilen, DMA_TO_DEVICE))); -+ pasemi_desc_hdr(&work_desc, XCT_FUN_LLEN(srclen)); -+ -+ pasemi_desc_build( -+ &work_desc, -+ XCT_FUN_SRC_PTR(srclen, pci_map_single( -+ sc->dma_pdev, -+ uiop->uio_iov->iov_base, -+ srclen, DMA_TO_DEVICE))); -+ } else { -+ /* using contig buffers */ -+ pasemi_desc_build( -+ &work_desc, -+ XCT_FUN_DST_PTR(crp->crp_ilen, pci_map_single( -+ sc->dma_pdev, -+ crp->crp_buf, -+ crp->crp_ilen, DMA_TO_DEVICE))); -+ pasemi_desc_build( -+ &work_desc, -+ XCT_FUN_SRC_PTR(srclen, pci_map_single( -+ sc->dma_pdev, -+ crp->crp_buf, srclen, -+ DMA_TO_DEVICE))); -+ pasemi_desc_hdr(&work_desc, XCT_FUN_LLEN(srclen)); -+ } -+ -+ spin_lock_irqsave(&txring->fill_lock, flags); -+ -+ if (txring->sesn != PASEMI_SESSION(crp->crp_sid)) { -+ txring->sesn = PASEMI_SESSION(crp->crp_sid); -+ reinit = 1; -+ } -+ -+ if (enccrd) { -+ pasemi_desc_start(&init_desc, -+ XCT_CTRL_HDR(chsel, reinit ? reinit_size : 0x10, DMA_FN_CIV0)); -+ pasemi_desc_build(&init_desc, -+ XCT_FUN_SRC_PTR(reinit ? reinit_size : 0x10, ses->dma_addr)); -+ } -+ -+ if (((txring->next_to_fill + pasemi_desc_size(&init_desc) + -+ pasemi_desc_size(&work_desc)) - -+ txring->next_to_clean) > TX_RING_SIZE) { -+ spin_unlock_irqrestore(&txring->fill_lock, flags); -+ err = ERESTART; -+ goto errout; -+ } -+ -+ pasemi_ring_add_desc(txring, &init_desc, NULL); -+ pasemi_ring_add_desc(txring, &work_desc, crp); -+ -+ pasemi_ring_incr(sc, chsel, -+ pasemi_desc_size(&init_desc) + -+ pasemi_desc_size(&work_desc)); -+ -+ spin_unlock_irqrestore(&txring->fill_lock, flags); -+ -+ mod_timer(&txring->crypto_timer, jiffies + TIMER_INTERVAL); -+ -+ return 0; -+ -+erralg: -+ printk(DRV_NAME ": unsupported algorithm or algorithm order alg1 %d alg2 %d\n", -+ crd1->crd_alg, crd2->crd_alg); -+ err = -EINVAL; -+ -+errout: -+ if (err != ERESTART) { -+ crp->crp_etype = err; -+ crypto_done(crp); -+ } -+ return err; -+} -+ -+static int pasemi_clean_tx(struct pasemi_softc *sc, int chan) -+{ -+ int i, j, ring_idx; -+ struct pasemi_fnu_txring *ring = &sc->tx[chan]; -+ u16 delta_cnt; -+ int flags, loops = 10; -+ int desc_size; -+ struct cryptop *crp; -+ -+ spin_lock_irqsave(&ring->clean_lock, flags); -+ -+ while ((delta_cnt = (dma_status->tx_sta[sc->base_chan + chan] -+ & PAS_STATUS_PCNT_M) - ring->total_pktcnt) -+ && loops--) { -+ -+ for (i = 0; i < delta_cnt; i++) { -+ desc_size = TX_DESC_INFO(ring, ring->next_to_clean).desc_size; -+ crp = TX_DESC_INFO(ring, ring->next_to_clean).cf_crp; -+ if (crp) { -+ ring_idx = 2 * (ring->next_to_clean & (TX_RING_SIZE-1)); -+ if (TX_DESC_INFO(ring, ring->next_to_clean).desc_postop & PASEMI_CHECK_SIG) { -+ /* Need to make sure signature matched, -+ * if not - return error */ -+ if (!(ring->desc[ring_idx + 1] & (1ULL << 63))) -+ crp->crp_etype = -EINVAL; -+ } -+ crypto_done(TX_DESC_INFO(ring, -+ ring->next_to_clean).cf_crp); -+ TX_DESC_INFO(ring, ring->next_to_clean).cf_crp = NULL; -+ pci_unmap_single( -+ sc->dma_pdev, -+ XCT_PTR_ADDR_LEN(ring->desc[ring_idx + 1]), -+ PCI_DMA_TODEVICE); -+ -+ ring->desc[ring_idx] = ring->desc[ring_idx + 1] = 0; -+ -+ ring->next_to_clean++; -+ for (j = 1; j < desc_size; j++) { -+ ring_idx = 2 * -+ (ring->next_to_clean & -+ (TX_RING_SIZE-1)); -+ pci_unmap_single( -+ sc->dma_pdev, -+ XCT_PTR_ADDR_LEN(ring->desc[ring_idx]), -+ PCI_DMA_TODEVICE); -+ if (ring->desc[ring_idx + 1]) -+ pci_unmap_single( -+ sc->dma_pdev, -+ XCT_PTR_ADDR_LEN( -+ ring->desc[ -+ ring_idx + 1]), -+ PCI_DMA_TODEVICE); -+ ring->desc[ring_idx] = -+ ring->desc[ring_idx + 1] = 0; -+ ring->next_to_clean++; -+ } -+ } else { -+ for (j = 0; j < desc_size; j++) { -+ ring_idx = 2 * (ring->next_to_clean & (TX_RING_SIZE-1)); -+ ring->desc[ring_idx] = -+ ring->desc[ring_idx + 1] = 0; -+ ring->next_to_clean++; -+ } -+ } -+ } -+ -+ ring->total_pktcnt += delta_cnt; -+ } -+ spin_unlock_irqrestore(&ring->clean_lock, flags); -+ -+ return 0; -+} -+ -+static void sweepup_tx(struct pasemi_softc *sc) -+{ -+ int i; -+ -+ for (i = 0; i < sc->sc_num_channels; i++) -+ pasemi_clean_tx(sc, i); -+} -+ -+static irqreturn_t pasemi_intr(int irq, void *arg, struct pt_regs *regs) -+{ -+ struct pasemi_softc *sc = arg; -+ unsigned int reg; -+ int chan = irq - sc->base_irq; -+ int chan_index = sc->base_chan + chan; -+ u64 stat = dma_status->tx_sta[chan_index]; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (!(stat & PAS_STATUS_CAUSE_M)) -+ return IRQ_NONE; -+ -+ pasemi_clean_tx(sc, chan); -+ -+ stat = dma_status->tx_sta[chan_index]; -+ -+ reg = PAS_IOB_DMA_TXCH_RESET_PINTC | -+ PAS_IOB_DMA_TXCH_RESET_PCNT(sc->tx[chan].total_pktcnt); -+ -+ if (stat & PAS_STATUS_SOFT) -+ reg |= PAS_IOB_DMA_RXCH_RESET_SINTC; -+ -+ out_le32(sc->iob_regs + PAS_IOB_DMA_TXCH_RESET(chan_index), reg); -+ -+ -+ return IRQ_HANDLED; -+} -+ -+static int pasemi_dma_setup_tx_resources(struct pasemi_softc *sc, int chan) -+{ -+ u32 val; -+ int chan_index = chan + sc->base_chan; -+ int ret; -+ struct pasemi_fnu_txring *ring; -+ -+ ring = &sc->tx[chan]; -+ -+ spin_lock_init(&ring->fill_lock); -+ spin_lock_init(&ring->clean_lock); -+ -+ ring->desc_info = kzalloc(sizeof(struct pasemi_desc_info) * -+ TX_RING_SIZE, GFP_KERNEL); -+ if (!ring->desc_info) -+ return -ENOMEM; -+ -+ /* Allocate descriptors */ -+ ring->desc = dma_alloc_coherent(&sc->dma_pdev->dev, -+ TX_RING_SIZE * -+ 2 * sizeof(u64), -+ &ring->dma, GFP_KERNEL); -+ if (!ring->desc) -+ return -ENOMEM; -+ -+ memset((void *) ring->desc, 0, TX_RING_SIZE * 2 * sizeof(u64)); -+ -+ out_le32(sc->iob_regs + PAS_IOB_DMA_TXCH_RESET(chan_index), 0x30); -+ -+ ring->total_pktcnt = 0; -+ -+ out_le32(sc->dma_regs + PAS_DMA_TXCHAN_BASEL(chan_index), -+ PAS_DMA_TXCHAN_BASEL_BRBL(ring->dma)); -+ -+ val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->dma >> 32); -+ val |= PAS_DMA_TXCHAN_BASEU_SIZ(TX_RING_SIZE >> 2); -+ -+ out_le32(sc->dma_regs + PAS_DMA_TXCHAN_BASEU(chan_index), val); -+ -+ out_le32(sc->dma_regs + PAS_DMA_TXCHAN_CFG(chan_index), -+ PAS_DMA_TXCHAN_CFG_TY_FUNC | -+ PAS_DMA_TXCHAN_CFG_TATTR(chan) | -+ PAS_DMA_TXCHAN_CFG_WT(2)); -+ -+ /* enable tx channel */ -+ out_le32(sc->dma_regs + -+ PAS_DMA_TXCHAN_TCMDSTA(chan_index), -+ PAS_DMA_TXCHAN_TCMDSTA_EN); -+ -+ out_le32(sc->iob_regs + PAS_IOB_DMA_TXCH_CFG(chan_index), -+ PAS_IOB_DMA_TXCH_CFG_CNTTH(1000)); -+ -+ ring->next_to_fill = 0; -+ ring->next_to_clean = 0; -+ -+ snprintf(ring->irq_name, sizeof(ring->irq_name), -+ "%s%d", "crypto", chan); -+ -+ ring->irq = irq_create_mapping(NULL, sc->base_irq + chan); -+ ret = request_irq(ring->irq, (irq_handler_t) -+ pasemi_intr, IRQF_DISABLED, ring->irq_name, sc); -+ if (ret) { -+ printk(KERN_ERR DRV_NAME ": failed to hook irq %d ret %d\n", -+ ring->irq, ret); -+ ring->irq = -1; -+ return ret; -+ } -+ -+ setup_timer(&ring->crypto_timer, (void *) sweepup_tx, (unsigned long) sc); -+ -+ return 0; -+} -+ -+static device_method_t pasemi_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, pasemi_newsession), -+ DEVMETHOD(cryptodev_freesession, pasemi_freesession), -+ DEVMETHOD(cryptodev_process, pasemi_process), -+}; -+ -+/* Set up the crypto device structure, private data, -+ * and anything else we need before we start */ -+ -+static int __devinit -+pasemi_dma_probe(struct pci_dev *pdev, const struct pci_device_id *ent) -+{ -+ struct pasemi_softc *sc; -+ int ret, i; -+ -+ DPRINTF(KERN_ERR "%s()\n", __FUNCTION__); -+ -+ sc = kzalloc(sizeof(*sc), GFP_KERNEL); -+ if (!sc) -+ return -ENOMEM; -+ -+ softc_device_init(sc, DRV_NAME, 1, pasemi_methods); -+ -+ pci_set_drvdata(pdev, sc); -+ -+ spin_lock_init(&sc->sc_chnlock); -+ -+ sc->sc_sessions = (struct pasemi_session **) -+ kzalloc(PASEMI_INITIAL_SESSIONS * -+ sizeof(struct pasemi_session *), GFP_ATOMIC); -+ if (sc->sc_sessions == NULL) { -+ ret = -ENOMEM; -+ goto out; -+ } -+ -+ sc->sc_nsessions = PASEMI_INITIAL_SESSIONS; -+ sc->sc_lastchn = 0; -+ sc->base_irq = pdev->irq + 6; -+ sc->base_chan = 6; -+ sc->sc_cid = -1; -+ sc->dma_pdev = pdev; -+ -+ sc->iob_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL); -+ if (!sc->iob_pdev) { -+ dev_err(&pdev->dev, "Can't find I/O Bridge\n"); -+ ret = -ENODEV; -+ goto out; -+ } -+ -+ /* This is hardcoded and ugly, but we have some firmware versions -+ * who don't provide the register space in the device tree. Luckily -+ * they are at well-known locations so we can just do the math here. -+ */ -+ sc->dma_regs = -+ ioremap(0xe0000000 + (sc->dma_pdev->devfn << 12), 0x2000); -+ sc->iob_regs = -+ ioremap(0xe0000000 + (sc->iob_pdev->devfn << 12), 0x2000); -+ if (!sc->dma_regs || !sc->iob_regs) { -+ dev_err(&pdev->dev, "Can't map registers\n"); -+ ret = -ENODEV; -+ goto out; -+ } -+ -+ dma_status = __ioremap(0xfd800000, 0x1000, 0); -+ if (!dma_status) { -+ ret = -ENODEV; -+ dev_err(&pdev->dev, "Can't map dmastatus space\n"); -+ goto out; -+ } -+ -+ sc->tx = (struct pasemi_fnu_txring *) -+ kzalloc(sizeof(struct pasemi_fnu_txring) -+ * 8, GFP_KERNEL); -+ if (!sc->tx) { -+ ret = -ENOMEM; -+ goto out; -+ } -+ -+ /* Initialize the h/w */ -+ out_le32(sc->dma_regs + PAS_DMA_COM_CFG, -+ (in_le32(sc->dma_regs + PAS_DMA_COM_CFG) | -+ PAS_DMA_COM_CFG_FWF)); -+ out_le32(sc->dma_regs + PAS_DMA_COM_TXCMD, PAS_DMA_COM_TXCMD_EN); -+ -+ for (i = 0; i < PASEMI_FNU_CHANNELS; i++) { -+ sc->sc_num_channels++; -+ ret = pasemi_dma_setup_tx_resources(sc, i); -+ if (ret) -+ goto out; -+ } -+ -+ sc->sc_cid = crypto_get_driverid(softc_get_device(sc), -+ CRYPTOCAP_F_HARDWARE); -+ if (sc->sc_cid < 0) { -+ printk(KERN_ERR DRV_NAME ": could not get crypto driver id\n"); -+ ret = -ENXIO; -+ goto out; -+ } -+ -+ /* register algorithms with the framework */ -+ printk(DRV_NAME ":"); -+ -+ crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); -+ -+ return 0; -+ -+out: -+ pasemi_dma_remove(pdev); -+ return ret; -+} -+ -+#define MAX_RETRIES 5000 -+ -+static void pasemi_free_tx_resources(struct pasemi_softc *sc, int chan) -+{ -+ struct pasemi_fnu_txring *ring = &sc->tx[chan]; -+ int chan_index = chan + sc->base_chan; -+ int retries; -+ u32 stat; -+ -+ /* Stop the channel */ -+ out_le32(sc->dma_regs + -+ PAS_DMA_TXCHAN_TCMDSTA(chan_index), -+ PAS_DMA_TXCHAN_TCMDSTA_ST); -+ -+ for (retries = 0; retries < MAX_RETRIES; retries++) { -+ stat = in_le32(sc->dma_regs + -+ PAS_DMA_TXCHAN_TCMDSTA(chan_index)); -+ if (!(stat & PAS_DMA_TXCHAN_TCMDSTA_ACT)) -+ break; -+ cond_resched(); -+ } -+ -+ if (stat & PAS_DMA_TXCHAN_TCMDSTA_ACT) -+ dev_err(&sc->dma_pdev->dev, "Failed to stop tx channel %d\n", -+ chan_index); -+ -+ /* Disable the channel */ -+ out_le32(sc->dma_regs + -+ PAS_DMA_TXCHAN_TCMDSTA(chan_index), -+ 0); -+ -+ if (ring->desc_info) -+ kfree((void *) ring->desc_info); -+ if (ring->desc) -+ dma_free_coherent(&sc->dma_pdev->dev, -+ TX_RING_SIZE * -+ 2 * sizeof(u64), -+ (void *) ring->desc, ring->dma); -+ if (ring->irq != -1) -+ free_irq(ring->irq, sc); -+ -+ del_timer(&ring->crypto_timer); -+} -+ -+static void __devexit pasemi_dma_remove(struct pci_dev *pdev) -+{ -+ struct pasemi_softc *sc = pci_get_drvdata(pdev); -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (sc->sc_cid >= 0) { -+ crypto_unregister_all(sc->sc_cid); -+ } -+ -+ if (sc->tx) { -+ for (i = 0; i < sc->sc_num_channels; i++) -+ pasemi_free_tx_resources(sc, i); -+ -+ kfree(sc->tx); -+ } -+ if (sc->sc_sessions) { -+ for (i = 0; i < sc->sc_nsessions; i++) -+ kfree(sc->sc_sessions[i]); -+ kfree(sc->sc_sessions); -+ } -+ if (sc->iob_pdev) -+ pci_dev_put(sc->iob_pdev); -+ if (sc->dma_regs) -+ iounmap(sc->dma_regs); -+ if (sc->iob_regs) -+ iounmap(sc->iob_regs); -+ kfree(sc); -+} -+ -+static struct pci_device_id pasemi_dma_pci_tbl[] = { -+ { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa007) }, -+}; -+ -+MODULE_DEVICE_TABLE(pci, pasemi_dma_pci_tbl); -+ -+static struct pci_driver pasemi_dma_driver = { -+ .name = "pasemi_dma", -+ .id_table = pasemi_dma_pci_tbl, -+ .probe = pasemi_dma_probe, -+ .remove = __devexit_p(pasemi_dma_remove), -+}; -+ -+static void __exit pasemi_dma_cleanup_module(void) -+{ -+ pci_unregister_driver(&pasemi_dma_driver); -+ __iounmap(dma_status); -+ dma_status = NULL; -+} -+ -+int pasemi_dma_init_module(void) -+{ -+ return pci_register_driver(&pasemi_dma_driver); -+} -+ -+module_init(pasemi_dma_init_module); -+module_exit(pasemi_dma_cleanup_module); -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_AUTHOR("Egor Martovetsky egor@pasemi.com"); -+MODULE_DESCRIPTION("OCF driver for PA Semi PWRficient DMA Crypto Engine"); -diff -Nur linux-3.0.4.orig/crypto/ocf/pasemi/pasemi_fnu.h linux-3.0.4/crypto/ocf/pasemi/pasemi_fnu.h ---- linux-3.0.4.orig/crypto/ocf/pasemi/pasemi_fnu.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/pasemi/pasemi_fnu.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,410 @@ -+/* -+ * Copyright (C) 2007 PA Semi, Inc -+ * -+ * Driver for the PA Semi PWRficient DMA Crypto Engine, soft state and -+ * hardware register layouts. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef PASEMI_FNU_H -+#define PASEMI_FNU_H -+ -+#include -+ -+#define PASEMI_SESSION(sid) ((sid) & 0xffffffff) -+#define PASEMI_SID(sesn) ((sesn) & 0xffffffff) -+#define DPRINTF(a...) if (debug) { printk(DRV_NAME ": " a); } -+ -+/* Must be a power of two */ -+#define RX_RING_SIZE 512 -+#define TX_RING_SIZE 512 -+#define TX_DESC(ring, num) ((ring)->desc[2 * (num & (TX_RING_SIZE-1))]) -+#define TX_DESC_INFO(ring, num) ((ring)->desc_info[(num) & (TX_RING_SIZE-1)]) -+#define MAX_DESC_SIZE 8 -+#define PASEMI_INITIAL_SESSIONS 10 -+#define PASEMI_FNU_CHANNELS 8 -+ -+/* DMA descriptor */ -+struct pasemi_desc { -+ u64 quad[2*MAX_DESC_SIZE]; -+ int quad_cnt; -+ int size; -+ int postop; -+}; -+ -+/* -+ * Holds per descriptor data -+ */ -+struct pasemi_desc_info { -+ int desc_size; -+ int desc_postop; -+#define PASEMI_CHECK_SIG 0x1 -+ -+ struct cryptop *cf_crp; -+}; -+ -+/* -+ * Holds per channel data -+ */ -+struct pasemi_fnu_txring { -+ volatile u64 *desc; -+ volatile struct -+ pasemi_desc_info *desc_info; -+ dma_addr_t dma; -+ struct timer_list crypto_timer; -+ spinlock_t fill_lock; -+ spinlock_t clean_lock; -+ unsigned int next_to_fill; -+ unsigned int next_to_clean; -+ u16 total_pktcnt; -+ int irq; -+ int sesn; -+ char irq_name[10]; -+}; -+ -+/* -+ * Holds data specific to a single pasemi device. -+ */ -+struct pasemi_softc { -+ softc_device_decl sc_cdev; -+ struct pci_dev *dma_pdev; /* device backpointer */ -+ struct pci_dev *iob_pdev; /* device backpointer */ -+ void __iomem *dma_regs; -+ void __iomem *iob_regs; -+ int base_irq; -+ int base_chan; -+ int32_t sc_cid; /* crypto tag */ -+ int sc_nsessions; -+ struct pasemi_session **sc_sessions; -+ int sc_num_channels;/* number of crypto channels */ -+ -+ /* pointer to the array of txring datastructures, one txring per channel */ -+ struct pasemi_fnu_txring *tx; -+ -+ /* -+ * mutual exclusion for the channel scheduler -+ */ -+ spinlock_t sc_chnlock; -+ /* last channel used, for now use round-robin to allocate channels */ -+ int sc_lastchn; -+}; -+ -+struct pasemi_session { -+ u64 civ[2]; -+ u64 keysz; -+ u64 key[4]; -+ u64 ccmd; -+ u64 hkey[4]; -+ u64 hseq; -+ u64 giv[2]; -+ u64 hiv[4]; -+ -+ int used; -+ dma_addr_t dma_addr; -+ int chan; -+}; -+ -+/* status register layout in IOB region, at 0xfd800000 */ -+struct pasdma_status { -+ u64 rx_sta[64]; -+ u64 tx_sta[20]; -+}; -+ -+#define ALG_IS_CIPHER(alg) ((alg == CRYPTO_DES_CBC) || \ -+ (alg == CRYPTO_3DES_CBC) || \ -+ (alg == CRYPTO_AES_CBC) || \ -+ (alg == CRYPTO_ARC4) || \ -+ (alg == CRYPTO_NULL_CBC)) -+ -+#define ALG_IS_SIG(alg) ((alg == CRYPTO_MD5) || \ -+ (alg == CRYPTO_MD5_HMAC) || \ -+ (alg == CRYPTO_SHA1) || \ -+ (alg == CRYPTO_SHA1_HMAC) || \ -+ (alg == CRYPTO_NULL_HMAC)) -+ -+enum { -+ PAS_DMA_COM_TXCMD = 0x100, /* Transmit Command Register */ -+ PAS_DMA_COM_TXSTA = 0x104, /* Transmit Status Register */ -+ PAS_DMA_COM_RXCMD = 0x108, /* Receive Command Register */ -+ PAS_DMA_COM_RXSTA = 0x10c, /* Receive Status Register */ -+ PAS_DMA_COM_CFG = 0x114, /* DMA Configuration Register */ -+}; -+ -+/* All these registers live in the PCI configuration space for the DMA PCI -+ * device. Use the normal PCI config access functions for them. -+ */ -+ -+#define PAS_DMA_COM_CFG_FWF 0x18000000 -+ -+#define PAS_DMA_COM_TXCMD_EN 0x00000001 /* enable */ -+#define PAS_DMA_COM_TXSTA_ACT 0x00000001 /* active */ -+#define PAS_DMA_COM_RXCMD_EN 0x00000001 /* enable */ -+#define PAS_DMA_COM_RXSTA_ACT 0x00000001 /* active */ -+ -+#define _PAS_DMA_TXCHAN_STRIDE 0x20 /* Size per channel */ -+#define _PAS_DMA_TXCHAN_TCMDSTA 0x300 /* Command / Status */ -+#define _PAS_DMA_TXCHAN_CFG 0x304 /* Configuration */ -+#define _PAS_DMA_TXCHAN_DSCRBU 0x308 /* Descriptor BU Allocation */ -+#define _PAS_DMA_TXCHAN_INCR 0x310 /* Descriptor increment */ -+#define _PAS_DMA_TXCHAN_CNT 0x314 /* Descriptor count/offset */ -+#define _PAS_DMA_TXCHAN_BASEL 0x318 /* Descriptor ring base (low) */ -+#define _PAS_DMA_TXCHAN_BASEU 0x31c /* (high) */ -+#define PAS_DMA_TXCHAN_TCMDSTA(c) (0x300+(c)*_PAS_DMA_TXCHAN_STRIDE) -+#define PAS_DMA_TXCHAN_TCMDSTA_EN 0x00000001 /* Enabled */ -+#define PAS_DMA_TXCHAN_TCMDSTA_ST 0x00000002 /* Stop interface */ -+#define PAS_DMA_TXCHAN_TCMDSTA_ACT 0x00010000 /* Active */ -+#define PAS_DMA_TXCHAN_CFG(c) (0x304+(c)*_PAS_DMA_TXCHAN_STRIDE) -+#define PAS_DMA_TXCHAN_CFG_TY_FUNC 0x00000002 /* Type = interface */ -+#define PAS_DMA_TXCHAN_CFG_TY_IFACE 0x00000000 /* Type = interface */ -+#define PAS_DMA_TXCHAN_CFG_TATTR_M 0x0000003c -+#define PAS_DMA_TXCHAN_CFG_TATTR_S 2 -+#define PAS_DMA_TXCHAN_CFG_TATTR(x) (((x) << PAS_DMA_TXCHAN_CFG_TATTR_S) & \ -+ PAS_DMA_TXCHAN_CFG_TATTR_M) -+#define PAS_DMA_TXCHAN_CFG_WT_M 0x000001c0 -+#define PAS_DMA_TXCHAN_CFG_WT_S 6 -+#define PAS_DMA_TXCHAN_CFG_WT(x) (((x) << PAS_DMA_TXCHAN_CFG_WT_S) & \ -+ PAS_DMA_TXCHAN_CFG_WT_M) -+#define PAS_DMA_TXCHAN_CFG_LPSQ_FAST 0x00000400 -+#define PAS_DMA_TXCHAN_CFG_LPDQ_FAST 0x00000800 -+#define PAS_DMA_TXCHAN_CFG_CF 0x00001000 /* Clean first line */ -+#define PAS_DMA_TXCHAN_CFG_CL 0x00002000 /* Clean last line */ -+#define PAS_DMA_TXCHAN_CFG_UP 0x00004000 /* update tx descr when sent */ -+#define PAS_DMA_TXCHAN_INCR(c) (0x310+(c)*_PAS_DMA_TXCHAN_STRIDE) -+#define PAS_DMA_TXCHAN_BASEL(c) (0x318+(c)*_PAS_DMA_TXCHAN_STRIDE) -+#define PAS_DMA_TXCHAN_BASEL_BRBL_M 0xffffffc0 -+#define PAS_DMA_TXCHAN_BASEL_BRBL_S 0 -+#define PAS_DMA_TXCHAN_BASEL_BRBL(x) (((x) << PAS_DMA_TXCHAN_BASEL_BRBL_S) & \ -+ PAS_DMA_TXCHAN_BASEL_BRBL_M) -+#define PAS_DMA_TXCHAN_BASEU(c) (0x31c+(c)*_PAS_DMA_TXCHAN_STRIDE) -+#define PAS_DMA_TXCHAN_BASEU_BRBH_M 0x00000fff -+#define PAS_DMA_TXCHAN_BASEU_BRBH_S 0 -+#define PAS_DMA_TXCHAN_BASEU_BRBH(x) (((x) << PAS_DMA_TXCHAN_BASEU_BRBH_S) & \ -+ PAS_DMA_TXCHAN_BASEU_BRBH_M) -+/* # of cache lines worth of buffer ring */ -+#define PAS_DMA_TXCHAN_BASEU_SIZ_M 0x3fff0000 -+#define PAS_DMA_TXCHAN_BASEU_SIZ_S 16 /* 0 = 16K */ -+#define PAS_DMA_TXCHAN_BASEU_SIZ(x) (((x) << PAS_DMA_TXCHAN_BASEU_SIZ_S) & \ -+ PAS_DMA_TXCHAN_BASEU_SIZ_M) -+ -+#define PAS_STATUS_PCNT_M 0x000000000000ffffull -+#define PAS_STATUS_PCNT_S 0 -+#define PAS_STATUS_DCNT_M 0x00000000ffff0000ull -+#define PAS_STATUS_DCNT_S 16 -+#define PAS_STATUS_BPCNT_M 0x0000ffff00000000ull -+#define PAS_STATUS_BPCNT_S 32 -+#define PAS_STATUS_CAUSE_M 0xf000000000000000ull -+#define PAS_STATUS_TIMER 0x1000000000000000ull -+#define PAS_STATUS_ERROR 0x2000000000000000ull -+#define PAS_STATUS_SOFT 0x4000000000000000ull -+#define PAS_STATUS_INT 0x8000000000000000ull -+ -+#define PAS_IOB_DMA_RXCH_CFG(i) (0x1100 + (i)*4) -+#define PAS_IOB_DMA_RXCH_CFG_CNTTH_M 0x00000fff -+#define PAS_IOB_DMA_RXCH_CFG_CNTTH_S 0 -+#define PAS_IOB_DMA_RXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_RXCH_CFG_CNTTH_S) & \ -+ PAS_IOB_DMA_RXCH_CFG_CNTTH_M) -+#define PAS_IOB_DMA_TXCH_CFG(i) (0x1200 + (i)*4) -+#define PAS_IOB_DMA_TXCH_CFG_CNTTH_M 0x00000fff -+#define PAS_IOB_DMA_TXCH_CFG_CNTTH_S 0 -+#define PAS_IOB_DMA_TXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_TXCH_CFG_CNTTH_S) & \ -+ PAS_IOB_DMA_TXCH_CFG_CNTTH_M) -+#define PAS_IOB_DMA_RXCH_STAT(i) (0x1300 + (i)*4) -+#define PAS_IOB_DMA_RXCH_STAT_INTGEN 0x00001000 -+#define PAS_IOB_DMA_RXCH_STAT_CNTDEL_M 0x00000fff -+#define PAS_IOB_DMA_RXCH_STAT_CNTDEL_S 0 -+#define PAS_IOB_DMA_RXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_RXCH_STAT_CNTDEL_S) &\ -+ PAS_IOB_DMA_RXCH_STAT_CNTDEL_M) -+#define PAS_IOB_DMA_TXCH_STAT(i) (0x1400 + (i)*4) -+#define PAS_IOB_DMA_TXCH_STAT_INTGEN 0x00001000 -+#define PAS_IOB_DMA_TXCH_STAT_CNTDEL_M 0x00000fff -+#define PAS_IOB_DMA_TXCH_STAT_CNTDEL_S 0 -+#define PAS_IOB_DMA_TXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_TXCH_STAT_CNTDEL_S) &\ -+ PAS_IOB_DMA_TXCH_STAT_CNTDEL_M) -+#define PAS_IOB_DMA_RXCH_RESET(i) (0x1500 + (i)*4) -+#define PAS_IOB_DMA_RXCH_RESET_PCNT_M 0xffff0000 -+#define PAS_IOB_DMA_RXCH_RESET_PCNT_S 16 -+#define PAS_IOB_DMA_RXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_RXCH_RESET_PCNT_S) & \ -+ PAS_IOB_DMA_RXCH_RESET_PCNT_M) -+#define PAS_IOB_DMA_RXCH_RESET_PCNTRST 0x00000020 -+#define PAS_IOB_DMA_RXCH_RESET_DCNTRST 0x00000010 -+#define PAS_IOB_DMA_RXCH_RESET_TINTC 0x00000008 -+#define PAS_IOB_DMA_RXCH_RESET_DINTC 0x00000004 -+#define PAS_IOB_DMA_RXCH_RESET_SINTC 0x00000002 -+#define PAS_IOB_DMA_RXCH_RESET_PINTC 0x00000001 -+#define PAS_IOB_DMA_TXCH_RESET(i) (0x1600 + (i)*4) -+#define PAS_IOB_DMA_TXCH_RESET_PCNT_M 0xffff0000 -+#define PAS_IOB_DMA_TXCH_RESET_PCNT_S 16 -+#define PAS_IOB_DMA_TXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_TXCH_RESET_PCNT_S) & \ -+ PAS_IOB_DMA_TXCH_RESET_PCNT_M) -+#define PAS_IOB_DMA_TXCH_RESET_PCNTRST 0x00000020 -+#define PAS_IOB_DMA_TXCH_RESET_DCNTRST 0x00000010 -+#define PAS_IOB_DMA_TXCH_RESET_TINTC 0x00000008 -+#define PAS_IOB_DMA_TXCH_RESET_DINTC 0x00000004 -+#define PAS_IOB_DMA_TXCH_RESET_SINTC 0x00000002 -+#define PAS_IOB_DMA_TXCH_RESET_PINTC 0x00000001 -+ -+#define PAS_IOB_DMA_COM_TIMEOUTCFG 0x1700 -+#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M 0x00ffffff -+#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S 0 -+#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(x) (((x) << PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S) & \ -+ PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M) -+ -+/* Transmit descriptor fields */ -+#define XCT_MACTX_T 0x8000000000000000ull -+#define XCT_MACTX_ST 0x4000000000000000ull -+#define XCT_MACTX_NORES 0x0000000000000000ull -+#define XCT_MACTX_8BRES 0x1000000000000000ull -+#define XCT_MACTX_24BRES 0x2000000000000000ull -+#define XCT_MACTX_40BRES 0x3000000000000000ull -+#define XCT_MACTX_I 0x0800000000000000ull -+#define XCT_MACTX_O 0x0400000000000000ull -+#define XCT_MACTX_E 0x0200000000000000ull -+#define XCT_MACTX_VLAN_M 0x0180000000000000ull -+#define XCT_MACTX_VLAN_NOP 0x0000000000000000ull -+#define XCT_MACTX_VLAN_REMOVE 0x0080000000000000ull -+#define XCT_MACTX_VLAN_INSERT 0x0100000000000000ull -+#define XCT_MACTX_VLAN_REPLACE 0x0180000000000000ull -+#define XCT_MACTX_CRC_M 0x0060000000000000ull -+#define XCT_MACTX_CRC_NOP 0x0000000000000000ull -+#define XCT_MACTX_CRC_INSERT 0x0020000000000000ull -+#define XCT_MACTX_CRC_PAD 0x0040000000000000ull -+#define XCT_MACTX_CRC_REPLACE 0x0060000000000000ull -+#define XCT_MACTX_SS 0x0010000000000000ull -+#define XCT_MACTX_LLEN_M 0x00007fff00000000ull -+#define XCT_MACTX_LLEN_S 32ull -+#define XCT_MACTX_LLEN(x) ((((long)(x)) << XCT_MACTX_LLEN_S) & \ -+ XCT_MACTX_LLEN_M) -+#define XCT_MACTX_IPH_M 0x00000000f8000000ull -+#define XCT_MACTX_IPH_S 27ull -+#define XCT_MACTX_IPH(x) ((((long)(x)) << XCT_MACTX_IPH_S) & \ -+ XCT_MACTX_IPH_M) -+#define XCT_MACTX_IPO_M 0x0000000007c00000ull -+#define XCT_MACTX_IPO_S 22ull -+#define XCT_MACTX_IPO(x) ((((long)(x)) << XCT_MACTX_IPO_S) & \ -+ XCT_MACTX_IPO_M) -+#define XCT_MACTX_CSUM_M 0x0000000000000060ull -+#define XCT_MACTX_CSUM_NOP 0x0000000000000000ull -+#define XCT_MACTX_CSUM_TCP 0x0000000000000040ull -+#define XCT_MACTX_CSUM_UDP 0x0000000000000060ull -+#define XCT_MACTX_V6 0x0000000000000010ull -+#define XCT_MACTX_C 0x0000000000000004ull -+#define XCT_MACTX_AL2 0x0000000000000002ull -+ -+#define XCT_PTR_T 0x8000000000000000ull -+#define XCT_PTR_LEN_M 0x7ffff00000000000ull -+#define XCT_PTR_LEN_S 44 -+#define XCT_PTR_LEN(x) ((((long)(x)) << XCT_PTR_LEN_S) & \ -+ XCT_PTR_LEN_M) -+#define XCT_PTR_ADDR_M 0x00000fffffffffffull -+#define XCT_PTR_ADDR_S 0 -+#define XCT_PTR_ADDR(x) ((((long)(x)) << XCT_PTR_ADDR_S) & \ -+ XCT_PTR_ADDR_M) -+ -+/* Function descriptor fields */ -+#define XCT_FUN_T 0x8000000000000000ull -+#define XCT_FUN_ST 0x4000000000000000ull -+#define XCT_FUN_NORES 0x0000000000000000ull -+#define XCT_FUN_8BRES 0x1000000000000000ull -+#define XCT_FUN_24BRES 0x2000000000000000ull -+#define XCT_FUN_40BRES 0x3000000000000000ull -+#define XCT_FUN_I 0x0800000000000000ull -+#define XCT_FUN_O 0x0400000000000000ull -+#define XCT_FUN_E 0x0200000000000000ull -+#define XCT_FUN_FUN_S 54 -+#define XCT_FUN_FUN_M 0x01c0000000000000ull -+#define XCT_FUN_FUN(num) ((((long)(num)) << XCT_FUN_FUN_S) & \ -+ XCT_FUN_FUN_M) -+#define XCT_FUN_CRM_NOP 0x0000000000000000ull -+#define XCT_FUN_CRM_SIG 0x0008000000000000ull -+#define XCT_FUN_CRM_ENC 0x0010000000000000ull -+#define XCT_FUN_CRM_DEC 0x0018000000000000ull -+#define XCT_FUN_CRM_SIG_ENC 0x0020000000000000ull -+#define XCT_FUN_CRM_ENC_SIG 0x0028000000000000ull -+#define XCT_FUN_CRM_SIG_DEC 0x0030000000000000ull -+#define XCT_FUN_CRM_DEC_SIG 0x0038000000000000ull -+#define XCT_FUN_LLEN_M 0x0007ffff00000000ull -+#define XCT_FUN_LLEN_S 32ULL -+#define XCT_FUN_LLEN(x) ((((long)(x)) << XCT_FUN_LLEN_S) & \ -+ XCT_FUN_LLEN_M) -+#define XCT_FUN_SHL_M 0x00000000f8000000ull -+#define XCT_FUN_SHL_S 27ull -+#define XCT_FUN_SHL(x) ((((long)(x)) << XCT_FUN_SHL_S) & \ -+ XCT_FUN_SHL_M) -+#define XCT_FUN_CHL_M 0x0000000007c00000ull -+#define XCT_FUN_CHL_S 22ull -+#define XCT_FUN_CHL(x) ((((long)(x)) << XCT_FUN_CHL_S) & \ -+ XCT_FUN_CHL_M) -+#define XCT_FUN_HSZ_M 0x00000000003c0000ull -+#define XCT_FUN_HSZ_S 18ull -+#define XCT_FUN_HSZ(x) ((((long)(x)) << XCT_FUN_HSZ_S) & \ -+ XCT_FUN_HSZ_M) -+#define XCT_FUN_ALG_DES 0x0000000000000000ull -+#define XCT_FUN_ALG_3DES 0x0000000000008000ull -+#define XCT_FUN_ALG_AES 0x0000000000010000ull -+#define XCT_FUN_ALG_ARC 0x0000000000018000ull -+#define XCT_FUN_ALG_KASUMI 0x0000000000020000ull -+#define XCT_FUN_BCM_ECB 0x0000000000000000ull -+#define XCT_FUN_BCM_CBC 0x0000000000001000ull -+#define XCT_FUN_BCM_CFB 0x0000000000002000ull -+#define XCT_FUN_BCM_OFB 0x0000000000003000ull -+#define XCT_FUN_BCM_CNT 0x0000000000003800ull -+#define XCT_FUN_BCM_KAS_F8 0x0000000000002800ull -+#define XCT_FUN_BCM_KAS_F9 0x0000000000001800ull -+#define XCT_FUN_BCP_NO_PAD 0x0000000000000000ull -+#define XCT_FUN_BCP_ZRO 0x0000000000000200ull -+#define XCT_FUN_BCP_PL 0x0000000000000400ull -+#define XCT_FUN_BCP_INCR 0x0000000000000600ull -+#define XCT_FUN_SIG_MD5 (0ull << 4) -+#define XCT_FUN_SIG_SHA1 (2ull << 4) -+#define XCT_FUN_SIG_HMAC_MD5 (8ull << 4) -+#define XCT_FUN_SIG_HMAC_SHA1 (10ull << 4) -+#define XCT_FUN_A 0x0000000000000008ull -+#define XCT_FUN_C 0x0000000000000004ull -+#define XCT_FUN_AL2 0x0000000000000002ull -+#define XCT_FUN_SE 0x0000000000000001ull -+ -+#define XCT_FUN_SRC_PTR(len, addr) (XCT_PTR_LEN(len) | XCT_PTR_ADDR(addr)) -+#define XCT_FUN_DST_PTR(len, addr) (XCT_FUN_SRC_PTR(len, addr) | \ -+ 0x8000000000000000ull) -+ -+#define XCT_CTRL_HDR_FUN_NUM_M 0x01c0000000000000ull -+#define XCT_CTRL_HDR_FUN_NUM_S 54 -+#define XCT_CTRL_HDR_LEN_M 0x0007ffff00000000ull -+#define XCT_CTRL_HDR_LEN_S 32 -+#define XCT_CTRL_HDR_REG_M 0x00000000000000ffull -+#define XCT_CTRL_HDR_REG_S 0 -+ -+#define XCT_CTRL_HDR(funcN,len,reg) (0x9400000000000000ull | \ -+ ((((long)(funcN)) << XCT_CTRL_HDR_FUN_NUM_S) \ -+ & XCT_CTRL_HDR_FUN_NUM_M) | \ -+ ((((long)(len)) << \ -+ XCT_CTRL_HDR_LEN_S) & XCT_CTRL_HDR_LEN_M) | \ -+ ((((long)(reg)) << \ -+ XCT_CTRL_HDR_REG_S) & XCT_CTRL_HDR_REG_M)) -+ -+/* Function config command options */ -+#define DMA_CALGO_DES 0x00 -+#define DMA_CALGO_3DES 0x01 -+#define DMA_CALGO_AES 0x02 -+#define DMA_CALGO_ARC 0x03 -+ -+#define DMA_FN_CIV0 0x02 -+#define DMA_FN_CIV1 0x03 -+#define DMA_FN_HKEY0 0x0a -+ -+#define XCT_PTR_ADDR_LEN(ptr) ((ptr) & XCT_PTR_ADDR_M), \ -+ (((ptr) & XCT_PTR_LEN_M) >> XCT_PTR_LEN_S) -+ -+#endif /* PASEMI_FNU_H */ -diff -Nur linux-3.0.4.orig/crypto/ocf/random.c linux-3.0.4/crypto/ocf/random.c ---- linux-3.0.4.orig/crypto/ocf/random.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/random.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,317 @@ -+/* -+ * A system independant way of adding entropy to the kernels pool -+ * this way the drivers can focus on the real work and we can take -+ * care of pushing it to the appropriate place in the kernel. -+ * -+ * This should be fast and callable from timers/interrupts -+ * -+ * Written by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * ALTERNATIVELY, provided that this notice is retained in full, this product -+ * may be distributed under the terms of the GNU General Public License (GPL), -+ * in which case the provisions of the GPL apply INSTEAD OF those given above. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ */ -+ -+#include -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#ifdef CONFIG_OCF_FIPS -+#include "rndtest.h" -+#endif -+ -+#ifndef HAS_RANDOM_INPUT_WAIT -+#error "Please do not enable OCF_RANDOMHARVEST unless you have applied patches" -+#endif -+ -+/* -+ * a hack to access the debug levels from the crypto driver -+ */ -+extern int crypto_debug; -+#define debug crypto_debug -+ -+/* -+ * a list of all registered random providers -+ */ -+static LIST_HEAD(random_ops); -+static int started = 0; -+static int initted = 0; -+ -+struct random_op { -+ struct list_head random_list; -+ u_int32_t driverid; -+ int (*read_random)(void *arg, u_int32_t *buf, int len); -+ void *arg; -+}; -+ -+static int random_proc(void *arg); -+ -+static pid_t randomproc = (pid_t) -1; -+static spinlock_t random_lock; -+ -+/* -+ * just init the spin locks -+ */ -+static int -+crypto_random_init(void) -+{ -+ spin_lock_init(&random_lock); -+ initted = 1; -+ return(0); -+} -+ -+/* -+ * Add the given random reader to our list (if not present) -+ * and start the thread (if not already started) -+ * -+ * we have to assume that driver id is ok for now -+ */ -+int -+crypto_rregister( -+ u_int32_t driverid, -+ int (*read_random)(void *arg, u_int32_t *buf, int len), -+ void *arg) -+{ -+ unsigned long flags; -+ int ret = 0; -+ struct random_op *rops, *tmp; -+ -+ dprintk("%s,%d: %s(0x%x, %p, %p)\n", __FILE__, __LINE__, -+ __FUNCTION__, driverid, read_random, arg); -+ -+ if (!initted) -+ crypto_random_init(); -+ -+#if 0 -+ struct cryptocap *cap; -+ -+ cap = crypto_checkdriver(driverid); -+ if (!cap) -+ return EINVAL; -+#endif -+ -+ list_for_each_entry_safe(rops, tmp, &random_ops, random_list) { -+ if (rops->driverid == driverid && rops->read_random == read_random) -+ return EEXIST; -+ } -+ -+ rops = (struct random_op *) kmalloc(sizeof(*rops), GFP_KERNEL); -+ if (!rops) -+ return ENOMEM; -+ -+ rops->driverid = driverid; -+ rops->read_random = read_random; -+ rops->arg = arg; -+ -+ spin_lock_irqsave(&random_lock, flags); -+ list_add_tail(&rops->random_list, &random_ops); -+ if (!started) { -+ randomproc = kernel_thread(random_proc, NULL, CLONE_FS|CLONE_FILES); -+ if (randomproc < 0) { -+ ret = randomproc; -+ printk("crypto: crypto_rregister cannot start random thread; " -+ "error %d", ret); -+ } else -+ started = 1; -+ } -+ spin_unlock_irqrestore(&random_lock, flags); -+ -+ return ret; -+} -+EXPORT_SYMBOL(crypto_rregister); -+ -+int -+crypto_runregister_all(u_int32_t driverid) -+{ -+ struct random_op *rops, *tmp; -+ unsigned long flags; -+ -+ dprintk("%s,%d: %s(0x%x)\n", __FILE__, __LINE__, __FUNCTION__, driverid); -+ -+ list_for_each_entry_safe(rops, tmp, &random_ops, random_list) { -+ if (rops->driverid == driverid) { -+ list_del(&rops->random_list); -+ kfree(rops); -+ } -+ } -+ -+ spin_lock_irqsave(&random_lock, flags); -+ if (list_empty(&random_ops) && started) -+ kill_proc(randomproc, SIGKILL, 1); -+ spin_unlock_irqrestore(&random_lock, flags); -+ return(0); -+} -+EXPORT_SYMBOL(crypto_runregister_all); -+ -+/* -+ * while we can add entropy to random.c continue to read random data from -+ * the drivers and push it to random. -+ */ -+static int -+random_proc(void *arg) -+{ -+ int n; -+ int wantcnt; -+ int bufcnt = 0; -+ int retval = 0; -+ int *buf = NULL; -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ daemonize(); -+ spin_lock_irq(¤t->sigmask_lock); -+ sigemptyset(¤t->blocked); -+ recalc_sigpending(current); -+ spin_unlock_irq(¤t->sigmask_lock); -+ sprintf(current->comm, "ocf-random"); -+#else -+ daemonize("ocf-random"); -+ allow_signal(SIGKILL); -+#endif -+ -+ (void) get_fs(); -+ set_fs(get_ds()); -+ -+#ifdef CONFIG_OCF_FIPS -+#define NUM_INT (RNDTEST_NBYTES/sizeof(int)) -+#else -+#define NUM_INT 32 -+#endif -+ -+ /* -+ * some devices can transferr their RNG data direct into memory, -+ * so make sure it is device friendly -+ */ -+ buf = kmalloc(NUM_INT * sizeof(int), GFP_DMA); -+ if (NULL == buf) { -+ printk("crypto: RNG could not allocate memory\n"); -+ retval = -ENOMEM; -+ goto bad_alloc; -+ } -+ -+ wantcnt = NUM_INT; /* start by adding some entropy */ -+ -+ /* -+ * its possible due to errors or driver removal that we no longer -+ * have anything to do, if so exit or we will consume all the CPU -+ * doing nothing -+ */ -+ while (!list_empty(&random_ops)) { -+ struct random_op *rops, *tmp; -+ -+#ifdef CONFIG_OCF_FIPS -+ if (wantcnt) -+ wantcnt = NUM_INT; /* FIPs mode can do 20000 bits or none */ -+#endif -+ -+ /* see if we can get enough entropy to make the world -+ * a better place. -+ */ -+ while (bufcnt < wantcnt && bufcnt < NUM_INT) { -+ list_for_each_entry_safe(rops, tmp, &random_ops, random_list) { -+ -+ n = (*rops->read_random)(rops->arg, &buf[bufcnt], -+ NUM_INT - bufcnt); -+ -+ /* on failure remove the random number generator */ -+ if (n == -1) { -+ list_del(&rops->random_list); -+ printk("crypto: RNG (driverid=0x%x) failed, disabling\n", -+ rops->driverid); -+ kfree(rops); -+ } else if (n > 0) -+ bufcnt += n; -+ } -+ /* give up CPU for a bit, just in case as this is a loop */ -+ schedule(); -+ } -+ -+ -+#ifdef CONFIG_OCF_FIPS -+ if (bufcnt > 0 && rndtest_buf((unsigned char *) &buf[0])) { -+ dprintk("crypto: buffer had fips errors, discarding\n"); -+ bufcnt = 0; -+ } -+#endif -+ -+ /* -+ * if we have a certified buffer, we can send some data -+ * to /dev/random and move along -+ */ -+ if (bufcnt > 0) { -+ /* add what we have */ -+ random_input_words(buf, bufcnt, bufcnt*sizeof(int)*8); -+ bufcnt = 0; -+ } -+ -+ /* give up CPU for a bit so we don't hog while filling */ -+ schedule(); -+ -+ /* wait for needing more */ -+ wantcnt = random_input_wait(); -+ -+ if (wantcnt <= 0) -+ wantcnt = 0; /* try to get some info again */ -+ else -+ /* round up to one word or we can loop forever */ -+ wantcnt = (wantcnt + (sizeof(int)*8)) / (sizeof(int)*8); -+ if (wantcnt > NUM_INT) { -+ wantcnt = NUM_INT; -+ } -+ -+ if (signal_pending(current)) { -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ spin_lock_irq(¤t->sigmask_lock); -+#endif -+ flush_signals(current); -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ spin_unlock_irq(¤t->sigmask_lock); -+#endif -+ } -+ } -+ -+ kfree(buf); -+ -+bad_alloc: -+ spin_lock_irq(&random_lock); -+ randomproc = (pid_t) -1; -+ started = 0; -+ spin_unlock_irq(&random_lock); -+ -+ return retval; -+} -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/rndtest.c linux-3.0.4/crypto/ocf/rndtest.c ---- linux-3.0.4.orig/crypto/ocf/rndtest.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/rndtest.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,300 @@ -+/* $OpenBSD$ */ -+ -+/* -+ * OCF/Linux port done by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * The license and original author are listed below. -+ * -+ * Copyright (c) 2002 Jason L. Wright (jason@thought.net) -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. All advertising materials mentioning features or use of this software -+ * must display the following acknowledgement: -+ * This product includes software developed by Jason L. Wright -+ * 4. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "rndtest.h" -+ -+static struct rndtest_stats rndstats; -+ -+static void rndtest_test(struct rndtest_state *); -+ -+/* The tests themselves */ -+static int rndtest_monobit(struct rndtest_state *); -+static int rndtest_runs(struct rndtest_state *); -+static int rndtest_longruns(struct rndtest_state *); -+static int rndtest_chi_4(struct rndtest_state *); -+ -+static int rndtest_runs_check(struct rndtest_state *, int, int *); -+static void rndtest_runs_record(struct rndtest_state *, int, int *); -+ -+static const struct rndtest_testfunc { -+ int (*test)(struct rndtest_state *); -+} rndtest_funcs[] = { -+ { rndtest_monobit }, -+ { rndtest_runs }, -+ { rndtest_chi_4 }, -+ { rndtest_longruns }, -+}; -+ -+#define RNDTEST_NTESTS (sizeof(rndtest_funcs)/sizeof(rndtest_funcs[0])) -+ -+static void -+rndtest_test(struct rndtest_state *rsp) -+{ -+ int i, rv = 0; -+ -+ rndstats.rst_tests++; -+ for (i = 0; i < RNDTEST_NTESTS; i++) -+ rv |= (*rndtest_funcs[i].test)(rsp); -+ rsp->rs_discard = (rv != 0); -+} -+ -+ -+extern int crypto_debug; -+#define rndtest_verbose 2 -+#define rndtest_report(rsp, failure, fmt, a...) \ -+ { if (failure || crypto_debug) { printk("rng_test: " fmt "\n", a); } else; } -+ -+#define RNDTEST_MONOBIT_MINONES 9725 -+#define RNDTEST_MONOBIT_MAXONES 10275 -+ -+static int -+rndtest_monobit(struct rndtest_state *rsp) -+{ -+ int i, ones = 0, j; -+ u_int8_t r; -+ -+ for (i = 0; i < RNDTEST_NBYTES; i++) { -+ r = rsp->rs_buf[i]; -+ for (j = 0; j < 8; j++, r <<= 1) -+ if (r & 0x80) -+ ones++; -+ } -+ if (ones > RNDTEST_MONOBIT_MINONES && -+ ones < RNDTEST_MONOBIT_MAXONES) { -+ if (rndtest_verbose > 1) -+ rndtest_report(rsp, 0, "monobit pass (%d < %d < %d)", -+ RNDTEST_MONOBIT_MINONES, ones, -+ RNDTEST_MONOBIT_MAXONES); -+ return (0); -+ } else { -+ if (rndtest_verbose) -+ rndtest_report(rsp, 1, -+ "monobit failed (%d ones)", ones); -+ rndstats.rst_monobit++; -+ return (-1); -+ } -+} -+ -+#define RNDTEST_RUNS_NINTERVAL 6 -+ -+static const struct rndtest_runs_tabs { -+ u_int16_t min, max; -+} rndtest_runs_tab[] = { -+ { 2343, 2657 }, -+ { 1135, 1365 }, -+ { 542, 708 }, -+ { 251, 373 }, -+ { 111, 201 }, -+ { 111, 201 }, -+}; -+ -+static int -+rndtest_runs(struct rndtest_state *rsp) -+{ -+ int i, j, ones, zeros, rv = 0; -+ int onei[RNDTEST_RUNS_NINTERVAL], zeroi[RNDTEST_RUNS_NINTERVAL]; -+ u_int8_t c; -+ -+ bzero(onei, sizeof(onei)); -+ bzero(zeroi, sizeof(zeroi)); -+ ones = zeros = 0; -+ for (i = 0; i < RNDTEST_NBYTES; i++) { -+ c = rsp->rs_buf[i]; -+ for (j = 0; j < 8; j++, c <<= 1) { -+ if (c & 0x80) { -+ ones++; -+ rndtest_runs_record(rsp, zeros, zeroi); -+ zeros = 0; -+ } else { -+ zeros++; -+ rndtest_runs_record(rsp, ones, onei); -+ ones = 0; -+ } -+ } -+ } -+ rndtest_runs_record(rsp, ones, onei); -+ rndtest_runs_record(rsp, zeros, zeroi); -+ -+ rv |= rndtest_runs_check(rsp, 0, zeroi); -+ rv |= rndtest_runs_check(rsp, 1, onei); -+ -+ if (rv) -+ rndstats.rst_runs++; -+ -+ return (rv); -+} -+ -+static void -+rndtest_runs_record(struct rndtest_state *rsp, int len, int *intrv) -+{ -+ if (len == 0) -+ return; -+ if (len > RNDTEST_RUNS_NINTERVAL) -+ len = RNDTEST_RUNS_NINTERVAL; -+ len -= 1; -+ intrv[len]++; -+} -+ -+static int -+rndtest_runs_check(struct rndtest_state *rsp, int val, int *src) -+{ -+ int i, rv = 0; -+ -+ for (i = 0; i < RNDTEST_RUNS_NINTERVAL; i++) { -+ if (src[i] < rndtest_runs_tab[i].min || -+ src[i] > rndtest_runs_tab[i].max) { -+ rndtest_report(rsp, 1, -+ "%s interval %d failed (%d, %d-%d)", -+ val ? "ones" : "zeros", -+ i + 1, src[i], rndtest_runs_tab[i].min, -+ rndtest_runs_tab[i].max); -+ rv = -1; -+ } else { -+ rndtest_report(rsp, 0, -+ "runs pass %s interval %d (%d < %d < %d)", -+ val ? "ones" : "zeros", -+ i + 1, rndtest_runs_tab[i].min, src[i], -+ rndtest_runs_tab[i].max); -+ } -+ } -+ return (rv); -+} -+ -+static int -+rndtest_longruns(struct rndtest_state *rsp) -+{ -+ int i, j, ones = 0, zeros = 0, maxones = 0, maxzeros = 0; -+ u_int8_t c; -+ -+ for (i = 0; i < RNDTEST_NBYTES; i++) { -+ c = rsp->rs_buf[i]; -+ for (j = 0; j < 8; j++, c <<= 1) { -+ if (c & 0x80) { -+ zeros = 0; -+ ones++; -+ if (ones > maxones) -+ maxones = ones; -+ } else { -+ ones = 0; -+ zeros++; -+ if (zeros > maxzeros) -+ maxzeros = zeros; -+ } -+ } -+ } -+ -+ if (maxones < 26 && maxzeros < 26) { -+ rndtest_report(rsp, 0, "longruns pass (%d ones, %d zeros)", -+ maxones, maxzeros); -+ return (0); -+ } else { -+ rndtest_report(rsp, 1, "longruns fail (%d ones, %d zeros)", -+ maxones, maxzeros); -+ rndstats.rst_longruns++; -+ return (-1); -+ } -+} -+ -+/* -+ * chi^2 test over 4 bits: (this is called the poker test in FIPS 140-2, -+ * but it is really the chi^2 test over 4 bits (the poker test as described -+ * by Knuth vol 2 is something different, and I take him as authoritative -+ * on nomenclature over NIST). -+ */ -+#define RNDTEST_CHI4_K 16 -+#define RNDTEST_CHI4_K_MASK (RNDTEST_CHI4_K - 1) -+ -+/* -+ * The unnormalized values are used so that we don't have to worry about -+ * fractional precision. The "real" value is found by: -+ * (V - 1562500) * (16 / 5000) = Vn (where V is the unnormalized value) -+ */ -+#define RNDTEST_CHI4_VMIN 1563181 /* 2.1792 */ -+#define RNDTEST_CHI4_VMAX 1576929 /* 46.1728 */ -+ -+static int -+rndtest_chi_4(struct rndtest_state *rsp) -+{ -+ unsigned int freq[RNDTEST_CHI4_K], i, sum; -+ -+ for (i = 0; i < RNDTEST_CHI4_K; i++) -+ freq[i] = 0; -+ -+ /* Get number of occurances of each 4 bit pattern */ -+ for (i = 0; i < RNDTEST_NBYTES; i++) { -+ freq[(rsp->rs_buf[i] >> 4) & RNDTEST_CHI4_K_MASK]++; -+ freq[(rsp->rs_buf[i] >> 0) & RNDTEST_CHI4_K_MASK]++; -+ } -+ -+ for (i = 0, sum = 0; i < RNDTEST_CHI4_K; i++) -+ sum += freq[i] * freq[i]; -+ -+ if (sum >= 1563181 && sum <= 1576929) { -+ rndtest_report(rsp, 0, "chi^2(4): pass (sum %u)", sum); -+ return (0); -+ } else { -+ rndtest_report(rsp, 1, "chi^2(4): failed (sum %u)", sum); -+ rndstats.rst_chi++; -+ return (-1); -+ } -+} -+ -+int -+rndtest_buf(unsigned char *buf) -+{ -+ struct rndtest_state rsp; -+ -+ memset(&rsp, 0, sizeof(rsp)); -+ rsp.rs_buf = buf; -+ rndtest_test(&rsp); -+ return(rsp.rs_discard); -+} -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/rndtest.h linux-3.0.4/crypto/ocf/rndtest.h ---- linux-3.0.4.orig/crypto/ocf/rndtest.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/rndtest.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,54 @@ -+/* $FreeBSD: src/sys/dev/rndtest/rndtest.h,v 1.1 2003/03/11 22:54:44 sam Exp $ */ -+/* $OpenBSD$ */ -+ -+/* -+ * Copyright (c) 2002 Jason L. Wright (jason@thought.net) -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. All advertising materials mentioning features or use of this software -+ * must display the following acknowledgement: -+ * This product includes software developed by Jason L. Wright -+ * 4. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/* Some of the tests depend on these values */ -+#define RNDTEST_NBYTES 2500 -+#define RNDTEST_NBITS (8 * RNDTEST_NBYTES) -+ -+struct rndtest_state { -+ int rs_discard; /* discard/accept random data */ -+ u_int8_t *rs_buf; -+}; -+ -+struct rndtest_stats { -+ u_int32_t rst_discard; /* number of bytes discarded */ -+ u_int32_t rst_tests; /* number of test runs */ -+ u_int32_t rst_monobit; /* monobit test failures */ -+ u_int32_t rst_runs; /* 0/1 runs failures */ -+ u_int32_t rst_longruns; /* longruns failures */ -+ u_int32_t rst_chi; /* chi^2 failures */ -+}; -+ -+extern int rndtest_buf(unsigned char *buf); -diff -Nur linux-3.0.4.orig/crypto/ocf/safe/Makefile linux-3.0.4/crypto/ocf/safe/Makefile ---- linux-3.0.4.orig/crypto/ocf/safe/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/safe/Makefile 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,12 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+obj-$(CONFIG_OCF_SAFE) += safe.o -+ -+obj ?= . -+EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/safe/hmachack.h linux-3.0.4/crypto/ocf/safe/hmachack.h ---- linux-3.0.4.orig/crypto/ocf/safe/hmachack.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/safe/hmachack.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,37 @@ -+/* -+ * until we find a cleaner way, include the BSD md5/sha1 code -+ * here -+ */ -+#ifdef HMAC_HACK -+#define LITTLE_ENDIAN 1234 -+#define BIG_ENDIAN 4321 -+#ifdef __LITTLE_ENDIAN -+#define BYTE_ORDER LITTLE_ENDIAN -+#endif -+#ifdef __BIG_ENDIAN -+#define BYTE_ORDER BIG_ENDIAN -+#endif -+ -+u_int8_t hmac_ipad_buffer[64] = { -+ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, -+ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, -+ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, -+ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, -+ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, -+ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, -+ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, -+ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36 -+}; -+ -+u_int8_t hmac_opad_buffer[64] = { -+ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, -+ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, -+ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, -+ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, -+ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, -+ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, -+ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, -+ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C -+}; -+#endif /* HMAC_HACK */ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/safe/md5.c linux-3.0.4/crypto/ocf/safe/md5.c ---- linux-3.0.4.orig/crypto/ocf/safe/md5.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/safe/md5.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,308 @@ -+/* $KAME: md5.c,v 1.5 2000/11/08 06:13:08 itojun Exp $ */ -+/* -+ * Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. Neither the name of the project nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ */ -+ -+#if 0 -+#include -+__FBSDID("$FreeBSD: src/sys/crypto/md5.c,v 1.9 2004/01/27 19:49:19 des Exp $"); -+ -+#include -+#include -+#include -+#include -+#include -+#endif -+ -+#define SHIFT(X, s) (((X) << (s)) | ((X) >> (32 - (s)))) -+ -+#define F(X, Y, Z) (((X) & (Y)) | ((~X) & (Z))) -+#define G(X, Y, Z) (((X) & (Z)) | ((Y) & (~Z))) -+#define H(X, Y, Z) ((X) ^ (Y) ^ (Z)) -+#define I(X, Y, Z) ((Y) ^ ((X) | (~Z))) -+ -+#define ROUND1(a, b, c, d, k, s, i) { \ -+ (a) = (a) + F((b), (c), (d)) + X[(k)] + T[(i)]; \ -+ (a) = SHIFT((a), (s)); \ -+ (a) = (b) + (a); \ -+} -+ -+#define ROUND2(a, b, c, d, k, s, i) { \ -+ (a) = (a) + G((b), (c), (d)) + X[(k)] + T[(i)]; \ -+ (a) = SHIFT((a), (s)); \ -+ (a) = (b) + (a); \ -+} -+ -+#define ROUND3(a, b, c, d, k, s, i) { \ -+ (a) = (a) + H((b), (c), (d)) + X[(k)] + T[(i)]; \ -+ (a) = SHIFT((a), (s)); \ -+ (a) = (b) + (a); \ -+} -+ -+#define ROUND4(a, b, c, d, k, s, i) { \ -+ (a) = (a) + I((b), (c), (d)) + X[(k)] + T[(i)]; \ -+ (a) = SHIFT((a), (s)); \ -+ (a) = (b) + (a); \ -+} -+ -+#define Sa 7 -+#define Sb 12 -+#define Sc 17 -+#define Sd 22 -+ -+#define Se 5 -+#define Sf 9 -+#define Sg 14 -+#define Sh 20 -+ -+#define Si 4 -+#define Sj 11 -+#define Sk 16 -+#define Sl 23 -+ -+#define Sm 6 -+#define Sn 10 -+#define So 15 -+#define Sp 21 -+ -+#define MD5_A0 0x67452301 -+#define MD5_B0 0xefcdab89 -+#define MD5_C0 0x98badcfe -+#define MD5_D0 0x10325476 -+ -+/* Integer part of 4294967296 times abs(sin(i)), where i is in radians. */ -+static const u_int32_t T[65] = { -+ 0, -+ 0xd76aa478, 0xe8c7b756, 0x242070db, 0xc1bdceee, -+ 0xf57c0faf, 0x4787c62a, 0xa8304613, 0xfd469501, -+ 0x698098d8, 0x8b44f7af, 0xffff5bb1, 0x895cd7be, -+ 0x6b901122, 0xfd987193, 0xa679438e, 0x49b40821, -+ -+ 0xf61e2562, 0xc040b340, 0x265e5a51, 0xe9b6c7aa, -+ 0xd62f105d, 0x2441453, 0xd8a1e681, 0xe7d3fbc8, -+ 0x21e1cde6, 0xc33707d6, 0xf4d50d87, 0x455a14ed, -+ 0xa9e3e905, 0xfcefa3f8, 0x676f02d9, 0x8d2a4c8a, -+ -+ 0xfffa3942, 0x8771f681, 0x6d9d6122, 0xfde5380c, -+ 0xa4beea44, 0x4bdecfa9, 0xf6bb4b60, 0xbebfbc70, -+ 0x289b7ec6, 0xeaa127fa, 0xd4ef3085, 0x4881d05, -+ 0xd9d4d039, 0xe6db99e5, 0x1fa27cf8, 0xc4ac5665, -+ -+ 0xf4292244, 0x432aff97, 0xab9423a7, 0xfc93a039, -+ 0x655b59c3, 0x8f0ccc92, 0xffeff47d, 0x85845dd1, -+ 0x6fa87e4f, 0xfe2ce6e0, 0xa3014314, 0x4e0811a1, -+ 0xf7537e82, 0xbd3af235, 0x2ad7d2bb, 0xeb86d391, -+}; -+ -+static const u_int8_t md5_paddat[MD5_BUFLEN] = { -+ 0x80, 0, 0, 0, 0, 0, 0, 0, -+ 0, 0, 0, 0, 0, 0, 0, 0, -+ 0, 0, 0, 0, 0, 0, 0, 0, -+ 0, 0, 0, 0, 0, 0, 0, 0, -+ 0, 0, 0, 0, 0, 0, 0, 0, -+ 0, 0, 0, 0, 0, 0, 0, 0, -+ 0, 0, 0, 0, 0, 0, 0, 0, -+ 0, 0, 0, 0, 0, 0, 0, 0, -+}; -+ -+static void md5_calc(u_int8_t *, md5_ctxt *); -+ -+void md5_init(ctxt) -+ md5_ctxt *ctxt; -+{ -+ ctxt->md5_n = 0; -+ ctxt->md5_i = 0; -+ ctxt->md5_sta = MD5_A0; -+ ctxt->md5_stb = MD5_B0; -+ ctxt->md5_stc = MD5_C0; -+ ctxt->md5_std = MD5_D0; -+ bzero(ctxt->md5_buf, sizeof(ctxt->md5_buf)); -+} -+ -+void md5_loop(ctxt, input, len) -+ md5_ctxt *ctxt; -+ u_int8_t *input; -+ u_int len; /* number of bytes */ -+{ -+ u_int gap, i; -+ -+ ctxt->md5_n += len * 8; /* byte to bit */ -+ gap = MD5_BUFLEN - ctxt->md5_i; -+ -+ if (len >= gap) { -+ bcopy((void *)input, (void *)(ctxt->md5_buf + ctxt->md5_i), -+ gap); -+ md5_calc(ctxt->md5_buf, ctxt); -+ -+ for (i = gap; i + MD5_BUFLEN <= len; i += MD5_BUFLEN) { -+ md5_calc((u_int8_t *)(input + i), ctxt); -+ } -+ -+ ctxt->md5_i = len - i; -+ bcopy((void *)(input + i), (void *)ctxt->md5_buf, ctxt->md5_i); -+ } else { -+ bcopy((void *)input, (void *)(ctxt->md5_buf + ctxt->md5_i), -+ len); -+ ctxt->md5_i += len; -+ } -+} -+ -+void md5_pad(ctxt) -+ md5_ctxt *ctxt; -+{ -+ u_int gap; -+ -+ /* Don't count up padding. Keep md5_n. */ -+ gap = MD5_BUFLEN - ctxt->md5_i; -+ if (gap > 8) { -+ bcopy(md5_paddat, -+ (void *)(ctxt->md5_buf + ctxt->md5_i), -+ gap - sizeof(ctxt->md5_n)); -+ } else { -+ /* including gap == 8 */ -+ bcopy(md5_paddat, (void *)(ctxt->md5_buf + ctxt->md5_i), -+ gap); -+ md5_calc(ctxt->md5_buf, ctxt); -+ bcopy((md5_paddat + gap), -+ (void *)ctxt->md5_buf, -+ MD5_BUFLEN - sizeof(ctxt->md5_n)); -+ } -+ -+ /* 8 byte word */ -+#if BYTE_ORDER == LITTLE_ENDIAN -+ bcopy(&ctxt->md5_n8[0], &ctxt->md5_buf[56], 8); -+#endif -+#if BYTE_ORDER == BIG_ENDIAN -+ ctxt->md5_buf[56] = ctxt->md5_n8[7]; -+ ctxt->md5_buf[57] = ctxt->md5_n8[6]; -+ ctxt->md5_buf[58] = ctxt->md5_n8[5]; -+ ctxt->md5_buf[59] = ctxt->md5_n8[4]; -+ ctxt->md5_buf[60] = ctxt->md5_n8[3]; -+ ctxt->md5_buf[61] = ctxt->md5_n8[2]; -+ ctxt->md5_buf[62] = ctxt->md5_n8[1]; -+ ctxt->md5_buf[63] = ctxt->md5_n8[0]; -+#endif -+ -+ md5_calc(ctxt->md5_buf, ctxt); -+} -+ -+void md5_result(digest, ctxt) -+ u_int8_t *digest; -+ md5_ctxt *ctxt; -+{ -+ /* 4 byte words */ -+#if BYTE_ORDER == LITTLE_ENDIAN -+ bcopy(&ctxt->md5_st8[0], digest, 16); -+#endif -+#if BYTE_ORDER == BIG_ENDIAN -+ digest[ 0] = ctxt->md5_st8[ 3]; digest[ 1] = ctxt->md5_st8[ 2]; -+ digest[ 2] = ctxt->md5_st8[ 1]; digest[ 3] = ctxt->md5_st8[ 0]; -+ digest[ 4] = ctxt->md5_st8[ 7]; digest[ 5] = ctxt->md5_st8[ 6]; -+ digest[ 6] = ctxt->md5_st8[ 5]; digest[ 7] = ctxt->md5_st8[ 4]; -+ digest[ 8] = ctxt->md5_st8[11]; digest[ 9] = ctxt->md5_st8[10]; -+ digest[10] = ctxt->md5_st8[ 9]; digest[11] = ctxt->md5_st8[ 8]; -+ digest[12] = ctxt->md5_st8[15]; digest[13] = ctxt->md5_st8[14]; -+ digest[14] = ctxt->md5_st8[13]; digest[15] = ctxt->md5_st8[12]; -+#endif -+} -+ -+static void md5_calc(b64, ctxt) -+ u_int8_t *b64; -+ md5_ctxt *ctxt; -+{ -+ u_int32_t A = ctxt->md5_sta; -+ u_int32_t B = ctxt->md5_stb; -+ u_int32_t C = ctxt->md5_stc; -+ u_int32_t D = ctxt->md5_std; -+#if BYTE_ORDER == LITTLE_ENDIAN -+ u_int32_t *X = (u_int32_t *)b64; -+#endif -+#if BYTE_ORDER == BIG_ENDIAN -+ /* 4 byte words */ -+ /* what a brute force but fast! */ -+ u_int32_t X[16]; -+ u_int8_t *y = (u_int8_t *)X; -+ y[ 0] = b64[ 3]; y[ 1] = b64[ 2]; y[ 2] = b64[ 1]; y[ 3] = b64[ 0]; -+ y[ 4] = b64[ 7]; y[ 5] = b64[ 6]; y[ 6] = b64[ 5]; y[ 7] = b64[ 4]; -+ y[ 8] = b64[11]; y[ 9] = b64[10]; y[10] = b64[ 9]; y[11] = b64[ 8]; -+ y[12] = b64[15]; y[13] = b64[14]; y[14] = b64[13]; y[15] = b64[12]; -+ y[16] = b64[19]; y[17] = b64[18]; y[18] = b64[17]; y[19] = b64[16]; -+ y[20] = b64[23]; y[21] = b64[22]; y[22] = b64[21]; y[23] = b64[20]; -+ y[24] = b64[27]; y[25] = b64[26]; y[26] = b64[25]; y[27] = b64[24]; -+ y[28] = b64[31]; y[29] = b64[30]; y[30] = b64[29]; y[31] = b64[28]; -+ y[32] = b64[35]; y[33] = b64[34]; y[34] = b64[33]; y[35] = b64[32]; -+ y[36] = b64[39]; y[37] = b64[38]; y[38] = b64[37]; y[39] = b64[36]; -+ y[40] = b64[43]; y[41] = b64[42]; y[42] = b64[41]; y[43] = b64[40]; -+ y[44] = b64[47]; y[45] = b64[46]; y[46] = b64[45]; y[47] = b64[44]; -+ y[48] = b64[51]; y[49] = b64[50]; y[50] = b64[49]; y[51] = b64[48]; -+ y[52] = b64[55]; y[53] = b64[54]; y[54] = b64[53]; y[55] = b64[52]; -+ y[56] = b64[59]; y[57] = b64[58]; y[58] = b64[57]; y[59] = b64[56]; -+ y[60] = b64[63]; y[61] = b64[62]; y[62] = b64[61]; y[63] = b64[60]; -+#endif -+ -+ ROUND1(A, B, C, D, 0, Sa, 1); ROUND1(D, A, B, C, 1, Sb, 2); -+ ROUND1(C, D, A, B, 2, Sc, 3); ROUND1(B, C, D, A, 3, Sd, 4); -+ ROUND1(A, B, C, D, 4, Sa, 5); ROUND1(D, A, B, C, 5, Sb, 6); -+ ROUND1(C, D, A, B, 6, Sc, 7); ROUND1(B, C, D, A, 7, Sd, 8); -+ ROUND1(A, B, C, D, 8, Sa, 9); ROUND1(D, A, B, C, 9, Sb, 10); -+ ROUND1(C, D, A, B, 10, Sc, 11); ROUND1(B, C, D, A, 11, Sd, 12); -+ ROUND1(A, B, C, D, 12, Sa, 13); ROUND1(D, A, B, C, 13, Sb, 14); -+ ROUND1(C, D, A, B, 14, Sc, 15); ROUND1(B, C, D, A, 15, Sd, 16); -+ -+ ROUND2(A, B, C, D, 1, Se, 17); ROUND2(D, A, B, C, 6, Sf, 18); -+ ROUND2(C, D, A, B, 11, Sg, 19); ROUND2(B, C, D, A, 0, Sh, 20); -+ ROUND2(A, B, C, D, 5, Se, 21); ROUND2(D, A, B, C, 10, Sf, 22); -+ ROUND2(C, D, A, B, 15, Sg, 23); ROUND2(B, C, D, A, 4, Sh, 24); -+ ROUND2(A, B, C, D, 9, Se, 25); ROUND2(D, A, B, C, 14, Sf, 26); -+ ROUND2(C, D, A, B, 3, Sg, 27); ROUND2(B, C, D, A, 8, Sh, 28); -+ ROUND2(A, B, C, D, 13, Se, 29); ROUND2(D, A, B, C, 2, Sf, 30); -+ ROUND2(C, D, A, B, 7, Sg, 31); ROUND2(B, C, D, A, 12, Sh, 32); -+ -+ ROUND3(A, B, C, D, 5, Si, 33); ROUND3(D, A, B, C, 8, Sj, 34); -+ ROUND3(C, D, A, B, 11, Sk, 35); ROUND3(B, C, D, A, 14, Sl, 36); -+ ROUND3(A, B, C, D, 1, Si, 37); ROUND3(D, A, B, C, 4, Sj, 38); -+ ROUND3(C, D, A, B, 7, Sk, 39); ROUND3(B, C, D, A, 10, Sl, 40); -+ ROUND3(A, B, C, D, 13, Si, 41); ROUND3(D, A, B, C, 0, Sj, 42); -+ ROUND3(C, D, A, B, 3, Sk, 43); ROUND3(B, C, D, A, 6, Sl, 44); -+ ROUND3(A, B, C, D, 9, Si, 45); ROUND3(D, A, B, C, 12, Sj, 46); -+ ROUND3(C, D, A, B, 15, Sk, 47); ROUND3(B, C, D, A, 2, Sl, 48); -+ -+ ROUND4(A, B, C, D, 0, Sm, 49); ROUND4(D, A, B, C, 7, Sn, 50); -+ ROUND4(C, D, A, B, 14, So, 51); ROUND4(B, C, D, A, 5, Sp, 52); -+ ROUND4(A, B, C, D, 12, Sm, 53); ROUND4(D, A, B, C, 3, Sn, 54); -+ ROUND4(C, D, A, B, 10, So, 55); ROUND4(B, C, D, A, 1, Sp, 56); -+ ROUND4(A, B, C, D, 8, Sm, 57); ROUND4(D, A, B, C, 15, Sn, 58); -+ ROUND4(C, D, A, B, 6, So, 59); ROUND4(B, C, D, A, 13, Sp, 60); -+ ROUND4(A, B, C, D, 4, Sm, 61); ROUND4(D, A, B, C, 11, Sn, 62); -+ ROUND4(C, D, A, B, 2, So, 63); ROUND4(B, C, D, A, 9, Sp, 64); -+ -+ ctxt->md5_sta += A; -+ ctxt->md5_stb += B; -+ ctxt->md5_stc += C; -+ ctxt->md5_std += D; -+} -diff -Nur linux-3.0.4.orig/crypto/ocf/safe/md5.h linux-3.0.4/crypto/ocf/safe/md5.h ---- linux-3.0.4.orig/crypto/ocf/safe/md5.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/safe/md5.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,76 @@ -+/* $FreeBSD: src/sys/crypto/md5.h,v 1.4 2002/03/20 05:13:50 alfred Exp $ */ -+/* $KAME: md5.h,v 1.4 2000/03/27 04:36:22 sumikawa Exp $ */ -+ -+/* -+ * Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. Neither the name of the project nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ */ -+ -+#ifndef _NETINET6_MD5_H_ -+#define _NETINET6_MD5_H_ -+ -+#define MD5_BUFLEN 64 -+ -+typedef struct { -+ union { -+ u_int32_t md5_state32[4]; -+ u_int8_t md5_state8[16]; -+ } md5_st; -+ -+#define md5_sta md5_st.md5_state32[0] -+#define md5_stb md5_st.md5_state32[1] -+#define md5_stc md5_st.md5_state32[2] -+#define md5_std md5_st.md5_state32[3] -+#define md5_st8 md5_st.md5_state8 -+ -+ union { -+ u_int64_t md5_count64; -+ u_int8_t md5_count8[8]; -+ } md5_count; -+#define md5_n md5_count.md5_count64 -+#define md5_n8 md5_count.md5_count8 -+ -+ u_int md5_i; -+ u_int8_t md5_buf[MD5_BUFLEN]; -+} md5_ctxt; -+ -+extern void md5_init(md5_ctxt *); -+extern void md5_loop(md5_ctxt *, u_int8_t *, u_int); -+extern void md5_pad(md5_ctxt *); -+extern void md5_result(u_int8_t *, md5_ctxt *); -+ -+/* compatibility */ -+#define MD5_CTX md5_ctxt -+#define MD5Init(x) md5_init((x)) -+#define MD5Update(x, y, z) md5_loop((x), (y), (z)) -+#define MD5Final(x, y) \ -+do { \ -+ md5_pad((y)); \ -+ md5_result((x), (y)); \ -+} while (0) -+ -+#endif /* ! _NETINET6_MD5_H_*/ -diff -Nur linux-3.0.4.orig/crypto/ocf/safe/safe.c linux-3.0.4/crypto/ocf/safe/safe.c ---- linux-3.0.4.orig/crypto/ocf/safe/safe.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/safe/safe.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,2230 @@ -+/*- -+ * Linux port done by David McCullough -+ * Copyright (C) 2004-2010 David McCullough -+ * The license and original author are listed below. -+ * -+ * Copyright (c) 2003 Sam Leffler, Errno Consulting -+ * Copyright (c) 2003 Global Technology Associates, Inc. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ * -+__FBSDID("$FreeBSD: src/sys/dev/safe/safe.c,v 1.18 2007/03/21 03:42:50 sam Exp $"); -+ */ -+ -+#include -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* -+ * SafeNet SafeXcel-1141 hardware crypto accelerator -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#if 1 -+#define DPRINTF(a) do { \ -+ if (debug) { \ -+ printk("%s: ", sc ? \ -+ device_get_nameunit(sc->sc_dev) : "safe"); \ -+ printk a; \ -+ } \ -+ } while (0) -+#else -+#define DPRINTF(a) -+#endif -+ -+/* -+ * until we find a cleaner way, include the BSD md5/sha1 code -+ * here -+ */ -+#define HMAC_HACK 1 -+#ifdef HMAC_HACK -+#include -+#include -+#include -+#include -+#include -+#endif /* HMAC_HACK */ -+ -+/* add proc entry for this */ -+struct safe_stats safestats; -+ -+#define debug safe_debug -+int safe_debug = 0; -+module_param(safe_debug, int, 0644); -+MODULE_PARM_DESC(safe_debug, "Enable debug"); -+ -+static void safe_callback(struct safe_softc *, struct safe_ringentry *); -+static void safe_feed(struct safe_softc *, struct safe_ringentry *); -+#if defined(CONFIG_OCF_RANDOMHARVEST) && !defined(SAFE_NO_RNG) -+static void safe_rng_init(struct safe_softc *); -+int safe_rngbufsize = 8; /* 32 bytes each read */ -+module_param(safe_rngbufsize, int, 0644); -+MODULE_PARM_DESC(safe_rngbufsize, "RNG polling buffer size (32-bit words)"); -+int safe_rngmaxalarm = 8; /* max alarms before reset */ -+module_param(safe_rngmaxalarm, int, 0644); -+MODULE_PARM_DESC(safe_rngmaxalarm, "RNG max alarms before reset"); -+#endif /* SAFE_NO_RNG */ -+ -+static void safe_totalreset(struct safe_softc *sc); -+static int safe_dmamap_aligned(struct safe_softc *sc, const struct safe_operand *op); -+static int safe_dmamap_uniform(struct safe_softc *sc, const struct safe_operand *op); -+static int safe_free_entry(struct safe_softc *sc, struct safe_ringentry *re); -+static int safe_kprocess(device_t dev, struct cryptkop *krp, int hint); -+static int safe_kstart(struct safe_softc *sc); -+static int safe_ksigbits(struct safe_softc *sc, struct crparam *cr); -+static void safe_kfeed(struct safe_softc *sc); -+static void safe_kpoll(unsigned long arg); -+static void safe_kload_reg(struct safe_softc *sc, u_int32_t off, -+ u_int32_t len, struct crparam *n); -+ -+static int safe_newsession(device_t, u_int32_t *, struct cryptoini *); -+static int safe_freesession(device_t, u_int64_t); -+static int safe_process(device_t, struct cryptop *, int); -+ -+static device_method_t safe_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, safe_newsession), -+ DEVMETHOD(cryptodev_freesession,safe_freesession), -+ DEVMETHOD(cryptodev_process, safe_process), -+ DEVMETHOD(cryptodev_kprocess, safe_kprocess), -+}; -+ -+#define READ_REG(sc,r) readl((sc)->sc_base_addr + (r)) -+#define WRITE_REG(sc,r,val) writel((val), (sc)->sc_base_addr + (r)) -+ -+#define SAFE_MAX_CHIPS 8 -+static struct safe_softc *safe_chip_idx[SAFE_MAX_CHIPS]; -+ -+/* -+ * split our buffers up into safe DMAable byte fragments to avoid lockup -+ * bug in 1141 HW on rev 1.0. -+ */ -+ -+static int -+pci_map_linear( -+ struct safe_softc *sc, -+ struct safe_operand *buf, -+ void *addr, -+ int len) -+{ -+ dma_addr_t tmp; -+ int chunk, tlen = len; -+ -+ tmp = pci_map_single(sc->sc_pcidev, addr, len, PCI_DMA_BIDIRECTIONAL); -+ -+ buf->mapsize += len; -+ while (len > 0) { -+ chunk = (len > sc->sc_max_dsize) ? sc->sc_max_dsize : len; -+ buf->segs[buf->nsegs].ds_addr = tmp; -+ buf->segs[buf->nsegs].ds_len = chunk; -+ buf->segs[buf->nsegs].ds_tlen = tlen; -+ buf->nsegs++; -+ tmp += chunk; -+ len -= chunk; -+ tlen = 0; -+ } -+ return 0; -+} -+ -+/* -+ * map in a given uio buffer (great on some arches :-) -+ */ -+ -+static int -+pci_map_uio(struct safe_softc *sc, struct safe_operand *buf, struct uio *uio) -+{ -+ struct iovec *iov = uio->uio_iov; -+ int n; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ buf->mapsize = 0; -+ buf->nsegs = 0; -+ -+ for (n = 0; n < uio->uio_iovcnt; n++) { -+ pci_map_linear(sc, buf, iov->iov_base, iov->iov_len); -+ iov++; -+ } -+ -+ /* identify this buffer by the first segment */ -+ buf->map = (void *) buf->segs[0].ds_addr; -+ return(0); -+} -+ -+/* -+ * map in a given sk_buff -+ */ -+ -+static int -+pci_map_skb(struct safe_softc *sc,struct safe_operand *buf,struct sk_buff *skb) -+{ -+ int i; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ buf->mapsize = 0; -+ buf->nsegs = 0; -+ -+ pci_map_linear(sc, buf, skb->data, skb_headlen(skb)); -+ -+ for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { -+ pci_map_linear(sc, buf, -+ page_address(skb_shinfo(skb)->frags[i].page) + -+ skb_shinfo(skb)->frags[i].page_offset, -+ skb_shinfo(skb)->frags[i].size); -+ } -+ -+ /* identify this buffer by the first segment */ -+ buf->map = (void *) buf->segs[0].ds_addr; -+ return(0); -+} -+ -+ -+#if 0 /* not needed at this time */ -+static void -+pci_sync_operand(struct safe_softc *sc, struct safe_operand *buf) -+{ -+ int i; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ for (i = 0; i < buf->nsegs; i++) -+ pci_dma_sync_single_for_cpu(sc->sc_pcidev, buf->segs[i].ds_addr, -+ buf->segs[i].ds_len, PCI_DMA_BIDIRECTIONAL); -+} -+#endif -+ -+static void -+pci_unmap_operand(struct safe_softc *sc, struct safe_operand *buf) -+{ -+ int i; -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ for (i = 0; i < buf->nsegs; i++) { -+ if (buf->segs[i].ds_tlen) { -+ DPRINTF(("%s - unmap %d 0x%x %d\n", __FUNCTION__, i, buf->segs[i].ds_addr, buf->segs[i].ds_tlen)); -+ pci_unmap_single(sc->sc_pcidev, buf->segs[i].ds_addr, -+ buf->segs[i].ds_tlen, PCI_DMA_BIDIRECTIONAL); -+ DPRINTF(("%s - unmap %d 0x%x %d done\n", __FUNCTION__, i, buf->segs[i].ds_addr, buf->segs[i].ds_tlen)); -+ } -+ buf->segs[i].ds_addr = 0; -+ buf->segs[i].ds_len = 0; -+ buf->segs[i].ds_tlen = 0; -+ } -+ buf->nsegs = 0; -+ buf->mapsize = 0; -+ buf->map = 0; -+} -+ -+ -+/* -+ * SafeXcel Interrupt routine -+ */ -+static irqreturn_t -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) -+safe_intr(int irq, void *arg) -+#else -+safe_intr(int irq, void *arg, struct pt_regs *regs) -+#endif -+{ -+ struct safe_softc *sc = arg; -+ int stat; -+ unsigned long flags; -+ -+ stat = READ_REG(sc, SAFE_HM_STAT); -+ -+ DPRINTF(("%s(stat=0x%x)\n", __FUNCTION__, stat)); -+ -+ if (stat == 0) /* shared irq, not for us */ -+ return IRQ_NONE; -+ -+ WRITE_REG(sc, SAFE_HI_CLR, stat); /* IACK */ -+ -+ if ((stat & SAFE_INT_PE_DDONE)) { -+ /* -+ * Descriptor(s) done; scan the ring and -+ * process completed operations. -+ */ -+ spin_lock_irqsave(&sc->sc_ringmtx, flags); -+ while (sc->sc_back != sc->sc_front) { -+ struct safe_ringentry *re = sc->sc_back; -+ -+#ifdef SAFE_DEBUG -+ if (debug) { -+ safe_dump_ringstate(sc, __func__); -+ safe_dump_request(sc, __func__, re); -+ } -+#endif -+ /* -+ * safe_process marks ring entries that were allocated -+ * but not used with a csr of zero. This insures the -+ * ring front pointer never needs to be set backwards -+ * in the event that an entry is allocated but not used -+ * because of a setup error. -+ */ -+ DPRINTF(("%s re->re_desc.d_csr=0x%x\n", __FUNCTION__, re->re_desc.d_csr)); -+ if (re->re_desc.d_csr != 0) { -+ if (!SAFE_PE_CSR_IS_DONE(re->re_desc.d_csr)) { -+ DPRINTF(("%s !CSR_IS_DONE\n", __FUNCTION__)); -+ break; -+ } -+ if (!SAFE_PE_LEN_IS_DONE(re->re_desc.d_len)) { -+ DPRINTF(("%s !LEN_IS_DONE\n", __FUNCTION__)); -+ break; -+ } -+ sc->sc_nqchip--; -+ safe_callback(sc, re); -+ } -+ if (++(sc->sc_back) == sc->sc_ringtop) -+ sc->sc_back = sc->sc_ring; -+ } -+ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); -+ } -+ -+ /* -+ * Check to see if we got any DMA Error -+ */ -+ if (stat & SAFE_INT_PE_ERROR) { -+ printk("%s: dmaerr dmastat %08x\n", device_get_nameunit(sc->sc_dev), -+ (int)READ_REG(sc, SAFE_PE_DMASTAT)); -+ safestats.st_dmaerr++; -+ safe_totalreset(sc); -+#if 0 -+ safe_feed(sc); -+#endif -+ } -+ -+ if (sc->sc_needwakeup) { /* XXX check high watermark */ -+ int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); -+ DPRINTF(("%s: wakeup crypto %x\n", __func__, -+ sc->sc_needwakeup)); -+ sc->sc_needwakeup &= ~wakeup; -+ crypto_unblock(sc->sc_cid, wakeup); -+ } -+ -+ return IRQ_HANDLED; -+} -+ -+/* -+ * safe_feed() - post a request to chip -+ */ -+static void -+safe_feed(struct safe_softc *sc, struct safe_ringentry *re) -+{ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+#ifdef SAFE_DEBUG -+ if (debug) { -+ safe_dump_ringstate(sc, __func__); -+ safe_dump_request(sc, __func__, re); -+ } -+#endif -+ sc->sc_nqchip++; -+ if (sc->sc_nqchip > safestats.st_maxqchip) -+ safestats.st_maxqchip = sc->sc_nqchip; -+ /* poke h/w to check descriptor ring, any value can be written */ -+ WRITE_REG(sc, SAFE_HI_RD_DESCR, 0); -+} -+ -+#define N(a) (sizeof(a) / sizeof (a[0])) -+static void -+safe_setup_enckey(struct safe_session *ses, caddr_t key) -+{ -+ int i; -+ -+ bcopy(key, ses->ses_key, ses->ses_klen / 8); -+ -+ /* PE is little-endian, insure proper byte order */ -+ for (i = 0; i < N(ses->ses_key); i++) -+ ses->ses_key[i] = htole32(ses->ses_key[i]); -+} -+ -+static void -+safe_setup_mackey(struct safe_session *ses, int algo, caddr_t key, int klen) -+{ -+#ifdef HMAC_HACK -+ MD5_CTX md5ctx; -+ SHA1_CTX sha1ctx; -+ int i; -+ -+ -+ for (i = 0; i < klen; i++) -+ key[i] ^= HMAC_IPAD_VAL; -+ -+ if (algo == CRYPTO_MD5_HMAC) { -+ MD5Init(&md5ctx); -+ MD5Update(&md5ctx, key, klen); -+ MD5Update(&md5ctx, hmac_ipad_buffer, MD5_HMAC_BLOCK_LEN - klen); -+ bcopy(md5ctx.md5_st8, ses->ses_hminner, sizeof(md5ctx.md5_st8)); -+ } else { -+ SHA1Init(&sha1ctx); -+ SHA1Update(&sha1ctx, key, klen); -+ SHA1Update(&sha1ctx, hmac_ipad_buffer, -+ SHA1_HMAC_BLOCK_LEN - klen); -+ bcopy(sha1ctx.h.b32, ses->ses_hminner, sizeof(sha1ctx.h.b32)); -+ } -+ -+ for (i = 0; i < klen; i++) -+ key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); -+ -+ if (algo == CRYPTO_MD5_HMAC) { -+ MD5Init(&md5ctx); -+ MD5Update(&md5ctx, key, klen); -+ MD5Update(&md5ctx, hmac_opad_buffer, MD5_HMAC_BLOCK_LEN - klen); -+ bcopy(md5ctx.md5_st8, ses->ses_hmouter, sizeof(md5ctx.md5_st8)); -+ } else { -+ SHA1Init(&sha1ctx); -+ SHA1Update(&sha1ctx, key, klen); -+ SHA1Update(&sha1ctx, hmac_opad_buffer, -+ SHA1_HMAC_BLOCK_LEN - klen); -+ bcopy(sha1ctx.h.b32, ses->ses_hmouter, sizeof(sha1ctx.h.b32)); -+ } -+ -+ for (i = 0; i < klen; i++) -+ key[i] ^= HMAC_OPAD_VAL; -+ -+#if 0 -+ /* -+ * this code prevents SHA working on a BE host, -+ * so it is obviously wrong. I think the byte -+ * swap setup we do with the chip fixes this for us -+ */ -+ -+ /* PE is little-endian, insure proper byte order */ -+ for (i = 0; i < N(ses->ses_hminner); i++) { -+ ses->ses_hminner[i] = htole32(ses->ses_hminner[i]); -+ ses->ses_hmouter[i] = htole32(ses->ses_hmouter[i]); -+ } -+#endif -+#else /* HMAC_HACK */ -+ printk("safe: md5/sha not implemented\n"); -+#endif /* HMAC_HACK */ -+} -+#undef N -+ -+/* -+ * Allocate a new 'session' and return an encoded session id. 'sidp' -+ * contains our registration id, and should contain an encoded session -+ * id on successful allocation. -+ */ -+static int -+safe_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) -+{ -+ struct safe_softc *sc = device_get_softc(dev); -+ struct cryptoini *c, *encini = NULL, *macini = NULL; -+ struct safe_session *ses = NULL; -+ int sesn; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (sidp == NULL || cri == NULL || sc == NULL) -+ return (EINVAL); -+ -+ for (c = cri; c != NULL; c = c->cri_next) { -+ if (c->cri_alg == CRYPTO_MD5_HMAC || -+ c->cri_alg == CRYPTO_SHA1_HMAC || -+ c->cri_alg == CRYPTO_NULL_HMAC) { -+ if (macini) -+ return (EINVAL); -+ macini = c; -+ } else if (c->cri_alg == CRYPTO_DES_CBC || -+ c->cri_alg == CRYPTO_3DES_CBC || -+ c->cri_alg == CRYPTO_AES_CBC || -+ c->cri_alg == CRYPTO_NULL_CBC) { -+ if (encini) -+ return (EINVAL); -+ encini = c; -+ } else -+ return (EINVAL); -+ } -+ if (encini == NULL && macini == NULL) -+ return (EINVAL); -+ if (encini) { /* validate key length */ -+ switch (encini->cri_alg) { -+ case CRYPTO_DES_CBC: -+ if (encini->cri_klen != 64) -+ return (EINVAL); -+ break; -+ case CRYPTO_3DES_CBC: -+ if (encini->cri_klen != 192) -+ return (EINVAL); -+ break; -+ case CRYPTO_AES_CBC: -+ if (encini->cri_klen != 128 && -+ encini->cri_klen != 192 && -+ encini->cri_klen != 256) -+ return (EINVAL); -+ break; -+ } -+ } -+ -+ if (sc->sc_sessions == NULL) { -+ ses = sc->sc_sessions = (struct safe_session *) -+ kmalloc(sizeof(struct safe_session), SLAB_ATOMIC); -+ if (ses == NULL) -+ return (ENOMEM); -+ memset(ses, 0, sizeof(struct safe_session)); -+ sesn = 0; -+ sc->sc_nsessions = 1; -+ } else { -+ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { -+ if (sc->sc_sessions[sesn].ses_used == 0) { -+ ses = &sc->sc_sessions[sesn]; -+ break; -+ } -+ } -+ -+ if (ses == NULL) { -+ sesn = sc->sc_nsessions; -+ ses = (struct safe_session *) -+ kmalloc((sesn + 1) * sizeof(struct safe_session), SLAB_ATOMIC); -+ if (ses == NULL) -+ return (ENOMEM); -+ memset(ses, 0, (sesn + 1) * sizeof(struct safe_session)); -+ bcopy(sc->sc_sessions, ses, sesn * -+ sizeof(struct safe_session)); -+ bzero(sc->sc_sessions, sesn * -+ sizeof(struct safe_session)); -+ kfree(sc->sc_sessions); -+ sc->sc_sessions = ses; -+ ses = &sc->sc_sessions[sesn]; -+ sc->sc_nsessions++; -+ } -+ } -+ -+ bzero(ses, sizeof(struct safe_session)); -+ ses->ses_used = 1; -+ -+ if (encini) { -+ ses->ses_klen = encini->cri_klen; -+ if (encini->cri_key != NULL) -+ safe_setup_enckey(ses, encini->cri_key); -+ } -+ -+ if (macini) { -+ ses->ses_mlen = macini->cri_mlen; -+ if (ses->ses_mlen == 0) { -+ if (macini->cri_alg == CRYPTO_MD5_HMAC) -+ ses->ses_mlen = MD5_HASH_LEN; -+ else -+ ses->ses_mlen = SHA1_HASH_LEN; -+ } -+ -+ if (macini->cri_key != NULL) { -+ safe_setup_mackey(ses, macini->cri_alg, macini->cri_key, -+ macini->cri_klen / 8); -+ } -+ } -+ -+ *sidp = SAFE_SID(device_get_unit(sc->sc_dev), sesn); -+ return (0); -+} -+ -+/* -+ * Deallocate a session. -+ */ -+static int -+safe_freesession(device_t dev, u_int64_t tid) -+{ -+ struct safe_softc *sc = device_get_softc(dev); -+ int session, ret; -+ u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (sc == NULL) -+ return (EINVAL); -+ -+ session = SAFE_SESSION(sid); -+ if (session < sc->sc_nsessions) { -+ bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session])); -+ ret = 0; -+ } else -+ ret = EINVAL; -+ return (ret); -+} -+ -+ -+static int -+safe_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ struct safe_softc *sc = device_get_softc(dev); -+ int err = 0, i, nicealign, uniform; -+ struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; -+ int bypass, oplen, ivsize; -+ caddr_t iv; -+ int16_t coffset; -+ struct safe_session *ses; -+ struct safe_ringentry *re; -+ struct safe_sarec *sa; -+ struct safe_pdesc *pd; -+ u_int32_t cmd0, cmd1, staterec, rand_iv[4]; -+ unsigned long flags; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { -+ safestats.st_invalid++; -+ return (EINVAL); -+ } -+ if (SAFE_SESSION(crp->crp_sid) >= sc->sc_nsessions) { -+ safestats.st_badsession++; -+ return (EINVAL); -+ } -+ -+ spin_lock_irqsave(&sc->sc_ringmtx, flags); -+ if (sc->sc_front == sc->sc_back && sc->sc_nqchip != 0) { -+ safestats.st_ringfull++; -+ sc->sc_needwakeup |= CRYPTO_SYMQ; -+ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); -+ return (ERESTART); -+ } -+ re = sc->sc_front; -+ -+ staterec = re->re_sa.sa_staterec; /* save */ -+ /* NB: zero everything but the PE descriptor */ -+ bzero(&re->re_sa, sizeof(struct safe_ringentry) - sizeof(re->re_desc)); -+ re->re_sa.sa_staterec = staterec; /* restore */ -+ -+ re->re_crp = crp; -+ re->re_sesn = SAFE_SESSION(crp->crp_sid); -+ -+ re->re_src.nsegs = 0; -+ re->re_dst.nsegs = 0; -+ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ re->re_src_skb = (struct sk_buff *)crp->crp_buf; -+ re->re_dst_skb = (struct sk_buff *)crp->crp_buf; -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ re->re_src_io = (struct uio *)crp->crp_buf; -+ re->re_dst_io = (struct uio *)crp->crp_buf; -+ } else { -+ safestats.st_badflags++; -+ err = EINVAL; -+ goto errout; /* XXX we don't handle contiguous blocks! */ -+ } -+ -+ sa = &re->re_sa; -+ ses = &sc->sc_sessions[re->re_sesn]; -+ -+ crd1 = crp->crp_desc; -+ if (crd1 == NULL) { -+ safestats.st_nodesc++; -+ err = EINVAL; -+ goto errout; -+ } -+ crd2 = crd1->crd_next; -+ -+ cmd0 = SAFE_SA_CMD0_BASIC; /* basic group operation */ -+ cmd1 = 0; -+ if (crd2 == NULL) { -+ if (crd1->crd_alg == CRYPTO_MD5_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1_HMAC || -+ crd1->crd_alg == CRYPTO_NULL_HMAC) { -+ maccrd = crd1; -+ enccrd = NULL; -+ cmd0 |= SAFE_SA_CMD0_OP_HASH; -+ } else if (crd1->crd_alg == CRYPTO_DES_CBC || -+ crd1->crd_alg == CRYPTO_3DES_CBC || -+ crd1->crd_alg == CRYPTO_AES_CBC || -+ crd1->crd_alg == CRYPTO_NULL_CBC) { -+ maccrd = NULL; -+ enccrd = crd1; -+ cmd0 |= SAFE_SA_CMD0_OP_CRYPT; -+ } else { -+ safestats.st_badalg++; -+ err = EINVAL; -+ goto errout; -+ } -+ } else { -+ if ((crd1->crd_alg == CRYPTO_MD5_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1_HMAC || -+ crd1->crd_alg == CRYPTO_NULL_HMAC) && -+ (crd2->crd_alg == CRYPTO_DES_CBC || -+ crd2->crd_alg == CRYPTO_3DES_CBC || -+ crd2->crd_alg == CRYPTO_AES_CBC || -+ crd2->crd_alg == CRYPTO_NULL_CBC) && -+ ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { -+ maccrd = crd1; -+ enccrd = crd2; -+ } else if ((crd1->crd_alg == CRYPTO_DES_CBC || -+ crd1->crd_alg == CRYPTO_3DES_CBC || -+ crd1->crd_alg == CRYPTO_AES_CBC || -+ crd1->crd_alg == CRYPTO_NULL_CBC) && -+ (crd2->crd_alg == CRYPTO_MD5_HMAC || -+ crd2->crd_alg == CRYPTO_SHA1_HMAC || -+ crd2->crd_alg == CRYPTO_NULL_HMAC) && -+ (crd1->crd_flags & CRD_F_ENCRYPT)) { -+ enccrd = crd1; -+ maccrd = crd2; -+ } else { -+ safestats.st_badalg++; -+ err = EINVAL; -+ goto errout; -+ } -+ cmd0 |= SAFE_SA_CMD0_OP_BOTH; -+ } -+ -+ if (enccrd) { -+ if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) -+ safe_setup_enckey(ses, enccrd->crd_key); -+ -+ if (enccrd->crd_alg == CRYPTO_DES_CBC) { -+ cmd0 |= SAFE_SA_CMD0_DES; -+ cmd1 |= SAFE_SA_CMD1_CBC; -+ ivsize = 2*sizeof(u_int32_t); -+ } else if (enccrd->crd_alg == CRYPTO_3DES_CBC) { -+ cmd0 |= SAFE_SA_CMD0_3DES; -+ cmd1 |= SAFE_SA_CMD1_CBC; -+ ivsize = 2*sizeof(u_int32_t); -+ } else if (enccrd->crd_alg == CRYPTO_AES_CBC) { -+ cmd0 |= SAFE_SA_CMD0_AES; -+ cmd1 |= SAFE_SA_CMD1_CBC; -+ if (ses->ses_klen == 128) -+ cmd1 |= SAFE_SA_CMD1_AES128; -+ else if (ses->ses_klen == 192) -+ cmd1 |= SAFE_SA_CMD1_AES192; -+ else -+ cmd1 |= SAFE_SA_CMD1_AES256; -+ ivsize = 4*sizeof(u_int32_t); -+ } else { -+ cmd0 |= SAFE_SA_CMD0_CRYPT_NULL; -+ ivsize = 0; -+ } -+ -+ /* -+ * Setup encrypt/decrypt state. When using basic ops -+ * we can't use an inline IV because hash/crypt offset -+ * must be from the end of the IV to the start of the -+ * crypt data and this leaves out the preceding header -+ * from the hash calculation. Instead we place the IV -+ * in the state record and set the hash/crypt offset to -+ * copy both the header+IV. -+ */ -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) { -+ cmd0 |= SAFE_SA_CMD0_OUTBOUND; -+ -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) -+ iv = enccrd->crd_iv; -+ else -+ read_random((iv = (caddr_t) &rand_iv[0]), sizeof(rand_iv)); -+ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ enccrd->crd_inject, ivsize, iv); -+ } -+ bcopy(iv, re->re_sastate.sa_saved_iv, ivsize); -+ /* make iv LE */ -+ for (i = 0; i < ivsize/sizeof(re->re_sastate.sa_saved_iv[0]); i++) -+ re->re_sastate.sa_saved_iv[i] = -+ cpu_to_le32(re->re_sastate.sa_saved_iv[i]); -+ cmd0 |= SAFE_SA_CMD0_IVLD_STATE | SAFE_SA_CMD0_SAVEIV; -+ re->re_flags |= SAFE_QFLAGS_COPYOUTIV; -+ } else { -+ cmd0 |= SAFE_SA_CMD0_INBOUND; -+ -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) { -+ bcopy(enccrd->crd_iv, -+ re->re_sastate.sa_saved_iv, ivsize); -+ } else { -+ crypto_copydata(crp->crp_flags, crp->crp_buf, -+ enccrd->crd_inject, ivsize, -+ (caddr_t)re->re_sastate.sa_saved_iv); -+ } -+ /* make iv LE */ -+ for (i = 0; i < ivsize/sizeof(re->re_sastate.sa_saved_iv[0]); i++) -+ re->re_sastate.sa_saved_iv[i] = -+ cpu_to_le32(re->re_sastate.sa_saved_iv[i]); -+ cmd0 |= SAFE_SA_CMD0_IVLD_STATE; -+ } -+ /* -+ * For basic encryption use the zero pad algorithm. -+ * This pads results to an 8-byte boundary and -+ * suppresses padding verification for inbound (i.e. -+ * decrypt) operations. -+ * -+ * NB: Not sure if the 8-byte pad boundary is a problem. -+ */ -+ cmd0 |= SAFE_SA_CMD0_PAD_ZERO; -+ -+ /* XXX assert key bufs have the same size */ -+ bcopy(ses->ses_key, sa->sa_key, sizeof(sa->sa_key)); -+ } -+ -+ if (maccrd) { -+ if (maccrd->crd_flags & CRD_F_KEY_EXPLICIT) { -+ safe_setup_mackey(ses, maccrd->crd_alg, -+ maccrd->crd_key, maccrd->crd_klen / 8); -+ } -+ -+ if (maccrd->crd_alg == CRYPTO_MD5_HMAC) { -+ cmd0 |= SAFE_SA_CMD0_MD5; -+ cmd1 |= SAFE_SA_CMD1_HMAC; /* NB: enable HMAC */ -+ } else if (maccrd->crd_alg == CRYPTO_SHA1_HMAC) { -+ cmd0 |= SAFE_SA_CMD0_SHA1; -+ cmd1 |= SAFE_SA_CMD1_HMAC; /* NB: enable HMAC */ -+ } else { -+ cmd0 |= SAFE_SA_CMD0_HASH_NULL; -+ } -+ /* -+ * Digest data is loaded from the SA and the hash -+ * result is saved to the state block where we -+ * retrieve it for return to the caller. -+ */ -+ /* XXX assert digest bufs have the same size */ -+ bcopy(ses->ses_hminner, sa->sa_indigest, -+ sizeof(sa->sa_indigest)); -+ bcopy(ses->ses_hmouter, sa->sa_outdigest, -+ sizeof(sa->sa_outdigest)); -+ -+ cmd0 |= SAFE_SA_CMD0_HSLD_SA | SAFE_SA_CMD0_SAVEHASH; -+ re->re_flags |= SAFE_QFLAGS_COPYOUTICV; -+ } -+ -+ if (enccrd && maccrd) { -+ /* -+ * The offset from hash data to the start of -+ * crypt data is the difference in the skips. -+ */ -+ bypass = maccrd->crd_skip; -+ coffset = enccrd->crd_skip - maccrd->crd_skip; -+ if (coffset < 0) { -+ DPRINTF(("%s: hash does not precede crypt; " -+ "mac skip %u enc skip %u\n", -+ __func__, maccrd->crd_skip, enccrd->crd_skip)); -+ safestats.st_skipmismatch++; -+ err = EINVAL; -+ goto errout; -+ } -+ oplen = enccrd->crd_skip + enccrd->crd_len; -+ if (maccrd->crd_skip + maccrd->crd_len != oplen) { -+ DPRINTF(("%s: hash amount %u != crypt amount %u\n", -+ __func__, maccrd->crd_skip + maccrd->crd_len, -+ oplen)); -+ safestats.st_lenmismatch++; -+ err = EINVAL; -+ goto errout; -+ } -+#ifdef SAFE_DEBUG -+ if (debug) { -+ printf("mac: skip %d, len %d, inject %d\n", -+ maccrd->crd_skip, maccrd->crd_len, -+ maccrd->crd_inject); -+ printf("enc: skip %d, len %d, inject %d\n", -+ enccrd->crd_skip, enccrd->crd_len, -+ enccrd->crd_inject); -+ printf("bypass %d coffset %d oplen %d\n", -+ bypass, coffset, oplen); -+ } -+#endif -+ if (coffset & 3) { /* offset must be 32-bit aligned */ -+ DPRINTF(("%s: coffset %u misaligned\n", -+ __func__, coffset)); -+ safestats.st_coffmisaligned++; -+ err = EINVAL; -+ goto errout; -+ } -+ coffset >>= 2; -+ if (coffset > 255) { /* offset must be <256 dwords */ -+ DPRINTF(("%s: coffset %u too big\n", -+ __func__, coffset)); -+ safestats.st_cofftoobig++; -+ err = EINVAL; -+ goto errout; -+ } -+ /* -+ * Tell the hardware to copy the header to the output. -+ * The header is defined as the data from the end of -+ * the bypass to the start of data to be encrypted. -+ * Typically this is the inline IV. Note that you need -+ * to do this even if src+dst are the same; it appears -+ * that w/o this bit the crypted data is written -+ * immediately after the bypass data. -+ */ -+ cmd1 |= SAFE_SA_CMD1_HDRCOPY; -+ /* -+ * Disable IP header mutable bit handling. This is -+ * needed to get correct HMAC calculations. -+ */ -+ cmd1 |= SAFE_SA_CMD1_MUTABLE; -+ } else { -+ if (enccrd) { -+ bypass = enccrd->crd_skip; -+ oplen = bypass + enccrd->crd_len; -+ } else { -+ bypass = maccrd->crd_skip; -+ oplen = bypass + maccrd->crd_len; -+ } -+ coffset = 0; -+ } -+ /* XXX verify multiple of 4 when using s/g */ -+ if (bypass > 96) { /* bypass offset must be <= 96 bytes */ -+ DPRINTF(("%s: bypass %u too big\n", __func__, bypass)); -+ safestats.st_bypasstoobig++; -+ err = EINVAL; -+ goto errout; -+ } -+ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ if (pci_map_skb(sc, &re->re_src, re->re_src_skb)) { -+ safestats.st_noload++; -+ err = ENOMEM; -+ goto errout; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ if (pci_map_uio(sc, &re->re_src, re->re_src_io)) { -+ safestats.st_noload++; -+ err = ENOMEM; -+ goto errout; -+ } -+ } -+ nicealign = safe_dmamap_aligned(sc, &re->re_src); -+ uniform = safe_dmamap_uniform(sc, &re->re_src); -+ -+ DPRINTF(("src nicealign %u uniform %u nsegs %u\n", -+ nicealign, uniform, re->re_src.nsegs)); -+ if (re->re_src.nsegs > 1) { -+ re->re_desc.d_src = sc->sc_spalloc.dma_paddr + -+ ((caddr_t) sc->sc_spfree - (caddr_t) sc->sc_spring); -+ for (i = 0; i < re->re_src_nsegs; i++) { -+ /* NB: no need to check if there's space */ -+ pd = sc->sc_spfree; -+ if (++(sc->sc_spfree) == sc->sc_springtop) -+ sc->sc_spfree = sc->sc_spring; -+ -+ KASSERT((pd->pd_flags&3) == 0 || -+ (pd->pd_flags&3) == SAFE_PD_DONE, -+ ("bogus source particle descriptor; flags %x", -+ pd->pd_flags)); -+ pd->pd_addr = re->re_src_segs[i].ds_addr; -+ pd->pd_size = re->re_src_segs[i].ds_len; -+ pd->pd_flags = SAFE_PD_READY; -+ } -+ cmd0 |= SAFE_SA_CMD0_IGATHER; -+ } else { -+ /* -+ * No need for gather, reference the operand directly. -+ */ -+ re->re_desc.d_src = re->re_src_segs[0].ds_addr; -+ } -+ -+ if (enccrd == NULL && maccrd != NULL) { -+ /* -+ * Hash op; no destination needed. -+ */ -+ } else { -+ if (crp->crp_flags & (CRYPTO_F_IOV|CRYPTO_F_SKBUF)) { -+ if (!nicealign) { -+ safestats.st_iovmisaligned++; -+ err = EINVAL; -+ goto errout; -+ } -+ if (uniform != 1) { -+ device_printf(sc->sc_dev, "!uniform source\n"); -+ if (!uniform) { -+ /* -+ * There's no way to handle the DMA -+ * requirements with this uio. We -+ * could create a separate DMA area for -+ * the result and then copy it back, -+ * but for now we just bail and return -+ * an error. Note that uio requests -+ * > SAFE_MAX_DSIZE are handled because -+ * the DMA map and segment list for the -+ * destination wil result in a -+ * destination particle list that does -+ * the necessary scatter DMA. -+ */ -+ safestats.st_iovnotuniform++; -+ err = EINVAL; -+ goto errout; -+ } -+ } else -+ re->re_dst = re->re_src; -+ } else { -+ safestats.st_badflags++; -+ err = EINVAL; -+ goto errout; -+ } -+ -+ if (re->re_dst.nsegs > 1) { -+ re->re_desc.d_dst = sc->sc_dpalloc.dma_paddr + -+ ((caddr_t) sc->sc_dpfree - (caddr_t) sc->sc_dpring); -+ for (i = 0; i < re->re_dst_nsegs; i++) { -+ pd = sc->sc_dpfree; -+ KASSERT((pd->pd_flags&3) == 0 || -+ (pd->pd_flags&3) == SAFE_PD_DONE, -+ ("bogus dest particle descriptor; flags %x", -+ pd->pd_flags)); -+ if (++(sc->sc_dpfree) == sc->sc_dpringtop) -+ sc->sc_dpfree = sc->sc_dpring; -+ pd->pd_addr = re->re_dst_segs[i].ds_addr; -+ pd->pd_flags = SAFE_PD_READY; -+ } -+ cmd0 |= SAFE_SA_CMD0_OSCATTER; -+ } else { -+ /* -+ * No need for scatter, reference the operand directly. -+ */ -+ re->re_desc.d_dst = re->re_dst_segs[0].ds_addr; -+ } -+ } -+ -+ /* -+ * All done with setup; fillin the SA command words -+ * and the packet engine descriptor. The operation -+ * is now ready for submission to the hardware. -+ */ -+ sa->sa_cmd0 = cmd0 | SAFE_SA_CMD0_IPCI | SAFE_SA_CMD0_OPCI; -+ sa->sa_cmd1 = cmd1 -+ | (coffset << SAFE_SA_CMD1_OFFSET_S) -+ | SAFE_SA_CMD1_SAREV1 /* Rev 1 SA data structure */ -+ | SAFE_SA_CMD1_SRPCI -+ ; -+ /* -+ * NB: the order of writes is important here. In case the -+ * chip is scanning the ring because of an outstanding request -+ * it might nab this one too. In that case we need to make -+ * sure the setup is complete before we write the length -+ * field of the descriptor as it signals the descriptor is -+ * ready for processing. -+ */ -+ re->re_desc.d_csr = SAFE_PE_CSR_READY | SAFE_PE_CSR_SAPCI; -+ if (maccrd) -+ re->re_desc.d_csr |= SAFE_PE_CSR_LOADSA | SAFE_PE_CSR_HASHFINAL; -+ wmb(); -+ re->re_desc.d_len = oplen -+ | SAFE_PE_LEN_READY -+ | (bypass << SAFE_PE_LEN_BYPASS_S) -+ ; -+ -+ safestats.st_ipackets++; -+ safestats.st_ibytes += oplen; -+ -+ if (++(sc->sc_front) == sc->sc_ringtop) -+ sc->sc_front = sc->sc_ring; -+ -+ /* XXX honor batching */ -+ safe_feed(sc, re); -+ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); -+ return (0); -+ -+errout: -+ if (re->re_src.map != re->re_dst.map) -+ pci_unmap_operand(sc, &re->re_dst); -+ if (re->re_src.map) -+ pci_unmap_operand(sc, &re->re_src); -+ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); -+ if (err != ERESTART) { -+ crp->crp_etype = err; -+ crypto_done(crp); -+ } else { -+ sc->sc_needwakeup |= CRYPTO_SYMQ; -+ } -+ return (err); -+} -+ -+static void -+safe_callback(struct safe_softc *sc, struct safe_ringentry *re) -+{ -+ struct cryptop *crp = (struct cryptop *)re->re_crp; -+ struct cryptodesc *crd; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ safestats.st_opackets++; -+ safestats.st_obytes += re->re_dst.mapsize; -+ -+ if (re->re_desc.d_csr & SAFE_PE_CSR_STATUS) { -+ device_printf(sc->sc_dev, "csr 0x%x cmd0 0x%x cmd1 0x%x\n", -+ re->re_desc.d_csr, -+ re->re_sa.sa_cmd0, re->re_sa.sa_cmd1); -+ safestats.st_peoperr++; -+ crp->crp_etype = EIO; /* something more meaningful? */ -+ } -+ -+ if (re->re_dst.map != NULL && re->re_dst.map != re->re_src.map) -+ pci_unmap_operand(sc, &re->re_dst); -+ pci_unmap_operand(sc, &re->re_src); -+ -+ /* -+ * If result was written to a differet mbuf chain, swap -+ * it in as the return value and reclaim the original. -+ */ -+ if ((crp->crp_flags & CRYPTO_F_SKBUF) && re->re_src_skb != re->re_dst_skb) { -+ device_printf(sc->sc_dev, "no CRYPTO_F_SKBUF swapping support\n"); -+ /* kfree_skb(skb) */ -+ /* crp->crp_buf = (caddr_t)re->re_dst_skb */ -+ return; -+ } -+ -+ if (re->re_flags & SAFE_QFLAGS_COPYOUTICV) { -+ /* copy out ICV result */ -+ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { -+ if (!(crd->crd_alg == CRYPTO_MD5_HMAC || -+ crd->crd_alg == CRYPTO_SHA1_HMAC || -+ crd->crd_alg == CRYPTO_NULL_HMAC)) -+ continue; -+ if (crd->crd_alg == CRYPTO_SHA1_HMAC) { -+ /* -+ * SHA-1 ICV's are byte-swapped; fix 'em up -+ * before copy them to their destination. -+ */ -+ re->re_sastate.sa_saved_indigest[0] = -+ cpu_to_be32(re->re_sastate.sa_saved_indigest[0]); -+ re->re_sastate.sa_saved_indigest[1] = -+ cpu_to_be32(re->re_sastate.sa_saved_indigest[1]); -+ re->re_sastate.sa_saved_indigest[2] = -+ cpu_to_be32(re->re_sastate.sa_saved_indigest[2]); -+ } else { -+ re->re_sastate.sa_saved_indigest[0] = -+ cpu_to_le32(re->re_sastate.sa_saved_indigest[0]); -+ re->re_sastate.sa_saved_indigest[1] = -+ cpu_to_le32(re->re_sastate.sa_saved_indigest[1]); -+ re->re_sastate.sa_saved_indigest[2] = -+ cpu_to_le32(re->re_sastate.sa_saved_indigest[2]); -+ } -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, -+ sc->sc_sessions[re->re_sesn].ses_mlen, -+ (caddr_t)re->re_sastate.sa_saved_indigest); -+ break; -+ } -+ } -+ crypto_done(crp); -+} -+ -+ -+#if defined(CONFIG_OCF_RANDOMHARVEST) && !defined(SAFE_NO_RNG) -+#define SAFE_RNG_MAXWAIT 1000 -+ -+static void -+safe_rng_init(struct safe_softc *sc) -+{ -+ u_int32_t w, v; -+ int i; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ WRITE_REG(sc, SAFE_RNG_CTRL, 0); -+ /* use default value according to the manual */ -+ WRITE_REG(sc, SAFE_RNG_CNFG, 0x834); /* magic from SafeNet */ -+ WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); -+ -+ /* -+ * There is a bug in rev 1.0 of the 1140 that when the RNG -+ * is brought out of reset the ready status flag does not -+ * work until the RNG has finished its internal initialization. -+ * -+ * So in order to determine the device is through its -+ * initialization we must read the data register, using the -+ * status reg in the read in case it is initialized. Then read -+ * the data register until it changes from the first read. -+ * Once it changes read the data register until it changes -+ * again. At this time the RNG is considered initialized. -+ * This could take between 750ms - 1000ms in time. -+ */ -+ i = 0; -+ w = READ_REG(sc, SAFE_RNG_OUT); -+ do { -+ v = READ_REG(sc, SAFE_RNG_OUT); -+ if (v != w) { -+ w = v; -+ break; -+ } -+ DELAY(10); -+ } while (++i < SAFE_RNG_MAXWAIT); -+ -+ /* Wait Until data changes again */ -+ i = 0; -+ do { -+ v = READ_REG(sc, SAFE_RNG_OUT); -+ if (v != w) -+ break; -+ DELAY(10); -+ } while (++i < SAFE_RNG_MAXWAIT); -+} -+ -+static __inline void -+safe_rng_disable_short_cycle(struct safe_softc *sc) -+{ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ WRITE_REG(sc, SAFE_RNG_CTRL, -+ READ_REG(sc, SAFE_RNG_CTRL) &~ SAFE_RNG_CTRL_SHORTEN); -+} -+ -+static __inline void -+safe_rng_enable_short_cycle(struct safe_softc *sc) -+{ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ WRITE_REG(sc, SAFE_RNG_CTRL, -+ READ_REG(sc, SAFE_RNG_CTRL) | SAFE_RNG_CTRL_SHORTEN); -+} -+ -+static __inline u_int32_t -+safe_rng_read(struct safe_softc *sc) -+{ -+ int i; -+ -+ i = 0; -+ while (READ_REG(sc, SAFE_RNG_STAT) != 0 && ++i < SAFE_RNG_MAXWAIT) -+ ; -+ return READ_REG(sc, SAFE_RNG_OUT); -+} -+ -+static int -+safe_read_random(void *arg, u_int32_t *buf, int maxwords) -+{ -+ struct safe_softc *sc = (struct safe_softc *) arg; -+ int i, rc; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ safestats.st_rng++; -+ /* -+ * Fetch the next block of data. -+ */ -+ if (maxwords > safe_rngbufsize) -+ maxwords = safe_rngbufsize; -+ if (maxwords > SAFE_RNG_MAXBUFSIZ) -+ maxwords = SAFE_RNG_MAXBUFSIZ; -+retry: -+ /* read as much as we can */ -+ for (rc = 0; rc < maxwords; rc++) { -+ if (READ_REG(sc, SAFE_RNG_STAT) != 0) -+ break; -+ buf[rc] = READ_REG(sc, SAFE_RNG_OUT); -+ } -+ if (rc == 0) -+ return 0; -+ /* -+ * Check the comparator alarm count and reset the h/w if -+ * it exceeds our threshold. This guards against the -+ * hardware oscillators resonating with external signals. -+ */ -+ if (READ_REG(sc, SAFE_RNG_ALM_CNT) > safe_rngmaxalarm) { -+ u_int32_t freq_inc, w; -+ -+ DPRINTF(("%s: alarm count %u exceeds threshold %u\n", __func__, -+ (unsigned)READ_REG(sc, SAFE_RNG_ALM_CNT), safe_rngmaxalarm)); -+ safestats.st_rngalarm++; -+ safe_rng_enable_short_cycle(sc); -+ freq_inc = 18; -+ for (i = 0; i < 64; i++) { -+ w = READ_REG(sc, SAFE_RNG_CNFG); -+ freq_inc = ((w + freq_inc) & 0x3fL); -+ w = ((w & ~0x3fL) | freq_inc); -+ WRITE_REG(sc, SAFE_RNG_CNFG, w); -+ -+ WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); -+ -+ (void) safe_rng_read(sc); -+ DELAY(25); -+ -+ if (READ_REG(sc, SAFE_RNG_ALM_CNT) == 0) { -+ safe_rng_disable_short_cycle(sc); -+ goto retry; -+ } -+ freq_inc = 1; -+ } -+ safe_rng_disable_short_cycle(sc); -+ } else -+ WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); -+ -+ return(rc); -+} -+#endif /* defined(CONFIG_OCF_RANDOMHARVEST) && !defined(SAFE_NO_RNG) */ -+ -+ -+/* -+ * Resets the board. Values in the regesters are left as is -+ * from the reset (i.e. initial values are assigned elsewhere). -+ */ -+static void -+safe_reset_board(struct safe_softc *sc) -+{ -+ u_int32_t v; -+ /* -+ * Reset the device. The manual says no delay -+ * is needed between marking and clearing reset. -+ */ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ v = READ_REG(sc, SAFE_PE_DMACFG) &~ -+ (SAFE_PE_DMACFG_PERESET | SAFE_PE_DMACFG_PDRRESET | -+ SAFE_PE_DMACFG_SGRESET); -+ WRITE_REG(sc, SAFE_PE_DMACFG, v -+ | SAFE_PE_DMACFG_PERESET -+ | SAFE_PE_DMACFG_PDRRESET -+ | SAFE_PE_DMACFG_SGRESET); -+ WRITE_REG(sc, SAFE_PE_DMACFG, v); -+} -+ -+/* -+ * Initialize registers we need to touch only once. -+ */ -+static void -+safe_init_board(struct safe_softc *sc) -+{ -+ u_int32_t v, dwords; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ v = READ_REG(sc, SAFE_PE_DMACFG); -+ v &=~ ( SAFE_PE_DMACFG_PEMODE -+ | SAFE_PE_DMACFG_FSENA /* failsafe enable */ -+ | SAFE_PE_DMACFG_GPRPCI /* gather ring on PCI */ -+ | SAFE_PE_DMACFG_SPRPCI /* scatter ring on PCI */ -+ | SAFE_PE_DMACFG_ESDESC /* endian-swap descriptors */ -+ | SAFE_PE_DMACFG_ESPDESC /* endian-swap part. desc's */ -+ | SAFE_PE_DMACFG_ESSA /* endian-swap SA's */ -+ | SAFE_PE_DMACFG_ESPACKET /* swap the packet data */ -+ ); -+ v |= SAFE_PE_DMACFG_FSENA /* failsafe enable */ -+ | SAFE_PE_DMACFG_GPRPCI /* gather ring on PCI */ -+ | SAFE_PE_DMACFG_SPRPCI /* scatter ring on PCI */ -+ | SAFE_PE_DMACFG_ESDESC /* endian-swap descriptors */ -+ | SAFE_PE_DMACFG_ESPDESC /* endian-swap part. desc's */ -+ | SAFE_PE_DMACFG_ESSA /* endian-swap SA's */ -+#if 0 -+ | SAFE_PE_DMACFG_ESPACKET /* swap the packet data */ -+#endif -+ ; -+ WRITE_REG(sc, SAFE_PE_DMACFG, v); -+ -+#ifdef __BIG_ENDIAN -+ /* tell the safenet that we are 4321 and not 1234 */ -+ WRITE_REG(sc, SAFE_ENDIAN, 0xe4e41b1b); -+#endif -+ -+ if (sc->sc_chiprev == SAFE_REV(1,0)) { -+ /* -+ * Avoid large PCI DMA transfers. Rev 1.0 has a bug where -+ * "target mode transfers" done while the chip is DMA'ing -+ * >1020 bytes cause the hardware to lockup. To avoid this -+ * we reduce the max PCI transfer size and use small source -+ * particle descriptors (<= 256 bytes). -+ */ -+ WRITE_REG(sc, SAFE_DMA_CFG, 256); -+ device_printf(sc->sc_dev, -+ "Reduce max DMA size to %u words for rev %u.%u WAR\n", -+ (unsigned) ((READ_REG(sc, SAFE_DMA_CFG)>>2) & 0xff), -+ (unsigned) SAFE_REV_MAJ(sc->sc_chiprev), -+ (unsigned) SAFE_REV_MIN(sc->sc_chiprev)); -+ sc->sc_max_dsize = 256; -+ } else { -+ sc->sc_max_dsize = SAFE_MAX_DSIZE; -+ } -+ -+ /* NB: operands+results are overlaid */ -+ WRITE_REG(sc, SAFE_PE_PDRBASE, sc->sc_ringalloc.dma_paddr); -+ WRITE_REG(sc, SAFE_PE_RDRBASE, sc->sc_ringalloc.dma_paddr); -+ /* -+ * Configure ring entry size and number of items in the ring. -+ */ -+ KASSERT((sizeof(struct safe_ringentry) % sizeof(u_int32_t)) == 0, -+ ("PE ring entry not 32-bit aligned!")); -+ dwords = sizeof(struct safe_ringentry) / sizeof(u_int32_t); -+ WRITE_REG(sc, SAFE_PE_RINGCFG, -+ (dwords << SAFE_PE_RINGCFG_OFFSET_S) | SAFE_MAX_NQUEUE); -+ WRITE_REG(sc, SAFE_PE_RINGPOLL, 0); /* disable polling */ -+ -+ WRITE_REG(sc, SAFE_PE_GRNGBASE, sc->sc_spalloc.dma_paddr); -+ WRITE_REG(sc, SAFE_PE_SRNGBASE, sc->sc_dpalloc.dma_paddr); -+ WRITE_REG(sc, SAFE_PE_PARTSIZE, -+ (SAFE_TOTAL_DPART<<16) | SAFE_TOTAL_SPART); -+ /* -+ * NB: destination particles are fixed size. We use -+ * an mbuf cluster and require all results go to -+ * clusters or smaller. -+ */ -+ WRITE_REG(sc, SAFE_PE_PARTCFG, sc->sc_max_dsize); -+ -+ /* it's now safe to enable PE mode, do it */ -+ WRITE_REG(sc, SAFE_PE_DMACFG, v | SAFE_PE_DMACFG_PEMODE); -+ -+ /* -+ * Configure hardware to use level-triggered interrupts and -+ * to interrupt after each descriptor is processed. -+ */ -+ WRITE_REG(sc, SAFE_HI_CFG, SAFE_HI_CFG_LEVEL); -+ WRITE_REG(sc, SAFE_HI_CLR, 0xffffffff); -+ WRITE_REG(sc, SAFE_HI_DESC_CNT, 1); -+ WRITE_REG(sc, SAFE_HI_MASK, SAFE_INT_PE_DDONE | SAFE_INT_PE_ERROR); -+} -+ -+ -+/* -+ * Clean up after a chip crash. -+ * It is assumed that the caller in splimp() -+ */ -+static void -+safe_cleanchip(struct safe_softc *sc) -+{ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (sc->sc_nqchip != 0) { -+ struct safe_ringentry *re = sc->sc_back; -+ -+ while (re != sc->sc_front) { -+ if (re->re_desc.d_csr != 0) -+ safe_free_entry(sc, re); -+ if (++re == sc->sc_ringtop) -+ re = sc->sc_ring; -+ } -+ sc->sc_back = re; -+ sc->sc_nqchip = 0; -+ } -+} -+ -+/* -+ * free a safe_q -+ * It is assumed that the caller is within splimp(). -+ */ -+static int -+safe_free_entry(struct safe_softc *sc, struct safe_ringentry *re) -+{ -+ struct cryptop *crp; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ /* -+ * Free header MCR -+ */ -+ if ((re->re_dst_skb != NULL) && (re->re_src_skb != re->re_dst_skb)) -+#ifdef NOTYET -+ m_freem(re->re_dst_m); -+#else -+ printk("%s,%d: SKB not supported\n", __FILE__, __LINE__); -+#endif -+ -+ crp = (struct cryptop *)re->re_crp; -+ -+ re->re_desc.d_csr = 0; -+ -+ crp->crp_etype = EFAULT; -+ crypto_done(crp); -+ return(0); -+} -+ -+/* -+ * Routine to reset the chip and clean up. -+ * It is assumed that the caller is in splimp() -+ */ -+static void -+safe_totalreset(struct safe_softc *sc) -+{ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ safe_reset_board(sc); -+ safe_init_board(sc); -+ safe_cleanchip(sc); -+} -+ -+/* -+ * Is the operand suitable aligned for direct DMA. Each -+ * segment must be aligned on a 32-bit boundary and all -+ * but the last segment must be a multiple of 4 bytes. -+ */ -+static int -+safe_dmamap_aligned(struct safe_softc *sc, const struct safe_operand *op) -+{ -+ int i; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ for (i = 0; i < op->nsegs; i++) { -+ if (op->segs[i].ds_addr & 3) -+ return (0); -+ if (i != (op->nsegs - 1) && (op->segs[i].ds_len & 3)) -+ return (0); -+ } -+ return (1); -+} -+ -+/* -+ * Is the operand suitable for direct DMA as the destination -+ * of an operation. The hardware requires that each ``particle'' -+ * but the last in an operation result have the same size. We -+ * fix that size at SAFE_MAX_DSIZE bytes. This routine returns -+ * 0 if some segment is not a multiple of of this size, 1 if all -+ * segments are exactly this size, or 2 if segments are at worst -+ * a multple of this size. -+ */ -+static int -+safe_dmamap_uniform(struct safe_softc *sc, const struct safe_operand *op) -+{ -+ int result = 1; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (op->nsegs > 0) { -+ int i; -+ -+ for (i = 0; i < op->nsegs-1; i++) { -+ if (op->segs[i].ds_len % sc->sc_max_dsize) -+ return (0); -+ if (op->segs[i].ds_len != sc->sc_max_dsize) -+ result = 2; -+ } -+ } -+ return (result); -+} -+ -+static int -+safe_kprocess(device_t dev, struct cryptkop *krp, int hint) -+{ -+ struct safe_softc *sc = device_get_softc(dev); -+ struct safe_pkq *q; -+ unsigned long flags; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (sc == NULL) { -+ krp->krp_status = EINVAL; -+ goto err; -+ } -+ -+ if (krp->krp_op != CRK_MOD_EXP) { -+ krp->krp_status = EOPNOTSUPP; -+ goto err; -+ } -+ -+ q = (struct safe_pkq *) kmalloc(sizeof(*q), GFP_KERNEL); -+ if (q == NULL) { -+ krp->krp_status = ENOMEM; -+ goto err; -+ } -+ memset(q, 0, sizeof(*q)); -+ q->pkq_krp = krp; -+ INIT_LIST_HEAD(&q->pkq_list); -+ -+ spin_lock_irqsave(&sc->sc_pkmtx, flags); -+ list_add_tail(&q->pkq_list, &sc->sc_pkq); -+ safe_kfeed(sc); -+ spin_unlock_irqrestore(&sc->sc_pkmtx, flags); -+ return (0); -+ -+err: -+ crypto_kdone(krp); -+ return (0); -+} -+ -+#define SAFE_CRK_PARAM_BASE 0 -+#define SAFE_CRK_PARAM_EXP 1 -+#define SAFE_CRK_PARAM_MOD 2 -+ -+static int -+safe_kstart(struct safe_softc *sc) -+{ -+ struct cryptkop *krp = sc->sc_pkq_cur->pkq_krp; -+ int exp_bits, mod_bits, base_bits; -+ u_int32_t op, a_off, b_off, c_off, d_off; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (krp->krp_iparams < 3 || krp->krp_oparams != 1) { -+ krp->krp_status = EINVAL; -+ return (1); -+ } -+ -+ base_bits = safe_ksigbits(sc, &krp->krp_param[SAFE_CRK_PARAM_BASE]); -+ if (base_bits > 2048) -+ goto too_big; -+ if (base_bits <= 0) /* 5. base not zero */ -+ goto too_small; -+ -+ exp_bits = safe_ksigbits(sc, &krp->krp_param[SAFE_CRK_PARAM_EXP]); -+ if (exp_bits > 2048) -+ goto too_big; -+ if (exp_bits <= 0) /* 1. exponent word length > 0 */ -+ goto too_small; /* 4. exponent not zero */ -+ -+ mod_bits = safe_ksigbits(sc, &krp->krp_param[SAFE_CRK_PARAM_MOD]); -+ if (mod_bits > 2048) -+ goto too_big; -+ if (mod_bits <= 32) /* 2. modulus word length > 1 */ -+ goto too_small; /* 8. MSW of modulus != zero */ -+ if (mod_bits < exp_bits) /* 3 modulus len >= exponent len */ -+ goto too_small; -+ if ((krp->krp_param[SAFE_CRK_PARAM_MOD].crp_p[0] & 1) == 0) -+ goto bad_domain; /* 6. modulus is odd */ -+ if (mod_bits > krp->krp_param[krp->krp_iparams].crp_nbits) -+ goto too_small; /* make sure result will fit */ -+ -+ /* 7. modulus > base */ -+ if (mod_bits < base_bits) -+ goto too_small; -+ if (mod_bits == base_bits) { -+ u_int8_t *basep, *modp; -+ int i; -+ -+ basep = krp->krp_param[SAFE_CRK_PARAM_BASE].crp_p + -+ ((base_bits + 7) / 8) - 1; -+ modp = krp->krp_param[SAFE_CRK_PARAM_MOD].crp_p + -+ ((mod_bits + 7) / 8) - 1; -+ -+ for (i = 0; i < (mod_bits + 7) / 8; i++, basep--, modp--) { -+ if (*modp < *basep) -+ goto too_small; -+ if (*modp > *basep) -+ break; -+ } -+ } -+ -+ /* And on the 9th step, he rested. */ -+ -+ WRITE_REG(sc, SAFE_PK_A_LEN, (exp_bits + 31) / 32); -+ WRITE_REG(sc, SAFE_PK_B_LEN, (mod_bits + 31) / 32); -+ if (mod_bits > 1024) { -+ op = SAFE_PK_FUNC_EXP4; -+ a_off = 0x000; -+ b_off = 0x100; -+ c_off = 0x200; -+ d_off = 0x300; -+ } else { -+ op = SAFE_PK_FUNC_EXP16; -+ a_off = 0x000; -+ b_off = 0x080; -+ c_off = 0x100; -+ d_off = 0x180; -+ } -+ sc->sc_pk_reslen = b_off - a_off; -+ sc->sc_pk_resoff = d_off; -+ -+ /* A is exponent, B is modulus, C is base, D is result */ -+ safe_kload_reg(sc, a_off, b_off - a_off, -+ &krp->krp_param[SAFE_CRK_PARAM_EXP]); -+ WRITE_REG(sc, SAFE_PK_A_ADDR, a_off >> 2); -+ safe_kload_reg(sc, b_off, b_off - a_off, -+ &krp->krp_param[SAFE_CRK_PARAM_MOD]); -+ WRITE_REG(sc, SAFE_PK_B_ADDR, b_off >> 2); -+ safe_kload_reg(sc, c_off, b_off - a_off, -+ &krp->krp_param[SAFE_CRK_PARAM_BASE]); -+ WRITE_REG(sc, SAFE_PK_C_ADDR, c_off >> 2); -+ WRITE_REG(sc, SAFE_PK_D_ADDR, d_off >> 2); -+ -+ WRITE_REG(sc, SAFE_PK_FUNC, op | SAFE_PK_FUNC_RUN); -+ -+ return (0); -+ -+too_big: -+ krp->krp_status = E2BIG; -+ return (1); -+too_small: -+ krp->krp_status = ERANGE; -+ return (1); -+bad_domain: -+ krp->krp_status = EDOM; -+ return (1); -+} -+ -+static int -+safe_ksigbits(struct safe_softc *sc, struct crparam *cr) -+{ -+ u_int plen = (cr->crp_nbits + 7) / 8; -+ int i, sig = plen * 8; -+ u_int8_t c, *p = cr->crp_p; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ for (i = plen - 1; i >= 0; i--) { -+ c = p[i]; -+ if (c != 0) { -+ while ((c & 0x80) == 0) { -+ sig--; -+ c <<= 1; -+ } -+ break; -+ } -+ sig -= 8; -+ } -+ return (sig); -+} -+ -+static void -+safe_kfeed(struct safe_softc *sc) -+{ -+ struct safe_pkq *q, *tmp; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (list_empty(&sc->sc_pkq) && sc->sc_pkq_cur == NULL) -+ return; -+ if (sc->sc_pkq_cur != NULL) -+ return; -+ list_for_each_entry_safe(q, tmp, &sc->sc_pkq, pkq_list) { -+ sc->sc_pkq_cur = q; -+ list_del(&q->pkq_list); -+ if (safe_kstart(sc) != 0) { -+ crypto_kdone(q->pkq_krp); -+ kfree(q); -+ sc->sc_pkq_cur = NULL; -+ } else { -+ /* op started, start polling */ -+ mod_timer(&sc->sc_pkto, jiffies + 1); -+ break; -+ } -+ } -+} -+ -+static void -+safe_kpoll(unsigned long arg) -+{ -+ struct safe_softc *sc = NULL; -+ struct safe_pkq *q; -+ struct crparam *res; -+ int i; -+ u_int32_t buf[64]; -+ unsigned long flags; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (arg >= SAFE_MAX_CHIPS) -+ return; -+ sc = safe_chip_idx[arg]; -+ if (!sc) { -+ DPRINTF(("%s() - bad callback\n", __FUNCTION__)); -+ return; -+ } -+ -+ spin_lock_irqsave(&sc->sc_pkmtx, flags); -+ if (sc->sc_pkq_cur == NULL) -+ goto out; -+ if (READ_REG(sc, SAFE_PK_FUNC) & SAFE_PK_FUNC_RUN) { -+ /* still running, check back later */ -+ mod_timer(&sc->sc_pkto, jiffies + 1); -+ goto out; -+ } -+ -+ q = sc->sc_pkq_cur; -+ res = &q->pkq_krp->krp_param[q->pkq_krp->krp_iparams]; -+ bzero(buf, sizeof(buf)); -+ bzero(res->crp_p, (res->crp_nbits + 7) / 8); -+ for (i = 0; i < sc->sc_pk_reslen >> 2; i++) -+ buf[i] = le32_to_cpu(READ_REG(sc, SAFE_PK_RAM_START + -+ sc->sc_pk_resoff + (i << 2))); -+ bcopy(buf, res->crp_p, (res->crp_nbits + 7) / 8); -+ /* -+ * reduce the bits that need copying if possible -+ */ -+ res->crp_nbits = min(res->crp_nbits,sc->sc_pk_reslen * 8); -+ res->crp_nbits = safe_ksigbits(sc, res); -+ -+ for (i = SAFE_PK_RAM_START; i < SAFE_PK_RAM_END; i += 4) -+ WRITE_REG(sc, i, 0); -+ -+ crypto_kdone(q->pkq_krp); -+ kfree(q); -+ sc->sc_pkq_cur = NULL; -+ -+ safe_kfeed(sc); -+out: -+ spin_unlock_irqrestore(&sc->sc_pkmtx, flags); -+} -+ -+static void -+safe_kload_reg(struct safe_softc *sc, u_int32_t off, u_int32_t len, -+ struct crparam *n) -+{ -+ u_int32_t buf[64], i; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ bzero(buf, sizeof(buf)); -+ bcopy(n->crp_p, buf, (n->crp_nbits + 7) / 8); -+ -+ for (i = 0; i < len >> 2; i++) -+ WRITE_REG(sc, SAFE_PK_RAM_START + off + (i << 2), -+ cpu_to_le32(buf[i])); -+} -+ -+#ifdef SAFE_DEBUG -+static void -+safe_dump_dmastatus(struct safe_softc *sc, const char *tag) -+{ -+ printf("%s: ENDIAN 0x%x SRC 0x%x DST 0x%x STAT 0x%x\n" -+ , tag -+ , READ_REG(sc, SAFE_DMA_ENDIAN) -+ , READ_REG(sc, SAFE_DMA_SRCADDR) -+ , READ_REG(sc, SAFE_DMA_DSTADDR) -+ , READ_REG(sc, SAFE_DMA_STAT) -+ ); -+} -+ -+static void -+safe_dump_intrstate(struct safe_softc *sc, const char *tag) -+{ -+ printf("%s: HI_CFG 0x%x HI_MASK 0x%x HI_DESC_CNT 0x%x HU_STAT 0x%x HM_STAT 0x%x\n" -+ , tag -+ , READ_REG(sc, SAFE_HI_CFG) -+ , READ_REG(sc, SAFE_HI_MASK) -+ , READ_REG(sc, SAFE_HI_DESC_CNT) -+ , READ_REG(sc, SAFE_HU_STAT) -+ , READ_REG(sc, SAFE_HM_STAT) -+ ); -+} -+ -+static void -+safe_dump_ringstate(struct safe_softc *sc, const char *tag) -+{ -+ u_int32_t estat = READ_REG(sc, SAFE_PE_ERNGSTAT); -+ -+ /* NB: assume caller has lock on ring */ -+ printf("%s: ERNGSTAT %x (next %u) back %lu front %lu\n", -+ tag, -+ estat, (estat >> SAFE_PE_ERNGSTAT_NEXT_S), -+ (unsigned long)(sc->sc_back - sc->sc_ring), -+ (unsigned long)(sc->sc_front - sc->sc_ring)); -+} -+ -+static void -+safe_dump_request(struct safe_softc *sc, const char* tag, struct safe_ringentry *re) -+{ -+ int ix, nsegs; -+ -+ ix = re - sc->sc_ring; -+ printf("%s: %p (%u): csr %x src %x dst %x sa %x len %x\n" -+ , tag -+ , re, ix -+ , re->re_desc.d_csr -+ , re->re_desc.d_src -+ , re->re_desc.d_dst -+ , re->re_desc.d_sa -+ , re->re_desc.d_len -+ ); -+ if (re->re_src.nsegs > 1) { -+ ix = (re->re_desc.d_src - sc->sc_spalloc.dma_paddr) / -+ sizeof(struct safe_pdesc); -+ for (nsegs = re->re_src.nsegs; nsegs; nsegs--) { -+ printf(" spd[%u] %p: %p size %u flags %x" -+ , ix, &sc->sc_spring[ix] -+ , (caddr_t)(uintptr_t) sc->sc_spring[ix].pd_addr -+ , sc->sc_spring[ix].pd_size -+ , sc->sc_spring[ix].pd_flags -+ ); -+ if (sc->sc_spring[ix].pd_size == 0) -+ printf(" (zero!)"); -+ printf("\n"); -+ if (++ix == SAFE_TOTAL_SPART) -+ ix = 0; -+ } -+ } -+ if (re->re_dst.nsegs > 1) { -+ ix = (re->re_desc.d_dst - sc->sc_dpalloc.dma_paddr) / -+ sizeof(struct safe_pdesc); -+ for (nsegs = re->re_dst.nsegs; nsegs; nsegs--) { -+ printf(" dpd[%u] %p: %p flags %x\n" -+ , ix, &sc->sc_dpring[ix] -+ , (caddr_t)(uintptr_t) sc->sc_dpring[ix].pd_addr -+ , sc->sc_dpring[ix].pd_flags -+ ); -+ if (++ix == SAFE_TOTAL_DPART) -+ ix = 0; -+ } -+ } -+ printf("sa: cmd0 %08x cmd1 %08x staterec %x\n", -+ re->re_sa.sa_cmd0, re->re_sa.sa_cmd1, re->re_sa.sa_staterec); -+ printf("sa: key %x %x %x %x %x %x %x %x\n" -+ , re->re_sa.sa_key[0] -+ , re->re_sa.sa_key[1] -+ , re->re_sa.sa_key[2] -+ , re->re_sa.sa_key[3] -+ , re->re_sa.sa_key[4] -+ , re->re_sa.sa_key[5] -+ , re->re_sa.sa_key[6] -+ , re->re_sa.sa_key[7] -+ ); -+ printf("sa: indigest %x %x %x %x %x\n" -+ , re->re_sa.sa_indigest[0] -+ , re->re_sa.sa_indigest[1] -+ , re->re_sa.sa_indigest[2] -+ , re->re_sa.sa_indigest[3] -+ , re->re_sa.sa_indigest[4] -+ ); -+ printf("sa: outdigest %x %x %x %x %x\n" -+ , re->re_sa.sa_outdigest[0] -+ , re->re_sa.sa_outdigest[1] -+ , re->re_sa.sa_outdigest[2] -+ , re->re_sa.sa_outdigest[3] -+ , re->re_sa.sa_outdigest[4] -+ ); -+ printf("sr: iv %x %x %x %x\n" -+ , re->re_sastate.sa_saved_iv[0] -+ , re->re_sastate.sa_saved_iv[1] -+ , re->re_sastate.sa_saved_iv[2] -+ , re->re_sastate.sa_saved_iv[3] -+ ); -+ printf("sr: hashbc %u indigest %x %x %x %x %x\n" -+ , re->re_sastate.sa_saved_hashbc -+ , re->re_sastate.sa_saved_indigest[0] -+ , re->re_sastate.sa_saved_indigest[1] -+ , re->re_sastate.sa_saved_indigest[2] -+ , re->re_sastate.sa_saved_indigest[3] -+ , re->re_sastate.sa_saved_indigest[4] -+ ); -+} -+ -+static void -+safe_dump_ring(struct safe_softc *sc, const char *tag) -+{ -+ unsigned long flags; -+ -+ spin_lock_irqsave(&sc->sc_ringmtx, flags); -+ printf("\nSafeNet Ring State:\n"); -+ safe_dump_intrstate(sc, tag); -+ safe_dump_dmastatus(sc, tag); -+ safe_dump_ringstate(sc, tag); -+ if (sc->sc_nqchip) { -+ struct safe_ringentry *re = sc->sc_back; -+ do { -+ safe_dump_request(sc, tag, re); -+ if (++re == sc->sc_ringtop) -+ re = sc->sc_ring; -+ } while (re != sc->sc_front); -+ } -+ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); -+} -+#endif /* SAFE_DEBUG */ -+ -+ -+static int safe_probe(struct pci_dev *dev, const struct pci_device_id *ent) -+{ -+ struct safe_softc *sc = NULL; -+ u32 mem_start, mem_len, cmd; -+ int i, rc, devinfo; -+ dma_addr_t raddr; -+ static int num_chips = 0; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (pci_enable_device(dev) < 0) -+ return(-ENODEV); -+ -+ if (!dev->irq) { -+ printk("safe: found device with no IRQ assigned. check BIOS settings!"); -+ pci_disable_device(dev); -+ return(-ENODEV); -+ } -+ -+ if (pci_set_mwi(dev)) { -+ printk("safe: pci_set_mwi failed!"); -+ return(-ENODEV); -+ } -+ -+ sc = (struct safe_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); -+ if (!sc) -+ return(-ENOMEM); -+ memset(sc, 0, sizeof(*sc)); -+ -+ softc_device_init(sc, "safe", num_chips, safe_methods); -+ -+ sc->sc_irq = -1; -+ sc->sc_cid = -1; -+ sc->sc_pcidev = dev; -+ if (num_chips < SAFE_MAX_CHIPS) { -+ safe_chip_idx[device_get_unit(sc->sc_dev)] = sc; -+ num_chips++; -+ } -+ -+ INIT_LIST_HEAD(&sc->sc_pkq); -+ spin_lock_init(&sc->sc_pkmtx); -+ -+ pci_set_drvdata(sc->sc_pcidev, sc); -+ -+ /* we read its hardware registers as memory */ -+ mem_start = pci_resource_start(sc->sc_pcidev, 0); -+ mem_len = pci_resource_len(sc->sc_pcidev, 0); -+ -+ sc->sc_base_addr = (ocf_iomem_t) ioremap(mem_start, mem_len); -+ if (!sc->sc_base_addr) { -+ device_printf(sc->sc_dev, "failed to ioremap 0x%x-0x%x\n", -+ mem_start, mem_start + mem_len - 1); -+ goto out; -+ } -+ -+ /* fix up the bus size */ -+ if (pci_set_dma_mask(sc->sc_pcidev, DMA_32BIT_MASK)) { -+ device_printf(sc->sc_dev, "No usable DMA configuration, aborting.\n"); -+ goto out; -+ } -+ if (pci_set_consistent_dma_mask(sc->sc_pcidev, DMA_32BIT_MASK)) { -+ device_printf(sc->sc_dev, "No usable consistent DMA configuration, aborting.\n"); -+ goto out; -+ } -+ -+ pci_set_master(sc->sc_pcidev); -+ -+ pci_read_config_dword(sc->sc_pcidev, PCI_COMMAND, &cmd); -+ -+ if (!(cmd & PCI_COMMAND_MEMORY)) { -+ device_printf(sc->sc_dev, "failed to enable memory mapping\n"); -+ goto out; -+ } -+ -+ if (!(cmd & PCI_COMMAND_MASTER)) { -+ device_printf(sc->sc_dev, "failed to enable bus mastering\n"); -+ goto out; -+ } -+ -+ rc = request_irq(dev->irq, safe_intr, IRQF_SHARED, "safe", sc); -+ if (rc) { -+ device_printf(sc->sc_dev, "failed to hook irq %d\n", sc->sc_irq); -+ goto out; -+ } -+ sc->sc_irq = dev->irq; -+ -+ sc->sc_chiprev = READ_REG(sc, SAFE_DEVINFO) & -+ (SAFE_DEVINFO_REV_MAJ | SAFE_DEVINFO_REV_MIN); -+ -+ /* -+ * Allocate packet engine descriptors. -+ */ -+ sc->sc_ringalloc.dma_vaddr = pci_alloc_consistent(sc->sc_pcidev, -+ SAFE_MAX_NQUEUE * sizeof (struct safe_ringentry), -+ &sc->sc_ringalloc.dma_paddr); -+ if (!sc->sc_ringalloc.dma_vaddr) { -+ device_printf(sc->sc_dev, "cannot allocate PE descriptor ring\n"); -+ goto out; -+ } -+ -+ /* -+ * Hookup the static portion of all our data structures. -+ */ -+ sc->sc_ring = (struct safe_ringentry *) sc->sc_ringalloc.dma_vaddr; -+ sc->sc_ringtop = sc->sc_ring + SAFE_MAX_NQUEUE; -+ sc->sc_front = sc->sc_ring; -+ sc->sc_back = sc->sc_ring; -+ raddr = sc->sc_ringalloc.dma_paddr; -+ bzero(sc->sc_ring, SAFE_MAX_NQUEUE * sizeof(struct safe_ringentry)); -+ for (i = 0; i < SAFE_MAX_NQUEUE; i++) { -+ struct safe_ringentry *re = &sc->sc_ring[i]; -+ -+ re->re_desc.d_sa = raddr + -+ offsetof(struct safe_ringentry, re_sa); -+ re->re_sa.sa_staterec = raddr + -+ offsetof(struct safe_ringentry, re_sastate); -+ -+ raddr += sizeof (struct safe_ringentry); -+ } -+ spin_lock_init(&sc->sc_ringmtx); -+ -+ /* -+ * Allocate scatter and gather particle descriptors. -+ */ -+ sc->sc_spalloc.dma_vaddr = pci_alloc_consistent(sc->sc_pcidev, -+ SAFE_TOTAL_SPART * sizeof (struct safe_pdesc), -+ &sc->sc_spalloc.dma_paddr); -+ if (!sc->sc_spalloc.dma_vaddr) { -+ device_printf(sc->sc_dev, "cannot allocate source particle descriptor ring\n"); -+ goto out; -+ } -+ sc->sc_spring = (struct safe_pdesc *) sc->sc_spalloc.dma_vaddr; -+ sc->sc_springtop = sc->sc_spring + SAFE_TOTAL_SPART; -+ sc->sc_spfree = sc->sc_spring; -+ bzero(sc->sc_spring, SAFE_TOTAL_SPART * sizeof(struct safe_pdesc)); -+ -+ sc->sc_dpalloc.dma_vaddr = pci_alloc_consistent(sc->sc_pcidev, -+ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), -+ &sc->sc_dpalloc.dma_paddr); -+ if (!sc->sc_dpalloc.dma_vaddr) { -+ device_printf(sc->sc_dev, "cannot allocate destination particle descriptor ring\n"); -+ goto out; -+ } -+ sc->sc_dpring = (struct safe_pdesc *) sc->sc_dpalloc.dma_vaddr; -+ sc->sc_dpringtop = sc->sc_dpring + SAFE_TOTAL_DPART; -+ sc->sc_dpfree = sc->sc_dpring; -+ bzero(sc->sc_dpring, SAFE_TOTAL_DPART * sizeof(struct safe_pdesc)); -+ -+ sc->sc_cid = crypto_get_driverid(softc_get_device(sc), CRYPTOCAP_F_HARDWARE); -+ if (sc->sc_cid < 0) { -+ device_printf(sc->sc_dev, "could not get crypto driver id\n"); -+ goto out; -+ } -+ -+ printf("%s:", device_get_nameunit(sc->sc_dev)); -+ -+ devinfo = READ_REG(sc, SAFE_DEVINFO); -+ if (devinfo & SAFE_DEVINFO_RNG) { -+ sc->sc_flags |= SAFE_FLAGS_RNG; -+ printf(" rng"); -+ } -+ if (devinfo & SAFE_DEVINFO_PKEY) { -+ printf(" key"); -+ sc->sc_flags |= SAFE_FLAGS_KEY; -+ crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0); -+#if 0 -+ crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0); -+#endif -+ init_timer(&sc->sc_pkto); -+ sc->sc_pkto.function = safe_kpoll; -+ sc->sc_pkto.data = (unsigned long) device_get_unit(sc->sc_dev); -+ } -+ if (devinfo & SAFE_DEVINFO_DES) { -+ printf(" des/3des"); -+ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); -+ } -+ if (devinfo & SAFE_DEVINFO_AES) { -+ printf(" aes"); -+ crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); -+ } -+ if (devinfo & SAFE_DEVINFO_MD5) { -+ printf(" md5"); -+ crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); -+ } -+ if (devinfo & SAFE_DEVINFO_SHA1) { -+ printf(" sha1"); -+ crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); -+ } -+ printf(" null"); -+ crypto_register(sc->sc_cid, CRYPTO_NULL_CBC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_NULL_HMAC, 0, 0); -+ /* XXX other supported algorithms */ -+ printf("\n"); -+ -+ safe_reset_board(sc); /* reset h/w */ -+ safe_init_board(sc); /* init h/w */ -+ -+#if defined(CONFIG_OCF_RANDOMHARVEST) && !defined(SAFE_NO_RNG) -+ if (sc->sc_flags & SAFE_FLAGS_RNG) { -+ safe_rng_init(sc); -+ crypto_rregister(sc->sc_cid, safe_read_random, sc); -+ } -+#endif /* SAFE_NO_RNG */ -+ -+ return (0); -+ -+out: -+ if (sc->sc_cid >= 0) -+ crypto_unregister_all(sc->sc_cid); -+ if (sc->sc_irq != -1) -+ free_irq(sc->sc_irq, sc); -+ if (sc->sc_ringalloc.dma_vaddr) -+ pci_free_consistent(sc->sc_pcidev, -+ SAFE_MAX_NQUEUE * sizeof (struct safe_ringentry), -+ sc->sc_ringalloc.dma_vaddr, sc->sc_ringalloc.dma_paddr); -+ if (sc->sc_spalloc.dma_vaddr) -+ pci_free_consistent(sc->sc_pcidev, -+ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), -+ sc->sc_spalloc.dma_vaddr, sc->sc_spalloc.dma_paddr); -+ if (sc->sc_dpalloc.dma_vaddr) -+ pci_free_consistent(sc->sc_pcidev, -+ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), -+ sc->sc_dpalloc.dma_vaddr, sc->sc_dpalloc.dma_paddr); -+ kfree(sc); -+ return(-ENODEV); -+} -+ -+static void safe_remove(struct pci_dev *dev) -+{ -+ struct safe_softc *sc = pci_get_drvdata(dev); -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ /* XXX wait/abort active ops */ -+ -+ WRITE_REG(sc, SAFE_HI_MASK, 0); /* disable interrupts */ -+ -+ del_timer_sync(&sc->sc_pkto); -+ -+ crypto_unregister_all(sc->sc_cid); -+ -+ safe_cleanchip(sc); -+ -+ if (sc->sc_irq != -1) -+ free_irq(sc->sc_irq, sc); -+ if (sc->sc_ringalloc.dma_vaddr) -+ pci_free_consistent(sc->sc_pcidev, -+ SAFE_MAX_NQUEUE * sizeof (struct safe_ringentry), -+ sc->sc_ringalloc.dma_vaddr, sc->sc_ringalloc.dma_paddr); -+ if (sc->sc_spalloc.dma_vaddr) -+ pci_free_consistent(sc->sc_pcidev, -+ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), -+ sc->sc_spalloc.dma_vaddr, sc->sc_spalloc.dma_paddr); -+ if (sc->sc_dpalloc.dma_vaddr) -+ pci_free_consistent(sc->sc_pcidev, -+ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), -+ sc->sc_dpalloc.dma_vaddr, sc->sc_dpalloc.dma_paddr); -+ sc->sc_irq = -1; -+ sc->sc_ringalloc.dma_vaddr = NULL; -+ sc->sc_spalloc.dma_vaddr = NULL; -+ sc->sc_dpalloc.dma_vaddr = NULL; -+} -+ -+static struct pci_device_id safe_pci_tbl[] = { -+ { PCI_VENDOR_SAFENET, PCI_PRODUCT_SAFEXCEL, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ { }, -+}; -+MODULE_DEVICE_TABLE(pci, safe_pci_tbl); -+ -+static struct pci_driver safe_driver = { -+ .name = "safe", -+ .id_table = safe_pci_tbl, -+ .probe = safe_probe, -+ .remove = safe_remove, -+ /* add PM stuff here one day */ -+}; -+ -+static int __init safe_init (void) -+{ -+ struct safe_softc *sc = NULL; -+ int rc; -+ -+ DPRINTF(("%s(%p)\n", __FUNCTION__, safe_init)); -+ -+ rc = pci_register_driver(&safe_driver); -+ pci_register_driver_compat(&safe_driver, rc); -+ -+ return rc; -+} -+ -+static void __exit safe_exit (void) -+{ -+ pci_unregister_driver(&safe_driver); -+} -+ -+module_init(safe_init); -+module_exit(safe_exit); -+ -+MODULE_LICENSE("BSD"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("OCF driver for safenet PCI crypto devices"); -diff -Nur linux-3.0.4.orig/crypto/ocf/safe/safereg.h linux-3.0.4/crypto/ocf/safe/safereg.h ---- linux-3.0.4.orig/crypto/ocf/safe/safereg.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/safe/safereg.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,421 @@ -+/*- -+ * Copyright (c) 2003 Sam Leffler, Errno Consulting -+ * Copyright (c) 2003 Global Technology Associates, Inc. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ * -+ * $FreeBSD: src/sys/dev/safe/safereg.h,v 1.1 2003/07/21 21:46:07 sam Exp $ -+ */ -+#ifndef _SAFE_SAFEREG_H_ -+#define _SAFE_SAFEREG_H_ -+ -+/* -+ * Register definitions for SafeNet SafeXcel-1141 crypto device. -+ * Definitions from revision 1.3 (Nov 6 2002) of the User's Manual. -+ */ -+ -+#define BS_BAR 0x10 /* DMA base address register */ -+#define BS_TRDY_TIMEOUT 0x40 /* TRDY timeout */ -+#define BS_RETRY_TIMEOUT 0x41 /* DMA retry timeout */ -+ -+#define PCI_VENDOR_SAFENET 0x16ae /* SafeNet, Inc. */ -+ -+/* SafeNet */ -+#define PCI_PRODUCT_SAFEXCEL 0x1141 /* 1141 */ -+ -+#define SAFE_PE_CSR 0x0000 /* Packet Enginge Ctrl/Status */ -+#define SAFE_PE_SRC 0x0004 /* Packet Engine Source */ -+#define SAFE_PE_DST 0x0008 /* Packet Engine Destination */ -+#define SAFE_PE_SA 0x000c /* Packet Engine SA */ -+#define SAFE_PE_LEN 0x0010 /* Packet Engine Length */ -+#define SAFE_PE_DMACFG 0x0040 /* Packet Engine DMA Configuration */ -+#define SAFE_PE_DMASTAT 0x0044 /* Packet Engine DMA Status */ -+#define SAFE_PE_PDRBASE 0x0048 /* Packet Engine Descriptor Ring Base */ -+#define SAFE_PE_RDRBASE 0x004c /* Packet Engine Result Ring Base */ -+#define SAFE_PE_RINGCFG 0x0050 /* Packet Engine Ring Configuration */ -+#define SAFE_PE_RINGPOLL 0x0054 /* Packet Engine Ring Poll */ -+#define SAFE_PE_IRNGSTAT 0x0058 /* Packet Engine Internal Ring Status */ -+#define SAFE_PE_ERNGSTAT 0x005c /* Packet Engine External Ring Status */ -+#define SAFE_PE_IOTHRESH 0x0060 /* Packet Engine I/O Threshold */ -+#define SAFE_PE_GRNGBASE 0x0064 /* Packet Engine Gather Ring Base */ -+#define SAFE_PE_SRNGBASE 0x0068 /* Packet Engine Scatter Ring Base */ -+#define SAFE_PE_PARTSIZE 0x006c /* Packet Engine Particlar Ring Size */ -+#define SAFE_PE_PARTCFG 0x0070 /* Packet Engine Particle Ring Config */ -+#define SAFE_CRYPTO_CTRL 0x0080 /* Crypto Control */ -+#define SAFE_DEVID 0x0084 /* Device ID */ -+#define SAFE_DEVINFO 0x0088 /* Device Info */ -+#define SAFE_HU_STAT 0x00a0 /* Host Unmasked Status */ -+#define SAFE_HM_STAT 0x00a4 /* Host Masked Status (read-only) */ -+#define SAFE_HI_CLR 0x00a4 /* Host Clear Interrupt (write-only) */ -+#define SAFE_HI_MASK 0x00a8 /* Host Mask Control */ -+#define SAFE_HI_CFG 0x00ac /* Interrupt Configuration */ -+#define SAFE_HI_RD_DESCR 0x00b4 /* Force Descriptor Read */ -+#define SAFE_HI_DESC_CNT 0x00b8 /* Host Descriptor Done Count */ -+#define SAFE_DMA_ENDIAN 0x00c0 /* Master Endian Status */ -+#define SAFE_DMA_SRCADDR 0x00c4 /* DMA Source Address Status */ -+#define SAFE_DMA_DSTADDR 0x00c8 /* DMA Destination Address Status */ -+#define SAFE_DMA_STAT 0x00cc /* DMA Current Status */ -+#define SAFE_DMA_CFG 0x00d4 /* DMA Configuration/Status */ -+#define SAFE_ENDIAN 0x00e0 /* Endian Configuration */ -+#define SAFE_PK_A_ADDR 0x0800 /* Public Key A Address */ -+#define SAFE_PK_B_ADDR 0x0804 /* Public Key B Address */ -+#define SAFE_PK_C_ADDR 0x0808 /* Public Key C Address */ -+#define SAFE_PK_D_ADDR 0x080c /* Public Key D Address */ -+#define SAFE_PK_A_LEN 0x0810 /* Public Key A Length */ -+#define SAFE_PK_B_LEN 0x0814 /* Public Key B Length */ -+#define SAFE_PK_SHIFT 0x0818 /* Public Key Shift */ -+#define SAFE_PK_FUNC 0x081c /* Public Key Function */ -+#define SAFE_PK_RAM_START 0x1000 /* Public Key RAM start address */ -+#define SAFE_PK_RAM_END 0x1fff /* Public Key RAM end address */ -+ -+#define SAFE_RNG_OUT 0x0100 /* RNG Output */ -+#define SAFE_RNG_STAT 0x0104 /* RNG Status */ -+#define SAFE_RNG_CTRL 0x0108 /* RNG Control */ -+#define SAFE_RNG_A 0x010c /* RNG A */ -+#define SAFE_RNG_B 0x0110 /* RNG B */ -+#define SAFE_RNG_X_LO 0x0114 /* RNG X [31:0] */ -+#define SAFE_RNG_X_MID 0x0118 /* RNG X [63:32] */ -+#define SAFE_RNG_X_HI 0x011c /* RNG X [80:64] */ -+#define SAFE_RNG_X_CNTR 0x0120 /* RNG Counter */ -+#define SAFE_RNG_ALM_CNT 0x0124 /* RNG Alarm Count */ -+#define SAFE_RNG_CNFG 0x0128 /* RNG Configuration */ -+#define SAFE_RNG_LFSR1_LO 0x012c /* RNG LFSR1 [31:0] */ -+#define SAFE_RNG_LFSR1_HI 0x0130 /* RNG LFSR1 [47:32] */ -+#define SAFE_RNG_LFSR2_LO 0x0134 /* RNG LFSR1 [31:0] */ -+#define SAFE_RNG_LFSR2_HI 0x0138 /* RNG LFSR1 [47:32] */ -+ -+#define SAFE_PE_CSR_READY 0x00000001 /* ready for processing */ -+#define SAFE_PE_CSR_DONE 0x00000002 /* h/w completed processing */ -+#define SAFE_PE_CSR_LOADSA 0x00000004 /* load SA digests */ -+#define SAFE_PE_CSR_HASHFINAL 0x00000010 /* do hash pad & write result */ -+#define SAFE_PE_CSR_SABUSID 0x000000c0 /* bus id for SA */ -+#define SAFE_PE_CSR_SAPCI 0x00000040 /* PCI bus id for SA */ -+#define SAFE_PE_CSR_NXTHDR 0x0000ff00 /* next hdr value for IPsec */ -+#define SAFE_PE_CSR_FPAD 0x0000ff00 /* fixed pad for basic ops */ -+#define SAFE_PE_CSR_STATUS 0x00ff0000 /* operation result status */ -+#define SAFE_PE_CSR_AUTH_FAIL 0x00010000 /* ICV mismatch (inbound) */ -+#define SAFE_PE_CSR_PAD_FAIL 0x00020000 /* pad verify fail (inbound) */ -+#define SAFE_PE_CSR_SEQ_FAIL 0x00040000 /* sequence number (inbound) */ -+#define SAFE_PE_CSR_XERROR 0x00080000 /* extended error follows */ -+#define SAFE_PE_CSR_XECODE 0x00f00000 /* extended error code */ -+#define SAFE_PE_CSR_XECODE_S 20 -+#define SAFE_PE_CSR_XECODE_BADCMD 0 /* invalid command */ -+#define SAFE_PE_CSR_XECODE_BADALG 1 /* invalid algorithm */ -+#define SAFE_PE_CSR_XECODE_ALGDIS 2 /* algorithm disabled */ -+#define SAFE_PE_CSR_XECODE_ZEROLEN 3 /* zero packet length */ -+#define SAFE_PE_CSR_XECODE_DMAERR 4 /* bus DMA error */ -+#define SAFE_PE_CSR_XECODE_PIPEABORT 5 /* secondary bus DMA error */ -+#define SAFE_PE_CSR_XECODE_BADSPI 6 /* IPsec SPI mismatch */ -+#define SAFE_PE_CSR_XECODE_TIMEOUT 10 /* failsafe timeout */ -+#define SAFE_PE_CSR_PAD 0xff000000 /* ESP padding control/status */ -+#define SAFE_PE_CSR_PAD_MIN 0x00000000 /* minimum IPsec padding */ -+#define SAFE_PE_CSR_PAD_16 0x08000000 /* pad to 16-byte boundary */ -+#define SAFE_PE_CSR_PAD_32 0x10000000 /* pad to 32-byte boundary */ -+#define SAFE_PE_CSR_PAD_64 0x20000000 /* pad to 64-byte boundary */ -+#define SAFE_PE_CSR_PAD_128 0x40000000 /* pad to 128-byte boundary */ -+#define SAFE_PE_CSR_PAD_256 0x80000000 /* pad to 256-byte boundary */ -+ -+/* -+ * Check the CSR to see if the PE has returned ownership to -+ * the host. Note that before processing a descriptor this -+ * must be done followed by a check of the SAFE_PE_LEN register -+ * status bits to avoid premature processing of a descriptor -+ * on its way back to the host. -+ */ -+#define SAFE_PE_CSR_IS_DONE(_csr) \ -+ (((_csr) & (SAFE_PE_CSR_READY | SAFE_PE_CSR_DONE)) == SAFE_PE_CSR_DONE) -+ -+#define SAFE_PE_LEN_LENGTH 0x000fffff /* total length (bytes) */ -+#define SAFE_PE_LEN_READY 0x00400000 /* ready for processing */ -+#define SAFE_PE_LEN_DONE 0x00800000 /* h/w completed processing */ -+#define SAFE_PE_LEN_BYPASS 0xff000000 /* bypass offset (bytes) */ -+#define SAFE_PE_LEN_BYPASS_S 24 -+ -+#define SAFE_PE_LEN_IS_DONE(_len) \ -+ (((_len) & (SAFE_PE_LEN_READY | SAFE_PE_LEN_DONE)) == SAFE_PE_LEN_DONE) -+ -+/* NB: these apply to HU_STAT, HM_STAT, HI_CLR, and HI_MASK */ -+#define SAFE_INT_PE_CDONE 0x00000002 /* PE context done */ -+#define SAFE_INT_PE_DDONE 0x00000008 /* PE descriptor done */ -+#define SAFE_INT_PE_ERROR 0x00000010 /* PE error */ -+#define SAFE_INT_PE_ODONE 0x00000020 /* PE operation done */ -+ -+#define SAFE_HI_CFG_PULSE 0x00000001 /* use pulse interrupt */ -+#define SAFE_HI_CFG_LEVEL 0x00000000 /* use level interrupt */ -+#define SAFE_HI_CFG_AUTOCLR 0x00000002 /* auto-clear pulse interrupt */ -+ -+#define SAFE_ENDIAN_PASS 0x000000e4 /* straight pass-thru */ -+#define SAFE_ENDIAN_SWAB 0x0000001b /* swap bytes in 32-bit word */ -+ -+#define SAFE_PE_DMACFG_PERESET 0x00000001 /* reset packet engine */ -+#define SAFE_PE_DMACFG_PDRRESET 0x00000002 /* reset PDR counters/ptrs */ -+#define SAFE_PE_DMACFG_SGRESET 0x00000004 /* reset scatter/gather cache */ -+#define SAFE_PE_DMACFG_FSENA 0x00000008 /* enable failsafe reset */ -+#define SAFE_PE_DMACFG_PEMODE 0x00000100 /* packet engine mode */ -+#define SAFE_PE_DMACFG_SAPREC 0x00000200 /* SA precedes packet */ -+#define SAFE_PE_DMACFG_PKFOLL 0x00000400 /* packet follows descriptor */ -+#define SAFE_PE_DMACFG_GPRBID 0x00003000 /* gather particle ring busid */ -+#define SAFE_PE_DMACFG_GPRPCI 0x00001000 /* PCI gather particle ring */ -+#define SAFE_PE_DMACFG_SPRBID 0x0000c000 /* scatter part. ring busid */ -+#define SAFE_PE_DMACFG_SPRPCI 0x00004000 /* PCI scatter part. ring */ -+#define SAFE_PE_DMACFG_ESDESC 0x00010000 /* endian swap descriptors */ -+#define SAFE_PE_DMACFG_ESSA 0x00020000 /* endian swap SA data */ -+#define SAFE_PE_DMACFG_ESPACKET 0x00040000 /* endian swap packet data */ -+#define SAFE_PE_DMACFG_ESPDESC 0x00080000 /* endian swap particle desc. */ -+#define SAFE_PE_DMACFG_NOPDRUP 0x00100000 /* supp. PDR ownership update */ -+#define SAFE_PD_EDMACFG_PCIMODE 0x01000000 /* PCI target mode */ -+ -+#define SAFE_PE_DMASTAT_PEIDONE 0x00000001 /* PE core input done */ -+#define SAFE_PE_DMASTAT_PEODONE 0x00000002 /* PE core output done */ -+#define SAFE_PE_DMASTAT_ENCDONE 0x00000004 /* encryption done */ -+#define SAFE_PE_DMASTAT_IHDONE 0x00000008 /* inner hash done */ -+#define SAFE_PE_DMASTAT_OHDONE 0x00000010 /* outer hash (HMAC) done */ -+#define SAFE_PE_DMASTAT_PADFLT 0x00000020 /* crypto pad fault */ -+#define SAFE_PE_DMASTAT_ICVFLT 0x00000040 /* ICV fault */ -+#define SAFE_PE_DMASTAT_SPIMIS 0x00000080 /* SPI mismatch */ -+#define SAFE_PE_DMASTAT_CRYPTO 0x00000100 /* crypto engine timeout */ -+#define SAFE_PE_DMASTAT_CQACT 0x00000200 /* command queue active */ -+#define SAFE_PE_DMASTAT_IRACT 0x00000400 /* input request active */ -+#define SAFE_PE_DMASTAT_ORACT 0x00000800 /* output request active */ -+#define SAFE_PE_DMASTAT_PEISIZE 0x003ff000 /* PE input size:32-bit words */ -+#define SAFE_PE_DMASTAT_PEOSIZE 0xffc00000 /* PE out. size:32-bit words */ -+ -+#define SAFE_PE_RINGCFG_SIZE 0x000003ff /* ring size (descriptors) */ -+#define SAFE_PE_RINGCFG_OFFSET 0xffff0000 /* offset btw desc's (dwords) */ -+#define SAFE_PE_RINGCFG_OFFSET_S 16 -+ -+#define SAFE_PE_RINGPOLL_POLL 0x00000fff /* polling frequency/divisor */ -+#define SAFE_PE_RINGPOLL_RETRY 0x03ff0000 /* polling frequency/divisor */ -+#define SAFE_PE_RINGPOLL_CONT 0x80000000 /* continuously poll */ -+ -+#define SAFE_PE_IRNGSTAT_CQAVAIL 0x00000001 /* command queue available */ -+ -+#define SAFE_PE_ERNGSTAT_NEXT 0x03ff0000 /* index of next packet desc. */ -+#define SAFE_PE_ERNGSTAT_NEXT_S 16 -+ -+#define SAFE_PE_IOTHRESH_INPUT 0x000003ff /* input threshold (dwords) */ -+#define SAFE_PE_IOTHRESH_OUTPUT 0x03ff0000 /* output threshold (dwords) */ -+ -+#define SAFE_PE_PARTCFG_SIZE 0x0000ffff /* scatter particle size */ -+#define SAFE_PE_PARTCFG_GBURST 0x00030000 /* gather particle burst */ -+#define SAFE_PE_PARTCFG_GBURST_2 0x00000000 -+#define SAFE_PE_PARTCFG_GBURST_4 0x00010000 -+#define SAFE_PE_PARTCFG_GBURST_8 0x00020000 -+#define SAFE_PE_PARTCFG_GBURST_16 0x00030000 -+#define SAFE_PE_PARTCFG_SBURST 0x000c0000 /* scatter particle burst */ -+#define SAFE_PE_PARTCFG_SBURST_2 0x00000000 -+#define SAFE_PE_PARTCFG_SBURST_4 0x00040000 -+#define SAFE_PE_PARTCFG_SBURST_8 0x00080000 -+#define SAFE_PE_PARTCFG_SBURST_16 0x000c0000 -+ -+#define SAFE_PE_PARTSIZE_SCAT 0xffff0000 /* scatter particle ring size */ -+#define SAFE_PE_PARTSIZE_GATH 0x0000ffff /* gather particle ring size */ -+ -+#define SAFE_CRYPTO_CTRL_3DES 0x00000001 /* enable 3DES support */ -+#define SAFE_CRYPTO_CTRL_PKEY 0x00010000 /* enable public key support */ -+#define SAFE_CRYPTO_CTRL_RNG 0x00020000 /* enable RNG support */ -+ -+#define SAFE_DEVINFO_REV_MIN 0x0000000f /* minor rev for chip */ -+#define SAFE_DEVINFO_REV_MAJ 0x000000f0 /* major rev for chip */ -+#define SAFE_DEVINFO_REV_MAJ_S 4 -+#define SAFE_DEVINFO_DES 0x00000100 /* DES/3DES support present */ -+#define SAFE_DEVINFO_ARC4 0x00000200 /* ARC4 support present */ -+#define SAFE_DEVINFO_AES 0x00000400 /* AES support present */ -+#define SAFE_DEVINFO_MD5 0x00001000 /* MD5 support present */ -+#define SAFE_DEVINFO_SHA1 0x00002000 /* SHA-1 support present */ -+#define SAFE_DEVINFO_RIPEMD 0x00004000 /* RIPEMD support present */ -+#define SAFE_DEVINFO_DEFLATE 0x00010000 /* Deflate support present */ -+#define SAFE_DEVINFO_SARAM 0x00100000 /* on-chip SA RAM present */ -+#define SAFE_DEVINFO_EMIBUS 0x00200000 /* EMI bus present */ -+#define SAFE_DEVINFO_PKEY 0x00400000 /* public key support present */ -+#define SAFE_DEVINFO_RNG 0x00800000 /* RNG present */ -+ -+#define SAFE_REV(_maj, _min) (((_maj) << SAFE_DEVINFO_REV_MAJ_S) | (_min)) -+#define SAFE_REV_MAJ(_chiprev) \ -+ (((_chiprev) & SAFE_DEVINFO_REV_MAJ) >> SAFE_DEVINFO_REV_MAJ_S) -+#define SAFE_REV_MIN(_chiprev) ((_chiprev) & SAFE_DEVINFO_REV_MIN) -+ -+#define SAFE_PK_FUNC_MULT 0x00000001 /* Multiply function */ -+#define SAFE_PK_FUNC_SQUARE 0x00000004 /* Square function */ -+#define SAFE_PK_FUNC_ADD 0x00000010 /* Add function */ -+#define SAFE_PK_FUNC_SUB 0x00000020 /* Subtract function */ -+#define SAFE_PK_FUNC_LSHIFT 0x00000040 /* Left-shift function */ -+#define SAFE_PK_FUNC_RSHIFT 0x00000080 /* Right-shift function */ -+#define SAFE_PK_FUNC_DIV 0x00000100 /* Divide function */ -+#define SAFE_PK_FUNC_CMP 0x00000400 /* Compare function */ -+#define SAFE_PK_FUNC_COPY 0x00000800 /* Copy function */ -+#define SAFE_PK_FUNC_EXP16 0x00002000 /* Exponentiate (4-bit ACT) */ -+#define SAFE_PK_FUNC_EXP4 0x00004000 /* Exponentiate (2-bit ACT) */ -+#define SAFE_PK_FUNC_RUN 0x00008000 /* start/status */ -+ -+#define SAFE_RNG_STAT_BUSY 0x00000001 /* busy, data not valid */ -+ -+#define SAFE_RNG_CTRL_PRE_LFSR 0x00000001 /* enable output pre-LFSR */ -+#define SAFE_RNG_CTRL_TST_MODE 0x00000002 /* enable test mode */ -+#define SAFE_RNG_CTRL_TST_RUN 0x00000004 /* start test state machine */ -+#define SAFE_RNG_CTRL_ENA_RING1 0x00000008 /* test entropy oscillator #1 */ -+#define SAFE_RNG_CTRL_ENA_RING2 0x00000010 /* test entropy oscillator #2 */ -+#define SAFE_RNG_CTRL_DIS_ALARM 0x00000020 /* disable RNG alarm reports */ -+#define SAFE_RNG_CTRL_TST_CLOCK 0x00000040 /* enable test clock */ -+#define SAFE_RNG_CTRL_SHORTEN 0x00000080 /* shorten state timers */ -+#define SAFE_RNG_CTRL_TST_ALARM 0x00000100 /* simulate alarm state */ -+#define SAFE_RNG_CTRL_RST_LFSR 0x00000200 /* reset LFSR */ -+ -+/* -+ * Packet engine descriptor. Note that d_csr is a copy of the -+ * SAFE_PE_CSR register and all definitions apply, and d_len -+ * is a copy of the SAFE_PE_LEN register and all definitions apply. -+ * d_src and d_len may point directly to contiguous data or to a -+ * list of ``particle descriptors'' when using scatter/gather i/o. -+ */ -+struct safe_desc { -+ u_int32_t d_csr; /* per-packet control/status */ -+ u_int32_t d_src; /* source address */ -+ u_int32_t d_dst; /* destination address */ -+ u_int32_t d_sa; /* SA address */ -+ u_int32_t d_len; /* length, bypass, status */ -+}; -+ -+/* -+ * Scatter/Gather particle descriptor. -+ * -+ * NB: scatter descriptors do not specify a size; this is fixed -+ * by the setting of the SAFE_PE_PARTCFG register. -+ */ -+struct safe_pdesc { -+ u_int32_t pd_addr; /* particle address */ -+#ifdef __BIG_ENDIAN -+ u_int16_t pd_flags; /* control word */ -+ u_int16_t pd_size; /* particle size (bytes) */ -+#else -+ u_int16_t pd_flags; /* control word */ -+ u_int16_t pd_size; /* particle size (bytes) */ -+#endif -+}; -+ -+#define SAFE_PD_READY 0x0001 /* ready for processing */ -+#define SAFE_PD_DONE 0x0002 /* h/w completed processing */ -+ -+/* -+ * Security Association (SA) Record (Rev 1). One of these is -+ * required for each operation processed by the packet engine. -+ */ -+struct safe_sarec { -+ u_int32_t sa_cmd0; -+ u_int32_t sa_cmd1; -+ u_int32_t sa_resv0; -+ u_int32_t sa_resv1; -+ u_int32_t sa_key[8]; /* DES/3DES/AES key */ -+ u_int32_t sa_indigest[5]; /* inner digest */ -+ u_int32_t sa_outdigest[5]; /* outer digest */ -+ u_int32_t sa_spi; /* SPI */ -+ u_int32_t sa_seqnum; /* sequence number */ -+ u_int32_t sa_seqmask[2]; /* sequence number mask */ -+ u_int32_t sa_resv2; -+ u_int32_t sa_staterec; /* address of state record */ -+ u_int32_t sa_resv3[2]; -+ u_int32_t sa_samgmt0; /* SA management field 0 */ -+ u_int32_t sa_samgmt1; /* SA management field 0 */ -+}; -+ -+#define SAFE_SA_CMD0_OP 0x00000007 /* operation code */ -+#define SAFE_SA_CMD0_OP_CRYPT 0x00000000 /* encrypt/decrypt (basic) */ -+#define SAFE_SA_CMD0_OP_BOTH 0x00000001 /* encrypt-hash/hash-decrypto */ -+#define SAFE_SA_CMD0_OP_HASH 0x00000003 /* hash (outbound-only) */ -+#define SAFE_SA_CMD0_OP_ESP 0x00000000 /* ESP in/out (proto) */ -+#define SAFE_SA_CMD0_OP_AH 0x00000001 /* AH in/out (proto) */ -+#define SAFE_SA_CMD0_INBOUND 0x00000008 /* inbound operation */ -+#define SAFE_SA_CMD0_OUTBOUND 0x00000000 /* outbound operation */ -+#define SAFE_SA_CMD0_GROUP 0x00000030 /* operation group */ -+#define SAFE_SA_CMD0_BASIC 0x00000000 /* basic operation */ -+#define SAFE_SA_CMD0_PROTO 0x00000010 /* protocol/packet operation */ -+#define SAFE_SA_CMD0_BUNDLE 0x00000020 /* bundled operation (resvd) */ -+#define SAFE_SA_CMD0_PAD 0x000000c0 /* crypto pad method */ -+#define SAFE_SA_CMD0_PAD_IPSEC 0x00000000 /* IPsec padding */ -+#define SAFE_SA_CMD0_PAD_PKCS7 0x00000040 /* PKCS#7 padding */ -+#define SAFE_SA_CMD0_PAD_CONS 0x00000080 /* constant padding */ -+#define SAFE_SA_CMD0_PAD_ZERO 0x000000c0 /* zero padding */ -+#define SAFE_SA_CMD0_CRYPT_ALG 0x00000f00 /* symmetric crypto algorithm */ -+#define SAFE_SA_CMD0_DES 0x00000000 /* DES crypto algorithm */ -+#define SAFE_SA_CMD0_3DES 0x00000100 /* 3DES crypto algorithm */ -+#define SAFE_SA_CMD0_AES 0x00000300 /* AES crypto algorithm */ -+#define SAFE_SA_CMD0_CRYPT_NULL 0x00000f00 /* null crypto algorithm */ -+#define SAFE_SA_CMD0_HASH_ALG 0x0000f000 /* hash algorithm */ -+#define SAFE_SA_CMD0_MD5 0x00000000 /* MD5 hash algorithm */ -+#define SAFE_SA_CMD0_SHA1 0x00001000 /* SHA-1 hash algorithm */ -+#define SAFE_SA_CMD0_HASH_NULL 0x0000f000 /* null hash algorithm */ -+#define SAFE_SA_CMD0_HDR_PROC 0x00080000 /* header processing */ -+#define SAFE_SA_CMD0_IBUSID 0x00300000 /* input bus id */ -+#define SAFE_SA_CMD0_IPCI 0x00100000 /* PCI input bus id */ -+#define SAFE_SA_CMD0_OBUSID 0x00c00000 /* output bus id */ -+#define SAFE_SA_CMD0_OPCI 0x00400000 /* PCI output bus id */ -+#define SAFE_SA_CMD0_IVLD 0x03000000 /* IV loading */ -+#define SAFE_SA_CMD0_IVLD_NONE 0x00000000 /* IV no load (reuse) */ -+#define SAFE_SA_CMD0_IVLD_IBUF 0x01000000 /* IV load from input buffer */ -+#define SAFE_SA_CMD0_IVLD_STATE 0x02000000 /* IV load from state */ -+#define SAFE_SA_CMD0_HSLD 0x0c000000 /* hash state loading */ -+#define SAFE_SA_CMD0_HSLD_SA 0x00000000 /* hash state load from SA */ -+#define SAFE_SA_CMD0_HSLD_STATE 0x08000000 /* hash state load from state */ -+#define SAFE_SA_CMD0_HSLD_NONE 0x0c000000 /* hash state no load */ -+#define SAFE_SA_CMD0_SAVEIV 0x10000000 /* save IV */ -+#define SAFE_SA_CMD0_SAVEHASH 0x20000000 /* save hash state */ -+#define SAFE_SA_CMD0_IGATHER 0x40000000 /* input gather */ -+#define SAFE_SA_CMD0_OSCATTER 0x80000000 /* output scatter */ -+ -+#define SAFE_SA_CMD1_HDRCOPY 0x00000002 /* copy header to output */ -+#define SAFE_SA_CMD1_PAYCOPY 0x00000004 /* copy payload to output */ -+#define SAFE_SA_CMD1_PADCOPY 0x00000008 /* copy pad to output */ -+#define SAFE_SA_CMD1_IPV4 0x00000000 /* IPv4 protocol */ -+#define SAFE_SA_CMD1_IPV6 0x00000010 /* IPv6 protocol */ -+#define SAFE_SA_CMD1_MUTABLE 0x00000020 /* mutable bit processing */ -+#define SAFE_SA_CMD1_SRBUSID 0x000000c0 /* state record bus id */ -+#define SAFE_SA_CMD1_SRPCI 0x00000040 /* state record from PCI */ -+#define SAFE_SA_CMD1_CRMODE 0x00000300 /* crypto mode */ -+#define SAFE_SA_CMD1_ECB 0x00000000 /* ECB crypto mode */ -+#define SAFE_SA_CMD1_CBC 0x00000100 /* CBC crypto mode */ -+#define SAFE_SA_CMD1_OFB 0x00000200 /* OFB crypto mode */ -+#define SAFE_SA_CMD1_CFB 0x00000300 /* CFB crypto mode */ -+#define SAFE_SA_CMD1_CRFEEDBACK 0x00000c00 /* crypto feedback mode */ -+#define SAFE_SA_CMD1_64BIT 0x00000000 /* 64-bit crypto feedback */ -+#define SAFE_SA_CMD1_8BIT 0x00000400 /* 8-bit crypto feedback */ -+#define SAFE_SA_CMD1_1BIT 0x00000800 /* 1-bit crypto feedback */ -+#define SAFE_SA_CMD1_128BIT 0x00000c00 /* 128-bit crypto feedback */ -+#define SAFE_SA_CMD1_OPTIONS 0x00001000 /* HMAC/options mutable bit */ -+#define SAFE_SA_CMD1_HMAC SAFE_SA_CMD1_OPTIONS -+#define SAFE_SA_CMD1_SAREV1 0x00008000 /* SA Revision 1 */ -+#define SAFE_SA_CMD1_OFFSET 0x00ff0000 /* hash/crypto offset(dwords) */ -+#define SAFE_SA_CMD1_OFFSET_S 16 -+#define SAFE_SA_CMD1_AESKEYLEN 0x0f000000 /* AES key length */ -+#define SAFE_SA_CMD1_AES128 0x02000000 /* 128-bit AES key */ -+#define SAFE_SA_CMD1_AES192 0x03000000 /* 192-bit AES key */ -+#define SAFE_SA_CMD1_AES256 0x04000000 /* 256-bit AES key */ -+ -+/* -+ * Security Associate State Record (Rev 1). -+ */ -+struct safe_sastate { -+ u_int32_t sa_saved_iv[4]; /* saved IV (DES/3DES/AES) */ -+ u_int32_t sa_saved_hashbc; /* saved hash byte count */ -+ u_int32_t sa_saved_indigest[5]; /* saved inner digest */ -+}; -+#endif /* _SAFE_SAFEREG_H_ */ -diff -Nur linux-3.0.4.orig/crypto/ocf/safe/safevar.h linux-3.0.4/crypto/ocf/safe/safevar.h ---- linux-3.0.4.orig/crypto/ocf/safe/safevar.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/safe/safevar.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,229 @@ -+/*- -+ * The linux port of this code done by David McCullough -+ * Copyright (C) 2004-2010 David McCullough -+ * The license and original author are listed below. -+ * -+ * Copyright (c) 2003 Sam Leffler, Errno Consulting -+ * Copyright (c) 2003 Global Technology Associates, Inc. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ * -+ * $FreeBSD: src/sys/dev/safe/safevar.h,v 1.2 2006/05/17 18:34:26 pjd Exp $ -+ */ -+#ifndef _SAFE_SAFEVAR_H_ -+#define _SAFE_SAFEVAR_H_ -+ -+/* Maximum queue length */ -+#ifndef SAFE_MAX_NQUEUE -+#define SAFE_MAX_NQUEUE 60 -+#endif -+ -+#define SAFE_MAX_PART 64 /* Maximum scatter/gather depth */ -+#define SAFE_DMA_BOUNDARY 0 /* No boundary for source DMA ops */ -+#define SAFE_MAX_DSIZE 2048 /* MCLBYTES Fixed scatter particle size */ -+#define SAFE_MAX_SSIZE 0x0ffff /* Maximum gather particle size */ -+#define SAFE_MAX_DMA 0xfffff /* Maximum PE operand size (20 bits) */ -+/* total src+dst particle descriptors */ -+#define SAFE_TOTAL_DPART (SAFE_MAX_NQUEUE * SAFE_MAX_PART) -+#define SAFE_TOTAL_SPART (SAFE_MAX_NQUEUE * SAFE_MAX_PART) -+ -+#define SAFE_RNG_MAXBUFSIZ 128 /* 32-bit words */ -+ -+#define SAFE_CARD(sid) (((sid) & 0xf0000000) >> 28) -+#define SAFE_SESSION(sid) ( (sid) & 0x0fffffff) -+#define SAFE_SID(crd, sesn) (((crd) << 28) | ((sesn) & 0x0fffffff)) -+ -+#define SAFE_DEF_RTY 0xff /* PCI Retry Timeout */ -+#define SAFE_DEF_TOUT 0xff /* PCI TRDY Timeout */ -+#define SAFE_DEF_CACHELINE 0x01 /* Cache Line setting */ -+ -+#ifdef __KERNEL__ -+/* -+ * State associated with the allocation of each chunk -+ * of memory setup for DMA. -+ */ -+struct safe_dma_alloc { -+ dma_addr_t dma_paddr; -+ void *dma_vaddr; -+}; -+ -+/* -+ * Cryptographic operand state. One of these exists for each -+ * source and destination operand passed in from the crypto -+ * subsystem. When possible source and destination operands -+ * refer to the same memory. More often they are distinct. -+ * We track the virtual address of each operand as well as -+ * where each is mapped for DMA. -+ */ -+struct safe_operand { -+ union { -+ struct sk_buff *skb; -+ struct uio *io; -+ } u; -+ void *map; -+ int mapsize; /* total number of bytes in segs */ -+ struct { -+ dma_addr_t ds_addr; -+ int ds_len; -+ int ds_tlen; -+ } segs[SAFE_MAX_PART]; -+ int nsegs; -+}; -+ -+/* -+ * Packet engine ring entry and cryptographic operation state. -+ * The packet engine requires a ring of descriptors that contain -+ * pointers to various cryptographic state. However the ring -+ * configuration register allows you to specify an arbitrary size -+ * for ring entries. We use this feature to collect most of the -+ * state for each cryptographic request into one spot. Other than -+ * ring entries only the ``particle descriptors'' (scatter/gather -+ * lists) and the actual operand data are kept separate. The -+ * particle descriptors must also be organized in rings. The -+ * operand data can be located aribtrarily (modulo alignment constraints). -+ * -+ * Note that the descriptor ring is mapped onto the PCI bus so -+ * the hardware can DMA data. This means the entire ring must be -+ * contiguous. -+ */ -+struct safe_ringentry { -+ struct safe_desc re_desc; /* command descriptor */ -+ struct safe_sarec re_sa; /* SA record */ -+ struct safe_sastate re_sastate; /* SA state record */ -+ -+ struct cryptop *re_crp; /* crypto operation */ -+ -+ struct safe_operand re_src; /* source operand */ -+ struct safe_operand re_dst; /* destination operand */ -+ -+ int re_sesn; /* crypto session ID */ -+ int re_flags; -+#define SAFE_QFLAGS_COPYOUTIV 0x1 /* copy back on completion */ -+#define SAFE_QFLAGS_COPYOUTICV 0x2 /* copy back on completion */ -+}; -+ -+#define re_src_skb re_src.u.skb -+#define re_src_io re_src.u.io -+#define re_src_map re_src.map -+#define re_src_nsegs re_src.nsegs -+#define re_src_segs re_src.segs -+#define re_src_mapsize re_src.mapsize -+ -+#define re_dst_skb re_dst.u.skb -+#define re_dst_io re_dst.u.io -+#define re_dst_map re_dst.map -+#define re_dst_nsegs re_dst.nsegs -+#define re_dst_segs re_dst.segs -+#define re_dst_mapsize re_dst.mapsize -+ -+struct rndstate_test; -+ -+struct safe_session { -+ u_int32_t ses_used; -+ u_int32_t ses_klen; /* key length in bits */ -+ u_int32_t ses_key[8]; /* DES/3DES/AES key */ -+ u_int32_t ses_mlen; /* hmac length in bytes */ -+ u_int32_t ses_hminner[5]; /* hmac inner state */ -+ u_int32_t ses_hmouter[5]; /* hmac outer state */ -+}; -+ -+struct safe_pkq { -+ struct list_head pkq_list; -+ struct cryptkop *pkq_krp; -+}; -+ -+struct safe_softc { -+ softc_device_decl sc_dev; -+ u32 sc_irq; -+ -+ struct pci_dev *sc_pcidev; -+ ocf_iomem_t sc_base_addr; -+ -+ u_int sc_chiprev; /* major/minor chip revision */ -+ int sc_flags; /* device specific flags */ -+#define SAFE_FLAGS_KEY 0x01 /* has key accelerator */ -+#define SAFE_FLAGS_RNG 0x02 /* hardware rng */ -+ int sc_suspended; -+ int sc_needwakeup; /* notify crypto layer */ -+ int32_t sc_cid; /* crypto tag */ -+ -+ struct safe_dma_alloc sc_ringalloc; /* PE ring allocation state */ -+ struct safe_ringentry *sc_ring; /* PE ring */ -+ struct safe_ringentry *sc_ringtop; /* PE ring top */ -+ struct safe_ringentry *sc_front; /* next free entry */ -+ struct safe_ringentry *sc_back; /* next pending entry */ -+ int sc_nqchip; /* # passed to chip */ -+ spinlock_t sc_ringmtx; /* PE ring lock */ -+ struct safe_pdesc *sc_spring; /* src particle ring */ -+ struct safe_pdesc *sc_springtop; /* src particle ring top */ -+ struct safe_pdesc *sc_spfree; /* next free src particle */ -+ struct safe_dma_alloc sc_spalloc; /* src particle ring state */ -+ struct safe_pdesc *sc_dpring; /* dest particle ring */ -+ struct safe_pdesc *sc_dpringtop; /* dest particle ring top */ -+ struct safe_pdesc *sc_dpfree; /* next free dest particle */ -+ struct safe_dma_alloc sc_dpalloc; /* dst particle ring state */ -+ int sc_nsessions; /* # of sessions */ -+ struct safe_session *sc_sessions; /* sessions */ -+ -+ struct timer_list sc_pkto; /* PK polling */ -+ spinlock_t sc_pkmtx; /* PK lock */ -+ struct list_head sc_pkq; /* queue of PK requests */ -+ struct safe_pkq *sc_pkq_cur; /* current processing request */ -+ u_int32_t sc_pk_reslen, sc_pk_resoff; -+ -+ int sc_max_dsize; /* maximum safe DMA size */ -+}; -+#endif /* __KERNEL__ */ -+ -+struct safe_stats { -+ u_int64_t st_ibytes; -+ u_int64_t st_obytes; -+ u_int32_t st_ipackets; -+ u_int32_t st_opackets; -+ u_int32_t st_invalid; /* invalid argument */ -+ u_int32_t st_badsession; /* invalid session id */ -+ u_int32_t st_badflags; /* flags indicate !(mbuf | uio) */ -+ u_int32_t st_nodesc; /* op submitted w/o descriptors */ -+ u_int32_t st_badalg; /* unsupported algorithm */ -+ u_int32_t st_ringfull; /* PE descriptor ring full */ -+ u_int32_t st_peoperr; /* PE marked error */ -+ u_int32_t st_dmaerr; /* PE DMA error */ -+ u_int32_t st_bypasstoobig; /* bypass > 96 bytes */ -+ u_int32_t st_skipmismatch; /* enc part begins before auth part */ -+ u_int32_t st_lenmismatch; /* enc length different auth length */ -+ u_int32_t st_coffmisaligned; /* crypto offset not 32-bit aligned */ -+ u_int32_t st_cofftoobig; /* crypto offset > 255 words */ -+ u_int32_t st_iovmisaligned; /* iov op not aligned */ -+ u_int32_t st_iovnotuniform; /* iov op not suitable */ -+ u_int32_t st_unaligned; /* unaligned src caused copy */ -+ u_int32_t st_notuniform; /* non-uniform src caused copy */ -+ u_int32_t st_nomap; /* bus_dmamap_create failed */ -+ u_int32_t st_noload; /* bus_dmamap_load_* failed */ -+ u_int32_t st_nombuf; /* MGET* failed */ -+ u_int32_t st_nomcl; /* MCLGET* failed */ -+ u_int32_t st_maxqchip; /* max mcr1 ops out for processing */ -+ u_int32_t st_rng; /* RNG requests */ -+ u_int32_t st_rngalarm; /* RNG alarm requests */ -+ u_int32_t st_noicvcopy; /* ICV data copies suppressed */ -+}; -+#endif /* _SAFE_SAFEVAR_H_ */ -diff -Nur linux-3.0.4.orig/crypto/ocf/safe/sha1.c linux-3.0.4/crypto/ocf/safe/sha1.c ---- linux-3.0.4.orig/crypto/ocf/safe/sha1.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/safe/sha1.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,279 @@ -+/* $KAME: sha1.c,v 1.5 2000/11/08 06:13:08 itojun Exp $ */ -+/* -+ * Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. Neither the name of the project nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ */ -+ -+/* -+ * FIPS pub 180-1: Secure Hash Algorithm (SHA-1) -+ * based on: http://csrc.nist.gov/fips/fip180-1.txt -+ * implemented by Jun-ichiro itojun Itoh -+ */ -+ -+#if 0 -+#include -+__FBSDID("$FreeBSD: src/sys/crypto/sha1.c,v 1.9 2003/06/10 21:36:57 obrien Exp $"); -+ -+#include -+#include -+#include -+#include -+ -+#include -+#endif -+ -+/* sanity check */ -+#if BYTE_ORDER != BIG_ENDIAN -+# if BYTE_ORDER != LITTLE_ENDIAN -+# define unsupported 1 -+# endif -+#endif -+ -+#ifndef unsupported -+ -+/* constant table */ -+static u_int32_t _K[] = { 0x5a827999, 0x6ed9eba1, 0x8f1bbcdc, 0xca62c1d6 }; -+#define K(t) _K[(t) / 20] -+ -+#define F0(b, c, d) (((b) & (c)) | ((~(b)) & (d))) -+#define F1(b, c, d) (((b) ^ (c)) ^ (d)) -+#define F2(b, c, d) (((b) & (c)) | ((b) & (d)) | ((c) & (d))) -+#define F3(b, c, d) (((b) ^ (c)) ^ (d)) -+ -+#define S(n, x) (((x) << (n)) | ((x) >> (32 - n))) -+ -+#undef H -+#define H(n) (ctxt->h.b32[(n)]) -+#define COUNT (ctxt->count) -+#define BCOUNT (ctxt->c.b64[0] / 8) -+#define W(n) (ctxt->m.b32[(n)]) -+ -+#define PUTBYTE(x) { \ -+ ctxt->m.b8[(COUNT % 64)] = (x); \ -+ COUNT++; \ -+ COUNT %= 64; \ -+ ctxt->c.b64[0] += 8; \ -+ if (COUNT % 64 == 0) \ -+ sha1_step(ctxt); \ -+ } -+ -+#define PUTPAD(x) { \ -+ ctxt->m.b8[(COUNT % 64)] = (x); \ -+ COUNT++; \ -+ COUNT %= 64; \ -+ if (COUNT % 64 == 0) \ -+ sha1_step(ctxt); \ -+ } -+ -+static void sha1_step(struct sha1_ctxt *); -+ -+static void -+sha1_step(ctxt) -+ struct sha1_ctxt *ctxt; -+{ -+ u_int32_t a, b, c, d, e; -+ size_t t, s; -+ u_int32_t tmp; -+ -+#if BYTE_ORDER == LITTLE_ENDIAN -+ struct sha1_ctxt tctxt; -+ bcopy(&ctxt->m.b8[0], &tctxt.m.b8[0], 64); -+ ctxt->m.b8[0] = tctxt.m.b8[3]; ctxt->m.b8[1] = tctxt.m.b8[2]; -+ ctxt->m.b8[2] = tctxt.m.b8[1]; ctxt->m.b8[3] = tctxt.m.b8[0]; -+ ctxt->m.b8[4] = tctxt.m.b8[7]; ctxt->m.b8[5] = tctxt.m.b8[6]; -+ ctxt->m.b8[6] = tctxt.m.b8[5]; ctxt->m.b8[7] = tctxt.m.b8[4]; -+ ctxt->m.b8[8] = tctxt.m.b8[11]; ctxt->m.b8[9] = tctxt.m.b8[10]; -+ ctxt->m.b8[10] = tctxt.m.b8[9]; ctxt->m.b8[11] = tctxt.m.b8[8]; -+ ctxt->m.b8[12] = tctxt.m.b8[15]; ctxt->m.b8[13] = tctxt.m.b8[14]; -+ ctxt->m.b8[14] = tctxt.m.b8[13]; ctxt->m.b8[15] = tctxt.m.b8[12]; -+ ctxt->m.b8[16] = tctxt.m.b8[19]; ctxt->m.b8[17] = tctxt.m.b8[18]; -+ ctxt->m.b8[18] = tctxt.m.b8[17]; ctxt->m.b8[19] = tctxt.m.b8[16]; -+ ctxt->m.b8[20] = tctxt.m.b8[23]; ctxt->m.b8[21] = tctxt.m.b8[22]; -+ ctxt->m.b8[22] = tctxt.m.b8[21]; ctxt->m.b8[23] = tctxt.m.b8[20]; -+ ctxt->m.b8[24] = tctxt.m.b8[27]; ctxt->m.b8[25] = tctxt.m.b8[26]; -+ ctxt->m.b8[26] = tctxt.m.b8[25]; ctxt->m.b8[27] = tctxt.m.b8[24]; -+ ctxt->m.b8[28] = tctxt.m.b8[31]; ctxt->m.b8[29] = tctxt.m.b8[30]; -+ ctxt->m.b8[30] = tctxt.m.b8[29]; ctxt->m.b8[31] = tctxt.m.b8[28]; -+ ctxt->m.b8[32] = tctxt.m.b8[35]; ctxt->m.b8[33] = tctxt.m.b8[34]; -+ ctxt->m.b8[34] = tctxt.m.b8[33]; ctxt->m.b8[35] = tctxt.m.b8[32]; -+ ctxt->m.b8[36] = tctxt.m.b8[39]; ctxt->m.b8[37] = tctxt.m.b8[38]; -+ ctxt->m.b8[38] = tctxt.m.b8[37]; ctxt->m.b8[39] = tctxt.m.b8[36]; -+ ctxt->m.b8[40] = tctxt.m.b8[43]; ctxt->m.b8[41] = tctxt.m.b8[42]; -+ ctxt->m.b8[42] = tctxt.m.b8[41]; ctxt->m.b8[43] = tctxt.m.b8[40]; -+ ctxt->m.b8[44] = tctxt.m.b8[47]; ctxt->m.b8[45] = tctxt.m.b8[46]; -+ ctxt->m.b8[46] = tctxt.m.b8[45]; ctxt->m.b8[47] = tctxt.m.b8[44]; -+ ctxt->m.b8[48] = tctxt.m.b8[51]; ctxt->m.b8[49] = tctxt.m.b8[50]; -+ ctxt->m.b8[50] = tctxt.m.b8[49]; ctxt->m.b8[51] = tctxt.m.b8[48]; -+ ctxt->m.b8[52] = tctxt.m.b8[55]; ctxt->m.b8[53] = tctxt.m.b8[54]; -+ ctxt->m.b8[54] = tctxt.m.b8[53]; ctxt->m.b8[55] = tctxt.m.b8[52]; -+ ctxt->m.b8[56] = tctxt.m.b8[59]; ctxt->m.b8[57] = tctxt.m.b8[58]; -+ ctxt->m.b8[58] = tctxt.m.b8[57]; ctxt->m.b8[59] = tctxt.m.b8[56]; -+ ctxt->m.b8[60] = tctxt.m.b8[63]; ctxt->m.b8[61] = tctxt.m.b8[62]; -+ ctxt->m.b8[62] = tctxt.m.b8[61]; ctxt->m.b8[63] = tctxt.m.b8[60]; -+#endif -+ -+ a = H(0); b = H(1); c = H(2); d = H(3); e = H(4); -+ -+ for (t = 0; t < 20; t++) { -+ s = t & 0x0f; -+ if (t >= 16) { -+ W(s) = S(1, W((s+13) & 0x0f) ^ W((s+8) & 0x0f) ^ W((s+2) & 0x0f) ^ W(s)); -+ } -+ tmp = S(5, a) + F0(b, c, d) + e + W(s) + K(t); -+ e = d; d = c; c = S(30, b); b = a; a = tmp; -+ } -+ for (t = 20; t < 40; t++) { -+ s = t & 0x0f; -+ W(s) = S(1, W((s+13) & 0x0f) ^ W((s+8) & 0x0f) ^ W((s+2) & 0x0f) ^ W(s)); -+ tmp = S(5, a) + F1(b, c, d) + e + W(s) + K(t); -+ e = d; d = c; c = S(30, b); b = a; a = tmp; -+ } -+ for (t = 40; t < 60; t++) { -+ s = t & 0x0f; -+ W(s) = S(1, W((s+13) & 0x0f) ^ W((s+8) & 0x0f) ^ W((s+2) & 0x0f) ^ W(s)); -+ tmp = S(5, a) + F2(b, c, d) + e + W(s) + K(t); -+ e = d; d = c; c = S(30, b); b = a; a = tmp; -+ } -+ for (t = 60; t < 80; t++) { -+ s = t & 0x0f; -+ W(s) = S(1, W((s+13) & 0x0f) ^ W((s+8) & 0x0f) ^ W((s+2) & 0x0f) ^ W(s)); -+ tmp = S(5, a) + F3(b, c, d) + e + W(s) + K(t); -+ e = d; d = c; c = S(30, b); b = a; a = tmp; -+ } -+ -+ H(0) = H(0) + a; -+ H(1) = H(1) + b; -+ H(2) = H(2) + c; -+ H(3) = H(3) + d; -+ H(4) = H(4) + e; -+ -+ bzero(&ctxt->m.b8[0], 64); -+} -+ -+/*------------------------------------------------------------*/ -+ -+void -+sha1_init(ctxt) -+ struct sha1_ctxt *ctxt; -+{ -+ bzero(ctxt, sizeof(struct sha1_ctxt)); -+ H(0) = 0x67452301; -+ H(1) = 0xefcdab89; -+ H(2) = 0x98badcfe; -+ H(3) = 0x10325476; -+ H(4) = 0xc3d2e1f0; -+} -+ -+void -+sha1_pad(ctxt) -+ struct sha1_ctxt *ctxt; -+{ -+ size_t padlen; /*pad length in bytes*/ -+ size_t padstart; -+ -+ PUTPAD(0x80); -+ -+ padstart = COUNT % 64; -+ padlen = 64 - padstart; -+ if (padlen < 8) { -+ bzero(&ctxt->m.b8[padstart], padlen); -+ COUNT += padlen; -+ COUNT %= 64; -+ sha1_step(ctxt); -+ padstart = COUNT % 64; /* should be 0 */ -+ padlen = 64 - padstart; /* should be 64 */ -+ } -+ bzero(&ctxt->m.b8[padstart], padlen - 8); -+ COUNT += (padlen - 8); -+ COUNT %= 64; -+#if BYTE_ORDER == BIG_ENDIAN -+ PUTPAD(ctxt->c.b8[0]); PUTPAD(ctxt->c.b8[1]); -+ PUTPAD(ctxt->c.b8[2]); PUTPAD(ctxt->c.b8[3]); -+ PUTPAD(ctxt->c.b8[4]); PUTPAD(ctxt->c.b8[5]); -+ PUTPAD(ctxt->c.b8[6]); PUTPAD(ctxt->c.b8[7]); -+#else -+ PUTPAD(ctxt->c.b8[7]); PUTPAD(ctxt->c.b8[6]); -+ PUTPAD(ctxt->c.b8[5]); PUTPAD(ctxt->c.b8[4]); -+ PUTPAD(ctxt->c.b8[3]); PUTPAD(ctxt->c.b8[2]); -+ PUTPAD(ctxt->c.b8[1]); PUTPAD(ctxt->c.b8[0]); -+#endif -+} -+ -+void -+sha1_loop(ctxt, input, len) -+ struct sha1_ctxt *ctxt; -+ const u_int8_t *input; -+ size_t len; -+{ -+ size_t gaplen; -+ size_t gapstart; -+ size_t off; -+ size_t copysiz; -+ -+ off = 0; -+ -+ while (off < len) { -+ gapstart = COUNT % 64; -+ gaplen = 64 - gapstart; -+ -+ copysiz = (gaplen < len - off) ? gaplen : len - off; -+ bcopy(&input[off], &ctxt->m.b8[gapstart], copysiz); -+ COUNT += copysiz; -+ COUNT %= 64; -+ ctxt->c.b64[0] += copysiz * 8; -+ if (COUNT % 64 == 0) -+ sha1_step(ctxt); -+ off += copysiz; -+ } -+} -+ -+void -+sha1_result(ctxt, digest0) -+ struct sha1_ctxt *ctxt; -+ caddr_t digest0; -+{ -+ u_int8_t *digest; -+ -+ digest = (u_int8_t *)digest0; -+ sha1_pad(ctxt); -+#if BYTE_ORDER == BIG_ENDIAN -+ bcopy(&ctxt->h.b8[0], digest, 20); -+#else -+ digest[0] = ctxt->h.b8[3]; digest[1] = ctxt->h.b8[2]; -+ digest[2] = ctxt->h.b8[1]; digest[3] = ctxt->h.b8[0]; -+ digest[4] = ctxt->h.b8[7]; digest[5] = ctxt->h.b8[6]; -+ digest[6] = ctxt->h.b8[5]; digest[7] = ctxt->h.b8[4]; -+ digest[8] = ctxt->h.b8[11]; digest[9] = ctxt->h.b8[10]; -+ digest[10] = ctxt->h.b8[9]; digest[11] = ctxt->h.b8[8]; -+ digest[12] = ctxt->h.b8[15]; digest[13] = ctxt->h.b8[14]; -+ digest[14] = ctxt->h.b8[13]; digest[15] = ctxt->h.b8[12]; -+ digest[16] = ctxt->h.b8[19]; digest[17] = ctxt->h.b8[18]; -+ digest[18] = ctxt->h.b8[17]; digest[19] = ctxt->h.b8[16]; -+#endif -+} -+ -+#endif /*unsupported*/ -diff -Nur linux-3.0.4.orig/crypto/ocf/safe/sha1.h linux-3.0.4/crypto/ocf/safe/sha1.h ---- linux-3.0.4.orig/crypto/ocf/safe/sha1.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/safe/sha1.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,72 @@ -+/* $FreeBSD: src/sys/crypto/sha1.h,v 1.8 2002/03/20 05:13:50 alfred Exp $ */ -+/* $KAME: sha1.h,v 1.5 2000/03/27 04:36:23 sumikawa Exp $ */ -+ -+/* -+ * Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. Neither the name of the project nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ */ -+/* -+ * FIPS pub 180-1: Secure Hash Algorithm (SHA-1) -+ * based on: http://csrc.nist.gov/fips/fip180-1.txt -+ * implemented by Jun-ichiro itojun Itoh -+ */ -+ -+#ifndef _NETINET6_SHA1_H_ -+#define _NETINET6_SHA1_H_ -+ -+struct sha1_ctxt { -+ union { -+ u_int8_t b8[20]; -+ u_int32_t b32[5]; -+ } h; -+ union { -+ u_int8_t b8[8]; -+ u_int64_t b64[1]; -+ } c; -+ union { -+ u_int8_t b8[64]; -+ u_int32_t b32[16]; -+ } m; -+ u_int8_t count; -+}; -+ -+#ifdef __KERNEL__ -+extern void sha1_init(struct sha1_ctxt *); -+extern void sha1_pad(struct sha1_ctxt *); -+extern void sha1_loop(struct sha1_ctxt *, const u_int8_t *, size_t); -+extern void sha1_result(struct sha1_ctxt *, caddr_t); -+ -+/* compatibilty with other SHA1 source codes */ -+typedef struct sha1_ctxt SHA1_CTX; -+#define SHA1Init(x) sha1_init((x)) -+#define SHA1Update(x, y, z) sha1_loop((x), (y), (z)) -+#define SHA1Final(x, y) sha1_result((y), (x)) -+#endif /* __KERNEL__ */ -+ -+#define SHA1_RESULTLEN (160/8) -+ -+#endif /*_NETINET6_SHA1_H_*/ -diff -Nur linux-3.0.4.orig/crypto/ocf/talitos/Makefile linux-3.0.4/crypto/ocf/talitos/Makefile ---- linux-3.0.4.orig/crypto/ocf/talitos/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/talitos/Makefile 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,12 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+obj-$(CONFIG_OCF_TALITOS) += talitos.o -+ -+obj ?= . -+EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/talitos/talitos.c linux-3.0.4/crypto/ocf/talitos/talitos.c ---- linux-3.0.4.orig/crypto/ocf/talitos/talitos.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/talitos/talitos.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,1355 @@ -+/* -+ * crypto/ocf/talitos/talitos.c -+ * -+ * An OCF-Linux module that uses Freescale's SEC to do the crypto. -+ * Based on crypto/ocf/hifn and crypto/ocf/safe OCF drivers -+ * -+ * Copyright (c) 2006 Freescale Semiconductor, Inc. -+ * -+ * This code written by Kim A. B. Phillips -+ * some code copied from files with the following: -+ * Copyright (C) 2004-2007 David McCullough -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * --------------------------------------------------------------------------- -+ * -+ * NOTES: -+ * -+ * The Freescale SEC (also known as 'talitos') resides on the -+ * internal bus, and runs asynchronous to the processor core. It has -+ * a wide gamut of cryptographic acceleration features, including single- -+ * pass IPsec (also known as algorithm chaining). To properly utilize -+ * all of the SEC's performance enhancing features, further reworking -+ * of higher level code (framework, applications) will be necessary. -+ * -+ * The following table shows which SEC version is present in which devices: -+ * -+ * Devices SEC version -+ * -+ * 8272, 8248 SEC 1.0 -+ * 885, 875 SEC 1.2 -+ * 8555E, 8541E SEC 2.0 -+ * 8349E SEC 2.01 -+ * 8548E SEC 2.1 -+ * -+ * The following table shows the features offered by each SEC version: -+ * -+ * Max. chan- -+ * version Bus I/F Clock nels DEU AESU AFEU MDEU PKEU RNG KEU -+ * -+ * SEC 1.0 internal 64b 100MHz 4 1 1 1 1 1 1 0 -+ * SEC 1.2 internal 32b 66MHz 1 1 1 0 1 0 0 0 -+ * SEC 2.0 internal 64b 166MHz 4 1 1 1 1 1 1 0 -+ * SEC 2.01 internal 64b 166MHz 4 1 1 1 1 1 1 0 -+ * SEC 2.1 internal 64b 333MHz 4 1 1 1 1 1 1 1 -+ * -+ * Each execution unit in the SEC has two modes of execution; channel and -+ * slave/debug. This driver employs the channel infrastructure in the -+ * device for convenience. Only the RNG is directly accessed due to the -+ * convenience of its random fifo pool. The relationship between the -+ * channels and execution units is depicted in the following diagram: -+ * -+ * ------- ------------ -+ * ---| ch0 |---| | -+ * ------- | | -+ * | |------+-------+-------+-------+------------ -+ * ------- | | | | | | | -+ * ---| ch1 |---| | | | | | | -+ * ------- | | ------ ------ ------ ------ ------ -+ * |controller| |DEU | |AESU| |MDEU| |PKEU| ... |RNG | -+ * ------- | | ------ ------ ------ ------ ------ -+ * ---| ch2 |---| | | | | | | -+ * ------- | | | | | | | -+ * | |------+-------+-------+-------+------------ -+ * ------- | | -+ * ---| ch3 |---| | -+ * ------- ------------ -+ * -+ * Channel ch0 may drive an aes operation to the aes unit (AESU), -+ * and, at the same time, ch1 may drive a message digest operation -+ * to the mdeu. Each channel has an input descriptor FIFO, and the -+ * FIFO can contain, e.g. on the 8541E, up to 24 entries, before a -+ * a buffer overrun error is triggered. The controller is responsible -+ * for fetching the data from descriptor pointers, and passing the -+ * data to the appropriate EUs. The controller also writes the -+ * cryptographic operation's result to memory. The SEC notifies -+ * completion by triggering an interrupt and/or setting the 1st byte -+ * of the hdr field to 0xff. -+ * -+ * TODO: -+ * o support more algorithms -+ * o support more versions of the SEC -+ * o add support for linux 2.4 -+ * o scatter-gather (sg) support -+ * o add support for public key ops (PKEU) -+ * o add statistics -+ */ -+ -+#include -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include /* dma_map_single() */ -+#include -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,15) -+#include -+#endif -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) -+#include -+#endif -+ -+#include -+#include -+ -+#define DRV_NAME "talitos" -+ -+#include "talitos_dev.h" -+#include "talitos_soft.h" -+ -+#define read_random(p,l) get_random_bytes(p,l) -+ -+const char talitos_driver_name[] = "Talitos OCF"; -+const char talitos_driver_version[] = "0.2"; -+ -+static int talitos_newsession(device_t dev, u_int32_t *sidp, -+ struct cryptoini *cri); -+static int talitos_freesession(device_t dev, u_int64_t tid); -+static int talitos_process(device_t dev, struct cryptop *crp, int hint); -+static void dump_talitos_status(struct talitos_softc *sc); -+static int talitos_submit(struct talitos_softc *sc, struct talitos_desc *td, -+ int chsel); -+static void talitos_doneprocessing(struct talitos_softc *sc); -+static void talitos_init_device(struct talitos_softc *sc); -+static void talitos_reset_device_master(struct talitos_softc *sc); -+static void talitos_reset_device(struct talitos_softc *sc); -+static void talitos_errorprocessing(struct talitos_softc *sc); -+#ifdef CONFIG_PPC_MERGE -+static int talitos_probe(struct of_device *ofdev, const struct of_device_id *match); -+static int talitos_remove(struct of_device *ofdev); -+#else -+static int talitos_probe(struct platform_device *pdev); -+static int talitos_remove(struct platform_device *pdev); -+#endif -+#ifdef CONFIG_OCF_RANDOMHARVEST -+static int talitos_read_random(void *arg, u_int32_t *buf, int maxwords); -+static void talitos_rng_init(struct talitos_softc *sc); -+#endif -+ -+static device_method_t talitos_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, talitos_newsession), -+ DEVMETHOD(cryptodev_freesession,talitos_freesession), -+ DEVMETHOD(cryptodev_process, talitos_process), -+}; -+ -+#define debug talitos_debug -+int talitos_debug = 0; -+module_param(talitos_debug, int, 0644); -+MODULE_PARM_DESC(talitos_debug, "Enable debug"); -+ -+static inline void talitos_write(volatile unsigned *addr, u32 val) -+{ -+ out_be32(addr, val); -+} -+ -+static inline u32 talitos_read(volatile unsigned *addr) -+{ -+ u32 val; -+ val = in_be32(addr); -+ return val; -+} -+ -+static void dump_talitos_status(struct talitos_softc *sc) -+{ -+ unsigned int v, v_hi, i, *ptr; -+ v = talitos_read(sc->sc_base_addr + TALITOS_MCR); -+ v_hi = talitos_read(sc->sc_base_addr + TALITOS_MCR_HI); -+ printk(KERN_INFO "%s: MCR 0x%08x_%08x\n", -+ device_get_nameunit(sc->sc_cdev), v, v_hi); -+ v = talitos_read(sc->sc_base_addr + TALITOS_IMR); -+ v_hi = talitos_read(sc->sc_base_addr + TALITOS_IMR_HI); -+ printk(KERN_INFO "%s: IMR 0x%08x_%08x\n", -+ device_get_nameunit(sc->sc_cdev), v, v_hi); -+ v = talitos_read(sc->sc_base_addr + TALITOS_ISR); -+ v_hi = talitos_read(sc->sc_base_addr + TALITOS_ISR_HI); -+ printk(KERN_INFO "%s: ISR 0x%08x_%08x\n", -+ device_get_nameunit(sc->sc_cdev), v, v_hi); -+ for (i = 0; i < sc->sc_num_channels; i++) { -+ v = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + -+ TALITOS_CH_CDPR); -+ v_hi = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + -+ TALITOS_CH_CDPR_HI); -+ printk(KERN_INFO "%s: CDPR ch%d 0x%08x_%08x\n", -+ device_get_nameunit(sc->sc_cdev), i, v, v_hi); -+ } -+ for (i = 0; i < sc->sc_num_channels; i++) { -+ v = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + -+ TALITOS_CH_CCPSR); -+ v_hi = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + -+ TALITOS_CH_CCPSR_HI); -+ printk(KERN_INFO "%s: CCPSR ch%d 0x%08x_%08x\n", -+ device_get_nameunit(sc->sc_cdev), i, v, v_hi); -+ } -+ ptr = sc->sc_base_addr + TALITOS_CH_DESCBUF; -+ for (i = 0; i < 16; i++) { -+ v = talitos_read(ptr++); v_hi = talitos_read(ptr++); -+ printk(KERN_INFO "%s: DESCBUF ch0 0x%08x_%08x (tdp%02d)\n", -+ device_get_nameunit(sc->sc_cdev), v, v_hi, i); -+ } -+ return; -+} -+ -+ -+#ifdef CONFIG_OCF_RANDOMHARVEST -+/* -+ * pull random numbers off the RNG FIFO, not exceeding amount available -+ */ -+static int -+talitos_read_random(void *arg, u_int32_t *buf, int maxwords) -+{ -+ struct talitos_softc *sc = (struct talitos_softc *) arg; -+ int rc; -+ u_int32_t v; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ /* check for things like FIFO underflow */ -+ v = talitos_read(sc->sc_base_addr + TALITOS_RNGISR_HI); -+ if (unlikely(v)) { -+ printk(KERN_ERR "%s: RNGISR_HI error %08x\n", -+ device_get_nameunit(sc->sc_cdev), v); -+ return 0; -+ } -+ /* -+ * OFL is number of available 64-bit words, -+ * shift and convert to a 32-bit word count -+ */ -+ v = talitos_read(sc->sc_base_addr + TALITOS_RNGSR_HI); -+ v = (v & TALITOS_RNGSR_HI_OFL) >> (16 - 1); -+ if (maxwords > v) -+ maxwords = v; -+ for (rc = 0; rc < maxwords; rc++) { -+ buf[rc] = talitos_read(sc->sc_base_addr + -+ TALITOS_RNG_FIFO + rc*sizeof(u_int32_t)); -+ } -+ if (maxwords & 1) { -+ /* -+ * RNG will complain with an AE in the RNGISR -+ * if we don't complete the pairs of 32-bit reads -+ * to its 64-bit register based FIFO -+ */ -+ v = talitos_read(sc->sc_base_addr + -+ TALITOS_RNG_FIFO + rc*sizeof(u_int32_t)); -+ } -+ -+ return rc; -+} -+ -+static void -+talitos_rng_init(struct talitos_softc *sc) -+{ -+ u_int32_t v; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ /* reset RNG EU */ -+ v = talitos_read(sc->sc_base_addr + TALITOS_RNGRCR_HI); -+ v |= TALITOS_RNGRCR_HI_SR; -+ talitos_write(sc->sc_base_addr + TALITOS_RNGRCR_HI, v); -+ while ((talitos_read(sc->sc_base_addr + TALITOS_RNGSR_HI) -+ & TALITOS_RNGSR_HI_RD) == 0) -+ cpu_relax(); -+ /* -+ * we tell the RNG to start filling the RNG FIFO -+ * by writing the RNGDSR -+ */ -+ v = talitos_read(sc->sc_base_addr + TALITOS_RNGDSR_HI); -+ talitos_write(sc->sc_base_addr + TALITOS_RNGDSR_HI, v); -+ /* -+ * 64 bits of data will be pushed onto the FIFO every -+ * 256 SEC cycles until the FIFO is full. The RNG then -+ * attempts to keep the FIFO full. -+ */ -+ v = talitos_read(sc->sc_base_addr + TALITOS_RNGISR_HI); -+ if (v) { -+ printk(KERN_ERR "%s: RNGISR_HI error %08x\n", -+ device_get_nameunit(sc->sc_cdev), v); -+ return; -+ } -+ /* -+ * n.b. we need to add a FIPS test here - if the RNG is going -+ * to fail, it's going to fail at reset time -+ */ -+ return; -+} -+#endif /* CONFIG_OCF_RANDOMHARVEST */ -+ -+/* -+ * Generate a new software session. -+ */ -+static int -+talitos_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) -+{ -+ struct cryptoini *c, *encini = NULL, *macini = NULL; -+ struct talitos_softc *sc = device_get_softc(dev); -+ struct talitos_session *ses = NULL; -+ int sesn; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ if (sidp == NULL || cri == NULL || sc == NULL) { -+ DPRINTF("%s,%d - EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ for (c = cri; c != NULL; c = c->cri_next) { -+ if (c->cri_alg == CRYPTO_MD5 || -+ c->cri_alg == CRYPTO_MD5_HMAC || -+ c->cri_alg == CRYPTO_SHA1 || -+ c->cri_alg == CRYPTO_SHA1_HMAC || -+ c->cri_alg == CRYPTO_NULL_HMAC) { -+ if (macini) -+ return EINVAL; -+ macini = c; -+ } else if (c->cri_alg == CRYPTO_DES_CBC || -+ c->cri_alg == CRYPTO_3DES_CBC || -+ c->cri_alg == CRYPTO_AES_CBC || -+ c->cri_alg == CRYPTO_NULL_CBC) { -+ if (encini) -+ return EINVAL; -+ encini = c; -+ } else { -+ DPRINTF("UNKNOWN c->cri_alg %d\n", encini->cri_alg); -+ return EINVAL; -+ } -+ } -+ if (encini == NULL && macini == NULL) -+ return EINVAL; -+ if (encini) { -+ /* validate key length */ -+ switch (encini->cri_alg) { -+ case CRYPTO_DES_CBC: -+ if (encini->cri_klen != 64) -+ return EINVAL; -+ break; -+ case CRYPTO_3DES_CBC: -+ if (encini->cri_klen != 192) { -+ return EINVAL; -+ } -+ break; -+ case CRYPTO_AES_CBC: -+ if (encini->cri_klen != 128 && -+ encini->cri_klen != 192 && -+ encini->cri_klen != 256) -+ return EINVAL; -+ break; -+ default: -+ DPRINTF("UNKNOWN encini->cri_alg %d\n", -+ encini->cri_alg); -+ return EINVAL; -+ } -+ } -+ -+ if (sc->sc_sessions == NULL) { -+ ses = sc->sc_sessions = (struct talitos_session *) -+ kmalloc(sizeof(struct talitos_session), SLAB_ATOMIC); -+ if (ses == NULL) -+ return ENOMEM; -+ memset(ses, 0, sizeof(struct talitos_session)); -+ sesn = 0; -+ sc->sc_nsessions = 1; -+ } else { -+ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { -+ if (sc->sc_sessions[sesn].ses_used == 0) { -+ ses = &sc->sc_sessions[sesn]; -+ break; -+ } -+ } -+ -+ if (ses == NULL) { -+ /* allocating session */ -+ sesn = sc->sc_nsessions; -+ ses = (struct talitos_session *) kmalloc( -+ (sesn + 1) * sizeof(struct talitos_session), -+ SLAB_ATOMIC); -+ if (ses == NULL) -+ return ENOMEM; -+ memset(ses, 0, -+ (sesn + 1) * sizeof(struct talitos_session)); -+ memcpy(ses, sc->sc_sessions, -+ sesn * sizeof(struct talitos_session)); -+ memset(sc->sc_sessions, 0, -+ sesn * sizeof(struct talitos_session)); -+ kfree(sc->sc_sessions); -+ sc->sc_sessions = ses; -+ ses = &sc->sc_sessions[sesn]; -+ sc->sc_nsessions++; -+ } -+ } -+ -+ ses->ses_used = 1; -+ -+ if (encini) { -+ ses->ses_klen = (encini->cri_klen + 7) / 8; -+ memcpy(ses->ses_key, encini->cri_key, ses->ses_klen); -+ if (macini) { -+ /* doing hash on top of cipher */ -+ ses->ses_hmac_len = (macini->cri_klen + 7) / 8; -+ memcpy(ses->ses_hmac, macini->cri_key, -+ ses->ses_hmac_len); -+ } -+ } else if (macini) { -+ /* doing hash */ -+ ses->ses_klen = (macini->cri_klen + 7) / 8; -+ memcpy(ses->ses_key, macini->cri_key, ses->ses_klen); -+ } -+ -+ /* back compat way of determining MSC result len */ -+ if (macini) { -+ ses->ses_mlen = macini->cri_mlen; -+ if (ses->ses_mlen == 0) { -+ if (macini->cri_alg == CRYPTO_MD5_HMAC) -+ ses->ses_mlen = MD5_HASH_LEN; -+ else -+ ses->ses_mlen = SHA1_HASH_LEN; -+ } -+ } -+ -+ /* really should make up a template td here, -+ * and only fill things like i/o and direction in process() */ -+ -+ /* assign session ID */ -+ *sidp = TALITOS_SID(sc->sc_num, sesn); -+ return 0; -+} -+ -+/* -+ * Deallocate a session. -+ */ -+static int -+talitos_freesession(device_t dev, u_int64_t tid) -+{ -+ struct talitos_softc *sc = device_get_softc(dev); -+ int session, ret; -+ u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; -+ -+ if (sc == NULL) -+ return EINVAL; -+ session = TALITOS_SESSION(sid); -+ if (session < sc->sc_nsessions) { -+ memset(&sc->sc_sessions[session], 0, -+ sizeof(sc->sc_sessions[session])); -+ ret = 0; -+ } else -+ ret = EINVAL; -+ return ret; -+} -+ -+/* -+ * launch device processing - it will come back with done notification -+ * in the form of an interrupt and/or HDR_DONE_BITS in header -+ */ -+static int -+talitos_submit( -+ struct talitos_softc *sc, -+ struct talitos_desc *td, -+ int chsel) -+{ -+ u_int32_t v; -+ -+ v = dma_map_single(NULL, td, sizeof(*td), DMA_TO_DEVICE); -+ talitos_write(sc->sc_base_addr + -+ chsel*TALITOS_CH_OFFSET + TALITOS_CH_FF, 0); -+ talitos_write(sc->sc_base_addr + -+ chsel*TALITOS_CH_OFFSET + TALITOS_CH_FF_HI, v); -+ return 0; -+} -+ -+static int -+talitos_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ int i, err = 0, ivsize; -+ struct talitos_softc *sc = device_get_softc(dev); -+ struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; -+ caddr_t iv; -+ struct talitos_session *ses; -+ struct talitos_desc *td; -+ unsigned long flags; -+ /* descriptor mappings */ -+ int hmac_key, hmac_data, cipher_iv, cipher_key, -+ in_fifo, out_fifo, cipher_iv_out; -+ static int chsel = -1; -+ u_int32_t rand_iv[4]; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { -+ return EINVAL; -+ } -+ crp->crp_etype = 0; -+ if (TALITOS_SESSION(crp->crp_sid) >= sc->sc_nsessions) { -+ return EINVAL; -+ } -+ -+ ses = &sc->sc_sessions[TALITOS_SESSION(crp->crp_sid)]; -+ -+ /* enter the channel scheduler */ -+ spin_lock_irqsave(&sc->sc_chnfifolock[sc->sc_num_channels], flags); -+ -+ /* reuse channel that already had/has requests for the required EU */ -+ for (i = 0; i < sc->sc_num_channels; i++) { -+ if (sc->sc_chnlastalg[i] == crp->crp_desc->crd_alg) -+ break; -+ } -+ if (i == sc->sc_num_channels) { -+ /* -+ * haven't seen this algo the last sc_num_channels or more -+ * use round robin in this case -+ * nb: sc->sc_num_channels must be power of 2 -+ */ -+ chsel = (chsel + 1) & (sc->sc_num_channels - 1); -+ } else { -+ /* -+ * matches channel with same target execution unit; -+ * use same channel in this case -+ */ -+ chsel = i; -+ } -+ sc->sc_chnlastalg[chsel] = crp->crp_desc->crd_alg; -+ -+ /* release the channel scheduler lock */ -+ spin_unlock_irqrestore(&sc->sc_chnfifolock[sc->sc_num_channels], flags); -+ -+ /* acquire the selected channel fifo lock */ -+ spin_lock_irqsave(&sc->sc_chnfifolock[chsel], flags); -+ -+ /* find and reserve next available descriptor-cryptop pair */ -+ for (i = 0; i < sc->sc_chfifo_len; i++) { -+ if (sc->sc_chnfifo[chsel][i].cf_desc.hdr == 0) { -+ /* -+ * ensure correct descriptor formation by -+ * avoiding inadvertently setting "optional" entries -+ * e.g. not using "optional" dptr2 for MD/HMAC descs -+ */ -+ memset(&sc->sc_chnfifo[chsel][i].cf_desc, -+ 0, sizeof(*td)); -+ /* reserve it with done notification request bit */ -+ sc->sc_chnfifo[chsel][i].cf_desc.hdr |= -+ TALITOS_DONE_NOTIFY; -+ break; -+ } -+ } -+ spin_unlock_irqrestore(&sc->sc_chnfifolock[chsel], flags); -+ -+ if (i == sc->sc_chfifo_len) { -+ /* fifo full */ -+ err = ERESTART; -+ goto errout; -+ } -+ -+ td = &sc->sc_chnfifo[chsel][i].cf_desc; -+ sc->sc_chnfifo[chsel][i].cf_crp = crp; -+ -+ crd1 = crp->crp_desc; -+ if (crd1 == NULL) { -+ err = EINVAL; -+ goto errout; -+ } -+ crd2 = crd1->crd_next; -+ /* prevent compiler warning */ -+ hmac_key = 0; -+ hmac_data = 0; -+ if (crd2 == NULL) { -+ td->hdr |= TD_TYPE_COMMON_NONSNOOP_NO_AFEU; -+ /* assign descriptor dword ptr mappings for this desc. type */ -+ cipher_iv = 1; -+ cipher_key = 2; -+ in_fifo = 3; -+ cipher_iv_out = 5; -+ if (crd1->crd_alg == CRYPTO_MD5_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1 || -+ crd1->crd_alg == CRYPTO_MD5) { -+ out_fifo = 5; -+ maccrd = crd1; -+ enccrd = NULL; -+ } else if (crd1->crd_alg == CRYPTO_DES_CBC || -+ crd1->crd_alg == CRYPTO_3DES_CBC || -+ crd1->crd_alg == CRYPTO_AES_CBC || -+ crd1->crd_alg == CRYPTO_ARC4) { -+ out_fifo = 4; -+ maccrd = NULL; -+ enccrd = crd1; -+ } else { -+ DPRINTF("UNKNOWN crd1->crd_alg %d\n", crd1->crd_alg); -+ err = EINVAL; -+ goto errout; -+ } -+ } else { -+ if (sc->sc_desc_types & TALITOS_HAS_DT_IPSEC_ESP) { -+ td->hdr |= TD_TYPE_IPSEC_ESP; -+ } else { -+ DPRINTF("unimplemented: multiple descriptor ipsec\n"); -+ err = EINVAL; -+ goto errout; -+ } -+ /* assign descriptor dword ptr mappings for this desc. type */ -+ hmac_key = 0; -+ hmac_data = 1; -+ cipher_iv = 2; -+ cipher_key = 3; -+ in_fifo = 4; -+ out_fifo = 5; -+ cipher_iv_out = 6; -+ if ((crd1->crd_alg == CRYPTO_MD5_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1_HMAC || -+ crd1->crd_alg == CRYPTO_MD5 || -+ crd1->crd_alg == CRYPTO_SHA1) && -+ (crd2->crd_alg == CRYPTO_DES_CBC || -+ crd2->crd_alg == CRYPTO_3DES_CBC || -+ crd2->crd_alg == CRYPTO_AES_CBC || -+ crd2->crd_alg == CRYPTO_ARC4) && -+ ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { -+ maccrd = crd1; -+ enccrd = crd2; -+ } else if ((crd1->crd_alg == CRYPTO_DES_CBC || -+ crd1->crd_alg == CRYPTO_ARC4 || -+ crd1->crd_alg == CRYPTO_3DES_CBC || -+ crd1->crd_alg == CRYPTO_AES_CBC) && -+ (crd2->crd_alg == CRYPTO_MD5_HMAC || -+ crd2->crd_alg == CRYPTO_SHA1_HMAC || -+ crd2->crd_alg == CRYPTO_MD5 || -+ crd2->crd_alg == CRYPTO_SHA1) && -+ (crd1->crd_flags & CRD_F_ENCRYPT)) { -+ enccrd = crd1; -+ maccrd = crd2; -+ } else { -+ /* We cannot order the SEC as requested */ -+ printk("%s: cannot do the order\n", -+ device_get_nameunit(sc->sc_cdev)); -+ err = EINVAL; -+ goto errout; -+ } -+ } -+ /* assign in_fifo and out_fifo based on input/output struct type */ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ /* using SKB buffers */ -+ struct sk_buff *skb = (struct sk_buff *)crp->crp_buf; -+ if (skb_shinfo(skb)->nr_frags) { -+ printk("%s: skb frags unimplemented\n", -+ device_get_nameunit(sc->sc_cdev)); -+ err = EINVAL; -+ goto errout; -+ } -+ td->ptr[in_fifo].ptr = dma_map_single(NULL, skb->data, -+ skb->len, DMA_TO_DEVICE); -+ td->ptr[in_fifo].len = skb->len; -+ td->ptr[out_fifo].ptr = dma_map_single(NULL, skb->data, -+ skb->len, DMA_TO_DEVICE); -+ td->ptr[out_fifo].len = skb->len; -+ td->ptr[hmac_data].ptr = dma_map_single(NULL, skb->data, -+ skb->len, DMA_TO_DEVICE); -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ /* using IOV buffers */ -+ struct uio *uiop = (struct uio *)crp->crp_buf; -+ if (uiop->uio_iovcnt > 1) { -+ printk("%s: iov frags unimplemented\n", -+ device_get_nameunit(sc->sc_cdev)); -+ err = EINVAL; -+ goto errout; -+ } -+ td->ptr[in_fifo].ptr = dma_map_single(NULL, -+ uiop->uio_iov->iov_base, crp->crp_ilen, DMA_TO_DEVICE); -+ td->ptr[in_fifo].len = crp->crp_ilen; -+ /* crp_olen is never set; always use crp_ilen */ -+ td->ptr[out_fifo].ptr = dma_map_single(NULL, -+ uiop->uio_iov->iov_base, -+ crp->crp_ilen, DMA_TO_DEVICE); -+ td->ptr[out_fifo].len = crp->crp_ilen; -+ } else { -+ /* using contig buffers */ -+ td->ptr[in_fifo].ptr = dma_map_single(NULL, -+ crp->crp_buf, crp->crp_ilen, DMA_TO_DEVICE); -+ td->ptr[in_fifo].len = crp->crp_ilen; -+ td->ptr[out_fifo].ptr = dma_map_single(NULL, -+ crp->crp_buf, crp->crp_ilen, DMA_TO_DEVICE); -+ td->ptr[out_fifo].len = crp->crp_ilen; -+ } -+ if (enccrd) { -+ switch (enccrd->crd_alg) { -+ case CRYPTO_3DES_CBC: -+ td->hdr |= TALITOS_MODE0_DEU_3DES; -+ /* FALLTHROUGH */ -+ case CRYPTO_DES_CBC: -+ td->hdr |= TALITOS_SEL0_DEU -+ | TALITOS_MODE0_DEU_CBC; -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) -+ td->hdr |= TALITOS_MODE0_DEU_ENC; -+ ivsize = 2*sizeof(u_int32_t); -+ DPRINTF("%cDES ses %d ch %d len %d\n", -+ (td->hdr & TALITOS_MODE0_DEU_3DES)?'3':'1', -+ (u32)TALITOS_SESSION(crp->crp_sid), -+ chsel, td->ptr[in_fifo].len); -+ break; -+ case CRYPTO_AES_CBC: -+ td->hdr |= TALITOS_SEL0_AESU -+ | TALITOS_MODE0_AESU_CBC; -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) -+ td->hdr |= TALITOS_MODE0_AESU_ENC; -+ ivsize = 4*sizeof(u_int32_t); -+ DPRINTF("AES ses %d ch %d len %d\n", -+ (u32)TALITOS_SESSION(crp->crp_sid), -+ chsel, td->ptr[in_fifo].len); -+ break; -+ default: -+ printk("%s: unimplemented enccrd->crd_alg %d\n", -+ device_get_nameunit(sc->sc_cdev), enccrd->crd_alg); -+ err = EINVAL; -+ goto errout; -+ } -+ /* -+ * Setup encrypt/decrypt state. When using basic ops -+ * we can't use an inline IV because hash/crypt offset -+ * must be from the end of the IV to the start of the -+ * crypt data and this leaves out the preceding header -+ * from the hash calculation. Instead we place the IV -+ * in the state record and set the hash/crypt offset to -+ * copy both the header+IV. -+ */ -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) { -+ td->hdr |= TALITOS_DIR_OUTBOUND; -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) -+ iv = enccrd->crd_iv; -+ else -+ read_random((iv = (caddr_t) rand_iv), sizeof(rand_iv)); -+ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ enccrd->crd_inject, ivsize, iv); -+ } -+ } else { -+ td->hdr |= TALITOS_DIR_INBOUND; -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) { -+ iv = enccrd->crd_iv; -+ } else { -+ iv = (caddr_t) rand_iv; -+ crypto_copydata(crp->crp_flags, crp->crp_buf, -+ enccrd->crd_inject, ivsize, iv); -+ } -+ } -+ td->ptr[cipher_iv].ptr = dma_map_single(NULL, iv, ivsize, -+ DMA_TO_DEVICE); -+ td->ptr[cipher_iv].len = ivsize; -+ /* -+ * we don't need the cipher iv out length/pointer -+ * field to do ESP IPsec. Therefore we set the len field as 0, -+ * which tells the SEC not to do anything with this len/ptr -+ * field. Previously, when length/pointer as pointing to iv, -+ * it gave us corruption of packets. -+ */ -+ td->ptr[cipher_iv_out].len = 0; -+ } -+ if (enccrd && maccrd) { -+ /* this is ipsec only for now */ -+ td->hdr |= TALITOS_SEL1_MDEU -+ | TALITOS_MODE1_MDEU_INIT -+ | TALITOS_MODE1_MDEU_PAD; -+ switch (maccrd->crd_alg) { -+ case CRYPTO_MD5: -+ td->hdr |= TALITOS_MODE1_MDEU_MD5; -+ break; -+ case CRYPTO_MD5_HMAC: -+ td->hdr |= TALITOS_MODE1_MDEU_MD5_HMAC; -+ break; -+ case CRYPTO_SHA1: -+ td->hdr |= TALITOS_MODE1_MDEU_SHA1; -+ break; -+ case CRYPTO_SHA1_HMAC: -+ td->hdr |= TALITOS_MODE1_MDEU_SHA1_HMAC; -+ break; -+ default: -+ /* We cannot order the SEC as requested */ -+ printk("%s: cannot do the order\n", -+ device_get_nameunit(sc->sc_cdev)); -+ err = EINVAL; -+ goto errout; -+ } -+ if ((maccrd->crd_alg == CRYPTO_MD5_HMAC) || -+ (maccrd->crd_alg == CRYPTO_SHA1_HMAC)) { -+ /* -+ * The offset from hash data to the start of -+ * crypt data is the difference in the skips. -+ */ -+ /* ipsec only for now */ -+ td->ptr[hmac_key].ptr = dma_map_single(NULL, -+ ses->ses_hmac, ses->ses_hmac_len, DMA_TO_DEVICE); -+ td->ptr[hmac_key].len = ses->ses_hmac_len; -+ td->ptr[in_fifo].ptr += enccrd->crd_skip; -+ td->ptr[in_fifo].len = enccrd->crd_len; -+ td->ptr[out_fifo].ptr += enccrd->crd_skip; -+ td->ptr[out_fifo].len = enccrd->crd_len; -+ /* bytes of HMAC to postpend to ciphertext */ -+ td->ptr[out_fifo].extent = ses->ses_mlen; -+ td->ptr[hmac_data].ptr += maccrd->crd_skip; -+ td->ptr[hmac_data].len = enccrd->crd_skip - maccrd->crd_skip; -+ } -+ if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) { -+ printk("%s: CRD_F_KEY_EXPLICIT unimplemented\n", -+ device_get_nameunit(sc->sc_cdev)); -+ } -+ } -+ if (!enccrd && maccrd) { -+ /* single MD5 or SHA */ -+ td->hdr |= TALITOS_SEL0_MDEU -+ | TALITOS_MODE0_MDEU_INIT -+ | TALITOS_MODE0_MDEU_PAD; -+ switch (maccrd->crd_alg) { -+ case CRYPTO_MD5: -+ td->hdr |= TALITOS_MODE0_MDEU_MD5; -+ DPRINTF("MD5 ses %d ch %d len %d\n", -+ (u32)TALITOS_SESSION(crp->crp_sid), -+ chsel, td->ptr[in_fifo].len); -+ break; -+ case CRYPTO_MD5_HMAC: -+ td->hdr |= TALITOS_MODE0_MDEU_MD5_HMAC; -+ break; -+ case CRYPTO_SHA1: -+ td->hdr |= TALITOS_MODE0_MDEU_SHA1; -+ DPRINTF("SHA1 ses %d ch %d len %d\n", -+ (u32)TALITOS_SESSION(crp->crp_sid), -+ chsel, td->ptr[in_fifo].len); -+ break; -+ case CRYPTO_SHA1_HMAC: -+ td->hdr |= TALITOS_MODE0_MDEU_SHA1_HMAC; -+ break; -+ default: -+ /* We cannot order the SEC as requested */ -+ DPRINTF("cannot do the order\n"); -+ err = EINVAL; -+ goto errout; -+ } -+ -+ if (crp->crp_flags & CRYPTO_F_IOV) -+ td->ptr[out_fifo].ptr += maccrd->crd_inject; -+ -+ if ((maccrd->crd_alg == CRYPTO_MD5_HMAC) || -+ (maccrd->crd_alg == CRYPTO_SHA1_HMAC)) { -+ td->ptr[hmac_key].ptr = dma_map_single(NULL, -+ ses->ses_hmac, ses->ses_hmac_len, -+ DMA_TO_DEVICE); -+ td->ptr[hmac_key].len = ses->ses_hmac_len; -+ } -+ } -+ else { -+ /* using process key (session data has duplicate) */ -+ td->ptr[cipher_key].ptr = dma_map_single(NULL, -+ enccrd->crd_key, (enccrd->crd_klen + 7) / 8, -+ DMA_TO_DEVICE); -+ td->ptr[cipher_key].len = (enccrd->crd_klen + 7) / 8; -+ } -+ /* descriptor complete - GO! */ -+ return talitos_submit(sc, td, chsel); -+ -+errout: -+ if (err != ERESTART) { -+ crp->crp_etype = err; -+ crypto_done(crp); -+ } -+ return err; -+} -+ -+/* go through all channels descriptors, notifying OCF what has -+ * _and_hasn't_ successfully completed and reset the device -+ * (otherwise it's up to decoding desc hdrs!) -+ */ -+static void talitos_errorprocessing(struct talitos_softc *sc) -+{ -+ unsigned long flags; -+ int i, j; -+ -+ /* disable further scheduling until under control */ -+ spin_lock_irqsave(&sc->sc_chnfifolock[sc->sc_num_channels], flags); -+ -+ if (debug) dump_talitos_status(sc); -+ /* go through descriptors, try and salvage those successfully done, -+ * and EIO those that weren't -+ */ -+ for (i = 0; i < sc->sc_num_channels; i++) { -+ spin_lock_irqsave(&sc->sc_chnfifolock[i], flags); -+ for (j = 0; j < sc->sc_chfifo_len; j++) { -+ if (sc->sc_chnfifo[i][j].cf_desc.hdr) { -+ if ((sc->sc_chnfifo[i][j].cf_desc.hdr -+ & TALITOS_HDR_DONE_BITS) -+ != TALITOS_HDR_DONE_BITS) { -+ /* this one didn't finish */ -+ /* signify in crp->etype */ -+ sc->sc_chnfifo[i][j].cf_crp->crp_etype -+ = EIO; -+ } -+ } else -+ continue; /* free entry */ -+ /* either way, notify ocf */ -+ crypto_done(sc->sc_chnfifo[i][j].cf_crp); -+ /* and tag it available again -+ * -+ * memset to ensure correct descriptor formation by -+ * avoiding inadvertently setting "optional" entries -+ * e.g. not using "optional" dptr2 MD/HMAC processing -+ */ -+ memset(&sc->sc_chnfifo[i][j].cf_desc, -+ 0, sizeof(struct talitos_desc)); -+ } -+ spin_unlock_irqrestore(&sc->sc_chnfifolock[i], flags); -+ } -+ /* reset and initialize the SEC h/w device */ -+ talitos_reset_device(sc); -+ talitos_init_device(sc); -+#ifdef CONFIG_OCF_RANDOMHARVEST -+ if (sc->sc_exec_units & TALITOS_HAS_EU_RNG) -+ talitos_rng_init(sc); -+#endif -+ -+ /* Okay. Stand by. */ -+ spin_unlock_irqrestore(&sc->sc_chnfifolock[sc->sc_num_channels], flags); -+ -+ return; -+} -+ -+/* go through all channels descriptors, notifying OCF what's been done */ -+static void talitos_doneprocessing(struct talitos_softc *sc) -+{ -+ unsigned long flags; -+ int i, j; -+ -+ /* go through descriptors looking for done bits */ -+ for (i = 0; i < sc->sc_num_channels; i++) { -+ spin_lock_irqsave(&sc->sc_chnfifolock[i], flags); -+ for (j = 0; j < sc->sc_chfifo_len; j++) { -+ /* descriptor has done bits set? */ -+ if ((sc->sc_chnfifo[i][j].cf_desc.hdr -+ & TALITOS_HDR_DONE_BITS) -+ == TALITOS_HDR_DONE_BITS) { -+ /* notify ocf */ -+ crypto_done(sc->sc_chnfifo[i][j].cf_crp); -+ /* and tag it available again -+ * -+ * memset to ensure correct descriptor formation by -+ * avoiding inadvertently setting "optional" entries -+ * e.g. not using "optional" dptr2 MD/HMAC processing -+ */ -+ memset(&sc->sc_chnfifo[i][j].cf_desc, -+ 0, sizeof(struct talitos_desc)); -+ } -+ } -+ spin_unlock_irqrestore(&sc->sc_chnfifolock[i], flags); -+ } -+ return; -+} -+ -+static irqreturn_t -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) -+talitos_intr(int irq, void *arg) -+#else -+talitos_intr(int irq, void *arg, struct pt_regs *regs) -+#endif -+{ -+ struct talitos_softc *sc = arg; -+ u_int32_t v, v_hi; -+ -+ /* ack */ -+ v = talitos_read(sc->sc_base_addr + TALITOS_ISR); -+ v_hi = talitos_read(sc->sc_base_addr + TALITOS_ISR_HI); -+ talitos_write(sc->sc_base_addr + TALITOS_ICR, v); -+ talitos_write(sc->sc_base_addr + TALITOS_ICR_HI, v_hi); -+ -+ if (unlikely(v & TALITOS_ISR_ERROR)) { -+ /* Okay, Houston, we've had a problem here. */ -+ printk(KERN_DEBUG "%s: got error interrupt - ISR 0x%08x_%08x\n", -+ device_get_nameunit(sc->sc_cdev), v, v_hi); -+ talitos_errorprocessing(sc); -+ } else -+ if (likely(v & TALITOS_ISR_DONE)) { -+ talitos_doneprocessing(sc); -+ } -+ return IRQ_HANDLED; -+} -+ -+/* -+ * Initialize registers we need to touch only once. -+ */ -+static void -+talitos_init_device(struct talitos_softc *sc) -+{ -+ u_int32_t v; -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ /* init all channels */ -+ for (i = 0; i < sc->sc_num_channels; i++) { -+ v = talitos_read(sc->sc_base_addr + -+ i*TALITOS_CH_OFFSET + TALITOS_CH_CCCR_HI); -+ v |= TALITOS_CH_CCCR_HI_CDWE -+ | TALITOS_CH_CCCR_HI_CDIE; /* invoke interrupt if done */ -+ talitos_write(sc->sc_base_addr + -+ i*TALITOS_CH_OFFSET + TALITOS_CH_CCCR_HI, v); -+ } -+ /* enable all interrupts */ -+ v = talitos_read(sc->sc_base_addr + TALITOS_IMR); -+ v |= TALITOS_IMR_ALL; -+ talitos_write(sc->sc_base_addr + TALITOS_IMR, v); -+ v = talitos_read(sc->sc_base_addr + TALITOS_IMR_HI); -+ v |= TALITOS_IMR_HI_ERRONLY; -+ talitos_write(sc->sc_base_addr + TALITOS_IMR_HI, v); -+ return; -+} -+ -+/* -+ * set the master reset bit on the device. -+ */ -+static void -+talitos_reset_device_master(struct talitos_softc *sc) -+{ -+ u_int32_t v; -+ -+ /* Reset the device by writing 1 to MCR:SWR and waiting 'til cleared */ -+ v = talitos_read(sc->sc_base_addr + TALITOS_MCR); -+ talitos_write(sc->sc_base_addr + TALITOS_MCR, v | TALITOS_MCR_SWR); -+ -+ while (talitos_read(sc->sc_base_addr + TALITOS_MCR) & TALITOS_MCR_SWR) -+ cpu_relax(); -+ -+ return; -+} -+ -+/* -+ * Resets the device. Values in the registers are left as is -+ * from the reset (i.e. initial values are assigned elsewhere). -+ */ -+static void -+talitos_reset_device(struct talitos_softc *sc) -+{ -+ u_int32_t v; -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ /* -+ * Master reset -+ * errata documentation: warning: certain SEC interrupts -+ * are not fully cleared by writing the MCR:SWR bit, -+ * set bit twice to completely reset -+ */ -+ talitos_reset_device_master(sc); /* once */ -+ talitos_reset_device_master(sc); /* and once again */ -+ -+ /* reset all channels */ -+ for (i = 0; i < sc->sc_num_channels; i++) { -+ v = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + -+ TALITOS_CH_CCCR); -+ talitos_write(sc->sc_base_addr + i*TALITOS_CH_OFFSET + -+ TALITOS_CH_CCCR, v | TALITOS_CH_CCCR_RESET); -+ } -+} -+ -+/* Set up the crypto device structure, private data, -+ * and anything else we need before we start */ -+#ifdef CONFIG_PPC_MERGE -+static int talitos_probe(struct of_device *ofdev, const struct of_device_id *match) -+#else -+static int talitos_probe(struct platform_device *pdev) -+#endif -+{ -+ struct talitos_softc *sc = NULL; -+ struct resource *r; -+#ifdef CONFIG_PPC_MERGE -+ struct device *device = &ofdev->dev; -+ struct device_node *np = ofdev->node; -+ const unsigned int *prop; -+ int err; -+ struct resource res; -+#endif -+ static int num_chips = 0; -+ int rc; -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ sc = (struct talitos_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); -+ if (!sc) -+ return -ENOMEM; -+ memset(sc, 0, sizeof(*sc)); -+ -+ softc_device_init(sc, DRV_NAME, num_chips, talitos_methods); -+ -+ sc->sc_irq = -1; -+ sc->sc_cid = -1; -+#ifndef CONFIG_PPC_MERGE -+ sc->sc_dev = pdev; -+#endif -+ sc->sc_num = num_chips++; -+ -+#ifdef CONFIG_PPC_MERGE -+ dev_set_drvdata(device, sc); -+#else -+ platform_set_drvdata(sc->sc_dev, sc); -+#endif -+ -+ /* get the irq line */ -+#ifdef CONFIG_PPC_MERGE -+ err = of_address_to_resource(np, 0, &res); -+ if (err) -+ return -EINVAL; -+ r = &res; -+ -+ sc->sc_irq = irq_of_parse_and_map(np, 0); -+#else -+ /* get a pointer to the register memory */ -+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ -+ sc->sc_irq = platform_get_irq(pdev, 0); -+#endif -+ rc = request_irq(sc->sc_irq, talitos_intr, 0, -+ device_get_nameunit(sc->sc_cdev), sc); -+ if (rc) { -+ printk(KERN_ERR "%s: failed to hook irq %d\n", -+ device_get_nameunit(sc->sc_cdev), sc->sc_irq); -+ sc->sc_irq = -1; -+ goto out; -+ } -+ -+ sc->sc_base_addr = (ocf_iomem_t) ioremap(r->start, (r->end - r->start)); -+ if (!sc->sc_base_addr) { -+ printk(KERN_ERR "%s: failed to ioremap\n", -+ device_get_nameunit(sc->sc_cdev)); -+ goto out; -+ } -+ -+ /* figure out our SEC's properties and capabilities */ -+ sc->sc_chiprev = (u64)talitos_read(sc->sc_base_addr + TALITOS_ID) << 32 -+ | talitos_read(sc->sc_base_addr + TALITOS_ID_HI); -+ DPRINTF("sec id 0x%llx\n", sc->sc_chiprev); -+ -+#ifdef CONFIG_PPC_MERGE -+ /* get SEC properties from device tree, defaulting to SEC 2.0 */ -+ -+ prop = of_get_property(np, "num-channels", NULL); -+ sc->sc_num_channels = prop ? *prop : TALITOS_NCHANNELS_SEC_2_0; -+ -+ prop = of_get_property(np, "channel-fifo-len", NULL); -+ sc->sc_chfifo_len = prop ? *prop : TALITOS_CHFIFOLEN_SEC_2_0; -+ -+ prop = of_get_property(np, "exec-units-mask", NULL); -+ sc->sc_exec_units = prop ? *prop : TALITOS_HAS_EUS_SEC_2_0; -+ -+ prop = of_get_property(np, "descriptor-types-mask", NULL); -+ sc->sc_desc_types = prop ? *prop : TALITOS_HAS_DESCTYPES_SEC_2_0; -+#else -+ /* bulk should go away with openfirmware flat device tree support */ -+ if (sc->sc_chiprev & TALITOS_ID_SEC_2_0) { -+ sc->sc_num_channels = TALITOS_NCHANNELS_SEC_2_0; -+ sc->sc_chfifo_len = TALITOS_CHFIFOLEN_SEC_2_0; -+ sc->sc_exec_units = TALITOS_HAS_EUS_SEC_2_0; -+ sc->sc_desc_types = TALITOS_HAS_DESCTYPES_SEC_2_0; -+ } else { -+ printk(KERN_ERR "%s: failed to id device\n", -+ device_get_nameunit(sc->sc_cdev)); -+ goto out; -+ } -+#endif -+ -+ /* + 1 is for the meta-channel lock used by the channel scheduler */ -+ sc->sc_chnfifolock = (spinlock_t *) kmalloc( -+ (sc->sc_num_channels + 1) * sizeof(spinlock_t), GFP_KERNEL); -+ if (!sc->sc_chnfifolock) -+ goto out; -+ for (i = 0; i < sc->sc_num_channels + 1; i++) { -+ spin_lock_init(&sc->sc_chnfifolock[i]); -+ } -+ -+ sc->sc_chnlastalg = (int *) kmalloc( -+ sc->sc_num_channels * sizeof(int), GFP_KERNEL); -+ if (!sc->sc_chnlastalg) -+ goto out; -+ memset(sc->sc_chnlastalg, 0, sc->sc_num_channels * sizeof(int)); -+ -+ sc->sc_chnfifo = (struct desc_cryptop_pair **) kmalloc( -+ sc->sc_num_channels * sizeof(struct desc_cryptop_pair *), -+ GFP_KERNEL); -+ if (!sc->sc_chnfifo) -+ goto out; -+ for (i = 0; i < sc->sc_num_channels; i++) { -+ sc->sc_chnfifo[i] = (struct desc_cryptop_pair *) kmalloc( -+ sc->sc_chfifo_len * sizeof(struct desc_cryptop_pair), -+ GFP_KERNEL); -+ if (!sc->sc_chnfifo[i]) -+ goto out; -+ memset(sc->sc_chnfifo[i], 0, -+ sc->sc_chfifo_len * sizeof(struct desc_cryptop_pair)); -+ } -+ -+ /* reset and initialize the SEC h/w device */ -+ talitos_reset_device(sc); -+ talitos_init_device(sc); -+ -+ sc->sc_cid = crypto_get_driverid(softc_get_device(sc),CRYPTOCAP_F_HARDWARE); -+ if (sc->sc_cid < 0) { -+ printk(KERN_ERR "%s: could not get crypto driver id\n", -+ device_get_nameunit(sc->sc_cdev)); -+ goto out; -+ } -+ -+ /* register algorithms with the framework */ -+ printk("%s:", device_get_nameunit(sc->sc_cdev)); -+ -+ if (sc->sc_exec_units & TALITOS_HAS_EU_RNG) { -+ printk(" rng"); -+#ifdef CONFIG_OCF_RANDOMHARVEST -+ talitos_rng_init(sc); -+ crypto_rregister(sc->sc_cid, talitos_read_random, sc); -+#endif -+ } -+ if (sc->sc_exec_units & TALITOS_HAS_EU_DEU) { -+ printk(" des/3des"); -+ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); -+ } -+ if (sc->sc_exec_units & TALITOS_HAS_EU_AESU) { -+ printk(" aes"); -+ crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); -+ } -+ if (sc->sc_exec_units & TALITOS_HAS_EU_MDEU) { -+ printk(" md5"); -+ crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0); -+ /* HMAC support only with IPsec for now */ -+ crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); -+ printk(" sha1"); -+ crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0); -+ /* HMAC support only with IPsec for now */ -+ crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); -+ } -+ printk("\n"); -+ return 0; -+ -+out: -+#ifndef CONFIG_PPC_MERGE -+ talitos_remove(pdev); -+#endif -+ return -ENOMEM; -+} -+ -+#ifdef CONFIG_PPC_MERGE -+static int talitos_remove(struct of_device *ofdev) -+#else -+static int talitos_remove(struct platform_device *pdev) -+#endif -+{ -+#ifdef CONFIG_PPC_MERGE -+ struct talitos_softc *sc = dev_get_drvdata(&ofdev->dev); -+#else -+ struct talitos_softc *sc = platform_get_drvdata(pdev); -+#endif -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ if (sc->sc_cid >= 0) -+ crypto_unregister_all(sc->sc_cid); -+ if (sc->sc_chnfifo) { -+ for (i = 0; i < sc->sc_num_channels; i++) -+ if (sc->sc_chnfifo[i]) -+ kfree(sc->sc_chnfifo[i]); -+ kfree(sc->sc_chnfifo); -+ } -+ if (sc->sc_chnlastalg) -+ kfree(sc->sc_chnlastalg); -+ if (sc->sc_chnfifolock) -+ kfree(sc->sc_chnfifolock); -+ if (sc->sc_irq != -1) -+ free_irq(sc->sc_irq, sc); -+ if (sc->sc_base_addr) -+ iounmap((void *) sc->sc_base_addr); -+ kfree(sc); -+ return 0; -+} -+ -+#ifdef CONFIG_PPC_MERGE -+static struct of_device_id talitos_match[] = { -+ { -+ .type = "crypto", -+ .compatible = "talitos", -+ }, -+ {}, -+}; -+ -+MODULE_DEVICE_TABLE(of, talitos_match); -+ -+static struct of_platform_driver talitos_driver = { -+ .name = DRV_NAME, -+ .match_table = talitos_match, -+ .probe = talitos_probe, -+ .remove = talitos_remove, -+}; -+ -+static int __init talitos_init(void) -+{ -+ return of_register_platform_driver(&talitos_driver); -+} -+ -+static void __exit talitos_exit(void) -+{ -+ of_unregister_platform_driver(&talitos_driver); -+} -+#else -+/* Structure for a platform device driver */ -+static struct platform_driver talitos_driver = { -+ .probe = talitos_probe, -+ .remove = talitos_remove, -+ .driver = { -+ .name = "fsl-sec2", -+ } -+}; -+ -+static int __init talitos_init(void) -+{ -+ return platform_driver_register(&talitos_driver); -+} -+ -+static void __exit talitos_exit(void) -+{ -+ platform_driver_unregister(&talitos_driver); -+} -+#endif -+ -+module_init(talitos_init); -+module_exit(talitos_exit); -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_AUTHOR("kim.phillips@freescale.com"); -+MODULE_DESCRIPTION("OCF driver for Freescale SEC (talitos)"); -diff -Nur linux-3.0.4.orig/crypto/ocf/talitos/talitos_dev.h linux-3.0.4/crypto/ocf/talitos/talitos_dev.h ---- linux-3.0.4.orig/crypto/ocf/talitos/talitos_dev.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/talitos/talitos_dev.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,277 @@ -+/* -+ * Freescale SEC (talitos) device dependent data structures -+ * -+ * Copyright (c) 2006 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ */ -+ -+/* device ID register values */ -+#define TALITOS_ID_SEC_2_0 0x40 -+#define TALITOS_ID_SEC_2_1 0x40 /* cross ref with IP block revision reg */ -+ -+/* -+ * following num_channels, channel-fifo-depth, exec-unit-mask, and -+ * descriptor-types-mask are for forward-compatibility with openfirmware -+ * flat device trees -+ */ -+ -+/* -+ * num_channels : the number of channels available in each SEC version. -+ */ -+ -+/* n.b. this driver requires these values be a power of 2 */ -+#define TALITOS_NCHANNELS_SEC_1_0 4 -+#define TALITOS_NCHANNELS_SEC_1_2 1 -+#define TALITOS_NCHANNELS_SEC_2_0 4 -+#define TALITOS_NCHANNELS_SEC_2_01 4 -+#define TALITOS_NCHANNELS_SEC_2_1 4 -+#define TALITOS_NCHANNELS_SEC_2_4 4 -+ -+/* -+ * channel-fifo-depth : The number of descriptor -+ * pointers a channel fetch fifo can hold. -+ */ -+#define TALITOS_CHFIFOLEN_SEC_1_0 1 -+#define TALITOS_CHFIFOLEN_SEC_1_2 1 -+#define TALITOS_CHFIFOLEN_SEC_2_0 24 -+#define TALITOS_CHFIFOLEN_SEC_2_01 24 -+#define TALITOS_CHFIFOLEN_SEC_2_1 24 -+#define TALITOS_CHFIFOLEN_SEC_2_4 24 -+ -+/* -+ * exec-unit-mask : The bitmask representing what Execution Units (EUs) -+ * are available. EU information should be encoded following the SEC's -+ * EU_SEL0 bitfield documentation, i.e. as follows: -+ * -+ * bit 31 = set if SEC permits no-EU selection (should be always set) -+ * bit 30 = set if SEC has the ARC4 EU (AFEU) -+ * bit 29 = set if SEC has the des/3des EU (DEU) -+ * bit 28 = set if SEC has the message digest EU (MDEU) -+ * bit 27 = set if SEC has the random number generator EU (RNG) -+ * bit 26 = set if SEC has the public key EU (PKEU) -+ * bit 25 = set if SEC has the aes EU (AESU) -+ * bit 24 = set if SEC has the Kasumi EU (KEU) -+ * -+ */ -+#define TALITOS_HAS_EU_NONE (1<<0) -+#define TALITOS_HAS_EU_AFEU (1<<1) -+#define TALITOS_HAS_EU_DEU (1<<2) -+#define TALITOS_HAS_EU_MDEU (1<<3) -+#define TALITOS_HAS_EU_RNG (1<<4) -+#define TALITOS_HAS_EU_PKEU (1<<5) -+#define TALITOS_HAS_EU_AESU (1<<6) -+#define TALITOS_HAS_EU_KEU (1<<7) -+ -+/* the corresponding masks for each SEC version */ -+#define TALITOS_HAS_EUS_SEC_1_0 0x7f -+#define TALITOS_HAS_EUS_SEC_1_2 0x4d -+#define TALITOS_HAS_EUS_SEC_2_0 0x7f -+#define TALITOS_HAS_EUS_SEC_2_01 0x7f -+#define TALITOS_HAS_EUS_SEC_2_1 0xff -+#define TALITOS_HAS_EUS_SEC_2_4 0x7f -+ -+/* -+ * descriptor-types-mask : The bitmask representing what descriptors -+ * are available. Descriptor type information should be encoded -+ * following the SEC's Descriptor Header Dword DESC_TYPE field -+ * documentation, i.e. as follows: -+ * -+ * bit 0 = set if SEC supports the aesu_ctr_nonsnoop desc. type -+ * bit 1 = set if SEC supports the ipsec_esp descriptor type -+ * bit 2 = set if SEC supports the common_nonsnoop desc. type -+ * bit 3 = set if SEC supports the 802.11i AES ccmp desc. type -+ * bit 4 = set if SEC supports the hmac_snoop_no_afeu desc. type -+ * bit 5 = set if SEC supports the srtp descriptor type -+ * bit 6 = set if SEC supports the non_hmac_snoop_no_afeu desc.type -+ * bit 7 = set if SEC supports the pkeu_assemble descriptor type -+ * bit 8 = set if SEC supports the aesu_key_expand_output desc.type -+ * bit 9 = set if SEC supports the pkeu_ptmul descriptor type -+ * bit 10 = set if SEC supports the common_nonsnoop_afeu desc. type -+ * bit 11 = set if SEC supports the pkeu_ptadd_dbl descriptor type -+ * -+ * ..and so on and so forth. -+ */ -+#define TALITOS_HAS_DT_AESU_CTR_NONSNOOP (1<<0) -+#define TALITOS_HAS_DT_IPSEC_ESP (1<<1) -+#define TALITOS_HAS_DT_COMMON_NONSNOOP (1<<2) -+ -+/* the corresponding masks for each SEC version */ -+#define TALITOS_HAS_DESCTYPES_SEC_2_0 0x01010ebf -+#define TALITOS_HAS_DESCTYPES_SEC_2_1 0x012b0ebf -+ -+/* -+ * a TALITOS_xxx_HI address points to the low data bits (32-63) of the register -+ */ -+ -+/* global register offset addresses */ -+#define TALITOS_ID 0x1020 -+#define TALITOS_ID_HI 0x1024 -+#define TALITOS_MCR 0x1030 /* master control register */ -+#define TALITOS_MCR_HI 0x1038 /* master control register */ -+#define TALITOS_MCR_SWR 0x1 -+#define TALITOS_IMR 0x1008 /* interrupt mask register */ -+#define TALITOS_IMR_ALL 0x00010fff /* enable all interrupts mask */ -+#define TALITOS_IMR_ERRONLY 0x00010aaa /* enable error interrupts */ -+#define TALITOS_IMR_HI 0x100C /* interrupt mask register */ -+#define TALITOS_IMR_HI_ALL 0x00323333 /* enable all interrupts mask */ -+#define TALITOS_IMR_HI_ERRONLY 0x00222222 /* enable error interrupts */ -+#define TALITOS_ISR 0x1010 /* interrupt status register */ -+#define TALITOS_ISR_ERROR 0x00010faa /* errors mask */ -+#define TALITOS_ISR_DONE 0x00000055 /* channel(s) done mask */ -+#define TALITOS_ISR_HI 0x1014 /* interrupt status register */ -+#define TALITOS_ICR 0x1018 /* interrupt clear register */ -+#define TALITOS_ICR_HI 0x101C /* interrupt clear register */ -+ -+/* channel register address stride */ -+#define TALITOS_CH_OFFSET 0x100 -+ -+/* channel register offset addresses and bits */ -+#define TALITOS_CH_CCCR 0x1108 /* Crypto-Channel Config Register */ -+#define TALITOS_CH_CCCR_RESET 0x1 /* Channel Reset bit */ -+#define TALITOS_CH_CCCR_HI 0x110c /* Crypto-Channel Config Register */ -+#define TALITOS_CH_CCCR_HI_CDWE 0x10 /* Channel done writeback enable bit */ -+#define TALITOS_CH_CCCR_HI_NT 0x4 /* Notification type bit */ -+#define TALITOS_CH_CCCR_HI_CDIE 0x2 /* Channel Done Interrupt Enable bit */ -+#define TALITOS_CH_CCPSR 0x1110 /* Crypto-Channel Pointer Status Reg */ -+#define TALITOS_CH_CCPSR_HI 0x1114 /* Crypto-Channel Pointer Status Reg */ -+#define TALITOS_CH_FF 0x1148 /* Fetch FIFO */ -+#define TALITOS_CH_FF_HI 0x114c /* Fetch FIFO's FETCH_ADRS */ -+#define TALITOS_CH_CDPR 0x1140 /* Crypto-Channel Pointer Status Reg */ -+#define TALITOS_CH_CDPR_HI 0x1144 /* Crypto-Channel Pointer Status Reg */ -+#define TALITOS_CH_DESCBUF 0x1180 /* (thru 11bf) Crypto-Channel -+ * Descriptor Buffer (debug) */ -+ -+/* execution unit register offset addresses and bits */ -+#define TALITOS_DEUSR 0x2028 /* DEU status register */ -+#define TALITOS_DEUSR_HI 0x202c /* DEU status register */ -+#define TALITOS_DEUISR 0x2030 /* DEU interrupt status register */ -+#define TALITOS_DEUISR_HI 0x2034 /* DEU interrupt status register */ -+#define TALITOS_DEUICR 0x2038 /* DEU interrupt control register */ -+#define TALITOS_DEUICR_HI 0x203c /* DEU interrupt control register */ -+#define TALITOS_AESUISR 0x4030 /* AESU interrupt status register */ -+#define TALITOS_AESUISR_HI 0x4034 /* AESU interrupt status register */ -+#define TALITOS_AESUICR 0x4038 /* AESU interrupt control register */ -+#define TALITOS_AESUICR_HI 0x403c /* AESU interrupt control register */ -+#define TALITOS_MDEUISR 0x6030 /* MDEU interrupt status register */ -+#define TALITOS_MDEUISR_HI 0x6034 /* MDEU interrupt status register */ -+#define TALITOS_RNGSR 0xa028 /* RNG status register */ -+#define TALITOS_RNGSR_HI 0xa02c /* RNG status register */ -+#define TALITOS_RNGSR_HI_RD 0x1 /* RNG Reset done */ -+#define TALITOS_RNGSR_HI_OFL 0xff0000/* number of dwords in RNG output FIFO*/ -+#define TALITOS_RNGDSR 0xa010 /* RNG data size register */ -+#define TALITOS_RNGDSR_HI 0xa014 /* RNG data size register */ -+#define TALITOS_RNG_FIFO 0xa800 /* RNG FIFO - pool of random numbers */ -+#define TALITOS_RNGISR 0xa030 /* RNG Interrupt status register */ -+#define TALITOS_RNGISR_HI 0xa034 /* RNG Interrupt status register */ -+#define TALITOS_RNGRCR 0xa018 /* RNG Reset control register */ -+#define TALITOS_RNGRCR_HI 0xa01c /* RNG Reset control register */ -+#define TALITOS_RNGRCR_HI_SR 0x1 /* RNG RNGRCR:Software Reset */ -+ -+/* descriptor pointer entry */ -+struct talitos_desc_ptr { -+ u16 len; /* length */ -+ u8 extent; /* jump (to s/g link table) and extent */ -+ u8 res; /* reserved */ -+ u32 ptr; /* pointer */ -+}; -+ -+/* descriptor */ -+struct talitos_desc { -+ u32 hdr; /* header */ -+ u32 res; /* reserved */ -+ struct talitos_desc_ptr ptr[7]; /* ptr/len pair array */ -+}; -+ -+/* talitos descriptor header (hdr) bits */ -+ -+/* primary execution unit select */ -+#define TALITOS_SEL0_AFEU 0x10000000 -+#define TALITOS_SEL0_DEU 0x20000000 -+#define TALITOS_SEL0_MDEU 0x30000000 -+#define TALITOS_SEL0_RNG 0x40000000 -+#define TALITOS_SEL0_PKEU 0x50000000 -+#define TALITOS_SEL0_AESU 0x60000000 -+ -+/* primary execution unit mode (MODE0) and derivatives */ -+#define TALITOS_MODE0_AESU_CBC 0x00200000 -+#define TALITOS_MODE0_AESU_ENC 0x00100000 -+#define TALITOS_MODE0_DEU_CBC 0x00400000 -+#define TALITOS_MODE0_DEU_3DES 0x00200000 -+#define TALITOS_MODE0_DEU_ENC 0x00100000 -+#define TALITOS_MODE0_MDEU_INIT 0x01000000 /* init starting regs */ -+#define TALITOS_MODE0_MDEU_HMAC 0x00800000 -+#define TALITOS_MODE0_MDEU_PAD 0x00400000 /* PD */ -+#define TALITOS_MODE0_MDEU_MD5 0x00200000 -+#define TALITOS_MODE0_MDEU_SHA256 0x00100000 -+#define TALITOS_MODE0_MDEU_SHA1 0x00000000 /* SHA-160 */ -+#define TALITOS_MODE0_MDEU_MD5_HMAC \ -+ (TALITOS_MODE0_MDEU_MD5 | TALITOS_MODE0_MDEU_HMAC) -+#define TALITOS_MODE0_MDEU_SHA256_HMAC \ -+ (TALITOS_MODE0_MDEU_SHA256 | TALITOS_MODE0_MDEU_HMAC) -+#define TALITOS_MODE0_MDEU_SHA1_HMAC \ -+ (TALITOS_MODE0_MDEU_SHA1 | TALITOS_MODE0_MDEU_HMAC) -+ -+/* secondary execution unit select (SEL1) */ -+/* it's MDEU or nothing */ -+#define TALITOS_SEL1_MDEU 0x00030000 -+ -+/* secondary execution unit mode (MODE1) and derivatives */ -+#define TALITOS_MODE1_MDEU_INIT 0x00001000 /* init starting regs */ -+#define TALITOS_MODE1_MDEU_HMAC 0x00000800 -+#define TALITOS_MODE1_MDEU_PAD 0x00000400 /* PD */ -+#define TALITOS_MODE1_MDEU_MD5 0x00000200 -+#define TALITOS_MODE1_MDEU_SHA256 0x00000100 -+#define TALITOS_MODE1_MDEU_SHA1 0x00000000 /* SHA-160 */ -+#define TALITOS_MODE1_MDEU_MD5_HMAC \ -+ (TALITOS_MODE1_MDEU_MD5 | TALITOS_MODE1_MDEU_HMAC) -+#define TALITOS_MODE1_MDEU_SHA256_HMAC \ -+ (TALITOS_MODE1_MDEU_SHA256 | TALITOS_MODE1_MDEU_HMAC) -+#define TALITOS_MODE1_MDEU_SHA1_HMAC \ -+ (TALITOS_MODE1_MDEU_SHA1 | TALITOS_MODE1_MDEU_HMAC) -+ -+/* direction of overall data flow (DIR) */ -+#define TALITOS_DIR_OUTBOUND 0x00000000 -+#define TALITOS_DIR_INBOUND 0x00000002 -+ -+/* done notification (DN) */ -+#define TALITOS_DONE_NOTIFY 0x00000001 -+ -+/* descriptor types */ -+/* odd numbers here are valid on SEC2 and greater only (e.g. ipsec_esp) */ -+#define TD_TYPE_AESU_CTR_NONSNOOP (0 << 3) -+#define TD_TYPE_IPSEC_ESP (1 << 3) -+#define TD_TYPE_COMMON_NONSNOOP_NO_AFEU (2 << 3) -+#define TD_TYPE_HMAC_SNOOP_NO_AFEU (4 << 3) -+ -+#define TALITOS_HDR_DONE_BITS 0xff000000 -+ -+#define DPRINTF(a...) do { \ -+ if (debug) { \ -+ printk("%s: ", sc ? \ -+ device_get_nameunit(sc->sc_cdev) : "talitos"); \ -+ printk(a); \ -+ } \ -+ } while (0) -diff -Nur linux-3.0.4.orig/crypto/ocf/talitos/talitos_soft.h linux-3.0.4/crypto/ocf/talitos/talitos_soft.h ---- linux-3.0.4.orig/crypto/ocf/talitos/talitos_soft.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/talitos/talitos_soft.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,76 @@ -+/* -+ * Freescale SEC data structures for integration with ocf-linux -+ * -+ * Copyright (c) 2006 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/* -+ * paired descriptor and associated crypto operation -+ */ -+struct desc_cryptop_pair { -+ struct talitos_desc cf_desc; /* descriptor ptr */ -+ struct cryptop *cf_crp; /* cryptop ptr */ -+}; -+ -+/* -+ * Holds data specific to a single talitos device. -+ */ -+struct talitos_softc { -+ softc_device_decl sc_cdev; -+ struct platform_device *sc_dev; /* device backpointer */ -+ ocf_iomem_t sc_base_addr; -+ int sc_irq; -+ int sc_num; /* if we have multiple chips */ -+ int32_t sc_cid; /* crypto tag */ -+ u64 sc_chiprev; /* major/minor chip revision */ -+ int sc_nsessions; -+ struct talitos_session *sc_sessions; -+ int sc_num_channels;/* number of crypto channels */ -+ int sc_chfifo_len; /* channel fetch fifo len */ -+ int sc_exec_units; /* execution units mask */ -+ int sc_desc_types; /* descriptor types mask */ -+ /* -+ * mutual exclusion for intra-channel resources, e.g. fetch fifos -+ * the last entry is a meta-channel lock used by the channel scheduler -+ */ -+ spinlock_t *sc_chnfifolock; -+ /* sc_chnlastalgo contains last algorithm for that channel */ -+ int *sc_chnlastalg; -+ /* sc_chnfifo holds pending descriptor--crypto operation pairs */ -+ struct desc_cryptop_pair **sc_chnfifo; -+}; -+ -+struct talitos_session { -+ u_int32_t ses_used; -+ u_int32_t ses_klen; /* key length in bits */ -+ u_int32_t ses_key[8]; /* DES/3DES/AES key */ -+ u_int32_t ses_hmac[5]; /* hmac inner state */ -+ u_int32_t ses_hmac_len; /* hmac length */ -+ u_int32_t ses_mlen; /* desired hash result len (12=ipsec or 16) */ -+}; -+ -+#define TALITOS_SESSION(sid) ((sid) & 0x0fffffff) -+#define TALITOS_SID(crd, sesn) (((crd) << 28) | ((sesn) & 0x0fffffff)) -diff -Nur linux-3.0.4.orig/crypto/ocf/ubsec_ssb/Makefile linux-3.0.4/crypto/ocf/ubsec_ssb/Makefile ---- linux-3.0.4.orig/crypto/ocf/ubsec_ssb/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/ubsec_ssb/Makefile 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,12 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+obj-$(CONFIG_OCF_UBSEC_SSB) += ubsec_ssb.o -+ -+obj ?= . -+EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/ubsec_ssb/bsdqueue.h linux-3.0.4/crypto/ocf/ubsec_ssb/bsdqueue.h ---- linux-3.0.4.orig/crypto/ocf/ubsec_ssb/bsdqueue.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/ubsec_ssb/bsdqueue.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,527 @@ -+/* $OpenBSD: queue.h,v 1.32 2007/04/30 18:42:34 pedro Exp $ */ -+/* $NetBSD: queue.h,v 1.11 1996/05/16 05:17:14 mycroft Exp $ */ -+ -+/* -+ * Copyright (c) 1991, 1993 -+ * The Regents of the University of California. All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. Neither the name of the University nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ * -+ * @(#)queue.h 8.5 (Berkeley) 8/20/94 -+ */ -+ -+#ifndef _BSD_SYS_QUEUE_H_ -+#define _BSD_SYS_QUEUE_H_ -+ -+/* -+ * This file defines five types of data structures: singly-linked lists, -+ * lists, simple queues, tail queues, and circular queues. -+ * -+ * -+ * A singly-linked list is headed by a single forward pointer. The elements -+ * are singly linked for minimum space and pointer manipulation overhead at -+ * the expense of O(n) removal for arbitrary elements. New elements can be -+ * added to the list after an existing element or at the head of the list. -+ * Elements being removed from the head of the list should use the explicit -+ * macro for this purpose for optimum efficiency. A singly-linked list may -+ * only be traversed in the forward direction. Singly-linked lists are ideal -+ * for applications with large datasets and few or no removals or for -+ * implementing a LIFO queue. -+ * -+ * A list is headed by a single forward pointer (or an array of forward -+ * pointers for a hash table header). The elements are doubly linked -+ * so that an arbitrary element can be removed without a need to -+ * traverse the list. New elements can be added to the list before -+ * or after an existing element or at the head of the list. A list -+ * may only be traversed in the forward direction. -+ * -+ * A simple queue is headed by a pair of pointers, one the head of the -+ * list and the other to the tail of the list. The elements are singly -+ * linked to save space, so elements can only be removed from the -+ * head of the list. New elements can be added to the list before or after -+ * an existing element, at the head of the list, or at the end of the -+ * list. A simple queue may only be traversed in the forward direction. -+ * -+ * A tail queue is headed by a pair of pointers, one to the head of the -+ * list and the other to the tail of the list. The elements are doubly -+ * linked so that an arbitrary element can be removed without a need to -+ * traverse the list. New elements can be added to the list before or -+ * after an existing element, at the head of the list, or at the end of -+ * the list. A tail queue may be traversed in either direction. -+ * -+ * A circle queue is headed by a pair of pointers, one to the head of the -+ * list and the other to the tail of the list. The elements are doubly -+ * linked so that an arbitrary element can be removed without a need to -+ * traverse the list. New elements can be added to the list before or after -+ * an existing element, at the head of the list, or at the end of the list. -+ * A circle queue may be traversed in either direction, but has a more -+ * complex end of list detection. -+ * -+ * For details on the use of these macros, see the queue(3) manual page. -+ */ -+ -+#if defined(QUEUE_MACRO_DEBUG) || (defined(_KERNEL) && defined(DIAGNOSTIC)) -+#define _Q_INVALIDATE(a) (a) = ((void *)-1) -+#else -+#define _Q_INVALIDATE(a) -+#endif -+ -+/* -+ * Singly-linked List definitions. -+ */ -+#define BSD_SLIST_HEAD(name, type) \ -+struct name { \ -+ struct type *slh_first; /* first element */ \ -+} -+ -+#define BSD_SLIST_HEAD_INITIALIZER(head) \ -+ { NULL } -+ -+#define BSD_SLIST_ENTRY(type) \ -+struct { \ -+ struct type *sle_next; /* next element */ \ -+} -+ -+/* -+ * Singly-linked List access methods. -+ */ -+#define BSD_SLIST_FIRST(head) ((head)->slh_first) -+#define BSD_SLIST_END(head) NULL -+#define BSD_SLIST_EMPTY(head) (BSD_SLIST_FIRST(head) == BSD_SLIST_END(head)) -+#define BSD_SLIST_NEXT(elm, field) ((elm)->field.sle_next) -+ -+#define BSD_SLIST_FOREACH(var, head, field) \ -+ for((var) = BSD_SLIST_FIRST(head); \ -+ (var) != BSD_SLIST_END(head); \ -+ (var) = BSD_SLIST_NEXT(var, field)) -+ -+#define BSD_SLIST_FOREACH_PREVPTR(var, varp, head, field) \ -+ for ((varp) = &BSD_SLIST_FIRST((head)); \ -+ ((var) = *(varp)) != BSD_SLIST_END(head); \ -+ (varp) = &BSD_SLIST_NEXT((var), field)) -+ -+/* -+ * Singly-linked List functions. -+ */ -+#define BSD_SLIST_INIT(head) { \ -+ BSD_SLIST_FIRST(head) = BSD_SLIST_END(head); \ -+} -+ -+#define BSD_SLIST_INSERT_AFTER(slistelm, elm, field) do { \ -+ (elm)->field.sle_next = (slistelm)->field.sle_next; \ -+ (slistelm)->field.sle_next = (elm); \ -+} while (0) -+ -+#define BSD_SLIST_INSERT_HEAD(head, elm, field) do { \ -+ (elm)->field.sle_next = (head)->slh_first; \ -+ (head)->slh_first = (elm); \ -+} while (0) -+ -+#define BSD_SLIST_REMOVE_NEXT(head, elm, field) do { \ -+ (elm)->field.sle_next = (elm)->field.sle_next->field.sle_next; \ -+} while (0) -+ -+#define BSD_SLIST_REMOVE_HEAD(head, field) do { \ -+ (head)->slh_first = (head)->slh_first->field.sle_next; \ -+} while (0) -+ -+#define BSD_SLIST_REMOVE(head, elm, type, field) do { \ -+ if ((head)->slh_first == (elm)) { \ -+ BSD_SLIST_REMOVE_HEAD((head), field); \ -+ } else { \ -+ struct type *curelm = (head)->slh_first; \ -+ \ -+ while (curelm->field.sle_next != (elm)) \ -+ curelm = curelm->field.sle_next; \ -+ curelm->field.sle_next = \ -+ curelm->field.sle_next->field.sle_next; \ -+ _Q_INVALIDATE((elm)->field.sle_next); \ -+ } \ -+} while (0) -+ -+/* -+ * List definitions. -+ */ -+#define BSD_LIST_HEAD(name, type) \ -+struct name { \ -+ struct type *lh_first; /* first element */ \ -+} -+ -+#define BSD_LIST_HEAD_INITIALIZER(head) \ -+ { NULL } -+ -+#define BSD_LIST_ENTRY(type) \ -+struct { \ -+ struct type *le_next; /* next element */ \ -+ struct type **le_prev; /* address of previous next element */ \ -+} -+ -+/* -+ * List access methods -+ */ -+#define BSD_LIST_FIRST(head) ((head)->lh_first) -+#define BSD_LIST_END(head) NULL -+#define BSD_LIST_EMPTY(head) (BSD_LIST_FIRST(head) == BSD_LIST_END(head)) -+#define BSD_LIST_NEXT(elm, field) ((elm)->field.le_next) -+ -+#define BSD_LIST_FOREACH(var, head, field) \ -+ for((var) = BSD_LIST_FIRST(head); \ -+ (var)!= BSD_LIST_END(head); \ -+ (var) = BSD_LIST_NEXT(var, field)) -+ -+/* -+ * List functions. -+ */ -+#define BSD_LIST_INIT(head) do { \ -+ BSD_LIST_FIRST(head) = BSD_LIST_END(head); \ -+} while (0) -+ -+#define BSD_LIST_INSERT_AFTER(listelm, elm, field) do { \ -+ if (((elm)->field.le_next = (listelm)->field.le_next) != NULL) \ -+ (listelm)->field.le_next->field.le_prev = \ -+ &(elm)->field.le_next; \ -+ (listelm)->field.le_next = (elm); \ -+ (elm)->field.le_prev = &(listelm)->field.le_next; \ -+} while (0) -+ -+#define BSD_LIST_INSERT_BEFORE(listelm, elm, field) do { \ -+ (elm)->field.le_prev = (listelm)->field.le_prev; \ -+ (elm)->field.le_next = (listelm); \ -+ *(listelm)->field.le_prev = (elm); \ -+ (listelm)->field.le_prev = &(elm)->field.le_next; \ -+} while (0) -+ -+#define BSD_LIST_INSERT_HEAD(head, elm, field) do { \ -+ if (((elm)->field.le_next = (head)->lh_first) != NULL) \ -+ (head)->lh_first->field.le_prev = &(elm)->field.le_next;\ -+ (head)->lh_first = (elm); \ -+ (elm)->field.le_prev = &(head)->lh_first; \ -+} while (0) -+ -+#define BSD_LIST_REMOVE(elm, field) do { \ -+ if ((elm)->field.le_next != NULL) \ -+ (elm)->field.le_next->field.le_prev = \ -+ (elm)->field.le_prev; \ -+ *(elm)->field.le_prev = (elm)->field.le_next; \ -+ _Q_INVALIDATE((elm)->field.le_prev); \ -+ _Q_INVALIDATE((elm)->field.le_next); \ -+} while (0) -+ -+#define BSD_LIST_REPLACE(elm, elm2, field) do { \ -+ if (((elm2)->field.le_next = (elm)->field.le_next) != NULL) \ -+ (elm2)->field.le_next->field.le_prev = \ -+ &(elm2)->field.le_next; \ -+ (elm2)->field.le_prev = (elm)->field.le_prev; \ -+ *(elm2)->field.le_prev = (elm2); \ -+ _Q_INVALIDATE((elm)->field.le_prev); \ -+ _Q_INVALIDATE((elm)->field.le_next); \ -+} while (0) -+ -+/* -+ * Simple queue definitions. -+ */ -+#define BSD_SIMPLEQ_HEAD(name, type) \ -+struct name { \ -+ struct type *sqh_first; /* first element */ \ -+ struct type **sqh_last; /* addr of last next element */ \ -+} -+ -+#define BSD_SIMPLEQ_HEAD_INITIALIZER(head) \ -+ { NULL, &(head).sqh_first } -+ -+#define BSD_SIMPLEQ_ENTRY(type) \ -+struct { \ -+ struct type *sqe_next; /* next element */ \ -+} -+ -+/* -+ * Simple queue access methods. -+ */ -+#define BSD_SIMPLEQ_FIRST(head) ((head)->sqh_first) -+#define BSD_SIMPLEQ_END(head) NULL -+#define BSD_SIMPLEQ_EMPTY(head) (BSD_SIMPLEQ_FIRST(head) == BSD_SIMPLEQ_END(head)) -+#define BSD_SIMPLEQ_NEXT(elm, field) ((elm)->field.sqe_next) -+ -+#define BSD_SIMPLEQ_FOREACH(var, head, field) \ -+ for((var) = BSD_SIMPLEQ_FIRST(head); \ -+ (var) != BSD_SIMPLEQ_END(head); \ -+ (var) = BSD_SIMPLEQ_NEXT(var, field)) -+ -+/* -+ * Simple queue functions. -+ */ -+#define BSD_SIMPLEQ_INIT(head) do { \ -+ (head)->sqh_first = NULL; \ -+ (head)->sqh_last = &(head)->sqh_first; \ -+} while (0) -+ -+#define BSD_SIMPLEQ_INSERT_HEAD(head, elm, field) do { \ -+ if (((elm)->field.sqe_next = (head)->sqh_first) == NULL) \ -+ (head)->sqh_last = &(elm)->field.sqe_next; \ -+ (head)->sqh_first = (elm); \ -+} while (0) -+ -+#define BSD_SIMPLEQ_INSERT_TAIL(head, elm, field) do { \ -+ (elm)->field.sqe_next = NULL; \ -+ *(head)->sqh_last = (elm); \ -+ (head)->sqh_last = &(elm)->field.sqe_next; \ -+} while (0) -+ -+#define BSD_SIMPLEQ_INSERT_AFTER(head, listelm, elm, field) do { \ -+ if (((elm)->field.sqe_next = (listelm)->field.sqe_next) == NULL)\ -+ (head)->sqh_last = &(elm)->field.sqe_next; \ -+ (listelm)->field.sqe_next = (elm); \ -+} while (0) -+ -+#define BSD_SIMPLEQ_REMOVE_HEAD(head, field) do { \ -+ if (((head)->sqh_first = (head)->sqh_first->field.sqe_next) == NULL) \ -+ (head)->sqh_last = &(head)->sqh_first; \ -+} while (0) -+ -+/* -+ * Tail queue definitions. -+ */ -+#define BSD_TAILQ_HEAD(name, type) \ -+struct name { \ -+ struct type *tqh_first; /* first element */ \ -+ struct type **tqh_last; /* addr of last next element */ \ -+} -+ -+#define BSD_TAILQ_HEAD_INITIALIZER(head) \ -+ { NULL, &(head).tqh_first } -+ -+#define BSD_TAILQ_ENTRY(type) \ -+struct { \ -+ struct type *tqe_next; /* next element */ \ -+ struct type **tqe_prev; /* address of previous next element */ \ -+} -+ -+/* -+ * tail queue access methods -+ */ -+#define BSD_TAILQ_FIRST(head) ((head)->tqh_first) -+#define BSD_TAILQ_END(head) NULL -+#define BSD_TAILQ_NEXT(elm, field) ((elm)->field.tqe_next) -+#define BSD_TAILQ_LAST(head, headname) \ -+ (*(((struct headname *)((head)->tqh_last))->tqh_last)) -+/* XXX */ -+#define BSD_TAILQ_PREV(elm, headname, field) \ -+ (*(((struct headname *)((elm)->field.tqe_prev))->tqh_last)) -+#define BSD_TAILQ_EMPTY(head) \ -+ (BSD_TAILQ_FIRST(head) == BSD_TAILQ_END(head)) -+ -+#define BSD_TAILQ_FOREACH(var, head, field) \ -+ for((var) = BSD_TAILQ_FIRST(head); \ -+ (var) != BSD_TAILQ_END(head); \ -+ (var) = BSD_TAILQ_NEXT(var, field)) -+ -+#define BSD_TAILQ_FOREACH_REVERSE(var, head, headname, field) \ -+ for((var) = BSD_TAILQ_LAST(head, headname); \ -+ (var) != BSD_TAILQ_END(head); \ -+ (var) = BSD_TAILQ_PREV(var, headname, field)) -+ -+/* -+ * Tail queue functions. -+ */ -+#define BSD_TAILQ_INIT(head) do { \ -+ (head)->tqh_first = NULL; \ -+ (head)->tqh_last = &(head)->tqh_first; \ -+} while (0) -+ -+#define BSD_TAILQ_INSERT_HEAD(head, elm, field) do { \ -+ if (((elm)->field.tqe_next = (head)->tqh_first) != NULL) \ -+ (head)->tqh_first->field.tqe_prev = \ -+ &(elm)->field.tqe_next; \ -+ else \ -+ (head)->tqh_last = &(elm)->field.tqe_next; \ -+ (head)->tqh_first = (elm); \ -+ (elm)->field.tqe_prev = &(head)->tqh_first; \ -+} while (0) -+ -+#define BSD_TAILQ_INSERT_TAIL(head, elm, field) do { \ -+ (elm)->field.tqe_next = NULL; \ -+ (elm)->field.tqe_prev = (head)->tqh_last; \ -+ *(head)->tqh_last = (elm); \ -+ (head)->tqh_last = &(elm)->field.tqe_next; \ -+} while (0) -+ -+#define BSD_TAILQ_INSERT_AFTER(head, listelm, elm, field) do { \ -+ if (((elm)->field.tqe_next = (listelm)->field.tqe_next) != NULL)\ -+ (elm)->field.tqe_next->field.tqe_prev = \ -+ &(elm)->field.tqe_next; \ -+ else \ -+ (head)->tqh_last = &(elm)->field.tqe_next; \ -+ (listelm)->field.tqe_next = (elm); \ -+ (elm)->field.tqe_prev = &(listelm)->field.tqe_next; \ -+} while (0) -+ -+#define BSD_TAILQ_INSERT_BEFORE(listelm, elm, field) do { \ -+ (elm)->field.tqe_prev = (listelm)->field.tqe_prev; \ -+ (elm)->field.tqe_next = (listelm); \ -+ *(listelm)->field.tqe_prev = (elm); \ -+ (listelm)->field.tqe_prev = &(elm)->field.tqe_next; \ -+} while (0) -+ -+#define BSD_TAILQ_REMOVE(head, elm, field) do { \ -+ if (((elm)->field.tqe_next) != NULL) \ -+ (elm)->field.tqe_next->field.tqe_prev = \ -+ (elm)->field.tqe_prev; \ -+ else \ -+ (head)->tqh_last = (elm)->field.tqe_prev; \ -+ *(elm)->field.tqe_prev = (elm)->field.tqe_next; \ -+ _Q_INVALIDATE((elm)->field.tqe_prev); \ -+ _Q_INVALIDATE((elm)->field.tqe_next); \ -+} while (0) -+ -+#define BSD_TAILQ_REPLACE(head, elm, elm2, field) do { \ -+ if (((elm2)->field.tqe_next = (elm)->field.tqe_next) != NULL) \ -+ (elm2)->field.tqe_next->field.tqe_prev = \ -+ &(elm2)->field.tqe_next; \ -+ else \ -+ (head)->tqh_last = &(elm2)->field.tqe_next; \ -+ (elm2)->field.tqe_prev = (elm)->field.tqe_prev; \ -+ *(elm2)->field.tqe_prev = (elm2); \ -+ _Q_INVALIDATE((elm)->field.tqe_prev); \ -+ _Q_INVALIDATE((elm)->field.tqe_next); \ -+} while (0) -+ -+/* -+ * Circular queue definitions. -+ */ -+#define BSD_CIRCLEQ_HEAD(name, type) \ -+struct name { \ -+ struct type *cqh_first; /* first element */ \ -+ struct type *cqh_last; /* last element */ \ -+} -+ -+#define BSD_CIRCLEQ_HEAD_INITIALIZER(head) \ -+ { BSD_CIRCLEQ_END(&head), BSD_CIRCLEQ_END(&head) } -+ -+#define BSD_CIRCLEQ_ENTRY(type) \ -+struct { \ -+ struct type *cqe_next; /* next element */ \ -+ struct type *cqe_prev; /* previous element */ \ -+} -+ -+/* -+ * Circular queue access methods -+ */ -+#define BSD_CIRCLEQ_FIRST(head) ((head)->cqh_first) -+#define BSD_CIRCLEQ_LAST(head) ((head)->cqh_last) -+#define BSD_CIRCLEQ_END(head) ((void *)(head)) -+#define BSD_CIRCLEQ_NEXT(elm, field) ((elm)->field.cqe_next) -+#define BSD_CIRCLEQ_PREV(elm, field) ((elm)->field.cqe_prev) -+#define BSD_CIRCLEQ_EMPTY(head) \ -+ (BSD_CIRCLEQ_FIRST(head) == BSD_CIRCLEQ_END(head)) -+ -+#define BSD_CIRCLEQ_FOREACH(var, head, field) \ -+ for((var) = BSD_CIRCLEQ_FIRST(head); \ -+ (var) != BSD_CIRCLEQ_END(head); \ -+ (var) = BSD_CIRCLEQ_NEXT(var, field)) -+ -+#define BSD_CIRCLEQ_FOREACH_REVERSE(var, head, field) \ -+ for((var) = BSD_CIRCLEQ_LAST(head); \ -+ (var) != BSD_CIRCLEQ_END(head); \ -+ (var) = BSD_CIRCLEQ_PREV(var, field)) -+ -+/* -+ * Circular queue functions. -+ */ -+#define BSD_CIRCLEQ_INIT(head) do { \ -+ (head)->cqh_first = BSD_CIRCLEQ_END(head); \ -+ (head)->cqh_last = BSD_CIRCLEQ_END(head); \ -+} while (0) -+ -+#define BSD_CIRCLEQ_INSERT_AFTER(head, listelm, elm, field) do { \ -+ (elm)->field.cqe_next = (listelm)->field.cqe_next; \ -+ (elm)->field.cqe_prev = (listelm); \ -+ if ((listelm)->field.cqe_next == BSD_CIRCLEQ_END(head)) \ -+ (head)->cqh_last = (elm); \ -+ else \ -+ (listelm)->field.cqe_next->field.cqe_prev = (elm); \ -+ (listelm)->field.cqe_next = (elm); \ -+} while (0) -+ -+#define BSD_CIRCLEQ_INSERT_BEFORE(head, listelm, elm, field) do { \ -+ (elm)->field.cqe_next = (listelm); \ -+ (elm)->field.cqe_prev = (listelm)->field.cqe_prev; \ -+ if ((listelm)->field.cqe_prev == BSD_CIRCLEQ_END(head)) \ -+ (head)->cqh_first = (elm); \ -+ else \ -+ (listelm)->field.cqe_prev->field.cqe_next = (elm); \ -+ (listelm)->field.cqe_prev = (elm); \ -+} while (0) -+ -+#define BSD_CIRCLEQ_INSERT_HEAD(head, elm, field) do { \ -+ (elm)->field.cqe_next = (head)->cqh_first; \ -+ (elm)->field.cqe_prev = BSD_CIRCLEQ_END(head); \ -+ if ((head)->cqh_last == BSD_CIRCLEQ_END(head)) \ -+ (head)->cqh_last = (elm); \ -+ else \ -+ (head)->cqh_first->field.cqe_prev = (elm); \ -+ (head)->cqh_first = (elm); \ -+} while (0) -+ -+#define BSD_CIRCLEQ_INSERT_TAIL(head, elm, field) do { \ -+ (elm)->field.cqe_next = BSD_CIRCLEQ_END(head); \ -+ (elm)->field.cqe_prev = (head)->cqh_last; \ -+ if ((head)->cqh_first == BSD_CIRCLEQ_END(head)) \ -+ (head)->cqh_first = (elm); \ -+ else \ -+ (head)->cqh_last->field.cqe_next = (elm); \ -+ (head)->cqh_last = (elm); \ -+} while (0) -+ -+#define BSD_CIRCLEQ_REMOVE(head, elm, field) do { \ -+ if ((elm)->field.cqe_next == BSD_CIRCLEQ_END(head)) \ -+ (head)->cqh_last = (elm)->field.cqe_prev; \ -+ else \ -+ (elm)->field.cqe_next->field.cqe_prev = \ -+ (elm)->field.cqe_prev; \ -+ if ((elm)->field.cqe_prev == BSD_CIRCLEQ_END(head)) \ -+ (head)->cqh_first = (elm)->field.cqe_next; \ -+ else \ -+ (elm)->field.cqe_prev->field.cqe_next = \ -+ (elm)->field.cqe_next; \ -+ _Q_INVALIDATE((elm)->field.cqe_prev); \ -+ _Q_INVALIDATE((elm)->field.cqe_next); \ -+} while (0) -+ -+#define BSD_CIRCLEQ_REPLACE(head, elm, elm2, field) do { \ -+ if (((elm2)->field.cqe_next = (elm)->field.cqe_next) == \ -+ BSD_CIRCLEQ_END(head)) \ -+ (head).cqh_last = (elm2); \ -+ else \ -+ (elm2)->field.cqe_next->field.cqe_prev = (elm2); \ -+ if (((elm2)->field.cqe_prev = (elm)->field.cqe_prev) == \ -+ BSD_CIRCLEQ_END(head)) \ -+ (head).cqh_first = (elm2); \ -+ else \ -+ (elm2)->field.cqe_prev->field.cqe_next = (elm2); \ -+ _Q_INVALIDATE((elm)->field.cqe_prev); \ -+ _Q_INVALIDATE((elm)->field.cqe_next); \ -+} while (0) -+ -+#endif /* !_BSD_SYS_QUEUE_H_ */ -diff -Nur linux-3.0.4.orig/crypto/ocf/ubsec_ssb/ubsec_ssb.c linux-3.0.4/crypto/ocf/ubsec_ssb/ubsec_ssb.c ---- linux-3.0.4.orig/crypto/ocf/ubsec_ssb/ubsec_ssb.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/ubsec_ssb/ubsec_ssb.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,2220 @@ -+ -+/* -+ * Copyright (c) 2008 Daniel Mueller (daniel@danm.de) -+ * Copyright (c) 2007 David McCullough (david_mccullough@securecomputing.com) -+ * Copyright (c) 2000 Jason L. Wright (jason@thought.net) -+ * Copyright (c) 2000 Theo de Raadt (deraadt@openbsd.org) -+ * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com) -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored in part by the Defense Advanced Research Projects -+ * Agency (DARPA) and Air Force Research Laboratory, Air Force -+ * Materiel Command, USAF, under agreement number F30602-01-2-0537. -+ * -+ */ -+#undef UBSEC_DEBUG -+#undef UBSEC_VERBOSE_DEBUG -+ -+#ifdef UBSEC_VERBOSE_DEBUG -+#define UBSEC_DEBUG -+#endif -+ -+/* -+ * uBsec BCM5365 hardware crypto accelerator -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+/* -+ * BSD queue -+ */ -+//#include "bsdqueue.h" -+ -+/* -+ * OCF -+ */ -+#include -+#include -+ -+#define HMAC_HACK 1 -+ -+#define HMAC_HACK 1 -+#ifdef HMAC_HACK -+#include -+#include -+#include -+#include -+#include -+#endif -+ -+#include "bsdqueue.h" -+#include "ubsecreg.h" -+#include "ubsecvar.h" -+ -+#define DRV_MODULE_NAME "ubsec_ssb" -+#define PFX DRV_MODULE_NAME ": " -+#define DRV_MODULE_VERSION "0.02" -+#define DRV_MODULE_RELDATE "Feb 21, 2009" -+ -+#if 1 -+#define DPRINTF(a...) \ -+ if (debug) \ -+ { \ -+ printk(DRV_MODULE_NAME ": " a); \ -+ } -+#else -+#define DPRINTF(a...) -+#endif -+ -+/* -+ * Prototypes -+ */ -+static irqreturn_t ubsec_ssb_isr(int, void *, struct pt_regs *); -+static int __devinit ubsec_ssb_probe(struct ssb_device *sdev, -+ const struct ssb_device_id *ent); -+static void __devexit ubsec_ssb_remove(struct ssb_device *sdev); -+int ubsec_attach(struct ssb_device *sdev, const struct ssb_device_id *ent, -+ struct device *self); -+static void ubsec_setup_mackey(struct ubsec_session *ses, int algo, -+ caddr_t key, int klen); -+static int dma_map_skb(struct ubsec_softc *sc, -+ struct ubsec_dma_alloc* q_map, struct sk_buff *skb, int *mlen); -+static int dma_map_uio(struct ubsec_softc *sc, -+ struct ubsec_dma_alloc *q_map, struct uio *uio, int *mlen); -+static void dma_unmap(struct ubsec_softc *sc, -+ struct ubsec_dma_alloc *q_map, int mlen); -+static int ubsec_dmamap_aligned(struct ubsec_softc *sc, -+ const struct ubsec_dma_alloc *q_map, int mlen); -+ -+#ifdef UBSEC_DEBUG -+static int proc_read(char *buf, char **start, off_t offset, -+ int size, int *peof, void *data); -+#endif -+ -+void ubsec_reset_board(struct ubsec_softc *); -+void ubsec_init_board(struct ubsec_softc *); -+void ubsec_cleanchip(struct ubsec_softc *); -+void ubsec_totalreset(struct ubsec_softc *); -+int ubsec_free_q(struct ubsec_softc*, struct ubsec_q *); -+ -+static int ubsec_newsession(device_t, u_int32_t *, struct cryptoini *); -+static int ubsec_freesession(device_t, u_int64_t); -+static int ubsec_process(device_t, struct cryptop *, int); -+ -+void ubsec_callback(struct ubsec_softc *, struct ubsec_q *); -+void ubsec_feed(struct ubsec_softc *); -+void ubsec_mcopy(struct sk_buff *, struct sk_buff *, int, int); -+void ubsec_dma_free(struct ubsec_softc *, struct ubsec_dma_alloc *); -+int ubsec_dma_malloc(struct ubsec_softc *, struct ubsec_dma_alloc *, -+ size_t, int); -+ -+/* DEBUG crap... */ -+void ubsec_dump_pb(struct ubsec_pktbuf *); -+void ubsec_dump_mcr(struct ubsec_mcr *); -+ -+#define READ_REG(sc,r) \ -+ ssb_read32((sc)->sdev, (r)); -+#define WRITE_REG(sc,r,val) \ -+ ssb_write32((sc)->sdev, (r), (val)); -+#define READ_REG_SDEV(sdev,r) \ -+ ssb_read32((sdev), (r)); -+#define WRITE_REG_SDEV(sdev,r,val) \ -+ ssb_write32((sdev), (r), (val)); -+ -+#define SWAP32(x) (x) = htole32(ntohl((x))) -+#define HTOLE32(x) (x) = htole32(x) -+ -+#ifdef __LITTLE_ENDIAN -+#define letoh16(x) (x) -+#define letoh32(x) (x) -+#endif -+ -+static int debug; -+module_param(debug, int, 0644); -+MODULE_PARM_DESC(debug, "Enable debug output"); -+ -+#define UBSEC_SSB_MAX_CHIPS 1 -+static struct ubsec_softc *ubsec_chip_idx[UBSEC_SSB_MAX_CHIPS]; -+static struct ubsec_stats ubsecstats; -+ -+#ifdef UBSEC_DEBUG -+static struct proc_dir_entry *procdebug; -+#endif -+ -+static struct ssb_device_id ubsec_ssb_tbl[] = { -+ /* Broadcom BCM5365P IPSec Core */ -+ SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_IPSEC, SSB_ANY_REV), -+ SSB_DEVTABLE_END -+}; -+ -+static struct ssb_driver ubsec_ssb_driver = { -+ .name = DRV_MODULE_NAME, -+ .id_table = ubsec_ssb_tbl, -+ .probe = ubsec_ssb_probe, -+ .remove = __devexit_p(ubsec_ssb_remove), -+ /* -+ .suspend = ubsec_ssb_suspend, -+ .resume = ubsec_ssb_resume -+ */ -+}; -+ -+static device_method_t ubsec_ssb_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, ubsec_newsession), -+ DEVMETHOD(cryptodev_freesession,ubsec_freesession), -+ DEVMETHOD(cryptodev_process, ubsec_process), -+}; -+ -+#ifdef UBSEC_DEBUG -+static int -+proc_read(char *buf, char **start, off_t offset, -+ int size, int *peof, void *data) -+{ -+ int i = 0, byteswritten = 0, ret; -+ unsigned int stat, ctrl; -+#ifdef UBSEC_VERBOSE_DEBUG -+ struct ubsec_q *q; -+ struct ubsec_dma *dmap; -+#endif -+ -+ while ((i < UBSEC_SSB_MAX_CHIPS) && (ubsec_chip_idx[i] != NULL)) -+ { -+ struct ubsec_softc *sc = ubsec_chip_idx[i]; -+ -+ stat = READ_REG(sc, BS_STAT); -+ ctrl = READ_REG(sc, BS_CTRL); -+ ret = snprintf((buf + byteswritten), -+ (size - byteswritten) , -+ "DEV %d, DMASTAT %08x, DMACTRL %08x\n", i, stat, ctrl); -+ -+ byteswritten += ret; -+ -+#ifdef UBSEC_VERBOSE_DEBUG -+ printf("DEV %d, DMASTAT %08x, DMACTRL %08x\n", i, stat, ctrl); -+ -+ /* Dump all queues MCRs */ -+ if (!BSD_SIMPLEQ_EMPTY(&sc->sc_qchip)) { -+ BSD_SIMPLEQ_FOREACH(q, &sc->sc_qchip, q_next) -+ { -+ dmap = q->q_dma; -+ ubsec_dump_mcr(&dmap->d_dma->d_mcr); -+ } -+ } -+#endif -+ -+ i++; -+ } -+ -+ *peof = 1; -+ -+ return byteswritten; -+} -+#endif -+ -+/* -+ * map in a given sk_buff -+ */ -+static int -+dma_map_skb(struct ubsec_softc *sc, struct ubsec_dma_alloc* q_map, struct sk_buff *skb, int *mlen) -+{ -+ int i = 0; -+ dma_addr_t tmp; -+ -+#ifdef UBSEC_DEBUG -+ DPRINTF("%s()\n", __FUNCTION__); -+#endif -+ -+ /* -+ * We support only a limited number of fragments. -+ */ -+ if (unlikely((skb_shinfo(skb)->nr_frags + 1) >= UBS_MAX_SCATTER)) -+ { -+ printk(KERN_ERR "Only %d scatter fragments are supported.\n", UBS_MAX_SCATTER); -+ return (-ENOMEM); -+ } -+ -+#ifdef UBSEC_VERBOSE_DEBUG -+ DPRINTF("%s - map %d 0x%x %d\n", __FUNCTION__, 0, (unsigned int)skb->data, skb_headlen(skb)); -+#endif -+ -+ /* first data package */ -+ tmp = dma_map_single(sc->sc_dv, -+ skb->data, -+ skb_headlen(skb), -+ DMA_BIDIRECTIONAL); -+ -+ q_map[i].dma_paddr = tmp; -+ q_map[i].dma_vaddr = skb->data; -+ q_map[i].dma_size = skb_headlen(skb); -+ -+ if (unlikely(tmp == 0)) -+ { -+ printk(KERN_ERR "Could not map memory region for dma.\n"); -+ return (-EINVAL); -+ } -+ -+#ifdef UBSEC_VERBOSE_DEBUG -+ DPRINTF("%s - map %d done physical addr 0x%x\n", __FUNCTION__, 0, (unsigned int)tmp); -+#endif -+ -+ -+ /* all other data packages */ -+ for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { -+ -+#ifdef UBSEC_VERBOSE_DEBUG -+ DPRINTF("%s - map %d 0x%x %d\n", __FUNCTION__, i + 1, -+ (unsigned int)page_address(skb_shinfo(skb)->frags[i].page) + -+ skb_shinfo(skb)->frags[i].page_offset, skb_shinfo(skb)->frags[i].size); -+#endif -+ -+ tmp = dma_map_single(sc->sc_dv, -+ page_address(skb_shinfo(skb)->frags[i].page) + -+ skb_shinfo(skb)->frags[i].page_offset, -+ skb_shinfo(skb)->frags[i].size, -+ DMA_BIDIRECTIONAL); -+ -+ q_map[i + 1].dma_paddr = tmp; -+ q_map[i + 1].dma_vaddr = (void*)(page_address(skb_shinfo(skb)->frags[i].page) + -+ skb_shinfo(skb)->frags[i].page_offset); -+ q_map[i + 1].dma_size = skb_shinfo(skb)->frags[i].size; -+ -+ if (unlikely(tmp == 0)) -+ { -+ printk(KERN_ERR "Could not map memory region for dma.\n"); -+ return (-EINVAL); -+ } -+ -+#ifdef UBSEC_VERBOSE_DEBUG -+ DPRINTF("%s - map %d done physical addr 0x%x\n", __FUNCTION__, i + 1, (unsigned int)tmp); -+#endif -+ -+ } -+ *mlen = i + 1; -+ -+ return(0); -+} -+ -+/* -+ * map in a given uio buffer -+ */ -+ -+static int -+dma_map_uio(struct ubsec_softc *sc, struct ubsec_dma_alloc *q_map, struct uio *uio, int *mlen) -+{ -+ struct iovec *iov = uio->uio_iov; -+ int n; -+ dma_addr_t tmp; -+ -+#ifdef UBSEC_DEBUG -+ DPRINTF("%s()\n", __FUNCTION__); -+#endif -+ -+ /* -+ * We support only a limited number of fragments. -+ */ -+ if (unlikely(uio->uio_iovcnt >= UBS_MAX_SCATTER)) -+ { -+ printk(KERN_ERR "Only %d scatter fragments are supported.\n", UBS_MAX_SCATTER); -+ return (-ENOMEM); -+ } -+ -+ for (n = 0; n < uio->uio_iovcnt; n++) { -+#ifdef UBSEC_VERBOSE_DEBUG -+ DPRINTF("%s - map %d 0x%x %d\n", __FUNCTION__, n, (unsigned int)iov->iov_base, iov->iov_len); -+#endif -+ tmp = dma_map_single(sc->sc_dv, -+ iov->iov_base, -+ iov->iov_len, -+ DMA_BIDIRECTIONAL); -+ -+ q_map[n].dma_paddr = tmp; -+ q_map[n].dma_vaddr = iov->iov_base; -+ q_map[n].dma_size = iov->iov_len; -+ -+ if (unlikely(tmp == 0)) -+ { -+ printk(KERN_ERR "Could not map memory region for dma.\n"); -+ return (-EINVAL); -+ } -+ -+#ifdef UBSEC_VERBOSE_DEBUG -+ DPRINTF("%s - map %d done physical addr 0x%x\n", __FUNCTION__, n, (unsigned int)tmp); -+#endif -+ -+ iov++; -+ } -+ *mlen = n; -+ -+ return(0); -+} -+ -+static void -+dma_unmap(struct ubsec_softc *sc, struct ubsec_dma_alloc *q_map, int mlen) -+{ -+ int i; -+ -+#ifdef UBSEC_DEBUG -+ DPRINTF("%s()\n", __FUNCTION__); -+#endif -+ -+ for(i = 0; i < mlen; i++) -+ { -+#ifdef UBSEC_VERBOSE_DEBUG -+ DPRINTF("%s - unmap %d 0x%x %d\n", __FUNCTION__, i, (unsigned int)q_map[i].dma_paddr, q_map[i].dma_size); -+#endif -+ dma_unmap_single(sc->sc_dv, -+ q_map[i].dma_paddr, -+ q_map[i].dma_size, -+ DMA_BIDIRECTIONAL); -+ } -+ return; -+} -+ -+/* -+ * Is the operand suitable aligned for direct DMA. Each -+ * segment must be aligned on a 32-bit boundary and all -+ * but the last segment must be a multiple of 4 bytes. -+ */ -+static int -+ubsec_dmamap_aligned(struct ubsec_softc *sc, const struct ubsec_dma_alloc *q_map, int mlen) -+{ -+ int i; -+ -+#ifdef UBSEC_DEBUG -+ DPRINTF("%s()\n", __FUNCTION__); -+#endif -+ -+ for (i = 0; i < mlen; i++) { -+ if (q_map[i].dma_paddr & 3) -+ return (0); -+ if (i != (mlen - 1) && (q_map[i].dma_size & 3)) -+ return (0); -+ } -+ return (1); -+} -+ -+ -+#define N(a) (sizeof(a) / sizeof (a[0])) -+static void -+ubsec_setup_mackey(struct ubsec_session *ses, int algo, caddr_t key, int klen) -+{ -+#ifdef HMAC_HACK -+ MD5_CTX md5ctx; -+ SHA1_CTX sha1ctx; -+ int i; -+ -+#ifdef UBSEC_DEBUG -+ DPRINTF("%s()\n", __FUNCTION__); -+#endif -+ -+ for (i = 0; i < klen; i++) -+ key[i] ^= HMAC_IPAD_VAL; -+ -+ if (algo == CRYPTO_MD5_HMAC) { -+ MD5Init(&md5ctx); -+ MD5Update(&md5ctx, key, klen); -+ MD5Update(&md5ctx, hmac_ipad_buffer, MD5_HMAC_BLOCK_LEN - klen); -+ bcopy(md5ctx.md5_st8, ses->ses_hminner, sizeof(md5ctx.md5_st8)); -+ } else { -+ SHA1Init(&sha1ctx); -+ SHA1Update(&sha1ctx, key, klen); -+ SHA1Update(&sha1ctx, hmac_ipad_buffer, -+ SHA1_HMAC_BLOCK_LEN - klen); -+ bcopy(sha1ctx.h.b32, ses->ses_hminner, sizeof(sha1ctx.h.b32)); -+ } -+ -+ for (i = 0; i < klen; i++) -+ key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); -+ -+ if (algo == CRYPTO_MD5_HMAC) { -+ MD5Init(&md5ctx); -+ MD5Update(&md5ctx, key, klen); -+ MD5Update(&md5ctx, hmac_opad_buffer, MD5_HMAC_BLOCK_LEN - klen); -+ bcopy(md5ctx.md5_st8, ses->ses_hmouter, sizeof(md5ctx.md5_st8)); -+ } else { -+ SHA1Init(&sha1ctx); -+ SHA1Update(&sha1ctx, key, klen); -+ SHA1Update(&sha1ctx, hmac_opad_buffer, -+ SHA1_HMAC_BLOCK_LEN - klen); -+ bcopy(sha1ctx.h.b32, ses->ses_hmouter, sizeof(sha1ctx.h.b32)); -+ } -+ -+ for (i = 0; i < klen; i++) -+ key[i] ^= HMAC_OPAD_VAL; -+ -+#else /* HMAC_HACK */ -+ DPRINTF("md5/sha not implemented\n"); -+#endif /* HMAC_HACK */ -+} -+#undef N -+ -+static int -+__devinit ubsec_ssb_probe(struct ssb_device *sdev, -+ const struct ssb_device_id *ent) -+{ -+ int err; -+ -+#ifdef UBSEC_DEBUG -+ DPRINTF("%s()\n", __FUNCTION__); -+#endif -+ -+ err = ssb_bus_powerup(sdev->bus, 0); -+ if (err) { -+ dev_err(sdev->dev, "Failed to powerup the bus\n"); -+ goto err_out; -+ } -+ -+ err = request_irq(sdev->irq, (irq_handler_t)ubsec_ssb_isr, -+ IRQF_DISABLED | IRQF_SHARED, DRV_MODULE_NAME, sdev); -+ if (err) { -+ dev_err(sdev->dev, "Could not request irq\n"); -+ goto err_out_powerdown; -+ } -+ -+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,36)) -+ err = dma_set_mask(sdev->dma_dev, DMA_BIT_MASK(32)) || -+ dma_set_coherent_mask(sdev->dma_dev, DMA_BIT_MASK(32)); -+#else -+ err = ssb_dma_set_mask(sdev, DMA_32BIT_MASK); -+#endif -+ if (err) { -+ dev_err(sdev->dev, -+ "Required 32BIT DMA mask unsupported by the system.\n"); -+ goto err_out_free_irq; -+ } -+ -+ printk(KERN_INFO "Sentry5(tm) ROBOGateway(tm) IPSec Core at IRQ %u\n", -+ sdev->irq); -+ -+ DPRINTF("Vendor: %x, core id: %x, revision: %x\n", -+ sdev->id.vendor, sdev->id.coreid, sdev->id.revision); -+ -+ ssb_device_enable(sdev, 0); -+ -+ if (ubsec_attach(sdev, ent, sdev->dev) != 0) -+ goto err_out_disable; -+ -+#ifdef UBSEC_DEBUG -+ procdebug = create_proc_entry(DRV_MODULE_NAME, S_IRUSR, NULL); -+ if (procdebug) -+ { -+ procdebug->read_proc = proc_read; -+ procdebug->data = NULL; -+ } else -+ DPRINTF("Unable to create proc file.\n"); -+#endif -+ -+ return 0; -+ -+err_out_disable: -+ ssb_device_disable(sdev, 0); -+ -+err_out_free_irq: -+ free_irq(sdev->irq, sdev); -+ -+err_out_powerdown: -+ ssb_bus_may_powerdown(sdev->bus); -+ -+err_out: -+ return err; -+} -+ -+static void __devexit ubsec_ssb_remove(struct ssb_device *sdev) { -+ -+ struct ubsec_softc *sc; -+ unsigned int ctrlflgs; -+ struct ubsec_dma *dmap; -+ u_int32_t i; -+ -+#ifdef UBSEC_DEBUG -+ DPRINTF("%s()\n", __FUNCTION__); -+#endif -+ -+ ctrlflgs = READ_REG_SDEV(sdev, BS_CTRL); -+ /* disable all IPSec Core interrupts globally */ -+ ctrlflgs ^= (BS_CTRL_MCR1INT | BS_CTRL_MCR2INT | -+ BS_CTRL_DMAERR); -+ WRITE_REG_SDEV(sdev, BS_CTRL, ctrlflgs); -+ -+ free_irq(sdev->irq, sdev); -+ -+ sc = (struct ubsec_softc *)ssb_get_drvdata(sdev); -+ -+ /* unregister all crypto algorithms */ -+ crypto_unregister_all(sc->sc_cid); -+ -+ /* Free queue / dma memory */ -+ for (i = 0; i < UBS_MAX_NQUEUE; i++) { -+ struct ubsec_q *q; -+ -+ q = sc->sc_queuea[i]; -+ if (q != NULL) -+ { -+ dmap = q->q_dma; -+ if (dmap != NULL) -+ { -+ ubsec_dma_free(sc, &dmap->d_alloc); -+ q->q_dma = NULL; -+ } -+ kfree(q); -+ } -+ sc->sc_queuea[i] = NULL; -+ } -+ -+ ssb_device_disable(sdev, 0); -+ ssb_bus_may_powerdown(sdev->bus); -+ ssb_set_drvdata(sdev, NULL); -+ -+#ifdef UBSEC_DEBUG -+ if (procdebug) -+ remove_proc_entry(DRV_MODULE_NAME, NULL); -+#endif -+ -+} -+ -+ -+int -+ubsec_attach(struct ssb_device *sdev, const struct ssb_device_id *ent, -+ struct device *self) -+{ -+ struct ubsec_softc *sc = NULL; -+ struct ubsec_dma *dmap; -+ u_int32_t i; -+ static int num_chips = 0; -+ -+#ifdef UBSEC_DEBUG -+ DPRINTF("%s()\n", __FUNCTION__); -+#endif -+ -+ sc = (struct ubsec_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); -+ if (!sc) -+ return(-ENOMEM); -+ memset(sc, 0, sizeof(*sc)); -+ -+ sc->sc_dv = sdev->dev; -+ sc->sdev = sdev; -+ -+ spin_lock_init(&sc->sc_ringmtx); -+ -+ softc_device_init(sc, "ubsec_ssb", num_chips, ubsec_ssb_methods); -+ -+ /* Maybe someday there are boards with more than one chip available */ -+ if (num_chips < UBSEC_SSB_MAX_CHIPS) { -+ ubsec_chip_idx[device_get_unit(sc->sc_dev)] = sc; -+ num_chips++; -+ } -+ -+ ssb_set_drvdata(sdev, sc); -+ -+ BSD_SIMPLEQ_INIT(&sc->sc_queue); -+ BSD_SIMPLEQ_INIT(&sc->sc_qchip); -+ BSD_SIMPLEQ_INIT(&sc->sc_queue2); -+ BSD_SIMPLEQ_INIT(&sc->sc_qchip2); -+ BSD_SIMPLEQ_INIT(&sc->sc_q2free); -+ -+ sc->sc_statmask = BS_STAT_MCR1_DONE | BS_STAT_DMAERR; -+ -+ sc->sc_cid = crypto_get_driverid(softc_get_device(sc), CRYPTOCAP_F_HARDWARE); -+ if (sc->sc_cid < 0) { -+ device_printf(sc->sc_dev, "could not get crypto driver id\n"); -+ return -1; -+ } -+ -+ BSD_SIMPLEQ_INIT(&sc->sc_freequeue); -+ dmap = sc->sc_dmaa; -+ for (i = 0; i < UBS_MAX_NQUEUE; i++, dmap++) { -+ struct ubsec_q *q; -+ -+ q = (struct ubsec_q *)kmalloc(sizeof(struct ubsec_q), GFP_KERNEL); -+ if (q == NULL) { -+ printf(": can't allocate queue buffers\n"); -+ break; -+ } -+ -+ if (ubsec_dma_malloc(sc, &dmap->d_alloc, sizeof(struct ubsec_dmachunk),0)) { -+ printf(": can't allocate dma buffers\n"); -+ kfree(q); -+ break; -+ } -+ dmap->d_dma = (struct ubsec_dmachunk *)dmap->d_alloc.dma_vaddr; -+ -+ q->q_dma = dmap; -+ sc->sc_queuea[i] = q; -+ -+ BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); -+ } -+ -+ /* -+ * Reset Broadcom chip -+ */ -+ ubsec_reset_board(sc); -+ -+ /* -+ * Init Broadcom chip -+ */ -+ ubsec_init_board(sc); -+ -+ /* supported crypto algorithms */ -+ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); -+ -+ if (sc->sc_flags & UBS_FLAGS_AES) { -+ crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); -+ printf(KERN_INFO DRV_MODULE_NAME ": DES 3DES AES128 AES192 AES256 MD5_HMAC SHA1_HMAC\n"); -+ } -+ else -+ printf(KERN_INFO DRV_MODULE_NAME ": DES 3DES MD5_HMAC SHA1_HMAC\n"); -+ -+ crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); -+ -+ return 0; -+} -+ -+/* -+ * UBSEC Interrupt routine -+ */ -+static irqreturn_t -+ubsec_ssb_isr(int irq, void *arg, struct pt_regs *regs) -+{ -+ struct ubsec_softc *sc = NULL; -+ volatile u_int32_t stat; -+ struct ubsec_q *q; -+ struct ubsec_dma *dmap; -+ int npkts = 0, i; -+ -+#ifdef UBSEC_VERBOSE_DEBUG -+ DPRINTF("%s()\n", __FUNCTION__); -+#endif -+ -+ sc = (struct ubsec_softc *)ssb_get_drvdata(arg); -+ -+ stat = READ_REG(sc, BS_STAT); -+ -+ stat &= sc->sc_statmask; -+ if (stat == 0) -+ return IRQ_NONE; -+ -+ WRITE_REG(sc, BS_STAT, stat); /* IACK */ -+ -+ /* -+ * Check to see if we have any packets waiting for us -+ */ -+ if ((stat & BS_STAT_MCR1_DONE)) { -+ while (!BSD_SIMPLEQ_EMPTY(&sc->sc_qchip)) { -+ q = BSD_SIMPLEQ_FIRST(&sc->sc_qchip); -+ dmap = q->q_dma; -+ -+ if ((dmap->d_dma->d_mcr.mcr_flags & htole16(UBS_MCR_DONE)) == 0) -+ { -+ DPRINTF("error while processing MCR. Flags = %x\n", dmap->d_dma->d_mcr.mcr_flags); -+ break; -+ } -+ -+ BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q_next); -+ -+ npkts = q->q_nstacked_mcrs; -+ /* -+ * search for further sc_qchip ubsec_q's that share -+ * the same MCR, and complete them too, they must be -+ * at the top. -+ */ -+ for (i = 0; i < npkts; i++) { -+ if(q->q_stacked_mcr[i]) -+ ubsec_callback(sc, q->q_stacked_mcr[i]); -+ else -+ break; -+ } -+ ubsec_callback(sc, q); -+ } -+ -+ /* -+ * Don't send any more packet to chip if there has been -+ * a DMAERR. -+ */ -+ if (likely(!(stat & BS_STAT_DMAERR))) -+ ubsec_feed(sc); -+ else -+ DPRINTF("DMA error occurred. Stop feeding crypto chip.\n"); -+ } -+ -+ /* -+ * Check to see if we got any DMA Error -+ */ -+ if (stat & BS_STAT_DMAERR) { -+ volatile u_int32_t a = READ_REG(sc, BS_ERR); -+ -+ printf(KERN_ERR "%s: dmaerr %s@%08x\n", DRV_MODULE_NAME, -+ (a & BS_ERR_READ) ? "read" : "write", a & BS_ERR_ADDR); -+ -+ ubsecstats.hst_dmaerr++; -+ ubsec_totalreset(sc); -+ ubsec_feed(sc); -+ } -+ -+ return IRQ_HANDLED; -+} -+ -+/* -+ * ubsec_feed() - aggregate and post requests to chip -+ * It is assumed that the caller set splnet() -+ */ -+void -+ubsec_feed(struct ubsec_softc *sc) -+{ -+#ifdef UBSEC_VERBOSE_DEBUG -+ static int max; -+#endif -+ struct ubsec_q *q, *q2; -+ int npkts, i; -+ void *v; -+ u_int32_t stat; -+ -+ npkts = sc->sc_nqueue; -+ if (npkts > UBS_MAX_AGGR) -+ npkts = UBS_MAX_AGGR; -+ if (npkts < 2) -+ goto feed1; -+ -+ stat = READ_REG(sc, BS_STAT); -+ -+ if (stat & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) { -+ if(stat & BS_STAT_DMAERR) { -+ ubsec_totalreset(sc); -+ ubsecstats.hst_dmaerr++; -+ } -+ return; -+ } -+ -+#ifdef UBSEC_VERBOSE_DEBUG -+ DPRINTF("merging %d records\n", npkts); -+ -+ /* XXX temporary aggregation statistics reporting code */ -+ if (max < npkts) { -+ max = npkts; -+ DPRINTF("%s: new max aggregate %d\n", DRV_MODULE_NAME, max); -+ } -+#endif /* UBSEC_VERBOSE_DEBUG */ -+ -+ q = BSD_SIMPLEQ_FIRST(&sc->sc_queue); -+ BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next); -+ --sc->sc_nqueue; -+ -+#if 0 -+ /* -+ * XXX -+ * We use dma_map_single() - no sync required! -+ */ -+ -+ bus_dmamap_sync(sc->sc_dmat, q->q_src_map, -+ 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE); -+ if (q->q_dst_map != NULL) -+ bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, -+ 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD); -+#endif -+ -+ q->q_nstacked_mcrs = npkts - 1; /* Number of packets stacked */ -+ -+ for (i = 0; i < q->q_nstacked_mcrs; i++) { -+ q2 = BSD_SIMPLEQ_FIRST(&sc->sc_queue); -+ -+#if 0 -+ bus_dmamap_sync(sc->sc_dmat, q2->q_src_map, -+ 0, q2->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE); -+ if (q2->q_dst_map != NULL) -+ bus_dmamap_sync(sc->sc_dmat, q2->q_dst_map, -+ 0, q2->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD); -+#endif -+ BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next); -+ --sc->sc_nqueue; -+ -+ v = ((char *)&q2->q_dma->d_dma->d_mcr) + sizeof(struct ubsec_mcr) - -+ sizeof(struct ubsec_mcr_add); -+ bcopy(v, &q->q_dma->d_dma->d_mcradd[i], sizeof(struct ubsec_mcr_add)); -+ q->q_stacked_mcr[i] = q2; -+ } -+ q->q_dma->d_dma->d_mcr.mcr_pkts = htole16(npkts); -+ BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); -+#if 0 -+ bus_dmamap_sync(sc->sc_dmat, q->q_dma->d_alloc.dma_map, -+ 0, q->q_dma->d_alloc.dma_map->dm_mapsize, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+#endif -+ WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + -+ offsetof(struct ubsec_dmachunk, d_mcr)); -+#ifdef UBSEC_VERBOSE_DEBUG -+ DPRINTF("feed (1): q->chip %p %08x %08x\n", q, -+ (u_int32_t)q->q_dma->d_alloc.dma_paddr, -+ (u_int32_t)(q->q_dma->d_alloc.dma_paddr + -+ offsetof(struct ubsec_dmachunk, d_mcr))); -+#endif /* UBSEC_DEBUG */ -+ return; -+ -+feed1: -+ while (!BSD_SIMPLEQ_EMPTY(&sc->sc_queue)) { -+ stat = READ_REG(sc, BS_STAT); -+ -+ if (stat & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) { -+ if(stat & BS_STAT_DMAERR) { -+ ubsec_totalreset(sc); -+ ubsecstats.hst_dmaerr++; -+ } -+ break; -+ } -+ -+ q = BSD_SIMPLEQ_FIRST(&sc->sc_queue); -+ -+#if 0 -+ bus_dmamap_sync(sc->sc_dmat, q->q_src_map, -+ 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE); -+ if (q->q_dst_map != NULL) -+ bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, -+ 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD); -+ bus_dmamap_sync(sc->sc_dmat, q->q_dma->d_alloc.dma_map, -+ 0, q->q_dma->d_alloc.dma_map->dm_mapsize, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+#endif -+ -+ WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + -+ offsetof(struct ubsec_dmachunk, d_mcr)); -+#ifdef UBSEC_VERBOSE_DEBUG -+ DPRINTF("feed (2): q->chip %p %08x %08x\n", q, -+ (u_int32_t)q->q_dma->d_alloc.dma_paddr, -+ (u_int32_t)(q->q_dma->d_alloc.dma_paddr + -+ offsetof(struct ubsec_dmachunk, d_mcr))); -+#endif /* UBSEC_DEBUG */ -+ BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next); -+ --sc->sc_nqueue; -+ BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); -+ } -+} -+ -+/* -+ * Allocate a new 'session' and return an encoded session id. 'sidp' -+ * contains our registration id, and should contain an encoded session -+ * id on successful allocation. -+ */ -+static int -+ubsec_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) -+{ -+ struct cryptoini *c, *encini = NULL, *macini = NULL; -+ struct ubsec_softc *sc = NULL; -+ struct ubsec_session *ses = NULL; -+ int sesn, i; -+ -+#ifdef UBSEC_DEBUG -+ DPRINTF("%s()\n", __FUNCTION__); -+#endif -+ -+ if (sidp == NULL || cri == NULL) -+ return (EINVAL); -+ -+ sc = device_get_softc(dev); -+ -+ if (sc == NULL) -+ return (EINVAL); -+ -+ for (c = cri; c != NULL; c = c->cri_next) { -+ if (c->cri_alg == CRYPTO_MD5_HMAC || -+ c->cri_alg == CRYPTO_SHA1_HMAC) { -+ if (macini) -+ return (EINVAL); -+ macini = c; -+ } else if (c->cri_alg == CRYPTO_DES_CBC || -+ c->cri_alg == CRYPTO_3DES_CBC || -+ c->cri_alg == CRYPTO_AES_CBC) { -+ if (encini) -+ return (EINVAL); -+ encini = c; -+ } else -+ return (EINVAL); -+ } -+ if (encini == NULL && macini == NULL) -+ return (EINVAL); -+ -+ if (sc->sc_sessions == NULL) { -+ ses = sc->sc_sessions = (struct ubsec_session *)kmalloc( -+ sizeof(struct ubsec_session), SLAB_ATOMIC); -+ if (ses == NULL) -+ return (ENOMEM); -+ memset(ses, 0, sizeof(struct ubsec_session)); -+ sesn = 0; -+ sc->sc_nsessions = 1; -+ } else { -+ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { -+ if (sc->sc_sessions[sesn].ses_used == 0) { -+ ses = &sc->sc_sessions[sesn]; -+ break; -+ } -+ } -+ -+ if (ses == NULL) { -+ sesn = sc->sc_nsessions; -+ ses = (struct ubsec_session *)kmalloc((sesn + 1) * -+ sizeof(struct ubsec_session), SLAB_ATOMIC); -+ if (ses == NULL) -+ return (ENOMEM); -+ memset(ses, 0, (sesn + 1) * sizeof(struct ubsec_session)); -+ bcopy(sc->sc_sessions, ses, sesn * -+ sizeof(struct ubsec_session)); -+ bzero(sc->sc_sessions, sesn * -+ sizeof(struct ubsec_session)); -+ kfree(sc->sc_sessions); -+ sc->sc_sessions = ses; -+ ses = &sc->sc_sessions[sesn]; -+ sc->sc_nsessions++; -+ } -+ } -+ -+ bzero(ses, sizeof(struct ubsec_session)); -+ ses->ses_used = 1; -+ if (encini) { -+ /* get an IV */ -+ /* XXX may read fewer than requested */ -+ read_random(ses->ses_iv, sizeof(ses->ses_iv)); -+ -+ /* Go ahead and compute key in ubsec's byte order */ -+ if (encini->cri_alg == CRYPTO_DES_CBC) { -+ /* DES uses the same key three times: -+ * 1st encrypt -> 2nd decrypt -> 3nd encrypt */ -+ bcopy(encini->cri_key, &ses->ses_key[0], 8); -+ bcopy(encini->cri_key, &ses->ses_key[2], 8); -+ bcopy(encini->cri_key, &ses->ses_key[4], 8); -+ ses->ses_keysize = 192; /* Fake! Actually its only 64bits .. -+ oh no it is even less: 54bits. */ -+ } else if(encini->cri_alg == CRYPTO_3DES_CBC) { -+ bcopy(encini->cri_key, ses->ses_key, 24); -+ ses->ses_keysize = 192; -+ } else if(encini->cri_alg == CRYPTO_AES_CBC) { -+ ses->ses_keysize = encini->cri_klen; -+ -+ if (ses->ses_keysize != 128 && -+ ses->ses_keysize != 192 && -+ ses->ses_keysize != 256) -+ { -+ DPRINTF("unsupported AES key size: %d\n", ses->ses_keysize); -+ return (EINVAL); -+ } -+ bcopy(encini->cri_key, ses->ses_key, (ses->ses_keysize / 8)); -+ } -+ -+ /* Hardware requires the keys in little endian byte order */ -+ for (i=0; i < (ses->ses_keysize / 32); i++) -+ SWAP32(ses->ses_key[i]); -+ } -+ -+ if (macini) { -+ ses->ses_mlen = macini->cri_mlen; -+ -+ if (ses->ses_mlen == 0 || -+ ses->ses_mlen > SHA1_HASH_LEN) { -+ -+ if (macini->cri_alg == CRYPTO_MD5_HMAC || -+ macini->cri_alg == CRYPTO_SHA1_HMAC) -+ { -+ ses->ses_mlen = DEFAULT_HMAC_LEN; -+ } else -+ { -+ /* -+ * Reserved for future usage. MD5/SHA1 calculations have -+ * different hash sizes. -+ */ -+ printk(KERN_ERR DRV_MODULE_NAME ": unsupported hash operation with mac/hash len: %d\n", ses->ses_mlen); -+ return (EINVAL); -+ } -+ -+ } -+ -+ if (macini->cri_key != NULL) { -+ ubsec_setup_mackey(ses, macini->cri_alg, macini->cri_key, -+ macini->cri_klen / 8); -+ } -+ } -+ -+ *sidp = UBSEC_SID(device_get_unit(sc->sc_dev), sesn); -+ return (0); -+} -+ -+/* -+ * Deallocate a session. -+ */ -+static int -+ubsec_freesession(device_t dev, u_int64_t tid) -+{ -+ struct ubsec_softc *sc = device_get_softc(dev); -+ int session; -+ u_int32_t sid = ((u_int32_t)tid) & 0xffffffff; -+ -+#ifdef UBSEC_DEBUG -+ DPRINTF("%s()\n", __FUNCTION__); -+#endif -+ -+ if (sc == NULL) -+ return (EINVAL); -+ -+ session = UBSEC_SESSION(sid); -+ if (session < sc->sc_nsessions) { -+ bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session])); -+ return (0); -+ } else -+ return (EINVAL); -+} -+ -+static int -+ubsec_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ struct ubsec_q *q = NULL; -+ int err = 0, i, j, nicealign; -+ struct ubsec_softc *sc = device_get_softc(dev); -+ struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; -+ int encoffset = 0, macoffset = 0, cpskip, cpoffset; -+ int sskip, dskip, stheend, dtheend, ivsize = 8; -+ int16_t coffset; -+ struct ubsec_session *ses; -+ struct ubsec_generic_ctx ctx; -+ struct ubsec_dma *dmap = NULL; -+ unsigned long flags; -+ -+#ifdef UBSEC_DEBUG -+ DPRINTF("%s()\n", __FUNCTION__); -+#endif -+ -+ if (unlikely(crp == NULL || crp->crp_callback == NULL)) { -+ ubsecstats.hst_invalid++; -+ return (EINVAL); -+ } -+ -+ if (unlikely(sc == NULL)) -+ return (EINVAL); -+ -+#ifdef UBSEC_VERBOSE_DEBUG -+ DPRINTF("spin_lock_irqsave\n"); -+#endif -+ spin_lock_irqsave(&sc->sc_ringmtx, flags); -+ //spin_lock_irq(&sc->sc_ringmtx); -+ -+ if (BSD_SIMPLEQ_EMPTY(&sc->sc_freequeue)) { -+ ubsecstats.hst_queuefull++; -+#ifdef UBSEC_VERBOSE_DEBUG -+ DPRINTF("spin_unlock_irqrestore\n"); -+#endif -+ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); -+ //spin_unlock_irq(&sc->sc_ringmtx); -+ err = ENOMEM; -+ goto errout2; -+ } -+ -+ q = BSD_SIMPLEQ_FIRST(&sc->sc_freequeue); -+ BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q_next); -+#ifdef UBSEC_VERBOSE_DEBUG -+ DPRINTF("spin_unlock_irqrestore\n"); -+#endif -+ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); -+ //spin_unlock_irq(&sc->sc_ringmtx); -+ -+ dmap = q->q_dma; /* Save dma pointer */ -+ bzero(q, sizeof(struct ubsec_q)); -+ bzero(&ctx, sizeof(ctx)); -+ -+ q->q_sesn = UBSEC_SESSION(crp->crp_sid); -+ q->q_dma = dmap; -+ ses = &sc->sc_sessions[q->q_sesn]; -+ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ q->q_src_m = (struct sk_buff *)crp->crp_buf; -+ q->q_dst_m = (struct sk_buff *)crp->crp_buf; -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ q->q_src_io = (struct uio *)crp->crp_buf; -+ q->q_dst_io = (struct uio *)crp->crp_buf; -+ } else { -+ err = EINVAL; -+ goto errout; /* XXX we don't handle contiguous blocks! */ -+ } -+ -+ bzero(&dmap->d_dma->d_mcr, sizeof(struct ubsec_mcr)); -+ -+ dmap->d_dma->d_mcr.mcr_pkts = htole16(1); -+ dmap->d_dma->d_mcr.mcr_flags = 0; -+ q->q_crp = crp; -+ -+ crd1 = crp->crp_desc; -+ if (crd1 == NULL) { -+ err = EINVAL; -+ goto errout; -+ } -+ crd2 = crd1->crd_next; -+ -+ if (crd2 == NULL) { -+ if (crd1->crd_alg == CRYPTO_MD5_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1_HMAC) { -+ maccrd = crd1; -+ enccrd = NULL; -+ } else if (crd1->crd_alg == CRYPTO_DES_CBC || -+ crd1->crd_alg == CRYPTO_3DES_CBC || -+ crd1->crd_alg == CRYPTO_AES_CBC) { -+ maccrd = NULL; -+ enccrd = crd1; -+ } else { -+ err = EINVAL; -+ goto errout; -+ } -+ } else { -+ if ((crd1->crd_alg == CRYPTO_MD5_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1_HMAC) && -+ (crd2->crd_alg == CRYPTO_DES_CBC || -+ crd2->crd_alg == CRYPTO_3DES_CBC || -+ crd2->crd_alg == CRYPTO_AES_CBC) && -+ ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { -+ maccrd = crd1; -+ enccrd = crd2; -+ } else if ((crd1->crd_alg == CRYPTO_DES_CBC || -+ crd1->crd_alg == CRYPTO_3DES_CBC || -+ crd1->crd_alg == CRYPTO_AES_CBC) && -+ (crd2->crd_alg == CRYPTO_MD5_HMAC || -+ crd2->crd_alg == CRYPTO_SHA1_HMAC) && -+ (crd1->crd_flags & CRD_F_ENCRYPT)) { -+ enccrd = crd1; -+ maccrd = crd2; -+ } else { -+ /* -+ * We cannot order the ubsec as requested -+ */ -+ printk(KERN_ERR DRV_MODULE_NAME ": got wrong algorithm/signature order.\n"); -+ err = EINVAL; -+ goto errout; -+ } -+ } -+ -+ /* Encryption/Decryption requested */ -+ if (enccrd) { -+ encoffset = enccrd->crd_skip; -+ -+ if (enccrd->crd_alg == CRYPTO_DES_CBC || -+ enccrd->crd_alg == CRYPTO_3DES_CBC) -+ { -+ ctx.pc_flags |= htole16(UBS_PKTCTX_ENC_3DES); -+ ctx.pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC_DES); -+ ivsize = 8; /* [3]DES uses 64bit IVs */ -+ } else { -+ ctx.pc_flags |= htole16(UBS_PKTCTX_ENC_AES); -+ ctx.pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC_AES); -+ ivsize = 16; /* AES uses 128bit IVs / [3]DES 64bit IVs */ -+ -+ switch(ses->ses_keysize) -+ { -+ case 128: -+ ctx.pc_flags |= htole16(UBS_PKTCTX_AES128); -+ break; -+ case 192: -+ ctx.pc_flags |= htole16(UBS_PKTCTX_AES192); -+ break; -+ case 256: -+ ctx.pc_flags |= htole16(UBS_PKTCTX_AES256); -+ break; -+ default: -+ DPRINTF("invalid AES key size: %d\n", ses->ses_keysize); -+ err = EINVAL; -+ goto errout; -+ } -+ } -+ -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) { -+ /* Direction: Outbound */ -+ -+ q->q_flags |= UBSEC_QFLAGS_COPYOUTIV; -+ -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) { -+ bcopy(enccrd->crd_iv, ctx.pc_iv, ivsize); -+ } else { -+ for(i=0; i < (ivsize / 4); i++) -+ ctx.pc_iv[i] = ses->ses_iv[i]; -+ } -+ -+ /* If there is no IV in the buffer -> copy it here */ -+ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { -+ if (crp->crp_flags & CRYPTO_F_SKBUF) -+ /* -+ m_copyback(q->q_src_m, -+ enccrd->crd_inject, -+ 8, ctx.pc_iv); -+ */ -+ crypto_copyback(crp->crp_flags, (caddr_t)q->q_src_m, -+ enccrd->crd_inject, ivsize, (caddr_t)ctx.pc_iv); -+ else if (crp->crp_flags & CRYPTO_F_IOV) -+ /* -+ cuio_copyback(q->q_src_io, -+ enccrd->crd_inject, -+ 8, ctx.pc_iv); -+ */ -+ crypto_copyback(crp->crp_flags, (caddr_t)q->q_src_io, -+ enccrd->crd_inject, ivsize, (caddr_t)ctx.pc_iv); -+ } -+ } else { -+ /* Direction: Inbound */ -+ -+ ctx.pc_flags |= htole16(UBS_PKTCTX_INBOUND); -+ -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) -+ bcopy(enccrd->crd_iv, ctx.pc_iv, ivsize); -+ else if (crp->crp_flags & CRYPTO_F_SKBUF) -+ /* -+ m_copydata(q->q_src_m, enccrd->crd_inject, -+ 8, (caddr_t)ctx.pc_iv); -+ */ -+ crypto_copydata(crp->crp_flags, (caddr_t)q->q_src_m, -+ enccrd->crd_inject, ivsize, -+ (caddr_t)ctx.pc_iv); -+ else if (crp->crp_flags & CRYPTO_F_IOV) -+ /* -+ cuio_copydata(q->q_src_io, -+ enccrd->crd_inject, 8, -+ (caddr_t)ctx.pc_iv); -+ */ -+ crypto_copydata(crp->crp_flags, (caddr_t)q->q_src_io, -+ enccrd->crd_inject, ivsize, -+ (caddr_t)ctx.pc_iv); -+ -+ } -+ -+ /* Even though key & IV sizes differ from cipher to cipher -+ * copy / swap the full array lengths. Let the compiler unroll -+ * the loop to increase the cpu pipeline performance... */ -+ for(i=0; i < 8; i++) -+ ctx.pc_key[i] = ses->ses_key[i]; -+ for(i=0; i < 4; i++) -+ SWAP32(ctx.pc_iv[i]); -+ } -+ -+ /* Authentication requested */ -+ if (maccrd) { -+ macoffset = maccrd->crd_skip; -+ -+ if (maccrd->crd_alg == CRYPTO_MD5_HMAC) -+ ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_MD5); -+ else -+ ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_SHA1); -+ -+ for (i = 0; i < 5; i++) { -+ ctx.pc_hminner[i] = ses->ses_hminner[i]; -+ ctx.pc_hmouter[i] = ses->ses_hmouter[i]; -+ -+ HTOLE32(ctx.pc_hminner[i]); -+ HTOLE32(ctx.pc_hmouter[i]); -+ } -+ } -+ -+ if (enccrd && maccrd) { -+ /* -+ * ubsec cannot handle packets where the end of encryption -+ * and authentication are not the same, or where the -+ * encrypted part begins before the authenticated part. -+ */ -+ if (((encoffset + enccrd->crd_len) != -+ (macoffset + maccrd->crd_len)) || -+ (enccrd->crd_skip < maccrd->crd_skip)) { -+ err = EINVAL; -+ goto errout; -+ } -+ sskip = maccrd->crd_skip; -+ cpskip = dskip = enccrd->crd_skip; -+ stheend = maccrd->crd_len; -+ dtheend = enccrd->crd_len; -+ coffset = enccrd->crd_skip - maccrd->crd_skip; -+ cpoffset = cpskip + dtheend; -+#ifdef UBSEC_DEBUG -+ DPRINTF("mac: skip %d, len %d, inject %d\n", -+ maccrd->crd_skip, maccrd->crd_len, maccrd->crd_inject); -+ DPRINTF("enc: skip %d, len %d, inject %d\n", -+ enccrd->crd_skip, enccrd->crd_len, enccrd->crd_inject); -+ DPRINTF("src: skip %d, len %d\n", sskip, stheend); -+ DPRINTF("dst: skip %d, len %d\n", dskip, dtheend); -+ DPRINTF("ubs: coffset %d, pktlen %d, cpskip %d, cpoffset %d\n", -+ coffset, stheend, cpskip, cpoffset); -+#endif -+ } else { -+ cpskip = dskip = sskip = macoffset + encoffset; -+ dtheend = stheend = (enccrd)?enccrd->crd_len:maccrd->crd_len; -+ cpoffset = cpskip + dtheend; -+ coffset = 0; -+ } -+ ctx.pc_offset = htole16(coffset >> 2); -+ -+#if 0 -+ if (bus_dmamap_create(sc->sc_dmat, 0xfff0, UBS_MAX_SCATTER, -+ 0xfff0, 0, BUS_DMA_NOWAIT, &q->q_src_map) != 0) { -+ err = ENOMEM; -+ goto errout; -+ } -+#endif -+ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+#if 0 -+ if (bus_dmamap_load_mbuf(sc->sc_dmat, q->q_src_map, -+ q->q_src_m, BUS_DMA_NOWAIT) != 0) { -+ bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); -+ q->q_src_map = NULL; -+ err = ENOMEM; -+ goto errout; -+ } -+#endif -+ err = dma_map_skb(sc, q->q_src_map, q->q_src_m, &q->q_src_len); -+ if (unlikely(err != 0)) -+ goto errout; -+ -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+#if 0 -+ if (bus_dmamap_load_uio(sc->sc_dmat, q->q_src_map, -+ q->q_src_io, BUS_DMA_NOWAIT) != 0) { -+ bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); -+ q->q_src_map = NULL; -+ err = ENOMEM; -+ goto errout; -+ } -+#endif -+ err = dma_map_uio(sc, q->q_src_map, q->q_src_io, &q->q_src_len); -+ if (unlikely(err != 0)) -+ goto errout; -+ } -+ -+ /* -+ * Check alignment -+ */ -+ nicealign = ubsec_dmamap_aligned(sc, q->q_src_map, q->q_src_len); -+ -+ dmap->d_dma->d_mcr.mcr_pktlen = htole16(stheend); -+ -+#ifdef UBSEC_DEBUG -+ DPRINTF("src skip: %d\n", sskip); -+#endif -+ for (i = j = 0; i < q->q_src_len; i++) { -+ struct ubsec_pktbuf *pb; -+ size_t packl = q->q_src_map[i].dma_size; -+ dma_addr_t packp = q->q_src_map[i].dma_paddr; -+ -+ if (sskip >= packl) { -+ sskip -= packl; -+ continue; -+ } -+ -+ packl -= sskip; -+ packp += sskip; -+ sskip = 0; -+ -+ /* maximum fragment size is 0xfffc */ -+ if (packl > 0xfffc) { -+ DPRINTF("Error: fragment size is bigger than 0xfffc.\n"); -+ err = EIO; -+ goto errout; -+ } -+ -+ if (j == 0) -+ pb = &dmap->d_dma->d_mcr.mcr_ipktbuf; -+ else -+ pb = &dmap->d_dma->d_sbuf[j - 1]; -+ -+ pb->pb_addr = htole32(packp); -+ -+ if (stheend) { -+ if (packl > stheend) { -+ pb->pb_len = htole32(stheend); -+ stheend = 0; -+ } else { -+ pb->pb_len = htole32(packl); -+ stheend -= packl; -+ } -+ } else -+ pb->pb_len = htole32(packl); -+ -+ if ((i + 1) == q->q_src_len) -+ pb->pb_next = 0; -+ else -+ pb->pb_next = htole32(dmap->d_alloc.dma_paddr + -+ offsetof(struct ubsec_dmachunk, d_sbuf[j])); -+ j++; -+ } -+ -+ if (enccrd == NULL && maccrd != NULL) { -+ /* Authentication only */ -+ dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr = 0; -+ dmap->d_dma->d_mcr.mcr_opktbuf.pb_len = 0; -+ dmap->d_dma->d_mcr.mcr_opktbuf.pb_next = -+ htole32(dmap->d_alloc.dma_paddr + -+ offsetof(struct ubsec_dmachunk, d_macbuf[0])); -+#ifdef UBSEC_DEBUG -+ DPRINTF("opkt: %x %x %x\n", -+ dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr, -+ dmap->d_dma->d_mcr.mcr_opktbuf.pb_len, -+ dmap->d_dma->d_mcr.mcr_opktbuf.pb_next); -+#endif -+ } else { -+ if (crp->crp_flags & CRYPTO_F_IOV) { -+ if (!nicealign) { -+ err = EINVAL; -+ goto errout; -+ } -+#if 0 -+ if (bus_dmamap_create(sc->sc_dmat, 0xfff0, -+ UBS_MAX_SCATTER, 0xfff0, 0, BUS_DMA_NOWAIT, -+ &q->q_dst_map) != 0) { -+ err = ENOMEM; -+ goto errout; -+ } -+ if (bus_dmamap_load_uio(sc->sc_dmat, q->q_dst_map, -+ q->q_dst_io, BUS_DMA_NOWAIT) != 0) { -+ bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); -+ q->q_dst_map = NULL; -+ goto errout; -+ } -+#endif -+ -+ /* HW shall copy the result into the source memory */ -+ for(i = 0; i < q->q_src_len; i++) -+ q->q_dst_map[i] = q->q_src_map[i]; -+ -+ q->q_dst_len = q->q_src_len; -+ q->q_has_dst = 0; -+ -+ } else if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ if (nicealign) { -+ -+ /* HW shall copy the result into the source memory */ -+ q->q_dst_m = q->q_src_m; -+ for(i = 0; i < q->q_src_len; i++) -+ q->q_dst_map[i] = q->q_src_map[i]; -+ -+ q->q_dst_len = q->q_src_len; -+ q->q_has_dst = 0; -+ -+ } else { -+#ifdef NOTYET -+ int totlen, len; -+ struct sk_buff *m, *top, **mp; -+ -+ totlen = q->q_src_map->dm_mapsize; -+ if (q->q_src_m->m_flags & M_PKTHDR) { -+ len = MHLEN; -+ MGETHDR(m, M_DONTWAIT, MT_DATA); -+ } else { -+ len = MLEN; -+ MGET(m, M_DONTWAIT, MT_DATA); -+ } -+ if (m == NULL) { -+ err = ENOMEM; -+ goto errout; -+ } -+ if (len == MHLEN) -+ M_DUP_PKTHDR(m, q->q_src_m); -+ if (totlen >= MINCLSIZE) { -+ MCLGET(m, M_DONTWAIT); -+ if (m->m_flags & M_EXT) -+ len = MCLBYTES; -+ } -+ m->m_len = len; -+ top = NULL; -+ mp = ⊤ -+ -+ while (totlen > 0) { -+ if (top) { -+ MGET(m, M_DONTWAIT, MT_DATA); -+ if (m == NULL) { -+ m_freem(top); -+ err = ENOMEM; -+ goto errout; -+ } -+ len = MLEN; -+ } -+ if (top && totlen >= MINCLSIZE) { -+ MCLGET(m, M_DONTWAIT); -+ if (m->m_flags & M_EXT) -+ len = MCLBYTES; -+ } -+ m->m_len = len = min(totlen, len); -+ totlen -= len; -+ *mp = m; -+ mp = &m->m_next; -+ } -+ q->q_dst_m = top; -+ ubsec_mcopy(q->q_src_m, q->q_dst_m, -+ cpskip, cpoffset); -+ if (bus_dmamap_create(sc->sc_dmat, 0xfff0, -+ UBS_MAX_SCATTER, 0xfff0, 0, BUS_DMA_NOWAIT, -+ &q->q_dst_map) != 0) { -+ err = ENOMEM; -+ goto errout; -+ } -+ if (bus_dmamap_load_mbuf(sc->sc_dmat, -+ q->q_dst_map, q->q_dst_m, -+ BUS_DMA_NOWAIT) != 0) { -+ bus_dmamap_destroy(sc->sc_dmat, -+ q->q_dst_map); -+ q->q_dst_map = NULL; -+ err = ENOMEM; -+ goto errout; -+ } -+#else -+ device_printf(sc->sc_dev, -+ "%s,%d: CRYPTO_F_SKBUF unaligned not implemented\n", -+ __FILE__, __LINE__); -+ err = EINVAL; -+ goto errout; -+#endif -+ } -+ } else { -+ err = EINVAL; -+ goto errout; -+ } -+ -+#ifdef UBSEC_DEBUG -+ DPRINTF("dst skip: %d\n", dskip); -+#endif -+ for (i = j = 0; i < q->q_dst_len; i++) { -+ struct ubsec_pktbuf *pb; -+ size_t packl = q->q_dst_map[i].dma_size; -+ dma_addr_t packp = q->q_dst_map[i].dma_paddr; -+ -+ if (dskip >= packl) { -+ dskip -= packl; -+ continue; -+ } -+ -+ packl -= dskip; -+ packp += dskip; -+ dskip = 0; -+ -+ if (packl > 0xfffc) { -+ DPRINTF("Error: fragment size is bigger than 0xfffc.\n"); -+ err = EIO; -+ goto errout; -+ } -+ -+ if (j == 0) -+ pb = &dmap->d_dma->d_mcr.mcr_opktbuf; -+ else -+ pb = &dmap->d_dma->d_dbuf[j - 1]; -+ -+ pb->pb_addr = htole32(packp); -+ -+ if (dtheend) { -+ if (packl > dtheend) { -+ pb->pb_len = htole32(dtheend); -+ dtheend = 0; -+ } else { -+ pb->pb_len = htole32(packl); -+ dtheend -= packl; -+ } -+ } else -+ pb->pb_len = htole32(packl); -+ -+ if ((i + 1) == q->q_dst_len) { -+ if (maccrd) -+ /* Authentication: -+ * The last fragment of the output buffer -+ * contains the HMAC. */ -+ pb->pb_next = htole32(dmap->d_alloc.dma_paddr + -+ offsetof(struct ubsec_dmachunk, d_macbuf[0])); -+ else -+ pb->pb_next = 0; -+ } else -+ pb->pb_next = htole32(dmap->d_alloc.dma_paddr + -+ offsetof(struct ubsec_dmachunk, d_dbuf[j])); -+ j++; -+ } -+ } -+ -+ dmap->d_dma->d_mcr.mcr_cmdctxp = htole32(dmap->d_alloc.dma_paddr + -+ offsetof(struct ubsec_dmachunk, d_ctx)); -+ -+ if (sc->sc_flags & UBS_FLAGS_LONGCTX) { -+ /* new Broadcom cards with dynamic long command context structure */ -+ -+ if (enccrd != NULL && -+ enccrd->crd_alg == CRYPTO_AES_CBC) -+ { -+ struct ubsec_pktctx_aes128 *ctxaes128; -+ struct ubsec_pktctx_aes192 *ctxaes192; -+ struct ubsec_pktctx_aes256 *ctxaes256; -+ -+ switch(ses->ses_keysize) -+ { -+ /* AES 128bit */ -+ case 128: -+ ctxaes128 = (struct ubsec_pktctx_aes128 *) -+ (dmap->d_alloc.dma_vaddr + -+ offsetof(struct ubsec_dmachunk, d_ctx)); -+ -+ ctxaes128->pc_len = htole16(sizeof(struct ubsec_pktctx_aes128)); -+ ctxaes128->pc_type = ctx.pc_type; -+ ctxaes128->pc_flags = ctx.pc_flags; -+ ctxaes128->pc_offset = ctx.pc_offset; -+ for (i = 0; i < 4; i++) -+ ctxaes128->pc_aeskey[i] = ctx.pc_key[i]; -+ for (i = 0; i < 5; i++) -+ ctxaes128->pc_hminner[i] = ctx.pc_hminner[i]; -+ for (i = 0; i < 5; i++) -+ ctxaes128->pc_hmouter[i] = ctx.pc_hmouter[i]; -+ for (i = 0; i < 4; i++) -+ ctxaes128->pc_iv[i] = ctx.pc_iv[i]; -+ break; -+ -+ /* AES 192bit */ -+ case 192: -+ ctxaes192 = (struct ubsec_pktctx_aes192 *) -+ (dmap->d_alloc.dma_vaddr + -+ offsetof(struct ubsec_dmachunk, d_ctx)); -+ -+ ctxaes192->pc_len = htole16(sizeof(struct ubsec_pktctx_aes192)); -+ ctxaes192->pc_type = ctx.pc_type; -+ ctxaes192->pc_flags = ctx.pc_flags; -+ ctxaes192->pc_offset = ctx.pc_offset; -+ for (i = 0; i < 6; i++) -+ ctxaes192->pc_aeskey[i] = ctx.pc_key[i]; -+ for (i = 0; i < 5; i++) -+ ctxaes192->pc_hminner[i] = ctx.pc_hminner[i]; -+ for (i = 0; i < 5; i++) -+ ctxaes192->pc_hmouter[i] = ctx.pc_hmouter[i]; -+ for (i = 0; i < 4; i++) -+ ctxaes192->pc_iv[i] = ctx.pc_iv[i]; -+ break; -+ -+ /* AES 256bit */ -+ case 256: -+ ctxaes256 = (struct ubsec_pktctx_aes256 *) -+ (dmap->d_alloc.dma_vaddr + -+ offsetof(struct ubsec_dmachunk, d_ctx)); -+ -+ ctxaes256->pc_len = htole16(sizeof(struct ubsec_pktctx_aes256)); -+ ctxaes256->pc_type = ctx.pc_type; -+ ctxaes256->pc_flags = ctx.pc_flags; -+ ctxaes256->pc_offset = ctx.pc_offset; -+ for (i = 0; i < 8; i++) -+ ctxaes256->pc_aeskey[i] = ctx.pc_key[i]; -+ for (i = 0; i < 5; i++) -+ ctxaes256->pc_hminner[i] = ctx.pc_hminner[i]; -+ for (i = 0; i < 5; i++) -+ ctxaes256->pc_hmouter[i] = ctx.pc_hmouter[i]; -+ for (i = 0; i < 4; i++) -+ ctxaes256->pc_iv[i] = ctx.pc_iv[i]; -+ break; -+ -+ } -+ } else { -+ /* -+ * [3]DES / MD5_HMAC / SHA1_HMAC -+ * -+ * MD5_HMAC / SHA1_HMAC can use the IPSEC 3DES operation without -+ * encryption. -+ */ -+ struct ubsec_pktctx_des *ctxdes; -+ -+ ctxdes = (struct ubsec_pktctx_des *)(dmap->d_alloc.dma_vaddr + -+ offsetof(struct ubsec_dmachunk, d_ctx)); -+ -+ ctxdes->pc_len = htole16(sizeof(struct ubsec_pktctx_des)); -+ ctxdes->pc_type = ctx.pc_type; -+ ctxdes->pc_flags = ctx.pc_flags; -+ ctxdes->pc_offset = ctx.pc_offset; -+ for (i = 0; i < 6; i++) -+ ctxdes->pc_deskey[i] = ctx.pc_key[i]; -+ for (i = 0; i < 5; i++) -+ ctxdes->pc_hminner[i] = ctx.pc_hminner[i]; -+ for (i = 0; i < 5; i++) -+ ctxdes->pc_hmouter[i] = ctx.pc_hmouter[i]; -+ ctxdes->pc_iv[0] = ctx.pc_iv[0]; -+ ctxdes->pc_iv[1] = ctx.pc_iv[1]; -+ } -+ } else -+ { -+ /* old Broadcom card with fixed small command context structure */ -+ -+ /* -+ * [3]DES / MD5_HMAC / SHA1_HMAC -+ */ -+ struct ubsec_pktctx *ctxs; -+ -+ ctxs = (struct ubsec_pktctx *)(dmap->d_alloc.dma_vaddr + -+ offsetof(struct ubsec_dmachunk, d_ctx)); -+ -+ /* transform generic context into small context */ -+ for (i = 0; i < 6; i++) -+ ctxs->pc_deskey[i] = ctx.pc_key[i]; -+ for (i = 0; i < 5; i++) -+ ctxs->pc_hminner[i] = ctx.pc_hminner[i]; -+ for (i = 0; i < 5; i++) -+ ctxs->pc_hmouter[i] = ctx.pc_hmouter[i]; -+ ctxs->pc_iv[0] = ctx.pc_iv[0]; -+ ctxs->pc_iv[1] = ctx.pc_iv[1]; -+ ctxs->pc_flags = ctx.pc_flags; -+ ctxs->pc_offset = ctx.pc_offset; -+ } -+ -+#ifdef UBSEC_VERBOSE_DEBUG -+ DPRINTF("spin_lock_irqsave\n"); -+#endif -+ spin_lock_irqsave(&sc->sc_ringmtx, flags); -+ //spin_lock_irq(&sc->sc_ringmtx); -+ -+ BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_queue, q, q_next); -+ sc->sc_nqueue++; -+ ubsecstats.hst_ipackets++; -+ ubsecstats.hst_ibytes += stheend; -+ ubsec_feed(sc); -+ -+#ifdef UBSEC_VERBOSE_DEBUG -+ DPRINTF("spin_unlock_irqrestore\n"); -+#endif -+ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); -+ //spin_unlock_irq(&sc->sc_ringmtx); -+ -+ return (0); -+ -+errout: -+ if (q != NULL) { -+#ifdef NOTYET -+ if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) -+ m_freem(q->q_dst_m); -+#endif -+ -+ if ((q->q_has_dst == 1) && q->q_dst_len > 0) { -+#if 0 -+ bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); -+ bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); -+#endif -+ dma_unmap(sc, q->q_dst_map, q->q_dst_len); -+ } -+ if (q->q_src_len > 0) { -+#if 0 -+ bus_dmamap_unload(sc->sc_dmat, q->q_src_map); -+ bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); -+#endif -+ dma_unmap(sc, q->q_src_map, q->q_src_len); -+ } -+ -+#ifdef UBSEC_VERBOSE_DEBUG -+ DPRINTF("spin_lock_irqsave\n"); -+#endif -+ spin_lock_irqsave(&sc->sc_ringmtx, flags); -+ //spin_lock_irq(&sc->sc_ringmtx); -+ -+ BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); -+ -+#ifdef UBSEC_VERBOSE_DEBUG -+ DPRINTF("spin_unlock_irqrestore\n"); -+#endif -+ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); -+ //spin_unlock_irq(&sc->sc_ringmtx); -+ -+ } -+ if (err == EINVAL) -+ ubsecstats.hst_invalid++; -+ else -+ ubsecstats.hst_nomem++; -+errout2: -+ crp->crp_etype = err; -+ crypto_done(crp); -+ -+#ifdef UBSEC_DEBUG -+ DPRINTF("%s() err = %x\n", __FUNCTION__, err); -+#endif -+ -+ return (0); -+} -+ -+void -+ubsec_callback(struct ubsec_softc *sc, struct ubsec_q *q) -+{ -+ struct cryptop *crp = (struct cryptop *)q->q_crp; -+ struct cryptodesc *crd; -+ struct ubsec_dma *dmap = q->q_dma; -+ int ivsize = 8; -+ -+#ifdef UBSEC_DEBUG -+ DPRINTF("%s()\n", __FUNCTION__); -+#endif -+ -+ ubsecstats.hst_opackets++; -+ ubsecstats.hst_obytes += dmap->d_alloc.dma_size; -+ -+#if 0 -+ bus_dmamap_sync(sc->sc_dmat, dmap->d_alloc.dma_map, 0, -+ dmap->d_alloc.dma_map->dm_mapsize, -+ BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); -+ if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { -+ bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, -+ 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_POSTREAD); -+ bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); -+ bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); -+ } -+ bus_dmamap_sync(sc->sc_dmat, q->q_src_map, -+ 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); -+ bus_dmamap_unload(sc->sc_dmat, q->q_src_map); -+ bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); -+#endif -+ -+ if ((q->q_has_dst == 1) && q->q_dst_len > 0) -+ dma_unmap(sc, q->q_dst_map, q->q_dst_len); -+ -+ dma_unmap(sc, q->q_src_map, q->q_src_len); -+ -+#ifdef NOTYET -+ if ((crp->crp_flags & CRYPTO_F_SKBUF) && (q->q_src_m != q->q_dst_m)) { -+ m_freem(q->q_src_m); -+ crp->crp_buf = (caddr_t)q->q_dst_m; -+ } -+#endif -+ -+ /* copy out IV for future use */ -+ if (q->q_flags & UBSEC_QFLAGS_COPYOUTIV) { -+ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { -+ if (crd->crd_alg != CRYPTO_DES_CBC && -+ crd->crd_alg != CRYPTO_3DES_CBC && -+ crd->crd_alg != CRYPTO_AES_CBC) -+ continue; -+ -+ if (crd->crd_alg == CRYPTO_AES_CBC) -+ ivsize = 16; -+ else -+ ivsize = 8; -+ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) -+#if 0 -+ m_copydata((struct sk_buff *)crp->crp_buf, -+ crd->crd_skip + crd->crd_len - 8, 8, -+ (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv); -+#endif -+ crypto_copydata(crp->crp_flags, (caddr_t)crp->crp_buf, -+ crd->crd_skip + crd->crd_len - ivsize, ivsize, -+ (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv); -+ -+ else if (crp->crp_flags & CRYPTO_F_IOV) { -+#if 0 -+ cuio_copydata((struct uio *)crp->crp_buf, -+ crd->crd_skip + crd->crd_len - 8, 8, -+ (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv); -+#endif -+ crypto_copydata(crp->crp_flags, (caddr_t)crp->crp_buf, -+ crd->crd_skip + crd->crd_len - ivsize, ivsize, -+ (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv); -+ -+ } -+ break; -+ } -+ } -+ -+ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { -+ if (crd->crd_alg != CRYPTO_MD5_HMAC && -+ crd->crd_alg != CRYPTO_SHA1_HMAC) -+ continue; -+#if 0 -+ if (crp->crp_flags & CRYPTO_F_SKBUF) -+ m_copyback((struct sk_buff *)crp->crp_buf, -+ crd->crd_inject, 12, -+ dmap->d_dma->d_macbuf); -+#endif -+#if 0 -+ /* BUG? it does not honor the mac len.. */ -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, 12, -+ (caddr_t)dmap->d_dma->d_macbuf); -+#endif -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, -+ sc->sc_sessions[q->q_sesn].ses_mlen, -+ (caddr_t)dmap->d_dma->d_macbuf); -+#if 0 -+ else if (crp->crp_flags & CRYPTO_F_IOV && crp->crp_mac) -+ bcopy((caddr_t)dmap->d_dma->d_macbuf, -+ crp->crp_mac, 12); -+#endif -+ break; -+ } -+ BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); -+ crypto_done(crp); -+} -+ -+void -+ubsec_mcopy(struct sk_buff *srcm, struct sk_buff *dstm, int hoffset, int toffset) -+{ -+ int i, j, dlen, slen; -+ caddr_t dptr, sptr; -+ -+ j = 0; -+ sptr = srcm->data; -+ slen = srcm->len; -+ dptr = dstm->data; -+ dlen = dstm->len; -+ -+ while (1) { -+ for (i = 0; i < min(slen, dlen); i++) { -+ if (j < hoffset || j >= toffset) -+ *dptr++ = *sptr++; -+ slen--; -+ dlen--; -+ j++; -+ } -+ if (slen == 0) { -+ srcm = srcm->next; -+ if (srcm == NULL) -+ return; -+ sptr = srcm->data; -+ slen = srcm->len; -+ } -+ if (dlen == 0) { -+ dstm = dstm->next; -+ if (dstm == NULL) -+ return; -+ dptr = dstm->data; -+ dlen = dstm->len; -+ } -+ } -+} -+ -+int -+ubsec_dma_malloc(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma, -+ size_t size, int mapflags) -+{ -+ dma->dma_vaddr = dma_alloc_coherent(sc->sc_dv, -+ size, &dma->dma_paddr, GFP_KERNEL); -+ -+ if (likely(dma->dma_vaddr)) -+ { -+ dma->dma_size = size; -+ return (0); -+ } -+ -+ DPRINTF("could not allocate %d bytes of coherent memory.\n", size); -+ -+ return (1); -+} -+ -+void -+ubsec_dma_free(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma) -+{ -+ dma_free_coherent(sc->sc_dv, dma->dma_size, dma->dma_vaddr, -+ dma->dma_paddr); -+} -+ -+/* -+ * Resets the board. Values in the regesters are left as is -+ * from the reset (i.e. initial values are assigned elsewhere). -+ */ -+void -+ubsec_reset_board(struct ubsec_softc *sc) -+{ -+ volatile u_int32_t ctrl; -+ -+#ifdef UBSEC_DEBUG -+ DPRINTF("%s()\n", __FUNCTION__); -+#endif -+ DPRINTF("Send reset signal to chip.\n"); -+ -+ ctrl = READ_REG(sc, BS_CTRL); -+ ctrl |= BS_CTRL_RESET; -+ WRITE_REG(sc, BS_CTRL, ctrl); -+ -+ /* -+ * Wait aprox. 30 PCI clocks = 900 ns = 0.9 us -+ */ -+ DELAY(10); -+} -+ -+/* -+ * Init Broadcom registers -+ */ -+void -+ubsec_init_board(struct ubsec_softc *sc) -+{ -+ u_int32_t ctrl; -+ -+#ifdef UBSEC_DEBUG -+ DPRINTF("%s()\n", __FUNCTION__); -+#endif -+ DPRINTF("Initialize chip.\n"); -+ -+ ctrl = READ_REG(sc, BS_CTRL); -+ ctrl &= ~(BS_CTRL_BE32 | BS_CTRL_BE64); -+ ctrl |= BS_CTRL_LITTLE_ENDIAN | BS_CTRL_MCR1INT | BS_CTRL_DMAERR; -+ -+ WRITE_REG(sc, BS_CTRL, ctrl); -+ -+ /* Set chip capabilities (BCM5365P) */ -+ sc->sc_flags |= UBS_FLAGS_LONGCTX | UBS_FLAGS_AES; -+} -+ -+/* -+ * Clean up after a chip crash. -+ * It is assumed that the caller has spin_lock_irq(sc_ringmtx). -+ */ -+void -+ubsec_cleanchip(struct ubsec_softc *sc) -+{ -+ struct ubsec_q *q; -+ -+#ifdef UBSEC_DEBUG -+ DPRINTF("%s()\n", __FUNCTION__); -+#endif -+ DPRINTF("Clean up queues after chip crash.\n"); -+ -+ while (!BSD_SIMPLEQ_EMPTY(&sc->sc_qchip)) { -+ q = BSD_SIMPLEQ_FIRST(&sc->sc_qchip); -+ BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q_next); -+ ubsec_free_q(sc, q); -+ } -+} -+ -+/* -+ * free a ubsec_q -+ * It is assumed that the caller has spin_lock_irq(sc_ringmtx). -+ */ -+int -+ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q) -+{ -+ struct ubsec_q *q2; -+ struct cryptop *crp; -+ int npkts; -+ int i; -+ -+#ifdef UBSEC_DEBUG -+ DPRINTF("%s()\n", __FUNCTION__); -+#endif -+ -+ npkts = q->q_nstacked_mcrs; -+ -+ for (i = 0; i < npkts; i++) { -+ if(q->q_stacked_mcr[i]) { -+ q2 = q->q_stacked_mcr[i]; -+ -+ if ((q2->q_dst_m != NULL) && (q2->q_src_m != q2->q_dst_m)) -+#ifdef NOTYET -+ m_freem(q2->q_dst_m); -+#else -+ printk(KERN_ERR "%s,%d: SKB not supported\n", __FILE__, __LINE__); -+#endif -+ -+ crp = (struct cryptop *)q2->q_crp; -+ -+ BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q2, q_next); -+ -+ crp->crp_etype = EFAULT; -+ crypto_done(crp); -+ } else { -+ break; -+ } -+ } -+ -+ /* -+ * Free header MCR -+ */ -+ if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) -+#ifdef NOTYET -+ m_freem(q->q_dst_m); -+#else -+ printk(KERN_ERR "%s,%d: SKB not supported\n", __FILE__, __LINE__); -+#endif -+ -+ crp = (struct cryptop *)q->q_crp; -+ -+ BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); -+ -+ crp->crp_etype = EFAULT; -+ crypto_done(crp); -+ return(0); -+} -+ -+/* -+ * Routine to reset the chip and clean up. -+ * It is assumed that the caller has spin_lock_irq(sc_ringmtx). -+ */ -+void -+ubsec_totalreset(struct ubsec_softc *sc) -+{ -+ -+#ifdef UBSEC_DEBUG -+ DPRINTF("%s()\n", __FUNCTION__); -+#endif -+ DPRINTF("initiate total chip reset.. \n"); -+ ubsec_reset_board(sc); -+ ubsec_init_board(sc); -+ ubsec_cleanchip(sc); -+} -+ -+void -+ubsec_dump_pb(struct ubsec_pktbuf *pb) -+{ -+ printf("addr 0x%x (0x%x) next 0x%x\n", -+ pb->pb_addr, pb->pb_len, pb->pb_next); -+} -+ -+void -+ubsec_dump_mcr(struct ubsec_mcr *mcr) -+{ -+ struct ubsec_mcr_add *ma; -+ int i; -+ -+ printf("MCR:\n"); -+ printf(" pkts: %u, flags 0x%x\n", -+ letoh16(mcr->mcr_pkts), letoh16(mcr->mcr_flags)); -+ ma = (struct ubsec_mcr_add *)&mcr->mcr_cmdctxp; -+ for (i = 0; i < letoh16(mcr->mcr_pkts); i++) { -+ printf(" %d: ctx 0x%x len 0x%x rsvd 0x%x\n", i, -+ letoh32(ma->mcr_cmdctxp), letoh16(ma->mcr_pktlen), -+ letoh16(ma->mcr_reserved)); -+ printf(" %d: ipkt ", i); -+ ubsec_dump_pb(&ma->mcr_ipktbuf); -+ printf(" %d: opkt ", i); -+ ubsec_dump_pb(&ma->mcr_opktbuf); -+ ma++; -+ } -+ printf("END MCR\n"); -+} -+ -+static int __init mod_init(void) { -+ return ssb_driver_register(&ubsec_ssb_driver); -+} -+ -+static void __exit mod_exit(void) { -+ ssb_driver_unregister(&ubsec_ssb_driver); -+} -+ -+module_init(mod_init); -+module_exit(mod_exit); -+ -+// Meta information -+MODULE_AUTHOR("Daniel Mueller "); -+MODULE_LICENSE("BSD"); -+MODULE_DESCRIPTION("OCF driver for BCM5365P IPSec Core"); -+MODULE_VERSION(DRV_MODULE_VERSION); -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/ubsec_ssb/ubsecreg.h linux-3.0.4/crypto/ocf/ubsec_ssb/ubsecreg.h ---- linux-3.0.4.orig/crypto/ocf/ubsec_ssb/ubsecreg.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/ubsec_ssb/ubsecreg.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,233 @@ -+ -+/* -+ * Copyright (c) 2008 Daniel Mueller (daniel@danm.de) -+ * Copyright (c) 2000 Theo de Raadt -+ * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com) -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored in part by the Defense Advanced Research Projects -+ * Agency (DARPA) and Air Force Research Laboratory, Air Force -+ * Materiel Command, USAF, under agreement number F30602-01-2-0537. -+ * -+ */ -+ -+/* -+ * Register definitions for 5601 BlueSteel Networks Ubiquitous Broadband -+ * Security "uBSec" chip. Definitions from revision 2.8 of the product -+ * datasheet. -+ */ -+ -+#define BS_BAR 0x10 /* DMA base address register */ -+#define BS_TRDY_TIMEOUT 0x40 /* TRDY timeout */ -+#define BS_RETRY_TIMEOUT 0x41 /* DMA retry timeout */ -+ -+#define UBS_PCI_RTY_SHIFT 8 -+#define UBS_PCI_RTY_MASK 0xff -+#define UBS_PCI_RTY(misc) \ -+ (((misc) >> UBS_PCI_RTY_SHIFT) & UBS_PCI_RTY_MASK) -+ -+#define UBS_PCI_TOUT_SHIFT 0 -+#define UBS_PCI_TOUT_MASK 0xff -+#define UBS_PCI_TOUT(misc) \ -+ (((misc) >> PCI_TOUT_SHIFT) & PCI_TOUT_MASK) -+ -+/* -+ * DMA Control & Status Registers (offset from BS_BAR) -+ */ -+#define BS_MCR1 0x20 /* DMA Master Command Record 1 */ -+#define BS_CTRL 0x24 /* DMA Control */ -+#define BS_STAT 0x28 /* DMA Status */ -+#define BS_ERR 0x2c /* DMA Error Address */ -+#define BS_DEV_ID 0x34 /* IPSec Device ID */ -+ -+/* BS_CTRL - DMA Control */ -+#define BS_CTRL_RESET 0x80000000 /* hardware reset, 5805/5820 */ -+#define BS_CTRL_MCR2INT 0x40000000 /* enable intr MCR for MCR2 */ -+#define BS_CTRL_MCR1INT 0x20000000 /* enable intr MCR for MCR1 */ -+#define BS_CTRL_OFM 0x10000000 /* Output fragment mode */ -+#define BS_CTRL_BE32 0x08000000 /* big-endian, 32bit bytes */ -+#define BS_CTRL_BE64 0x04000000 /* big-endian, 64bit bytes */ -+#define BS_CTRL_DMAERR 0x02000000 /* enable intr DMA error */ -+#define BS_CTRL_RNG_M 0x01800000 /* RNG mode */ -+#define BS_CTRL_RNG_1 0x00000000 /* 1bit rn/one slow clock */ -+#define BS_CTRL_RNG_4 0x00800000 /* 1bit rn/four slow clocks */ -+#define BS_CTRL_RNG_8 0x01000000 /* 1bit rn/eight slow clocks */ -+#define BS_CTRL_RNG_16 0x01800000 /* 1bit rn/16 slow clocks */ -+#define BS_CTRL_SWNORM 0x00400000 /* 582[01], sw normalization */ -+#define BS_CTRL_FRAG_M 0x0000ffff /* output fragment size mask */ -+#define BS_CTRL_LITTLE_ENDIAN (BS_CTRL_BE32 | BS_CTRL_BE64) -+ -+/* BS_STAT - DMA Status */ -+#define BS_STAT_MCR1_BUSY 0x80000000 /* MCR1 is busy */ -+#define BS_STAT_MCR1_FULL 0x40000000 /* MCR1 is full */ -+#define BS_STAT_MCR1_DONE 0x20000000 /* MCR1 is done */ -+#define BS_STAT_DMAERR 0x10000000 /* DMA error */ -+#define BS_STAT_MCR2_FULL 0x08000000 /* MCR2 is full */ -+#define BS_STAT_MCR2_DONE 0x04000000 /* MCR2 is done */ -+#define BS_STAT_MCR1_ALLEMPTY 0x02000000 /* 5821, MCR1 is empty */ -+#define BS_STAT_MCR2_ALLEMPTY 0x01000000 /* 5821, MCR2 is empty */ -+ -+/* BS_ERR - DMA Error Address */ -+#define BS_ERR_ADDR 0xfffffffc /* error address mask */ -+#define BS_ERR_READ 0x00000002 /* fault was on read */ -+ -+struct ubsec_pktctx { -+ u_int32_t pc_deskey[6]; /* 3DES key */ -+ u_int32_t pc_hminner[5]; /* hmac inner state */ -+ u_int32_t pc_hmouter[5]; /* hmac outer state */ -+ u_int32_t pc_iv[2]; /* [3]DES iv */ -+ u_int16_t pc_flags; /* flags, below */ -+ u_int16_t pc_offset; /* crypto offset */ -+} __attribute__ ((packed)); -+ -+#define UBS_PKTCTX_ENC_3DES 0x8000 /* use 3des */ -+#define UBS_PKTCTX_ENC_AES 0x8000 /* use aes */ -+#define UBS_PKTCTX_ENC_NONE 0x0000 /* no encryption */ -+#define UBS_PKTCTX_INBOUND 0x4000 /* inbound packet */ -+#define UBS_PKTCTX_AUTH 0x3000 /* authentication mask */ -+#define UBS_PKTCTX_AUTH_NONE 0x0000 /* no authentication */ -+#define UBS_PKTCTX_AUTH_MD5 0x1000 /* use hmac-md5 */ -+#define UBS_PKTCTX_AUTH_SHA1 0x2000 /* use hmac-sha1 */ -+#define UBS_PKTCTX_AES128 0x0 /* AES 128bit keys */ -+#define UBS_PKTCTX_AES192 0x100 /* AES 192bit keys */ -+#define UBS_PKTCTX_AES256 0x200 /* AES 256bit keys */ -+ -+struct ubsec_pktctx_des { -+ volatile u_int16_t pc_len; /* length of ctx struct */ -+ volatile u_int16_t pc_type; /* context type */ -+ volatile u_int16_t pc_flags; /* flags, same as above */ -+ volatile u_int16_t pc_offset; /* crypto/auth offset */ -+ volatile u_int32_t pc_deskey[6]; /* 3DES key */ -+ volatile u_int32_t pc_iv[2]; /* [3]DES iv */ -+ volatile u_int32_t pc_hminner[5]; /* hmac inner state */ -+ volatile u_int32_t pc_hmouter[5]; /* hmac outer state */ -+} __attribute__ ((packed)); -+ -+struct ubsec_pktctx_aes128 { -+ volatile u_int16_t pc_len; /* length of ctx struct */ -+ volatile u_int16_t pc_type; /* context type */ -+ volatile u_int16_t pc_flags; /* flags, same as above */ -+ volatile u_int16_t pc_offset; /* crypto/auth offset */ -+ volatile u_int32_t pc_aeskey[4]; /* AES 128bit key */ -+ volatile u_int32_t pc_iv[4]; /* AES iv */ -+ volatile u_int32_t pc_hminner[5]; /* hmac inner state */ -+ volatile u_int32_t pc_hmouter[5]; /* hmac outer state */ -+} __attribute__ ((packed)); -+ -+struct ubsec_pktctx_aes192 { -+ volatile u_int16_t pc_len; /* length of ctx struct */ -+ volatile u_int16_t pc_type; /* context type */ -+ volatile u_int16_t pc_flags; /* flags, same as above */ -+ volatile u_int16_t pc_offset; /* crypto/auth offset */ -+ volatile u_int32_t pc_aeskey[6]; /* AES 192bit key */ -+ volatile u_int32_t pc_iv[4]; /* AES iv */ -+ volatile u_int32_t pc_hminner[5]; /* hmac inner state */ -+ volatile u_int32_t pc_hmouter[5]; /* hmac outer state */ -+} __attribute__ ((packed)); -+ -+struct ubsec_pktctx_aes256 { -+ volatile u_int16_t pc_len; /* length of ctx struct */ -+ volatile u_int16_t pc_type; /* context type */ -+ volatile u_int16_t pc_flags; /* flags, same as above */ -+ volatile u_int16_t pc_offset; /* crypto/auth offset */ -+ volatile u_int32_t pc_aeskey[8]; /* AES 256bit key */ -+ volatile u_int32_t pc_iv[4]; /* AES iv */ -+ volatile u_int32_t pc_hminner[5]; /* hmac inner state */ -+ volatile u_int32_t pc_hmouter[5]; /* hmac outer state */ -+} __attribute__ ((packed)); -+ -+#define UBS_PKTCTX_TYPE_IPSEC_DES 0x0000 -+#define UBS_PKTCTX_TYPE_IPSEC_AES 0x0040 -+ -+struct ubsec_pktbuf { -+ volatile u_int32_t pb_addr; /* address of buffer start */ -+ volatile u_int32_t pb_next; /* pointer to next pktbuf */ -+ volatile u_int32_t pb_len; /* packet length */ -+} __attribute__ ((packed)); -+#define UBS_PKTBUF_LEN 0x0000ffff /* length mask */ -+ -+struct ubsec_mcr { -+ volatile u_int16_t mcr_pkts; /* #pkts in this mcr */ -+ volatile u_int16_t mcr_flags; /* mcr flags (below) */ -+ volatile u_int32_t mcr_cmdctxp; /* command ctx pointer */ -+ struct ubsec_pktbuf mcr_ipktbuf; /* input chain header */ -+ volatile u_int16_t mcr_reserved; -+ volatile u_int16_t mcr_pktlen; -+ struct ubsec_pktbuf mcr_opktbuf; /* output chain header */ -+} __attribute__ ((packed)); -+ -+struct ubsec_mcr_add { -+ volatile u_int32_t mcr_cmdctxp; /* command ctx pointer */ -+ struct ubsec_pktbuf mcr_ipktbuf; /* input chain header */ -+ volatile u_int16_t mcr_reserved; -+ volatile u_int16_t mcr_pktlen; -+ struct ubsec_pktbuf mcr_opktbuf; /* output chain header */ -+} __attribute__ ((packed)); -+ -+#define UBS_MCR_DONE 0x0001 /* mcr has been processed */ -+#define UBS_MCR_ERROR 0x0002 /* error in processing */ -+#define UBS_MCR_ERRORCODE 0xff00 /* error type */ -+ -+struct ubsec_ctx_keyop { -+ volatile u_int16_t ctx_len; /* command length */ -+ volatile u_int16_t ctx_op; /* operation code */ -+ volatile u_int8_t ctx_pad[60]; /* padding */ -+} __attribute__ ((packed)); -+#define UBS_CTXOP_DHPKGEN 0x01 /* dh public key generation */ -+#define UBS_CTXOP_DHSSGEN 0x02 /* dh shared secret gen. */ -+#define UBS_CTXOP_RSAPUB 0x03 /* rsa public key op */ -+#define UBS_CTXOP_RSAPRIV 0x04 /* rsa private key op */ -+#define UBS_CTXOP_DSASIGN 0x05 /* dsa signing op */ -+#define UBS_CTXOP_DSAVRFY 0x06 /* dsa verification */ -+#define UBS_CTXOP_RNGBYPASS 0x41 /* rng direct test mode */ -+#define UBS_CTXOP_RNGSHA1 0x42 /* rng sha1 test mode */ -+#define UBS_CTXOP_MODADD 0x43 /* modular addition */ -+#define UBS_CTXOP_MODSUB 0x44 /* modular subtraction */ -+#define UBS_CTXOP_MODMUL 0x45 /* modular multiplication */ -+#define UBS_CTXOP_MODRED 0x46 /* modular reduction */ -+#define UBS_CTXOP_MODEXP 0x47 /* modular exponentiation */ -+#define UBS_CTXOP_MODINV 0x48 /* modular inverse */ -+ -+struct ubsec_ctx_rngbypass { -+ volatile u_int16_t rbp_len; /* command length, 64 */ -+ volatile u_int16_t rbp_op; /* rng bypass, 0x41 */ -+ volatile u_int8_t rbp_pad[60]; /* padding */ -+} __attribute__ ((packed)); -+ -+/* modexp: C = (M ^ E) mod N */ -+struct ubsec_ctx_modexp { -+ volatile u_int16_t me_len; /* command length */ -+ volatile u_int16_t me_op; /* modexp, 0x47 */ -+ volatile u_int16_t me_E_len; /* E (bits) */ -+ volatile u_int16_t me_N_len; /* N (bits) */ -+ u_int8_t me_N[2048/8]; /* N */ -+} __attribute__ ((packed)); -+ -+struct ubsec_ctx_rsapriv { -+ volatile u_int16_t rpr_len; /* command length */ -+ volatile u_int16_t rpr_op; /* rsaprivate, 0x04 */ -+ volatile u_int16_t rpr_q_len; /* q (bits) */ -+ volatile u_int16_t rpr_p_len; /* p (bits) */ -+ u_int8_t rpr_buf[5 * 1024 / 8]; /* parameters: */ -+ /* p, q, dp, dq, pinv */ -+} __attribute__ ((packed)); -diff -Nur linux-3.0.4.orig/crypto/ocf/ubsec_ssb/ubsecvar.h linux-3.0.4/crypto/ocf/ubsec_ssb/ubsecvar.h ---- linux-3.0.4.orig/crypto/ocf/ubsec_ssb/ubsecvar.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/ubsec_ssb/ubsecvar.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,228 @@ -+ -+/* -+ * Copyright (c) 2008 Daniel Mueller (daniel@danm.de) -+ * Copyright (c) 2000 Theo de Raadt -+ * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com) -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored in part by the Defense Advanced Research Projects -+ * Agency (DARPA) and Air Force Research Laboratory, Air Force -+ * Materiel Command, USAF, under agreement number F30602-01-2-0537. -+ * -+ */ -+ -+/* Maximum queue length */ -+#ifndef UBS_MAX_NQUEUE -+#define UBS_MAX_NQUEUE 60 -+#endif -+ -+#define UBS_MAX_SCATTER 64 /* Maximum scatter/gather depth */ -+ -+#ifndef UBS_MAX_AGGR -+#define UBS_MAX_AGGR 5 /* Maximum aggregation count */ -+#endif -+ -+#define UBSEC_CARD(sid) (((sid) & 0xf0000000) >> 28) -+#define UBSEC_SESSION(sid) ( (sid) & 0x0fffffff) -+#define UBSEC_SID(crd, sesn) (((crd) << 28) | ((sesn) & 0x0fffffff)) -+ -+#define UBS_DEF_RTY 0xff /* PCI Retry Timeout */ -+#define UBS_DEF_TOUT 0xff /* PCI TRDY Timeout */ -+#define UBS_DEF_CACHELINE 0x01 /* Cache Line setting */ -+ -+#define DEFAULT_HMAC_LEN 12 -+ -+struct ubsec_dma_alloc { -+ dma_addr_t dma_paddr; -+ void *dma_vaddr; -+ /* -+ bus_dmamap_t dma_map; -+ bus_dma_segment_t dma_seg; -+ */ -+ size_t dma_size; -+ /* -+ int dma_nseg; -+ */ -+}; -+ -+struct ubsec_q2 { -+ BSD_SIMPLEQ_ENTRY(ubsec_q2) q_next; -+ struct ubsec_dma_alloc q_mcr; -+ struct ubsec_dma_alloc q_ctx; -+ u_int q_type; -+}; -+ -+struct ubsec_q2_rng { -+ struct ubsec_q2 rng_q; -+ struct ubsec_dma_alloc rng_buf; -+ int rng_used; -+}; -+ -+/* C = (M ^ E) mod N */ -+#define UBS_MODEXP_PAR_M 0 -+#define UBS_MODEXP_PAR_E 1 -+#define UBS_MODEXP_PAR_N 2 -+struct ubsec_q2_modexp { -+ struct ubsec_q2 me_q; -+ struct cryptkop * me_krp; -+ struct ubsec_dma_alloc me_M; -+ struct ubsec_dma_alloc me_E; -+ struct ubsec_dma_alloc me_C; -+ struct ubsec_dma_alloc me_epb; -+ int me_modbits; -+ int me_shiftbits; -+ int me_normbits; -+}; -+ -+#define UBS_RSAPRIV_PAR_P 0 -+#define UBS_RSAPRIV_PAR_Q 1 -+#define UBS_RSAPRIV_PAR_DP 2 -+#define UBS_RSAPRIV_PAR_DQ 3 -+#define UBS_RSAPRIV_PAR_PINV 4 -+#define UBS_RSAPRIV_PAR_MSGIN 5 -+#define UBS_RSAPRIV_PAR_MSGOUT 6 -+struct ubsec_q2_rsapriv { -+ struct ubsec_q2 rpr_q; -+ struct cryptkop * rpr_krp; -+ struct ubsec_dma_alloc rpr_msgin; -+ struct ubsec_dma_alloc rpr_msgout; -+}; -+ -+#define UBSEC_RNG_BUFSIZ 16 /* measured in 32bit words */ -+ -+struct ubsec_dmachunk { -+ struct ubsec_mcr d_mcr; -+ struct ubsec_mcr_add d_mcradd[UBS_MAX_AGGR-1]; -+ struct ubsec_pktbuf d_sbuf[UBS_MAX_SCATTER-1]; -+ struct ubsec_pktbuf d_dbuf[UBS_MAX_SCATTER-1]; -+ u_int32_t d_macbuf[5]; -+ union { -+ struct ubsec_pktctx_aes256 ctxaes256; -+ struct ubsec_pktctx_aes192 ctxaes192; -+ struct ubsec_pktctx_des ctxdes; -+ struct ubsec_pktctx_aes128 ctxaes128; -+ struct ubsec_pktctx ctx; -+ } d_ctx; -+}; -+ -+struct ubsec_dma { -+ BSD_SIMPLEQ_ENTRY(ubsec_dma) d_next; -+ struct ubsec_dmachunk *d_dma; -+ struct ubsec_dma_alloc d_alloc; -+}; -+ -+#define UBS_FLAGS_KEY 0x01 /* has key accelerator */ -+#define UBS_FLAGS_LONGCTX 0x02 /* uses long ipsec ctx */ -+#define UBS_FLAGS_BIGKEY 0x04 /* 2048bit keys */ -+#define UBS_FLAGS_HWNORM 0x08 /* hardware normalization */ -+#define UBS_FLAGS_RNG 0x10 /* hardware rng */ -+#define UBS_FLAGS_AES 0x20 /* hardware AES support */ -+ -+struct ubsec_q { -+ BSD_SIMPLEQ_ENTRY(ubsec_q) q_next; -+ int q_nstacked_mcrs; -+ struct ubsec_q *q_stacked_mcr[UBS_MAX_AGGR-1]; -+ struct cryptop *q_crp; -+ struct ubsec_dma *q_dma; -+ -+ //struct mbuf *q_src_m, *q_dst_m; -+ struct sk_buff *q_src_m, *q_dst_m; -+ struct uio *q_src_io, *q_dst_io; -+ -+ /* -+ bus_dmamap_t q_src_map; -+ bus_dmamap_t q_dst_map; -+ */ -+ -+ /* DMA addresses for In-/Out packages */ -+ int q_src_len; -+ int q_dst_len; -+ struct ubsec_dma_alloc q_src_map[UBS_MAX_SCATTER]; -+ struct ubsec_dma_alloc q_dst_map[UBS_MAX_SCATTER]; -+ int q_has_dst; -+ -+ int q_sesn; -+ int q_flags; -+}; -+ -+struct ubsec_softc { -+ softc_device_decl sc_dev; -+ struct ssb_device *sdev; /* device backpointer */ -+ -+ struct device *sc_dv; /* generic device */ -+ void *sc_ih; /* interrupt handler cookie */ -+ int sc_flags; /* device specific flags */ -+ u_int32_t sc_statmask; /* interrupt status mask */ -+ int32_t sc_cid; /* crypto tag */ -+ BSD_SIMPLEQ_HEAD(,ubsec_q) sc_queue; /* packet queue, mcr1 */ -+ int sc_nqueue; /* count enqueued, mcr1 */ -+ BSD_SIMPLEQ_HEAD(,ubsec_q) sc_qchip; /* on chip, mcr1 */ -+ BSD_SIMPLEQ_HEAD(,ubsec_q) sc_freequeue; /* list of free queue elements */ -+ BSD_SIMPLEQ_HEAD(,ubsec_q2) sc_queue2; /* packet queue, mcr2 */ -+ int sc_nqueue2; /* count enqueued, mcr2 */ -+ BSD_SIMPLEQ_HEAD(,ubsec_q2) sc_qchip2; /* on chip, mcr2 */ -+ int sc_nsessions; /* # of sessions */ -+ struct ubsec_session *sc_sessions; /* sessions */ -+ int sc_rnghz; /* rng poll time */ -+ struct ubsec_q2_rng sc_rng; -+ struct ubsec_dma sc_dmaa[UBS_MAX_NQUEUE]; -+ struct ubsec_q *sc_queuea[UBS_MAX_NQUEUE]; -+ BSD_SIMPLEQ_HEAD(,ubsec_q2) sc_q2free; /* free list */ -+ spinlock_t sc_ringmtx; /* PE ring lock */ -+}; -+ -+#define UBSEC_QFLAGS_COPYOUTIV 0x1 -+ -+struct ubsec_session { -+ u_int32_t ses_used; -+ u_int32_t ses_key[8]; /* 3DES/AES key */ -+ u_int32_t ses_hminner[5]; /* hmac inner state */ -+ u_int32_t ses_hmouter[5]; /* hmac outer state */ -+ u_int32_t ses_iv[4]; /* [3]DES/AES iv */ -+ u_int32_t ses_keysize; /* AES key size */ -+ u_int32_t ses_mlen; /* hmac/hash length */ -+}; -+ -+struct ubsec_stats { -+ u_int64_t hst_ibytes; -+ u_int64_t hst_obytes; -+ u_int32_t hst_ipackets; -+ u_int32_t hst_opackets; -+ u_int32_t hst_invalid; -+ u_int32_t hst_nomem; -+ u_int32_t hst_queuefull; -+ u_int32_t hst_dmaerr; -+ u_int32_t hst_mcrerr; -+ u_int32_t hst_nodmafree; -+}; -+ -+struct ubsec_generic_ctx { -+ u_int32_t pc_key[8]; /* [3]DES/AES key */ -+ u_int32_t pc_hminner[5]; /* hmac inner state */ -+ u_int32_t pc_hmouter[5]; /* hmac outer state */ -+ u_int32_t pc_iv[4]; /* [3]DES/AES iv */ -+ u_int16_t pc_flags; /* flags, below */ -+ u_int16_t pc_offset; /* crypto offset */ -+ u_int16_t pc_type; /* Cryptographic operation */ -+}; -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/uio.h linux-3.0.4/crypto/ocf/uio.h ---- linux-3.0.4.orig/crypto/ocf/uio.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/uio.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,54 @@ -+#ifndef _OCF_UIO_H_ -+#define _OCF_UIO_H_ -+ -+#include -+ -+/* -+ * The linux uio.h doesn't have all we need. To be fully api compatible -+ * with the BSD cryptodev, we need to keep this around. Perhaps this can -+ * be moved back into the linux/uio.h -+ * -+ * Linux port done by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * ALTERNATIVELY, provided that this notice is retained in full, this product -+ * may be distributed under the terms of the GNU General Public License (GPL), -+ * in which case the provisions of the GPL apply INSTEAD OF those given above. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ * --------------------------------------------------------------------------- -+ */ -+ -+struct uio { -+ struct iovec *uio_iov; -+ int uio_iovcnt; -+ off_t uio_offset; -+ int uio_resid; -+#if 0 -+ enum uio_seg uio_segflg; -+ enum uio_rw uio_rw; -+ struct thread *uio_td; -+#endif -+}; -+ -+#endif -diff -Nur linux-3.0.4.orig/drivers/char/random.c linux-3.0.4/drivers/char/random.c ---- linux-3.0.4.orig/drivers/char/random.c 2011-08-29 22:56:30.000000000 +0200 -+++ linux-3.0.4/drivers/char/random.c 2011-10-17 04:36:27.356574299 +0200 -@@ -130,6 +130,9 @@ - * void add_interrupt_randomness(int irq); - * void add_disk_randomness(struct gendisk *disk); - * -+ * void random_input_words(__u32 *buf, size_t wordcount, int ent_count) -+ * int random_input_wait(void); -+ * - * add_input_randomness() uses the input layer interrupt timing, as well as - * the event type information from the hardware. - * -@@ -147,6 +150,13 @@ - * seek times do not make for good sources of entropy, as their seek - * times are usually fairly consistent. - * -+ * random_input_words() just provides a raw block of entropy to the input -+ * pool, such as from a hardware entropy generator. -+ * -+ * random_input_wait() suspends the caller until such time as the -+ * entropy pool falls below the write threshold, and returns a count of how -+ * much entropy (in bits) is needed to sustain the pool. -+ * - * All of these routines try to estimate how many bits of randomness a - * particular randomness source. They do this by keeping track of the - * first and second order deltas of the event timings. -@@ -722,6 +732,63 @@ - } - #endif - -+/* -+ * random_input_words - add bulk entropy to pool -+ * -+ * @buf: buffer to add -+ * @wordcount: number of __u32 words to add -+ * @ent_count: total amount of entropy (in bits) to credit -+ * -+ * this provides bulk input of entropy to the input pool -+ * -+ */ -+void random_input_words(__u32 *buf, size_t wordcount, int ent_count) -+{ -+ mix_pool_bytes(&input_pool, buf, wordcount*4); -+ -+ credit_entropy_bits(&input_pool, ent_count); -+ -+ DEBUG_ENT("crediting %d bits => %d\n", -+ ent_count, input_pool.entropy_count); -+ /* -+ * Wake up waiting processes if we have enough -+ * entropy. -+ */ -+ if (input_pool.entropy_count >= random_read_wakeup_thresh) -+ wake_up_interruptible(&random_read_wait); -+} -+EXPORT_SYMBOL(random_input_words); -+ -+/* -+ * random_input_wait - wait until random needs entropy -+ * -+ * this function sleeps until the /dev/random subsystem actually -+ * needs more entropy, and then return the amount of entropy -+ * that it would be nice to have added to the system. -+ */ -+int random_input_wait(void) -+{ -+ int count; -+ -+ wait_event_interruptible(random_write_wait, -+ input_pool.entropy_count < random_write_wakeup_thresh); -+ -+ count = random_write_wakeup_thresh - input_pool.entropy_count; -+ -+ /* likely we got woken up due to a signal */ -+ if (count <= 0) count = random_read_wakeup_thresh; -+ -+ DEBUG_ENT("requesting %d bits from input_wait()er %d<%d\n", -+ count, -+ input_pool.entropy_count, random_write_wakeup_thresh); -+ -+ return count; -+} -+EXPORT_SYMBOL(random_input_wait); -+ -+ -+#define EXTRACT_SIZE 10 -+ - /********************************************************************* - * - * Entropy extraction routines -diff -Nur linux-3.0.4.orig/drivers/char/random.c.orig linux-3.0.4/drivers/char/random.c.orig ---- linux-3.0.4.orig/drivers/char/random.c.orig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/drivers/char/random.c.orig 2011-08-29 22:56:30.000000000 +0200 -@@ -0,0 +1,1349 @@ -+/* -+ * random.c -- A strong random number generator -+ * -+ * Copyright Matt Mackall , 2003, 2004, 2005 -+ * -+ * Copyright Theodore Ts'o, 1994, 1995, 1996, 1997, 1998, 1999. All -+ * rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, and the entire permission notice in its entirety, -+ * including the disclaimer of warranties. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote -+ * products derived from this software without specific prior -+ * written permission. -+ * -+ * ALTERNATIVELY, this product may be distributed under the terms of -+ * the GNU General Public License, in which case the provisions of the GPL are -+ * required INSTEAD OF the above restrictions. (This clause is -+ * necessary due to a potential bad interaction between the GPL and -+ * the restrictions contained in a BSD-style copyright.) -+ * -+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED -+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ALL OF -+ * WHICH ARE HEREBY DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT -+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE -+ * USE OF THIS SOFTWARE, EVEN IF NOT ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ */ -+ -+/* -+ * (now, with legal B.S. out of the way.....) -+ * -+ * This routine gathers environmental noise from device drivers, etc., -+ * and returns good random numbers, suitable for cryptographic use. -+ * Besides the obvious cryptographic uses, these numbers are also good -+ * for seeding TCP sequence numbers, and other places where it is -+ * desirable to have numbers which are not only random, but hard to -+ * predict by an attacker. -+ * -+ * Theory of operation -+ * =================== -+ * -+ * Computers are very predictable devices. Hence it is extremely hard -+ * to produce truly random numbers on a computer --- as opposed to -+ * pseudo-random numbers, which can easily generated by using a -+ * algorithm. Unfortunately, it is very easy for attackers to guess -+ * the sequence of pseudo-random number generators, and for some -+ * applications this is not acceptable. So instead, we must try to -+ * gather "environmental noise" from the computer's environment, which -+ * must be hard for outside attackers to observe, and use that to -+ * generate random numbers. In a Unix environment, this is best done -+ * from inside the kernel. -+ * -+ * Sources of randomness from the environment include inter-keyboard -+ * timings, inter-interrupt timings from some interrupts, and other -+ * events which are both (a) non-deterministic and (b) hard for an -+ * outside observer to measure. Randomness from these sources are -+ * added to an "entropy pool", which is mixed using a CRC-like function. -+ * This is not cryptographically strong, but it is adequate assuming -+ * the randomness is not chosen maliciously, and it is fast enough that -+ * the overhead of doing it on every interrupt is very reasonable. -+ * As random bytes are mixed into the entropy pool, the routines keep -+ * an *estimate* of how many bits of randomness have been stored into -+ * the random number generator's internal state. -+ * -+ * When random bytes are desired, they are obtained by taking the SHA -+ * hash of the contents of the "entropy pool". The SHA hash avoids -+ * exposing the internal state of the entropy pool. It is believed to -+ * be computationally infeasible to derive any useful information -+ * about the input of SHA from its output. Even if it is possible to -+ * analyze SHA in some clever way, as long as the amount of data -+ * returned from the generator is less than the inherent entropy in -+ * the pool, the output data is totally unpredictable. For this -+ * reason, the routine decreases its internal estimate of how many -+ * bits of "true randomness" are contained in the entropy pool as it -+ * outputs random numbers. -+ * -+ * If this estimate goes to zero, the routine can still generate -+ * random numbers; however, an attacker may (at least in theory) be -+ * able to infer the future output of the generator from prior -+ * outputs. This requires successful cryptanalysis of SHA, which is -+ * not believed to be feasible, but there is a remote possibility. -+ * Nonetheless, these numbers should be useful for the vast majority -+ * of purposes. -+ * -+ * Exported interfaces ---- output -+ * =============================== -+ * -+ * There are three exported interfaces; the first is one designed to -+ * be used from within the kernel: -+ * -+ * void get_random_bytes(void *buf, int nbytes); -+ * -+ * This interface will return the requested number of random bytes, -+ * and place it in the requested buffer. -+ * -+ * The two other interfaces are two character devices /dev/random and -+ * /dev/urandom. /dev/random is suitable for use when very high -+ * quality randomness is desired (for example, for key generation or -+ * one-time pads), as it will only return a maximum of the number of -+ * bits of randomness (as estimated by the random number generator) -+ * contained in the entropy pool. -+ * -+ * The /dev/urandom device does not have this limit, and will return -+ * as many bytes as are requested. As more and more random bytes are -+ * requested without giving time for the entropy pool to recharge, -+ * this will result in random numbers that are merely cryptographically -+ * strong. For many applications, however, this is acceptable. -+ * -+ * Exported interfaces ---- input -+ * ============================== -+ * -+ * The current exported interfaces for gathering environmental noise -+ * from the devices are: -+ * -+ * void add_input_randomness(unsigned int type, unsigned int code, -+ * unsigned int value); -+ * void add_interrupt_randomness(int irq); -+ * void add_disk_randomness(struct gendisk *disk); -+ * -+ * add_input_randomness() uses the input layer interrupt timing, as well as -+ * the event type information from the hardware. -+ * -+ * add_interrupt_randomness() uses the inter-interrupt timing as random -+ * inputs to the entropy pool. Note that not all interrupts are good -+ * sources of randomness! For example, the timer interrupts is not a -+ * good choice, because the periodicity of the interrupts is too -+ * regular, and hence predictable to an attacker. Network Interface -+ * Controller interrupts are a better measure, since the timing of the -+ * NIC interrupts are more unpredictable. -+ * -+ * add_disk_randomness() uses what amounts to the seek time of block -+ * layer request events, on a per-disk_devt basis, as input to the -+ * entropy pool. Note that high-speed solid state drives with very low -+ * seek times do not make for good sources of entropy, as their seek -+ * times are usually fairly consistent. -+ * -+ * All of these routines try to estimate how many bits of randomness a -+ * particular randomness source. They do this by keeping track of the -+ * first and second order deltas of the event timings. -+ * -+ * Ensuring unpredictability at system startup -+ * ============================================ -+ * -+ * When any operating system starts up, it will go through a sequence -+ * of actions that are fairly predictable by an adversary, especially -+ * if the start-up does not involve interaction with a human operator. -+ * This reduces the actual number of bits of unpredictability in the -+ * entropy pool below the value in entropy_count. In order to -+ * counteract this effect, it helps to carry information in the -+ * entropy pool across shut-downs and start-ups. To do this, put the -+ * following lines an appropriate script which is run during the boot -+ * sequence: -+ * -+ * echo "Initializing random number generator..." -+ * random_seed=/var/run/random-seed -+ * # Carry a random seed from start-up to start-up -+ * # Load and then save the whole entropy pool -+ * if [ -f $random_seed ]; then -+ * cat $random_seed >/dev/urandom -+ * else -+ * touch $random_seed -+ * fi -+ * chmod 600 $random_seed -+ * dd if=/dev/urandom of=$random_seed count=1 bs=512 -+ * -+ * and the following lines in an appropriate script which is run as -+ * the system is shutdown: -+ * -+ * # Carry a random seed from shut-down to start-up -+ * # Save the whole entropy pool -+ * echo "Saving random seed..." -+ * random_seed=/var/run/random-seed -+ * touch $random_seed -+ * chmod 600 $random_seed -+ * dd if=/dev/urandom of=$random_seed count=1 bs=512 -+ * -+ * For example, on most modern systems using the System V init -+ * scripts, such code fragments would be found in -+ * /etc/rc.d/init.d/random. On older Linux systems, the correct script -+ * location might be in /etc/rcb.d/rc.local or /etc/rc.d/rc.0. -+ * -+ * Effectively, these commands cause the contents of the entropy pool -+ * to be saved at shut-down time and reloaded into the entropy pool at -+ * start-up. (The 'dd' in the addition to the bootup script is to -+ * make sure that /etc/random-seed is different for every start-up, -+ * even if the system crashes without executing rc.0.) Even with -+ * complete knowledge of the start-up activities, predicting the state -+ * of the entropy pool requires knowledge of the previous history of -+ * the system. -+ * -+ * Configuring the /dev/random driver under Linux -+ * ============================================== -+ * -+ * The /dev/random driver under Linux uses minor numbers 8 and 9 of -+ * the /dev/mem major number (#1). So if your system does not have -+ * /dev/random and /dev/urandom created already, they can be created -+ * by using the commands: -+ * -+ * mknod /dev/random c 1 8 -+ * mknod /dev/urandom c 1 9 -+ * -+ * Acknowledgements: -+ * ================= -+ * -+ * Ideas for constructing this random number generator were derived -+ * from Pretty Good Privacy's random number generator, and from private -+ * discussions with Phil Karn. Colin Plumb provided a faster random -+ * number generator, which speed up the mixing function of the entropy -+ * pool, taken from PGPfone. Dale Worley has also contributed many -+ * useful ideas and suggestions to improve this driver. -+ * -+ * Any flaws in the design are solely my responsibility, and should -+ * not be attributed to the Phil, Colin, or any of authors of PGP. -+ * -+ * Further background information on this topic may be obtained from -+ * RFC 1750, "Randomness Recommendations for Security", by Donald -+ * Eastlake, Steve Crocker, and Jeff Schiller. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#ifdef CONFIG_GENERIC_HARDIRQS -+# include -+#endif -+ -+#include -+#include -+#include -+#include -+ -+/* -+ * Configuration information -+ */ -+#define INPUT_POOL_WORDS 128 -+#define OUTPUT_POOL_WORDS 32 -+#define SEC_XFER_SIZE 512 -+#define EXTRACT_SIZE 10 -+ -+/* -+ * The minimum number of bits of entropy before we wake up a read on -+ * /dev/random. Should be enough to do a significant reseed. -+ */ -+static int random_read_wakeup_thresh = 64; -+ -+/* -+ * If the entropy count falls under this number of bits, then we -+ * should wake up processes which are selecting or polling on write -+ * access to /dev/random. -+ */ -+static int random_write_wakeup_thresh = 128; -+ -+/* -+ * When the input pool goes over trickle_thresh, start dropping most -+ * samples to avoid wasting CPU time and reduce lock contention. -+ */ -+ -+static int trickle_thresh __read_mostly = INPUT_POOL_WORDS * 28; -+ -+static DEFINE_PER_CPU(int, trickle_count); -+ -+/* -+ * A pool of size .poolwords is stirred with a primitive polynomial -+ * of degree .poolwords over GF(2). The taps for various sizes are -+ * defined below. They are chosen to be evenly spaced (minimum RMS -+ * distance from evenly spaced; the numbers in the comments are a -+ * scaled squared error sum) except for the last tap, which is 1 to -+ * get the twisting happening as fast as possible. -+ */ -+static struct poolinfo { -+ int poolwords; -+ int tap1, tap2, tap3, tap4, tap5; -+} poolinfo_table[] = { -+ /* x^128 + x^103 + x^76 + x^51 +x^25 + x + 1 -- 105 */ -+ { 128, 103, 76, 51, 25, 1 }, -+ /* x^32 + x^26 + x^20 + x^14 + x^7 + x + 1 -- 15 */ -+ { 32, 26, 20, 14, 7, 1 }, -+#if 0 -+ /* x^2048 + x^1638 + x^1231 + x^819 + x^411 + x + 1 -- 115 */ -+ { 2048, 1638, 1231, 819, 411, 1 }, -+ -+ /* x^1024 + x^817 + x^615 + x^412 + x^204 + x + 1 -- 290 */ -+ { 1024, 817, 615, 412, 204, 1 }, -+ -+ /* x^1024 + x^819 + x^616 + x^410 + x^207 + x^2 + 1 -- 115 */ -+ { 1024, 819, 616, 410, 207, 2 }, -+ -+ /* x^512 + x^411 + x^308 + x^208 + x^104 + x + 1 -- 225 */ -+ { 512, 411, 308, 208, 104, 1 }, -+ -+ /* x^512 + x^409 + x^307 + x^206 + x^102 + x^2 + 1 -- 95 */ -+ { 512, 409, 307, 206, 102, 2 }, -+ /* x^512 + x^409 + x^309 + x^205 + x^103 + x^2 + 1 -- 95 */ -+ { 512, 409, 309, 205, 103, 2 }, -+ -+ /* x^256 + x^205 + x^155 + x^101 + x^52 + x + 1 -- 125 */ -+ { 256, 205, 155, 101, 52, 1 }, -+ -+ /* x^128 + x^103 + x^78 + x^51 + x^27 + x^2 + 1 -- 70 */ -+ { 128, 103, 78, 51, 27, 2 }, -+ -+ /* x^64 + x^52 + x^39 + x^26 + x^14 + x + 1 -- 15 */ -+ { 64, 52, 39, 26, 14, 1 }, -+#endif -+}; -+ -+#define POOLBITS poolwords*32 -+#define POOLBYTES poolwords*4 -+ -+/* -+ * For the purposes of better mixing, we use the CRC-32 polynomial as -+ * well to make a twisted Generalized Feedback Shift Reigster -+ * -+ * (See M. Matsumoto & Y. Kurita, 1992. Twisted GFSR generators. ACM -+ * Transactions on Modeling and Computer Simulation 2(3):179-194. -+ * Also see M. Matsumoto & Y. Kurita, 1994. Twisted GFSR generators -+ * II. ACM Transactions on Mdeling and Computer Simulation 4:254-266) -+ * -+ * Thanks to Colin Plumb for suggesting this. -+ * -+ * We have not analyzed the resultant polynomial to prove it primitive; -+ * in fact it almost certainly isn't. Nonetheless, the irreducible factors -+ * of a random large-degree polynomial over GF(2) are more than large enough -+ * that periodicity is not a concern. -+ * -+ * The input hash is much less sensitive than the output hash. All -+ * that we want of it is that it be a good non-cryptographic hash; -+ * i.e. it not produce collisions when fed "random" data of the sort -+ * we expect to see. As long as the pool state differs for different -+ * inputs, we have preserved the input entropy and done a good job. -+ * The fact that an intelligent attacker can construct inputs that -+ * will produce controlled alterations to the pool's state is not -+ * important because we don't consider such inputs to contribute any -+ * randomness. The only property we need with respect to them is that -+ * the attacker can't increase his/her knowledge of the pool's state. -+ * Since all additions are reversible (knowing the final state and the -+ * input, you can reconstruct the initial state), if an attacker has -+ * any uncertainty about the initial state, he/she can only shuffle -+ * that uncertainty about, but never cause any collisions (which would -+ * decrease the uncertainty). -+ * -+ * The chosen system lets the state of the pool be (essentially) the input -+ * modulo the generator polymnomial. Now, for random primitive polynomials, -+ * this is a universal class of hash functions, meaning that the chance -+ * of a collision is limited by the attacker's knowledge of the generator -+ * polynomail, so if it is chosen at random, an attacker can never force -+ * a collision. Here, we use a fixed polynomial, but we *can* assume that -+ * ###--> it is unknown to the processes generating the input entropy. <-### -+ * Because of this important property, this is a good, collision-resistant -+ * hash; hash collisions will occur no more often than chance. -+ */ -+ -+/* -+ * Static global variables -+ */ -+static DECLARE_WAIT_QUEUE_HEAD(random_read_wait); -+static DECLARE_WAIT_QUEUE_HEAD(random_write_wait); -+static struct fasync_struct *fasync; -+ -+#if 0 -+static int debug; -+module_param(debug, bool, 0644); -+#define DEBUG_ENT(fmt, arg...) do { \ -+ if (debug) \ -+ printk(KERN_DEBUG "random %04d %04d %04d: " \ -+ fmt,\ -+ input_pool.entropy_count,\ -+ blocking_pool.entropy_count,\ -+ nonblocking_pool.entropy_count,\ -+ ## arg); } while (0) -+#else -+#define DEBUG_ENT(fmt, arg...) do {} while (0) -+#endif -+ -+/********************************************************************** -+ * -+ * OS independent entropy store. Here are the functions which handle -+ * storing entropy in an entropy pool. -+ * -+ **********************************************************************/ -+ -+struct entropy_store; -+struct entropy_store { -+ /* read-only data: */ -+ struct poolinfo *poolinfo; -+ __u32 *pool; -+ const char *name; -+ struct entropy_store *pull; -+ int limit; -+ -+ /* read-write data: */ -+ spinlock_t lock; -+ unsigned add_ptr; -+ int entropy_count; -+ int input_rotate; -+ __u8 last_data[EXTRACT_SIZE]; -+}; -+ -+static __u32 input_pool_data[INPUT_POOL_WORDS]; -+static __u32 blocking_pool_data[OUTPUT_POOL_WORDS]; -+static __u32 nonblocking_pool_data[OUTPUT_POOL_WORDS]; -+ -+static struct entropy_store input_pool = { -+ .poolinfo = &poolinfo_table[0], -+ .name = "input", -+ .limit = 1, -+ .lock = __SPIN_LOCK_UNLOCKED(&input_pool.lock), -+ .pool = input_pool_data -+}; -+ -+static struct entropy_store blocking_pool = { -+ .poolinfo = &poolinfo_table[1], -+ .name = "blocking", -+ .limit = 1, -+ .pull = &input_pool, -+ .lock = __SPIN_LOCK_UNLOCKED(&blocking_pool.lock), -+ .pool = blocking_pool_data -+}; -+ -+static struct entropy_store nonblocking_pool = { -+ .poolinfo = &poolinfo_table[1], -+ .name = "nonblocking", -+ .pull = &input_pool, -+ .lock = __SPIN_LOCK_UNLOCKED(&nonblocking_pool.lock), -+ .pool = nonblocking_pool_data -+}; -+ -+/* -+ * This function adds bytes into the entropy "pool". It does not -+ * update the entropy estimate. The caller should call -+ * credit_entropy_bits if this is appropriate. -+ * -+ * The pool is stirred with a primitive polynomial of the appropriate -+ * degree, and then twisted. We twist by three bits at a time because -+ * it's cheap to do so and helps slightly in the expected case where -+ * the entropy is concentrated in the low-order bits. -+ */ -+static void mix_pool_bytes_extract(struct entropy_store *r, const void *in, -+ int nbytes, __u8 out[64]) -+{ -+ static __u32 const twist_table[8] = { -+ 0x00000000, 0x3b6e20c8, 0x76dc4190, 0x4db26158, -+ 0xedb88320, 0xd6d6a3e8, 0x9b64c2b0, 0xa00ae278 }; -+ unsigned long i, j, tap1, tap2, tap3, tap4, tap5; -+ int input_rotate; -+ int wordmask = r->poolinfo->poolwords - 1; -+ const char *bytes = in; -+ __u32 w; -+ unsigned long flags; -+ -+ /* Taps are constant, so we can load them without holding r->lock. */ -+ tap1 = r->poolinfo->tap1; -+ tap2 = r->poolinfo->tap2; -+ tap3 = r->poolinfo->tap3; -+ tap4 = r->poolinfo->tap4; -+ tap5 = r->poolinfo->tap5; -+ -+ spin_lock_irqsave(&r->lock, flags); -+ input_rotate = r->input_rotate; -+ i = r->add_ptr; -+ -+ /* mix one byte at a time to simplify size handling and churn faster */ -+ while (nbytes--) { -+ w = rol32(*bytes++, input_rotate & 31); -+ i = (i - 1) & wordmask; -+ -+ /* XOR in the various taps */ -+ w ^= r->pool[i]; -+ w ^= r->pool[(i + tap1) & wordmask]; -+ w ^= r->pool[(i + tap2) & wordmask]; -+ w ^= r->pool[(i + tap3) & wordmask]; -+ w ^= r->pool[(i + tap4) & wordmask]; -+ w ^= r->pool[(i + tap5) & wordmask]; -+ -+ /* Mix the result back in with a twist */ -+ r->pool[i] = (w >> 3) ^ twist_table[w & 7]; -+ -+ /* -+ * Normally, we add 7 bits of rotation to the pool. -+ * At the beginning of the pool, add an extra 7 bits -+ * rotation, so that successive passes spread the -+ * input bits across the pool evenly. -+ */ -+ input_rotate += i ? 7 : 14; -+ } -+ -+ r->input_rotate = input_rotate; -+ r->add_ptr = i; -+ -+ if (out) -+ for (j = 0; j < 16; j++) -+ ((__u32 *)out)[j] = r->pool[(i - j) & wordmask]; -+ -+ spin_unlock_irqrestore(&r->lock, flags); -+} -+ -+static void mix_pool_bytes(struct entropy_store *r, const void *in, int bytes) -+{ -+ mix_pool_bytes_extract(r, in, bytes, NULL); -+} -+ -+/* -+ * Credit (or debit) the entropy store with n bits of entropy -+ */ -+static void credit_entropy_bits(struct entropy_store *r, int nbits) -+{ -+ unsigned long flags; -+ int entropy_count; -+ -+ if (!nbits) -+ return; -+ -+ spin_lock_irqsave(&r->lock, flags); -+ -+ DEBUG_ENT("added %d entropy credits to %s\n", nbits, r->name); -+ entropy_count = r->entropy_count; -+ entropy_count += nbits; -+ if (entropy_count < 0) { -+ DEBUG_ENT("negative entropy/overflow\n"); -+ entropy_count = 0; -+ } else if (entropy_count > r->poolinfo->POOLBITS) -+ entropy_count = r->poolinfo->POOLBITS; -+ r->entropy_count = entropy_count; -+ -+ /* should we wake readers? */ -+ if (r == &input_pool && entropy_count >= random_read_wakeup_thresh) { -+ wake_up_interruptible(&random_read_wait); -+ kill_fasync(&fasync, SIGIO, POLL_IN); -+ } -+ spin_unlock_irqrestore(&r->lock, flags); -+} -+ -+/********************************************************************* -+ * -+ * Entropy input management -+ * -+ *********************************************************************/ -+ -+/* There is one of these per entropy source */ -+struct timer_rand_state { -+ cycles_t last_time; -+ long last_delta, last_delta2; -+ unsigned dont_count_entropy:1; -+}; -+ -+#ifndef CONFIG_GENERIC_HARDIRQS -+ -+static struct timer_rand_state *irq_timer_state[NR_IRQS]; -+ -+static struct timer_rand_state *get_timer_rand_state(unsigned int irq) -+{ -+ return irq_timer_state[irq]; -+} -+ -+static void set_timer_rand_state(unsigned int irq, -+ struct timer_rand_state *state) -+{ -+ irq_timer_state[irq] = state; -+} -+ -+#else -+ -+static struct timer_rand_state *get_timer_rand_state(unsigned int irq) -+{ -+ struct irq_desc *desc; -+ -+ desc = irq_to_desc(irq); -+ -+ return desc->timer_rand_state; -+} -+ -+static void set_timer_rand_state(unsigned int irq, -+ struct timer_rand_state *state) -+{ -+ struct irq_desc *desc; -+ -+ desc = irq_to_desc(irq); -+ -+ desc->timer_rand_state = state; -+} -+#endif -+ -+static struct timer_rand_state input_timer_state; -+ -+/* -+ * This function adds entropy to the entropy "pool" by using timing -+ * delays. It uses the timer_rand_state structure to make an estimate -+ * of how many bits of entropy this call has added to the pool. -+ * -+ * The number "num" is also added to the pool - it should somehow describe -+ * the type of event which just happened. This is currently 0-255 for -+ * keyboard scan codes, and 256 upwards for interrupts. -+ * -+ */ -+static void add_timer_randomness(struct timer_rand_state *state, unsigned num) -+{ -+ struct { -+ cycles_t cycles; -+ long jiffies; -+ unsigned num; -+ } sample; -+ long delta, delta2, delta3; -+ -+ preempt_disable(); -+ /* if over the trickle threshold, use only 1 in 4096 samples */ -+ if (input_pool.entropy_count > trickle_thresh && -+ ((__this_cpu_inc_return(trickle_count) - 1) & 0xfff)) -+ goto out; -+ -+ sample.jiffies = jiffies; -+ sample.cycles = get_cycles(); -+ sample.num = num; -+ mix_pool_bytes(&input_pool, &sample, sizeof(sample)); -+ -+ /* -+ * Calculate number of bits of randomness we probably added. -+ * We take into account the first, second and third-order deltas -+ * in order to make our estimate. -+ */ -+ -+ if (!state->dont_count_entropy) { -+ delta = sample.jiffies - state->last_time; -+ state->last_time = sample.jiffies; -+ -+ delta2 = delta - state->last_delta; -+ state->last_delta = delta; -+ -+ delta3 = delta2 - state->last_delta2; -+ state->last_delta2 = delta2; -+ -+ if (delta < 0) -+ delta = -delta; -+ if (delta2 < 0) -+ delta2 = -delta2; -+ if (delta3 < 0) -+ delta3 = -delta3; -+ if (delta > delta2) -+ delta = delta2; -+ if (delta > delta3) -+ delta = delta3; -+ -+ /* -+ * delta is now minimum absolute delta. -+ * Round down by 1 bit on general principles, -+ * and limit entropy entimate to 12 bits. -+ */ -+ credit_entropy_bits(&input_pool, -+ min_t(int, fls(delta>>1), 11)); -+ } -+out: -+ preempt_enable(); -+} -+ -+void add_input_randomness(unsigned int type, unsigned int code, -+ unsigned int value) -+{ -+ static unsigned char last_value; -+ -+ /* ignore autorepeat and the like */ -+ if (value == last_value) -+ return; -+ -+ DEBUG_ENT("input event\n"); -+ last_value = value; -+ add_timer_randomness(&input_timer_state, -+ (type << 4) ^ code ^ (code >> 4) ^ value); -+} -+EXPORT_SYMBOL_GPL(add_input_randomness); -+ -+void add_interrupt_randomness(int irq) -+{ -+ struct timer_rand_state *state; -+ -+ state = get_timer_rand_state(irq); -+ -+ if (state == NULL) -+ return; -+ -+ DEBUG_ENT("irq event %d\n", irq); -+ add_timer_randomness(state, 0x100 + irq); -+} -+ -+#ifdef CONFIG_BLOCK -+void add_disk_randomness(struct gendisk *disk) -+{ -+ if (!disk || !disk->random) -+ return; -+ /* first major is 1, so we get >= 0x200 here */ -+ DEBUG_ENT("disk event %d:%d\n", -+ MAJOR(disk_devt(disk)), MINOR(disk_devt(disk))); -+ -+ add_timer_randomness(disk->random, 0x100 + disk_devt(disk)); -+} -+#endif -+ -+/********************************************************************* -+ * -+ * Entropy extraction routines -+ * -+ *********************************************************************/ -+ -+static ssize_t extract_entropy(struct entropy_store *r, void *buf, -+ size_t nbytes, int min, int rsvd); -+ -+/* -+ * This utility inline function is responsible for transferring entropy -+ * from the primary pool to the secondary extraction pool. We make -+ * sure we pull enough for a 'catastrophic reseed'. -+ */ -+static void xfer_secondary_pool(struct entropy_store *r, size_t nbytes) -+{ -+ __u32 tmp[OUTPUT_POOL_WORDS]; -+ -+ if (r->pull && r->entropy_count < nbytes * 8 && -+ r->entropy_count < r->poolinfo->POOLBITS) { -+ /* If we're limited, always leave two wakeup worth's BITS */ -+ int rsvd = r->limit ? 0 : random_read_wakeup_thresh/4; -+ int bytes = nbytes; -+ -+ /* pull at least as many as BYTES as wakeup BITS */ -+ bytes = max_t(int, bytes, random_read_wakeup_thresh / 8); -+ /* but never more than the buffer size */ -+ bytes = min_t(int, bytes, sizeof(tmp)); -+ -+ DEBUG_ENT("going to reseed %s with %d bits " -+ "(%d of %d requested)\n", -+ r->name, bytes * 8, nbytes * 8, r->entropy_count); -+ -+ bytes = extract_entropy(r->pull, tmp, bytes, -+ random_read_wakeup_thresh / 8, rsvd); -+ mix_pool_bytes(r, tmp, bytes); -+ credit_entropy_bits(r, bytes*8); -+ } -+} -+ -+/* -+ * These functions extracts randomness from the "entropy pool", and -+ * returns it in a buffer. -+ * -+ * The min parameter specifies the minimum amount we can pull before -+ * failing to avoid races that defeat catastrophic reseeding while the -+ * reserved parameter indicates how much entropy we must leave in the -+ * pool after each pull to avoid starving other readers. -+ * -+ * Note: extract_entropy() assumes that .poolwords is a multiple of 16 words. -+ */ -+ -+static size_t account(struct entropy_store *r, size_t nbytes, int min, -+ int reserved) -+{ -+ unsigned long flags; -+ -+ /* Hold lock while accounting */ -+ spin_lock_irqsave(&r->lock, flags); -+ -+ BUG_ON(r->entropy_count > r->poolinfo->POOLBITS); -+ DEBUG_ENT("trying to extract %d bits from %s\n", -+ nbytes * 8, r->name); -+ -+ /* Can we pull enough? */ -+ if (r->entropy_count / 8 < min + reserved) { -+ nbytes = 0; -+ } else { -+ /* If limited, never pull more than available */ -+ if (r->limit && nbytes + reserved >= r->entropy_count / 8) -+ nbytes = r->entropy_count/8 - reserved; -+ -+ if (r->entropy_count / 8 >= nbytes + reserved) -+ r->entropy_count -= nbytes*8; -+ else -+ r->entropy_count = reserved; -+ -+ if (r->entropy_count < random_write_wakeup_thresh) { -+ wake_up_interruptible(&random_write_wait); -+ kill_fasync(&fasync, SIGIO, POLL_OUT); -+ } -+ } -+ -+ DEBUG_ENT("debiting %d entropy credits from %s%s\n", -+ nbytes * 8, r->name, r->limit ? "" : " (unlimited)"); -+ -+ spin_unlock_irqrestore(&r->lock, flags); -+ -+ return nbytes; -+} -+ -+static void extract_buf(struct entropy_store *r, __u8 *out) -+{ -+ int i; -+ __u32 hash[5], workspace[SHA_WORKSPACE_WORDS]; -+ __u8 extract[64]; -+ -+ /* Generate a hash across the pool, 16 words (512 bits) at a time */ -+ sha_init(hash); -+ for (i = 0; i < r->poolinfo->poolwords; i += 16) -+ sha_transform(hash, (__u8 *)(r->pool + i), workspace); -+ -+ /* -+ * We mix the hash back into the pool to prevent backtracking -+ * attacks (where the attacker knows the state of the pool -+ * plus the current outputs, and attempts to find previous -+ * ouputs), unless the hash function can be inverted. By -+ * mixing at least a SHA1 worth of hash data back, we make -+ * brute-forcing the feedback as hard as brute-forcing the -+ * hash. -+ */ -+ mix_pool_bytes_extract(r, hash, sizeof(hash), extract); -+ -+ /* -+ * To avoid duplicates, we atomically extract a portion of the -+ * pool while mixing, and hash one final time. -+ */ -+ sha_transform(hash, extract, workspace); -+ memset(extract, 0, sizeof(extract)); -+ memset(workspace, 0, sizeof(workspace)); -+ -+ /* -+ * In case the hash function has some recognizable output -+ * pattern, we fold it in half. Thus, we always feed back -+ * twice as much data as we output. -+ */ -+ hash[0] ^= hash[3]; -+ hash[1] ^= hash[4]; -+ hash[2] ^= rol32(hash[2], 16); -+ memcpy(out, hash, EXTRACT_SIZE); -+ memset(hash, 0, sizeof(hash)); -+} -+ -+static ssize_t extract_entropy(struct entropy_store *r, void *buf, -+ size_t nbytes, int min, int reserved) -+{ -+ ssize_t ret = 0, i; -+ __u8 tmp[EXTRACT_SIZE]; -+ unsigned long flags; -+ -+ xfer_secondary_pool(r, nbytes); -+ nbytes = account(r, nbytes, min, reserved); -+ -+ while (nbytes) { -+ extract_buf(r, tmp); -+ -+ if (fips_enabled) { -+ spin_lock_irqsave(&r->lock, flags); -+ if (!memcmp(tmp, r->last_data, EXTRACT_SIZE)) -+ panic("Hardware RNG duplicated output!\n"); -+ memcpy(r->last_data, tmp, EXTRACT_SIZE); -+ spin_unlock_irqrestore(&r->lock, flags); -+ } -+ i = min_t(int, nbytes, EXTRACT_SIZE); -+ memcpy(buf, tmp, i); -+ nbytes -= i; -+ buf += i; -+ ret += i; -+ } -+ -+ /* Wipe data just returned from memory */ -+ memset(tmp, 0, sizeof(tmp)); -+ -+ return ret; -+} -+ -+static ssize_t extract_entropy_user(struct entropy_store *r, void __user *buf, -+ size_t nbytes) -+{ -+ ssize_t ret = 0, i; -+ __u8 tmp[EXTRACT_SIZE]; -+ -+ xfer_secondary_pool(r, nbytes); -+ nbytes = account(r, nbytes, 0, 0); -+ -+ while (nbytes) { -+ if (need_resched()) { -+ if (signal_pending(current)) { -+ if (ret == 0) -+ ret = -ERESTARTSYS; -+ break; -+ } -+ schedule(); -+ } -+ -+ extract_buf(r, tmp); -+ i = min_t(int, nbytes, EXTRACT_SIZE); -+ if (copy_to_user(buf, tmp, i)) { -+ ret = -EFAULT; -+ break; -+ } -+ -+ nbytes -= i; -+ buf += i; -+ ret += i; -+ } -+ -+ /* Wipe data just returned from memory */ -+ memset(tmp, 0, sizeof(tmp)); -+ -+ return ret; -+} -+ -+/* -+ * This function is the exported kernel interface. It returns some -+ * number of good random numbers, suitable for seeding TCP sequence -+ * numbers, etc. -+ */ -+void get_random_bytes(void *buf, int nbytes) -+{ -+ extract_entropy(&nonblocking_pool, buf, nbytes, 0, 0); -+} -+EXPORT_SYMBOL(get_random_bytes); -+ -+/* -+ * init_std_data - initialize pool with system data -+ * -+ * @r: pool to initialize -+ * -+ * This function clears the pool's entropy count and mixes some system -+ * data into the pool to prepare it for use. The pool is not cleared -+ * as that can only decrease the entropy in the pool. -+ */ -+static void init_std_data(struct entropy_store *r) -+{ -+ ktime_t now; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&r->lock, flags); -+ r->entropy_count = 0; -+ spin_unlock_irqrestore(&r->lock, flags); -+ -+ now = ktime_get_real(); -+ mix_pool_bytes(r, &now, sizeof(now)); -+ mix_pool_bytes(r, utsname(), sizeof(*(utsname()))); -+} -+ -+static int rand_initialize(void) -+{ -+ init_std_data(&input_pool); -+ init_std_data(&blocking_pool); -+ init_std_data(&nonblocking_pool); -+ return 0; -+} -+module_init(rand_initialize); -+ -+void rand_initialize_irq(int irq) -+{ -+ struct timer_rand_state *state; -+ -+ state = get_timer_rand_state(irq); -+ -+ if (state) -+ return; -+ -+ /* -+ * If kzalloc returns null, we just won't use that entropy -+ * source. -+ */ -+ state = kzalloc(sizeof(struct timer_rand_state), GFP_KERNEL); -+ if (state) -+ set_timer_rand_state(irq, state); -+} -+ -+#ifdef CONFIG_BLOCK -+void rand_initialize_disk(struct gendisk *disk) -+{ -+ struct timer_rand_state *state; -+ -+ /* -+ * If kzalloc returns null, we just won't use that entropy -+ * source. -+ */ -+ state = kzalloc(sizeof(struct timer_rand_state), GFP_KERNEL); -+ if (state) -+ disk->random = state; -+} -+#endif -+ -+static ssize_t -+random_read(struct file *file, char __user *buf, size_t nbytes, loff_t *ppos) -+{ -+ ssize_t n, retval = 0, count = 0; -+ -+ if (nbytes == 0) -+ return 0; -+ -+ while (nbytes > 0) { -+ n = nbytes; -+ if (n > SEC_XFER_SIZE) -+ n = SEC_XFER_SIZE; -+ -+ DEBUG_ENT("reading %d bits\n", n*8); -+ -+ n = extract_entropy_user(&blocking_pool, buf, n); -+ -+ DEBUG_ENT("read got %d bits (%d still needed)\n", -+ n*8, (nbytes-n)*8); -+ -+ if (n == 0) { -+ if (file->f_flags & O_NONBLOCK) { -+ retval = -EAGAIN; -+ break; -+ } -+ -+ DEBUG_ENT("sleeping?\n"); -+ -+ wait_event_interruptible(random_read_wait, -+ input_pool.entropy_count >= -+ random_read_wakeup_thresh); -+ -+ DEBUG_ENT("awake\n"); -+ -+ if (signal_pending(current)) { -+ retval = -ERESTARTSYS; -+ break; -+ } -+ -+ continue; -+ } -+ -+ if (n < 0) { -+ retval = n; -+ break; -+ } -+ count += n; -+ buf += n; -+ nbytes -= n; -+ break; /* This break makes the device work */ -+ /* like a named pipe */ -+ } -+ -+ return (count ? count : retval); -+} -+ -+static ssize_t -+urandom_read(struct file *file, char __user *buf, size_t nbytes, loff_t *ppos) -+{ -+ return extract_entropy_user(&nonblocking_pool, buf, nbytes); -+} -+ -+static unsigned int -+random_poll(struct file *file, poll_table * wait) -+{ -+ unsigned int mask; -+ -+ poll_wait(file, &random_read_wait, wait); -+ poll_wait(file, &random_write_wait, wait); -+ mask = 0; -+ if (input_pool.entropy_count >= random_read_wakeup_thresh) -+ mask |= POLLIN | POLLRDNORM; -+ if (input_pool.entropy_count < random_write_wakeup_thresh) -+ mask |= POLLOUT | POLLWRNORM; -+ return mask; -+} -+ -+static int -+write_pool(struct entropy_store *r, const char __user *buffer, size_t count) -+{ -+ size_t bytes; -+ __u32 buf[16]; -+ const char __user *p = buffer; -+ -+ while (count > 0) { -+ bytes = min(count, sizeof(buf)); -+ if (copy_from_user(&buf, p, bytes)) -+ return -EFAULT; -+ -+ count -= bytes; -+ p += bytes; -+ -+ mix_pool_bytes(r, buf, bytes); -+ cond_resched(); -+ } -+ -+ return 0; -+} -+ -+static ssize_t random_write(struct file *file, const char __user *buffer, -+ size_t count, loff_t *ppos) -+{ -+ size_t ret; -+ -+ ret = write_pool(&blocking_pool, buffer, count); -+ if (ret) -+ return ret; -+ ret = write_pool(&nonblocking_pool, buffer, count); -+ if (ret) -+ return ret; -+ -+ return (ssize_t)count; -+} -+ -+static long random_ioctl(struct file *f, unsigned int cmd, unsigned long arg) -+{ -+ int size, ent_count; -+ int __user *p = (int __user *)arg; -+ int retval; -+ -+ switch (cmd) { -+ case RNDGETENTCNT: -+ /* inherently racy, no point locking */ -+ if (put_user(input_pool.entropy_count, p)) -+ return -EFAULT; -+ return 0; -+ case RNDADDTOENTCNT: -+ if (!capable(CAP_SYS_ADMIN)) -+ return -EPERM; -+ if (get_user(ent_count, p)) -+ return -EFAULT; -+ credit_entropy_bits(&input_pool, ent_count); -+ return 0; -+ case RNDADDENTROPY: -+ if (!capable(CAP_SYS_ADMIN)) -+ return -EPERM; -+ if (get_user(ent_count, p++)) -+ return -EFAULT; -+ if (ent_count < 0) -+ return -EINVAL; -+ if (get_user(size, p++)) -+ return -EFAULT; -+ retval = write_pool(&input_pool, (const char __user *)p, -+ size); -+ if (retval < 0) -+ return retval; -+ credit_entropy_bits(&input_pool, ent_count); -+ return 0; -+ case RNDZAPENTCNT: -+ case RNDCLEARPOOL: -+ /* Clear the entropy pool counters. */ -+ if (!capable(CAP_SYS_ADMIN)) -+ return -EPERM; -+ rand_initialize(); -+ return 0; -+ default: -+ return -EINVAL; -+ } -+} -+ -+static int random_fasync(int fd, struct file *filp, int on) -+{ -+ return fasync_helper(fd, filp, on, &fasync); -+} -+ -+const struct file_operations random_fops = { -+ .read = random_read, -+ .write = random_write, -+ .poll = random_poll, -+ .unlocked_ioctl = random_ioctl, -+ .fasync = random_fasync, -+ .llseek = noop_llseek, -+}; -+ -+const struct file_operations urandom_fops = { -+ .read = urandom_read, -+ .write = random_write, -+ .unlocked_ioctl = random_ioctl, -+ .fasync = random_fasync, -+ .llseek = noop_llseek, -+}; -+ -+/*************************************************************** -+ * Random UUID interface -+ * -+ * Used here for a Boot ID, but can be useful for other kernel -+ * drivers. -+ ***************************************************************/ -+ -+/* -+ * Generate random UUID -+ */ -+void generate_random_uuid(unsigned char uuid_out[16]) -+{ -+ get_random_bytes(uuid_out, 16); -+ /* Set UUID version to 4 --- truly random generation */ -+ uuid_out[6] = (uuid_out[6] & 0x0F) | 0x40; -+ /* Set the UUID variant to DCE */ -+ uuid_out[8] = (uuid_out[8] & 0x3F) | 0x80; -+} -+EXPORT_SYMBOL(generate_random_uuid); -+ -+/******************************************************************** -+ * -+ * Sysctl interface -+ * -+ ********************************************************************/ -+ -+#ifdef CONFIG_SYSCTL -+ -+#include -+ -+static int min_read_thresh = 8, min_write_thresh; -+static int max_read_thresh = INPUT_POOL_WORDS * 32; -+static int max_write_thresh = INPUT_POOL_WORDS * 32; -+static char sysctl_bootid[16]; -+ -+/* -+ * These functions is used to return both the bootid UUID, and random -+ * UUID. The difference is in whether table->data is NULL; if it is, -+ * then a new UUID is generated and returned to the user. -+ * -+ * If the user accesses this via the proc interface, it will be returned -+ * as an ASCII string in the standard UUID format. If accesses via the -+ * sysctl system call, it is returned as 16 bytes of binary data. -+ */ -+static int proc_do_uuid(ctl_table *table, int write, -+ void __user *buffer, size_t *lenp, loff_t *ppos) -+{ -+ ctl_table fake_table; -+ unsigned char buf[64], tmp_uuid[16], *uuid; -+ -+ uuid = table->data; -+ if (!uuid) { -+ uuid = tmp_uuid; -+ uuid[8] = 0; -+ } -+ if (uuid[8] == 0) -+ generate_random_uuid(uuid); -+ -+ sprintf(buf, "%pU", uuid); -+ -+ fake_table.data = buf; -+ fake_table.maxlen = sizeof(buf); -+ -+ return proc_dostring(&fake_table, write, buffer, lenp, ppos); -+} -+ -+static int sysctl_poolsize = INPUT_POOL_WORDS * 32; -+ctl_table random_table[] = { -+ { -+ .procname = "poolsize", -+ .data = &sysctl_poolsize, -+ .maxlen = sizeof(int), -+ .mode = 0444, -+ .proc_handler = proc_dointvec, -+ }, -+ { -+ .procname = "entropy_avail", -+ .maxlen = sizeof(int), -+ .mode = 0444, -+ .proc_handler = proc_dointvec, -+ .data = &input_pool.entropy_count, -+ }, -+ { -+ .procname = "read_wakeup_threshold", -+ .data = &random_read_wakeup_thresh, -+ .maxlen = sizeof(int), -+ .mode = 0644, -+ .proc_handler = proc_dointvec_minmax, -+ .extra1 = &min_read_thresh, -+ .extra2 = &max_read_thresh, -+ }, -+ { -+ .procname = "write_wakeup_threshold", -+ .data = &random_write_wakeup_thresh, -+ .maxlen = sizeof(int), -+ .mode = 0644, -+ .proc_handler = proc_dointvec_minmax, -+ .extra1 = &min_write_thresh, -+ .extra2 = &max_write_thresh, -+ }, -+ { -+ .procname = "boot_id", -+ .data = &sysctl_bootid, -+ .maxlen = 16, -+ .mode = 0444, -+ .proc_handler = proc_do_uuid, -+ }, -+ { -+ .procname = "uuid", -+ .maxlen = 16, -+ .mode = 0444, -+ .proc_handler = proc_do_uuid, -+ }, -+ { } -+}; -+#endif /* CONFIG_SYSCTL */ -+ -+static u32 random_int_secret[MD5_MESSAGE_BYTES / 4] ____cacheline_aligned; -+ -+static int __init random_int_secret_init(void) -+{ -+ get_random_bytes(random_int_secret, sizeof(random_int_secret)); -+ return 0; -+} -+late_initcall(random_int_secret_init); -+ -+/* -+ * Get a random word for internal kernel use only. Similar to urandom but -+ * with the goal of minimal entropy pool depletion. As a result, the random -+ * value is not cryptographically secure but for several uses the cost of -+ * depleting entropy is too high -+ */ -+DEFINE_PER_CPU(__u32 [MD5_DIGEST_WORDS], get_random_int_hash); -+unsigned int get_random_int(void) -+{ -+ __u32 *hash = get_cpu_var(get_random_int_hash); -+ unsigned int ret; -+ -+ hash[0] += current->pid + jiffies + get_cycles(); -+ md5_transform(hash, random_int_secret); -+ ret = hash[0]; -+ put_cpu_var(get_random_int_hash); -+ -+ return ret; -+} -+ -+/* -+ * randomize_range() returns a start address such that -+ * -+ * [...... .....] -+ * start end -+ * -+ * a with size "len" starting at the return value is inside in the -+ * area defined by [start, end], but is otherwise randomized. -+ */ -+unsigned long -+randomize_range(unsigned long start, unsigned long end, unsigned long len) -+{ -+ unsigned long range = end - len - start; -+ -+ if (end <= start + len) -+ return 0; -+ return PAGE_ALIGN(get_random_int() % range + start); -+} -diff -Nur linux-3.0.4.orig/fs/fcntl.c linux-3.0.4/fs/fcntl.c ---- linux-3.0.4.orig/fs/fcntl.c 2011-08-29 22:56:30.000000000 +0200 -+++ linux-3.0.4/fs/fcntl.c 2011-10-17 04:36:27.356574299 +0200 -@@ -142,6 +142,7 @@ - } - return ret; - } -+EXPORT_SYMBOL(sys_dup); - - #define SETFL_MASK (O_APPEND | O_NONBLOCK | O_NDELAY | O_DIRECT | O_NOATIME) - -diff -Nur linux-3.0.4.orig/include/linux/miscdevice.h linux-3.0.4/include/linux/miscdevice.h ---- linux-3.0.4.orig/include/linux/miscdevice.h 2011-08-29 22:56:30.000000000 +0200 -+++ linux-3.0.4/include/linux/miscdevice.h 2011-10-17 04:36:27.356574299 +0200 -@@ -18,6 +18,7 @@ - #define APOLLO_MOUSE_MINOR 7 - #define PC110PAD_MINOR 9 - /*#define ADB_MOUSE_MINOR 10 FIXME OBSOLETE */ -+#define CRYPTODEV_MINOR 70 /* /dev/crypto */ - #define WATCHDOG_MINOR 130 /* Watchdog timer */ - #define TEMP_MINOR 131 /* Temperature Sensor */ - #define RTC_MINOR 135 -diff -Nur linux-3.0.4.orig/include/linux/random.h linux-3.0.4/include/linux/random.h ---- linux-3.0.4.orig/include/linux/random.h 2011-08-29 22:56:30.000000000 +0200 -+++ linux-3.0.4/include/linux/random.h 2011-10-17 04:36:27.356574299 +0200 -@@ -54,6 +54,10 @@ - unsigned int value); - extern void add_interrupt_randomness(int irq); - -+extern void random_input_words(__u32 *buf, size_t wordcount, int ent_count); -+extern int random_input_wait(void); -+#define HAS_RANDOM_INPUT_WAIT 1 -+ - extern void get_random_bytes(void *buf, int nbytes); - void generate_random_uuid(unsigned char uuid_out[16]); - -diff -Nur linux-3.0.4.orig/kernel/pid.c linux-3.0.4/kernel/pid.c ---- linux-3.0.4.orig/kernel/pid.c 2011-08-29 22:56:30.000000000 +0200 -+++ linux-3.0.4/kernel/pid.c 2011-10-17 04:36:27.356574299 +0200 -@@ -427,6 +427,7 @@ - { - return find_task_by_pid_ns(vnr, current->nsproxy->pid_ns); - } -+EXPORT_SYMBOL(find_task_by_vpid); - - struct pid *get_task_pid(struct task_struct *task, enum pid_type type) - { -diff -Nur linux-3.0.4.orig/kernel/pid.c.orig linux-3.0.4/kernel/pid.c.orig ---- linux-3.0.4.orig/kernel/pid.c.orig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/kernel/pid.c.orig 2011-08-29 22:56:30.000000000 +0200 -@@ -0,0 +1,570 @@ -+/* -+ * Generic pidhash and scalable, time-bounded PID allocator -+ * -+ * (C) 2002-2003 William Irwin, IBM -+ * (C) 2004 William Irwin, Oracle -+ * (C) 2002-2004 Ingo Molnar, Red Hat -+ * -+ * pid-structures are backing objects for tasks sharing a given ID to chain -+ * against. There is very little to them aside from hashing them and -+ * parking tasks using given ID's on a list. -+ * -+ * The hash is always changed with the tasklist_lock write-acquired, -+ * and the hash is only accessed with the tasklist_lock at least -+ * read-acquired, so there's no additional SMP locking needed here. -+ * -+ * We have a list of bitmap pages, which bitmaps represent the PID space. -+ * Allocating and freeing PIDs is completely lockless. The worst-case -+ * allocation scenario when all but one out of 1 million PIDs possible are -+ * allocated already: the scanning of 32 list entries and at most PAGE_SIZE -+ * bytes. The typical fastpath is a single successful setbit. Freeing is O(1). -+ * -+ * Pid namespaces: -+ * (C) 2007 Pavel Emelyanov , OpenVZ, SWsoft Inc. -+ * (C) 2007 Sukadev Bhattiprolu , IBM -+ * Many thanks to Oleg Nesterov for comments and help -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define pid_hashfn(nr, ns) \ -+ hash_long((unsigned long)nr + (unsigned long)ns, pidhash_shift) -+static struct hlist_head *pid_hash; -+static unsigned int pidhash_shift = 4; -+struct pid init_struct_pid = INIT_STRUCT_PID; -+ -+int pid_max = PID_MAX_DEFAULT; -+ -+#define RESERVED_PIDS 300 -+ -+int pid_max_min = RESERVED_PIDS + 1; -+int pid_max_max = PID_MAX_LIMIT; -+ -+#define BITS_PER_PAGE (PAGE_SIZE*8) -+#define BITS_PER_PAGE_MASK (BITS_PER_PAGE-1) -+ -+static inline int mk_pid(struct pid_namespace *pid_ns, -+ struct pidmap *map, int off) -+{ -+ return (map - pid_ns->pidmap)*BITS_PER_PAGE + off; -+} -+ -+#define find_next_offset(map, off) \ -+ find_next_zero_bit((map)->page, BITS_PER_PAGE, off) -+ -+/* -+ * PID-map pages start out as NULL, they get allocated upon -+ * first use and are never deallocated. This way a low pid_max -+ * value does not cause lots of bitmaps to be allocated, but -+ * the scheme scales to up to 4 million PIDs, runtime. -+ */ -+struct pid_namespace init_pid_ns = { -+ .kref = { -+ .refcount = ATOMIC_INIT(2), -+ }, -+ .pidmap = { -+ [ 0 ... PIDMAP_ENTRIES-1] = { ATOMIC_INIT(BITS_PER_PAGE), NULL } -+ }, -+ .last_pid = 0, -+ .level = 0, -+ .child_reaper = &init_task, -+}; -+EXPORT_SYMBOL_GPL(init_pid_ns); -+ -+int is_container_init(struct task_struct *tsk) -+{ -+ int ret = 0; -+ struct pid *pid; -+ -+ rcu_read_lock(); -+ pid = task_pid(tsk); -+ if (pid != NULL && pid->numbers[pid->level].nr == 1) -+ ret = 1; -+ rcu_read_unlock(); -+ -+ return ret; -+} -+EXPORT_SYMBOL(is_container_init); -+ -+/* -+ * Note: disable interrupts while the pidmap_lock is held as an -+ * interrupt might come in and do read_lock(&tasklist_lock). -+ * -+ * If we don't disable interrupts there is a nasty deadlock between -+ * detach_pid()->free_pid() and another cpu that does -+ * spin_lock(&pidmap_lock) followed by an interrupt routine that does -+ * read_lock(&tasklist_lock); -+ * -+ * After we clean up the tasklist_lock and know there are no -+ * irq handlers that take it we can leave the interrupts enabled. -+ * For now it is easier to be safe than to prove it can't happen. -+ */ -+ -+static __cacheline_aligned_in_smp DEFINE_SPINLOCK(pidmap_lock); -+ -+static void free_pidmap(struct upid *upid) -+{ -+ int nr = upid->nr; -+ struct pidmap *map = upid->ns->pidmap + nr / BITS_PER_PAGE; -+ int offset = nr & BITS_PER_PAGE_MASK; -+ -+ clear_bit(offset, map->page); -+ atomic_inc(&map->nr_free); -+} -+ -+/* -+ * If we started walking pids at 'base', is 'a' seen before 'b'? -+ */ -+static int pid_before(int base, int a, int b) -+{ -+ /* -+ * This is the same as saying -+ * -+ * (a - base + MAXUINT) % MAXUINT < (b - base + MAXUINT) % MAXUINT -+ * and that mapping orders 'a' and 'b' with respect to 'base'. -+ */ -+ return (unsigned)(a - base) < (unsigned)(b - base); -+} -+ -+/* -+ * We might be racing with someone else trying to set pid_ns->last_pid. -+ * We want the winner to have the "later" value, because if the -+ * "earlier" value prevails, then a pid may get reused immediately. -+ * -+ * Since pids rollover, it is not sufficient to just pick the bigger -+ * value. We have to consider where we started counting from. -+ * -+ * 'base' is the value of pid_ns->last_pid that we observed when -+ * we started looking for a pid. -+ * -+ * 'pid' is the pid that we eventually found. -+ */ -+static void set_last_pid(struct pid_namespace *pid_ns, int base, int pid) -+{ -+ int prev; -+ int last_write = base; -+ do { -+ prev = last_write; -+ last_write = cmpxchg(&pid_ns->last_pid, prev, pid); -+ } while ((prev != last_write) && (pid_before(base, last_write, pid))); -+} -+ -+static int alloc_pidmap(struct pid_namespace *pid_ns) -+{ -+ int i, offset, max_scan, pid, last = pid_ns->last_pid; -+ struct pidmap *map; -+ -+ pid = last + 1; -+ if (pid >= pid_max) -+ pid = RESERVED_PIDS; -+ offset = pid & BITS_PER_PAGE_MASK; -+ map = &pid_ns->pidmap[pid/BITS_PER_PAGE]; -+ /* -+ * If last_pid points into the middle of the map->page we -+ * want to scan this bitmap block twice, the second time -+ * we start with offset == 0 (or RESERVED_PIDS). -+ */ -+ max_scan = DIV_ROUND_UP(pid_max, BITS_PER_PAGE) - !offset; -+ for (i = 0; i <= max_scan; ++i) { -+ if (unlikely(!map->page)) { -+ void *page = kzalloc(PAGE_SIZE, GFP_KERNEL); -+ /* -+ * Free the page if someone raced with us -+ * installing it: -+ */ -+ spin_lock_irq(&pidmap_lock); -+ if (!map->page) { -+ map->page = page; -+ page = NULL; -+ } -+ spin_unlock_irq(&pidmap_lock); -+ kfree(page); -+ if (unlikely(!map->page)) -+ break; -+ } -+ if (likely(atomic_read(&map->nr_free))) { -+ do { -+ if (!test_and_set_bit(offset, map->page)) { -+ atomic_dec(&map->nr_free); -+ set_last_pid(pid_ns, last, pid); -+ return pid; -+ } -+ offset = find_next_offset(map, offset); -+ pid = mk_pid(pid_ns, map, offset); -+ } while (offset < BITS_PER_PAGE && pid < pid_max); -+ } -+ if (map < &pid_ns->pidmap[(pid_max-1)/BITS_PER_PAGE]) { -+ ++map; -+ offset = 0; -+ } else { -+ map = &pid_ns->pidmap[0]; -+ offset = RESERVED_PIDS; -+ if (unlikely(last == offset)) -+ break; -+ } -+ pid = mk_pid(pid_ns, map, offset); -+ } -+ return -1; -+} -+ -+int next_pidmap(struct pid_namespace *pid_ns, unsigned int last) -+{ -+ int offset; -+ struct pidmap *map, *end; -+ -+ if (last >= PID_MAX_LIMIT) -+ return -1; -+ -+ offset = (last + 1) & BITS_PER_PAGE_MASK; -+ map = &pid_ns->pidmap[(last + 1)/BITS_PER_PAGE]; -+ end = &pid_ns->pidmap[PIDMAP_ENTRIES]; -+ for (; map < end; map++, offset = 0) { -+ if (unlikely(!map->page)) -+ continue; -+ offset = find_next_bit((map)->page, BITS_PER_PAGE, offset); -+ if (offset < BITS_PER_PAGE) -+ return mk_pid(pid_ns, map, offset); -+ } -+ return -1; -+} -+ -+void put_pid(struct pid *pid) -+{ -+ struct pid_namespace *ns; -+ -+ if (!pid) -+ return; -+ -+ ns = pid->numbers[pid->level].ns; -+ if ((atomic_read(&pid->count) == 1) || -+ atomic_dec_and_test(&pid->count)) { -+ kmem_cache_free(ns->pid_cachep, pid); -+ put_pid_ns(ns); -+ } -+} -+EXPORT_SYMBOL_GPL(put_pid); -+ -+static void delayed_put_pid(struct rcu_head *rhp) -+{ -+ struct pid *pid = container_of(rhp, struct pid, rcu); -+ put_pid(pid); -+} -+ -+void free_pid(struct pid *pid) -+{ -+ /* We can be called with write_lock_irq(&tasklist_lock) held */ -+ int i; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&pidmap_lock, flags); -+ for (i = 0; i <= pid->level; i++) -+ hlist_del_rcu(&pid->numbers[i].pid_chain); -+ spin_unlock_irqrestore(&pidmap_lock, flags); -+ -+ for (i = 0; i <= pid->level; i++) -+ free_pidmap(pid->numbers + i); -+ -+ call_rcu(&pid->rcu, delayed_put_pid); -+} -+ -+struct pid *alloc_pid(struct pid_namespace *ns) -+{ -+ struct pid *pid; -+ enum pid_type type; -+ int i, nr; -+ struct pid_namespace *tmp; -+ struct upid *upid; -+ -+ pid = kmem_cache_alloc(ns->pid_cachep, GFP_KERNEL); -+ if (!pid) -+ goto out; -+ -+ tmp = ns; -+ for (i = ns->level; i >= 0; i--) { -+ nr = alloc_pidmap(tmp); -+ if (nr < 0) -+ goto out_free; -+ -+ pid->numbers[i].nr = nr; -+ pid->numbers[i].ns = tmp; -+ tmp = tmp->parent; -+ } -+ -+ get_pid_ns(ns); -+ pid->level = ns->level; -+ atomic_set(&pid->count, 1); -+ for (type = 0; type < PIDTYPE_MAX; ++type) -+ INIT_HLIST_HEAD(&pid->tasks[type]); -+ -+ upid = pid->numbers + ns->level; -+ spin_lock_irq(&pidmap_lock); -+ for ( ; upid >= pid->numbers; --upid) -+ hlist_add_head_rcu(&upid->pid_chain, -+ &pid_hash[pid_hashfn(upid->nr, upid->ns)]); -+ spin_unlock_irq(&pidmap_lock); -+ -+out: -+ return pid; -+ -+out_free: -+ while (++i <= ns->level) -+ free_pidmap(pid->numbers + i); -+ -+ kmem_cache_free(ns->pid_cachep, pid); -+ pid = NULL; -+ goto out; -+} -+ -+struct pid *find_pid_ns(int nr, struct pid_namespace *ns) -+{ -+ struct hlist_node *elem; -+ struct upid *pnr; -+ -+ hlist_for_each_entry_rcu(pnr, elem, -+ &pid_hash[pid_hashfn(nr, ns)], pid_chain) -+ if (pnr->nr == nr && pnr->ns == ns) -+ return container_of(pnr, struct pid, -+ numbers[ns->level]); -+ -+ return NULL; -+} -+EXPORT_SYMBOL_GPL(find_pid_ns); -+ -+struct pid *find_vpid(int nr) -+{ -+ return find_pid_ns(nr, current->nsproxy->pid_ns); -+} -+EXPORT_SYMBOL_GPL(find_vpid); -+ -+/* -+ * attach_pid() must be called with the tasklist_lock write-held. -+ */ -+void attach_pid(struct task_struct *task, enum pid_type type, -+ struct pid *pid) -+{ -+ struct pid_link *link; -+ -+ link = &task->pids[type]; -+ link->pid = pid; -+ hlist_add_head_rcu(&link->node, &pid->tasks[type]); -+} -+ -+static void __change_pid(struct task_struct *task, enum pid_type type, -+ struct pid *new) -+{ -+ struct pid_link *link; -+ struct pid *pid; -+ int tmp; -+ -+ link = &task->pids[type]; -+ pid = link->pid; -+ -+ hlist_del_rcu(&link->node); -+ link->pid = new; -+ -+ for (tmp = PIDTYPE_MAX; --tmp >= 0; ) -+ if (!hlist_empty(&pid->tasks[tmp])) -+ return; -+ -+ free_pid(pid); -+} -+ -+void detach_pid(struct task_struct *task, enum pid_type type) -+{ -+ __change_pid(task, type, NULL); -+} -+ -+void change_pid(struct task_struct *task, enum pid_type type, -+ struct pid *pid) -+{ -+ __change_pid(task, type, pid); -+ attach_pid(task, type, pid); -+} -+ -+/* transfer_pid is an optimization of attach_pid(new), detach_pid(old) */ -+void transfer_pid(struct task_struct *old, struct task_struct *new, -+ enum pid_type type) -+{ -+ new->pids[type].pid = old->pids[type].pid; -+ hlist_replace_rcu(&old->pids[type].node, &new->pids[type].node); -+} -+ -+struct task_struct *pid_task(struct pid *pid, enum pid_type type) -+{ -+ struct task_struct *result = NULL; -+ if (pid) { -+ struct hlist_node *first; -+ first = rcu_dereference_check(hlist_first_rcu(&pid->tasks[type]), -+ rcu_read_lock_held() || -+ lockdep_tasklist_lock_is_held()); -+ if (first) -+ result = hlist_entry(first, struct task_struct, pids[(type)].node); -+ } -+ return result; -+} -+EXPORT_SYMBOL(pid_task); -+ -+/* -+ * Must be called under rcu_read_lock(). -+ */ -+struct task_struct *find_task_by_pid_ns(pid_t nr, struct pid_namespace *ns) -+{ -+ rcu_lockdep_assert(rcu_read_lock_held()); -+ return pid_task(find_pid_ns(nr, ns), PIDTYPE_PID); -+} -+ -+struct task_struct *find_task_by_vpid(pid_t vnr) -+{ -+ return find_task_by_pid_ns(vnr, current->nsproxy->pid_ns); -+} -+ -+struct pid *get_task_pid(struct task_struct *task, enum pid_type type) -+{ -+ struct pid *pid; -+ rcu_read_lock(); -+ if (type != PIDTYPE_PID) -+ task = task->group_leader; -+ pid = get_pid(task->pids[type].pid); -+ rcu_read_unlock(); -+ return pid; -+} -+EXPORT_SYMBOL_GPL(get_task_pid); -+ -+struct task_struct *get_pid_task(struct pid *pid, enum pid_type type) -+{ -+ struct task_struct *result; -+ rcu_read_lock(); -+ result = pid_task(pid, type); -+ if (result) -+ get_task_struct(result); -+ rcu_read_unlock(); -+ return result; -+} -+EXPORT_SYMBOL_GPL(get_pid_task); -+ -+struct pid *find_get_pid(pid_t nr) -+{ -+ struct pid *pid; -+ -+ rcu_read_lock(); -+ pid = get_pid(find_vpid(nr)); -+ rcu_read_unlock(); -+ -+ return pid; -+} -+EXPORT_SYMBOL_GPL(find_get_pid); -+ -+pid_t pid_nr_ns(struct pid *pid, struct pid_namespace *ns) -+{ -+ struct upid *upid; -+ pid_t nr = 0; -+ -+ if (pid && ns->level <= pid->level) { -+ upid = &pid->numbers[ns->level]; -+ if (upid->ns == ns) -+ nr = upid->nr; -+ } -+ return nr; -+} -+ -+pid_t pid_vnr(struct pid *pid) -+{ -+ return pid_nr_ns(pid, current->nsproxy->pid_ns); -+} -+EXPORT_SYMBOL_GPL(pid_vnr); -+ -+pid_t __task_pid_nr_ns(struct task_struct *task, enum pid_type type, -+ struct pid_namespace *ns) -+{ -+ pid_t nr = 0; -+ -+ rcu_read_lock(); -+ if (!ns) -+ ns = current->nsproxy->pid_ns; -+ if (likely(pid_alive(task))) { -+ if (type != PIDTYPE_PID) -+ task = task->group_leader; -+ nr = pid_nr_ns(task->pids[type].pid, ns); -+ } -+ rcu_read_unlock(); -+ -+ return nr; -+} -+EXPORT_SYMBOL(__task_pid_nr_ns); -+ -+pid_t task_tgid_nr_ns(struct task_struct *tsk, struct pid_namespace *ns) -+{ -+ return pid_nr_ns(task_tgid(tsk), ns); -+} -+EXPORT_SYMBOL(task_tgid_nr_ns); -+ -+struct pid_namespace *task_active_pid_ns(struct task_struct *tsk) -+{ -+ return ns_of_pid(task_pid(tsk)); -+} -+EXPORT_SYMBOL_GPL(task_active_pid_ns); -+ -+/* -+ * Used by proc to find the first pid that is greater than or equal to nr. -+ * -+ * If there is a pid at nr this function is exactly the same as find_pid_ns. -+ */ -+struct pid *find_ge_pid(int nr, struct pid_namespace *ns) -+{ -+ struct pid *pid; -+ -+ do { -+ pid = find_pid_ns(nr, ns); -+ if (pid) -+ break; -+ nr = next_pidmap(ns, nr); -+ } while (nr > 0); -+ -+ return pid; -+} -+ -+/* -+ * The pid hash table is scaled according to the amount of memory in the -+ * machine. From a minimum of 16 slots up to 4096 slots at one gigabyte or -+ * more. -+ */ -+void __init pidhash_init(void) -+{ -+ int i, pidhash_size; -+ -+ pid_hash = alloc_large_system_hash("PID", sizeof(*pid_hash), 0, 18, -+ HASH_EARLY | HASH_SMALL, -+ &pidhash_shift, NULL, 4096); -+ pidhash_size = 1 << pidhash_shift; -+ -+ for (i = 0; i < pidhash_size; i++) -+ INIT_HLIST_HEAD(&pid_hash[i]); -+} -+ -+void __init pidmap_init(void) -+{ -+ /* bump default and minimum pid_max based on number of cpus */ -+ pid_max = min(pid_max_max, max_t(int, pid_max, -+ PIDS_PER_CPU_DEFAULT * num_possible_cpus())); -+ pid_max_min = max_t(int, pid_max_min, -+ PIDS_PER_CPU_MIN * num_possible_cpus()); -+ pr_info("pid_max: default: %u minimum: %u\n", pid_max, pid_max_min); -+ -+ init_pid_ns.pidmap[0].page = kzalloc(PAGE_SIZE, GFP_KERNEL); -+ /* Reserve PID 0. We never call free_pidmap(0) */ -+ set_bit(0, init_pid_ns.pidmap[0].page); -+ atomic_dec(&init_pid_ns.pidmap[0].nr_free); -+ -+ init_pid_ns.pid_cachep = KMEM_CACHE(pid, -+ SLAB_HWCACHE_ALIGN | SLAB_PANIC); -+} diff --git a/target/linux/patches/3.0.4/sparc-include.patch b/target/linux/patches/3.0.4/sparc-include.patch deleted file mode 100644 index 2f8ffd061..000000000 --- a/target/linux/patches/3.0.4/sparc-include.patch +++ /dev/null @@ -1,11 +0,0 @@ -diff -Nur linux-2.6.39-rc7.orig/arch/sparc/boot/btfixupprep.c linux-2.6.39-rc7/arch/sparc/boot/btfixupprep.c ---- linux-2.6.39-rc7.orig/arch/sparc/boot/btfixupprep.c 2011-05-10 04:33:54.000000000 +0200 -+++ linux-2.6.39-rc7/arch/sparc/boot/btfixupprep.c 2011-05-21 13:34:40.000000000 +0200 -@@ -25,7 +25,6 @@ - #include - #include - #include --#include - - #define MAXSYMS 1024 - diff --git a/target/linux/patches/3.0.4/startup.patch b/target/linux/patches/3.0.4/startup.patch deleted file mode 100644 index 68e8987b0..000000000 --- a/target/linux/patches/3.0.4/startup.patch +++ /dev/null @@ -1,20 +0,0 @@ -diff -Nur linux-2.6.34.orig/init/main.c linux-2.6.34/init/main.c ---- linux-2.6.34.orig/init/main.c 2010-05-16 23:17:36.000000000 +0200 -+++ linux-2.6.34/init/main.c 2010-05-20 20:13:26.321613615 +0200 -@@ -842,6 +842,7 @@ - printk(KERN_WARNING "Failed to execute %s. Attempting " - "defaults...\n", execute_command); - } -+ run_init_process("/init"); - run_init_process("/sbin/init"); - run_init_process("/etc/init"); - run_init_process("/bin/init"); -@@ -889,6 +890,8 @@ - if (sys_open((const char __user *) "/dev/console", O_RDWR, 0) < 0) - printk(KERN_WARNING "Warning: unable to open an initial console.\n"); - -+ printk(KERN_WARNING "Starting Linux (built with OpenADK).\n"); -+ - (void) sys_dup(0); - (void) sys_dup(0); - /* diff --git a/target/linux/patches/3.0.4/usb-defaults-off.patch b/target/linux/patches/3.0.4/usb-defaults-off.patch deleted file mode 100644 index 31367108a..000000000 --- a/target/linux/patches/3.0.4/usb-defaults-off.patch +++ /dev/null @@ -1,32 +0,0 @@ -diff -Nur linux-2.6.37.orig//drivers/usb/core/Kconfig linux-2.6.37/drivers/usb/core/Kconfig ---- linux-2.6.37.orig//drivers/usb/core/Kconfig 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/usb/core/Kconfig 2011-04-12 19:04:23.000000000 +0200 -@@ -59,7 +59,7 @@ - config USB_DEVICE_CLASS - bool "USB device class-devices (DEPRECATED)" - depends on USB -- default y -+ default n - ---help--- - Userspace access to USB devices is granted by device-nodes exported - directly from the usbdev in sysfs. Old versions of the driver -diff -Nur linux-2.6.37.orig//drivers/usb/host/Kconfig linux-2.6.37/drivers/usb/host/Kconfig ---- linux-2.6.37.orig//drivers/usb/host/Kconfig 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/usb/host/Kconfig 2011-04-12 19:04:48.000000000 +0200 -@@ -62,6 +62,7 @@ - config USB_EHCI_ROOT_HUB_TT - bool "Root Hub Transaction Translators" - depends on USB_EHCI_HCD -+ default n - ---help--- - Some EHCI chips have vendor-specific extensions to integrate - transaction translators, so that no OHCI or UHCI companion -@@ -74,7 +75,7 @@ - config USB_EHCI_TT_NEWSCHED - bool "Improved Transaction Translator scheduling" - depends on USB_EHCI_HCD -- default y -+ default n - ---help--- - This changes the periodic scheduling code to fill more of the low - and full speed bandwidth available from the Transaction Translator diff --git a/target/linux/patches/3.0.4/uuid.patch b/target/linux/patches/3.0.4/uuid.patch deleted file mode 100644 index 2529fdab5..000000000 --- a/target/linux/patches/3.0.4/uuid.patch +++ /dev/null @@ -1,255 +0,0 @@ -diff -Nur linux-2.6.38.4.orig/block/genhd.c linux-2.6.38.4/block/genhd.c ---- linux-2.6.38.4.orig/block/genhd.c 2011-04-21 23:34:46.000000000 +0200 -+++ linux-2.6.38.4/block/genhd.c 2011-04-27 19:21:18.668912036 +0200 -@@ -34,7 +34,7 @@ - static DEFINE_MUTEX(ext_devt_mutex); - static DEFINE_IDR(ext_devt_idr); - --static struct device_type disk_type; -+struct device_type disk_type; - - static void disk_add_events(struct gendisk *disk); - static void disk_del_events(struct gendisk *disk); -@@ -1118,7 +1118,7 @@ - return NULL; - } - --static struct device_type disk_type = { -+struct device_type disk_type = { - .name = "disk", - .groups = disk_attr_groups, - .release = disk_release, -diff -Nur linux-2.6.38.4.orig/init/do_mounts.c linux-2.6.38.4/init/do_mounts.c ---- linux-2.6.38.4.orig/init/do_mounts.c 2011-04-21 23:34:46.000000000 +0200 -+++ linux-2.6.38.4/init/do_mounts.c 2011-04-27 19:26:52.721413000 +0200 -@@ -32,6 +32,132 @@ - - dev_t ROOT_DEV; - -+#ifdef CONFIG_EXT2_FS -+/* support for root=UUID=ce40d6b2-18eb-4a75-aefe-7ddb0995ce63 bootargs */ -+ -+#include -+ -+__u8 root_dev_uuid[16]; -+int root_dev_type; /* 0 = normal (/dev/hda1, 0301); 1 = UUID; 3 = bad */ -+ -+/* imported from block/genhd.c after removing its static qualifier */ -+extern struct device_type disk_type; -+ -+/* helper function */ -+static __u8 __init fromhex(char c) -+{ -+ if (c >= '0' && c <= '9') -+ return (c - '0'); -+ c &= ~32; -+ if (c >= 'A' && c <= 'F') -+ return (c - 'A' + 10); -+ return (0xFF); -+} -+ -+static void __init parse_uuid(const char *s) -+{ -+ int i; -+ __u8 j, k; -+ -+ if (strlen(s) != 36 || s[8] != '-' || s[13] != '-' || -+ s[18] != '-' || s[23] != '-') -+ goto bad_uuid; -+ for (i = 0; i < 16; i++) { -+ if (*s == '-') -+ ++s; -+ j = fromhex(*s++); -+ k = fromhex(*s++); -+ if (j == 0xFF || k == 0xFF) -+ goto bad_uuid; -+ root_dev_uuid[i] = (j << 4) | k; -+ } -+ return; -+ bad_uuid: -+ /* we cannot panic here, defer */ -+ root_dev_type = 3; -+} -+ -+/* from drivers/md/md.c */ -+static void __init initcode_bi_complete(struct bio *bio, int error) -+{ -+ complete((struct completion*)bio->bi_private); -+} -+ -+static int __init initcode_sync_page_read(struct block_device *bdev, -+ sector_t sector, int size, struct page *page) -+{ -+ struct bio *bio = bio_alloc(GFP_NOIO, 1); -+ struct completion event; -+ int ret, rw = READ; -+ -+ rw |= REQ_SYNC; -+ -+ bio->bi_bdev = bdev; -+ bio->bi_sector = sector; -+ bio_add_page(bio, page, size, 0); -+ init_completion(&event); -+ bio->bi_private = &event; -+ bio->bi_end_io = initcode_bi_complete; -+ submit_bio(rw, bio); -+ wait_for_completion(&event); -+ -+ ret = test_bit(BIO_UPTODATE, &bio->bi_flags); -+ bio_put(bio); -+ /* 0 = failure */ -+ return ret; -+} -+ -+/* most of this taken from fs/ext2/super.c */ -+static int __init check_dev(struct gendisk *thedisk, dev_t devt, -+ int blocksize, struct page *page) -+{ -+ struct ext2_super_block * es; -+ struct block_device *bdev; -+ unsigned long sb_block = 1; -+ unsigned long logic_sb_block; -+ unsigned long offset = 0; -+ int rv = /* not found */ 0; -+ char bff[22]; -+ -+ bdev = bdget(devt); -+ if (blkdev_get(bdev, FMODE_READ, NULL)) { -+ printk(KERN_ERR "VFS: opening block device %s failed!\n", -+ format_dev_t(bff, devt)); -+ return (0); -+ } -+ -+ if (blocksize != BLOCK_SIZE) { -+ logic_sb_block = (sb_block*BLOCK_SIZE) / blocksize; -+ offset = (sb_block*BLOCK_SIZE) % blocksize; -+ } else { -+ logic_sb_block = sb_block; -+ } -+ -+// printk(KERN_ERR "D: attempting to read %d @%lu from " -+// "bdev %p devt %08X %s\n", blocksize, logic_sb_block, -+// bdev, devt, format_dev_t(bff, devt)); -+ if (!initcode_sync_page_read(bdev, logic_sb_block, blocksize, page)) { -+// printk(KERN_ERR "D: failed!\n"); -+ goto out; -+ } -+ es = (struct ext2_super_block *)(((char *)page_address(page)) + offset); -+ if (le16_to_cpu(es->s_magic) == EXT2_SUPER_MAGIC) { -+// printk(KERN_ERR "D: has uuid " -+// "%02X%02X%02X%02X-%02X%02X-%02X%02X-%02X%02X-%02X%02X%02X%02X%02X%02X\n", -+// es->s_uuid[0], es->s_uuid[1], es->s_uuid[2], es->s_uuid[3], -+// es->s_uuid[4], es->s_uuid[5], es->s_uuid[6], es->s_uuid[7], -+// es->s_uuid[8], es->s_uuid[9], es->s_uuid[10], es->s_uuid[11], -+// es->s_uuid[12], es->s_uuid[13], es->s_uuid[14], es->s_uuid[15]); -+ if (!memcmp(es->s_uuid, root_dev_uuid, 16)) -+ rv = /* found */ 1; -+ } -+// else printk(KERN_ERR "D: bad ext2fs magic\n"); -+ out: -+ blkdev_put(bdev, FMODE_READ); -+ return (rv); -+} -+#endif /* CONFIG_EXT2_FS for UUID support */ -+ - static int __init load_ramdisk(char *str) - { - rd_doload = simple_strtol(str,NULL,0) & 3; -@@ -218,6 +344,13 @@ - static int __init root_dev_setup(char *line) - { - strlcpy(saved_root_name, line, sizeof(saved_root_name)); -+#ifdef CONFIG_EXT2_FS -+ root_dev_type = 0; -+ if (!strncmp(line, "UUID=", 5)) { -+ root_dev_type = 1; -+ parse_uuid(line + 5); -+ } -+#endif /* CONFIG_EXT2_FS for UUID support */ - return 1; - } - -@@ -403,6 +536,83 @@ - - void __init mount_root(void) - { -+#ifdef CONFIG_EXT2_FS -+ /* UUID support */ -+// printk_all_partitions(); -+ if (root_dev_type == 1) { -+ int blocksize; -+ -+ /* from block/genhd.c printk_all_partitions */ -+ struct class_dev_iter iter; -+ struct device *dev; -+ -+ /* from drivers/md/md.c */ -+ struct page *sb_page; -+ -+ if (!(sb_page = alloc_page(GFP_KERNEL))) { -+ printk(KERN_ERR "VFS: no memory for bio page\n"); -+ goto nomemforbio; -+ } -+ -+// printk(KERN_ERR "D: root is: " -+// "%02X%02X%02X%02X-%02X%02X-%02X%02X-%02X%02X-%02X%02X%02X%02X%02X%02X\n", -+// root_dev_uuid[0], root_dev_uuid[1], root_dev_uuid[2], root_dev_uuid[3], -+// root_dev_uuid[4], root_dev_uuid[5], root_dev_uuid[6], root_dev_uuid[7], -+// root_dev_uuid[8], root_dev_uuid[9], root_dev_uuid[10], root_dev_uuid[11], -+// root_dev_uuid[12], root_dev_uuid[13], root_dev_uuid[14], root_dev_uuid[15]); -+ /* from block/genhd.c printk_all_partitions */ -+// printk(KERN_ERR "D: begin iter\n"); -+ class_dev_iter_init(&iter, &block_class, NULL, &disk_type); -+ while (root_dev_type && (dev = class_dev_iter_next(&iter))) { -+// char bff[22]; -+ struct gendisk *disk = dev_to_disk(dev); -+ struct disk_part_iter piter; -+ struct hd_struct *part; -+ if (get_capacity(disk) == 0 || -+ (disk->flags & GENHD_FL_SUPPRESS_PARTITION_INFO)) { -+// printk(KERN_ERR "D: ignoring\n"); -+ continue; -+ } -+ blocksize = queue_logical_block_size(disk->queue); -+// printk(KERN_ERR "D: gendisk, blocksize %d " -+// "name '%s' devt %08X %s #part %d\n", blocksize, -+// disk->disk_name, dev->devt, -+// format_dev_t(bff, dev->devt), -+// disk_max_parts(disk)); -+ disk_part_iter_init(&piter, disk, DISK_PITER_INCL_PART0); -+ while (root_dev_type && (part = disk_part_iter_next(&piter))) { -+ /* avoid empty or too small partitions */ -+// printk(KERN_ERR "D: part #%d start %llu " -+// "nr %llu\n", part->partno, -+// (__u64)part->start_sect, -+// (__u64)part->nr_sects); -+ if (part->nr_sects < 8) -+ continue; -+ if (check_dev(disk, MKDEV(MAJOR(dev->devt), -+ MINOR(dev->devt) + part->partno), -+ blocksize, sb_page)) { -+ ROOT_DEV = part_devt(part); -+// printk(KERN_ERR "D: got match!\n"); -+ // comment out below for debugging -+ root_dev_type = 0; -+ } -+ } -+ disk_part_iter_exit(&piter); -+ } -+// printk(KERN_ERR "D: end iter\n"); -+ class_dev_iter_exit(&iter); -+ put_page(sb_page); -+ } -+ nomemforbio: -+ if (root_dev_type == 1) -+ printk(KERN_ERR "VFS: Unable to find root by UUID %s.\n", -+ saved_root_name + 5); -+ else if (root_dev_type == 3) -+ /* execute deferred panic from parse_uuid */ -+ panic("Badly formatted UUID %s was supplied as kernel " -+ "parameter root", saved_root_name + 5); -+#endif /* CONFIG_EXT2_FS for UUID support */ -+ - #ifdef CONFIG_ROOT_NFS - if (MAJOR(ROOT_DEV) == UNNAMED_MAJOR) { - if (mount_nfs_root()) diff --git a/target/linux/patches/3.0.4/vga-cons-default-off.patch b/target/linux/patches/3.0.4/vga-cons-default-off.patch deleted file mode 100644 index 178aeeeb9..000000000 --- a/target/linux/patches/3.0.4/vga-cons-default-off.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff -Nur linux-2.6.37.orig//drivers/video/console/Kconfig linux-2.6.37/drivers/video/console/Kconfig ---- linux-2.6.37.orig//drivers/video/console/Kconfig 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/video/console/Kconfig 2011-04-12 16:29:34.000000000 +0200 -@@ -7,7 +7,7 @@ - config VGA_CONSOLE - bool "VGA text console" if EMBEDDED || !X86 - depends on !4xx && !8xx && !SPARC && !M68K && !PARISC && !FRV && !SUPERH && !BLACKFIN && !AVR32 && !MN10300 && (!ARM || ARCH_FOOTBRIDGE || ARCH_INTEGRATOR || ARCH_NETWINDER) -- default y -+ default n - help - Saying Y here will allow you to use Linux in text mode through a - display that complies with the generic VGA standard. Virtually diff --git a/target/linux/patches/3.0.4/wlan-cf.patch b/target/linux/patches/3.0.4/wlan-cf.patch deleted file mode 100644 index fc20759e2..000000000 --- a/target/linux/patches/3.0.4/wlan-cf.patch +++ /dev/null @@ -1,11 +0,0 @@ -diff -Nur linux-2.6.39.orig/drivers/net/wireless/hostap/hostap_cs.c linux-2.6.39/drivers/net/wireless/hostap/hostap_cs.c ---- linux-2.6.39.orig/drivers/net/wireless/hostap/hostap_cs.c 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/drivers/net/wireless/hostap/hostap_cs.c 2011-09-12 02:46:26.987984145 +0200 -@@ -623,6 +623,7 @@ - static struct pcmcia_device_id hostap_cs_ids[] = { - PCMCIA_DEVICE_MANF_CARD(0x000b, 0x7100), - PCMCIA_DEVICE_MANF_CARD(0x000b, 0x7300), -+ PCMCIA_DEVICE_MANF_CARD(0x0004, 0x2003), - PCMCIA_DEVICE_MANF_CARD(0x0101, 0x0777), - PCMCIA_DEVICE_MANF_CARD(0x0126, 0x8000), - PCMCIA_DEVICE_MANF_CARD(0x0138, 0x0002), diff --git a/target/linux/patches/3.0.4/x86-build.patch b/target/linux/patches/3.0.4/x86-build.patch deleted file mode 100644 index 339140f41..000000000 --- a/target/linux/patches/3.0.4/x86-build.patch +++ /dev/null @@ -1,11 +0,0 @@ -diff -Nur linux-2.6.39-rc6.orig/arch/x86/boot/tools/build.c linux-2.6.39-rc6/arch/x86/boot/tools/build.c ---- linux-2.6.39-rc6.orig/arch/x86/boot/tools/build.c 2011-05-04 04:59:13.000000000 +0200 -+++ linux-2.6.39-rc6/arch/x86/boot/tools/build.c 2011-05-05 20:10:07.000000000 +0200 -@@ -29,7 +29,6 @@ - #include - #include - #include --#include - #include - #include - #include diff --git a/target/linux/patches/3.0.4/zlib-inflate.patch b/target/linux/patches/3.0.4/zlib-inflate.patch deleted file mode 100644 index 58e1f6d21..000000000 --- a/target/linux/patches/3.0.4/zlib-inflate.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff -Nur linux-2.6.37.orig/lib/Kconfig linux-2.6.37/lib/Kconfig ---- linux-2.6.37.orig/lib/Kconfig 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/lib/Kconfig 2011-03-01 20:10:29.833370667 +0100 -@@ -95,7 +95,7 @@ - # compression support is select'ed if needed - # - config ZLIB_INFLATE -- tristate -+ boolean - - config ZLIB_DEFLATE - tristate diff --git a/target/linux/patches/3.0.8/bsd-compatibility.patch b/target/linux/patches/3.0.8/bsd-compatibility.patch deleted file mode 100644 index 9e91a62de..000000000 --- a/target/linux/patches/3.0.8/bsd-compatibility.patch +++ /dev/null @@ -1,2512 +0,0 @@ -diff -Nur linux-2.6.36.orig/scripts/Makefile.lib linux-2.6.36/scripts/Makefile.lib ---- linux-2.6.36.orig/scripts/Makefile.lib 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/scripts/Makefile.lib 2010-11-28 18:34:22.000000000 +0100 -@@ -216,7 +216,12 @@ - size_append = printf $(shell \ - dec_size=0; \ - for F in $1; do \ -- fsize=$$(stat -c "%s" $$F); \ -+ if stat -qs .>/dev/null 2>&1; then \ -+ statcmd='stat -f %z'; \ -+ else \ -+ statcmd='stat -c %s'; \ -+ fi; \ -+ fsize=$$($$statcmd $$F); \ - dec_size=$$(expr $$dec_size + $$fsize); \ - done; \ - printf "%08x\n" $$dec_size | \ -diff -Nur linux-2.6.36.orig/scripts/mod/mk_elfconfig.c linux-2.6.36/scripts/mod/mk_elfconfig.c ---- linux-2.6.36.orig/scripts/mod/mk_elfconfig.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/scripts/mod/mk_elfconfig.c 2010-11-28 18:33:24.000000000 +0100 -@@ -1,7 +1,18 @@ - #include - #include - #include --#include -+ -+#define EI_NIDENT (16) -+#define ELFMAG "\177ELF" -+ -+#define SELFMAG 4 -+#define EI_CLASS 4 -+#define ELFCLASS32 1 /* 32-bit objects */ -+#define ELFCLASS64 2 /* 64-bit objects */ -+ -+#define EI_DATA 5 /* Data encoding byte index */ -+#define ELFDATA2LSB 1 /* 2's complement, little endian */ -+#define ELFDATA2MSB 2 /* 2's complement, big endian */ - - int - main(int argc, char **argv) -diff -Nur linux-2.6.36.orig/scripts/mod/modpost.h linux-2.6.36/scripts/mod/modpost.h ---- linux-2.6.36.orig/scripts/mod/modpost.h 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/scripts/mod/modpost.h 2010-11-28 18:33:24.000000000 +0100 -@@ -7,7 +7,2453 @@ - #include - #include - #include --#include -+ -+ -+/* This file defines standard ELF types, structures, and macros. -+ Copyright (C) 1995-1999,2000,2001,2002,2003 Free Software Foundation, Inc. -+ This file is part of the GNU C Library. -+ -+ The GNU C Library is free software; you can redistribute it and/or -+ modify it under the terms of the GNU Lesser General Public -+ License as published by the Free Software Foundation; either -+ version 2.1 of the License, or (at your option) any later version. -+ -+ The GNU C Library is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ Lesser General Public License for more details. -+ -+ You should have received a copy of the GNU Lesser General Public -+ License along with the GNU C Library; if not, write to the Free -+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA -+ 02111-1307 USA. */ -+ -+#ifndef _ELF_H -+#define _ELF_H 1 -+ -+__BEGIN_DECLS -+ -+/* Standard ELF types. */ -+ -+#include -+ -+/* Type for a 16-bit quantity. */ -+typedef uint16_t Elf32_Half; -+typedef uint16_t Elf64_Half; -+ -+/* Types for signed and unsigned 32-bit quantities. */ -+typedef uint32_t Elf32_Word; -+typedef int32_t Elf32_Sword; -+typedef uint32_t Elf64_Word; -+typedef int32_t Elf64_Sword; -+ -+/* Types for signed and unsigned 64-bit quantities. */ -+typedef uint64_t Elf32_Xword; -+typedef int64_t Elf32_Sxword; -+typedef uint64_t Elf64_Xword; -+typedef int64_t Elf64_Sxword; -+ -+/* Type of addresses. */ -+typedef uint32_t Elf32_Addr; -+typedef uint64_t Elf64_Addr; -+ -+/* Type of file offsets. */ -+typedef uint32_t Elf32_Off; -+typedef uint64_t Elf64_Off; -+ -+/* Type for section indices, which are 16-bit quantities. */ -+typedef uint16_t Elf32_Section; -+typedef uint16_t Elf64_Section; -+ -+/* Type for version symbol information. */ -+typedef Elf32_Half Elf32_Versym; -+typedef Elf64_Half Elf64_Versym; -+ -+ -+/* The ELF file header. This appears at the start of every ELF file. */ -+ -+#define EI_NIDENT (16) -+ -+typedef struct -+{ -+ unsigned char e_ident[EI_NIDENT]; /* Magic number and other info */ -+ Elf32_Half e_type; /* Object file type */ -+ Elf32_Half e_machine; /* Architecture */ -+ Elf32_Word e_version; /* Object file version */ -+ Elf32_Addr e_entry; /* Entry point virtual address */ -+ Elf32_Off e_phoff; /* Program header table file offset */ -+ Elf32_Off e_shoff; /* Section header table file offset */ -+ Elf32_Word e_flags; /* Processor-specific flags */ -+ Elf32_Half e_ehsize; /* ELF header size in bytes */ -+ Elf32_Half e_phentsize; /* Program header table entry size */ -+ Elf32_Half e_phnum; /* Program header table entry count */ -+ Elf32_Half e_shentsize; /* Section header table entry size */ -+ Elf32_Half e_shnum; /* Section header table entry count */ -+ Elf32_Half e_shstrndx; /* Section header string table index */ -+} Elf32_Ehdr; -+ -+typedef struct -+{ -+ unsigned char e_ident[EI_NIDENT]; /* Magic number and other info */ -+ Elf64_Half e_type; /* Object file type */ -+ Elf64_Half e_machine; /* Architecture */ -+ Elf64_Word e_version; /* Object file version */ -+ Elf64_Addr e_entry; /* Entry point virtual address */ -+ Elf64_Off e_phoff; /* Program header table file offset */ -+ Elf64_Off e_shoff; /* Section header table file offset */ -+ Elf64_Word e_flags; /* Processor-specific flags */ -+ Elf64_Half e_ehsize; /* ELF header size in bytes */ -+ Elf64_Half e_phentsize; /* Program header table entry size */ -+ Elf64_Half e_phnum; /* Program header table entry count */ -+ Elf64_Half e_shentsize; /* Section header table entry size */ -+ Elf64_Half e_shnum; /* Section header table entry count */ -+ Elf64_Half e_shstrndx; /* Section header string table index */ -+} Elf64_Ehdr; -+ -+/* Fields in the e_ident array. The EI_* macros are indices into the -+ array. The macros under each EI_* macro are the values the byte -+ may have. */ -+ -+#define EI_MAG0 0 /* File identification byte 0 index */ -+#define ELFMAG0 0x7f /* Magic number byte 0 */ -+ -+#define EI_MAG1 1 /* File identification byte 1 index */ -+#define ELFMAG1 'E' /* Magic number byte 1 */ -+ -+#define EI_MAG2 2 /* File identification byte 2 index */ -+#define ELFMAG2 'L' /* Magic number byte 2 */ -+ -+#define EI_MAG3 3 /* File identification byte 3 index */ -+#define ELFMAG3 'F' /* Magic number byte 3 */ -+ -+/* Conglomeration of the identification bytes, for easy testing as a word. */ -+#define ELFMAG "\177ELF" -+#define SELFMAG 4 -+ -+#define EI_CLASS 4 /* File class byte index */ -+#define ELFCLASSNONE 0 /* Invalid class */ -+#define ELFCLASS32 1 /* 32-bit objects */ -+#define ELFCLASS64 2 /* 64-bit objects */ -+#define ELFCLASSNUM 3 -+ -+#define EI_DATA 5 /* Data encoding byte index */ -+#define ELFDATANONE 0 /* Invalid data encoding */ -+#define ELFDATA2LSB 1 /* 2's complement, little endian */ -+#define ELFDATA2MSB 2 /* 2's complement, big endian */ -+#define ELFDATANUM 3 -+ -+#define EI_VERSION 6 /* File version byte index */ -+ /* Value must be EV_CURRENT */ -+ -+#define EI_OSABI 7 /* OS ABI identification */ -+#define ELFOSABI_NONE 0 /* UNIX System V ABI */ -+#define ELFOSABI_SYSV 0 /* Alias. */ -+#define ELFOSABI_HPUX 1 /* HP-UX */ -+#define ELFOSABI_NETBSD 2 /* NetBSD. */ -+#define ELFOSABI_LINUX 3 /* Linux. */ -+#define ELFOSABI_SOLARIS 6 /* Sun Solaris. */ -+#define ELFOSABI_AIX 7 /* IBM AIX. */ -+#define ELFOSABI_IRIX 8 /* SGI Irix. */ -+#define ELFOSABI_FREEBSD 9 /* FreeBSD. */ -+#define ELFOSABI_TRU64 10 /* Compaq TRU64 UNIX. */ -+#define ELFOSABI_MODESTO 11 /* Novell Modesto. */ -+#define ELFOSABI_OPENBSD 12 /* OpenBSD. */ -+#define ELFOSABI_ARM 97 /* ARM */ -+#define ELFOSABI_STANDALONE 255 /* Standalone (embedded) application */ -+ -+#define EI_ABIVERSION 8 /* ABI version */ -+ -+#define EI_PAD 9 /* Byte index of padding bytes */ -+ -+/* Legal values for e_type (object file type). */ -+ -+#define ET_NONE 0 /* No file type */ -+#define ET_REL 1 /* Relocatable file */ -+#define ET_EXEC 2 /* Executable file */ -+#define ET_DYN 3 /* Shared object file */ -+#define ET_CORE 4 /* Core file */ -+#define ET_NUM 5 /* Number of defined types */ -+#define ET_LOOS 0xfe00 /* OS-specific range start */ -+#define ET_HIOS 0xfeff /* OS-specific range end */ -+#define ET_LOPROC 0xff00 /* Processor-specific range start */ -+#define ET_HIPROC 0xffff /* Processor-specific range end */ -+ -+/* Legal values for e_machine (architecture). */ -+ -+#define EM_NONE 0 /* No machine */ -+#define EM_M32 1 /* AT&T WE 32100 */ -+#define EM_SPARC 2 /* SUN SPARC */ -+#define EM_386 3 /* Intel 80386 */ -+#define EM_68K 4 /* Motorola m68k family */ -+#define EM_88K 5 /* Motorola m88k family */ -+#define EM_860 7 /* Intel 80860 */ -+#define EM_MIPS 8 /* MIPS R3000 big-endian */ -+#define EM_S370 9 /* IBM System/370 */ -+#define EM_MIPS_RS3_LE 10 /* MIPS R3000 little-endian */ -+ -+#define EM_PARISC 15 /* HPPA */ -+#define EM_VPP500 17 /* Fujitsu VPP500 */ -+#define EM_SPARC32PLUS 18 /* Sun's "v8plus" */ -+#define EM_960 19 /* Intel 80960 */ -+#define EM_PPC 20 /* PowerPC */ -+#define EM_PPC64 21 /* PowerPC 64-bit */ -+#define EM_S390 22 /* IBM S390 */ -+ -+#define EM_V800 36 /* NEC V800 series */ -+#define EM_FR20 37 /* Fujitsu FR20 */ -+#define EM_RH32 38 /* TRW RH-32 */ -+#define EM_RCE 39 /* Motorola RCE */ -+#define EM_ARM 40 /* ARM */ -+#define EM_FAKE_ALPHA 41 /* Digital Alpha */ -+#define EM_SH 42 /* Hitachi SH */ -+#define EM_SPARCV9 43 /* SPARC v9 64-bit */ -+#define EM_TRICORE 44 /* Siemens Tricore */ -+#define EM_ARC 45 /* Argonaut RISC Core */ -+#define EM_H8_300 46 /* Hitachi H8/300 */ -+#define EM_H8_300H 47 /* Hitachi H8/300H */ -+#define EM_H8S 48 /* Hitachi H8S */ -+#define EM_H8_500 49 /* Hitachi H8/500 */ -+#define EM_IA_64 50 /* Intel Merced */ -+#define EM_MIPS_X 51 /* Stanford MIPS-X */ -+#define EM_COLDFIRE 52 /* Motorola Coldfire */ -+#define EM_68HC12 53 /* Motorola M68HC12 */ -+#define EM_MMA 54 /* Fujitsu MMA Multimedia Accelerator*/ -+#define EM_PCP 55 /* Siemens PCP */ -+#define EM_NCPU 56 /* Sony nCPU embeeded RISC */ -+#define EM_NDR1 57 /* Denso NDR1 microprocessor */ -+#define EM_STARCORE 58 /* Motorola Start*Core processor */ -+#define EM_ME16 59 /* Toyota ME16 processor */ -+#define EM_ST100 60 /* STMicroelectronic ST100 processor */ -+#define EM_TINYJ 61 /* Advanced Logic Corp. Tinyj emb.fam*/ -+#define EM_X86_64 62 /* AMD x86-64 architecture */ -+#define EM_PDSP 63 /* Sony DSP Processor */ -+ -+#define EM_FX66 66 /* Siemens FX66 microcontroller */ -+#define EM_ST9PLUS 67 /* STMicroelectronics ST9+ 8/16 mc */ -+#define EM_ST7 68 /* STmicroelectronics ST7 8 bit mc */ -+#define EM_68HC16 69 /* Motorola MC68HC16 microcontroller */ -+#define EM_68HC11 70 /* Motorola MC68HC11 microcontroller */ -+#define EM_68HC08 71 /* Motorola MC68HC08 microcontroller */ -+#define EM_68HC05 72 /* Motorola MC68HC05 microcontroller */ -+#define EM_SVX 73 /* Silicon Graphics SVx */ -+#define EM_ST19 74 /* STMicroelectronics ST19 8 bit mc */ -+#define EM_VAX 75 /* Digital VAX */ -+#define EM_CRIS 76 /* Axis Communications 32-bit embedded processor */ -+#define EM_JAVELIN 77 /* Infineon Technologies 32-bit embedded processor */ -+#define EM_FIREPATH 78 /* Element 14 64-bit DSP Processor */ -+#define EM_ZSP 79 /* LSI Logic 16-bit DSP Processor */ -+#define EM_MMIX 80 /* Donald Knuth's educational 64-bit processor */ -+#define EM_HUANY 81 /* Harvard University machine-independent object files */ -+#define EM_PRISM 82 /* SiTera Prism */ -+#define EM_AVR 83 /* Atmel AVR 8-bit microcontroller */ -+#define EM_FR30 84 /* Fujitsu FR30 */ -+#define EM_D10V 85 /* Mitsubishi D10V */ -+#define EM_D30V 86 /* Mitsubishi D30V */ -+#define EM_V850 87 /* NEC v850 */ -+#define EM_M32R 88 /* Mitsubishi M32R */ -+#define EM_MN10300 89 /* Matsushita MN10300 */ -+#define EM_MN10200 90 /* Matsushita MN10200 */ -+#define EM_PJ 91 /* picoJava */ -+#define EM_OPENRISC 92 /* OpenRISC 32-bit embedded processor */ -+#define EM_ARC_A5 93 /* ARC Cores Tangent-A5 */ -+#define EM_XTENSA 94 /* Tensilica Xtensa Architecture */ -+#define EM_NUM 95 -+ -+/* If it is necessary to assign new unofficial EM_* values, please -+ pick large random numbers (0x8523, 0xa7f2, etc.) to minimize the -+ chances of collision with official or non-GNU unofficial values. */ -+ -+#define EM_ALPHA 0x9026 -+ -+/* Legal values for e_version (version). */ -+ -+#define EV_NONE 0 /* Invalid ELF version */ -+#define EV_CURRENT 1 /* Current version */ -+#define EV_NUM 2 -+ -+/* Section header. */ -+ -+typedef struct -+{ -+ Elf32_Word sh_name; /* Section name (string tbl index) */ -+ Elf32_Word sh_type; /* Section type */ -+ Elf32_Word sh_flags; /* Section flags */ -+ Elf32_Addr sh_addr; /* Section virtual addr at execution */ -+ Elf32_Off sh_offset; /* Section file offset */ -+ Elf32_Word sh_size; /* Section size in bytes */ -+ Elf32_Word sh_link; /* Link to another section */ -+ Elf32_Word sh_info; /* Additional section information */ -+ Elf32_Word sh_addralign; /* Section alignment */ -+ Elf32_Word sh_entsize; /* Entry size if section holds table */ -+} Elf32_Shdr; -+ -+typedef struct -+{ -+ Elf64_Word sh_name; /* Section name (string tbl index) */ -+ Elf64_Word sh_type; /* Section type */ -+ Elf64_Xword sh_flags; /* Section flags */ -+ Elf64_Addr sh_addr; /* Section virtual addr at execution */ -+ Elf64_Off sh_offset; /* Section file offset */ -+ Elf64_Xword sh_size; /* Section size in bytes */ -+ Elf64_Word sh_link; /* Link to another section */ -+ Elf64_Word sh_info; /* Additional section information */ -+ Elf64_Xword sh_addralign; /* Section alignment */ -+ Elf64_Xword sh_entsize; /* Entry size if section holds table */ -+} Elf64_Shdr; -+ -+/* Special section indices. */ -+ -+#define SHN_UNDEF 0 /* Undefined section */ -+#define SHN_LORESERVE 0xff00 /* Start of reserved indices */ -+#define SHN_LOPROC 0xff00 /* Start of processor-specific */ -+#define SHN_HIPROC 0xff1f /* End of processor-specific */ -+#define SHN_LOOS 0xff20 /* Start of OS-specific */ -+#define SHN_HIOS 0xff3f /* End of OS-specific */ -+#define SHN_ABS 0xfff1 /* Associated symbol is absolute */ -+#define SHN_COMMON 0xfff2 /* Associated symbol is common */ -+#define SHN_XINDEX 0xffff /* Index is in extra table. */ -+#define SHN_HIRESERVE 0xffff /* End of reserved indices */ -+ -+/* Legal values for sh_type (section type). */ -+ -+#define SHT_NULL 0 /* Section header table entry unused */ -+#define SHT_PROGBITS 1 /* Program data */ -+#define SHT_SYMTAB 2 /* Symbol table */ -+#define SHT_STRTAB 3 /* String table */ -+#define SHT_RELA 4 /* Relocation entries with addends */ -+#define SHT_HASH 5 /* Symbol hash table */ -+#define SHT_DYNAMIC 6 /* Dynamic linking information */ -+#define SHT_NOTE 7 /* Notes */ -+#define SHT_NOBITS 8 /* Program space with no data (bss) */ -+#define SHT_REL 9 /* Relocation entries, no addends */ -+#define SHT_SHLIB 10 /* Reserved */ -+#define SHT_DYNSYM 11 /* Dynamic linker symbol table */ -+#define SHT_INIT_ARRAY 14 /* Array of constructors */ -+#define SHT_FINI_ARRAY 15 /* Array of destructors */ -+#define SHT_PREINIT_ARRAY 16 /* Array of pre-constructors */ -+#define SHT_GROUP 17 /* Section group */ -+#define SHT_SYMTAB_SHNDX 18 /* Extended section indeces */ -+#define SHT_NUM 19 /* Number of defined types. */ -+#define SHT_LOOS 0x60000000 /* Start OS-specific */ -+#define SHT_GNU_LIBLIST 0x6ffffff7 /* Prelink library list */ -+#define SHT_CHECKSUM 0x6ffffff8 /* Checksum for DSO content. */ -+#define SHT_LOSUNW 0x6ffffffa /* Sun-specific low bound. */ -+#define SHT_SUNW_move 0x6ffffffa -+#define SHT_SUNW_COMDAT 0x6ffffffb -+#define SHT_SUNW_syminfo 0x6ffffffc -+#define SHT_GNU_verdef 0x6ffffffd /* Version definition section. */ -+#define SHT_GNU_verneed 0x6ffffffe /* Version needs section. */ -+#define SHT_GNU_versym 0x6fffffff /* Version symbol table. */ -+#define SHT_HISUNW 0x6fffffff /* Sun-specific high bound. */ -+#define SHT_HIOS 0x6fffffff /* End OS-specific type */ -+#define SHT_LOPROC 0x70000000 /* Start of processor-specific */ -+#define SHT_HIPROC 0x7fffffff /* End of processor-specific */ -+#define SHT_LOUSER 0x80000000 /* Start of application-specific */ -+#define SHT_HIUSER 0x8fffffff /* End of application-specific */ -+ -+/* Legal values for sh_flags (section flags). */ -+ -+#define SHF_WRITE (1 << 0) /* Writable */ -+#define SHF_ALLOC (1 << 1) /* Occupies memory during execution */ -+#define SHF_EXECINSTR (1 << 2) /* Executable */ -+#define SHF_MERGE (1 << 4) /* Might be merged */ -+#define SHF_STRINGS (1 << 5) /* Contains nul-terminated strings */ -+#define SHF_INFO_LINK (1 << 6) /* `sh_info' contains SHT index */ -+#define SHF_LINK_ORDER (1 << 7) /* Preserve order after combining */ -+#define SHF_OS_NONCONFORMING (1 << 8) /* Non-standard OS specific handling -+ required */ -+#define SHF_GROUP (1 << 9) /* Section is member of a group. */ -+#define SHF_TLS (1 << 10) /* Section hold thread-local data. */ -+#define SHF_MASKOS 0x0ff00000 /* OS-specific. */ -+#define SHF_MASKPROC 0xf0000000 /* Processor-specific */ -+ -+/* Section group handling. */ -+#define GRP_COMDAT 0x1 /* Mark group as COMDAT. */ -+ -+/* Symbol table entry. */ -+ -+typedef struct -+{ -+ Elf32_Word st_name; /* Symbol name (string tbl index) */ -+ Elf32_Addr st_value; /* Symbol value */ -+ Elf32_Word st_size; /* Symbol size */ -+ unsigned char st_info; /* Symbol type and binding */ -+ unsigned char st_other; /* Symbol visibility */ -+ Elf32_Section st_shndx; /* Section index */ -+} Elf32_Sym; -+ -+typedef struct -+{ -+ Elf64_Word st_name; /* Symbol name (string tbl index) */ -+ unsigned char st_info; /* Symbol type and binding */ -+ unsigned char st_other; /* Symbol visibility */ -+ Elf64_Section st_shndx; /* Section index */ -+ Elf64_Addr st_value; /* Symbol value */ -+ Elf64_Xword st_size; /* Symbol size */ -+} Elf64_Sym; -+ -+/* The syminfo section if available contains additional information about -+ every dynamic symbol. */ -+ -+typedef struct -+{ -+ Elf32_Half si_boundto; /* Direct bindings, symbol bound to */ -+ Elf32_Half si_flags; /* Per symbol flags */ -+} Elf32_Syminfo; -+ -+typedef struct -+{ -+ Elf64_Half si_boundto; /* Direct bindings, symbol bound to */ -+ Elf64_Half si_flags; /* Per symbol flags */ -+} Elf64_Syminfo; -+ -+/* Possible values for si_boundto. */ -+#define SYMINFO_BT_SELF 0xffff /* Symbol bound to self */ -+#define SYMINFO_BT_PARENT 0xfffe /* Symbol bound to parent */ -+#define SYMINFO_BT_LOWRESERVE 0xff00 /* Beginning of reserved entries */ -+ -+/* Possible bitmasks for si_flags. */ -+#define SYMINFO_FLG_DIRECT 0x0001 /* Direct bound symbol */ -+#define SYMINFO_FLG_PASSTHRU 0x0002 /* Pass-thru symbol for translator */ -+#define SYMINFO_FLG_COPY 0x0004 /* Symbol is a copy-reloc */ -+#define SYMINFO_FLG_LAZYLOAD 0x0008 /* Symbol bound to object to be lazy -+ loaded */ -+/* Syminfo version values. */ -+#define SYMINFO_NONE 0 -+#define SYMINFO_CURRENT 1 -+#define SYMINFO_NUM 2 -+ -+ -+/* How to extract and insert information held in the st_info field. */ -+ -+#define ELF32_ST_BIND(val) (((unsigned char) (val)) >> 4) -+#define ELF32_ST_TYPE(val) ((val) & 0xf) -+#define ELF32_ST_INFO(bind, type) (((bind) << 4) + ((type) & 0xf)) -+ -+/* Both Elf32_Sym and Elf64_Sym use the same one-byte st_info field. */ -+#define ELF64_ST_BIND(val) ELF32_ST_BIND (val) -+#define ELF64_ST_TYPE(val) ELF32_ST_TYPE (val) -+#define ELF64_ST_INFO(bind, type) ELF32_ST_INFO ((bind), (type)) -+ -+/* Legal values for ST_BIND subfield of st_info (symbol binding). */ -+ -+#define STB_LOCAL 0 /* Local symbol */ -+#define STB_GLOBAL 1 /* Global symbol */ -+#define STB_WEAK 2 /* Weak symbol */ -+#define STB_NUM 3 /* Number of defined types. */ -+#define STB_LOOS 10 /* Start of OS-specific */ -+#define STB_HIOS 12 /* End of OS-specific */ -+#define STB_LOPROC 13 /* Start of processor-specific */ -+#define STB_HIPROC 15 /* End of processor-specific */ -+ -+/* Legal values for ST_TYPE subfield of st_info (symbol type). */ -+ -+#define STT_NOTYPE 0 /* Symbol type is unspecified */ -+#define STT_OBJECT 1 /* Symbol is a data object */ -+#define STT_FUNC 2 /* Symbol is a code object */ -+#define STT_SECTION 3 /* Symbol associated with a section */ -+#define STT_FILE 4 /* Symbol's name is file name */ -+#define STT_COMMON 5 /* Symbol is a common data object */ -+#define STT_TLS 6 /* Symbol is thread-local data object*/ -+#define STT_NUM 7 /* Number of defined types. */ -+#define STT_LOOS 10 /* Start of OS-specific */ -+#define STT_HIOS 12 /* End of OS-specific */ -+#define STT_LOPROC 13 /* Start of processor-specific */ -+#define STT_HIPROC 15 /* End of processor-specific */ -+ -+ -+/* Symbol table indices are found in the hash buckets and chain table -+ of a symbol hash table section. This special index value indicates -+ the end of a chain, meaning no further symbols are found in that bucket. */ -+ -+#define STN_UNDEF 0 /* End of a chain. */ -+ -+ -+/* How to extract and insert information held in the st_other field. */ -+ -+#define ELF32_ST_VISIBILITY(o) ((o) & 0x03) -+ -+/* For ELF64 the definitions are the same. */ -+#define ELF64_ST_VISIBILITY(o) ELF32_ST_VISIBILITY (o) -+ -+/* Symbol visibility specification encoded in the st_other field. */ -+#define STV_DEFAULT 0 /* Default symbol visibility rules */ -+#define STV_INTERNAL 1 /* Processor specific hidden class */ -+#define STV_HIDDEN 2 /* Sym unavailable in other modules */ -+#define STV_PROTECTED 3 /* Not preemptible, not exported */ -+ -+ -+/* Relocation table entry without addend (in section of type SHT_REL). */ -+ -+typedef struct -+{ -+ Elf32_Addr r_offset; /* Address */ -+ Elf32_Word r_info; /* Relocation type and symbol index */ -+} Elf32_Rel; -+ -+/* I have seen two different definitions of the Elf64_Rel and -+ Elf64_Rela structures, so we'll leave them out until Novell (or -+ whoever) gets their act together. */ -+/* The following, at least, is used on Sparc v9, MIPS, and Alpha. */ -+ -+typedef struct -+{ -+ Elf64_Addr r_offset; /* Address */ -+ Elf64_Xword r_info; /* Relocation type and symbol index */ -+} Elf64_Rel; -+ -+/* Relocation table entry with addend (in section of type SHT_RELA). */ -+ -+typedef struct -+{ -+ Elf32_Addr r_offset; /* Address */ -+ Elf32_Word r_info; /* Relocation type and symbol index */ -+ Elf32_Sword r_addend; /* Addend */ -+} Elf32_Rela; -+ -+typedef struct -+{ -+ Elf64_Addr r_offset; /* Address */ -+ Elf64_Xword r_info; /* Relocation type and symbol index */ -+ Elf64_Sxword r_addend; /* Addend */ -+} Elf64_Rela; -+ -+/* How to extract and insert information held in the r_info field. */ -+ -+#define ELF32_R_SYM(val) ((val) >> 8) -+#define ELF32_R_TYPE(val) ((val) & 0xff) -+#define ELF32_R_INFO(sym, type) (((sym) << 8) + ((type) & 0xff)) -+ -+#define ELF64_R_SYM(i) ((i) >> 32) -+#define ELF64_R_TYPE(i) ((i) & 0xffffffff) -+#define ELF64_R_INFO(sym,type) ((((Elf64_Xword) (sym)) << 32) + (type)) -+ -+/* Program segment header. */ -+ -+typedef struct -+{ -+ Elf32_Word p_type; /* Segment type */ -+ Elf32_Off p_offset; /* Segment file offset */ -+ Elf32_Addr p_vaddr; /* Segment virtual address */ -+ Elf32_Addr p_paddr; /* Segment physical address */ -+ Elf32_Word p_filesz; /* Segment size in file */ -+ Elf32_Word p_memsz; /* Segment size in memory */ -+ Elf32_Word p_flags; /* Segment flags */ -+ Elf32_Word p_align; /* Segment alignment */ -+} Elf32_Phdr; -+ -+typedef struct -+{ -+ Elf64_Word p_type; /* Segment type */ -+ Elf64_Word p_flags; /* Segment flags */ -+ Elf64_Off p_offset; /* Segment file offset */ -+ Elf64_Addr p_vaddr; /* Segment virtual address */ -+ Elf64_Addr p_paddr; /* Segment physical address */ -+ Elf64_Xword p_filesz; /* Segment size in file */ -+ Elf64_Xword p_memsz; /* Segment size in memory */ -+ Elf64_Xword p_align; /* Segment alignment */ -+} Elf64_Phdr; -+ -+/* Legal values for p_type (segment type). */ -+ -+#define PT_NULL 0 /* Program header table entry unused */ -+#define PT_LOAD 1 /* Loadable program segment */ -+#define PT_DYNAMIC 2 /* Dynamic linking information */ -+#define PT_INTERP 3 /* Program interpreter */ -+#define PT_NOTE 4 /* Auxiliary information */ -+#define PT_SHLIB 5 /* Reserved */ -+#define PT_PHDR 6 /* Entry for header table itself */ -+#define PT_TLS 7 /* Thread-local storage segment */ -+#define PT_NUM 8 /* Number of defined types */ -+#define PT_LOOS 0x60000000 /* Start of OS-specific */ -+#define PT_GNU_EH_FRAME 0x6474e550 /* GCC .eh_frame_hdr segment */ -+#define PT_GNU_STACK 0x6474e551 /* Indicates stack executability */ -+#define PT_LOSUNW 0x6ffffffa -+#define PT_SUNWBSS 0x6ffffffa /* Sun Specific segment */ -+#define PT_SUNWSTACK 0x6ffffffb /* Stack segment */ -+#define PT_HISUNW 0x6fffffff -+#define PT_HIOS 0x6fffffff /* End of OS-specific */ -+#define PT_LOPROC 0x70000000 /* Start of processor-specific */ -+#define PT_HIPROC 0x7fffffff /* End of processor-specific */ -+ -+/* Legal values for p_flags (segment flags). */ -+ -+#define PF_X (1 << 0) /* Segment is executable */ -+#define PF_W (1 << 1) /* Segment is writable */ -+#define PF_R (1 << 2) /* Segment is readable */ -+#define PF_MASKOS 0x0ff00000 /* OS-specific */ -+#define PF_MASKPROC 0xf0000000 /* Processor-specific */ -+ -+/* Legal values for note segment descriptor types for core files. */ -+ -+#define NT_PRSTATUS 1 /* Contains copy of prstatus struct */ -+#define NT_FPREGSET 2 /* Contains copy of fpregset struct */ -+#define NT_PRPSINFO 3 /* Contains copy of prpsinfo struct */ -+#define NT_PRXREG 4 /* Contains copy of prxregset struct */ -+#define NT_TASKSTRUCT 4 /* Contains copy of task structure */ -+#define NT_PLATFORM 5 /* String from sysinfo(SI_PLATFORM) */ -+#define NT_AUXV 6 /* Contains copy of auxv array */ -+#define NT_GWINDOWS 7 /* Contains copy of gwindows struct */ -+#define NT_ASRS 8 /* Contains copy of asrset struct */ -+#define NT_PSTATUS 10 /* Contains copy of pstatus struct */ -+#define NT_PSINFO 13 /* Contains copy of psinfo struct */ -+#define NT_PRCRED 14 /* Contains copy of prcred struct */ -+#define NT_UTSNAME 15 /* Contains copy of utsname struct */ -+#define NT_LWPSTATUS 16 /* Contains copy of lwpstatus struct */ -+#define NT_LWPSINFO 17 /* Contains copy of lwpinfo struct */ -+#define NT_PRFPXREG 20 /* Contains copy of fprxregset struct*/ -+ -+/* Legal values for the note segment descriptor types for object files. */ -+ -+#define NT_VERSION 1 /* Contains a version string. */ -+ -+ -+/* Dynamic section entry. */ -+ -+typedef struct -+{ -+ Elf32_Sword d_tag; /* Dynamic entry type */ -+ union -+ { -+ Elf32_Word d_val; /* Integer value */ -+ Elf32_Addr d_ptr; /* Address value */ -+ } d_un; -+} Elf32_Dyn; -+ -+typedef struct -+{ -+ Elf64_Sxword d_tag; /* Dynamic entry type */ -+ union -+ { -+ Elf64_Xword d_val; /* Integer value */ -+ Elf64_Addr d_ptr; /* Address value */ -+ } d_un; -+} Elf64_Dyn; -+ -+/* Legal values for d_tag (dynamic entry type). */ -+ -+#define DT_NULL 0 /* Marks end of dynamic section */ -+#define DT_NEEDED 1 /* Name of needed library */ -+#define DT_PLTRELSZ 2 /* Size in bytes of PLT relocs */ -+#define DT_PLTGOT 3 /* Processor defined value */ -+#define DT_HASH 4 /* Address of symbol hash table */ -+#define DT_STRTAB 5 /* Address of string table */ -+#define DT_SYMTAB 6 /* Address of symbol table */ -+#define DT_RELA 7 /* Address of Rela relocs */ -+#define DT_RELASZ 8 /* Total size of Rela relocs */ -+#define DT_RELAENT 9 /* Size of one Rela reloc */ -+#define DT_STRSZ 10 /* Size of string table */ -+#define DT_SYMENT 11 /* Size of one symbol table entry */ -+#define DT_INIT 12 /* Address of init function */ -+#define DT_FINI 13 /* Address of termination function */ -+#define DT_SONAME 14 /* Name of shared object */ -+#define DT_RPATH 15 /* Library search path (deprecated) */ -+#define DT_SYMBOLIC 16 /* Start symbol search here */ -+#define DT_REL 17 /* Address of Rel relocs */ -+#define DT_RELSZ 18 /* Total size of Rel relocs */ -+#define DT_RELENT 19 /* Size of one Rel reloc */ -+#define DT_PLTREL 20 /* Type of reloc in PLT */ -+#define DT_DEBUG 21 /* For debugging; unspecified */ -+#define DT_TEXTREL 22 /* Reloc might modify .text */ -+#define DT_JMPREL 23 /* Address of PLT relocs */ -+#define DT_BIND_NOW 24 /* Process relocations of object */ -+#define DT_INIT_ARRAY 25 /* Array with addresses of init fct */ -+#define DT_FINI_ARRAY 26 /* Array with addresses of fini fct */ -+#define DT_INIT_ARRAYSZ 27 /* Size in bytes of DT_INIT_ARRAY */ -+#define DT_FINI_ARRAYSZ 28 /* Size in bytes of DT_FINI_ARRAY */ -+#define DT_RUNPATH 29 /* Library search path */ -+#define DT_FLAGS 30 /* Flags for the object being loaded */ -+#define DT_ENCODING 32 /* Start of encoded range */ -+#define DT_PREINIT_ARRAY 32 /* Array with addresses of preinit fct*/ -+#define DT_PREINIT_ARRAYSZ 33 /* size in bytes of DT_PREINIT_ARRAY */ -+#define DT_NUM 34 /* Number used */ -+#define DT_LOOS 0x6000000d /* Start of OS-specific */ -+#define DT_HIOS 0x6ffff000 /* End of OS-specific */ -+#define DT_LOPROC 0x70000000 /* Start of processor-specific */ -+#define DT_HIPROC 0x7fffffff /* End of processor-specific */ -+#define DT_PROCNUM DT_MIPS_NUM /* Most used by any processor */ -+ -+/* DT_* entries which fall between DT_VALRNGHI & DT_VALRNGLO use the -+ Dyn.d_un.d_val field of the Elf*_Dyn structure. This follows Sun's -+ approach. */ -+#define DT_VALRNGLO 0x6ffffd00 -+#define DT_GNU_PRELINKED 0x6ffffdf5 /* Prelinking timestamp */ -+#define DT_GNU_CONFLICTSZ 0x6ffffdf6 /* Size of conflict section */ -+#define DT_GNU_LIBLISTSZ 0x6ffffdf7 /* Size of library list */ -+#define DT_CHECKSUM 0x6ffffdf8 -+#define DT_PLTPADSZ 0x6ffffdf9 -+#define DT_MOVEENT 0x6ffffdfa -+#define DT_MOVESZ 0x6ffffdfb -+#define DT_FEATURE_1 0x6ffffdfc /* Feature selection (DTF_*). */ -+#define DT_POSFLAG_1 0x6ffffdfd /* Flags for DT_* entries, effecting -+ the following DT_* entry. */ -+#define DT_SYMINSZ 0x6ffffdfe /* Size of syminfo table (in bytes) */ -+#define DT_SYMINENT 0x6ffffdff /* Entry size of syminfo */ -+#define DT_VALRNGHI 0x6ffffdff -+#define DT_VALTAGIDX(tag) (DT_VALRNGHI - (tag)) /* Reverse order! */ -+#define DT_VALNUM 12 -+ -+/* DT_* entries which fall between DT_ADDRRNGHI & DT_ADDRRNGLO use the -+ Dyn.d_un.d_ptr field of the Elf*_Dyn structure. -+ -+ If any adjustment is made to the ELF object after it has been -+ built these entries will need to be adjusted. */ -+#define DT_ADDRRNGLO 0x6ffffe00 -+#define DT_GNU_CONFLICT 0x6ffffef8 /* Start of conflict section */ -+#define DT_GNU_LIBLIST 0x6ffffef9 /* Library list */ -+#define DT_CONFIG 0x6ffffefa /* Configuration information. */ -+#define DT_DEPAUDIT 0x6ffffefb /* Dependency auditing. */ -+#define DT_AUDIT 0x6ffffefc /* Object auditing. */ -+#define DT_PLTPAD 0x6ffffefd /* PLT padding. */ -+#define DT_MOVETAB 0x6ffffefe /* Move table. */ -+#define DT_SYMINFO 0x6ffffeff /* Syminfo table. */ -+#define DT_ADDRRNGHI 0x6ffffeff -+#define DT_ADDRTAGIDX(tag) (DT_ADDRRNGHI - (tag)) /* Reverse order! */ -+#define DT_ADDRNUM 10 -+ -+/* The versioning entry types. The next are defined as part of the -+ GNU extension. */ -+#define DT_VERSYM 0x6ffffff0 -+ -+#define DT_RELACOUNT 0x6ffffff9 -+#define DT_RELCOUNT 0x6ffffffa -+ -+/* These were chosen by Sun. */ -+#define DT_FLAGS_1 0x6ffffffb /* State flags, see DF_1_* below. */ -+#define DT_VERDEF 0x6ffffffc /* Address of version definition -+ table */ -+#define DT_VERDEFNUM 0x6ffffffd /* Number of version definitions */ -+#define DT_VERNEED 0x6ffffffe /* Address of table with needed -+ versions */ -+#define DT_VERNEEDNUM 0x6fffffff /* Number of needed versions */ -+#define DT_VERSIONTAGIDX(tag) (DT_VERNEEDNUM - (tag)) /* Reverse order! */ -+#define DT_VERSIONTAGNUM 16 -+ -+/* Sun added these machine-independent extensions in the "processor-specific" -+ range. Be compatible. */ -+#define DT_AUXILIARY 0x7ffffffd /* Shared object to load before self */ -+#define DT_FILTER 0x7fffffff /* Shared object to get values from */ -+#define DT_EXTRATAGIDX(tag) ((Elf32_Word)-((Elf32_Sword) (tag) <<1>>1)-1) -+#define DT_EXTRANUM 3 -+ -+/* Values of `d_un.d_val' in the DT_FLAGS entry. */ -+#define DF_ORIGIN 0x00000001 /* Object may use DF_ORIGIN */ -+#define DF_SYMBOLIC 0x00000002 /* Symbol resolutions starts here */ -+#define DF_TEXTREL 0x00000004 /* Object contains text relocations */ -+#define DF_BIND_NOW 0x00000008 /* No lazy binding for this object */ -+#define DF_STATIC_TLS 0x00000010 /* Module uses the static TLS model */ -+ -+/* State flags selectable in the `d_un.d_val' element of the DT_FLAGS_1 -+ entry in the dynamic section. */ -+#define DF_1_NOW 0x00000001 /* Set RTLD_NOW for this object. */ -+#define DF_1_GLOBAL 0x00000002 /* Set RTLD_GLOBAL for this object. */ -+#define DF_1_GROUP 0x00000004 /* Set RTLD_GROUP for this object. */ -+#define DF_1_NODELETE 0x00000008 /* Set RTLD_NODELETE for this object.*/ -+#define DF_1_LOADFLTR 0x00000010 /* Trigger filtee loading at runtime.*/ -+#define DF_1_INITFIRST 0x00000020 /* Set RTLD_INITFIRST for this object*/ -+#define DF_1_NOOPEN 0x00000040 /* Set RTLD_NOOPEN for this object. */ -+#define DF_1_ORIGIN 0x00000080 /* $ORIGIN must be handled. */ -+#define DF_1_DIRECT 0x00000100 /* Direct binding enabled. */ -+#define DF_1_TRANS 0x00000200 -+#define DF_1_INTERPOSE 0x00000400 /* Object is used to interpose. */ -+#define DF_1_NODEFLIB 0x00000800 /* Ignore default lib search path. */ -+#define DF_1_NODUMP 0x00001000 /* Object can't be dldump'ed. */ -+#define DF_1_CONFALT 0x00002000 /* Configuration alternative created.*/ -+#define DF_1_ENDFILTEE 0x00004000 /* Filtee terminates filters search. */ -+#define DF_1_DISPRELDNE 0x00008000 /* Disp reloc applied at build time. */ -+#define DF_1_DISPRELPND 0x00010000 /* Disp reloc applied at run-time. */ -+ -+/* Flags for the feature selection in DT_FEATURE_1. */ -+#define DTF_1_PARINIT 0x00000001 -+#define DTF_1_CONFEXP 0x00000002 -+ -+/* Flags in the DT_POSFLAG_1 entry effecting only the next DT_* entry. */ -+#define DF_P1_LAZYLOAD 0x00000001 /* Lazyload following object. */ -+#define DF_P1_GROUPPERM 0x00000002 /* Symbols from next object are not -+ generally available. */ -+ -+/* Version definition sections. */ -+ -+typedef struct -+{ -+ Elf32_Half vd_version; /* Version revision */ -+ Elf32_Half vd_flags; /* Version information */ -+ Elf32_Half vd_ndx; /* Version Index */ -+ Elf32_Half vd_cnt; /* Number of associated aux entries */ -+ Elf32_Word vd_hash; /* Version name hash value */ -+ Elf32_Word vd_aux; /* Offset in bytes to verdaux array */ -+ Elf32_Word vd_next; /* Offset in bytes to next verdef -+ entry */ -+} Elf32_Verdef; -+ -+typedef struct -+{ -+ Elf64_Half vd_version; /* Version revision */ -+ Elf64_Half vd_flags; /* Version information */ -+ Elf64_Half vd_ndx; /* Version Index */ -+ Elf64_Half vd_cnt; /* Number of associated aux entries */ -+ Elf64_Word vd_hash; /* Version name hash value */ -+ Elf64_Word vd_aux; /* Offset in bytes to verdaux array */ -+ Elf64_Word vd_next; /* Offset in bytes to next verdef -+ entry */ -+} Elf64_Verdef; -+ -+ -+/* Legal values for vd_version (version revision). */ -+#define VER_DEF_NONE 0 /* No version */ -+#define VER_DEF_CURRENT 1 /* Current version */ -+#define VER_DEF_NUM 2 /* Given version number */ -+ -+/* Legal values for vd_flags (version information flags). */ -+#define VER_FLG_BASE 0x1 /* Version definition of file itself */ -+#define VER_FLG_WEAK 0x2 /* Weak version identifier */ -+ -+/* Versym symbol index values. */ -+#define VER_NDX_LOCAL 0 /* Symbol is local. */ -+#define VER_NDX_GLOBAL 1 /* Symbol is global. */ -+#define VER_NDX_LORESERVE 0xff00 /* Beginning of reserved entries. */ -+#define VER_NDX_ELIMINATE 0xff01 /* Symbol is to be eliminated. */ -+ -+/* Auxialiary version information. */ -+ -+typedef struct -+{ -+ Elf32_Word vda_name; /* Version or dependency names */ -+ Elf32_Word vda_next; /* Offset in bytes to next verdaux -+ entry */ -+} Elf32_Verdaux; -+ -+typedef struct -+{ -+ Elf64_Word vda_name; /* Version or dependency names */ -+ Elf64_Word vda_next; /* Offset in bytes to next verdaux -+ entry */ -+} Elf64_Verdaux; -+ -+ -+/* Version dependency section. */ -+ -+typedef struct -+{ -+ Elf32_Half vn_version; /* Version of structure */ -+ Elf32_Half vn_cnt; /* Number of associated aux entries */ -+ Elf32_Word vn_file; /* Offset of filename for this -+ dependency */ -+ Elf32_Word vn_aux; /* Offset in bytes to vernaux array */ -+ Elf32_Word vn_next; /* Offset in bytes to next verneed -+ entry */ -+} Elf32_Verneed; -+ -+typedef struct -+{ -+ Elf64_Half vn_version; /* Version of structure */ -+ Elf64_Half vn_cnt; /* Number of associated aux entries */ -+ Elf64_Word vn_file; /* Offset of filename for this -+ dependency */ -+ Elf64_Word vn_aux; /* Offset in bytes to vernaux array */ -+ Elf64_Word vn_next; /* Offset in bytes to next verneed -+ entry */ -+} Elf64_Verneed; -+ -+ -+/* Legal values for vn_version (version revision). */ -+#define VER_NEED_NONE 0 /* No version */ -+#define VER_NEED_CURRENT 1 /* Current version */ -+#define VER_NEED_NUM 2 /* Given version number */ -+ -+/* Auxiliary needed version information. */ -+ -+typedef struct -+{ -+ Elf32_Word vna_hash; /* Hash value of dependency name */ -+ Elf32_Half vna_flags; /* Dependency specific information */ -+ Elf32_Half vna_other; /* Unused */ -+ Elf32_Word vna_name; /* Dependency name string offset */ -+ Elf32_Word vna_next; /* Offset in bytes to next vernaux -+ entry */ -+} Elf32_Vernaux; -+ -+typedef struct -+{ -+ Elf64_Word vna_hash; /* Hash value of dependency name */ -+ Elf64_Half vna_flags; /* Dependency specific information */ -+ Elf64_Half vna_other; /* Unused */ -+ Elf64_Word vna_name; /* Dependency name string offset */ -+ Elf64_Word vna_next; /* Offset in bytes to next vernaux -+ entry */ -+} Elf64_Vernaux; -+ -+ -+/* Legal values for vna_flags. */ -+#define VER_FLG_WEAK 0x2 /* Weak version identifier */ -+ -+ -+/* Auxiliary vector. */ -+ -+/* This vector is normally only used by the program interpreter. The -+ usual definition in an ABI supplement uses the name auxv_t. The -+ vector is not usually defined in a standard file, but it -+ can't hurt. We rename it to avoid conflicts. The sizes of these -+ types are an arrangement between the exec server and the program -+ interpreter, so we don't fully specify them here. */ -+ -+typedef struct -+{ -+ int a_type; /* Entry type */ -+ union -+ { -+ long int a_val; /* Integer value */ -+ void *a_ptr; /* Pointer value */ -+ void (*a_fcn) (void); /* Function pointer value */ -+ } a_un; -+} Elf32_auxv_t; -+ -+typedef struct -+{ -+ long int a_type; /* Entry type */ -+ union -+ { -+ long int a_val; /* Integer value */ -+ void *a_ptr; /* Pointer value */ -+ void (*a_fcn) (void); /* Function pointer value */ -+ } a_un; -+} Elf64_auxv_t; -+ -+/* Legal values for a_type (entry type). */ -+ -+#define AT_NULL 0 /* End of vector */ -+#define AT_IGNORE 1 /* Entry should be ignored */ -+#define AT_EXECFD 2 /* File descriptor of program */ -+#define AT_PHDR 3 /* Program headers for program */ -+#define AT_PHENT 4 /* Size of program header entry */ -+#define AT_PHNUM 5 /* Number of program headers */ -+#define AT_PAGESZ 6 /* System page size */ -+#define AT_BASE 7 /* Base address of interpreter */ -+#define AT_FLAGS 8 /* Flags */ -+#define AT_ENTRY 9 /* Entry point of program */ -+#define AT_NOTELF 10 /* Program is not ELF */ -+#define AT_UID 11 /* Real uid */ -+#define AT_EUID 12 /* Effective uid */ -+#define AT_GID 13 /* Real gid */ -+#define AT_EGID 14 /* Effective gid */ -+#define AT_CLKTCK 17 /* Frequency of times() */ -+ -+/* Some more special a_type values describing the hardware. */ -+#define AT_PLATFORM 15 /* String identifying platform. */ -+#define AT_HWCAP 16 /* Machine dependent hints about -+ processor capabilities. */ -+ -+/* This entry gives some information about the FPU initialization -+ performed by the kernel. */ -+#define AT_FPUCW 18 /* Used FPU control word. */ -+ -+/* Cache block sizes. */ -+#define AT_DCACHEBSIZE 19 /* Data cache block size. */ -+#define AT_ICACHEBSIZE 20 /* Instruction cache block size. */ -+#define AT_UCACHEBSIZE 21 /* Unified cache block size. */ -+ -+/* A special ignored value for PPC, used by the kernel to control the -+ interpretation of the AUXV. Must be > 16. */ -+#define AT_IGNOREPPC 22 /* Entry should be ignored. */ -+ -+#define AT_SECURE 23 /* Boolean, was exec setuid-like? */ -+ -+/* Pointer to the global system page used for system calls and other -+ nice things. */ -+#define AT_SYSINFO 32 -+#define AT_SYSINFO_EHDR 33 -+ -+ -+/* Note section contents. Each entry in the note section begins with -+ a header of a fixed form. */ -+ -+typedef struct -+{ -+ Elf32_Word n_namesz; /* Length of the note's name. */ -+ Elf32_Word n_descsz; /* Length of the note's descriptor. */ -+ Elf32_Word n_type; /* Type of the note. */ -+} Elf32_Nhdr; -+ -+typedef struct -+{ -+ Elf64_Word n_namesz; /* Length of the note's name. */ -+ Elf64_Word n_descsz; /* Length of the note's descriptor. */ -+ Elf64_Word n_type; /* Type of the note. */ -+} Elf64_Nhdr; -+ -+/* Known names of notes. */ -+ -+/* Solaris entries in the note section have this name. */ -+#define ELF_NOTE_SOLARIS "SUNW Solaris" -+ -+/* Note entries for GNU systems have this name. */ -+#define ELF_NOTE_GNU "GNU" -+ -+ -+/* Defined types of notes for Solaris. */ -+ -+/* Value of descriptor (one word) is desired pagesize for the binary. */ -+#define ELF_NOTE_PAGESIZE_HINT 1 -+ -+ -+/* Defined note types for GNU systems. */ -+ -+/* ABI information. The descriptor consists of words: -+ word 0: OS descriptor -+ word 1: major version of the ABI -+ word 2: minor version of the ABI -+ word 3: subminor version of the ABI -+*/ -+#define ELF_NOTE_ABI 1 -+ -+/* Known OSes. These value can appear in word 0 of an ELF_NOTE_ABI -+ note section entry. */ -+#define ELF_NOTE_OS_LINUX 0 -+#define ELF_NOTE_OS_GNU 1 -+#define ELF_NOTE_OS_SOLARIS2 2 -+#define ELF_NOTE_OS_FREEBSD 3 -+ -+ -+/* Move records. */ -+typedef struct -+{ -+ Elf32_Xword m_value; /* Symbol value. */ -+ Elf32_Word m_info; /* Size and index. */ -+ Elf32_Word m_poffset; /* Symbol offset. */ -+ Elf32_Half m_repeat; /* Repeat count. */ -+ Elf32_Half m_stride; /* Stride info. */ -+} Elf32_Move; -+ -+typedef struct -+{ -+ Elf64_Xword m_value; /* Symbol value. */ -+ Elf64_Xword m_info; /* Size and index. */ -+ Elf64_Xword m_poffset; /* Symbol offset. */ -+ Elf64_Half m_repeat; /* Repeat count. */ -+ Elf64_Half m_stride; /* Stride info. */ -+} Elf64_Move; -+ -+/* Macro to construct move records. */ -+#define ELF32_M_SYM(info) ((info) >> 8) -+#define ELF32_M_SIZE(info) ((unsigned char) (info)) -+#define ELF32_M_INFO(sym, size) (((sym) << 8) + (unsigned char) (size)) -+ -+#define ELF64_M_SYM(info) ELF32_M_SYM (info) -+#define ELF64_M_SIZE(info) ELF32_M_SIZE (info) -+#define ELF64_M_INFO(sym, size) ELF32_M_INFO (sym, size) -+ -+ -+/* Motorola 68k specific definitions. */ -+ -+/* Values for Elf32_Ehdr.e_flags. */ -+#define EF_CPU32 0x00810000 -+ -+/* m68k relocs. */ -+ -+#define R_68K_NONE 0 /* No reloc */ -+#define R_68K_32 1 /* Direct 32 bit */ -+#define R_68K_16 2 /* Direct 16 bit */ -+#define R_68K_8 3 /* Direct 8 bit */ -+#define R_68K_PC32 4 /* PC relative 32 bit */ -+#define R_68K_PC16 5 /* PC relative 16 bit */ -+#define R_68K_PC8 6 /* PC relative 8 bit */ -+#define R_68K_GOT32 7 /* 32 bit PC relative GOT entry */ -+#define R_68K_GOT16 8 /* 16 bit PC relative GOT entry */ -+#define R_68K_GOT8 9 /* 8 bit PC relative GOT entry */ -+#define R_68K_GOT32O 10 /* 32 bit GOT offset */ -+#define R_68K_GOT16O 11 /* 16 bit GOT offset */ -+#define R_68K_GOT8O 12 /* 8 bit GOT offset */ -+#define R_68K_PLT32 13 /* 32 bit PC relative PLT address */ -+#define R_68K_PLT16 14 /* 16 bit PC relative PLT address */ -+#define R_68K_PLT8 15 /* 8 bit PC relative PLT address */ -+#define R_68K_PLT32O 16 /* 32 bit PLT offset */ -+#define R_68K_PLT16O 17 /* 16 bit PLT offset */ -+#define R_68K_PLT8O 18 /* 8 bit PLT offset */ -+#define R_68K_COPY 19 /* Copy symbol at runtime */ -+#define R_68K_GLOB_DAT 20 /* Create GOT entry */ -+#define R_68K_JMP_SLOT 21 /* Create PLT entry */ -+#define R_68K_RELATIVE 22 /* Adjust by program base */ -+/* Keep this the last entry. */ -+#define R_68K_NUM 23 -+ -+/* Intel 80386 specific definitions. */ -+ -+/* i386 relocs. */ -+ -+#define R_386_NONE 0 /* No reloc */ -+#define R_386_32 1 /* Direct 32 bit */ -+#define R_386_PC32 2 /* PC relative 32 bit */ -+#define R_386_GOT32 3 /* 32 bit GOT entry */ -+#define R_386_PLT32 4 /* 32 bit PLT address */ -+#define R_386_COPY 5 /* Copy symbol at runtime */ -+#define R_386_GLOB_DAT 6 /* Create GOT entry */ -+#define R_386_JMP_SLOT 7 /* Create PLT entry */ -+#define R_386_RELATIVE 8 /* Adjust by program base */ -+#define R_386_GOTOFF 9 /* 32 bit offset to GOT */ -+#define R_386_GOTPC 10 /* 32 bit PC relative offset to GOT */ -+#define R_386_32PLT 11 -+#define R_386_TLS_TPOFF 14 /* Offset in static TLS block */ -+#define R_386_TLS_IE 15 /* Address of GOT entry for static TLS -+ block offset */ -+#define R_386_TLS_GOTIE 16 /* GOT entry for static TLS block -+ offset */ -+#define R_386_TLS_LE 17 /* Offset relative to static TLS -+ block */ -+#define R_386_TLS_GD 18 /* Direct 32 bit for GNU version of -+ general dynamic thread local data */ -+#define R_386_TLS_LDM 19 /* Direct 32 bit for GNU version of -+ local dynamic thread local data -+ in LE code */ -+#define R_386_16 20 -+#define R_386_PC16 21 -+#define R_386_8 22 -+#define R_386_PC8 23 -+#define R_386_TLS_GD_32 24 /* Direct 32 bit for general dynamic -+ thread local data */ -+#define R_386_TLS_GD_PUSH 25 /* Tag for pushl in GD TLS code */ -+#define R_386_TLS_GD_CALL 26 /* Relocation for call to -+ __tls_get_addr() */ -+#define R_386_TLS_GD_POP 27 /* Tag for popl in GD TLS code */ -+#define R_386_TLS_LDM_32 28 /* Direct 32 bit for local dynamic -+ thread local data in LE code */ -+#define R_386_TLS_LDM_PUSH 29 /* Tag for pushl in LDM TLS code */ -+#define R_386_TLS_LDM_CALL 30 /* Relocation for call to -+ __tls_get_addr() in LDM code */ -+#define R_386_TLS_LDM_POP 31 /* Tag for popl in LDM TLS code */ -+#define R_386_TLS_LDO_32 32 /* Offset relative to TLS block */ -+#define R_386_TLS_IE_32 33 /* GOT entry for negated static TLS -+ block offset */ -+#define R_386_TLS_LE_32 34 /* Negated offset relative to static -+ TLS block */ -+#define R_386_TLS_DTPMOD32 35 /* ID of module containing symbol */ -+#define R_386_TLS_DTPOFF32 36 /* Offset in TLS block */ -+#define R_386_TLS_TPOFF32 37 /* Negated offset in static TLS block */ -+/* Keep this the last entry. */ -+#define R_386_NUM 38 -+ -+/* SUN SPARC specific definitions. */ -+ -+/* Legal values for ST_TYPE subfield of st_info (symbol type). */ -+ -+#define STT_REGISTER 13 /* Global register reserved to app. */ -+ -+/* Values for Elf64_Ehdr.e_flags. */ -+ -+#define EF_SPARCV9_MM 3 -+#define EF_SPARCV9_TSO 0 -+#define EF_SPARCV9_PSO 1 -+#define EF_SPARCV9_RMO 2 -+#define EF_SPARC_LEDATA 0x800000 /* little endian data */ -+#define EF_SPARC_EXT_MASK 0xFFFF00 -+#define EF_SPARC_32PLUS 0x000100 /* generic V8+ features */ -+#define EF_SPARC_SUN_US1 0x000200 /* Sun UltraSPARC1 extensions */ -+#define EF_SPARC_HAL_R1 0x000400 /* HAL R1 extensions */ -+#define EF_SPARC_SUN_US3 0x000800 /* Sun UltraSPARCIII extensions */ -+ -+/* SPARC relocs. */ -+ -+#define R_SPARC_NONE 0 /* No reloc */ -+#define R_SPARC_8 1 /* Direct 8 bit */ -+#define R_SPARC_16 2 /* Direct 16 bit */ -+#define R_SPARC_32 3 /* Direct 32 bit */ -+#define R_SPARC_DISP8 4 /* PC relative 8 bit */ -+#define R_SPARC_DISP16 5 /* PC relative 16 bit */ -+#define R_SPARC_DISP32 6 /* PC relative 32 bit */ -+#define R_SPARC_WDISP30 7 /* PC relative 30 bit shifted */ -+#define R_SPARC_WDISP22 8 /* PC relative 22 bit shifted */ -+#define R_SPARC_HI22 9 /* High 22 bit */ -+#define R_SPARC_22 10 /* Direct 22 bit */ -+#define R_SPARC_13 11 /* Direct 13 bit */ -+#define R_SPARC_LO10 12 /* Truncated 10 bit */ -+#define R_SPARC_GOT10 13 /* Truncated 10 bit GOT entry */ -+#define R_SPARC_GOT13 14 /* 13 bit GOT entry */ -+#define R_SPARC_GOT22 15 /* 22 bit GOT entry shifted */ -+#define R_SPARC_PC10 16 /* PC relative 10 bit truncated */ -+#define R_SPARC_PC22 17 /* PC relative 22 bit shifted */ -+#define R_SPARC_WPLT30 18 /* 30 bit PC relative PLT address */ -+#define R_SPARC_COPY 19 /* Copy symbol at runtime */ -+#define R_SPARC_GLOB_DAT 20 /* Create GOT entry */ -+#define R_SPARC_JMP_SLOT 21 /* Create PLT entry */ -+#define R_SPARC_RELATIVE 22 /* Adjust by program base */ -+#define R_SPARC_UA32 23 /* Direct 32 bit unaligned */ -+ -+/* Additional Sparc64 relocs. */ -+ -+#define R_SPARC_PLT32 24 /* Direct 32 bit ref to PLT entry */ -+#define R_SPARC_HIPLT22 25 /* High 22 bit PLT entry */ -+#define R_SPARC_LOPLT10 26 /* Truncated 10 bit PLT entry */ -+#define R_SPARC_PCPLT32 27 /* PC rel 32 bit ref to PLT entry */ -+#define R_SPARC_PCPLT22 28 /* PC rel high 22 bit PLT entry */ -+#define R_SPARC_PCPLT10 29 /* PC rel trunc 10 bit PLT entry */ -+#define R_SPARC_10 30 /* Direct 10 bit */ -+#define R_SPARC_11 31 /* Direct 11 bit */ -+#define R_SPARC_64 32 /* Direct 64 bit */ -+#define R_SPARC_OLO10 33 /* 10bit with secondary 13bit addend */ -+#define R_SPARC_HH22 34 /* Top 22 bits of direct 64 bit */ -+#define R_SPARC_HM10 35 /* High middle 10 bits of ... */ -+#define R_SPARC_LM22 36 /* Low middle 22 bits of ... */ -+#define R_SPARC_PC_HH22 37 /* Top 22 bits of pc rel 64 bit */ -+#define R_SPARC_PC_HM10 38 /* High middle 10 bit of ... */ -+#define R_SPARC_PC_LM22 39 /* Low miggle 22 bits of ... */ -+#define R_SPARC_WDISP16 40 /* PC relative 16 bit shifted */ -+#define R_SPARC_WDISP19 41 /* PC relative 19 bit shifted */ -+#define R_SPARC_7 43 /* Direct 7 bit */ -+#define R_SPARC_5 44 /* Direct 5 bit */ -+#define R_SPARC_6 45 /* Direct 6 bit */ -+#define R_SPARC_DISP64 46 /* PC relative 64 bit */ -+#define R_SPARC_PLT64 47 /* Direct 64 bit ref to PLT entry */ -+#define R_SPARC_HIX22 48 /* High 22 bit complemented */ -+#define R_SPARC_LOX10 49 /* Truncated 11 bit complemented */ -+#define R_SPARC_H44 50 /* Direct high 12 of 44 bit */ -+#define R_SPARC_M44 51 /* Direct mid 22 of 44 bit */ -+#define R_SPARC_L44 52 /* Direct low 10 of 44 bit */ -+#define R_SPARC_REGISTER 53 /* Global register usage */ -+#define R_SPARC_UA64 54 /* Direct 64 bit unaligned */ -+#define R_SPARC_UA16 55 /* Direct 16 bit unaligned */ -+#define R_SPARC_TLS_GD_HI22 56 -+#define R_SPARC_TLS_GD_LO10 57 -+#define R_SPARC_TLS_GD_ADD 58 -+#define R_SPARC_TLS_GD_CALL 59 -+#define R_SPARC_TLS_LDM_HI22 60 -+#define R_SPARC_TLS_LDM_LO10 61 -+#define R_SPARC_TLS_LDM_ADD 62 -+#define R_SPARC_TLS_LDM_CALL 63 -+#define R_SPARC_TLS_LDO_HIX22 64 -+#define R_SPARC_TLS_LDO_LOX10 65 -+#define R_SPARC_TLS_LDO_ADD 66 -+#define R_SPARC_TLS_IE_HI22 67 -+#define R_SPARC_TLS_IE_LO10 68 -+#define R_SPARC_TLS_IE_LD 69 -+#define R_SPARC_TLS_IE_LDX 70 -+#define R_SPARC_TLS_IE_ADD 71 -+#define R_SPARC_TLS_LE_HIX22 72 -+#define R_SPARC_TLS_LE_LOX10 73 -+#define R_SPARC_TLS_DTPMOD32 74 -+#define R_SPARC_TLS_DTPMOD64 75 -+#define R_SPARC_TLS_DTPOFF32 76 -+#define R_SPARC_TLS_DTPOFF64 77 -+#define R_SPARC_TLS_TPOFF32 78 -+#define R_SPARC_TLS_TPOFF64 79 -+/* Keep this the last entry. */ -+#define R_SPARC_NUM 80 -+ -+/* For Sparc64, legal values for d_tag of Elf64_Dyn. */ -+ -+#define DT_SPARC_REGISTER 0x70000001 -+#define DT_SPARC_NUM 2 -+ -+/* Bits present in AT_HWCAP, primarily for Sparc32. */ -+ -+#define HWCAP_SPARC_FLUSH 1 /* The cpu supports flush insn. */ -+#define HWCAP_SPARC_STBAR 2 -+#define HWCAP_SPARC_SWAP 4 -+#define HWCAP_SPARC_MULDIV 8 -+#define HWCAP_SPARC_V9 16 /* The cpu is v9, so v8plus is ok. */ -+#define HWCAP_SPARC_ULTRA3 32 -+ -+/* MIPS R3000 specific definitions. */ -+ -+/* Legal values for e_flags field of Elf32_Ehdr. */ -+ -+#define EF_MIPS_NOREORDER 1 /* A .noreorder directive was used */ -+#define EF_MIPS_PIC 2 /* Contains PIC code */ -+#define EF_MIPS_CPIC 4 /* Uses PIC calling sequence */ -+#define EF_MIPS_XGOT 8 -+#define EF_MIPS_64BIT_WHIRL 16 -+#define EF_MIPS_ABI2 32 -+#define EF_MIPS_ABI_ON32 64 -+#define EF_MIPS_ARCH 0xf0000000 /* MIPS architecture level */ -+ -+/* Legal values for MIPS architecture level. */ -+ -+#define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ -+#define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ -+#define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ -+#define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ -+#define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ -+#define EF_MIPS_ARCH_32 0x60000000 /* MIPS32 code. */ -+#define EF_MIPS_ARCH_64 0x70000000 /* MIPS64 code. */ -+ -+/* The following are non-official names and should not be used. */ -+ -+#define E_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ -+#define E_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ -+#define E_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ -+#define E_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ -+#define E_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ -+#define E_MIPS_ARCH_32 0x60000000 /* MIPS32 code. */ -+#define E_MIPS_ARCH_64 0x70000000 /* MIPS64 code. */ -+ -+/* Special section indices. */ -+ -+#define SHN_MIPS_ACOMMON 0xff00 /* Allocated common symbols */ -+#define SHN_MIPS_TEXT 0xff01 /* Allocated test symbols. */ -+#define SHN_MIPS_DATA 0xff02 /* Allocated data symbols. */ -+#define SHN_MIPS_SCOMMON 0xff03 /* Small common symbols */ -+#define SHN_MIPS_SUNDEFINED 0xff04 /* Small undefined symbols */ -+ -+/* Legal values for sh_type field of Elf32_Shdr. */ -+ -+#define SHT_MIPS_LIBLIST 0x70000000 /* Shared objects used in link */ -+#define SHT_MIPS_MSYM 0x70000001 -+#define SHT_MIPS_CONFLICT 0x70000002 /* Conflicting symbols */ -+#define SHT_MIPS_GPTAB 0x70000003 /* Global data area sizes */ -+#define SHT_MIPS_UCODE 0x70000004 /* Reserved for SGI/MIPS compilers */ -+#define SHT_MIPS_DEBUG 0x70000005 /* MIPS ECOFF debugging information*/ -+#define SHT_MIPS_REGINFO 0x70000006 /* Register usage information */ -+#define SHT_MIPS_PACKAGE 0x70000007 -+#define SHT_MIPS_PACKSYM 0x70000008 -+#define SHT_MIPS_RELD 0x70000009 -+#define SHT_MIPS_IFACE 0x7000000b -+#define SHT_MIPS_CONTENT 0x7000000c -+#define SHT_MIPS_OPTIONS 0x7000000d /* Miscellaneous options. */ -+#define SHT_MIPS_SHDR 0x70000010 -+#define SHT_MIPS_FDESC 0x70000011 -+#define SHT_MIPS_EXTSYM 0x70000012 -+#define SHT_MIPS_DENSE 0x70000013 -+#define SHT_MIPS_PDESC 0x70000014 -+#define SHT_MIPS_LOCSYM 0x70000015 -+#define SHT_MIPS_AUXSYM 0x70000016 -+#define SHT_MIPS_OPTSYM 0x70000017 -+#define SHT_MIPS_LOCSTR 0x70000018 -+#define SHT_MIPS_LINE 0x70000019 -+#define SHT_MIPS_RFDESC 0x7000001a -+#define SHT_MIPS_DELTASYM 0x7000001b -+#define SHT_MIPS_DELTAINST 0x7000001c -+#define SHT_MIPS_DELTACLASS 0x7000001d -+#define SHT_MIPS_DWARF 0x7000001e /* DWARF debugging information. */ -+#define SHT_MIPS_DELTADECL 0x7000001f -+#define SHT_MIPS_SYMBOL_LIB 0x70000020 -+#define SHT_MIPS_EVENTS 0x70000021 /* Event section. */ -+#define SHT_MIPS_TRANSLATE 0x70000022 -+#define SHT_MIPS_PIXIE 0x70000023 -+#define SHT_MIPS_XLATE 0x70000024 -+#define SHT_MIPS_XLATE_DEBUG 0x70000025 -+#define SHT_MIPS_WHIRL 0x70000026 -+#define SHT_MIPS_EH_REGION 0x70000027 -+#define SHT_MIPS_XLATE_OLD 0x70000028 -+#define SHT_MIPS_PDR_EXCEPTION 0x70000029 -+ -+/* Legal values for sh_flags field of Elf32_Shdr. */ -+ -+#define SHF_MIPS_GPREL 0x10000000 /* Must be part of global data area */ -+#define SHF_MIPS_MERGE 0x20000000 -+#define SHF_MIPS_ADDR 0x40000000 -+#define SHF_MIPS_STRINGS 0x80000000 -+#define SHF_MIPS_NOSTRIP 0x08000000 -+#define SHF_MIPS_LOCAL 0x04000000 -+#define SHF_MIPS_NAMES 0x02000000 -+#define SHF_MIPS_NODUPE 0x01000000 -+ -+ -+/* Symbol tables. */ -+ -+/* MIPS specific values for `st_other'. */ -+#define STO_MIPS_DEFAULT 0x0 -+#define STO_MIPS_INTERNAL 0x1 -+#define STO_MIPS_HIDDEN 0x2 -+#define STO_MIPS_PROTECTED 0x3 -+#define STO_MIPS_SC_ALIGN_UNUSED 0xff -+ -+/* MIPS specific values for `st_info'. */ -+#define STB_MIPS_SPLIT_COMMON 13 -+ -+/* Entries found in sections of type SHT_MIPS_GPTAB. */ -+ -+typedef union -+{ -+ struct -+ { -+ Elf32_Word gt_current_g_value; /* -G value used for compilation */ -+ Elf32_Word gt_unused; /* Not used */ -+ } gt_header; /* First entry in section */ -+ struct -+ { -+ Elf32_Word gt_g_value; /* If this value were used for -G */ -+ Elf32_Word gt_bytes; /* This many bytes would be used */ -+ } gt_entry; /* Subsequent entries in section */ -+} Elf32_gptab; -+ -+/* Entry found in sections of type SHT_MIPS_REGINFO. */ -+ -+typedef struct -+{ -+ Elf32_Word ri_gprmask; /* General registers used */ -+ Elf32_Word ri_cprmask[4]; /* Coprocessor registers used */ -+ Elf32_Sword ri_gp_value; /* $gp register value */ -+} Elf32_RegInfo; -+ -+/* Entries found in sections of type SHT_MIPS_OPTIONS. */ -+ -+typedef struct -+{ -+ unsigned char kind; /* Determines interpretation of the -+ variable part of descriptor. */ -+ unsigned char size; /* Size of descriptor, including header. */ -+ Elf32_Section section; /* Section header index of section affected, -+ 0 for global options. */ -+ Elf32_Word info; /* Kind-specific information. */ -+} Elf_Options; -+ -+/* Values for `kind' field in Elf_Options. */ -+ -+#define ODK_NULL 0 /* Undefined. */ -+#define ODK_REGINFO 1 /* Register usage information. */ -+#define ODK_EXCEPTIONS 2 /* Exception processing options. */ -+#define ODK_PAD 3 /* Section padding options. */ -+#define ODK_HWPATCH 4 /* Hardware workarounds performed */ -+#define ODK_FILL 5 /* record the fill value used by the linker. */ -+#define ODK_TAGS 6 /* reserve space for desktop tools to write. */ -+#define ODK_HWAND 7 /* HW workarounds. 'AND' bits when merging. */ -+#define ODK_HWOR 8 /* HW workarounds. 'OR' bits when merging. */ -+ -+/* Values for `info' in Elf_Options for ODK_EXCEPTIONS entries. */ -+ -+#define OEX_FPU_MIN 0x1f /* FPE's which MUST be enabled. */ -+#define OEX_FPU_MAX 0x1f00 /* FPE's which MAY be enabled. */ -+#define OEX_PAGE0 0x10000 /* page zero must be mapped. */ -+#define OEX_SMM 0x20000 /* Force sequential memory mode? */ -+#define OEX_FPDBUG 0x40000 /* Force floating point debug mode? */ -+#define OEX_PRECISEFP OEX_FPDBUG -+#define OEX_DISMISS 0x80000 /* Dismiss invalid address faults? */ -+ -+#define OEX_FPU_INVAL 0x10 -+#define OEX_FPU_DIV0 0x08 -+#define OEX_FPU_OFLO 0x04 -+#define OEX_FPU_UFLO 0x02 -+#define OEX_FPU_INEX 0x01 -+ -+/* Masks for `info' in Elf_Options for an ODK_HWPATCH entry. */ -+ -+#define OHW_R4KEOP 0x1 /* R4000 end-of-page patch. */ -+#define OHW_R8KPFETCH 0x2 /* may need R8000 prefetch patch. */ -+#define OHW_R5KEOP 0x4 /* R5000 end-of-page patch. */ -+#define OHW_R5KCVTL 0x8 /* R5000 cvt.[ds].l bug. clean=1. */ -+ -+#define OPAD_PREFIX 0x1 -+#define OPAD_POSTFIX 0x2 -+#define OPAD_SYMBOL 0x4 -+ -+/* Entry found in `.options' section. */ -+ -+typedef struct -+{ -+ Elf32_Word hwp_flags1; /* Extra flags. */ -+ Elf32_Word hwp_flags2; /* Extra flags. */ -+} Elf_Options_Hw; -+ -+/* Masks for `info' in ElfOptions for ODK_HWAND and ODK_HWOR entries. */ -+ -+#define OHWA0_R4KEOP_CHECKED 0x00000001 -+#define OHWA1_R4KEOP_CLEAN 0x00000002 -+ -+/* MIPS relocs. */ -+ -+#define R_MIPS_NONE 0 /* No reloc */ -+#define R_MIPS_16 1 /* Direct 16 bit */ -+#define R_MIPS_32 2 /* Direct 32 bit */ -+#define R_MIPS_REL32 3 /* PC relative 32 bit */ -+#define R_MIPS_26 4 /* Direct 26 bit shifted */ -+#define R_MIPS_HI16 5 /* High 16 bit */ -+#define R_MIPS_LO16 6 /* Low 16 bit */ -+#define R_MIPS_GPREL16 7 /* GP relative 16 bit */ -+#define R_MIPS_LITERAL 8 /* 16 bit literal entry */ -+#define R_MIPS_GOT16 9 /* 16 bit GOT entry */ -+#define R_MIPS_PC16 10 /* PC relative 16 bit */ -+#define R_MIPS_CALL16 11 /* 16 bit GOT entry for function */ -+#define R_MIPS_GPREL32 12 /* GP relative 32 bit */ -+ -+#define R_MIPS_SHIFT5 16 -+#define R_MIPS_SHIFT6 17 -+#define R_MIPS_64 18 -+#define R_MIPS_GOT_DISP 19 -+#define R_MIPS_GOT_PAGE 20 -+#define R_MIPS_GOT_OFST 21 -+#define R_MIPS_GOT_HI16 22 -+#define R_MIPS_GOT_LO16 23 -+#define R_MIPS_SUB 24 -+#define R_MIPS_INSERT_A 25 -+#define R_MIPS_INSERT_B 26 -+#define R_MIPS_DELETE 27 -+#define R_MIPS_HIGHER 28 -+#define R_MIPS_HIGHEST 29 -+#define R_MIPS_CALL_HI16 30 -+#define R_MIPS_CALL_LO16 31 -+#define R_MIPS_SCN_DISP 32 -+#define R_MIPS_REL16 33 -+#define R_MIPS_ADD_IMMEDIATE 34 -+#define R_MIPS_PJUMP 35 -+#define R_MIPS_RELGOT 36 -+#define R_MIPS_JALR 37 -+/* Keep this the last entry. */ -+#define R_MIPS_NUM 38 -+ -+/* Legal values for p_type field of Elf32_Phdr. */ -+ -+#define PT_MIPS_REGINFO 0x70000000 /* Register usage information */ -+#define PT_MIPS_RTPROC 0x70000001 /* Runtime procedure table. */ -+#define PT_MIPS_OPTIONS 0x70000002 -+ -+/* Special program header types. */ -+ -+#define PF_MIPS_LOCAL 0x10000000 -+ -+/* Legal values for d_tag field of Elf32_Dyn. */ -+ -+#define DT_MIPS_RLD_VERSION 0x70000001 /* Runtime linker interface version */ -+#define DT_MIPS_TIME_STAMP 0x70000002 /* Timestamp */ -+#define DT_MIPS_ICHECKSUM 0x70000003 /* Checksum */ -+#define DT_MIPS_IVERSION 0x70000004 /* Version string (string tbl index) */ -+#define DT_MIPS_FLAGS 0x70000005 /* Flags */ -+#define DT_MIPS_BASE_ADDRESS 0x70000006 /* Base address */ -+#define DT_MIPS_MSYM 0x70000007 -+#define DT_MIPS_CONFLICT 0x70000008 /* Address of CONFLICT section */ -+#define DT_MIPS_LIBLIST 0x70000009 /* Address of LIBLIST section */ -+#define DT_MIPS_LOCAL_GOTNO 0x7000000a /* Number of local GOT entries */ -+#define DT_MIPS_CONFLICTNO 0x7000000b /* Number of CONFLICT entries */ -+#define DT_MIPS_LIBLISTNO 0x70000010 /* Number of LIBLIST entries */ -+#define DT_MIPS_SYMTABNO 0x70000011 /* Number of DYNSYM entries */ -+#define DT_MIPS_UNREFEXTNO 0x70000012 /* First external DYNSYM */ -+#define DT_MIPS_GOTSYM 0x70000013 /* First GOT entry in DYNSYM */ -+#define DT_MIPS_HIPAGENO 0x70000014 /* Number of GOT page table entries */ -+#define DT_MIPS_RLD_MAP 0x70000016 /* Address of run time loader map. */ -+#define DT_MIPS_DELTA_CLASS 0x70000017 /* Delta C++ class definition. */ -+#define DT_MIPS_DELTA_CLASS_NO 0x70000018 /* Number of entries in -+ DT_MIPS_DELTA_CLASS. */ -+#define DT_MIPS_DELTA_INSTANCE 0x70000019 /* Delta C++ class instances. */ -+#define DT_MIPS_DELTA_INSTANCE_NO 0x7000001a /* Number of entries in -+ DT_MIPS_DELTA_INSTANCE. */ -+#define DT_MIPS_DELTA_RELOC 0x7000001b /* Delta relocations. */ -+#define DT_MIPS_DELTA_RELOC_NO 0x7000001c /* Number of entries in -+ DT_MIPS_DELTA_RELOC. */ -+#define DT_MIPS_DELTA_SYM 0x7000001d /* Delta symbols that Delta -+ relocations refer to. */ -+#define DT_MIPS_DELTA_SYM_NO 0x7000001e /* Number of entries in -+ DT_MIPS_DELTA_SYM. */ -+#define DT_MIPS_DELTA_CLASSSYM 0x70000020 /* Delta symbols that hold the -+ class declaration. */ -+#define DT_MIPS_DELTA_CLASSSYM_NO 0x70000021 /* Number of entries in -+ DT_MIPS_DELTA_CLASSSYM. */ -+#define DT_MIPS_CXX_FLAGS 0x70000022 /* Flags indicating for C++ flavor. */ -+#define DT_MIPS_PIXIE_INIT 0x70000023 -+#define DT_MIPS_SYMBOL_LIB 0x70000024 -+#define DT_MIPS_LOCALPAGE_GOTIDX 0x70000025 -+#define DT_MIPS_LOCAL_GOTIDX 0x70000026 -+#define DT_MIPS_HIDDEN_GOTIDX 0x70000027 -+#define DT_MIPS_PROTECTED_GOTIDX 0x70000028 -+#define DT_MIPS_OPTIONS 0x70000029 /* Address of .options. */ -+#define DT_MIPS_INTERFACE 0x7000002a /* Address of .interface. */ -+#define DT_MIPS_DYNSTR_ALIGN 0x7000002b -+#define DT_MIPS_INTERFACE_SIZE 0x7000002c /* Size of the .interface section. */ -+#define DT_MIPS_RLD_TEXT_RESOLVE_ADDR 0x7000002d /* Address of rld_text_rsolve -+ function stored in GOT. */ -+#define DT_MIPS_PERF_SUFFIX 0x7000002e /* Default suffix of dso to be added -+ by rld on dlopen() calls. */ -+#define DT_MIPS_COMPACT_SIZE 0x7000002f /* (O32)Size of compact rel section. */ -+#define DT_MIPS_GP_VALUE 0x70000030 /* GP value for aux GOTs. */ -+#define DT_MIPS_AUX_DYNAMIC 0x70000031 /* Address of aux .dynamic. */ -+#define DT_MIPS_NUM 0x32 -+ -+/* Legal values for DT_MIPS_FLAGS Elf32_Dyn entry. */ -+ -+#define RHF_NONE 0 /* No flags */ -+#define RHF_QUICKSTART (1 << 0) /* Use quickstart */ -+#define RHF_NOTPOT (1 << 1) /* Hash size not power of 2 */ -+#define RHF_NO_LIBRARY_REPLACEMENT (1 << 2) /* Ignore LD_LIBRARY_PATH */ -+#define RHF_NO_MOVE (1 << 3) -+#define RHF_SGI_ONLY (1 << 4) -+#define RHF_GUARANTEE_INIT (1 << 5) -+#define RHF_DELTA_C_PLUS_PLUS (1 << 6) -+#define RHF_GUARANTEE_START_INIT (1 << 7) -+#define RHF_PIXIE (1 << 8) -+#define RHF_DEFAULT_DELAY_LOAD (1 << 9) -+#define RHF_REQUICKSTART (1 << 10) -+#define RHF_REQUICKSTARTED (1 << 11) -+#define RHF_CORD (1 << 12) -+#define RHF_NO_UNRES_UNDEF (1 << 13) -+#define RHF_RLD_ORDER_SAFE (1 << 14) -+ -+/* Entries found in sections of type SHT_MIPS_LIBLIST. */ -+ -+typedef struct -+{ -+ Elf32_Word l_name; /* Name (string table index) */ -+ Elf32_Word l_time_stamp; /* Timestamp */ -+ Elf32_Word l_checksum; /* Checksum */ -+ Elf32_Word l_version; /* Interface version */ -+ Elf32_Word l_flags; /* Flags */ -+} Elf32_Lib; -+ -+typedef struct -+{ -+ Elf64_Word l_name; /* Name (string table index) */ -+ Elf64_Word l_time_stamp; /* Timestamp */ -+ Elf64_Word l_checksum; /* Checksum */ -+ Elf64_Word l_version; /* Interface version */ -+ Elf64_Word l_flags; /* Flags */ -+} Elf64_Lib; -+ -+ -+/* Legal values for l_flags. */ -+ -+#define LL_NONE 0 -+#define LL_EXACT_MATCH (1 << 0) /* Require exact match */ -+#define LL_IGNORE_INT_VER (1 << 1) /* Ignore interface version */ -+#define LL_REQUIRE_MINOR (1 << 2) -+#define LL_EXPORTS (1 << 3) -+#define LL_DELAY_LOAD (1 << 4) -+#define LL_DELTA (1 << 5) -+ -+/* Entries found in sections of type SHT_MIPS_CONFLICT. */ -+ -+typedef Elf32_Addr Elf32_Conflict; -+ -+ -+/* HPPA specific definitions. */ -+ -+/* Legal values for e_flags field of Elf32_Ehdr. */ -+ -+#define EF_PARISC_TRAPNIL 0x00010000 /* Trap nil pointer dereference. */ -+#define EF_PARISC_EXT 0x00020000 /* Program uses arch. extensions. */ -+#define EF_PARISC_LSB 0x00040000 /* Program expects little endian. */ -+#define EF_PARISC_WIDE 0x00080000 /* Program expects wide mode. */ -+#define EF_PARISC_NO_KABP 0x00100000 /* No kernel assisted branch -+ prediction. */ -+#define EF_PARISC_LAZYSWAP 0x00400000 /* Allow lazy swapping. */ -+#define EF_PARISC_ARCH 0x0000ffff /* Architecture version. */ -+ -+/* Defined values for `e_flags & EF_PARISC_ARCH' are: */ -+ -+#define EFA_PARISC_1_0 0x020b /* PA-RISC 1.0 big-endian. */ -+#define EFA_PARISC_1_1 0x0210 /* PA-RISC 1.1 big-endian. */ -+#define EFA_PARISC_2_0 0x0214 /* PA-RISC 2.0 big-endian. */ -+ -+/* Additional section indeces. */ -+ -+#define SHN_PARISC_ANSI_COMMON 0xff00 /* Section for tenatively declared -+ symbols in ANSI C. */ -+#define SHN_PARISC_HUGE_COMMON 0xff01 /* Common blocks in huge model. */ -+ -+/* Legal values for sh_type field of Elf32_Shdr. */ -+ -+#define SHT_PARISC_EXT 0x70000000 /* Contains product specific ext. */ -+#define SHT_PARISC_UNWIND 0x70000001 /* Unwind information. */ -+#define SHT_PARISC_DOC 0x70000002 /* Debug info for optimized code. */ -+ -+/* Legal values for sh_flags field of Elf32_Shdr. */ -+ -+#define SHF_PARISC_SHORT 0x20000000 /* Section with short addressing. */ -+#define SHF_PARISC_HUGE 0x40000000 /* Section far from gp. */ -+#define SHF_PARISC_SBP 0x80000000 /* Static branch prediction code. */ -+ -+/* Legal values for ST_TYPE subfield of st_info (symbol type). */ -+ -+#define STT_PARISC_MILLICODE 13 /* Millicode function entry point. */ -+ -+#define STT_HP_OPAQUE (STT_LOOS + 0x1) -+#define STT_HP_STUB (STT_LOOS + 0x2) -+ -+/* HPPA relocs. */ -+ -+#define R_PARISC_NONE 0 /* No reloc. */ -+#define R_PARISC_DIR32 1 /* Direct 32-bit reference. */ -+#define R_PARISC_DIR21L 2 /* Left 21 bits of eff. address. */ -+#define R_PARISC_DIR17R 3 /* Right 17 bits of eff. address. */ -+#define R_PARISC_DIR17F 4 /* 17 bits of eff. address. */ -+#define R_PARISC_DIR14R 6 /* Right 14 bits of eff. address. */ -+#define R_PARISC_PCREL32 9 /* 32-bit rel. address. */ -+#define R_PARISC_PCREL21L 10 /* Left 21 bits of rel. address. */ -+#define R_PARISC_PCREL17R 11 /* Right 17 bits of rel. address. */ -+#define R_PARISC_PCREL17F 12 /* 17 bits of rel. address. */ -+#define R_PARISC_PCREL14R 14 /* Right 14 bits of rel. address. */ -+#define R_PARISC_DPREL21L 18 /* Left 21 bits of rel. address. */ -+#define R_PARISC_DPREL14R 22 /* Right 14 bits of rel. address. */ -+#define R_PARISC_GPREL21L 26 /* GP-relative, left 21 bits. */ -+#define R_PARISC_GPREL14R 30 /* GP-relative, right 14 bits. */ -+#define R_PARISC_LTOFF21L 34 /* LT-relative, left 21 bits. */ -+#define R_PARISC_LTOFF14R 38 /* LT-relative, right 14 bits. */ -+#define R_PARISC_SECREL32 41 /* 32 bits section rel. address. */ -+#define R_PARISC_SEGBASE 48 /* No relocation, set segment base. */ -+#define R_PARISC_SEGREL32 49 /* 32 bits segment rel. address. */ -+#define R_PARISC_PLTOFF21L 50 /* PLT rel. address, left 21 bits. */ -+#define R_PARISC_PLTOFF14R 54 /* PLT rel. address, right 14 bits. */ -+#define R_PARISC_LTOFF_FPTR32 57 /* 32 bits LT-rel. function pointer. */ -+#define R_PARISC_LTOFF_FPTR21L 58 /* LT-rel. fct ptr, left 21 bits. */ -+#define R_PARISC_LTOFF_FPTR14R 62 /* LT-rel. fct ptr, right 14 bits. */ -+#define R_PARISC_FPTR64 64 /* 64 bits function address. */ -+#define R_PARISC_PLABEL32 65 /* 32 bits function address. */ -+#define R_PARISC_PCREL64 72 /* 64 bits PC-rel. address. */ -+#define R_PARISC_PCREL22F 74 /* 22 bits PC-rel. address. */ -+#define R_PARISC_PCREL14WR 75 /* PC-rel. address, right 14 bits. */ -+#define R_PARISC_PCREL14DR 76 /* PC rel. address, right 14 bits. */ -+#define R_PARISC_PCREL16F 77 /* 16 bits PC-rel. address. */ -+#define R_PARISC_PCREL16WF 78 /* 16 bits PC-rel. address. */ -+#define R_PARISC_PCREL16DF 79 /* 16 bits PC-rel. address. */ -+#define R_PARISC_DIR64 80 /* 64 bits of eff. address. */ -+#define R_PARISC_DIR14WR 83 /* 14 bits of eff. address. */ -+#define R_PARISC_DIR14DR 84 /* 14 bits of eff. address. */ -+#define R_PARISC_DIR16F 85 /* 16 bits of eff. address. */ -+#define R_PARISC_DIR16WF 86 /* 16 bits of eff. address. */ -+#define R_PARISC_DIR16DF 87 /* 16 bits of eff. address. */ -+#define R_PARISC_GPREL64 88 /* 64 bits of GP-rel. address. */ -+#define R_PARISC_GPREL14WR 91 /* GP-rel. address, right 14 bits. */ -+#define R_PARISC_GPREL14DR 92 /* GP-rel. address, right 14 bits. */ -+#define R_PARISC_GPREL16F 93 /* 16 bits GP-rel. address. */ -+#define R_PARISC_GPREL16WF 94 /* 16 bits GP-rel. address. */ -+#define R_PARISC_GPREL16DF 95 /* 16 bits GP-rel. address. */ -+#define R_PARISC_LTOFF64 96 /* 64 bits LT-rel. address. */ -+#define R_PARISC_LTOFF14WR 99 /* LT-rel. address, right 14 bits. */ -+#define R_PARISC_LTOFF14DR 100 /* LT-rel. address, right 14 bits. */ -+#define R_PARISC_LTOFF16F 101 /* 16 bits LT-rel. address. */ -+#define R_PARISC_LTOFF16WF 102 /* 16 bits LT-rel. address. */ -+#define R_PARISC_LTOFF16DF 103 /* 16 bits LT-rel. address. */ -+#define R_PARISC_SECREL64 104 /* 64 bits section rel. address. */ -+#define R_PARISC_SEGREL64 112 /* 64 bits segment rel. address. */ -+#define R_PARISC_PLTOFF14WR 115 /* PLT-rel. address, right 14 bits. */ -+#define R_PARISC_PLTOFF14DR 116 /* PLT-rel. address, right 14 bits. */ -+#define R_PARISC_PLTOFF16F 117 /* 16 bits LT-rel. address. */ -+#define R_PARISC_PLTOFF16WF 118 /* 16 bits PLT-rel. address. */ -+#define R_PARISC_PLTOFF16DF 119 /* 16 bits PLT-rel. address. */ -+#define R_PARISC_LTOFF_FPTR64 120 /* 64 bits LT-rel. function ptr. */ -+#define R_PARISC_LTOFF_FPTR14WR 123 /* LT-rel. fct. ptr., right 14 bits. */ -+#define R_PARISC_LTOFF_FPTR14DR 124 /* LT-rel. fct. ptr., right 14 bits. */ -+#define R_PARISC_LTOFF_FPTR16F 125 /* 16 bits LT-rel. function ptr. */ -+#define R_PARISC_LTOFF_FPTR16WF 126 /* 16 bits LT-rel. function ptr. */ -+#define R_PARISC_LTOFF_FPTR16DF 127 /* 16 bits LT-rel. function ptr. */ -+#define R_PARISC_LORESERVE 128 -+#define R_PARISC_COPY 128 /* Copy relocation. */ -+#define R_PARISC_IPLT 129 /* Dynamic reloc, imported PLT */ -+#define R_PARISC_EPLT 130 /* Dynamic reloc, exported PLT */ -+#define R_PARISC_TPREL32 153 /* 32 bits TP-rel. address. */ -+#define R_PARISC_TPREL21L 154 /* TP-rel. address, left 21 bits. */ -+#define R_PARISC_TPREL14R 158 /* TP-rel. address, right 14 bits. */ -+#define R_PARISC_LTOFF_TP21L 162 /* LT-TP-rel. address, left 21 bits. */ -+#define R_PARISC_LTOFF_TP14R 166 /* LT-TP-rel. address, right 14 bits.*/ -+#define R_PARISC_LTOFF_TP14F 167 /* 14 bits LT-TP-rel. address. */ -+#define R_PARISC_TPREL64 216 /* 64 bits TP-rel. address. */ -+#define R_PARISC_TPREL14WR 219 /* TP-rel. address, right 14 bits. */ -+#define R_PARISC_TPREL14DR 220 /* TP-rel. address, right 14 bits. */ -+#define R_PARISC_TPREL16F 221 /* 16 bits TP-rel. address. */ -+#define R_PARISC_TPREL16WF 222 /* 16 bits TP-rel. address. */ -+#define R_PARISC_TPREL16DF 223 /* 16 bits TP-rel. address. */ -+#define R_PARISC_LTOFF_TP64 224 /* 64 bits LT-TP-rel. address. */ -+#define R_PARISC_LTOFF_TP14WR 227 /* LT-TP-rel. address, right 14 bits.*/ -+#define R_PARISC_LTOFF_TP14DR 228 /* LT-TP-rel. address, right 14 bits.*/ -+#define R_PARISC_LTOFF_TP16F 229 /* 16 bits LT-TP-rel. address. */ -+#define R_PARISC_LTOFF_TP16WF 230 /* 16 bits LT-TP-rel. address. */ -+#define R_PARISC_LTOFF_TP16DF 231 /* 16 bits LT-TP-rel. address. */ -+#define R_PARISC_HIRESERVE 255 -+ -+/* Legal values for p_type field of Elf32_Phdr/Elf64_Phdr. */ -+ -+#define PT_HP_TLS (PT_LOOS + 0x0) -+#define PT_HP_CORE_NONE (PT_LOOS + 0x1) -+#define PT_HP_CORE_VERSION (PT_LOOS + 0x2) -+#define PT_HP_CORE_KERNEL (PT_LOOS + 0x3) -+#define PT_HP_CORE_COMM (PT_LOOS + 0x4) -+#define PT_HP_CORE_PROC (PT_LOOS + 0x5) -+#define PT_HP_CORE_LOADABLE (PT_LOOS + 0x6) -+#define PT_HP_CORE_STACK (PT_LOOS + 0x7) -+#define PT_HP_CORE_SHM (PT_LOOS + 0x8) -+#define PT_HP_CORE_MMF (PT_LOOS + 0x9) -+#define PT_HP_PARALLEL (PT_LOOS + 0x10) -+#define PT_HP_FASTBIND (PT_LOOS + 0x11) -+#define PT_HP_OPT_ANNOT (PT_LOOS + 0x12) -+#define PT_HP_HSL_ANNOT (PT_LOOS + 0x13) -+#define PT_HP_STACK (PT_LOOS + 0x14) -+ -+#define PT_PARISC_ARCHEXT 0x70000000 -+#define PT_PARISC_UNWIND 0x70000001 -+ -+/* Legal values for p_flags field of Elf32_Phdr/Elf64_Phdr. */ -+ -+#define PF_PARISC_SBP 0x08000000 -+ -+#define PF_HP_PAGE_SIZE 0x00100000 -+#define PF_HP_FAR_SHARED 0x00200000 -+#define PF_HP_NEAR_SHARED 0x00400000 -+#define PF_HP_CODE 0x01000000 -+#define PF_HP_MODIFY 0x02000000 -+#define PF_HP_LAZYSWAP 0x04000000 -+#define PF_HP_SBP 0x08000000 -+ -+ -+/* Alpha specific definitions. */ -+ -+/* Legal values for e_flags field of Elf64_Ehdr. */ -+ -+#define EF_ALPHA_32BIT 1 /* All addresses must be < 2GB. */ -+#define EF_ALPHA_CANRELAX 2 /* Relocations for relaxing exist. */ -+ -+/* Legal values for sh_type field of Elf64_Shdr. */ -+ -+/* These two are primerily concerned with ECOFF debugging info. */ -+#define SHT_ALPHA_DEBUG 0x70000001 -+#define SHT_ALPHA_REGINFO 0x70000002 -+ -+/* Legal values for sh_flags field of Elf64_Shdr. */ -+ -+#define SHF_ALPHA_GPREL 0x10000000 -+ -+/* Legal values for st_other field of Elf64_Sym. */ -+#define STO_ALPHA_NOPV 0x80 /* No PV required. */ -+#define STO_ALPHA_STD_GPLOAD 0x88 /* PV only used for initial ldgp. */ -+ -+/* Alpha relocs. */ -+ -+#define R_ALPHA_NONE 0 /* No reloc */ -+#define R_ALPHA_REFLONG 1 /* Direct 32 bit */ -+#define R_ALPHA_REFQUAD 2 /* Direct 64 bit */ -+#define R_ALPHA_GPREL32 3 /* GP relative 32 bit */ -+#define R_ALPHA_LITERAL 4 /* GP relative 16 bit w/optimization */ -+#define R_ALPHA_LITUSE 5 /* Optimization hint for LITERAL */ -+#define R_ALPHA_GPDISP 6 /* Add displacement to GP */ -+#define R_ALPHA_BRADDR 7 /* PC+4 relative 23 bit shifted */ -+#define R_ALPHA_HINT 8 /* PC+4 relative 16 bit shifted */ -+#define R_ALPHA_SREL16 9 /* PC relative 16 bit */ -+#define R_ALPHA_SREL32 10 /* PC relative 32 bit */ -+#define R_ALPHA_SREL64 11 /* PC relative 64 bit */ -+#define R_ALPHA_GPRELHIGH 17 /* GP relative 32 bit, high 16 bits */ -+#define R_ALPHA_GPRELLOW 18 /* GP relative 32 bit, low 16 bits */ -+#define R_ALPHA_GPREL16 19 /* GP relative 16 bit */ -+#define R_ALPHA_COPY 24 /* Copy symbol at runtime */ -+#define R_ALPHA_GLOB_DAT 25 /* Create GOT entry */ -+#define R_ALPHA_JMP_SLOT 26 /* Create PLT entry */ -+#define R_ALPHA_RELATIVE 27 /* Adjust by program base */ -+#define R_ALPHA_TLS_GD_HI 28 -+#define R_ALPHA_TLSGD 29 -+#define R_ALPHA_TLS_LDM 30 -+#define R_ALPHA_DTPMOD64 31 -+#define R_ALPHA_GOTDTPREL 32 -+#define R_ALPHA_DTPREL64 33 -+#define R_ALPHA_DTPRELHI 34 -+#define R_ALPHA_DTPRELLO 35 -+#define R_ALPHA_DTPREL16 36 -+#define R_ALPHA_GOTTPREL 37 -+#define R_ALPHA_TPREL64 38 -+#define R_ALPHA_TPRELHI 39 -+#define R_ALPHA_TPRELLO 40 -+#define R_ALPHA_TPREL16 41 -+/* Keep this the last entry. */ -+#define R_ALPHA_NUM 46 -+ -+/* Magic values of the LITUSE relocation addend. */ -+#define LITUSE_ALPHA_ADDR 0 -+#define LITUSE_ALPHA_BASE 1 -+#define LITUSE_ALPHA_BYTOFF 2 -+#define LITUSE_ALPHA_JSR 3 -+#define LITUSE_ALPHA_TLS_GD 4 -+#define LITUSE_ALPHA_TLS_LDM 5 -+ -+ -+/* PowerPC specific declarations */ -+ -+/* Values for Elf32/64_Ehdr.e_flags. */ -+#define EF_PPC_EMB 0x80000000 /* PowerPC embedded flag */ -+ -+/* Cygnus local bits below */ -+#define EF_PPC_RELOCATABLE 0x00010000 /* PowerPC -mrelocatable flag*/ -+#define EF_PPC_RELOCATABLE_LIB 0x00008000 /* PowerPC -mrelocatable-lib -+ flag */ -+ -+/* PowerPC relocations defined by the ABIs */ -+#define R_PPC_NONE 0 -+#define R_PPC_ADDR32 1 /* 32bit absolute address */ -+#define R_PPC_ADDR24 2 /* 26bit address, 2 bits ignored. */ -+#define R_PPC_ADDR16 3 /* 16bit absolute address */ -+#define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */ -+#define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */ -+#define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */ -+#define R_PPC_ADDR14 7 /* 16bit address, 2 bits ignored */ -+#define R_PPC_ADDR14_BRTAKEN 8 -+#define R_PPC_ADDR14_BRNTAKEN 9 -+#define R_PPC_REL24 10 /* PC relative 26 bit */ -+#define R_PPC_REL14 11 /* PC relative 16 bit */ -+#define R_PPC_REL14_BRTAKEN 12 -+#define R_PPC_REL14_BRNTAKEN 13 -+#define R_PPC_GOT16 14 -+#define R_PPC_GOT16_LO 15 -+#define R_PPC_GOT16_HI 16 -+#define R_PPC_GOT16_HA 17 -+#define R_PPC_PLTREL24 18 -+#define R_PPC_COPY 19 -+#define R_PPC_GLOB_DAT 20 -+#define R_PPC_JMP_SLOT 21 -+#define R_PPC_RELATIVE 22 -+#define R_PPC_LOCAL24PC 23 -+#define R_PPC_UADDR32 24 -+#define R_PPC_UADDR16 25 -+#define R_PPC_REL32 26 -+#define R_PPC_PLT32 27 -+#define R_PPC_PLTREL32 28 -+#define R_PPC_PLT16_LO 29 -+#define R_PPC_PLT16_HI 30 -+#define R_PPC_PLT16_HA 31 -+#define R_PPC_SDAREL16 32 -+#define R_PPC_SECTOFF 33 -+#define R_PPC_SECTOFF_LO 34 -+#define R_PPC_SECTOFF_HI 35 -+#define R_PPC_SECTOFF_HA 36 -+ -+/* PowerPC relocations defined for the TLS access ABI. */ -+#define R_PPC_TLS 67 /* none (sym+add)@tls */ -+#define R_PPC_DTPMOD32 68 /* word32 (sym+add)@dtpmod */ -+#define R_PPC_TPREL16 69 /* half16* (sym+add)@tprel */ -+#define R_PPC_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */ -+#define R_PPC_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */ -+#define R_PPC_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */ -+#define R_PPC_TPREL32 73 /* word32 (sym+add)@tprel */ -+#define R_PPC_DTPREL16 74 /* half16* (sym+add)@dtprel */ -+#define R_PPC_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */ -+#define R_PPC_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */ -+#define R_PPC_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */ -+#define R_PPC_DTPREL32 78 /* word32 (sym+add)@dtprel */ -+#define R_PPC_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */ -+#define R_PPC_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */ -+#define R_PPC_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */ -+#define R_PPC_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */ -+#define R_PPC_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */ -+#define R_PPC_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */ -+#define R_PPC_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */ -+#define R_PPC_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */ -+#define R_PPC_GOT_TPREL16 87 /* half16* (sym+add)@got@tprel */ -+#define R_PPC_GOT_TPREL16_LO 88 /* half16 (sym+add)@got@tprel@l */ -+#define R_PPC_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */ -+#define R_PPC_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */ -+#define R_PPC_GOT_DTPREL16 91 /* half16* (sym+add)@got@dtprel */ -+#define R_PPC_GOT_DTPREL16_LO 92 /* half16* (sym+add)@got@dtprel@l */ -+#define R_PPC_GOT_DTPREL16_HI 93 /* half16* (sym+add)@got@dtprel@h */ -+#define R_PPC_GOT_DTPREL16_HA 94 /* half16* (sym+add)@got@dtprel@ha */ -+ -+/* Keep this the last entry. */ -+#define R_PPC_NUM 95 -+ -+/* The remaining relocs are from the Embedded ELF ABI, and are not -+ in the SVR4 ELF ABI. */ -+#define R_PPC_EMB_NADDR32 101 -+#define R_PPC_EMB_NADDR16 102 -+#define R_PPC_EMB_NADDR16_LO 103 -+#define R_PPC_EMB_NADDR16_HI 104 -+#define R_PPC_EMB_NADDR16_HA 105 -+#define R_PPC_EMB_SDAI16 106 -+#define R_PPC_EMB_SDA2I16 107 -+#define R_PPC_EMB_SDA2REL 108 -+#define R_PPC_EMB_SDA21 109 /* 16 bit offset in SDA */ -+#define R_PPC_EMB_MRKREF 110 -+#define R_PPC_EMB_RELSEC16 111 -+#define R_PPC_EMB_RELST_LO 112 -+#define R_PPC_EMB_RELST_HI 113 -+#define R_PPC_EMB_RELST_HA 114 -+#define R_PPC_EMB_BIT_FLD 115 -+#define R_PPC_EMB_RELSDA 116 /* 16 bit relative offset in SDA */ -+ -+/* Diab tool relocations. */ -+#define R_PPC_DIAB_SDA21_LO 180 /* like EMB_SDA21, but lower 16 bit */ -+#define R_PPC_DIAB_SDA21_HI 181 /* like EMB_SDA21, but high 16 bit */ -+#define R_PPC_DIAB_SDA21_HA 182 /* like EMB_SDA21, adjusted high 16 */ -+#define R_PPC_DIAB_RELSDA_LO 183 /* like EMB_RELSDA, but lower 16 bit */ -+#define R_PPC_DIAB_RELSDA_HI 184 /* like EMB_RELSDA, but high 16 bit */ -+#define R_PPC_DIAB_RELSDA_HA 185 /* like EMB_RELSDA, adjusted high 16 */ -+ -+/* This is a phony reloc to handle any old fashioned TOC16 references -+ that may still be in object files. */ -+#define R_PPC_TOC16 255 -+ -+ -+/* PowerPC64 relocations defined by the ABIs */ -+#define R_PPC64_NONE R_PPC_NONE -+#define R_PPC64_ADDR32 R_PPC_ADDR32 /* 32bit absolute address */ -+#define R_PPC64_ADDR24 R_PPC_ADDR24 /* 26bit address, word aligned */ -+#define R_PPC64_ADDR16 R_PPC_ADDR16 /* 16bit absolute address */ -+#define R_PPC64_ADDR16_LO R_PPC_ADDR16_LO /* lower 16bits of address */ -+#define R_PPC64_ADDR16_HI R_PPC_ADDR16_HI /* high 16bits of address. */ -+#define R_PPC64_ADDR16_HA R_PPC_ADDR16_HA /* adjusted high 16bits. */ -+#define R_PPC64_ADDR14 R_PPC_ADDR14 /* 16bit address, word aligned */ -+#define R_PPC64_ADDR14_BRTAKEN R_PPC_ADDR14_BRTAKEN -+#define R_PPC64_ADDR14_BRNTAKEN R_PPC_ADDR14_BRNTAKEN -+#define R_PPC64_REL24 R_PPC_REL24 /* PC-rel. 26 bit, word aligned */ -+#define R_PPC64_REL14 R_PPC_REL14 /* PC relative 16 bit */ -+#define R_PPC64_REL14_BRTAKEN R_PPC_REL14_BRTAKEN -+#define R_PPC64_REL14_BRNTAKEN R_PPC_REL14_BRNTAKEN -+#define R_PPC64_GOT16 R_PPC_GOT16 -+#define R_PPC64_GOT16_LO R_PPC_GOT16_LO -+#define R_PPC64_GOT16_HI R_PPC_GOT16_HI -+#define R_PPC64_GOT16_HA R_PPC_GOT16_HA -+ -+#define R_PPC64_COPY R_PPC_COPY -+#define R_PPC64_GLOB_DAT R_PPC_GLOB_DAT -+#define R_PPC64_JMP_SLOT R_PPC_JMP_SLOT -+#define R_PPC64_RELATIVE R_PPC_RELATIVE -+ -+#define R_PPC64_UADDR32 R_PPC_UADDR32 -+#define R_PPC64_UADDR16 R_PPC_UADDR16 -+#define R_PPC64_REL32 R_PPC_REL32 -+#define R_PPC64_PLT32 R_PPC_PLT32 -+#define R_PPC64_PLTREL32 R_PPC_PLTREL32 -+#define R_PPC64_PLT16_LO R_PPC_PLT16_LO -+#define R_PPC64_PLT16_HI R_PPC_PLT16_HI -+#define R_PPC64_PLT16_HA R_PPC_PLT16_HA -+ -+#define R_PPC64_SECTOFF R_PPC_SECTOFF -+#define R_PPC64_SECTOFF_LO R_PPC_SECTOFF_LO -+#define R_PPC64_SECTOFF_HI R_PPC_SECTOFF_HI -+#define R_PPC64_SECTOFF_HA R_PPC_SECTOFF_HA -+#define R_PPC64_ADDR30 37 /* word30 (S + A - P) >> 2 */ -+#define R_PPC64_ADDR64 38 /* doubleword64 S + A */ -+#define R_PPC64_ADDR16_HIGHER 39 /* half16 #higher(S + A) */ -+#define R_PPC64_ADDR16_HIGHERA 40 /* half16 #highera(S + A) */ -+#define R_PPC64_ADDR16_HIGHEST 41 /* half16 #highest(S + A) */ -+#define R_PPC64_ADDR16_HIGHESTA 42 /* half16 #highesta(S + A) */ -+#define R_PPC64_UADDR64 43 /* doubleword64 S + A */ -+#define R_PPC64_REL64 44 /* doubleword64 S + A - P */ -+#define R_PPC64_PLT64 45 /* doubleword64 L + A */ -+#define R_PPC64_PLTREL64 46 /* doubleword64 L + A - P */ -+#define R_PPC64_TOC16 47 /* half16* S + A - .TOC */ -+#define R_PPC64_TOC16_LO 48 /* half16 #lo(S + A - .TOC.) */ -+#define R_PPC64_TOC16_HI 49 /* half16 #hi(S + A - .TOC.) */ -+#define R_PPC64_TOC16_HA 50 /* half16 #ha(S + A - .TOC.) */ -+#define R_PPC64_TOC 51 /* doubleword64 .TOC */ -+#define R_PPC64_PLTGOT16 52 /* half16* M + A */ -+#define R_PPC64_PLTGOT16_LO 53 /* half16 #lo(M + A) */ -+#define R_PPC64_PLTGOT16_HI 54 /* half16 #hi(M + A) */ -+#define R_PPC64_PLTGOT16_HA 55 /* half16 #ha(M + A) */ -+ -+#define R_PPC64_ADDR16_DS 56 /* half16ds* (S + A) >> 2 */ -+#define R_PPC64_ADDR16_LO_DS 57 /* half16ds #lo(S + A) >> 2 */ -+#define R_PPC64_GOT16_DS 58 /* half16ds* (G + A) >> 2 */ -+#define R_PPC64_GOT16_LO_DS 59 /* half16ds #lo(G + A) >> 2 */ -+#define R_PPC64_PLT16_LO_DS 60 /* half16ds #lo(L + A) >> 2 */ -+#define R_PPC64_SECTOFF_DS 61 /* half16ds* (R + A) >> 2 */ -+#define R_PPC64_SECTOFF_LO_DS 62 /* half16ds #lo(R + A) >> 2 */ -+#define R_PPC64_TOC16_DS 63 /* half16ds* (S + A - .TOC.) >> 2 */ -+#define R_PPC64_TOC16_LO_DS 64 /* half16ds #lo(S + A - .TOC.) >> 2 */ -+#define R_PPC64_PLTGOT16_DS 65 /* half16ds* (M + A) >> 2 */ -+#define R_PPC64_PLTGOT16_LO_DS 66 /* half16ds #lo(M + A) >> 2 */ -+ -+/* PowerPC64 relocations defined for the TLS access ABI. */ -+#define R_PPC64_TLS 67 /* none (sym+add)@tls */ -+#define R_PPC64_DTPMOD64 68 /* doubleword64 (sym+add)@dtpmod */ -+#define R_PPC64_TPREL16 69 /* half16* (sym+add)@tprel */ -+#define R_PPC64_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */ -+#define R_PPC64_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */ -+#define R_PPC64_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */ -+#define R_PPC64_TPREL64 73 /* doubleword64 (sym+add)@tprel */ -+#define R_PPC64_DTPREL16 74 /* half16* (sym+add)@dtprel */ -+#define R_PPC64_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */ -+#define R_PPC64_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */ -+#define R_PPC64_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */ -+#define R_PPC64_DTPREL64 78 /* doubleword64 (sym+add)@dtprel */ -+#define R_PPC64_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */ -+#define R_PPC64_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */ -+#define R_PPC64_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */ -+#define R_PPC64_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */ -+#define R_PPC64_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */ -+#define R_PPC64_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */ -+#define R_PPC64_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */ -+#define R_PPC64_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */ -+#define R_PPC64_GOT_TPREL16_DS 87 /* half16ds* (sym+add)@got@tprel */ -+#define R_PPC64_GOT_TPREL16_LO_DS 88 /* half16ds (sym+add)@got@tprel@l */ -+#define R_PPC64_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */ -+#define R_PPC64_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */ -+#define R_PPC64_GOT_DTPREL16_DS 91 /* half16ds* (sym+add)@got@dtprel */ -+#define R_PPC64_GOT_DTPREL16_LO_DS 92 /* half16ds (sym+add)@got@dtprel@l */ -+#define R_PPC64_GOT_DTPREL16_HI 93 /* half16 (sym+add)@got@dtprel@h */ -+#define R_PPC64_GOT_DTPREL16_HA 94 /* half16 (sym+add)@got@dtprel@ha */ -+#define R_PPC64_TPREL16_DS 95 /* half16ds* (sym+add)@tprel */ -+#define R_PPC64_TPREL16_LO_DS 96 /* half16ds (sym+add)@tprel@l */ -+#define R_PPC64_TPREL16_HIGHER 97 /* half16 (sym+add)@tprel@higher */ -+#define R_PPC64_TPREL16_HIGHERA 98 /* half16 (sym+add)@tprel@highera */ -+#define R_PPC64_TPREL16_HIGHEST 99 /* half16 (sym+add)@tprel@highest */ -+#define R_PPC64_TPREL16_HIGHESTA 100 /* half16 (sym+add)@tprel@highesta */ -+#define R_PPC64_DTPREL16_DS 101 /* half16ds* (sym+add)@dtprel */ -+#define R_PPC64_DTPREL16_LO_DS 102 /* half16ds (sym+add)@dtprel@l */ -+#define R_PPC64_DTPREL16_HIGHER 103 /* half16 (sym+add)@dtprel@higher */ -+#define R_PPC64_DTPREL16_HIGHERA 104 /* half16 (sym+add)@dtprel@highera */ -+#define R_PPC64_DTPREL16_HIGHEST 105 /* half16 (sym+add)@dtprel@highest */ -+#define R_PPC64_DTPREL16_HIGHESTA 106 /* half16 (sym+add)@dtprel@highesta */ -+ -+/* Keep this the last entry. */ -+#define R_PPC64_NUM 107 -+ -+/* PowerPC64 specific values for the Dyn d_tag field. */ -+#define DT_PPC64_GLINK (DT_LOPROC + 0) -+#define DT_PPC64_NUM 1 -+ -+ -+/* ARM specific declarations */ -+ -+/* Processor specific flags for the ELF header e_flags field. */ -+#define EF_ARM_RELEXEC 0x01 -+#define EF_ARM_HASENTRY 0x02 -+#define EF_ARM_INTERWORK 0x04 -+#define EF_ARM_APCS_26 0x08 -+#define EF_ARM_APCS_FLOAT 0x10 -+#define EF_ARM_PIC 0x20 -+#define EF_ARM_ALIGN8 0x40 /* 8-bit structure alignment is in use */ -+#define EF_ARM_NEW_ABI 0x80 -+#define EF_ARM_OLD_ABI 0x100 -+ -+/* Other constants defined in the ARM ELF spec. version B-01. */ -+/* NB. These conflict with values defined above. */ -+#define EF_ARM_SYMSARESORTED 0x04 -+#define EF_ARM_DYNSYMSUSESEGIDX 0x08 -+#define EF_ARM_MAPSYMSFIRST 0x10 -+#define EF_ARM_EABIMASK 0XFF000000 -+ -+#define EF_ARM_EABI_VERSION(flags) ((flags) & EF_ARM_EABIMASK) -+#define EF_ARM_EABI_UNKNOWN 0x00000000 -+#define EF_ARM_EABI_VER1 0x01000000 -+#define EF_ARM_EABI_VER2 0x02000000 -+ -+/* Additional symbol types for Thumb */ -+#define STT_ARM_TFUNC 0xd -+ -+/* ARM-specific values for sh_flags */ -+#define SHF_ARM_ENTRYSECT 0x10000000 /* Section contains an entry point */ -+#define SHF_ARM_COMDEF 0x80000000 /* Section may be multiply defined -+ in the input to a link step */ -+ -+/* ARM-specific program header flags */ -+#define PF_ARM_SB 0x10000000 /* Segment contains the location -+ addressed by the static base */ -+ -+/* ARM relocs. */ -+#define R_ARM_NONE 0 /* No reloc */ -+#define R_ARM_PC24 1 /* PC relative 26 bit branch */ -+#define R_ARM_ABS32 2 /* Direct 32 bit */ -+#define R_ARM_REL32 3 /* PC relative 32 bit */ -+#define R_ARM_PC13 4 -+#define R_ARM_ABS16 5 /* Direct 16 bit */ -+#define R_ARM_ABS12 6 /* Direct 12 bit */ -+#define R_ARM_THM_ABS5 7 -+#define R_ARM_ABS8 8 /* Direct 8 bit */ -+#define R_ARM_SBREL32 9 -+#define R_ARM_THM_PC22 10 -+#define R_ARM_THM_PC8 11 -+#define R_ARM_AMP_VCALL9 12 -+#define R_ARM_SWI24 13 -+#define R_ARM_THM_SWI8 14 -+#define R_ARM_XPC25 15 -+#define R_ARM_THM_XPC22 16 -+#define R_ARM_COPY 20 /* Copy symbol at runtime */ -+#define R_ARM_GLOB_DAT 21 /* Create GOT entry */ -+#define R_ARM_JUMP_SLOT 22 /* Create PLT entry */ -+#define R_ARM_RELATIVE 23 /* Adjust by program base */ -+#define R_ARM_GOTOFF 24 /* 32 bit offset to GOT */ -+#define R_ARM_GOTPC 25 /* 32 bit PC relative offset to GOT */ -+#define R_ARM_GOT32 26 /* 32 bit GOT entry */ -+#define R_ARM_PLT32 27 /* 32 bit PLT address */ -+#define R_ARM_ALU_PCREL_7_0 32 -+#define R_ARM_ALU_PCREL_15_8 33 -+#define R_ARM_ALU_PCREL_23_15 34 -+#define R_ARM_LDR_SBREL_11_0 35 -+#define R_ARM_ALU_SBREL_19_12 36 -+#define R_ARM_ALU_SBREL_27_20 37 -+#define R_ARM_GNU_VTENTRY 100 -+#define R_ARM_GNU_VTINHERIT 101 -+#define R_ARM_THM_PC11 102 /* thumb unconditional branch */ -+#define R_ARM_THM_PC9 103 /* thumb conditional branch */ -+#define R_ARM_RXPC25 249 -+#define R_ARM_RSBREL32 250 -+#define R_ARM_THM_RPC22 251 -+#define R_ARM_RREL32 252 -+#define R_ARM_RABS22 253 -+#define R_ARM_RPC24 254 -+#define R_ARM_RBASE 255 -+/* Keep this the last entry. */ -+#define R_ARM_NUM 256 -+ -+/* IA-64 specific declarations. */ -+ -+/* Processor specific flags for the Ehdr e_flags field. */ -+#define EF_IA_64_MASKOS 0x0000000f /* os-specific flags */ -+#define EF_IA_64_ABI64 0x00000010 /* 64-bit ABI */ -+#define EF_IA_64_ARCH 0xff000000 /* arch. version mask */ -+ -+/* Processor specific values for the Phdr p_type field. */ -+#define PT_IA_64_ARCHEXT (PT_LOPROC + 0) /* arch extension bits */ -+#define PT_IA_64_UNWIND (PT_LOPROC + 1) /* ia64 unwind bits */ -+ -+/* Processor specific flags for the Phdr p_flags field. */ -+#define PF_IA_64_NORECOV 0x80000000 /* spec insns w/o recovery */ -+ -+/* Processor specific values for the Shdr sh_type field. */ -+#define SHT_IA_64_EXT (SHT_LOPROC + 0) /* extension bits */ -+#define SHT_IA_64_UNWIND (SHT_LOPROC + 1) /* unwind bits */ -+ -+/* Processor specific flags for the Shdr sh_flags field. */ -+#define SHF_IA_64_SHORT 0x10000000 /* section near gp */ -+#define SHF_IA_64_NORECOV 0x20000000 /* spec insns w/o recovery */ -+ -+/* Processor specific values for the Dyn d_tag field. */ -+#define DT_IA_64_PLT_RESERVE (DT_LOPROC + 0) -+#define DT_IA_64_NUM 1 -+ -+/* IA-64 relocations. */ -+#define R_IA64_NONE 0x00 /* none */ -+#define R_IA64_IMM14 0x21 /* symbol + addend, add imm14 */ -+#define R_IA64_IMM22 0x22 /* symbol + addend, add imm22 */ -+#define R_IA64_IMM64 0x23 /* symbol + addend, mov imm64 */ -+#define R_IA64_DIR32MSB 0x24 /* symbol + addend, data4 MSB */ -+#define R_IA64_DIR32LSB 0x25 /* symbol + addend, data4 LSB */ -+#define R_IA64_DIR64MSB 0x26 /* symbol + addend, data8 MSB */ -+#define R_IA64_DIR64LSB 0x27 /* symbol + addend, data8 LSB */ -+#define R_IA64_GPREL22 0x2a /* @gprel(sym + add), add imm22 */ -+#define R_IA64_GPREL64I 0x2b /* @gprel(sym + add), mov imm64 */ -+#define R_IA64_GPREL32MSB 0x2c /* @gprel(sym + add), data4 MSB */ -+#define R_IA64_GPREL32LSB 0x2d /* @gprel(sym + add), data4 LSB */ -+#define R_IA64_GPREL64MSB 0x2e /* @gprel(sym + add), data8 MSB */ -+#define R_IA64_GPREL64LSB 0x2f /* @gprel(sym + add), data8 LSB */ -+#define R_IA64_LTOFF22 0x32 /* @ltoff(sym + add), add imm22 */ -+#define R_IA64_LTOFF64I 0x33 /* @ltoff(sym + add), mov imm64 */ -+#define R_IA64_PLTOFF22 0x3a /* @pltoff(sym + add), add imm22 */ -+#define R_IA64_PLTOFF64I 0x3b /* @pltoff(sym + add), mov imm64 */ -+#define R_IA64_PLTOFF64MSB 0x3e /* @pltoff(sym + add), data8 MSB */ -+#define R_IA64_PLTOFF64LSB 0x3f /* @pltoff(sym + add), data8 LSB */ -+#define R_IA64_FPTR64I 0x43 /* @fptr(sym + add), mov imm64 */ -+#define R_IA64_FPTR32MSB 0x44 /* @fptr(sym + add), data4 MSB */ -+#define R_IA64_FPTR32LSB 0x45 /* @fptr(sym + add), data4 LSB */ -+#define R_IA64_FPTR64MSB 0x46 /* @fptr(sym + add), data8 MSB */ -+#define R_IA64_FPTR64LSB 0x47 /* @fptr(sym + add), data8 LSB */ -+#define R_IA64_PCREL60B 0x48 /* @pcrel(sym + add), brl */ -+#define R_IA64_PCREL21B 0x49 /* @pcrel(sym + add), ptb, call */ -+#define R_IA64_PCREL21M 0x4a /* @pcrel(sym + add), chk.s */ -+#define R_IA64_PCREL21F 0x4b /* @pcrel(sym + add), fchkf */ -+#define R_IA64_PCREL32MSB 0x4c /* @pcrel(sym + add), data4 MSB */ -+#define R_IA64_PCREL32LSB 0x4d /* @pcrel(sym + add), data4 LSB */ -+#define R_IA64_PCREL64MSB 0x4e /* @pcrel(sym + add), data8 MSB */ -+#define R_IA64_PCREL64LSB 0x4f /* @pcrel(sym + add), data8 LSB */ -+#define R_IA64_LTOFF_FPTR22 0x52 /* @ltoff(@fptr(s+a)), imm22 */ -+#define R_IA64_LTOFF_FPTR64I 0x53 /* @ltoff(@fptr(s+a)), imm64 */ -+#define R_IA64_LTOFF_FPTR32MSB 0x54 /* @ltoff(@fptr(s+a)), data4 MSB */ -+#define R_IA64_LTOFF_FPTR32LSB 0x55 /* @ltoff(@fptr(s+a)), data4 LSB */ -+#define R_IA64_LTOFF_FPTR64MSB 0x56 /* @ltoff(@fptr(s+a)), data8 MSB */ -+#define R_IA64_LTOFF_FPTR64LSB 0x57 /* @ltoff(@fptr(s+a)), data8 LSB */ -+#define R_IA64_SEGREL32MSB 0x5c /* @segrel(sym + add), data4 MSB */ -+#define R_IA64_SEGREL32LSB 0x5d /* @segrel(sym + add), data4 LSB */ -+#define R_IA64_SEGREL64MSB 0x5e /* @segrel(sym + add), data8 MSB */ -+#define R_IA64_SEGREL64LSB 0x5f /* @segrel(sym + add), data8 LSB */ -+#define R_IA64_SECREL32MSB 0x64 /* @secrel(sym + add), data4 MSB */ -+#define R_IA64_SECREL32LSB 0x65 /* @secrel(sym + add), data4 LSB */ -+#define R_IA64_SECREL64MSB 0x66 /* @secrel(sym + add), data8 MSB */ -+#define R_IA64_SECREL64LSB 0x67 /* @secrel(sym + add), data8 LSB */ -+#define R_IA64_REL32MSB 0x6c /* data 4 + REL */ -+#define R_IA64_REL32LSB 0x6d /* data 4 + REL */ -+#define R_IA64_REL64MSB 0x6e /* data 8 + REL */ -+#define R_IA64_REL64LSB 0x6f /* data 8 + REL */ -+#define R_IA64_LTV32MSB 0x74 /* symbol + addend, data4 MSB */ -+#define R_IA64_LTV32LSB 0x75 /* symbol + addend, data4 LSB */ -+#define R_IA64_LTV64MSB 0x76 /* symbol + addend, data8 MSB */ -+#define R_IA64_LTV64LSB 0x77 /* symbol + addend, data8 LSB */ -+#define R_IA64_PCREL21BI 0x79 /* @pcrel(sym + add), 21bit inst */ -+#define R_IA64_PCREL22 0x7a /* @pcrel(sym + add), 22bit inst */ -+#define R_IA64_PCREL64I 0x7b /* @pcrel(sym + add), 64bit inst */ -+#define R_IA64_IPLTMSB 0x80 /* dynamic reloc, imported PLT, MSB */ -+#define R_IA64_IPLTLSB 0x81 /* dynamic reloc, imported PLT, LSB */ -+#define R_IA64_COPY 0x84 /* copy relocation */ -+#define R_IA64_SUB 0x85 /* Addend and symbol difference */ -+#define R_IA64_LTOFF22X 0x86 /* LTOFF22, relaxable. */ -+#define R_IA64_LDXMOV 0x87 /* Use of LTOFF22X. */ -+#define R_IA64_TPREL14 0x91 /* @tprel(sym + add), imm14 */ -+#define R_IA64_TPREL22 0x92 /* @tprel(sym + add), imm22 */ -+#define R_IA64_TPREL64I 0x93 /* @tprel(sym + add), imm64 */ -+#define R_IA64_TPREL64MSB 0x96 /* @tprel(sym + add), data8 MSB */ -+#define R_IA64_TPREL64LSB 0x97 /* @tprel(sym + add), data8 LSB */ -+#define R_IA64_LTOFF_TPREL22 0x9a /* @ltoff(@tprel(s+a)), imm2 */ -+#define R_IA64_DTPMOD64MSB 0xa6 /* @dtpmod(sym + add), data8 MSB */ -+#define R_IA64_DTPMOD64LSB 0xa7 /* @dtpmod(sym + add), data8 LSB */ -+#define R_IA64_LTOFF_DTPMOD22 0xaa /* @ltoff(@dtpmod(sym + add)), imm22 */ -+#define R_IA64_DTPREL14 0xb1 /* @dtprel(sym + add), imm14 */ -+#define R_IA64_DTPREL22 0xb2 /* @dtprel(sym + add), imm22 */ -+#define R_IA64_DTPREL64I 0xb3 /* @dtprel(sym + add), imm64 */ -+#define R_IA64_DTPREL32MSB 0xb4 /* @dtprel(sym + add), data4 MSB */ -+#define R_IA64_DTPREL32LSB 0xb5 /* @dtprel(sym + add), data4 LSB */ -+#define R_IA64_DTPREL64MSB 0xb6 /* @dtprel(sym + add), data8 MSB */ -+#define R_IA64_DTPREL64LSB 0xb7 /* @dtprel(sym + add), data8 LSB */ -+#define R_IA64_LTOFF_DTPREL22 0xba /* @ltoff(@dtprel(s+a)), imm22 */ -+ -+/* SH specific declarations */ -+ -+/* SH relocs. */ -+#define R_SH_NONE 0 -+#define R_SH_DIR32 1 -+#define R_SH_REL32 2 -+#define R_SH_DIR8WPN 3 -+#define R_SH_IND12W 4 -+#define R_SH_DIR8WPL 5 -+#define R_SH_DIR8WPZ 6 -+#define R_SH_DIR8BP 7 -+#define R_SH_DIR8W 8 -+#define R_SH_DIR8L 9 -+#define R_SH_SWITCH16 25 -+#define R_SH_SWITCH32 26 -+#define R_SH_USES 27 -+#define R_SH_COUNT 28 -+#define R_SH_ALIGN 29 -+#define R_SH_CODE 30 -+#define R_SH_DATA 31 -+#define R_SH_LABEL 32 -+#define R_SH_SWITCH8 33 -+#define R_SH_GNU_VTINHERIT 34 -+#define R_SH_GNU_VTENTRY 35 -+#define R_SH_TLS_GD_32 144 -+#define R_SH_TLS_LD_32 145 -+#define R_SH_TLS_LDO_32 146 -+#define R_SH_TLS_IE_32 147 -+#define R_SH_TLS_LE_32 148 -+#define R_SH_TLS_DTPMOD32 149 -+#define R_SH_TLS_DTPOFF32 150 -+#define R_SH_TLS_TPOFF32 151 -+#define R_SH_GOT32 160 -+#define R_SH_PLT32 161 -+#define R_SH_COPY 162 -+#define R_SH_GLOB_DAT 163 -+#define R_SH_JMP_SLOT 164 -+#define R_SH_RELATIVE 165 -+#define R_SH_GOTOFF 166 -+#define R_SH_GOTPC 167 -+/* Keep this the last entry. */ -+#define R_SH_NUM 256 -+ -+/* Additional s390 relocs */ -+ -+#define R_390_NONE 0 /* No reloc. */ -+#define R_390_8 1 /* Direct 8 bit. */ -+#define R_390_12 2 /* Direct 12 bit. */ -+#define R_390_16 3 /* Direct 16 bit. */ -+#define R_390_32 4 /* Direct 32 bit. */ -+#define R_390_PC32 5 /* PC relative 32 bit. */ -+#define R_390_GOT12 6 /* 12 bit GOT offset. */ -+#define R_390_GOT32 7 /* 32 bit GOT offset. */ -+#define R_390_PLT32 8 /* 32 bit PC relative PLT address. */ -+#define R_390_COPY 9 /* Copy symbol at runtime. */ -+#define R_390_GLOB_DAT 10 /* Create GOT entry. */ -+#define R_390_JMP_SLOT 11 /* Create PLT entry. */ -+#define R_390_RELATIVE 12 /* Adjust by program base. */ -+#define R_390_GOTOFF32 13 /* 32 bit offset to GOT. */ -+#define R_390_GOTPC 14 /* 32 bit PC relative offset to GOT. */ -+#define R_390_GOT16 15 /* 16 bit GOT offset. */ -+#define R_390_PC16 16 /* PC relative 16 bit. */ -+#define R_390_PC16DBL 17 /* PC relative 16 bit shifted by 1. */ -+#define R_390_PLT16DBL 18 /* 16 bit PC rel. PLT shifted by 1. */ -+#define R_390_PC32DBL 19 /* PC relative 32 bit shifted by 1. */ -+#define R_390_PLT32DBL 20 /* 32 bit PC rel. PLT shifted by 1. */ -+#define R_390_GOTPCDBL 21 /* 32 bit PC rel. GOT shifted by 1. */ -+#define R_390_64 22 /* Direct 64 bit. */ -+#define R_390_PC64 23 /* PC relative 64 bit. */ -+#define R_390_GOT64 24 /* 64 bit GOT offset. */ -+#define R_390_PLT64 25 /* 64 bit PC relative PLT address. */ -+#define R_390_GOTENT 26 /* 32 bit PC rel. to GOT entry >> 1. */ -+#define R_390_GOTOFF16 27 /* 16 bit offset to GOT. */ -+#define R_390_GOTOFF64 28 /* 64 bit offset to GOT. */ -+#define R_390_GOTPLT12 29 /* 12 bit offset to jump slot. */ -+#define R_390_GOTPLT16 30 /* 16 bit offset to jump slot. */ -+#define R_390_GOTPLT32 31 /* 32 bit offset to jump slot. */ -+#define R_390_GOTPLT64 32 /* 64 bit offset to jump slot. */ -+#define R_390_GOTPLTENT 33 /* 32 bit rel. offset to jump slot. */ -+#define R_390_PLTOFF16 34 /* 16 bit offset from GOT to PLT. */ -+#define R_390_PLTOFF32 35 /* 32 bit offset from GOT to PLT. */ -+#define R_390_PLTOFF64 36 /* 16 bit offset from GOT to PLT. */ -+#define R_390_TLS_LOAD 37 /* Tag for load insn in TLS code. */ -+#define R_390_TLS_GDCALL 38 /* Tag for function call in general -+ dynamic TLS code. */ -+#define R_390_TLS_LDCALL 39 /* Tag for function call in local -+ dynamic TLS code. */ -+#define R_390_TLS_GD32 40 /* Direct 32 bit for general dynamic -+ thread local data. */ -+#define R_390_TLS_GD64 41 /* Direct 64 bit for general dynamic -+ thread local data. */ -+#define R_390_TLS_GOTIE12 42 /* 12 bit GOT offset for static TLS -+ block offset. */ -+#define R_390_TLS_GOTIE32 43 /* 32 bit GOT offset for static TLS -+ block offset. */ -+#define R_390_TLS_GOTIE64 44 /* 64 bit GOT offset for static TLS -+ block offset. */ -+#define R_390_TLS_LDM32 45 /* Direct 32 bit for local dynamic -+ thread local data in LE code. */ -+#define R_390_TLS_LDM64 46 /* Direct 64 bit for local dynamic -+ thread local data in LE code. */ -+#define R_390_TLS_IE32 47 /* 32 bit address of GOT entry for -+ negated static TLS block offset. */ -+#define R_390_TLS_IE64 48 /* 64 bit address of GOT entry for -+ negated static TLS block offset. */ -+#define R_390_TLS_IEENT 49 /* 32 bit rel. offset to GOT entry for -+ negated static TLS block offset. */ -+#define R_390_TLS_LE32 50 /* 32 bit negated offset relative to -+ static TLS block. */ -+#define R_390_TLS_LE64 51 /* 64 bit negated offset relative to -+ static TLS block. */ -+#define R_390_TLS_LDO32 52 /* 32 bit offset relative to TLS -+ block. */ -+#define R_390_TLS_LDO64 53 /* 64 bit offset relative to TLS -+ block. */ -+#define R_390_TLS_DTPMOD 54 /* ID of module containing symbol. */ -+#define R_390_TLS_DTPOFF 55 /* Offset in TLS block. */ -+#define R_390_TLS_TPOFF 56 /* Negated offset in static TLS -+ block. */ -+ -+/* Keep this the last entry. */ -+#define R_390_NUM 57 -+ -+/* CRIS relocations. */ -+#define R_CRIS_NONE 0 -+#define R_CRIS_8 1 -+#define R_CRIS_16 2 -+#define R_CRIS_32 3 -+#define R_CRIS_8_PCREL 4 -+#define R_CRIS_16_PCREL 5 -+#define R_CRIS_32_PCREL 6 -+#define R_CRIS_GNU_VTINHERIT 7 -+#define R_CRIS_GNU_VTENTRY 8 -+#define R_CRIS_COPY 9 -+#define R_CRIS_GLOB_DAT 10 -+#define R_CRIS_JUMP_SLOT 11 -+#define R_CRIS_RELATIVE 12 -+#define R_CRIS_16_GOT 13 -+#define R_CRIS_32_GOT 14 -+#define R_CRIS_16_GOTPLT 15 -+#define R_CRIS_32_GOTPLT 16 -+#define R_CRIS_32_GOTREL 17 -+#define R_CRIS_32_PLT_GOTREL 18 -+#define R_CRIS_32_PLT_PCREL 19 -+ -+#define R_CRIS_NUM 20 -+ -+/* AMD x86-64 relocations. */ -+#define R_X86_64_NONE 0 /* No reloc */ -+#define R_X86_64_64 1 /* Direct 64 bit */ -+#define R_X86_64_PC32 2 /* PC relative 32 bit signed */ -+#define R_X86_64_GOT32 3 /* 32 bit GOT entry */ -+#define R_X86_64_PLT32 4 /* 32 bit PLT address */ -+#define R_X86_64_COPY 5 /* Copy symbol at runtime */ -+#define R_X86_64_GLOB_DAT 6 /* Create GOT entry */ -+#define R_X86_64_JUMP_SLOT 7 /* Create PLT entry */ -+#define R_X86_64_RELATIVE 8 /* Adjust by program base */ -+#define R_X86_64_GOTPCREL 9 /* 32 bit signed PC relative -+ offset to GOT */ -+#define R_X86_64_32 10 /* Direct 32 bit zero extended */ -+#define R_X86_64_32S 11 /* Direct 32 bit sign extended */ -+#define R_X86_64_16 12 /* Direct 16 bit zero extended */ -+#define R_X86_64_PC16 13 /* 16 bit sign extended pc relative */ -+#define R_X86_64_8 14 /* Direct 8 bit sign extended */ -+#define R_X86_64_PC8 15 /* 8 bit sign extended pc relative */ -+#define R_X86_64_DTPMOD64 16 /* ID of module containing symbol */ -+#define R_X86_64_DTPOFF64 17 /* Offset in module's TLS block */ -+#define R_X86_64_TPOFF64 18 /* Offset in initial TLS block */ -+#define R_X86_64_TLSGD 19 /* 32 bit signed PC relative offset -+ to two GOT entries for GD symbol */ -+#define R_X86_64_TLSLD 20 /* 32 bit signed PC relative offset -+ to two GOT entries for LD symbol */ -+#define R_X86_64_DTPOFF32 21 /* Offset in TLS block */ -+#define R_X86_64_GOTTPOFF 22 /* 32 bit signed PC relative offset -+ to GOT entry for IE symbol */ -+#define R_X86_64_TPOFF32 23 /* Offset in initial TLS block */ -+ -+#define R_X86_64_NUM 24 -+ -+__END_DECLS -+ -+#endif /* elf.h */ - - #include "elfconfig.h" - -@@ -195,3 +2641,4 @@ - void fatal(const char *fmt, ...); - void warn(const char *fmt, ...); - void merror(const char *fmt, ...); -+ -diff -Nur linux-2.6.36.orig/scripts/mod/sumversion.c linux-2.6.36/scripts/mod/sumversion.c ---- linux-2.6.36.orig/scripts/mod/sumversion.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/scripts/mod/sumversion.c 2010-11-28 18:33:24.000000000 +0100 -@@ -1,4 +1,4 @@ --#include -+/* #include */ - #ifdef __sun__ - #include - #else diff --git a/target/linux/patches/3.0.8/cris-etrax.patch b/target/linux/patches/3.0.8/cris-etrax.patch deleted file mode 100644 index a80d9a8b8..000000000 --- a/target/linux/patches/3.0.8/cris-etrax.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff -Nur linux-2.6.39.orig/arch/cris/arch-v32/drivers/i2c.h linux-2.6.39/arch/cris/arch-v32/drivers/i2c.h ---- linux-2.6.39.orig/arch/cris/arch-v32/drivers/i2c.h 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/arch/cris/arch-v32/drivers/i2c.h 2011-08-24 19:15:05.000000000 +0200 -@@ -2,7 +2,7 @@ - #include - - /* High level I2C actions */ --int __init i2c_init(void); -+static int __init i2c_init(void); - int i2c_write(unsigned char theSlave, void *data, size_t nbytes); - int i2c_read(unsigned char theSlave, void *data, size_t nbytes); - int i2c_writereg(unsigned char theSlave, unsigned char theReg, unsigned char theValue); diff --git a/target/linux/patches/3.0.8/defaults.patch b/target/linux/patches/3.0.8/defaults.patch deleted file mode 100644 index 58aae610b..000000000 --- a/target/linux/patches/3.0.8/defaults.patch +++ /dev/null @@ -1,22 +0,0 @@ -diff -Nur linux-3.0.4.orig/fs/Kconfig linux-3.0.4/fs/Kconfig ---- linux-3.0.4.orig/fs/Kconfig 2011-08-29 22:56:30.000000000 +0200 -+++ linux-3.0.4/fs/Kconfig 2011-10-15 22:08:44.000000000 +0200 -@@ -47,7 +47,7 @@ - def_bool n - - config EXPORTFS -- tristate -+ def_bool y - - config FILE_LOCKING - bool "Enable POSIX file locking API" if EXPERT -diff -Nur linux-3.0.4.orig/fs/notify/Kconfig linux-3.0.4/fs/notify/Kconfig ---- linux-3.0.4.orig/fs/notify/Kconfig 2011-08-29 22:56:30.000000000 +0200 -+++ linux-3.0.4/fs/notify/Kconfig 2011-10-15 22:02:00.000000000 +0200 -@@ -1,5 +1,5 @@ - config FSNOTIFY -- def_bool n -+ def_bool y - - source "fs/notify/dnotify/Kconfig" - source "fs/notify/inotify/Kconfig" diff --git a/target/linux/patches/3.0.8/fon2100.patch b/target/linux/patches/3.0.8/fon2100.patch deleted file mode 100644 index 038ff7020..000000000 --- a/target/linux/patches/3.0.8/fon2100.patch +++ /dev/null @@ -1,6279 +0,0 @@ -diff -Nur linux-2.6.39-rc7.orig/arch/mips/Kbuild.platforms linux-2.6.39-rc7/arch/mips/Kbuild.platforms ---- linux-2.6.39-rc7.orig/arch/mips/Kbuild.platforms 2011-05-10 04:33:54.000000000 +0200 -+++ linux-2.6.39-rc7/arch/mips/Kbuild.platforms 2011-05-15 21:34:57.000000000 +0200 -@@ -6,6 +6,7 @@ - platforms += bcm47xx - platforms += bcm63xx - platforms += cavium-octeon -+platforms += ar231x - platforms += cobalt - platforms += dec - platforms += emma -diff -Nur linux-2.6.39-rc7.orig/arch/mips/Kconfig linux-2.6.39-rc7/arch/mips/Kconfig ---- linux-2.6.39-rc7.orig/arch/mips/Kconfig 2011-05-10 04:33:54.000000000 +0200 -+++ linux-2.6.39-rc7/arch/mips/Kconfig 2011-05-16 12:11:11.000000000 +0200 -@@ -121,6 +121,21 @@ - help - Support for BCM63XX based boards - -+config ATHEROS_AR231X -+ bool "Atheros 231x/531x SoC support" -+ select CEVT_R4K -+ select CSRC_R4K -+ select DMA_NONCOHERENT -+ select IRQ_CPU -+ select SYS_HAS_CPU_MIPS32_R1 -+ select SYS_SUPPORTS_BIG_ENDIAN -+ select SYS_SUPPORTS_32BIT_KERNEL -+ select GENERIC_GPIO -+ select SYS_HAS_EARLY_PRINTK -+ select SYS_SUPPORTS_ZBOOT -+ help -+ Support for AR231x and AR531x based boards -+ - config MIPS_COBALT - bool "Cobalt Server" - select CEVT_R4K -@@ -738,6 +753,7 @@ - - endchoice - -+source "arch/mips/ar231x/Kconfig" - source "arch/mips/alchemy/Kconfig" - source "arch/mips/ath79/Kconfig" - source "arch/mips/bcm63xx/Kconfig" -diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/Kconfig linux-2.6.39-rc7/arch/mips/ar231x/Kconfig ---- linux-2.6.39-rc7.orig/arch/mips/ar231x/Kconfig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/ar231x/Kconfig 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,27 @@ -+config ATHEROS_AR5312 -+ bool "Atheros 5312/2312+ support" -+ depends on ATHEROS_AR231X -+ default y -+ -+config ATHEROS_AR2315 -+ bool "Atheros 2315+ support" -+ depends on ATHEROS_AR231X -+ select DMA_NONCOHERENT -+ select CEVT_R4K -+ select CSRC_R4K -+ select IRQ_CPU -+ select SYS_HAS_CPU_MIPS32_R1 -+ select SYS_SUPPORTS_32BIT_KERNEL -+ select SYS_SUPPORTS_BIG_ENDIAN -+ select GENERIC_GPIO -+ default y -+ -+config ATHEROS_AR2315_PCI -+ bool "PCI support" -+ depends on ATHEROS_AR2315 -+ select HW_HAS_PCI -+ select PCI -+ select USB_ARCH_HAS_HCD -+ select USB_ARCH_HAS_OHCI -+ select USB_ARCH_HAS_EHCI -+ default n -diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/Makefile linux-2.6.39-rc7/arch/mips/ar231x/Makefile ---- linux-2.6.39-rc7.orig/arch/mips/ar231x/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/ar231x/Makefile 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,17 @@ -+# -+# This file is subject to the terms and conditions of the GNU General Public -+# License. See the file "COPYING" in the main directory of this archive -+# for more details. -+# -+# Copyright (C) 2006 FON Technology, SL. -+# Copyright (C) 2006 Imre Kaloz -+# Copyright (C) 2006-2009 Felix Fietkau -+# -+ -+obj-y += board.o prom.o devices.o -+ -+obj-$(CONFIG_EARLY_PRINTK) += early_printk.o -+ -+obj-$(CONFIG_ATHEROS_AR5312) += ar5312.o -+obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o -+obj-$(CONFIG_ATHEROS_AR2315_PCI) += pci.o -diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/Platform linux-2.6.39-rc7/arch/mips/ar231x/Platform ---- linux-2.6.39-rc7.orig/arch/mips/ar231x/Platform 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/ar231x/Platform 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,6 @@ -+# -+# Atheros AR5312/AR2312 WiSoC -+# -+platform-$(CONFIG_ATHEROS_AR231X) += ar231x/ -+cflags-$(CONFIG_ATHEROS_AR231X) += -I$(srctree)/arch/mips/include/asm/mach-ar231x -+load-$(CONFIG_ATHEROS_AR231X) += 0xffffffff80041000 -diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/ar2315.c linux-2.6.39-rc7/arch/mips/ar231x/ar2315.c ---- linux-2.6.39-rc7.orig/arch/mips/ar231x/ar2315.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/ar231x/ar2315.c 2011-05-15 21:47:07.000000000 +0200 -@@ -0,0 +1,654 @@ -+/* -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. -+ * Copyright (C) 2006 FON Technology, SL. -+ * Copyright (C) 2006 Imre Kaloz -+ * Copyright (C) 2006 Felix Fietkau -+ */ -+ -+/* -+ * Platform devices for Atheros SoCs -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include "devices.h" -+#include "ar2315.h" -+ -+static u32 gpiointmask = 0, gpiointval = 0; -+ -+static inline void ar2315_gpio_irq(void) -+{ -+ u32 pend; -+ int bit = -1; -+ -+ /* only do one gpio interrupt at a time */ -+ pend = (ar231x_read_reg(AR2315_GPIO_DI) ^ gpiointval) & gpiointmask; -+ -+ if (pend) { -+ bit = fls(pend) - 1; -+ pend &= ~(1 << bit); -+ gpiointval ^= (1 << bit); -+ } -+ -+ if (!pend) -+ ar231x_write_reg(AR2315_ISR, AR2315_ISR_GPIO); -+ -+ /* Enable interrupt with edge detection */ -+ if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(bit)) != AR2315_GPIO_CR_I(bit)) -+ return; -+ -+ if (bit >= 0) -+ do_IRQ(AR531X_GPIO_IRQ_BASE + bit); -+} -+ -+#ifdef CONFIG_ATHEROS_AR2315_PCI -+static inline void pci_abort_irq(void) -+{ -+ ar231x_write_reg(AR2315_PCI_INT_STATUS, AR2315_PCI_ABORT_INT); -+} -+ -+static inline void pci_ack_irq(void) -+{ -+ ar231x_write_reg(AR2315_PCI_INT_STATUS, AR2315_PCI_EXT_INT); -+} -+ -+void ar2315_pci_irq(int irq) -+{ -+ if (ar231x_read_reg(AR2315_PCI_INT_STATUS) == AR2315_PCI_ABORT_INT) -+ pci_abort_irq(); -+ else { -+ do_IRQ(irq); -+ pci_ack_irq(); -+ } -+} -+#endif /* CONFIG_ATHEROS_AR2315_PCI */ -+ -+/* -+ * Called when an interrupt is received, this function -+ * determines exactly which interrupt it was, and it -+ * invokes the appropriate handler. -+ * -+ * Implicitly, we also define interrupt priority by -+ * choosing which to dispatch first. -+ */ -+static asmlinkage void -+ar2315_irq_dispatch(void) -+{ -+ int pending = read_c0_status() & read_c0_cause(); -+ -+ if (pending & CAUSEF_IP3) -+ do_IRQ(AR2315_IRQ_WLAN0_INTRS); -+ else if (pending & CAUSEF_IP4) -+ do_IRQ(AR2315_IRQ_ENET0_INTRS); -+#ifdef CONFIG_ATHEROS_AR2315_PCI -+ else if (pending & CAUSEF_IP5) -+ ar2315_pci_irq(AR2315_IRQ_LCBUS_PCI); -+#endif -+ else if (pending & CAUSEF_IP2) { -+ unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) & ar231x_read_reg(AR2315_IMR); -+ -+ if (misc_intr & AR2315_ISR_SPI) -+ do_IRQ(AR531X_MISC_IRQ_SPI); -+ else if (misc_intr & AR2315_ISR_TIMER) -+ do_IRQ(AR531X_MISC_IRQ_TIMER); -+ else if (misc_intr & AR2315_ISR_AHB) -+ do_IRQ(AR531X_MISC_IRQ_AHB_PROC); -+ else if (misc_intr & AR2315_ISR_GPIO) -+ ar2315_gpio_irq(); -+ else if (misc_intr & AR2315_ISR_UART0) -+ do_IRQ(AR531X_MISC_IRQ_UART0); -+ else if (misc_intr & AR2315_ISR_WD) -+ do_IRQ(AR531X_MISC_IRQ_WATCHDOG); -+ else -+ do_IRQ(AR531X_MISC_IRQ_NONE); -+ } else if (pending & CAUSEF_IP7) -+ do_IRQ(AR531X_IRQ_CPU_CLOCK); -+} -+ -+static void ar2315_set_gpiointmask(int gpio, int level) -+{ -+ u32 reg; -+ -+ reg = ar231x_read_reg(AR2315_GPIO_INT); -+ reg &= ~(AR2315_GPIO_INT_M | AR2315_GPIO_INT_LVL_M); -+ reg |= gpio | AR2315_GPIO_INT_LVL(level); -+ ar231x_write_reg(AR2315_GPIO_INT, reg); -+} -+ -+static void ar2315_gpio_intr_enable(struct irq_data *d) -+{ -+ unsigned int gpio = d->irq - AR531X_GPIO_IRQ_BASE; -+ -+ /* Enable interrupt with edge detection */ -+ if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(gpio)) != AR2315_GPIO_CR_I(gpio)) -+ return; -+ -+ gpiointmask |= (1 << gpio); -+ ar2315_set_gpiointmask(gpio, 3); -+} -+ -+static void ar2315_gpio_intr_disable(struct irq_data *d) -+{ -+ unsigned int gpio = d->irq - AR531X_GPIO_IRQ_BASE; -+ -+ /* Disable interrupt */ -+ gpiointmask &= ~(1 << gpio); -+ ar2315_set_gpiointmask(gpio, 0); -+} -+ -+static struct irq_chip ar2315_gpio_intr_controller = { -+ .name = "AR2315-GPIO", -+ .irq_ack = ar2315_gpio_intr_disable, -+ .irq_mask_ack = ar2315_gpio_intr_disable, -+ .irq_mask = ar2315_gpio_intr_disable, -+ .irq_unmask = ar2315_gpio_intr_enable, -+}; -+ -+static void -+ar2315_misc_intr_enable(struct irq_data *d) -+{ -+ unsigned int imr; -+ -+ imr = ar231x_read_reg(AR2315_IMR); -+ switch(d->irq) { -+ case AR531X_MISC_IRQ_SPI: -+ imr |= AR2315_ISR_SPI; -+ break; -+ case AR531X_MISC_IRQ_TIMER: -+ imr |= AR2315_ISR_TIMER; -+ break; -+ case AR531X_MISC_IRQ_AHB_PROC: -+ imr |= AR2315_ISR_AHB; -+ break; -+ case AR531X_MISC_IRQ_GPIO: -+ imr |= AR2315_ISR_GPIO; -+ break; -+ case AR531X_MISC_IRQ_UART0: -+ imr |= AR2315_ISR_UART0; -+ break; -+ case AR531X_MISC_IRQ_WATCHDOG: -+ imr |= AR2315_ISR_WD; -+ break; -+ default: -+ break; -+ } -+ ar231x_write_reg(AR2315_IMR, imr); -+} -+ -+static void -+ar2315_misc_intr_disable(struct irq_data *d) -+{ -+ unsigned int imr; -+ -+ imr = ar231x_read_reg(AR2315_IMR); -+ switch(d->irq) { -+ case AR531X_MISC_IRQ_SPI: -+ imr &= ~AR2315_ISR_SPI; -+ break; -+ case AR531X_MISC_IRQ_TIMER: -+ imr &= ~AR2315_ISR_TIMER; -+ break; -+ case AR531X_MISC_IRQ_AHB_PROC: -+ imr &= ~AR2315_ISR_AHB; -+ break; -+ case AR531X_MISC_IRQ_GPIO: -+ imr &= ~AR2315_ISR_GPIO; -+ break; -+ case AR531X_MISC_IRQ_UART0: -+ imr &= ~AR2315_ISR_UART0; -+ break; -+ case AR531X_MISC_IRQ_WATCHDOG: -+ imr &= ~AR2315_ISR_WD; -+ break; -+ default: -+ break; -+ } -+ ar231x_write_reg(AR2315_IMR, imr); -+} -+ -+ -+static struct irq_chip ar2315_misc_intr_controller = { -+ .name = "AR2315-MISC", -+ .irq_mask = ar2315_misc_intr_disable, -+ .irq_unmask = ar2315_misc_intr_enable, -+}; -+ -+static irqreturn_t ar2315_ahb_proc_handler(int cpl, void *dev_id) -+{ -+ ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET); -+ ar231x_read_reg(AR2315_AHB_ERR1); -+ -+ printk(KERN_ERR "AHB fatal error\n"); -+ machine_restart("AHB error"); /* Catastrophic failure */ -+ -+ return IRQ_HANDLED; -+} -+ -+static struct irqaction ar2315_ahb_proc_interrupt = { -+ .handler = ar2315_ahb_proc_handler, -+ .flags = IRQF_DISABLED, -+ .name = "ar2315_ahb_proc_interrupt", -+}; -+ -+static struct irqaction cascade = { -+ .handler = no_action, -+ .flags = IRQF_DISABLED, -+ .name = "cascade", -+}; -+ -+void -+ar2315_irq_init(void) -+{ -+ int i; -+ -+ if (!is_2315()) -+ return; -+ -+ ar231x_irq_dispatch = ar2315_irq_dispatch; -+ gpiointval = ar231x_read_reg(AR2315_GPIO_DI); -+ for (i = 0; i < AR531X_MISC_IRQ_COUNT; i++) { -+ int irq = AR531X_MISC_IRQ_BASE + i; -+ irq_set_chip_and_handler(irq, &ar2315_misc_intr_controller, -+ handle_level_irq); -+ } -+ for (i = 0; i < AR531X_GPIO_IRQ_COUNT; i++) { -+ int irq = AR531X_GPIO_IRQ_BASE + i; -+ irq_set_chip_and_handler(irq, &ar2315_gpio_intr_controller, -+ handle_level_irq); -+ } -+ setup_irq(AR531X_MISC_IRQ_GPIO, &cascade); -+ setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar2315_ahb_proc_interrupt); -+ setup_irq(AR2315_IRQ_MISC_INTRS, &cascade); -+} -+ -+const struct ar231x_gpiodev ar2315_gpiodev; -+ -+static u32 -+ar2315_gpio_get_output(void) -+{ -+ u32 reg; -+ reg = ar231x_read_reg(AR2315_GPIO_CR); -+ reg &= ar2315_gpiodev.valid_mask; -+ return reg; -+} -+ -+static u32 -+ar2315_gpio_set_output(u32 mask, u32 val) -+{ -+ u32 reg; -+ -+ reg = ar231x_read_reg(AR2315_GPIO_CR); -+ reg &= ~mask; -+ reg |= val; -+ ar231x_write_reg(AR2315_GPIO_CR, reg); -+ return reg; -+} -+ -+static u32 -+ar2315_gpio_get(void) -+{ -+ u32 reg; -+ reg = ar231x_read_reg(AR2315_GPIO_DI); -+ reg &= ar2315_gpiodev.valid_mask; -+ return reg; -+} -+ -+static u32 -+ar2315_gpio_set(u32 mask, u32 value) -+{ -+ u32 reg; -+ reg = ar231x_read_reg(AR2315_GPIO_DO); -+ reg &= ~mask; -+ reg |= value; -+ ar231x_write_reg(AR2315_GPIO_DO, reg); -+ return reg; -+} -+ -+const struct ar231x_gpiodev ar2315_gpiodev = { -+ .valid_mask = (1 << 22) - 1, -+ .get_output = ar2315_gpio_get_output, -+ .set_output = ar2315_gpio_set_output, -+ .get = ar2315_gpio_get, -+ .set = ar2315_gpio_set, -+}; -+ -+static struct ar231x_eth ar2315_eth_data = { -+ .reset_base = AR2315_RESET, -+ .reset_mac = AR2315_RESET_ENET0, -+ .reset_phy = AR2315_RESET_EPHY0, -+ .phy_base = KSEG1ADDR(AR2315_ENET0), -+ .config = &ar231x_board, -+}; -+ -+static struct resource ar2315_spiflash_res[] = { -+ { -+ .name = "flash_base", -+ .flags = IORESOURCE_MEM, -+ .start = KSEG1ADDR(AR2315_SPI_READ), -+ .end = KSEG1ADDR(AR2315_SPI_READ) + 0x1000000 - 1, -+ }, -+ { -+ .name = "flash_regs", -+ .flags = IORESOURCE_MEM, -+ .start = 0x11300000, -+ .end = 0x11300012, -+ }, -+}; -+ -+static struct platform_device ar2315_spiflash = { -+ .id = 0, -+ .name = "spiflash", -+ .resource = ar2315_spiflash_res, -+ .num_resources = ARRAY_SIZE(ar2315_spiflash_res) -+}; -+ -+static struct platform_device ar2315_wdt = { -+ .id = 0, -+ .name = "ar2315_wdt", -+}; -+ -+#define SPI_FLASH_CTL 0x00 -+#define SPI_FLASH_OPCODE 0x04 -+#define SPI_FLASH_DATA 0x08 -+ -+static inline u32 -+spiflash_read_reg(int reg) -+{ -+ return ar231x_read_reg(AR2315_SPI + reg); -+} -+ -+static inline void -+spiflash_write_reg(int reg, u32 data) -+{ -+ ar231x_write_reg(AR2315_SPI + reg, data); -+} -+ -+static u32 -+spiflash_wait_status(void) -+{ -+ u32 reg; -+ -+ do { -+ reg = spiflash_read_reg(SPI_FLASH_CTL); -+ } while (reg & SPI_CTL_BUSY); -+ -+ return reg; -+} -+ -+static u8 -+spiflash_probe(void) -+{ -+ u32 reg; -+ -+ reg = spiflash_wait_status(); -+ reg &= ~SPI_CTL_TX_RX_CNT_MASK; -+ reg |= (1 << 4) | 4 | SPI_CTL_START; -+ -+ spiflash_write_reg(SPI_FLASH_OPCODE, 0xab); -+ spiflash_write_reg(SPI_FLASH_CTL, reg); -+ -+ reg = spiflash_wait_status(); -+ reg = spiflash_read_reg(SPI_FLASH_DATA); -+ reg &= 0xff; -+ -+ return (u8) reg; -+} -+ -+ -+#define STM_8MBIT_SIGNATURE 0x13 -+#define STM_16MBIT_SIGNATURE 0x14 -+#define STM_32MBIT_SIGNATURE 0x15 -+#define STM_64MBIT_SIGNATURE 0x16 -+#define STM_128MBIT_SIGNATURE 0x17 -+ -+static u8 __init * -+ar2315_flash_limit(void) -+{ -+ u32 flash_size = 0; -+ -+ /* probe the flash chip size */ -+ switch(spiflash_probe()) { -+ case STM_8MBIT_SIGNATURE: -+ flash_size = 0x00100000; -+ break; -+ case STM_16MBIT_SIGNATURE: -+ flash_size = 0x00200000; -+ break; -+ case STM_32MBIT_SIGNATURE: -+ flash_size = 0x00400000; -+ break; -+ case STM_64MBIT_SIGNATURE: -+ flash_size = 0x00800000; -+ break; -+ case STM_128MBIT_SIGNATURE: -+ flash_size = 0x01000000; -+ break; -+ } -+ -+ ar2315_spiflash_res[0].end = ar2315_spiflash_res[0].start + -+ flash_size - 1; -+ return (u8 *) ar2315_spiflash_res[0].end + 1; -+} -+ -+#ifdef CONFIG_LEDS_GPIO -+static struct gpio_led ar2315_leds[6]; -+static struct gpio_led_platform_data ar2315_led_data = { -+ .leds = (void *) ar2315_leds, -+}; -+ -+static struct platform_device ar2315_gpio_leds = { -+ .name = "leds-gpio", -+ .id = -1, -+ .dev = { -+ .platform_data = (void *) &ar2315_led_data, -+ } -+}; -+ -+static void __init -+ar2315_init_gpio(void) -+{ -+ static char led_names[6][6]; -+ int i, led = 0; -+ -+ ar2315_led_data.num_leds = 0; -+ for(i = 1; i < 8; i++) -+ { -+ if((i == AR2315_RESET_GPIO) || -+ (i == ar231x_board.config->resetConfigGpio)) -+ continue; -+ -+ if(i == ar231x_board.config->sysLedGpio) -+ strcpy(led_names[led], "wlan"); -+ else -+ sprintf(led_names[led], "gpio%d", i); -+ -+ ar2315_leds[led].name = led_names[led]; -+ ar2315_leds[led].gpio = i; -+ ar2315_leds[led].active_low = 0; -+ led++; -+ } -+ ar2315_led_data.num_leds = led; -+ platform_device_register(&ar2315_gpio_leds); -+} -+#else -+static inline void ar2315_init_gpio(void) -+{ -+} -+#endif -+ -+int __init -+ar2315_init_devices(void) -+{ -+ if (!is_2315()) -+ return 0; -+ -+ /* Find board configuration */ -+ ar231x_find_config(ar2315_flash_limit()); -+ ar2315_eth_data.macaddr = ar231x_board.config->enet0_mac; -+ -+ ar2315_init_gpio(); -+ platform_device_register(&ar2315_wdt); -+ platform_device_register(&ar2315_spiflash); -+ ar231x_add_ethernet(0, KSEG1ADDR(AR2315_ENET0), AR2315_IRQ_ENET0_INTRS, -+ &ar2315_eth_data); -+ ar231x_add_wmac(0, AR2315_WLAN0, AR2315_IRQ_WLAN0_INTRS); -+ -+ return 0; -+} -+ -+static void -+ar2315_restart(char *command) -+{ -+ void (*mips_reset_vec)(void) = (void *) 0xbfc00000; -+ -+ local_irq_disable(); -+ -+ /* try reset the system via reset control */ -+ ar231x_write_reg(AR2315_COLD_RESET,AR2317_RESET_SYSTEM); -+ -+ /* Cold reset does not work on the AR2315/6, use the GPIO reset bits a workaround. -+ * give it some time to attempt a gpio based hardware reset -+ * (atheros reference design workaround) */ -+ gpio_direction_output(AR2315_RESET_GPIO, 0); -+ mdelay(100); -+ -+ /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic -+ * workaround. Attempt to jump to the mips reset location - -+ * the boot loader itself might be able to recover the system */ -+ mips_reset_vec(); -+} -+ -+ -+/* -+ * This table is indexed by bits 5..4 of the CLOCKCTL1 register -+ * to determine the predevisor value. -+ */ -+static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = { 1, 2, 4, 5 }; -+static int __initdata PLLC_DIVIDE_TABLE[5] = { 2, 3, 4, 6, 3 }; -+ -+static unsigned int __init -+ar2315_sys_clk(unsigned int clockCtl) -+{ -+ unsigned int pllcCtrl,cpuDiv; -+ unsigned int pllcOut,refdiv,fdiv,divby2; -+ unsigned int clkDiv; -+ -+ pllcCtrl = ar231x_read_reg(AR2315_PLLC_CTL); -+ refdiv = (pllcCtrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S; -+ refdiv = CLOCKCTL1_PREDIVIDE_TABLE[refdiv]; -+ fdiv = (pllcCtrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S; -+ divby2 = (pllcCtrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S; -+ divby2 += 1; -+ pllcOut = (40000000/refdiv)*(2*divby2)*fdiv; -+ -+ -+ /* clkm input selected */ -+ switch(clockCtl & CPUCLK_CLK_SEL_M) { -+ case 0: -+ case 1: -+ clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKM_DIV_M) >> PLLC_CLKM_DIV_S]; -+ break; -+ case 2: -+ clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKC_DIV_M) >> PLLC_CLKC_DIV_S]; -+ break; -+ default: -+ pllcOut = 40000000; -+ clkDiv = 1; -+ break; -+ } -+ cpuDiv = (clockCtl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S; -+ cpuDiv = cpuDiv * 2 ?: 1; -+ return (pllcOut/(clkDiv * cpuDiv)); -+} -+ -+static inline unsigned int -+ar2315_cpu_frequency(void) -+{ -+ return ar2315_sys_clk(ar231x_read_reg(AR2315_CPUCLK)); -+} -+ -+static inline unsigned int -+ar2315_apb_frequency(void) -+{ -+ return ar2315_sys_clk(ar231x_read_reg(AR2315_AMBACLK)); -+} -+ -+void __init -+ar2315_time_init(void) -+{ -+ if (!is_2315()) -+ return; -+ -+ mips_hpt_frequency = ar2315_cpu_frequency() / 2; -+} -+ -+void __init -+ar2315_prom_init(void) -+{ -+ u32 memsize, memcfg, devid; -+ -+ if (!is_2315()) -+ return; -+ -+ memcfg = ar231x_read_reg(AR2315_MEM_CFG); -+ memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S); -+ memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S); -+ memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S); -+ memsize <<= 3; -+ add_memory_region(0, memsize, BOOT_MEM_RAM); -+ -+ /* Detect the hardware based on the device ID */ -+ devid = ar231x_read_reg(AR2315_SREV) & AR2315_REV_CHIP; -+ switch(devid) { -+ case 0x90: -+ case 0x91: -+ ar231x_devtype = DEV_TYPE_AR2317; -+ break; -+ default: -+ ar231x_devtype = DEV_TYPE_AR2315; -+ break; -+ } -+ ar231x_gpiodev = &ar2315_gpiodev; -+ ar231x_board.devid = devid; -+} -+ -+void __init -+ar2315_plat_setup(void) -+{ -+ u32 config; -+ -+ if (!is_2315()) -+ return; -+ -+ /* Clear any lingering AHB errors */ -+ config = read_c0_config(); -+ write_c0_config(config & ~0x3); -+ ar231x_write_reg(AR2315_AHB_ERR0,AHB_ERROR_DET); -+ ar231x_read_reg(AR2315_AHB_ERR1); -+ ar231x_write_reg(AR2315_WDC, AR2315_WDC_IGNORE_EXPIRATION); -+ -+ _machine_restart = ar2315_restart; -+ ar231x_serial_setup(KSEG1ADDR(AR2315_UART0), ar2315_apb_frequency()); -+} -diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/ar2315.h linux-2.6.39-rc7/arch/mips/ar231x/ar2315.h ---- linux-2.6.39-rc7.orig/arch/mips/ar231x/ar2315.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/ar231x/ar2315.h 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,37 @@ -+#ifndef __AR2315_H -+#define __AR2315_H -+ -+#ifdef CONFIG_ATHEROS_AR2315 -+ -+extern void ar2315_irq_init(void); -+extern int ar2315_init_devices(void); -+extern void ar2315_prom_init(void); -+extern void ar2315_plat_setup(void); -+extern void ar2315_time_init(void); -+ -+#else -+ -+static inline void ar2315_irq_init(void) -+{ -+} -+ -+static inline int ar2315_init_devices(void) -+{ -+ return 0; -+} -+ -+static inline void ar2315_prom_init(void) -+{ -+} -+ -+static inline void ar2315_plat_setup(void) -+{ -+} -+ -+static inline void ar2315_time_init(void) -+{ -+} -+ -+#endif -+ -+#endif -diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/ar5312.c linux-2.6.39-rc7/arch/mips/ar231x/ar5312.c ---- linux-2.6.39-rc7.orig/arch/mips/ar231x/ar5312.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/ar231x/ar5312.c 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,538 @@ -+/* -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. -+ * Copyright (C) 2006 FON Technology, SL. -+ * Copyright (C) 2006 Imre Kaloz -+ * Copyright (C) 2006-2009 Felix Fietkau -+ */ -+ -+/* -+ * Platform devices for Atheros SoCs -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include "devices.h" -+#include "ar5312.h" -+ -+static void -+ar5312_misc_irq_dispatch(void) -+{ -+ unsigned int ar231x_misc_intrs = ar231x_read_reg(AR531X_ISR) & ar231x_read_reg(AR531X_IMR); -+ -+ if (ar231x_misc_intrs & AR531X_ISR_TIMER) { -+ do_IRQ(AR531X_MISC_IRQ_TIMER); -+ (void)ar231x_read_reg(AR531X_TIMER); -+ } else if (ar231x_misc_intrs & AR531X_ISR_AHBPROC) -+ do_IRQ(AR531X_MISC_IRQ_AHB_PROC); -+ else if ((ar231x_misc_intrs & AR531X_ISR_UART0)) -+ do_IRQ(AR531X_MISC_IRQ_UART0); -+ else if (ar231x_misc_intrs & AR531X_ISR_WD) -+ do_IRQ(AR531X_MISC_IRQ_WATCHDOG); -+ else -+ do_IRQ(AR531X_MISC_IRQ_NONE); -+} -+ -+static asmlinkage void -+ar5312_irq_dispatch(void) -+{ -+ int pending = read_c0_status() & read_c0_cause(); -+ -+ if (pending & CAUSEF_IP2) -+ do_IRQ(AR5312_IRQ_WLAN0_INTRS); -+ else if (pending & CAUSEF_IP3) -+ do_IRQ(AR5312_IRQ_ENET0_INTRS); -+ else if (pending & CAUSEF_IP4) -+ do_IRQ(AR5312_IRQ_ENET1_INTRS); -+ else if (pending & CAUSEF_IP5) -+ do_IRQ(AR5312_IRQ_WLAN1_INTRS); -+ else if (pending & CAUSEF_IP6) -+ ar5312_misc_irq_dispatch(); -+ else if (pending & CAUSEF_IP7) -+ do_IRQ(AR531X_IRQ_CPU_CLOCK); -+} -+ -+ -+/* Enable the specified AR531X_MISC_IRQ interrupt */ -+static void -+ar5312_misc_intr_enable(struct irq_data *d) -+{ -+ unsigned int imr; -+ -+ imr = ar231x_read_reg(AR531X_IMR); -+ imr |= (1 << (d->irq - AR531X_MISC_IRQ_BASE - 1)); -+ ar231x_write_reg(AR531X_IMR, imr); -+} -+ -+/* Disable the specified AR531X_MISC_IRQ interrupt */ -+static void -+ar5312_misc_intr_disable(struct irq_data *d) -+{ -+ unsigned int imr; -+ -+ imr = ar231x_read_reg(AR531X_IMR); -+ imr &= ~(1 << (d->irq - AR531X_MISC_IRQ_BASE - 1)); -+ ar231x_write_reg(AR531X_IMR, imr); -+ ar231x_read_reg(AR531X_IMR); /* flush write buffer */ -+} -+ -+static struct irq_chip ar5312_misc_intr_controller = { -+ .name = "AR5312-MISC", -+ .irq_mask = ar5312_misc_intr_disable, -+ .irq_unmask = ar5312_misc_intr_enable, -+}; -+ -+ -+static irqreturn_t ar5312_ahb_proc_handler(int cpl, void *dev_id) -+{ -+ u32 proc1 = ar231x_read_reg(AR531X_PROC1); -+ u32 procAddr = ar231x_read_reg(AR531X_PROCADDR); /* clears error state */ -+ u32 dma1 = ar231x_read_reg(AR531X_DMA1); -+ u32 dmaAddr = ar231x_read_reg(AR531X_DMAADDR); /* clears error state */ -+ -+ printk("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n", -+ procAddr, proc1, dmaAddr, dma1); -+ -+ machine_restart("AHB error"); /* Catastrophic failure */ -+ return IRQ_HANDLED; -+} -+ -+ -+static struct irqaction ar5312_ahb_proc_interrupt = { -+ .handler = ar5312_ahb_proc_handler, -+ .flags = IRQF_DISABLED, -+ .name = "ar5312_ahb_proc_interrupt", -+}; -+ -+ -+static struct irqaction cascade = { -+ .handler = no_action, -+ .flags = IRQF_DISABLED, -+ .name = "cascade", -+}; -+ -+void __init ar5312_irq_init(void) -+{ -+ int i; -+ -+ if (!is_5312()) -+ return; -+ -+ ar231x_irq_dispatch = ar5312_irq_dispatch; -+ for (i = 0; i < AR531X_MISC_IRQ_COUNT; i++) { -+ int irq = AR531X_MISC_IRQ_BASE + i; -+ irq_set_chip_and_handler(irq, &ar5312_misc_intr_controller, -+ handle_level_irq); -+ } -+ setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt); -+ setup_irq(AR5312_IRQ_MISC_INTRS, &cascade); -+} -+ -+const struct ar231x_gpiodev ar5312_gpiodev; -+ -+static u32 -+ar5312_gpio_get_output(void) -+{ -+ u32 reg; -+ reg = ~(ar231x_read_reg(AR531X_GPIO_CR)); -+ reg &= ar5312_gpiodev.valid_mask; -+ return reg; -+} -+ -+static u32 -+ar5312_gpio_set_output(u32 mask, u32 val) -+{ -+ u32 reg; -+ -+ reg = ar231x_read_reg(AR531X_GPIO_CR); -+ reg |= mask; -+ reg &= ~val; -+ ar231x_write_reg(AR531X_GPIO_CR, reg); -+ return reg; -+} -+ -+static u32 -+ar5312_gpio_get(void) -+{ -+ u32 reg; -+ reg = ar231x_read_reg(AR531X_GPIO_DI); -+ reg &= ar5312_gpiodev.valid_mask; -+ return reg; -+} -+ -+static u32 -+ar5312_gpio_set(u32 mask, u32 value) -+{ -+ u32 reg; -+ reg = ar231x_read_reg(AR531X_GPIO_DO); -+ reg &= ~mask; -+ reg |= value; -+ ar231x_write_reg(AR531X_GPIO_DO, reg); -+ return reg; -+} -+ -+const struct ar231x_gpiodev ar5312_gpiodev = { -+ .valid_mask = (1 << 8) - 1, -+ .get_output = ar5312_gpio_get_output, -+ .set_output = ar5312_gpio_set_output, -+ .get = ar5312_gpio_get, -+ .set = ar5312_gpio_set, -+}; -+ -+static struct physmap_flash_data ar5312_flash_data = { -+ .width = 2, -+}; -+ -+static struct resource ar5312_flash_resource = { -+ .start = AR531X_FLASH, -+ .end = AR531X_FLASH + 0x800000 - 1, -+ .flags = IORESOURCE_MEM, -+}; -+ -+static struct ar231x_eth ar5312_eth0_data = { -+ .reset_base = AR531X_RESET, -+ .reset_mac = AR531X_RESET_ENET0, -+ .reset_phy = AR531X_RESET_EPHY0, -+ .phy_base = KSEG1ADDR(AR531X_ENET0), -+ .config = &ar231x_board, -+}; -+ -+static struct ar231x_eth ar5312_eth1_data = { -+ .reset_base = AR531X_RESET, -+ .reset_mac = AR531X_RESET_ENET1, -+ .reset_phy = AR531X_RESET_EPHY1, -+ .phy_base = KSEG1ADDR(AR531X_ENET1), -+ .config = &ar231x_board, -+}; -+ -+static struct platform_device ar5312_physmap_flash = { -+ .name = "physmap-flash", -+ .id = 0, -+ .dev.platform_data = &ar5312_flash_data, -+ .resource = &ar5312_flash_resource, -+ .num_resources = 1, -+}; -+ -+#ifdef CONFIG_LEDS_GPIO -+static struct gpio_led ar5312_leds[] = { -+ { .name = "wlan", .gpio = 0, .active_low = 1, }, -+}; -+ -+static const struct gpio_led_platform_data ar5312_led_data = { -+ .num_leds = ARRAY_SIZE(ar5312_leds), -+ .leds = (void *) ar5312_leds, -+}; -+ -+static struct platform_device ar5312_gpio_leds = { -+ .name = "leds-gpio", -+ .id = -1, -+ .dev.platform_data = (void *) &ar5312_led_data, -+}; -+#endif -+ -+/* -+ * NB: This mapping size is larger than the actual flash size, -+ * but this shouldn't be a problem here, because the flash -+ * will simply be mapped multiple times. -+ */ -+static char __init *ar5312_flash_limit(void) -+{ -+ u32 ctl; -+ /* -+ * Configure flash bank 0. -+ * Assume 8M window size. Flash will be aliased if it's smaller -+ */ -+ ctl = FLASHCTL_E | -+ FLASHCTL_AC_8M | -+ FLASHCTL_RBLE | -+ (0x01 << FLASHCTL_IDCY_S) | -+ (0x07 << FLASHCTL_WST1_S) | -+ (0x07 << FLASHCTL_WST2_S) | -+ (ar231x_read_reg(AR531X_FLASHCTL0) & FLASHCTL_MW); -+ -+ ar231x_write_reg(AR531X_FLASHCTL0, ctl); -+ -+ /* Disable other flash banks */ -+ ar231x_write_reg(AR531X_FLASHCTL1, -+ ar231x_read_reg(AR531X_FLASHCTL1) & ~(FLASHCTL_E | FLASHCTL_AC)); -+ -+ ar231x_write_reg(AR531X_FLASHCTL2, -+ ar231x_read_reg(AR531X_FLASHCTL2) & ~(FLASHCTL_E | FLASHCTL_AC)); -+ -+ return (char *) KSEG1ADDR(AR531X_FLASH + 0x800000); -+} -+ -+int __init ar5312_init_devices(void) -+{ -+ struct ar231x_boarddata *config; -+ u32 fctl = 0; -+ const u8 *radio; -+ u8 *c; -+ -+ if (!is_5312()) -+ return 0; -+ -+ /* Locate board/radio config data */ -+ ar231x_find_config(ar5312_flash_limit()); -+ config = ar231x_board.config; -+ -+ -+ /* -+ * Chip IDs and hardware detection for some Atheros -+ * models are really broken! -+ * -+ * Atheros uses a disabled WMAC0 and Silicon ID of AR5312 -+ * as indication for AR2312, which is otherwise -+ * indistinguishable from the real AR5312. -+ */ -+ if (ar231x_board.radio) { -+ radio = ar231x_board.radio + AR531X_RADIO_MASK_OFF; -+ if ((*((const u32 *) radio) & AR531X_RADIO0_MASK) == 0) -+ config->flags |= BD_ISCASPER; -+ } else -+ radio = NULL; -+ -+ /* AR2313 has CPU minor rev. 10 */ -+ if ((current_cpu_data.processor_id & 0xff) == 0x0a) -+ ar231x_devtype = DEV_TYPE_AR2313; -+ -+ /* AR2312 shares the same Silicon ID as AR5312 */ -+ else if (config->flags & BD_ISCASPER) -+ ar231x_devtype = DEV_TYPE_AR2312; -+ -+ /* Everything else is probably AR5312 or compatible */ -+ else -+ ar231x_devtype = DEV_TYPE_AR5312; -+ -+ /* fixup flash width */ -+ fctl = ar231x_read_reg(AR531X_FLASHCTL) & FLASHCTL_MW; -+ switch (fctl) { -+ case FLASHCTL_MWx16: -+ ar5312_flash_data.width = 2; -+ break; -+ case FLASHCTL_MWx8: -+ default: -+ ar5312_flash_data.width = 1; -+ break; -+ } -+ -+ platform_device_register(&ar5312_physmap_flash); -+ -+#ifdef CONFIG_LEDS_GPIO -+ ar5312_leds[0].gpio = config->sysLedGpio; -+ platform_device_register(&ar5312_gpio_leds); -+#endif -+ -+ /* Fix up MAC addresses if necessary */ -+ if (!memcmp(config->enet0_mac, "\xff\xff\xff\xff\xff\xff", 6)) -+ memcpy(config->enet0_mac, config->enet1_mac, 6); -+ -+ /* If ENET0 and ENET1 have the same mac address, -+ * increment the one from ENET1 */ -+ if (memcmp(config->enet0_mac, config->enet1_mac, 6) == 0) { -+ c = config->enet1_mac + 5; -+ while ((c >= config->enet1_mac) && !(++(*c))) -+ c--; -+ } -+ -+ switch(ar231x_devtype) { -+ case DEV_TYPE_AR5312: -+ ar5312_eth0_data.macaddr = config->enet0_mac; -+ ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET0), -+ AR5312_IRQ_ENET0_INTRS, &ar5312_eth0_data); -+ -+ ar5312_eth1_data.macaddr = config->enet1_mac; -+ ar231x_add_ethernet(1, KSEG1ADDR(AR531X_ENET1), -+ AR5312_IRQ_ENET1_INTRS, &ar5312_eth1_data); -+ -+ if (!ar231x_board.radio) -+ return 0; -+ -+ if ((*((u32 *) radio) & AR531X_RADIO0_MASK) && -+ (config->flags & BD_WLAN0)) -+ ar231x_add_wmac(0, AR531X_WLAN0, -+ AR5312_IRQ_WLAN0_INTRS); -+ -+ break; -+ /* -+ * AR2312/3 ethernet uses the PHY of ENET0, but the MAC -+ * of ENET1. Atheros calls it 'twisted' for a reason :) -+ */ -+ case DEV_TYPE_AR2312: -+ case DEV_TYPE_AR2313: -+ ar5312_eth1_data.phy_base = ar5312_eth0_data.phy_base; -+ ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy; -+ ar5312_eth1_data.macaddr = config->enet0_mac; -+ ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET1), -+ AR5312_IRQ_ENET1_INTRS, &ar5312_eth1_data); -+ -+ if (!ar231x_board.radio) -+ return 0; -+ break; -+ default: -+ break; -+ } -+ -+ if ((*((u32 *) radio) & AR531X_RADIO1_MASK) && -+ (config->flags & BD_WLAN1)) -+ ar231x_add_wmac(1, AR531X_WLAN1, -+ AR5312_IRQ_WLAN1_INTRS); -+ -+ return 0; -+} -+ -+ -+static void ar5312_restart(char *command) -+{ -+ /* reset the system */ -+ local_irq_disable(); -+ while(1) { -+ ar231x_write_reg(AR531X_RESET, AR531X_RESET_SYSTEM); -+ } -+} -+ -+ -+/* -+ * This table is indexed by bits 5..4 of the CLOCKCTL1 register -+ * to determine the predevisor value. -+ */ -+static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = { 1, 2, 4, 5 }; -+ -+ -+static int __init -+ar5312_cpu_frequency(void) -+{ -+ unsigned int result; -+ unsigned int predivide_mask, predivide_shift; -+ unsigned int multiplier_mask, multiplier_shift; -+ unsigned int clockCtl1, preDivideSelect, preDivisor, multiplier; -+ unsigned int doubler_mask; -+ u16 devid; -+ -+ /* Trust the bootrom's idea of cpu frequency. */ -+ if ((result = ar231x_read_reg(AR5312_SCRATCH))) -+ return result; -+ -+ devid = ar231x_read_reg(AR531X_REV); -+ devid &= AR531X_REV_MAJ; -+ devid >>= AR531X_REV_MAJ_S; -+ if (devid == AR531X_REV_MAJ_AR2313) { -+ predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK; -+ predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT; -+ multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK; -+ multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT; -+ doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK; -+ } else { /* AR5312 and AR2312 */ -+ predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK; -+ predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT; -+ multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK; -+ multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT; -+ doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK; -+ } -+ -+ /* -+ * Clocking is derived from a fixed 40MHz input clock. -+ * -+ * cpuFreq = InputClock * MULT (where MULT is PLL multiplier) -+ * sysFreq = cpuFreq / 4 (used for APB clock, serial, -+ * flash, Timer, Watchdog Timer) -+ * -+ * cntFreq = cpuFreq / 2 (use for CPU count/compare) -+ * -+ * So, for example, with a PLL multiplier of 5, we have -+ * -+ * cpuFreq = 200MHz -+ * sysFreq = 50MHz -+ * cntFreq = 100MHz -+ * -+ * We compute the CPU frequency, based on PLL settings. -+ */ -+ -+ clockCtl1 = ar231x_read_reg(AR5312_CLOCKCTL1); -+ preDivideSelect = (clockCtl1 & predivide_mask) >> predivide_shift; -+ preDivisor = CLOCKCTL1_PREDIVIDE_TABLE[preDivideSelect]; -+ multiplier = (clockCtl1 & multiplier_mask) >> multiplier_shift; -+ -+ if (clockCtl1 & doubler_mask) { -+ multiplier = multiplier << 1; -+ } -+ return (40000000 / preDivisor) * multiplier; -+} -+ -+static inline int -+ar5312_sys_frequency(void) -+{ -+ return ar5312_cpu_frequency() / 4; -+} -+ -+void __init -+ar5312_time_init(void) -+{ -+ if (!is_5312()) -+ return; -+ -+ mips_hpt_frequency = ar5312_cpu_frequency() / 2; -+} -+ -+ -+void __init -+ar5312_prom_init(void) -+{ -+ u32 memsize, memcfg, bank0AC, bank1AC; -+ u32 devid; -+ -+ if (!is_5312()) -+ return; -+ -+ /* Detect memory size */ -+ memcfg = ar231x_read_reg(AR531X_MEM_CFG1); -+ bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S; -+ bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S; -+ memsize = (bank0AC ? (1 << (bank0AC+1)) : 0) -+ + (bank1AC ? (1 << (bank1AC+1)) : 0); -+ memsize <<= 20; -+ add_memory_region(0, memsize, BOOT_MEM_RAM); -+ -+ devid = ar231x_read_reg(AR531X_REV); -+ devid >>= AR531X_REV_WMAC_MIN_S; -+ devid &= AR531X_REV_CHIP; -+ ar231x_board.devid = (u16) devid; -+ ar231x_gpiodev = &ar5312_gpiodev; -+} -+ -+void __init -+ar5312_plat_setup(void) -+{ -+ if (!is_5312()) -+ return; -+ -+ /* Clear any lingering AHB errors */ -+ ar231x_read_reg(AR531X_PROCADDR); -+ ar231x_read_reg(AR531X_DMAADDR); -+ ar231x_write_reg(AR531X_WD_CTRL, AR531X_WD_CTRL_IGNORE_EXPIRATION); -+ -+ _machine_restart = ar5312_restart; -+ ar231x_serial_setup(KSEG1ADDR(AR531X_UART0), ar5312_sys_frequency()); -+} -+ -diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/ar5312.h linux-2.6.39-rc7/arch/mips/ar231x/ar5312.h ---- linux-2.6.39-rc7.orig/arch/mips/ar231x/ar5312.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/ar231x/ar5312.h 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,38 @@ -+#ifndef __AR5312_H -+#define __AR5312_H -+ -+#ifdef CONFIG_ATHEROS_AR5312 -+ -+extern void ar5312_irq_init(void); -+extern int ar5312_init_devices(void); -+extern void ar5312_prom_init(void); -+extern void ar5312_plat_setup(void); -+extern void ar5312_time_init(void); -+extern void ar5312_time_init(void); -+ -+#else -+ -+static inline void ar5312_irq_init(void) -+{ -+} -+ -+static inline int ar5312_init_devices(void) -+{ -+ return 0; -+} -+ -+static inline void ar5312_prom_init(void) -+{ -+} -+ -+static inline void ar5312_plat_setup(void) -+{ -+} -+ -+static inline void ar5312_time_init(void) -+{ -+} -+ -+#endif -+ -+#endif -diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/board.c linux-2.6.39-rc7/arch/mips/ar231x/board.c ---- linux-2.6.39-rc7.orig/arch/mips/ar231x/board.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/ar231x/board.c 2011-05-15 22:16:11.000000000 +0200 -@@ -0,0 +1,261 @@ -+/* -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. -+ * Copyright (C) 2006 FON Technology, SL. -+ * Copyright (C) 2006 Imre Kaloz -+ * Copyright (C) 2006-2009 Felix Fietkau -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include "devices.h" -+#include "ar5312.h" -+#include "ar2315.h" -+ -+void (*ar231x_irq_dispatch)(void); -+ -+static inline bool -+check_radio_magic(u8 *addr) -+{ -+ addr += 0x7a; /* offset for flash magic */ -+ if ((addr[0] == 0x5a) && (addr[1] == 0xa5)) { -+ return 1; -+ } -+ return 0; -+} -+ -+static inline bool -+check_board_data(u8 *flash_limit, u8 *addr, bool broken) -+{ -+ /* config magic found */ -+ if (*((u32 *)addr) == AR531X_BD_MAGIC) -+ return 1; -+ -+ if (!broken) -+ return 0; -+ -+ if (check_radio_magic(addr + 0xf8)) -+ ar231x_board.radio = addr + 0xf8; -+ if ((addr < flash_limit + 0x10000) && -+ check_radio_magic(addr + 0x10000)) -+ ar231x_board.radio = addr + 0x10000; -+ -+ if (ar231x_board.radio) { -+ /* broken board data detected, use radio data to find the offset, -+ * user will fix this */ -+ return 1; -+ } -+ return 0; -+} -+ -+static u8 * -+find_board_config(u8 *flash_limit, bool broken) -+{ -+ u8 *addr; -+ int found = 0; -+ -+ for (addr = flash_limit - 0x1000; -+ addr >= flash_limit - 0x30000; -+ addr -= 0x1000) { -+ -+ if (check_board_data(flash_limit, addr, broken)) { -+ found = 1; -+ break; -+ } -+ } -+ -+ if (!found) -+ addr = NULL; -+ -+ return addr; -+} -+ -+static u8 * -+find_radio_config(u8 *flash_limit, u8 *board_config) -+{ -+ int found; -+ u8 *radio_config; -+ -+ /* -+ * Now find the start of Radio Configuration data, using heuristics: -+ * Search forward from Board Configuration data by 0x1000 bytes -+ * at a time until we find non-0xffffffff. -+ */ -+ found = 0; -+ for (radio_config = board_config + 0x1000; -+ (radio_config < flash_limit); -+ radio_config += 0x1000) { -+ if ((*(u32 *)radio_config != 0xffffffff) && -+ check_radio_magic(radio_config)) { -+ found = 1; -+ break; -+ } -+ } -+ -+ /* AR2316 relocates radio config to new location */ -+ if (!found) { -+ for (radio_config = board_config + 0xf8; -+ (radio_config < flash_limit - 0x1000 + 0xf8); -+ radio_config += 0x1000) { -+ if ((*(u32 *)radio_config != 0xffffffff) && -+ check_radio_magic(radio_config)) { -+ found = 1; -+ break; -+ } -+ } -+ } -+ -+ if (!found) { -+ printk("Could not find Radio Configuration data\n"); -+ radio_config = 0; -+ } -+ -+ return (u8 *) radio_config; -+} -+ -+int __init -+ar231x_find_config(u8 *flash_limit) -+{ -+ struct ar231x_boarddata *config; -+ unsigned int rcfg_size; -+ int broken_boarddata = 0, i, tmp; -+ u8 *bcfg, *rcfg; -+ u8 *board_data; -+ u8 *radio_data; -+ u32 offset; -+ -+ ar231x_board.config = NULL; -+ ar231x_board.radio = NULL; -+ /* Copy the board and radio data to RAM, because accessing the mapped -+ * memory of the flash directly after booting is not safe */ -+ -+ /* Try to find valid board and radio data */ -+ bcfg = find_board_config(flash_limit, false); -+ -+ /* If that fails, try to at least find valid radio data */ -+ if (!bcfg) { -+ bcfg = find_board_config(flash_limit, true); -+ broken_boarddata = 1; -+ } -+ -+ if (!bcfg) { -+ printk(KERN_WARNING "WARNING: No board configuration data found!\n"); -+ return -ENODEV; -+ } -+ -+ board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL); -+ ar231x_board.config = (struct ar231x_boarddata *) board_data; -+ memcpy(board_data, bcfg, 0x100); -+ if (broken_boarddata) { -+ printk(KERN_WARNING "WARNING: broken board data detected\n"); -+ config = ar231x_board.config; -+ if (!memcmp(config->enet0_mac, "\x00\x00\x00\x00\x00\x00", 6)) { -+ printk(KERN_INFO "Fixing up empty mac addresses\n"); -+ config->resetConfigGpio = 0xffff; -+ config->sysLedGpio = 0xffff; -+ random_ether_addr(config->wlan0_mac); -+ config->wlan0_mac[0] &= ~0x06; -+ random_ether_addr(config->enet0_mac); -+ random_ether_addr(config->enet1_mac); -+ } -+ } -+ -+ -+ /* Radio config starts 0x100 bytes after board config, regardless -+ * of what the physical layout on the flash chip looks like */ -+ -+ if (ar231x_board.radio) -+ rcfg = (u8 *) ar231x_board.radio; -+ else -+ rcfg = find_radio_config(flash_limit, bcfg); -+ -+ if (!rcfg) -+ return -ENODEV; -+ -+ radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff); -+ ar231x_board.radio = radio_data; -+ offset = radio_data - board_data; -+ printk(KERN_INFO "Radio config found at offset 0x%x(0x%x)\n", rcfg - bcfg, offset); -+ rcfg_size = BOARD_CONFIG_BUFSZ - offset; -+ memcpy(radio_data, rcfg, rcfg_size); -+ -+ for (tmp = 0xff, i = 0; i < ETH_ALEN; i++) -+ tmp &= radio_data[i + 0x1d * 2]; -+ if (tmp == 0xff) { -+ u16 *eep = (u16 *)radio_data, *bcfgs = (u16 *)bcfg; -+ printk(KERN_INFO "Radio MAC is blank; using board-data\n"); -+ eep[0x1f] = bcfgs[0x30]; -+ eep[0x1e] = bcfgs[0x34]; -+ eep[0x1d] = bcfgs[0x32]; -+ } -+ -+ return 0; -+} -+ -+static void -+ar231x_halt(void) -+{ -+ local_irq_disable(); -+ while (1); -+} -+ -+void __init -+plat_mem_setup(void) -+{ -+ _machine_halt = ar231x_halt; -+ pm_power_off = ar231x_halt; -+ -+ ar5312_plat_setup(); -+ ar2315_plat_setup(); -+ -+ /* Disable data watchpoints */ -+ write_c0_watchlo0(0); -+} -+ -+ -+asmlinkage void -+plat_irq_dispatch(void) -+{ -+ ar231x_irq_dispatch(); -+} -+ -+void __init -+plat_time_init(void) -+{ -+ ar5312_time_init(); -+ ar2315_time_init(); -+} -+ -+unsigned int __cpuinit -+get_c0_compare_int(void) -+{ -+ return CP0_LEGACY_COMPARE_IRQ; -+} -+ -+void __init -+arch_init_irq(void) -+{ -+ clear_c0_status(ST0_IM); -+ mips_cpu_irq_init(); -+ -+ /* Initialize interrupt controllers */ -+ ar5312_irq_init(); -+ ar2315_irq_init(); -+} -+ -+ -diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/devices.c linux-2.6.39-rc7/arch/mips/ar231x/devices.c ---- linux-2.6.39-rc7.orig/arch/mips/ar231x/devices.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/ar231x/devices.c 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,175 @@ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "devices.h" -+#include "ar5312.h" -+#include "ar2315.h" -+ -+struct ar231x_board_config ar231x_board; -+int ar231x_devtype = DEV_TYPE_UNKNOWN; -+const struct ar231x_gpiodev *ar231x_gpiodev; -+EXPORT_SYMBOL(ar231x_gpiodev); -+ -+static struct resource ar231x_eth0_res[] = { -+ { -+ .name = "eth0_membase", -+ .flags = IORESOURCE_MEM, -+ }, -+ { -+ .name = "eth0_irq", -+ .flags = IORESOURCE_IRQ, -+ } -+}; -+ -+static struct resource ar231x_eth1_res[] = { -+ { -+ .name = "eth1_membase", -+ .flags = IORESOURCE_MEM, -+ }, -+ { -+ .name = "eth1_irq", -+ .flags = IORESOURCE_IRQ, -+ } -+}; -+ -+static struct platform_device ar231x_eth[] = { -+ { -+ .id = 0, -+ .name = "ar231x-eth", -+ .resource = ar231x_eth0_res, -+ .num_resources = ARRAY_SIZE(ar231x_eth0_res) -+ }, -+ { -+ .id = 1, -+ .name = "ar231x-eth", -+ .resource = ar231x_eth1_res, -+ .num_resources = ARRAY_SIZE(ar231x_eth1_res) -+ } -+}; -+ -+static struct resource ar231x_wmac0_res[] = { -+ { -+ .name = "wmac0_membase", -+ .flags = IORESOURCE_MEM, -+ }, -+ { -+ .name = "wmac0_irq", -+ .flags = IORESOURCE_IRQ, -+ } -+}; -+ -+static struct resource ar231x_wmac1_res[] = { -+ { -+ .name = "wmac1_membase", -+ .flags = IORESOURCE_MEM, -+ }, -+ { -+ .name = "wmac1_irq", -+ .flags = IORESOURCE_IRQ, -+ } -+}; -+ -+ -+static struct platform_device ar231x_wmac[] = { -+ { -+ .id = 0, -+ .name = "ar231x-wmac", -+ .resource = ar231x_wmac0_res, -+ .num_resources = ARRAY_SIZE(ar231x_wmac0_res), -+ .dev.platform_data = &ar231x_board, -+ }, -+ { -+ .id = 1, -+ .name = "ar231x-wmac", -+ .resource = ar231x_wmac1_res, -+ .num_resources = ARRAY_SIZE(ar231x_wmac1_res), -+ .dev.platform_data = &ar231x_board, -+ }, -+}; -+ -+static const char *devtype_strings[] = { -+ [DEV_TYPE_AR5312] = "Atheros AR5312", -+ [DEV_TYPE_AR2312] = "Atheros AR2312", -+ [DEV_TYPE_AR2313] = "Atheros AR2313", -+ [DEV_TYPE_AR2315] = "Atheros AR2315", -+ [DEV_TYPE_AR2316] = "Atheros AR2316", -+ [DEV_TYPE_AR2317] = "Atheros AR2317", -+ [DEV_TYPE_UNKNOWN] = "Atheros (unknown)", -+}; -+ -+const char *get_system_type(void) -+{ -+ if ((ar231x_devtype >= ARRAY_SIZE(devtype_strings)) || -+ !devtype_strings[ar231x_devtype]) -+ return devtype_strings[DEV_TYPE_UNKNOWN]; -+ return devtype_strings[ar231x_devtype]; -+} -+ -+ -+int __init -+ar231x_add_ethernet(int nr, u32 base, int irq, void *pdata) -+{ -+ struct resource *res; -+ -+ ar231x_eth[nr].dev.platform_data = pdata; -+ res = &ar231x_eth[nr].resource[0]; -+ res->start = base; -+ res->end = base + 0x2000 - 1; -+ res++; -+ res->start = irq; -+ res->end = irq; -+ return platform_device_register(&ar231x_eth[nr]); -+} -+ -+void __init -+ar231x_serial_setup(u32 mapbase, unsigned int uartclk) -+{ -+ struct uart_port s; -+ -+ memset(&s, 0, sizeof(s)); -+ -+ s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST; -+ s.iotype = UPIO_MEM; -+ s.irq = AR531X_MISC_IRQ_UART0; -+ s.regshift = 2; -+ s.mapbase = mapbase; -+ s.uartclk = uartclk; -+ s.membase = (void __iomem *)s.mapbase; -+ -+ early_serial_setup(&s); -+} -+ -+int __init -+ar231x_add_wmac(int nr, u32 base, int irq) -+{ -+ struct resource *res; -+ -+ ar231x_wmac[nr].dev.platform_data = &ar231x_board; -+ res = &ar231x_wmac[nr].resource[0]; -+ res->start = base; -+ res->end = base + 0x10000 - 1; -+ res++; -+ res->start = irq; -+ res->end = irq; -+ return platform_device_register(&ar231x_wmac[nr]); -+} -+ -+static int __init ar231x_register_devices(void) -+{ -+ static struct resource res = { -+ .start = 0xFFFFFFFF, -+ }; -+ -+ platform_device_register_simple("GPIODEV", 0, &res, 1); -+ ar5312_init_devices(); -+ ar2315_init_devices(); -+ -+ return 0; -+} -+ -+device_initcall(ar231x_register_devices); -diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/devices.h linux-2.6.39-rc7/arch/mips/ar231x/devices.h ---- linux-2.6.39-rc7.orig/arch/mips/ar231x/devices.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/ar231x/devices.h 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,37 @@ -+#ifndef __AR231X_DEVICES_H -+#define __AR231X_DEVICES_H -+ -+enum { -+ /* handled by ar5312.c */ -+ DEV_TYPE_AR2312, -+ DEV_TYPE_AR2313, -+ DEV_TYPE_AR5312, -+ -+ /* handled by ar2315.c */ -+ DEV_TYPE_AR2315, -+ DEV_TYPE_AR2316, -+ DEV_TYPE_AR2317, -+ -+ DEV_TYPE_UNKNOWN -+}; -+ -+extern int ar231x_devtype; -+extern struct ar231x_board_config ar231x_board; -+extern asmlinkage void (*ar231x_irq_dispatch)(void); -+ -+extern int ar231x_find_config(u8 *flash_limit); -+extern void ar231x_serial_setup(u32 mapbase, unsigned int uartclk); -+extern int ar231x_add_wmac(int nr, u32 base, int irq); -+extern int ar231x_add_ethernet(int nr, u32 base, int irq, void *pdata); -+ -+static inline bool is_2315(void) -+{ -+ return (current_cpu_data.cputype == CPU_4KEC); -+} -+ -+static inline bool is_5312(void) -+{ -+ return !is_2315(); -+} -+ -+#endif -diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/early_printk.c linux-2.6.39-rc7/arch/mips/ar231x/early_printk.c ---- linux-2.6.39-rc7.orig/arch/mips/ar231x/early_printk.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/ar231x/early_printk.c 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,44 @@ -+/* -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 2010 Gabor Juhos -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include "devices.h" -+ -+static inline void prom_uart_wr(void __iomem *base, unsigned reg, -+ unsigned char ch) -+{ -+ __raw_writeb(ch, base + 4 * reg); -+} -+ -+static inline unsigned char prom_uart_rr(void __iomem *base, unsigned reg) -+{ -+ return __raw_readb(base + 4 * reg); -+} -+ -+void prom_putchar(unsigned char ch) -+{ -+ static void __iomem *base; -+ -+ if (unlikely(base == NULL)) { -+ if (is_2315()) -+ base = (void __iomem *)(KSEG1ADDR(AR2315_UART0)); -+ else -+ base = (void __iomem *)(KSEG1ADDR(AR531X_UART0)); -+ } -+ -+ while ((prom_uart_rr(base, UART_LSR) & UART_LSR_THRE) == 0); -+ prom_uart_wr(base, UART_TX, ch); -+ while ((prom_uart_rr(base, UART_LSR) & UART_LSR_THRE) == 0); -+} -+ -diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/pci.c linux-2.6.39-rc7/arch/mips/ar231x/pci.c ---- linux-2.6.39-rc7.orig/arch/mips/ar231x/pci.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/ar231x/pci.c 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,230 @@ -+/* -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "devices.h" -+ -+#define AR531X_MEM_BASE 0x80800000UL -+#define AR531X_MEM_SIZE 0x00ffffffUL -+#define AR531X_IO_SIZE 0x00007fffUL -+ -+static unsigned long configspace; -+ -+static int config_access(int devfn, int where, int size, u32 *ptr, bool write) -+{ -+ unsigned long flags; -+ int func = PCI_FUNC(devfn); -+ int dev = PCI_SLOT(devfn); -+ u32 value = 0; -+ int err = 0; -+ u32 addr; -+ -+ if (((dev != 0) && (dev != 3)) || (func > 2)) -+ return PCIBIOS_DEVICE_NOT_FOUND; -+ -+ /* Select Configuration access */ -+ local_irq_save(flags); -+ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, 0, AR2315_PCIMISC_CFG_SEL); -+ mb(); -+ -+ addr = (u32) configspace + (1 << (13 + dev)) + (func << 8) + where; -+ if (size == 1) -+ addr ^= 0x3; -+ else if (size == 2) -+ addr ^= 0x2; -+ -+ if (write) { -+ value = *ptr; -+ if (size == 1) -+ err = put_dbe(value, (u8 *) addr); -+ else if (size == 2) -+ err = put_dbe(value, (u16 *) addr); -+ else if (size == 4) -+ err = put_dbe(value, (u32 *) addr); -+ } else { -+ if (size == 1) -+ err = get_dbe(value, (u8 *) addr); -+ else if (size == 2) -+ err = get_dbe(value, (u16 *) addr); -+ else if (size == 4) -+ err = get_dbe(value, (u32 *) addr); -+ if (err) -+ *ptr = 0xffffffff; -+ else -+ *ptr = value; -+ } -+ -+ /* Select Memory access */ -+ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_CFG_SEL, 0); -+ local_irq_restore(flags); -+ -+ return (err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL); -+} -+ -+static int ar231x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * value) -+{ -+ return config_access(devfn, where, size, value, 0); -+} -+ -+static int ar231x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value) -+{ -+ return config_access(devfn, where, size, &value, 1); -+} -+ -+struct pci_ops ar231x_pci_ops = { -+ .read = ar231x_pci_read, -+ .write = ar231x_pci_write, -+}; -+ -+static struct resource ar231x_mem_resource = { -+ .name = "AR531x PCI MEM", -+ .start = AR531X_MEM_BASE, -+ .end = AR531X_MEM_BASE + AR531X_MEM_SIZE - AR531X_IO_SIZE - 1 + 0x4000000, -+ .flags = IORESOURCE_MEM, -+}; -+ -+static struct resource ar231x_io_resource = { -+ .name = "AR531x PCI I/O", -+ .start = AR531X_MEM_BASE + AR531X_MEM_SIZE - AR531X_IO_SIZE, -+ .end = AR531X_MEM_BASE + AR531X_MEM_SIZE - 1, -+ .flags = IORESOURCE_IO, -+}; -+ -+struct pci_controller ar231x_pci_controller = { -+ .pci_ops = &ar231x_pci_ops, -+ .mem_resource = &ar231x_mem_resource, -+ .io_resource = &ar231x_io_resource, -+ .mem_offset = 0x00000000UL, -+ .io_offset = 0x00000000UL, -+}; -+ -+int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -+{ -+ return AR2315_IRQ_LCBUS_PCI; -+} -+ -+int pcibios_plat_dev_init(struct pci_dev *dev) -+{ -+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 5); -+ pci_write_config_word(dev, 0x40, 0); -+ -+ /* Clear any pending Abort or external Interrupts -+ * and enable interrupt processing */ -+ ar231x_mask_reg(AR2315_PCI_INTEN_REG, AR2315_PCI_INT_ENABLE, 0); -+ ar231x_write_reg(AR2315_PCI_INT_STATUS, (AR2315_PCI_ABORT_INT | AR2315_PCI_EXT_INT)); -+ ar231x_write_reg(AR2315_PCI_INT_MASK, (AR2315_PCI_ABORT_INT | AR2315_PCI_EXT_INT)); -+ ar231x_mask_reg(AR2315_PCI_INTEN_REG, 0, AR2315_PCI_INT_ENABLE); -+ -+ return 0; -+} -+ -+static void -+ar2315_pci_fixup(struct pci_dev *dev) -+{ -+ unsigned int devfn = dev->devfn; -+ -+ if (dev->bus->number != 0) -+ return; -+ -+ /* Only fix up the PCI host settings */ -+ if ((PCI_SLOT(devfn) != 3) || (PCI_FUNC(devfn) != 0)) -+ return; -+ -+ /* Fix up MBARs */ -+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, HOST_PCI_MBAR0); -+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, HOST_PCI_MBAR1); -+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, HOST_PCI_MBAR2); -+ pci_write_config_dword(dev, PCI_COMMAND, -+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL | -+ PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | -+ PCI_COMMAND_FAST_BACK); -+} -+DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, ar2315_pci_fixup); -+ -+static int __init -+ar2315_pci_init(void) -+{ -+ u32 reg; -+ -+ if (ar231x_devtype != DEV_TYPE_AR2315) -+ return -ENODEV; -+ -+ configspace = (unsigned long) ioremap_nocache(0x80000000, 1*1024*1024); /* Remap PCI config space */ -+ ar231x_pci_controller.io_map_base = -+ (unsigned long) ioremap_nocache(AR531X_MEM_BASE + AR531X_MEM_SIZE, AR531X_IO_SIZE); -+ set_io_port_base(ar231x_pci_controller.io_map_base); /* PCI I/O space */ -+ -+ reg = ar231x_mask_reg(AR2315_RESET, 0, AR2315_RESET_PCIDMA); -+ msleep(10); -+ -+ reg &= ~AR2315_RESET_PCIDMA; -+ ar231x_write_reg(AR2315_RESET, reg); -+ msleep(10); -+ -+ ar231x_mask_reg(AR2315_ENDIAN_CTL, 0, -+ AR2315_CONFIG_PCIAHB | AR2315_CONFIG_PCIAHB_BRIDGE); -+ -+ ar231x_write_reg(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM | -+ (AR2315_PCICLK_IN_FREQ_DIV_6 << AR2315_PCICLK_DIV_S)); -+ ar231x_mask_reg(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI); -+ ar231x_mask_reg(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK | AR2315_IF_MASK, -+ AR2315_IF_PCI | AR2315_IF_PCI_HOST | AR2315_IF_PCI_INTR | -+ (AR2315_IF_PCI_CLK_OUTPUT_CLK << AR2315_IF_PCI_CLK_SHIFT)); -+ -+ /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */ -+ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE, -+ AR2315_PCIRST_LOW); -+ msleep(100); -+ -+ /* Bring the PCI out of reset */ -+ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE, -+ AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8); -+ -+ ar231x_write_reg(AR2315_PCI_UNCACHE_CFG, -+ 0x1E | /* 1GB uncached */ -+ (1 << 5) | /* Enable uncached */ -+ (0x2 << 30) /* Base: 0x80000000 */ -+ ); -+ ar231x_read_reg(AR2315_PCI_UNCACHE_CFG); -+ -+ msleep(500); -+ -+ /* dirty hack - anyone with a datasheet that knows the memory map ? */ -+ ioport_resource.start = 0x10000000; -+ ioport_resource.end = 0xffffffff; -+ iomem_resource.start = 0x10000000; -+ iomem_resource.end = 0xffffffff; -+ -+ register_pci_controller(&ar231x_pci_controller); -+ -+ return 0; -+} -+ -+arch_initcall(ar2315_pci_init); -diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/prom.c linux-2.6.39-rc7/arch/mips/ar231x/prom.c ---- linux-2.6.39-rc7.orig/arch/mips/ar231x/prom.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/ar231x/prom.c 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,37 @@ -+/* -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright MontaVista Software Inc -+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. -+ * Copyright (C) 2006 FON Technology, SL. -+ * Copyright (C) 2006 Imre Kaloz -+ * Copyright (C) 2006 Felix Fietkau -+ */ -+ -+/* -+ * Prom setup file for ar531x -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include "ar5312.h" -+#include "ar2315.h" -+ -+void __init prom_init(void) -+{ -+ ar5312_prom_init(); -+ ar2315_prom_init(); -+} -+ -+void __init prom_free_prom_memory(void) -+{ -+} -diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/reset.c linux-2.6.39-rc7/arch/mips/ar231x/reset.c ---- linux-2.6.39-rc7.orig/arch/mips/ar231x/reset.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/ar231x/reset.c 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,161 @@ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "devices.h" -+ -+#define AR531X_RESET_GPIO_IRQ (AR531X_GPIO_IRQ(ar231x_board.config->resetConfigGpio)) -+ -+struct event_t { -+ struct work_struct wq; -+ int set; -+ unsigned long jiffies; -+}; -+ -+static struct timer_list rst_button_timer; -+static unsigned long seen; -+ -+struct sock *uevent_sock = NULL; -+EXPORT_SYMBOL_GPL(uevent_sock); -+extern u64 uevent_next_seqnum(void); -+ -+static int no_release_workaround = 1; -+module_param(no_release_workaround, int, 0); -+ -+static inline void -+add_msg(struct sk_buff *skb, char *msg) -+{ -+ char *scratch; -+ scratch = skb_put(skb, strlen(msg) + 1); -+ sprintf(scratch, msg); -+} -+ -+static void -+hotplug_button(struct work_struct *wq) -+{ -+ struct sk_buff *skb; -+ struct event_t *event; -+ size_t len; -+ char *scratch, *s; -+ char buf[128]; -+ -+ event = container_of(wq, struct event_t, wq); -+ if (!uevent_sock) -+ goto done; -+ -+ /* allocate message with the maximum possible size */ -+ s = event->set ? "pressed" : "released"; -+ len = strlen(s) + 2; -+ skb = alloc_skb(NLMSG_GOODSIZE, GFP_KERNEL); -+ if (!skb) -+ goto done; -+ -+ /* add header */ -+ scratch = skb_put(skb, len); -+ sprintf(scratch, "%s@",s); -+ -+ /* copy keys to our continuous event payload buffer */ -+ add_msg(skb, "HOME=/"); -+ add_msg(skb, "PATH=/sbin:/bin:/usr/sbin:/usr/bin"); -+ add_msg(skb, "SUBSYSTEM=button"); -+ add_msg(skb, "BUTTON=reset"); -+ add_msg(skb, (event->set ? "ACTION=pressed" : "ACTION=released")); -+ sprintf(buf, "SEEN=%ld", (event->jiffies - seen)/HZ); -+ add_msg(skb, buf); -+ snprintf(buf, 128, "SEQNUM=%llu", uevent_next_seqnum()); -+ add_msg(skb, buf); -+ -+ NETLINK_CB(skb).dst_group = 1; -+ netlink_broadcast(uevent_sock, skb, 0, 1, GFP_KERNEL); -+ -+done: -+ kfree(event); -+} -+ -+static void -+reset_button_poll(unsigned long unused) -+{ -+ struct event_t *event; -+ int gpio = ~0; -+ -+ if(!no_release_workaround) -+ return; -+ -+ gpio = ar231x_gpiodev->get(); -+ gpio &= (1 << (AR531X_RESET_GPIO_IRQ - AR531X_GPIO_IRQ_BASE)); -+ if(gpio) { -+ rst_button_timer.expires = jiffies + (HZ / 4); -+ add_timer(&rst_button_timer); -+ return; -+ } -+ -+ event = (struct event_t *) kzalloc(sizeof(struct event_t), GFP_ATOMIC); -+ if (!event) -+ return; -+ -+ event->set = 0; -+ event->jiffies = jiffies; -+ INIT_WORK(&event->wq, hotplug_button); -+ schedule_work(&event->wq); -+} -+ -+static irqreturn_t -+button_handler(int irq, void *dev_id) -+{ -+ static int pressed = 0; -+ struct event_t *event; -+ u32 gpio = ~0; -+ -+ event = (struct event_t *) kzalloc(sizeof(struct event_t), GFP_ATOMIC); -+ if (!event) -+ return IRQ_NONE; -+ -+ pressed = !pressed; -+ -+ gpio = ar231x_gpiodev->get() & (1 << (irq - AR531X_GPIO_IRQ_BASE)); -+ -+ event->set = gpio; -+ if(!event->set) -+ no_release_workaround = 0; -+ -+ event->jiffies = jiffies; -+ -+ INIT_WORK(&event->wq, hotplug_button); -+ schedule_work(&event->wq); -+ -+ seen = jiffies; -+ if(event->set && no_release_workaround) -+ mod_timer(&rst_button_timer, jiffies + (HZ / 4)); -+ -+ return IRQ_HANDLED; -+} -+ -+ -+static int __init -+ar231x_init_reset(void) -+{ -+ seen = jiffies; -+ -+ if (ar231x_board.config->resetConfigGpio == 0xffff) -+ return -ENODEV; -+ -+ init_timer(&rst_button_timer); -+ rst_button_timer.function = reset_button_poll; -+ rst_button_timer.expires = jiffies + HZ / 50; -+ add_timer(&rst_button_timer); -+ -+ request_irq(AR531X_RESET_GPIO_IRQ, &button_handler, IRQF_SAMPLE_RANDOM, "ar231x_reset", NULL); -+ -+ return 0; -+} -+ -+module_init(ar231x_init_reset); -diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar2315_regs.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar2315_regs.h ---- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar2315_regs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar2315_regs.h 2011-05-15 21:44:12.000000000 +0200 -@@ -0,0 +1,580 @@ -+/* -+ * Register definitions for AR2315+ -+ * -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. -+ * Copyright (C) 2006 FON Technology, SL. -+ * Copyright (C) 2006 Imre Kaloz -+ * Copyright (C) 2006-2008 Felix Fietkau -+ */ -+ -+#ifndef __AR2315_REG_H -+#define __AR2315_REG_H -+ -+/* -+ * IRQs -+ */ -+#define AR2315_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */ -+#define AR2315_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */ -+#define AR2315_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */ -+#define AR2315_IRQ_LCBUS_PCI MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */ -+#define AR2315_IRQ_WLAN0_POLL MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */ -+ -+/* -+ * Address map -+ */ -+#define AR2315_SPI_READ 0x08000000 /* SPI FLASH */ -+#define AR2315_WLAN0 0x10000000 /* Wireless MMR */ -+#define AR2315_PCI 0x10100000 /* PCI MMR */ -+#define AR2315_SDRAMCTL 0x10300000 /* SDRAM MMR */ -+#define AR2315_LOCAL 0x10400000 /* LOCAL BUS MMR */ -+#define AR2315_ENET0 0x10500000 /* ETHERNET MMR */ -+#define AR2315_DSLBASE 0x11000000 /* RESET CONTROL MMR */ -+#define AR2315_UART0 0x11100003 /* UART MMR */ -+#define AR2315_SPI 0x11300000 /* SPI FLASH MMR */ -+#define AR2315_PCIEXT 0x80000000 /* pci external */ -+ -+/* -+ * Reset Register -+ */ -+#define AR2315_COLD_RESET (AR2315_DSLBASE + 0x0000) -+ -+#define AR2315_RESET_COLD_AHB 0x00000001 -+#define AR2315_RESET_COLD_APB 0x00000002 -+#define AR2315_RESET_COLD_CPU 0x00000004 -+#define AR2315_RESET_COLD_CPUWARM 0x00000008 -+#define AR2315_RESET_SYSTEM (RESET_COLD_CPU | RESET_COLD_APB | RESET_COLD_AHB) /* full system */ -+#define AR2317_RESET_SYSTEM 0x00000010 -+ -+ -+#define AR2315_RESET (AR2315_DSLBASE + 0x0004) -+ -+#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001 /* warm reset WLAN0 MAC */ -+#define AR2315_RESET_WARM_WLAN0_BB 0x00000002 /* warm reset WLAN0 BaseBand */ -+#define AR2315_RESET_MPEGTS_RSVD 0x00000004 /* warm reset MPEG-TS */ -+#define AR2315_RESET_PCIDMA 0x00000008 /* warm reset PCI ahb/dma */ -+#define AR2315_RESET_MEMCTL 0x00000010 /* warm reset memory controller */ -+#define AR2315_RESET_LOCAL 0x00000020 /* warm reset local bus */ -+#define AR2315_RESET_I2C_RSVD 0x00000040 /* warm reset I2C bus */ -+#define AR2315_RESET_SPI 0x00000080 /* warm reset SPI interface */ -+#define AR2315_RESET_UART0 0x00000100 /* warm reset UART0 */ -+#define AR2315_RESET_IR_RSVD 0x00000200 /* warm reset IR interface */ -+#define AR2315_RESET_EPHY0 0x00000400 /* cold reset ENET0 phy */ -+#define AR2315_RESET_ENET0 0x00000800 /* cold reset ENET0 mac */ -+ -+/* -+ * AHB master arbitration control -+ */ -+#define AR2315_AHB_ARB_CTL (AR2315_DSLBASE + 0x0008) -+ -+#define AR2315_ARB_CPU 0x00000001 /* CPU, default */ -+#define AR2315_ARB_WLAN 0x00000002 /* WLAN */ -+#define AR2315_ARB_MPEGTS_RSVD 0x00000004 /* MPEG-TS */ -+#define AR2315_ARB_LOCAL 0x00000008 /* LOCAL */ -+#define AR2315_ARB_PCI 0x00000010 /* PCI */ -+#define AR2315_ARB_ETHERNET 0x00000020 /* Ethernet */ -+#define AR2315_ARB_RETRY 0x00000100 /* retry policy, debug only */ -+ -+/* -+ * Config Register -+ */ -+#define AR2315_ENDIAN_CTL (AR2315_DSLBASE + 0x000c) -+ -+#define AR2315_CONFIG_AHB 0x00000001 /* EC - AHB bridge endianess */ -+#define AR2315_CONFIG_WLAN 0x00000002 /* WLAN byteswap */ -+#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004 /* MPEG-TS byteswap */ -+#define AR2315_CONFIG_PCI 0x00000008 /* PCI byteswap */ -+#define AR2315_CONFIG_MEMCTL 0x00000010 /* Memory controller endianess */ -+#define AR2315_CONFIG_LOCAL 0x00000020 /* Local bus byteswap */ -+#define AR2315_CONFIG_ETHERNET 0x00000040 /* Ethernet byteswap */ -+ -+#define AR2315_CONFIG_MERGE 0x00000200 /* CPU write buffer merge */ -+#define AR2315_CONFIG_CPU 0x00000400 /* CPU big endian */ -+#define AR2315_CONFIG_PCIAHB 0x00000800 -+#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000 -+#define AR2315_CONFIG_SPI 0x00008000 /* SPI byteswap */ -+#define AR2315_CONFIG_CPU_DRAM 0x00010000 -+#define AR2315_CONFIG_CPU_PCI 0x00020000 -+#define AR2315_CONFIG_CPU_MMR 0x00040000 -+#define AR2315_CONFIG_BIG 0x00000400 -+ -+ -+/* -+ * NMI control -+ */ -+#define AR2315_NMI_CTL (AR2315_DSLBASE + 0x0010) -+ -+#define AR2315_NMI_EN 1 -+ -+/* -+ * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR531X 1.0). -+ */ -+#define AR2315_SREV (AR2315_DSLBASE + 0x0014) -+ -+#define AR2315_REV_MAJ 0x00f0 -+#define AR2315_REV_MAJ_S 4 -+#define AR2315_REV_MIN 0x000f -+#define AR2315_REV_MIN_S 0 -+#define AR2315_REV_CHIP (AR2315_REV_MAJ|AR2315_REV_MIN) -+ -+/* -+ * Interface Enable -+ */ -+#define AR2315_IF_CTL (AR2315_DSLBASE + 0x0018) -+ -+#define AR2315_IF_MASK 0x00000007 -+#define AR2315_IF_DISABLED 0 -+#define AR2315_IF_PCI 1 -+#define AR2315_IF_TS_LOCAL 2 -+#define AR2315_IF_ALL 3 /* only for emulation with separate pins */ -+#define AR2315_IF_LOCAL_HOST 0x00000008 -+#define AR2315_IF_PCI_HOST 0x00000010 -+#define AR2315_IF_PCI_INTR 0x00000020 -+#define AR2315_IF_PCI_CLK_MASK 0x00030000 -+#define AR2315_IF_PCI_CLK_INPUT 0 -+#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1 -+#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2 -+#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3 -+#define AR2315_IF_PCI_CLK_SHIFT 16 -+ -+/* -+ * APB Interrupt control -+ */ -+ -+#define AR2315_ISR (AR2315_DSLBASE + 0x0020) -+#define AR2315_IMR (AR2315_DSLBASE + 0x0024) -+#define AR2315_GISR (AR2315_DSLBASE + 0x0028) -+ -+#define AR2315_ISR_UART0 0x0001 /* high speed UART */ -+#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */ -+#define AR2315_ISR_SPI 0x0004 /* SPI bus */ -+#define AR2315_ISR_AHB 0x0008 /* AHB error */ -+#define AR2315_ISR_APB 0x0010 /* APB error */ -+#define AR2315_ISR_TIMER 0x0020 /* timer */ -+#define AR2315_ISR_GPIO 0x0040 /* GPIO */ -+#define AR2315_ISR_WD 0x0080 /* watchdog */ -+#define AR2315_ISR_IR_RSVD 0x0100 /* IR */ -+ -+#define AR2315_GISR_MISC 0x0001 -+#define AR2315_GISR_WLAN0 0x0002 -+#define AR2315_GISR_MPEGTS_RSVD 0x0004 -+#define AR2315_GISR_LOCALPCI 0x0008 -+#define AR2315_GISR_WMACPOLL 0x0010 -+#define AR2315_GISR_TIMER 0x0020 -+#define AR2315_GISR_ETHERNET 0x0040 -+ -+/* -+ * Interrupt routing from IO to the processor IP bits -+ * Define our inter mask and level -+ */ -+#define AR2315_INTR_MISCIO SR_IBIT3 -+#define AR2315_INTR_WLAN0 SR_IBIT4 -+#define AR2315_INTR_ENET0 SR_IBIT5 -+#define AR2315_INTR_LOCALPCI SR_IBIT6 -+#define AR2315_INTR_WMACPOLL SR_IBIT7 -+#define AR2315_INTR_COMPARE SR_IBIT8 -+ -+/* -+ * Timers -+ */ -+#define AR2315_TIMER (AR2315_DSLBASE + 0x0030) -+#define AR2315_RELOAD (AR2315_DSLBASE + 0x0034) -+#define AR2315_WD (AR2315_DSLBASE + 0x0038) -+#define AR2315_WDC (AR2315_DSLBASE + 0x003c) -+ -+#define AR2315_WDC_IGNORE_EXPIRATION 0x00000000 -+#define AR2315_WDC_NMI 0x00000001 /* NMI on watchdog */ -+#define AR2315_WDC_RESET 0x00000002 /* reset on watchdog */ -+ -+/* -+ * CPU Performance Counters -+ */ -+#define AR2315_PERFCNT0 (AR2315_DSLBASE + 0x0048) -+#define AR2315_PERFCNT1 (AR2315_DSLBASE + 0x004c) -+ -+#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */ -+#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */ -+#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */ -+#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */ -+#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */ -+#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */ -+#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */ -+ -+#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */ -+#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */ -+#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */ -+#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */ -+#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */ -+#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */ -+#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */ -+ -+/* -+ * AHB Error Reporting. -+ */ -+#define AR2315_AHB_ERR0 (AR2315_DSLBASE + 0x0050) /* error */ -+#define AR2315_AHB_ERR1 (AR2315_DSLBASE + 0x0054) /* haddr */ -+#define AR2315_AHB_ERR2 (AR2315_DSLBASE + 0x0058) /* hwdata */ -+#define AR2315_AHB_ERR3 (AR2315_DSLBASE + 0x005c) /* hrdata */ -+#define AR2315_AHB_ERR4 (AR2315_DSLBASE + 0x0060) /* status */ -+ -+#define AHB_ERROR_DET 1 /* AHB Error has been detected, */ -+ /* write 1 to clear all bits in ERR0 */ -+#define AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */ -+#define AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */ -+ -+#define AR2315_PROCERR_HMAST 0x0000000f -+#define AR2315_PROCERR_HMAST_DFLT 0 -+#define AR2315_PROCERR_HMAST_WMAC 1 -+#define AR2315_PROCERR_HMAST_ENET 2 -+#define AR2315_PROCERR_HMAST_PCIENDPT 3 -+#define AR2315_PROCERR_HMAST_LOCAL 4 -+#define AR2315_PROCERR_HMAST_CPU 5 -+#define AR2315_PROCERR_HMAST_PCITGT 6 -+ -+#define AR2315_PROCERR_HMAST_S 0 -+#define AR2315_PROCERR_HWRITE 0x00000010 -+#define AR2315_PROCERR_HSIZE 0x00000060 -+#define AR2315_PROCERR_HSIZE_S 5 -+#define AR2315_PROCERR_HTRANS 0x00000180 -+#define AR2315_PROCERR_HTRANS_S 7 -+#define AR2315_PROCERR_HBURST 0x00000e00 -+#define AR2315_PROCERR_HBURST_S 9 -+ -+/* -+ * Clock Control -+ */ -+#define AR2315_PLLC_CTL (AR2315_DSLBASE + 0x0064) -+#define AR2315_PLLV_CTL (AR2315_DSLBASE + 0x0068) -+#define AR2315_CPUCLK (AR2315_DSLBASE + 0x006c) -+#define AR2315_AMBACLK (AR2315_DSLBASE + 0x0070) -+#define AR2315_SYNCCLK (AR2315_DSLBASE + 0x0074) -+#define AR2315_DSL_SLEEP_CTL (AR2315_DSLBASE + 0x0080) -+#define AR2315_DSL_SLEEP_DUR (AR2315_DSLBASE + 0x0084) -+ -+/* PLLc Control fields */ -+#define PLLC_REF_DIV_M 0x00000003 -+#define PLLC_REF_DIV_S 0 -+#define PLLC_FDBACK_DIV_M 0x0000007C -+#define PLLC_FDBACK_DIV_S 2 -+#define PLLC_ADD_FDBACK_DIV_M 0x00000080 -+#define PLLC_ADD_FDBACK_DIV_S 7 -+#define PLLC_CLKC_DIV_M 0x0001c000 -+#define PLLC_CLKC_DIV_S 14 -+#define PLLC_CLKM_DIV_M 0x00700000 -+#define PLLC_CLKM_DIV_S 20 -+ -+/* CPU CLK Control fields */ -+#define CPUCLK_CLK_SEL_M 0x00000003 -+#define CPUCLK_CLK_SEL_S 0 -+#define CPUCLK_CLK_DIV_M 0x0000000c -+#define CPUCLK_CLK_DIV_S 2 -+ -+/* AMBA CLK Control fields */ -+#define AMBACLK_CLK_SEL_M 0x00000003 -+#define AMBACLK_CLK_SEL_S 0 -+#define AMBACLK_CLK_DIV_M 0x0000000c -+#define AMBACLK_CLK_DIV_S 2 -+ -+/* -+ * GPIO -+ */ -+#define AR2315_GPIO_DI (AR2315_DSLBASE + 0x0088) -+#define AR2315_GPIO_DO (AR2315_DSLBASE + 0x0090) -+#define AR2315_GPIO_CR (AR2315_DSLBASE + 0x0098) -+#define AR2315_GPIO_INT (AR2315_DSLBASE + 0x00a0) -+ -+#define AR2315_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */ -+#define AR2315_GPIO_CR_O(x) (1 << (x)) /* output */ -+#define AR2315_GPIO_CR_I(x) (0) /* input */ -+ -+#define AR2315_GPIO_INT_S(x) (x) /* interrupt enable */ -+#define AR2315_GPIO_INT_M (0x3F) /* mask for int */ -+#define AR2315_GPIO_INT_LVL(x) ((x) << 6) /* interrupt level */ -+#define AR2315_GPIO_INT_LVL_M ((0x3) << 6) /* mask for int level */ -+ -+#define AR2315_GPIO_INT_MAX_Y 1 /* Maximum value of Y for AR5313_GPIO_INT_* macros */ -+#define AR2315_GPIO_INT_LVL_OFF 0 /* Triggerring off */ -+#define AR2315_GPIO_INT_LVL_LOW 1 /* Low Level Triggered */ -+#define AR2315_GPIO_INT_LVL_HIGH 2 /* High Level Triggered */ -+#define AR2315_GPIO_INT_LVL_EDGE 3 /* Edge Triggered */ -+ -+#define AR2315_RESET_GPIO 5 -+#define AR2315_NUM_GPIO 22 -+ -+/* -+ * PCI Clock Control -+ */ -+#define AR2315_PCICLK (AR2315_DSLBASE + 0x00a4) -+ -+#define AR2315_PCICLK_INPUT_M 0x3 -+#define AR2315_PCICLK_INPUT_S 0 -+ -+#define AR2315_PCICLK_PLLC_CLKM 0 -+#define AR2315_PCICLK_PLLC_CLKM1 1 -+#define AR2315_PCICLK_PLLC_CLKC 2 -+#define AR2315_PCICLK_REF_CLK 3 -+ -+#define AR2315_PCICLK_DIV_M 0xc -+#define AR2315_PCICLK_DIV_S 2 -+ -+#define AR2315_PCICLK_IN_FREQ 0 -+#define AR2315_PCICLK_IN_FREQ_DIV_6 1 -+#define AR2315_PCICLK_IN_FREQ_DIV_8 2 -+#define AR2315_PCICLK_IN_FREQ_DIV_10 3 -+ -+/* -+ * Observation Control Register -+ */ -+#define AR2315_OCR (AR2315_DSLBASE + 0x00b0) -+#define OCR_GPIO0_IRIN 0x0040 -+#define OCR_GPIO1_IROUT 0x0080 -+#define OCR_GPIO3_RXCLR 0x0200 -+ -+/* -+ * General Clock Control -+ */ -+ -+#define AR2315_MISCCLK (AR2315_DSLBASE + 0x00b4) -+#define MISCCLK_PLLBYPASS_EN 0x00000001 -+#define MISCCLK_PROCREFCLK 0x00000002 -+ -+/* -+ * SDRAM Controller -+ * - No read or write buffers are included. -+ */ -+#define AR2315_MEM_CFG (AR2315_SDRAMCTL + 0x00) -+#define AR2315_MEM_CTRL (AR2315_SDRAMCTL + 0x0c) -+#define AR2315_MEM_REF (AR2315_SDRAMCTL + 0x10) -+ -+#define SDRAM_DATA_WIDTH_M 0x00006000 -+#define SDRAM_DATA_WIDTH_S 13 -+ -+#define SDRAM_COL_WIDTH_M 0x00001E00 -+#define SDRAM_COL_WIDTH_S 9 -+ -+#define SDRAM_ROW_WIDTH_M 0x000001E0 -+#define SDRAM_ROW_WIDTH_S 5 -+ -+#define SDRAM_BANKADDR_BITS_M 0x00000018 -+#define SDRAM_BANKADDR_BITS_S 3 -+ -+/* -+ * SPI Flash Interface Registers -+ */ -+ -+#define AR2315_SPI_CTL (AR2315_SPI + 0x00) -+#define AR2315_SPI_OPCODE (AR2315_SPI + 0x04) -+#define AR2315_SPI_DATA (AR2315_SPI + 0x08) -+ -+#define SPI_CTL_START 0x00000100 -+#define SPI_CTL_BUSY 0x00010000 -+#define SPI_CTL_TXCNT_MASK 0x0000000f -+#define SPI_CTL_RXCNT_MASK 0x000000f0 -+#define SPI_CTL_TX_RX_CNT_MASK 0x000000ff -+#define SPI_CTL_SIZE_MASK 0x00060000 -+ -+#define SPI_CTL_CLK_SEL_MASK 0x03000000 -+#define SPI_OPCODE_MASK 0x000000ff -+ -+/* -+ * PCI Bus Interface Registers -+ */ -+#define AR2315_PCI_1MS_REG (AR2315_PCI + 0x0008) -+#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */ -+ -+#define AR2315_PCI_MISC_CONFIG (AR2315_PCI + 0x000c) -+#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */ -+#define AR2315_PCIMISC_CFG_SEL 0x00000002 /* mem or config cycles */ -+#define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */ -+#define AR2315_PCIMISC_RST_MODE 0x00000030 -+#define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */ -+#define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */ -+#define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */ -+#define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */ -+#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */ -+#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */ -+#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */ -+#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache disable */ -+ -+#define AR2315_PCI_OUT_TSTAMP (AR2315_PCI + 0x0010) -+ -+#define AR2315_PCI_UNCACHE_CFG (AR2315_PCI + 0x0014) -+ -+#define AR2315_PCI_IN_EN (AR2315_PCI + 0x0100) -+#define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */ -+#define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */ -+#define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */ -+#define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */ -+ -+#define AR2315_PCI_IN_DIS (AR2315_PCI + 0x0104) -+#define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */ -+#define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */ -+#define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */ -+#define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */ -+ -+#define AR2315_PCI_IN_PTR (AR2315_PCI + 0x0200) -+ -+#define AR2315_PCI_OUT_EN (AR2315_PCI + 0x0400) -+#define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */ -+ -+#define AR2315_PCI_OUT_DIS (AR2315_PCI + 0x0404) -+#define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */ -+ -+#define AR2315_PCI_OUT_PTR (AR2315_PCI + 0x0408) -+ -+#define AR2315_PCI_INT_STATUS (AR2315_PCI + 0x0500) /* write one to clr */ -+#define AR2315_PCI_TXINT 0x00000001 /* Desc In Completed */ -+#define AR2315_PCI_TXOK 0x00000002 /* Desc In OK */ -+#define AR2315_PCI_TXERR 0x00000004 /* Desc In ERR */ -+#define AR2315_PCI_TXEOL 0x00000008 /* Desc In End-of-List */ -+#define AR2315_PCI_RXINT 0x00000010 /* Desc Out Completed */ -+#define AR2315_PCI_RXOK 0x00000020 /* Desc Out OK */ -+#define AR2315_PCI_RXERR 0x00000040 /* Desc Out ERR */ -+#define AR2315_PCI_RXEOL 0x00000080 /* Desc Out EOL */ -+#define AR2315_PCI_TXOOD 0x00000200 /* Desc In Out-of-Desc */ -+#define AR2315_PCI_MASK 0x0000FFFF /* Desc Mask */ -+#define AR2315_PCI_EXT_INT 0x02000000 -+#define AR2315_PCI_ABORT_INT 0x04000000 -+ -+#define AR2315_PCI_INT_MASK (AR2315_PCI + 0x0504) /* same as INT_STATUS */ -+ -+#define AR2315_PCI_INTEN_REG (AR2315_PCI + 0x0508) -+#define AR2315_PCI_INT_DISABLE 0x00 /* disable pci interrupts */ -+#define AR2315_PCI_INT_ENABLE 0x01 /* enable pci interrupts */ -+ -+#define AR2315_PCI_HOST_IN_EN (AR2315_PCI + 0x0800) -+#define AR2315_PCI_HOST_IN_DIS (AR2315_PCI + 0x0804) -+#define AR2315_PCI_HOST_IN_PTR (AR2315_PCI + 0x0810) -+#define AR2315_PCI_HOST_OUT_EN (AR2315_PCI + 0x0900) -+#define AR2315_PCI_HOST_OUT_DIS (AR2315_PCI + 0x0904) -+#define AR2315_PCI_HOST_OUT_PTR (AR2315_PCI + 0x0908) -+ -+ -+/* -+ * Local Bus Interface Registers -+ */ -+#define AR2315_LB_CONFIG (AR2315_LOCAL + 0x0000) -+#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */ -+#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */ -+#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */ -+#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */ -+#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */ -+#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */ -+#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */ -+#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */ -+#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */ -+#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */ -+#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */ -+#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */ -+#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */ -+#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */ -+#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */ -+#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */ -+#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */ -+#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */ -+#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */ -+#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */ -+#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */ -+#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */ -+#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */ -+#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */ -+#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */ -+ -+#define AR2315_LB_CLKSEL (AR2315_LOCAL + 0x0004) -+#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */ -+ -+#define AR2315_LB_1MS (AR2315_LOCAL + 0x0008) -+#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */ -+ -+#define AR2315_LB_MISCCFG (AR2315_LOCAL + 0x000C) -+#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */ -+#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */ -+#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */ -+#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */ -+#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */ -+#define AR2315_LBM_TIMEOUT_MASK 0x00FFFF80 -+#define AR2315_LBM_TIMEOUT_SHFT 7 -+#define AR2315_LBM_PORTMUX 0x07000000 -+ -+ -+#define AR2315_LB_RXTSOFF (AR2315_LOCAL + 0x0010) -+ -+#define AR2315_LB_TX_CHAIN_EN (AR2315_LOCAL + 0x0100) -+#define AR2315_LB_TXEN_0 0x01 -+#define AR2315_LB_TXEN_1 0x02 -+#define AR2315_LB_TXEN_2 0x04 -+#define AR2315_LB_TXEN_3 0x08 -+ -+#define AR2315_LB_TX_CHAIN_DIS (AR2315_LOCAL + 0x0104) -+#define AR2315_LB_TX_DESC_PTR (AR2315_LOCAL + 0x0200) -+ -+#define AR2315_LB_RX_CHAIN_EN (AR2315_LOCAL + 0x0400) -+#define AR2315_LB_RXEN 0x01 -+ -+#define AR2315_LB_RX_CHAIN_DIS (AR2315_LOCAL + 0x0404) -+#define AR2315_LB_RX_DESC_PTR (AR2315_LOCAL + 0x0408) -+ -+#define AR2315_LB_INT_STATUS (AR2315_LOCAL + 0x0500) -+#define AR2315_INT_TX_DESC 0x0001 -+#define AR2315_INT_TX_OK 0x0002 -+#define AR2315_INT_TX_ERR 0x0004 -+#define AR2315_INT_TX_EOF 0x0008 -+#define AR2315_INT_RX_DESC 0x0010 -+#define AR2315_INT_RX_OK 0x0020 -+#define AR2315_INT_RX_ERR 0x0040 -+#define AR2315_INT_RX_EOF 0x0080 -+#define AR2315_INT_TX_TRUNC 0x0100 -+#define AR2315_INT_TX_STARVE 0x0200 -+#define AR2315_INT_LB_TIMEOUT 0x0400 -+#define AR2315_INT_LB_ERR 0x0800 -+#define AR2315_INT_MBOX_WR 0x1000 -+#define AR2315_INT_MBOX_RD 0x2000 -+ -+/* Bit definitions for INT MASK are the same as INT_STATUS */ -+#define AR2315_LB_INT_MASK (AR2315_LOCAL + 0x0504) -+ -+#define AR2315_LB_INT_EN (AR2315_LOCAL + 0x0508) -+#define AR2315_LB_MBOX (AR2315_LOCAL + 0x0600) -+ -+/* -+ * IR Interface Registers -+ */ -+#define AR2315_IR_PKTDATA (AR2315_IR + 0x0000) -+ -+#define AR2315_IR_PKTLEN (AR2315_IR + 0x07fc) /* 0 - 63 */ -+ -+#define AR2315_IR_CONTROL (AR2315_IR + 0x0800) -+#define AR2315_IRCTL_TX 0x00000000 /* use as tranmitter */ -+#define AR2315_IRCTL_RX 0x00000001 /* use as receiver */ -+#define AR2315_IRCTL_SAMPLECLK_MASK 0x00003ffe /* Sample clk divisor mask */ -+#define AR2315_IRCTL_SAMPLECLK_SHFT 1 -+#define AR2315_IRCTL_OUTPUTCLK_MASK 0x03ffc000 /* Output clk divisor mask */ -+#define AR2315_IRCTL_OUTPUTCLK_SHFT 14 -+ -+#define AR2315_IR_STATUS (AR2315_IR + 0x0804) -+#define AR2315_IRSTS_RX 0x00000001 /* receive in progress */ -+#define AR2315_IRSTS_TX 0x00000002 /* transmit in progress */ -+ -+#define AR2315_IR_CONFIG (AR2315_IR + 0x0808) -+#define AR2315_IRCFG_INVIN 0x00000001 /* invert input polarity */ -+#define AR2315_IRCFG_INVOUT 0x00000002 /* invert output polarity */ -+#define AR2315_IRCFG_SEQ_START_WIN_SEL 0x00000004 /* 1 => 28, 0 => 7 */ -+#define AR2315_IRCFG_SEQ_START_THRESH 0x000000f0 /* */ -+#define AR2315_IRCFG_SEQ_END_UNIT_SEL 0x00000100 /* */ -+#define AR2315_IRCFG_SEQ_END_UNIT_THRESH 0x00007e00 /* */ -+#define AR2315_IRCFG_SEQ_END_WIN_SEL 0x00008000 /* */ -+#define AR2315_IRCFG_SEQ_END_WIN_THRESH 0x001f0000 /* */ -+#define AR2315_IRCFG_NUM_BACKOFF_WORDS 0x01e00000 /* */ -+ -+#define HOST_PCI_DEV_ID 3 -+#define HOST_PCI_MBAR0 0x10000000 -+#define HOST_PCI_MBAR1 0x20000000 -+#define HOST_PCI_MBAR2 0x30000000 -+ -+#define HOST_PCI_SDRAM_BASEADDR HOST_PCI_MBAR1 -+#define PCI_DEVICE_MEM_SPACE 0x800000 -+ -+#endif /* __AR2315_REG_H */ -diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar2315_spiflash.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar2315_spiflash.h ---- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar2315_spiflash.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar2315_spiflash.h 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,116 @@ -+/* -+ * SPI Flash Memory support header file. -+ * -+ * Copyright (c) 2005, Atheros Communications Inc. -+ * Copyright (C) 2006 FON Technology, SL. -+ * Copyright (C) 2006 Imre Kaloz -+ * Copyright (C) 2006-2009 Felix Fietkau -+ * -+ * This code is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ */ -+#ifndef __AR2315_SPIFLASH_H -+#define __AR2315_SPIFLASH_H -+ -+#define STM_PAGE_SIZE 256 -+ -+#define SFI_WRITE_BUFFER_SIZE 4 -+#define SFI_FLASH_ADDR_MASK 0x00ffffff -+ -+#define STM_8MBIT_SIGNATURE 0x13 -+#define STM_M25P80_BYTE_COUNT 1048576 -+#define STM_M25P80_SECTOR_COUNT 16 -+#define STM_M25P80_SECTOR_SIZE 0x10000 -+ -+#define STM_16MBIT_SIGNATURE 0x14 -+#define STM_M25P16_BYTE_COUNT 2097152 -+#define STM_M25P16_SECTOR_COUNT 32 -+#define STM_M25P16_SECTOR_SIZE 0x10000 -+ -+#define STM_32MBIT_SIGNATURE 0x15 -+#define STM_M25P32_BYTE_COUNT 4194304 -+#define STM_M25P32_SECTOR_COUNT 64 -+#define STM_M25P32_SECTOR_SIZE 0x10000 -+ -+#define STM_64MBIT_SIGNATURE 0x16 -+#define STM_M25P64_BYTE_COUNT 8388608 -+#define STM_M25P64_SECTOR_COUNT 128 -+#define STM_M25P64_SECTOR_SIZE 0x10000 -+ -+#define STM_128MBIT_SIGNATURE 0x17 -+#define STM_M25P128_BYTE_COUNT 16777216 -+#define STM_M25P128_SECTOR_COUNT 256 -+#define STM_M25P128_SECTOR_SIZE 0x10000 -+ -+#define STM_1MB_BYTE_COUNT STM_M25P80_BYTE_COUNT -+#define STM_1MB_SECTOR_COUNT STM_M25P80_SECTOR_COUNT -+#define STM_1MB_SECTOR_SIZE STM_M25P80_SECTOR_SIZE -+#define STM_2MB_BYTE_COUNT STM_M25P16_BYTE_COUNT -+#define STM_2MB_SECTOR_COUNT STM_M25P16_SECTOR_COUNT -+#define STM_2MB_SECTOR_SIZE STM_M25P16_SECTOR_SIZE -+#define STM_4MB_BYTE_COUNT STM_M25P32_BYTE_COUNT -+#define STM_4MB_SECTOR_COUNT STM_M25P32_SECTOR_COUNT -+#define STM_4MB_SECTOR_SIZE STM_M25P32_SECTOR_SIZE -+#define STM_8MB_BYTE_COUNT STM_M25P64_BYTE_COUNT -+#define STM_8MB_SECTOR_COUNT STM_M25P64_SECTOR_COUNT -+#define STM_8MB_SECTOR_SIZE STM_M25P64_SECTOR_SIZE -+#define STM_16MB_BYTE_COUNT STM_M25P128_BYTE_COUNT -+#define STM_16MB_SECTOR_COUNT STM_M25P128_SECTOR_COUNT -+#define STM_16MB_SECTOR_SIZE STM_M25P128_SECTOR_SIZE -+ -+/* -+ * ST Microelectronics Opcodes for Serial Flash -+ */ -+ -+#define STM_OP_WR_ENABLE 0x06 /* Write Enable */ -+#define STM_OP_WR_DISABLE 0x04 /* Write Disable */ -+#define STM_OP_RD_STATUS 0x05 /* Read Status */ -+#define STM_OP_WR_STATUS 0x01 /* Write Status */ -+#define STM_OP_RD_DATA 0x03 /* Read Data */ -+#define STM_OP_FAST_RD_DATA 0x0b /* Fast Read Data */ -+#define STM_OP_PAGE_PGRM 0x02 /* Page Program */ -+#define STM_OP_SECTOR_ERASE 0xd8 /* Sector Erase */ -+#define STM_OP_BULK_ERASE 0xc7 /* Bulk Erase */ -+#define STM_OP_DEEP_PWRDOWN 0xb9 /* Deep Power-Down Mode */ -+#define STM_OP_RD_SIG 0xab /* Read Electronic Signature */ -+ -+#define STM_STATUS_WIP 0x01 /* Write-In-Progress */ -+#define STM_STATUS_WEL 0x02 /* Write Enable Latch */ -+#define STM_STATUS_BP0 0x04 /* Block Protect 0 */ -+#define STM_STATUS_BP1 0x08 /* Block Protect 1 */ -+#define STM_STATUS_BP2 0x10 /* Block Protect 2 */ -+#define STM_STATUS_SRWD 0x80 /* Status Register Write Disable */ -+ -+/* -+ * SPI Flash Interface Registers -+ */ -+#define AR531XPLUS_SPI_READ 0x08000000 -+#define AR531XPLUS_SPI_MMR 0x11300000 -+#define AR531XPLUS_SPI_MMR_SIZE 12 -+ -+#define AR531XPLUS_SPI_CTL 0x00 -+#define AR531XPLUS_SPI_OPCODE 0x04 -+#define AR531XPLUS_SPI_DATA 0x08 -+ -+#define SPI_FLASH_READ AR531XPLUS_SPI_READ -+#define SPI_FLASH_MMR AR531XPLUS_SPI_MMR -+#define SPI_FLASH_MMR_SIZE AR531XPLUS_SPI_MMR_SIZE -+#define SPI_FLASH_CTL AR531XPLUS_SPI_CTL -+#define SPI_FLASH_OPCODE AR531XPLUS_SPI_OPCODE -+#define SPI_FLASH_DATA AR531XPLUS_SPI_DATA -+ -+#define SPI_CTL_START 0x00000100 -+#define SPI_CTL_BUSY 0x00010000 -+#define SPI_CTL_TXCNT_MASK 0x0000000f -+#define SPI_CTL_RXCNT_MASK 0x000000f0 -+#define SPI_CTL_TX_RX_CNT_MASK 0x000000ff -+#define SPI_CTL_SIZE_MASK 0x00060000 -+ -+#define SPI_CTL_CLK_SEL_MASK 0x03000000 -+#define SPI_OPCODE_MASK 0x000000ff -+ -+#define SPI_STATUS_WIP STM_STATUS_WIP -+ -+#endif -diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar231x.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar231x.h ---- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar231x.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar231x.h 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,54 @@ -+#ifndef __AR531X_H -+#define __AR531X_H -+ -+#define AR531X_MISC_IRQ_BASE 0x20 -+#define AR531X_GPIO_IRQ_BASE 0x30 -+ -+/* Software's idea of interrupts handled by "CPU Interrupt Controller" */ -+#define AR531X_IRQ_NONE MIPS_CPU_IRQ_BASE+0 -+#define AR531X_IRQ_CPU_CLOCK MIPS_CPU_IRQ_BASE+7 /* C0_CAUSE: 0x8000 */ -+ -+/* Miscellaneous interrupts, which share IP6 */ -+#define AR531X_MISC_IRQ_NONE AR531X_MISC_IRQ_BASE+0 -+#define AR531X_MISC_IRQ_TIMER AR531X_MISC_IRQ_BASE+1 -+#define AR531X_MISC_IRQ_AHB_PROC AR531X_MISC_IRQ_BASE+2 -+#define AR531X_MISC_IRQ_AHB_DMA AR531X_MISC_IRQ_BASE+3 -+#define AR531X_MISC_IRQ_GPIO AR531X_MISC_IRQ_BASE+4 -+#define AR531X_MISC_IRQ_UART0 AR531X_MISC_IRQ_BASE+5 -+#define AR531X_MISC_IRQ_UART0_DMA AR531X_MISC_IRQ_BASE+6 -+#define AR531X_MISC_IRQ_WATCHDOG AR531X_MISC_IRQ_BASE+7 -+#define AR531X_MISC_IRQ_LOCAL AR531X_MISC_IRQ_BASE+8 -+#define AR531X_MISC_IRQ_SPI AR531X_MISC_IRQ_BASE+9 -+#define AR531X_MISC_IRQ_COUNT 10 -+ -+/* GPIO Interrupts [0..7], share AR531X_MISC_IRQ_GPIO */ -+#define AR531X_GPIO_IRQ_NONE AR531X_GPIO_IRQ_BASE+0 -+#define AR531X_GPIO_IRQ(n) AR531X_GPIO_IRQ_BASE+n -+#define AR531X_GPIO_IRQ_COUNT 22 -+ -+static inline u32 -+ar231x_read_reg(u32 reg) -+{ -+ return __raw_readl((u32 *) KSEG1ADDR(reg)); -+} -+ -+static inline void -+ar231x_write_reg(u32 reg, u32 val) -+{ -+ __raw_writel(val, (u32 *) KSEG1ADDR(reg)); -+} -+ -+static inline u32 -+ar231x_mask_reg(u32 reg, u32 mask, u32 val) -+{ -+ u32 ret; -+ -+ ret = ar231x_read_reg(reg); -+ ret &= ~mask; -+ ret |= val; -+ ar231x_write_reg(reg, ret); -+ -+ return ret; -+} -+ -+#endif -diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar231x_platform.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar231x_platform.h ---- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar231x_platform.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar231x_platform.h 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,83 @@ -+#ifndef __AR531X_PLATFORM_H -+#define __AR531X_PLATFORM_H -+ -+/* -+ * This is board-specific data that is stored in a "fixed" location in flash. -+ * It is shared across operating systems, so it should not be changed lightly. -+ * The main reason we need it is in order to extract the ethernet MAC -+ * address(es). -+ */ -+struct ar231x_boarddata { -+ u32 magic; /* board data is valid */ -+#define AR531X_BD_MAGIC 0x35333131 /* "5311", for all 531x platforms */ -+ u16 cksum; /* checksum (starting with BD_REV 2) */ -+ u16 rev; /* revision of this struct */ -+#define BD_REV 4 -+ char boardName[64]; /* Name of board */ -+ u16 major; /* Board major number */ -+ u16 minor; /* Board minor number */ -+ u32 flags; /* Board configuration */ -+#define BD_ENET0 0x00000001 /* ENET0 is stuffed */ -+#define BD_ENET1 0x00000002 /* ENET1 is stuffed */ -+#define BD_UART1 0x00000004 /* UART1 is stuffed */ -+#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */ -+#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */ -+#define BD_SYSLED 0x00000020 /* System LED stuffed */ -+#define BD_EXTUARTCLK 0x00000040 /* External UART clock */ -+#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */ -+#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */ -+#define BD_WLAN0 0x00000200 /* Enable WLAN0 */ -+#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ memCap for testing */ -+#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */ -+#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */ -+#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */ -+#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */ -+#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */ -+#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */ -+#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */ -+ u16 resetConfigGpio; /* Reset factory GPIO pin */ -+ u16 sysLedGpio; /* System LED GPIO pin */ -+ -+ u32 cpuFreq; /* CPU core frequency in Hz */ -+ u32 sysFreq; /* System frequency in Hz */ -+ u32 cntFreq; /* Calculated C0_COUNT frequency */ -+ -+ u8 wlan0_mac[6]; -+ u8 enet0_mac[6]; -+ u8 enet1_mac[6]; -+ -+ u16 pciId; /* Pseudo PCIID for common code */ -+ u16 memCap; /* cap bank1 in MB */ -+ -+ /* version 3 */ -+ u8 wlan1_mac[6]; /* (ar5212) */ -+}; -+ -+#define BOARD_CONFIG_BUFSZ 0x1000 -+ -+/* -+ * Platform device information for the Wireless MAC -+ */ -+struct ar231x_board_config { -+ u16 devid; -+ -+ /* board config data */ -+ struct ar231x_boarddata *config; -+ -+ /* radio calibration data */ -+ const char *radio; -+}; -+ -+/* -+ * Platform device information for the Ethernet MAC -+ */ -+struct ar231x_eth { -+ u32 reset_base; -+ u32 reset_mac; -+ u32 reset_phy; -+ u32 phy_base; -+ struct ar231x_board_config *config; -+ char *macaddr; -+}; -+ -+#endif /* __AR531X_PLATFORM_H */ -diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar5312_regs.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar5312_regs.h ---- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar5312_regs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar5312_regs.h 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,236 @@ -+/* -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. -+ * Copyright (C) 2006 Imre Kaloz -+ * Copyright (C) 2006 Felix Fietkau -+ */ -+ -+#ifndef AR5312_H -+#define AR5312_H -+ -+#include -+ -+/* -+ * IRQs -+ */ -+ -+#define AR5312_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */ -+#define AR5312_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */ -+#define AR5312_IRQ_ENET1_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */ -+#define AR5312_IRQ_WLAN1_INTRS MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */ -+#define AR5312_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */ -+ -+ -+/* Address Map */ -+#define AR531X_WLAN0 0x18000000 -+#define AR531X_WLAN1 0x18500000 -+#define AR531X_ENET0 0x18100000 -+#define AR531X_ENET1 0x18200000 -+#define AR531X_SDRAMCTL 0x18300000 -+#define AR531X_FLASHCTL 0x18400000 -+#define AR531X_APBBASE 0x1c000000 -+#define AR531X_FLASH 0x1e000000 -+#define AR531X_UART0 0xbc000003 /* UART MMR */ -+ -+/* -+ * AR531X_NUM_ENET_MAC defines the number of ethernet MACs that -+ * should be considered available. The AR5312 supports 2 enet MACS, -+ * even though many reference boards only actually use 1 of them -+ * (i.e. Only MAC 0 is actually connected to an enet PHY or PHY switch. -+ * The AR2312 supports 1 enet MAC. -+ */ -+#define AR531X_NUM_ENET_MAC 2 -+ -+/* -+ * Need these defines to determine true number of ethernet MACs -+ */ -+#define AR5212_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */ -+#define AR5212_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */ -+#define AR5212_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */ -+#define AR531X_RADIO_MASK_OFF 0xc8 -+#define AR531X_RADIO0_MASK 0x0003 -+#define AR531X_RADIO1_MASK 0x000c -+#define AR531X_RADIO1_S 2 -+ -+/* -+ * AR531X_NUM_WMAC defines the number of Wireless MACs that\ -+ * should be considered available. -+ */ -+#define AR531X_NUM_WMAC 2 -+ -+/* Reset/Timer Block Address Map */ -+#define AR531X_RESETTMR (AR531X_APBBASE + 0x3000) -+#define AR531X_TIMER (AR531X_RESETTMR + 0x0000) /* countdown timer */ -+#define AR531X_WD_CTRL (AR531X_RESETTMR + 0x0008) /* watchdog cntrl */ -+#define AR531X_WD_TIMER (AR531X_RESETTMR + 0x000c) /* watchdog timer */ -+#define AR531X_ISR (AR531X_RESETTMR + 0x0010) /* Intr Status Reg */ -+#define AR531X_IMR (AR531X_RESETTMR + 0x0014) /* Intr Mask Reg */ -+#define AR531X_RESET (AR531X_RESETTMR + 0x0020) -+#define AR5312_CLOCKCTL1 (AR531X_RESETTMR + 0x0064) -+#define AR5312_SCRATCH (AR531X_RESETTMR + 0x006c) -+#define AR531X_PROCADDR (AR531X_RESETTMR + 0x0070) -+#define AR531X_PROC1 (AR531X_RESETTMR + 0x0074) -+#define AR531X_DMAADDR (AR531X_RESETTMR + 0x0078) -+#define AR531X_DMA1 (AR531X_RESETTMR + 0x007c) -+#define AR531X_ENABLE (AR531X_RESETTMR + 0x0080) /* interface enb */ -+#define AR531X_REV (AR531X_RESETTMR + 0x0090) /* revision */ -+ -+/* AR531X_WD_CTRL register bit field definitions */ -+#define AR531X_WD_CTRL_IGNORE_EXPIRATION 0x0000 -+#define AR531X_WD_CTRL_NMI 0x0001 -+#define AR531X_WD_CTRL_RESET 0x0002 -+ -+/* AR531X_ISR register bit field definitions */ -+#define AR531X_ISR_NONE 0x0000 -+#define AR531X_ISR_TIMER 0x0001 -+#define AR531X_ISR_AHBPROC 0x0002 -+#define AR531X_ISR_AHBDMA 0x0004 -+#define AR531X_ISR_GPIO 0x0008 -+#define AR531X_ISR_UART0 0x0010 -+#define AR531X_ISR_UART0DMA 0x0020 -+#define AR531X_ISR_WD 0x0040 -+#define AR531X_ISR_LOCAL 0x0080 -+ -+/* AR531X_RESET register bit field definitions */ -+#define AR531X_RESET_SYSTEM 0x00000001 /* cold reset full system */ -+#define AR531X_RESET_PROC 0x00000002 /* cold reset MIPS core */ -+#define AR531X_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */ -+#define AR531X_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */ -+#define AR531X_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */ -+#define AR531X_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */ -+#define AR531X_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */ -+#define AR531X_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */ -+#define AR531X_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */ -+#define AR531X_RESET_APB 0x00000400 /* cold reset APB (ar5312) */ -+#define AR531X_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */ -+#define AR531X_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */ -+#define AR531X_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */ -+#define AR531X_RESET_NMI 0x00010000 /* send an NMI to the processor */ -+#define AR531X_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */ -+#define AR531X_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */ -+#define AR531X_RESET_LOCAL_BUS 0x00080000 /* reset local bus */ -+#define AR531X_RESET_WDOG 0x00100000 /* last reset was a watchdog */ -+ -+#define AR531X_RESET_WMAC0_BITS \ -+ AR531X_RESET_WLAN0 |\ -+ AR531X_RESET_WARM_WLAN0_MAC |\ -+ AR531X_RESET_WARM_WLAN0_BB -+ -+#define AR531X_RESERT_WMAC1_BITS \ -+ AR531X_RESET_WLAN1 |\ -+ AR531X_RESET_WARM_WLAN1_MAC |\ -+ AR531X_RESET_WARM_WLAN1_BB -+ -+/* AR5312_CLOCKCTL1 register bit field definitions */ -+#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030 -+#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4 -+#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00 -+#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8 -+#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000 -+ -+/* Valid for AR5312 and AR2312 */ -+#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030 -+#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4 -+#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00 -+#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8 -+#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000 -+ -+/* Valid for AR2313 */ -+#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000 -+#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12 -+#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000 -+#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16 -+#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000 -+ -+ -+/* AR531X_ENABLE register bit field definitions */ -+#define AR531X_ENABLE_WLAN0 0x0001 -+#define AR531X_ENABLE_ENET0 0x0002 -+#define AR531X_ENABLE_ENET1 0x0004 -+#define AR531X_ENABLE_UART_AND_WLAN1_PIO 0x0008 /* UART, and WLAN1 PIOs */ -+#define AR531X_ENABLE_WLAN1_DMA 0x0010 /* WLAN1 DMAs */ -+#define AR531X_ENABLE_WLAN1 \ -+ (AR531X_ENABLE_UART_AND_WLAN1_PIO | AR531X_ENABLE_WLAN1_DMA) -+ -+/* AR531X_REV register bit field definitions */ -+#define AR531X_REV_WMAC_MAJ 0xf000 -+#define AR531X_REV_WMAC_MAJ_S 12 -+#define AR531X_REV_WMAC_MIN 0x0f00 -+#define AR531X_REV_WMAC_MIN_S 8 -+#define AR531X_REV_MAJ 0x00f0 -+#define AR531X_REV_MAJ_S 4 -+#define AR531X_REV_MIN 0x000f -+#define AR531X_REV_MIN_S 0 -+#define AR531X_REV_CHIP (AR531X_REV_MAJ|AR531X_REV_MIN) -+ -+/* Major revision numbers, bits 7..4 of Revision ID register */ -+#define AR531X_REV_MAJ_AR5312 0x4 -+#define AR531X_REV_MAJ_AR2313 0x5 -+ -+/* Minor revision numbers, bits 3..0 of Revision ID register */ -+#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */ -+#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */ -+ -+/* AR531X_FLASHCTL register bit field definitions */ -+#define FLASHCTL_IDCY 0x0000000f /* Idle cycle turn around time */ -+#define FLASHCTL_IDCY_S 0 -+#define FLASHCTL_WST1 0x000003e0 /* Wait state 1 */ -+#define FLASHCTL_WST1_S 5 -+#define FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */ -+#define FLASHCTL_WST2 0x0000f800 /* Wait state 2 */ -+#define FLASHCTL_WST2_S 11 -+#define FLASHCTL_AC 0x00070000 /* Flash address check (added) */ -+#define FLASHCTL_AC_S 16 -+#define FLASHCTL_AC_128K 0x00000000 -+#define FLASHCTL_AC_256K 0x00010000 -+#define FLASHCTL_AC_512K 0x00020000 -+#define FLASHCTL_AC_1M 0x00030000 -+#define FLASHCTL_AC_2M 0x00040000 -+#define FLASHCTL_AC_4M 0x00050000 -+#define FLASHCTL_AC_8M 0x00060000 -+#define FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */ -+#define FLASHCTL_E 0x00080000 /* Flash bank enable (added) */ -+#define FLASHCTL_BUSERR 0x01000000 /* Bus transfer error status flag */ -+#define FLASHCTL_WPERR 0x02000000 /* Write protect error status flag */ -+#define FLASHCTL_WP 0x04000000 /* Write protect */ -+#define FLASHCTL_BM 0x08000000 /* Burst mode */ -+#define FLASHCTL_MW 0x30000000 /* Memory width */ -+#define FLASHCTL_MWx8 0x00000000 /* Memory width x8 */ -+#define FLASHCTL_MWx16 0x10000000 /* Memory width x16 */ -+#define FLASHCTL_MWx32 0x20000000 /* Memory width x32 (not supported) */ -+#define FLASHCTL_ATNR 0x00000000 /* Access type == no retry */ -+#define FLASHCTL_ATR 0x80000000 /* Access type == retry every */ -+#define FLASHCTL_ATR4 0xc0000000 /* Access type == retry every 4 */ -+ -+/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */ -+#define AR531X_FLASHCTL0 (AR531X_FLASHCTL + 0x00) -+#define AR531X_FLASHCTL1 (AR531X_FLASHCTL + 0x04) -+#define AR531X_FLASHCTL2 (AR531X_FLASHCTL + 0x08) -+ -+/* ARM SDRAM Controller -- just enough to determine memory size */ -+#define AR531X_MEM_CFG1 (AR531X_SDRAMCTL + 0x04) -+#define MEM_CFG1_AC0 0x00000700 /* bank 0: SDRAM addr check (added) */ -+#define MEM_CFG1_AC0_S 8 -+#define MEM_CFG1_AC1 0x00007000 /* bank 1: SDRAM addr check (added) */ -+#define MEM_CFG1_AC1_S 12 -+ -+/* GPIO Address Map */ -+#define AR531X_GPIO (AR531X_APBBASE + 0x2000) -+#define AR531X_GPIO_DO (AR531X_GPIO + 0x00) /* output register */ -+#define AR531X_GPIO_DI (AR531X_GPIO + 0x04) /* intput register */ -+#define AR531X_GPIO_CR (AR531X_GPIO + 0x08) /* control register */ -+ -+/* GPIO Control Register bit field definitions */ -+#define AR531X_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */ -+#define AR531X_GPIO_CR_O(x) (0 << (x)) /* mask for output */ -+#define AR531X_GPIO_CR_I(x) (1 << (x)) /* mask for input */ -+#define AR531X_GPIO_CR_INT(x) (1 << ((x)+8)) /* mask for interrupt */ -+#define AR531X_GPIO_CR_UART(x) (1 << ((x)+16)) /* uart multiplex */ -+#define AR531X_NUM_GPIO 8 -+ -+ -+#endif -+ -diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h ---- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,84 @@ -+/* -+ * Atheros SoC specific CPU feature overrides -+ * -+ * Copyright (C) 2008 Gabor Juhos -+ * -+ * This file was derived from: include/asm-mips/cpu-features.h -+ * Copyright (C) 2003, 2004 Ralf Baechle -+ * Copyright (C) 2004 Maciej W. Rozycki -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ */ -+#ifndef __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H -+#define __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H -+ -+/* -+ * The ATHEROS SoCs have MIPS 4Kc/4KEc core. -+ */ -+#define cpu_has_tlb 1 -+#define cpu_has_4kex 1 -+#define cpu_has_3k_cache 0 -+#define cpu_has_4k_cache 1 -+#define cpu_has_tx39_cache 0 -+#define cpu_has_sb1_cache 0 -+#define cpu_has_fpu 0 -+#define cpu_has_32fpr 0 -+#define cpu_has_counter 1 -+/* #define cpu_has_watch ? */ -+/* #define cpu_has_divec ? */ -+/* #define cpu_has_vce ? */ -+/* #define cpu_has_cache_cdex_p ? */ -+/* #define cpu_has_cache_cdex_s ? */ -+/* #define cpu_has_prefetch ? */ -+/* #define cpu_has_mcheck ? */ -+#define cpu_has_ejtag 1 -+ -+#if !defined(CONFIG_ATHEROS_AR5312) -+# define cpu_has_llsc 1 -+#else -+/* -+ * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the -+ * ll/sc instructions. -+ */ -+# define cpu_has_llsc 0 -+#endif -+ -+#define cpu_has_mips16 0 -+#define cpu_has_mdmx 0 -+#define cpu_has_mips3d 0 -+#define cpu_has_smartmips 0 -+ -+/* #define cpu_has_vtag_icache ? */ -+/* #define cpu_has_dc_aliases ? */ -+/* #define cpu_has_ic_fills_f_dc ? */ -+/* #define cpu_has_pindexed_dcache ? */ -+ -+/* #define cpu_icache_snoops_remote_store ? */ -+ -+#define cpu_has_mips32r1 1 -+ -+#if !defined(CONFIG_ATHEROS_AR5312) -+# define cpu_has_mips32r2 1 -+#endif -+ -+#define cpu_has_mips64r1 0 -+#define cpu_has_mips64r2 0 -+ -+#define cpu_has_dsp 0 -+#define cpu_has_mipsmt 0 -+ -+/* #define cpu_has_nofpuex ? */ -+#define cpu_has_64bits 0 -+#define cpu_has_64bit_zero_reg 0 -+#define cpu_has_64bit_gp_regs 0 -+#define cpu_has_64bit_addresses 0 -+ -+/* #define cpu_has_inclusive_pcaches ? */ -+ -+/* #define cpu_dcache_line_size() ? */ -+/* #define cpu_icache_line_size() ? */ -+ -+#endif /* __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H */ -diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/dma-coherence.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/dma-coherence.h ---- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/dma-coherence.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/dma-coherence.h 2011-05-15 21:41:19.000000000 +0200 -@@ -0,0 +1,76 @@ -+/* -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 2006 Ralf Baechle -+ * Copyright (C) 2007 Felix Fietkau -+ * -+ */ -+#ifndef __ASM_MACH_GENERIC_DMA_COHERENCE_H -+#define __ASM_MACH_GENERIC_DMA_COHERENCE_H -+ -+#define PCI_DMA_OFFSET 0x20000000 -+ -+#include -+ -+static inline dma_addr_t ar231x_dev_offset(struct device *dev) -+{ -+#ifdef CONFIG_PCI -+ extern struct bus_type pci_bus_type; -+ -+ if (dev && dev->bus == &pci_bus_type) -+ return PCI_DMA_OFFSET; -+ else -+#endif -+ return 0; -+} -+ -+static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size) -+{ -+ return virt_to_phys(addr) + ar231x_dev_offset(dev); -+} -+ -+static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page) -+{ -+ return page_to_phys(page) + ar231x_dev_offset(dev); -+} -+ -+static inline unsigned long plat_dma_addr_to_phys(struct device *dev, -+ dma_addr_t dma_addr) -+{ -+ return dma_addr - ar231x_dev_offset(dev); -+} -+ -+static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, -+ size_t size, enum dma_data_direction direction) -+{ -+} -+ -+static inline int plat_dma_supported(struct device *dev, u64 mask) -+{ -+ return 1; -+} -+ -+static inline void plat_extra_sync_for_device(struct device *dev) -+{ -+ return; -+} -+ -+static inline int plat_dma_mapping_error(struct device *dev, -+ dma_addr_t dma_addr) -+{ -+ return 0; -+} -+ -+static inline int plat_device_is_coherent(struct device *dev) -+{ -+#ifdef CONFIG_DMA_COHERENT -+ return 1; -+#endif -+#ifdef CONFIG_DMA_NONCOHERENT -+ return 0; -+#endif -+} -+ -+#endif /* __ASM_MACH_GENERIC_DMA_COHERENCE_H */ -diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/gpio.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/gpio.h ---- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/gpio.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/gpio.h 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,84 @@ -+#ifndef _ATHEROS_GPIO_H_ -+#define _ATHEROS_GPIO_H_ -+ -+#include -+ -+struct ar231x_gpiodev { -+ u32 valid_mask; -+ u32 (*get_output)(void); -+ u32 (*set_output)(u32 mask, u32 val); -+ u32 (*get)(void); -+ u32 (*set)(u32 mask, u32 val); -+}; -+ -+extern const struct ar231x_gpiodev *ar231x_gpiodev; -+ -+/* -+ * Wrappers for the generic GPIO layer -+ */ -+ -+static inline int gpio_direction_input(unsigned gpio) { -+ u32 mask = 1 << gpio; -+ -+ if (!(ar231x_gpiodev->valid_mask & mask)) -+ return -ENXIO; -+ -+ ar231x_gpiodev->set_output(mask, 0); -+ return 0; -+} -+ -+static inline void gpio_set_value(unsigned gpio, int value) { -+ u32 mask = 1 << gpio; -+ -+ if (!(ar231x_gpiodev->valid_mask & mask)) -+ return; -+ -+ ar231x_gpiodev->set(mask, (!!value) * mask); -+} -+ -+static inline int gpio_direction_output(unsigned gpio, int value) { -+ u32 mask = 1 << gpio; -+ -+ if (!(ar231x_gpiodev->valid_mask & mask)) -+ return -ENXIO; -+ -+ ar231x_gpiodev->set_output(mask, mask); -+ ar231x_gpiodev->set(mask, (!!value) * mask); -+ return 0; -+} -+ -+/* Reads the gpio pin. Unchecked function */ -+static inline int gpio_get_value(unsigned gpio) { -+ u32 mask = 1 << gpio; -+ -+ if (!(ar231x_gpiodev->valid_mask & mask)) -+ return 0; -+ -+ return !!(ar231x_gpiodev->get() & mask); -+} -+ -+static inline int gpio_request(unsigned gpio, const char *label) { -+ return 0; -+} -+ -+static inline void gpio_free(unsigned gpio) { -+} -+ -+/* Returns IRQ to attach for gpio. Unchecked function */ -+static inline int gpio_to_irq(unsigned gpio) { -+ return AR531X_GPIO_IRQ(gpio); -+} -+ -+/* Returns gpio for IRQ attached. Unchecked function */ -+static inline int irq_to_gpio(unsigned irq) { -+ return (irq - (AR531X_GPIO_IRQ(0))); -+} -+ -+static inline int gpio_set_debounce(unsigned gpio, unsigned debounce) -+{ -+ return -ENOSYS; -+} -+ -+#include /* cansleep wrappers */ -+ -+#endif -diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/reset.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/reset.h ---- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/reset.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/reset.h 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,6 @@ -+#ifndef __AR531X_RESET_H -+#define __AR531X_RESET_H -+ -+void ar531x_disable_reset_button(void); -+ -+#endif /* __AR531X_RESET_H */ -diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/war.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/war.h ---- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/war.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/war.h 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,25 @@ -+/* -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 2008 Felix Fietkau -+ */ -+#ifndef __ASM_MIPS_MACH_ATHEROS_WAR_H -+#define __ASM_MIPS_MACH_ATHEROS_WAR_H -+ -+#define R4600_V1_INDEX_ICACHEOP_WAR 0 -+#define R4600_V1_HIT_CACHEOP_WAR 0 -+#define R4600_V2_HIT_CACHEOP_WAR 0 -+#define R5432_CP0_INTERRUPT_WAR 0 -+#define BCM1250_M3_WAR 0 -+#define SIBYTE_1956_WAR 0 -+#define MIPS4K_ICACHE_REFILL_WAR 0 -+#define MIPS_CACHE_SYNC_WAR 0 -+#define TX49XX_ICACHE_INDEX_INV_WAR 0 -+#define RM9000_CDEX_SMP_WAR 0 -+#define ICACHE_REFILLS_WORKAROUND_WAR 0 -+#define R10000_LLSC_WAR 0 -+#define MIPS34K_MISSED_ITLB_WAR 0 -+ -+#endif /* __ASM_MIPS_MACH_ATHEROS_WAR_H */ -diff -Nur linux-2.6.39-rc7.orig/arch/mips/kernel/cevt-r4k.c linux-2.6.39-rc7/arch/mips/kernel/cevt-r4k.c ---- linux-2.6.39-rc7.orig/arch/mips/kernel/cevt-r4k.c 2011-05-10 04:33:54.000000000 +0200 -+++ linux-2.6.39-rc7/arch/mips/kernel/cevt-r4k.c 2011-05-15 21:34:57.000000000 +0200 -@@ -168,20 +168,23 @@ - struct clock_event_device *cd; - unsigned int irq; - -- if (!cpu_has_counter || !mips_hpt_frequency) -- return -ENXIO; -- -- if (!c0_compare_int_usable()) -- return -ENXIO; -- - /* - * With vectored interrupts things are getting platform specific. - * get_c0_compare_int is a hook to allow a platform to return the - * interrupt number of it's liking. - */ - irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; -- if (get_c0_compare_int) -+ if (get_c0_compare_int) { - irq = get_c0_compare_int(); -+ if ((irq >= MIPS_CPU_IRQ_BASE) && (irq < MIPS_CPU_IRQ_BASE + 8)) -+ cp0_compare_irq = irq - MIPS_CPU_IRQ_BASE; -+ } -+ -+ if (!cpu_has_counter || !mips_hpt_frequency) -+ return -ENXIO; -+ -+ if (!c0_compare_int_usable()) -+ return -ENXIO; - - cd = &per_cpu(mips_clockevent_device, cpu); - -diff -Nur linux-2.6.39-rc7.orig/drivers/mtd/devices/Kconfig linux-2.6.39-rc7/drivers/mtd/devices/Kconfig ---- linux-2.6.39-rc7.orig/drivers/mtd/devices/Kconfig 2011-05-10 04:33:54.000000000 +0200 -+++ linux-2.6.39-rc7/drivers/mtd/devices/Kconfig 2011-05-15 21:34:57.000000000 +0200 -@@ -112,6 +112,10 @@ - Set up your spi devices with the right board-specific platform data, - if you want to specify device partitioning. - -+config MTD_AR2315 -+ tristate "Atheros AR2315+ SPI Flash support" -+ depends on ATHEROS_AR2315 -+ - config MTD_SLRAM - tristate "Uncached system RAM" - help -diff -Nur linux-2.6.39-rc7.orig/drivers/mtd/devices/Makefile linux-2.6.39-rc7/drivers/mtd/devices/Makefile ---- linux-2.6.39-rc7.orig/drivers/mtd/devices/Makefile 2011-05-10 04:33:54.000000000 +0200 -+++ linux-2.6.39-rc7/drivers/mtd/devices/Makefile 2011-05-15 21:34:57.000000000 +0200 -@@ -17,3 +17,4 @@ - obj-$(CONFIG_MTD_DATAFLASH) += mtd_dataflash.o - obj-$(CONFIG_MTD_M25P80) += m25p80.o - obj-$(CONFIG_MTD_SST25L) += sst25l.o -+obj-$(CONFIG_MTD_AR2315) += ar2315.o -diff -Nur linux-2.6.39-rc7.orig/drivers/mtd/devices/ar2315.c linux-2.6.39-rc7/drivers/mtd/devices/ar2315.c ---- linux-2.6.39-rc7.orig/drivers/mtd/devices/ar2315.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/drivers/mtd/devices/ar2315.c 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,517 @@ -+ -+/* -+ * MTD driver for the SPI Flash Memory support on Atheros AR2315 -+ * -+ * Copyright (c) 2005-2006 Atheros Communications Inc. -+ * Copyright (C) 2006-2007 FON Technology, SL. -+ * Copyright (C) 2006-2007 Imre Kaloz -+ * Copyright (C) 2006-2009 Felix Fietkau -+ * -+ * This code is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+ -+#define SPIFLASH "spiflash: " -+#define busy_wait(_priv, _condition, _wait) do { \ -+ while (_condition) { \ -+ spin_unlock_bh(&_priv->lock); \ -+ if (_wait > 1) \ -+ msleep(_wait); \ -+ else if ((_wait == 1) && need_resched()) \ -+ schedule(); \ -+ else \ -+ udelay(1); \ -+ spin_lock_bh(&_priv->lock); \ -+ } \ -+} while (0) -+ -+enum { -+ FLASH_NONE, -+ FLASH_1MB, -+ FLASH_2MB, -+ FLASH_4MB, -+ FLASH_8MB, -+ FLASH_16MB, -+}; -+ -+/* Flash configuration table */ -+struct flashconfig { -+ u32 byte_cnt; -+ u32 sector_cnt; -+ u32 sector_size; -+}; -+ -+const struct flashconfig flashconfig_tbl[] = { -+ [FLASH_NONE] = { 0, 0, 0}, -+ [FLASH_1MB] = { STM_1MB_BYTE_COUNT, STM_1MB_SECTOR_COUNT, STM_1MB_SECTOR_SIZE}, -+ [FLASH_2MB] = { STM_2MB_BYTE_COUNT, STM_2MB_SECTOR_COUNT, STM_2MB_SECTOR_SIZE}, -+ [FLASH_4MB] = { STM_4MB_BYTE_COUNT, STM_4MB_SECTOR_COUNT, STM_4MB_SECTOR_SIZE}, -+ [FLASH_8MB] = { STM_8MB_BYTE_COUNT, STM_8MB_SECTOR_COUNT, STM_8MB_SECTOR_SIZE}, -+ [FLASH_16MB] = { STM_16MB_BYTE_COUNT, STM_16MB_SECTOR_COUNT, STM_16MB_SECTOR_SIZE} -+}; -+ -+/* Mapping of generic opcodes to STM serial flash opcodes */ -+enum { -+ SPI_WRITE_ENABLE, -+ SPI_WRITE_DISABLE, -+ SPI_RD_STATUS, -+ SPI_WR_STATUS, -+ SPI_RD_DATA, -+ SPI_FAST_RD_DATA, -+ SPI_PAGE_PROGRAM, -+ SPI_SECTOR_ERASE, -+ SPI_BULK_ERASE, -+ SPI_DEEP_PWRDOWN, -+ SPI_RD_SIG, -+}; -+ -+struct opcodes { -+ __u16 code; -+ __s8 tx_cnt; -+ __s8 rx_cnt; -+}; -+const struct opcodes stm_opcodes[] = { -+ [SPI_WRITE_ENABLE] = {STM_OP_WR_ENABLE, 1, 0}, -+ [SPI_WRITE_DISABLE] = {STM_OP_WR_DISABLE, 1, 0}, -+ [SPI_RD_STATUS] = {STM_OP_RD_STATUS, 1, 1}, -+ [SPI_WR_STATUS] = {STM_OP_WR_STATUS, 1, 0}, -+ [SPI_RD_DATA] = {STM_OP_RD_DATA, 4, 4}, -+ [SPI_FAST_RD_DATA] = {STM_OP_FAST_RD_DATA, 5, 0}, -+ [SPI_PAGE_PROGRAM] = {STM_OP_PAGE_PGRM, 8, 0}, -+ [SPI_SECTOR_ERASE] = {STM_OP_SECTOR_ERASE, 4, 0}, -+ [SPI_BULK_ERASE] = {STM_OP_BULK_ERASE, 1, 0}, -+ [SPI_DEEP_PWRDOWN] = {STM_OP_DEEP_PWRDOWN, 1, 0}, -+ [SPI_RD_SIG] = {STM_OP_RD_SIG, 4, 1}, -+}; -+ -+/* Driver private data structure */ -+struct spiflash_priv { -+ struct mtd_info mtd; -+ void *readaddr; /* memory mapped data for read */ -+ void *mmraddr; /* memory mapped register space */ -+ wait_queue_head_t wq; -+ spinlock_t lock; -+ int state; -+}; -+ -+#define to_spiflash(_mtd) container_of(_mtd, struct spiflash_priv, mtd) -+ -+enum { -+ FL_READY, -+ FL_READING, -+ FL_ERASING, -+ FL_WRITING -+}; -+ -+/***************************************************************************************************/ -+ -+static u32 -+spiflash_read_reg(struct spiflash_priv *priv, int reg) -+{ -+ return ar231x_read_reg((u32) priv->mmraddr + reg); -+} -+ -+static void -+spiflash_write_reg(struct spiflash_priv *priv, int reg, u32 data) -+{ -+ ar231x_write_reg((u32) priv->mmraddr + reg, data); -+} -+ -+static u32 -+spiflash_wait_busy(struct spiflash_priv *priv) -+{ -+ u32 reg; -+ -+ busy_wait(priv, (reg = spiflash_read_reg(priv, SPI_FLASH_CTL)) & -+ SPI_CTL_BUSY, 0); -+ return reg; -+} -+ -+static u32 -+spiflash_sendcmd (struct spiflash_priv *priv, int opcode, u32 addr) -+{ -+ const struct opcodes *op; -+ u32 reg, mask; -+ -+ op = &stm_opcodes[opcode]; -+ reg = spiflash_wait_busy(priv); -+ spiflash_write_reg(priv, SPI_FLASH_OPCODE, -+ ((u32) op->code) | (addr << 8)); -+ -+ reg &= ~SPI_CTL_TX_RX_CNT_MASK; -+ reg |= SPI_CTL_START | op->tx_cnt | (op->rx_cnt << 4); -+ -+ spiflash_write_reg(priv, SPI_FLASH_CTL, reg); -+ spiflash_wait_busy(priv); -+ -+ if (!op->rx_cnt) -+ return 0; -+ -+ reg = spiflash_read_reg(priv, SPI_FLASH_DATA); -+ -+ switch (op->rx_cnt) { -+ case 1: -+ mask = 0x000000ff; -+ break; -+ case 2: -+ mask = 0x0000ffff; -+ break; -+ case 3: -+ mask = 0x00ffffff; -+ break; -+ default: -+ mask = 0xffffffff; -+ break; -+ } -+ reg &= mask; -+ -+ return reg; -+} -+ -+ -+/* -+ * Probe SPI flash device -+ * Function returns 0 for failure. -+ * and flashconfig_tbl array index for success. -+ */ -+static int -+spiflash_probe_chip (struct spiflash_priv *priv) -+{ -+ u32 sig; -+ int flash_size; -+ -+ /* Read the signature on the flash device */ -+ spin_lock_bh(&priv->lock); -+ sig = spiflash_sendcmd(priv, SPI_RD_SIG, 0); -+ spin_unlock_bh(&priv->lock); -+ -+ switch (sig) { -+ case STM_8MBIT_SIGNATURE: -+ flash_size = FLASH_1MB; -+ break; -+ case STM_16MBIT_SIGNATURE: -+ flash_size = FLASH_2MB; -+ break; -+ case STM_32MBIT_SIGNATURE: -+ flash_size = FLASH_4MB; -+ break; -+ case STM_64MBIT_SIGNATURE: -+ flash_size = FLASH_8MB; -+ break; -+ case STM_128MBIT_SIGNATURE: -+ flash_size = FLASH_16MB; -+ break; -+ default: -+ printk (KERN_WARNING SPIFLASH "Read of flash device signature failed!\n"); -+ return 0; -+ } -+ -+ return flash_size; -+} -+ -+ -+/* wait until the flash chip is ready and grab a lock */ -+static int spiflash_wait_ready(struct spiflash_priv *priv, int state) -+{ -+ DECLARE_WAITQUEUE(wait, current); -+ -+retry: -+ spin_lock_bh(&priv->lock); -+ if (priv->state != FL_READY) { -+ set_current_state(TASK_UNINTERRUPTIBLE); -+ add_wait_queue(&priv->wq, &wait); -+ spin_unlock_bh(&priv->lock); -+ schedule(); -+ remove_wait_queue(&priv->wq, &wait); -+ -+ if(signal_pending(current)) -+ return 0; -+ -+ goto retry; -+ } -+ priv->state = state; -+ -+ return 1; -+} -+ -+static inline void spiflash_done(struct spiflash_priv *priv) -+{ -+ priv->state = FL_READY; -+ spin_unlock_bh(&priv->lock); -+ wake_up(&priv->wq); -+} -+ -+static void -+spiflash_wait_complete(struct spiflash_priv *priv, unsigned int timeout) -+{ -+ busy_wait(priv, spiflash_sendcmd(priv, SPI_RD_STATUS, 0) & -+ SPI_STATUS_WIP, timeout); -+ spiflash_done(priv); -+} -+ -+ -+ -+static int -+spiflash_erase (struct mtd_info *mtd, struct erase_info *instr) -+{ -+ struct spiflash_priv *priv = to_spiflash(mtd); -+ const struct opcodes *op; -+ u32 temp, reg; -+ -+ if (instr->addr + instr->len > mtd->size) -+ return -EINVAL; -+ -+ if (!spiflash_wait_ready(priv, FL_ERASING)) -+ return -EINTR; -+ -+ spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0); -+ reg = spiflash_wait_busy(priv); -+ -+ op = &stm_opcodes[SPI_SECTOR_ERASE]; -+ temp = ((u32)instr->addr << 8) | (u32)(op->code); -+ spiflash_write_reg(priv, SPI_FLASH_OPCODE, temp); -+ -+ reg &= ~SPI_CTL_TX_RX_CNT_MASK; -+ reg |= op->tx_cnt | SPI_CTL_START; -+ spiflash_write_reg(priv, SPI_FLASH_CTL, reg); -+ -+ spiflash_wait_complete(priv, 20); -+ -+ instr->state = MTD_ERASE_DONE; -+ mtd_erase_callback(instr); -+ -+ return 0; -+} -+ -+static int -+spiflash_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf) -+{ -+ struct spiflash_priv *priv = to_spiflash(mtd); -+ u8 *read_addr; -+ -+ if (!len) -+ return 0; -+ -+ if (from + len > mtd->size) -+ return -EINVAL; -+ -+ *retlen = len; -+ -+ if (!spiflash_wait_ready(priv, FL_READING)) -+ return -EINTR; -+ -+ read_addr = (u8 *)(priv->readaddr + from); -+ memcpy_fromio(buf, read_addr, len); -+ spiflash_done(priv); -+ -+ return 0; -+} -+ -+static int -+spiflash_write (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u8 *buf) -+{ -+ struct spiflash_priv *priv = to_spiflash(mtd); -+ u32 opcode, bytes_left; -+ -+ *retlen = 0; -+ -+ if (!len) -+ return 0; -+ -+ if (to + len > mtd->size) -+ return -EINVAL; -+ -+ bytes_left = len; -+ -+ do { -+ u32 read_len, reg, page_offset, spi_data = 0; -+ -+ read_len = min(bytes_left, sizeof(u32)); -+ -+ /* 32-bit writes cannot span across a page boundary -+ * (256 bytes). This types of writes require two page -+ * program operations to handle it correctly. The STM part -+ * will write the overflow data to the beginning of the -+ * current page as opposed to the subsequent page. -+ */ -+ page_offset = (to & (STM_PAGE_SIZE - 1)) + read_len; -+ -+ if (page_offset > STM_PAGE_SIZE) -+ read_len -= (page_offset - STM_PAGE_SIZE); -+ -+ if (!spiflash_wait_ready(priv, FL_WRITING)) -+ return -EINTR; -+ -+ spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0); -+ spi_data = 0; -+ switch (read_len) { -+ case 4: -+ spi_data |= buf[3] << 24; -+ /* fall through */ -+ case 3: -+ spi_data |= buf[2] << 16; -+ /* fall through */ -+ case 2: -+ spi_data |= buf[1] << 8; -+ /* fall through */ -+ case 1: -+ spi_data |= buf[0] & 0xff; -+ break; -+ default: -+ break; -+ } -+ -+ spiflash_write_reg(priv, SPI_FLASH_DATA, spi_data); -+ opcode = stm_opcodes[SPI_PAGE_PROGRAM].code | -+ (to & 0x00ffffff) << 8; -+ spiflash_write_reg(priv, SPI_FLASH_OPCODE, opcode); -+ -+ reg = spiflash_read_reg(priv, SPI_FLASH_CTL); -+ reg &= ~SPI_CTL_TX_RX_CNT_MASK; -+ reg |= (read_len + 4) | SPI_CTL_START; -+ spiflash_write_reg(priv, SPI_FLASH_CTL, reg); -+ -+ spiflash_wait_complete(priv, 1); -+ -+ bytes_left -= read_len; -+ to += read_len; -+ buf += read_len; -+ -+ *retlen += read_len; -+ } while (bytes_left != 0); -+ -+ return 0; -+} -+ -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static const char *part_probe_types[] = { "cmdlinepart", "RedBoot", "MyLoader", NULL }; -+#endif -+ -+ -+static int -+spiflash_probe(struct platform_device *pdev) -+{ -+ struct spiflash_priv *priv; -+ struct mtd_partition *parts; -+ struct mtd_info *mtd; -+ int index, num_parts; -+ int result = 0; -+ -+ priv = kzalloc(sizeof(struct spiflash_priv), GFP_KERNEL); -+ spin_lock_init(&priv->lock); -+ init_waitqueue_head(&priv->wq); -+ priv->state = FL_READY; -+ mtd = &priv->mtd; -+ -+ priv->mmraddr = ioremap_nocache(SPI_FLASH_MMR, SPI_FLASH_MMR_SIZE); -+ if (!priv->mmraddr) { -+ printk(KERN_WARNING SPIFLASH "Failed to map flash device\n"); -+ goto error; -+ } -+ -+ index = spiflash_probe_chip(priv); -+ if (!index) { -+ printk (KERN_WARNING SPIFLASH "Found no serial flash device\n"); -+ goto error; -+ } -+ -+ priv->readaddr = ioremap_nocache(SPI_FLASH_READ, flashconfig_tbl[index].byte_cnt); -+ if (!priv->readaddr) { -+ printk (KERN_WARNING SPIFLASH "Failed to map flash device\n"); -+ goto error; -+ } -+ -+ platform_set_drvdata(pdev, priv); -+ mtd->name = "spiflash"; -+ mtd->type = MTD_NORFLASH; -+ mtd->flags = (MTD_CAP_NORFLASH|MTD_WRITEABLE); -+ mtd->size = flashconfig_tbl[index].byte_cnt; -+ mtd->erasesize = flashconfig_tbl[index].sector_size; -+ mtd->writesize = 1; -+ mtd->numeraseregions = 0; -+ mtd->eraseregions = NULL; -+ mtd->erase = spiflash_erase; -+ mtd->read = spiflash_read; -+ mtd->write = spiflash_write; -+ mtd->owner = THIS_MODULE; -+ -+#ifdef CONFIG_MTD_PARTITIONS -+ /* parse redboot partitions */ -+ num_parts = parse_mtd_partitions(mtd, part_probe_types, &parts, 0); -+ if (!num_parts) -+ goto error; -+ -+ result = add_mtd_partitions(mtd, parts, num_parts); -+#endif -+ -+ return result; -+ -+error: -+ if (priv->mmraddr) -+ iounmap(priv->mmraddr); -+ kfree(priv); -+ return -ENXIO; -+} -+ -+static int -+spiflash_remove (struct platform_device *pdev) -+{ -+ struct spiflash_priv *priv = platform_get_drvdata(pdev); -+ struct mtd_info *mtd = &priv->mtd; -+ -+ del_mtd_partitions(mtd); -+ iounmap(priv->mmraddr); -+ iounmap(priv->readaddr); -+ kfree(priv); -+ -+ return 0; -+} -+ -+struct platform_driver spiflash_driver = { -+ .driver.name = "spiflash", -+ .probe = spiflash_probe, -+ .remove = spiflash_remove, -+}; -+ -+int __init -+spiflash_init (void) -+{ -+ return platform_driver_register(&spiflash_driver); -+} -+ -+void __exit -+spiflash_exit (void) -+{ -+ return platform_driver_unregister(&spiflash_driver); -+} -+ -+module_init (spiflash_init); -+module_exit (spiflash_exit); -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("OpenWrt.org, Atheros Communications Inc"); -+MODULE_DESCRIPTION("MTD driver for SPI Flash on Atheros SOC"); -+ -diff -Nur linux-2.6.39-rc7.orig/drivers/mtd/redboot.c linux-2.6.39-rc7/drivers/mtd/redboot.c ---- linux-2.6.39-rc7.orig/drivers/mtd/redboot.c 2011-05-10 04:33:54.000000000 +0200 -+++ linux-2.6.39-rc7/drivers/mtd/redboot.c 2011-05-15 21:34:57.000000000 +0200 -@@ -55,6 +55,22 @@ - return 1; - } - -+static uint32_t mtd_get_offset_erasesize(struct mtd_info *mtd, uint64_t offset) -+{ -+ struct mtd_erase_region_info *regions = mtd->eraseregions; -+ int i; -+ -+ for (i = 0; i < mtd->numeraseregions; i++) { -+ if (regions[i].offset + -+ regions[i].numblocks * regions[i].erasesize <= offset) -+ continue; -+ -+ return regions[i].erasesize; -+ } -+ -+ return mtd->erasesize; -+} -+ - static int parse_redboot_partitions(struct mtd_info *master, - struct mtd_partition **pparts, - unsigned long fis_origin) -@@ -70,36 +86,38 @@ - int namelen = 0; - int nulllen = 0; - int numslots; -+ int first_slot; - unsigned long offset; - #ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED - static char nullstring[] = "unallocated"; - #endif - -+ buf = vmalloc(master->erasesize); -+ if (!buf) -+ return -ENOMEM; -+ -+ restart: - if ( directory < 0 ) { - offset = master->size + directory * master->erasesize; -- while (master->block_isbad && -+ while (master->block_isbad && - master->block_isbad(master, offset)) { - if (!offset) { - nogood: - printk(KERN_NOTICE "Failed to find a non-bad block to check for RedBoot partition table\n"); -+ vfree(buf); - return -EIO; - } - offset -= master->erasesize; - } - } else { - offset = directory * master->erasesize; -- while (master->block_isbad && -+ while (master->block_isbad && - master->block_isbad(master, offset)) { - offset += master->erasesize; - if (offset == master->size) - goto nogood; - } - } -- buf = vmalloc(master->erasesize); -- -- if (!buf) -- return -ENOMEM; -- - printk(KERN_NOTICE "Searching for RedBoot partition table in %s at offset 0x%lx\n", - master->name, offset); - -@@ -171,13 +189,21 @@ - } - if (i == numslots) { - /* Didn't find it */ -+ if (offset + master->erasesize < master->size) { -+ /* not at the end of the flash yet, maybe next block :) */ -+ directory++; -+ goto restart; -+ } - printk(KERN_NOTICE "No RedBoot partition table detected in %s\n", - master->name); - ret = 0; - goto out; - } - -- for (i = 0; i < numslots; i++) { -+ first_slot = (buf[i].flash_base & (master->erasesize - 1)) / -+ sizeof(struct fis_image_desc); -+ -+ for (i = first_slot; i < first_slot + numslots; i++) { - struct fis_list *new_fl, **prev; - - if (buf[i].name[0] == 0xff) { -diff -Nur linux-2.6.39-rc7.orig/drivers/net/Kconfig linux-2.6.39-rc7/drivers/net/Kconfig ---- linux-2.6.39-rc7.orig/drivers/net/Kconfig 2011-05-10 04:33:54.000000000 +0200 -+++ linux-2.6.39-rc7/drivers/net/Kconfig 2011-05-15 21:34:57.000000000 +0200 -@@ -251,6 +251,12 @@ - help - Select this if your platform comes with an external 93CX6 eeprom. - -+config AR231X_ETHERNET -+ tristate "AR231x Ethernet support" -+ depends on ATHEROS_AR231X -+ help -+ Support for the AR231x/531x ethernet controller -+ - config MACE - tristate "MACE (Power Mac ethernet) support" - depends on PPC_PMAC && PPC32 -diff -Nur linux-2.6.39-rc7.orig/drivers/net/Makefile linux-2.6.39-rc7/drivers/net/Makefile ---- linux-2.6.39-rc7.orig/drivers/net/Makefile 2011-05-10 04:33:54.000000000 +0200 -+++ linux-2.6.39-rc7/drivers/net/Makefile 2011-05-15 21:34:57.000000000 +0200 -@@ -226,6 +226,7 @@ - obj-$(CONFIG_KORINA) += korina.o - obj-$(CONFIG_MIPS_JAZZ_SONIC) += jazzsonic.o - obj-$(CONFIG_MIPS_AU1X00_ENET) += au1000_eth.o -+obj-$(CONFIG_AR231X_ETHERNET) += ar231x.o - obj-$(CONFIG_MIPS_SIM_NET) += mipsnet.o - obj-$(CONFIG_SGI_IOC3_ETH) += ioc3-eth.o - obj-$(CONFIG_DECLANCE) += declance.o -diff -Nur linux-2.6.39-rc7.orig/drivers/net/ar231x.c linux-2.6.39-rc7/drivers/net/ar231x.c ---- linux-2.6.39-rc7.orig/drivers/net/ar231x.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/drivers/net/ar231x.c 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,1293 @@ -+/* -+ * ar231x.c: Linux driver for the Atheros AR231x Ethernet device. -+ * -+ * Copyright (C) 2004 by Sameer Dekate -+ * Copyright (C) 2006 Imre Kaloz -+ * Copyright (C) 2006-2009 Felix Fietkau -+ * -+ * Thanks to Atheros for providing hardware and documentation -+ * enabling me to write this driver. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * Additional credits: -+ * This code is taken from John Taylor's Sibyte driver and then -+ * modified for the AR2313. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define AR2313_MTU 1692 -+#define AR2313_PRIOS 1 -+#define AR2313_QUEUES (2*AR2313_PRIOS) -+#define AR2313_DESCR_ENTRIES 64 -+ -+ -+#ifndef min -+#define min(a,b) (((a)<(b))?(a):(b)) -+#endif -+ -+#ifndef SMP_CACHE_BYTES -+#define SMP_CACHE_BYTES L1_CACHE_BYTES -+#endif -+ -+#define AR2313_MBOX_SET_BIT 0x8 -+ -+#include "ar231x.h" -+ -+/* -+ * New interrupt handler strategy: -+ * -+ * An old interrupt handler worked using the traditional method of -+ * replacing an skbuff with a new one when a packet arrives. However -+ * the rx rings do not need to contain a static number of buffer -+ * descriptors, thus it makes sense to move the memory allocation out -+ * of the main interrupt handler and do it in a bottom half handler -+ * and only allocate new buffers when the number of buffers in the -+ * ring is below a certain threshold. In order to avoid starving the -+ * NIC under heavy load it is however necessary to force allocation -+ * when hitting a minimum threshold. The strategy for alloction is as -+ * follows: -+ * -+ * RX_LOW_BUF_THRES - allocate buffers in the bottom half -+ * RX_PANIC_LOW_THRES - we are very low on buffers, allocate -+ * the buffers in the interrupt handler -+ * RX_RING_THRES - maximum number of buffers in the rx ring -+ * -+ * One advantagous side effect of this allocation approach is that the -+ * entire rx processing can be done without holding any spin lock -+ * since the rx rings and registers are totally independent of the tx -+ * ring and its registers. This of course includes the kmalloc's of -+ * new skb's. Thus start_xmit can run in parallel with rx processing -+ * and the memory allocation on SMP systems. -+ * -+ * Note that running the skb reallocation in a bottom half opens up -+ * another can of races which needs to be handled properly. In -+ * particular it can happen that the interrupt handler tries to run -+ * the reallocation while the bottom half is either running on another -+ * CPU or was interrupted on the same CPU. To get around this the -+ * driver uses bitops to prevent the reallocation routines from being -+ * reentered. -+ * -+ * TX handling can also be done without holding any spin lock, wheee -+ * this is fun! since tx_csm is only written to by the interrupt -+ * handler. -+ */ -+ -+/* -+ * Threshold values for RX buffer allocation - the low water marks for -+ * when to start refilling the rings are set to 75% of the ring -+ * sizes. It seems to make sense to refill the rings entirely from the -+ * intrrupt handler once it gets below the panic threshold, that way -+ * we don't risk that the refilling is moved to another CPU when the -+ * one running the interrupt handler just got the slab code hot in its -+ * cache. -+ */ -+#define RX_RING_SIZE AR2313_DESCR_ENTRIES -+#define RX_PANIC_THRES (RX_RING_SIZE/4) -+#define RX_LOW_THRES ((3*RX_RING_SIZE)/4) -+#define CRC_LEN 4 -+#define RX_OFFSET 2 -+ -+#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) -+#define VLAN_HDR 4 -+#else -+#define VLAN_HDR 0 -+#endif -+ -+#define AR2313_BUFSIZE (AR2313_MTU + VLAN_HDR + ETH_HLEN + CRC_LEN + RX_OFFSET) -+ -+#ifdef MODULE -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Sameer Dekate , Imre Kaloz , Felix Fietkau "); -+MODULE_DESCRIPTION("AR231x Ethernet driver"); -+#endif -+ -+#define virt_to_phys(x) ((u32)(x) & 0x1fffffff) -+ -+// prototypes -+static void ar231x_halt(struct net_device *dev); -+static void rx_tasklet_func(unsigned long data); -+static void rx_tasklet_cleanup(struct net_device *dev); -+static void ar231x_multicast_list(struct net_device *dev); -+static void ar231x_tx_timeout(struct net_device *dev); -+ -+static int ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum); -+static int ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, u16 value); -+static int ar231x_mdiobus_reset(struct mii_bus *bus); -+static int ar231x_mdiobus_probe (struct net_device *dev); -+static void ar231x_adjust_link(struct net_device *dev); -+ -+#ifndef ERR -+#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args) -+#endif -+ -+#ifdef CONFIG_NET_POLL_CONTROLLER -+static void -+ar231x_netpoll(struct net_device *dev) -+{ -+ unsigned long flags; -+ -+ local_irq_save(flags); -+ ar231x_interrupt(dev->irq, dev); -+ local_irq_restore(flags); -+} -+#endif -+ -+static const struct net_device_ops ar231x_ops = { -+ .ndo_open = ar231x_open, -+ .ndo_stop = ar231x_close, -+ .ndo_start_xmit = ar231x_start_xmit, -+ .ndo_set_multicast_list = ar231x_multicast_list, -+ .ndo_do_ioctl = ar231x_ioctl, -+ .ndo_change_mtu = eth_change_mtu, -+ .ndo_validate_addr = eth_validate_addr, -+ .ndo_set_mac_address = eth_mac_addr, -+ .ndo_tx_timeout = ar231x_tx_timeout, -+#ifdef CONFIG_NET_POLL_CONTROLLER -+ .ndo_poll_controller = ar231x_netpoll, -+#endif -+}; -+ -+int __init ar231x_probe(struct platform_device *pdev) -+{ -+ struct net_device *dev; -+ struct ar231x_private *sp; -+ struct resource *res; -+ unsigned long ar_eth_base; -+ char buf[64]; -+ -+ dev = alloc_etherdev(sizeof(struct ar231x_private)); -+ -+ if (dev == NULL) { -+ printk(KERN_ERR -+ "ar231x: Unable to allocate net_device structure!\n"); -+ return -ENOMEM; -+ } -+ -+ platform_set_drvdata(pdev, dev); -+ -+ sp = netdev_priv(dev); -+ sp->dev = dev; -+ sp->cfg = pdev->dev.platform_data; -+ -+ sprintf(buf, "eth%d_membase", pdev->id); -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, buf); -+ if (!res) -+ return -ENODEV; -+ -+ sp->link = 0; -+ ar_eth_base = res->start; -+ -+ sprintf(buf, "eth%d_irq", pdev->id); -+ dev->irq = platform_get_irq_byname(pdev, buf); -+ -+ spin_lock_init(&sp->lock); -+ -+ dev->features |= NETIF_F_HIGHDMA; -+ dev->netdev_ops = &ar231x_ops; -+ -+ tasklet_init(&sp->rx_tasklet, rx_tasklet_func, (unsigned long) dev); -+ tasklet_disable(&sp->rx_tasklet); -+ -+ sp->eth_regs = -+ ioremap_nocache(virt_to_phys(ar_eth_base), sizeof(*sp->eth_regs)); -+ if (!sp->eth_regs) { -+ printk("Can't remap eth registers\n"); -+ return (-ENXIO); -+ } -+ -+ /* -+ * When there's only one MAC, PHY regs are typically on ENET0, -+ * even though the MAC might be on ENET1. -+ * Needto remap PHY regs separately in this case -+ */ -+ if (virt_to_phys(ar_eth_base) == virt_to_phys(sp->phy_regs)) -+ sp->phy_regs = sp->eth_regs; -+ else { -+ sp->phy_regs = -+ ioremap_nocache(virt_to_phys(sp->cfg->phy_base), -+ sizeof(*sp->phy_regs)); -+ if (!sp->phy_regs) { -+ printk("Can't remap phy registers\n"); -+ return (-ENXIO); -+ } -+ } -+ -+ sp->dma_regs = -+ ioremap_nocache(virt_to_phys(ar_eth_base + 0x1000), -+ sizeof(*sp->dma_regs)); -+ dev->base_addr = (unsigned int) sp->dma_regs; -+ if (!sp->dma_regs) { -+ printk("Can't remap DMA registers\n"); -+ return (-ENXIO); -+ } -+ -+ sp->int_regs = ioremap_nocache(virt_to_phys(sp->cfg->reset_base), 4); -+ if (!sp->int_regs) { -+ printk("Can't remap INTERRUPT registers\n"); -+ return (-ENXIO); -+ } -+ -+ strncpy(sp->name, "Atheros AR231x", sizeof(sp->name) - 1); -+ sp->name[sizeof(sp->name) - 1] = '\0'; -+ memcpy(dev->dev_addr, sp->cfg->macaddr, 6); -+ -+ if (ar231x_init(dev)) { -+ /* -+ * ar231x_init() calls ar231x_init_cleanup() on error. -+ */ -+ kfree(dev); -+ return -ENODEV; -+ } -+ -+ if (register_netdev(dev)) { -+ printk("%s: register_netdev failed\n", __func__); -+ return -1; -+ } -+ -+ printk("%s: %s: %02x:%02x:%02x:%02x:%02x:%02x, irq %d\n", -+ dev->name, sp->name, -+ dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], -+ dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5], dev->irq); -+ -+ sp->mii_bus = mdiobus_alloc(); -+ if (sp->mii_bus == NULL) -+ return -1; -+ -+ sp->mii_bus->priv = dev; -+ sp->mii_bus->read = ar231x_mdiobus_read; -+ sp->mii_bus->write = ar231x_mdiobus_write; -+ sp->mii_bus->reset = ar231x_mdiobus_reset; -+ sp->mii_bus->name = "ar231x_eth_mii"; -+ snprintf(sp->mii_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id); -+ sp->mii_bus->irq = kmalloc(sizeof(int), GFP_KERNEL); -+ *sp->mii_bus->irq = PHY_POLL; -+ -+ mdiobus_register(sp->mii_bus); -+ -+ if (ar231x_mdiobus_probe(dev) != 0) { -+ printk(KERN_ERR "%s: mdiobus_probe failed\n", dev->name); -+ rx_tasklet_cleanup(dev); -+ ar231x_init_cleanup(dev); -+ unregister_netdev(dev); -+ kfree(dev); -+ return -ENODEV; -+ } -+ -+ /* start link poll timer */ -+ ar231x_setup_timer(dev); -+ -+ return 0; -+} -+ -+ -+static void ar231x_multicast_list(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ unsigned int filter; -+ -+ filter = sp->eth_regs->mac_control; -+ -+ if (dev->flags & IFF_PROMISC) -+ filter |= MAC_CONTROL_PR; -+ else -+ filter &= ~MAC_CONTROL_PR; -+ if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 0)) -+ filter |= MAC_CONTROL_PM; -+ else -+ filter &= ~MAC_CONTROL_PM; -+ -+ sp->eth_regs->mac_control = filter; -+} -+ -+static void rx_tasklet_cleanup(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ -+ /* -+ * Tasklet may be scheduled. Need to get it removed from the list -+ * since we're about to free the struct. -+ */ -+ -+ sp->unloading = 1; -+ tasklet_enable(&sp->rx_tasklet); -+ tasklet_kill(&sp->rx_tasklet); -+} -+ -+static int __devexit ar231x_remove(struct platform_device *pdev) -+{ -+ struct net_device *dev = platform_get_drvdata(pdev); -+ struct ar231x_private *sp = netdev_priv(dev); -+ rx_tasklet_cleanup(dev); -+ ar231x_init_cleanup(dev); -+ unregister_netdev(dev); -+ mdiobus_unregister(sp->mii_bus); -+ mdiobus_free(sp->mii_bus); -+ kfree(dev); -+ return 0; -+} -+ -+ -+/* -+ * Restart the AR2313 ethernet controller. -+ */ -+static int ar231x_restart(struct net_device *dev) -+{ -+ /* disable interrupts */ -+ disable_irq(dev->irq); -+ -+ /* stop mac */ -+ ar231x_halt(dev); -+ -+ /* initialize */ -+ ar231x_init(dev); -+ -+ /* enable interrupts */ -+ enable_irq(dev->irq); -+ -+ return 0; -+} -+ -+static struct platform_driver ar231x_driver = { -+ .driver.name = "ar231x-eth", -+ .probe = ar231x_probe, -+ .remove = __devexit_p(ar231x_remove), -+}; -+ -+int __init ar231x_module_init(void) -+{ -+ return platform_driver_register(&ar231x_driver); -+} -+ -+void __exit ar231x_module_cleanup(void) -+{ -+ platform_driver_unregister(&ar231x_driver); -+} -+ -+module_init(ar231x_module_init); -+module_exit(ar231x_module_cleanup); -+ -+ -+static void ar231x_free_descriptors(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ if (sp->rx_ring != NULL) { -+ kfree((void *) KSEG0ADDR(sp->rx_ring)); -+ sp->rx_ring = NULL; -+ sp->tx_ring = NULL; -+ } -+} -+ -+ -+static int ar231x_allocate_descriptors(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ int size; -+ int j; -+ ar231x_descr_t *space; -+ -+ if (sp->rx_ring != NULL) { -+ printk("%s: already done.\n", __FUNCTION__); -+ return 0; -+ } -+ -+ size = -+ (sizeof(ar231x_descr_t) * (AR2313_DESCR_ENTRIES * AR2313_QUEUES)); -+ space = kmalloc(size, GFP_KERNEL); -+ if (space == NULL) -+ return 1; -+ -+ /* invalidate caches */ -+ dma_cache_inv((unsigned int) space, size); -+ -+ /* now convert pointer to KSEG1 */ -+ space = (ar231x_descr_t *) KSEG1ADDR(space); -+ -+ memset((void *) space, 0, size); -+ -+ sp->rx_ring = space; -+ space += AR2313_DESCR_ENTRIES; -+ -+ sp->tx_ring = space; -+ space += AR2313_DESCR_ENTRIES; -+ -+ /* Initialize the transmit Descriptors */ -+ for (j = 0; j < AR2313_DESCR_ENTRIES; j++) { -+ ar231x_descr_t *td = &sp->tx_ring[j]; -+ td->status = 0; -+ td->devcs = DMA_TX1_CHAINED; -+ td->addr = 0; -+ td->descr = -+ virt_to_phys(&sp-> -+ tx_ring[(j + 1) & (AR2313_DESCR_ENTRIES - 1)]); -+ } -+ -+ return 0; -+} -+ -+ -+/* -+ * Generic cleanup handling data allocated during init. Used when the -+ * module is unloaded or if an error occurs during initialization -+ */ -+static void ar231x_init_cleanup(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ struct sk_buff *skb; -+ int j; -+ -+ ar231x_free_descriptors(dev); -+ -+ if (sp->eth_regs) -+ iounmap((void *) sp->eth_regs); -+ if (sp->dma_regs) -+ iounmap((void *) sp->dma_regs); -+ -+ if (sp->rx_skb) { -+ for (j = 0; j < AR2313_DESCR_ENTRIES; j++) { -+ skb = sp->rx_skb[j]; -+ if (skb) { -+ sp->rx_skb[j] = NULL; -+ dev_kfree_skb(skb); -+ } -+ } -+ kfree(sp->rx_skb); -+ sp->rx_skb = NULL; -+ } -+ -+ if (sp->tx_skb) { -+ for (j = 0; j < AR2313_DESCR_ENTRIES; j++) { -+ skb = sp->tx_skb[j]; -+ if (skb) { -+ sp->tx_skb[j] = NULL; -+ dev_kfree_skb(skb); -+ } -+ } -+ kfree(sp->tx_skb); -+ sp->tx_skb = NULL; -+ } -+} -+ -+static int ar231x_setup_timer(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ -+ init_timer(&sp->link_timer); -+ -+ sp->link_timer.function = ar231x_link_timer_fn; -+ sp->link_timer.data = (int) dev; -+ sp->link_timer.expires = jiffies + HZ; -+ -+ add_timer(&sp->link_timer); -+ return 0; -+ -+} -+ -+static void ar231x_link_timer_fn(unsigned long data) -+{ -+ struct net_device *dev = (struct net_device *) data; -+ struct ar231x_private *sp = netdev_priv(dev); -+ -+ // see if the link status changed -+ // This was needed to make sure we set the PHY to the -+ // autonegotiated value of half or full duplex. -+ ar231x_check_link(dev); -+ -+ // Loop faster when we don't have link. -+ // This was needed to speed up the AP bootstrap time. -+ if (sp->link == 0) { -+ mod_timer(&sp->link_timer, jiffies + HZ / 2); -+ } else { -+ mod_timer(&sp->link_timer, jiffies + LINK_TIMER); -+ } -+} -+ -+static void ar231x_check_link(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ u16 phyData; -+ -+ phyData = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_BMSR); -+ if (sp->phyData != phyData) { -+ if (phyData & BMSR_LSTATUS) { -+ /* link is present, ready link partner ability to deterine -+ duplexity */ -+ int duplex = 0; -+ u16 reg; -+ -+ sp->link = 1; -+ reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_BMCR); -+ if (reg & BMCR_ANENABLE) { -+ /* auto neg enabled */ -+ reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_LPA); -+ duplex = (reg & (LPA_100FULL | LPA_10FULL)) ? 1 : 0; -+ } else { -+ /* no auto neg, just read duplex config */ -+ duplex = (reg & BMCR_FULLDPLX) ? 1 : 0; -+ } -+ -+ printk(KERN_INFO "%s: Configuring MAC for %s duplex\n", -+ dev->name, (duplex) ? "full" : "half"); -+ -+ if (duplex) { -+ /* full duplex */ -+ sp->eth_regs->mac_control = -+ ((sp->eth_regs-> -+ mac_control | MAC_CONTROL_F) & ~MAC_CONTROL_DRO); -+ } else { -+ /* half duplex */ -+ sp->eth_regs->mac_control = -+ ((sp->eth_regs-> -+ mac_control | MAC_CONTROL_DRO) & ~MAC_CONTROL_F); -+ } -+ } else { -+ /* no link */ -+ sp->link = 0; -+ } -+ sp->phyData = phyData; -+ } -+} -+ -+static int ar231x_reset_reg(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ unsigned int ethsal, ethsah; -+ unsigned int flags; -+ -+ *sp->int_regs |= sp->cfg->reset_mac; -+ mdelay(10); -+ *sp->int_regs &= ~sp->cfg->reset_mac; -+ mdelay(10); -+ *sp->int_regs |= sp->cfg->reset_phy; -+ mdelay(10); -+ *sp->int_regs &= ~sp->cfg->reset_phy; -+ mdelay(10); -+ -+ sp->dma_regs->bus_mode = (DMA_BUS_MODE_SWR); -+ mdelay(10); -+ sp->dma_regs->bus_mode = -+ ((32 << DMA_BUS_MODE_PBL_SHIFT) | DMA_BUS_MODE_BLE); -+ -+ /* enable interrupts */ -+ sp->dma_regs->intr_ena = (DMA_STATUS_AIS | -+ DMA_STATUS_NIS | -+ DMA_STATUS_RI | -+ DMA_STATUS_TI | DMA_STATUS_FBE); -+ sp->dma_regs->xmt_base = virt_to_phys(sp->tx_ring); -+ sp->dma_regs->rcv_base = virt_to_phys(sp->rx_ring); -+ sp->dma_regs->control = -+ (DMA_CONTROL_SR | DMA_CONTROL_ST | DMA_CONTROL_SF); -+ -+ sp->eth_regs->flow_control = (FLOW_CONTROL_FCE); -+ sp->eth_regs->vlan_tag = (0x8100); -+ -+ /* Enable Ethernet Interface */ -+ flags = (MAC_CONTROL_TE | /* transmit enable */ -+ MAC_CONTROL_PM | /* pass mcast */ -+ MAC_CONTROL_F | /* full duplex */ -+ MAC_CONTROL_HBD); /* heart beat disabled */ -+ -+ if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */ -+ flags |= MAC_CONTROL_PR; -+ } -+ sp->eth_regs->mac_control = flags; -+ -+ /* Set all Ethernet station address registers to their initial values */ -+ ethsah = ((((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) | -+ (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF)); -+ -+ ethsal = ((((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) | -+ (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) | -+ (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) | -+ (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF)); -+ -+ sp->eth_regs->mac_addr[0] = ethsah; -+ sp->eth_regs->mac_addr[1] = ethsal; -+ -+ mdelay(10); -+ -+ return (0); -+} -+ -+ -+static int ar231x_init(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ int ecode = 0; -+ -+ /* -+ * Allocate descriptors -+ */ -+ if (ar231x_allocate_descriptors(dev)) { -+ printk("%s: %s: ar231x_allocate_descriptors failed\n", -+ dev->name, __FUNCTION__); -+ ecode = -EAGAIN; -+ goto init_error; -+ } -+ -+ /* -+ * Get the memory for the skb rings. -+ */ -+ if (sp->rx_skb == NULL) { -+ sp->rx_skb = -+ kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES, -+ GFP_KERNEL); -+ if (!(sp->rx_skb)) { -+ printk("%s: %s: rx_skb kmalloc failed\n", -+ dev->name, __FUNCTION__); -+ ecode = -EAGAIN; -+ goto init_error; -+ } -+ } -+ memset(sp->rx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES); -+ -+ if (sp->tx_skb == NULL) { -+ sp->tx_skb = -+ kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES, -+ GFP_KERNEL); -+ if (!(sp->tx_skb)) { -+ printk("%s: %s: tx_skb kmalloc failed\n", -+ dev->name, __FUNCTION__); -+ ecode = -EAGAIN; -+ goto init_error; -+ } -+ } -+ memset(sp->tx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES); -+ -+ /* -+ * Set tx_csm before we start receiving interrupts, otherwise -+ * the interrupt handler might think it is supposed to process -+ * tx ints before we are up and running, which may cause a null -+ * pointer access in the int handler. -+ */ -+ sp->rx_skbprd = 0; -+ sp->cur_rx = 0; -+ sp->tx_prd = 0; -+ sp->tx_csm = 0; -+ -+ /* -+ * Zero the stats before starting the interface -+ */ -+ memset(&dev->stats, 0, sizeof(dev->stats)); -+ -+ /* -+ * We load the ring here as there seem to be no way to tell the -+ * firmware to wipe the ring without re-initializing it. -+ */ -+ ar231x_load_rx_ring(dev, RX_RING_SIZE); -+ -+ /* -+ * Init hardware -+ */ -+ ar231x_reset_reg(dev); -+ -+ /* -+ * Get the IRQ -+ */ -+ ecode = -+ request_irq(dev->irq, &ar231x_interrupt, -+ IRQF_DISABLED | IRQF_SAMPLE_RANDOM, -+ dev->name, dev); -+ if (ecode) { -+ printk(KERN_WARNING "%s: %s: Requested IRQ %d is busy\n", -+ dev->name, __FUNCTION__, dev->irq); -+ goto init_error; -+ } -+ -+ -+ tasklet_enable(&sp->rx_tasklet); -+ -+ return 0; -+ -+ init_error: -+ ar231x_init_cleanup(dev); -+ return ecode; -+} -+ -+/* -+ * Load the rx ring. -+ * -+ * Loading rings is safe without holding the spin lock since this is -+ * done only before the device is enabled, thus no interrupts are -+ * generated and by the interrupt handler/tasklet handler. -+ */ -+static void ar231x_load_rx_ring(struct net_device *dev, int nr_bufs) -+{ -+ -+ struct ar231x_private *sp = netdev_priv(dev); -+ short i, idx; -+ -+ idx = sp->rx_skbprd; -+ -+ for (i = 0; i < nr_bufs; i++) { -+ struct sk_buff *skb; -+ ar231x_descr_t *rd; -+ -+ if (sp->rx_skb[idx]) -+ break; -+ -+ skb = netdev_alloc_skb(dev, AR2313_BUFSIZE); -+ if (!skb) { -+ printk("\n\n\n\n %s: No memory in system\n\n\n\n", -+ __FUNCTION__); -+ break; -+ } -+ -+ /* -+ * Make sure IP header starts on a fresh cache line. -+ */ -+ skb->dev = dev; -+ skb_reserve(skb, RX_OFFSET); -+ sp->rx_skb[idx] = skb; -+ -+ rd = (ar231x_descr_t *) & sp->rx_ring[idx]; -+ -+ /* initialize dma descriptor */ -+ rd->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) | -+ DMA_RX1_CHAINED); -+ rd->addr = virt_to_phys(skb->data); -+ rd->descr = -+ virt_to_phys(&sp-> -+ rx_ring[(idx + 1) & (AR2313_DESCR_ENTRIES - 1)]); -+ rd->status = DMA_RX_OWN; -+ -+ idx = DSC_NEXT(idx); -+ } -+ -+ if (i) -+ sp->rx_skbprd = idx; -+ -+ return; -+} -+ -+#define AR2313_MAX_PKTS_PER_CALL 64 -+ -+static int ar231x_rx_int(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ struct sk_buff *skb, *skb_new; -+ ar231x_descr_t *rxdesc; -+ unsigned int status; -+ u32 idx; -+ int pkts = 0; -+ int rval; -+ -+ idx = sp->cur_rx; -+ -+ /* process at most the entire ring and then wait for another interrupt -+ */ -+ while (1) { -+ -+ rxdesc = &sp->rx_ring[idx]; -+ status = rxdesc->status; -+ if (status & DMA_RX_OWN) { -+ /* SiByte owns descriptor or descr not yet filled in */ -+ rval = 0; -+ break; -+ } -+ -+ if (++pkts > AR2313_MAX_PKTS_PER_CALL) { -+ rval = 1; -+ break; -+ } -+ -+ if ((status & DMA_RX_ERROR) && !(status & DMA_RX_LONG)) { -+ dev->stats.rx_errors++; -+ dev->stats.rx_dropped++; -+ -+ /* add statistics counters */ -+ if (status & DMA_RX_ERR_CRC) -+ dev->stats.rx_crc_errors++; -+ if (status & DMA_RX_ERR_COL) -+ dev->stats.rx_over_errors++; -+ if (status & DMA_RX_ERR_LENGTH) -+ dev->stats.rx_length_errors++; -+ if (status & DMA_RX_ERR_RUNT) -+ dev->stats.rx_over_errors++; -+ if (status & DMA_RX_ERR_DESC) -+ dev->stats.rx_over_errors++; -+ -+ } else { -+ /* alloc new buffer. */ -+ skb_new = netdev_alloc_skb(dev, AR2313_BUFSIZE + RX_OFFSET); -+ if (skb_new != NULL) { -+ -+ skb = sp->rx_skb[idx]; -+ /* set skb */ -+ skb_put(skb, -+ ((status >> DMA_RX_LEN_SHIFT) & 0x3fff) - CRC_LEN); -+ -+ dev->stats.rx_bytes += skb->len; -+ skb->protocol = eth_type_trans(skb, dev); -+ /* pass the packet to upper layers */ -+ netif_rx(skb); -+ -+ skb_new->dev = dev; -+ /* 16 bit align */ -+ skb_reserve(skb_new, RX_OFFSET); -+ /* reset descriptor's curr_addr */ -+ rxdesc->addr = virt_to_phys(skb_new->data); -+ -+ dev->stats.rx_packets++; -+ sp->rx_skb[idx] = skb_new; -+ } else { -+ dev->stats.rx_dropped++; -+ } -+ } -+ -+ rxdesc->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) | -+ DMA_RX1_CHAINED); -+ rxdesc->status = DMA_RX_OWN; -+ -+ idx = DSC_NEXT(idx); -+ } -+ -+ sp->cur_rx = idx; -+ -+ return rval; -+} -+ -+ -+static void ar231x_tx_int(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ u32 idx; -+ struct sk_buff *skb; -+ ar231x_descr_t *txdesc; -+ unsigned int status = 0; -+ -+ idx = sp->tx_csm; -+ -+ while (idx != sp->tx_prd) { -+ txdesc = &sp->tx_ring[idx]; -+ -+ if ((status = txdesc->status) & DMA_TX_OWN) { -+ /* ar231x dma still owns descr */ -+ break; -+ } -+ /* done with this descriptor */ -+ dma_unmap_single(NULL, txdesc->addr, -+ txdesc->devcs & DMA_TX1_BSIZE_MASK, -+ DMA_TO_DEVICE); -+ txdesc->status = 0; -+ -+ if (status & DMA_TX_ERROR) { -+ dev->stats.tx_errors++; -+ dev->stats.tx_dropped++; -+ if (status & DMA_TX_ERR_UNDER) -+ dev->stats.tx_fifo_errors++; -+ if (status & DMA_TX_ERR_HB) -+ dev->stats.tx_heartbeat_errors++; -+ if (status & (DMA_TX_ERR_LOSS | DMA_TX_ERR_LINK)) -+ dev->stats.tx_carrier_errors++; -+ if (status & (DMA_TX_ERR_LATE | -+ DMA_TX_ERR_COL | -+ DMA_TX_ERR_JABBER | DMA_TX_ERR_DEFER)) -+ dev->stats.tx_aborted_errors++; -+ } else { -+ /* transmit OK */ -+ dev->stats.tx_packets++; -+ } -+ -+ skb = sp->tx_skb[idx]; -+ sp->tx_skb[idx] = NULL; -+ idx = DSC_NEXT(idx); -+ dev->stats.tx_bytes += skb->len; -+ dev_kfree_skb_irq(skb); -+ } -+ -+ sp->tx_csm = idx; -+ -+ return; -+} -+ -+ -+static void rx_tasklet_func(unsigned long data) -+{ -+ struct net_device *dev = (struct net_device *) data; -+ struct ar231x_private *sp = netdev_priv(dev); -+ -+ if (sp->unloading) { -+ return; -+ } -+ -+ if (ar231x_rx_int(dev)) { -+ tasklet_hi_schedule(&sp->rx_tasklet); -+ } else { -+ unsigned long flags; -+ spin_lock_irqsave(&sp->lock, flags); -+ sp->dma_regs->intr_ena |= DMA_STATUS_RI; -+ spin_unlock_irqrestore(&sp->lock, flags); -+ } -+} -+ -+static void rx_schedule(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ -+ sp->dma_regs->intr_ena &= ~DMA_STATUS_RI; -+ -+ tasklet_hi_schedule(&sp->rx_tasklet); -+} -+ -+static irqreturn_t ar231x_interrupt(int irq, void *dev_id) -+{ -+ struct net_device *dev = (struct net_device *) dev_id; -+ struct ar231x_private *sp = netdev_priv(dev); -+ unsigned int status, enabled; -+ -+ /* clear interrupt */ -+ /* -+ * Don't clear RI bit if currently disabled. -+ */ -+ status = sp->dma_regs->status; -+ enabled = sp->dma_regs->intr_ena; -+ sp->dma_regs->status = status & enabled; -+ -+ if (status & DMA_STATUS_NIS) { -+ /* normal status */ -+ /* -+ * Don't schedule rx processing if interrupt -+ * is already disabled. -+ */ -+ if (status & enabled & DMA_STATUS_RI) { -+ /* receive interrupt */ -+ rx_schedule(dev); -+ } -+ if (status & DMA_STATUS_TI) { -+ /* transmit interrupt */ -+ ar231x_tx_int(dev); -+ } -+ } -+ -+ /* abnormal status */ -+ if (status & (DMA_STATUS_FBE | DMA_STATUS_TPS)) { -+ ar231x_restart(dev); -+ } -+ return IRQ_HANDLED; -+} -+ -+ -+static int ar231x_open(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ unsigned int ethsal, ethsah; -+ -+ /* reset the hardware, in case the MAC address changed */ -+ ethsah = ((((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) | -+ (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF)); -+ -+ ethsal = ((((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) | -+ (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) | -+ (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) | -+ (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF)); -+ -+ sp->eth_regs->mac_addr[0] = ethsah; -+ sp->eth_regs->mac_addr[1] = ethsal; -+ -+ mdelay(10); -+ -+ dev->mtu = 1500; -+ netif_start_queue(dev); -+ -+ sp->eth_regs->mac_control |= MAC_CONTROL_RE; -+ -+ return 0; -+} -+ -+static void ar231x_tx_timeout(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ unsigned long flags; -+ -+ spin_lock_irqsave(&sp->lock, flags); -+ ar231x_restart(dev); -+ spin_unlock_irqrestore(&sp->lock, flags); -+} -+ -+static void ar231x_halt(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ int j; -+ -+ tasklet_disable(&sp->rx_tasklet); -+ -+ /* kill the MAC */ -+ sp->eth_regs->mac_control &= ~(MAC_CONTROL_RE | /* disable Receives */ -+ MAC_CONTROL_TE); /* disable Transmits */ -+ /* stop dma */ -+ sp->dma_regs->control = 0; -+ sp->dma_regs->bus_mode = DMA_BUS_MODE_SWR; -+ -+ /* place phy and MAC in reset */ -+ *sp->int_regs |= (sp->cfg->reset_mac | sp->cfg->reset_phy); -+ -+ /* free buffers on tx ring */ -+ for (j = 0; j < AR2313_DESCR_ENTRIES; j++) { -+ struct sk_buff *skb; -+ ar231x_descr_t *txdesc; -+ -+ txdesc = &sp->tx_ring[j]; -+ txdesc->descr = 0; -+ -+ skb = sp->tx_skb[j]; -+ if (skb) { -+ dev_kfree_skb(skb); -+ sp->tx_skb[j] = NULL; -+ } -+ } -+} -+ -+/* -+ * close should do nothing. Here's why. It's called when -+ * 'ifconfig bond0 down' is run. If it calls free_irq then -+ * the irq is gone forever ! When bond0 is made 'up' again, -+ * the ar231x_open () does not call request_irq (). Worse, -+ * the call to ar231x_halt() generates a WDOG reset due to -+ * the write to 'sp->int_regs' and the box reboots. -+ * Commenting this out is good since it allows the -+ * system to resume when bond0 is made up again. -+ */ -+static int ar231x_close(struct net_device *dev) -+{ -+#if 0 -+ /* -+ * Disable interrupts -+ */ -+ disable_irq(dev->irq); -+ -+ /* -+ * Without (or before) releasing irq and stopping hardware, this -+ * is an absolute non-sense, by the way. It will be reset instantly -+ * by the first irq. -+ */ -+ netif_stop_queue(dev); -+ -+ /* stop the MAC and DMA engines */ -+ ar231x_halt(dev); -+ -+ /* release the interrupt */ -+ free_irq(dev->irq, dev); -+ -+#endif -+ return 0; -+} -+ -+static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ ar231x_descr_t *td; -+ u32 idx; -+ -+ idx = sp->tx_prd; -+ td = &sp->tx_ring[idx]; -+ -+ if (td->status & DMA_TX_OWN) { -+ /* free skbuf and lie to the caller that we sent it out */ -+ dev->stats.tx_dropped++; -+ dev_kfree_skb(skb); -+ -+ /* restart transmitter in case locked */ -+ sp->dma_regs->xmt_poll = 0; -+ return 0; -+ } -+ -+ /* Setup the transmit descriptor. */ -+ td->devcs = ((skb->len << DMA_TX1_BSIZE_SHIFT) | -+ (DMA_TX1_LS | DMA_TX1_IC | DMA_TX1_CHAINED)); -+ td->addr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE); -+ td->status = DMA_TX_OWN; -+ -+ /* kick transmitter last */ -+ sp->dma_regs->xmt_poll = 0; -+ -+ sp->tx_skb[idx] = skb; -+ idx = DSC_NEXT(idx); -+ sp->tx_prd = idx; -+ -+ return 0; -+} -+ -+static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) -+{ -+ struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_data; -+ struct ar231x_private *sp = netdev_priv(dev); -+ int ret; -+ -+ switch (cmd) { -+ -+ case SIOCETHTOOL: -+ spin_lock_irq(&sp->lock); -+ ret = phy_ethtool_ioctl(sp->phy_dev, (void *) ifr->ifr_data); -+ spin_unlock_irq(&sp->lock); -+ return ret; -+ -+ case SIOCSIFHWADDR: -+ if (copy_from_user -+ (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr))) -+ return -EFAULT; -+ return 0; -+ -+ case SIOCGIFHWADDR: -+ if (copy_to_user -+ (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr))) -+ return -EFAULT; -+ return 0; -+ -+ case SIOCGMIIPHY: -+ case SIOCGMIIREG: -+ case SIOCSMIIREG: -+ return phy_mii_ioctl(sp->phy_dev, data, cmd); -+ -+ default: -+ break; -+ } -+ -+ return -EOPNOTSUPP; -+} -+ -+static void ar231x_adjust_link(struct net_device *dev) -+{ -+ struct ar231x_private *sp = netdev_priv(dev); -+ unsigned int mc; -+ -+ if (!sp->phy_dev->link) -+ return; -+ -+ if (sp->phy_dev->duplex != sp->oldduplex) { -+ mc = readl(&sp->eth_regs->mac_control); -+ mc &= ~(MAC_CONTROL_F | MAC_CONTROL_DRO); -+ if (sp->phy_dev->duplex) -+ mc |= MAC_CONTROL_F; -+ else -+ mc |= MAC_CONTROL_DRO; -+ writel(mc, &sp->eth_regs->mac_control); -+ sp->oldduplex = sp->phy_dev->duplex; -+ } -+} -+ -+#define MII_ADDR(phy, reg) \ -+ ((reg << MII_ADDR_REG_SHIFT) | (phy << MII_ADDR_PHY_SHIFT)) -+ -+static int -+ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum) -+{ -+ struct net_device *const dev = bus->priv; -+ struct ar231x_private *sp = netdev_priv(dev); -+ volatile ETHERNET_STRUCT *ethernet = sp->phy_regs; -+ -+ ethernet->mii_addr = MII_ADDR(phy_addr, regnum); -+ while (ethernet->mii_addr & MII_ADDR_BUSY); -+ return (ethernet->mii_data >> MII_DATA_SHIFT); -+} -+ -+static int -+ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, -+ u16 value) -+{ -+ struct net_device *const dev = bus->priv; -+ struct ar231x_private *sp = netdev_priv(dev); -+ volatile ETHERNET_STRUCT *ethernet = sp->phy_regs; -+ -+ while (ethernet->mii_addr & MII_ADDR_BUSY); -+ ethernet->mii_data = value << MII_DATA_SHIFT; -+ ethernet->mii_addr = MII_ADDR(phy_addr, regnum) | MII_ADDR_WRITE; -+ -+ return 0; -+} -+ -+static int ar231x_mdiobus_reset(struct mii_bus *bus) -+{ -+ struct net_device *const dev = bus->priv; -+ -+ ar231x_reset_reg(dev); -+ -+ return 0; -+} -+ -+static int ar231x_mdiobus_probe (struct net_device *dev) -+{ -+ struct ar231x_private *const sp = netdev_priv(dev); -+ struct phy_device *phydev = NULL; -+ int phy_addr; -+ -+ /* find the first (lowest address) PHY on the current MAC's MII bus */ -+ for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) -+ if (sp->mii_bus->phy_map[phy_addr]) { -+ phydev = sp->mii_bus->phy_map[phy_addr]; -+ sp->phy = phy_addr; -+ break; /* break out with first one found */ -+ } -+ -+ if (!phydev) { -+ printk (KERN_ERR "ar231x: %s: no PHY found\n", dev->name); -+ return -1; -+ } -+ -+ /* now we are supposed to have a proper phydev, to attach to... */ -+ BUG_ON(!phydev); -+ BUG_ON(phydev->attached_dev); -+ -+ phydev = phy_connect(dev, dev_name(&phydev->dev), &ar231x_adjust_link, 0, -+ PHY_INTERFACE_MODE_MII); -+ -+ if (IS_ERR(phydev)) { -+ printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name); -+ return PTR_ERR(phydev); -+ } -+ -+ /* mask with MAC supported features */ -+ phydev->supported &= (SUPPORTED_10baseT_Half -+ | SUPPORTED_10baseT_Full -+ | SUPPORTED_100baseT_Half -+ | SUPPORTED_100baseT_Full -+ | SUPPORTED_Autoneg -+ /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */ -+ | SUPPORTED_MII -+ | SUPPORTED_TP); -+ -+ phydev->advertising = phydev->supported; -+ -+ sp->oldduplex = -1; -+ sp->phy_dev = phydev; -+ -+ printk(KERN_INFO "%s: attached PHY driver [%s] " -+ "(mii_bus:phy_addr=%s)\n", -+ dev->name, phydev->drv->name, dev_name(&phydev->dev)); -+ -+ return 0; -+} -+ -diff -Nur linux-2.6.39-rc7.orig/drivers/net/ar231x.h linux-2.6.39-rc7/drivers/net/ar231x.h ---- linux-2.6.39-rc7.orig/drivers/net/ar231x.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/drivers/net/ar231x.h 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,302 @@ -+/* -+ * ar231x.h: Linux driver for the Atheros AR231x Ethernet device. -+ * -+ * Copyright (C) 2004 by Sameer Dekate -+ * Copyright (C) 2006 Imre Kaloz -+ * Copyright (C) 2006-2009 Felix Fietkau -+ * -+ * Thanks to Atheros for providing hardware and documentation -+ * enabling me to write this driver. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ */ -+ -+#ifndef _AR2313_H_ -+#define _AR2313_H_ -+ -+#include -+#include -+#include -+#include -+ -+/* -+ * probe link timer - 5 secs -+ */ -+#define LINK_TIMER (5*HZ) -+ -+#define IS_DMA_TX_INT(X) (((X) & (DMA_STATUS_TI)) != 0) -+#define IS_DMA_RX_INT(X) (((X) & (DMA_STATUS_RI)) != 0) -+#define IS_DRIVER_OWNED(X) (((X) & (DMA_TX_OWN)) == 0) -+ -+#define AR2313_TX_TIMEOUT (HZ/4) -+ -+/* -+ * Rings -+ */ -+#define DSC_RING_ENTRIES_SIZE (AR2313_DESCR_ENTRIES * sizeof(struct desc)) -+#define DSC_NEXT(idx) ((idx + 1) & (AR2313_DESCR_ENTRIES - 1)) -+ -+#define AR2313_MBGET 2 -+#define AR2313_MBSET 3 -+#define AR2313_PCI_RECONFIG 4 -+#define AR2313_PCI_DUMP 5 -+#define AR2313_TEST_PANIC 6 -+#define AR2313_TEST_NULLPTR 7 -+#define AR2313_READ_DATA 8 -+#define AR2313_WRITE_DATA 9 -+#define AR2313_GET_VERSION 10 -+#define AR2313_TEST_HANG 11 -+#define AR2313_SYNC 12 -+ -+#define DMA_RX_ERR_CRC BIT(1) -+#define DMA_RX_ERR_DRIB BIT(2) -+#define DMA_RX_ERR_MII BIT(3) -+#define DMA_RX_EV2 BIT(5) -+#define DMA_RX_ERR_COL BIT(6) -+#define DMA_RX_LONG BIT(7) -+#define DMA_RX_LS BIT(8) /* last descriptor */ -+#define DMA_RX_FS BIT(9) /* first descriptor */ -+#define DMA_RX_MF BIT(10) /* multicast frame */ -+#define DMA_RX_ERR_RUNT BIT(11) /* runt frame */ -+#define DMA_RX_ERR_LENGTH BIT(12) /* length error */ -+#define DMA_RX_ERR_DESC BIT(14) /* descriptor error */ -+#define DMA_RX_ERROR BIT(15) /* error summary */ -+#define DMA_RX_LEN_MASK 0x3fff0000 -+#define DMA_RX_LEN_SHIFT 16 -+#define DMA_RX_FILT BIT(30) -+#define DMA_RX_OWN BIT(31) /* desc owned by DMA controller */ -+ -+#define DMA_RX1_BSIZE_MASK 0x000007ff -+#define DMA_RX1_BSIZE_SHIFT 0 -+#define DMA_RX1_CHAINED BIT(24) -+#define DMA_RX1_RER BIT(25) -+ -+#define DMA_TX_ERR_UNDER BIT(1) /* underflow error */ -+#define DMA_TX_ERR_DEFER BIT(2) /* excessive deferral */ -+#define DMA_TX_COL_MASK 0x78 -+#define DMA_TX_COL_SHIFT 3 -+#define DMA_TX_ERR_HB BIT(7) /* hearbeat failure */ -+#define DMA_TX_ERR_COL BIT(8) /* excessive collisions */ -+#define DMA_TX_ERR_LATE BIT(9) /* late collision */ -+#define DMA_TX_ERR_LINK BIT(10) /* no carrier */ -+#define DMA_TX_ERR_LOSS BIT(11) /* loss of carrier */ -+#define DMA_TX_ERR_JABBER BIT(14) /* transmit jabber timeout */ -+#define DMA_TX_ERROR BIT(15) /* frame aborted */ -+#define DMA_TX_OWN BIT(31) /* descr owned by DMA controller */ -+ -+#define DMA_TX1_BSIZE_MASK 0x000007ff -+#define DMA_TX1_BSIZE_SHIFT 0 -+#define DMA_TX1_CHAINED BIT(24) /* chained descriptors */ -+#define DMA_TX1_TER BIT(25) /* transmit end of ring */ -+#define DMA_TX1_FS BIT(29) /* first segment */ -+#define DMA_TX1_LS BIT(30) /* last segment */ -+#define DMA_TX1_IC BIT(31) /* interrupt on completion */ -+ -+#define RCVPKT_LENGTH(X) (X >> 16) /* Received pkt Length */ -+ -+#define MAC_CONTROL_RE BIT(2) /* receive enable */ -+#define MAC_CONTROL_TE BIT(3) /* transmit enable */ -+#define MAC_CONTROL_DC BIT(5) /* Deferral check */ -+#define MAC_CONTROL_ASTP BIT(8) /* Auto pad strip */ -+#define MAC_CONTROL_DRTY BIT(10) /* Disable retry */ -+#define MAC_CONTROL_DBF BIT(11) /* Disable bcast frames */ -+#define MAC_CONTROL_LCC BIT(12) /* late collision ctrl */ -+#define MAC_CONTROL_HP BIT(13) /* Hash Perfect filtering */ -+#define MAC_CONTROL_HASH BIT(14) /* Unicast hash filtering */ -+#define MAC_CONTROL_HO BIT(15) /* Hash only filtering */ -+#define MAC_CONTROL_PB BIT(16) /* Pass Bad frames */ -+#define MAC_CONTROL_IF BIT(17) /* Inverse filtering */ -+#define MAC_CONTROL_PR BIT(18) /* promiscuous mode (valid frames only) */ -+#define MAC_CONTROL_PM BIT(19) /* pass multicast */ -+#define MAC_CONTROL_F BIT(20) /* full-duplex */ -+#define MAC_CONTROL_DRO BIT(23) /* Disable Receive Own */ -+#define MAC_CONTROL_HBD BIT(28) /* heart-beat disabled (MUST BE SET) */ -+#define MAC_CONTROL_BLE BIT(30) /* big endian mode */ -+#define MAC_CONTROL_RA BIT(31) /* receive all (valid and invalid frames) */ -+ -+#define MII_ADDR_BUSY BIT(0) -+#define MII_ADDR_WRITE BIT(1) -+#define MII_ADDR_REG_SHIFT 6 -+#define MII_ADDR_PHY_SHIFT 11 -+#define MII_DATA_SHIFT 0 -+ -+#define FLOW_CONTROL_FCE BIT(1) -+ -+#define DMA_BUS_MODE_SWR BIT(0) /* software reset */ -+#define DMA_BUS_MODE_BLE BIT(7) /* big endian mode */ -+#define DMA_BUS_MODE_PBL_SHIFT 8 /* programmable burst length 32 */ -+#define DMA_BUS_MODE_DBO BIT(20) /* big-endian descriptors */ -+ -+#define DMA_STATUS_TI BIT(0) /* transmit interrupt */ -+#define DMA_STATUS_TPS BIT(1) /* transmit process stopped */ -+#define DMA_STATUS_TU BIT(2) /* transmit buffer unavailable */ -+#define DMA_STATUS_TJT BIT(3) /* transmit buffer timeout */ -+#define DMA_STATUS_UNF BIT(5) /* transmit underflow */ -+#define DMA_STATUS_RI BIT(6) /* receive interrupt */ -+#define DMA_STATUS_RU BIT(7) /* receive buffer unavailable */ -+#define DMA_STATUS_RPS BIT(8) /* receive process stopped */ -+#define DMA_STATUS_ETI BIT(10) /* early transmit interrupt */ -+#define DMA_STATUS_FBE BIT(13) /* fatal bus interrupt */ -+#define DMA_STATUS_ERI BIT(14) /* early receive interrupt */ -+#define DMA_STATUS_AIS BIT(15) /* abnormal interrupt summary */ -+#define DMA_STATUS_NIS BIT(16) /* normal interrupt summary */ -+#define DMA_STATUS_RS_SHIFT 17 /* receive process state */ -+#define DMA_STATUS_TS_SHIFT 20 /* transmit process state */ -+#define DMA_STATUS_EB_SHIFT 23 /* error bits */ -+ -+#define DMA_CONTROL_SR BIT(1) /* start receive */ -+#define DMA_CONTROL_ST BIT(13) /* start transmit */ -+#define DMA_CONTROL_SF BIT(21) /* store and forward */ -+ -+ -+typedef struct { -+ volatile unsigned int status; // OWN, Device control and status. -+ volatile unsigned int devcs; // pkt Control bits + Length -+ volatile unsigned int addr; // Current Address. -+ volatile unsigned int descr; // Next descriptor in chain. -+} ar231x_descr_t; -+ -+ -+ -+// -+// New Combo structure for Both Eth0 AND eth1 -+// -+typedef struct { -+ volatile unsigned int mac_control; /* 0x00 */ -+ volatile unsigned int mac_addr[2]; /* 0x04 - 0x08 */ -+ volatile unsigned int mcast_table[2]; /* 0x0c - 0x10 */ -+ volatile unsigned int mii_addr; /* 0x14 */ -+ volatile unsigned int mii_data; /* 0x18 */ -+ volatile unsigned int flow_control; /* 0x1c */ -+ volatile unsigned int vlan_tag; /* 0x20 */ -+ volatile unsigned int pad[7]; /* 0x24 - 0x3c */ -+ volatile unsigned int ucast_table[8]; /* 0x40-0x5c */ -+ -+} ETHERNET_STRUCT; -+ -+/******************************************************************** -+ * Interrupt controller -+ ********************************************************************/ -+ -+typedef struct { -+ volatile unsigned int wdog_control; /* 0x08 */ -+ volatile unsigned int wdog_timer; /* 0x0c */ -+ volatile unsigned int misc_status; /* 0x10 */ -+ volatile unsigned int misc_mask; /* 0x14 */ -+ volatile unsigned int global_status; /* 0x18 */ -+ volatile unsigned int reserved; /* 0x1c */ -+ volatile unsigned int reset_control; /* 0x20 */ -+} INTERRUPT; -+ -+/******************************************************************** -+ * DMA controller -+ ********************************************************************/ -+typedef struct { -+ volatile unsigned int bus_mode; /* 0x00 (CSR0) */ -+ volatile unsigned int xmt_poll; /* 0x04 (CSR1) */ -+ volatile unsigned int rcv_poll; /* 0x08 (CSR2) */ -+ volatile unsigned int rcv_base; /* 0x0c (CSR3) */ -+ volatile unsigned int xmt_base; /* 0x10 (CSR4) */ -+ volatile unsigned int status; /* 0x14 (CSR5) */ -+ volatile unsigned int control; /* 0x18 (CSR6) */ -+ volatile unsigned int intr_ena; /* 0x1c (CSR7) */ -+ volatile unsigned int rcv_missed; /* 0x20 (CSR8) */ -+ volatile unsigned int reserved[11]; /* 0x24-0x4c (CSR9-19) */ -+ volatile unsigned int cur_tx_buf_addr; /* 0x50 (CSR20) */ -+ volatile unsigned int cur_rx_buf_addr; /* 0x50 (CSR21) */ -+} DMA; -+ -+/* -+ * Struct private for the Sibyte. -+ * -+ * Elements are grouped so variables used by the tx handling goes -+ * together, and will go into the same cache lines etc. in order to -+ * avoid cache line contention between the rx and tx handling on SMP. -+ * -+ * Frequently accessed variables are put at the beginning of the -+ * struct to help the compiler generate better/shorter code. -+ */ -+struct ar231x_private { -+ struct net_device *dev; -+ int version; -+ u32 mb[2]; -+ -+ volatile ETHERNET_STRUCT *phy_regs; -+ volatile ETHERNET_STRUCT *eth_regs; -+ volatile DMA *dma_regs; -+ volatile u32 *int_regs; -+ struct ar231x_eth *cfg; -+ -+ spinlock_t lock; /* Serialise access to device */ -+ -+ /* -+ * RX and TX descriptors, must be adjacent -+ */ -+ ar231x_descr_t *rx_ring; -+ ar231x_descr_t *tx_ring; -+ -+ -+ struct sk_buff **rx_skb; -+ struct sk_buff **tx_skb; -+ -+ /* -+ * RX elements -+ */ -+ u32 rx_skbprd; -+ u32 cur_rx; -+ -+ /* -+ * TX elements -+ */ -+ u32 tx_prd; -+ u32 tx_csm; -+ -+ /* -+ * Misc elements -+ */ -+ char name[48]; -+ struct { -+ u32 address; -+ u32 length; -+ char *mapping; -+ } desc; -+ -+ -+ struct timer_list link_timer; -+ unsigned short phy; /* merlot phy = 1, samsung phy = 0x1f */ -+ unsigned short mac; -+ unsigned short link; /* 0 - link down, 1 - link up */ -+ u16 phyData; -+ -+ struct tasklet_struct rx_tasklet; -+ int unloading; -+ -+ struct phy_device *phy_dev; -+ struct mii_bus *mii_bus; -+ int oldduplex; -+}; -+ -+ -+/* -+ * Prototypes -+ */ -+static int ar231x_init(struct net_device *dev); -+#ifdef TX_TIMEOUT -+static void ar231x_tx_timeout(struct net_device *dev); -+#endif -+static int ar231x_restart(struct net_device *dev); -+static void ar231x_load_rx_ring(struct net_device *dev, int bufs); -+static irqreturn_t ar231x_interrupt(int irq, void *dev_id); -+static int ar231x_open(struct net_device *dev); -+static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev); -+static int ar231x_close(struct net_device *dev); -+static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr, -+ int cmd); -+static void ar231x_init_cleanup(struct net_device *dev); -+static int ar231x_setup_timer(struct net_device *dev); -+static void ar231x_link_timer_fn(unsigned long data); -+static void ar231x_check_link(struct net_device *dev); -+#endif /* _AR2313_H_ */ -diff -Nur linux-2.6.39-rc7.orig/drivers/watchdog/Kconfig linux-2.6.39-rc7/drivers/watchdog/Kconfig ---- linux-2.6.39-rc7.orig/drivers/watchdog/Kconfig 2011-05-10 04:33:54.000000000 +0200 -+++ linux-2.6.39-rc7/drivers/watchdog/Kconfig 2011-05-15 21:34:57.000000000 +0200 -@@ -990,6 +990,12 @@ - To compile this driver as a loadable module, choose M here. - The module will be called bcm63xx_wdt. - -+config ATHEROS_WDT -+ tristate "Atheros wisoc Watchdog Timer" -+ depends on ATHEROS_AR231X -+ help -+ Hardware driver for the Atheros wisoc Watchdog Timer. -+ - # PARISC Architecture - - # POWERPC Architecture -diff -Nur linux-2.6.39-rc7.orig/drivers/watchdog/Makefile linux-2.6.39-rc7/drivers/watchdog/Makefile ---- linux-2.6.39-rc7.orig/drivers/watchdog/Makefile 2011-05-10 04:33:54.000000000 +0200 -+++ linux-2.6.39-rc7/drivers/watchdog/Makefile 2011-05-15 21:34:57.000000000 +0200 -@@ -120,6 +120,7 @@ - obj-$(CONFIG_PNX833X_WDT) += pnx833x_wdt.o - obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o - obj-$(CONFIG_AR7_WDT) += ar7_wdt.o -+obj-$(CONFIG_ATHEROS_WDT) += ar2315-wtd.o - obj-$(CONFIG_TXX9_WDT) += txx9wdt.o - obj-$(CONFIG_OCTEON_WDT) += octeon-wdt.o - octeon-wdt-y := octeon-wdt-main.o octeon-wdt-nmi.o -diff -Nur linux-2.6.39-rc7.orig/drivers/watchdog/ar2315-wtd.c linux-2.6.39-rc7/drivers/watchdog/ar2315-wtd.c ---- linux-2.6.39-rc7.orig/drivers/watchdog/ar2315-wtd.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.39-rc7/drivers/watchdog/ar2315-wtd.c 2011-05-15 21:34:57.000000000 +0200 -@@ -0,0 +1,200 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ * -+ * Copyright (C) 2008 John Crispin -+ * Based on EP93xx and ifxmips wdt driver -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define CLOCK_RATE 40000000 -+#define HEARTBEAT(x) (x < 1 || x > 90)?(20):(x) -+ -+static int wdt_timeout = 20; -+static int started = 0; -+static int in_use = 0; -+ -+static void -+ar2315_wdt_enable(void) -+{ -+ ar231x_write_reg(AR2315_WD, wdt_timeout * CLOCK_RATE); -+ ar231x_write_reg(AR2315_ISR, 0x80); -+} -+ -+static ssize_t -+ar2315_wdt_write(struct file *file, const char __user *data, size_t len, loff_t *ppos) -+{ -+ if(len) -+ ar2315_wdt_enable(); -+ return len; -+} -+ -+static int -+ar2315_wdt_open(struct inode *inode, struct file *file) -+{ -+ if(in_use) -+ return -EBUSY; -+ ar2315_wdt_enable(); -+ in_use = started = 1; -+ return nonseekable_open(inode, file); -+} -+ -+static int -+ar2315_wdt_release(struct inode *inode, struct file *file) -+{ -+ in_use = 0; -+ return 0; -+} -+ -+static irqreturn_t -+ar2315_wdt_interrupt(int irq, void *dev_id) -+{ -+ if(started) -+ { -+ printk(KERN_CRIT "watchdog expired, rebooting system\n"); -+ emergency_restart(); -+ } else { -+ ar231x_write_reg(AR2315_WDC, 0); -+ ar231x_write_reg(AR2315_WD, 0); -+ ar231x_write_reg(AR2315_ISR, 0x80); -+ } -+ return IRQ_HANDLED; -+} -+ -+static struct watchdog_info ident = { -+ .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, -+ .identity = "ar2315 Watchdog", -+}; -+ -+static int -+ar2315_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) -+{ -+ int new_wdt_timeout; -+ int ret = -ENOIOCTLCMD; -+ -+ switch(cmd) -+ { -+ case WDIOC_GETSUPPORT: -+ ret = copy_to_user((struct watchdog_info __user *)arg, &ident, sizeof(ident)) ? -EFAULT : 0; -+ break; -+ -+ case WDIOC_KEEPALIVE: -+ ar2315_wdt_enable(); -+ ret = 0; -+ break; -+ -+ case WDIOC_SETTIMEOUT: -+ if((ret = get_user(new_wdt_timeout, (int __user *)arg))) -+ break; -+ wdt_timeout = HEARTBEAT(new_wdt_timeout); -+ ar2315_wdt_enable(); -+ break; -+ -+ case WDIOC_GETTIMEOUT: -+ ret = put_user(wdt_timeout, (int __user *)arg); -+ break; -+ } -+ return ret; -+} -+ -+static struct file_operations ar2315_wdt_fops = { -+ .owner = THIS_MODULE, -+ .llseek = no_llseek, -+ .write = ar2315_wdt_write, -+ .unlocked_ioctl = ar2315_wdt_ioctl, -+ .open = ar2315_wdt_open, -+ .release = ar2315_wdt_release, -+}; -+ -+static struct miscdevice ar2315_wdt_miscdev = { -+ .minor = WATCHDOG_MINOR, -+ .name = "watchdog", -+ .fops = &ar2315_wdt_fops, -+}; -+ -+static int -+ar2315_wdt_probe(struct platform_device *dev) -+{ -+ int ret = 0; -+ -+ ar2315_wdt_enable(); -+ ret = request_irq(AR531X_MISC_IRQ_WATCHDOG, ar2315_wdt_interrupt, IRQF_DISABLED, "ar2315_wdt", NULL); -+ if(ret) -+ { -+ printk(KERN_ERR "ar2315wdt: failed to register inetrrupt\n"); -+ goto out; -+ } -+ -+ ret = misc_register(&ar2315_wdt_miscdev); -+ if(ret) -+ printk(KERN_ERR "ar2315wdt: failed to register miscdev\n"); -+ -+out: -+ return ret; -+} -+ -+static int -+ar2315_wdt_remove(struct platform_device *dev) -+{ -+ misc_deregister(&ar2315_wdt_miscdev); -+ free_irq(AR531X_MISC_IRQ_WATCHDOG, NULL); -+ return 0; -+} -+ -+static struct platform_driver ar2315_wdt_driver = { -+ .probe = ar2315_wdt_probe, -+ .remove = ar2315_wdt_remove, -+ .driver = { -+ .name = "ar2315_wdt", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init -+init_ar2315_wdt(void) -+{ -+ int ret = platform_driver_register(&ar2315_wdt_driver); -+ if(ret) -+ printk(KERN_INFO "ar2315_wdt: error registering platfom driver!"); -+ return ret; -+} -+ -+static void __exit -+exit_ar2315_wdt(void) -+{ -+ platform_driver_unregister(&ar2315_wdt_driver); -+} -+ -+module_init(init_ar2315_wdt); -+module_exit(exit_ar2315_wdt); diff --git a/target/linux/patches/3.0.8/gemalto.patch b/target/linux/patches/3.0.8/gemalto.patch deleted file mode 100644 index f3c223b5e..000000000 --- a/target/linux/patches/3.0.8/gemalto.patch +++ /dev/null @@ -1,11 +0,0 @@ -diff -Nur linux-2.6.36.orig/drivers/tty/serial/serial_cs.c linux-2.6.36/drivers/serial/serial_cs.c ---- linux-2.6.36.orig/drivers/tty/serial/serial_cs.c 2010-10-20 22:30:22.000000000 +0200 -+++ linux-2.6.36/drivers/tty/serial/serial_cs.c 2010-12-13 23:03:40.000000000 +0100 -@@ -794,6 +794,7 @@ - PCMCIA_DEVICE_MANF_CARD(0x0137, 0x0025), - PCMCIA_DEVICE_MANF_CARD(0x0137, 0x0045), - PCMCIA_DEVICE_MANF_CARD(0x0137, 0x0052), -+ PCMCIA_DEVICE_MANF_CARD(0x0157, 0x0100), /* Gemalto SCR */ - PCMCIA_DEVICE_MANF_CARD(0x016c, 0x0006), /* Psion 56K+Fax */ - PCMCIA_DEVICE_MANF_CARD(0x0200, 0x0001), /* MultiMobile */ - PCMCIA_DEVICE_PROD_ID134("ADV", "TECH", "COMpad-32/85", 0x67459937, 0x916d02ba, 0x8fbe92ae), diff --git a/target/linux/patches/3.0.8/mips-malta.patch b/target/linux/patches/3.0.8/mips-malta.patch deleted file mode 100644 index cc8789dca..000000000 --- a/target/linux/patches/3.0.8/mips-malta.patch +++ /dev/null @@ -1,135 +0,0 @@ -http://lkml.indiana.edu/hypermail/linux/kernel/1105.3/02199.html - -diff -Nur linux-2.6.39.orig/arch/mips/include/asm/smp-ops.h linux-2.6.39/arch/mips/include/asm/smp-ops.h ---- linux-2.6.39.orig/arch/mips/include/asm/smp-ops.h 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/arch/mips/include/asm/smp-ops.h 2011-08-29 04:39:03.360480881 +0200 -@@ -56,8 +56,43 @@ - - #endif /* !CONFIG_SMP */ - --extern struct plat_smp_ops up_smp_ops; --extern struct plat_smp_ops cmp_smp_ops; --extern struct plat_smp_ops vsmp_smp_ops; -+static inline int register_up_smp_ops(void) -+{ -+#ifdef CONFIG_SMP_UP -+ extern struct plat_smp_ops up_smp_ops; -+ -+ register_smp_ops(&up_smp_ops); -+ -+ return 0; -+#else -+ return -ENODEV; -+#endif -+} -+ -+static inline int register_cmp_smp_ops(void) -+{ -+#ifdef CONFIG_MIPS_CMP -+ extern struct plat_smp_ops cmp_smp_ops; -+ -+ register_smp_ops(&cmp_smp_ops); -+ -+ return 0; -+#else -+ return -ENODEV; -+#endif -+} -+ -+static inline int register_vsmp_smp_ops(void) -+{ -+#ifdef CONFIG_MIPS_MT_SMP -+ extern struct plat_smp_ops vsmp_smp_ops; -+ -+ register_smp_ops(&vsmp_smp_ops); -+ -+ return 0; -+#else -+ return -ENODEV; -+#endif -+} - - #endif /* __ASM_SMP_OPS_H */ -diff -Nur linux-2.6.39.orig/arch/mips/mipssim/sim_setup.c linux-2.6.39/arch/mips/mipssim/sim_setup.c ---- linux-2.6.39.orig/arch/mips/mipssim/sim_setup.c 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/arch/mips/mipssim/sim_setup.c 2011-08-29 04:39:03.390480572 +0200 -@@ -59,18 +59,17 @@ - - prom_meminit(); - --#ifdef CONFIG_MIPS_MT_SMP -- if (cpu_has_mipsmt) -- register_smp_ops(&vsmp_smp_ops); -- else -- register_smp_ops(&up_smp_ops); --#endif -+ if (cpu_has_mipsmt) { -+ if (!register_vsmp_smp_ops()) -+ return; -+ - #ifdef CONFIG_MIPS_MT_SMTC -- if (cpu_has_mipsmt) - register_smp_ops(&ssmtc_smp_ops); -- else -- register_smp_ops(&up_smp_ops); -+ return; - #endif -+ } -+ -+ register_up_smp_ops(); - } - - static void __init serial_init(void) -diff -Nur linux-2.6.39.orig/arch/mips/mti-malta/malta-init.c linux-2.6.39/arch/mips/mti-malta/malta-init.c ---- linux-2.6.39.orig/arch/mips/mti-malta/malta-init.c 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/arch/mips/mti-malta/malta-init.c 2011-08-29 04:39:03.700480601 +0200 -@@ -29,6 +29,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -358,15 +359,14 @@ - #ifdef CONFIG_SERIAL_8250_CONSOLE - console_config(); - #endif --#ifdef CONFIG_MIPS_CMP - /* Early detection of CMP support */ - if (gcmp_probe(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ)) -- register_smp_ops(&cmp_smp_ops); -- else --#endif --#ifdef CONFIG_MIPS_MT_SMP -- register_smp_ops(&vsmp_smp_ops); --#endif -+ if (!register_cmp_smp_ops()) -+ return; -+ -+ if (!register_vsmp_smp_ops()) -+ return; -+ - #ifdef CONFIG_MIPS_MT_SMTC - register_smp_ops(&msmtc_smp_ops); - #endif -diff -Nur linux-2.6.39.orig/arch/mips/pmc-sierra/msp71xx/msp_setup.c linux-2.6.39/arch/mips/pmc-sierra/msp71xx/msp_setup.c ---- linux-2.6.39.orig/arch/mips/pmc-sierra/msp71xx/msp_setup.c 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/arch/mips/pmc-sierra/msp71xx/msp_setup.c 2011-08-29 04:39:03.790480302 +0200 -@@ -228,13 +228,11 @@ - */ - msp_serial_setup(); - --#ifdef CONFIG_MIPS_MT_SMP -- register_smp_ops(&vsmp_smp_ops); --#endif -- -+ if (register_vsmp_smp_ops()) { - #ifdef CONFIG_MIPS_MT_SMTC -- register_smp_ops(&msp_smtc_smp_ops); -+ register_smp_ops(&msp_smtc_smp_ops); - #endif -+ } - - #ifdef CONFIG_PMCTWILED - /* diff --git a/target/linux/patches/3.0.8/mmc-host.patch b/target/linux/patches/3.0.8/mmc-host.patch deleted file mode 100644 index 3d0e37add..000000000 --- a/target/linux/patches/3.0.8/mmc-host.patch +++ /dev/null @@ -1,36 +0,0 @@ -diff -Nur linux-2.6.39-rc6.orig/drivers/mmc/host/Kconfig linux-2.6.39-rc6/drivers/mmc/host/Kconfig ---- linux-2.6.39-rc6.orig/drivers/mmc/host/Kconfig 2011-05-04 04:59:13.000000000 +0200 -+++ linux-2.6.39-rc6/drivers/mmc/host/Kconfig 2011-05-10 23:39:01.000000000 +0200 -@@ -253,13 +253,6 @@ - - If unsure, say N. - --choice -- prompt "Atmel SD/MMC Driver" -- depends on AVR32 || ARCH_AT91 -- default MMC_ATMELMCI if AVR32 -- help -- Choose which driver to use for the Atmel MCI Silicon -- - config MMC_AT91 - tristate "AT91 SD/MMC Card Interface support" - depends on ARCH_AT91 -@@ -268,18 +261,6 @@ - - If unsure, say N. - --config MMC_ATMELMCI -- tristate "Atmel Multimedia Card Interface support" -- depends on AVR32 || ARCH_AT91 -- help -- This selects the Atmel Multimedia Card Interface driver. If -- you have an AT32 (AVR32) or AT91 platform with a Multimedia -- Card slot, say Y or M here. -- -- If unsure, say N. -- --endchoice -- - config MMC_ATMELMCI_DMA - bool "Atmel MCI DMA support (EXPERIMENTAL)" - depends on MMC_ATMELMCI && (AVR32 || ARCH_AT91SAM9G45) && DMA_ENGINE && EXPERIMENTAL diff --git a/target/linux/patches/3.0.8/non-static.patch b/target/linux/patches/3.0.8/non-static.patch deleted file mode 100644 index a967703d0..000000000 --- a/target/linux/patches/3.0.8/non-static.patch +++ /dev/null @@ -1,33 +0,0 @@ -diff -Nur linux-2.6.39-rc6.orig/fs/namei.c linux-2.6.39-rc6/fs/namei.c ---- linux-2.6.39-rc6.orig/fs/namei.c 2011-05-04 04:59:13.000000000 +0200 -+++ linux-2.6.39-rc6/fs/namei.c 2011-05-05 11:30:14.000000000 +0200 -@@ -1769,7 +1769,7 @@ - * needs parent already locked. Doesn't follow mounts. - * SMP-safe. - */ --static struct dentry *lookup_hash(struct nameidata *nd) -+struct dentry *lookup_hash(struct nameidata *nd) - { - return __lookup_hash(&nd->last, nd->path.dentry, nd); - } -diff -Nur linux-2.6.39-rc6.orig/fs/splice.c linux-2.6.39-rc6/fs/splice.c ---- linux-2.6.39-rc6.orig/fs/splice.c 2011-05-04 04:59:13.000000000 +0200 -+++ linux-2.6.39-rc6/fs/splice.c 2011-05-05 11:31:04.000000000 +0200 -@@ -1081,7 +1081,7 @@ - /* - * Attempt to initiate a splice from pipe to file. - */ --static long do_splice_from(struct pipe_inode_info *pipe, struct file *out, -+long do_splice_from(struct pipe_inode_info *pipe, struct file *out, - loff_t *ppos, size_t len, unsigned int flags) - { - ssize_t (*splice_write)(struct pipe_inode_info *, struct file *, -@@ -1109,7 +1109,7 @@ - /* - * Attempt to initiate a splice from a file to a pipe. - */ --static long do_splice_to(struct file *in, loff_t *ppos, -+long do_splice_to(struct file *in, loff_t *ppos, - struct pipe_inode_info *pipe, size_t len, - unsigned int flags) - { diff --git a/target/linux/patches/3.0.8/ocf-20110720.patch b/target/linux/patches/3.0.8/ocf-20110720.patch deleted file mode 100644 index b5a257324..000000000 --- a/target/linux/patches/3.0.8/ocf-20110720.patch +++ /dev/null @@ -1,99170 +0,0 @@ -diff -Nur linux-3.0.4.orig/crypto/Kconfig linux-3.0.4/crypto/Kconfig ---- linux-3.0.4.orig/crypto/Kconfig 2011-08-29 22:56:30.000000000 +0200 -+++ linux-3.0.4/crypto/Kconfig 2011-10-17 04:36:27.356574299 +0200 -@@ -860,3 +860,6 @@ - source "drivers/crypto/Kconfig" - - endif # if CRYPTO -+ -+source "crypto/ocf/Kconfig" -+ -diff -Nur linux-3.0.4.orig/crypto/Kconfig.orig linux-3.0.4/crypto/Kconfig.orig ---- linux-3.0.4.orig/crypto/Kconfig.orig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/Kconfig.orig 2011-08-29 22:56:30.000000000 +0200 -@@ -0,0 +1,862 @@ -+# -+# Generic algorithms support -+# -+config XOR_BLOCKS -+ tristate -+ -+# -+# async_tx api: hardware offloaded memory transfer/transform support -+# -+source "crypto/async_tx/Kconfig" -+ -+# -+# Cryptographic API Configuration -+# -+menuconfig CRYPTO -+ tristate "Cryptographic API" -+ help -+ This option provides the core Cryptographic API. -+ -+if CRYPTO -+ -+comment "Crypto core or helper" -+ -+config CRYPTO_FIPS -+ bool "FIPS 200 compliance" -+ depends on CRYPTO_ANSI_CPRNG && !CRYPTO_MANAGER_DISABLE_TESTS -+ help -+ This options enables the fips boot option which is -+ required if you want to system to operate in a FIPS 200 -+ certification. You should say no unless you know what -+ this is. -+ -+config CRYPTO_ALGAPI -+ tristate -+ select CRYPTO_ALGAPI2 -+ help -+ This option provides the API for cryptographic algorithms. -+ -+config CRYPTO_ALGAPI2 -+ tristate -+ -+config CRYPTO_AEAD -+ tristate -+ select CRYPTO_AEAD2 -+ select CRYPTO_ALGAPI -+ -+config CRYPTO_AEAD2 -+ tristate -+ select CRYPTO_ALGAPI2 -+ -+config CRYPTO_BLKCIPHER -+ tristate -+ select CRYPTO_BLKCIPHER2 -+ select CRYPTO_ALGAPI -+ -+config CRYPTO_BLKCIPHER2 -+ tristate -+ select CRYPTO_ALGAPI2 -+ select CRYPTO_RNG2 -+ select CRYPTO_WORKQUEUE -+ -+config CRYPTO_HASH -+ tristate -+ select CRYPTO_HASH2 -+ select CRYPTO_ALGAPI -+ -+config CRYPTO_HASH2 -+ tristate -+ select CRYPTO_ALGAPI2 -+ -+config CRYPTO_RNG -+ tristate -+ select CRYPTO_RNG2 -+ select CRYPTO_ALGAPI -+ -+config CRYPTO_RNG2 -+ tristate -+ select CRYPTO_ALGAPI2 -+ -+config CRYPTO_PCOMP -+ tristate -+ select CRYPTO_PCOMP2 -+ select CRYPTO_ALGAPI -+ -+config CRYPTO_PCOMP2 -+ tristate -+ select CRYPTO_ALGAPI2 -+ -+config CRYPTO_MANAGER -+ tristate "Cryptographic algorithm manager" -+ select CRYPTO_MANAGER2 -+ help -+ Create default cryptographic template instantiations such as -+ cbc(aes). -+ -+config CRYPTO_MANAGER2 -+ def_tristate CRYPTO_MANAGER || (CRYPTO_MANAGER!=n && CRYPTO_ALGAPI=y) -+ select CRYPTO_AEAD2 -+ select CRYPTO_HASH2 -+ select CRYPTO_BLKCIPHER2 -+ select CRYPTO_PCOMP2 -+ -+config CRYPTO_MANAGER_DISABLE_TESTS -+ bool "Disable run-time self tests" -+ default y -+ depends on CRYPTO_MANAGER2 -+ help -+ Disable run-time self tests that normally take place at -+ algorithm registration. -+ -+config CRYPTO_GF128MUL -+ tristate "GF(2^128) multiplication functions (EXPERIMENTAL)" -+ help -+ Efficient table driven implementation of multiplications in the -+ field GF(2^128). This is needed by some cypher modes. This -+ option will be selected automatically if you select such a -+ cipher mode. Only select this option by hand if you expect to load -+ an external module that requires these functions. -+ -+config CRYPTO_NULL -+ tristate "Null algorithms" -+ select CRYPTO_ALGAPI -+ select CRYPTO_BLKCIPHER -+ select CRYPTO_HASH -+ help -+ These are 'Null' algorithms, used by IPsec, which do nothing. -+ -+config CRYPTO_PCRYPT -+ tristate "Parallel crypto engine (EXPERIMENTAL)" -+ depends on SMP && EXPERIMENTAL -+ select PADATA -+ select CRYPTO_MANAGER -+ select CRYPTO_AEAD -+ help -+ This converts an arbitrary crypto algorithm into a parallel -+ algorithm that executes in kernel threads. -+ -+config CRYPTO_WORKQUEUE -+ tristate -+ -+config CRYPTO_CRYPTD -+ tristate "Software async crypto daemon" -+ select CRYPTO_BLKCIPHER -+ select CRYPTO_HASH -+ select CRYPTO_MANAGER -+ select CRYPTO_WORKQUEUE -+ help -+ This is a generic software asynchronous crypto daemon that -+ converts an arbitrary synchronous software crypto algorithm -+ into an asynchronous algorithm that executes in a kernel thread. -+ -+config CRYPTO_AUTHENC -+ tristate "Authenc support" -+ select CRYPTO_AEAD -+ select CRYPTO_BLKCIPHER -+ select CRYPTO_MANAGER -+ select CRYPTO_HASH -+ help -+ Authenc: Combined mode wrapper for IPsec. -+ This is required for IPSec. -+ -+config CRYPTO_TEST -+ tristate "Testing module" -+ depends on m -+ select CRYPTO_MANAGER -+ help -+ Quick & dirty crypto test module. -+ -+comment "Authenticated Encryption with Associated Data" -+ -+config CRYPTO_CCM -+ tristate "CCM support" -+ select CRYPTO_CTR -+ select CRYPTO_AEAD -+ help -+ Support for Counter with CBC MAC. Required for IPsec. -+ -+config CRYPTO_GCM -+ tristate "GCM/GMAC support" -+ select CRYPTO_CTR -+ select CRYPTO_AEAD -+ select CRYPTO_GHASH -+ help -+ Support for Galois/Counter Mode (GCM) and Galois Message -+ Authentication Code (GMAC). Required for IPSec. -+ -+config CRYPTO_SEQIV -+ tristate "Sequence Number IV Generator" -+ select CRYPTO_AEAD -+ select CRYPTO_BLKCIPHER -+ select CRYPTO_RNG -+ help -+ This IV generator generates an IV based on a sequence number by -+ xoring it with a salt. This algorithm is mainly useful for CTR -+ -+comment "Block modes" -+ -+config CRYPTO_CBC -+ tristate "CBC support" -+ select CRYPTO_BLKCIPHER -+ select CRYPTO_MANAGER -+ help -+ CBC: Cipher Block Chaining mode -+ This block cipher algorithm is required for IPSec. -+ -+config CRYPTO_CTR -+ tristate "CTR support" -+ select CRYPTO_BLKCIPHER -+ select CRYPTO_SEQIV -+ select CRYPTO_MANAGER -+ help -+ CTR: Counter mode -+ This block cipher algorithm is required for IPSec. -+ -+config CRYPTO_CTS -+ tristate "CTS support" -+ select CRYPTO_BLKCIPHER -+ help -+ CTS: Cipher Text Stealing -+ This is the Cipher Text Stealing mode as described by -+ Section 8 of rfc2040 and referenced by rfc3962. -+ (rfc3962 includes errata information in its Appendix A) -+ This mode is required for Kerberos gss mechanism support -+ for AES encryption. -+ -+config CRYPTO_ECB -+ tristate "ECB support" -+ select CRYPTO_BLKCIPHER -+ select CRYPTO_MANAGER -+ help -+ ECB: Electronic CodeBook mode -+ This is the simplest block cipher algorithm. It simply encrypts -+ the input block by block. -+ -+config CRYPTO_LRW -+ tristate "LRW support (EXPERIMENTAL)" -+ depends on EXPERIMENTAL -+ select CRYPTO_BLKCIPHER -+ select CRYPTO_MANAGER -+ select CRYPTO_GF128MUL -+ help -+ LRW: Liskov Rivest Wagner, a tweakable, non malleable, non movable -+ narrow block cipher mode for dm-crypt. Use it with cipher -+ specification string aes-lrw-benbi, the key must be 256, 320 or 384. -+ The first 128, 192 or 256 bits in the key are used for AES and the -+ rest is used to tie each cipher block to its logical position. -+ -+config CRYPTO_PCBC -+ tristate "PCBC support" -+ select CRYPTO_BLKCIPHER -+ select CRYPTO_MANAGER -+ help -+ PCBC: Propagating Cipher Block Chaining mode -+ This block cipher algorithm is required for RxRPC. -+ -+config CRYPTO_XTS -+ tristate "XTS support (EXPERIMENTAL)" -+ depends on EXPERIMENTAL -+ select CRYPTO_BLKCIPHER -+ select CRYPTO_MANAGER -+ select CRYPTO_GF128MUL -+ help -+ XTS: IEEE1619/D16 narrow block cipher use with aes-xts-plain, -+ key size 256, 384 or 512 bits. This implementation currently -+ can't handle a sectorsize which is not a multiple of 16 bytes. -+ -+comment "Hash modes" -+ -+config CRYPTO_HMAC -+ tristate "HMAC support" -+ select CRYPTO_HASH -+ select CRYPTO_MANAGER -+ help -+ HMAC: Keyed-Hashing for Message Authentication (RFC2104). -+ This is required for IPSec. -+ -+config CRYPTO_XCBC -+ tristate "XCBC support" -+ depends on EXPERIMENTAL -+ select CRYPTO_HASH -+ select CRYPTO_MANAGER -+ help -+ XCBC: Keyed-Hashing with encryption algorithm -+ http://www.ietf.org/rfc/rfc3566.txt -+ http://csrc.nist.gov/encryption/modes/proposedmodes/ -+ xcbc-mac/xcbc-mac-spec.pdf -+ -+config CRYPTO_VMAC -+ tristate "VMAC support" -+ depends on EXPERIMENTAL -+ select CRYPTO_HASH -+ select CRYPTO_MANAGER -+ help -+ VMAC is a message authentication algorithm designed for -+ very high speed on 64-bit architectures. -+ -+ See also: -+ -+ -+comment "Digest" -+ -+config CRYPTO_CRC32C -+ tristate "CRC32c CRC algorithm" -+ select CRYPTO_HASH -+ help -+ Castagnoli, et al Cyclic Redundancy-Check Algorithm. Used -+ by iSCSI for header and data digests and by others. -+ See Castagnoli93. Module will be crc32c. -+ -+config CRYPTO_CRC32C_INTEL -+ tristate "CRC32c INTEL hardware acceleration" -+ depends on X86 -+ select CRYPTO_HASH -+ help -+ In Intel processor with SSE4.2 supported, the processor will -+ support CRC32C implementation using hardware accelerated CRC32 -+ instruction. This option will create 'crc32c-intel' module, -+ which will enable any routine to use the CRC32 instruction to -+ gain performance compared with software implementation. -+ Module will be crc32c-intel. -+ -+config CRYPTO_GHASH -+ tristate "GHASH digest algorithm" -+ select CRYPTO_SHASH -+ select CRYPTO_GF128MUL -+ help -+ GHASH is message digest algorithm for GCM (Galois/Counter Mode). -+ -+config CRYPTO_MD4 -+ tristate "MD4 digest algorithm" -+ select CRYPTO_HASH -+ help -+ MD4 message digest algorithm (RFC1320). -+ -+config CRYPTO_MD5 -+ tristate "MD5 digest algorithm" -+ select CRYPTO_HASH -+ help -+ MD5 message digest algorithm (RFC1321). -+ -+config CRYPTO_MICHAEL_MIC -+ tristate "Michael MIC keyed digest algorithm" -+ select CRYPTO_HASH -+ help -+ Michael MIC is used for message integrity protection in TKIP -+ (IEEE 802.11i). This algorithm is required for TKIP, but it -+ should not be used for other purposes because of the weakness -+ of the algorithm. -+ -+config CRYPTO_RMD128 -+ tristate "RIPEMD-128 digest algorithm" -+ select CRYPTO_HASH -+ help -+ RIPEMD-128 (ISO/IEC 10118-3:2004). -+ -+ RIPEMD-128 is a 128-bit cryptographic hash function. It should only -+ to be used as a secure replacement for RIPEMD. For other use cases -+ RIPEMD-160 should be used. -+ -+ Developed by Hans Dobbertin, Antoon Bosselaers and Bart Preneel. -+ See -+ -+config CRYPTO_RMD160 -+ tristate "RIPEMD-160 digest algorithm" -+ select CRYPTO_HASH -+ help -+ RIPEMD-160 (ISO/IEC 10118-3:2004). -+ -+ RIPEMD-160 is a 160-bit cryptographic hash function. It is intended -+ to be used as a secure replacement for the 128-bit hash functions -+ MD4, MD5 and it's predecessor RIPEMD -+ (not to be confused with RIPEMD-128). -+ -+ It's speed is comparable to SHA1 and there are no known attacks -+ against RIPEMD-160. -+ -+ Developed by Hans Dobbertin, Antoon Bosselaers and Bart Preneel. -+ See -+ -+config CRYPTO_RMD256 -+ tristate "RIPEMD-256 digest algorithm" -+ select CRYPTO_HASH -+ help -+ RIPEMD-256 is an optional extension of RIPEMD-128 with a -+ 256 bit hash. It is intended for applications that require -+ longer hash-results, without needing a larger security level -+ (than RIPEMD-128). -+ -+ Developed by Hans Dobbertin, Antoon Bosselaers and Bart Preneel. -+ See -+ -+config CRYPTO_RMD320 -+ tristate "RIPEMD-320 digest algorithm" -+ select CRYPTO_HASH -+ help -+ RIPEMD-320 is an optional extension of RIPEMD-160 with a -+ 320 bit hash. It is intended for applications that require -+ longer hash-results, without needing a larger security level -+ (than RIPEMD-160). -+ -+ Developed by Hans Dobbertin, Antoon Bosselaers and Bart Preneel. -+ See -+ -+config CRYPTO_SHA1 -+ tristate "SHA1 digest algorithm" -+ select CRYPTO_HASH -+ help -+ SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2). -+ -+config CRYPTO_SHA256 -+ tristate "SHA224 and SHA256 digest algorithm" -+ select CRYPTO_HASH -+ help -+ SHA256 secure hash standard (DFIPS 180-2). -+ -+ This version of SHA implements a 256 bit hash with 128 bits of -+ security against collision attacks. -+ -+ This code also includes SHA-224, a 224 bit hash with 112 bits -+ of security against collision attacks. -+ -+config CRYPTO_SHA512 -+ tristate "SHA384 and SHA512 digest algorithms" -+ select CRYPTO_HASH -+ help -+ SHA512 secure hash standard (DFIPS 180-2). -+ -+ This version of SHA implements a 512 bit hash with 256 bits of -+ security against collision attacks. -+ -+ This code also includes SHA-384, a 384 bit hash with 192 bits -+ of security against collision attacks. -+ -+config CRYPTO_TGR192 -+ tristate "Tiger digest algorithms" -+ select CRYPTO_HASH -+ help -+ Tiger hash algorithm 192, 160 and 128-bit hashes -+ -+ Tiger is a hash function optimized for 64-bit processors while -+ still having decent performance on 32-bit processors. -+ Tiger was developed by Ross Anderson and Eli Biham. -+ -+ See also: -+ . -+ -+config CRYPTO_WP512 -+ tristate "Whirlpool digest algorithms" -+ select CRYPTO_HASH -+ help -+ Whirlpool hash algorithm 512, 384 and 256-bit hashes -+ -+ Whirlpool-512 is part of the NESSIE cryptographic primitives. -+ Whirlpool will be part of the ISO/IEC 10118-3:2003(E) standard -+ -+ See also: -+ -+ -+config CRYPTO_GHASH_CLMUL_NI_INTEL -+ tristate "GHASH digest algorithm (CLMUL-NI accelerated)" -+ depends on (X86 || UML_X86) && 64BIT -+ select CRYPTO_SHASH -+ select CRYPTO_CRYPTD -+ help -+ GHASH is message digest algorithm for GCM (Galois/Counter Mode). -+ The implementation is accelerated by CLMUL-NI of Intel. -+ -+comment "Ciphers" -+ -+config CRYPTO_AES -+ tristate "AES cipher algorithms" -+ select CRYPTO_ALGAPI -+ help -+ AES cipher algorithms (FIPS-197). AES uses the Rijndael -+ algorithm. -+ -+ Rijndael appears to be consistently a very good performer in -+ both hardware and software across a wide range of computing -+ environments regardless of its use in feedback or non-feedback -+ modes. Its key setup time is excellent, and its key agility is -+ good. Rijndael's very low memory requirements make it very well -+ suited for restricted-space environments, in which it also -+ demonstrates excellent performance. Rijndael's operations are -+ among the easiest to defend against power and timing attacks. -+ -+ The AES specifies three key sizes: 128, 192 and 256 bits -+ -+ See for more information. -+ -+config CRYPTO_AES_586 -+ tristate "AES cipher algorithms (i586)" -+ depends on (X86 || UML_X86) && !64BIT -+ select CRYPTO_ALGAPI -+ select CRYPTO_AES -+ help -+ AES cipher algorithms (FIPS-197). AES uses the Rijndael -+ algorithm. -+ -+ Rijndael appears to be consistently a very good performer in -+ both hardware and software across a wide range of computing -+ environments regardless of its use in feedback or non-feedback -+ modes. Its key setup time is excellent, and its key agility is -+ good. Rijndael's very low memory requirements make it very well -+ suited for restricted-space environments, in which it also -+ demonstrates excellent performance. Rijndael's operations are -+ among the easiest to defend against power and timing attacks. -+ -+ The AES specifies three key sizes: 128, 192 and 256 bits -+ -+ See for more information. -+ -+config CRYPTO_AES_X86_64 -+ tristate "AES cipher algorithms (x86_64)" -+ depends on (X86 || UML_X86) && 64BIT -+ select CRYPTO_ALGAPI -+ select CRYPTO_AES -+ help -+ AES cipher algorithms (FIPS-197). AES uses the Rijndael -+ algorithm. -+ -+ Rijndael appears to be consistently a very good performer in -+ both hardware and software across a wide range of computing -+ environments regardless of its use in feedback or non-feedback -+ modes. Its key setup time is excellent, and its key agility is -+ good. Rijndael's very low memory requirements make it very well -+ suited for restricted-space environments, in which it also -+ demonstrates excellent performance. Rijndael's operations are -+ among the easiest to defend against power and timing attacks. -+ -+ The AES specifies three key sizes: 128, 192 and 256 bits -+ -+ See for more information. -+ -+config CRYPTO_AES_NI_INTEL -+ tristate "AES cipher algorithms (AES-NI)" -+ depends on (X86 || UML_X86) -+ select CRYPTO_AES_X86_64 if 64BIT -+ select CRYPTO_AES_586 if !64BIT -+ select CRYPTO_CRYPTD -+ select CRYPTO_ALGAPI -+ help -+ Use Intel AES-NI instructions for AES algorithm. -+ -+ AES cipher algorithms (FIPS-197). AES uses the Rijndael -+ algorithm. -+ -+ Rijndael appears to be consistently a very good performer in -+ both hardware and software across a wide range of computing -+ environments regardless of its use in feedback or non-feedback -+ modes. Its key setup time is excellent, and its key agility is -+ good. Rijndael's very low memory requirements make it very well -+ suited for restricted-space environments, in which it also -+ demonstrates excellent performance. Rijndael's operations are -+ among the easiest to defend against power and timing attacks. -+ -+ The AES specifies three key sizes: 128, 192 and 256 bits -+ -+ See for more information. -+ -+ In addition to AES cipher algorithm support, the acceleration -+ for some popular block cipher mode is supported too, including -+ ECB, CBC, LRW, PCBC, XTS. The 64 bit version has additional -+ acceleration for CTR. -+ -+config CRYPTO_ANUBIS -+ tristate "Anubis cipher algorithm" -+ select CRYPTO_ALGAPI -+ help -+ Anubis cipher algorithm. -+ -+ Anubis is a variable key length cipher which can use keys from -+ 128 bits to 320 bits in length. It was evaluated as a entrant -+ in the NESSIE competition. -+ -+ See also: -+ -+ -+ -+config CRYPTO_ARC4 -+ tristate "ARC4 cipher algorithm" -+ select CRYPTO_ALGAPI -+ help -+ ARC4 cipher algorithm. -+ -+ ARC4 is a stream cipher using keys ranging from 8 bits to 2048 -+ bits in length. This algorithm is required for driver-based -+ WEP, but it should not be for other purposes because of the -+ weakness of the algorithm. -+ -+config CRYPTO_BLOWFISH -+ tristate "Blowfish cipher algorithm" -+ select CRYPTO_ALGAPI -+ help -+ Blowfish cipher algorithm, by Bruce Schneier. -+ -+ This is a variable key length cipher which can use keys from 32 -+ bits to 448 bits in length. It's fast, simple and specifically -+ designed for use on "large microprocessors". -+ -+ See also: -+ -+ -+config CRYPTO_CAMELLIA -+ tristate "Camellia cipher algorithms" -+ depends on CRYPTO -+ select CRYPTO_ALGAPI -+ help -+ Camellia cipher algorithms module. -+ -+ Camellia is a symmetric key block cipher developed jointly -+ at NTT and Mitsubishi Electric Corporation. -+ -+ The Camellia specifies three key sizes: 128, 192 and 256 bits. -+ -+ See also: -+ -+ -+config CRYPTO_CAST5 -+ tristate "CAST5 (CAST-128) cipher algorithm" -+ select CRYPTO_ALGAPI -+ help -+ The CAST5 encryption algorithm (synonymous with CAST-128) is -+ described in RFC2144. -+ -+config CRYPTO_CAST6 -+ tristate "CAST6 (CAST-256) cipher algorithm" -+ select CRYPTO_ALGAPI -+ help -+ The CAST6 encryption algorithm (synonymous with CAST-256) is -+ described in RFC2612. -+ -+config CRYPTO_DES -+ tristate "DES and Triple DES EDE cipher algorithms" -+ select CRYPTO_ALGAPI -+ help -+ DES cipher algorithm (FIPS 46-2), and Triple DES EDE (FIPS 46-3). -+ -+config CRYPTO_FCRYPT -+ tristate "FCrypt cipher algorithm" -+ select CRYPTO_ALGAPI -+ select CRYPTO_BLKCIPHER -+ help -+ FCrypt algorithm used by RxRPC. -+ -+config CRYPTO_KHAZAD -+ tristate "Khazad cipher algorithm" -+ select CRYPTO_ALGAPI -+ help -+ Khazad cipher algorithm. -+ -+ Khazad was a finalist in the initial NESSIE competition. It is -+ an algorithm optimized for 64-bit processors with good performance -+ on 32-bit processors. Khazad uses an 128 bit key size. -+ -+ See also: -+ -+ -+config CRYPTO_SALSA20 -+ tristate "Salsa20 stream cipher algorithm (EXPERIMENTAL)" -+ depends on EXPERIMENTAL -+ select CRYPTO_BLKCIPHER -+ help -+ Salsa20 stream cipher algorithm. -+ -+ Salsa20 is a stream cipher submitted to eSTREAM, the ECRYPT -+ Stream Cipher Project. See -+ -+ The Salsa20 stream cipher algorithm is designed by Daniel J. -+ Bernstein . See -+ -+config CRYPTO_SALSA20_586 -+ tristate "Salsa20 stream cipher algorithm (i586) (EXPERIMENTAL)" -+ depends on (X86 || UML_X86) && !64BIT -+ depends on EXPERIMENTAL -+ select CRYPTO_BLKCIPHER -+ help -+ Salsa20 stream cipher algorithm. -+ -+ Salsa20 is a stream cipher submitted to eSTREAM, the ECRYPT -+ Stream Cipher Project. See -+ -+ The Salsa20 stream cipher algorithm is designed by Daniel J. -+ Bernstein . See -+ -+config CRYPTO_SALSA20_X86_64 -+ tristate "Salsa20 stream cipher algorithm (x86_64) (EXPERIMENTAL)" -+ depends on (X86 || UML_X86) && 64BIT -+ depends on EXPERIMENTAL -+ select CRYPTO_BLKCIPHER -+ help -+ Salsa20 stream cipher algorithm. -+ -+ Salsa20 is a stream cipher submitted to eSTREAM, the ECRYPT -+ Stream Cipher Project. See -+ -+ The Salsa20 stream cipher algorithm is designed by Daniel J. -+ Bernstein . See -+ -+config CRYPTO_SEED -+ tristate "SEED cipher algorithm" -+ select CRYPTO_ALGAPI -+ help -+ SEED cipher algorithm (RFC4269). -+ -+ SEED is a 128-bit symmetric key block cipher that has been -+ developed by KISA (Korea Information Security Agency) as a -+ national standard encryption algorithm of the Republic of Korea. -+ It is a 16 round block cipher with the key size of 128 bit. -+ -+ See also: -+ -+ -+config CRYPTO_SERPENT -+ tristate "Serpent cipher algorithm" -+ select CRYPTO_ALGAPI -+ help -+ Serpent cipher algorithm, by Anderson, Biham & Knudsen. -+ -+ Keys are allowed to be from 0 to 256 bits in length, in steps -+ of 8 bits. Also includes the 'Tnepres' algorithm, a reversed -+ variant of Serpent for compatibility with old kerneli.org code. -+ -+ See also: -+ -+ -+config CRYPTO_TEA -+ tristate "TEA, XTEA and XETA cipher algorithms" -+ select CRYPTO_ALGAPI -+ help -+ TEA cipher algorithm. -+ -+ Tiny Encryption Algorithm is a simple cipher that uses -+ many rounds for security. It is very fast and uses -+ little memory. -+ -+ Xtendend Tiny Encryption Algorithm is a modification to -+ the TEA algorithm to address a potential key weakness -+ in the TEA algorithm. -+ -+ Xtendend Encryption Tiny Algorithm is a mis-implementation -+ of the XTEA algorithm for compatibility purposes. -+ -+config CRYPTO_TWOFISH -+ tristate "Twofish cipher algorithm" -+ select CRYPTO_ALGAPI -+ select CRYPTO_TWOFISH_COMMON -+ help -+ Twofish cipher algorithm. -+ -+ Twofish was submitted as an AES (Advanced Encryption Standard) -+ candidate cipher by researchers at CounterPane Systems. It is a -+ 16 round block cipher supporting key sizes of 128, 192, and 256 -+ bits. -+ -+ See also: -+ -+ -+config CRYPTO_TWOFISH_COMMON -+ tristate -+ help -+ Common parts of the Twofish cipher algorithm shared by the -+ generic c and the assembler implementations. -+ -+config CRYPTO_TWOFISH_586 -+ tristate "Twofish cipher algorithms (i586)" -+ depends on (X86 || UML_X86) && !64BIT -+ select CRYPTO_ALGAPI -+ select CRYPTO_TWOFISH_COMMON -+ help -+ Twofish cipher algorithm. -+ -+ Twofish was submitted as an AES (Advanced Encryption Standard) -+ candidate cipher by researchers at CounterPane Systems. It is a -+ 16 round block cipher supporting key sizes of 128, 192, and 256 -+ bits. -+ -+ See also: -+ -+ -+config CRYPTO_TWOFISH_X86_64 -+ tristate "Twofish cipher algorithm (x86_64)" -+ depends on (X86 || UML_X86) && 64BIT -+ select CRYPTO_ALGAPI -+ select CRYPTO_TWOFISH_COMMON -+ help -+ Twofish cipher algorithm (x86_64). -+ -+ Twofish was submitted as an AES (Advanced Encryption Standard) -+ candidate cipher by researchers at CounterPane Systems. It is a -+ 16 round block cipher supporting key sizes of 128, 192, and 256 -+ bits. -+ -+ See also: -+ -+ -+comment "Compression" -+ -+config CRYPTO_DEFLATE -+ tristate "Deflate compression algorithm" -+ select CRYPTO_ALGAPI -+ select ZLIB_INFLATE -+ select ZLIB_DEFLATE -+ help -+ This is the Deflate algorithm (RFC1951), specified for use in -+ IPSec with the IPCOMP protocol (RFC3173, RFC2394). -+ -+ You will most probably want this if using IPSec. -+ -+config CRYPTO_ZLIB -+ tristate "Zlib compression algorithm" -+ select CRYPTO_PCOMP -+ select ZLIB_INFLATE -+ select ZLIB_DEFLATE -+ select NLATTR -+ help -+ This is the zlib algorithm. -+ -+config CRYPTO_LZO -+ tristate "LZO compression algorithm" -+ select CRYPTO_ALGAPI -+ select LZO_COMPRESS -+ select LZO_DECOMPRESS -+ help -+ This is the LZO algorithm. -+ -+comment "Random Number Generation" -+ -+config CRYPTO_ANSI_CPRNG -+ tristate "Pseudo Random Number Generation for Cryptographic modules" -+ default m -+ select CRYPTO_AES -+ select CRYPTO_RNG -+ help -+ This option enables the generic pseudo random number generator -+ for cryptographic modules. Uses the Algorithm specified in -+ ANSI X9.31 A.2.4. Note that this option must be enabled if -+ CRYPTO_FIPS is selected -+ -+config CRYPTO_USER_API -+ tristate -+ -+config CRYPTO_USER_API_HASH -+ tristate "User-space interface for hash algorithms" -+ depends on NET -+ select CRYPTO_HASH -+ select CRYPTO_USER_API -+ help -+ This option enables the user-spaces interface for hash -+ algorithms. -+ -+config CRYPTO_USER_API_SKCIPHER -+ tristate "User-space interface for symmetric key cipher algorithms" -+ depends on NET -+ select CRYPTO_BLKCIPHER -+ select CRYPTO_USER_API -+ help -+ This option enables the user-spaces interface for symmetric -+ key cipher algorithms. -+ -+source "drivers/crypto/Kconfig" -+ -+endif # if CRYPTO -diff -Nur linux-3.0.4.orig/crypto/Makefile linux-3.0.4/crypto/Makefile ---- linux-3.0.4.orig/crypto/Makefile 2011-08-29 22:56:30.000000000 +0200 -+++ linux-3.0.4/crypto/Makefile 2011-10-17 04:36:27.356574299 +0200 -@@ -89,6 +89,8 @@ - obj-$(CONFIG_CRYPTO_USER_API_HASH) += algif_hash.o - obj-$(CONFIG_CRYPTO_USER_API_SKCIPHER) += algif_skcipher.o - -+obj-$(CONFIG_OCF_OCF) += ocf/ -+ - # - # generic algorithms and the async_tx api - # -diff -Nur linux-3.0.4.orig/crypto/ocf/Config.in linux-3.0.4/crypto/ocf/Config.in ---- linux-3.0.4.orig/crypto/ocf/Config.in 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/Config.in 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,38 @@ -+############################################################################# -+ -+mainmenu_option next_comment -+comment 'OCF Configuration' -+tristate 'OCF (Open Cryptograhic Framework)' CONFIG_OCF_OCF -+dep_mbool ' enable fips RNG checks (fips check on RNG data before use)' \ -+ CONFIG_OCF_FIPS $CONFIG_OCF_OCF -+dep_mbool ' enable harvesting entropy for /dev/random' \ -+ CONFIG_OCF_RANDOMHARVEST $CONFIG_OCF_OCF -+dep_tristate ' cryptodev (user space support)' \ -+ CONFIG_OCF_CRYPTODEV $CONFIG_OCF_OCF -+dep_tristate ' cryptosoft (software crypto engine)' \ -+ CONFIG_OCF_CRYPTOSOFT $CONFIG_OCF_OCF -+dep_tristate ' safenet (HW crypto engine)' \ -+ CONFIG_OCF_SAFE $CONFIG_OCF_OCF -+dep_tristate ' IXP4xx (HW crypto engine)' \ -+ CONFIG_OCF_IXP4XX $CONFIG_OCF_OCF -+dep_mbool ' Enable IXP4xx HW to perform SHA1 and MD5 hashing (very slow)' \ -+ CONFIG_OCF_IXP4XX_SHA1_MD5 $CONFIG_OCF_IXP4XX -+dep_tristate ' hifn (HW crypto engine)' \ -+ CONFIG_OCF_HIFN $CONFIG_OCF_OCF -+dep_tristate ' talitos (HW crypto engine)' \ -+ CONFIG_OCF_TALITOS $CONFIG_OCF_OCF -+dep_tristate ' pasemi (HW crypto engine)' \ -+ CONFIG_OCF_PASEMI $CONFIG_OCF_OCF -+dep_tristate ' ep80579 (HW crypto engine)' \ -+ CONFIG_OCF_EP80579 $CONFIG_OCF_OCF -+dep_tristate ' Micronas c7108 (HW crypto engine)' \ -+ CONFIG_OCF_C7108 $CONFIG_OCF_OCF -+dep_tristate ' uBsec BCM5365 (HW crypto engine)' -+ CONFIG_OCF_UBSEC_SSB $CONFIG_OCF_OCF -+dep_tristate ' ocfnull (does no crypto)' \ -+ CONFIG_OCF_OCFNULL $CONFIG_OCF_OCF -+dep_tristate ' ocf-bench (HW crypto in-kernel benchmark)' \ -+ CONFIG_OCF_BENCH $CONFIG_OCF_OCF -+endmenu -+ -+############################################################################# -diff -Nur linux-3.0.4.orig/crypto/ocf/Kconfig linux-3.0.4/crypto/ocf/Kconfig ---- linux-3.0.4.orig/crypto/ocf/Kconfig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/Kconfig 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,125 @@ -+menu "OCF Configuration" -+ -+config OCF_OCF -+ tristate "OCF (Open Cryptograhic Framework)" -+ help -+ A linux port of the OpenBSD/FreeBSD crypto framework. -+ -+config OCF_RANDOMHARVEST -+ bool "crypto random --- harvest entropy for /dev/random" -+ depends on OCF_OCF -+ help -+ Includes code to harvest random numbers from devices that support it. -+ -+config OCF_FIPS -+ bool "enable fips RNG checks" -+ depends on OCF_OCF && OCF_RANDOMHARVEST -+ help -+ Run all RNG provided data through a fips check before -+ adding it /dev/random's entropy pool. -+ -+config OCF_CRYPTODEV -+ tristate "cryptodev (user space support)" -+ depends on OCF_OCF -+ help -+ The user space API to access crypto hardware. -+ -+config OCF_CRYPTOSOFT -+ tristate "cryptosoft (software crypto engine)" -+ depends on OCF_OCF -+ help -+ A software driver for the OCF framework that uses -+ the kernel CryptoAPI. -+ -+config OCF_SAFE -+ tristate "safenet (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ A driver for a number of the safenet Excel crypto accelerators. -+ Currently tested and working on the 1141 and 1741. -+ -+config OCF_IXP4XX -+ tristate "IXP4xx (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ XScale IXP4xx crypto accelerator driver. Requires the -+ Intel Access library. -+ -+config OCF_IXP4XX_SHA1_MD5 -+ bool "IXP4xx SHA1 and MD5 Hashing" -+ depends on OCF_IXP4XX -+ help -+ Allows the IXP4xx crypto accelerator to perform SHA1 and MD5 hashing. -+ Note: this is MUCH slower than using cryptosoft (software crypto engine). -+ -+config OCF_HIFN -+ tristate "hifn (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for various HIFN based crypto accelerators. -+ (7951, 7955, 7956, 7751, 7811) -+ -+config OCF_HIFNHIPP -+ tristate "Hifn HIPP (HW packet crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for various HIFN (HIPP) based crypto accelerators -+ (7855) -+ -+config OCF_TALITOS -+ tristate "talitos (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for Freescale's security engine (SEC/talitos). -+ -+config OCF_PASEMI -+ tristate "pasemi (HW crypto engine)" -+ depends on OCF_OCF && PPC_PASEMI -+ help -+ OCF driver for the PA Semi PWRficient DMA Engine -+ -+config OCF_EP80579 -+ tristate "ep80579 (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for the Intel EP80579 Integrated Processor Product Line. -+ -+config OCF_CRYPTOCTEON -+ tristate "cryptocteon (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for the Cavium OCTEON Processors. -+ -+config OCF_KIRKWOOD -+ tristate "kirkwood (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for the Marvell Kirkwood (88F6xxx) Processors. -+ -+config OCF_C7108 -+ tristate "Micronas 7108 (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for the Microna 7108 Cipher processors. -+ -+config OCF_UBSEC_SSB -+ tristate "uBsec BCM5365 (HW crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for uBsec BCM5365 hardware crypto accelerator. -+ -+config OCF_OCFNULL -+ tristate "ocfnull (fake crypto engine)" -+ depends on OCF_OCF -+ help -+ OCF driver for measuring ipsec overheads (does no crypto) -+ -+config OCF_BENCH -+ tristate "ocf-bench (HW crypto in-kernel benchmark)" -+ depends on OCF_OCF -+ help -+ A very simple encryption test for the in-kernel interface -+ of OCF. Also includes code to benchmark the IXP Access library -+ for comparison. -+ -+endmenu -diff -Nur linux-3.0.4.orig/crypto/ocf/Makefile linux-3.0.4/crypto/ocf/Makefile ---- linux-3.0.4.orig/crypto/ocf/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/Makefile 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,145 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+OCF_OBJS = crypto.o criov.o -+ -+ifdef CONFIG_OCF_RANDOMHARVEST -+ OCF_OBJS += random.o -+endif -+ -+ifdef CONFIG_OCF_FIPS -+ OCF_OBJS += rndtest.o -+endif -+ -+# Add in autoconf.h to get #defines for CONFIG_xxx -+AUTOCONF_H=$(ROOTDIR)/modules/autoconf.h -+ifeq ($(AUTOCONF_H), $(wildcard $(AUTOCONF_H))) -+ EXTRA_CFLAGS += -include $(AUTOCONF_H) -+ export EXTRA_CFLAGS -+endif -+ -+ifndef obj -+ obj ?= . -+ _obj = subdir -+ mod-subdirs := safe hifn ixp4xx talitos ocfnull -+ export-objs += crypto.o criov.o random.o -+ list-multi += ocf.o -+ _slash := -+else -+ _obj = obj -+ _slash := / -+endif -+ -+EXTRA_CFLAGS += -I$(obj)/. -+ -+obj-$(CONFIG_OCF_OCF) += ocf.o -+obj-$(CONFIG_OCF_CRYPTODEV) += cryptodev.o -+obj-$(CONFIG_OCF_CRYPTOSOFT) += cryptosoft.o -+obj-$(CONFIG_OCF_BENCH) += ocf-bench.o -+ -+$(_obj)-$(CONFIG_OCF_SAFE) += safe$(_slash) -+$(_obj)-$(CONFIG_OCF_HIFN) += hifn$(_slash) -+$(_obj)-$(CONFIG_OCF_IXP4XX) += ixp4xx$(_slash) -+$(_obj)-$(CONFIG_OCF_TALITOS) += talitos$(_slash) -+$(_obj)-$(CONFIG_OCF_PASEMI) += pasemi$(_slash) -+$(_obj)-$(CONFIG_OCF_EP80579) += ep80579$(_slash) -+$(_obj)-$(CONFIG_OCF_CRYPTOCTEON) += cryptocteon$(_slash) -+$(_obj)-$(CONFIG_OCF_KIRKWOOD) += kirkwood$(_slash) -+$(_obj)-$(CONFIG_OCF_OCFNULL) += ocfnull$(_slash) -+$(_obj)-$(CONFIG_OCF_C7108) += c7108$(_slash) -+$(_obj)-$(CONFIG_OCF_UBSEC_SSB) += ubsec_ssb$(_slash) -+ -+ocf-objs := $(OCF_OBJS) -+ -+dummy: -+ @echo "Please consult the README for how to build OCF." -+ @echo "If you can't wait then the following should do it:" -+ @echo "" -+ @echo " make ocf_modules" -+ @echo " sudo make ocf_install" -+ @echo "" -+ @exit 1 -+ -+$(list-multi) dummy1: $(ocf-objs) -+ $(LD) -r -o $@ $(ocf-objs) -+ -+.PHONY: -+clean: -+ rm -f *.o *.ko .*.o.flags .*.ko.cmd .*.o.cmd .*.mod.o.cmd *.mod.c -+ rm -f */*.o */*.ko */.*.o.cmd */.*.ko.cmd */.*.mod.o.cmd */*.mod.c */.*.o.flags -+ rm -f */modules.order */modules.builtin modules.order modules.builtin -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -+# -+# targets to build easily on the current machine -+# -+ -+ocf_make: -+ make -C /lib/modules/$(shell uname -r)/build M=`pwd` $(OCF_TARGET) CONFIG_OCF_OCF=m -+ make -C /lib/modules/$(shell uname -r)/build M=`pwd` $(OCF_TARGET) CONFIG_OCF_OCF=m CONFIG_OCF_CRYPTOSOFT=m -+ -make -C /lib/modules/$(shell uname -r)/build M=`pwd` $(OCF_TARGET) CONFIG_OCF_OCF=m CONFIG_OCF_BENCH=m -+ -make -C /lib/modules/$(shell uname -r)/build M=`pwd` $(OCF_TARGET) CONFIG_OCF_OCF=m CONFIG_OCF_OCFNULL=m -+ -make -C /lib/modules/$(shell uname -r)/build M=`pwd` $(OCF_TARGET) CONFIG_OCF_OCF=m CONFIG_OCF_HIFN=m -+ -+ocf_modules: -+ $(MAKE) ocf_make OCF_TARGET=modules -+ -+ocf_install: -+ $(MAKE) ocf_make OCF_TARGET="modules modules_install" -+ depmod -+ mkdir -p /usr/include/crypto -+ cp cryptodev.h /usr/include/crypto/. -+ -+# -+# generate full kernel patches for 2.4 and 2.6 kernels to make patching -+# your kernel easier -+# -+ -+.PHONY: patch -+patch: -+ patchbase=.; \ -+ [ -d $$patchbase/patches ] || patchbase=..; \ -+ patch=ocf-linux-base.patch; \ -+ patch24=ocf-linux-24.patch; \ -+ patch26=ocf-linux-26.patch; \ -+ ( \ -+ find . -name Makefile; \ -+ find . -name Config.in; \ -+ find . -name Kconfig; \ -+ find . -name README; \ -+ find . -name '*.[ch]' | grep -v '.mod.c'; \ -+ ) | while read t; do \ -+ diff -Nau /dev/null $$t | sed 's?^+++ \./?+++ linux/crypto/ocf/?'; \ -+ done > $$patch; \ -+ cat $$patchbase/patches/linux-2.4.35-ocf.patch $$patch > $$patch24; \ -+ cat $$patchbase/patches/linux-2.6.38-ocf.patch $$patch > $$patch26; \ -+ -+# -+# this target probably does nothing for anyone but me - davidm -+# -+ -+.PHONY: release -+release: -+ REL=`date +%Y%m%d`; RELDIR=/tmp/ocf-linux-$$REL; \ -+ CURDIR=`pwd`; \ -+ rm -rf /tmp/ocf-linux-$$REL*; \ -+ mkdir -p $$RELDIR/ocf; \ -+ mkdir -p $$RELDIR/patches; \ -+ mkdir -p $$RELDIR/crypto-tools; \ -+ cp README* $$RELDIR/.; \ -+ cp patches/[!C]* $$RELDIR/patches/.; \ -+ cp tools/[!C]* $$RELDIR/crypto-tools/.; \ -+ cp -r [!C]* Config.in $$RELDIR/ocf/.; \ -+ rm -rf $$RELDIR/ocf/patches $$RELDIR/ocf/tools; \ -+ rm -f $$RELDIR/ocf/README*; \ -+ cp $$CURDIR/../../user/crypto-tools/[!C]* $$RELDIR/crypto-tools/.; \ -+ make -C $$RELDIR/crypto-tools clean; \ -+ make -C $$RELDIR/ocf clean; \ -+ find $$RELDIR/ocf -name CVS | xargs rm -rf; \ -+ cd $$RELDIR/..; \ -+ tar cvf ocf-linux-$$REL.tar ocf-linux-$$REL; \ -+ gzip -9 ocf-linux-$$REL.tar -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/c7108/Makefile linux-3.0.4/crypto/ocf/c7108/Makefile ---- linux-3.0.4.orig/crypto/ocf/c7108/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/c7108/Makefile 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,12 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+obj-$(CONFIG_OCF_C7108) += aes-7108.o -+ -+obj ?= . -+EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/c7108/aes-7108.c linux-3.0.4/crypto/ocf/c7108/aes-7108.c ---- linux-3.0.4.orig/crypto/ocf/c7108/aes-7108.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/c7108/aes-7108.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,839 @@ -+/* -+ * Copyright (C) 2006 Micronas USA -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored in part by the Defense Advanced Research Projects -+ * Agency (DARPA) and Air Force Research Laboratory, Air Force -+ * Materiel Command, USAF, under agreement number F30602-01-2-0537. -+ * -+ */ -+ -+//#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+//#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* Runtime mode */ -+static int c7108_crypto_mode = C7108_AES_CTRL_MODE_CTR; -+//static int c7108_crypto_mode = C7108_AES_CTRL_MODE_CBC; -+ -+static int32_t c7108_id = -1; -+static struct cipher_7108 **c7108_sessions = NULL; -+static u_int32_t c7108_sesnum = 0; -+static unsigned long iobar; -+ -+/* Crypto entry points */ -+static int c7108_process(void *, struct cryptop *, int); -+static int c7108_newsession(void *, u_int32_t *, struct cryptoini *); -+static int c7108_freesession(void *, u_int64_t); -+ -+/* Globals */ -+static int debug = 0; -+static spinlock_t csr_mutex; -+ -+/* Generic controller-based lock */ -+#define AES_LOCK()\ -+ spin_lock(&csr_mutex) -+#define AES_UNLOCK()\ -+ spin_unlock(&csr_mutex) -+ -+/* 7108 AES register access */ -+#define c7108_reg_wr8(a,d) iowrite8(d, (void*)(iobar+(a))) -+#define c7108_reg_wr16(a,d) iowrite16(d, (void*)(iobar+(a))) -+#define c7108_reg_wr32(a,d) iowrite32(d, (void*)(iobar+(a))) -+#define c7108_reg_rd8(a) ioread8((void*)(iobar+(a))) -+#define c7108_reg_rd16(a) ioread16((void*)(iobar+(a))) -+#define c7108_reg_rd32(a) ioread32((void*)(iobar+(a))) -+ -+static int -+c7108_xlate_key(int klen, u8* k8ptr, u32* k32ptr) -+{ -+ int i, nw=0; -+ nw = ((klen >= 256) ? 8 : (klen >= 192) ? 6 : 4); -+ for ( i = 0; i < nw; i++) { -+ k32ptr[i] = (k8ptr[i+3] << 24) | (k8ptr[i+2] << 16) | -+ (k8ptr[i+1] << 8) | k8ptr[i]; -+ -+ } -+ return 0; -+} -+ -+static int -+c7108_cache_key(int klen, u32* k32ptr, u8* k8ptr) -+{ -+ int i, nb=0; -+ u8* ptr = (u8*)k32ptr; -+ nb = ((klen >= 256) ? 32 : (klen >= 192) ? 24 : 16); -+ for ( i = 0; i < nb; i++) -+ k8ptr[i] = ptr[i]; -+ return 0; -+} -+ -+static int -+c7108_aes_setup_dma(u32 src, u32 dst, u32 len) -+{ -+ if (len < 16) { -+ printk("len < 16\n"); -+ return -10; -+ } -+ if (len % 16) { -+ printk("len not multiple of 16\n"); -+ return -11; -+ } -+ c7108_reg_wr16(C7108_AES_DMA_SRC0_LO, (u16) src); -+ c7108_reg_wr16(C7108_AES_DMA_SRC0_HI, (u16)((src & 0xffff0000) >> 16)); -+ c7108_reg_wr16(C7108_AES_DMA_DST0_LO, (u16) dst); -+ c7108_reg_wr16(C7108_AES_DMA_DST0_HI, (u16)((dst & 0xffff0000) >> 16)); -+ c7108_reg_wr16(C7108_AES_DMA_LEN, (u16) ((len / 16) - 1)); -+ -+ return 0; -+} -+ -+static int -+c7108_aes_set_hw_iv(u8 iv[16]) -+{ -+ c7108_reg_wr16(C7108_AES_IV0_LO, (u16) ((iv[1] << 8) | iv[0])); -+ c7108_reg_wr16(C7108_AES_IV0_HI, (u16) ((iv[3] << 8) | iv[2])); -+ c7108_reg_wr16(C7108_AES_IV1_LO, (u16) ((iv[5] << 8) | iv[4])); -+ c7108_reg_wr16(C7108_AES_IV1_HI, (u16) ((iv[7] << 8) | iv[6])); -+ c7108_reg_wr16(C7108_AES_IV2_LO, (u16) ((iv[9] << 8) | iv[8])); -+ c7108_reg_wr16(C7108_AES_IV2_HI, (u16) ((iv[11] << 8) | iv[10])); -+ c7108_reg_wr16(C7108_AES_IV3_LO, (u16) ((iv[13] << 8) | iv[12])); -+ c7108_reg_wr16(C7108_AES_IV3_HI, (u16) ((iv[15] << 8) | iv[14])); -+ -+ return 0; -+} -+ -+static void -+c7108_aes_read_dkey(u32 * dkey) -+{ -+ dkey[0] = (c7108_reg_rd16(C7108_AES_EKEY0_HI) << 16) | -+ c7108_reg_rd16(C7108_AES_EKEY0_LO); -+ dkey[1] = (c7108_reg_rd16(C7108_AES_EKEY1_HI) << 16) | -+ c7108_reg_rd16(C7108_AES_EKEY1_LO); -+ dkey[2] = (c7108_reg_rd16(C7108_AES_EKEY2_HI) << 16) | -+ c7108_reg_rd16(C7108_AES_EKEY2_LO); -+ dkey[3] = (c7108_reg_rd16(C7108_AES_EKEY3_HI) << 16) | -+ c7108_reg_rd16(C7108_AES_EKEY3_LO); -+ dkey[4] = (c7108_reg_rd16(C7108_AES_EKEY4_HI) << 16) | -+ c7108_reg_rd16(C7108_AES_EKEY4_LO); -+ dkey[5] = (c7108_reg_rd16(C7108_AES_EKEY5_HI) << 16) | -+ c7108_reg_rd16(C7108_AES_EKEY5_LO); -+ dkey[6] = (c7108_reg_rd16(C7108_AES_EKEY6_HI) << 16) | -+ c7108_reg_rd16(C7108_AES_EKEY6_LO); -+ dkey[7] = (c7108_reg_rd16(C7108_AES_EKEY7_HI) << 16) | -+ c7108_reg_rd16(C7108_AES_EKEY7_LO); -+} -+ -+static int -+c7108_aes_cipher(int op, -+ u32 dst, -+ u32 src, -+ u32 len, -+ int klen, -+ u16 mode, -+ u32 key[8], -+ u8 iv[16]) -+{ -+ int rv = 0, cnt=0; -+ u16 ctrl = 0, stat = 0; -+ -+ AES_LOCK(); -+ -+ /* Setup key length */ -+ if (klen == 128) { -+ ctrl |= C7108_AES_KEY_LEN_128; -+ } else if (klen == 192) { -+ ctrl |= C7108_AES_KEY_LEN_192; -+ } else if (klen == 256) { -+ ctrl |= C7108_AES_KEY_LEN_256; -+ } else { -+ AES_UNLOCK(); -+ return -3; -+ } -+ -+ /* Check opcode */ -+ if (C7108_AES_ENCRYPT == op) { -+ ctrl |= C7108_AES_ENCRYPT; -+ } else if (C7108_AES_DECRYPT == op) { -+ ctrl |= C7108_AES_DECRYPT; -+ } else { -+ AES_UNLOCK(); -+ return -4; -+ } -+ -+ /* check mode */ -+ if ( (mode != C7108_AES_CTRL_MODE_CBC) && -+ (mode != C7108_AES_CTRL_MODE_CFB) && -+ (mode != C7108_AES_CTRL_MODE_OFB) && -+ (mode != C7108_AES_CTRL_MODE_CTR) && -+ (mode != C7108_AES_CTRL_MODE_ECB) ) { -+ AES_UNLOCK(); -+ return -5; -+ } -+ -+ /* Now set mode */ -+ ctrl |= mode; -+ -+ /* For CFB, OFB, and CTR, neither backward key -+ * expansion nor key inversion is required. -+ */ -+ if ( (C7108_AES_DECRYPT == op) && -+ (C7108_AES_CTRL_MODE_CBC == mode || -+ C7108_AES_CTRL_MODE_ECB == mode ) ){ -+ -+ /* Program Key */ -+ c7108_reg_wr16(C7108_AES_KEY0_LO, (u16) key[4]); -+ c7108_reg_wr16(C7108_AES_KEY0_HI, (u16) (key[4] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY1_LO, (u16) key[5]); -+ c7108_reg_wr16(C7108_AES_KEY1_HI, (u16) (key[5] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY2_LO, (u16) key[6]); -+ c7108_reg_wr16(C7108_AES_KEY2_HI, (u16) (key[6] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY3_LO, (u16) key[7]); -+ c7108_reg_wr16(C7108_AES_KEY3_HI, (u16) (key[7] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY6_LO, (u16) key[2]); -+ c7108_reg_wr16(C7108_AES_KEY6_HI, (u16) (key[2] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY7_LO, (u16) key[3]); -+ c7108_reg_wr16(C7108_AES_KEY7_HI, (u16) (key[3] >> 16)); -+ -+ -+ if (192 == klen) { -+ c7108_reg_wr16(C7108_AES_KEY4_LO, (u16) key[7]); -+ c7108_reg_wr16(C7108_AES_KEY4_HI, (u16) (key[7] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY5_LO, (u16) key[7]); -+ c7108_reg_wr16(C7108_AES_KEY5_HI, (u16) (key[7] >> 16)); -+ -+ } else if (256 == klen) { -+ /* 256 */ -+ c7108_reg_wr16(C7108_AES_KEY4_LO, (u16) key[0]); -+ c7108_reg_wr16(C7108_AES_KEY4_HI, (u16) (key[0] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY5_LO, (u16) key[1]); -+ c7108_reg_wr16(C7108_AES_KEY5_HI, (u16) (key[1] >> 16)); -+ -+ } -+ -+ } else { -+ /* Program Key */ -+ c7108_reg_wr16(C7108_AES_KEY0_LO, (u16) key[0]); -+ c7108_reg_wr16(C7108_AES_KEY0_HI, (u16) (key[0] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY1_LO, (u16) key[1]); -+ c7108_reg_wr16(C7108_AES_KEY1_HI, (u16) (key[1] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY2_LO, (u16) key[2]); -+ c7108_reg_wr16(C7108_AES_KEY2_HI, (u16) (key[2] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY3_LO, (u16) key[3]); -+ c7108_reg_wr16(C7108_AES_KEY3_HI, (u16) (key[3] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY4_LO, (u16) key[4]); -+ c7108_reg_wr16(C7108_AES_KEY4_HI, (u16) (key[4] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY5_LO, (u16) key[5]); -+ c7108_reg_wr16(C7108_AES_KEY5_HI, (u16) (key[5] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY6_LO, (u16) key[6]); -+ c7108_reg_wr16(C7108_AES_KEY6_HI, (u16) (key[6] >> 16)); -+ c7108_reg_wr16(C7108_AES_KEY7_LO, (u16) key[7]); -+ c7108_reg_wr16(C7108_AES_KEY7_HI, (u16) (key[7] >> 16)); -+ -+ } -+ -+ /* Set IV always */ -+ c7108_aes_set_hw_iv(iv); -+ -+ /* Program DMA addresses */ -+ if ((rv = c7108_aes_setup_dma(src, dst, len)) < 0) { -+ AES_UNLOCK(); -+ return rv; -+ } -+ -+ -+ /* Start AES cipher */ -+ c7108_reg_wr16(C7108_AES_CTRL, ctrl | C7108_AES_GO); -+ -+ //printk("Ctrl: 0x%x\n", ctrl | C7108_AES_GO); -+ do { -+ /* TODO: interrupt mode */ -+ // printk("aes_stat=0x%x\n", stat); -+ //udelay(100); -+ } while ((cnt++ < 1000000) && -+ !((stat=c7108_reg_rd16(C7108_AES_CTRL))&C7108_AES_OP_DONE)); -+ -+ -+ if ((mode == C7108_AES_CTRL_MODE_ECB)|| -+ (mode == C7108_AES_CTRL_MODE_CBC)) { -+ /* Save out key when the lock is held ... */ -+ c7108_aes_read_dkey(key); -+ } -+ -+ AES_UNLOCK(); -+ return 0; -+ -+} -+ -+/* -+ * Generate a new crypto device session. -+ */ -+static int -+c7108_newsession(void *arg, u_int32_t *sid, struct cryptoini *cri) -+{ -+ struct cipher_7108 **swd; -+ u_int32_t i; -+ char *algo; -+ int mode, xfm_type; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid == NULL || cri == NULL) { -+ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ if (c7108_sessions) { -+ for (i = 1; i < c7108_sesnum; i++) -+ if (c7108_sessions[i] == NULL) -+ break; -+ } else -+ i = 1; /* NB: to silence compiler warning */ -+ -+ if (c7108_sessions == NULL || i == c7108_sesnum) { -+ if (c7108_sessions == NULL) { -+ i = 1; /* We leave c7108_sessions[0] empty */ -+ c7108_sesnum = CRYPTO_SW_SESSIONS; -+ } else -+ c7108_sesnum *= 2; -+ -+ swd = kmalloc(c7108_sesnum * sizeof(struct cipher_7108 *), -+ GFP_ATOMIC); -+ if (swd == NULL) { -+ /* Reset session number */ -+ if (c7108_sesnum == CRYPTO_SW_SESSIONS) -+ c7108_sesnum = 0; -+ else -+ c7108_sesnum /= 2; -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memset(swd, 0, c7108_sesnum * sizeof(struct cipher_7108 *)); -+ -+ /* Copy existing sessions */ -+ if (c7108_sessions) { -+ memcpy(swd, c7108_sessions, -+ (c7108_sesnum / 2) * sizeof(struct cipher_7108 *)); -+ kfree(c7108_sessions); -+ } -+ -+ c7108_sessions = swd; -+ -+ } -+ -+ swd = &c7108_sessions[i]; -+ *sid = i; -+ -+ while (cri) { -+ *swd = (struct cipher_7108 *) -+ kmalloc(sizeof(struct cipher_7108), GFP_ATOMIC); -+ if (*swd == NULL) { -+ c7108_freesession(NULL, i); -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memset(*swd, 0, sizeof(struct cipher_7108)); -+ -+ algo = NULL; -+ mode = 0; -+ xfm_type = HW_TYPE_CIPHER; -+ -+ switch (cri->cri_alg) { -+ -+ case CRYPTO_AES_CBC: -+ algo = "aes"; -+ mode = CRYPTO_TFM_MODE_CBC; -+ c7108_crypto_mode = C7108_AES_CTRL_MODE_CBC; -+ break; -+#if 0 -+ case CRYPTO_AES_CTR: -+ algo = "aes_ctr"; -+ mode = CRYPTO_TFM_MODE_CBC; -+ c7108_crypto_mode = C7108_AES_CTRL_MODE_CTR; -+ break; -+ case CRYPTO_AES_ECB: -+ algo = "aes_ecb"; -+ mode = CRYPTO_TFM_MODE_CBC; -+ c7108_crypto_mode = C7108_AES_CTRL_MODE_ECB; -+ break; -+ case CRYPTO_AES_OFB: -+ algo = "aes_ofb"; -+ mode = CRYPTO_TFM_MODE_CBC; -+ c7108_crypto_mode = C7108_AES_CTRL_MODE_OFB; -+ break; -+ case CRYPTO_AES_CFB: -+ algo = "aes_cfb"; -+ mode = CRYPTO_TFM_MODE_CBC; -+ c7108_crypto_mode = C7108_AES_CTRL_MODE_CFB; -+ break; -+#endif -+ default: -+ printk("unsupported crypto algorithm: %d\n", -+ cri->cri_alg); -+ return -EINVAL; -+ break; -+ } -+ -+ -+ if (!algo || !*algo) { -+ printk("cypher_7108_crypto: Unknown algo 0x%x\n", -+ cri->cri_alg); -+ c7108_freesession(NULL, i); -+ return EINVAL; -+ } -+ -+ if (xfm_type == HW_TYPE_CIPHER) { -+ if (debug) { -+ dprintk("%s key:", __FUNCTION__); -+ for (i = 0; i < (cri->cri_klen + 7) / 8; i++) -+ dprintk("%s0x%02x", (i % 8) ? " " : "\n ", -+ cri->cri_key[i]); -+ dprintk("\n"); -+ } -+ -+ } else if (xfm_type == SW_TYPE_HMAC || -+ xfm_type == SW_TYPE_HASH) { -+ printk("cypher_7108_crypto: HMAC unsupported!\n"); -+ return -EINVAL; -+ c7108_freesession(NULL, i); -+ } else { -+ printk("cypher_7108_crypto: " -+ "Unhandled xfm_type %d\n", xfm_type); -+ c7108_freesession(NULL, i); -+ return EINVAL; -+ } -+ -+ (*swd)->cri_alg = cri->cri_alg; -+ (*swd)->xfm_type = xfm_type; -+ -+ cri = cri->cri_next; -+ swd = &((*swd)->next); -+ } -+ return 0; -+} -+ -+/* -+ * Free a session. -+ */ -+static int -+c7108_freesession(void *arg, u_int64_t tid) -+{ -+ struct cipher_7108 *swd; -+ u_int32_t sid = CRYPTO_SESID2LID(tid); -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid > c7108_sesnum || c7108_sessions == NULL || -+ c7108_sessions[sid] == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return(EINVAL); -+ } -+ -+ /* Silently accept and return */ -+ if (sid == 0) -+ return(0); -+ -+ while ((swd = c7108_sessions[sid]) != NULL) { -+ c7108_sessions[sid] = swd->next; -+ kfree(swd); -+ } -+ return 0; -+} -+ -+/* -+ * Process a hardware request. -+ */ -+static int -+c7108_process(void *arg, struct cryptop *crp, int hint) -+{ -+ struct cryptodesc *crd; -+ struct cipher_7108 *sw; -+ u_int32_t lid; -+ int type; -+ u32 hwkey[8]; -+ -+#define SCATTERLIST_MAX 16 -+ struct scatterlist sg[SCATTERLIST_MAX]; -+ int sg_num, sg_len, skip; -+ struct sk_buff *skb = NULL; -+ struct uio *uiop = NULL; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ /* Sanity check */ -+ if (crp == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ crp->crp_etype = 0; -+ -+ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ lid = crp->crp_sid & 0xffffffff; -+ if (lid >= c7108_sesnum || lid == 0 || c7108_sessions == NULL || -+ c7108_sessions[lid] == NULL) { -+ crp->crp_etype = ENOENT; -+ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); -+ goto done; -+ } -+ -+ /* -+ * do some error checking outside of the loop for SKB and IOV -+ * processing this leaves us with valid skb or uiop pointers -+ * for later -+ */ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ skb = (struct sk_buff *) crp->crp_buf; -+ if (skb_shinfo(skb)->nr_frags >= SCATTERLIST_MAX) { -+ printk("%s,%d: %d nr_frags > SCATTERLIST_MAX", -+ __FILE__, __LINE__, -+ skb_shinfo(skb)->nr_frags); -+ goto done; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ uiop = (struct uio *) crp->crp_buf; -+ if (uiop->uio_iovcnt > SCATTERLIST_MAX) { -+ printk("%s,%d: %d uio_iovcnt > SCATTERLIST_MAX", -+ __FILE__, __LINE__, -+ uiop->uio_iovcnt); -+ goto done; -+ } -+ } -+ -+ /* Go through crypto descriptors, processing as we go */ -+ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { -+ /* -+ * Find the crypto context. -+ * -+ * XXX Note that the logic here prevents us from having -+ * XXX the same algorithm multiple times in a session -+ * XXX (or rather, we can but it won't give us the right -+ * XXX results). To do that, we'd need some way of differentiating -+ * XXX between the various instances of an algorithm (so we can -+ * XXX locate the correct crypto context). -+ */ -+ for (sw = c7108_sessions[lid]; -+ sw && sw->cri_alg != crd->crd_alg; -+ sw = sw->next) -+ ; -+ -+ /* No such context ? */ -+ if (sw == NULL) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ goto done; -+ } -+ -+ skip = crd->crd_skip; -+ -+ /* -+ * setup the SG list skip from the start of the buffer -+ */ -+ memset(sg, 0, sizeof(sg)); -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ int i, len; -+ type = CRYPTO_BUF_SKBUF; -+ -+ sg_num = 0; -+ sg_len = 0; -+ -+ if (skip < skb_headlen(skb)) { -+ //sg[sg_num].page = virt_to_page(skb->data + skip); -+ //sg[sg_num].offset = offset_in_page(skb->data + skip); -+ len = skb_headlen(skb) - skip; -+ if (len + sg_len > crd->crd_len) -+ len = crd->crd_len - sg_len; -+ //sg[sg_num].length = len; -+ sg_set_page(&sg[sg_num], virt_to_page(skb->data + skip), len, offset_in_page(skb->data + skip)); -+ sg_len += sg[sg_num].length; -+ sg_num++; -+ skip = 0; -+ } else -+ skip -= skb_headlen(skb); -+ -+ for (i = 0; sg_len < crd->crd_len && -+ i < skb_shinfo(skb)->nr_frags && -+ sg_num < SCATTERLIST_MAX; i++) { -+ if (skip < skb_shinfo(skb)->frags[i].size) { -+ //sg[sg_num].page = skb_shinfo(skb)->frags[i].page; -+ //sg[sg_num].offset = skb_shinfo(skb)->frags[i].page_offset + skip; -+ len = skb_shinfo(skb)->frags[i].size - skip; -+ if (len + sg_len > crd->crd_len) -+ len = crd->crd_len - sg_len; -+ //sg[sg_num].length = len; -+ sg_set_page(&sg[sg_num], skb_shinfo(skb)->frags[i].page, len, skb_shinfo(skb)->frags[i].page_offset + skip); -+ sg_len += sg[sg_num].length; -+ sg_num++; -+ skip = 0; -+ } else -+ skip -= skb_shinfo(skb)->frags[i].size; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ int len; -+ type = CRYPTO_BUF_IOV; -+ sg_len = 0; -+ for (sg_num = 0; sg_len < crd->crd_len && -+ sg_num < uiop->uio_iovcnt && -+ sg_num < SCATTERLIST_MAX; sg_num++) { -+ if (skip < uiop->uio_iov[sg_num].iov_len) { -+ //sg[sg_num].page = virt_to_page(uiop->uio_iov[sg_num].iov_base+skip); -+ //sg[sg_num].offset = offset_in_page(uiop->uio_iov[sg_num].iov_base+skip); -+ len = uiop->uio_iov[sg_num].iov_len - skip; -+ if (len + sg_len > crd->crd_len) -+ len = crd->crd_len - sg_len; -+ //sg[sg_num].length = len; -+ sg_set_page(&sg[sg_num], virt_to_page(uiop->uio_iov[sg_num].iov_base+skip), len, offset_in_page(uiop->uio_iov[sg_num].iov_base+skip)); -+ sg_len += sg[sg_num].length; -+ skip = 0; -+ } else -+ skip -= uiop->uio_iov[sg_num].iov_len; -+ } -+ } else { -+ type = CRYPTO_BUF_CONTIG; -+ //sg[0].page = virt_to_page(crp->crp_buf + skip); -+ //sg[0].offset = offset_in_page(crp->crp_buf + skip); -+ sg_len = (crp->crp_ilen - skip); -+ if (sg_len > crd->crd_len) -+ sg_len = crd->crd_len; -+ //sg[0].length = sg_len; -+ sg_set_page(&sg[0], virt_to_page(crp->crp_buf + skip), sg_len, offset_in_page(crp->crp_buf + skip)); -+ sg_num = 1; -+ } -+ -+ -+ switch (sw->xfm_type) { -+ -+ case HW_TYPE_CIPHER: { -+ -+ unsigned char iv[64]; -+ unsigned char *ivp = iv; -+ int i; -+ int ivsize = 16; /* fixed for AES */ -+ int blocksize = 16; /* fixed for AES */ -+ -+ if (sg_len < blocksize) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: EINVAL len %d < %d\n", -+ __FILE__, __LINE__, -+ sg_len, -+ blocksize); -+ goto done; -+ } -+ -+ if (ivsize > sizeof(iv)) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ goto done; -+ } -+ -+ if (crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ -+ -+ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { -+ ivp = crd->crd_iv; -+ } else { -+ get_random_bytes(ivp, ivsize); -+ } -+ /* -+ * do we have to copy the IV back to the buffer ? -+ */ -+ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { -+ crypto_copyback(crp->crp_buf, -+ crd->crd_inject, -+ ivsize, -+ (caddr_t)ivp); -+ } -+ -+ c7108_xlate_key(crd->crd_klen, -+ (u8*)crd->crd_key, (u32*)hwkey); -+ -+ /* Encrypt SG list */ -+ for (i = 0; i < sg_num; i++) { -+ sg[i].dma_address = -+ dma_map_single(NULL, -+ kmap(sg_page(&sg[i])) + sg[i].offset, sg_len, DMA_BIDIRECTIONAL); -+#if 0 -+ printk("sg[%d]:0x%08x, off 0x%08x " -+ "kmap 0x%08x phys 0x%08x\n", -+ i, sg[i].page, sg[i].offset, -+ kmap(sg[i].page) + sg[i].offset, -+ sg[i].dma_address); -+#endif -+ c7108_aes_cipher(C7108_AES_ENCRYPT, -+ sg[i].dma_address, -+ sg[i].dma_address, -+ sg_len, -+ crd->crd_klen, -+ c7108_crypto_mode, -+ hwkey, -+ ivp); -+ -+ if ((c7108_crypto_mode == C7108_AES_CTRL_MODE_CBC)|| -+ (c7108_crypto_mode == C7108_AES_CTRL_MODE_ECB)) { -+ /* Read back expanded key and cache it in key -+ * context. -+ * NOTE: for ECB/CBC modes only (not CTR, CFB, OFB) -+ * where you set the key once. -+ */ -+ c7108_cache_key(crd->crd_klen, -+ (u32*)hwkey, (u8*)crd->crd_key); -+#if 0 -+ printk("%s expanded key:", __FUNCTION__); -+ for (i = 0; i < (crd->crd_klen + 7) / 8; i++) -+ printk("%s0x%02x", (i % 8) ? " " : "\n ", -+ crd->crd_key[i]); -+ printk("\n"); -+#endif -+ } -+ } -+ } -+ else { /*decrypt */ -+ -+ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { -+ ivp = crd->crd_iv; -+ } else { -+ crypto_copydata(crp->crp_buf, crd->crd_inject, -+ ivsize, (caddr_t)ivp); -+ } -+ -+ c7108_xlate_key(crd->crd_klen, -+ (u8*)crd->crd_key, (u32*)hwkey); -+ -+ /* Decrypt SG list */ -+ for (i = 0; i < sg_num; i++) { -+ sg[i].dma_address = -+ dma_map_single(NULL, -+ kmap(sg_page(&sg[i])) + sg[i].offset, -+ sg_len, DMA_BIDIRECTIONAL); -+ -+#if 0 -+ printk("sg[%d]:0x%08x, off 0x%08x " -+ "kmap 0x%08x phys 0x%08x\n", -+ i, sg[i].page, sg[i].offset, -+ kmap(sg[i].page) + sg[i].offset, -+ sg[i].dma_address); -+#endif -+ c7108_aes_cipher(C7108_AES_DECRYPT, -+ sg[i].dma_address, -+ sg[i].dma_address, -+ sg_len, -+ crd->crd_klen, -+ c7108_crypto_mode, -+ hwkey, -+ ivp); -+ } -+ } -+ } break; -+ case SW_TYPE_HMAC: -+ case SW_TYPE_HASH: -+ crp->crp_etype = EINVAL; -+ goto done; -+ break; -+ -+ case SW_TYPE_COMP: -+ crp->crp_etype = EINVAL; -+ goto done; -+ break; -+ -+ default: -+ /* Unknown/unsupported algorithm */ -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ } -+ -+done: -+ crypto_done(crp); -+ return 0; -+} -+ -+static struct { -+ softc_device_decl sc_dev; -+} a7108dev; -+ -+static device_method_t a7108_methods = { -+/* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, c7108_newsession), -+ DEVMETHOD(cryptodev_freesession, c7108_freesession), -+ DEVMETHOD(cryptodev_process, c7108_process), -+ DEVMETHOD(cryptodev_kprocess, NULL) -+}; -+ -+static int -+cypher_7108_crypto_init(void) -+{ -+ dprintk("%s(%p)\n", __FUNCTION__, cypher_7108_crypto_init); -+ -+ iobar = (unsigned long)ioremap(CCU_AES_REG_BASE, 0x4000); -+ printk("7108: AES @ 0x%08x (0x%08x phys) %s mode\n", -+ iobar, CCU_AES_REG_BASE, -+ c7108_crypto_mode & C7108_AES_CTRL_MODE_CBC ? "CBC" : -+ c7108_crypto_mode & C7108_AES_CTRL_MODE_ECB ? "ECB" : -+ c7108_crypto_mode & C7108_AES_CTRL_MODE_CTR ? "CTR" : -+ c7108_crypto_mode & C7108_AES_CTRL_MODE_CFB ? "CFB" : -+ c7108_crypto_mode & C7108_AES_CTRL_MODE_OFB ? "OFB" : "???"); -+ csr_mutex = SPIN_LOCK_UNLOCKED; -+ -+ memset(&a7108dev, 0, sizeof(a7108dev)); -+ softc_device_init(&a7108dev, "aes7108", 0, a7108_methods); -+ -+ c7108_id = crypto_get_driverid(softc_get_device(&a7108dev), CRYPTOCAP_F_HARDWARE); -+ if (c7108_id < 0) -+ panic("7108: crypto device cannot initialize!"); -+ -+// crypto_register(c7108_id, CRYPTO_AES_CBC, 0, 0, c7108_newsession, c7108_freesession, c7108_process, NULL); -+ crypto_register(c7108_id, CRYPTO_AES_CBC, 0, 0); -+ -+ return(0); -+} -+ -+static void -+cypher_7108_crypto_exit(void) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ crypto_unregister_all(c7108_id); -+ c7108_id = -1; -+} -+ -+module_init(cypher_7108_crypto_init); -+module_exit(cypher_7108_crypto_exit); -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_DESCRIPTION("Cypher 7108 Crypto (OCF module for kernel crypto)"); -diff -Nur linux-3.0.4.orig/crypto/ocf/c7108/aes-7108.h linux-3.0.4/crypto/ocf/c7108/aes-7108.h ---- linux-3.0.4.orig/crypto/ocf/c7108/aes-7108.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/c7108/aes-7108.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,134 @@ -+/* -+ * Copyright (C) 2006 Micronas USA -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored in part by the Defense Advanced Research Projects -+ * Agency (DARPA) and Air Force Research Laboratory, Air Force -+ * Materiel Command, USAF, under agreement number F30602-01-2-0537. -+ * -+ */ -+ -+#ifndef __AES_7108_H__ -+#define __AES_7108_H__ -+ -+/* Cypher 7108 AES Controller Hardware */ -+#define CCU_REG_BASE 0x1b500000 -+#define CCU_AES_REG_BASE (CCU_REG_BASE + 0x100) -+#define C7108_AES_KEY0_LO (0x0000) -+#define C7108_AES_KEY0_HI (0x0004) -+#define C7108_AES_KEY1_LO (0x0008) -+#define C7108_AES_KEY1_HI (0x000c) -+#define C7108_AES_KEY2_LO (0x0010) -+#define C7108_AES_KEY2_HI (0x0014) -+#define C7108_AES_KEY3_LO (0x0018) -+#define C7108_AES_KEY3_HI (0x001c) -+#define C7108_AES_KEY4_LO (0x0020) -+#define C7108_AES_KEY4_HI (0x0024) -+#define C7108_AES_KEY5_LO (0x0028) -+#define C7108_AES_KEY5_HI (0x002c) -+#define C7108_AES_KEY6_LO (0x0030) -+#define C7108_AES_KEY6_HI (0x0034) -+#define C7108_AES_KEY7_LO (0x0038) -+#define C7108_AES_KEY7_HI (0x003c) -+#define C7108_AES_IV0_LO (0x0040) -+#define C7108_AES_IV0_HI (0x0044) -+#define C7108_AES_IV1_LO (0x0048) -+#define C7108_AES_IV1_HI (0x004c) -+#define C7108_AES_IV2_LO (0x0050) -+#define C7108_AES_IV2_HI (0x0054) -+#define C7108_AES_IV3_LO (0x0058) -+#define C7108_AES_IV3_HI (0x005c) -+ -+#define C7108_AES_DMA_SRC0_LO (0x0068) /* Bits 0:15 */ -+#define C7108_AES_DMA_SRC0_HI (0x006c) /* Bits 27:16 */ -+#define C7108_AES_DMA_DST0_LO (0x0070) /* Bits 0:15 */ -+#define C7108_AES_DMA_DST0_HI (0x0074) /* Bits 27:16 */ -+#define C7108_AES_DMA_LEN (0x0078) /*Bytes:(Count+1)x16 */ -+ -+/* AES/Copy engine control register */ -+#define C7108_AES_CTRL (0x007c) /* AES control */ -+#define C7108_AES_CTRL_RS (1<<0) /* Which set of src/dst to use */ -+ -+/* AES Cipher mode, controlled by setting Bits 2:0 */ -+#define C7108_AES_CTRL_MODE_CBC 0 -+#define C7108_AES_CTRL_MODE_CFB (1<<0) -+#define C7108_AES_CTRL_MODE_OFB (1<<1) -+#define C7108_AES_CTRL_MODE_CTR ((1<<0)|(1<<1)) -+#define C7108_AES_CTRL_MODE_ECB (1<<2) -+ -+/* AES Key length , Bits 5:4 */ -+#define C7108_AES_KEY_LEN_128 0 /* 00 */ -+#define C7108_AES_KEY_LEN_192 (1<<4) /* 01 */ -+#define C7108_AES_KEY_LEN_256 (1<<5) /* 10 */ -+ -+/* AES Operation (crypt/decrypt), Bit 3 */ -+#define C7108_AES_DECRYPT (1<<3) /* Clear for encrypt */ -+#define C7108_AES_ENCRYPT 0 -+#define C7108_AES_INTR (1<<13) /* Set on done trans from 0->1*/ -+#define C7108_AES_GO (1<<14) /* Run */ -+#define C7108_AES_OP_DONE (1<<15) /* Set when complete */ -+ -+ -+/* Expanded key registers */ -+#define C7108_AES_EKEY0_LO (0x0080) -+#define C7108_AES_EKEY0_HI (0x0084) -+#define C7108_AES_EKEY1_LO (0x0088) -+#define C7108_AES_EKEY1_HI (0x008c) -+#define C7108_AES_EKEY2_LO (0x0090) -+#define C7108_AES_EKEY2_HI (0x0094) -+#define C7108_AES_EKEY3_LO (0x0098) -+#define C7108_AES_EKEY3_HI (0x009c) -+#define C7108_AES_EKEY4_LO (0x00a0) -+#define C7108_AES_EKEY4_HI (0x00a4) -+#define C7108_AES_EKEY5_LO (0x00a8) -+#define C7108_AES_EKEY5_HI (0x00ac) -+#define C7108_AES_EKEY6_LO (0x00b0) -+#define C7108_AES_EKEY6_HI (0x00b4) -+#define C7108_AES_EKEY7_LO (0x00b8) -+#define C7108_AES_EKEY7_HI (0x00bc) -+#define C7108_AES_OK (0x00fc) /* Reset: "OK" */ -+ -+#define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK) -+ -+/* Software session entry */ -+ -+#define HW_TYPE_CIPHER 0 -+#define SW_TYPE_HMAC 1 -+#define SW_TYPE_AUTH2 2 -+#define SW_TYPE_HASH 3 -+#define SW_TYPE_COMP 4 -+ -+struct cipher_7108 { -+ int xfm_type; -+ int cri_alg; -+ union { -+ struct { -+ char sw_key[HMAC_BLOCK_LEN]; -+ int sw_klen; -+ int sw_authlen; -+ } hmac; -+ } u; -+ struct cipher_7108 *next; -+}; -+ -+ -+ -+#endif /* __C7108_AES_7108_H__ */ -diff -Nur linux-3.0.4.orig/crypto/ocf/criov.c linux-3.0.4/crypto/ocf/criov.c ---- linux-3.0.4.orig/crypto/ocf/criov.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/criov.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,216 @@ -+/* $OpenBSD: criov.c,v 1.9 2002/01/29 15:48:29 jason Exp $ */ -+ -+/* -+ * Linux port done by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * The license and original author are listed below. -+ * -+ * Copyright (c) 1999 Theo de Raadt -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+__FBSDID("$FreeBSD: src/sys/opencrypto/criov.c,v 1.5 2006/06/04 22:15:13 pjd Exp $"); -+ */ -+ -+#include -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+/* -+ * This macro is only for avoiding code duplication, as we need to skip -+ * given number of bytes in the same way in three functions below. -+ */ -+#define CUIO_SKIP() do { \ -+ KASSERT(off >= 0, ("%s: off %d < 0", __func__, off)); \ -+ KASSERT(len >= 0, ("%s: len %d < 0", __func__, len)); \ -+ while (off > 0) { \ -+ KASSERT(iol >= 0, ("%s: empty in skip", __func__)); \ -+ if (off < iov->iov_len) \ -+ break; \ -+ off -= iov->iov_len; \ -+ iol--; \ -+ iov++; \ -+ } \ -+} while (0) -+ -+void -+cuio_copydata(struct uio* uio, int off, int len, caddr_t cp) -+{ -+ struct iovec *iov = uio->uio_iov; -+ int iol = uio->uio_iovcnt; -+ unsigned count; -+ -+ CUIO_SKIP(); -+ while (len > 0) { -+ KASSERT(iol >= 0, ("%s: empty", __func__)); -+ count = min((int)(iov->iov_len - off), len); -+ memcpy(cp, ((caddr_t)iov->iov_base) + off, count); -+ len -= count; -+ cp += count; -+ off = 0; -+ iol--; -+ iov++; -+ } -+} -+ -+void -+cuio_copyback(struct uio* uio, int off, int len, caddr_t cp) -+{ -+ struct iovec *iov = uio->uio_iov; -+ int iol = uio->uio_iovcnt; -+ unsigned count; -+ -+ CUIO_SKIP(); -+ while (len > 0) { -+ KASSERT(iol >= 0, ("%s: empty", __func__)); -+ count = min((int)(iov->iov_len - off), len); -+ memcpy(((caddr_t)iov->iov_base) + off, cp, count); -+ len -= count; -+ cp += count; -+ off = 0; -+ iol--; -+ iov++; -+ } -+} -+ -+/* -+ * Return a pointer to iov/offset of location in iovec list. -+ */ -+struct iovec * -+cuio_getptr(struct uio *uio, int loc, int *off) -+{ -+ struct iovec *iov = uio->uio_iov; -+ int iol = uio->uio_iovcnt; -+ -+ while (loc >= 0) { -+ /* Normal end of search */ -+ if (loc < iov->iov_len) { -+ *off = loc; -+ return (iov); -+ } -+ -+ loc -= iov->iov_len; -+ if (iol == 0) { -+ if (loc == 0) { -+ /* Point at the end of valid data */ -+ *off = iov->iov_len; -+ return (iov); -+ } else -+ return (NULL); -+ } else { -+ iov++, iol--; -+ } -+ } -+ -+ return (NULL); -+} -+ -+EXPORT_SYMBOL(cuio_copyback); -+EXPORT_SYMBOL(cuio_copydata); -+EXPORT_SYMBOL(cuio_getptr); -+ -+ -+static void -+skb_copy_bits_back(struct sk_buff *skb, int offset, caddr_t cp, int len) -+{ -+ int i; -+ if (offset < skb_headlen(skb)) { -+ memcpy(skb->data + offset, cp, min_t(int, skb_headlen(skb), len)); -+ len -= skb_headlen(skb); -+ cp += skb_headlen(skb); -+ } -+ offset -= skb_headlen(skb); -+ for (i = 0; len > 0 && i < skb_shinfo(skb)->nr_frags; i++) { -+ if (offset < skb_shinfo(skb)->frags[i].size) { -+ memcpy(page_address(skb_shinfo(skb)->frags[i].page) + -+ skb_shinfo(skb)->frags[i].page_offset, -+ cp, min_t(int, skb_shinfo(skb)->frags[i].size, len)); -+ len -= skb_shinfo(skb)->frags[i].size; -+ cp += skb_shinfo(skb)->frags[i].size; -+ } -+ offset -= skb_shinfo(skb)->frags[i].size; -+ } -+} -+ -+void -+crypto_copyback(int flags, caddr_t buf, int off, int size, caddr_t in) -+{ -+ -+ if ((flags & CRYPTO_F_SKBUF) != 0) -+ skb_copy_bits_back((struct sk_buff *)buf, off, in, size); -+ else if ((flags & CRYPTO_F_IOV) != 0) -+ cuio_copyback((struct uio *)buf, off, size, in); -+ else -+ bcopy(in, buf + off, size); -+} -+ -+void -+crypto_copydata(int flags, caddr_t buf, int off, int size, caddr_t out) -+{ -+ -+ if ((flags & CRYPTO_F_SKBUF) != 0) -+ skb_copy_bits((struct sk_buff *)buf, off, out, size); -+ else if ((flags & CRYPTO_F_IOV) != 0) -+ cuio_copydata((struct uio *)buf, off, size, out); -+ else -+ bcopy(buf + off, out, size); -+} -+ -+int -+crypto_apply(int flags, caddr_t buf, int off, int len, -+ int (*f)(void *, void *, u_int), void *arg) -+{ -+#if 0 -+ int error; -+ -+ if ((flags & CRYPTO_F_SKBUF) != 0) -+ error = XXXXXX((struct mbuf *)buf, off, len, f, arg); -+ else if ((flags & CRYPTO_F_IOV) != 0) -+ error = cuio_apply((struct uio *)buf, off, len, f, arg); -+ else -+ error = (*f)(arg, buf + off, len); -+ return (error); -+#else -+ KASSERT(0, ("crypto_apply not implemented!\n")); -+#endif -+ return 0; -+} -+ -+EXPORT_SYMBOL(crypto_copyback); -+EXPORT_SYMBOL(crypto_copydata); -+EXPORT_SYMBOL(crypto_apply); -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/crypto.c linux-3.0.4/crypto/ocf/crypto.c ---- linux-3.0.4.orig/crypto/ocf/crypto.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/crypto.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,1766 @@ -+/*- -+ * Linux port done by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * The license and original author are listed below. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * Copyright (c) 2002-2006 Sam Leffler. All rights reserved. -+ * -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#if 0 -+#include -+__FBSDID("$FreeBSD: src/sys/opencrypto/crypto.c,v 1.27 2007/03/21 03:42:51 sam Exp $"); -+#endif -+ -+/* -+ * Cryptographic Subsystem. -+ * -+ * This code is derived from the Openbsd Cryptographic Framework (OCF) -+ * that has the copyright shown below. Very little of the original -+ * code remains. -+ */ -+/*- -+ * The author of this code is Angelos D. Keromytis (angelos@cis.upenn.edu) -+ * -+ * This code was written by Angelos D. Keromytis in Athens, Greece, in -+ * February 2000. Network Security Technologies Inc. (NSTI) kindly -+ * supported the development of this code. -+ * -+ * Copyright (c) 2000, 2001 Angelos D. Keromytis -+ * -+ * Permission to use, copy, and modify this software with or without fee -+ * is hereby granted, provided that this entire notice is included in -+ * all source code copies of any software which is or includes a copy or -+ * modification of this software. -+ * -+ * THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR -+ * IMPLIED WARRANTY. IN PARTICULAR, NONE OF THE AUTHORS MAKES ANY -+ * REPRESENTATION OR WARRANTY OF ANY KIND CONCERNING THE -+ * MERCHANTABILITY OF THIS SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR -+ * PURPOSE. -+ * -+__FBSDID("$FreeBSD: src/sys/opencrypto/crypto.c,v 1.16 2005/01/07 02:29:16 imp Exp $"); -+ */ -+ -+ -+#include -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,4) -+#include -+#endif -+#include -+ -+/* -+ * keep track of whether or not we have been initialised, a big -+ * issue if we are linked into the kernel and a driver gets started before -+ * us -+ */ -+static int crypto_initted = 0; -+ -+/* -+ * Crypto drivers register themselves by allocating a slot in the -+ * crypto_drivers table with crypto_get_driverid() and then registering -+ * each algorithm they support with crypto_register() and crypto_kregister(). -+ */ -+ -+/* -+ * lock on driver table -+ * we track its state as spin_is_locked does not do anything on non-SMP boxes -+ */ -+static spinlock_t crypto_drivers_lock; -+static int crypto_drivers_locked; /* for non-SMP boxes */ -+ -+#define CRYPTO_DRIVER_LOCK() \ -+ ({ \ -+ spin_lock_irqsave(&crypto_drivers_lock, d_flags); \ -+ crypto_drivers_locked = 1; \ -+ dprintk("%s,%d: DRIVER_LOCK()\n", __FILE__, __LINE__); \ -+ }) -+#define CRYPTO_DRIVER_UNLOCK() \ -+ ({ \ -+ dprintk("%s,%d: DRIVER_UNLOCK()\n", __FILE__, __LINE__); \ -+ crypto_drivers_locked = 0; \ -+ spin_unlock_irqrestore(&crypto_drivers_lock, d_flags); \ -+ }) -+#define CRYPTO_DRIVER_ASSERT() \ -+ ({ \ -+ if (!crypto_drivers_locked) { \ -+ dprintk("%s,%d: DRIVER_ASSERT!\n", __FILE__, __LINE__); \ -+ } \ -+ }) -+ -+/* -+ * Crypto device/driver capabilities structure. -+ * -+ * Synchronization: -+ * (d) - protected by CRYPTO_DRIVER_LOCK() -+ * (q) - protected by CRYPTO_Q_LOCK() -+ * Not tagged fields are read-only. -+ */ -+struct cryptocap { -+ device_t cc_dev; /* (d) device/driver */ -+ u_int32_t cc_sessions; /* (d) # of sessions */ -+ u_int32_t cc_koperations; /* (d) # os asym operations */ -+ /* -+ * Largest possible operator length (in bits) for each type of -+ * encryption algorithm. XXX not used -+ */ -+ u_int16_t cc_max_op_len[CRYPTO_ALGORITHM_MAX + 1]; -+ u_int8_t cc_alg[CRYPTO_ALGORITHM_MAX + 1]; -+ u_int8_t cc_kalg[CRK_ALGORITHM_MAX + 1]; -+ -+ int cc_flags; /* (d) flags */ -+#define CRYPTOCAP_F_CLEANUP 0x80000000 /* needs resource cleanup */ -+ int cc_qblocked; /* (q) symmetric q blocked */ -+ int cc_kqblocked; /* (q) asymmetric q blocked */ -+ -+ int cc_unqblocked; /* (q) symmetric q blocked */ -+ int cc_unkqblocked; /* (q) asymmetric q blocked */ -+}; -+static struct cryptocap *crypto_drivers = NULL; -+static int crypto_drivers_num = 0; -+ -+/* -+ * There are two queues for crypto requests; one for symmetric (e.g. -+ * cipher) operations and one for asymmetric (e.g. MOD)operations. -+ * A single mutex is used to lock access to both queues. We could -+ * have one per-queue but having one simplifies handling of block/unblock -+ * operations. -+ */ -+static LIST_HEAD(crp_q); /* crypto request queue */ -+static LIST_HEAD(crp_kq); /* asym request queue */ -+ -+static spinlock_t crypto_q_lock; -+ -+int crypto_all_qblocked = 0; /* protect with Q_LOCK */ -+module_param(crypto_all_qblocked, int, 0444); -+MODULE_PARM_DESC(crypto_all_qblocked, "Are all crypto queues blocked"); -+ -+int crypto_all_kqblocked = 0; /* protect with Q_LOCK */ -+module_param(crypto_all_kqblocked, int, 0444); -+MODULE_PARM_DESC(crypto_all_kqblocked, "Are all asym crypto queues blocked"); -+ -+#define CRYPTO_Q_LOCK() \ -+ ({ \ -+ spin_lock_irqsave(&crypto_q_lock, q_flags); \ -+ dprintk("%s,%d: Q_LOCK()\n", __FILE__, __LINE__); \ -+ }) -+#define CRYPTO_Q_UNLOCK() \ -+ ({ \ -+ dprintk("%s,%d: Q_UNLOCK()\n", __FILE__, __LINE__); \ -+ spin_unlock_irqrestore(&crypto_q_lock, q_flags); \ -+ }) -+ -+/* -+ * There are two queues for processing completed crypto requests; one -+ * for the symmetric and one for the asymmetric ops. We only need one -+ * but have two to avoid type futzing (cryptop vs. cryptkop). A single -+ * mutex is used to lock access to both queues. Note that this lock -+ * must be separate from the lock on request queues to insure driver -+ * callbacks don't generate lock order reversals. -+ */ -+static LIST_HEAD(crp_ret_q); /* callback queues */ -+static LIST_HEAD(crp_ret_kq); -+ -+static spinlock_t crypto_ret_q_lock; -+#define CRYPTO_RETQ_LOCK() \ -+ ({ \ -+ spin_lock_irqsave(&crypto_ret_q_lock, r_flags); \ -+ dprintk("%s,%d: RETQ_LOCK\n", __FILE__, __LINE__); \ -+ }) -+#define CRYPTO_RETQ_UNLOCK() \ -+ ({ \ -+ dprintk("%s,%d: RETQ_UNLOCK\n", __FILE__, __LINE__); \ -+ spin_unlock_irqrestore(&crypto_ret_q_lock, r_flags); \ -+ }) -+#define CRYPTO_RETQ_EMPTY() (list_empty(&crp_ret_q) && list_empty(&crp_ret_kq)) -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) -+static kmem_cache_t *cryptop_zone; -+static kmem_cache_t *cryptodesc_zone; -+#else -+static struct kmem_cache *cryptop_zone; -+static struct kmem_cache *cryptodesc_zone; -+#endif -+ -+#define debug crypto_debug -+int crypto_debug = 0; -+module_param(crypto_debug, int, 0644); -+MODULE_PARM_DESC(crypto_debug, "Enable debug"); -+EXPORT_SYMBOL(crypto_debug); -+ -+/* -+ * Maximum number of outstanding crypto requests before we start -+ * failing requests. We need this to prevent DOS when too many -+ * requests are arriving for us to keep up. Otherwise we will -+ * run the system out of memory. Since crypto is slow, we are -+ * usually the bottleneck that needs to say, enough is enough. -+ * -+ * We cannot print errors when this condition occurs, we are already too -+ * slow, printing anything will just kill us -+ */ -+ -+static int crypto_q_cnt = 0; -+module_param(crypto_q_cnt, int, 0444); -+MODULE_PARM_DESC(crypto_q_cnt, -+ "Current number of outstanding crypto requests"); -+ -+static int crypto_q_max = 1000; -+module_param(crypto_q_max, int, 0644); -+MODULE_PARM_DESC(crypto_q_max, -+ "Maximum number of outstanding crypto requests"); -+ -+#define bootverbose crypto_verbose -+static int crypto_verbose = 0; -+module_param(crypto_verbose, int, 0644); -+MODULE_PARM_DESC(crypto_verbose, -+ "Enable verbose crypto startup"); -+ -+int crypto_usercrypto = 1; /* userland may do crypto reqs */ -+module_param(crypto_usercrypto, int, 0644); -+MODULE_PARM_DESC(crypto_usercrypto, -+ "Enable/disable user-mode access to crypto support"); -+ -+int crypto_userasymcrypto = 1; /* userland may do asym crypto reqs */ -+module_param(crypto_userasymcrypto, int, 0644); -+MODULE_PARM_DESC(crypto_userasymcrypto, -+ "Enable/disable user-mode access to asymmetric crypto support"); -+ -+int crypto_devallowsoft = 0; /* only use hardware crypto */ -+module_param(crypto_devallowsoft, int, 0644); -+MODULE_PARM_DESC(crypto_devallowsoft, -+ "Enable/disable use of software crypto support"); -+ -+/* -+ * This parameter controls the maximum number of crypto operations to -+ * do consecutively in the crypto kernel thread before scheduling to allow -+ * other processes to run. Without it, it is possible to get into a -+ * situation where the crypto thread never allows any other processes to run. -+ * Default to 1000 which should be less than one second. -+ */ -+static int crypto_max_loopcount = 1000; -+module_param(crypto_max_loopcount, int, 0644); -+MODULE_PARM_DESC(crypto_max_loopcount, -+ "Maximum number of crypto ops to do before yielding to other processes"); -+ -+#ifndef CONFIG_NR_CPUS -+#define CONFIG_NR_CPUS 1 -+#endif -+ -+static struct task_struct *cryptoproc[CONFIG_NR_CPUS]; -+static struct task_struct *cryptoretproc[CONFIG_NR_CPUS]; -+static DECLARE_WAIT_QUEUE_HEAD(cryptoproc_wait); -+static DECLARE_WAIT_QUEUE_HEAD(cryptoretproc_wait); -+ -+static int crypto_proc(void *arg); -+static int crypto_ret_proc(void *arg); -+static int crypto_invoke(struct cryptocap *cap, struct cryptop *crp, int hint); -+static int crypto_kinvoke(struct cryptkop *krp, int flags); -+static void crypto_exit(void); -+static int crypto_init(void); -+ -+static struct cryptostats cryptostats; -+ -+static struct cryptocap * -+crypto_checkdriver(u_int32_t hid) -+{ -+ if (crypto_drivers == NULL) -+ return NULL; -+ return (hid >= crypto_drivers_num ? NULL : &crypto_drivers[hid]); -+} -+ -+/* -+ * Compare a driver's list of supported algorithms against another -+ * list; return non-zero if all algorithms are supported. -+ */ -+static int -+driver_suitable(const struct cryptocap *cap, const struct cryptoini *cri) -+{ -+ const struct cryptoini *cr; -+ -+ /* See if all the algorithms are supported. */ -+ for (cr = cri; cr; cr = cr->cri_next) -+ if (cap->cc_alg[cr->cri_alg] == 0) -+ return 0; -+ return 1; -+} -+ -+ -+/* -+ * Select a driver for a new session that supports the specified -+ * algorithms and, optionally, is constrained according to the flags. -+ * The algorithm we use here is pretty stupid; just use the -+ * first driver that supports all the algorithms we need. If there -+ * are multiple drivers we choose the driver with the fewest active -+ * sessions. We prefer hardware-backed drivers to software ones. -+ * -+ * XXX We need more smarts here (in real life too, but that's -+ * XXX another story altogether). -+ */ -+static struct cryptocap * -+crypto_select_driver(const struct cryptoini *cri, int flags) -+{ -+ struct cryptocap *cap, *best; -+ int match, hid; -+ -+ CRYPTO_DRIVER_ASSERT(); -+ -+ /* -+ * Look first for hardware crypto devices if permitted. -+ */ -+ if (flags & CRYPTOCAP_F_HARDWARE) -+ match = CRYPTOCAP_F_HARDWARE; -+ else -+ match = CRYPTOCAP_F_SOFTWARE; -+ best = NULL; -+again: -+ for (hid = 0; hid < crypto_drivers_num; hid++) { -+ cap = &crypto_drivers[hid]; -+ /* -+ * If it's not initialized, is in the process of -+ * going away, or is not appropriate (hardware -+ * or software based on match), then skip. -+ */ -+ if (cap->cc_dev == NULL || -+ (cap->cc_flags & CRYPTOCAP_F_CLEANUP) || -+ (cap->cc_flags & match) == 0) -+ continue; -+ -+ /* verify all the algorithms are supported. */ -+ if (driver_suitable(cap, cri)) { -+ if (best == NULL || -+ cap->cc_sessions < best->cc_sessions) -+ best = cap; -+ } -+ } -+ if (best != NULL) -+ return best; -+ if (match == CRYPTOCAP_F_HARDWARE && (flags & CRYPTOCAP_F_SOFTWARE)) { -+ /* sort of an Algol 68-style for loop */ -+ match = CRYPTOCAP_F_SOFTWARE; -+ goto again; -+ } -+ return best; -+} -+ -+/* -+ * Create a new session. The crid argument specifies a crypto -+ * driver to use or constraints on a driver to select (hardware -+ * only, software only, either). Whatever driver is selected -+ * must be capable of the requested crypto algorithms. -+ */ -+int -+crypto_newsession(u_int64_t *sid, struct cryptoini *cri, int crid) -+{ -+ struct cryptocap *cap; -+ u_int32_t hid, lid; -+ int err; -+ unsigned long d_flags; -+ -+ CRYPTO_DRIVER_LOCK(); -+ if ((crid & (CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE)) == 0) { -+ /* -+ * Use specified driver; verify it is capable. -+ */ -+ cap = crypto_checkdriver(crid); -+ if (cap != NULL && !driver_suitable(cap, cri)) -+ cap = NULL; -+ } else { -+ /* -+ * No requested driver; select based on crid flags. -+ */ -+ cap = crypto_select_driver(cri, crid); -+ /* -+ * if NULL then can't do everything in one session. -+ * XXX Fix this. We need to inject a "virtual" session -+ * XXX layer right about here. -+ */ -+ } -+ if (cap != NULL) { -+ /* Call the driver initialization routine. */ -+ hid = cap - crypto_drivers; -+ lid = hid; /* Pass the driver ID. */ -+ cap->cc_sessions++; -+ CRYPTO_DRIVER_UNLOCK(); -+ err = CRYPTODEV_NEWSESSION(cap->cc_dev, &lid, cri); -+ CRYPTO_DRIVER_LOCK(); -+ if (err == 0) { -+ (*sid) = (cap->cc_flags & 0xff000000) -+ | (hid & 0x00ffffff); -+ (*sid) <<= 32; -+ (*sid) |= (lid & 0xffffffff); -+ } else -+ cap->cc_sessions--; -+ } else -+ err = EINVAL; -+ CRYPTO_DRIVER_UNLOCK(); -+ return err; -+} -+ -+static void -+crypto_remove(struct cryptocap *cap) -+{ -+ CRYPTO_DRIVER_ASSERT(); -+ if (cap->cc_sessions == 0 && cap->cc_koperations == 0) -+ bzero(cap, sizeof(*cap)); -+} -+ -+/* -+ * Delete an existing session (or a reserved session on an unregistered -+ * driver). -+ */ -+int -+crypto_freesession(u_int64_t sid) -+{ -+ struct cryptocap *cap; -+ u_int32_t hid; -+ int err = 0; -+ unsigned long d_flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ CRYPTO_DRIVER_LOCK(); -+ -+ if (crypto_drivers == NULL) { -+ err = EINVAL; -+ goto done; -+ } -+ -+ /* Determine two IDs. */ -+ hid = CRYPTO_SESID2HID(sid); -+ -+ if (hid >= crypto_drivers_num) { -+ dprintk("%s - INVALID DRIVER NUM %d\n", __FUNCTION__, hid); -+ err = ENOENT; -+ goto done; -+ } -+ cap = &crypto_drivers[hid]; -+ -+ if (cap->cc_dev) { -+ CRYPTO_DRIVER_UNLOCK(); -+ /* Call the driver cleanup routine, if available, unlocked. */ -+ err = CRYPTODEV_FREESESSION(cap->cc_dev, sid); -+ CRYPTO_DRIVER_LOCK(); -+ } -+ -+ if (cap->cc_sessions) -+ cap->cc_sessions--; -+ -+ if (cap->cc_flags & CRYPTOCAP_F_CLEANUP) -+ crypto_remove(cap); -+ -+done: -+ CRYPTO_DRIVER_UNLOCK(); -+ return err; -+} -+ -+/* -+ * Return an unused driver id. Used by drivers prior to registering -+ * support for the algorithms they handle. -+ */ -+int32_t -+crypto_get_driverid(device_t dev, int flags) -+{ -+ struct cryptocap *newdrv; -+ int i; -+ unsigned long d_flags; -+ -+ if ((flags & (CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE)) == 0) { -+ printf("%s: no flags specified when registering driver\n", -+ device_get_nameunit(dev)); -+ return -1; -+ } -+ -+ CRYPTO_DRIVER_LOCK(); -+ -+ for (i = 0; i < crypto_drivers_num; i++) { -+ if (crypto_drivers[i].cc_dev == NULL && -+ (crypto_drivers[i].cc_flags & CRYPTOCAP_F_CLEANUP) == 0) { -+ break; -+ } -+ } -+ -+ /* Out of entries, allocate some more. */ -+ if (i == crypto_drivers_num) { -+ /* Be careful about wrap-around. */ -+ if (2 * crypto_drivers_num <= crypto_drivers_num) { -+ CRYPTO_DRIVER_UNLOCK(); -+ printk("crypto: driver count wraparound!\n"); -+ return -1; -+ } -+ -+ newdrv = kmalloc(2 * crypto_drivers_num * sizeof(struct cryptocap), -+ GFP_KERNEL); -+ if (newdrv == NULL) { -+ CRYPTO_DRIVER_UNLOCK(); -+ printk("crypto: no space to expand driver table!\n"); -+ return -1; -+ } -+ -+ memcpy(newdrv, crypto_drivers, -+ crypto_drivers_num * sizeof(struct cryptocap)); -+ memset(&newdrv[crypto_drivers_num], 0, -+ crypto_drivers_num * sizeof(struct cryptocap)); -+ -+ crypto_drivers_num *= 2; -+ -+ kfree(crypto_drivers); -+ crypto_drivers = newdrv; -+ } -+ -+ /* NB: state is zero'd on free */ -+ crypto_drivers[i].cc_sessions = 1; /* Mark */ -+ crypto_drivers[i].cc_dev = dev; -+ crypto_drivers[i].cc_flags = flags; -+ if (bootverbose) -+ printf("crypto: assign %s driver id %u, flags %u\n", -+ device_get_nameunit(dev), i, flags); -+ -+ CRYPTO_DRIVER_UNLOCK(); -+ -+ return i; -+} -+ -+/* -+ * Lookup a driver by name. We match against the full device -+ * name and unit, and against just the name. The latter gives -+ * us a simple widlcarding by device name. On success return the -+ * driver/hardware identifier; otherwise return -1. -+ */ -+int -+crypto_find_driver(const char *match) -+{ -+ int i, len = strlen(match); -+ unsigned long d_flags; -+ -+ CRYPTO_DRIVER_LOCK(); -+ for (i = 0; i < crypto_drivers_num; i++) { -+ device_t dev = crypto_drivers[i].cc_dev; -+ if (dev == NULL || -+ (crypto_drivers[i].cc_flags & CRYPTOCAP_F_CLEANUP)) -+ continue; -+ if (strncmp(match, device_get_nameunit(dev), len) == 0 || -+ strncmp(match, device_get_name(dev), len) == 0) -+ break; -+ } -+ CRYPTO_DRIVER_UNLOCK(); -+ return i < crypto_drivers_num ? i : -1; -+} -+ -+/* -+ * Return the device_t for the specified driver or NULL -+ * if the driver identifier is invalid. -+ */ -+device_t -+crypto_find_device_byhid(int hid) -+{ -+ struct cryptocap *cap = crypto_checkdriver(hid); -+ return cap != NULL ? cap->cc_dev : NULL; -+} -+ -+/* -+ * Return the device/driver capabilities. -+ */ -+int -+crypto_getcaps(int hid) -+{ -+ struct cryptocap *cap = crypto_checkdriver(hid); -+ return cap != NULL ? cap->cc_flags : 0; -+} -+ -+/* -+ * Register support for a key-related algorithm. This routine -+ * is called once for each algorithm supported a driver. -+ */ -+int -+crypto_kregister(u_int32_t driverid, int kalg, u_int32_t flags) -+{ -+ struct cryptocap *cap; -+ int err; -+ unsigned long d_flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ CRYPTO_DRIVER_LOCK(); -+ -+ cap = crypto_checkdriver(driverid); -+ if (cap != NULL && -+ (CRK_ALGORITM_MIN <= kalg && kalg <= CRK_ALGORITHM_MAX)) { -+ /* -+ * XXX Do some performance testing to determine placing. -+ * XXX We probably need an auxiliary data structure that -+ * XXX describes relative performances. -+ */ -+ -+ cap->cc_kalg[kalg] = flags | CRYPTO_ALG_FLAG_SUPPORTED; -+ if (bootverbose) -+ printf("crypto: %s registers key alg %u flags %u\n" -+ , device_get_nameunit(cap->cc_dev) -+ , kalg -+ , flags -+ ); -+ err = 0; -+ } else -+ err = EINVAL; -+ -+ CRYPTO_DRIVER_UNLOCK(); -+ return err; -+} -+ -+/* -+ * Register support for a non-key-related algorithm. This routine -+ * is called once for each such algorithm supported by a driver. -+ */ -+int -+crypto_register(u_int32_t driverid, int alg, u_int16_t maxoplen, -+ u_int32_t flags) -+{ -+ struct cryptocap *cap; -+ int err; -+ unsigned long d_flags; -+ -+ dprintk("%s(id=0x%x, alg=%d, maxoplen=%d, flags=0x%x)\n", __FUNCTION__, -+ driverid, alg, maxoplen, flags); -+ -+ CRYPTO_DRIVER_LOCK(); -+ -+ cap = crypto_checkdriver(driverid); -+ /* NB: algorithms are in the range [1..max] */ -+ if (cap != NULL && -+ (CRYPTO_ALGORITHM_MIN <= alg && alg <= CRYPTO_ALGORITHM_MAX)) { -+ /* -+ * XXX Do some performance testing to determine placing. -+ * XXX We probably need an auxiliary data structure that -+ * XXX describes relative performances. -+ */ -+ -+ cap->cc_alg[alg] = flags | CRYPTO_ALG_FLAG_SUPPORTED; -+ cap->cc_max_op_len[alg] = maxoplen; -+ if (bootverbose) -+ printf("crypto: %s registers alg %u flags %u maxoplen %u\n" -+ , device_get_nameunit(cap->cc_dev) -+ , alg -+ , flags -+ , maxoplen -+ ); -+ cap->cc_sessions = 0; /* Unmark */ -+ err = 0; -+ } else -+ err = EINVAL; -+ -+ CRYPTO_DRIVER_UNLOCK(); -+ return err; -+} -+ -+static void -+driver_finis(struct cryptocap *cap) -+{ -+ u_int32_t ses, kops; -+ -+ CRYPTO_DRIVER_ASSERT(); -+ -+ ses = cap->cc_sessions; -+ kops = cap->cc_koperations; -+ bzero(cap, sizeof(*cap)); -+ if (ses != 0 || kops != 0) { -+ /* -+ * If there are pending sessions, -+ * just mark as invalid. -+ */ -+ cap->cc_flags |= CRYPTOCAP_F_CLEANUP; -+ cap->cc_sessions = ses; -+ cap->cc_koperations = kops; -+ } -+} -+ -+/* -+ * Unregister a crypto driver. If there are pending sessions using it, -+ * leave enough information around so that subsequent calls using those -+ * sessions will correctly detect the driver has been unregistered and -+ * reroute requests. -+ */ -+int -+crypto_unregister(u_int32_t driverid, int alg) -+{ -+ struct cryptocap *cap; -+ int i, err; -+ unsigned long d_flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ CRYPTO_DRIVER_LOCK(); -+ -+ cap = crypto_checkdriver(driverid); -+ if (cap != NULL && -+ (CRYPTO_ALGORITHM_MIN <= alg && alg <= CRYPTO_ALGORITHM_MAX) && -+ cap->cc_alg[alg] != 0) { -+ cap->cc_alg[alg] = 0; -+ cap->cc_max_op_len[alg] = 0; -+ -+ /* Was this the last algorithm ? */ -+ for (i = 1; i <= CRYPTO_ALGORITHM_MAX; i++) -+ if (cap->cc_alg[i] != 0) -+ break; -+ -+ if (i == CRYPTO_ALGORITHM_MAX + 1) -+ driver_finis(cap); -+ err = 0; -+ } else -+ err = EINVAL; -+ CRYPTO_DRIVER_UNLOCK(); -+ return err; -+} -+ -+/* -+ * Unregister all algorithms associated with a crypto driver. -+ * If there are pending sessions using it, leave enough information -+ * around so that subsequent calls using those sessions will -+ * correctly detect the driver has been unregistered and reroute -+ * requests. -+ */ -+int -+crypto_unregister_all(u_int32_t driverid) -+{ -+ struct cryptocap *cap; -+ int err; -+ unsigned long d_flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ CRYPTO_DRIVER_LOCK(); -+ cap = crypto_checkdriver(driverid); -+ if (cap != NULL) { -+ driver_finis(cap); -+ err = 0; -+ } else -+ err = EINVAL; -+ CRYPTO_DRIVER_UNLOCK(); -+ -+ return err; -+} -+ -+/* -+ * Clear blockage on a driver. The what parameter indicates whether -+ * the driver is now ready for cryptop's and/or cryptokop's. -+ */ -+int -+crypto_unblock(u_int32_t driverid, int what) -+{ -+ struct cryptocap *cap; -+ int err; -+ unsigned long q_flags; -+ -+ CRYPTO_Q_LOCK(); -+ cap = crypto_checkdriver(driverid); -+ if (cap != NULL) { -+ if (what & CRYPTO_SYMQ) { -+ cap->cc_qblocked = 0; -+ cap->cc_unqblocked = 0; -+ crypto_all_qblocked = 0; -+ } -+ if (what & CRYPTO_ASYMQ) { -+ cap->cc_kqblocked = 0; -+ cap->cc_unkqblocked = 0; -+ crypto_all_kqblocked = 0; -+ } -+ wake_up_interruptible(&cryptoproc_wait); -+ err = 0; -+ } else -+ err = EINVAL; -+ CRYPTO_Q_UNLOCK(); //DAVIDM should this be a driver lock -+ -+ return err; -+} -+ -+/* -+ * Add a crypto request to a queue, to be processed by the kernel thread. -+ */ -+int -+crypto_dispatch(struct cryptop *crp) -+{ -+ struct cryptocap *cap; -+ int result = -1; -+ unsigned long q_flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ cryptostats.cs_ops++; -+ -+ CRYPTO_Q_LOCK(); -+ if (crypto_q_cnt >= crypto_q_max) { -+ cryptostats.cs_drops++; -+ CRYPTO_Q_UNLOCK(); -+ return ENOMEM; -+ } -+ crypto_q_cnt++; -+ -+ /* make sure we are starting a fresh run on this crp. */ -+ crp->crp_flags &= ~CRYPTO_F_DONE; -+ crp->crp_etype = 0; -+ -+ /* -+ * Caller marked the request to be processed immediately; dispatch -+ * it directly to the driver unless the driver is currently blocked. -+ */ -+ if ((crp->crp_flags & CRYPTO_F_BATCH) == 0) { -+ int hid = CRYPTO_SESID2HID(crp->crp_sid); -+ cap = crypto_checkdriver(hid); -+ /* Driver cannot disappear when there is an active session. */ -+ KASSERT(cap != NULL, ("%s: Driver disappeared.", __func__)); -+ if (!cap->cc_qblocked) { -+ crypto_all_qblocked = 0; -+ crypto_drivers[hid].cc_unqblocked = 1; -+ CRYPTO_Q_UNLOCK(); -+ result = crypto_invoke(cap, crp, 0); -+ CRYPTO_Q_LOCK(); -+ if (result == ERESTART) -+ if (crypto_drivers[hid].cc_unqblocked) -+ crypto_drivers[hid].cc_qblocked = 1; -+ crypto_drivers[hid].cc_unqblocked = 0; -+ } -+ } -+ if (result == ERESTART) { -+ /* -+ * The driver ran out of resources, mark the -+ * driver ``blocked'' for cryptop's and put -+ * the request back in the queue. It would -+ * best to put the request back where we got -+ * it but that's hard so for now we put it -+ * at the front. This should be ok; putting -+ * it at the end does not work. -+ */ -+ list_add(&crp->crp_next, &crp_q); -+ cryptostats.cs_blocks++; -+ result = 0; -+ } else if (result == -1) { -+ TAILQ_INSERT_TAIL(&crp_q, crp, crp_next); -+ result = 0; -+ } -+ wake_up_interruptible(&cryptoproc_wait); -+ CRYPTO_Q_UNLOCK(); -+ return result; -+} -+ -+/* -+ * Add an asymetric crypto request to a queue, -+ * to be processed by the kernel thread. -+ */ -+int -+crypto_kdispatch(struct cryptkop *krp) -+{ -+ int error; -+ unsigned long q_flags; -+ -+ cryptostats.cs_kops++; -+ -+ error = crypto_kinvoke(krp, krp->krp_crid); -+ if (error == ERESTART) { -+ CRYPTO_Q_LOCK(); -+ TAILQ_INSERT_TAIL(&crp_kq, krp, krp_next); -+ wake_up_interruptible(&cryptoproc_wait); -+ CRYPTO_Q_UNLOCK(); -+ error = 0; -+ } -+ return error; -+} -+ -+/* -+ * Verify a driver is suitable for the specified operation. -+ */ -+static __inline int -+kdriver_suitable(const struct cryptocap *cap, const struct cryptkop *krp) -+{ -+ return (cap->cc_kalg[krp->krp_op] & CRYPTO_ALG_FLAG_SUPPORTED) != 0; -+} -+ -+/* -+ * Select a driver for an asym operation. The driver must -+ * support the necessary algorithm. The caller can constrain -+ * which device is selected with the flags parameter. The -+ * algorithm we use here is pretty stupid; just use the first -+ * driver that supports the algorithms we need. If there are -+ * multiple suitable drivers we choose the driver with the -+ * fewest active operations. We prefer hardware-backed -+ * drivers to software ones when either may be used. -+ */ -+static struct cryptocap * -+crypto_select_kdriver(const struct cryptkop *krp, int flags) -+{ -+ struct cryptocap *cap, *best, *blocked; -+ int match, hid; -+ -+ CRYPTO_DRIVER_ASSERT(); -+ -+ /* -+ * Look first for hardware crypto devices if permitted. -+ */ -+ if (flags & CRYPTOCAP_F_HARDWARE) -+ match = CRYPTOCAP_F_HARDWARE; -+ else -+ match = CRYPTOCAP_F_SOFTWARE; -+ best = NULL; -+ blocked = NULL; -+again: -+ for (hid = 0; hid < crypto_drivers_num; hid++) { -+ cap = &crypto_drivers[hid]; -+ /* -+ * If it's not initialized, is in the process of -+ * going away, or is not appropriate (hardware -+ * or software based on match), then skip. -+ */ -+ if (cap->cc_dev == NULL || -+ (cap->cc_flags & CRYPTOCAP_F_CLEANUP) || -+ (cap->cc_flags & match) == 0) -+ continue; -+ -+ /* verify all the algorithms are supported. */ -+ if (kdriver_suitable(cap, krp)) { -+ if (best == NULL || -+ cap->cc_koperations < best->cc_koperations) -+ best = cap; -+ } -+ } -+ if (best != NULL) -+ return best; -+ if (match == CRYPTOCAP_F_HARDWARE && (flags & CRYPTOCAP_F_SOFTWARE)) { -+ /* sort of an Algol 68-style for loop */ -+ match = CRYPTOCAP_F_SOFTWARE; -+ goto again; -+ } -+ return best; -+} -+ -+/* -+ * Dispatch an assymetric crypto request. -+ */ -+static int -+crypto_kinvoke(struct cryptkop *krp, int crid) -+{ -+ struct cryptocap *cap = NULL; -+ int error; -+ unsigned long d_flags; -+ -+ KASSERT(krp != NULL, ("%s: krp == NULL", __func__)); -+ KASSERT(krp->krp_callback != NULL, -+ ("%s: krp->crp_callback == NULL", __func__)); -+ -+ CRYPTO_DRIVER_LOCK(); -+ if ((crid & (CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE)) == 0) { -+ cap = crypto_checkdriver(crid); -+ if (cap != NULL) { -+ /* -+ * Driver present, it must support the necessary -+ * algorithm and, if s/w drivers are excluded, -+ * it must be registered as hardware-backed. -+ */ -+ if (!kdriver_suitable(cap, krp) || -+ (!crypto_devallowsoft && -+ (cap->cc_flags & CRYPTOCAP_F_HARDWARE) == 0)) -+ cap = NULL; -+ } -+ } else { -+ /* -+ * No requested driver; select based on crid flags. -+ */ -+ if (!crypto_devallowsoft) /* NB: disallow s/w drivers */ -+ crid &= ~CRYPTOCAP_F_SOFTWARE; -+ cap = crypto_select_kdriver(krp, crid); -+ } -+ if (cap != NULL && !cap->cc_kqblocked) { -+ krp->krp_hid = cap - crypto_drivers; -+ cap->cc_koperations++; -+ CRYPTO_DRIVER_UNLOCK(); -+ error = CRYPTODEV_KPROCESS(cap->cc_dev, krp, 0); -+ CRYPTO_DRIVER_LOCK(); -+ if (error == ERESTART) { -+ cap->cc_koperations--; -+ CRYPTO_DRIVER_UNLOCK(); -+ return (error); -+ } -+ /* return the actual device used */ -+ krp->krp_crid = krp->krp_hid; -+ } else { -+ /* -+ * NB: cap is !NULL if device is blocked; in -+ * that case return ERESTART so the operation -+ * is resubmitted if possible. -+ */ -+ error = (cap == NULL) ? ENODEV : ERESTART; -+ } -+ CRYPTO_DRIVER_UNLOCK(); -+ -+ if (error) { -+ krp->krp_status = error; -+ crypto_kdone(krp); -+ } -+ return 0; -+} -+ -+ -+/* -+ * Dispatch a crypto request to the appropriate crypto devices. -+ */ -+static int -+crypto_invoke(struct cryptocap *cap, struct cryptop *crp, int hint) -+{ -+ KASSERT(crp != NULL, ("%s: crp == NULL", __func__)); -+ KASSERT(crp->crp_callback != NULL, -+ ("%s: crp->crp_callback == NULL", __func__)); -+ KASSERT(crp->crp_desc != NULL, ("%s: crp->crp_desc == NULL", __func__)); -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+#ifdef CRYPTO_TIMING -+ if (crypto_timing) -+ crypto_tstat(&cryptostats.cs_invoke, &crp->crp_tstamp); -+#endif -+ if (cap->cc_flags & CRYPTOCAP_F_CLEANUP) { -+ struct cryptodesc *crd; -+ u_int64_t nid; -+ -+ /* -+ * Driver has unregistered; migrate the session and return -+ * an error to the caller so they'll resubmit the op. -+ * -+ * XXX: What if there are more already queued requests for this -+ * session? -+ */ -+ crypto_freesession(crp->crp_sid); -+ -+ for (crd = crp->crp_desc; crd->crd_next; crd = crd->crd_next) -+ crd->CRD_INI.cri_next = &(crd->crd_next->CRD_INI); -+ -+ /* XXX propagate flags from initial session? */ -+ if (crypto_newsession(&nid, &(crp->crp_desc->CRD_INI), -+ CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE) == 0) -+ crp->crp_sid = nid; -+ -+ crp->crp_etype = EAGAIN; -+ crypto_done(crp); -+ return 0; -+ } else { -+ /* -+ * Invoke the driver to process the request. -+ */ -+ return CRYPTODEV_PROCESS(cap->cc_dev, crp, hint); -+ } -+} -+ -+/* -+ * Release a set of crypto descriptors. -+ */ -+void -+crypto_freereq(struct cryptop *crp) -+{ -+ struct cryptodesc *crd; -+ -+ if (crp == NULL) -+ return; -+ -+#ifdef DIAGNOSTIC -+ { -+ struct cryptop *crp2; -+ unsigned long q_flags; -+ -+ CRYPTO_Q_LOCK(); -+ TAILQ_FOREACH(crp2, &crp_q, crp_next) { -+ KASSERT(crp2 != crp, -+ ("Freeing cryptop from the crypto queue (%p).", -+ crp)); -+ } -+ CRYPTO_Q_UNLOCK(); -+ CRYPTO_RETQ_LOCK(); -+ TAILQ_FOREACH(crp2, &crp_ret_q, crp_next) { -+ KASSERT(crp2 != crp, -+ ("Freeing cryptop from the return queue (%p).", -+ crp)); -+ } -+ CRYPTO_RETQ_UNLOCK(); -+ } -+#endif -+ -+ while ((crd = crp->crp_desc) != NULL) { -+ crp->crp_desc = crd->crd_next; -+ kmem_cache_free(cryptodesc_zone, crd); -+ } -+ kmem_cache_free(cryptop_zone, crp); -+} -+ -+/* -+ * Acquire a set of crypto descriptors. -+ */ -+struct cryptop * -+crypto_getreq(int num) -+{ -+ struct cryptodesc *crd; -+ struct cryptop *crp; -+ -+ crp = kmem_cache_alloc(cryptop_zone, SLAB_ATOMIC); -+ if (crp != NULL) { -+ memset(crp, 0, sizeof(*crp)); -+ INIT_LIST_HEAD(&crp->crp_next); -+ init_waitqueue_head(&crp->crp_waitq); -+ while (num--) { -+ crd = kmem_cache_alloc(cryptodesc_zone, SLAB_ATOMIC); -+ if (crd == NULL) { -+ crypto_freereq(crp); -+ return NULL; -+ } -+ memset(crd, 0, sizeof(*crd)); -+ crd->crd_next = crp->crp_desc; -+ crp->crp_desc = crd; -+ } -+ } -+ return crp; -+} -+ -+/* -+ * Invoke the callback on behalf of the driver. -+ */ -+void -+crypto_done(struct cryptop *crp) -+{ -+ unsigned long q_flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if ((crp->crp_flags & CRYPTO_F_DONE) == 0) { -+ crp->crp_flags |= CRYPTO_F_DONE; -+ CRYPTO_Q_LOCK(); -+ crypto_q_cnt--; -+ CRYPTO_Q_UNLOCK(); -+ } else -+ printk("crypto: crypto_done op already done, flags 0x%x", -+ crp->crp_flags); -+ if (crp->crp_etype != 0) -+ cryptostats.cs_errs++; -+ /* -+ * CBIMM means unconditionally do the callback immediately; -+ * CBIFSYNC means do the callback immediately only if the -+ * operation was done synchronously. Both are used to avoid -+ * doing extraneous context switches; the latter is mostly -+ * used with the software crypto driver. -+ */ -+ if ((crp->crp_flags & CRYPTO_F_CBIMM) || -+ ((crp->crp_flags & CRYPTO_F_CBIFSYNC) && -+ (CRYPTO_SESID2CAPS(crp->crp_sid) & CRYPTOCAP_F_SYNC))) { -+ /* -+ * Do the callback directly. This is ok when the -+ * callback routine does very little (e.g. the -+ * /dev/crypto callback method just does a wakeup). -+ */ -+ crp->crp_callback(crp); -+ } else { -+ unsigned long r_flags; -+ /* -+ * Normal case; queue the callback for the thread. -+ */ -+ CRYPTO_RETQ_LOCK(); -+ wake_up_interruptible(&cryptoretproc_wait);/* shared wait channel */ -+ TAILQ_INSERT_TAIL(&crp_ret_q, crp, crp_next); -+ CRYPTO_RETQ_UNLOCK(); -+ } -+} -+ -+/* -+ * Invoke the callback on behalf of the driver. -+ */ -+void -+crypto_kdone(struct cryptkop *krp) -+{ -+ struct cryptocap *cap; -+ unsigned long d_flags; -+ -+ if ((krp->krp_flags & CRYPTO_KF_DONE) != 0) -+ printk("crypto: crypto_kdone op already done, flags 0x%x", -+ krp->krp_flags); -+ krp->krp_flags |= CRYPTO_KF_DONE; -+ if (krp->krp_status != 0) -+ cryptostats.cs_kerrs++; -+ -+ CRYPTO_DRIVER_LOCK(); -+ /* XXX: What if driver is loaded in the meantime? */ -+ if (krp->krp_hid < crypto_drivers_num) { -+ cap = &crypto_drivers[krp->krp_hid]; -+ cap->cc_koperations--; -+ KASSERT(cap->cc_koperations >= 0, ("cc_koperations < 0")); -+ if (cap->cc_flags & CRYPTOCAP_F_CLEANUP) -+ crypto_remove(cap); -+ } -+ CRYPTO_DRIVER_UNLOCK(); -+ -+ /* -+ * CBIMM means unconditionally do the callback immediately; -+ * This is used to avoid doing extraneous context switches -+ */ -+ if ((krp->krp_flags & CRYPTO_KF_CBIMM)) { -+ /* -+ * Do the callback directly. This is ok when the -+ * callback routine does very little (e.g. the -+ * /dev/crypto callback method just does a wakeup). -+ */ -+ krp->krp_callback(krp); -+ } else { -+ unsigned long r_flags; -+ /* -+ * Normal case; queue the callback for the thread. -+ */ -+ CRYPTO_RETQ_LOCK(); -+ wake_up_interruptible(&cryptoretproc_wait);/* shared wait channel */ -+ TAILQ_INSERT_TAIL(&crp_ret_kq, krp, krp_next); -+ CRYPTO_RETQ_UNLOCK(); -+ } -+} -+ -+int -+crypto_getfeat(int *featp) -+{ -+ int hid, kalg, feat = 0; -+ unsigned long d_flags; -+ -+ CRYPTO_DRIVER_LOCK(); -+ for (hid = 0; hid < crypto_drivers_num; hid++) { -+ const struct cryptocap *cap = &crypto_drivers[hid]; -+ -+ if ((cap->cc_flags & CRYPTOCAP_F_SOFTWARE) && -+ !crypto_devallowsoft) { -+ continue; -+ } -+ for (kalg = 0; kalg < CRK_ALGORITHM_MAX; kalg++) -+ if (cap->cc_kalg[kalg] & CRYPTO_ALG_FLAG_SUPPORTED) -+ feat |= 1 << kalg; -+ } -+ CRYPTO_DRIVER_UNLOCK(); -+ *featp = feat; -+ return (0); -+} -+ -+/* -+ * Crypto thread, dispatches crypto requests. -+ */ -+static int -+crypto_proc(void *arg) -+{ -+ struct cryptop *crp, *submit; -+ struct cryptkop *krp, *krpp; -+ struct cryptocap *cap; -+ u_int32_t hid; -+ int result, hint; -+ unsigned long q_flags; -+ int loopcount = 0; -+ -+ set_current_state(TASK_INTERRUPTIBLE); -+ -+ CRYPTO_Q_LOCK(); -+ for (;;) { -+ /* -+ * we need to make sure we don't get into a busy loop with nothing -+ * to do, the two crypto_all_*blocked vars help us find out when -+ * we are all full and can do nothing on any driver or Q. If so we -+ * wait for an unblock. -+ */ -+ crypto_all_qblocked = !list_empty(&crp_q); -+ -+ /* -+ * Find the first element in the queue that can be -+ * processed and look-ahead to see if multiple ops -+ * are ready for the same driver. -+ */ -+ submit = NULL; -+ hint = 0; -+ list_for_each_entry(crp, &crp_q, crp_next) { -+ hid = CRYPTO_SESID2HID(crp->crp_sid); -+ cap = crypto_checkdriver(hid); -+ /* -+ * Driver cannot disappear when there is an active -+ * session. -+ */ -+ KASSERT(cap != NULL, ("%s:%u Driver disappeared.", -+ __func__, __LINE__)); -+ if (cap == NULL || cap->cc_dev == NULL) { -+ /* Op needs to be migrated, process it. */ -+ if (submit == NULL) -+ submit = crp; -+ break; -+ } -+ if (!cap->cc_qblocked) { -+ if (submit != NULL) { -+ /* -+ * We stop on finding another op, -+ * regardless whether its for the same -+ * driver or not. We could keep -+ * searching the queue but it might be -+ * better to just use a per-driver -+ * queue instead. -+ */ -+ if (CRYPTO_SESID2HID(submit->crp_sid) == hid) -+ hint = CRYPTO_HINT_MORE; -+ break; -+ } else { -+ submit = crp; -+ if ((submit->crp_flags & CRYPTO_F_BATCH) == 0) -+ break; -+ /* keep scanning for more are q'd */ -+ } -+ } -+ } -+ if (submit != NULL) { -+ hid = CRYPTO_SESID2HID(submit->crp_sid); -+ crypto_all_qblocked = 0; -+ list_del(&submit->crp_next); -+ crypto_drivers[hid].cc_unqblocked = 1; -+ cap = crypto_checkdriver(hid); -+ CRYPTO_Q_UNLOCK(); -+ KASSERT(cap != NULL, ("%s:%u Driver disappeared.", -+ __func__, __LINE__)); -+ result = crypto_invoke(cap, submit, hint); -+ CRYPTO_Q_LOCK(); -+ if (result == ERESTART) { -+ /* -+ * The driver ran out of resources, mark the -+ * driver ``blocked'' for cryptop's and put -+ * the request back in the queue. It would -+ * best to put the request back where we got -+ * it but that's hard so for now we put it -+ * at the front. This should be ok; putting -+ * it at the end does not work. -+ */ -+ /* XXX validate sid again? */ -+ list_add(&submit->crp_next, &crp_q); -+ cryptostats.cs_blocks++; -+ if (crypto_drivers[hid].cc_unqblocked) -+ crypto_drivers[hid].cc_qblocked=0; -+ crypto_drivers[hid].cc_unqblocked=0; -+ } -+ crypto_drivers[hid].cc_unqblocked = 0; -+ } -+ -+ crypto_all_kqblocked = !list_empty(&crp_kq); -+ -+ /* As above, but for key ops */ -+ krp = NULL; -+ list_for_each_entry(krpp, &crp_kq, krp_next) { -+ cap = crypto_checkdriver(krpp->krp_hid); -+ if (cap == NULL || cap->cc_dev == NULL) { -+ /* -+ * Operation needs to be migrated, invalidate -+ * the assigned device so it will reselect a -+ * new one below. Propagate the original -+ * crid selection flags if supplied. -+ */ -+ krp->krp_hid = krp->krp_crid & -+ (CRYPTOCAP_F_SOFTWARE|CRYPTOCAP_F_HARDWARE); -+ if (krp->krp_hid == 0) -+ krp->krp_hid = -+ CRYPTOCAP_F_SOFTWARE|CRYPTOCAP_F_HARDWARE; -+ break; -+ } -+ if (!cap->cc_kqblocked) { -+ krp = krpp; -+ break; -+ } -+ } -+ if (krp != NULL) { -+ crypto_all_kqblocked = 0; -+ list_del(&krp->krp_next); -+ crypto_drivers[krp->krp_hid].cc_kqblocked = 1; -+ CRYPTO_Q_UNLOCK(); -+ result = crypto_kinvoke(krp, krp->krp_hid); -+ CRYPTO_Q_LOCK(); -+ if (result == ERESTART) { -+ /* -+ * The driver ran out of resources, mark the -+ * driver ``blocked'' for cryptkop's and put -+ * the request back in the queue. It would -+ * best to put the request back where we got -+ * it but that's hard so for now we put it -+ * at the front. This should be ok; putting -+ * it at the end does not work. -+ */ -+ /* XXX validate sid again? */ -+ list_add(&krp->krp_next, &crp_kq); -+ cryptostats.cs_kblocks++; -+ } else -+ crypto_drivers[krp->krp_hid].cc_kqblocked = 0; -+ } -+ -+ if (submit == NULL && krp == NULL) { -+ /* -+ * Nothing more to be processed. Sleep until we're -+ * woken because there are more ops to process. -+ * This happens either by submission or by a driver -+ * becoming unblocked and notifying us through -+ * crypto_unblock. Note that when we wakeup we -+ * start processing each queue again from the -+ * front. It's not clear that it's important to -+ * preserve this ordering since ops may finish -+ * out of order if dispatched to different devices -+ * and some become blocked while others do not. -+ */ -+ dprintk("%s - sleeping (qe=%d qb=%d kqe=%d kqb=%d)\n", -+ __FUNCTION__, -+ list_empty(&crp_q), crypto_all_qblocked, -+ list_empty(&crp_kq), crypto_all_kqblocked); -+ loopcount = 0; -+ CRYPTO_Q_UNLOCK(); -+ wait_event_interruptible(cryptoproc_wait, -+ !(list_empty(&crp_q) || crypto_all_qblocked) || -+ !(list_empty(&crp_kq) || crypto_all_kqblocked) || -+ kthread_should_stop()); -+ if (signal_pending (current)) { -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ spin_lock_irq(¤t->sigmask_lock); -+#endif -+ flush_signals(current); -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ spin_unlock_irq(¤t->sigmask_lock); -+#endif -+ } -+ CRYPTO_Q_LOCK(); -+ dprintk("%s - awake\n", __FUNCTION__); -+ if (kthread_should_stop()) -+ break; -+ cryptostats.cs_intrs++; -+ } else if (loopcount > crypto_max_loopcount) { -+ /* -+ * Give other processes a chance to run if we've -+ * been using the CPU exclusively for a while. -+ */ -+ loopcount = 0; -+ CRYPTO_Q_UNLOCK(); -+ schedule(); -+ CRYPTO_Q_LOCK(); -+ } -+ loopcount++; -+ } -+ CRYPTO_Q_UNLOCK(); -+ return 0; -+} -+ -+/* -+ * Crypto returns thread, does callbacks for processed crypto requests. -+ * Callbacks are done here, rather than in the crypto drivers, because -+ * callbacks typically are expensive and would slow interrupt handling. -+ */ -+static int -+crypto_ret_proc(void *arg) -+{ -+ struct cryptop *crpt; -+ struct cryptkop *krpt; -+ unsigned long r_flags; -+ -+ set_current_state(TASK_INTERRUPTIBLE); -+ -+ CRYPTO_RETQ_LOCK(); -+ for (;;) { -+ /* Harvest return q's for completed ops */ -+ crpt = NULL; -+ if (!list_empty(&crp_ret_q)) -+ crpt = list_entry(crp_ret_q.next, typeof(*crpt), crp_next); -+ if (crpt != NULL) -+ list_del(&crpt->crp_next); -+ -+ krpt = NULL; -+ if (!list_empty(&crp_ret_kq)) -+ krpt = list_entry(crp_ret_kq.next, typeof(*krpt), krp_next); -+ if (krpt != NULL) -+ list_del(&krpt->krp_next); -+ -+ if (crpt != NULL || krpt != NULL) { -+ CRYPTO_RETQ_UNLOCK(); -+ /* -+ * Run callbacks unlocked. -+ */ -+ if (crpt != NULL) -+ crpt->crp_callback(crpt); -+ if (krpt != NULL) -+ krpt->krp_callback(krpt); -+ CRYPTO_RETQ_LOCK(); -+ } else { -+ /* -+ * Nothing more to be processed. Sleep until we're -+ * woken because there are more returns to process. -+ */ -+ dprintk("%s - sleeping\n", __FUNCTION__); -+ CRYPTO_RETQ_UNLOCK(); -+ wait_event_interruptible(cryptoretproc_wait, -+ !list_empty(&crp_ret_q) || -+ !list_empty(&crp_ret_kq) || -+ kthread_should_stop()); -+ if (signal_pending (current)) { -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ spin_lock_irq(¤t->sigmask_lock); -+#endif -+ flush_signals(current); -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ spin_unlock_irq(¤t->sigmask_lock); -+#endif -+ } -+ CRYPTO_RETQ_LOCK(); -+ dprintk("%s - awake\n", __FUNCTION__); -+ if (kthread_should_stop()) { -+ dprintk("%s - EXITING!\n", __FUNCTION__); -+ break; -+ } -+ cryptostats.cs_rets++; -+ } -+ } -+ CRYPTO_RETQ_UNLOCK(); -+ return 0; -+} -+ -+ -+#if 0 /* should put this into /proc or something */ -+static void -+db_show_drivers(void) -+{ -+ int hid; -+ -+ db_printf("%12s %4s %4s %8s %2s %2s\n" -+ , "Device" -+ , "Ses" -+ , "Kops" -+ , "Flags" -+ , "QB" -+ , "KB" -+ ); -+ for (hid = 0; hid < crypto_drivers_num; hid++) { -+ const struct cryptocap *cap = &crypto_drivers[hid]; -+ if (cap->cc_dev == NULL) -+ continue; -+ db_printf("%-12s %4u %4u %08x %2u %2u\n" -+ , device_get_nameunit(cap->cc_dev) -+ , cap->cc_sessions -+ , cap->cc_koperations -+ , cap->cc_flags -+ , cap->cc_qblocked -+ , cap->cc_kqblocked -+ ); -+ } -+} -+ -+DB_SHOW_COMMAND(crypto, db_show_crypto) -+{ -+ struct cryptop *crp; -+ -+ db_show_drivers(); -+ db_printf("\n"); -+ -+ db_printf("%4s %8s %4s %4s %4s %4s %8s %8s\n", -+ "HID", "Caps", "Ilen", "Olen", "Etype", "Flags", -+ "Desc", "Callback"); -+ TAILQ_FOREACH(crp, &crp_q, crp_next) { -+ db_printf("%4u %08x %4u %4u %4u %04x %8p %8p\n" -+ , (int) CRYPTO_SESID2HID(crp->crp_sid) -+ , (int) CRYPTO_SESID2CAPS(crp->crp_sid) -+ , crp->crp_ilen, crp->crp_olen -+ , crp->crp_etype -+ , crp->crp_flags -+ , crp->crp_desc -+ , crp->crp_callback -+ ); -+ } -+ if (!TAILQ_EMPTY(&crp_ret_q)) { -+ db_printf("\n%4s %4s %4s %8s\n", -+ "HID", "Etype", "Flags", "Callback"); -+ TAILQ_FOREACH(crp, &crp_ret_q, crp_next) { -+ db_printf("%4u %4u %04x %8p\n" -+ , (int) CRYPTO_SESID2HID(crp->crp_sid) -+ , crp->crp_etype -+ , crp->crp_flags -+ , crp->crp_callback -+ ); -+ } -+ } -+} -+ -+DB_SHOW_COMMAND(kcrypto, db_show_kcrypto) -+{ -+ struct cryptkop *krp; -+ -+ db_show_drivers(); -+ db_printf("\n"); -+ -+ db_printf("%4s %5s %4s %4s %8s %4s %8s\n", -+ "Op", "Status", "#IP", "#OP", "CRID", "HID", "Callback"); -+ TAILQ_FOREACH(krp, &crp_kq, krp_next) { -+ db_printf("%4u %5u %4u %4u %08x %4u %8p\n" -+ , krp->krp_op -+ , krp->krp_status -+ , krp->krp_iparams, krp->krp_oparams -+ , krp->krp_crid, krp->krp_hid -+ , krp->krp_callback -+ ); -+ } -+ if (!TAILQ_EMPTY(&crp_ret_q)) { -+ db_printf("%4s %5s %8s %4s %8s\n", -+ "Op", "Status", "CRID", "HID", "Callback"); -+ TAILQ_FOREACH(krp, &crp_ret_kq, krp_next) { -+ db_printf("%4u %5u %08x %4u %8p\n" -+ , krp->krp_op -+ , krp->krp_status -+ , krp->krp_crid, krp->krp_hid -+ , krp->krp_callback -+ ); -+ } -+ } -+} -+#endif -+ -+ -+static int -+crypto_init(void) -+{ -+ int error; -+ unsigned long cpu; -+ -+ dprintk("%s(%p)\n", __FUNCTION__, (void *) crypto_init); -+ -+ if (crypto_initted) -+ return 0; -+ crypto_initted = 1; -+ -+ spin_lock_init(&crypto_drivers_lock); -+ spin_lock_init(&crypto_q_lock); -+ spin_lock_init(&crypto_ret_q_lock); -+ -+ cryptop_zone = kmem_cache_create("cryptop", sizeof(struct cryptop), -+ 0, SLAB_HWCACHE_ALIGN, NULL -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) -+ , NULL -+#endif -+ ); -+ -+ cryptodesc_zone = kmem_cache_create("cryptodesc", sizeof(struct cryptodesc), -+ 0, SLAB_HWCACHE_ALIGN, NULL -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) -+ , NULL -+#endif -+ ); -+ -+ if (cryptodesc_zone == NULL || cryptop_zone == NULL) { -+ printk("crypto: crypto_init cannot setup crypto zones\n"); -+ error = ENOMEM; -+ goto bad; -+ } -+ -+ crypto_drivers_num = CRYPTO_DRIVERS_INITIAL; -+ crypto_drivers = kmalloc(crypto_drivers_num * sizeof(struct cryptocap), -+ GFP_KERNEL); -+ if (crypto_drivers == NULL) { -+ printk("crypto: crypto_init cannot setup crypto drivers\n"); -+ error = ENOMEM; -+ goto bad; -+ } -+ -+ memset(crypto_drivers, 0, crypto_drivers_num * sizeof(struct cryptocap)); -+ -+ ocf_for_each_cpu(cpu) { -+ cryptoproc[cpu] = kthread_create(crypto_proc, (void *) cpu, -+ "ocf_%d", (int) cpu); -+ if (IS_ERR(cryptoproc[cpu])) { -+ error = PTR_ERR(cryptoproc[cpu]); -+ printk("crypto: crypto_init cannot start crypto thread; error %d", -+ error); -+ goto bad; -+ } -+ kthread_bind(cryptoproc[cpu], cpu); -+ wake_up_process(cryptoproc[cpu]); -+ -+ cryptoretproc[cpu] = kthread_create(crypto_ret_proc, (void *) cpu, -+ "ocf_ret_%d", (int) cpu); -+ if (IS_ERR(cryptoretproc[cpu])) { -+ error = PTR_ERR(cryptoretproc[cpu]); -+ printk("crypto: crypto_init cannot start cryptoret thread; error %d", -+ error); -+ goto bad; -+ } -+ kthread_bind(cryptoretproc[cpu], cpu); -+ wake_up_process(cryptoretproc[cpu]); -+ } -+ -+ return 0; -+bad: -+ crypto_exit(); -+ return error; -+} -+ -+ -+static void -+crypto_exit(void) -+{ -+ int cpu; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ /* -+ * Terminate any crypto threads. -+ */ -+ ocf_for_each_cpu(cpu) { -+ kthread_stop(cryptoproc[cpu]); -+ kthread_stop(cryptoretproc[cpu]); -+ } -+ -+ /* -+ * Reclaim dynamically allocated resources. -+ */ -+ if (crypto_drivers != NULL) -+ kfree(crypto_drivers); -+ -+ if (cryptodesc_zone != NULL) -+ kmem_cache_destroy(cryptodesc_zone); -+ if (cryptop_zone != NULL) -+ kmem_cache_destroy(cryptop_zone); -+} -+ -+ -+EXPORT_SYMBOL(crypto_newsession); -+EXPORT_SYMBOL(crypto_freesession); -+EXPORT_SYMBOL(crypto_get_driverid); -+EXPORT_SYMBOL(crypto_kregister); -+EXPORT_SYMBOL(crypto_register); -+EXPORT_SYMBOL(crypto_unregister); -+EXPORT_SYMBOL(crypto_unregister_all); -+EXPORT_SYMBOL(crypto_unblock); -+EXPORT_SYMBOL(crypto_dispatch); -+EXPORT_SYMBOL(crypto_kdispatch); -+EXPORT_SYMBOL(crypto_freereq); -+EXPORT_SYMBOL(crypto_getreq); -+EXPORT_SYMBOL(crypto_done); -+EXPORT_SYMBOL(crypto_kdone); -+EXPORT_SYMBOL(crypto_getfeat); -+EXPORT_SYMBOL(crypto_userasymcrypto); -+EXPORT_SYMBOL(crypto_getcaps); -+EXPORT_SYMBOL(crypto_find_driver); -+EXPORT_SYMBOL(crypto_find_device_byhid); -+ -+module_init(crypto_init); -+module_exit(crypto_exit); -+ -+MODULE_LICENSE("BSD"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("OCF (OpenBSD Cryptographic Framework)"); -diff -Nur linux-3.0.4.orig/crypto/ocf/cryptocteon/Makefile linux-3.0.4/crypto/ocf/cryptocteon/Makefile ---- linux-3.0.4.orig/crypto/ocf/cryptocteon/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/cryptocteon/Makefile 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,17 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+obj-$(CONFIG_OCF_CRYPTOCTEON) += cryptocteon.o -+ -+obj ?= . -+EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ -+ -+ifdef CONFIG_OCF_CRYPTOCTEON -+# you need the cavium crypto component installed -+EXTRA_CFLAGS += -I$(ROOTDIR)/prop/include -+endif -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/cryptocteon/README.txt linux-3.0.4/crypto/ocf/cryptocteon/README.txt ---- linux-3.0.4.orig/crypto/ocf/cryptocteon/README.txt 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/cryptocteon/README.txt 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,11 @@ -+ -+You will need the CRYPTO package installed to build this driver, and -+potentially the ADK. -+ -+cavium_crypto sourced from: -+ -+ adk/components/source/cavium_ipsec_kame/cavium_ipsec.c -+ -+and significantly modified to suit use with OCF. All original -+copyright/ownership headers retained. -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/cryptocteon/cavium_crypto.c linux-3.0.4/crypto/ocf/cryptocteon/cavium_crypto.c ---- linux-3.0.4.orig/crypto/ocf/cryptocteon/cavium_crypto.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/cryptocteon/cavium_crypto.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,2283 @@ -+/* -+ * Copyright (c) 2009 David McCullough -+ * -+ * Copyright (c) 2003-2007 Cavium Networks (support@cavium.com). All rights -+ * reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * 1. Redistributions of source code must retain the above copyright notice, -+ * this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright notice, -+ * this list of conditions and the following disclaimer in the documentation -+ * and/or other materials provided with the distribution. -+ * 3. All advertising materials mentioning features or use of this software -+ * must display the following acknowledgement: -+ * This product includes software developed by Cavium Networks -+ * 4. Cavium Networks' name may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * This Software, including technical data, may be subject to U.S. export -+ * control laws, including the U.S. Export Administration Act and its -+ * associated regulations, and may be subject to export or import regulations -+ * in other countries. You warrant that You will comply strictly in all -+ * respects with all such regulations and acknowledge that you have the -+ * responsibility to obtain licenses to export, re-export or import the -+ * Software. -+ * -+ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" AND -+ * WITH ALL FAULTS AND CAVIUM MAKES NO PROMISES, REPRESENTATIONS OR WARRANTIES, -+ * EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO THE -+ * SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR -+ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM -+ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, -+ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF -+ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR -+ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR -+ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. -+*/ -+/****************************************************************************/ -+ -+#include -+#include -+#include "octeon-asm.h" -+ -+/****************************************************************************/ -+ -+extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *); -+extern void octeon_crypto_disable(struct octeon_cop2_state *, unsigned long); -+ -+#define SG_INIT(s, p, i, l) \ -+ { \ -+ (i) = 0; \ -+ (l) = (s)[0].length; \ -+ (p) = (typeof(p)) sg_virt((s)); \ -+ CVMX_PREFETCH0((p)); \ -+ } -+ -+#define SG_CONSUME(s, p, i, l) \ -+ { \ -+ (p)++; \ -+ (l) -= sizeof(*(p)); \ -+ if ((l) < 0) { \ -+ dprintk("%s, %d: l = %d\n", __FILE__, __LINE__, l); \ -+ } else if ((l) == 0) { \ -+ (i)++; \ -+ (l) = (s)[0].length; \ -+ (p) = (typeof(p)) sg_virt(s); \ -+ CVMX_PREFETCH0((p)); \ -+ } \ -+ } -+ -+#define ESP_HEADER_LENGTH 8 -+#define DES_CBC_IV_LENGTH 8 -+#define AES_CBC_IV_LENGTH 16 -+#define ESP_HMAC_LEN 12 -+ -+#define ESP_HEADER_LENGTH 8 -+#define DES_CBC_IV_LENGTH 8 -+ -+/****************************************************************************/ -+ -+#define CVM_LOAD_SHA_UNIT(dat, next) { \ -+ if (next == 0) { \ -+ next = 1; \ -+ CVMX_MT_HSH_DAT (dat, 0); \ -+ } else if (next == 1) { \ -+ next = 2; \ -+ CVMX_MT_HSH_DAT (dat, 1); \ -+ } else if (next == 2) { \ -+ next = 3; \ -+ CVMX_MT_HSH_DAT (dat, 2); \ -+ } else if (next == 3) { \ -+ next = 4; \ -+ CVMX_MT_HSH_DAT (dat, 3); \ -+ } else if (next == 4) { \ -+ next = 5; \ -+ CVMX_MT_HSH_DAT (dat, 4); \ -+ } else if (next == 5) { \ -+ next = 6; \ -+ CVMX_MT_HSH_DAT (dat, 5); \ -+ } else if (next == 6) { \ -+ next = 7; \ -+ CVMX_MT_HSH_DAT (dat, 6); \ -+ } else { \ -+ CVMX_MT_HSH_STARTSHA (dat); \ -+ next = 0; \ -+ } \ -+} -+ -+#define CVM_LOAD2_SHA_UNIT(dat1, dat2, next) { \ -+ if (next == 0) { \ -+ CVMX_MT_HSH_DAT (dat1, 0); \ -+ CVMX_MT_HSH_DAT (dat2, 1); \ -+ next = 2; \ -+ } else if (next == 1) { \ -+ CVMX_MT_HSH_DAT (dat1, 1); \ -+ CVMX_MT_HSH_DAT (dat2, 2); \ -+ next = 3; \ -+ } else if (next == 2) { \ -+ CVMX_MT_HSH_DAT (dat1, 2); \ -+ CVMX_MT_HSH_DAT (dat2, 3); \ -+ next = 4; \ -+ } else if (next == 3) { \ -+ CVMX_MT_HSH_DAT (dat1, 3); \ -+ CVMX_MT_HSH_DAT (dat2, 4); \ -+ next = 5; \ -+ } else if (next == 4) { \ -+ CVMX_MT_HSH_DAT (dat1, 4); \ -+ CVMX_MT_HSH_DAT (dat2, 5); \ -+ next = 6; \ -+ } else if (next == 5) { \ -+ CVMX_MT_HSH_DAT (dat1, 5); \ -+ CVMX_MT_HSH_DAT (dat2, 6); \ -+ next = 7; \ -+ } else if (next == 6) { \ -+ CVMX_MT_HSH_DAT (dat1, 6); \ -+ CVMX_MT_HSH_STARTSHA (dat2); \ -+ next = 0; \ -+ } else { \ -+ CVMX_MT_HSH_STARTSHA (dat1); \ -+ CVMX_MT_HSH_DAT (dat2, 0); \ -+ next = 1; \ -+ } \ -+} -+ -+/****************************************************************************/ -+ -+#define CVM_LOAD_MD5_UNIT(dat, next) { \ -+ if (next == 0) { \ -+ next = 1; \ -+ CVMX_MT_HSH_DAT (dat, 0); \ -+ } else if (next == 1) { \ -+ next = 2; \ -+ CVMX_MT_HSH_DAT (dat, 1); \ -+ } else if (next == 2) { \ -+ next = 3; \ -+ CVMX_MT_HSH_DAT (dat, 2); \ -+ } else if (next == 3) { \ -+ next = 4; \ -+ CVMX_MT_HSH_DAT (dat, 3); \ -+ } else if (next == 4) { \ -+ next = 5; \ -+ CVMX_MT_HSH_DAT (dat, 4); \ -+ } else if (next == 5) { \ -+ next = 6; \ -+ CVMX_MT_HSH_DAT (dat, 5); \ -+ } else if (next == 6) { \ -+ next = 7; \ -+ CVMX_MT_HSH_DAT (dat, 6); \ -+ } else { \ -+ CVMX_MT_HSH_STARTMD5 (dat); \ -+ next = 0; \ -+ } \ -+} -+ -+#define CVM_LOAD2_MD5_UNIT(dat1, dat2, next) { \ -+ if (next == 0) { \ -+ CVMX_MT_HSH_DAT (dat1, 0); \ -+ CVMX_MT_HSH_DAT (dat2, 1); \ -+ next = 2; \ -+ } else if (next == 1) { \ -+ CVMX_MT_HSH_DAT (dat1, 1); \ -+ CVMX_MT_HSH_DAT (dat2, 2); \ -+ next = 3; \ -+ } else if (next == 2) { \ -+ CVMX_MT_HSH_DAT (dat1, 2); \ -+ CVMX_MT_HSH_DAT (dat2, 3); \ -+ next = 4; \ -+ } else if (next == 3) { \ -+ CVMX_MT_HSH_DAT (dat1, 3); \ -+ CVMX_MT_HSH_DAT (dat2, 4); \ -+ next = 5; \ -+ } else if (next == 4) { \ -+ CVMX_MT_HSH_DAT (dat1, 4); \ -+ CVMX_MT_HSH_DAT (dat2, 5); \ -+ next = 6; \ -+ } else if (next == 5) { \ -+ CVMX_MT_HSH_DAT (dat1, 5); \ -+ CVMX_MT_HSH_DAT (dat2, 6); \ -+ next = 7; \ -+ } else if (next == 6) { \ -+ CVMX_MT_HSH_DAT (dat1, 6); \ -+ CVMX_MT_HSH_STARTMD5 (dat2); \ -+ next = 0; \ -+ } else { \ -+ CVMX_MT_HSH_STARTMD5 (dat1); \ -+ CVMX_MT_HSH_DAT (dat2, 0); \ -+ next = 1; \ -+ } \ -+} -+ -+/****************************************************************************/ -+ -+static inline uint64_t -+swap64(uint64_t a) -+{ -+ return ((a >> 56) | -+ (((a >> 48) & 0xfful) << 8) | -+ (((a >> 40) & 0xfful) << 16) | -+ (((a >> 32) & 0xfful) << 24) | -+ (((a >> 24) & 0xfful) << 32) | -+ (((a >> 16) & 0xfful) << 40) | -+ (((a >> 8) & 0xfful) << 48) | (((a >> 0) & 0xfful) << 56)); -+} -+ -+/****************************************************************************/ -+ -+void -+octo_calc_hash(__u8 auth, unsigned char *key, uint64_t *inner, uint64_t *outer) -+{ -+ uint8_t hash_key[64]; -+ uint64_t *key1; -+ register uint64_t xor1 = 0x3636363636363636ULL; -+ register uint64_t xor2 = 0x5c5c5c5c5c5c5c5cULL; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ memset(hash_key, 0, sizeof(hash_key)); -+ memcpy(hash_key, (uint8_t *) key, (auth ? 20 : 16)); -+ key1 = (uint64_t *) hash_key; -+ flags = octeon_crypto_enable(&state); -+ if (auth) { -+ CVMX_MT_HSH_IV(0x67452301EFCDAB89ULL, 0); -+ CVMX_MT_HSH_IV(0x98BADCFE10325476ULL, 1); -+ CVMX_MT_HSH_IV(0xC3D2E1F000000000ULL, 2); -+ } else { -+ CVMX_MT_HSH_IV(0x0123456789ABCDEFULL, 0); -+ CVMX_MT_HSH_IV(0xFEDCBA9876543210ULL, 1); -+ } -+ -+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 0); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 1); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 2); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 3); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 4); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 5); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor1), 6); -+ key1++; -+ if (auth) -+ CVMX_MT_HSH_STARTSHA((*key1 ^ xor1)); -+ else -+ CVMX_MT_HSH_STARTMD5((*key1 ^ xor1)); -+ -+ CVMX_MF_HSH_IV(inner[0], 0); -+ CVMX_MF_HSH_IV(inner[1], 1); -+ if (auth) { -+ inner[2] = 0; -+ CVMX_MF_HSH_IV(((uint64_t *) inner)[2], 2); -+ } -+ -+ memset(hash_key, 0, sizeof(hash_key)); -+ memcpy(hash_key, (uint8_t *) key, (auth ? 20 : 16)); -+ key1 = (uint64_t *) hash_key; -+ if (auth) { -+ CVMX_MT_HSH_IV(0x67452301EFCDAB89ULL, 0); -+ CVMX_MT_HSH_IV(0x98BADCFE10325476ULL, 1); -+ CVMX_MT_HSH_IV(0xC3D2E1F000000000ULL, 2); -+ } else { -+ CVMX_MT_HSH_IV(0x0123456789ABCDEFULL, 0); -+ CVMX_MT_HSH_IV(0xFEDCBA9876543210ULL, 1); -+ } -+ -+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 0); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 1); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 2); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 3); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 4); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 5); -+ key1++; -+ CVMX_MT_HSH_DAT((*key1 ^ xor2), 6); -+ key1++; -+ if (auth) -+ CVMX_MT_HSH_STARTSHA((*key1 ^ xor2)); -+ else -+ CVMX_MT_HSH_STARTMD5((*key1 ^ xor2)); -+ -+ CVMX_MF_HSH_IV(outer[0], 0); -+ CVMX_MF_HSH_IV(outer[1], 1); -+ if (auth) { -+ outer[2] = 0; -+ CVMX_MF_HSH_IV(outer[2], 2); -+ } -+ octeon_crypto_disable(&state, flags); -+ return; -+} -+ -+/****************************************************************************/ -+/* DES functions */ -+ -+int -+octo_des_cbc_encrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ uint64_t *data; -+ int data_i, data_l; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x7) || (crypt_off + crypt_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load 3DES Key */ -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ if (od->octo_encklen == 24) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ } else if (od->octo_encklen == 8) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ -+ CVMX_MT_3DES_IV(* (uint64_t *) ivp); -+ -+ while (crypt_off > 0) { -+ SG_CONSUME(sg, data, data_i, data_l); -+ crypt_off -= 8; -+ } -+ -+ while (crypt_len > 0) { -+ CVMX_MT_3DES_ENC_CBC(*data); -+ CVMX_MF_3DES_RESULT(*data); -+ SG_CONSUME(sg, data, data_i, data_l); -+ crypt_len -= 8; -+ } -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+ -+int -+octo_des_cbc_decrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ uint64_t *data; -+ int data_i, data_l; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x7) || (crypt_off + crypt_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load 3DES Key */ -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ if (od->octo_encklen == 24) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ } else if (od->octo_encklen == 8) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ -+ CVMX_MT_3DES_IV(* (uint64_t *) ivp); -+ -+ while (crypt_off > 0) { -+ SG_CONSUME(sg, data, data_i, data_l); -+ crypt_off -= 8; -+ } -+ -+ while (crypt_len > 0) { -+ CVMX_MT_3DES_DEC_CBC(*data); -+ CVMX_MF_3DES_RESULT(*data); -+ SG_CONSUME(sg, data, data_i, data_l); -+ crypt_len -= 8; -+ } -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+/****************************************************************************/ -+/* AES functions */ -+ -+int -+octo_aes_cbc_encrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ uint64_t *data, *pdata; -+ int data_i, data_l; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x7) || (crypt_off + crypt_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load AES Key */ -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ -+ if (od->octo_encklen == 16) { -+ CVMX_MT_AES_KEY(0x0, 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 24) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 32) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); -+ -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); -+ -+ while (crypt_off > 0) { -+ SG_CONSUME(sg, data, data_i, data_l); -+ crypt_off -= 8; -+ } -+ -+ while (crypt_len > 0) { -+ pdata = data; -+ CVMX_MT_AES_ENC_CBC0(*data); -+ SG_CONSUME(sg, data, data_i, data_l); -+ CVMX_MT_AES_ENC_CBC1(*data); -+ CVMX_MF_AES_RESULT(*pdata, 0); -+ CVMX_MF_AES_RESULT(*data, 1); -+ SG_CONSUME(sg, data, data_i, data_l); -+ crypt_len -= 16; -+ } -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+ -+int -+octo_aes_cbc_decrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ uint64_t *data, *pdata; -+ int data_i, data_l; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x7) || (crypt_off + crypt_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load AES Key */ -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ -+ if (od->octo_encklen == 16) { -+ CVMX_MT_AES_KEY(0x0, 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 24) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 32) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); -+ -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); -+ -+ while (crypt_off > 0) { -+ SG_CONSUME(sg, data, data_i, data_l); -+ crypt_off -= 8; -+ } -+ -+ while (crypt_len > 0) { -+ pdata = data; -+ CVMX_MT_AES_DEC_CBC0(*data); -+ SG_CONSUME(sg, data, data_i, data_l); -+ CVMX_MT_AES_DEC_CBC1(*data); -+ CVMX_MF_AES_RESULT(*pdata, 0); -+ CVMX_MF_AES_RESULT(*data, 1); -+ SG_CONSUME(sg, data, data_i, data_l); -+ crypt_len -= 16; -+ } -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+/****************************************************************************/ -+/* MD5 */ -+ -+int -+octo_null_md5_encrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ uint64_t *data; -+ uint64_t tmp1, tmp2; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || -+ (auth_off & 0x7) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data, data_i, data_l); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* Load MD5 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ -+ while (auth_off > 0) { -+ SG_CONSUME(sg, data, data_i, data_l); -+ auth_off -= 8; -+ } -+ -+ while (auth_len > 0) { -+ CVM_LOAD_MD5_UNIT(*data, next); -+ auth_len -= 8; -+ SG_CONSUME(sg, data, data_i, data_l); -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_MD5_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVMX_ES64(tmp1, ((alen + 64) << 3)); -+ CVM_LOAD_MD5_UNIT(tmp1, next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_ES64(tmp1, ((64 + 16) << 3)); -+ CVMX_MT_HSH_STARTMD5(tmp1); -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data, data_i, data_l); -+ icv_off -= 8; -+ } -+ CVMX_MF_HSH_IV(*data, 0); -+ SG_CONSUME(sg, data, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *(uint32_t *)data = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+/****************************************************************************/ -+/* SHA1 */ -+ -+int -+octo_null_sha1_encrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ uint64_t *data; -+ uint64_t tmp1, tmp2, tmp3; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || -+ (auth_off & 0x7) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data, data_i, data_l); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* Load SHA1 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); -+ -+ while (auth_off > 0) { -+ SG_CONSUME(sg, data, data_i, data_l); -+ auth_off -= 8; -+ } -+ -+ while (auth_len > 0) { -+ CVM_LOAD_SHA_UNIT(*data, next); -+ auth_len -= 8; -+ SG_CONSUME(sg, data, data_i, data_l); -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_MD5_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ tmp3 = 0; -+ CVMX_MF_HSH_IV(tmp3, 2); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ tmp3 |= 0x0000000080000000; -+ CVMX_MT_HSH_DAT(tmp3, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data, data_i, data_l); -+ icv_off -= 8; -+ } -+ CVMX_MF_HSH_IV(*data, 0); -+ SG_CONSUME(sg, data, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *(uint32_t *)data = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+/****************************************************************************/ -+/* DES MD5 */ -+ -+int -+octo_des_cbc_md5_encrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ union { -+ uint32_t data32[2]; -+ uint64_t data64[1]; -+ } mydata; -+ uint64_t *data = &mydata.data64[0]; -+ uint32_t *data32; -+ uint64_t tmp1, tmp2; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || -+ (crypt_len & 0x7) || -+ (auth_len & 0x7) || -+ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data32, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load 3DES Key */ -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ if (od->octo_encklen == 24) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ } else if (od->octo_encklen == 8) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ -+ CVMX_MT_3DES_IV(* (uint64_t *) ivp); -+ -+ /* Load MD5 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ -+ while (crypt_off > 0 && auth_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ crypt_off -= 4; -+ auth_off -= 4; -+ } -+ -+ while (crypt_len > 0 || auth_len > 0) { -+ uint32_t *first = data32; -+ mydata.data32[0] = *first; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata.data32[1] = *data32; -+ if (crypt_off <= 0) { -+ if (crypt_len > 0) { -+ CVMX_MT_3DES_ENC_CBC(*data); -+ CVMX_MF_3DES_RESULT(*data); -+ crypt_len -= 8; -+ } -+ } else -+ crypt_off -= 8; -+ if (auth_off <= 0) { -+ if (auth_len > 0) { -+ CVM_LOAD_MD5_UNIT(*data, next); -+ auth_len -= 8; -+ } -+ } else -+ auth_off -= 8; -+ *first = mydata.data32[0]; -+ *data32 = mydata.data32[1]; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_MD5_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVMX_ES64(tmp1, ((alen + 64) << 3)); -+ CVM_LOAD_MD5_UNIT(tmp1, next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_ES64(tmp1, ((64 + 16) << 3)); -+ CVMX_MT_HSH_STARTMD5(tmp1); -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data32, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ icv_off -= 4; -+ } -+ CVMX_MF_HSH_IV(tmp1, 0); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ SG_CONSUME(sg, data32, data_i, data_l); -+ *data32 = (uint32_t) tmp1; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+int -+octo_des_cbc_md5_decrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ union { -+ uint32_t data32[2]; -+ uint64_t data64[1]; -+ } mydata; -+ uint64_t *data = &mydata.data64[0]; -+ uint32_t *data32; -+ uint64_t tmp1, tmp2; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || -+ (crypt_len & 0x7) || -+ (auth_len & 0x7) || -+ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data32, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load 3DES Key */ -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ if (od->octo_encklen == 24) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ } else if (od->octo_encklen == 8) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ -+ CVMX_MT_3DES_IV(* (uint64_t *) ivp); -+ -+ /* Load MD5 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ -+ while (crypt_off > 0 && auth_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ crypt_off -= 4; -+ auth_off -= 4; -+ } -+ -+ while (crypt_len > 0 || auth_len > 0) { -+ uint32_t *first = data32; -+ mydata.data32[0] = *first; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata.data32[1] = *data32; -+ if (auth_off <= 0) { -+ if (auth_len > 0) { -+ CVM_LOAD_MD5_UNIT(*data, next); -+ auth_len -= 8; -+ } -+ } else -+ auth_off -= 8; -+ if (crypt_off <= 0) { -+ if (crypt_len > 0) { -+ CVMX_MT_3DES_DEC_CBC(*data); -+ CVMX_MF_3DES_RESULT(*data); -+ crypt_len -= 8; -+ } -+ } else -+ crypt_off -= 8; -+ *first = mydata.data32[0]; -+ *data32 = mydata.data32[1]; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_MD5_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVMX_ES64(tmp1, ((alen + 64) << 3)); -+ CVM_LOAD_MD5_UNIT(tmp1, next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_ES64(tmp1, ((64 + 16) << 3)); -+ CVMX_MT_HSH_STARTMD5(tmp1); -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data32, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ icv_off -= 4; -+ } -+ CVMX_MF_HSH_IV(tmp1, 0); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ SG_CONSUME(sg, data32, data_i, data_l); -+ *data32 = (uint32_t) tmp1; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+/****************************************************************************/ -+/* DES SHA */ -+ -+int -+octo_des_cbc_sha1_encrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ union { -+ uint32_t data32[2]; -+ uint64_t data64[1]; -+ } mydata; -+ uint64_t *data = &mydata.data64[0]; -+ uint32_t *data32; -+ uint64_t tmp1, tmp2, tmp3; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || -+ (crypt_len & 0x7) || -+ (auth_len & 0x7) || -+ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data32, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load 3DES Key */ -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ if (od->octo_encklen == 24) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ } else if (od->octo_encklen == 8) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ -+ CVMX_MT_3DES_IV(* (uint64_t *) ivp); -+ -+ /* Load SHA1 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); -+ -+ while (crypt_off > 0 && auth_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ crypt_off -= 4; -+ auth_off -= 4; -+ } -+ -+ while (crypt_len > 0 || auth_len > 0) { -+ uint32_t *first = data32; -+ mydata.data32[0] = *first; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata.data32[1] = *data32; -+ if (crypt_off <= 0) { -+ if (crypt_len > 0) { -+ CVMX_MT_3DES_ENC_CBC(*data); -+ CVMX_MF_3DES_RESULT(*data); -+ crypt_len -= 8; -+ } -+ } else -+ crypt_off -= 8; -+ if (auth_off <= 0) { -+ if (auth_len > 0) { -+ CVM_LOAD_SHA_UNIT(*data, next); -+ auth_len -= 8; -+ } -+ } else -+ auth_off -= 8; -+ *first = mydata.data32[0]; -+ *data32 = mydata.data32[1]; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_SHA_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ tmp3 = 0; -+ CVMX_MF_HSH_IV(tmp3, 2); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ tmp3 |= 0x0000000080000000; -+ CVMX_MT_HSH_DAT(tmp3, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data32, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ icv_off -= 4; -+ } -+ CVMX_MF_HSH_IV(tmp1, 0); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ SG_CONSUME(sg, data32, data_i, data_l); -+ *data32 = (uint32_t) tmp1; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+int -+octo_des_cbc_sha1_decrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ union { -+ uint32_t data32[2]; -+ uint64_t data64[1]; -+ } mydata; -+ uint64_t *data = &mydata.data64[0]; -+ uint32_t *data32; -+ uint64_t tmp1, tmp2, tmp3; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || -+ (crypt_len & 0x7) || -+ (auth_len & 0x7) || -+ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data32, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load 3DES Key */ -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ if (od->octo_encklen == 24) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ } else if (od->octo_encklen == 8) { -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); -+ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ -+ CVMX_MT_3DES_IV(* (uint64_t *) ivp); -+ -+ /* Load SHA1 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); -+ -+ while (crypt_off > 0 && auth_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ crypt_off -= 4; -+ auth_off -= 4; -+ } -+ -+ while (crypt_len > 0 || auth_len > 0) { -+ uint32_t *first = data32; -+ mydata.data32[0] = *first; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata.data32[1] = *data32; -+ if (auth_off <= 0) { -+ if (auth_len > 0) { -+ CVM_LOAD_SHA_UNIT(*data, next); -+ auth_len -= 8; -+ } -+ } else -+ auth_off -= 8; -+ if (crypt_off <= 0) { -+ if (crypt_len > 0) { -+ CVMX_MT_3DES_DEC_CBC(*data); -+ CVMX_MF_3DES_RESULT(*data); -+ crypt_len -= 8; -+ } -+ } else -+ crypt_off -= 8; -+ *first = mydata.data32[0]; -+ *data32 = mydata.data32[1]; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_SHA_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ tmp3 = 0; -+ CVMX_MF_HSH_IV(tmp3, 2); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ tmp3 |= 0x0000000080000000; -+ CVMX_MT_HSH_DAT(tmp3, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); -+ /* save the HMAC */ -+ SG_INIT(sg, data32, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ icv_off -= 4; -+ } -+ CVMX_MF_HSH_IV(tmp1, 0); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ SG_CONSUME(sg, data32, data_i, data_l); -+ *data32 = (uint32_t) tmp1; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+/****************************************************************************/ -+/* AES MD5 */ -+ -+int -+octo_aes_cbc_md5_encrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ union { -+ uint32_t data32[2]; -+ uint64_t data64[1]; -+ } mydata[2]; -+ uint64_t *pdata = &mydata[0].data64[0]; -+ uint64_t *data = &mydata[1].data64[0]; -+ uint32_t *data32; -+ uint64_t tmp1, tmp2; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || -+ (crypt_len & 0x7) || -+ (auth_len & 0x7) || -+ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data32, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load AES Key */ -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ -+ if (od->octo_encklen == 16) { -+ CVMX_MT_AES_KEY(0x0, 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 24) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 32) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); -+ -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); -+ -+ /* Load MD5 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ -+ while (crypt_off > 0 && auth_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ crypt_off -= 4; -+ auth_off -= 4; -+ } -+ -+ /* align auth and crypt */ -+ while (crypt_off > 0 && auth_len > 0) { -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVM_LOAD_MD5_UNIT(*pdata, next); -+ crypt_off -= 8; -+ auth_len -= 8; -+ } -+ -+ while (crypt_len > 0) { -+ uint32_t *pdata32[3]; -+ -+ pdata32[0] = data32; -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ -+ pdata32[1] = data32; -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ -+ pdata32[2] = data32; -+ mydata[1].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ -+ mydata[1].data32[1] = *data32; -+ -+ CVMX_MT_AES_ENC_CBC0(*pdata); -+ CVMX_MT_AES_ENC_CBC1(*data); -+ CVMX_MF_AES_RESULT(*pdata, 0); -+ CVMX_MF_AES_RESULT(*data, 1); -+ crypt_len -= 16; -+ -+ if (auth_len > 0) { -+ CVM_LOAD_MD5_UNIT(*pdata, next); -+ auth_len -= 8; -+ } -+ if (auth_len > 0) { -+ CVM_LOAD_MD5_UNIT(*data, next); -+ auth_len -= 8; -+ } -+ -+ *pdata32[0] = mydata[0].data32[0]; -+ *pdata32[1] = mydata[0].data32[1]; -+ *pdata32[2] = mydata[1].data32[0]; -+ *data32 = mydata[1].data32[1]; -+ -+ SG_CONSUME(sg, data32, data_i, data_l); -+ } -+ -+ /* finish any left over hashing */ -+ while (auth_len > 0) { -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVM_LOAD_MD5_UNIT(*pdata, next); -+ auth_len -= 8; -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_MD5_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVMX_ES64(tmp1, ((alen + 64) << 3)); -+ CVM_LOAD_MD5_UNIT(tmp1, next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_ES64(tmp1, ((64 + 16) << 3)); -+ CVMX_MT_HSH_STARTMD5(tmp1); -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data32, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ icv_off -= 4; -+ } -+ CVMX_MF_HSH_IV(tmp1, 0); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ SG_CONSUME(sg, data32, data_i, data_l); -+ *data32 = (uint32_t) tmp1; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+int -+octo_aes_cbc_md5_decrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ union { -+ uint32_t data32[2]; -+ uint64_t data64[1]; -+ } mydata[2]; -+ uint64_t *pdata = &mydata[0].data64[0]; -+ uint64_t *data = &mydata[1].data64[0]; -+ uint32_t *data32; -+ uint64_t tmp1, tmp2; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || -+ (crypt_len & 0x7) || -+ (auth_len & 0x7) || -+ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data32, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load AES Key */ -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ -+ if (od->octo_encklen == 16) { -+ CVMX_MT_AES_KEY(0x0, 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 24) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 32) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); -+ -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); -+ -+ /* Load MD5 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ -+ while (crypt_off > 0 && auth_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ crypt_off -= 4; -+ auth_off -= 4; -+ } -+ -+ /* align auth and crypt */ -+ while (crypt_off > 0 && auth_len > 0) { -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVM_LOAD_MD5_UNIT(*pdata, next); -+ crypt_off -= 8; -+ auth_len -= 8; -+ } -+ -+ while (crypt_len > 0) { -+ uint32_t *pdata32[3]; -+ -+ pdata32[0] = data32; -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ pdata32[1] = data32; -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ pdata32[2] = data32; -+ mydata[1].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[1].data32[1] = *data32; -+ -+ if (auth_len > 0) { -+ CVM_LOAD_MD5_UNIT(*pdata, next); -+ auth_len -= 8; -+ } -+ -+ if (auth_len > 0) { -+ CVM_LOAD_MD5_UNIT(*data, next); -+ auth_len -= 8; -+ } -+ -+ CVMX_MT_AES_DEC_CBC0(*pdata); -+ CVMX_MT_AES_DEC_CBC1(*data); -+ CVMX_MF_AES_RESULT(*pdata, 0); -+ CVMX_MF_AES_RESULT(*data, 1); -+ crypt_len -= 16; -+ -+ *pdata32[0] = mydata[0].data32[0]; -+ *pdata32[1] = mydata[0].data32[1]; -+ *pdata32[2] = mydata[1].data32[0]; -+ *data32 = mydata[1].data32[1]; -+ -+ SG_CONSUME(sg, data32, data_i, data_l); -+ } -+ -+ /* finish left over hash if any */ -+ while (auth_len > 0) { -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVM_LOAD_MD5_UNIT(*pdata, next); -+ auth_len -= 8; -+ } -+ -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_MD5_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVMX_ES64(tmp1, ((alen + 64) << 3)); -+ CVM_LOAD_MD5_UNIT(tmp1, next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_ES64(tmp1, ((64 + 16) << 3)); -+ CVMX_MT_HSH_STARTMD5(tmp1); -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data32, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ icv_off -= 4; -+ } -+ CVMX_MF_HSH_IV(tmp1, 0); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ SG_CONSUME(sg, data32, data_i, data_l); -+ *data32 = (uint32_t) tmp1; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+/****************************************************************************/ -+/* AES SHA1 */ -+ -+int -+octo_aes_cbc_sha1_encrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ union { -+ uint32_t data32[2]; -+ uint64_t data64[1]; -+ } mydata[2]; -+ uint64_t *pdata = &mydata[0].data64[0]; -+ uint64_t *data = &mydata[1].data64[0]; -+ uint32_t *data32; -+ uint64_t tmp1, tmp2, tmp3; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s(a_off=%d a_len=%d c_off=%d c_len=%d icv_off=%d)\n", -+ __FUNCTION__, auth_off, auth_len, crypt_off, crypt_len, icv_off); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || -+ (crypt_len & 0x7) || -+ (auth_len & 0x7) || -+ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data32, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load AES Key */ -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ -+ if (od->octo_encklen == 16) { -+ CVMX_MT_AES_KEY(0x0, 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 24) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 32) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); -+ -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); -+ -+ /* Load SHA IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); -+ -+ while (crypt_off > 0 && auth_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ crypt_off -= 4; -+ auth_off -= 4; -+ } -+ -+ /* align auth and crypt */ -+ while (crypt_off > 0 && auth_len > 0) { -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVM_LOAD_SHA_UNIT(*pdata, next); -+ crypt_off -= 8; -+ auth_len -= 8; -+ } -+ -+ while (crypt_len > 0) { -+ uint32_t *pdata32[3]; -+ -+ pdata32[0] = data32; -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ pdata32[1] = data32; -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ pdata32[2] = data32; -+ mydata[1].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[1].data32[1] = *data32; -+ -+ CVMX_MT_AES_ENC_CBC0(*pdata); -+ CVMX_MT_AES_ENC_CBC1(*data); -+ CVMX_MF_AES_RESULT(*pdata, 0); -+ CVMX_MF_AES_RESULT(*data, 1); -+ crypt_len -= 16; -+ -+ if (auth_len > 0) { -+ CVM_LOAD_SHA_UNIT(*pdata, next); -+ auth_len -= 8; -+ } -+ if (auth_len > 0) { -+ CVM_LOAD_SHA_UNIT(*data, next); -+ auth_len -= 8; -+ } -+ -+ *pdata32[0] = mydata[0].data32[0]; -+ *pdata32[1] = mydata[0].data32[1]; -+ *pdata32[2] = mydata[1].data32[0]; -+ *data32 = mydata[1].data32[1]; -+ -+ SG_CONSUME(sg, data32, data_i, data_l); -+ } -+ -+ /* finish and hashing */ -+ while (auth_len > 0) { -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVM_LOAD_SHA_UNIT(*pdata, next); -+ auth_len -= 8; -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_SHA_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ tmp3 = 0; -+ CVMX_MF_HSH_IV(tmp3, 2); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ tmp3 |= 0x0000000080000000; -+ CVMX_MT_HSH_DAT(tmp3, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_MD5_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data32, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ icv_off -= 4; -+ } -+ CVMX_MF_HSH_IV(tmp1, 0); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ SG_CONSUME(sg, data32, data_i, data_l); -+ *data32 = (uint32_t) tmp1; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+int -+octo_aes_cbc_sha1_decrypt( -+ struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp) -+{ -+ register int next = 0; -+ union { -+ uint32_t data32[2]; -+ uint64_t data64[1]; -+ } mydata[2]; -+ uint64_t *pdata = &mydata[0].data64[0]; -+ uint64_t *data = &mydata[1].data64[0]; -+ uint32_t *data32; -+ uint64_t tmp1, tmp2, tmp3; -+ int data_i, data_l, alen = auth_len; -+ struct octeon_cop2_state state; -+ unsigned long flags; -+ -+ dprintk("%s(a_off=%d a_len=%d c_off=%d c_len=%d icv_off=%d)\n", -+ __FUNCTION__, auth_off, auth_len, crypt_off, crypt_len, icv_off); -+ -+ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || -+ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || -+ (crypt_len & 0x7) || -+ (auth_len & 0x7) || -+ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { -+ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " -+ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " -+ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ return -EINVAL; -+ } -+ -+ SG_INIT(sg, data32, data_i, data_l); -+ -+ CVMX_PREFETCH0(ivp); -+ CVMX_PREFETCH0(od->octo_enckey); -+ -+ flags = octeon_crypto_enable(&state); -+ -+ /* load AES Key */ -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); -+ -+ if (od->octo_encklen == 16) { -+ CVMX_MT_AES_KEY(0x0, 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 24) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(0x0, 3); -+ } else if (od->octo_encklen == 32) { -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); -+ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); -+ } else { -+ octeon_crypto_disable(&state, flags); -+ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); -+ return -EINVAL; -+ } -+ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); -+ -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); -+ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); -+ -+ /* Load SHA1 IV */ -+ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); -+ -+ while (crypt_off > 0 && auth_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ crypt_off -= 4; -+ auth_off -= 4; -+ } -+ -+ /* align auth and crypt */ -+ while (crypt_off > 0 && auth_len > 0) { -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVM_LOAD_SHA_UNIT(*pdata, next); -+ crypt_off -= 8; -+ auth_len -= 8; -+ } -+ -+ while (crypt_len > 0) { -+ uint32_t *pdata32[3]; -+ -+ pdata32[0] = data32; -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ pdata32[1] = data32; -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ pdata32[2] = data32; -+ mydata[1].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[1].data32[1] = *data32; -+ -+ if (auth_len > 0) { -+ CVM_LOAD_SHA_UNIT(*pdata, next); -+ auth_len -= 8; -+ } -+ if (auth_len > 0) { -+ CVM_LOAD_SHA_UNIT(*data, next); -+ auth_len -= 8; -+ } -+ -+ CVMX_MT_AES_DEC_CBC0(*pdata); -+ CVMX_MT_AES_DEC_CBC1(*data); -+ CVMX_MF_AES_RESULT(*pdata, 0); -+ CVMX_MF_AES_RESULT(*data, 1); -+ crypt_len -= 16; -+ -+ *pdata32[0] = mydata[0].data32[0]; -+ *pdata32[1] = mydata[0].data32[1]; -+ *pdata32[2] = mydata[1].data32[0]; -+ *data32 = mydata[1].data32[1]; -+ -+ SG_CONSUME(sg, data32, data_i, data_l); -+ } -+ -+ /* finish and leftover hashing */ -+ while (auth_len > 0) { -+ mydata[0].data32[0] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ mydata[0].data32[1] = *data32; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVM_LOAD_SHA_UNIT(*pdata, next); -+ auth_len -= 8; -+ } -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_SHA_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* Finish Inner hash */ -+ while (next != 7) { -+ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); -+ } -+ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); -+ -+ /* Get the inner hash of HMAC */ -+ CVMX_MF_HSH_IV(tmp1, 0); -+ CVMX_MF_HSH_IV(tmp2, 1); -+ tmp3 = 0; -+ CVMX_MF_HSH_IV(tmp3, 2); -+ -+ /* Initialize hash unit */ -+ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); -+ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); -+ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); -+ -+ CVMX_MT_HSH_DAT(tmp1, 0); -+ CVMX_MT_HSH_DAT(tmp2, 1); -+ tmp3 |= 0x0000000080000000; -+ CVMX_MT_HSH_DAT(tmp3, 2); -+ CVMX_MT_HSH_DATZ(3); -+ CVMX_MT_HSH_DATZ(4); -+ CVMX_MT_HSH_DATZ(5); -+ CVMX_MT_HSH_DATZ(6); -+ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); -+ -+ /* finish the hash */ -+ CVMX_PREFETCH0(od->octo_hmouter); -+#if 0 -+ if (unlikely(inplen)) { -+ uint64_t tmp = 0; -+ uint8_t *p = (uint8_t *) & tmp; -+ p[inplen] = 0x80; -+ do { -+ inplen--; -+ p[inplen] = ((uint8_t *) data)[inplen]; -+ } while (inplen); -+ CVM_LOAD_MD5_UNIT(tmp, next); -+ } else { -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+ } -+#else -+ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); -+#endif -+ -+ /* save the HMAC */ -+ SG_INIT(sg, data32, data_i, data_l); -+ while (icv_off > 0) { -+ SG_CONSUME(sg, data32, data_i, data_l); -+ icv_off -= 4; -+ } -+ CVMX_MF_HSH_IV(tmp1, 0); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ SG_CONSUME(sg, data32, data_i, data_l); -+ *data32 = (uint32_t) tmp1; -+ SG_CONSUME(sg, data32, data_i, data_l); -+ CVMX_MF_HSH_IV(tmp1, 1); -+ *data32 = (uint32_t) (tmp1 >> 32); -+ -+ octeon_crypto_disable(&state, flags); -+ return 0; -+} -+ -+/****************************************************************************/ -diff -Nur linux-3.0.4.orig/crypto/ocf/cryptocteon/cryptocteon.c linux-3.0.4/crypto/ocf/cryptocteon/cryptocteon.c ---- linux-3.0.4.orig/crypto/ocf/cryptocteon/cryptocteon.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/cryptocteon/cryptocteon.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,575 @@ -+/* -+ * Octeon Crypto for OCF -+ * -+ * Written by David McCullough -+ * Copyright (C) 2009-2010 David McCullough -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ * --------------------------------------------------------------------------- -+ */ -+ -+#include -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+struct { -+ softc_device_decl sc_dev; -+} octo_softc; -+ -+#define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK) -+ -+struct octo_sess { -+ int octo_encalg; -+ #define MAX_CIPHER_KEYLEN 64 -+ char octo_enckey[MAX_CIPHER_KEYLEN]; -+ int octo_encklen; -+ -+ int octo_macalg; -+ #define MAX_HASH_KEYLEN 64 -+ char octo_mackey[MAX_HASH_KEYLEN]; -+ int octo_macklen; -+ int octo_mackey_set; -+ -+ int octo_mlen; -+ int octo_ivsize; -+ -+ int (*octo_encrypt)(struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp); -+ int (*octo_decrypt)(struct octo_sess *od, -+ struct scatterlist *sg, int sg_len, -+ int auth_off, int auth_len, -+ int crypt_off, int crypt_len, -+ int icv_off, uint8_t *ivp); -+ -+ uint64_t octo_hminner[3]; -+ uint64_t octo_hmouter[3]; -+}; -+ -+int32_t octo_id = -1; -+module_param(octo_id, int, 0444); -+MODULE_PARM_DESC(octo_id, "Read-Only OCF ID for cryptocteon driver"); -+ -+static struct octo_sess **octo_sessions = NULL; -+static u_int32_t octo_sesnum = 0; -+ -+static int octo_process(device_t, struct cryptop *, int); -+static int octo_newsession(device_t, u_int32_t *, struct cryptoini *); -+static int octo_freesession(device_t, u_int64_t); -+ -+static device_method_t octo_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, octo_newsession), -+ DEVMETHOD(cryptodev_freesession,octo_freesession), -+ DEVMETHOD(cryptodev_process, octo_process), -+}; -+ -+#define debug octo_debug -+int octo_debug = 0; -+module_param(octo_debug, int, 0644); -+MODULE_PARM_DESC(octo_debug, "Enable debug"); -+ -+ -+#include "cavium_crypto.c" -+ -+ -+/* -+ * Generate a new octo session. We artifically limit it to a single -+ * hash/cipher or hash-cipher combo just to make it easier, most callers -+ * do not expect more than this anyway. -+ */ -+static int -+octo_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) -+{ -+ struct cryptoini *c, *encini = NULL, *macini = NULL; -+ struct octo_sess **ocd; -+ int i; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid == NULL || cri == NULL) { -+ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ /* -+ * To keep it simple, we only handle hash, cipher or hash/cipher in a -+ * session, you cannot currently do multiple ciphers/hashes in one -+ * session even though it would be possibel to code this driver to -+ * handle it. -+ */ -+ for (i = 0, c = cri; c && i < 2; i++) { -+ if (c->cri_alg == CRYPTO_MD5_HMAC || -+ c->cri_alg == CRYPTO_SHA1_HMAC || -+ c->cri_alg == CRYPTO_NULL_HMAC) { -+ if (macini) { -+ break; -+ } -+ macini = c; -+ } -+ if (c->cri_alg == CRYPTO_DES_CBC || -+ c->cri_alg == CRYPTO_3DES_CBC || -+ c->cri_alg == CRYPTO_AES_CBC || -+ c->cri_alg == CRYPTO_NULL_CBC) { -+ if (encini) { -+ break; -+ } -+ encini = c; -+ } -+ c = c->cri_next; -+ } -+ if (!macini && !encini) { -+ dprintk("%s,%d - EINVAL bad cipher/hash or combination\n", -+ __FILE__, __LINE__); -+ return EINVAL; -+ } -+ if (c) { -+ dprintk("%s,%d - EINVAL cannot handle chained cipher/hash combos\n", -+ __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ /* -+ * So we have something we can do, lets setup the session -+ */ -+ -+ if (octo_sessions) { -+ for (i = 1; i < octo_sesnum; i++) -+ if (octo_sessions[i] == NULL) -+ break; -+ } else -+ i = 1; /* NB: to silence compiler warning */ -+ -+ if (octo_sessions == NULL || i == octo_sesnum) { -+ if (octo_sessions == NULL) { -+ i = 1; /* We leave octo_sessions[0] empty */ -+ octo_sesnum = CRYPTO_SW_SESSIONS; -+ } else -+ octo_sesnum *= 2; -+ -+ ocd = kmalloc(octo_sesnum * sizeof(struct octo_sess *), SLAB_ATOMIC); -+ if (ocd == NULL) { -+ /* Reset session number */ -+ if (octo_sesnum == CRYPTO_SW_SESSIONS) -+ octo_sesnum = 0; -+ else -+ octo_sesnum /= 2; -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memset(ocd, 0, octo_sesnum * sizeof(struct octo_sess *)); -+ -+ /* Copy existing sessions */ -+ if (octo_sessions) { -+ memcpy(ocd, octo_sessions, -+ (octo_sesnum / 2) * sizeof(struct octo_sess *)); -+ kfree(octo_sessions); -+ } -+ -+ octo_sessions = ocd; -+ } -+ -+ ocd = &octo_sessions[i]; -+ *sid = i; -+ -+ -+ *ocd = (struct octo_sess *) kmalloc(sizeof(struct octo_sess), SLAB_ATOMIC); -+ if (*ocd == NULL) { -+ octo_freesession(NULL, i); -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memset(*ocd, 0, sizeof(struct octo_sess)); -+ -+ if (encini && encini->cri_key) { -+ (*ocd)->octo_encklen = (encini->cri_klen + 7) / 8; -+ memcpy((*ocd)->octo_enckey, encini->cri_key, (*ocd)->octo_encklen); -+ } -+ -+ if (macini && macini->cri_key) { -+ (*ocd)->octo_macklen = (macini->cri_klen + 7) / 8; -+ memcpy((*ocd)->octo_mackey, macini->cri_key, (*ocd)->octo_macklen); -+ } -+ -+ (*ocd)->octo_mlen = 0; -+ if (encini && encini->cri_mlen) -+ (*ocd)->octo_mlen = encini->cri_mlen; -+ else if (macini && macini->cri_mlen) -+ (*ocd)->octo_mlen = macini->cri_mlen; -+ else -+ (*ocd)->octo_mlen = 12; -+ -+ /* -+ * point c at the enc if it exists, otherwise the mac -+ */ -+ c = encini ? encini : macini; -+ -+ switch (c->cri_alg) { -+ case CRYPTO_DES_CBC: -+ case CRYPTO_3DES_CBC: -+ (*ocd)->octo_ivsize = 8; -+ switch (macini ? macini->cri_alg : -1) { -+ case CRYPTO_MD5_HMAC: -+ (*ocd)->octo_encrypt = octo_des_cbc_md5_encrypt; -+ (*ocd)->octo_decrypt = octo_des_cbc_md5_decrypt; -+ octo_calc_hash(0, macini->cri_key, (*ocd)->octo_hminner, -+ (*ocd)->octo_hmouter); -+ break; -+ case CRYPTO_SHA1_HMAC: -+ (*ocd)->octo_encrypt = octo_des_cbc_sha1_encrypt; -+ (*ocd)->octo_decrypt = octo_des_cbc_sha1_decrypt; -+ octo_calc_hash(1, macini->cri_key, (*ocd)->octo_hminner, -+ (*ocd)->octo_hmouter); -+ break; -+ case -1: -+ (*ocd)->octo_encrypt = octo_des_cbc_encrypt; -+ (*ocd)->octo_decrypt = octo_des_cbc_decrypt; -+ break; -+ default: -+ octo_freesession(NULL, i); -+ dprintk("%s,%d: EINVALn", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ break; -+ case CRYPTO_AES_CBC: -+ (*ocd)->octo_ivsize = 16; -+ switch (macini ? macini->cri_alg : -1) { -+ case CRYPTO_MD5_HMAC: -+ (*ocd)->octo_encrypt = octo_aes_cbc_md5_encrypt; -+ (*ocd)->octo_decrypt = octo_aes_cbc_md5_decrypt; -+ octo_calc_hash(0, macini->cri_key, (*ocd)->octo_hminner, -+ (*ocd)->octo_hmouter); -+ break; -+ case CRYPTO_SHA1_HMAC: -+ (*ocd)->octo_encrypt = octo_aes_cbc_sha1_encrypt; -+ (*ocd)->octo_decrypt = octo_aes_cbc_sha1_decrypt; -+ octo_calc_hash(1, macini->cri_key, (*ocd)->octo_hminner, -+ (*ocd)->octo_hmouter); -+ break; -+ case -1: -+ (*ocd)->octo_encrypt = octo_aes_cbc_encrypt; -+ (*ocd)->octo_decrypt = octo_aes_cbc_decrypt; -+ break; -+ default: -+ octo_freesession(NULL, i); -+ dprintk("%s,%d: EINVALn", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ break; -+ case CRYPTO_MD5_HMAC: -+ (*ocd)->octo_encrypt = octo_null_md5_encrypt; -+ (*ocd)->octo_decrypt = octo_null_md5_encrypt; /* encrypt == decrypt */ -+ octo_calc_hash(0, macini->cri_key, (*ocd)->octo_hminner, -+ (*ocd)->octo_hmouter); -+ break; -+ case CRYPTO_SHA1_HMAC: -+ (*ocd)->octo_encrypt = octo_null_sha1_encrypt; -+ (*ocd)->octo_decrypt = octo_null_sha1_encrypt; /* encrypt == decrypt */ -+ octo_calc_hash(1, macini->cri_key, (*ocd)->octo_hminner, -+ (*ocd)->octo_hmouter); -+ break; -+ default: -+ octo_freesession(NULL, i); -+ dprintk("%s,%d: EINVALn", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ (*ocd)->octo_encalg = encini ? encini->cri_alg : -1; -+ (*ocd)->octo_macalg = macini ? macini->cri_alg : -1; -+ -+ return 0; -+} -+ -+/* -+ * Free a session. -+ */ -+static int -+octo_freesession(device_t dev, u_int64_t tid) -+{ -+ u_int32_t sid = CRYPTO_SESID2LID(tid); -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid > octo_sesnum || octo_sessions == NULL || -+ octo_sessions[sid] == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return(EINVAL); -+ } -+ -+ /* Silently accept and return */ -+ if (sid == 0) -+ return(0); -+ -+ if (octo_sessions[sid]) -+ kfree(octo_sessions[sid]); -+ octo_sessions[sid] = NULL; -+ return 0; -+} -+ -+/* -+ * Process a request. -+ */ -+static int -+octo_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ struct cryptodesc *crd; -+ struct octo_sess *od; -+ u_int32_t lid; -+#define SCATTERLIST_MAX 16 -+ struct scatterlist sg[SCATTERLIST_MAX]; -+ int sg_num, sg_len; -+ struct sk_buff *skb = NULL; -+ struct uio *uiop = NULL; -+ struct cryptodesc *enccrd = NULL, *maccrd = NULL; -+ unsigned char *ivp = NULL; -+ unsigned char iv_data[HASH_MAX_LEN]; -+ int auth_off = 0, auth_len = 0, crypt_off = 0, crypt_len = 0, icv_off = 0; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ /* Sanity check */ -+ if (crp == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ crp->crp_etype = 0; -+ -+ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ lid = crp->crp_sid & 0xffffffff; -+ if (lid >= octo_sesnum || lid == 0 || octo_sessions == NULL || -+ octo_sessions[lid] == NULL) { -+ crp->crp_etype = ENOENT; -+ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); -+ goto done; -+ } -+ od = octo_sessions[lid]; -+ -+ /* -+ * do some error checking outside of the loop for SKB and IOV processing -+ * this leaves us with valid skb or uiop pointers for later -+ */ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ skb = (struct sk_buff *) crp->crp_buf; -+ if (skb_shinfo(skb)->nr_frags >= SCATTERLIST_MAX) { -+ printk("%s,%d: %d nr_frags > SCATTERLIST_MAX", __FILE__, __LINE__, -+ skb_shinfo(skb)->nr_frags); -+ goto done; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ uiop = (struct uio *) crp->crp_buf; -+ if (uiop->uio_iovcnt > SCATTERLIST_MAX) { -+ printk("%s,%d: %d uio_iovcnt > SCATTERLIST_MAX", __FILE__, __LINE__, -+ uiop->uio_iovcnt); -+ goto done; -+ } -+ } -+ -+ /* point our enccrd and maccrd appropriately */ -+ crd = crp->crp_desc; -+ if (crd->crd_alg == od->octo_encalg) enccrd = crd; -+ if (crd->crd_alg == od->octo_macalg) maccrd = crd; -+ crd = crd->crd_next; -+ if (crd) { -+ if (crd->crd_alg == od->octo_encalg) enccrd = crd; -+ if (crd->crd_alg == od->octo_macalg) maccrd = crd; -+ crd = crd->crd_next; -+ } -+ if (crd) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: ENOENT - descriptors do not match session\n", -+ __FILE__, __LINE__); -+ goto done; -+ } -+ -+ if (enccrd) { -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) { -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) -+ ivp = enccrd->crd_iv; -+ else -+ read_random((ivp = iv_data), od->octo_ivsize); -+ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ enccrd->crd_inject, od->octo_ivsize, ivp); -+ } else { -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) { -+ ivp = enccrd->crd_iv; -+ } else { -+ ivp = iv_data; -+ crypto_copydata(crp->crp_flags, crp->crp_buf, -+ enccrd->crd_inject, od->octo_ivsize, (caddr_t) ivp); -+ } -+ } -+ -+ if (maccrd) { -+ auth_off = maccrd->crd_skip; -+ auth_len = maccrd->crd_len; -+ icv_off = maccrd->crd_inject; -+ } -+ -+ crypt_off = enccrd->crd_skip; -+ crypt_len = enccrd->crd_len; -+ } else { /* if (maccrd) */ -+ auth_off = maccrd->crd_skip; -+ auth_len = maccrd->crd_len; -+ icv_off = maccrd->crd_inject; -+ } -+ -+ -+ /* -+ * setup the SG list to cover the buffer -+ */ -+ memset(sg, 0, sizeof(sg)); -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ int i, len; -+ -+ sg_num = 0; -+ sg_len = 0; -+ -+ len = skb_headlen(skb); -+ sg_set_page(&sg[sg_num], virt_to_page(skb->data), len, -+ offset_in_page(skb->data)); -+ sg_len += len; -+ sg_num++; -+ -+ for (i = 0; i < skb_shinfo(skb)->nr_frags && sg_num < SCATTERLIST_MAX; -+ i++) { -+ len = skb_shinfo(skb)->frags[i].size; -+ sg_set_page(&sg[sg_num], skb_shinfo(skb)->frags[i].page, -+ len, skb_shinfo(skb)->frags[i].page_offset); -+ sg_len += len; -+ sg_num++; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ int len; -+ -+ sg_len = 0; -+ for (sg_num = 0; sg_len < crp->crp_ilen && -+ sg_num < uiop->uio_iovcnt && -+ sg_num < SCATTERLIST_MAX; sg_num++) { -+ len = uiop->uio_iov[sg_num].iov_len; -+ sg_set_page(&sg[sg_num], -+ virt_to_page(uiop->uio_iov[sg_num].iov_base), len, -+ offset_in_page(uiop->uio_iov[sg_num].iov_base)); -+ sg_len += len; -+ } -+ } else { -+ sg_len = crp->crp_ilen; -+ sg_set_page(&sg[0], virt_to_page(crp->crp_buf), sg_len, -+ offset_in_page(crp->crp_buf)); -+ sg_num = 1; -+ } -+ -+ -+ /* -+ * setup a new explicit key -+ */ -+ if (enccrd) { -+ if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) { -+ od->octo_encklen = (enccrd->crd_klen + 7) / 8; -+ memcpy(od->octo_enckey, enccrd->crd_key, od->octo_encklen); -+ } -+ } -+ if (maccrd) { -+ if (maccrd->crd_flags & CRD_F_KEY_EXPLICIT) { -+ od->octo_macklen = (maccrd->crd_klen + 7) / 8; -+ memcpy(od->octo_mackey, maccrd->crd_key, od->octo_macklen); -+ od->octo_mackey_set = 0; -+ } -+ if (!od->octo_mackey_set) { -+ octo_calc_hash(maccrd->crd_alg == CRYPTO_MD5_HMAC ? 0 : 1, -+ maccrd->crd_key, od->octo_hminner, od->octo_hmouter); -+ od->octo_mackey_set = 1; -+ } -+ } -+ -+ -+ if (!enccrd || (enccrd->crd_flags & CRD_F_ENCRYPT)) -+ (*od->octo_encrypt)(od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ else -+ (*od->octo_decrypt)(od, sg, sg_len, -+ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); -+ -+done: -+ crypto_done(crp); -+ return 0; -+} -+ -+static int -+cryptocteon_init(void) -+{ -+ dprintk("%s(%p)\n", __FUNCTION__, cryptocteon_init); -+ -+ softc_device_init(&octo_softc, "cryptocteon", 0, octo_methods); -+ -+ octo_id = crypto_get_driverid(softc_get_device(&octo_softc), -+ CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SYNC); -+ if (octo_id < 0) { -+ printk("Cryptocteon device cannot initialize!"); -+ return -ENODEV; -+ } -+ -+ crypto_register(octo_id, CRYPTO_MD5_HMAC, 0,0); -+ crypto_register(octo_id, CRYPTO_SHA1_HMAC, 0,0); -+ //crypto_register(octo_id, CRYPTO_MD5, 0,0); -+ //crypto_register(octo_id, CRYPTO_SHA1, 0,0); -+ crypto_register(octo_id, CRYPTO_DES_CBC, 0,0); -+ crypto_register(octo_id, CRYPTO_3DES_CBC, 0,0); -+ crypto_register(octo_id, CRYPTO_AES_CBC, 0,0); -+ -+ return(0); -+} -+ -+static void -+cryptocteon_exit(void) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ crypto_unregister_all(octo_id); -+ octo_id = -1; -+} -+ -+module_init(cryptocteon_init); -+module_exit(cryptocteon_exit); -+ -+MODULE_LICENSE("BSD"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("Cryptocteon (OCF module for Cavium OCTEON crypto)"); -diff -Nur linux-3.0.4.orig/crypto/ocf/cryptodev.c linux-3.0.4/crypto/ocf/cryptodev.c ---- linux-3.0.4.orig/crypto/ocf/cryptodev.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/cryptodev.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,1069 @@ -+/* $OpenBSD: cryptodev.c,v 1.52 2002/06/19 07:22:46 deraadt Exp $ */ -+ -+/*- -+ * Linux port done by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * The license and original author are listed below. -+ * -+ * Copyright (c) 2001 Theo de Raadt -+ * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored in part by the Defense Advanced Research Projects -+ * Agency (DARPA) and Air Force Research Laboratory, Air Force -+ * Materiel Command, USAF, under agreement number F30602-01-2-0537. -+ * -+__FBSDID("$FreeBSD: src/sys/opencrypto/cryptodev.c,v 1.34 2007/05/09 19:37:02 gnn Exp $"); -+ */ -+ -+#include -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+extern asmlinkage long sys_dup(unsigned int fildes); -+ -+#define debug cryptodev_debug -+int cryptodev_debug = 0; -+module_param(cryptodev_debug, int, 0644); -+MODULE_PARM_DESC(cryptodev_debug, "Enable cryptodev debug"); -+ -+struct csession_info { -+ u_int16_t blocksize; -+ u_int16_t minkey, maxkey; -+ -+ u_int16_t keysize; -+ /* u_int16_t hashsize; */ -+ u_int16_t authsize; -+ u_int16_t authkey; -+ /* u_int16_t ctxsize; */ -+}; -+ -+struct csession { -+ struct list_head list; -+ u_int64_t sid; -+ u_int32_t ses; -+ -+ wait_queue_head_t waitq; -+ -+ u_int32_t cipher; -+ -+ u_int32_t mac; -+ -+ caddr_t key; -+ int keylen; -+ u_char tmp_iv[EALG_MAX_BLOCK_LEN]; -+ -+ caddr_t mackey; -+ int mackeylen; -+ -+ struct csession_info info; -+ -+ struct iovec iovec; -+ struct uio uio; -+ int error; -+}; -+ -+struct fcrypt { -+ struct list_head csessions; -+ int sesn; -+}; -+ -+static struct csession *csefind(struct fcrypt *, u_int); -+static int csedelete(struct fcrypt *, struct csession *); -+static struct csession *cseadd(struct fcrypt *, struct csession *); -+static struct csession *csecreate(struct fcrypt *, u_int64_t, -+ struct cryptoini *crie, struct cryptoini *cria, struct csession_info *); -+static int csefree(struct csession *); -+ -+static int cryptodev_op(struct csession *, struct crypt_op *); -+static int cryptodev_key(struct crypt_kop *); -+static int cryptodev_find(struct crypt_find_op *); -+ -+static int cryptodev_cb(void *); -+static int cryptodev_open(struct inode *inode, struct file *filp); -+ -+/* -+ * Check a crypto identifier to see if it requested -+ * a valid crid and it's capabilities match. -+ */ -+static int -+checkcrid(int crid) -+{ -+ int hid = crid & ~(CRYPTOCAP_F_SOFTWARE | CRYPTOCAP_F_HARDWARE); -+ int typ = crid & (CRYPTOCAP_F_SOFTWARE | CRYPTOCAP_F_HARDWARE); -+ int caps = 0; -+ -+ /* if the user hasn't selected a driver, then just call newsession */ -+ if (hid == 0 && typ != 0) -+ return 0; -+ -+ caps = crypto_getcaps(hid); -+ -+ /* didn't find anything with capabilities */ -+ if (caps == 0) { -+ dprintk("%s: hid=%x typ=%x not matched\n", __FUNCTION__, hid, typ); -+ return EINVAL; -+ } -+ -+ /* the user didn't specify SW or HW, so the driver is ok */ -+ if (typ == 0) -+ return 0; -+ -+ /* if the type specified didn't match */ -+ if (typ != (caps & (CRYPTOCAP_F_SOFTWARE | CRYPTOCAP_F_HARDWARE))) { -+ dprintk("%s: hid=%x typ=%x caps=%x not matched\n", __FUNCTION__, -+ hid, typ, caps); -+ return EINVAL; -+ } -+ -+ return 0; -+} -+ -+static int -+cryptodev_op(struct csession *cse, struct crypt_op *cop) -+{ -+ struct cryptop *crp = NULL; -+ struct cryptodesc *crde = NULL, *crda = NULL; -+ int error = 0; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (cop->len > CRYPTO_MAX_DATA_LEN) { -+ dprintk("%s: %d > %d\n", __FUNCTION__, cop->len, CRYPTO_MAX_DATA_LEN); -+ return (E2BIG); -+ } -+ -+ if (cse->info.blocksize && (cop->len % cse->info.blocksize) != 0) { -+ dprintk("%s: blocksize=%d len=%d\n", __FUNCTION__, cse->info.blocksize, -+ cop->len); -+ return (EINVAL); -+ } -+ -+ cse->uio.uio_iov = &cse->iovec; -+ cse->uio.uio_iovcnt = 1; -+ cse->uio.uio_offset = 0; -+#if 0 -+ cse->uio.uio_resid = cop->len; -+ cse->uio.uio_segflg = UIO_SYSSPACE; -+ cse->uio.uio_rw = UIO_WRITE; -+ cse->uio.uio_td = td; -+#endif -+ cse->uio.uio_iov[0].iov_len = cop->len; -+ if (cse->info.authsize) -+ cse->uio.uio_iov[0].iov_len += cse->info.authsize; -+ cse->uio.uio_iov[0].iov_base = kmalloc(cse->uio.uio_iov[0].iov_len, -+ GFP_KERNEL); -+ -+ if (cse->uio.uio_iov[0].iov_base == NULL) { -+ dprintk("%s: iov_base kmalloc(%d) failed\n", __FUNCTION__, -+ (int)cse->uio.uio_iov[0].iov_len); -+ return (ENOMEM); -+ } -+ -+ crp = crypto_getreq((cse->info.blocksize != 0) + (cse->info.authsize != 0)); -+ if (crp == NULL) { -+ dprintk("%s: ENOMEM\n", __FUNCTION__); -+ error = ENOMEM; -+ goto bail; -+ } -+ -+ if (cse->info.authsize && cse->info.blocksize) { -+ if (cop->op == COP_ENCRYPT) { -+ crde = crp->crp_desc; -+ crda = crde->crd_next; -+ } else { -+ crda = crp->crp_desc; -+ crde = crda->crd_next; -+ } -+ } else if (cse->info.authsize) { -+ crda = crp->crp_desc; -+ } else if (cse->info.blocksize) { -+ crde = crp->crp_desc; -+ } else { -+ dprintk("%s: bad request\n", __FUNCTION__); -+ error = EINVAL; -+ goto bail; -+ } -+ -+ if ((error = copy_from_user(cse->uio.uio_iov[0].iov_base, cop->src, -+ cop->len))) { -+ dprintk("%s: bad copy\n", __FUNCTION__); -+ goto bail; -+ } -+ -+ if (crda) { -+ crda->crd_skip = 0; -+ crda->crd_len = cop->len; -+ crda->crd_inject = cop->len; -+ -+ crda->crd_alg = cse->mac; -+ crda->crd_key = cse->mackey; -+ crda->crd_klen = cse->mackeylen * 8; -+ } -+ -+ if (crde) { -+ if (cop->op == COP_ENCRYPT) -+ crde->crd_flags |= CRD_F_ENCRYPT; -+ else -+ crde->crd_flags &= ~CRD_F_ENCRYPT; -+ crde->crd_len = cop->len; -+ crde->crd_inject = 0; -+ -+ crde->crd_alg = cse->cipher; -+ crde->crd_key = cse->key; -+ crde->crd_klen = cse->keylen * 8; -+ } -+ -+ crp->crp_ilen = cse->uio.uio_iov[0].iov_len; -+ crp->crp_flags = CRYPTO_F_IOV | CRYPTO_F_CBIMM -+ | (cop->flags & COP_F_BATCH); -+ crp->crp_buf = (caddr_t)&cse->uio; -+ crp->crp_callback = (int (*) (struct cryptop *)) cryptodev_cb; -+ crp->crp_sid = cse->sid; -+ crp->crp_opaque = (void *)cse; -+ -+ if (cop->iv) { -+ if (crde == NULL) { -+ error = EINVAL; -+ dprintk("%s no crde\n", __FUNCTION__); -+ goto bail; -+ } -+ if (cse->cipher == CRYPTO_ARC4) { /* XXX use flag? */ -+ error = EINVAL; -+ dprintk("%s arc4 with IV\n", __FUNCTION__); -+ goto bail; -+ } -+ if ((error = copy_from_user(cse->tmp_iv, cop->iv, -+ cse->info.blocksize))) { -+ dprintk("%s bad iv copy\n", __FUNCTION__); -+ goto bail; -+ } -+ memcpy(crde->crd_iv, cse->tmp_iv, cse->info.blocksize); -+ crde->crd_flags |= CRD_F_IV_EXPLICIT | CRD_F_IV_PRESENT; -+ crde->crd_skip = 0; -+ } else if (cse->cipher == CRYPTO_ARC4) { /* XXX use flag? */ -+ crde->crd_skip = 0; -+ } else if (crde) { -+ crde->crd_flags |= CRD_F_IV_PRESENT; -+ crde->crd_skip = cse->info.blocksize; -+ crde->crd_len -= cse->info.blocksize; -+ } -+ -+ if (cop->mac && crda == NULL) { -+ error = EINVAL; -+ dprintk("%s no crda\n", __FUNCTION__); -+ goto bail; -+ } -+ -+ /* -+ * Let the dispatch run unlocked, then, interlock against the -+ * callback before checking if the operation completed and going -+ * to sleep. This insures drivers don't inherit our lock which -+ * results in a lock order reversal between crypto_dispatch forced -+ * entry and the crypto_done callback into us. -+ */ -+ error = crypto_dispatch(crp); -+ if (error) { -+ dprintk("%s error in crypto_dispatch\n", __FUNCTION__); -+ goto bail; -+ } -+ -+ dprintk("%s about to WAIT\n", __FUNCTION__); -+ /* -+ * we really need to wait for driver to complete to maintain -+ * state, luckily interrupts will be remembered -+ */ -+ do { -+ error = wait_event_interruptible(crp->crp_waitq, -+ ((crp->crp_flags & CRYPTO_F_DONE) != 0)); -+ /* -+ * we can't break out of this loop or we will leave behind -+ * a huge mess, however, staying here means if your driver -+ * is broken user applications can hang and not be killed. -+ * The solution, fix your driver :-) -+ */ -+ if (error) { -+ schedule(); -+ error = 0; -+ } -+ } while ((crp->crp_flags & CRYPTO_F_DONE) == 0); -+ dprintk("%s finished WAITING error=%d\n", __FUNCTION__, error); -+ -+ if (crp->crp_etype != 0) { -+ error = crp->crp_etype; -+ dprintk("%s error in crp processing\n", __FUNCTION__); -+ goto bail; -+ } -+ -+ if (cse->error) { -+ error = cse->error; -+ dprintk("%s error in cse processing\n", __FUNCTION__); -+ goto bail; -+ } -+ -+ if (cop->dst && (error = copy_to_user(cop->dst, -+ cse->uio.uio_iov[0].iov_base, cop->len))) { -+ dprintk("%s bad dst copy\n", __FUNCTION__); -+ goto bail; -+ } -+ -+ if (cop->mac && -+ (error=copy_to_user(cop->mac, -+ (caddr_t)cse->uio.uio_iov[0].iov_base + cop->len, -+ cse->info.authsize))) { -+ dprintk("%s bad mac copy\n", __FUNCTION__); -+ goto bail; -+ } -+ -+bail: -+ if (crp) -+ crypto_freereq(crp); -+ if (cse->uio.uio_iov[0].iov_base) -+ kfree(cse->uio.uio_iov[0].iov_base); -+ -+ return (error); -+} -+ -+static int -+cryptodev_cb(void *op) -+{ -+ struct cryptop *crp = (struct cryptop *) op; -+ struct csession *cse = (struct csession *)crp->crp_opaque; -+ int error; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ error = crp->crp_etype; -+ if (error == EAGAIN) { -+ crp->crp_flags &= ~CRYPTO_F_DONE; -+#ifdef NOTYET -+ /* -+ * DAVIDM I am fairly sure that we should turn this into a batch -+ * request to stop bad karma/lockup, revisit -+ */ -+ crp->crp_flags |= CRYPTO_F_BATCH; -+#endif -+ return crypto_dispatch(crp); -+ } -+ if (error != 0 || (crp->crp_flags & CRYPTO_F_DONE)) { -+ cse->error = error; -+ wake_up_interruptible(&crp->crp_waitq); -+ } -+ return (0); -+} -+ -+static int -+cryptodevkey_cb(void *op) -+{ -+ struct cryptkop *krp = (struct cryptkop *) op; -+ dprintk("%s()\n", __FUNCTION__); -+ wake_up_interruptible(&krp->krp_waitq); -+ return (0); -+} -+ -+static int -+cryptodev_key(struct crypt_kop *kop) -+{ -+ struct cryptkop *krp = NULL; -+ int error = EINVAL; -+ int in, out, size, i; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (kop->crk_iparams + kop->crk_oparams > CRK_MAXPARAM) { -+ dprintk("%s params too big\n", __FUNCTION__); -+ return (EFBIG); -+ } -+ -+ in = kop->crk_iparams; -+ out = kop->crk_oparams; -+ switch (kop->crk_op) { -+ case CRK_MOD_EXP: -+ if (in == 3 && out == 1) -+ break; -+ return (EINVAL); -+ case CRK_MOD_EXP_CRT: -+ if (in == 6 && out == 1) -+ break; -+ return (EINVAL); -+ case CRK_DSA_SIGN: -+ if (in == 5 && out == 2) -+ break; -+ return (EINVAL); -+ case CRK_DSA_VERIFY: -+ if (in == 7 && out == 0) -+ break; -+ return (EINVAL); -+ case CRK_DH_COMPUTE_KEY: -+ if (in == 3 && out == 1) -+ break; -+ return (EINVAL); -+ default: -+ return (EINVAL); -+ } -+ -+ krp = (struct cryptkop *)kmalloc(sizeof *krp, GFP_KERNEL); -+ if (!krp) -+ return (ENOMEM); -+ bzero(krp, sizeof *krp); -+ krp->krp_op = kop->crk_op; -+ krp->krp_status = kop->crk_status; -+ krp->krp_iparams = kop->crk_iparams; -+ krp->krp_oparams = kop->crk_oparams; -+ krp->krp_crid = kop->crk_crid; -+ krp->krp_status = 0; -+ krp->krp_flags = CRYPTO_KF_CBIMM; -+ krp->krp_callback = (int (*) (struct cryptkop *)) cryptodevkey_cb; -+ init_waitqueue_head(&krp->krp_waitq); -+ -+ for (i = 0; i < CRK_MAXPARAM; i++) -+ krp->krp_param[i].crp_nbits = kop->crk_param[i].crp_nbits; -+ for (i = 0; i < krp->krp_iparams + krp->krp_oparams; i++) { -+ size = (krp->krp_param[i].crp_nbits + 7) / 8; -+ if (size == 0) -+ continue; -+ krp->krp_param[i].crp_p = (caddr_t) kmalloc(size, GFP_KERNEL); -+ if (i >= krp->krp_iparams) -+ continue; -+ error = copy_from_user(krp->krp_param[i].crp_p, -+ kop->crk_param[i].crp_p, size); -+ if (error) -+ goto fail; -+ } -+ -+ error = crypto_kdispatch(krp); -+ if (error) -+ goto fail; -+ -+ do { -+ error = wait_event_interruptible(krp->krp_waitq, -+ ((krp->krp_flags & CRYPTO_KF_DONE) != 0)); -+ /* -+ * we can't break out of this loop or we will leave behind -+ * a huge mess, however, staying here means if your driver -+ * is broken user applications can hang and not be killed. -+ * The solution, fix your driver :-) -+ */ -+ if (error) { -+ schedule(); -+ error = 0; -+ } -+ } while ((krp->krp_flags & CRYPTO_KF_DONE) == 0); -+ -+ dprintk("%s finished WAITING error=%d\n", __FUNCTION__, error); -+ -+ kop->crk_crid = krp->krp_crid; /* device that did the work */ -+ if (krp->krp_status != 0) { -+ error = krp->krp_status; -+ goto fail; -+ } -+ -+ for (i = krp->krp_iparams; i < krp->krp_iparams + krp->krp_oparams; i++) { -+ size = (krp->krp_param[i].crp_nbits + 7) / 8; -+ if (size == 0) -+ continue; -+ error = copy_to_user(kop->crk_param[i].crp_p, krp->krp_param[i].crp_p, -+ size); -+ if (error) -+ goto fail; -+ } -+ -+fail: -+ if (krp) { -+ kop->crk_status = krp->krp_status; -+ for (i = 0; i < CRK_MAXPARAM; i++) { -+ if (krp->krp_param[i].crp_p) -+ kfree(krp->krp_param[i].crp_p); -+ } -+ kfree(krp); -+ } -+ return (error); -+} -+ -+static int -+cryptodev_find(struct crypt_find_op *find) -+{ -+ device_t dev; -+ -+ if (find->crid != -1) { -+ dev = crypto_find_device_byhid(find->crid); -+ if (dev == NULL) -+ return (ENOENT); -+ strlcpy(find->name, device_get_nameunit(dev), -+ sizeof(find->name)); -+ } else { -+ find->crid = crypto_find_driver(find->name); -+ if (find->crid == -1) -+ return (ENOENT); -+ } -+ return (0); -+} -+ -+static struct csession * -+csefind(struct fcrypt *fcr, u_int ses) -+{ -+ struct csession *cse; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ list_for_each_entry(cse, &fcr->csessions, list) -+ if (cse->ses == ses) -+ return (cse); -+ return (NULL); -+} -+ -+static int -+csedelete(struct fcrypt *fcr, struct csession *cse_del) -+{ -+ struct csession *cse; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ list_for_each_entry(cse, &fcr->csessions, list) { -+ if (cse == cse_del) { -+ list_del(&cse->list); -+ return (1); -+ } -+ } -+ return (0); -+} -+ -+static struct csession * -+cseadd(struct fcrypt *fcr, struct csession *cse) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ list_add_tail(&cse->list, &fcr->csessions); -+ cse->ses = fcr->sesn++; -+ return (cse); -+} -+ -+static struct csession * -+csecreate(struct fcrypt *fcr, u_int64_t sid, struct cryptoini *crie, -+ struct cryptoini *cria, struct csession_info *info) -+{ -+ struct csession *cse; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ cse = (struct csession *) kmalloc(sizeof(struct csession), GFP_KERNEL); -+ if (cse == NULL) -+ return NULL; -+ memset(cse, 0, sizeof(struct csession)); -+ -+ INIT_LIST_HEAD(&cse->list); -+ init_waitqueue_head(&cse->waitq); -+ -+ cse->key = crie->cri_key; -+ cse->keylen = crie->cri_klen/8; -+ cse->mackey = cria->cri_key; -+ cse->mackeylen = cria->cri_klen/8; -+ cse->sid = sid; -+ cse->cipher = crie->cri_alg; -+ cse->mac = cria->cri_alg; -+ cse->info = *info; -+ cseadd(fcr, cse); -+ return (cse); -+} -+ -+static int -+csefree(struct csession *cse) -+{ -+ int error; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ error = crypto_freesession(cse->sid); -+ if (cse->key) -+ kfree(cse->key); -+ if (cse->mackey) -+ kfree(cse->mackey); -+ kfree(cse); -+ return(error); -+} -+ -+static int -+cryptodev_ioctl( -+ struct inode *inode, -+ struct file *filp, -+ unsigned int cmd, -+ unsigned long arg) -+{ -+ struct cryptoini cria, crie; -+ struct fcrypt *fcr = filp->private_data; -+ struct csession *cse; -+ struct csession_info info; -+ struct session2_op sop; -+ struct crypt_op cop; -+ struct crypt_kop kop; -+ struct crypt_find_op fop; -+ u_int64_t sid; -+ u_int32_t ses = 0; -+ int feat, fd, error = 0, crid; -+ mm_segment_t fs; -+ -+ dprintk("%s(cmd=%x arg=%lx)\n", __FUNCTION__, cmd, arg); -+ -+ switch (cmd) { -+ -+ case CRIOGET: { -+ dprintk("%s(CRIOGET)\n", __FUNCTION__); -+ fs = get_fs(); -+ set_fs(get_ds()); -+ for (fd = 0; fd < files_fdtable(current->files)->max_fds; fd++) -+ if (files_fdtable(current->files)->fd[fd] == filp) -+ break; -+ fd = sys_dup(fd); -+ set_fs(fs); -+ put_user(fd, (int *) arg); -+ return IS_ERR_VALUE(fd) ? fd : 0; -+ } -+ -+#define CIOCGSESSSTR (cmd == CIOCGSESSION ? "CIOCGSESSION" : "CIOCGSESSION2") -+ case CIOCGSESSION: -+ case CIOCGSESSION2: -+ dprintk("%s(%s)\n", __FUNCTION__, CIOCGSESSSTR); -+ memset(&crie, 0, sizeof(crie)); -+ memset(&cria, 0, sizeof(cria)); -+ memset(&info, 0, sizeof(info)); -+ memset(&sop, 0, sizeof(sop)); -+ -+ if (copy_from_user(&sop, (void*)arg, (cmd == CIOCGSESSION) ? -+ sizeof(struct session_op) : sizeof(sop))) { -+ dprintk("%s(%s) - bad copy\n", __FUNCTION__, CIOCGSESSSTR); -+ error = EFAULT; -+ goto bail; -+ } -+ -+ switch (sop.cipher) { -+ case 0: -+ dprintk("%s(%s) - no cipher\n", __FUNCTION__, CIOCGSESSSTR); -+ break; -+ case CRYPTO_NULL_CBC: -+ info.blocksize = NULL_BLOCK_LEN; -+ info.minkey = NULL_MIN_KEY_LEN; -+ info.maxkey = NULL_MAX_KEY_LEN; -+ break; -+ case CRYPTO_DES_CBC: -+ info.blocksize = DES_BLOCK_LEN; -+ info.minkey = DES_MIN_KEY_LEN; -+ info.maxkey = DES_MAX_KEY_LEN; -+ break; -+ case CRYPTO_3DES_CBC: -+ info.blocksize = DES3_BLOCK_LEN; -+ info.minkey = DES3_MIN_KEY_LEN; -+ info.maxkey = DES3_MAX_KEY_LEN; -+ break; -+ case CRYPTO_BLF_CBC: -+ info.blocksize = BLOWFISH_BLOCK_LEN; -+ info.minkey = BLOWFISH_MIN_KEY_LEN; -+ info.maxkey = BLOWFISH_MAX_KEY_LEN; -+ break; -+ case CRYPTO_CAST_CBC: -+ info.blocksize = CAST128_BLOCK_LEN; -+ info.minkey = CAST128_MIN_KEY_LEN; -+ info.maxkey = CAST128_MAX_KEY_LEN; -+ break; -+ case CRYPTO_SKIPJACK_CBC: -+ info.blocksize = SKIPJACK_BLOCK_LEN; -+ info.minkey = SKIPJACK_MIN_KEY_LEN; -+ info.maxkey = SKIPJACK_MAX_KEY_LEN; -+ break; -+ case CRYPTO_AES_CBC: -+ info.blocksize = AES_BLOCK_LEN; -+ info.minkey = AES_MIN_KEY_LEN; -+ info.maxkey = AES_MAX_KEY_LEN; -+ break; -+ case CRYPTO_ARC4: -+ info.blocksize = ARC4_BLOCK_LEN; -+ info.minkey = ARC4_MIN_KEY_LEN; -+ info.maxkey = ARC4_MAX_KEY_LEN; -+ break; -+ case CRYPTO_CAMELLIA_CBC: -+ info.blocksize = CAMELLIA_BLOCK_LEN; -+ info.minkey = CAMELLIA_MIN_KEY_LEN; -+ info.maxkey = CAMELLIA_MAX_KEY_LEN; -+ break; -+ default: -+ dprintk("%s(%s) - bad cipher\n", __FUNCTION__, CIOCGSESSSTR); -+ error = EINVAL; -+ goto bail; -+ } -+ -+ switch (sop.mac) { -+ case 0: -+ dprintk("%s(%s) - no mac\n", __FUNCTION__, CIOCGSESSSTR); -+ break; -+ case CRYPTO_NULL_HMAC: -+ info.authsize = NULL_HASH_LEN; -+ break; -+ case CRYPTO_MD5: -+ info.authsize = MD5_HASH_LEN; -+ break; -+ case CRYPTO_SHA1: -+ info.authsize = SHA1_HASH_LEN; -+ break; -+ case CRYPTO_SHA2_256: -+ info.authsize = SHA2_256_HASH_LEN; -+ break; -+ case CRYPTO_SHA2_384: -+ info.authsize = SHA2_384_HASH_LEN; -+ break; -+ case CRYPTO_SHA2_512: -+ info.authsize = SHA2_512_HASH_LEN; -+ break; -+ case CRYPTO_RIPEMD160: -+ info.authsize = RIPEMD160_HASH_LEN; -+ break; -+ case CRYPTO_MD5_HMAC: -+ info.authsize = MD5_HASH_LEN; -+ info.authkey = 16; -+ break; -+ case CRYPTO_SHA1_HMAC: -+ info.authsize = SHA1_HASH_LEN; -+ info.authkey = 20; -+ break; -+ case CRYPTO_SHA2_256_HMAC: -+ info.authsize = SHA2_256_HASH_LEN; -+ info.authkey = 32; -+ break; -+ case CRYPTO_SHA2_384_HMAC: -+ info.authsize = SHA2_384_HASH_LEN; -+ info.authkey = 48; -+ break; -+ case CRYPTO_SHA2_512_HMAC: -+ info.authsize = SHA2_512_HASH_LEN; -+ info.authkey = 64; -+ break; -+ case CRYPTO_RIPEMD160_HMAC: -+ info.authsize = RIPEMD160_HASH_LEN; -+ info.authkey = 20; -+ break; -+ default: -+ dprintk("%s(%s) - bad mac\n", __FUNCTION__, CIOCGSESSSTR); -+ error = EINVAL; -+ goto bail; -+ } -+ -+ if (info.blocksize) { -+ crie.cri_alg = sop.cipher; -+ crie.cri_klen = sop.keylen * 8; -+ if ((info.maxkey && sop.keylen > info.maxkey) || -+ sop.keylen < info.minkey) { -+ dprintk("%s(%s) - bad key\n", __FUNCTION__, CIOCGSESSSTR); -+ error = EINVAL; -+ goto bail; -+ } -+ -+ crie.cri_key = (u_int8_t *) kmalloc(crie.cri_klen/8+1, GFP_KERNEL); -+ if (copy_from_user(crie.cri_key, sop.key, -+ crie.cri_klen/8)) { -+ dprintk("%s(%s) - bad copy\n", __FUNCTION__, CIOCGSESSSTR); -+ error = EFAULT; -+ goto bail; -+ } -+ if (info.authsize) -+ crie.cri_next = &cria; -+ } -+ -+ if (info.authsize) { -+ cria.cri_alg = sop.mac; -+ cria.cri_klen = sop.mackeylen * 8; -+ if (info.authkey && sop.mackeylen != info.authkey) { -+ dprintk("%s(%s) - mackeylen %d != %d\n", __FUNCTION__, -+ CIOCGSESSSTR, sop.mackeylen, info.authkey); -+ error = EINVAL; -+ goto bail; -+ } -+ -+ if (cria.cri_klen) { -+ cria.cri_key = (u_int8_t *) kmalloc(cria.cri_klen/8,GFP_KERNEL); -+ if (copy_from_user(cria.cri_key, sop.mackey, -+ cria.cri_klen / 8)) { -+ dprintk("%s(%s) - bad copy\n", __FUNCTION__, CIOCGSESSSTR); -+ error = EFAULT; -+ goto bail; -+ } -+ } -+ } -+ -+ /* NB: CIOGSESSION2 has the crid */ -+ if (cmd == CIOCGSESSION2) { -+ crid = sop.crid; -+ error = checkcrid(crid); -+ if (error) { -+ dprintk("%s(%s) - checkcrid %x\n", __FUNCTION__, -+ CIOCGSESSSTR, error); -+ goto bail; -+ } -+ } else { -+ /* allow either HW or SW to be used */ -+ crid = CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE; -+ } -+ error = crypto_newsession(&sid, (info.blocksize ? &crie : &cria), crid); -+ if (error) { -+ dprintk("%s(%s) - newsession %d\n",__FUNCTION__,CIOCGSESSSTR,error); -+ goto bail; -+ } -+ -+ cse = csecreate(fcr, sid, &crie, &cria, &info); -+ if (cse == NULL) { -+ crypto_freesession(sid); -+ error = EINVAL; -+ dprintk("%s(%s) - csecreate failed\n", __FUNCTION__, CIOCGSESSSTR); -+ goto bail; -+ } -+ sop.ses = cse->ses; -+ -+ if (cmd == CIOCGSESSION2) { -+ /* return hardware/driver id */ -+ sop.crid = CRYPTO_SESID2HID(cse->sid); -+ } -+ -+ if (copy_to_user((void*)arg, &sop, (cmd == CIOCGSESSION) ? -+ sizeof(struct session_op) : sizeof(sop))) { -+ dprintk("%s(%s) - bad copy\n", __FUNCTION__, CIOCGSESSSTR); -+ error = EFAULT; -+ } -+bail: -+ if (error) { -+ dprintk("%s(%s) - bail %d\n", __FUNCTION__, CIOCGSESSSTR, error); -+ if (crie.cri_key) -+ kfree(crie.cri_key); -+ if (cria.cri_key) -+ kfree(cria.cri_key); -+ } -+ break; -+ case CIOCFSESSION: -+ dprintk("%s(CIOCFSESSION)\n", __FUNCTION__); -+ get_user(ses, (uint32_t*)arg); -+ cse = csefind(fcr, ses); -+ if (cse == NULL) { -+ error = EINVAL; -+ dprintk("%s(CIOCFSESSION) - Fail %d\n", __FUNCTION__, error); -+ break; -+ } -+ csedelete(fcr, cse); -+ error = csefree(cse); -+ break; -+ case CIOCCRYPT: -+ dprintk("%s(CIOCCRYPT)\n", __FUNCTION__); -+ if(copy_from_user(&cop, (void*)arg, sizeof(cop))) { -+ dprintk("%s(CIOCCRYPT) - bad copy\n", __FUNCTION__); -+ error = EFAULT; -+ goto bail; -+ } -+ cse = csefind(fcr, cop.ses); -+ if (cse == NULL) { -+ error = EINVAL; -+ dprintk("%s(CIOCCRYPT) - Fail %d\n", __FUNCTION__, error); -+ break; -+ } -+ error = cryptodev_op(cse, &cop); -+ if(copy_to_user((void*)arg, &cop, sizeof(cop))) { -+ dprintk("%s(CIOCCRYPT) - bad return copy\n", __FUNCTION__); -+ error = EFAULT; -+ goto bail; -+ } -+ break; -+ case CIOCKEY: -+ case CIOCKEY2: -+ dprintk("%s(CIOCKEY)\n", __FUNCTION__); -+ if (!crypto_userasymcrypto) -+ return (EPERM); /* XXX compat? */ -+ if(copy_from_user(&kop, (void*)arg, sizeof(kop))) { -+ dprintk("%s(CIOCKEY) - bad copy\n", __FUNCTION__); -+ error = EFAULT; -+ goto bail; -+ } -+ if (cmd == CIOCKEY) { -+ /* NB: crypto core enforces s/w driver use */ -+ kop.crk_crid = -+ CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE; -+ } -+ error = cryptodev_key(&kop); -+ if(copy_to_user((void*)arg, &kop, sizeof(kop))) { -+ dprintk("%s(CIOCGKEY) - bad return copy\n", __FUNCTION__); -+ error = EFAULT; -+ goto bail; -+ } -+ break; -+ case CIOCASYMFEAT: -+ dprintk("%s(CIOCASYMFEAT)\n", __FUNCTION__); -+ if (!crypto_userasymcrypto) { -+ /* -+ * NB: if user asym crypto operations are -+ * not permitted return "no algorithms" -+ * so well-behaved applications will just -+ * fallback to doing them in software. -+ */ -+ feat = 0; -+ } else -+ error = crypto_getfeat(&feat); -+ if (!error) { -+ error = copy_to_user((void*)arg, &feat, sizeof(feat)); -+ } -+ break; -+ case CIOCFINDDEV: -+ if (copy_from_user(&fop, (void*)arg, sizeof(fop))) { -+ dprintk("%s(CIOCFINDDEV) - bad copy\n", __FUNCTION__); -+ error = EFAULT; -+ goto bail; -+ } -+ error = cryptodev_find(&fop); -+ if (copy_to_user((void*)arg, &fop, sizeof(fop))) { -+ dprintk("%s(CIOCFINDDEV) - bad return copy\n", __FUNCTION__); -+ error = EFAULT; -+ goto bail; -+ } -+ break; -+ default: -+ dprintk("%s(unknown ioctl 0x%x)\n", __FUNCTION__, cmd); -+ error = EINVAL; -+ break; -+ } -+ return(-error); -+} -+ -+#ifdef HAVE_UNLOCKED_IOCTL -+static long -+cryptodev_unlocked_ioctl( -+ struct file *filp, -+ unsigned int cmd, -+ unsigned long arg) -+{ -+ return cryptodev_ioctl(NULL, filp, cmd, arg); -+} -+#endif -+ -+static int -+cryptodev_open(struct inode *inode, struct file *filp) -+{ -+ struct fcrypt *fcr; -+ -+ dprintk("%s()\n", __FUNCTION__); -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35) -+ /* -+ * on 2.6.35 private_data points to a miscdevice structure, we override -+ * it, which is currently safe to do. -+ */ -+ if (filp->private_data) { -+ printk("cryptodev: Private data already exists - %p!\n", filp->private_data); -+ return(-ENODEV); -+ } -+#endif -+ -+ fcr = kmalloc(sizeof(*fcr), GFP_KERNEL); -+ if (!fcr) { -+ dprintk("%s() - malloc failed\n", __FUNCTION__); -+ return(-ENOMEM); -+ } -+ memset(fcr, 0, sizeof(*fcr)); -+ -+ INIT_LIST_HEAD(&fcr->csessions); -+ filp->private_data = fcr; -+ return(0); -+} -+ -+static int -+cryptodev_release(struct inode *inode, struct file *filp) -+{ -+ struct fcrypt *fcr = filp->private_data; -+ struct csession *cse, *tmp; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (!filp) { -+ printk("cryptodev: No private data on release\n"); -+ return(0); -+ } -+ -+ list_for_each_entry_safe(cse, tmp, &fcr->csessions, list) { -+ list_del(&cse->list); -+ (void)csefree(cse); -+ } -+ filp->private_data = NULL; -+ kfree(fcr); -+ return(0); -+} -+ -+static struct file_operations cryptodev_fops = { -+ .owner = THIS_MODULE, -+ .open = cryptodev_open, -+ .release = cryptodev_release, -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36) -+ .ioctl = cryptodev_ioctl, -+#endif -+#ifdef HAVE_UNLOCKED_IOCTL -+ .unlocked_ioctl = cryptodev_unlocked_ioctl, -+#endif -+}; -+ -+static struct miscdevice cryptodev = { -+ .minor = CRYPTODEV_MINOR, -+ .name = "crypto", -+ .fops = &cryptodev_fops, -+}; -+ -+static int __init -+cryptodev_init(void) -+{ -+ int rc; -+ -+ dprintk("%s(%p)\n", __FUNCTION__, cryptodev_init); -+ rc = misc_register(&cryptodev); -+ if (rc) { -+ printk(KERN_ERR "cryptodev: registration of /dev/crypto failed\n"); -+ return(rc); -+ } -+ -+ return(0); -+} -+ -+static void __exit -+cryptodev_exit(void) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ misc_deregister(&cryptodev); -+} -+ -+module_init(cryptodev_init); -+module_exit(cryptodev_exit); -+ -+MODULE_LICENSE("BSD"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("Cryptodev (user interface to OCF)"); -diff -Nur linux-3.0.4.orig/crypto/ocf/cryptodev.h linux-3.0.4/crypto/ocf/cryptodev.h ---- linux-3.0.4.orig/crypto/ocf/cryptodev.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/cryptodev.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,480 @@ -+/* $FreeBSD: src/sys/opencrypto/cryptodev.h,v 1.25 2007/05/09 19:37:02 gnn Exp $ */ -+/* $OpenBSD: cryptodev.h,v 1.31 2002/06/11 11:14:29 beck Exp $ */ -+ -+/*- -+ * Linux port done by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * The license and original author are listed below. -+ * -+ * The author of this code is Angelos D. Keromytis (angelos@cis.upenn.edu) -+ * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting -+ * -+ * This code was written by Angelos D. Keromytis in Athens, Greece, in -+ * February 2000. Network Security Technologies Inc. (NSTI) kindly -+ * supported the development of this code. -+ * -+ * Copyright (c) 2000 Angelos D. Keromytis -+ * -+ * Permission to use, copy, and modify this software with or without fee -+ * is hereby granted, provided that this entire notice is included in -+ * all source code copies of any software which is or includes a copy or -+ * modification of this software. -+ * -+ * THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR -+ * IMPLIED WARRANTY. IN PARTICULAR, NONE OF THE AUTHORS MAKES ANY -+ * REPRESENTATION OR WARRANTY OF ANY KIND CONCERNING THE -+ * MERCHANTABILITY OF THIS SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR -+ * PURPOSE. -+ * -+ * Copyright (c) 2001 Theo de Raadt -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored in part by the Defense Advanced Research Projects -+ * Agency (DARPA) and Air Force Research Laboratory, Air Force -+ * Materiel Command, USAF, under agreement number F30602-01-2-0537. -+ * -+ */ -+ -+#ifndef _CRYPTO_CRYPTO_H_ -+#define _CRYPTO_CRYPTO_H_ -+ -+/* Some initial values */ -+#define CRYPTO_DRIVERS_INITIAL 4 -+#define CRYPTO_SW_SESSIONS 32 -+ -+/* Hash values */ -+#define NULL_HASH_LEN 0 -+#define MD5_HASH_LEN 16 -+#define SHA1_HASH_LEN 20 -+#define RIPEMD160_HASH_LEN 20 -+#define SHA2_256_HASH_LEN 32 -+#define SHA2_384_HASH_LEN 48 -+#define SHA2_512_HASH_LEN 64 -+#define MD5_KPDK_HASH_LEN 16 -+#define SHA1_KPDK_HASH_LEN 20 -+/* Maximum hash algorithm result length */ -+#define HASH_MAX_LEN SHA2_512_HASH_LEN /* Keep this updated */ -+ -+/* HMAC values */ -+#define NULL_HMAC_BLOCK_LEN 1 -+#define MD5_HMAC_BLOCK_LEN 64 -+#define SHA1_HMAC_BLOCK_LEN 64 -+#define RIPEMD160_HMAC_BLOCK_LEN 64 -+#define SHA2_256_HMAC_BLOCK_LEN 64 -+#define SHA2_384_HMAC_BLOCK_LEN 128 -+#define SHA2_512_HMAC_BLOCK_LEN 128 -+/* Maximum HMAC block length */ -+#define HMAC_MAX_BLOCK_LEN SHA2_512_HMAC_BLOCK_LEN /* Keep this updated */ -+#define HMAC_IPAD_VAL 0x36 -+#define HMAC_OPAD_VAL 0x5C -+ -+/* Encryption algorithm block sizes */ -+#define NULL_BLOCK_LEN 1 -+#define DES_BLOCK_LEN 8 -+#define DES3_BLOCK_LEN 8 -+#define BLOWFISH_BLOCK_LEN 8 -+#define SKIPJACK_BLOCK_LEN 8 -+#define CAST128_BLOCK_LEN 8 -+#define RIJNDAEL128_BLOCK_LEN 16 -+#define AES_BLOCK_LEN RIJNDAEL128_BLOCK_LEN -+#define CAMELLIA_BLOCK_LEN 16 -+#define ARC4_BLOCK_LEN 1 -+#define EALG_MAX_BLOCK_LEN AES_BLOCK_LEN /* Keep this updated */ -+ -+/* Encryption algorithm min and max key sizes */ -+#define NULL_MIN_KEY_LEN 0 -+#define NULL_MAX_KEY_LEN 0 -+#define DES_MIN_KEY_LEN 8 -+#define DES_MAX_KEY_LEN 8 -+#define DES3_MIN_KEY_LEN 24 -+#define DES3_MAX_KEY_LEN 24 -+#define BLOWFISH_MIN_KEY_LEN 4 -+#define BLOWFISH_MAX_KEY_LEN 56 -+#define SKIPJACK_MIN_KEY_LEN 10 -+#define SKIPJACK_MAX_KEY_LEN 10 -+#define CAST128_MIN_KEY_LEN 5 -+#define CAST128_MAX_KEY_LEN 16 -+#define RIJNDAEL128_MIN_KEY_LEN 16 -+#define RIJNDAEL128_MAX_KEY_LEN 32 -+#define AES_MIN_KEY_LEN RIJNDAEL128_MIN_KEY_LEN -+#define AES_MAX_KEY_LEN RIJNDAEL128_MAX_KEY_LEN -+#define CAMELLIA_MIN_KEY_LEN 16 -+#define CAMELLIA_MAX_KEY_LEN 32 -+#define ARC4_MIN_KEY_LEN 1 -+#define ARC4_MAX_KEY_LEN 256 -+ -+/* Max size of data that can be processed */ -+#define CRYPTO_MAX_DATA_LEN 64*1024 - 1 -+ -+#define CRYPTO_ALGORITHM_MIN 1 -+#define CRYPTO_DES_CBC 1 -+#define CRYPTO_3DES_CBC 2 -+#define CRYPTO_BLF_CBC 3 -+#define CRYPTO_CAST_CBC 4 -+#define CRYPTO_SKIPJACK_CBC 5 -+#define CRYPTO_MD5_HMAC 6 -+#define CRYPTO_SHA1_HMAC 7 -+#define CRYPTO_RIPEMD160_HMAC 8 -+#define CRYPTO_MD5_KPDK 9 -+#define CRYPTO_SHA1_KPDK 10 -+#define CRYPTO_RIJNDAEL128_CBC 11 /* 128 bit blocksize */ -+#define CRYPTO_AES_CBC 11 /* 128 bit blocksize -- the same as above */ -+#define CRYPTO_ARC4 12 -+#define CRYPTO_MD5 13 -+#define CRYPTO_SHA1 14 -+#define CRYPTO_NULL_HMAC 15 -+#define CRYPTO_NULL_CBC 16 -+#define CRYPTO_DEFLATE_COMP 17 /* Deflate compression algorithm */ -+#define CRYPTO_SHA2_256_HMAC 18 -+#define CRYPTO_SHA2_384_HMAC 19 -+#define CRYPTO_SHA2_512_HMAC 20 -+#define CRYPTO_CAMELLIA_CBC 21 -+#define CRYPTO_SHA2_256 22 -+#define CRYPTO_SHA2_384 23 -+#define CRYPTO_SHA2_512 24 -+#define CRYPTO_RIPEMD160 25 -+#define CRYPTO_LZS_COMP 26 -+#define CRYPTO_ALGORITHM_MAX 26 /* Keep updated - see above */ -+ -+/* Algorithm flags */ -+#define CRYPTO_ALG_FLAG_SUPPORTED 0x01 /* Algorithm is supported */ -+#define CRYPTO_ALG_FLAG_RNG_ENABLE 0x02 /* Has HW RNG for DH/DSA */ -+#define CRYPTO_ALG_FLAG_DSA_SHA 0x04 /* Can do SHA on msg */ -+ -+/* -+ * Crypto driver/device flags. They can set in the crid -+ * parameter when creating a session or submitting a key -+ * op to affect the device/driver assigned. If neither -+ * of these are specified then the crid is assumed to hold -+ * the driver id of an existing (and suitable) device that -+ * must be used to satisfy the request. -+ */ -+#define CRYPTO_FLAG_HARDWARE 0x01000000 /* hardware accelerated */ -+#define CRYPTO_FLAG_SOFTWARE 0x02000000 /* software implementation */ -+ -+/* NB: deprecated */ -+struct session_op { -+ u_int32_t cipher; /* ie. CRYPTO_DES_CBC */ -+ u_int32_t mac; /* ie. CRYPTO_MD5_HMAC */ -+ -+ u_int32_t keylen; /* cipher key */ -+ caddr_t key; -+ int mackeylen; /* mac key */ -+ caddr_t mackey; -+ -+ u_int32_t ses; /* returns: session # */ -+}; -+ -+struct session2_op { -+ u_int32_t cipher; /* ie. CRYPTO_DES_CBC */ -+ u_int32_t mac; /* ie. CRYPTO_MD5_HMAC */ -+ -+ u_int32_t keylen; /* cipher key */ -+ caddr_t key; -+ int mackeylen; /* mac key */ -+ caddr_t mackey; -+ -+ u_int32_t ses; /* returns: session # */ -+ int crid; /* driver id + flags (rw) */ -+ int pad[4]; /* for future expansion */ -+}; -+ -+struct crypt_op { -+ u_int32_t ses; -+ u_int16_t op; /* i.e. COP_ENCRYPT */ -+#define COP_NONE 0 -+#define COP_ENCRYPT 1 -+#define COP_DECRYPT 2 -+ u_int16_t flags; -+#define COP_F_BATCH 0x0008 /* Batch op if possible */ -+ u_int len; -+ caddr_t src, dst; /* become iov[] inside kernel */ -+ caddr_t mac; /* must be big enough for chosen MAC */ -+ caddr_t iv; -+}; -+ -+/* -+ * Parameters for looking up a crypto driver/device by -+ * device name or by id. The latter are returned for -+ * created sessions (crid) and completed key operations. -+ */ -+struct crypt_find_op { -+ int crid; /* driver id + flags */ -+ char name[32]; /* device/driver name */ -+}; -+ -+/* bignum parameter, in packed bytes, ... */ -+struct crparam { -+ caddr_t crp_p; -+ u_int crp_nbits; -+}; -+ -+#define CRK_MAXPARAM 8 -+ -+struct crypt_kop { -+ u_int crk_op; /* ie. CRK_MOD_EXP or other */ -+ u_int crk_status; /* return status */ -+ u_short crk_iparams; /* # of input parameters */ -+ u_short crk_oparams; /* # of output parameters */ -+ u_int crk_crid; /* NB: only used by CIOCKEY2 (rw) */ -+ struct crparam crk_param[CRK_MAXPARAM]; -+}; -+#define CRK_ALGORITM_MIN 0 -+#define CRK_MOD_EXP 0 -+#define CRK_MOD_EXP_CRT 1 -+#define CRK_DSA_SIGN 2 -+#define CRK_DSA_VERIFY 3 -+#define CRK_DH_COMPUTE_KEY 4 -+#define CRK_ALGORITHM_MAX 4 /* Keep updated - see below */ -+ -+#define CRF_MOD_EXP (1 << CRK_MOD_EXP) -+#define CRF_MOD_EXP_CRT (1 << CRK_MOD_EXP_CRT) -+#define CRF_DSA_SIGN (1 << CRK_DSA_SIGN) -+#define CRF_DSA_VERIFY (1 << CRK_DSA_VERIFY) -+#define CRF_DH_COMPUTE_KEY (1 << CRK_DH_COMPUTE_KEY) -+ -+/* -+ * done against open of /dev/crypto, to get a cloned descriptor. -+ * Please use F_SETFD against the cloned descriptor. -+ */ -+#define CRIOGET _IOWR('c', 100, u_int32_t) -+#define CRIOASYMFEAT CIOCASYMFEAT -+#define CRIOFINDDEV CIOCFINDDEV -+ -+/* the following are done against the cloned descriptor */ -+#define CIOCGSESSION _IOWR('c', 101, struct session_op) -+#define CIOCFSESSION _IOW('c', 102, u_int32_t) -+#define CIOCCRYPT _IOWR('c', 103, struct crypt_op) -+#define CIOCKEY _IOWR('c', 104, struct crypt_kop) -+#define CIOCASYMFEAT _IOR('c', 105, u_int32_t) -+#define CIOCGSESSION2 _IOWR('c', 106, struct session2_op) -+#define CIOCKEY2 _IOWR('c', 107, struct crypt_kop) -+#define CIOCFINDDEV _IOWR('c', 108, struct crypt_find_op) -+ -+struct cryptotstat { -+ struct timespec acc; /* total accumulated time */ -+ struct timespec min; /* min time */ -+ struct timespec max; /* max time */ -+ u_int32_t count; /* number of observations */ -+}; -+ -+struct cryptostats { -+ u_int32_t cs_ops; /* symmetric crypto ops submitted */ -+ u_int32_t cs_errs; /* symmetric crypto ops that failed */ -+ u_int32_t cs_kops; /* asymetric/key ops submitted */ -+ u_int32_t cs_kerrs; /* asymetric/key ops that failed */ -+ u_int32_t cs_intrs; /* crypto swi thread activations */ -+ u_int32_t cs_rets; /* crypto return thread activations */ -+ u_int32_t cs_blocks; /* symmetric op driver block */ -+ u_int32_t cs_kblocks; /* symmetric op driver block */ -+ /* -+ * When CRYPTO_TIMING is defined at compile time and the -+ * sysctl debug.crypto is set to 1, the crypto system will -+ * accumulate statistics about how long it takes to process -+ * crypto requests at various points during processing. -+ */ -+ struct cryptotstat cs_invoke; /* crypto_dipsatch -> crypto_invoke */ -+ struct cryptotstat cs_done; /* crypto_invoke -> crypto_done */ -+ struct cryptotstat cs_cb; /* crypto_done -> callback */ -+ struct cryptotstat cs_finis; /* callback -> callback return */ -+ -+ u_int32_t cs_drops; /* crypto ops dropped due to congestion */ -+}; -+ -+#ifdef __KERNEL__ -+ -+/* Standard initialization structure beginning */ -+struct cryptoini { -+ int cri_alg; /* Algorithm to use */ -+ int cri_klen; /* Key length, in bits */ -+ int cri_mlen; /* Number of bytes we want from the -+ entire hash. 0 means all. */ -+ caddr_t cri_key; /* key to use */ -+ u_int8_t cri_iv[EALG_MAX_BLOCK_LEN]; /* IV to use */ -+ struct cryptoini *cri_next; -+}; -+ -+/* Describe boundaries of a single crypto operation */ -+struct cryptodesc { -+ int crd_skip; /* How many bytes to ignore from start */ -+ int crd_len; /* How many bytes to process */ -+ int crd_inject; /* Where to inject results, if applicable */ -+ int crd_flags; -+ -+#define CRD_F_ENCRYPT 0x01 /* Set when doing encryption */ -+#define CRD_F_IV_PRESENT 0x02 /* When encrypting, IV is already in -+ place, so don't copy. */ -+#define CRD_F_IV_EXPLICIT 0x04 /* IV explicitly provided */ -+#define CRD_F_DSA_SHA_NEEDED 0x08 /* Compute SHA-1 of buffer for DSA */ -+#define CRD_F_KEY_EXPLICIT 0x10 /* Key explicitly provided */ -+#define CRD_F_COMP 0x0f /* Set when doing compression */ -+ -+ struct cryptoini CRD_INI; /* Initialization/context data */ -+#define crd_iv CRD_INI.cri_iv -+#define crd_key CRD_INI.cri_key -+#define crd_alg CRD_INI.cri_alg -+#define crd_klen CRD_INI.cri_klen -+#define crd_mlen CRD_INI.cri_mlen -+ -+ struct cryptodesc *crd_next; -+}; -+ -+/* Structure describing complete operation */ -+struct cryptop { -+ struct list_head crp_next; -+ wait_queue_head_t crp_waitq; -+ -+ u_int64_t crp_sid; /* Session ID */ -+ int crp_ilen; /* Input data total length */ -+ int crp_olen; /* Result total length */ -+ -+ int crp_etype; /* -+ * Error type (zero means no error). -+ * All error codes except EAGAIN -+ * indicate possible data corruption (as in, -+ * the data have been touched). On all -+ * errors, the crp_sid may have changed -+ * (reset to a new one), so the caller -+ * should always check and use the new -+ * value on future requests. -+ */ -+ int crp_flags; -+ -+#define CRYPTO_F_SKBUF 0x0001 /* Input/output are skbuf chains */ -+#define CRYPTO_F_IOV 0x0002 /* Input/output are uio */ -+#define CRYPTO_F_REL 0x0004 /* Must return data in same place */ -+#define CRYPTO_F_BATCH 0x0008 /* Batch op if possible */ -+#define CRYPTO_F_CBIMM 0x0010 /* Do callback immediately */ -+#define CRYPTO_F_DONE 0x0020 /* Operation completed */ -+#define CRYPTO_F_CBIFSYNC 0x0040 /* Do CBIMM if op is synchronous */ -+ -+ caddr_t crp_buf; /* Data to be processed */ -+ caddr_t crp_opaque; /* Opaque pointer, passed along */ -+ struct cryptodesc *crp_desc; /* Linked list of processing descriptors */ -+ -+ int (*crp_callback)(struct cryptop *); /* Callback function */ -+}; -+ -+#define CRYPTO_BUF_CONTIG 0x0 -+#define CRYPTO_BUF_IOV 0x1 -+#define CRYPTO_BUF_SKBUF 0x2 -+ -+#define CRYPTO_OP_DECRYPT 0x0 -+#define CRYPTO_OP_ENCRYPT 0x1 -+ -+/* -+ * Hints passed to process methods. -+ */ -+#define CRYPTO_HINT_MORE 0x1 /* more ops coming shortly */ -+ -+struct cryptkop { -+ struct list_head krp_next; -+ wait_queue_head_t krp_waitq; -+ -+ int krp_flags; -+#define CRYPTO_KF_DONE 0x0001 /* Operation completed */ -+#define CRYPTO_KF_CBIMM 0x0002 /* Do callback immediately */ -+ -+ u_int krp_op; /* ie. CRK_MOD_EXP or other */ -+ u_int krp_status; /* return status */ -+ u_short krp_iparams; /* # of input parameters */ -+ u_short krp_oparams; /* # of output parameters */ -+ u_int krp_crid; /* desired device, etc. */ -+ u_int32_t krp_hid; -+ struct crparam krp_param[CRK_MAXPARAM]; /* kvm */ -+ int (*krp_callback)(struct cryptkop *); -+}; -+ -+#include -+ -+/* -+ * Session ids are 64 bits. The lower 32 bits contain a "local id" which -+ * is a driver-private session identifier. The upper 32 bits contain a -+ * "hardware id" used by the core crypto code to identify the driver and -+ * a copy of the driver's capabilities that can be used by client code to -+ * optimize operation. -+ */ -+#define CRYPTO_SESID2HID(_sid) (((_sid) >> 32) & 0x00ffffff) -+#define CRYPTO_SESID2CAPS(_sid) (((_sid) >> 32) & 0xff000000) -+#define CRYPTO_SESID2LID(_sid) (((u_int32_t) (_sid)) & 0xffffffff) -+ -+extern int crypto_newsession(u_int64_t *sid, struct cryptoini *cri, int hard); -+extern int crypto_freesession(u_int64_t sid); -+#define CRYPTOCAP_F_HARDWARE CRYPTO_FLAG_HARDWARE -+#define CRYPTOCAP_F_SOFTWARE CRYPTO_FLAG_SOFTWARE -+#define CRYPTOCAP_F_SYNC 0x04000000 /* operates synchronously */ -+extern int32_t crypto_get_driverid(device_t dev, int flags); -+extern int crypto_find_driver(const char *); -+extern device_t crypto_find_device_byhid(int hid); -+extern int crypto_getcaps(int hid); -+extern int crypto_register(u_int32_t driverid, int alg, u_int16_t maxoplen, -+ u_int32_t flags); -+extern int crypto_kregister(u_int32_t, int, u_int32_t); -+extern int crypto_unregister(u_int32_t driverid, int alg); -+extern int crypto_unregister_all(u_int32_t driverid); -+extern int crypto_dispatch(struct cryptop *crp); -+extern int crypto_kdispatch(struct cryptkop *); -+#define CRYPTO_SYMQ 0x1 -+#define CRYPTO_ASYMQ 0x2 -+extern int crypto_unblock(u_int32_t, int); -+extern void crypto_done(struct cryptop *crp); -+extern void crypto_kdone(struct cryptkop *); -+extern int crypto_getfeat(int *); -+ -+extern void crypto_freereq(struct cryptop *crp); -+extern struct cryptop *crypto_getreq(int num); -+ -+extern int crypto_usercrypto; /* userland may do crypto requests */ -+extern int crypto_userasymcrypto; /* userland may do asym crypto reqs */ -+extern int crypto_devallowsoft; /* only use hardware crypto */ -+ -+/* -+ * random number support, crypto_unregister_all will unregister -+ */ -+extern int crypto_rregister(u_int32_t driverid, -+ int (*read_random)(void *arg, u_int32_t *buf, int len), void *arg); -+extern int crypto_runregister_all(u_int32_t driverid); -+ -+/* -+ * Crypto-related utility routines used mainly by drivers. -+ * -+ * XXX these don't really belong here; but for now they're -+ * kept apart from the rest of the system. -+ */ -+struct uio; -+extern void cuio_copydata(struct uio* uio, int off, int len, caddr_t cp); -+extern void cuio_copyback(struct uio* uio, int off, int len, caddr_t cp); -+extern struct iovec *cuio_getptr(struct uio *uio, int loc, int *off); -+ -+extern void crypto_copyback(int flags, caddr_t buf, int off, int size, -+ caddr_t in); -+extern void crypto_copydata(int flags, caddr_t buf, int off, int size, -+ caddr_t out); -+extern int crypto_apply(int flags, caddr_t buf, int off, int len, -+ int (*f)(void *, void *, u_int), void *arg); -+ -+#endif /* __KERNEL__ */ -+#endif /* _CRYPTO_CRYPTO_H_ */ -diff -Nur linux-3.0.4.orig/crypto/ocf/cryptosoft.c linux-3.0.4/crypto/ocf/cryptosoft.c ---- linux-3.0.4.orig/crypto/ocf/cryptosoft.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/cryptosoft.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,1320 @@ -+/* -+ * An OCF module that uses the linux kernel cryptoapi, based on the -+ * original cryptosoft for BSD by Angelos D. Keromytis (angelos@cis.upenn.edu) -+ * but is mostly unrecognisable, -+ * -+ * Written by David McCullough -+ * Copyright (C) 2004-2011 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * ALTERNATIVELY, provided that this notice is retained in full, this product -+ * may be distributed under the terms of the GNU General Public License (GPL), -+ * in which case the provisions of the GPL apply INSTEAD OF those given above. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ * --------------------------------------------------------------------------- -+ */ -+ -+#include -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,10) -+#include -+#endif -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29) -+#include -+#endif -+ -+#include -+#include -+ -+struct { -+ softc_device_decl sc_dev; -+} swcr_softc; -+ -+#define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK) -+ -+#define SW_TYPE_CIPHER 0x01 -+#define SW_TYPE_HMAC 0x02 -+#define SW_TYPE_HASH 0x04 -+#define SW_TYPE_COMP 0x08 -+#define SW_TYPE_BLKCIPHER 0x10 -+#define SW_TYPE_ALG_MASK 0x1f -+ -+#define SW_TYPE_ASYNC 0x8000 -+ -+#define SW_TYPE_INUSE 0x10000000 -+ -+/* We change some of the above if we have an async interface */ -+ -+#define SW_TYPE_ALG_AMASK (SW_TYPE_ALG_MASK | SW_TYPE_ASYNC) -+ -+#define SW_TYPE_ABLKCIPHER (SW_TYPE_BLKCIPHER | SW_TYPE_ASYNC) -+#define SW_TYPE_AHASH (SW_TYPE_HASH | SW_TYPE_ASYNC) -+#define SW_TYPE_AHMAC (SW_TYPE_HMAC | SW_TYPE_ASYNC) -+ -+#define SCATTERLIST_MAX 16 -+ -+struct swcr_data { -+ struct work_struct workq; -+ int sw_type; -+ int sw_alg; -+ struct crypto_tfm *sw_tfm; -+ spinlock_t sw_tfm_lock; -+ union { -+ struct { -+ char *sw_key; -+ int sw_klen; -+ int sw_mlen; -+ } hmac; -+ void *sw_comp_buf; -+ } u; -+ struct swcr_data *sw_next; -+}; -+ -+struct swcr_req { -+ struct swcr_data *sw_head; -+ struct swcr_data *sw; -+ struct cryptop *crp; -+ struct cryptodesc *crd; -+ struct scatterlist sg[SCATTERLIST_MAX]; -+ unsigned char iv[EALG_MAX_BLOCK_LEN]; -+ char result[HASH_MAX_LEN]; -+ void *crypto_req; -+}; -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) -+static kmem_cache_t *swcr_req_cache; -+#else -+static struct kmem_cache *swcr_req_cache; -+#endif -+ -+#ifndef CRYPTO_TFM_MODE_CBC -+/* -+ * As of linux-2.6.21 this is no longer defined, and presumably no longer -+ * needed to be passed into the crypto core code. -+ */ -+#define CRYPTO_TFM_MODE_CBC 0 -+#define CRYPTO_TFM_MODE_ECB 0 -+#endif -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) -+ /* -+ * Linux 2.6.19 introduced a new Crypto API, setup macro's to convert new -+ * API into old API. -+ */ -+ -+ /* Symmetric/Block Cipher */ -+ struct blkcipher_desc -+ { -+ struct crypto_tfm *tfm; -+ void *info; -+ }; -+ #define ecb(X) #X , CRYPTO_TFM_MODE_ECB -+ #define cbc(X) #X , CRYPTO_TFM_MODE_CBC -+ #define crypto_has_blkcipher(X, Y, Z) crypto_alg_available(X, 0) -+ #define crypto_blkcipher_cast(X) X -+ #define crypto_blkcipher_tfm(X) X -+ #define crypto_alloc_blkcipher(X, Y, Z) crypto_alloc_tfm(X, mode) -+ #define crypto_blkcipher_ivsize(X) crypto_tfm_alg_ivsize(X) -+ #define crypto_blkcipher_blocksize(X) crypto_tfm_alg_blocksize(X) -+ #define crypto_blkcipher_setkey(X, Y, Z) crypto_cipher_setkey(X, Y, Z) -+ #define crypto_blkcipher_encrypt_iv(W, X, Y, Z) \ -+ crypto_cipher_encrypt_iv((W)->tfm, X, Y, Z, (u8 *)((W)->info)) -+ #define crypto_blkcipher_decrypt_iv(W, X, Y, Z) \ -+ crypto_cipher_decrypt_iv((W)->tfm, X, Y, Z, (u8 *)((W)->info)) -+ #define crypto_blkcipher_set_flags(x, y) /* nop */ -+ #define crypto_free_blkcipher(x) crypto_free_tfm(x) -+ #define crypto_free_comp crypto_free_tfm -+ #define crypto_free_hash crypto_free_tfm -+ -+ /* Hash/HMAC/Digest */ -+ struct hash_desc -+ { -+ struct crypto_tfm *tfm; -+ }; -+ #define hmac(X) #X , 0 -+ #define crypto_has_hash(X, Y, Z) crypto_alg_available(X, 0) -+ #define crypto_hash_cast(X) X -+ #define crypto_hash_tfm(X) X -+ #define crypto_alloc_hash(X, Y, Z) crypto_alloc_tfm(X, mode) -+ #define crypto_hash_digestsize(X) crypto_tfm_alg_digestsize(X) -+ #define crypto_hash_digest(W, X, Y, Z) \ -+ crypto_digest_digest((W)->tfm, X, sg_num, Z) -+ -+ /* Asymmetric Cipher */ -+ #define crypto_has_cipher(X, Y, Z) crypto_alg_available(X, 0) -+ -+ /* Compression */ -+ #define crypto_has_comp(X, Y, Z) crypto_alg_available(X, 0) -+ #define crypto_comp_tfm(X) X -+ #define crypto_comp_cast(X) X -+ #define crypto_alloc_comp(X, Y, Z) crypto_alloc_tfm(X, mode) -+ #define plain(X) #X , 0 -+#else -+ #define ecb(X) "ecb(" #X ")" , 0 -+ #define cbc(X) "cbc(" #X ")" , 0 -+ #define hmac(X) "hmac(" #X ")" , 0 -+ #define plain(X) #X , 0 -+#endif /* if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) */ -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22) -+/* no ablkcipher in older kernels */ -+#define crypto_alloc_ablkcipher(a,b,c) (NULL) -+#define crypto_ablkcipher_tfm(x) ((struct crypto_tfm *)(x)) -+#define crypto_ablkcipher_set_flags(a, b) /* nop */ -+#define crypto_ablkcipher_setkey(x, y, z) (-EINVAL) -+#define crypto_has_ablkcipher(a,b,c) (0) -+#else -+#define HAVE_ABLKCIPHER -+#endif -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,32) -+/* no ahash in older kernels */ -+#define crypto_ahash_tfm(x) ((struct crypto_tfm *)(x)) -+#define crypto_alloc_ahash(a,b,c) (NULL) -+#define crypto_ahash_digestsize(x) 0 -+#else -+#define HAVE_AHASH -+#endif -+ -+struct crypto_details { -+ char *alg_name; -+ int mode; -+ int sw_type; -+}; -+ -+static struct crypto_details crypto_details[] = { -+ [CRYPTO_DES_CBC] = { cbc(des), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_3DES_CBC] = { cbc(des3_ede), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_BLF_CBC] = { cbc(blowfish), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_CAST_CBC] = { cbc(cast5), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_SKIPJACK_CBC] = { cbc(skipjack), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_MD5_HMAC] = { hmac(md5), SW_TYPE_HMAC, }, -+ [CRYPTO_SHA1_HMAC] = { hmac(sha1), SW_TYPE_HMAC, }, -+ [CRYPTO_RIPEMD160_HMAC] = { hmac(ripemd160), SW_TYPE_HMAC, }, -+ [CRYPTO_MD5_KPDK] = { plain(md5-kpdk), SW_TYPE_HASH, }, -+ [CRYPTO_SHA1_KPDK] = { plain(sha1-kpdk), SW_TYPE_HASH, }, -+ [CRYPTO_AES_CBC] = { cbc(aes), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_ARC4] = { ecb(arc4), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_MD5] = { plain(md5), SW_TYPE_HASH, }, -+ [CRYPTO_SHA1] = { plain(sha1), SW_TYPE_HASH, }, -+ [CRYPTO_NULL_HMAC] = { hmac(digest_null), SW_TYPE_HMAC, }, -+ [CRYPTO_NULL_CBC] = { cbc(cipher_null), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_DEFLATE_COMP] = { plain(deflate), SW_TYPE_COMP, }, -+ [CRYPTO_SHA2_256_HMAC] = { hmac(sha256), SW_TYPE_HMAC, }, -+ [CRYPTO_SHA2_384_HMAC] = { hmac(sha384), SW_TYPE_HMAC, }, -+ [CRYPTO_SHA2_512_HMAC] = { hmac(sha512), SW_TYPE_HMAC, }, -+ [CRYPTO_CAMELLIA_CBC] = { cbc(camellia), SW_TYPE_BLKCIPHER, }, -+ [CRYPTO_SHA2_256] = { plain(sha256), SW_TYPE_HASH, }, -+ [CRYPTO_SHA2_384] = { plain(sha384), SW_TYPE_HASH, }, -+ [CRYPTO_SHA2_512] = { plain(sha512), SW_TYPE_HASH, }, -+ [CRYPTO_RIPEMD160] = { plain(ripemd160), SW_TYPE_HASH, }, -+}; -+ -+int32_t swcr_id = -1; -+module_param(swcr_id, int, 0444); -+MODULE_PARM_DESC(swcr_id, "Read-Only OCF ID for cryptosoft driver"); -+ -+int swcr_fail_if_compression_grows = 1; -+module_param(swcr_fail_if_compression_grows, int, 0644); -+MODULE_PARM_DESC(swcr_fail_if_compression_grows, -+ "Treat compression that results in more data as a failure"); -+ -+int swcr_no_ahash = 0; -+module_param(swcr_no_ahash, int, 0644); -+MODULE_PARM_DESC(swcr_no_ahash, -+ "Do not use async hash/hmac even if available"); -+ -+int swcr_no_ablk = 0; -+module_param(swcr_no_ablk, int, 0644); -+MODULE_PARM_DESC(swcr_no_ablk, -+ "Do not use async blk ciphers even if available"); -+ -+static struct swcr_data **swcr_sessions = NULL; -+static u_int32_t swcr_sesnum = 0; -+ -+static int swcr_process(device_t, struct cryptop *, int); -+static int swcr_newsession(device_t, u_int32_t *, struct cryptoini *); -+static int swcr_freesession(device_t, u_int64_t); -+ -+static device_method_t swcr_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, swcr_newsession), -+ DEVMETHOD(cryptodev_freesession,swcr_freesession), -+ DEVMETHOD(cryptodev_process, swcr_process), -+}; -+ -+#define debug swcr_debug -+int swcr_debug = 0; -+module_param(swcr_debug, int, 0644); -+MODULE_PARM_DESC(swcr_debug, "Enable debug"); -+ -+static void swcr_process_req(struct swcr_req *req); -+ -+/* -+ * somethings just need to be run with user context no matter whether -+ * the kernel compression libs use vmalloc/vfree for example. -+ */ -+ -+typedef struct { -+ struct work_struct wq; -+ void (*func)(void *arg); -+ void *arg; -+} execute_later_t; -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void -+doing_it_now(struct work_struct *wq) -+{ -+ execute_later_t *w = container_of(wq, execute_later_t, wq); -+ (w->func)(w->arg); -+ kfree(w); -+} -+#else -+static void -+doing_it_now(void *arg) -+{ -+ execute_later_t *w = (execute_later_t *) arg; -+ (w->func)(w->arg); -+ kfree(w); -+} -+#endif -+ -+static void -+execute_later(void (fn)(void *), void *arg) -+{ -+ execute_later_t *w; -+ -+ w = (execute_later_t *) kmalloc(sizeof(execute_later_t), SLAB_ATOMIC); -+ if (w) { -+ memset(w, '\0', sizeof(w)); -+ w->func = fn; -+ w->arg = arg; -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ INIT_WORK(&w->wq, doing_it_now); -+#else -+ INIT_WORK(&w->wq, doing_it_now, w); -+#endif -+ schedule_work(&w->wq); -+ } -+} -+ -+/* -+ * Generate a new software session. -+ */ -+static int -+swcr_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) -+{ -+ struct swcr_data **swd; -+ u_int32_t i; -+ int error; -+ char *algo; -+ int mode; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid == NULL || cri == NULL) { -+ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ if (swcr_sessions) { -+ for (i = 1; i < swcr_sesnum; i++) -+ if (swcr_sessions[i] == NULL) -+ break; -+ } else -+ i = 1; /* NB: to silence compiler warning */ -+ -+ if (swcr_sessions == NULL || i == swcr_sesnum) { -+ if (swcr_sessions == NULL) { -+ i = 1; /* We leave swcr_sessions[0] empty */ -+ swcr_sesnum = CRYPTO_SW_SESSIONS; -+ } else -+ swcr_sesnum *= 2; -+ -+ swd = kmalloc(swcr_sesnum * sizeof(struct swcr_data *), SLAB_ATOMIC); -+ if (swd == NULL) { -+ /* Reset session number */ -+ if (swcr_sesnum == CRYPTO_SW_SESSIONS) -+ swcr_sesnum = 0; -+ else -+ swcr_sesnum /= 2; -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memset(swd, 0, swcr_sesnum * sizeof(struct swcr_data *)); -+ -+ /* Copy existing sessions */ -+ if (swcr_sessions) { -+ memcpy(swd, swcr_sessions, -+ (swcr_sesnum / 2) * sizeof(struct swcr_data *)); -+ kfree(swcr_sessions); -+ } -+ -+ swcr_sessions = swd; -+ } -+ -+ swd = &swcr_sessions[i]; -+ *sid = i; -+ -+ while (cri) { -+ *swd = (struct swcr_data *) kmalloc(sizeof(struct swcr_data), -+ SLAB_ATOMIC); -+ if (*swd == NULL) { -+ swcr_freesession(NULL, i); -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memset(*swd, 0, sizeof(struct swcr_data)); -+ -+ if (cri->cri_alg < 0 || -+ cri->cri_alg>=sizeof(crypto_details)/sizeof(crypto_details[0])){ -+ printk("cryptosoft: Unknown algorithm 0x%x\n", cri->cri_alg); -+ swcr_freesession(NULL, i); -+ return EINVAL; -+ } -+ -+ algo = crypto_details[cri->cri_alg].alg_name; -+ if (!algo || !*algo) { -+ printk("cryptosoft: Unsupported algorithm 0x%x\n", cri->cri_alg); -+ swcr_freesession(NULL, i); -+ return EINVAL; -+ } -+ -+ mode = crypto_details[cri->cri_alg].mode; -+ (*swd)->sw_type = crypto_details[cri->cri_alg].sw_type; -+ (*swd)->sw_alg = cri->cri_alg; -+ -+ spin_lock_init(&(*swd)->sw_tfm_lock); -+ -+ /* Algorithm specific configuration */ -+ switch (cri->cri_alg) { -+ case CRYPTO_NULL_CBC: -+ cri->cri_klen = 0; /* make it work with crypto API */ -+ break; -+ default: -+ break; -+ } -+ -+ if ((*swd)->sw_type & SW_TYPE_BLKCIPHER) { -+ dprintk("%s crypto_alloc_*blkcipher(%s, 0x%x)\n", __FUNCTION__, -+ algo, mode); -+ -+ /* try async first */ -+ (*swd)->sw_tfm = swcr_no_ablk ? NULL : -+ crypto_ablkcipher_tfm(crypto_alloc_ablkcipher(algo, 0, 0)); -+ if ((*swd)->sw_tfm && !IS_ERR((*swd)->sw_tfm)) { -+ dprintk("%s %s cipher is async\n", __FUNCTION__, algo); -+ (*swd)->sw_type |= SW_TYPE_ASYNC; -+ } else { -+ (*swd)->sw_tfm = crypto_blkcipher_tfm( -+ crypto_alloc_blkcipher(algo, 0, CRYPTO_ALG_ASYNC)); -+ if ((*swd)->sw_tfm && !IS_ERR((*swd)->sw_tfm)) -+ dprintk("%s %s cipher is sync\n", __FUNCTION__, algo); -+ } -+ if (!(*swd)->sw_tfm || IS_ERR((*swd)->sw_tfm)) { -+ int err; -+ dprintk("cryptosoft: crypto_alloc_blkcipher failed(%s, 0x%x)\n", -+ algo,mode); -+ err = IS_ERR((*swd)->sw_tfm) ? -(PTR_ERR((*swd)->sw_tfm)) : EINVAL; -+ (*swd)->sw_tfm = NULL; /* ensure NULL */ -+ swcr_freesession(NULL, i); -+ return err; -+ } -+ -+ if (debug) { -+ dprintk("%s key:cri->cri_klen=%d,(cri->cri_klen + 7)/8=%d", -+ __FUNCTION__, cri->cri_klen, (cri->cri_klen + 7) / 8); -+ for (i = 0; i < (cri->cri_klen + 7) / 8; i++) -+ dprintk("%s0x%x", (i % 8) ? " " : "\n ", -+ cri->cri_key[i] & 0xff); -+ dprintk("\n"); -+ } -+ if ((*swd)->sw_type & SW_TYPE_ASYNC) { -+ /* OCF doesn't enforce keys */ -+ crypto_ablkcipher_set_flags( -+ __crypto_ablkcipher_cast((*swd)->sw_tfm), -+ CRYPTO_TFM_REQ_WEAK_KEY); -+ error = crypto_ablkcipher_setkey( -+ __crypto_ablkcipher_cast((*swd)->sw_tfm), -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ } else { -+ /* OCF doesn't enforce keys */ -+ crypto_blkcipher_set_flags( -+ crypto_blkcipher_cast((*swd)->sw_tfm), -+ CRYPTO_TFM_REQ_WEAK_KEY); -+ error = crypto_blkcipher_setkey( -+ crypto_blkcipher_cast((*swd)->sw_tfm), -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ } -+ if (error) { -+ printk("cryptosoft: setkey failed %d (crt_flags=0x%x)\n", error, -+ (*swd)->sw_tfm->crt_flags); -+ swcr_freesession(NULL, i); -+ return error; -+ } -+ } else if ((*swd)->sw_type & (SW_TYPE_HMAC | SW_TYPE_HASH)) { -+ dprintk("%s crypto_alloc_*hash(%s, 0x%x)\n", __FUNCTION__, -+ algo, mode); -+ -+ /* try async first */ -+ (*swd)->sw_tfm = swcr_no_ahash ? NULL : -+ crypto_ahash_tfm(crypto_alloc_ahash(algo, 0, 0)); -+ if ((*swd)->sw_tfm) { -+ dprintk("%s %s hash is async\n", __FUNCTION__, algo); -+ (*swd)->sw_type |= SW_TYPE_ASYNC; -+ } else { -+ dprintk("%s %s hash is sync\n", __FUNCTION__, algo); -+ (*swd)->sw_tfm = crypto_hash_tfm( -+ crypto_alloc_hash(algo, 0, CRYPTO_ALG_ASYNC)); -+ } -+ -+ if (!(*swd)->sw_tfm) { -+ dprintk("cryptosoft: crypto_alloc_hash failed(%s,0x%x)\n", -+ algo, mode); -+ swcr_freesession(NULL, i); -+ return EINVAL; -+ } -+ -+ (*swd)->u.hmac.sw_klen = (cri->cri_klen + 7) / 8; -+ (*swd)->u.hmac.sw_key = (char *)kmalloc((*swd)->u.hmac.sw_klen, -+ SLAB_ATOMIC); -+ if ((*swd)->u.hmac.sw_key == NULL) { -+ swcr_freesession(NULL, i); -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memcpy((*swd)->u.hmac.sw_key, cri->cri_key, (*swd)->u.hmac.sw_klen); -+ if (cri->cri_mlen) { -+ (*swd)->u.hmac.sw_mlen = cri->cri_mlen; -+ } else if ((*swd)->sw_type & SW_TYPE_ASYNC) { -+ (*swd)->u.hmac.sw_mlen = crypto_ahash_digestsize( -+ __crypto_ahash_cast((*swd)->sw_tfm)); -+ } else { -+ (*swd)->u.hmac.sw_mlen = crypto_hash_digestsize( -+ crypto_hash_cast((*swd)->sw_tfm)); -+ } -+ } else if ((*swd)->sw_type & SW_TYPE_COMP) { -+ (*swd)->sw_tfm = crypto_comp_tfm( -+ crypto_alloc_comp(algo, 0, CRYPTO_ALG_ASYNC)); -+ if (!(*swd)->sw_tfm) { -+ dprintk("cryptosoft: crypto_alloc_comp failed(%s,0x%x)\n", -+ algo, mode); -+ swcr_freesession(NULL, i); -+ return EINVAL; -+ } -+ (*swd)->u.sw_comp_buf = kmalloc(CRYPTO_MAX_DATA_LEN, SLAB_ATOMIC); -+ if ((*swd)->u.sw_comp_buf == NULL) { -+ swcr_freesession(NULL, i); -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ } else { -+ printk("cryptosoft: Unhandled sw_type %d\n", (*swd)->sw_type); -+ swcr_freesession(NULL, i); -+ return EINVAL; -+ } -+ -+ cri = cri->cri_next; -+ swd = &((*swd)->sw_next); -+ } -+ return 0; -+} -+ -+/* -+ * Free a session. -+ */ -+static int -+swcr_freesession(device_t dev, u_int64_t tid) -+{ -+ struct swcr_data *swd; -+ u_int32_t sid = CRYPTO_SESID2LID(tid); -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid > swcr_sesnum || swcr_sessions == NULL || -+ swcr_sessions[sid] == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return(EINVAL); -+ } -+ -+ /* Silently accept and return */ -+ if (sid == 0) -+ return(0); -+ -+ while ((swd = swcr_sessions[sid]) != NULL) { -+ swcr_sessions[sid] = swd->sw_next; -+ if (swd->sw_tfm) { -+ switch (swd->sw_type & SW_TYPE_ALG_AMASK) { -+#ifdef HAVE_AHASH -+ case SW_TYPE_AHMAC: -+ case SW_TYPE_AHASH: -+ crypto_free_ahash(__crypto_ahash_cast(swd->sw_tfm)); -+ break; -+#endif -+#ifdef HAVE_ABLKCIPHER -+ case SW_TYPE_ABLKCIPHER: -+ crypto_free_ablkcipher(__crypto_ablkcipher_cast(swd->sw_tfm)); -+ break; -+#endif -+ case SW_TYPE_BLKCIPHER: -+ crypto_free_blkcipher(crypto_blkcipher_cast(swd->sw_tfm)); -+ break; -+ case SW_TYPE_HMAC: -+ case SW_TYPE_HASH: -+ crypto_free_hash(crypto_hash_cast(swd->sw_tfm)); -+ break; -+ case SW_TYPE_COMP: -+ if (in_interrupt()) -+ execute_later((void (*)(void *))crypto_free_comp, (void *)crypto_comp_cast(swd->sw_tfm)); -+ else -+ crypto_free_comp(crypto_comp_cast(swd->sw_tfm)); -+ break; -+ default: -+ crypto_free_tfm(swd->sw_tfm); -+ break; -+ } -+ swd->sw_tfm = NULL; -+ } -+ if (swd->sw_type & SW_TYPE_COMP) { -+ if (swd->u.sw_comp_buf) -+ kfree(swd->u.sw_comp_buf); -+ } else { -+ if (swd->u.hmac.sw_key) -+ kfree(swd->u.hmac.sw_key); -+ } -+ kfree(swd); -+ } -+ return 0; -+} -+ -+static void swcr_process_req_complete(struct swcr_req *req) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (req->sw->sw_type & SW_TYPE_INUSE) { -+ unsigned long flags; -+ spin_lock_irqsave(&req->sw->sw_tfm_lock, flags); -+ req->sw->sw_type &= ~SW_TYPE_INUSE; -+ spin_unlock_irqrestore(&req->sw->sw_tfm_lock, flags); -+ } -+ -+ if (req->crp->crp_etype) -+ goto done; -+ -+ switch (req->sw->sw_type & SW_TYPE_ALG_AMASK) { -+#if defined(HAVE_AHASH) -+ case SW_TYPE_AHMAC: -+ case SW_TYPE_AHASH: -+ crypto_copyback(req->crp->crp_flags, req->crp->crp_buf, -+ req->crd->crd_inject, req->sw->u.hmac.sw_mlen, req->result); -+ ahash_request_free(req->crypto_req); -+ break; -+#endif -+#if defined(HAVE_ABLKCIPHER) -+ case SW_TYPE_ABLKCIPHER: -+ ablkcipher_request_free(req->crypto_req); -+ break; -+#endif -+ case SW_TYPE_CIPHER: -+ case SW_TYPE_HMAC: -+ case SW_TYPE_HASH: -+ case SW_TYPE_COMP: -+ case SW_TYPE_BLKCIPHER: -+ break; -+ default: -+ req->crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ req->crd = req->crd->crd_next; -+ if (req->crd) { -+ swcr_process_req(req); -+ return; -+ } -+ -+done: -+ dprintk("%s crypto_done %p\n", __FUNCTION__, req); -+ crypto_done(req->crp); -+ kmem_cache_free(swcr_req_cache, req); -+} -+ -+#if defined(HAVE_ABLKCIPHER) || defined(HAVE_AHASH) -+static void swcr_process_callback(struct crypto_async_request *creq, int err) -+{ -+ struct swcr_req *req = creq->data; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (err) { -+ if (err == -EINPROGRESS) -+ return; -+ dprintk("%s() fail %d\n", __FUNCTION__, -err); -+ req->crp->crp_etype = -err; -+ } -+ -+ swcr_process_req_complete(req); -+} -+#endif /* defined(HAVE_ABLKCIPHER) || defined(HAVE_AHASH) */ -+ -+ -+static void swcr_process_req(struct swcr_req *req) -+{ -+ struct swcr_data *sw; -+ struct cryptop *crp = req->crp; -+ struct cryptodesc *crd = req->crd; -+ struct sk_buff *skb = (struct sk_buff *) crp->crp_buf; -+ struct uio *uiop = (struct uio *) crp->crp_buf; -+ int sg_num, sg_len, skip; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ /* -+ * Find the crypto context. -+ * -+ * XXX Note that the logic here prevents us from having -+ * XXX the same algorithm multiple times in a session -+ * XXX (or rather, we can but it won't give us the right -+ * XXX results). To do that, we'd need some way of differentiating -+ * XXX between the various instances of an algorithm (so we can -+ * XXX locate the correct crypto context). -+ */ -+ for (sw = req->sw_head; sw && sw->sw_alg != crd->crd_alg; sw = sw->sw_next) -+ ; -+ -+ /* No such context ? */ -+ if (sw == NULL) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ goto done; -+ } -+ -+ /* -+ * for some types we need to ensure only one user as info is stored in -+ * the tfm during an operation that can get corrupted -+ */ -+ switch (sw->sw_type & SW_TYPE_ALG_AMASK) { -+#ifdef HAVE_AHASH -+ case SW_TYPE_AHMAC: -+ case SW_TYPE_AHASH: -+#endif -+ case SW_TYPE_HMAC: -+ case SW_TYPE_HASH: { -+ unsigned long flags; -+ spin_lock_irqsave(&sw->sw_tfm_lock, flags); -+ if (sw->sw_type & SW_TYPE_INUSE) { -+ spin_unlock_irqrestore(&sw->sw_tfm_lock, flags); -+ execute_later((void (*)(void *))swcr_process_req, (void *)req); -+ return; -+ } -+ sw->sw_type |= SW_TYPE_INUSE; -+ spin_unlock_irqrestore(&sw->sw_tfm_lock, flags); -+ } break; -+ } -+ -+ req->sw = sw; -+ skip = crd->crd_skip; -+ -+ /* -+ * setup the SG list skip from the start of the buffer -+ */ -+ memset(req->sg, 0, sizeof(req->sg)); -+ sg_init_table(req->sg, SCATTERLIST_MAX); -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ int i, len; -+ -+ sg_num = 0; -+ sg_len = 0; -+ -+ if (skip < skb_headlen(skb)) { -+ len = skb_headlen(skb) - skip; -+ if (len + sg_len > crd->crd_len) -+ len = crd->crd_len - sg_len; -+ sg_set_page(&req->sg[sg_num], -+ virt_to_page(skb->data + skip), len, -+ offset_in_page(skb->data + skip)); -+ sg_len += len; -+ sg_num++; -+ skip = 0; -+ } else -+ skip -= skb_headlen(skb); -+ -+ for (i = 0; sg_len < crd->crd_len && -+ i < skb_shinfo(skb)->nr_frags && -+ sg_num < SCATTERLIST_MAX; i++) { -+ if (skip < skb_shinfo(skb)->frags[i].size) { -+ len = skb_shinfo(skb)->frags[i].size - skip; -+ if (len + sg_len > crd->crd_len) -+ len = crd->crd_len - sg_len; -+ sg_set_page(&req->sg[sg_num], -+ skb_shinfo(skb)->frags[i].page, -+ len, -+ skb_shinfo(skb)->frags[i].page_offset + skip); -+ sg_len += len; -+ sg_num++; -+ skip = 0; -+ } else -+ skip -= skb_shinfo(skb)->frags[i].size; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ int len; -+ -+ sg_len = 0; -+ for (sg_num = 0; sg_len < crd->crd_len && -+ sg_num < uiop->uio_iovcnt && -+ sg_num < SCATTERLIST_MAX; sg_num++) { -+ if (skip <= uiop->uio_iov[sg_num].iov_len) { -+ len = uiop->uio_iov[sg_num].iov_len - skip; -+ if (len + sg_len > crd->crd_len) -+ len = crd->crd_len - sg_len; -+ sg_set_page(&req->sg[sg_num], -+ virt_to_page(uiop->uio_iov[sg_num].iov_base+skip), -+ len, -+ offset_in_page(uiop->uio_iov[sg_num].iov_base+skip)); -+ sg_len += len; -+ skip = 0; -+ } else -+ skip -= uiop->uio_iov[sg_num].iov_len; -+ } -+ } else { -+ sg_len = (crp->crp_ilen - skip); -+ if (sg_len > crd->crd_len) -+ sg_len = crd->crd_len; -+ sg_set_page(&req->sg[0], virt_to_page(crp->crp_buf + skip), -+ sg_len, offset_in_page(crp->crp_buf + skip)); -+ sg_num = 1; -+ } -+ -+ switch (sw->sw_type & SW_TYPE_ALG_AMASK) { -+ -+#ifdef HAVE_AHASH -+ case SW_TYPE_AHMAC: -+ case SW_TYPE_AHASH: -+ { -+ int ret; -+ -+ /* check we have room for the result */ -+ if (crp->crp_ilen - crd->crd_inject < sw->u.hmac.sw_mlen) { -+ dprintk("cryptosoft: EINVAL crp_ilen=%d, len=%d, inject=%d " -+ "digestsize=%d\n", crp->crp_ilen, crd->crd_skip + sg_len, -+ crd->crd_inject, sw->u.hmac.sw_mlen); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ req->crypto_req = -+ ahash_request_alloc(__crypto_ahash_cast(sw->sw_tfm),GFP_ATOMIC); -+ if (!req->crypto_req) { -+ crp->crp_etype = ENOMEM; -+ dprintk("%s,%d: ENOMEM ahash_request_alloc", __FILE__, __LINE__); -+ goto done; -+ } -+ -+ ahash_request_set_callback(req->crypto_req, -+ CRYPTO_TFM_REQ_MAY_BACKLOG, swcr_process_callback, req); -+ -+ memset(req->result, 0, sizeof(req->result)); -+ -+ if (sw->sw_type & SW_TYPE_AHMAC) -+ crypto_ahash_setkey(__crypto_ahash_cast(sw->sw_tfm), -+ sw->u.hmac.sw_key, sw->u.hmac.sw_klen); -+ ahash_request_set_crypt(req->crypto_req, req->sg, req->result, sg_len); -+ ret = crypto_ahash_digest(req->crypto_req); -+ switch (ret) { -+ case -EINPROGRESS: -+ case -EBUSY: -+ return; -+ default: -+ case 0: -+ dprintk("hash OP %s %d\n", ret ? "failed" : "success", ret); -+ crp->crp_etype = ret; -+ goto done; -+ } -+ } break; -+#endif /* HAVE_AHASH */ -+ -+#ifdef HAVE_ABLKCIPHER -+ case SW_TYPE_ABLKCIPHER: { -+ int ret; -+ unsigned char *ivp = req->iv; -+ int ivsize = -+ crypto_ablkcipher_ivsize(__crypto_ablkcipher_cast(sw->sw_tfm)); -+ -+ if (sg_len < crypto_ablkcipher_blocksize( -+ __crypto_ablkcipher_cast(sw->sw_tfm))) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: EINVAL len %d < %d\n", __FILE__, __LINE__, -+ sg_len, crypto_ablkcipher_blocksize( -+ __crypto_ablkcipher_cast(sw->sw_tfm))); -+ goto done; -+ } -+ -+ if (ivsize > sizeof(req->iv)) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ goto done; -+ } -+ -+ req->crypto_req = ablkcipher_request_alloc( -+ __crypto_ablkcipher_cast(sw->sw_tfm), GFP_ATOMIC); -+ if (!req->crypto_req) { -+ crp->crp_etype = ENOMEM; -+ dprintk("%s,%d: ENOMEM ablkcipher_request_alloc", -+ __FILE__, __LINE__); -+ goto done; -+ } -+ -+ ablkcipher_request_set_callback(req->crypto_req, -+ CRYPTO_TFM_REQ_MAY_BACKLOG, swcr_process_callback, req); -+ -+ if (crd->crd_flags & CRD_F_KEY_EXPLICIT) { -+ int i, error; -+ -+ if (debug) { -+ dprintk("%s key:", __FUNCTION__); -+ for (i = 0; i < (crd->crd_klen + 7) / 8; i++) -+ dprintk("%s0x%x", (i % 8) ? " " : "\n ", -+ crd->crd_key[i] & 0xff); -+ dprintk("\n"); -+ } -+ /* OCF doesn't enforce keys */ -+ crypto_ablkcipher_set_flags(__crypto_ablkcipher_cast(sw->sw_tfm), -+ CRYPTO_TFM_REQ_WEAK_KEY); -+ error = crypto_ablkcipher_setkey( -+ __crypto_ablkcipher_cast(sw->sw_tfm), crd->crd_key, -+ (crd->crd_klen + 7) / 8); -+ if (error) { -+ dprintk("cryptosoft: setkey failed %d (crt_flags=0x%x)\n", -+ error, sw->sw_tfm->crt_flags); -+ crp->crp_etype = -error; -+ } -+ } -+ -+ if (crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ -+ -+ if (crd->crd_flags & CRD_F_IV_EXPLICIT) -+ ivp = crd->crd_iv; -+ else -+ get_random_bytes(ivp, ivsize); -+ /* -+ * do we have to copy the IV back to the buffer ? -+ */ -+ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, ivsize, (caddr_t)ivp); -+ } -+ ablkcipher_request_set_crypt(req->crypto_req, req->sg, req->sg, -+ sg_len, ivp); -+ ret = crypto_ablkcipher_encrypt(req->crypto_req); -+ -+ } else { /*decrypt */ -+ -+ if (crd->crd_flags & CRD_F_IV_EXPLICIT) -+ ivp = crd->crd_iv; -+ else -+ crypto_copydata(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, ivsize, (caddr_t)ivp); -+ ablkcipher_request_set_crypt(req->crypto_req, req->sg, req->sg, -+ sg_len, ivp); -+ ret = crypto_ablkcipher_decrypt(req->crypto_req); -+ } -+ -+ switch (ret) { -+ case -EINPROGRESS: -+ case -EBUSY: -+ return; -+ default: -+ case 0: -+ dprintk("crypto OP %s %d\n", ret ? "failed" : "success", ret); -+ crp->crp_etype = ret; -+ goto done; -+ } -+ } break; -+#endif /* HAVE_ABLKCIPHER */ -+ -+ case SW_TYPE_BLKCIPHER: { -+ unsigned char iv[EALG_MAX_BLOCK_LEN]; -+ unsigned char *ivp = iv; -+ struct blkcipher_desc desc; -+ int ivsize = crypto_blkcipher_ivsize(crypto_blkcipher_cast(sw->sw_tfm)); -+ -+ if (sg_len < crypto_blkcipher_blocksize( -+ crypto_blkcipher_cast(sw->sw_tfm))) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: EINVAL len %d < %d\n", __FILE__, __LINE__, -+ sg_len, crypto_blkcipher_blocksize( -+ crypto_blkcipher_cast(sw->sw_tfm))); -+ goto done; -+ } -+ -+ if (ivsize > sizeof(iv)) { -+ crp->crp_etype = EINVAL; -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ goto done; -+ } -+ -+ if (crd->crd_flags & CRD_F_KEY_EXPLICIT) { -+ int i, error; -+ -+ if (debug) { -+ dprintk("%s key:", __FUNCTION__); -+ for (i = 0; i < (crd->crd_klen + 7) / 8; i++) -+ dprintk("%s0x%x", (i % 8) ? " " : "\n ", -+ crd->crd_key[i] & 0xff); -+ dprintk("\n"); -+ } -+ /* OCF doesn't enforce keys */ -+ crypto_blkcipher_set_flags(crypto_blkcipher_cast(sw->sw_tfm), -+ CRYPTO_TFM_REQ_WEAK_KEY); -+ error = crypto_blkcipher_setkey( -+ crypto_blkcipher_cast(sw->sw_tfm), crd->crd_key, -+ (crd->crd_klen + 7) / 8); -+ if (error) { -+ dprintk("cryptosoft: setkey failed %d (crt_flags=0x%x)\n", -+ error, sw->sw_tfm->crt_flags); -+ crp->crp_etype = -error; -+ } -+ } -+ -+ memset(&desc, 0, sizeof(desc)); -+ desc.tfm = crypto_blkcipher_cast(sw->sw_tfm); -+ -+ if (crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ -+ -+ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { -+ ivp = crd->crd_iv; -+ } else { -+ get_random_bytes(ivp, ivsize); -+ } -+ /* -+ * do we have to copy the IV back to the buffer ? -+ */ -+ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, ivsize, (caddr_t)ivp); -+ } -+ desc.info = ivp; -+ crypto_blkcipher_encrypt_iv(&desc, req->sg, req->sg, sg_len); -+ -+ } else { /*decrypt */ -+ -+ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { -+ ivp = crd->crd_iv; -+ } else { -+ crypto_copydata(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, ivsize, (caddr_t)ivp); -+ } -+ desc.info = ivp; -+ crypto_blkcipher_decrypt_iv(&desc, req->sg, req->sg, sg_len); -+ } -+ } break; -+ -+ case SW_TYPE_HMAC: -+ case SW_TYPE_HASH: -+ { -+ char result[HASH_MAX_LEN]; -+ struct hash_desc desc; -+ -+ /* check we have room for the result */ -+ if (crp->crp_ilen - crd->crd_inject < sw->u.hmac.sw_mlen) { -+ dprintk("cryptosoft: EINVAL crp_ilen=%d, len=%d, inject=%d " -+ "digestsize=%d\n", crp->crp_ilen, crd->crd_skip + sg_len, -+ crd->crd_inject, sw->u.hmac.sw_mlen); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ memset(&desc, 0, sizeof(desc)); -+ desc.tfm = crypto_hash_cast(sw->sw_tfm); -+ -+ memset(result, 0, sizeof(result)); -+ -+ if (sw->sw_type & SW_TYPE_HMAC) { -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) -+ crypto_hmac(sw->sw_tfm, sw->u.hmac.sw_key, &sw->u.hmac.sw_klen, -+ req->sg, sg_num, result); -+#else -+ crypto_hash_setkey(desc.tfm, sw->u.hmac.sw_key, -+ sw->u.hmac.sw_klen); -+ crypto_hash_digest(&desc, req->sg, sg_len, result); -+#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) */ -+ -+ } else { /* SW_TYPE_HASH */ -+ crypto_hash_digest(&desc, req->sg, sg_len, result); -+ } -+ -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, sw->u.hmac.sw_mlen, result); -+ } -+ break; -+ -+ case SW_TYPE_COMP: { -+ void *ibuf = NULL; -+ void *obuf = sw->u.sw_comp_buf; -+ int ilen = sg_len, olen = CRYPTO_MAX_DATA_LEN; -+ int ret = 0; -+ -+ /* -+ * we need to use an additional copy if there is more than one -+ * input chunk since the kernel comp routines do not handle -+ * SG yet. Otherwise we just use the input buffer as is. -+ * Rather than allocate another buffer we just split the tmp -+ * buffer we already have. -+ * Perhaps we should just use zlib directly ? -+ */ -+ if (sg_num > 1) { -+ int blk; -+ -+ ibuf = obuf; -+ for (blk = 0; blk < sg_num; blk++) { -+ memcpy(obuf, sg_virt(&req->sg[blk]), -+ req->sg[blk].length); -+ obuf += req->sg[blk].length; -+ } -+ olen -= sg_len; -+ } else -+ ibuf = sg_virt(&req->sg[0]); -+ -+ if (crd->crd_flags & CRD_F_ENCRYPT) { /* compress */ -+ ret = crypto_comp_compress(crypto_comp_cast(sw->sw_tfm), -+ ibuf, ilen, obuf, &olen); -+ if (!ret && olen > crd->crd_len) { -+ dprintk("cryptosoft: ERANGE compress %d into %d\n", -+ crd->crd_len, olen); -+ if (swcr_fail_if_compression_grows) -+ ret = ERANGE; -+ } -+ } else { /* decompress */ -+ ret = crypto_comp_decompress(crypto_comp_cast(sw->sw_tfm), -+ ibuf, ilen, obuf, &olen); -+ if (!ret && (olen + crd->crd_inject) > crp->crp_olen) { -+ dprintk("cryptosoft: ETOOSMALL decompress %d into %d, " -+ "space for %d,at offset %d\n", -+ crd->crd_len, olen, crp->crp_olen, crd->crd_inject); -+ ret = ETOOSMALL; -+ } -+ } -+ if (ret) -+ dprintk("%s,%d: ret = %d\n", __FILE__, __LINE__, ret); -+ -+ /* -+ * on success copy result back, -+ * linux crpyto API returns -errno, we need to fix that -+ */ -+ crp->crp_etype = ret < 0 ? -ret : ret; -+ if (ret == 0) { -+ /* copy back the result and return it's size */ -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, olen, obuf); -+ crp->crp_olen = olen; -+ } -+ } break; -+ -+ default: -+ /* Unknown/unsupported algorithm */ -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+done: -+ swcr_process_req_complete(req); -+} -+ -+ -+/* -+ * Process a crypto request. -+ */ -+static int -+swcr_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ struct swcr_req *req = NULL; -+ u_int32_t lid; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ /* Sanity check */ -+ if (crp == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ crp->crp_etype = 0; -+ -+ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ lid = crp->crp_sid & 0xffffffff; -+ if (lid >= swcr_sesnum || lid == 0 || swcr_sessions == NULL || -+ swcr_sessions[lid] == NULL) { -+ crp->crp_etype = ENOENT; -+ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); -+ goto done; -+ } -+ -+ /* -+ * do some error checking outside of the loop for SKB and IOV processing -+ * this leaves us with valid skb or uiop pointers for later -+ */ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ struct sk_buff *skb = (struct sk_buff *) crp->crp_buf; -+ if (skb_shinfo(skb)->nr_frags >= SCATTERLIST_MAX) { -+ printk("%s,%d: %d nr_frags > SCATTERLIST_MAX", __FILE__, __LINE__, -+ skb_shinfo(skb)->nr_frags); -+ goto done; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ struct uio *uiop = (struct uio *) crp->crp_buf; -+ if (uiop->uio_iovcnt > SCATTERLIST_MAX) { -+ printk("%s,%d: %d uio_iovcnt > SCATTERLIST_MAX", __FILE__, __LINE__, -+ uiop->uio_iovcnt); -+ goto done; -+ } -+ } -+ -+ /* -+ * setup a new request ready for queuing -+ */ -+ req = kmem_cache_alloc(swcr_req_cache, SLAB_ATOMIC); -+ if (req == NULL) { -+ dprintk("%s,%d: ENOMEM\n", __FILE__, __LINE__); -+ crp->crp_etype = ENOMEM; -+ goto done; -+ } -+ memset(req, 0, sizeof(*req)); -+ -+ req->sw_head = swcr_sessions[lid]; -+ req->crp = crp; -+ req->crd = crp->crp_desc; -+ -+ swcr_process_req(req); -+ return 0; -+ -+done: -+ crypto_done(crp); -+ if (req) -+ kmem_cache_free(swcr_req_cache, req); -+ return 0; -+} -+ -+ -+static int -+cryptosoft_init(void) -+{ -+ int i, sw_type, mode; -+ char *algo; -+ -+ dprintk("%s(%p)\n", __FUNCTION__, cryptosoft_init); -+ -+ swcr_req_cache = kmem_cache_create("cryptosoft_req", -+ sizeof(struct swcr_req), 0, SLAB_HWCACHE_ALIGN, NULL -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) -+ , NULL -+#endif -+ ); -+ if (!swcr_req_cache) { -+ printk("cryptosoft: failed to create request cache\n"); -+ return -ENOENT; -+ } -+ -+ softc_device_init(&swcr_softc, "cryptosoft", 0, swcr_methods); -+ -+ swcr_id = crypto_get_driverid(softc_get_device(&swcr_softc), -+ CRYPTOCAP_F_SOFTWARE | CRYPTOCAP_F_SYNC); -+ if (swcr_id < 0) { -+ printk("cryptosoft: Software crypto device cannot initialize!"); -+ return -ENODEV; -+ } -+ -+#define REGISTER(alg) \ -+ crypto_register(swcr_id, alg, 0,0) -+ -+ for (i = 0; i < sizeof(crypto_details)/sizeof(crypto_details[0]); i++) { -+ int found; -+ -+ algo = crypto_details[i].alg_name; -+ if (!algo || !*algo) { -+ dprintk("%s:Algorithm %d not supported\n", __FUNCTION__, i); -+ continue; -+ } -+ -+ mode = crypto_details[i].mode; -+ sw_type = crypto_details[i].sw_type; -+ -+ found = 0; -+ switch (sw_type & SW_TYPE_ALG_MASK) { -+ case SW_TYPE_CIPHER: -+ found = crypto_has_cipher(algo, 0, CRYPTO_ALG_ASYNC); -+ break; -+ case SW_TYPE_HMAC: -+ found = crypto_has_hash(algo, 0, swcr_no_ahash?CRYPTO_ALG_ASYNC:0); -+ break; -+ case SW_TYPE_HASH: -+ found = crypto_has_hash(algo, 0, swcr_no_ahash?CRYPTO_ALG_ASYNC:0); -+ break; -+ case SW_TYPE_COMP: -+ found = crypto_has_comp(algo, 0, CRYPTO_ALG_ASYNC); -+ break; -+ case SW_TYPE_BLKCIPHER: -+ found = crypto_has_blkcipher(algo, 0, CRYPTO_ALG_ASYNC); -+ if (!found && !swcr_no_ablk) -+ found = crypto_has_ablkcipher(algo, 0, 0); -+ break; -+ } -+ if (found) { -+ REGISTER(i); -+ } else { -+ dprintk("%s:Algorithm Type %d not supported (algorithm %d:'%s')\n", -+ __FUNCTION__, sw_type, i, algo); -+ } -+ } -+ return 0; -+} -+ -+static void -+cryptosoft_exit(void) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ crypto_unregister_all(swcr_id); -+ swcr_id = -1; -+ kmem_cache_destroy(swcr_req_cache); -+} -+ -+late_initcall(cryptosoft_init); -+module_exit(cryptosoft_exit); -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("Cryptosoft (OCF module for kernel crypto)"); -diff -Nur linux-3.0.4.orig/crypto/ocf/ep80579/Makefile linux-3.0.4/crypto/ocf/ep80579/Makefile ---- linux-3.0.4.orig/crypto/ocf/ep80579/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/ep80579/Makefile 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,119 @@ -+######################################################################### -+# -+# Targets supported -+# all - builds everything and installs -+# install - identical to all -+# depend - build dependencies -+# clean - clears derived objects except the .depend files -+# distclean- clears all derived objects and the .depend file -+# -+# @par -+# This file is provided under a dual BSD/GPLv2 license. When using or -+# redistributing this file, you may do so under either license. -+# -+# GPL LICENSE SUMMARY -+# -+# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+# -+# This program is free software; you can redistribute it and/or modify -+# it under the terms of version 2 of the GNU General Public License as -+# published by the Free Software Foundation. -+# -+# This program is distributed in the hope that it will be useful, but -+# WITHOUT ANY WARRANTY; without even the implied warranty of -+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+# General Public License for more details. -+# -+# You should have received a copy of the GNU General Public License -+# along with this program; if not, write to the Free Software -+# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. -+# The full GNU General Public License is included in this distribution -+# in the file called LICENSE.GPL. -+# -+# Contact Information: -+# Intel Corporation -+# -+# BSD LICENSE -+# -+# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+# All rights reserved. -+# -+# Redistribution and use in source and binary forms, with or without -+# modification, are permitted provided that the following conditions -+# are met: -+# -+# * Redistributions of source code must retain the above copyright -+# notice, this list of conditions and the following disclaimer. -+# * Redistributions in binary form must reproduce the above copyright -+# notice, this list of conditions and the following disclaimer in -+# the documentation and/or other materials provided with the -+# distribution. -+# * Neither the name of Intel Corporation nor the names of its -+# contributors may be used to endorse or promote products derived -+# from this software without specific prior written permission. -+# -+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+# -+# -+# version: Security.L.1.0.2-229 -+############################################################################ -+ -+ -+####################Common variables and definitions######################## -+ -+ifndef ICP_ROOT -+$(warning ICP_ROOT is undefined. Please set the path to EP80579 release package directory \ -+ "-> setenv ICP_ROOT ") -+all fastdep: -+ : -+else -+ -+ifndef KERNEL_SOURCE_ROOT -+$(error KERNEL_SOURCE_ROOT is undefined. Please set the path to the kernel source directory \ -+ "-> setenv KERNEL_SOURCE_ROOT ") -+endif -+ -+# Ensure The ENV_DIR environmental var is defined. -+ifndef ICP_ENV_DIR -+$(error ICP_ENV_DIR is undefined. Please set the path to EP80579 driver environment.mk file \ -+ "-> setenv ICP_ENV_DIR ") -+endif -+ -+#Add your project environment Makefile -+include ${ICP_ENV_DIR}/environment.mk -+ -+#include the makefile with all the default and common Make variable definitions -+include ${ICP_BUILDSYSTEM_PATH}/build_files/common.mk -+ -+#Add the name for the executable, Library or Module output definitions -+OUTPUT_NAME= icp_ocf -+ -+# List of Source Files to be compiled -+SOURCES= icp_common.c icp_sym.c icp_asym.c icp_ocf_linux.c -+ -+#common includes between all supported OSes -+INCLUDES= -I ${ICP_API_DIR} -I${ICP_LAC_API} \ -+-I${ICP_OCF_SRC_DIR} -+ -+# The location of the os level makefile needs to be changed. -+include ${ICP_ENV_DIR}/${ICP_OS}_${ICP_OS_LEVEL}.mk -+ -+# On the line directly below list the outputs you wish to build for, -+# e.g "lib_static lib_shared exe module" as shown below -+install: module -+ -+###################Include rules makefiles######################## -+include ${ICP_BUILDSYSTEM_PATH}/build_files/rules.mk -+###################End of Rules inclusion######################### -+ -+endif -diff -Nur linux-3.0.4.orig/crypto/ocf/ep80579/environment.mk linux-3.0.4/crypto/ocf/ep80579/environment.mk ---- linux-3.0.4.orig/crypto/ocf/ep80579/environment.mk 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/ep80579/environment.mk 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,78 @@ -+ ########################################################################### -+ # -+# This file is provided under a dual BSD/GPLv2 license. When using or -+# redistributing this file, you may do so under either license. -+# -+# GPL LICENSE SUMMARY -+# -+# Copyright(c) 2007,2008 Intel Corporation. All rights reserved. -+# -+# This program is free software; you can redistribute it and/or modify -+# it under the terms of version 2 of the GNU General Public License as -+# published by the Free Software Foundation. -+# -+# This program is distributed in the hope that it will be useful, but -+# WITHOUT ANY WARRANTY; without even the implied warranty of -+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+# General Public License for more details. -+# -+# You should have received a copy of the GNU General Public License -+# along with this program; if not, write to the Free Software -+# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. -+# The full GNU General Public License is included in this distribution -+# in the file called LICENSE.GPL. -+# -+# Contact Information: -+# Intel Corporation -+# -+# BSD LICENSE -+# -+# Copyright(c) 2007,2008 Intel Corporation. All rights reserved. -+# All rights reserved. -+# -+# Redistribution and use in source and binary forms, with or without -+# modification, are permitted provided that the following conditions -+# are met: -+# -+# * Redistributions of source code must retain the above copyright -+# notice, this list of conditions and the following disclaimer. -+# * Redistributions in binary form must reproduce the above copyright -+# notice, this list of conditions and the following disclaimer in -+# the documentation and/or other materials provided with the -+# distribution. -+# * Neither the name of Intel Corporation nor the names of its -+# contributors may be used to endorse or promote products derived -+# from this software without specific prior written permission. -+# -+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+# -+# -+# version: Security.L.1.0.130 -+ # -+ ########################################################################### -+ -+ -+ICP_LAC_API=$(ICP_ROOT)/Acceleration/include/lac -+ICP_BTR_API=$(ICP_ROOT)/Acceleration/include/btr -+ICP_API_DIR=$(ICP_ROOT)/Acceleration/include -+ICP_OCF_SHIM_DIR?=$(KERNEL_SOURCE_ROOT)/crypto/ocf/ -+ifeq ($(wildcard $(ICP_OCF_SHIM_DIR)),) -+ICP_OCF_SHIM_DIR?=$(ROOTDIR)/modules/ocf/ -+endif -+ -+ICP_OS_LEVEL?=kernel_space -+ -+ICP_OS?=linux_2.6 -+ -+ICP_CORE?=ia -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/ep80579/icp_asym.c linux-3.0.4/crypto/ocf/ep80579/icp_asym.c ---- linux-3.0.4.orig/crypto/ocf/ep80579/icp_asym.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/ep80579/icp_asym.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,1334 @@ -+/*************************************************************************** -+ * -+ * This file is provided under a dual BSD/GPLv2 license. When using or -+ * redistributing this file, you may do so under either license. -+ * -+ * GPL LICENSE SUMMARY -+ * -+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of version 2 of the GNU General Public License as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. -+ * The full GNU General Public License is included in this distribution -+ * in the file called LICENSE.GPL. -+ * -+ * Contact Information: -+ * Intel Corporation -+ * -+ * BSD LICENSE -+ * -+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * * Neither the name of Intel Corporation nor the names of its -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * -+ * version: Security.L.1.0.2-229 -+ * -+ ***************************************************************************/ -+ -+#include "icp_ocf.h" -+ -+/*The following define values (containing the word 'INDEX') are used to find -+the index of each input buffer of the crypto_kop struct (see OCF cryptodev.h). -+These values were found through analysis of the OCF OpenSSL patch. If the -+calling program uses different input buffer positions, these defines will have -+to be changed.*/ -+ -+/*DIFFIE HELLMAN buffer index values*/ -+#define ICP_DH_KRP_PARAM_PRIME_INDEX (0) -+#define ICP_DH_KRP_PARAM_BASE_INDEX (1) -+#define ICP_DH_KRP_PARAM_PRIVATE_VALUE_INDEX (2) -+#define ICP_DH_KRP_PARAM_RESULT_INDEX (3) -+ -+/*MOD EXP buffer index values*/ -+#define ICP_MOD_EXP_KRP_PARAM_BASE_INDEX (0) -+#define ICP_MOD_EXP_KRP_PARAM_EXPONENT_INDEX (1) -+#define ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX (2) -+#define ICP_MOD_EXP_KRP_PARAM_RESULT_INDEX (3) -+ -+/*MOD EXP CRT buffer index values*/ -+#define ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_P_INDEX (0) -+#define ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_Q_INDEX (1) -+#define ICP_MOD_EXP_CRT_KRP_PARAM_I_INDEX (2) -+#define ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DP_INDEX (3) -+#define ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DQ_INDEX (4) -+#define ICP_MOD_EXP_CRT_KRP_PARAM_COEFF_QINV_INDEX (5) -+#define ICP_MOD_EXP_CRT_KRP_PARAM_RESULT_INDEX (6) -+ -+/*DSA sign buffer index values*/ -+#define ICP_DSA_SIGN_KRP_PARAM_DGST_INDEX (0) -+#define ICP_DSA_SIGN_KRP_PARAM_PRIME_P_INDEX (1) -+#define ICP_DSA_SIGN_KRP_PARAM_PRIME_Q_INDEX (2) -+#define ICP_DSA_SIGN_KRP_PARAM_G_INDEX (3) -+#define ICP_DSA_SIGN_KRP_PARAM_X_INDEX (4) -+#define ICP_DSA_SIGN_KRP_PARAM_R_RESULT_INDEX (5) -+#define ICP_DSA_SIGN_KRP_PARAM_S_RESULT_INDEX (6) -+ -+/*DSA verify buffer index values*/ -+#define ICP_DSA_VERIFY_KRP_PARAM_DGST_INDEX (0) -+#define ICP_DSA_VERIFY_KRP_PARAM_PRIME_P_INDEX (1) -+#define ICP_DSA_VERIFY_KRP_PARAM_PRIME_Q_INDEX (2) -+#define ICP_DSA_VERIFY_KRP_PARAM_G_INDEX (3) -+#define ICP_DSA_VERIFY_KRP_PARAM_PUBKEY_INDEX (4) -+#define ICP_DSA_VERIFY_KRP_PARAM_SIG_R_INDEX (5) -+#define ICP_DSA_VERIFY_KRP_PARAM_SIG_S_INDEX (6) -+ -+/*DSA sign prime Q vs random number K size check values*/ -+#define DONT_RUN_LESS_THAN_CHECK (0) -+#define FAIL_A_IS_GREATER_THAN_B (1) -+#define FAIL_A_IS_EQUAL_TO_B (1) -+#define SUCCESS_A_IS_LESS_THAN_B (0) -+#define DSA_SIGN_RAND_GEN_VAL_CHECK_MAX_ITERATIONS (500) -+ -+/* We need to set a cryptokp success value just in case it is set or allocated -+ and not set to zero outside of this module */ -+#define CRYPTO_OP_SUCCESS (0) -+ -+/*Function to compute Diffie Hellman (DH) phase 1 or phase 2 key values*/ -+static int icp_ocfDrvDHComputeKey(struct cryptkop *krp); -+ -+/*Function to compute a Modular Exponentiation (Mod Exp)*/ -+static int icp_ocfDrvModExp(struct cryptkop *krp); -+ -+/*Function to compute a Mod Exp using the Chinease Remainder Theorem*/ -+static int icp_ocfDrvModExpCRT(struct cryptkop *krp); -+ -+/*Helper function to compute whether the first big number argument is less than -+ the second big number argument */ -+static int -+icp_ocfDrvCheckALessThanB(CpaFlatBuffer * pK, CpaFlatBuffer * pQ, int *doCheck); -+ -+/*Function to sign an input with DSA R and S keys*/ -+static int icp_ocfDrvDsaSign(struct cryptkop *krp); -+ -+/*Function to Verify a DSA buffer signature*/ -+static int icp_ocfDrvDsaVerify(struct cryptkop *krp); -+ -+/*Callback function for DH operation*/ -+static void -+icp_ocfDrvDhP1CallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, CpaFlatBuffer * pLocalOctetStringPV); -+ -+/*Callback function for ME operation*/ -+static void -+icp_ocfDrvModExpCallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, CpaFlatBuffer * pResult); -+ -+/*Callback function for ME CRT operation*/ -+static void -+icp_ocfDrvModExpCRTCallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, CpaFlatBuffer * pOutputData); -+ -+/*Callback function for DSA sign operation*/ -+static void -+icp_ocfDrvDsaRSSignCallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, -+ CpaBoolean protocolStatus, -+ CpaFlatBuffer * pR, CpaFlatBuffer * pS); -+ -+/*Callback function for DSA Verify operation*/ -+static void -+icp_ocfDrvDsaVerifyCallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, CpaBoolean verifyStatus); -+ -+/* Name : icp_ocfDrvPkeProcess -+ * -+ * Description : This function will choose which PKE process to follow -+ * based on the input arguments -+ */ -+int icp_ocfDrvPkeProcess(icp_device_t dev, struct cryptkop *krp, int hint) -+{ -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ -+ if (NULL == krp) { -+ DPRINTK("%s(): Invalid input parameters, cryptkop = %p\n", -+ __FUNCTION__, krp); -+ return EINVAL; -+ } -+ -+ if (CPA_TRUE == icp_atomic_read(&icp_ocfDrvIsExiting)) { -+ krp->krp_status = ECANCELED; -+ return ECANCELED; -+ } -+ -+ switch (krp->krp_op) { -+ case CRK_DH_COMPUTE_KEY: -+ DPRINTK("%s() doing DH_COMPUTE_KEY\n", __FUNCTION__); -+ lacStatus = icp_ocfDrvDHComputeKey(krp); -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): icp_ocfDrvDHComputeKey failed " -+ "(%d).\n", __FUNCTION__, lacStatus); -+ krp->krp_status = ECANCELED; -+ return ECANCELED; -+ } -+ -+ break; -+ -+ case CRK_MOD_EXP: -+ DPRINTK("%s() doing MOD_EXP \n", __FUNCTION__); -+ lacStatus = icp_ocfDrvModExp(krp); -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): icp_ocfDrvModExp failed (%d).\n", -+ __FUNCTION__, lacStatus); -+ krp->krp_status = ECANCELED; -+ return ECANCELED; -+ } -+ -+ break; -+ -+ case CRK_MOD_EXP_CRT: -+ DPRINTK("%s() doing MOD_EXP_CRT \n", __FUNCTION__); -+ lacStatus = icp_ocfDrvModExpCRT(krp); -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): icp_ocfDrvModExpCRT " -+ "failed (%d).\n", __FUNCTION__, lacStatus); -+ krp->krp_status = ECANCELED; -+ return ECANCELED; -+ } -+ -+ break; -+ -+ case CRK_DSA_SIGN: -+ DPRINTK("%s() doing DSA_SIGN \n", __FUNCTION__); -+ lacStatus = icp_ocfDrvDsaSign(krp); -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): icp_ocfDrvDsaSign " -+ "failed (%d).\n", __FUNCTION__, lacStatus); -+ krp->krp_status = ECANCELED; -+ return ECANCELED; -+ } -+ -+ break; -+ -+ case CRK_DSA_VERIFY: -+ DPRINTK("%s() doing DSA_VERIFY \n", __FUNCTION__); -+ lacStatus = icp_ocfDrvDsaVerify(krp); -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): icp_ocfDrvDsaVerify " -+ "failed (%d).\n", __FUNCTION__, lacStatus); -+ krp->krp_status = ECANCELED; -+ return ECANCELED; -+ } -+ -+ break; -+ -+ default: -+ EPRINTK("%s(): Asymettric function not " -+ "supported (%d).\n", __FUNCTION__, krp->krp_op); -+ krp->krp_status = EOPNOTSUPP; -+ return EOPNOTSUPP; -+ } -+ -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+} -+ -+/* Name : icp_ocfDrvSwapBytes -+ * -+ * Description : This function is used to swap the byte order of a buffer. -+ * It has been seen that in general we are passed little endian byte order -+ * buffers, but LAC only accepts big endian byte order buffers. -+ */ -+static void inline icp_ocfDrvSwapBytes(u_int8_t * num, u_int32_t buff_len_bytes) -+{ -+ -+ int i; -+ u_int8_t *end_ptr; -+ u_int8_t hold_val; -+ -+ end_ptr = num + (buff_len_bytes - 1); -+ buff_len_bytes = buff_len_bytes >> 1; -+ for (i = 0; i < buff_len_bytes; i++) { -+ hold_val = *num; -+ *num = *end_ptr; -+ num++; -+ *end_ptr = hold_val; -+ end_ptr--; -+ } -+} -+ -+/* Name : icp_ocfDrvDHComputeKey -+ * -+ * Description : This function will map Diffie Hellman calls from OCF -+ * to the LAC API. OCF uses this function for Diffie Hellman Phase1 and -+ * Phase2. LAC has a separate Diffie Hellman Phase2 call, however both phases -+ * break down to a modular exponentiation. -+ */ -+static int icp_ocfDrvDHComputeKey(struct cryptkop *krp) -+{ -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ void *callbackTag = NULL; -+ CpaCyDhPhase1KeyGenOpData *pPhase1OpData = NULL; -+ CpaFlatBuffer *pLocalOctetStringPV = NULL; -+ uint32_t dh_prime_len_bytes = 0, dh_prime_len_bits = 0; -+ -+ /* Input checks - check prime is a multiple of 8 bits to allow for -+ allocation later */ -+ dh_prime_len_bits = -+ (krp->krp_param[ICP_DH_KRP_PARAM_PRIME_INDEX].crp_nbits); -+ -+ /* LAC can reject prime lengths based on prime key sizes, we just -+ need to make sure we can allocate space for the base and -+ exponent buffers correctly */ -+ if ((dh_prime_len_bits % NUM_BITS_IN_BYTE) != 0) { -+ APRINTK("%s(): Warning Prime number buffer size is not a " -+ "multiple of 8 bits\n", __FUNCTION__); -+ } -+ -+ /* Result storage space should be the same size as the prime as this -+ value can take up the same amount of storage space */ -+ if (dh_prime_len_bits != -+ krp->krp_param[ICP_DH_KRP_PARAM_RESULT_INDEX].crp_nbits) { -+ DPRINTK("%s(): Return Buffer must be the same size " -+ "as the Prime buffer\n", __FUNCTION__); -+ krp->krp_status = EINVAL; -+ return EINVAL; -+ } -+ /* Switch to size in bytes */ -+ BITS_TO_BYTES(dh_prime_len_bytes, dh_prime_len_bits); -+ -+ callbackTag = krp; -+ -+/*All allocations are set to ICP_M_NOWAIT due to the possibility of getting -+called in interrupt context*/ -+ pPhase1OpData = icp_kmem_cache_zalloc(drvDH_zone, ICP_M_NOWAIT); -+ if (NULL == pPhase1OpData) { -+ APRINTK("%s():Failed to get memory for key gen data\n", -+ __FUNCTION__); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ pLocalOctetStringPV = -+ icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); -+ if (NULL == pLocalOctetStringPV) { -+ APRINTK("%s():Failed to get memory for pLocalOctetStringPV\n", -+ __FUNCTION__); -+ ICP_CACHE_FREE(drvDH_zone, pPhase1OpData); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ /* Link parameters */ -+ pPhase1OpData->primeP.pData = -+ krp->krp_param[ICP_DH_KRP_PARAM_PRIME_INDEX].crp_p; -+ -+ pPhase1OpData->primeP.dataLenInBytes = dh_prime_len_bytes; -+ -+ icp_ocfDrvSwapBytes(pPhase1OpData->primeP.pData, dh_prime_len_bytes); -+ -+ pPhase1OpData->baseG.pData = -+ krp->krp_param[ICP_DH_KRP_PARAM_BASE_INDEX].crp_p; -+ -+ BITS_TO_BYTES(pPhase1OpData->baseG.dataLenInBytes, -+ krp->krp_param[ICP_DH_KRP_PARAM_BASE_INDEX].crp_nbits); -+ -+ icp_ocfDrvSwapBytes(pPhase1OpData->baseG.pData, -+ pPhase1OpData->baseG.dataLenInBytes); -+ -+ pPhase1OpData->privateValueX.pData = -+ krp->krp_param[ICP_DH_KRP_PARAM_PRIVATE_VALUE_INDEX].crp_p; -+ -+ BITS_TO_BYTES(pPhase1OpData->privateValueX.dataLenInBytes, -+ krp->krp_param[ICP_DH_KRP_PARAM_PRIVATE_VALUE_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(pPhase1OpData->privateValueX.pData, -+ pPhase1OpData->privateValueX.dataLenInBytes); -+ -+ /* Output parameters */ -+ pLocalOctetStringPV->pData = -+ krp->krp_param[ICP_DH_KRP_PARAM_RESULT_INDEX].crp_p; -+ -+ BITS_TO_BYTES(pLocalOctetStringPV->dataLenInBytes, -+ krp->krp_param[ICP_DH_KRP_PARAM_RESULT_INDEX].crp_nbits); -+ -+ lacStatus = cpaCyDhKeyGenPhase1(CPA_INSTANCE_HANDLE_SINGLE, -+ icp_ocfDrvDhP1CallBack, -+ callbackTag, pPhase1OpData, -+ pLocalOctetStringPV); -+ -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): DH Phase 1 Key Gen failed (%d).\n", -+ __FUNCTION__, lacStatus); -+ icp_ocfDrvFreeFlatBuffer(pLocalOctetStringPV); -+ ICP_CACHE_FREE(drvDH_zone, pPhase1OpData); -+ } -+ -+ return lacStatus; -+} -+ -+/* Name : icp_ocfDrvModExp -+ * -+ * Description : This function will map ordinary Modular Exponentiation calls -+ * from OCF to the LAC API. -+ * -+ */ -+static int icp_ocfDrvModExp(struct cryptkop *krp) -+{ -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ void *callbackTag = NULL; -+ CpaCyLnModExpOpData *pModExpOpData = NULL; -+ CpaFlatBuffer *pResult = NULL; -+ -+ if ((krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX].crp_nbits % -+ NUM_BITS_IN_BYTE) != 0) { -+ DPRINTK("%s(): Warning - modulus buffer size (%d) is not a " -+ "multiple of 8 bits\n", __FUNCTION__, -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX]. -+ crp_nbits); -+ } -+ -+ /* Result storage space should be the same size as the prime as this -+ value can take up the same amount of storage space */ -+ if (krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX].crp_nbits > -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_RESULT_INDEX].crp_nbits) { -+ APRINTK("%s(): Return Buffer size must be the same or" -+ " greater than the Modulus buffer\n", __FUNCTION__); -+ krp->krp_status = EINVAL; -+ return EINVAL; -+ } -+ -+ callbackTag = krp; -+ -+ pModExpOpData = icp_kmem_cache_zalloc(drvLnModExp_zone, ICP_M_NOWAIT); -+ if (NULL == pModExpOpData) { -+ APRINTK("%s():Failed to get memory for key gen data\n", -+ __FUNCTION__); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ pResult = icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); -+ if (NULL == pResult) { -+ APRINTK("%s():Failed to get memory for ModExp result\n", -+ __FUNCTION__); -+ ICP_CACHE_FREE(drvLnModExp_zone, pModExpOpData); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ /* Link parameters */ -+ pModExpOpData->modulus.pData = -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX].crp_p; -+ BITS_TO_BYTES(pModExpOpData->modulus.dataLenInBytes, -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(pModExpOpData->modulus.pData, -+ pModExpOpData->modulus.dataLenInBytes); -+ -+ DPRINTK("%s : base (%d)\n", __FUNCTION__, krp-> -+ krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX].crp_nbits); -+ pModExpOpData->base.pData = -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX].crp_p; -+ BITS_TO_BYTES(pModExpOpData->base.dataLenInBytes, -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX]. -+ crp_nbits); -+ icp_ocfDrvSwapBytes(pModExpOpData->base.pData, -+ pModExpOpData->base.dataLenInBytes); -+ -+ pModExpOpData->exponent.pData = -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_EXPONENT_INDEX].crp_p; -+ BITS_TO_BYTES(pModExpOpData->exponent.dataLenInBytes, -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_EXPONENT_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(pModExpOpData->exponent.pData, -+ pModExpOpData->exponent.dataLenInBytes); -+ /* Output parameters */ -+ pResult->pData = -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_RESULT_INDEX].crp_p, -+ BITS_TO_BYTES(pResult->dataLenInBytes, -+ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_RESULT_INDEX]. -+ crp_nbits); -+ -+ lacStatus = cpaCyLnModExp(CPA_INSTANCE_HANDLE_SINGLE, -+ icp_ocfDrvModExpCallBack, -+ callbackTag, pModExpOpData, pResult); -+ -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): Mod Exp Operation failed (%d).\n", -+ __FUNCTION__, lacStatus); -+ krp->krp_status = ECANCELED; -+ icp_ocfDrvFreeFlatBuffer(pResult); -+ ICP_CACHE_FREE(drvLnModExp_zone, pModExpOpData); -+ } -+ -+ return lacStatus; -+} -+ -+/* Name : icp_ocfDrvModExpCRT -+ * -+ * Description : This function will map ordinary Modular Exponentiation Chinese -+ * Remainder Theorem implementaion calls from OCF to the LAC API. -+ * -+ * Note : Mod Exp CRT for this driver is accelerated through LAC RSA type 2 -+ * decrypt operation. Therefore P and Q input values must always be prime -+ * numbers. Although basic primality checks are done in LAC, it is up to the -+ * user to do any correct prime number checking before passing the inputs. -+ */ -+static int icp_ocfDrvModExpCRT(struct cryptkop *krp) -+{ -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ CpaCyRsaDecryptOpData *rsaDecryptOpData = NULL; -+ void *callbackTag = NULL; -+ CpaFlatBuffer *pOutputData = NULL; -+ -+ /*Parameter input checks are all done by LAC, no need to repeat -+ them here. */ -+ callbackTag = krp; -+ -+ rsaDecryptOpData = -+ icp_kmem_cache_zalloc(drvRSADecrypt_zone, ICP_M_NOWAIT); -+ if (NULL == rsaDecryptOpData) { -+ APRINTK("%s():Failed to get memory" -+ " for MOD EXP CRT Op data struct\n", __FUNCTION__); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ rsaDecryptOpData->pRecipientPrivateKey -+ = icp_kmem_cache_zalloc(drvRSAPrivateKey_zone, ICP_M_NOWAIT); -+ if (NULL == rsaDecryptOpData->pRecipientPrivateKey) { -+ APRINTK("%s():Failed to get memory for MOD EXP CRT" -+ " private key values struct\n", __FUNCTION__); -+ ICP_CACHE_FREE(drvRSADecrypt_zone, rsaDecryptOpData); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ version = CPA_CY_RSA_VERSION_TWO_PRIME; -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRepType = CPA_CY_RSA_PRIVATE_KEY_REP_TYPE_2; -+ -+ pOutputData = icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); -+ if (NULL == pOutputData) { -+ APRINTK("%s():Failed to get memory" -+ " for MOD EXP CRT output data\n", __FUNCTION__); -+ ICP_CACHE_FREE(drvRSAPrivateKey_zone, -+ rsaDecryptOpData->pRecipientPrivateKey); -+ ICP_CACHE_FREE(drvRSADecrypt_zone, rsaDecryptOpData); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ version = CPA_CY_RSA_VERSION_TWO_PRIME; -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRepType = CPA_CY_RSA_PRIVATE_KEY_REP_TYPE_2; -+ -+ /* Link parameters */ -+ rsaDecryptOpData->inputData.pData = -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_I_INDEX].crp_p; -+ BITS_TO_BYTES(rsaDecryptOpData->inputData.dataLenInBytes, -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_I_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(rsaDecryptOpData->inputData.pData, -+ rsaDecryptOpData->inputData.dataLenInBytes); -+ -+ rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2.prime1P.pData = -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_P_INDEX].crp_p; -+ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2. -+ prime1P.dataLenInBytes, -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_P_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.prime1P.pData, -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.prime1P.dataLenInBytes); -+ -+ rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2.prime2Q.pData = -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_Q_INDEX].crp_p; -+ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2. -+ prime2Q.dataLenInBytes, -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_Q_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.prime2Q.pData, -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.prime2Q.dataLenInBytes); -+ -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.exponent1Dp.pData = -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DP_INDEX].crp_p; -+ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2. -+ exponent1Dp.dataLenInBytes, -+ krp-> -+ krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DP_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.exponent1Dp.pData, -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.exponent1Dp.dataLenInBytes); -+ -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.exponent2Dq.pData = -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DQ_INDEX].crp_p; -+ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.exponent2Dq.dataLenInBytes, -+ krp-> -+ krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DQ_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.exponent2Dq.pData, -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.exponent2Dq.dataLenInBytes); -+ -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.coefficientQInv.pData = -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_COEFF_QINV_INDEX].crp_p; -+ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.coefficientQInv.dataLenInBytes, -+ krp-> -+ krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_COEFF_QINV_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.coefficientQInv.pData, -+ rsaDecryptOpData->pRecipientPrivateKey-> -+ privateKeyRep2.coefficientQInv.dataLenInBytes); -+ -+ /* Output Parameter */ -+ pOutputData->pData = -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_RESULT_INDEX].crp_p; -+ BITS_TO_BYTES(pOutputData->dataLenInBytes, -+ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_RESULT_INDEX]. -+ crp_nbits); -+ -+ lacStatus = cpaCyRsaDecrypt(CPA_INSTANCE_HANDLE_SINGLE, -+ icp_ocfDrvModExpCRTCallBack, -+ callbackTag, rsaDecryptOpData, pOutputData); -+ -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): Mod Exp CRT Operation failed (%d).\n", -+ __FUNCTION__, lacStatus); -+ krp->krp_status = ECANCELED; -+ icp_ocfDrvFreeFlatBuffer(pOutputData); -+ ICP_CACHE_FREE(drvRSAPrivateKey_zone, -+ rsaDecryptOpData->pRecipientPrivateKey); -+ ICP_CACHE_FREE(drvRSADecrypt_zone, rsaDecryptOpData); -+ } -+ -+ return lacStatus; -+} -+ -+/* Name : icp_ocfDrvCheckALessThanB -+ * -+ * Description : This function will check whether the first argument is less -+ * than the second. It is used to check whether the DSA RS sign Random K -+ * value is less than the Prime Q value (as defined in the specification) -+ * -+ */ -+static int -+icp_ocfDrvCheckALessThanB(CpaFlatBuffer * pK, CpaFlatBuffer * pQ, int *doCheck) -+{ -+ -+ uint8_t *MSB_K = pK->pData; -+ uint8_t *MSB_Q = pQ->pData; -+ uint32_t buffer_lengths_in_bytes = pQ->dataLenInBytes; -+ -+ if (DONT_RUN_LESS_THAN_CHECK == *doCheck) { -+ return FAIL_A_IS_GREATER_THAN_B; -+ } -+ -+/*Check MSBs -+if A == B, check next MSB -+if A > B, return A_IS_GREATER_THAN_B -+if A < B, return A_IS_LESS_THAN_B (success) -+*/ -+ while (*MSB_K == *MSB_Q) { -+ MSB_K++; -+ MSB_Q++; -+ -+ buffer_lengths_in_bytes--; -+ if (0 == buffer_lengths_in_bytes) { -+ DPRINTK("%s() Buffers have equal value!!\n", -+ __FUNCTION__); -+ return FAIL_A_IS_EQUAL_TO_B; -+ } -+ -+ } -+ -+ if (*MSB_K < *MSB_Q) { -+ return SUCCESS_A_IS_LESS_THAN_B; -+ } else { -+ return FAIL_A_IS_GREATER_THAN_B; -+ } -+ -+} -+ -+/* Name : icp_ocfDrvDsaSign -+ * -+ * Description : This function will map DSA RS Sign from OCF to the LAC API. -+ * -+ * NOTE: From looking at OCF patch to OpenSSL and even the number of input -+ * parameters, OCF expects us to generate the random seed value. This value -+ * is generated and passed to LAC, however the number is discared in the -+ * callback and not returned to the user. -+ */ -+static int icp_ocfDrvDsaSign(struct cryptkop *krp) -+{ -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ CpaCyDsaRSSignOpData *dsaRsSignOpData = NULL; -+ void *callbackTag = NULL; -+ CpaCyRandGenOpData randGenOpData; -+ int primeQSizeInBytes = 0; -+ int doCheck = 0; -+ CpaFlatBuffer randData; -+ CpaBoolean protocolStatus = CPA_FALSE; -+ CpaFlatBuffer *pR = NULL; -+ CpaFlatBuffer *pS = NULL; -+ -+ callbackTag = krp; -+ -+ BITS_TO_BYTES(primeQSizeInBytes, -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_Q_INDEX]. -+ crp_nbits); -+ -+ if (DSA_RS_SIGN_PRIMEQ_SIZE_IN_BYTES != primeQSizeInBytes) { -+ APRINTK("%s(): DSA PRIME Q size not equal to the " -+ "FIPS defined 20bytes, = %d\n", -+ __FUNCTION__, primeQSizeInBytes); -+ krp->krp_status = EDOM; -+ return EDOM; -+ } -+ -+ dsaRsSignOpData = -+ icp_kmem_cache_zalloc(drvDSARSSign_zone, ICP_M_NOWAIT); -+ if (NULL == dsaRsSignOpData) { -+ APRINTK("%s():Failed to get memory" -+ " for DSA RS Sign Op data struct\n", __FUNCTION__); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ dsaRsSignOpData->K.pData = -+ icp_kmem_cache_alloc(drvDSARSSignKValue_zone, ICP_M_NOWAIT); -+ -+ if (NULL == dsaRsSignOpData->K.pData) { -+ APRINTK("%s():Failed to get memory" -+ " for DSA RS Sign Op Random value\n", __FUNCTION__); -+ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ pR = icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); -+ if (NULL == pR) { -+ APRINTK("%s():Failed to get memory" -+ " for DSA signature R\n", __FUNCTION__); -+ ICP_CACHE_FREE(drvDSARSSignKValue_zone, -+ dsaRsSignOpData->K.pData); -+ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ pS = icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); -+ if (NULL == pS) { -+ APRINTK("%s():Failed to get memory" -+ " for DSA signature S\n", __FUNCTION__); -+ icp_ocfDrvFreeFlatBuffer(pR); -+ ICP_CACHE_FREE(drvDSARSSignKValue_zone, -+ dsaRsSignOpData->K.pData); -+ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ /*link prime number parameter for ease of processing */ -+ dsaRsSignOpData->P.pData = -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_P_INDEX].crp_p; -+ BITS_TO_BYTES(dsaRsSignOpData->P.dataLenInBytes, -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_P_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(dsaRsSignOpData->P.pData, -+ dsaRsSignOpData->P.dataLenInBytes); -+ -+ dsaRsSignOpData->Q.pData = -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_Q_INDEX].crp_p; -+ BITS_TO_BYTES(dsaRsSignOpData->Q.dataLenInBytes, -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_Q_INDEX]. -+ crp_nbits); -+ -+ icp_ocfDrvSwapBytes(dsaRsSignOpData->Q.pData, -+ dsaRsSignOpData->Q.dataLenInBytes); -+ -+ /*generate random number with equal buffer size to Prime value Q, -+ but value less than Q */ -+ dsaRsSignOpData->K.dataLenInBytes = dsaRsSignOpData->Q.dataLenInBytes; -+ -+ randGenOpData.generateBits = CPA_TRUE; -+ randGenOpData.lenInBytes = dsaRsSignOpData->K.dataLenInBytes; -+ -+ icp_ocfDrvPtrAndLenToFlatBuffer(dsaRsSignOpData->K.pData, -+ dsaRsSignOpData->K.dataLenInBytes, -+ &randData); -+ -+ doCheck = 0; -+ while (icp_ocfDrvCheckALessThanB(&(dsaRsSignOpData->K), -+ &(dsaRsSignOpData->Q), &doCheck)) { -+ -+ if (CPA_STATUS_SUCCESS -+ != cpaCyRandGen(CPA_INSTANCE_HANDLE_SINGLE, -+ NULL, NULL, &randGenOpData, &randData)) { -+ APRINTK("%s(): ERROR - Failed to generate DSA RS Sign K" -+ "value\n", __FUNCTION__); -+ icp_ocfDrvFreeFlatBuffer(pS); -+ icp_ocfDrvFreeFlatBuffer(pR); -+ ICP_CACHE_FREE(drvDSARSSignKValue_zone, -+ dsaRsSignOpData->K.pData); -+ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); -+ krp->krp_status = EAGAIN; -+ return EAGAIN; -+ } -+ -+ doCheck++; -+ if (DSA_SIGN_RAND_GEN_VAL_CHECK_MAX_ITERATIONS == doCheck) { -+ APRINTK("%s(): ERROR - Failed to find DSA RS Sign K " -+ "value less than Q value\n", __FUNCTION__); -+ icp_ocfDrvFreeFlatBuffer(pS); -+ icp_ocfDrvFreeFlatBuffer(pR); -+ ICP_CACHE_FREE(drvDSARSSignKValue_zone, -+ dsaRsSignOpData->K.pData); -+ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); -+ krp->krp_status = EAGAIN; -+ return EAGAIN; -+ } -+ -+ } -+ /*Rand Data - no need to swap bytes for pK */ -+ -+ /* Link parameters */ -+ dsaRsSignOpData->G.pData = -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_G_INDEX].crp_p; -+ BITS_TO_BYTES(dsaRsSignOpData->G.dataLenInBytes, -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_G_INDEX].crp_nbits); -+ -+ icp_ocfDrvSwapBytes(dsaRsSignOpData->G.pData, -+ dsaRsSignOpData->G.dataLenInBytes); -+ -+ dsaRsSignOpData->X.pData = -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_X_INDEX].crp_p; -+ BITS_TO_BYTES(dsaRsSignOpData->X.dataLenInBytes, -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_X_INDEX].crp_nbits); -+ icp_ocfDrvSwapBytes(dsaRsSignOpData->X.pData, -+ dsaRsSignOpData->X.dataLenInBytes); -+ -+ /*OpenSSL dgst parameter is left in big endian byte order, -+ therefore no byte swap is required */ -+ dsaRsSignOpData->M.pData = -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_DGST_INDEX].crp_p; -+ BITS_TO_BYTES(dsaRsSignOpData->M.dataLenInBytes, -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_DGST_INDEX]. -+ crp_nbits); -+ -+ /* Output Parameters */ -+ pS->pData = krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_S_RESULT_INDEX].crp_p; -+ BITS_TO_BYTES(pS->dataLenInBytes, -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_S_RESULT_INDEX]. -+ crp_nbits); -+ -+ pR->pData = krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_R_RESULT_INDEX].crp_p; -+ BITS_TO_BYTES(pR->dataLenInBytes, -+ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_R_RESULT_INDEX]. -+ crp_nbits); -+ -+ lacStatus = cpaCyDsaSignRS(CPA_INSTANCE_HANDLE_SINGLE, -+ icp_ocfDrvDsaRSSignCallBack, -+ callbackTag, dsaRsSignOpData, -+ &protocolStatus, pR, pS); -+ -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): DSA RS Sign Operation failed (%d).\n", -+ __FUNCTION__, lacStatus); -+ krp->krp_status = ECANCELED; -+ icp_ocfDrvFreeFlatBuffer(pS); -+ icp_ocfDrvFreeFlatBuffer(pR); -+ ICP_CACHE_FREE(drvDSARSSignKValue_zone, -+ dsaRsSignOpData->K.pData); -+ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); -+ } -+ -+ return lacStatus; -+} -+ -+/* Name : icp_ocfDrvDsaVerify -+ * -+ * Description : This function will map DSA RS Verify from OCF to the LAC API. -+ * -+ */ -+static int icp_ocfDrvDsaVerify(struct cryptkop *krp) -+{ -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ CpaCyDsaVerifyOpData *dsaVerifyOpData = NULL; -+ void *callbackTag = NULL; -+ CpaBoolean verifyStatus = CPA_FALSE; -+ -+ callbackTag = krp; -+ -+ dsaVerifyOpData = -+ icp_kmem_cache_zalloc(drvDSAVerify_zone, ICP_M_NOWAIT); -+ if (NULL == dsaVerifyOpData) { -+ APRINTK("%s():Failed to get memory" -+ " for DSA Verify Op data struct\n", __FUNCTION__); -+ krp->krp_status = ENOMEM; -+ return ENOMEM; -+ } -+ -+ /* Link parameters */ -+ dsaVerifyOpData->P.pData = -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PRIME_P_INDEX].crp_p; -+ BITS_TO_BYTES(dsaVerifyOpData->P.dataLenInBytes, -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PRIME_P_INDEX]. -+ crp_nbits); -+ icp_ocfDrvSwapBytes(dsaVerifyOpData->P.pData, -+ dsaVerifyOpData->P.dataLenInBytes); -+ -+ dsaVerifyOpData->Q.pData = -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PRIME_Q_INDEX].crp_p; -+ BITS_TO_BYTES(dsaVerifyOpData->Q.dataLenInBytes, -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PRIME_Q_INDEX]. -+ crp_nbits); -+ icp_ocfDrvSwapBytes(dsaVerifyOpData->Q.pData, -+ dsaVerifyOpData->Q.dataLenInBytes); -+ -+ dsaVerifyOpData->G.pData = -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_G_INDEX].crp_p; -+ BITS_TO_BYTES(dsaVerifyOpData->G.dataLenInBytes, -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_G_INDEX]. -+ crp_nbits); -+ icp_ocfDrvSwapBytes(dsaVerifyOpData->G.pData, -+ dsaVerifyOpData->G.dataLenInBytes); -+ -+ dsaVerifyOpData->Y.pData = -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PUBKEY_INDEX].crp_p; -+ BITS_TO_BYTES(dsaVerifyOpData->Y.dataLenInBytes, -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PUBKEY_INDEX]. -+ crp_nbits); -+ icp_ocfDrvSwapBytes(dsaVerifyOpData->Y.pData, -+ dsaVerifyOpData->Y.dataLenInBytes); -+ -+ /*OpenSSL dgst parameter is left in big endian byte order, -+ therefore no byte swap is required */ -+ dsaVerifyOpData->M.pData = -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_DGST_INDEX].crp_p; -+ BITS_TO_BYTES(dsaVerifyOpData->M.dataLenInBytes, -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_DGST_INDEX]. -+ crp_nbits); -+ -+ dsaVerifyOpData->R.pData = -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_SIG_R_INDEX].crp_p; -+ BITS_TO_BYTES(dsaVerifyOpData->R.dataLenInBytes, -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_SIG_R_INDEX]. -+ crp_nbits); -+ icp_ocfDrvSwapBytes(dsaVerifyOpData->R.pData, -+ dsaVerifyOpData->R.dataLenInBytes); -+ -+ dsaVerifyOpData->S.pData = -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_SIG_S_INDEX].crp_p; -+ BITS_TO_BYTES(dsaVerifyOpData->S.dataLenInBytes, -+ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_SIG_S_INDEX]. -+ crp_nbits); -+ icp_ocfDrvSwapBytes(dsaVerifyOpData->S.pData, -+ dsaVerifyOpData->S.dataLenInBytes); -+ -+ lacStatus = cpaCyDsaVerify(CPA_INSTANCE_HANDLE_SINGLE, -+ icp_ocfDrvDsaVerifyCallBack, -+ callbackTag, dsaVerifyOpData, &verifyStatus); -+ -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): DSA Verify Operation failed (%d).\n", -+ __FUNCTION__, lacStatus); -+ ICP_CACHE_FREE(drvDSAVerify_zone, dsaVerifyOpData); -+ krp->krp_status = ECANCELED; -+ } -+ -+ return lacStatus; -+} -+ -+/* Name : icp_ocfDrvDhP1Callback -+ * -+ * Description : When this function returns it signifies that the LAC -+ * component has completed the DH operation. -+ */ -+static void -+icp_ocfDrvDhP1CallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, CpaFlatBuffer * pLocalOctetStringPV) -+{ -+ struct cryptkop *krp = NULL; -+ CpaCyDhPhase1KeyGenOpData *pPhase1OpData = NULL; -+ -+ if (NULL == callbackTag) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "callbackTag data is NULL\n", __FUNCTION__); -+ return; -+ } -+ krp = (struct cryptkop *)callbackTag; -+ -+ if (NULL == pOpData) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "Operation Data is NULL\n", __FUNCTION__); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ pPhase1OpData = (CpaCyDhPhase1KeyGenOpData *) pOpData; -+ -+ if (NULL == pLocalOctetStringPV) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "pLocalOctetStringPV Data is NULL\n", __FUNCTION__); -+ memset(pPhase1OpData, 0, sizeof(CpaCyDhPhase1KeyGenOpData)); -+ ICP_CACHE_FREE(drvDH_zone, pPhase1OpData); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ -+ if (CPA_STATUS_SUCCESS == status) { -+ krp->krp_status = CRYPTO_OP_SUCCESS; -+ } else { -+ APRINTK("%s(): Diffie Hellman Phase1 Key Gen failed - " -+ "Operation Status = %d\n", __FUNCTION__, status); -+ krp->krp_status = ECANCELED; -+ } -+ -+ icp_ocfDrvSwapBytes(pLocalOctetStringPV->pData, -+ pLocalOctetStringPV->dataLenInBytes); -+ -+ icp_ocfDrvFreeFlatBuffer(pLocalOctetStringPV); -+ memset(pPhase1OpData, 0, sizeof(CpaCyDhPhase1KeyGenOpData)); -+ ICP_CACHE_FREE(drvDH_zone, pPhase1OpData); -+ -+ crypto_kdone(krp); -+ -+ return; -+} -+ -+/* Name : icp_ocfDrvModExpCallBack -+ * -+ * Description : When this function returns it signifies that the LAC -+ * component has completed the Mod Exp operation. -+ */ -+static void -+icp_ocfDrvModExpCallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpdata, CpaFlatBuffer * pResult) -+{ -+ struct cryptkop *krp = NULL; -+ CpaCyLnModExpOpData *pLnModExpOpData = NULL; -+ -+ if (NULL == callbackTag) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "callbackTag data is NULL\n", __FUNCTION__); -+ return; -+ } -+ krp = (struct cryptkop *)callbackTag; -+ -+ if (NULL == pOpdata) { -+ DPRINTK("%s(): Invalid Mod Exp input parameters - " -+ "Operation Data is NULL\n", __FUNCTION__); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ pLnModExpOpData = (CpaCyLnModExpOpData *) pOpdata; -+ -+ if (NULL == pResult) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "pResult data is NULL\n", __FUNCTION__); -+ krp->krp_status = ECANCELED; -+ memset(pLnModExpOpData, 0, sizeof(CpaCyLnModExpOpData)); -+ ICP_CACHE_FREE(drvLnModExp_zone, pLnModExpOpData); -+ crypto_kdone(krp); -+ return; -+ } -+ -+ if (CPA_STATUS_SUCCESS == status) { -+ krp->krp_status = CRYPTO_OP_SUCCESS; -+ } else { -+ APRINTK("%s(): LAC Mod Exp Operation failed - " -+ "Operation Status = %d\n", __FUNCTION__, status); -+ krp->krp_status = ECANCELED; -+ } -+ -+ icp_ocfDrvSwapBytes(pResult->pData, pResult->dataLenInBytes); -+ -+ /*switch base size value back to original */ -+ if (pLnModExpOpData->base.pData == -+ (uint8_t *) & (krp-> -+ krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX]. -+ crp_nbits)) { -+ *((uint32_t *) pLnModExpOpData->base.pData) = -+ ntohl(*((uint32_t *) pLnModExpOpData->base.pData)); -+ } -+ icp_ocfDrvFreeFlatBuffer(pResult); -+ memset(pLnModExpOpData, 0, sizeof(CpaCyLnModExpOpData)); -+ ICP_CACHE_FREE(drvLnModExp_zone, pLnModExpOpData); -+ -+ crypto_kdone(krp); -+ -+ return; -+ -+} -+ -+/* Name : icp_ocfDrvModExpCRTCallBack -+ * -+ * Description : When this function returns it signifies that the LAC -+ * component has completed the Mod Exp CRT operation. -+ */ -+static void -+icp_ocfDrvModExpCRTCallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, CpaFlatBuffer * pOutputData) -+{ -+ struct cryptkop *krp = NULL; -+ CpaCyRsaDecryptOpData *pDecryptData = NULL; -+ -+ if (NULL == callbackTag) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "callbackTag data is NULL\n", __FUNCTION__); -+ return; -+ } -+ -+ krp = (struct cryptkop *)callbackTag; -+ -+ if (NULL == pOpData) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "Operation Data is NULL\n", __FUNCTION__); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ pDecryptData = (CpaCyRsaDecryptOpData *) pOpData; -+ -+ if (NULL == pOutputData) { -+ DPRINTK("%s(): Invalid input parameter - " -+ "pOutputData is NULL\n", __FUNCTION__); -+ memset(pDecryptData->pRecipientPrivateKey, 0, -+ sizeof(CpaCyRsaPrivateKey)); -+ ICP_CACHE_FREE(drvRSAPrivateKey_zone, -+ pDecryptData->pRecipientPrivateKey); -+ memset(pDecryptData, 0, sizeof(CpaCyRsaDecryptOpData)); -+ ICP_CACHE_FREE(drvRSADecrypt_zone, pDecryptData); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ -+ if (CPA_STATUS_SUCCESS == status) { -+ krp->krp_status = CRYPTO_OP_SUCCESS; -+ } else { -+ APRINTK("%s(): LAC Mod Exp CRT operation failed - " -+ "Operation Status = %d\n", __FUNCTION__, status); -+ krp->krp_status = ECANCELED; -+ } -+ -+ icp_ocfDrvSwapBytes(pOutputData->pData, pOutputData->dataLenInBytes); -+ -+ icp_ocfDrvFreeFlatBuffer(pOutputData); -+ memset(pDecryptData->pRecipientPrivateKey, 0, -+ sizeof(CpaCyRsaPrivateKey)); -+ ICP_CACHE_FREE(drvRSAPrivateKey_zone, -+ pDecryptData->pRecipientPrivateKey); -+ memset(pDecryptData, 0, sizeof(CpaCyRsaDecryptOpData)); -+ ICP_CACHE_FREE(drvRSADecrypt_zone, pDecryptData); -+ -+ crypto_kdone(krp); -+ -+ return; -+} -+ -+/* Name : icp_ocfDrvDsaRSSignCallBack -+ * -+ * Description : When this function returns it signifies that the LAC -+ * component has completed the DSA RS sign operation. -+ */ -+static void -+icp_ocfDrvDsaRSSignCallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, -+ CpaBoolean protocolStatus, -+ CpaFlatBuffer * pR, CpaFlatBuffer * pS) -+{ -+ struct cryptkop *krp = NULL; -+ CpaCyDsaRSSignOpData *pSignData = NULL; -+ -+ if (NULL == callbackTag) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "callbackTag data is NULL\n", __FUNCTION__); -+ return; -+ } -+ -+ krp = (struct cryptkop *)callbackTag; -+ -+ if (NULL == pOpData) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "Operation Data is NULL\n", __FUNCTION__); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ pSignData = (CpaCyDsaRSSignOpData *) pOpData; -+ -+ if (NULL == pR) { -+ DPRINTK("%s(): Invalid input parameter - " -+ "pR sign is NULL\n", __FUNCTION__); -+ icp_ocfDrvFreeFlatBuffer(pS); -+ ICP_CACHE_FREE(drvDSARSSign_zone, pSignData); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ -+ if (NULL == pS) { -+ DPRINTK("%s(): Invalid input parameter - " -+ "pS sign is NULL\n", __FUNCTION__); -+ icp_ocfDrvFreeFlatBuffer(pR); -+ ICP_CACHE_FREE(drvDSARSSign_zone, pSignData); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ -+ if (CPA_STATUS_SUCCESS != status) { -+ APRINTK("%s(): LAC DSA RS Sign operation failed - " -+ "Operation Status = %d\n", __FUNCTION__, status); -+ krp->krp_status = ECANCELED; -+ } else { -+ krp->krp_status = CRYPTO_OP_SUCCESS; -+ -+ if (CPA_TRUE != protocolStatus) { -+ DPRINTK("%s(): LAC DSA RS Sign operation failed due " -+ "to protocol error\n", __FUNCTION__); -+ krp->krp_status = EIO; -+ } -+ } -+ -+ /* Swap bytes only when the callback status is successful and -+ protocolStatus is set to true */ -+ if (CPA_STATUS_SUCCESS == status && CPA_TRUE == protocolStatus) { -+ icp_ocfDrvSwapBytes(pR->pData, pR->dataLenInBytes); -+ icp_ocfDrvSwapBytes(pS->pData, pS->dataLenInBytes); -+ } -+ -+ icp_ocfDrvFreeFlatBuffer(pR); -+ icp_ocfDrvFreeFlatBuffer(pS); -+ memset(pSignData->K.pData, 0, pSignData->K.dataLenInBytes); -+ ICP_CACHE_FREE(drvDSARSSignKValue_zone, pSignData->K.pData); -+ memset(pSignData, 0, sizeof(CpaCyDsaRSSignOpData)); -+ ICP_CACHE_FREE(drvDSARSSign_zone, pSignData); -+ crypto_kdone(krp); -+ -+ return; -+} -+ -+/* Name : icp_ocfDrvDsaVerifyCallback -+ * -+ * Description : When this function returns it signifies that the LAC -+ * component has completed the DSA Verify operation. -+ */ -+static void -+icp_ocfDrvDsaVerifyCallBack(void *callbackTag, -+ CpaStatus status, -+ void *pOpData, CpaBoolean verifyStatus) -+{ -+ -+ struct cryptkop *krp = NULL; -+ CpaCyDsaVerifyOpData *pVerData = NULL; -+ -+ if (NULL == callbackTag) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "callbackTag data is NULL\n", __FUNCTION__); -+ return; -+ } -+ -+ krp = (struct cryptkop *)callbackTag; -+ -+ if (NULL == pOpData) { -+ DPRINTK("%s(): Invalid input parameters - " -+ "Operation Data is NULL\n", __FUNCTION__); -+ krp->krp_status = ECANCELED; -+ crypto_kdone(krp); -+ return; -+ } -+ pVerData = (CpaCyDsaVerifyOpData *) pOpData; -+ -+ if (CPA_STATUS_SUCCESS != status) { -+ APRINTK("%s(): LAC DSA Verify operation failed - " -+ "Operation Status = %d\n", __FUNCTION__, status); -+ krp->krp_status = ECANCELED; -+ } else { -+ krp->krp_status = CRYPTO_OP_SUCCESS; -+ -+ if (CPA_TRUE != verifyStatus) { -+ DPRINTK("%s(): DSA signature invalid\n", __FUNCTION__); -+ krp->krp_status = EIO; -+ } -+ } -+ -+ /* Swap bytes only when the callback status is successful and -+ verifyStatus is set to true */ -+ /*Just swapping back the key values for now. Possibly all -+ swapped buffers need to be reverted */ -+ if (CPA_STATUS_SUCCESS == status && CPA_TRUE == verifyStatus) { -+ icp_ocfDrvSwapBytes(pVerData->R.pData, -+ pVerData->R.dataLenInBytes); -+ icp_ocfDrvSwapBytes(pVerData->S.pData, -+ pVerData->S.dataLenInBytes); -+ } -+ -+ memset(pVerData, 0, sizeof(CpaCyDsaVerifyOpData)); -+ ICP_CACHE_FREE(drvDSAVerify_zone, pVerData); -+ crypto_kdone(krp); -+ -+ return; -+} -diff -Nur linux-3.0.4.orig/crypto/ocf/ep80579/icp_common.c linux-3.0.4/crypto/ocf/ep80579/icp_common.c ---- linux-3.0.4.orig/crypto/ocf/ep80579/icp_common.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/ep80579/icp_common.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,773 @@ -+/************************************************************************* -+ * -+ * This file is provided under a dual BSD/GPLv2 license. When using or -+ * redistributing this file, you may do so under either license. -+ * -+ * GPL LICENSE SUMMARY -+ * -+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of version 2 of the GNU General Public License as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. -+ * The full GNU General Public License is included in this distribution -+ * in the file called LICENSE.GPL. -+ * -+ * Contact Information: -+ * Intel Corporation -+ * -+ * BSD LICENSE -+ * -+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * * Neither the name of Intel Corporation nor the names of its -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * -+ * version: Security.L.1.0.2-229 -+ * -+ ***************************************************************************/ -+ -+/* -+ * An OCF module that uses Intel® QuickAssist Integrated Accelerator to do the -+ * crypto. -+ * -+ * This driver requires the ICP Access Library that is available from Intel in -+ * order to operate. -+ */ -+ -+#include "icp_ocf.h" -+ -+#define ICP_OCF_COMP_NAME "ICP_OCF" -+#define ICP_OCF_VER_MAIN (2) -+#define ICP_OCF_VER_MJR (1) -+#define ICP_OCF_VER_MNR (0) -+ -+#define MAX_DEREG_RETRIES (100) -+#define DEFAULT_DEREG_RETRIES (10) -+#define DEFAULT_DEREG_DELAY_IN_JIFFIES (10) -+ -+/* This defines the maximum number of sessions possible between OCF -+ and the OCF EP80579 Driver. If set to zero, there is no limit. */ -+#define DEFAULT_OCF_TO_DRV_MAX_SESSION_COUNT (0) -+#define NUM_SUPPORTED_CAPABILITIES (21) -+ -+/*Slab zone names*/ -+#define ICP_SESSION_DATA_NAME "icp_ocf.SesDat" -+#define ICP_OP_DATA_NAME "icp_ocf.OpDat" -+#define ICP_DH_NAME "icp_ocf.DH" -+#define ICP_MODEXP_NAME "icp_ocf.ModExp" -+#define ICP_RSA_DECRYPT_NAME "icp_ocf.RSAdec" -+#define ICP_RSA_PKEY_NAME "icp_ocf.RSApk" -+#define ICP_DSA_SIGN_NAME "icp_ocf.DSAsg" -+#define ICP_DSA_VER_NAME "icp_ocf.DSAver" -+#define ICP_RAND_VAL_NAME "icp_ocf.DSArnd" -+#define ICP_FLAT_BUFF_NAME "icp_ocf.FB" -+ -+/*Slabs zones*/ -+icp_kmem_cache drvSessionData_zone = NULL; -+icp_kmem_cache drvOpData_zone = NULL; -+icp_kmem_cache drvDH_zone = NULL; -+icp_kmem_cache drvLnModExp_zone = NULL; -+icp_kmem_cache drvRSADecrypt_zone = NULL; -+icp_kmem_cache drvRSAPrivateKey_zone = NULL; -+icp_kmem_cache drvDSARSSign_zone = NULL; -+icp_kmem_cache drvDSARSSignKValue_zone = NULL; -+icp_kmem_cache drvDSAVerify_zone = NULL; -+ -+/*Slab zones for flatbuffers and bufferlist*/ -+icp_kmem_cache drvFlatBuffer_zone = NULL; -+ -+static inline int icp_cache_null_check(void) -+{ -+ return (drvSessionData_zone && drvOpData_zone -+ && drvDH_zone && drvLnModExp_zone && drvRSADecrypt_zone -+ && drvRSAPrivateKey_zone && drvDSARSSign_zone -+ && drvDSARSSign_zone && drvDSARSSignKValue_zone -+ && drvDSAVerify_zone && drvFlatBuffer_zone); -+} -+ -+/*Function to free all allocated slab caches before exiting the module*/ -+static void icp_ocfDrvFreeCaches(void); -+ -+int32_t icp_ocfDrvDriverId = INVALID_DRIVER_ID; -+ -+/* Module parameter - gives the number of times LAC deregistration shall be -+ re-tried */ -+int num_dereg_retries = DEFAULT_DEREG_RETRIES; -+ -+/* Module parameter - gives the delay time in jiffies before a LAC session -+ shall be attempted to be deregistered again */ -+int dereg_retry_delay_in_jiffies = DEFAULT_DEREG_DELAY_IN_JIFFIES; -+ -+/* Module parameter - gives the maximum number of sessions possible between -+ OCF and the OCF EP80579 Driver. If set to zero, there is no limit.*/ -+int max_sessions = DEFAULT_OCF_TO_DRV_MAX_SESSION_COUNT; -+ -+/* This is set when the module is removed from the system, no further -+ processing can take place if this is set */ -+icp_atomic_t icp_ocfDrvIsExiting = ICP_ATOMIC_INIT(0); -+ -+/* This is used to show how many lac sessions were not deregistered*/ -+icp_atomic_t lac_session_failed_dereg_count = ICP_ATOMIC_INIT(0); -+ -+/* This is used to track the number of registered sessions between OCF and -+ * and the OCF EP80579 driver, when max_session is set to value other than -+ * zero. This ensures that the max_session set for the OCF and the driver -+ * is equal to the LAC registered sessions */ -+icp_atomic_t num_ocf_to_drv_registered_sessions = ICP_ATOMIC_INIT(0); -+ -+/* Head of linked list used to store session data */ -+icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead; -+icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead_FreeMemList; -+ -+icp_spinlock_t icp_ocfDrvSymSessInfoListSpinlock; -+ -+/*Below pointer is only used in linux, FreeBSD uses the name to -+create its own variable name*/ -+icp_workqueue *icp_ocfDrvFreeLacSessionWorkQ = NULL; -+ICP_WORKQUEUE_DEFINE_THREAD(icp_ocfDrvFreeLacSessionWorkQ); -+ -+struct icp_drvBuffListInfo defBuffListInfo; -+ -+/* Name : icp_ocfDrvInit -+ * -+ * Description : This function will register all the symmetric and asymmetric -+ * functionality that will be accelerated by the hardware. It will also -+ * get a unique driver ID from the OCF and initialise all slab caches -+ */ -+ICP_MODULE_INIT_FUNC(icp_ocfDrvInit) -+{ -+ int ocfStatus = 0; -+ -+ IPRINTK("=== %s ver %d.%d.%d ===\n", ICP_OCF_COMP_NAME, -+ ICP_OCF_VER_MAIN, ICP_OCF_VER_MJR, ICP_OCF_VER_MNR); -+ -+ if (MAX_DEREG_RETRIES < num_dereg_retries) { -+ EPRINTK("Session deregistration retry count set to greater " -+ "than %d", MAX_DEREG_RETRIES); -+ icp_module_return_code(EINVAL); -+ } -+ -+ /* Initialize and Start the Cryptographic component */ -+ if (CPA_STATUS_SUCCESS != -+ cpaCyStartInstance(CPA_INSTANCE_HANDLE_SINGLE)) { -+ EPRINTK("Failed to initialize and start the instance " -+ "of the Cryptographic component.\n"); -+ return icp_module_return_code(EINVAL); -+ } -+ -+ icp_spin_lock_init(&icp_ocfDrvSymSessInfoListSpinlock); -+ -+ /* Set the default size of BufferList to allocate */ -+ memset(&defBuffListInfo, 0, sizeof(struct icp_drvBuffListInfo)); -+ if (ICP_OCF_DRV_STATUS_SUCCESS != -+ icp_ocfDrvBufferListMemInfo(ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS, -+ &defBuffListInfo)) { -+ EPRINTK("Failed to get bufferlist memory info.\n"); -+ return icp_module_return_code(ENOMEM); -+ } -+ -+ /*Register OCF EP80579 Driver with OCF */ -+ icp_ocfDrvDriverId = ICP_CRYPTO_GET_DRIVERID(); -+ -+ if (icp_ocfDrvDriverId < 0) { -+ EPRINTK("%s : ICP driver failed to register with OCF!\n", -+ __FUNCTION__); -+ return icp_module_return_code(ENODEV); -+ } -+ -+ /*Create all the slab caches used by the OCF EP80579 Driver */ -+ drvSessionData_zone = -+ ICP_CACHE_CREATE(ICP_SESSION_DATA_NAME, struct icp_drvSessionData); -+ -+ /* -+ * Allocation of the OpData includes the allocation space for meta data. -+ * The memory after the opData structure is reserved for this meta data. -+ */ -+ drvOpData_zone = -+ icp_kmem_cache_create(ICP_OP_DATA_NAME, -+ sizeof(struct icp_drvOpData) + -+ defBuffListInfo.metaSize, -+ ICP_KERNEL_CACHE_ALIGN, -+ ICP_KERNEL_CACHE_NOINIT); -+ -+ drvDH_zone = ICP_CACHE_CREATE(ICP_DH_NAME, CpaCyDhPhase1KeyGenOpData); -+ -+ drvLnModExp_zone = -+ ICP_CACHE_CREATE(ICP_MODEXP_NAME, CpaCyLnModExpOpData); -+ -+ drvRSADecrypt_zone = -+ ICP_CACHE_CREATE(ICP_RSA_DECRYPT_NAME, CpaCyRsaDecryptOpData); -+ -+ drvRSAPrivateKey_zone = -+ ICP_CACHE_CREATE(ICP_RSA_PKEY_NAME, CpaCyRsaPrivateKey); -+ -+ drvDSARSSign_zone = -+ ICP_CACHE_CREATE(ICP_DSA_SIGN_NAME, CpaCyDsaRSSignOpData); -+ -+ /*too awkward to use a macro here */ -+ drvDSARSSignKValue_zone = -+ ICP_CACHE_CREATE(ICP_RAND_VAL_NAME, -+ DSA_RS_SIGN_PRIMEQ_SIZE_IN_BYTES); -+ -+ drvDSAVerify_zone = -+ ICP_CACHE_CREATE(ICP_DSA_VER_NAME, CpaCyDsaVerifyOpData); -+ -+ drvFlatBuffer_zone = -+ ICP_CACHE_CREATE(ICP_FLAT_BUFF_NAME, CpaFlatBuffer); -+ -+ if (0 == icp_cache_null_check()) { -+ icp_ocfDrvFreeCaches(); -+ EPRINTK("%s() line %d: Not enough memory!\n", -+ __FUNCTION__, __LINE__); -+ return ENOMEM; -+ } -+ -+ /* Register the ICP symmetric crypto support. */ -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_NULL_CBC, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_DES_CBC, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_3DES_CBC, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_AES_CBC, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_ARC4, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_MD5, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_MD5_HMAC, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA1, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA1_HMAC, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_256, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_256_HMAC, -+ ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_384, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_384_HMAC, -+ ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_512, ocfStatus); -+ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_512_HMAC, -+ ocfStatus); -+ -+ /* Register the ICP asymmetric algorithm support */ -+ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_DH_COMPUTE_KEY, -+ ocfStatus); -+ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_MOD_EXP, ocfStatus); -+ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_MOD_EXP_CRT, ocfStatus); -+ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_DSA_SIGN, ocfStatus); -+ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_DSA_VERIFY, ocfStatus); -+ -+ /* Register the ICP random number generator support */ -+ ICP_REG_RAND_WITH_OCF(icp_ocfDrvDriverId, -+ icp_ocfDrvReadRandom, NULL, ocfStatus); -+ -+ if (OCF_ZERO_FUNCTIONALITY_REGISTERED == ocfStatus) { -+ DPRINTK("%s: Failed to register any device capabilities\n", -+ __FUNCTION__); -+ icp_ocfDrvFreeCaches(); -+ icp_ocfDrvDriverId = INVALID_DRIVER_ID; -+ return icp_module_return_code(ECANCELED); -+ } -+ -+ DPRINTK("%s: Registered %d of %d device capabilities\n", -+ __FUNCTION__, ocfStatus, NUM_SUPPORTED_CAPABILITIES); -+ -+ /*Session data linked list used during module exit */ -+ ICP_INIT_LIST_HEAD(&icp_ocfDrvGlobalSymListHead); -+ ICP_INIT_LIST_HEAD(&icp_ocfDrvGlobalSymListHead_FreeMemList); -+ -+ ICP_WORKQUEUE_CREATE(icp_ocfDrvFreeLacSessionWorkQ, "icpwq"); -+ if (ICP_WORKQUEUE_NULL_CHECK(icp_ocfDrvFreeLacSessionWorkQ)) { -+ EPRINTK("%s: Failed to create single " -+ "thread workqueue\n", __FUNCTION__); -+ icp_ocfDrvFreeCaches(); -+ icp_ocfDrvDriverId = INVALID_DRIVER_ID; -+ return icp_module_return_code(ENOMEM); -+ } -+ -+ return icp_module_return_code(0); -+} -+ -+/* Name : icp_ocfDrvExit -+ * -+ * Description : This function will deregister all the symmetric sessions -+ * registered with the LAC component. It will also deregister all symmetric -+ * and asymmetric functionality that can be accelerated by the hardware via OCF -+ * and random number generation if it is enabled. -+ */ -+ICP_MODULE_EXIT_FUNC(icp_ocfDrvExit) -+{ -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ struct icp_drvSessionData *sessionData = NULL; -+ struct icp_drvSessionData *tempSessionData = NULL; -+ int i, remaining_delay_time_in_jiffies = 0; -+ -+ /* For FreeBSD the invariant macro below makes function to return */ -+ /* with EBUSY value in the case of any session which has been regi- */ -+ /* stered with LAC not being deregistered. */ -+ /* The Linux implementation is empty since it is purely to compensate */ -+ /* for a limitation of the FreeBSD 7.1 Opencrypto framework. */ -+ -+ ICP_MODULE_EXIT_INV(); -+ -+ /* There is a possibility of a process or new session command being */ -+ /* sent before this variable is incremented. The aim of this variable */ -+ /* is to stop a loop of calls creating a deadlock situation which */ -+ /* would prevent the driver from exiting. */ -+ icp_atomic_set(&icp_ocfDrvIsExiting, 1); -+ -+ /*Existing sessions will be routed to another driver after these calls */ -+ crypto_unregister_all(icp_ocfDrvDriverId); -+ crypto_runregister_all(icp_ocfDrvDriverId); -+ -+ if (ICP_WORKQUEUE_NULL_CHECK(icp_ocfDrvFreeLacSessionWorkQ)) { -+ DPRINTK("%s: workqueue already " -+ "destroyed, therefore module exit " -+ " function already called. Exiting.\n", __FUNCTION__); -+ return ICP_MODULE_EXIT_FUNC_RETURN_VAL; -+ } -+ /*If any sessions are waiting to be deregistered, do that. This also -+ flushes the work queue */ -+ ICP_WORKQUEUE_DESTROY(icp_ocfDrvFreeLacSessionWorkQ); -+ -+ /*ENTER CRITICAL SECTION */ -+ icp_spin_lockbh_lock(&icp_ocfDrvSymSessInfoListSpinlock); -+ -+ ICP_LIST_FOR_EACH_ENTRY_SAFE(tempSessionData, sessionData, -+ &icp_ocfDrvGlobalSymListHead, listNode) { -+ for (i = 0; i < num_dereg_retries; i++) { -+ /*No harm if bad input - LAC will handle error cases */ -+ if (ICP_SESSION_RUNNING == tempSessionData->inUse) { -+ lacStatus = -+ cpaCySymRemoveSession -+ (CPA_INSTANCE_HANDLE_SINGLE, -+ tempSessionData->sessHandle); -+ if (CPA_STATUS_SUCCESS == lacStatus) { -+ /* Succesfully deregistered */ -+ break; -+ } else if (CPA_STATUS_RETRY != lacStatus) { -+ icp_atomic_inc -+ (&lac_session_failed_dereg_count); -+ break; -+ } -+ -+ /*schedule_timout returns the time left for completion if -+ * this task is set to TASK_INTERRUPTIBLE */ -+ remaining_delay_time_in_jiffies = -+ dereg_retry_delay_in_jiffies; -+ while (0 > remaining_delay_time_in_jiffies) { -+ remaining_delay_time_in_jiffies = -+ icp_schedule_timeout -+ (&icp_ocfDrvSymSessInfoListSpinlock, -+ remaining_delay_time_in_jiffies); -+ } -+ -+ DPRINTK -+ ("%s(): Retry %d to deregistrate the session\n", -+ __FUNCTION__, i); -+ } -+ } -+ -+ /*remove from current list */ -+ ICP_LIST_DEL(tempSessionData, listNode); -+ /*add to free mem linked list */ -+ ICP_LIST_ADD(tempSessionData, -+ &icp_ocfDrvGlobalSymListHead_FreeMemList, -+ listNode); -+ -+ } -+ -+ /*EXIT CRITICAL SECTION */ -+ icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock); -+ -+ /*set back to initial values */ -+ sessionData = NULL; -+ /*still have a reference in our list! */ -+ tempSessionData = NULL; -+ /*free memory */ -+ -+ ICP_LIST_FOR_EACH_ENTRY_SAFE(tempSessionData, sessionData, -+ &icp_ocfDrvGlobalSymListHead_FreeMemList, -+ listNode) { -+ -+ ICP_LIST_DEL(tempSessionData, listNode); -+ /* Free allocated CpaCySymSessionCtx */ -+ if (NULL != tempSessionData->sessHandle) { -+ icp_kfree(tempSessionData->sessHandle); -+ } -+ memset(tempSessionData, 0, sizeof(struct icp_drvSessionData)); -+ ICP_CACHE_FREE(drvSessionData_zone, tempSessionData); -+ } -+ -+ if (0 != icp_atomic_read(&lac_session_failed_dereg_count)) { -+ DPRINTK("%s(): %d LAC sessions were not deregistered " -+ "correctly. This is not a clean exit! \n", -+ __FUNCTION__, -+ icp_atomic_read(&lac_session_failed_dereg_count)); -+ } -+ -+ icp_ocfDrvFreeCaches(); -+ icp_ocfDrvDriverId = INVALID_DRIVER_ID; -+ -+ icp_spin_lock_destroy(&icp_ocfDrvSymSessInfoListSpinlock); -+ -+ /* Shutdown the Cryptographic component */ -+ lacStatus = cpaCyStopInstance(CPA_INSTANCE_HANDLE_SINGLE); -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ DPRINTK("%s(): Failed to stop instance of the " -+ "Cryptographic component.(status == %d)\n", -+ __FUNCTION__, lacStatus); -+ } -+ -+ return ICP_MODULE_EXIT_FUNC_RETURN_VAL; -+} -+ -+/* Name : icp_ocfDrvFreeCaches -+ * -+ * Description : This function deregisters all slab caches -+ */ -+static void icp_ocfDrvFreeCaches(void) -+{ -+ icp_atomic_set(&icp_ocfDrvIsExiting, 1); -+ -+ /*Sym Zones */ -+ ICP_CACHE_DESTROY(drvSessionData_zone); -+ ICP_CACHE_DESTROY(drvOpData_zone); -+ -+ /*Asym zones */ -+ ICP_CACHE_DESTROY(drvDH_zone); -+ ICP_CACHE_DESTROY(drvLnModExp_zone); -+ ICP_CACHE_DESTROY(drvRSADecrypt_zone); -+ ICP_CACHE_DESTROY(drvRSAPrivateKey_zone); -+ ICP_CACHE_DESTROY(drvDSARSSignKValue_zone); -+ ICP_CACHE_DESTROY(drvDSARSSign_zone); -+ ICP_CACHE_DESTROY(drvDSAVerify_zone); -+ -+ /*FlatBuffer and BufferList Zones */ -+ ICP_CACHE_DESTROY(drvFlatBuffer_zone); -+ -+} -+ -+/* Name : icp_ocfDrvDeregRetry -+ * -+ * Description : This function will try to farm the session deregistration -+ * off to a work queue. If it fails, nothing more can be done and it -+ * returns an error -+ */ -+int icp_ocfDrvDeregRetry(CpaCySymSessionCtx sessionToDeregister) -+{ -+ struct icp_ocfDrvFreeLacSession *workstore = NULL; -+ -+ DPRINTK("%s(): Retry - Deregistering session (%p)\n", -+ __FUNCTION__, sessionToDeregister); -+ -+ /*make sure the session is not available to be allocated during this -+ process */ -+ icp_atomic_inc(&lac_session_failed_dereg_count); -+ -+ /*Farm off to work queue */ -+ workstore = -+ icp_kmalloc(sizeof(struct icp_ocfDrvFreeLacSession), ICP_M_NOWAIT); -+ if (NULL == workstore) { -+ DPRINTK("%s(): unable to free session - no memory available " -+ "for work queue\n", __FUNCTION__); -+ return ENOMEM; -+ } -+ -+ workstore->sessionToDeregister = sessionToDeregister; -+ -+ icp_init_work(&(workstore->work), -+ icp_ocfDrvDeferedFreeLacSessionTaskFn, workstore); -+ -+ ICP_WORKQUEUE_ENQUEUE(icp_ocfDrvFreeLacSessionWorkQ, -+ &(workstore->work)); -+ -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+ -+} -+ -+/* Name : icp_ocfDrvDeferedFreeLacSessionProcess -+ * -+ * Description : This function will retry (module input parameter) -+ * 'num_dereg_retries' times to deregister any symmetric session that recieves a -+ * CPA_STATUS_RETRY message from the LAC component. This function is run in -+ * Thread context because it is called from a worker thread -+ */ -+void icp_ocfDrvDeferedFreeLacSessionProcess(void *arg) -+{ -+ struct icp_ocfDrvFreeLacSession *workstore = NULL; -+ CpaCySymSessionCtx sessionToDeregister = NULL; -+ int i = 0; -+ int remaining_delay_time_in_jiffies = 0; -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ -+ workstore = (struct icp_ocfDrvFreeLacSession *)arg; -+ if (NULL == workstore) { -+ DPRINTK("%s() function called with null parameter \n", -+ __FUNCTION__); -+ return; -+ } -+ -+ sessionToDeregister = workstore->sessionToDeregister; -+ icp_kfree(workstore); -+ -+ /*if exiting, give deregistration one more blast only */ -+ if (icp_atomic_read(&icp_ocfDrvIsExiting) == CPA_TRUE) { -+ lacStatus = cpaCySymRemoveSession(CPA_INSTANCE_HANDLE_SINGLE, -+ sessionToDeregister); -+ -+ if (lacStatus != CPA_STATUS_SUCCESS) { -+ DPRINTK("%s() Failed to Dereg LAC session %p " -+ "during module exit\n", __FUNCTION__, -+ sessionToDeregister); -+ return; -+ } -+ -+ icp_atomic_dec(&lac_session_failed_dereg_count); -+ return; -+ } -+ -+ for (i = 0; i <= num_dereg_retries; i++) { -+ lacStatus = cpaCySymRemoveSession(CPA_INSTANCE_HANDLE_SINGLE, -+ sessionToDeregister); -+ -+ if (lacStatus == CPA_STATUS_SUCCESS) { -+ icp_atomic_dec(&lac_session_failed_dereg_count); -+ return; -+ } -+ if (lacStatus != CPA_STATUS_RETRY) { -+ DPRINTK("%s() Failed to deregister session - lacStatus " -+ " = %d", __FUNCTION__, lacStatus); -+ break; -+ } -+ -+ /*schedule_timout returns the time left for completion if this -+ task is set to TASK_INTERRUPTIBLE */ -+ remaining_delay_time_in_jiffies = dereg_retry_delay_in_jiffies; -+ while (0 < remaining_delay_time_in_jiffies) { -+ remaining_delay_time_in_jiffies = -+ icp_schedule_timeout(NULL, -+ remaining_delay_time_in_jiffies); -+ } -+ -+ } -+ -+ DPRINTK("%s(): Unable to deregister session\n", __FUNCTION__); -+ DPRINTK("%s(): Number of unavailable LAC sessions = %d\n", __FUNCTION__, -+ icp_atomic_read(&lac_session_failed_dereg_count)); -+} -+ -+/* Name : icp_ocfDrvPtrAndLenToFlatBuffer -+ * -+ * Description : This function converts a "pointer and length" buffer -+ * structure to Fredericksburg Flat Buffer (CpaFlatBuffer) format. -+ * -+ * This function assumes that the data passed in are valid. -+ */ -+inline void -+icp_ocfDrvPtrAndLenToFlatBuffer(void *pData, uint32_t len, -+ CpaFlatBuffer * pFlatBuffer) -+{ -+ pFlatBuffer->pData = pData; -+ pFlatBuffer->dataLenInBytes = len; -+} -+ -+/* Name : icp_ocfDrvPtrAndLenToBufferList -+ * -+ * Description : This function converts a "pointer and length" buffer -+ * structure to Fredericksburg Scatter/Gather Buffer (CpaBufferList) format. -+ * -+ * This function assumes that the data passed in are valid. -+ */ -+inline void -+icp_ocfDrvPtrAndLenToBufferList(void *pDataIn, uint32_t length, -+ CpaBufferList * pBufferList) -+{ -+ pBufferList->numBuffers = 1; -+ pBufferList->pBuffers->pData = pDataIn; -+ pBufferList->pBuffers->dataLenInBytes = length; -+} -+ -+/* Name : icp_ocfDrvBufferListToPtrAndLen -+ * -+ * Description : This function converts Fredericksburg Scatter/Gather Buffer -+ * (CpaBufferList) format to a "pointer and length" buffer structure. -+ * -+ * This function assumes that the data passed in are valid. -+ */ -+inline void -+icp_ocfDrvBufferListToPtrAndLen(CpaBufferList * pBufferList, -+ void **ppDataOut, uint32_t * pLength) -+{ -+ *ppDataOut = pBufferList->pBuffers->pData; -+ *pLength = pBufferList->pBuffers->dataLenInBytes; -+} -+ -+/* Name : icp_ocfDrvBufferListMemInfo -+ * -+ * Description : This function will set the number of flat buffers in -+ * bufferlist, the size of memory to allocate for the pPrivateMetaData -+ * member of the CpaBufferList. -+ */ -+int -+icp_ocfDrvBufferListMemInfo(uint16_t numBuffers, -+ struct icp_drvBuffListInfo *buffListInfo) -+{ -+ buffListInfo->numBuffers = numBuffers; -+ -+ if (CPA_STATUS_SUCCESS != -+ cpaCyBufferListGetMetaSize(CPA_INSTANCE_HANDLE_SINGLE, -+ buffListInfo->numBuffers, -+ &(buffListInfo->metaSize))) { -+ EPRINTK("%s() Failed to get buffer list meta size.\n", -+ __FUNCTION__); -+ return ICP_OCF_DRV_STATUS_FAIL; -+ } -+ -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+} -+ -+/* Name : icp_ocfDrvFreeFlatBuffer -+ * -+ * Description : This function will deallocate flat buffer. -+ */ -+inline void icp_ocfDrvFreeFlatBuffer(CpaFlatBuffer * pFlatBuffer) -+{ -+ if (pFlatBuffer != NULL) { -+ memset(pFlatBuffer, 0, sizeof(CpaFlatBuffer)); -+ ICP_CACHE_FREE(drvFlatBuffer_zone, pFlatBuffer); -+ } -+} -+ -+/* Name : icp_ocfDrvAllocMetaData -+ * -+ * Description : This function will allocate memory for the -+ * pPrivateMetaData member of CpaBufferList. -+ */ -+inline int -+icp_ocfDrvAllocMetaData(CpaBufferList * pBufferList, -+ struct icp_drvOpData *pOpData) -+{ -+ Cpa32U metaSize = 0; -+ -+ if (pBufferList->numBuffers <= ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) { -+ uint8_t *pOpDataStartAddr = (uint8_t *) pOpData; -+ -+ if (0 == defBuffListInfo.metaSize) { -+ pBufferList->pPrivateMetaData = NULL; -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+ } -+ /* -+ * The meta data allocation has been included as part of the -+ * op data. It has been pre-allocated in memory just after the -+ * icp_drvOpData structure. -+ */ -+ pBufferList->pPrivateMetaData = (void *)(pOpDataStartAddr + -+ sizeof(struct -+ icp_drvOpData)); -+ } else { -+ if (CPA_STATUS_SUCCESS != -+ cpaCyBufferListGetMetaSize(CPA_INSTANCE_HANDLE_SINGLE, -+ pBufferList->numBuffers, -+ &metaSize)) { -+ EPRINTK("%s() Failed to get buffer list meta size.\n", -+ __FUNCTION__); -+ return ICP_OCF_DRV_STATUS_FAIL; -+ } -+ -+ if (0 == metaSize) { -+ pBufferList->pPrivateMetaData = NULL; -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+ } -+ -+ pBufferList->pPrivateMetaData = -+ icp_kmalloc(metaSize, ICP_M_NOWAIT); -+ } -+ if (NULL == pBufferList->pPrivateMetaData) { -+ EPRINTK("%s() Failed to allocate pPrivateMetaData.\n", -+ __FUNCTION__); -+ return ICP_OCF_DRV_STATUS_FAIL; -+ } -+ -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+} -+ -+/* Name : icp_ocfDrvFreeMetaData -+ * -+ * Description : This function will deallocate pPrivateMetaData memory. -+ */ -+inline void icp_ocfDrvFreeMetaData(CpaBufferList * pBufferList) -+{ -+ if (NULL == pBufferList->pPrivateMetaData) { -+ return; -+ } -+ -+ /* -+ * Only free the meta data if the BufferList has more than -+ * ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS number of buffers. -+ * Otherwise, the meta data shall be freed when the icp_drvOpData is -+ * freed. -+ */ -+ if (ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS < pBufferList->numBuffers) { -+ icp_kfree(pBufferList->pPrivateMetaData); -+ } -+} -+ -+/* Module declaration, init and exit functions */ -+ICP_DECLARE_MODULE(icp_ocf, icp_ocfDrvInit, icp_ocfDrvExit); -+ICP_MODULE_DESCRIPTION("OCF Driver for Intel Quick Assist crypto acceleration"); -+ICP_MODULE_VERSION(icp_ocf, ICP_OCF_VER_MJR); -+ICP_MODULE_LICENSE("Dual BSD/GPL"); -+ICP_MODULE_AUTHOR("Intel"); -+ -+/* Module parameters */ -+ICP_MODULE_PARAM_INT(icp_ocf, num_dereg_retries, -+ "Number of times to retry LAC Sym Session Deregistration. " -+ "Default 10, Max 100"); -+ICP_MODULE_PARAM_INT(icp_ocf, dereg_retry_delay_in_jiffies, "Delay in jiffies " -+ "(added to a schedule() function call) before a LAC Sym " -+ "Session Dereg is retried. Default 10"); -+ICP_MODULE_PARAM_INT(icp_ocf, max_sessions, -+ "This sets the maximum number of sessions " -+ "between OCF and this driver. If this value is set to zero," -+ "max session count checking is disabled. Default is zero(0)"); -+ -+/* Module dependencies */ -+#define MODULE_MIN_VER 1 -+#define CRYPTO_MAX_VER 3 -+#define LAC_MAX_VER 2 -+ -+ICP_MODULE_DEPEND(icp_ocf, crypto, MODULE_MIN_VER, MODULE_MIN_VER, -+ CRYPTO_MAX_VER); -+ICP_MODULE_DEPEND(icp_ocf, cryptodev, MODULE_MIN_VER, MODULE_MIN_VER, -+ CRYPTO_MAX_VER); -+ICP_MODULE_DEPEND(icp_ocf, icp_crypto, MODULE_MIN_VER, MODULE_MIN_VER, -+ LAC_MAX_VER); -diff -Nur linux-3.0.4.orig/crypto/ocf/ep80579/icp_ocf.h linux-3.0.4/crypto/ocf/ep80579/icp_ocf.h ---- linux-3.0.4.orig/crypto/ocf/ep80579/icp_ocf.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/ep80579/icp_ocf.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,376 @@ -+/*************************************************************************** -+ * -+ * This file is provided under a dual BSD/GPLv2 license. When using or -+ * redistributing this file, you may do so under either license. -+ * -+ * GPL LICENSE SUMMARY -+ * -+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of version 2 of the GNU General Public License as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. -+ * The full GNU General Public License is included in this distribution -+ * in the file called LICENSE.GPL. -+ * -+ * Contact Information: -+ * Intel Corporation -+ * -+ * BSD LICENSE -+ * -+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * * Neither the name of Intel Corporation nor the names of its -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * -+ * version: Security.L.1.0.2-229 -+ * -+ ***************************************************************************/ -+ -+/* -+ * OCF driver header file for the Intel ICP processor. -+ */ -+ -+#ifndef ICP_OCF_H_ -+#define ICP_OCF_H_ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "icp_os.h" -+ -+#define NUM_BITS_IN_BYTE (8) -+#define NUM_BITS_IN_BYTE_MINUS_ONE (NUM_BITS_IN_BYTE -1) -+#define INVALID_DRIVER_ID (-1) -+#define RETURN_RAND_NUM_GEN_FAILED (-1) -+ -+/*This is the max block cipher initialisation vector*/ -+#define MAX_IV_LEN_IN_BYTES (20) -+/*This is used to check whether the OCF to this driver session limit has -+ been disabled*/ -+#define NO_OCF_TO_DRV_MAX_SESSIONS (0) -+ -+/*OCF values mapped here*/ -+#define ICP_SHA1_DIGEST_SIZE_IN_BYTES (SHA1_HASH_LEN) -+#define ICP_SHA256_DIGEST_SIZE_IN_BYTES (SHA2_256_HASH_LEN) -+#define ICP_SHA384_DIGEST_SIZE_IN_BYTES (SHA2_384_HASH_LEN) -+#define ICP_SHA512_DIGEST_SIZE_IN_BYTES (SHA2_512_HASH_LEN) -+#define ICP_MD5_DIGEST_SIZE_IN_BYTES (MD5_HASH_LEN) -+#define ARC4_COUNTER_LEN (ARC4_BLOCK_LEN) -+ -+#define OCF_REGISTRATION_STATUS_SUCCESS (0) -+#define OCF_ZERO_FUNCTIONALITY_REGISTERED (0) -+#define ICP_OCF_DRV_NO_CRYPTO_PROCESS_ERROR (0) -+#define ICP_OCF_DRV_STATUS_SUCCESS (0) -+#define ICP_OCF_DRV_STATUS_FAIL (1) -+ -+/*Turn on/off debug options*/ -+#define ICP_OCF_PRINT_DEBUG_MESSAGES (0) -+#define ICP_OCF_PRINT_KERN_ALERT (1) -+#define ICP_OCF_PRINT_KERN_ERRS (1) -+ -+#if ICP_OCF_PRINT_DEBUG_MESSAGES == 1 -+#define DPRINTK(args...) \ -+{ \ -+ ICP_IPRINTK(args); \ -+} -+ -+#else //ICP_OCF_PRINT_DEBUG_MESSAGES == 1 -+ -+#define DPRINTK(args...) -+ -+#endif //ICP_OCF_PRINT_DEBUG_MESSAGES == 1 -+ -+#if ICP_OCF_PRINT_KERN_ALERT == 1 -+#define APRINTK(args...) \ -+{ \ -+ ICP_APRINTK(args); \ -+} -+ -+#else //ICP_OCF_PRINT_KERN_ALERT == 1 -+ -+#define APRINTK(args...) -+ -+#endif //ICP_OCF_PRINT_KERN_ALERT == 1 -+ -+#if ICP_OCF_PRINT_KERN_ERRS == 1 -+#define EPRINTK(args...) \ -+{ \ -+ ICP_EPRINTK(args); \ -+} -+ -+#else //ICP_OCF_PRINT_KERN_ERRS == 1 -+ -+#define EPRINTK(args...) -+ -+#endif //ICP_OCF_PRINT_KERN_ERRS == 1 -+ -+#define IPRINTK(args...) \ -+{ \ -+ ICP_IPRINTK(args); \ -+} -+ -+/*DSA Prime Q size in bytes (as defined in the standard) */ -+#define DSA_RS_SIGN_PRIMEQ_SIZE_IN_BYTES (20) -+ -+#define BITS_TO_BYTES(bytes, bits) \ -+ bytes = (bits + NUM_BITS_IN_BYTE_MINUS_ONE) / NUM_BITS_IN_BYTE -+ -+typedef enum { -+ ICP_OCF_DRV_ALG_CIPHER = 0, -+ ICP_OCF_DRV_ALG_HASH -+} icp_ocf_drv_alg_type_t; -+ -+typedef ICP_LIST_HEAD(icp_drvSessionListHead_s, -+ icp_drvSessionData) icp_drvSessionListHead_t; -+ -+/*Values used to derisk chances of performs being called against -+deregistered sessions (for which the slab page has been reclaimed) -+This is not a fix - since page frames are reclaimed from a slab, one cannot -+rely on that memory not being re-used by another app.*/ -+typedef enum { -+ ICP_SESSION_INITIALISED = 0x5C5C5C, -+ ICP_SESSION_RUNNING = 0x005C00, -+ ICP_SESSION_DEREGISTERED = 0xC5C5C5 -+} usage_derisk; -+ -+/* This struct is required for deferred session -+ deregistration as a work queue function can -+ only have one argument*/ -+struct icp_ocfDrvFreeLacSession { -+ CpaCySymSessionCtx sessionToDeregister; -+ icp_workstruct work; -+}; -+ -+/* -+This is the OCF<->OCF_DRV session object: -+ -+1.listNode -+ The first member is a listNode. These session objects are added to a linked -+ list in order to make it easier to remove them all at session exit time. -+ -+2.inUse -+ The second member is used to give the session object state and derisk the -+ possibility of OCF batch calls executing against a deregistered session (as -+ described above). -+ -+3.sessHandle -+ The third member is a LAC<->OCF_DRV session handle (initialised with the first -+ perform request for that session). -+ -+4.lacSessCtx -+ The fourth is the LAC session context. All the parameters for this structure -+ are only known when the first perform request for this session occurs. That is -+ why the OCF EP80579 Driver only registers a new LAC session at perform time -+*/ -+struct icp_drvSessionData { -+ ICP_LIST_ENTRY(icp_drvSessionData) listNode; -+ usage_derisk inUse; -+ CpaCySymSessionCtx sessHandle; -+ CpaCySymSessionSetupData lacSessCtx; -+}; -+ -+/* These are all defined in icp_common.c */ -+extern icp_atomic_t lac_session_failed_dereg_count; -+extern icp_atomic_t icp_ocfDrvIsExiting; -+extern icp_atomic_t num_ocf_to_drv_registered_sessions; -+ -+extern int32_t icp_ocfDrvDriverId; -+ -+extern icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead; -+extern icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead_FreeMemList; -+extern icp_workqueue *icp_ocfDrvFreeLacSessionWorkQ; -+extern icp_spinlock_t icp_ocfDrvSymSessInfoListSpinlock; -+ -+/*Slab zones for symettric functionality, instantiated in icp_common.c*/ -+extern icp_kmem_cache drvSessionData_zone; -+extern icp_kmem_cache drvOpData_zone; -+ -+/*Slabs zones for asymettric functionality, instantiated in icp_common.c*/ -+extern icp_kmem_cache drvDH_zone; -+extern icp_kmem_cache drvLnModExp_zone; -+extern icp_kmem_cache drvRSADecrypt_zone; -+extern icp_kmem_cache drvRSAPrivateKey_zone; -+extern icp_kmem_cache drvDSARSSign_zone; -+extern icp_kmem_cache drvDSARSSignKValue_zone; -+extern icp_kmem_cache drvDSAVerify_zone; -+ -+/* Module parameters defined in icp_cpmmon.c*/ -+ -+/* Module parameters - gives the number of times LAC deregistration shall be -+ re-tried */ -+extern int num_dereg_retries; -+ -+/* Module parameter - gives the delay time in jiffies before a LAC session -+ shall be attempted to be deregistered again */ -+extern int dereg_retry_delay_in_jiffies; -+ -+/* Module parameter - gives the maximum number of sessions possible between -+ OCF and the OCF EP80579 Driver. If set to zero, there is no limit.*/ -+extern int max_sessions; -+ -+/*Slab zones for flatbuffers and bufferlist*/ -+extern icp_kmem_cache drvFlatBuffer_zone; -+ -+#define ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS (16) -+ -+struct icp_drvBuffListInfo { -+ Cpa16U numBuffers; -+ Cpa32U metaSize; -+ Cpa32U metaOffset; -+ Cpa32U buffListSize; -+}; -+ -+extern struct icp_drvBuffListInfo defBuffListInfo; -+ -+/* This struct is used to keep a reference to the relevant node in the list -+ of sessionData structs, to the buffer type required by OCF and to the OCF -+ provided crp struct that needs to be returned. All this info is needed in -+ the callback function.*/ -+struct icp_drvOpData { -+ CpaCySymOpData lacOpData; -+ uint32_t digestSizeInBytes; -+ struct cryptop *crp; -+ uint8_t bufferType; -+ uint8_t ivData[MAX_IV_LEN_IN_BYTES]; -+ uint16_t numBufferListArray; -+ CpaBufferList srcBuffer; -+ CpaFlatBuffer bufferListArray[ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS]; -+ CpaBoolean verifyResult; -+}; -+ -+/* Create a new session between OCF and this driver*/ -+int icp_ocfDrvNewSession(icp_device_t dev, uint32_t * sild, -+ struct cryptoini *cri); -+ -+/* Free a session between this driver and the Quick Assist Framework*/ -+int icp_ocfDrvFreeLACSession(icp_device_t dev, uint64_t sid); -+ -+/* Defer freeing a Quick Assist session*/ -+void icp_ocfDrvDeferedFreeLacSessionProcess(void *arg); -+ -+/* Process OCF cryptographic request for a symmetric algorithm*/ -+int icp_ocfDrvSymProcess(icp_device_t dev, struct cryptop *crp, int hint); -+ -+/* Process OCF cryptographic request for an asymmetric algorithm*/ -+int icp_ocfDrvPkeProcess(icp_device_t dev, struct cryptkop *krp, int hint); -+ -+/* Populate a buffer with random data*/ -+int icp_ocfDrvReadRandom(void *arg, uint32_t * buf, int maxwords); -+ -+/* Retry Quick Assist session deregistration*/ -+int icp_ocfDrvDeregRetry(CpaCySymSessionCtx sessionToDeregister); -+ -+/* Convert an OS scatter gather list to a CPA buffer list*/ -+int icp_ocfDrvPacketBuffToBufferList(icp_packet_buffer_t * pPacketBuffer, -+ CpaBufferList * bufferList); -+ -+/* Convert a CPA buffer list to an OS scatter gather list*/ -+int icp_ocfDrvBufferListToPacketBuff(CpaBufferList * bufferList, -+ icp_packet_buffer_t ** pPacketBuffer); -+ -+/* Get the number of buffers in an OS scatter gather list*/ -+uint16_t icp_ocfDrvGetPacketBuffFrags(icp_packet_buffer_t * pPacketBuffer); -+ -+/* Convert a single OS buffer to a CPA Flat Buffer*/ -+void icp_ocfDrvSinglePacketBuffToFlatBuffer(icp_packet_buffer_t * pPacketBuffer, -+ CpaFlatBuffer * pFlatBuffer); -+ -+/* Add pointer and length to a CPA Flat Buffer structure*/ -+void icp_ocfDrvPtrAndLenToFlatBuffer(void *pData, uint32_t len, -+ CpaFlatBuffer * pFlatBuffer); -+ -+/* Convert pointer and length values to a CPA buffer list*/ -+void icp_ocfDrvPtrAndLenToBufferList(void *pDataIn, uint32_t length, -+ CpaBufferList * pBufferList); -+ -+/* Convert a CPA buffer list to pointer and length values*/ -+void icp_ocfDrvBufferListToPtrAndLen(CpaBufferList * pBufferList, -+ void **ppDataOut, uint32_t * pLength); -+ -+/* Set the number of flat buffers in bufferlist and the size of memory -+ to allocate for the pPrivateMetaData member of the CpaBufferList.*/ -+int icp_ocfDrvBufferListMemInfo(uint16_t numBuffers, -+ struct icp_drvBuffListInfo *buffListInfo); -+ -+/* Find pointer position of the digest within an OS scatter gather list*/ -+uint8_t *icp_ocfDrvPacketBufferDigestPointerFind(struct icp_drvOpData -+ *drvOpData, -+ int offsetInBytes, -+ uint32_t digestSizeInBytes); -+ -+/*This top level function is used to find a pointer to where a digest is -+ stored/needs to be inserted. */ -+uint8_t *icp_ocfDrvDigestPointerFind(struct icp_drvOpData *drvOpData, -+ struct cryptodesc *crp_desc); -+ -+/* Free a CPA flat buffer*/ -+void icp_ocfDrvFreeFlatBuffer(CpaFlatBuffer * pFlatBuffer); -+ -+/* This function will allocate memory for the pPrivateMetaData -+ member of CpaBufferList. */ -+int icp_ocfDrvAllocMetaData(CpaBufferList * pBufferList, -+ struct icp_drvOpData *pOpData); -+ -+/* Free data allocated for the pPrivateMetaData -+ member of CpaBufferList.*/ -+void icp_ocfDrvFreeMetaData(CpaBufferList * pBufferList); -+ -+#define ICP_CACHE_CREATE(cache_ID, cache_name) \ -+ icp_kmem_cache_create(cache_ID, sizeof(cache_name),ICP_KERNEL_CACHE_ALIGN,\ -+ ICP_KERNEL_CACHE_NOINIT) -+ -+#define ICP_CACHE_FREE(args...) \ -+ icp_kmem_cache_free (args) -+ -+#define ICP_CACHE_DESTROY(slab_zone)\ -+{\ -+ if(NULL != slab_zone){\ -+ icp_kmem_cache_destroy(slab_zone);\ -+ slab_zone = NULL;\ -+ }\ -+} -+ -+#endif -+/* ICP_OCF_H_ */ -diff -Nur linux-3.0.4.orig/crypto/ocf/ep80579/icp_sym.c linux-3.0.4/crypto/ocf/ep80579/icp_sym.c ---- linux-3.0.4.orig/crypto/ocf/ep80579/icp_sym.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/ep80579/icp_sym.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,1153 @@ -+/*************************************************************************** -+ * -+ * This file is provided under a dual BSD/GPLv2 license. When using or -+ * redistributing this file, you may do so under either license. -+ * -+ * GPL LICENSE SUMMARY -+ * -+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of version 2 of the GNU General Public License as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. -+ * The full GNU General Public License is included in this distribution -+ * in the file called LICENSE.GPL. -+ * -+ * Contact Information: -+ * Intel Corporation -+ * -+ * BSD LICENSE -+ * -+ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * * Neither the name of Intel Corporation nor the names of its -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * -+ * version: Security.L.1.0.2-229 -+ * -+ ***************************************************************************/ -+/* -+ * An OCF module that uses the API for Intel® QuickAssist Technology to do the -+ * cryptography. -+ * -+ * This driver requires the ICP Access Library that is available from Intel in -+ * order to operate. -+ */ -+ -+#include "icp_ocf.h" -+ -+/*This is the call back function for all symmetric cryptographic processes. -+ Its main functionality is to free driver crypto operation structure and to -+ call back to OCF*/ -+static void -+icp_ocfDrvSymCallBack(void *callbackTag, -+ CpaStatus status, -+ const CpaCySymOp operationType, -+ void *pOpData, -+ CpaBufferList * pDstBuffer, CpaBoolean verifyResult); -+ -+/*This function is used to extract crypto processing information from the OCF -+ inputs, so as that it may be passed onto LAC*/ -+static int -+icp_ocfDrvProcessDataSetup(struct icp_drvOpData *drvOpData, -+ struct cryptodesc *crp_desc); -+ -+/*This function checks whether the crp_desc argument pertains to a digest or a -+ cipher operation*/ -+static int icp_ocfDrvAlgCheck(struct cryptodesc *crp_desc); -+ -+/*This function copies all the passed in session context information and stores -+ it in a LAC context structure*/ -+static int -+icp_ocfDrvAlgorithmSetup(struct cryptoini *cri, -+ CpaCySymSessionSetupData * lacSessCtx); -+ -+/*This function is used to free an OCF->OCF_DRV session object*/ -+static void icp_ocfDrvFreeOCFSession(struct icp_drvSessionData *sessionData); -+ -+/*max IOV buffs supported in a UIO structure*/ -+#define NUM_IOV_SUPPORTED (1) -+ -+/* Name : icp_ocfDrvSymCallBack -+ * -+ * Description : When this function returns it signifies that the LAC -+ * component has completed the relevant symmetric operation. -+ * -+ * Notes : The callbackTag is a pointer to an icp_drvOpData. This memory -+ * object was passed to LAC for the cryptographic processing and contains all -+ * the relevant information for cleaning up buffer handles etc. so that the -+ * OCF EP80579 Driver portion of this crypto operation can be fully completed. -+ */ -+static void -+icp_ocfDrvSymCallBack(void *callbackTag, -+ CpaStatus status, -+ const CpaCySymOp operationType, -+ void *pOpData, -+ CpaBufferList * pDstBuffer, CpaBoolean verifyResult) -+{ -+ struct cryptop *crp = NULL; -+ struct icp_drvOpData *temp_drvOpData = -+ (struct icp_drvOpData *)callbackTag; -+ uint64_t *tempBasePtr = NULL; -+ uint32_t tempLen = 0; -+ -+ if (NULL == temp_drvOpData) { -+ DPRINTK("%s(): The callback from the LAC component" -+ " has failed due to Null userOpaque data" -+ "(status == %d).\n", __FUNCTION__, status); -+ DPRINTK("%s(): Unable to call OCF back! \n", __FUNCTION__); -+ return; -+ } -+ -+ crp = temp_drvOpData->crp; -+ crp->crp_etype = ICP_OCF_DRV_NO_CRYPTO_PROCESS_ERROR; -+ -+ if (NULL == pOpData) { -+ DPRINTK("%s(): The callback from the LAC component" -+ " has failed due to Null Symmetric Op data" -+ "(status == %d).\n", __FUNCTION__, status); -+ crp->crp_etype = ECANCELED; -+ crypto_done(crp); -+ return; -+ } -+ -+ if (NULL == pDstBuffer) { -+ DPRINTK("%s(): The callback from the LAC component" -+ " has failed due to Null Dst Bufferlist data" -+ "(status == %d).\n", __FUNCTION__, status); -+ crp->crp_etype = ECANCELED; -+ crypto_done(crp); -+ return; -+ } -+ -+ if (CPA_STATUS_SUCCESS == status) { -+ -+ if (temp_drvOpData->bufferType == ICP_CRYPTO_F_PACKET_BUF) { -+ if (ICP_OCF_DRV_STATUS_SUCCESS != -+ icp_ocfDrvBufferListToPacketBuff(pDstBuffer, -+ (icp_packet_buffer_t -+ **) -+ & (crp->crp_buf))) { -+ EPRINTK("%s(): BufferList to SkBuff " -+ "conversion error.\n", __FUNCTION__); -+ crp->crp_etype = EPERM; -+ } -+ } else { -+ icp_ocfDrvBufferListToPtrAndLen(pDstBuffer, -+ (void **)&tempBasePtr, -+ &tempLen); -+ crp->crp_olen = (int)tempLen; -+ } -+ -+ } else { -+ DPRINTK("%s(): The callback from the LAC component has failed" -+ "(status == %d).\n", __FUNCTION__, status); -+ -+ crp->crp_etype = ECANCELED; -+ } -+ -+ if (temp_drvOpData->numBufferListArray > -+ ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) { -+ icp_kfree(pDstBuffer->pBuffers); -+ } -+ icp_ocfDrvFreeMetaData(pDstBuffer); -+ ICP_CACHE_FREE(drvOpData_zone, temp_drvOpData); -+ -+ /* Invoke the OCF callback function */ -+ crypto_done(crp); -+ -+ return; -+} -+ -+/* Name : icp_ocfDrvNewSession -+ * -+ * Description : This function will create a new Driver<->OCF session -+ * -+ * Notes : LAC session registration happens during the first perform call. -+ * That is the first time we know all information about a given session. -+ */ -+int icp_ocfDrvNewSession(icp_device_t dev, uint32_t * sid, -+ struct cryptoini *cri) -+{ -+ struct icp_drvSessionData *sessionData = NULL; -+ uint32_t delete_session = 0; -+ -+ /* The SID passed in should be our driver ID. We can return the */ -+ /* local ID (LID) which is a unique identifier which we can use */ -+ /* to differentiate between the encrypt/decrypt LAC session handles */ -+ if (NULL == sid) { -+ EPRINTK("%s(): Invalid input parameters - NULL sid.\n", -+ __FUNCTION__); -+ return EINVAL; -+ } -+ -+ if (NULL == cri) { -+ EPRINTK("%s(): Invalid input parameters - NULL cryptoini.\n", -+ __FUNCTION__); -+ return EINVAL; -+ } -+ -+ if (icp_ocfDrvDriverId != *sid) { -+ EPRINTK("%s(): Invalid input parameters - bad driver ID\n", -+ __FUNCTION__); -+ EPRINTK("\t sid = 0x08%p \n \t cri = 0x08%p \n", sid, cri); -+ return EINVAL; -+ } -+ -+ sessionData = icp_kmem_cache_zalloc(drvSessionData_zone, ICP_M_NOWAIT); -+ if (NULL == sessionData) { -+ DPRINTK("%s():No memory for Session Data\n", __FUNCTION__); -+ return ENOMEM; -+ } -+ -+ /*ENTER CRITICAL SECTION */ -+ icp_spin_lockbh_lock(&icp_ocfDrvSymSessInfoListSpinlock); -+ /*put this check in the spinlock so no new sessions can be added to the -+ linked list when we are exiting */ -+ if (CPA_TRUE == icp_atomic_read(&icp_ocfDrvIsExiting)) { -+ delete_session++; -+ -+ } else if (NO_OCF_TO_DRV_MAX_SESSIONS != max_sessions) { -+ if (icp_atomic_read(&num_ocf_to_drv_registered_sessions) >= -+ (max_sessions - -+ icp_atomic_read(&lac_session_failed_dereg_count))) { -+ delete_session++; -+ } else { -+ icp_atomic_inc(&num_ocf_to_drv_registered_sessions); -+ /* Add to session data linked list */ -+ ICP_LIST_ADD(sessionData, &icp_ocfDrvGlobalSymListHead, -+ listNode); -+ } -+ -+ } else if (NO_OCF_TO_DRV_MAX_SESSIONS == max_sessions) { -+ ICP_LIST_ADD(sessionData, &icp_ocfDrvGlobalSymListHead, -+ listNode); -+ } -+ -+ sessionData->inUse = ICP_SESSION_INITIALISED; -+ -+ /*EXIT CRITICAL SECTION */ -+ icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock); -+ -+ if (delete_session) { -+ DPRINTK("%s():No Session handles available\n", __FUNCTION__); -+ ICP_CACHE_FREE(drvSessionData_zone, sessionData); -+ return EPERM; -+ } -+ -+ if (ICP_OCF_DRV_STATUS_SUCCESS != -+ icp_ocfDrvAlgorithmSetup(cri, &(sessionData->lacSessCtx))) { -+ DPRINTK("%s():algorithm not supported\n", __FUNCTION__); -+ icp_ocfDrvFreeOCFSession(sessionData); -+ return EINVAL; -+ } -+ -+ if (cri->cri_next) { -+ if (cri->cri_next->cri_next != NULL) { -+ DPRINTK("%s():only two chained algorithms supported\n", -+ __FUNCTION__); -+ icp_ocfDrvFreeOCFSession(sessionData); -+ return EPERM; -+ } -+ -+ if (ICP_OCF_DRV_STATUS_SUCCESS != -+ icp_ocfDrvAlgorithmSetup(cri->cri_next, -+ &(sessionData->lacSessCtx))) { -+ DPRINTK("%s():second algorithm not supported\n", -+ __FUNCTION__); -+ icp_ocfDrvFreeOCFSession(sessionData); -+ return EINVAL; -+ } -+ -+ sessionData->lacSessCtx.symOperation = -+ CPA_CY_SYM_OP_ALGORITHM_CHAINING; -+ } -+ -+ *sid = (uint32_t) sessionData; -+ -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+} -+ -+/* Name : icp_ocfDrvAlgorithmSetup -+ * -+ * Description : This function builds the session context data from the -+ * information supplied through OCF. Algorithm chain order and whether the -+ * session is Encrypt/Decrypt can only be found out at perform time however, so -+ * the session is registered with LAC at that time. -+ */ -+static int -+icp_ocfDrvAlgorithmSetup(struct cryptoini *cri, -+ CpaCySymSessionSetupData * lacSessCtx) -+{ -+ -+ lacSessCtx->sessionPriority = CPA_CY_PRIORITY_NORMAL; -+ -+ switch (cri->cri_alg) { -+ -+ case CRYPTO_NULL_CBC: -+ DPRINTK("%s(): NULL CBC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; -+ lacSessCtx->cipherSetupData.cipherAlgorithm = -+ CPA_CY_SYM_CIPHER_NULL; -+ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; -+ break; -+ -+ case CRYPTO_DES_CBC: -+ DPRINTK("%s(): DES CBC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; -+ lacSessCtx->cipherSetupData.cipherAlgorithm = -+ CPA_CY_SYM_CIPHER_DES_CBC; -+ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; -+ break; -+ -+ case CRYPTO_3DES_CBC: -+ DPRINTK("%s(): 3DES CBC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; -+ lacSessCtx->cipherSetupData.cipherAlgorithm = -+ CPA_CY_SYM_CIPHER_3DES_CBC; -+ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; -+ break; -+ -+ case CRYPTO_AES_CBC: -+ DPRINTK("%s(): AES CBC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; -+ lacSessCtx->cipherSetupData.cipherAlgorithm = -+ CPA_CY_SYM_CIPHER_AES_CBC; -+ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; -+ break; -+ -+ case CRYPTO_ARC4: -+ DPRINTK("%s(): ARC4\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; -+ lacSessCtx->cipherSetupData.cipherAlgorithm = -+ CPA_CY_SYM_CIPHER_ARC4; -+ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; -+ break; -+ -+ case CRYPTO_SHA1: -+ DPRINTK("%s(): SHA1\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_SHA1; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_SHA1_DIGEST_SIZE_IN_BYTES); -+ -+ break; -+ -+ case CRYPTO_SHA1_HMAC: -+ DPRINTK("%s(): SHA1_HMAC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_SHA1; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_SHA1_DIGEST_SIZE_IN_BYTES); -+ lacSessCtx->hashSetupData.authModeSetupData.authKey = -+ cri->cri_key; -+ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; -+ -+ break; -+ -+ case CRYPTO_SHA2_256: -+ DPRINTK("%s(): SHA256\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = -+ CPA_CY_SYM_HASH_SHA256; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_SHA256_DIGEST_SIZE_IN_BYTES); -+ -+ break; -+ -+ case CRYPTO_SHA2_256_HMAC: -+ DPRINTK("%s(): SHA256_HMAC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = -+ CPA_CY_SYM_HASH_SHA256; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_SHA256_DIGEST_SIZE_IN_BYTES); -+ lacSessCtx->hashSetupData.authModeSetupData.authKey = -+ cri->cri_key; -+ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; -+ -+ break; -+ -+ case CRYPTO_SHA2_384: -+ DPRINTK("%s(): SHA384\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = -+ CPA_CY_SYM_HASH_SHA384; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_SHA384_DIGEST_SIZE_IN_BYTES); -+ -+ break; -+ -+ case CRYPTO_SHA2_384_HMAC: -+ DPRINTK("%s(): SHA384_HMAC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = -+ CPA_CY_SYM_HASH_SHA384; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_SHA384_DIGEST_SIZE_IN_BYTES); -+ lacSessCtx->hashSetupData.authModeSetupData.authKey = -+ cri->cri_key; -+ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; -+ -+ break; -+ -+ case CRYPTO_SHA2_512: -+ DPRINTK("%s(): SHA512\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = -+ CPA_CY_SYM_HASH_SHA512; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_SHA512_DIGEST_SIZE_IN_BYTES); -+ -+ break; -+ -+ case CRYPTO_SHA2_512_HMAC: -+ DPRINTK("%s(): SHA512_HMAC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = -+ CPA_CY_SYM_HASH_SHA512; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_SHA512_DIGEST_SIZE_IN_BYTES); -+ lacSessCtx->hashSetupData.authModeSetupData.authKey = -+ cri->cri_key; -+ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; -+ -+ break; -+ -+ case CRYPTO_MD5: -+ DPRINTK("%s(): MD5\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_MD5; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_MD5_DIGEST_SIZE_IN_BYTES); -+ -+ break; -+ -+ case CRYPTO_MD5_HMAC: -+ DPRINTK("%s(): MD5_HMAC\n", __FUNCTION__); -+ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; -+ lacSessCtx->hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_MD5; -+ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; -+ lacSessCtx->hashSetupData.digestResultLenInBytes = -+ (cri->cri_mlen ? -+ cri->cri_mlen : ICP_MD5_DIGEST_SIZE_IN_BYTES); -+ lacSessCtx->hashSetupData.authModeSetupData.authKey = -+ cri->cri_key; -+ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = -+ cri->cri_klen / NUM_BITS_IN_BYTE; -+ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; -+ -+ break; -+ -+ default: -+ DPRINTK("%s(): ALG Setup FAIL\n", __FUNCTION__); -+ return ICP_OCF_DRV_STATUS_FAIL; -+ } -+ -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+} -+ -+/* Name : icp_ocfDrvFreeOCFSession -+ * -+ * Description : This function deletes all existing Session data representing -+ * the Cryptographic session established between OCF and this driver. This -+ * also includes freeing the memory allocated for the session context. The -+ * session object is also removed from the session linked list. -+ */ -+static void icp_ocfDrvFreeOCFSession(struct icp_drvSessionData *sessionData) -+{ -+ -+ sessionData->inUse = ICP_SESSION_DEREGISTERED; -+ -+ /*ENTER CRITICAL SECTION */ -+ icp_spin_lockbh_lock(&icp_ocfDrvSymSessInfoListSpinlock); -+ -+ if (CPA_TRUE == icp_atomic_read(&icp_ocfDrvIsExiting)) { -+ /*If the Driver is exiting, allow that process to -+ handle any deletions */ -+ /*EXIT CRITICAL SECTION */ -+ icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock); -+ return; -+ } -+ -+ icp_atomic_dec(&num_ocf_to_drv_registered_sessions); -+ -+ ICP_LIST_DEL(sessionData, listNode); -+ -+ /*EXIT CRITICAL SECTION */ -+ icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock); -+ -+ if (NULL != sessionData->sessHandle) { -+ icp_kfree(sessionData->sessHandle); -+ } -+ ICP_CACHE_FREE(drvSessionData_zone, sessionData); -+} -+ -+/* Name : icp_ocfDrvFreeLACSession -+ * -+ * Description : This attempts to deregister a LAC session. If it fails, the -+ * deregistation retry function is called. -+ */ -+int icp_ocfDrvFreeLACSession(icp_device_t dev, uint64_t sid) -+{ -+ CpaCySymSessionCtx sessionToDeregister = NULL; -+ struct icp_drvSessionData *sessionData = NULL; -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ int retval = 0; -+ -+ sessionData = (struct icp_drvSessionData *)CRYPTO_SESID2LID(sid); -+ if (NULL == sessionData) { -+ EPRINTK("%s(): OCF Free session called with Null Session ID.\n", -+ __FUNCTION__); -+ return EINVAL; -+ } -+ -+ sessionToDeregister = sessionData->sessHandle; -+ -+ if ((ICP_SESSION_INITIALISED != sessionData->inUse) && -+ (ICP_SESSION_RUNNING != sessionData->inUse) && -+ (ICP_SESSION_DEREGISTERED != sessionData->inUse)) { -+ DPRINTK("%s() Session not initialised.\n", __FUNCTION__); -+ return EINVAL; -+ } -+ -+ if (ICP_SESSION_RUNNING == sessionData->inUse) { -+ lacStatus = cpaCySymRemoveSession(CPA_INSTANCE_HANDLE_SINGLE, -+ sessionToDeregister); -+ if (CPA_STATUS_RETRY == lacStatus) { -+ if (ICP_OCF_DRV_STATUS_SUCCESS != -+ icp_ocfDrvDeregRetry(&sessionToDeregister)) { -+ /* the retry function increments the -+ dereg failed count */ -+ DPRINTK("%s(): LAC failed to deregister the " -+ "session. (localSessionId= %p)\n", -+ __FUNCTION__, sessionToDeregister); -+ retval = EPERM; -+ } -+ -+ } else if (CPA_STATUS_SUCCESS != lacStatus) { -+ DPRINTK("%s(): LAC failed to deregister the session. " -+ "localSessionId= %p, lacStatus = %d\n", -+ __FUNCTION__, sessionToDeregister, lacStatus); -+ icp_atomic_inc(&lac_session_failed_dereg_count); -+ retval = EPERM; -+ } -+ } else { -+ DPRINTK("%s() Session not registered with LAC.\n", -+ __FUNCTION__); -+ } -+ -+ icp_ocfDrvFreeOCFSession(sessionData); -+ return retval; -+ -+} -+ -+/* Name : icp_ocfDrvAlgCheck -+ * -+ * Description : This function checks whether the cryptodesc argument pertains -+ * to a sym or hash function -+ */ -+static int icp_ocfDrvAlgCheck(struct cryptodesc *crp_desc) -+{ -+ -+ if (crp_desc->crd_alg == CRYPTO_3DES_CBC || -+ crp_desc->crd_alg == CRYPTO_AES_CBC || -+ crp_desc->crd_alg == CRYPTO_DES_CBC || -+ crp_desc->crd_alg == CRYPTO_NULL_CBC || -+ crp_desc->crd_alg == CRYPTO_ARC4) { -+ return ICP_OCF_DRV_ALG_CIPHER; -+ } -+ -+ return ICP_OCF_DRV_ALG_HASH; -+} -+ -+/* Name : icp_ocfDrvSymProcess -+ * -+ * Description : This function will map symmetric functionality calls from OCF -+ * to the LAC API. It will also allocate memory to store the session context. -+ * -+ * Notes: If it is the first perform call for a given session, then a LAC -+ * session is registered. After the session is registered, no checks as -+ * to whether session paramaters have changed (e.g. alg chain order) are -+ * done. -+ */ -+int icp_ocfDrvSymProcess(icp_device_t dev, struct cryptop *crp, int hint) -+{ -+ struct icp_drvSessionData *sessionData = NULL; -+ struct icp_drvOpData *drvOpData = NULL; -+ CpaStatus lacStatus = CPA_STATUS_SUCCESS; -+ Cpa32U sessionCtxSizeInBytes = 0; -+ -+ if (NULL == crp) { -+ DPRINTK("%s(): Invalid input parameters, cryptop is NULL\n", -+ __FUNCTION__); -+ return EINVAL; -+ } -+ -+ if (NULL == crp->crp_desc) { -+ DPRINTK("%s(): Invalid input parameters, no crp_desc attached " -+ "to crp\n", __FUNCTION__); -+ crp->crp_etype = EINVAL; -+ return EINVAL; -+ } -+ -+ if (NULL == crp->crp_buf) { -+ DPRINTK("%s(): Invalid input parameters, no buffer attached " -+ "to crp\n", __FUNCTION__); -+ crp->crp_etype = EINVAL; -+ return EINVAL; -+ } -+ -+ if (CPA_TRUE == icp_atomic_read(&icp_ocfDrvIsExiting)) { -+ crp->crp_etype = EFAULT; -+ return EFAULT; -+ } -+ -+ sessionData = (struct icp_drvSessionData *) -+ (CRYPTO_SESID2LID(crp->crp_sid)); -+ if (NULL == sessionData) { -+ DPRINTK("%s(): Invalid input parameters, Null Session ID \n", -+ __FUNCTION__); -+ crp->crp_etype = EINVAL; -+ return EINVAL; -+ } -+ -+/*If we get a request against a deregisted session, cancel operation*/ -+ if (ICP_SESSION_DEREGISTERED == sessionData->inUse) { -+ DPRINTK("%s(): Session ID %d was deregistered \n", -+ __FUNCTION__, (int)(CRYPTO_SESID2LID(crp->crp_sid))); -+ crp->crp_etype = EFAULT; -+ return EFAULT; -+ } -+ -+/*If none of the session states are set, then the session structure was either -+ not initialised properly or we are reading from a freed memory area (possible -+ due to OCF batch mode not removing queued requests against deregistered -+ sessions*/ -+ if (ICP_SESSION_INITIALISED != sessionData->inUse && -+ ICP_SESSION_RUNNING != sessionData->inUse) { -+ DPRINTK("%s(): Session - ID %d - not properly initialised or " -+ "memory freed back to the kernel \n", -+ __FUNCTION__, (int)(CRYPTO_SESID2LID(crp->crp_sid))); -+ crp->crp_etype = EINVAL; -+ return EINVAL; -+ } -+ -+ /*For the below checks, remember error checking is already done in LAC. -+ We're not validating inputs subsequent to registration */ -+ if (sessionData->inUse == ICP_SESSION_INITIALISED) { -+ DPRINTK("%s(): Initialising session\n", __FUNCTION__); -+ -+ if (NULL != crp->crp_desc->crd_next) { -+ if (ICP_OCF_DRV_ALG_CIPHER == -+ icp_ocfDrvAlgCheck(crp->crp_desc)) { -+ -+ sessionData->lacSessCtx.algChainOrder = -+ CPA_CY_SYM_ALG_CHAIN_ORDER_CIPHER_THEN_HASH; -+ -+ if (crp->crp_desc->crd_flags & CRD_F_ENCRYPT) { -+ sessionData->lacSessCtx.cipherSetupData. -+ cipherDirection = -+ CPA_CY_SYM_CIPHER_DIRECTION_ENCRYPT; -+ } else { -+ sessionData->lacSessCtx.cipherSetupData. -+ cipherDirection = -+ CPA_CY_SYM_CIPHER_DIRECTION_DECRYPT; -+ } -+ } else { -+ sessionData->lacSessCtx.algChainOrder = -+ CPA_CY_SYM_ALG_CHAIN_ORDER_HASH_THEN_CIPHER; -+ -+ if (crp->crp_desc->crd_next->crd_flags & -+ CRD_F_ENCRYPT) { -+ sessionData->lacSessCtx.cipherSetupData. -+ cipherDirection = -+ CPA_CY_SYM_CIPHER_DIRECTION_ENCRYPT; -+ } else { -+ sessionData->lacSessCtx.cipherSetupData. -+ cipherDirection = -+ CPA_CY_SYM_CIPHER_DIRECTION_DECRYPT; -+ } -+ -+ } -+ -+ } else if (ICP_OCF_DRV_ALG_CIPHER == -+ icp_ocfDrvAlgCheck(crp->crp_desc)) { -+ if (crp->crp_desc->crd_flags & CRD_F_ENCRYPT) { -+ sessionData->lacSessCtx.cipherSetupData. -+ cipherDirection = -+ CPA_CY_SYM_CIPHER_DIRECTION_ENCRYPT; -+ } else { -+ sessionData->lacSessCtx.cipherSetupData. -+ cipherDirection = -+ CPA_CY_SYM_CIPHER_DIRECTION_DECRYPT; -+ } -+ -+ } -+ -+ /*No action required for standalone Auth here */ -+ -+ /* Allocate memory for SymSessionCtx before the Session Registration */ -+ lacStatus = -+ cpaCySymSessionCtxGetSize(CPA_INSTANCE_HANDLE_SINGLE, -+ &(sessionData->lacSessCtx), -+ &sessionCtxSizeInBytes); -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): cpaCySymSessionCtxGetSize failed - %d\n", -+ __FUNCTION__, lacStatus); -+ crp->crp_etype = EINVAL; -+ return EINVAL; -+ } -+ sessionData->sessHandle = -+ icp_kmalloc(sessionCtxSizeInBytes, ICP_M_NOWAIT); -+ if (NULL == sessionData->sessHandle) { -+ EPRINTK -+ ("%s(): Failed to get memory for SymSessionCtx\n", -+ __FUNCTION__); -+ crp->crp_etype = ENOMEM; -+ return ENOMEM; -+ } -+ -+ lacStatus = cpaCySymInitSession(CPA_INSTANCE_HANDLE_SINGLE, -+ icp_ocfDrvSymCallBack, -+ &(sessionData->lacSessCtx), -+ sessionData->sessHandle); -+ -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): cpaCySymInitSession failed -%d \n", -+ __FUNCTION__, lacStatus); -+ crp->crp_etype = EFAULT; -+ return EFAULT; -+ } -+ -+ sessionData->inUse = ICP_SESSION_RUNNING; -+ } -+ -+ drvOpData = icp_kmem_cache_zalloc(drvOpData_zone, ICP_M_NOWAIT); -+ if (NULL == drvOpData) { -+ EPRINTK("%s():Failed to get memory for drvOpData\n", -+ __FUNCTION__); -+ crp->crp_etype = ENOMEM; -+ return ENOMEM; -+ } -+ -+ drvOpData->lacOpData.pSessionCtx = sessionData->sessHandle; -+ drvOpData->digestSizeInBytes = sessionData->lacSessCtx.hashSetupData. -+ digestResultLenInBytes; -+ drvOpData->crp = crp; -+ -+ /* Set the default buffer list array memory allocation */ -+ drvOpData->srcBuffer.pBuffers = drvOpData->bufferListArray; -+ drvOpData->numBufferListArray = ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS; -+ -+ if (ICP_OCF_DRV_STATUS_SUCCESS != -+ icp_ocfDrvProcessDataSetup(drvOpData, drvOpData->crp->crp_desc)) { -+ crp->crp_etype = EINVAL; -+ goto err; -+ } -+ -+ if (drvOpData->crp->crp_desc->crd_next != NULL) { -+ if (icp_ocfDrvProcessDataSetup(drvOpData, drvOpData->crp-> -+ crp_desc->crd_next)) { -+ crp->crp_etype = EINVAL; -+ goto err; -+ } -+ -+ } -+ -+ /* -+ * Allocate buffer list array memory if the data fragment is more than -+ * the default number (ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) and not -+ * calculated already -+ */ -+ if (crp->crp_flags & ICP_CRYPTO_F_PACKET_BUF) { -+ if (NULL == drvOpData->lacOpData.pDigestResult) { -+ drvOpData->numBufferListArray = -+ icp_ocfDrvGetPacketBuffFrags((icp_packet_buffer_t *) -+ crp->crp_buf); -+ } -+ -+ if (ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS < -+ drvOpData->numBufferListArray) { -+ DPRINTK("%s() numBufferListArray more than default\n", -+ __FUNCTION__); -+ drvOpData->srcBuffer.pBuffers = NULL; -+ drvOpData->srcBuffer.pBuffers = -+ icp_kmalloc(drvOpData->numBufferListArray * -+ sizeof(CpaFlatBuffer), ICP_M_NOWAIT); -+ if (NULL == drvOpData->srcBuffer.pBuffers) { -+ EPRINTK("%s() Failed to get memory for " -+ "pBuffers\n", __FUNCTION__); -+ ICP_CACHE_FREE(drvOpData_zone, drvOpData); -+ crp->crp_etype = ENOMEM; -+ return ENOMEM; -+ } -+ } -+ } -+ -+ /* -+ * Check the type of buffer structure we got and convert it into -+ * CpaBufferList format. -+ */ -+ if (crp->crp_flags & ICP_CRYPTO_F_PACKET_BUF) { -+ if (ICP_OCF_DRV_STATUS_SUCCESS != -+ icp_ocfDrvPacketBuffToBufferList((icp_packet_buffer_t *) -+ crp->crp_buf, -+ &(drvOpData->srcBuffer))) { -+ EPRINTK("%s():Failed to translate from packet buffer " -+ "to bufferlist\n", __FUNCTION__); -+ crp->crp_etype = EINVAL; -+ goto err; -+ } -+ -+ drvOpData->bufferType = ICP_CRYPTO_F_PACKET_BUF; -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ /* OCF only supports IOV of one entry. */ -+ if (NUM_IOV_SUPPORTED == -+ ((struct uio *)(crp->crp_buf))->uio_iovcnt) { -+ -+ icp_ocfDrvPtrAndLenToBufferList(((struct uio *)(crp-> -+ crp_buf))-> -+ uio_iov[0].iov_base, -+ ((struct uio *)(crp-> -+ crp_buf))-> -+ uio_iov[0].iov_len, -+ &(drvOpData-> -+ srcBuffer)); -+ -+ drvOpData->bufferType = CRYPTO_F_IOV; -+ -+ } else { -+ DPRINTK("%s():Unable to handle IOVs with lengths of " -+ "greater than one!\n", __FUNCTION__); -+ crp->crp_etype = EINVAL; -+ goto err; -+ } -+ -+ } else { -+ icp_ocfDrvPtrAndLenToBufferList(crp->crp_buf, -+ crp->crp_ilen, -+ &(drvOpData->srcBuffer)); -+ -+ drvOpData->bufferType = CRYPTO_BUF_CONTIG; -+ } -+ -+ /* Allocate srcBuffer's private meta data */ -+ if (ICP_OCF_DRV_STATUS_SUCCESS != -+ icp_ocfDrvAllocMetaData(&(drvOpData->srcBuffer), drvOpData)) { -+ EPRINTK("%s() icp_ocfDrvAllocMetaData failed\n", __FUNCTION__); -+ memset(&(drvOpData->lacOpData), 0, sizeof(CpaCySymOpData)); -+ crp->crp_etype = EINVAL; -+ goto err; -+ } -+ -+ /* Perform "in-place" crypto operation */ -+ lacStatus = cpaCySymPerformOp(CPA_INSTANCE_HANDLE_SINGLE, -+ (void *)drvOpData, -+ &(drvOpData->lacOpData), -+ &(drvOpData->srcBuffer), -+ &(drvOpData->srcBuffer), -+ &(drvOpData->verifyResult)); -+ if (CPA_STATUS_RETRY == lacStatus) { -+ DPRINTK("%s(): cpaCySymPerformOp retry, lacStatus = %d\n", -+ __FUNCTION__, lacStatus); -+ memset(&(drvOpData->lacOpData), 0, sizeof(CpaCySymOpData)); -+ crp->crp_etype = ERESTART; -+ goto err; -+ } -+ if (CPA_STATUS_SUCCESS != lacStatus) { -+ EPRINTK("%s(): cpaCySymPerformOp failed, lacStatus = %d\n", -+ __FUNCTION__, lacStatus); -+ memset(&(drvOpData->lacOpData), 0, sizeof(CpaCySymOpData)); -+ crp->crp_etype = EINVAL; -+ goto err; -+ } -+ -+ return 0; //OCF success status value -+ -+ err: -+ if (drvOpData->numBufferListArray > ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) { -+ icp_kfree(drvOpData->srcBuffer.pBuffers); -+ } -+ icp_ocfDrvFreeMetaData(&(drvOpData->srcBuffer)); -+ ICP_CACHE_FREE(drvOpData_zone, drvOpData); -+ -+ return crp->crp_etype; -+} -+ -+/* Name : icp_ocfDrvProcessDataSetup -+ * -+ * Description : This function will setup all the cryptographic operation data -+ * that is required by LAC to execute the operation. -+ */ -+static int icp_ocfDrvProcessDataSetup(struct icp_drvOpData *drvOpData, -+ struct cryptodesc *crp_desc) -+{ -+ CpaCyRandGenOpData randGenOpData; -+ CpaFlatBuffer randData; -+ -+ drvOpData->lacOpData.packetType = CPA_CY_SYM_PACKET_TYPE_FULL; -+ -+ /* Convert from the cryptop to the ICP LAC crypto parameters */ -+ switch (crp_desc->crd_alg) { -+ case CRYPTO_NULL_CBC: -+ drvOpData->lacOpData. -+ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; -+ drvOpData->lacOpData. -+ messageLenToCipherInBytes = crp_desc->crd_len; -+ drvOpData->verifyResult = CPA_FALSE; -+ drvOpData->lacOpData.ivLenInBytes = NULL_BLOCK_LEN; -+ break; -+ case CRYPTO_DES_CBC: -+ drvOpData->lacOpData. -+ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; -+ drvOpData->lacOpData. -+ messageLenToCipherInBytes = crp_desc->crd_len; -+ drvOpData->verifyResult = CPA_FALSE; -+ drvOpData->lacOpData.ivLenInBytes = DES_BLOCK_LEN; -+ break; -+ case CRYPTO_3DES_CBC: -+ drvOpData->lacOpData. -+ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; -+ drvOpData->lacOpData. -+ messageLenToCipherInBytes = crp_desc->crd_len; -+ drvOpData->verifyResult = CPA_FALSE; -+ drvOpData->lacOpData.ivLenInBytes = DES3_BLOCK_LEN; -+ break; -+ case CRYPTO_ARC4: -+ drvOpData->lacOpData. -+ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; -+ drvOpData->lacOpData. -+ messageLenToCipherInBytes = crp_desc->crd_len; -+ drvOpData->verifyResult = CPA_FALSE; -+ drvOpData->lacOpData.ivLenInBytes = ARC4_COUNTER_LEN; -+ break; -+ case CRYPTO_AES_CBC: -+ drvOpData->lacOpData. -+ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; -+ drvOpData->lacOpData. -+ messageLenToCipherInBytes = crp_desc->crd_len; -+ drvOpData->verifyResult = CPA_FALSE; -+ drvOpData->lacOpData.ivLenInBytes = RIJNDAEL128_BLOCK_LEN; -+ break; -+ case CRYPTO_SHA1: -+ case CRYPTO_SHA1_HMAC: -+ case CRYPTO_SHA2_256: -+ case CRYPTO_SHA2_256_HMAC: -+ case CRYPTO_SHA2_384: -+ case CRYPTO_SHA2_384_HMAC: -+ case CRYPTO_SHA2_512: -+ case CRYPTO_SHA2_512_HMAC: -+ case CRYPTO_MD5: -+ case CRYPTO_MD5_HMAC: -+ drvOpData->lacOpData. -+ hashStartSrcOffsetInBytes = crp_desc->crd_skip; -+ drvOpData->lacOpData. -+ messageLenToHashInBytes = crp_desc->crd_len; -+ drvOpData->lacOpData. -+ pDigestResult = -+ icp_ocfDrvDigestPointerFind(drvOpData, crp_desc); -+ -+ if (NULL == drvOpData->lacOpData.pDigestResult) { -+ DPRINTK("%s(): ERROR - could not calculate " -+ "Digest Result memory address\n", __FUNCTION__); -+ return ICP_OCF_DRV_STATUS_FAIL; -+ } -+ -+ drvOpData->lacOpData.digestVerify = CPA_FALSE; -+ break; -+ default: -+ DPRINTK("%s(): Crypto process error - algorithm not " -+ "found \n", __FUNCTION__); -+ return ICP_OCF_DRV_STATUS_FAIL; -+ } -+ -+ /* Figure out what the IV is supposed to be */ -+ if ((crp_desc->crd_alg == CRYPTO_DES_CBC) || -+ (crp_desc->crd_alg == CRYPTO_3DES_CBC) || -+ (crp_desc->crd_alg == CRYPTO_AES_CBC)) { -+ /*ARC4 doesn't use an IV */ -+ if (crp_desc->crd_flags & CRD_F_IV_EXPLICIT) { -+ /* Explicit IV provided to OCF */ -+ drvOpData->lacOpData.pIv = crp_desc->crd_iv; -+ } else { -+ /* IV is not explicitly provided to OCF */ -+ -+ /* Point the LAC OP Data IV pointer to our allocated -+ storage location for this session. */ -+ drvOpData->lacOpData.pIv = drvOpData->ivData; -+ -+ if ((crp_desc->crd_flags & CRD_F_ENCRYPT) && -+ ((crp_desc->crd_flags & CRD_F_IV_PRESENT) == 0)) { -+ -+ /* Encrypting - need to create IV */ -+ randGenOpData.generateBits = CPA_TRUE; -+ randGenOpData.lenInBytes = MAX_IV_LEN_IN_BYTES; -+ -+ icp_ocfDrvPtrAndLenToFlatBuffer((Cpa8U *) -+ drvOpData-> -+ ivData, -+ MAX_IV_LEN_IN_BYTES, -+ &randData); -+ -+ if (CPA_STATUS_SUCCESS != -+ cpaCyRandGen(CPA_INSTANCE_HANDLE_SINGLE, -+ NULL, NULL, -+ &randGenOpData, &randData)) { -+ DPRINTK("%s(): ERROR - Failed to" -+ " generate" -+ " Initialisation Vector\n", -+ __FUNCTION__); -+ return ICP_OCF_DRV_STATUS_FAIL; -+ } -+ -+ crypto_copyback(drvOpData->crp-> -+ crp_flags, -+ drvOpData->crp->crp_buf, -+ crp_desc->crd_inject, -+ drvOpData->lacOpData. -+ ivLenInBytes, -+ (caddr_t) (drvOpData->lacOpData. -+ pIv)); -+ } else { -+ /* Reading IV from buffer */ -+ crypto_copydata(drvOpData->crp-> -+ crp_flags, -+ drvOpData->crp->crp_buf, -+ crp_desc->crd_inject, -+ drvOpData->lacOpData. -+ ivLenInBytes, -+ (caddr_t) (drvOpData->lacOpData. -+ pIv)); -+ } -+ -+ } -+ -+ } -+ -+ return ICP_OCF_DRV_STATUS_SUCCESS; -+} -+ -+/* Name : icp_ocfDrvDigestPointerFind -+ * -+ * Description : This function is used to find the memory address of where the -+ * digest information shall be stored in. Input buffer types are an skbuff, iov -+ * or flat buffer. The address is found using the buffer data start address and -+ * an offset. -+ * -+ * Note: In the case of a linux skbuff, the digest address may exist within -+ * a memory space linked to from the start buffer. These linked memory spaces -+ * must be traversed by the data length offset in order to find the digest start -+ * address. Whether there is enough space for the digest must also be checked. -+ */ -+uint8_t *icp_ocfDrvDigestPointerFind(struct icp_drvOpData * drvOpData, -+ struct cryptodesc * crp_desc) -+{ -+ -+ int offsetInBytes = crp_desc->crd_inject; -+ uint32_t digestSizeInBytes = drvOpData->digestSizeInBytes; -+ uint8_t *flat_buffer_base = NULL; -+ int flat_buffer_length = 0; -+ -+ if (drvOpData->crp->crp_flags & ICP_CRYPTO_F_PACKET_BUF) { -+ -+ return icp_ocfDrvPacketBufferDigestPointerFind(drvOpData, -+ offsetInBytes, -+ digestSizeInBytes); -+ -+ } else { -+ /* IOV or flat buffer */ -+ if (drvOpData->crp->crp_flags & CRYPTO_F_IOV) { -+ /*single IOV check has already been done */ -+ flat_buffer_base = ((struct uio *) -+ (drvOpData->crp->crp_buf))-> -+ uio_iov[0].iov_base; -+ flat_buffer_length = ((struct uio *) -+ (drvOpData->crp->crp_buf))-> -+ uio_iov[0].iov_len; -+ } else { -+ flat_buffer_base = (uint8_t *) drvOpData->crp->crp_buf; -+ flat_buffer_length = drvOpData->crp->crp_ilen; -+ } -+ -+ if (flat_buffer_length < (offsetInBytes + digestSizeInBytes)) { -+ DPRINTK("%s() Not enough space for Digest " -+ "(IOV/Flat Buffer) \n", __FUNCTION__); -+ return NULL; -+ } else { -+ return (uint8_t *) (flat_buffer_base + offsetInBytes); -+ } -+ } -+ DPRINTK("%s() Should not reach this point\n", __FUNCTION__); -+ return NULL; -+} -diff -Nur linux-3.0.4.orig/crypto/ocf/ep80579/linux_2.6_kernel_space.mk linux-3.0.4/crypto/ocf/ep80579/linux_2.6_kernel_space.mk ---- linux-3.0.4.orig/crypto/ocf/ep80579/linux_2.6_kernel_space.mk 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/ep80579/linux_2.6_kernel_space.mk 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,69 @@ -+################### -+# @par -+# This file is provided under a dual BSD/GPLv2 license. When using or -+# redistributing this file, you may do so under either license. -+# -+# GPL LICENSE SUMMARY -+# -+# Copyright(c) 2007,2008 Intel Corporation. All rights reserved. -+# -+# This program is free software; you can redistribute it and/or modify -+# it under the terms of version 2 of the GNU General Public License as -+# published by the Free Software Foundation. -+# -+# This program is distributed in the hope that it will be useful, but -+# WITHOUT ANY WARRANTY; without even the implied warranty of -+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+# General Public License for more details. -+# -+# You should have received a copy of the GNU General Public License -+# along with this program; if not, write to the Free Software -+# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. -+# The full GNU General Public License is included in this distribution -+# in the file called LICENSE.GPL. -+# -+# Contact Information: -+# Intel Corporation -+# -+# BSD LICENSE -+# -+# Copyright(c) 2007,2008 Intel Corporation. All rights reserved. -+# All rights reserved. -+# -+# Redistribution and use in source and binary forms, with or without -+# modification, are permitted provided that the following conditions -+# are met: -+# -+# * Redistributions of source code must retain the above copyright -+# notice, this list of conditions and the following disclaimer. -+# * Redistributions in binary form must reproduce the above copyright -+# notice, this list of conditions and the following disclaimer in -+# the documentation and/or other materials provided with the -+# distribution. -+# * Neither the name of Intel Corporation nor the names of its -+# contributors may be used to endorse or promote products derived -+# from this software without specific prior written permission. -+# -+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+# -+# -+# version: Security.L.1.0.130 -+################### -+ -+#specific include directories in kernel space -+INCLUDES+=#e.g. -I$(OSAL_DIR)/include \ -+ -+#Extra Flags Specific in kernel space e.g. include path or debug flags etc. e.g to add an include path EXTRA_CFLAGS += -I$(src)/../include -+EXTRA_CFLAGS += $(INCLUDES) -O2 -Wall -+EXTRA_LDFLAGS +=-whole-archive -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/hifn/Makefile linux-3.0.4/crypto/ocf/hifn/Makefile ---- linux-3.0.4.orig/crypto/ocf/hifn/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/hifn/Makefile 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,13 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+obj-$(CONFIG_OCF_HIFN) += hifn7751.o -+obj-$(CONFIG_OCF_HIFNHIPP) += hifnHIPP.o -+ -+obj ?= . -+EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/hifn/hifn7751.c linux-3.0.4/crypto/ocf/hifn/hifn7751.c ---- linux-3.0.4.orig/crypto/ocf/hifn/hifn7751.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/hifn/hifn7751.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,2954 @@ -+/* $OpenBSD: hifn7751.c,v 1.120 2002/05/17 00:33:34 deraadt Exp $ */ -+ -+/*- -+ * Invertex AEON / Hifn 7751 driver -+ * Copyright (c) 1999 Invertex Inc. All rights reserved. -+ * Copyright (c) 1999 Theo de Raadt -+ * Copyright (c) 2000-2001 Network Security Technologies, Inc. -+ * http://www.netsec.net -+ * Copyright (c) 2003 Hifn Inc. -+ * -+ * This driver is based on a previous driver by Invertex, for which they -+ * requested: Please send any comments, feedback, bug-fixes, or feature -+ * requests to software@invertex.com. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored in part by the Defense Advanced Research Projects -+ * Agency (DARPA) and Air Force Research Laboratory, Air Force -+ * Materiel Command, USAF, under agreement number F30602-01-2-0537. -+ * -+ * -+__FBSDID("$FreeBSD: src/sys/dev/hifn/hifn7751.c,v 1.40 2007/03/21 03:42:49 sam Exp $"); -+ */ -+ -+/* -+ * Driver for various Hifn encryption processors. -+ */ -+#include -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+ -+#if 1 -+#define DPRINTF(a...) if (hifn_debug) { \ -+ printk("%s: ", sc ? \ -+ device_get_nameunit(sc->sc_dev) : "hifn"); \ -+ printk(a); \ -+ } else -+#else -+#define DPRINTF(a...) -+#endif -+ -+static inline int -+pci_get_revid(struct pci_dev *dev) -+{ -+ u8 rid = 0; -+ pci_read_config_byte(dev, PCI_REVISION_ID, &rid); -+ return rid; -+} -+ -+static struct hifn_stats hifnstats; -+ -+#define debug hifn_debug -+int hifn_debug = 0; -+module_param(hifn_debug, int, 0644); -+MODULE_PARM_DESC(hifn_debug, "Enable debug"); -+ -+int hifn_maxbatch = 1; -+module_param(hifn_maxbatch, int, 0644); -+MODULE_PARM_DESC(hifn_maxbatch, "max ops to batch w/o interrupt"); -+ -+int hifn_cache_linesize = 0x10; -+module_param(hifn_cache_linesize, int, 0444); -+MODULE_PARM_DESC(hifn_cache_linesize, "PCI config cache line size"); -+ -+#ifdef MODULE_PARM -+char *hifn_pllconfig = NULL; -+MODULE_PARM(hifn_pllconfig, "s"); -+#else -+char hifn_pllconfig[32]; /* This setting is RO after loading */ -+module_param_string(hifn_pllconfig, hifn_pllconfig, 32, 0444); -+#endif -+MODULE_PARM_DESC(hifn_pllconfig, "PLL config, ie., pci66, ext33, ..."); -+ -+#ifdef HIFN_VULCANDEV -+#include -+#include -+ -+static struct cdevsw vulcanpk_cdevsw; /* forward declaration */ -+#endif -+ -+/* -+ * Prototypes and count for the pci_device structure -+ */ -+static int hifn_probe(struct pci_dev *dev, const struct pci_device_id *ent); -+static void hifn_remove(struct pci_dev *dev); -+ -+static int hifn_newsession(device_t, u_int32_t *, struct cryptoini *); -+static int hifn_freesession(device_t, u_int64_t); -+static int hifn_process(device_t, struct cryptop *, int); -+ -+static device_method_t hifn_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, hifn_newsession), -+ DEVMETHOD(cryptodev_freesession,hifn_freesession), -+ DEVMETHOD(cryptodev_process, hifn_process), -+}; -+ -+static void hifn_reset_board(struct hifn_softc *, int); -+static void hifn_reset_puc(struct hifn_softc *); -+static void hifn_puc_wait(struct hifn_softc *); -+static int hifn_enable_crypto(struct hifn_softc *); -+static void hifn_set_retry(struct hifn_softc *sc); -+static void hifn_init_dma(struct hifn_softc *); -+static void hifn_init_pci_registers(struct hifn_softc *); -+static int hifn_sramsize(struct hifn_softc *); -+static int hifn_dramsize(struct hifn_softc *); -+static int hifn_ramtype(struct hifn_softc *); -+static void hifn_sessions(struct hifn_softc *); -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) -+static irqreturn_t hifn_intr(int irq, void *arg); -+#else -+static irqreturn_t hifn_intr(int irq, void *arg, struct pt_regs *regs); -+#endif -+static u_int hifn_write_command(struct hifn_command *, u_int8_t *); -+static u_int32_t hifn_next_signature(u_int32_t a, u_int cnt); -+static void hifn_callback(struct hifn_softc *, struct hifn_command *, u_int8_t *); -+static int hifn_crypto(struct hifn_softc *, struct hifn_command *, struct cryptop *, int); -+static int hifn_readramaddr(struct hifn_softc *, int, u_int8_t *); -+static int hifn_writeramaddr(struct hifn_softc *, int, u_int8_t *); -+static int hifn_dmamap_load_src(struct hifn_softc *, struct hifn_command *); -+static int hifn_dmamap_load_dst(struct hifn_softc *, struct hifn_command *); -+static int hifn_init_pubrng(struct hifn_softc *); -+static void hifn_tick(unsigned long arg); -+static void hifn_abort(struct hifn_softc *); -+static void hifn_alloc_slot(struct hifn_softc *, int *, int *, int *, int *); -+ -+static void hifn_write_reg_0(struct hifn_softc *, bus_size_t, u_int32_t); -+static void hifn_write_reg_1(struct hifn_softc *, bus_size_t, u_int32_t); -+ -+#ifdef CONFIG_OCF_RANDOMHARVEST -+static int hifn_read_random(void *arg, u_int32_t *buf, int len); -+#endif -+ -+#define HIFN_MAX_CHIPS 8 -+static struct hifn_softc *hifn_chip_idx[HIFN_MAX_CHIPS]; -+ -+static __inline u_int32_t -+READ_REG_0(struct hifn_softc *sc, bus_size_t reg) -+{ -+ u_int32_t v = readl(sc->sc_bar0 + reg); -+ sc->sc_bar0_lastreg = (bus_size_t) -1; -+ return (v); -+} -+#define WRITE_REG_0(sc, reg, val) hifn_write_reg_0(sc, reg, val) -+ -+static __inline u_int32_t -+READ_REG_1(struct hifn_softc *sc, bus_size_t reg) -+{ -+ u_int32_t v = readl(sc->sc_bar1 + reg); -+ sc->sc_bar1_lastreg = (bus_size_t) -1; -+ return (v); -+} -+#define WRITE_REG_1(sc, reg, val) hifn_write_reg_1(sc, reg, val) -+ -+/* -+ * map in a given buffer (great on some arches :-) -+ */ -+ -+static int -+pci_map_uio(struct hifn_softc *sc, struct hifn_operand *buf, struct uio *uio) -+{ -+ struct iovec *iov = uio->uio_iov; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ buf->mapsize = 0; -+ for (buf->nsegs = 0; buf->nsegs < uio->uio_iovcnt; ) { -+ buf->segs[buf->nsegs].ds_addr = pci_map_single(sc->sc_pcidev, -+ iov->iov_base, iov->iov_len, -+ PCI_DMA_BIDIRECTIONAL); -+ buf->segs[buf->nsegs].ds_len = iov->iov_len; -+ buf->mapsize += iov->iov_len; -+ iov++; -+ buf->nsegs++; -+ } -+ /* identify this buffer by the first segment */ -+ buf->map = (void *) buf->segs[0].ds_addr; -+ return(0); -+} -+ -+/* -+ * map in a given sk_buff -+ */ -+ -+static int -+pci_map_skb(struct hifn_softc *sc,struct hifn_operand *buf,struct sk_buff *skb) -+{ -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ buf->mapsize = 0; -+ -+ buf->segs[0].ds_addr = pci_map_single(sc->sc_pcidev, -+ skb->data, skb_headlen(skb), PCI_DMA_BIDIRECTIONAL); -+ buf->segs[0].ds_len = skb_headlen(skb); -+ buf->mapsize += buf->segs[0].ds_len; -+ -+ buf->nsegs = 1; -+ -+ for (i = 0; i < skb_shinfo(skb)->nr_frags; ) { -+ buf->segs[buf->nsegs].ds_len = skb_shinfo(skb)->frags[i].size; -+ buf->segs[buf->nsegs].ds_addr = pci_map_single(sc->sc_pcidev, -+ page_address(skb_shinfo(skb)->frags[i].page) + -+ skb_shinfo(skb)->frags[i].page_offset, -+ buf->segs[buf->nsegs].ds_len, PCI_DMA_BIDIRECTIONAL); -+ buf->mapsize += buf->segs[buf->nsegs].ds_len; -+ buf->nsegs++; -+ } -+ -+ /* identify this buffer by the first segment */ -+ buf->map = (void *) buf->segs[0].ds_addr; -+ return(0); -+} -+ -+/* -+ * map in a given contiguous buffer -+ */ -+ -+static int -+pci_map_buf(struct hifn_softc *sc,struct hifn_operand *buf, void *b, int len) -+{ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ buf->mapsize = 0; -+ buf->segs[0].ds_addr = pci_map_single(sc->sc_pcidev, -+ b, len, PCI_DMA_BIDIRECTIONAL); -+ buf->segs[0].ds_len = len; -+ buf->mapsize += buf->segs[0].ds_len; -+ buf->nsegs = 1; -+ -+ /* identify this buffer by the first segment */ -+ buf->map = (void *) buf->segs[0].ds_addr; -+ return(0); -+} -+ -+#if 0 /* not needed at this time */ -+static void -+pci_sync_iov(struct hifn_softc *sc, struct hifn_operand *buf) -+{ -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ for (i = 0; i < buf->nsegs; i++) -+ pci_dma_sync_single_for_cpu(sc->sc_pcidev, buf->segs[i].ds_addr, -+ buf->segs[i].ds_len, PCI_DMA_BIDIRECTIONAL); -+} -+#endif -+ -+static void -+pci_unmap_buf(struct hifn_softc *sc, struct hifn_operand *buf) -+{ -+ int i; -+ DPRINTF("%s()\n", __FUNCTION__); -+ for (i = 0; i < buf->nsegs; i++) { -+ pci_unmap_single(sc->sc_pcidev, buf->segs[i].ds_addr, -+ buf->segs[i].ds_len, PCI_DMA_BIDIRECTIONAL); -+ buf->segs[i].ds_addr = 0; -+ buf->segs[i].ds_len = 0; -+ } -+ buf->nsegs = 0; -+ buf->mapsize = 0; -+ buf->map = 0; -+} -+ -+static const char* -+hifn_partname(struct hifn_softc *sc) -+{ -+ /* XXX sprintf numbers when not decoded */ -+ switch (pci_get_vendor(sc->sc_pcidev)) { -+ case PCI_VENDOR_HIFN: -+ switch (pci_get_device(sc->sc_pcidev)) { -+ case PCI_PRODUCT_HIFN_6500: return "Hifn 6500"; -+ case PCI_PRODUCT_HIFN_7751: return "Hifn 7751"; -+ case PCI_PRODUCT_HIFN_7811: return "Hifn 7811"; -+ case PCI_PRODUCT_HIFN_7951: return "Hifn 7951"; -+ case PCI_PRODUCT_HIFN_7955: return "Hifn 7955"; -+ case PCI_PRODUCT_HIFN_7956: return "Hifn 7956"; -+ } -+ return "Hifn unknown-part"; -+ case PCI_VENDOR_INVERTEX: -+ switch (pci_get_device(sc->sc_pcidev)) { -+ case PCI_PRODUCT_INVERTEX_AEON: return "Invertex AEON"; -+ } -+ return "Invertex unknown-part"; -+ case PCI_VENDOR_NETSEC: -+ switch (pci_get_device(sc->sc_pcidev)) { -+ case PCI_PRODUCT_NETSEC_7751: return "NetSec 7751"; -+ } -+ return "NetSec unknown-part"; -+ } -+ return "Unknown-vendor unknown-part"; -+} -+ -+static u_int -+checkmaxmin(struct pci_dev *dev, const char *what, u_int v, u_int min, u_int max) -+{ -+ struct hifn_softc *sc = pci_get_drvdata(dev); -+ if (v > max) { -+ device_printf(sc->sc_dev, "Warning, %s %u out of range, " -+ "using max %u\n", what, v, max); -+ v = max; -+ } else if (v < min) { -+ device_printf(sc->sc_dev, "Warning, %s %u out of range, " -+ "using min %u\n", what, v, min); -+ v = min; -+ } -+ return v; -+} -+ -+/* -+ * Select PLL configuration for 795x parts. This is complicated in -+ * that we cannot determine the optimal parameters without user input. -+ * The reference clock is derived from an external clock through a -+ * multiplier. The external clock is either the host bus (i.e. PCI) -+ * or an external clock generator. When using the PCI bus we assume -+ * the clock is either 33 or 66 MHz; for an external source we cannot -+ * tell the speed. -+ * -+ * PLL configuration is done with a string: "pci" for PCI bus, or "ext" -+ * for an external source, followed by the frequency. We calculate -+ * the appropriate multiplier and PLL register contents accordingly. -+ * When no configuration is given we default to "pci66" since that -+ * always will allow the card to work. If a card is using the PCI -+ * bus clock and in a 33MHz slot then it will be operating at half -+ * speed until the correct information is provided. -+ * -+ * We use a default setting of "ext66" because according to Mike Ham -+ * of HiFn, almost every board in existence has an external crystal -+ * populated at 66Mhz. Using PCI can be a problem on modern motherboards, -+ * because PCI33 can have clocks from 0 to 33Mhz, and some have -+ * non-PCI-compliant spread-spectrum clocks, which can confuse the pll. -+ */ -+static void -+hifn_getpllconfig(struct pci_dev *dev, u_int *pll) -+{ -+ const char *pllspec = hifn_pllconfig; -+ u_int freq, mul, fl, fh; -+ u_int32_t pllconfig; -+ char *nxt; -+ -+ if (pllspec == NULL) -+ pllspec = "ext66"; -+ fl = 33, fh = 66; -+ pllconfig = 0; -+ if (strncmp(pllspec, "ext", 3) == 0) { -+ pllspec += 3; -+ pllconfig |= HIFN_PLL_REF_SEL; -+ switch (pci_get_device(dev)) { -+ case PCI_PRODUCT_HIFN_7955: -+ case PCI_PRODUCT_HIFN_7956: -+ fl = 20, fh = 100; -+ break; -+#ifdef notyet -+ case PCI_PRODUCT_HIFN_7954: -+ fl = 20, fh = 66; -+ break; -+#endif -+ } -+ } else if (strncmp(pllspec, "pci", 3) == 0) -+ pllspec += 3; -+ freq = strtoul(pllspec, &nxt, 10); -+ if (nxt == pllspec) -+ freq = 66; -+ else -+ freq = checkmaxmin(dev, "frequency", freq, fl, fh); -+ /* -+ * Calculate multiplier. We target a Fck of 266 MHz, -+ * allowing only even values, possibly rounded down. -+ * Multipliers > 8 must set the charge pump current. -+ */ -+ mul = checkmaxmin(dev, "PLL divisor", (266 / freq) &~ 1, 2, 12); -+ pllconfig |= (mul / 2 - 1) << HIFN_PLL_ND_SHIFT; -+ if (mul > 8) -+ pllconfig |= HIFN_PLL_IS; -+ *pll = pllconfig; -+} -+ -+/* -+ * Attach an interface that successfully probed. -+ */ -+static int -+hifn_probe(struct pci_dev *dev, const struct pci_device_id *ent) -+{ -+ struct hifn_softc *sc = NULL; -+ char rbase; -+ u_int16_t ena, rev; -+ int rseg, rc; -+ unsigned long mem_start, mem_len; -+ static int num_chips = 0; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (pci_enable_device(dev) < 0) -+ return(-ENODEV); -+ -+ if (pci_set_mwi(dev)) -+ return(-ENODEV); -+ -+ if (!dev->irq) { -+ printk("hifn: found device with no IRQ assigned. check BIOS settings!"); -+ pci_disable_device(dev); -+ return(-ENODEV); -+ } -+ -+ sc = (struct hifn_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); -+ if (!sc) -+ return(-ENOMEM); -+ memset(sc, 0, sizeof(*sc)); -+ -+ softc_device_init(sc, "hifn", num_chips, hifn_methods); -+ -+ sc->sc_pcidev = dev; -+ sc->sc_irq = -1; -+ sc->sc_cid = -1; -+ sc->sc_num = num_chips++; -+ if (sc->sc_num < HIFN_MAX_CHIPS) -+ hifn_chip_idx[sc->sc_num] = sc; -+ -+ pci_set_drvdata(sc->sc_pcidev, sc); -+ -+ spin_lock_init(&sc->sc_mtx); -+ -+ /* XXX handle power management */ -+ -+ /* -+ * The 7951 and 795x have a random number generator and -+ * public key support; note this. -+ */ -+ if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && -+ (pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 || -+ pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 || -+ pci_get_device(dev) == PCI_PRODUCT_HIFN_7956)) -+ sc->sc_flags = HIFN_HAS_RNG | HIFN_HAS_PUBLIC; -+ /* -+ * The 7811 has a random number generator and -+ * we also note it's identity 'cuz of some quirks. -+ */ -+ if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && -+ pci_get_device(dev) == PCI_PRODUCT_HIFN_7811) -+ sc->sc_flags |= HIFN_IS_7811 | HIFN_HAS_RNG; -+ -+ /* -+ * The 795x parts support AES. -+ */ -+ if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && -+ (pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 || -+ pci_get_device(dev) == PCI_PRODUCT_HIFN_7956)) { -+ sc->sc_flags |= HIFN_IS_7956 | HIFN_HAS_AES; -+ /* -+ * Select PLL configuration. This depends on the -+ * bus and board design and must be manually configured -+ * if the default setting is unacceptable. -+ */ -+ hifn_getpllconfig(dev, &sc->sc_pllconfig); -+ } -+ -+ /* -+ * Setup PCI resources. Note that we record the bus -+ * tag and handle for each register mapping, this is -+ * used by the READ_REG_0, WRITE_REG_0, READ_REG_1, -+ * and WRITE_REG_1 macros throughout the driver. -+ */ -+ mem_start = pci_resource_start(sc->sc_pcidev, 0); -+ mem_len = pci_resource_len(sc->sc_pcidev, 0); -+ sc->sc_bar0 = (ocf_iomem_t) ioremap(mem_start, mem_len); -+ if (!sc->sc_bar0) { -+ device_printf(sc->sc_dev, "cannot map bar%d register space\n", 0); -+ goto fail; -+ } -+ sc->sc_bar0_lastreg = (bus_size_t) -1; -+ -+ mem_start = pci_resource_start(sc->sc_pcidev, 1); -+ mem_len = pci_resource_len(sc->sc_pcidev, 1); -+ sc->sc_bar1 = (ocf_iomem_t) ioremap(mem_start, mem_len); -+ if (!sc->sc_bar1) { -+ device_printf(sc->sc_dev, "cannot map bar%d register space\n", 1); -+ goto fail; -+ } -+ sc->sc_bar1_lastreg = (bus_size_t) -1; -+ -+ /* fix up the bus size */ -+ if (pci_set_dma_mask(dev, DMA_32BIT_MASK)) { -+ device_printf(sc->sc_dev, "No usable DMA configuration, aborting.\n"); -+ goto fail; -+ } -+ if (pci_set_consistent_dma_mask(dev, DMA_32BIT_MASK)) { -+ device_printf(sc->sc_dev, -+ "No usable consistent DMA configuration, aborting.\n"); -+ goto fail; -+ } -+ -+ hifn_set_retry(sc); -+ -+ /* -+ * Setup the area where the Hifn DMA's descriptors -+ * and associated data structures. -+ */ -+ sc->sc_dma = (struct hifn_dma *) pci_alloc_consistent(dev, -+ sizeof(*sc->sc_dma), -+ &sc->sc_dma_physaddr); -+ if (!sc->sc_dma) { -+ device_printf(sc->sc_dev, "cannot alloc sc_dma\n"); -+ goto fail; -+ } -+ bzero(sc->sc_dma, sizeof(*sc->sc_dma)); -+ -+ /* -+ * Reset the board and do the ``secret handshake'' -+ * to enable the crypto support. Then complete the -+ * initialization procedure by setting up the interrupt -+ * and hooking in to the system crypto support so we'll -+ * get used for system services like the crypto device, -+ * IPsec, RNG device, etc. -+ */ -+ hifn_reset_board(sc, 0); -+ -+ if (hifn_enable_crypto(sc) != 0) { -+ device_printf(sc->sc_dev, "crypto enabling failed\n"); -+ goto fail; -+ } -+ hifn_reset_puc(sc); -+ -+ hifn_init_dma(sc); -+ hifn_init_pci_registers(sc); -+ -+ pci_set_master(sc->sc_pcidev); -+ -+ /* XXX can't dynamically determine ram type for 795x; force dram */ -+ if (sc->sc_flags & HIFN_IS_7956) -+ sc->sc_drammodel = 1; -+ else if (hifn_ramtype(sc)) -+ goto fail; -+ -+ if (sc->sc_drammodel == 0) -+ hifn_sramsize(sc); -+ else -+ hifn_dramsize(sc); -+ -+ /* -+ * Workaround for NetSec 7751 rev A: half ram size because two -+ * of the address lines were left floating -+ */ -+ if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC && -+ pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751 && -+ pci_get_revid(dev) == 0x61) /*XXX???*/ -+ sc->sc_ramsize >>= 1; -+ -+ /* -+ * Arrange the interrupt line. -+ */ -+ rc = request_irq(dev->irq, hifn_intr, IRQF_SHARED, "hifn", sc); -+ if (rc) { -+ device_printf(sc->sc_dev, "could not map interrupt: %d\n", rc); -+ goto fail; -+ } -+ sc->sc_irq = dev->irq; -+ -+ hifn_sessions(sc); -+ -+ /* -+ * NB: Keep only the low 16 bits; this masks the chip id -+ * from the 7951. -+ */ -+ rev = READ_REG_1(sc, HIFN_1_REVID) & 0xffff; -+ -+ rseg = sc->sc_ramsize / 1024; -+ rbase = 'K'; -+ if (sc->sc_ramsize >= (1024 * 1024)) { -+ rbase = 'M'; -+ rseg /= 1024; -+ } -+ device_printf(sc->sc_dev, "%s, rev %u, %d%cB %cram", -+ hifn_partname(sc), rev, -+ rseg, rbase, sc->sc_drammodel ? 'd' : 's'); -+ if (sc->sc_flags & HIFN_IS_7956) -+ printf(", pll=0x%x<%s clk, %ux mult>", -+ sc->sc_pllconfig, -+ sc->sc_pllconfig & HIFN_PLL_REF_SEL ? "ext" : "pci", -+ 2 + 2*((sc->sc_pllconfig & HIFN_PLL_ND) >> 11)); -+ printf("\n"); -+ -+ sc->sc_cid = crypto_get_driverid(softc_get_device(sc),CRYPTOCAP_F_HARDWARE); -+ if (sc->sc_cid < 0) { -+ device_printf(sc->sc_dev, "could not get crypto driver id\n"); -+ goto fail; -+ } -+ -+ WRITE_REG_0(sc, HIFN_0_PUCNFG, -+ READ_REG_0(sc, HIFN_0_PUCNFG) | HIFN_PUCNFG_CHIPID); -+ ena = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; -+ -+ switch (ena) { -+ case HIFN_PUSTAT_ENA_2: -+ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0); -+ if (sc->sc_flags & HIFN_HAS_AES) -+ crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); -+ /*FALLTHROUGH*/ -+ case HIFN_PUSTAT_ENA_1: -+ crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); -+ break; -+ } -+ -+ if (sc->sc_flags & (HIFN_HAS_PUBLIC | HIFN_HAS_RNG)) -+ hifn_init_pubrng(sc); -+ -+ init_timer(&sc->sc_tickto); -+ sc->sc_tickto.function = hifn_tick; -+ sc->sc_tickto.data = (unsigned long) sc->sc_num; -+ mod_timer(&sc->sc_tickto, jiffies + HZ); -+ -+ return (0); -+ -+fail: -+ if (sc->sc_cid >= 0) -+ crypto_unregister_all(sc->sc_cid); -+ if (sc->sc_irq != -1) -+ free_irq(sc->sc_irq, sc); -+ if (sc->sc_dma) { -+ /* Turn off DMA polling */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | -+ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); -+ -+ pci_free_consistent(sc->sc_pcidev, -+ sizeof(*sc->sc_dma), -+ sc->sc_dma, sc->sc_dma_physaddr); -+ } -+ kfree(sc); -+ return (-ENXIO); -+} -+ -+/* -+ * Detach an interface that successfully probed. -+ */ -+static void -+hifn_remove(struct pci_dev *dev) -+{ -+ struct hifn_softc *sc = pci_get_drvdata(dev); -+ unsigned long l_flags; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ KASSERT(sc != NULL, ("hifn_detach: null software carrier!")); -+ -+ /* disable interrupts */ -+ HIFN_LOCK(sc); -+ WRITE_REG_1(sc, HIFN_1_DMA_IER, 0); -+ HIFN_UNLOCK(sc); -+ -+ /*XXX other resources */ -+ del_timer_sync(&sc->sc_tickto); -+ -+ /* Turn off DMA polling */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | -+ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); -+ -+ crypto_unregister_all(sc->sc_cid); -+ -+ free_irq(sc->sc_irq, sc); -+ -+ pci_free_consistent(sc->sc_pcidev, sizeof(*sc->sc_dma), -+ sc->sc_dma, sc->sc_dma_physaddr); -+} -+ -+ -+static int -+hifn_init_pubrng(struct hifn_softc *sc) -+{ -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if ((sc->sc_flags & HIFN_IS_7811) == 0) { -+ /* Reset 7951 public key/rng engine */ -+ WRITE_REG_1(sc, HIFN_1_PUB_RESET, -+ READ_REG_1(sc, HIFN_1_PUB_RESET) | HIFN_PUBRST_RESET); -+ -+ for (i = 0; i < 100; i++) { -+ DELAY(1000); -+ if ((READ_REG_1(sc, HIFN_1_PUB_RESET) & -+ HIFN_PUBRST_RESET) == 0) -+ break; -+ } -+ -+ if (i == 100) { -+ device_printf(sc->sc_dev, "public key init failed\n"); -+ return (1); -+ } -+ } -+ -+ /* Enable the rng, if available */ -+#ifdef CONFIG_OCF_RANDOMHARVEST -+ if (sc->sc_flags & HIFN_HAS_RNG) { -+ if (sc->sc_flags & HIFN_IS_7811) { -+ u_int32_t r; -+ r = READ_REG_1(sc, HIFN_1_7811_RNGENA); -+ if (r & HIFN_7811_RNGENA_ENA) { -+ r &= ~HIFN_7811_RNGENA_ENA; -+ WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); -+ } -+ WRITE_REG_1(sc, HIFN_1_7811_RNGCFG, -+ HIFN_7811_RNGCFG_DEFL); -+ r |= HIFN_7811_RNGENA_ENA; -+ WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); -+ } else -+ WRITE_REG_1(sc, HIFN_1_RNG_CONFIG, -+ READ_REG_1(sc, HIFN_1_RNG_CONFIG) | -+ HIFN_RNGCFG_ENA); -+ -+ sc->sc_rngfirst = 1; -+ crypto_rregister(sc->sc_cid, hifn_read_random, sc); -+ } -+#endif -+ -+ /* Enable public key engine, if available */ -+ if (sc->sc_flags & HIFN_HAS_PUBLIC) { -+ WRITE_REG_1(sc, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE); -+ sc->sc_dmaier |= HIFN_DMAIER_PUBDONE; -+ WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); -+#ifdef HIFN_VULCANDEV -+ sc->sc_pkdev = make_dev(&vulcanpk_cdevsw, 0, -+ UID_ROOT, GID_WHEEL, 0666, -+ "vulcanpk"); -+ sc->sc_pkdev->si_drv1 = sc; -+#endif -+ } -+ -+ return (0); -+} -+ -+#ifdef CONFIG_OCF_RANDOMHARVEST -+static int -+hifn_read_random(void *arg, u_int32_t *buf, int len) -+{ -+ struct hifn_softc *sc = (struct hifn_softc *) arg; -+ u_int32_t sts; -+ int i, rc = 0; -+ -+ if (len <= 0) -+ return rc; -+ -+ if (sc->sc_flags & HIFN_IS_7811) { -+ /* ONLY VALID ON 7811!!!! */ -+ for (i = 0; i < 5; i++) { -+ sts = READ_REG_1(sc, HIFN_1_7811_RNGSTS); -+ if (sts & HIFN_7811_RNGSTS_UFL) { -+ device_printf(sc->sc_dev, -+ "RNG underflow: disabling\n"); -+ /* DAVIDM perhaps return -1 */ -+ break; -+ } -+ if ((sts & HIFN_7811_RNGSTS_RDY) == 0) -+ break; -+ -+ /* -+ * There are at least two words in the RNG FIFO -+ * at this point. -+ */ -+ if (rc < len) -+ buf[rc++] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); -+ if (rc < len) -+ buf[rc++] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); -+ } -+ } else -+ buf[rc++] = READ_REG_1(sc, HIFN_1_RNG_DATA); -+ -+ /* NB: discard first data read */ -+ if (sc->sc_rngfirst) { -+ sc->sc_rngfirst = 0; -+ rc = 0; -+ } -+ -+ return(rc); -+} -+#endif /* CONFIG_OCF_RANDOMHARVEST */ -+ -+static void -+hifn_puc_wait(struct hifn_softc *sc) -+{ -+ int i; -+ int reg = HIFN_0_PUCTRL; -+ -+ if (sc->sc_flags & HIFN_IS_7956) { -+ reg = HIFN_0_PUCTRL2; -+ } -+ -+ for (i = 5000; i > 0; i--) { -+ DELAY(1); -+ if (!(READ_REG_0(sc, reg) & HIFN_PUCTRL_RESET)) -+ break; -+ } -+ if (!i) -+ device_printf(sc->sc_dev, "proc unit did not reset(0x%x)\n", -+ READ_REG_0(sc, HIFN_0_PUCTRL)); -+} -+ -+/* -+ * Reset the processing unit. -+ */ -+static void -+hifn_reset_puc(struct hifn_softc *sc) -+{ -+ /* Reset processing unit */ -+ int reg = HIFN_0_PUCTRL; -+ -+ if (sc->sc_flags & HIFN_IS_7956) { -+ reg = HIFN_0_PUCTRL2; -+ } -+ WRITE_REG_0(sc, reg, HIFN_PUCTRL_DMAENA); -+ -+ hifn_puc_wait(sc); -+} -+ -+/* -+ * Set the Retry and TRDY registers; note that we set them to -+ * zero because the 7811 locks up when forced to retry (section -+ * 3.6 of "Specification Update SU-0014-04". Not clear if we -+ * should do this for all Hifn parts, but it doesn't seem to hurt. -+ */ -+static void -+hifn_set_retry(struct hifn_softc *sc) -+{ -+ DPRINTF("%s()\n", __FUNCTION__); -+ /* NB: RETRY only responds to 8-bit reads/writes */ -+ pci_write_config_byte(sc->sc_pcidev, HIFN_RETRY_TIMEOUT, 0); -+ pci_write_config_byte(sc->sc_pcidev, HIFN_TRDY_TIMEOUT, 0); -+ /* piggy back the cache line setting here */ -+ pci_write_config_byte(sc->sc_pcidev, PCI_CACHE_LINE_SIZE, hifn_cache_linesize); -+} -+ -+/* -+ * Resets the board. Values in the regesters are left as is -+ * from the reset (i.e. initial values are assigned elsewhere). -+ */ -+static void -+hifn_reset_board(struct hifn_softc *sc, int full) -+{ -+ u_int32_t reg; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ /* -+ * Set polling in the DMA configuration register to zero. 0x7 avoids -+ * resetting the board and zeros out the other fields. -+ */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | -+ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); -+ -+ /* -+ * Now that polling has been disabled, we have to wait 1 ms -+ * before resetting the board. -+ */ -+ DELAY(1000); -+ -+ /* Reset the DMA unit */ -+ if (full) { -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE); -+ DELAY(1000); -+ } else { -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, -+ HIFN_DMACNFG_MODE | HIFN_DMACNFG_MSTRESET); -+ hifn_reset_puc(sc); -+ } -+ -+ KASSERT(sc->sc_dma != NULL, ("hifn_reset_board: null DMA tag!")); -+ bzero(sc->sc_dma, sizeof(*sc->sc_dma)); -+ -+ /* Bring dma unit out of reset */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | -+ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); -+ -+ hifn_puc_wait(sc); -+ hifn_set_retry(sc); -+ -+ if (sc->sc_flags & HIFN_IS_7811) { -+ for (reg = 0; reg < 1000; reg++) { -+ if (READ_REG_1(sc, HIFN_1_7811_MIPSRST) & -+ HIFN_MIPSRST_CRAMINIT) -+ break; -+ DELAY(1000); -+ } -+ if (reg == 1000) -+ device_printf(sc->sc_dev, ": cram init timeout\n"); -+ } else { -+ /* set up DMA configuration register #2 */ -+ /* turn off all PK and BAR0 swaps */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG2, -+ (3 << HIFN_DMACNFG2_INIT_WRITE_BURST_SHIFT)| -+ (3 << HIFN_DMACNFG2_INIT_READ_BURST_SHIFT)| -+ (2 << HIFN_DMACNFG2_TGT_WRITE_BURST_SHIFT)| -+ (2 << HIFN_DMACNFG2_TGT_READ_BURST_SHIFT)); -+ } -+} -+ -+static u_int32_t -+hifn_next_signature(u_int32_t a, u_int cnt) -+{ -+ int i; -+ u_int32_t v; -+ -+ for (i = 0; i < cnt; i++) { -+ -+ /* get the parity */ -+ v = a & 0x80080125; -+ v ^= v >> 16; -+ v ^= v >> 8; -+ v ^= v >> 4; -+ v ^= v >> 2; -+ v ^= v >> 1; -+ -+ a = (v & 1) ^ (a << 1); -+ } -+ -+ return a; -+} -+ -+ -+/* -+ * Checks to see if crypto is already enabled. If crypto isn't enable, -+ * "hifn_enable_crypto" is called to enable it. The check is important, -+ * as enabling crypto twice will lock the board. -+ */ -+static int -+hifn_enable_crypto(struct hifn_softc *sc) -+{ -+ u_int32_t dmacfg, ramcfg, encl, addr, i; -+ char offtbl[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00 }; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ ramcfg = READ_REG_0(sc, HIFN_0_PUCNFG); -+ dmacfg = READ_REG_1(sc, HIFN_1_DMA_CNFG); -+ -+ /* -+ * The RAM config register's encrypt level bit needs to be set before -+ * every read performed on the encryption level register. -+ */ -+ WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); -+ -+ encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; -+ -+ /* -+ * Make sure we don't re-unlock. Two unlocks kills chip until the -+ * next reboot. -+ */ -+ if (encl == HIFN_PUSTAT_ENA_1 || encl == HIFN_PUSTAT_ENA_2) { -+#ifdef HIFN_DEBUG -+ if (hifn_debug) -+ device_printf(sc->sc_dev, -+ "Strong crypto already enabled!\n"); -+#endif -+ goto report; -+ } -+ -+ if (encl != 0 && encl != HIFN_PUSTAT_ENA_0) { -+#ifdef HIFN_DEBUG -+ if (hifn_debug) -+ device_printf(sc->sc_dev, -+ "Unknown encryption level 0x%x\n", encl); -+#endif -+ return 1; -+ } -+ -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_UNLOCK | -+ HIFN_DMACNFG_MSTRESET | HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); -+ DELAY(1000); -+ addr = READ_REG_1(sc, HIFN_UNLOCK_SECRET1); -+ DELAY(1000); -+ WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, 0); -+ DELAY(1000); -+ -+ for (i = 0; i <= 12; i++) { -+ addr = hifn_next_signature(addr, offtbl[i] + 0x101); -+ WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, addr); -+ -+ DELAY(1000); -+ } -+ -+ WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); -+ encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; -+ -+#ifdef HIFN_DEBUG -+ if (hifn_debug) { -+ if (encl != HIFN_PUSTAT_ENA_1 && encl != HIFN_PUSTAT_ENA_2) -+ device_printf(sc->sc_dev, "Engine is permanently " -+ "locked until next system reset!\n"); -+ else -+ device_printf(sc->sc_dev, "Engine enabled " -+ "successfully!\n"); -+ } -+#endif -+ -+report: -+ WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg); -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, dmacfg); -+ -+ switch (encl) { -+ case HIFN_PUSTAT_ENA_1: -+ case HIFN_PUSTAT_ENA_2: -+ break; -+ case HIFN_PUSTAT_ENA_0: -+ default: -+ device_printf(sc->sc_dev, "disabled\n"); -+ break; -+ } -+ -+ return 0; -+} -+ -+/* -+ * Give initial values to the registers listed in the "Register Space" -+ * section of the HIFN Software Development reference manual. -+ */ -+static void -+hifn_init_pci_registers(struct hifn_softc *sc) -+{ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ /* write fixed values needed by the Initialization registers */ -+ WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA); -+ WRITE_REG_0(sc, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD); -+ WRITE_REG_0(sc, HIFN_0_PUIER, HIFN_PUIER_DSTOVER); -+ -+ /* write all 4 ring address registers */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CRAR, sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, cmdr[0])); -+ WRITE_REG_1(sc, HIFN_1_DMA_SRAR, sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, srcr[0])); -+ WRITE_REG_1(sc, HIFN_1_DMA_DRAR, sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, dstr[0])); -+ WRITE_REG_1(sc, HIFN_1_DMA_RRAR, sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, resr[0])); -+ -+ DELAY(2000); -+ -+ /* write status register */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CSR, -+ HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS | -+ HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS | -+ HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST | -+ HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER | -+ HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST | -+ HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER | -+ HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST | -+ HIFN_DMACSR_S_WAIT | -+ HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST | -+ HIFN_DMACSR_C_WAIT | -+ HIFN_DMACSR_ENGINE | -+ ((sc->sc_flags & HIFN_HAS_PUBLIC) ? -+ HIFN_DMACSR_PUBDONE : 0) | -+ ((sc->sc_flags & HIFN_IS_7811) ? -+ HIFN_DMACSR_ILLW | HIFN_DMACSR_ILLR : 0)); -+ -+ sc->sc_d_busy = sc->sc_r_busy = sc->sc_s_busy = sc->sc_c_busy = 0; -+ sc->sc_dmaier |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT | -+ HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER | -+ HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT | -+ ((sc->sc_flags & HIFN_IS_7811) ? -+ HIFN_DMAIER_ILLW | HIFN_DMAIER_ILLR : 0); -+ sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; -+ WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); -+ -+ -+ if (sc->sc_flags & HIFN_IS_7956) { -+ u_int32_t pll; -+ -+ WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING | -+ HIFN_PUCNFG_TCALLPHASES | -+ HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32); -+ -+ /* turn off the clocks and insure bypass is set */ -+ pll = READ_REG_1(sc, HIFN_1_PLL); -+ pll = (pll &~ (HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL)) -+ | HIFN_PLL_BP | HIFN_PLL_MBSET; -+ WRITE_REG_1(sc, HIFN_1_PLL, pll); -+ DELAY(10*1000); /* 10ms */ -+ -+ /* change configuration */ -+ pll = (pll &~ HIFN_PLL_CONFIG) | sc->sc_pllconfig; -+ WRITE_REG_1(sc, HIFN_1_PLL, pll); -+ DELAY(10*1000); /* 10ms */ -+ -+ /* disable bypass */ -+ pll &= ~HIFN_PLL_BP; -+ WRITE_REG_1(sc, HIFN_1_PLL, pll); -+ /* enable clocks with new configuration */ -+ pll |= HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL; -+ WRITE_REG_1(sc, HIFN_1_PLL, pll); -+ } else { -+ WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING | -+ HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES | -+ HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 | -+ (sc->sc_drammodel ? HIFN_PUCNFG_DRAM : HIFN_PUCNFG_SRAM)); -+ } -+ -+ WRITE_REG_0(sc, HIFN_0_PUISR, HIFN_PUISR_DSTOVER); -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | -+ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST | -+ ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) | -+ ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL)); -+} -+ -+/* -+ * The maximum number of sessions supported by the card -+ * is dependent on the amount of context ram, which -+ * encryption algorithms are enabled, and how compression -+ * is configured. This should be configured before this -+ * routine is called. -+ */ -+static void -+hifn_sessions(struct hifn_softc *sc) -+{ -+ u_int32_t pucnfg; -+ int ctxsize; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ pucnfg = READ_REG_0(sc, HIFN_0_PUCNFG); -+ -+ if (pucnfg & HIFN_PUCNFG_COMPSING) { -+ if (pucnfg & HIFN_PUCNFG_ENCCNFG) -+ ctxsize = 128; -+ else -+ ctxsize = 512; -+ /* -+ * 7955/7956 has internal context memory of 32K -+ */ -+ if (sc->sc_flags & HIFN_IS_7956) -+ sc->sc_maxses = 32768 / ctxsize; -+ else -+ sc->sc_maxses = 1 + -+ ((sc->sc_ramsize - 32768) / ctxsize); -+ } else -+ sc->sc_maxses = sc->sc_ramsize / 16384; -+ -+ if (sc->sc_maxses > 2048) -+ sc->sc_maxses = 2048; -+} -+ -+/* -+ * Determine ram type (sram or dram). Board should be just out of a reset -+ * state when this is called. -+ */ -+static int -+hifn_ramtype(struct hifn_softc *sc) -+{ -+ u_int8_t data[8], dataexpect[8]; -+ int i; -+ -+ for (i = 0; i < sizeof(data); i++) -+ data[i] = dataexpect[i] = 0x55; -+ if (hifn_writeramaddr(sc, 0, data)) -+ return (-1); -+ if (hifn_readramaddr(sc, 0, data)) -+ return (-1); -+ if (bcmp(data, dataexpect, sizeof(data)) != 0) { -+ sc->sc_drammodel = 1; -+ return (0); -+ } -+ -+ for (i = 0; i < sizeof(data); i++) -+ data[i] = dataexpect[i] = 0xaa; -+ if (hifn_writeramaddr(sc, 0, data)) -+ return (-1); -+ if (hifn_readramaddr(sc, 0, data)) -+ return (-1); -+ if (bcmp(data, dataexpect, sizeof(data)) != 0) { -+ sc->sc_drammodel = 1; -+ return (0); -+ } -+ -+ return (0); -+} -+ -+#define HIFN_SRAM_MAX (32 << 20) -+#define HIFN_SRAM_STEP_SIZE 16384 -+#define HIFN_SRAM_GRANULARITY (HIFN_SRAM_MAX / HIFN_SRAM_STEP_SIZE) -+ -+static int -+hifn_sramsize(struct hifn_softc *sc) -+{ -+ u_int32_t a; -+ u_int8_t data[8]; -+ u_int8_t dataexpect[sizeof(data)]; -+ int32_t i; -+ -+ for (i = 0; i < sizeof(data); i++) -+ data[i] = dataexpect[i] = i ^ 0x5a; -+ -+ for (i = HIFN_SRAM_GRANULARITY - 1; i >= 0; i--) { -+ a = i * HIFN_SRAM_STEP_SIZE; -+ bcopy(&i, data, sizeof(i)); -+ hifn_writeramaddr(sc, a, data); -+ } -+ -+ for (i = 0; i < HIFN_SRAM_GRANULARITY; i++) { -+ a = i * HIFN_SRAM_STEP_SIZE; -+ bcopy(&i, dataexpect, sizeof(i)); -+ if (hifn_readramaddr(sc, a, data) < 0) -+ return (0); -+ if (bcmp(data, dataexpect, sizeof(data)) != 0) -+ return (0); -+ sc->sc_ramsize = a + HIFN_SRAM_STEP_SIZE; -+ } -+ -+ return (0); -+} -+ -+/* -+ * XXX For dram boards, one should really try all of the -+ * HIFN_PUCNFG_DSZ_*'s. This just assumes that PUCNFG -+ * is already set up correctly. -+ */ -+static int -+hifn_dramsize(struct hifn_softc *sc) -+{ -+ u_int32_t cnfg; -+ -+ if (sc->sc_flags & HIFN_IS_7956) { -+ /* -+ * 7955/7956 have a fixed internal ram of only 32K. -+ */ -+ sc->sc_ramsize = 32768; -+ } else { -+ cnfg = READ_REG_0(sc, HIFN_0_PUCNFG) & -+ HIFN_PUCNFG_DRAMMASK; -+ sc->sc_ramsize = 1 << ((cnfg >> 13) + 18); -+ } -+ return (0); -+} -+ -+static void -+hifn_alloc_slot(struct hifn_softc *sc, int *cmdp, int *srcp, int *dstp, int *resp) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (dma->cmdi == HIFN_D_CMD_RSIZE) { -+ dma->cmdi = 0; -+ dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); -+ wmb(); -+ dma->cmdr[HIFN_D_CMD_RSIZE].l |= htole32(HIFN_D_VALID); -+ HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, -+ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); -+ } -+ *cmdp = dma->cmdi++; -+ dma->cmdk = dma->cmdi; -+ -+ if (dma->srci == HIFN_D_SRC_RSIZE) { -+ dma->srci = 0; -+ dma->srcr[HIFN_D_SRC_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); -+ wmb(); -+ dma->srcr[HIFN_D_SRC_RSIZE].l |= htole32(HIFN_D_VALID); -+ HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, -+ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); -+ } -+ *srcp = dma->srci++; -+ dma->srck = dma->srci; -+ -+ if (dma->dsti == HIFN_D_DST_RSIZE) { -+ dma->dsti = 0; -+ dma->dstr[HIFN_D_DST_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); -+ wmb(); -+ dma->dstr[HIFN_D_DST_RSIZE].l |= htole32(HIFN_D_VALID); -+ HIFN_DSTR_SYNC(sc, HIFN_D_DST_RSIZE, -+ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); -+ } -+ *dstp = dma->dsti++; -+ dma->dstk = dma->dsti; -+ -+ if (dma->resi == HIFN_D_RES_RSIZE) { -+ dma->resi = 0; -+ dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); -+ wmb(); -+ dma->resr[HIFN_D_RES_RSIZE].l |= htole32(HIFN_D_VALID); -+ HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, -+ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); -+ } -+ *resp = dma->resi++; -+ dma->resk = dma->resi; -+} -+ -+static int -+hifn_writeramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ hifn_base_command_t wc; -+ const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; -+ int r, cmdi, resi, srci, dsti; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ wc.masks = htole16(3 << 13); -+ wc.session_num = htole16(addr >> 14); -+ wc.total_source_count = htole16(8); -+ wc.total_dest_count = htole16(addr & 0x3fff); -+ -+ hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); -+ -+ WRITE_REG_1(sc, HIFN_1_DMA_CSR, -+ HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | -+ HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); -+ -+ /* build write command */ -+ bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); -+ *(hifn_base_command_t *)dma->command_bufs[cmdi] = wc; -+ bcopy(data, &dma->test_src, sizeof(dma->test_src)); -+ -+ dma->srcr[srci].p = htole32(sc->sc_dma_physaddr -+ + offsetof(struct hifn_dma, test_src)); -+ dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr -+ + offsetof(struct hifn_dma, test_dst)); -+ -+ dma->cmdr[cmdi].l = htole32(16 | masks); -+ dma->srcr[srci].l = htole32(8 | masks); -+ dma->dstr[dsti].l = htole32(4 | masks); -+ dma->resr[resi].l = htole32(4 | masks); -+ -+ for (r = 10000; r >= 0; r--) { -+ DELAY(10); -+ if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) -+ break; -+ } -+ if (r == 0) { -+ device_printf(sc->sc_dev, "writeramaddr -- " -+ "result[%d](addr %d) still valid\n", resi, addr); -+ r = -1; -+ return (-1); -+ } else -+ r = 0; -+ -+ WRITE_REG_1(sc, HIFN_1_DMA_CSR, -+ HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | -+ HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); -+ -+ return (r); -+} -+ -+static int -+hifn_readramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ hifn_base_command_t rc; -+ const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; -+ int r, cmdi, srci, dsti, resi; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ rc.masks = htole16(2 << 13); -+ rc.session_num = htole16(addr >> 14); -+ rc.total_source_count = htole16(addr & 0x3fff); -+ rc.total_dest_count = htole16(8); -+ -+ hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); -+ -+ WRITE_REG_1(sc, HIFN_1_DMA_CSR, -+ HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | -+ HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); -+ -+ bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); -+ *(hifn_base_command_t *)dma->command_bufs[cmdi] = rc; -+ -+ dma->srcr[srci].p = htole32(sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, test_src)); -+ dma->test_src = 0; -+ dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, test_dst)); -+ dma->test_dst = 0; -+ dma->cmdr[cmdi].l = htole32(8 | masks); -+ dma->srcr[srci].l = htole32(8 | masks); -+ dma->dstr[dsti].l = htole32(8 | masks); -+ dma->resr[resi].l = htole32(HIFN_MAX_RESULT | masks); -+ -+ for (r = 10000; r >= 0; r--) { -+ DELAY(10); -+ if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) -+ break; -+ } -+ if (r == 0) { -+ device_printf(sc->sc_dev, "readramaddr -- " -+ "result[%d](addr %d) still valid\n", resi, addr); -+ r = -1; -+ } else { -+ r = 0; -+ bcopy(&dma->test_dst, data, sizeof(dma->test_dst)); -+ } -+ -+ WRITE_REG_1(sc, HIFN_1_DMA_CSR, -+ HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | -+ HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); -+ -+ return (r); -+} -+ -+/* -+ * Initialize the descriptor rings. -+ */ -+static void -+hifn_init_dma(struct hifn_softc *sc) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ hifn_set_retry(sc); -+ -+ /* initialize static pointer values */ -+ for (i = 0; i < HIFN_D_CMD_RSIZE; i++) -+ dma->cmdr[i].p = htole32(sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, command_bufs[i][0])); -+ for (i = 0; i < HIFN_D_RES_RSIZE; i++) -+ dma->resr[i].p = htole32(sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, result_bufs[i][0])); -+ -+ dma->cmdr[HIFN_D_CMD_RSIZE].p = -+ htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, cmdr[0])); -+ dma->srcr[HIFN_D_SRC_RSIZE].p = -+ htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, srcr[0])); -+ dma->dstr[HIFN_D_DST_RSIZE].p = -+ htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, dstr[0])); -+ dma->resr[HIFN_D_RES_RSIZE].p = -+ htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, resr[0])); -+ -+ dma->cmdu = dma->srcu = dma->dstu = dma->resu = 0; -+ dma->cmdi = dma->srci = dma->dsti = dma->resi = 0; -+ dma->cmdk = dma->srck = dma->dstk = dma->resk = 0; -+} -+ -+/* -+ * Writes out the raw command buffer space. Returns the -+ * command buffer size. -+ */ -+static u_int -+hifn_write_command(struct hifn_command *cmd, u_int8_t *buf) -+{ -+ struct hifn_softc *sc = NULL; -+ u_int8_t *buf_pos; -+ hifn_base_command_t *base_cmd; -+ hifn_mac_command_t *mac_cmd; -+ hifn_crypt_command_t *cry_cmd; -+ int using_mac, using_crypt, len, ivlen; -+ u_int32_t dlen, slen; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ buf_pos = buf; -+ using_mac = cmd->base_masks & HIFN_BASE_CMD_MAC; -+ using_crypt = cmd->base_masks & HIFN_BASE_CMD_CRYPT; -+ -+ base_cmd = (hifn_base_command_t *)buf_pos; -+ base_cmd->masks = htole16(cmd->base_masks); -+ slen = cmd->src_mapsize; -+ if (cmd->sloplen) -+ dlen = cmd->dst_mapsize - cmd->sloplen + sizeof(u_int32_t); -+ else -+ dlen = cmd->dst_mapsize; -+ base_cmd->total_source_count = htole16(slen & HIFN_BASE_CMD_LENMASK_LO); -+ base_cmd->total_dest_count = htole16(dlen & HIFN_BASE_CMD_LENMASK_LO); -+ dlen >>= 16; -+ slen >>= 16; -+ base_cmd->session_num = htole16( -+ ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) | -+ ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M)); -+ buf_pos += sizeof(hifn_base_command_t); -+ -+ if (using_mac) { -+ mac_cmd = (hifn_mac_command_t *)buf_pos; -+ dlen = cmd->maccrd->crd_len; -+ mac_cmd->source_count = htole16(dlen & 0xffff); -+ dlen >>= 16; -+ mac_cmd->masks = htole16(cmd->mac_masks | -+ ((dlen << HIFN_MAC_CMD_SRCLEN_S) & HIFN_MAC_CMD_SRCLEN_M)); -+ mac_cmd->header_skip = htole16(cmd->maccrd->crd_skip); -+ mac_cmd->reserved = 0; -+ buf_pos += sizeof(hifn_mac_command_t); -+ } -+ -+ if (using_crypt) { -+ cry_cmd = (hifn_crypt_command_t *)buf_pos; -+ dlen = cmd->enccrd->crd_len; -+ cry_cmd->source_count = htole16(dlen & 0xffff); -+ dlen >>= 16; -+ cry_cmd->masks = htole16(cmd->cry_masks | -+ ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) & HIFN_CRYPT_CMD_SRCLEN_M)); -+ cry_cmd->header_skip = htole16(cmd->enccrd->crd_skip); -+ cry_cmd->reserved = 0; -+ buf_pos += sizeof(hifn_crypt_command_t); -+ } -+ -+ if (using_mac && cmd->mac_masks & HIFN_MAC_CMD_NEW_KEY) { -+ bcopy(cmd->mac, buf_pos, HIFN_MAC_KEY_LENGTH); -+ buf_pos += HIFN_MAC_KEY_LENGTH; -+ } -+ -+ if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_KEY) { -+ switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) { -+ case HIFN_CRYPT_CMD_ALG_3DES: -+ bcopy(cmd->ck, buf_pos, HIFN_3DES_KEY_LENGTH); -+ buf_pos += HIFN_3DES_KEY_LENGTH; -+ break; -+ case HIFN_CRYPT_CMD_ALG_DES: -+ bcopy(cmd->ck, buf_pos, HIFN_DES_KEY_LENGTH); -+ buf_pos += HIFN_DES_KEY_LENGTH; -+ break; -+ case HIFN_CRYPT_CMD_ALG_RC4: -+ len = 256; -+ do { -+ int clen; -+ -+ clen = MIN(cmd->cklen, len); -+ bcopy(cmd->ck, buf_pos, clen); -+ len -= clen; -+ buf_pos += clen; -+ } while (len > 0); -+ bzero(buf_pos, 4); -+ buf_pos += 4; -+ break; -+ case HIFN_CRYPT_CMD_ALG_AES: -+ /* -+ * AES keys are variable 128, 192 and -+ * 256 bits (16, 24 and 32 bytes). -+ */ -+ bcopy(cmd->ck, buf_pos, cmd->cklen); -+ buf_pos += cmd->cklen; -+ break; -+ } -+ } -+ -+ if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_IV) { -+ switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) { -+ case HIFN_CRYPT_CMD_ALG_AES: -+ ivlen = HIFN_AES_IV_LENGTH; -+ break; -+ default: -+ ivlen = HIFN_IV_LENGTH; -+ break; -+ } -+ bcopy(cmd->iv, buf_pos, ivlen); -+ buf_pos += ivlen; -+ } -+ -+ if ((cmd->base_masks & (HIFN_BASE_CMD_MAC|HIFN_BASE_CMD_CRYPT)) == 0) { -+ bzero(buf_pos, 8); -+ buf_pos += 8; -+ } -+ -+ return (buf_pos - buf); -+} -+ -+static int -+hifn_dmamap_aligned(struct hifn_operand *op) -+{ -+ struct hifn_softc *sc = NULL; -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ for (i = 0; i < op->nsegs; i++) { -+ if (op->segs[i].ds_addr & 3) -+ return (0); -+ if ((i != (op->nsegs - 1)) && (op->segs[i].ds_len & 3)) -+ return (0); -+ } -+ return (1); -+} -+ -+static __inline int -+hifn_dmamap_dstwrap(struct hifn_softc *sc, int idx) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ -+ if (++idx == HIFN_D_DST_RSIZE) { -+ dma->dstr[idx].l = htole32(HIFN_D_VALID | HIFN_D_JUMP | -+ HIFN_D_MASKDONEIRQ); -+ HIFN_DSTR_SYNC(sc, idx, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ idx = 0; -+ } -+ return (idx); -+} -+ -+static int -+hifn_dmamap_load_dst(struct hifn_softc *sc, struct hifn_command *cmd) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ struct hifn_operand *dst = &cmd->dst; -+ u_int32_t p, l; -+ int idx, used = 0, i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ idx = dma->dsti; -+ for (i = 0; i < dst->nsegs - 1; i++) { -+ dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); -+ dma->dstr[idx].l = htole32(HIFN_D_MASKDONEIRQ | dst->segs[i].ds_len); -+ wmb(); -+ dma->dstr[idx].l |= htole32(HIFN_D_VALID); -+ HIFN_DSTR_SYNC(sc, idx, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ used++; -+ -+ idx = hifn_dmamap_dstwrap(sc, idx); -+ } -+ -+ if (cmd->sloplen == 0) { -+ p = dst->segs[i].ds_addr; -+ l = HIFN_D_MASKDONEIRQ | HIFN_D_LAST | -+ dst->segs[i].ds_len; -+ } else { -+ p = sc->sc_dma_physaddr + -+ offsetof(struct hifn_dma, slop[cmd->slopidx]); -+ l = HIFN_D_MASKDONEIRQ | HIFN_D_LAST | -+ sizeof(u_int32_t); -+ -+ if ((dst->segs[i].ds_len - cmd->sloplen) != 0) { -+ dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); -+ dma->dstr[idx].l = htole32(HIFN_D_MASKDONEIRQ | -+ (dst->segs[i].ds_len - cmd->sloplen)); -+ wmb(); -+ dma->dstr[idx].l |= htole32(HIFN_D_VALID); -+ HIFN_DSTR_SYNC(sc, idx, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ used++; -+ -+ idx = hifn_dmamap_dstwrap(sc, idx); -+ } -+ } -+ dma->dstr[idx].p = htole32(p); -+ dma->dstr[idx].l = htole32(l); -+ wmb(); -+ dma->dstr[idx].l |= htole32(HIFN_D_VALID); -+ HIFN_DSTR_SYNC(sc, idx, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ used++; -+ -+ idx = hifn_dmamap_dstwrap(sc, idx); -+ -+ dma->dsti = idx; -+ dma->dstu += used; -+ return (idx); -+} -+ -+static __inline int -+hifn_dmamap_srcwrap(struct hifn_softc *sc, int idx) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ -+ if (++idx == HIFN_D_SRC_RSIZE) { -+ dma->srcr[idx].l = htole32(HIFN_D_VALID | -+ HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); -+ HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, -+ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); -+ idx = 0; -+ } -+ return (idx); -+} -+ -+static int -+hifn_dmamap_load_src(struct hifn_softc *sc, struct hifn_command *cmd) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ struct hifn_operand *src = &cmd->src; -+ int idx, i; -+ u_int32_t last = 0; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ idx = dma->srci; -+ for (i = 0; i < src->nsegs; i++) { -+ if (i == src->nsegs - 1) -+ last = HIFN_D_LAST; -+ -+ dma->srcr[idx].p = htole32(src->segs[i].ds_addr); -+ dma->srcr[idx].l = htole32(src->segs[i].ds_len | -+ HIFN_D_MASKDONEIRQ | last); -+ wmb(); -+ dma->srcr[idx].l |= htole32(HIFN_D_VALID); -+ HIFN_SRCR_SYNC(sc, idx, -+ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); -+ -+ idx = hifn_dmamap_srcwrap(sc, idx); -+ } -+ dma->srci = idx; -+ dma->srcu += src->nsegs; -+ return (idx); -+} -+ -+ -+static int -+hifn_crypto( -+ struct hifn_softc *sc, -+ struct hifn_command *cmd, -+ struct cryptop *crp, -+ int hint) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ u_int32_t cmdlen, csr; -+ int cmdi, resi, err = 0; -+ unsigned long l_flags; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ /* -+ * need 1 cmd, and 1 res -+ * -+ * NB: check this first since it's easy. -+ */ -+ HIFN_LOCK(sc); -+ if ((dma->cmdu + 1) > HIFN_D_CMD_RSIZE || -+ (dma->resu + 1) > HIFN_D_RES_RSIZE) { -+#ifdef HIFN_DEBUG -+ if (hifn_debug) { -+ device_printf(sc->sc_dev, -+ "cmd/result exhaustion, cmdu %u resu %u\n", -+ dma->cmdu, dma->resu); -+ } -+#endif -+ hifnstats.hst_nomem_cr++; -+ sc->sc_needwakeup |= CRYPTO_SYMQ; -+ HIFN_UNLOCK(sc); -+ return (ERESTART); -+ } -+ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ if (pci_map_skb(sc, &cmd->src, cmd->src_skb)) { -+ hifnstats.hst_nomem_load++; -+ err = ENOMEM; -+ goto err_srcmap1; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ if (pci_map_uio(sc, &cmd->src, cmd->src_io)) { -+ hifnstats.hst_nomem_load++; -+ err = ENOMEM; -+ goto err_srcmap1; -+ } -+ } else { -+ if (pci_map_buf(sc, &cmd->src, cmd->src_buf, crp->crp_ilen)) { -+ hifnstats.hst_nomem_load++; -+ err = ENOMEM; -+ goto err_srcmap1; -+ } -+ } -+ -+ if (hifn_dmamap_aligned(&cmd->src)) { -+ cmd->sloplen = cmd->src_mapsize & 3; -+ cmd->dst = cmd->src; -+ } else { -+ if (crp->crp_flags & CRYPTO_F_IOV) { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ err = EINVAL; -+ goto err_srcmap; -+ } else if (crp->crp_flags & CRYPTO_F_SKBUF) { -+#ifdef NOTYET -+ int totlen, len; -+ struct mbuf *m, *m0, *mlast; -+ -+ KASSERT(cmd->dst_m == cmd->src_m, -+ ("hifn_crypto: dst_m initialized improperly")); -+ hifnstats.hst_unaligned++; -+ /* -+ * Source is not aligned on a longword boundary. -+ * Copy the data to insure alignment. If we fail -+ * to allocate mbufs or clusters while doing this -+ * we return ERESTART so the operation is requeued -+ * at the crypto later, but only if there are -+ * ops already posted to the hardware; otherwise we -+ * have no guarantee that we'll be re-entered. -+ */ -+ totlen = cmd->src_mapsize; -+ if (cmd->src_m->m_flags & M_PKTHDR) { -+ len = MHLEN; -+ MGETHDR(m0, M_DONTWAIT, MT_DATA); -+ if (m0 && !m_dup_pkthdr(m0, cmd->src_m, M_DONTWAIT)) { -+ m_free(m0); -+ m0 = NULL; -+ } -+ } else { -+ len = MLEN; -+ MGET(m0, M_DONTWAIT, MT_DATA); -+ } -+ if (m0 == NULL) { -+ hifnstats.hst_nomem_mbuf++; -+ err = dma->cmdu ? ERESTART : ENOMEM; -+ goto err_srcmap; -+ } -+ if (totlen >= MINCLSIZE) { -+ MCLGET(m0, M_DONTWAIT); -+ if ((m0->m_flags & M_EXT) == 0) { -+ hifnstats.hst_nomem_mcl++; -+ err = dma->cmdu ? ERESTART : ENOMEM; -+ m_freem(m0); -+ goto err_srcmap; -+ } -+ len = MCLBYTES; -+ } -+ totlen -= len; -+ m0->m_pkthdr.len = m0->m_len = len; -+ mlast = m0; -+ -+ while (totlen > 0) { -+ MGET(m, M_DONTWAIT, MT_DATA); -+ if (m == NULL) { -+ hifnstats.hst_nomem_mbuf++; -+ err = dma->cmdu ? ERESTART : ENOMEM; -+ m_freem(m0); -+ goto err_srcmap; -+ } -+ len = MLEN; -+ if (totlen >= MINCLSIZE) { -+ MCLGET(m, M_DONTWAIT); -+ if ((m->m_flags & M_EXT) == 0) { -+ hifnstats.hst_nomem_mcl++; -+ err = dma->cmdu ? ERESTART : ENOMEM; -+ mlast->m_next = m; -+ m_freem(m0); -+ goto err_srcmap; -+ } -+ len = MCLBYTES; -+ } -+ -+ m->m_len = len; -+ m0->m_pkthdr.len += len; -+ totlen -= len; -+ -+ mlast->m_next = m; -+ mlast = m; -+ } -+ cmd->dst_m = m0; -+#else -+ device_printf(sc->sc_dev, -+ "%s,%d: CRYPTO_F_SKBUF unaligned not implemented\n", -+ __FILE__, __LINE__); -+ err = EINVAL; -+ goto err_srcmap; -+#endif -+ } else { -+ device_printf(sc->sc_dev, -+ "%s,%d: unaligned contig buffers not implemented\n", -+ __FILE__, __LINE__); -+ err = EINVAL; -+ goto err_srcmap; -+ } -+ } -+ -+ if (cmd->dst_map == NULL) { -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ if (pci_map_skb(sc, &cmd->dst, cmd->dst_skb)) { -+ hifnstats.hst_nomem_map++; -+ err = ENOMEM; -+ goto err_dstmap1; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ if (pci_map_uio(sc, &cmd->dst, cmd->dst_io)) { -+ hifnstats.hst_nomem_load++; -+ err = ENOMEM; -+ goto err_dstmap1; -+ } -+ } else { -+ if (pci_map_buf(sc, &cmd->dst, cmd->dst_buf, crp->crp_ilen)) { -+ hifnstats.hst_nomem_load++; -+ err = ENOMEM; -+ goto err_dstmap1; -+ } -+ } -+ } -+ -+#ifdef HIFN_DEBUG -+ if (hifn_debug) { -+ device_printf(sc->sc_dev, -+ "Entering cmd: stat %8x ien %8x u %d/%d/%d/%d n %d/%d\n", -+ READ_REG_1(sc, HIFN_1_DMA_CSR), -+ READ_REG_1(sc, HIFN_1_DMA_IER), -+ dma->cmdu, dma->srcu, dma->dstu, dma->resu, -+ cmd->src_nsegs, cmd->dst_nsegs); -+ } -+#endif -+ -+#if 0 -+ if (cmd->src_map == cmd->dst_map) { -+ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, -+ BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); -+ } else { -+ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, -+ BUS_DMASYNC_PREWRITE); -+ bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, -+ BUS_DMASYNC_PREREAD); -+ } -+#endif -+ -+ /* -+ * need N src, and N dst -+ */ -+ if ((dma->srcu + cmd->src_nsegs) > HIFN_D_SRC_RSIZE || -+ (dma->dstu + cmd->dst_nsegs + 1) > HIFN_D_DST_RSIZE) { -+#ifdef HIFN_DEBUG -+ if (hifn_debug) { -+ device_printf(sc->sc_dev, -+ "src/dst exhaustion, srcu %u+%u dstu %u+%u\n", -+ dma->srcu, cmd->src_nsegs, -+ dma->dstu, cmd->dst_nsegs); -+ } -+#endif -+ hifnstats.hst_nomem_sd++; -+ err = ERESTART; -+ goto err_dstmap; -+ } -+ -+ if (dma->cmdi == HIFN_D_CMD_RSIZE) { -+ dma->cmdi = 0; -+ dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); -+ wmb(); -+ dma->cmdr[HIFN_D_CMD_RSIZE].l |= htole32(HIFN_D_VALID); -+ HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, -+ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); -+ } -+ cmdi = dma->cmdi++; -+ cmdlen = hifn_write_command(cmd, dma->command_bufs[cmdi]); -+ HIFN_CMD_SYNC(sc, cmdi, BUS_DMASYNC_PREWRITE); -+ -+ /* .p for command/result already set */ -+ dma->cmdr[cmdi].l = htole32(cmdlen | HIFN_D_LAST | -+ HIFN_D_MASKDONEIRQ); -+ wmb(); -+ dma->cmdr[cmdi].l |= htole32(HIFN_D_VALID); -+ HIFN_CMDR_SYNC(sc, cmdi, -+ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); -+ dma->cmdu++; -+ -+ /* -+ * We don't worry about missing an interrupt (which a "command wait" -+ * interrupt salvages us from), unless there is more than one command -+ * in the queue. -+ */ -+ if (dma->cmdu > 1) { -+ sc->sc_dmaier |= HIFN_DMAIER_C_WAIT; -+ WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); -+ } -+ -+ hifnstats.hst_ipackets++; -+ hifnstats.hst_ibytes += cmd->src_mapsize; -+ -+ hifn_dmamap_load_src(sc, cmd); -+ -+ /* -+ * Unlike other descriptors, we don't mask done interrupt from -+ * result descriptor. -+ */ -+#ifdef HIFN_DEBUG -+ if (hifn_debug) -+ device_printf(sc->sc_dev, "load res\n"); -+#endif -+ if (dma->resi == HIFN_D_RES_RSIZE) { -+ dma->resi = 0; -+ dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); -+ wmb(); -+ dma->resr[HIFN_D_RES_RSIZE].l |= htole32(HIFN_D_VALID); -+ HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ } -+ resi = dma->resi++; -+ KASSERT(dma->hifn_commands[resi] == NULL, -+ ("hifn_crypto: command slot %u busy", resi)); -+ dma->hifn_commands[resi] = cmd; -+ HIFN_RES_SYNC(sc, resi, BUS_DMASYNC_PREREAD); -+ if ((hint & CRYPTO_HINT_MORE) && sc->sc_curbatch < hifn_maxbatch) { -+ dma->resr[resi].l = htole32(HIFN_MAX_RESULT | -+ HIFN_D_LAST | HIFN_D_MASKDONEIRQ); -+ wmb(); -+ dma->resr[resi].l |= htole32(HIFN_D_VALID); -+ sc->sc_curbatch++; -+ if (sc->sc_curbatch > hifnstats.hst_maxbatch) -+ hifnstats.hst_maxbatch = sc->sc_curbatch; -+ hifnstats.hst_totbatch++; -+ } else { -+ dma->resr[resi].l = htole32(HIFN_MAX_RESULT | HIFN_D_LAST); -+ wmb(); -+ dma->resr[resi].l |= htole32(HIFN_D_VALID); -+ sc->sc_curbatch = 0; -+ } -+ HIFN_RESR_SYNC(sc, resi, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ dma->resu++; -+ -+ if (cmd->sloplen) -+ cmd->slopidx = resi; -+ -+ hifn_dmamap_load_dst(sc, cmd); -+ -+ csr = 0; -+ if (sc->sc_c_busy == 0) { -+ csr |= HIFN_DMACSR_C_CTRL_ENA; -+ sc->sc_c_busy = 1; -+ } -+ if (sc->sc_s_busy == 0) { -+ csr |= HIFN_DMACSR_S_CTRL_ENA; -+ sc->sc_s_busy = 1; -+ } -+ if (sc->sc_r_busy == 0) { -+ csr |= HIFN_DMACSR_R_CTRL_ENA; -+ sc->sc_r_busy = 1; -+ } -+ if (sc->sc_d_busy == 0) { -+ csr |= HIFN_DMACSR_D_CTRL_ENA; -+ sc->sc_d_busy = 1; -+ } -+ if (csr) -+ WRITE_REG_1(sc, HIFN_1_DMA_CSR, csr); -+ -+#ifdef HIFN_DEBUG -+ if (hifn_debug) { -+ device_printf(sc->sc_dev, "command: stat %8x ier %8x\n", -+ READ_REG_1(sc, HIFN_1_DMA_CSR), -+ READ_REG_1(sc, HIFN_1_DMA_IER)); -+ } -+#endif -+ -+ sc->sc_active = 5; -+ HIFN_UNLOCK(sc); -+ KASSERT(err == 0, ("hifn_crypto: success with error %u", err)); -+ return (err); /* success */ -+ -+err_dstmap: -+ if (cmd->src_map != cmd->dst_map) -+ pci_unmap_buf(sc, &cmd->dst); -+err_dstmap1: -+err_srcmap: -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ if (cmd->src_skb != cmd->dst_skb) -+#ifdef NOTYET -+ m_freem(cmd->dst_m); -+#else -+ device_printf(sc->sc_dev, -+ "%s,%d: CRYPTO_F_SKBUF src != dst not implemented\n", -+ __FILE__, __LINE__); -+#endif -+ } -+ pci_unmap_buf(sc, &cmd->src); -+err_srcmap1: -+ HIFN_UNLOCK(sc); -+ return (err); -+} -+ -+static void -+hifn_tick(unsigned long arg) -+{ -+ struct hifn_softc *sc; -+ unsigned long l_flags; -+ -+ if (arg >= HIFN_MAX_CHIPS) -+ return; -+ sc = hifn_chip_idx[arg]; -+ if (!sc) -+ return; -+ -+ HIFN_LOCK(sc); -+ if (sc->sc_active == 0) { -+ struct hifn_dma *dma = sc->sc_dma; -+ u_int32_t r = 0; -+ -+ if (dma->cmdu == 0 && sc->sc_c_busy) { -+ sc->sc_c_busy = 0; -+ r |= HIFN_DMACSR_C_CTRL_DIS; -+ } -+ if (dma->srcu == 0 && sc->sc_s_busy) { -+ sc->sc_s_busy = 0; -+ r |= HIFN_DMACSR_S_CTRL_DIS; -+ } -+ if (dma->dstu == 0 && sc->sc_d_busy) { -+ sc->sc_d_busy = 0; -+ r |= HIFN_DMACSR_D_CTRL_DIS; -+ } -+ if (dma->resu == 0 && sc->sc_r_busy) { -+ sc->sc_r_busy = 0; -+ r |= HIFN_DMACSR_R_CTRL_DIS; -+ } -+ if (r) -+ WRITE_REG_1(sc, HIFN_1_DMA_CSR, r); -+ } else -+ sc->sc_active--; -+ HIFN_UNLOCK(sc); -+ mod_timer(&sc->sc_tickto, jiffies + HZ); -+} -+ -+static irqreturn_t -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) -+hifn_intr(int irq, void *arg) -+#else -+hifn_intr(int irq, void *arg, struct pt_regs *regs) -+#endif -+{ -+ struct hifn_softc *sc = arg; -+ struct hifn_dma *dma; -+ u_int32_t dmacsr, restart; -+ int i, u; -+ unsigned long l_flags; -+ -+ dmacsr = READ_REG_1(sc, HIFN_1_DMA_CSR); -+ -+ /* Nothing in the DMA unit interrupted */ -+ if ((dmacsr & sc->sc_dmaier) == 0) -+ return IRQ_NONE; -+ -+ HIFN_LOCK(sc); -+ -+ dma = sc->sc_dma; -+ -+#ifdef HIFN_DEBUG -+ if (hifn_debug) { -+ device_printf(sc->sc_dev, -+ "irq: stat %08x ien %08x damier %08x i %d/%d/%d/%d k %d/%d/%d/%d u %d/%d/%d/%d\n", -+ dmacsr, READ_REG_1(sc, HIFN_1_DMA_IER), sc->sc_dmaier, -+ dma->cmdi, dma->srci, dma->dsti, dma->resi, -+ dma->cmdk, dma->srck, dma->dstk, dma->resk, -+ dma->cmdu, dma->srcu, dma->dstu, dma->resu); -+ } -+#endif -+ -+ WRITE_REG_1(sc, HIFN_1_DMA_CSR, dmacsr & sc->sc_dmaier); -+ -+ if ((sc->sc_flags & HIFN_HAS_PUBLIC) && -+ (dmacsr & HIFN_DMACSR_PUBDONE)) -+ WRITE_REG_1(sc, HIFN_1_PUB_STATUS, -+ READ_REG_1(sc, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE); -+ -+ restart = dmacsr & (HIFN_DMACSR_D_OVER | HIFN_DMACSR_R_OVER); -+ if (restart) -+ device_printf(sc->sc_dev, "overrun %x\n", dmacsr); -+ -+ if (sc->sc_flags & HIFN_IS_7811) { -+ if (dmacsr & HIFN_DMACSR_ILLR) -+ device_printf(sc->sc_dev, "illegal read\n"); -+ if (dmacsr & HIFN_DMACSR_ILLW) -+ device_printf(sc->sc_dev, "illegal write\n"); -+ } -+ -+ restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT | -+ HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT); -+ if (restart) { -+ device_printf(sc->sc_dev, "abort, resetting.\n"); -+ hifnstats.hst_abort++; -+ hifn_abort(sc); -+ HIFN_UNLOCK(sc); -+ return IRQ_HANDLED; -+ } -+ -+ if ((dmacsr & HIFN_DMACSR_C_WAIT) && (dma->cmdu == 0)) { -+ /* -+ * If no slots to process and we receive a "waiting on -+ * command" interrupt, we disable the "waiting on command" -+ * (by clearing it). -+ */ -+ sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; -+ WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); -+ } -+ -+ /* clear the rings */ -+ i = dma->resk; u = dma->resu; -+ while (u != 0) { -+ HIFN_RESR_SYNC(sc, i, -+ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); -+ if (dma->resr[i].l & htole32(HIFN_D_VALID)) { -+ HIFN_RESR_SYNC(sc, i, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ break; -+ } -+ -+ if (i != HIFN_D_RES_RSIZE) { -+ struct hifn_command *cmd; -+ u_int8_t *macbuf = NULL; -+ -+ HIFN_RES_SYNC(sc, i, BUS_DMASYNC_POSTREAD); -+ cmd = dma->hifn_commands[i]; -+ KASSERT(cmd != NULL, -+ ("hifn_intr: null command slot %u", i)); -+ dma->hifn_commands[i] = NULL; -+ -+ if (cmd->base_masks & HIFN_BASE_CMD_MAC) { -+ macbuf = dma->result_bufs[i]; -+ macbuf += 12; -+ } -+ -+ hifn_callback(sc, cmd, macbuf); -+ hifnstats.hst_opackets++; -+ u--; -+ } -+ -+ if (++i == (HIFN_D_RES_RSIZE + 1)) -+ i = 0; -+ } -+ dma->resk = i; dma->resu = u; -+ -+ i = dma->srck; u = dma->srcu; -+ while (u != 0) { -+ if (i == HIFN_D_SRC_RSIZE) -+ i = 0; -+ HIFN_SRCR_SYNC(sc, i, -+ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); -+ if (dma->srcr[i].l & htole32(HIFN_D_VALID)) { -+ HIFN_SRCR_SYNC(sc, i, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ break; -+ } -+ i++, u--; -+ } -+ dma->srck = i; dma->srcu = u; -+ -+ i = dma->cmdk; u = dma->cmdu; -+ while (u != 0) { -+ HIFN_CMDR_SYNC(sc, i, -+ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); -+ if (dma->cmdr[i].l & htole32(HIFN_D_VALID)) { -+ HIFN_CMDR_SYNC(sc, i, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+ break; -+ } -+ if (i != HIFN_D_CMD_RSIZE) { -+ u--; -+ HIFN_CMD_SYNC(sc, i, BUS_DMASYNC_POSTWRITE); -+ } -+ if (++i == (HIFN_D_CMD_RSIZE + 1)) -+ i = 0; -+ } -+ dma->cmdk = i; dma->cmdu = u; -+ -+ HIFN_UNLOCK(sc); -+ -+ if (sc->sc_needwakeup) { /* XXX check high watermark */ -+ int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); -+#ifdef HIFN_DEBUG -+ if (hifn_debug) -+ device_printf(sc->sc_dev, -+ "wakeup crypto (%x) u %d/%d/%d/%d\n", -+ sc->sc_needwakeup, -+ dma->cmdu, dma->srcu, dma->dstu, dma->resu); -+#endif -+ sc->sc_needwakeup &= ~wakeup; -+ crypto_unblock(sc->sc_cid, wakeup); -+ } -+ -+ return IRQ_HANDLED; -+} -+ -+/* -+ * Allocate a new 'session' and return an encoded session id. 'sidp' -+ * contains our registration id, and should contain an encoded session -+ * id on successful allocation. -+ */ -+static int -+hifn_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) -+{ -+ struct hifn_softc *sc = device_get_softc(dev); -+ struct cryptoini *c; -+ int mac = 0, cry = 0, sesn; -+ struct hifn_session *ses = NULL; -+ unsigned long l_flags; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ KASSERT(sc != NULL, ("hifn_newsession: null softc")); -+ if (sidp == NULL || cri == NULL || sc == NULL) { -+ DPRINTF("%s,%d: %s - EINVAL\n", __FILE__, __LINE__, __FUNCTION__); -+ return (EINVAL); -+ } -+ -+ HIFN_LOCK(sc); -+ if (sc->sc_sessions == NULL) { -+ ses = sc->sc_sessions = (struct hifn_session *)kmalloc(sizeof(*ses), -+ SLAB_ATOMIC); -+ if (ses == NULL) { -+ HIFN_UNLOCK(sc); -+ return (ENOMEM); -+ } -+ sesn = 0; -+ sc->sc_nsessions = 1; -+ } else { -+ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { -+ if (!sc->sc_sessions[sesn].hs_used) { -+ ses = &sc->sc_sessions[sesn]; -+ break; -+ } -+ } -+ -+ if (ses == NULL) { -+ sesn = sc->sc_nsessions; -+ ses = (struct hifn_session *)kmalloc((sesn + 1) * sizeof(*ses), -+ SLAB_ATOMIC); -+ if (ses == NULL) { -+ HIFN_UNLOCK(sc); -+ return (ENOMEM); -+ } -+ bcopy(sc->sc_sessions, ses, sesn * sizeof(*ses)); -+ bzero(sc->sc_sessions, sesn * sizeof(*ses)); -+ kfree(sc->sc_sessions); -+ sc->sc_sessions = ses; -+ ses = &sc->sc_sessions[sesn]; -+ sc->sc_nsessions++; -+ } -+ } -+ HIFN_UNLOCK(sc); -+ -+ bzero(ses, sizeof(*ses)); -+ ses->hs_used = 1; -+ -+ for (c = cri; c != NULL; c = c->cri_next) { -+ switch (c->cri_alg) { -+ case CRYPTO_MD5: -+ case CRYPTO_SHA1: -+ case CRYPTO_MD5_HMAC: -+ case CRYPTO_SHA1_HMAC: -+ if (mac) { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ return (EINVAL); -+ } -+ mac = 1; -+ ses->hs_mlen = c->cri_mlen; -+ if (ses->hs_mlen == 0) { -+ switch (c->cri_alg) { -+ case CRYPTO_MD5: -+ case CRYPTO_MD5_HMAC: -+ ses->hs_mlen = 16; -+ break; -+ case CRYPTO_SHA1: -+ case CRYPTO_SHA1_HMAC: -+ ses->hs_mlen = 20; -+ break; -+ } -+ } -+ break; -+ case CRYPTO_DES_CBC: -+ case CRYPTO_3DES_CBC: -+ case CRYPTO_AES_CBC: -+ case CRYPTO_ARC4: -+ if (cry) { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ return (EINVAL); -+ } -+ cry = 1; -+ break; -+ default: -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ return (EINVAL); -+ } -+ } -+ if (mac == 0 && cry == 0) { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ return (EINVAL); -+ } -+ -+ *sidp = HIFN_SID(device_get_unit(sc->sc_dev), sesn); -+ -+ return (0); -+} -+ -+/* -+ * Deallocate a session. -+ * XXX this routine should run a zero'd mac/encrypt key into context ram. -+ * XXX to blow away any keys already stored there. -+ */ -+static int -+hifn_freesession(device_t dev, u_int64_t tid) -+{ -+ struct hifn_softc *sc = device_get_softc(dev); -+ int session, error; -+ u_int32_t sid = CRYPTO_SESID2LID(tid); -+ unsigned long l_flags; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ KASSERT(sc != NULL, ("hifn_freesession: null softc")); -+ if (sc == NULL) { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ return (EINVAL); -+ } -+ -+ HIFN_LOCK(sc); -+ session = HIFN_SESSION(sid); -+ if (session < sc->sc_nsessions) { -+ bzero(&sc->sc_sessions[session], sizeof(struct hifn_session)); -+ error = 0; -+ } else { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ error = EINVAL; -+ } -+ HIFN_UNLOCK(sc); -+ -+ return (error); -+} -+ -+static int -+hifn_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ struct hifn_softc *sc = device_get_softc(dev); -+ struct hifn_command *cmd = NULL; -+ int session, err, ivlen; -+ struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (crp == NULL || crp->crp_callback == NULL) { -+ hifnstats.hst_invalid++; -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ return (EINVAL); -+ } -+ session = HIFN_SESSION(crp->crp_sid); -+ -+ if (sc == NULL || session >= sc->sc_nsessions) { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ err = EINVAL; -+ goto errout; -+ } -+ -+ cmd = kmalloc(sizeof(struct hifn_command), SLAB_ATOMIC); -+ if (cmd == NULL) { -+ hifnstats.hst_nomem++; -+ err = ENOMEM; -+ goto errout; -+ } -+ memset(cmd, 0, sizeof(*cmd)); -+ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ cmd->src_skb = (struct sk_buff *)crp->crp_buf; -+ cmd->dst_skb = (struct sk_buff *)crp->crp_buf; -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ cmd->src_io = (struct uio *)crp->crp_buf; -+ cmd->dst_io = (struct uio *)crp->crp_buf; -+ } else { -+ cmd->src_buf = crp->crp_buf; -+ cmd->dst_buf = crp->crp_buf; -+ } -+ -+ crd1 = crp->crp_desc; -+ if (crd1 == NULL) { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ err = EINVAL; -+ goto errout; -+ } -+ crd2 = crd1->crd_next; -+ -+ if (crd2 == NULL) { -+ if (crd1->crd_alg == CRYPTO_MD5_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1 || -+ crd1->crd_alg == CRYPTO_MD5) { -+ maccrd = crd1; -+ enccrd = NULL; -+ } else if (crd1->crd_alg == CRYPTO_DES_CBC || -+ crd1->crd_alg == CRYPTO_3DES_CBC || -+ crd1->crd_alg == CRYPTO_AES_CBC || -+ crd1->crd_alg == CRYPTO_ARC4) { -+ if ((crd1->crd_flags & CRD_F_ENCRYPT) == 0) -+ cmd->base_masks |= HIFN_BASE_CMD_DECODE; -+ maccrd = NULL; -+ enccrd = crd1; -+ } else { -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ err = EINVAL; -+ goto errout; -+ } -+ } else { -+ if ((crd1->crd_alg == CRYPTO_MD5_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1_HMAC || -+ crd1->crd_alg == CRYPTO_MD5 || -+ crd1->crd_alg == CRYPTO_SHA1) && -+ (crd2->crd_alg == CRYPTO_DES_CBC || -+ crd2->crd_alg == CRYPTO_3DES_CBC || -+ crd2->crd_alg == CRYPTO_AES_CBC || -+ crd2->crd_alg == CRYPTO_ARC4) && -+ ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { -+ cmd->base_masks = HIFN_BASE_CMD_DECODE; -+ maccrd = crd1; -+ enccrd = crd2; -+ } else if ((crd1->crd_alg == CRYPTO_DES_CBC || -+ crd1->crd_alg == CRYPTO_ARC4 || -+ crd1->crd_alg == CRYPTO_3DES_CBC || -+ crd1->crd_alg == CRYPTO_AES_CBC) && -+ (crd2->crd_alg == CRYPTO_MD5_HMAC || -+ crd2->crd_alg == CRYPTO_SHA1_HMAC || -+ crd2->crd_alg == CRYPTO_MD5 || -+ crd2->crd_alg == CRYPTO_SHA1) && -+ (crd1->crd_flags & CRD_F_ENCRYPT)) { -+ enccrd = crd1; -+ maccrd = crd2; -+ } else { -+ /* -+ * We cannot order the 7751 as requested -+ */ -+ DPRINTF("%s,%d: %s %d,%d,%d - EINVAL\n",__FILE__,__LINE__,__FUNCTION__, crd1->crd_alg, crd2->crd_alg, crd1->crd_flags & CRD_F_ENCRYPT); -+ err = EINVAL; -+ goto errout; -+ } -+ } -+ -+ if (enccrd) { -+ cmd->enccrd = enccrd; -+ cmd->base_masks |= HIFN_BASE_CMD_CRYPT; -+ switch (enccrd->crd_alg) { -+ case CRYPTO_ARC4: -+ cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_RC4; -+ break; -+ case CRYPTO_DES_CBC: -+ cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_DES | -+ HIFN_CRYPT_CMD_MODE_CBC | -+ HIFN_CRYPT_CMD_NEW_IV; -+ break; -+ case CRYPTO_3DES_CBC: -+ cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_3DES | -+ HIFN_CRYPT_CMD_MODE_CBC | -+ HIFN_CRYPT_CMD_NEW_IV; -+ break; -+ case CRYPTO_AES_CBC: -+ cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_AES | -+ HIFN_CRYPT_CMD_MODE_CBC | -+ HIFN_CRYPT_CMD_NEW_IV; -+ break; -+ default: -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ err = EINVAL; -+ goto errout; -+ } -+ if (enccrd->crd_alg != CRYPTO_ARC4) { -+ ivlen = ((enccrd->crd_alg == CRYPTO_AES_CBC) ? -+ HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH); -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) { -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) -+ bcopy(enccrd->crd_iv, cmd->iv, ivlen); -+ else -+ read_random(cmd->iv, ivlen); -+ -+ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) -+ == 0) { -+ crypto_copyback(crp->crp_flags, -+ crp->crp_buf, enccrd->crd_inject, -+ ivlen, cmd->iv); -+ } -+ } else { -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) -+ bcopy(enccrd->crd_iv, cmd->iv, ivlen); -+ else { -+ crypto_copydata(crp->crp_flags, -+ crp->crp_buf, enccrd->crd_inject, -+ ivlen, cmd->iv); -+ } -+ } -+ } -+ -+ if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) -+ cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY; -+ cmd->ck = enccrd->crd_key; -+ cmd->cklen = enccrd->crd_klen >> 3; -+ cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY; -+ -+ /* -+ * Need to specify the size for the AES key in the masks. -+ */ -+ if ((cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) == -+ HIFN_CRYPT_CMD_ALG_AES) { -+ switch (cmd->cklen) { -+ case 16: -+ cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_128; -+ break; -+ case 24: -+ cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_192; -+ break; -+ case 32: -+ cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_256; -+ break; -+ default: -+ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); -+ err = EINVAL; -+ goto errout; -+ } -+ } -+ } -+ -+ if (maccrd) { -+ cmd->maccrd = maccrd; -+ cmd->base_masks |= HIFN_BASE_CMD_MAC; -+ -+ switch (maccrd->crd_alg) { -+ case CRYPTO_MD5: -+ cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | -+ HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | -+ HIFN_MAC_CMD_POS_IPSEC; -+ break; -+ case CRYPTO_MD5_HMAC: -+ cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | -+ HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | -+ HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; -+ break; -+ case CRYPTO_SHA1: -+ cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | -+ HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | -+ HIFN_MAC_CMD_POS_IPSEC; -+ break; -+ case CRYPTO_SHA1_HMAC: -+ cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | -+ HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | -+ HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; -+ break; -+ } -+ -+ if (maccrd->crd_alg == CRYPTO_SHA1_HMAC || -+ maccrd->crd_alg == CRYPTO_MD5_HMAC) { -+ cmd->mac_masks |= HIFN_MAC_CMD_NEW_KEY; -+ bcopy(maccrd->crd_key, cmd->mac, maccrd->crd_klen >> 3); -+ bzero(cmd->mac + (maccrd->crd_klen >> 3), -+ HIFN_MAC_KEY_LENGTH - (maccrd->crd_klen >> 3)); -+ } -+ } -+ -+ cmd->crp = crp; -+ cmd->session_num = session; -+ cmd->softc = sc; -+ -+ err = hifn_crypto(sc, cmd, crp, hint); -+ if (!err) { -+ return 0; -+ } else if (err == ERESTART) { -+ /* -+ * There weren't enough resources to dispatch the request -+ * to the part. Notify the caller so they'll requeue this -+ * request and resubmit it again soon. -+ */ -+#ifdef HIFN_DEBUG -+ if (hifn_debug) -+ device_printf(sc->sc_dev, "requeue request\n"); -+#endif -+ kfree(cmd); -+ sc->sc_needwakeup |= CRYPTO_SYMQ; -+ return (err); -+ } -+ -+errout: -+ if (cmd != NULL) -+ kfree(cmd); -+ if (err == EINVAL) -+ hifnstats.hst_invalid++; -+ else -+ hifnstats.hst_nomem++; -+ crp->crp_etype = err; -+ crypto_done(crp); -+ return (err); -+} -+ -+static void -+hifn_abort(struct hifn_softc *sc) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ struct hifn_command *cmd; -+ struct cryptop *crp; -+ int i, u; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ i = dma->resk; u = dma->resu; -+ while (u != 0) { -+ cmd = dma->hifn_commands[i]; -+ KASSERT(cmd != NULL, ("hifn_abort: null command slot %u", i)); -+ dma->hifn_commands[i] = NULL; -+ crp = cmd->crp; -+ -+ if ((dma->resr[i].l & htole32(HIFN_D_VALID)) == 0) { -+ /* Salvage what we can. */ -+ u_int8_t *macbuf; -+ -+ if (cmd->base_masks & HIFN_BASE_CMD_MAC) { -+ macbuf = dma->result_bufs[i]; -+ macbuf += 12; -+ } else -+ macbuf = NULL; -+ hifnstats.hst_opackets++; -+ hifn_callback(sc, cmd, macbuf); -+ } else { -+#if 0 -+ if (cmd->src_map == cmd->dst_map) { -+ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, -+ BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); -+ } else { -+ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, -+ BUS_DMASYNC_POSTWRITE); -+ bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, -+ BUS_DMASYNC_POSTREAD); -+ } -+#endif -+ -+ if (cmd->src_skb != cmd->dst_skb) { -+#ifdef NOTYET -+ m_freem(cmd->src_m); -+ crp->crp_buf = (caddr_t)cmd->dst_m; -+#else -+ device_printf(sc->sc_dev, -+ "%s,%d: CRYPTO_F_SKBUF src != dst not implemented\n", -+ __FILE__, __LINE__); -+#endif -+ } -+ -+ /* non-shared buffers cannot be restarted */ -+ if (cmd->src_map != cmd->dst_map) { -+ /* -+ * XXX should be EAGAIN, delayed until -+ * after the reset. -+ */ -+ crp->crp_etype = ENOMEM; -+ pci_unmap_buf(sc, &cmd->dst); -+ } else -+ crp->crp_etype = ENOMEM; -+ -+ pci_unmap_buf(sc, &cmd->src); -+ -+ kfree(cmd); -+ if (crp->crp_etype != EAGAIN) -+ crypto_done(crp); -+ } -+ -+ if (++i == HIFN_D_RES_RSIZE) -+ i = 0; -+ u--; -+ } -+ dma->resk = i; dma->resu = u; -+ -+ hifn_reset_board(sc, 1); -+ hifn_init_dma(sc); -+ hifn_init_pci_registers(sc); -+} -+ -+static void -+hifn_callback(struct hifn_softc *sc, struct hifn_command *cmd, u_int8_t *macbuf) -+{ -+ struct hifn_dma *dma = sc->sc_dma; -+ struct cryptop *crp = cmd->crp; -+ struct cryptodesc *crd; -+ int i, u; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+#if 0 -+ if (cmd->src_map == cmd->dst_map) { -+ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, -+ BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); -+ } else { -+ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, -+ BUS_DMASYNC_POSTWRITE); -+ bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, -+ BUS_DMASYNC_POSTREAD); -+ } -+#endif -+ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ if (cmd->src_skb != cmd->dst_skb) { -+#ifdef NOTYET -+ crp->crp_buf = (caddr_t)cmd->dst_m; -+ totlen = cmd->src_mapsize; -+ for (m = cmd->dst_m; m != NULL; m = m->m_next) { -+ if (totlen < m->m_len) { -+ m->m_len = totlen; -+ totlen = 0; -+ } else -+ totlen -= m->m_len; -+ } -+ cmd->dst_m->m_pkthdr.len = cmd->src_m->m_pkthdr.len; -+ m_freem(cmd->src_m); -+#else -+ device_printf(sc->sc_dev, -+ "%s,%d: CRYPTO_F_SKBUF src != dst not implemented\n", -+ __FILE__, __LINE__); -+#endif -+ } -+ } -+ -+ if (cmd->sloplen != 0) { -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ cmd->src_mapsize - cmd->sloplen, cmd->sloplen, -+ (caddr_t)&dma->slop[cmd->slopidx]); -+ } -+ -+ i = dma->dstk; u = dma->dstu; -+ while (u != 0) { -+ if (i == HIFN_D_DST_RSIZE) -+ i = 0; -+#if 0 -+ bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, -+ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); -+#endif -+ if (dma->dstr[i].l & htole32(HIFN_D_VALID)) { -+#if 0 -+ bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+#endif -+ break; -+ } -+ i++, u--; -+ } -+ dma->dstk = i; dma->dstu = u; -+ -+ hifnstats.hst_obytes += cmd->dst_mapsize; -+ -+ if (macbuf != NULL) { -+ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { -+ int len; -+ -+ if (crd->crd_alg != CRYPTO_MD5 && -+ crd->crd_alg != CRYPTO_SHA1 && -+ crd->crd_alg != CRYPTO_MD5_HMAC && -+ crd->crd_alg != CRYPTO_SHA1_HMAC) { -+ continue; -+ } -+ len = cmd->softc->sc_sessions[cmd->session_num].hs_mlen; -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, len, macbuf); -+ break; -+ } -+ } -+ -+ if (cmd->src_map != cmd->dst_map) -+ pci_unmap_buf(sc, &cmd->dst); -+ pci_unmap_buf(sc, &cmd->src); -+ kfree(cmd); -+ crypto_done(crp); -+} -+ -+/* -+ * 7811 PB3 rev/2 parts lock-up on burst writes to Group 0 -+ * and Group 1 registers; avoid conditions that could create -+ * burst writes by doing a read in between the writes. -+ * -+ * NB: The read we interpose is always to the same register; -+ * we do this because reading from an arbitrary (e.g. last) -+ * register may not always work. -+ */ -+static void -+hifn_write_reg_0(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) -+{ -+ if (sc->sc_flags & HIFN_IS_7811) { -+ if (sc->sc_bar0_lastreg == reg - 4) -+ readl(sc->sc_bar0 + HIFN_0_PUCNFG); -+ sc->sc_bar0_lastreg = reg; -+ } -+ writel(val, sc->sc_bar0 + reg); -+} -+ -+static void -+hifn_write_reg_1(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) -+{ -+ if (sc->sc_flags & HIFN_IS_7811) { -+ if (sc->sc_bar1_lastreg == reg - 4) -+ readl(sc->sc_bar1 + HIFN_1_REVID); -+ sc->sc_bar1_lastreg = reg; -+ } -+ writel(val, sc->sc_bar1 + reg); -+} -+ -+ -+static struct pci_device_id hifn_pci_tbl[] = { -+ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7951, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7955, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7956, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ { PCI_VENDOR_NETSEC, PCI_PRODUCT_NETSEC_7751, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ { PCI_VENDOR_INVERTEX, PCI_PRODUCT_INVERTEX_AEON, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7811, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ /* -+ * Other vendors share this PCI ID as well, such as -+ * http://www.powercrypt.com, and obviously they also -+ * use the same key. -+ */ -+ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7751, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ { 0, 0, 0, 0, 0, 0, } -+}; -+MODULE_DEVICE_TABLE(pci, hifn_pci_tbl); -+ -+static struct pci_driver hifn_driver = { -+ .name = "hifn", -+ .id_table = hifn_pci_tbl, -+ .probe = hifn_probe, -+ .remove = hifn_remove, -+ /* add PM stuff here one day */ -+}; -+ -+static int __init hifn_init (void) -+{ -+ struct hifn_softc *sc = NULL; -+ int rc; -+ -+ DPRINTF("%s(%p)\n", __FUNCTION__, hifn_init); -+ -+ rc = pci_register_driver(&hifn_driver); -+ pci_register_driver_compat(&hifn_driver, rc); -+ -+ return rc; -+} -+ -+static void __exit hifn_exit (void) -+{ -+ pci_unregister_driver(&hifn_driver); -+} -+ -+module_init(hifn_init); -+module_exit(hifn_exit); -+ -+MODULE_LICENSE("BSD"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("OCF driver for hifn PCI crypto devices"); -diff -Nur linux-3.0.4.orig/crypto/ocf/hifn/hifn7751reg.h linux-3.0.4/crypto/ocf/hifn/hifn7751reg.h ---- linux-3.0.4.orig/crypto/ocf/hifn/hifn7751reg.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/hifn/hifn7751reg.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,540 @@ -+/* $FreeBSD: src/sys/dev/hifn/hifn7751reg.h,v 1.7 2007/03/21 03:42:49 sam Exp $ */ -+/* $OpenBSD: hifn7751reg.h,v 1.35 2002/04/08 17:49:42 jason Exp $ */ -+ -+/*- -+ * Invertex AEON / Hifn 7751 driver -+ * Copyright (c) 1999 Invertex Inc. All rights reserved. -+ * Copyright (c) 1999 Theo de Raadt -+ * Copyright (c) 2000-2001 Network Security Technologies, Inc. -+ * http://www.netsec.net -+ * -+ * Please send any comments, feedback, bug-fixes, or feature requests to -+ * software@invertex.com. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored in part by the Defense Advanced Research Projects -+ * Agency (DARPA) and Air Force Research Laboratory, Air Force -+ * Materiel Command, USAF, under agreement number F30602-01-2-0537. -+ * -+ */ -+#ifndef __HIFN_H__ -+#define __HIFN_H__ -+ -+/* -+ * Some PCI configuration space offset defines. The names were made -+ * identical to the names used by the Linux kernel. -+ */ -+#define HIFN_BAR0 PCIR_BAR(0) /* PUC register map */ -+#define HIFN_BAR1 PCIR_BAR(1) /* DMA register map */ -+#define HIFN_TRDY_TIMEOUT 0x40 -+#define HIFN_RETRY_TIMEOUT 0x41 -+ -+/* -+ * PCI vendor and device identifiers -+ * (the names are preserved from their OpenBSD source). -+ */ -+#define PCI_VENDOR_HIFN 0x13a3 /* Hifn */ -+#define PCI_PRODUCT_HIFN_7751 0x0005 /* 7751 */ -+#define PCI_PRODUCT_HIFN_6500 0x0006 /* 6500 */ -+#define PCI_PRODUCT_HIFN_7811 0x0007 /* 7811 */ -+#define PCI_PRODUCT_HIFN_7855 0x001f /* 7855 */ -+#define PCI_PRODUCT_HIFN_7951 0x0012 /* 7951 */ -+#define PCI_PRODUCT_HIFN_7955 0x0020 /* 7954/7955 */ -+#define PCI_PRODUCT_HIFN_7956 0x001d /* 7956 */ -+ -+#define PCI_VENDOR_INVERTEX 0x14e1 /* Invertex */ -+#define PCI_PRODUCT_INVERTEX_AEON 0x0005 /* AEON */ -+ -+#define PCI_VENDOR_NETSEC 0x1660 /* NetSec */ -+#define PCI_PRODUCT_NETSEC_7751 0x7751 /* 7751 */ -+ -+/* -+ * The values below should multiple of 4 -- and be large enough to handle -+ * any command the driver implements. -+ * -+ * MAX_COMMAND = base command + mac command + encrypt command + -+ * mac-key + rc4-key -+ * MAX_RESULT = base result + mac result + mac + encrypt result -+ * -+ * -+ */ -+#define HIFN_MAX_COMMAND (8 + 8 + 8 + 64 + 260) -+#define HIFN_MAX_RESULT (8 + 4 + 20 + 4) -+ -+/* -+ * hifn_desc_t -+ * -+ * Holds an individual descriptor for any of the rings. -+ */ -+typedef struct hifn_desc { -+ volatile u_int32_t l; /* length and status bits */ -+ volatile u_int32_t p; -+} hifn_desc_t; -+ -+/* -+ * Masks for the "length" field of struct hifn_desc. -+ */ -+#define HIFN_D_LENGTH 0x0000ffff /* length bit mask */ -+#define HIFN_D_MASKDONEIRQ 0x02000000 /* mask the done interrupt */ -+#define HIFN_D_DESTOVER 0x04000000 /* destination overflow */ -+#define HIFN_D_OVER 0x08000000 /* overflow */ -+#define HIFN_D_LAST 0x20000000 /* last descriptor in chain */ -+#define HIFN_D_JUMP 0x40000000 /* jump descriptor */ -+#define HIFN_D_VALID 0x80000000 /* valid bit */ -+ -+ -+/* -+ * Processing Unit Registers (offset from BASEREG0) -+ */ -+#define HIFN_0_PUDATA 0x00 /* Processing Unit Data */ -+#define HIFN_0_PUCTRL 0x04 /* Processing Unit Control */ -+#define HIFN_0_PUISR 0x08 /* Processing Unit Interrupt Status */ -+#define HIFN_0_PUCNFG 0x0c /* Processing Unit Configuration */ -+#define HIFN_0_PUIER 0x10 /* Processing Unit Interrupt Enable */ -+#define HIFN_0_PUSTAT 0x14 /* Processing Unit Status/Chip ID */ -+#define HIFN_0_FIFOSTAT 0x18 /* FIFO Status */ -+#define HIFN_0_FIFOCNFG 0x1c /* FIFO Configuration */ -+#define HIFN_0_PUCTRL2 0x28 /* Processing Unit Control (2nd map) */ -+#define HIFN_0_MUTE1 0x80 -+#define HIFN_0_MUTE2 0x90 -+#define HIFN_0_SPACESIZE 0x100 /* Register space size */ -+ -+/* Processing Unit Control Register (HIFN_0_PUCTRL) */ -+#define HIFN_PUCTRL_CLRSRCFIFO 0x0010 /* clear source fifo */ -+#define HIFN_PUCTRL_STOP 0x0008 /* stop pu */ -+#define HIFN_PUCTRL_LOCKRAM 0x0004 /* lock ram */ -+#define HIFN_PUCTRL_DMAENA 0x0002 /* enable dma */ -+#define HIFN_PUCTRL_RESET 0x0001 /* Reset processing unit */ -+ -+/* Processing Unit Interrupt Status Register (HIFN_0_PUISR) */ -+#define HIFN_PUISR_CMDINVAL 0x8000 /* Invalid command interrupt */ -+#define HIFN_PUISR_DATAERR 0x4000 /* Data error interrupt */ -+#define HIFN_PUISR_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ -+#define HIFN_PUISR_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ -+#define HIFN_PUISR_DSTOVER 0x0200 /* Destination overrun interrupt */ -+#define HIFN_PUISR_SRCCMD 0x0080 /* Source command interrupt */ -+#define HIFN_PUISR_SRCCTX 0x0040 /* Source context interrupt */ -+#define HIFN_PUISR_SRCDATA 0x0020 /* Source data interrupt */ -+#define HIFN_PUISR_DSTDATA 0x0010 /* Destination data interrupt */ -+#define HIFN_PUISR_DSTRESULT 0x0004 /* Destination result interrupt */ -+ -+/* Processing Unit Configuration Register (HIFN_0_PUCNFG) */ -+#define HIFN_PUCNFG_DRAMMASK 0xe000 /* DRAM size mask */ -+#define HIFN_PUCNFG_DSZ_256K 0x0000 /* 256k dram */ -+#define HIFN_PUCNFG_DSZ_512K 0x2000 /* 512k dram */ -+#define HIFN_PUCNFG_DSZ_1M 0x4000 /* 1m dram */ -+#define HIFN_PUCNFG_DSZ_2M 0x6000 /* 2m dram */ -+#define HIFN_PUCNFG_DSZ_4M 0x8000 /* 4m dram */ -+#define HIFN_PUCNFG_DSZ_8M 0xa000 /* 8m dram */ -+#define HIFN_PUNCFG_DSZ_16M 0xc000 /* 16m dram */ -+#define HIFN_PUCNFG_DSZ_32M 0xe000 /* 32m dram */ -+#define HIFN_PUCNFG_DRAMREFRESH 0x1800 /* DRAM refresh rate mask */ -+#define HIFN_PUCNFG_DRFR_512 0x0000 /* 512 divisor of ECLK */ -+#define HIFN_PUCNFG_DRFR_256 0x0800 /* 256 divisor of ECLK */ -+#define HIFN_PUCNFG_DRFR_128 0x1000 /* 128 divisor of ECLK */ -+#define HIFN_PUCNFG_TCALLPHASES 0x0200 /* your guess is as good as mine... */ -+#define HIFN_PUCNFG_TCDRVTOTEM 0x0100 /* your guess is as good as mine... */ -+#define HIFN_PUCNFG_BIGENDIAN 0x0080 /* DMA big endian mode */ -+#define HIFN_PUCNFG_BUS32 0x0040 /* Bus width 32bits */ -+#define HIFN_PUCNFG_BUS16 0x0000 /* Bus width 16 bits */ -+#define HIFN_PUCNFG_CHIPID 0x0020 /* Allow chipid from PUSTAT */ -+#define HIFN_PUCNFG_DRAM 0x0010 /* Context RAM is DRAM */ -+#define HIFN_PUCNFG_SRAM 0x0000 /* Context RAM is SRAM */ -+#define HIFN_PUCNFG_COMPSING 0x0004 /* Enable single compression context */ -+#define HIFN_PUCNFG_ENCCNFG 0x0002 /* Encryption configuration */ -+ -+/* Processing Unit Interrupt Enable Register (HIFN_0_PUIER) */ -+#define HIFN_PUIER_CMDINVAL 0x8000 /* Invalid command interrupt */ -+#define HIFN_PUIER_DATAERR 0x4000 /* Data error interrupt */ -+#define HIFN_PUIER_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ -+#define HIFN_PUIER_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ -+#define HIFN_PUIER_DSTOVER 0x0200 /* Destination overrun interrupt */ -+#define HIFN_PUIER_SRCCMD 0x0080 /* Source command interrupt */ -+#define HIFN_PUIER_SRCCTX 0x0040 /* Source context interrupt */ -+#define HIFN_PUIER_SRCDATA 0x0020 /* Source data interrupt */ -+#define HIFN_PUIER_DSTDATA 0x0010 /* Destination data interrupt */ -+#define HIFN_PUIER_DSTRESULT 0x0004 /* Destination result interrupt */ -+ -+/* Processing Unit Status Register/Chip ID (HIFN_0_PUSTAT) */ -+#define HIFN_PUSTAT_CMDINVAL 0x8000 /* Invalid command interrupt */ -+#define HIFN_PUSTAT_DATAERR 0x4000 /* Data error interrupt */ -+#define HIFN_PUSTAT_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ -+#define HIFN_PUSTAT_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ -+#define HIFN_PUSTAT_DSTOVER 0x0200 /* Destination overrun interrupt */ -+#define HIFN_PUSTAT_SRCCMD 0x0080 /* Source command interrupt */ -+#define HIFN_PUSTAT_SRCCTX 0x0040 /* Source context interrupt */ -+#define HIFN_PUSTAT_SRCDATA 0x0020 /* Source data interrupt */ -+#define HIFN_PUSTAT_DSTDATA 0x0010 /* Destination data interrupt */ -+#define HIFN_PUSTAT_DSTRESULT 0x0004 /* Destination result interrupt */ -+#define HIFN_PUSTAT_CHIPREV 0x00ff /* Chip revision mask */ -+#define HIFN_PUSTAT_CHIPENA 0xff00 /* Chip enabled mask */ -+#define HIFN_PUSTAT_ENA_2 0x1100 /* Level 2 enabled */ -+#define HIFN_PUSTAT_ENA_1 0x1000 /* Level 1 enabled */ -+#define HIFN_PUSTAT_ENA_0 0x3000 /* Level 0 enabled */ -+#define HIFN_PUSTAT_REV_2 0x0020 /* 7751 PT6/2 */ -+#define HIFN_PUSTAT_REV_3 0x0030 /* 7751 PT6/3 */ -+ -+/* FIFO Status Register (HIFN_0_FIFOSTAT) */ -+#define HIFN_FIFOSTAT_SRC 0x7f00 /* Source FIFO available */ -+#define HIFN_FIFOSTAT_DST 0x007f /* Destination FIFO available */ -+ -+/* FIFO Configuration Register (HIFN_0_FIFOCNFG) */ -+#define HIFN_FIFOCNFG_THRESHOLD 0x0400 /* must be written as this value */ -+ -+/* -+ * DMA Interface Registers (offset from BASEREG1) -+ */ -+#define HIFN_1_DMA_CRAR 0x0c /* DMA Command Ring Address */ -+#define HIFN_1_DMA_SRAR 0x1c /* DMA Source Ring Address */ -+#define HIFN_1_DMA_RRAR 0x2c /* DMA Result Ring Address */ -+#define HIFN_1_DMA_DRAR 0x3c /* DMA Destination Ring Address */ -+#define HIFN_1_DMA_CSR 0x40 /* DMA Status and Control */ -+#define HIFN_1_DMA_IER 0x44 /* DMA Interrupt Enable */ -+#define HIFN_1_DMA_CNFG 0x48 /* DMA Configuration */ -+#define HIFN_1_PLL 0x4c /* 7955/7956: PLL config */ -+#define HIFN_1_7811_RNGENA 0x60 /* 7811: rng enable */ -+#define HIFN_1_7811_RNGCFG 0x64 /* 7811: rng config */ -+#define HIFN_1_7811_RNGDAT 0x68 /* 7811: rng data */ -+#define HIFN_1_7811_RNGSTS 0x6c /* 7811: rng status */ -+#define HIFN_1_DMA_CNFG2 0x6c /* 7955/7956: dma config #2 */ -+#define HIFN_1_7811_MIPSRST 0x94 /* 7811: MIPS reset */ -+#define HIFN_1_REVID 0x98 /* Revision ID */ -+ -+#define HIFN_1_PUB_RESET 0x204 /* Public/RNG Reset */ -+#define HIFN_1_PUB_BASE 0x300 /* Public Base Address */ -+#define HIFN_1_PUB_OPLEN 0x304 /* 7951-compat Public Operand Length */ -+#define HIFN_1_PUB_OP 0x308 /* 7951-compat Public Operand */ -+#define HIFN_1_PUB_STATUS 0x30c /* 7951-compat Public Status */ -+#define HIFN_1_PUB_IEN 0x310 /* Public Interrupt enable */ -+#define HIFN_1_RNG_CONFIG 0x314 /* RNG config */ -+#define HIFN_1_RNG_DATA 0x318 /* RNG data */ -+#define HIFN_1_PUB_MODE 0x320 /* PK mode */ -+#define HIFN_1_PUB_FIFO_OPLEN 0x380 /* first element of oplen fifo */ -+#define HIFN_1_PUB_FIFO_OP 0x384 /* first element of op fifo */ -+#define HIFN_1_PUB_MEM 0x400 /* start of Public key memory */ -+#define HIFN_1_PUB_MEMEND 0xbff /* end of Public key memory */ -+ -+/* DMA Status and Control Register (HIFN_1_DMA_CSR) */ -+#define HIFN_DMACSR_D_CTRLMASK 0xc0000000 /* Destinition Ring Control */ -+#define HIFN_DMACSR_D_CTRL_NOP 0x00000000 /* Dest. Control: no-op */ -+#define HIFN_DMACSR_D_CTRL_DIS 0x40000000 /* Dest. Control: disable */ -+#define HIFN_DMACSR_D_CTRL_ENA 0x80000000 /* Dest. Control: enable */ -+#define HIFN_DMACSR_D_ABORT 0x20000000 /* Destinition Ring PCIAbort */ -+#define HIFN_DMACSR_D_DONE 0x10000000 /* Destinition Ring Done */ -+#define HIFN_DMACSR_D_LAST 0x08000000 /* Destinition Ring Last */ -+#define HIFN_DMACSR_D_WAIT 0x04000000 /* Destinition Ring Waiting */ -+#define HIFN_DMACSR_D_OVER 0x02000000 /* Destinition Ring Overflow */ -+#define HIFN_DMACSR_R_CTRL 0x00c00000 /* Result Ring Control */ -+#define HIFN_DMACSR_R_CTRL_NOP 0x00000000 /* Result Control: no-op */ -+#define HIFN_DMACSR_R_CTRL_DIS 0x00400000 /* Result Control: disable */ -+#define HIFN_DMACSR_R_CTRL_ENA 0x00800000 /* Result Control: enable */ -+#define HIFN_DMACSR_R_ABORT 0x00200000 /* Result Ring PCI Abort */ -+#define HIFN_DMACSR_R_DONE 0x00100000 /* Result Ring Done */ -+#define HIFN_DMACSR_R_LAST 0x00080000 /* Result Ring Last */ -+#define HIFN_DMACSR_R_WAIT 0x00040000 /* Result Ring Waiting */ -+#define HIFN_DMACSR_R_OVER 0x00020000 /* Result Ring Overflow */ -+#define HIFN_DMACSR_S_CTRL 0x0000c000 /* Source Ring Control */ -+#define HIFN_DMACSR_S_CTRL_NOP 0x00000000 /* Source Control: no-op */ -+#define HIFN_DMACSR_S_CTRL_DIS 0x00004000 /* Source Control: disable */ -+#define HIFN_DMACSR_S_CTRL_ENA 0x00008000 /* Source Control: enable */ -+#define HIFN_DMACSR_S_ABORT 0x00002000 /* Source Ring PCI Abort */ -+#define HIFN_DMACSR_S_DONE 0x00001000 /* Source Ring Done */ -+#define HIFN_DMACSR_S_LAST 0x00000800 /* Source Ring Last */ -+#define HIFN_DMACSR_S_WAIT 0x00000400 /* Source Ring Waiting */ -+#define HIFN_DMACSR_ILLW 0x00000200 /* Illegal write (7811 only) */ -+#define HIFN_DMACSR_ILLR 0x00000100 /* Illegal read (7811 only) */ -+#define HIFN_DMACSR_C_CTRL 0x000000c0 /* Command Ring Control */ -+#define HIFN_DMACSR_C_CTRL_NOP 0x00000000 /* Command Control: no-op */ -+#define HIFN_DMACSR_C_CTRL_DIS 0x00000040 /* Command Control: disable */ -+#define HIFN_DMACSR_C_CTRL_ENA 0x00000080 /* Command Control: enable */ -+#define HIFN_DMACSR_C_ABORT 0x00000020 /* Command Ring PCI Abort */ -+#define HIFN_DMACSR_C_DONE 0x00000010 /* Command Ring Done */ -+#define HIFN_DMACSR_C_LAST 0x00000008 /* Command Ring Last */ -+#define HIFN_DMACSR_C_WAIT 0x00000004 /* Command Ring Waiting */ -+#define HIFN_DMACSR_PUBDONE 0x00000002 /* Public op done (7951 only) */ -+#define HIFN_DMACSR_ENGINE 0x00000001 /* Command Ring Engine IRQ */ -+ -+/* DMA Interrupt Enable Register (HIFN_1_DMA_IER) */ -+#define HIFN_DMAIER_D_ABORT 0x20000000 /* Destination Ring PCIAbort */ -+#define HIFN_DMAIER_D_DONE 0x10000000 /* Destination Ring Done */ -+#define HIFN_DMAIER_D_LAST 0x08000000 /* Destination Ring Last */ -+#define HIFN_DMAIER_D_WAIT 0x04000000 /* Destination Ring Waiting */ -+#define HIFN_DMAIER_D_OVER 0x02000000 /* Destination Ring Overflow */ -+#define HIFN_DMAIER_R_ABORT 0x00200000 /* Result Ring PCI Abort */ -+#define HIFN_DMAIER_R_DONE 0x00100000 /* Result Ring Done */ -+#define HIFN_DMAIER_R_LAST 0x00080000 /* Result Ring Last */ -+#define HIFN_DMAIER_R_WAIT 0x00040000 /* Result Ring Waiting */ -+#define HIFN_DMAIER_R_OVER 0x00020000 /* Result Ring Overflow */ -+#define HIFN_DMAIER_S_ABORT 0x00002000 /* Source Ring PCI Abort */ -+#define HIFN_DMAIER_S_DONE 0x00001000 /* Source Ring Done */ -+#define HIFN_DMAIER_S_LAST 0x00000800 /* Source Ring Last */ -+#define HIFN_DMAIER_S_WAIT 0x00000400 /* Source Ring Waiting */ -+#define HIFN_DMAIER_ILLW 0x00000200 /* Illegal write (7811 only) */ -+#define HIFN_DMAIER_ILLR 0x00000100 /* Illegal read (7811 only) */ -+#define HIFN_DMAIER_C_ABORT 0x00000020 /* Command Ring PCI Abort */ -+#define HIFN_DMAIER_C_DONE 0x00000010 /* Command Ring Done */ -+#define HIFN_DMAIER_C_LAST 0x00000008 /* Command Ring Last */ -+#define HIFN_DMAIER_C_WAIT 0x00000004 /* Command Ring Waiting */ -+#define HIFN_DMAIER_PUBDONE 0x00000002 /* public op done (7951 only) */ -+#define HIFN_DMAIER_ENGINE 0x00000001 /* Engine IRQ */ -+ -+/* DMA Configuration Register (HIFN_1_DMA_CNFG) */ -+#define HIFN_DMACNFG_BIGENDIAN 0x10000000 /* big endian mode */ -+#define HIFN_DMACNFG_POLLFREQ 0x00ff0000 /* Poll frequency mask */ -+#define HIFN_DMACNFG_UNLOCK 0x00000800 -+#define HIFN_DMACNFG_POLLINVAL 0x00000700 /* Invalid Poll Scalar */ -+#define HIFN_DMACNFG_LAST 0x00000010 /* Host control LAST bit */ -+#define HIFN_DMACNFG_MODE 0x00000004 /* DMA mode */ -+#define HIFN_DMACNFG_DMARESET 0x00000002 /* DMA Reset # */ -+#define HIFN_DMACNFG_MSTRESET 0x00000001 /* Master Reset # */ -+ -+/* DMA Configuration Register (HIFN_1_DMA_CNFG2) */ -+#define HIFN_DMACNFG2_PKSWAP32 (1 << 19) /* swap the OPLEN/OP reg */ -+#define HIFN_DMACNFG2_PKSWAP8 (1 << 18) /* swap the bits of OPLEN/OP */ -+#define HIFN_DMACNFG2_BAR0_SWAP32 (1<<17) /* swap the bytes of BAR0 */ -+#define HIFN_DMACNFG2_BAR1_SWAP8 (1<<16) /* swap the bits of BAR0 */ -+#define HIFN_DMACNFG2_INIT_WRITE_BURST_SHIFT 12 -+#define HIFN_DMACNFG2_INIT_READ_BURST_SHIFT 8 -+#define HIFN_DMACNFG2_TGT_WRITE_BURST_SHIFT 4 -+#define HIFN_DMACNFG2_TGT_READ_BURST_SHIFT 0 -+ -+/* 7811 RNG Enable Register (HIFN_1_7811_RNGENA) */ -+#define HIFN_7811_RNGENA_ENA 0x00000001 /* enable RNG */ -+ -+/* 7811 RNG Config Register (HIFN_1_7811_RNGCFG) */ -+#define HIFN_7811_RNGCFG_PRE1 0x00000f00 /* first prescalar */ -+#define HIFN_7811_RNGCFG_OPRE 0x00000080 /* output prescalar */ -+#define HIFN_7811_RNGCFG_DEFL 0x00000f80 /* 2 words/ 1/100 sec */ -+ -+/* 7811 RNG Status Register (HIFN_1_7811_RNGSTS) */ -+#define HIFN_7811_RNGSTS_RDY 0x00004000 /* two numbers in FIFO */ -+#define HIFN_7811_RNGSTS_UFL 0x00001000 /* rng underflow */ -+ -+/* 7811 MIPS Reset Register (HIFN_1_7811_MIPSRST) */ -+#define HIFN_MIPSRST_BAR2SIZE 0xffff0000 /* sdram size */ -+#define HIFN_MIPSRST_GPRAMINIT 0x00008000 /* gpram can be accessed */ -+#define HIFN_MIPSRST_CRAMINIT 0x00004000 /* ctxram can be accessed */ -+#define HIFN_MIPSRST_LED2 0x00000400 /* external LED2 */ -+#define HIFN_MIPSRST_LED1 0x00000200 /* external LED1 */ -+#define HIFN_MIPSRST_LED0 0x00000100 /* external LED0 */ -+#define HIFN_MIPSRST_MIPSDIS 0x00000004 /* disable MIPS */ -+#define HIFN_MIPSRST_MIPSRST 0x00000002 /* warm reset MIPS */ -+#define HIFN_MIPSRST_MIPSCOLD 0x00000001 /* cold reset MIPS */ -+ -+/* Public key reset register (HIFN_1_PUB_RESET) */ -+#define HIFN_PUBRST_RESET 0x00000001 /* reset public/rng unit */ -+ -+/* Public operation register (HIFN_1_PUB_OP) */ -+#define HIFN_PUBOP_AOFFSET 0x0000003e /* A offset */ -+#define HIFN_PUBOP_BOFFSET 0x00000fc0 /* B offset */ -+#define HIFN_PUBOP_MOFFSET 0x0003f000 /* M offset */ -+#define HIFN_PUBOP_OP_MASK 0x003c0000 /* Opcode: */ -+#define HIFN_PUBOP_OP_NOP 0x00000000 /* NOP */ -+#define HIFN_PUBOP_OP_ADD 0x00040000 /* ADD */ -+#define HIFN_PUBOP_OP_ADDC 0x00080000 /* ADD w/carry */ -+#define HIFN_PUBOP_OP_SUB 0x000c0000 /* SUB */ -+#define HIFN_PUBOP_OP_SUBC 0x00100000 /* SUB w/carry */ -+#define HIFN_PUBOP_OP_MODADD 0x00140000 /* Modular ADD */ -+#define HIFN_PUBOP_OP_MODSUB 0x00180000 /* Modular SUB */ -+#define HIFN_PUBOP_OP_INCA 0x001c0000 /* INC A */ -+#define HIFN_PUBOP_OP_DECA 0x00200000 /* DEC A */ -+#define HIFN_PUBOP_OP_MULT 0x00240000 /* MULT */ -+#define HIFN_PUBOP_OP_MODMULT 0x00280000 /* Modular MULT */ -+#define HIFN_PUBOP_OP_MODRED 0x002c0000 /* Modular Red */ -+#define HIFN_PUBOP_OP_MODEXP 0x00300000 /* Modular Exp */ -+ -+/* Public operand length register (HIFN_1_PUB_OPLEN) */ -+#define HIFN_PUBOPLEN_MODLEN 0x0000007f -+#define HIFN_PUBOPLEN_EXPLEN 0x0003ff80 -+#define HIFN_PUBOPLEN_REDLEN 0x003c0000 -+ -+/* Public status register (HIFN_1_PUB_STATUS) */ -+#define HIFN_PUBSTS_DONE 0x00000001 /* operation done */ -+#define HIFN_PUBSTS_CARRY 0x00000002 /* carry */ -+#define HIFN_PUBSTS_FIFO_EMPTY 0x00000100 /* fifo empty */ -+#define HIFN_PUBSTS_FIFO_FULL 0x00000200 /* fifo full */ -+#define HIFN_PUBSTS_FIFO_OVFL 0x00000400 /* fifo overflow */ -+#define HIFN_PUBSTS_FIFO_WRITE 0x000f0000 /* fifo write */ -+#define HIFN_PUBSTS_FIFO_READ 0x0f000000 /* fifo read */ -+ -+/* Public interrupt enable register (HIFN_1_PUB_IEN) */ -+#define HIFN_PUBIEN_DONE 0x00000001 /* operation done interrupt */ -+ -+/* Random number generator config register (HIFN_1_RNG_CONFIG) */ -+#define HIFN_RNGCFG_ENA 0x00000001 /* enable rng */ -+ -+/* -+ * Register offsets in register set 1 -+ */ -+ -+#define HIFN_UNLOCK_SECRET1 0xf4 -+#define HIFN_UNLOCK_SECRET2 0xfc -+ -+/* -+ * PLL config register -+ * -+ * This register is present only on 7954/7955/7956 parts. It must be -+ * programmed according to the bus interface method used by the h/w. -+ * Note that the parts require a stable clock. Since the PCI clock -+ * may vary the reference clock must usually be used. To avoid -+ * overclocking the core logic, setup must be done carefully, refer -+ * to the driver for details. The exact multiplier required varies -+ * by part and system configuration; refer to the Hifn documentation. -+ */ -+#define HIFN_PLL_REF_SEL 0x00000001 /* REF/HBI clk selection */ -+#define HIFN_PLL_BP 0x00000002 /* bypass (used during setup) */ -+/* bit 2 reserved */ -+#define HIFN_PLL_PK_CLK_SEL 0x00000008 /* public key clk select */ -+#define HIFN_PLL_PE_CLK_SEL 0x00000010 /* packet engine clk select */ -+/* bits 5-9 reserved */ -+#define HIFN_PLL_MBSET 0x00000400 /* must be set to 1 */ -+#define HIFN_PLL_ND 0x00003800 /* Fpll_ref multiplier select */ -+#define HIFN_PLL_ND_SHIFT 11 -+#define HIFN_PLL_ND_2 0x00000000 /* 2x */ -+#define HIFN_PLL_ND_4 0x00000800 /* 4x */ -+#define HIFN_PLL_ND_6 0x00001000 /* 6x */ -+#define HIFN_PLL_ND_8 0x00001800 /* 8x */ -+#define HIFN_PLL_ND_10 0x00002000 /* 10x */ -+#define HIFN_PLL_ND_12 0x00002800 /* 12x */ -+/* bits 14-15 reserved */ -+#define HIFN_PLL_IS 0x00010000 /* charge pump current select */ -+/* bits 17-31 reserved */ -+ -+/* -+ * Board configuration specifies only these bits. -+ */ -+#define HIFN_PLL_CONFIG (HIFN_PLL_IS|HIFN_PLL_ND|HIFN_PLL_REF_SEL) -+ -+/* -+ * Public Key Engine Mode Register -+ */ -+#define HIFN_PKMODE_HOSTINVERT (1 << 0) /* HOST INVERT */ -+#define HIFN_PKMODE_ENHANCED (1 << 1) /* Enable enhanced mode */ -+ -+ -+/********************************************************************* -+ * Structs for board commands -+ * -+ *********************************************************************/ -+ -+/* -+ * Structure to help build up the command data structure. -+ */ -+typedef struct hifn_base_command { -+ volatile u_int16_t masks; -+ volatile u_int16_t session_num; -+ volatile u_int16_t total_source_count; -+ volatile u_int16_t total_dest_count; -+} hifn_base_command_t; -+ -+#define HIFN_BASE_CMD_MAC 0x0400 -+#define HIFN_BASE_CMD_CRYPT 0x0800 -+#define HIFN_BASE_CMD_DECODE 0x2000 -+#define HIFN_BASE_CMD_SRCLEN_M 0xc000 -+#define HIFN_BASE_CMD_SRCLEN_S 14 -+#define HIFN_BASE_CMD_DSTLEN_M 0x3000 -+#define HIFN_BASE_CMD_DSTLEN_S 12 -+#define HIFN_BASE_CMD_LENMASK_HI 0x30000 -+#define HIFN_BASE_CMD_LENMASK_LO 0x0ffff -+ -+/* -+ * Structure to help build up the command data structure. -+ */ -+typedef struct hifn_crypt_command { -+ volatile u_int16_t masks; -+ volatile u_int16_t header_skip; -+ volatile u_int16_t source_count; -+ volatile u_int16_t reserved; -+} hifn_crypt_command_t; -+ -+#define HIFN_CRYPT_CMD_ALG_MASK 0x0003 /* algorithm: */ -+#define HIFN_CRYPT_CMD_ALG_DES 0x0000 /* DES */ -+#define HIFN_CRYPT_CMD_ALG_3DES 0x0001 /* 3DES */ -+#define HIFN_CRYPT_CMD_ALG_RC4 0x0002 /* RC4 */ -+#define HIFN_CRYPT_CMD_ALG_AES 0x0003 /* AES */ -+#define HIFN_CRYPT_CMD_MODE_MASK 0x0018 /* Encrypt mode: */ -+#define HIFN_CRYPT_CMD_MODE_ECB 0x0000 /* ECB */ -+#define HIFN_CRYPT_CMD_MODE_CBC 0x0008 /* CBC */ -+#define HIFN_CRYPT_CMD_MODE_CFB 0x0010 /* CFB */ -+#define HIFN_CRYPT_CMD_MODE_OFB 0x0018 /* OFB */ -+#define HIFN_CRYPT_CMD_CLR_CTX 0x0040 /* clear context */ -+#define HIFN_CRYPT_CMD_NEW_KEY 0x0800 /* expect new key */ -+#define HIFN_CRYPT_CMD_NEW_IV 0x1000 /* expect new iv */ -+ -+#define HIFN_CRYPT_CMD_SRCLEN_M 0xc000 -+#define HIFN_CRYPT_CMD_SRCLEN_S 14 -+ -+#define HIFN_CRYPT_CMD_KSZ_MASK 0x0600 /* AES key size: */ -+#define HIFN_CRYPT_CMD_KSZ_128 0x0000 /* 128 bit */ -+#define HIFN_CRYPT_CMD_KSZ_192 0x0200 /* 192 bit */ -+#define HIFN_CRYPT_CMD_KSZ_256 0x0400 /* 256 bit */ -+ -+/* -+ * Structure to help build up the command data structure. -+ */ -+typedef struct hifn_mac_command { -+ volatile u_int16_t masks; -+ volatile u_int16_t header_skip; -+ volatile u_int16_t source_count; -+ volatile u_int16_t reserved; -+} hifn_mac_command_t; -+ -+#define HIFN_MAC_CMD_ALG_MASK 0x0001 -+#define HIFN_MAC_CMD_ALG_SHA1 0x0000 -+#define HIFN_MAC_CMD_ALG_MD5 0x0001 -+#define HIFN_MAC_CMD_MODE_MASK 0x000c -+#define HIFN_MAC_CMD_MODE_HMAC 0x0000 -+#define HIFN_MAC_CMD_MODE_SSL_MAC 0x0004 -+#define HIFN_MAC_CMD_MODE_HASH 0x0008 -+#define HIFN_MAC_CMD_MODE_FULL 0x0004 -+#define HIFN_MAC_CMD_TRUNC 0x0010 -+#define HIFN_MAC_CMD_RESULT 0x0020 -+#define HIFN_MAC_CMD_APPEND 0x0040 -+#define HIFN_MAC_CMD_SRCLEN_M 0xc000 -+#define HIFN_MAC_CMD_SRCLEN_S 14 -+ -+/* -+ * MAC POS IPsec initiates authentication after encryption on encodes -+ * and before decryption on decodes. -+ */ -+#define HIFN_MAC_CMD_POS_IPSEC 0x0200 -+#define HIFN_MAC_CMD_NEW_KEY 0x0800 -+ -+/* -+ * The poll frequency and poll scalar defines are unshifted values used -+ * to set fields in the DMA Configuration Register. -+ */ -+#ifndef HIFN_POLL_FREQUENCY -+#define HIFN_POLL_FREQUENCY 0x1 -+#endif -+ -+#ifndef HIFN_POLL_SCALAR -+#define HIFN_POLL_SCALAR 0x0 -+#endif -+ -+#define HIFN_MAX_SEGLEN 0xffff /* maximum dma segment len */ -+#define HIFN_MAX_DMALEN 0x3ffff /* maximum dma length */ -+#endif /* __HIFN_H__ */ -diff -Nur linux-3.0.4.orig/crypto/ocf/hifn/hifn7751var.h linux-3.0.4/crypto/ocf/hifn/hifn7751var.h ---- linux-3.0.4.orig/crypto/ocf/hifn/hifn7751var.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/hifn/hifn7751var.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,368 @@ -+/* $FreeBSD: src/sys/dev/hifn/hifn7751var.h,v 1.9 2007/03/21 03:42:49 sam Exp $ */ -+/* $OpenBSD: hifn7751var.h,v 1.42 2002/04/08 17:49:42 jason Exp $ */ -+ -+/*- -+ * Invertex AEON / Hifn 7751 driver -+ * Copyright (c) 1999 Invertex Inc. All rights reserved. -+ * Copyright (c) 1999 Theo de Raadt -+ * Copyright (c) 2000-2001 Network Security Technologies, Inc. -+ * http://www.netsec.net -+ * -+ * Please send any comments, feedback, bug-fixes, or feature requests to -+ * software@invertex.com. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored in part by the Defense Advanced Research Projects -+ * Agency (DARPA) and Air Force Research Laboratory, Air Force -+ * Materiel Command, USAF, under agreement number F30602-01-2-0537. -+ * -+ */ -+ -+#ifndef __HIFN7751VAR_H__ -+#define __HIFN7751VAR_H__ -+ -+#ifdef __KERNEL__ -+ -+/* -+ * Some configurable values for the driver. By default command+result -+ * descriptor rings are the same size. The src+dst descriptor rings -+ * are sized at 3.5x the number of potential commands. Slower parts -+ * (e.g. 7951) tend to run out of src descriptors; faster parts (7811) -+ * src+cmd/result descriptors. It's not clear that increasing the size -+ * of the descriptor rings helps performance significantly as other -+ * factors tend to come into play (e.g. copying misaligned packets). -+ */ -+#define HIFN_D_CMD_RSIZE 24 /* command descriptors */ -+#define HIFN_D_SRC_RSIZE ((HIFN_D_CMD_RSIZE * 7) / 2) /* source descriptors */ -+#define HIFN_D_RES_RSIZE HIFN_D_CMD_RSIZE /* result descriptors */ -+#define HIFN_D_DST_RSIZE HIFN_D_SRC_RSIZE /* destination descriptors */ -+ -+/* -+ * Length values for cryptography -+ */ -+#define HIFN_DES_KEY_LENGTH 8 -+#define HIFN_3DES_KEY_LENGTH 24 -+#define HIFN_MAX_CRYPT_KEY_LENGTH HIFN_3DES_KEY_LENGTH -+#define HIFN_IV_LENGTH 8 -+#define HIFN_AES_IV_LENGTH 16 -+#define HIFN_MAX_IV_LENGTH HIFN_AES_IV_LENGTH -+ -+/* -+ * Length values for authentication -+ */ -+#define HIFN_MAC_KEY_LENGTH 64 -+#define HIFN_MD5_LENGTH 16 -+#define HIFN_SHA1_LENGTH 20 -+#define HIFN_MAC_TRUNC_LENGTH 12 -+ -+#define MAX_SCATTER 64 -+ -+/* -+ * Data structure to hold all 4 rings and any other ring related data. -+ */ -+struct hifn_dma { -+ /* -+ * Descriptor rings. We add +1 to the size to accomidate the -+ * jump descriptor. -+ */ -+ struct hifn_desc cmdr[HIFN_D_CMD_RSIZE+1]; -+ struct hifn_desc srcr[HIFN_D_SRC_RSIZE+1]; -+ struct hifn_desc dstr[HIFN_D_DST_RSIZE+1]; -+ struct hifn_desc resr[HIFN_D_RES_RSIZE+1]; -+ -+ struct hifn_command *hifn_commands[HIFN_D_RES_RSIZE]; -+ -+ u_char command_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_COMMAND]; -+ u_char result_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_RESULT]; -+ u_int32_t slop[HIFN_D_CMD_RSIZE]; -+ -+ u_int64_t test_src, test_dst; -+ -+ /* -+ * Our current positions for insertion and removal from the desriptor -+ * rings. -+ */ -+ int cmdi, srci, dsti, resi; -+ volatile int cmdu, srcu, dstu, resu; -+ int cmdk, srck, dstk, resk; -+}; -+ -+struct hifn_session { -+ int hs_used; -+ int hs_mlen; -+}; -+ -+#define HIFN_RING_SYNC(sc, r, i, f) \ -+ /* DAVIDM bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, (f)) */ -+ -+#define HIFN_CMDR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), cmdr, (i), (f)) -+#define HIFN_RESR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), resr, (i), (f)) -+#define HIFN_SRCR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), srcr, (i), (f)) -+#define HIFN_DSTR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), dstr, (i), (f)) -+ -+#define HIFN_CMD_SYNC(sc, i, f) \ -+ /* DAVIDM bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, (f)) */ -+ -+#define HIFN_RES_SYNC(sc, i, f) \ -+ /* DAVIDM bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, (f)) */ -+ -+typedef int bus_size_t; -+ -+/* -+ * Holds data specific to a single HIFN board. -+ */ -+struct hifn_softc { -+ softc_device_decl sc_dev; -+ -+ struct pci_dev *sc_pcidev; /* PCI device pointer */ -+ spinlock_t sc_mtx; /* per-instance lock */ -+ -+ int sc_num; /* for multiple devs */ -+ -+ ocf_iomem_t sc_bar0; -+ bus_size_t sc_bar0_lastreg;/* bar0 last reg written */ -+ ocf_iomem_t sc_bar1; -+ bus_size_t sc_bar1_lastreg;/* bar1 last reg written */ -+ -+ int sc_irq; -+ -+ u_int32_t sc_dmaier; -+ u_int32_t sc_drammodel; /* 1=dram, 0=sram */ -+ u_int32_t sc_pllconfig; /* 7954/7955/7956 PLL config */ -+ -+ struct hifn_dma *sc_dma; -+ dma_addr_t sc_dma_physaddr;/* physical address of sc_dma */ -+ -+ int sc_dmansegs; -+ int32_t sc_cid; -+ int sc_maxses; -+ int sc_nsessions; -+ struct hifn_session *sc_sessions; -+ int sc_ramsize; -+ int sc_flags; -+#define HIFN_HAS_RNG 0x1 /* includes random number generator */ -+#define HIFN_HAS_PUBLIC 0x2 /* includes public key support */ -+#define HIFN_HAS_AES 0x4 /* includes AES support */ -+#define HIFN_IS_7811 0x8 /* Hifn 7811 part */ -+#define HIFN_IS_7956 0x10 /* Hifn 7956/7955 don't have SDRAM */ -+ -+ struct timer_list sc_tickto; /* for managing DMA */ -+ -+ int sc_rngfirst; -+ int sc_rnghz; /* RNG polling frequency */ -+ -+ int sc_c_busy; /* command ring busy */ -+ int sc_s_busy; /* source data ring busy */ -+ int sc_d_busy; /* destination data ring busy */ -+ int sc_r_busy; /* result ring busy */ -+ int sc_active; /* for initial countdown */ -+ int sc_needwakeup; /* ops q'd wating on resources */ -+ int sc_curbatch; /* # ops submitted w/o int */ -+ int sc_suspended; -+#ifdef HIFN_VULCANDEV -+ struct cdev *sc_pkdev; -+#endif -+}; -+ -+#define HIFN_LOCK(_sc) spin_lock_irqsave(&(_sc)->sc_mtx, l_flags) -+#define HIFN_UNLOCK(_sc) spin_unlock_irqrestore(&(_sc)->sc_mtx, l_flags) -+ -+/* -+ * hifn_command_t -+ * -+ * This is the control structure used to pass commands to hifn_encrypt(). -+ * -+ * flags -+ * ----- -+ * Flags is the bitwise "or" values for command configuration. A single -+ * encrypt direction needs to be set: -+ * -+ * HIFN_ENCODE or HIFN_DECODE -+ * -+ * To use cryptography, a single crypto algorithm must be included: -+ * -+ * HIFN_CRYPT_3DES or HIFN_CRYPT_DES -+ * -+ * To use authentication is used, a single MAC algorithm must be included: -+ * -+ * HIFN_MAC_MD5 or HIFN_MAC_SHA1 -+ * -+ * By default MD5 uses a 16 byte hash and SHA-1 uses a 20 byte hash. -+ * If the value below is set, hash values are truncated or assumed -+ * truncated to 12 bytes: -+ * -+ * HIFN_MAC_TRUNC -+ * -+ * Keys for encryption and authentication can be sent as part of a command, -+ * or the last key value used with a particular session can be retrieved -+ * and used again if either of these flags are not specified. -+ * -+ * HIFN_CRYPT_NEW_KEY, HIFN_MAC_NEW_KEY -+ * -+ * session_num -+ * ----------- -+ * A number between 0 and 2048 (for DRAM models) or a number between -+ * 0 and 768 (for SRAM models). Those who don't want to use session -+ * numbers should leave value at zero and send a new crypt key and/or -+ * new MAC key on every command. If you use session numbers and -+ * don't send a key with a command, the last key sent for that same -+ * session number will be used. -+ * -+ * Warning: Using session numbers and multiboard at the same time -+ * is currently broken. -+ * -+ * mbuf -+ * ---- -+ * Either fill in the mbuf pointer and npa=0 or -+ * fill packp[] and packl[] and set npa to > 0 -+ * -+ * mac_header_skip -+ * --------------- -+ * The number of bytes of the source_buf that are skipped over before -+ * authentication begins. This must be a number between 0 and 2^16-1 -+ * and can be used by IPsec implementers to skip over IP headers. -+ * *** Value ignored if authentication not used *** -+ * -+ * crypt_header_skip -+ * ----------------- -+ * The number of bytes of the source_buf that are skipped over before -+ * the cryptographic operation begins. This must be a number between 0 -+ * and 2^16-1. For IPsec, this number will always be 8 bytes larger -+ * than the auth_header_skip (to skip over the ESP header). -+ * *** Value ignored if cryptography not used *** -+ * -+ */ -+struct hifn_operand { -+ union { -+ struct sk_buff *skb; -+ struct uio *io; -+ unsigned char *buf; -+ } u; -+ void *map; -+ bus_size_t mapsize; -+ int nsegs; -+ struct { -+ dma_addr_t ds_addr; -+ int ds_len; -+ } segs[MAX_SCATTER]; -+}; -+ -+struct hifn_command { -+ u_int16_t session_num; -+ u_int16_t base_masks, cry_masks, mac_masks; -+ u_int8_t iv[HIFN_MAX_IV_LENGTH], *ck, mac[HIFN_MAC_KEY_LENGTH]; -+ int cklen; -+ int sloplen, slopidx; -+ -+ struct hifn_operand src; -+ struct hifn_operand dst; -+ -+ struct hifn_softc *softc; -+ struct cryptop *crp; -+ struct cryptodesc *enccrd, *maccrd; -+}; -+ -+#define src_skb src.u.skb -+#define src_io src.u.io -+#define src_map src.map -+#define src_mapsize src.mapsize -+#define src_segs src.segs -+#define src_nsegs src.nsegs -+#define src_buf src.u.buf -+ -+#define dst_skb dst.u.skb -+#define dst_io dst.u.io -+#define dst_map dst.map -+#define dst_mapsize dst.mapsize -+#define dst_segs dst.segs -+#define dst_nsegs dst.nsegs -+#define dst_buf dst.u.buf -+ -+/* -+ * Return values for hifn_crypto() -+ */ -+#define HIFN_CRYPTO_SUCCESS 0 -+#define HIFN_CRYPTO_BAD_INPUT (-1) -+#define HIFN_CRYPTO_RINGS_FULL (-2) -+ -+/************************************************************************** -+ * -+ * Function: hifn_crypto -+ * -+ * Purpose: Called by external drivers to begin an encryption on the -+ * HIFN board. -+ * -+ * Blocking/Non-blocking Issues -+ * ============================ -+ * The driver cannot block in hifn_crypto (no calls to tsleep) currently. -+ * hifn_crypto() returns HIFN_CRYPTO_RINGS_FULL if there is not enough -+ * room in any of the rings for the request to proceed. -+ * -+ * Return Values -+ * ============= -+ * 0 for success, negative values on error -+ * -+ * Defines for negative error codes are: -+ * -+ * HIFN_CRYPTO_BAD_INPUT : The passed in command had invalid settings. -+ * HIFN_CRYPTO_RINGS_FULL : All DMA rings were full and non-blocking -+ * behaviour was requested. -+ * -+ *************************************************************************/ -+ -+/* -+ * Convert back and forth from 'sid' to 'card' and 'session' -+ */ -+#define HIFN_CARD(sid) (((sid) & 0xf0000000) >> 28) -+#define HIFN_SESSION(sid) ((sid) & 0x000007ff) -+#define HIFN_SID(crd,ses) (((crd) << 28) | ((ses) & 0x7ff)) -+ -+#endif /* _KERNEL */ -+ -+struct hifn_stats { -+ u_int64_t hst_ibytes; -+ u_int64_t hst_obytes; -+ u_int32_t hst_ipackets; -+ u_int32_t hst_opackets; -+ u_int32_t hst_invalid; -+ u_int32_t hst_nomem; /* malloc or one of hst_nomem_* */ -+ u_int32_t hst_abort; -+ u_int32_t hst_noirq; /* IRQ for no reason */ -+ u_int32_t hst_totbatch; /* ops submitted w/o interrupt */ -+ u_int32_t hst_maxbatch; /* max ops submitted together */ -+ u_int32_t hst_unaligned; /* unaligned src caused copy */ -+ /* -+ * The following divides hst_nomem into more specific buckets. -+ */ -+ u_int32_t hst_nomem_map; /* bus_dmamap_create failed */ -+ u_int32_t hst_nomem_load; /* bus_dmamap_load_* failed */ -+ u_int32_t hst_nomem_mbuf; /* MGET* failed */ -+ u_int32_t hst_nomem_mcl; /* MCLGET* failed */ -+ u_int32_t hst_nomem_cr; /* out of command/result descriptor */ -+ u_int32_t hst_nomem_sd; /* out of src/dst descriptors */ -+}; -+ -+#endif /* __HIFN7751VAR_H__ */ -diff -Nur linux-3.0.4.orig/crypto/ocf/hifn/hifnHIPP.c linux-3.0.4/crypto/ocf/hifn/hifnHIPP.c ---- linux-3.0.4.orig/crypto/ocf/hifn/hifnHIPP.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/hifn/hifnHIPP.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,420 @@ -+/*- -+ * Driver for Hifn HIPP-I/II chipset -+ * Copyright (c) 2006 Michael Richardson -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored by Hifn Inc. -+ * -+ */ -+ -+/* -+ * Driver for various Hifn encryption processors. -+ */ -+#include -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "hifnHIPPreg.h" -+#include "hifnHIPPvar.h" -+ -+#if 1 -+#define DPRINTF(a...) if (hipp_debug) { \ -+ printk("%s: ", sc ? \ -+ device_get_nameunit(sc->sc_dev) : "hifn"); \ -+ printk(a); \ -+ } else -+#else -+#define DPRINTF(a...) -+#endif -+ -+typedef int bus_size_t; -+ -+static inline int -+pci_get_revid(struct pci_dev *dev) -+{ -+ u8 rid = 0; -+ pci_read_config_byte(dev, PCI_REVISION_ID, &rid); -+ return rid; -+} -+ -+#define debug hipp_debug -+int hipp_debug = 0; -+module_param(hipp_debug, int, 0644); -+MODULE_PARM_DESC(hipp_debug, "Enable debug"); -+ -+int hipp_maxbatch = 1; -+module_param(hipp_maxbatch, int, 0644); -+MODULE_PARM_DESC(hipp_maxbatch, "max ops to batch w/o interrupt"); -+ -+static int hipp_probe(struct pci_dev *dev, const struct pci_device_id *ent); -+static void hipp_remove(struct pci_dev *dev); -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) -+static irqreturn_t hipp_intr(int irq, void *arg); -+#else -+static irqreturn_t hipp_intr(int irq, void *arg, struct pt_regs *regs); -+#endif -+ -+static int hipp_num_chips = 0; -+static struct hipp_softc *hipp_chip_idx[HIPP_MAX_CHIPS]; -+ -+static int hipp_newsession(device_t, u_int32_t *, struct cryptoini *); -+static int hipp_freesession(device_t, u_int64_t); -+static int hipp_process(device_t, struct cryptop *, int); -+ -+static device_method_t hipp_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, hipp_newsession), -+ DEVMETHOD(cryptodev_freesession,hipp_freesession), -+ DEVMETHOD(cryptodev_process, hipp_process), -+}; -+ -+static __inline u_int32_t -+READ_REG(struct hipp_softc *sc, unsigned int barno, bus_size_t reg) -+{ -+ u_int32_t v = readl(sc->sc_bar[barno] + reg); -+ //sc->sc_bar0_lastreg = (bus_size_t) -1; -+ return (v); -+} -+static __inline void -+WRITE_REG(struct hipp_softc *sc, unsigned int barno, bus_size_t reg, u_int32_t val) -+{ -+ writel(val, sc->sc_bar[barno] + reg); -+} -+ -+#define READ_REG_0(sc, reg) READ_REG(sc, 0, reg) -+#define WRITE_REG_0(sc, reg, val) WRITE_REG(sc,0, reg, val) -+#define READ_REG_1(sc, reg) READ_REG(sc, 1, reg) -+#define WRITE_REG_1(sc, reg, val) WRITE_REG(sc,1, reg, val) -+ -+static int -+hipp_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) -+{ -+ return EINVAL; -+} -+ -+static int -+hipp_freesession(device_t dev, u_int64_t tid) -+{ -+ return EINVAL; -+} -+ -+static int -+hipp_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ return EINVAL; -+} -+ -+static const char* -+hipp_partname(struct hipp_softc *sc, char buf[128], size_t blen) -+{ -+ char *n = NULL; -+ -+ switch (pci_get_vendor(sc->sc_pcidev)) { -+ case PCI_VENDOR_HIFN: -+ switch (pci_get_device(sc->sc_pcidev)) { -+ case PCI_PRODUCT_HIFN_7855: n = "Hifn 7855"; -+ case PCI_PRODUCT_HIFN_8155: n = "Hifn 8155"; -+ case PCI_PRODUCT_HIFN_6500: n = "Hifn 6500"; -+ } -+ } -+ -+ if(n==NULL) { -+ snprintf(buf, blen, "VID=%02x,PID=%02x", -+ pci_get_vendor(sc->sc_pcidev), -+ pci_get_device(sc->sc_pcidev)); -+ } else { -+ buf[0]='\0'; -+ strncat(buf, n, blen); -+ } -+ return buf; -+} -+ -+struct hipp_fs_entry { -+ struct attribute attr; -+ /* other stuff */ -+}; -+ -+ -+static ssize_t -+cryptoid_show(struct device *dev, -+ struct device_attribute *attr, -+ char *buf) -+{ -+ struct hipp_softc *sc; -+ -+ sc = pci_get_drvdata(to_pci_dev (dev)); -+ return sprintf (buf, "%d\n", sc->sc_cid); -+} -+ -+struct device_attribute hipp_dev_cryptoid = __ATTR_RO(cryptoid); -+ -+/* -+ * Attach an interface that successfully probed. -+ */ -+static int -+hipp_probe(struct pci_dev *dev, const struct pci_device_id *ent) -+{ -+ struct hipp_softc *sc = NULL; -+ int i; -+ //char rbase; -+ //u_int16_t ena; -+ int rev; -+ //int rseg; -+ int rc; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (pci_enable_device(dev) < 0) -+ return(-ENODEV); -+ -+ if (pci_set_mwi(dev)) -+ return(-ENODEV); -+ -+ if (!dev->irq) { -+ printk("hifn: found device with no IRQ assigned. check BIOS settings!"); -+ pci_disable_device(dev); -+ return(-ENODEV); -+ } -+ -+ sc = (struct hipp_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); -+ if (!sc) -+ return(-ENOMEM); -+ memset(sc, 0, sizeof(*sc)); -+ -+ softc_device_init(sc, "hifn-hipp", hipp_num_chips, hipp_methods); -+ -+ sc->sc_pcidev = dev; -+ sc->sc_irq = -1; -+ sc->sc_cid = -1; -+ sc->sc_num = hipp_num_chips++; -+ -+ if (sc->sc_num < HIPP_MAX_CHIPS) -+ hipp_chip_idx[sc->sc_num] = sc; -+ -+ pci_set_drvdata(sc->sc_pcidev, sc); -+ -+ spin_lock_init(&sc->sc_mtx); -+ -+ /* -+ * Setup PCI resources. -+ * The READ_REG_0, WRITE_REG_0, READ_REG_1, -+ * and WRITE_REG_1 macros throughout the driver are used -+ * to permit better debugging. -+ */ -+ for(i=0; i<4; i++) { -+ unsigned long mem_start, mem_len; -+ mem_start = pci_resource_start(sc->sc_pcidev, i); -+ mem_len = pci_resource_len(sc->sc_pcidev, i); -+ sc->sc_barphy[i] = (caddr_t)mem_start; -+ sc->sc_bar[i] = (ocf_iomem_t) ioremap(mem_start, mem_len); -+ if (!sc->sc_bar[i]) { -+ device_printf(sc->sc_dev, "cannot map bar%d register space\n", i); -+ goto fail; -+ } -+ } -+ -+ //hipp_reset_board(sc, 0); -+ pci_set_master(sc->sc_pcidev); -+ -+ /* -+ * Arrange the interrupt line. -+ */ -+ rc = request_irq(dev->irq, hipp_intr, IRQF_SHARED, "hifn", sc); -+ if (rc) { -+ device_printf(sc->sc_dev, "could not map interrupt: %d\n", rc); -+ goto fail; -+ } -+ sc->sc_irq = dev->irq; -+ -+ rev = READ_REG_1(sc, HIPP_1_REVID) & 0xffff; -+ -+ { -+ char b[32]; -+ device_printf(sc->sc_dev, "%s, rev %u", -+ hipp_partname(sc, b, sizeof(b)), rev); -+ } -+ -+#if 0 -+ if (sc->sc_flags & HIFN_IS_7956) -+ printf(", pll=0x%x<%s clk, %ux mult>", -+ sc->sc_pllconfig, -+ sc->sc_pllconfig & HIFN_PLL_REF_SEL ? "ext" : "pci", -+ 2 + 2*((sc->sc_pllconfig & HIFN_PLL_ND) >> 11)); -+#endif -+ printf("\n"); -+ -+ sc->sc_cid = crypto_get_driverid(softc_get_device(sc),CRYPTOCAP_F_HARDWARE); -+ if (sc->sc_cid < 0) { -+ device_printf(sc->sc_dev, "could not get crypto driver id\n"); -+ goto fail; -+ } -+ -+#if 0 /* cannot work with a non-GPL module */ -+ /* make a sysfs entry to let the world know what entry we got */ -+ sysfs_create_file(&sc->sc_pcidev->dev.kobj, &hipp_dev_cryptoid.attr); -+#endif -+ -+#if 0 -+ init_timer(&sc->sc_tickto); -+ sc->sc_tickto.function = hifn_tick; -+ sc->sc_tickto.data = (unsigned long) sc->sc_num; -+ mod_timer(&sc->sc_tickto, jiffies + HZ); -+#endif -+ -+#if 0 /* no code here yet ?? */ -+ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); -+#endif -+ -+ return (0); -+ -+fail: -+ if (sc->sc_cid >= 0) -+ crypto_unregister_all(sc->sc_cid); -+ if (sc->sc_irq != -1) -+ free_irq(sc->sc_irq, sc); -+ -+#if 0 -+ if (sc->sc_dma) { -+ /* Turn off DMA polling */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | -+ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); -+ -+ pci_free_consistent(sc->sc_pcidev, -+ sizeof(*sc->sc_dma), -+ sc->sc_dma, sc->sc_dma_physaddr); -+ } -+#endif -+ kfree(sc); -+ return (-ENXIO); -+} -+ -+/* -+ * Detach an interface that successfully probed. -+ */ -+static void -+hipp_remove(struct pci_dev *dev) -+{ -+ struct hipp_softc *sc = pci_get_drvdata(dev); -+ unsigned long l_flags; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ /* disable interrupts */ -+ HIPP_LOCK(sc); -+ -+#if 0 -+ WRITE_REG_1(sc, HIFN_1_DMA_IER, 0); -+ HIFN_UNLOCK(sc); -+ -+ /*XXX other resources */ -+ del_timer_sync(&sc->sc_tickto); -+ -+ /* Turn off DMA polling */ -+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | -+ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); -+#endif -+ -+ crypto_unregister_all(sc->sc_cid); -+ -+ free_irq(sc->sc_irq, sc); -+ -+#if 0 -+ pci_free_consistent(sc->sc_pcidev, sizeof(*sc->sc_dma), -+ sc->sc_dma, sc->sc_dma_physaddr); -+#endif -+} -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) -+static irqreturn_t hipp_intr(int irq, void *arg) -+#else -+static irqreturn_t hipp_intr(int irq, void *arg, struct pt_regs *regs) -+#endif -+{ -+ struct hipp_softc *sc = arg; -+ -+ sc = sc; /* shut up compiler */ -+ -+ return IRQ_HANDLED; -+} -+ -+static struct pci_device_id hipp_pci_tbl[] = { -+ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7855, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_8155, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+}; -+MODULE_DEVICE_TABLE(pci, hipp_pci_tbl); -+ -+static struct pci_driver hipp_driver = { -+ .name = "hipp", -+ .id_table = hipp_pci_tbl, -+ .probe = hipp_probe, -+ .remove = hipp_remove, -+ /* add PM stuff here one day */ -+}; -+ -+static int __init hipp_init (void) -+{ -+ struct hipp_softc *sc = NULL; -+ int rc; -+ -+ DPRINTF("%s(%p)\n", __FUNCTION__, hipp_init); -+ -+ rc = pci_register_driver(&hipp_driver); -+ pci_register_driver_compat(&hipp_driver, rc); -+ -+ return rc; -+} -+ -+static void __exit hipp_exit (void) -+{ -+ pci_unregister_driver(&hipp_driver); -+} -+ -+module_init(hipp_init); -+module_exit(hipp_exit); -+ -+MODULE_LICENSE("BSD"); -+MODULE_AUTHOR("Michael Richardson "); -+MODULE_DESCRIPTION("OCF driver for hifn HIPP-I/II PCI crypto devices"); -diff -Nur linux-3.0.4.orig/crypto/ocf/hifn/hifnHIPPreg.h linux-3.0.4/crypto/ocf/hifn/hifnHIPPreg.h ---- linux-3.0.4.orig/crypto/ocf/hifn/hifnHIPPreg.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/hifn/hifnHIPPreg.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,46 @@ -+/*- -+ * Hifn HIPP-I/HIPP-II (7855/8155) driver. -+ * Copyright (c) 2006 Michael Richardson -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored by Hifn inc. -+ * -+ */ -+ -+#ifndef __HIFNHIPP_H__ -+#define __HIFNHIPP_H__ -+ -+/* -+ * PCI vendor and device identifiers -+ */ -+#define PCI_VENDOR_HIFN 0x13a3 /* Hifn */ -+#define PCI_PRODUCT_HIFN_6500 0x0006 /* 6500 */ -+#define PCI_PRODUCT_HIFN_7855 0x001f /* 7855 */ -+#define PCI_PRODUCT_HIFN_8155 0x999 /* XXX 8155 */ -+ -+#define HIPP_1_REVID 0x01 /* BOGUS */ -+ -+#endif /* __HIPP_H__ */ -diff -Nur linux-3.0.4.orig/crypto/ocf/hifn/hifnHIPPvar.h linux-3.0.4/crypto/ocf/hifn/hifnHIPPvar.h ---- linux-3.0.4.orig/crypto/ocf/hifn/hifnHIPPvar.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/hifn/hifnHIPPvar.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,93 @@ -+/* -+ * Hifn HIPP-I/HIPP-II (7855/8155) driver. -+ * Copyright (c) 2006 Michael Richardson * -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored by Hifn inc. -+ * -+ */ -+ -+#ifndef __HIFNHIPPVAR_H__ -+#define __HIFNHIPPVAR_H__ -+ -+#define HIPP_MAX_CHIPS 8 -+ -+/* -+ * Holds data specific to a single Hifn HIPP-I board. -+ */ -+struct hipp_softc { -+ softc_device_decl sc_dev; -+ -+ struct pci_dev *sc_pcidev; /* device backpointer */ -+ ocf_iomem_t sc_bar[5]; -+ caddr_t sc_barphy[5]; /* physical address */ -+ int sc_num; /* for multiple devs */ -+ spinlock_t sc_mtx; /* per-instance lock */ -+ int32_t sc_cid; -+ int sc_irq; -+ -+#if 0 -+ -+ u_int32_t sc_dmaier; -+ u_int32_t sc_drammodel; /* 1=dram, 0=sram */ -+ u_int32_t sc_pllconfig; /* 7954/7955/7956 PLL config */ -+ -+ struct hifn_dma *sc_dma; -+ dma_addr_t sc_dma_physaddr;/* physical address of sc_dma */ -+ -+ int sc_dmansegs; -+ int sc_maxses; -+ int sc_nsessions; -+ struct hifn_session *sc_sessions; -+ int sc_ramsize; -+ int sc_flags; -+#define HIFN_HAS_RNG 0x1 /* includes random number generator */ -+#define HIFN_HAS_PUBLIC 0x2 /* includes public key support */ -+#define HIFN_HAS_AES 0x4 /* includes AES support */ -+#define HIFN_IS_7811 0x8 /* Hifn 7811 part */ -+#define HIFN_IS_7956 0x10 /* Hifn 7956/7955 don't have SDRAM */ -+ -+ struct timer_list sc_tickto; /* for managing DMA */ -+ -+ int sc_rngfirst; -+ int sc_rnghz; /* RNG polling frequency */ -+ -+ int sc_c_busy; /* command ring busy */ -+ int sc_s_busy; /* source data ring busy */ -+ int sc_d_busy; /* destination data ring busy */ -+ int sc_r_busy; /* result ring busy */ -+ int sc_active; /* for initial countdown */ -+ int sc_needwakeup; /* ops q'd wating on resources */ -+ int sc_curbatch; /* # ops submitted w/o int */ -+ int sc_suspended; -+ struct miscdevice sc_miscdev; -+#endif -+}; -+ -+#define HIPP_LOCK(_sc) spin_lock_irqsave(&(_sc)->sc_mtx, l_flags) -+#define HIPP_UNLOCK(_sc) spin_unlock_irqrestore(&(_sc)->sc_mtx, l_flags) -+ -+#endif /* __HIFNHIPPVAR_H__ */ -diff -Nur linux-3.0.4.orig/crypto/ocf/ixp4xx/.#ixp4xx.c.1.46 linux-3.0.4/crypto/ocf/ixp4xx/.#ixp4xx.c.1.46 ---- linux-3.0.4.orig/crypto/ocf/ixp4xx/.#ixp4xx.c.1.46 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/ixp4xx/.#ixp4xx.c.1.46 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,1323 @@ -+/* -+ * An OCF module that uses Intels IXP CryptACC API to do the crypto. -+ * This driver requires the IXP400 Access Library that is available -+ * from Intel in order to operate (or compile). -+ * -+ * Written by David McCullough -+ * Copyright (C) 2006-2007 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * ALTERNATIVELY, provided that this notice is retained in full, this product -+ * may be distributed under the terms of the GNU General Public License (GPL), -+ * in which case the provisions of the GPL apply INSTEAD OF those given above. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ */ -+ -+#ifndef AUTOCONF_INCLUDED -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#ifndef IX_MBUF_PRIV -+#define IX_MBUF_PRIV(x) ((x)->priv) -+#endif -+ -+struct ixp_data; -+ -+struct ixp_q { -+ struct list_head ixp_q_list; -+ struct ixp_data *ixp_q_data; -+ struct cryptop *ixp_q_crp; -+ struct cryptodesc *ixp_q_ccrd; -+ struct cryptodesc *ixp_q_acrd; -+ IX_MBUF ixp_q_mbuf; -+ UINT8 *ixp_hash_dest; /* Location for hash in client buffer */ -+ UINT8 *ixp_hash_src; /* Location of hash in internal buffer */ -+ unsigned char ixp_q_iv_data[IX_CRYPTO_ACC_MAX_CIPHER_IV_LENGTH]; -+ unsigned char *ixp_q_iv; -+}; -+ -+struct ixp_data { -+ int ixp_registered; /* is the context registered */ -+ int ixp_crd_flags; /* detect direction changes */ -+ -+ int ixp_cipher_alg; -+ int ixp_auth_alg; -+ -+ UINT32 ixp_ctx_id; -+ UINT32 ixp_hash_key_id; /* used when hashing */ -+ IxCryptoAccCtx ixp_ctx; -+ IX_MBUF ixp_pri_mbuf; -+ IX_MBUF ixp_sec_mbuf; -+ -+ struct work_struct ixp_pending_work; -+ struct work_struct ixp_registration_work; -+ struct list_head ixp_q; /* unprocessed requests */ -+}; -+ -+#ifdef __ixp46X -+ -+#define MAX_IOP_SIZE 64 /* words */ -+#define MAX_OOP_SIZE 128 -+ -+#define MAX_PARAMS 3 -+ -+struct ixp_pkq { -+ struct list_head pkq_list; -+ struct cryptkop *pkq_krp; -+ -+ IxCryptoAccPkeEauInOperands pkq_op; -+ IxCryptoAccPkeEauOpResult pkq_result; -+ -+ UINT32 pkq_ibuf0[MAX_IOP_SIZE]; -+ UINT32 pkq_ibuf1[MAX_IOP_SIZE]; -+ UINT32 pkq_ibuf2[MAX_IOP_SIZE]; -+ UINT32 pkq_obuf[MAX_OOP_SIZE]; -+}; -+ -+static LIST_HEAD(ixp_pkq); /* current PK wait list */ -+static struct ixp_pkq *ixp_pk_cur; -+static spinlock_t ixp_pkq_lock; -+ -+#endif /* __ixp46X */ -+ -+static int ixp_blocked = 0; -+ -+static int32_t ixp_id = -1; -+static struct ixp_data **ixp_sessions = NULL; -+static u_int32_t ixp_sesnum = 0; -+ -+static int ixp_process(device_t, struct cryptop *, int); -+static int ixp_newsession(device_t, u_int32_t *, struct cryptoini *); -+static int ixp_freesession(device_t, u_int64_t); -+#ifdef __ixp46X -+static int ixp_kprocess(device_t, struct cryptkop *krp, int hint); -+#endif -+ -+static struct kmem_cache *qcache; -+ -+#define debug ixp_debug -+static int ixp_debug = 0; -+module_param(ixp_debug, int, 0644); -+MODULE_PARM_DESC(ixp_debug, "Enable debug"); -+ -+static int ixp_init_crypto = 1; -+module_param(ixp_init_crypto, int, 0444); /* RO after load/boot */ -+MODULE_PARM_DESC(ixp_init_crypto, "Call ixCryptoAccInit (default is 1)"); -+ -+static void ixp_process_pending(void *arg); -+static void ixp_registration(void *arg); -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void ixp_process_pending_wq(struct work_struct *work); -+static void ixp_registration_wq(struct work_struct *work); -+#endif -+ -+/* -+ * dummy device structure -+ */ -+ -+static struct { -+ softc_device_decl sc_dev; -+} ixpdev; -+ -+static device_method_t ixp_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, ixp_newsession), -+ DEVMETHOD(cryptodev_freesession,ixp_freesession), -+ DEVMETHOD(cryptodev_process, ixp_process), -+#ifdef __ixp46X -+ DEVMETHOD(cryptodev_kprocess, ixp_kprocess), -+#endif -+}; -+ -+/* -+ * Generate a new software session. -+ */ -+static int -+ixp_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) -+{ -+ struct ixp_data *ixp; -+ u_int32_t i; -+#define AUTH_LEN(cri, def) \ -+ (cri->cri_mlen ? cri->cri_mlen : (def)) -+ -+ dprintk("%s():alg %d\n", __FUNCTION__,cri->cri_alg); -+ if (sid == NULL || cri == NULL) { -+ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ if (ixp_sessions) { -+ for (i = 1; i < ixp_sesnum; i++) -+ if (ixp_sessions[i] == NULL) -+ break; -+ } else -+ i = 1; /* NB: to silence compiler warning */ -+ -+ if (ixp_sessions == NULL || i == ixp_sesnum) { -+ struct ixp_data **ixpd; -+ -+ if (ixp_sessions == NULL) { -+ i = 1; /* We leave ixp_sessions[0] empty */ -+ ixp_sesnum = CRYPTO_SW_SESSIONS; -+ } else -+ ixp_sesnum *= 2; -+ -+ ixpd = kmalloc(ixp_sesnum * sizeof(struct ixp_data *), SLAB_ATOMIC); -+ if (ixpd == NULL) { -+ /* Reset session number */ -+ if (ixp_sesnum == CRYPTO_SW_SESSIONS) -+ ixp_sesnum = 0; -+ else -+ ixp_sesnum /= 2; -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memset(ixpd, 0, ixp_sesnum * sizeof(struct ixp_data *)); -+ -+ /* Copy existing sessions */ -+ if (ixp_sessions) { -+ memcpy(ixpd, ixp_sessions, -+ (ixp_sesnum / 2) * sizeof(struct ixp_data *)); -+ kfree(ixp_sessions); -+ } -+ -+ ixp_sessions = ixpd; -+ } -+ -+ ixp_sessions[i] = (struct ixp_data *) kmalloc(sizeof(struct ixp_data), -+ SLAB_ATOMIC); -+ if (ixp_sessions[i] == NULL) { -+ ixp_freesession(NULL, i); -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ -+ *sid = i; -+ -+ ixp = ixp_sessions[i]; -+ memset(ixp, 0, sizeof(*ixp)); -+ -+ ixp->ixp_cipher_alg = -1; -+ ixp->ixp_auth_alg = -1; -+ ixp->ixp_ctx_id = -1; -+ INIT_LIST_HEAD(&ixp->ixp_q); -+ -+ ixp->ixp_ctx.useDifferentSrcAndDestMbufs = 0; -+ -+ while (cri) { -+ switch (cri->cri_alg) { -+ case CRYPTO_DES_CBC: -+ ixp->ixp_cipher_alg = cri->cri_alg; -+ ixp->ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_DES; -+ ixp->ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; -+ ixp->ixp_ctx.cipherCtx.cipherKeyLen = (cri->cri_klen + 7) / 8; -+ ixp->ixp_ctx.cipherCtx.cipherBlockLen = IX_CRYPTO_ACC_DES_BLOCK_64; -+ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen = -+ IX_CRYPTO_ACC_DES_IV_64; -+ memcpy(ixp->ixp_ctx.cipherCtx.key.cipherKey, -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ break; -+ -+ case CRYPTO_3DES_CBC: -+ ixp->ixp_cipher_alg = cri->cri_alg; -+ ixp->ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_3DES; -+ ixp->ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; -+ ixp->ixp_ctx.cipherCtx.cipherKeyLen = (cri->cri_klen + 7) / 8; -+ ixp->ixp_ctx.cipherCtx.cipherBlockLen = IX_CRYPTO_ACC_DES_BLOCK_64; -+ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen = -+ IX_CRYPTO_ACC_DES_IV_64; -+ memcpy(ixp->ixp_ctx.cipherCtx.key.cipherKey, -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ break; -+ -+ case CRYPTO_RIJNDAEL128_CBC: -+ ixp->ixp_cipher_alg = cri->cri_alg; -+ ixp->ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_AES; -+ ixp->ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; -+ ixp->ixp_ctx.cipherCtx.cipherKeyLen = (cri->cri_klen + 7) / 8; -+ ixp->ixp_ctx.cipherCtx.cipherBlockLen = 16; -+ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen = 16; -+ memcpy(ixp->ixp_ctx.cipherCtx.key.cipherKey, -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ break; -+ -+ case CRYPTO_MD5: -+ case CRYPTO_MD5_HMAC: -+ ixp->ixp_auth_alg = cri->cri_alg; -+ ixp->ixp_ctx.authCtx.authAlgo = IX_CRYPTO_ACC_AUTH_MD5; -+ ixp->ixp_ctx.authCtx.authDigestLen = AUTH_LEN(cri, MD5_HASH_LEN); -+ ixp->ixp_ctx.authCtx.aadLen = 0; -+ /* Only MD5_HMAC needs a key */ -+ if (cri->cri_alg == CRYPTO_MD5_HMAC) { -+ ixp->ixp_ctx.authCtx.authKeyLen = (cri->cri_klen + 7) / 8; -+ if (ixp->ixp_ctx.authCtx.authKeyLen > -+ sizeof(ixp->ixp_ctx.authCtx.key.authKey)) { -+ printk( -+ "ixp4xx: Invalid key length for MD5_HMAC - %d bits\n", -+ cri->cri_klen); -+ ixp_freesession(NULL, i); -+ return EINVAL; -+ } -+ memcpy(ixp->ixp_ctx.authCtx.key.authKey, -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ } -+ break; -+ -+ case CRYPTO_SHA1: -+ case CRYPTO_SHA1_HMAC: -+ ixp->ixp_auth_alg = cri->cri_alg; -+ ixp->ixp_ctx.authCtx.authAlgo = IX_CRYPTO_ACC_AUTH_SHA1; -+ ixp->ixp_ctx.authCtx.authDigestLen = AUTH_LEN(cri, SHA1_HASH_LEN); -+ ixp->ixp_ctx.authCtx.aadLen = 0; -+ /* Only SHA1_HMAC needs a key */ -+ if (cri->cri_alg == CRYPTO_SHA1_HMAC) { -+ ixp->ixp_ctx.authCtx.authKeyLen = (cri->cri_klen + 7) / 8; -+ if (ixp->ixp_ctx.authCtx.authKeyLen > -+ sizeof(ixp->ixp_ctx.authCtx.key.authKey)) { -+ printk( -+ "ixp4xx: Invalid key length for SHA1_HMAC - %d bits\n", -+ cri->cri_klen); -+ ixp_freesession(NULL, i); -+ return EINVAL; -+ } -+ memcpy(ixp->ixp_ctx.authCtx.key.authKey, -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ } -+ break; -+ -+ default: -+ printk("ixp: unknown algo 0x%x\n", cri->cri_alg); -+ ixp_freesession(NULL, i); -+ return EINVAL; -+ } -+ cri = cri->cri_next; -+ } -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ INIT_WORK(&ixp->ixp_pending_work, ixp_process_pending_wq); -+ INIT_WORK(&ixp->ixp_registration_work, ixp_registration_wq); -+#else -+ INIT_WORK(&ixp->ixp_pending_work, ixp_process_pending, ixp); -+ INIT_WORK(&ixp->ixp_registration_work, ixp_registration, ixp); -+#endif -+ -+ return 0; -+} -+ -+ -+/* -+ * Free a session. -+ */ -+static int -+ixp_freesession(device_t dev, u_int64_t tid) -+{ -+ u_int32_t sid = CRYPTO_SESID2LID(tid); -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid > ixp_sesnum || ixp_sessions == NULL || -+ ixp_sessions[sid] == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ /* Silently accept and return */ -+ if (sid == 0) -+ return 0; -+ -+ if (ixp_sessions[sid]) { -+ if (ixp_sessions[sid]->ixp_ctx_id != -1) { -+ ixCryptoAccCtxUnregister(ixp_sessions[sid]->ixp_ctx_id); -+ ixp_sessions[sid]->ixp_ctx_id = -1; -+ } -+ -+ flush_scheduled_work(); -+ -+ kfree(ixp_sessions[sid]); -+ } -+ ixp_sessions[sid] = NULL; -+ if (ixp_blocked) { -+ ixp_blocked = 0; -+ crypto_unblock(ixp_id, CRYPTO_SYMQ); -+ } -+ return 0; -+} -+ -+ -+/* -+ * callback for when hash processing is complete -+ */ -+ -+static void -+ixp_hash_perform_cb( -+ UINT32 hash_key_id, -+ IX_MBUF *bufp, -+ IxCryptoAccStatus status) -+{ -+ struct ixp_q *q; -+ -+ dprintk("%s(%u, %p, 0x%x)\n", __FUNCTION__, hash_key_id, bufp, status); -+ -+ if (bufp == NULL) { -+ printk("ixp: NULL buf in %s\n", __FUNCTION__); -+ return; -+ } -+ -+ q = IX_MBUF_PRIV(bufp); -+ if (q == NULL) { -+ printk("ixp: NULL priv in %s\n", __FUNCTION__); -+ return; -+ } -+ -+ if (status == IX_CRYPTO_ACC_STATUS_SUCCESS) { -+ /* On success, need to copy hash back into original client buffer */ -+ memcpy(q->ixp_hash_dest, q->ixp_hash_src, -+ (q->ixp_q_data->ixp_auth_alg == CRYPTO_SHA1) ? -+ SHA1_HASH_LEN : MD5_HASH_LEN); -+ } -+ else { -+ printk("ixp: hash perform failed status=%d\n", status); -+ q->ixp_q_crp->crp_etype = EINVAL; -+ } -+ -+ /* Free internal buffer used for hashing */ -+ kfree(IX_MBUF_MDATA(&q->ixp_q_mbuf)); -+ -+ crypto_done(q->ixp_q_crp); -+ kmem_cache_free(qcache, q); -+} -+ -+/* -+ * setup a request and perform it -+ */ -+static void -+ixp_q_process(struct ixp_q *q) -+{ -+ IxCryptoAccStatus status; -+ struct ixp_data *ixp = q->ixp_q_data; -+ int auth_off = 0; -+ int auth_len = 0; -+ int crypt_off = 0; -+ int crypt_len = 0; -+ int icv_off = 0; -+ char *crypt_func; -+ -+ dprintk("%s(%p)\n", __FUNCTION__, q); -+ -+ if (q->ixp_q_ccrd) { -+ if (q->ixp_q_ccrd->crd_flags & CRD_F_IV_EXPLICIT) { -+ q->ixp_q_iv = q->ixp_q_ccrd->crd_iv; -+ } else { -+ q->ixp_q_iv = q->ixp_q_iv_data; -+ crypto_copydata(q->ixp_q_crp->crp_flags, q->ixp_q_crp->crp_buf, -+ q->ixp_q_ccrd->crd_inject, -+ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen, -+ (caddr_t) q->ixp_q_iv); -+ } -+ -+ if (q->ixp_q_acrd) { -+ auth_off = q->ixp_q_acrd->crd_skip; -+ auth_len = q->ixp_q_acrd->crd_len; -+ icv_off = q->ixp_q_acrd->crd_inject; -+ } -+ -+ crypt_off = q->ixp_q_ccrd->crd_skip; -+ crypt_len = q->ixp_q_ccrd->crd_len; -+ } else { /* if (q->ixp_q_acrd) */ -+ auth_off = q->ixp_q_acrd->crd_skip; -+ auth_len = q->ixp_q_acrd->crd_len; -+ icv_off = q->ixp_q_acrd->crd_inject; -+ } -+ -+ if (q->ixp_q_crp->crp_flags & CRYPTO_F_SKBUF) { -+ struct sk_buff *skb = (struct sk_buff *) q->ixp_q_crp->crp_buf; -+ if (skb_shinfo(skb)->nr_frags) { -+ /* -+ * DAVIDM fix this limitation one day by using -+ * a buffer pool and chaining, it is not currently -+ * needed for current user/kernel space acceleration -+ */ -+ printk("ixp: Cannot handle fragmented skb's yet !\n"); -+ q->ixp_q_crp->crp_etype = ENOENT; -+ goto done; -+ } -+ IX_MBUF_MLEN(&q->ixp_q_mbuf) = -+ IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = skb->len; -+ IX_MBUF_MDATA(&q->ixp_q_mbuf) = skb->data; -+ } else if (q->ixp_q_crp->crp_flags & CRYPTO_F_IOV) { -+ struct uio *uiop = (struct uio *) q->ixp_q_crp->crp_buf; -+ if (uiop->uio_iovcnt != 1) { -+ /* -+ * DAVIDM fix this limitation one day by using -+ * a buffer pool and chaining, it is not currently -+ * needed for current user/kernel space acceleration -+ */ -+ printk("ixp: Cannot handle more than 1 iovec yet !\n"); -+ q->ixp_q_crp->crp_etype = ENOENT; -+ goto done; -+ } -+ IX_MBUF_MLEN(&q->ixp_q_mbuf) = -+ IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = uiop->uio_iov[0].iov_len; -+ IX_MBUF_MDATA(&q->ixp_q_mbuf) = uiop->uio_iov[0].iov_base; -+ } else /* contig buffer */ { -+ IX_MBUF_MLEN(&q->ixp_q_mbuf) = -+ IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = q->ixp_q_crp->crp_ilen; -+ IX_MBUF_MDATA(&q->ixp_q_mbuf) = q->ixp_q_crp->crp_buf; -+ } -+ -+ IX_MBUF_PRIV(&q->ixp_q_mbuf) = q; -+ -+ if (ixp->ixp_auth_alg == CRYPTO_SHA1 || ixp->ixp_auth_alg == CRYPTO_MD5) { -+ /* -+ * For SHA1 and MD5 hash, need to create an internal buffer that is big -+ * enough to hold the original data + the appropriate padding for the -+ * hash algorithm. -+ */ -+ UINT8 *tbuf = NULL; -+ -+ IX_MBUF_MLEN(&q->ixp_q_mbuf) = IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = -+ ((IX_MBUF_MLEN(&q->ixp_q_mbuf) * 8) + 72 + 511) / 8; -+ tbuf = kmalloc(IX_MBUF_MLEN(&q->ixp_q_mbuf), SLAB_ATOMIC); -+ -+ if (IX_MBUF_MDATA(&q->ixp_q_mbuf) == NULL) { -+ printk("ixp: kmalloc(%u, SLAB_ATOMIC) failed\n", -+ IX_MBUF_MLEN(&q->ixp_q_mbuf)); -+ q->ixp_q_crp->crp_etype = ENOMEM; -+ goto done; -+ } -+ memcpy(tbuf, &(IX_MBUF_MDATA(&q->ixp_q_mbuf))[auth_off], auth_len); -+ -+ /* Set location in client buffer to copy hash into */ -+ q->ixp_hash_dest = -+ &(IX_MBUF_MDATA(&q->ixp_q_mbuf))[auth_off + auth_len]; -+ -+ IX_MBUF_MDATA(&q->ixp_q_mbuf) = tbuf; -+ -+ /* Set location in internal buffer for where hash starts */ -+ q->ixp_hash_src = &(IX_MBUF_MDATA(&q->ixp_q_mbuf))[auth_len]; -+ -+ crypt_func = "ixCryptoAccHashPerform"; -+ status = ixCryptoAccHashPerform(ixp->ixp_ctx.authCtx.authAlgo, -+ &q->ixp_q_mbuf, ixp_hash_perform_cb, 0, auth_len, auth_len, -+ &ixp->ixp_hash_key_id); -+ } -+ else { -+ crypt_func = "ixCryptoAccAuthCryptPerform"; -+ status = ixCryptoAccAuthCryptPerform(ixp->ixp_ctx_id, &q->ixp_q_mbuf, -+ NULL, auth_off, auth_len, crypt_off, crypt_len, icv_off, -+ q->ixp_q_iv); -+ } -+ -+ if (IX_CRYPTO_ACC_STATUS_QUEUE_FULL == status) { -+ q->ixp_q_crp->crp_etype = ENOMEM; -+ goto done; -+ } -+ -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS != status) { -+ printk("ixp: %s failed %u\n", crypt_func, status); -+ q->ixp_q_crp->crp_etype = EINVAL; -+ } -+ -+done: -+ crypto_done(q->ixp_q_crp); -+ kmem_cache_free(qcache, q); -+} -+ -+ -+/* -+ * because we cannot process the Q from the Register callback -+ * we do it here on a task Q. -+ */ -+ -+static void -+ixp_process_pending(void *arg) -+{ -+ struct ixp_data *ixp = arg; -+ struct ixp_q *q = NULL; -+ -+ dprintk("%s(%p)\n", __FUNCTION__, arg); -+ -+ if (!ixp) -+ return; -+ -+ while (!list_empty(&ixp->ixp_q)) { -+ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); -+ list_del(&q->ixp_q_list); -+ ixp_q_process(q); -+ } -+} -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void -+ixp_process_pending_wq(struct work_struct *work) -+{ -+ struct ixp_data *ixp = container_of(work, struct ixp_data, -+ ixp_pending_work); -+ ixp_process_pending(ixp); -+} -+#endif -+ -+/* -+ * callback for when context registration is complete -+ */ -+ -+static void -+ixp_register_cb(UINT32 ctx_id, IX_MBUF *bufp, IxCryptoAccStatus status) -+{ -+ int i; -+ struct ixp_data *ixp; -+ struct ixp_q *q; -+ -+ dprintk("%s(%d, %p, %d)\n", __FUNCTION__, ctx_id, bufp, status); -+ -+ /* -+ * free any buffer passed in to this routine -+ */ -+ if (bufp) { -+ IX_MBUF_MLEN(bufp) = IX_MBUF_PKT_LEN(bufp) = 0; -+ kfree(IX_MBUF_MDATA(bufp)); -+ IX_MBUF_MDATA(bufp) = NULL; -+ } -+ -+ for (i = 0; i < ixp_sesnum; i++) { -+ ixp = ixp_sessions[i]; -+ if (ixp && ixp->ixp_ctx_id == ctx_id) -+ break; -+ } -+ if (i >= ixp_sesnum) { -+ printk("ixp: invalid context id %d\n", ctx_id); -+ return; -+ } -+ -+ if (IX_CRYPTO_ACC_STATUS_WAIT == status) { -+ /* this is normal to free the first of two buffers */ -+ dprintk("ixp: register not finished yet.\n"); -+ return; -+ } -+ -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS != status) { -+ printk("ixp: register failed 0x%x\n", status); -+ while (!list_empty(&ixp->ixp_q)) { -+ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); -+ list_del(&q->ixp_q_list); -+ q->ixp_q_crp->crp_etype = EINVAL; -+ crypto_done(q->ixp_q_crp); -+ kmem_cache_free(qcache, q); -+ } -+ return; -+ } -+ -+ /* -+ * we are now registered, we cannot start processing the Q here -+ * or we get strange errors with AES (DES/3DES seem to be ok). -+ */ -+ ixp->ixp_registered = 1; -+ schedule_work(&ixp->ixp_pending_work); -+} -+ -+ -+/* -+ * callback for when data processing is complete -+ */ -+ -+static void -+ixp_perform_cb( -+ UINT32 ctx_id, -+ IX_MBUF *sbufp, -+ IX_MBUF *dbufp, -+ IxCryptoAccStatus status) -+{ -+ struct ixp_q *q; -+ -+ dprintk("%s(%d, %p, %p, 0x%x)\n", __FUNCTION__, ctx_id, sbufp, -+ dbufp, status); -+ -+ if (sbufp == NULL) { -+ printk("ixp: NULL sbuf in ixp_perform_cb\n"); -+ return; -+ } -+ -+ q = IX_MBUF_PRIV(sbufp); -+ if (q == NULL) { -+ printk("ixp: NULL priv in ixp_perform_cb\n"); -+ return; -+ } -+ -+ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { -+ printk("ixp: perform failed status=%d\n", status); -+ q->ixp_q_crp->crp_etype = EINVAL; -+ } -+ -+ crypto_done(q->ixp_q_crp); -+ kmem_cache_free(qcache, q); -+} -+ -+ -+/* -+ * registration is not callable at IRQ time, so we defer -+ * to a task queue, this routines completes the registration for us -+ * when the task queue runs -+ * -+ * Unfortunately this means we cannot tell OCF that the driver is blocked, -+ * we do that on the next request. -+ */ -+ -+static void -+ixp_registration(void *arg) -+{ -+ struct ixp_data *ixp = arg; -+ struct ixp_q *q = NULL; -+ IX_MBUF *pri = NULL, *sec = NULL; -+ int status = IX_CRYPTO_ACC_STATUS_SUCCESS; -+ -+ if (!ixp) { -+ printk("ixp: ixp_registration with no arg\n"); -+ return; -+ } -+ -+ if (ixp->ixp_ctx_id != -1) { -+ ixCryptoAccCtxUnregister(ixp->ixp_ctx_id); -+ ixp->ixp_ctx_id = -1; -+ } -+ -+ if (list_empty(&ixp->ixp_q)) { -+ printk("ixp: ixp_registration with no Q\n"); -+ return; -+ } -+ -+ /* -+ * setup the primary and secondary buffers -+ */ -+ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); -+ if (q->ixp_q_acrd) { -+ pri = &ixp->ixp_pri_mbuf; -+ sec = &ixp->ixp_sec_mbuf; -+ IX_MBUF_MLEN(pri) = IX_MBUF_PKT_LEN(pri) = 128; -+ IX_MBUF_MDATA(pri) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); -+ IX_MBUF_MLEN(sec) = IX_MBUF_PKT_LEN(sec) = 128; -+ IX_MBUF_MDATA(sec) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); -+ } -+ -+ /* Only need to register if a crypt op or HMAC op */ -+ if (!(ixp->ixp_auth_alg == CRYPTO_SHA1 || -+ ixp->ixp_auth_alg == CRYPTO_MD5)) { -+ status = ixCryptoAccCtxRegister( -+ &ixp->ixp_ctx, -+ pri, sec, -+ ixp_register_cb, -+ ixp_perform_cb, -+ &ixp->ixp_ctx_id); -+ } -+ else { -+ /* Otherwise we start processing pending q */ -+ schedule_work(&ixp->ixp_pending_work); -+ } -+ -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) -+ return; -+ -+ if (IX_CRYPTO_ACC_STATUS_EXCEED_MAX_TUNNELS == status) { -+ printk("ixp: ixCryptoAccCtxRegister failed (out of tunnels)\n"); -+ ixp_blocked = 1; -+ /* perhaps we should return EGAIN on queued ops ? */ -+ return; -+ } -+ -+ printk("ixp: ixCryptoAccCtxRegister failed %d\n", status); -+ ixp->ixp_ctx_id = -1; -+ -+ /* -+ * everything waiting is toasted -+ */ -+ while (!list_empty(&ixp->ixp_q)) { -+ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); -+ list_del(&q->ixp_q_list); -+ q->ixp_q_crp->crp_etype = ENOENT; -+ crypto_done(q->ixp_q_crp); -+ kmem_cache_free(qcache, q); -+ } -+} -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void -+ixp_registration_wq(struct work_struct *work) -+{ -+ struct ixp_data *ixp = container_of(work, struct ixp_data, -+ ixp_registration_work); -+ ixp_registration(ixp); -+} -+#endif -+ -+/* -+ * Process a request. -+ */ -+static int -+ixp_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ struct ixp_data *ixp; -+ unsigned int lid; -+ struct ixp_q *q = NULL; -+ int status; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ /* Sanity check */ -+ if (crp == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ crp->crp_etype = 0; -+ -+ if (ixp_blocked) -+ return ERESTART; -+ -+ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ /* -+ * find the session we are using -+ */ -+ -+ lid = crp->crp_sid & 0xffffffff; -+ if (lid >= ixp_sesnum || lid == 0 || ixp_sessions == NULL || -+ ixp_sessions[lid] == NULL) { -+ crp->crp_etype = ENOENT; -+ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); -+ goto done; -+ } -+ ixp = ixp_sessions[lid]; -+ -+ /* -+ * setup a new request ready for queuing -+ */ -+ q = kmem_cache_alloc(qcache, SLAB_ATOMIC); -+ if (q == NULL) { -+ dprintk("%s,%d: ENOMEM\n", __FILE__, __LINE__); -+ crp->crp_etype = ENOMEM; -+ goto done; -+ } -+ /* -+ * save some cycles by only zeroing the important bits -+ */ -+ memset(&q->ixp_q_mbuf, 0, sizeof(q->ixp_q_mbuf)); -+ q->ixp_q_ccrd = NULL; -+ q->ixp_q_acrd = NULL; -+ q->ixp_q_crp = crp; -+ q->ixp_q_data = ixp; -+ -+ /* -+ * point the cipher and auth descriptors appropriately -+ * check that we have something to do -+ */ -+ if (crp->crp_desc->crd_alg == ixp->ixp_cipher_alg) -+ q->ixp_q_ccrd = crp->crp_desc; -+ else if (crp->crp_desc->crd_alg == ixp->ixp_auth_alg) -+ q->ixp_q_acrd = crp->crp_desc; -+ else { -+ crp->crp_etype = ENOENT; -+ dprintk("%s,%d: bad desc match: ENOENT\n", __FILE__, __LINE__); -+ goto done; -+ } -+ if (crp->crp_desc->crd_next) { -+ if (crp->crp_desc->crd_next->crd_alg == ixp->ixp_cipher_alg) -+ q->ixp_q_ccrd = crp->crp_desc->crd_next; -+ else if (crp->crp_desc->crd_next->crd_alg == ixp->ixp_auth_alg) -+ q->ixp_q_acrd = crp->crp_desc->crd_next; -+ else { -+ crp->crp_etype = ENOENT; -+ dprintk("%s,%d: bad desc match: ENOENT\n", __FILE__, __LINE__); -+ goto done; -+ } -+ } -+ -+ /* -+ * If there is a direction change for this context then we mark it as -+ * unregistered and re-register is for the new direction. This is not -+ * a very expensive operation and currently only tends to happen when -+ * user-space application are doing benchmarks -+ * -+ * DM - we should be checking for pending requests before unregistering. -+ */ -+ if (q->ixp_q_ccrd && ixp->ixp_registered && -+ ixp->ixp_crd_flags != (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT)) { -+ dprintk("%s - detected direction change on session\n", __FUNCTION__); -+ ixp->ixp_registered = 0; -+ } -+ -+ /* -+ * if we are registered, call straight into the perform code -+ */ -+ if (ixp->ixp_registered) { -+ ixp_q_process(q); -+ return 0; -+ } -+ -+ /* -+ * the only part of the context not set in newsession is the direction -+ * dependent parts -+ */ -+ if (q->ixp_q_ccrd) { -+ ixp->ixp_crd_flags = (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT); -+ if (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT) { -+ ixp->ixp_ctx.operation = q->ixp_q_acrd ? -+ IX_CRYPTO_ACC_OP_ENCRYPT_AUTH : IX_CRYPTO_ACC_OP_ENCRYPT; -+ } else { -+ ixp->ixp_ctx.operation = q->ixp_q_acrd ? -+ IX_CRYPTO_ACC_OP_AUTH_DECRYPT : IX_CRYPTO_ACC_OP_DECRYPT; -+ } -+ } else { -+ /* q->ixp_q_acrd must be set if we are here */ -+ ixp->ixp_ctx.operation = IX_CRYPTO_ACC_OP_AUTH_CALC; -+ } -+ -+ status = list_empty(&ixp->ixp_q); -+ list_add_tail(&q->ixp_q_list, &ixp->ixp_q); -+ if (status) -+ schedule_work(&ixp->ixp_registration_work); -+ return 0; -+ -+done: -+ if (q) -+ kmem_cache_free(qcache, q); -+ crypto_done(crp); -+ return 0; -+} -+ -+ -+#ifdef __ixp46X -+/* -+ * key processing support for the ixp465 -+ */ -+ -+ -+/* -+ * copy a BN (LE) into a buffer (BE) an fill out the op appropriately -+ * assume zeroed and only copy bits that are significant -+ */ -+ -+static int -+ixp_copy_ibuf(struct crparam *p, IxCryptoAccPkeEauOperand *op, UINT32 *buf) -+{ -+ unsigned char *src = (unsigned char *) p->crp_p; -+ unsigned char *dst; -+ int len, bits = p->crp_nbits; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (bits > MAX_IOP_SIZE * sizeof(UINT32) * 8) { -+ dprintk("%s - ibuf too big (%d > %d)\n", __FUNCTION__, -+ bits, MAX_IOP_SIZE * sizeof(UINT32) * 8); -+ return -1; -+ } -+ -+ len = (bits + 31) / 32; /* the number UINT32's needed */ -+ -+ dst = (unsigned char *) &buf[len]; -+ dst--; -+ -+ while (bits > 0) { -+ *dst-- = *src++; -+ bits -= 8; -+ } -+ -+#if 0 /* no need to zero remaining bits as it is done during request alloc */ -+ while (dst > (unsigned char *) buf) -+ *dst-- = '\0'; -+#endif -+ -+ op->pData = buf; -+ op->dataLen = len; -+ return 0; -+} -+ -+/* -+ * copy out the result, be as forgiving as we can about small output buffers -+ */ -+ -+static int -+ixp_copy_obuf(struct crparam *p, IxCryptoAccPkeEauOpResult *op, UINT32 *buf) -+{ -+ unsigned char *dst = (unsigned char *) p->crp_p; -+ unsigned char *src = (unsigned char *) buf; -+ int len, z, bits = p->crp_nbits; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ len = op->dataLen * sizeof(UINT32); -+ -+ /* skip leading zeroes to be small buffer friendly */ -+ z = 0; -+ while (z < len && src[z] == '\0') -+ z++; -+ -+ src += len; -+ src--; -+ len -= z; -+ -+ while (len > 0 && bits > 0) { -+ *dst++ = *src--; -+ len--; -+ bits -= 8; -+ } -+ -+ while (bits > 0) { -+ *dst++ = '\0'; -+ bits -= 8; -+ } -+ -+ if (len > 0) { -+ dprintk("%s - obuf is %d (z=%d, ob=%d) bytes too small\n", -+ __FUNCTION__, len, z, p->crp_nbits / 8); -+ return -1; -+ } -+ -+ return 0; -+} -+ -+ -+/* -+ * the parameter offsets for exp_mod -+ */ -+ -+#define IXP_PARAM_BASE 0 -+#define IXP_PARAM_EXP 1 -+#define IXP_PARAM_MOD 2 -+#define IXP_PARAM_RES 3 -+ -+/* -+ * key processing complete callback, is also used to start processing -+ * by passing a NULL for pResult -+ */ -+ -+static void -+ixp_kperform_cb( -+ IxCryptoAccPkeEauOperation operation, -+ IxCryptoAccPkeEauOpResult *pResult, -+ BOOL carryOrBorrow, -+ IxCryptoAccStatus status) -+{ -+ struct ixp_pkq *q, *tmp; -+ unsigned long flags; -+ -+ dprintk("%s(0x%x, %p, %d, 0x%x)\n", __FUNCTION__, operation, pResult, -+ carryOrBorrow, status); -+ -+ /* handle a completed request */ -+ if (pResult) { -+ if (ixp_pk_cur && &ixp_pk_cur->pkq_result == pResult) { -+ q = ixp_pk_cur; -+ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { -+ dprintk("%s() - op failed 0x%x\n", __FUNCTION__, status); -+ q->pkq_krp->krp_status = ERANGE; /* could do better */ -+ } else { -+ /* copy out the result */ -+ if (ixp_copy_obuf(&q->pkq_krp->krp_param[IXP_PARAM_RES], -+ &q->pkq_result, q->pkq_obuf)) -+ q->pkq_krp->krp_status = ERANGE; -+ } -+ crypto_kdone(q->pkq_krp); -+ kfree(q); -+ ixp_pk_cur = NULL; -+ } else -+ printk("%s - callback with invalid result pointer\n", __FUNCTION__); -+ } -+ -+ spin_lock_irqsave(&ixp_pkq_lock, flags); -+ if (ixp_pk_cur || list_empty(&ixp_pkq)) { -+ spin_unlock_irqrestore(&ixp_pkq_lock, flags); -+ return; -+ } -+ -+ list_for_each_entry_safe(q, tmp, &ixp_pkq, pkq_list) { -+ -+ list_del(&q->pkq_list); -+ ixp_pk_cur = q; -+ -+ spin_unlock_irqrestore(&ixp_pkq_lock, flags); -+ -+ status = ixCryptoAccPkeEauPerform( -+ IX_CRYPTO_ACC_OP_EAU_MOD_EXP, -+ &q->pkq_op, -+ ixp_kperform_cb, -+ &q->pkq_result); -+ -+ if (status == IX_CRYPTO_ACC_STATUS_SUCCESS) { -+ dprintk("%s() - ixCryptoAccPkeEauPerform SUCCESS\n", __FUNCTION__); -+ return; /* callback will return here for callback */ -+ } else if (status == IX_CRYPTO_ACC_STATUS_RETRY) { -+ printk("%s() - ixCryptoAccPkeEauPerform RETRY\n", __FUNCTION__); -+ } else { -+ printk("%s() - ixCryptoAccPkeEauPerform failed %d\n", -+ __FUNCTION__, status); -+ } -+ q->pkq_krp->krp_status = ERANGE; /* could do better */ -+ crypto_kdone(q->pkq_krp); -+ kfree(q); -+ spin_lock_irqsave(&ixp_pkq_lock, flags); -+ } -+ spin_unlock_irqrestore(&ixp_pkq_lock, flags); -+} -+ -+ -+static int -+ixp_kprocess(device_t dev, struct cryptkop *krp, int hint) -+{ -+ struct ixp_pkq *q; -+ int rc = 0; -+ unsigned long flags; -+ -+ dprintk("%s l1=%d l2=%d l3=%d l4=%d\n", __FUNCTION__, -+ krp->krp_param[IXP_PARAM_BASE].crp_nbits, -+ krp->krp_param[IXP_PARAM_EXP].crp_nbits, -+ krp->krp_param[IXP_PARAM_MOD].crp_nbits, -+ krp->krp_param[IXP_PARAM_RES].crp_nbits); -+ -+ -+ if (krp->krp_op != CRK_MOD_EXP) { -+ krp->krp_status = EOPNOTSUPP; -+ goto err; -+ } -+ -+ q = (struct ixp_pkq *) kmalloc(sizeof(*q), GFP_KERNEL); -+ if (q == NULL) { -+ krp->krp_status = ENOMEM; -+ goto err; -+ } -+ -+ /* -+ * The PKE engine does not appear to zero the output buffer -+ * appropriately, so we need to do it all here. -+ */ -+ memset(q, 0, sizeof(*q)); -+ -+ q->pkq_krp = krp; -+ INIT_LIST_HEAD(&q->pkq_list); -+ -+ if (ixp_copy_ibuf(&krp->krp_param[IXP_PARAM_BASE], &q->pkq_op.modExpOpr.M, -+ q->pkq_ibuf0)) -+ rc = 1; -+ if (!rc && ixp_copy_ibuf(&krp->krp_param[IXP_PARAM_EXP], -+ &q->pkq_op.modExpOpr.e, q->pkq_ibuf1)) -+ rc = 2; -+ if (!rc && ixp_copy_ibuf(&krp->krp_param[IXP_PARAM_MOD], -+ &q->pkq_op.modExpOpr.N, q->pkq_ibuf2)) -+ rc = 3; -+ -+ if (rc) { -+ kfree(q); -+ krp->krp_status = ERANGE; -+ goto err; -+ } -+ -+ q->pkq_result.pData = q->pkq_obuf; -+ q->pkq_result.dataLen = -+ (krp->krp_param[IXP_PARAM_RES].crp_nbits + 31) / 32; -+ -+ spin_lock_irqsave(&ixp_pkq_lock, flags); -+ list_add_tail(&q->pkq_list, &ixp_pkq); -+ spin_unlock_irqrestore(&ixp_pkq_lock, flags); -+ -+ if (!ixp_pk_cur) -+ ixp_kperform_cb(0, NULL, 0, 0); -+ return (0); -+ -+err: -+ crypto_kdone(krp); -+ return (0); -+} -+ -+ -+ -+#ifdef CONFIG_OCF_RANDOMHARVEST -+/* -+ * We run the random number generator output through SHA so that it -+ * is FIPS compliant. -+ */ -+ -+static volatile int sha_done = 0; -+static unsigned char sha_digest[20]; -+ -+static void -+ixp_hash_cb(UINT8 *digest, IxCryptoAccStatus status) -+{ -+ dprintk("%s(%p, %d)\n", __FUNCTION__, digest, status); -+ if (sha_digest != digest) -+ printk("digest error\n"); -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) -+ sha_done = 1; -+ else -+ sha_done = -status; -+} -+ -+static int -+ixp_read_random(void *arg, u_int32_t *buf, int maxwords) -+{ -+ IxCryptoAccStatus status; -+ int i, n, rc; -+ -+ dprintk("%s(%p, %d)\n", __FUNCTION__, buf, maxwords); -+ memset(buf, 0, maxwords * sizeof(*buf)); -+ status = ixCryptoAccPkePseudoRandomNumberGet(maxwords, buf); -+ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { -+ dprintk("%s: ixCryptoAccPkePseudoRandomNumberGet failed %d\n", -+ __FUNCTION__, status); -+ return 0; -+ } -+ -+ /* -+ * run the random data through SHA to make it look more random -+ */ -+ -+ n = sizeof(sha_digest); /* process digest bytes at a time */ -+ -+ rc = 0; -+ for (i = 0; i < maxwords; i += n / sizeof(*buf)) { -+ if ((maxwords - i) * sizeof(*buf) < n) -+ n = (maxwords - i) * sizeof(*buf); -+ sha_done = 0; -+ status = ixCryptoAccPkeHashPerform(IX_CRYPTO_ACC_AUTH_SHA1, -+ (UINT8 *) &buf[i], n, ixp_hash_cb, sha_digest); -+ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { -+ dprintk("ixCryptoAccPkeHashPerform failed %d\n", status); -+ return -EIO; -+ } -+ while (!sha_done) -+ schedule(); -+ if (sha_done < 0) { -+ dprintk("ixCryptoAccPkeHashPerform failed CB %d\n", -sha_done); -+ return 0; -+ } -+ memcpy(&buf[i], sha_digest, n); -+ rc += n / sizeof(*buf);; -+ } -+ -+ return rc; -+} -+#endif /* CONFIG_OCF_RANDOMHARVEST */ -+ -+#endif /* __ixp46X */ -+ -+ -+ -+/* -+ * our driver startup and shutdown routines -+ */ -+ -+static int -+ixp_init(void) -+{ -+ dprintk("%s(%p)\n", __FUNCTION__, ixp_init); -+ -+ if (ixp_init_crypto && ixCryptoAccInit() != IX_CRYPTO_ACC_STATUS_SUCCESS) -+ printk("ixCryptoAccInit failed, assuming already initialised!\n"); -+ -+ qcache = kmem_cache_create("ixp4xx_q", sizeof(struct ixp_q), 0, -+ SLAB_HWCACHE_ALIGN, NULL -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) -+ , NULL -+#endif -+ ); -+ if (!qcache) { -+ printk("failed to create Qcache\n"); -+ return -ENOENT; -+ } -+ -+ memset(&ixpdev, 0, sizeof(ixpdev)); -+ softc_device_init(&ixpdev, "ixp4xx", 0, ixp_methods); -+ -+ ixp_id = crypto_get_driverid(softc_get_device(&ixpdev), -+ CRYPTOCAP_F_HARDWARE); -+ if (ixp_id < 0) -+ panic("IXP/OCF crypto device cannot initialize!"); -+ -+#define REGISTER(alg) \ -+ crypto_register(ixp_id,alg,0,0) -+ -+ REGISTER(CRYPTO_DES_CBC); -+ REGISTER(CRYPTO_3DES_CBC); -+ REGISTER(CRYPTO_RIJNDAEL128_CBC); -+#ifdef CONFIG_OCF_IXP4XX_SHA1_MD5 -+ REGISTER(CRYPTO_MD5); -+ REGISTER(CRYPTO_SHA1); -+#endif -+ REGISTER(CRYPTO_MD5_HMAC); -+ REGISTER(CRYPTO_SHA1_HMAC); -+#undef REGISTER -+ -+#ifdef __ixp46X -+ spin_lock_init(&ixp_pkq_lock); -+ /* -+ * we do not enable the go fast options here as they can potentially -+ * allow timing based attacks -+ * -+ * http://www.openssl.org/news/secadv_20030219.txt -+ */ -+ ixCryptoAccPkeEauExpConfig(0, 0); -+ crypto_kregister(ixp_id, CRK_MOD_EXP, 0); -+#ifdef CONFIG_OCF_RANDOMHARVEST -+ crypto_rregister(ixp_id, ixp_read_random, NULL); -+#endif -+#endif -+ -+ return 0; -+} -+ -+static void -+ixp_exit(void) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ crypto_unregister_all(ixp_id); -+ ixp_id = -1; -+ kmem_cache_destroy(qcache); -+ qcache = NULL; -+} -+ -+module_init(ixp_init); -+module_exit(ixp_exit); -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("ixp (OCF module for IXP4xx crypto)"); -diff -Nur linux-3.0.4.orig/crypto/ocf/ixp4xx/Makefile linux-3.0.4/crypto/ocf/ixp4xx/Makefile ---- linux-3.0.4.orig/crypto/ocf/ixp4xx/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/ixp4xx/Makefile 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,104 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+# -+# You will need to point this at your Intel ixp425 includes, this portion -+# of the Makefile only really works under SGLinux with the appropriate libs -+# installed. They can be downloaded from http://www.snapgear.org/ -+# -+ifeq ($(CONFIG_CPU_IXP46X),y) -+IXPLATFORM = ixp46X -+else -+ifeq ($(CONFIG_CPU_IXP43X),y) -+IXPLATFORM = ixp43X -+else -+IXPLATFORM = ixp42X -+endif -+endif -+ -+ifdef CONFIG_IXP400_LIB_2_4 -+IX_XSCALE_SW = $(ROOTDIR)/modules/ixp425/ixp400-2.4/ixp400_xscale_sw -+OSAL_DIR = $(ROOTDIR)/modules/ixp425/ixp400-2.4/ixp_osal -+endif -+ifdef CONFIG_IXP400_LIB_2_1 -+IX_XSCALE_SW = $(ROOTDIR)/modules/ixp425/ixp400-2.1/ixp400_xscale_sw -+OSAL_DIR = $(ROOTDIR)/modules/ixp425/ixp400-2.1/ixp_osal -+endif -+ifdef CONFIG_IXP400_LIB_2_0 -+IX_XSCALE_SW = $(ROOTDIR)/modules/ixp425/ixp400-2.0/ixp400_xscale_sw -+OSAL_DIR = $(ROOTDIR)/modules/ixp425/ixp400-2.0/ixp_osal -+endif -+ifdef IX_XSCALE_SW -+ifdef CONFIG_IXP400_LIB_2_4 -+IXP_CFLAGS = \ -+ -I$(ROOTDIR)/. \ -+ -I$(IX_XSCALE_SW)/src/include \ -+ -I$(OSAL_DIR)/common/include/ \ -+ -I$(OSAL_DIR)/common/include/modules/ \ -+ -I$(OSAL_DIR)/common/include/modules/ddk/ \ -+ -I$(OSAL_DIR)/common/include/modules/bufferMgt/ \ -+ -I$(OSAL_DIR)/common/include/modules/ioMem/ \ -+ -I$(OSAL_DIR)/common/os/linux/include/ \ -+ -I$(OSAL_DIR)/common/os/linux/include/core/ \ -+ -I$(OSAL_DIR)/common/os/linux/include/modules/ \ -+ -I$(OSAL_DIR)/common/os/linux/include/modules/ddk/ \ -+ -I$(OSAL_DIR)/common/os/linux/include/modules/bufferMgt/ \ -+ -I$(OSAL_DIR)/common/os/linux/include/modules/ioMem/ \ -+ -I$(OSAL_DIR)/platforms/$(IXPLATFORM)/include/ \ -+ -I$(OSAL_DIR)/platforms/$(IXPLATFORM)/os/linux/include/ \ -+ -DENABLE_IOMEM -DENABLE_BUFFERMGT -DENABLE_DDK \ -+ -DUSE_IXP4XX_CRYPTO -+else -+IXP_CFLAGS = \ -+ -I$(ROOTDIR)/. \ -+ -I$(IX_XSCALE_SW)/src/include \ -+ -I$(OSAL_DIR)/ \ -+ -I$(OSAL_DIR)/os/linux/include/ \ -+ -I$(OSAL_DIR)/os/linux/include/modules/ \ -+ -I$(OSAL_DIR)/os/linux/include/modules/ioMem/ \ -+ -I$(OSAL_DIR)/os/linux/include/modules/bufferMgt/ \ -+ -I$(OSAL_DIR)/os/linux/include/core/ \ -+ -I$(OSAL_DIR)/os/linux/include/platforms/ \ -+ -I$(OSAL_DIR)/os/linux/include/platforms/ixp400/ \ -+ -I$(OSAL_DIR)/os/linux/include/platforms/ixp400/ixp425 \ -+ -I$(OSAL_DIR)/os/linux/include/platforms/ixp400/ixp465 \ -+ -I$(OSAL_DIR)/os/linux/include/core/ \ -+ -I$(OSAL_DIR)/include/ \ -+ -I$(OSAL_DIR)/include/modules/ \ -+ -I$(OSAL_DIR)/include/modules/bufferMgt/ \ -+ -I$(OSAL_DIR)/include/modules/ioMem/ \ -+ -I$(OSAL_DIR)/include/platforms/ \ -+ -I$(OSAL_DIR)/include/platforms/ixp400/ \ -+ -DUSE_IXP4XX_CRYPTO -+endif -+endif -+ifdef CONFIG_IXP400_LIB_1_4 -+IXP_CFLAGS = \ -+ -I$(ROOTDIR)/. \ -+ -I$(ROOTDIR)/modules/ixp425/ixp400-1.4/ixp400_xscale_sw/src/include \ -+ -I$(ROOTDIR)/modules/ixp425/ixp400-1.4/ixp400_xscale_sw/src/linux \ -+ -DUSE_IXP4XX_CRYPTO -+endif -+ifndef IXPDIR -+IXPDIR = ixp-version-is-not-supported -+endif -+ -+ifeq ($(CONFIG_CPU_IXP46X),y) -+IXP_CFLAGS += -D__ixp46X -+else -+ifeq ($(CONFIG_CPU_IXP43X),y) -+IXP_CFLAGS += -D__ixp43X -+else -+IXP_CFLAGS += -D__ixp42X -+endif -+endif -+ -+obj-$(CONFIG_OCF_IXP4XX) += ixp4xx.o -+ -+obj ?= . -+EXTRA_CFLAGS += $(IXP_CFLAGS) -I$(obj)/.. -I$(obj)/. -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/ixp4xx/ixp4xx.c linux-3.0.4/crypto/ocf/ixp4xx/ixp4xx.c ---- linux-3.0.4.orig/crypto/ocf/ixp4xx/ixp4xx.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/ixp4xx/ixp4xx.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,1339 @@ -+/* -+ * An OCF module that uses Intels IXP CryptACC API to do the crypto. -+ * This driver requires the IXP400 Access Library that is available -+ * from Intel in order to operate (or compile). -+ * -+ * Written by David McCullough -+ * Copyright (C) 2006-2011 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * ALTERNATIVELY, provided that this notice is retained in full, this product -+ * may be distributed under the terms of the GNU General Public License (GPL), -+ * in which case the provisions of the GPL apply INSTEAD OF those given above. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ */ -+ -+#include -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#ifndef IX_MBUF_PRIV -+#define IX_MBUF_PRIV(x) ((x)->priv) -+#endif -+ -+struct ixp_data; -+ -+struct ixp_q { -+ struct list_head ixp_q_list; -+ struct ixp_data *ixp_q_data; -+ struct cryptop *ixp_q_crp; -+ struct cryptodesc *ixp_q_ccrd; -+ struct cryptodesc *ixp_q_acrd; -+ IX_MBUF ixp_q_mbuf; -+ UINT8 *ixp_hash_dest; /* Location for hash in client buffer */ -+ UINT8 *ixp_hash_src; /* Location of hash in internal buffer */ -+ unsigned char ixp_q_iv_data[IX_CRYPTO_ACC_MAX_CIPHER_IV_LENGTH]; -+ unsigned char *ixp_q_iv; -+}; -+ -+struct ixp_data { -+ int ixp_registered; /* is the context registered */ -+ int ixp_crd_flags; /* detect direction changes */ -+ -+ int ixp_cipher_alg; -+ int ixp_auth_alg; -+ -+ UINT32 ixp_ctx_id; -+ UINT32 ixp_hash_key_id; /* used when hashing */ -+ IxCryptoAccCtx ixp_ctx; -+ IX_MBUF ixp_pri_mbuf; -+ IX_MBUF ixp_sec_mbuf; -+ -+ struct work_struct ixp_pending_work; -+ struct work_struct ixp_registration_work; -+ struct list_head ixp_q; /* unprocessed requests */ -+}; -+ -+#ifdef __ixp46X -+ -+#define MAX_IOP_SIZE 64 /* words */ -+#define MAX_OOP_SIZE 128 -+ -+#define MAX_PARAMS 3 -+ -+struct ixp_pkq { -+ struct list_head pkq_list; -+ struct cryptkop *pkq_krp; -+ -+ IxCryptoAccPkeEauInOperands pkq_op; -+ IxCryptoAccPkeEauOpResult pkq_result; -+ -+ UINT32 pkq_ibuf0[MAX_IOP_SIZE]; -+ UINT32 pkq_ibuf1[MAX_IOP_SIZE]; -+ UINT32 pkq_ibuf2[MAX_IOP_SIZE]; -+ UINT32 pkq_obuf[MAX_OOP_SIZE]; -+}; -+ -+static LIST_HEAD(ixp_pkq); /* current PK wait list */ -+static struct ixp_pkq *ixp_pk_cur; -+static spinlock_t ixp_pkq_lock; -+ -+#endif /* __ixp46X */ -+ -+static int ixp_blocked = 0; -+ -+static int32_t ixp_id = -1; -+static struct ixp_data **ixp_sessions = NULL; -+static u_int32_t ixp_sesnum = 0; -+ -+static int ixp_process(device_t, struct cryptop *, int); -+static int ixp_newsession(device_t, u_int32_t *, struct cryptoini *); -+static int ixp_freesession(device_t, u_int64_t); -+#ifdef __ixp46X -+static int ixp_kprocess(device_t, struct cryptkop *krp, int hint); -+#endif -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) -+static kmem_cache_t *qcache; -+#else -+static struct kmem_cache *qcache; -+#endif -+ -+#define debug ixp_debug -+static int ixp_debug = 0; -+module_param(ixp_debug, int, 0644); -+MODULE_PARM_DESC(ixp_debug, "Enable debug"); -+ -+static int ixp_init_crypto = 1; -+module_param(ixp_init_crypto, int, 0444); /* RO after load/boot */ -+MODULE_PARM_DESC(ixp_init_crypto, "Call ixCryptoAccInit (default is 1)"); -+ -+static void ixp_process_pending(void *arg); -+static void ixp_registration(void *arg); -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void ixp_process_pending_wq(struct work_struct *work); -+static void ixp_registration_wq(struct work_struct *work); -+#endif -+ -+/* -+ * dummy device structure -+ */ -+ -+static struct { -+ softc_device_decl sc_dev; -+} ixpdev; -+ -+static device_method_t ixp_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, ixp_newsession), -+ DEVMETHOD(cryptodev_freesession,ixp_freesession), -+ DEVMETHOD(cryptodev_process, ixp_process), -+#ifdef __ixp46X -+ DEVMETHOD(cryptodev_kprocess, ixp_kprocess), -+#endif -+}; -+ -+/* -+ * Generate a new software session. -+ */ -+static int -+ixp_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) -+{ -+ struct ixp_data *ixp; -+ u_int32_t i; -+#define AUTH_LEN(cri, def) \ -+ (cri->cri_mlen ? cri->cri_mlen : (def)) -+ -+ dprintk("%s():alg %d\n", __FUNCTION__,cri->cri_alg); -+ if (sid == NULL || cri == NULL) { -+ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ if (ixp_sessions) { -+ for (i = 1; i < ixp_sesnum; i++) -+ if (ixp_sessions[i] == NULL) -+ break; -+ } else -+ i = 1; /* NB: to silence compiler warning */ -+ -+ if (ixp_sessions == NULL || i == ixp_sesnum) { -+ struct ixp_data **ixpd; -+ -+ if (ixp_sessions == NULL) { -+ i = 1; /* We leave ixp_sessions[0] empty */ -+ ixp_sesnum = CRYPTO_SW_SESSIONS; -+ } else -+ ixp_sesnum *= 2; -+ -+ ixpd = kmalloc(ixp_sesnum * sizeof(struct ixp_data *), SLAB_ATOMIC); -+ if (ixpd == NULL) { -+ /* Reset session number */ -+ if (ixp_sesnum == CRYPTO_SW_SESSIONS) -+ ixp_sesnum = 0; -+ else -+ ixp_sesnum /= 2; -+ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ memset(ixpd, 0, ixp_sesnum * sizeof(struct ixp_data *)); -+ -+ /* Copy existing sessions */ -+ if (ixp_sessions) { -+ memcpy(ixpd, ixp_sessions, -+ (ixp_sesnum / 2) * sizeof(struct ixp_data *)); -+ kfree(ixp_sessions); -+ } -+ -+ ixp_sessions = ixpd; -+ } -+ -+ ixp_sessions[i] = (struct ixp_data *) kmalloc(sizeof(struct ixp_data), -+ SLAB_ATOMIC); -+ if (ixp_sessions[i] == NULL) { -+ ixp_freesession(NULL, i); -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ -+ *sid = i; -+ -+ ixp = ixp_sessions[i]; -+ memset(ixp, 0, sizeof(*ixp)); -+ -+ ixp->ixp_cipher_alg = -1; -+ ixp->ixp_auth_alg = -1; -+ ixp->ixp_ctx_id = -1; -+ INIT_LIST_HEAD(&ixp->ixp_q); -+ -+ ixp->ixp_ctx.useDifferentSrcAndDestMbufs = 0; -+ -+ while (cri) { -+ switch (cri->cri_alg) { -+ case CRYPTO_DES_CBC: -+ ixp->ixp_cipher_alg = cri->cri_alg; -+ ixp->ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_DES; -+ ixp->ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; -+ ixp->ixp_ctx.cipherCtx.cipherKeyLen = (cri->cri_klen + 7) / 8; -+ ixp->ixp_ctx.cipherCtx.cipherBlockLen = IX_CRYPTO_ACC_DES_BLOCK_64; -+ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen = -+ IX_CRYPTO_ACC_DES_IV_64; -+ memcpy(ixp->ixp_ctx.cipherCtx.key.cipherKey, -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ break; -+ -+ case CRYPTO_3DES_CBC: -+ ixp->ixp_cipher_alg = cri->cri_alg; -+ ixp->ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_3DES; -+ ixp->ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; -+ ixp->ixp_ctx.cipherCtx.cipherKeyLen = (cri->cri_klen + 7) / 8; -+ ixp->ixp_ctx.cipherCtx.cipherBlockLen = IX_CRYPTO_ACC_DES_BLOCK_64; -+ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen = -+ IX_CRYPTO_ACC_DES_IV_64; -+ memcpy(ixp->ixp_ctx.cipherCtx.key.cipherKey, -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ break; -+ -+ case CRYPTO_RIJNDAEL128_CBC: -+ ixp->ixp_cipher_alg = cri->cri_alg; -+ ixp->ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_AES; -+ ixp->ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; -+ ixp->ixp_ctx.cipherCtx.cipherKeyLen = (cri->cri_klen + 7) / 8; -+ ixp->ixp_ctx.cipherCtx.cipherBlockLen = 16; -+ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen = 16; -+ memcpy(ixp->ixp_ctx.cipherCtx.key.cipherKey, -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ break; -+ -+ case CRYPTO_MD5: -+ case CRYPTO_MD5_HMAC: -+ ixp->ixp_auth_alg = cri->cri_alg; -+ ixp->ixp_ctx.authCtx.authAlgo = IX_CRYPTO_ACC_AUTH_MD5; -+ ixp->ixp_ctx.authCtx.authDigestLen = AUTH_LEN(cri, MD5_HASH_LEN); -+ ixp->ixp_ctx.authCtx.aadLen = 0; -+ /* Only MD5_HMAC needs a key */ -+ if (cri->cri_alg == CRYPTO_MD5_HMAC) { -+ ixp->ixp_ctx.authCtx.authKeyLen = (cri->cri_klen + 7) / 8; -+ if (ixp->ixp_ctx.authCtx.authKeyLen > -+ sizeof(ixp->ixp_ctx.authCtx.key.authKey)) { -+ printk( -+ "ixp4xx: Invalid key length for MD5_HMAC - %d bits\n", -+ cri->cri_klen); -+ ixp_freesession(NULL, i); -+ return EINVAL; -+ } -+ memcpy(ixp->ixp_ctx.authCtx.key.authKey, -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ } -+ break; -+ -+ case CRYPTO_SHA1: -+ case CRYPTO_SHA1_HMAC: -+ ixp->ixp_auth_alg = cri->cri_alg; -+ ixp->ixp_ctx.authCtx.authAlgo = IX_CRYPTO_ACC_AUTH_SHA1; -+ ixp->ixp_ctx.authCtx.authDigestLen = AUTH_LEN(cri, SHA1_HASH_LEN); -+ ixp->ixp_ctx.authCtx.aadLen = 0; -+ /* Only SHA1_HMAC needs a key */ -+ if (cri->cri_alg == CRYPTO_SHA1_HMAC) { -+ ixp->ixp_ctx.authCtx.authKeyLen = (cri->cri_klen + 7) / 8; -+ if (ixp->ixp_ctx.authCtx.authKeyLen > -+ sizeof(ixp->ixp_ctx.authCtx.key.authKey)) { -+ printk( -+ "ixp4xx: Invalid key length for SHA1_HMAC - %d bits\n", -+ cri->cri_klen); -+ ixp_freesession(NULL, i); -+ return EINVAL; -+ } -+ memcpy(ixp->ixp_ctx.authCtx.key.authKey, -+ cri->cri_key, (cri->cri_klen + 7) / 8); -+ } -+ break; -+ -+ default: -+ printk("ixp: unknown algo 0x%x\n", cri->cri_alg); -+ ixp_freesession(NULL, i); -+ return EINVAL; -+ } -+ cri = cri->cri_next; -+ } -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ INIT_WORK(&ixp->ixp_pending_work, ixp_process_pending_wq); -+ INIT_WORK(&ixp->ixp_registration_work, ixp_registration_wq); -+#else -+ INIT_WORK(&ixp->ixp_pending_work, ixp_process_pending, ixp); -+ INIT_WORK(&ixp->ixp_registration_work, ixp_registration, ixp); -+#endif -+ -+ return 0; -+} -+ -+ -+/* -+ * Free a session. -+ */ -+static int -+ixp_freesession(device_t dev, u_int64_t tid) -+{ -+ u_int32_t sid = CRYPTO_SESID2LID(tid); -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid > ixp_sesnum || ixp_sessions == NULL || -+ ixp_sessions[sid] == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ /* Silently accept and return */ -+ if (sid == 0) -+ return 0; -+ -+ if (ixp_sessions[sid]) { -+ if (ixp_sessions[sid]->ixp_ctx_id != -1) { -+ ixCryptoAccCtxUnregister(ixp_sessions[sid]->ixp_ctx_id); -+ ixp_sessions[sid]->ixp_ctx_id = -1; -+ } -+ kfree(ixp_sessions[sid]); -+ } -+ ixp_sessions[sid] = NULL; -+ if (ixp_blocked) { -+ ixp_blocked = 0; -+ crypto_unblock(ixp_id, CRYPTO_SYMQ); -+ } -+ return 0; -+} -+ -+ -+/* -+ * callback for when hash processing is complete -+ */ -+ -+static void -+ixp_hash_perform_cb( -+ UINT32 hash_key_id, -+ IX_MBUF *bufp, -+ IxCryptoAccStatus status) -+{ -+ struct ixp_q *q; -+ -+ dprintk("%s(%u, %p, 0x%x)\n", __FUNCTION__, hash_key_id, bufp, status); -+ -+ if (bufp == NULL) { -+ printk("ixp: NULL buf in %s\n", __FUNCTION__); -+ return; -+ } -+ -+ q = IX_MBUF_PRIV(bufp); -+ if (q == NULL) { -+ printk("ixp: NULL priv in %s\n", __FUNCTION__); -+ return; -+ } -+ -+ if (status == IX_CRYPTO_ACC_STATUS_SUCCESS) { -+ /* On success, need to copy hash back into original client buffer */ -+ memcpy(q->ixp_hash_dest, q->ixp_hash_src, -+ (q->ixp_q_data->ixp_auth_alg == CRYPTO_SHA1) ? -+ SHA1_HASH_LEN : MD5_HASH_LEN); -+ } -+ else { -+ printk("ixp: hash perform failed status=%d\n", status); -+ q->ixp_q_crp->crp_etype = EINVAL; -+ } -+ -+ /* Free internal buffer used for hashing */ -+ kfree(IX_MBUF_MDATA(&q->ixp_q_mbuf)); -+ -+ crypto_done(q->ixp_q_crp); -+ kmem_cache_free(qcache, q); -+} -+ -+/* -+ * setup a request and perform it -+ */ -+static void -+ixp_q_process(struct ixp_q *q) -+{ -+ IxCryptoAccStatus status; -+ struct ixp_data *ixp = q->ixp_q_data; -+ int auth_off = 0; -+ int auth_len = 0; -+ int crypt_off = 0; -+ int crypt_len = 0; -+ int icv_off = 0; -+ char *crypt_func; -+ -+ dprintk("%s(%p)\n", __FUNCTION__, q); -+ -+ if (q->ixp_q_ccrd) { -+ if (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT) { -+ if (q->ixp_q_ccrd->crd_flags & CRD_F_IV_EXPLICIT) { -+ q->ixp_q_iv = q->ixp_q_ccrd->crd_iv; -+ } else { -+ q->ixp_q_iv = q->ixp_q_iv_data; -+ read_random(q->ixp_q_iv, ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen); -+ } -+ if ((q->ixp_q_ccrd->crd_flags & CRD_F_IV_PRESENT) == 0) -+ crypto_copyback(q->ixp_q_crp->crp_flags, q->ixp_q_crp->crp_buf, -+ q->ixp_q_ccrd->crd_inject, -+ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen, -+ (caddr_t) q->ixp_q_iv); -+ } else { -+ if (q->ixp_q_ccrd->crd_flags & CRD_F_IV_EXPLICIT) -+ q->ixp_q_iv = q->ixp_q_ccrd->crd_iv; -+ else { -+ q->ixp_q_iv = q->ixp_q_iv_data; -+ crypto_copydata(q->ixp_q_crp->crp_flags, q->ixp_q_crp->crp_buf, -+ q->ixp_q_ccrd->crd_inject, -+ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen, -+ (caddr_t) q->ixp_q_iv); -+ } -+ } -+ -+ if (q->ixp_q_acrd) { -+ auth_off = q->ixp_q_acrd->crd_skip; -+ auth_len = q->ixp_q_acrd->crd_len; -+ icv_off = q->ixp_q_acrd->crd_inject; -+ } -+ -+ crypt_off = q->ixp_q_ccrd->crd_skip; -+ crypt_len = q->ixp_q_ccrd->crd_len; -+ } else { /* if (q->ixp_q_acrd) */ -+ auth_off = q->ixp_q_acrd->crd_skip; -+ auth_len = q->ixp_q_acrd->crd_len; -+ icv_off = q->ixp_q_acrd->crd_inject; -+ } -+ -+ if (q->ixp_q_crp->crp_flags & CRYPTO_F_SKBUF) { -+ struct sk_buff *skb = (struct sk_buff *) q->ixp_q_crp->crp_buf; -+ if (skb_shinfo(skb)->nr_frags) { -+ /* -+ * DAVIDM fix this limitation one day by using -+ * a buffer pool and chaining, it is not currently -+ * needed for current user/kernel space acceleration -+ */ -+ printk("ixp: Cannot handle fragmented skb's yet !\n"); -+ q->ixp_q_crp->crp_etype = ENOENT; -+ goto done; -+ } -+ IX_MBUF_MLEN(&q->ixp_q_mbuf) = -+ IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = skb->len; -+ IX_MBUF_MDATA(&q->ixp_q_mbuf) = skb->data; -+ } else if (q->ixp_q_crp->crp_flags & CRYPTO_F_IOV) { -+ struct uio *uiop = (struct uio *) q->ixp_q_crp->crp_buf; -+ if (uiop->uio_iovcnt != 1) { -+ /* -+ * DAVIDM fix this limitation one day by using -+ * a buffer pool and chaining, it is not currently -+ * needed for current user/kernel space acceleration -+ */ -+ printk("ixp: Cannot handle more than 1 iovec yet !\n"); -+ q->ixp_q_crp->crp_etype = ENOENT; -+ goto done; -+ } -+ IX_MBUF_MLEN(&q->ixp_q_mbuf) = -+ IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = uiop->uio_iov[0].iov_len; -+ IX_MBUF_MDATA(&q->ixp_q_mbuf) = uiop->uio_iov[0].iov_base; -+ } else /* contig buffer */ { -+ IX_MBUF_MLEN(&q->ixp_q_mbuf) = -+ IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = q->ixp_q_crp->crp_ilen; -+ IX_MBUF_MDATA(&q->ixp_q_mbuf) = q->ixp_q_crp->crp_buf; -+ } -+ -+ IX_MBUF_PRIV(&q->ixp_q_mbuf) = q; -+ -+ if (ixp->ixp_auth_alg == CRYPTO_SHA1 || ixp->ixp_auth_alg == CRYPTO_MD5) { -+ /* -+ * For SHA1 and MD5 hash, need to create an internal buffer that is big -+ * enough to hold the original data + the appropriate padding for the -+ * hash algorithm. -+ */ -+ UINT8 *tbuf = NULL; -+ -+ IX_MBUF_MLEN(&q->ixp_q_mbuf) = IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = -+ ((IX_MBUF_MLEN(&q->ixp_q_mbuf) * 8) + 72 + 511) / 8; -+ tbuf = kmalloc(IX_MBUF_MLEN(&q->ixp_q_mbuf), SLAB_ATOMIC); -+ -+ if (IX_MBUF_MDATA(&q->ixp_q_mbuf) == NULL) { -+ printk("ixp: kmalloc(%u, SLAB_ATOMIC) failed\n", -+ IX_MBUF_MLEN(&q->ixp_q_mbuf)); -+ q->ixp_q_crp->crp_etype = ENOMEM; -+ goto done; -+ } -+ memcpy(tbuf, &(IX_MBUF_MDATA(&q->ixp_q_mbuf))[auth_off], auth_len); -+ -+ /* Set location in client buffer to copy hash into */ -+ q->ixp_hash_dest = -+ &(IX_MBUF_MDATA(&q->ixp_q_mbuf))[auth_off + auth_len]; -+ -+ IX_MBUF_MDATA(&q->ixp_q_mbuf) = tbuf; -+ -+ /* Set location in internal buffer for where hash starts */ -+ q->ixp_hash_src = &(IX_MBUF_MDATA(&q->ixp_q_mbuf))[auth_len]; -+ -+ crypt_func = "ixCryptoAccHashPerform"; -+ status = ixCryptoAccHashPerform(ixp->ixp_ctx.authCtx.authAlgo, -+ &q->ixp_q_mbuf, ixp_hash_perform_cb, 0, auth_len, auth_len, -+ &ixp->ixp_hash_key_id); -+ } -+ else { -+ crypt_func = "ixCryptoAccAuthCryptPerform"; -+ status = ixCryptoAccAuthCryptPerform(ixp->ixp_ctx_id, &q->ixp_q_mbuf, -+ NULL, auth_off, auth_len, crypt_off, crypt_len, icv_off, -+ q->ixp_q_iv); -+ } -+ -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) -+ return; -+ -+ if (IX_CRYPTO_ACC_STATUS_QUEUE_FULL == status) { -+ q->ixp_q_crp->crp_etype = ENOMEM; -+ goto done; -+ } -+ -+ printk("ixp: %s failed %u\n", crypt_func, status); -+ q->ixp_q_crp->crp_etype = EINVAL; -+ -+done: -+ crypto_done(q->ixp_q_crp); -+ kmem_cache_free(qcache, q); -+} -+ -+ -+/* -+ * because we cannot process the Q from the Register callback -+ * we do it here on a task Q. -+ */ -+ -+static void -+ixp_process_pending(void *arg) -+{ -+ struct ixp_data *ixp = arg; -+ struct ixp_q *q = NULL; -+ -+ dprintk("%s(%p)\n", __FUNCTION__, arg); -+ -+ if (!ixp) -+ return; -+ -+ while (!list_empty(&ixp->ixp_q)) { -+ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); -+ list_del(&q->ixp_q_list); -+ ixp_q_process(q); -+ } -+} -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void -+ixp_process_pending_wq(struct work_struct *work) -+{ -+ struct ixp_data *ixp = container_of(work, struct ixp_data, ixp_pending_work); -+ ixp_process_pending(ixp); -+} -+#endif -+ -+/* -+ * callback for when context registration is complete -+ */ -+ -+static void -+ixp_register_cb(UINT32 ctx_id, IX_MBUF *bufp, IxCryptoAccStatus status) -+{ -+ int i; -+ struct ixp_data *ixp; -+ struct ixp_q *q; -+ -+ dprintk("%s(%d, %p, %d)\n", __FUNCTION__, ctx_id, bufp, status); -+ -+ /* -+ * free any buffer passed in to this routine -+ */ -+ if (bufp) { -+ IX_MBUF_MLEN(bufp) = IX_MBUF_PKT_LEN(bufp) = 0; -+ kfree(IX_MBUF_MDATA(bufp)); -+ IX_MBUF_MDATA(bufp) = NULL; -+ } -+ -+ for (i = 0; i < ixp_sesnum; i++) { -+ ixp = ixp_sessions[i]; -+ if (ixp && ixp->ixp_ctx_id == ctx_id) -+ break; -+ } -+ if (i >= ixp_sesnum) { -+ printk("ixp: invalid context id %d\n", ctx_id); -+ return; -+ } -+ -+ if (IX_CRYPTO_ACC_STATUS_WAIT == status) { -+ /* this is normal to free the first of two buffers */ -+ dprintk("ixp: register not finished yet.\n"); -+ return; -+ } -+ -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS != status) { -+ printk("ixp: register failed 0x%x\n", status); -+ while (!list_empty(&ixp->ixp_q)) { -+ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); -+ list_del(&q->ixp_q_list); -+ q->ixp_q_crp->crp_etype = EINVAL; -+ crypto_done(q->ixp_q_crp); -+ kmem_cache_free(qcache, q); -+ } -+ return; -+ } -+ -+ /* -+ * we are now registered, we cannot start processing the Q here -+ * or we get strange errors with AES (DES/3DES seem to be ok). -+ */ -+ ixp->ixp_registered = 1; -+ schedule_work(&ixp->ixp_pending_work); -+} -+ -+ -+/* -+ * callback for when data processing is complete -+ */ -+ -+static void -+ixp_perform_cb( -+ UINT32 ctx_id, -+ IX_MBUF *sbufp, -+ IX_MBUF *dbufp, -+ IxCryptoAccStatus status) -+{ -+ struct ixp_q *q; -+ -+ dprintk("%s(%d, %p, %p, 0x%x)\n", __FUNCTION__, ctx_id, sbufp, -+ dbufp, status); -+ -+ if (sbufp == NULL) { -+ printk("ixp: NULL sbuf in ixp_perform_cb\n"); -+ return; -+ } -+ -+ q = IX_MBUF_PRIV(sbufp); -+ if (q == NULL) { -+ printk("ixp: NULL priv in ixp_perform_cb\n"); -+ return; -+ } -+ -+ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { -+ printk("ixp: perform failed status=%d\n", status); -+ q->ixp_q_crp->crp_etype = EINVAL; -+ } -+ -+ crypto_done(q->ixp_q_crp); -+ kmem_cache_free(qcache, q); -+} -+ -+ -+/* -+ * registration is not callable at IRQ time, so we defer -+ * to a task queue, this routines completes the registration for us -+ * when the task queue runs -+ * -+ * Unfortunately this means we cannot tell OCF that the driver is blocked, -+ * we do that on the next request. -+ */ -+ -+static void -+ixp_registration(void *arg) -+{ -+ struct ixp_data *ixp = arg; -+ struct ixp_q *q = NULL; -+ IX_MBUF *pri = NULL, *sec = NULL; -+ int status = IX_CRYPTO_ACC_STATUS_SUCCESS; -+ -+ if (!ixp) { -+ printk("ixp: ixp_registration with no arg\n"); -+ return; -+ } -+ -+ if (ixp->ixp_ctx_id != -1) { -+ ixCryptoAccCtxUnregister(ixp->ixp_ctx_id); -+ ixp->ixp_ctx_id = -1; -+ } -+ -+ if (list_empty(&ixp->ixp_q)) { -+ printk("ixp: ixp_registration with no Q\n"); -+ return; -+ } -+ -+ /* -+ * setup the primary and secondary buffers -+ */ -+ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); -+ if (q->ixp_q_acrd) { -+ pri = &ixp->ixp_pri_mbuf; -+ sec = &ixp->ixp_sec_mbuf; -+ IX_MBUF_MLEN(pri) = IX_MBUF_PKT_LEN(pri) = 128; -+ IX_MBUF_MDATA(pri) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); -+ IX_MBUF_MLEN(sec) = IX_MBUF_PKT_LEN(sec) = 128; -+ IX_MBUF_MDATA(sec) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); -+ } -+ -+ /* Only need to register if a crypt op or HMAC op */ -+ if (!(ixp->ixp_auth_alg == CRYPTO_SHA1 || -+ ixp->ixp_auth_alg == CRYPTO_MD5)) { -+ status = ixCryptoAccCtxRegister( -+ &ixp->ixp_ctx, -+ pri, sec, -+ ixp_register_cb, -+ ixp_perform_cb, -+ &ixp->ixp_ctx_id); -+ } -+ else { -+ /* Otherwise we start processing pending q */ -+ schedule_work(&ixp->ixp_pending_work); -+ } -+ -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) -+ return; -+ -+ if (IX_CRYPTO_ACC_STATUS_EXCEED_MAX_TUNNELS == status) { -+ printk("ixp: ixCryptoAccCtxRegister failed (out of tunnels)\n"); -+ ixp_blocked = 1; -+ /* perhaps we should return EGAIN on queued ops ? */ -+ return; -+ } -+ -+ printk("ixp: ixCryptoAccCtxRegister failed %d\n", status); -+ ixp->ixp_ctx_id = -1; -+ -+ /* -+ * everything waiting is toasted -+ */ -+ while (!list_empty(&ixp->ixp_q)) { -+ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); -+ list_del(&q->ixp_q_list); -+ q->ixp_q_crp->crp_etype = ENOENT; -+ crypto_done(q->ixp_q_crp); -+ kmem_cache_free(qcache, q); -+ } -+} -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void -+ixp_registration_wq(struct work_struct *work) -+{ -+ struct ixp_data *ixp = container_of(work, struct ixp_data, -+ ixp_registration_work); -+ ixp_registration(ixp); -+} -+#endif -+ -+/* -+ * Process a request. -+ */ -+static int -+ixp_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ struct ixp_data *ixp; -+ unsigned int lid; -+ struct ixp_q *q = NULL; -+ int status; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ /* Sanity check */ -+ if (crp == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ crp->crp_etype = 0; -+ -+ if (ixp_blocked) -+ return ERESTART; -+ -+ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ /* -+ * find the session we are using -+ */ -+ -+ lid = crp->crp_sid & 0xffffffff; -+ if (lid >= ixp_sesnum || lid == 0 || ixp_sessions == NULL || -+ ixp_sessions[lid] == NULL) { -+ crp->crp_etype = ENOENT; -+ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); -+ goto done; -+ } -+ ixp = ixp_sessions[lid]; -+ -+ /* -+ * setup a new request ready for queuing -+ */ -+ q = kmem_cache_alloc(qcache, SLAB_ATOMIC); -+ if (q == NULL) { -+ dprintk("%s,%d: ENOMEM\n", __FILE__, __LINE__); -+ crp->crp_etype = ENOMEM; -+ goto done; -+ } -+ /* -+ * save some cycles by only zeroing the important bits -+ */ -+ memset(&q->ixp_q_mbuf, 0, sizeof(q->ixp_q_mbuf)); -+ q->ixp_q_ccrd = NULL; -+ q->ixp_q_acrd = NULL; -+ q->ixp_q_crp = crp; -+ q->ixp_q_data = ixp; -+ -+ /* -+ * point the cipher and auth descriptors appropriately -+ * check that we have something to do -+ */ -+ if (crp->crp_desc->crd_alg == ixp->ixp_cipher_alg) -+ q->ixp_q_ccrd = crp->crp_desc; -+ else if (crp->crp_desc->crd_alg == ixp->ixp_auth_alg) -+ q->ixp_q_acrd = crp->crp_desc; -+ else { -+ crp->crp_etype = ENOENT; -+ dprintk("%s,%d: bad desc match: ENOENT\n", __FILE__, __LINE__); -+ goto done; -+ } -+ if (crp->crp_desc->crd_next) { -+ if (crp->crp_desc->crd_next->crd_alg == ixp->ixp_cipher_alg) -+ q->ixp_q_ccrd = crp->crp_desc->crd_next; -+ else if (crp->crp_desc->crd_next->crd_alg == ixp->ixp_auth_alg) -+ q->ixp_q_acrd = crp->crp_desc->crd_next; -+ else { -+ crp->crp_etype = ENOENT; -+ dprintk("%s,%d: bad desc match: ENOENT\n", __FILE__, __LINE__); -+ goto done; -+ } -+ } -+ -+ /* -+ * If there is a direction change for this context then we mark it as -+ * unregistered and re-register is for the new direction. This is not -+ * a very expensive operation and currently only tends to happen when -+ * user-space application are doing benchmarks -+ * -+ * DM - we should be checking for pending requests before unregistering. -+ */ -+ if (q->ixp_q_ccrd && ixp->ixp_registered && -+ ixp->ixp_crd_flags != (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT)) { -+ dprintk("%s - detected direction change on session\n", __FUNCTION__); -+ ixp->ixp_registered = 0; -+ } -+ -+ /* -+ * if we are registered, call straight into the perform code -+ */ -+ if (ixp->ixp_registered) { -+ ixp_q_process(q); -+ return 0; -+ } -+ -+ /* -+ * the only part of the context not set in newsession is the direction -+ * dependent parts -+ */ -+ if (q->ixp_q_ccrd) { -+ ixp->ixp_crd_flags = (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT); -+ if (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT) { -+ ixp->ixp_ctx.operation = q->ixp_q_acrd ? -+ IX_CRYPTO_ACC_OP_ENCRYPT_AUTH : IX_CRYPTO_ACC_OP_ENCRYPT; -+ } else { -+ ixp->ixp_ctx.operation = q->ixp_q_acrd ? -+ IX_CRYPTO_ACC_OP_AUTH_DECRYPT : IX_CRYPTO_ACC_OP_DECRYPT; -+ } -+ } else { -+ /* q->ixp_q_acrd must be set if we are here */ -+ ixp->ixp_ctx.operation = IX_CRYPTO_ACC_OP_AUTH_CALC; -+ } -+ -+ status = list_empty(&ixp->ixp_q); -+ list_add_tail(&q->ixp_q_list, &ixp->ixp_q); -+ if (status) -+ schedule_work(&ixp->ixp_registration_work); -+ return 0; -+ -+done: -+ if (q) -+ kmem_cache_free(qcache, q); -+ crypto_done(crp); -+ return 0; -+} -+ -+ -+#ifdef __ixp46X -+/* -+ * key processing support for the ixp465 -+ */ -+ -+ -+/* -+ * copy a BN (LE) into a buffer (BE) an fill out the op appropriately -+ * assume zeroed and only copy bits that are significant -+ */ -+ -+static int -+ixp_copy_ibuf(struct crparam *p, IxCryptoAccPkeEauOperand *op, UINT32 *buf) -+{ -+ unsigned char *src = (unsigned char *) p->crp_p; -+ unsigned char *dst; -+ int len, bits = p->crp_nbits; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if (bits > MAX_IOP_SIZE * sizeof(UINT32) * 8) { -+ dprintk("%s - ibuf too big (%d > %d)\n", __FUNCTION__, -+ bits, MAX_IOP_SIZE * sizeof(UINT32) * 8); -+ return -1; -+ } -+ -+ len = (bits + 31) / 32; /* the number UINT32's needed */ -+ -+ dst = (unsigned char *) &buf[len]; -+ dst--; -+ -+ while (bits > 0) { -+ *dst-- = *src++; -+ bits -= 8; -+ } -+ -+#if 0 /* no need to zero remaining bits as it is done during request alloc */ -+ while (dst > (unsigned char *) buf) -+ *dst-- = '\0'; -+#endif -+ -+ op->pData = buf; -+ op->dataLen = len; -+ return 0; -+} -+ -+/* -+ * copy out the result, be as forgiving as we can about small output buffers -+ */ -+ -+static int -+ixp_copy_obuf(struct crparam *p, IxCryptoAccPkeEauOpResult *op, UINT32 *buf) -+{ -+ unsigned char *dst = (unsigned char *) p->crp_p; -+ unsigned char *src = (unsigned char *) buf; -+ int len, z, bits = p->crp_nbits; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ len = op->dataLen * sizeof(UINT32); -+ -+ /* skip leading zeroes to be small buffer friendly */ -+ z = 0; -+ while (z < len && src[z] == '\0') -+ z++; -+ -+ src += len; -+ src--; -+ len -= z; -+ -+ while (len > 0 && bits > 0) { -+ *dst++ = *src--; -+ len--; -+ bits -= 8; -+ } -+ -+ while (bits > 0) { -+ *dst++ = '\0'; -+ bits -= 8; -+ } -+ -+ if (len > 0) { -+ dprintk("%s - obuf is %d (z=%d, ob=%d) bytes too small\n", -+ __FUNCTION__, len, z, p->crp_nbits / 8); -+ return -1; -+ } -+ -+ return 0; -+} -+ -+ -+/* -+ * the parameter offsets for exp_mod -+ */ -+ -+#define IXP_PARAM_BASE 0 -+#define IXP_PARAM_EXP 1 -+#define IXP_PARAM_MOD 2 -+#define IXP_PARAM_RES 3 -+ -+/* -+ * key processing complete callback, is also used to start processing -+ * by passing a NULL for pResult -+ */ -+ -+static void -+ixp_kperform_cb( -+ IxCryptoAccPkeEauOperation operation, -+ IxCryptoAccPkeEauOpResult *pResult, -+ BOOL carryOrBorrow, -+ IxCryptoAccStatus status) -+{ -+ struct ixp_pkq *q, *tmp; -+ unsigned long flags; -+ -+ dprintk("%s(0x%x, %p, %d, 0x%x)\n", __FUNCTION__, operation, pResult, -+ carryOrBorrow, status); -+ -+ /* handle a completed request */ -+ if (pResult) { -+ if (ixp_pk_cur && &ixp_pk_cur->pkq_result == pResult) { -+ q = ixp_pk_cur; -+ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { -+ dprintk("%s() - op failed 0x%x\n", __FUNCTION__, status); -+ q->pkq_krp->krp_status = ERANGE; /* could do better */ -+ } else { -+ /* copy out the result */ -+ if (ixp_copy_obuf(&q->pkq_krp->krp_param[IXP_PARAM_RES], -+ &q->pkq_result, q->pkq_obuf)) -+ q->pkq_krp->krp_status = ERANGE; -+ } -+ crypto_kdone(q->pkq_krp); -+ kfree(q); -+ ixp_pk_cur = NULL; -+ } else -+ printk("%s - callback with invalid result pointer\n", __FUNCTION__); -+ } -+ -+ spin_lock_irqsave(&ixp_pkq_lock, flags); -+ if (ixp_pk_cur || list_empty(&ixp_pkq)) { -+ spin_unlock_irqrestore(&ixp_pkq_lock, flags); -+ return; -+ } -+ -+ list_for_each_entry_safe(q, tmp, &ixp_pkq, pkq_list) { -+ -+ list_del(&q->pkq_list); -+ ixp_pk_cur = q; -+ -+ spin_unlock_irqrestore(&ixp_pkq_lock, flags); -+ -+ status = ixCryptoAccPkeEauPerform( -+ IX_CRYPTO_ACC_OP_EAU_MOD_EXP, -+ &q->pkq_op, -+ ixp_kperform_cb, -+ &q->pkq_result); -+ -+ if (status == IX_CRYPTO_ACC_STATUS_SUCCESS) { -+ dprintk("%s() - ixCryptoAccPkeEauPerform SUCCESS\n", __FUNCTION__); -+ return; /* callback will return here for callback */ -+ } else if (status == IX_CRYPTO_ACC_STATUS_RETRY) { -+ printk("%s() - ixCryptoAccPkeEauPerform RETRY\n", __FUNCTION__); -+ } else { -+ printk("%s() - ixCryptoAccPkeEauPerform failed %d\n", -+ __FUNCTION__, status); -+ } -+ q->pkq_krp->krp_status = ERANGE; /* could do better */ -+ crypto_kdone(q->pkq_krp); -+ kfree(q); -+ spin_lock_irqsave(&ixp_pkq_lock, flags); -+ } -+ spin_unlock_irqrestore(&ixp_pkq_lock, flags); -+} -+ -+ -+static int -+ixp_kprocess(device_t dev, struct cryptkop *krp, int hint) -+{ -+ struct ixp_pkq *q; -+ int rc = 0; -+ unsigned long flags; -+ -+ dprintk("%s l1=%d l2=%d l3=%d l4=%d\n", __FUNCTION__, -+ krp->krp_param[IXP_PARAM_BASE].crp_nbits, -+ krp->krp_param[IXP_PARAM_EXP].crp_nbits, -+ krp->krp_param[IXP_PARAM_MOD].crp_nbits, -+ krp->krp_param[IXP_PARAM_RES].crp_nbits); -+ -+ -+ if (krp->krp_op != CRK_MOD_EXP) { -+ krp->krp_status = EOPNOTSUPP; -+ goto err; -+ } -+ -+ q = (struct ixp_pkq *) kmalloc(sizeof(*q), GFP_KERNEL); -+ if (q == NULL) { -+ krp->krp_status = ENOMEM; -+ goto err; -+ } -+ -+ /* -+ * The PKE engine does not appear to zero the output buffer -+ * appropriately, so we need to do it all here. -+ */ -+ memset(q, 0, sizeof(*q)); -+ -+ q->pkq_krp = krp; -+ INIT_LIST_HEAD(&q->pkq_list); -+ -+ if (ixp_copy_ibuf(&krp->krp_param[IXP_PARAM_BASE], &q->pkq_op.modExpOpr.M, -+ q->pkq_ibuf0)) -+ rc = 1; -+ if (!rc && ixp_copy_ibuf(&krp->krp_param[IXP_PARAM_EXP], -+ &q->pkq_op.modExpOpr.e, q->pkq_ibuf1)) -+ rc = 2; -+ if (!rc && ixp_copy_ibuf(&krp->krp_param[IXP_PARAM_MOD], -+ &q->pkq_op.modExpOpr.N, q->pkq_ibuf2)) -+ rc = 3; -+ -+ if (rc) { -+ kfree(q); -+ krp->krp_status = ERANGE; -+ goto err; -+ } -+ -+ q->pkq_result.pData = q->pkq_obuf; -+ q->pkq_result.dataLen = -+ (krp->krp_param[IXP_PARAM_RES].crp_nbits + 31) / 32; -+ -+ spin_lock_irqsave(&ixp_pkq_lock, flags); -+ list_add_tail(&q->pkq_list, &ixp_pkq); -+ spin_unlock_irqrestore(&ixp_pkq_lock, flags); -+ -+ if (!ixp_pk_cur) -+ ixp_kperform_cb(0, NULL, 0, 0); -+ return (0); -+ -+err: -+ crypto_kdone(krp); -+ return (0); -+} -+ -+ -+ -+#ifdef CONFIG_OCF_RANDOMHARVEST -+/* -+ * We run the random number generator output through SHA so that it -+ * is FIPS compliant. -+ */ -+ -+static volatile int sha_done = 0; -+static unsigned char sha_digest[20]; -+ -+static void -+ixp_hash_cb(UINT8 *digest, IxCryptoAccStatus status) -+{ -+ dprintk("%s(%p, %d)\n", __FUNCTION__, digest, status); -+ if (sha_digest != digest) -+ printk("digest error\n"); -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) -+ sha_done = 1; -+ else -+ sha_done = -status; -+} -+ -+static int -+ixp_read_random(void *arg, u_int32_t *buf, int maxwords) -+{ -+ IxCryptoAccStatus status; -+ int i, n, rc; -+ -+ dprintk("%s(%p, %d)\n", __FUNCTION__, buf, maxwords); -+ memset(buf, 0, maxwords * sizeof(*buf)); -+ status = ixCryptoAccPkePseudoRandomNumberGet(maxwords, buf); -+ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { -+ dprintk("%s: ixCryptoAccPkePseudoRandomNumberGet failed %d\n", -+ __FUNCTION__, status); -+ return 0; -+ } -+ -+ /* -+ * run the random data through SHA to make it look more random -+ */ -+ -+ n = sizeof(sha_digest); /* process digest bytes at a time */ -+ -+ rc = 0; -+ for (i = 0; i < maxwords; i += n / sizeof(*buf)) { -+ if ((maxwords - i) * sizeof(*buf) < n) -+ n = (maxwords - i) * sizeof(*buf); -+ sha_done = 0; -+ status = ixCryptoAccPkeHashPerform(IX_CRYPTO_ACC_AUTH_SHA1, -+ (UINT8 *) &buf[i], n, ixp_hash_cb, sha_digest); -+ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { -+ dprintk("ixCryptoAccPkeHashPerform failed %d\n", status); -+ return -EIO; -+ } -+ while (!sha_done) -+ schedule(); -+ if (sha_done < 0) { -+ dprintk("ixCryptoAccPkeHashPerform failed CB %d\n", -sha_done); -+ return 0; -+ } -+ memcpy(&buf[i], sha_digest, n); -+ rc += n / sizeof(*buf);; -+ } -+ -+ return rc; -+} -+#endif /* CONFIG_OCF_RANDOMHARVEST */ -+ -+#endif /* __ixp46X */ -+ -+ -+ -+/* -+ * our driver startup and shutdown routines -+ */ -+ -+static int -+ixp_init(void) -+{ -+ dprintk("%s(%p)\n", __FUNCTION__, ixp_init); -+ -+ if (ixp_init_crypto && ixCryptoAccInit() != IX_CRYPTO_ACC_STATUS_SUCCESS) -+ printk("ixCryptoAccInit failed, assuming already initialised!\n"); -+ -+ qcache = kmem_cache_create("ixp4xx_q", sizeof(struct ixp_q), 0, -+ SLAB_HWCACHE_ALIGN, NULL -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) -+ , NULL -+#endif -+ ); -+ if (!qcache) { -+ printk("failed to create Qcache\n"); -+ return -ENOENT; -+ } -+ -+ memset(&ixpdev, 0, sizeof(ixpdev)); -+ softc_device_init(&ixpdev, "ixp4xx", 0, ixp_methods); -+ -+ ixp_id = crypto_get_driverid(softc_get_device(&ixpdev), -+ CRYPTOCAP_F_HARDWARE); -+ if (ixp_id < 0) -+ panic("IXP/OCF crypto device cannot initialize!"); -+ -+#define REGISTER(alg) \ -+ crypto_register(ixp_id,alg,0,0) -+ -+ REGISTER(CRYPTO_DES_CBC); -+ REGISTER(CRYPTO_3DES_CBC); -+ REGISTER(CRYPTO_RIJNDAEL128_CBC); -+#ifdef CONFIG_OCF_IXP4XX_SHA1_MD5 -+ REGISTER(CRYPTO_MD5); -+ REGISTER(CRYPTO_SHA1); -+#endif -+ REGISTER(CRYPTO_MD5_HMAC); -+ REGISTER(CRYPTO_SHA1_HMAC); -+#undef REGISTER -+ -+#ifdef __ixp46X -+ spin_lock_init(&ixp_pkq_lock); -+ /* -+ * we do not enable the go fast options here as they can potentially -+ * allow timing based attacks -+ * -+ * http://www.openssl.org/news/secadv_20030219.txt -+ */ -+ ixCryptoAccPkeEauExpConfig(0, 0); -+ crypto_kregister(ixp_id, CRK_MOD_EXP, 0); -+#ifdef CONFIG_OCF_RANDOMHARVEST -+ crypto_rregister(ixp_id, ixp_read_random, NULL); -+#endif -+#endif -+ -+ return 0; -+} -+ -+static void -+ixp_exit(void) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ crypto_unregister_all(ixp_id); -+ ixp_id = -1; -+ kmem_cache_destroy(qcache); -+ qcache = NULL; -+} -+ -+module_init(ixp_init); -+module_exit(ixp_exit); -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("ixp (OCF module for IXP4xx crypto)"); -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/Makefile linux-3.0.4/crypto/ocf/kirkwood/Makefile ---- linux-3.0.4.orig/crypto/ocf/kirkwood/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/Makefile 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,19 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+obj-$(CONFIG_OCF_KIRKWOOD) += mv_cesa.o -+ -+mv_cesa-y := cesa/mvCesa.o cesa/mvLru.o cesa/mvMD5.o cesa/mvSHA1.o cesa/AES/mvAesAlg.o cesa/AES/mvAesApi.o cesa/mvCesaDebug.o cesa_ocf_drv.o -+ -+# Extra objects required by the CESA driver -+mv_cesa-y += mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.o mvHal/kw_family/boardEnv/mvBoardEnvLib.o mvHal/mv_hal/twsi/mvTwsi.o mvHal/kw_family/ctrlEnv/sys/mvCpuIf.o mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.o mvHal/kw_family/ctrlEnv/sys/mvSysDram.o mvHal/linux_oss/mvOs.o mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.o mvHal/mv_hal/gpp/mvGpp.o mvHal/kw_family/ctrlEnv/sys/mvSysPex.o mvHal/mv_hal/pex/mvPex.o mvHal/kw_family/boardEnv/mvBoardEnvSpec.o mvHal/common/mvCommon.o mvHal/common/mvDebug.o mvHal/kw_family/ctrlEnv/sys/mvSysCesa.o -+ -+ifdef src -+EXTRA_CFLAGS += -I$(src)/.. -I$(src)/cesa -I$(src)/mvHal -I$(src)/mvHal/common -I$(src)/mvHal/kw_family -I$(src)/mvHal/mv_hal -I$(src)/mvHal/linux_oss -I$(src) -+endif -+ -+EXTRA_CFLAGS += -DMV_LINUX -DMV_CPU_LE -DMV_ARM -DMV_INCLUDE_CESA -DMV_INCLUDE_PEX -DMV_CACHE_COHERENCY=3 -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/AES/mvAes.h linux-3.0.4/crypto/ocf/kirkwood/cesa/AES/mvAes.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/AES/mvAes.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/cesa/AES/mvAes.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,62 @@ -+/* mvAes.h v2.0 August '99 -+ * Reference ANSI C code -+ */ -+ -+/* AES Cipher header file for ANSI C Submissions -+ Lawrence E. Bassham III -+ Computer Security Division -+ National Institute of Standards and Technology -+ -+ April 15, 1998 -+ -+ This sample is to assist implementers developing to the Cryptographic -+API Profile for AES Candidate Algorithm Submissions. Please consult this -+document as a cross-reference. -+ -+ ANY CHANGES, WHERE APPROPRIATE, TO INFORMATION PROVIDED IN THIS FILE -+MUST BE DOCUMENTED. CHANGES ARE ONLY APPROPRIATE WHERE SPECIFIED WITH -+THE STRING "CHANGE POSSIBLE". FUNCTION CALLS AND THEIR PARAMETERS CANNOT -+BE CHANGED. STRUCTURES CAN BE ALTERED TO ALLOW IMPLEMENTERS TO INCLUDE -+IMPLEMENTATION SPECIFIC INFORMATION. -+*/ -+ -+/* Includes: -+ Standard include files -+*/ -+ -+#include "mvOs.h" -+ -+ -+/* Error Codes - CHANGE POSSIBLE: inclusion of additional error codes */ -+ -+/* Key direction is invalid, e.g., unknown value */ -+#define AES_BAD_KEY_DIR -1 -+ -+/* Key material not of correct length */ -+#define AES_BAD_KEY_MAT -2 -+ -+/* Key passed is not valid */ -+#define AES_BAD_KEY_INSTANCE -3 -+ -+/* Params struct passed to cipherInit invalid */ -+#define AES_BAD_CIPHER_MODE -4 -+ -+/* Cipher in wrong state (e.g., not initialized) */ -+#define AES_BAD_CIPHER_STATE -5 -+ -+#define AES_BAD_CIPHER_INSTANCE -7 -+ -+ -+/* Function protoypes */ -+/* CHANGED: makeKey(): parameter blockLen added -+ this parameter is absolutely necessary if you want to -+ setup the round keys in a variable block length setting -+ cipherInit(): parameter blockLen added (for obvious reasons) -+ */ -+int aesMakeKey(MV_U8 *expandedKey, MV_U8 *keyMaterial, int keyLen, int blockLen); -+int aesBlockEncrypt128(MV_U8 mode, MV_U8 *IV, MV_U8 *expandedKey, int keyLen, -+ MV_U32 *plain, int numBlocks, MV_U32 *cipher); -+int aesBlockDecrypt128(MV_U8 mode, MV_U8 *IV, MV_U8 *expandedKey, int keyLen, -+ MV_U32 *plain, int numBlocks, MV_U32 *cipher); -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.c linux-3.0.4/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,317 @@ -+/* rijndael-alg-ref.c v2.0 August '99 -+ * Reference ANSI C code -+ * authors: Paulo Barreto -+ * Vincent Rijmen, K.U.Leuven -+ * -+ * This code is placed in the public domain. -+ */ -+ -+#include "mvOs.h" -+ -+#include "mvAesAlg.h" -+ -+#include "mvAesBoxes.dat" -+ -+ -+MV_U8 mul1(MV_U8 aa, MV_U8 bb); -+void KeyAddition(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC], MV_U8 BC); -+void ShiftRow128Enc(MV_U8 a[4][MAXBC]); -+void ShiftRow128Dec(MV_U8 a[4][MAXBC]); -+void Substitution(MV_U8 a[4][MAXBC], MV_U8 box[256]); -+void MixColumn(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC]); -+void InvMixColumn(MV_U8 a[4][MAXBC]); -+ -+ -+#define mul(aa, bb) (mask[bb] & Alogtable[aa + Logtable[bb]]) -+ -+MV_U8 mul1(MV_U8 aa, MV_U8 bb) -+{ -+ return mask[bb] & Alogtable[aa + Logtable[bb]]; -+} -+ -+ -+void KeyAddition(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC], MV_U8 BC) -+{ -+ /* Exor corresponding text input and round key input bytes -+ */ -+ ((MV_U32*)(&(a[0][0])))[0] ^= ((MV_U32*)(&(rk[0][0])))[0]; -+ ((MV_U32*)(&(a[1][0])))[0] ^= ((MV_U32*)(&(rk[1][0])))[0]; -+ ((MV_U32*)(&(a[2][0])))[0] ^= ((MV_U32*)(&(rk[2][0])))[0]; -+ ((MV_U32*)(&(a[3][0])))[0] ^= ((MV_U32*)(&(rk[3][0])))[0]; -+ -+} -+ -+void ShiftRow128Enc(MV_U8 a[4][MAXBC]) { -+ /* Row 0 remains unchanged -+ * The other three rows are shifted a variable amount -+ */ -+ MV_U8 tmp[MAXBC]; -+ -+ tmp[0] = a[1][1]; -+ tmp[1] = a[1][2]; -+ tmp[2] = a[1][3]; -+ tmp[3] = a[1][0]; -+ -+ ((MV_U32*)(&(a[1][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; -+ /* -+ a[1][0] = tmp[0]; -+ a[1][1] = tmp[1]; -+ a[1][2] = tmp[2]; -+ a[1][3] = tmp[3]; -+ */ -+ tmp[0] = a[2][2]; -+ tmp[1] = a[2][3]; -+ tmp[2] = a[2][0]; -+ tmp[3] = a[2][1]; -+ -+ ((MV_U32*)(&(a[2][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; -+ /* -+ a[2][0] = tmp[0]; -+ a[2][1] = tmp[1]; -+ a[2][2] = tmp[2]; -+ a[2][3] = tmp[3]; -+ */ -+ tmp[0] = a[3][3]; -+ tmp[1] = a[3][0]; -+ tmp[2] = a[3][1]; -+ tmp[3] = a[3][2]; -+ -+ ((MV_U32*)(&(a[3][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; -+ /* -+ a[3][0] = tmp[0]; -+ a[3][1] = tmp[1]; -+ a[3][2] = tmp[2]; -+ a[3][3] = tmp[3]; -+ */ -+} -+ -+void ShiftRow128Dec(MV_U8 a[4][MAXBC]) { -+ /* Row 0 remains unchanged -+ * The other three rows are shifted a variable amount -+ */ -+ MV_U8 tmp[MAXBC]; -+ -+ tmp[0] = a[1][3]; -+ tmp[1] = a[1][0]; -+ tmp[2] = a[1][1]; -+ tmp[3] = a[1][2]; -+ -+ ((MV_U32*)(&(a[1][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; -+ /* -+ a[1][0] = tmp[0]; -+ a[1][1] = tmp[1]; -+ a[1][2] = tmp[2]; -+ a[1][3] = tmp[3]; -+ */ -+ -+ tmp[0] = a[2][2]; -+ tmp[1] = a[2][3]; -+ tmp[2] = a[2][0]; -+ tmp[3] = a[2][1]; -+ -+ ((MV_U32*)(&(a[2][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; -+ /* -+ a[2][0] = tmp[0]; -+ a[2][1] = tmp[1]; -+ a[2][2] = tmp[2]; -+ a[2][3] = tmp[3]; -+ */ -+ -+ tmp[0] = a[3][1]; -+ tmp[1] = a[3][2]; -+ tmp[2] = a[3][3]; -+ tmp[3] = a[3][0]; -+ -+ ((MV_U32*)(&(a[3][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; -+ /* -+ a[3][0] = tmp[0]; -+ a[3][1] = tmp[1]; -+ a[3][2] = tmp[2]; -+ a[3][3] = tmp[3]; -+ */ -+} -+ -+void Substitution(MV_U8 a[4][MAXBC], MV_U8 box[256]) { -+ /* Replace every byte of the input by the byte at that place -+ * in the nonlinear S-box -+ */ -+ int i, j; -+ -+ for(i = 0; i < 4; i++) -+ for(j = 0; j < 4; j++) a[i][j] = box[a[i][j]] ; -+} -+ -+void MixColumn(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC]) { -+ /* Mix the four bytes of every column in a linear way -+ */ -+ MV_U8 b[4][MAXBC]; -+ int i, j; -+ -+ for(j = 0; j < 4; j++){ -+ b[0][j] = mul(25,a[0][j]) ^ mul(1,a[1][j]) ^ a[2][j] ^ a[3][j]; -+ b[1][j] = mul(25,a[1][j]) ^ mul(1,a[2][j]) ^ a[3][j] ^ a[0][j]; -+ b[2][j] = mul(25,a[2][j]) ^ mul(1,a[3][j]) ^ a[0][j] ^ a[1][j]; -+ b[3][j] = mul(25,a[3][j]) ^ mul(1,a[0][j]) ^ a[1][j] ^ a[2][j]; -+ } -+ for(i = 0; i < 4; i++) -+ /*for(j = 0; j < BC; j++) a[i][j] = b[i][j];*/ -+ ((MV_U32*)(&(a[i][0])))[0] = ((MV_U32*)(&(b[i][0])))[0] ^ ((MV_U32*)(&(rk[i][0])))[0];; -+} -+ -+void InvMixColumn(MV_U8 a[4][MAXBC]) { -+ /* Mix the four bytes of every column in a linear way -+ * This is the opposite operation of Mixcolumn -+ */ -+ MV_U8 b[4][MAXBC]; -+ int i, j; -+ -+ for(j = 0; j < 4; j++){ -+ b[0][j] = mul(223,a[0][j]) ^ mul(104,a[1][j]) ^ mul(238,a[2][j]) ^ mul(199,a[3][j]); -+ b[1][j] = mul(223,a[1][j]) ^ mul(104,a[2][j]) ^ mul(238,a[3][j]) ^ mul(199,a[0][j]); -+ b[2][j] = mul(223,a[2][j]) ^ mul(104,a[3][j]) ^ mul(238,a[0][j]) ^ mul(199,a[1][j]); -+ b[3][j] = mul(223,a[3][j]) ^ mul(104,a[0][j]) ^ mul(238,a[1][j]) ^ mul(199,a[2][j]); -+ } -+ for(i = 0; i < 4; i++) -+ /*for(j = 0; j < BC; j++) a[i][j] = b[i][j];*/ -+ ((MV_U32*)(&(a[i][0])))[0] = ((MV_U32*)(&(b[i][0])))[0]; -+} -+ -+int rijndaelKeySched (MV_U8 k[4][MAXKC], int keyBits, int blockBits, MV_U8 W[MAXROUNDS+1][4][MAXBC]) -+{ -+ /* Calculate the necessary round keys -+ * The number of calculations depends on keyBits and blockBits -+ */ -+ int KC, BC, ROUNDS; -+ int i, j, t, rconpointer = 0; -+ MV_U8 tk[4][MAXKC]; -+ -+ switch (keyBits) { -+ case 128: KC = 4; break; -+ case 192: KC = 6; break; -+ case 256: KC = 8; break; -+ default : return (-1); -+ } -+ -+ switch (blockBits) { -+ case 128: BC = 4; break; -+ case 192: BC = 6; break; -+ case 256: BC = 8; break; -+ default : return (-2); -+ } -+ -+ switch (keyBits >= blockBits ? keyBits : blockBits) { -+ case 128: ROUNDS = 10; break; -+ case 192: ROUNDS = 12; break; -+ case 256: ROUNDS = 14; break; -+ default : return (-3); /* this cannot happen */ -+ } -+ -+ -+ for(j = 0; j < KC; j++) -+ for(i = 0; i < 4; i++) -+ tk[i][j] = k[i][j]; -+ t = 0; -+ /* copy values into round key array */ -+ for(j = 0; (j < KC) && (t < (ROUNDS+1)*BC); j++, t++) -+ for(i = 0; i < 4; i++) W[t / BC][i][t % BC] = tk[i][j]; -+ -+ while (t < (ROUNDS+1)*BC) { /* while not enough round key material calculated */ -+ /* calculate new values */ -+ for(i = 0; i < 4; i++) -+ tk[i][0] ^= S[tk[(i+1)%4][KC-1]]; -+ tk[0][0] ^= rcon[rconpointer++]; -+ -+ if (KC != 8) -+ for(j = 1; j < KC; j++) -+ for(i = 0; i < 4; i++) tk[i][j] ^= tk[i][j-1]; -+ else { -+ for(j = 1; j < KC/2; j++) -+ for(i = 0; i < 4; i++) tk[i][j] ^= tk[i][j-1]; -+ for(i = 0; i < 4; i++) tk[i][KC/2] ^= S[tk[i][KC/2 - 1]]; -+ for(j = KC/2 + 1; j < KC; j++) -+ for(i = 0; i < 4; i++) tk[i][j] ^= tk[i][j-1]; -+ } -+ /* copy values into round key array */ -+ for(j = 0; (j < KC) && (t < (ROUNDS+1)*BC); j++, t++) -+ for(i = 0; i < 4; i++) W[t / BC][i][t % BC] = tk[i][j]; -+ } -+ -+ return 0; -+} -+ -+ -+ -+int rijndaelEncrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds) -+{ -+ /* Encryption of one block. -+ */ -+ int r, BC, ROUNDS; -+ -+ BC = 4; -+ ROUNDS = rounds; -+ -+ /* begin with a key addition -+ */ -+ -+ KeyAddition(a,rk[0],BC); -+ -+ /* ROUNDS-1 ordinary rounds -+ */ -+ for(r = 1; r < ROUNDS; r++) { -+ Substitution(a,S); -+ ShiftRow128Enc(a); -+ MixColumn(a, rk[r]); -+ /*KeyAddition(a,rk[r],BC);*/ -+ } -+ -+ /* Last round is special: there is no MixColumn -+ */ -+ Substitution(a,S); -+ ShiftRow128Enc(a); -+ KeyAddition(a,rk[ROUNDS],BC); -+ -+ return 0; -+} -+ -+ -+int rijndaelDecrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds) -+{ -+ int r, BC, ROUNDS; -+ -+ BC = 4; -+ ROUNDS = rounds; -+ -+ /* To decrypt: apply the inverse operations of the encrypt routine, -+ * in opposite order -+ * -+ * (KeyAddition is an involution: it 's equal to its inverse) -+ * (the inverse of Substitution with table S is Substitution with the inverse table of S) -+ * (the inverse of Shiftrow is Shiftrow over a suitable distance) -+ */ -+ -+ /* First the special round: -+ * without InvMixColumn -+ * with extra KeyAddition -+ */ -+ KeyAddition(a,rk[ROUNDS],BC); -+ ShiftRow128Dec(a); -+ Substitution(a,Si); -+ -+ /* ROUNDS-1 ordinary rounds -+ */ -+ for(r = ROUNDS-1; r > 0; r--) { -+ KeyAddition(a,rk[r],BC); -+ InvMixColumn(a); -+ ShiftRow128Dec(a); -+ Substitution(a,Si); -+ -+ } -+ -+ /* End with the extra key addition -+ */ -+ -+ KeyAddition(a,rk[0],BC); -+ -+ return 0; -+} -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.h linux-3.0.4/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,19 @@ -+/* rijndael-alg-ref.h v2.0 August '99 -+ * Reference ANSI C code -+ * authors: Paulo Barreto -+ * Vincent Rijmen, K.U.Leuven -+ */ -+#ifndef __RIJNDAEL_ALG_H -+#define __RIJNDAEL_ALG_H -+ -+#define MAXBC (128/32) -+#define MAXKC (256/32) -+#define MAXROUNDS 14 -+ -+ -+int rijndaelKeySched (MV_U8 k[4][MAXKC], int keyBits, int blockBits, MV_U8 rk[MAXROUNDS+1][4][MAXBC]); -+ -+int rijndaelEncrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds); -+int rijndaelDecrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds); -+ -+#endif /* __RIJNDAEL_ALG_H */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/AES/mvAesApi.c linux-3.0.4/crypto/ocf/kirkwood/cesa/AES/mvAesApi.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/AES/mvAesApi.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/cesa/AES/mvAesApi.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,312 @@ -+/* rijndael-api-ref.c v2.1 April 2000 -+ * Reference ANSI C code -+ * authors: v2.0 Paulo Barreto -+ * Vincent Rijmen, K.U.Leuven -+ * v2.1 Vincent Rijmen, K.U.Leuven -+ * -+ * This code is placed in the public domain. -+ */ -+#include "mvOs.h" -+ -+#include "mvAes.h" -+#include "mvAesAlg.h" -+ -+ -+/* Defines: -+ Add any additional defines you need -+*/ -+ -+#define MODE_ECB 1 /* Are we ciphering in ECB mode? */ -+#define MODE_CBC 2 /* Are we ciphering in CBC mode? */ -+#define MODE_CFB1 3 /* Are we ciphering in 1-bit CFB mode? */ -+ -+ -+int aesMakeKey(MV_U8 *expandedKey, MV_U8 *keyMaterial, int keyLen, int blockLen) -+{ -+ MV_U8 W[MAXROUNDS+1][4][MAXBC]; -+ MV_U8 k[4][MAXKC]; -+ MV_U8 j; -+ int i, rounds, KC; -+ -+ if (expandedKey == NULL) -+ { -+ return AES_BAD_KEY_INSTANCE; -+ } -+ -+ if (!((keyLen == 128) || (keyLen == 192) || (keyLen == 256))) -+ { -+ return AES_BAD_KEY_MAT; -+ } -+ -+ if (keyMaterial == NULL) -+ { -+ return AES_BAD_KEY_MAT; -+ } -+ -+ /* initialize key schedule: */ -+ for(i=0; i= 3) -+MV_U32 cesaChainLength = 0; -+int chainReqNum = 0; -+MV_U32 chainIndex = 0; -+MV_CESA_REQ* pNextActiveChain = 0; -+MV_CESA_REQ* pEndCurrChain = 0; -+MV_BOOL isFirstReq = MV_TRUE; -+#endif -+ -+static INLINE MV_U8* mvCesaSramAddrGet(void) -+{ -+#ifdef MV_CESA_NO_SRAM -+ return (MV_U8*)cesaSramVirtPtr; -+#else -+ return (MV_U8*)cesaCryptEngBase; -+#endif /* MV_CESA_NO_SRAM */ -+} -+ -+static INLINE MV_ULONG mvCesaSramVirtToPhys(void* pDev, MV_U8* pSramVirt) -+{ -+#ifdef MV_CESA_NO_SRAM -+ return (MV_ULONG)mvOsIoVirtToPhy(NULL, pSramVirt); -+#else -+ return (MV_ULONG)pSramVirt; -+#endif /* MV_CESA_NO_SRAM */ -+} -+ -+/* Internal Function prototypes */ -+ -+static INLINE void mvCesaSramDescrBuild(MV_U32 config, int frag, -+ int cryptoOffset, int ivOffset, int cryptoLength, -+ int macOffset, int digestOffset, int macLength, int macTotalLen, -+ MV_CESA_REQ *pCesaReq, MV_DMA_DESC* pDmaDesc); -+ -+static INLINE void mvCesaSramSaUpdate(short sid, MV_DMA_DESC *pDmaDesc); -+ -+static INLINE int mvCesaDmaCopyPrepare(MV_CESA_MBUF* pMbuf, MV_U8* pSramBuf, -+ MV_DMA_DESC* pDmaDesc, MV_BOOL isToMbuf, -+ int offset, int copySize, MV_BOOL skipFlush); -+ -+static void mvCesaHmacIvGet(MV_CESA_MAC_MODE macMode, unsigned char key[], int keyLength, -+ unsigned char innerIV[], unsigned char outerIV[]); -+ -+static MV_STATUS mvCesaFragAuthComplete(MV_CESA_REQ* pReq, MV_CESA_SA* pSA, -+ int macDataSize); -+ -+static MV_CESA_COMMAND* mvCesaCtrModeInit(void); -+ -+static MV_STATUS mvCesaCtrModePrepare(MV_CESA_COMMAND *pCtrModeCmd, MV_CESA_COMMAND *pCmd); -+static MV_STATUS mvCesaCtrModeComplete(MV_CESA_COMMAND *pOrgCmd, MV_CESA_COMMAND *pCmd); -+static void mvCesaCtrModeFinish(MV_CESA_COMMAND *pCmd); -+ -+static INLINE MV_STATUS mvCesaReqProcess(MV_CESA_REQ* pReq); -+static MV_STATUS mvCesaFragReqProcess(MV_CESA_REQ* pReq, MV_U8 frag); -+ -+static INLINE MV_STATUS mvCesaParamCheck(MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, MV_U8* pFixOffset); -+static INLINE MV_STATUS mvCesaFragParamCheck(MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd); -+ -+static INLINE void mvCesaFragSizeFind(MV_CESA_SA* pSA, MV_CESA_REQ* pReq, -+ int cryptoOffset, int macOffset, -+ int* pCopySize, int* pCryptoDataSize, int* pMacDataSize); -+static MV_STATUS mvCesaMbufCacheUnmap(MV_CESA_MBUF* pMbuf, int offset, int size); -+ -+ -+/* Go to the next request in the request queue */ -+static INLINE MV_CESA_REQ* MV_CESA_REQ_NEXT_PTR(MV_CESA_REQ* pReq) -+{ -+ if(pReq == pCesaReqLast) -+ return pCesaReqFirst; -+ -+ return pReq+1; -+} -+ -+#if (MV_CESA_VERSION >= 3) -+/* Go to the previous request in the request queue */ -+static INLINE MV_CESA_REQ* MV_CESA_REQ_PREV_PTR(MV_CESA_REQ* pReq) -+{ -+ if(pReq == pCesaReqFirst) -+ return pCesaReqLast; -+ -+ return pReq-1; -+} -+ -+#endif -+ -+ -+static INLINE void mvCesaReqProcessStart(MV_CESA_REQ* pReq) -+{ -+ int frag; -+ -+#if (MV_CESA_VERSION >= 3) -+ pReq->state = MV_CESA_CHAIN; -+#else -+ pReq->state = MV_CESA_PROCESS; -+#endif -+ cesaStats.startCount++; -+ -+ if(pReq->fragMode == MV_CESA_FRAG_NONE) -+ { -+ frag = 0; -+ } -+ else -+ { -+ frag = pReq->frags.nextFrag; -+ pReq->frags.nextFrag++; -+ } -+#if (MV_CESA_VERSION >= 2) -+ /* Enable TDMA engine */ -+ MV_REG_WRITE(MV_CESA_TDMA_CURR_DESC_PTR_REG, 0); -+ MV_REG_WRITE(MV_CESA_TDMA_NEXT_DESC_PTR_REG, -+ (MV_U32)mvCesaVirtToPhys(&pReq->dmaDescBuf, pReq->dma[frag].pDmaFirst)); -+#else -+ /* Enable IDMA engine */ -+ MV_REG_WRITE(IDMA_CURR_DESC_PTR_REG(0), 0); -+ MV_REG_WRITE(IDMA_NEXT_DESC_PTR_REG(0), -+ (MV_U32)mvCesaVirtToPhys(&pReq->dmaDescBuf, pReq->dma[frag].pDmaFirst)); -+#endif /* MV_CESA_VERSION >= 2 */ -+ -+#if defined(MV_BRIDGE_SYNC_REORDER) -+ mvOsBridgeReorderWA(); -+#endif -+ -+ /* Start Accelerator */ -+ MV_REG_WRITE(MV_CESA_CMD_REG, MV_CESA_CMD_CHAN_ENABLE_MASK); -+} -+ -+ -+/******************************************************************************* -+* mvCesaHalInit - Initialize the CESA driver -+* -+* DESCRIPTION: -+* This function initialize the CESA driver. -+* 1) Session database -+* 2) Request queue -+* 4) DMA descriptor lists - one list per request. Each list -+* has MV_CESA_MAX_DMA_DESC descriptors. -+* -+* INPUT: -+* numOfSession - maximum number of supported sessions -+* queueDepth - number of elements in the request queue. -+* pSramBase - virtual address of Sram -+* osHandle - A handle used by the OS to allocate memory for the -+* module (Passed to the OS Services layer) -+* -+* RETURN: -+* MV_OK - Success -+* MV_NO_RESOURCE - Fail, can't allocate resources: -+* Session database, request queue, -+* DMA descriptors list, LRU cache database. -+* MV_NOT_ALIGNED - Sram base address is not 8 byte aligned. -+* -+*******************************************************************************/ -+MV_STATUS mvCesaHalInit (int numOfSession, int queueDepth, char* pSramBase, MV_U32 cryptEngBase, -+ void *osHandle) -+{ -+ int i, req; -+ MV_U32 descOffsetReg, configReg; -+ MV_CESA_SRAM_SA *pSramSA; -+ -+ -+ mvOsPrintf("mvCesaInit: sessions=%d, queue=%d, pSram=%p\n", -+ numOfSession, queueDepth, pSramBase); -+ -+ cesaOsHandle = osHandle; -+ /* Create Session database */ -+ pCesaSAD = mvOsMalloc(sizeof(MV_CESA_SA)*numOfSession); -+ if(pCesaSAD == NULL) -+ { -+ mvOsPrintf("mvCesaInit: Can't allocate %u bytes for %d SAs\n", -+ sizeof(MV_CESA_SA)*numOfSession, numOfSession); -+ mvCesaFinish(); -+ return MV_NO_RESOURCE; -+ } -+ memset(pCesaSAD, 0, sizeof(MV_CESA_SA)*numOfSession); -+ cesaMaxSA = numOfSession; -+ -+ /* Allocate imag of sramSA in the DRAM */ -+ cesaSramSaBuf.bufSize = sizeof(MV_CESA_SRAM_SA)*numOfSession + -+ CPU_D_CACHE_LINE_SIZE; -+ -+ cesaSramSaBuf.bufVirtPtr = mvOsIoCachedMalloc(osHandle,cesaSramSaBuf.bufSize, -+ &cesaSramSaBuf.bufPhysAddr, -+ &cesaSramSaBuf.memHandle); -+ -+ if(cesaSramSaBuf.bufVirtPtr == NULL) -+ { -+ mvOsPrintf("mvCesaInit: Can't allocate %d bytes for sramSA structures\n", -+ cesaSramSaBuf.bufSize); -+ mvCesaFinish(); -+ return MV_NO_RESOURCE; -+ } -+ memset(cesaSramSaBuf.bufVirtPtr, 0, cesaSramSaBuf.bufSize); -+ pSramSA = (MV_CESA_SRAM_SA*)MV_ALIGN_UP((MV_ULONG)cesaSramSaBuf.bufVirtPtr, -+ CPU_D_CACHE_LINE_SIZE); -+ for(i=0; i= 3) -+ cesaChainLength = MAX_CESA_CHAIN_LENGTH; -+#endif -+ /* pSramBase must be 8 byte aligned */ -+ if( MV_IS_NOT_ALIGN((MV_ULONG)pSramBase, 8) ) -+ { -+ mvOsPrintf("mvCesaInit: pSramBase (%p) must be 8 byte aligned\n", -+ pSramBase); -+ mvCesaFinish(); -+ return MV_NOT_ALIGNED; -+ } -+ cesaSramVirtPtr = (MV_CESA_SRAM_MAP*)pSramBase; -+ -+ cesaCryptEngBase = cryptEngBase; -+ -+ /*memset(cesaSramVirtPtr, 0, sizeof(MV_CESA_SRAM_MAP));*/ -+ -+ /* Clear registers */ -+ MV_REG_WRITE( MV_CESA_CFG_REG, 0); -+ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); -+ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, 0); -+ -+ /* Initialize DMA descriptor lists for all requests in Request queue */ -+ descOffsetReg = configReg = 0; -+ for(req=0; reqcesaDescBuf.bufSize = sizeof(MV_CESA_DESC)*MV_CESA_MAX_REQ_FRAGS + -+ CPU_D_CACHE_LINE_SIZE; -+ -+ pReq->cesaDescBuf.bufVirtPtr = -+ mvOsIoCachedMalloc(osHandle,pReq->cesaDescBuf.bufSize, -+ &pReq->cesaDescBuf.bufPhysAddr, -+ &pReq->cesaDescBuf.memHandle); -+ -+ if(pReq->cesaDescBuf.bufVirtPtr == NULL) -+ { -+ mvOsPrintf("mvCesaInit: req=%d, Can't allocate %d bytes for CESA descriptors\n", -+ req, pReq->cesaDescBuf.bufSize); -+ mvCesaFinish(); -+ return MV_NO_RESOURCE; -+ } -+ memset(pReq->cesaDescBuf.bufVirtPtr, 0, pReq->cesaDescBuf.bufSize); -+ pReq->pCesaDesc = (MV_CESA_DESC*)MV_ALIGN_UP((MV_ULONG)pReq->cesaDescBuf.bufVirtPtr, -+ CPU_D_CACHE_LINE_SIZE); -+ -+ pReq->dmaDescBuf.bufSize = sizeof(MV_DMA_DESC)*MV_CESA_MAX_DMA_DESC*MV_CESA_MAX_REQ_FRAGS + -+ CPU_D_CACHE_LINE_SIZE; -+ -+ pReq->dmaDescBuf.bufVirtPtr = -+ mvOsIoCachedMalloc(osHandle,pReq->dmaDescBuf.bufSize, -+ &pReq->dmaDescBuf.bufPhysAddr, -+ &pReq->dmaDescBuf.memHandle); -+ -+ if(pReq->dmaDescBuf.bufVirtPtr == NULL) -+ { -+ mvOsPrintf("mvCesaInit: req=%d, Can't allocate %d bytes for DMA descriptor list\n", -+ req, pReq->dmaDescBuf.bufSize); -+ mvCesaFinish(); -+ return MV_NO_RESOURCE; -+ } -+ memset(pReq->dmaDescBuf.bufVirtPtr, 0, pReq->dmaDescBuf.bufSize); -+ pDmaDesc = (MV_DMA_DESC*)MV_ALIGN_UP((MV_ULONG)pReq->dmaDescBuf.bufVirtPtr, -+ CPU_D_CACHE_LINE_SIZE); -+ -+ for(frag=0; fragdma[frag]; -+ -+ pDma->pDmaFirst = pDmaDesc; -+ pDma->pDmaLast = NULL; -+ -+ for(i=0; ipDmaFirst[i].phyNextDescPtr = -+ MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, &pDmaDesc[i+1])); -+ } -+ pDma->pDmaFirst[i].phyNextDescPtr = 0; -+ mvOsCacheFlush(NULL, &pDma->pDmaFirst[0], MV_CESA_MAX_DMA_DESC*sizeof(MV_DMA_DESC)); -+ -+ pDmaDesc += MV_CESA_MAX_DMA_DESC; -+ } -+ } -+ /*mvCesaCryptoIvSet(NULL, MV_CESA_MAX_IV_LENGTH);*/ -+ descOffsetReg = (MV_U16)((MV_U8*)&cesaSramVirtPtr->desc - mvCesaSramAddrGet()); -+ MV_REG_WRITE(MV_CESA_CHAN_DESC_OFFSET_REG, descOffsetReg); -+ -+ configReg |= (MV_CESA_CFG_WAIT_DMA_MASK | MV_CESA_CFG_ACT_DMA_MASK); -+#if (MV_CESA_VERSION >= 3) -+ configReg |= MV_CESA_CFG_CHAIN_MODE_MASK; -+#endif -+ -+#if (MV_CESA_VERSION >= 2) -+ /* Initialize TDMA engine */ -+ MV_REG_WRITE(MV_CESA_TDMA_CTRL_REG, MV_CESA_TDMA_CTRL_VALUE); -+ MV_REG_WRITE(MV_CESA_TDMA_BYTE_COUNT_REG, 0); -+ MV_REG_WRITE(MV_CESA_TDMA_CURR_DESC_PTR_REG, 0); -+#else -+ /* Initialize IDMA #0 engine */ -+ MV_REG_WRITE(IDMA_CTRL_LOW_REG(0), 0); -+ MV_REG_WRITE(IDMA_BYTE_COUNT_REG(0), 0); -+ MV_REG_WRITE(IDMA_CURR_DESC_PTR_REG(0), 0); -+ MV_REG_WRITE(IDMA_CTRL_HIGH_REG(0), ICCHR_ENDIAN_LITTLE -+#ifdef MV_CPU_LE -+ | ICCHR_DESC_BYTE_SWAP_EN -+#endif -+ ); -+ /* Clear Cause Byte of IDMA channel to be used */ -+ MV_REG_WRITE( IDMA_CAUSE_REG, ~ICICR_CAUSE_MASK_ALL(0)); -+ MV_REG_WRITE(IDMA_CTRL_LOW_REG(0), MV_CESA_IDMA_CTRL_LOW_VALUE); -+#endif /* (MV_CESA_VERSION >= 2) */ -+ -+ /* Set CESA configuration registers */ -+ MV_REG_WRITE( MV_CESA_CFG_REG, configReg); -+ mvCesaDebugStatsClear(); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaFinish - Shutdown the CESA driver -+* -+* DESCRIPTION: -+* This function shutdown the CESA driver and free all allocted resources. -+* -+* INPUT: None -+* -+* RETURN: -+* MV_OK - Success -+* Other - Fail -+* -+*******************************************************************************/ -+MV_STATUS mvCesaFinish (void) -+{ -+ int req; -+ MV_CESA_REQ* pReq; -+ -+ mvOsPrintf("mvCesaFinish: \n"); -+ -+ cesaSramVirtPtr = NULL; -+ -+ /* Free all resources: DMA list, etc. */ -+ for(req=0; reqdmaDescBuf.bufVirtPtr != NULL) -+ { -+ mvOsIoCachedFree(cesaOsHandle,pReq->dmaDescBuf.bufSize, -+ pReq->dmaDescBuf.bufPhysAddr, -+ pReq->dmaDescBuf.bufVirtPtr, -+ pReq->dmaDescBuf.memHandle); -+ } -+ if(pReq->cesaDescBuf.bufVirtPtr != NULL) -+ { -+ mvOsIoCachedFree(cesaOsHandle,pReq->cesaDescBuf.bufSize, -+ pReq->cesaDescBuf.bufPhysAddr, -+ pReq->cesaDescBuf.bufVirtPtr, -+ pReq->cesaDescBuf.memHandle); -+ } -+ } -+#if (MV_CESA_VERSION < 2) -+ MV_REG_WRITE(IDMA_CTRL_LOW_REG(0), 0); -+#endif /* (MV_CESA_VERSION < 2) */ -+ -+ /* Free request queue */ -+ if(pCesaReqFirst != NULL) -+ { -+ mvOsFree(pCesaReqFirst); -+ pCesaReqFirst = pCesaReqLast = NULL; -+ pCesaReqEmpty = pCesaReqProcess = NULL; -+ cesaQueueDepth = cesaReqResources = 0; -+ } -+ /* Free SA database */ -+ if(pCesaSAD != NULL) -+ { -+ mvOsFree(pCesaSAD); -+ pCesaSAD = NULL; -+ cesaMaxSA = 0; -+ } -+ MV_REG_WRITE( MV_CESA_CFG_REG, 0); -+ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); -+ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, 0); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaCryptoIvSet - Set IV value for Crypto algorithm working in CBC mode -+* -+* DESCRIPTION: -+* This function set IV value using by Crypto algorithms in CBC mode. -+* Each channel has its own IV value. -+* This function gets IV value from the caller. If no IV value passed from -+* the caller or only part of IV passed, the function will init the rest part -+* of IV value (or the whole IV) by random value. -+* -+* INPUT: -+* MV_U8* pIV - Pointer to IV value supplied by user. If pIV==NULL -+* the function will generate random IV value. -+* int ivSize - size (in bytes) of IV provided by user. If ivSize is -+* smaller than maximum IV size, the function will complete -+* IV by random value. -+* -+* RETURN: -+* MV_OK - Success -+* Other - Fail -+* -+*******************************************************************************/ -+MV_STATUS mvCesaCryptoIvSet(MV_U8* pIV, int ivSize) -+{ -+ MV_U8* pSramIV; -+#if defined(MV646xx) -+ mvOsPrintf("mvCesaCryptoIvSet: ERR. shouldn't use this call on MV64660\n"); -+#endif -+ pSramIV = cesaSramVirtPtr->cryptoIV; -+ if(ivSize > MV_CESA_MAX_IV_LENGTH) -+ { -+ mvOsPrintf("mvCesaCryptoIvSet: ivSize (%d) is too large\n", ivSize); -+ ivSize = MV_CESA_MAX_IV_LENGTH; -+ } -+ if(pIV != NULL) -+ { -+ memcpy(pSramIV, pIV, ivSize); -+ ivSize = MV_CESA_MAX_IV_LENGTH - ivSize; -+ pSramIV += ivSize; -+ } -+ -+ while(ivSize > 0) -+ { -+ int size, mv_random = mvOsRand(); -+ -+ size = MV_MIN(ivSize, sizeof(mv_random)); -+ memcpy(pSramIV, (void*)&mv_random, size); -+ -+ pSramIV += size; -+ ivSize -= size; -+ } -+/* -+ mvOsCacheFlush(NULL, cesaSramVirtPtr->cryptoIV, -+ MV_CESA_MAX_IV_LENGTH); -+ mvOsCacheInvalidate(NULL, cesaSramVirtPtr->cryptoIV, -+ MV_CESA_MAX_IV_LENGTH); -+*/ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaSessionOpen - Open new uni-directional crypto session -+* -+* DESCRIPTION: -+* This function open new session. -+* -+* INPUT: -+* MV_CESA_OPEN_SESSION *pSession - pointer to new session input parameters -+* -+* OUTPUT: -+* short *pSid - session ID, should be used for all future -+* requests over this session. -+* -+* RETURN: -+* MV_OK - Session opend successfully. -+* MV_FULL - All sessions are in use, no free place in -+* SA database. -+* MV_BAD_PARAM - One of session input parameters is invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvCesaSessionOpen(MV_CESA_OPEN_SESSION *pSession, short* pSid) -+{ -+ short sid; -+ MV_U32 config = 0; -+ int digestSize; -+ -+ cesaStats.openedCount++; -+ -+ /* Find free entry in SAD */ -+ for(sid=0; sidoperation >= MV_CESA_MAX_OPERATION) -+ { -+ mvOsPrintf("mvCesaSessionOpen: Unexpected operation %d\n", -+ pSession->operation); -+ return MV_BAD_PARAM; -+ } -+ config |= (pSession->operation << MV_CESA_OPERATION_OFFSET); -+ -+ if( (pSession->direction != MV_CESA_DIR_ENCODE) && -+ (pSession->direction != MV_CESA_DIR_DECODE) ) -+ { -+ mvOsPrintf("mvCesaSessionOpen: Unexpected direction %d\n", -+ pSession->direction); -+ return MV_BAD_PARAM; -+ } -+ config |= (pSession->direction << MV_CESA_DIRECTION_BIT); -+ /* Clear SA entry */ -+ /* memset(&pCesaSAD[sid], 0, sizeof(pCesaSAD[sid])); */ -+ -+ /* Check AUTH parameters and update SA entry */ -+ if(pSession->operation != MV_CESA_CRYPTO_ONLY) -+ { -+ /* For HMAC (MD5 and SHA1) - Maximum Key size is 64 bytes */ -+ if( (pSession->macMode == MV_CESA_MAC_HMAC_MD5) || -+ (pSession->macMode == MV_CESA_MAC_HMAC_SHA1) ) -+ { -+ if(pSession->macKeyLength > MV_CESA_MAX_MAC_KEY_LENGTH) -+ { -+ mvOsPrintf("mvCesaSessionOpen: macKeyLength %d is too large\n", -+ pSession->macKeyLength); -+ return MV_BAD_PARAM; -+ } -+ mvCesaHmacIvGet(pSession->macMode, pSession->macKey, pSession->macKeyLength, -+ pCesaSAD[sid].pSramSA->macInnerIV, -+ pCesaSAD[sid].pSramSA->macOuterIV); -+ pCesaSAD[sid].macKeyLength = pSession->macKeyLength; -+ } -+ switch(pSession->macMode) -+ { -+ case MV_CESA_MAC_MD5: -+ case MV_CESA_MAC_HMAC_MD5: -+ digestSize = MV_CESA_MD5_DIGEST_SIZE; -+ break; -+ -+ case MV_CESA_MAC_SHA1: -+ case MV_CESA_MAC_HMAC_SHA1: -+ digestSize = MV_CESA_SHA1_DIGEST_SIZE; -+ break; -+ -+ default: -+ mvOsPrintf("mvCesaSessionOpen: Unexpected macMode %d\n", -+ pSession->macMode); -+ return MV_BAD_PARAM; -+ } -+ config |= (pSession->macMode << MV_CESA_MAC_MODE_OFFSET); -+ -+ /* Supported digest sizes: MD5 - 16 bytes (128 bits), */ -+ /* SHA1 - 20 bytes (160 bits) or 12 bytes (96 bits) for both */ -+ if( (pSession->digestSize != digestSize) && (pSession->digestSize != 12)) -+ { -+ mvOsPrintf("mvCesaSessionOpen: Unexpected digest size %d\n", -+ pSession->digestSize); -+ mvOsPrintf("\t Valid values [bytes]: MD5-16, SHA1-20, Both-12\n"); -+ return MV_BAD_PARAM; -+ } -+ pCesaSAD[sid].digestSize = pSession->digestSize; -+ -+ if(pCesaSAD[sid].digestSize == 12) -+ { -+ /* Set MV_CESA_MAC_DIGEST_SIZE_BIT if digest size is 96 bits */ -+ config |= (MV_CESA_MAC_DIGEST_96B << MV_CESA_MAC_DIGEST_SIZE_BIT); -+ } -+ } -+ -+ /* Check CRYPTO parameters and update SA entry */ -+ if(pSession->operation != MV_CESA_MAC_ONLY) -+ { -+ switch(pSession->cryptoAlgorithm) -+ { -+ case MV_CESA_CRYPTO_DES: -+ pCesaSAD[sid].cryptoKeyLength = MV_CESA_DES_KEY_LENGTH; -+ pCesaSAD[sid].cryptoBlockSize = MV_CESA_DES_BLOCK_SIZE; -+ break; -+ -+ case MV_CESA_CRYPTO_3DES: -+ pCesaSAD[sid].cryptoKeyLength = MV_CESA_3DES_KEY_LENGTH; -+ pCesaSAD[sid].cryptoBlockSize = MV_CESA_DES_BLOCK_SIZE; -+ /* Only EDE mode is supported */ -+ config |= (MV_CESA_CRYPTO_3DES_EDE << -+ MV_CESA_CRYPTO_3DES_MODE_BIT); -+ break; -+ -+ case MV_CESA_CRYPTO_AES: -+ switch(pSession->cryptoKeyLength) -+ { -+ case 16: -+ pCesaSAD[sid].cryptoKeyLength = MV_CESA_AES_128_KEY_LENGTH; -+ config |= (MV_CESA_CRYPTO_AES_KEY_128 << -+ MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET); -+ break; -+ -+ case 24: -+ pCesaSAD[sid].cryptoKeyLength = MV_CESA_AES_192_KEY_LENGTH; -+ config |= (MV_CESA_CRYPTO_AES_KEY_192 << -+ MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET); -+ break; -+ -+ case 32: -+ default: -+ pCesaSAD[sid].cryptoKeyLength = MV_CESA_AES_256_KEY_LENGTH; -+ config |= (MV_CESA_CRYPTO_AES_KEY_256 << -+ MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET); -+ break; -+ } -+ pCesaSAD[sid].cryptoBlockSize = MV_CESA_AES_BLOCK_SIZE; -+ break; -+ -+ default: -+ mvOsPrintf("mvCesaSessionOpen: Unexpected cryptoAlgorithm %d\n", -+ pSession->cryptoAlgorithm); -+ return MV_BAD_PARAM; -+ } -+ config |= (pSession->cryptoAlgorithm << MV_CESA_CRYPTO_ALG_OFFSET); -+ -+ if(pSession->cryptoKeyLength != pCesaSAD[sid].cryptoKeyLength) -+ { -+ mvOsPrintf("cesaSessionOpen: Wrong CryptoKeySize %d != %d\n", -+ pSession->cryptoKeyLength, pCesaSAD[sid].cryptoKeyLength); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Copy Crypto key */ -+ if( (pSession->cryptoAlgorithm == MV_CESA_CRYPTO_AES) && -+ (pSession->direction == MV_CESA_DIR_DECODE)) -+ { -+ /* Crypto Key for AES decode is computed from original key material */ -+ /* and depend on cryptoKeyLength (128/192/256 bits) */ -+ aesMakeKey(pCesaSAD[sid].pSramSA->cryptoKey, pSession->cryptoKey, -+ pSession->cryptoKeyLength*8, MV_CESA_AES_BLOCK_SIZE*8); -+ } -+ else -+ { -+ /*panic("mvCesaSessionOpen2");*/ -+ memcpy(pCesaSAD[sid].pSramSA->cryptoKey, pSession->cryptoKey, -+ pCesaSAD[sid].cryptoKeyLength); -+ -+ } -+ -+ switch(pSession->cryptoMode) -+ { -+ case MV_CESA_CRYPTO_ECB: -+ pCesaSAD[sid].cryptoIvSize = 0; -+ break; -+ -+ case MV_CESA_CRYPTO_CBC: -+ pCesaSAD[sid].cryptoIvSize = pCesaSAD[sid].cryptoBlockSize; -+ break; -+ -+ case MV_CESA_CRYPTO_CTR: -+ /* Supported only for AES algorithm */ -+ if(pSession->cryptoAlgorithm != MV_CESA_CRYPTO_AES) -+ { -+ mvOsPrintf("mvCesaSessionOpen: CRYPTO CTR mode supported for AES only\n"); -+ return MV_BAD_PARAM; -+ } -+ pCesaSAD[sid].cryptoIvSize = 0; -+ pCesaSAD[sid].ctrMode = 1; -+ /* Replace to ECB mode for HW */ -+ pSession->cryptoMode = MV_CESA_CRYPTO_ECB; -+ break; -+ -+ default: -+ mvOsPrintf("mvCesaSessionOpen: Unexpected cryptoMode %d\n", -+ pSession->cryptoMode); -+ return MV_BAD_PARAM; -+ } -+ -+ config |= (pSession->cryptoMode << MV_CESA_CRYPTO_MODE_BIT); -+ } -+ pCesaSAD[sid].config = config; -+ -+ mvOsCacheFlush(NULL, pCesaSAD[sid].pSramSA, sizeof(MV_CESA_SRAM_SA)); -+ if(pSid != NULL) -+ *pSid = sid; -+ -+ pCesaSAD[sid].valid = 1; -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaSessionClose - Close active crypto session -+* -+* DESCRIPTION: -+* This function closes existing session -+* -+* INPUT: -+* short sid - Unique identifier of the session to be closed -+* -+* RETURN: -+* MV_OK - Session closed successfully. -+* MV_BAD_PARAM - Session identifier is out of valid range. -+* MV_NOT_FOUND - There is no active session with such ID. -+* -+*******************************************************************************/ -+MV_STATUS mvCesaSessionClose(short sid) -+{ -+ cesaStats.closedCount++; -+ -+ if(sid >= cesaMaxSA) -+ { -+ mvOsPrintf("CESA Error: sid (%d) is too big\n", sid); -+ return MV_BAD_PARAM; -+ } -+ if(pCesaSAD[sid].valid == 0) -+ { -+ mvOsPrintf("CESA Warning: Session (sid=%d) is invalid\n", sid); -+ return MV_NOT_FOUND; -+ } -+ if(cesaLastSid == sid) -+ cesaLastSid = -1; -+ -+ pCesaSAD[sid].valid = 0; -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaAction - Perform crypto operation -+* -+* DESCRIPTION: -+* This function set new CESA request FIFO queue for further HW processing. -+* The function checks request parameters before set new request to the queue. -+* If one of the CESA channels is ready for processing the request will be -+* passed to HW. When request processing is finished the CESA interrupt will -+* be generated by HW. The caller should call mvCesaReadyGet() function to -+* complete request processing and get result. -+* -+* INPUT: -+* MV_CESA_COMMAND *pCmd - pointer to new CESA request. -+* It includes pointers to Source and Destination -+* buffers, session identifier get from -+* mvCesaSessionOpen() function, pointer to caller -+* private data and all needed crypto parameters. -+* -+* RETURN: -+* MV_OK - request successfully added to request queue -+* and will be processed. -+* MV_NO_MORE - request successfully added to request queue and will -+* be processed, but request queue became Full and next -+* request will not be accepted. -+* MV_NO_RESOURCE - request queue is FULL and the request can not -+* be processed. -+* MV_OUT_OF_CPU_MEM - memory allocation needed for request processing is -+* failed. Request can not be processed. -+* MV_NOT_ALLOWED - This mixed request (CRYPTO+MAC) can not be processed -+* as one request and should be splitted for two requests: -+* CRYPTO_ONLY and MAC_ONLY. -+* MV_BAD_PARAM - One of the request parameters is out of valid range. -+* The request can not be processed. -+* -+*******************************************************************************/ -+MV_STATUS mvCesaAction (MV_CESA_COMMAND *pCmd) -+{ -+ MV_STATUS status; -+ MV_CESA_REQ* pReq = pCesaReqEmpty; -+ int sid = pCmd->sessionId; -+ MV_CESA_SA* pSA = &pCesaSAD[sid]; -+#if (MV_CESA_VERSION >= 3) -+ MV_CESA_REQ* pFromReq; -+ MV_CESA_REQ* pToReq; -+#endif -+ cesaStats.reqCount++; -+ -+ /* Check that the request queue is not FULL */ -+ if(cesaReqResources == 0) -+ return MV_NO_RESOURCE; -+ -+ if( (sid >= cesaMaxSA) || (!pSA->valid) ) -+ { -+ mvOsPrintf("CESA Action Error: Session sid=%d is INVALID\n", sid); -+ return MV_BAD_PARAM; -+ } -+ pSA->count++; -+ -+ if(pSA->ctrMode) -+ { -+ /* AES in CTR mode can't be mixed with Authentication */ -+ if( (pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ mvOsPrintf("mvCesaAction : CRYPTO CTR mode can't be mixed with AUTH\n"); -+ return MV_NOT_ALLOWED; -+ } -+ /* All other request parameters should not be checked because key stream */ -+ /* (not user data) processed by AES HW engine */ -+ pReq->pOrgCmd = pCmd; -+ /* Allocate temporary pCmd structure for Key stream */ -+ pCmd = mvCesaCtrModeInit(); -+ if(pCmd == NULL) -+ return MV_OUT_OF_CPU_MEM; -+ -+ /* Prepare Key stream */ -+ mvCesaCtrModePrepare(pCmd, pReq->pOrgCmd); -+ pReq->fixOffset = 0; -+ } -+ else -+ { -+ /* Check request parameters and calculae fixOffset */ -+ status = mvCesaParamCheck(pSA, pCmd, &pReq->fixOffset); -+ if(status != MV_OK) -+ { -+ return status; -+ } -+ } -+ pReq->pCmd = pCmd; -+ -+ /* Check if the packet need fragmentation */ -+ if(pCmd->pSrc->mbufSize <= sizeof(cesaSramVirtPtr->buf) ) -+ { -+ /* request size is smaller than single buffer size */ -+ pReq->fragMode = MV_CESA_FRAG_NONE; -+ -+ /* Prepare NOT fragmented packets */ -+ status = mvCesaReqProcess(pReq); -+ if(status != MV_OK) -+ { -+ mvOsPrintf("CesaReady: ReqProcess error: pReq=%p, status=0x%x\n", -+ pReq, status); -+ } -+#if (MV_CESA_VERSION >= 3) -+ pReq->frags.numFrag = 1; -+#endif -+ } -+ else -+ { -+ MV_U8 frag = 0; -+ -+ /* request size is larger than buffer size - needs fragmentation */ -+ -+ /* Check restrictions for processing fragmented packets */ -+ status = mvCesaFragParamCheck(pSA, pCmd); -+ if(status != MV_OK) -+ return status; -+ -+ pReq->fragMode = MV_CESA_FRAG_FIRST; -+ pReq->frags.nextFrag = 0; -+ -+ /* Prepare Process Fragmented packets */ -+ while(pReq->fragMode != MV_CESA_FRAG_LAST) -+ { -+ if(frag >= MV_CESA_MAX_REQ_FRAGS) -+ { -+ mvOsPrintf("mvCesaAction Error: Too large request frag=%d\n", frag); -+ return MV_OUT_OF_CPU_MEM; -+ } -+ status = mvCesaFragReqProcess(pReq, frag); -+ if(status == MV_OK) { -+#if (MV_CESA_VERSION >= 3) -+ if(frag) { -+ pReq->dma[frag-1].pDmaLast->phyNextDescPtr = -+ MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, pReq->dma[frag].pDmaFirst)); -+ mvOsCacheFlush(NULL, pReq->dma[frag-1].pDmaLast, sizeof(MV_DMA_DESC)); -+ } -+#endif -+ frag++; -+ } -+ } -+ pReq->frags.numFrag = frag; -+#if (MV_CESA_VERSION >= 3) -+ if(chainReqNum) { -+ chainReqNum += pReq->frags.numFrag; -+ if(chainReqNum >= MAX_CESA_CHAIN_LENGTH) -+ chainReqNum = MAX_CESA_CHAIN_LENGTH; -+ } -+#endif -+ } -+ -+ pReq->state = MV_CESA_PENDING; -+ -+ pCesaReqEmpty = MV_CESA_REQ_NEXT_PTR(pReq); -+ cesaReqResources -= 1; -+ -+/* #ifdef CESA_DEBUG */ -+ if( (cesaQueueDepth - cesaReqResources) > cesaStats.maxReqCount) -+ cesaStats.maxReqCount = (cesaQueueDepth - cesaReqResources); -+/* #endif CESA_DEBUG */ -+ -+ cesaLastSid = sid; -+ -+#if (MV_CESA_VERSION >= 3) -+ /* Are we within chain bounderies and follows the first request ? */ -+ if((chainReqNum > 0) && (chainReqNum < MAX_CESA_CHAIN_LENGTH)) { -+ if(chainIndex) { -+ pFromReq = MV_CESA_REQ_PREV_PTR(pReq); -+ pToReq = pReq; -+ pReq->state = MV_CESA_CHAIN; -+ /* assume concatenating is possible */ -+ pFromReq->dma[pFromReq->frags.numFrag-1].pDmaLast->phyNextDescPtr = -+ MV_32BIT_LE(mvCesaVirtToPhys(&pToReq->dmaDescBuf, pToReq->dma[0].pDmaFirst)); -+ mvOsCacheFlush(NULL, pFromReq->dma[pFromReq->frags.numFrag-1].pDmaLast, sizeof(MV_DMA_DESC)); -+ -+ /* align active & next pointers */ -+ if(pNextActiveChain->state != MV_CESA_PENDING) -+ pEndCurrChain = pNextActiveChain = MV_CESA_REQ_NEXT_PTR(pReq); -+ } -+ else { /* we have only one chain, start new one */ -+ chainReqNum = 0; -+ chainIndex++; -+ /* align active & next pointers */ -+ if(pNextActiveChain->state != MV_CESA_PENDING) -+ pEndCurrChain = pNextActiveChain = pReq; -+ } -+ } -+ else { -+ /* In case we concatenate full chain */ -+ if(chainReqNum == MAX_CESA_CHAIN_LENGTH) { -+ chainIndex++; -+ if(pNextActiveChain->state != MV_CESA_PENDING) -+ pEndCurrChain = pNextActiveChain = pReq; -+ chainReqNum = 0; -+ } -+ -+ pReq = pCesaReqProcess; -+ if(pReq->state == MV_CESA_PENDING) { -+ pNextActiveChain = pReq; -+ pEndCurrChain = MV_CESA_REQ_NEXT_PTR(pReq); -+ /* Start Process new request */ -+ mvCesaReqProcessStart(pReq); -+ } -+ } -+ -+ chainReqNum++; -+ -+ if((chainIndex < MAX_CESA_CHAIN_LENGTH) && (chainReqNum > cesaStats.maxChainUsage)) -+ cesaStats.maxChainUsage = chainReqNum; -+ -+#else -+ -+ /* Check status of CESA channels and process requests if possible */ -+ pReq = pCesaReqProcess; -+ if(pReq->state == MV_CESA_PENDING) -+ { -+ /* Start Process new request */ -+ mvCesaReqProcessStart(pReq); -+ } -+#endif -+ /* If request queue became FULL - return MV_NO_MORE */ -+ if(cesaReqResources == 0) -+ return MV_NO_MORE; -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvCesaReadyGet - Get crypto request that processing is finished -+* -+* DESCRIPTION: -+* This function complete request processing and return ready request to -+* caller. To don't miss interrupts the caller must call this function -+* while MV_OK or MV_TERMINATE values returned. -+* -+* INPUT: -+* MV_U32 chanMap - map of CESA channels finished thier job -+* accordingly with CESA Cause register. -+* MV_CESA_RESULT* pResult - pointer to structure contains information -+* about ready request. It includes pointer to -+* user private structure "pReqPrv", session identifier -+* for this request "sessionId" and return code. -+* Return code set to MV_FAIL if calculated digest value -+* on decode direction is different than digest value -+* in the packet. -+* -+* RETURN: -+* MV_OK - Success, ready request is returned. -+* MV_NOT_READY - Next request is not ready yet. New interrupt will -+* be generated for futher request processing. -+* MV_EMPTY - There is no more request for processing. -+* MV_BUSY - Fragmented request is not ready yet. -+* MV_TERMINATE - Call this function once more to complete processing -+* of fragmented request. -+* -+*******************************************************************************/ -+MV_STATUS mvCesaReadyGet(MV_CESA_RESULT* pResult) -+{ -+ MV_STATUS status, readyStatus = MV_NOT_READY; -+ MV_U32 statusReg; -+ MV_CESA_REQ* pReq; -+ MV_CESA_SA* pSA; -+ -+#if (MV_CESA_VERSION >= 3) -+ if(isFirstReq == MV_TRUE) { -+ if(chainIndex == 0) -+ chainReqNum = 0; -+ -+ isFirstReq = MV_FALSE; -+ -+ if(pNextActiveChain->state == MV_CESA_PENDING) { -+ /* Start request Process */ -+ mvCesaReqProcessStart(pNextActiveChain); -+ pEndCurrChain = pNextActiveChain; -+ if(chainIndex > 0) -+ chainIndex--; -+ /* Update pNextActiveChain to next chain head */ -+ while(pNextActiveChain->state == MV_CESA_CHAIN) -+ pNextActiveChain = MV_CESA_REQ_NEXT_PTR(pNextActiveChain); -+ } -+ } -+ -+ /* Check if there are more processed requests - can we remove pEndCurrChain ??? */ -+ if(pCesaReqProcess == pEndCurrChain) { -+ isFirstReq = MV_TRUE; -+ pEndCurrChain = pNextActiveChain; -+#else -+ if(pCesaReqProcess->state != MV_CESA_PROCESS) { -+#endif -+ return MV_EMPTY; -+ } -+ -+#ifdef CESA_DEBUG -+ statusReg = MV_REG_READ(MV_CESA_STATUS_REG); -+ if( statusReg & MV_CESA_STATUS_ACTIVE_MASK ) -+ { -+ mvOsPrintf("mvCesaReadyGet: Not Ready, Status = 0x%x\n", statusReg); -+ cesaStats.notReadyCount++; -+ return MV_NOT_READY; -+ } -+#endif /* CESA_DEBUG */ -+ -+ cesaStats.readyCount++; -+ -+ pReq = pCesaReqProcess; -+ pSA = &pCesaSAD[pReq->pCmd->sessionId]; -+ -+ pResult->retCode = MV_OK; -+ if(pReq->fragMode != MV_CESA_FRAG_NONE) -+ { -+ MV_U8* pNewDigest; -+ int frag; -+#if (MV_CESA_VERSION >= 3) -+ pReq->frags.nextFrag = 1; -+ while(pReq->frags.nextFrag <= pReq->frags.numFrag) { -+#endif -+ frag = (pReq->frags.nextFrag - 1); -+ -+ /* Restore DMA descriptor list */ -+ pReq->dma[frag].pDmaLast->phyNextDescPtr = -+ MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, &pReq->dma[frag].pDmaLast[1])); -+ pReq->dma[frag].pDmaLast = NULL; -+ -+ /* Special processing for finished fragmented request */ -+ if(pReq->frags.nextFrag >= pReq->frags.numFrag) -+ { -+ mvCesaMbufCacheUnmap(pReq->pCmd->pDst, 0, pReq->pCmd->pDst->mbufSize); -+ -+ /* Fragmented packet is ready */ -+ if( (pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ int macDataSize = pReq->pCmd->macLength - pReq->frags.macSize; -+ -+ if(macDataSize != 0) -+ { -+ /* Calculate all other blocks by SW */ -+ mvCesaFragAuthComplete(pReq, pSA, macDataSize); -+ } -+ -+ /* Copy new digest from SRAM to the Destination buffer */ -+ pNewDigest = cesaSramVirtPtr->buf + pReq->frags.newDigestOffset; -+ status = mvCesaCopyToMbuf(pNewDigest, pReq->pCmd->pDst, -+ pReq->pCmd->digestOffset, pSA->digestSize); -+ -+ /* For decryption: Compare new digest value with original one */ -+ if((pSA->config & MV_CESA_DIRECTION_MASK) == -+ (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) -+ { -+ if( memcmp(pNewDigest, pReq->frags.orgDigest, pSA->digestSize) != 0) -+ { -+/* -+ mvOsPrintf("Digest error: chan=%d, newDigest=%p, orgDigest=%p, status = 0x%x\n", -+ chan, pNewDigest, pReq->frags.orgDigest, MV_REG_READ(MV_CESA_STATUS_REG)); -+*/ -+ /* Signiture verification is failed */ -+ pResult->retCode = MV_FAIL; -+ } -+ } -+ } -+ readyStatus = MV_OK; -+ } -+#if (MV_CESA_VERSION >= 3) -+ pReq->frags.nextFrag++; -+ } -+#endif -+ } -+ else -+ { -+ mvCesaMbufCacheUnmap(pReq->pCmd->pDst, 0, pReq->pCmd->pDst->mbufSize); -+ -+ /* Restore DMA descriptor list */ -+ pReq->dma[0].pDmaLast->phyNextDescPtr = -+ MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, &pReq->dma[0].pDmaLast[1])); -+ pReq->dma[0].pDmaLast = NULL; -+ if( ((pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) && -+ ((pSA->config & MV_CESA_DIRECTION_MASK) == -+ (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) ) -+ { -+ /* For AUTH on decode : Check Digest result in Status register */ -+ statusReg = MV_REG_READ(MV_CESA_STATUS_REG); -+ if(statusReg & MV_CESA_STATUS_DIGEST_ERR_MASK) -+ { -+/* -+ mvOsPrintf("Digest error: chan=%d, status = 0x%x\n", -+ chan, statusReg); -+*/ -+ /* Signiture verification is failed */ -+ pResult->retCode = MV_FAIL; -+ } -+ } -+ readyStatus = MV_OK; -+ } -+ -+ if(readyStatus == MV_OK) -+ { -+ /* If Request is ready - Prepare pResult structure */ -+ pResult->pReqPrv = pReq->pCmd->pReqPrv; -+ pResult->sessionId = pReq->pCmd->sessionId; -+ -+ pReq->state = MV_CESA_IDLE; -+ pCesaReqProcess = MV_CESA_REQ_NEXT_PTR(pReq); -+ cesaReqResources++; -+ -+ if(pSA->ctrMode) -+ { -+ /* For AES CTR mode - complete processing and free allocated resources */ -+ mvCesaCtrModeComplete(pReq->pOrgCmd, pReq->pCmd); -+ mvCesaCtrModeFinish(pReq->pCmd); -+ pReq->pOrgCmd = NULL; -+ } -+ } -+ -+#if (MV_CESA_VERSION < 3) -+ if(pCesaReqProcess->state == MV_CESA_PROCESS) -+ { -+ /* Start request Process */ -+ mvCesaReqProcessStart(pCesaReqProcess); -+ if(readyStatus == MV_NOT_READY) -+ readyStatus = MV_BUSY; -+ } -+ else if(pCesaReqProcess != pCesaReqEmpty) -+ { -+ /* Start process new request from the queue */ -+ mvCesaReqProcessStart(pCesaReqProcess); -+ } -+#endif -+ return readyStatus; -+} -+ -+/***************** Functions to work with CESA_MBUF structure ******************/ -+ -+/******************************************************************************* -+* mvCesaMbufOffset - Locate offset in the Mbuf structure -+* -+* DESCRIPTION: -+* This function locates offset inside Multi-Bufeer structure. -+* It get fragment number and place in the fragment where the offset -+* is located. -+* -+* -+* INPUT: -+* MV_CESA_MBUF* pMbuf - Pointer to multi-buffer structure -+* int offset - Offset from the beginning of the data presented by -+* the Mbuf structure. -+* -+* OUTPUT: -+* int* pBufOffset - Offset from the beginning of the fragment where -+* the offset is located. -+* -+* RETURN: -+* int - Number of fragment, where the offset is located\ -+* -+*******************************************************************************/ -+int mvCesaMbufOffset(MV_CESA_MBUF* pMbuf, int offset, int* pBufOffset) -+{ -+ int frag = 0; -+ -+ while(offset > 0) -+ { -+ if(frag >= pMbuf->numFrags) -+ { -+ mvOsPrintf("mvCesaMbufOffset: Error: frag (%d) > numFrags (%d)\n", -+ frag, pMbuf->numFrags); -+ return MV_INVALID; -+ } -+ if(offset < pMbuf->pFrags[frag].bufSize) -+ { -+ break; -+ } -+ offset -= pMbuf->pFrags[frag].bufSize; -+ frag++; -+ } -+ if(pBufOffset != NULL) -+ *pBufOffset = offset; -+ -+ return frag; -+} -+ -+/******************************************************************************* -+* mvCesaCopyFromMbuf - Copy data from the Mbuf structure to continuous buffer -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_U8* pDstBuf - Pointer to continuous buffer, where data is -+* copied to. -+* MV_CESA_MBUF* pSrcMbuf - Pointer to multi-buffer structure where data is -+* copied from. -+* int offset - Offset in the Mbuf structure where located first -+* byte of data should be copied. -+* int size - Size of data should be copied -+* -+* RETURN: -+* MV_OK - Success, all data is copied successfully. -+* MV_OUT_OF_RANGE - Failed, offset is out of Multi-buffer data range. -+* No data is copied. -+* MV_EMPTY - Multi-buffer structure has not enough data to copy -+* Data from the offset to end of Mbuf data is copied. -+* -+*******************************************************************************/ -+MV_STATUS mvCesaCopyFromMbuf(MV_U8* pDstBuf, MV_CESA_MBUF* pSrcMbuf, -+ int offset, int size) -+{ -+ int frag, fragOffset, bufSize; -+ MV_U8* pBuf; -+ -+ if(size == 0) -+ return MV_OK; -+ -+ frag = mvCesaMbufOffset(pSrcMbuf, offset, &fragOffset); -+ if(frag == MV_INVALID) -+ { -+ mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); -+ return MV_OUT_OF_RANGE; -+ } -+ -+ bufSize = pSrcMbuf->pFrags[frag].bufSize - fragOffset; -+ pBuf = pSrcMbuf->pFrags[frag].bufVirtPtr + fragOffset; -+ while(MV_TRUE) -+ { -+ if(size <= bufSize) -+ { -+ memcpy(pDstBuf, pBuf, size); -+ return MV_OK; -+ } -+ memcpy(pDstBuf, pBuf, bufSize); -+ size -= bufSize; -+ frag++; -+ pDstBuf += bufSize; -+ if(frag >= pSrcMbuf->numFrags) -+ break; -+ -+ bufSize = pSrcMbuf->pFrags[frag].bufSize; -+ pBuf = pSrcMbuf->pFrags[frag].bufVirtPtr; -+ } -+ mvOsPrintf("mvCesaCopyFromMbuf: Mbuf is EMPTY - %d bytes isn't copied\n", -+ size); -+ return MV_EMPTY; -+} -+ -+/******************************************************************************* -+* mvCesaCopyToMbuf - Copy data from continuous buffer to the Mbuf structure -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_U8* pSrcBuf - Pointer to continuous buffer, where data is -+* copied from. -+* MV_CESA_MBUF* pDstMbuf - Pointer to multi-buffer structure where data is -+* copied to. -+* int offset - Offset in the Mbuf structure where located first -+* byte of data should be copied. -+* int size - Size of data should be copied -+* -+* RETURN: -+* MV_OK - Success, all data is copied successfully. -+* MV_OUT_OF_RANGE - Failed, offset is out of Multi-buffer data range. -+* No data is copied. -+* MV_FULL - Multi-buffer structure has not enough place to copy -+* all data. Data from the offset to end of Mbuf data -+* is copied. -+* -+*******************************************************************************/ -+MV_STATUS mvCesaCopyToMbuf(MV_U8* pSrcBuf, MV_CESA_MBUF* pDstMbuf, -+ int offset, int size) -+{ -+ int frag, fragOffset, bufSize; -+ MV_U8* pBuf; -+ -+ if(size == 0) -+ return MV_OK; -+ -+ frag = mvCesaMbufOffset(pDstMbuf, offset, &fragOffset); -+ if(frag == MV_INVALID) -+ { -+ mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); -+ return MV_OUT_OF_RANGE; -+ } -+ -+ bufSize = pDstMbuf->pFrags[frag].bufSize - fragOffset; -+ pBuf = pDstMbuf->pFrags[frag].bufVirtPtr + fragOffset; -+ while(MV_TRUE) -+ { -+ if(size <= bufSize) -+ { -+ memcpy(pBuf, pSrcBuf, size); -+ return MV_OK; -+ } -+ memcpy(pBuf, pSrcBuf, bufSize); -+ size -= bufSize; -+ frag++; -+ pSrcBuf += bufSize; -+ if(frag >= pDstMbuf->numFrags) -+ break; -+ -+ bufSize = pDstMbuf->pFrags[frag].bufSize; -+ pBuf = pDstMbuf->pFrags[frag].bufVirtPtr; -+ } -+ mvOsPrintf("mvCesaCopyToMbuf: Mbuf is FULL - %d bytes isn't copied\n", -+ size); -+ return MV_FULL; -+} -+ -+/******************************************************************************* -+* mvCesaMbufCopy - Copy data from one Mbuf structure to the other Mbuf structure -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* -+* MV_CESA_MBUF* pDstMbuf - Pointer to multi-buffer structure where data is -+* copied to. -+* int dstMbufOffset - Offset in the dstMbuf structure where first byte -+* of data should be copied to. -+* MV_CESA_MBUF* pSrcMbuf - Pointer to multi-buffer structure where data is -+* copied from. -+* int srcMbufOffset - Offset in the srcMbuf structure where first byte -+* of data should be copied from. -+* int size - Size of data should be copied -+* -+* RETURN: -+* MV_OK - Success, all data is copied successfully. -+* MV_OUT_OF_RANGE - Failed, srcMbufOffset or dstMbufOffset is out of -+* srcMbuf or dstMbuf structure correspondently. -+* No data is copied. -+* MV_BAD_SIZE - srcMbuf or dstMbuf structure is too small to copy -+* all data. Partial data is copied -+* -+*******************************************************************************/ -+MV_STATUS mvCesaMbufCopy(MV_CESA_MBUF* pMbufDst, int dstMbufOffset, -+ MV_CESA_MBUF* pMbufSrc, int srcMbufOffset, int size) -+{ -+ int srcFrag, dstFrag, srcSize, dstSize, srcOffset, dstOffset; -+ int copySize; -+ MV_U8 *pSrc, *pDst; -+ -+ if(size == 0) -+ return MV_OK; -+ -+ srcFrag = mvCesaMbufOffset(pMbufSrc, srcMbufOffset, &srcOffset); -+ if(srcFrag == MV_INVALID) -+ { -+ mvOsPrintf("CESA srcMbuf Error: offset (%d) out of range\n", srcMbufOffset); -+ return MV_OUT_OF_RANGE; -+ } -+ pSrc = pMbufSrc->pFrags[srcFrag].bufVirtPtr + srcOffset; -+ srcSize = pMbufSrc->pFrags[srcFrag].bufSize - srcOffset; -+ -+ dstFrag = mvCesaMbufOffset(pMbufDst, dstMbufOffset, &dstOffset); -+ if(dstFrag == MV_INVALID) -+ { -+ mvOsPrintf("CESA dstMbuf Error: offset (%d) out of range\n", dstMbufOffset); -+ return MV_OUT_OF_RANGE; -+ } -+ pDst = pMbufDst->pFrags[dstFrag].bufVirtPtr + dstOffset; -+ dstSize = pMbufDst->pFrags[dstFrag].bufSize - dstOffset; -+ -+ while(size > 0) -+ { -+ copySize = MV_MIN(srcSize, dstSize); -+ if(size <= copySize) -+ { -+ memcpy(pDst, pSrc, size); -+ return MV_OK; -+ } -+ memcpy(pDst, pSrc, copySize); -+ size -= copySize; -+ srcSize -= copySize; -+ dstSize -= copySize; -+ -+ if(srcSize == 0) -+ { -+ srcFrag++; -+ if(srcFrag >= pMbufSrc->numFrags) -+ break; -+ -+ pSrc = pMbufSrc->pFrags[srcFrag].bufVirtPtr; -+ srcSize = pMbufSrc->pFrags[srcFrag].bufSize; -+ } -+ -+ if(dstSize == 0) -+ { -+ dstFrag++; -+ if(dstFrag >= pMbufDst->numFrags) -+ break; -+ -+ pDst = pMbufDst->pFrags[dstFrag].bufVirtPtr; -+ dstSize = pMbufDst->pFrags[dstFrag].bufSize; -+ } -+ } -+ mvOsPrintf("mvCesaMbufCopy: BAD size - %d bytes isn't copied\n", -+ size); -+ -+ return MV_BAD_SIZE; -+} -+ -+static MV_STATUS mvCesaMbufCacheUnmap(MV_CESA_MBUF* pMbuf, int offset, int size) -+{ -+ int frag, fragOffset, bufSize; -+ MV_U8* pBuf; -+ -+ if(size == 0) -+ return MV_OK; -+ -+ frag = mvCesaMbufOffset(pMbuf, offset, &fragOffset); -+ if(frag == MV_INVALID) -+ { -+ mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); -+ return MV_OUT_OF_RANGE; -+ } -+ -+ bufSize = pMbuf->pFrags[frag].bufSize - fragOffset; -+ pBuf = pMbuf->pFrags[frag].bufVirtPtr + fragOffset; -+ while(MV_TRUE) -+ { -+ if(size <= bufSize) -+ { -+ mvOsCacheUnmap(NULL, mvOsIoVirtToPhy(NULL, pBuf), size); -+ return MV_OK; -+ } -+ -+ mvOsCacheUnmap(NULL, mvOsIoVirtToPhy(NULL, pBuf), bufSize); -+ size -= bufSize; -+ frag++; -+ if(frag >= pMbuf->numFrags) -+ break; -+ -+ bufSize = pMbuf->pFrags[frag].bufSize; -+ pBuf = pMbuf->pFrags[frag].bufVirtPtr; -+ } -+ mvOsPrintf("%s: Mbuf is FULL - %d bytes isn't Unmapped\n", -+ __FUNCTION__, size); -+ return MV_FULL; -+} -+ -+ -+/*************************************** Local Functions ******************************/ -+ -+/******************************************************************************* -+* mvCesaFragReqProcess - Process fragmented request -+* -+* DESCRIPTION: -+* This function processes a fragment of fragmented request (First, Middle or Last) -+* -+* -+* INPUT: -+* MV_CESA_REQ* pReq - Pointer to the request in the request queue. -+* -+* RETURN: -+* MV_OK - The fragment is successfully passed to HW for processing. -+* MV_TERMINATE - Means, that HW finished its work on this packet and no more -+* interrupts will be generated for this request. -+* Function mvCesaReadyGet() must be called to complete request -+* processing and get request result. -+* -+*******************************************************************************/ -+static MV_STATUS mvCesaFragReqProcess(MV_CESA_REQ* pReq, MV_U8 frag) -+{ -+ int i, copySize, cryptoDataSize, macDataSize, sid; -+ int cryptoIvOffset, digestOffset; -+ MV_U32 config; -+ MV_CESA_COMMAND* pCmd = pReq->pCmd; -+ MV_CESA_SA* pSA; -+ MV_CESA_MBUF* pMbuf; -+ MV_DMA_DESC* pDmaDesc = pReq->dma[frag].pDmaFirst; -+ MV_U8* pSramBuf = cesaSramVirtPtr->buf; -+ int macTotalLen = 0; -+ int fixOffset, cryptoOffset, macOffset; -+ -+ cesaStats.fragCount++; -+ -+ sid = pReq->pCmd->sessionId; -+ -+ pSA = &pCesaSAD[sid]; -+ -+ cryptoIvOffset = digestOffset = 0; -+ i = macDataSize = 0; -+ cryptoDataSize = 0; -+ -+ /* First fragment processing */ -+ if(pReq->fragMode == MV_CESA_FRAG_FIRST) -+ { -+ /* pReq->frags monitors processing of fragmented request between fragments */ -+ pReq->frags.bufOffset = 0; -+ pReq->frags.cryptoSize = 0; -+ pReq->frags.macSize = 0; -+ -+ config = pSA->config | (MV_CESA_FRAG_FIRST << MV_CESA_FRAG_MODE_OFFSET); -+ -+ /* fixOffset can be not equal to zero only for FIRST fragment */ -+ fixOffset = pReq->fixOffset; -+ /* For FIRST fragment crypto and mac offsets are taken from pCmd */ -+ cryptoOffset = pCmd->cryptoOffset; -+ macOffset = pCmd->macOffset; -+ -+ copySize = sizeof(cesaSramVirtPtr->buf) - pReq->fixOffset; -+ -+ /* Find fragment size: Must meet all requirements for CRYPTO and MAC -+ * cryptoDataSize - size of data will be encrypted/decrypted in this fragment -+ * macDataSize - size of data will be signed/verified in this fragment -+ * copySize - size of data will be copied from srcMbuf to SRAM and -+ * back to dstMbuf for this fragment -+ */ -+ mvCesaFragSizeFind(pSA, pReq, cryptoOffset, macOffset, -+ ©Size, &cryptoDataSize, &macDataSize); -+ -+ if( (pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) -+ { -+ /* CryptoIV special processing */ -+ if( (pSA->config & MV_CESA_CRYPTO_MODE_MASK) == -+ (MV_CESA_CRYPTO_CBC << MV_CESA_CRYPTO_MODE_BIT) ) -+ { -+ /* In CBC mode for encode direction when IV from user */ -+ if( (pCmd->ivFromUser) && -+ ((pSA->config & MV_CESA_DIRECTION_MASK) == -+ (MV_CESA_DIR_ENCODE << MV_CESA_DIRECTION_BIT)) ) -+ { -+ -+ /* For Crypto Encode in CBC mode HW always takes IV from SRAM IVPointer, -+ * (not from IVBufPointer). So when ivFromUser==1, we should copy IV from user place -+ * in the buffer to SRAM IVPointer -+ */ -+ i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->cryptoIV, &pDmaDesc[i], -+ MV_FALSE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); -+ } -+ -+ /* Special processing when IV is not located in the first fragment */ -+ if(pCmd->ivOffset > (copySize - pSA->cryptoIvSize)) -+ { -+ /* Prepare dummy place for cryptoIV in SRAM */ -+ cryptoIvOffset = cesaSramVirtPtr->tempCryptoIV - mvCesaSramAddrGet(); -+ -+ /* For Decryption: Copy IV value from pCmd->ivOffset to Special SRAM place */ -+ if((pSA->config & MV_CESA_DIRECTION_MASK) == -+ (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) -+ { -+ i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->tempCryptoIV, &pDmaDesc[i], -+ MV_FALSE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); -+ } -+ else -+ { -+ /* For Encryption when IV is NOT from User: */ -+ /* Copy IV from SRAM to buffer (pCmd->ivOffset) */ -+ if(pCmd->ivFromUser == 0) -+ { -+ /* copy IV value from cryptoIV to Buffer (pCmd->ivOffset) */ -+ i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->cryptoIV, &pDmaDesc[i], -+ MV_TRUE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); -+ } -+ } -+ } -+ else -+ { -+ cryptoIvOffset = pCmd->ivOffset; -+ } -+ } -+ } -+ -+ if( (pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ /* MAC digest special processing on Decode direction */ -+ if((pSA->config & MV_CESA_DIRECTION_MASK) == -+ (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) -+ { -+ /* Save digest from pCmd->digestOffset */ -+ mvCesaCopyFromMbuf(pReq->frags.orgDigest, -+ pCmd->pSrc, pCmd->digestOffset, pSA->digestSize); -+ -+ /* If pCmd->digestOffset is not located on the first */ -+ if(pCmd->digestOffset > (copySize - pSA->digestSize)) -+ { -+ MV_U8 digestZero[MV_CESA_MAX_DIGEST_SIZE]; -+ -+ /* Set zeros to pCmd->digestOffset (DRAM) */ -+ memset(digestZero, 0, MV_CESA_MAX_DIGEST_SIZE); -+ mvCesaCopyToMbuf(digestZero, pCmd->pSrc, pCmd->digestOffset, pSA->digestSize); -+ -+ /* Prepare dummy place for digest in SRAM */ -+ digestOffset = cesaSramVirtPtr->tempDigest - mvCesaSramAddrGet(); -+ } -+ else -+ { -+ digestOffset = pCmd->digestOffset; -+ } -+ } -+ } -+ /* Update SA in SRAM */ -+ if(cesaLastSid != sid) -+ { -+ mvCesaSramSaUpdate(sid, &pDmaDesc[i]); -+ i++; -+ } -+ -+ pReq->fragMode = MV_CESA_FRAG_MIDDLE; -+ } -+ else -+ { -+ /* Continue fragment */ -+ fixOffset = 0; -+ cryptoOffset = 0; -+ macOffset = 0; -+ if( (pCmd->pSrc->mbufSize - pReq->frags.bufOffset) <= sizeof(cesaSramVirtPtr->buf)) -+ { -+ /* Last fragment */ -+ config = pSA->config | (MV_CESA_FRAG_LAST << MV_CESA_FRAG_MODE_OFFSET); -+ pReq->fragMode = MV_CESA_FRAG_LAST; -+ copySize = pCmd->pSrc->mbufSize - pReq->frags.bufOffset; -+ -+ if( (pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ macDataSize = pCmd->macLength - pReq->frags.macSize; -+ -+ /* If pCmd->digestOffset is not located on last fragment */ -+ if(pCmd->digestOffset < pReq->frags.bufOffset) -+ { -+ /* Prepare dummy place for digest in SRAM */ -+ digestOffset = cesaSramVirtPtr->tempDigest - mvCesaSramAddrGet(); -+ } -+ else -+ { -+ digestOffset = pCmd->digestOffset - pReq->frags.bufOffset; -+ } -+ pReq->frags.newDigestOffset = digestOffset; -+ macTotalLen = pCmd->macLength; -+ -+ /* HW can't calculate the Digest correctly for fragmented packets -+ * in the following cases: -+ * - MV88F5182 || -+ * - MV88F5181L when total macLength more that 16 Kbytes || -+ * - total macLength more that 64 Kbytes -+ */ -+ if( (mvCtrlModelGet() == MV_5182_DEV_ID) || -+ ( (mvCtrlModelGet() == MV_5181_DEV_ID) && -+ (mvCtrlRevGet() >= MV_5181L_A0_REV) && -+ (pCmd->macLength >= (1 << 14)) ) ) -+ { -+ return MV_TERMINATE; -+ } -+ } -+ if( (pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ cryptoDataSize = pCmd->cryptoLength - pReq->frags.cryptoSize; -+ } -+ -+ /* cryptoIvOffset - don't care */ -+ } -+ else -+ { -+ /* WA for MV88F5182 SHA1 and MD5 fragmentation mode */ -+ if( (mvCtrlModelGet() == MV_5182_DEV_ID) && -+ (((pSA->config & MV_CESA_MAC_MODE_MASK) == -+ (MV_CESA_MAC_MD5 << MV_CESA_MAC_MODE_OFFSET)) || -+ ((pSA->config & MV_CESA_MAC_MODE_MASK) == -+ (MV_CESA_MAC_SHA1 << MV_CESA_MAC_MODE_OFFSET))) ) -+ { -+ pReq->frags.newDigestOffset = cesaSramVirtPtr->tempDigest - mvCesaSramAddrGet(); -+ pReq->fragMode = MV_CESA_FRAG_LAST; -+ -+ return MV_TERMINATE; -+ } -+ /* Middle fragment */ -+ config = pSA->config | (MV_CESA_FRAG_MIDDLE << MV_CESA_FRAG_MODE_OFFSET); -+ copySize = sizeof(cesaSramVirtPtr->buf); -+ /* digestOffset and cryptoIvOffset - don't care */ -+ -+ /* Find fragment size */ -+ mvCesaFragSizeFind(pSA, pReq, cryptoOffset, macOffset, -+ ©Size, &cryptoDataSize, &macDataSize); -+ } -+ } -+ /********* Prepare DMA descriptors to copy from pSrc to SRAM *********/ -+ pMbuf = pCmd->pSrc; -+ i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], -+ MV_FALSE, pReq->frags.bufOffset, copySize, pCmd->skipFlush); -+ -+ /* Prepare CESA descriptor to copy from DRAM to SRAM by DMA */ -+ mvCesaSramDescrBuild(config, frag, -+ cryptoOffset + fixOffset, cryptoIvOffset + fixOffset, -+ cryptoDataSize, macOffset + fixOffset, -+ digestOffset + fixOffset, macDataSize, macTotalLen, -+ pReq, &pDmaDesc[i]); -+ i++; -+ -+ /* Add special descriptor Ownership for CPU */ -+ pDmaDesc[i].byteCnt = 0; -+ pDmaDesc[i].phySrcAdd = 0; -+ pDmaDesc[i].phyDestAdd = 0; -+ i++; -+ -+ /********* Prepare DMA descriptors to copy from SRAM to pDst *********/ -+ pMbuf = pCmd->pDst; -+ i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], -+ MV_TRUE, pReq->frags.bufOffset, copySize, pCmd->skipFlush); -+ -+ /* Next field of Last DMA descriptor must be NULL */ -+ pDmaDesc[i-1].phyNextDescPtr = 0; -+ pReq->dma[frag].pDmaLast = &pDmaDesc[i-1]; -+ mvOsCacheFlush(NULL, pReq->dma[frag].pDmaFirst, -+ i*sizeof(MV_DMA_DESC)); -+ -+ /*mvCesaDebugDescriptor(&cesaSramVirtPtr->desc[frag]);*/ -+ -+ pReq->frags.bufOffset += copySize; -+ pReq->frags.cryptoSize += cryptoDataSize; -+ pReq->frags.macSize += macDataSize; -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvCesaReqProcess - Process regular (Non-fragmented) request -+* -+* DESCRIPTION: -+* This function processes the whole (not fragmented) request -+* -+* INPUT: -+* MV_CESA_REQ* pReq - Pointer to the request in the request queue. -+* -+* RETURN: -+* MV_OK - The request is successfully passed to HW for processing. -+* Other - Failure. The request will not be processed -+* -+*******************************************************************************/ -+static MV_STATUS mvCesaReqProcess(MV_CESA_REQ* pReq) -+{ -+ MV_CESA_MBUF *pMbuf; -+ MV_DMA_DESC *pDmaDesc; -+ MV_U8 *pSramBuf; -+ int sid, i, fixOffset; -+ MV_CESA_SA *pSA; -+ MV_CESA_COMMAND *pCmd = pReq->pCmd; -+ -+ cesaStats.procCount++; -+ -+ sid = pCmd->sessionId; -+ pSA = &pCesaSAD[sid]; -+ pDmaDesc = pReq->dma[0].pDmaFirst; -+ pSramBuf = cesaSramVirtPtr->buf; -+ fixOffset = pReq->fixOffset; -+ -+/* -+ mvOsPrintf("mvCesaReqProcess: sid=%d, pSA=%p, pDmaDesc=%p, pSramBuf=%p\n", -+ sid, pSA, pDmaDesc, pSramBuf); -+*/ -+ i = 0; -+ -+ /* Crypto IV Special processing in CBC mode for Encryption direction */ -+ if( ((pSA->config & MV_CESA_OPERATION_MASK) != (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) && -+ ((pSA->config & MV_CESA_CRYPTO_MODE_MASK) == (MV_CESA_CRYPTO_CBC << MV_CESA_CRYPTO_MODE_BIT)) && -+ ((pSA->config & MV_CESA_DIRECTION_MASK) == (MV_CESA_DIR_ENCODE << MV_CESA_DIRECTION_BIT)) && -+ (pCmd->ivFromUser) ) -+ { -+ /* For Crypto Encode in CBC mode HW always takes IV from SRAM IVPointer, -+ * (not from IVBufPointer). So when ivFromUser==1, we should copy IV from user place -+ * in the buffer to SRAM IVPointer -+ */ -+ i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->cryptoIV, &pDmaDesc[i], -+ MV_FALSE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); -+ } -+ -+ /* Update SA in SRAM */ -+ if(cesaLastSid != sid) -+ { -+ mvCesaSramSaUpdate(sid, &pDmaDesc[i]); -+ i++; -+ } -+ -+ /********* Prepare DMA descriptors to copy from pSrc to SRAM *********/ -+ pMbuf = pCmd->pSrc; -+ i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], -+ MV_FALSE, 0, pMbuf->mbufSize, pCmd->skipFlush); -+ -+ /* Prepare Security Accelerator descriptor to SRAM words 0 - 7 */ -+ mvCesaSramDescrBuild(pSA->config, 0, pCmd->cryptoOffset + fixOffset, -+ pCmd->ivOffset + fixOffset, pCmd->cryptoLength, -+ pCmd->macOffset + fixOffset, pCmd->digestOffset + fixOffset, -+ pCmd->macLength, pCmd->macLength, pReq, &pDmaDesc[i]); -+ i++; -+ -+ /* Add special descriptor Ownership for CPU */ -+ pDmaDesc[i].byteCnt = 0; -+ pDmaDesc[i].phySrcAdd = 0; -+ pDmaDesc[i].phyDestAdd = 0; -+ i++; -+ -+ /********* Prepare DMA descriptors to copy from SRAM to pDst *********/ -+ pMbuf = pCmd->pDst; -+ i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], -+ MV_TRUE, 0, pMbuf->mbufSize, pCmd->skipFlush); -+ -+ /* Next field of Last DMA descriptor must be NULL */ -+ pDmaDesc[i-1].phyNextDescPtr = 0; -+ pReq->dma[0].pDmaLast = &pDmaDesc[i-1]; -+ mvOsCacheFlush(NULL, pReq->dma[0].pDmaFirst, i*sizeof(MV_DMA_DESC)); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvCesaSramDescrBuild - Set CESA descriptor in SRAM -+* -+* DESCRIPTION: -+* This function builds CESA descriptor in SRAM from all Command parameters -+* -+* -+* INPUT: -+* int chan - CESA channel uses the descriptor -+* MV_U32 config - 32 bits of WORD_0 in CESA descriptor structure -+* int cryptoOffset - Offset from the beginning of SRAM buffer where -+* data for encryption/decription is started. -+* int ivOffset - Offset of crypto IV from the SRAM base. Valid only -+* for first fragment. -+* int cryptoLength - Size (in bytes) of data for encryption/descryption -+* operation on this fragment. -+* int macOffset - Offset from the beginning of SRAM buffer where -+* data for Authentication is started -+* int digestOffset - Offset from the beginning of SRAM buffer where -+* digest is located. Valid for first and last fragments. -+* int macLength - Size (in bytes) of data for Authentication -+* operation on this fragment. -+* int macTotalLen - Toatl size (in bytes) of data for Authentication -+* operation on the whole request (packet). Valid for -+* last fragment only. -+* -+* RETURN: None -+* -+*******************************************************************************/ -+static void mvCesaSramDescrBuild(MV_U32 config, int frag, -+ int cryptoOffset, int ivOffset, int cryptoLength, -+ int macOffset, int digestOffset, int macLength, -+ int macTotalLen, MV_CESA_REQ* pReq, MV_DMA_DESC* pDmaDesc) -+{ -+ MV_CESA_DESC* pCesaDesc = &pReq->pCesaDesc[frag]; -+ MV_CESA_DESC* pSramDesc = pSramDesc = &cesaSramVirtPtr->desc; -+ MV_U16 sramBufOffset = (MV_U16)((MV_U8*)cesaSramVirtPtr->buf - mvCesaSramAddrGet()); -+ -+ pCesaDesc->config = MV_32BIT_LE(config); -+ -+ if( (config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ /* word 1 */ -+ pCesaDesc->cryptoSrcOffset = MV_16BIT_LE(sramBufOffset + cryptoOffset); -+ pCesaDesc->cryptoDstOffset = MV_16BIT_LE(sramBufOffset + cryptoOffset); -+ /* word 2 */ -+ pCesaDesc->cryptoDataLen = MV_16BIT_LE(cryptoLength); -+ /* word 3 */ -+ pCesaDesc->cryptoKeyOffset = MV_16BIT_LE((MV_U16)(cesaSramVirtPtr->sramSA.cryptoKey - -+ mvCesaSramAddrGet())); -+ /* word 4 */ -+ pCesaDesc->cryptoIvOffset = MV_16BIT_LE((MV_U16)(cesaSramVirtPtr->cryptoIV - -+ mvCesaSramAddrGet())); -+ pCesaDesc->cryptoIvBufOffset = MV_16BIT_LE(sramBufOffset + ivOffset); -+ } -+ -+ if( (config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ /* word 5 */ -+ pCesaDesc->macSrcOffset = MV_16BIT_LE(sramBufOffset + macOffset); -+ pCesaDesc->macTotalLen = MV_16BIT_LE(macTotalLen); -+ -+ /* word 6 */ -+ pCesaDesc->macDigestOffset = MV_16BIT_LE(sramBufOffset + digestOffset); -+ pCesaDesc->macDataLen = MV_16BIT_LE(macLength); -+ -+ /* word 7 */ -+ pCesaDesc->macInnerIvOffset = MV_16BIT_LE((MV_U16)(cesaSramVirtPtr->sramSA.macInnerIV - -+ mvCesaSramAddrGet())); -+ pCesaDesc->macOuterIvOffset = MV_16BIT_LE((MV_U16)(cesaSramVirtPtr->sramSA.macOuterIV - -+ mvCesaSramAddrGet())); -+ } -+ /* Prepare DMA descriptor to CESA descriptor from DRAM to SRAM */ -+ pDmaDesc->phySrcAdd = MV_32BIT_LE(mvCesaVirtToPhys(&pReq->cesaDescBuf, pCesaDesc)); -+ pDmaDesc->phyDestAdd = MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (MV_U8*)pSramDesc)); -+ pDmaDesc->byteCnt = MV_32BIT_LE(sizeof(MV_CESA_DESC) | BIT31); -+ -+ /* flush Source buffer */ -+ mvOsCacheFlush(NULL, pCesaDesc, sizeof(MV_CESA_DESC)); -+} -+ -+/******************************************************************************* -+* mvCesaSramSaUpdate - Move required SA information to SRAM if needed. -+* -+* DESCRIPTION: -+* Copy to SRAM values of the required SA. -+* -+* -+* INPUT: -+* short sid - Session ID needs SRAM Cache update -+* MV_DMA_DESC *pDmaDesc - Pointer to DMA descriptor used to -+* copy SA values from DRAM to SRAM. -+* -+* RETURN: -+* MV_OK - Cache entry for this SA copied to SRAM. -+* MV_NO_CHANGE - Cache entry for this SA already exist in SRAM -+* -+*******************************************************************************/ -+static INLINE void mvCesaSramSaUpdate(short sid, MV_DMA_DESC *pDmaDesc) -+{ -+ MV_CESA_SA *pSA = &pCesaSAD[sid]; -+ -+ /* Prepare DMA descriptor to Copy CACHE_SA from SA database in DRAM to SRAM */ -+ pDmaDesc->byteCnt = MV_32BIT_LE(sizeof(MV_CESA_SRAM_SA) | BIT31); -+ pDmaDesc->phySrcAdd = MV_32BIT_LE(mvCesaVirtToPhys(&cesaSramSaBuf, pSA->pSramSA)); -+ pDmaDesc->phyDestAdd = -+ MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (MV_U8*)&cesaSramVirtPtr->sramSA)); -+ -+ /* Source buffer is already flushed during OpenSession*/ -+ /*mvOsCacheFlush(NULL, &pSA->sramSA, sizeof(MV_CESA_SRAM_SA));*/ -+} -+ -+/******************************************************************************* -+* mvCesaDmaCopyPrepare - prepare DMA descriptor list to copy data presented by -+* Mbuf structure from DRAM to SRAM -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_CESA_MBUF* pMbuf - pointer to Mbuf structure contains request -+* data in DRAM -+* MV_U8* pSramBuf - pointer to buffer in SRAM where data should -+* be copied to. -+* MV_DMA_DESC* pDmaDesc - pointer to first DMA descriptor for this copy. -+* The function set number of DMA descriptors needed -+* to copy the copySize bytes from Mbuf. -+* MV_BOOL isToMbuf - Copy direction. -+* MV_TRUE means copy from SRAM buffer to Mbuf in DRAM. -+* MV_FALSE means copy from Mbuf in DRAM to SRAM buffer. -+* int offset - Offset in the Mbuf structure that copy should be -+* started from. -+* int copySize - Size of data should be copied. -+* -+* RETURN: -+* int - number of DMA descriptors used for the copy. -+* -+*******************************************************************************/ -+#ifndef MV_NETBSD -+static INLINE int mvCesaDmaCopyPrepare(MV_CESA_MBUF* pMbuf, MV_U8* pSramBuf, -+ MV_DMA_DESC* pDmaDesc, MV_BOOL isToMbuf, -+ int offset, int copySize, MV_BOOL skipFlush) -+{ -+ int bufOffset, bufSize, size, frag, i; -+ MV_U8* pBuf; -+ -+ i = 0; -+ -+ /* Calculate start place for copy: fragment number and offset in the fragment */ -+ frag = mvCesaMbufOffset(pMbuf, offset, &bufOffset); -+ bufSize = pMbuf->pFrags[frag].bufSize - bufOffset; -+ pBuf = pMbuf->pFrags[frag].bufVirtPtr + bufOffset; -+ -+ /* Size accumulate total copy size */ -+ size = 0; -+ -+ /* Create DMA lists to copy mBuf from pSrc to SRAM */ -+ while(size < copySize) -+ { -+ /* Find copy size for each DMA descriptor */ -+ bufSize = MV_MIN(bufSize, (copySize - size)); -+ pDmaDesc[i].byteCnt = MV_32BIT_LE(bufSize | BIT31); -+ if(isToMbuf) -+ { -+ pDmaDesc[i].phyDestAdd = MV_32BIT_LE(mvOsIoVirtToPhy(NULL, pBuf)); -+ pDmaDesc[i].phySrcAdd = -+ MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (pSramBuf + size))); -+ /* invalidate the buffer */ -+ if(skipFlush == MV_FALSE) -+ mvOsCacheInvalidate(NULL, pBuf, bufSize); -+ } -+ else -+ { -+ pDmaDesc[i].phySrcAdd = MV_32BIT_LE(mvOsIoVirtToPhy(NULL, pBuf)); -+ pDmaDesc[i].phyDestAdd = -+ MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (pSramBuf + size))); -+ /* flush the buffer */ -+ if(skipFlush == MV_FALSE) -+ mvOsCacheFlush(NULL, pBuf, bufSize); -+ } -+ -+ /* Count number of used DMA descriptors */ -+ i++; -+ size += bufSize; -+ -+ /* go to next fragment in the Mbuf */ -+ frag++; -+ pBuf = pMbuf->pFrags[frag].bufVirtPtr; -+ bufSize = pMbuf->pFrags[frag].bufSize; -+ } -+ return i; -+} -+#else /* MV_NETBSD */ -+static int mvCesaDmaCopyPrepare(MV_CESA_MBUF* pMbuf, MV_U8* pSramBuf, -+ MV_DMA_DESC* pDmaDesc, MV_BOOL isToMbuf, -+ int offset, int copySize, MV_BOOL skipFlush) -+{ -+ int bufOffset, bufSize, thisSize, size, frag, i; -+ MV_ULONG bufPhys, sramPhys; -+ MV_U8* pBuf; -+ -+ /* -+ * Calculate start place for copy: fragment number and offset in -+ * the fragment -+ */ -+ frag = mvCesaMbufOffset(pMbuf, offset, &bufOffset); -+ -+ /* -+ * Get SRAM physical address only once. We can update it in-place -+ * as we build the descriptor chain. -+ */ -+ sramPhys = mvCesaSramVirtToPhys(NULL, pSramBuf); -+ -+ /* -+ * 'size' accumulates total copy size, 'i' counts desccriptors. -+ */ -+ size = i = 0; -+ -+ /* Create DMA lists to copy mBuf from pSrc to SRAM */ -+ while (size < copySize) { -+ /* -+ * Calculate # of bytes to copy from the current fragment, -+ * and the pointer to the start of data -+ */ -+ bufSize = pMbuf->pFrags[frag].bufSize - bufOffset; -+ pBuf = pMbuf->pFrags[frag].bufVirtPtr + bufOffset; -+ bufOffset = 0; /* First frag may be non-zero */ -+ frag++; -+ -+ /* -+ * As long as there is data in the current fragment... -+ */ -+ while (bufSize > 0) { -+ /* -+ * Ensure we don't cross an MMU page boundary. -+ * XXX: This is NetBSD-specific, but it is a -+ * quick and dirty way to fix the problem. -+ * A true HAL would rely on the OS-specific -+ * driver to do this... -+ */ -+ thisSize = PAGE_SIZE - -+ (((MV_ULONG)pBuf) & (PAGE_SIZE - 1)); -+ thisSize = MV_MIN(bufSize, thisSize); -+ /* -+ * Make sure we don't copy more than requested -+ */ -+ if (thisSize > (copySize - size)) { -+ thisSize = copySize - size; -+ bufSize = 0; -+ } -+ -+ /* -+ * Physicall address of this fragment -+ */ -+ bufPhys = MV_32BIT_LE(mvOsIoVirtToPhy(NULL, pBuf)); -+ -+ /* -+ * Set up the descriptor -+ */ -+ pDmaDesc[i].byteCnt = MV_32BIT_LE(thisSize | BIT31); -+ if(isToMbuf) { -+ pDmaDesc[i].phyDestAdd = bufPhys; -+ pDmaDesc[i].phySrcAdd = MV_32BIT_LE(sramPhys); -+ /* invalidate the buffer */ -+ if(skipFlush == MV_FALSE) -+ mvOsCacheInvalidate(NULL, pBuf, thisSize); -+ } else { -+ pDmaDesc[i].phySrcAdd = bufPhys; -+ pDmaDesc[i].phyDestAdd = MV_32BIT_LE(sramPhys); -+ /* flush the buffer */ -+ if(skipFlush == MV_FALSE) -+ mvOsCacheFlush(NULL, pBuf, thisSize); -+ } -+ -+ pDmaDesc[i].phyNextDescPtr = -+ MV_32BIT_LE(mvOsIoVirtToPhy(NULL,(&pDmaDesc[i+1]))); -+ -+ /* flush the DMA desc */ -+ mvOsCacheFlush(NULL, &pDmaDesc[i], sizeof(MV_DMA_DESC)); -+ -+ /* Update state */ -+ bufSize -= thisSize; -+ sramPhys += thisSize; -+ pBuf += thisSize; -+ size += thisSize; -+ i++; -+ } -+ } -+ -+ return i; -+} -+#endif /* MV_NETBSD */ -+/******************************************************************************* -+* mvCesaHmacIvGet - Calculate Inner and Outter values from HMAC key -+* -+* DESCRIPTION: -+* This function calculate Inner and Outer values used for HMAC algorithm. -+* This operation allows improve performance fro the whole HMAC processing. -+* -+* INPUT: -+* MV_CESA_MAC_MODE macMode - Authentication mode: HMAC_MD5 or HMAC_SHA1. -+* unsigned char key[] - Pointer to HMAC key. -+* int keyLength - Size of HMAC key (maximum 64 bytes) -+* -+* OUTPUT: -+* unsigned char innerIV[] - HASH(key^inner) -+* unsigned char outerIV[] - HASH(key^outter) -+* -+* RETURN: None -+* -+*******************************************************************************/ -+static void mvCesaHmacIvGet(MV_CESA_MAC_MODE macMode, unsigned char key[], int keyLength, -+ unsigned char innerIV[], unsigned char outerIV[]) -+{ -+ unsigned char inner[MV_CESA_MAX_MAC_KEY_LENGTH]; -+ unsigned char outer[MV_CESA_MAX_MAC_KEY_LENGTH]; -+ int i, digestSize = 0; -+#if defined(MV_CPU_LE) || defined(MV_PPC) -+ MV_U32 swapped32, val32, *pVal32; -+#endif -+ for(i=0; ipFrags[frag].bufVirtPtr + fragOffset; -+ size = pMbuf->pFrags[frag].bufSize - fragOffset; -+ -+ /* Complete Inner part */ -+ while(macLeftSize > 0) -+ { -+ if(macLeftSize <= size) -+ { -+ mvSHA1Update(&ctx, pData, macLeftSize); -+ break; -+ } -+ mvSHA1Update(&ctx, pData, size); -+ macLeftSize -= size; -+ frag++; -+ pData = pMbuf->pFrags[frag].bufVirtPtr; -+ size = pMbuf->pFrags[frag].bufSize; -+ } -+ mvSHA1Final(pDigest, &ctx); -+/* -+ mvOsPrintf("mvCesaFragSha1Complete: pOuterIV=%p, macLeftSize=%d, macTotalSize=%d\n", -+ pOuterIV, macLeftSize, macTotalSize); -+ mvDebugMemDump(pDigest, MV_CESA_SHA1_DIGEST_SIZE, 1); -+*/ -+ -+ if(pOuterIV != NULL) -+ { -+ /* If HMAC - Complete Outer part */ -+ for(i=0; ipFrags[frag].bufVirtPtr + fragOffset; -+ size = pMbuf->pFrags[frag].bufSize - fragOffset; -+ -+ /* Complete Inner part */ -+ while(macLeftSize > 0) -+ { -+ if(macLeftSize <= size) -+ { -+ mvMD5Update(&ctx, pData, macLeftSize); -+ break; -+ } -+ mvMD5Update(&ctx, pData, size); -+ macLeftSize -= size; -+ frag++; -+ pData = pMbuf->pFrags[frag].bufVirtPtr; -+ size = pMbuf->pFrags[frag].bufSize; -+ } -+ mvMD5Final(pDigest, &ctx); -+ -+/* -+ mvOsPrintf("mvCesaFragMd5Complete: pOuterIV=%p, macLeftSize=%d, macTotalSize=%d\n", -+ pOuterIV, macLeftSize, macTotalSize); -+ mvDebugMemDump(pDigest, MV_CESA_MD5_DIGEST_SIZE, 1); -+*/ -+ if(pOuterIV != NULL) -+ { -+ /* Complete Outer part */ -+ for(i=0; ipCmd; -+ MV_U8* pDigest; -+ MV_CESA_MAC_MODE macMode; -+ MV_U8* pOuterIV = NULL; -+ -+ /* Copy data from Source fragment to Destination */ -+ if(pCmd->pSrc != pCmd->pDst) -+ { -+ mvCesaMbufCopy(pCmd->pDst, pReq->frags.bufOffset, -+ pCmd->pSrc, pReq->frags.bufOffset, macDataSize); -+ } -+ -+/* -+ mvCesaCopyFromMbuf(cesaSramVirtPtr->buf[0], pCmd->pSrc, pReq->frags.bufOffset, macDataSize); -+ mvCesaCopyToMbuf(cesaSramVirtPtr->buf[0], pCmd->pDst, pReq->frags.bufOffset, macDataSize); -+*/ -+ pDigest = (mvCesaSramAddrGet() + pReq->frags.newDigestOffset); -+ -+ macMode = (pSA->config & MV_CESA_MAC_MODE_MASK) >> MV_CESA_MAC_MODE_OFFSET; -+/* -+ mvOsPrintf("macDataSize=%d, macLength=%d, digestOffset=%d, macMode=%d\n", -+ macDataSize, pCmd->macLength, pCmd->digestOffset, macMode); -+*/ -+ switch(macMode) -+ { -+ case MV_CESA_MAC_HMAC_MD5: -+ pOuterIV = pSA->pSramSA->macOuterIV; -+ -+ case MV_CESA_MAC_MD5: -+ mvCesaFragMd5Complete(pCmd->pDst, pReq->frags.bufOffset, pOuterIV, -+ macDataSize, pCmd->macLength, pDigest); -+ break; -+ -+ case MV_CESA_MAC_HMAC_SHA1: -+ pOuterIV = pSA->pSramSA->macOuterIV; -+ -+ case MV_CESA_MAC_SHA1: -+ mvCesaFragSha1Complete(pCmd->pDst, pReq->frags.bufOffset, pOuterIV, -+ macDataSize, pCmd->macLength, pDigest); -+ break; -+ -+ default: -+ mvOsPrintf("mvCesaFragAuthComplete: Unexpected macMode %d\n", macMode); -+ return MV_BAD_PARAM; -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaCtrModeInit - -+* -+* DESCRIPTION: -+* -+* -+* INPUT: NONE -+* -+* -+* RETURN: -+* MV_CESA_COMMAND* -+* -+*******************************************************************************/ -+static MV_CESA_COMMAND* mvCesaCtrModeInit(void) -+{ -+ MV_CESA_MBUF *pMbuf; -+ MV_U8 *pBuf; -+ MV_CESA_COMMAND *pCmd; -+ -+ pBuf = mvOsMalloc(sizeof(MV_CESA_COMMAND) + -+ sizeof(MV_CESA_MBUF) + sizeof(MV_BUF_INFO) + 100); -+ if(pBuf == NULL) -+ { -+ mvOsPrintf("mvCesaSessionOpen: Can't allocate %u bytes for CTR Mode\n", -+ sizeof(MV_CESA_COMMAND) + sizeof(MV_CESA_MBUF) + sizeof(MV_BUF_INFO) ); -+ return NULL; -+ } -+ pCmd = (MV_CESA_COMMAND*)pBuf; -+ pBuf += sizeof(MV_CESA_COMMAND); -+ -+ pMbuf = (MV_CESA_MBUF*)pBuf; -+ pBuf += sizeof(MV_CESA_MBUF); -+ -+ pMbuf->pFrags = (MV_BUF_INFO*)pBuf; -+ -+ pMbuf->numFrags = 1; -+ pCmd->pSrc = pMbuf; -+ pCmd->pDst = pMbuf; -+/* -+ mvOsPrintf("CtrModeInit: pCmd=%p, pSrc=%p, pDst=%p, pFrags=%p\n", -+ pCmd, pCmd->pSrc, pCmd->pDst, -+ pMbuf->pFrags); -+*/ -+ return pCmd; -+} -+ -+/******************************************************************************* -+* mvCesaCtrModePrepare - -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_CESA_COMMAND *pCtrModeCmd, MV_CESA_COMMAND *pCmd -+* -+* RETURN: -+* MV_STATUS -+* -+*******************************************************************************/ -+static MV_STATUS mvCesaCtrModePrepare(MV_CESA_COMMAND *pCtrModeCmd, MV_CESA_COMMAND *pCmd) -+{ -+ MV_CESA_MBUF *pMbuf; -+ MV_U8 *pBuf, *pIV; -+ MV_U32 counter, *pCounter; -+ int cryptoSize = MV_ALIGN_UP(pCmd->cryptoLength, MV_CESA_AES_BLOCK_SIZE); -+/* -+ mvOsPrintf("CtrModePrepare: pCmd=%p, pCtrSrc=%p, pCtrDst=%p, pOrgCmd=%p, pOrgSrc=%p, pOrgDst=%p\n", -+ pCmd, pCmd->pSrc, pCmd->pDst, -+ pCtrModeCmd, pCtrModeCmd->pSrc, pCtrModeCmd->pDst); -+*/ -+ pMbuf = pCtrModeCmd->pSrc; -+ -+ /* Allocate buffer for Key stream */ -+ pBuf = mvOsIoCachedMalloc(cesaOsHandle,cryptoSize, -+ &pMbuf->pFrags[0].bufPhysAddr, -+ &pMbuf->pFrags[0].memHandle); -+ if(pBuf == NULL) -+ { -+ mvOsPrintf("mvCesaCtrModePrepare: Can't allocate %d bytes\n", cryptoSize); -+ return MV_OUT_OF_CPU_MEM; -+ } -+ memset(pBuf, 0, cryptoSize); -+ mvOsCacheFlush(NULL, pBuf, cryptoSize); -+ -+ pMbuf->pFrags[0].bufVirtPtr = pBuf; -+ pMbuf->mbufSize = cryptoSize; -+ pMbuf->pFrags[0].bufSize = cryptoSize; -+ -+ pCtrModeCmd->pReqPrv = pCmd->pReqPrv; -+ pCtrModeCmd->sessionId = pCmd->sessionId; -+ -+ /* ivFromUser and ivOffset are don't care */ -+ pCtrModeCmd->cryptoOffset = 0; -+ pCtrModeCmd->cryptoLength = cryptoSize; -+ -+ /* digestOffset, macOffset and macLength are don't care */ -+ -+ mvCesaCopyFromMbuf(pBuf, pCmd->pSrc, pCmd->ivOffset, MV_CESA_AES_BLOCK_SIZE); -+ pCounter = (MV_U32*)(pBuf + (MV_CESA_AES_BLOCK_SIZE - sizeof(counter))); -+ counter = *pCounter; -+ counter = MV_32BIT_BE(counter); -+ pIV = pBuf; -+ cryptoSize -= MV_CESA_AES_BLOCK_SIZE; -+ -+ /* fill key stream */ -+ while(cryptoSize > 0) -+ { -+ pBuf += MV_CESA_AES_BLOCK_SIZE; -+ memcpy(pBuf, pIV, MV_CESA_AES_BLOCK_SIZE - sizeof(counter)); -+ pCounter = (MV_U32*)(pBuf + (MV_CESA_AES_BLOCK_SIZE - sizeof(counter))); -+ counter++; -+ *pCounter = MV_32BIT_BE(counter); -+ cryptoSize -= MV_CESA_AES_BLOCK_SIZE; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaCtrModeComplete - -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_CESA_COMMAND *pOrgCmd, MV_CESA_COMMAND *pCmd -+* -+* RETURN: -+* MV_STATUS -+* -+*******************************************************************************/ -+static MV_STATUS mvCesaCtrModeComplete(MV_CESA_COMMAND *pOrgCmd, MV_CESA_COMMAND *pCmd) -+{ -+ int srcFrag, dstFrag, srcOffset, dstOffset, keyOffset, srcSize, dstSize; -+ int cryptoSize = pCmd->cryptoLength; -+ MV_U8 *pSrc, *pDst, *pKey; -+ MV_STATUS status = MV_OK; -+/* -+ mvOsPrintf("CtrModeComplete: pCmd=%p, pCtrSrc=%p, pCtrDst=%p, pOrgCmd=%p, pOrgSrc=%p, pOrgDst=%p\n", -+ pCmd, pCmd->pSrc, pCmd->pDst, -+ pOrgCmd, pOrgCmd->pSrc, pOrgCmd->pDst); -+*/ -+ /* XOR source data with key stream to destination data */ -+ pKey = pCmd->pDst->pFrags[0].bufVirtPtr; -+ keyOffset = 0; -+ -+ if( (pOrgCmd->pSrc != pOrgCmd->pDst) && -+ (pOrgCmd->cryptoOffset > 0) ) -+ { -+ /* Copy Prefix from source buffer to destination buffer */ -+ -+ status = mvCesaMbufCopy(pOrgCmd->pDst, 0, -+ pOrgCmd->pSrc, 0, pOrgCmd->cryptoOffset); -+/* -+ status = mvCesaCopyFromMbuf(tempBuf, pOrgCmd->pSrc, -+ 0, pOrgCmd->cryptoOffset); -+ status = mvCesaCopyToMbuf(tempBuf, pOrgCmd->pDst, -+ 0, pOrgCmd->cryptoOffset); -+*/ -+ } -+ -+ srcFrag = mvCesaMbufOffset(pOrgCmd->pSrc, pOrgCmd->cryptoOffset, &srcOffset); -+ pSrc = pOrgCmd->pSrc->pFrags[srcFrag].bufVirtPtr; -+ srcSize = pOrgCmd->pSrc->pFrags[srcFrag].bufSize; -+ -+ dstFrag = mvCesaMbufOffset(pOrgCmd->pDst, pOrgCmd->cryptoOffset, &dstOffset); -+ pDst = pOrgCmd->pDst->pFrags[dstFrag].bufVirtPtr; -+ dstSize = pOrgCmd->pDst->pFrags[dstFrag].bufSize; -+ -+ while(cryptoSize > 0) -+ { -+ pDst[dstOffset] = (pSrc[srcOffset] ^ pKey[keyOffset]); -+ -+ cryptoSize--; -+ dstOffset++; -+ srcOffset++; -+ keyOffset++; -+ -+ if(srcOffset >= srcSize) -+ { -+ srcFrag++; -+ srcOffset = 0; -+ pSrc = pOrgCmd->pSrc->pFrags[srcFrag].bufVirtPtr; -+ srcSize = pOrgCmd->pSrc->pFrags[srcFrag].bufSize; -+ } -+ -+ if(dstOffset >= dstSize) -+ { -+ dstFrag++; -+ dstOffset = 0; -+ pDst = pOrgCmd->pDst->pFrags[dstFrag].bufVirtPtr; -+ dstSize = pOrgCmd->pDst->pFrags[dstFrag].bufSize; -+ } -+ } -+ -+ if(pOrgCmd->pSrc != pOrgCmd->pDst) -+ { -+ /* Copy Suffix from source buffer to destination buffer */ -+ srcOffset = pOrgCmd->cryptoOffset + pOrgCmd->cryptoLength; -+ -+ if( (pOrgCmd->pDst->mbufSize - srcOffset) > 0) -+ { -+ status = mvCesaMbufCopy(pOrgCmd->pDst, srcOffset, -+ pOrgCmd->pSrc, srcOffset, -+ pOrgCmd->pDst->mbufSize - srcOffset); -+ } -+ -+/* -+ status = mvCesaCopyFromMbuf(tempBuf, pOrgCmd->pSrc, -+ srcOffset, pOrgCmd->pSrc->mbufSize - srcOffset); -+ status = mvCesaCopyToMbuf(tempBuf, pOrgCmd->pDst, -+ srcOffset, pOrgCmd->pDst->mbufSize - srcOffset); -+*/ -+ } -+ -+ /* Free buffer used for Key stream */ -+ mvOsIoCachedFree(cesaOsHandle,pCmd->pDst->pFrags[0].bufSize, -+ pCmd->pDst->pFrags[0].bufPhysAddr, -+ pCmd->pDst->pFrags[0].bufVirtPtr, -+ pCmd->pDst->pFrags[0].memHandle); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaCtrModeFinish - -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_CESA_COMMAND* pCmd -+* -+* RETURN: -+* MV_STATUS -+* -+*******************************************************************************/ -+static void mvCesaCtrModeFinish(MV_CESA_COMMAND* pCmd) -+{ -+ mvOsFree(pCmd); -+} -+ -+/******************************************************************************* -+* mvCesaParamCheck - -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, MV_U8* pFixOffset -+* -+* RETURN: -+* MV_STATUS -+* -+*******************************************************************************/ -+static MV_STATUS mvCesaParamCheck(MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, -+ MV_U8* pFixOffset) -+{ -+ MV_U8 fixOffset = 0xFF; -+ -+ /* Check AUTH operation parameters */ -+ if( ((pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET)) ) -+ { -+ /* MAC offset should be at least 4 byte aligned */ -+ if( MV_IS_NOT_ALIGN(pCmd->macOffset, 4) ) -+ { -+ mvOsPrintf("mvCesaAction: macOffset %d must be 4 byte aligned\n", -+ pCmd->macOffset); -+ return MV_BAD_PARAM; -+ } -+ /* Digest offset must be 4 byte aligned */ -+ if( MV_IS_NOT_ALIGN(pCmd->digestOffset, 4) ) -+ { -+ mvOsPrintf("mvCesaAction: digestOffset %d must be 4 byte aligned\n", -+ pCmd->digestOffset); -+ return MV_BAD_PARAM; -+ } -+ /* In addition all offsets should be the same alignment: 8 or 4 */ -+ if(fixOffset == 0xFF) -+ { -+ fixOffset = (pCmd->macOffset % 8); -+ } -+ else -+ { -+ if( (pCmd->macOffset % 8) != fixOffset) -+ { -+ mvOsPrintf("mvCesaAction: macOffset %d mod 8 must be equal %d\n", -+ pCmd->macOffset, fixOffset); -+ return MV_BAD_PARAM; -+ } -+ } -+ if( (pCmd->digestOffset % 8) != fixOffset) -+ { -+ mvOsPrintf("mvCesaAction: digestOffset %d mod 8 must be equal %d\n", -+ pCmd->digestOffset, fixOffset); -+ return MV_BAD_PARAM; -+ } -+ } -+ /* Check CRYPTO operation parameters */ -+ if( ((pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) ) -+ { -+ /* CryptoOffset should be at least 4 byte aligned */ -+ if( MV_IS_NOT_ALIGN(pCmd->cryptoOffset, 4) ) -+ { -+ mvOsPrintf("CesaAction: cryptoOffset=%d must be 4 byte aligned\n", -+ pCmd->cryptoOffset); -+ return MV_BAD_PARAM; -+ } -+ /* cryptoLength should be the whole number of blocks */ -+ if( MV_IS_NOT_ALIGN(pCmd->cryptoLength, pSA->cryptoBlockSize) ) -+ { -+ mvOsPrintf("mvCesaAction: cryptoLength=%d must be %d byte aligned\n", -+ pCmd->cryptoLength, pSA->cryptoBlockSize); -+ return MV_BAD_PARAM; -+ } -+ if(fixOffset == 0xFF) -+ { -+ fixOffset = (pCmd->cryptoOffset % 8); -+ } -+ else -+ { -+ /* In addition all offsets should be the same alignment: 8 or 4 */ -+ if( (pCmd->cryptoOffset % 8) != fixOffset) -+ { -+ mvOsPrintf("mvCesaAction: cryptoOffset %d mod 8 must be equal %d \n", -+ pCmd->cryptoOffset, fixOffset); -+ return MV_BAD_PARAM; -+ } -+ } -+ -+ /* check for CBC mode */ -+ if(pSA->cryptoIvSize > 0) -+ { -+ /* cryptoIV must not be part of CryptoLength */ -+ if( ((pCmd->ivOffset + pSA->cryptoIvSize) > pCmd->cryptoOffset) && -+ (pCmd->ivOffset < (pCmd->cryptoOffset + pCmd->cryptoLength)) ) -+ { -+ mvOsPrintf("mvCesaFragParamCheck: cryptoIvOffset (%d) is part of cryptoLength (%d+%d)\n", -+ pCmd->ivOffset, pCmd->macOffset, pCmd->macLength); -+ return MV_BAD_PARAM; -+ } -+ -+ /* ivOffset must be 4 byte aligned */ -+ if( MV_IS_NOT_ALIGN(pCmd->ivOffset, 4) ) -+ { -+ mvOsPrintf("CesaAction: ivOffset=%d must be 4 byte aligned\n", -+ pCmd->ivOffset); -+ return MV_BAD_PARAM; -+ } -+ /* In addition all offsets should be the same alignment: 8 or 4 */ -+ if( (pCmd->ivOffset % 8) != fixOffset) -+ { -+ mvOsPrintf("mvCesaAction: ivOffset %d mod 8 must be %d\n", -+ pCmd->ivOffset, fixOffset); -+ return MV_BAD_PARAM; -+ } -+ } -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaFragParamCheck - -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd -+* -+* RETURN: -+* MV_STATUS -+* -+*******************************************************************************/ -+static MV_STATUS mvCesaFragParamCheck(MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd) -+{ -+ int offset; -+ -+ if( ((pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET)) ) -+ { -+ /* macOffset must be less that SRAM buffer size */ -+ if(pCmd->macOffset > (sizeof(cesaSramVirtPtr->buf) - MV_CESA_AUTH_BLOCK_SIZE)) -+ { -+ mvOsPrintf("mvCesaFragParamCheck: macOffset is too large (%d)\n", -+ pCmd->macOffset); -+ return MV_BAD_PARAM; -+ } -+ /* macOffset+macSize must be more than mbufSize - SRAM buffer size */ -+ if( ((pCmd->macOffset + pCmd->macLength) > pCmd->pSrc->mbufSize) || -+ ((pCmd->pSrc->mbufSize - (pCmd->macOffset + pCmd->macLength)) >= -+ sizeof(cesaSramVirtPtr->buf)) ) -+ { -+ mvOsPrintf("mvCesaFragParamCheck: macLength is too large (%d), mbufSize=%d\n", -+ pCmd->macLength, pCmd->pSrc->mbufSize); -+ return MV_BAD_PARAM; -+ } -+ } -+ -+ if( ((pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) ) -+ { -+ /* cryptoOffset must be less that SRAM buffer size */ -+ /* 4 for possible fixOffset */ -+ if( (pCmd->cryptoOffset + 4) > (sizeof(cesaSramVirtPtr->buf) - pSA->cryptoBlockSize)) -+ { -+ mvOsPrintf("mvCesaFragParamCheck: cryptoOffset is too large (%d)\n", -+ pCmd->cryptoOffset); -+ return MV_BAD_PARAM; -+ } -+ -+ /* cryptoOffset+cryptoSize must be more than mbufSize - SRAM buffer size */ -+ if( ((pCmd->cryptoOffset + pCmd->cryptoLength) > pCmd->pSrc->mbufSize) || -+ ((pCmd->pSrc->mbufSize - (pCmd->cryptoOffset + pCmd->cryptoLength)) >= -+ (sizeof(cesaSramVirtPtr->buf) - pSA->cryptoBlockSize)) ) -+ { -+ mvOsPrintf("mvCesaFragParamCheck: cryptoLength is too large (%d), mbufSize=%d\n", -+ pCmd->cryptoLength, pCmd->pSrc->mbufSize); -+ return MV_BAD_PARAM; -+ } -+ } -+ -+ /* When MAC_THEN_CRYPTO or CRYPTO_THEN_MAC */ -+ if( ((pSA->config & MV_CESA_OPERATION_MASK) == -+ (MV_CESA_MAC_THEN_CRYPTO << MV_CESA_OPERATION_OFFSET)) || -+ ((pSA->config & MV_CESA_OPERATION_MASK) == -+ (MV_CESA_CRYPTO_THEN_MAC << MV_CESA_OPERATION_OFFSET)) ) -+ { -+ if( (mvCtrlModelGet() == MV_5182_DEV_ID) || -+ ( (mvCtrlModelGet() == MV_5181_DEV_ID) && -+ (mvCtrlRevGet() >= MV_5181L_A0_REV) && -+ (pCmd->macLength >= (1 << 14)) ) ) -+ { -+ return MV_NOT_ALLOWED; -+ } -+ -+ /* abs(cryptoOffset-macOffset) must be aligned cryptoBlockSize */ -+ if(pCmd->cryptoOffset > pCmd->macOffset) -+ { -+ offset = pCmd->cryptoOffset - pCmd->macOffset; -+ } -+ else -+ { -+ offset = pCmd->macOffset - pCmd->cryptoOffset; -+ } -+ -+ if( MV_IS_NOT_ALIGN(offset, pSA->cryptoBlockSize) ) -+ { -+/* -+ mvOsPrintf("mvCesaFragParamCheck: (cryptoOffset - macOffset) must be %d byte aligned\n", -+ pSA->cryptoBlockSize); -+*/ -+ return MV_NOT_ALLOWED; -+ } -+ /* Digest must not be part of CryptoLength */ -+ if( ((pCmd->digestOffset + pSA->digestSize) > pCmd->cryptoOffset) && -+ (pCmd->digestOffset < (pCmd->cryptoOffset + pCmd->cryptoLength)) ) -+ { -+/* -+ mvOsPrintf("mvCesaFragParamCheck: digestOffset (%d) is part of cryptoLength (%d+%d)\n", -+ pCmd->digestOffset, pCmd->cryptoOffset, pCmd->cryptoLength); -+*/ -+ return MV_NOT_ALLOWED; -+ } -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCesaFragSizeFind - -+* -+* DESCRIPTION: -+* -+* -+* INPUT: -+* MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, -+* int cryptoOffset, int macOffset, -+* -+* OUTPUT: -+* int* pCopySize, int* pCryptoDataSize, int* pMacDataSize -+* -+* RETURN: -+* MV_STATUS -+* -+*******************************************************************************/ -+static void mvCesaFragSizeFind(MV_CESA_SA* pSA, MV_CESA_REQ* pReq, -+ int cryptoOffset, int macOffset, -+ int* pCopySize, int* pCryptoDataSize, int* pMacDataSize) -+{ -+ MV_CESA_COMMAND *pCmd = pReq->pCmd; -+ int cryptoDataSize, macDataSize, copySize; -+ -+ cryptoDataSize = macDataSize = 0; -+ copySize = *pCopySize; -+ -+ if( (pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ cryptoDataSize = MV_MIN( (copySize - cryptoOffset), -+ (pCmd->cryptoLength - (pReq->frags.cryptoSize + 1)) ); -+ -+ /* cryptoSize for each fragment must be the whole number of blocksSize */ -+ if( MV_IS_NOT_ALIGN(cryptoDataSize, pSA->cryptoBlockSize) ) -+ { -+ cryptoDataSize = MV_ALIGN_DOWN(cryptoDataSize, pSA->cryptoBlockSize); -+ copySize = cryptoOffset + cryptoDataSize; -+ } -+ } -+ if( (pSA->config & MV_CESA_OPERATION_MASK) != -+ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) -+ { -+ macDataSize = MV_MIN( (copySize - macOffset), -+ (pCmd->macLength - (pReq->frags.macSize + 1))); -+ -+ /* macSize for each fragment (except last) must be the whole number of blocksSize */ -+ if( MV_IS_NOT_ALIGN(macDataSize, MV_CESA_AUTH_BLOCK_SIZE) ) -+ { -+ macDataSize = MV_ALIGN_DOWN(macDataSize, MV_CESA_AUTH_BLOCK_SIZE); -+ copySize = macOffset + macDataSize; -+ } -+ cryptoDataSize = copySize - cryptoOffset; -+ } -+ *pCopySize = copySize; -+ -+ if(pCryptoDataSize != NULL) -+ *pCryptoDataSize = cryptoDataSize; -+ -+ if(pMacDataSize != NULL) -+ *pMacDataSize = macDataSize; -+} -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvCesa.h linux-3.0.4/crypto/ocf/kirkwood/cesa/mvCesa.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvCesa.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/cesa/mvCesa.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,412 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+/******************************************************************************* -+* mvCesa.h - Header File for Cryptographic Engines and Security Accelerator -+* -+* DESCRIPTION: -+* This header file contains macros typedefs and function declaration for -+* the Marvell Cryptographic Engines and Security Accelerator. -+* -+*******************************************************************************/ -+ -+#ifndef __mvCesa_h__ -+#define __mvCesa_h__ -+ -+#include "mvOs.h" -+#include "mvCommon.h" -+#include "mvDebug.h" -+ -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+ -+#include "cesa/mvMD5.h" -+#include "cesa/mvSHA1.h" -+ -+#include "cesa/mvCesa.h" -+#include "cesa/AES/mvAes.h" -+#include "mvSysHwConfig.h" -+ -+#ifdef MV_INCLUDE_IDMA -+#include "idma/mvIdma.h" -+#include "idma/mvIdmaRegs.h" -+#else -+/* Redefine MV_DMA_DESC structure */ -+typedef struct _mvDmaDesc -+{ -+ MV_U32 byteCnt; /* The total number of bytes to transfer */ -+ MV_U32 phySrcAdd; /* The physical source address */ -+ MV_U32 phyDestAdd; /* The physical destination address */ -+ MV_U32 phyNextDescPtr; /* If we are using chain mode DMA transfer, */ -+ /* then this pointer should point to the */ -+ /* physical address of the next descriptor, */ -+ /* otherwise it should be NULL. */ -+}MV_DMA_DESC; -+#endif /* MV_INCLUDE_IDMA */ -+ -+#include "cesa/mvCesaRegs.h" -+ -+#define MV_CESA_AUTH_BLOCK_SIZE 64 /* bytes */ -+ -+#define MV_CESA_MD5_DIGEST_SIZE 16 /* bytes */ -+#define MV_CESA_SHA1_DIGEST_SIZE 20 /* bytes */ -+ -+#define MV_CESA_MAX_DIGEST_SIZE MV_CESA_SHA1_DIGEST_SIZE -+ -+#define MV_CESA_DES_KEY_LENGTH 8 /* bytes = 64 bits */ -+#define MV_CESA_3DES_KEY_LENGTH 24 /* bytes = 192 bits */ -+#define MV_CESA_AES_128_KEY_LENGTH 16 /* bytes = 128 bits */ -+#define MV_CESA_AES_192_KEY_LENGTH 24 /* bytes = 192 bits */ -+#define MV_CESA_AES_256_KEY_LENGTH 32 /* bytes = 256 bits */ -+ -+#define MV_CESA_MAX_CRYPTO_KEY_LENGTH MV_CESA_AES_256_KEY_LENGTH -+ -+#define MV_CESA_DES_BLOCK_SIZE 8 /* bytes = 64 bits */ -+#define MV_CESA_3DES_BLOCK_SIZE 8 /* bytes = 64 bits */ -+ -+#define MV_CESA_AES_BLOCK_SIZE 16 /* bytes = 128 bits */ -+ -+#define MV_CESA_MAX_IV_LENGTH MV_CESA_AES_BLOCK_SIZE -+ -+#define MV_CESA_MAX_MAC_KEY_LENGTH 64 /* bytes */ -+ -+typedef struct -+{ -+ MV_U8 cryptoKey[MV_CESA_MAX_CRYPTO_KEY_LENGTH]; -+ MV_U8 macKey[MV_CESA_MAX_MAC_KEY_LENGTH]; -+ MV_CESA_OPERATION operation; -+ MV_CESA_DIRECTION direction; -+ MV_CESA_CRYPTO_ALG cryptoAlgorithm; -+ MV_CESA_CRYPTO_MODE cryptoMode; -+ MV_U8 cryptoKeyLength; -+ MV_CESA_MAC_MODE macMode; -+ MV_U8 macKeyLength; -+ MV_U8 digestSize; -+ -+} MV_CESA_OPEN_SESSION; -+ -+typedef struct -+{ -+ MV_BUF_INFO *pFrags; -+ MV_U16 numFrags; -+ MV_U16 mbufSize; -+ -+} MV_CESA_MBUF; -+ -+typedef struct -+{ -+ void* pReqPrv; /* instead of reqId */ -+ MV_U32 retCode; -+ MV_16 sessionId; -+ -+} MV_CESA_RESULT; -+ -+typedef void (*MV_CESA_CALLBACK) (MV_CESA_RESULT* pResult); -+ -+ -+typedef struct -+{ -+ void* pReqPrv; /* instead of reqId */ -+ MV_CESA_MBUF* pSrc; -+ MV_CESA_MBUF* pDst; -+ MV_CESA_CALLBACK* pFuncCB; -+ MV_16 sessionId; -+ MV_U16 ivFromUser; -+ MV_U16 ivOffset; -+ MV_U16 cryptoOffset; -+ MV_U16 cryptoLength; -+ MV_U16 digestOffset; -+ MV_U16 macOffset; -+ MV_U16 macLength; -+ MV_BOOL skipFlush; -+} MV_CESA_COMMAND; -+ -+ -+ -+MV_STATUS mvCesaHalInit (int numOfSession, int queueDepth, char* pSramBase, MV_U32 cryptEngBase, void *osHandle); -+MV_STATUS mvCesaFinish (void); -+MV_STATUS mvCesaSessionOpen(MV_CESA_OPEN_SESSION *pSession, short* pSid); -+MV_STATUS mvCesaSessionClose(short sid); -+MV_STATUS mvCesaCryptoIvSet(MV_U8* pIV, int ivSize); -+ -+MV_STATUS mvCesaAction (MV_CESA_COMMAND* pCmd); -+ -+MV_U32 mvCesaInProcessGet(void); -+MV_STATUS mvCesaReadyDispatch(void); -+MV_STATUS mvCesaReadyGet(MV_CESA_RESULT* pResult); -+MV_BOOL mvCesaIsReady(void); -+ -+int mvCesaMbufOffset(MV_CESA_MBUF* pMbuf, int offset, int* pBufOffset); -+MV_STATUS mvCesaCopyFromMbuf(MV_U8* pDst, MV_CESA_MBUF* pSrcMbuf, -+ int offset, int size); -+MV_STATUS mvCesaCopyToMbuf(MV_U8* pSrc, MV_CESA_MBUF* pDstMbuf, -+ int offset, int size); -+MV_STATUS mvCesaMbufCopy(MV_CESA_MBUF* pMbufDst, int dstMbufOffset, -+ MV_CESA_MBUF* pMbufSrc, int srcMbufOffset, int size); -+ -+/********** Debug functions ********/ -+ -+void mvCesaDebugMbuf(const char* str, MV_CESA_MBUF *pMbuf, int offset, int size); -+void mvCesaDebugSA(short sid, int mode); -+void mvCesaDebugStats(void); -+void mvCesaDebugStatsClear(void); -+void mvCesaDebugRegs(void); -+void mvCesaDebugStatus(void); -+void mvCesaDebugQueue(int mode); -+void mvCesaDebugSram(int mode); -+void mvCesaDebugSAD(int mode); -+ -+ -+/******** CESA Private definitions ********/ -+#if (MV_CESA_VERSION >= 2) -+#if (MV_CACHE_COHERENCY == MV_CACHE_COHER_SW) -+#define MV_CESA_TDMA_CTRL_VALUE MV_CESA_TDMA_DST_BURST_MASK(MV_CESA_TDMA_BURST_128B) \ -+ | MV_CESA_TDMA_SRC_BURST_MASK(MV_CESA_TDMA_BURST_128B) \ -+ | MV_CESA_TDMA_OUTSTAND_READ_EN_MASK \ -+ | MV_CESA_TDMA_NO_BYTE_SWAP_MASK \ -+ | MV_CESA_TDMA_ENABLE_MASK -+#else -+#define MV_CESA_TDMA_CTRL_VALUE MV_CESA_TDMA_DST_BURST_MASK(MV_CESA_TDMA_BURST_32B) \ -+ | MV_CESA_TDMA_SRC_BURST_MASK(MV_CESA_TDMA_BURST_128B) \ -+ /*| MV_CESA_TDMA_OUTSTAND_READ_EN_MASK */\ -+ | MV_CESA_TDMA_ENABLE_MASK -+ -+#endif -+#else -+#define MV_CESA_IDMA_CTRL_LOW_VALUE ICCLR_DST_BURST_LIM_128BYTE \ -+ | ICCLR_SRC_BURST_LIM_128BYTE \ -+ | ICCLR_INT_MODE_MASK \ -+ | ICCLR_BLOCK_MODE \ -+ | ICCLR_CHAN_ENABLE \ -+ | ICCLR_DESC_MODE_16M -+#endif /* MV_CESA_VERSION >= 2 */ -+ -+#define MV_CESA_MAX_PKT_SIZE (64 * 1024) -+#define MV_CESA_MAX_MBUF_FRAGS 20 -+ -+#define MV_CESA_MAX_REQ_FRAGS ( (MV_CESA_MAX_PKT_SIZE / MV_CESA_MAX_BUF_SIZE) + 1) -+ -+#define MV_CESA_MAX_DMA_DESC (MV_CESA_MAX_MBUF_FRAGS*2 + 5) -+ -+#define MAX_CESA_CHAIN_LENGTH 20 -+ -+typedef enum -+{ -+ MV_CESA_IDLE = 0, -+ MV_CESA_PENDING, -+ MV_CESA_PROCESS, -+ MV_CESA_READY, -+#if (MV_CESA_VERSION >= 3) -+ MV_CESA_CHAIN, -+#endif -+} MV_CESA_STATE; -+ -+ -+/* Session database */ -+ -+/* Map of Key materials of the session in SRAM. -+ * Each field must be 8 byte aligned -+ * Total size: 32 + 24 + 24 = 80 bytes -+ */ -+typedef struct -+{ -+ MV_U8 cryptoKey[MV_CESA_MAX_CRYPTO_KEY_LENGTH]; -+ MV_U8 macInnerIV[MV_CESA_MAX_DIGEST_SIZE]; -+ MV_U8 reservedInner[4]; -+ MV_U8 macOuterIV[MV_CESA_MAX_DIGEST_SIZE]; -+ MV_U8 reservedOuter[4]; -+ -+} MV_CESA_SRAM_SA; -+ -+typedef struct -+{ -+ MV_CESA_SRAM_SA* pSramSA; -+ MV_U32 config; -+ MV_U8 cryptoKeyLength; -+ MV_U8 cryptoIvSize; -+ MV_U8 cryptoBlockSize; -+ MV_U8 digestSize; -+ MV_U8 macKeyLength; -+ MV_U8 valid; -+ MV_U8 ctrMode; -+ MV_U32 count; -+ -+} MV_CESA_SA; -+ -+/* DMA list management */ -+typedef struct -+{ -+ MV_DMA_DESC* pDmaFirst; -+ MV_DMA_DESC* pDmaLast; -+ -+} MV_CESA_DMA; -+ -+ -+typedef struct -+{ -+ MV_U8 numFrag; -+ MV_U8 nextFrag; -+ int bufOffset; -+ int cryptoSize; -+ int macSize; -+ int newDigestOffset; -+ MV_U8 orgDigest[MV_CESA_MAX_DIGEST_SIZE]; -+ -+} MV_CESA_FRAGS; -+ -+/* Request queue */ -+typedef struct -+{ -+ MV_U8 state; -+ MV_U8 fragMode; -+ MV_U8 fixOffset; -+ MV_CESA_COMMAND* pCmd; -+ MV_CESA_COMMAND* pOrgCmd; -+ MV_BUF_INFO dmaDescBuf; -+ MV_CESA_DMA dma[MV_CESA_MAX_REQ_FRAGS]; -+ MV_BUF_INFO cesaDescBuf; -+ MV_CESA_DESC* pCesaDesc; -+ MV_CESA_FRAGS frags; -+ -+ -+} MV_CESA_REQ; -+ -+ -+/* SRAM map */ -+/* Total SRAM size calculation */ -+/* SRAM size = -+ * MV_CESA_MAX_BUF_SIZE + -+ * sizeof(MV_CESA_DESC) + -+ * MV_CESA_MAX_IV_LENGTH + -+ * MV_CESA_MAX_IV_LENGTH + -+ * MV_CESA_MAX_DIGEST_SIZE + -+ * sizeof(MV_CESA_SRAM_SA) -+ * = 1600 + 32 + 16 + 16 + 24 + 80 + 280 (reserved) = 2048 bytes -+ * = 3200 + 32 + 16 + 16 + 24 + 80 + 728 (reserved) = 4096 bytes -+ */ -+typedef struct -+{ -+ MV_U8 buf[MV_CESA_MAX_BUF_SIZE]; -+ MV_CESA_DESC desc; -+ MV_U8 cryptoIV[MV_CESA_MAX_IV_LENGTH]; -+ MV_U8 tempCryptoIV[MV_CESA_MAX_IV_LENGTH]; -+ MV_U8 tempDigest[MV_CESA_MAX_DIGEST_SIZE+4]; -+ MV_CESA_SRAM_SA sramSA; -+ -+} MV_CESA_SRAM_MAP; -+ -+ -+typedef struct -+{ -+ MV_U32 openedCount; -+ MV_U32 closedCount; -+ MV_U32 fragCount; -+ MV_U32 reqCount; -+ MV_U32 maxReqCount; -+ MV_U32 procCount; -+ MV_U32 readyCount; -+ MV_U32 notReadyCount; -+ MV_U32 startCount; -+#if (MV_CESA_VERSION >= 3) -+ MV_U32 maxChainUsage; -+#endif -+ -+} MV_CESA_STATS; -+ -+ -+/* External variables */ -+ -+extern MV_CESA_STATS cesaStats; -+extern MV_CESA_FRAGS cesaFrags; -+ -+extern MV_BUF_INFO cesaSramSaBuf; -+ -+extern MV_CESA_SA* pCesaSAD; -+extern MV_U16 cesaMaxSA; -+ -+extern MV_CESA_REQ* pCesaReqFirst; -+extern MV_CESA_REQ* pCesaReqLast; -+extern MV_CESA_REQ* pCesaReqEmpty; -+extern MV_CESA_REQ* pCesaReqProcess; -+extern int cesaQueueDepth; -+extern int cesaReqResources; -+#if (MV_CESA_VERSION>= 3) -+extern MV_U32 cesaChainLength; -+#endif -+ -+extern MV_CESA_SRAM_MAP* cesaSramVirtPtr; -+extern MV_U32 cesaSramPhysAddr; -+ -+static INLINE MV_ULONG mvCesaVirtToPhys(MV_BUF_INFO* pBufInfo, void* pVirt) -+{ -+ return (pBufInfo->bufPhysAddr + ((MV_U8*)pVirt - pBufInfo->bufVirtPtr)); -+} -+ -+/* Additional DEBUG functions */ -+void mvCesaDebugSramSA(MV_CESA_SRAM_SA* pSramSA, int mode); -+void mvCesaDebugCmd(MV_CESA_COMMAND* pCmd, int mode); -+void mvCesaDebugDescriptor(MV_CESA_DESC* pDesc); -+ -+ -+ -+#endif /* __mvCesa_h__ */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvCesaDebug.c linux-3.0.4/crypto/ocf/kirkwood/cesa/mvCesaDebug.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvCesaDebug.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/cesa/mvCesaDebug.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,484 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "mvOs.h" -+#include "mvDebug.h" -+ -+#include "cesa/mvMD5.h" -+#include "cesa/mvSHA1.h" -+ -+#include "cesa/mvCesa.h" -+#include "cesa/mvCesaRegs.h" -+#include "cesa/AES/mvAes.h" -+ -+static const char* mvCesaDebugStateStr(MV_CESA_STATE state) -+{ -+ switch(state) -+ { -+ case MV_CESA_IDLE: -+ return "Idle"; -+ -+ case MV_CESA_PENDING: -+ return "Pend"; -+ -+ case MV_CESA_PROCESS: -+ return "Proc"; -+ -+ case MV_CESA_READY: -+ return "Ready"; -+ -+ default: -+ break; -+ } -+ return "Unknown"; -+} -+ -+static const char* mvCesaDebugOperStr(MV_CESA_OPERATION oper) -+{ -+ switch(oper) -+ { -+ case MV_CESA_MAC_ONLY: -+ return "MacOnly"; -+ -+ case MV_CESA_CRYPTO_ONLY: -+ return "CryptoOnly"; -+ -+ case MV_CESA_MAC_THEN_CRYPTO: -+ return "MacCrypto"; -+ -+ case MV_CESA_CRYPTO_THEN_MAC: -+ return "CryptoMac"; -+ -+ default: -+ break; -+ } -+ return "Null"; -+} -+ -+static const char* mvCesaDebugCryptoAlgStr(MV_CESA_CRYPTO_ALG cryptoAlg) -+{ -+ switch(cryptoAlg) -+ { -+ case MV_CESA_CRYPTO_DES: -+ return "DES"; -+ -+ case MV_CESA_CRYPTO_3DES: -+ return "3DES"; -+ -+ case MV_CESA_CRYPTO_AES: -+ return "AES"; -+ -+ default: -+ break; -+ } -+ return "Null"; -+} -+ -+static const char* mvCesaDebugMacModeStr(MV_CESA_MAC_MODE macMode) -+{ -+ switch(macMode) -+ { -+ case MV_CESA_MAC_MD5: -+ return "MD5"; -+ -+ case MV_CESA_MAC_SHA1: -+ return "SHA1"; -+ -+ case MV_CESA_MAC_HMAC_MD5: -+ return "HMAC-MD5"; -+ -+ case MV_CESA_MAC_HMAC_SHA1: -+ return "HMAC_SHA1"; -+ -+ default: -+ break; -+ } -+ return "Null"; -+} -+ -+void mvCesaDebugCmd(MV_CESA_COMMAND* pCmd, int mode) -+{ -+ mvOsPrintf("pCmd=%p, pReqPrv=%p, pSrc=%p, pDst=%p, pCB=%p, sid=%d\n", -+ pCmd, pCmd->pReqPrv, pCmd->pSrc, pCmd->pDst, -+ pCmd->pFuncCB, pCmd->sessionId); -+ mvOsPrintf("isUser=%d, ivOffs=%d, crOffs=%d, crLen=%d, digest=%d, macOffs=%d, macLen=%d\n", -+ pCmd->ivFromUser, pCmd->ivOffset, pCmd->cryptoOffset, pCmd->cryptoLength, -+ pCmd->digestOffset, pCmd->macOffset, pCmd->macLength); -+} -+ -+/* no need to use in tool */ -+void mvCesaDebugMbuf(const char* str, MV_CESA_MBUF *pMbuf, int offset, int size) -+{ -+ int frag, len, fragOffset; -+ -+ if(str != NULL) -+ mvOsPrintf("%s: pMbuf=%p, numFrags=%d, mbufSize=%d\n", -+ str, pMbuf, pMbuf->numFrags, pMbuf->mbufSize); -+ -+ frag = mvCesaMbufOffset(pMbuf, offset, &fragOffset); -+ if(frag == MV_INVALID) -+ { -+ mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); -+ return; -+ } -+ -+ for(; fragnumFrags; frag++) -+ { -+ mvOsPrintf("#%2d. bufVirt=%p, bufSize=%d\n", -+ frag, pMbuf->pFrags[frag].bufVirtPtr, -+ pMbuf->pFrags[frag].bufSize); -+ if(size > 0) -+ { -+ len = MV_MIN(pMbuf->pFrags[frag].bufSize, size); -+ mvDebugMemDump(pMbuf->pFrags[frag].bufVirtPtr+fragOffset, len, 1); -+ size -= len; -+ fragOffset = 0; -+ } -+ } -+} -+ -+void mvCesaDebugRegs(void) -+{ -+ mvOsPrintf("\t CESA Registers:\n"); -+ -+ mvOsPrintf("MV_CESA_CMD_REG : 0x%X = 0x%08x\n", -+ MV_CESA_CMD_REG, -+ MV_REG_READ( MV_CESA_CMD_REG ) ); -+ -+ mvOsPrintf("MV_CESA_CHAN_DESC_OFFSET_REG : 0x%X = 0x%08x\n", -+ MV_CESA_CHAN_DESC_OFFSET_REG, -+ MV_REG_READ(MV_CESA_CHAN_DESC_OFFSET_REG) ); -+ -+ mvOsPrintf("MV_CESA_CFG_REG : 0x%X = 0x%08x\n", -+ MV_CESA_CFG_REG, -+ MV_REG_READ( MV_CESA_CFG_REG ) ); -+ -+ mvOsPrintf("MV_CESA_STATUS_REG : 0x%X = 0x%08x\n", -+ MV_CESA_STATUS_REG, -+ MV_REG_READ( MV_CESA_STATUS_REG ) ); -+ -+ mvOsPrintf("MV_CESA_ISR_CAUSE_REG : 0x%X = 0x%08x\n", -+ MV_CESA_ISR_CAUSE_REG, -+ MV_REG_READ( MV_CESA_ISR_CAUSE_REG ) ); -+ -+ mvOsPrintf("MV_CESA_ISR_MASK_REG : 0x%X = 0x%08x\n", -+ MV_CESA_ISR_MASK_REG, -+ MV_REG_READ( MV_CESA_ISR_MASK_REG ) ); -+#if (MV_CESA_VERSION >= 2) -+ mvOsPrintf("MV_CESA_TDMA_CTRL_REG : 0x%X = 0x%08x\n", -+ MV_CESA_TDMA_CTRL_REG, -+ MV_REG_READ( MV_CESA_TDMA_CTRL_REG ) ); -+ -+ mvOsPrintf("MV_CESA_TDMA_BYTE_COUNT_REG : 0x%X = 0x%08x\n", -+ MV_CESA_TDMA_BYTE_COUNT_REG, -+ MV_REG_READ( MV_CESA_TDMA_BYTE_COUNT_REG ) ); -+ -+ mvOsPrintf("MV_CESA_TDMA_SRC_ADDR_REG : 0x%X = 0x%08x\n", -+ MV_CESA_TDMA_SRC_ADDR_REG, -+ MV_REG_READ( MV_CESA_TDMA_SRC_ADDR_REG ) ); -+ -+ mvOsPrintf("MV_CESA_TDMA_DST_ADDR_REG : 0x%X = 0x%08x\n", -+ MV_CESA_TDMA_DST_ADDR_REG, -+ MV_REG_READ( MV_CESA_TDMA_DST_ADDR_REG ) ); -+ -+ mvOsPrintf("MV_CESA_TDMA_NEXT_DESC_PTR_REG : 0x%X = 0x%08x\n", -+ MV_CESA_TDMA_NEXT_DESC_PTR_REG, -+ MV_REG_READ( MV_CESA_TDMA_NEXT_DESC_PTR_REG ) ); -+ -+ mvOsPrintf("MV_CESA_TDMA_CURR_DESC_PTR_REG : 0x%X = 0x%08x\n", -+ MV_CESA_TDMA_CURR_DESC_PTR_REG, -+ MV_REG_READ( MV_CESA_TDMA_CURR_DESC_PTR_REG ) ); -+ -+ mvOsPrintf("MV_CESA_TDMA_ERROR_CAUSE_REG : 0x%X = 0x%08x\n", -+ MV_CESA_TDMA_ERROR_CAUSE_REG, -+ MV_REG_READ( MV_CESA_TDMA_ERROR_CAUSE_REG ) ); -+ -+ mvOsPrintf("MV_CESA_TDMA_ERROR_MASK_REG : 0x%X = 0x%08x\n", -+ MV_CESA_TDMA_ERROR_MASK_REG, -+ MV_REG_READ( MV_CESA_TDMA_ERROR_CAUSE_REG ) ); -+ -+#endif -+} -+ -+void mvCesaDebugStatus(void) -+{ -+ mvOsPrintf("\n\t CESA Status\n\n"); -+ -+ mvOsPrintf("pReqQ=%p, qDepth=%d, reqSize=%ld bytes, qRes=%d, ", -+ pCesaReqFirst, cesaQueueDepth, sizeof(MV_CESA_REQ), -+ cesaReqResources); -+#if (MV_CESA_VERSION >= 3) -+ mvOsPrintf("chainLength=%u\n",cesaChainLength); -+#else -+ mvOsPrintf("\n"); -+#endif -+ -+ mvOsPrintf("pSAD=%p, maxSA=%d, sizeSA=%ld bytes\n", -+ pCesaSAD, cesaMaxSA, sizeof(MV_CESA_SA)); -+ -+ mvOsPrintf("\n"); -+ -+ mvCesaDebugRegs(); -+ mvCesaDebugStats(); -+ mvCesaDebugStatsClear(); -+} -+ -+void mvCesaDebugDescriptor(MV_CESA_DESC* pDesc) -+{ -+ mvOsPrintf("config=0x%08x, crSrcOffs=0x%04x, crDstOffs=0x%04x\n", -+ pDesc->config, pDesc->cryptoSrcOffset, pDesc->cryptoDstOffset); -+ -+ mvOsPrintf("crLen=0x%04x, crKeyOffs=0x%04x, ivOffs=0x%04x, ivBufOffs=0x%04x\n", -+ pDesc->cryptoDataLen, pDesc->cryptoKeyOffset, -+ pDesc->cryptoIvOffset, pDesc->cryptoIvBufOffset); -+ -+ mvOsPrintf("macSrc=0x%04x, digest=0x%04x, macLen=0x%04x, inIv=0x%04x, outIv=0x%04x\n", -+ pDesc->macSrcOffset, pDesc->macDigestOffset, pDesc->macDataLen, -+ pDesc->macInnerIvOffset, pDesc->macOuterIvOffset); -+} -+ -+void mvCesaDebugQueue(int mode) -+{ -+ mvOsPrintf("\n\t CESA Request Queue:\n\n"); -+ -+ mvOsPrintf("pFirstReq=%p, pLastReq=%p, qDepth=%d, reqSize=%ld bytes\n", -+ pCesaReqFirst, pCesaReqLast, cesaQueueDepth, sizeof(MV_CESA_REQ)); -+ -+ mvOsPrintf("pEmpty=%p, pProcess=%p, qResources=%d\n", -+ pCesaReqEmpty, pCesaReqProcess, -+ cesaReqResources); -+ -+ if(mode != 0) -+ { -+ int count = 0; -+ MV_CESA_REQ* pReq = pCesaReqFirst; -+ -+ for(count=0; countstate), -+ pReq->fragMode, pReq->pCmd, pReq->dma[0].pDmaFirst, &pReq->pCesaDesc[0]); -+ if(pReq->fragMode != MV_CESA_FRAG_NONE) -+ { -+ int frag; -+ -+ mvOsPrintf("pFrags=%p, num=%d, next=%d, bufOffset=%d, cryptoSize=%d, macSize=%d\n", -+ &pReq->frags, pReq->frags.numFrag, pReq->frags.nextFrag, -+ pReq->frags.bufOffset, pReq->frags.cryptoSize, pReq->frags.macSize); -+ for(frag=0; fragfrags.numFrag; frag++) -+ { -+ mvOsPrintf("#%d: pDmaFirst=%p, pDesc=%p\n", frag, -+ pReq->dma[frag].pDmaFirst, &pReq->pCesaDesc[frag]); -+ } -+ } -+ if(mode > 1) -+ { -+ /* Print out Command */ -+ mvCesaDebugCmd(pReq->pCmd, mode); -+ -+ /* Print out Descriptor */ -+ mvCesaDebugDescriptor(&pReq->pCesaDesc[0]); -+ } -+ pReq++; -+ } -+ } -+} -+ -+ -+void mvCesaDebugSramSA(MV_CESA_SRAM_SA* pSramSA, int mode) -+{ -+ if(pSramSA == NULL) -+ { -+ mvOsPrintf("cesaSramSA: Unexpected pSramSA=%p\n", pSramSA); -+ return; -+ } -+ mvOsPrintf("pSramSA=%p, sizeSramSA=%ld bytes\n", -+ pSramSA, sizeof(MV_CESA_SRAM_SA)); -+ -+ if(mode != 0) -+ { -+ mvOsPrintf("cryptoKey=%p, maxCryptoKey=%d bytes\n", -+ pSramSA->cryptoKey, MV_CESA_MAX_CRYPTO_KEY_LENGTH); -+ mvDebugMemDump(pSramSA->cryptoKey, MV_CESA_MAX_CRYPTO_KEY_LENGTH, 1); -+ -+ mvOsPrintf("macInnerIV=%p, maxInnerIV=%d bytes\n", -+ pSramSA->macInnerIV, MV_CESA_MAX_DIGEST_SIZE); -+ mvDebugMemDump(pSramSA->macInnerIV, MV_CESA_MAX_DIGEST_SIZE, 1); -+ -+ mvOsPrintf("macOuterIV=%p, maxOuterIV=%d bytes\n", -+ pSramSA->macOuterIV, MV_CESA_MAX_DIGEST_SIZE); -+ mvDebugMemDump(pSramSA->macOuterIV, MV_CESA_MAX_DIGEST_SIZE, 1); -+ } -+} -+ -+void mvCesaDebugSA(short sid, int mode) -+{ -+ MV_CESA_OPERATION oper; -+ MV_CESA_DIRECTION dir; -+ MV_CESA_CRYPTO_ALG cryptoAlg; -+ MV_CESA_CRYPTO_MODE cryptoMode; -+ MV_CESA_MAC_MODE macMode; -+ MV_CESA_SA* pSA = &pCesaSAD[sid]; -+ -+ if( (pSA->valid) || ((pSA->count != 0) && (mode > 0)) || (mode >= 2) ) -+ { -+ mvOsPrintf("\n\nCESA SA Entry #%d (%p) - %s (count=%d)\n", -+ sid, pSA, -+ pSA->valid ? "Valid" : "Invalid", pSA->count); -+ -+ oper = (pSA->config & MV_CESA_OPERATION_MASK) >> MV_CESA_OPERATION_OFFSET; -+ dir = (pSA->config & MV_CESA_DIRECTION_MASK) >> MV_CESA_DIRECTION_BIT; -+ mvOsPrintf("%s - %s ", mvCesaDebugOperStr(oper), -+ (dir == MV_CESA_DIR_ENCODE) ? "Encode" : "Decode"); -+ if(oper != MV_CESA_MAC_ONLY) -+ { -+ cryptoAlg = (pSA->config & MV_CESA_CRYPTO_ALG_MASK) >> MV_CESA_CRYPTO_ALG_OFFSET; -+ cryptoMode = (pSA->config & MV_CESA_CRYPTO_MODE_MASK) >> MV_CESA_CRYPTO_MODE_BIT; -+ mvOsPrintf("- %s - %s ", mvCesaDebugCryptoAlgStr(cryptoAlg), -+ (cryptoMode == MV_CESA_CRYPTO_ECB) ? "ECB" : "CBC"); -+ } -+ if(oper != MV_CESA_CRYPTO_ONLY) -+ { -+ macMode = (pSA->config & MV_CESA_MAC_MODE_MASK) >> MV_CESA_MAC_MODE_OFFSET; -+ mvOsPrintf("- %s ", mvCesaDebugMacModeStr(macMode)); -+ } -+ mvOsPrintf("\n"); -+ -+ if(mode > 0) -+ { -+ mvOsPrintf("config=0x%08x, cryptoKeySize=%d, digestSize=%d\n", -+ pCesaSAD[sid].config, pCesaSAD[sid].cryptoKeyLength, -+ pCesaSAD[sid].digestSize); -+ -+ mvCesaDebugSramSA(pCesaSAD[sid].pSramSA, mode); -+ } -+ } -+} -+ -+ -+/**/ -+void mvCesaDebugSram(int mode) -+{ -+ mvOsPrintf("\n\t SRAM contents: size=%ld, pVirt=%p\n\n", -+ sizeof(MV_CESA_SRAM_MAP), cesaSramVirtPtr); -+ -+ mvOsPrintf("\n\t Sram buffer: size=%d, pVirt=%p\n", -+ MV_CESA_MAX_BUF_SIZE, cesaSramVirtPtr->buf); -+ if(mode != 0) -+ mvDebugMemDump(cesaSramVirtPtr->buf, 64, 1); -+ -+ mvOsPrintf("\n"); -+ mvOsPrintf("\n\t Sram descriptor: size=%ld, pVirt=%p\n", -+ sizeof(MV_CESA_DESC), &cesaSramVirtPtr->desc); -+ if(mode != 0) -+ { -+ mvOsPrintf("\n"); -+ mvCesaDebugDescriptor(&cesaSramVirtPtr->desc); -+ } -+ mvOsPrintf("\n\t Sram IV: size=%d, pVirt=%p\n", -+ MV_CESA_MAX_IV_LENGTH, &cesaSramVirtPtr->cryptoIV); -+ if(mode != 0) -+ { -+ mvOsPrintf("\n"); -+ mvDebugMemDump(cesaSramVirtPtr->cryptoIV, MV_CESA_MAX_IV_LENGTH, 1); -+ } -+ mvOsPrintf("\n"); -+ mvCesaDebugSramSA(&cesaSramVirtPtr->sramSA, 0); -+} -+ -+void mvCesaDebugSAD(int mode) -+{ -+ int sid; -+ -+ mvOsPrintf("\n\t Cesa SAD status: pSAD=%p, maxSA=%d\n", -+ pCesaSAD, cesaMaxSA); -+ -+ for(sid=0; sid= 3) -+ mvOsPrintf("maxChainUsage=%u\n",cesaStats.maxChainUsage); -+#endif -+ mvOsPrintf("\n"); -+ mvOsPrintf("proc=%u, ready=%u, notReady=%u\n", -+ cesaStats.procCount, cesaStats.readyCount, cesaStats.notReadyCount); -+} -+ -+void mvCesaDebugStatsClear(void) -+{ -+ memset(&cesaStats, 0, sizeof(cesaStats)); -+} -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvCesaRegs.h linux-3.0.4/crypto/ocf/kirkwood/cesa/mvCesaRegs.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvCesaRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/cesa/mvCesaRegs.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,357 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __mvCesaRegs_h__ -+#define __mvCesaRegs_h__ -+ -+#include "mvTypes.h" -+ -+typedef struct -+{ -+ /* word 0 */ -+ MV_U32 config; -+ /* word 1 */ -+ MV_U16 cryptoSrcOffset; -+ MV_U16 cryptoDstOffset; -+ /* word 2 */ -+ MV_U16 cryptoDataLen; -+ MV_U16 reserved1; -+ /* word 3 */ -+ MV_U16 cryptoKeyOffset; -+ MV_U16 reserved2; -+ /* word 4 */ -+ MV_U16 cryptoIvOffset; -+ MV_U16 cryptoIvBufOffset; -+ /* word 5 */ -+ MV_U16 macSrcOffset; -+ MV_U16 macTotalLen; -+ /* word 6 */ -+ MV_U16 macDigestOffset; -+ MV_U16 macDataLen; -+ /* word 7 */ -+ MV_U16 macInnerIvOffset; -+ MV_U16 macOuterIvOffset; -+ -+} MV_CESA_DESC; -+ -+/* operation */ -+typedef enum -+{ -+ MV_CESA_MAC_ONLY = 0, -+ MV_CESA_CRYPTO_ONLY = 1, -+ MV_CESA_MAC_THEN_CRYPTO = 2, -+ MV_CESA_CRYPTO_THEN_MAC = 3, -+ -+ MV_CESA_MAX_OPERATION -+ -+} MV_CESA_OPERATION; -+ -+#define MV_CESA_OPERATION_OFFSET 0 -+#define MV_CESA_OPERATION_MASK (0x3 << MV_CESA_OPERATION_OFFSET) -+ -+/* mac algorithm */ -+typedef enum -+{ -+ MV_CESA_MAC_NULL = 0, -+ MV_CESA_MAC_MD5 = 4, -+ MV_CESA_MAC_SHA1 = 5, -+ MV_CESA_MAC_HMAC_MD5 = 6, -+ MV_CESA_MAC_HMAC_SHA1 = 7, -+ -+} MV_CESA_MAC_MODE; -+ -+#define MV_CESA_MAC_MODE_OFFSET 4 -+#define MV_CESA_MAC_MODE_MASK (0x7 << MV_CESA_MAC_MODE_OFFSET) -+ -+typedef enum -+{ -+ MV_CESA_MAC_DIGEST_FULL = 0, -+ MV_CESA_MAC_DIGEST_96B = 1, -+ -+} MV_CESA_MAC_DIGEST_SIZE; -+ -+#define MV_CESA_MAC_DIGEST_SIZE_BIT 7 -+#define MV_CESA_MAC_DIGEST_SIZE_MASK (1 << MV_CESA_MAC_DIGEST_SIZE_BIT) -+ -+ -+typedef enum -+{ -+ MV_CESA_CRYPTO_NULL = 0, -+ MV_CESA_CRYPTO_DES = 1, -+ MV_CESA_CRYPTO_3DES = 2, -+ MV_CESA_CRYPTO_AES = 3, -+ -+} MV_CESA_CRYPTO_ALG; -+ -+#define MV_CESA_CRYPTO_ALG_OFFSET 8 -+#define MV_CESA_CRYPTO_ALG_MASK (0x3 << MV_CESA_CRYPTO_ALG_OFFSET) -+ -+ -+/* direction */ -+typedef enum -+{ -+ MV_CESA_DIR_ENCODE = 0, -+ MV_CESA_DIR_DECODE = 1, -+ -+} MV_CESA_DIRECTION; -+ -+#define MV_CESA_DIRECTION_BIT 12 -+#define MV_CESA_DIRECTION_MASK (1 << MV_CESA_DIRECTION_BIT) -+ -+/* crypto IV mode */ -+typedef enum -+{ -+ MV_CESA_CRYPTO_ECB = 0, -+ MV_CESA_CRYPTO_CBC = 1, -+ -+ /* NO HW Support */ -+ MV_CESA_CRYPTO_CTR = 10, -+ -+} MV_CESA_CRYPTO_MODE; -+ -+#define MV_CESA_CRYPTO_MODE_BIT 16 -+#define MV_CESA_CRYPTO_MODE_MASK (1 << MV_CESA_CRYPTO_MODE_BIT) -+ -+/* 3DES mode */ -+typedef enum -+{ -+ MV_CESA_CRYPTO_3DES_EEE = 0, -+ MV_CESA_CRYPTO_3DES_EDE = 1, -+ -+} MV_CESA_CRYPTO_3DES_MODE; -+ -+#define MV_CESA_CRYPTO_3DES_MODE_BIT 20 -+#define MV_CESA_CRYPTO_3DES_MODE_MASK (1 << MV_CESA_CRYPTO_3DES_MODE_BIT) -+ -+ -+/* AES Key Length */ -+typedef enum -+{ -+ MV_CESA_CRYPTO_AES_KEY_128 = 0, -+ MV_CESA_CRYPTO_AES_KEY_192 = 1, -+ MV_CESA_CRYPTO_AES_KEY_256 = 2, -+ -+} MV_CESA_CRYPTO_AES_KEY_LEN; -+ -+#define MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET 24 -+#define MV_CESA_CRYPTO_AES_KEY_LEN_MASK (0x3 << MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET) -+ -+/* Fragmentation mode */ -+typedef enum -+{ -+ MV_CESA_FRAG_NONE = 0, -+ MV_CESA_FRAG_FIRST = 1, -+ MV_CESA_FRAG_LAST = 2, -+ MV_CESA_FRAG_MIDDLE = 3, -+ -+} MV_CESA_FRAG_MODE; -+ -+#define MV_CESA_FRAG_MODE_OFFSET 30 -+#define MV_CESA_FRAG_MODE_MASK (0x3 << MV_CESA_FRAG_MODE_OFFSET) -+/*---------------------------------------------------------------------------*/ -+ -+/********** Security Accelerator Command Register **************/ -+#define MV_CESA_CMD_REG (MV_CESA_REG_BASE + 0xE00) -+ -+#define MV_CESA_CMD_CHAN_ENABLE_BIT 0 -+#define MV_CESA_CMD_CHAN_ENABLE_MASK (1 << MV_CESA_CMD_CHAN_ENABLE_BIT) -+ -+#define MV_CESA_CMD_CHAN_DISABLE_BIT 2 -+#define MV_CESA_CMD_CHAN_DISABLE_MASK (1 << MV_CESA_CMD_CHAN_DISABLE_BIT) -+ -+/********** Security Accelerator Descriptor Pointers Register **********/ -+#define MV_CESA_CHAN_DESC_OFFSET_REG (MV_CESA_REG_BASE + 0xE04) -+ -+/********** Security Accelerator Configuration Register **********/ -+#define MV_CESA_CFG_REG (MV_CESA_REG_BASE + 0xE08) -+ -+#define MV_CESA_CFG_STOP_DIGEST_ERR_BIT 0 -+#define MV_CESA_CFG_STOP_DIGEST_ERR_MASK (1 << MV_CESA_CFG_STOP_DIGEST_ERR_BIT) -+ -+#define MV_CESA_CFG_WAIT_DMA_BIT 7 -+#define MV_CESA_CFG_WAIT_DMA_MASK (1 << MV_CESA_CFG_WAIT_DMA_BIT) -+ -+#define MV_CESA_CFG_ACT_DMA_BIT 9 -+#define MV_CESA_CFG_ACT_DMA_MASK (1 << MV_CESA_CFG_ACT_DMA_BIT) -+ -+#define MV_CESA_CFG_CHAIN_MODE_BIT 11 -+#define MV_CESA_CFG_CHAIN_MODE_MASK (1 << MV_CESA_CFG_CHAIN_MODE_BIT) -+ -+/********** Security Accelerator Status Register ***********/ -+#define MV_CESA_STATUS_REG (MV_CESA_REG_BASE + 0xE0C) -+ -+#define MV_CESA_STATUS_ACTIVE_BIT 0 -+#define MV_CESA_STATUS_ACTIVE_MASK (1 << MV_CESA_STATUS_ACTIVE_BIT) -+ -+#define MV_CESA_STATUS_DIGEST_ERR_BIT 8 -+#define MV_CESA_STATUS_DIGEST_ERR_MASK (1 << MV_CESA_STATUS_DIGEST_ERR_BIT) -+ -+ -+/* Cryptographic Engines and Security Accelerator Interrupt Cause Register */ -+#define MV_CESA_ISR_CAUSE_REG (MV_CESA_REG_BASE + 0xE20) -+ -+/* Cryptographic Engines and Security Accelerator Interrupt Mask Register */ -+#define MV_CESA_ISR_MASK_REG (MV_CESA_REG_BASE + 0xE24) -+ -+#define MV_CESA_CAUSE_AUTH_MASK (1 << 0) -+#define MV_CESA_CAUSE_DES_MASK (1 << 1) -+#define MV_CESA_CAUSE_AES_ENCR_MASK (1 << 2) -+#define MV_CESA_CAUSE_AES_DECR_MASK (1 << 3) -+#define MV_CESA_CAUSE_DES_ALL_MASK (1 << 4) -+ -+#define MV_CESA_CAUSE_ACC_BIT 5 -+#define MV_CESA_CAUSE_ACC_MASK (1 << MV_CESA_CAUSE_ACC_BIT) -+ -+#define MV_CESA_CAUSE_ACC_DMA_BIT 7 -+#define MV_CESA_CAUSE_ACC_DMA_MASK (1 << MV_CESA_CAUSE_ACC_DMA_BIT) -+#define MV_CESA_CAUSE_ACC_DMA_ALL_MASK (3 << MV_CESA_CAUSE_ACC_DMA_BIT) -+ -+#define MV_CESA_CAUSE_DMA_COMPL_BIT 9 -+#define MV_CESA_CAUSE_DMA_COMPL_MASK (1 << MV_CESA_CAUSE_DMA_COMPL_BIT) -+ -+#define MV_CESA_CAUSE_DMA_OWN_ERR_BIT 10 -+#define MV_CESA_CAUSE_DMA_OWN_ERR_MASK (1 < MV_CESA_CAUSE_DMA_OWN_ERR_BIT) -+ -+#define MV_CESA_CAUSE_DMA_CHAIN_PKT_BIT 11 -+#define MV_CESA_CAUSE_DMA_CHAIN_PKT_MASK (1 < MV_CESA_CAUSE_DMA_CHAIN_PKT_BIT) -+ -+ -+#define MV_CESA_AUTH_DATA_IN_REG (MV_CESA_REG_BASE + 0xd38) -+#define MV_CESA_AUTH_BIT_COUNT_LOW_REG (MV_CESA_REG_BASE + 0xd20) -+#define MV_CESA_AUTH_BIT_COUNT_HIGH_REG (MV_CESA_REG_BASE + 0xd24) -+ -+#define MV_CESA_AUTH_INIT_VAL_DIGEST_REG(i) (MV_CESA_REG_BASE + 0xd00 + (i<<2)) -+ -+#define MV_CESA_AUTH_INIT_VAL_DIGEST_A_REG (MV_CESA_REG_BASE + 0xd00) -+#define MV_CESA_AUTH_INIT_VAL_DIGEST_B_REG (MV_CESA_REG_BASE + 0xd04) -+#define MV_CESA_AUTH_INIT_VAL_DIGEST_C_REG (MV_CESA_REG_BASE + 0xd08) -+#define MV_CESA_AUTH_INIT_VAL_DIGEST_D_REG (MV_CESA_REG_BASE + 0xd0c) -+#define MV_CESA_AUTH_INIT_VAL_DIGEST_E_REG (MV_CESA_REG_BASE + 0xd10) -+#define MV_CESA_AUTH_COMMAND_REG (MV_CESA_REG_BASE + 0xd18) -+ -+#define MV_CESA_AUTH_ALGORITHM_BIT 0 -+#define MV_CESA_AUTH_ALGORITHM_MD5 (0< -+wait_queue_head_t cesaTest_waitq; -+spinlock_t cesaLock; -+ -+#define CESA_TEST_LOCK(flags) spin_lock_irqsave( &cesaLock, flags) -+#define CESA_TEST_UNLOCK(flags) spin_unlock_irqrestore( &cesaLock, flags); -+ -+#define CESA_TEST_WAIT_INIT() init_waitqueue_head(&cesaTest_waitq) -+#define CESA_TEST_WAKE_UP() wake_up(&cesaTest_waitq) -+#define CESA_TEST_WAIT(cond, ms) wait_event_timeout(cesaTest_waitq, (cond), msecs_to_jiffies(ms)) -+ -+#define CESA_TEST_TICK_GET() jiffies -+#define CESA_TEST_TICK_TO_MS(tick) jiffies_to_msecs(tick) -+ -+#elif defined(MV_NETBSD) -+ -+#include -+#include -+static int cesaLock; -+ -+#define CESA_TEST_LOCK(flags) flags = splnet() -+#define CESA_TEST_UNLOCK(flags) splx(flags) -+ -+#define CESA_TEST_WAIT_INIT() /* nothing */ -+#define CESA_TEST_WAKE_UP() wakeup(&cesaLock) -+#define CESA_TEST_WAIT(cond, ms) \ -+do { \ -+ while (!(cond)) \ -+ tsleep(&cesaLock, PWAIT, "cesatest",mstohz(ms)); \ -+} while (/*CONSTCOND*/0) -+ -+#define CESA_TEST_TICK_GET() hardclock_ticks -+#define CESA_TEST_TICK_TO_MS(tick) ((1000/hz)*(tick)) -+ -+#define request_irq(i,h,t,n,a) \ -+ !mv_intr_establish((i),IPL_NET,(int(*)(void *))(h),(a)) -+ -+#else -+#error "Only Linux, VxWorks, or NetBSD OS are supported" -+#endif -+ -+#include "mvDebug.h" -+ -+#include "mvSysHwConfig.h" -+#include "boardEnv/mvBoardEnvLib.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+#include "cntmr/mvCntmr.h" -+#include "cesa/mvCesa.h" -+#include "cesa/mvCesaRegs.h" -+#include "cesa/mvMD5.h" -+#include "cesa/mvSHA1.h" -+ -+#if defined(CONFIG_MV646xx) -+#include "marvell_pic.h" -+#endif -+ -+#define MV_CESA_USE_TIMER_ID 0 -+#define CESA_DEF_BUF_SIZE 1500 -+#define CESA_DEF_BUF_NUM 1 -+#define CESA_DEF_SESSION_NUM 32 -+ -+#define CESA_DEF_ITER_NUM 100 -+ -+#define CESA_DEF_REQ_SIZE 256 -+ -+ -+/* CESA Tests Debug */ -+#undef CESA_TEST_DEBUG -+ -+#ifdef CESA_TEST_DEBUG -+ -+# define CESA_TEST_DEBUG_PRINT(msg) mvOsPrintf msg -+# define CESA_TEST_DEBUG_CODE(code) code -+ -+typedef struct -+{ -+ int type; /* 0 - isrEmpty, 1 - cesaReadyGet, 2 - cesaAction */ -+ MV_U32 timeStamp; -+ MV_U32 cause; -+ MV_U32 realCause; -+ MV_U32 dmaCause; -+ int resources; -+ MV_CESA_REQ* pReqReady; -+ MV_CESA_REQ* pReqEmpty; -+ MV_CESA_REQ* pReqProcess; -+} MV_CESA_TEST_TRACE; -+ -+#define MV_CESA_TEST_TRACE_SIZE 25 -+ -+static int cesaTestTraceIdx = 0; -+static MV_CESA_TEST_TRACE cesaTestTrace[MV_CESA_TEST_TRACE_SIZE]; -+ -+static void cesaTestTraceAdd(int type, MV_U32 cause) -+{ -+ cesaTestTrace[cesaTestTraceIdx].type = type; -+ cesaTestTrace[cesaTestTraceIdx].cause = cause; -+ cesaTestTrace[cesaTestTraceIdx].realCause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); -+ cesaTestTrace[cesaTestTraceIdx].dmaCause = MV_REG_READ(IDMA_CAUSE_REG); -+ cesaTestTrace[cesaTestTraceIdx].resources = cesaReqResources; -+ cesaTestTrace[cesaTestTraceIdx].pReqReady = pCesaReqReady; -+ cesaTestTrace[cesaTestTraceIdx].pReqEmpty = pCesaReqEmpty; -+ cesaTestTrace[cesaTestTraceIdx].pReqProcess = pCesaReqProcess; -+ cesaTestTrace[cesaTestTraceIdx].timeStamp = mvCntmrRead(MV_CESA_USE_TIMER_ID); -+ cesaTestTraceIdx++; -+ if(cesaTestTraceIdx == MV_CESA_TEST_TRACE_SIZE) -+ cesaTestTraceIdx = 0; -+} -+ -+#else -+ -+# define CESA_TEST_DEBUG_PRINT(msg) -+# define CESA_TEST_DEBUG_CODE(code) -+ -+#endif /* CESA_TEST_DEBUG */ -+ -+int cesaExpReqId=0; -+int cesaCbIter=0; -+ -+int cesaIdx; -+int cesaIteration; -+int cesaRateSize; -+int cesaReqSize; -+unsigned long cesaTaskId; -+int cesaBufNum; -+int cesaBufSize; -+int cesaCheckOffset; -+int cesaCheckSize; -+int cesaCheckMode; -+int cesaTestIdx; -+int cesaCaseIdx; -+ -+ -+MV_U32 cesaTestIsrCount = 0; -+MV_U32 cesaTestIsrMissCount = 0; -+ -+MV_U32 cesaCryptoError = 0; -+MV_U32 cesaReqIdError = 0; -+MV_U32 cesaError = 0; -+ -+char* cesaHexBuffer = NULL; -+ -+char* cesaBinBuffer = NULL; -+char* cesaExpBinBuffer = NULL; -+ -+char* cesaInputHexStr = NULL; -+char* cesaOutputHexStr = NULL; -+ -+MV_BUF_INFO cesaReqBufs[CESA_DEF_REQ_SIZE]; -+ -+MV_CESA_COMMAND* cesaCmdRing; -+MV_CESA_RESULT cesaResult; -+ -+int cesaTestFull = 0; -+ -+MV_BOOL cesaIsReady = MV_FALSE; -+MV_U32 cesaCycles = 0; -+MV_U32 cesaBeginTicks = 0; -+MV_U32 cesaEndTicks = 0; -+MV_U32 cesaRate = 0; -+MV_U32 cesaRateAfterDot = 0; -+ -+void *cesaTestOSHandle = NULL; -+ -+enum -+{ -+ CESA_FAST_CHECK_MODE = 0, -+ CESA_FULL_CHECK_MODE, -+ CESA_NULL_CHECK_MODE, -+ CESA_SHOW_CHECK_MODE, -+ CESA_SW_SHOW_CHECK_MODE, -+ CESA_SW_NULL_CHECK_MODE, -+ -+ CESA_MAX_CHECK_MODE -+}; -+ -+enum -+{ -+ DES_TEST_TYPE = 0, -+ TRIPLE_DES_TEST_TYPE = 1, -+ AES_TEST_TYPE = 2, -+ MD5_TEST_TYPE = 3, -+ SHA_TEST_TYPE = 4, -+ COMBINED_TEST_TYPE = 5, -+ -+ MAX_TEST_TYPE -+}; -+ -+/* Tests data base */ -+typedef struct -+{ -+ short sid; -+ char cryptoAlgorithm; /* DES/3DES/AES */ -+ char cryptoMode; /* ECB or CBC */ -+ char macAlgorithm; /* MD5 / SHA1 */ -+ char operation; /* CRYPTO/HMAC/CRYPTO+HMAC/HMAC+CRYPTO */ -+ char direction; /* ENCODE(SIGN)/DECODE(VERIFY) */ -+ unsigned char* pCryptoKey; -+ int cryptoKeySize; -+ unsigned char* pMacKey; -+ int macKeySize; -+ const char* name; -+ -+} MV_CESA_TEST_SESSION; -+ -+typedef struct -+{ -+ MV_CESA_TEST_SESSION* pSessions; -+ int numSessions; -+ -+} MV_CESA_TEST_DB_ENTRY; -+ -+typedef struct -+{ -+ char* plainHexStr; -+ char* cipherHexStr; -+ unsigned char* pCryptoIV; -+ int cryptoLength; -+ int macLength; -+ int digestOffset; -+ -+} MV_CESA_TEST_CASE; -+ -+typedef struct -+{ -+ int size; -+ const char* outputHexStr; -+ -+} MV_CESA_SIZE_TEST; -+ -+static unsigned char cryptoKey1[] = {0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, -+ 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, -+ 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef}; -+ -+static unsigned char cryptoKey7[] = {0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef}; -+static unsigned char iv1[] = {0x12, 0x34, 0x56, 0x78, 0x90, 0xab, 0xcd, 0xef}; -+ -+ -+static unsigned char cryptoKey2[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, -+ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F}; -+ -+static unsigned char cryptoKey3[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, -+ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, -+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17}; -+ -+static unsigned char cryptoKey4[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, -+ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, -+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, -+ 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f}; -+ -+static unsigned char cryptoKey5[] = {0x56, 0xe4, 0x7a, 0x38, 0xc5, 0x59, 0x89, 0x74, -+ 0xbc, 0x46, 0x90, 0x3d, 0xba, 0x29, 0x03, 0x49}; -+ -+ -+static unsigned char key3des1[] = {0x01, 0x23, 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF, -+ 0x23, 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF, 0x01, -+ 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF, 0x01, 0x23}; -+ -+/* Input ASCII string: The quick brown fox jump */ -+static char plain3des1[] = "54686520717566636B2062726F776E20666F78206A756D70"; -+static char cipher3des1[] = "A826FD8CE53B855FCCE21C8112256FE668D5C05DD9B6B900"; -+ -+static unsigned char key3des2[] = {0x62, 0x7f, 0x46, 0x0e, 0x08, 0x10, 0x4a, 0x10, -+ 0x43, 0xcd, 0x26, 0x5d, 0x58, 0x40, 0xea, 0xf1, -+ 0x31, 0x3e, 0xdf, 0x97, 0xdf, 0x2a, 0x8a, 0x8c}; -+ -+static unsigned char iv3des2[] = {0x8e, 0x29, 0xf7, 0x5e, 0xa7, 0x7e, 0x54, 0x75}; -+ -+static char plain3des2[] = "326a494cd33fe756"; -+ -+static char cipher3desCbc2[] = "8e29f75ea77e5475" -+ "b22b8d66de970692"; -+ -+static unsigned char key3des3[] = {0x37, 0xae, 0x5e, 0xbf, 0x46, 0xdf, 0xf2, 0xdc, -+ 0x07, 0x54, 0xb9, 0x4f, 0x31, 0xcb, 0xb3, 0x85, -+ 0x5e, 0x7f, 0xd3, 0x6d, 0xc8, 0x70, 0xbf, 0xae}; -+ -+static unsigned char iv3des3[] = {0x3d, 0x1d, 0xe3, 0xcc, 0x13, 0x2e, 0x3b, 0x65}; -+ -+static char plain3des3[] = "84401f78fe6c10876d8ea23094ea5309"; -+ -+static char cipher3desCbc3[] = "3d1de3cc132e3b65" -+ "7b1f7c7e3b1c948ebd04a75ffba7d2f5"; -+ -+static unsigned char iv5[] = {0x8c, 0xe8, 0x2e, 0xef, 0xbe, 0xa0, 0xda, 0x3c, -+ 0x44, 0x69, 0x9e, 0xd7, 0xdb, 0x51, 0xb7, 0xd9}; -+ -+static unsigned char aesCtrKey[] = {0x76, 0x91, 0xBE, 0x03, 0x5E, 0x50, 0x20, 0xA8, -+ 0xAC, 0x6E, 0x61, 0x85, 0x29, 0xF9, 0xA0, 0xDC}; -+ -+static unsigned char mdKey1[] = {0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, -+ 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b}; -+ -+static unsigned char mdKey2[] = {0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -+ 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa}; -+ -+static unsigned char shaKey1[] = {0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, -+ 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, -+ 0x0b, 0x0b, 0x0b, 0x0b}; -+ -+static unsigned char shaKey2[] = {0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -+ 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -+ 0xaa, 0xaa, 0xaa, 0xaa}; -+ -+static unsigned char mdKey4[] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10}; -+ -+static unsigned char shaKey4[] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10, -+ 0x11, 0x12, 0x13, 0x14}; -+ -+ -+static MV_CESA_TEST_SESSION desTestSessions[] = -+{ -+/*000*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey7, sizeof(cryptoKey7)/sizeof(cryptoKey7[0]), -+ NULL, 0, -+ "DES ECB encode", -+ }, -+/*001*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_DECODE, -+ cryptoKey7, sizeof(cryptoKey7)/sizeof(cryptoKey7[0]), -+ NULL, 0, -+ "DES ECB decode", -+ }, -+/*002*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey7, sizeof(cryptoKey7)/sizeof(cryptoKey7[0]), -+ NULL, 0, -+ "DES CBC encode" -+ }, -+/*003*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_DECODE, -+ cryptoKey7, sizeof(cryptoKey7)/sizeof(cryptoKey7[0]), -+ NULL, 0, -+ "DES CBC decode" -+ }, -+/*004*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, NULL, 0, -+ "NULL Crypto Algorithm encode" -+ }, -+}; -+ -+ -+static MV_CESA_TEST_SESSION tripleDesTestSessions[] = -+{ -+/*100*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ NULL, 0, -+ "3DES ECB encode", -+ }, -+/*101*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_DECODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ NULL, 0, -+ "3DES ECB decode", -+ }, -+/*102*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ NULL, 0, -+ "3DES CBC encode" -+ }, -+/*103*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_DECODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ NULL, 0, -+ "3DES CBC decode" -+ }, -+/*104*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ key3des1, sizeof(key3des1), -+ NULL, 0, -+ "3DES ECB encode" -+ }, -+/*105*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ key3des2, sizeof(key3des2), -+ NULL, 0, -+ "3DES ECB encode" -+ }, -+/*106*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ key3des3, sizeof(key3des3), -+ NULL, 0, -+ "3DES ECB encode" -+ }, -+}; -+ -+ -+static MV_CESA_TEST_SESSION aesTestSessions[] = -+{ -+/*200*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey2, sizeof(cryptoKey2)/sizeof(cryptoKey2[0]), -+ NULL, 0, -+ "AES-128 ECB encode" -+ }, -+/*201*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_DECODE, -+ cryptoKey2, sizeof(cryptoKey2)/sizeof(cryptoKey2[0]), -+ NULL, 0, -+ "AES-128 ECB decode" -+ }, -+/*202*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey5, sizeof(cryptoKey5)/sizeof(cryptoKey5[0]), -+ NULL, 0, -+ "AES-128 CBC encode" -+ }, -+/*203*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_DECODE, -+ cryptoKey5, sizeof(cryptoKey5)/sizeof(cryptoKey5[0]), -+ NULL, 0, -+ "AES-128 CBC decode" -+ }, -+/*204*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey3, sizeof(cryptoKey3)/sizeof(cryptoKey3[0]), -+ NULL, 0, -+ "AES-192 ECB encode" -+ }, -+/*205*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_DECODE, -+ cryptoKey3, sizeof(cryptoKey3)/sizeof(cryptoKey3[0]), -+ NULL, 0, -+ "AES-192 ECB decode" -+ }, -+/*206*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey4, sizeof(cryptoKey4)/sizeof(cryptoKey4[0]), -+ NULL, 0, -+ "AES-256 ECB encode" -+ }, -+/*207*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_DECODE, -+ cryptoKey4, sizeof(cryptoKey4)/sizeof(cryptoKey4[0]), -+ NULL, 0, -+ "AES-256 ECB decode" -+ }, -+/*208*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CTR, -+ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, -+ MV_CESA_DIR_ENCODE, -+ aesCtrKey, sizeof(aesCtrKey)/sizeof(aesCtrKey[0]), -+ NULL, 0, -+ "AES-128 CTR encode" -+ }, -+}; -+ -+ -+static MV_CESA_TEST_SESSION md5TestSessions[] = -+{ -+/*300*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, -+ mdKey1, sizeof(mdKey1), -+ "HMAC-MD5 Generate Signature" -+ }, -+/*301*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_DECODE, -+ NULL, 0, -+ mdKey1, sizeof(mdKey1), -+ "HMAC-MD5 Verify Signature" -+ }, -+/*302*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, -+ mdKey2, sizeof(mdKey2), -+ "HMAC-MD5 Generate Signature" -+ }, -+/*303*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_DECODE, -+ NULL, 0, -+ mdKey2, sizeof(mdKey2), -+ "HMAC-MD5 Verify Signature" -+ }, -+/*304*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, -+ mdKey4, sizeof(mdKey4), -+ "HMAC-MD5 Generate Signature" -+ }, -+/*305*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_MD5, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, -+ NULL, 0, -+ "HASH-MD5 Generate Signature" -+ }, -+}; -+ -+ -+static MV_CESA_TEST_SESSION shaTestSessions[] = -+{ -+/*400*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, -+ shaKey1, sizeof(shaKey1), -+ "HMAC-SHA1 Generate Signature" -+ }, -+/*401*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_DECODE, -+ NULL, 0, -+ shaKey1, sizeof(shaKey1), -+ "HMAC-SHA1 Verify Signature" -+ }, -+/*402*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, -+ shaKey2, sizeof(shaKey2), -+ "HMAC-SHA1 Generate Signature" -+ }, -+/*403*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_DECODE, -+ NULL, 0, -+ shaKey2, sizeof(shaKey2), -+ "HMAC-SHA1 Verify Signature" -+ }, -+/*404*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, -+ shaKey4, sizeof(shaKey4), -+ "HMAC-SHA1 Generate Signature" -+ }, -+/*405*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_SHA1, MV_CESA_MAC_ONLY, -+ MV_CESA_DIR_ENCODE, -+ NULL, 0, -+ NULL, 0, -+ "HASH-SHA1 Generate Signature" -+ }, -+}; -+ -+static MV_CESA_TEST_SESSION combinedTestSessions[] = -+{ -+/*500*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey1, MV_CESA_DES_KEY_LENGTH, -+ mdKey4, sizeof(mdKey4), -+ "DES + MD5 encode" -+ }, -+/*501*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey1, MV_CESA_DES_KEY_LENGTH, -+ shaKey4, sizeof(shaKey4), -+ "DES + SHA1 encode" -+ }, -+/*502*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ mdKey4, sizeof(mdKey4), -+ "3DES + MD5 encode" -+ }, -+/*503*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ shaKey4, sizeof(shaKey4), -+ "3DES + SHA1 encode" -+ }, -+/*504*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ mdKey4, sizeof(mdKey4), -+ "3DES CBC + MD5 encode" -+ }, -+/*505*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ shaKey4, sizeof(shaKey4), -+ "3DES CBC + SHA1 encode" -+ }, -+/*506*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey5, sizeof(cryptoKey5)/sizeof(cryptoKey5[0]), -+ mdKey4, sizeof(mdKey4), -+ "AES-128 CBC + MD5 encode" -+ }, -+/*507*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, -+ MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, -+ MV_CESA_DIR_ENCODE, -+ cryptoKey5, sizeof(cryptoKey5)/sizeof(cryptoKey5[0]), -+ shaKey4, sizeof(shaKey4), -+ "AES-128 CBC + SHA1 encode" -+ }, -+/*508*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, -+ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_THEN_CRYPTO, -+ MV_CESA_DIR_DECODE, -+ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), -+ mdKey4, sizeof(mdKey4), -+ "HMAC-MD5 + 3DES decode" -+ }, -+}; -+ -+ -+static MV_CESA_TEST_DB_ENTRY cesaTestsDB[MAX_TEST_TYPE+1] = -+{ -+ { desTestSessions, sizeof(desTestSessions)/sizeof(desTestSessions[0]) }, -+ { tripleDesTestSessions, sizeof(tripleDesTestSessions)/sizeof(tripleDesTestSessions[0]) }, -+ { aesTestSessions, sizeof(aesTestSessions)/sizeof(aesTestSessions[0]) }, -+ { md5TestSessions, sizeof(md5TestSessions)/sizeof(md5TestSessions[0]) }, -+ { shaTestSessions, sizeof(shaTestSessions)/sizeof(shaTestSessions[0]) }, -+ { combinedTestSessions, sizeof(combinedTestSessions)/sizeof(combinedTestSessions[0]) }, -+ { NULL, 0 } -+}; -+ -+ -+char cesaNullPlainHexText[] = "000000000000000000000000000000000000000000000000"; -+ -+char cesaPlainAsciiText[] = "Now is the time for all "; -+char cesaPlainHexEbc[] = "4e6f77206973207468652074696d6520666f7220616c6c20"; -+char cesaCipherHexEcb[] = "3fa40e8a984d48156a271787ab8883f9893d51ec4b563b53"; -+char cesaPlainHexCbc[] = "1234567890abcdef4e6f77206973207468652074696d6520666f7220616c6c20"; -+char cesaCipherHexCbc[] = "1234567890abcdefe5c7cdde872bf27c43e934008c389c0f683788499a7c05f6"; -+ -+char cesaAesPlainHexEcb[] = "000102030405060708090a0b0c0d0e0f"; -+char cesaAes128cipherHexEcb[] = "0a940bb5416ef045f1c39458c653ea5a"; -+char cesaAes192cipherHexEcb[] = "0060bffe46834bb8da5cf9a61ff220ae"; -+char cesaAes256cipherHexEcb[] = "5a6e045708fb7196f02e553d02c3a692"; -+ -+char cesaAsciiStr1[] = "Hi There"; -+char cesaDataHexStr1[] = "4869205468657265"; -+char cesaHmacMd5digestHex1[] = "9294727a3638bb1c13f48ef8158bfc9d"; -+char cesaHmacSha1digestHex1[] = "b617318655057264e28bc0b6fb378c8ef146be00"; -+char cesaDataAndMd5digest1[] = "48692054686572659294727a3638bb1c13f48ef8158bfc9d"; -+char cesaDataAndSha1digest1[] = "4869205468657265b617318655057264e28bc0b6fb378c8ef146be00"; -+ -+char cesaAesPlainText[] = "a0a1a2a3a4a5a6a7a8a9aaabacadaeaf" -+ "b0b1b2b3b4b5b6b7b8b9babbbcbdbebf" -+ "c0c1c2c3c4c5c6c7c8c9cacbcccdcecf" -+ "d0d1d2d3d4d5d6d7d8d9dadbdcdddedf"; -+ -+char cesaAes128CipherCbc[] = "c30e32ffedc0774e6aff6af0869f71aa" -+ "0f3af07a9a31a9c684db207eb0ef8e4e" -+ "35907aa632c3ffdf868bb7b29d3d46ad" -+ "83ce9f9a102ee99d49a53e87f4c3da55"; -+ -+char cesaAesIvPlainText[] = "8ce82eefbea0da3c44699ed7db51b7d9" -+ "a0a1a2a3a4a5a6a7a8a9aaabacadaeaf" -+ "b0b1b2b3b4b5b6b7b8b9babbbcbdbebf" -+ "c0c1c2c3c4c5c6c7c8c9cacbcccdcecf" -+ "d0d1d2d3d4d5d6d7d8d9dadbdcdddedf"; -+ -+char cesaAes128IvCipherCbc[] = "8ce82eefbea0da3c44699ed7db51b7d9" -+ "c30e32ffedc0774e6aff6af0869f71aa" -+ "0f3af07a9a31a9c684db207eb0ef8e4e" -+ "35907aa632c3ffdf868bb7b29d3d46ad" -+ "83ce9f9a102ee99d49a53e87f4c3da55"; -+ -+char cesaAesCtrPlain[] = "00E0017B27777F3F4A1786F000000001" -+ "000102030405060708090A0B0C0D0E0F" -+ "101112131415161718191A1B1C1D1E1F" -+ "20212223"; -+ -+char cesaAesCtrCipher[] = "00E0017B27777F3F4A1786F000000001" -+ "C1CF48A89F2FFDD9CF4652E9EFDB72D7" -+ "4540A42BDE6D7836D59A5CEAAEF31053" -+ "25B2072F"; -+ -+ -+ -+/* Input cesaHmacHex3 is '0xdd' repeated 50 times */ -+char cesaHmacMd5digestHex3[] = "56be34521d144c88dbb8c733f0e8b3f6"; -+char cesaHmacSha1digestHex3[] = "125d7342b9ac11cd91a39af48aa17b4f63f175d3"; -+char cesaDataHexStr3[50*2+1] = ""; -+char cesaDataAndMd5digest3[sizeof(cesaDataHexStr3)+sizeof(cesaHmacMd5digestHex3)+8*2+1] = ""; -+char cesaDataAndSha1digest3[sizeof(cesaDataHexStr3)+sizeof(cesaHmacSha1digestHex3)+8*2+1] = ""; -+ -+/* Ascii string is "abc" */ -+char hashHexStr3[] = "616263"; -+char hashMd5digest3[] = "900150983cd24fb0d6963f7d28e17f72"; -+char hashSha1digest3[] = "a9993e364706816aba3e25717850c26c9cd0d89d"; -+ -+char hashHexStr80[] = "31323334353637383930" -+ "31323334353637383930" -+ "31323334353637383930" -+ "31323334353637383930" -+ "31323334353637383930" -+ "31323334353637383930" -+ "31323334353637383930" -+ "31323334353637383930"; -+ -+char hashMd5digest80[] = "57edf4a22be3c955ac49da2e2107b67a"; -+ -+char tripleDesThenMd5digest80[] = "b7726a03aad490bd6c5a452a89a1b271"; -+char tripleDesThenSha1digest80[] = "b2ddeaca91030eab5b95a234ef2c0f6e738ff883"; -+ -+char cbc3desThenMd5digest80[] = "6f463057e1a90e0e91ae505b527bcec0"; -+char cbc3desThenSha1digest80[] = "1b002ed050be743aa98860cf35659646bb8efcc0"; -+ -+char cbcAes128ThenMd5digest80[] = "6b6e863ac5a71d15e3e9b1c86c9ba05f"; -+char cbcAes128ThenSha1digest80[] = "13558472d1fc1c90dffec6e5136c7203452d509b"; -+ -+ -+static MV_CESA_TEST_CASE cesaTestCases[] = -+{ -+ /* plainHexStr cipherHexStr IV crypto mac digest */ -+ /* Length Length Offset */ -+ /*0*/ { NULL, NULL, NULL, 0, 0, -1 }, -+ /*1*/ { cesaPlainHexEbc, cesaCipherHexEcb, NULL, 24, 0, -1 }, -+ /*2*/ { cesaPlainHexCbc, cesaCipherHexCbc, NULL, 24, 0, -1 }, -+ /*3*/ { cesaAesPlainHexEcb, cesaAes128cipherHexEcb, NULL, 16, 0, -1 }, -+ /*4*/ { cesaAesPlainHexEcb, cesaAes192cipherHexEcb, NULL, 16, 0, -1 }, -+ /*5*/ { cesaAesPlainHexEcb, cesaAes256cipherHexEcb, NULL, 16, 0, -1 }, -+ /*6*/ { cesaDataHexStr1, cesaHmacMd5digestHex1, NULL, 0, 8, -1 }, -+ /*7*/ { NULL, cesaDataAndMd5digest1, NULL, 0, 8, -1 }, -+ /*8*/ { cesaDataHexStr3, cesaHmacMd5digestHex3, NULL, 0, 50, -1 }, -+ /*9*/ { NULL, cesaDataAndMd5digest3, NULL, 0, 50, -1 }, -+/*10*/ { cesaAesPlainText, cesaAes128IvCipherCbc, iv5, 64, 0, -1 }, -+/*11*/ { cesaDataHexStr1, cesaHmacSha1digestHex1, NULL, 0, 8, -1 }, -+/*12*/ { NULL, cesaDataAndSha1digest1, NULL, 0, 8, -1 }, -+/*13*/ { cesaDataHexStr3, cesaHmacSha1digestHex3, NULL, 0, 50, -1 }, -+/*14*/ { NULL, cesaDataAndSha1digest3, NULL, 0, 50, -1 }, -+/*15*/ { hashHexStr3, hashMd5digest3, NULL, 0, 3, -1 }, -+/*16*/ { hashHexStr3, hashSha1digest3, NULL, 0, 3, -1 }, -+/*17*/ { hashHexStr80, tripleDesThenMd5digest80, NULL, 80, 80, -1 }, -+/*18*/ { hashHexStr80, tripleDesThenSha1digest80, NULL, 80, 80, -1 }, -+/*19*/ { hashHexStr80, cbc3desThenMd5digest80, iv1, 80, 80, -1 }, -+/*20*/ { hashHexStr80, cbc3desThenSha1digest80, iv1, 80, 80, -1 }, -+/*21*/ { hashHexStr80, cbcAes128ThenMd5digest80, iv5, 80, 80, -1 }, -+/*22*/ { hashHexStr80, cbcAes128ThenSha1digest80, iv5, 80, 80, -1 }, -+/*23*/ { cesaAesCtrPlain, cesaAesCtrCipher, NULL, 36, 0, -1 }, -+/*24*/ { cesaAesIvPlainText, cesaAes128IvCipherCbc, NULL, 64, 0, -1 }, -+/*25*/ { plain3des1, cipher3des1, NULL, 0, 0, -1 }, -+/*26*/ { plain3des2, cipher3desCbc2, iv3des2,0, 0, -1 }, -+/*27*/ { plain3des3, cipher3desCbc3, iv3des3,0, 0, -1 }, -+}; -+ -+ -+/* Key = 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -+ * 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa -+ * Input 0xdd repeated "size" times -+ */ -+static MV_CESA_SIZE_TEST mdMultiSizeTest302[] = -+{ -+ { 80, "7a031a640c14a4872814930b1ef3a5b2" }, -+ { 512, "5488e6c5a14dc72a79f28312ca5b939b" }, -+ { 1000, "d00814f586a8b78a05724239d2531821" }, -+ { 1001, "bf07df7b7f49d3f5b5ecacd4e9e63281" }, -+ { 1002, "1ed4a1a802e87817a819d4e37bb4d0f7" }, -+ { 1003, "5972ab64a4f265ee371dac2f2f137f90" }, -+ { 1004, "71f95e7ec3aa7df2548e90898abdb28e" }, -+ { 1005, "e082790b4857fcfc266e92e59e608814" }, -+ { 1006, "9500f02fd8ac7fde8b10e4fece9a920d" }, -+ { 1336, "e42edcce57d0b75b01aa09d71427948b" }, -+ { 1344, "bb5454ada0deb49ba0a97ffd60f57071" }, -+ { 1399, "0f44d793e744b24d53f44f295082ee8c" }, -+ { 1400, "359de8a03a9b707928c6c60e0e8d79f1" }, -+ { 1401, "e913858b484cbe2b384099ea88d8855b" }, -+ { 1402, "d9848a164af53620e0540c1d7d87629e" }, -+ { 1403, "0c9ee1c2c9ef45e9b625c26cbaf3e822" }, -+ { 1404, "12edd4f609416e3c936170360561b064" }, -+ { 1405, "7fc912718a05446395345009132bf562" }, -+ { 1406, "882f17425e579ff0d85a91a59f308aa0" }, -+ { 1407, "005cae408630a2fb5db82ad9db7e59da" }, -+ { 1408, "64655f8b404b3fea7a3e3e609bc5088f" }, -+ { 1409, "4a145284a7f74e01b6bb1a0ec6a0dd80" }, -+ { 2048, "67caf64475650732def374ebb8bde3fd" }, -+ { 2049, "6c84f11f472825f7e6cd125c2981884b" }, -+ { 2050, "8999586754a73a99efbe4dbad2816d41" }, -+ { 2051, "ba6946b610e098d286bc81091659dfff" }, -+ { 2052, "d0afa01c92d4d13def2b024f36faed83" }, -+ { 3072, "61d8beac61806afa2585d74a9a0e6974" }, -+ { 3074, "f6501a28dcc24d1e4770505c51a87ed3" }, -+ { 3075, "ea4a6929be67e33e61ff475369248b73" }, -+ { 4048, "aa8c4d68f282a07e7385acdfa69f4bed" }, -+ { 4052, "afb5ed2c0e1d430ea59e59ed5ed6b18a" }, -+ { 4058, "9e8553f9bdd43aebe0bd729f0e600c99" }, -+ { 6144, "f628f3e5d183fe5cdd3a5abee39cf872" }, -+ { 6150, "89a3efcea9a2f25f919168ad4a1fd292" }, -+ { 6400, "cdd176b7fb747873efa4da5e32bdf88f" }, -+ { 6528, "b1d707b027354aca152c45ee559ccd3f" }, -+ { 8192, "c600ea4429ac47f9941f09182166e51a" }, -+ {16384, "16e8754bfbeb4c649218422792267a37" }, -+ {18432, "0fd0607521b0aa8b52219cfbe215f63e" }, -+ { 0, NULL }, -+}; -+ -+/* Key = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ */ -+static MV_CESA_SIZE_TEST mdMultiSizeTest304[] = -+{ -+ { 80, "a456c4723fee6068530af5a2afa71627" }, -+ { 512, "f85c2a2344f5de68b432208ad13e5794" }, -+ { 1000, "35464d6821fd4a293a41eb84e274c8c5" }, -+ { 1001, "c08eedbdce60cceb54bc2d732bb32c8b" }, -+ { 1002, "5664f71800c011cc311cb6943339c1b8" }, -+ { 1003, "779c723b044c585dc7802b13e8501bdc" }, -+ { 1004, "55e500766a2c307bc5c5fdd15e4cacd4" }, -+ { 1005, "d5f978954f5c38529d1679d2b714f068" }, -+ { 1006, "cd3efc827ce628b7281b72172693abf9" }, -+ { 1336, "6f04479910785878ae6335b8d1e87edf" }, -+ { 1344, "b6d27b50c2bce1ba2a8e1b5cc4324368" }, -+ { 1399, "65f70a1d4c86e5eaeb0704c8a7816795" }, -+ { 1400, "3394b5adc4cb3ff98843ca260a44a88a" }, -+ { 1401, "3a06f3582033a66a4e57e0603ce94e74" }, -+ { 1402, "e4d97f5ed51edc48abfa46eeb5c31752" }, -+ { 1403, "3d05e40b080ee3bedf293cb87b7140e7" }, -+ { 1404, "8cf294fc3cd153ab18dccb2a52cbf244" }, -+ { 1405, "d1487bd42f6edd9b4dab316631159221" }, -+ { 1406, "0527123b6bf6936cf5d369dc18c6c70f" }, -+ { 1407, "3224a06639db70212a0cd1ae1fcc570a" }, -+ { 1408, "a9e13335612c0356f5e2c27086e86c43" }, -+ { 1409, "a86d1f37d1ed8a3552e9a4f04dceea98" }, -+ { 2048, "396905c9b961cd0f6152abfb69c4449c" }, -+ { 2049, "49f39bff85d9dcf059fadb89efc4a70f" }, -+ { 2050, "3a2b4823bc4d0415656550226a63e34a" }, -+ { 2051, "dec60580d406c782540f398ad0bcc7e0" }, -+ { 2052, "32f76610a14310309eb748fe025081bf" }, -+ { 3072, "45edc1a42bf9d708a621076b63b774da" }, -+ { 3074, "9be1b333fe7c0c9f835fb369dc45f778" }, -+ { 3075, "8c06fcac7bd0e7b7a17fd6508c09a549" }, -+ { 4048, "0ddaef848184bf0ad98507a10f1e90e4" }, -+ { 4052, "81976bcaeb274223983996c137875cb8" }, -+ { 4058, "0b0a7a1c82bc7cbc64d8b7cd2dc2bb22" }, -+ { 6144, "1c24056f52725ede2dff0d7f9fc9855f" }, -+ { 6150, "b7f4b65681c4e43ee68ca466ca9ca4ec" }, -+ { 6400, "443bbaab9f7331ddd4bf11b659cd43c8" }, -+ { 6528, "216f44f23047cfee03a7a64f88f9a995" }, -+ { 8192, "ac7a993b2cad54879dba1bde63e39097" }, -+ { 8320, "55ed7be9682d6c0025b3221a62088d08" }, -+ {16384, "c6c722087653b62007aea668277175e5" }, -+ {18432, "f1faca8e907872c809e14ffbd85792d6" }, -+ { 0, NULL }, -+}; -+ -+/* HASH-MD5 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ * repeated "size" times -+ */ -+static MV_CESA_SIZE_TEST mdMultiSizeTest305[] = -+{ -+ { 80, "57edf4a22be3c955ac49da2e2107b67a" }, -+ { 512, "c729ae8f0736cc377a9767a660eaa04e" }, -+ { 1000, "f1257a8659eb92d36fe14c6bf3852a6a" }, -+ { 1001, "f8a46fe8ea04fdc8c7de0e84042d3878" }, -+ { 1002, "da188dd67bff87d58aa3c02af2d0cc0f" }, -+ { 1003, "961753017feee04c9b93a8e51658a829" }, -+ { 1004, "dd68c4338608dcc87807a711636bf2af" }, -+ { 1005, "e338d567d3ce66bf69ada29658a8759b" }, -+ { 1006, "443c9811e8b92599b0b149e8d7ec700a" }, -+ { 1336, "89a98511706008ba4cbd0b4a24fa5646" }, -+ { 1344, "335a919805f370b9e402a62c6fe01739" }, -+ { 1399, "5d18d0eddcd84212fe28d812b5e80e3b" }, -+ { 1400, "6b695c240d2dffd0dffc99459ca76db6" }, -+ { 1401, "49590f61298a76719bc93a57a30136f5" }, -+ { 1402, "94c2999fa3ef1910a683d69b2b8476f2" }, -+ { 1403, "37073a02ab00ecba2645c57c228860db" }, -+ { 1404, "1bcd06994fce28b624f0c5fdc2dcdd2b" }, -+ { 1405, "11b93671a64c95079e8cf9e7cddc8b3d" }, -+ { 1406, "4b6695772a4c66313fa4871017d05f36" }, -+ { 1407, "d1539b97fbfda1c075624e958de19c5b" }, -+ { 1408, "b801b9b69920907cd018e8063092ede9" }, -+ { 1409, "b765f1406cfe78e238273ed01bbcaf7e" }, -+ { 2048, "1d7e2c64ac29e2b3fb4c272844ed31f5" }, -+ { 2049, "71d38fac49c6b1f4478d8d88447bcdd0" }, -+ { 2050, "141c34a5592b1bebfa731e0b23d0cdba" }, -+ { 2051, "c5e1853f21c59f5d6039bd13d4b380d8" }, -+ { 2052, "dd44a0d128b63d4b5cccd967906472d7" }, -+ { 3072, "37d158e33b21390822739d13db7b87fe" }, -+ { 3074, "aef3b209d01d39d0597fe03634bbf441" }, -+ { 3075, "335ffb428eabf210bada96d74d5a4012" }, -+ { 4048, "2434c2b43d798d2819487a886261fc64" }, -+ { 4052, "ac2fa84a8a33065b2e92e36432e861f8" }, -+ { 4058, "856781f85616c341c3533d090c1e1e84" }, -+ { 6144, "e5d134c652c18bf19833e115f7a82e9b" }, -+ { 6150, "a09a353be7795fac2401dac5601872e6" }, -+ { 6400, "08b9033ac6a1821398f50af75a2dbc83" }, -+ { 6528, "3d47aa193a8540c091e7e02f779e6751" }, -+ { 8192, "d3164e710c0626f6f395b38f20141cb7" }, -+ { 8320, "b727589d9183ff4e8491dd24466974a3" }, -+ {16384, "3f54d970793d2274d5b20d10a69938ac" }, -+ {18432, "f558511dcf81985b7a1bb57fad970531" }, -+ { 0, NULL }, -+}; -+ -+ -+/* Key = 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, -+ * 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa -+ * 0xaa, 0xaa, 0xaa, 0xaa -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ */ -+static MV_CESA_SIZE_TEST shaMultiSizeTest402[] = -+{ -+ { 80, "e812f370e659705a1649940d1f78cd7af18affd3" }, -+ { 512, "e547f886b2c15d995ed76a8a924cb408c8080f66" }, -+ { 1000, "239443194409f1a5342ecde1a092c8f3a3ed790a" }, -+ { 1001, "f278ab9a102850a9f48dc4e9e6822afe2d0c52b5" }, -+ { 1002, "8bcc667df5ab6ece988b3af361d09747c77f4e72" }, -+ { 1003, "0fae6046c7dc1d3e356b25af836f6077a363f338" }, -+ { 1004, "0ea48401cc92ae6bc92ae76685269cb0167fbe1a" }, -+ { 1005, "ecbcd7c879b295bafcd8766cbeac58cc371e31d1" }, -+ { 1006, "eb4a4a3d07d1e9a15e6f1ab8a9c47f243e27324c" }, -+ { 1336, "f5950ee1d77c10e9011d2149699c9366fe52529c" }, -+ { 1344, "b04263604a63c351b0b3b9cf1785b4bdba6c8838" }, -+ { 1399, "8cb1cff61d5b784045974a2fc69386e3b8d24218" }, -+ { 1400, "9bb2f3fcbeddb2b90f0be797cd647334a2816d51" }, -+ { 1401, "23ae462a7a0cb440f7445791079a5d75a535dd33" }, -+ { 1402, "832974b524a4d3f9cc2f45a3cabf5ccef65cd2aa" }, -+ { 1403, "d1c683742fe404c3c20d5704a5430e7832a7ec95" }, -+ { 1404, "867c79042e64f310628e219d8b85594cd0c7adc3" }, -+ { 1405, "c9d81d49d13d94358f56ccfd61af02b36c69f7c3" }, -+ { 1406, "0df43daab2786172f9b8d07d61f14a070cf1287a" }, -+ { 1407, "0fd8f3ad7f169534b274d4c66bbddd89f759e391" }, -+ { 1408, "3987511182b18473a564436003139b808fa46343" }, -+ { 1409, "ef667e063c9e9f539a8987a8d0bd3066ee85d901" }, -+ { 2048, "921109c99f3fedaca21727156d5f2b4460175327" }, -+ { 2049, "47188600dd165eb45f27c27196d3c46f4f042c1b" }, -+ { 2050, "8831939904009338de10e7fa670847041387807d" }, -+ { 2051, "2f8ebb5db2997d614e767be1050366f3641e7520" }, -+ { 2052, "669e51cd730dae158d3bef8adba075bd95a0d011" }, -+ { 3072, "cfee66cfd83abc8451af3c96c6b35a41cc6c55f5" }, -+ { 3074, "216ea26f02976a261b7d21a4dd3085157bedfabd" }, -+ { 3075, "bd612ebba021fd8e012b14c3bd60c8c5161fabc0" }, -+ { 4048, "c2564c1fdf2d5e9d7dde7aace2643428e90662e8" }, -+ { 4052, "91ce61fe924b445dfe7b5a1dcd10a27caec16df6" }, -+ { 4058, "db2a9be5ee8124f091c7ebd699266c5de223c164" }, -+ { 6144, "855109903feae2ba3a7a05a326b8a171116eb368" }, -+ { 6150, "37520bb3a668294d9c7b073e7e3daf8fee248a78" }, -+ { 6400, "60a353c841b6d2b1a05890349dad2fa33c7536b7" }, -+ { 6528, "9e53a43a69bb42d7c8522ca8bd632e421d5edb36" }, -+ { 8192, "a918cb0da862eaea0a33ee0efea50243e6b4927c" }, -+ { 8320, "29a5dcf55d1db29cd113fcf0572ae414f1c71329" }, -+ {16384, "6fb27966138e0c8d5a0d65ace817ebd53633cee1" }, -+ {18432, "ca09900d891c7c9ae2a559b10f63a217003341c1" }, -+ { 0, NULL }, -+}; -+ -+/* Key = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 -+ * 0x11, 0x12, 0x13, 0x14 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ */ -+static MV_CESA_SIZE_TEST shaMultiSizeTest404[] = -+{ -+ { 80, "beaf20a34b06a87558d156c0949bc3957d40222e" }, -+ { 512, "3353955358d886bc2940a3c7f337ff7dafb59c7b" }, -+ { 1000, "8737a542c5e9b2b6244b757ebb69d5bd602a829f" }, -+ { 1001, "fd9e7582d8a5d3c9fe3b923e4e6a41b07a1eb4d4" }, -+ { 1002, "a146d14a6fc3c274ff600568f4d75b977989e00d" }, -+ { 1003, "be22601bbc027ddef2dec97d30b3dc424fd803c5" }, -+ { 1004, "3e71fe99b2fe2b7bfdf4dbf0c7f3da25d7ea35e7" }, -+ { 1005, "2c422735d7295408fddd76f5e8a83a2a8da13df3" }, -+ { 1006, "6d875319049314b61855101a647b9ba3313428e6" }, -+ { 1336, "c1631ea80bad9dc43a180712461b65a0598c711c" }, -+ { 1344, "816069bf91d34581005746e2e0283d0f9c7b7605" }, -+ { 1399, "4e139866dc61cfcb8b67ca2ebd637b3a538593af" }, -+ { 1400, "ff2a0f8dd2b02c5417910f6f55d33a78e081a723" }, -+ { 1401, "ab00c12be62336964cbce31ae97fe2a0002984d5" }, -+ { 1402, "61349e7f999f3a1acc56c3e9a5060a9c4a7b05b6" }, -+ { 1403, "3edbc0f61e435bc1317fa27d840076093fb79353" }, -+ { 1404, "d052c6dfdbe63d45dab23ef9893e2aa4636aca1e" }, -+ { 1405, "0cc16b7388d67bf0add15a31e6e6c753cfae4987" }, -+ { 1406, "c96ba7eaad74253c38c22101b558d2850b1d1b90" }, -+ { 1407, "3445428a40d2c6556e7c55797ad8d323b61a48d9" }, -+ { 1408, "8d6444f937a09317c89834187b8ea9b8d3a8c56b" }, -+ { 1409, "c700acd3ecd19014ea2bdb4d42510c467e088475" }, -+ { 2048, "ee27d2a0cb77470c2f496212dfd68b5bb7b04e4b" }, -+ { 2049, "683762d7a02983b26a6d046e6451d9cd82c25932" }, -+ { 2050, "0fd20f1d55a9ee18363c2a6fd54aa13aee69992f" }, -+ { 2051, "86c267d8cc4bc8d59090e4f8b303da960fd228b7" }, -+ { 2052, "452395ae05b3ec503eea34f86fc0832485ad97c1" }, -+ { 3072, "75198e3cfd0b9bcff2dabdf8e38e6fdaa33ca49a" }, -+ { 3074, "4e24785ef080141ce4aab4675986d9acea624d7c" }, -+ { 3075, "3a20c5978dd637ec0e809bf84f0d9ccf30bc65bf" }, -+ { 4048, "3c32da256be7a7554922bf5fed51b0d2d09e59ad" }, -+ { 4052, "fff898426ea16e54325ae391a32c6c9bce4c23c0" }, -+ { 4058, "c800b9e562e1c91e1310116341a3c91d37f848ec" }, -+ { 6144, "d91d509d0cc4376c2d05bf9a5097717a373530e6" }, -+ { 6150, "d957030e0f13c5df07d9eec298542d8f94a07f12" }, -+ { 6400, "bb745313c3d7dc17b3f955e5534ad500a1082613" }, -+ { 6528, "77905f80d9ca82080bbb3e5654896dabfcfd1bdb" }, -+ { 8192, "5237fd9a81830c974396f99f32047586612ff3c0" }, -+ { 8320, "57668e28d5f2dba0839518a11db0f6af3d7e08bf" }, -+ {16384, "62e093fde467f0748087beea32e9af97d5c61241" }, -+ {18432, "845fb33130c7d6ea554fd5aacb9c50cf7ccb5929" }, -+ { 0, NULL }, -+}; -+ -+/* HASH-SHA1 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ * repeated "size" times -+ */ -+static MV_CESA_SIZE_TEST shaMultiSizeTest405[] = -+{ -+ { 80, "50abf5706a150990a08b2c5ea40fa0e585554732" }, -+ { 512, "f14516a08948fa27917a974d219741a697ba0087" }, -+ { 1000, "0bd18c378d5788817eb4f1e5dc07d867efa5cbf4" }, -+ { 1001, "ca29b85c35db1b8aef83c977893a11159d1b7aa2" }, -+ { 1002, "d83bc973eaaedb8a31437994dabbb3304b0be086" }, -+ { 1003, "2cf7bbef0acd6c00536b5c58ca470df9a3a90b6c" }, -+ { 1004, "e4375d09b1223385a8a393066f8209acfd936a80" }, -+ { 1005, "1029b38043e027745d019ce1d2d68e3d8b9d8f99" }, -+ { 1006, "deea16dcebbd8ac137e2b984deb639b9fb5e9680" }, -+ { 1336, "ea031b065fff63dcfb6a41956e4777520cdbc55d" }, -+ { 1344, "b52096c6445e6c0a8355995c70dc36ae186c863c" }, -+ { 1399, "cde2f6f8379870db4b32cf17471dc828a8dbff2b" }, -+ { 1400, "e53ff664064bc09fe5054c650806bd42d8179518" }, -+ { 1401, "d1156db5ddafcace64cdb510ff0d4af9b9a8ad64" }, -+ { 1402, "34ede0e9a909dd84a2ae291539105c0507b958e1" }, -+ { 1403, "a772ca3536da77e6ad3251e4f9e1234a4d7b87c0" }, -+ { 1404, "29740fd2b04e7a8bfd32242db6233156ad699948" }, -+ { 1405, "65b17397495b70ce4865dad93bf991b74c97cce1" }, -+ { 1406, "a7ee89cd0754061fdb91af7ea6abad2c69d542e3" }, -+ { 1407, "3eebf82f7420188e23d328b7ce93580b279a5715" }, -+ { 1408, "e08d3363a8b9a490dfb3a4c453452b8f114deeec" }, -+ { 1409, "95d74df739181a4ff30b8c39e28793a36598e924" }, -+ { 2048, "aa40262509c2abf84aab0197f83187fc90056d91" }, -+ { 2049, "7dec28ef105bc313bade8d9a7cdeac58b99de5ea" }, -+ { 2050, "d2e30f77ec81197de20f56588a156094ecb88450" }, -+ { 2051, "6b22ccc874833e96551a39da0c0edcaa0d969d92" }, -+ { 2052, "f843141e57875cd669af58744bc60aa9ea59549c" }, -+ { 3072, "09c5fedeaa62c132e673cc3c608a00142273d086" }, -+ { 3074, "b09e95eea9c7b1b007a58accec488301901a7f3d" }, -+ { 3075, "e6226b77b4ada287a8c9bbcf4ed71eec5ce632dc" }, -+ { 4048, "e99394894f855821951ddddf5bfc628547435f5c" }, -+ { 4052, "32d2f1af38be9cfba6cd03d55a254d0b3e1eb382" }, -+ { 4058, "d906552a4f2aca3a22e1fecccbcd183d7289d0ef" }, -+ { 6144, "2e7f62d35a860988e1224dc0543204af19316041" }, -+ { 6150, "d6b89698ee133df46fec9d552fadc328aa5a1b51" }, -+ { 6400, "dff50e90c46853988fa3a4b4ce5dda6945aae976" }, -+ { 6528, "9e63ec0430b96db02d38bc78357a2f63de2ab7f8" }, -+ { 8192, "971eb71ed60394d5ab5abb12e88420bdd41b5992" }, -+ { 8320, "91606a31b46afeaac965cecf87297e791b211013" }, -+ {16384, "547f830a5ec1f5f170ce818f156b1002cabc7569" }, -+ {18432, "f16f272787f3b8d539652e4dc315af6ab4fda0ef" }, -+ { 0, NULL }, -+}; -+ -+/* CryptoKey = 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef; -+ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ * Note: only sizes aligned to 3DES block size (8 bytes) allowed -+ */ -+static MV_CESA_SIZE_TEST tripleDesMdMultiSizeTest502[] = -+{ -+ { 64, "9586962a2aaaef28803dec2e17807a7f" }, -+ { 80, "b7726a03aad490bd6c5a452a89a1b271" }, -+ { 352, "f1ed9563aecc3c0d2766eb2bed3b4e4c" }, -+ { 512, "0f9decb11ab40fe86f4d4d9397bc020e" }, -+ { 1000, "3ba69deac12cab8ff9dff7dbd9669927" }, -+ { 1336, "6cf47bf1e80e03e2c1d0945bc50d37d2" }, -+ { 1344, "4be388dab21ceb3fa1b8d302e9b821f7" }, -+ { 1400, "a58b79fb21dd9bfc6ec93e3b99fb0ef1" }, -+ { 1408, "8bc97379fc2ac3237effcdd4f7a86528" }, -+ { 2048, "1339f03ab3076f25a20bc4cba16eb5bf" }, -+ { 3072, "731204d2d90c4b36ae41f5e1fb874288" }, -+ { 4048, "c028d998cfda5642547b7e1ed5ea16e4" }, -+ { 6144, "b1b19cd910cc51bd22992f1e59f1e068" }, -+ { 6400, "44e4613496ba622deb0e7cb768135a2f" }, -+ { 6528, "3b06b0a86f8db9cd67f9448dfcf10549" }, -+ { 8192, "d581780b7163138a0f412be681457d82" }, -+ {16384, "03b8ac05527faaf1bed03df149c65ccf" }, -+ {18432, "677c8a86a41dab6c5d81b85b8fb10ff6" }, -+ { 0, NULL }, -+}; -+ -+ -+/* CryptoKey = 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef; -+ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 -+ * 0x11, 0x12, 0x13, 0x14 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ * Note: only sizes aligned to 3DES block size (8 bytes) allowed -+ */ -+static MV_CESA_SIZE_TEST tripleDesShaMultiSizeTest503[] = -+{ -+ { 64, "44a1e9bcbfc1429630d9ea68b7a48b0427a684f2" }, -+ { 80, "b2ddeaca91030eab5b95a234ef2c0f6e738ff883" }, -+ { 352, "4b91864c7ff629bdff75d9726421f76705452aaf" }, -+ { 512, "6dd37faceeb2aa98ba74f4242ed6734a4d546af5" }, -+ { 1000, "463661c30300be512a9df40904f0757cde5f1141" }, -+ { 1336, "b931f831d9034fe59c65176400b039fe9c1f44a5" }, -+ { 1344, "af8866b1cd4a4887d6185bfe72470ffdfb3648e1" }, -+ { 1400, "49c6caf07296d5e31d2504d088bc5b20c3ee7cdb" }, -+ { 1408, "fcae8deedbc6ebf0763575dc7e9de075b448a0f4" }, -+ { 2048, "edece5012146c1faa0dd10f50b183ba5d2af58ac" }, -+ { 3072, "5b83625adb43a488b8d64fecf39bb766818547b7" }, -+ { 4048, "d2c533678d26c970293af60f14c8279dc708bfc9" }, -+ { 6144, "b8f67af4f991b08b725f969b049ebf813bfacc5c" }, -+ { 6400, "d9a6c7f746ac7a60ef2edbed2841cf851c25cfb0" }, -+ { 6528, "376792b8c8d18161d15579fb7829e6e3a27e9946" }, -+ { 8192, "d890eabdca195b34ef8724b28360cffa92ae5655" }, -+ {16384, "a167ee52639ec7bf19aee9c6e8f76667c14134b9" }, -+ {18432, "e4396ab56f67296b220985a12078f4a0e365d2cc" }, -+ { 0, NULL }, -+}; -+ -+/* CryptoKey = 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef -+ * IV = 0x12345678, 0x90abcdef -+ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ * Note: only sizes aligned to 3DES block size (8 bytes) allowed -+ */ -+static MV_CESA_SIZE_TEST cbc3desMdMultiSizeTest504[] = -+{ -+ { 64, "8d10e00802460ede0058c139ba48bd2d" }, -+ { 80, "6f463057e1a90e0e91ae505b527bcec0" }, -+ { 352, "4938d48bdf86aece2c6851e7c6079788" }, -+ { 512, "516705d59f3cf810ebf2a13a23a7d42e" }, -+ { 1000, "a5a000ee5c830e67ddc6a2d2e5644b31" }, -+ { 1336, "44af60087b74ed07950088efbe3b126a" }, -+ { 1344, "1f5b39e0577920af731dabbfcf6dfc2a" }, -+ { 1400, "6804ea640e29b9cd39e08bc37dbce734" }, -+ { 1408, "4fb436624b02516fc9d1535466574bf9" }, -+ { 2048, "c909b0985c423d8d86719f701e9e83db" }, -+ { 3072, "cfe0bc34ef97213ee3d3f8b10122db21" }, -+ { 4048, "03ea10b5ae4ddeb20aed6af373082ed1" }, -+ { 6144, "b9a0ff4f87fc14b3c2dc6f0ed0998fdf" }, -+ { 6400, "6995f85d9d4985dd99e974ec7dda9dd6" }, -+ { 6528, "bbbb548ce2fa3d58467f6a6a5168a0e6" }, -+ { 8192, "afe101fbe745bb449ae4f50d10801456" }, -+ {16384, "9741706d0b1c923340c4660ff97cacdf" }, -+ {18432, "b0217becb73cb8f61fd79c7ce9d023fb" }, -+ { 0, NULL }, -+}; -+ -+ -+/* CryptoKey = 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef; -+ * IV = 0x12345678, 0x90abcdef -+ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 -+ * 0x11, 0x12, 0x13, 0x14 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ * Note: only sizes aligned to 3DES block size (8 bytes) allowed -+ */ -+static MV_CESA_SIZE_TEST cbc3desShaMultiSizeTest505[] = -+{ -+ { 64, "409187e5bdb0be4a7754ca3747f7433dc4f01b98" }, -+ { 80, "1b002ed050be743aa98860cf35659646bb8efcc0" }, -+ { 352, "6cbf7ebe50fa4fa6eecc19eca23f9eae553ccfff" }, -+ { 512, "cfb5253fb4bf72b743320c30c7e48c54965853b0" }, -+ { 1000, "95e04e1ca2937e7c5a9aba9e42d2bcdb8a7af21f" }, -+ { 1336, "3b5c1f5eee5837ebf67b83ae01405542d77a6627" }, -+ { 1344, "2b3d42ab25615437f98a1ee310b81d07a02badc2" }, -+ { 1400, "7f8687df7c1af44e4baf3c934b6cca5ab6bc993e" }, -+ { 1408, "473a581c5f04f7527d50793c845471ac87e86430" }, -+ { 2048, "e41d20cae7ebe34e6e828ed62b1e5734019037bb" }, -+ { 3072, "275664afd7a561d804e6b0d204e53939cde653ae" }, -+ { 4048, "0d220cc5b34aeeb46bbbd637dde6290b5a8285a3" }, -+ { 6144, "cb393ddcc8b1c206060625b7d822ef9839e67bc5" }, -+ { 6400, "dd3317e2a627fc04800f74a4b05bfda00fab0347" }, -+ { 6528, "8a74c3b2441ab3f5a7e08895cc432566219a7c41" }, -+ { 8192, "b8e6ef3a549ed0e005bd5b8b1a5fe6689e9711a7" }, -+ {16384, "55f59404008276cdac0e2ba0d193af2d40eac5ce" }, -+ {18432, "86ae6c4fc72369a54cce39938e2d0296cd9c6ec5" }, -+ { 0, NULL }, -+}; -+ -+ -+/* CryptoKey = 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef -+ * IV = 0x12345678, 0x90abcdef -+ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ * Note: only sizes aligned to AES block size (16 bytes) allowed -+ */ -+static MV_CESA_SIZE_TEST cbcAes128md5multiSizeTest506[] = -+{ -+ { 16, "7ca4c2ba866751598720c5c4aa0d6786" }, -+ { 64, "7dba7fb988e80da609b1fea7254bced8" }, -+ { 80, "6b6e863ac5a71d15e3e9b1c86c9ba05f" }, -+ { 352, "a1ceb9c2e3021002400d525187a9f38c" }, -+ { 512, "596c055c1c55db748379223164075641" }, -+ { 1008, "f920989c02f3b3603f53c99d89492377" }, -+ { 1344, "2e496b73759d77ed32ea222dbd2e7b41" }, -+ { 1408, "7178c046b3a8d772efdb6a71c4991ea4" }, -+ { 2048, "a917f0099c69eb94079a8421714b6aad" }, -+ { 3072, "693cd5033d7f5391d3c958519fa9e934" }, -+ { 4048, "139dca91bcff65b3c40771749052906b" }, -+ { 6144, "428d9cef6df4fb70a6e9b6bbe4819e55" }, -+ { 6400, "9c0b909e76daa811e12b1fc17000a0c4" }, -+ { 6528, "ad876f6297186a7be1f1b907ed860eda" }, -+ { 8192, "479cbbaca37dd3191ea1f3e8134a0ef4" }, -+ {16384, "60fda559c74f91df538100c9842f2f15" }, -+ {18432, "4a3eb1cba1fa45f3981270953f720c42" }, -+ { 0, NULL }, -+}; -+ -+ -+/* CryptoKey = 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef, -+ * 0x01234567, 0x89abcdef; -+ * IV = 0x12345678, 0x90abcdef -+ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, -+ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 -+ * 0x11, 0x12, 0x13, 0x14 -+ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") -+ * Note: only sizes aligned to AES block size (16 bytes) allowed -+ */ -+static MV_CESA_SIZE_TEST cbcAes128sha1multiSizeTest507[] = -+{ -+ { 16, "9aa8dc1c45f0946daf78057fa978759c625c1fee" }, -+ { 64, "9f588fc1ede851e5f8b20256abc9979465ae2189" }, -+ { 80, "13558472d1fc1c90dffec6e5136c7203452d509b" }, -+ { 352, "6b93518e006cfaa1f7adb24615e7291fb0a27e06" }, -+ { 512, "096874951a77fbbf333e49d80c096ee2016e09bd" }, -+ { 1008, "696fc203c2e4b5ae0ec5d1db3f623c490bc6dbac" }, -+ { 1344, "79bf77509935ccd3528caaac6a5eb6481f74029b" }, -+ { 1408, "627f9462b95fc188e8cfa7eec15119bdc5d4fcf1" }, -+ { 2048, "3d50d0c005feba92fe41502d609fced9c882b4d1" }, -+ { 3072, "758807e5b983e3a91c06fb218fe0f73f77111e94" }, -+ { 4048, "ca90e85242e33f005da3504416a52098d0d31fb2" }, -+ { 6144, "8044c1d4fd06642dfc46990b4f18b61ef1e972cf" }, -+ { 6400, "166f1f4ea57409f04feba9fb1e39af0e00bd6f43" }, -+ { 6528, "0389016a39485d6e330f8b4215ddf718b404f7e9" }, -+ { 8192, "6df7ee2a8b61d6f7f860ce8dbf778f0c2a5b508b" }, -+ {16384, "a70a6d8dfa1f91ded621c3dbaed34162bc48783f" }, -+ {18432, "8dfad627922ce15df1eed10bdbed49244efa57db" }, -+ { 0, NULL }, -+}; -+ -+ -+void cesaTestPrintStatus(void); -+ -+ -+/*------------------------- LOCAL FUNCTIONs ---------------------------------*/ -+MV_STATUS testCmd(int sid, int iter, MV_CESA_COMMAND* pCmd, -+ MV_CESA_TEST_SESSION* pTestSession, MV_U8* pIV, int ivSize); -+MV_STATUS testClose(int idx); -+MV_STATUS testOpen(int idx); -+void close_session(int sid); -+void cesaTestCheckReady(const MV_CESA_RESULT *r); -+void cesaCheckReady(MV_CESA_RESULT* r); -+void printTestResults(int idx, MV_STATUS status, int checkMode); -+void cesaLastResult(void); -+void cesaTestPrintReq(int req, int offset, int size); -+ -+void cesaTestPrintStatus(void); -+void cesaTestPrintSession(int idx); -+void sizeTest(int testIdx, int iter, int checkMode); -+void multiTest(int iter, int reqSize, int checkMode); -+void oneTest(int testIdx, int caseIdx,int iter, int reqSize, int checkMode); -+void multiSizeTest(int idx, int iter, int checkMode, char* inputData); -+void cesaTest(int iter, int reqSize, int checkMode); -+void cesaOneTest(int testIdx, int caseIdx,int iter, int reqSize, int checkMode); -+void combiTest(int iter, int reqSize, int checkMode); -+void shaTest(int iter, int reqSize, int checkMode); -+void mdTest(int iter, int reqSize, int checkMode); -+void aesTest(int iter, int reqSize, int checkMode); -+void tripleDesTest(int iter, int reqSize, int checkMode); -+void desTest(int iter, int reqSize, int checkMode); -+void cesaTestStop(void); -+MV_STATUS testRun(int idx, int caseIdx, int iter,int reqSize, int checkMode); -+void cesaTestStart(int bufNum, int bufSize); -+ -+ -+static MV_U32 getRate(MV_U32* remainder) -+{ -+ MV_U32 kBits, milliSec, rate; -+ -+ milliSec = 0; -+ if( (cesaEndTicks - cesaBeginTicks) > 0) -+ { -+ milliSec = CESA_TEST_TICK_TO_MS(cesaEndTicks - cesaBeginTicks); -+ } -+ if(milliSec == 0) -+ { -+ if(remainder != NULL) -+ *remainder = 0; -+ return 0; -+ } -+ -+ kBits = (cesaIteration*cesaRateSize*8)/1000; -+ rate = kBits/milliSec; -+ if(remainder != NULL) -+ *remainder = ((kBits % milliSec)*10)/milliSec; -+ -+ return rate; -+} -+ -+static char* extractMbuf(MV_CESA_MBUF *pMbuf, -+ int offset, int size, char* hexStr) -+{ -+ mvCesaCopyFromMbuf((MV_U8*)cesaBinBuffer, pMbuf, offset, size); -+ mvBinToHex((const MV_U8*)cesaBinBuffer, hexStr, size); -+ -+ return hexStr; -+} -+ -+static MV_BOOL cesaCheckMbuf(MV_CESA_MBUF *pMbuf, -+ const char* hexString, int offset, -+ int checkSize) -+{ -+ MV_BOOL isFailed = MV_FALSE; -+ MV_STATUS status; -+ int size = strlen(hexString)/2; -+ int checkedSize = 0; -+/* -+ mvOsPrintf("cesaCheckMbuf: pMbuf=%p, offset=%d, checkSize=%d, mBufSize=%d\n", -+ pMbuf, offset, checkSize, pMbuf->mbufSize); -+*/ -+ if(pMbuf->mbufSize < (checkSize + offset)) -+ { -+ mvOsPrintf("checkSize (%d) is too large: offset=%d, mbufSize=%d\n", -+ checkSize, offset, pMbuf->mbufSize); -+ return MV_TRUE; -+ } -+ status = mvCesaCopyFromMbuf((MV_U8*)cesaBinBuffer, pMbuf, offset, checkSize); -+ if(status != MV_OK) -+ { -+ mvOsPrintf("CesaTest: Can't copy %d bytes from Mbuf=%p to checkBuf=%p\n", -+ checkSize, pMbuf, cesaBinBuffer); -+ return MV_TRUE; -+ } -+/* -+ mvDebugMemDump(cesaBinBuffer, size, 1); -+*/ -+ mvHexToBin(hexString, (MV_U8*)cesaExpBinBuffer, size); -+ -+ /* Compare buffers */ -+ while(checkSize > checkedSize) -+ { -+ size = MV_MIN(size, (checkSize - checkedSize)); -+ if(memcmp(cesaExpBinBuffer, &cesaBinBuffer[checkedSize], size) != 0) -+ { -+ mvOsPrintf("CheckMbuf failed: checkSize=%d, size=%d, checkedSize=%d\n", -+ checkSize, size, checkedSize); -+ mvDebugMemDump(&cesaBinBuffer[checkedSize], size, 1); -+ mvDebugMemDump(cesaExpBinBuffer, size, 1); -+ -+ isFailed = MV_TRUE; -+ break; -+ } -+ checkedSize += size; -+ } -+ -+ return isFailed; -+} -+ -+static MV_STATUS cesaSetMbuf(MV_CESA_MBUF *pMbuf, -+ const char* hexString, -+ int offset, int reqSize) -+{ -+ MV_STATUS status = MV_OK; -+ int copySize, size = strlen(hexString)/2; -+ -+ mvHexToBin(hexString, (MV_U8*)cesaBinBuffer, size); -+ -+ copySize = 0; -+ while(reqSize > copySize) -+ { -+ size = MV_MIN(size, (reqSize - copySize)); -+ -+ status = mvCesaCopyToMbuf((MV_U8*)cesaBinBuffer, pMbuf, offset+copySize, size); -+ if(status != MV_OK) -+ { -+ mvOsPrintf("cesaSetMbuf Error: Copy %d of %d bytes to MBuf\n", -+ copySize, reqSize); -+ break; -+ } -+ copySize += size; -+ } -+ pMbuf->mbufSize = offset+copySize; -+ return status; -+} -+ -+static MV_CESA_TEST_SESSION* getTestSessionDb(int idx, int* pTestIdx) -+{ -+ int testIdx, dbIdx = idx/100; -+ -+ if(dbIdx > MAX_TEST_TYPE) -+ { -+ mvOsPrintf("Wrong index %d - No such test type\n", idx); -+ return NULL; -+ } -+ testIdx = idx % 100; -+ -+ if(testIdx >= cesaTestsDB[dbIdx].numSessions) -+ { -+ mvOsPrintf("Wrong index %d - No such test\n", idx); -+ return NULL; -+ } -+ if(pTestIdx != NULL) -+ *pTestIdx = testIdx; -+ -+ return cesaTestsDB[dbIdx].pSessions; -+} -+ -+/* Debug */ -+void cesaTestPrintReq(int req, int offset, int size) -+{ -+ MV_CESA_MBUF* pMbuf; -+ -+ mvOsPrintf("cesaTestPrintReq: req=%d, offset=%d, size=%d\n", -+ req, offset, size); -+ mvDebugMemDump(cesaCmdRing, 128, 4); -+ -+ pMbuf = cesaCmdRing[req].pSrc; -+ mvCesaDebugMbuf("src", pMbuf, offset,size); -+ pMbuf = cesaCmdRing[req].pDst; -+ mvCesaDebugMbuf("dst", pMbuf, offset, size); -+ -+ cesaTestPrintStatus(); -+} -+ -+void cesaLastResult(void) -+{ -+ mvOsPrintf("Last Result: ReqId = %d, SessionId = %d, rc = (%d)\n", -+ (MV_U32)cesaResult.pReqPrv, cesaResult.sessionId, -+ cesaResult.retCode); -+} -+ -+void printTestResults(int idx, MV_STATUS status, int checkMode) -+{ -+ int testIdx; -+ MV_CESA_TEST_SESSION* pTestSessions = getTestSessionDb(idx, &testIdx); -+ -+ if(pTestSessions == NULL) -+ return; -+ -+ mvOsPrintf("%-35s %4dx%-4d : ", pTestSessions[testIdx].name, -+ cesaIteration, cesaReqSize); -+ if( (status == MV_OK) && -+ (cesaCryptoError == 0) && -+ (cesaError == 0) && -+ (cesaReqIdError == 0) ) -+ { -+ mvOsPrintf("Passed, Rate=%3u.%u Mbps (%5u cpp)\n", -+ cesaRate, cesaRateAfterDot, cesaEndTicks - cesaBeginTicks); -+ } -+ else -+ { -+ mvOsPrintf("Failed, Status = 0x%x\n", status); -+ if(cesaCryptoError > 0) -+ mvOsPrintf("cryptoError : %d\n", cesaCryptoError); -+ if(cesaReqIdError > 0) -+ mvOsPrintf("reqIdError : %d\n", cesaReqIdError); -+ if(cesaError > 0) -+ mvOsPrintf("cesaError : %d\n", cesaError); -+ } -+ if(cesaTestIsrMissCount > 0) -+ mvOsPrintf("cesaIsrMissed : %d\n", cesaTestIsrMissCount); -+} -+ -+void cesaCheckReady(MV_CESA_RESULT* r) -+{ -+ int reqId; -+ MV_CESA_MBUF *pMbuf; -+ MV_BOOL isFailed; -+ -+ cesaResult = *r; -+ reqId = (int)cesaResult.pReqPrv; -+ pMbuf = cesaCmdRing[reqId].pDst; -+ -+/* -+ mvOsPrintf("cesaCheckReady: reqId=%d, checkOffset=%d, checkSize=%d\n", -+ reqId, cesaCheckOffset, cesaCheckSize); -+*/ -+ /* Check expected reqId */ -+ if(reqId != cesaExpReqId) -+ { -+ cesaReqIdError++; -+/* -+ mvOsPrintf("CESA reqId Error: cbIter=%d (%d), reqId=%d, expReqId=%d\n", -+ cesaCbIter, cesaIteration, reqId, cesaExpReqId); -+*/ -+ } -+ else -+ { -+ if( (cesaCheckMode == CESA_FULL_CHECK_MODE) || -+ (cesaCheckMode == CESA_FAST_CHECK_MODE) ) -+ { -+ if(cesaResult.retCode != MV_OK) -+ { -+ cesaError++; -+ -+ mvOsPrintf("CESA Error: cbIter=%d (%d), reqId=%d, rc=%d\n", -+ cesaCbIter, cesaIteration, reqId, cesaResult.retCode); -+ } -+ else -+ { -+ if( (cesaCheckSize > 0) && (cesaOutputHexStr != NULL) ) -+ { -+ /* Check expected output */ -+ -+ isFailed = cesaCheckMbuf(pMbuf, cesaOutputHexStr, cesaCheckOffset, cesaCheckSize); -+ if(isFailed) -+ { -+ mvOsPrintf("CESA Crypto Error: cbIter=%d (%d), reqId=%d\n", -+ cesaCbIter, cesaIteration, reqId); -+ -+ CESA_TEST_DEBUG_PRINT(("Error: reqId=%d, reqSize=%d, checkOffset=%d, checkSize=%d\n", -+ reqId, cesaReqSize, cesaCheckOffset, cesaCheckSize)); -+ -+ CESA_TEST_DEBUG_PRINT(("Output str: %s\n", cesaOutputHexStr)); -+ -+ CESA_TEST_DEBUG_CODE( mvCesaDebugMbuf("error", pMbuf, 0, cesaCheckOffset+cesaCheckSize) ); -+ -+ cesaCryptoError++; -+ } -+ } -+ } -+ } -+ } -+ if(cesaCheckMode == CESA_SHOW_CHECK_MODE) -+ { -+ extractMbuf(pMbuf, cesaCheckOffset, cesaCheckSize, cesaHexBuffer); -+ mvOsPrintf("%4d, %s\n", cesaCheckOffset, cesaHexBuffer); -+ } -+ -+ cesaCbIter++; -+ if(cesaCbIter >= cesaIteration) -+ { -+ cesaCbIter = 0; -+ cesaExpReqId = 0; -+ cesaIsReady = MV_TRUE; -+ -+ cesaEndTicks = CESA_TEST_TICK_GET(); -+ cesaRate = getRate(&cesaRateAfterDot); -+ } -+ else -+ { -+ cesaExpReqId = reqId + 1; -+ if(cesaExpReqId == CESA_DEF_REQ_SIZE) -+ cesaExpReqId = 0; -+ } -+} -+ -+ -+#ifdef MV_NETBSD -+static int cesaTestReadyIsr(void *arg) -+#else -+#ifdef __KERNEL__ -+static irqreturn_t cesaTestReadyIsr( int irq , void *dev_id) -+#endif -+#ifdef MV_VXWORKS -+void cesaTestReadyIsr(void) -+#endif -+#endif -+{ -+ MV_U32 cause; -+ MV_STATUS status; -+ MV_CESA_RESULT result; -+ -+ cesaTestIsrCount++; -+ /* Clear cause register */ -+ cause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); -+ if( (cause & MV_CESA_CAUSE_ACC_DMA_ALL_MASK) == 0) -+ { -+ mvOsPrintf("cesaTestReadyIsr: cause=0x%x\n", cause); -+#ifdef MV_NETBSD -+ return 0; -+#else -+#ifdef __KERNEL__ -+ return 1; -+#else -+ return; -+#endif -+#endif -+ } -+ -+ MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); -+ -+ while(MV_TRUE) -+ { -+ /* Get Ready requests */ -+ status = mvCesaReadyGet(&result); -+ if(status == MV_OK) -+ cesaCheckReady(&result); -+ -+ break; -+ } -+ if( (cesaTestFull == 1) && (status != MV_BUSY) ) -+ { -+ cesaTestFull = 0; -+ CESA_TEST_WAKE_UP(); -+ } -+ -+#ifdef __KERNEL__ -+ return 1; -+#endif -+} -+ -+void -+cesaTestCheckReady(const MV_CESA_RESULT *r) -+{ -+ MV_CESA_RESULT result = *r; -+ -+ cesaCheckReady(&result); -+ -+ if (cesaTestFull == 1) { -+ cesaTestFull = 0; -+ CESA_TEST_WAKE_UP(); -+ } -+} -+ -+static INLINE int open_session(MV_CESA_OPEN_SESSION* pOs) -+{ -+ MV_U16 sid; -+ MV_STATUS status; -+ -+ status = mvCesaSessionOpen(pOs, (short*)&sid); -+ if(status != MV_OK) -+ { -+ mvOsPrintf("CesaTest: Can't open new session - status = 0x%x\n", -+ status); -+ return -1; -+ } -+ -+ return (int)sid; -+} -+ -+void close_session(int sid) -+{ -+ MV_STATUS status; -+ -+ status = mvCesaSessionClose(sid); -+ if(status != MV_OK) -+ { -+ mvOsPrintf("CesaTest: Can't close session %d - status = 0x%x\n", -+ sid, status); -+ } -+} -+ -+MV_STATUS testOpen(int idx) -+{ -+ MV_CESA_OPEN_SESSION os; -+ int sid, i, testIdx; -+ MV_CESA_TEST_SESSION* pTestSession; -+ MV_U16 digestSize = 0; -+ -+ pTestSession = getTestSessionDb(idx, &testIdx); -+ if(pTestSession == NULL) -+ { -+ mvOsPrintf("Test %d is not exist\n", idx); -+ return MV_BAD_PARAM; -+ } -+ pTestSession = &pTestSession[testIdx]; -+ -+ if(pTestSession->sid != -1) -+ { -+ mvOsPrintf("Session for test %d already created: sid=%d\n", -+ idx, pTestSession->sid); -+ return MV_OK; -+ } -+ -+ os.cryptoAlgorithm = pTestSession->cryptoAlgorithm; -+ os.macMode = pTestSession->macAlgorithm; -+ switch(os.macMode) -+ { -+ case MV_CESA_MAC_MD5: -+ case MV_CESA_MAC_HMAC_MD5: -+ digestSize = MV_CESA_MD5_DIGEST_SIZE; -+ break; -+ -+ case MV_CESA_MAC_SHA1: -+ case MV_CESA_MAC_HMAC_SHA1: -+ digestSize = MV_CESA_SHA1_DIGEST_SIZE; -+ break; -+ -+ case MV_CESA_MAC_NULL: -+ digestSize = 0; -+ } -+ os.cryptoMode = pTestSession->cryptoMode; -+ os.direction = pTestSession->direction; -+ os.operation = pTestSession->operation; -+ -+ for(i=0; icryptoKeySize; i++) -+ os.cryptoKey[i] = pTestSession->pCryptoKey[i]; -+ -+ os.cryptoKeyLength = pTestSession->cryptoKeySize; -+ -+ for(i=0; imacKeySize; i++) -+ os.macKey[i] = pTestSession->pMacKey[i]; -+ -+ os.macKeyLength = pTestSession->macKeySize; -+ os.digestSize = digestSize; -+ -+ sid = open_session(&os); -+ if(sid == -1) -+ { -+ mvOsPrintf("Can't open session for test %d: rc=0x%x\n", -+ idx, cesaResult.retCode); -+ return cesaResult.retCode; -+ } -+ CESA_TEST_DEBUG_PRINT(("Opened session: sid = %d\n", sid)); -+ pTestSession->sid = sid; -+ return MV_OK; -+} -+ -+MV_STATUS testClose(int idx) -+{ -+ int testIdx; -+ MV_CESA_TEST_SESSION* pTestSession; -+ -+ pTestSession = getTestSessionDb(idx, &testIdx); -+ if(pTestSession == NULL) -+ { -+ mvOsPrintf("Test %d is not exist\n", idx); -+ return MV_BAD_PARAM; -+ } -+ pTestSession = &pTestSession[testIdx]; -+ -+ if(pTestSession->sid == -1) -+ { -+ mvOsPrintf("Test session %d is not opened\n", idx); -+ return MV_NO_SUCH; -+ } -+ -+ close_session(pTestSession->sid); -+ pTestSession->sid = -1; -+ -+ return MV_OK; -+} -+ -+MV_STATUS testCmd(int sid, int iter, MV_CESA_COMMAND* pCmd, -+ MV_CESA_TEST_SESSION* pTestSession, MV_U8* pIV, int ivSize) -+{ -+ int cmdReqId = 0; -+ int i; -+ MV_STATUS rc = MV_OK; -+ char ivZeroHex[] = "0000"; -+ -+ if(iter == 0) -+ iter = CESA_DEF_ITER_NUM; -+ -+ if(pCmd == NULL) -+ { -+ mvOsPrintf("testCmd failed: pCmd=NULL\n"); -+ return MV_BAD_PARAM; -+ } -+ pCmd->sessionId = sid; -+ -+ cesaCryptoError = 0; -+ cesaReqIdError = 0; -+ cesaError = 0; -+ cesaTestIsrMissCount = 0; -+ cesaIsReady = MV_FALSE; -+ cesaIteration = iter; -+ -+ if(cesaInputHexStr == NULL) -+ cesaInputHexStr = cesaPlainHexEbc; -+ -+ for(i=0; ipSrc = (MV_CESA_MBUF*)(cesaCmdRing[i].pSrc); -+ if(pIV != NULL) -+ { -+ /* If IV from SA - set IV in Source buffer to zeros */ -+ cesaSetMbuf(pCmd->pSrc, ivZeroHex, 0, pCmd->cryptoOffset); -+ cesaSetMbuf(pCmd->pSrc, cesaInputHexStr, pCmd->cryptoOffset, -+ (cesaReqSize - pCmd->cryptoOffset)); -+ } -+ else -+ { -+ cesaSetMbuf(pCmd->pSrc, cesaInputHexStr, 0, cesaReqSize); -+ } -+ pCmd->pDst = (MV_CESA_MBUF*)(cesaCmdRing[i].pDst); -+ cesaSetMbuf(pCmd->pDst, cesaNullPlainHexText, 0, cesaReqSize); -+ -+ memcpy(&cesaCmdRing[i], pCmd, sizeof(*pCmd)); -+ } -+ -+ if(cesaCheckMode == CESA_SW_SHOW_CHECK_MODE) -+ { -+ MV_U8 pDigest[MV_CESA_MAX_DIGEST_SIZE]; -+ -+ if(pTestSession->macAlgorithm == MV_CESA_MAC_MD5) -+ { -+ mvMD5(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, pDigest); -+ mvOsPrintf("SW HASH_MD5: reqSize=%d, macLength=%d\n", -+ cesaReqSize, pCmd->macLength); -+ mvDebugMemDump(pDigest, MV_CESA_MD5_DIGEST_SIZE, 1); -+ return MV_OK; -+ } -+ if(pTestSession->macAlgorithm == MV_CESA_MAC_SHA1) -+ { -+ mvSHA1(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, pDigest); -+ mvOsPrintf("SW HASH_SHA1: reqSize=%d, macLength=%d\n", -+ cesaReqSize, pCmd->macLength); -+ mvDebugMemDump(pDigest, MV_CESA_SHA1_DIGEST_SIZE, 1); -+ return MV_OK; -+ } -+ } -+ -+ cesaBeginTicks = CESA_TEST_TICK_GET(); -+ CESA_TEST_DEBUG_CODE( memset(cesaTestTrace, 0, sizeof(cesaTestTrace)); -+ cesaTestTraceIdx = 0; -+ ); -+ -+ if(cesaCheckMode == CESA_SW_NULL_CHECK_MODE) -+ { -+ volatile MV_U8 pDigest[MV_CESA_MAX_DIGEST_SIZE]; -+ -+ for(i=0; imacAlgorithm == MV_CESA_MAC_MD5) -+ { -+ mvMD5(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, (unsigned char*)pDigest); -+ } -+ if(pTestSession->macAlgorithm == MV_CESA_MAC_SHA1) -+ { -+ mvSHA1(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, (MV_U8 *)pDigest); -+ } -+ } -+ cesaEndTicks = CESA_TEST_TICK_GET(); -+ cesaRate = getRate(&cesaRateAfterDot); -+ cesaIsReady = MV_TRUE; -+ -+ return MV_OK; -+ } -+ -+ /*cesaTestIsrCount = 0;*/ -+ /*mvCesaDebugStatsClear();*/ -+ -+#ifndef MV_NETBSD -+ MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); -+#endif -+ -+ for(i=0; ipReqPrv = (void*)cmdReqId; -+ -+ CESA_TEST_LOCK(flags); -+ -+ rc = mvCesaAction(pCmd); -+ if(rc == MV_NO_RESOURCE) -+ cesaTestFull = 1; -+ -+ CESA_TEST_UNLOCK(flags); -+ -+ if(rc == MV_NO_RESOURCE) -+ { -+ CESA_TEST_LOCK(flags); -+ CESA_TEST_WAIT( (cesaTestFull == 0), 100); -+ CESA_TEST_UNLOCK(flags); -+ if(cesaTestFull == 1) -+ { -+ mvOsPrintf("CESA Test timeout: i=%d, iter=%d, cesaTestFull=%d\n", -+ i, iter, cesaTestFull); -+ cesaTestFull = 0; -+ return MV_TIMEOUT; -+ } -+ -+ CESA_TEST_LOCK(flags); -+ -+ rc = mvCesaAction(pCmd); -+ -+ CESA_TEST_UNLOCK(flags); -+ } -+ if( (rc != MV_OK) && (rc != MV_NO_MORE) ) -+ { -+ mvOsPrintf("mvCesaAction failed: rc=%d\n", rc); -+ return rc; -+ } -+ -+ cmdReqId++; -+ if(cmdReqId >= CESA_DEF_REQ_SIZE) -+ cmdReqId = 0; -+ -+#ifdef MV_LINUX -+ /* Reschedule each 16 requests */ -+ if( (i & 0xF) == 0) -+ schedule(); -+#endif -+ } -+ return MV_OK; -+} -+ -+void cesaTestStart(int bufNum, int bufSize) -+{ -+ int i, j, idx; -+ MV_CESA_MBUF *pMbufSrc, *pMbufDst; -+ MV_BUF_INFO *pFragsSrc, *pFragsDst; -+ char *pBuf; -+#ifndef MV_NETBSD -+ int numOfSessions, queueDepth; -+ char *pSram; -+ MV_STATUS status; -+ MV_CPU_DEC_WIN addrDecWin; -+#endif -+ -+ cesaCmdRing = mvOsMalloc(sizeof(MV_CESA_COMMAND) * CESA_DEF_REQ_SIZE); -+ if(cesaCmdRing == NULL) -+ { -+ mvOsPrintf("testStart: Can't allocate %ld bytes of memory\n", -+ sizeof(MV_CESA_COMMAND) * CESA_DEF_REQ_SIZE); -+ return; -+ } -+ memset(cesaCmdRing, 0, sizeof(MV_CESA_COMMAND) * CESA_DEF_REQ_SIZE); -+ -+ if(bufNum == 0) -+ bufNum = CESA_DEF_BUF_NUM; -+ -+ if(bufSize == 0) -+ bufSize = CESA_DEF_BUF_SIZE; -+ -+ cesaBufNum = bufNum; -+ cesaBufSize = bufSize; -+ mvOsPrintf("CESA test started: bufNum = %d, bufSize = %d\n", -+ bufNum, bufSize); -+ -+ cesaHexBuffer = mvOsMalloc(2*bufNum*bufSize); -+ if(cesaHexBuffer == NULL) -+ { -+ mvOsPrintf("testStart: Can't malloc %d bytes for cesaHexBuffer.\n", -+ 2*bufNum*bufSize); -+ return; -+ } -+ memset(cesaHexBuffer, 0, (2*bufNum*bufSize)); -+ -+ cesaBinBuffer = mvOsMalloc(bufNum*bufSize); -+ if(cesaBinBuffer == NULL) -+ { -+ mvOsPrintf("testStart: Can't malloc %d bytes for cesaBinBuffer\n", -+ bufNum*bufSize); -+ return; -+ } -+ memset(cesaBinBuffer, 0, (bufNum*bufSize)); -+ -+ cesaExpBinBuffer = mvOsMalloc(bufNum*bufSize); -+ if(cesaExpBinBuffer == NULL) -+ { -+ mvOsPrintf("testStart: Can't malloc %d bytes for cesaExpBinBuffer\n", -+ bufNum*bufSize); -+ return; -+ } -+ memset(cesaExpBinBuffer, 0, (bufNum*bufSize)); -+ -+ CESA_TEST_WAIT_INIT(); -+ -+ pMbufSrc = mvOsMalloc(sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); -+ pFragsSrc = mvOsMalloc(sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); -+ -+ pMbufDst = mvOsMalloc(sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); -+ pFragsDst = mvOsMalloc(sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); -+ -+ if( (pMbufSrc == NULL) || (pFragsSrc == NULL) || -+ (pMbufDst == NULL) || (pFragsDst == NULL) ) -+ { -+ mvOsPrintf("testStart: Can't malloc Src and Dst pMbuf and pFrags structures.\n"); -+ /* !!!! Dima cesaTestCleanup();*/ -+ return; -+ } -+ -+ memset(pMbufSrc, 0, sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); -+ memset(pFragsSrc, 0, sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); -+ -+ memset(pMbufDst, 0, sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); -+ memset(pFragsDst, 0, sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); -+ -+ mvOsPrintf("Cesa Test Start: pMbufSrc=%p, pFragsSrc=%p, pMbufDst=%p, pFragsDst=%p\n", -+ pMbufSrc, pFragsSrc, pMbufDst, pFragsDst); -+ -+ idx = 0; -+ for(i=0; ipFrags = &pFragsSrc[idx]; -+ cesaCmdRing[i].pSrc->numFrags = bufNum; -+ cesaCmdRing[i].pSrc->mbufSize = 0; -+ -+ cesaCmdRing[i].pDst = &pMbufDst[i]; -+ cesaCmdRing[i].pDst->pFrags = &pFragsDst[idx]; -+ cesaCmdRing[i].pDst->numFrags = bufNum; -+ cesaCmdRing[i].pDst->mbufSize = 0; -+ -+ for(j=0; jpFrags[j].bufVirtPtr = (MV_U8*)pBuf; -+ cesaCmdRing[i].pSrc->pFrags[j].bufSize = bufSize; -+ pBuf += bufSize; -+ cesaCmdRing[i].pDst->pFrags[j].bufVirtPtr = (MV_U8*)pBuf; -+ cesaCmdRing[i].pDst->pFrags[j].bufSize = bufSize; -+ pBuf += bufSize; -+ } -+ idx += bufNum; -+ } -+ -+#ifndef MV_NETBSD -+ if (mvCpuIfTargetWinGet(CRYPT_ENG, &addrDecWin) == MV_OK) -+ pSram = (char*)addrDecWin.addrWin.baseLow; -+ else -+ { -+ mvOsPrintf("mvCesaInit: ERR. mvCpuIfTargetWinGet failed\n"); -+ return; -+ } -+ -+#ifdef MV_CESA_NO_SRAM -+ pSram = mvOsMalloc(4*1024+8); -+ if(pSram == NULL) -+ { -+ mvOsPrintf("CesaTest: can't allocate %d bytes for SRAM simulation\n", -+ 4*1024+8); -+ /* !!!! Dima cesaTestCleanup();*/ -+ return; -+ } -+ pSram = (MV_U8*)MV_ALIGN_UP((MV_U32)pSram, 8); -+#endif /* MV_CESA_NO_SRAM */ -+ -+ numOfSessions = CESA_DEF_SESSION_NUM; -+ queueDepth = CESA_DEF_REQ_SIZE - MV_CESA_MAX_CHAN; -+ -+ status = mvCesaInit(numOfSessions, queueDepth, pSram, NULL); -+ if(status != MV_OK) -+ { -+ mvOsPrintf("mvCesaInit is Failed: status = 0x%x\n", status); -+ /* !!!! Dima cesaTestCleanup();*/ -+ return; -+ } -+#endif /* !MV_NETBSD */ -+ -+ /* Prepare data for tests */ -+ for(i=0; i<50; i++) -+ strcat((char*)cesaDataHexStr3, "dd"); -+ -+ strcpy((char*)cesaDataAndMd5digest3, cesaDataHexStr3); -+ strcpy((char*)cesaDataAndSha1digest3, cesaDataHexStr3); -+ -+ /* Digest must be 8 byte aligned */ -+ for(; i<56; i++) -+ { -+ strcat((char*)cesaDataAndMd5digest3, "00"); -+ strcat((char*)cesaDataAndSha1digest3, "00"); -+ } -+ strcat((char*)cesaDataAndMd5digest3, cesaHmacMd5digestHex3); -+ strcat((char*)cesaDataAndSha1digest3, cesaHmacSha1digestHex3); -+ -+#ifndef MV_NETBSD -+ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); -+ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, MV_CESA_CAUSE_ACC_DMA_MASK); -+#endif -+ -+#ifdef MV_VXWORKS -+ { -+ MV_STATUS status; -+ -+ status = intConnect((VOIDFUNCPTR *)INT_LVL_CESA, cesaTestReadyIsr, (int)NULL); -+ if (status != OK) -+ { -+ mvOsPrintf("CESA: Can't connect CESA (%d) interrupt, status=0x%x \n", -+ INT_LVL_CESA, status); -+ /* !!!! Dima cesaTestCleanup();*/ -+ return; -+ } -+ cesaSemId = semMCreate(SEM_Q_PRIORITY | SEM_INVERSION_SAFE | SEM_DELETE_SAFE); -+ if(cesaSemId == NULL) -+ { -+ mvOsPrintf("cesaTestStart: Can't create semaphore\n"); -+ return; -+ } -+ intEnable(INT_LVL_CESA); -+ } -+#endif /* MV_VXWORKS */ -+ -+#if !defined(MV_NETBSD) && defined(__KERNEL__) -+ if( request_irq(CESA_IRQ, cesaTestReadyIsr, (SA_INTERRUPT) , "cesa_test", NULL ) ) -+ { -+ mvOsPrintf( "cannot assign irq\n" ); -+ /* !!!! Dima cesaTestCleanup();*/ -+ return; -+ } -+ spin_lock_init( &cesaLock ); -+#endif -+} -+ -+MV_STATUS testRun(int idx, int caseIdx, int iter, -+ int reqSize, int checkMode) -+{ -+ int testIdx, count, sid, digestSize; -+ int blockSize; -+ MV_CESA_TEST_SESSION* pTestSession; -+ MV_CESA_COMMAND cmd; -+ MV_STATUS status; -+ -+ memset(&cmd, 0, sizeof(cmd)); -+ -+ pTestSession = getTestSessionDb(idx, &testIdx); -+ if(pTestSession == NULL) -+ { -+ mvOsPrintf("Test %d is not exist\n", idx); -+ return MV_BAD_PARAM; -+ } -+ pTestSession = &pTestSession[testIdx]; -+ -+ sid = pTestSession->sid; -+ if(sid == -1) -+ { -+ mvOsPrintf("Test %d is not opened\n", idx); -+ return MV_BAD_STATE; -+ } -+ switch(pTestSession->cryptoAlgorithm) -+ { -+ case MV_CESA_CRYPTO_DES: -+ case MV_CESA_CRYPTO_3DES: -+ blockSize = MV_CESA_DES_BLOCK_SIZE; -+ break; -+ -+ case MV_CESA_CRYPTO_AES: -+ blockSize = MV_CESA_AES_BLOCK_SIZE; -+ break; -+ -+ case MV_CESA_CRYPTO_NULL: -+ blockSize = 0; -+ break; -+ -+ default: -+ mvOsPrintf("cesaTestRun: Bad CryptoAlgorithm=%d\n", -+ pTestSession->cryptoAlgorithm); -+ return MV_BAD_PARAM; -+ } -+ switch(pTestSession->macAlgorithm) -+ { -+ case MV_CESA_MAC_MD5: -+ case MV_CESA_MAC_HMAC_MD5: -+ digestSize = MV_CESA_MD5_DIGEST_SIZE; -+ break; -+ -+ case MV_CESA_MAC_SHA1: -+ case MV_CESA_MAC_HMAC_SHA1: -+ digestSize = MV_CESA_SHA1_DIGEST_SIZE; -+ break; -+ default: -+ digestSize = 0; -+ } -+ -+ if(iter == 0) -+ iter = CESA_DEF_ITER_NUM; -+ -+ if(pTestSession->direction == MV_CESA_DIR_ENCODE) -+ { -+ cesaOutputHexStr = cesaTestCases[caseIdx].cipherHexStr; -+ cesaInputHexStr = cesaTestCases[caseIdx].plainHexStr; -+ } -+ else -+ { -+ cesaOutputHexStr = cesaTestCases[caseIdx].plainHexStr; -+ cesaInputHexStr = cesaTestCases[caseIdx].cipherHexStr; -+ } -+ -+ cmd.sessionId = sid; -+ if(checkMode == CESA_FAST_CHECK_MODE) -+ { -+ cmd.cryptoLength = cesaTestCases[caseIdx].cryptoLength; -+ cmd.macLength = cesaTestCases[caseIdx].macLength; -+ } -+ else -+ { -+ cmd.cryptoLength = reqSize; -+ cmd.macLength = reqSize; -+ } -+ cesaRateSize = cmd.cryptoLength; -+ cesaReqSize = cmd.cryptoLength; -+ cmd.cryptoOffset = 0; -+ if(pTestSession->operation != MV_CESA_MAC_ONLY) -+ { -+ if( (pTestSession->cryptoMode == MV_CESA_CRYPTO_CBC) || -+ (pTestSession->cryptoMode == MV_CESA_CRYPTO_CTR) ) -+ { -+ cmd.ivOffset = 0; -+ cmd.cryptoOffset = blockSize; -+ if(cesaTestCases[caseIdx].pCryptoIV == NULL) -+ { -+ cmd.ivFromUser = 1; -+ } -+ else -+ { -+ cmd.ivFromUser = 0; -+ mvCesaCryptoIvSet(cesaTestCases[caseIdx].pCryptoIV, blockSize); -+ } -+ cesaReqSize = cmd.cryptoOffset + cmd.cryptoLength; -+ } -+ } -+ -+/* -+ mvOsPrintf("ivFromUser=%d, cryptoLength=%d, cesaReqSize=%d, cryptoOffset=%d\n", -+ cmd.ivFromUser, cmd.cryptoLength, cesaReqSize, cmd.cryptoOffset); -+*/ -+ if(pTestSession->operation != MV_CESA_CRYPTO_ONLY) -+ { -+ cmd.macOffset = cmd.cryptoOffset; -+ -+ if(cesaTestCases[caseIdx].digestOffset == -1) -+ { -+ cmd.digestOffset = cmd.macOffset + cmd.macLength; -+ cmd.digestOffset = MV_ALIGN_UP(cmd.digestOffset, 8); -+ } -+ else -+ { -+ cmd.digestOffset = cesaTestCases[caseIdx].digestOffset; -+ } -+ if( (cmd.digestOffset + digestSize) > cesaReqSize) -+ cesaReqSize = cmd.digestOffset + digestSize; -+ } -+ -+ cesaCheckMode = checkMode; -+ -+ if(checkMode == CESA_NULL_CHECK_MODE) -+ { -+ cesaCheckSize = 0; -+ cesaCheckOffset = 0; -+ } -+ else -+ { -+ if(pTestSession->operation == MV_CESA_CRYPTO_ONLY) -+ { -+ cesaCheckOffset = 0; -+ cesaCheckSize = cmd.cryptoLength; -+ } -+ else -+ { -+ cesaCheckSize = digestSize; -+ cesaCheckOffset = cmd.digestOffset; -+ } -+ } -+/* -+ mvOsPrintf("reqSize=%d, checkSize=%d, checkOffset=%d, checkMode=%d\n", -+ cesaReqSize, cesaCheckSize, cesaCheckOffset, cesaCheckMode); -+ -+ mvOsPrintf("blockSize=%d, ivOffset=%d, ivFromUser=%d, crOffset=%d, crLength=%d\n", -+ blockSize, cmd.ivOffset, cmd.ivFromUser, -+ cmd.cryptoOffset, cmd.cryptoLength); -+ -+ mvOsPrintf("macOffset=%d, digestOffset=%d, macLength=%d\n", -+ cmd.macOffset, cmd.digestOffset, cmd.macLength); -+*/ -+ status = testCmd(sid, iter, &cmd, pTestSession, -+ cesaTestCases[caseIdx].pCryptoIV, blockSize); -+ -+ if(status != MV_OK) -+ return status; -+ -+ /* Wait when all callbacks is received */ -+ count = 0; -+ while(cesaIsReady == MV_FALSE) -+ { -+ mvOsSleep(10); -+ count++; -+ if(count > 100) -+ { -+ mvOsPrintf("testRun: Timeout occured\n"); -+ return MV_TIMEOUT; -+ } -+ } -+ -+ return MV_OK; -+} -+ -+ -+void cesaTestStop(void) -+{ -+ MV_CESA_MBUF *pMbufSrc, *pMbufDst; -+ MV_BUF_INFO *pFragsSrc, *pFragsDst; -+ int i; -+ -+ /* Release all allocated memories */ -+ pMbufSrc = (MV_CESA_MBUF*)(cesaCmdRing[0].pSrc); -+ pFragsSrc = cesaCmdRing[0].pSrc->pFrags; -+ -+ pMbufDst = (MV_CESA_MBUF*)(cesaCmdRing[0].pDst); -+ pFragsDst = cesaCmdRing[0].pDst->pFrags; -+ -+ mvOsFree(pMbufSrc); -+ mvOsFree(pMbufDst); -+ mvOsFree(pFragsSrc); -+ mvOsFree(pFragsDst); -+ -+ for(i=0; i 0) -+ cryptoError++; -+ if(cesaReqIdError > 0) -+ reqIdError++; -+ -+ testClose(idx); -+ } -+ } -+ if(cryptoError > 0) -+ mvOsPrintf("cryptoError : %d\n", cryptoError); -+ if(reqIdError > 0) -+ mvOsPrintf("reqIdError : %d\n", reqIdError); -+ -+ if(openErrors > 0) -+ { -+ mvOsPrintf("Open Errors = %d\n", openErrors); -+ for(i=0; i<100; i++) -+ { -+ if(openErrDisp[i] != 0) -+ mvOsPrintf("Error %d - occurs %d times\n", i, openErrDisp[i]); -+ } -+ } -+} -+ -+ -+void loopback_test(int idx, int iter, int size, char* pPlainData) -+{ -+} -+ -+ -+#if defined(MV_VXWORKS) -+int testMode = 0; -+unsigned __TASKCONV cesaTask(void* args) -+{ -+ int reqSize = cesaReqSize; -+ -+ if(testMode == 0) -+ { -+ cesaOneTest(cesaTestIdx, cesaCaseIdx, cesaIteration, -+ reqSize, cesaCheckMode); -+ } -+ else -+ { -+ if(testMode == 1) -+ { -+ cesaTest(cesaIteration, reqSize, cesaCheckMode); -+ combiTest(cesaIteration, reqSize, cesaCheckMode); -+ } -+ else -+ { -+ multiSizeTest(cesaIdx, cesaIteration, cesaCheckMode, NULL); -+ } -+ } -+ return 0; -+} -+ -+void oneTest(int testIdx, int caseIdx, -+ int iter, int reqSize, int checkMode) -+{ -+ long rc; -+ -+ cesaIteration = iter; -+ cesaReqSize = cesaRateSize = reqSize; -+ cesaCheckMode = checkMode; -+ testMode = 0; -+ cesaTestIdx = testIdx; -+ cesaCaseIdx = caseIdx; -+ rc = mvOsTaskCreate("CESA_T", 100, 4*1024, cesaTask, NULL, &cesaTaskId); -+ if (rc != MV_OK) -+ { -+ mvOsPrintf("hMW: Can't create CESA multiCmd test task, rc = %ld\n", rc); -+ } -+} -+ -+void multiTest(int iter, int reqSize, int checkMode) -+{ -+ long rc; -+ -+ cesaIteration = iter; -+ cesaCheckMode = checkMode; -+ cesaReqSize = reqSize; -+ testMode = 1; -+ rc = mvOsTaskCreate("CESA_T", 100, 4*1024, cesaTask, NULL, &cesaTaskId); -+ if (rc != MV_OK) -+ { -+ mvOsPrintf("hMW: Can't create CESA multiCmd test task, rc = %ld\n", rc); -+ } -+} -+ -+void sizeTest(int testIdx, int iter, int checkMode) -+{ -+ long rc; -+ -+ cesaIteration = iter; -+ cesaCheckMode = checkMode; -+ testMode = 2; -+ cesaIdx = testIdx; -+ rc = mvOsTaskCreate("CESA_T", 100, 4*1024, cesaTask, NULL, &cesaTaskId); -+ if (rc != MV_OK) -+ { -+ mvOsPrintf("hMW: Can't create CESA test task, rc = %ld\n", rc); -+ } -+} -+ -+#endif /* MV_VXWORKS */ -+ -+extern void mvCesaDebugSA(short sid, int mode); -+void cesaTestPrintSession(int idx) -+{ -+ int testIdx; -+ MV_CESA_TEST_SESSION* pTestSession; -+ -+ pTestSession = getTestSessionDb(idx, &testIdx); -+ if(pTestSession == NULL) -+ { -+ mvOsPrintf("Test %d is not exist\n", idx); -+ return; -+ } -+ pTestSession = &pTestSession[testIdx]; -+ -+ if(pTestSession->sid == -1) -+ { -+ mvOsPrintf("Test session %d is not opened\n", idx); -+ return; -+ } -+ -+ mvCesaDebugSA(pTestSession->sid, 1); -+} -+ -+void cesaTestPrintStatus(void) -+{ -+ mvOsPrintf("\n\t Cesa Test Status\n\n"); -+ -+ mvOsPrintf("isrCount=%d\n", -+ cesaTestIsrCount); -+ -+#ifdef CESA_TEST_DEBUG -+ { -+ int i, j; -+ j = cesaTestTraceIdx; -+ mvOsPrintf("No Type Cause rCause iCause Res Time pReady pProc pEmpty\n"); -+ for(i=0; itable = mvOsMalloc(numOfEntries*sizeof(MV_LRU_ENTRY)); -+ if(pLruCache->table == NULL) -+ { -+ mvOsFree(pLruCache); -+ return NULL; -+ } -+ memset(pLruCache->table, 0, numOfEntries*sizeof(MV_LRU_ENTRY)); -+ pLruCache->tableSize = numOfEntries; -+ -+ for(i=0; itable[i].next = i+1; -+ pLruCache->table[i].prev = i-1; -+ } -+ pLruCache->least = 0; -+ pLruCache->most = numOfEntries-1; -+ -+ return pLruCache; -+} -+ -+void mvLruCacheFinish(MV_LRU_CACHE* pLruCache) -+{ -+ mvOsFree(pLruCache->table); -+ mvOsFree(pLruCache); -+} -+ -+/* Update LRU cache database after using cache Index */ -+void mvLruCacheIdxUpdate(MV_LRU_CACHE* pLruHndl, int cacheIdx) -+{ -+ int prev, next; -+ -+ if(cacheIdx == pLruHndl->most) -+ return; -+ -+ next = pLruHndl->table[cacheIdx].next; -+ if(cacheIdx == pLruHndl->least) -+ { -+ pLruHndl->least = next; -+ } -+ else -+ { -+ prev = pLruHndl->table[cacheIdx].prev; -+ -+ pLruHndl->table[next].prev = prev; -+ pLruHndl->table[prev].next = next; -+ } -+ -+ pLruHndl->table[pLruHndl->most].next = cacheIdx; -+ pLruHndl->table[cacheIdx].prev = pLruHndl->most; -+ pLruHndl->most = cacheIdx; -+} -+ -+/* Delete LRU cache entry */ -+void mvLruCacheIdxDelete(MV_LRU_CACHE* pLruHndl, int cacheIdx) -+{ -+ int prev, next; -+ -+ if(cacheIdx == pLruHndl->least) -+ return; -+ -+ prev = pLruHndl->table[cacheIdx].prev; -+ if(cacheIdx == pLruHndl->most) -+ { -+ pLruHndl->most = prev; -+ } -+ else -+ { -+ next = pLruHndl->table[cacheIdx].next; -+ -+ pLruHndl->table[next].prev = prev; -+ pLruHndl->table[prev].next = next; -+ } -+ pLruHndl->table[pLruHndl->least].prev = cacheIdx; -+ pLruHndl->table[cacheIdx].next = pLruHndl->least; -+ pLruHndl->least = cacheIdx; -+} -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvLru.h linux-3.0.4/crypto/ocf/kirkwood/cesa/mvLru.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvLru.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/cesa/mvLru.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,112 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+/******************************************************************************* -+* mvLru.h - Header File for Least Recently Used Cache algorithm -+* -+* DESCRIPTION: -+* This header file contains macros typedefs and function declaration for -+* the Least Recently Used Cache algorithm. -+* -+*******************************************************************************/ -+ -+#ifndef __mvLru_h__ -+#define __mvLru_h__ -+ -+ -+typedef struct -+{ -+ int next; -+ int prev; -+} MV_LRU_ENTRY; -+ -+typedef struct -+{ -+ int least; -+ int most; -+ MV_LRU_ENTRY* table; -+ int tableSize; -+ -+}MV_LRU_CACHE; -+ -+ -+/* Find Cache index for replacement LRU */ -+static INLINE int mvLruCacheIdxFind(MV_LRU_CACHE* pLruHndl) -+{ -+ return pLruHndl->least; -+} -+ -+/* Init LRU cache module */ -+MV_LRU_CACHE* mvLruCacheInit(int numOfEntries); -+ -+/* Finish LRU cache module */ -+void mvLruCacheFinish(MV_LRU_CACHE* pLruHndl); -+ -+/* Update LRU cache database after using cache Index */ -+void mvLruCacheIdxUpdate(MV_LRU_CACHE* pLruHndl, int cacheIdx); -+ -+/* Delete LRU cache entry */ -+void mvLruCacheIdxDelete(MV_LRU_CACHE* pLruHndl, int cacheIdx); -+ -+ -+#endif /* __mvLru_h__ */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvMD5.c linux-3.0.4/crypto/ocf/kirkwood/cesa/mvMD5.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvMD5.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/cesa/mvMD5.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,349 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "mvOs.h" -+#include "mvMD5.h" -+ -+static void mvMD5Transform(MV_U32 buf[4], MV_U32 const in[MV_MD5_MAC_LEN]); -+ -+#ifdef MV_CPU_LE -+#define mvByteReverse(buf, len) /* Nothing */ -+#else -+static void mvByteReverse(unsigned char *buf, unsigned longs); -+ -+/* -+ * Note: this code is harmless on little-endian machines. -+ */ -+static void mvByteReverse(unsigned char *buf, unsigned longs) -+{ -+ MV_U32 t; -+ -+ do -+ { -+ t = (MV_U32) ((unsigned) buf[3] << 8 | buf[2]) << 16 | -+ ((unsigned) buf[1] << 8 | buf[0]); -+ *(MV_U32 *) buf = t; -+ buf += 4; -+ } while (--longs); -+} -+#endif -+ -+/* -+ * Start MD5 accumulation. Set bit count to 0 and buffer to mysterious -+ * initialization constants. -+ */ -+void mvMD5Init(MV_MD5_CONTEXT *ctx) -+{ -+ ctx->buf[0] = 0x67452301; -+ ctx->buf[1] = 0xefcdab89; -+ ctx->buf[2] = 0x98badcfe; -+ ctx->buf[3] = 0x10325476; -+ -+ ctx->bits[0] = 0; -+ ctx->bits[1] = 0; -+} -+ -+/* -+ * Update context to reflect the concatenation of another buffer full -+ * of bytes. -+ */ -+void mvMD5Update(MV_MD5_CONTEXT *ctx, unsigned char const *buf, unsigned len) -+{ -+ MV_U32 t; -+ -+ /* Update bitcount */ -+ -+ t = ctx->bits[0]; -+ if ((ctx->bits[0] = t + ((MV_U32) len << 3)) < t) -+ ctx->bits[1]++; /* Carry from low to high */ -+ ctx->bits[1] += len >> 29; -+ -+ t = (t >> 3) & 0x3f; /* Bytes already in shsInfo->data */ -+ -+ /* Handle any leading odd-sized chunks */ -+ -+ if (t) -+ { -+ unsigned char *p = (unsigned char *) ctx->in + t; -+ -+ t = 64 - t; -+ if (len < t) -+ { -+ memcpy(p, buf, len); -+ return; -+ } -+ memcpy(p, buf, t); -+ mvByteReverse(ctx->in, MV_MD5_MAC_LEN); -+ mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in); -+ buf += t; -+ len -= t; -+ } -+ /* Process data in 64-byte chunks */ -+ -+ while (len >= 64) -+ { -+ memcpy(ctx->in, buf, 64); -+ mvByteReverse(ctx->in, MV_MD5_MAC_LEN); -+ mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in); -+ buf += 64; -+ len -= 64; -+ } -+ -+ /* Handle any remaining bytes of data. */ -+ -+ memcpy(ctx->in, buf, len); -+} -+ -+/* -+ * Final wrapup - pad to 64-byte boundary with the bit pattern -+ * 1 0* (64-bit count of bits processed, MSB-first) -+ */ -+void mvMD5Final(unsigned char digest[MV_MD5_MAC_LEN], MV_MD5_CONTEXT *ctx) -+{ -+ unsigned count; -+ unsigned char *p; -+ -+ /* Compute number of bytes mod 64 */ -+ count = (ctx->bits[0] >> 3) & 0x3F; -+ -+ /* Set the first char of padding to 0x80. This is safe since there is -+ always at least one byte free */ -+ p = ctx->in + count; -+ *p++ = 0x80; -+ -+ /* Bytes of padding needed to make 64 bytes */ -+ count = 64 - 1 - count; -+ -+ /* Pad out to 56 mod 64 */ -+ if (count < 8) -+ { -+ /* Two lots of padding: Pad the first block to 64 bytes */ -+ memset(p, 0, count); -+ mvByteReverse(ctx->in, MV_MD5_MAC_LEN); -+ mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in); -+ -+ /* Now fill the next block with 56 bytes */ -+ memset(ctx->in, 0, 56); -+ } -+ else -+ { -+ /* Pad block to 56 bytes */ -+ memset(p, 0, count - 8); -+ } -+ mvByteReverse(ctx->in, 14); -+ -+ /* Append length in bits and transform */ -+ ((MV_U32 *) ctx->in)[14] = ctx->bits[0]; -+ ((MV_U32 *) ctx->in)[15] = ctx->bits[1]; -+ -+ mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in); -+ mvByteReverse((unsigned char *) ctx->buf, 4); -+ memcpy(digest, ctx->buf, MV_MD5_MAC_LEN); -+ memset(ctx, 0, sizeof(ctx)); /* In case it's sensitive */ -+} -+ -+/* The four core functions - F1 is optimized somewhat */ -+ -+/* #define F1(x, y, z) (x & y | ~x & z) */ -+#define F1(x, y, z) (z ^ (x & (y ^ z))) -+#define F2(x, y, z) F1(z, x, y) -+#define F3(x, y, z) (x ^ y ^ z) -+#define F4(x, y, z) (y ^ (x | ~z)) -+ -+/* This is the central step in the MD5 algorithm. */ -+#define MD5STEP(f, w, x, y, z, data, s) \ -+ ( w += f(x, y, z) + data, w = w<>(32-s), w += x ) -+ -+/* -+ * The core of the MD5 algorithm, this alters an existing MD5 hash to -+ * reflect the addition of 16 longwords of new data. MD5Update blocks -+ * the data and converts bytes into longwords for this routine. -+ */ -+static void mvMD5Transform(MV_U32 buf[4], MV_U32 const in[MV_MD5_MAC_LEN]) -+{ -+ register MV_U32 a, b, c, d; -+ -+ a = buf[0]; -+ b = buf[1]; -+ c = buf[2]; -+ d = buf[3]; -+ -+ MD5STEP(F1, a, b, c, d, in[0] + 0xd76aa478, 7); -+ MD5STEP(F1, d, a, b, c, in[1] + 0xe8c7b756, 12); -+ MD5STEP(F1, c, d, a, b, in[2] + 0x242070db, 17); -+ MD5STEP(F1, b, c, d, a, in[3] + 0xc1bdceee, 22); -+ MD5STEP(F1, a, b, c, d, in[4] + 0xf57c0faf, 7); -+ MD5STEP(F1, d, a, b, c, in[5] + 0x4787c62a, 12); -+ MD5STEP(F1, c, d, a, b, in[6] + 0xa8304613, 17); -+ MD5STEP(F1, b, c, d, a, in[7] + 0xfd469501, 22); -+ MD5STEP(F1, a, b, c, d, in[8] + 0x698098d8, 7); -+ MD5STEP(F1, d, a, b, c, in[9] + 0x8b44f7af, 12); -+ MD5STEP(F1, c, d, a, b, in[10] + 0xffff5bb1, 17); -+ MD5STEP(F1, b, c, d, a, in[11] + 0x895cd7be, 22); -+ MD5STEP(F1, a, b, c, d, in[12] + 0x6b901122, 7); -+ MD5STEP(F1, d, a, b, c, in[13] + 0xfd987193, 12); -+ MD5STEP(F1, c, d, a, b, in[14] + 0xa679438e, 17); -+ MD5STEP(F1, b, c, d, a, in[15] + 0x49b40821, 22); -+ -+ MD5STEP(F2, a, b, c, d, in[1] + 0xf61e2562, 5); -+ MD5STEP(F2, d, a, b, c, in[6] + 0xc040b340, 9); -+ MD5STEP(F2, c, d, a, b, in[11] + 0x265e5a51, 14); -+ MD5STEP(F2, b, c, d, a, in[0] + 0xe9b6c7aa, 20); -+ MD5STEP(F2, a, b, c, d, in[5] + 0xd62f105d, 5); -+ MD5STEP(F2, d, a, b, c, in[10] + 0x02441453, 9); -+ MD5STEP(F2, c, d, a, b, in[15] + 0xd8a1e681, 14); -+ MD5STEP(F2, b, c, d, a, in[4] + 0xe7d3fbc8, 20); -+ MD5STEP(F2, a, b, c, d, in[9] + 0x21e1cde6, 5); -+ MD5STEP(F2, d, a, b, c, in[14] + 0xc33707d6, 9); -+ MD5STEP(F2, c, d, a, b, in[3] + 0xf4d50d87, 14); -+ MD5STEP(F2, b, c, d, a, in[8] + 0x455a14ed, 20); -+ MD5STEP(F2, a, b, c, d, in[13] + 0xa9e3e905, 5); -+ MD5STEP(F2, d, a, b, c, in[2] + 0xfcefa3f8, 9); -+ MD5STEP(F2, c, d, a, b, in[7] + 0x676f02d9, 14); -+ MD5STEP(F2, b, c, d, a, in[12] + 0x8d2a4c8a, 20); -+ -+ MD5STEP(F3, a, b, c, d, in[5] + 0xfffa3942, 4); -+ MD5STEP(F3, d, a, b, c, in[8] + 0x8771f681, 11); -+ MD5STEP(F3, c, d, a, b, in[11] + 0x6d9d6122, 16); -+ MD5STEP(F3, b, c, d, a, in[14] + 0xfde5380c, 23); -+ MD5STEP(F3, a, b, c, d, in[1] + 0xa4beea44, 4); -+ MD5STEP(F3, d, a, b, c, in[4] + 0x4bdecfa9, 11); -+ MD5STEP(F3, c, d, a, b, in[7] + 0xf6bb4b60, 16); -+ MD5STEP(F3, b, c, d, a, in[10] + 0xbebfbc70, 23); -+ MD5STEP(F3, a, b, c, d, in[13] + 0x289b7ec6, 4); -+ MD5STEP(F3, d, a, b, c, in[0] + 0xeaa127fa, 11); -+ MD5STEP(F3, c, d, a, b, in[3] + 0xd4ef3085, 16); -+ MD5STEP(F3, b, c, d, a, in[6] + 0x04881d05, 23); -+ MD5STEP(F3, a, b, c, d, in[9] + 0xd9d4d039, 4); -+ MD5STEP(F3, d, a, b, c, in[12] + 0xe6db99e5, 11); -+ MD5STEP(F3, c, d, a, b, in[15] + 0x1fa27cf8, 16); -+ MD5STEP(F3, b, c, d, a, in[2] + 0xc4ac5665, 23); -+ -+ MD5STEP(F4, a, b, c, d, in[0] + 0xf4292244, 6); -+ MD5STEP(F4, d, a, b, c, in[7] + 0x432aff97, 10); -+ MD5STEP(F4, c, d, a, b, in[14] + 0xab9423a7, 15); -+ MD5STEP(F4, b, c, d, a, in[5] + 0xfc93a039, 21); -+ MD5STEP(F4, a, b, c, d, in[12] + 0x655b59c3, 6); -+ MD5STEP(F4, d, a, b, c, in[3] + 0x8f0ccc92, 10); -+ MD5STEP(F4, c, d, a, b, in[10] + 0xffeff47d, 15); -+ MD5STEP(F4, b, c, d, a, in[1] + 0x85845dd1, 21); -+ MD5STEP(F4, a, b, c, d, in[8] + 0x6fa87e4f, 6); -+ MD5STEP(F4, d, a, b, c, in[15] + 0xfe2ce6e0, 10); -+ MD5STEP(F4, c, d, a, b, in[6] + 0xa3014314, 15); -+ MD5STEP(F4, b, c, d, a, in[13] + 0x4e0811a1, 21); -+ MD5STEP(F4, a, b, c, d, in[4] + 0xf7537e82, 6); -+ MD5STEP(F4, d, a, b, c, in[11] + 0xbd3af235, 10); -+ MD5STEP(F4, c, d, a, b, in[2] + 0x2ad7d2bb, 15); -+ MD5STEP(F4, b, c, d, a, in[9] + 0xeb86d391, 21); -+ -+ buf[0] += a; -+ buf[1] += b; -+ buf[2] += c; -+ buf[3] += d; -+} -+ -+void mvMD5(unsigned char const *buf, unsigned len, unsigned char* digest) -+{ -+ MV_MD5_CONTEXT ctx; -+ -+ mvMD5Init(&ctx); -+ mvMD5Update(&ctx, buf, len); -+ mvMD5Final(digest, &ctx); -+} -+ -+ -+void mvHmacMd5(unsigned char const* text, int text_len, -+ unsigned char const* key, int key_len, -+ unsigned char* digest) -+{ -+ int i; -+ MV_MD5_CONTEXT ctx; -+ unsigned char k_ipad[64+1]; /* inner padding - key XORd with ipad */ -+ unsigned char k_opad[64+1]; /* outer padding - key XORd with opad */ -+ -+ /* start out by storing key in pads */ -+ memset(k_ipad, 0, 64); -+ memcpy(k_ipad, key, key_len); -+ memset(k_opad, 0, 64); -+ memcpy(k_opad, key, key_len); -+ -+ /* XOR key with ipad and opad values */ -+ for (i=0; i<64; i++) -+ { -+ k_ipad[i] ^= 0x36; -+ k_opad[i] ^= 0x5c; -+ } -+ -+ /* perform inner MD5 */ -+ mvMD5Init(&ctx); /* init ctx for 1st pass */ -+ mvMD5Update(&ctx, k_ipad, 64); /* start with inner pad */ -+ mvMD5Update(&ctx, text, text_len); /* then text of datagram */ -+ mvMD5Final(digest, &ctx); /* finish up 1st pass */ -+ -+ /* perform outer MD5 */ -+ mvMD5Init(&ctx); /* init ctx for 2nd pass */ -+ mvMD5Update(&ctx, k_opad, 64); /* start with outer pad */ -+ mvMD5Update(&ctx, digest, 16); /* then results of 1st hash */ -+ mvMD5Final(digest, &ctx); /* finish up 2nd pass */ -+} -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvMD5.h linux-3.0.4/crypto/ocf/kirkwood/cesa/mvMD5.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvMD5.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/cesa/mvMD5.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,93 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __mvMD5_h__ -+#define __mvMD5_h__ -+ -+#include "mvMD5.h" -+ -+#define MV_MD5_MAC_LEN 16 -+ -+ -+typedef struct -+{ -+ MV_U32 buf[4]; -+ MV_U32 bits[2]; -+ MV_U8 in[64]; -+ -+} MV_MD5_CONTEXT; -+ -+void mvMD5Init(MV_MD5_CONTEXT *context); -+void mvMD5Update(MV_MD5_CONTEXT *context, unsigned char const *buf, -+ unsigned len); -+void mvMD5Final(unsigned char digest[16], MV_MD5_CONTEXT *context); -+ -+void mvMD5(unsigned char const *buf, unsigned len, unsigned char* digest); -+ -+void mvHmacMd5(unsigned char const* text, int text_len, -+ unsigned char const* key, int key_len, -+ unsigned char* digest); -+ -+ -+#endif /* __mvMD5_h__ */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvSHA1.c linux-3.0.4/crypto/ocf/kirkwood/cesa/mvSHA1.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvSHA1.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/cesa/mvSHA1.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,239 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "mvOs.h" -+#include "mvSHA1.h" -+ -+#define SHA1HANDSOFF -+ -+typedef union -+{ -+ MV_U8 c[64]; -+ MV_U32 l[16]; -+ -+} CHAR64LONG16; -+ -+static void mvSHA1Transform(MV_U32 state[5], const MV_U8 *buffer); -+ -+#define rol(value, bits) (((value) << (bits)) | ((value) >> (32 - (bits)))) -+ -+ -+#ifdef MV_CPU_LE -+#define blk0(i) (block->l[i] = (rol(block->l[i], 24) & 0xFF00FF00) | \ -+ (rol(block->l[i], 8) & 0x00FF00FF)) -+#else -+#define blk0(i) block->l[i] -+#endif -+#define blk(i) (block->l[i & 15] = rol(block->l[(i + 13) & 15] ^ \ -+ block->l[(i + 8) & 15] ^ block->l[(i + 2) & 15] ^ block->l[i & 15], 1)) -+ -+/* (R0+R1), R2, R3, R4 are the different operations used in SHA1 */ -+#define R0(v,w,x,y,z,i) \ -+ z += ((w & (x ^ y)) ^ y) + blk0(i) + 0x5A827999 + rol(v, 5); \ -+ w = rol(w, 30); -+#define R1(v,w,x,y,z,i) \ -+ z += ((w & (x ^ y)) ^ y) + blk(i) + 0x5A827999 + rol(v, 5); \ -+ w = rol(w, 30); -+#define R2(v,w,x,y,z,i) \ -+ z += (w ^ x ^ y) + blk(i) + 0x6ED9EBA1 + rol(v, 5); w = rol(w, 30); -+#define R3(v,w,x,y,z,i) \ -+ z += (((w | x) & y) | (w & x)) + blk(i) + 0x8F1BBCDC + rol(v, 5); \ -+ w = rol(w, 30); -+#define R4(v,w,x,y,z,i) \ -+ z += (w ^ x ^ y) + blk(i) + 0xCA62C1D6 + rol(v, 5); \ -+ w=rol(w, 30); -+ -+/* Hash a single 512-bit block. This is the core of the algorithm. */ -+static void mvSHA1Transform(MV_U32 state[5], const MV_U8 *buffer) -+{ -+ MV_U32 a, b, c, d, e; -+ CHAR64LONG16* block; -+ -+#ifdef SHA1HANDSOFF -+ static MV_U32 workspace[16]; -+ -+ block = (CHAR64LONG16 *) workspace; -+ memcpy(block, buffer, 64); -+#else -+ block = (CHAR64LONG16 *) buffer; -+#endif -+ /* Copy context->state[] to working vars */ -+ a = state[0]; -+ b = state[1]; -+ c = state[2]; -+ d = state[3]; -+ e = state[4]; -+ /* 4 rounds of 20 operations each. Loop unrolled. */ -+ R0(a,b,c,d,e, 0); R0(e,a,b,c,d, 1); R0(d,e,a,b,c, 2); R0(c,d,e,a,b, 3); -+ R0(b,c,d,e,a, 4); R0(a,b,c,d,e, 5); R0(e,a,b,c,d, 6); R0(d,e,a,b,c, 7); -+ R0(c,d,e,a,b, 8); R0(b,c,d,e,a, 9); R0(a,b,c,d,e,10); R0(e,a,b,c,d,11); -+ R0(d,e,a,b,c,12); R0(c,d,e,a,b,13); R0(b,c,d,e,a,14); R0(a,b,c,d,e,15); -+ R1(e,a,b,c,d,16); R1(d,e,a,b,c,17); R1(c,d,e,a,b,18); R1(b,c,d,e,a,19); -+ R2(a,b,c,d,e,20); R2(e,a,b,c,d,21); R2(d,e,a,b,c,22); R2(c,d,e,a,b,23); -+ R2(b,c,d,e,a,24); R2(a,b,c,d,e,25); R2(e,a,b,c,d,26); R2(d,e,a,b,c,27); -+ R2(c,d,e,a,b,28); R2(b,c,d,e,a,29); R2(a,b,c,d,e,30); R2(e,a,b,c,d,31); -+ R2(d,e,a,b,c,32); R2(c,d,e,a,b,33); R2(b,c,d,e,a,34); R2(a,b,c,d,e,35); -+ R2(e,a,b,c,d,36); R2(d,e,a,b,c,37); R2(c,d,e,a,b,38); R2(b,c,d,e,a,39); -+ R3(a,b,c,d,e,40); R3(e,a,b,c,d,41); R3(d,e,a,b,c,42); R3(c,d,e,a,b,43); -+ R3(b,c,d,e,a,44); R3(a,b,c,d,e,45); R3(e,a,b,c,d,46); R3(d,e,a,b,c,47); -+ R3(c,d,e,a,b,48); R3(b,c,d,e,a,49); R3(a,b,c,d,e,50); R3(e,a,b,c,d,51); -+ R3(d,e,a,b,c,52); R3(c,d,e,a,b,53); R3(b,c,d,e,a,54); R3(a,b,c,d,e,55); -+ R3(e,a,b,c,d,56); R3(d,e,a,b,c,57); R3(c,d,e,a,b,58); R3(b,c,d,e,a,59); -+ R4(a,b,c,d,e,60); R4(e,a,b,c,d,61); R4(d,e,a,b,c,62); R4(c,d,e,a,b,63); -+ R4(b,c,d,e,a,64); R4(a,b,c,d,e,65); R4(e,a,b,c,d,66); R4(d,e,a,b,c,67); -+ R4(c,d,e,a,b,68); R4(b,c,d,e,a,69); R4(a,b,c,d,e,70); R4(e,a,b,c,d,71); -+ R4(d,e,a,b,c,72); R4(c,d,e,a,b,73); R4(b,c,d,e,a,74); R4(a,b,c,d,e,75); -+ R4(e,a,b,c,d,76); R4(d,e,a,b,c,77); R4(c,d,e,a,b,78); R4(b,c,d,e,a,79); -+ /* Add the working vars back into context.state[] */ -+ state[0] += a; -+ state[1] += b; -+ state[2] += c; -+ state[3] += d; -+ state[4] += e; -+ /* Wipe variables */ -+ a = b = c = d = e = 0; -+} -+ -+void mvSHA1Init(MV_SHA1_CTX* context) -+{ -+ /* SHA1 initialization constants */ -+ context->state[0] = 0x67452301; -+ context->state[1] = 0xEFCDAB89; -+ context->state[2] = 0x98BADCFE; -+ context->state[3] = 0x10325476; -+ context->state[4] = 0xC3D2E1F0; -+ context->count[0] = context->count[1] = 0; -+} -+ -+ -+/* Run your data through this. */ -+void mvSHA1Update(MV_SHA1_CTX *context, MV_U8 const *data, -+ unsigned int len) -+{ -+ MV_U32 i, j; -+ -+ j = (context->count[0] >> 3) & 63; -+ if ((context->count[0] += len << 3) < (len << 3)) -+ context->count[1]++; -+ context->count[1] += (len >> 29); -+ if ((j + len) > 63) -+ { -+ memcpy(&context->buffer[j], data, (i = 64-j)); -+ mvSHA1Transform(context->state, context->buffer); -+ for ( ; i + 63 < len; i += 64) -+ { -+ mvSHA1Transform(context->state, &data[i]); -+ } -+ j = 0; -+ } -+ else -+ { -+ i = 0; -+ } -+ memcpy(&context->buffer[j], &data[i], len - i); -+} -+ -+void mvSHA1Final(MV_U8* digest, MV_SHA1_CTX* context) -+{ -+ MV_U32 i; -+ MV_U8 finalcount[8]; -+ -+ for (i = 0; i < 8; i++) -+ { -+ finalcount[i] = (unsigned char)((context->count[(i >= 4 ? 0 : 1)] >> -+ ((3-(i & 3)) * 8) ) & 255); /* Endian independent */ -+ } -+ mvSHA1Update(context, (const unsigned char *) "\200", 1); -+ while ((context->count[0] & 504) != 448) -+ { -+ mvSHA1Update(context, (const unsigned char *) "\0", 1); -+ } -+ mvSHA1Update(context, finalcount, 8); /* Should cause a mvSHA1Transform() -+ */ -+ for (i = 0; i < 20; i++) -+ { -+ digest[i] = (unsigned char) -+ ((context->state[i >> 2] >> ((3 - (i & 3)) * 8)) & 255); -+ } -+ /* Wipe variables */ -+ i = 0; -+ memset(context->buffer, 0, 64); -+ memset(context->state, 0, 20); -+ memset(context->count, 0, 8); -+ memset(finalcount, 0, 8); -+ -+#ifdef SHA1HANDSOFF /* make SHA1Transform overwrite it's own static vars */ -+ mvSHA1Transform(context->state, context->buffer); -+#endif -+} -+ -+ -+void mvSHA1(MV_U8 const *buf, unsigned int len, MV_U8* digest) -+{ -+ MV_SHA1_CTX ctx; -+ -+ mvSHA1Init(&ctx); -+ mvSHA1Update(&ctx, buf, len); -+ mvSHA1Final(digest, &ctx); -+} -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvSHA1.h linux-3.0.4/crypto/ocf/kirkwood/cesa/mvSHA1.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvSHA1.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/cesa/mvSHA1.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,88 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __mvSHA1_h__ -+#define __mvSHA1_h__ -+ -+#include "mvSHA1.h" -+ -+#define MV_SHA1_MAC_LEN 20 -+ -+ -+typedef struct -+{ -+ MV_U32 state[5]; -+ MV_U32 count[2]; -+ MV_U8 buffer[64]; -+ -+} MV_SHA1_CTX; -+ -+void mvSHA1Init(MV_SHA1_CTX *context); -+void mvSHA1Update(MV_SHA1_CTX *context, MV_U8 const *buf, unsigned int len); -+void mvSHA1Final(MV_U8* digest, MV_SHA1_CTX *context); -+ -+void mvSHA1(MV_U8 const *buf, unsigned int len, MV_U8* digest); -+ -+ -+#endif /* __mvSHA1_h__ */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa_ocf_drv.c linux-3.0.4/crypto/ocf/kirkwood/cesa_ocf_drv.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa_ocf_drv.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/cesa_ocf_drv.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,1297 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+*******************************************************************************/ -+ -+#include -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "ctrlEnv/sys/mvSysCesa.h" -+#include "cesa/mvCesa.h" /* moved here before cryptodev.h due to include dependencies */ -+#include -+#include -+#include -+#include -+#include "mvDebug.h" -+ -+#include "cesa/mvMD5.h" -+#include "cesa/mvSHA1.h" -+ -+#include "cesa/mvCesaRegs.h" -+#include "cesa/AES/mvAes.h" -+#include "cesa/mvLru.h" -+ -+#undef RT_DEBUG -+#ifdef RT_DEBUG -+static int debug = 1; -+module_param(debug, int, 1); -+MODULE_PARM_DESC(debug, "Enable debug"); -+#undef dprintk -+#define dprintk(a...) if (debug) { printk(a); } else -+#else -+static int debug = 0; -+#undef dprintk -+#define dprintk(a...) -+#endif -+ -+ -+/* TDMA Regs */ -+#define WINDOW_BASE(i) 0xA00 + (i << 3) -+#define WINDOW_CTRL(i) 0xA04 + (i << 3) -+ -+/* interrupt handling */ -+#undef CESA_OCF_POLLING -+#undef CESA_OCF_TASKLET -+ -+#if defined(CESA_OCF_POLLING) && defined(CESA_OCF_TASKLET) -+#error "don't use both tasklet and polling mode" -+#endif -+ -+extern int cesaReqResources; -+/* support for spliting action into 2 actions */ -+#define CESA_OCF_SPLIT -+ -+/* general defines */ -+#define CESA_OCF_MAX_SES 128 -+#define CESA_Q_SIZE 64 -+ -+ -+/* data structures */ -+struct cesa_ocf_data { -+ int cipher_alg; -+ int auth_alg; -+ int encrypt_tn_auth; -+#define auth_tn_decrypt encrypt_tn_auth -+ int ivlen; -+ int digestlen; -+ short sid_encrypt; -+ short sid_decrypt; -+ /* fragment workaround sessions */ -+ short frag_wa_encrypt; -+ short frag_wa_decrypt; -+ short frag_wa_auth; -+}; -+ -+/* CESA device data */ -+struct cesa_dev { -+ void __iomem *sram; -+ void __iomem *reg; -+ struct mv_cesa_platform_data *plat_data; -+ int irq; -+}; -+ -+#define DIGEST_BUF_SIZE 32 -+struct cesa_ocf_process { -+ MV_CESA_COMMAND cesa_cmd; -+ MV_CESA_MBUF cesa_mbuf; -+ MV_BUF_INFO cesa_bufs[MV_CESA_MAX_MBUF_FRAGS]; -+ char digest[DIGEST_BUF_SIZE]; -+ int digest_len; -+ struct cryptop *crp; -+ int need_cb; -+}; -+ -+/* global variables */ -+static int32_t cesa_ocf_id = -1; -+static struct cesa_ocf_data *cesa_ocf_sessions[CESA_OCF_MAX_SES]; -+static spinlock_t cesa_lock; -+static struct cesa_dev cesa_device; -+ -+/* static APIs */ -+static int cesa_ocf_process (device_t, struct cryptop *, int); -+static int cesa_ocf_newsession (device_t, u_int32_t *, struct cryptoini *); -+static int cesa_ocf_freesession (device_t, u_int64_t); -+static void cesa_callback (unsigned long); -+static irqreturn_t cesa_interrupt_handler (int, void *); -+#ifdef CESA_OCF_POLLING -+static void cesa_interrupt_polling(void); -+#endif -+#ifdef CESA_OCF_TASKLET -+static struct tasklet_struct cesa_ocf_tasklet; -+#endif -+ -+static struct timeval tt_start; -+static struct timeval tt_end; -+ -+/* -+ * dummy device structure -+ */ -+ -+static struct { -+ softc_device_decl sc_dev; -+} mv_cesa_dev; -+ -+static device_method_t mv_cesa_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, cesa_ocf_newsession), -+ DEVMETHOD(cryptodev_freesession,cesa_ocf_freesession), -+ DEVMETHOD(cryptodev_process, cesa_ocf_process), -+ DEVMETHOD(cryptodev_kprocess, NULL), -+}; -+ -+ -+ -+/* Add debug Trace */ -+#undef CESA_OCF_TRACE_DEBUG -+#ifdef CESA_OCF_TRACE_DEBUG -+ -+#define MV_CESA_USE_TIMER_ID 0 -+ -+typedef struct -+{ -+ int type; /* 0 - isrEmpty, 1 - cesaReadyGet, 2 - cesaAction */ -+ MV_U32 timeStamp; -+ MV_U32 cause; -+ MV_U32 realCause; -+ MV_U32 dmaCause; -+ int resources; -+ MV_CESA_REQ* pReqReady; -+ MV_CESA_REQ* pReqEmpty; -+ MV_CESA_REQ* pReqProcess; -+} MV_CESA_TEST_TRACE; -+ -+#define MV_CESA_TEST_TRACE_SIZE 50 -+ -+static int cesaTestTraceIdx = 0; -+static MV_CESA_TEST_TRACE cesaTestTrace[MV_CESA_TEST_TRACE_SIZE]; -+ -+static void cesaTestTraceAdd(int type) -+{ -+ cesaTestTrace[cesaTestTraceIdx].type = type; -+ cesaTestTrace[cesaTestTraceIdx].realCause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); -+ //cesaTestTrace[cesaTestTraceIdx].idmaCause = MV_REG_READ(IDMA_CAUSE_REG); -+ cesaTestTrace[cesaTestTraceIdx].resources = cesaReqResources; -+ cesaTestTrace[cesaTestTraceIdx].pReqReady = pCesaReqReady; -+ cesaTestTrace[cesaTestTraceIdx].pReqEmpty = pCesaReqEmpty; -+ cesaTestTrace[cesaTestTraceIdx].pReqProcess = pCesaReqProcess; -+ cesaTestTrace[cesaTestTraceIdx].timeStamp = mvCntmrRead(MV_CESA_USE_TIMER_ID); -+ cesaTestTraceIdx++; -+ if(cesaTestTraceIdx == MV_CESA_TEST_TRACE_SIZE) -+ cesaTestTraceIdx = 0; -+} -+ -+#else /* CESA_OCF_TRACE_DEBUG */ -+ -+#define cesaTestTraceAdd(x) -+ -+#endif /* CESA_OCF_TRACE_DEBUG */ -+ -+unsigned int -+get_usec(unsigned int start) -+{ -+ if(start) { -+ do_gettimeofday (&tt_start); -+ return 0; -+ } -+ else { -+ do_gettimeofday (&tt_end); -+ tt_end.tv_sec -= tt_start.tv_sec; -+ tt_end.tv_usec -= tt_start.tv_usec; -+ if (tt_end.tv_usec < 0) { -+ tt_end.tv_usec += 1000 * 1000; -+ tt_end.tv_sec -= 1; -+ } -+ } -+ printk("time taken is %d\n", (unsigned int)(tt_end.tv_usec + tt_end.tv_sec * 1000000)); -+ return (tt_end.tv_usec + tt_end.tv_sec * 1000000); -+} -+ -+#ifdef RT_DEBUG -+/* -+ * check that the crp action match the current session -+ */ -+static int -+ocf_check_action(struct cryptop *crp, struct cesa_ocf_data *cesa_ocf_cur_ses) { -+ int count = 0; -+ int encrypt = 0, decrypt = 0, auth = 0; -+ struct cryptodesc *crd; -+ -+ /* Go through crypto descriptors, processing as we go */ -+ for (crd = crp->crp_desc; crd; crd = crd->crd_next, count++) { -+ if(count > 2) { -+ printk("%s,%d: session mode is not supported.\n", __FILE__, __LINE__); -+ return 1; -+ } -+ -+ /* Encryption /Decryption */ -+ if(crd->crd_alg == cesa_ocf_cur_ses->cipher_alg) { -+ /* check that the action is compatible with session */ -+ if(encrypt || decrypt) { -+ printk("%s,%d: session mode is not supported.\n", __FILE__, __LINE__); -+ return 1; -+ } -+ -+ if(crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ -+ if( (count == 2) && (cesa_ocf_cur_ses->encrypt_tn_auth) ) { -+ printk("%s,%d: sequence isn't supported by this session.\n", __FILE__, __LINE__); -+ return 1; -+ } -+ encrypt++; -+ } -+ else { /* decrypt */ -+ if( (count == 2) && !(cesa_ocf_cur_ses->auth_tn_decrypt) ) { -+ printk("%s,%d: sequence isn't supported by this session.\n", __FILE__, __LINE__); -+ return 1; -+ } -+ decrypt++; -+ } -+ -+ } -+ /* Authentication */ -+ else if(crd->crd_alg == cesa_ocf_cur_ses->auth_alg) { -+ /* check that the action is compatible with session */ -+ if(auth) { -+ printk("%s,%d: session mode is not supported.\n", __FILE__, __LINE__); -+ return 1; -+ } -+ if( (count == 2) && (decrypt) && (cesa_ocf_cur_ses->auth_tn_decrypt)) { -+ printk("%s,%d: sequence isn't supported by this session.\n", __FILE__, __LINE__); -+ return 1; -+ } -+ if( (count == 2) && (encrypt) && !(cesa_ocf_cur_ses->encrypt_tn_auth)) { -+ printk("%s,%d: sequence isn't supported by this session.\n", __FILE__, __LINE__); -+ return 1; -+ } -+ auth++; -+ } -+ else { -+ printk("%s,%d: Alg isn't supported by this session.\n", __FILE__, __LINE__); -+ return 1; -+ } -+ } -+ return 0; -+ -+} -+#endif -+ -+/* -+ * Process a request. -+ */ -+static int -+cesa_ocf_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ struct cesa_ocf_process *cesa_ocf_cmd = NULL; -+ struct cesa_ocf_process *cesa_ocf_cmd_wa = NULL; -+ MV_CESA_COMMAND *cesa_cmd; -+ struct cryptodesc *crd; -+ struct cesa_ocf_data *cesa_ocf_cur_ses; -+ int sid = 0, temp_len = 0, i; -+ int encrypt = 0, decrypt = 0, auth = 0; -+ int status; -+ struct sk_buff *skb = NULL; -+ struct uio *uiop = NULL; -+ unsigned char *ivp; -+ MV_BUF_INFO *p_buf_info; -+ MV_CESA_MBUF *p_mbuf_info; -+ unsigned long flags; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ if( cesaReqResources <= 1 ) { -+ dprintk("%s,%d: ERESTART\n", __FILE__, __LINE__); -+ return ERESTART; -+ } -+ -+#ifdef RT_DEBUG -+ /* Sanity check */ -+ if (crp == NULL) { -+ printk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ if (crp->crp_desc == NULL || crp->crp_buf == NULL ) { -+ printk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ return EINVAL; -+ } -+ -+ sid = crp->crp_sid & 0xffffffff; -+ if ((sid >= CESA_OCF_MAX_SES) || (cesa_ocf_sessions[sid] == NULL)) { -+ crp->crp_etype = ENOENT; -+ printk("%s,%d: ENOENT session %d \n", __FILE__, __LINE__, sid); -+ return EINVAL; -+ } -+#endif -+ -+ sid = crp->crp_sid & 0xffffffff; -+ crp->crp_etype = 0; -+ cesa_ocf_cur_ses = cesa_ocf_sessions[sid]; -+ -+#ifdef RT_DEBUG -+ if(ocf_check_action(crp, cesa_ocf_cur_ses)){ -+ goto p_error; -+ } -+#endif -+ -+ /* malloc a new cesa process */ -+ cesa_ocf_cmd = kmalloc(sizeof(struct cesa_ocf_process), GFP_ATOMIC); -+ -+ if (cesa_ocf_cmd == NULL) { -+ printk("%s,%d: ENOBUFS \n", __FILE__, __LINE__); -+ goto p_error; -+ } -+ memset(cesa_ocf_cmd, 0, sizeof(struct cesa_ocf_process)); -+ -+ /* init cesa_process */ -+ cesa_ocf_cmd->crp = crp; -+ /* always call callback */ -+ cesa_ocf_cmd->need_cb = 1; -+ -+ /* init cesa_cmd for usage of the HALs */ -+ cesa_cmd = &cesa_ocf_cmd->cesa_cmd; -+ cesa_cmd->pReqPrv = (void *)cesa_ocf_cmd; -+ cesa_cmd->sessionId = cesa_ocf_cur_ses->sid_encrypt; /* defualt use encrypt */ -+ -+ /* prepare src buffer */ -+ /* we send the entire buffer to the HAL, even if only part of it should be encrypt/auth. */ -+ /* if not using seesions for both encrypt and auth, then it will be wiser to to copy only */ -+ /* from skip to crd_len. */ -+ p_buf_info = cesa_ocf_cmd->cesa_bufs; -+ p_mbuf_info = &cesa_ocf_cmd->cesa_mbuf; -+ -+ p_buf_info += 2; /* save 2 first buffers for IV and digest - -+ we won't append them to the end since, they -+ might be places in an unaligned addresses. */ -+ -+ p_mbuf_info->pFrags = p_buf_info; -+ temp_len = 0; -+ -+ /* handle SKB */ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ -+ dprintk("%s,%d: handle SKB.\n", __FILE__, __LINE__); -+ skb = (struct sk_buff *) crp->crp_buf; -+ -+ if (skb_shinfo(skb)->nr_frags >= (MV_CESA_MAX_MBUF_FRAGS - 1)) { -+ printk("%s,%d: %d nr_frags > MV_CESA_MAX_MBUF_FRAGS", __FILE__, __LINE__, skb_shinfo(skb)->nr_frags); -+ goto p_error; -+ } -+ -+ p_mbuf_info->mbufSize = skb->len; -+ temp_len = skb->len; -+ /* first skb fragment */ -+ p_buf_info->bufSize = skb_headlen(skb); -+ p_buf_info->bufVirtPtr = skb->data; -+ p_buf_info++; -+ -+ /* now handle all other skb fragments */ -+ for ( i = 0; i < skb_shinfo(skb)->nr_frags; i++ ) { -+ skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; -+ p_buf_info->bufSize = frag->size; -+ p_buf_info->bufVirtPtr = page_address(frag->page) + frag->page_offset; -+ p_buf_info++; -+ } -+ p_mbuf_info->numFrags = skb_shinfo(skb)->nr_frags + 1; -+ } -+ /* handle UIO */ -+ else if(crp->crp_flags & CRYPTO_F_IOV) { -+ -+ dprintk("%s,%d: handle UIO.\n", __FILE__, __LINE__); -+ uiop = (struct uio *) crp->crp_buf; -+ -+ if (uiop->uio_iovcnt > (MV_CESA_MAX_MBUF_FRAGS - 1)) { -+ printk("%s,%d: %d uio_iovcnt > MV_CESA_MAX_MBUF_FRAGS \n", __FILE__, __LINE__, uiop->uio_iovcnt); -+ goto p_error; -+ } -+ -+ p_mbuf_info->mbufSize = crp->crp_ilen; -+ p_mbuf_info->numFrags = uiop->uio_iovcnt; -+ for(i = 0; i < uiop->uio_iovcnt; i++) { -+ p_buf_info->bufVirtPtr = uiop->uio_iov[i].iov_base; -+ p_buf_info->bufSize = uiop->uio_iov[i].iov_len; -+ temp_len += p_buf_info->bufSize; -+ dprintk("%s,%d: buf %x-> addr %x, size %x \n" -+ , __FILE__, __LINE__, i, (unsigned int)p_buf_info->bufVirtPtr, p_buf_info->bufSize); -+ p_buf_info++; -+ } -+ -+ } -+ /* handle CONTIG */ -+ else { -+ dprintk("%s,%d: handle CONTIG.\n", __FILE__, __LINE__); -+ p_mbuf_info->numFrags = 1; -+ p_mbuf_info->mbufSize = crp->crp_ilen; -+ p_buf_info->bufVirtPtr = crp->crp_buf; -+ p_buf_info->bufSize = crp->crp_ilen; -+ temp_len = crp->crp_ilen; -+ p_buf_info++; -+ } -+ -+ /* Support up to 64K why? cause! */ -+ if(crp->crp_ilen > 64*1024) { -+ printk("%s,%d: buf too big %x \n", __FILE__, __LINE__, crp->crp_ilen); -+ goto p_error; -+ } -+ -+ if( temp_len != crp->crp_ilen ) { -+ printk("%s,%d: warning size don't match.(%x %x) \n", __FILE__, __LINE__, temp_len, crp->crp_ilen); -+ } -+ -+ cesa_cmd->pSrc = p_mbuf_info; -+ cesa_cmd->pDst = p_mbuf_info; -+ -+ /* restore p_buf_info to point to first available buf */ -+ p_buf_info = cesa_ocf_cmd->cesa_bufs; -+ p_buf_info += 1; -+ -+ -+ /* Go through crypto descriptors, processing as we go */ -+ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { -+ -+ /* Encryption /Decryption */ -+ if(crd->crd_alg == cesa_ocf_cur_ses->cipher_alg) { -+ -+ dprintk("%s,%d: cipher", __FILE__, __LINE__); -+ -+ cesa_cmd->cryptoOffset = crd->crd_skip; -+ cesa_cmd->cryptoLength = crd->crd_len; -+ -+ if(crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ -+ dprintk(" encrypt \n"); -+ encrypt++; -+ -+ /* handle IV */ -+ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { /* IV from USER */ -+ dprintk("%s,%d: IV from USER (offset %x) \n", __FILE__, __LINE__, crd->crd_inject); -+ cesa_cmd->ivFromUser = 1; -+ ivp = crd->crd_iv; -+ -+ /* -+ * do we have to copy the IV back to the buffer ? -+ */ -+ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { -+ dprintk("%s,%d: copy the IV back to the buffer\n", __FILE__, __LINE__); -+ cesa_cmd->ivOffset = crd->crd_inject; -+ crypto_copyback(crp->crp_flags, crp->crp_buf, crd->crd_inject, cesa_ocf_cur_ses->ivlen, ivp); -+ } -+ else { -+ dprintk("%s,%d: don't copy the IV back to the buffer \n", __FILE__, __LINE__); -+ p_mbuf_info->numFrags++; -+ p_mbuf_info->mbufSize += cesa_ocf_cur_ses->ivlen; -+ p_mbuf_info->pFrags = p_buf_info; -+ -+ p_buf_info->bufVirtPtr = ivp; -+ p_buf_info->bufSize = cesa_ocf_cur_ses->ivlen; -+ p_buf_info--; -+ -+ /* offsets */ -+ cesa_cmd->ivOffset = 0; -+ cesa_cmd->cryptoOffset += cesa_ocf_cur_ses->ivlen; -+ if(auth) { -+ cesa_cmd->macOffset += cesa_ocf_cur_ses->ivlen; -+ cesa_cmd->digestOffset += cesa_ocf_cur_ses->ivlen; -+ } -+ } -+ } -+ else { /* random IV */ -+ dprintk("%s,%d: random IV \n", __FILE__, __LINE__); -+ cesa_cmd->ivFromUser = 0; -+ -+ /* -+ * do we have to copy the IV back to the buffer ? -+ */ -+ /* in this mode the HAL will always copy the IV */ -+ /* given by the session to the ivOffset */ -+ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { -+ cesa_cmd->ivOffset = crd->crd_inject; -+ } -+ else { -+ /* if IV isn't copy, then how will the user know which IV did we use??? */ -+ printk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ goto p_error; -+ } -+ } -+ } -+ else { /* decrypt */ -+ dprintk(" decrypt \n"); -+ decrypt++; -+ cesa_cmd->sessionId = cesa_ocf_cur_ses->sid_decrypt; -+ -+ /* handle IV */ -+ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { -+ dprintk("%s,%d: IV from USER \n", __FILE__, __LINE__); -+ /* append the IV buf to the mbuf */ -+ cesa_cmd->ivFromUser = 1; -+ p_mbuf_info->numFrags++; -+ p_mbuf_info->mbufSize += cesa_ocf_cur_ses->ivlen; -+ p_mbuf_info->pFrags = p_buf_info; -+ -+ p_buf_info->bufVirtPtr = crd->crd_iv; -+ p_buf_info->bufSize = cesa_ocf_cur_ses->ivlen; -+ p_buf_info--; -+ -+ /* offsets */ -+ cesa_cmd->ivOffset = 0; -+ cesa_cmd->cryptoOffset += cesa_ocf_cur_ses->ivlen; -+ if(auth) { -+ cesa_cmd->macOffset += cesa_ocf_cur_ses->ivlen; -+ cesa_cmd->digestOffset += cesa_ocf_cur_ses->ivlen; -+ } -+ } -+ else { -+ dprintk("%s,%d: IV inside the buffer \n", __FILE__, __LINE__); -+ cesa_cmd->ivFromUser = 0; -+ cesa_cmd->ivOffset = crd->crd_inject; -+ } -+ } -+ -+ } -+ /* Authentication */ -+ else if(crd->crd_alg == cesa_ocf_cur_ses->auth_alg) { -+ dprintk("%s,%d: Authentication \n", __FILE__, __LINE__); -+ auth++; -+ cesa_cmd->macOffset = crd->crd_skip; -+ cesa_cmd->macLength = crd->crd_len; -+ -+ /* digest + mac */ -+ cesa_cmd->digestOffset = crd->crd_inject; -+ } -+ else { -+ printk("%s,%d: Alg isn't supported by this session.\n", __FILE__, __LINE__); -+ goto p_error; -+ } -+ } -+ -+ dprintk("\n"); -+ dprintk("%s,%d: Sending Action: \n", __FILE__, __LINE__); -+ dprintk("%s,%d: IV from user: %d. IV offset %x \n", __FILE__, __LINE__, cesa_cmd->ivFromUser, cesa_cmd->ivOffset); -+ dprintk("%s,%d: crypt offset %x len %x \n", __FILE__, __LINE__, cesa_cmd->cryptoOffset, cesa_cmd->cryptoLength); -+ dprintk("%s,%d: Auth offset %x len %x \n", __FILE__, __LINE__, cesa_cmd->macOffset, cesa_cmd->macLength); -+ dprintk("%s,%d: set digest in offset %x . \n", __FILE__, __LINE__, cesa_cmd->digestOffset); -+ if(debug) { -+ mvCesaDebugMbuf("SRC BUFFER", cesa_cmd->pSrc, 0, cesa_cmd->pSrc->mbufSize); -+ } -+ -+ -+ /* send action to HAL */ -+ spin_lock_irqsave(&cesa_lock, flags); -+ status = mvCesaAction(cesa_cmd); -+ spin_unlock_irqrestore(&cesa_lock, flags); -+ -+ /* action not allowed */ -+ if(status == MV_NOT_ALLOWED) { -+#ifdef CESA_OCF_SPLIT -+ /* if both encrypt and auth try to split */ -+ if(auth && (encrypt || decrypt)) { -+ MV_CESA_COMMAND *cesa_cmd_wa; -+ -+ /* malloc a new cesa process and init it */ -+ cesa_ocf_cmd_wa = kmalloc(sizeof(struct cesa_ocf_process), GFP_ATOMIC); -+ -+ if (cesa_ocf_cmd_wa == NULL) { -+ printk("%s,%d: ENOBUFS \n", __FILE__, __LINE__); -+ goto p_error; -+ } -+ memcpy(cesa_ocf_cmd_wa, cesa_ocf_cmd, sizeof(struct cesa_ocf_process)); -+ cesa_cmd_wa = &cesa_ocf_cmd_wa->cesa_cmd; -+ cesa_cmd_wa->pReqPrv = (void *)cesa_ocf_cmd_wa; -+ cesa_ocf_cmd_wa->need_cb = 0; -+ -+ /* break requests to two operation, first operation completion won't call callback */ -+ if((decrypt) && (cesa_ocf_cur_ses->auth_tn_decrypt)) { -+ cesa_cmd_wa->sessionId = cesa_ocf_cur_ses->frag_wa_auth; -+ cesa_cmd->sessionId = cesa_ocf_cur_ses->frag_wa_decrypt; -+ } -+ else if((decrypt) && !(cesa_ocf_cur_ses->auth_tn_decrypt)) { -+ cesa_cmd_wa->sessionId = cesa_ocf_cur_ses->frag_wa_decrypt; -+ cesa_cmd->sessionId = cesa_ocf_cur_ses->frag_wa_auth; -+ } -+ else if((encrypt) && (cesa_ocf_cur_ses->encrypt_tn_auth)) { -+ cesa_cmd_wa->sessionId = cesa_ocf_cur_ses->frag_wa_encrypt; -+ cesa_cmd->sessionId = cesa_ocf_cur_ses->frag_wa_auth; -+ } -+ else if((encrypt) && !(cesa_ocf_cur_ses->encrypt_tn_auth)){ -+ cesa_cmd_wa->sessionId = cesa_ocf_cur_ses->frag_wa_auth; -+ cesa_cmd->sessionId = cesa_ocf_cur_ses->frag_wa_encrypt; -+ } -+ else { -+ printk("%s,%d: Unsupporterd fragment wa mode \n", __FILE__, __LINE__); -+ goto p_error; -+ } -+ -+ /* send the 2 actions to the HAL */ -+ spin_lock_irqsave(&cesa_lock, flags); -+ status = mvCesaAction(cesa_cmd_wa); -+ spin_unlock_irqrestore(&cesa_lock, flags); -+ -+ if((status != MV_NO_MORE) && (status != MV_OK)) { -+ printk("%s,%d: cesa action failed, status = 0x%x\n", __FILE__, __LINE__, status); -+ goto p_error; -+ } -+ spin_lock_irqsave(&cesa_lock, flags); -+ status = mvCesaAction(cesa_cmd); -+ spin_unlock_irqrestore(&cesa_lock, flags); -+ -+ } -+ /* action not allowed and can't split */ -+ else -+#endif -+ { -+ goto p_error; -+ } -+ } -+ -+ /* Hal Q is full, send again. This should never happen */ -+ if(status == MV_NO_RESOURCE) { -+ printk("%s,%d: cesa no more resources \n", __FILE__, __LINE__); -+ if(cesa_ocf_cmd) -+ kfree(cesa_ocf_cmd); -+ if(cesa_ocf_cmd_wa) -+ kfree(cesa_ocf_cmd_wa); -+ return ERESTART; -+ } -+ else if((status != MV_NO_MORE) && (status != MV_OK)) { -+ printk("%s,%d: cesa action failed, status = 0x%x\n", __FILE__, __LINE__, status); -+ goto p_error; -+ } -+ -+ -+#ifdef CESA_OCF_POLLING -+ cesa_interrupt_polling(); -+#endif -+ cesaTestTraceAdd(5); -+ -+ return 0; -+p_error: -+ crp->crp_etype = EINVAL; -+ if(cesa_ocf_cmd) -+ kfree(cesa_ocf_cmd); -+ if(cesa_ocf_cmd_wa) -+ kfree(cesa_ocf_cmd_wa); -+ return EINVAL; -+} -+ -+/* -+ * cesa callback. -+ */ -+static void -+cesa_callback(unsigned long dummy) -+{ -+ struct cesa_ocf_process *cesa_ocf_cmd = NULL; -+ struct cryptop *crp = NULL; -+ MV_CESA_RESULT result[MV_CESA_MAX_CHAN]; -+ int res_idx = 0,i; -+ MV_STATUS status; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+#ifdef CESA_OCF_TASKLET -+ disable_irq(cesa_device.irq); -+#endif -+ while(MV_TRUE) { -+ -+ /* Get Ready requests */ -+ spin_lock(&cesa_lock); -+ status = mvCesaReadyGet(&result[res_idx]); -+ spin_unlock(&cesa_lock); -+ -+ cesaTestTraceAdd(2); -+ -+ if(status != MV_OK) { -+#ifdef CESA_OCF_POLLING -+ if(status == MV_BUSY) { /* Fragment */ -+ cesa_interrupt_polling(); -+ return; -+ } -+#endif -+ break; -+ } -+ res_idx++; -+ break; -+ } -+ -+ for(i = 0; i < res_idx; i++) { -+ -+ if(!result[i].pReqPrv) { -+ printk("%s,%d: warning private is NULL\n", __FILE__, __LINE__); -+ break; -+ } -+ -+ cesa_ocf_cmd = result[i].pReqPrv; -+ crp = cesa_ocf_cmd->crp; -+ -+ // ignore HMAC error. -+ //if(result->retCode) -+ // crp->crp_etype = EIO; -+ -+#if defined(CESA_OCF_POLLING) -+ if(!cesa_ocf_cmd->need_cb){ -+ cesa_interrupt_polling(); -+ } -+#endif -+ if(cesa_ocf_cmd->need_cb) { -+ if(debug) { -+ mvCesaDebugMbuf("DST BUFFER", cesa_ocf_cmd->cesa_cmd.pDst, 0, cesa_ocf_cmd->cesa_cmd.pDst->mbufSize); -+ } -+ crypto_done(crp); -+ } -+ kfree(cesa_ocf_cmd); -+ } -+#ifdef CESA_OCF_TASKLET -+ enable_irq(cesa_device.irq); -+#endif -+ -+ cesaTestTraceAdd(3); -+ -+ return; -+} -+ -+#ifdef CESA_OCF_POLLING -+static void -+cesa_interrupt_polling(void) -+{ -+ u32 cause; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ /* Read cause register */ -+ do { -+ cause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); -+ cause &= MV_CESA_CAUSE_ACC_DMA_ALL_MASK; -+ -+ } while (cause == 0); -+ -+ /* clear interrupts */ -+ MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); -+ -+ cesa_callback(0); -+ -+ return; -+} -+ -+#endif -+ -+/* -+ * cesa Interrupt polling routine. -+ */ -+static irqreturn_t -+cesa_interrupt_handler(int irq, void *arg) -+{ -+ u32 cause; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ cesaTestTraceAdd(0); -+ -+ /* Read cause register */ -+ cause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); -+ -+ if( (cause & MV_CESA_CAUSE_ACC_DMA_ALL_MASK) == 0) -+ { -+ /* Empty interrupt */ -+ dprintk("%s,%d: cesaTestReadyIsr: cause=0x%x\n", __FILE__, __LINE__, cause); -+ return IRQ_HANDLED; -+ } -+ -+ /* clear interrupts */ -+ MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); -+ -+ cesaTestTraceAdd(1); -+#ifdef CESA_OCF_TASKLET -+ tasklet_hi_schedule(&cesa_ocf_tasklet); -+#else -+ cesa_callback(0); -+#endif -+ return IRQ_HANDLED; -+} -+ -+/* -+ * Open a session. -+ */ -+static int -+/*cesa_ocf_newsession(void *arg, u_int32_t *sid, struct cryptoini *cri)*/ -+cesa_ocf_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) -+{ -+ u32 status = 0, i; -+ u32 count = 0, auth = 0, encrypt =0; -+ struct cesa_ocf_data *cesa_ocf_cur_ses; -+ MV_CESA_OPEN_SESSION cesa_session; -+ MV_CESA_OPEN_SESSION *cesa_ses = &cesa_session; -+ -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid == NULL || cri == NULL) { -+ printk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ /* leave first empty like in other implementations */ -+ for (i = 1; i < CESA_OCF_MAX_SES; i++) { -+ if (cesa_ocf_sessions[i] == NULL) -+ break; -+ } -+ -+ if(i >= CESA_OCF_MAX_SES) { -+ printk("%s,%d: no more sessions \n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ cesa_ocf_sessions[i] = (struct cesa_ocf_data *) kmalloc(sizeof(struct cesa_ocf_data), GFP_ATOMIC); -+ if (cesa_ocf_sessions[i] == NULL) { -+ cesa_ocf_freesession(NULL, i); -+ printk("%s,%d: ENOBUFS \n", __FILE__, __LINE__); -+ return ENOBUFS; -+ } -+ dprintk("%s,%d: new session %d \n", __FILE__, __LINE__, i); -+ -+ *sid = i; -+ cesa_ocf_cur_ses = cesa_ocf_sessions[i]; -+ memset(cesa_ocf_cur_ses, 0, sizeof(struct cesa_ocf_data)); -+ cesa_ocf_cur_ses->sid_encrypt = -1; -+ cesa_ocf_cur_ses->sid_decrypt = -1; -+ cesa_ocf_cur_ses->frag_wa_encrypt = -1; -+ cesa_ocf_cur_ses->frag_wa_decrypt = -1; -+ cesa_ocf_cur_ses->frag_wa_auth = -1; -+ -+ /* init the session */ -+ memset(cesa_ses, 0, sizeof(MV_CESA_OPEN_SESSION)); -+ count = 1; -+ while (cri) { -+ if(count > 2) { -+ printk("%s,%d: don't support more then 2 operations\n", __FILE__, __LINE__); -+ goto error; -+ } -+ switch (cri->cri_alg) { -+ case CRYPTO_AES_CBC: -+ dprintk("%s,%d: (%d) AES CBC \n", __FILE__, __LINE__, count); -+ cesa_ocf_cur_ses->cipher_alg = cri->cri_alg; -+ cesa_ocf_cur_ses->ivlen = MV_CESA_AES_BLOCK_SIZE; -+ cesa_ses->cryptoAlgorithm = MV_CESA_CRYPTO_AES; -+ cesa_ses->cryptoMode = MV_CESA_CRYPTO_CBC; -+ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { -+ printk("%s,%d: CRYPTO key too long.\n", __FILE__, __LINE__); -+ goto error; -+ } -+ memcpy(cesa_ses->cryptoKey, cri->cri_key, cri->cri_klen/8); -+ dprintk("%s,%d: key length %d \n", __FILE__, __LINE__, cri->cri_klen/8); -+ cesa_ses->cryptoKeyLength = cri->cri_klen/8; -+ encrypt += count; -+ break; -+ case CRYPTO_3DES_CBC: -+ dprintk("%s,%d: (%d) 3DES CBC \n", __FILE__, __LINE__, count); -+ cesa_ocf_cur_ses->cipher_alg = cri->cri_alg; -+ cesa_ocf_cur_ses->ivlen = MV_CESA_3DES_BLOCK_SIZE; -+ cesa_ses->cryptoAlgorithm = MV_CESA_CRYPTO_3DES; -+ cesa_ses->cryptoMode = MV_CESA_CRYPTO_CBC; -+ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { -+ printk("%s,%d: CRYPTO key too long.\n", __FILE__, __LINE__); -+ goto error; -+ } -+ memcpy(cesa_ses->cryptoKey, cri->cri_key, cri->cri_klen/8); -+ cesa_ses->cryptoKeyLength = cri->cri_klen/8; -+ encrypt += count; -+ break; -+ case CRYPTO_DES_CBC: -+ dprintk("%s,%d: (%d) DES CBC \n", __FILE__, __LINE__, count); -+ cesa_ocf_cur_ses->cipher_alg = cri->cri_alg; -+ cesa_ocf_cur_ses->ivlen = MV_CESA_DES_BLOCK_SIZE; -+ cesa_ses->cryptoAlgorithm = MV_CESA_CRYPTO_DES; -+ cesa_ses->cryptoMode = MV_CESA_CRYPTO_CBC; -+ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { -+ printk("%s,%d: CRYPTO key too long.\n", __FILE__, __LINE__); -+ goto error; -+ } -+ memcpy(cesa_ses->cryptoKey, cri->cri_key, cri->cri_klen/8); -+ cesa_ses->cryptoKeyLength = cri->cri_klen/8; -+ encrypt += count; -+ break; -+ case CRYPTO_MD5: -+ case CRYPTO_MD5_HMAC: -+ dprintk("%s,%d: (%d) %sMD5 CBC \n", __FILE__, __LINE__, count, (cri->cri_alg != CRYPTO_MD5)? "H-":" "); -+ cesa_ocf_cur_ses->auth_alg = cri->cri_alg; -+ cesa_ocf_cur_ses->digestlen = (cri->cri_alg == CRYPTO_MD5)? MV_CESA_MD5_DIGEST_SIZE : 12; -+ cesa_ses->macMode = (cri->cri_alg == CRYPTO_MD5)? MV_CESA_MAC_MD5 : MV_CESA_MAC_HMAC_MD5; -+ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { -+ printk("%s,%d: MAC key too long. \n", __FILE__, __LINE__); -+ goto error; -+ } -+ cesa_ses->macKeyLength = cri->cri_klen/8; -+ memcpy(cesa_ses->macKey, cri->cri_key, cri->cri_klen/8); -+ cesa_ses->digestSize = cesa_ocf_cur_ses->digestlen; -+ auth += count; -+ break; -+ case CRYPTO_SHA1: -+ case CRYPTO_SHA1_HMAC: -+ dprintk("%s,%d: (%d) %sSHA1 CBC \n", __FILE__, __LINE__, count, (cri->cri_alg != CRYPTO_SHA1)? "H-":" "); -+ cesa_ocf_cur_ses->auth_alg = cri->cri_alg; -+ cesa_ocf_cur_ses->digestlen = (cri->cri_alg == CRYPTO_SHA1)? MV_CESA_SHA1_DIGEST_SIZE : 12; -+ cesa_ses->macMode = (cri->cri_alg == CRYPTO_SHA1)? MV_CESA_MAC_SHA1 : MV_CESA_MAC_HMAC_SHA1; -+ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { -+ printk("%s,%d: MAC key too long. \n", __FILE__, __LINE__); -+ goto error; -+ } -+ cesa_ses->macKeyLength = cri->cri_klen/8; -+ memcpy(cesa_ses->macKey, cri->cri_key, cri->cri_klen/8); -+ cesa_ses->digestSize = cesa_ocf_cur_ses->digestlen; -+ auth += count; -+ break; -+ default: -+ printk("%s,%d: unknown algo 0x%x\n", __FILE__, __LINE__, cri->cri_alg); -+ goto error; -+ } -+ cri = cri->cri_next; -+ count++; -+ } -+ -+ if((encrypt > 2) || (auth > 2)) { -+ printk("%s,%d: session mode is not supported.\n", __FILE__, __LINE__); -+ goto error; -+ } -+ /* create new sessions in HAL */ -+ if(encrypt) { -+ cesa_ses->operation = MV_CESA_CRYPTO_ONLY; -+ /* encrypt session */ -+ if(auth == 1) { -+ cesa_ses->operation = MV_CESA_MAC_THEN_CRYPTO; -+ } -+ else if(auth == 2) { -+ cesa_ses->operation = MV_CESA_CRYPTO_THEN_MAC; -+ cesa_ocf_cur_ses->encrypt_tn_auth = 1; -+ } -+ else { -+ cesa_ses->operation = MV_CESA_CRYPTO_ONLY; -+ } -+ cesa_ses->direction = MV_CESA_DIR_ENCODE; -+ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->sid_encrypt); -+ if(status != MV_OK) { -+ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); -+ goto error; -+ } -+ /* decrypt session */ -+ if( cesa_ses->operation == MV_CESA_MAC_THEN_CRYPTO ) { -+ cesa_ses->operation = MV_CESA_CRYPTO_THEN_MAC; -+ } -+ else if( cesa_ses->operation == MV_CESA_CRYPTO_THEN_MAC ) { -+ cesa_ses->operation = MV_CESA_MAC_THEN_CRYPTO; -+ } -+ cesa_ses->direction = MV_CESA_DIR_DECODE; -+ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->sid_decrypt); -+ if(status != MV_OK) { -+ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); -+ goto error; -+ } -+ -+ /* preapre one action sessions for case we will need to split an action */ -+#ifdef CESA_OCF_SPLIT -+ if(( cesa_ses->operation == MV_CESA_MAC_THEN_CRYPTO ) || -+ ( cesa_ses->operation == MV_CESA_CRYPTO_THEN_MAC )) { -+ /* open one session for encode and one for decode */ -+ cesa_ses->operation = MV_CESA_CRYPTO_ONLY; -+ cesa_ses->direction = MV_CESA_DIR_ENCODE; -+ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->frag_wa_encrypt); -+ if(status != MV_OK) { -+ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); -+ goto error; -+ } -+ -+ cesa_ses->direction = MV_CESA_DIR_DECODE; -+ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->frag_wa_decrypt); -+ if(status != MV_OK) { -+ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); -+ goto error; -+ } -+ /* open one session for auth */ -+ cesa_ses->operation = MV_CESA_MAC_ONLY; -+ cesa_ses->direction = MV_CESA_DIR_ENCODE; -+ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->frag_wa_auth); -+ if(status != MV_OK) { -+ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); -+ goto error; -+ } -+ } -+#endif -+ } -+ else { /* only auth */ -+ cesa_ses->operation = MV_CESA_MAC_ONLY; -+ cesa_ses->direction = MV_CESA_DIR_ENCODE; -+ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->sid_encrypt); -+ if(status != MV_OK) { -+ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); -+ goto error; -+ } -+ } -+ -+ return 0; -+error: -+ cesa_ocf_freesession(NULL, *sid); -+ return EINVAL; -+ -+} -+ -+ -+/* -+ * Free a session. -+ */ -+static int -+cesa_ocf_freesession(device_t dev, u_int64_t tid) -+{ -+ struct cesa_ocf_data *cesa_ocf_cur_ses; -+ u_int32_t sid = CRYPTO_SESID2LID(tid); -+ //unsigned long flags; -+ -+ dprintk("%s() %d \n", __FUNCTION__, sid); -+ if ( (sid >= CESA_OCF_MAX_SES) || (cesa_ocf_sessions[sid] == NULL) ) { -+ printk("%s,%d: EINVAL can't free session %d \n", __FILE__, __LINE__, sid); -+ return(EINVAL); -+ } -+ -+ /* Silently accept and return */ -+ if (sid == 0) -+ return(0); -+ -+ /* release session from HAL */ -+ cesa_ocf_cur_ses = cesa_ocf_sessions[sid]; -+ if (cesa_ocf_cur_ses->sid_encrypt != -1) { -+ mvCesaSessionClose(cesa_ocf_cur_ses->sid_encrypt); -+ } -+ if (cesa_ocf_cur_ses->sid_decrypt != -1) { -+ mvCesaSessionClose(cesa_ocf_cur_ses->sid_decrypt); -+ } -+ if (cesa_ocf_cur_ses->frag_wa_encrypt != -1) { -+ mvCesaSessionClose(cesa_ocf_cur_ses->frag_wa_encrypt); -+ } -+ if (cesa_ocf_cur_ses->frag_wa_decrypt != -1) { -+ mvCesaSessionClose(cesa_ocf_cur_ses->frag_wa_decrypt); -+ } -+ if (cesa_ocf_cur_ses->frag_wa_auth != -1) { -+ mvCesaSessionClose(cesa_ocf_cur_ses->frag_wa_auth); -+ } -+ -+ kfree(cesa_ocf_cur_ses); -+ cesa_ocf_sessions[sid] = NULL; -+ -+ return 0; -+} -+ -+ -+/* TDMA Window setup */ -+ -+static void __init -+setup_tdma_mbus_windows(struct cesa_dev *dev) -+{ -+ int i; -+ -+ for (i = 0; i < 4; i++) { -+ writel(0, dev->reg + WINDOW_BASE(i)); -+ writel(0, dev->reg + WINDOW_CTRL(i)); -+ } -+ -+ for (i = 0; i < dev->plat_data->dram->num_cs; i++) { -+ struct mbus_dram_window *cs = dev->plat_data->dram->cs + i; -+ writel( -+ ((cs->size - 1) & 0xffff0000) | -+ (cs->mbus_attr << 8) | -+ (dev->plat_data->dram->mbus_dram_target_id << 4) | 1, -+ dev->reg + WINDOW_CTRL(i) -+ ); -+ writel(cs->base, dev->reg + WINDOW_BASE(i)); -+ } -+} -+ -+/* -+ * our driver startup and shutdown routines -+ */ -+static int -+mv_cesa_ocf_init(struct platform_device *pdev) -+{ -+#if defined(CONFIG_MV78200) || defined(CONFIG_MV632X) -+ if (MV_FALSE == mvSocUnitIsMappedToThisCpu(CESA)) -+ { -+ dprintk("CESA is not mapped to this CPU\n"); -+ return -ENODEV; -+ } -+#endif -+ -+ dprintk("%s\n", __FUNCTION__); -+ memset(&mv_cesa_dev, 0, sizeof(mv_cesa_dev)); -+ softc_device_init(&mv_cesa_dev, "MV CESA", 0, mv_cesa_methods); -+ cesa_ocf_id = crypto_get_driverid(softc_get_device(&mv_cesa_dev),CRYPTOCAP_F_HARDWARE); -+ -+ if (cesa_ocf_id < 0) -+ panic("MV CESA crypto device cannot initialize!"); -+ -+ dprintk("%s,%d: cesa ocf device id is %d \n", __FILE__, __LINE__, cesa_ocf_id); -+ -+ /* CESA unit is auto power on off */ -+#if 0 -+ if (MV_FALSE == mvCtrlPwrClckGet(CESA_UNIT_ID,0)) -+ { -+ printk("\nWarning CESA %d is Powered Off\n",0); -+ return EINVAL; -+ } -+#endif -+ -+ memset(&cesa_device, 0, sizeof(struct cesa_dev)); -+ /* Get the IRQ, and crypto memory regions */ -+ { -+ struct resource *res; -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram"); -+ -+ if (!res) -+ return -ENXIO; -+ -+ cesa_device.sram = ioremap(res->start, res->end - res->start + 1); -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); -+ -+ if (!res) { -+ iounmap(cesa_device.sram); -+ return -ENXIO; -+ } -+ cesa_device.reg = ioremap(res->start, res->end - res->start + 1); -+ cesa_device.irq = platform_get_irq(pdev, 0); -+ cesa_device.plat_data = pdev->dev.platform_data; -+ setup_tdma_mbus_windows(&cesa_device); -+ -+ } -+ -+ -+ if( MV_OK != mvCesaInit(CESA_OCF_MAX_SES*5, CESA_Q_SIZE, cesa_device.reg, -+ NULL) ) { -+ printk("%s,%d: mvCesaInit Failed. \n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ /* clear and unmask Int */ -+ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); -+#ifndef CESA_OCF_POLLING -+ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, MV_CESA_CAUSE_ACC_DMA_MASK); -+#endif -+#ifdef CESA_OCF_TASKLET -+ tasklet_init(&cesa_ocf_tasklet, cesa_callback, (unsigned int) 0); -+#endif -+ /* register interrupt */ -+ if( request_irq( cesa_device.irq, cesa_interrupt_handler, -+ (IRQF_DISABLED) , "cesa", &cesa_ocf_id) < 0) { -+ printk("%s,%d: cannot assign irq %x\n", __FILE__, __LINE__, cesa_device.reg); -+ return EINVAL; -+ } -+ -+ -+ memset(cesa_ocf_sessions, 0, sizeof(struct cesa_ocf_data *) * CESA_OCF_MAX_SES); -+ -+#define REGISTER(alg) \ -+ crypto_register(cesa_ocf_id, alg, 0,0) -+ REGISTER(CRYPTO_AES_CBC); -+ REGISTER(CRYPTO_DES_CBC); -+ REGISTER(CRYPTO_3DES_CBC); -+ REGISTER(CRYPTO_MD5); -+ REGISTER(CRYPTO_MD5_HMAC); -+ REGISTER(CRYPTO_SHA1); -+ REGISTER(CRYPTO_SHA1_HMAC); -+#undef REGISTER -+ -+ return 0; -+} -+ -+static void -+mv_cesa_ocf_exit(struct platform_device *pdev) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ crypto_unregister_all(cesa_ocf_id); -+ cesa_ocf_id = -1; -+ iounmap(cesa_device.reg); -+ iounmap(cesa_device.sram); -+ free_irq(cesa_device.irq, NULL); -+ -+ /* mask and clear Int */ -+ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, 0); -+ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); -+ -+ -+ if( MV_OK != mvCesaFinish() ) { -+ printk("%s,%d: mvCesaFinish Failed. \n", __FILE__, __LINE__); -+ return; -+ } -+} -+ -+ -+void cesa_ocf_debug(void) -+{ -+ -+#ifdef CESA_OCF_TRACE_DEBUG -+ { -+ int i, j; -+ j = cesaTestTraceIdx; -+ mvOsPrintf("No Type rCause iCause Proc Isr Res Time pReady pProc pEmpty\n"); -+ for(i=0; i= _1G) -+ { -+ mvOsOutput("%3dGB ", size / _1G); -+ size %= _1G; -+ if(size) -+ mvOsOutput("+"); -+ } -+ if(size >= _1M ) -+ { -+ mvOsOutput("%3dMB ", size / _1M); -+ size %= _1M; -+ if(size) -+ mvOsOutput("+"); -+ } -+ if(size >= _1K) -+ { -+ mvOsOutput("%3dKB ", size / _1K); -+ size %= _1K; -+ if(size) -+ mvOsOutput("+"); -+ } -+ if(size > 0) -+ { -+ mvOsOutput("%3dB ", size); -+ } -+} -+ -+/******************************************************************************* -+* mvHexToBin - Convert hex to binary -+* -+* DESCRIPTION: -+* This function Convert hex to binary. -+* -+* INPUT: -+* pHexStr - hex buffer pointer. -+* size - Size to convert. -+* -+* OUTPUT: -+* pBin - Binary buffer pointer. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvHexToBin(const char* pHexStr, MV_U8* pBin, int size) -+{ -+ int j, i; -+ char tmp[3]; -+ MV_U8 byte; -+ -+ for(j=0, i=0; j> 1; -+ result++; -+ } -+ return result; -+} -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvCommon.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvCommon.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvCommon.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvCommon.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,308 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+ -+#ifndef __INCmvCommonh -+#define __INCmvCommonh -+ -+#include "mvTypes.h" -+ -+/* Swap tool */ -+ -+/* 16bit nibble swap. For example 0x1234 -> 0x2143 */ -+#define MV_NIBBLE_SWAP_16BIT(X) (((X&0xf) << 4) | \ -+ ((X&0xf0) >> 4) | \ -+ ((X&0xf00) << 4) | \ -+ ((X&0xf000) >> 4)) -+ -+/* 32bit nibble swap. For example 0x12345678 -> 0x21436587 */ -+#define MV_NIBBLE_SWAP_32BIT(X) (((X&0xf) << 4) | \ -+ ((X&0xf0) >> 4) | \ -+ ((X&0xf00) << 4) | \ -+ ((X&0xf000) >> 4) | \ -+ ((X&0xf0000) << 4) | \ -+ ((X&0xf00000) >> 4) | \ -+ ((X&0xf000000) << 4) | \ -+ ((X&0xf0000000) >> 4)) -+ -+/* 16bit byte swap. For example 0x1122 -> 0x2211 */ -+#define MV_BYTE_SWAP_16BIT(X) ((((X)&0xff)<<8) | (((X)&0xff00)>>8)) -+ -+/* 32bit byte swap. For example 0x11223344 -> 0x44332211 */ -+#define MV_BYTE_SWAP_32BIT(X) ((((X)&0xff)<<24) | \ -+ (((X)&0xff00)<<8) | \ -+ (((X)&0xff0000)>>8) | \ -+ (((X)&0xff000000)>>24)) -+ -+/* 64bit byte swap. For example 0x11223344.55667788 -> 0x88776655.44332211 */ -+#define MV_BYTE_SWAP_64BIT(X) ((l64) ((((X)&0xffULL)<<56) | \ -+ (((X)&0xff00ULL)<<40) | \ -+ (((X)&0xff0000ULL)<<24) | \ -+ (((X)&0xff000000ULL)<<8) | \ -+ (((X)&0xff00000000ULL)>>8) | \ -+ (((X)&0xff0000000000ULL)>>24) | \ -+ (((X)&0xff000000000000ULL)>>40) | \ -+ (((X)&0xff00000000000000ULL)>>56))) -+ -+/* Endianess macros. */ -+#if defined(MV_CPU_LE) -+ #define MV_16BIT_LE(X) (X) -+ #define MV_32BIT_LE(X) (X) -+ #define MV_64BIT_LE(X) (X) -+ #define MV_16BIT_BE(X) MV_BYTE_SWAP_16BIT(X) -+ #define MV_32BIT_BE(X) MV_BYTE_SWAP_32BIT(X) -+ #define MV_64BIT_BE(X) MV_BYTE_SWAP_64BIT(X) -+#elif defined(MV_CPU_BE) -+ #define MV_16BIT_LE(X) MV_BYTE_SWAP_16BIT(X) -+ #define MV_32BIT_LE(X) MV_BYTE_SWAP_32BIT(X) -+ #define MV_64BIT_LE(X) MV_BYTE_SWAP_64BIT(X) -+ #define MV_16BIT_BE(X) (X) -+ #define MV_32BIT_BE(X) (X) -+ #define MV_64BIT_BE(X) (X) -+#else -+ #error "CPU endianess isn't defined!\n" -+#endif -+ -+ -+/* Bit field definitions */ -+#define NO_BIT 0x00000000 -+#define BIT0 0x00000001 -+#define BIT1 0x00000002 -+#define BIT2 0x00000004 -+#define BIT3 0x00000008 -+#define BIT4 0x00000010 -+#define BIT5 0x00000020 -+#define BIT6 0x00000040 -+#define BIT7 0x00000080 -+#define BIT8 0x00000100 -+#define BIT9 0x00000200 -+#define BIT10 0x00000400 -+#define BIT11 0x00000800 -+#define BIT12 0x00001000 -+#define BIT13 0x00002000 -+#define BIT14 0x00004000 -+#define BIT15 0x00008000 -+#define BIT16 0x00010000 -+#define BIT17 0x00020000 -+#define BIT18 0x00040000 -+#define BIT19 0x00080000 -+#define BIT20 0x00100000 -+#define BIT21 0x00200000 -+#define BIT22 0x00400000 -+#define BIT23 0x00800000 -+#define BIT24 0x01000000 -+#define BIT25 0x02000000 -+#define BIT26 0x04000000 -+#define BIT27 0x08000000 -+#define BIT28 0x10000000 -+#define BIT29 0x20000000 -+#define BIT30 0x40000000 -+#define BIT31 0x80000000 -+ -+/* Handy sizes */ -+#define _1K 0x00000400 -+#define _2K 0x00000800 -+#define _4K 0x00001000 -+#define _8K 0x00002000 -+#define _16K 0x00004000 -+#define _32K 0x00008000 -+#define _64K 0x00010000 -+#define _128K 0x00020000 -+#define _256K 0x00040000 -+#define _512K 0x00080000 -+ -+#define _1M 0x00100000 -+#define _2M 0x00200000 -+#define _4M 0x00400000 -+#define _8M 0x00800000 -+#define _16M 0x01000000 -+#define _32M 0x02000000 -+#define _64M 0x04000000 -+#define _128M 0x08000000 -+#define _256M 0x10000000 -+#define _512M 0x20000000 -+ -+#define _1G 0x40000000 -+#define _2G 0x80000000 -+ -+/* Tclock and Sys clock define */ -+#define _100MHz 100000000 -+#define _125MHz 125000000 -+#define _133MHz 133333334 -+#define _150MHz 150000000 -+#define _160MHz 160000000 -+#define _166MHz 166666667 -+#define _175MHz 175000000 -+#define _178MHz 178000000 -+#define _183MHz 183333334 -+#define _187MHz 187000000 -+#define _192MHz 192000000 -+#define _194MHz 194000000 -+#define _200MHz 200000000 -+#define _233MHz 233333334 -+#define _250MHz 250000000 -+#define _266MHz 266666667 -+#define _300MHz 300000000 -+ -+/* For better address window table readability */ -+#define EN MV_TRUE -+#define DIS MV_FALSE -+#define N_A -1 /* Not applicable */ -+ -+/* Cache configuration options for memory (DRAM, SRAM, ... ) */ -+ -+/* Memory uncached, HW or SW cache coherency is not needed */ -+#define MV_UNCACHED 0 -+/* Memory cached, HW cache coherency supported in WriteThrough mode */ -+#define MV_CACHE_COHER_HW_WT 1 -+/* Memory cached, HW cache coherency supported in WriteBack mode */ -+#define MV_CACHE_COHER_HW_WB 2 -+/* Memory cached, No HW cache coherency, Cache coherency must be in SW */ -+#define MV_CACHE_COHER_SW 3 -+ -+ -+/* Macro for testing aligment. Positive if number is NOT aligned */ -+#define MV_IS_NOT_ALIGN(number, align) ((number) & ((align) - 1)) -+ -+/* Macro for alignment up. For example, MV_ALIGN_UP(0x0330, 0x20) = 0x0340 */ -+#define MV_ALIGN_UP(number, align) \ -+(((number) & ((align) - 1)) ? (((number) + (align)) & ~((align)-1)) : (number)) -+ -+/* Macro for alignment down. For example, MV_ALIGN_UP(0x0330, 0x20) = 0x0320 */ -+#define MV_ALIGN_DOWN(number, align) ((number) & ~((align)-1)) -+ -+/* This macro returns absolute value */ -+#define MV_ABS(number) (((int)(number) < 0) ? -(int)(number) : (int)(number)) -+ -+ -+/* Bit fields manipulation macros */ -+ -+/* An integer word which its 'x' bit is set */ -+#define MV_BIT_MASK(bitNum) (1 << (bitNum) ) -+ -+/* Checks wheter bit 'x' in integer word is set */ -+#define MV_BIT_CHECK(word, bitNum) ( (word) & MV_BIT_MASK(bitNum) ) -+ -+/* Clear (reset) bit 'x' in integer word (RMW - Read-Modify-Write) */ -+#define MV_BIT_CLEAR(word, bitNum) ( (word) &= ~(MV_BIT_MASK(bitNum)) ) -+ -+/* Set bit 'x' in integer word (RMW) */ -+#define MV_BIT_SET(word, bitNum) ( (word) |= MV_BIT_MASK(bitNum) ) -+ -+/* Invert bit 'x' in integer word (RMW) */ -+#define MV_BIT_INV(word, bitNum) ( (word) ^= MV_BIT_MASK(bitNum) ) -+ -+/* Get the min between 'a' or 'b' */ -+#define MV_MIN(a,b) (((a) < (b)) ? (a) : (b)) -+ -+/* Get the max between 'a' or 'b' */ -+#define MV_MAX(a,b) (((a) < (b)) ? (b) : (a)) -+ -+/* Temporary */ -+#define mvOsDivide(num, div) \ -+({ \ -+ int i=0, rem=(num); \ -+ \ -+ while(rem >= (div)) \ -+ { \ -+ rem -= (div); \ -+ i++; \ -+ } \ -+ (i); \ -+}) -+ -+/* Temporary */ -+#define mvOsReminder(num, div) \ -+({ \ -+ int rem = (num); \ -+ \ -+ while(rem >= (div)) \ -+ rem -= (div); \ -+ (rem); \ -+}) -+ -+#define MV_IP_QUAD(ipAddr) ((ipAddr >> 24) & 0xFF), ((ipAddr >> 16) & 0xFF), \ -+ ((ipAddr >> 8) & 0xFF), ((ipAddr >> 0) & 0xFF) -+ -+#define MV_IS_POWER_OF_2(num) ((num != 0) && ((num & (num - 1)) == 0)) -+ -+#ifndef MV_ASMLANGUAGE -+/* mvCommon API list */ -+ -+MV_VOID mvHexToBin(const char* pHexStr, MV_U8* pBin, int size); -+void mvAsciiToHex(const char* asciiStr, char* hexStr); -+void mvBinToHex(const MV_U8* bin, char* hexStr, int size); -+void mvBinToAscii(const MV_U8* bin, char* asciiStr, int size); -+ -+MV_STATUS mvMacStrToHex(const char* macStr, MV_U8* macHex); -+MV_STATUS mvMacHexToStr(MV_U8* macHex, char* macStr); -+void mvSizePrint(MV_U32); -+ -+MV_U32 mvLog2(MV_U32 num); -+ -+#endif /* MV_ASMLANGUAGE */ -+ -+ -+#endif /* __INCmvCommonh */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvCompVer.txt linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvCompVer.txt ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvCompVer.txt 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvCompVer.txt 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,4 @@ -+Global HAL Version: FEROCEON_HAL_3_1_7 -+Unit HAL Version: 3.1.4 -+Description: This component includes an implementation of the unit HAL drivers -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvDebug.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvDebug.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvDebug.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvDebug.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,326 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+ -+/* includes */ -+#include "mvOs.h" -+#include "mv802_3.h" -+#include "mvCommon.h" -+#include "mvDebug.h" -+ -+/* Global variables effect on behave MV_DEBUG_PRINT and MV_DEBUG_CODE macros -+ * mvDebug - map of bits (one for each module) bit=1 means enable -+ * debug code and messages for this module -+ * mvModuleDebug - array of 32 bits varables one for each module -+ */ -+MV_U32 mvDebug = 0; -+MV_U32 mvDebugModules[MV_MODULE_MAX]; -+ -+/* Init mvModuleDebug array to default values */ -+void mvDebugInit(void) -+{ -+ int bit; -+ -+ mvDebug = 0; -+ for(bit=0; bit 0) -+ { -+ mvOsPrintf("%08x: ", memAddr); -+ i = 0; -+ /* 32 bytes in the line */ -+ while(i < 32) -+ { -+ if(memAddr >= (MV_U32)addr) -+ { -+ switch(access) -+ { -+ case 1: -+ if( memAddr == CPU_PHY_MEM(memAddr) ) -+ { -+ mvOsPrintf("%02x ", MV_MEMIO8_READ(memAddr)); -+ } -+ else -+ { -+ mvOsPrintf("%02x ", *((MV_U8*)memAddr)); -+ } -+ break; -+ -+ case 2: -+ if( memAddr == CPU_PHY_MEM(memAddr) ) -+ { -+ mvOsPrintf("%04x ", MV_MEMIO16_READ(memAddr)); -+ } -+ else -+ { -+ mvOsPrintf("%04x ", *((MV_U16*)memAddr)); -+ } -+ break; -+ -+ case 4: -+ if( memAddr == CPU_PHY_MEM(memAddr) ) -+ { -+ mvOsPrintf("%08x ", MV_MEMIO32_READ(memAddr)); -+ } -+ else -+ { -+ mvOsPrintf("%08x ", *((MV_U32*)memAddr)); -+ } -+ break; -+ } -+ } -+ else -+ { -+ for(j=0; j<(access*2+1); j++) -+ mvOsPrintf(" "); -+ } -+ i += access; -+ memAddr += access; -+ size -= access; -+ if(size <= 0) -+ break; -+ } -+ mvOsPrintf("\n"); -+ } -+} -+ -+void mvDebugPrintBufInfo(BUF_INFO* pBufInfo, int size, int access) -+{ -+ if(pBufInfo == NULL) -+ { -+ mvOsPrintf("\n!!! pBufInfo = NULL\n"); -+ return; -+ } -+ mvOsPrintf("\n*** pBufInfo=0x%x, cmdSts=0x%08x, pBuf=0x%x, bufSize=%d\n", -+ (unsigned int)pBufInfo, -+ (unsigned int)pBufInfo->cmdSts, -+ (unsigned int)pBufInfo->pBuff, -+ (unsigned int)pBufInfo->bufSize); -+ mvOsPrintf("pData=0x%x, byteCnt=%d, pNext=0x%x, uInfo1=0x%x, uInfo2=0x%x\n", -+ (unsigned int)pBufInfo->pData, -+ (unsigned int)pBufInfo->byteCnt, -+ (unsigned int)pBufInfo->pNextBufInfo, -+ (unsigned int)pBufInfo->userInfo1, -+ (unsigned int)pBufInfo->userInfo2); -+ if(pBufInfo->pData != NULL) -+ { -+ if(size > pBufInfo->byteCnt) -+ size = pBufInfo->byteCnt; -+ mvDebugMemDump(pBufInfo->pData, size, access); -+ } -+} -+ -+void mvDebugPrintPktInfo(MV_PKT_INFO* pPktInfo, int size, int access) -+{ -+ int frag, len; -+ -+ if(pPktInfo == NULL) -+ { -+ mvOsPrintf("\n!!! pPktInfo = NULL\n"); -+ return; -+ } -+ mvOsPrintf("\npPkt=%p, stat=0x%08x, numFr=%d, size=%d, pFr=%p, osInfo=0x%lx\n", -+ pPktInfo, pPktInfo->status, pPktInfo->numFrags, pPktInfo->pktSize, -+ pPktInfo->pFrags, pPktInfo->osInfo); -+ -+ for(frag=0; fragnumFrags; frag++) -+ { -+ mvOsPrintf("#%2d. bufVirt=%p, bufSize=%d\n", -+ frag, pPktInfo->pFrags[frag].bufVirtPtr, -+ pPktInfo->pFrags[frag].bufSize); -+ if(size > 0) -+ { -+ len = MV_MIN((int)pPktInfo->pFrags[frag].bufSize, size); -+ mvDebugMemDump(pPktInfo->pFrags[frag].bufVirtPtr, len, access); -+ size -= len; -+ } -+ } -+ -+} -+ -+void mvDebugPrintIpAddr(MV_U32 ipAddr) -+{ -+ mvOsPrintf("%d.%d.%d.%d", ((ipAddr >> 24) & 0xFF), ((ipAddr >> 16) & 0xFF), -+ ((ipAddr >> 8) & 0xFF), ((ipAddr >> 0) & 0xFF)); -+} -+ -+void mvDebugPrintMacAddr(const MV_U8* pMacAddr) -+{ -+ int i; -+ -+ mvOsPrintf("%02x", (unsigned int)pMacAddr[0]); -+ for(i=1; ibegin = 0; -+ pTimeEntry->count = count; -+ pTimeEntry->end = 0; -+ pTimeEntry->left = pTimeEntry->count; -+ pTimeEntry->total = 0; -+ pTimeEntry->min = 0xFFFFFFFF; -+ pTimeEntry->max = 0x0; -+ strncpy(pTimeEntry->name, pName, sizeof(pTimeEntry->name)-1); -+ pTimeEntry->name[sizeof(pTimeEntry->name)-1] = '\0'; -+} -+ -+/* Print out MV_DEBUG_TIMES entry */ -+void mvDebugPrintTimeEntry(MV_DEBUG_TIMES* pTimeEntry, MV_BOOL isTitle) -+{ -+ int num; -+ -+ if(isTitle == MV_TRUE) -+ mvOsPrintf("Event NumOfEvents TotalTime Average Min Max\n"); -+ -+ num = pTimeEntry->count-pTimeEntry->left; -+ if(num > 0) -+ { -+ mvOsPrintf("%-11s %6u 0x%08lx %6lu %6lu %6lu\n", -+ pTimeEntry->name, num, pTimeEntry->total, pTimeEntry->total/num, -+ pTimeEntry->min, pTimeEntry->max); -+ } -+} -+ -+/* Update MV_DEBUG_TIMES entry */ -+void mvDebugUpdateTimeEntry(MV_DEBUG_TIMES* pTimeEntry) -+{ -+ MV_U32 delta; -+ -+ if(pTimeEntry->left > 0) -+ { -+ if(pTimeEntry->end <= pTimeEntry->begin) -+ { -+ delta = pTimeEntry->begin - pTimeEntry->end; -+ } -+ else -+ { -+ delta = ((MV_U32)0x10000 - pTimeEntry->end) + pTimeEntry->begin; -+ } -+ pTimeEntry->total += delta; -+ -+ if(delta < pTimeEntry->min) -+ pTimeEntry->min = delta; -+ -+ if(delta > pTimeEntry->max) -+ pTimeEntry->max = delta; -+ -+ pTimeEntry->left--; -+ } -+} -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvDebug.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvDebug.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvDebug.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvDebug.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,178 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+ -+#ifndef __INCmvDebugh -+#define __INCmvDebugh -+ -+/* includes */ -+#include "mvTypes.h" -+ -+typedef enum -+{ -+ MV_MODULE_INVALID = -1, -+ MV_MODULE_ETH = 0, -+ MV_MODULE_IDMA, -+ MV_MODULE_XOR, -+ MV_MODULE_TWASI, -+ MV_MODULE_MGI, -+ MV_MODULE_USB, -+ MV_MODULE_CESA, -+ -+ MV_MODULE_MAX -+}MV_MODULE_ID; -+ -+/* Define generic flags useful for most of modules */ -+#define MV_DEBUG_FLAG_ALL (0) -+#define MV_DEBUG_FLAG_INIT (1 << 0) -+#define MV_DEBUG_FLAG_RX (1 << 1) -+#define MV_DEBUG_FLAG_TX (1 << 2) -+#define MV_DEBUG_FLAG_ERR (1 << 3) -+#define MV_DEBUG_FLAG_TRACE (1 << 4) -+#define MV_DEBUG_FLAG_DUMP (1 << 5) -+#define MV_DEBUG_FLAG_CACHE (1 << 6) -+#define MV_DEBUG_FLAG_IOCTL (1 << 7) -+#define MV_DEBUG_FLAG_STATS (1 << 8) -+ -+extern MV_U32 mvDebug; -+extern MV_U32 mvDebugModules[MV_MODULE_MAX]; -+ -+#ifdef MV_DEBUG -+# define MV_DEBUG_PRINT(module, flags, msg) mvOsPrintf msg -+# define MV_DEBUG_CODE(module, flags, code) code -+#elif defined(MV_RT_DEBUG) -+# define MV_DEBUG_PRINT(module, flags, msg) \ -+ if( (mvDebug & (1<<(module))) && \ -+ ((mvDebugModules[(module)] & (flags)) == (flags)) ) \ -+ mvOsPrintf msg -+# define MV_DEBUG_CODE(module, flags, code) \ -+ if( (mvDebug & (1<<(module))) && \ -+ ((mvDebugModules[(module)] & (flags)) == (flags)) ) \ -+ code -+#else -+# define MV_DEBUG_PRINT(module, flags, msg) -+# define MV_DEBUG_CODE(module, flags, code) -+#endif -+ -+ -+ -+/* typedefs */ -+ -+/* time measurement structure used to check how much time pass between -+ * two points -+ */ -+typedef struct { -+ char name[20]; /* name of the entry */ -+ unsigned long begin; /* time measured on begin point */ -+ unsigned long end; /* time measured on end point */ -+ unsigned long total; /* Accumulated time */ -+ unsigned long left; /* The rest measurement actions */ -+ unsigned long count; /* Maximum measurement actions */ -+ unsigned long min; /* Minimum time from begin to end */ -+ unsigned long max; /* Maximum time from begin to end */ -+} MV_DEBUG_TIMES; -+ -+ -+/* mvDebug.h API list */ -+ -+/****** Error Recording ******/ -+ -+/* Dump memory in specific format: -+ * address: X1X1X1X1 X2X2X2X2 ... X8X8X8X8 -+ */ -+void mvDebugMemDump(void* addr, int size, int access); -+ -+void mvDebugPrintBufInfo(BUF_INFO* pBufInfo, int size, int access); -+ -+void mvDebugPrintPktInfo(MV_PKT_INFO* pPktInfo, int size, int access); -+ -+void mvDebugPrintIpAddr(MV_U32 ipAddr); -+ -+void mvDebugPrintMacAddr(const MV_U8* pMacAddr); -+ -+/**** There are three functions deals with MV_DEBUG_TIMES structure ****/ -+ -+/* Reset MV_DEBUG_TIMES entry */ -+void mvDebugResetTimeEntry(MV_DEBUG_TIMES* pTimeEntry, int count, char* name); -+ -+/* Update MV_DEBUG_TIMES entry */ -+void mvDebugUpdateTimeEntry(MV_DEBUG_TIMES* pTimeEntry); -+ -+/* Print out MV_DEBUG_TIMES entry */ -+void mvDebugPrintTimeEntry(MV_DEBUG_TIMES* pTimeEntry, MV_BOOL isTitle); -+ -+ -+/******** General ***********/ -+ -+/* Change value of mvDebugPrint global variable */ -+ -+void mvDebugInit(void); -+void mvDebugModuleEnable(MV_MODULE_ID module, MV_BOOL isEnable); -+void mvDebugModuleSetFlags(MV_MODULE_ID module, MV_U32 flags); -+void mvDebugModuleClearFlags(MV_MODULE_ID module, MV_U32 flags); -+ -+ -+#endif /* __INCmvDebug.h */ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,225 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvDeviceIdh -+#define __INCmvDeviceIdh -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* defines */ -+#define MARVELL_VEN_ID 0x11ab -+ -+/* Disco-3 */ -+#define MV64460_DEV_ID 0x6480 -+#define MV64460B_DEV_ID 0x6485 -+#define MV64430_DEV_ID 0x6420 -+ -+/* Disco-5 */ -+#define MV64560_DEV_ID 0x6450 -+ -+/* Disco-6 */ -+#define MV64660_DEV_ID 0x6460 -+ -+/* Orion */ -+#define MV_1181_DEV_ID 0x1181 -+#define MV_5181_DEV_ID 0x5181 -+#define MV_5281_DEV_ID 0x5281 -+#define MV_5182_DEV_ID 0x5182 -+#define MV_8660_DEV_ID 0x8660 -+#define MV_5180_DEV_ID 0x5180 -+#define MV_5082_DEV_ID 0x5082 -+#define MV_1281_DEV_ID 0x1281 -+#define MV_6082_DEV_ID 0x6082 -+#define MV_6183_DEV_ID 0x6183 -+#define MV_6183L_DEV_ID 0x6083 -+ -+#define MV_5281_D0_REV 0x4 -+#define MV_5281_D0_ID ((MV_5281_DEV_ID << 16) | MV_5281_D0_REV) -+#define MV_5281_D0_NAME "88F5281 D0" -+ -+#define MV_5281_D1_REV 0x5 -+#define MV_5281_D1_ID ((MV_5281_DEV_ID << 16) | MV_5281_D1_REV) -+#define MV_5281_D1_NAME "88F5281 D1" -+ -+#define MV_5281_D2_REV 0x6 -+#define MV_5281_D2_ID ((MV_5281_DEV_ID << 16) | MV_5281_D2_REV) -+#define MV_5281_D2_NAME "88F5281 D2" -+ -+ -+#define MV_5181L_A0_REV 0x8 /* need for PCIE Er */ -+#define MV_5181_A1_REV 0x1 /* for USB Er ..*/ -+#define MV_5181_B0_REV 0x2 -+#define MV_5181_B1_REV 0x3 -+#define MV_5182_A1_REV 0x1 -+#define MV_5180N_B1_REV 0x3 -+#define MV_5181L_A0_ID ((MV_5181_DEV_ID << 16) | MV_5181L_A0_REV) -+ -+ -+ -+/* kw */ -+#define MV_6281_DEV_ID 0x6281 -+#define MV_6192_DEV_ID 0x6192 -+#define MV_6190_DEV_ID 0x6190 -+#define MV_6180_DEV_ID 0x6180 -+ -+#define MV_6281_A0_REV 0x2 -+#define MV_6281_A0_ID ((MV_6281_DEV_ID << 16) | MV_6281_A0_REV) -+#define MV_6281_A0_NAME "88F6281 A0" -+ -+#define MV_6192_A0_REV 0x2 -+#define MV_6192_A0_ID ((MV_6192_DEV_ID << 16) | MV_6192_A0_REV) -+#define MV_6192_A0_NAME "88F6192 A0" -+ -+#define MV_6190_A0_REV 0x2 -+#define MV_6190_A0_ID ((MV_6190_DEV_ID << 16) | MV_6190_A0_REV) -+#define MV_6190_A0_NAME "88F6190 A0" -+ -+#define MV_6180_A0_REV 0x2 -+#define MV_6180_A0_ID ((MV_6180_DEV_ID << 16) | MV_6180_A0_REV) -+#define MV_6180_A0_NAME "88F6180 A0" -+ -+#define MV_6281_A1_REV 0x3 -+#define MV_6281_A1_ID ((MV_6281_DEV_ID << 16) | MV_6281_A1_REV) -+#define MV_6281_A1_NAME "88F6281 A1" -+ -+#define MV_6192_A1_REV 0x3 -+#define MV_6192_A1_ID ((MV_6192_DEV_ID << 16) | MV_6192_A1_REV) -+#define MV_6192_A1_NAME "88F6192 A1" -+ -+#define MV_6190_A1_REV 0x3 -+#define MV_6190_A1_ID ((MV_6190_DEV_ID << 16) | MV_6190_A1_REV) -+#define MV_6190_A1_NAME "88F6190 A1" -+ -+#define MV_6180_A1_REV 0x3 -+#define MV_6180_A1_ID ((MV_6180_DEV_ID << 16) | MV_6180_A1_REV) -+#define MV_6180_A1_NAME "88F6180 A1" -+ -+#define MV_88F6XXX_A0_REV 0x2 -+#define MV_88F6XXX_A1_REV 0x3 -+/* Disco-Duo */ -+#define MV_78XX0_ZY_DEV_ID 0x6381 -+#define MV_78XX0_ZY_NAME "MV78X00" -+ -+#define MV_78XX0_Z0_REV 0x1 -+#define MV_78XX0_Z0_ID ((MV_78XX0_ZY_DEV_ID << 16) | MV_78XX0_Z0_REV) -+#define MV_78XX0_Z0_NAME "78X00 Z0" -+ -+#define MV_78XX0_Y0_REV 0x2 -+#define MV_78XX0_Y0_ID ((MV_78XX0_ZY_DEV_ID << 16) | MV_78XX0_Y0_REV) -+#define MV_78XX0_Y0_NAME "78X00 Y0" -+ -+#define MV_78XX0_DEV_ID 0x7800 -+#define MV_78XX0_NAME "MV78X00" -+ -+#define MV_76100_DEV_ID 0x7610 -+#define MV_78200_DEV_ID 0x7820 -+#define MV_78100_DEV_ID 0x7810 -+#define MV_78XX0_A0_REV 0x1 -+#define MV_78XX0_A1_REV 0x2 -+ -+#define MV_76100_NAME "MV76100" -+#define MV_78100_NAME "MV78100" -+#define MV_78200_NAME "MV78200" -+ -+#define MV_76100_A0_ID ((MV_76100_DEV_ID << 16) | MV_78XX0_A0_REV) -+#define MV_78100_A0_ID ((MV_78100_DEV_ID << 16) | MV_78XX0_A0_REV) -+#define MV_78200_A0_ID ((MV_78200_DEV_ID << 16) | MV_78XX0_A0_REV) -+ -+#define MV_76100_A1_ID ((MV_76100_DEV_ID << 16) | MV_78XX0_A1_REV) -+#define MV_78100_A1_ID ((MV_78100_DEV_ID << 16) | MV_78XX0_A1_REV) -+#define MV_78200_A1_ID ((MV_78200_DEV_ID << 16) | MV_78XX0_A1_REV) -+ -+#define MV_76100_A0_NAME "MV76100 A0" -+#define MV_78100_A0_NAME "MV78100 A0" -+#define MV_78200_A0_NAME "MV78200 A0" -+#define MV_78XX0_A0_NAME "MV78XX0 A0" -+ -+#define MV_76100_A1_NAME "MV76100 A1" -+#define MV_78100_A1_NAME "MV78100 A1" -+#define MV_78200_A1_NAME "MV78200 A1" -+#define MV_78XX0_A1_NAME "MV78XX0 A1" -+ -+/*MV88F632X family*/ -+#define MV_6321_DEV_ID 0x6321 -+#define MV_6322_DEV_ID 0x6322 -+#define MV_6323_DEV_ID 0x6323 -+ -+#define MV_6321_NAME "88F6321" -+#define MV_6322_NAME "88F6322" -+#define MV_6323_NAME "88F6323" -+ -+#define MV_632X_A1_REV 0x2 -+ -+#define MV_6321_A1_ID ((MV_6321_DEV_ID << 16) | MV_632X_A1_REV) -+#define MV_6322_A1_ID ((MV_6322_DEV_ID << 16) | MV_632X_A1_REV) -+#define MV_6323_A1_ID ((MV_6323_DEV_ID << 16) | MV_632X_A1_REV) -+ -+#define MV_6321_A1_NAME "88F6321 A1" -+#define MV_6322_A1_NAME "88F6322 A1" -+#define MV_6323_A1_NAME "88F6323 A1" -+ -+ -+#endif /* __INCmvDeviceIdh */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvHalVer.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvHalVer.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvHalVer.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvHalVer.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,73 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvHalVerh -+#define __INCmvHalVerh -+ -+/* Defines */ -+#define MV_HAL_VERSION "FEROCEON_HAL_3_1_7" -+#define MV_RELEASE_BASELINE "SoCandControllers_FEROCEON_RELEASE_7_9_2009_KW_4_3_4_DD_2_1_4_6183_1_1_4" -+ -+#endif /* __INCmvHalVerh */ -\ No newline at end of file -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvStack.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvStack.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvStack.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvStack.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,100 @@ -+/******************************************************************************* -+* Copyright 2003, Marvell Semiconductor Israel LTD. * -+* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL. * -+* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT * -+* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE * -+* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL. * -+* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED, * -+* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE. * -+* * -+* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, * -+* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL * -+* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K. * -+* (MJKK), MARVELL SEMICONDUCTOR ISRAEL LTD (MSIL). * -+******************************************************************************** -+* mvQueue.c -+* -+* FILENAME: $Workfile: mvStack.c $ -+* REVISION: $Revision: 1.1 $ -+* LAST UPDATE: $Modtime: $ -+* -+* DESCRIPTION: -+* This file implements simple Stack LIFO functionality. -+*******************************************************************************/ -+ -+/* includes */ -+#include "mvOs.h" -+#include "mvTypes.h" -+#include "mvDebug.h" -+#include "mvStack.h" -+ -+/* defines */ -+ -+ -+/* Public functions */ -+ -+ -+/* Purpose: Create new stack -+ * Inputs: -+ * - MV_U32 noOfElements - maximum number of elements in the stack. -+ * Each element 4 bytes size -+ * Return: void* - pointer to created stack. -+ */ -+void* mvStackCreate(int numOfElements) -+{ -+ MV_STACK* pStack; -+ MV_U32* pStackElements; -+ -+ pStack = (MV_STACK*)mvOsMalloc(sizeof(MV_STACK)); -+ pStackElements = (MV_U32*)mvOsMalloc(numOfElements*sizeof(MV_U32)); -+ if( (pStack == NULL) || (pStackElements == NULL) ) -+ { -+ mvOsPrintf("mvStack: Can't create new stack\n"); -+ return NULL; -+ } -+ memset(pStackElements, 0, numOfElements*sizeof(MV_U32)); -+ pStack->numOfElements = numOfElements; -+ pStack->stackIdx = 0; -+ pStack->stackElements = pStackElements; -+ -+ return pStack; -+} -+ -+/* Purpose: Delete existing stack -+ * Inputs: -+ * - void* stackHndl - Stack handle as returned by "mvStackCreate()" function -+ * -+ * Return: MV_STATUS MV_NOT_FOUND - Failure. StackHandle is not valid. -+ * MV_OK - Success. -+ */ -+MV_STATUS mvStackDelete(void* stackHndl) -+{ -+ MV_STACK* pStack = (MV_STACK*)stackHndl; -+ -+ if( (pStack == NULL) || (pStack->stackElements == NULL) ) -+ return MV_NOT_FOUND; -+ -+ mvOsFree(pStack->stackElements); -+ mvOsFree(pStack); -+ -+ return MV_OK; -+} -+ -+ -+/* PrintOut status of the stack */ -+void mvStackStatus(void* stackHndl, MV_BOOL isPrintElements) -+{ -+ int i; -+ MV_STACK* pStack = (MV_STACK*)stackHndl; -+ -+ mvOsPrintf("StackHandle=%p, pElements=%p, numElements=%d, stackIdx=%d\n", -+ stackHndl, pStack->stackElements, pStack->numOfElements, -+ pStack->stackIdx); -+ if(isPrintElements == MV_TRUE) -+ { -+ for(i=0; istackIdx; i++) -+ { -+ mvOsPrintf("%3d. Value=0x%x\n", i, pStack->stackElements[i]); -+ } -+ } -+} -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvStack.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvStack.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvStack.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvStack.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,140 @@ -+/******************************************************************************* -+* Copyright 2003, Marvell Semiconductor Israel LTD. * -+* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL. * -+* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT * -+* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE * -+* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL. * -+* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED, * -+* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE. * -+* * -+* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, * -+* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL * -+* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K. * -+* (MJKK), MARVELL SEMICONDUCTOR ISRAEL LTD (MSIL). * -+******************************************************************************** -+* mvStack.h - Header File for : -+* -+* FILENAME: $Workfile: mvStack.h $ -+* REVISION: $Revision: 1.1 $ -+* LAST UPDATE: $Modtime: $ -+* -+* DESCRIPTION: -+* This file defines simple Stack (LIFO) functionality. -+* -+*******************************************************************************/ -+ -+#ifndef __mvStack_h__ -+#define __mvStack_h__ -+ -+ -+/* includes */ -+#include "mvTypes.h" -+ -+ -+/* defines */ -+ -+ -+/* typedefs */ -+/* Data structure describes general purpose Stack */ -+typedef struct -+{ -+ int stackIdx; -+ int numOfElements; -+ MV_U32* stackElements; -+} MV_STACK; -+ -+static INLINE MV_BOOL mvStackIsFull(void* stackHndl) -+{ -+ MV_STACK* pStack = (MV_STACK*)stackHndl; -+ -+ if(pStack->stackIdx == pStack->numOfElements) -+ return MV_TRUE; -+ -+ return MV_FALSE; -+} -+ -+static INLINE MV_BOOL mvStackIsEmpty(void* stackHndl) -+{ -+ MV_STACK* pStack = (MV_STACK*)stackHndl; -+ -+ if(pStack->stackIdx == 0) -+ return MV_TRUE; -+ -+ return MV_FALSE; -+} -+/* Purpose: Push new element to stack -+ * Inputs: -+ * - void* stackHndl - Stack handle as returned by "mvStackCreate()" function. -+ * - MV_U32 value - New element. -+ * -+ * Return: MV_STATUS MV_FULL - Failure. Stack is full. -+ * MV_OK - Success. Element is put to stack. -+ */ -+static INLINE void mvStackPush(void* stackHndl, MV_U32 value) -+{ -+ MV_STACK* pStack = (MV_STACK*)stackHndl; -+ -+#ifdef MV_RT_DEBUG -+ if(pStack->stackIdx == pStack->numOfElements) -+ { -+ mvOsPrintf("mvStackPush: Stack is FULL\n"); -+ return; -+ } -+#endif /* MV_RT_DEBUG */ -+ -+ pStack->stackElements[pStack->stackIdx] = value; -+ pStack->stackIdx++; -+} -+ -+/* Purpose: Pop element from the top of stack and copy it to "pValue" -+ * Inputs: -+ * - void* stackHndl - Stack handle as returned by "mvStackCreate()" function. -+ * - MV_U32 value - Element in the top of stack. -+ * -+ * Return: MV_STATUS MV_EMPTY - Failure. Stack is empty. -+ * MV_OK - Success. Element is removed from the stack and -+ * copied to pValue argument -+ */ -+static INLINE MV_U32 mvStackPop(void* stackHndl) -+{ -+ MV_STACK* pStack = (MV_STACK*)stackHndl; -+ -+#ifdef MV_RT_DEBUG -+ if(pStack->stackIdx == 0) -+ { -+ mvOsPrintf("mvStackPop: Stack is EMPTY\n"); -+ return 0; -+ } -+#endif /* MV_RT_DEBUG */ -+ -+ pStack->stackIdx--; -+ return pStack->stackElements[pStack->stackIdx]; -+} -+ -+static INLINE int mvStackIndex(void* stackHndl) -+{ -+ MV_STACK* pStack = (MV_STACK*)stackHndl; -+ -+ return pStack->stackIdx; -+} -+ -+static INLINE int mvStackFreeElements(void* stackHndl) -+{ -+ MV_STACK* pStack = (MV_STACK*)stackHndl; -+ -+ return (pStack->numOfElements - pStack->stackIdx); -+} -+ -+/* mvStack.h API list */ -+ -+/* Create new Stack */ -+void* mvStackCreate(int numOfElements); -+ -+/* Delete existing stack */ -+MV_STATUS mvStackDelete(void* stackHndl); -+ -+/* Print status of the stack */ -+void mvStackStatus(void* stackHndl, MV_BOOL isPrintElements); -+ -+#endif /* __mvStack_h__ */ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvTypes.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvTypes.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvTypes.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvTypes.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,245 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvTypesh -+#define __INCmvTypesh -+ -+/* Defines */ -+ -+/* The following is a list of Marvell status */ -+#define MV_ERROR (-1) -+#define MV_OK (0x00) /* Operation succeeded */ -+#define MV_FAIL (0x01) /* Operation failed */ -+#define MV_BAD_VALUE (0x02) /* Illegal value (general) */ -+#define MV_OUT_OF_RANGE (0x03) /* The value is out of range */ -+#define MV_BAD_PARAM (0x04) /* Illegal parameter in function called */ -+#define MV_BAD_PTR (0x05) /* Illegal pointer value */ -+#define MV_BAD_SIZE (0x06) /* Illegal size */ -+#define MV_BAD_STATE (0x07) /* Illegal state of state machine */ -+#define MV_SET_ERROR (0x08) /* Set operation failed */ -+#define MV_GET_ERROR (0x09) /* Get operation failed */ -+#define MV_CREATE_ERROR (0x0A) /* Fail while creating an item */ -+#define MV_NOT_FOUND (0x0B) /* Item not found */ -+#define MV_NO_MORE (0x0C) /* No more items found */ -+#define MV_NO_SUCH (0x0D) /* No such item */ -+#define MV_TIMEOUT (0x0E) /* Time Out */ -+#define MV_NO_CHANGE (0x0F) /* Parameter(s) is already in this value */ -+#define MV_NOT_SUPPORTED (0x10) /* This request is not support */ -+#define MV_NOT_IMPLEMENTED (0x11) /* Request supported but not implemented */ -+#define MV_NOT_INITIALIZED (0x12) /* The item is not initialized */ -+#define MV_NO_RESOURCE (0x13) /* Resource not available (memory ...) */ -+#define MV_FULL (0x14) /* Item is full (Queue or table etc...) */ -+#define MV_EMPTY (0x15) /* Item is empty (Queue or table etc...) */ -+#define MV_INIT_ERROR (0x16) /* Error occured while INIT process */ -+#define MV_HW_ERROR (0x17) /* Hardware error */ -+#define MV_TX_ERROR (0x18) /* Transmit operation not succeeded */ -+#define MV_RX_ERROR (0x19) /* Recieve operation not succeeded */ -+#define MV_NOT_READY (0x1A) /* The other side is not ready yet */ -+#define MV_ALREADY_EXIST (0x1B) /* Tried to create existing item */ -+#define MV_OUT_OF_CPU_MEM (0x1C) /* Cpu memory allocation failed. */ -+#define MV_NOT_STARTED (0x1D) /* Not started yet */ -+#define MV_BUSY (0x1E) /* Item is busy. */ -+#define MV_TERMINATE (0x1F) /* Item terminates it's work. */ -+#define MV_NOT_ALIGNED (0x20) /* Wrong alignment */ -+#define MV_NOT_ALLOWED (0x21) /* Operation NOT allowed */ -+#define MV_WRITE_PROTECT (0x22) /* Write protected */ -+ -+ -+#define MV_INVALID (int)(-1) -+ -+#define MV_FALSE 0 -+#define MV_TRUE (!(MV_FALSE)) -+ -+ -+#ifndef NULL -+#define NULL ((void*)0) -+#endif -+ -+ -+#ifndef MV_ASMLANGUAGE -+/* typedefs */ -+ -+typedef char MV_8; -+typedef unsigned char MV_U8; -+ -+typedef int MV_32; -+typedef unsigned int MV_U32; -+ -+typedef short MV_16; -+typedef unsigned short MV_U16; -+ -+#ifdef MV_PPC64 -+typedef long MV_64; -+typedef unsigned long MV_U64; -+#else -+typedef long long MV_64; -+typedef unsigned long long MV_U64; -+#endif -+ -+typedef long MV_LONG; /* 32/64 */ -+typedef unsigned long MV_ULONG; /* 32/64 */ -+ -+typedef int MV_STATUS; -+typedef int MV_BOOL; -+typedef void MV_VOID; -+typedef float MV_FLOAT; -+ -+typedef int (*MV_FUNCPTR) (void); /* ptr to function returning int */ -+typedef void (*MV_VOIDFUNCPTR) (void); /* ptr to function returning void */ -+typedef double (*MV_DBLFUNCPTR) (void); /* ptr to function returning double*/ -+typedef float (*MV_FLTFUNCPTR) (void); /* ptr to function returning float */ -+ -+typedef MV_U32 MV_KHZ; -+typedef MV_U32 MV_MHZ; -+typedef MV_U32 MV_HZ; -+ -+ -+/* This enumerator describes the set of commands that can be applied on */ -+/* an engine (e.g. IDMA, XOR). Appling a comman depends on the current */ -+/* status (see MV_STATE enumerator) */ -+/* Start can be applied only when status is IDLE */ -+/* Stop can be applied only when status is IDLE, ACTIVE or PAUSED */ -+/* Pause can be applied only when status is ACTIVE */ -+/* Restart can be applied only when status is PAUSED */ -+typedef enum _mvCommand -+{ -+ MV_START, /* Start */ -+ MV_STOP, /* Stop */ -+ MV_PAUSE, /* Pause */ -+ MV_RESTART /* Restart */ -+} MV_COMMAND; -+ -+/* This enumerator describes the set of state conditions. */ -+/* Moving from one state to other is stricted. */ -+typedef enum _mvState -+{ -+ MV_IDLE, -+ MV_ACTIVE, -+ MV_PAUSED, -+ MV_UNDEFINED_STATE -+} MV_STATE; -+ -+ -+/* This structure describes address space window. Window base can be */ -+/* 64 bit, window size up to 4GB */ -+typedef struct _mvAddrWin -+{ -+ MV_U32 baseLow; /* 32bit base low */ -+ MV_U32 baseHigh; /* 32bit base high */ -+ MV_U32 size; /* 32bit size */ -+}MV_ADDR_WIN; -+ -+/* This binary enumerator describes protection attribute status */ -+typedef enum _mvProtRight -+{ -+ ALLOWED, /* Protection attribute allowed */ -+ FORBIDDEN /* Protection attribute forbidden */ -+}MV_PROT_RIGHT; -+ -+/* Unified struct for Rx and Tx packet operations. The user is required to */ -+/* be familier only with Tx/Rx descriptor command status. */ -+typedef struct _bufInfo -+{ -+ MV_U32 cmdSts; /* Tx/Rx command status */ -+ MV_U16 byteCnt; /* Size of valid data in the buffer */ -+ MV_U16 bufSize; /* Total size of the buffer */ -+ MV_U8 *pBuff; /* Pointer to Buffer */ -+ MV_U8 *pData; /* Pointer to data in the Buffer */ -+ MV_U32 userInfo1; /* Tx/Rx attached user information 1 */ -+ MV_U32 userInfo2; /* Tx/Rx attached user information 2 */ -+ struct _bufInfo *pNextBufInfo; /* Next buffer in packet */ -+} BUF_INFO; -+ -+/* This structure contains information describing one of buffers -+ * (fragments) they are built Ethernet packet. -+ */ -+typedef struct -+{ -+ MV_U8* bufVirtPtr; -+ MV_ULONG bufPhysAddr; -+ MV_U32 bufSize; -+ MV_U32 dataSize; -+ MV_U32 memHandle; -+ MV_32 bufAddrShift; -+} MV_BUF_INFO; -+ -+/* This structure contains information describing Ethernet packet. -+ * The packet can be divided for few buffers (fragments) -+ */ -+typedef struct -+{ -+ MV_ULONG osInfo; -+ MV_BUF_INFO *pFrags; -+ MV_U32 status; -+ MV_U16 pktSize; -+ MV_U16 numFrags; -+ MV_U32 ownerId; -+ MV_U32 fragIP; -+} MV_PKT_INFO; -+ -+#endif /* MV_ASMLANGUAGE */ -+ -+#endif /* __INCmvTypesh */ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/dbg-trace.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/dbg-trace.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/dbg-trace.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/dbg-trace.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,110 @@ -+#include -+#include -+#include -+#include "dbg-trace.h" -+ -+#define TRACE_ARR_LEN 800 -+#define STR_LEN 128 -+struct trace { -+ struct timeval tv; -+ char str[STR_LEN]; -+ unsigned int callback_val1; -+ unsigned int callback_val2; -+ char valid; -+}; -+static unsigned int (*trc_callback1) (unsigned char) = NULL; -+static unsigned int (*trc_callback2) (unsigned char) = NULL; -+static unsigned char trc_param1 = 0; -+static unsigned char trc_param2 = 0; -+struct trace *trc_arr; -+static int trc_index; -+static int trc_active = 0; -+ -+void TRC_START() -+{ -+ trc_active = 1; -+} -+ -+void TRC_STOP() -+{ -+ trc_active = 0; -+} -+ -+void TRC_INIT(void *callback1, void *callback2, unsigned char callback1_param, unsigned char callback2_param) -+{ -+ printk("Marvell debug tracing is on\n"); -+ trc_arr = (struct trace *)kmalloc(TRACE_ARR_LEN*sizeof(struct trace),GFP_KERNEL); -+ if(trc_arr == NULL) -+ { -+ printk("Can't allocate Debug Trace buffer\n"); -+ return; -+ } -+ memset(trc_arr,0,TRACE_ARR_LEN*sizeof(struct trace)); -+ trc_index = 0; -+ trc_callback1 = callback1; -+ trc_callback2 = callback2; -+ trc_param1 = callback1_param; -+ trc_param2 = callback2_param; -+} -+void TRC_REC(char *fmt,...) -+{ -+ va_list args; -+ struct trace *trc = &trc_arr[trc_index]; -+ -+ if(trc_active == 0) -+ return; -+ -+ do_gettimeofday(&trc->tv); -+ if(trc_callback1) -+ trc->callback_val1 = trc_callback1(trc_param1); -+ if(trc_callback2) -+ trc->callback_val2 = trc_callback2(trc_param2); -+ va_start(args, fmt); -+ vsprintf(trc->str,fmt,args); -+ va_end(args); -+ trc->valid = 1; -+ if((++trc_index) == TRACE_ARR_LEN) { -+ trc_index = 0; -+ } -+} -+void TRC_OUTPUT(void) -+{ -+ int i,j; -+ struct trace *p; -+ printk("\n\nTrace %d items\n",TRACE_ARR_LEN); -+ for(i=0,j=trc_index; ivalid) { -+ unsigned long uoffs; -+ struct trace *plast; -+ if(p == &trc_arr[0]) -+ plast = &trc_arr[TRACE_ARR_LEN-1]; -+ else -+ plast = p-1; -+ if(p->tv.tv_sec == ((plast)->tv.tv_sec)) -+ uoffs = (p->tv.tv_usec - ((plast)->tv.tv_usec)); -+ else -+ uoffs = (1000000 - ((plast)->tv.tv_usec)) + -+ ((p->tv.tv_sec - ((plast)->tv.tv_sec) - 1) * 1000000) + -+ p->tv.tv_usec; -+ printk("%03d: [+%ld usec]", j, (unsigned long)uoffs); -+ if(trc_callback1) -+ printk("[%u]",p->callback_val1); -+ if(trc_callback2) -+ printk("[%u]",p->callback_val2); -+ printk(": %s",p->str); -+ } -+ p->valid = 0; -+ } -+ memset(trc_arr,0,TRACE_ARR_LEN*sizeof(struct trace)); -+ trc_index = 0; -+} -+void TRC_RELEASE(void) -+{ -+ kfree(trc_arr); -+ trc_index = 0; -+} -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/dbg-trace.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/dbg-trace.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/dbg-trace.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/dbg-trace.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,24 @@ -+ -+#ifndef _MV_DBG_TRCE_H_ -+#define _MV_DBG_TRCE_H_ -+ -+#ifdef CONFIG_MV_DBG_TRACE -+void TRC_INIT(void *callback1, void *callback2, -+ unsigned char callback1_param, unsigned char callback2_param); -+void TRC_REC(char *fmt,...); -+void TRC_OUTPUT(void); -+void TRC_RELEASE(void); -+void TRC_START(void); -+void TRC_STOP(void); -+ -+#else -+#define TRC_INIT(x1,x2,x3,x4) -+#define TRC_REC(X...) -+#define TRC_OUTPUT() -+#define TRC_RELEASE() -+#define TRC_START() -+#define TRC_STOP() -+#endif -+ -+ -+#endif -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,2513 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "boardEnv/mvBoardEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+#include "cpu/mvCpu.h" -+#include "cntmr/mvCntmr.h" -+#include "gpp/mvGpp.h" -+#include "twsi/mvTwsi.h" -+#include "pex/mvPex.h" -+#include "device/mvDevice.h" -+#include "eth/gbe/mvEthRegs.h" -+ -+/* defines */ -+/* #define MV_DEBUG */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+extern MV_CPU_ARM_CLK _cpuARMDDRCLK[]; -+ -+#define CODE_IN_ROM MV_FALSE -+#define CODE_IN_RAM MV_TRUE -+ -+extern MV_BOARD_INFO* boardInfoTbl[]; -+#define BOARD_INFO(boardId) boardInfoTbl[boardId - BOARD_ID_BASE] -+ -+/* Locals */ -+static MV_DEV_CS_INFO* boardGetDevEntry(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); -+ -+MV_U32 tClkRate = -1; -+ -+ -+/******************************************************************************* -+* mvBoardEnvInit - Init board -+* -+* DESCRIPTION: -+* In this function the board environment take care of device bank -+* initialization. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvBoardEnvInit(MV_VOID) -+{ -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardEnvInit:Board unknown.\n"); -+ return; -+ -+ } -+ -+ /* Set GPP Out value */ -+ MV_REG_WRITE(GPP_DATA_OUT_REG(0), BOARD_INFO(boardId)->gppOutValLow); -+ MV_REG_WRITE(GPP_DATA_OUT_REG(1), BOARD_INFO(boardId)->gppOutValHigh); -+ -+ /* set GPP polarity */ -+ mvGppPolaritySet(0, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValLow); -+ mvGppPolaritySet(1, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValHigh); -+ -+ /* Workaround for Erratum FE-MISC-70*/ -+ if(mvCtrlRevGet()==MV_88F6XXX_A0_REV) -+ { -+ BOARD_INFO(boardId)->gppOutEnValLow &= 0xfffffffd; -+ BOARD_INFO(boardId)->gppOutEnValLow |= (BOARD_INFO(boardId)->gppOutEnValHigh) & 0x00000002; -+ } /*End of WA*/ -+ -+ /* Set GPP Out Enable*/ -+ mvGppTypeSet(0, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValLow); -+ mvGppTypeSet(1, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValHigh); -+ -+ /* Nand CE */ -+ MV_REG_BIT_SET(NAND_CTRL_REG, NAND_ACTCEBOOT_BIT); -+} -+ -+/******************************************************************************* -+* mvBoardModelGet - Get Board model -+* -+* DESCRIPTION: -+* This function returns 16bit describing board model. -+* Board model is constructed of one byte major and minor numbers in the -+* following manner: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* String describing board model. -+* -+*******************************************************************************/ -+MV_U16 mvBoardModelGet(MV_VOID) -+{ -+ return (mvBoardIdGet() >> 16); -+} -+ -+/******************************************************************************* -+* mbBoardRevlGet - Get Board revision -+* -+* DESCRIPTION: -+* This function returns a 32bit describing the board revision. -+* Board revision is constructed of 4bytes. 2bytes describes major number -+* and the other 2bytes describes minor munber. -+* For example for board revision 3.4 the function will return -+* 0x00030004. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* String describing board model. -+* -+*******************************************************************************/ -+MV_U16 mvBoardRevGet(MV_VOID) -+{ -+ return (mvBoardIdGet() & 0xFFFF); -+} -+ -+/******************************************************************************* -+* mvBoardNameGet - Get Board name -+* -+* DESCRIPTION: -+* This function returns a string describing the board model and revision. -+* String is extracted from board I2C EEPROM. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* pNameBuff - Buffer to contain board name string. Minimum size 32 chars. -+* -+* RETURN: -+* -+* MV_ERROR if informantion can not be read. -+*******************************************************************************/ -+MV_STATUS mvBoardNameGet(char *pNameBuff) -+{ -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsSPrintf (pNameBuff, "Board unknown.\n"); -+ return MV_ERROR; -+ -+ } -+ -+ mvOsSPrintf (pNameBuff, "%s",BOARD_INFO(boardId)->boardName); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvBoardIsPortInSgmii - -+* -+* DESCRIPTION: -+* This routine returns MV_TRUE for port number works in SGMII or MV_FALSE -+* For all other options. -+* -+* INPUT: -+* ethPortNum - Ethernet port number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE - port in SGMII. -+* MV_FALSE - other. -+* -+*******************************************************************************/ -+MV_BOOL mvBoardIsPortInSgmii(MV_U32 ethPortNum) -+{ -+ MV_BOOL ethPortSgmiiSupport[BOARD_ETH_PORT_NUM] = MV_ETH_PORT_SGMII; -+ -+ if(ethPortNum >= BOARD_ETH_PORT_NUM) -+ { -+ mvOsPrintf ("Invalid portNo=%d\n", ethPortNum); -+ return MV_FALSE; -+ } -+ return ethPortSgmiiSupport[ethPortNum]; -+} -+ -+/******************************************************************************* -+* mvBoardIsPortInGmii - -+* -+* DESCRIPTION: -+* This routine returns MV_TRUE for port number works in GMII or MV_FALSE -+* For all other options. -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE - port in GMII. -+* MV_FALSE - other. -+* -+*******************************************************************************/ -+MV_BOOL mvBoardIsPortInGmii(MV_VOID) -+{ -+ MV_U32 devClassId, devClass = 0; -+ if (mvBoardMppGroupTypeGet(devClass) == MV_BOARD_AUTO) -+ { -+ /* Get MPP module ID */ -+ devClassId = mvBoarModuleTypeGet(devClass); -+ if (MV_BOARD_MODULE_GMII_ID == devClassId) -+ return MV_TRUE; -+ } -+ else if (mvBoardMppGroupTypeGet(devClass) == MV_BOARD_GMII) -+ return MV_TRUE; -+ -+ return MV_FALSE; -+} -+/******************************************************************************* -+* mvBoardPhyAddrGet - Get the phy address -+* -+* DESCRIPTION: -+* This routine returns the Phy address of a given ethernet port. -+* -+* INPUT: -+* ethPortNum - Ethernet port number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit describing Phy address, -1 if the port number is wrong. -+* -+*******************************************************************************/ -+MV_32 mvBoardPhyAddrGet(MV_U32 ethPortNum) -+{ -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardPhyAddrGet: Board unknown.\n"); -+ return MV_ERROR; -+ } -+ -+ return BOARD_INFO(boardId)->pBoardMacInfo[ethPortNum].boardEthSmiAddr; -+} -+ -+/******************************************************************************* -+* mvBoardMacSpeedGet - Get the Mac speed -+* -+* DESCRIPTION: -+* This routine returns the Mac speed if pre define of a given ethernet port. -+* -+* INPUT: -+* ethPortNum - Ethernet port number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BOARD_MAC_SPEED, -1 if the port number is wrong. -+* -+*******************************************************************************/ -+MV_BOARD_MAC_SPEED mvBoardMacSpeedGet(MV_U32 ethPortNum) -+{ -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardMacSpeedGet: Board unknown.\n"); -+ return MV_ERROR; -+ } -+ -+ return BOARD_INFO(boardId)->pBoardMacInfo[ethPortNum].boardMacSpeed; -+} -+ -+/******************************************************************************* -+* mvBoardLinkStatusIrqGet - Get the IRQ number for the link status indication -+* -+* DESCRIPTION: -+* This routine returns the IRQ number for the link status indication. -+* -+* INPUT: -+* ethPortNum - Ethernet port number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* the number of the IRQ for the link status indication, -1 if the port -+* number is wrong or if not relevant. -+* -+*******************************************************************************/ -+MV_32 mvBoardLinkStatusIrqGet(MV_U32 ethPortNum) -+{ -+ MV_U32 boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardLinkStatusIrqGet: Board unknown.\n"); -+ return MV_ERROR; -+ } -+ -+ return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].linkStatusIrq; -+} -+ -+/******************************************************************************* -+* mvBoardSwitchPortGet - Get the mapping between the board connector and the -+* Ethernet Switch port -+* -+* DESCRIPTION: -+* This routine returns the matching Switch port. -+* -+* INPUT: -+* ethPortNum - Ethernet port number. -+* boardPortNum - logical number of the connector on the board -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* the matching Switch port, -1 if the port number is wrong or if not relevant. -+* -+*******************************************************************************/ -+MV_32 mvBoardSwitchPortGet(MV_U32 ethPortNum, MV_U8 boardPortNum) -+{ -+ MV_U32 boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardSwitchPortGet: Board unknown.\n"); -+ return MV_ERROR; -+ } -+ if (boardPortNum >= BOARD_ETH_SWITCH_PORT_NUM) -+ { -+ mvOsPrintf("mvBoardSwitchPortGet: Illegal board port number.\n"); -+ return MV_ERROR; -+ } -+ -+ return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].qdPort[boardPortNum]; -+} -+ -+/******************************************************************************* -+* mvBoardSwitchCpuPortGet - Get the the Ethernet Switch CPU port -+* -+* DESCRIPTION: -+* This routine returns the Switch CPU port. -+* -+* INPUT: -+* ethPortNum - Ethernet port number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* the Switch CPU port, -1 if the port number is wrong or if not relevant. -+* -+*******************************************************************************/ -+MV_32 mvBoardSwitchCpuPortGet(MV_U32 ethPortNum) -+{ -+ MV_U32 boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardSwitchCpuPortGet: Board unknown.\n"); -+ return MV_ERROR; -+ } -+ -+ return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].qdCpuPort; -+} -+ -+/******************************************************************************* -+* mvBoardIsSwitchConnected - Get switch connection status -+* DESCRIPTION: -+* This routine returns port's connection status -+* -+* INPUT: -+* ethPortNum - Ethernet port number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 1 - if ethPortNum is connected to switch, 0 otherwise -+* -+*******************************************************************************/ -+MV_32 mvBoardIsSwitchConnected(MV_U32 ethPortNum) -+{ -+ MV_U32 boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardIsSwitchConnected: Board unknown.\n"); -+ return MV_ERROR; -+ } -+ -+ if(ethPortNum >= BOARD_INFO(boardId)->numBoardMacInfo) -+ { -+ mvOsPrintf("mvBoardIsSwitchConnected: Illegal port number(%u)\n", ethPortNum); -+ return MV_ERROR; -+ } -+ -+ if((MV_32)(BOARD_INFO(boardId)->pSwitchInfo)) -+ return (MV_32)(BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].switchOnPort == ethPortNum); -+ else -+ return 0; -+} -+/******************************************************************************* -+* mvBoardSmiScanModeGet - Get Switch SMI scan mode -+* -+* DESCRIPTION: -+* This routine returns Switch SMI scan mode. -+* -+* INPUT: -+* ethPortNum - Ethernet port number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 1 for SMI_MANUAL_MODE, -1 if the port number is wrong or if not relevant. -+* -+*******************************************************************************/ -+MV_32 mvBoardSmiScanModeGet(MV_U32 ethPortNum) -+{ -+ MV_U32 boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardSmiScanModeGet: Board unknown.\n"); -+ return MV_ERROR; -+ } -+ -+ return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].smiScanMode; -+} -+/******************************************************************************* -+* mvBoardSpecInitGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: Return MV_TRUE and parameters in case board need spesific phy init, -+* otherwise return MV_FALSE. -+* -+* -+*******************************************************************************/ -+ -+MV_BOOL mvBoardSpecInitGet(MV_U32* regOff, MV_U32* data) -+{ -+ return MV_FALSE; -+} -+ -+/******************************************************************************* -+* mvBoardTclkGet - Get the board Tclk (Controller clock) -+* -+* DESCRIPTION: -+* This routine extract the controller core clock. -+* This function uses the controller counters to make identification. -+* Note: In order to avoid interference, make sure task context switch -+* and interrupts will not occure during this function operation -+* -+* INPUT: -+* countNum - Counter number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit clock cycles in Hertz. -+* -+*******************************************************************************/ -+MV_U32 mvBoardTclkGet(MV_VOID) -+{ -+ if(mvCtrlModelGet()==MV_6281_DEV_ID) -+ { -+#if defined(TCLK_AUTO_DETECT) -+ MV_U32 tmpTClkRate = MV_BOARD_TCLK_166MHZ; -+ -+ tmpTClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ tmpTClkRate &= MSAR_TCLCK_MASK; -+ -+ switch (tmpTClkRate) -+ { -+ case MSAR_TCLCK_166: -+ return MV_BOARD_TCLK_166MHZ; -+ break; -+ case MSAR_TCLCK_200: -+ return MV_BOARD_TCLK_200MHZ; -+ break; -+ } -+#else -+ return MV_BOARD_TCLK_200MHZ; -+#endif -+ } -+ -+ return MV_BOARD_TCLK_166MHZ; -+ -+} -+/******************************************************************************* -+* mvBoardSysClkGet - Get the board SysClk (CPU bus clock) -+* -+* DESCRIPTION: -+* This routine extract the CPU bus clock. -+* -+* INPUT: -+* countNum - Counter number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit clock cycles in Hertz. -+* -+*******************************************************************************/ -+static MV_U32 mvBoard6180SysClkGet(MV_VOID) -+{ -+ MV_U32 sysClkRate=0; -+ MV_CPU_ARM_CLK _cpu6180_ddr_l2_CLK[] = MV_CPU6180_DDR_L2_CLCK_TBL; -+ -+ sysClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ sysClkRate = sysClkRate & MSAR_CPUCLCK_MASK_6180; -+ sysClkRate = sysClkRate >> MSAR_CPUCLCK_OFFS_6180; -+ -+ sysClkRate = _cpu6180_ddr_l2_CLK[sysClkRate].ddrClk; -+ -+ return sysClkRate; -+ -+} -+ -+MV_U32 mvBoardSysClkGet(MV_VOID) -+{ -+#ifdef SYSCLK_AUTO_DETECT -+ MV_U32 sysClkRate, tmp, pClkRate, indexDdrRtio; -+ MV_U32 cpuCLK[] = MV_CPU_CLCK_TBL; -+ MV_U32 ddrRtio[][2] = MV_DDR_CLCK_RTIO_TBL; -+ -+ if(mvCtrlModelGet() == MV_6180_DEV_ID) -+ return mvBoard6180SysClkGet(); -+ -+ tmp = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ pClkRate = MSAR_CPUCLCK_EXTRACT(tmp); -+ pClkRate = cpuCLK[pClkRate]; -+ -+ indexDdrRtio = tmp & MSAR_DDRCLCK_RTIO_MASK; -+ indexDdrRtio = indexDdrRtio >> MSAR_DDRCLCK_RTIO_OFFS; -+ if(ddrRtio[indexDdrRtio][0] != 0) -+ sysClkRate = ((pClkRate * ddrRtio[indexDdrRtio][1]) / ddrRtio[indexDdrRtio][0]); -+ else -+ sysClkRate = 0; -+ return sysClkRate; -+#else -+ return MV_BOARD_DEFAULT_SYSCLK; -+#endif -+} -+ -+ -+/******************************************************************************* -+* mvBoardPexBridgeIntPinGet - Get PEX to PCI bridge interrupt pin number -+* -+* DESCRIPTION: -+* Multi-ported PCI Express bridges that is implemented on the board -+* collapse interrupts across multiple conventional PCI/PCI-X buses. -+* A dual-headed PCI Express bridge would map (or "swizzle") the -+* interrupts per the following table (in accordance with the respective -+* logical PCI/PCI-X bridge's Device Number), collapse the INTA#-INTD# -+* signals from its two logical PCI/PCI-X bridges, collapse the -+* INTA#-INTD# signals from any internal sources, and convert the -+* signals to in-band PCI Express messages. 10 -+* This function returns the upstream interrupt as it was converted by -+* the bridge, according to board configuration and the following table: -+* PCI dev num -+* Interrupt pin 7, 8, 9 -+* A -> A D C -+* B -> B A D -+* C -> C B A -+* D -> D C B -+* -+* -+* INPUT: -+* devNum - PCI/PCIX device number. -+* intPin - PCI Int pin -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Int pin connected to the Interrupt controller -+* -+*******************************************************************************/ -+MV_U32 mvBoardPexBridgeIntPinGet(MV_U32 devNum, MV_U32 intPin) -+{ -+ MV_U32 realIntPin = ((intPin + (3 - (devNum % 4))) %4 ); -+ -+ if (realIntPin == 0) return 4; -+ else return realIntPin; -+ -+} -+ -+/******************************************************************************* -+* mvBoardDebugLedNumGet - Get number of debug Leds -+* -+* DESCRIPTION: -+* INPUT: -+* boardId -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_U32 mvBoardDebugLedNumGet(MV_U32 boardId) -+{ -+ return BOARD_INFO(boardId)->activeLedsNumber; -+} -+ -+/******************************************************************************* -+* mvBoardDebugLeg - Set the board debug Leds -+* -+* DESCRIPTION: turn on/off status leds. -+* Note: assume MPP leds are part of group 0 only. -+* -+* INPUT: -+* hexNum - Number to be displied in hex by Leds. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvBoardDebugLed(MV_U32 hexNum) -+{ -+ MV_U32 val = 0,totalMask, currentBitMask = 1,i; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (BOARD_INFO(boardId)->pLedGppPin == NULL) -+ return; -+ -+ totalMask = (1 << BOARD_INFO(boardId)->activeLedsNumber) -1; -+ hexNum &= totalMask; -+ totalMask = 0; -+ -+ for (i = 0 ; i < BOARD_INFO(boardId)->activeLedsNumber ; i++) -+ { -+ if (hexNum & currentBitMask) -+ { -+ val |= (1 << BOARD_INFO(boardId)->pLedGppPin[i]); -+ } -+ -+ totalMask |= (1 << BOARD_INFO(boardId)->pLedGppPin[i]); -+ -+ currentBitMask = (currentBitMask << 1); -+ } -+ -+ if (BOARD_INFO(boardId)->ledsPolarity) -+ { -+ mvGppValueSet(0, totalMask, val); -+ } -+ else -+ { -+ mvGppValueSet(0, totalMask, ~val); -+ } -+} -+ -+ -+/******************************************************************************* -+* mvBoarGpioPinGet - mvBoarGpioPinGet -+* -+* DESCRIPTION: -+* -+* INPUT: -+* class - MV_BOARD_GPP_CLASS enum. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* GPIO pin number. The function return -1 for bad parameters. -+* -+*******************************************************************************/ -+MV_32 mvBoarGpioPinNumGet(MV_BOARD_GPP_CLASS class, MV_U32 index) -+{ -+ MV_U32 boardId, i; -+ MV_U32 indexFound = 0; -+ -+ boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardRTCGpioPinGet:Board unknown.\n"); -+ return MV_ERROR; -+ -+ } -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardGppInfo; i++) -+ if (BOARD_INFO(boardId)->pBoardGppInfo[i].devClass == class) { -+ if (indexFound == index) -+ return (MV_U32)BOARD_INFO(boardId)->pBoardGppInfo[i].gppPinNum; -+ else -+ indexFound++; -+ -+ } -+ -+ return MV_ERROR; -+} -+ -+ -+/******************************************************************************* -+* mvBoardRTCGpioPinGet - mvBoardRTCGpioPinGet -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* GPIO pin number. The function return -1 for bad parameters. -+* -+*******************************************************************************/ -+MV_32 mvBoardRTCGpioPinGet(MV_VOID) -+{ -+ return mvBoarGpioPinNumGet(BOARD_GPP_RTC, 0); -+} -+ -+ -+/******************************************************************************* -+* mvBoardReset - mvBoardReset -+* -+* DESCRIPTION: -+* Reset the board -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None -+* -+*******************************************************************************/ -+MV_VOID mvBoardReset(MV_VOID) -+{ -+ MV_32 resetPin; -+ -+ /* Get gpp reset pin if define */ -+ resetPin = mvBoardResetGpioPinGet(); -+ if (resetPin != MV_ERROR) -+ { -+ MV_REG_BIT_RESET( GPP_DATA_OUT_REG(0) ,(1 << resetPin)); -+ MV_REG_BIT_RESET( GPP_DATA_OUT_EN_REG(0) ,(1 << resetPin)); -+ -+ } -+ else -+ { -+ /* No gpp reset pin was found, try to reset ussing -+ system reset out */ -+ MV_REG_BIT_SET( CPU_RSTOUTN_MASK_REG , BIT2); -+ MV_REG_BIT_SET( CPU_SYS_SOFT_RST_REG , BIT0); -+ } -+} -+ -+/******************************************************************************* -+* mvBoardResetGpioPinGet - mvBoardResetGpioPinGet -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* GPIO pin number. The function return -1 for bad parameters. -+* -+*******************************************************************************/ -+MV_32 mvBoardResetGpioPinGet(MV_VOID) -+{ -+ return mvBoarGpioPinNumGet(BOARD_GPP_RESET, 0); -+} -+/******************************************************************************* -+* mvBoardSDIOGpioPinGet - mvBoardSDIOGpioPinGet -+* -+* DESCRIPTION: -+* used for hotswap detection -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* GPIO pin number. The function return -1 for bad parameters. -+* -+*******************************************************************************/ -+MV_32 mvBoardSDIOGpioPinGet(MV_VOID) -+{ -+ return mvBoarGpioPinNumGet(BOARD_GPP_SDIO_DETECT, 0); -+} -+ -+/******************************************************************************* -+* mvBoardUSBVbusGpioPinGet - return Vbus input GPP -+* -+* DESCRIPTION: -+* -+* INPUT: -+* int devNo. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* GPIO pin number. The function return -1 for bad parameters. -+* -+*******************************************************************************/ -+MV_32 mvBoardUSBVbusGpioPinGet(MV_32 devId) -+{ -+ return mvBoarGpioPinNumGet(BOARD_GPP_USB_VBUS, devId); -+} -+ -+/******************************************************************************* -+* mvBoardUSBVbusEnGpioPinGet - return Vbus Enable output GPP -+* -+* DESCRIPTION: -+* -+* INPUT: -+* int devNo. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* GPIO pin number. The function return -1 for bad parameters. -+* -+*******************************************************************************/ -+MV_32 mvBoardUSBVbusEnGpioPinGet(MV_32 devId) -+{ -+ return mvBoarGpioPinNumGet(BOARD_GPP_USB_VBUS_EN, devId); -+} -+ -+ -+/******************************************************************************* -+* mvBoardGpioIntMaskGet - Get GPIO mask for interrupt pins -+* -+* DESCRIPTION: -+* This function returns a 32-bit mask of GPP pins that connected to -+* interrupt generating sources on board. -+* For example if UART channel A is hardwired to GPP pin 8 and -+* UART channel B is hardwired to GPP pin 4 the fuinction will return -+* the value 0x000000110 -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* See description. The function return -1 if board is not identified. -+* -+*******************************************************************************/ -+MV_32 mvBoardGpioIntMaskLowGet(MV_VOID) -+{ -+ MV_U32 boardId; -+ -+ boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardGpioIntMaskGet:Board unknown.\n"); -+ return MV_ERROR; -+ -+ } -+ -+ return BOARD_INFO(boardId)->intsGppMaskLow; -+} -+MV_32 mvBoardGpioIntMaskHighGet(MV_VOID) -+{ -+ MV_U32 boardId; -+ -+ boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardGpioIntMaskGet:Board unknown.\n"); -+ return MV_ERROR; -+ -+ } -+ -+ return BOARD_INFO(boardId)->intsGppMaskHigh; -+} -+ -+ -+/******************************************************************************* -+* mvBoardMppGet - Get board dependent MPP register value -+* -+* DESCRIPTION: -+* MPP settings are derived from board design. -+* MPP group consist of 8 MPPs. An MPP group represent MPP -+* control register. -+* This function retrieves board dependend MPP register value. -+* -+* INPUT: -+* mppGroupNum - MPP group number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit value describing MPP control register value. -+* -+*******************************************************************************/ -+MV_32 mvBoardMppGet(MV_U32 mppGroupNum) -+{ -+ MV_U32 boardId; -+ -+ boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardMppGet:Board unknown.\n"); -+ return MV_ERROR; -+ -+ } -+ -+ return BOARD_INFO(boardId)->pBoardMppConfigValue[0].mppGroup[mppGroupNum]; -+} -+ -+ -+/******************************************************************************* -+* mvBoardMppGroupId - If MPP group type is AUTO then identify it using twsi -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_VOID mvBoardMppGroupIdUpdate(MV_VOID) -+{ -+ -+ MV_BOARD_MPP_GROUP_CLASS devClass; -+ MV_BOARD_MODULE_ID_CLASS devClassId; -+ MV_BOARD_MPP_TYPE_CLASS mppGroupType; -+ MV_U32 devId; -+ MV_U32 maxMppGrp = 1; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ maxMppGrp = MV_6281_MPP_MAX_MODULE; -+ break; -+ case MV_6192_DEV_ID: -+ maxMppGrp = MV_6192_MPP_MAX_MODULE; -+ break; -+ case MV_6190_DEV_ID: -+ maxMppGrp = MV_6190_MPP_MAX_MODULE; -+ break; -+ case MV_6180_DEV_ID: -+ maxMppGrp = MV_6180_MPP_MAX_MODULE; -+ break; -+ } -+ -+ for (devClass = 0; devClass < maxMppGrp; devClass++) -+ { -+ /* If MPP group can be defined by the module connected to it */ -+ if (mvBoardMppGroupTypeGet(devClass) == MV_BOARD_AUTO) -+ { -+ /* Get MPP module ID */ -+ devClassId = mvBoarModuleTypeGet(devClass); -+ if (MV_ERROR != devClassId) -+ { -+ switch(devClassId) -+ { -+ case MV_BOARD_MODULE_TDM_ID: -+ case MV_BOARD_MODULE_TDM_5CHAN_ID: -+ mppGroupType = MV_BOARD_TDM; -+ break; -+ case MV_BOARD_MODULE_AUDIO_ID: -+ mppGroupType = MV_BOARD_AUDIO; -+ break; -+ case MV_BOARD_MODULE_RGMII_ID: -+ mppGroupType = MV_BOARD_RGMII; -+ break; -+ case MV_BOARD_MODULE_GMII_ID: -+ mppGroupType = MV_BOARD_GMII; -+ break; -+ case MV_BOARD_MODULE_TS_ID: -+ mppGroupType = MV_BOARD_TS; -+ break; -+ case MV_BOARD_MODULE_MII_ID: -+ mppGroupType = MV_BOARD_MII; -+ break; -+ default: -+ mppGroupType = MV_BOARD_OTHER; -+ break; -+ } -+ } -+ else -+ /* The module bay is empty */ -+ mppGroupType = MV_BOARD_OTHER; -+ -+ /* Update MPP group type */ -+ mvBoardMppGroupTypeSet(devClass, mppGroupType); -+ } -+ -+ /* Update MPP output voltage for RGMII 1.8V. Set port to GMII for GMII module */ -+ if ((mvBoardMppGroupTypeGet(devClass) == MV_BOARD_RGMII)) -+ MV_REG_BIT_SET(MPP_OUTPUT_DRIVE_REG,MPP_1_8_RGMII1_OUTPUT_DRIVE | MPP_1_8_RGMII0_OUTPUT_DRIVE); -+ else -+ { -+ if ((mvBoardMppGroupTypeGet(devClass) == MV_BOARD_GMII)) -+ { -+ MV_REG_BIT_RESET(MPP_OUTPUT_DRIVE_REG, BIT7 | BIT15); -+ MV_REG_BIT_RESET(ETH_PORT_SERIAL_CTRL_1_REG(0),BIT3); -+ MV_REG_BIT_RESET(ETH_PORT_SERIAL_CTRL_1_REG(1),BIT3); -+ } -+ else if ((mvBoardMppGroupTypeGet(devClass) == MV_BOARD_MII)) -+ { -+ /* Assumption that the MDC & MDIO should be 3.3V */ -+ MV_REG_BIT_RESET(MPP_OUTPUT_DRIVE_REG, BIT7 | BIT15); -+ /* Assumption that only ETH1 can be MII when using modules on DB */ -+ MV_REG_BIT_RESET(ETH_PORT_SERIAL_CTRL_1_REG(1),BIT3); -+ } -+ } -+ } -+} -+ -+/******************************************************************************* -+* mvBoardMppGroupTypeGet -+* -+* DESCRIPTION: -+* -+* INPUT: -+* mppGroupClass - MPP group number 0 for MPP[35:20] or 1 for MPP[49:36]. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_BOARD_MPP_TYPE_CLASS mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass) -+{ -+ MV_U32 boardId; -+ -+ boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardMppGet:Board unknown.\n"); -+ return MV_ERROR; -+ -+ } -+ -+ if (mppGroupClass == MV_BOARD_MPP_GROUP_1) -+ return BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup1; -+ else -+ return BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup2; -+} -+ -+/******************************************************************************* -+* mvBoardMppGroupTypeSet -+* -+* DESCRIPTION: -+* -+* INPUT: -+* mppGroupClass - MPP group number 0 for MPP[35:20] or 1 for MPP[49:36]. -+* mppGroupType - MPP group type for MPP[35:20] or for MPP[49:36]. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_VOID mvBoardMppGroupTypeSet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass, -+ MV_BOARD_MPP_TYPE_CLASS mppGroupType) -+{ -+ MV_U32 boardId; -+ -+ boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardMppGet:Board unknown.\n"); -+ } -+ -+ if (mppGroupClass == MV_BOARD_MPP_GROUP_1) -+ BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup1 = mppGroupType; -+ else -+ BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup2 = mppGroupType; -+ -+} -+ -+/******************************************************************************* -+* mvBoardMppMuxSet - Update MPP mux -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_VOID mvBoardMppMuxSet(MV_VOID) -+{ -+ -+ MV_BOARD_MPP_GROUP_CLASS devClass; -+ MV_BOARD_MPP_TYPE_CLASS mppGroupType; -+ MV_U32 devId; -+ MV_U8 muxVal = 0xf; -+ MV_U32 maxMppGrp = 1; -+ MV_TWSI_SLAVE twsiSlave; -+ MV_TWSI_ADDR slave; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ maxMppGrp = MV_6281_MPP_MAX_MODULE; -+ break; -+ case MV_6192_DEV_ID: -+ maxMppGrp = MV_6192_MPP_MAX_MODULE; -+ break; -+ case MV_6190_DEV_ID: -+ maxMppGrp = MV_6190_MPP_MAX_MODULE; -+ break; -+ case MV_6180_DEV_ID: -+ maxMppGrp = MV_6180_MPP_MAX_MODULE; -+ break; -+ } -+ -+ for (devClass = 0; devClass < maxMppGrp; devClass++) -+ { -+ mppGroupType = mvBoardMppGroupTypeGet(devClass); -+ -+ switch(mppGroupType) -+ { -+ case MV_BOARD_TDM: -+ muxVal &= ~(devClass ? (0x2 << (devClass * 2)):0x0); -+ break; -+ case MV_BOARD_AUDIO: -+ muxVal &= ~(devClass ? 0x7 : 0x0); /*old Z0 value 0xd:0x0*/ -+ break; -+ case MV_BOARD_TS: -+ muxVal &= ~(devClass ? (0x2 << (devClass * 2)):0x0); -+ break; -+ default: -+ muxVal |= (devClass ? 0xf : 0); -+ break; -+ } -+ } -+ -+ /* TWSI init */ -+ slave.type = ADDR7_BIT; -+ slave.address = 0; -+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); -+ -+ /* Read MPP module ID */ -+ DB(mvOsPrintf("Board: twsi exp set\n")); -+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(MV_BOARD_MUX_I2C_ADDR_ENTRY); -+ twsiSlave.slaveAddr.type = mvBoardTwsiExpAddrTypeGet(MV_BOARD_MUX_I2C_ADDR_ENTRY); -+ twsiSlave.validOffset = MV_TRUE; -+ /* Offset is the first command after the address which indicate the register number to be read -+ in next operation */ -+ twsiSlave.offset = 2; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ -+ -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) -+ { -+ DB(mvOsPrintf("Board: twsi exp out val fail\n")); -+ return; -+ } -+ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); -+ -+ /* Change twsi exp to output */ -+ twsiSlave.offset = 6; -+ muxVal = 0; -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) -+ { -+ DB(mvOsPrintf("Board: twsi exp change to out fail\n")); -+ return; -+ } -+ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); -+ -+} -+ -+/******************************************************************************* -+* mvBoardTdmMppSet - set MPPs in TDM module -+* -+* DESCRIPTION: -+* -+* INPUT: type of second telephony device -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_VOID mvBoardTdmMppSet(MV_32 chType) -+{ -+ -+ MV_BOARD_MPP_GROUP_CLASS devClass; -+ MV_BOARD_MPP_TYPE_CLASS mppGroupType; -+ MV_U32 devId; -+ MV_U8 muxVal = 1; -+ MV_U8 muxValMask = 1; -+ MV_U8 twsiVal; -+ MV_U32 maxMppGrp = 1; -+ MV_TWSI_SLAVE twsiSlave; -+ MV_TWSI_ADDR slave; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ maxMppGrp = MV_6281_MPP_MAX_MODULE; -+ break; -+ case MV_6192_DEV_ID: -+ maxMppGrp = MV_6192_MPP_MAX_MODULE; -+ break; -+ case MV_6190_DEV_ID: -+ maxMppGrp = MV_6190_MPP_MAX_MODULE; -+ break; -+ case MV_6180_DEV_ID: -+ maxMppGrp = MV_6180_MPP_MAX_MODULE; -+ break; -+ } -+ -+ for (devClass = 0; devClass < maxMppGrp; devClass++) -+ { -+ mppGroupType = mvBoardMppGroupTypeGet(devClass); -+ if(mppGroupType == MV_BOARD_TDM) -+ break; -+ } -+ -+ if(devClass == maxMppGrp) -+ return; /* TDM module not found */ -+ -+ /* TWSI init */ -+ slave.type = ADDR7_BIT; -+ slave.address = 0; -+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); -+ -+ /* Read MPP module ID */ -+ DB(mvOsPrintf("Board: twsi exp set\n")); -+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(devClass); -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ /* Offset is the first command after the address which indicate the register number to be read -+ in next operation */ -+ twsiSlave.offset = 3; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ if(mvBoardIdGet() == RD_88F6281A_ID) -+ { -+ muxVal = 0xc; -+ muxValMask = 0xf3; -+ } -+ -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ muxVal = (twsiVal & muxValMask) | muxVal; -+ -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) -+ { -+ mvOsPrintf("Board: twsi exp out val fail\n"); -+ return; -+ } -+ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); -+ -+ /* Change twsi exp to output */ -+ twsiSlave.offset = 7; -+ muxVal = 0xfe; -+ if(mvBoardIdGet() == RD_88F6281A_ID) -+ muxVal = 0xf3; -+ -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ muxVal = (twsiVal & muxVal); -+ -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) -+ { -+ mvOsPrintf("Board: twsi exp change to out fail\n"); -+ return; -+ } -+ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); -+ /* reset the line to 0 */ -+ twsiSlave.offset = 3; -+ muxVal = 0; -+ muxValMask = 1; -+ -+ if(mvBoardIdGet() == RD_88F6281A_ID) { -+ muxVal = 0x0; -+ muxValMask = 0xf3; -+ } -+ -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ muxVal = (twsiVal & muxValMask) | muxVal; -+ -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) -+ { -+ mvOsPrintf("Board: twsi exp out val fail\n"); -+ return; -+ } -+ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); -+ -+ mvOsDelay(20); -+ -+ /* set the line to 1 */ -+ twsiSlave.offset = 3; -+ muxVal = 1; -+ muxValMask = 1; -+ -+ if(mvBoardIdGet() == RD_88F6281A_ID) -+ { -+ muxVal = 0xc; -+ muxValMask = 0xf3; -+ if(chType) /* FXS - issue reset properly */ -+ { -+ MV_REG_BIT_SET(GPP_DATA_OUT_REG(1), MV_GPP12); -+ mvOsDelay(50); -+ MV_REG_BIT_RESET(GPP_DATA_OUT_REG(1), MV_GPP12); -+ } -+ else /* FXO - issue reset via TDM_CODEC_RST*/ -+ { -+ /* change MPP44 type to TDM_CODEC_RST(0x2) */ -+ MV_REG_WRITE(MPP_CONTROL_REG5, ((MV_REG_READ(MPP_CONTROL_REG5) & 0xFFF0FFFF) | BIT17)); -+ } -+ } -+ -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ muxVal = (twsiVal & muxValMask) | muxVal; -+ -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) -+ { -+ mvOsPrintf("Board: twsi exp out val fail\n"); -+ return; -+ } -+ -+ /* TBD - 5 channels */ -+#if defined(MV_TDM_5CHANNELS) -+ /* change MPP38 type to GPIO(0x0) & polarity for TDM_STROBE */ -+ MV_REG_WRITE(MPP_CONTROL_REG4, (MV_REG_READ(MPP_CONTROL_REG4) & 0xF0FFFFFF)); -+ mvGppPolaritySet(1, MV_GPP6, 0); -+ -+ twsiSlave.offset = 6; -+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(2); -+ -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ muxVal = (twsiVal & ~BIT2); -+ -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) -+ { -+ mvOsPrintf("Board: twsi exp change to out fail\n"); -+ return; -+ } -+ -+ -+ twsiSlave.offset = 2; -+ -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ muxVal = (twsiVal & ~BIT2); -+ -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) -+ { -+ mvOsPrintf("Board: twsi exp change to out fail\n"); -+ return; -+ } -+#endif -+ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); -+ -+ -+} -+/******************************************************************************* -+* mvBoardVoiceConnModeGet - return SLIC/DAA connection & interrupt modes -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+ -+MV_VOID mvBoardVoiceConnModeGet(MV_32* connMode, MV_32* irqMode) -+{ -+ switch(mvBoardIdGet()) -+ { -+ case RD_88F6281A_ID: -+ *connMode = DAISY_CHAIN_MODE; -+ *irqMode = INTERRUPT_TO_TDM; -+ break; -+ case DB_88F6281A_BP_ID: -+ *connMode = DUAL_CHIP_SELECT_MODE; -+ *irqMode = INTERRUPT_TO_TDM; -+ break; -+ case RD_88F6192A_ID: -+ *connMode = DUAL_CHIP_SELECT_MODE; -+ *irqMode = INTERRUPT_TO_TDM; -+ break; -+ case DB_88F6192A_BP_ID: -+ *connMode = DUAL_CHIP_SELECT_MODE; -+ *irqMode = INTERRUPT_TO_TDM; -+ break; -+ default: -+ *connMode = *irqMode = -1; -+ mvOsPrintf("mvBoardVoiceAssembleModeGet: TDM not supported(boardId=0x%x)\n",mvBoardIdGet()); -+ } -+ return; -+ -+} -+ -+/******************************************************************************* -+* mvBoardMppModuleTypePrint - print module detect -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_VOID mvBoardMppModuleTypePrint(MV_VOID) -+{ -+ -+ MV_BOARD_MPP_GROUP_CLASS devClass; -+ MV_BOARD_MPP_TYPE_CLASS mppGroupType; -+ MV_U32 devId; -+ MV_U32 maxMppGrp = 1; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ maxMppGrp = MV_6281_MPP_MAX_MODULE; -+ break; -+ case MV_6192_DEV_ID: -+ maxMppGrp = MV_6192_MPP_MAX_MODULE; -+ break; -+ case MV_6190_DEV_ID: -+ maxMppGrp = MV_6190_MPP_MAX_MODULE; -+ break; -+ case MV_6180_DEV_ID: -+ maxMppGrp = MV_6180_MPP_MAX_MODULE; -+ break; -+ } -+ -+ for (devClass = 0; devClass < maxMppGrp; devClass++) -+ { -+ mppGroupType = mvBoardMppGroupTypeGet(devClass); -+ -+ switch(mppGroupType) -+ { -+ case MV_BOARD_TDM: -+ if(devId != MV_6190_DEV_ID) -+ mvOsPrintf("Module %d is TDM\n", devClass); -+ break; -+ case MV_BOARD_AUDIO: -+ if(devId != MV_6190_DEV_ID) -+ mvOsPrintf("Module %d is AUDIO\n", devClass); -+ break; -+ case MV_BOARD_RGMII: -+ if(devId != MV_6190_DEV_ID) -+ mvOsPrintf("Module %d is RGMII\n", devClass); -+ break; -+ case MV_BOARD_GMII: -+ if(devId != MV_6190_DEV_ID) -+ mvOsPrintf("Module %d is GMII\n", devClass); -+ break; -+ case MV_BOARD_TS: -+ if(devId != MV_6190_DEV_ID) -+ mvOsPrintf("Module %d is TS\n", devClass); -+ break; -+ default: -+ break; -+ } -+ } -+} -+ -+/* Board devices API managments */ -+ -+/******************************************************************************* -+* mvBoardGetDeviceNumber - Get number of device of some type on the board -+* -+* DESCRIPTION: -+* -+* INPUT: -+* devType - The device type ( Flash,RTC , etc .. ) -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* If the device is found on the board the then the functions returns the -+* number of those devices else the function returns 0 -+* -+* -+*******************************************************************************/ -+MV_32 mvBoardGetDevicesNumber(MV_BOARD_DEV_CLASS devClass) -+{ -+ MV_U32 foundIndex=0,devNum; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("mvBoardGetDeviceNumber:Board unknown.\n"); -+ return 0xFFFFFFFF; -+ -+ } -+ -+ for (devNum = START_DEV_CS; devNum < BOARD_INFO(boardId)->numBoardDeviceIf; devNum++) -+ { -+ if (BOARD_INFO(boardId)->pDevCsInfo[devNum].devClass == devClass) -+ { -+ foundIndex++; -+ } -+ } -+ -+ return foundIndex; -+ -+} -+ -+/******************************************************************************* -+* mvBoardGetDeviceBaseAddr - Get base address of a device existing on the board -+* -+* DESCRIPTION: -+* -+* INPUT: -+* devIndex - The device sequential number on the board -+* devType - The device type ( Flash,RTC , etc .. ) -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* If the device is found on the board the then the functions returns the -+* Base address else the function returns 0xffffffff -+* -+* -+*******************************************************************************/ -+MV_32 mvBoardGetDeviceBaseAddr(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) -+{ -+ MV_DEV_CS_INFO* devEntry; -+ devEntry = boardGetDevEntry(devNum,devClass); -+ if (devEntry != NULL) -+ { -+ return mvCpuIfTargetWinBaseLowGet(DEV_TO_TARGET(devEntry->deviceCS)); -+ -+ } -+ -+ return 0xFFFFFFFF; -+} -+ -+/******************************************************************************* -+* mvBoardGetDeviceBusWidth - Get Bus width of a device existing on the board -+* -+* DESCRIPTION: -+* -+* INPUT: -+* devIndex - The device sequential number on the board -+* devType - The device type ( Flash,RTC , etc .. ) -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* If the device is found on the board the then the functions returns the -+* Bus width else the function returns 0xffffffff -+* -+* -+*******************************************************************************/ -+MV_32 mvBoardGetDeviceBusWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) -+{ -+ MV_DEV_CS_INFO* devEntry; -+ -+ devEntry = boardGetDevEntry(devNum,devClass); -+ if (devEntry != NULL) -+ { -+ return 8; -+ } -+ -+ return 0xFFFFFFFF; -+ -+} -+ -+/******************************************************************************* -+* mvBoardGetDeviceWidth - Get dev width of a device existing on the board -+* -+* DESCRIPTION: -+* -+* INPUT: -+* devIndex - The device sequential number on the board -+* devType - The device type ( Flash,RTC , etc .. ) -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* If the device is found on the board the then the functions returns the -+* dev width else the function returns 0xffffffff -+* -+* -+*******************************************************************************/ -+MV_32 mvBoardGetDeviceWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) -+{ -+ MV_DEV_CS_INFO* devEntry; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("Board unknown.\n"); -+ return 0xFFFFFFFF; -+ } -+ -+ devEntry = boardGetDevEntry(devNum,devClass); -+ if (devEntry != NULL) -+ return devEntry->devWidth; -+ -+ return MV_ERROR; -+ -+} -+ -+/******************************************************************************* -+* mvBoardGetDeviceWinSize - Get the window size of a device existing on the board -+* -+* DESCRIPTION: -+* -+* INPUT: -+* devIndex - The device sequential number on the board -+* devType - The device type ( Flash,RTC , etc .. ) -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* If the device is found on the board the then the functions returns the -+* window size else the function returns 0xffffffff -+* -+* -+*******************************************************************************/ -+MV_32 mvBoardGetDeviceWinSize(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) -+{ -+ MV_DEV_CS_INFO* devEntry; -+ MV_U32 boardId = mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("Board unknown.\n"); -+ return 0xFFFFFFFF; -+ } -+ -+ devEntry = boardGetDevEntry(devNum,devClass); -+ if (devEntry != NULL) -+ { -+ return mvCpuIfTargetWinSizeGet(DEV_TO_TARGET(devEntry->deviceCS)); -+ } -+ -+ return 0xFFFFFFFF; -+} -+ -+ -+/******************************************************************************* -+* boardGetDevEntry - returns the entry pointer of a device on the board -+* -+* DESCRIPTION: -+* -+* INPUT: -+* devIndex - The device sequential number on the board -+* devType - The device type ( Flash,RTC , etc .. ) -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* If the device is found on the board the then the functions returns the -+* dev number else the function returns 0x0 -+* -+* -+*******************************************************************************/ -+static MV_DEV_CS_INFO* boardGetDevEntry(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) -+{ -+ MV_U32 foundIndex=0,devIndex; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("boardGetDevEntry: Board unknown.\n"); -+ return NULL; -+ -+ } -+ -+ for (devIndex = START_DEV_CS; devIndex < BOARD_INFO(boardId)->numBoardDeviceIf; devIndex++) -+ { -+ /* TBR */ -+ /*if (BOARD_INFO(boardId)->pDevCsInfo[devIndex].deviceCS == MV_BOOTDEVICE_INDEX) -+ continue;*/ -+ -+ if (BOARD_INFO(boardId)->pDevCsInfo[devIndex].devClass == devClass) -+ { -+ if (foundIndex == devNum) -+ { -+ return &(BOARD_INFO(boardId)->pDevCsInfo[devIndex]); -+ } -+ foundIndex++; -+ } -+ } -+ -+ /* device not found */ -+ return NULL; -+} -+ -+/* Get device CS number */ -+ -+MV_U32 boardGetDevCSNum(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) -+{ -+ MV_DEV_CS_INFO* devEntry; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) -+ { -+ mvOsPrintf("Board unknown.\n"); -+ return 0xFFFFFFFF; -+ -+ } -+ -+ -+ devEntry = boardGetDevEntry(devNum,devClass); -+ if (devEntry != NULL) -+ return devEntry->deviceCS; -+ -+ return 0xFFFFFFFF; -+ -+} -+ -+/******************************************************************************* -+* mvBoardRtcTwsiAddrTypeGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_U8 mvBoardRtcTwsiAddrTypeGet() -+{ -+ int i; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) -+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_RTC) -+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; -+ return (MV_ERROR); -+} -+ -+/******************************************************************************* -+* mvBoardRtcTwsiAddrGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_U8 mvBoardRtcTwsiAddrGet() -+{ -+ int i; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) -+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_RTC) -+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; -+ return (0xFF); -+} -+ -+/******************************************************************************* -+* mvBoardA2DTwsiAddrTypeGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_U8 mvBoardA2DTwsiAddrTypeGet() -+{ -+ int i; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) -+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_AUDIO_DEC) -+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; -+ return (MV_ERROR); -+} -+ -+/******************************************************************************* -+* mvBoardA2DTwsiAddrGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_U8 mvBoardA2DTwsiAddrGet() -+{ -+ int i; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) -+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_AUDIO_DEC) -+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; -+ return (0xFF); -+} -+ -+/******************************************************************************* -+* mvBoardTwsiExpAddrTypeGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_U8 mvBoardTwsiExpAddrTypeGet(MV_U32 index) -+{ -+ int i; -+ MV_U32 indexFound = 0; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) -+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_EXP) -+ { -+ if (indexFound == index) -+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; -+ else -+ indexFound++; -+ } -+ -+ return (MV_ERROR); -+} -+ -+/******************************************************************************* -+* mvBoardTwsiExpAddrGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_U8 mvBoardTwsiExpAddrGet(MV_U32 index) -+{ -+ int i; -+ MV_U32 indexFound = 0; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) -+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_EXP) -+ { -+ if (indexFound == index) -+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; -+ else -+ indexFound++; -+ } -+ -+ return (0xFF); -+} -+ -+ -+/******************************************************************************* -+* mvBoardTwsiSatRAddrTypeGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_U8 mvBoardTwsiSatRAddrTypeGet(MV_U32 index) -+{ -+ int i; -+ MV_U32 indexFound = 0; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) -+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_SATR) -+ { -+ if (indexFound == index) -+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; -+ else -+ indexFound++; -+ } -+ -+ return (MV_ERROR); -+} -+ -+/******************************************************************************* -+* mvBoardTwsiSatRAddrGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_U8 mvBoardTwsiSatRAddrGet(MV_U32 index) -+{ -+ int i; -+ MV_U32 indexFound = 0; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) -+ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_SATR) -+ { -+ if (indexFound == index) -+ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; -+ else -+ indexFound++; -+ } -+ -+ return (0xFF); -+} -+ -+/******************************************************************************* -+* mvBoardNandWidthGet - -+* -+* DESCRIPTION: Get the width of the first NAND device in byte. -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: 1, 2, 4 or MV_ERROR -+* -+* -+*******************************************************************************/ -+/* */ -+MV_32 mvBoardNandWidthGet(void) -+{ -+ MV_U32 devNum; -+ MV_U32 devWidth; -+ MV_U32 boardId= mvBoardIdGet(); -+ -+ for (devNum = START_DEV_CS; devNum < BOARD_INFO(boardId)->numBoardDeviceIf; devNum++) -+ { -+ devWidth = mvBoardGetDeviceWidth(devNum, BOARD_DEV_NAND_FLASH); -+ if (devWidth != MV_ERROR) -+ return (devWidth / 8); -+ } -+ -+ /* NAND wasn't found */ -+ return MV_ERROR; -+} -+ -+MV_U32 gBoardId = -1; -+ -+/******************************************************************************* -+* mvBoardIdGet - Get Board model -+* -+* DESCRIPTION: -+* This function returns board ID. -+* Board ID is 32bit word constructed of board model (16bit) and -+* board revision (16bit) in the following way: 0xMMMMRRRR. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit board ID number, '-1' if board is undefined. -+* -+*******************************************************************************/ -+MV_U32 mvBoardIdGet(MV_VOID) -+{ -+ MV_U32 tmpBoardId = -1; -+ -+ if(gBoardId == -1) -+ { -+ #if defined(DB_88F6281A) -+ tmpBoardId = DB_88F6281A_BP_ID; -+ #elif defined(RD_88F6281A) -+ tmpBoardId = RD_88F6281A_ID; -+ #elif defined(DB_88F6192A) -+ tmpBoardId = DB_88F6192A_BP_ID; -+ #elif defined(DB_88F6190A) -+ tmpBoardId = DB_88F6190A_BP_ID; -+ #elif defined(RD_88F6192A) -+ tmpBoardId = RD_88F6192A_ID; -+ #elif defined(RD_88F6190A) -+ tmpBoardId = RD_88F6190A_ID; -+ #elif defined(DB_88F6180A) -+ tmpBoardId = DB_88F6180A_BP_ID; -+ #elif defined(RD_88F6281A_PCAC) -+ tmpBoardId = RD_88F6281A_PCAC_ID; -+ #elif defined(RD_88F6281A_SHEEVA_PLUG) -+ tmpBoardId = SHEEVA_PLUG_ID; -+ #elif defined(DB_CUSTOMER) -+ tmpBoardId = DB_CUSTOMER_ID; -+ #endif -+ gBoardId = tmpBoardId; -+ } -+ -+ return gBoardId; -+} -+ -+ -+/******************************************************************************* -+* mvBoarModuleTypeGet - mvBoarModuleTypeGet -+* -+* DESCRIPTION: -+* -+* INPUT: -+* group num - MV_BOARD_MPP_GROUP_CLASS enum -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* module num - MV_BOARD_MODULE_CLASS enum -+* -+*******************************************************************************/ -+MV_BOARD_MODULE_ID_CLASS mvBoarModuleTypeGet(MV_BOARD_MPP_GROUP_CLASS devClass) -+{ -+ MV_TWSI_SLAVE twsiSlave; -+ MV_TWSI_ADDR slave; -+ MV_U8 data; -+ -+ /* TWSI init */ -+ slave.type = ADDR7_BIT; -+ slave.address = 0; -+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); -+ -+ /* Read MPP module ID */ -+ DB(mvOsPrintf("Board: Read MPP module ID\n")); -+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(devClass); -+ twsiSlave.slaveAddr.type = mvBoardTwsiExpAddrTypeGet(devClass); -+ twsiSlave.validOffset = MV_TRUE; -+ /* Offset is the first command after the address which indicate the register number to be read -+ in next operation */ -+ twsiSlave.offset = 0; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ -+ -+ if( MV_OK != mvTwsiRead (0, &twsiSlave, &data, 1) ) -+ { -+ DB(mvOsPrintf("Board: Read MPP module ID fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: Read MPP module ID succeded\n")); -+ -+ return data; -+} -+ -+/******************************************************************************* -+* mvBoarTwsiSatRGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* device num - one of three devices -+* reg num - 0 or 1 -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* reg value -+* -+*******************************************************************************/ -+MV_U8 mvBoarTwsiSatRGet(MV_U8 devNum, MV_U8 regNum) -+{ -+ MV_TWSI_SLAVE twsiSlave; -+ MV_TWSI_ADDR slave; -+ MV_U8 data; -+ -+ /* TWSI init */ -+ slave.type = ADDR7_BIT; -+ slave.address = 0; -+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); -+ -+ /* Read MPP module ID */ -+ DB(mvOsPrintf("Board: Read S@R device read\n")); -+ twsiSlave.slaveAddr.address = mvBoardTwsiSatRAddrGet(devNum); -+ twsiSlave.slaveAddr.type = mvBoardTwsiSatRAddrTypeGet(devNum); -+ twsiSlave.validOffset = MV_TRUE; -+ /* Use offset as command */ -+ twsiSlave.offset = regNum; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ if( MV_OK != mvTwsiRead (0, &twsiSlave, &data, 1) ) -+ { -+ DB(mvOsPrintf("Board: Read S@R fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: Read S@R succeded\n")); -+ -+ return data; -+} -+ -+/******************************************************************************* -+* mvBoarTwsiSatRSet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* devNum - one of three devices -+* regNum - 0 or 1 -+* regVal - value -+* -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* reg value -+* -+*******************************************************************************/ -+MV_STATUS mvBoarTwsiSatRSet(MV_U8 devNum, MV_U8 regNum, MV_U8 regVal) -+{ -+ MV_TWSI_SLAVE twsiSlave; -+ MV_TWSI_ADDR slave; -+ -+ /* TWSI init */ -+ slave.type = ADDR7_BIT; -+ slave.address = 0; -+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); -+ -+ /* Read MPP module ID */ -+ twsiSlave.slaveAddr.address = mvBoardTwsiSatRAddrGet(devNum); -+ twsiSlave.slaveAddr.type = mvBoardTwsiSatRAddrTypeGet(devNum); -+ twsiSlave.validOffset = MV_TRUE; -+ DB(mvOsPrintf("Board: Write S@R device addr %x, type %x, data %x\n", twsiSlave.slaveAddr.address,\ -+ twsiSlave.slaveAddr.type, regVal)); -+ /* Use offset as command */ -+ twsiSlave.offset = regNum; -+ twsiSlave.moreThen256 = MV_FALSE; -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, ®Val, 1) ) -+ { -+ DB(mvOsPrintf("Board: Write S@R fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: Write S@R succeded\n")); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvBoardSlicGpioPinGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* -+*******************************************************************************/ -+MV_32 mvBoardSlicGpioPinGet(MV_U32 slicNum) -+{ -+ MV_U32 boardId; -+ boardId = mvBoardIdGet(); -+ -+ switch (boardId) -+ { -+ case DB_88F6281A_BP_ID: -+ case RD_88F6281A_ID: -+ default: -+ return MV_ERROR; -+ break; -+ -+ } -+} -+ -+/******************************************************************************* -+* mvBoardFanPowerControl - Turn on/off the fan power control on the RD-6281A -+* -+* DESCRIPTION: -+* -+* INPUT: -+* mode - MV_TRUE = on ; MV_FALSE = off -+* -+* OUTPUT: -+* MV_STATUS - MV_OK , MV_ERROR. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_STATUS mvBoardFanPowerControl(MV_BOOL mode) -+{ -+ -+ MV_U8 val = 1, twsiVal; -+ MV_TWSI_SLAVE twsiSlave; -+ MV_TWSI_ADDR slave; -+ -+ if(mvBoardIdGet() != RD_88F6281A_ID) -+ return MV_ERROR; -+ -+ /* TWSI init */ -+ slave.type = ADDR7_BIT; -+ slave.address = 0; -+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); -+ -+ /* Read MPP module ID */ -+ DB(mvOsPrintf("Board: twsi exp set\n")); -+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(1); -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ /* Offset is the first command after the address which indicate the register number to be read -+ in next operation */ -+ twsiSlave.offset = 3; -+ twsiSlave.moreThen256 = MV_FALSE; -+ if(mode == MV_TRUE) -+ val = 0x1; -+ else -+ val = 0; -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ val = (twsiVal & 0xfe) | val; -+ -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) -+ { -+ DB(mvOsPrintf("Board: twsi exp out val fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); -+ -+ /* Change twsi exp to output */ -+ twsiSlave.offset = 7; -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ val = (twsiVal & 0xfe); -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) -+ { -+ DB(mvOsPrintf("Board: twsi exp change to out fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvBoardHDDPowerControl - Turn on/off the HDD power control on the RD-6281A -+* -+* DESCRIPTION: -+* -+* INPUT: -+* mode - MV_TRUE = on ; MV_FALSE = off -+* -+* OUTPUT: -+* MV_STATUS - MV_OK , MV_ERROR. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_STATUS mvBoardHDDPowerControl(MV_BOOL mode) -+{ -+ -+ MV_U8 val = 1, twsiVal; -+ MV_TWSI_SLAVE twsiSlave; -+ MV_TWSI_ADDR slave; -+ -+ if(mvBoardIdGet() != RD_88F6281A_ID) -+ return MV_ERROR; -+ -+ /* TWSI init */ -+ slave.type = ADDR7_BIT; -+ slave.address = 0; -+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); -+ -+ /* Read MPP module ID */ -+ DB(mvOsPrintf("Board: twsi exp set\n")); -+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(1); -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ /* Offset is the first command after the address which indicate the register number to be read -+ in next operation */ -+ twsiSlave.offset = 3; -+ twsiSlave.moreThen256 = MV_FALSE; -+ if(mode == MV_TRUE) -+ val = 0x2; -+ else -+ val = 0; -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ val = (twsiVal & 0xfd) | val; -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) -+ { -+ DB(mvOsPrintf("Board: twsi exp out val fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); -+ -+ /* Change twsi exp to output */ -+ twsiSlave.offset = 7; -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ val = (twsiVal & 0xfd); -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) -+ { -+ DB(mvOsPrintf("Board: twsi exp change to out fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvBoardSDioWPControl - Turn on/off the SDIO WP on the RD-6281A -+* -+* DESCRIPTION: -+* -+* INPUT: -+* mode - MV_TRUE = on ; MV_FALSE = off -+* -+* OUTPUT: -+* MV_STATUS - MV_OK , MV_ERROR. -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_STATUS mvBoardSDioWPControl(MV_BOOL mode) -+{ -+ -+ MV_U8 val = 1, twsiVal; -+ MV_TWSI_SLAVE twsiSlave; -+ MV_TWSI_ADDR slave; -+ -+ if(mvBoardIdGet() != RD_88F6281A_ID) -+ return MV_ERROR; -+ -+ /* TWSI init */ -+ slave.type = ADDR7_BIT; -+ slave.address = 0; -+ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); -+ -+ /* Read MPP module ID */ -+ DB(mvOsPrintf("Board: twsi exp set\n")); -+ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(0); -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ /* Offset is the first command after the address which indicate the register number to be read -+ in next operation */ -+ twsiSlave.offset = 3; -+ twsiSlave.moreThen256 = MV_FALSE; -+ if(mode == MV_TRUE) -+ val = 0x10; -+ else -+ val = 0; -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ val = (twsiVal & 0xef) | val; -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) -+ { -+ DB(mvOsPrintf("Board: twsi exp out val fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); -+ -+ /* Change twsi exp to output */ -+ twsiSlave.offset = 7; -+ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); -+ val = (twsiVal & 0xef); -+ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) -+ { -+ DB(mvOsPrintf("Board: twsi exp change to out fail\n")); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); -+ return MV_OK; -+} -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,376 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#ifndef __INCmvBoardEnvLibh -+#define __INCmvBoardEnvLibh -+ -+/* defines */ -+/* The below constant macros defines the board I2C EEPROM data offsets */ -+ -+ -+ -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "mvSysHwConfig.h" -+#include "boardEnv/mvBoardEnvSpec.h" -+ -+ -+/* DUART stuff for Tclk detection only */ -+#define DUART_BAUD_RATE 115200 -+#define MAX_CLOCK_MARGINE 5000000 /* Maximum detected clock margine */ -+ -+/* Voice devices assembly modes */ -+#define DAISY_CHAIN_MODE 1 -+#define DUAL_CHIP_SELECT_MODE 0 -+#define INTERRUPT_TO_MPP 1 -+#define INTERRUPT_TO_TDM 0 -+ -+ -+#define BOARD_ETH_PORT_NUM MV_ETH_MAX_PORTS -+#define BOARD_ETH_SWITCH_PORT_NUM 5 -+ -+#define MV_BOARD_MAX_USB_IF 1 -+#define MV_BOARD_MAX_MPP 7 -+#define MV_BOARD_NAME_LEN 0x20 -+ -+typedef struct _boardData -+{ -+ MV_U32 magic; -+ MV_U16 boardId; -+ MV_U8 boardVer; -+ MV_U8 boardRev; -+ MV_U32 reserved1; -+ MV_U32 reserved2; -+ -+}BOARD_DATA; -+ -+typedef enum _devBoardMppGroupClass -+{ -+ MV_BOARD_MPP_GROUP_1, -+ MV_BOARD_MPP_GROUP_2, -+ MV_BOARD_MAX_MPP_GROUP -+}MV_BOARD_MPP_GROUP_CLASS; -+ -+typedef enum _devBoardMppTypeClass -+{ -+ MV_BOARD_AUTO, -+ MV_BOARD_TDM, -+ MV_BOARD_AUDIO, -+ MV_BOARD_RGMII, -+ MV_BOARD_GMII, -+ MV_BOARD_TS, -+ MV_BOARD_MII, -+ MV_BOARD_OTHER -+}MV_BOARD_MPP_TYPE_CLASS; -+ -+typedef enum _devBoardModuleIdClass -+{ -+ MV_BOARD_MODULE_TDM_ID = 1, -+ MV_BOARD_MODULE_AUDIO_ID, -+ MV_BOARD_MODULE_RGMII_ID, -+ MV_BOARD_MODULE_GMII_ID, -+ MV_BOARD_MODULE_TS_ID, -+ MV_BOARD_MODULE_MII_ID, -+ MV_BOARD_MODULE_TDM_5CHAN_ID, -+ MV_BOARD_MODULE_OTHER_ID -+}MV_BOARD_MODULE_ID_CLASS; -+ -+typedef struct _boardMppTypeInfo -+{ -+ MV_BOARD_MPP_TYPE_CLASS boardMppGroup1; -+ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2; -+ -+}MV_BOARD_MPP_TYPE_INFO; -+ -+ -+typedef enum _devBoardClass -+{ -+ BOARD_DEV_NOR_FLASH, -+ BOARD_DEV_NAND_FLASH, -+ BOARD_DEV_SEVEN_SEG, -+ BOARD_DEV_FPGA, -+ BOARD_DEV_SRAM, -+ BOARD_DEV_SPI_FLASH, -+ BOARD_DEV_OTHER, -+}MV_BOARD_DEV_CLASS; -+ -+typedef enum _devTwsiBoardClass -+{ -+ BOARD_TWSI_RTC, -+ BOARD_DEV_TWSI_EXP, -+ BOARD_DEV_TWSI_SATR, -+ BOARD_TWSI_AUDIO_DEC, -+ BOARD_TWSI_OTHER -+}MV_BOARD_TWSI_CLASS; -+ -+typedef enum _devGppBoardClass -+{ -+ BOARD_GPP_RTC, -+ BOARD_GPP_MV_SWITCH, -+ BOARD_GPP_USB_VBUS, -+ BOARD_GPP_USB_VBUS_EN, -+ BOARD_GPP_USB_OC, -+ BOARD_GPP_USB_HOST_DEVICE, -+ BOARD_GPP_REF_CLCK, -+ BOARD_GPP_VOIP_SLIC, -+ BOARD_GPP_LIFELINE, -+ BOARD_GPP_BUTTON, -+ BOARD_GPP_TS_BUTTON_C, -+ BOARD_GPP_TS_BUTTON_U, -+ BOARD_GPP_TS_BUTTON_D, -+ BOARD_GPP_TS_BUTTON_L, -+ BOARD_GPP_TS_BUTTON_R, -+ BOARD_GPP_POWER_BUTTON, -+ BOARD_GPP_RESTOR_BUTTON, -+ BOARD_GPP_WPS_BUTTON, -+ BOARD_GPP_HDD0_POWER, -+ BOARD_GPP_HDD1_POWER, -+ BOARD_GPP_FAN_POWER, -+ BOARD_GPP_RESET, -+ BOARD_GPP_POWER_ON_LED, -+ BOARD_GPP_HDD_POWER, -+ BOARD_GPP_SDIO_POWER, -+ BOARD_GPP_SDIO_DETECT, -+ BOARD_GPP_SDIO_WP, -+ BOARD_GPP_SWITCH_PHY_INT, -+ BOARD_GPP_TSU_DIRCTION, -+ BOARD_GPP_OTHER -+}MV_BOARD_GPP_CLASS; -+ -+ -+typedef struct _devCsInfo -+{ -+ MV_U8 deviceCS; -+ MV_U32 params; -+ MV_U32 devClass; /* MV_BOARD_DEV_CLASS */ -+ MV_U8 devWidth; -+ -+}MV_DEV_CS_INFO; -+ -+ -+#define MV_BOARD_PHY_FORCE_10MB 0x0 -+#define MV_BOARD_PHY_FORCE_100MB 0x1 -+#define MV_BOARD_PHY_FORCE_1000MB 0x2 -+#define MV_BOARD_PHY_SPEED_AUTO 0x3 -+ -+typedef struct _boardSwitchInfo -+{ -+ MV_32 linkStatusIrq; -+ MV_32 qdPort[BOARD_ETH_SWITCH_PORT_NUM]; -+ MV_32 qdCpuPort; -+ MV_32 smiScanMode; /* 1 for SMI_MANUAL_MODE, 0 otherwise */ -+ MV_32 switchOnPort; -+ -+}MV_BOARD_SWITCH_INFO; -+ -+typedef struct _boardLedInfo -+{ -+ MV_U8 activeLedsNumber; -+ MV_U8 ledsPolarity; /* '0' or '1' to turn on led */ -+ MV_U8* gppPinNum; /* Pointer to GPP values */ -+ -+}MV_BOARD_LED_INFO; -+ -+typedef struct _boardGppInfo -+{ -+ MV_BOARD_GPP_CLASS devClass; -+ MV_U8 gppPinNum; -+ -+}MV_BOARD_GPP_INFO; -+ -+ -+typedef struct _boardTwsiInfo -+{ -+ MV_BOARD_TWSI_CLASS devClass; -+ MV_U8 twsiDevAddr; -+ MV_U8 twsiDevAddrType; -+ -+}MV_BOARD_TWSI_INFO; -+ -+ -+typedef enum _boardMacSpeed -+{ -+ BOARD_MAC_SPEED_10M, -+ BOARD_MAC_SPEED_100M, -+ BOARD_MAC_SPEED_1000M, -+ BOARD_MAC_SPEED_AUTO, -+ -+}MV_BOARD_MAC_SPEED; -+ -+typedef struct _boardMacInfo -+{ -+ MV_BOARD_MAC_SPEED boardMacSpeed; -+ MV_U8 boardEthSmiAddr; -+ -+}MV_BOARD_MAC_INFO; -+ -+typedef struct _boardMppInfo -+{ -+ MV_U32 mppGroup[MV_BOARD_MAX_MPP]; -+ -+}MV_BOARD_MPP_INFO; -+ -+typedef struct _boardInfo -+{ -+ char boardName[MV_BOARD_NAME_LEN]; -+ MV_U8 numBoardMppTypeValue; -+ MV_BOARD_MPP_TYPE_INFO* pBoardMppTypeValue; -+ MV_U8 numBoardMppConfigValue; -+ MV_BOARD_MPP_INFO* pBoardMppConfigValue; -+ MV_U32 intsGppMaskLow; -+ MV_U32 intsGppMaskHigh; -+ MV_U8 numBoardDeviceIf; -+ MV_DEV_CS_INFO* pDevCsInfo; -+ MV_U8 numBoardTwsiDev; -+ MV_BOARD_TWSI_INFO* pBoardTwsiDev; -+ MV_U8 numBoardMacInfo; -+ MV_BOARD_MAC_INFO* pBoardMacInfo; -+ MV_U8 numBoardGppInfo; -+ MV_BOARD_GPP_INFO* pBoardGppInfo; -+ MV_U8 activeLedsNumber; -+ MV_U8* pLedGppPin; -+ MV_U8 ledsPolarity; /* '0' or '1' to turn on led */ -+ /* GPP values */ -+ MV_U32 gppOutEnValLow; -+ MV_U32 gppOutEnValHigh; -+ MV_U32 gppOutValLow; -+ MV_U32 gppOutValHigh; -+ MV_U32 gppPolarityValLow; -+ MV_U32 gppPolarityValHigh; -+ -+ /* Switch Configuration */ -+ MV_BOARD_SWITCH_INFO* pSwitchInfo; -+}MV_BOARD_INFO; -+ -+ -+ -+MV_VOID mvBoardEnvInit(MV_VOID); -+MV_U32 mvBoardIdGet(MV_VOID); -+MV_U16 mvBoardModelGet(MV_VOID); -+MV_U16 mvBoardRevGet(MV_VOID); -+MV_STATUS mvBoardNameGet(char *pNameBuff); -+MV_32 mvBoardPhyAddrGet(MV_U32 ethPortNum); -+MV_BOARD_MAC_SPEED mvBoardMacSpeedGet(MV_U32 ethPortNum); -+MV_32 mvBoardLinkStatusIrqGet(MV_U32 ethPortNum); -+MV_32 mvBoardSwitchPortGet(MV_U32 ethPortNum, MV_U8 boardPortNum); -+MV_32 mvBoardSwitchCpuPortGet(MV_U32 ethPortNum); -+MV_32 mvBoardIsSwitchConnected(MV_U32 ethPortNum); -+MV_32 mvBoardSmiScanModeGet(MV_U32 ethPortNum); -+MV_BOOL mvBoardIsPortInSgmii(MV_U32 ethPortNum); -+MV_BOOL mvBoardIsPortInGmii(MV_VOID); -+MV_U32 mvBoardTclkGet(MV_VOID); -+MV_U32 mvBoardSysClkGet(MV_VOID); -+MV_U32 mvBoardDebugLedNumGet(MV_U32 boardId); -+MV_VOID mvBoardDebugLed(MV_U32 hexNum); -+MV_32 mvBoardMppGet(MV_U32 mppGroupNum); -+ -+MV_U8 mvBoardRtcTwsiAddrTypeGet(MV_VOID); -+MV_U8 mvBoardRtcTwsiAddrGet(MV_VOID); -+ -+MV_U8 mvBoardA2DTwsiAddrTypeGet(MV_VOID); -+MV_U8 mvBoardA2DTwsiAddrGet(MV_VOID); -+ -+MV_U8 mvBoardTwsiExpAddrGet(MV_U32 index); -+MV_U8 mvBoardTwsiSatRAddrTypeGet(MV_U32 index); -+MV_U8 mvBoardTwsiSatRAddrGet(MV_U32 index); -+MV_U8 mvBoardTwsiExpAddrTypeGet(MV_U32 index); -+MV_BOARD_MODULE_ID_CLASS mvBoarModuleTypeGet(MV_BOARD_MPP_GROUP_CLASS devClass); -+MV_BOARD_MPP_TYPE_CLASS mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass); -+MV_VOID mvBoardMppGroupTypeSet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass, -+ MV_BOARD_MPP_TYPE_CLASS mppGroupType); -+MV_VOID mvBoardMppGroupIdUpdate(MV_VOID); -+MV_VOID mvBoardMppMuxSet(MV_VOID); -+MV_VOID mvBoardTdmMppSet(MV_32 chType); -+MV_VOID mvBoardVoiceConnModeGet(MV_32* connMode, MV_32* irqMode); -+ -+MV_VOID mvBoardMppModuleTypePrint(MV_VOID); -+MV_VOID mvBoardReset(MV_VOID); -+MV_U8 mvBoarTwsiSatRGet(MV_U8 devNum, MV_U8 regNum); -+MV_STATUS mvBoarTwsiSatRSet(MV_U8 devNum, MV_U8 regNum, MV_U8 regVal); -+MV_BOOL mvBoardSpecInitGet(MV_U32* regOff, MV_U32* data); -+/* Board devices API managments */ -+MV_32 mvBoardGetDevicesNumber(MV_BOARD_DEV_CLASS devClass); -+MV_32 mvBoardGetDeviceBaseAddr(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); -+MV_32 mvBoardGetDeviceBusWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); -+MV_32 mvBoardGetDeviceWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); -+MV_32 mvBoardGetDeviceWinSize(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); -+MV_U32 boardGetDevCSNum(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); -+ -+/* Gpio Pin Connections API */ -+MV_32 mvBoardUSBVbusGpioPinGet(int devId); -+MV_32 mvBoardUSBVbusEnGpioPinGet(int devId); -+MV_U32 mvBoardPexBridgeIntPinGet(MV_U32 devNum, MV_U32 intPin); -+ -+MV_32 mvBoardResetGpioPinGet(MV_VOID); -+MV_32 mvBoardRTCGpioPinGet(MV_VOID); -+MV_32 mvBoardGpioIntMaskLowGet(MV_VOID); -+MV_32 mvBoardGpioIntMaskHighGet(MV_VOID); -+MV_32 mvBoardSlicGpioPinGet(MV_U32 slicNum); -+ -+MV_32 mvBoardSDIOGpioPinGet(MV_VOID); -+MV_STATUS mvBoardSDioWPControl(MV_BOOL mode); -+MV_32 mvBoarGpioPinNumGet(MV_BOARD_GPP_CLASS class, MV_U32 index); -+ -+MV_32 mvBoardNandWidthGet(void); -+MV_STATUS mvBoardFanPowerControl(MV_BOOL mode); -+MV_STATUS mvBoardHDDPowerControl(MV_BOOL mode); -+#endif /* __INCmvBoardEnvLibh */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,848 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#include "mvCommon.h" -+#include "mvBoardEnvLib.h" -+#include "mvBoardEnvSpec.h" -+#include "twsi/mvTwsi.h" -+ -+#define DB_88F6281A_BOARD_PCI_IF_NUM 0x0 -+#define DB_88F6281A_BOARD_TWSI_DEF_NUM 0x7 -+#define DB_88F6281A_BOARD_MAC_INFO_NUM 0x2 -+#define DB_88F6281A_BOARD_GPP_INFO_NUM 0x3 -+#define DB_88F6281A_BOARD_MPP_CONFIG_NUM 0x1 -+#define DB_88F6281A_BOARD_MPP_GROUP_TYPE_NUM 0x1 -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ #define DB_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1 -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ #define DB_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x2 -+#else -+ #define DB_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1 -+#endif -+#define DB_88F6281A_BOARD_DEBUG_LED_NUM 0x0 -+ -+ -+MV_BOARD_TWSI_INFO db88f6281AInfoBoardTwsiDev[] = -+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ -+ { -+ {BOARD_DEV_TWSI_EXP, 0x20, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_EXP, 0x21, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_SATR, 0x4D, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_SATR, 0x4E, ADDR7_BIT}, -+ {BOARD_TWSI_AUDIO_DEC, 0x4A, ADDR7_BIT} -+ }; -+ -+MV_BOARD_MAC_INFO db88f6281AInfoBoardMacInfo[] = -+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ -+ { -+ {BOARD_MAC_SPEED_AUTO, 0x8}, -+ {BOARD_MAC_SPEED_AUTO, 0x9} -+ }; -+ -+MV_BOARD_MPP_TYPE_INFO db88f6281AInfoBoardMppTypeInfo[] = -+ /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, -+ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ -+ {{MV_BOARD_AUTO, MV_BOARD_AUTO} -+ }; -+ -+MV_BOARD_GPP_INFO db88f6281AInfoBoardGppInfo[] = -+ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ -+ { -+ {BOARD_GPP_TSU_DIRCTION, 33} -+ /*muxed with TDM/Audio module via IOexpender -+ {BOARD_GPP_SDIO_DETECT, 38}, -+ {BOARD_GPP_USB_VBUS, 49}*/ -+ }; -+ -+MV_DEV_CS_INFO db88f6281AInfoBoardDeCsInfo[] = -+ /*{deviceCS, params, devType, devWidth}*/ -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ { -+ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ -+ {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ -+ }; -+#else -+ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ -+#endif -+ -+MV_BOARD_MPP_INFO db88f6281AInfoBoardMppConfigValue[] = -+ {{{ -+ DB_88F6281A_MPP0_7, -+ DB_88F6281A_MPP8_15, -+ DB_88F6281A_MPP16_23, -+ DB_88F6281A_MPP24_31, -+ DB_88F6281A_MPP32_39, -+ DB_88F6281A_MPP40_47, -+ DB_88F6281A_MPP48_55 -+ }}}; -+ -+ -+MV_BOARD_INFO db88f6281AInfo = { -+ "DB-88F6281A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ -+ DB_88F6281A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ -+ db88f6281AInfoBoardMppTypeInfo, -+ DB_88F6281A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ db88f6281AInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ 0, /* intsGppMaskHigh */ -+ DB_88F6281A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ db88f6281AInfoBoardDeCsInfo, -+ DB_88F6281A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ db88f6281AInfoBoardTwsiDev, -+ DB_88F6281A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ db88f6281AInfoBoardMacInfo, -+ DB_88F6281A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ db88f6281AInfoBoardGppInfo, -+ DB_88F6281A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ NULL, -+ 0, /* ledsPolarity */ -+ DB_88F6281A_OE_LOW, /* gppOutEnLow */ -+ DB_88F6281A_OE_HIGH, /* gppOutEnHigh */ -+ DB_88F6281A_OE_VAL_LOW, /* gppOutValLow */ -+ DB_88F6281A_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ BIT6, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+ -+#define RD_88F6281A_BOARD_PCI_IF_NUM 0x0 -+#define RD_88F6281A_BOARD_TWSI_DEF_NUM 0x2 -+#define RD_88F6281A_BOARD_MAC_INFO_NUM 0x2 -+#define RD_88F6281A_BOARD_GPP_INFO_NUM 0x5 -+#define RD_88F6281A_BOARD_MPP_GROUP_TYPE_NUM 0x1 -+#define RD_88F6281A_BOARD_MPP_CONFIG_NUM 0x1 -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ #define RD_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1 -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ #define RD_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x2 -+#else -+ #define RD_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1 -+#endif -+#define RD_88F6281A_BOARD_DEBUG_LED_NUM 0x0 -+ -+MV_BOARD_MAC_INFO rd88f6281AInfoBoardMacInfo[] = -+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ -+ {{BOARD_MAC_SPEED_1000M, 0xa}, -+ {BOARD_MAC_SPEED_AUTO, 0xb} -+ }; -+ -+MV_BOARD_SWITCH_INFO rd88f6281AInfoBoardSwitchInfo[] = -+ /* MV_32 linkStatusIrq, {MV_32 qdPort0, MV_32 qdPort1, MV_32 qdPort2, MV_32 qdPort3, MV_32 qdPort4}, -+ MV_32 qdCpuPort, MV_32 smiScanMode, MV_32 switchOnPort} */ -+ {{38, {0, 1, 2, 3, -1}, 5, 2, 0}, -+ {-1, {-1}, -1, -1, -1}}; -+ -+MV_BOARD_TWSI_INFO rd88f6281AInfoBoardTwsiDev[] = -+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ -+ { -+ {BOARD_DEV_TWSI_EXP, 0xFF, ADDR7_BIT}, /* dummy entry to align with modules indexes */ -+ {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT} -+ }; -+ -+MV_BOARD_MPP_TYPE_INFO rd88f6281AInfoBoardMppTypeInfo[] = -+ {{MV_BOARD_RGMII, MV_BOARD_TDM} -+ }; -+ -+MV_DEV_CS_INFO rd88f6281AInfoBoardDeCsInfo[] = -+ /*{deviceCS, params, devType, devWidth}*/ -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ { -+ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ -+ {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ -+ }; -+#else -+ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ -+#endif -+ -+MV_BOARD_GPP_INFO rd88f6281AInfoBoardGppInfo[] = -+ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ -+ {{BOARD_GPP_SDIO_DETECT, 28}, -+ {BOARD_GPP_USB_OC, 29}, -+ {BOARD_GPP_WPS_BUTTON, 35}, -+ {BOARD_GPP_MV_SWITCH, 38}, -+ {BOARD_GPP_USB_VBUS, 49} -+ }; -+ -+MV_BOARD_MPP_INFO rd88f6281AInfoBoardMppConfigValue[] = -+ {{{ -+ RD_88F6281A_MPP0_7, -+ RD_88F6281A_MPP8_15, -+ RD_88F6281A_MPP16_23, -+ RD_88F6281A_MPP24_31, -+ RD_88F6281A_MPP32_39, -+ RD_88F6281A_MPP40_47, -+ RD_88F6281A_MPP48_55 -+ }}}; -+ -+MV_BOARD_INFO rd88f6281AInfo = { -+ "RD-88F6281A", /* boardName[MAX_BOARD_NAME_LEN] */ -+ RD_88F6281A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ -+ rd88f6281AInfoBoardMppTypeInfo, -+ RD_88F6281A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ rd88f6281AInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ (1 << 3), /* intsGppMaskHigh */ -+ RD_88F6281A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ rd88f6281AInfoBoardDeCsInfo, -+ RD_88F6281A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ rd88f6281AInfoBoardTwsiDev, -+ RD_88F6281A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ rd88f6281AInfoBoardMacInfo, -+ RD_88F6281A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ rd88f6281AInfoBoardGppInfo, -+ RD_88F6281A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ NULL, -+ 0, /* ledsPolarity */ -+ RD_88F6281A_OE_LOW, /* gppOutEnLow */ -+ RD_88F6281A_OE_HIGH, /* gppOutEnHigh */ -+ RD_88F6281A_OE_VAL_LOW, /* gppOutValLow */ -+ RD_88F6281A_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ BIT6, /* gppPolarityValHigh */ -+ rd88f6281AInfoBoardSwitchInfo /* pSwitchInfo */ -+}; -+ -+ -+#define DB_88F6192A_BOARD_PCI_IF_NUM 0x0 -+#define DB_88F6192A_BOARD_TWSI_DEF_NUM 0x7 -+#define DB_88F6192A_BOARD_MAC_INFO_NUM 0x2 -+#define DB_88F6192A_BOARD_GPP_INFO_NUM 0x3 -+#define DB_88F6192A_BOARD_MPP_GROUP_TYPE_NUM 0x1 -+#define DB_88F6192A_BOARD_MPP_CONFIG_NUM 0x1 -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ #define DB_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x1 -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ #define DB_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x2 -+#else -+ #define DB_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x1 -+#endif -+#define DB_88F6192A_BOARD_DEBUG_LED_NUM 0x0 -+ -+MV_BOARD_TWSI_INFO db88f6192AInfoBoardTwsiDev[] = -+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ -+ { -+ {BOARD_DEV_TWSI_EXP, 0x20, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_EXP, 0x21, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_SATR, 0x4D, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_SATR, 0x4E, ADDR7_BIT}, -+ {BOARD_TWSI_AUDIO_DEC, 0x4A, ADDR7_BIT} -+ }; -+ -+MV_BOARD_MAC_INFO db88f6192AInfoBoardMacInfo[] = -+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ -+ { -+ {BOARD_MAC_SPEED_AUTO, 0x8}, -+ {BOARD_MAC_SPEED_AUTO, 0x9} -+ }; -+ -+MV_BOARD_MPP_TYPE_INFO db88f6192AInfoBoardMppTypeInfo[] = -+ /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, -+ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ -+ {{MV_BOARD_AUTO, MV_BOARD_OTHER} -+ }; -+ -+MV_DEV_CS_INFO db88f6192AInfoBoardDeCsInfo[] = -+ /*{deviceCS, params, devType, devWidth}*/ -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ { -+ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ -+ {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ -+ }; -+#else -+ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ -+#endif -+ -+MV_BOARD_GPP_INFO db88f6192AInfoBoardGppInfo[] = -+ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ -+ { -+ {BOARD_GPP_SDIO_WP, 20}, -+ {BOARD_GPP_USB_VBUS, 22}, -+ {BOARD_GPP_SDIO_DETECT, 23}, -+ }; -+ -+MV_BOARD_MPP_INFO db88f6192AInfoBoardMppConfigValue[] = -+ {{{ -+ DB_88F6192A_MPP0_7, -+ DB_88F6192A_MPP8_15, -+ DB_88F6192A_MPP16_23, -+ DB_88F6192A_MPP24_31, -+ DB_88F6192A_MPP32_35 -+ }}}; -+ -+MV_BOARD_INFO db88f6192AInfo = { -+ "DB-88F6192A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ -+ DB_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ -+ db88f6192AInfoBoardMppTypeInfo, -+ DB_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ db88f6192AInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ (1 << 3), /* intsGppMaskHigh */ -+ DB_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ db88f6192AInfoBoardDeCsInfo, -+ DB_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ db88f6192AInfoBoardTwsiDev, -+ DB_88F6192A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ db88f6192AInfoBoardMacInfo, -+ DB_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ db88f6192AInfoBoardGppInfo, -+ DB_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ NULL, -+ 0, /* ledsPolarity */ -+ DB_88F6192A_OE_LOW, /* gppOutEnLow */ -+ DB_88F6192A_OE_HIGH, /* gppOutEnHigh */ -+ DB_88F6192A_OE_VAL_LOW, /* gppOutValLow */ -+ DB_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ 0, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+#define DB_88F6190A_BOARD_MAC_INFO_NUM 0x1 -+ -+MV_BOARD_INFO db88f6190AInfo = { -+ "DB-88F6190A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ -+ DB_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ -+ db88f6192AInfoBoardMppTypeInfo, -+ DB_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ db88f6192AInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ (1 << 3), /* intsGppMaskHigh */ -+ DB_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ db88f6192AInfoBoardDeCsInfo, -+ DB_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ db88f6192AInfoBoardTwsiDev, -+ DB_88F6190A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ db88f6192AInfoBoardMacInfo, -+ DB_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ db88f6192AInfoBoardGppInfo, -+ DB_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ NULL, -+ 0, /* ledsPolarity */ -+ DB_88F6192A_OE_LOW, /* gppOutEnLow */ -+ DB_88F6192A_OE_HIGH, /* gppOutEnHigh */ -+ DB_88F6192A_OE_VAL_LOW, /* gppOutValLow */ -+ DB_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ 0, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+#define RD_88F6192A_BOARD_PCI_IF_NUM 0x0 -+#define RD_88F6192A_BOARD_TWSI_DEF_NUM 0x0 -+#define RD_88F6192A_BOARD_MAC_INFO_NUM 0x1 -+#define RD_88F6192A_BOARD_GPP_INFO_NUM 0xE -+#define RD_88F6192A_BOARD_MPP_GROUP_TYPE_NUM 0x1 -+#define RD_88F6192A_BOARD_MPP_CONFIG_NUM 0x1 -+#define RD_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x1 -+#define RD_88F6192A_BOARD_DEBUG_LED_NUM 0x3 -+ -+MV_U8 rd88f6192AInfoBoardDebugLedIf[] = -+ {17, 28, 29}; -+ -+MV_BOARD_MAC_INFO rd88f6192AInfoBoardMacInfo[] = -+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ -+ {{BOARD_MAC_SPEED_AUTO, 0x8} -+ }; -+ -+MV_BOARD_MPP_TYPE_INFO rd88f6192AInfoBoardMppTypeInfo[] = -+ /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, -+ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ -+ {{MV_BOARD_OTHER, MV_BOARD_OTHER} -+ }; -+ -+MV_DEV_CS_INFO rd88f6192AInfoBoardDeCsInfo[] = -+ /*{deviceCS, params, devType, devWidth}*/ -+ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ -+ -+MV_BOARD_GPP_INFO rd88f6192AInfoBoardGppInfo[] = -+ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ -+ { -+ {BOARD_GPP_USB_VBUS_EN, 10}, -+ {BOARD_GPP_USB_HOST_DEVICE, 11}, -+ {BOARD_GPP_RESET, 14}, -+ {BOARD_GPP_POWER_ON_LED, 15}, -+ {BOARD_GPP_HDD_POWER, 16}, -+ {BOARD_GPP_WPS_BUTTON, 24}, -+ {BOARD_GPP_TS_BUTTON_C, 25}, -+ {BOARD_GPP_USB_VBUS, 26}, -+ {BOARD_GPP_USB_OC, 27}, -+ {BOARD_GPP_TS_BUTTON_U, 30}, -+ {BOARD_GPP_TS_BUTTON_R, 31}, -+ {BOARD_GPP_TS_BUTTON_L, 32}, -+ {BOARD_GPP_TS_BUTTON_D, 34}, -+ {BOARD_GPP_FAN_POWER, 35} -+ }; -+ -+MV_BOARD_MPP_INFO rd88f6192AInfoBoardMppConfigValue[] = -+ {{{ -+ RD_88F6192A_MPP0_7, -+ RD_88F6192A_MPP8_15, -+ RD_88F6192A_MPP16_23, -+ RD_88F6192A_MPP24_31, -+ RD_88F6192A_MPP32_35 -+ }}}; -+ -+MV_BOARD_INFO rd88f6192AInfo = { -+ "RD-88F6192A-NAS", /* boardName[MAX_BOARD_NAME_LEN] */ -+ RD_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ -+ rd88f6192AInfoBoardMppTypeInfo, -+ RD_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ rd88f6192AInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ (1 << 3), /* intsGppMaskHigh */ -+ RD_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ rd88f6192AInfoBoardDeCsInfo, -+ RD_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ NULL, -+ RD_88F6192A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ rd88f6192AInfoBoardMacInfo, -+ RD_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ rd88f6192AInfoBoardGppInfo, -+ RD_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ rd88f6192AInfoBoardDebugLedIf, -+ 0, /* ledsPolarity */ -+ RD_88F6192A_OE_LOW, /* gppOutEnLow */ -+ RD_88F6192A_OE_HIGH, /* gppOutEnHigh */ -+ RD_88F6192A_OE_VAL_LOW, /* gppOutValLow */ -+ RD_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ 0, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+MV_BOARD_INFO rd88f6190AInfo = { -+ "RD-88F6190A-NAS", /* boardName[MAX_BOARD_NAME_LEN] */ -+ RD_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ -+ rd88f6192AInfoBoardMppTypeInfo, -+ RD_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ rd88f6192AInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ (1 << 3), /* intsGppMaskHigh */ -+ RD_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ rd88f6192AInfoBoardDeCsInfo, -+ RD_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ NULL, -+ RD_88F6192A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ rd88f6192AInfoBoardMacInfo, -+ RD_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ rd88f6192AInfoBoardGppInfo, -+ RD_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ rd88f6192AInfoBoardDebugLedIf, -+ 0, /* ledsPolarity */ -+ RD_88F6192A_OE_LOW, /* gppOutEnLow */ -+ RD_88F6192A_OE_HIGH, /* gppOutEnHigh */ -+ RD_88F6192A_OE_VAL_LOW, /* gppOutValLow */ -+ RD_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ 0, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+#define DB_88F6180A_BOARD_PCI_IF_NUM 0x0 -+#define DB_88F6180A_BOARD_TWSI_DEF_NUM 0x5 -+#define DB_88F6180A_BOARD_MAC_INFO_NUM 0x1 -+#define DB_88F6180A_BOARD_GPP_INFO_NUM 0x0 -+#define DB_88F6180A_BOARD_MPP_GROUP_TYPE_NUM 0x2 -+#define DB_88F6180A_BOARD_MPP_CONFIG_NUM 0x1 -+#define DB_88F6180A_BOARD_DEVICE_CONFIG_NUM 0x1 -+#define DB_88F6180A_BOARD_DEBUG_LED_NUM 0x0 -+ -+MV_BOARD_TWSI_INFO db88f6180AInfoBoardTwsiDev[] = -+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ -+ { -+ {BOARD_DEV_TWSI_EXP, 0x20, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_EXP, 0x21, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT}, -+ {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, -+ {BOARD_TWSI_AUDIO_DEC, 0x4A, ADDR7_BIT} -+ }; -+ -+MV_BOARD_MAC_INFO db88f6180AInfoBoardMacInfo[] = -+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ -+ {{BOARD_MAC_SPEED_AUTO, 0x8} -+ }; -+ -+MV_BOARD_GPP_INFO db88f6180AInfoBoardGppInfo[] = -+ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ -+ { -+ /* Muxed with TDM/Audio module via IOexpender -+ {BOARD_GPP_USB_VBUS, 6} */ -+ }; -+ -+MV_BOARD_MPP_TYPE_INFO db88f6180AInfoBoardMppTypeInfo[] = -+ /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, -+ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ -+ {{MV_BOARD_OTHER, MV_BOARD_AUTO} -+ }; -+ -+MV_DEV_CS_INFO db88f6180AInfoBoardDeCsInfo[] = -+ /*{deviceCS, params, devType, devWidth}*/ -+#if defined(MV_NAND_BOOT) -+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ -+#else -+ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ -+#endif -+ -+MV_BOARD_MPP_INFO db88f6180AInfoBoardMppConfigValue[] = -+ {{{ -+ DB_88F6180A_MPP0_7, -+ DB_88F6180A_MPP8_15, -+ DB_88F6180A_MPP16_23, -+ DB_88F6180A_MPP24_31, -+ DB_88F6180A_MPP32_39, -+ DB_88F6180A_MPP40_44 -+ }}}; -+ -+MV_BOARD_INFO db88f6180AInfo = { -+ "DB-88F6180A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ -+ DB_88F6180A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ -+ db88f6180AInfoBoardMppTypeInfo, -+ DB_88F6180A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ db88f6180AInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ 0, /* intsGppMaskHigh */ -+ DB_88F6180A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ db88f6180AInfoBoardDeCsInfo, -+ DB_88F6180A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ db88f6180AInfoBoardTwsiDev, -+ DB_88F6180A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ db88f6180AInfoBoardMacInfo, -+ DB_88F6180A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ NULL, -+ DB_88F6180A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ NULL, -+ 0, /* ledsPolarity */ -+ DB_88F6180A_OE_LOW, /* gppOutEnLow */ -+ DB_88F6180A_OE_HIGH, /* gppOutEnHigh */ -+ DB_88F6180A_OE_VAL_LOW, /* gppOutValLow */ -+ DB_88F6180A_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ 0, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+ -+#define RD_88F6281A_PCAC_BOARD_PCI_IF_NUM 0x0 -+#define RD_88F6281A_PCAC_BOARD_TWSI_DEF_NUM 0x1 -+#define RD_88F6281A_PCAC_BOARD_MAC_INFO_NUM 0x1 -+#define RD_88F6281A_PCAC_BOARD_GPP_INFO_NUM 0x0 -+#define RD_88F6281A_PCAC_BOARD_MPP_GROUP_TYPE_NUM 0x1 -+#define RD_88F6281A_PCAC_BOARD_MPP_CONFIG_NUM 0x1 -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ #define RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM 0x1 -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ #define RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM 0x2 -+#else -+ #define RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM 0x1 -+#endif -+#define RD_88F6281A_PCAC_BOARD_DEBUG_LED_NUM 0x4 -+ -+MV_U8 rd88f6281APcacInfoBoardDebugLedIf[] = -+ {38, 39, 40, 41}; -+ -+MV_BOARD_MAC_INFO rd88f6281APcacInfoBoardMacInfo[] = -+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ -+ {{BOARD_MAC_SPEED_AUTO, 0x8} -+ }; -+ -+MV_BOARD_TWSI_INFO rd88f6281APcacInfoBoardTwsiDev[] = -+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ -+ { -+ {BOARD_TWSI_OTHER, 0xa7, ADDR7_BIT} -+ }; -+ -+MV_BOARD_MPP_TYPE_INFO rd88f6281APcacInfoBoardMppTypeInfo[] = -+ {{MV_BOARD_OTHER, MV_BOARD_OTHER} -+ }; -+ -+MV_DEV_CS_INFO rd88f6281APcacInfoBoardDeCsInfo[] = -+ /*{deviceCS, params, devType, devWidth}*/ -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ { -+ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ -+ {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ -+ }; -+#else -+ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ -+#endif -+ -+MV_BOARD_MPP_INFO rd88f6281APcacInfoBoardMppConfigValue[] = -+ {{{ -+ RD_88F6281A_PCAC_MPP0_7, -+ RD_88F6281A_PCAC_MPP8_15, -+ RD_88F6281A_PCAC_MPP16_23, -+ RD_88F6281A_PCAC_MPP24_31, -+ RD_88F6281A_PCAC_MPP32_39, -+ RD_88F6281A_PCAC_MPP40_47, -+ RD_88F6281A_PCAC_MPP48_55 -+ }}}; -+ -+MV_BOARD_INFO rd88f6281APcacInfo = { -+ "RD-88F6281A-PCAC", /* boardName[MAX_BOARD_NAME_LEN] */ -+ RD_88F6281A_PCAC_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ -+ rd88f6281APcacInfoBoardMppTypeInfo, -+ RD_88F6281A_PCAC_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ rd88f6281APcacInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ (1 << 3), /* intsGppMaskHigh */ -+ RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ rd88f6281APcacInfoBoardDeCsInfo, -+ RD_88F6281A_PCAC_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ rd88f6281APcacInfoBoardTwsiDev, -+ RD_88F6281A_PCAC_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ rd88f6281APcacInfoBoardMacInfo, -+ RD_88F6281A_PCAC_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ 0, -+ RD_88F6281A_PCAC_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ NULL, -+ 0, /* ledsPolarity */ -+ RD_88F6281A_PCAC_OE_LOW, /* gppOutEnLow */ -+ RD_88F6281A_PCAC_OE_HIGH, /* gppOutEnHigh */ -+ RD_88F6281A_PCAC_OE_VAL_LOW, /* gppOutValLow */ -+ RD_88F6281A_PCAC_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ 0, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+ -+/* 6281 Sheeva Plug*/ -+ -+#define SHEEVA_PLUG_BOARD_PCI_IF_NUM 0x0 -+#define SHEEVA_PLUG_BOARD_TWSI_DEF_NUM 0x0 -+#define SHEEVA_PLUG_BOARD_MAC_INFO_NUM 0x1 -+#define SHEEVA_PLUG_BOARD_GPP_INFO_NUM 0x0 -+#define SHEEVA_PLUG_BOARD_MPP_GROUP_TYPE_NUN 0x1 -+#define SHEEVA_PLUG_BOARD_MPP_CONFIG_NUM 0x1 -+#define SHEEVA_PLUG_BOARD_DEVICE_CONFIG_NUM 0x1 -+#define SHEEVA_PLUG_BOARD_DEBUG_LED_NUM 0x1 -+ -+MV_U8 sheevaPlugInfoBoardDebugLedIf[] = -+ {49}; -+ -+MV_BOARD_MAC_INFO sheevaPlugInfoBoardMacInfo[] = -+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ -+ {{BOARD_MAC_SPEED_AUTO, 0x0}}; -+ -+MV_BOARD_TWSI_INFO sheevaPlugInfoBoardTwsiDev[] = -+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ -+ {{BOARD_TWSI_OTHER, 0x0, ADDR7_BIT}}; -+ -+MV_BOARD_MPP_TYPE_INFO sheevaPlugInfoBoardMppTypeInfo[] = -+ {{MV_BOARD_OTHER, MV_BOARD_OTHER} -+ }; -+ -+MV_DEV_CS_INFO sheevaPlugInfoBoardDeCsInfo[] = -+ /*{deviceCS, params, devType, devWidth}*/ -+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ -+ -+MV_BOARD_MPP_INFO sheevaPlugInfoBoardMppConfigValue[] = -+ {{{ -+ RD_SHEEVA_PLUG_MPP0_7, -+ RD_SHEEVA_PLUG_MPP8_15, -+ RD_SHEEVA_PLUG_MPP16_23, -+ RD_SHEEVA_PLUG_MPP24_31, -+ RD_SHEEVA_PLUG_MPP32_39, -+ RD_SHEEVA_PLUG_MPP40_47, -+ RD_SHEEVA_PLUG_MPP48_55 -+ }}}; -+ -+MV_BOARD_INFO sheevaPlugInfo = { -+ "SHEEVA PLUG", /* boardName[MAX_BOARD_NAME_LEN] */ -+ SHEEVA_PLUG_BOARD_MPP_GROUP_TYPE_NUN, /* numBoardMppGroupType */ -+ sheevaPlugInfoBoardMppTypeInfo, -+ SHEEVA_PLUG_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ sheevaPlugInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ 0, /* intsGppMaskHigh */ -+ SHEEVA_PLUG_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ sheevaPlugInfoBoardDeCsInfo, -+ SHEEVA_PLUG_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ sheevaPlugInfoBoardTwsiDev, -+ SHEEVA_PLUG_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ sheevaPlugInfoBoardMacInfo, -+ SHEEVA_PLUG_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ 0, -+ SHEEVA_PLUG_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ sheevaPlugInfoBoardDebugLedIf, -+ 0, /* ledsPolarity */ -+ RD_SHEEVA_PLUG_OE_LOW, /* gppOutEnLow */ -+ RD_SHEEVA_PLUG_OE_HIGH, /* gppOutEnHigh */ -+ RD_SHEEVA_PLUG_OE_VAL_LOW, /* gppOutValLow */ -+ RD_SHEEVA_PLUG_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ 0, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+/* Customer specific board place holder*/ -+ -+#define DB_CUSTOMER_BOARD_PCI_IF_NUM 0x0 -+#define DB_CUSTOMER_BOARD_TWSI_DEF_NUM 0x0 -+#define DB_CUSTOMER_BOARD_MAC_INFO_NUM 0x0 -+#define DB_CUSTOMER_BOARD_GPP_INFO_NUM 0x0 -+#define DB_CUSTOMER_BOARD_MPP_GROUP_TYPE_NUN 0x0 -+#define DB_CUSTOMER_BOARD_MPP_CONFIG_NUM 0x0 -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ #define DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM 0x0 -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ #define DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM 0x0 -+#else -+ #define DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM 0x0 -+#endif -+#define DB_CUSTOMER_BOARD_DEBUG_LED_NUM 0x0 -+ -+MV_U8 dbCustomerInfoBoardDebugLedIf[] = -+ {0}; -+ -+MV_BOARD_MAC_INFO dbCustomerInfoBoardMacInfo[] = -+ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ -+ {{BOARD_MAC_SPEED_AUTO, 0x0}}; -+ -+MV_BOARD_TWSI_INFO dbCustomerInfoBoardTwsiDev[] = -+ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ -+ {{BOARD_TWSI_OTHER, 0x0, ADDR7_BIT}}; -+ -+MV_BOARD_MPP_TYPE_INFO dbCustomerInfoBoardMppTypeInfo[] = -+ {{MV_BOARD_OTHER, MV_BOARD_OTHER} -+ }; -+ -+MV_DEV_CS_INFO dbCustomerInfoBoardDeCsInfo[] = -+ /*{deviceCS, params, devType, devWidth}*/ -+#if defined(MV_NAND) && defined(MV_NAND_BOOT) -+ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ -+#elif defined(MV_NAND) && defined(MV_SPI_BOOT) -+ { -+ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ -+ {2, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ -+ }; -+#else -+ {{2, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ -+#endif -+ -+MV_BOARD_MPP_INFO dbCustomerInfoBoardMppConfigValue[] = -+ {{{ -+ DB_CUSTOMER_MPP0_7, -+ DB_CUSTOMER_MPP8_15, -+ DB_CUSTOMER_MPP16_23, -+ DB_CUSTOMER_MPP24_31, -+ DB_CUSTOMER_MPP32_39, -+ DB_CUSTOMER_MPP40_47, -+ DB_CUSTOMER_MPP48_55 -+ }}}; -+ -+MV_BOARD_INFO dbCustomerInfo = { -+ "DB-CUSTOMER", /* boardName[MAX_BOARD_NAME_LEN] */ -+ DB_CUSTOMER_BOARD_MPP_GROUP_TYPE_NUN, /* numBoardMppGroupType */ -+ dbCustomerInfoBoardMppTypeInfo, -+ DB_CUSTOMER_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ -+ dbCustomerInfoBoardMppConfigValue, -+ 0, /* intsGppMaskLow */ -+ 0, /* intsGppMaskHigh */ -+ DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ -+ dbCustomerInfoBoardDeCsInfo, -+ DB_CUSTOMER_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ -+ dbCustomerInfoBoardTwsiDev, -+ DB_CUSTOMER_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ -+ dbCustomerInfoBoardMacInfo, -+ DB_CUSTOMER_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ -+ 0, -+ DB_CUSTOMER_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ -+ NULL, -+ 0, /* ledsPolarity */ -+ DB_CUSTOMER_OE_LOW, /* gppOutEnLow */ -+ DB_CUSTOMER_OE_HIGH, /* gppOutEnHigh */ -+ DB_CUSTOMER_OE_VAL_LOW, /* gppOutValLow */ -+ DB_CUSTOMER_OE_VAL_HIGH, /* gppOutValHigh */ -+ 0, /* gppPolarityValLow */ -+ 0, /* gppPolarityValHigh */ -+ NULL /* pSwitchInfo */ -+}; -+ -+MV_BOARD_INFO* boardInfoTbl[] = { -+ &db88f6281AInfo, -+ &rd88f6281AInfo, -+ &db88f6192AInfo, -+ &rd88f6192AInfo, -+ &db88f6180AInfo, -+ &db88f6190AInfo, -+ &rd88f6190AInfo, -+ &rd88f6281APcacInfo, -+ &dbCustomerInfo, -+ &sheevaPlugInfo -+ }; -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,262 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvBoardEnvSpech -+#define __INCmvBoardEnvSpech -+ -+#include "mvSysHwConfig.h" -+ -+ -+/* For future use */ -+#define BD_ID_DATA_START_OFFS 0x0 -+#define BD_DETECT_SEQ_OFFS 0x0 -+#define BD_SYS_NUM_OFFS 0x4 -+#define BD_NAME_OFFS 0x8 -+ -+/* I2C bus addresses */ -+#define MV_BOARD_CTRL_I2C_ADDR 0x0 /* Controller slave addr */ -+#define MV_BOARD_CTRL_I2C_ADDR_TYPE ADDR7_BIT -+#define MV_BOARD_DIMM0_I2C_ADDR 0x56 -+#define MV_BOARD_DIMM0_I2C_ADDR_TYPE ADDR7_BIT -+#define MV_BOARD_DIMM1_I2C_ADDR 0x54 -+#define MV_BOARD_DIMM1_I2C_ADDR_TYPE ADDR7_BIT -+#define MV_BOARD_EEPROM_I2C_ADDR 0x51 -+#define MV_BOARD_EEPROM_I2C_ADDR_TYPE ADDR7_BIT -+#define MV_BOARD_MAIN_EEPROM_I2C_ADDR 0x50 -+#define MV_BOARD_MAIN_EEPROM_I2C_ADDR_TYPE ADDR7_BIT -+#define MV_BOARD_MUX_I2C_ADDR_ENTRY 0x2 -+#define MV_BOARD_DIMM_I2C_CHANNEL 0x0 -+ -+#define BOOT_FLASH_INDEX 0 -+#define MAIN_FLASH_INDEX 1 -+ -+#define BOARD_ETH_START_PORT_NUM 0 -+ -+/* Supported clocks */ -+#define MV_BOARD_TCLK_100MHZ 100000000 -+#define MV_BOARD_TCLK_125MHZ 125000000 -+#define MV_BOARD_TCLK_133MHZ 133333333 -+#define MV_BOARD_TCLK_150MHZ 150000000 -+#define MV_BOARD_TCLK_166MHZ 166666667 -+#define MV_BOARD_TCLK_200MHZ 200000000 -+ -+#define MV_BOARD_SYSCLK_100MHZ 100000000 -+#define MV_BOARD_SYSCLK_125MHZ 125000000 -+#define MV_BOARD_SYSCLK_133MHZ 133333333 -+#define MV_BOARD_SYSCLK_150MHZ 150000000 -+#define MV_BOARD_SYSCLK_166MHZ 166666667 -+#define MV_BOARD_SYSCLK_200MHZ 200000000 -+#define MV_BOARD_SYSCLK_233MHZ 233333333 -+#define MV_BOARD_SYSCLK_250MHZ 250000000 -+#define MV_BOARD_SYSCLK_267MHZ 266666667 -+#define MV_BOARD_SYSCLK_300MHZ 300000000 -+#define MV_BOARD_SYSCLK_333MHZ 333333334 -+#define MV_BOARD_SYSCLK_400MHZ 400000000 -+ -+#define MV_BOARD_REFCLK_25MHZ 25000000 -+ -+/* Board specific */ -+/* =============================== */ -+ -+/* boards ID numbers */ -+ -+#define BOARD_ID_BASE 0x0 -+ -+/* New board ID numbers */ -+#define DB_88F6281A_BP_ID (BOARD_ID_BASE) -+#define DB_88F6281_BP_MLL_ID 1680 -+#define RD_88F6281A_ID (BOARD_ID_BASE+0x1) -+#define RD_88F6281_MLL_ID 1682 -+#define DB_88F6192A_BP_ID (BOARD_ID_BASE+0x2) -+#define RD_88F6192A_ID (BOARD_ID_BASE+0x3) -+#define RD_88F6192_MLL_ID 1681 -+#define DB_88F6180A_BP_ID (BOARD_ID_BASE+0x4) -+#define DB_88F6190A_BP_ID (BOARD_ID_BASE+0x5) -+#define RD_88F6190A_ID (BOARD_ID_BASE+0x6) -+#define RD_88F6281A_PCAC_ID (BOARD_ID_BASE+0x7) -+#define DB_CUSTOMER_ID (BOARD_ID_BASE+0x8) -+#define SHEEVA_PLUG_ID (BOARD_ID_BASE+0x9) -+#define MV_MAX_BOARD_ID (SHEEVA_PLUG_ID + 1) -+ -+/* DB-88F6281A-BP */ -+#if defined(MV_NAND) -+ #define DB_88F6281A_MPP0_7 0x21111111 -+#else -+ #define DB_88F6281A_MPP0_7 0x21112220 -+#endif -+#define DB_88F6281A_MPP8_15 0x11113311 -+#define DB_88F6281A_MPP16_23 0x00551111 -+#define DB_88F6281A_MPP24_31 0x00000000 -+#define DB_88F6281A_MPP32_39 0x00000000 -+#define DB_88F6281A_MPP40_47 0x00000000 -+#define DB_88F6281A_MPP48_55 0x00000000 -+#define DB_88F6281A_OE_LOW 0x0 -+#if defined(MV_TDM_5CHANNELS) -+ #define DB_88F6281A_OE_HIGH (BIT6) -+#else -+#define DB_88F6281A_OE_HIGH 0x0 -+#endif -+#define DB_88F6281A_OE_VAL_LOW 0x0 -+#define DB_88F6281A_OE_VAL_HIGH 0x0 -+ -+/* RD-88F6281A */ -+#if defined(MV_NAND) -+ #define RD_88F6281A_MPP0_7 0x21111111 -+#else -+ #define RD_88F6281A_MPP0_7 0x21112220 -+#endif -+#define RD_88F6281A_MPP8_15 0x11113311 -+#define RD_88F6281A_MPP16_23 0x33331111 -+#define RD_88F6281A_MPP24_31 0x33003333 -+#define RD_88F6281A_MPP32_39 0x20440533 -+#define RD_88F6281A_MPP40_47 0x22202222 -+#define RD_88F6281A_MPP48_55 0x00000002 -+#define RD_88F6281A_OE_LOW (BIT28 | BIT29) -+#define RD_88F6281A_OE_HIGH (BIT3 | BIT6 | BIT17) -+#define RD_88F6281A_OE_VAL_LOW 0x0 -+#define RD_88F6281A_OE_VAL_HIGH 0x0 -+ -+/* DB-88F6192A-BP */ -+#if defined(MV_NAND) -+ #define DB_88F6192A_MPP0_7 0x21111111 -+#else -+ #define DB_88F6192A_MPP0_7 0x21112220 -+#endif -+#define DB_88F6192A_MPP8_15 0x11113311 -+#define DB_88F6192A_MPP16_23 0x00501111 -+#define DB_88F6192A_MPP24_31 0x00000000 -+#define DB_88F6192A_MPP32_35 0x00000000 -+#define DB_88F6192A_OE_LOW (BIT22 | BIT23) -+#define DB_88F6192A_OE_HIGH 0x0 -+#define DB_88F6192A_OE_VAL_LOW 0x0 -+#define DB_88F6192A_OE_VAL_HIGH 0x0 -+ -+/* RD-88F6192A */ -+#define RD_88F6192A_MPP0_7 0x01222222 -+#define RD_88F6192A_MPP8_15 0x00000011 -+#define RD_88F6192A_MPP16_23 0x05550000 -+#define RD_88F6192A_MPP24_31 0x0 -+#define RD_88F6192A_MPP32_35 0x0 -+#define RD_88F6192A_OE_LOW (BIT11 | BIT14 | BIT24 | BIT25 | BIT26 | BIT27 | BIT30 | BIT31) -+#define RD_88F6192A_OE_HIGH (BIT0 | BIT2) -+#define RD_88F6192A_OE_VAL_LOW 0x18400 -+#define RD_88F6192A_OE_VAL_HIGH 0x8 -+ -+/* DB-88F6180A-BP */ -+#if defined(MV_NAND) -+ #define DB_88F6180A_MPP0_7 0x21111111 -+#else -+ #define DB_88F6180A_MPP0_7 0x01112222 -+#endif -+#define DB_88F6180A_MPP8_15 0x11113311 -+#define DB_88F6180A_MPP16_23 0x00001111 -+#define DB_88F6180A_MPP24_31 0x0 -+#define DB_88F6180A_MPP32_39 0x4444c000 -+#define DB_88F6180A_MPP40_44 0x00044444 -+#define DB_88F6180A_OE_LOW 0x0 -+#define DB_88F6180A_OE_HIGH 0x0 -+#define DB_88F6180A_OE_VAL_LOW 0x0 -+#define DB_88F6180A_OE_VAL_HIGH 0x0 -+ -+/* RD-88F6281A_PCAC */ -+#define RD_88F6281A_PCAC_MPP0_7 0x21111111 -+#define RD_88F6281A_PCAC_MPP8_15 0x00003311 -+#define RD_88F6281A_PCAC_MPP16_23 0x00001100 -+#define RD_88F6281A_PCAC_MPP24_31 0x00000000 -+#define RD_88F6281A_PCAC_MPP32_39 0x00000000 -+#define RD_88F6281A_PCAC_MPP40_47 0x00000000 -+#define RD_88F6281A_PCAC_MPP48_55 0x00000000 -+#define RD_88F6281A_PCAC_OE_LOW 0x0 -+#define RD_88F6281A_PCAC_OE_HIGH 0x0 -+#define RD_88F6281A_PCAC_OE_VAL_LOW 0x0 -+#define RD_88F6281A_PCAC_OE_VAL_HIGH 0x0 -+ -+/* SHEEVA PLUG */ -+#define RD_SHEEVA_PLUG_MPP0_7 0x01111111 -+#define RD_SHEEVA_PLUG_MPP8_15 0x11113322 -+#define RD_SHEEVA_PLUG_MPP16_23 0x00001111 -+#define RD_SHEEVA_PLUG_MPP24_31 0x00100000 -+#define RD_SHEEVA_PLUG_MPP32_39 0x00000000 -+#define RD_SHEEVA_PLUG_MPP40_47 0x00000000 -+#define RD_SHEEVA_PLUG_MPP48_55 0x00000000 -+#define RD_SHEEVA_PLUG_OE_LOW 0x0 -+#define RD_SHEEVA_PLUG_OE_HIGH 0x0 -+#define RD_SHEEVA_PLUG_OE_VAL_LOW (BIT29) -+#define RD_SHEEVA_PLUG_OE_VAL_HIGH ((~(BIT17 | BIT16 | BIT15)) | BIT14) -+ -+/* DB-CUSTOMER */ -+#define DB_CUSTOMER_MPP0_7 0x21111111 -+#define DB_CUSTOMER_MPP8_15 0x00003311 -+#define DB_CUSTOMER_MPP16_23 0x00001100 -+#define DB_CUSTOMER_MPP24_31 0x00000000 -+#define DB_CUSTOMER_MPP32_39 0x00000000 -+#define DB_CUSTOMER_MPP40_47 0x00000000 -+#define DB_CUSTOMER_MPP48_55 0x00000000 -+#define DB_CUSTOMER_OE_LOW 0x0 -+#define DB_CUSTOMER_OE_HIGH (~((BIT6) | (BIT7) | (BIT8) | (BIT9))) -+#define DB_CUSTOMER_OE_VAL_LOW 0x0 -+#define DB_CUSTOMER_OE_VAL_HIGH 0x0 -+ -+#endif /* __INCmvBoardEnvSpech */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,320 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#include "cpu/mvCpu.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvRegs.h" -+#include "ctrlEnv/sys/mvCpuIfRegs.h" -+ -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+/* locals */ -+ -+/******************************************************************************* -+* mvCpuPclkGet - Get the CPU pClk (pipe clock) -+* -+* DESCRIPTION: -+* This routine extract the CPU core clock. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit clock cycles in MHertz. -+* -+*******************************************************************************/ -+/* 6180 have different clk reset sampling */ -+ -+static MV_U32 mvCpu6180PclkGet(MV_VOID) -+{ -+ MV_U32 tmpPClkRate=0; -+ MV_CPU_ARM_CLK cpu6180_ddr_l2_CLK[] = MV_CPU6180_DDR_L2_CLCK_TBL; -+ -+ tmpPClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ tmpPClkRate = tmpPClkRate & MSAR_CPUCLCK_MASK_6180; -+ tmpPClkRate = tmpPClkRate >> MSAR_CPUCLCK_OFFS_6180; -+ -+ tmpPClkRate = cpu6180_ddr_l2_CLK[tmpPClkRate].cpuClk; -+ -+ return tmpPClkRate; -+} -+ -+ -+MV_U32 mvCpuPclkGet(MV_VOID) -+{ -+#if defined(PCLCK_AUTO_DETECT) -+ MV_U32 tmpPClkRate=0; -+ MV_U32 cpuCLK[] = MV_CPU_CLCK_TBL; -+ -+ if(mvCtrlModelGet() == MV_6180_DEV_ID) -+ return mvCpu6180PclkGet(); -+ -+ tmpPClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ tmpPClkRate = MSAR_CPUCLCK_EXTRACT(tmpPClkRate); -+ tmpPClkRate = cpuCLK[tmpPClkRate]; -+ -+ return tmpPClkRate; -+#else -+ return MV_DEFAULT_PCLK -+#endif -+} -+ -+/******************************************************************************* -+* mvCpuL2ClkGet - Get the CPU L2 (CPU bus clock) -+* -+* DESCRIPTION: -+* This routine extract the CPU L2 clock. -+* -+* RETURN: -+* 32bit clock cycles in Hertz. -+* -+*******************************************************************************/ -+static MV_U32 mvCpu6180L2ClkGet(MV_VOID) -+{ -+ MV_U32 L2ClkRate=0; -+ MV_CPU_ARM_CLK _cpu6180_ddr_l2_CLK[] = MV_CPU6180_DDR_L2_CLCK_TBL; -+ -+ L2ClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ L2ClkRate = L2ClkRate & MSAR_CPUCLCK_MASK_6180; -+ L2ClkRate = L2ClkRate >> MSAR_CPUCLCK_OFFS_6180; -+ -+ L2ClkRate = _cpu6180_ddr_l2_CLK[L2ClkRate].l2Clk; -+ -+ return L2ClkRate; -+ -+} -+ -+MV_U32 mvCpuL2ClkGet(MV_VOID) -+{ -+#ifdef L2CLK_AUTO_DETECT -+ MV_U32 L2ClkRate, tmp, pClkRate, indexL2Rtio; -+ MV_U32 L2Rtio[][2] = MV_L2_CLCK_RTIO_TBL; -+ -+ if(mvCtrlModelGet() == MV_6180_DEV_ID) -+ return mvCpu6180L2ClkGet(); -+ -+ pClkRate = mvCpuPclkGet(); -+ -+ tmp = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ indexL2Rtio = MSAR_L2CLCK_EXTRACT(tmp); -+ -+ L2ClkRate = ((pClkRate * L2Rtio[indexL2Rtio][1]) / L2Rtio[indexL2Rtio][0]); -+ -+ return L2ClkRate; -+#else -+ return MV_BOARD_DEFAULT_L2CLK; -+#endif -+} -+ -+ -+/******************************************************************************* -+* mvCpuNameGet - Get CPU name -+* -+* DESCRIPTION: -+* This function returns a string describing the CPU model and revision. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* pNameBuff - Buffer to contain board name string. Minimum size 32 chars. -+* -+* RETURN: -+* None. -+*******************************************************************************/ -+MV_VOID mvCpuNameGet(char *pNameBuff) -+{ -+ MV_U32 cpuModel; -+ -+ cpuModel = mvOsCpuPartGet(); -+ -+ /* The CPU module is indicated in the Processor Version Register (PVR) */ -+ switch(cpuModel) -+ { -+ case CPU_PART_MRVL131: -+ mvOsSPrintf(pNameBuff, "%s (Rev %d)", "Marvell Feroceon",mvOsCpuRevGet()); -+ break; -+ case CPU_PART_ARM926: -+ mvOsSPrintf(pNameBuff, "%s (Rev %d)", "ARM926",mvOsCpuRevGet()); -+ break; -+ case CPU_PART_ARM946: -+ mvOsSPrintf(pNameBuff, "%s (Rev %d)", "ARM946",mvOsCpuRevGet()); -+ break; -+ default: -+ mvOsSPrintf(pNameBuff,"??? (0x%04x) (Rev %d)",cpuModel,mvOsCpuRevGet()); -+ break; -+ } /* switch */ -+ -+ return; -+} -+ -+ -+#define MV_PROC_STR_SIZE 50 -+ -+static void mvCpuIfGetL2EccMode(MV_8 *buf) -+{ -+ MV_U32 regVal = MV_REG_READ(CPU_L2_CONFIG_REG); -+ if (regVal & BIT2) -+ mvOsSPrintf(buf, "L2 ECC Enabled"); -+ else -+ mvOsSPrintf(buf, "L2 ECC Disabled"); -+} -+ -+static void mvCpuIfGetL2Mode(MV_8 *buf) -+{ -+ MV_U32 regVal = 0; -+ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ -+ if (regVal & BIT22) -+ mvOsSPrintf(buf, "L2 Enabled"); -+ else -+ mvOsSPrintf(buf, "L2 Disabled"); -+} -+ -+static void mvCpuIfGetL2PrefetchMode(MV_8 *buf) -+{ -+ MV_U32 regVal = 0; -+ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ -+ if (regVal & BIT24) -+ mvOsSPrintf(buf, "L2 Prefetch Disabled"); -+ else -+ mvOsSPrintf(buf, "L2 Prefetch Enabled"); -+} -+ -+static void mvCpuIfGetWriteAllocMode(MV_8 *buf) -+{ -+ MV_U32 regVal = 0; -+ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ -+ if (regVal & BIT28) -+ mvOsSPrintf(buf, "Write Allocate Enabled"); -+ else -+ mvOsSPrintf(buf, "Write Allocate Disabled"); -+} -+ -+static void mvCpuIfGetCpuStreamMode(MV_8 *buf) -+{ -+ MV_U32 regVal = 0; -+ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ -+ if (regVal & BIT29) -+ mvOsSPrintf(buf, "CPU Streaming Enabled"); -+ else -+ mvOsSPrintf(buf, "CPU Streaming Disabled"); -+} -+ -+static void mvCpuIfPrintCpuRegs(void) -+{ -+ MV_U32 regVal = 0; -+ -+ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ -+ mvOsPrintf("Extra Feature Reg = 0x%x\n",regVal); -+ -+ __asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (regVal)); /* Read Control register */ -+ mvOsPrintf("Control Reg = 0x%x\n",regVal); -+ -+ __asm volatile ("mrc p15, 0, %0, c0, c0, 0" : "=r" (regVal)); /* Read ID Code register */ -+ mvOsPrintf("ID Code Reg = 0x%x\n",regVal); -+ -+ __asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=r" (regVal)); /* Read Cache Type register */ -+ mvOsPrintf("Cache Type Reg = 0x%x\n",regVal); -+ -+} -+ -+MV_U32 mvCpuIfPrintSystemConfig(MV_8 *buffer, MV_U32 index) -+{ -+ MV_U32 count = 0; -+ -+ MV_8 L2_ECC_str[MV_PROC_STR_SIZE]; -+ MV_8 L2_En_str[MV_PROC_STR_SIZE]; -+ MV_8 L2_Prefetch_str[MV_PROC_STR_SIZE]; -+ MV_8 Write_Alloc_str[MV_PROC_STR_SIZE]; -+ MV_8 Cpu_Stream_str[MV_PROC_STR_SIZE]; -+ -+ mvCpuIfGetL2Mode(L2_En_str); -+ mvCpuIfGetL2EccMode(L2_ECC_str); -+ mvCpuIfGetL2PrefetchMode(L2_Prefetch_str); -+ mvCpuIfGetWriteAllocMode(Write_Alloc_str); -+ mvCpuIfGetCpuStreamMode(Cpu_Stream_str); -+ mvCpuIfPrintCpuRegs(); -+ -+ count += mvOsSPrintf(buffer + count + index, "%s\n", L2_En_str); -+ count += mvOsSPrintf(buffer + count + index, "%s\n", L2_ECC_str); -+ count += mvOsSPrintf(buffer + count + index, "%s\n", L2_Prefetch_str); -+ count += mvOsSPrintf(buffer + count + index, "%s\n", Write_Alloc_str); -+ count += mvOsSPrintf(buffer + count + index, "%s\n", Cpu_Stream_str); -+ return count; -+} -+ -+MV_U32 whoAmI(MV_VOID) -+{ -+ return 0; -+} -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,99 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvCpuh -+#define __INCmvCpuh -+ -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+ -+/* defines */ -+#define CPU_PART_MRVL131 0x131 -+#define CPU_PART_ARM926 0x926 -+#define CPU_PART_ARM946 0x946 -+#define MV_CPU_ARM_CLK_ELM_SIZE 12 -+#define MV_CPU_ARM_CLK_RATIO_OFF 8 -+#define MV_CPU_ARM_CLK_DDR_OFF 4 -+ -+#ifndef MV_ASMLANGUAGE -+typedef struct _mvCpuArmClk -+{ -+ MV_U32 cpuClk; /* CPU clock in MHz */ -+ MV_U32 ddrClk; /* DDR clock in MHz */ -+ MV_U32 l2Clk; /* CPU DDR clock ratio */ -+ -+}MV_CPU_ARM_CLK; -+ -+MV_U32 mvCpuPclkGet(MV_VOID); -+MV_VOID mvCpuNameGet(char *pNameBuff); -+MV_U32 mvCpuL2ClkGet(MV_VOID); -+MV_U32 mvCpuIfPrintSystemConfig(MV_8 *buffer, MV_U32 index); -+MV_U32 whoAmI(MV_VOID); -+ -+#endif /* MV_ASMLANGUAGE */ -+ -+ -+#endif /* __INCmvCpuh */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,296 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+/******************************************************************************* -+* mvCtrlEnvAddrDec.h - Marvell controller address decode library -+* -+* DESCRIPTION: -+* -+* DEPENDENCIES: -+* None. -+* -+*******************************************************************************/ -+ -+/* includes */ -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+#include "ctrlEnv/sys/mvAhbToMbusRegs.h" -+#include "ddr2/mvDramIfRegs.h" -+#include "pex/mvPexRegs.h" -+ -+#define MV_DEBUG -+ -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+/* Default Attributes array */ -+MV_TARGET_ATTRIB mvTargetDefaultsArray[] = TARGETS_DEF_ARRAY; -+extern MV_TARGET *sampleAtResetTargetArray; -+/* Dram\AHBToMbus\PEX share regsiter */ -+ -+#define CTRL_DEC_BASE_OFFS 16 -+#define CTRL_DEC_BASE_MASK (0xffff << CTRL_DEC_BASE_OFFS) -+#define CTRL_DEC_BASE_ALIGNMENT 0x10000 -+ -+#define CTRL_DEC_SIZE_OFFS 16 -+#define CTRL_DEC_SIZE_MASK (0xffff << CTRL_DEC_SIZE_OFFS) -+#define CTRL_DEC_SIZE_ALIGNMENT 0x10000 -+ -+#define CTRL_DEC_WIN_EN BIT0 -+ -+ -+ -+/******************************************************************************* -+* mvCtrlAddrDecToReg - Get address decode register format values -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_STATUS mvCtrlAddrDecToReg(MV_ADDR_WIN *pAddrDecWin, MV_DEC_REGS *pAddrDecRegs) -+{ -+ -+ MV_U32 baseToReg=0 , sizeToReg=0; -+ -+ /* BaseLow[31:16] => base register [31:16] */ -+ baseToReg = pAddrDecWin->baseLow & CTRL_DEC_BASE_MASK; -+ -+ /* Write to address decode Base Address Register */ -+ pAddrDecRegs->baseReg &= ~CTRL_DEC_BASE_MASK; -+ pAddrDecRegs->baseReg |= baseToReg; -+ -+ /* Get size register value according to window size */ -+ sizeToReg = ctrlSizeToReg(pAddrDecWin->size, CTRL_DEC_SIZE_ALIGNMENT); -+ -+ /* Size parameter validity check. */ -+ if (-1 == sizeToReg) -+ { -+ return MV_BAD_PARAM; -+ } -+ -+ /* set size */ -+ pAddrDecRegs->sizeReg &= ~CTRL_DEC_SIZE_MASK; -+ pAddrDecRegs->sizeReg |= (sizeToReg << CTRL_DEC_SIZE_OFFS); -+ -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvCtrlRegToAddrDec - Extract address decode struct from registers. -+* -+* DESCRIPTION: -+* This function extract address decode struct from address decode -+* registers given as parameters. -+* -+* INPUT: -+* pAddrDecRegs - Address decode register struct. -+* -+* OUTPUT: -+* pAddrDecWin - Target window data structure. -+* -+* RETURN: -+* MV_BAD_PARAM if address decode registers data is invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvCtrlRegToAddrDec(MV_DEC_REGS *pAddrDecRegs, MV_ADDR_WIN *pAddrDecWin) -+{ -+ MV_U32 sizeRegVal; -+ -+ sizeRegVal = (pAddrDecRegs->sizeReg & CTRL_DEC_SIZE_MASK) >> -+ CTRL_DEC_SIZE_OFFS; -+ -+ pAddrDecWin->size = ctrlRegToSize(sizeRegVal, CTRL_DEC_SIZE_ALIGNMENT); -+ -+ -+ /* Extract base address */ -+ /* Base register [31:16] ==> baseLow[31:16] */ -+ pAddrDecWin->baseLow = pAddrDecRegs->baseReg & CTRL_DEC_BASE_MASK; -+ -+ pAddrDecWin->baseHigh = 0; -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvCtrlAttribGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+* -+*******************************************************************************/ -+ -+MV_STATUS mvCtrlAttribGet(MV_TARGET target, -+ MV_TARGET_ATTRIB *targetAttrib) -+{ -+ -+ targetAttrib->attrib = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].attrib; -+ targetAttrib->targetId = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId; -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvCtrlGetAttrib - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_TARGET mvCtrlTargetGet(MV_TARGET_ATTRIB *targetAttrib) -+{ -+ MV_TARGET target; -+ MV_TARGET x; -+ for (target = SDRAM_CS0; target < MAX_TARGETS ; target ++) -+ { -+ x = MV_CHANGE_BOOT_CS(target); -+ if ((mvTargetDefaultsArray[x].attrib == targetAttrib->attrib) && -+ (mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId == targetAttrib->targetId)) -+ { -+ /* found it */ -+ break; -+ } -+ } -+ -+ return target; -+} -+ -+MV_STATUS mvCtrlAddrDecToParams(MV_DEC_WIN *pAddrDecWin, -+ MV_DEC_WIN_PARAMS *pWinParam) -+{ -+ MV_U32 baseToReg=0, sizeToReg=0; -+ -+ /* BaseLow[31:16] => base register [31:16] */ -+ baseToReg = pAddrDecWin->addrWin.baseLow & CTRL_DEC_BASE_MASK; -+ -+ /* Write to address decode Base Address Register */ -+ pWinParam->baseAddr &= ~CTRL_DEC_BASE_MASK; -+ pWinParam->baseAddr |= baseToReg; -+ -+ /* Get size register value according to window size */ -+ sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, CTRL_DEC_SIZE_ALIGNMENT); -+ -+ /* Size parameter validity check. */ -+ if (-1 == sizeToReg) -+ { -+ mvOsPrintf("mvCtrlAddrDecToParams: ERR. ctrlSizeToReg failed.\n"); -+ return MV_BAD_PARAM; -+ } -+ pWinParam->size = sizeToReg; -+ -+ pWinParam->attrib = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(pAddrDecWin->target)].attrib; -+ pWinParam->targetId = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(pAddrDecWin->target)].targetId; -+ -+ return MV_OK; -+} -+ -+MV_STATUS mvCtrlParamsToAddrDec(MV_DEC_WIN_PARAMS *pWinParam, -+ MV_DEC_WIN *pAddrDecWin) -+{ -+ MV_TARGET_ATTRIB targetAttrib; -+ -+ pAddrDecWin->addrWin.baseLow = pWinParam->baseAddr; -+ -+ /* Upper 32bit address base is supported under PCI High Address remap */ -+ pAddrDecWin->addrWin.baseHigh = 0; -+ -+ /* Prepare sizeReg to ctrlRegToSize function */ -+ pAddrDecWin->addrWin.size = ctrlRegToSize(pWinParam->size, CTRL_DEC_SIZE_ALIGNMENT); -+ -+ if (-1 == pAddrDecWin->addrWin.size) -+ { -+ DB(mvOsPrintf("mvCtrlParamsToAddrDec: ERR. ctrlRegToSize failed.\n")); -+ return MV_BAD_PARAM; -+ } -+ targetAttrib.targetId = pWinParam->targetId; -+ targetAttrib.attrib = pWinParam->attrib; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ return MV_OK; -+} -+ -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,203 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvCtrlEnvAddrDech -+#define __INCmvCtrlEnvAddrDech -+ -+/* includes */ -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvRegs.h" -+ -+ -+/* defines */ -+/* DUnit attributes */ -+#define ATMWCR_WIN_DUNIT_CS0_OFFS 0 -+#define ATMWCR_WIN_DUNIT_CS0_MASK BIT0 -+#define ATMWCR_WIN_DUNIT_CS0_REQ (0 << ATMWCR_WIN_DUNIT_CS0_OFFS) -+ -+#define ATMWCR_WIN_DUNIT_CS1_OFFS 1 -+#define ATMWCR_WIN_DUNIT_CS1_MASK BIT1 -+#define ATMWCR_WIN_DUNIT_CS1_REQ (0 << ATMWCR_WIN_DUNIT_CS1_OFFS) -+ -+#define ATMWCR_WIN_DUNIT_CS2_OFFS 2 -+#define ATMWCR_WIN_DUNIT_CS2_MASK BIT2 -+#define ATMWCR_WIN_DUNIT_CS2_REQ (0 << ATMWCR_WIN_DUNIT_CS2_OFFS) -+ -+#define ATMWCR_WIN_DUNIT_CS3_OFFS 3 -+#define ATMWCR_WIN_DUNIT_CS3_MASK BIT3 -+#define ATMWCR_WIN_DUNIT_CS3_REQ (0 << ATMWCR_WIN_DUNIT_CS3_OFFS) -+ -+/* RUnit (Device) attributes */ -+#define ATMWCR_WIN_RUNIT_DEVCS0_OFFS 0 -+#define ATMWCR_WIN_RUNIT_DEVCS0_MASK BIT0 -+#define ATMWCR_WIN_RUNIT_DEVCS0_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS0_OFFS) -+ -+#define ATMWCR_WIN_RUNIT_DEVCS1_OFFS 1 -+#define ATMWCR_WIN_RUNIT_DEVCS1_MASK BIT1 -+#define ATMWCR_WIN_RUNIT_DEVCS1_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS1_OFFS) -+ -+#define ATMWCR_WIN_RUNIT_DEVCS2_OFFS 2 -+#define ATMWCR_WIN_RUNIT_DEVCS2_MASK BIT2 -+#define ATMWCR_WIN_RUNIT_DEVCS2_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS2_OFFS) -+ -+#define ATMWCR_WIN_RUNIT_BOOTCS_OFFS 4 -+#define ATMWCR_WIN_RUNIT_BOOTCS_MASK BIT4 -+#define ATMWCR_WIN_RUNIT_BOOTCS_REQ (0 << ATMWCR_WIN_RUNIT_BOOTCS_OFFS) -+ -+/* LMaster (PCI) attributes */ -+#define ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS 0 -+#define ATMWCR_WIN_LUNIT_BYTE_SWP_MASK BIT0 -+#define ATMWCR_WIN_LUNIT_BYTE_SWP (0 << ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS) -+#define ATMWCR_WIN_LUNIT_BYTE_NO_SWP (1 << ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS) -+ -+ -+#define ATMWCR_WIN_LUNIT_WORD_SWP_OFFS 1 -+#define ATMWCR_WIN_LUNIT_WORD_SWP_MASK BIT1 -+#define ATMWCR_WIN_LUNIT_WORD_SWP (0 << ATMWCR_WIN_LUNIT_WORD_SWP_OFFS) -+#define ATMWCR_WIN_LUNIT_WORD_NO_SWP (1 << ATMWCR_WIN_LUNIT_WORD_SWP_OFFS) -+ -+#define ATMWCR_WIN_LUNIT_NO_SNOOP BIT2 -+ -+#define ATMWCR_WIN_LUNIT_TYPE_OFFS 3 -+#define ATMWCR_WIN_LUNIT_TYPE_MASK BIT3 -+#define ATMWCR_WIN_LUNIT_TYPE_IO (0 << ATMWCR_WIN_LUNIT_TYPE_OFFS) -+#define ATMWCR_WIN_LUNIT_TYPE_MEM (1 << ATMWCR_WIN_LUNIT_TYPE_OFFS) -+ -+#define ATMWCR_WIN_LUNIT_FORCE64_OFFS 4 -+#define ATMWCR_WIN_LUNIT_FORCE64_MASK BIT4 -+#define ATMWCR_WIN_LUNIT_FORCE64 (0 << ATMWCR_WIN_LUNIT_FORCE64_OFFS) -+ -+#define ATMWCR_WIN_LUNIT_ORDERING_OFFS 6 -+#define ATMWCR_WIN_LUNIT_ORDERING_MASK BIT6 -+#define ATMWCR_WIN_LUNIT_ORDERING (1 << ATMWCR_WIN_LUNIT_FORCE64_OFFS) -+ -+/* PEX Attributes */ -+#define ATMWCR_WIN_PEX_TYPE_OFFS 3 -+#define ATMWCR_WIN_PEX_TYPE_MASK BIT3 -+#define ATMWCR_WIN_PEX_TYPE_IO (0 << ATMWCR_WIN_PEX_TYPE_OFFS) -+#define ATMWCR_WIN_PEX_TYPE_MEM (1 << ATMWCR_WIN_PEX_TYPE_OFFS) -+ -+/* typedefs */ -+ -+/* Unsupported attributes for address decode: */ -+/* 2) PCI0/1_REQ64n control */ -+ -+typedef struct _mvDecRegs -+{ -+ MV_U32 baseReg; -+ MV_U32 baseRegHigh; -+ MV_U32 sizeReg; -+ -+}MV_DEC_REGS; -+ -+typedef struct _mvTargetAttrib -+{ -+ MV_U8 attrib; /* chip select attributes */ -+ MV_TARGET_ID targetId; /* Target Id of this MV_TARGET */ -+ -+}MV_TARGET_ATTRIB; -+ -+ -+/* This structure describes address decode window */ -+typedef struct _mvDecWin -+{ -+ MV_TARGET target; /* Target for addr decode window */ -+ MV_ADDR_WIN addrWin; /* Address window of target */ -+ MV_BOOL enable; /* Window enable/disable */ -+}MV_DEC_WIN; -+ -+typedef struct _mvDecWinParams -+{ -+ MV_TARGET_ID targetId; /* Target ID field */ -+ MV_U8 attrib; /* Attribute field */ -+ MV_U32 baseAddr; /* Base address in register format */ -+ MV_U32 size; /* Size in register format */ -+}MV_DEC_WIN_PARAMS; -+ -+ -+/* mvCtrlEnvAddrDec API list */ -+ -+MV_STATUS mvCtrlAddrDecToReg(MV_ADDR_WIN *pAddrDecWin, -+ MV_DEC_REGS *pAddrDecRegs); -+ -+MV_STATUS mvCtrlRegToAddrDec(MV_DEC_REGS *pAddrDecRegs, -+ MV_ADDR_WIN *pAddrDecWin); -+ -+MV_STATUS mvCtrlAttribGet(MV_TARGET target, -+ MV_TARGET_ATTRIB *targetAttrib); -+ -+MV_TARGET mvCtrlTargetGet(MV_TARGET_ATTRIB *targetAttrib); -+ -+ -+MV_STATUS mvCtrlAddrDecToParams(MV_DEC_WIN *pAddrDecWin, -+ MV_DEC_WIN_PARAMS *pWinParam); -+ -+MV_STATUS mvCtrlParamsToAddrDec(MV_DEC_WIN_PARAMS *pWinParam, -+ MV_DEC_WIN *pAddrDecWin); -+ -+ -+ -+ -+#endif /* __INCmvCtrlEnvAddrDech */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,98 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvCtrlEnvAsmh -+#define __INCmvCtrlEnvAsmh -+#include "pex/mvPexRegs.h" -+ -+#define CHIP_BOND_REG 0x10034 -+#define PCKG_OPT_MASK_AS #3 -+#define PXCCARI_REVID_MASK_AS #PXCCARI_REVID_MASK -+ -+/* Read device ID into toReg bits 15:0 from 0xd0000000 */ -+/* defines */ -+#define MV_DV_CTRL_MODEL_GET_ASM(toReg, tmpReg) \ -+ MV_DV_REG_READ_ASM(toReg, tmpReg, CHIP_BOND_REG);\ -+ and toReg, toReg, PCKG_OPT_MASK_AS /* Mask for package ID */ -+ -+/* Read device ID into toReg bits 15:0 from 0xf1000000*/ -+#define MV_CTRL_MODEL_GET_ASM(toReg, tmpReg) \ -+ MV_REG_READ_ASM(toReg, tmpReg, CHIP_BOND_REG);\ -+ and toReg, toReg, PCKG_OPT_MASK_AS /* Mask for package ID */ -+ -+/* Read Revision into toReg bits 7:0 0xd0000000*/ -+#define MV_DV_CTRL_REV_GET_ASM(toReg, tmpReg) \ -+ /* Read device revision */ \ -+ MV_DV_REG_READ_ASM(toReg, tmpReg, PEX_CFG_DIRECT_ACCESS(0,PEX_CLASS_CODE_AND_REVISION_ID));\ -+ and toReg, toReg, PXCCARI_REVID_MASK_AS /* Mask for calss ID */ -+ -+/* Read Revision into toReg bits 7:0 0xf1000000*/ -+#define MV_CTRL_REV_GET_ASM(toReg, tmpReg) \ -+ /* Read device revision */ \ -+ MV_REG_READ_ASM(toReg, tmpReg, PEX_CFG_DIRECT_ACCESS(0,PEX_CLASS_CODE_AND_REVISION_ID));\ -+ and toReg, toReg, PXCCARI_REVID_MASK_AS /* Mask for calss ID */ -+ -+ -+#endif /* __INCmvCtrlEnvAsmh */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,1825 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+/* includes */ -+#include "mvCommon.h" -+#include "mvCtrlEnvLib.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+ -+#if defined(MV_INCLUDE_PEX) -+#include "pex/mvPex.h" -+#include "ctrlEnv/sys/mvSysPex.h" -+#endif -+ -+#if defined(MV_INCLUDE_GIG_ETH) -+#include "ctrlEnv/sys/mvSysGbe.h" -+#endif -+ -+#if defined(MV_INCLUDE_XOR) -+#include "ctrlEnv/sys/mvSysXor.h" -+#endif -+ -+#if defined(MV_INCLUDE_SATA) -+#include "ctrlEnv/sys/mvSysSata.h" -+#endif -+ -+#if defined(MV_INCLUDE_USB) -+#include "ctrlEnv/sys/mvSysUsb.h" -+#endif -+ -+#if defined(MV_INCLUDE_AUDIO) -+#include "ctrlEnv/sys/mvSysAudio.h" -+#endif -+ -+#if defined(MV_INCLUDE_CESA) -+#include "ctrlEnv/sys/mvSysCesa.h" -+#endif -+ -+#if defined(MV_INCLUDE_TS) -+#include "ctrlEnv/sys/mvSysTs.h" -+#endif -+ -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+/******************************************************************************* -+* mvCtrlEnvInit - Initialize Marvell controller environment. -+* -+* DESCRIPTION: -+* This function get environment information and initialize controller -+* internal/external environment. For example -+* 1) MPP settings according to board MPP macros. -+* NOTE: It is the user responsibility to shut down all DMA channels -+* in device and disable controller sub units interrupts during -+* boot process. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvCtrlEnvInit(MV_VOID) -+{ -+ MV_U32 mppGroup; -+ MV_U32 devId; -+ MV_U32 boardId; -+ MV_U32 i; -+ MV_U32 maxMppGrp = 1; -+ MV_U32 mppVal = 0; -+ MV_U32 bootVal = 0; -+ MV_U32 mppGroupType = 0; -+ MV_U32 mppGroup1[][3] = MPP_GROUP_1_TYPE; -+ MV_U32 mppGroup2[][3] = MPP_GROUP_2_TYPE; -+ -+ devId = mvCtrlModelGet(); -+ boardId= mvBoardIdGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ maxMppGrp = MV_6281_MPP_MAX_GROUP; -+ break; -+ case MV_6192_DEV_ID: -+ maxMppGrp = MV_6192_MPP_MAX_GROUP; -+ break; -+ case MV_6190_DEV_ID: -+ maxMppGrp = MV_6190_MPP_MAX_GROUP; -+ break; -+ case MV_6180_DEV_ID: -+ maxMppGrp = MV_6180_MPP_MAX_GROUP; -+ break; -+ } -+ -+ /* MPP Init */ -+ /* We split mpp init to 3 phases: -+ * 1. We init mpp[19:0] from the board info. mpp[23:20] will be over write -+ * in phase 2. -+ * 2. We detect the mpp group type and according the mpp values [35:20]. -+ * 3. We detect the mpp group type and according the mpp values [49:36]. -+ */ -+ /* Mpp phase 1 mpp[19:0] */ -+ /* Read MPP group from board level and assign to MPP register */ -+ for (mppGroup = 0; mppGroup < 3; mppGroup++) -+ { -+ mppVal = mvBoardMppGet(mppGroup); -+ if (mppGroup == 0) -+ { -+ bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); -+ if (mvCtrlIsBootFromSPI()) -+ { -+ mppVal &= ~0xffff; -+ bootVal &= 0xffff; -+ mppVal |= bootVal; -+ } -+ else if (mvCtrlIsBootFromSPIUseNAND()) -+ { -+ mppVal &= ~0xf0000000; -+ bootVal &= 0xf0000000; -+ mppVal |= bootVal; -+ } -+ else if (mvCtrlIsBootFromNAND()) -+ { -+ mppVal &= ~0xffffff; -+ bootVal &= 0xffffff; -+ mppVal |= bootVal; -+ } -+ } -+ -+ if (mppGroup == 2) -+ { -+ bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); -+ if (mvCtrlIsBootFromNAND()) -+ { -+ mppVal &= ~0xff00; -+ bootVal &= 0xff00; -+ mppVal |= bootVal; -+ } -+ } -+ -+ MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal); -+ } -+ -+ /* Identify MPPs group */ -+ mvBoardMppGroupIdUpdate(); -+ -+ /* Update MPPs mux relevent only on Marvell DB */ -+ if ((boardId == DB_88F6281A_BP_ID) || -+ (boardId == DB_88F6180A_BP_ID)) -+ mvBoardMppMuxSet(); -+ -+ mppGroupType = mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_1); -+ -+ /* Mpp phase 2 */ -+ /* Read MPP group from board level and assign to MPP register */ -+ if (devId != MV_6180_DEV_ID) -+ { -+ i = 0; -+ for (mppGroup = 2; mppGroup < 5; mppGroup++) -+ { -+ if ((mppGroupType == MV_BOARD_OTHER) || -+ (boardId == RD_88F6281A_ID) || -+ (boardId == RD_88F6192A_ID) || -+ (boardId == RD_88F6190A_ID) || -+ (boardId == RD_88F6281A_PCAC_ID) || -+ (boardId == SHEEVA_PLUG_ID)) -+ mppVal = mvBoardMppGet(mppGroup); -+ else -+ { -+ mppVal = mppGroup1[mppGroupType][i]; -+ i++; -+ } -+ -+ /* Group 2 is shared mpp[23:16] */ -+ if (mppGroup == 2) -+ { -+ bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); -+ mppVal &= ~0xffff; -+ bootVal &= 0xffff; -+ mppVal |= bootVal; -+ } -+ -+ MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal); -+ } -+ } -+ -+ if ((devId == MV_6192_DEV_ID) || (devId == MV_6190_DEV_ID)) -+ return MV_OK; -+ -+ /* Mpp phase 3 */ -+ mppGroupType = mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_2); -+ /* Read MPP group from board level and assign to MPP register */ -+ i = 0; -+ for (mppGroup = 4; mppGroup < 7; mppGroup++) -+ { -+ if ((mppGroupType == MV_BOARD_OTHER) || -+ (boardId == RD_88F6281A_ID) || -+ (boardId == RD_88F6281A_PCAC_ID) || -+ (boardId == SHEEVA_PLUG_ID)) -+ mppVal = mvBoardMppGet(mppGroup); -+ else -+ { -+ mppVal = mppGroup2[mppGroupType][i]; -+ i++; -+ } -+ -+ /* Group 4 is shared mpp[35:32] */ -+ if (mppGroup == 4) -+ { -+ bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); -+ mppVal &= ~0xffff; -+ bootVal &= 0xffff; -+ mppVal |= bootVal; -+ } -+ -+ MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal); -+ } -+ /* Update SSCG configuration register*/ -+ if(mvBoardIdGet() == DB_88F6281A_BP_ID || mvBoardIdGet() == DB_88F6192A_BP_ID || -+ mvBoardIdGet() == DB_88F6190A_BP_ID || mvBoardIdGet() == DB_88F6180A_BP_ID) -+ MV_REG_WRITE(0x100d8, 0x53); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCtrlMppRegGet - return reg address of mpp group -+* -+* DESCRIPTION: -+* -+* INPUT: -+* mppGroup - MPP group. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_U32 - Register address. -+* -+*******************************************************************************/ -+MV_U32 mvCtrlMppRegGet(MV_U32 mppGroup) -+{ -+ MV_U32 ret; -+ -+ switch(mppGroup){ -+ case (0): ret = MPP_CONTROL_REG0; -+ break; -+ case (1): ret = MPP_CONTROL_REG1; -+ break; -+ case (2): ret = MPP_CONTROL_REG2; -+ break; -+ case (3): ret = MPP_CONTROL_REG3; -+ break; -+ case (4): ret = MPP_CONTROL_REG4; -+ break; -+ case (5): ret = MPP_CONTROL_REG5; -+ break; -+ case (6): ret = MPP_CONTROL_REG6; -+ break; -+ default: ret = MPP_CONTROL_REG0; -+ break; -+ } -+ return ret; -+} -+#if defined(MV_INCLUDE_PEX) -+/******************************************************************************* -+* mvCtrlPexMaxIfGet - Get Marvell controller number of PEX interfaces. -+* -+* DESCRIPTION: -+* This function returns Marvell controller number of PEX interfaces. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Marvell controller number of PEX interfaces. If controller -+* ID is undefined the function returns '0'. -+* -+*******************************************************************************/ -+MV_U32 mvCtrlPexMaxIfGet(MV_VOID) -+{ -+ -+ return MV_PEX_MAX_IF; -+} -+#endif -+ -+#if defined(MV_INCLUDE_GIG_ETH) -+/******************************************************************************* -+* mvCtrlEthMaxPortGet - Get Marvell controller number of etherent ports. -+* -+* DESCRIPTION: -+* This function returns Marvell controller number of etherent port. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Marvell controller number of etherent port. -+* -+*******************************************************************************/ -+MV_U32 mvCtrlEthMaxPortGet(MV_VOID) -+{ -+ MV_U32 devId; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ return MV_6281_ETH_MAX_PORTS; -+ break; -+ case MV_6192_DEV_ID: -+ return MV_6192_ETH_MAX_PORTS; -+ break; -+ case MV_6190_DEV_ID: -+ return MV_6190_ETH_MAX_PORTS; -+ break; -+ case MV_6180_DEV_ID: -+ return MV_6180_ETH_MAX_PORTS; -+ break; -+ } -+ return 0; -+ -+} -+#endif -+ -+#if defined(MV_INCLUDE_XOR) -+/******************************************************************************* -+* mvCtrlXorMaxChanGet - Get Marvell controller number of XOR channels. -+* -+* DESCRIPTION: -+* This function returns Marvell controller number of XOR channels. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Marvell controller number of XOR channels. -+* -+*******************************************************************************/ -+MV_U32 mvCtrlXorMaxChanGet(MV_VOID) -+{ -+ return MV_XOR_MAX_CHAN; -+} -+#endif -+ -+#if defined(MV_INCLUDE_USB) -+/******************************************************************************* -+* mvCtrlUsbHostMaxGet - Get number of Marvell Usb controllers -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* returns number of Marvell USB controllers. -+* -+*******************************************************************************/ -+MV_U32 mvCtrlUsbMaxGet(void) -+{ -+ return MV_USB_MAX_PORTS; -+} -+#endif -+ -+ -+#if defined(MV_INCLUDE_NAND) -+/******************************************************************************* -+* mvCtrlNandSupport - Return if this controller has integrated NAND flash support -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if NAND is supported and MV_FALSE otherwise -+* -+*******************************************************************************/ -+MV_U32 mvCtrlNandSupport(MV_VOID) -+{ -+ MV_U32 devId; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ return MV_6281_NAND; -+ break; -+ case MV_6192_DEV_ID: -+ return MV_6192_NAND; -+ break; -+ case MV_6190_DEV_ID: -+ return MV_6190_NAND; -+ break; -+ case MV_6180_DEV_ID: -+ return MV_6180_NAND; -+ break; -+ } -+ return 0; -+ -+} -+#endif -+ -+#if defined(MV_INCLUDE_SDIO) -+/******************************************************************************* -+* mvCtrlSdioSupport - Return if this controller has integrated SDIO flash support -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if SDIO is supported and MV_FALSE otherwise -+* -+*******************************************************************************/ -+MV_U32 mvCtrlSdioSupport(MV_VOID) -+{ -+ MV_U32 devId; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ return MV_6281_SDIO; -+ break; -+ case MV_6192_DEV_ID: -+ return MV_6192_SDIO; -+ break; -+ case MV_6190_DEV_ID: -+ return MV_6190_SDIO; -+ break; -+ case MV_6180_DEV_ID: -+ return MV_6180_SDIO; -+ break; -+ } -+ return 0; -+ -+} -+#endif -+ -+#if defined(MV_INCLUDE_TS) -+/******************************************************************************* -+* mvCtrlTsSupport - Return if this controller has integrated TS flash support -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if TS is supported and MV_FALSE otherwise -+* -+*******************************************************************************/ -+MV_U32 mvCtrlTsSupport(MV_VOID) -+{ -+ MV_U32 devId; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ return MV_6281_TS; -+ break; -+ case MV_6192_DEV_ID: -+ return MV_6192_TS; -+ break; -+ case MV_6190_DEV_ID: -+ return MV_6190_TS; -+ break; -+ case MV_6180_DEV_ID: -+ return MV_6180_TS; -+ break; -+ } -+ return 0; -+} -+#endif -+ -+#if defined(MV_INCLUDE_AUDIO) -+/******************************************************************************* -+* mvCtrlAudioSupport - Return if this controller has integrated AUDIO flash support -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if AUDIO is supported and MV_FALSE otherwise -+* -+*******************************************************************************/ -+MV_U32 mvCtrlAudioSupport(MV_VOID) -+{ -+ MV_U32 devId; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ return MV_6281_AUDIO; -+ break; -+ case MV_6192_DEV_ID: -+ return MV_6192_AUDIO; -+ break; -+ case MV_6190_DEV_ID: -+ return MV_6190_AUDIO; -+ break; -+ case MV_6180_DEV_ID: -+ return MV_6180_AUDIO; -+ break; -+ } -+ return 0; -+ -+} -+#endif -+ -+#if defined(MV_INCLUDE_TDM) -+/******************************************************************************* -+* mvCtrlTdmSupport - Return if this controller has integrated TDM flash support -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if TDM is supported and MV_FALSE otherwise -+* -+*******************************************************************************/ -+MV_U32 mvCtrlTdmSupport(MV_VOID) -+{ -+ MV_U32 devId; -+ -+ devId = mvCtrlModelGet(); -+ -+ switch(devId){ -+ case MV_6281_DEV_ID: -+ return MV_6281_TDM; -+ break; -+ case MV_6192_DEV_ID: -+ return MV_6192_TDM; -+ break; -+ case MV_6190_DEV_ID: -+ return MV_6190_TDM; -+ break; -+ case MV_6180_DEV_ID: -+ return MV_6180_TDM; -+ break; -+ } -+ return 0; -+ -+} -+#endif -+ -+/******************************************************************************* -+* mvCtrlModelGet - Get Marvell controller device model (Id) -+* -+* DESCRIPTION: -+* This function returns 16bit describing the device model (ID) as defined -+* in PCI Device and Vendor ID configuration register offset 0x0. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 16bit desscribing Marvell controller ID -+* -+*******************************************************************************/ -+MV_U16 mvCtrlModelGet(MV_VOID) -+{ -+ MV_U32 devId; -+ -+ devId = MV_REG_READ(CHIP_BOND_REG); -+ devId &= PCKG_OPT_MASK; -+ -+ switch(devId){ -+ case 2: -+ return MV_6281_DEV_ID; -+ break; -+ case 1: -+ if (((MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0,PEX_DEVICE_AND_VENDOR_ID))& 0xffff0000) >> 16) -+ == MV_6190_DEV_ID) -+ return MV_6190_DEV_ID; -+ else -+ return MV_6192_DEV_ID; -+ break; -+ case 0: -+ return MV_6180_DEV_ID; -+ break; -+ } -+ -+ return 0; -+} -+/******************************************************************************* -+* mvCtrlRevGet - Get Marvell controller device revision number -+* -+* DESCRIPTION: -+* This function returns 8bit describing the device revision as defined -+* in PCI Express Class Code and Revision ID Register. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 8bit desscribing Marvell controller revision number -+* -+*******************************************************************************/ -+MV_U8 mvCtrlRevGet(MV_VOID) -+{ -+ MV_U8 revNum; -+#if defined(MV_INCLUDE_CLK_PWR_CNTRL) -+ /* Check pex power state */ -+ MV_U32 pexPower; -+ pexPower = mvCtrlPwrClckGet(PEX_UNIT_ID,0); -+ if (pexPower == MV_FALSE) -+ mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_TRUE); -+#endif -+ revNum = (MV_U8)MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0,PCI_CLASS_CODE_AND_REVISION_ID)); -+#if defined(MV_INCLUDE_CLK_PWR_CNTRL) -+ /* Return to power off state */ -+ if (pexPower == MV_FALSE) -+ mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_FALSE); -+#endif -+ return ((revNum & PCCRIR_REVID_MASK) >> PCCRIR_REVID_OFFS); -+} -+ -+/******************************************************************************* -+* mvCtrlNameGet - Get Marvell controller name -+* -+* DESCRIPTION: -+* This function returns a string describing the device model and revision. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* pNameBuff - Buffer to contain device name string. Minimum size 30 chars. -+* -+* RETURN: -+* -+* MV_ERROR if informantion can not be read. -+*******************************************************************************/ -+MV_STATUS mvCtrlNameGet(char *pNameBuff) -+{ -+ mvOsSPrintf (pNameBuff, "%s%x Rev %d", SOC_NAME_PREFIX, -+ mvCtrlModelGet(), mvCtrlRevGet()); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCtrlModelRevGet - Get Controller Model (Device ID) and Revision -+* -+* DESCRIPTION: -+* This function returns 32bit value describing both Device ID and Revision -+* as defined in PCI Express Device and Vendor ID Register and device revision -+* as defined in PCI Express Class Code and Revision ID Register. -+ -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit describing both controller device ID and revision number -+* -+*******************************************************************************/ -+MV_U32 mvCtrlModelRevGet(MV_VOID) -+{ -+ return ((mvCtrlModelGet() << 16) | mvCtrlRevGet()); -+} -+ -+/******************************************************************************* -+* mvCtrlModelRevNameGet - Get Marvell controller name -+* -+* DESCRIPTION: -+* This function returns a string describing the device model and revision. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* pNameBuff - Buffer to contain device name string. Minimum size 30 chars. -+* -+* RETURN: -+* -+* MV_ERROR if informantion can not be read. -+*******************************************************************************/ -+ -+MV_STATUS mvCtrlModelRevNameGet(char *pNameBuff) -+{ -+ -+ switch (mvCtrlModelRevGet()) -+ { -+ case MV_6281_A0_ID: -+ mvOsSPrintf (pNameBuff, "%s",MV_6281_A0_NAME); -+ break; -+ case MV_6192_A0_ID: -+ mvOsSPrintf (pNameBuff, "%s",MV_6192_A0_NAME); -+ break; -+ case MV_6180_A0_ID: -+ mvOsSPrintf (pNameBuff, "%s",MV_6180_A0_NAME); -+ break; -+ case MV_6190_A0_ID: -+ mvOsSPrintf (pNameBuff, "%s",MV_6190_A0_NAME); -+ break; -+ case MV_6281_A1_ID: -+ mvOsSPrintf (pNameBuff, "%s",MV_6281_A1_NAME); -+ break; -+ case MV_6192_A1_ID: -+ mvOsSPrintf (pNameBuff, "%s",MV_6192_A1_NAME); -+ break; -+ case MV_6180_A1_ID: -+ mvOsSPrintf (pNameBuff, "%s",MV_6180_A1_NAME); -+ break; -+ case MV_6190_A1_ID: -+ mvOsSPrintf (pNameBuff, "%s",MV_6190_A1_NAME); -+ break; -+ default: -+ mvCtrlNameGet(pNameBuff); -+ break; -+ } -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* ctrlWinOverlapTest - Test address windows for overlaping. -+* -+* DESCRIPTION: -+* This function checks the given two address windows for overlaping. -+* -+* INPUT: -+* pAddrWin1 - Address window 1. -+* pAddrWin2 - Address window 2. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* MV_TRUE if address window overlaps, MV_FALSE otherwise. -+*******************************************************************************/ -+MV_STATUS ctrlWinOverlapTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2) -+{ -+ MV_U32 winBase1, winBase2; -+ MV_U32 winTop1, winTop2; -+ -+ /* check if we have overflow than 4G*/ -+ if (((0xffffffff - pAddrWin1->baseLow) < pAddrWin1->size-1)|| -+ ((0xffffffff - pAddrWin2->baseLow) < pAddrWin2->size-1)) -+ { -+ return MV_TRUE; -+ } -+ -+ winBase1 = pAddrWin1->baseLow; -+ winBase2 = pAddrWin2->baseLow; -+ winTop1 = winBase1 + pAddrWin1->size-1; -+ winTop2 = winBase2 + pAddrWin2->size-1; -+ -+ -+ if (((winBase1 <= winTop2 ) && ( winTop2 <= winTop1)) || -+ ((winBase1 <= winBase2) && (winBase2 <= winTop1))) -+ { -+ return MV_TRUE; -+ } -+ else -+ { -+ return MV_FALSE; -+ } -+} -+ -+/******************************************************************************* -+* ctrlWinWithinWinTest - Test address windows for overlaping. -+* -+* DESCRIPTION: -+* This function checks the given win1 boundries is within -+* win2 boundries. -+* -+* INPUT: -+* pAddrWin1 - Address window 1. -+* pAddrWin2 - Address window 2. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+* MV_TRUE if found win1 inside win2, MV_FALSE otherwise. -+*******************************************************************************/ -+MV_STATUS ctrlWinWithinWinTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2) -+{ -+ MV_U32 winBase1, winBase2; -+ MV_U32 winTop1, winTop2; -+ -+ winBase1 = pAddrWin1->baseLow; -+ winBase2 = pAddrWin2->baseLow; -+ winTop1 = winBase1 + pAddrWin1->size -1; -+ winTop2 = winBase2 + pAddrWin2->size -1; -+ -+ if (((winBase1 >= winBase2 ) && ( winBase1 <= winTop2)) || -+ ((winTop1 >= winBase2) && (winTop1 <= winTop2))) -+ { -+ return MV_TRUE; -+ } -+ else -+ { -+ return MV_FALSE; -+ } -+} -+ -+static const char* cntrlName[] = TARGETS_NAME_ARRAY; -+ -+/******************************************************************************* -+* mvCtrlTargetNameGet - Get Marvell controller target name -+* -+* DESCRIPTION: -+* This function convert the trget enumeration to string. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Target name (const MV_8 *) -+*******************************************************************************/ -+const MV_8* mvCtrlTargetNameGet( MV_TARGET target ) -+{ -+ -+ if (target >= MAX_TARGETS) -+ { -+ return "target unknown"; -+ } -+ -+ return cntrlName[target]; -+} -+ -+/******************************************************************************* -+* mvCtrlAddrDecShow - Print the Controller units address decode map. -+* -+* DESCRIPTION: -+* This function the Controller units address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvCtrlAddrDecShow(MV_VOID) -+{ -+ mvCpuIfAddDecShow(); -+ mvAhbToMbusAddDecShow(); -+#if defined(MV_INCLUDE_PEX) -+ mvPexAddrDecShow(); -+#endif -+#if defined(MV_INCLUDE_USB) -+ mvUsbAddrDecShow(); -+#endif -+#if defined(MV_INCLUDE_GIG_ETH) -+ mvEthAddrDecShow(); -+#endif -+#if defined(MV_INCLUDE_XOR) -+ mvXorAddrDecShow(); -+#endif -+#if defined(MV_INCLUDE_SATA) -+ mvSataAddrDecShow(); -+#endif -+#if defined(MV_INCLUDE_AUDIO) -+ mvAudioAddrDecShow(); -+#endif -+#if defined(MV_INCLUDE_TS) -+ mvTsuAddrDecShow(); -+#endif -+} -+ -+/******************************************************************************* -+* ctrlSizeToReg - Extract size value for register assignment. -+* -+* DESCRIPTION: -+* Address decode size parameter must be programed from LSB to MSB as -+* sequence of 1's followed by sequence of 0's. The number of 1's -+* specifies the size of the window in 64 KB granularity (e.g. a -+* value of 0x00ff specifies 256x64k = 16 MB). -+* This function extract the size value from the size parameter according -+* to given aligment paramter. For example for size 0x1000000 (16MB) and -+* aligment 0x10000 (64KB) the function will return 0x00FF. -+* -+* INPUT: -+* size - Size. -+* alignment - Size alignment. Note that alignment must be power of 2! -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit describing size register value correspond to size parameter. -+* If value is '-1' size parameter or aligment are invalid. -+*******************************************************************************/ -+MV_U32 ctrlSizeToReg(MV_U32 size, MV_U32 alignment) -+{ -+ MV_U32 retVal; -+ -+ /* Check size parameter alignment */ -+ if ((0 == size) || (MV_IS_NOT_ALIGN(size, alignment))) -+ { -+ DB(mvOsPrintf("ctrlSizeToReg: ERR. Size is zero or not aligned.\n")); -+ return -1; -+ } -+ -+ /* Take out the "alignment" portion out of the size parameter */ -+ alignment--; /* Now the alignmet is a sequance of '1' (e.g. 0xffff) */ -+ /* and size is 0x1000000 (16MB) for example */ -+ while(alignment & 1) /* Check that alignmet LSB is set */ -+ { -+ size = (size >> 1); /* If LSB is set, move 'size' one bit to right */ -+ alignment = (alignment >> 1); -+ } -+ -+ /* If after the alignment first '0' was met we still have '1' in */ -+ /* it then aligment is invalid (not power of 2) */ -+ if (alignment) -+ { -+ DB(mvOsPrintf("ctrlSizeToReg: ERR. Alignment parameter 0x%x invalid.\n", -+ (MV_U32)alignment)); -+ return -1; -+ } -+ -+ /* Now the size is shifted right according to aligment: 0x0100 */ -+ size--; /* Now the size is a sequance of '1': 0x00ff */ -+ -+ retVal = size ; -+ -+ /* Check that LSB to MSB is sequence of 1's followed by sequence of 0's */ -+ while(size & 1) /* Check that LSB is set */ -+ { -+ size = (size >> 1); /* If LSB is set, move one bit to the right */ -+ } -+ -+ if (size) /* Sequance of 1's is over. Check that we have no other 1's */ -+ { -+ DB(mvOsPrintf("ctrlSizeToReg: ERR. Size parameter 0x%x invalid.\n", -+ size)); -+ return -1; -+ } -+ -+ return retVal; -+ -+} -+ -+/******************************************************************************* -+* ctrlRegToSize - Extract size value from register value. -+* -+* DESCRIPTION: -+* This function extract a size value from the register size parameter -+* according to given aligment paramter. For example for register size -+* value 0xff and aligment 0x10000 the function will return 0x01000000. -+* -+* INPUT: -+* regSize - Size as in register format. See ctrlSizeToReg. -+* alignment - Size alignment. Note that alignment must be power of 2! -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit describing size. -+* If value is '-1' size parameter or aligment are invalid. -+*******************************************************************************/ -+MV_U32 ctrlRegToSize(MV_U32 regSize, MV_U32 alignment) -+{ -+ MV_U32 temp; -+ -+ /* Check that LSB to MSB is sequence of 1's followed by sequence of 0's */ -+ temp = regSize; /* Now the size is a sequance of '1': 0x00ff */ -+ -+ while(temp & 1) /* Check that LSB is set */ -+ { -+ temp = (temp >> 1); /* If LSB is set, move one bit to the right */ -+ } -+ -+ if (temp) /* Sequance of 1's is over. Check that we have no other 1's */ -+ { -+ DB(mvOsPrintf("ctrlRegToSize: ERR. Size parameter 0x%x invalid.\n", -+ regSize)); -+ return -1; -+ } -+ -+ -+ /* Check that aligment is a power of two */ -+ temp = alignment - 1;/* Now the alignmet is a sequance of '1' (0xffff) */ -+ -+ while(temp & 1) /* Check that alignmet LSB is set */ -+ { -+ temp = (temp >> 1); /* If LSB is set, move 'size' one bit to right */ -+ } -+ -+ /* If after the 'temp' first '0' was met we still have '1' in 'temp' */ -+ /* then 'temp' is invalid (not power of 2) */ -+ if (temp) -+ { -+ DB(mvOsPrintf("ctrlSizeToReg: ERR. Alignment parameter 0x%x invalid.\n", -+ alignment)); -+ return -1; -+ } -+ -+ regSize++; /* Now the size is 0x0100 */ -+ -+ /* Add in the "alignment" portion to the register size parameter */ -+ alignment--; /* Now the alignmet is a sequance of '1' (e.g. 0xffff) */ -+ -+ while(alignment & 1) /* Check that alignmet LSB is set */ -+ { -+ regSize = (regSize << 1); /* LSB is set, move 'size' one bit left */ -+ alignment = (alignment >> 1); -+ } -+ -+ return regSize; -+} -+ -+ -+/******************************************************************************* -+* ctrlSizeRegRoundUp - Round up given size -+* -+* DESCRIPTION: -+* This function round up a given size to a size that fits the -+* restrictions of size format given an aligment parameter. -+* to given aligment paramter. For example for size parameter 0xa1000 and -+* aligment 0x1000 the function will return 0xFF000. -+* -+* INPUT: -+* size - Size. -+* alignment - Size alignment. Note that alignment must be power of 2! -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit describing size value correspond to size in register. -+*******************************************************************************/ -+MV_U32 ctrlSizeRegRoundUp(MV_U32 size, MV_U32 alignment) -+{ -+ MV_U32 msbBit = 0; -+ MV_U32 retSize; -+ -+ /* Check if size parameter is already comply with restriction */ -+ if (!(-1 == ctrlSizeToReg(size, alignment))) -+ { -+ return size; -+ } -+ -+ while(size) -+ { -+ size = (size >> 1); -+ msbBit++; -+ } -+ -+ retSize = (1 << msbBit); -+ -+ if (retSize < alignment) -+ { -+ return alignment; -+ } -+ else -+ { -+ return retSize; -+ } -+} -+/******************************************************************************* -+* mvCtrlSysRstLengthCounterGet - Return number of milliseconds the reset button -+* was pressed and clear counter -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: number of milliseconds the reset button was pressed -+*******************************************************************************/ -+MV_U32 mvCtrlSysRstLengthCounterGet(MV_VOID) -+{ -+ static volatile MV_U32 Count = 0; -+ -+ if(!Count) { -+ Count = (MV_REG_READ(SYSRST_LENGTH_COUNTER_REG) & SLCR_COUNT_MASK); -+ Count = (Count / (MV_BOARD_REFCLK_25MHZ / 1000)); -+ /* clear counter for next boot */ -+ MV_REG_BIT_SET(SYSRST_LENGTH_COUNTER_REG, SLCR_CLR_MASK); -+ } -+ -+ DB(mvOsPrintf("mvCtrlSysRstLengthCounterGet: Reset button was pressed for %u milliseconds\n", Count)); -+ -+ return Count; -+} -+ -+MV_BOOL mvCtrlIsBootFromSPI(MV_VOID) -+{ -+ MV_U32 satr = 0; -+ satr = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ if(mvCtrlModelGet() == MV_6180_DEV_ID) -+ { -+ if (MSAR_BOOT_MODE_6180(satr) == MSAR_BOOT_SPI_WITH_BOOTROM_6180) -+ return MV_TRUE; -+ else -+ return MV_FALSE; -+ } -+ satr = satr & MSAR_BOOT_MODE_MASK; -+ if (satr == MSAR_BOOT_SPI_WITH_BOOTROM) -+ return MV_TRUE; -+ else -+ return MV_FALSE; -+} -+ -+MV_BOOL mvCtrlIsBootFromSPIUseNAND(MV_VOID) -+{ -+ MV_U32 satr = 0; -+ if(mvCtrlModelGet() == MV_6180_DEV_ID) -+ return MV_FALSE; -+ satr = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ satr = satr & MSAR_BOOT_MODE_MASK; -+ -+ if (satr == MSAR_BOOT_SPI_USE_NAND_WITH_BOOTROM) -+ return MV_TRUE; -+ else -+ return MV_FALSE; -+} -+ -+MV_BOOL mvCtrlIsBootFromNAND(MV_VOID) -+{ -+ MV_U32 satr = 0; -+ satr = MV_REG_READ(MPP_SAMPLE_AT_RESET); -+ if(mvCtrlModelGet() == MV_6180_DEV_ID) -+ { -+ if (MSAR_BOOT_MODE_6180(satr) == MSAR_BOOT_NAND_WITH_BOOTROM_6180) -+ return MV_TRUE; -+ else -+ return MV_FALSE; -+ } -+ satr = satr & MSAR_BOOT_MODE_MASK; -+ if ((satr == MSAR_BOOT_NAND_WITH_BOOTROM)) -+ return MV_TRUE; -+ else -+ return MV_FALSE; -+} -+ -+#if defined(MV_INCLUDE_CLK_PWR_CNTRL) -+/******************************************************************************* -+* mvCtrlPwrSaveOn - Set Power save mode -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+*******************************************************************************/ -+MV_VOID mvCtrlPwrSaveOn(MV_VOID) -+{ -+ unsigned long old,temp; -+ /* Disable int */ -+ __asm__ __volatile__("mrs %0, cpsr\n" -+ "orr %1, %0, #0xc0\n" -+ "msr cpsr_c, %1" -+ : "=r" (old), "=r" (temp) -+ : -+ : "memory"); -+ -+ /* Set SoC in power save */ -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, BIT11); -+ /* Wait for int */ -+ __asm__ __volatile__("mcr p15, 0, r0, c7, c0, 4"); -+ -+ /* Enabled int */ -+ __asm__ __volatile__("msr cpsr_c, %0" -+ : -+ : "r" (old) -+ : "memory"); -+} -+ -+ -+ -+/******************************************************************************* -+* mvCtrlPwrSaveOff - Go out of power save mode -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+*******************************************************************************/ -+MV_VOID mvCtrlPwrSaveOff(MV_VOID) -+{ -+ unsigned long old,temp; -+ /* Disable int */ -+ __asm__ __volatile__("mrs %0, cpsr\n" -+ "orr %1, %0, #0xc0\n" -+ "msr cpsr_c, %1" -+ : "=r" (old), "=r" (temp) -+ : -+ : "memory"); -+ -+ /* Set SoC in power save */ -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, BIT11); -+ /* Wait for int */ -+ __asm__ __volatile__("mcr p15, 0, r0, c7, c0, 4"); -+ -+ /* Enabled int */ -+ __asm__ __volatile__("msr cpsr_c, %0" -+ : -+ : "r" (old) -+ : "memory"); -+} -+ -+/******************************************************************************* -+* mvCtrlPwrClckSet - Set Power State for specific Unit -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+*******************************************************************************/ -+MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) -+{ -+ switch (unitId) -+ { -+#if defined(MV_INCLUDE_PEX) -+ case PEX_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_PEXSTOPCLOCK_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_PEXSTOPCLOCK_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_GIG_ETH) -+ case ETH_GIG_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_GESTOPCLOCK_MASK(index)); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_GESTOPCLOCK_MASK(index)); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_INTEG_SATA) -+ case SATA_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SATASTOPCLOCK_MASK(index)); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SATASTOPCLOCK_MASK(index)); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_CESA) -+ case CESA_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SESTOPCLOCK_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SESTOPCLOCK_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_USB) -+ case USB_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_USBSTOPCLOCK_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_USBSTOPCLOCK_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_AUDIO) -+ case AUDIO_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_AUDIOSTOPCLOCK_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_AUDIOSTOPCLOCK_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_TS) -+ case TS_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_TSSTOPCLOCK_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_TSSTOPCLOCK_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_SDIO) -+ case SDIO_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SDIOSTOPCLOCK_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SDIOSTOPCLOCK_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_TDM) -+ case TDM_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_TDMSTOPCLOCK_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_TDMSTOPCLOCK_MASK); -+ } -+ break; -+#endif -+ -+ default: -+ -+ break; -+ -+ } -+} -+ -+/******************************************************************************* -+* mvCtrlPwrClckGet - Get Power State of specific Unit -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+******************************************************************************/ -+MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index) -+{ -+ MV_U32 reg = MV_REG_READ(POWER_MNG_CTRL_REG); -+ MV_BOOL state = MV_TRUE; -+ -+ switch (unitId) -+ { -+#if defined(MV_INCLUDE_PEX) -+ case PEX_UNIT_ID: -+ if ((reg & PMC_PEXSTOPCLOCK_MASK) == PMC_PEXSTOPCLOCK_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ -+ break; -+#endif -+#if defined(MV_INCLUDE_GIG_ETH) -+ case ETH_GIG_UNIT_ID: -+ if ((reg & PMC_GESTOPCLOCK_MASK(index)) == PMC_GESTOPCLOCK_STOP(index)) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_SATA) -+ case SATA_UNIT_ID: -+ if ((reg & PMC_SATASTOPCLOCK_MASK(index)) == PMC_SATASTOPCLOCK_STOP(index)) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_CESA) -+ case CESA_UNIT_ID: -+ if ((reg & PMC_SESTOPCLOCK_MASK) == PMC_SESTOPCLOCK_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_USB) -+ case USB_UNIT_ID: -+ if ((reg & PMC_USBSTOPCLOCK_MASK) == PMC_USBSTOPCLOCK_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_AUDIO) -+ case AUDIO_UNIT_ID: -+ if ((reg & PMC_AUDIOSTOPCLOCK_MASK) == PMC_AUDIOSTOPCLOCK_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_TS) -+ case TS_UNIT_ID: -+ if ((reg & PMC_TSSTOPCLOCK_MASK) == PMC_TSSTOPCLOCK_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_SDIO) -+ case SDIO_UNIT_ID: -+ if ((reg & PMC_SDIOSTOPCLOCK_MASK)== PMC_SDIOSTOPCLOCK_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_TDM) -+ case TDM_UNIT_ID: -+ if ((reg & PMC_TDMSTOPCLOCK_MASK) == PMC_TDMSTOPCLOCK_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+ -+ default: -+ state = MV_TRUE; -+ break; -+ } -+ -+ -+ return state; -+} -+/******************************************************************************* -+* mvCtrlPwrMemSet - Set Power State for memory on specific Unit -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+*******************************************************************************/ -+MV_VOID mvCtrlPwrMemSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) -+{ -+ switch (unitId) -+ { -+#if defined(MV_INCLUDE_PEX) -+ case PEX_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_PEXSTOPMEM_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_PEXSTOPMEM_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_GIG_ETH) -+ case ETH_GIG_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_GESTOPMEM_MASK(index)); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_GESTOPMEM_MASK(index)); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_INTEG_SATA) -+ case SATA_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_SATASTOPMEM_MASK(index)); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_SATASTOPMEM_MASK(index)); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_CESA) -+ case CESA_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_SESTOPMEM_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_SESTOPMEM_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_USB) -+ case USB_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_USBSTOPMEM_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_USBSTOPMEM_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_AUDIO) -+ case AUDIO_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_AUDIOSTOPMEM_MASK); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_AUDIOSTOPMEM_MASK); -+ } -+ break; -+#endif -+#if defined(MV_INCLUDE_XOR) -+ case XOR_UNIT_ID: -+ if (enable == MV_FALSE) -+ { -+ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_XORSTOPMEM_MASK(index)); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_XORSTOPMEM_MASK(index)); -+ } -+ break; -+#endif -+ default: -+ -+ break; -+ -+ } -+} -+ -+/******************************************************************************* -+* mvCtrlPwrMemGet - Get Power State of memory on specific Unit -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+******************************************************************************/ -+MV_BOOL mvCtrlPwrMemGet(MV_UNIT_ID unitId, MV_U32 index) -+{ -+ MV_U32 reg = MV_REG_READ(POWER_MNG_MEM_CTRL_REG); -+ MV_BOOL state = MV_TRUE; -+ -+ switch (unitId) -+ { -+#if defined(MV_INCLUDE_PEX) -+ case PEX_UNIT_ID: -+ if ((reg & PMC_PEXSTOPMEM_MASK) == PMC_PEXSTOPMEM_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ -+ break; -+#endif -+#if defined(MV_INCLUDE_GIG_ETH) -+ case ETH_GIG_UNIT_ID: -+ if ((reg & PMC_GESTOPMEM_MASK(index)) == PMC_GESTOPMEM_STOP(index)) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_SATA) -+ case SATA_UNIT_ID: -+ if ((reg & PMC_SATASTOPMEM_MASK(index)) == PMC_SATASTOPMEM_STOP(index)) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_CESA) -+ case CESA_UNIT_ID: -+ if ((reg & PMC_SESTOPMEM_MASK) == PMC_SESTOPMEM_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_USB) -+ case USB_UNIT_ID: -+ if ((reg & PMC_USBSTOPMEM_MASK) == PMC_USBSTOPMEM_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_AUDIO) -+ case AUDIO_UNIT_ID: -+ if ((reg & PMC_AUDIOSTOPMEM_MASK) == PMC_AUDIOSTOPMEM_STOP) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+#if defined(MV_INCLUDE_XOR) -+ case XOR_UNIT_ID: -+ if ((reg & PMC_XORSTOPMEM_MASK(index)) == PMC_XORSTOPMEM_STOP(index)) -+ { -+ state = MV_FALSE; -+ } -+ else state = MV_TRUE; -+ break; -+#endif -+ -+ default: -+ state = MV_TRUE; -+ break; -+ } -+ -+ -+ return state; -+} -+#else -+MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) {return;} -+MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index) {return MV_TRUE;} -+#endif /* #if defined(MV_INCLUDE_CLK_PWR_CNTRL) */ -+ -+ -+/******************************************************************************* -+* mvMPPConfigToSPI - Change MPP[3:0] configuration to SPI mode -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+******************************************************************************/ -+MV_VOID mvMPPConfigToSPI(MV_VOID) -+{ -+ MV_U32 mppVal = 0; -+ MV_U32 bootVal = 0; -+ -+ if(!mvCtrlIsBootFromSPIUseNAND()) -+ return; -+ mppVal = 0x00002220; /* Set MPP [3:1] to SPI mode */ -+ bootVal = MV_REG_READ(mvCtrlMppRegGet(0)); -+ bootVal &= 0xffff000f; -+ mppVal |= bootVal; -+ -+ MV_REG_WRITE(mvCtrlMppRegGet(0), mppVal); -+} -+ -+ -+/******************************************************************************* -+* mvMPPConfigToDefault - Change MPP[7:0] configuration to default configuration -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+******************************************************************************/ -+MV_VOID mvMPPConfigToDefault(MV_VOID) -+{ -+ MV_U32 mppVal = 0; -+ MV_U32 bootVal = 0; -+ -+ if(!mvCtrlIsBootFromSPIUseNAND()) -+ return; -+ mppVal = mvBoardMppGet(0); -+ bootVal = MV_REG_READ(mvCtrlMppRegGet(0)); -+ mppVal &= ~0xffff000f; -+ bootVal &= 0xffff000f; -+ mppVal |= bootVal; -+ -+ MV_REG_WRITE(mvCtrlMppRegGet(0), mppVal); -+} -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,185 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvCtrlEnvLibh -+#define __INCmvCtrlEnvLibh -+ -+/* includes */ -+#include "mvSysHwConfig.h" -+#include "mvCommon.h" -+#include "mvTypes.h" -+#include "mvOs.h" -+#include "boardEnv/mvBoardEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+#include "ctrlEnv/mvCtrlEnvRegs.h" -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+ -+ -+/* typedefs */ -+ -+/* This enumerator describes the possible HW cache coherency policies the */ -+/* controllers supports. */ -+typedef enum _mvCachePolicy -+{ -+ NO_COHERENCY, /* No HW cache coherency support */ -+ WT_COHERENCY, /* HW cache coherency supported in Write Through policy */ -+ WB_COHERENCY /* HW cache coherency supported in Write Back policy */ -+}MV_CACHE_POLICY; -+ -+ -+/* The swapping is referred to a 64-bit words (as this is the controller */ -+/* internal data path width). This enumerator describes the possible */ -+/* data swap types. Below is an example of the data 0x0011223344556677 */ -+typedef enum _mvSwapType -+{ -+ MV_BYTE_SWAP, /* Byte Swap 77 66 55 44 33 22 11 00 */ -+ MV_NO_SWAP, /* No swapping 00 11 22 33 44 55 66 77 */ -+ MV_BYTE_WORD_SWAP, /* Both byte and word swap 33 22 11 00 77 66 55 44 */ -+ MV_WORD_SWAP, /* Word swap 44 55 66 77 00 11 22 33 */ -+ SWAP_TYPE_MAX /* Delimiter for this enumerator */ -+}MV_SWAP_TYPE; -+ -+/* This structure describes access rights for Access protection windows */ -+/* that can be found in IDMA, XOR, Ethernet and MPSC units. */ -+/* Note that the permission enumerator coresponds to its register format. */ -+/* For example, Read only premission is presented as "1" in register field. */ -+typedef enum _mvAccessRights -+{ -+ NO_ACCESS_ALLOWED = 0, /* No access allowed */ -+ READ_ONLY = 1, /* Read only permission */ -+ ACC_RESERVED = 2, /* Reserved access right */ -+ FULL_ACCESS = 3, /* Read and Write permission */ -+ MAX_ACC_RIGHTS -+}MV_ACCESS_RIGHTS; -+ -+ -+/* mcspLib.h API list */ -+ -+MV_STATUS mvCtrlEnvInit(MV_VOID); -+MV_U32 mvCtrlMppRegGet(MV_U32 mppGroup); -+ -+#if defined(MV_INCLUDE_PEX) -+MV_U32 mvCtrlPexMaxIfGet(MV_VOID); -+#else -+#define mvCtrlPexMaxIfGet() (0) -+#endif -+ -+#define mvCtrlPciIfMaxIfGet() (0) -+ -+#if defined(MV_INCLUDE_GIG_ETH) -+MV_U32 mvCtrlEthMaxPortGet(MV_VOID); -+#endif -+#if defined(MV_INCLUDE_XOR) -+MV_U32 mvCtrlXorMaxChanGet(MV_VOID); -+#endif -+#if defined(MV_INCLUDE_USB) -+MV_U32 mvCtrlUsbMaxGet(MV_VOID); -+#endif -+#if defined(MV_INCLUDE_NAND) -+MV_U32 mvCtrlNandSupport(MV_VOID); -+#endif -+#if defined(MV_INCLUDE_SDIO) -+MV_U32 mvCtrlSdioSupport(MV_VOID); -+#endif -+#if defined(MV_INCLUDE_TS) -+MV_U32 mvCtrlTsSupport(MV_VOID); -+#endif -+#if defined(MV_INCLUDE_AUDIO) -+MV_U32 mvCtrlAudioSupport(MV_VOID); -+#endif -+#if defined(MV_INCLUDE_TDM) -+MV_U32 mvCtrlTdmSupport(MV_VOID); -+#endif -+ -+MV_U16 mvCtrlModelGet(MV_VOID); -+MV_U8 mvCtrlRevGet(MV_VOID); -+MV_STATUS mvCtrlNameGet(char *pNameBuff); -+MV_U32 mvCtrlModelRevGet(MV_VOID); -+MV_STATUS mvCtrlModelRevNameGet(char *pNameBuff); -+MV_VOID mvCtrlAddrDecShow(MV_VOID); -+const MV_8* mvCtrlTargetNameGet(MV_TARGET target); -+MV_U32 ctrlSizeToReg(MV_U32 size, MV_U32 alignment); -+MV_U32 ctrlRegToSize(MV_U32 regSize, MV_U32 alignment); -+MV_U32 ctrlSizeRegRoundUp(MV_U32 size, MV_U32 alignment); -+MV_U32 mvCtrlSysRstLengthCounterGet(MV_VOID); -+MV_STATUS ctrlWinOverlapTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2); -+MV_STATUS ctrlWinWithinWinTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2); -+ -+MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable); -+MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index); -+MV_VOID mvCtrlPwrMemSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable); -+MV_BOOL mvCtrlIsBootFromSPI(MV_VOID); -+MV_BOOL mvCtrlIsBootFromSPIUseNAND(MV_VOID); -+MV_BOOL mvCtrlIsBootFromNAND(MV_VOID); -+#if defined(MV_INCLUDE_CLK_PWR_CNTRL) -+MV_VOID mvCtrlPwrSaveOn(MV_VOID); -+MV_VOID mvCtrlPwrSaveOff(MV_VOID); -+#endif -+MV_BOOL mvCtrlPwrMemGet(MV_UNIT_ID unitId, MV_U32 index); -+MV_VOID mvMPPConfigToSPI(MV_VOID); -+MV_VOID mvMPPConfigToDefault(MV_VOID); -+ -+ -+#endif /* __INCmvCtrlEnvLibh */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,419 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvCtrlEnvRegsh -+#define __INCmvCtrlEnvRegsh -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* CV Support */ -+#define PEX0_MEM0 PEX0_MEM -+#define PCI0_MEM0 PEX0_MEM -+ -+/* Controller revision info */ -+#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 -+#define PCCRIR_REVID_OFFS 0 /* Revision ID */ -+#define PCCRIR_REVID_MASK (0xff << PCCRIR_REVID_OFFS) -+ -+/* Controler environment registers offsets */ -+ -+/* Power Managment Control */ -+#define POWER_MNG_MEM_CTRL_REG 0x20118 -+ -+#define PMC_GESTOPMEM_OFFS(port) ((port)? 13 : 0) -+#define PMC_GESTOPMEM_MASK(port) (1 << PMC_GESTOPMEM_OFFS(port)) -+#define PMC_GESTOPMEM_EN(port) (0 << PMC_GESTOPMEM_OFFS(port)) -+#define PMC_GESTOPMEM_STOP(port) (1 << PMC_GESTOPMEM_OFFS(port)) -+ -+#define PMC_PEXSTOPMEM_OFFS 1 -+#define PMC_PEXSTOPMEM_MASK (1 << PMC_PEXSTOPMEM_OFFS) -+#define PMC_PEXSTOPMEM_EN (0 << PMC_PEXSTOPMEM_OFFS) -+#define PMC_PEXSTOPMEM_STOP (1 << PMC_PEXSTOPMEM_OFFS) -+ -+#define PMC_USBSTOPMEM_OFFS 2 -+#define PMC_USBSTOPMEM_MASK (1 << PMC_USBSTOPMEM_OFFS) -+#define PMC_USBSTOPMEM_EN (0 << PMC_USBSTOPMEM_OFFS) -+#define PMC_USBSTOPMEM_STOP (1 << PMC_USBSTOPMEM_OFFS) -+ -+#define PMC_DUNITSTOPMEM_OFFS 3 -+#define PMC_DUNITSTOPMEM_MASK (1 << PMC_DUNITSTOPMEM_OFFS) -+#define PMC_DUNITSTOPMEM_EN (0 << PMC_DUNITSTOPMEM_OFFS) -+#define PMC_DUNITSTOPMEM_STOP (1 << PMC_DUNITSTOPMEM_OFFS) -+ -+#define PMC_RUNITSTOPMEM_OFFS 4 -+#define PMC_RUNITSTOPMEM_MASK (1 << PMC_RUNITSTOPMEM_OFFS) -+#define PMC_RUNITSTOPMEM_EN (0 << PMC_RUNITSTOPMEM_OFFS) -+#define PMC_RUNITSTOPMEM_STOP (1 << PMC_RUNITSTOPMEM_OFFS) -+ -+#define PMC_XORSTOPMEM_OFFS(port) (5+(port*2)) -+#define PMC_XORSTOPMEM_MASK(port) (1 << PMC_XORSTOPMEM_OFFS(port)) -+#define PMC_XORSTOPMEM_EN(port) (0 << PMC_XORSTOPMEM_OFFS(port)) -+#define PMC_XORSTOPMEM_STOP(port) (1 << PMC_XORSTOPMEM_OFFS(port)) -+ -+#define PMC_SATASTOPMEM_OFFS(port) (6+(port*5)) -+#define PMC_SATASTOPMEM_MASK(port) (1 << PMC_SATASTOPMEM_OFFS(port)) -+#define PMC_SATASTOPMEM_EN(port) (0 << PMC_SATASTOPMEM_OFFS(port)) -+#define PMC_SATASTOPMEM_STOP(port) (1 << PMC_SATASTOPMEM_OFFS(port)) -+ -+#define PMC_SESTOPMEM_OFFS 8 -+#define PMC_SESTOPMEM_MASK (1 << PMC_SESTOPMEM_OFFS) -+#define PMC_SESTOPMEM_EN (0 << PMC_SESTOPMEM_OFFS) -+#define PMC_SESTOPMEM_STOP (1 << PMC_SESTOPMEM_OFFS) -+ -+#define PMC_AUDIOSTOPMEM_OFFS 9 -+#define PMC_AUDIOSTOPMEM_MASK (1 << PMC_AUDIOSTOPMEM_OFFS) -+#define PMC_AUDIOSTOPMEM_EN (0 << PMC_AUDIOSTOPMEM_OFFS) -+#define PMC_AUDIOSTOPMEM_STOP (1 << PMC_AUDIOSTOPMEM_OFFS) -+ -+#define POWER_MNG_CTRL_REG 0x2011C -+ -+#define PMC_GESTOPCLOCK_OFFS(port) ((port)? 19 : 0) -+#define PMC_GESTOPCLOCK_MASK(port) (1 << PMC_GESTOPCLOCK_OFFS(port)) -+#define PMC_GESTOPCLOCK_EN(port) (1 << PMC_GESTOPCLOCK_OFFS(port)) -+#define PMC_GESTOPCLOCK_STOP(port) (0 << PMC_GESTOPCLOCK_OFFS(port)) -+ -+#define PMC_PEXPHYSTOPCLOCK_OFFS 1 -+#define PMC_PEXPHYSTOPCLOCK_MASK (1 << PMC_PEXPHYSTOPCLOCK_OFFS) -+#define PMC_PEXPHYSTOPCLOCK_EN (1 << PMC_PEXPHYSTOPCLOCK_OFFS) -+#define PMC_PEXPHYSTOPCLOCK_STOP (0 << PMC_PEXPHYSTOPCLOCK_OFFS) -+ -+#define PMC_PEXSTOPCLOCK_OFFS 2 -+#define PMC_PEXSTOPCLOCK_MASK (1 << PMC_PEXSTOPCLOCK_OFFS) -+#define PMC_PEXSTOPCLOCK_EN (1 << PMC_PEXSTOPCLOCK_OFFS) -+#define PMC_PEXSTOPCLOCK_STOP (0 << PMC_PEXSTOPCLOCK_OFFS) -+ -+#define PMC_USBSTOPCLOCK_OFFS 3 -+#define PMC_USBSTOPCLOCK_MASK (1 << PMC_USBSTOPCLOCK_OFFS) -+#define PMC_USBSTOPCLOCK_EN (1 << PMC_USBSTOPCLOCK_OFFS) -+#define PMC_USBSTOPCLOCK_STOP (0 << PMC_USBSTOPCLOCK_OFFS) -+ -+#define PMC_SDIOSTOPCLOCK_OFFS 4 -+#define PMC_SDIOSTOPCLOCK_MASK (1 << PMC_SDIOSTOPCLOCK_OFFS) -+#define PMC_SDIOSTOPCLOCK_EN (1 << PMC_SDIOSTOPCLOCK_OFFS) -+#define PMC_SDIOSTOPCLOCK_STOP (0 << PMC_SDIOSTOPCLOCK_OFFS) -+ -+#define PMC_TSSTOPCLOCK_OFFS 5 -+#define PMC_TSSTOPCLOCK_MASK (1 << PMC_TSSTOPCLOCK_OFFS) -+#define PMC_TSSTOPCLOCK_EN (1 << PMC_TSSTOPCLOCK_OFFS) -+#define PMC_TSSTOPCLOCK_STOP (0 << PMC_TSSTOPCLOCK_OFFS) -+ -+#define PMC_AUDIOSTOPCLOCK_OFFS 9 -+#define PMC_AUDIOSTOPCLOCK_MASK (1 << PMC_AUDIOSTOPCLOCK_OFFS) -+#define PMC_AUDIOSTOPCLOCK_EN (1 << PMC_AUDIOSTOPCLOCK_OFFS) -+#define PMC_AUDIOSTOPCLOCK_STOP (0 << PMC_AUDIOSTOPCLOCK_OFFS) -+ -+#define PMC_POWERSAVE_OFFS 11 -+#define PMC_POWERSAVE_MASK (1 << PMC_POWERSAVE_OFFS) -+#define PMC_POWERSAVE_EN (1 << PMC_POWERSAVE_OFFS) -+#define PMC_POWERSAVE_STOP (0 << PMC_POWERSAVE_OFFS) -+ -+ -+ -+ -+#define PMC_SATASTOPCLOCK_OFFS(port) (14+(port)) -+#define PMC_SATASTOPCLOCK_MASK(port) (1 << PMC_SATASTOPCLOCK_OFFS(port)) -+#define PMC_SATASTOPCLOCK_EN(port) (1 << PMC_SATASTOPCLOCK_OFFS(port)) -+#define PMC_SATASTOPCLOCK_STOP(port) (0 << PMC_SATASTOPCLOCK_OFFS(port)) -+ -+#define PMC_SESTOPCLOCK_OFFS 17 -+#define PMC_SESTOPCLOCK_MASK (1 << PMC_SESTOPCLOCK_OFFS) -+#define PMC_SESTOPCLOCK_EN (1 << PMC_SESTOPCLOCK_OFFS) -+#define PMC_SESTOPCLOCK_STOP (0 << PMC_SESTOPCLOCK_OFFS) -+ -+#define PMC_TDMSTOPCLOCK_OFFS 20 -+#define PMC_TDMSTOPCLOCK_MASK (1 << PMC_TDMSTOPCLOCK_OFFS) -+#define PMC_TDMSTOPCLOCK_EN (1 << PMC_TDMSTOPCLOCK_OFFS) -+#define PMC_TDMSTOPCLOCK_STOP (0 << PMC_TDMSTOPCLOCK_OFFS) -+ -+ -+/* Controler environment registers offsets */ -+#define MPP_CONTROL_REG0 0x10000 -+#define MPP_CONTROL_REG1 0x10004 -+#define MPP_CONTROL_REG2 0x10008 -+#define MPP_CONTROL_REG3 0x1000C -+#define MPP_CONTROL_REG4 0x10010 -+#define MPP_CONTROL_REG5 0x10014 -+#define MPP_CONTROL_REG6 0x10018 -+#define MPP_SAMPLE_AT_RESET 0x10030 -+#define CHIP_BOND_REG 0x10034 -+#define SYSRST_LENGTH_COUNTER_REG 0x10050 -+#define SLCR_COUNT_OFFS 0 -+#define SLCR_COUNT_MASK (0x1FFFFFFF << SLCR_COUNT_OFFS) -+#define SLCR_CLR_OFFS 31 -+#define SLCR_CLR_MASK (1 << SLCR_CLR_OFFS) -+#define PCKG_OPT_MASK 0x3 -+#define MPP_OUTPUT_DRIVE_REG 0x100E0 -+#define MPP_RGMII0_OUTPUT_DRIVE_OFFS 7 -+#define MPP_3_3_RGMII0_OUTPUT_DRIVE (0x0 << MPP_RGMII0_OUTPUT_DRIVE_OFFS) -+#define MPP_1_8_RGMII0_OUTPUT_DRIVE (0x1 << MPP_RGMII0_OUTPUT_DRIVE_OFFS) -+#define MPP_RGMII1_OUTPUT_DRIVE_OFFS 15 -+#define MPP_3_3_RGMII1_OUTPUT_DRIVE (0x0 << MPP_RGMII1_OUTPUT_DRIVE_OFFS) -+#define MPP_1_8_RGMII1_OUTPUT_DRIVE (0x1 << MPP_RGMII1_OUTPUT_DRIVE_OFFS) -+ -+#define MSAR_BOOT_MODE_OFFS 12 -+#define MSAR_BOOT_MODE_MASK (0x7 << MSAR_BOOT_MODE_OFFS) -+#define MSAR_BOOT_NAND_WITH_BOOTROM (0x5 << MSAR_BOOT_MODE_OFFS) -+#define MSAR_BOOT_SPI_WITH_BOOTROM (0x4 << MSAR_BOOT_MODE_OFFS) -+#define MSAR_BOOT_SPI_USE_NAND_WITH_BOOTROM (0x2 << MSAR_BOOT_MODE_OFFS) -+ -+#define MSAR_BOOT_MODE_6180(X) (((X & 0x3000) >> 12) | \ -+ ((X & 0x2) << 1)) -+#define MSAR_BOOT_SPI_WITH_BOOTROM_6180 0x1 -+#define MSAR_BOOT_NAND_WITH_BOOTROM_6180 0x5 -+ -+#define MSAR_TCLCK_OFFS 21 -+#define MSAR_TCLCK_MASK (0x1 << MSAR_TCLCK_OFFS) -+#define MSAR_TCLCK_166 (0x1 << MSAR_TCLCK_OFFS) -+#define MSAR_TCLCK_200 (0x0 << MSAR_TCLCK_OFFS) -+ -+ -+#define MSAR_CPUCLCK_EXTRACT(X) (((X & 0x2) >> 1) | ((X & 0x400000) >> 21) | \ -+ ((X & 0x18) >> 1)) -+ -+#define MSAR_CPUCLCK_OFFS_6180 2 -+#define MSAR_CPUCLCK_MASK_6180 (0x7 << MSAR_CPUCLCK_OFFS_6180) -+ -+#define MSAR_DDRCLCK_RTIO_OFFS 5 -+#define MSAR_DDRCLCK_RTIO_MASK (0xF << MSAR_DDRCLCK_RTIO_OFFS) -+ -+#define MSAR_L2CLCK_EXTRACT(X) (((X & 0x600) >> 9) | ((X & 0x80000) >> 17)) -+ -+#ifndef MV_ASMLANGUAGE -+/* CPU clock for 6281,6192 0->Resereved */ -+#define MV_CPU_CLCK_TBL { 0, 0, 0, 0, \ -+ 600000000, 0, 800000000, 1000000000, \ -+ 0, 1200000000, 0, 0, \ -+ 1500000000, 0, 0, 0} -+ -+/* DDR clock RATIO for 6281,6192 {0,0}->Reserved */ -+#define MV_DDR_CLCK_RTIO_TBL {\ -+ {0, 0}, {0, 0}, {2, 1}, {0, 0}, \ -+ {3, 1}, {0, 0}, {4, 1}, {9, 2}, \ -+ {5, 1}, {6, 1}, {0, 0}, {0, 0}, \ -+ {0, 0}, {0, 0}, {0, 0}, {0, 0} \ -+} -+ -+/* L2 clock RATIO for 6281,6192 {1,1}->Reserved */ -+#define MV_L2_CLCK_RTIO_TBL {\ -+ {0, 0}, {2, 1}, {0, 0}, {3, 1}, \ -+ {0, 0}, {0, 0}, {0, 0}, {0, 0} \ -+} -+ -+/* 6180 have different clk reset sampling */ -+/* ARM CPU, DDR, L2 clock for 6180 {0,0,0}->Reserved */ -+#define MV_CPU6180_DDR_L2_CLCK_TBL { \ -+ {0, 0, 0 },\ -+ {0, 0, 0 },\ -+ {0, 0, 0 },\ -+ {0, 0, 0 },\ -+ {0, 0, 0 },\ -+ {600000000, 200000000, 300000000 },\ -+ {800000000, 200000000, 400000000 },\ -+ {0, 0, 0 }\ -+} -+ -+ -+ -+/* These macros help units to identify a target Mbus Arbiter group */ -+#define MV_TARGET_IS_DRAM(target) \ -+ ((target >= SDRAM_CS0) && (target <= SDRAM_CS3)) -+ -+#define MV_TARGET_IS_PEX0(target) \ -+ ((target >= PEX0_MEM) && (target <= PEX0_IO)) -+ -+#define MV_TARGET_IS_PEX1(target) 0 -+ -+#define MV_TARGET_IS_PEX(target) (MV_TARGET_IS_PEX0(target) || MV_TARGET_IS_PEX1(target)) -+ -+#define MV_TARGET_IS_DEVICE(target) \ -+ ((target >= DEVICE_CS0) && (target <= DEVICE_CS3)) -+ -+#define MV_PCI_DRAM_BAR_TO_DRAM_TARGET(bar) 0 -+ -+#define MV_TARGET_IS_AS_BOOT(target) ((target) == (sampleAtResetTargetArray[ \ -+ (mvCtrlModelGet() == MV_6180_DEV_ID)? MSAR_BOOT_MODE_6180 \ -+ (MV_REG_READ(MPP_SAMPLE_AT_RESET)):((MV_REG_READ(MPP_SAMPLE_AT_RESET)\ -+ & MSAR_BOOT_MODE_MASK) >> MSAR_BOOT_MODE_OFFS)])) -+ -+ -+#define MV_CHANGE_BOOT_CS(target) (((target) == DEV_BOOCS)?\ -+ sampleAtResetTargetArray[(mvCtrlModelGet() == MV_6180_DEV_ID)? \ -+ MSAR_BOOT_MODE_6180(MV_REG_READ(MPP_SAMPLE_AT_RESET)): \ -+ ((MV_REG_READ(MPP_SAMPLE_AT_RESET) & MSAR_BOOT_MODE_MASK)\ -+ >> MSAR_BOOT_MODE_OFFS)]:(target)) -+ -+#define TCLK_TO_COUNTER_RATIO 1 /* counters running in Tclk */ -+ -+#define BOOT_TARGETS_NAME_ARRAY { \ -+ TBL_TERM, \ -+ TBL_TERM, \ -+ BOOT_ROM_CS, \ -+ TBL_TERM, \ -+ BOOT_ROM_CS, \ -+ BOOT_ROM_CS, \ -+ TBL_TERM, \ -+ TBL_TERM \ -+} -+ -+#define BOOT_TARGETS_NAME_ARRAY_6180 { \ -+ TBL_TERM, \ -+ BOOT_ROM_CS, \ -+ TBL_TERM, \ -+ TBL_TERM, \ -+ TBL_TERM, \ -+ BOOT_ROM_CS, \ -+ TBL_TERM, \ -+ TBL_TERM \ -+} -+ -+ -+/* For old competability */ -+#define DEVICE_CS0 NFLASH_CS -+#define DEVICE_CS1 SPI_CS -+#define DEVICE_CS2 BOOT_ROM_CS -+#define DEVICE_CS3 DEV_BOOCS -+#define MV_BOOTDEVICE_INDEX 0 -+ -+#define START_DEV_CS DEV_CS0 -+#define DEV_TO_TARGET(dev) ((dev) + DEVICE_CS0) -+ -+#define PCI_IF0_MEM0 PEX0_MEM -+#define PCI_IF0_IO PEX0_IO -+ -+ -+/* This enumerator defines the Marvell controller target ID */ -+typedef enum _mvTargetId -+{ -+ DRAM_TARGET_ID = 0 , /* Port 0 -> DRAM interface */ -+ DEV_TARGET_ID = 1, /* Port 1 -> Nand/SPI */ -+ PEX0_TARGET_ID = 4 , /* Port 4 -> PCI Express0 */ -+ CRYPT_TARGET_ID = 3 , /* Port 3 --> Crypto Engine */ -+ SAGE_TARGET_ID = 12 , /* Port 12 -> SAGE Unit */ -+ MAX_TARGETS_ID -+}MV_TARGET_ID; -+ -+ -+/* This enumerator described the possible Controller paripheral targets. */ -+/* Controller peripherals are designated memory/IO address spaces that the */ -+/* controller can access. They are also refered as "targets" */ -+typedef enum _mvTarget -+{ -+ TBL_TERM = -1, /* none valid target, used as targets list terminator*/ -+ SDRAM_CS0, /* SDRAM chip select 0 */ -+ SDRAM_CS1, /* SDRAM chip select 1 */ -+ SDRAM_CS2, /* SDRAM chip select 2 */ -+ SDRAM_CS3, /* SDRAM chip select 3 */ -+ PEX0_MEM, /* PCI Express 0 Memory */ -+ PEX0_IO, /* PCI Express 0 IO */ -+ INTER_REGS, /* Internal registers */ -+ NFLASH_CS, /* NFLASH_CS */ -+ SPI_CS, /* SPI_CS */ -+ BOOT_ROM_CS, /* BOOT_ROM_CS */ -+ DEV_BOOCS, /* DEV_BOOCS */ -+ CRYPT_ENG, /* Crypto Engine */ -+#ifdef MV_INCLUDE_SAGE -+ SAGE_UNIT, /* SAGE Unit */ -+#endif -+ MAX_TARGETS -+ -+}MV_TARGET; -+ -+#define TARGETS_DEF_ARRAY { \ -+ {0x0E, DRAM_TARGET_ID }, /* SDRAM_CS0 */ \ -+ {0x0D, DRAM_TARGET_ID }, /* SDRAM_CS1 */ \ -+ {0x0B, DRAM_TARGET_ID }, /* SDRAM_CS0 */ \ -+ {0x07, DRAM_TARGET_ID }, /* SDRAM_CS1 */ \ -+ {0xE8, PEX0_TARGET_ID }, /* PEX0_MEM */ \ -+ {0xE0, PEX0_TARGET_ID }, /* PEX0_IO */ \ -+ {0xFF, 0xFF }, /* INTER_REGS */ \ -+ {0x2F, DEV_TARGET_ID }, /* NFLASH_CS */ \ -+ {0x1E, DEV_TARGET_ID }, /* SPI_CS */ \ -+ {0x1D, DEV_TARGET_ID }, /* BOOT_ROM_CS */ \ -+ {0x1E, DEV_TARGET_ID }, /* DEV_BOOCS */ \ -+ {0x01, CRYPT_TARGET_ID}, /* CRYPT_ENG */ \ -+ {0x00, SAGE_TARGET_ID } \ -+} -+ -+ -+#define TARGETS_NAME_ARRAY { \ -+ "SDRAM_CS0", /* SDRAM_CS0 */ \ -+ "SDRAM_CS1", /* SDRAM_CS1 */ \ -+ "SDRAM_CS2", /* SDRAM_CS2 */ \ -+ "SDRAM_CS3", /* SDRAM_CS3 */ \ -+ "PEX0_MEM", /* PEX0_MEM */ \ -+ "PEX0_IO", /* PEX0_IO */ \ -+ "INTER_REGS", /* INTER_REGS */ \ -+ "NFLASH_CS", /* NFLASH_CS */ \ -+ "SPI_CS", /* SPI_CS */ \ -+ "BOOT_ROM_CS", /* BOOT_ROM_CS */ \ -+ "DEV_BOOTCS", /* DEV_BOOCS */ \ -+ "CRYPT_ENG", /* CRYPT_ENG */ \ -+ "SAGE_UNIT" /* SAGE_UNIT */ \ -+} -+#endif /* MV_ASMLANGUAGE */ -+ -+ -+#endif -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,257 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvCtrlEnvSpech -+#define __INCmvCtrlEnvSpech -+ -+#include "mvDeviceId.h" -+#include "mvSysHwConfig.h" -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+#define MV_ARM_SOC -+#define SOC_NAME_PREFIX "MV88F" -+ -+ -+/* units base and port numbers */ -+#ifdef MV_ASMLANGUAGE -+#define XOR_UNIT_BASE(unit) 0x60800 -+#else -+#define MV_XOR_REG_BASE 0x60000 -+#define XOR_UNIT_BASE(unit) ((unit)? 0x60900:0x60800) -+#endif -+ -+#define TDM_REG_BASE 0xD0000 -+#define USB_REG_BASE(dev) 0x50000 -+#define AUDIO_REG_BASE 0xA0000 -+#define SATA_REG_BASE 0x80000 -+#define MV_CESA_REG_BASE 0x3D000 -+#define MV_CESA_TDMA_REG_BASE 0x30000 -+#define MV_SDIO_REG_BASE 0x90000 -+#define MV_ETH_REG_BASE(port) (((port) == 0) ? 0x72000 : 0x76000) -+#define MV_UART_CHAN_BASE(chanNum) (0x12000 + (chanNum * 0x100)) -+#define DRAM_BASE 0x0 -+#define CNTMR_BASE 0x20300 -+#define TWSI_SLAVE_BASE(chanNum) 0x11000 -+#define PEX_IF_BASE(pexIf) 0x40000 -+#define MPP_REG_BASE 0x10000 -+#define TSU_GLOBAL_REG_BASE 0xB4000 -+#define MAX_AHB_TO_MBUS_REG_BASE 0x20000 -+ -+#define INTER_REGS_SIZE _1M -+/* This define describes the TWSI interrupt bit and location */ -+#define TWSI_CPU_MAIN_INT_CAUSE_REG 0x20200 -+#define TWSI0_CPU_MAIN_INT_BIT (1<<29) -+#define TWSI_SPEED 100000 -+ -+#define MV_GPP_MAX_GROUP 2 -+#define MV_CNTMR_MAX_COUNTER 2 -+#define MV_UART_MAX_CHAN 2 -+#define MV_XOR_MAX_UNIT 2 -+#define MV_XOR_MAX_CHAN 4 /* total channels for all units together*/ -+#define MV_XOR_MAX_CHAN_PER_UNIT 2 /* channels for units */ -+#define MV_SATA_MAX_CHAN 2 -+ -+#define MV_6281_MPP_MAX_MODULE 2 -+#define MV_6192_MPP_MAX_MODULE 1 -+#define MV_6190_MPP_MAX_MODULE 1 -+#define MV_6180_MPP_MAX_MODULE 2 -+#define MV_6281_MPP_MAX_GROUP 7 -+#define MV_6192_MPP_MAX_GROUP 4 -+#define MV_6190_MPP_MAX_GROUP 4 -+#define MV_6180_MPP_MAX_GROUP 3 -+ -+#define MV_DRAM_MAX_CS 4 -+ -+/* This define describes the maximum number of supported PCI\PCIX Interfaces*/ -+#define MV_PCI_MAX_IF 0 -+#define MV_PCI_START_IF 0 -+ -+/* This define describes the maximum number of supported PEX Interfaces */ -+#define MV_INCLUDE_PEX0 -+#define MV_DISABLE_PEX_DEVICE_BAR -+#define MV_PEX_MAX_IF 1 -+#define MV_PEX_START_IF MV_PCI_MAX_IF -+ -+/* This define describes the maximum number of supported PCI Interfaces */ -+#define MV_PCI_IF_MAX_IF (MV_PEX_MAX_IF+MV_PCI_MAX_IF) -+ -+#define MV_ETH_MAX_PORTS 2 -+#define MV_6281_ETH_MAX_PORTS 2 -+#define MV_6192_ETH_MAX_PORTS 2 -+#define MV_6190_ETH_MAX_PORTS 1 -+#define MV_6180_ETH_MAX_PORTS 1 -+ -+#define MV_IDMA_MAX_CHAN 0 -+ -+#define MV_USB_MAX_PORTS 1 -+ -+#define MV_USB_VERSION 1 -+ -+ -+#define MV_6281_NAND 1 -+#define MV_6192_NAND 1 -+#define MV_6190_NAND 1 -+#define MV_6180_NAND 0 -+ -+#define MV_6281_SDIO 1 -+#define MV_6192_SDIO 1 -+#define MV_6190_SDIO 1 -+#define MV_6180_SDIO 1 -+ -+#define MV_6281_TS 1 -+#define MV_6192_TS 1 -+#define MV_6190_TS 0 -+#define MV_6180_TS 0 -+ -+#define MV_6281_AUDIO 1 -+#define MV_6192_AUDIO 1 -+#define MV_6190_AUDIO 0 -+#define MV_6180_AUDIO 1 -+ -+#define MV_6281_TDM 1 -+#define MV_6192_TDM 1 -+#define MV_6190_TDM 0 -+#define MV_6180_TDM 0 -+ -+#define MV_DEVICE_MAX_CS 4 -+ -+/* Others */ -+#define PEX_HOST_BUS_NUM(pciIf) (pciIf) -+#define PEX_HOST_DEV_NUM(pciIf) 0 -+ -+#define PCI_IO(pciIf) (PEX0_IO) -+#define PCI_MEM(pciIf, memNum) (PEX0_MEM0) -+/* CESA version #2: One channel, 2KB SRAM, TDMA */ -+#if defined(MV_CESA_CHAIN_MODE_SUPPORT) -+ #define MV_CESA_VERSION 3 -+#else -+#define MV_CESA_VERSION 2 -+#endif -+#define MV_CESA_SRAM_SIZE 2*1024 -+/* This define describes the maximum number of supported Ethernet ports */ -+#define MV_ETH_VERSION 4 -+#define MV_ETH_MAX_RXQ 8 -+#define MV_ETH_MAX_TXQ 8 -+#define MV_ETH_PORT_SGMII { MV_FALSE, MV_FALSE } -+/* This define describes the the support of USB */ -+#define MV_USB_VERSION 1 -+ -+#define MV_INCLUDE_SDRAM_CS0 -+#define MV_INCLUDE_SDRAM_CS1 -+#define MV_INCLUDE_SDRAM_CS2 -+#define MV_INCLUDE_SDRAM_CS3 -+ -+#define MV_INCLUDE_DEVICE_CS0 -+#define MV_INCLUDE_DEVICE_CS1 -+#define MV_INCLUDE_DEVICE_CS2 -+#define MV_INCLUDE_DEVICE_CS3 -+ -+#define MPP_GROUP_1_TYPE {\ -+ {0, 0, 0}, /* Reserved for AUTO */ \ -+ {0x22220000, 0x22222222, 0x2222}, /* TDM */ \ -+ {0x44440000, 0x00044444, 0x0000}, /* AUDIO */ \ -+ {0x33330000, 0x33003333, 0x0033}, /* RGMII */ \ -+ {0x33330000, 0x03333333, 0x0033}, /* GMII */ \ -+ {0x11110000, 0x11111111, 0x0001}, /* TS */ \ -+ {0x33330000, 0x33333333, 0x3333} /* MII */ \ -+} -+ -+#define MPP_GROUP_2_TYPE {\ -+ {0, 0, 0}, /* Reserved for AUTO */ \ -+ {0x22220000, 0x22222222, 0x22}, /* TDM */ \ -+ {0x44440000, 0x00044444, 0x0}, /* AUDIO */ \ -+ {0, 0, 0}, /* N_A */ \ -+ {0, 0, 0}, /* N_A */ \ -+ {0x11110000, 0x11111111, 0x01} /* TS */ \ -+} -+ -+#ifndef MV_ASMLANGUAGE -+ -+/* This enumerator defines the Marvell Units ID */ -+typedef enum _mvUnitId -+{ -+ DRAM_UNIT_ID, -+ PEX_UNIT_ID, -+ ETH_GIG_UNIT_ID, -+ USB_UNIT_ID, -+ IDMA_UNIT_ID, -+ XOR_UNIT_ID, -+ SATA_UNIT_ID, -+ TDM_UNIT_ID, -+ UART_UNIT_ID, -+ CESA_UNIT_ID, -+ SPI_UNIT_ID, -+ AUDIO_UNIT_ID, -+ SDIO_UNIT_ID, -+ TS_UNIT_ID, -+ MAX_UNITS_ID -+ -+}MV_UNIT_ID; -+ -+#endif -+ -+#endif /* __INCmvCtrlEnvSpech */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,1048 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+/* includes */ -+#include "ctrlEnv/sys/mvAhbToMbus.h" -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+ -+#undef MV_DEBUG -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+/* typedefs */ -+ -+ -+/* CPU address remap registers offsets are inconsecutive. This struct */ -+/* describes address remap register offsets */ -+typedef struct _ahbToMbusRemapRegOffs -+{ -+ MV_U32 lowRegOffs; /* Low 32-bit remap register offset */ -+ MV_U32 highRegOffs; /* High 32 bit remap register offset */ -+}AHB_TO_MBUS_REMAP_REG_OFFS; -+ -+/* locals */ -+static MV_STATUS ahbToMbusRemapRegOffsGet (MV_U32 winNum, -+ AHB_TO_MBUS_REMAP_REG_OFFS *pRemapRegs); -+ -+/******************************************************************************* -+* mvAhbToMbusInit - Initialize Ahb To Mbus Address Map ! -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK laways. -+* -+*******************************************************************************/ -+MV_STATUS mvAhbToMbusInit(void) -+{ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvAhbToMbusWinSet - Set CPU-to-peripheral winNum address window -+* -+* DESCRIPTION: -+* This function sets -+* address window, also known as address decode window. -+* A new address decode window is set for specified winNum address window. -+* If address decode window parameter structure enables the window, -+* the routine will also enable the winNum window, allowing CPU to access -+* the winNum window. -+* -+* INPUT: -+* winNum - Windows number. -+* pAddrDecWin - CPU winNum window data structure. -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_OK if CPU winNum window was set correctly, MV_ERROR in case of -+* address window overlapps with other active CPU winNum window or -+* trying to assign 36bit base address while CPU does not support that. -+* The function returns MV_NOT_SUPPORTED, if the winNum is unsupported. -+* -+*******************************************************************************/ -+MV_STATUS mvAhbToMbusWinSet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin) -+{ -+ MV_TARGET_ATTRIB targetAttribs; -+ MV_DEC_REGS decRegs; -+ -+ /* Parameter checking */ -+ if (winNum >= MAX_AHB_TO_MBUS_WINS) -+ { -+ mvOsPrintf("mvAhbToMbusWinSet: ERR. Invalid winNum %d\n", winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ -+ /* read base register*/ -+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum)); -+ } -+ else -+ { -+ decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_INTEREG_REG); -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvAhbToMbusWinSet:Error setting AHB to MBUS window %d to "\ -+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, -+ mvCtrlTargetNameGet(pAddrDecWin->target), -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ /* read control register*/ -+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ decRegs.sizeReg = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum)); -+ } -+ -+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) -+ { -+ mvOsPrintf("mvAhbToMbusWinSet:mvCtrlAddrDecToReg Failed\n"); -+ return MV_ERROR; -+ } -+ -+ /* enable\Disable */ -+ if (MV_TRUE == pAddrDecWin->enable) -+ { -+ decRegs.sizeReg |= ATMWCR_WIN_ENABLE; -+ } -+ else -+ { -+ decRegs.sizeReg &= ~ATMWCR_WIN_ENABLE; -+ } -+ -+ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); -+ -+ /* set attributes */ -+ decRegs.sizeReg &= ~ATMWCR_WIN_ATTR_MASK; -+ decRegs.sizeReg |= targetAttribs.attrib << ATMWCR_WIN_ATTR_OFFS; -+ /* set target ID */ -+ decRegs.sizeReg &= ~ATMWCR_WIN_TARGET_MASK; -+ decRegs.sizeReg |= targetAttribs.targetId << ATMWCR_WIN_TARGET_OFFS; -+ -+#if !defined(MV_RUN_FROM_FLASH) -+ /* To be on the safe side we disable the window before writing the */ -+ /* new values. */ -+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ mvAhbToMbusWinEnable(winNum,MV_FALSE); -+ } -+#endif -+ -+ /* 3) Write to address decode Base Address Register */ -+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum), decRegs.baseReg); -+ } -+ else -+ { -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_INTEREG_REG, decRegs.baseReg); -+ } -+ -+ -+ /* Internal register space have no size */ -+ /* register. Do not perform size register assigment for those targets */ -+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ /* Write to address decode Size Register */ -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), decRegs.sizeReg); -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvAhbToMbusWinGet - Get CPU-to-peripheral winNum address window -+* -+* DESCRIPTION: -+* Get the CPU peripheral winNum address window. -+* -+* INPUT: -+* winNum - Peripheral winNum enumerator -+* -+* OUTPUT: -+* pAddrDecWin - CPU winNum window information data structure. -+* -+* RETURN: -+* MV_OK if winNum exist, MV_ERROR otherwise. -+* -+*******************************************************************************/ -+MV_STATUS mvAhbToMbusWinGet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin) -+{ -+ MV_DEC_REGS decRegs; -+ MV_TARGET_ATTRIB targetAttrib; -+ -+ -+ /* Parameter checking */ -+ if (winNum >= MAX_AHB_TO_MBUS_WINS) -+ { -+ mvOsPrintf("mvAhbToMbusWinGet: ERR. Invalid winNum %d\n", winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ -+ /* Internal register space size have no size register*/ -+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ decRegs.sizeReg = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum)); -+ } -+ else -+ { -+ decRegs.sizeReg = 0; -+ } -+ -+ -+ /* Read base and size */ -+ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum)); -+ } -+ else -+ { -+ decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_INTEREG_REG); -+ } -+ -+ -+ -+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) -+ { -+ mvOsPrintf("mvAhbToMbusWinGet: mvCtrlRegToAddrDec Failed \n"); -+ return MV_ERROR; -+ } -+ -+ if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ pAddrDecWin->addrWin.size = INTER_REGS_SIZE; -+ pAddrDecWin->target = INTER_REGS; -+ pAddrDecWin->enable = MV_TRUE; -+ -+ return MV_OK; -+ } -+ -+ -+ if (decRegs.sizeReg & ATMWCR_WIN_ENABLE) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ -+ } -+ -+ -+ -+ if (-1 == pAddrDecWin->addrWin.size) -+ { -+ return MV_ERROR; -+ } -+ -+ /* attrib and targetId */ -+ targetAttrib.attrib = (decRegs.sizeReg & ATMWCR_WIN_ATTR_MASK) >> -+ ATMWCR_WIN_ATTR_OFFS; -+ targetAttrib.targetId = (decRegs.sizeReg & ATMWCR_WIN_TARGET_MASK) >> -+ ATMWCR_WIN_TARGET_OFFS; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvAhbToMbusWinTargetGet - Get Window number associated with target -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_U32 mvAhbToMbusWinTargetGet(MV_TARGET target) -+{ -+ MV_AHB_TO_MBUS_DEC_WIN decWin; -+ MV_U32 winNum; -+ -+ /* Check parameters */ -+ if (target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetGet: target %d is Illigal\n", target); -+ return 0xffffffff; -+ } -+ -+ if (INTER_REGS == target) -+ { -+ return MV_AHB_TO_MBUS_INTREG_WIN; -+ } -+ -+ for (winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS ; winNum++) -+ { -+ if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) -+ continue; -+ -+ if (mvAhbToMbusWinGet(winNum,&decWin) != MV_OK) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetGet: mvAhbToMbusWinGet fail\n"); -+ return 0xffffffff; -+ -+ } -+ -+ if (decWin.enable == MV_TRUE) -+ { -+ if (decWin.target == target) -+ { -+ return winNum; -+ } -+ -+ } -+ -+ } -+ -+ return 0xFFFFFFFF; -+ -+ -+} -+ -+/******************************************************************************* -+* mvAhbToMbusWinAvailGet - Get First Available window number. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_U32 mvAhbToMbusWinAvailGet(MV_VOID) -+{ -+ MV_AHB_TO_MBUS_DEC_WIN decWin; -+ MV_U32 winNum; -+ -+ for (winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS ; winNum++) -+ { -+ if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) -+ continue; -+ -+ if (mvAhbToMbusWinGet(winNum,&decWin) != MV_OK) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetGet: mvAhbToMbusWinGet fail\n"); -+ return 0xffffffff; -+ -+ } -+ -+ if (decWin.enable == MV_FALSE) -+ { -+ return winNum; -+ } -+ -+ } -+ -+ return 0xFFFFFFFF; -+} -+ -+ -+/******************************************************************************* -+* mvAhbToMbusWinEnable - Enable/disable a CPU address decode window -+* -+* DESCRIPTION: -+* This function enable/disable a CPU address decode window. -+* if parameter 'enable' == MV_TRUE the routine will enable the -+* window, thus enabling CPU accesses (before enabling the window it is -+* tested for overlapping). Otherwise, the window will be disabled. -+* -+* INPUT: -+* winNum - Peripheral winNum enumerator. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_ERROR if protection window number was wrong, or the window -+* overlapps other winNum window. -+* -+*******************************************************************************/ -+MV_STATUS mvAhbToMbusWinEnable(MV_U32 winNum, MV_BOOL enable) -+{ -+ -+ /* Parameter checking */ -+ if (winNum >= MAX_AHB_TO_MBUS_WINS) -+ { -+ mvOsPrintf("mvAhbToMbusWinEnable: ERR. Invalid winNum %d\n", winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ /* Internal registers bar can't be disable or enabled */ -+ if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) -+ { -+ return (enable ? MV_OK : MV_ERROR); -+ } -+ -+ if (enable == MV_TRUE) -+ { -+ /* enable the window */ -+ MV_REG_BIT_SET(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ATMWCR_WIN_ENABLE); -+ } -+ else -+ { /* Disable address decode winNum window */ -+ MV_REG_BIT_RESET(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ATMWCR_WIN_ENABLE); -+ } -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvAhbToMbusWinRemap - Set CPU remap register for address windows. -+* -+* DESCRIPTION: -+* After a CPU address hits one of PCI address decode windows there is an -+* option to remap the address to a different one. For example, CPU -+* executes a read from PCI winNum window address 0x1200.0000. This -+* can be modified so the address on the PCI bus would be 0x1400.0000 -+* Using the PCI address remap mechanism. -+* -+* INPUT: -+* winNum - Peripheral winNum enumerator. Must be a PCI winNum. -+* pAddrDecWin - CPU winNum window information data structure. -+* Note that caller has to fill in the base field only. The -+* size field is ignored. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR if winNum is not a PCI one, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_U32 mvAhbToMbusWinRemap(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 baseAddr; -+ AHB_TO_MBUS_REMAP_REG_OFFS remapRegOffs; -+ -+ MV_U32 effectiveBaseAddress=0, -+ baseAddrValue=0,windowSizeValue=0; -+ -+ -+ /* Get registers offsets of given winNum */ -+ if (MV_NO_SUCH == ahbToMbusRemapRegOffsGet(winNum, &remapRegOffs)) -+ { -+ return 0xffffffff; -+ } -+ -+ /* 1) Set address remap low */ -+ baseAddr = pAddrWin->baseLow; -+ -+ /* Check base address aligment */ -+ /* -+ if (MV_IS_NOT_ALIGN(baseAddr, ATMWRLR_REMAP_LOW_ALIGNMENT)) -+ { -+ mvOsPrintf("mvAhbToMbusPciRemap: Warning. Target base 0x%x unaligned\n", -+ baseAddr); -+ return MV_ERROR; -+ } -+ */ -+ -+ /* BaseLow[31:16] => base register [31:16] */ -+ baseAddr = baseAddr & ATMWRLR_REMAP_LOW_MASK; -+ -+ MV_REG_WRITE(remapRegOffs.lowRegOffs, baseAddr); -+ -+ MV_REG_WRITE(remapRegOffs.highRegOffs, pAddrWin->baseHigh); -+ -+ -+ baseAddrValue = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum)); -+ windowSizeValue = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum)); -+ -+ baseAddrValue &= ATMWBR_BASE_MASK; -+ windowSizeValue &=ATMWCR_WIN_SIZE_MASK; -+ -+ /* Start calculating the effective Base Address */ -+ effectiveBaseAddress = baseAddrValue ; -+ -+ /* The effective base address will be combined from the chopped (if any) -+ remap value (according to the size value and remap mechanism) and the -+ window's base address */ -+ effectiveBaseAddress |= (((windowSizeValue) | 0xffff) & pAddrWin->baseLow); -+ /* If the effectiveBaseAddress exceed the window boundaries return an -+ invalid value. */ -+ -+ if (effectiveBaseAddress > (baseAddrValue + (windowSizeValue | 0xffff))) -+ { -+ mvOsPrintf("mvAhbToMbusPciRemap: Error\n"); -+ return 0xffffffff; -+ } -+ -+ return effectiveBaseAddress; -+ -+ -+} -+/******************************************************************************* -+* mvAhbToMbusWinTargetSwap - Swap AhbToMbus windows between targets -+* -+* DESCRIPTION: -+* -+* INPUT: -+* target1 - CPU Interface target 1 -+* target2 - CPU Interface target 2 -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR if targets are illigal, or if one of the targets is not -+* associated to a valid window . -+* MV_OK otherwise. -+* -+*******************************************************************************/ -+ -+ -+MV_STATUS mvAhbToMbusWinTargetSwap(MV_TARGET target1,MV_TARGET target2) -+{ -+ MV_U32 winNum1,winNum2; -+ MV_AHB_TO_MBUS_DEC_WIN winDec1,winDec2,winDecTemp; -+ AHB_TO_MBUS_REMAP_REG_OFFS remapRegs1,remapRegs2; -+ MV_U32 remapBaseLow1=0,remapBaseLow2=0; -+ MV_U32 remapBaseHigh1=0,remapBaseHigh2=0; -+ -+ -+ /* Check parameters */ -+ if (target1 >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d is Illigal\n", target1); -+ return MV_ERROR; -+ } -+ -+ if (target2 >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d is Illigal\n", target1); -+ return MV_ERROR; -+ } -+ -+ -+ /* get window associated with this target */ -+ winNum1 = mvAhbToMbusWinTargetGet(target1); -+ -+ if (winNum1 == 0xffffffff) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d has illigal win %d\n", -+ target1,winNum1); -+ return MV_ERROR; -+ -+ } -+ -+ /* get window associated with this target */ -+ winNum2 = mvAhbToMbusWinTargetGet(target2); -+ -+ if (winNum2 == 0xffffffff) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d has illigal win %d\n", -+ target2,winNum2); -+ return MV_ERROR; -+ -+ } -+ -+ /* now Get original values of both Windows */ -+ if (MV_OK != mvAhbToMbusWinGet(winNum1,&winDec1)) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetSwap: mvAhbToMbusWinGet failed win %d\n", -+ winNum1); -+ return MV_ERROR; -+ -+ } -+ if (MV_OK != mvAhbToMbusWinGet(winNum2,&winDec2)) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetSwap: mvAhbToMbusWinGet failed win %d\n", -+ winNum2); -+ return MV_ERROR; -+ -+ } -+ -+ -+ /* disable both windows */ -+ if (MV_OK != mvAhbToMbusWinEnable(winNum1,MV_FALSE)) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetSwap: failed to enable window %d\n", -+ winNum1); -+ return MV_ERROR; -+ -+ } -+ if (MV_OK != mvAhbToMbusWinEnable(winNum2,MV_FALSE)) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetSwap: failed to enable windo %d\n", -+ winNum2); -+ return MV_ERROR; -+ -+ } -+ -+ -+ /* now swap targets */ -+ -+ /* first save winDec2 values */ -+ winDecTemp.addrWin.baseHigh = winDec2.addrWin.baseHigh; -+ winDecTemp.addrWin.baseLow = winDec2.addrWin.baseLow; -+ winDecTemp.addrWin.size = winDec2.addrWin.size; -+ winDecTemp.enable = winDec2.enable; -+ winDecTemp.target = winDec2.target; -+ -+ /* winDec2 = winDec1 */ -+ winDec2.addrWin.baseHigh = winDec1.addrWin.baseHigh; -+ winDec2.addrWin.baseLow = winDec1.addrWin.baseLow; -+ winDec2.addrWin.size = winDec1.addrWin.size; -+ winDec2.enable = winDec1.enable; -+ winDec2.target = winDec1.target; -+ -+ -+ /* winDec1 = winDecTemp */ -+ winDec1.addrWin.baseHigh = winDecTemp.addrWin.baseHigh; -+ winDec1.addrWin.baseLow = winDecTemp.addrWin.baseLow; -+ winDec1.addrWin.size = winDecTemp.addrWin.size; -+ winDec1.enable = winDecTemp.enable; -+ winDec1.target = winDecTemp.target; -+ -+ -+ /* now set the new values */ -+ -+ -+ mvAhbToMbusWinSet(winNum1,&winDec1); -+ mvAhbToMbusWinSet(winNum2,&winDec2); -+ -+ -+ -+ -+ -+ /* now we will treat the remap windows if exist */ -+ -+ -+ /* now check if one or both windows has a remap window -+ as well after the swap ! */ -+ -+ /* if a window had a remap value differnt than the base value -+ before the swap , then after the swap the remap value will be -+ equal to the base value unless both windows has a remap windows*/ -+ -+ /* first get old values */ -+ if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum1,&remapRegs1)) -+ { -+ remapBaseLow1 = MV_REG_READ(remapRegs1.lowRegOffs); -+ remapBaseHigh1 = MV_REG_READ(remapRegs1.highRegOffs); -+ -+ } -+ if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2,&remapRegs2)) -+ { -+ remapBaseLow2 = MV_REG_READ(remapRegs2.lowRegOffs); -+ remapBaseHigh2 = MV_REG_READ(remapRegs2.highRegOffs); -+ -+ -+ } -+ -+ /* now do the swap */ -+ if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum1,&remapRegs1)) -+ { -+ if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2,&remapRegs2)) -+ { -+ /* Two windows has a remap !!! so swap */ -+ -+ MV_REG_WRITE(remapRegs2.highRegOffs,remapBaseHigh1); -+ MV_REG_WRITE(remapRegs2.lowRegOffs,remapBaseLow1); -+ -+ MV_REG_WRITE(remapRegs1.highRegOffs,remapBaseHigh2); -+ MV_REG_WRITE(remapRegs1.lowRegOffs,remapBaseLow2); -+ -+ -+ -+ } -+ else -+ { -+ /* remap == base */ -+ MV_REG_WRITE(remapRegs1.highRegOffs,winDec1.addrWin.baseHigh); -+ MV_REG_WRITE(remapRegs1.lowRegOffs,winDec1.addrWin.baseLow); -+ -+ } -+ -+ } -+ else if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2,&remapRegs2)) -+ { -+ /* remap == base */ -+ MV_REG_WRITE(remapRegs2.highRegOffs,winDec2.addrWin.baseHigh); -+ MV_REG_WRITE(remapRegs2.lowRegOffs,winDec2.addrWin.baseLow); -+ -+ } -+ -+ -+ -+ return MV_OK; -+ -+ -+} -+ -+ -+ -+#if defined(MV_88F1181) -+ -+/******************************************************************************* -+* mvAhbToMbusXbarCtrlSet - Set The CPU master Xbar arbitration. -+* -+* DESCRIPTION: -+* This function sets CPU Mbus Arbiter -+* -+* INPUT: -+* pPizzaArbArray - A priority Structure describing 16 "pizza slices". At -+* each clock cycle, the crossbar arbiter samples all -+* requests and gives the bus to the next agent according -+* to the "pizza". -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_ERROR if paramers to function invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvMbusArbSet(MV_MBUS_ARB_TARGET *pPizzaArbArray) -+{ -+ MV_U32 sliceNum; -+ MV_U32 xbarCtrl = 0; -+ MV_MBUS_ARB_TARGET xbarTarget; -+ -+ /* 1) Set crossbar control low register */ -+ for (sliceNum = 0; sliceNum < MRLR_SLICE_NUM; sliceNum++) -+ { -+ xbarTarget = pPizzaArbArray[sliceNum]; -+ -+ /* sliceNum parameter check */ -+ if (xbarTarget > MAX_MBUS_ARB_TARGETS) -+ { -+ mvOsPrintf("mvAhbToMbusXbarCtrlSet: ERR. Can't set Target %d\n", -+ xbarTarget); -+ return MV_ERROR; -+ } -+ xbarCtrl |= (xbarTarget << MRLR_LOW_ARB_OFFS(sliceNum)); -+ } -+ /* Write to crossbar control low register */ -+ MV_REG_WRITE(MBUS_ARBITER_LOW_REG, xbarCtrl); -+ -+ xbarCtrl = 0; -+ -+ /* 2) Set crossbar control high register */ -+ for (sliceNum = MRLR_SLICE_NUM; -+ sliceNum < MRLR_SLICE_NUM+MRHR_SLICE_NUM; -+ sliceNum++) -+ { -+ -+ xbarTarget = pPizzaArbArray[sliceNum]; -+ -+ /* sliceNum parameter check */ -+ if (xbarTarget > MAX_MBUS_ARB_TARGETS) -+ { -+ mvOsPrintf("mvAhbToMbusXbarCtrlSet: ERR. Can't set Target %d\n", -+ xbarTarget); -+ return MV_ERROR; -+ } -+ xbarCtrl |= (xbarTarget << MRHR_HIGH_ARB_OFFS(sliceNum)); -+ } -+ /* Write to crossbar control high register */ -+ MV_REG_WRITE(MBUS_ARBITER_HIGH_REG, xbarCtrl); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvMbusArbCtrlSet - Set MBus Arbiter control register -+* -+* DESCRIPTION: -+* -+* INPUT: -+* ctrl - pointer to MV_MBUS_ARB_CTRL register -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_ERROR if paramers to function invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvMbusArbCtrlSet(MV_MBUS_ARB_CTRL *ctrl) -+{ -+ -+ if (ctrl->highPrio == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(MBUS_ARBITER_CTRL_REG, MACR_ARB_ARM_TOP); -+ } -+ else -+ { -+ MV_REG_BIT_SET(MBUS_ARBITER_CTRL_REG, MACR_ARB_ARM_TOP); -+ } -+ -+ if (ctrl->fixedRoundRobin == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(MBUS_ARBITER_CTRL_REG, MACR_ARB_TARGET_FIXED); -+ } -+ else -+ { -+ MV_REG_BIT_SET(MBUS_ARBITER_CTRL_REG, MACR_ARB_TARGET_FIXED); -+ } -+ -+ if (ctrl->starvEn == MV_FALSE) -+ { -+ MV_REG_BIT_RESET(MBUS_ARBITER_CTRL_REG, MACR_ARB_REQ_CTRL_EN); -+ } -+ else -+ { -+ MV_REG_BIT_SET(MBUS_ARBITER_CTRL_REG, MACR_ARB_REQ_CTRL_EN); -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvMbusArbCtrlGet - Get MBus Arbiter control register -+* -+* DESCRIPTION: -+* -+* INPUT: -+* ctrl - pointer to MV_MBUS_ARB_CTRL register -+* -+* OUTPUT: -+* ctrl - pointer to MV_MBUS_ARB_CTRL register -+* -+* RETURN: -+* MV_ERROR if paramers to function invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvMbusArbCtrlGet(MV_MBUS_ARB_CTRL *ctrl) -+{ -+ -+ MV_U32 ctrlReg = MV_REG_READ(MBUS_ARBITER_CTRL_REG); -+ -+ if (ctrlReg & MACR_ARB_ARM_TOP) -+ { -+ ctrl->highPrio = MV_TRUE; -+ } -+ else -+ { -+ ctrl->highPrio = MV_FALSE; -+ } -+ -+ if (ctrlReg & MACR_ARB_TARGET_FIXED) -+ { -+ ctrl->fixedRoundRobin = MV_TRUE; -+ } -+ else -+ { -+ ctrl->fixedRoundRobin = MV_FALSE; -+ } -+ -+ if (ctrlReg & MACR_ARB_REQ_CTRL_EN) -+ { -+ ctrl->starvEn = MV_TRUE; -+ } -+ else -+ { -+ ctrl->starvEn = MV_FALSE; -+ } -+ -+ -+ return MV_OK; -+} -+ -+#endif /* #if defined(MV_88F1181) */ -+ -+ -+ -+/******************************************************************************* -+* ahbToMbusRemapRegOffsGet - Get CPU address remap register offsets -+* -+* DESCRIPTION: -+* CPU to PCI address remap registers offsets are inconsecutive. -+* This function returns PCI address remap registers offsets. -+* -+* INPUT: -+* winNum - Address decode window number. See MV_U32 enumerator. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR if winNum is not a PCI one. -+* -+*******************************************************************************/ -+static MV_STATUS ahbToMbusRemapRegOffsGet(MV_U32 winNum, -+ AHB_TO_MBUS_REMAP_REG_OFFS *pRemapRegs) -+{ -+ switch (winNum) -+ { -+ case 0: -+ case 1: -+ pRemapRegs->lowRegOffs = AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum); -+ pRemapRegs->highRegOffs = AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum); -+ break; -+ case 2: -+ case 3: -+ if((mvCtrlModelGet() == MV_5281_DEV_ID) || -+ (mvCtrlModelGet() == MV_1281_DEV_ID) || -+ (mvCtrlModelGet() == MV_6183_DEV_ID) || -+ (mvCtrlModelGet() == MV_6183L_DEV_ID)) -+ { -+ pRemapRegs->lowRegOffs = AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum); -+ pRemapRegs->highRegOffs = AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum); -+ break; -+ } -+ else -+ { -+ pRemapRegs->lowRegOffs = 0; -+ pRemapRegs->highRegOffs = 0; -+ -+ DB(mvOsPrintf("ahbToMbusRemapRegOffsGet: ERR. Invalid winNum %d\n", -+ winNum)); -+ return MV_NO_SUCH; -+ } -+ default: -+ { -+ pRemapRegs->lowRegOffs = 0; -+ pRemapRegs->highRegOffs = 0; -+ -+ DB(mvOsPrintf("ahbToMbusRemapRegOffsGet: ERR. Invalid winNum %d\n", -+ winNum)); -+ return MV_NO_SUCH; -+ } -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvAhbToMbusAddDecShow - Print the AHB to MBus bridge address decode map. -+* -+* DESCRIPTION: -+* This function print the CPU address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvAhbToMbusAddDecShow(MV_VOID) -+{ -+ MV_AHB_TO_MBUS_DEC_WIN win; -+ MV_U32 winNum; -+ mvOsOutput( "\n" ); -+ mvOsOutput( "AHB To MBUS Bridge:\n" ); -+ mvOsOutput( "-------------------\n" ); -+ -+ for( winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS; winNum++ ) -+ { -+ memset( &win, 0, sizeof(MV_AHB_TO_MBUS_DEC_WIN) ); -+ -+ mvOsOutput( "win%d - ", winNum ); -+ -+ if( mvAhbToMbusWinGet( winNum, &win ) == MV_OK ) -+ { -+ if( win.enable ) -+ { -+ mvOsOutput( "%s base %08x, ", -+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); -+ mvOsOutput( "...." ); -+ mvSizePrint( win.addrWin.size ); -+ -+ mvOsOutput( "\n" ); -+ -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ } -+ } -+ -+} -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,130 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvAhbToMbush -+#define __INCmvAhbToMbush -+ -+/* includes */ -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/sys/mvAhbToMbusRegs.h" -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+ -+/* defines */ -+ -+#if defined(MV_88F1181) -+/* This enumerator defines the Marvell controller possible MBUS arbiter */ -+/* target ports. It is used to define crossbar priority scheame (pizza) */ -+typedef enum _mvMBusArbTargetId -+{ -+ DRAM_MBUS_ARB_TARGET = 0, /* Port 0 -> DRAM interface */ -+ TWSI_MBUS_ARB_TARGET = 1, /* Port 1 -> TWSI */ -+ ARM_MBUS_ARB_TARGET = 2, /* Port 2 -> ARM */ -+ PEX1_MBUS_ARB_TARGET = 3, /* Port 3 -> PCI Express 1 */ -+ PEX0_MBUS_ARB_TARGET = 4, /* Port 4 -> PCI Express0 */ -+ MAX_MBUS_ARB_TARGETS -+}MV_MBUS_ARB_TARGET; -+ -+typedef struct _mvMBusArbCtrl -+{ -+ MV_BOOL starvEn; -+ MV_BOOL highPrio; -+ MV_BOOL fixedRoundRobin; -+ -+}MV_MBUS_ARB_CTRL; -+ -+#endif /* #if defined(MV_88F1181) */ -+ -+typedef struct _mvAhbtoMbusDecWin -+{ -+ MV_TARGET target; -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+}MV_AHB_TO_MBUS_DEC_WIN; -+ -+/* mvAhbToMbus.h API list */ -+ -+MV_STATUS mvAhbToMbusInit(MV_VOID); -+MV_STATUS mvAhbToMbusWinSet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin); -+MV_STATUS mvAhbToMbusWinGet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin); -+MV_STATUS mvAhbToMbusWinEnable(MV_U32 winNum,MV_BOOL enable); -+MV_U32 mvAhbToMbusWinRemap(MV_U32 winNum, MV_ADDR_WIN *pAddrDecWin); -+MV_U32 mvAhbToMbusWinTargetGet(MV_TARGET target); -+MV_U32 mvAhbToMbusWinAvailGet(MV_VOID); -+MV_STATUS mvAhbToMbusWinTargetSwap(MV_TARGET target1,MV_TARGET target2); -+ -+#if defined(MV_88F1181) -+ -+MV_STATUS mvMbusArbSet(MV_MBUS_ARB_TARGET *pPizzaArbArray); -+MV_STATUS mvMbusArbCtrlSet(MV_MBUS_ARB_CTRL *ctrl); -+MV_STATUS mvMbusArbCtrlGet(MV_MBUS_ARB_CTRL *ctrl); -+ -+#endif /* #if defined(MV_88F1181) */ -+ -+ -+MV_VOID mvAhbToMbusAddDecShow(MV_VOID); -+ -+ -+#endif /* __INCmvAhbToMbush */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,143 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvAhbToMbusRegsh -+#define __INCmvAhbToMbusRegsh -+ -+/******************************/ -+/* ARM Address Map Registers */ -+/******************************/ -+ -+#define MAX_AHB_TO_MBUS_WINS 9 -+#define MV_AHB_TO_MBUS_INTREG_WIN 8 -+ -+ -+#define AHB_TO_MBUS_WIN_CTRL_REG(winNum) (0x20000 + (winNum)*0x10) -+#define AHB_TO_MBUS_WIN_BASE_REG(winNum) (0x20004 + (winNum)*0x10) -+#define AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum) (0x20008 + (winNum)*0x10) -+#define AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum) (0x2000C + (winNum)*0x10) -+#define AHB_TO_MBUS_WIN_INTEREG_REG 0x20080 -+ -+/* Window Control Register */ -+/* AHB_TO_MBUS_WIN_CTRL_REG (ATMWCR)*/ -+#define ATMWCR_WIN_ENABLE BIT0 /* Window Enable */ -+ -+#define ATMWCR_WIN_TARGET_OFFS 4 /* The target interface associated -+ with this window*/ -+#define ATMWCR_WIN_TARGET_MASK (0xf << ATMWCR_WIN_TARGET_OFFS) -+ -+#define ATMWCR_WIN_ATTR_OFFS 8 /* The target interface attributes -+ Associated with this window */ -+#define ATMWCR_WIN_ATTR_MASK (0xff << ATMWCR_WIN_ATTR_OFFS) -+ -+ -+/* -+Used with the Base register to set the address window size and location -+Must be programed from LSB to MSB as sequence of 1’s followed -+by sequence of 0’s. The number of 1’s specifies the size of the window -+in 64 KB granularity (e.g. a value of 0x00FF specifies 256 = 16 MB). -+ -+NOTE: A value of 0x0 specifies 64KB size. -+*/ -+#define ATMWCR_WIN_SIZE_OFFS 16 /* Window Size */ -+#define ATMWCR_WIN_SIZE_MASK (0xffff << ATMWCR_WIN_SIZE_OFFS) -+#define ATMWCR_WIN_SIZE_ALIGNMENT 0x10000 -+ -+/* Window Base Register */ -+/* AHB_TO_MBUS_WIN_BASE_REG (ATMWBR) */ -+ -+/* -+Used with the size field to set the address window size and location. -+Corresponds to transaction address[31:16] -+*/ -+#define ATMWBR_BASE_OFFS 16 /* Base Address */ -+#define ATMWBR_BASE_MASK (0xffff << ATMWBR_BASE_OFFS) -+#define ATMWBR_BASE_ALIGNMENT 0x10000 -+ -+/* Window Remap Low Register */ -+/* AHB_TO_MBUS_WIN_REMAP_LOW_REG (ATMWRLR) */ -+ -+/* -+Used with the size field to specifies address bits[31:0] to be driven to -+the target interface.: -+target_addr[31:16] = (addr[31:16] & size[15:0]) | (remap[31:16] & ~size[15:0]) -+*/ -+#define ATMWRLR_REMAP_LOW_OFFS 16 /* Remap Address */ -+#define ATMWRLR_REMAP_LOW_MASK (0xffff << ATMWRLR_REMAP_LOW_OFFS) -+#define ATMWRLR_REMAP_LOW_ALIGNMENT 0x10000 -+ -+/* Window Remap High Register */ -+/* AHB_TO_MBUS_WIN_REMAP_HIGH_REG (ATMWRHR) */ -+ -+/* -+Specifies address bits[63:32] to be driven to the target interface. -+target_addr[63:32] = (RemapHigh[31:0] -+*/ -+#define ATMWRHR_REMAP_HIGH_OFFS 0 /* Remap Address */ -+#define ATMWRHR_REMAP_HIGH_MASK (0xffffffff << ATMWRHR_REMAP_HIGH_OFFS) -+ -+ -+#endif /* __INCmvAhbToMbusRegsh */ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,1036 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+/* includes */ -+#include "ctrlEnv/sys/mvCpuIf.h" -+#include "ctrlEnv/sys/mvAhbToMbusRegs.h" -+#include "cpu/mvCpu.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "mvSysHwConfig.h" -+#include "mvSysDram.h" -+ -+/*#define MV_DEBUG*/ -+/* defines */ -+ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+/* locals */ -+/* static functions */ -+static MV_BOOL cpuTargetWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin); -+ -+MV_TARGET * sampleAtResetTargetArray; -+MV_TARGET sampleAtResetTargetArrayP[] = BOOT_TARGETS_NAME_ARRAY; -+MV_TARGET sampleAtResetTargetArray6180P[] = BOOT_TARGETS_NAME_ARRAY_6180; -+/******************************************************************************* -+* mvCpuIfInit - Initialize Controller CPU interface -+* -+* DESCRIPTION: -+* This function initialize Controller CPU interface: -+* 1. Set CPU interface configuration registers. -+* 2. Set CPU master Pizza arbiter control according to static -+* configuration described in configuration file. -+* 3. Opens CPU address decode windows. DRAM windows are assumed to be -+* already set (auto detection). -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvCpuIfInit(MV_CPU_DEC_WIN *cpuAddrWinMap) -+{ -+ MV_U32 regVal; -+ MV_TARGET target; -+ MV_ADDR_WIN addrWin; -+ -+ if (cpuAddrWinMap == NULL) -+ { -+ DB(mvOsPrintf("mvCpuIfInit:ERR. cpuAddrWinMap == NULL\n")); -+ return MV_ERROR; -+ } -+ -+ /*Initialize the boot target array according to device type*/ -+ if(mvCtrlModelGet() == MV_6180_DEV_ID) -+ sampleAtResetTargetArray = sampleAtResetTargetArray6180P; -+ else -+ sampleAtResetTargetArray = sampleAtResetTargetArrayP; -+ -+ /* Set ARM Configuration register */ -+ regVal = MV_REG_READ(CPU_CONFIG_REG); -+ regVal &= ~CPU_CONFIG_DEFAULT_MASK; -+ regVal |= CPU_CONFIG_DEFAULT; -+ MV_REG_WRITE(CPU_CONFIG_REG,regVal); -+ -+ /* First disable all CPU target windows */ -+ for (target = 0; cpuAddrWinMap[target].enable != TBL_TERM; target++) -+ { -+ if ((MV_TARGET_IS_DRAM(target))||(target == INTER_REGS)) -+ { -+ continue; -+ } -+ -+#if defined(MV_MEM_OVER_PCI_WA) || defined(MV_UART_OVER_PCI_WA) -+ /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ -+ if (MV_TARGET_IS_PCI(target)) -+ { -+ continue; -+ } -+#endif -+ -+#if defined(MV_MEM_OVER_PEX_WA) || defined(MV_UART_OVER_PEX_WA) -+ /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ -+ if (MV_TARGET_IS_PEX(target)) -+ { -+ continue; -+ } -+#endif -+#if defined(MV_RUN_FROM_FLASH) -+ /* Don't disable the boot device. */ -+ if (target == DEV_BOOCS) -+ { -+ continue; -+ } -+#endif /* MV_RUN_FROM_FLASH */ -+ mvCpuIfTargetWinEnable(MV_CHANGE_BOOT_CS(target),MV_FALSE); -+ } -+ -+#if defined(MV_RUN_FROM_FLASH) -+ /* Resize the bootcs windows before other windows, because this */ -+ /* window is enabled and will cause an overlap if not resized. */ -+ target = DEV_BOOCS; -+ -+ if (MV_OK != mvCpuIfTargetWinSet(target, &cpuAddrWinMap[target])) -+ { -+ DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinSet fail\n")); -+ return MV_ERROR; -+ } -+ -+ addrWin.baseLow = cpuAddrWinMap[target].addrWin.baseLow; -+ addrWin.baseHigh = cpuAddrWinMap[target].addrWin.baseHigh; -+ if (0xffffffff == mvAhbToMbusWinRemap(cpuAddrWinMap[target].winNum ,&addrWin)) -+ { -+ DB(mvOsPrintf("mvCpuIfInit:WARN. mvAhbToMbusWinRemap can't remap winNum=%d\n", -+ cpuAddrWinMap[target].winNum)); -+ } -+ -+#endif /* MV_RUN_FROM_FLASH */ -+ -+ /* Go through all targets in user table until table terminator */ -+ for (target = 0; cpuAddrWinMap[target].enable != TBL_TERM; target++) -+ { -+ -+#if defined(MV_RUN_FROM_FLASH) -+ if (target == DEV_BOOCS) -+ { -+ continue; -+ } -+#endif /* MV_RUN_FROM_FLASH */ -+ -+ /* if DRAM auto sizing is used do not initialized DRAM target windows, */ -+ /* assuming this already has been done earlier. */ -+#ifdef MV_DRAM_AUTO_SIZE -+ if (MV_TARGET_IS_DRAM(target)) -+ { -+ continue; -+ } -+#endif -+ -+#if defined(MV_MEM_OVER_PCI_WA) || defined(MV_UART_OVER_PCI_WA) -+ /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ -+ if (MV_TARGET_IS_PCI(target)) -+ { -+ continue; -+ } -+#endif -+ -+#if defined(MV_MEM_OVER_PEX_WA) || defined(MV_UART_OVER_PEX_WA) -+ /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ -+ if (MV_TARGET_IS_PEX(target)) -+ { -+ continue; -+ } -+#endif -+ /* If the target attribute is the same as the boot device attribute */ -+ /* then it's stays disable */ -+ if (MV_TARGET_IS_AS_BOOT(target)) -+ { -+ continue; -+ } -+ -+ if((0 == cpuAddrWinMap[target].addrWin.size) || -+ (DIS == cpuAddrWinMap[target].enable)) -+ -+ { -+ if (MV_OK != mvCpuIfTargetWinEnable(target, MV_FALSE)) -+ { -+ DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinEnable fail\n")); -+ return MV_ERROR; -+ } -+ -+ } -+ else -+ { -+ if (MV_OK != mvCpuIfTargetWinSet(target, &cpuAddrWinMap[target])) -+ { -+ DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinSet fail\n")); -+ return MV_ERROR; -+ } -+ -+ addrWin.baseLow = cpuAddrWinMap[target].addrWin.baseLow; -+ addrWin.baseHigh = cpuAddrWinMap[target].addrWin.baseHigh; -+ if (0xffffffff == mvAhbToMbusWinRemap(cpuAddrWinMap[target].winNum ,&addrWin)) -+ { -+ DB(mvOsPrintf("mvCpuIfInit:WARN. mvAhbToMbusWinRemap can't remap winNum=%d\n", -+ cpuAddrWinMap[target].winNum)); -+ } -+ -+ -+ } -+ } -+ -+ return MV_OK; -+ -+ -+} -+ -+ -+/******************************************************************************* -+* mvCpuIfTargetWinSet - Set CPU-to-peripheral target address window -+* -+* DESCRIPTION: -+* This function sets a peripheral target (e.g. SDRAM bank0, PCI0_MEM0) -+* address window, also known as address decode window. -+* A new address decode window is set for specified target address window. -+* If address decode window parameter structure enables the window, -+* the routine will also enable the target window, allowing CPU to access -+* the target window. -+* -+* INPUT: -+* target - Peripheral target enumerator. -+* pAddrDecWin - CPU target window data structure. -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_OK if CPU target window was set correctly, MV_ERROR in case of -+* address window overlapps with other active CPU target window or -+* trying to assign 36bit base address while CPU does not support that. -+* The function returns MV_NOT_SUPPORTED, if the target is unsupported. -+* -+*******************************************************************************/ -+MV_STATUS mvCpuIfTargetWinSet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin) -+{ -+ MV_AHB_TO_MBUS_DEC_WIN decWin; -+ MV_U32 existingWinNum; -+ MV_DRAM_DEC_WIN addrDecWin; -+ -+ target = MV_CHANGE_BOOT_CS(target); -+ -+ /* Check parameters */ -+ if (target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvCpuIfTargetWinSet: target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ /* 2) Check if the requested window overlaps with current windows */ -+ if (MV_TRUE == cpuTargetWinOverlap(target, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("mvCpuIfTargetWinSet: ERR. Target %d overlap\n", target); -+ return MV_BAD_PARAM; -+ } -+ -+ if (MV_TARGET_IS_DRAM(target)) -+ { -+ /* copy relevant data to MV_DRAM_DEC_WIN structure */ -+ addrDecWin.addrWin.baseHigh = pAddrDecWin->addrWin.baseHigh; -+ addrDecWin.addrWin.baseLow = pAddrDecWin->addrWin.baseLow; -+ addrDecWin.addrWin.size = pAddrDecWin->addrWin.size; -+ addrDecWin.enable = pAddrDecWin->enable; -+ -+ -+ if (mvDramIfWinSet(target,&addrDecWin) != MV_OK); -+ { -+ mvOsPrintf("mvCpuIfTargetWinSet: mvDramIfWinSet Failed\n"); -+ return MV_ERROR; -+ } -+ -+ } -+ else -+ { -+ /* copy relevant data to MV_AHB_TO_MBUS_DEC_WIN structure */ -+ decWin.addrWin.baseLow = pAddrDecWin->addrWin.baseLow; -+ decWin.addrWin.baseHigh = pAddrDecWin->addrWin.baseHigh; -+ decWin.addrWin.size = pAddrDecWin->addrWin.size; -+ decWin.enable = pAddrDecWin->enable; -+ decWin.target = target; -+ -+ existingWinNum = mvAhbToMbusWinTargetGet(target); -+ -+ /* check if there is already another Window configured -+ for this target */ -+ if ((existingWinNum < MAX_AHB_TO_MBUS_WINS )&& -+ (existingWinNum != pAddrDecWin->winNum)) -+ { -+ /* if we want to enable the new winow number -+ passed by the user , then the old one should -+ be disabled */ -+ if (MV_TRUE == pAddrDecWin->enable) -+ { -+ /* be sure it is disabled */ -+ mvAhbToMbusWinEnable(existingWinNum , MV_FALSE); -+ } -+ } -+ -+ if (mvAhbToMbusWinSet(pAddrDecWin->winNum,&decWin) != MV_OK) -+ { -+ mvOsPrintf("mvCpuIfTargetWinSet: mvAhbToMbusWinSet Failed\n"); -+ return MV_ERROR; -+ } -+ -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCpuIfTargetWinGet - Get CPU-to-peripheral target address window -+* -+* DESCRIPTION: -+* Get the CPU peripheral target address window. -+* -+* INPUT: -+* target - Peripheral target enumerator -+* -+* OUTPUT: -+* pAddrDecWin - CPU target window information data structure. -+* -+* RETURN: -+* MV_OK if target exist, MV_ERROR otherwise. -+* -+*******************************************************************************/ -+MV_STATUS mvCpuIfTargetWinGet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin) -+{ -+ -+ MV_U32 winNum=0xffffffff; -+ MV_AHB_TO_MBUS_DEC_WIN decWin; -+ MV_DRAM_DEC_WIN addrDecWin; -+ -+ target = MV_CHANGE_BOOT_CS(target); -+ -+ /* Check parameters */ -+ if (target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvCpuIfTargetWinGet: target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ if (MV_TARGET_IS_DRAM(target)) -+ { -+ if (mvDramIfWinGet(target,&addrDecWin) != MV_OK) -+ { -+ mvOsPrintf("mvCpuIfTargetWinGet: Failed to get window target %d\n", -+ target); -+ return MV_ERROR; -+ } -+ -+ /* copy relevant data to MV_CPU_DEC_WIN structure */ -+ pAddrDecWin->addrWin.baseLow = addrDecWin.addrWin.baseLow; -+ pAddrDecWin->addrWin.baseHigh = addrDecWin.addrWin.baseHigh; -+ pAddrDecWin->addrWin.size = addrDecWin.addrWin.size; -+ pAddrDecWin->enable = addrDecWin.enable; -+ pAddrDecWin->winNum = 0xffffffff; -+ -+ } -+ else -+ { -+ /* get the Window number associated with this target */ -+ -+ winNum = mvAhbToMbusWinTargetGet(target); -+ if (winNum >= MAX_AHB_TO_MBUS_WINS) -+ { -+ return MV_NO_SUCH; -+ -+ } -+ -+ if (mvAhbToMbusWinGet(winNum , &decWin) != MV_OK) -+ { -+ mvOsPrintf("%s: mvAhbToMbusWinGet Failed at winNum = %d\n", -+ __FUNCTION__, winNum); -+ return MV_ERROR; -+ -+ } -+ -+ /* copy relevant data to MV_CPU_DEC_WIN structure */ -+ pAddrDecWin->addrWin.baseLow = decWin.addrWin.baseLow; -+ pAddrDecWin->addrWin.baseHigh = decWin.addrWin.baseHigh; -+ pAddrDecWin->addrWin.size = decWin.addrWin.size; -+ pAddrDecWin->enable = decWin.enable; -+ pAddrDecWin->winNum = winNum; -+ -+ } -+ -+ -+ -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvCpuIfTargetWinEnable - Enable/disable a CPU address decode window -+* -+* DESCRIPTION: -+* This function enable/disable a CPU address decode window. -+* if parameter 'enable' == MV_TRUE the routine will enable the -+* window, thus enabling CPU accesses (before enabling the window it is -+* tested for overlapping). Otherwise, the window will be disabled. -+* -+* INPUT: -+* target - Peripheral target enumerator. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_ERROR if protection window number was wrong, or the window -+* overlapps other target window. -+* -+*******************************************************************************/ -+MV_STATUS mvCpuIfTargetWinEnable(MV_TARGET target,MV_BOOL enable) -+{ -+ MV_U32 winNum, temp; -+ MV_CPU_DEC_WIN addrDecWin; -+ -+ target = MV_CHANGE_BOOT_CS(target); -+ -+ /* Check parameters */ -+ if (target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvCpuIfTargetWinEnable: target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ /* get the window and check if it exist */ -+ temp = mvCpuIfTargetWinGet(target, &addrDecWin); -+ if (MV_NO_SUCH == temp) -+ { -+ return (enable? MV_ERROR: MV_OK); -+ } -+ else if( MV_OK != temp) -+ { -+ mvOsPrintf("%s: ERR. Getting target %d failed.\n",__FUNCTION__, target); -+ return MV_ERROR; -+ } -+ -+ -+ /* check overlap */ -+ -+ if (MV_TRUE == enable) -+ { -+ if (MV_TRUE == cpuTargetWinOverlap(target, &addrDecWin.addrWin)) -+ { -+ DB(mvOsPrintf("%s: ERR. Target %d overlap\n",__FUNCTION__, target)); -+ return MV_ERROR; -+ } -+ -+ } -+ -+ -+ if (MV_TARGET_IS_DRAM(target)) -+ { -+ if (mvDramIfWinEnable(target , enable) != MV_OK) -+ { -+ mvOsPrintf("mvCpuIfTargetWinGet: mvDramIfWinEnable Failed at \n"); -+ return MV_ERROR; -+ -+ } -+ -+ } -+ else -+ { -+ /* get the Window number associated with this target */ -+ -+ winNum = mvAhbToMbusWinTargetGet(target); -+ -+ if (winNum >= MAX_AHB_TO_MBUS_WINS) -+ { -+ return (enable? MV_ERROR: MV_OK); -+ } -+ -+ if (mvAhbToMbusWinEnable(winNum , enable) != MV_OK) -+ { -+ mvOsPrintf("mvCpuIfTargetWinGet: Failed to enable window = %d\n", -+ winNum); -+ return MV_ERROR; -+ -+ } -+ -+ } -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvCpuIfTargetWinSizeGet - Get CPU target address window size -+* -+* DESCRIPTION: -+* Get the size of CPU-to-peripheral target window. -+* -+* INPUT: -+* target - Peripheral target enumerator -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit size. Function also returns '0' if window is closed. -+* Function returns 0xFFFFFFFF in case of an error. -+* -+*******************************************************************************/ -+MV_U32 mvCpuIfTargetWinSizeGet(MV_TARGET target) -+{ -+ MV_CPU_DEC_WIN addrDecWin; -+ -+ target = MV_CHANGE_BOOT_CS(target); -+ -+ /* Check parameters */ -+ if (target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvCpuIfTargetWinSizeGet: target %d is Illigal\n", target); -+ return 0; -+ } -+ -+ /* Get the winNum window */ -+ if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) -+ { -+ mvOsPrintf("mvCpuIfTargetWinSizeGet:ERR. Getting target %d failed.\n", -+ target); -+ return 0; -+ } -+ -+ /* Check if window is enabled */ -+ if (addrDecWin.enable == MV_TRUE) -+ { -+ return (addrDecWin.addrWin.size); -+ } -+ else -+ { -+ return 0; /* Window disabled. return 0 */ -+ } -+} -+ -+/******************************************************************************* -+* mvCpuIfTargetWinBaseLowGet - Get CPU target address window base low -+* -+* DESCRIPTION: -+* CPU-to-peripheral target address window base is constructed of -+* two parts: Low and high. -+* This function gets the CPU peripheral target low base address. -+* -+* INPUT: -+* target - Peripheral target enumerator -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit low base address. -+* -+*******************************************************************************/ -+MV_U32 mvCpuIfTargetWinBaseLowGet(MV_TARGET target) -+{ -+ MV_CPU_DEC_WIN addrDecWin; -+ -+ target = MV_CHANGE_BOOT_CS(target); -+ -+ /* Check parameters */ -+ if (target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvCpuIfTargetWinBaseLowGet: target %d is Illigal\n", target); -+ return 0xffffffff; -+ } -+ -+ /* Get the target window */ -+ if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) -+ { -+ mvOsPrintf("mvCpuIfTargetWinBaseLowGet:ERR. Getting target %d failed.\n", -+ target); -+ return 0xffffffff; -+ } -+ -+ if (MV_FALSE == addrDecWin.enable) -+ { -+ return 0xffffffff; -+ } -+ return (addrDecWin.addrWin.baseLow); -+} -+ -+/******************************************************************************* -+* mvCpuIfTargetWinBaseHighGet - Get CPU target address window base high -+* -+* DESCRIPTION: -+* CPU-to-peripheral target address window base is constructed of -+* two parts: Low and high. -+* This function gets the CPU peripheral target high base address. -+* -+* INPUT: -+* target - Peripheral target enumerator -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit high base address. -+* -+*******************************************************************************/ -+MV_U32 mvCpuIfTargetWinBaseHighGet(MV_TARGET target) -+{ -+ MV_CPU_DEC_WIN addrDecWin; -+ -+ target = MV_CHANGE_BOOT_CS(target); -+ -+ /* Check parameters */ -+ if (target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvCpuIfTargetWinBaseLowGet: target %d is Illigal\n", target); -+ return 0xffffffff; -+ } -+ -+ /* Get the target window */ -+ if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) -+ { -+ mvOsPrintf("mvCpuIfTargetWinBaseHighGet:ERR. Getting target %d failed.\n", -+ target); -+ return 0xffffffff; -+ } -+ -+ if (MV_FALSE == addrDecWin.enable) -+ { -+ return 0; -+ } -+ -+ return (addrDecWin.addrWin.baseHigh); -+} -+ -+#if defined(MV_INCLUDE_PEX) -+/******************************************************************************* -+* mvCpuIfPexRemap - Set CPU remap register for address windows. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* pexTarget - Peripheral target enumerator. Must be a PEX target. -+* pAddrDecWin - CPU target window information data structure. -+* Note that caller has to fill in the base field only. The -+* size field is ignored. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR if target is not a PEX one, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_U32 mvCpuIfPexRemap(MV_TARGET pexTarget, MV_ADDR_WIN *pAddrDecWin) -+{ -+ MV_U32 winNum; -+ -+ /* Check parameters */ -+ -+ if (mvCtrlPexMaxIfGet() > 1) -+ { -+ if ((!MV_TARGET_IS_PEX1(pexTarget))&&(!MV_TARGET_IS_PEX0(pexTarget))) -+ { -+ mvOsPrintf("mvCpuIfPexRemap: target %d is Illigal\n",pexTarget); -+ return 0xffffffff; -+ } -+ -+ } -+ else -+ { -+ if (!MV_TARGET_IS_PEX0(pexTarget)) -+ { -+ mvOsPrintf("mvCpuIfPexRemap: target %d is Illigal\n",pexTarget); -+ return 0xffffffff; -+ } -+ -+ } -+ -+ /* get the Window number associated with this target */ -+ winNum = mvAhbToMbusWinTargetGet(pexTarget); -+ -+ if (winNum >= MAX_AHB_TO_MBUS_WINS) -+ { -+ mvOsPrintf("mvCpuIfPexRemap: mvAhbToMbusWinTargetGet Failed\n"); -+ return 0xffffffff; -+ -+ } -+ -+ return mvAhbToMbusWinRemap(winNum , pAddrDecWin); -+} -+ -+#endif -+ -+#if defined(MV_INCLUDE_PCI) -+/******************************************************************************* -+* mvCpuIfPciRemap - Set CPU remap register for address windows. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* pciTarget - Peripheral target enumerator. Must be a PCI target. -+* pAddrDecWin - CPU target window information data structure. -+* Note that caller has to fill in the base field only. The -+* size field is ignored. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR if target is not a PCI one, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_U32 mvCpuIfPciRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin) -+{ -+ MV_U32 winNum; -+ -+ /* Check parameters */ -+ if (!MV_TARGET_IS_PCI(pciTarget)) -+ { -+ mvOsPrintf("mvCpuIfPciRemap: target %d is Illigal\n",pciTarget); -+ return 0xffffffff; -+ } -+ -+ /* get the Window number associated with this target */ -+ winNum = mvAhbToMbusWinTargetGet(pciTarget); -+ -+ if (winNum >= MAX_AHB_TO_MBUS_WINS) -+ { -+ mvOsPrintf("mvCpuIfPciRemap: mvAhbToMbusWinTargetGet Failed\n"); -+ return 0xffffffff; -+ -+ } -+ -+ return mvAhbToMbusWinRemap(winNum , pAddrDecWin); -+} -+#endif /* MV_INCLUDE_PCI */ -+ -+ -+/******************************************************************************* -+* mvCpuIfPciIfRemap - Set CPU remap register for address windows. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* pciTarget - Peripheral target enumerator. Must be a PCI target. -+* pAddrDecWin - CPU target window information data structure. -+* Note that caller has to fill in the base field only. The -+* size field is ignored. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR if target is not a PCI one, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_U32 mvCpuIfPciIfRemap(MV_TARGET pciIfTarget, MV_ADDR_WIN *pAddrDecWin) -+{ -+#if defined(MV_INCLUDE_PEX) -+ if (MV_TARGET_IS_PEX(pciIfTarget)) -+ { -+ return mvCpuIfPexRemap(pciIfTarget,pAddrDecWin); -+ } -+#endif -+#if defined(MV_INCLUDE_PCI) -+ -+ if (MV_TARGET_IS_PCI(pciIfTarget)) -+ { -+ return mvCpuIfPciRemap(pciIfTarget,pAddrDecWin); -+ } -+#endif -+ return 0; -+} -+ -+ -+ -+/******************************************************************************* -+* mvCpuIfTargetOfBaseAddressGet - Get the target according to base address -+* -+* DESCRIPTION: -+* -+* INPUT: -+* baseAddress - base address to be checked -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* the target number that baseAddress belongs to or MAX_TARGETS is not -+* found -+* -+*******************************************************************************/ -+ -+MV_TARGET mvCpuIfTargetOfBaseAddressGet(MV_U32 baseAddress) -+{ -+ MV_CPU_DEC_WIN win; -+ MV_U32 target; -+ -+ for( target = 0; target < MAX_TARGETS; target++ ) -+ { -+ if( mvCpuIfTargetWinGet( target, &win ) == MV_OK ) -+ { -+ if( win.enable ) -+ { -+ if ((baseAddress >= win.addrWin.baseLow) && -+ (baseAddress < win.addrWin.baseLow + win.addrWin.size)) break; -+ } -+ } -+ else return MAX_TARGETS; -+ -+ } -+ -+ return target; -+} -+/******************************************************************************* -+* cpuTargetWinOverlap - Detect CPU address decode windows overlapping -+* -+* DESCRIPTION: -+* An unpredicted behaviur is expected in case CPU address decode -+* windows overlapps. -+* This function detects CPU address decode windows overlapping of a -+* specified target. The function does not check the target itself for -+* overlapping. The function also skipps disabled address decode windows. -+* -+* INPUT: -+* target - Peripheral target enumerator. -+* pAddrDecWin - An address decode window struct. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlaps current address -+* decode map, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+static MV_BOOL cpuTargetWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 targetNum; -+ MV_CPU_DEC_WIN addrDecWin; -+ MV_STATUS status; -+ -+ -+ for(targetNum = 0; targetNum < MAX_TARGETS; targetNum++) -+ { -+#if defined(MV_RUN_FROM_FLASH) -+ if(MV_TARGET_IS_AS_BOOT(target)) -+ { -+ if (MV_CHANGE_BOOT_CS(targetNum) == target) -+ continue; -+ } -+#endif /* MV_RUN_FROM_FLASH */ -+ -+ /* don't check our target or illegal targets */ -+ if (targetNum == target) -+ { -+ continue; -+ } -+ -+ /* Get window parameters */ -+ status = mvCpuIfTargetWinGet(targetNum, &addrDecWin); -+ if(MV_NO_SUCH == status) -+ { -+ continue; -+ } -+ if(MV_OK != status) -+ { -+ DB(mvOsPrintf("cpuTargetWinOverlap: ERR. TargetWinGet failed\n")); -+ return MV_TRUE; -+ } -+ -+ /* Do not check disabled windows */ -+ if (MV_FALSE == addrDecWin.enable) -+ { -+ continue; -+ } -+ -+ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) -+ { -+ DB(mvOsPrintf( -+ "cpuTargetWinOverlap: Required target %d overlap current %d\n", -+ target, targetNum)); -+ return MV_TRUE; -+ } -+ } -+ -+ return MV_FALSE; -+ -+} -+ -+/******************************************************************************* -+* mvCpuIfAddDecShow - Print the CPU address decode map. -+* -+* DESCRIPTION: -+* This function print the CPU address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvCpuIfAddDecShow(MV_VOID) -+{ -+ MV_CPU_DEC_WIN win; -+ MV_U32 target; -+ mvOsOutput( "\n" ); -+ mvOsOutput( "CPU Interface\n" ); -+ mvOsOutput( "-------------\n" ); -+ -+ for( target = 0; target < MAX_TARGETS; target++ ) -+ { -+ -+ memset( &win, 0, sizeof(MV_CPU_DEC_WIN) ); -+ -+ mvOsOutput( "%s ",mvCtrlTargetNameGet(target)); -+ mvOsOutput( "...." ); -+ -+ if( mvCpuIfTargetWinGet( target, &win ) == MV_OK ) -+ { -+ if( win.enable ) -+ { -+ mvOsOutput( "base %08x, ", win.addrWin.baseLow ); -+ mvSizePrint( win.addrWin.size ); -+ mvOsOutput( "\n" ); -+ -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ } -+ else if( mvCpuIfTargetWinGet( target, &win ) == MV_NO_SUCH ) -+ { -+ mvOsOutput( "no such\n" ); -+ } -+ } -+} -+ -+/******************************************************************************* -+* mvCpuIfEnablePex - Enable PCI Express. -+* -+* DESCRIPTION: -+* This function Enable PCI Express. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* pexType - MV_PEX_ROOT_COMPLEX - root complex device -+* MV_PEX_END_POINT - end point device -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+#if defined(MV_INCLUDE_PEX) -+MV_VOID mvCpuIfEnablePex(MV_U32 pexIf, MV_PEX_TYPE pexType) -+{ -+ /* Set pex mode incase S@R not exist */ -+ if( pexType == MV_PEX_END_POINT) -+ { -+ MV_REG_BIT_RESET(PEX_CTRL_REG(pexIf),PXCR_DEV_TYPE_CTRL_MASK); -+ /* Change pex mode in capability reg */ -+ MV_REG_BIT_RESET(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_CAPABILITY_REG), BIT22); -+ MV_REG_BIT_SET(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_CAPABILITY_REG), BIT20); -+ -+ } -+ else -+ { -+ MV_REG_BIT_SET(PEX_CTRL_REG(pexIf),PXCR_DEV_TYPE_CTRL_MASK); -+ } -+ -+ /* CPU config register Pex enable */ -+ MV_REG_BIT_SET(CPU_CTRL_STAT_REG,CCSR_PCI_ACCESS_MASK); -+} -+#endif -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,120 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvCpuIfh -+#define __INCmvCpuIfh -+ -+/* includes */ -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/sys/mvCpuIfRegs.h" -+#include "ctrlEnv/sys/mvAhbToMbus.h" -+#include "ddr2/mvDramIf.h" -+#include "ctrlEnv/sys/mvSysDram.h" -+#if defined(MV_INCLUDE_PEX) -+#include "pex/mvPex.h" -+#endif -+ -+/* defines */ -+ -+/* typedefs */ -+/* This structure describes CPU interface address decode window */ -+typedef struct _mvCpuIfDecWin -+{ -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_U32 winNum; /* Window Number in the AHB To Mbus bridge */ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+}MV_CPU_DEC_WIN; -+ -+ -+ -+/* mvCpuIfLib.h API list */ -+ -+/* mvCpuIfLib.h API list */ -+ -+MV_STATUS mvCpuIfInit(MV_CPU_DEC_WIN *cpuAddrWinMap); -+MV_STATUS mvCpuIfTargetWinSet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin); -+MV_STATUS mvCpuIfTargetWinGet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin); -+MV_STATUS mvCpuIfTargetWinEnable(MV_TARGET target,MV_BOOL enable); -+MV_U32 mvCpuIfTargetWinSizeGet(MV_TARGET target); -+MV_U32 mvCpuIfTargetWinBaseLowGet(MV_TARGET target); -+MV_U32 mvCpuIfTargetWinBaseHighGet(MV_TARGET target); -+MV_TARGET mvCpuIfTargetOfBaseAddressGet(MV_U32 baseAddress); -+#if defined(MV_INCLUDE_PEX) -+MV_U32 mvCpuIfPexRemap(MV_TARGET pexTarget, MV_ADDR_WIN *pAddrDecWin); -+MV_VOID mvCpuIfEnablePex(MV_U32 pexIf, MV_PEX_TYPE pexType); -+#endif -+#if defined(MV_INCLUDE_PCI) -+MV_U32 mvCpuIfPciRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin); -+#endif -+MV_U32 mvCpuIfPciIfRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin); -+ -+MV_VOID mvCpuIfAddDecShow(MV_VOID); -+ -+#if defined(MV88F6281) -+MV_STATUS mvCpuIfBridgeReorderWAInit(void); -+#endif -+ -+#endif /* __INCmvCpuIfh */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfInit.S linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfInit.S ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfInit.S 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfInit.S 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,163 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#define MV_ASMLANGUAGE -+#include "mvOsAsm.h" -+#include "mvDeviceId.h" -+#include "mvCtrlEnvRegs.h" -+#include "mvCpuIfRegs.h" -+#include "mvCtrlEnvAsm.h" -+ -+ -+/******************************************************************************* -+* mvCpuIfPreInit - Make early initialization of CPU interface. -+* -+* DESCRIPTION: -+* The function will initialize the CPU interface parameters that must -+* be initialize before any BUS activity towards the DDR interface, -+* which means it must be executed from ROM. Because of that, the function -+* is implemented in assembly code. -+* The function configure the following CPU config register parameters: -+* 1) CPU2MbusLTickDrv -+* 2) CPU2MbusLTickSample. -+* NOTE: This function must be called AFTER the internal register -+* base is modified to INTER_REGS_BASE. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+* r11 holds return function address. -+*******************************************************************************/ -+#define MV88F6281_PCKG_OPT 2 -+#define MV88F6192_PCKG_OPT 1 -+#define MV88F6180_PCKG_OPT 0 -+ -+ .globl _mvCpuIfPreInit -+_mvCpuIfPreInit: -+ -+ mov r11, LR /* Save link register */ -+ -+ /* Read device ID */ -+ MV_CTRL_MODEL_GET_ASM(r4, r5); -+ -+ /* goto calcConfigReg if device is 6281 */ -+ ldr r5, =MV88F6281_PCKG_OPT -+ cmp r4, r5 -+ beq calcConfigReg -+ -+ /* goto calcConfigReg if device is 6192/6190 */ -+ ldr r5, =MV88F6192_PCKG_OPT -+ cmp r4, r5 -+ beq calcConfigReg -+ -+ /* Else 6180 */ -+ /* Get the "sample on reset" register */ -+ MV_REG_READ_ASM (r4, r5, MPP_SAMPLE_AT_RESET) -+ ldr r5, =MSAR_CPUCLCK_MASK_6180 -+ and r5, r4, r5 -+ mov r5, r5, lsr #MSAR_CPUCLCK_OFFS_6180 -+ -+ ldr r4, =CPU_2_MBUSL_DDR_CLK_1x3 -+ cmp r5, #CPU_2_DDR_CLK_1x3_1 -+ beq setConfigReg -+ -+ ldr r4, =CPU_2_MBUSL_DDR_CLK_1x4 -+ cmp r5, #CPU_2_DDR_CLK_1x4_1 -+ beq setConfigReg -+ b setConfigReg -+ -+calcConfigReg: -+ /* Get the "sample on reset" register */ -+ MV_REG_READ_ASM (r4, r5, MPP_SAMPLE_AT_RESET) -+ ldr r5, =MSAR_DDRCLCK_RTIO_MASK -+ and r5, r4, r5 -+ mov r5, r5, lsr #MSAR_DDRCLCK_RTIO_OFFS -+ -+ ldr r4, =CPU_2_MBUSL_DDR_CLK_1x3 -+ cmp r5, #CPU_2_DDR_CLK_1x3 -+ beq setConfigReg -+ -+ ldr r4, =CPU_2_MBUSL_DDR_CLK_1x4 -+ cmp r5, #CPU_2_DDR_CLK_1x4 -+ beq setConfigReg -+ -+ /* Else */ -+ ldr r4, =0 -+ -+setConfigReg: -+ /* Read CPU Config register */ -+ MV_REG_READ_ASM (r7, r5, CPU_CONFIG_REG) -+ ldr r5, =~(CCR_CPU_2_MBUSL_TICK_DRV_MASK | CCR_CPU_2_MBUSL_TICK_SMPL_MASK) -+ and r7, r7, r5 /* Clear register fields */ -+ orr r7, r7, r4 /* Set the values according to the findings */ -+ MV_REG_WRITE_ASM (r7, r5, CPU_CONFIG_REG) -+ -+done: -+ mov PC, r11 /* r11 is saved link register */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,304 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvCpuIfRegsh -+#define __INCmvCpuIfRegsh -+ -+/****************************************/ -+/* ARM Control and Status Registers Map */ -+/****************************************/ -+ -+#define CPU_CONFIG_REG 0x20100 -+#define CPU_CTRL_STAT_REG 0x20104 -+#define CPU_RSTOUTN_MASK_REG 0x20108 -+#define CPU_SYS_SOFT_RST_REG 0x2010C -+#define CPU_AHB_MBUS_CAUSE_INT_REG 0x20110 -+#define CPU_AHB_MBUS_MASK_INT_REG 0x20114 -+#define CPU_FTDLL_CONFIG_REG 0x20120 -+#define CPU_L2_CONFIG_REG 0x20128 -+ -+ -+ -+/* ARM Configuration register */ -+/* CPU_CONFIG_REG (CCR) */ -+ -+ -+/* Reset vector location */ -+#define CCR_VEC_INIT_LOC_OFFS 1 -+#define CCR_VEC_INIT_LOC_MASK BIT1 -+/* reset at 0x00000000 */ -+#define CCR_VEC_INIT_LOC_0000 (0 << CCR_VEC_INIT_LOC_OFFS) -+/* reset at 0xFFFF0000 */ -+#define CCR_VEC_INIT_LOC_FF00 (1 << CCR_VEC_INIT_LOC_OFFS) -+ -+ -+#define CCR_AHB_ERROR_PROP_OFFS 2 -+#define CCR_AHB_ERROR_PROP_MASK BIT2 -+/* Erros are not propogated to AHB */ -+#define CCR_AHB_ERROR_PROP_NO_INDICATE (0 << CCR_AHB_ERROR_PROP_OFFS) -+/* Erros are propogated to AHB */ -+#define CCR_AHB_ERROR_PROP_INDICATE (1 << CCR_AHB_ERROR_PROP_OFFS) -+ -+ -+#define CCR_ENDIAN_INIT_OFFS 3 -+#define CCR_ENDIAN_INIT_MASK BIT3 -+#define CCR_ENDIAN_INIT_LITTLE (0 << CCR_ENDIAN_INIT_OFFS) -+#define CCR_ENDIAN_INIT_BIG (1 << CCR_ENDIAN_INIT_OFFS) -+ -+ -+#define CCR_INCR_EN_OFFS 4 -+#define CCR_INCR_EN_MASK BIT4 -+#define CCR_INCR_EN BIT4 -+ -+ -+#define CCR_NCB_BLOCKING_OFFS 5 -+#define CCR_NCB_BLOCKING_MASK (1 << CCR_NCB_BLOCKING_OFFS) -+#define CCR_NCB_BLOCKING_NON (0 << CCR_NCB_BLOCKING_OFFS) -+#define CCR_NCB_BLOCKING_EN (1 << CCR_NCB_BLOCKING_OFFS) -+ -+#define CCR_CPU_2_MBUSL_TICK_DRV_OFFS 8 -+#define CCR_CPU_2_MBUSL_TICK_DRV_MASK (0xF << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) -+#define CCR_CPU_2_MBUSL_TICK_SMPL_OFFS 12 -+#define CCR_CPU_2_MBUSL_TICK_SMPL_MASK (0xF << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS) -+#define CCR_ICACH_PREF_BUF_ENABLE BIT16 -+#define CCR_DCACH_PREF_BUF_ENABLE BIT17 -+ -+/* Ratio options for CPU to DDR for 6281/6192/6190 */ -+#define CPU_2_DDR_CLK_1x3 4 -+#define CPU_2_DDR_CLK_1x4 6 -+ -+/* Ratio options for CPU to DDR for 6281 only */ -+#define CPU_2_DDR_CLK_2x9 7 -+#define CPU_2_DDR_CLK_1x5 8 -+#define CPU_2_DDR_CLK_1x6 9 -+ -+/* Ratio options for CPU to DDR for 6180 only */ -+#define CPU_2_DDR_CLK_1x3_1 0x5 -+#define CPU_2_DDR_CLK_1x4_1 0x6 -+ -+/* Default values for CPU to Mbus-L DDR Interface Tick Driver and */ -+/* CPU to Mbus-L Tick Sample fields in CPU config register */ -+ -+#define TICK_DRV_1x1 0 -+#define TICK_DRV_1x2 0 -+#define TICK_DRV_1x3 1 -+#define TICK_DRV_1x4 2 -+#define TICK_SMPL_1x1 0 -+#define TICK_SMPL_1x2 1 -+#define TICK_SMPL_1x3 0 -+#define TICK_SMPL_1x4 0 -+ -+#define CPU_2_MBUSL_DDR_CLK_1x2 \ -+ ((TICK_DRV_1x2 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \ -+ (TICK_SMPL_1x2 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS)) -+#define CPU_2_MBUSL_DDR_CLK_1x3 \ -+ ((TICK_DRV_1x3 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \ -+ (TICK_SMPL_1x3 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS)) -+#define CPU_2_MBUSL_DDR_CLK_1x4 \ -+ ((TICK_DRV_1x4 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \ -+ (TICK_SMPL_1x4 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS)) -+ -+/* ARM Control and Status register */ -+/* CPU_CTRL_STAT_REG (CCSR) */ -+ -+ -+/* -+This is used to block PCI express\PCI from access Socrates/Feroceon GP -+while ARM boot is still in progress -+*/ -+ -+#define CCSR_PCI_ACCESS_OFFS 0 -+#define CCSR_PCI_ACCESS_MASK BIT0 -+#define CCSR_PCI_ACCESS_ENABLE (0 << CCSR_PCI_ACCESS_OFFS) -+#define CCSR_PCI_ACCESS_DISBALE (1 << CCSR_PCI_ACCESS_OFFS) -+ -+#define CCSR_ARM_RESET BIT1 -+#define CCSR_SELF_INT BIT2 -+#define CCSR_BIG_ENDIAN BIT15 -+ -+ -+/* RSTOUTn Mask Register */ -+/* CPU_RSTOUTN_MASK_REG (CRMR) */ -+ -+#define CRMR_PEX_RST_OUT_OFFS 0 -+#define CRMR_PEX_RST_OUT_MASK BIT0 -+#define CRMR_PEX_RST_OUT_ENABLE (1 << CRMR_PEX_RST_OUT_OFFS) -+#define CRMR_PEX_RST_OUT_DISABLE (0 << CRMR_PEX_RST_OUT_OFFS) -+ -+#define CRMR_WD_RST_OUT_OFFS 1 -+#define CRMR_WD_RST_OUT_MASK BIT1 -+#define CRMR_WD_RST_OUT_ENABLE (1 << CRMR_WD_RST_OUT_OFFS) -+#define CRMR_WD_RST_OUT_DISBALE (0 << CRMR_WD_RST_OUT_OFFS) -+ -+#define CRMR_SOFT_RST_OUT_OFFS 2 -+#define CRMR_SOFT_RST_OUT_MASK BIT2 -+#define CRMR_SOFT_RST_OUT_ENABLE (1 << CRMR_SOFT_RST_OUT_OFFS) -+#define CRMR_SOFT_RST_OUT_DISBALE (0 << CRMR_SOFT_RST_OUT_OFFS) -+ -+/* System Software Reset Register */ -+/* CPU_SYS_SOFT_RST_REG (CSSRR) */ -+ -+#define CSSRR_SYSTEM_SOFT_RST BIT0 -+ -+/* AHB to Mbus Bridge Interrupt Cause Register*/ -+/* CPU_AHB_MBUS_CAUSE_INT_REG (CAMCIR) */ -+ -+#define CAMCIR_ARM_SELF_INT BIT0 -+#define CAMCIR_ARM_TIMER0_INT_REQ BIT1 -+#define CAMCIR_ARM_TIMER1_INT_REQ BIT2 -+#define CAMCIR_ARM_WD_TIMER_INT_REQ BIT3 -+ -+ -+/* AHB to Mbus Bridge Interrupt Mask Register*/ -+/* CPU_AHB_MBUS_MASK_INT_REG (CAMMIR) */ -+ -+#define CAMCIR_ARM_SELF_INT_OFFS 0 -+#define CAMCIR_ARM_SELF_INT_MASK BIT0 -+#define CAMCIR_ARM_SELF_INT_EN (1 << CAMCIR_ARM_SELF_INT_OFFS) -+#define CAMCIR_ARM_SELF_INT_DIS (0 << CAMCIR_ARM_SELF_INT_OFFS) -+ -+ -+#define CAMCIR_ARM_TIMER0_INT_REQ_OFFS 1 -+#define CAMCIR_ARM_TIMER0_INT_REQ_MASK BIT1 -+#define CAMCIR_ARM_TIMER0_INT_REQ_EN (1 << CAMCIR_ARM_TIMER0_INT_REQ_OFFS) -+#define CAMCIR_ARM_TIMER0_INT_REQ_DIS (0 << CAMCIR_ARM_TIMER0_INT_REQ_OFFS) -+ -+#define CAMCIR_ARM_TIMER1_INT_REQ_OFFS 2 -+#define CAMCIR_ARM_TIMER1_INT_REQ_MASK BIT2 -+#define CAMCIR_ARM_TIMER1_INT_REQ_EN (1 << CAMCIR_ARM_TIMER1_INT_REQ_OFFS) -+#define CAMCIR_ARM_TIMER1_INT_REQ_DIS (0 << CAMCIR_ARM_TIMER1_INT_REQ_OFFS) -+ -+#define CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS 3 -+#define CAMCIR_ARM_WD_TIMER_INT_REQ_MASK BIT3 -+#define CAMCIR_ARM_WD_TIMER_INT_REQ_EN (1 << CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS) -+#define CAMCIR_ARM_WD_TIMER_INT_REQ_DIS (0 << CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS) -+ -+/* CPU FTDLL Config register (CFCR) fields */ -+#define CFCR_FTDLL_ICACHE_TAG_OFFS 0 -+#define CFCR_FTDLL_ICACHE_TAG_MASK (0x7F << CFCR_FTDLL_ICACHE_TAG_OFFS) -+#define CFCR_FTDLL_DCACHE_TAG_OFFS 8 -+#define CFCR_FTDLL_DCACHE_TAG_MASK (0x7F << CFCR_FTDLL_DCACHE_TAG_OFFS) -+#define CFCR_FTDLL_OVERWRITE_ENABLE (1 << 15) -+/* For Orion 2 D2 only */ -+#define CFCR_MRVL_CPU_ID_OFFS 16 -+#define CFCR_MRVL_CPU_ID_MASK (0x1 << CFCR_MRVL_CPU_ID_OFFS) -+#define CFCR_ARM_CPU_ID (0x0 << CFCR_MRVL_CPU_ID_OFFS) -+#define CFCR_MRVL_CPU_ID (0x1 << CFCR_MRVL_CPU_ID_OFFS) -+#define CFCR_VFP_SUB_ARC_NUM_OFFS 7 -+#define CFCR_VFP_SUB_ARC_NUM_MASK (0x1 << CFCR_VFP_SUB_ARC_NUM_OFFS) -+#define CFCR_VFP_SUB_ARC_NUM_1 (0x0 << CFCR_VFP_SUB_ARC_NUM_OFFS) -+#define CFCR_VFP_SUB_ARC_NUM_2 (0x1 << CFCR_VFP_SUB_ARC_NUM_OFFS) -+ -+/* CPU_L2_CONFIG_REG fields */ -+#ifdef MV_CPU_LE -+#define CL2CR_L2_ECC_EN_OFFS 2 -+#define CL2CR_L2_WT_MODE_OFFS 4 -+#else -+#define CL2CR_L2_ECC_EN_OFFS 26 -+#define CL2CR_L2_WT_MODE_OFFS 28 -+#endif -+ -+#define CL2CR_L2_ECC_EN_MASK (1 << CL2CR_L2_ECC_EN_OFFS) -+#define CL2CR_L2_WT_MODE_MASK (1 << CL2CR_L2_WT_MODE_OFFS) -+ -+/*******************************************/ -+/* Main Interrupt Controller Registers Map */ -+/*******************************************/ -+ -+#define CPU_MAIN_INT_CAUSE_REG 0x20200 -+#define CPU_MAIN_IRQ_MASK_REG 0x20204 -+#define CPU_MAIN_FIQ_MASK_REG 0x20208 -+#define CPU_ENPOINT_MASK_REG 0x2020C -+#define CPU_MAIN_INT_CAUSE_HIGH_REG 0x20210 -+#define CPU_MAIN_IRQ_MASK_HIGH_REG 0x20214 -+#define CPU_MAIN_FIQ_MASK_HIGH_REG 0x20218 -+#define CPU_ENPOINT_MASK_HIGH_REG 0x2021C -+ -+ -+/*******************************************/ -+/* ARM Doorbell Registers Map */ -+/*******************************************/ -+ -+#define CPU_HOST_TO_ARM_DRBL_REG 0x20400 -+#define CPU_HOST_TO_ARM_MASK_REG 0x20404 -+#define CPU_ARM_TO_HOST_DRBL_REG 0x20408 -+#define CPU_ARM_TO_HOST_MASK_REG 0x2040C -+ -+ -+ -+/* CPU control register map */ -+/* Set bits means value is about to change according to new value */ -+#define CPU_CONFIG_DEFAULT_MASK (CCR_VEC_INIT_LOC_MASK | CCR_AHB_ERROR_PROP_MASK) -+ -+#define CPU_CONFIG_DEFAULT (CCR_VEC_INIT_LOC_FF00) -+ -+/* CPU Control and status defaults */ -+#define CPU_CTRL_STAT_DEFAULT_MASK (CCSR_PCI_ACCESS_MASK) -+ -+ -+#define CPU_CTRL_STAT_DEFAULT (CCSR_PCI_ACCESS_ENABLE) -+ -+#endif /* __INCmvCpuIfRegsh */ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,324 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#include "mvSysAudio.h" -+ -+/******************************************************************************* -+* mvAudioWinSet - Set AUDIO target address window -+* -+* DESCRIPTION: -+* This function sets a peripheral target (e.g. SDRAM bank0, PCI_MEM0) -+* address window, also known as address decode window. -+* After setting this target window, the AUDIO will be able to access the -+* target within the address window. -+* -+* INPUT: -+* winNum - AUDIO target address decode window number. -+* pAddrDecWin - AUDIO target window data structure. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR if address window overlapps with other address decode windows. -+* MV_BAD_PARAM if base address is invalid parameter or target is -+* unknown. -+* -+*******************************************************************************/ -+MV_STATUS mvAudioWinSet(MV_U32 winNum, MV_AUDIO_DEC_WIN *pAddrDecWin) -+{ -+ MV_TARGET_ATTRIB targetAttribs; -+ MV_DEC_REGS decRegs; -+ -+ /* Parameter checking */ -+ if (winNum >= MV_AUDIO_MAX_ADDR_DECODE_WIN) -+ { -+ mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvAudioWinSet:Error setting AUDIO window %d to "\ -+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, -+ mvCtrlTargetNameGet(pAddrDecWin->target), -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ decRegs.baseReg = 0; -+ decRegs.sizeReg = 0; -+ -+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) -+ { -+ mvOsPrintf("%s: mvCtrlAddrDecToReg Failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); -+ -+ /* set attributes */ -+ decRegs.sizeReg &= ~MV_AUDIO_WIN_ATTR_MASK; -+ decRegs.sizeReg |= (targetAttribs.attrib << MV_AUDIO_WIN_ATTR_OFFSET); -+ -+ /* set target ID */ -+ decRegs.sizeReg &= ~MV_AUDIO_WIN_TARGET_MASK; -+ decRegs.sizeReg |= (targetAttribs.targetId << MV_AUDIO_WIN_TARGET_OFFSET); -+ -+ if (pAddrDecWin->enable == MV_TRUE) -+ { -+ decRegs.sizeReg |= MV_AUDIO_WIN_ENABLE_MASK; -+ } -+ else -+ { -+ decRegs.sizeReg &= ~MV_AUDIO_WIN_ENABLE_MASK; -+ } -+ -+ MV_REG_WRITE( MV_AUDIO_WIN_CTRL_REG(winNum), decRegs.sizeReg); -+ MV_REG_WRITE( MV_AUDIO_WIN_BASE_REG(winNum), decRegs.baseReg); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvAudioWinGet - Get AUDIO peripheral target address window. -+* -+* DESCRIPTION: -+* Get AUDIO peripheral target address window. -+* -+* INPUT: -+* winNum - AUDIO target address decode window number. -+* -+* OUTPUT: -+* pAddrDecWin - AUDIO target window data structure. -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvAudioWinGet(MV_U32 winNum, MV_AUDIO_DEC_WIN *pAddrDecWin) -+{ -+ MV_DEC_REGS decRegs; -+ MV_TARGET_ATTRIB targetAttrib; -+ -+ /* Parameter checking */ -+ if (winNum >= MV_AUDIO_MAX_ADDR_DECODE_WIN) -+ { -+ mvOsPrintf("%s : ERR. Invalid winNum %d\n", -+ __FUNCTION__, winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ decRegs.baseReg = MV_REG_READ( MV_AUDIO_WIN_BASE_REG(winNum) ); -+ decRegs.sizeReg = MV_REG_READ( MV_AUDIO_WIN_CTRL_REG(winNum) ); -+ -+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs, &pAddrDecWin->addrWin) ) -+ { -+ mvOsPrintf("%s: mvCtrlRegToAddrDec Failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ /* attrib and targetId */ -+ targetAttrib.attrib = (decRegs.sizeReg & MV_AUDIO_WIN_ATTR_MASK) >> -+ MV_AUDIO_WIN_ATTR_OFFSET; -+ targetAttrib.targetId = (decRegs.sizeReg & MV_AUDIO_WIN_TARGET_MASK) >> -+ MV_AUDIO_WIN_TARGET_OFFSET; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ /* Check if window is enabled */ -+ if(decRegs.sizeReg & MV_AUDIO_WIN_ENABLE_MASK) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ } -+ return MV_OK; -+} -+/******************************************************************************* -+* mvAudioAddrDecShow - Print the AUDIO address decode map. -+* -+* DESCRIPTION: -+* This function print the AUDIO address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvAudioAddrDecShow(MV_VOID) -+{ -+ -+ MV_AUDIO_DEC_WIN win; -+ int i; -+ -+ if (MV_FALSE == mvCtrlPwrClckGet(AUDIO_UNIT_ID, 0)) -+ return; -+ -+ -+ mvOsOutput( "\n" ); -+ mvOsOutput( "AUDIO:\n" ); -+ mvOsOutput( "----\n" ); -+ -+ for( i = 0; i < MV_AUDIO_MAX_ADDR_DECODE_WIN; i++ ) -+ { -+ memset( &win, 0, sizeof(MV_AUDIO_DEC_WIN) ); -+ -+ mvOsOutput( "win%d - ", i ); -+ -+ if( mvAudioWinGet( i, &win ) == MV_OK ) -+ { -+ if( win.enable ) -+ { -+ mvOsOutput( "%s base %08x, ", -+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); -+ mvOsOutput( "...." ); -+ -+ mvSizePrint( win.addrWin.size ); -+ -+ mvOsOutput( "\n" ); -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ } -+ } -+} -+ -+ -+/******************************************************************************* -+* mvAudioWinInit - Initialize the integrated AUDIO target address window. -+* -+* DESCRIPTION: -+* Initialize the AUDIO peripheral target address window. -+* -+* INPUT: -+* -+* -+* OUTPUT: -+* -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvAudioInit(MV_VOID) -+{ -+ int winNum; -+ MV_AUDIO_DEC_WIN audioWin; -+ MV_CPU_DEC_WIN cpuAddrDecWin; -+ MV_U32 status; -+ -+ mvAudioHalInit(); -+ -+ /* Initiate Audio address decode */ -+ -+ /* First disable all address decode windows */ -+ for(winNum = 0; winNum < MV_AUDIO_MAX_ADDR_DECODE_WIN; winNum++) -+ { -+ MV_U32 regVal = MV_REG_READ(MV_AUDIO_WIN_CTRL_REG(winNum)); -+ regVal &= ~MV_AUDIO_WIN_ENABLE_MASK; -+ MV_REG_WRITE(MV_AUDIO_WIN_CTRL_REG(winNum), regVal); -+ } -+ -+ for(winNum = 0; winNum < MV_AUDIO_MAX_ADDR_DECODE_WIN; winNum++) -+ { -+ -+ /* We will set the Window to DRAM_CS0 in default */ -+ /* first get attributes from CPU If */ -+ status = mvCpuIfTargetWinGet(SDRAM_CS0, -+ &cpuAddrDecWin); -+ -+ if (MV_OK != status) -+ { -+ mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ if (cpuAddrDecWin.enable == MV_TRUE) -+ { -+ audioWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; -+ audioWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; -+ audioWin.addrWin.size = cpuAddrDecWin.addrWin.size; -+ audioWin.enable = MV_TRUE; -+ audioWin.target = SDRAM_CS0; -+ -+ if(MV_OK != mvAudioWinSet(winNum, &audioWin)) -+ { -+ return MV_ERROR; -+ } -+ } -+ } -+ -+ return MV_OK; -+} -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,123 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#ifndef __INCMVSysAudioH -+#define __INCMVSysAudioH -+ -+#include "mvCommon.h" -+#include "audio/mvAudio.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+ -+/***********************************/ -+/* Audio Address Decoding registers*/ -+/***********************************/ -+ -+#define MV_AUDIO_MAX_ADDR_DECODE_WIN 2 -+#define MV_AUDIO_RECORD_WIN_NUM 0 -+#define MV_AUDIO_PLAYBACK_WIN_NUM 1 -+ -+#define MV_AUDIO_WIN_CTRL_REG(win) (AUDIO_REG_BASE + 0xA04 + ((win)<<3)) -+#define MV_AUDIO_WIN_BASE_REG(win) (AUDIO_REG_BASE + 0xA00 + ((win)<<3)) -+ -+#define MV_AUDIO_RECORD_WIN_CTRL_REG MV_AUDIO_WIN_CTRL_REG(MV_AUDIO_RECORD_WIN_NUM) -+#define MV_AUDIO_RECORD_WIN_BASE_REG MV_AUDIO_WIN_BASE_REG(MV_AUDIO_RECORD_WIN_NUM) -+#define MV_AUDIO_PLAYBACK_WIN_CTRL_REG MV_AUDIO_WIN_CTRL_REG(MV_AUDIO_PLAYBACK_WIN_NUM) -+#define MV_AUDIO_PLAYBACK_WIN_BASE_REG MV_AUDIO_WIN_BASE_REG(MV_AUDIO_PLAYBACK_WIN_NUM) -+ -+ -+/* BITs in Windows 0-3 Control and Base Registers */ -+#define MV_AUDIO_WIN_ENABLE_BIT 0 -+#define MV_AUDIO_WIN_ENABLE_MASK (1<= 2) -+MV_TARGET tdmaAddrDecPrioTable[] = -+{ -+#if defined(MV_INCLUDE_SDRAM_CS0) -+ SDRAM_CS0, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS1) -+ SDRAM_CS1, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS2) -+ SDRAM_CS2, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS3) -+ SDRAM_CS3, -+#endif -+#if defined(MV_INCLUDE_PEX) -+ PEX0_MEM, -+#endif -+ -+ TBL_TERM -+}; -+ -+/******************************************************************************* -+* mvCesaWinGet - Get TDMA target address window. -+* -+* DESCRIPTION: -+* Get TDMA target address window. -+* -+* INPUT: -+* winNum - TDMA target address decode window number. -+* -+* OUTPUT: -+* pDecWin - TDMA target window data structure. -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+static MV_STATUS mvCesaWinGet(MV_U32 winNum, MV_DEC_WIN *pDecWin) -+{ -+ MV_DEC_WIN_PARAMS winParam; -+ MV_U32 sizeReg, baseReg; -+ -+ /* Parameter checking */ -+ if (winNum >= MV_CESA_TDMA_ADDR_DEC_WIN) -+ { -+ mvOsPrintf("%s : ERR. Invalid winNum %d\n", -+ __FUNCTION__, winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ baseReg = MV_REG_READ( MV_CESA_TDMA_BASE_ADDR_REG(winNum) ); -+ sizeReg = MV_REG_READ( MV_CESA_TDMA_WIN_CTRL_REG(winNum) ); -+ -+ /* Check if window is enabled */ -+ if(sizeReg & MV_CESA_TDMA_WIN_ENABLE_MASK) -+ { -+ pDecWin->enable = MV_TRUE; -+ -+ /* Extract window parameters from registers */ -+ winParam.targetId = (sizeReg & MV_CESA_TDMA_WIN_TARGET_MASK) >> MV_CESA_TDMA_WIN_TARGET_OFFSET; -+ winParam.attrib = (sizeReg & MV_CESA_TDMA_WIN_ATTR_MASK) >> MV_CESA_TDMA_WIN_ATTR_OFFSET; -+ winParam.size = (sizeReg & MV_CESA_TDMA_WIN_SIZE_MASK) >> MV_CESA_TDMA_WIN_SIZE_OFFSET; -+ winParam.baseAddr = (baseReg & MV_CESA_TDMA_WIN_BASE_MASK); -+ -+ /* Translate the decode window parameters to address decode struct */ -+ if (MV_OK != mvCtrlParamsToAddrDec(&winParam, pDecWin)) -+ { -+ mvOsPrintf("Failed to translate register parameters to CESA address" \ -+ " decode window structure\n"); -+ return MV_ERROR; -+ } -+ } -+ else -+ { -+ pDecWin->enable = MV_FALSE; -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* cesaWinOverlapDetect - Detect CESA TDMA address windows overlapping -+* -+* DESCRIPTION: -+* An unpredicted behaviur is expected in case TDMA address decode -+* windows overlapps. -+* This function detects TDMA address decode windows overlapping of a -+* specified window. The function does not check the window itself for -+* overlapping. The function also skipps disabled address decode windows. -+* -+* INPUT: -+* winNum - address decode window number. -+* pAddrDecWin - An address decode window struct. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE - if the given address window overlap current address -+* decode map, -+* MV_FALSE - otherwise, MV_ERROR if reading invalid data -+* from registers. -+* -+*******************************************************************************/ -+static MV_STATUS cesaWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 winNumIndex; -+ MV_DEC_WIN addrDecWin; -+ -+ for(winNumIndex=0; winNumIndex= MV_CESA_TDMA_ADDR_DEC_WIN) -+ { -+ mvOsPrintf("mvCesaTdmaWinSet: ERR. Invalid win num %d\n",winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlapps with current windows */ -+ if (MV_TRUE == cesaWinOverlapDetect(winNum, &pDecWin->addrWin)) -+ { -+ mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); -+ return MV_ERROR; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pDecWin->addrWin.baseLow, pDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvCesaTdmaWinSet: Error setting CESA TDMA window %d to "\ -+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, -+ mvCtrlTargetNameGet(pDecWin->target), -+ pDecWin->addrWin.baseLow, -+ pDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ if(MV_OK != mvCtrlAddrDecToParams(pDecWin, &winParams)) -+ { -+ mvOsPrintf("%s: mvCtrlAddrDecToParams Failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ /* set Size, Attributes and TargetID */ -+ sizeReg = (((winParams.targetId << MV_CESA_TDMA_WIN_TARGET_OFFSET) & MV_CESA_TDMA_WIN_TARGET_MASK) | -+ ((winParams.attrib << MV_CESA_TDMA_WIN_ATTR_OFFSET) & MV_CESA_TDMA_WIN_ATTR_MASK) | -+ ((winParams.size << MV_CESA_TDMA_WIN_SIZE_OFFSET) & MV_CESA_TDMA_WIN_SIZE_MASK)); -+ -+ if (pDecWin->enable == MV_TRUE) -+ { -+ sizeReg |= MV_CESA_TDMA_WIN_ENABLE_MASK; -+ } -+ else -+ { -+ sizeReg &= ~MV_CESA_TDMA_WIN_ENABLE_MASK; -+ } -+ -+ /* Update Base value */ -+ baseReg = (winParams.baseAddr & MV_CESA_TDMA_WIN_BASE_MASK); -+ -+ MV_REG_WRITE( MV_CESA_TDMA_WIN_CTRL_REG(winNum), sizeReg); -+ MV_REG_WRITE( MV_CESA_TDMA_BASE_ADDR_REG(winNum), baseReg); -+ -+ return MV_OK; -+} -+ -+ -+static MV_STATUS mvCesaTdmaAddrDecInit (void) -+{ -+ MV_U32 winNum; -+ MV_STATUS status; -+ MV_CPU_DEC_WIN cpuAddrDecWin; -+ MV_DEC_WIN cesaWin; -+ MV_U32 winPrioIndex = 0; -+ -+ /* First disable all address decode windows */ -+ for(winNum=0; winNum= 2 */ -+ -+ -+ -+ -+MV_STATUS mvCesaInit (int numOfSession, int queueDepth, char* pSramBase, void *osHandle) -+{ -+ MV_U32 cesaCryptEngBase; -+ MV_CPU_DEC_WIN addrDecWin; -+ -+ if(sizeof(MV_CESA_SRAM_MAP) > MV_CESA_SRAM_SIZE) -+ { -+ mvOsPrintf("mvCesaInit: Wrong SRAM map - %ld > %d\n", -+ sizeof(MV_CESA_SRAM_MAP), MV_CESA_SRAM_SIZE); -+ return MV_FAIL; -+ } -+#if 0 -+ if (mvCpuIfTargetWinGet(CRYPT_ENG, &addrDecWin) == MV_OK) -+ cesaCryptEngBase = addrDecWin.addrWin.baseLow; -+ else -+ { -+ mvOsPrintf("mvCesaInit: ERR. mvCpuIfTargetWinGet failed\n"); -+ return MV_ERROR; -+ } -+#else -+ cesaCryptEngBase = (MV_U32)pSramBase; -+#endif -+ -+#if 0 /* Already done in the platform init */ -+#if (MV_CESA_VERSION >= 2) -+ mvCesaTdmaAddrDecInit(); -+#endif /* MV_CESA_VERSION >= 2 */ -+#endif -+ return mvCesaHalInit(numOfSession, queueDepth, pSramBase, cesaCryptEngBase, -+ osHandle); -+ -+} -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,100 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __mvSysCesa_h__ -+#define __mvSysCesa_h__ -+ -+ -+#include "mvCommon.h" -+#include "cesa/mvCesa.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+ -+/***************************** TDMA Registers *************************************/ -+ -+#define MV_CESA_TDMA_ADDR_DEC_WIN 4 -+ -+#define MV_CESA_TDMA_BASE_ADDR_REG(win) (MV_CESA_TDMA_REG_BASE + 0xa00 + (win<<3)) -+ -+#define MV_CESA_TDMA_WIN_CTRL_REG(win) (MV_CESA_TDMA_REG_BASE + 0xa04 + (win<<3)) -+ -+#define MV_CESA_TDMA_WIN_ENABLE_BIT 0 -+#define MV_CESA_TDMA_WIN_ENABLE_MASK (1 << MV_CESA_TDMA_WIN_ENABLE_BIT) -+ -+#define MV_CESA_TDMA_WIN_TARGET_OFFSET 4 -+#define MV_CESA_TDMA_WIN_TARGET_MASK (0xf << MV_CESA_TDMA_WIN_TARGET_OFFSET) -+ -+#define MV_CESA_TDMA_WIN_ATTR_OFFSET 8 -+#define MV_CESA_TDMA_WIN_ATTR_MASK (0xff << MV_CESA_TDMA_WIN_ATTR_OFFSET) -+ -+#define MV_CESA_TDMA_WIN_SIZE_OFFSET 16 -+#define MV_CESA_TDMA_WIN_SIZE_MASK (0xFFFF << MV_CESA_TDMA_WIN_SIZE_OFFSET) -+ -+#define MV_CESA_TDMA_WIN_BASE_OFFSET 16 -+#define MV_CESA_TDMA_WIN_BASE_MASK (0xFFFF << MV_CESA_TDMA_WIN_BASE_OFFSET) -+ -+ -+MV_STATUS mvCesaInit (int numOfSession, int queueDepth, char* pSramBase, void *osHandle); -+ -+#endif -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,348 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+/* includes */ -+ -+#include "ddr2/mvDramIf.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+#include "ctrlEnv/sys/mvSysDram.h" -+ -+/* #define MV_DEBUG */ -+#ifdef MV_DEBUG -+#define DB(x) x -+#else -+#define DB(x) -+#endif -+ -+static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin); -+ -+/******************************************************************************* -+* mvDramIfWinSet - Set DRAM interface address decode window -+* -+* DESCRIPTION: -+* This function sets DRAM interface address decode window. -+* -+* INPUT: -+* target - System target. Use only SDRAM targets. -+* pAddrDecWin - SDRAM address window structure. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK -+* otherwise. -+*******************************************************************************/ -+MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) -+{ -+ MV_U32 baseReg=0,sizeReg=0; -+ MV_U32 baseToReg=0 , sizeToReg=0; -+ -+ /* Check parameters */ -+ if (!MV_TARGET_IS_DRAM(target)) -+ { -+ mvOsPrintf("mvDramIfWinSet: target %d is not SDRAM\n", target); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlaps with current enabled windows */ -+ if (MV_TRUE == sdramIfWinOverlap(target, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("mvDramIfWinSet: ERR. Target %d overlaps\n", target); -+ return MV_BAD_PARAM; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvDramIfWinSet:Error setting DRAM interface window %d."\ -+ "\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ target, -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ /* read base register*/ -+ baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(0,target)); -+ -+ /* read size register */ -+ sizeReg = MV_REG_READ(SDRAM_SIZE_REG(0,target)); -+ -+ /* BaseLow[31:16] => base register [31:16] */ -+ baseToReg = pAddrDecWin->addrWin.baseLow & SCBAR_BASE_MASK; -+ -+ /* Write to address decode Base Address Register */ -+ baseReg &= ~SCBAR_BASE_MASK; -+ baseReg |= baseToReg; -+ -+ /* Translate the given window size to register format */ -+ sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, SCSR_SIZE_ALIGNMENT); -+ -+ /* Size parameter validity check. */ -+ if (-1 == sizeToReg) -+ { -+ mvOsPrintf("mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n",target); -+ return MV_BAD_PARAM; -+ } -+ -+ /* set size */ -+ sizeReg &= ~SCSR_SIZE_MASK; -+ /* Size is located at upper 16 bits */ -+ sizeReg |= (sizeToReg << SCSR_SIZE_OFFS); -+ -+ /* enable/Disable */ -+ if (MV_TRUE == pAddrDecWin->enable) -+ { -+ sizeReg |= SCSR_WIN_EN; -+ } -+ else -+ { -+ sizeReg &= ~SCSR_WIN_EN; -+ } -+ -+ /* 3) Write to address decode Base Address Register */ -+ MV_REG_WRITE(SDRAM_BASE_ADDR_REG(0,target), baseReg); -+ -+ /* Write to address decode Size Register */ -+ MV_REG_WRITE(SDRAM_SIZE_REG(0,target), sizeReg); -+ -+ return MV_OK; -+} -+/******************************************************************************* -+* mvDramIfWinGet - Get DRAM interface address decode window -+* -+* DESCRIPTION: -+* This function gets DRAM interface address decode window. -+* -+* INPUT: -+* target - System target. Use only SDRAM targets. -+* -+* OUTPUT: -+* pAddrDecWin - SDRAM address window structure. -+* -+* RETURN: -+* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK -+* otherwise. -+*******************************************************************************/ -+MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) -+{ -+ MV_U32 baseReg,sizeReg; -+ MV_U32 sizeRegVal; -+ /* Check parameters */ -+ if (!MV_TARGET_IS_DRAM(target)) -+ { -+ mvOsPrintf("mvDramIfWinGet: target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ /* Read base and size registers */ -+ sizeReg = MV_REG_READ(SDRAM_SIZE_REG(0,target)); -+ baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(0,target)); -+ -+ sizeRegVal = (sizeReg & SCSR_SIZE_MASK) >> SCSR_SIZE_OFFS; -+ -+ pAddrDecWin->addrWin.size = ctrlRegToSize(sizeRegVal, -+ SCSR_SIZE_ALIGNMENT); -+ -+ /* Check if ctrlRegToSize returned OK */ -+ if (-1 == pAddrDecWin->addrWin.size) -+ { -+ mvOsPrintf("mvDramIfWinGet: size of target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ /* Extract base address */ -+ /* Base register [31:16] ==> baseLow[31:16] */ -+ pAddrDecWin->addrWin.baseLow = baseReg & SCBAR_BASE_MASK; -+ -+ pAddrDecWin->addrWin.baseHigh = 0; -+ -+ -+ if (sizeReg & SCSR_WIN_EN) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ } -+ -+ return MV_OK; -+} -+/******************************************************************************* -+* mvDramIfWinEnable - Enable/Disable SDRAM address decode window -+* -+* DESCRIPTION: -+* This function enable/Disable SDRAM address decode window. -+* -+* INPUT: -+* target - System target. Use only SDRAM targets. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR in case function parameter are invalid, MV_OK otherewise. -+* -+*******************************************************************************/ -+MV_STATUS mvDramIfWinEnable(MV_TARGET target, MV_BOOL enable) -+{ -+ MV_DRAM_DEC_WIN addrDecWin; -+ -+ /* Check parameters */ -+ if (!MV_TARGET_IS_DRAM(target)) -+ { -+ mvOsPrintf("mvDramIfWinEnable: target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ if (enable == MV_TRUE) -+ { /* First check for overlap with other enabled windows */ -+ if (MV_OK != mvDramIfWinGet(target, &addrDecWin)) -+ { -+ mvOsPrintf("mvDramIfWinEnable:ERR. Getting target %d failed.\n", -+ target); -+ return MV_ERROR; -+ } -+ /* Check for overlapping */ -+ if (MV_FALSE == sdramIfWinOverlap(target, &(addrDecWin.addrWin))) -+ { -+ /* No Overlap. Enable address decode winNum window */ -+ MV_REG_BIT_SET(SDRAM_SIZE_REG(0,target), SCSR_WIN_EN); -+ } -+ else -+ { /* Overlap detected */ -+ mvOsPrintf("mvDramIfWinEnable: ERR. Target %d overlap detect\n", -+ target); -+ return MV_ERROR; -+ } -+ } -+ else -+ { /* Disable address decode winNum window */ -+ MV_REG_BIT_RESET(SDRAM_SIZE_REG(0, target), SCSR_WIN_EN); -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* sdramIfWinOverlap - Check if an address window overlap an SDRAM address window -+* -+* DESCRIPTION: -+* This function scan each SDRAM address decode window to test if it -+* overlapps the given address windoow -+* -+* INPUT: -+* target - SDRAM target where the function skips checking. -+* pAddrDecWin - The tested address window for overlapping with -+* SDRAM windows. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlaps any enabled address -+* decode map, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_TARGET targetNum; -+ MV_DRAM_DEC_WIN addrDecWin; -+ -+ for(targetNum = SDRAM_CS0; targetNum < MV_DRAM_MAX_CS ; targetNum++) -+ { -+ /* don't check our winNum or illegal targets */ -+ if (targetNum == target) -+ { -+ continue; -+ } -+ -+ /* Get window parameters */ -+ if (MV_OK != mvDramIfWinGet(targetNum, &addrDecWin)) -+ { -+ mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); -+ return MV_ERROR; -+ } -+ -+ /* Do not check disabled windows */ -+ if (MV_FALSE == addrDecWin.enable) -+ { -+ continue; -+ } -+ -+ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) -+ { -+ mvOsPrintf( -+ "sdramIfWinOverlap: Required target %d overlap winNum %d\n", -+ target, targetNum); -+ return MV_TRUE; -+ } -+ } -+ -+ return MV_FALSE; -+} -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,80 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __sysDram -+#define __sysDram -+ -+/* This structure describes CPU interface address decode window */ -+typedef struct _mvDramIfDecWin -+{ -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+}MV_DRAM_DEC_WIN; -+ -+MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); -+MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); -+MV_STATUS mvDramIfWinEnable(MV_TARGET target, MV_BOOL enable); -+ -+#endif -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,658 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#include "ctrlEnv/sys/mvSysGbe.h" -+ -+ -+ -+typedef struct _mvEthDecWin -+{ -+ MV_TARGET target; -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+}MV_ETH_DEC_WIN; -+ -+MV_TARGET ethAddrDecPrioTap[] = -+{ -+#if defined(MV_INCLUDE_SDRAM_CS0) -+ SDRAM_CS0, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS1) -+ SDRAM_CS1, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS2) -+ SDRAM_CS2, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS3) -+ SDRAM_CS3, -+#endif -+#if defined(MV_INCLUDE_DEVICE_CS0) -+ DEVICE_CS0, -+#endif -+#if defined(MV_INCLUDE_DEVICE_CS1) -+ DEVICE_CS1, -+#endif -+#if defined(MV_INCLUDE_DEVICE_CS2) -+ DEVICE_CS2, -+#endif -+#if defined(MV_INCLUDE_DEVICE_CS3) -+ DEVICE_CS3, -+#endif -+#if defined(MV_INCLUDE_PEX) -+ PEX0_IO, -+#endif -+ TBL_TERM -+}; -+ -+static MV_STATUS ethWinOverlapDetect(int port, MV_U32 winNum, MV_ADDR_WIN *pAddrWin); -+static MV_STATUS mvEthWinSet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin); -+static MV_STATUS mvEthWinGet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin); -+ -+ -+/******************************************************************************* -+* mvEthWinInit - Initialize ETH address decode windows -+* -+* DESCRIPTION: -+* This function initialize ETH window decode unit. It set the -+* default address decode windows of the unit. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR if setting fail. -+*******************************************************************************/ -+/* Configure EthDrv memory map registes. */ -+MV_STATUS mvEthWinInit (int port) -+{ -+ MV_U32 winNum, status, winPrioIndex=0, i, regVal=0; -+ MV_ETH_DEC_WIN ethWin; -+ MV_CPU_DEC_WIN cpuAddrDecWin; -+ static MV_U32 accessProtReg = 0; -+ -+#if (MV_ETH_VERSION <= 1) -+ static MV_BOOL isFirst = MV_TRUE; -+ -+ if(isFirst == MV_FALSE) -+ { -+ MV_REG_WRITE(ETH_ACCESS_PROTECT_REG(port), accessProtReg); -+ return MV_OK; -+ } -+ isFirst = MV_FALSE; -+#endif /* MV_GIGA_ETH_VERSION */ -+ -+ /* Initiate Ethernet address decode */ -+ -+ /* First disable all address decode windows */ -+ for(winNum=0; winNum= ETH_MAX_DECODE_WIN) -+ { -+ mvOsPrintf("mvEthWinSet: ERR. Invalid win num %d\n",winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlapps with current windows */ -+ if (MV_TRUE == ethWinOverlapDetect(port, winNum, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("mvEthWinSet: ERR. Window %d overlap\n", winNum); -+ return MV_ERROR; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvEthWinSet: Error setting Ethernet window %d to "\ -+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, -+ mvCtrlTargetNameGet(pAddrDecWin->target), -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ -+ decRegs.baseReg = MV_REG_READ(ETH_WIN_BASE_REG(port, winNum)); -+ decRegs.sizeReg = MV_REG_READ(ETH_WIN_SIZE_REG(port, winNum)); -+ -+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) -+ { -+ mvOsPrintf("mvEthWinSet:mvCtrlAddrDecToReg Failed\n"); -+ return MV_ERROR; -+ } -+ -+ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); -+ -+ /* set attributes */ -+ decRegs.baseReg &= ~ETH_WIN_ATTR_MASK; -+ decRegs.baseReg |= targetAttribs.attrib << ETH_WIN_ATTR_OFFS; -+ /* set target ID */ -+ decRegs.baseReg &= ~ETH_WIN_TARGET_MASK; -+ decRegs.baseReg |= targetAttribs.targetId << ETH_WIN_TARGET_OFFS; -+ -+ /* for the safe side we disable the window before writing the new -+ values */ -+ mvEthWinEnable(port, winNum, MV_FALSE); -+ MV_REG_WRITE(ETH_WIN_BASE_REG(port, winNum), decRegs.baseReg); -+ -+ /* Write to address decode Size Register */ -+ MV_REG_WRITE(ETH_WIN_SIZE_REG(port, winNum), decRegs.sizeReg); -+ -+ /* Enable address decode target window */ -+ if (pAddrDecWin->enable == MV_TRUE) -+ { -+ mvEthWinEnable(port, winNum, MV_TRUE); -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvETHWinGet - Get dma peripheral target address window. -+* -+* DESCRIPTION: -+* Get ETH peripheral target address window. -+* -+* INPUT: -+* winNum - ETH to target address decode window number. -+* -+* OUTPUT: -+* pAddrDecWin - ETH target window data structure. -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvEthWinGet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin) -+{ -+ MV_DEC_REGS decRegs; -+ MV_TARGET_ATTRIB targetAttrib; -+ -+ /* Parameter checking */ -+ if (winNum >= ETH_MAX_DECODE_WIN) -+ { -+ mvOsPrintf("mvEthWinGet: ERR. Invalid winNum %d\n", winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ decRegs.baseReg = MV_REG_READ(ETH_WIN_BASE_REG(port, winNum)); -+ decRegs.sizeReg = MV_REG_READ(ETH_WIN_SIZE_REG(port, winNum)); -+ -+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) -+ { -+ mvOsPrintf("mvAhbToMbusWinGet: mvCtrlRegToAddrDec Failed \n"); -+ return MV_ERROR; -+ } -+ -+ /* attrib and targetId */ -+ targetAttrib.attrib = -+ (decRegs.baseReg & ETH_WIN_ATTR_MASK) >> ETH_WIN_ATTR_OFFS; -+ targetAttrib.targetId = -+ (decRegs.baseReg & ETH_WIN_TARGET_MASK) >> ETH_WIN_TARGET_OFFS; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ /* Check if window is enabled */ -+ if (~(MV_REG_READ(ETH_BASE_ADDR_ENABLE_REG(port))) & (1 << winNum) ) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthWinEnable - Enable/disable a ETH to target address window -+* -+* DESCRIPTION: -+* This function enable/disable a ETH to target address window. -+* According to parameter 'enable' the routine will enable the -+* window, thus enabling ETH accesses (before enabling the window it is -+* tested for overlapping). Otherwise, the window will be disabled. -+* -+* INPUT: -+* winNum - ETH to target address decode window number. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_ERROR if decode window number was wrong or enabled window overlapps. -+* -+*******************************************************************************/ -+MV_STATUS mvEthWinEnable(int port, MV_U32 winNum,MV_BOOL enable) -+{ -+ MV_ETH_DEC_WIN addrDecWin; -+ -+ /* Parameter checking */ -+ if (winNum >= ETH_MAX_DECODE_WIN) -+ { -+ mvOsPrintf("mvEthTargetWinEnable:ERR. Invalid winNum%d\n",winNum); -+ return MV_ERROR; -+ } -+ -+ if (enable == MV_TRUE) -+ { /* First check for overlap with other enabled windows */ -+ /* Get current window */ -+ if (MV_OK != mvEthWinGet(port, winNum, &addrDecWin)) -+ { -+ mvOsPrintf("mvEthTargetWinEnable:ERR. targetWinGet fail\n"); -+ return MV_ERROR; -+ } -+ /* Check for overlapping */ -+ if (MV_FALSE == ethWinOverlapDetect(port, winNum, &(addrDecWin.addrWin))) -+ { -+ /* No Overlap. Enable address decode target window */ -+ MV_REG_BIT_RESET(ETH_BASE_ADDR_ENABLE_REG(port), (1 << winNum)); -+ } -+ else -+ { /* Overlap detected */ -+ mvOsPrintf("mvEthTargetWinEnable:ERR. Overlap detected\n"); -+ return MV_ERROR; -+ } -+ } -+ else -+ { /* Disable address decode target window */ -+ MV_REG_BIT_SET(ETH_BASE_ADDR_ENABLE_REG(port), (1 << winNum)); -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthWinTargetGet - Get Window number associated with target -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+* window number -+* -+*******************************************************************************/ -+MV_U32 mvEthWinTargetGet(int port, MV_TARGET target) -+{ -+ MV_ETH_DEC_WIN decWin; -+ MV_U32 winNum; -+ -+ /* Check parameters */ -+ if (target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvAhbToMbusWinTargetGet: target %d is Illigal\n", target); -+ return 0xffffffff; -+ } -+ -+ for (winNum=0; winNum= mvCtrlEthMaxPortGet()) -+ { -+ mvOsPrintf("mvEthProtWinSet:ERR. Invalid port number %d\n", portNo); -+ return MV_ERROR; -+ } -+ -+ if (winNum >= ETH_MAX_DECODE_WIN) -+ { -+ mvOsPrintf("mvEthProtWinSet:ERR. Invalid winNum%d\n",winNum); -+ return MV_ERROR; -+ } -+ -+ if((access == ACC_RESERVED) || (access >= MAX_ACC_RIGHTS)) -+ { -+ mvOsPrintf("mvEthProtWinSet:ERR. Inv access param %d\n", access); -+ return MV_ERROR; -+ } -+ /* Read current protection register */ -+ protReg = MV_REG_READ(ETH_ACCESS_PROTECT_REG(portNo)); -+ -+ /* Clear protection window field */ -+ protReg &= ~(ETH_PROT_WIN_MASK(winNum)); -+ -+ /* Set new protection field value */ -+ protReg |= (access << (ETH_PROT_WIN_OFFS(winNum))); -+ -+ /* Write protection register back */ -+ MV_REG_WRITE(ETH_ACCESS_PROTECT_REG(portNo), protReg); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* ethWinOverlapDetect - Detect ETH address windows overlapping -+* -+* DESCRIPTION: -+* An unpredicted behaviur is expected in case ETH address decode -+* windows overlapps. -+* This function detects ETH address decode windows overlapping of a -+* specified window. The function does not check the window itself for -+* overlapping. The function also skipps disabled address decode windows. -+* -+* INPUT: -+* winNum - address decode window number. -+* pAddrDecWin - An address decode window struct. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data -+* from registers. -+* -+*******************************************************************************/ -+static MV_STATUS ethWinOverlapDetect(int port, MV_U32 winNum, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 baseAddrEnableReg; -+ MV_U32 winNumIndex; -+ MV_ETH_DEC_WIN addrDecWin; -+ -+ /* Read base address enable register. Do not check disabled windows */ -+ baseAddrEnableReg = MV_REG_READ(ETH_BASE_ADDR_ENABLE_REG(port)); -+ -+ for (winNumIndex=0; winNumIndex= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexInit: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Enabled CPU access to PCI-Express */ -+ mvCpuIfEnablePex(pexIf, pexType); -+ -+ /* Start with bars */ -+ /* First disable all PEX bars*/ -+ for (bar = 0; bar < PEX_MAX_BARS; bar++) -+ { -+ if (PEX_INTER_REGS_BAR != bar) -+ { -+ if (MV_OK != mvPexBarEnable(pexIf, bar, MV_FALSE)) -+ { -+ mvOsPrintf("mvPexInit:mvPexBarEnable bar =%d failed \n",bar); -+ return MV_ERROR; -+ } -+ -+ } -+ -+ } -+ -+ /* and disable all PEX target windows */ -+ for (winNum = 0; winNum < PEX_MAX_TARGET_WIN - 2; winNum++) -+ { -+ if (MV_OK != mvPexTargetWinEnable(pexIf, winNum, MV_FALSE)) -+ { -+ mvOsPrintf("mvPexInit:mvPexTargetWinEnable winNum =%d failed \n", -+ winNum); -+ return MV_ERROR; -+ -+ } -+ } -+ -+ /* Now, go through all bars*/ -+ -+ -+ -+/******************************************************************************/ -+/* Internal registers bar */ -+/******************************************************************************/ -+ bar = PEX_INTER_REGS_BAR; -+ -+ /* we only open the bar , no need to open windows for this bar */ -+ -+ /* first get the CS attribute from the CPU Interface */ -+ if (MV_OK !=mvCpuIfTargetWinGet(INTER_REGS,&addrDecWin)) -+ { -+ mvOsPrintf("mvPexInit: ERR. mvCpuIfTargetWinGet failed target =%d\n",INTER_REGS); -+ return MV_ERROR; -+ } -+ -+ pexBar.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; -+ pexBar.addrWin.baseLow = addrDecWin.addrWin.baseLow; -+ pexBar.addrWin.size = addrDecWin.addrWin.size; -+ pexBar.enable = MV_TRUE; -+ -+ if (MV_OK != mvPexBarSet(pexIf, bar, &pexBar)) -+ { -+ mvOsPrintf("mvPexInit: ERR. mvPexBarSet %d failed\n", bar); -+ return MV_ERROR; -+ } -+ -+/******************************************************************************/ -+/* DRAM bar */ -+/******************************************************************************/ -+ -+ bar = PEX_DRAM_BAR; -+ -+ pexBar.addrWin.size = 0; -+ -+ for (target = SDRAM_CS0;target < MV_DRAM_MAX_CS; target++ ) -+ { -+ -+ status = mvCpuIfTargetWinGet(target,&addrDecWin); -+ -+ if((MV_NO_SUCH == status)&&(target != SDRAM_CS0)) -+ { -+ continue; -+ } -+ -+ /* first get attributes from CPU If */ -+ if (MV_OK != status) -+ { -+ mvOsPrintf("mvPexInit: ERR. mvCpuIfTargetWinGet failed target =%d\n",target); -+ return MV_ERROR; -+ } -+ if (addrDecWin.enable == MV_TRUE) -+ { -+ /* the base is the base of DRAM CS0 always */ -+ if (SDRAM_CS0 == target ) -+ { -+ pexBar.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; -+ pexBar.addrWin.baseLow = addrDecWin.addrWin.baseLow; -+ -+ } -+ -+ /* increment the bar size to be the sum of the size of all -+ DRAM chips selecs */ -+ pexBar.addrWin.size += addrDecWin.addrWin.size; -+ -+ /* set a Pex window for this target ! -+ DRAM CS always will have a Pex Window , and is not a -+ part of the priority table */ -+ pexWin.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; -+ pexWin.addrWin.baseLow = addrDecWin.addrWin.baseLow; -+ pexWin.addrWin.size = addrDecWin.addrWin.size; -+ -+ /* we disable the windows at first because we are not -+ sure that it is witihin bar boundries */ -+ pexWin.enable =MV_FALSE; -+ pexWin.target = target; -+ pexWin.targetBar = bar; -+ -+ if (MV_OK != mvPexTargetWinSet(pexIf,pexCurrWin++,&pexWin)) -+ { -+ mvOsPrintf("mvPexInit: ERR. mvPexTargetWinSet failed\n"); -+ return MV_ERROR; -+ } -+ } -+ } -+ -+ /* check if the size of the bar is illeggal */ -+ if (-1 == ctrlSizeToReg(pexBar.addrWin.size, PXBCR_BAR_SIZE_ALIGNMENT)) -+ { -+ /* try to get a good size */ -+ pexBar.addrWin.size = ctrlSizeRegRoundUp(pexBar.addrWin.size, -+ PXBCR_BAR_SIZE_ALIGNMENT); -+ } -+ -+ /* check if the size and base are valid */ -+ if (MV_TRUE == pexBarOverlapDetect(pexIf,bar,&pexBar.addrWin)) -+ { -+ mvOsPrintf("mvPexInit:Warning :Bar %d size is illigal\n",bar); -+ mvOsPrintf("it will be disabled\n"); -+ mvOsPrintf("please check Pex and CPU windows configuration\n"); -+ } -+ else -+ { -+ pexBar.enable = MV_TRUE; -+ -+ /* configure the bar */ -+ if (MV_OK != mvPexBarSet(pexIf, bar, &pexBar)) -+ { -+ mvOsPrintf("mvPexInit: ERR. mvPexBarSet %d failed\n", bar); -+ return MV_ERROR; -+ } -+ -+ /* after the bar was configured then we enable the Pex windows*/ -+ for (winNum = 0;winNum < pexCurrWin ;winNum++) -+ { -+ if (MV_OK != mvPexTargetWinEnable(pexIf, winNum, MV_TRUE)) -+ { -+ mvOsPrintf("mvPexInit: Can't enable window =%d\n",winNum); -+ return MV_ERROR; -+ } -+ -+ } -+ } -+ -+/******************************************************************************/ -+/* DEVICE bar */ -+/******************************************************************************/ -+ -+/* Open the Device BAR for non linux only */ -+#ifndef MV_DISABLE_PEX_DEVICE_BAR -+ -+ /* then device bar*/ -+ bar = PEX_DEVICE_BAR; -+ -+ /* save the starting window */ -+ pexStartWindow = pexCurrWin; -+ pexBar.addrWin.size = 0; -+ pexBar.addrWin.baseLow = 0xffffffff; -+ pexBar.addrWin.baseHigh = 0; -+ maxBase = 0; -+ -+ for (target = DEV_TO_TARGET(START_DEV_CS);target < DEV_TO_TARGET(MV_DEV_MAX_CS); target++ ) -+ { -+ status = mvCpuIfTargetWinGet(target,&addrDecWin); -+ -+ if (MV_NO_SUCH == status) -+ { -+ continue; -+ } -+ -+ if (MV_OK != status) -+ { -+ mvOsPrintf("mvPexInit: ERR. mvCpuIfTargetWinGet failed target =%d\n",target); -+ return MV_ERROR; -+ } -+ -+ if (addrDecWin.enable == MV_TRUE) -+ { -+ /* get the minimum base */ -+ if (addrDecWin.addrWin.baseLow < pexBar.addrWin.baseLow) -+ { -+ pexBar.addrWin.baseLow = addrDecWin.addrWin.baseLow; -+ } -+ -+ /* get the maximum base */ -+ if (addrDecWin.addrWin.baseLow > maxBase) -+ { -+ maxBase = addrDecWin.addrWin.baseLow; -+ sizeOfMaxBase = addrDecWin.addrWin.size; -+ } -+ -+ /* search in the priority table for this target */ -+ for (winIndex = 0; pexDevBarPrioTable[winIndex] != TBL_TERM; -+ winIndex++) -+ { -+ if (pexDevBarPrioTable[winIndex] != target) -+ { -+ continue; -+ } -+ else if (pexDevBarPrioTable[winIndex] == target) -+ { -+ /*found it */ -+ -+ /* if the index of this target in the prio table is valid -+ then we set the Pex window for this target, a valid index is -+ an index that is lower than the number of the windows that -+ was not configured yet */ -+ -+ /* we subtract 2 always because the default and expantion -+ rom windows are always configured */ -+ if ( pexCurrWin < PEX_MAX_TARGET_WIN - 2) -+ { -+ /* set a Pex window for this target ! */ -+ pexWin.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; -+ pexWin.addrWin.baseLow = addrDecWin.addrWin.baseLow; -+ pexWin.addrWin.size = addrDecWin.addrWin.size; -+ -+ /* we disable the windows at first because we are not -+ sure that it is witihin bar boundries */ -+ pexWin.enable = MV_FALSE; -+ pexWin.target = target; -+ pexWin.targetBar = bar; -+ -+ if (MV_OK != mvPexTargetWinSet(pexIf,pexCurrWin++, -+ &pexWin)) -+ { -+ mvOsPrintf("mvPexInit: ERR. Window Set failed\n"); -+ return MV_ERROR; -+ } -+ } -+ } -+ } -+ } -+ } -+ -+ pexBar.addrWin.size = maxBase - pexBar.addrWin.baseLow + sizeOfMaxBase; -+ pexBar.enable = MV_TRUE; -+ -+ /* check if the size of the bar is illegal */ -+ if (-1 == ctrlSizeToReg(pexBar.addrWin.size, PXBCR_BAR_SIZE_ALIGNMENT)) -+ { -+ /* try to get a good size */ -+ pexBar.addrWin.size = ctrlSizeRegRoundUp(pexBar.addrWin.size, -+ PXBCR_BAR_SIZE_ALIGNMENT); -+ } -+ -+ /* check if the size and base are valid */ -+ if (MV_TRUE == pexBarOverlapDetect(pexIf,bar,&pexBar.addrWin)) -+ { -+ mvOsPrintf("mvPexInit:Warning :Bar %d size is illigal\n",bar); -+ mvOsPrintf("it will be disabled\n"); -+ mvOsPrintf("please check Pex and CPU windows configuration\n"); -+ } -+ else -+ { -+ if (MV_OK != mvPexBarSet(pexIf, bar, &pexBar)) -+ { -+ mvOsPrintf("mvPexInit: ERR. mvPexBarSet %d failed\n", bar); -+ return MV_ERROR; -+ } -+ -+ /* now enable the windows */ -+ for (winNum = pexStartWindow; winNum < pexCurrWin ; winNum++) -+ { -+ if (MV_OK != mvPexTargetWinEnable(pexIf, winNum, MV_TRUE)) -+ { -+ mvOsPrintf("mvPexInit:mvPexTargetWinEnable winNum =%d failed \n", -+ winNum); -+ return MV_ERROR; -+ } -+ } -+ } -+ -+#endif -+ -+ return mvPexHalInit(pexIf, pexType); -+ -+} -+ -+/******************************************************************************* -+* mvPexTargetWinSet - Set PEX to peripheral target address window BAR -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_OK if PEX BAR target window was set correctly, -+* MV_BAD_PARAM on bad params -+* MV_ERROR otherwise -+* (e.g. address window overlapps with other active PEX target window). -+* -+*******************************************************************************/ -+MV_STATUS mvPexTargetWinSet(MV_U32 pexIf, MV_U32 winNum, -+ MV_PEX_DEC_WIN *pAddrDecWin) -+{ -+ -+ MV_DEC_REGS decRegs; -+ PEX_WIN_REG_INFO winRegInfo; -+ MV_TARGET_ATTRIB targetAttribs; -+ -+ /* Parameter checking */ -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexTargetWinSet: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ -+ if (winNum >= PEX_MAX_TARGET_WIN) -+ { -+ mvOsPrintf("mvPexTargetWinSet: ERR. Invalid PEX winNum %d\n", winNum); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ /* get the pex Window registers offsets */ -+ pexWinRegInfoGet(pexIf,winNum,&winRegInfo); -+ -+ -+ if (MV_TRUE == pAddrDecWin->enable) -+ { -+ -+ /* 2) Check if the requested window overlaps with current windows */ -+ if (MV_TRUE == pexWinOverlapDetect(pexIf,winNum, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("mvPexTargetWinSet: ERR. Target %d overlap\n", winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* 2) Check if the requested window overlaps with current windows */ -+ if (MV_FALSE == pexIsWinWithinBar(pexIf,&pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("mvPexTargetWinSet: Win %d should be in bar boundries\n", -+ winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ } -+ -+ -+ -+ /* read base register*/ -+ -+ if (winRegInfo.baseLowRegOffs) -+ { -+ decRegs.baseReg = MV_REG_READ(winRegInfo.baseLowRegOffs); -+ } -+ else -+ { -+ decRegs.baseReg = 0; -+ } -+ -+ if (winRegInfo.sizeRegOffs) -+ { -+ decRegs.sizeReg = MV_REG_READ(winRegInfo.sizeRegOffs); -+ } -+ else -+ { -+ decRegs.sizeReg =0; -+ } -+ -+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) -+ { -+ mvOsPrintf("mvPexTargetWinSet:mvCtrlAddrDecToReg Failed\n"); -+ return MV_ERROR; -+ } -+ -+ /* enable\Disable */ -+ if (MV_TRUE == pAddrDecWin->enable) -+ { -+ decRegs.sizeReg |= PXWCR_WIN_EN; -+ } -+ else -+ { -+ decRegs.sizeReg &= ~PXWCR_WIN_EN; -+ } -+ -+ -+ /* clear bit location */ -+ decRegs.sizeReg &= ~PXWCR_WIN_BAR_MAP_MASK; -+ -+ /* set bar Mapping */ -+ if (pAddrDecWin->targetBar == 1) -+ { -+ decRegs.sizeReg |= PXWCR_WIN_BAR_MAP_BAR1; -+ } -+ else if (pAddrDecWin->targetBar == 2) -+ { -+ decRegs.sizeReg |= PXWCR_WIN_BAR_MAP_BAR2; -+ } -+ -+ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); -+ -+ /* set attributes */ -+ decRegs.sizeReg &= ~PXWCR_ATTRIB_MASK; -+ decRegs.sizeReg |= targetAttribs.attrib << PXWCR_ATTRIB_OFFS; -+ /* set target ID */ -+ decRegs.sizeReg &= ~PXWCR_TARGET_MASK; -+ decRegs.sizeReg |= targetAttribs.targetId << PXWCR_TARGET_OFFS; -+ -+ -+ /* 3) Write to address decode Base Address Register */ -+ -+ if (winRegInfo.baseLowRegOffs) -+ { -+ MV_REG_WRITE(winRegInfo.baseLowRegOffs, decRegs.baseReg); -+ } -+ -+ /* write size reg */ -+ if (winRegInfo.sizeRegOffs) -+ { -+ if ((MV_PEX_WIN_DEFAULT == winNum)|| -+ (MV_PEX_WIN_EXP_ROM == winNum)) -+ { -+ /* clear size because there is no size field*/ -+ decRegs.sizeReg &= ~PXWCR_SIZE_MASK; -+ -+ /* clear enable because there is no enable field*/ -+ decRegs.sizeReg &= ~PXWCR_WIN_EN; -+ -+ } -+ -+ MV_REG_WRITE(winRegInfo.sizeRegOffs, decRegs.sizeReg); -+ } -+ -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvPexTargetWinGet - Get PEX to peripheral target address window -+* -+* DESCRIPTION: -+* Get the PEX to peripheral target address window BAR. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* bar - BAR to be accessed by slave. -+* -+* OUTPUT: -+* pAddrBarWin - PEX target window information data structure. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexTargetWinGet(MV_U32 pexIf, MV_U32 winNum, -+ MV_PEX_DEC_WIN *pAddrDecWin) -+{ -+ MV_TARGET_ATTRIB targetAttrib; -+ MV_DEC_REGS decRegs; -+ -+ PEX_WIN_REG_INFO winRegInfo; -+ -+ /* Parameter checking */ -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexTargetWinGet: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ -+ if (winNum >= PEX_MAX_TARGET_WIN) -+ { -+ mvOsPrintf("mvPexTargetWinGet: ERR. Invalid PEX winNum %d\n", winNum); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ /* get the pex Window registers offsets */ -+ pexWinRegInfoGet(pexIf,winNum,&winRegInfo); -+ -+ /* read base register*/ -+ if (winRegInfo.baseLowRegOffs) -+ { -+ decRegs.baseReg = MV_REG_READ(winRegInfo.baseLowRegOffs); -+ } -+ else -+ { -+ decRegs.baseReg = 0; -+ } -+ -+ /* read size reg */ -+ if (winRegInfo.sizeRegOffs) -+ { -+ decRegs.sizeReg = MV_REG_READ(winRegInfo.sizeRegOffs); -+ } -+ else -+ { -+ decRegs.sizeReg =0; -+ } -+ -+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) -+ { -+ mvOsPrintf("mvPexTargetWinGet: mvCtrlRegToAddrDec Failed \n"); -+ return MV_ERROR; -+ -+ } -+ -+ if (decRegs.sizeReg & PXWCR_WIN_EN) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ -+ } -+ -+ -+ #if 0 -+ if (-1 == pAddrDecWin->addrWin.size) -+ { -+ return MV_ERROR; -+ } -+ #endif -+ -+ -+ /* get target bar */ -+ if ((decRegs.sizeReg & PXWCR_WIN_BAR_MAP_MASK) == PXWCR_WIN_BAR_MAP_BAR1 ) -+ { -+ pAddrDecWin->targetBar = 1; -+ } -+ else if ((decRegs.sizeReg & PXWCR_WIN_BAR_MAP_MASK) == -+ PXWCR_WIN_BAR_MAP_BAR2 ) -+ { -+ pAddrDecWin->targetBar = 2; -+ } -+ -+ /* attrib and targetId */ -+ pAddrDecWin->attrib = (decRegs.sizeReg & PXWCR_ATTRIB_MASK) >> -+ PXWCR_ATTRIB_OFFS; -+ pAddrDecWin->targetId = (decRegs.sizeReg & PXWCR_TARGET_MASK) >> -+ PXWCR_TARGET_OFFS; -+ -+ targetAttrib.attrib = pAddrDecWin->attrib; -+ targetAttrib.targetId = pAddrDecWin->targetId; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ return MV_OK; -+ -+} -+ -+ -+/******************************************************************************* -+* mvPexTargetWinEnable - Enable/disable a PEX BAR window -+* -+* DESCRIPTION: -+* This function enable/disable a PEX BAR window. -+* if parameter 'enable' == MV_TRUE the routine will enable the -+* window, thus enabling PEX accesses for that BAR (before enabling the -+* window it is tested for overlapping). Otherwise, the window will -+* be disabled. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* bar - BAR to be accessed by slave. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexTargetWinEnable(MV_U32 pexIf,MV_U32 winNum, MV_BOOL enable) -+{ -+ PEX_WIN_REG_INFO winRegInfo; -+ MV_PEX_DEC_WIN addrDecWin; -+ -+ /* Parameter checking */ -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexTargetWinEnable: ERR. Invalid PEX If %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ -+ if (winNum >= PEX_MAX_TARGET_WIN) -+ { -+ mvOsPrintf("mvPexTargetWinEnable ERR. Invalid PEX winNum %d\n", winNum); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ -+ /* get the pex Window registers offsets */ -+ pexWinRegInfoGet(pexIf,winNum,&winRegInfo); -+ -+ -+ /* if the address windows is disabled , we only disable the appropriare -+ pex window and ignore other settings */ -+ -+ if (MV_FALSE == enable) -+ { -+ -+ /* this is not relevant to default and expantion rom -+ windows */ -+ if (winRegInfo.sizeRegOffs) -+ { -+ if ((MV_PEX_WIN_DEFAULT != winNum)&& -+ (MV_PEX_WIN_EXP_ROM != winNum)) -+ { -+ MV_REG_BIT_RESET(winRegInfo.sizeRegOffs, PXWCR_WIN_EN); -+ } -+ } -+ -+ } -+ else -+ { -+ if (MV_OK != mvPexTargetWinGet(pexIf,winNum, &addrDecWin)) -+ { -+ mvOsPrintf("mvPexTargetWinEnable: mvPexTargetWinGet Failed\n"); -+ return MV_ERROR; -+ } -+ -+ /* Check if the requested window overlaps with current windows */ -+ if (MV_TRUE == pexWinOverlapDetect(pexIf,winNum, &addrDecWin.addrWin)) -+ { -+ mvOsPrintf("mvPexTargetWinEnable: ERR. Target %d overlap\n", winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ if (MV_FALSE == pexIsWinWithinBar(pexIf,&addrDecWin.addrWin)) -+ { -+ mvOsPrintf("mvPexTargetWinEnable: Win %d should be in bar boundries\n", -+ winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ -+ /* this is not relevant to default and expantion rom -+ windows */ -+ if (winRegInfo.sizeRegOffs) -+ { -+ if ((MV_PEX_WIN_DEFAULT != winNum)&& -+ (MV_PEX_WIN_EXP_ROM != winNum)) -+ { -+ MV_REG_BIT_SET(winRegInfo.sizeRegOffs, PXWCR_WIN_EN); -+ } -+ } -+ -+ -+ } -+ -+ return MV_OK; -+ -+} -+ -+ -+ -+/******************************************************************************* -+* mvPexTargetWinRemap - Set PEX to target address window remap. -+* -+* DESCRIPTION: -+* The PEX interface supports remap of the BAR original address window. -+* For each BAR it is possible to define a remap address. For example -+* an address 0x12345678 that hits BAR 0x10 (SDRAM CS[0]) will be modified -+* according to remap register but will also be targeted to the -+* SDRAM CS[0]. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* bar - Peripheral target enumerator accessed by slave. -+* pAddrWin - Address window to be checked. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexTargetWinRemap(MV_U32 pexIf, MV_U32 winNum, -+ MV_PEX_REMAP_WIN *pAddrWin) -+{ -+ -+ PEX_WIN_REG_INFO winRegInfo; -+ -+ /* Parameter checking */ -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX interface num %d\n", -+ pexIf); -+ return MV_BAD_PARAM; -+ } -+ if (MV_PEX_WIN_DEFAULT == winNum) -+ { -+ mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX win num %d\n", -+ winNum); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ if (MV_IS_NOT_ALIGN(pAddrWin->addrWin.baseLow, PXWRR_REMAP_ALIGNMENT)) -+ { -+ mvOsPrintf("mvPexTargetWinRemap: Error remap PEX interface %d win %d."\ -+ "\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ pexIf, -+ winNum, -+ pAddrWin->addrWin.baseLow, -+ pAddrWin->addrWin.size); -+ -+ return MV_ERROR; -+ } -+ -+ pexWinRegInfoGet(pexIf, winNum, &winRegInfo); -+ -+ /* Set remap low register value */ -+ MV_REG_WRITE(winRegInfo.remapLowRegOffs, pAddrWin->addrWin.baseLow); -+ -+ /* Skip base high settings if the BAR has only base low (32-bit) */ -+ if (0 != winRegInfo.remapHighRegOffs) -+ { -+ MV_REG_WRITE(winRegInfo.remapHighRegOffs, pAddrWin->addrWin.baseHigh); -+ } -+ -+ -+ if (pAddrWin->enable == MV_TRUE) -+ { -+ MV_REG_BIT_SET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvPexTargetWinRemapEnable - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+ -+MV_STATUS mvPexTargetWinRemapEnable(MV_U32 pexIf, MV_U32 winNum, -+ MV_BOOL enable) -+{ -+ PEX_WIN_REG_INFO winRegInfo; -+ -+ /* Parameter checking */ -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX interface num %d\n", -+ pexIf); -+ return MV_BAD_PARAM; -+ } -+ if (MV_PEX_WIN_DEFAULT == winNum) -+ { -+ mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX win num %d\n", -+ winNum); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ -+ pexWinRegInfoGet(pexIf, winNum, &winRegInfo); -+ -+ if (enable == MV_TRUE) -+ { -+ MV_REG_BIT_SET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); -+ } -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvPexBarSet - Set PEX bar address and size -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexBarSet(MV_U32 pexIf, -+ MV_U32 barNum, -+ MV_PEX_BAR *pAddrWin) -+{ -+ MV_U32 regBaseLow; -+ MV_U32 regSize,sizeToReg; -+ -+ -+ /* check parameters */ -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexBarSet: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ -+ if(barNum >= PEX_MAX_BARS) -+ { -+ mvOsPrintf("mvPexBarSet: ERR. Invalid bar number %d\n", barNum); -+ return MV_BAD_PARAM; -+ } -+ -+ -+ if (pAddrWin->addrWin.size == 0) -+ { -+ mvOsPrintf("mvPexBarSet: Size zero is Illigal\n" ); -+ return MV_BAD_PARAM; -+ } -+ -+ -+ /* Check if the window complies with PEX spec */ -+ if (MV_TRUE != pexBarIsValid(pAddrWin->addrWin.baseLow, -+ pAddrWin->addrWin.size)) -+ { -+ mvOsPrintf("mvPexBarSet: ERR. Target %d window invalid\n", barNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* 2) Check if the requested bar overlaps with current bars */ -+ if (MV_TRUE == pexBarOverlapDetect(pexIf,barNum, &pAddrWin->addrWin)) -+ { -+ mvOsPrintf("mvPexBarSet: ERR. Target %d overlap\n", barNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Get size register value according to window size */ -+ sizeToReg = ctrlSizeToReg(pAddrWin->addrWin.size, PXBCR_BAR_SIZE_ALIGNMENT); -+ -+ /* Read bar size */ -+ if (PEX_INTER_REGS_BAR != barNum) /* internal registers have no size */ -+ { -+ regSize = MV_REG_READ(PEX_BAR_CTRL_REG(pexIf,barNum)); -+ -+ /* Size parameter validity check. */ -+ if (-1 == sizeToReg) -+ { -+ mvOsPrintf("mvPexBarSet: ERR. Target BAR %d size invalid.\n",barNum); -+ return MV_BAD_PARAM; -+ } -+ -+ regSize &= ~PXBCR_BAR_SIZE_MASK; -+ regSize |= (sizeToReg << PXBCR_BAR_SIZE_OFFS) ; -+ -+ MV_REG_WRITE(PEX_BAR_CTRL_REG(pexIf,barNum),regSize); -+ -+ } -+ -+ /* set size */ -+ -+ -+ -+ /* Read base address low */ -+ regBaseLow = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, -+ PEX_MV_BAR_BASE(barNum))); -+ -+ /* clear current base */ -+ if (PEX_INTER_REGS_BAR == barNum) -+ { -+ regBaseLow &= ~PXBIR_BASE_MASK; -+ regBaseLow |= (pAddrWin->addrWin.baseLow & PXBIR_BASE_MASK); -+ } -+ else -+ { -+ regBaseLow &= ~PXBR_BASE_MASK; -+ regBaseLow |= (pAddrWin->addrWin.baseLow & PXBR_BASE_MASK); -+ } -+ -+ /* if we had a previous value that contain the bar type (MeM\IO), we want to -+ restore it */ -+ regBaseLow |= PEX_BAR_DEFAULT_ATTRIB; -+ -+ -+ -+ /* write base low */ -+ MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE(barNum)), -+ regBaseLow); -+ -+ if (pAddrWin->addrWin.baseHigh != 0) -+ { -+ /* Read base address high */ -+ MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE_HIGH(barNum)), -+ pAddrWin->addrWin.baseHigh); -+ -+ } -+ -+ /* lastly enable the Bar */ -+ if (pAddrWin->enable == MV_TRUE) -+ { -+ if (PEX_INTER_REGS_BAR != barNum) /* internal registers -+ are enabled always */ -+ { -+ MV_REG_BIT_SET(PEX_BAR_CTRL_REG(pexIf,barNum),PXBCR_BAR_EN); -+ } -+ } -+ else if (MV_FALSE == pAddrWin->enable) -+ { -+ if (PEX_INTER_REGS_BAR != barNum) /* internal registers -+ are enabled always */ -+ { -+ MV_REG_BIT_RESET(PEX_BAR_CTRL_REG(pexIf,barNum),PXBCR_BAR_EN); -+ } -+ -+ } -+ -+ -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPexBarGet - Get PEX bar address and size -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+ -+MV_STATUS mvPexBarGet(MV_U32 pexIf, -+ MV_U32 barNum, -+ MV_PEX_BAR *pAddrWin) -+{ -+ /* check parameters */ -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexBarGet: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ -+ if(barNum >= PEX_MAX_BARS) -+ { -+ mvOsPrintf("mvPexBarGet: ERR. Invalid bar number %d\n", barNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* read base low */ -+ pAddrWin->addrWin.baseLow = -+ MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE(barNum))); -+ -+ -+ if (PEX_INTER_REGS_BAR == barNum) -+ { -+ pAddrWin->addrWin.baseLow &= PXBIR_BASE_MASK; -+ } -+ else -+ { -+ pAddrWin->addrWin.baseLow &= PXBR_BASE_MASK; -+ } -+ -+ -+ /* read base high */ -+ pAddrWin->addrWin.baseHigh = -+ MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE_HIGH(barNum))); -+ -+ -+ /* Read bar size */ -+ if (PEX_INTER_REGS_BAR != barNum) /* internal registers have no size */ -+ { -+ pAddrWin->addrWin.size = MV_REG_READ(PEX_BAR_CTRL_REG(pexIf,barNum)); -+ -+ /* check if enable or not */ -+ if (pAddrWin->addrWin.size & PXBCR_BAR_EN) -+ { -+ pAddrWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrWin->enable = MV_FALSE; -+ } -+ -+ /* now get the size */ -+ pAddrWin->addrWin.size &= PXBCR_BAR_SIZE_MASK; -+ pAddrWin->addrWin.size >>= PXBCR_BAR_SIZE_OFFS; -+ -+ pAddrWin->addrWin.size = ctrlRegToSize(pAddrWin->addrWin.size, -+ PXBCR_BAR_SIZE_ALIGNMENT); -+ -+ } -+ else /* PEX_INTER_REGS_BAR */ -+ { -+ pAddrWin->addrWin.size = INTER_REGS_SIZE; -+ pAddrWin->enable = MV_TRUE; -+ } -+ -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvPexBarEnable - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+ -+ -+MV_STATUS mvPexBarEnable(MV_U32 pexIf, MV_U32 barNum, MV_BOOL enable) -+{ -+ -+ MV_PEX_BAR pexBar; -+ -+ /* check parameters */ -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexBarEnable: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ -+ -+ if(barNum >= PEX_MAX_BARS) -+ { -+ mvOsPrintf("mvPexBarEnable: ERR. Invalid bar number %d\n", barNum); -+ return MV_BAD_PARAM; -+ } -+ -+ if (PEX_INTER_REGS_BAR == barNum) -+ { -+ if (MV_TRUE == enable) -+ { -+ return MV_OK; -+ } -+ else -+ { -+ return MV_ERROR; -+ } -+ } -+ -+ -+ if (MV_FALSE == enable) -+ { -+ /* disable bar and quit */ -+ MV_REG_BIT_RESET(PEX_BAR_CTRL_REG(pexIf,barNum),PXBCR_BAR_EN); -+ return MV_OK; -+ } -+ -+ /* else */ -+ -+ if (mvPexBarGet(pexIf,barNum,&pexBar) != MV_OK) -+ { -+ mvOsPrintf("mvPexBarEnable: mvPexBarGet Failed\n"); -+ return MV_ERROR; -+ -+ } -+ -+ if (MV_TRUE == pexBar.enable) -+ { -+ /* it is already enabled !!! */ -+ return MV_OK; -+ } -+ -+ /* else enable the bar*/ -+ -+ pexBar.enable = MV_TRUE; -+ -+ if (mvPexBarSet(pexIf,barNum,&pexBar) != MV_OK) -+ { -+ mvOsPrintf("mvPexBarEnable: mvPexBarSet Failed\n"); -+ return MV_ERROR; -+ -+ } -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* pexWinOverlapDetect - Detect address windows overlapping -+* -+* DESCRIPTION: -+* This function detects address window overlapping of a given address -+* window in PEX BARs. -+* -+* INPUT: -+* pAddrWin - Address window to be checked. -+* bar - BAR to be accessed by slave. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+static MV_BOOL pexWinOverlapDetect(MV_U32 pexIf, -+ MV_U32 winNum, -+ MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 win; -+ MV_PEX_DEC_WIN addrDecWin; -+ -+ -+ for(win = 0; win < PEX_MAX_TARGET_WIN -2 ; win++) -+ { -+ /* don't check our target or illegal targets */ -+ if (winNum == win) -+ { -+ continue; -+ } -+ -+ /* Get window parameters */ -+ if (MV_OK != mvPexTargetWinGet(pexIf, win, &addrDecWin)) -+ { -+ mvOsPrintf("pexWinOverlapDetect: ERR. TargetWinGet failed win=%x\n", -+ win); -+ return MV_ERROR; -+ } -+ -+ /* Do not check disabled windows */ -+ if (MV_FALSE == addrDecWin.enable) -+ { -+ continue; -+ } -+ -+ -+ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) -+ { -+ mvOsPrintf("pexWinOverlapDetect: winNum %d overlap current %d\n", -+ winNum, win); -+ return MV_TRUE; -+ } -+ } -+ -+ return MV_FALSE; -+} -+ -+/******************************************************************************* -+* pexIsWinWithinBar - Detect if address is within PEX bar boundries -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+static MV_BOOL pexIsWinWithinBar(MV_U32 pexIf, -+ MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 bar; -+ MV_PEX_BAR addrDecWin; -+ -+ for(bar = 0; bar < PEX_MAX_BARS; bar++) -+ { -+ -+ /* Get window parameters */ -+ if (MV_OK != mvPexBarGet(pexIf, bar, &addrDecWin)) -+ { -+ mvOsPrintf("pexIsWinWithinBar: ERR. mvPexBarGet failed\n"); -+ return MV_ERROR; -+ } -+ -+ /* Do not check disabled bars */ -+ if (MV_FALSE == addrDecWin.enable) -+ { -+ continue; -+ } -+ -+ -+ if(MV_TRUE == ctrlWinWithinWinTest(pAddrWin, &addrDecWin.addrWin)) -+ { -+ return MV_TRUE; -+ } -+ } -+ -+ return MV_FALSE; -+ -+} -+ -+/******************************************************************************* -+* pexBarOverlapDetect - Detect address windows overlapping -+* -+* DESCRIPTION: -+* This function detects address window overlapping of a given address -+* window in PEX BARs. -+* -+* INPUT: -+* pAddrWin - Address window to be checked. -+* bar - BAR to be accessed by slave. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+static MV_BOOL pexBarOverlapDetect(MV_U32 pexIf, -+ MV_U32 barNum, -+ MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 bar; -+ MV_PEX_BAR barDecWin; -+ -+ -+ for(bar = 0; bar < PEX_MAX_BARS; bar++) -+ { -+ /* don't check our target or illegal targets */ -+ if (barNum == bar) -+ { -+ continue; -+ } -+ -+ /* Get window parameters */ -+ if (MV_OK != mvPexBarGet(pexIf, bar, &barDecWin)) -+ { -+ mvOsPrintf("pexBarOverlapDetect: ERR. TargetWinGet failed\n"); -+ return MV_ERROR; -+ } -+ -+ /* don'nt check disabled bars */ -+ if (barDecWin.enable == MV_FALSE) -+ { -+ continue; -+ } -+ -+ -+ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &barDecWin.addrWin)) -+ { -+ mvOsPrintf("pexBarOverlapDetect: winNum %d overlap current %d\n", -+ barNum, bar); -+ return MV_TRUE; -+ } -+ } -+ -+ return MV_FALSE; -+} -+ -+/******************************************************************************* -+* pexBarIsValid - Check if the given address window is valid -+* -+* DESCRIPTION: -+* PEX spec restrict BAR base to be aligned to BAR size. -+* This function checks if the given address window is valid. -+* -+* INPUT: -+* baseLow - 32bit low base address. -+* size - Window size. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the address window is valid, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+static MV_STATUS pexBarIsValid(MV_U32 baseLow, MV_U32 size) -+{ -+ -+ /* PCI spec restrict BAR base to be aligned to BAR size */ -+ if(MV_IS_NOT_ALIGN(baseLow, size)) -+ { -+ return MV_ERROR; -+ } -+ else -+ { -+ return MV_TRUE; -+ } -+ -+ return MV_TRUE; -+} -+ -+/******************************************************************************* -+* pexBarRegInfoGet - Get BAR register information -+* -+* DESCRIPTION: -+* PEX BARs registers offsets are inconsecutive. -+* This function gets a PEX BAR register information like register offsets -+* and function location of the BAR. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* bar - The PEX BAR in question. -+* -+* OUTPUT: -+* pBarRegInfo - BAR register info struct. -+* -+* RETURN: -+* MV_BAD_PARAM when bad parameters ,MV_ERROR on error ,othewise MV_OK -+* -+*******************************************************************************/ -+static MV_STATUS pexWinRegInfoGet(MV_U32 pexIf, -+ MV_U32 winNum, -+ PEX_WIN_REG_INFO *pWinRegInfo) -+{ -+ -+ if ((winNum >= 0)&&(winNum <=3)) -+ { -+ pWinRegInfo->baseLowRegOffs = PEX_WIN0_3_BASE_REG(pexIf,winNum); -+ pWinRegInfo->baseHighRegOffs = 0; -+ pWinRegInfo->sizeRegOffs = PEX_WIN0_3_CTRL_REG(pexIf,winNum); -+ pWinRegInfo->remapLowRegOffs = PEX_WIN0_3_REMAP_REG(pexIf,winNum); -+ pWinRegInfo->remapHighRegOffs = 0; -+ } -+ else if ((winNum >= 4)&&(winNum <=5)) -+ { -+ pWinRegInfo->baseLowRegOffs = PEX_WIN4_5_BASE_REG(pexIf,winNum); -+ pWinRegInfo->baseHighRegOffs = 0; -+ pWinRegInfo->sizeRegOffs = PEX_WIN4_5_CTRL_REG(pexIf,winNum); -+ pWinRegInfo->remapLowRegOffs = PEX_WIN4_5_REMAP_REG(pexIf,winNum); -+ pWinRegInfo->remapHighRegOffs = PEX_WIN4_5_REMAP_HIGH_REG(pexIf,winNum); -+ -+ } -+ else if (MV_PEX_WIN_DEFAULT == winNum) -+ { -+ pWinRegInfo->baseLowRegOffs = 0; -+ pWinRegInfo->baseHighRegOffs = 0; -+ pWinRegInfo->sizeRegOffs = PEX_WIN_DEFAULT_CTRL_REG(pexIf); -+ pWinRegInfo->remapLowRegOffs = 0; -+ pWinRegInfo->remapHighRegOffs = 0; -+ } -+ else if (MV_PEX_WIN_EXP_ROM == winNum) -+ { -+ pWinRegInfo->baseLowRegOffs = 0; -+ pWinRegInfo->baseHighRegOffs = 0; -+ pWinRegInfo->sizeRegOffs = PEX_WIN_EXP_ROM_CTRL_REG(pexIf); -+ pWinRegInfo->remapLowRegOffs = PEX_WIN_EXP_ROM_REMAP_REG(pexIf); -+ pWinRegInfo->remapHighRegOffs = 0; -+ -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* pexBarNameGet - Get the string name of PEX BAR. -+* -+* DESCRIPTION: -+* This function get the string name of PEX BAR. -+* -+* INPUT: -+* bar - PEX bar number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* pointer to the string name of PEX BAR. -+* -+*******************************************************************************/ -+const MV_8* pexBarNameGet( MV_U32 bar ) -+{ -+ switch( bar ) -+ { -+ case PEX_INTER_REGS_BAR: -+ return "Internal Regs Bar0...."; -+ case PEX_DRAM_BAR: -+ return "DRAM Bar1............."; -+ case PEX_DEVICE_BAR: -+ return "Devices Bar2.........."; -+ default: -+ return "Bar unknown"; -+ } -+} -+/******************************************************************************* -+* mvPexAddrDecShow - Print the PEX address decode map (BARs and windows). -+* -+* DESCRIPTION: -+* This function print the PEX address decode map (BARs and windows). -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvPexAddrDecShow(MV_VOID) -+{ -+ MV_PEX_BAR pexBar; -+ MV_PEX_DEC_WIN win; -+ MV_U32 pexIf; -+ MV_U32 bar,winNum; -+ -+ for( pexIf = 0; pexIf < mvCtrlPexMaxIfGet(); pexIf++ ) -+ { -+ if (MV_FALSE == mvCtrlPwrClckGet(PEX_UNIT_ID, pexIf)) continue; -+ mvOsOutput( "\n" ); -+ mvOsOutput( "PEX%d:\n", pexIf ); -+ mvOsOutput( "-----\n" ); -+ -+ mvOsOutput( "\nPex Bars \n\n"); -+ -+ for( bar = 0; bar < PEX_MAX_BARS; bar++ ) -+ { -+ memset( &pexBar, 0, sizeof(MV_PEX_BAR) ); -+ -+ mvOsOutput( "%s ", pexBarNameGet(bar) ); -+ -+ if( mvPexBarGet( pexIf, bar, &pexBar ) == MV_OK ) -+ { -+ if( pexBar.enable ) -+ { -+ mvOsOutput( "base %08x, ", pexBar.addrWin.baseLow ); -+ mvSizePrint( pexBar.addrWin.size ); -+ mvOsOutput( "\n" ); -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ } -+ } -+ mvOsOutput( "\nPex Decode Windows\n\n"); -+ -+ for( winNum = 0; winNum < PEX_MAX_TARGET_WIN - 2; winNum++) -+ { -+ memset( &win, 0,sizeof(MV_PEX_DEC_WIN) ); -+ -+ mvOsOutput( "win%d - ", winNum ); -+ -+ if ( mvPexTargetWinGet(pexIf,winNum,&win) == MV_OK) -+ { -+ if (win.enable) -+ { -+ mvOsOutput( "%s base %08x, ", -+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); -+ mvOsOutput( "...." ); -+ mvSizePrint( win.addrWin.size ); -+ -+ mvOsOutput( "\n" ); -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ -+ -+ } -+ } -+ -+ memset( &win, 0,sizeof(MV_PEX_DEC_WIN) ); -+ -+ mvOsOutput( "default win - " ); -+ -+ if ( mvPexTargetWinGet(pexIf, MV_PEX_WIN_DEFAULT, &win) == MV_OK) -+ { -+ mvOsOutput( "%s ", -+ mvCtrlTargetNameGet(win.target) ); -+ mvOsOutput( "\n" ); -+ } -+ memset( &win, 0,sizeof(MV_PEX_DEC_WIN) ); -+ -+ mvOsOutput( "Expansion ROM - " ); -+ -+ if ( mvPexTargetWinGet(pexIf, MV_PEX_WIN_EXP_ROM, &win) == MV_OK) -+ { -+ mvOsOutput( "%s ", -+ mvCtrlTargetNameGet(win.target) ); -+ mvOsOutput( "\n" ); -+ } -+ -+ } -+} -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,348 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCSysPEXH -+#define __INCSysPEXH -+ -+#include "mvCommon.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+ -+/* 4KB granularity */ -+#define MINIMUM_WINDOW_SIZE 0x1000 -+#define MINIMUM_BAR_SIZE 0x1000 -+#define MINIMUM_BAR_SIZE_MASK 0xFFFFF000 -+#define BAR_SIZE_OFFS 12 -+#define BAR_SIZE_MASK (0xFFFFF << BAR_SIZE_OFFS) -+ -+ -+ -+#define MV_PEX_WIN_DEFAULT 6 -+#define MV_PEX_WIN_EXP_ROM 7 -+#define PEX_MAX_TARGET_WIN 8 -+ -+ -+#define PEX_MAX_BARS 3 -+#define PEX_INTER_REGS_BAR 0 -+#define PEX_DRAM_BAR 1 -+#define PEX_DEVICE_BAR 2 -+ -+/*************************************/ -+/* PCI Express BAR Control Registers */ -+/*************************************/ -+#define PEX_BAR_CTRL_REG(pexIf,bar) (0x41804 + (bar-1)*4- (pexIf)*0x10000) -+#define PEX_EXP_ROM_BAR_CTRL_REG(pexIf) (0x4180C - (pexIf)*0x10000) -+ -+ -+/* PCI Express BAR Control Register */ -+/* PEX_BAR_CTRL_REG (PXBCR) */ -+ -+#define PXBCR_BAR_EN BIT0 -+#define PXBCR_BAR_SIZE_OFFS 16 -+#define PXBCR_BAR_SIZE_MASK (0xffff << PXBCR_BAR_SIZE_OFFS) -+#define PXBCR_BAR_SIZE_ALIGNMENT 0x10000 -+ -+ -+ -+/* PCI Express Expansion ROM BAR Control Register */ -+/* PEX_EXP_ROM_BAR_CTRL_REG (PXERBCR) */ -+ -+#define PXERBCR_EXPROM_EN BIT0 -+#define PXERBCR_EXPROMSZ_OFFS 19 -+#define PXERBCR_EXPROMSZ_MASK (0xf << PXERBCR_EXPROMSZ_OFFS) -+#define PXERBCR_EXPROMSZ_512KB (0x0 << PXERBCR_EXPROMSZ_OFFS) -+#define PXERBCR_EXPROMSZ_1024KB (0x1 << PXERBCR_EXPROMSZ_OFFS) -+#define PXERBCR_EXPROMSZ_2048KB (0x3 << PXERBCR_EXPROMSZ_OFFS) -+#define PXERBCR_EXPROMSZ_4096KB (0x7 << PXERBCR_EXPROMSZ_OFFS) -+ -+/************************************************/ -+/* PCI Express Address Window Control Registers */ -+/************************************************/ -+#define PEX_WIN0_3_CTRL_REG(pexIf,winNum) \ -+ (0x41820 + (winNum) * 0x10 - (pexIf) * 0x10000) -+#define PEX_WIN0_3_BASE_REG(pexIf,winNum) \ -+ (0x41824 + (winNum) * 0x10 - (pexIf) * 0x10000) -+#define PEX_WIN0_3_REMAP_REG(pexIf,winNum) \ -+ (0x4182C + (winNum) * 0x10 - (pexIf) * 0x10000) -+#define PEX_WIN4_5_CTRL_REG(pexIf,winNum) \ -+ (0x41860 + (winNum - 4) * 0x20 - (pexIf) * 0x10000) -+#define PEX_WIN4_5_BASE_REG(pexIf,winNum) \ -+ (0x41864 + (winNum - 4) * 0x20 - (pexIf) * 0x10000) -+#define PEX_WIN4_5_REMAP_REG(pexIf,winNum) \ -+ (0x4186C + (winNum - 4) * 0x20 - (pexIf) * 0x10000) -+#define PEX_WIN4_5_REMAP_HIGH_REG(pexIf,winNum) \ -+ (0x41870 + (winNum - 4) * 0x20 - (pexIf) * 0x10000) -+ -+#define PEX_WIN_DEFAULT_CTRL_REG(pexIf) (0x418B0 - (pexIf) * 0x10000) -+#define PEX_WIN_EXP_ROM_CTRL_REG(pexIf) (0x418C0 - (pexIf) * 0x10000) -+#define PEX_WIN_EXP_ROM_REMAP_REG(pexIf) (0x418C4 - (pexIf) * 0x10000) -+ -+/* PCI Express Window Control Register */ -+/* PEX_WIN_CTRL_REG (PXWCR) */ -+ -+#define PXWCR_WIN_EN BIT0 /* Window Enable.*/ -+ -+#define PXWCR_WIN_BAR_MAP_OFFS 1 /* Mapping to BAR.*/ -+#define PXWCR_WIN_BAR_MAP_MASK BIT1 -+#define PXWCR_WIN_BAR_MAP_BAR1 (0 << PXWCR_WIN_BAR_MAP_OFFS) -+#define PXWCR_WIN_BAR_MAP_BAR2 (1 << PXWCR_WIN_BAR_MAP_OFFS) -+ -+#define PXWCR_TARGET_OFFS 4 /*Unit ID */ -+#define PXWCR_TARGET_MASK (0xf << PXWCR_TARGET_OFFS) -+ -+#define PXWCR_ATTRIB_OFFS 8 /* target attributes */ -+#define PXWCR_ATTRIB_MASK (0xff << PXWCR_ATTRIB_OFFS) -+ -+#define PXWCR_SIZE_OFFS 16 /* size */ -+#define PXWCR_SIZE_MASK (0xffff << PXWCR_SIZE_OFFS) -+#define PXWCR_SIZE_ALIGNMENT 0x10000 -+ -+/* PCI Express Window Base Register */ -+/* PEX_WIN_BASE_REG (PXWBR)*/ -+ -+#define PXWBR_BASE_OFFS 16 /* address[31:16] */ -+#define PXWBR_BASE_MASK (0xffff << PXWBR_BASE_OFFS) -+#define PXWBR_BASE_ALIGNMENT 0x10000 -+ -+/* PCI Express Window Remap Register */ -+/* PEX_WIN_REMAP_REG (PXWRR)*/ -+ -+#define PXWRR_REMAP_EN BIT0 -+#define PXWRR_REMAP_OFFS 16 -+#define PXWRR_REMAP_MASK (0xffff << PXWRR_REMAP_OFFS) -+#define PXWRR_REMAP_ALIGNMENT 0x10000 -+ -+/* PCI Express Window Remap (High) Register */ -+/* PEX_WIN_REMAP_HIGH_REG (PXWRHR)*/ -+ -+#define PXWRHR_REMAP_HIGH_OFFS 0 -+#define PXWRHR_REMAP_HIGH_MASK (0xffffffff << PXWRHR_REMAP_HIGH_OFFS) -+ -+/* PCI Express Default Window Control Register */ -+/* PEX_WIN_DEFAULT_CTRL_REG (PXWDCR) */ -+ -+#define PXWDCR_TARGET_OFFS 4 /*Unit ID */ -+#define PXWDCR_TARGET_MASK (0xf << PXWDCR_TARGET_OFFS) -+#define PXWDCR_ATTRIB_OFFS 8 /* target attributes */ -+#define PXWDCR_ATTRIB_MASK (0xff << PXWDCR_ATTRIB_OFFS) -+ -+/* PCI Express Expansion ROM Window Control Register */ -+/* PEX_WIN_EXP_ROM_CTRL_REG (PXWERCR)*/ -+ -+#define PXWERCR_TARGET_OFFS 4 /*Unit ID */ -+#define PXWERCR_TARGET_MASK (0xf << PXWERCR_TARGET_OFFS) -+#define PXWERCR_ATTRIB_OFFS 8 /* target attributes */ -+#define PXWERCR_ATTRIB_MASK (0xff << PXWERCR_ATTRIB_OFFS) -+ -+/* PCI Express Expansion ROM Window Remap Register */ -+/* PEX_WIN_EXP_ROM_REMAP_REG (PXWERRR)*/ -+ -+#define PXWERRR_REMAP_EN BIT0 -+#define PXWERRR_REMAP_OFFS 16 -+#define PXWERRR_REMAP_MASK (0xffff << PXWERRR_REMAP_OFFS) -+#define PXWERRR_REMAP_ALIGNMENT 0x10000 -+ -+ -+ -+/*PEX_MEMORY_BAR_BASE_ADDR(barNum) (PXMBBA)*/ -+/* PCI Express BAR0 Internal Register*/ -+/*PEX BAR0_INTER_REG (PXBIR)*/ -+ -+#define PXBIR_IOSPACE BIT0 /* Memory Space Indicator */ -+ -+#define PXBIR_TYPE_OFFS 1 /* BAR Type/Init Val. */ -+#define PXBIR_TYPE_MASK (0x3 << PXBIR_TYPE_OFFS) -+#define PXBIR_TYPE_32BIT_ADDR (0x0 << PXBIR_TYPE_OFFS) -+#define PXBIR_TYPE_64BIT_ADDR (0x2 << PXBIR_TYPE_OFFS) -+ -+#define PXBIR_PREFETCH_EN BIT3 /* Prefetch Enable */ -+ -+#define PXBIR_BASE_OFFS 20 /* Base address. Address bits [31:20] */ -+#define PXBIR_BASE_MASK (0xfff << PXBIR_BASE_OFFS) -+#define PXBIR_BASE_ALIGNMET (1 << PXBIR_BASE_OFFS) -+ -+ -+/* PCI Express BAR0 Internal (High) Register*/ -+/*PEX BAR0_INTER_REG_HIGH (PXBIRH)*/ -+ -+#define PXBIRH_BASE_OFFS 0 /* Base address. Bits [63:32] */ -+#define PXBIRH_BASE_MASK (0xffffffff << PBBHR_BASE_OFFS) -+ -+ -+#define PEX_BAR_DEFAULT_ATTRIB 0xc /* Memory - Prefetch - 64 bit address */ -+#define PEX_BAR0_DEFAULT_ATTRIB PEX_BAR_DEFAULT_ATTRIB -+#define PEX_BAR1_DEFAULT_ATTRIB PEX_BAR_DEFAULT_ATTRIB -+#define PEX_BAR2_DEFAULT_ATTRIB PEX_BAR_DEFAULT_ATTRIB -+ -+ -+/* PCI Express BAR1 Register */ -+/* PCI Express BAR2 Register*/ -+/*PEX BAR1_REG (PXBR)*/ -+/*PEX BAR2_REG (PXBR)*/ -+ -+#define PXBR_IOSPACE BIT0 /* Memory Space Indicator */ -+ -+#define PXBR_TYPE_OFFS 1 /* BAR Type/Init Val. */ -+#define PXBR_TYPE_MASK (0x3 << PXBR_TYPE_OFFS) -+#define PXBR_TYPE_32BIT_ADDR (0x0 << PXBR_TYPE_OFFS) -+#define PXBR_TYPE_64BIT_ADDR (0x2 << PXBR_TYPE_OFFS) -+ -+#define PXBR_PREFETCH_EN BIT3 /* Prefetch Enable */ -+ -+#define PXBR_BASE_OFFS 16 /* Base address. Address bits [31:16] */ -+#define PXBR_BASE_MASK (0xffff << PXBR_BASE_OFFS) -+#define PXBR_BASE_ALIGNMET (1 << PXBR_BASE_OFFS) -+ -+ -+/* PCI Express BAR1 (High) Register*/ -+/* PCI Express BAR2 (High) Register*/ -+/*PEX BAR1_REG_HIGH (PXBRH)*/ -+/*PEX BAR2_REG_HIGH (PXBRH)*/ -+ -+#define PXBRH_BASE_OFFS 0 /* Base address. Address bits [63:32] */ -+#define PXBRH_BASE_MASK (0xffffffff << PXBRH_BASE_OFFS) -+ -+/* PCI Express Expansion ROM BAR Register*/ -+/*PEX_EXPANSION_ROM_BASE_ADDR_REG (PXERBAR)*/ -+ -+#define PXERBAR_EXPROMEN BIT0 /* Expansion ROM Enable */ -+ -+#define PXERBAR_BASE_512K_OFFS 19 /* Expansion ROM Base Address */ -+#define PXERBAR_BASE_512K_MASK (0x1fff << PXERBAR_BASE_512K_OFFS) -+ -+#define PXERBAR_BASE_1MB_OFFS 20 /* Expansion ROM Base Address */ -+#define PXERBAR_BASE_1MB_MASK (0xfff << PXERBAR_BASE_1MB_OFFS) -+ -+#define PXERBAR_BASE_2MB_OFFS 21 /* Expansion ROM Base Address */ -+#define PXERBAR_BASE_2MB_MASK (0x7ff << PXERBAR_BASE_2MB_OFFS) -+ -+#define PXERBAR_BASE_4MB_OFFS 22 /* Expansion ROM Base Address */ -+#define PXERBAR_BASE_4MB_MASK (0x3ff << PXERBAR_BASE_4MB_OFFS) -+ -+/* PEX Bar attributes */ -+typedef struct _mvPexBar -+{ -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+}MV_PEX_BAR; -+ -+/* PEX Remap Window attributes */ -+typedef struct _mvPexRemapWin -+{ -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+}MV_PEX_REMAP_WIN; -+ -+/* PEX Remap Window attributes */ -+typedef struct _mvPexDecWin -+{ -+ MV_TARGET target; -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_U32 targetBar; -+ MV_U8 attrib; /* chip select attributes */ -+ MV_TARGET_ID targetId; /* Target Id of this MV_TARGET */ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+}MV_PEX_DEC_WIN; -+ -+/* Global Functions prototypes */ -+/* mvPexHalInit - Initialize PEX interfaces*/ -+MV_STATUS mvPexInit(MV_U32 pexIf, MV_PEX_TYPE pexType); -+ -+ -+/* mvPexTargetWinSet - Set PEX to peripheral target address window BAR*/ -+MV_STATUS mvPexTargetWinSet(MV_U32 pexIf, MV_U32 winNum, -+ MV_PEX_DEC_WIN *pAddrDecWin); -+ -+/* mvPexTargetWinGet - Get PEX to peripheral target address window*/ -+MV_STATUS mvPexTargetWinGet(MV_U32 pexIf, MV_U32 winNum, -+ MV_PEX_DEC_WIN *pAddrDecWin); -+ -+/* mvPexTargetWinEnable - Enable/disable a PEX BAR window*/ -+MV_STATUS mvPexTargetWinEnable(MV_U32 pexIf,MV_U32 winNum, MV_BOOL enable); -+ -+/* mvPexTargetWinRemap - Set PEX to target address window remap.*/ -+MV_STATUS mvPexTargetWinRemap(MV_U32 pexIf, MV_U32 winNum, -+ MV_PEX_REMAP_WIN *pAddrWin); -+ -+/* mvPexTargetWinRemapEnable -enable\disable a PEX Window remap.*/ -+MV_STATUS mvPexTargetWinRemapEnable(MV_U32 pexIf, MV_U32 winNum, -+ MV_BOOL enable); -+ -+/* mvPexBarSet - Set PEX bar address and size */ -+MV_STATUS mvPexBarSet(MV_U32 pexIf, MV_U32 barNum, MV_PEX_BAR *addrWin); -+ -+/* mvPexBarGet - Get PEX bar address and size */ -+MV_STATUS mvPexBarGet(MV_U32 pexIf, MV_U32 barNum, MV_PEX_BAR *addrWin); -+ -+/* mvPexBarEnable - enable\disable a PEX bar*/ -+MV_STATUS mvPexBarEnable(MV_U32 pexIf, MV_U32 barNum, MV_BOOL enable); -+ -+/* mvPexAddrDecShow - Display address decode windows attributes */ -+MV_VOID mvPexAddrDecShow(MV_VOID); -+ -+#endif -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,430 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#include "mvTypes.h" -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "cpu/mvCpu.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+#include "sata/CoreDriver/mvRegs.h" -+#include "ctrlEnv/sys/mvSysSata.h" -+ -+MV_TARGET sataAddrDecPrioTab[] = -+{ -+#if defined(MV_INCLUDE_SDRAM_CS0) -+ SDRAM_CS0, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS1) -+ SDRAM_CS1, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS2) -+ SDRAM_CS2, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS3) -+ SDRAM_CS3, -+#endif -+#if defined(MV_INCLUDE_PEX) -+ PEX0_MEM, -+#endif -+ TBL_TERM -+}; -+ -+ -+/******************************************************************************* -+* sataWinOverlapDetect - Detect SATA address windows overlapping -+* -+* DESCRIPTION: -+* An unpredicted behaviur is expected in case SATA address decode -+* windows overlapps. -+* This function detects SATA address decode windows overlapping of a -+* specified window. The function does not check the window itself for -+* overlapping. The function also skipps disabled address decode windows. -+* -+* INPUT: -+* winNum - address decode window number. -+* pAddrDecWin - An address decode window struct. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data -+* from registers. -+* -+*******************************************************************************/ -+static MV_STATUS sataWinOverlapDetect(int dev, MV_U32 winNum, -+ MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 winNumIndex; -+ MV_SATA_DEC_WIN addrDecWin; -+ -+ for(winNumIndex=0; winNumIndex= MV_SATA_MAX_ADDR_DECODE_WIN) -+ { -+ mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlapps with current windows */ -+ if (MV_TRUE == sataWinOverlapDetect(dev, winNum, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); -+ return MV_ERROR; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvSataWinSet:Error setting SATA window %d to "\ -+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, -+ mvCtrlTargetNameGet(pAddrDecWin->target), -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ decRegs.baseReg = 0; -+ decRegs.sizeReg = 0; -+ -+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) -+ { -+ mvOsPrintf("%s: mvCtrlAddrDecToReg Failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); -+ -+ /* set attributes */ -+ decRegs.sizeReg &= ~MV_SATA_WIN_ATTR_MASK; -+ decRegs.sizeReg |= (targetAttribs.attrib << MV_SATA_WIN_ATTR_OFFSET); -+ -+ /* set target ID */ -+ decRegs.sizeReg &= ~MV_SATA_WIN_TARGET_MASK; -+ decRegs.sizeReg |= (targetAttribs.targetId << MV_SATA_WIN_TARGET_OFFSET); -+ -+ if (pAddrDecWin->enable == MV_TRUE) -+ { -+ decRegs.sizeReg |= MV_SATA_WIN_ENABLE_MASK; -+ } -+ else -+ { -+ decRegs.sizeReg &= ~MV_SATA_WIN_ENABLE_MASK; -+ } -+ -+ MV_REG_WRITE( MV_SATA_WIN_CTRL_REG(dev, winNum), decRegs.sizeReg); -+ MV_REG_WRITE( MV_SATA_WIN_BASE_REG(dev, winNum), decRegs.baseReg); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSataWinGet - Get SATA peripheral target address window. -+* -+* DESCRIPTION: -+* Get SATA peripheral target address window. -+* -+* INPUT: -+* winNum - SATA target address decode window number. -+* -+* OUTPUT: -+* pAddrDecWin - SATA target window data structure. -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvSataWinGet(int dev, MV_U32 winNum, MV_SATA_DEC_WIN *pAddrDecWin) -+{ -+ MV_DEC_REGS decRegs; -+ MV_TARGET_ATTRIB targetAttrib; -+ -+ /* Parameter checking */ -+ if (winNum >= MV_SATA_MAX_ADDR_DECODE_WIN) -+ { -+ mvOsPrintf("%s (dev=%d): ERR. Invalid winNum %d\n", -+ __FUNCTION__, dev, winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ decRegs.baseReg = MV_REG_READ( MV_SATA_WIN_BASE_REG(dev, winNum) ); -+ decRegs.sizeReg = MV_REG_READ( MV_SATA_WIN_CTRL_REG(dev, winNum) ); -+ -+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs, &pAddrDecWin->addrWin) ) -+ { -+ mvOsPrintf("%s: mvCtrlRegToAddrDec Failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ /* attrib and targetId */ -+ targetAttrib.attrib = (decRegs.sizeReg & MV_SATA_WIN_ATTR_MASK) >> -+ MV_SATA_WIN_ATTR_OFFSET; -+ targetAttrib.targetId = (decRegs.sizeReg & MV_SATA_WIN_TARGET_MASK) >> -+ MV_SATA_WIN_TARGET_OFFSET; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ /* Check if window is enabled */ -+ if(decRegs.sizeReg & MV_SATA_WIN_ENABLE_MASK) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ } -+ return MV_OK; -+} -+/******************************************************************************* -+* mvSataAddrDecShow - Print the SATA address decode map. -+* -+* DESCRIPTION: -+* This function print the SATA address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvSataAddrDecShow(MV_VOID) -+{ -+ -+ MV_SATA_DEC_WIN win; -+ int i,j; -+ -+ -+ -+ for( j = 0; j < MV_SATA_MAX_CHAN; j++ ) -+ { -+ if (MV_FALSE == mvCtrlPwrClckGet(SATA_UNIT_ID, j)) -+ return; -+ -+ mvOsOutput( "\n" ); -+ mvOsOutput( "SATA %d:\n", j ); -+ mvOsOutput( "----\n" ); -+ -+ for( i = 0; i < MV_SATA_MAX_ADDR_DECODE_WIN; i++ ) -+ { -+ memset( &win, 0, sizeof(MV_SATA_DEC_WIN) ); -+ -+ mvOsOutput( "win%d - ", i ); -+ -+ if( mvSataWinGet(j, i, &win ) == MV_OK ) -+ { -+ if( win.enable ) -+ { -+ mvOsOutput( "%s base %08x, ", -+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); -+ mvOsOutput( "...." ); -+ -+ mvSizePrint( win.addrWin.size ); -+ -+ mvOsOutput( "\n" ); -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ } -+ } -+ } -+} -+ -+ -+/******************************************************************************* -+* mvSataWinInit - Initialize the integrated SATA target address window. -+* -+* DESCRIPTION: -+* Initialize the SATA peripheral target address window. -+* -+* INPUT: -+* -+* -+* OUTPUT: -+* -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvSataWinInit(MV_VOID) -+{ -+ int winNum; -+ MV_SATA_DEC_WIN sataWin; -+ MV_CPU_DEC_WIN cpuAddrDecWin; -+ MV_U32 status, winPrioIndex = 0; -+ -+ /* Initiate Sata address decode */ -+ -+ /* First disable all address decode windows */ -+ for(winNum = 0; winNum < MV_SATA_MAX_ADDR_DECODE_WIN; winNum++) -+ { -+ MV_U32 regVal = MV_REG_READ(MV_SATA_WIN_CTRL_REG(0, winNum)); -+ regVal &= ~MV_SATA_WIN_ENABLE_MASK; -+ MV_REG_WRITE(MV_SATA_WIN_CTRL_REG(0, winNum), regVal); -+ } -+ -+ winNum = 0; -+ while( (sataAddrDecPrioTab[winPrioIndex] != TBL_TERM) && -+ (winNum < MV_SATA_MAX_ADDR_DECODE_WIN) ) -+ { -+ /* first get attributes from CPU If */ -+ status = mvCpuIfTargetWinGet(sataAddrDecPrioTab[winPrioIndex], -+ &cpuAddrDecWin); -+ -+ if(MV_NO_SUCH == status) -+ { -+ winPrioIndex++; -+ continue; -+ } -+ if (MV_OK != status) -+ { -+ mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ if (cpuAddrDecWin.enable == MV_TRUE) -+ { -+ sataWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; -+ sataWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; -+ sataWin.addrWin.size = cpuAddrDecWin.addrWin.size; -+ sataWin.enable = MV_TRUE; -+ sataWin.target = sataAddrDecPrioTab[winPrioIndex]; -+ -+ if(MV_OK != mvSataWinSet(0/*dev*/, winNum, &sataWin)) -+ { -+ return MV_ERROR; -+ } -+ winNum++; -+ } -+ winPrioIndex++; -+ } -+ return MV_OK; -+} -+ -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,128 @@ -+ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#ifndef __INCMVSysSataAddrDech -+#define __INCMVSysSataAddrDech -+ -+#include "mvCommon.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+ -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+typedef struct _mvSataDecWin -+{ -+ MV_TARGET target; -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+} MV_SATA_DEC_WIN; -+ -+ -+#define MV_SATA_MAX_ADDR_DECODE_WIN 4 -+ -+#define MV_SATA_WIN_CTRL_REG(dev, win) (SATA_REG_BASE + 0x30 + ((win)<<4)) -+#define MV_SATA_WIN_BASE_REG(dev, win) (SATA_REG_BASE + 0x34 + ((win)<<4)) -+ -+/* BITs in Bridge Interrupt Cause and Mask registers */ -+#define MV_SATA_ADDR_DECODE_ERROR_BIT 0 -+#define MV_SATA_ADDR_DECODE_ERROR_MASK (1<= MV_SDMMC_MAX_ADDR_DECODE_WIN) -+ { -+ mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlapps with current windows */ -+ if (MV_TRUE == sdmmcWinOverlapDetect(dev, winNum, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); -+ return MV_ERROR; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvSdmmcWinSet:Error setting SDMMC window %d to "\ -+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, -+ mvCtrlTargetNameGet(pAddrDecWin->target), -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ decRegs.baseReg = 0; -+ decRegs.sizeReg = 0; -+ -+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) -+ { -+ mvOsPrintf("%s: mvCtrlAddrDecToReg Failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); -+ -+ /* set attributes */ -+ decRegs.sizeReg &= ~MV_SDMMC_WIN_ATTR_MASK; -+ decRegs.sizeReg |= (targetAttribs.attrib << MV_SDMMC_WIN_ATTR_OFFSET); -+ -+ /* set target ID */ -+ decRegs.sizeReg &= ~MV_SDMMC_WIN_TARGET_MASK; -+ decRegs.sizeReg |= (targetAttribs.targetId << MV_SDMMC_WIN_TARGET_OFFSET); -+ -+ if (pAddrDecWin->enable == MV_TRUE) -+ { -+ decRegs.sizeReg |= MV_SDMMC_WIN_ENABLE_MASK; -+ } -+ else -+ { -+ decRegs.sizeReg &= ~MV_SDMMC_WIN_ENABLE_MASK; -+ } -+ -+ MV_REG_WRITE( MV_SDMMC_WIN_CTRL_REG(dev, winNum), decRegs.sizeReg); -+ MV_REG_WRITE( MV_SDMMC_WIN_BASE_REG(dev, winNum), decRegs.baseReg); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSdmmcWinGet - Get SDMMC peripheral target address window. -+* -+* DESCRIPTION: -+* Get SDMMC peripheral target address window. -+* -+* INPUT: -+* winNum - SDMMC target address decode window number. -+*d -+* OUTPUT: -+* pAddrDecWin - SDMMC target window data structure. -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvSdmmcWinGet(int dev, MV_U32 winNum, MV_SDMMC_DEC_WIN *pAddrDecWin) -+{ -+ MV_DEC_REGS decRegs; -+ MV_TARGET_ATTRIB targetAttrib; -+ -+ /* Parameter checking */ -+ if (winNum >= MV_SDMMC_MAX_ADDR_DECODE_WIN) -+ { -+ mvOsPrintf("%s (dev=%d): ERR. Invalid winNum %d\n", -+ __FUNCTION__, dev, winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ decRegs.baseReg = MV_REG_READ( MV_SDMMC_WIN_BASE_REG(dev, winNum) ); -+ decRegs.sizeReg = MV_REG_READ( MV_SDMMC_WIN_CTRL_REG(dev, winNum) ); -+ -+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs, &pAddrDecWin->addrWin) ) -+ { -+ mvOsPrintf("%s: mvCtrlRegToAddrDec Failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ /* attrib and targetId */ -+ targetAttrib.attrib = (decRegs.sizeReg & MV_SDMMC_WIN_ATTR_MASK) >> -+ MV_SDMMC_WIN_ATTR_OFFSET; -+ targetAttrib.targetId = (decRegs.sizeReg & MV_SDMMC_WIN_TARGET_MASK) >> -+ MV_SDMMC_WIN_TARGET_OFFSET; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ /* Check if window is enabled */ -+ if(decRegs.sizeReg & MV_SDMMC_WIN_ENABLE_MASK) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ } -+ return MV_OK; -+} -+/******************************************************************************* -+* mvSdmmcAddrDecShow - Print the SDMMC address decode map. -+* -+* DESCRIPTION: -+* This function print the SDMMC address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvSdmmcAddrDecShow(MV_VOID) -+{ -+ -+ MV_SDMMC_DEC_WIN win; -+ int i,j=0; -+ -+ -+ -+ if (MV_FALSE == mvCtrlPwrClckGet(SDIO_UNIT_ID, 0)) -+ return; -+ -+ mvOsOutput( "\n" ); -+ mvOsOutput( "SDMMC %d:\n", j ); -+ mvOsOutput( "----\n" ); -+ -+ for( i = 0; i < MV_SDMMC_MAX_ADDR_DECODE_WIN; i++ ) -+ { -+ memset( &win, 0, sizeof(MV_SDMMC_DEC_WIN) ); -+ -+ mvOsOutput( "win%d - ", i ); -+ -+ if( mvSdmmcWinGet(j, i, &win ) == MV_OK ) -+ { -+ if( win.enable ) -+ { -+ mvOsOutput( "%s base %08x, ", -+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); -+ mvOsOutput( "...." ); -+ -+ mvSizePrint( win.addrWin.size ); -+ -+ mvOsOutput( "\n" ); -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ } -+ } -+} -+ -+ -+/******************************************************************************* -+* mvSdmmcWinInit - Initialize the integrated SDMMC target address window. -+* -+* DESCRIPTION: -+* Initialize the SDMMC peripheral target address window. -+* -+* INPUT: -+* -+* -+* OUTPUT: -+* -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvSdmmcWinInit(MV_VOID) -+{ -+ int winNum; -+ MV_SDMMC_DEC_WIN sdmmcWin; -+ MV_CPU_DEC_WIN cpuAddrDecWin; -+ MV_U32 status, winPrioIndex = 0; -+ -+ /* Initiate Sdmmc address decode */ -+ -+ /* First disable all address decode windows */ -+ for(winNum = 0; winNum < MV_SDMMC_MAX_ADDR_DECODE_WIN; winNum++) -+ { -+ MV_U32 regVal = MV_REG_READ(MV_SDMMC_WIN_CTRL_REG(0, winNum)); -+ regVal &= ~MV_SDMMC_WIN_ENABLE_MASK; -+ MV_REG_WRITE(MV_SDMMC_WIN_CTRL_REG(0, winNum), regVal); -+ } -+ -+ winNum = 0; -+ while( (sdmmcAddrDecPrioTab[winPrioIndex] != TBL_TERM) && -+ (winNum < MV_SDMMC_MAX_ADDR_DECODE_WIN) ) -+ { -+ /* first get attributes from CPU If */ -+ status = mvCpuIfTargetWinGet(sdmmcAddrDecPrioTab[winPrioIndex], -+ &cpuAddrDecWin); -+ -+ if(MV_NO_SUCH == status) -+ { -+ winPrioIndex++; -+ continue; -+ } -+ if (MV_OK != status) -+ { -+ mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ if (cpuAddrDecWin.enable == MV_TRUE) -+ { -+ sdmmcWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; -+ sdmmcWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; -+ sdmmcWin.addrWin.size = cpuAddrDecWin.addrWin.size; -+ sdmmcWin.enable = MV_TRUE; -+ sdmmcWin.target = sdmmcAddrDecPrioTab[winPrioIndex]; -+ -+ if(MV_OK != mvSdmmcWinSet(0/*dev*/, winNum, &sdmmcWin)) -+ { -+ return MV_ERROR; -+ } -+ winNum++; -+ } -+ winPrioIndex++; -+ } -+ return MV_OK; -+} -+ -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,125 @@ -+ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#ifndef __INCMVSysSdmmcAddrDech -+#define __INCMVSysSdmmcAddrDech -+ -+#include "mvCommon.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+ -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+typedef struct _mvSdmmcDecWin -+{ -+ MV_TARGET target; -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+} MV_SDMMC_DEC_WIN; -+ -+ -+#define MV_SDMMC_MAX_ADDR_DECODE_WIN 4 -+ -+#define MV_SDMMC_WIN_CTRL_REG(dev, win) (MV_SDIO_REG_BASE + 0x108 + ((win)<<3)) -+#define MV_SDMMC_WIN_BASE_REG(dev, win) (MV_SDIO_REG_BASE + 0x10c + ((win)<<3)) -+ -+ -+/* BITs in Windows 0-3 Control and Base Registers */ -+#define MV_SDMMC_WIN_ENABLE_BIT 0 -+#define MV_SDMMC_WIN_ENABLE_MASK (1<= TDM_MBUS_MAX_WIN) -+ { -+ mvOsPrintf("mvTdmWinSet: ERR. Invalid win num %d\n",winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlapps with current windows */ -+ if (MV_TRUE == tdmWinOverlapDetect(winNum, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("mvTdmWinSet: ERR. Window %d overlap\n", winNum); -+ return MV_ERROR; -+ } -+ -+ /* check if address is aligned to the size */ -+ if (MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvTdmWinSet: Error setting TDM window %d to "\ -+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, -+ mvCtrlTargetNameGet(pAddrDecWin->target), -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ decRegs.baseReg = MV_REG_READ(TDM_WIN_BASE_REG(winNum)); -+ decRegs.sizeReg = (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_SIZE_MASK) >> TDM_WIN_SIZE_OFFS; -+ -+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) -+ { -+ mvOsPrintf("mvTdmWinSet: mvCtrlAddrDecToReg Failed\n"); -+ return MV_ERROR; -+ } -+ -+ mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); -+ -+ /* for the safe side we disable the window before writing the new -+ values */ -+ mvTdmWinEnable(winNum, MV_FALSE); -+ -+ ctrlReg |= (targetAttribs.attrib << TDM_WIN_ATTRIB_OFFS); -+ ctrlReg |= (targetAttribs.targetId << TDM_WIN_TARGET_OFFS); -+ ctrlReg |= (decRegs.sizeReg & TDM_WIN_SIZE_MASK); -+ -+ /* Write to address base and control registers */ -+ MV_REG_WRITE(TDM_WIN_BASE_REG(winNum), decRegs.baseReg); -+ MV_REG_WRITE(TDM_WIN_CTRL_REG(winNum), ctrlReg); -+ /* Enable address decode target window */ -+ if (pAddrDecWin->enable == MV_TRUE) -+ { -+ mvTdmWinEnable(winNum, MV_TRUE); -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvTdmWinGet - Get peripheral target address window. -+* -+* DESCRIPTION: -+* Get TDM peripheral target address window. -+* -+* INPUT: -+* winNum - TDM to target address decode window number. -+* -+* OUTPUT: -+* pAddrDecWin - TDM target window data structure. -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+ -+MV_STATUS mvTdmWinGet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin) -+{ -+ -+ MV_DEC_REGS decRegs; -+ MV_TARGET_ATTRIB targetAttrib; -+ -+ /* Parameter checking */ -+ if (winNum >= TDM_MBUS_MAX_WIN) -+ { -+ mvOsPrintf("mvTdmWinGet: ERR. Invalid winNum %d\n", winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ decRegs.baseReg = MV_REG_READ(TDM_WIN_BASE_REG(winNum)); -+ decRegs.sizeReg = (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_SIZE_MASK) >> TDM_WIN_SIZE_OFFS; -+ -+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) -+ { -+ mvOsPrintf("mvTdmWinGet: mvCtrlRegToAddrDec Failed \n"); -+ return MV_ERROR; -+ } -+ -+ /* attrib and targetId */ -+ targetAttrib.attrib = -+ (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ATTRIB_MASK) >> TDM_WIN_ATTRIB_OFFS; -+ targetAttrib.targetId = -+ (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_TARGET_MASK) >> TDM_WIN_TARGET_OFFS; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ /* Check if window is enabled */ -+ if (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ENABLE_MASK) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvTdmWinEnable - Enable/disable a TDM to target address window -+* -+* DESCRIPTION: -+* This function enable/disable a TDM to target address window. -+* According to parameter 'enable' the routine will enable the -+* window, thus enabling TDM accesses (before enabling the window it is -+* tested for overlapping). Otherwise, the window will be disabled. -+* -+* INPUT: -+* winNum - TDM to target address decode window number. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_ERROR if decode window number was wrong or enabled window overlapps. -+* -+*******************************************************************************/ -+MV_STATUS mvTdmWinEnable(int winNum, MV_BOOL enable) -+{ -+ MV_TDM_DEC_WIN addrDecWin; -+ -+ if (MV_TRUE == enable) -+ { -+ if (winNum >= TDM_MBUS_MAX_WIN) -+ { -+ mvOsPrintf("mvTdmWinEnable:ERR. Invalid winNum%d\n",winNum); -+ return MV_ERROR; -+ } -+ -+ /* First check for overlap with other enabled windows */ -+ /* Get current window */ -+ if (MV_OK != mvTdmWinGet(winNum, &addrDecWin)) -+ { -+ mvOsPrintf("mvTdmWinEnable:ERR. targetWinGet fail\n"); -+ return MV_ERROR; -+ } -+ /* Check for overlapping */ -+ if (MV_FALSE == tdmWinOverlapDetect(winNum, &(addrDecWin.addrWin))) -+ { -+ /* No Overlap. Enable address decode target window */ -+ MV_REG_BIT_SET(TDM_WIN_CTRL_REG(winNum), TDM_WIN_ENABLE_MASK); -+ } -+ else -+ { /* Overlap detected */ -+ mvOsPrintf("mvTdmWinEnable:ERR. Overlap detected\n"); -+ return MV_ERROR; -+ } -+ } -+ else -+ { -+ MV_REG_BIT_RESET(TDM_WIN_CTRL_REG(winNum), TDM_WIN_ENABLE_MASK); -+ } -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* tdmWinOverlapDetect - Detect TDM address windows overlapping -+* -+* DESCRIPTION: -+* An unpredicted behaviour is expected in case TDM address decode -+* windows overlapps. -+* This function detects TDM address decode windows overlapping of a -+* specified window. The function does not check the window itself for -+* overlapping. The function also skipps disabled address decode windows. -+* -+* INPUT: -+* winNum - address decode window number. -+* pAddrDecWin - An address decode window struct. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data -+* from registers. -+* -+*******************************************************************************/ -+static MV_STATUS tdmWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 winNumIndex; -+ MV_TDM_DEC_WIN addrDecWin; -+ -+ for (winNumIndex = 0; winNumIndex < TDM_MBUS_MAX_WIN; winNumIndex++) -+ { -+ /* Do not check window itself */ -+ if (winNumIndex == winNum) -+ { -+ continue; -+ } -+ /* Do not check disabled windows */ -+ if (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ENABLE_MASK) -+ { -+ /* Get window parameters */ -+ if (MV_OK != mvTdmWinGet(winNumIndex, &addrDecWin)) -+ { -+ DB(mvOsPrintf("dmaWinOverlapDetect: ERR. TargetWinGet failed\n")); -+ return MV_ERROR; -+ } -+ -+ if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin))) -+ { -+ return MV_TRUE; -+ } -+ } -+ } -+ return MV_FALSE; -+} -+ -+/******************************************************************************* -+* mvTdmAddrDecShow - Print the TDM address decode map. -+* -+* DESCRIPTION: -+* This function print the TDM address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvTdmAddrDecShow(MV_VOID) -+{ -+ MV_TDM_DEC_WIN win; -+ int i; -+ -+ mvOsOutput( "\n" ); -+ mvOsOutput( "TDM:\n" ); -+ mvOsOutput( "----\n" ); -+ -+ for( i = 0; i < TDM_MBUS_MAX_WIN; i++ ) -+ { -+ memset( &win, 0, sizeof(MV_TDM_DEC_WIN) ); -+ -+ mvOsOutput( "win%d - ", i ); -+ -+ if (mvTdmWinGet(i, &win ) == MV_OK ) -+ { -+ if( win.enable ) -+ { -+ mvOsOutput( "%s base %08x, ", -+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow); -+ mvOsOutput( "...." ); -+ mvSizePrint( win.addrWin.size ); -+ mvOsOutput( "\n" ); -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ } -+ } -+} -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,106 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvSysTdmh -+#define __INCmvSysTdmh -+ -+#include "ctrlEnv/sys/mvCpuIf.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+ -+typedef struct _mvTdmDecWin -+{ -+ MV_TARGET target; -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+} MV_TDM_DEC_WIN; -+ -+MV_STATUS mvTdmWinInit(MV_VOID); -+MV_STATUS mvTdmWinSet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin); -+MV_STATUS mvTdmWinGet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin); -+MV_STATUS mvTdmWinEnable(int winNum, MV_BOOL enable); -+MV_VOID mvTdmAddrDecShow(MV_VOID); -+ -+ -+#define TDM_MBUS_MAX_WIN 4 -+#define TDM_WIN_CTRL_REG(win) ((TDM_REG_BASE + 0x4030) + (win<<4)) -+#define TDM_WIN_BASE_REG(win) ((TDM_REG_BASE +0x4034) + (win<<4)) -+ -+/* TDM_WIN_CTRL_REG bits */ -+#define TDM_WIN_ENABLE_OFFS 0 -+#define TDM_WIN_ENABLE_MASK (1<= TSU_MAX_DECODE_WIN) -+ { -+ mvOsPrintf("mvTsuWinSet: ERR. Invalid win num %d\n",winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlapps with current windows */ -+ if(MV_TRUE == tsuWinOverlapDetect(winNum, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("mvTsuWinSet: ERR. Window %d overlap\n", winNum); -+ return MV_ERROR; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow,pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvTsuWinSet: Error setting TSU window %d to target " -+ "%s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, mvCtrlTargetNameGet(pAddrDecWin->target), -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ decRegs.baseReg = MV_REG_READ(MV_TSU_WIN_BASE_REG(winNum)); -+ decRegs.sizeReg = MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNum)); -+ -+ if(MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) -+ { -+ mvOsPrintf("mvTsuWinSet: mvCtrlAddrDecToReg Failed\n"); -+ return MV_ERROR; -+ } -+ -+ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); -+ -+ /* set attributes */ -+ decRegs.sizeReg &= ~TSU_WIN_CTRL_ATTR_MASK; -+ decRegs.sizeReg |= targetAttribs.attrib << TSU_WIN_CTRL_ATTR_OFFS; -+ /* set target ID */ -+ decRegs.sizeReg &= ~TSU_WIN_CTRL_TARGET_MASK; -+ decRegs.sizeReg |= targetAttribs.targetId << TSU_WIN_CTRL_TARGET_OFFS; -+ -+ /* for the safe side we disable the window before writing the new */ -+ /* values */ -+ mvTsuWinEnable(winNum, MV_FALSE); -+ MV_REG_WRITE(MV_TSU_WIN_CTRL_REG(winNum),decRegs.sizeReg); -+ -+ /* Write to address decode Size Register */ -+ MV_REG_WRITE(MV_TSU_WIN_BASE_REG(winNum), decRegs.baseReg); -+ -+ /* Enable address decode target window */ -+ if(pAddrDecWin->enable == MV_TRUE) -+ { -+ mvTsuWinEnable(winNum,MV_TRUE); -+ } -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvTsuWinGet -+* -+* DESCRIPTION: -+* Get TSU peripheral target address window. -+* -+* INPUT: -+* winNum - TSU to target address decode window number. -+* -+* OUTPUT: -+* pAddrDecWin - TSU target window data structure. -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvTsuWinGet(MV_U32 winNum, MV_TSU_DEC_WIN *pAddrDecWin) -+{ -+ MV_DEC_REGS decRegs; -+ MV_TARGET_ATTRIB targetAttrib; -+ -+ /* Parameter checking */ -+ if(winNum >= TSU_MAX_DECODE_WIN) -+ { -+ mvOsPrintf("mvTsuWinGet: ERR. Invalid winNum %d\n", winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ decRegs.baseReg = MV_REG_READ(MV_TSU_WIN_BASE_REG(winNum)); -+ decRegs.sizeReg = MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNum)); -+ -+ if(MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) -+ { -+ mvOsPrintf("mvTsuWinGet: mvCtrlRegToAddrDec Failed \n"); -+ return MV_ERROR; -+ } -+ -+ /* attrib and targetId */ -+ targetAttrib.attrib = -+ (decRegs.sizeReg & TSU_WIN_CTRL_ATTR_MASK) >> TSU_WIN_CTRL_ATTR_OFFS; -+ targetAttrib.targetId = -+ (decRegs.sizeReg & TSU_WIN_CTRL_TARGET_MASK) >> TSU_WIN_CTRL_TARGET_OFFS; -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ /* Check if window is enabled */ -+ if((MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNum)) & TSU_WIN_CTRL_EN_MASK)) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ } -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvTsuWinEnable -+* -+* DESCRIPTION: -+* This function enable/disable a TSU to target address window. -+* According to parameter 'enable' the routine will enable the -+* window, thus enabling TSU accesses (before enabling the window it is -+* tested for overlapping). Otherwise, the window will be disabled. -+* -+* INPUT: -+* winNum - TSU to target address decode window number. -+* enable - Enable / disable parameter. -+* -+* OUTPUT: -+* N/A -+* -+* RETURN: -+* MV_ERROR if decode window number was wrong or enabled window overlapps. -+* -+*******************************************************************************/ -+MV_STATUS mvTsuWinEnable(MV_U32 winNum,MV_BOOL enable) -+{ -+ MV_TSU_DEC_WIN addrDecWin; -+ -+ /* Parameter checking */ -+ if(winNum >= TSU_MAX_DECODE_WIN) -+ { -+ mvOsPrintf("mvTsuWinEnable: ERR. Invalid winNum%d\n",winNum); -+ return MV_ERROR; -+ } -+ -+ if(enable == MV_TRUE) -+ { -+ /* First check for overlap with other enabled windows */ -+ /* Get current window. */ -+ if(MV_OK != mvTsuWinGet(winNum,&addrDecWin)) -+ { -+ mvOsPrintf("mvTsuWinEnable: ERR. targetWinGet fail\n"); -+ return MV_ERROR; -+ } -+ /* Check for overlapping. */ -+ if(MV_FALSE == tsuWinOverlapDetect(winNum,&(addrDecWin.addrWin))) -+ { -+ /* No Overlap. Enable address decode target window */ -+ MV_REG_BIT_SET(MV_TSU_WIN_CTRL_REG(winNum), -+ TSU_WIN_CTRL_EN_MASK); -+ } -+ else -+ { -+ /* Overlap detected */ -+ mvOsPrintf("mvTsuWinEnable: ERR. Overlap detected\n"); -+ return MV_ERROR; -+ } -+ } -+ else -+ { -+ /* Disable address decode target window */ -+ MV_REG_BIT_RESET(MV_TSU_WIN_CTRL_REG(winNum), -+ TSU_WIN_CTRL_EN_MASK); -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvTsuWinTargetGet -+* -+* DESCRIPTION: -+* Get Window number associated with target -+* -+* INPUT: -+* target - Target ID to get the window number for. -+* OUTPUT: -+* -+* RETURN: -+* window number or 0xFFFFFFFF on error. -+* -+*******************************************************************************/ -+MV_U32 mvTsuWinTargetGet(MV_TARGET target) -+{ -+ MV_TSU_DEC_WIN decWin; -+ MV_U32 winNum; -+ -+ /* Check parameters */ -+ if(target >= MAX_TARGETS) -+ { -+ mvOsPrintf("mvTsuWinTargetGet: target %d is Illigal\n", target); -+ return 0xffffffff; -+ } -+ -+ for(winNum = 0; winNum < TSU_MAX_DECODE_WIN; winNum++) -+ { -+ if(mvTsuWinGet(winNum,&decWin) != MV_OK) -+ { -+ mvOsPrintf("mvTsuWinGet: window returned error\n"); -+ return 0xffffffff; -+ } -+ -+ if (decWin.enable == MV_TRUE) -+ { -+ if(decWin.target == target) -+ { -+ return winNum; -+ } -+ } -+ } -+ return 0xFFFFFFFF; -+} -+ -+ -+/******************************************************************************* -+* tsuWinOverlapDetect -+* -+* DESCRIPTION: -+* Detect TSU address windows overlapping -+* An unpredicted behaviur is expected in case TSU address decode -+* windows overlapps. -+* This function detects TSU address decode windows overlapping of a -+* specified window. The function does not check the window itself for -+* overlapping. The function also skipps disabled address decode windows. -+* -+* INPUT: -+* winNum - address decode window number. -+* pAddrDecWin - An address decode window struct. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data -+* from registers. -+* -+*******************************************************************************/ -+static MV_STATUS tsuWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 ctrlReg; -+ MV_U32 winNumIndex; -+ MV_TSU_DEC_WIN addrDecWin; -+ -+ for(winNumIndex = 0; winNumIndex < TSU_MAX_DECODE_WIN; winNumIndex++) -+ { -+ /* Do not check window itself */ -+ if(winNumIndex == winNum) -+ { -+ continue; -+ } -+ -+ /* Do not check disabled windows */ -+ ctrlReg = MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNumIndex)); -+ if((ctrlReg & TSU_WIN_CTRL_EN_MASK) == 0) -+ { -+ continue; -+ } -+ -+ /* Get window parameters */ -+ if (MV_OK != mvTsuWinGet(winNumIndex, &addrDecWin)) -+ { -+ mvOsPrintf("tsuWinOverlapDetect: ERR. mvTsuWinGet failed\n"); -+ return MV_ERROR; -+ } -+ -+ if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin))) -+ { -+ return MV_TRUE; -+ } -+ } -+ return MV_FALSE; -+} -+ -+ -+/******************************************************************************* -+* mvTsuAddrDecShow -+* -+* DESCRIPTION: -+* Print the TSU address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+void mvTsuAddrDecShow(void) -+{ -+ MV_TSU_DEC_WIN win; -+ int i; -+ -+ if (MV_FALSE == mvCtrlPwrClckGet(TS_UNIT_ID, 0)) -+ return; -+ -+ mvOsOutput( "\n" ); -+ mvOsOutput( "TSU:\n"); -+ mvOsOutput( "----\n" ); -+ -+ for(i = 0; i < TSU_MAX_DECODE_WIN; i++) -+ { -+ memset(&win, 0, sizeof(TSU_MAX_DECODE_WIN)); -+ mvOsOutput( "win%d - ", i ); -+ -+ if(mvTsuWinGet(i, &win ) == MV_OK ) -+ { -+ if(win.enable == MV_TRUE) -+ { -+ mvOsOutput("%s base %08x, ", -+ mvCtrlTargetNameGet(win.target), -+ win.addrWin.baseLow); -+ mvOsOutput( "...." ); -+ mvSizePrint(win.addrWin.size ); -+ mvOsOutput( "\n" ); -+ } -+ else -+ { -+ mvOsOutput( "disable\n" ); -+ } -+ } -+ } -+ return; -+} -+ -+ -+/******************************************************************************* -+* mvTsuInit -+* -+* DESCRIPTION: -+* Initialize the TSU unit, and get unit out of reset. -+* -+* INPUT: -+* coreClock - The core clock at which the TSU should operate. -+* mode - The mode on configure the unit into (serial/parallel). -+* memHandle - Memory handle used for memory allocations. -+* OUTPUT: -+* None. -+* RETURN: -+* MV_OK - on success, -+* -+*******************************************************************************/ -+MV_STATUS mvTsuInit(MV_TSU_CORE_CLOCK coreClock, MV_TSU_PORTS_MODE mode, -+ void *osHandle) -+{ -+ MV_STATUS status; -+ -+ status = mvTsuWinInit(); -+ if(status == MV_OK) -+ status = mvTsuHalInit(coreClock,mode,osHandle); -+ -+ return status; -+} -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,110 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvSysTsh -+#define __INCmvSysTsh -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* includes */ -+#include "ts/mvTsu.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+ -+#define TSU_MAX_DECODE_WIN 4 -+ -+ -+/*******************************************/ -+/* TSU Windows Registers */ -+/*******************************************/ -+#define MV_TSU_WIN_CTRL_REG(win) (TSU_GLOBAL_REG_BASE +0x30 + 0x10 * win) -+#define MV_TSU_WIN_BASE_REG(win) (TSU_GLOBAL_REG_BASE +0x34 + 0x10 * win) -+ -+/* TSU windows control register. */ -+#define TSU_WIN_CTRL_EN_MASK (0x1 << 0) -+#define TSU_WIN_CTRL_TARGET_OFFS 4 -+#define TSU_WIN_CTRL_TARGET_MASK (0xF << TSU_WIN_CTRL_TARGET_OFFS) -+#define TSU_WIN_CTRL_ATTR_OFFS 8 -+#define TSU_WIN_CTRL_ATTR_MASK (0xFF << TSU_WIN_CTRL_ATTR_OFFS) -+#define TSU_WIN_CTRL_SIZE_OFFS 16 -+#define TSU_WIN_CTRL_SIZE_MASK (0xFFFF << TSU_WIN_CTRL_SIZE_OFFS) -+ -+/* TSU windows base register. */ -+#define TSU_WIN_BASE_OFFS 16 -+#define TSU_WIN_BASE_MASK (0xFFFF << TSU_WIN_BASE_OFFS) -+ -+MV_STATUS mvTsuWinInit(void); -+ -+void mvTsuAddrDecShow(void); -+MV_STATUS mvTsuInit(MV_TSU_CORE_CLOCK coreClock, MV_TSU_PORTS_MODE mode, -+ void *osHandle); -+ -+#ifdef __cplusplus -+} -+#endif /* __cplusplus */ -+ -+#endif /* __INCmvTsh */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,497 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "ctrlEnv/sys/mvSysUsb.h" -+ -+MV_TARGET usbAddrDecPrioTab[] = -+{ -+#if defined(MV_INCLUDE_SDRAM_CS0) -+ SDRAM_CS0, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS1) -+ SDRAM_CS1, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS2) -+ SDRAM_CS2, -+#endif -+#if defined(MV_INCLUDE_SDRAM_CS3) -+ SDRAM_CS3, -+#endif -+#if defined(MV_INCLUDE_CESA) && defined(USB_UNDERRUN_WA) -+ CRYPT_ENG, -+#endif -+#if defined(MV_INCLUDE_PEX) -+ PEX0_MEM, -+#endif -+ TBL_TERM -+}; -+ -+ -+ -+MV_STATUS mvUsbInit(int dev, MV_BOOL isHost) -+{ -+ MV_STATUS status; -+ -+ status = mvUsbWinInit(dev); -+ if(status != MV_OK) -+ return status; -+ -+ return mvUsbHalInit(dev, isHost); -+} -+ -+ -+/******************************************************************************* -+* usbWinOverlapDetect - Detect USB address windows overlapping -+* -+* DESCRIPTION: -+* An unpredicted behaviur is expected in case USB address decode -+* windows overlapps. -+* This function detects USB address decode windows overlapping of a -+* specified window. The function does not check the window itself for -+* overlapping. The function also skipps disabled address decode windows. -+* -+* INPUT: -+* winNum - address decode window number. -+* pAddrDecWin - An address decode window struct. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data -+* from registers. -+* -+*******************************************************************************/ -+static MV_STATUS usbWinOverlapDetect(int dev, MV_U32 winNum, -+ MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 winNumIndex; -+ MV_DEC_WIN addrDecWin; -+ -+ for(winNumIndex=0; winNumIndex= MV_USB_MAX_ADDR_DECODE_WIN) -+ { -+ mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlapps with current windows */ -+ if (MV_TRUE == usbWinOverlapDetect(dev, winNum, &pDecWin->addrWin)) -+ { -+ mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); -+ return MV_ERROR; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pDecWin->addrWin.baseLow, pDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvUsbWinSet:Error setting USB window %d to "\ -+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ winNum, -+ mvCtrlTargetNameGet(pDecWin->target), -+ pDecWin->addrWin.baseLow, -+ pDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ if(MV_OK != mvCtrlAddrDecToParams(pDecWin, &winParams)) -+ { -+ mvOsPrintf("%s: mvCtrlAddrDecToParams Failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ /* set Size, Attributes and TargetID */ -+ sizeReg = (((winParams.targetId << MV_USB_WIN_TARGET_OFFSET) & MV_USB_WIN_TARGET_MASK) | -+ ((winParams.attrib << MV_USB_WIN_ATTR_OFFSET) & MV_USB_WIN_ATTR_MASK) | -+ ((winParams.size << MV_USB_WIN_SIZE_OFFSET) & MV_USB_WIN_SIZE_MASK)); -+ -+#if defined(MV645xx) || defined(MV646xx) -+ /* If window is DRAM with HW cache coherency, make sure bit2 is set */ -+ sizeReg &= ~MV_USB_WIN_BURST_WR_LIMIT_MASK; -+ -+ if((MV_TARGET_IS_DRAM(pDecWin->target)) && -+ (pDecWin->addrWinAttr.cachePolicy != NO_COHERENCY)) -+ { -+ sizeReg |= MV_USB_WIN_BURST_WR_32BIT_LIMIT; -+ } -+ else -+ { -+ sizeReg |= MV_USB_WIN_BURST_WR_NO_LIMIT; -+ } -+#endif /* MV645xx || MV646xx */ -+ -+ if (pDecWin->enable == MV_TRUE) -+ { -+ sizeReg |= MV_USB_WIN_ENABLE_MASK; -+ } -+ else -+ { -+ sizeReg &= ~MV_USB_WIN_ENABLE_MASK; -+ } -+ -+ /* Update Base value */ -+ baseReg = (winParams.baseAddr & MV_USB_WIN_BASE_MASK); -+ -+ MV_REG_WRITE( MV_USB_WIN_CTRL_REG(dev, winNum), sizeReg); -+ MV_REG_WRITE( MV_USB_WIN_BASE_REG(dev, winNum), baseReg); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvUsbWinGet - Get USB peripheral target address window. -+* -+* DESCRIPTION: -+* Get USB peripheral target address window. -+* -+* INPUT: -+* winNum - USB target address decode window number. -+* -+* OUTPUT: -+* pDecWin - USB target window data structure. -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvUsbWinGet(int dev, MV_U32 winNum, MV_DEC_WIN *pDecWin) -+{ -+ MV_DEC_WIN_PARAMS winParam; -+ MV_U32 sizeReg, baseReg; -+ -+ /* Parameter checking */ -+ if (winNum >= MV_USB_MAX_ADDR_DECODE_WIN) -+ { -+ mvOsPrintf("%s (dev=%d): ERR. Invalid winNum %d\n", -+ __FUNCTION__, dev, winNum); -+ return MV_NOT_SUPPORTED; -+ } -+ -+ baseReg = MV_REG_READ( MV_USB_WIN_BASE_REG(dev, winNum) ); -+ sizeReg = MV_REG_READ( MV_USB_WIN_CTRL_REG(dev, winNum) ); -+ -+ /* Check if window is enabled */ -+ if(sizeReg & MV_USB_WIN_ENABLE_MASK) -+ { -+ pDecWin->enable = MV_TRUE; -+ -+ /* Extract window parameters from registers */ -+ winParam.targetId = (sizeReg & MV_USB_WIN_TARGET_MASK) >> MV_USB_WIN_TARGET_OFFSET; -+ winParam.attrib = (sizeReg & MV_USB_WIN_ATTR_MASK) >> MV_USB_WIN_ATTR_OFFSET; -+ winParam.size = (sizeReg & MV_USB_WIN_SIZE_MASK) >> MV_USB_WIN_SIZE_OFFSET; -+ winParam.baseAddr = (baseReg & MV_USB_WIN_BASE_MASK); -+ -+ /* Translate the decode window parameters to address decode struct */ -+ if (MV_OK != mvCtrlParamsToAddrDec(&winParam, pDecWin)) -+ { -+ mvOsPrintf("Failed to translate register parameters to USB address" \ -+ " decode window structure\n"); -+ return MV_ERROR; -+ } -+ } -+ else -+ { -+ pDecWin->enable = MV_FALSE; -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvUsbWinInit - -+* -+* INPUT: -+* -+* OUTPUT: -+* -+* RETURN: -+* MV_ERROR if register parameters are invalid. -+* -+*******************************************************************************/ -+MV_STATUS mvUsbWinInit(int dev) -+{ -+ MV_STATUS status; -+ MV_DEC_WIN usbWin; -+ MV_CPU_DEC_WIN cpuAddrDecWin; -+ int winNum; -+ MV_U32 winPrioIndex = 0; -+ -+ /* First disable all address decode windows */ -+ for(winNum = 0; winNum < MV_USB_MAX_ADDR_DECODE_WIN; winNum++) -+ { -+ MV_REG_BIT_RESET(MV_USB_WIN_CTRL_REG(dev, winNum), MV_USB_WIN_ENABLE_MASK); -+ } -+ -+ /* Go through all windows in user table until table terminator */ -+ winNum = 0; -+ while( (usbAddrDecPrioTab[winPrioIndex] != TBL_TERM) && -+ (winNum < MV_USB_MAX_ADDR_DECODE_WIN) ) -+ { -+ /* first get attributes from CPU If */ -+ status = mvCpuIfTargetWinGet(usbAddrDecPrioTab[winPrioIndex], -+ &cpuAddrDecWin); -+ -+ if(MV_NO_SUCH == status) -+ { -+ winPrioIndex++; -+ continue; -+ } -+ if (MV_OK != status) -+ { -+ mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ if (cpuAddrDecWin.enable == MV_TRUE) -+ { -+ usbWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; -+ usbWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; -+ usbWin.addrWin.size = cpuAddrDecWin.addrWin.size; -+ usbWin.enable = MV_TRUE; -+ usbWin.target = usbAddrDecPrioTab[winPrioIndex]; -+ -+#if defined(MV645xx) || defined(MV646xx) -+ /* Get the default attributes for that target window */ -+ mvCtrlDefAttribGet(usbWin.target, &usbWin.addrWinAttr); -+#endif /* MV645xx || MV646xx */ -+ -+ if(MV_OK != mvUsbWinSet(dev, winNum, &usbWin)) -+ { -+ return MV_ERROR; -+ } -+ winNum++; -+ } -+ winPrioIndex++; -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvUsbAddrDecShow - Print the USB address decode map. -+* -+* DESCRIPTION: -+* This function print the USB address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvUsbAddrDecShow(MV_VOID) -+{ -+ MV_DEC_WIN addrDecWin; -+ int i, winNum; -+ -+ mvOsOutput( "\n" ); -+ mvOsOutput( "USB:\n" ); -+ mvOsOutput( "----\n" ); -+ -+ for(i=0; i= XOR_MAX_ADDR_DEC_WIN) -+ { -+ DB(mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum)); -+ return MV_BAD_PARAM; -+ } -+ if (pAddrDecWin == NULL) -+ { -+ DB(mvOsPrintf("%s: ERR. pAddrDecWin is NULL pointer\n", __FUNCTION__ )); -+ return MV_BAD_PTR; -+ } -+ /* Check if the requested window overlaps with current windows */ -+ if (MV_TRUE == xorWinOverlapDetect(unit, winNum, &pAddrDecWin->addrWin)) -+ { -+ DB(mvOsPrintf("%s: ERR. Window %d overlap\n",__FUNCTION__,winNum)); -+ return MV_ERROR; -+ } -+ -+ xorDecRegs.baseReg = MV_REG_READ(XOR_BASE_ADDR_REG(unit,winNum)); -+ xorDecRegs.sizeReg = MV_REG_READ(XOR_SIZE_MASK_REG(unit,winNum)); -+ -+ /* Get Base Address and size registers values */ -+ if(MV_OK != mvCtrlAddrDecToReg(&pAddrDecWin->addrWin, &xorDecRegs)) -+ { -+ DB(mvOsPrintf("%s: ERR. Invalid addr dec window\n",__FUNCTION__)); -+ return MV_BAD_PARAM; -+ } -+ -+ -+ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); -+ -+ /* set attributes */ -+ xorDecRegs.baseReg &= ~XEBARX_ATTR_MASK; -+ xorDecRegs.baseReg |= targetAttribs.attrib << XEBARX_ATTR_OFFS; -+ /* set target ID */ -+ xorDecRegs.baseReg &= ~XEBARX_TARGET_MASK; -+ xorDecRegs.baseReg |= targetAttribs.targetId << XEBARX_TARGET_OFFS; -+ -+ -+ /* Write to address decode Base Address Register */ -+ MV_REG_WRITE(XOR_BASE_ADDR_REG(unit,winNum), xorDecRegs.baseReg); -+ -+ /* Write to Size Register */ -+ MV_REG_WRITE(XOR_SIZE_MASK_REG(unit,winNum), xorDecRegs.sizeReg); -+ -+ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) -+ { -+ if (pAddrDecWin->enable) -+ { -+ MV_REG_BIT_SET(XOR_WINDOW_CTRL_REG(unit,chan), -+ XEXWCR_WIN_EN_MASK(winNum)); -+ } -+ else -+ { -+ MV_REG_BIT_RESET(XOR_WINDOW_CTRL_REG(unit,chan), -+ XEXWCR_WIN_EN_MASK(winNum)); -+ } -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvXorTargetWinGet - Get xor peripheral target address window. -+* -+* DESCRIPTION: -+* Get xor peripheral target address window. -+* -+* INPUT: -+* winNum - One of the possible XOR memory decode windows. -+* -+* OUTPUT: -+* base - Window base address. -+* size - Window size. -+* enable - window enable/disable. -+* -+* RETURN: -+* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_STATUS mvXorTargetWinGet(MV_U32 unit,MV_U32 winNum, MV_XOR_DEC_WIN *pAddrDecWin) -+{ -+ MV_DEC_REGS xorDecRegs; -+ MV_TARGET_ATTRIB targetAttrib; -+ MV_U32 chan=0,chanWinEn; -+ -+ /* Parameter checking */ -+ if (winNum >= XOR_MAX_ADDR_DEC_WIN) -+ { -+ DB(mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__ , winNum)); -+ return MV_ERROR; -+ } -+ -+ if (NULL == pAddrDecWin) -+ { -+ DB(mvOsPrintf("%s: ERR. pAddrDecWin is NULL pointer\n", __FUNCTION__ )); -+ return MV_BAD_PTR; -+ } -+ -+ chanWinEn = MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,0)) & XEXWCR_WIN_EN_MASK(winNum); -+ -+ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) /* we should scan here all channels per unit */ -+ { -+ /* Check if enable bit is equal for all channels */ -+ if ((MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,chan)) & -+ XEXWCR_WIN_EN_MASK(winNum)) != chanWinEn) -+ { -+ mvOsPrintf("%s: ERR. Window enable field must be equal in " -+ "all channels(chan=%d)\n",__FUNCTION__, chan); -+ return MV_ERROR; -+ } -+ } -+ -+ -+ -+ xorDecRegs.baseReg = MV_REG_READ(XOR_BASE_ADDR_REG(unit,winNum)); -+ xorDecRegs.sizeReg = MV_REG_READ(XOR_SIZE_MASK_REG(unit,winNum)); -+ -+ if (MV_OK != mvCtrlRegToAddrDec(&xorDecRegs, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("%s: ERR. mvCtrlRegToAddrDec failed\n", __FUNCTION__); -+ return MV_ERROR; -+ } -+ -+ /* attrib and targetId */ -+ targetAttrib.attrib = -+ (xorDecRegs.baseReg & XEBARX_ATTR_MASK) >> XEBARX_ATTR_OFFS; -+ targetAttrib.targetId = -+ (xorDecRegs.baseReg & XEBARX_TARGET_MASK) >> XEBARX_TARGET_OFFS; -+ -+ -+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); -+ -+ if(chanWinEn) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else pAddrDecWin->enable = MV_FALSE; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvXorTargetWinEnable - Enable/disable a Xor address decode window -+* -+* DESCRIPTION: -+* This function enable/disable a XOR address decode window. -+* if parameter 'enable' == MV_TRUE the routine will enable the -+* window, thus enabling XOR accesses (before enabling the window it is -+* tested for overlapping). Otherwise, the window will be disabled. -+* -+* INPUT: -+* winNum - Decode window number. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_STATUS mvXorTargetWinEnable(MV_U32 unit,MV_U32 winNum, MV_BOOL enable) -+{ -+ MV_XOR_DEC_WIN addrDecWin; -+ MV_U32 chan; -+ -+ /* Parameter checking */ -+ if (winNum >= XOR_MAX_ADDR_DEC_WIN) -+ { -+ DB(mvOsPrintf("%s: ERR. Invalid winNum%d\n", __FUNCTION__, winNum)); -+ return MV_ERROR; -+ } -+ -+ if (enable == MV_TRUE) -+ { -+ /* Get current window */ -+ if (MV_OK != mvXorTargetWinGet(unit,winNum, &addrDecWin)) -+ { -+ DB(mvOsPrintf("%s: ERR. targetWinGet fail\n", __FUNCTION__)); -+ return MV_ERROR; -+ } -+ -+ /* Check for overlapping */ -+ if (MV_TRUE == xorWinOverlapDetect(unit,winNum, &(addrDecWin.addrWin))) -+ { -+ /* Overlap detected */ -+ DB(mvOsPrintf("%s: ERR. Overlap detected\n", __FUNCTION__)); -+ return MV_ERROR; -+ } -+ -+ /* No Overlap. Enable address decode target window */ -+ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) -+ { -+ MV_REG_BIT_SET(XOR_WINDOW_CTRL_REG(unit,chan), -+ XEXWCR_WIN_EN_MASK(winNum)); -+ } -+ -+ } -+ else -+ { -+ /* Disable address decode target window */ -+ -+ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) -+ { -+ MV_REG_BIT_RESET(XOR_WINDOW_CTRL_REG(unit,chan), -+ XEXWCR_WIN_EN_MASK(winNum)); -+ } -+ -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvXorSetProtWinSet - Configure access attributes of a XOR engine -+* to one of the XOR memory windows. -+* -+* DESCRIPTION: -+* Each engine can be configured with access attributes for each of the -+* memory spaces. This function sets access attributes -+* to a given window for the given engine -+* -+* INPUTS: -+* chan - One of the possible engines. -+* winNum - One of the possible XOR memory spaces. -+* access - Protection access rights. -+* write - Write rights. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_STATUS mvXorProtWinSet (MV_U32 unit,MV_U32 chan, MV_U32 winNum, MV_BOOL access, -+ MV_BOOL write) -+{ -+ MV_U32 temp; -+ -+ /* Parameter checking */ -+ if (chan >= MV_XOR_MAX_CHAN_PER_UNIT) -+ { -+ DB(mvOsPrintf("%s: ERR. Invalid chan num %d\n", __FUNCTION__ , chan)); -+ return MV_BAD_PARAM; -+ } -+ if (winNum >= XOR_MAX_ADDR_DEC_WIN) -+ { -+ DB(mvOsPrintf("%s: ERR. Invalid win num %d\n", __FUNCTION__, winNum)); -+ return MV_BAD_PARAM; -+ } -+ -+ temp = MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,chan)) & -+ (~XEXWCR_WIN_ACC_MASK(winNum)); -+ -+ /* if access is disable */ -+ if (!access) -+ { -+ /* disable access */ -+ temp |= XEXWCR_WIN_ACC_NO_ACC(winNum); -+ } -+ /* if access is enable */ -+ else -+ { -+ /* if write is enable */ -+ if (write) -+ { -+ /* enable write */ -+ temp |= XEXWCR_WIN_ACC_RW(winNum); -+ } -+ /* if write is disable */ -+ else -+ { -+ /* disable write */ -+ temp |= XEXWCR_WIN_ACC_RO(winNum); -+ } -+ } -+ MV_REG_WRITE(XOR_WINDOW_CTRL_REG(unit,chan),temp); -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvXorPciRemap - Set XOR remap register for PCI address windows. -+* -+* DESCRIPTION: -+* only Windows 0-3 can be remapped. -+* -+* INPUT: -+* winNum - window number -+* pAddrDecWin - pointer to address space window structure -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_STATUS mvXorPciRemap(MV_U32 unit,MV_U32 winNum, MV_U32 addrHigh) -+{ -+ /* Parameter checking */ -+ if (winNum >= XOR_MAX_REMAP_WIN) -+ { -+ DB(mvOsPrintf("%s: ERR. Invalid win num %d\n", __FUNCTION__, winNum)); -+ return MV_BAD_PARAM; -+ } -+ -+ MV_REG_WRITE(XOR_HIGH_ADDR_REMAP_REG(unit,winNum), addrHigh); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* xorWinOverlapDetect - Detect XOR address windows overlaping -+* -+* DESCRIPTION: -+* An unpredicted behaviour is expected in case XOR address decode -+* windows overlaps. -+* This function detects XOR address decode windows overlaping of a -+* specified window. The function does not check the window itself for -+* overlaping. The function also skipps disabled address decode windows. -+* -+* INPUT: -+* winNum - address decode window number. -+* pAddrDecWin - An address decode window struct. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlap current address -+* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data -+* from registers. -+* -+*******************************************************************************/ -+static MV_STATUS xorWinOverlapDetect(MV_U32 unit,MV_U32 winNum, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_U32 baseAddrEnableReg; -+ MV_U32 winNumIndex,chan; -+ MV_XOR_DEC_WIN addrDecWin; -+ -+ if (pAddrWin == NULL) -+ { -+ DB(mvOsPrintf("%s: ERR. pAddrWin is NULL pointer\n", __FUNCTION__ )); -+ return MV_BAD_PTR; -+ } -+ -+ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) -+ { -+ /* Read base address enable register. Do not check disabled windows */ -+ baseAddrEnableReg = MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,chan)); -+ -+ for (winNumIndex = 0; winNumIndex < XOR_MAX_ADDR_DEC_WIN; winNumIndex++) -+ { -+ /* Do not check window itself */ -+ if (winNumIndex == winNum) -+ { -+ continue; -+ } -+ -+ /* Do not check disabled windows */ -+ if ((baseAddrEnableReg & XEXWCR_WIN_EN_MASK(winNumIndex)) == 0) -+ { -+ continue; -+ } -+ -+ /* Get window parameters */ -+ if (MV_OK != mvXorTargetWinGet(unit,winNumIndex, &addrDecWin)) -+ { -+ DB(mvOsPrintf("%s: ERR. TargetWinGet failed\n", __FUNCTION__ )); -+ return MV_ERROR; -+ } -+ -+ if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin))) -+ { -+ return MV_TRUE; -+ } -+ } -+ } -+ -+ return MV_FALSE; -+} -+ -+static MV_VOID mvXorAddrDecShowUnit(MV_U32 unit) -+{ -+ MV_XOR_DEC_WIN win; -+ int i; -+ -+ mvOsOutput( "\n" ); -+ mvOsOutput( "XOR %d:\n", unit ); -+ mvOsOutput( "----\n" ); -+ -+ for( i = 0; i < XOR_MAX_ADDR_DEC_WIN; i++ ) -+ { -+ memset( &win, 0, sizeof(MV_XOR_DEC_WIN) ); -+ -+ mvOsOutput( "win%d - ", i ); -+ -+ if( mvXorTargetWinGet(unit, i, &win ) == MV_OK ) -+ { -+ if( win.enable ) -+ { -+ mvOsOutput( "%s base %x, ", -+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); -+ -+ mvSizePrint( win.addrWin.size ); -+ -+ mvOsOutput( "\n" ); -+ } -+ else -+ mvOsOutput( "disable\n" ); -+ } -+ } -+} -+ -+/******************************************************************************* -+* mvXorAddrDecShow - Print the XOR address decode map. -+* -+* DESCRIPTION: -+* This function print the XOR address decode map. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID mvXorAddrDecShow(MV_VOID) -+{ -+ int i; -+ -+ for( i = 0; i < MV_XOR_MAX_UNIT; i++ ) -+ mvXorAddrDecShowUnit(i); -+ -+} -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,140 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCMVSysXorh -+#define __INCMVSysXorh -+ -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+#include "ctrlEnv/sys/mvCpuIf.h" -+ -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+ -+#define XOR_MAX_ADDR_DEC_WIN 8 /* Maximum address decode windows */ -+#define XOR_MAX_REMAP_WIN 4 /* Maximum address arbiter windows */ -+ -+/* XOR Engine Address Decoding Register Map */ -+#define XOR_WINDOW_CTRL_REG(unit,chan) (XOR_UNIT_BASE(unit)+(0x240 + ((chan) * 4))) -+#define XOR_BASE_ADDR_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x250 + ((winNum) * 4))) -+#define XOR_SIZE_MASK_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x270 + ((winNum) * 4))) -+#define XOR_HIGH_ADDR_REMAP_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x290 + ((winNum) * 4))) -+ -+/* XOR Engine [0..1] Window Control Registers (XExWCR) */ -+#define XEXWCR_WIN_EN_OFFS(winNum) (winNum) -+#define XEXWCR_WIN_EN_MASK(winNum) (1 << (XEXWCR_WIN_EN_OFFS(winNum))) -+#define XEXWCR_WIN_EN_ENABLE(winNum) (1 << (XEXWCR_WIN_EN_OFFS(winNum))) -+#define XEXWCR_WIN_EN_DISABLE(winNum) (0 << (XEXWCR_WIN_EN_OFFS(winNum))) -+ -+#define XEXWCR_WIN_ACC_OFFS(winNum) ((2 * winNum) + 16) -+#define XEXWCR_WIN_ACC_MASK(winNum) (3 << (XEXWCR_WIN_ACC_OFFS(winNum))) -+#define XEXWCR_WIN_ACC_NO_ACC(winNum) (0 << (XEXWCR_WIN_ACC_OFFS(winNum))) -+#define XEXWCR_WIN_ACC_RO(winNum) (1 << (XEXWCR_WIN_ACC_OFFS(winNum))) -+#define XEXWCR_WIN_ACC_RW(winNum) (3 << (XEXWCR_WIN_ACC_OFFS(winNum))) -+ -+/* XOR Engine Base Address Registers (XEBARx) */ -+#define XEBARX_TARGET_OFFS (0) -+#define XEBARX_TARGET_MASK (0xF << XEBARX_TARGET_OFFS) -+#define XEBARX_ATTR_OFFS (8) -+#define XEBARX_ATTR_MASK (0xFF << XEBARX_ATTR_OFFS) -+#define XEBARX_BASE_OFFS (16) -+#define XEBARX_BASE_MASK (0xFFFF << XEBARX_BASE_OFFS) -+ -+/* XOR Engine Size Mask Registers (XESMRx) */ -+#define XESMRX_SIZE_MASK_OFFS (16) -+#define XESMRX_SIZE_MASK_MASK (0xFFFF << XESMRX_SIZE_MASK_OFFS) -+ -+/* XOR Engine High Address Remap Register (XEHARRx1) */ -+#define XEHARRX_REMAP_OFFS (0) -+#define XEHARRX_REMAP_MASK (0xFFFFFFFF << XEHARRX_REMAP_OFFS) -+ -+typedef struct _mvXorDecWin -+{ -+ MV_TARGET target; -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+ -+}MV_XOR_DEC_WIN; -+ -+MV_STATUS mvXorInit (MV_VOID); -+MV_STATUS mvXorTargetWinSet(MV_U32 unit, MV_U32 winNum, -+ MV_XOR_DEC_WIN *pAddrDecWin); -+MV_STATUS mvXorTargetWinGet(MV_U32 unit, MV_U32 winNum, -+ MV_XOR_DEC_WIN *pAddrDecWin); -+MV_STATUS mvXorTargetWinEnable(MV_U32 unit, -+ MV_U32 winNum, MV_BOOL enable); -+MV_STATUS mvXorProtWinSet (MV_U32 unit,MV_U32 chan, MV_U32 winNum, MV_BOOL access, -+ MV_BOOL write); -+MV_STATUS mvXorPciRemap(MV_U32 unit, MV_U32 winNum, MV_U32 addrHigh); -+ -+MV_VOID mvXorAddrDecShow(MV_VOID); -+ -+#ifdef __cplusplus -+} -+#endif -+ -+#endif -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,75 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "device/mvDevice.h" -+ -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,74 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvDeviceH -+#define __INCmvDeviceH -+ -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+#include "device/mvDeviceRegs.h" -+ -+ -+#endif /* #ifndef __INCmvDeviceH */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDeviceRegs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDeviceRegs.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDeviceRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDeviceRegs.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,101 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvDeviceRegsH -+#define __INCmvDeviceRegsH -+ -+#ifndef MV_ASMLANGUAGE -+#include "ctrlEnv/mvCtrlEnvLib.h" -+/* This enumerator describes the Marvell controller possible devices that */ -+/* can be connected to its device interface. */ -+typedef enum _mvDevice -+{ -+#if defined(MV_INCLUDE_DEVICE_CS0) -+ DEV_CS0 = 0, /* Device connected to dev CS[0] */ -+#endif -+#if defined(MV_INCLUDE_DEVICE_CS1) -+ DEV_CS1 = 1, /* Device connected to dev CS[1] */ -+#endif -+#if defined(MV_INCLUDE_DEVICE_CS2) -+ DEV_CS2 = 2, /* Device connected to dev CS[2] */ -+#endif -+#if defined(MV_INCLUDE_DEVICE_CS3) -+ DEV_CS3 = 3, /* Device connected to dev CS[2] */ -+#endif -+#if defined(MV_INCLUDE_DEVICE_CS4) -+ DEV_CS4 = 4, /* Device connected to BOOT dev */ -+#endif -+ MV_DEV_MAX_CS = MV_DEVICE_MAX_CS -+}MV_DEVICE; -+ -+ -+#endif /* MV_ASMLANGUAGE */ -+ -+ -+#define NAND_CTRL_REG 0x10470 -+ -+#define NAND_ACTCEBOOT_BIT BIT1 -+ -+ -+#endif /* #ifndef __INCmvDeviceRegsH */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/mvCompVer.txt linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/mvCompVer.txt ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/mvCompVer.txt 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/mvCompVer.txt 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,4 @@ -+Global HAL Version: FEROCEON_HAL_3_1_7 -+Unit HAL Version: 3.1.5 -+Description: This component includes an implementation of the unit HAL drivers -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,211 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+*******************************************************************************/ -+/******************************************************************************* -+* mvOsCpuArchLib.c - Marvell CPU architecture library -+* -+* DESCRIPTION: -+* This library introduce Marvell API for OS dependent CPU architecture -+* APIs. This library introduce single CPU architecture services APKI -+* cross OS. -+* -+* DEPENDENCIES: -+* None. -+* -+*******************************************************************************/ -+ -+/* includes */ -+#include -+#include "mvOs.h" -+ -+static MV_U32 read_p15_c0 (void); -+ -+/* defines */ -+#define ARM_ID_REVISION_OFFS 0 -+#define ARM_ID_REVISION_MASK (0xf << ARM_ID_REVISION_OFFS) -+ -+#define ARM_ID_PART_NUM_OFFS 4 -+#define ARM_ID_PART_NUM_MASK (0xfff << ARM_ID_PART_NUM_OFFS) -+ -+#define ARM_ID_ARCH_OFFS 16 -+#define ARM_ID_ARCH_MASK (0xf << ARM_ID_ARCH_OFFS) -+ -+#define ARM_ID_VAR_OFFS 20 -+#define ARM_ID_VAR_MASK (0xf << ARM_ID_VAR_OFFS) -+ -+#define ARM_ID_ASCII_OFFS 24 -+#define ARM_ID_ASCII_MASK (0xff << ARM_ID_ASCII_OFFS) -+ -+ -+ -+void* mvOsIoCachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, -+ MV_U32 *memHandle) -+{ -+ void *p = kmalloc( size, GFP_KERNEL ); -+ *pPhyAddr = pci_map_single( osHandle, p, 0, PCI_DMA_BIDIRECTIONAL ); -+ return p; -+} -+void* mvOsIoUncachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, -+ MV_U32 *memHandle) -+{ -+ return pci_alloc_consistent( osHandle, size, (dma_addr_t *)pPhyAddr ); -+} -+ -+void mvOsIoUncachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, -+ MV_U32 memHandle) -+{ -+ return pci_free_consistent( osHandle, size, pVirtAddr, (dma_addr_t)phyAddr ); -+} -+ -+void mvOsIoCachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, -+ MV_U32 memHandle ) -+{ -+ return kfree( pVirtAddr ); -+} -+ -+int mvOsRand(void) -+{ -+ int rand; -+ get_random_bytes(&rand, sizeof(rand) ); -+ return rand; -+} -+ -+/******************************************************************************* -+* mvOsCpuVerGet() - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit CPU Revision -+* -+*******************************************************************************/ -+MV_U32 mvOsCpuRevGet( MV_VOID ) -+{ -+ return ((read_p15_c0() & ARM_ID_REVISION_MASK ) >> ARM_ID_REVISION_OFFS); -+} -+/******************************************************************************* -+* mvOsCpuPartGet() - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit CPU Part number -+* -+*******************************************************************************/ -+MV_U32 mvOsCpuPartGet( MV_VOID ) -+{ -+ return ((read_p15_c0() & ARM_ID_PART_NUM_MASK ) >> ARM_ID_PART_NUM_OFFS); -+} -+/******************************************************************************* -+* mvOsCpuArchGet() - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit CPU Architicture number -+* -+*******************************************************************************/ -+MV_U32 mvOsCpuArchGet( MV_VOID ) -+{ -+ return ((read_p15_c0() & ARM_ID_ARCH_MASK ) >> ARM_ID_ARCH_OFFS); -+} -+/******************************************************************************* -+* mvOsCpuVarGet() - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit CPU Variant number -+* -+*******************************************************************************/ -+MV_U32 mvOsCpuVarGet( MV_VOID ) -+{ -+ return ((read_p15_c0() & ARM_ID_VAR_MASK ) >> ARM_ID_VAR_OFFS); -+} -+/******************************************************************************* -+* mvOsCpuAsciiGet() - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit CPU Variant number -+* -+*******************************************************************************/ -+MV_U32 mvOsCpuAsciiGet( MV_VOID ) -+{ -+ return ((read_p15_c0() & ARM_ID_ASCII_MASK ) >> ARM_ID_ASCII_OFFS); -+} -+ -+ -+ -+/* -+static unsigned long read_p15_c0 (void) -+*/ -+/* read co-processor 15, register #0 (ID register) */ -+static MV_U32 read_p15_c0 (void) -+{ -+ MV_U32 value; -+ -+ __asm__ __volatile__( -+ "mrc p15, 0, %0, c0, c0, 0 @ read control reg\n" -+ : "=r" (value) -+ : -+ : "memory"); -+ -+ return value; -+} -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,423 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+*******************************************************************************/ -+#ifndef _MV_OS_LNX_H_ -+#define _MV_OS_LNX_H_ -+ -+ -+#ifdef __KERNEL__ -+/* for kernel space */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "dbg-trace.h" -+ -+extern void mv_early_printk(char *fmt,...); -+ -+#define MV_ASM __asm__ __volatile__ -+#define INLINE inline -+#define MV_TRC_REC TRC_REC -+#define mvOsPrintf printk -+#define mvOsEarlyPrintf mv_early_printk -+#define mvOsOutput printk -+#define mvOsSPrintf sprintf -+#define mvOsMalloc(_size_) kmalloc(_size_,GFP_ATOMIC) -+#define mvOsFree kfree -+#define mvOsMemcpy memcpy -+#define mvOsSleep(_mils_) mdelay(_mils_) -+#define mvOsTaskLock() -+#define mvOsTaskUnlock() -+#define strtol simple_strtoul -+#define mvOsDelay(x) mdelay(x) -+#define mvOsUDelay(x) udelay(x) -+#define mvCopyFromOs copy_from_user -+#define mvCopyToOs copy_to_user -+ -+ -+#include "mvTypes.h" -+#include "mvCommon.h" -+ -+#ifdef MV_NDEBUG -+#define mvOsAssert(cond) -+#else -+#define mvOsAssert(cond) { do { if(!(cond)) { BUG(); } }while(0); } -+#endif /* MV_NDEBUG */ -+ -+#else /* __KERNEL__ */ -+ -+/* for user space applications */ -+#include -+#include -+#include -+#include -+ -+#define INLINE inline -+#define mvOsPrintf printf -+#define mvOsOutput printf -+#define mvOsMalloc(_size_) malloc(_size_) -+#define mvOsFree free -+#define mvOsAssert(cond) assert(cond) -+ -+#endif /* __KERNEL__ */ -+#define mvOsIoVirtToPhy(pDev, pVirtAddr) \ -+ pci_map_single( (pDev), (pVirtAddr), 0, PCI_DMA_BIDIRECTIONAL ) -+ -+#define mvOsCacheClear(pDev, p, size ) \ -+ pci_map_single( (pDev), (p), (size), PCI_DMA_BIDIRECTIONAL) -+ -+#define mvOsCacheFlush(pDev, p, size ) \ -+ pci_map_single( (pDev), (p), (size), PCI_DMA_TODEVICE) -+ -+#define mvOsCacheInvalidate(pDev, p, size) \ -+ pci_map_single( (pDev), (p), (size), PCI_DMA_FROMDEVICE ) -+ -+#define mvOsCacheUnmap(pDev, phys, size) \ -+ pci_unmap_single( (pDev), (dma_addr_t)(phys), (size), PCI_DMA_FROMDEVICE ) -+ -+ -+#define CPU_PHY_MEM(x) (MV_U32)x -+#define CPU_MEMIO_CACHED_ADDR(x) (void*)x -+#define CPU_MEMIO_UNCACHED_ADDR(x) (void*)x -+ -+ -+/* CPU architecture dependent 32, 16, 8 bit read/write IO addresses */ -+#define MV_MEMIO32_WRITE(addr, data) \ -+ ((*((volatile unsigned int*)(addr))) = ((unsigned int)(data))) -+ -+#define MV_MEMIO32_READ(addr) \ -+ ((*((volatile unsigned int*)(addr)))) -+ -+#define MV_MEMIO16_WRITE(addr, data) \ -+ ((*((volatile unsigned short*)(addr))) = ((unsigned short)(data))) -+ -+#define MV_MEMIO16_READ(addr) \ -+ ((*((volatile unsigned short*)(addr)))) -+ -+#define MV_MEMIO8_WRITE(addr, data) \ -+ ((*((volatile unsigned char*)(addr))) = ((unsigned char)(data))) -+ -+#define MV_MEMIO8_READ(addr) \ -+ ((*((volatile unsigned char*)(addr)))) -+ -+ -+/* No Fast Swap implementation (in assembler) for ARM */ -+#define MV_32BIT_LE_FAST(val) MV_32BIT_LE(val) -+#define MV_16BIT_LE_FAST(val) MV_16BIT_LE(val) -+#define MV_32BIT_BE_FAST(val) MV_32BIT_BE(val) -+#define MV_16BIT_BE_FAST(val) MV_16BIT_BE(val) -+ -+/* 32 and 16 bit read/write in big/little endian mode */ -+ -+/* 16bit write in little endian mode */ -+#define MV_MEMIO_LE16_WRITE(addr, data) \ -+ MV_MEMIO16_WRITE(addr, MV_16BIT_LE_FAST(data)) -+ -+/* 16bit read in little endian mode */ -+static __inline MV_U16 MV_MEMIO_LE16_READ(MV_U32 addr) -+{ -+ MV_U16 data; -+ -+ data= (MV_U16)MV_MEMIO16_READ(addr); -+ -+ return (MV_U16)MV_16BIT_LE_FAST(data); -+} -+ -+/* 32bit write in little endian mode */ -+#define MV_MEMIO_LE32_WRITE(addr, data) \ -+ MV_MEMIO32_WRITE(addr, MV_32BIT_LE_FAST(data)) -+ -+/* 32bit read in little endian mode */ -+static __inline MV_U32 MV_MEMIO_LE32_READ(MV_U32 addr) -+{ -+ MV_U32 data; -+ -+ data= (MV_U32)MV_MEMIO32_READ(addr); -+ -+ return (MV_U32)MV_32BIT_LE_FAST(data); -+} -+ -+static __inline void mvOsBCopy(char* srcAddr, char* dstAddr, int byteCount) -+{ -+ while(byteCount != 0) -+ { -+ *dstAddr = *srcAddr; -+ dstAddr++; -+ srcAddr++; -+ byteCount--; -+ } -+} -+ -+static INLINE MV_U64 mvOsDivMod64(MV_U64 divided, MV_U64 divisor, MV_U64* modulu) -+{ -+ MV_U64 division = 0; -+ -+ if(divisor == 1) -+ return divided; -+ -+ while(divided >= divisor) -+ { -+ division++; -+ divided -= divisor; -+ } -+ if (modulu != NULL) -+ *modulu = divided; -+ -+ return division; -+} -+ -+#if defined(MV_BRIDGE_SYNC_REORDER) -+extern MV_U32 *mvUncachedParam; -+ -+static __inline void mvOsBridgeReorderWA(void) -+{ -+ volatile MV_U32 val = 0; -+ -+ val = mvUncachedParam[0]; -+} -+#endif -+ -+ -+/* Flash APIs */ -+#define MV_FL_8_READ MV_MEMIO8_READ -+#define MV_FL_16_READ MV_MEMIO_LE16_READ -+#define MV_FL_32_READ MV_MEMIO_LE32_READ -+#define MV_FL_8_DATA_READ MV_MEMIO8_READ -+#define MV_FL_16_DATA_READ MV_MEMIO16_READ -+#define MV_FL_32_DATA_READ MV_MEMIO32_READ -+#define MV_FL_8_WRITE MV_MEMIO8_WRITE -+#define MV_FL_16_WRITE MV_MEMIO_LE16_WRITE -+#define MV_FL_32_WRITE MV_MEMIO_LE32_WRITE -+#define MV_FL_8_DATA_WRITE MV_MEMIO8_WRITE -+#define MV_FL_16_DATA_WRITE MV_MEMIO16_WRITE -+#define MV_FL_32_DATA_WRITE MV_MEMIO32_WRITE -+ -+ -+/* CPU cache information */ -+#define CPU_I_CACHE_LINE_SIZE 32 /* 2do: replace 32 with linux core macro */ -+#define CPU_D_CACHE_LINE_SIZE 32 /* 2do: replace 32 with linux core macro */ -+ -+#ifdef CONFIG_L2_CACHE_ENABLE -+/* Data cache flush one line */ -+#define mvOsCacheLineFlushInv(handle, addr) \ -+{ \ -+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c14, 1" : : "r" (addr));\ -+ __asm__ __volatile__ ("mcr p15, 1, %0, c15, c10, 1" : : "r" (addr));\ -+ __asm__ __volatile__ ("mcr p15, 0, r0, c7, c10, 4"); \ -+} -+ -+#else -+ -+/* Data cache flush one line */ -+#define mvOsCacheLineFlushInv(handle, addr) \ -+{ \ -+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c14, 1" : : "r" (addr));\ -+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" : : "r" (addr)); \ -+} -+#endif -+ -+#ifdef CONFIG_L2_CACHE_ENABLE -+#define mvOsCacheLineInv(handle,addr) \ -+{ \ -+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c6, 1" : : "r" (addr)); \ -+ __asm__ __volatile__ ("mcr p15, 1, %0, c15, c11, 1" : : "r" (addr)); \ -+} -+#else -+#define mvOsCacheLineInv(handle,addr) \ -+{ \ -+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c6, 1" : : "r" (addr)); \ -+} -+#endif -+ -+#ifdef CONFIG_L2_CACHE_ENABLE -+/* Data cache flush one line */ -+#define mvOsCacheLineFlush(handle, addr) \ -+{ \ -+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 1" : : "r" (addr));\ -+ __asm__ __volatile__ ("mcr p15, 1, %0, c15, c9, 1" : : "r" (addr));\ -+ __asm__ __volatile__ ("mcr p15, 0, r0, c7, c10, 4"); \ -+} -+ -+#else -+/* Data cache flush one line */ -+#define mvOsCacheLineFlush(handle, addr) \ -+{ \ -+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 1" : : "r" (addr));\ -+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" : : "r" (addr)); \ -+} -+#endif -+ -+static __inline void mvOsPrefetch(const void *ptr) -+{ -+#ifdef CONFIG_USE_DSP -+ __asm__ __volatile__( -+ "pld\t%0" -+ : -+ : "o" (*(char *)ptr) -+ : "cc"); -+#else -+ return; -+#endif -+} -+ -+ -+/* Flush CPU pipe */ -+#define CPU_PIPE_FLUSH -+ -+ -+ -+ -+ -+/* register manipulations */ -+ -+/****************************************************************************** -+* This debug function enable the write of each register that u-boot access to -+* to an array in the DRAM, the function record only MV_REG_WRITE access. -+* The function could not be operate when booting from flash. -+* In order to print the array we use the printreg command. -+******************************************************************************/ -+/* #define REG_DEBUG */ -+#if defined(REG_DEBUG) -+extern int reg_arry[2048][2]; -+extern int reg_arry_index; -+#endif -+ -+/* Marvell controller register read/write macros */ -+#define MV_REG_VALUE(offset) \ -+ (MV_MEMIO32_READ((INTER_REGS_BASE | (offset)))) -+ -+#define MV_REG_READ(offset) \ -+ (MV_MEMIO_LE32_READ(INTER_REGS_BASE | (offset))) -+ -+#if defined(REG_DEBUG) -+#define MV_REG_WRITE(offset, val) \ -+ MV_MEMIO_LE32_WRITE((INTER_REGS_BASE | (offset)), (val)); \ -+ { \ -+ reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\ -+ reg_arry[reg_arry_index][1] = (val);\ -+ reg_arry_index++;\ -+ } -+#else -+#define MV_REG_WRITE(offset, val) \ -+ MV_MEMIO_LE32_WRITE((INTER_REGS_BASE | (offset)), (val)); -+#endif -+ -+#define MV_REG_BYTE_READ(offset) \ -+ (MV_MEMIO8_READ((INTER_REGS_BASE | (offset)))) -+ -+#if defined(REG_DEBUG) -+#define MV_REG_BYTE_WRITE(offset, val) \ -+ MV_MEMIO8_WRITE((INTER_REGS_BASE | (offset)), (val)); \ -+ { \ -+ reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\ -+ reg_arry[reg_arry_index][1] = (val);\ -+ reg_arry_index++;\ -+ } -+#else -+#define MV_REG_BYTE_WRITE(offset, val) \ -+ MV_MEMIO8_WRITE((INTER_REGS_BASE | (offset)), (val)) -+#endif -+ -+#if defined(REG_DEBUG) -+#define MV_REG_BIT_SET(offset, bitMask) \ -+ (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ -+ (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) | \ -+ MV_32BIT_LE_FAST(bitMask)))); \ -+ { \ -+ reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\ -+ reg_arry[reg_arry_index][1] = (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)));\ -+ reg_arry_index++;\ -+ } -+#else -+#define MV_REG_BIT_SET(offset, bitMask) \ -+ (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ -+ (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) | \ -+ MV_32BIT_LE_FAST(bitMask)))) -+#endif -+ -+#if defined(REG_DEBUG) -+#define MV_REG_BIT_RESET(offset,bitMask) \ -+ (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ -+ (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) & \ -+ MV_32BIT_LE_FAST(~bitMask)))); \ -+ { \ -+ reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\ -+ reg_arry[reg_arry_index][1] = (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)));\ -+ reg_arry_index++;\ -+ } -+#else -+#define MV_REG_BIT_RESET(offset,bitMask) \ -+ (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ -+ (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) & \ -+ MV_32BIT_LE_FAST(~bitMask)))) -+#endif -+ -+ -+ -+/* ARM architecture APIs */ -+MV_U32 mvOsCpuRevGet (MV_VOID); -+MV_U32 mvOsCpuPartGet (MV_VOID); -+MV_U32 mvOsCpuArchGet (MV_VOID); -+MV_U32 mvOsCpuVarGet (MV_VOID); -+MV_U32 mvOsCpuAsciiGet (MV_VOID); -+ -+/* Other APIs */ -+void* mvOsIoCachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, MV_U32 *memHandle); -+void* mvOsIoUncachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, MV_U32 *memHandle ); -+void mvOsIoUncachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, MV_U32 memHandle ); -+void mvOsIoCachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, MV_U32 memHandle ); -+int mvOsRand(void); -+ -+#endif /* _MV_OS_LNX_H_ */ -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOsSata.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/linux_oss/mvOsSata.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOsSata.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/linux_oss/mvOsSata.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,158 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+*******************************************************************************/ -+/******************************************************************************* -+* mvOsLinux.h - O.S. interface header file for Linux -+* -+* DESCRIPTION: -+* This header file contains OS dependent definition under Linux -+* -+* DEPENDENCIES: -+* Linux kernel header files. -+* -+* FILE REVISION NUMBER: -+* $Revision: 1.1 $ -+*******************************************************************************/ -+ -+#ifndef __INCmvOsLinuxh -+#define __INCmvOsLinuxh -+ -+/* Includes */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include "mvOs.h" -+ -+ -+/* Definitions */ -+#define MV_DEFAULT_QUEUE_DEPTH 2 -+#define MV_SATA_SUPPORT_EDMA_SINGLE_DATA_REGION -+#define MV_SATA_SUPPORT_GEN2E_128_QUEUE_LEN -+ -+#ifdef CONFIG_MV88F6082 -+ #define MV_SATA_OVERRIDE_SW_QUEUE_SIZE -+ #define MV_SATA_REQUESTED_SW_QUEUE_SIZE 2 -+ #undef MV_SATA_SUPPORT_GEN2E_128_QUEUE_LEN -+#endif -+ -+/* System dependent macro for flushing CPU write cache */ -+#if defined (MV_BRIDGE_SYNC_REORDER) -+#define MV_CPU_WRITE_BUFFER_FLUSH() do { \ -+ wmb(); \ -+ mvOsBridgeReorderWA(); \ -+ } while (0) -+#else -+#define MV_CPU_WRITE_BUFFER_FLUSH() wmb() -+#endif /* CONFIG_MV78XX0 */ -+ -+/* System dependent little endian from / to CPU conversions */ -+#define MV_CPU_TO_LE16(x) cpu_to_le16(x) -+#define MV_CPU_TO_LE32(x) cpu_to_le32(x) -+ -+#define MV_LE16_TO_CPU(x) le16_to_cpu(x) -+#define MV_LE32_TO_CPU(x) le32_to_cpu(x) -+ -+#ifdef __BIG_ENDIAN_BITFIELD -+#define MV_BIG_ENDIAN_BITFIELD -+#endif -+ -+/* System dependent register read / write in byte/word/dword variants */ -+#define MV_REG_WRITE_BYTE(base, offset, val) writeb(val, base + offset) -+#define MV_REG_WRITE_WORD(base, offset, val) writew(val, base + offset) -+#define MV_REG_WRITE_DWORD(base, offset, val) writel(val, base + offset) -+#define MV_REG_READ_BYTE(base, offset) readb(base + offset) -+#define MV_REG_READ_WORD(base, offset) readw(base + offset) -+#define MV_REG_READ_DWORD(base, offset) readl(base + offset) -+ -+ -+/* Typedefs */ -+ -+/* System dependant typedefs */ -+typedef void *MV_VOID_PTR; -+typedef u32 *MV_U32_PTR; -+typedef u16 *MV_U16_PTR; -+typedef u8 *MV_U8_PTR; -+typedef char *MV_CHAR_PTR; -+typedef void *MV_BUS_ADDR_T; -+typedef unsigned long MV_CPU_FLAGS; -+ -+ -+/* Structures */ -+/* System dependent structure */ -+typedef struct mvOsSemaphore -+{ -+ int notUsed; -+} MV_OS_SEMAPHORE; -+ -+ -+/* Functions (User implemented)*/ -+ -+/* Semaphore init, take and release */ -+#define mvOsSemInit(x) MV_TRUE -+#define mvOsSemTake(x) -+#define mvOsSemRelease(x) -+ -+/* Interrupt masking and unmasking functions */ -+MV_CPU_FLAGS mvOsSaveFlagsAndMaskCPUInterrupts(MV_VOID); -+MV_VOID mvOsRestoreFlags(MV_CPU_FLAGS); -+ -+/* Delay function in micro seconds resolution */ -+void mvMicroSecondsDelay(MV_VOID_PTR, MV_U32); -+ -+/* Typedefs */ -+typedef enum mvBoolean -+{ -+ MV_SFALSE, MV_STRUE -+} MV_BOOLEAN; -+ -+/* System logging function */ -+#include "mvLog.h" -+/* Enable READ/WRITE Long SCSI command only when driver is compiled for debugging */ -+#ifdef MV_LOGGER -+#define MV_SATA_SUPPORT_READ_WRITE_LONG -+#endif -+ -+#define MV_IAL_LOG_ID 3 -+ -+#endif /* __INCmvOsLinuxh */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mvSysHwConfig.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mvSysHwConfig.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mvSysHwConfig.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mvSysHwConfig.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,375 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+ -+*******************************************************************************/ -+/******************************************************************************* -+* mvSysHwCfg.h - Marvell system HW configuration file -+* -+* DESCRIPTION: -+* None. -+* -+* DEPENDENCIES: -+* None. -+* -+*******************************************************************************/ -+ -+#ifndef __INCmvSysHwConfigh -+#define __INCmvSysHwConfigh -+ -+#include "../../../../include/linux/autoconf.h" -+ -+#define CONFIG_MARVELL 1 -+ -+/* includes */ -+#define _1K 0x00000400 -+#define _4K 0x00001000 -+#define _8K 0x00002000 -+#define _16K 0x00004000 -+#define _32K 0x00008000 -+#define _64K 0x00010000 -+#define _128K 0x00020000 -+#define _256K 0x00040000 -+#define _512K 0x00080000 -+ -+#define _1M 0x00100000 -+#define _2M 0x00200000 -+#define _4M 0x00400000 -+#define _8M 0x00800000 -+#define _16M 0x01000000 -+#define _32M 0x02000000 -+#define _64M 0x04000000 -+#define _128M 0x08000000 -+#define _256M 0x10000000 -+#define _512M 0x20000000 -+ -+#define _1G 0x40000000 -+#define _2G 0x80000000 -+ -+/****************************************/ -+/* Soc supporeted Units definitions */ -+/****************************************/ -+ -+#ifdef CONFIG_MV_INCLUDE_PEX -+#define MV_INCLUDE_PEX -+#endif -+#ifdef CONFIG_MV_INCLUDE_TWSI -+#define MV_INCLUDE_TWSI -+#endif -+#ifdef CONFIG_MV_INCLUDE_CESA -+#define MV_INCLUDE_CESA -+#endif -+#ifdef CONFIG_MV_INCLUDE_GIG_ETH -+#define MV_INCLUDE_GIG_ETH -+#endif -+#ifdef CONFIG_MV_INCLUDE_INTEG_SATA -+#define MV_INCLUDE_INTEG_SATA -+#define MV_INCLUDE_SATA -+#endif -+#ifdef CONFIG_MV_INCLUDE_USB -+#define MV_INCLUDE_USB -+#define MV_USB_VOLTAGE_FIX -+#endif -+#ifdef CONFIG_MV_INCLUDE_NAND -+#define MV_INCLUDE_NAND -+#endif -+#ifdef CONFIG_MV_INCLUDE_TDM -+#define MV_INCLUDE_TDM -+#endif -+#ifdef CONFIG_MV_INCLUDE_XOR -+#define MV_INCLUDE_XOR -+#endif -+#ifdef CONFIG_MV_INCLUDE_TWSI -+#define MV_INCLUDE_TWSI -+#endif -+#ifdef CONFIG_MV_INCLUDE_UART -+#define MV_INCLUDE_UART -+#endif -+#ifdef CONFIG_MV_INCLUDE_SPI -+#define MV_INCLUDE_SPI -+#endif -+#ifdef CONFIG_MV_INCLUDE_SFLASH_MTD -+#define MV_INCLUDE_SFLASH_MTD -+#endif -+#ifdef CONFIG_MV_INCLUDE_AUDIO -+#define MV_INCLUDE_AUDIO -+#endif -+#ifdef CONFIG_MV_INCLUDE_TS -+#define MV_INCLUDE_TS -+#endif -+#ifdef CONFIG_MV_INCLUDE_SDIO -+#define MV_INCLUDE_SDIO -+#endif -+ -+ -+/* NAND flash stuff */ -+#ifdef CONFIG_MV_NAND_BOOT -+#define MV_NAND_BOOT -+#endif -+#ifdef CONFIG_MV_NAND -+#define MV_NAND -+#endif -+ -+/* SPI flash stuff */ -+#ifdef CONFIG_MV_SPI_BOOT -+#define MV_SPI_BOOT -+#endif -+ -+ -+/****************************************************************/ -+/************* General configuration ********************/ -+/****************************************************************/ -+ -+/* Enable Clock Power Control */ -+#define MV_INCLUDE_CLK_PWR_CNTRL -+ -+/* Disable the DEVICE BAR in the PEX */ -+#define MV_DISABLE_PEX_DEVICE_BAR -+ -+/* Allow the usage of early printings during initialization */ -+#define MV_INCLUDE_EARLY_PRINTK -+ -+/****************************************************************/ -+/************* NFP configuration ********************************/ -+/****************************************************************/ -+#define MV_NFP_SEC_Q_SIZE 64 -+#define MV_NFP_SEC_REQ_Q_SIZE 1000 -+ -+ -+ -+/****************************************************************/ -+/************* CESA configuration ********************/ -+/****************************************************************/ -+ -+#ifdef MV_INCLUDE_CESA -+ -+#define MV_CESA_MAX_CHAN 4 -+ -+/* Use 2K of SRAM */ -+#define MV_CESA_MAX_BUF_SIZE 1600 -+ -+#endif /* MV_INCLUDE_CESA */ -+ -+#if defined(CONFIG_MV_INCLUDE_GIG_ETH) -+ -+#ifdef CONFIG_MV_NFP_STATS -+#define MV_FP_STATISTICS -+#else -+#undef MV_FP_STATISTICS -+#endif -+/* Default configuration for SKB_REUSE: 0 - Disabled, 1 - Enabled */ -+#define MV_ETH_SKB_REUSE_DEFAULT 1 -+/* Default configuration for TX_EN workaround: 0 - Disabled, 1 - Enabled */ -+#define MV_ETH_TX_EN_DEFAULT 0 -+ -+/* un-comment if you want to perform tx_done from within the poll function */ -+/* #define ETH_TX_DONE_ISR */ -+ -+/* put descriptors in uncached memory */ -+/* #define ETH_DESCR_UNCACHED */ -+ -+/* Descriptors location: DRAM/internal-SRAM */ -+#define ETH_DESCR_IN_SDRAM -+#undef ETH_DESCR_IN_SRAM /* No integrated SRAM in 88Fxx81 devices */ -+ -+#if defined(ETH_DESCR_IN_SRAM) -+#if defined(ETH_DESCR_UNCACHED) -+ #define ETH_DESCR_CONFIG_STR "Uncached descriptors in integrated SRAM" -+#else -+ #define ETH_DESCR_CONFIG_STR "Cached descriptors in integrated SRAM" -+#endif -+#elif defined(ETH_DESCR_IN_SDRAM) -+#if defined(ETH_DESCR_UNCACHED) -+ #define ETH_DESCR_CONFIG_STR "Uncached descriptors in DRAM" -+#else -+ #define ETH_DESCR_CONFIG_STR "Cached descriptors in DRAM" -+#endif -+#else -+ #error "Ethernet descriptors location undefined" -+#endif /* ETH_DESCR_IN_SRAM or ETH_DESCR_IN_SDRAM*/ -+ -+/* SW Sync-Barrier: not relevant for 88fxx81*/ -+/* Reasnable to define this macro when descriptors in SRAM and buffers in DRAM */ -+/* In RX the CPU theoretically might see himself as the descriptor owner, */ -+/* although the buffer hadn't been written to DRAM yet. Performance cost. */ -+/* #define INCLUDE_SYNC_BARR */ -+ -+/* Buffers cache coherency method (buffers in DRAM) */ -+#ifndef MV_CACHE_COHER_SW -+/* Taken from mvCommon.h */ -+/* Memory uncached, HW or SW cache coherency is not needed */ -+#define MV_UNCACHED 0 -+/* Memory cached, HW cache coherency supported in WriteThrough mode */ -+#define MV_CACHE_COHER_HW_WT 1 -+/* Memory cached, HW cache coherency supported in WriteBack mode */ -+#define MV_CACHE_COHER_HW_WB 2 -+/* Memory cached, No HW cache coherency, Cache coherency must be in SW */ -+#define MV_CACHE_COHER_SW 3 -+ -+#endif -+ -+/* DRAM cache coherency configuration */ -+#define MV_CACHE_COHERENCY MV_CACHE_COHER_SW -+ -+ -+#define ETHER_DRAM_COHER MV_CACHE_COHER_SW /* No HW coherency in 88Fxx81 devices */ -+ -+#if (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WB) -+ #define ETH_SDRAM_CONFIG_STR "DRAM HW cache coherency (write-back)" -+#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WT) -+ #define ETH_SDRAM_CONFIG_STR "DRAM HW cache coherency (write-through)" -+#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) -+ #define ETH_SDRAM_CONFIG_STR "DRAM SW cache-coherency" -+#elif (ETHER_DRAM_COHER == MV_UNCACHED) -+# define ETH_SDRAM_CONFIG_STR "DRAM uncached" -+#else -+ #error "Ethernet-DRAM undefined" -+#endif /* ETHER_DRAM_COHER */ -+ -+ -+/****************************************************************/ -+/************* Ethernet driver configuration ********************/ -+/****************************************************************/ -+ -+/* port's default queueus */ -+#define ETH_DEF_TXQ 0 -+#define ETH_DEF_RXQ 0 -+ -+#define MV_ETH_RX_Q_NUM CONFIG_MV_ETH_RX_Q_NUM -+#define MV_ETH_TX_Q_NUM CONFIG_MV_ETH_TX_Q_NUM -+ -+/* interrupt coalescing setting */ -+#define ETH_TX_COAL 200 -+#define ETH_RX_COAL 200 -+ -+/* Checksum offloading */ -+#define TX_CSUM_OFFLOAD -+#define RX_CSUM_OFFLOAD -+ -+#endif /* CONFIG_MV_INCLUDE_GIG_ETH */ -+ -+/****************************************************************/ -+/*************** Telephony configuration ************************/ -+/****************************************************************/ -+#if defined(CONFIG_MV_TDM_LINEAR_MODE) -+ #define MV_TDM_LINEAR_MODE -+#elif defined(CONFIG_MV_TDM_ULAW_MODE) -+ #define MV_TDM_ULAW_MODE -+#endif -+ -+#if defined(CONFIG_MV_TDM_5CHANNELS) -+ #define MV_TDM_5CHANNELS -+#endif -+ -+#if defined(CONFIG_MV_TDM_USE_EXTERNAL_PCLK_SOURCE) -+ #define MV_TDM_USE_EXTERNAL_PCLK_SOURCE -+#endif -+ -+/* We use the following registers to store DRAM interface pre configuration */ -+/* auto-detection results */ -+/* IMPORTANT: We are using mask register for that purpose. Before writing */ -+/* to units mask register, make sure main maks register is set to disable */ -+/* all interrupts. */ -+#define DRAM_BUF_REG0 0x30810 /* sdram bank 0 size */ -+#define DRAM_BUF_REG1 0x30820 /* sdram config */ -+#define DRAM_BUF_REG2 0x30830 /* sdram mode */ -+#define DRAM_BUF_REG3 0x308c4 /* dunit control low */ -+#define DRAM_BUF_REG4 0x60a90 /* sdram address control */ -+#define DRAM_BUF_REG5 0x60a94 /* sdram timing control low */ -+#define DRAM_BUF_REG6 0x60a98 /* sdram timing control high */ -+#define DRAM_BUF_REG7 0x60a9c /* sdram ODT control low */ -+#define DRAM_BUF_REG8 0x60b90 /* sdram ODT control high */ -+#define DRAM_BUF_REG9 0x60b94 /* sdram Dunit ODT control */ -+#define DRAM_BUF_REG10 0x60b98 /* sdram Extended Mode */ -+#define DRAM_BUF_REG11 0x60b9c /* sdram Ddr2 Time Low Reg */ -+#define DRAM_BUF_REG12 0x60a00 /* sdram Ddr2 Time High Reg */ -+#define DRAM_BUF_REG13 0x60a04 /* dunit Ctrl High */ -+#define DRAM_BUF_REG14 0x60b00 /* sdram second DIMM exist */ -+ -+/* Following the pre-configuration registers default values restored after */ -+/* auto-detection is done */ -+#define DRAM_BUF_REG_DV 0 -+ -+/* System Mapping */ -+#define SDRAM_CS0_BASE 0x00000000 -+#define SDRAM_CS0_SIZE _256M -+ -+#define SDRAM_CS1_BASE 0x10000000 -+#define SDRAM_CS1_SIZE _256M -+ -+#define SDRAM_CS2_BASE 0x20000000 -+#define SDRAM_CS2_SIZE _256M -+ -+#define SDRAM_CS3_BASE 0x30000000 -+#define SDRAM_CS3_SIZE _256M -+ -+/* PEX */ -+#define PEX0_MEM_BASE 0xe8000000 -+#define PEX0_MEM_SIZE _128M -+ -+#define PEX0_IO_BASE 0xf2000000 -+#define PEX0_IO_SIZE _1M -+ -+/* Device Chip Selects */ -+#define NFLASH_CS_BASE 0xfa000000 -+#define NFLASH_CS_SIZE _2M -+ -+#define SPI_CS_BASE 0xf4000000 -+#define SPI_CS_SIZE _16M -+ -+#define CRYPT_ENG_BASE 0xf0000000 -+#define CRYPT_ENG_SIZE _2M -+ -+#define BOOTDEV_CS_BASE 0xff800000 -+#define BOOTDEV_CS_SIZE _8M -+ -+/* CS2 - BOOTROM */ -+#define DEVICE_CS2_BASE 0xff900000 -+#define DEVICE_CS2_SIZE _1M -+ -+/* PEX Work arround */ -+/* the target we will use for the workarround */ -+#define PEX_CONFIG_RW_WA_TARGET PEX0_MEM -+/*a flag that indicates if we are going to use the -+size and base of the target we using for the workarround -+window */ -+#define PEX_CONFIG_RW_WA_USE_ORIGINAL_WIN_VALUES 1 -+/* if the above flag is 0 then the following values -+will be used for the workarround window base and size, -+otherwise the following defines will be ignored */ -+#define PEX_CONFIG_RW_WA_BASE 0xF3000000 -+#define PEX_CONFIG_RW_WA_SIZE _16M -+ -+/* Internal registers: size is defined in Controllerenvironment */ -+#define INTER_REGS_BASE 0xFEE00000 -+ -+/* DRAM detection stuff */ -+#define MV_DRAM_AUTO_SIZE -+ -+/* Board clock detection */ -+#define TCLK_AUTO_DETECT /* Use Tclk auto detection */ -+#define SYSCLK_AUTO_DETECT /* Use SysClk auto detection */ -+#define PCLCK_AUTO_DETECT /* Use PClk auto detection */ -+#define L2CLK_AUTO_DETECT /* Use L2Clk auto detection */ -+ -+/* PEX-PCI\PCI-PCI Bridge*/ -+#define PCI0_IF_PTP 0 /* Bridge exist on pciIf0*/ -+ -+ -+ -+#endif /* __INCmvSysHwConfigh */ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,376 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "mvCntmr.h" -+#include "cpu/mvCpu.h" -+ -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+extern unsigned int whoAmI(void); -+ -+/******************************************************************************* -+* mvCntmrLoad - -+* -+* DESCRIPTION: -+* Load an init Value to a given counter/timer -+* -+* INPUT: -+* countNum - counter number -+* value - value to be loaded -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess -+*******************************************************************************/ -+MV_STATUS mvCntmrLoad(MV_U32 countNum, MV_U32 value) -+{ -+ if (countNum >= MV_CNTMR_MAX_COUNTER ) -+ { -+ -+ mvOsPrintf(("mvCntmrLoad: Err. Illigal counter number \n")); -+ return MV_BAD_PARAM;; -+ -+ } -+ -+ MV_REG_WRITE(CNTMR_RELOAD_REG(countNum),value); -+ MV_REG_WRITE(CNTMR_VAL_REG(countNum),value); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCntmrRead - -+* -+* DESCRIPTION: -+* Returns the value of the given Counter/Timer -+* -+* INPUT: -+* countNum - counter number -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_U32 counter value -+*******************************************************************************/ -+MV_U32 mvCntmrRead(MV_U32 countNum) -+{ -+ return MV_REG_READ(CNTMR_VAL_REG(countNum)); -+} -+ -+/******************************************************************************* -+* mvCntmrWrite - -+* -+* DESCRIPTION: -+* Returns the value of the given Counter/Timer -+* -+* INPUT: -+* countNum - counter number -+* countVal - value to write -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None -+*******************************************************************************/ -+void mvCntmrWrite(MV_U32 countNum,MV_U32 countVal) -+{ -+ MV_REG_WRITE(CNTMR_VAL_REG(countNum),countVal); -+} -+ -+/******************************************************************************* -+* mvCntmrCtrlSet - -+* -+* DESCRIPTION: -+* Set the Control to a given counter/timer -+* -+* INPUT: -+* countNum - counter number -+* pCtrl - pointer to MV_CNTMR_CTRL structure -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess -+*******************************************************************************/ -+MV_STATUS mvCntmrCtrlSet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl) -+{ -+ MV_U32 cntmrCtrl; -+ -+ if (countNum >= MV_CNTMR_MAX_COUNTER ) -+ { -+ -+ DB(mvOsPrintf(("mvCntmrCtrlSet: Err. Illigal counter number \n"))); -+ return MV_BAD_PARAM;; -+ -+ } -+ -+ /* read control register */ -+ cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG); -+ -+ -+ if (pCtrl->enable) /* enable counter\timer */ -+ { -+ cntmrCtrl |= CTCR_ARM_TIMER_EN(countNum); -+ } -+ else /* disable counter\timer */ -+ { -+ cntmrCtrl &= ~CTCR_ARM_TIMER_EN(countNum); -+ } -+ -+ if ( pCtrl->autoEnable ) /* Auto mode */ -+ { -+ cntmrCtrl |= CTCR_ARM_TIMER_AUTO_EN(countNum); -+ -+ } -+ else /* no auto mode */ -+ { -+ cntmrCtrl &= ~CTCR_ARM_TIMER_AUTO_EN(countNum); -+ } -+ -+ MV_REG_WRITE(CNTMR_CTRL_REG,cntmrCtrl); -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvCntmrCtrlGet - -+* -+* DESCRIPTION: -+* Get the Control value of a given counter/timer -+* -+* INPUT: -+* countNum - counter number -+* pCtrl - pointer to MV_CNTMR_CTRL structure -+* -+* OUTPUT: -+* Counter\Timer control value -+* -+* RETURN: -+* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess -+*******************************************************************************/ -+MV_STATUS mvCntmrCtrlGet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl) -+{ -+ MV_U32 cntmrCtrl; -+ -+ if (countNum >= MV_CNTMR_MAX_COUNTER ) -+ { -+ DB(mvOsPrintf(("mvCntmrCtrlGet: Err. Illigal counter number \n"))); -+ return MV_BAD_PARAM;; -+ } -+ -+ /* read control register */ -+ cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG); -+ -+ /* enable counter\timer */ -+ if (cntmrCtrl & CTCR_ARM_TIMER_EN(countNum)) -+ { -+ pCtrl->enable = MV_TRUE; -+ } -+ else -+ { -+ pCtrl->enable = MV_FALSE; -+ } -+ -+ /* counter mode */ -+ if (cntmrCtrl & CTCR_ARM_TIMER_AUTO_EN(countNum)) -+ { -+ pCtrl->autoEnable = MV_TRUE; -+ } -+ else -+ { -+ pCtrl->autoEnable = MV_FALSE; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCntmrEnable - -+* -+* DESCRIPTION: -+* Set the Enable-Bit to logic '1' ==> starting the counter -+* -+* INPUT: -+* countNum - counter number -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess -+*******************************************************************************/ -+MV_STATUS mvCntmrEnable(MV_U32 countNum) -+{ -+ MV_U32 cntmrCtrl; -+ -+ if (countNum >= MV_CNTMR_MAX_COUNTER ) -+ { -+ -+ DB(mvOsPrintf(("mvCntmrEnable: Err. Illigal counter number \n"))); -+ return MV_BAD_PARAM;; -+ -+ } -+ -+ /* read control register */ -+ cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG); -+ -+ /* enable counter\timer */ -+ cntmrCtrl |= CTCR_ARM_TIMER_EN(countNum); -+ -+ -+ MV_REG_WRITE(CNTMR_CTRL_REG,cntmrCtrl); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCntmrDisable - -+* -+* DESCRIPTION: -+* Stop the counter/timer running, and returns its Value -+* -+* INPUT: -+* countNum - counter number -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_U32 counter\timer value -+*******************************************************************************/ -+MV_STATUS mvCntmrDisable(MV_U32 countNum) -+{ -+ MV_U32 cntmrCtrl; -+ -+ if (countNum >= MV_CNTMR_MAX_COUNTER ) -+ { -+ -+ DB(mvOsPrintf(("mvCntmrDisable: Err. Illigal counter number \n"))); -+ return MV_BAD_PARAM;; -+ -+ } -+ -+ /* read control register */ -+ cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG); -+ -+ /* disable counter\timer */ -+ cntmrCtrl &= ~CTCR_ARM_TIMER_EN(countNum); -+ -+ MV_REG_WRITE(CNTMR_CTRL_REG,cntmrCtrl); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvCntmrStart - -+* -+* DESCRIPTION: -+* Combined all the sub-operations above to one function: Load,setMode,Enable -+* -+* INPUT: -+* countNum - counter number -+* value - value of the counter\timer to be set -+* pCtrl - pointer to MV_CNTMR_CTRL structure -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess -+*******************************************************************************/ -+MV_STATUS mvCntmrStart(MV_U32 countNum, MV_U32 value, -+ MV_CNTMR_CTRL *pCtrl) -+{ -+ -+ if (countNum >= MV_CNTMR_MAX_COUNTER ) -+ { -+ -+ mvOsPrintf(("mvCntmrDisable: Err. Illigal counter number \n")); -+ return MV_BAD_PARAM;; -+ -+ } -+ -+ /* load value onto counter\timer */ -+ mvCntmrLoad(countNum,value); -+ -+ /* set the counter to load in the first time */ -+ mvCntmrWrite(countNum,value); -+ -+ /* set control for timer \ cunter and enable */ -+ mvCntmrCtrlSet(countNum,pCtrl); -+ -+ return MV_OK; -+} -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,121 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvTmrWtdgh -+#define __INCmvTmrWtdgh -+ -+/* includes */ -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "cntmr/mvCntmrRegs.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+ -+ -+/* This enumerator describe counters\watchdog numbers */ -+typedef enum _mvCntmrID -+{ -+ TIMER0 = 0, -+ TIMER1, -+ WATCHDOG, -+ TIMER2, -+ TIMER3, -+}MV_CNTMR_ID; -+ -+ -+/* Counter / Timer control structure */ -+typedef struct _mvCntmrCtrl -+{ -+ MV_BOOL enable; /* enable */ -+ MV_BOOL autoEnable; /* counter/Timer */ -+}MV_CNTMR_CTRL; -+ -+ -+/* Functions */ -+ -+/* Load an init Value to a given counter/timer */ -+MV_STATUS mvCntmrLoad(MV_U32 countNum, MV_U32 value); -+ -+/* Returns the value of the given Counter/Timer */ -+MV_U32 mvCntmrRead(MV_U32 countNum); -+ -+/* Write a value of the given Counter/Timer */ -+void mvCntmrWrite(MV_U32 countNum,MV_U32 countVal); -+ -+/* Set the Control to a given counter/timer */ -+MV_STATUS mvCntmrCtrlSet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl); -+ -+/* Get the value of a given counter/timer */ -+MV_STATUS mvCntmrCtrlGet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl); -+ -+/* Set the Enable-Bit to logic '1' ==> starting the counter. */ -+MV_STATUS mvCntmrEnable(MV_U32 countNum); -+ -+/* Stop the counter/timer running, and returns its Value. */ -+MV_STATUS mvCntmrDisable(MV_U32 countNum); -+ -+/* Combined all the sub-operations above to one function: Load,setMode,Enable */ -+MV_STATUS mvCntmrStart(MV_U32 countNum, MV_U32 value, -+ MV_CNTMR_CTRL *pCtrl); -+ -+#endif /* __INCmvTmrWtdgh */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmrRegs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmrRegs.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmrRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmrRegs.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,121 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvTmrwtdgRegsh -+#define __INCmvTmrwtdgRegsh -+ -+/*******************************************/ -+/* ARM Timers Registers Map */ -+/*******************************************/ -+ -+#define CNTMR_RELOAD_REG(tmrNum) (CNTMR_BASE + 0x10 + (tmrNum)*8 + \ -+ (((tmrNum) <= 3)?0:8)) -+#define CNTMR_VAL_REG(tmrNum) (CNTMR_BASE + 0x14 + (tmrNum)*8 + \ -+ (((tmrNum) <= 3)?0:8)) -+#define CNTMR_CTRL_REG (CNTMR_BASE) -+ -+/*For MV78XX0*/ -+#define CNTMR_CAUSE_REG (CPU_AHB_MBUS_CAUSE_INT_REG(whoAmI())) -+#define CNTMR_MASK_REG (CPU_AHB_MBUS_MASK_INT_REG(whoAmI())) -+ -+/* ARM Timers Registers Map */ -+/*******************************************/ -+ -+ -+/* ARM Timers Control Register */ -+/* CPU_TIMERS_CTRL_REG (CTCR) */ -+ -+#define TIMER0_NUM 0 -+#define TIMER1_NUM 1 -+#define WATCHDOG_NUM 2 -+#define TIMER2_NUM 3 -+#define TIMER3_NUM 4 -+ -+#define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2) -+#define CTCR_ARM_TIMER_EN_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS) -+#define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr)) -+#define CTCR_ARM_TIMER_DIS(cntr) (0 << CTCR_ARM_TIMER_EN_OFFS(cntr)) -+ -+#define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1) -+#define CTCR_ARM_TIMER_AUTO_MASK(cntr) BIT1 -+#define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) -+#define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) -+ -+ -+/* ARM Timer\Watchdog Reload Register */ -+/* CNTMR_RELOAD_REG (TRR) */ -+ -+#define TRG_ARM_TIMER_REL_OFFS 0 -+#define TRG_ARM_TIMER_REL_MASK 0xffffffff -+ -+/* ARM Timer\Watchdog Register */ -+/* CNTMR_VAL_REG (TVRG) */ -+ -+#define TVR_ARM_TIMER_OFFS 0 -+#define TVR_ARM_TIMER_MASK 0xffffffff -+#define TVR_ARM_TIMER_MAX 0xffffffff -+ -+ -+ -+#endif /* __INCmvTmrwtdgRegsh */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCompVer.txt linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCompVer.txt ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCompVer.txt 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCompVer.txt 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,4 @@ -+Global HAL Version: FEROCEON_HAL_3_1_7 -+Unit HAL Version: 3.1.3 -+Description: This component includes an implementation of the unit HAL drivers -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,207 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include "mvOs.h" -+#include "mvCpuCntrs.h" -+ -+ -+const static MV_CPU_CNTRS_OPS mvCpuCntrsOpsTbl[MV_CPU_CNTRS_NUM][MV_CPU_CNTRS_OPS_NUM] = -+{ -+ /*0*/ -+ { -+ MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_DCACHE_READ_HIT, MV_CPU_CNTRS_DCACHE_READ_MISS, -+ MV_CPU_CNTRS_DCACHE_WRITE_HIT, MV_CPU_CNTRS_DCACHE_WRITE_MISS, MV_CPU_CNTRS_INSTRUCTIONS, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, -+ MV_CPU_CNTRS_MMU_READ_LATENCY, MV_CPU_CNTRS_ICACHE_READ_LATENCY, MV_CPU_CNTRS_WB_WRITE_LATENCY, -+ MV_CPU_CNTRS_LDM_STM_HOLD, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, -+ MV_CPU_CNTRS_DATA_WRITE_ACCESS, MV_CPU_CNTRS_DATA_READ_ACCESS, MV_CPU_CNTRS_INVALID, -+ MV_CPU_CNTRS_BRANCH_PREDICT_COUNT, -+ }, -+ /*1*/ -+ { -+ MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_ICACHE_READ_MISS, MV_CPU_CNTRS_DCACHE_READ_MISS, -+ MV_CPU_CNTRS_DCACHE_WRITE_MISS, MV_CPU_CNTRS_ITLB_MISS, MV_CPU_CNTRS_SINGLE_ISSUE, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BRANCH_RETIRED, MV_CPU_CNTRS_INVALID, -+ MV_CPU_CNTRS_MMU_READ_BEAT, MV_CPU_CNTRS_ICACHE_READ_LATENCY, MV_CPU_CNTRS_WB_WRITE_BEAT, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_IS_HOLD, MV_CPU_CNTRS_DATA_READ_ACCESS, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, -+ MV_CPU_CNTRS_INVALID, -+ }, -+ /*2*/ -+ { -+ MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DCACHE_ACCESS, -+ MV_CPU_CNTRS_DTLB_MISS, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BRANCH_PREDICT_MISS, MV_CPU_CNTRS_WB_WRITE_BEAT, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DCACHE_READ_LATENCY, MV_CPU_CNTRS_DCACHE_WRITE_LATENCY, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BIU_SIMULT_ACCESS, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, -+ MV_CPU_CNTRS_INVALID, -+ }, -+ /*3*/ -+ { -+ MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_DCACHE_READ_MISS, MV_CPU_CNTRS_DCACHE_WRITE_MISS, -+ MV_CPU_CNTRS_TLB_MISS, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BRANCH_TAKEN, MV_CPU_CNTRS_WB_FULL_CYCLES, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DCACHE_READ_BEAT, MV_CPU_CNTRS_DCACHE_WRITE_BEAT, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BIU_ANY_ACCESS, -+ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DATA_WRITE_ACCESS, -+ MV_CPU_CNTRS_INVALID, -+ } -+}; -+ -+MV_CPU_CNTRS_ENTRY mvCpuCntrsTbl[MV_CPU_CNTRS_NUM]; -+ -+MV_CPU_CNTRS_EVENT* mvCpuCntrsEventTbl[128]; -+ -+void mvCpuCntrsReset(void) -+{ -+ MV_U32 reg = 0; -+ -+ MV_ASM ("mcr p15, 0, %0, c15, c13, 0" : : "r" (reg)); -+ MV_ASM ("mcr p15, 0, %0, c15, c13, 1" : : "r" (reg)); -+ MV_ASM ("mcr p15, 0, %0, c15, c13, 2" : : "r" (reg)); -+ MV_ASM ("mcr p15, 0, %0, c15, c13, 3" : : "r" (reg)); -+ MV_ASM ("mcr p15, 0, %0, c15, c13, 4" : : "r" (reg)); -+ MV_ASM ("mcr p15, 0, %0, c15, c13, 5" : : "r" (reg)); -+ MV_ASM ("mcr p15, 0, %0, c15, c13, 6" : : "r" (reg)); -+ MV_ASM ("mcr p15, 0, %0, c15, c13, 7" : : "r" (reg)); -+} -+ -+void program_counter(int counter, int op) -+{ -+ MV_U32 reg = (1 << op) | 0x1; /*enable*/ -+ -+ switch(counter) -+ { -+ case 0: -+ __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 0" : : "r" (reg)); -+ return; -+ -+ case 1: -+ __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 1" : : "r" (reg)); -+ return; -+ -+ case 2: -+ __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 2" : : "r" (reg)); -+ return; -+ -+ case 3: -+ __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 3" : : "r" (reg)); -+ return; -+ -+ default: -+ mvOsPrintf("error in program_counter: bad counter number (%d)\n", counter); -+ } -+ return; -+} -+ -+void mvCpuCntrsEventClear(MV_CPU_CNTRS_EVENT* pEvent) -+{ -+ int i; -+ -+ for(i=0; icounters_sum[i] = 0; -+ } -+ pEvent->num_of_measurements = 0; -+} -+ -+ -+MV_CPU_CNTRS_EVENT* mvCpuCntrsEventCreate(char* name, MV_U32 print_threshold) -+{ -+ int i; -+ MV_CPU_CNTRS_EVENT* event = mvOsMalloc(sizeof(MV_CPU_CNTRS_EVENT)); -+ -+ if(event) -+ { -+ strncpy(event->name, name, sizeof(event->name)); -+ event->num_of_measurements = 0; -+ event->avg_sample_count = print_threshold; -+ for(i=0; icounters_before[i] = 0; -+ event->counters_after[i] = 0; -+ event->counters_sum[i] = 0; -+ } -+ } -+ return event; -+} -+ -+void mvCpuCntrsEventDelete(MV_CPU_CNTRS_EVENT* event) -+{ -+ if(event != NULL) -+ mvOsFree(event); -+} -+ -+ -+MV_STATUS mvCpuCntrsProgram(int counter, MV_CPU_CNTRS_OPS op, -+ char* name, MV_U32 overhead) -+{ -+ int i; -+ -+ /* Find required operations */ -+ for(i=0; inum_of_measurements < pEvent->avg_sample_count) -+ return; -+ -+ mvOsPrintf("%16s: ", pEvent->name); -+ for(i=0; icounters_sum[i], -+ pEvent->num_of_measurements, NULL); -+ if(counters_avg >= mvCpuCntrsTbl[i].overhead) -+ counters_avg -= mvCpuCntrsTbl[i].overhead; -+ else -+ counters_avg = 0; -+ -+ mvOsPrintf("%s=%5llu, ", mvCpuCntrsTbl[i].name, counters_avg); -+ } -+ mvOsPrintf("\n"); -+ mvCpuCntrsEventClear(pEvent); -+ mvCpuCntrsReset(); -+} -+ -+void mvCpuCntrsStatus(void) -+{ -+ int i; -+ -+ for(i=0; icounters_before[i] = mvCpuCntrsRead(i); -+#else -+ pEvent->counters_before[1] = mvCpuCntrsRead(1); -+ pEvent->counters_before[3] = mvCpuCntrsRead(3); -+ pEvent->counters_before[0] = mvCpuCntrsRead(0); -+ pEvent->counters_before[2] = mvCpuCntrsRead(2); -+#endif -+} -+ -+static INLINE void mvCpuCntrsReadAfter(MV_CPU_CNTRS_EVENT* pEvent) -+{ -+ int i; -+ -+#if 0 -+ /* order is important - we want to measure the cycle count first here! */ -+ for(i=0; icounters_after[i] = mvCpuCntrsRead(i); -+#else -+ pEvent->counters_after[2] = mvCpuCntrsRead(2); -+ pEvent->counters_after[0] = mvCpuCntrsRead(0); -+ pEvent->counters_after[3] = mvCpuCntrsRead(3); -+ pEvent->counters_after[1] = mvCpuCntrsRead(1); -+#endif -+ -+ for(i=0; icounters_sum[i] += (pEvent->counters_after[i] - pEvent->counters_before[i]); -+ } -+ pEvent->num_of_measurements++; -+} -+ -+ -+#ifdef CONFIG_MV_CPU_PERF_CNTRS -+ -+#define MV_CPU_CNTRS_READ(counter) mvCpuCntrsRead(counter) -+ -+#define MV_CPU_CNTRS_START(event) mvCpuCntrsReadBefore(event) -+ -+#define MV_CPU_CNTRS_STOP(event) mvCpuCntrsReadAfter(event) -+ -+#define MV_CPU_CNTRS_SHOW(event) mvCpuCntrsShow(event) -+ -+#else -+ -+#define MV_CPU_CNTRS_READ(counter) -+#define MV_CPU_CNTRS_START(event) -+#define MV_CPU_CNTRS_STOP(event) -+#define MV_CPU_CNTRS_SHOW(event) -+ -+#endif /* CONFIG_MV_CPU_PERF_CNTRS */ -+ -+ -+#endif /* __mvCpuCntrs_h__ */ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,143 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include "mvOs.h" -+#include "mvCpuL2Cntrs.h" -+ -+ -+ -+MV_CPU_L2_CNTRS_ENTRY mvCpuL2CntrsTbl[MV_CPU_L2_CNTRS_NUM]; -+ -+MV_CPU_L2_CNTRS_EVENT* mvCpuL2CntrsEventTbl[128]; -+ -+void mvCpuL2CntrsReset(void) -+{ -+ MV_U32 reg = 0; -+ -+ MV_ASM ("mcr p15, 6, %0, c15, c13, 0" : : "r" (reg)); -+ MV_ASM ("mcr p15, 6, %0, c15, c13, 1" : : "r" (reg)); -+ MV_ASM ("mcr p15, 6, %0, c15, c13, 2" : : "r" (reg)); -+ MV_ASM ("mcr p15, 6, %0, c15, c13, 3" : : "r" (reg)); -+} -+ -+static void mvCpuL2CntrConfig(int counter, int op) -+{ -+ MV_U32 reg = (1 << op) | 0x1; /*enable*/ -+ -+ switch(counter) -+ { -+ case 0: -+ MV_ASM ("mcr p15, 6, %0, c15, c12, 0" : : "r" (reg)); -+ return; -+ -+ case 1: -+ MV_ASM ("mcr p15, 6, %0, c15, c12, 1" : : "r" (reg)); -+ return; -+ -+ default: -+ mvOsPrintf("mvCpuL2CntrConfig: bad counter number (%d)\n", counter); -+ } -+ return; -+} -+ -+void mvCpuL2CntrsEventClear(MV_CPU_L2_CNTRS_EVENT* pEvent) -+{ -+ int i; -+ -+ for(i=0; icounters_sum[i] = 0; -+ } -+ pEvent->num_of_measurements = 0; -+} -+ -+ -+MV_CPU_L2_CNTRS_EVENT* mvCpuL2CntrsEventCreate(char* name, MV_U32 print_threshold) -+{ -+ int i; -+ MV_CPU_L2_CNTRS_EVENT* event = mvOsMalloc(sizeof(MV_CPU_L2_CNTRS_EVENT)); -+ -+ if(event) -+ { -+ strncpy(event->name, name, sizeof(event->name)); -+ event->num_of_measurements = 0; -+ event->avg_sample_count = print_threshold; -+ for(i=0; icounters_before[i] = 0; -+ event->counters_after[i] = 0; -+ event->counters_sum[i] = 0; -+ } -+ } -+ return event; -+} -+ -+void mvCpuL2CntrsEventDelete(MV_CPU_L2_CNTRS_EVENT* event) -+{ -+ if(event != NULL) -+ mvOsFree(event); -+} -+ -+ -+MV_STATUS mvCpuL2CntrsProgram(int counter, MV_CPU_L2_CNTRS_OPS op, -+ char* name, MV_U32 overhead) -+{ -+ strncpy(mvCpuL2CntrsTbl[counter].name, name, sizeof(mvCpuL2CntrsTbl[counter].name)); -+ mvCpuL2CntrsTbl[counter].operation = op; -+ mvCpuL2CntrsTbl[counter].opIdx = op; -+ mvCpuL2CntrsTbl[counter].overhead = overhead; -+ mvCpuL2CntrConfig(counter, op); -+ mvOsPrintf("CPU L2 Counter %d: operation=%d, overhead=%d\n", -+ counter, op, overhead); -+ return MV_OK; -+} -+ -+void mvCpuL2CntrsShow(MV_CPU_L2_CNTRS_EVENT* pEvent) -+{ -+ int i; -+ MV_U64 counters_avg; -+ -+ if(pEvent->num_of_measurements < pEvent->avg_sample_count) -+ return; -+ -+ mvOsPrintf("%16s: ", pEvent->name); -+ for(i=0; icounters_sum[i], -+ pEvent->num_of_measurements, NULL); -+ -+ if(counters_avg >= mvCpuL2CntrsTbl[i].overhead) -+ counters_avg -= mvCpuL2CntrsTbl[i].overhead; -+ else -+ counters_avg = 0; -+ -+ mvOsPrintf("%s=%5llu, ", mvCpuL2CntrsTbl[i].name, counters_avg); -+ } -+ mvOsPrintf("\n"); -+ mvCpuL2CntrsEventClear(pEvent); -+ mvCpuL2CntrsReset(); -+} -+ -+void mvCpuL2CntrsStatus(void) -+{ -+ int i; -+ -+ for(i=0; icounters_before[i] = mvCpuL2CntrsRead(i); -+} -+ -+static INLINE void mvCpuL2CntrsReadAfter(MV_CPU_L2_CNTRS_EVENT* pEvent) -+{ -+ int i; -+ -+ for(i=0; icounters_after[i] = mvCpuL2CntrsRead(i); -+ pEvent->counters_sum[i] += (pEvent->counters_after[i] - pEvent->counters_before[i]); -+ } -+ pEvent->num_of_measurements++; -+} -+ -+ -+#ifdef CONFIG_MV_CPU_L2_PERF_CNTRS -+ -+#define MV_CPU_L2_CNTRS_READ(counter) mvCpuL2CntrsRead(counter) -+ -+#define MV_CPU_L2_CNTRS_START(event) mvCpuL2CntrsReadBefore(event) -+ -+#define MV_CPU_L2_CNTRS_STOP(event) mvCpuL2CntrsReadAfter(event) -+ -+#define MV_CPU_L2_CNTRS_SHOW(event) mvCpuL2CntrsShow(event) -+ -+#else -+ -+#define MV_CPU_L2_CNTRS_READ(counter) -+#define MV_CPU_L2_CNTRS_START(event) -+#define MV_CPU_L2_CNTRS_STOP(event) -+#define MV_CPU_L2_CNTRS_SHOW(event) -+ -+#endif /* CONFIG_MV_CPU_L2_PERF_CNTRS */ -+ -+ -+#endif /* __mvCpuL2Cntrs_h__ */ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvCompVer.txt linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvCompVer.txt ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvCompVer.txt 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvCompVer.txt 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,4 @@ -+Global HAL Version: FEROCEON_HAL_3_1_7 -+Unit HAL Version: 3.1.3 -+Description: This component includes an implementation of the unit HAL drivers -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,1479 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "ddr1_2/mvDram.h" -+#include "boardEnv/mvBoardEnvLib.h" -+ -+#undef MV_DEBUG -+#ifdef MV_DEBUG -+#define DB(x) x -+#else -+#define DB(x) -+#endif -+ -+static MV_VOID cpyDimm2BankInfo(MV_DIMM_INFO *pDimmInfo, -+ MV_DRAM_BANK_INFO *pBankInfo); -+static MV_U32 cas2ps(MV_U8 spd_byte); -+/******************************************************************************* -+* mvDramBankGet - Get the DRAM bank paramters. -+* -+* DESCRIPTION: -+* This function retrieves DRAM bank parameters as described in -+* DRAM_BANK_INFO struct to the controller DRAM unit. In case the board -+* has its DRAM on DIMMs it will use its EEPROM to extract SPD data -+* from it. Otherwise, if the DRAM is soldered on board, the function -+* should insert its bank information into MV_DRAM_BANK_INFO struct. -+* -+* INPUT: -+* bankNum - Board DRAM bank number. -+* -+* OUTPUT: -+* pBankInfo - DRAM bank information struct. -+* -+* RETURN: -+* MV_FAIL - Bank parameters could not be read. -+* -+*******************************************************************************/ -+MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo) -+{ -+ MV_DIMM_INFO dimmInfo; -+ -+ DB(mvOsPrintf("Dram: mvDramBankInfoGet bank %d\n", bankNum)); -+ /* zero pBankInfo structure */ -+ memset(pBankInfo, 0, sizeof(*pBankInfo)); -+ -+ if((NULL == pBankInfo) || (bankNum >= MV_DRAM_MAX_CS )) -+ { -+ DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); -+ return MV_BAD_PARAM; -+ } -+ if( MV_OK != dimmSpdGet((MV_U32)(bankNum/2), &dimmInfo)) -+ { -+ DB(mvOsPrintf("Dram: ERR dimmSpdGet failed to get dimm info \n")); -+ return MV_FAIL; -+ } -+ if((dimmInfo.numOfModuleBanks == 1) && ((bankNum % 2) == 1)) -+ { -+ DB(mvOsPrintf("Dram: ERR dimmSpdGet. Can't find DIMM bank 2 \n")); -+ return MV_FAIL; -+ } -+ -+ /* convert Dimm info to Bank info */ -+ cpyDimm2BankInfo(&dimmInfo, pBankInfo); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* cpyDimm2BankInfo - Convert a Dimm info struct into a bank info struct. -+* -+* DESCRIPTION: -+* Convert a Dimm info struct into a bank info struct. -+* -+* INPUT: -+* pDimmInfo - DIMM information structure. -+* -+* OUTPUT: -+* pBankInfo - DRAM bank information struct. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+static MV_VOID cpyDimm2BankInfo(MV_DIMM_INFO *pDimmInfo, -+ MV_DRAM_BANK_INFO *pBankInfo) -+{ -+ pBankInfo->memoryType = pDimmInfo->memoryType; -+ -+ /* DIMM dimensions */ -+ pBankInfo->numOfRowAddr = pDimmInfo->numOfRowAddr; -+ pBankInfo->numOfColAddr = pDimmInfo->numOfColAddr; -+ pBankInfo->dataWidth = pDimmInfo->dataWidth; -+ pBankInfo->errorCheckType = pDimmInfo->errorCheckType; -+ pBankInfo->sdramWidth = pDimmInfo->sdramWidth; -+ pBankInfo->errorCheckDataWidth = pDimmInfo->errorCheckDataWidth; -+ pBankInfo->numOfBanksOnEachDevice = pDimmInfo->numOfBanksOnEachDevice; -+ pBankInfo->suportedCasLatencies = pDimmInfo->suportedCasLatencies; -+ pBankInfo->refreshInterval = pDimmInfo->refreshInterval; -+ -+ /* DIMM timing parameters */ -+ pBankInfo->minCycleTimeAtMaxCasLatPs = pDimmInfo->minCycleTimeAtMaxCasLatPs; -+ pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps = -+ pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps; -+ pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps = -+ pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps; -+ -+ pBankInfo->minRowPrechargeTime = pDimmInfo->minRowPrechargeTime; -+ pBankInfo->minRowActiveToRowActive = pDimmInfo->minRowActiveToRowActive; -+ pBankInfo->minRasToCasDelay = pDimmInfo->minRasToCasDelay; -+ pBankInfo->minRasPulseWidth = pDimmInfo->minRasPulseWidth; -+ pBankInfo->minWriteRecoveryTime = pDimmInfo->minWriteRecoveryTime; -+ pBankInfo->minWriteToReadCmdDelay = pDimmInfo->minWriteToReadCmdDelay; -+ pBankInfo->minReadToPrechCmdDelay = pDimmInfo->minReadToPrechCmdDelay; -+ pBankInfo->minRefreshToActiveCmd = pDimmInfo->minRefreshToActiveCmd; -+ -+ /* Parameters calculated from the extracted DIMM information */ -+ pBankInfo->size = pDimmInfo->size/pDimmInfo->numOfModuleBanks; -+ pBankInfo->deviceDensity = pDimmInfo->deviceDensity; -+ pBankInfo->numberOfDevices = pDimmInfo->numberOfDevices / -+ pDimmInfo->numOfModuleBanks; -+ -+ /* DIMM attributes (MV_TRUE for yes) */ -+ -+ if ((pDimmInfo->memoryType == MEM_TYPE_SDRAM) || -+ (pDimmInfo->memoryType == MEM_TYPE_DDR1) ) -+ { -+ if (pDimmInfo->dimmAttributes & BIT1) -+ pBankInfo->registeredAddrAndControlInputs = MV_TRUE; -+ else -+ pBankInfo->registeredAddrAndControlInputs = MV_FALSE; -+ } -+ else /* pDimmInfo->memoryType == MEM_TYPE_DDR2 */ -+ { -+ if (pDimmInfo->dimmTypeInfo & (BIT0 | BIT4)) -+ pBankInfo->registeredAddrAndControlInputs = MV_TRUE; -+ else -+ pBankInfo->registeredAddrAndControlInputs = MV_FALSE; -+ } -+ -+ return; -+} -+ -+/******************************************************************************* -+* dimmSpdCpy - Cpy SPD parameters from dimm 0 to dimm 1. -+* -+* DESCRIPTION: -+* Read the DIMM SPD parameters from dimm 0 into dimm 1 SPD. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+MV_STATUS dimmSpdCpy(MV_VOID) -+{ -+ MV_U32 i; -+ MV_U32 spdChecksum; -+ -+ MV_TWSI_SLAVE twsiSlave; -+ MV_U8 data[SPD_SIZE]; -+ -+ /* zero dimmInfo structure */ -+ memset(data, 0, SPD_SIZE); -+ -+ /* read the dimm eeprom */ -+ DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); -+ twsiSlave.slaveAddr.address = MV_BOARD_DIMM0_I2C_ADDR; -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ twsiSlave.offset = 0; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, -+ &twsiSlave, data, SPD_SIZE) ) -+ { -+ DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 0\n")); -+ return MV_FAIL; -+ } -+ DB(puts("DRAM: Reading dimm info succeded.\n")); -+ -+ /* calculate SPD checksum */ -+ spdChecksum = 0; -+ -+ for(i = 0 ; i <= 62 ; i++) -+ { -+ spdChecksum += data[i]; -+ } -+ -+ if ((spdChecksum & 0xff) != data[63]) -+ { -+ DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", -+ (MV_U32)(spdChecksum & 0xff), data[63])); -+ } -+ else -+ { -+ DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); -+ } -+ -+ /* copy the SPD content 1:1 into the DIMM 1 SPD */ -+ twsiSlave.slaveAddr.address = MV_BOARD_DIMM1_I2C_ADDR; -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ twsiSlave.offset = 0; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ for(i = 0 ; i < SPD_SIZE ; i++) -+ { -+ twsiSlave.offset = i; -+ if( MV_OK != mvTwsiWrite (MV_BOARD_DIMM_I2C_CHANNEL, -+ &twsiSlave, &data[i], 1) ) -+ { -+ mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 1 byte %d \n",i); -+ return MV_FAIL; -+ } -+ mvOsDelay(5); -+ } -+ -+ DB(puts("DRAM: Reading dimm info succeded.\n")); -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* dimmSpdGet - Get the SPD parameters. -+* -+* DESCRIPTION: -+* Read the DIMM SPD parameters into given struct parameter. -+* -+* INPUT: -+* dimmNum - DIMM number. See MV_BOARD_DIMM_NUM enumerator. -+* -+* OUTPUT: -+* pDimmInfo - DIMM information structure. -+* -+* RETURN: -+* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo) -+{ -+ MV_U32 i; -+ MV_U32 density = 1; -+ MV_U32 spdChecksum; -+ -+ MV_TWSI_SLAVE twsiSlave; -+ MV_U8 data[SPD_SIZE]; -+ -+ if((NULL == pDimmInfo)|| (dimmNum >= MAX_DIMM_NUM)) -+ { -+ DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); -+ return MV_BAD_PARAM; -+ } -+ -+ /* zero dimmInfo structure */ -+ memset(data, 0, SPD_SIZE); -+ -+ /* read the dimm eeprom */ -+ DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); -+ twsiSlave.slaveAddr.address = (dimmNum == 0) ? -+ MV_BOARD_DIMM0_I2C_ADDR : MV_BOARD_DIMM1_I2C_ADDR; -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ twsiSlave.offset = 0; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, -+ &twsiSlave, data, SPD_SIZE) ) -+ { -+ DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum %d \n", dimmNum)); -+ return MV_FAIL; -+ } -+ DB(puts("DRAM: Reading dimm info succeded.\n")); -+ -+ /* calculate SPD checksum */ -+ spdChecksum = 0; -+ -+ for(i = 0 ; i <= 62 ; i++) -+ { -+ spdChecksum += data[i]; -+ } -+ -+ if ((spdChecksum & 0xff) != data[63]) -+ { -+ DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", -+ (MV_U32)(spdChecksum & 0xff), data[63])); -+ } -+ else -+ { -+ DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); -+ } -+ -+ /* copy the SPD content 1:1 into the dimmInfo structure*/ -+ for(i = 0 ; i < SPD_SIZE ; i++) -+ { -+ pDimmInfo->spdRawData[i] = data[i]; -+ DB(mvOsPrintf("SPD-EEPROM Byte %3d = %3x (%3d)\n",i, data[i], data[i])); -+ } -+ -+ DB(mvOsPrintf("DRAM SPD Information:\n")); -+ -+ /* Memory type (DDR / SDRAM) */ -+ switch (data[DIMM_MEM_TYPE]) -+ { -+ case (DIMM_MEM_TYPE_SDRAM): -+ pDimmInfo->memoryType = MEM_TYPE_SDRAM; -+ DB(mvOsPrintf("DRAM Memeory type SDRAM\n")); -+ break; -+ case (DIMM_MEM_TYPE_DDR1): -+ pDimmInfo->memoryType = MEM_TYPE_DDR1; -+ DB(mvOsPrintf("DRAM Memeory type DDR1\n")); -+ break; -+ case (DIMM_MEM_TYPE_DDR2): -+ pDimmInfo->memoryType = MEM_TYPE_DDR2; -+ DB(mvOsPrintf("DRAM Memeory type DDR2\n")); -+ break; -+ default: -+ mvOsPrintf("ERROR: Undefined memory type!\n"); -+ return MV_ERROR; -+ } -+ -+ -+ /* Number Of Row Addresses */ -+ pDimmInfo->numOfRowAddr = data[DIMM_ROW_NUM]; -+ DB(mvOsPrintf("DRAM numOfRowAddr[3] %d\n",pDimmInfo->numOfRowAddr)); -+ -+ /* Number Of Column Addresses */ -+ pDimmInfo->numOfColAddr = data[DIMM_COL_NUM]; -+ DB(mvOsPrintf("DRAM numOfColAddr[4] %d\n",pDimmInfo->numOfColAddr)); -+ -+ /* Number Of Module Banks */ -+ pDimmInfo->numOfModuleBanks = data[DIMM_MODULE_BANK_NUM]; -+ DB(mvOsPrintf("DRAM numOfModuleBanks[5] 0x%x\n", -+ pDimmInfo->numOfModuleBanks)); -+ -+ /* Number of module banks encoded differently for DDR2 */ -+ if (pDimmInfo->memoryType == MEM_TYPE_DDR2) -+ pDimmInfo->numOfModuleBanks = (pDimmInfo->numOfModuleBanks & 0x7)+1; -+ -+ /* Data Width */ -+ pDimmInfo->dataWidth = data[DIMM_DATA_WIDTH]; -+ DB(mvOsPrintf("DRAM dataWidth[6] 0x%x\n", pDimmInfo->dataWidth)); -+ -+ /* Minimum Cycle Time At Max CasLatancy */ -+ pDimmInfo->minCycleTimeAtMaxCasLatPs = cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS]); -+ -+ /* Error Check Type */ -+ pDimmInfo->errorCheckType = data[DIMM_ERR_CHECK_TYPE]; -+ DB(mvOsPrintf("DRAM errorCheckType[11] 0x%x\n", -+ pDimmInfo->errorCheckType)); -+ -+ /* Refresh Interval */ -+ pDimmInfo->refreshInterval = data[DIMM_REFRESH_INTERVAL]; -+ DB(mvOsPrintf("DRAM refreshInterval[12] 0x%x\n", -+ pDimmInfo->refreshInterval)); -+ -+ /* Sdram Width */ -+ pDimmInfo->sdramWidth = data[DIMM_SDRAM_WIDTH]; -+ DB(mvOsPrintf("DRAM sdramWidth[13] 0x%x\n",pDimmInfo->sdramWidth)); -+ -+ /* Error Check Data Width */ -+ pDimmInfo->errorCheckDataWidth = data[DIMM_ERR_CHECK_DATA_WIDTH]; -+ DB(mvOsPrintf("DRAM errorCheckDataWidth[14] 0x%x\n", -+ pDimmInfo->errorCheckDataWidth)); -+ -+ /* Burst Length Supported */ -+ /* SDRAM/DDR1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * -+ *********************************************************/ -+ /* DDR2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * -+ *********************************************************/ -+ -+ pDimmInfo->burstLengthSupported = data[DIMM_BURST_LEN_SUP]; -+ DB(mvOsPrintf("DRAM burstLengthSupported[16] 0x%x\n", -+ pDimmInfo->burstLengthSupported)); -+ -+ /* Number Of Banks On Each Device */ -+ pDimmInfo->numOfBanksOnEachDevice = data[DIMM_DEV_BANK_NUM]; -+ DB(mvOsPrintf("DRAM numOfBanksOnEachDevice[17] 0x%x\n", -+ pDimmInfo->numOfBanksOnEachDevice)); -+ -+ /* Suported Cas Latencies */ -+ -+ /* SDRAM: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * -+ ********************************************************/ -+ -+ /* DDR 1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * -+ *********************************************************/ -+ -+ /* DDR 2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * -+ *********************************************************/ -+ -+ pDimmInfo->suportedCasLatencies = data[DIMM_SUP_CAL]; -+ DB(mvOsPrintf("DRAM suportedCasLatencies[18] 0x%x\n", -+ pDimmInfo->suportedCasLatencies)); -+ -+ /* For DDR2 only, get the DIMM type information */ -+ if (pDimmInfo->memoryType == MEM_TYPE_DDR2) -+ { -+ pDimmInfo->dimmTypeInfo = data[DIMM_DDR2_TYPE_INFORMATION]; -+ DB(mvOsPrintf("DRAM dimmTypeInfo[20] (DDR2) 0x%x\n", -+ pDimmInfo->dimmTypeInfo)); -+ } -+ -+ /* SDRAM Modules Attributes */ -+ pDimmInfo->dimmAttributes = data[DIMM_BUF_ADDR_CONT_IN]; -+ DB(mvOsPrintf("DRAM dimmAttributes[21] 0x%x\n", -+ pDimmInfo->dimmAttributes)); -+ -+ /* Minimum Cycle Time At Max CasLatancy Minus 1*/ -+ pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps = -+ cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS1]); -+ -+ /* Minimum Cycle Time At Max CasLatancy Minus 2*/ -+ pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps = -+ cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS2]); -+ -+ pDimmInfo->minRowPrechargeTime = data[DIMM_MIN_ROW_PRECHARGE_TIME]; -+ DB(mvOsPrintf("DRAM minRowPrechargeTime[27] 0x%x\n", -+ pDimmInfo->minRowPrechargeTime)); -+ pDimmInfo->minRowActiveToRowActive = data[DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE]; -+ DB(mvOsPrintf("DRAM minRowActiveToRowActive[28] 0x%x\n", -+ pDimmInfo->minRowActiveToRowActive)); -+ pDimmInfo->minRasToCasDelay = data[DIMM_MIN_RAS_TO_CAS_DELAY]; -+ DB(mvOsPrintf("DRAM minRasToCasDelay[29] 0x%x\n", -+ pDimmInfo->minRasToCasDelay)); -+ pDimmInfo->minRasPulseWidth = data[DIMM_MIN_RAS_PULSE_WIDTH]; -+ DB(mvOsPrintf("DRAM minRasPulseWidth[30] 0x%x\n", -+ pDimmInfo->minRasPulseWidth)); -+ -+ /* DIMM Bank Density */ -+ pDimmInfo->dimmBankDensity = data[DIMM_BANK_DENSITY]; -+ DB(mvOsPrintf("DRAM dimmBankDensity[31] 0x%x\n", -+ pDimmInfo->dimmBankDensity)); -+ -+ /* Only DDR2 includes Write Recovery Time field. Other SDRAM ignore */ -+ pDimmInfo->minWriteRecoveryTime = data[DIMM_MIN_WRITE_RECOVERY_TIME]; -+ DB(mvOsPrintf("DRAM minWriteRecoveryTime[36] 0x%x\n", -+ pDimmInfo->minWriteRecoveryTime)); -+ -+ /* Only DDR2 includes Internal Write To Read Command Delay field. */ -+ pDimmInfo->minWriteToReadCmdDelay = data[DIMM_MIN_WRITE_TO_READ_CMD_DELAY]; -+ DB(mvOsPrintf("DRAM minWriteToReadCmdDelay[37] 0x%x\n", -+ pDimmInfo->minWriteToReadCmdDelay)); -+ -+ /* Only DDR2 includes Internal Read To Precharge Command Delay field. */ -+ pDimmInfo->minReadToPrechCmdDelay = data[DIMM_MIN_READ_TO_PRECH_CMD_DELAY]; -+ DB(mvOsPrintf("DRAM minReadToPrechCmdDelay[38] 0x%x\n", -+ pDimmInfo->minReadToPrechCmdDelay)); -+ -+ /* Only DDR2 includes Minimum Refresh to Activate/Refresh Command field */ -+ pDimmInfo->minRefreshToActiveCmd = data[DIMM_MIN_REFRESH_TO_ACTIVATE_CMD]; -+ DB(mvOsPrintf("DRAM minRefreshToActiveCmd[42] 0x%x\n", -+ pDimmInfo->minRefreshToActiveCmd)); -+ -+ /* calculating the sdram density. Representing device density from */ -+ /* bit 20 to allow representation of 4GB and above. */ -+ /* For example, if density is 512Mbit 0x20000000, will be represent in */ -+ /* deviceDensity by 0x20000000 >> 16 --> 0x00000200. Another example */ -+ /* is density 8GB 0x200000000 >> 16 --> 0x00002000. */ -+ density = (1 << ((pDimmInfo->numOfRowAddr + pDimmInfo->numOfColAddr) - 20)); -+ pDimmInfo->deviceDensity = density * -+ pDimmInfo->numOfBanksOnEachDevice * -+ pDimmInfo->sdramWidth; -+ DB(mvOsPrintf("DRAM deviceDensity %d\n",pDimmInfo->deviceDensity)); -+ -+ /* Number of devices includeing Error correction */ -+ pDimmInfo->numberOfDevices = (pDimmInfo->dataWidth/pDimmInfo->sdramWidth) * -+ pDimmInfo->numOfModuleBanks; -+ DB(mvOsPrintf("DRAM numberOfDevices %d\n", -+ pDimmInfo->numberOfDevices)); -+ -+ pDimmInfo->size = 0; -+ -+ /* Note that pDimmInfo->size is in MB units */ -+ if (pDimmInfo->memoryType == MEM_TYPE_SDRAM) -+ { -+ if (pDimmInfo->dimmBankDensity & BIT0) -+ pDimmInfo->size += 1024; /* Equal to 1GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT1) -+ pDimmInfo->size += 8; /* Equal to 8MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT2) -+ pDimmInfo->size += 16; /* Equal to 16MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT3) -+ pDimmInfo->size += 32; /* Equal to 32MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT4) -+ pDimmInfo->size += 64; /* Equal to 64MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT5) -+ pDimmInfo->size += 128; /* Equal to 128MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT6) -+ pDimmInfo->size += 256; /* Equal to 256MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT7) -+ pDimmInfo->size += 512; /* Equal to 512MB */ -+ } -+ else if (pDimmInfo->memoryType == MEM_TYPE_DDR1) -+ { -+ if (pDimmInfo->dimmBankDensity & BIT0) -+ pDimmInfo->size += 1024; /* Equal to 1GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT1) -+ pDimmInfo->size += 2048; /* Equal to 2GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT2) -+ pDimmInfo->size += 16; /* Equal to 16MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT3) -+ pDimmInfo->size += 32; /* Equal to 32MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT4) -+ pDimmInfo->size += 64; /* Equal to 64MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT5) -+ pDimmInfo->size += 128; /* Equal to 128MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT6) -+ pDimmInfo->size += 256; /* Equal to 256MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT7) -+ pDimmInfo->size += 512; /* Equal to 512MB */ -+ } -+ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ -+ { -+ if (pDimmInfo->dimmBankDensity & BIT0) -+ pDimmInfo->size += 1024; /* Equal to 1GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT1) -+ pDimmInfo->size += 2048; /* Equal to 2GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT2) -+ pDimmInfo->size += 4096; /* Equal to 4GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT3) -+ pDimmInfo->size += 8192; /* Equal to 8GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT4) -+ pDimmInfo->size += 16384; /* Equal to 16GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT5) -+ pDimmInfo->size += 128; /* Equal to 128MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT6) -+ pDimmInfo->size += 256; /* Equal to 256MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT7) -+ pDimmInfo->size += 512; /* Equal to 512MB */ -+ } -+ -+ pDimmInfo->size *= pDimmInfo->numOfModuleBanks; -+ -+ DB(mvOsPrintf("Dram: dimm size %dMB \n",pDimmInfo->size)); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* dimmSpdPrint - Print the SPD parameters. -+* -+* DESCRIPTION: -+* Print the Dimm SPD parameters. -+* -+* INPUT: -+* pDimmInfo - DIMM information structure. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID dimmSpdPrint(MV_U32 dimmNum) -+{ -+ MV_DIMM_INFO dimmInfo; -+ MV_U32 i, temp = 0; -+ MV_U32 k, maskLeftOfPoint = 0, maskRightOfPoint = 0; -+ MV_U32 rightOfPoint = 0,leftOfPoint = 0, div, time_tmp, shift; -+ MV_U32 busClkPs; -+ MV_U8 trp_clocks=0, trcd_clocks, tras_clocks, trrd_clocks, -+ temp_buf[40], *spdRawData; -+ -+ busClkPs = 1000000000 / (mvBoardSysClkGet() / 100); /* in 10 ps units */ -+ -+ spdRawData = dimmInfo.spdRawData; -+ -+ if(MV_OK != dimmSpdGet(dimmNum, &dimmInfo)) -+ { -+ mvOsOutput("ERROR: Could not read SPD information!\n"); -+ return; -+ } -+ -+ /* find Manufactura of Dimm Module */ -+ mvOsOutput("\nManufacturer's JEDEC ID Code: "); -+ for(i = 0 ; i < DIMM_MODULE_MANU_SIZE ; i++) -+ { -+ mvOsOutput("%x",spdRawData[DIMM_MODULE_MANU_OFFS + i]); -+ } -+ mvOsOutput("\n"); -+ -+ /* Manufacturer's Specific Data */ -+ for(i = 0 ; i < DIMM_MODULE_ID_SIZE ; i++) -+ { -+ temp_buf[i] = spdRawData[DIMM_MODULE_ID_OFFS + i]; -+ } -+ mvOsOutput("Manufacturer's Specific Data: %s\n", temp_buf); -+ -+ /* Module Part Number */ -+ for(i = 0 ; i < DIMM_MODULE_VEN_SIZE ; i++) -+ { -+ temp_buf[i] = spdRawData[DIMM_MODULE_VEN_OFFS + i]; -+ } -+ mvOsOutput("Module Part Number: %s\n", temp_buf); -+ -+ /* Module Serial Number */ -+ for(i = 0; i < sizeof(MV_U32); i++) -+ { -+ temp |= spdRawData[95+i] << 8*i; -+ } -+ mvOsOutput("DIMM Serial No. %ld (%lx)\n", (long)temp, -+ (long)temp); -+ -+ /* find Manufac-Data of Dimm Module */ -+ mvOsOutput("Manufactoring Date: Year 20%d%d/ ww %d%d\n", -+ ((spdRawData[93] & 0xf0) >> 4), (spdRawData[93] & 0xf), -+ ((spdRawData[94] & 0xf0) >> 4), (spdRawData[94] & 0xf)); -+ /* find modul_revision of Dimm Module */ -+ mvOsOutput("Module Revision: %d.%d\n", -+ spdRawData[91], spdRawData[92]); -+ -+ /* find manufac_place of Dimm Module */ -+ mvOsOutput("manufac_place: %d\n", spdRawData[72]); -+ -+ /* go over the first 35 I2C data bytes */ -+ for(i = 2 ; i <= 35 ; i++) -+ switch(i) -+ { -+ case 2: /* Memory type (DDR1/2 / SDRAM) */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ mvOsOutput("Dram Type is: SDRAM\n"); -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ mvOsOutput("Dram Type is: SDRAM DDR1\n"); -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) -+ mvOsOutput("Dram Type is: SDRAM DDR2\n"); -+ else -+ mvOsOutput("Dram Type unknown\n"); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 3: /* Number Of Row Addresses */ -+ mvOsOutput("Module Number of row addresses: %d\n", -+ dimmInfo.numOfRowAddr); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 4: /* Number Of Column Addresses */ -+ mvOsOutput("Module Number of col addresses: %d\n", -+ dimmInfo.numOfColAddr); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 5: /* Number Of Module Banks */ -+ mvOsOutput("Number of Banks on Mod.: %d\n", -+ dimmInfo.numOfModuleBanks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 6: /* Data Width */ -+ mvOsOutput("Module Data Width: %d bit\n", -+ dimmInfo.dataWidth); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 8: /* Voltage Interface */ -+ switch(spdRawData[i]) -+ { -+ case 0x0: -+ mvOsOutput("Module is TTL_5V_TOLERANT\n"); -+ break; -+ case 0x1: -+ mvOsOutput("Module is LVTTL\n"); -+ break; -+ case 0x2: -+ mvOsOutput("Module is HSTL_1_5V\n"); -+ break; -+ case 0x3: -+ mvOsOutput("Module is SSTL_3_3V\n"); -+ break; -+ case 0x4: -+ mvOsOutput("Module is SSTL_2_5V\n"); -+ break; -+ case 0x5: -+ if (dimmInfo.memoryType != MEM_TYPE_SDRAM) -+ { -+ mvOsOutput("Module is SSTL_1_8V\n"); -+ break; -+ } -+ default: -+ mvOsOutput("Module is VOLTAGE_UNKNOWN\n"); -+ break; -+ } -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 9: /* Minimum Cycle Time At Max CasLatancy */ -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ rightOfPoint = (spdRawData[i] & 0x0f) * 10; -+ -+ /* DDR2 addition of right of point */ -+ if ((spdRawData[i] & 0x0f) == 0xA) -+ { -+ rightOfPoint = 25; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xB) -+ { -+ rightOfPoint = 33; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xC) -+ { -+ rightOfPoint = 66; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xD) -+ { -+ rightOfPoint = 75; -+ } -+ mvOsOutput("Minimum Cycle Time At Max CL: %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 10: /* Clock To Data Out */ -+ div = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 10:100; -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / div; -+ rightOfPoint = time_tmp % div; -+ mvOsOutput("Clock To Data Out: %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 11: /* Error Check Type */ -+ mvOsOutput("Error Check Type (0=NONE): %d\n", -+ dimmInfo.errorCheckType); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 12: /* Refresh Interval */ -+ mvOsOutput("Refresh Rate: %x\n", -+ dimmInfo.refreshInterval); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 13: /* Sdram Width */ -+ mvOsOutput("Sdram Width: %d bits\n", -+ dimmInfo.sdramWidth); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 14: /* Error Check Data Width */ -+ mvOsOutput("Error Check Data Width: %d bits\n", -+ dimmInfo.errorCheckDataWidth); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 15: /* Minimum Clock Delay is unsupported */ -+ if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || -+ (dimmInfo.memoryType == MEM_TYPE_DDR1)) -+ { -+ mvOsOutput("Minimum Clk Delay back to back: %d\n", -+ spdRawData[i]); -+ } -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 16: /* Burst Length Supported */ -+ /* SDRAM/DDR1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * -+ *********************************************************/ -+ /* DDR2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * -+ *********************************************************/ -+ mvOsOutput("Burst Length Supported: "); -+ if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || -+ (dimmInfo.memoryType == MEM_TYPE_DDR1)) -+ { -+ if (dimmInfo.burstLengthSupported & BIT0) -+ mvOsOutput("1, "); -+ if (dimmInfo.burstLengthSupported & BIT1) -+ mvOsOutput("2, "); -+ } -+ if (dimmInfo.burstLengthSupported & BIT2) -+ mvOsOutput("4, "); -+ if (dimmInfo.burstLengthSupported & BIT3) -+ mvOsOutput("8, "); -+ -+ mvOsOutput(" Bit \n"); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 17: /* Number Of Banks On Each Device */ -+ mvOsOutput("Number Of Banks On Each Chip: %d\n", -+ dimmInfo.numOfBanksOnEachDevice); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 18: /* Suported Cas Latencies */ -+ -+ /* SDRAM: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * -+ ********************************************************/ -+ -+ /* DDR 1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * -+ *********************************************************/ -+ -+ /* DDR 2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * -+ *********************************************************/ -+ -+ mvOsOutput("Suported Cas Latencies: (CL) "); -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ for (k = 0; k <=7; k++) -+ { -+ if (dimmInfo.suportedCasLatencies & (1 << k)) -+ mvOsOutput("%d, ", k+1); -+ } -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ { -+ if (dimmInfo.suportedCasLatencies & BIT0) -+ mvOsOutput("1, "); -+ if (dimmInfo.suportedCasLatencies & BIT1) -+ mvOsOutput("1.5, "); -+ if (dimmInfo.suportedCasLatencies & BIT2) -+ mvOsOutput("2, "); -+ if (dimmInfo.suportedCasLatencies & BIT3) -+ mvOsOutput("2.5, "); -+ if (dimmInfo.suportedCasLatencies & BIT4) -+ mvOsOutput("3, "); -+ if (dimmInfo.suportedCasLatencies & BIT5) -+ mvOsOutput("3.5, "); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) -+ { -+ if (dimmInfo.suportedCasLatencies & BIT2) -+ mvOsOutput("2, "); -+ if (dimmInfo.suportedCasLatencies & BIT3) -+ mvOsOutput("3, "); -+ if (dimmInfo.suportedCasLatencies & BIT4) -+ mvOsOutput("4, "); -+ if (dimmInfo.suportedCasLatencies & BIT5) -+ mvOsOutput("5, "); -+ } -+ else -+ mvOsOutput("?.?, "); -+ mvOsOutput("\n"); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 20: /* DDR2 DIMM type info */ -+ if (dimmInfo.memoryType == MEM_TYPE_DDR2) -+ { -+ if (dimmInfo.dimmTypeInfo & (BIT0 | BIT4)) -+ mvOsOutput("Registered DIMM (RDIMM)\n"); -+ else if (dimmInfo.dimmTypeInfo & (BIT1 | BIT5)) -+ mvOsOutput("Unbuffered DIMM (UDIMM)\n"); -+ else -+ mvOsOutput("Unknown DIMM type.\n"); -+ } -+ -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 21: /* SDRAM Modules Attributes */ -+ mvOsOutput("\nModule Attributes (SPD Byte 21): \n"); -+ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ if (dimmInfo.dimmAttributes & BIT0) -+ mvOsOutput(" Buffered Addr/Control Input: Yes\n"); -+ else -+ mvOsOutput(" Buffered Addr/Control Input: No\n"); -+ -+ if (dimmInfo.dimmAttributes & BIT1) -+ mvOsOutput(" Registered Addr/Control Input: Yes\n"); -+ else -+ mvOsOutput(" Registered Addr/Control Input: No\n"); -+ -+ if (dimmInfo.dimmAttributes & BIT2) -+ mvOsOutput(" On-Card PLL (clock): Yes \n"); -+ else -+ mvOsOutput(" On-Card PLL (clock): No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT3) -+ mvOsOutput(" Bufferd DQMB Input: Yes \n"); -+ else -+ mvOsOutput(" Bufferd DQMB Inputs: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT4) -+ mvOsOutput(" Registered DQMB Inputs: Yes \n"); -+ else -+ mvOsOutput(" Registered DQMB Inputs: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT5) -+ mvOsOutput(" Differential Clock Input: Yes \n"); -+ else -+ mvOsOutput(" Differential Clock Input: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT6) -+ mvOsOutput(" redundant Row Addressing: Yes \n"); -+ else -+ mvOsOutput(" redundant Row Addressing: No \n"); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ { -+ if (dimmInfo.dimmAttributes & BIT0) -+ mvOsOutput(" Buffered Addr/Control Input: Yes\n"); -+ else -+ mvOsOutput(" Buffered Addr/Control Input: No\n"); -+ -+ if (dimmInfo.dimmAttributes & BIT1) -+ mvOsOutput(" Registered Addr/Control Input: Yes\n"); -+ else -+ mvOsOutput(" Registered Addr/Control Input: No\n"); -+ -+ if (dimmInfo.dimmAttributes & BIT2) -+ mvOsOutput(" On-Card PLL (clock): Yes \n"); -+ else -+ mvOsOutput(" On-Card PLL (clock): No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT3) -+ mvOsOutput(" FET Switch On-Card Enabled: Yes \n"); -+ else -+ mvOsOutput(" FET Switch On-Card Enabled: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT4) -+ mvOsOutput(" FET Switch External Enabled: Yes \n"); -+ else -+ mvOsOutput(" FET Switch External Enabled: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT5) -+ mvOsOutput(" Differential Clock Input: Yes \n"); -+ else -+ mvOsOutput(" Differential Clock Input: No \n"); -+ } -+ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ -+ { -+ mvOsOutput(" Number of Active Registers on the DIMM: %d\n", -+ (dimmInfo.dimmAttributes & 0x3) + 1); -+ -+ mvOsOutput(" Number of PLLs on the DIMM: %d\n", -+ ((dimmInfo.dimmAttributes) >> 2) & 0x3); -+ -+ if (dimmInfo.dimmAttributes & BIT4) -+ mvOsOutput(" FET Switch External Enabled: Yes \n"); -+ else -+ mvOsOutput(" FET Switch External Enabled: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT6) -+ mvOsOutput(" Analysis probe installed: Yes \n"); -+ else -+ mvOsOutput(" Analysis probe installed: No \n"); -+ } -+ -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 22: /* Suported AutoPreCharge */ -+ mvOsOutput("\nModul Attributes (SPD Byte 22): \n"); -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ if ( spdRawData[i] & BIT0 ) -+ mvOsOutput(" Early Ras Precharge: Yes \n"); -+ else -+ mvOsOutput(" Early Ras Precharge: No \n"); -+ -+ if ( spdRawData[i] & BIT1 ) -+ mvOsOutput(" AutoPreCharge: Yes \n"); -+ else -+ mvOsOutput(" AutoPreCharge: No \n"); -+ -+ if ( spdRawData[i] & BIT2 ) -+ mvOsOutput(" Precharge All: Yes \n"); -+ else -+ mvOsOutput(" Precharge All: No \n"); -+ -+ if ( spdRawData[i] & BIT3 ) -+ mvOsOutput(" Write 1/ReadBurst: Yes \n"); -+ else -+ mvOsOutput(" Write 1/ReadBurst: No \n"); -+ -+ if ( spdRawData[i] & BIT4 ) -+ mvOsOutput(" lower VCC tolerance: 5%%\n"); -+ else -+ mvOsOutput(" lower VCC tolerance: 10%%\n"); -+ -+ if ( spdRawData[i] & BIT5 ) -+ mvOsOutput(" upper VCC tolerance: 5%%\n"); -+ else -+ mvOsOutput(" upper VCC tolerance: 10%%\n"); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ { -+ if ( spdRawData[i] & BIT0 ) -+ mvOsOutput(" Supports Weak Driver: Yes \n"); -+ else -+ mvOsOutput(" Supports Weak Driver: No \n"); -+ -+ if ( !(spdRawData[i] & BIT4) ) -+ mvOsOutput(" lower VCC tolerance: 0.2V\n"); -+ -+ if ( !(spdRawData[i] & BIT5) ) -+ mvOsOutput(" upper VCC tolerance: 0.2V\n"); -+ -+ if ( spdRawData[i] & BIT6 ) -+ mvOsOutput(" Concurrent Auto Preharge: Yes \n"); -+ else -+ mvOsOutput(" Concurrent Auto Preharge: No \n"); -+ -+ if ( spdRawData[i] & BIT7 ) -+ mvOsOutput(" Supports Fast AP: Yes \n"); -+ else -+ mvOsOutput(" Supports Fast AP: No \n"); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) -+ { -+ if ( spdRawData[i] & BIT0 ) -+ mvOsOutput(" Supports Weak Driver: Yes \n"); -+ else -+ mvOsOutput(" Supports Weak Driver: No \n"); -+ } -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 23: -+ /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */ -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ rightOfPoint = (spdRawData[i] & 0x0f) * 10; -+ -+ /* DDR2 addition of right of point */ -+ if ((spdRawData[i] & 0x0f) == 0xA) -+ { -+ rightOfPoint = 25; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xB) -+ { -+ rightOfPoint = 33; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xC) -+ { -+ rightOfPoint = 66; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xD) -+ { -+ rightOfPoint = 75; -+ } -+ -+ mvOsOutput("Minimum Cycle Time At 2nd highest CasLatancy" -+ "(0 = Not supported): %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint ); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 24: /* Clock To Data Out 2nd highest Cas Latency Value*/ -+ div = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? 10:100; -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / div; -+ rightOfPoint = time_tmp % div; -+ mvOsOutput("Clock To Data Out (2nd CL value): %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 25: -+ /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ leftOfPoint = (spdRawData[i] & 0xfc) >> 2; -+ rightOfPoint = (spdRawData[i] & 0x3) * 25; -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ rightOfPoint = (spdRawData[i] & 0x0f) * 10; -+ -+ /* DDR2 addition of right of point */ -+ if ((spdRawData[i] & 0x0f) == 0xA) -+ { -+ rightOfPoint = 25; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xB) -+ { -+ rightOfPoint = 33; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xC) -+ { -+ rightOfPoint = 66; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xD) -+ { -+ rightOfPoint = 75; -+ } -+ } -+ mvOsOutput("Minimum Cycle Time At 3rd highest CasLatancy" -+ "(0 = Not supported): %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint ); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 26: /* Clock To Data Out 3rd highest Cas Latency Value*/ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ leftOfPoint = (spdRawData[i] & 0xfc) >> 2; -+ rightOfPoint = (spdRawData[i] & 0x3) * 25; -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = 0; -+ rightOfPoint = time_tmp; -+ } -+ mvOsOutput("Clock To Data Out (3rd CL value): %d.%2d[ns]\n", -+ leftOfPoint, rightOfPoint ); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 27: /* Minimum Row Precharge Time */ -+ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; -+ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0xff : 0xfc; -+ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0x00 : 0x03; -+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); -+ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; -+ temp = ((leftOfPoint*100) + rightOfPoint);/* in 10ps Intervals*/ -+ trp_clocks = (temp + (busClkPs-1)) / busClkPs; -+ mvOsOutput("Minimum Row Precharge Time [ns]: %d.%d = " -+ "in Clk cycles %d\n", -+ leftOfPoint, rightOfPoint, trp_clocks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 28: /* Minimum Row Active to Row Active Time */ -+ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; -+ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0xff : 0xfc; -+ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0x00 : 0x03; -+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); -+ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; -+ temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ -+ trrd_clocks = (temp + (busClkPs-1)) / busClkPs; -+ mvOsOutput("Minimum Row Active -To- Row Active Delay [ns]: " -+ "%d.%d = in Clk cycles %d\n", -+ leftOfPoint, rightOfPoint, trp_clocks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 29: /* Minimum Ras-To-Cas Delay */ -+ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; -+ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0xff : 0xfc; -+ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0x00 : 0x03; -+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); -+ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; -+ temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ -+ trcd_clocks = (temp + (busClkPs-1) )/ busClkPs; -+ mvOsOutput("Minimum Ras-To-Cas Delay [ns]: %d.%d = " -+ "in Clk cycles %d\n", -+ leftOfPoint, rightOfPoint, trp_clocks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 30: /* Minimum Ras Pulse Width */ -+ tras_clocks = (cas2ps(spdRawData[i])+(busClkPs-1)) / busClkPs; -+ mvOsOutput("Minimum Ras Pulse Width [ns]: %d = " -+ "in Clk cycles %d\n", spdRawData[i], tras_clocks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 31: /* Module Bank Density */ -+ mvOsOutput("Module Bank Density (more than 1= Multisize-Module):"); -+ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ if (dimmInfo.dimmBankDensity & BIT0) -+ mvOsOutput("1GB, "); -+ if (dimmInfo.dimmBankDensity & BIT1) -+ mvOsOutput("8MB, "); -+ if (dimmInfo.dimmBankDensity & BIT2) -+ mvOsOutput("16MB, "); -+ if (dimmInfo.dimmBankDensity & BIT3) -+ mvOsOutput("32MB, "); -+ if (dimmInfo.dimmBankDensity & BIT4) -+ mvOsOutput("64MB, "); -+ if (dimmInfo.dimmBankDensity & BIT5) -+ mvOsOutput("128MB, "); -+ if (dimmInfo.dimmBankDensity & BIT6) -+ mvOsOutput("256MB, "); -+ if (dimmInfo.dimmBankDensity & BIT7) -+ mvOsOutput("512MB, "); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ { -+ if (dimmInfo.dimmBankDensity & BIT0) -+ mvOsOutput("1GB, "); -+ if (dimmInfo.dimmBankDensity & BIT1) -+ mvOsOutput("2GB, "); -+ if (dimmInfo.dimmBankDensity & BIT2) -+ mvOsOutput("16MB, "); -+ if (dimmInfo.dimmBankDensity & BIT3) -+ mvOsOutput("32MB, "); -+ if (dimmInfo.dimmBankDensity & BIT4) -+ mvOsOutput("64MB, "); -+ if (dimmInfo.dimmBankDensity & BIT5) -+ mvOsOutput("128MB, "); -+ if (dimmInfo.dimmBankDensity & BIT6) -+ mvOsOutput("256MB, "); -+ if (dimmInfo.dimmBankDensity & BIT7) -+ mvOsOutput("512MB, "); -+ } -+ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ -+ { -+ if (dimmInfo.dimmBankDensity & BIT0) -+ mvOsOutput("1GB, "); -+ if (dimmInfo.dimmBankDensity & BIT1) -+ mvOsOutput("2GB, "); -+ if (dimmInfo.dimmBankDensity & BIT2) -+ mvOsOutput("4GB, "); -+ if (dimmInfo.dimmBankDensity & BIT3) -+ mvOsOutput("8GB, "); -+ if (dimmInfo.dimmBankDensity & BIT4) -+ mvOsOutput("16GB, "); -+ if (dimmInfo.dimmBankDensity & BIT5) -+ mvOsOutput("128MB, "); -+ if (dimmInfo.dimmBankDensity & BIT6) -+ mvOsOutput("256MB, "); -+ if (dimmInfo.dimmBankDensity & BIT7) -+ mvOsOutput("512MB, "); -+ } -+ mvOsOutput("\n"); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 32: /* Address And Command Setup Time (measured in ns/1000) */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ rightOfPoint = (spdRawData[i] & 0x0f); -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ if(leftOfPoint > 7) -+ { -+ leftOfPoint *= -1; -+ } -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / 100; -+ rightOfPoint = time_tmp % 100; -+ } -+ mvOsOutput("Address And Command Setup Time [ns]: %d.%d\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 33: /* Address And Command Hold Time */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ rightOfPoint = (spdRawData[i] & 0x0f); -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ if(leftOfPoint > 7) -+ { -+ leftOfPoint *= -1; -+ } -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / 100; -+ rightOfPoint = time_tmp % 100; -+ } -+ mvOsOutput("Address And Command Hold Time [ns]: %d.%d\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 34: /* Data Input Setup Time */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ rightOfPoint = (spdRawData[i] & 0x0f); -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ if(leftOfPoint > 7) -+ { -+ leftOfPoint *= -1; -+ } -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / 100; -+ rightOfPoint = time_tmp % 100; -+ } -+ mvOsOutput("Data Input Setup Time [ns]: %d.%d\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 35: /* Data Input Hold Time */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ rightOfPoint = (spdRawData[i] & 0x0f); -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ if(leftOfPoint > 7) -+ { -+ leftOfPoint *= -1; -+ } -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / 100; -+ rightOfPoint = time_tmp % 100; -+ } -+ mvOsOutput("Data Input Hold Time [ns]: %d.%d\n\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 36: /* Relevant for DDR2 only: Write Recovery Time */ -+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> 2); -+ rightOfPoint = (spdRawData[i] & maskRightOfPoint) * 25; -+ mvOsOutput("Write Recovery Time [ns]: %d.%d\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ } -+ -+} -+ -+ -+/* -+ * translate ns.ns/10 coding of SPD timing values -+ * into ps unit values -+ */ -+/******************************************************************************* -+* cas2ps - Translate x.y ns parameter to pico-seconds values -+* -+* DESCRIPTION: -+* This function translates x.y nano seconds to its value in pico seconds. -+* For example 3.75ns will return 3750. -+* -+* INPUT: -+* spd_byte - DIMM SPD byte. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* value in pico seconds. -+* -+*******************************************************************************/ -+static MV_U32 cas2ps(MV_U8 spd_byte) -+{ -+ MV_U32 ns, ns10; -+ -+ /* isolate upper nibble */ -+ ns = (spd_byte >> 4) & 0x0F; -+ /* isolate lower nibble */ -+ ns10 = (spd_byte & 0x0F); -+ -+ if( ns10 < 10 ) { -+ ns10 *= 10; -+ } -+ else if( ns10 == 10 ) -+ ns10 = 25; -+ else if( ns10 == 11 ) -+ ns10 = 33; -+ else if( ns10 == 12 ) -+ ns10 = 66; -+ else if( ns10 == 13 ) -+ ns10 = 75; -+ else -+ { -+ mvOsOutput("cas2ps Err. unsupported cycle time.\n"); -+ } -+ -+ return (ns*1000 + ns10*10); -+} -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,191 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvDram -+#define __INCmvDram -+ -+#include "ddr1_2/mvDramIf.h" -+#include "twsi/mvTwsi.h" -+ -+#define MAX_DIMM_NUM 2 -+#define SPD_SIZE 128 -+ -+/* Dimm spd offsets */ -+#define DIMM_MEM_TYPE 2 -+#define DIMM_ROW_NUM 3 -+#define DIMM_COL_NUM 4 -+#define DIMM_MODULE_BANK_NUM 5 -+#define DIMM_DATA_WIDTH 6 -+#define DIMM_VOLT_IF 8 -+#define DIMM_MIN_CC_AT_MAX_CAS 9 -+#define DIMM_ERR_CHECK_TYPE 11 -+#define DIMM_REFRESH_INTERVAL 12 -+#define DIMM_SDRAM_WIDTH 13 -+#define DIMM_ERR_CHECK_DATA_WIDTH 14 -+#define DIMM_MIN_CLK_DEL 15 -+#define DIMM_BURST_LEN_SUP 16 -+#define DIMM_DEV_BANK_NUM 17 -+#define DIMM_SUP_CAL 18 -+#define DIMM_DDR2_TYPE_INFORMATION 20 /* DDR2 only */ -+#define DIMM_BUF_ADDR_CONT_IN 21 -+#define DIMM_MIN_CC_AT_MAX_CAS_MINUS1 23 -+#define DIMM_MIN_CC_AT_MAX_CAS_MINUS2 25 -+#define DIMM_MIN_ROW_PRECHARGE_TIME 27 -+#define DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE 28 -+#define DIMM_MIN_RAS_TO_CAS_DELAY 29 -+#define DIMM_MIN_RAS_PULSE_WIDTH 30 -+#define DIMM_BANK_DENSITY 31 -+#define DIMM_MIN_WRITE_RECOVERY_TIME 36 -+#define DIMM_MIN_WRITE_TO_READ_CMD_DELAY 37 -+#define DIMM_MIN_READ_TO_PRECH_CMD_DELAY 38 -+#define DIMM_MIN_REFRESH_TO_ACTIVATE_CMD 42 -+ -+/* Dimm Memory Type values */ -+#define DIMM_MEM_TYPE_SDRAM 0x4 -+#define DIMM_MEM_TYPE_DDR1 0x7 -+#define DIMM_MEM_TYPE_DDR2 0x8 -+ -+#define DIMM_MODULE_MANU_OFFS 64 -+#define DIMM_MODULE_MANU_SIZE 8 -+#define DIMM_MODULE_VEN_OFFS 73 -+#define DIMM_MODULE_VEN_SIZE 25 -+#define DIMM_MODULE_ID_OFFS 99 -+#define DIMM_MODULE_ID_SIZE 18 -+ -+/* enumeration for voltage levels. */ -+typedef enum _mvDimmVoltageIf -+{ -+ TTL_5V_TOLERANT, -+ LVTTL, -+ HSTL_1_5V, -+ SSTL_3_3V, -+ SSTL_2_5V, -+ VOLTAGE_UNKNOWN, -+} MV_DIMM_VOLTAGE_IF; -+ -+ -+/* enumaration for SDRAM CAS Latencies. */ -+typedef enum _mvDimmSdramCas -+{ -+ SD_CL_1 =1, -+ SD_CL_2, -+ SD_CL_3, -+ SD_CL_4, -+ SD_CL_5, -+ SD_CL_6, -+ SD_CL_7, -+ SD_FAULT -+}MV_DIMM_SDRAM_CAS; -+ -+ -+/* DIMM information structure */ -+typedef struct _mvDimmInfo -+{ -+ MV_MEMORY_TYPE memoryType; /* DDR or SDRAM */ -+ -+ MV_U8 spdRawData[SPD_SIZE]; /* Content of SPD-EEPROM copied 1:1 */ -+ -+ /* DIMM dimensions */ -+ MV_U32 numOfRowAddr; -+ MV_U32 numOfColAddr; -+ MV_U32 numOfModuleBanks; -+ MV_U32 dataWidth; -+ MV_U32 errorCheckType; /* ECC , PARITY..*/ -+ MV_U32 sdramWidth; /* 4,8,16 or 32 */ -+ MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ -+ MV_U32 burstLengthSupported; -+ MV_U32 numOfBanksOnEachDevice; -+ MV_U32 suportedCasLatencies; -+ MV_U32 refreshInterval; -+ MV_U32 dimmBankDensity; -+ MV_U32 dimmTypeInfo; /* DDR2 only */ -+ MV_U32 dimmAttributes; -+ -+ /* DIMM timing parameters */ -+ MV_U32 minCycleTimeAtMaxCasLatPs; -+ MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; -+ MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; -+ MV_U32 minRowPrechargeTime; -+ MV_U32 minRowActiveToRowActive; -+ MV_U32 minRasToCasDelay; -+ MV_U32 minRasPulseWidth; -+ MV_U32 minWriteRecoveryTime; /* DDR2 only */ -+ MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ -+ MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ -+ MV_U32 minRefreshToActiveCmd; /* DDR2 only */ -+ -+ /* Parameters calculated from the extracted DIMM information */ -+ MV_U32 size; /* 16,64,128,256 or 512 MByte in MB units */ -+ MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit in MB units */ -+ MV_U32 numberOfDevices; -+ -+} MV_DIMM_INFO; -+ -+ -+MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo); -+MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo); -+MV_VOID dimmSpdPrint(MV_U32 dimmNum); -+MV_STATUS dimmSpdCpy(MV_VOID); -+ -+#endif /* __INCmvDram */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,1599 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+/* includes */ -+#include "ddr1_2/mvDramIf.h" -+#include "ctrlEnv/sys/mvCpuIf.h" -+ -+ -+ -+#ifdef MV_DEBUG -+#define DB(x) x -+#else -+#define DB(x) -+#endif -+ -+/* DRAM bank presence encoding */ -+#define BANK_PRESENT_CS0 0x1 -+#define BANK_PRESENT_CS0_CS1 0x3 -+#define BANK_PRESENT_CS0_CS2 0x5 -+#define BANK_PRESENT_CS0_CS1_CS2 0x7 -+#define BANK_PRESENT_CS0_CS2_CS3 0xd -+#define BANK_PRESENT_CS0_CS2_CS3_CS4 0xf -+ -+/* locals */ -+static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin); -+#if defined(MV_INC_BOARD_DDIM) -+static void sdramDDr2OdtConfig(MV_DRAM_BANK_INFO *pBankInfo); -+static MV_U32 dunitCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas); -+static MV_U32 sdramModeRegCalc(MV_U32 minCas); -+static MV_U32 sdramExtModeRegCalc(MV_DRAM_BANK_INFO *pBankInfo); -+static MV_U32 sdramAddrCtrlRegCalc(MV_DRAM_BANK_INFO *pBankInfo); -+static MV_U32 sdramConfigRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk); -+static MV_U32 minCasCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk, -+ MV_U32 forcedCl); -+static MV_U32 sdramTimeCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, -+ MV_U32 minCas, MV_U32 busClk); -+static MV_U32 sdramTimeCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, -+ MV_U32 busClk); -+ -+/******************************************************************************* -+* mvDramIfDetect - Prepare DRAM interface configuration values. -+* -+* DESCRIPTION: -+* This function implements the full DRAM detection and timing -+* configuration for best system performance. -+* Since this routine runs from a ROM device (Boot Flash), its stack -+* resides on RAM, that might be the system DRAM. Changing DRAM -+* configuration values while keeping vital data in DRAM is risky. That -+* is why the function does not preform the configuration setting but -+* prepare those in predefined 32bit registers (in this case IDMA -+* registers are used) for other routine to perform the settings. -+* The function will call for board DRAM SPD information for each DRAM -+* chip select. The function will then analyze those SPD parameters of -+* all DRAM banks in order to decide on DRAM configuration compatible -+* for all DRAM banks. -+* The function will set the CPU DRAM address decode registers. -+* Note: This routine prepares values that will overide configuration of -+* mvDramBasicAsmInit(). -+* -+* INPUT: -+* forcedCl - Forced CAL Latency. If equal to zero, do not force. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvDramIfDetect(MV_U32 forcedCl) -+{ -+ MV_U32 retVal = MV_OK; /* return value */ -+ MV_DRAM_BANK_INFO bankInfo[MV_DRAM_MAX_CS]; -+ MV_U32 busClk, size, base = 0, i, temp, deviceW, dimmW; -+ MV_U8 minCas; -+ MV_DRAM_DEC_WIN dramDecWin; -+ -+ dramDecWin.addrWin.baseHigh = 0; -+ -+ busClk = mvBoardSysClkGet(); -+ -+ if (0 == busClk) -+ { -+ mvOsPrintf("Dram: ERR. Can't detect system clock! \n"); -+ return MV_ERROR; -+ } -+ -+ /* Close DRAM banks except bank 0 (in case code is excecuting from it...) */ -+#if defined(MV_INCLUDE_SDRAM_CS1) -+ for(i= SDRAM_CS1; i < MV_DRAM_MAX_CS; i++) -+ mvCpuIfTargetWinEnable(i, MV_FALSE); -+#endif -+ -+ /* we will use bank 0 as the representative of the all the DRAM banks, */ -+ /* since bank 0 must exist. */ -+ for(i = 0; i < MV_DRAM_MAX_CS; i++) -+ { -+ /* if Bank exist */ -+ if(MV_OK == mvDramBankInfoGet(i, &bankInfo[i])) -+ { -+ /* check it isn't SDRAM */ -+ if(bankInfo[i].memoryType == MEM_TYPE_SDRAM) -+ { -+ mvOsPrintf("Dram: ERR. SDRAM type not supported !!!\n"); -+ return MV_ERROR; -+ } -+ /* All banks must support registry in order to activate it */ -+ if(bankInfo[i].registeredAddrAndControlInputs != -+ bankInfo[0].registeredAddrAndControlInputs) -+ { -+ mvOsPrintf("Dram: ERR. different Registered settings !!!\n"); -+ return MV_ERROR; -+ } -+ -+ /* Init the CPU window decode */ -+ /* Note that the size in Bank info is in MB units */ -+ /* Note that the Dimm width might be different then the device DRAM width */ -+ temp = MV_REG_READ(SDRAM_CONFIG_REG); -+ -+ deviceW = ((temp & SDRAM_DWIDTH_MASK) == SDRAM_DWIDTH_16BIT )? 16 : 32; -+ dimmW = bankInfo[0].dataWidth - (bankInfo[0].dataWidth % 16); -+ size = ((bankInfo[i].size << 20) / (dimmW/deviceW)); -+ -+ /* We can not change DRAM window settings while excecuting */ -+ /* code from it. That is why we skip the DRAM CS[0], saving */ -+ /* it to the ROM configuration routine */ -+ if(i == SDRAM_CS0) -+ { -+ MV_U32 sizeToReg; -+ -+ /* Translate the given window size to register format */ -+ sizeToReg = ctrlSizeToReg(size, SCSR_SIZE_ALIGNMENT); -+ -+ /* Size parameter validity check. */ -+ if (-1 == sizeToReg) -+ { -+ mvOsPrintf("mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n" -+ ,i); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Size is located at upper 16 bits */ -+ sizeToReg <<= SCSR_SIZE_OFFS; -+ -+ /* enable it */ -+ sizeToReg |= SCSR_WIN_EN; -+ -+ MV_REG_WRITE(DRAM_BUF_REG0, sizeToReg); -+ } -+ else -+ { -+ dramDecWin.addrWin.baseLow = base; -+ dramDecWin.addrWin.size = size; -+ dramDecWin.enable = MV_TRUE; -+ -+ if (MV_OK != mvDramIfWinSet(SDRAM_CS0 + i, &dramDecWin)) -+ { -+ mvOsPrintf("Dram: ERR. Fail to set bank %d!!!\n", -+ SDRAM_CS0 + i); -+ return MV_ERROR; -+ } -+ } -+ -+ base += size; -+ -+ /* update the suportedCasLatencies mask */ -+ bankInfo[0].suportedCasLatencies &= bankInfo[i].suportedCasLatencies; -+ -+ } -+ else -+ { -+ if( i == 0 ) /* bank 0 doesn't exist */ -+ { -+ mvOsPrintf("Dram: ERR. Fail to detect bank 0 !!!\n"); -+ return MV_ERROR; -+ } -+ else -+ { -+ DB(mvOsPrintf("Dram: Could not find bank %d\n", i)); -+ bankInfo[i].size = 0; /* Mark this bank as non exist */ -+ } -+ } -+ } -+ -+ /* calculate minimum CAS */ -+ minCas = minCasCalc(&bankInfo[0], busClk, forcedCl); -+ if (0 == minCas) -+ { -+ mvOsOutput("Dram: Warn: Could not find CAS compatible to SysClk %dMhz\n", -+ (busClk / 1000000)); -+ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ minCas = DDR2_CL_4; /* Continue with this CAS */ -+ mvOsPrintf("Set default CAS latency 4\n"); -+ } -+ else -+ { -+ minCas = DDR1_CL_3; /* Continue with this CAS */ -+ mvOsPrintf("Set default CAS latency 3\n"); -+ } -+ } -+ -+ /* calc SDRAM_CONFIG_REG and save it to temp register */ -+ temp = sdramConfigRegCalc(&bankInfo[0], busClk); -+ if(-1 == temp) -+ { -+ mvOsPrintf("Dram: ERR. sdramConfigRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG1, temp); -+ -+ /* calc SDRAM_MODE_REG and save it to temp register */ -+ temp = sdramModeRegCalc(minCas); -+ if(-1 == temp) -+ { -+ mvOsPrintf("Dram: ERR. sdramModeRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG2, temp); -+ -+ /* calc SDRAM_EXTENDED_MODE_REG and save it to temp register */ -+ temp = sdramExtModeRegCalc(&bankInfo[0]); -+ if(-1 == temp) -+ { -+ mvOsPrintf("Dram: ERR. sdramModeRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG10, temp); -+ -+ /* calc D_UNIT_CONTROL_LOW and save it to temp register */ -+ temp = dunitCtrlLowRegCalc(&bankInfo[0], minCas); -+ if(-1 == temp) -+ { -+ mvOsPrintf("Dram: ERR. dunitCtrlLowRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG3, temp); -+ -+ /* calc SDRAM_ADDR_CTRL_REG and save it to temp register */ -+ temp = sdramAddrCtrlRegCalc(&bankInfo[0]); -+ if(-1 == temp) -+ { -+ mvOsPrintf("Dram: ERR. sdramAddrCtrlRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG4, temp); -+ -+ /* calc SDRAM_TIMING_CTRL_LOW_REG and save it to temp register */ -+ temp = sdramTimeCtrlLowRegCalc(&bankInfo[0], minCas, busClk); -+ if(-1 == temp) -+ { -+ mvOsPrintf("Dram: ERR. sdramTimeCtrlLowRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG5, temp); -+ -+ /* calc SDRAM_TIMING_CTRL_HIGH_REG and save it to temp register */ -+ temp = sdramTimeCtrlHighRegCalc(&bankInfo[0], busClk); -+ if(-1 == temp) -+ { -+ mvOsPrintf("Dram: ERR. sdramTimeCtrlHighRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG6, temp); -+ -+ /* Config DDR2 On Die Termination (ODT) registers */ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ sdramDDr2OdtConfig(bankInfo); -+ } -+ -+ /* Note that DDR SDRAM Address/Control and Data pad calibration */ -+ /* settings is done in mvSdramIfConfig.s */ -+ -+ return retVal; -+} -+ -+/******************************************************************************* -+* minCasCalc - Calculate the Minimum CAS latency which can be used. -+* -+* DESCRIPTION: -+* Calculate the minimum CAS latency that can be used, base on the DRAM -+* parameters and the SDRAM bus Clock freq. -+* -+* INPUT: -+* busClk - the DRAM bus Clock. -+* pBankInfo - bank info parameters. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* The minimum CAS Latency. The function returns 0 if max CAS latency -+* supported by banks is incompatible with system bus clock frequancy. -+* -+*******************************************************************************/ -+static MV_U32 minCasCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk, -+ MV_U32 forcedCl) -+{ -+ MV_U32 count = 1, j; -+ MV_U32 busClkPs = 1000000000 / (busClk / 1000); /* in ps units */ -+ MV_U32 startBit, stopBit; -+ -+ /* DDR 1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * -+ *********************************************************/ -+ -+ /* DDR 2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * -+ *********************************************************/ -+ -+ -+ /* If we are asked to use the forced CAL */ -+ if (forcedCl) -+ { -+ mvOsPrintf("DRAM: Using forced CL %d.%d\n", (forcedCl / 10), -+ (forcedCl % 10)); -+ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ if (forcedCl == 30) -+ pBankInfo->suportedCasLatencies = 0x08; -+ else if (forcedCl == 40) -+ pBankInfo->suportedCasLatencies = 0x10; -+ else -+ { -+ mvOsPrintf("Forced CL %d.%d not supported. Set default CL 4\n", -+ (forcedCl / 10), (forcedCl % 10)); -+ pBankInfo->suportedCasLatencies = 0x10; -+ } -+ } -+ else -+ { -+ if (forcedCl == 15) -+ pBankInfo->suportedCasLatencies = 0x02; -+ else if (forcedCl == 20) -+ pBankInfo->suportedCasLatencies = 0x04; -+ else if (forcedCl == 25) -+ pBankInfo->suportedCasLatencies = 0x08; -+ else if (forcedCl == 30) -+ pBankInfo->suportedCasLatencies = 0x10; -+ else if (forcedCl == 40) -+ pBankInfo->suportedCasLatencies = 0x40; -+ else -+ { -+ mvOsPrintf("Forced CL %d.%d not supported. Set default CL 3\n", -+ (forcedCl / 10), (forcedCl % 10)); -+ pBankInfo->suportedCasLatencies = 0x10; -+ } -+ } -+ -+ return pBankInfo->suportedCasLatencies; -+ } -+ -+ /* go over the supported cas mask from Max Cas down and check if the */ -+ /* SysClk stands in its time requirments. */ -+ -+ -+ DB(mvOsPrintf("Dram: minCasCalc supported mask = %x busClkPs = %x \n", -+ pBankInfo->suportedCasLatencies,busClkPs )); -+ for(j = 7; j > 0; j--) -+ { -+ if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) -+ { -+ /* Reset the bits for CL incompatible for the sysClk */ -+ switch (count) -+ { -+ case 1: -+ if (pBankInfo->minCycleTimeAtMaxCasLatPs > busClkPs) -+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ case 2: -+ if (pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps > busClkPs) -+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ case 3: -+ if (pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps > busClkPs) -+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ default: -+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); -+ break; -+ } -+ } -+ } -+ -+ DB(mvOsPrintf("Dram: minCasCalc support = %x (after SysCC calc)\n", -+ pBankInfo->suportedCasLatencies )); -+ -+ /* SDRAM DDR1 controller supports CL 1.5 to 3.5 */ -+ /* SDRAM DDR2 controller supports CL 3 to 5 */ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ startBit = 3; /* DDR2 support CL start with CL3 (bit 3) */ -+ stopBit = 5; /* DDR2 support CL stops with CL5 (bit 5) */ -+ } -+ else -+ { -+ startBit = 1; /* DDR1 support CL start with CL1.5 (bit 3) */ -+ stopBit = 4; /* DDR1 support CL stops with CL3 (bit 4) */ -+ } -+ -+ for(j = startBit; j <= stopBit ; j++) -+ { -+ if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) -+ { -+ DB(mvOsPrintf("Dram: minCasCalc choose CAS %x \n",(BIT0 << j))); -+ return (BIT0 << j); -+ } -+ } -+ -+ return 0; -+} -+ -+/******************************************************************************* -+* sdramConfigRegCalc - Calculate sdram config register -+* -+* DESCRIPTION: Calculate sdram config register optimized value based -+* on the bank info parameters. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram config reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramConfigRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) -+{ -+ MV_U32 sdramConfig = 0; -+ MV_U32 refreshPeriod; -+ -+ busClk /= 1000000; /* we work with busClk in MHz */ -+ -+ sdramConfig = MV_REG_READ(SDRAM_CONFIG_REG); -+ -+ /* figure out the memory refresh internal */ -+ switch (pBankInfo->refreshInterval & 0xf) -+ { -+ case 0x0: /* refresh period is 15.625 usec */ -+ refreshPeriod = 15625; -+ break; -+ case 0x1: /* refresh period is 3.9 usec */ -+ refreshPeriod = 3900; -+ break; -+ case 0x2: /* refresh period is 7.8 usec */ -+ refreshPeriod = 7800; -+ break; -+ case 0x3: /* refresh period is 31.3 usec */ -+ refreshPeriod = 31300; -+ break; -+ case 0x4: /* refresh period is 62.5 usec */ -+ refreshPeriod = 62500; -+ break; -+ case 0x5: /* refresh period is 125 usec */ -+ refreshPeriod = 125000; -+ break; -+ default: /* refresh period undefined */ -+ mvOsPrintf("Dram: ERR. DRAM refresh period is unknown!\n"); -+ return -1; -+ } -+ -+ /* Now the refreshPeriod is in register format value */ -+ refreshPeriod = (busClk * refreshPeriod) / 1000; -+ -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc calculated refresh interval %0x\n", -+ refreshPeriod)); -+ -+ /* make sure the refresh value is only 14 bits */ -+ if(refreshPeriod > SDRAM_REFRESH_MAX) -+ { -+ refreshPeriod = SDRAM_REFRESH_MAX; -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc adjusted refresh interval %0x\n", -+ refreshPeriod)); -+ } -+ -+ /* Clear the refresh field */ -+ sdramConfig &= ~SDRAM_REFRESH_MASK; -+ -+ /* Set new value to refresh field */ -+ sdramConfig |= (refreshPeriod & SDRAM_REFRESH_MASK); -+ -+ /* registered DRAM ? */ -+ if ( pBankInfo->registeredAddrAndControlInputs ) -+ { -+ /* it's registered DRAM, so set the reg. DRAM bit */ -+ sdramConfig |= SDRAM_REGISTERED; -+ mvOsPrintf("DRAM Attribute: Registered address and control inputs.\n"); -+ } -+ -+ /* set DDR SDRAM devices configuration */ -+ sdramConfig &= ~SDRAM_DCFG_MASK; /* Clear Dcfg field */ -+ -+ switch (pBankInfo->sdramWidth) -+ { -+ case 8: /* memory is x8 */ -+ sdramConfig |= SDRAM_DCFG_X8_DEV; -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc SDRAM device width x8\n")); -+ break; -+ case 16: -+ sdramConfig |= SDRAM_DCFG_X16_DEV; -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc SDRAM device width x16\n")); -+ break; -+ default: /* memory width unsupported */ -+ mvOsPrintf("Dram: ERR. DRAM chip width is unknown!\n"); -+ return -1; -+ } -+ -+ /* Set static default settings */ -+ sdramConfig |= SDRAM_CONFIG_DV; -+ -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc set sdramConfig to 0x%x\n", -+ sdramConfig)); -+ -+ return sdramConfig; -+} -+ -+/******************************************************************************* -+* sdramModeRegCalc - Calculate sdram mode register -+* -+* DESCRIPTION: Calculate sdram mode register optimized value based -+* on the bank info parameters and the minCas. -+* -+* INPUT: -+* minCas - minimum CAS supported. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram mode reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramModeRegCalc(MV_U32 minCas) -+{ -+ MV_U32 sdramMode; -+ -+ sdramMode = MV_REG_READ(SDRAM_MODE_REG); -+ -+ /* Clear CAS Latency field */ -+ sdramMode &= ~SDRAM_CL_MASK; -+ -+ mvOsPrintf("DRAM CAS Latency "); -+ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ switch (minCas) -+ { -+ case DDR2_CL_3: -+ sdramMode |= SDRAM_DDR2_CL_3; -+ mvOsPrintf("3.\n"); -+ break; -+ case DDR2_CL_4: -+ sdramMode |= SDRAM_DDR2_CL_4; -+ mvOsPrintf("4.\n"); -+ break; -+ case DDR2_CL_5: -+ sdramMode |= SDRAM_DDR2_CL_5; -+ mvOsPrintf("5.\n"); -+ break; -+ default: -+ mvOsPrintf("\nsdramModeRegCalc ERROR: Max. CL out of range\n"); -+ return -1; -+ } -+ sdramMode |= DDR2_MODE_REG_DV; -+ } -+ else /* DDR1 */ -+ { -+ switch (minCas) -+ { -+ case DDR1_CL_1_5: -+ sdramMode |= SDRAM_DDR1_CL_1_5; -+ mvOsPrintf("1.5\n"); -+ break; -+ case DDR1_CL_2: -+ sdramMode |= SDRAM_DDR1_CL_2; -+ mvOsPrintf("2\n"); -+ break; -+ case DDR1_CL_2_5: -+ sdramMode |= SDRAM_DDR1_CL_2_5; -+ mvOsPrintf("2.5\n"); -+ break; -+ case DDR1_CL_3: -+ sdramMode |= SDRAM_DDR1_CL_3; -+ mvOsPrintf("3\n"); -+ break; -+ case DDR1_CL_4: -+ sdramMode |= SDRAM_DDR1_CL_4; -+ mvOsPrintf("4\n"); -+ break; -+ default: -+ mvOsPrintf("\nsdramModeRegCalc ERROR: Max. CL out of range\n"); -+ return -1; -+ } -+ sdramMode |= DDR1_MODE_REG_DV; -+ } -+ -+ DB(mvOsPrintf("nsdramModeRegCalc register 0x%x\n", sdramMode )); -+ -+ return sdramMode; -+} -+ -+/******************************************************************************* -+* sdramExtModeRegCalc - Calculate sdram Extended mode register -+* -+* DESCRIPTION: -+* Return sdram Extended mode register value based -+* on the bank info parameters and bank presence. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram Extended mode reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramExtModeRegCalc(MV_DRAM_BANK_INFO *pBankInfo) -+{ -+ MV_U32 populateBanks = 0; -+ int bankNum; -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ /* Represent the populate banks in binary form */ -+ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ if (0 != pBankInfo[bankNum].size) -+ { -+ populateBanks |= (1 << bankNum); -+ } -+ } -+ -+ switch(populateBanks) -+ { -+ case(BANK_PRESENT_CS0): -+ return DDR_SDRAM_EXT_MODE_CS0_DV; -+ -+ case(BANK_PRESENT_CS0_CS1): -+ return DDR_SDRAM_EXT_MODE_CS0_DV; -+ -+ case(BANK_PRESENT_CS0_CS2): -+ return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; -+ -+ case(BANK_PRESENT_CS0_CS1_CS2): -+ return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; -+ -+ case(BANK_PRESENT_CS0_CS2_CS3): -+ return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; -+ -+ case(BANK_PRESENT_CS0_CS2_CS3_CS4): -+ return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; -+ -+ default: -+ mvOsPrintf("sdramExtModeRegCalc: Invalid DRAM bank presence\n"); -+ return -1; -+ } -+ } -+ return 0; -+} -+ -+/******************************************************************************* -+* dunitCtrlLowRegCalc - Calculate sdram dunit control low register -+* -+* DESCRIPTION: Calculate sdram dunit control low register optimized value based -+* on the bank info parameters and the minCas. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* minCas - minimum CAS supported. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram dunit control low reg value. -+* -+*******************************************************************************/ -+static MV_U32 dunitCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas) -+{ -+ MV_U32 dunitCtrlLow; -+ -+ dunitCtrlLow = MV_REG_READ(SDRAM_DUNIT_CTRL_REG); -+ -+ /* Clear StBurstDel field */ -+ dunitCtrlLow &= ~SDRAM_ST_BURST_DEL_MASK; -+ -+#ifdef MV_88W8660 -+ /* Clear address/control output timing field */ -+ dunitCtrlLow &= ~SDRAM_CTRL_POS_RISE; -+#endif /* MV_88W8660 */ -+ -+ DB(mvOsPrintf("Dram: dunitCtrlLowRegCalc\n")); -+ -+ /* For proper sample of read data set the Dunit Control register's */ -+ /* stBurstDel bits [27:24] */ -+ /********-********-********-********-********-********* -+ * CL=1.5 | CL=2 | CL=2.5 | CL=3 | CL=4 | CL=5 * -+ *********-********-********-********-********-********* -+Not Reg. * 0011 | 0011 | 0100 | 0100 | 0101 | TBD * -+ *********-********-********-********-********-********* -+Registered * 0100 | 0100 | 0101 | 0101 | 0110 | TBD * -+ *********-********-********-********-********-*********/ -+ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ switch (minCas) -+ { -+ case DDR2_CL_3: -+ /* registerd DDR SDRAM? */ -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; -+ else -+ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; -+ break; -+ case DDR2_CL_4: -+ /* registerd DDR SDRAM? */ -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ dunitCtrlLow |= 0x6 << SDRAM_ST_BURST_DEL_OFFS; -+ else -+ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; -+ break; -+ default: -+ mvOsPrintf("Dram: dunitCtrlLowRegCalc Max. CL out of range %d\n", -+ minCas); -+ return -1; -+ } -+ } -+ else /* DDR1 */ -+ { -+ switch (minCas) -+ { -+ case DDR1_CL_1_5: -+ /* registerd DDR SDRAM? */ -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; -+ else -+ dunitCtrlLow |= 0x3 << SDRAM_ST_BURST_DEL_OFFS; -+ break; -+ case DDR1_CL_2: -+ /* registerd DDR SDRAM? */ -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; -+ else -+ dunitCtrlLow |= 0x3 << SDRAM_ST_BURST_DEL_OFFS; -+ break; -+ case DDR1_CL_2_5: -+ /* registerd DDR SDRAM? */ -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; -+ else -+ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; -+ break; -+ case DDR1_CL_3: -+ /* registerd DDR SDRAM? */ -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; -+ else -+ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; -+ break; -+ case DDR1_CL_4: -+ /* registerd DDR SDRAM? */ -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ dunitCtrlLow |= 0x6 << SDRAM_ST_BURST_DEL_OFFS; -+ else -+ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; -+ break; -+ default: -+ mvOsPrintf("Dram: dunitCtrlLowRegCalc Max. CL out of range %d\n", -+ minCas); -+ return -1; -+ } -+ -+ } -+ DB(mvOsPrintf("Dram: Reg dunit control low = %x\n", dunitCtrlLow )); -+ -+ return dunitCtrlLow; -+} -+ -+/******************************************************************************* -+* sdramAddrCtrlRegCalc - Calculate sdram address control register -+* -+* DESCRIPTION: Calculate sdram address control register optimized value based -+* on the bank info parameters and the minCas. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram address control reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramAddrCtrlRegCalc(MV_DRAM_BANK_INFO *pBankInfo) -+{ -+ MV_U32 addrCtrl = 0; -+ -+ /* Set Address Control register static configuration bits */ -+ addrCtrl = MV_REG_READ(SDRAM_ADDR_CTRL_REG); -+ -+ /* Set address control default value */ -+ addrCtrl |= SDRAM_ADDR_CTRL_DV; -+ -+ /* Clear DSize field */ -+ addrCtrl &= ~SDRAM_DSIZE_MASK; -+ -+ /* Note that density is in MB units */ -+ switch (pBankInfo->deviceDensity) -+ { -+ case 128: /* 128 Mbit */ -+ DB(mvOsPrintf("DRAM Device Density 128Mbit\n")); -+ addrCtrl |= SDRAM_DSIZE_128Mb; -+ break; -+ case 256: /* 256 Mbit */ -+ DB(mvOsPrintf("DRAM Device Density 256Mbit\n")); -+ addrCtrl |= SDRAM_DSIZE_256Mb; -+ break; -+ case 512: /* 512 Mbit */ -+ DB(mvOsPrintf("DRAM Device Density 512Mbit\n")); -+ addrCtrl |= SDRAM_DSIZE_512Mb; -+ break; -+ default: -+ mvOsPrintf("Dram: sdramAddrCtrl unsupported RAM-Device size %d\n", -+ pBankInfo->deviceDensity); -+ return -1; -+ } -+ -+ /* SDRAM address control */ -+ DB(mvOsPrintf("Dram: setting sdram address control with: %x \n", addrCtrl)); -+ -+ return addrCtrl; -+} -+ -+/******************************************************************************* -+* sdramTimeCtrlLowRegCalc - Calculate sdram timing control low register -+* -+* DESCRIPTION: -+* This function calculates sdram timing control low register -+* optimized value based on the bank info parameters and the minCas. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* busClk - Bus clock -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram timinf control low reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramTimeCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, -+ MV_U32 minCas, MV_U32 busClk) -+{ -+ MV_U32 tRp = 0; -+ MV_U32 tRrd = 0; -+ MV_U32 tRcd = 0; -+ MV_U32 tRas = 0; -+ MV_U32 tWr = 0; -+ MV_U32 tWtr = 0; -+ MV_U32 tRtp = 0; -+ -+ MV_U32 bankNum; -+ -+ busClk = busClk / 1000000; /* In MHz */ -+ -+ /* Scan all DRAM banks to find maximum timing values */ -+ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ tRp = MV_MAX(tRp, pBankInfo[bankNum].minRowPrechargeTime); -+ tRrd = MV_MAX(tRrd, pBankInfo[bankNum].minRowActiveToRowActive); -+ tRcd = MV_MAX(tRcd, pBankInfo[bankNum].minRasToCasDelay); -+ tRas = MV_MAX(tRas, pBankInfo[bankNum].minRasPulseWidth); -+ } -+ -+ /* Extract timing (in ns) from SPD value. We ignore the tenth ns part. */ -+ /* by shifting the data two bits right. */ -+ tRp = tRp >> 2; /* For example 0x50 -> 20ns */ -+ tRrd = tRrd >> 2; -+ tRcd = tRcd >> 2; -+ -+ /* Extract clock cycles from time parameter. We need to round up */ -+ tRp = ((busClk * tRp) / 1000) + (((busClk * tRp) % 1000) ? 1 : 0); -+ /* Micron work around for 133MHz */ -+ if (busClk == 133) -+ tRp += 1; -+ DB(mvOsPrintf("Dram Timing Low: tRp = %d ", tRp)); -+ tRrd = ((busClk * tRrd) / 1000) + (((busClk * tRrd) % 1000) ? 1 : 0); -+ /* JEDEC min reqeirments tRrd = 2 */ -+ if (tRrd < 2) -+ tRrd = 2; -+ DB(mvOsPrintf("tRrd = %d ", tRrd)); -+ tRcd = ((busClk * tRcd) / 1000) + (((busClk * tRcd) % 1000) ? 1 : 0); -+ DB(mvOsPrintf("tRcd = %d ", tRcd)); -+ tRas = ((busClk * tRas) / 1000) + (((busClk * tRas) % 1000) ? 1 : 0); -+ DB(mvOsPrintf("tRas = %d ", tRas)); -+ -+ /* tWr and tWtr is different for DDR1 and DDR2. tRtp is only for DDR2 */ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ /* Scan all DRAM banks to find maximum timing values */ -+ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ tWr = MV_MAX(tWr, pBankInfo[bankNum].minWriteRecoveryTime); -+ tWtr = MV_MAX(tWtr, pBankInfo[bankNum].minWriteToReadCmdDelay); -+ tRtp = MV_MAX(tRtp, pBankInfo[bankNum].minReadToPrechCmdDelay); -+ } -+ -+ /* Extract timing (in ns) from SPD value. We ignore the tenth ns */ -+ /* part by shifting the data two bits right. */ -+ tWr = tWr >> 2; /* For example 0x50 -> 20ns */ -+ tWtr = tWtr >> 2; -+ tRtp = tRtp >> 2; -+ -+ /* Extract clock cycles from time parameter. We need to round up */ -+ tWr = ((busClk * tWr) / 1000) + (((busClk * tWr) % 1000) ? 1 : 0); -+ DB(mvOsPrintf("tWr = %d ", tWr)); -+ tWtr = ((busClk * tWtr) / 1000) + (((busClk * tWtr) % 1000) ? 1 : 0); -+ /* JEDEC min reqeirments tWtr = 2 */ -+ if (tWtr < 2) -+ tWtr = 2; -+ DB(mvOsPrintf("tWtr = %d ", tWtr)); -+ tRtp = ((busClk * tRtp) / 1000) + (((busClk * tRtp) % 1000) ? 1 : 0); -+ /* JEDEC min reqeirments tRtp = 2 */ -+ if (tRtp < 2) -+ tRtp = 2; -+ DB(mvOsPrintf("tRtp = %d ", tRtp)); -+ } -+ else -+ { -+ tWr = ((busClk*SDRAM_TWR) / 1000) + (((busClk*SDRAM_TWR) % 1000)?1:0); -+ -+ if ((200 == busClk) || ((100 == busClk) && (DDR1_CL_1_5 == minCas))) -+ { -+ tWtr = 2; -+ } -+ else -+ { -+ tWtr = 1; -+ } -+ -+ tRtp = 2; /* Must be set to 0x1 (two cycles) when using DDR1 */ -+ } -+ -+ DB(mvOsPrintf("tWtr = %d\n", tWtr)); -+ -+ /* Note: value of 0 in register means one cycle, 1 means two and so on */ -+ return (((tRp - 1) << SDRAM_TRP_OFFS) | -+ ((tRrd - 1) << SDRAM_TRRD_OFFS) | -+ ((tRcd - 1) << SDRAM_TRCD_OFFS) | -+ ((tRas - 1) << SDRAM_TRAS_OFFS) | -+ ((tWr - 1) << SDRAM_TWR_OFFS) | -+ ((tWtr - 1) << SDRAM_TWTR_OFFS) | -+ ((tRtp - 1) << SDRAM_TRTP_OFFS)); -+} -+ -+/******************************************************************************* -+* sdramTimeCtrlHighRegCalc - Calculate sdram timing control high register -+* -+* DESCRIPTION: -+* This function calculates sdram timing control high register -+* optimized value based on the bank info parameters and the bus clock. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* busClk - Bus clock -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram timinf control high reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramTimeCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, -+ MV_U32 busClk) -+{ -+ MV_U32 tRfc; -+ MV_U32 timeNs = 0; -+ int bankNum; -+ MV_U32 sdramTw2wCyc = 0; -+ -+ busClk = busClk / 1000000; /* In MHz */ -+ -+ /* tRfc is different for DDR1 and DDR2. */ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) -+ { -+ MV_U32 bankNum; -+ -+ /* Scan all DRAM banks to find maximum timing values */ -+ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ timeNs = MV_MAX(timeNs, pBankInfo[bankNum].minRefreshToActiveCmd); -+ } -+ else -+ { -+ if (pBankInfo[0].deviceDensity == _1G) -+ { -+ timeNs = SDRAM_TRFC_1G; -+ } -+ else -+ { -+ if (200 == busClk) -+ { -+ timeNs = SDRAM_TRFC_64_512M_AT_200MHZ; -+ } -+ else -+ { -+ timeNs = SDRAM_TRFC_64_512M; -+ } -+ } -+ } -+ -+ tRfc = ((busClk * timeNs) / 1000) + (((busClk * timeNs) % 1000) ? 1 : 0); -+ -+ DB(mvOsPrintf("Dram Timing High: tRfc = %d\n", tRfc)); -+ -+ -+ /* Represent the populate banks in binary form */ -+ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ if (0 != pBankInfo[bankNum].size) -+ sdramTw2wCyc++; -+ } -+ -+ /* If we have more the 1 bank then we need the TW2W in 1 for ODT switch */ -+ if (sdramTw2wCyc > 1) -+ sdramTw2wCyc = 1; -+ else -+ sdramTw2wCyc = 0; -+ -+ /* Note: value of 0 in register means one cycle, 1 means two and so on */ -+ return ((((tRfc - 1) & SDRAM_TRFC_MASK) << SDRAM_TRFC_OFFS) | -+ ((SDRAM_TR2R_CYC - 1) << SDRAM_TR2R_OFFS) | -+ ((SDRAM_TR2WW2R_CYC - 1) << SDRAM_TR2W_W2R_OFFS) | -+ (((tRfc - 1) >> 4) << SDRAM_TRFC_EXT_OFFS) | -+ (sdramTw2wCyc << SDRAM_TW2W_OFFS)); -+ -+} -+ -+/******************************************************************************* -+* sdramDDr2OdtConfig - Set DRAM DDR2 On Die Termination registers. -+* -+* DESCRIPTION: -+* This function config DDR2 On Die Termination (ODT) registers. -+* ODT configuration is done according to DIMM presence: -+* -+* Presence Ctrl Low Ctrl High Dunit Ctrl Ext Mode -+* CS0 0x84210000 0x00000000 0x0000780F 0x00000440 -+* CS0+CS1 0x84210000 0x00000000 0x0000780F 0x00000440 -+* CS0+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 -+* CS0+CS1+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 -+* CS0+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 -+* CS0+CS1+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 -+* -+* INPUT: -+* pBankInfo - bank info parameters. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* None -+*******************************************************************************/ -+static void sdramDDr2OdtConfig(MV_DRAM_BANK_INFO *pBankInfo) -+{ -+ MV_U32 populateBanks = 0; -+ MV_U32 odtCtrlLow, odtCtrlHigh, dunitOdtCtrl; -+ int bankNum; -+ -+ /* Represent the populate banks in binary form */ -+ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ if (0 != pBankInfo[bankNum].size) -+ { -+ populateBanks |= (1 << bankNum); -+ } -+ } -+ -+ switch(populateBanks) -+ { -+ case(BANK_PRESENT_CS0): -+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_DV; -+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_DV; -+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_DV; -+ break; -+ case(BANK_PRESENT_CS0_CS1): -+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_DV; -+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_DV; -+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_DV; -+ break; -+ case(BANK_PRESENT_CS0_CS2): -+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; -+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; -+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; -+ break; -+ case(BANK_PRESENT_CS0_CS1_CS2): -+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; -+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; -+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; -+ break; -+ case(BANK_PRESENT_CS0_CS2_CS3): -+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; -+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; -+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; -+ break; -+ case(BANK_PRESENT_CS0_CS2_CS3_CS4): -+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; -+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; -+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; -+ break; -+ default: -+ mvOsPrintf("sdramDDr2OdtConfig: Invalid DRAM bank presence\n"); -+ return; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG7, odtCtrlLow); -+ MV_REG_WRITE(DRAM_BUF_REG8, odtCtrlHigh); -+ MV_REG_WRITE(DRAM_BUF_REG9, dunitOdtCtrl); -+ return; -+} -+#endif /* defined(MV_INC_BOARD_DDIM) */ -+ -+/******************************************************************************* -+* mvDramIfWinSet - Set DRAM interface address decode window -+* -+* DESCRIPTION: -+* This function sets DRAM interface address decode window. -+* -+* INPUT: -+* target - System target. Use only SDRAM targets. -+* pAddrDecWin - SDRAM address window structure. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK -+* otherwise. -+*******************************************************************************/ -+MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) -+{ -+ MV_U32 baseReg=0,sizeReg=0; -+ MV_U32 baseToReg=0 , sizeToReg=0; -+ -+ /* Check parameters */ -+ if (!MV_TARGET_IS_DRAM(target)) -+ { -+ mvOsPrintf("mvDramIfWinSet: target %d is not SDRAM\n", target); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the requested window overlaps with current enabled windows */ -+ if (MV_TRUE == sdramIfWinOverlap(target, &pAddrDecWin->addrWin)) -+ { -+ mvOsPrintf("mvDramIfWinSet: ERR. Target %d overlaps\n", target); -+ return MV_BAD_PARAM; -+ } -+ -+ /* check if address is aligned to the size */ -+ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) -+ { -+ mvOsPrintf("mvDramIfWinSet:Error setting DRAM interface window %d."\ -+ "\nAddress 0x%08x is unaligned to size 0x%x.\n", -+ target, -+ pAddrDecWin->addrWin.baseLow, -+ pAddrDecWin->addrWin.size); -+ return MV_ERROR; -+ } -+ -+ /* read base register*/ -+ baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(target)); -+ -+ /* read size register */ -+ sizeReg = MV_REG_READ(SDRAM_SIZE_REG(target)); -+ -+ /* BaseLow[31:16] => base register [31:16] */ -+ baseToReg = pAddrDecWin->addrWin.baseLow & SCBAR_BASE_MASK; -+ -+ /* Write to address decode Base Address Register */ -+ baseReg &= ~SCBAR_BASE_MASK; -+ baseReg |= baseToReg; -+ -+ /* Translate the given window size to register format */ -+ sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, SCSR_SIZE_ALIGNMENT); -+ -+ /* Size parameter validity check. */ -+ if (-1 == sizeToReg) -+ { -+ mvOsPrintf("mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n",target); -+ return MV_BAD_PARAM; -+ } -+ -+ /* set size */ -+ sizeReg &= ~SCSR_SIZE_MASK; -+ /* Size is located at upper 16 bits */ -+ sizeReg |= (sizeToReg << SCSR_SIZE_OFFS); -+ -+ /* enable/Disable */ -+ if (MV_TRUE == pAddrDecWin->enable) -+ { -+ sizeReg |= SCSR_WIN_EN; -+ } -+ else -+ { -+ sizeReg &= ~SCSR_WIN_EN; -+ } -+ -+ /* 3) Write to address decode Base Address Register */ -+ MV_REG_WRITE(SDRAM_BASE_ADDR_REG(target), baseReg); -+ -+ /* Write to address decode Size Register */ -+ MV_REG_WRITE(SDRAM_SIZE_REG(target), sizeReg); -+ -+ return MV_OK; -+} -+/******************************************************************************* -+* mvDramIfWinGet - Get DRAM interface address decode window -+* -+* DESCRIPTION: -+* This function gets DRAM interface address decode window. -+* -+* INPUT: -+* target - System target. Use only SDRAM targets. -+* -+* OUTPUT: -+* pAddrDecWin - SDRAM address window structure. -+* -+* RETURN: -+* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK -+* otherwise. -+*******************************************************************************/ -+MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) -+{ -+ MV_U32 baseReg,sizeReg; -+ MV_U32 sizeRegVal; -+ -+ /* Check parameters */ -+ if (!MV_TARGET_IS_DRAM(target)) -+ { -+ mvOsPrintf("mvDramIfWinGet: target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ /* Read base and size registers */ -+ sizeReg = MV_REG_READ(SDRAM_SIZE_REG(target)); -+ baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(target)); -+ -+ sizeRegVal = (sizeReg & SCSR_SIZE_MASK) >> SCSR_SIZE_OFFS; -+ -+ pAddrDecWin->addrWin.size = ctrlRegToSize(sizeRegVal, -+ SCSR_SIZE_ALIGNMENT); -+ -+ /* Check if ctrlRegToSize returned OK */ -+ if (-1 == pAddrDecWin->addrWin.size) -+ { -+ mvOsPrintf("mvDramIfWinGet: size of target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ /* Extract base address */ -+ /* Base register [31:16] ==> baseLow[31:16] */ -+ pAddrDecWin->addrWin.baseLow = baseReg & SCBAR_BASE_MASK; -+ -+ pAddrDecWin->addrWin.baseHigh = 0; -+ -+ -+ if (sizeReg & SCSR_WIN_EN) -+ { -+ pAddrDecWin->enable = MV_TRUE; -+ } -+ else -+ { -+ pAddrDecWin->enable = MV_FALSE; -+ } -+ -+ return MV_OK; -+} -+/******************************************************************************* -+* mvDramIfWinEnable - Enable/Disable SDRAM address decode window -+* -+* DESCRIPTION: -+* This function enable/Disable SDRAM address decode window. -+* -+* INPUT: -+* target - System target. Use only SDRAM targets. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_ERROR in case function parameter are invalid, MV_OK otherewise. -+* -+*******************************************************************************/ -+MV_STATUS mvDramIfWinEnable(MV_TARGET target,MV_BOOL enable) -+{ -+ MV_DRAM_DEC_WIN addrDecWin; -+ -+ /* Check parameters */ -+ if (!MV_TARGET_IS_DRAM(target)) -+ { -+ mvOsPrintf("mvDramIfWinEnable: target %d is Illigal\n", target); -+ return MV_ERROR; -+ } -+ -+ if (enable == MV_TRUE) -+ { /* First check for overlap with other enabled windows */ -+ if (MV_OK != mvDramIfWinGet(target, &addrDecWin)) -+ { -+ mvOsPrintf("mvDramIfWinEnable:ERR. Getting target %d failed.\n", -+ target); -+ return MV_ERROR; -+ } -+ /* Check for overlapping */ -+ if (MV_FALSE == sdramIfWinOverlap(target, &(addrDecWin.addrWin))) -+ { -+ /* No Overlap. Enable address decode winNum window */ -+ MV_REG_BIT_SET(SDRAM_SIZE_REG(target), SCSR_WIN_EN); -+ } -+ else -+ { /* Overlap detected */ -+ mvOsPrintf("mvDramIfWinEnable: ERR. Target %d overlap detect\n", -+ target); -+ return MV_ERROR; -+ } -+ } -+ else -+ { /* Disable address decode winNum window */ -+ MV_REG_BIT_RESET(SDRAM_SIZE_REG(target), SCSR_WIN_EN); -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* sdramIfWinOverlap - Check if an address window overlap an SDRAM address window -+* -+* DESCRIPTION: -+* This function scan each SDRAM address decode window to test if it -+* overlapps the given address windoow -+* -+* INPUT: -+* target - SDRAM target where the function skips checking. -+* pAddrDecWin - The tested address window for overlapping with -+* SDRAM windows. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if the given address window overlaps any enabled address -+* decode map, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin) -+{ -+ MV_TARGET targetNum; -+ MV_DRAM_DEC_WIN addrDecWin; -+ -+ for(targetNum = SDRAM_CS0; targetNum < MV_DRAM_MAX_CS ; targetNum++) -+ { -+ /* don't check our winNum or illegal targets */ -+ if (targetNum == target) -+ { -+ continue; -+ } -+ -+ /* Get window parameters */ -+ if (MV_OK != mvDramIfWinGet(targetNum, &addrDecWin)) -+ { -+ mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); -+ return MV_ERROR; -+ } -+ -+ /* Do not check disabled windows */ -+ if (MV_FALSE == addrDecWin.enable) -+ { -+ continue; -+ } -+ -+ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) -+ { -+ mvOsPrintf( -+ "sdramIfWinOverlap: Required target %d overlap winNum %d\n", -+ target, targetNum); -+ return MV_TRUE; -+ } -+ } -+ -+ return MV_FALSE; -+} -+ -+/******************************************************************************* -+* mvDramIfBankSizeGet - Get DRAM interface bank size. -+* -+* DESCRIPTION: -+* This function returns the size of a given DRAM bank. -+* -+* INPUT: -+* bankNum - Bank number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* DRAM bank size. If bank is disabled the function return '0'. In case -+* or paramter is invalid, the function returns -1. -+* -+*******************************************************************************/ -+MV_32 mvDramIfBankSizeGet(MV_U32 bankNum) -+{ -+ MV_DRAM_DEC_WIN addrDecWin; -+ -+ /* Check parameters */ -+ if (!MV_TARGET_IS_DRAM(bankNum)) -+ { -+ mvOsPrintf("mvDramIfBankBaseGet: bankNum %d is invalid\n", bankNum); -+ return -1; -+ } -+ /* Get window parameters */ -+ if (MV_OK != mvDramIfWinGet(bankNum, &addrDecWin)) -+ { -+ mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); -+ return -1; -+ } -+ -+ if (MV_TRUE == addrDecWin.enable) -+ { -+ return addrDecWin.addrWin.size; -+ } -+ else -+ { -+ return 0; -+ } -+} -+ -+ -+/******************************************************************************* -+* mvDramIfSizeGet - Get DRAM interface total size. -+* -+* DESCRIPTION: -+* This function get the DRAM total size. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* DRAM total size. In case or paramter is invalid, the function -+* returns -1. -+* -+*******************************************************************************/ -+MV_32 mvDramIfSizeGet(MV_VOID) -+{ -+ MV_U32 totalSize = 0, bankSize = 0, bankNum; -+ -+ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ bankSize = mvDramIfBankSizeGet(bankNum); -+ -+ if (-1 == bankSize) -+ { -+ mvOsPrintf("Dram: mvDramIfSizeGet error with bank %d \n",bankNum); -+ return -1; -+ } -+ else -+ { -+ totalSize += bankSize; -+ } -+ } -+ -+ DB(mvOsPrintf("Dram: Total DRAM size is 0x%x \n",totalSize)); -+ -+ return totalSize; -+} -+ -+/******************************************************************************* -+* mvDramIfBankBaseGet - Get DRAM interface bank base. -+* -+* DESCRIPTION: -+* This function returns the 32 bit base address of a given DRAM bank. -+* -+* INPUT: -+* bankNum - Bank number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* DRAM bank size. If bank is disabled or paramter is invalid, the -+* function returns -1. -+* -+*******************************************************************************/ -+MV_32 mvDramIfBankBaseGet(MV_U32 bankNum) -+{ -+ MV_DRAM_DEC_WIN addrDecWin; -+ -+ /* Check parameters */ -+ if (!MV_TARGET_IS_DRAM(bankNum)) -+ { -+ mvOsPrintf("mvDramIfBankBaseGet: bankNum %d is invalid\n", bankNum); -+ return -1; -+ } -+ /* Get window parameters */ -+ if (MV_OK != mvDramIfWinGet(bankNum, &addrDecWin)) -+ { -+ mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); -+ return -1; -+ } -+ -+ if (MV_TRUE == addrDecWin.enable) -+ { -+ return addrDecWin.addrWin.baseLow; -+ } -+ else -+ { -+ return -1; -+ } -+} -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,179 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvDramIfh -+#define __INCmvDramIfh -+ -+/* includes */ -+#include "ddr1_2/mvDramIfRegs.h" -+#include "ddr1_2/mvDramIfConfig.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+ -+/* defines */ -+/* DRAM Timing parameters */ -+#define SDRAM_TWR 15 /* ns tWr */ -+#define SDRAM_TRFC_64_512M_AT_200MHZ 70 /* ns tRfc for dens 64-512 @ 200MHz */ -+#define SDRAM_TRFC_64_512M 75 /* ns tRfc for dens 64-512 */ -+#define SDRAM_TRFC_1G 120 /* ns tRfc for dens 1GB */ -+#define SDRAM_TR2R_CYC 1 /* cycle for tR2r */ -+#define SDRAM_TR2WW2R_CYC 1 /* cycle for tR2wW2r */ -+ -+/* typedefs */ -+ -+/* enumeration for memory types */ -+typedef enum _mvMemoryType -+{ -+ MEM_TYPE_SDRAM, -+ MEM_TYPE_DDR1, -+ MEM_TYPE_DDR2 -+}MV_MEMORY_TYPE; -+ -+/* enumeration for DDR1 supported CAS Latencies */ -+typedef enum _mvDimmDdr1Cas -+{ -+ DDR1_CL_1_5 = 0x02, -+ DDR1_CL_2 = 0x04, -+ DDR1_CL_2_5 = 0x08, -+ DDR1_CL_3 = 0x10, -+ DDR1_CL_4 = 0x40, -+ DDR1_CL_FAULT -+} MV_DIMM_DDR1_CAS; -+ -+/* enumeration for DDR2 supported CAS Latencies */ -+typedef enum _mvDimmDdr2Cas -+{ -+ DDR2_CL_3 = 0x08, -+ DDR2_CL_4 = 0x10, -+ DDR2_CL_5 = 0x20, -+ DDR2_CL_FAULT -+} MV_DIMM_DDR2_CAS; -+ -+ -+typedef struct _mvDramBankInfo -+{ -+ MV_MEMORY_TYPE memoryType; /* DDR1, DDR2 or SDRAM */ -+ -+ /* DIMM dimensions */ -+ MV_U32 numOfRowAddr; -+ MV_U32 numOfColAddr; -+ MV_U32 dataWidth; -+ MV_U32 errorCheckType; /* ECC , PARITY..*/ -+ MV_U32 sdramWidth; /* 4,8,16 or 32 */ -+ MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ -+ MV_U32 burstLengthSupported; -+ MV_U32 numOfBanksOnEachDevice; -+ MV_U32 suportedCasLatencies; -+ MV_U32 refreshInterval; -+ -+ /* DIMM timing parameters */ -+ MV_U32 minCycleTimeAtMaxCasLatPs; -+ MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; -+ MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; -+ MV_U32 minRowPrechargeTime; -+ MV_U32 minRowActiveToRowActive; -+ MV_U32 minRasToCasDelay; -+ MV_U32 minRasPulseWidth; -+ MV_U32 minWriteRecoveryTime; /* DDR2 only */ -+ MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ -+ MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ -+ MV_U32 minRefreshToActiveCmd; /* DDR2 only */ -+ -+ /* Parameters calculated from the extracted DIMM information */ -+ MV_U32 size; -+ MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit */ -+ MV_U32 numberOfDevices; -+ -+ /* DIMM attributes (MV_TRUE for yes) */ -+ MV_BOOL registeredAddrAndControlInputs; -+ -+}MV_DRAM_BANK_INFO; -+ -+/* This structure describes CPU interface address decode window */ -+typedef struct _mvDramIfDecWin -+{ -+ MV_ADDR_WIN addrWin; /* An address window*/ -+ MV_BOOL enable; /* Address decode window is enabled/disabled */ -+}MV_DRAM_DEC_WIN; -+ -+#include "ddr1_2/mvDram.h" -+ -+/* mvDramIf.h API list */ -+MV_VOID mvDramIfBasicAsmInit(MV_VOID); -+MV_STATUS mvDramIfDetect(MV_U32 forcedCl); -+MV_VOID _mvDramIfConfig(MV_VOID); -+ -+MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); -+MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); -+MV_STATUS mvDramIfWinEnable(MV_TARGET target,MV_BOOL enable); -+MV_32 mvDramIfBankSizeGet(MV_U32 bankNum); -+MV_32 mvDramIfBankBaseGet(MV_U32 bankNum); -+MV_32 mvDramIfSizeGet(MV_VOID); -+ -+#if 0 -+MV_STATUS mvDramIfMbusCtrlSet(MV_XBAR_TARGET *pPizzaArbArray); -+MV_STATUS mvDramIfMbusToutSet(MV_U32 timeout, MV_BOOL enable); -+#endif -+ -+#endif /* __INCmvDramIfh */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfBasicInit.S linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfBasicInit.S ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfBasicInit.S 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfBasicInit.S 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,988 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#define MV_ASMLANGUAGE -+#include "mvSysHwConfig.h" -+#include "mvOsAsm.h" -+#include "mvBoardEnvSpec.h" -+#include "mvCpuIfRegs.h" -+#include "mvDramIfConfig.h" -+#include "mvDramIfRegs.h" -+#include "pex/mvPexRegs.h" -+#include "pci/mvPciRegs.h" -+#include "mvCtrlEnvSpec.h" -+#include "mvCtrlEnvAsm.h" -+#include "cpu/mvCpuArm.h" -+#include "mvCommon.h" -+ -+/* defines */ -+ -+#if !defined(MV_INC_BOARD_DDIM) -+.globl dramBoot1 -+dramBoot1: -+ .word 0 -+ -+/****************************************************************************** -+* -+* -+* -+* -+*******************************************************************************/ -+#if defined(DB_PRPMC) || defined(DB_PEX_PCI) || defined(DB_MNG) -+ -+/* PEX_PCI and PRPMC boards 256 MB*/ -+#define STATIC_SDRAM0_BANK0_SIZE 0x0fff0001 -+#define STATIC_SDRAM_CONFIG 0x03248400 -+#define STATIC_SDRAM_MODE 0x62 -+#define STATIC_DUNIT_CTRL_LOW 0x4041000 -+#define STATIC_SDRAM_ADDR_CTRL 0x00000020 -+#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220 -+#define STATIC_SDRAM_TIME_CTRL_HI 0x0000030F -+#define STATIC_SDRAM_ODT_CTRL_LOW 0x0 -+#define STATIC_SDRAM_ODT_CTRL_HI 0x0 -+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0 -+#define STATIC_SDRAM_EXT_MODE 0x0 -+ -+#elif defined(DB_FPGA) -+ -+/* FPGA DC boards 256 MB*/ -+#define STATIC_SDRAM0_BANK0_SIZE 0x0fff0001 -+#define STATIC_SDRAM_CONFIG 0x03208400 /* 32bit */ -+#define STATIC_SDRAM_MODE 0x22 -+#define STATIC_DUNIT_CTRL_LOW 0x03041000 -+#define STATIC_SDRAM_ADDR_CTRL 0x00000020 -+#define STATIC_SDRAM_TIME_CTRL_LOW 0x11112220 -+#define STATIC_SDRAM_TIME_CTRL_HI 0x0000000D -+#define STATIC_SDRAM_ODT_CTRL_LOW 0x0 -+#define STATIC_SDRAM_ODT_CTRL_HI 0x0 -+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0 -+#define STATIC_SDRAM_EXT_MODE 0x1 -+ -+#elif defined(RD_88F6183GP) || defined(DB_CUSTOMER) -+ -+/* Customer 1 DDR2 2 devices 512Mbit by 16 bit */ -+#define STATIC_SDRAM0_BANK0_SIZE 0x07ff0001 -+#define STATIC_SDRAM_CONFIG 0x03158400 -+#define STATIC_SDRAM_MODE 0x452 -+#define STATIC_DUNIT_CTRL_LOW 0x06041000 -+#define STATIC_SDRAM_ADDR_CTRL 0x00000020 -+#define STATIC_SDRAM_TIME_CTRL_LOW 0x11912220 -+#define STATIC_SDRAM_TIME_CTRL_HI 0x00000502 -+#define STATIC_SDRAM_ODT_CTRL_LOW 0x00010000 -+#define STATIC_SDRAM_ODT_CTRL_HI 0x00000002 -+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x00000601 -+#define STATIC_SDRAM_EXT_MODE 0x00000440 -+ -+ -+#elif defined(RD_88F6183AP) -+ -+/* DDR2 1 devices 512Mbit by 16 bit */ -+#define STATIC_SDRAM0_BANK0_SIZE 0x03ff0001 -+#define STATIC_SDRAM_CONFIG 0x1f154400 -+#define STATIC_SDRAM_MODE 0x432 -+#define STATIC_DUNIT_CTRL_LOW 0x04041000 -+#define STATIC_SDRAM_ADDR_CTRL 0x00000020 -+#define STATIC_SDRAM_TIME_CTRL_LOW 0x11912220 -+#define STATIC_SDRAM_TIME_CTRL_HI 0x00000502 -+#define STATIC_SDRAM_ODT_CTRL_LOW 0x00010000 -+#define STATIC_SDRAM_ODT_CTRL_HI 0x00000002 -+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x00000601 -+#define STATIC_SDRAM_EXT_MODE 0x00000440 -+ -+/* 6082L MARVELL DIMM */ -+#elif defined(DB_88F6082LBP) -+#define STATIC_SDRAM0_BANK0_SIZE 0x07ff0001 -+#define STATIC_SDRAM_CONFIG 0x7f158400 -+#define STATIC_SDRAM_MODE 0x432 -+#define STATIC_DUNIT_CTRL_LOW 0x04041040 -+#define STATIC_SDRAM_ADDR_CTRL 0x00000020 -+#define STATIC_SDRAM_TIME_CTRL_LOW 0x11612220 -+#define STATIC_SDRAM_TIME_CTRL_HI 0x00000501 -+#define STATIC_SDRAM_ODT_CTRL_LOW 0x00010000 -+#define STATIC_SDRAM_ODT_CTRL_HI 0x00000002 -+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x00000a01 -+#define STATIC_SDRAM_EXT_MODE 0x00000440 -+ -+#elif defined(RD_88W8660_AP82S) -+ -+/* Shark RD */ -+ -+#if defined(MV_DRAM_32M) -+#define STATIC_SDRAM0_BANK0_SIZE 0x01ff0001 -+#define STATIC_SDRAM_ADDR_CTRL 0x00000010 -+#elif defined(MV_DRAM_16M) -+ -+#define STATIC_SDRAM0_BANK0_SIZE 0x00ff0001 -+#define STATIC_SDRAM_ADDR_CTRL 0x00000000 -+ -+#else -+#error "NO DDR size selected" -+#endif -+ -+#define STATIC_SDRAM_CONFIG 0x03144400 -+#define STATIC_SDRAM_MODE 0x62 -+#define STATIC_DUNIT_CTRL_LOW 0x4041000 -+ -+#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220 -+#define STATIC_SDRAM_TIME_CTRL_HI 0x0000040b -+#define STATIC_SDRAM_ODT_CTRL_LOW 0x0 -+#define STATIC_SDRAM_ODT_CTRL_HI 0x0 -+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0 -+#define STATIC_SDRAM_EXT_MODE 0x0 -+ -+#elif defined(RD_88W8660) -+ -+/* Shark RD */ -+#define STATIC_SDRAM0_BANK0_SIZE 0x03ff0001 -+#define STATIC_SDRAM_CONFIG 0x03144400 -+#define STATIC_SDRAM_MODE 0x62 -+#define STATIC_DUNIT_CTRL_LOW 0x4041000 -+#define STATIC_SDRAM_ADDR_CTRL 0x00000010 -+#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220 -+#define STATIC_SDRAM_TIME_CTRL_HI 0x0000040b -+#define STATIC_SDRAM_ODT_CTRL_LOW 0x0 -+#define STATIC_SDRAM_ODT_CTRL_HI 0x0 -+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0 -+#define STATIC_SDRAM_EXT_MODE 0x0 -+ -+#else /* NAS */ -+ -+ -+#if defined(RD_88F5182) -+ -+#if defined(MV_88F5082) -+#define STATIC_SDRAM0_BANK0_SIZE 0x3ff0001 -+#define STATIC_SDRAM_ADDR_CTRL 0x20 -+#else -+#define STATIC_SDRAM0_BANK0_SIZE 0x7ff0001 -+#define STATIC_SDRAM_ADDR_CTRL 0x20 -+#endif -+ -+#elif defined(RD_88F5182_3) -+ -+#if defined(MV_88F5082) -+#define STATIC_SDRAM0_BANK0_SIZE 0x3ff0001 -+#define STATIC_SDRAM_ADDR_CTRL 0x20 -+#else -+#define STATIC_SDRAM0_BANK0_SIZE 0x7ff0001 -+#define STATIC_SDRAM_ADDR_CTRL 0x20 -+#endif -+ -+#else -+ -+#define STATIC_SDRAM0_BANK0_SIZE 0x1ff0001 -+#define STATIC_SDRAM_ADDR_CTRL 0x0 -+ -+#endif -+ -+#if defined(MV_88F5082) -+#define STATIC_SDRAM_CONFIG 0x3144400 -+#else -+#define STATIC_SDRAM_CONFIG 0x3148400 -+#endif -+#define STATIC_SDRAM_MODE 0x62 -+#define STATIC_DUNIT_CTRL_LOW 0x4041000 -+#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220 -+#define STATIC_SDRAM_TIME_CTRL_HI 0x40c -+#define STATIC_SDRAM_ODT_CTRL_LOW 0x0 -+#define STATIC_SDRAM_ODT_CTRL_HI 0x0 -+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0 -+#define STATIC_SDRAM_EXT_MODE 0x0 -+ -+#endif -+ -+ .globl _mvDramIfStaticInit -+_mvDramIfStaticInit: -+ -+ mov r11, LR /* Save link register */ -+ mov r10, r2 -+ -+ /* If we boot from NAND jump to DRAM sddress */ -+ -+ mov r5, #1 -+ ldr r6, =dramBoot1 -+ str r5, [r6] /* We started executing from DRAM */ -+ -+ ldr r6, dramBoot1 -+ cmp r6, #0 -+ bne 1f -+ -+ -+ /* set all dram windows to 0 */ -+ mov r6, #0 -+ MV_REG_WRITE_ASM(r6, r5, 0x1504) -+ MV_REG_WRITE_ASM(r6, r5, 0x150c) -+ MV_REG_WRITE_ASM(r6, r5, 0x1514) -+ MV_REG_WRITE_ASM(r6, r5, 0x151c) -+ -+ /* set all dram configuration in temp registers */ -+ ldr r6, = STATIC_SDRAM0_BANK0_SIZE -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG0) -+ ldr r6, = STATIC_SDRAM_CONFIG -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG1) -+ ldr r6, = STATIC_SDRAM_MODE -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG2) -+ ldr r6, = STATIC_DUNIT_CTRL_LOW -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG3) -+ ldr r6, = STATIC_SDRAM_ADDR_CTRL -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG4) -+ ldr r6, = STATIC_SDRAM_TIME_CTRL_LOW -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG5) -+ ldr r6, = STATIC_SDRAM_TIME_CTRL_HI -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG6) -+ ldr r6, = STATIC_SDRAM_ODT_CTRL_LOW -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG7) -+ ldr r6, = STATIC_SDRAM_ODT_CTRL_HI -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG8) -+ ldr r6, = STATIC_SDRAM_DUNIT_ODT_CTRL -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG9) -+ ldr r6, = STATIC_SDRAM_EXT_MODE -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG10) -+ -+ mov sp, #0 -+ bl _mvDramIfConfig -+1: -+ mov r2, r10 -+ mov PC, r11 /* r11 is saved link register */ -+ -+#else /* #if !defined(MV_INC_BOARD_DDIM) */ -+ -+.globl dramBoot1 -+dramBoot1: -+ .word 0 -+ -+/******************************************************************************* -+* mvDramIfBasicInit - Basic initialization of DRAM interface -+* -+* DESCRIPTION: -+* The function will initialize the DRAM for basic usage. The function -+* will use the TWSI assembly API to extract DIMM parameters according -+* to which DRAM interface will be initialized. -+* The function referes to the following DRAM parameters: -+* 1) DIMM is registered or not. -+* 2) DIMM width detection. -+* 3) DIMM density. -+* -+* INPUT: -+* r3 - required size for initial DRAM. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+* Note: -+* r4 holds I2C EEPROM address -+* r5 holds SDRAM register base address -+* r7 holds returned values -+* r8 holds SDRAM various configuration registers value. -+* r11 holds return function address. -+*******************************************************************************/ -+/* Setting the offsets of the I2C registers */ -+#define NUM_OF_ROWS_OFFSET 3 -+#define NUM_OF_COLS_OFFSET 4 -+#define NUM_OF_RANKS 5 -+#define SDRAM_WIDTH_OFFSET 13 -+#define NUM_OF_BANKS_OFFSET 17 -+#define SUPPORTED_CL_OFFSET 18 -+#define DIMM_TYPE_INFO_OFFSET 20 /* DDR2 only */ -+#define SDRAM_MODULES_ATTR_OFFSET 21 -+ -+#define DRAM_DEV_DENSITY_128M 0x080 -+#define DRAM_DEV_DENSITY_256M 0x100 -+#define DRAM_DEV_DENSITY_512M 0x200 -+ .globl _mvDramIfBasicInit -+ .extern _i2cInit -+ -+_mvDramIfBasicInit: -+ -+ mov r11, LR /* Save link register */ -+ -+ mov r5, #1 -+ ldr r8, =dramBoot1 -+ str r5, [r8] /* We started executing from DRAM */ -+ -+ /* If we boot from NAND jump to DRAM sddress */ -+ ldr r8, dramBoot1 -+ cmp r8, #0 -+ movne pc, r11 -+ -+ -+ -+ bl _i2cInit /* Initialize TWSI master */ -+ -+ /* Get default SDRAM Config values */ -+ MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG) -+ bic r8, r8, #SDRAM_DCFG_MASK -+ -+ -+ /* Read device ID */ -+ MV_CTRL_MODEL_GET_ASM(r4, r5); -+ -+ /* Return if OrionN */ -+ ldr r5, =MV_5180_DEV_ID -+ cmp r4, r5 -+ beq cat_through_end -+ -+ /* Return if Orion1 */ -+ ldr r5, =MV_5181_DEV_ID -+ cmp r4, r5 -+ beq cat_through_end -+ -+ /* Return if Nas */ -+ ldr r5, =MV_5182_DEV_ID -+ cmp r4, r5 -+ beq cat_through_end -+ -+ /* Return if Shark */ -+ ldr r5, =MV_8660_DEV_ID -+ cmp r4, r5 -+ beq cat_through_end -+ -+ /* goto calcConfigReg if bigger than Orion2*/ -+ ldr r5, =MV_5281_DEV_ID -+ cmp r4, r5 -+ bne cat_through -+ -+cat_through: -+ /* set cat through - for better performance - in orion2 b0 and higher*/ -+ orr r8, r8, #SDRAM_CATTHR_EN -+ -+cat_through_end: -+ -+ -+ /* Get registered/non registered info from DIMM */ -+ bl _is_Registered -+ beq nonRegistered -+ -+setRegistered: -+ orr r8, r8, #SDRAM_REGISTERED /* Set registered bit(17) */ -+ -+nonRegistered: -+ /* Get SDRAM width */ -+ bl _get_width -+ -+ orr r6, r8, #SDRAM_DCFG_X16_DEV /* x16 devices */ -+ cmp r7, #16 -+ beq setConfigReg -+ -+ orr r6, r8, #SDRAM_DCFG_X8_DEV /* x8 devices */ -+ cmp r7, #8 -+ beq setConfigReg -+ -+ /* This is an error. return */ -+ b exit_ddrAutoConfig -+ -+setConfigReg: -+ mov r8, r6 -+ ldr r6, =SDRAM_CONFIG_DV -+ orr r8, r8, r6 /* Add default settings */ -+ mov r6, r8 /* Do not swap r8 content */ -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_CONFIG_REG) -+ -+ /* Set maximum CL supported by DIMM */ -+ bl _get_CAL -+ -+ /* r7 is DIMM supported CAS (e.g: 3 --> 0x1C) */ -+ clz r6, r7 -+ rsb r6, r6, #31 /* r6 = the bit number of MAX CAS supported */ -+ -+ /* Check the DDR version */ -+ tst r8, #SDRAM_DTYPE_DDR2 -+ bne casDdr2 -+ -+casDdr1: -+ ldr r7, =3 /* stBurstDel field value */ -+ ldr r8, =0x52 /* Assuming MAX CL = 1.5 */ -+ cmp r6, #1 /* If CL = 1.5 break */ -+ beq setModeReg -+ -+ ldr r7, =3 /* stBurstDel field value */ -+ ldr r8, =0x22 /* Assuming MAX CL = 2 */ -+ cmp r6, #2 /* If CL = 2 break */ -+ beq setModeReg -+ -+ ldr r7, =4 /* stBurstDel field value */ -+ ldr r8, =0x62 /* Assuming MAX CL = 2.5 */ -+ cmp r6, #3 /* If CL = 2.5 break */ -+ beq setModeReg -+ -+ ldr r7, =4 /* stBurstDel field value */ -+ ldr r8, =0x32 /* Assuming MAX CL = 3 */ -+ cmp r6, #4 /* If CL = 3 break */ -+ beq setModeReg -+ -+ ldr r7, =5 /* stBurstDel field value */ -+ ldr r8, =0x42 /* Assuming MAX CL = 4 */ -+ cmp r6, #6 /* If CL = 4 break */ -+ b setModeReg -+ -+ b exit_ddrAutoConfig /* This is an error !! */ -+ -+casDdr2: -+ ldr r7, =4 /* stBurstDel field value */ -+ ldr r8, =0x32 /* Assuming MAX CL = 3 */ -+ cmp r6, #3 /* If CL = 3 break */ -+ beq casDdr2Cont -+ -+ ldr r7, =5 /* stBurstDel field value */ -+ ldr r8, =0x42 /* Assuming MAX CL = 4 */ -+ cmp r6, #4 /* If CL = 4 break */ -+ beq casDdr2Cont -+ -+ /* CL 5 currently unsupported. We use CL 4 instead */ -+ ldr r7, =5 /* stBurstDel field value */ -+ ldr r8, =0x42 /* Assuming MAX CL = 5 */ -+ cmp r6, #5 /* If CL = 5 break */ -+ beq casDdr2Cont -+ -+ b exit_ddrAutoConfig /* This is an error !! */ -+casDdr2Cont: -+ /* Write recovery for auto-precharge relevant only in DDR2 */ -+ orr r8, r8, #0x400 /* Default value */ -+ -+setModeReg: -+ /* The CPU must not attempt to change the SDRAM Mode register setting */ -+ /* prior to DRAM controller completion of the DRAM initialization */ -+ /* sequence. To guarantee this restriction, it is recommended that */ -+ /* the CPU sets the SDRAM Operation register to NOP command, performs */ -+ /* read polling until the register is back in Normal operation value, */ -+ /* and then sets SDRAM Mode register to it's new value. */ -+ -+ /* write 'nop' to SDRAM operation */ -+ mov r6, #0x5 /* 'NOP' command */ -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG) -+ -+ /* poll SDRAM operation. Make sure its back to normal operation */ -+_sdramOpPoll1: -+ ldr r6, [r5] -+ cmp r6, #0 /* '0' = Normal SDRAM Mode */ -+ bne _sdramOpPoll1 -+ -+ /* Now its safe to write new value to SDRAM Mode register */ -+ MV_REG_WRITE_ASM (r8, r5, SDRAM_MODE_REG) -+ -+ /* Make the Dunit write the DRAM its new mode */ -+ mov r6, #0x3 /* Mode Register Set command */ -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG) -+ -+ /* poll SDRAM operation. Make sure its back to normal operation */ -+_sdramOpPoll2: -+ ldr r6, [r5] -+ cmp r6, #0 /* '0' = Normal SDRAM Mode */ -+ bne _sdramOpPoll2 -+ -+ /* Set Dunit control register according to max CL detected */ -+ /* If we use registered DIMM, add 1 to stBurstDel */ -+ MV_REG_READ_ASM (r6, r5, SDRAM_CONFIG_REG) -+ tst r6, #SDRAM_REGISTERED -+ beq setDunitReg -+ add r7, r7, #1 -+ -+setDunitReg: -+ ldr r6, =SDRAM_DUNIT_CTRL_LOW_DV -+ orr r6, r6, r7, LSL #SDRAM_ST_BURST_DEL_OFFS -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) -+ -+ -+ /* DIMM density configuration*/ -+ /* Density = (1 << (rowNum + colNum)) * dramWidth * dramBankNum */ -+Density: -+ bl _getDensity -+ mov r8, r7 -+ mov r8, r8, LSR #20 /* Move density 20 bits to the right */ -+ /* For example 0x10000000 --> 0x1000 */ -+ -+ mov r6, #0x00 -+ cmp r8, #DRAM_DEV_DENSITY_128M -+ beq densCont -+ -+ mov r6, #0x10 -+ cmp r8, #DRAM_DEV_DENSITY_256M -+ beq densCont -+ -+ mov r6, #0x20 -+ cmp r8, #DRAM_DEV_DENSITY_512M -+ beq densCont -+ -+ /* This is an error. return */ -+ b exit_ddrAutoConfig -+ -+densCont: -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_REG) -+ -+ /* Config DDR2 registers (Extended mode, ODTs and pad calibration) */ -+ MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG) -+ tst r8, #SDRAM_DTYPE_DDR2 -+ beq _extModeODTEnd -+ -+ -+ /* Set DDR Extended Mode register for working with CS[0] */ -+ /* write 'nop' to SDRAM operation */ -+ mov r6, #0x5 /* 'NOP' command */ -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG) -+ -+ /* poll SDRAM operation. Make sure its back to normal operation */ -+_sdramOpPoll3: -+ ldr r6, [r5] -+ cmp r6, #0 /* '0' = Normal SDRAM Mode */ -+ bne _sdramOpPoll3 -+ -+ /* Now its safe to write new value to SDRAM Extended Mode register */ -+ ldr r6, =DDR_SDRAM_EXT_MODE_CS0_DV -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_EXTENDED_MODE_REG) -+ -+ /* Make the Dunit write the DRAM its new extended mode */ -+ mov r6, #0x4 /* Extended Mode Register Set command */ -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG) -+ -+ /* poll SDRAM operation. Make sure its back to normal operation */ -+_sdramOpPoll4: -+ ldr r6, [r5] -+ cmp r6, #0 /* '0' = Normal SDRAM Mode */ -+ bne _sdramOpPoll4 -+ -+ /* ODT configuration is done for single bank CS[0] only */ -+ /* Config DDR2 On Die Termination (ODT) registers */ -+ ldr r6, =DDR2_ODT_CTRL_LOW_CS0_DV -+ MV_REG_WRITE_ASM (r6, r5, DDR2_SDRAM_ODT_CTRL_LOW_REG) -+ -+ ldr r6, =DDR2_ODT_CTRL_HIGH_CS0_DV -+ MV_REG_WRITE_ASM (r6, r5, DDR2_SDRAM_ODT_CTRL_HIGH_REG) -+ -+ ldr r6, =DDR2_DUNIT_ODT_CTRL_CS0_DV -+ MV_REG_WRITE_ASM (r6, r5, DDR2_DUNIT_ODT_CONTROL_REG) -+ -+ -+ /* we will check what device we are running and perform -+ Initialization according to device value */ -+ -+_extModeODTEnd: -+ -+ /* Implement Guideline (GL# MEM-2) P_CAL Automatic Calibration */ -+ /* Does Not Work for Address/Control and Data Pads. */ -+ /* Relevant for: 88F5181-A1/B0 and 88F5281-A0 */ -+ -+ /* Read device ID */ -+ MV_CTRL_MODEL_GET_ASM(r6, r5); -+ /* Read device revision */ -+ MV_CTRL_REV_GET_ASM(r8, r5); -+ -+ /* Continue if OrionN */ -+ ldr r5, =MV_5180_DEV_ID -+ cmp r6, r5 -+ bne 1f -+ b glMem2End -+1: -+ -+ /* Continue if Orion1 and device revision B1 */ -+ ldr r5, =MV_5181_DEV_ID -+ cmp r6, r5 -+ bne 1f -+ -+ cmp r8, #MV_5181_B1_REV -+ bge glMem2End -+ b glMem2Start -+1: -+ -+ /* Orion NAS */ -+ ldr r5, =MV_5182_DEV_ID -+ cmp r6, r5 -+ beq glMem2Start -+ -+ /* Orion Shark */ -+ ldr r5, =MV_8660_DEV_ID -+ cmp r6, r5 -+ beq glMem2Start -+ -+ b glMem2End -+ -+glMem2Start: -+ -+ /* DDR SDRAM Address/Control Pads Calibration */ -+ MV_REG_READ_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) -+ -+ /* Set Bit [31] to make the register writable */ -+ orr r8, r6, #SDRAM_WR_EN -+ -+ MV_REG_WRITE_ASM (r8, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) -+ -+ bic r6, r6, #SDRAM_WR_EN /* Make register read-only */ -+ bic r6, r6, #SDRAM_TUNE_EN /* Disable auto calibration */ -+ bic r6, r6, #SDRAM_DRVN_MASK /* Clear r5[5:0] */ -+ bic r6, r6, #SDRAM_DRVP_MASK /* Clear r5[11:6] */ -+ -+ /* Get the final N locked value of driving strength [22:17] */ -+ mov r5, r6 -+ mov r5, r5, LSL #9 -+ mov r5, r5, LSR #26 /* r5[5:0] = r6[22:17] */ -+ orr r5, r5, r5, LSL #6 /* r5[11:6] = r5[5:0] */ -+ -+ /* Write to both bits [5:0] and bits [11:6] */ -+ orr r6, r6, r5 -+ -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) -+ -+ -+ /* DDR SDRAM Data Pads Calibration */ -+ MV_REG_READ_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG) -+ -+ /* Set Bit [31] to make the register writable */ -+ orr r8, r6, #SDRAM_WR_EN -+ -+ MV_REG_WRITE_ASM (r8, r5, SDRAM_DATA_PADS_CAL_REG) -+ -+ bic r6, r6, #SDRAM_WR_EN /* Make register read-only */ -+ bic r6, r6, #SDRAM_TUNE_EN /* Disable auto calibration */ -+ bic r6, r6, #SDRAM_DRVN_MASK /* Clear r5[5:0] */ -+ bic r6, r6, #SDRAM_DRVP_MASK /* Clear r5[11:6] */ -+ -+ /* Get the final N locked value of driving strength [22:17] */ -+ mov r5, r6 -+ mov r5, r5, LSL #9 -+ mov r5, r5, LSR #26 -+ orr r5, r5, r5, LSL #6 /* r5[5:0] = r6[22:17] */ -+ -+ /* Write to both bits [5:0] and bits [11:6] */ -+ orr r6, r6, r5 -+ -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG) -+ -+glMem2End: -+ /* Implement Guideline (GL# MEM-3) Drive Strength Value */ -+ /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */ -+ -+ /* Get SDRAM Config value */ -+ MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG) -+ -+ /* Get DIMM type */ -+ tst r8, #SDRAM_DTYPE_DDR2 -+ beq ddr1StrengthVal -+ -+ddr2StrengthVal: -+ ldr r4, =DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV -+ ldr r8, =DDR2_DATA_PAD_STRENGTH_TYPICAL_DV -+ b setDrvStrength -+ddr1StrengthVal: -+ ldr r4, =DDR1_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV -+ ldr r8, =DDR1_DATA_PAD_STRENGTH_TYPICAL_DV -+ -+setDrvStrength: -+ /* DDR SDRAM Address/Control Pads Calibration */ -+ MV_REG_READ_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) -+ -+ orr r6, r6, #SDRAM_WR_EN /* Make register writeable */ -+ -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) -+ HTOLL(r6,r5) -+ -+ bic r6, r6, #SDRAM_WR_EN /* Make register read-only */ -+ bic r6, r6, #SDRAM_PRE_DRIVER_STRENGTH_MASK -+ orr r6, r4, r6 /* Set default value for DDR */ -+ -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) -+ -+ -+ /* DDR SDRAM Data Pads Calibration */ -+ MV_REG_READ_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG) -+ -+ orr r6, r6, #SDRAM_WR_EN /* Make register writeable */ -+ -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG) -+ HTOLL(r6,r5) -+ -+ bic r6, r6, #SDRAM_WR_EN /* Make register read-only */ -+ bic r6, r6, #SDRAM_PRE_DRIVER_STRENGTH_MASK -+ orr r6, r8, r6 /* Set default value for DDR */ -+ -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG) -+ -+ -+ /* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */ -+ /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */ -+ /* Get the "sample on reset" register for the DDR frequancy */ -+ -+#if defined(MV_RUN_FROM_FLASH) -+ /* Calc the absolute address of the _cpuARMDDRCLK[] in the boot flash */ -+ ldr r7, = _cpuARMDDRCLK -+ ldr r4, =_start -+ ldr r4, [r4] -+ sub r7, r7, r4 -+ ldr r4, = Lrom_start_of_data -+ ldr r4, [r4] -+ add r7, r4, r7 -+#else -+ /* Calc the absolute address of the _cpuARMDDRCLK[] in the boot flash */ -+ ldr r7, = _cpuARMDDRCLK -+ ldr r4, =_start -+ sub r7, r7, r4 -+ add r7, r7, #CFG_MONITOR_BASE -+#endif -+ /* Get the "sample on reset" register for the DDR frequancy */ -+ MV_REG_READ_ASM (r4, r5, MPP_SAMPLE_AT_RESET) -+ ldr r5, =MSAR_ARMDDRCLCK_MASK -+ and r5, r4, r5 -+#if 0 /* YOTAM TO BE FIX */ -+ mov r5, r5, LSR #MSAR_ARMDDRCLCK_OFFS -+#endif -+ -+ /* Read device ID */ -+ MV_CTRL_MODEL_GET_ASM(r6, r8); -+ -+ /* Continue if TC90 */ -+ ldr r8, =MV_1281_DEV_ID -+ cmp r6, r6 -+ beq armClkMsb -+ -+ /* Continue if Orion2 */ -+ ldr r8, =MV_5281_DEV_ID -+ cmp r6, r8 -+#if 0 /* YOTAM TO BE FIX */ -+ bne 1f -+#endif -+ -+armClkMsb: -+#if 0 /* YOTAM TO BE FIX */ -+ tst r4, #MSAR_ARMDDRCLCK_H_MASK -+ beq 1f -+ orr r5, r5, #BIT4 -+1: -+ ldr r4, =MV_CPU_ARM_CLK_ELM_SIZE -+ mul r5, r4, r5 -+ add r7, r7, r5 -+ add r7, r7, #MV_CPU_ARM_CLK_DDR_OFF -+ ldr r5, [r7] -+#endif -+ -+ /* Get SDRAM Config value */ -+ MV_REG_READ_ASM (r8, r4, SDRAM_CONFIG_REG) -+ -+ /* Get DIMM type */ -+ tst r8, #SDRAM_DTYPE_DDR2 -+ beq ddr1FtdllVal -+ -+ddr2FtdllVal: -+ ldr r4, =FTDLL_DDR2_250MHZ -+ ldr r7, =_250MHz -+ cmp r5, r7 -+ beq setFtdllReg -+ ldr r4, =FTDLL_DDR2_200MHZ -+ ldr r7, =_200MHz -+ cmp r5, r7 -+ beq setFtdllReg -+ ldr r4, =FTDLL_DDR2_166MHZ -+ ldr r7, =_166MHz -+ cmp r5, r7 -+ beq setFtdllReg -+ ldr r4, =FTDLL_DDR2_133MHZ -+ b setFtdllReg -+ -+ddr1FtdllVal: -+ ldr r4, =FTDLL_DDR1_200MHZ -+ ldr r7, =_200MHz -+ cmp r5, r7 -+ beq setFtdllReg -+ ldr r4, =FTDLL_DDR1_166MHZ -+ ldr r7, =_166MHz -+ cmp r5, r7 -+ beq setFtdllReg -+ ldr r4, =FTDLL_DDR1_133MHZ -+ ldr r7, =_133MHz -+ cmp r5, r7 -+ beq setFtdllReg -+ ldr r4, =0 -+ -+setFtdllReg: -+ -+#if !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L) -+ MV_REG_READ_ASM (r8, r5, SDRAM_FTDLL_CONFIG_REG) -+ orr r8, r8, r4 -+ MV_REG_WRITE_ASM (r8, r5, SDRAM_FTDLL_CONFIG_REG) -+ bic r8, r8, #1 -+ MV_REG_WRITE_ASM (r8, r5, SDRAM_FTDLL_CONFIG_REG) -+#endif /* !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L)*/ -+ -+ -+setTimingReg: -+ /* Set default Timing parameters */ -+ MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG) -+ tst r8, #SDRAM_DTYPE_DDR2 -+ bne ddr2TimeParam -+ -+ddr1TimeParam: -+ ldr r6, =DDR1_TIMING_LOW_DV -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_LOW_REG) -+ ldr r6, =DDR1_TIMING_HIGH_DV -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_HIGH_REG) -+ b timeParamDone -+ -+ddr2TimeParam: -+ ldr r6, =DDR2_TIMING_LOW_DV -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_LOW_REG) -+ ldr r6, =DDR2_TIMING_HIGH_DV -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_HIGH_REG) -+ -+timeParamDone: -+ /* Open CS[0] window to requested size and enable it. Disable other */ -+ /* windows */ -+ ldr r6, =SCBAR_BASE_MASK -+ sub r3, r3, #1 -+ and r3, r3, r6 -+ orr r3, r3, #1 /* Enable bank */ -+ MV_REG_WRITE_ASM (r3, r5, SDRAM_SIZE_REG(0)) -+ ldr r6, =0 -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(1)) -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(2)) -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(3)) -+ -+exit_ddrAutoConfig: -+ mov PC, r11 /* r11 is saved link register */ -+ -+ -+/***************************************************************************************/ -+/* r4 holds I2C EEPROM address -+ * r7 holds I2C EEPROM offset parameter for i2cRead and its --> returned value -+ * r8 holds SDRAM various configuration registers value. -+ * r13 holds Link register -+ */ -+/**************************/ -+_getDensity: -+ mov r13, LR /* Save link register */ -+ -+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ -+ mov r7, #NUM_OF_ROWS_OFFSET /* offset 3 */ -+ bl _i2cRead -+ mov r8, r7 /* r8 save number of rows */ -+ -+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ -+ mov r7, #NUM_OF_COLS_OFFSET /* offset 4 */ -+ bl _i2cRead -+ add r8, r8, r7 /* r8 = number of rows + number of col */ -+ -+ mov r7, #0x1 -+ mov r8, r7, LSL r8 /* r8 = (1 << r8) */ -+ -+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ -+ mov r7, #SDRAM_WIDTH_OFFSET /* offset 13 */ -+ bl _i2cRead -+ mul r8, r7, r8 -+ -+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ -+ mov r7, #NUM_OF_BANKS_OFFSET /* offset 17 */ -+ bl _i2cRead -+ mul r7, r8, r7 -+ -+ mov PC, r13 -+ -+/**************************/ -+_get_width: -+ mov r13, LR /* Save link register */ -+ -+ /* Get SDRAM width (SPD offset 13) */ -+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ -+ mov r7, #SDRAM_WIDTH_OFFSET -+ bl _i2cRead /* result in r7 */ -+ -+ mov PC, r13 -+ -+/**************************/ -+_get_CAL: -+ mov r13, LR /* Save link register */ -+ -+ /* Set maximum CL supported by DIMM */ -+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ -+ mov r7, #SUPPORTED_CL_OFFSET /* offset 18 */ -+ bl _i2cRead -+ -+ mov PC, r13 -+ -+/**************************/ -+/* R8 - sdram configuration register. -+ * Return value in flag if no-registered then Z-flag is set -+ */ -+_is_Registered: -+ mov r13, LR /* Save link register */ -+ -+ /* Get registered/non registered info from DIMM */ -+ tst r8, #SDRAM_DTYPE_DDR2 -+ bne regDdr2 -+ -+regDdr1: -+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ -+ mov r7, #SDRAM_MODULES_ATTR_OFFSET -+ bl _i2cRead /* result in r7 */ -+ tst r7, #0x2 -+ b exit -+regDdr2: -+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ -+ mov r7, #DIMM_TYPE_INFO_OFFSET -+ bl _i2cRead /* result in r7 */ -+ tst r7, #0x11 /* DIMM type = regular RDIMM (0x01) */ -+ /* or Mini-RDIMM (0x10) */ -+exit: -+ mov PC, r13 -+ -+ -+#endif -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.S linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.S ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.S 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.S 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,668 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+/******************************************************************************* -+* mvDramIfBasicAsm.s -+* -+* DESCRIPTION: -+* Memory full detection and best timing configuration is done in -+* C code. C runtime environment requires a stack. This module API -+* initialize DRAM interface chip select 0 for basic functionality for -+* the use of stack. -+* The module API assumes DRAM information is stored in I2C EEPROM reside -+* in a given I2C address MV_BOARD_DIMM0_I2C_ADDR. The I2C EEPROM -+* internal data structure is assumed to be orgenzied in common DRAM -+* vendor SPD structure. -+* NOTE: DFCDL values are assumed to be already initialized prior to -+* this module API activity. -+* -+* -+* DEPENDENCIES: -+* None. -+* -+*******************************************************************************/ -+ -+/* includes */ -+#define MV_ASMLANGUAGE -+#include "mvOsAsm.h" -+#include "mvSysHwConfig.h" -+#include "mvDramIfRegs.h" -+#include "mvDramIfConfig.h" -+#include "mvCpuIfRegs.h" -+#include "pex/mvPexRegs.h" -+#include "pci/mvPciRegs.h" -+#include "mvCtrlEnvSpec.h" -+#include "mvCtrlEnvAsm.h" -+#include "cpu/mvCpuArm.h" -+#include "mvCommon.h" -+ -+/* defines */ -+ -+/* locals */ -+.data -+.globl _mvDramIfConfig -+ -+.text -+ -+/******************************************************************************* -+* _mvDramIfConfig - Basic DRAM interface initialization. -+* -+* DESCRIPTION: -+* The function will initialize the following DRAM parameters using the -+* values prepared by mvDramIfDetect routine. Values are located -+* in predefined registers. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+ -+_mvDramIfConfig: -+ -+ /* Save register on stack */ -+ cmp sp, #0 -+ beq no_stack_s -+save_on_stack: -+ stmdb sp!, {r1, r2, r3, r4, r7, r11} -+no_stack_s: -+ -+ /* 1) Write to SDRAM coniguration register */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG1) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + SDRAM_CONFIG_REG) -+ str r4, [r1] -+ -+ /* 2) Write Dunit control low register */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG3) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + SDRAM_DUNIT_CTRL_REG) -+ str r4, [r1] -+ -+ /* 3) Write SDRAM address control register */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG4) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + SDRAM_ADDR_CTRL_REG) -+ str r4, [r1] -+ -+ /* 4) Write SDRAM bank 0 size register */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG0) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + SDRAM_SIZE_REG(0)) -+ str r4, [r1] -+ -+ /* 5) Write SDRAM open pages control register */ -+ ldr r1, =(INTER_REGS_BASE + SDRAM_OPEN_PAGE_CTRL_REG) -+ ldr r4, =SDRAM_OPEN_PAGES_CTRL_REG_DV -+ str r4, [r1] -+ -+ /* 6) Write SDRAM timing Low register */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG5) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_LOW_REG) -+ str r4, [r1] -+ -+ /* 7) Write SDRAM timing High register */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG6) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_HIGH_REG) -+ str r4, [r1] -+ -+ /* 8) Write SDRAM mode register */ -+ /* The CPU must not attempt to change the SDRAM Mode register setting */ -+ /* prior to DRAM controller completion of the DRAM initialization */ -+ /* sequence. To guarantee this restriction, it is recommended that */ -+ /* the CPU sets the SDRAM Operation register to NOP command, performs */ -+ /* read polling until the register is back in Normal operation value, */ -+ /* and then sets SDRAM Mode register to it’s new value. */ -+ -+ /* 8.1 write 'nop' to SDRAM operation */ -+ mov r4, #0x5 /* 'NOP' command */ -+ MV_REG_WRITE_ASM(r4, r1, SDRAM_OPERATION_REG) -+ -+ /* 8.2 poll SDRAM operation. Make sure its back to normal operation */ -+_sdramOpPoll1: -+ ldr r4, [r1] -+ cmp r4, #0 /* '0' = Normal SDRAM Mode */ -+ bne _sdramOpPoll1 -+ -+ /* 8.3 Now its safe to write new value to SDRAM Mode register */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG2) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + SDRAM_MODE_REG) -+ str r4, [r1] -+ -+ /* 8.4 Make the Dunit write the DRAM its new mode */ -+ mov r4, #0x3 /* Mode Register Set command */ -+ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) -+ -+ /* 8.5 poll SDRAM operation. Make sure its back to normal operation */ -+_sdramOpPoll2: -+ ldr r4, [r1] -+ cmp r4, #0 /* '0' = Normal SDRAM Mode */ -+ bne _sdramOpPoll2 -+ -+#ifndef DB_FPGA -+ /* Config DDR2 registers (Extended mode, ODTs and pad calibration) */ -+ MV_REG_READ_ASM (r4, r1, SDRAM_CONFIG_REG) -+ tst r4, #SDRAM_DTYPE_DDR2 -+ beq _extModeODTEnd -+#endif /* DB_FPGA */ -+ -+ /* 9) Write SDRAM Extended mode register This operation should be */ -+ /* done for each memory bank */ -+ /* write 'nop' to SDRAM operation */ -+ mov r4, #0x5 /* 'NOP' command */ -+ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) -+ -+ /* poll SDRAM operation. Make sure its back to normal operation */ -+_sdramOpPoll3: -+ ldr r4, [r1] -+ cmp r4, #0 /* '0' = Normal SDRAM Mode */ -+ bne _sdramOpPoll3 -+ -+ /* Now its safe to write new value to SDRAM Extended Mode register */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG10) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + SDRAM_EXTENDED_MODE_REG) -+ str r4, [r1] -+ -+ /* Go over each of the Banks */ -+ ldr r3, =0 /* r3 = DRAM bank Num */ -+ -+extModeLoop: -+ /* Set the SDRAM Operation Control to each of the DRAM banks */ -+ mov r2, r3 /* Do not swap the bank counter value */ -+ MV_REG_WRITE_ASM (r2, r1, SDRAM_OPERATION_CTRL_REG) -+ -+ /* Make the Dunit write the DRAM its new mode */ -+ mov r4, #0x4 /* Extended Mode Register Set command */ -+ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) -+ -+ /* poll SDRAM operation. Make sure its back to normal operation */ -+_sdramOpPoll4: -+ ldr r4, [r1] -+ cmp r4, #0 /* '0' = Normal SDRAM Mode */ -+ bne _sdramOpPoll4 -+#ifndef DB_FPGA -+ add r3, r3, #1 -+ cmp r3, #4 /* 4 = Number of banks */ -+ bne extModeLoop -+ -+extModeEnd: -+ /* Config DDR2 On Die Termination (ODT) registers */ -+ /* Write SDRAM DDR2 ODT control low register */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG7) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_LOW_REG) -+ str r4, [r1] -+ -+ /* Write SDRAM DDR2 ODT control high register */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG8) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_HIGH_REG) -+ str r4, [r1] -+ -+ /* Write SDRAM DDR2 Dunit ODT control register */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG9) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + DDR2_DUNIT_ODT_CONTROL_REG) -+ str r4, [r1] -+ -+#endif /* DB_FPGA */ -+_extModeODTEnd: -+#ifndef DB_FPGA -+ /* Implement Guideline (GL# MEM-2) P_CAL Automatic Calibration */ -+ /* Does Not Work for Address/Control and Data Pads. */ -+ /* Relevant for: 88F5181-A1/B0 and 88F5281-A0 */ -+ -+ /* Read device ID */ -+ MV_CTRL_MODEL_GET_ASM(r3, r1); -+ /* Read device revision */ -+ MV_CTRL_REV_GET_ASM(r2, r1); -+ -+ /* Continue if OrionN */ -+ ldr r1, =MV_5180_DEV_ID -+ cmp r3, r1 -+ bne 1f -+ b glMem2End -+1: -+ /* Continue if Orion1 and device revision B1 */ -+ ldr r1, =MV_5181_DEV_ID -+ cmp r3, r1 -+ bne 1f -+ -+ cmp r2, #MV_5181_B1_REV -+ bge glMem2End -+ b glMem2Start -+1: -+ -+ /* Orion NAS */ -+ ldr r1, =MV_5182_DEV_ID -+ cmp r3, r1 -+ beq glMem2Start -+ -+ /* Orion NAS */ -+ ldr r1, =MV_5082_DEV_ID -+ cmp r3, r1 -+ beq glMem2Start -+ -+ /* Orion Shark */ -+ ldr r1, =MV_8660_DEV_ID -+ cmp r3, r1 -+ beq glMem2Start -+ -+ b glMem2End -+ -+glMem2Start: -+ -+ /* DDR SDRAM Address/Control Pads Calibration */ -+ MV_REG_READ_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) -+ -+ /* Set Bit [31] to make the register writable */ -+ orr r2, r3, #SDRAM_WR_EN -+ -+ MV_REG_WRITE_ASM (r2, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) -+ -+ bic r3, r3, #SDRAM_WR_EN /* Make register read-only */ -+ bic r3, r3, #SDRAM_TUNE_EN /* Disable auto calibration */ -+ bic r3, r3, #SDRAM_DRVN_MASK /* Clear r1[5:0] */ -+ bic r3, r3, #SDRAM_DRVP_MASK /* Clear r1[11:6] */ -+ -+ /* Get the final N locked value of driving strength [22:17] */ -+ mov r1, r3 -+ mov r1, r1, LSL #9 -+ mov r1, r1, LSR #26 /* r1[5:0] = r3[22:17] */ -+ orr r1, r1, r1, LSL #6 /* r1[11:6] = r1[5:0] */ -+ -+ /* Write to both bits [5:0] and bits [11:6] */ -+ orr r3, r3, r1 -+ -+ MV_REG_WRITE_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) -+ -+ -+ /* DDR SDRAM Data Pads Calibration */ -+ MV_REG_READ_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG) -+ -+ /* Set Bit [31] to make the register writable */ -+ orr r2, r3, #SDRAM_WR_EN -+ -+ MV_REG_WRITE_ASM (r2, r1, SDRAM_DATA_PADS_CAL_REG) -+ -+ bic r3, r3, #SDRAM_WR_EN /* Make register read-only */ -+ bic r3, r3, #SDRAM_TUNE_EN /* Disable auto calibration */ -+ bic r3, r3, #SDRAM_DRVN_MASK /* Clear r1[5:0] */ -+ bic r3, r3, #SDRAM_DRVP_MASK /* Clear r1[11:6] */ -+ -+ /* Get the final N locked value of driving strength [22:17] */ -+ mov r1, r3 -+ mov r1, r1, LSL #9 -+ mov r1, r1, LSR #26 -+ orr r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17] */ -+ -+ /* Write to both bits [5:0] and bits [11:6] */ -+ orr r3, r3, r1 -+ -+ MV_REG_WRITE_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG) -+ -+glMem2End: -+ -+ -+ /* Implement Guideline (GL# MEM-3) Drive Strength Value */ -+ /* Relevant for: 88F5181-A1/B0/B1, 88F5281-A0/B0/C/D, 88F5182, */ -+ /* 88F5082, 88F5181L, 88F6082/L, 88F6183, 88F6183L */ -+ -+ /* Get SDRAM Config value */ -+ MV_REG_READ_ASM (r2, r1, SDRAM_CONFIG_REG) -+ -+ /* Get DIMM type */ -+ tst r2, #SDRAM_DTYPE_DDR2 -+ beq ddr1StrengthVal -+ -+ddr2StrengthVal: -+ ldr r4, =DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV -+ ldr r2, =DDR2_DATA_PAD_STRENGTH_TYPICAL_DV -+ b setDrvStrength -+ddr1StrengthVal: -+ ldr r4, =DDR1_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV -+ ldr r2, =DDR1_DATA_PAD_STRENGTH_TYPICAL_DV -+ -+setDrvStrength: -+ /* DDR SDRAM Address/Control Pads Calibration */ -+ MV_REG_READ_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) -+ -+ orr r3, r3, #SDRAM_WR_EN /* Make register writeable */ -+ -+ MV_REG_WRITE_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) -+ HTOLL(r3,r1) -+ -+ bic r3, r3, #SDRAM_WR_EN /* Make register read-only */ -+ bic r3, r3, #SDRAM_PRE_DRIVER_STRENGTH_MASK -+ orr r3, r4, r3 /* Set default value for DDR */ -+ -+ MV_REG_WRITE_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) -+ -+ -+ /* DDR SDRAM Data Pads Calibration */ -+ MV_REG_READ_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG) -+ -+ orr r3, r3, #SDRAM_WR_EN /* Make register writeable */ -+ -+ MV_REG_WRITE_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG) -+ HTOLL(r3,r1) -+ -+ bic r3, r3, #SDRAM_WR_EN /* Make register read-only */ -+ bic r3, r3, #SDRAM_PRE_DRIVER_STRENGTH_MASK -+ orr r3, r2, r3 /* Set default value for DDR */ -+ -+ MV_REG_WRITE_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG) -+ -+#if !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L) -+ /* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */ -+ /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0/C/D, 88F5182 */ -+ /* 88F5082, 88F5181L, 88F6082/L */ -+ -+ /* Calc the absolute address of the _cpuARMDDRCLK[] in the boot flash */ -+ ldr r7, = _cpuARMDDRCLK -+ ldr r4, =_start -+ sub r7, r7, r4 -+ add r7, r7, #CFG_MONITOR_BASE -+ -+ /* Get the "sample on reset" register for the DDR frequancy */ -+ MV_REG_READ_ASM (r4, r1, MPP_SAMPLE_AT_RESET) -+ ldr r1, =MSAR_ARMDDRCLCK_MASK -+ and r1, r4, r1 -+#if 0 /* YOTAM TO BE FIX */ -+ mov r1, r1, LSR #MSAR_ARMDDRCLCK_OFFS -+#endif -+ -+ /* Read device ID */ -+ MV_CTRL_MODEL_GET_ASM(r3, r2); -+ -+ /* Continue if TC90 */ -+ ldr r2, =MV_1281_DEV_ID -+ cmp r3, r2 -+ beq armClkMsb -+ -+ /* Continue if Orion2 */ -+ ldr r2, =MV_5281_DEV_ID -+ cmp r3, r2 -+#if 0 /* YOTAM TO BE FIX */ -+ bne 1f -+#endif -+ -+armClkMsb: -+#if 0 /* YOTAM TO BE FIX */ -+ tst r4, #MSAR_ARMDDRCLCK_H_MASK -+ beq 1f -+ orr r1, r1, #BIT4 -+1: -+ ldr r4, =MV_CPU_ARM_CLK_ELM_SIZE -+ mul r1, r4, r1 -+ add r7, r7, r1 -+ add r7, r7, #MV_CPU_ARM_CLK_DDR_OFF -+ ldr r1, [r7] -+#endif -+ -+ /* Get SDRAM Config value */ -+ MV_REG_READ_ASM (r2, r4, SDRAM_CONFIG_REG) -+ -+ /* Get DIMM type */ -+ tst r2, #SDRAM_DTYPE_DDR2 -+ beq ddr1FtdllVal -+ -+ddr2FtdllVal: -+ ldr r2, =MV_5281_DEV_ID -+ cmp r3, r2 -+ bne 2f -+ MV_CTRL_REV_GET_ASM(r3, r2) -+ cmp r3, #MV_5281_D0_REV -+ beq orin2_d0_ddr2_ftdll_val -+ cmp r3, #MV_5281_D1_REV -+ beq orin2_d1_ddr2_ftdll_val -+ cmp r3, #MV_5281_D2_REV -+ beq orin2_d1_ddr2_ftdll_val -+ b ddr2_default_val -+ -+/* Set Orion 2 D1 ftdll values for DDR2 */ -+orin2_d1_ddr2_ftdll_val: -+ ldr r4, =FTDLL_DDR2_250MHZ_5281_D1 -+ ldr r7, =_250MHz -+ cmp r1, r7 -+ beq setFtdllReg -+ ldr r4, =FTDLL_DDR2_200MHZ_5281_D1 -+ ldr r7, =_200MHz -+ cmp r1, r7 -+ beq setFtdllReg -+ ldr r4, =FTDLL_DDR2_166MHZ_5281_D0 -+ ldr r7, =_166MHz -+ cmp r1, r7 -+ beq setFtdllReg -+ b ddr2_default_val -+ -+/* Set Orion 2 D0 ftdll values for DDR2 */ -+orin2_d0_ddr2_ftdll_val: -+ ldr r4, =FTDLL_DDR2_250MHZ_5281_D0 -+ ldr r7, =_250MHz -+ cmp r1, r7 -+ beq setFtdllReg -+ ldr r4, =FTDLL_DDR2_200MHZ_5281_D0 -+ ldr r7, =_200MHz -+ cmp r1, r7 -+ beq setFtdllReg -+ ldr r4, =FTDLL_DDR2_166MHZ_5281_D0 -+ ldr r7, =_166MHz -+ cmp r1, r7 -+ beq setFtdllReg -+ b ddr2_default_val -+2: -+ ldr r2, =MV_5182_DEV_ID -+ cmp r3, r2 -+ bne 3f -+ -+/* Set Orion nas ftdll values for DDR2 */ -+orin_nas_ftdll_val: -+ ldr r4, =FTDLL_DDR2_166MHZ_5182 -+ ldr r7, =_166MHz -+ cmp r1, r7 -+ beq setFtdllReg -+ -+/* default values for all other devices */ -+3: -+ddr2_default_val: -+ ldr r4, =FTDLL_DDR2_250MHZ -+ ldr r7, =_250MHz -+ cmp r1, r7 -+ beq setFtdllReg -+ ldr r4, =FTDLL_DDR2_200MHZ -+ ldr r7, =_200MHz -+ cmp r1, r7 -+ beq setFtdllReg -+ ldr r4, =FTDLL_DDR2_166MHZ -+ ldr r7, =_166MHz -+ cmp r1, r7 -+ beq setFtdllReg -+ ldr r4, =FTDLL_DDR2_133MHZ -+ ldr r7, =_133MHz -+ cmp r1, r7 -+ beq setFtdllReg -+ ldr r4, =0 -+ b setFtdllReg -+ -+ddr1FtdllVal: -+ ldr r2, =MV_5281_DEV_ID -+ cmp r3, r2 -+ bne 2f -+ MV_CTRL_REV_GET_ASM(r3, r2) -+ cmp r3, #MV_5281_D0_REV -+ bge orin2_ddr1_ftdll_val -+ b ddr1_default_val -+ -+/* Set Orion 2 D0 and above ftdll values for DDR1 */ -+orin2_ddr1_ftdll_val: -+ ldr r4, =FTDLL_DDR1_200MHZ_5281_D0 -+ ldr r7, =_200MHz -+ cmp r1, r7 -+ beq setFtdllReg -+ ldr r4, =FTDLL_DDR1_166MHZ_5281_D0 -+ ldr r7, =_166MHz -+ cmp r1, r7 -+ beq setFtdllReg -+ b ddr1_default_val -+2: -+ ldr r2, =MV_5181_DEV_ID -+ cmp r3, r2 -+ bne 3f -+ MV_CTRL_REV_GET_ASM(r3, r2) -+ cmp r3, #MV_5181_B1_REV -+ bge orin1_ddr1_ftdll_val -+ b ddr1_default_val -+ -+/* Set Orion 1 ftdll values for DDR1 */ -+orin1_ddr1_ftdll_val: -+ ldr r4, =FTDLL_DDR1_166MHZ_5181_B1 -+ ldr r7, =_166MHz -+ cmp r1, r7 -+ beq setFtdllReg -+3: -+ddr1_default_val: -+ ldr r4, =FTDLL_DDR1_133MHZ -+ ldr r7, =_133MHz -+ cmp r1, r7 -+ beq setFtdllReg -+ -+ ldr r4, =FTDLL_DDR1_166MHZ -+ ldr r7, =_166MHz -+ cmp r1, r7 -+ beq setFtdllReg -+ -+ ldr r4, =FTDLL_DDR1_200MHZ -+ ldr r7, =_200MHz -+ cmp r1, r7 -+ beq setFtdllReg -+ -+ ldr r4, =0 -+ -+setFtdllReg: -+ -+ MV_REG_WRITE_ASM (r4, r1, SDRAM_FTDLL_CONFIG_REG) -+ HTOLL(r4,r1) -+ bic r4, r4, #1 -+ MV_REG_WRITE_ASM (r4, r1, SDRAM_FTDLL_CONFIG_REG) -+ -+#endif /* !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L) */ -+#endif /* DB_FPGA */ -+ -+restoreTmpRegs: -+ /* Restore the registers we used to save the DDR detect values */ -+ -+ ldr r4, =DRAM_BUF_REG0_DV -+ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG0) -+ -+ ldr r4, =DRAM_BUF_REG1_DV -+ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG1) -+ -+ ldr r4, =DRAM_BUF_REG2_DV -+ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG2) -+ -+ ldr r4, =DRAM_BUF_REG3_DV -+ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG3) -+ -+ ldr r4, =DRAM_BUF_REG4_DV -+ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG4) -+ -+ ldr r4, =DRAM_BUF_REG5_DV -+ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG5) -+ -+ ldr r4, =DRAM_BUF_REG6_DV -+ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG6) -+ -+ ldr r4, =DRAM_BUF_REG7_DV -+ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG7) -+ -+ ldr r4, =DRAM_BUF_REG8_DV -+ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG8) -+ -+ ldr r4, =DRAM_BUF_REG9_DV -+ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG9) -+ -+ ldr r4, =DRAM_BUF_REG10_DV -+ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG10) -+ -+ -+ /* Restore registers */ -+ /* Save register on stack */ -+ cmp sp, #0 -+ beq no_stack_l -+load_from_stack: -+ ldmia sp!, {r1, r2, r3, r4, r7, r11} -+no_stack_l: -+ -+ mov pc, lr -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,192 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvDramIfConfigh -+#define __INCmvDramIfConfigh -+ -+/* includes */ -+ -+/* defines */ -+ -+/* registers defaults values */ -+ -+#define SDRAM_CONFIG_DV \ -+ (SDRAM_PERR_WRITE | \ -+ SDRAM_SRMODE | \ -+ SDRAM_SRCLK_GATED) -+ -+#define SDRAM_DUNIT_CTRL_LOW_DV \ -+ (SDRAM_CTRL_POS_RISE | \ -+ SDRAM_CLK1DRV_NORMAL | \ -+ SDRAM_LOCKEN_ENABLE) -+ -+#define SDRAM_ADDR_CTRL_DV 0 -+ -+#define SDRAM_TIMING_CTRL_LOW_REG_DV \ -+ ((0x2 << SDRAM_TRCD_OFFS) | \ -+ (0x2 << SDRAM_TRP_OFFS) | \ -+ (0x1 << SDRAM_TWR_OFFS) | \ -+ (0x0 << SDRAM_TWTR_OFFS) | \ -+ (0x5 << SDRAM_TRAS_OFFS) | \ -+ (0x1 << SDRAM_TRRD_OFFS)) -+/* TRFC 0x27, TW2W 0x1 */ -+#define SDRAM_TIMING_CTRL_HIGH_REG_DV (( 0x7 << SDRAM_TRFC_OFFS ) |\ -+ ( 0x2 << SDRAM_TRFC_EXT_OFFS) |\ -+ ( 0x1 << SDRAM_TW2W_OFFS)) -+ -+#define SDRAM_OPEN_PAGES_CTRL_REG_DV SDRAM_OPEN_PAGE_EN -+ -+/* DDR2 ODT default register values */ -+ -+/* Presence Ctrl Low Ctrl High Dunit Ctrl Ext Mode */ -+/* CS0 0x84210000 0x00000000 0x0000780F 0x00000440 */ -+/* CS0+CS1 0x84210000 0x00000000 0x0000780F 0x00000440 */ -+/* CS0+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -+/* CS0+CS1+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -+/* CS0+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -+/* CS0+CS1+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -+ -+#define DDR2_ODT_CTRL_LOW_CS0_DV 0x84210000 -+#define DDR2_ODT_CTRL_HIGH_CS0_DV 0x00000000 -+#define DDR2_DUNIT_ODT_CTRL_CS0_DV 0x0000780F -+#define DDR_SDRAM_EXT_MODE_CS0_DV 0x00000440 -+ -+#define DDR2_ODT_CTRL_LOW_CS0_CS2_DV 0x030C030C -+#define DDR2_ODT_CTRL_HIGH_CS0_CS2_DV 0x00000000 -+#define DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV 0x0000740F -+#define DDR_SDRAM_EXT_MODE_CS0_CS2_DV 0x00000404 -+ -+ -+/* DDR SDRAM Adderss/Control and Data Pads Calibration default values */ -+#define DDR1_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \ -+ (1 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) -+#define DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \ -+ (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) -+ -+ -+#define DDR1_DATA_PAD_STRENGTH_TYPICAL_DV \ -+ (1 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) -+#define DDR2_DATA_PAD_STRENGTH_TYPICAL_DV \ -+ (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) -+ -+/* DDR SDRAM Mode Register default value */ -+#define DDR1_MODE_REG_DV 0x00000000 -+#define DDR2_MODE_REG_DV 0x00000400 -+ -+/* DDR SDRAM Timing parameter default values */ -+#define DDR1_TIMING_LOW_DV 0x11602220 -+#define DDR1_TIMING_HIGH_DV 0x0000000d -+ -+#define DDR2_TIMING_LOW_DV 0x11812220 -+#define DDR2_TIMING_HIGH_DV 0x0000030f -+ -+/* For Guideline (GL# MEM-4) DQS Reference Delay Tuning */ -+#define FTDLL_DDR1_166MHZ ((0x1 << 0) | \ -+ (0x7F<< 12) | \ -+ (0x1 << 22)) -+ -+#define FTDLL_DDR1_133MHZ FTDLL_DDR1_166MHZ -+ -+#define FTDLL_DDR1_200MHZ ((0x1 << 0) | \ -+ (0x1 << 12) | \ -+ (0x3 << 14) | \ -+ (0x1 << 18) | \ -+ (0x1 << 22)) -+ -+ -+#define FTDLL_DDR2_166MHZ ((0x1 << 0) | \ -+ (0x1 << 12) | \ -+ (0x1 << 14) | \ -+ (0x1 << 16) | \ -+ (0x1 << 19) | \ -+ (0xF << 20)) -+ -+#define FTDLL_DDR2_133MHZ FTDLL_DDR2_166MHZ -+ -+#define FTDLL_DDR2_200MHZ ((0x1 << 0) | \ -+ (0x1 << 12) | \ -+ (0x1 << 14) | \ -+ (0x1 << 16) | \ -+ (0x1 << 19) | \ -+ (0xF << 20)) -+ -+#define FTDLL_DDR2_250MHZ 0x445001 -+ -+/* Orion 1 B1 and above */ -+#define FTDLL_DDR1_166MHZ_5181_B1 0x45D001 -+ -+/* Orion nas */ -+#define FTDLL_DDR2_166MHZ_5182 0x597001 -+ -+/* Orion 2 D0 and above */ -+#define FTDLL_DDR1_166MHZ_5281_D0 0x8D0001 -+#define FTDLL_DDR1_200MHZ_5281_D0 0x8D0001 -+#define FTDLL_DDR2_166MHZ_5281_D0 0x485001 -+#define FTDLL_DDR2_200MHZ_5281_D0 0x485001 -+#define FTDLL_DDR2_250MHZ_5281_D0 0x445001 -+#define FTDLL_DDR2_200MHZ_5281_D1 0x995001 -+#define FTDLL_DDR2_250MHZ_5281_D1 0x984801 -+ -+#endif /* __INCmvDramIfh */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,306 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvDramIfRegsh -+#define __INCmvDramIfRegsh -+ -+ -+/* DDR SDRAM Controller Address Decode Registers */ -+/* SDRAM CSn Base Address Register (SCBAR) */ -+#define SDRAM_BASE_ADDR_REG(csNum) (0x1500 + (csNum * 8)) -+#define SCBAR_BASE_OFFS 16 -+#define SCBAR_BASE_MASK (0xffff << SCBAR_BASE_OFFS) -+#define SCBAR_BASE_ALIGNMENT 0x10000 -+ -+/* SDRAM CSn Size Register (SCSR) */ -+#define SDRAM_SIZE_REG(csNum) (0x1504 + (csNum * 8)) -+#define SCSR_WIN_EN BIT0 -+#define SCSR_SIZE_OFFS 16 -+#define SCSR_SIZE_MASK (0xffff << SCSR_SIZE_OFFS) -+#define SCSR_SIZE_ALIGNMENT 0x10000 -+ -+/* configuration register */ -+#define SDRAM_CONFIG_REG 0x1400 -+#define SDRAM_REFRESH_OFFS 0 -+#define SDRAM_REFRESH_MAX 0x3000 -+#define SDRAM_REFRESH_MASK (SDRAM_REFRESH_MAX << SDRAM_REFRESH_OFFS) -+#define SDRAM_DWIDTH_OFFS 14 -+#define SDRAM_DWIDTH_MASK (3 << SDRAM_DWIDTH_OFFS) -+#define SDRAM_DWIDTH_16BIT (1 << SDRAM_DWIDTH_OFFS) -+#define SDRAM_DWIDTH_32BIT (2 << SDRAM_DWIDTH_OFFS) -+#define SDRAM_DTYPE_OFFS 16 -+#define SDRAM_DTYPE_MASK (1 << SDRAM_DTYPE_OFFS) -+#define SDRAM_DTYPE_DDR1 (0 << SDRAM_DTYPE_OFFS) -+#define SDRAM_DTYPE_DDR2 (1 << SDRAM_DTYPE_OFFS) -+#define SDRAM_REGISTERED (1 << 17) -+#define SDRAM_PERR_OFFS 18 -+#define SDRAM_PERR_MASK (1 << SDRAM_PERR_OFFS) -+#define SDRAM_PERR_NO_WRITE (0 << SDRAM_PERR_OFFS) -+#define SDRAM_PERR_WRITE (1 << SDRAM_PERR_OFFS) -+#define SDRAM_DCFG_OFFS 20 -+#define SDRAM_DCFG_MASK (0x3 << SDRAM_DCFG_OFFS) -+#define SDRAM_DCFG_X16_DEV (1 << SDRAM_DCFG_OFFS) -+#define SDRAM_DCFG_X8_DEV (2 << SDRAM_DCFG_OFFS) -+#define SDRAM_SRMODE (1 << 24) -+#define SDRAM_SRCLK_OFFS 25 -+#define SDRAM_SRCLK_MASK (1 << SDRAM_SRCLK_OFFS) -+#define SDRAM_SRCLK_KEPT (0 << SDRAM_SRCLK_OFFS) -+#define SDRAM_SRCLK_GATED (1 << SDRAM_SRCLK_OFFS) -+#define SDRAM_CATTH_OFFS 26 -+#define SDRAM_CATTHR_EN (1 << SDRAM_CATTH_OFFS) -+ -+ -+/* dunit control register */ -+#define SDRAM_DUNIT_CTRL_REG 0x1404 -+#define SDRAM_CTRL_POS_OFFS 6 -+#define SDRAM_CTRL_POS_FALL (0 << SDRAM_CTRL_POS_OFFS) -+#define SDRAM_CTRL_POS_RISE (1 << SDRAM_CTRL_POS_OFFS) -+#define SDRAM_CLK1DRV_OFFS 12 -+#define SDRAM_CLK1DRV_MASK (1 << SDRAM_CLK1DRV_OFFS) -+#define SDRAM_CLK1DRV_HIGH_Z (0 << SDRAM_CLK1DRV_OFFS) -+#define SDRAM_CLK1DRV_NORMAL (1 << SDRAM_CLK1DRV_OFFS) -+#define SDRAM_LOCKEN_OFFS 18 -+#define SDRAM_LOCKEN_MASK (1 << SDRAM_LOCKEN_OFFS) -+#define SDRAM_LOCKEN_DISABLE (0 << SDRAM_LOCKEN_OFFS) -+#define SDRAM_LOCKEN_ENABLE (1 << SDRAM_LOCKEN_OFFS) -+#define SDRAM_ST_BURST_DEL_OFFS 24 -+#define SDRAM_ST_BURST_DEL_MAX 0xf -+#define SDRAM_ST_BURST_DEL_MASK (SDRAM_ST_BURST_DEL_MAX< busClkPs) -+ { -+ mvOsOutput("Dram: ERR. Bank %d doesn't support memory clock!!!\n", i); -+ return MV_ERROR; -+ } -+ -+ /* All banks must support registry in order to activate it */ -+ if(bankInfo[i].registeredAddrAndControlInputs != -+ bankInfo[0].registeredAddrAndControlInputs) -+ { -+ mvOsOutput("Dram: ERR. different Registered settings !!!\n"); -+ return MV_ERROR; -+ } -+ -+ /* All banks must support same ECC mode */ -+ if(bankInfo[i].errorCheckType != -+ bankInfo[0].errorCheckType) -+ { -+ mvOsOutput("Dram: ERR. different ECC settings !!!\n"); -+ return MV_ERROR; -+ } -+ -+ } -+ else -+ { -+ if( i == 0 ) /* bank 0 doesn't exist */ -+ { -+ mvOsOutput("Dram: ERR. Fail to detect bank 0 !!!\n"); -+ return MV_ERROR; -+ } -+ else -+ { -+ DB(mvOsPrintf("Dram: Could not find bank %d\n", i)); -+ bankInfo[i].size = 0; /* Mark this bank as non exist */ -+ } -+ } -+ } -+ -+#ifdef MV_INCLUDE_SDRAM_CS2 -+ if (bankInfo[SDRAM_CS0].size < bankInfo[SDRAM_CS2].size) -+ { -+ MV_DRAM_CS_order[0] = SDRAM_CS2; -+ MV_DRAM_CS_order[1] = SDRAM_CS3; -+ MV_DRAM_CS_order[2] = SDRAM_CS0; -+ MV_DRAM_CS_order[3] = SDRAM_CS1; -+ DRAM_CS_Order[0] = SDRAM_CS2; -+ DRAM_CS_Order[1] = SDRAM_CS3; -+ DRAM_CS_Order[2] = SDRAM_CS0; -+ DRAM_CS_Order[3] = SDRAM_CS1; -+ -+ } -+ else -+#endif -+ { -+ MV_DRAM_CS_order[0] = SDRAM_CS0; -+ MV_DRAM_CS_order[1] = SDRAM_CS1; -+ DRAM_CS_Order[0] = SDRAM_CS0; -+ DRAM_CS_Order[1] = SDRAM_CS1; -+#ifdef MV_INCLUDE_SDRAM_CS2 -+ MV_DRAM_CS_order[2] = SDRAM_CS2; -+ MV_DRAM_CS_order[3] = SDRAM_CS3; -+ DRAM_CS_Order[2] = SDRAM_CS2; -+ DRAM_CS_Order[3] = SDRAM_CS3; -+#endif -+ } -+ -+ for(j = 0; j < MV_DRAM_MAX_CS; j++) -+ { -+ i = MV_DRAM_CS_order[j]; -+ -+ if (0 == bankInfo[i].size) -+ continue; -+ -+ /* Init the CPU window decode */ -+ /* Note that the Dimm width might be different then the device DRAM width */ -+#ifdef MV78XX0 -+ temp = MV_REG_READ(SDRAM_CONFIG_REG); -+ deviceW = ((temp & SDRAM_DWIDTH_MASK) == SDRAM_DWIDTH_32BIT )? 32 : 64; -+#else -+ deviceW = 16 /* KW family */; -+#endif -+ dimmW = bankInfo[0].dataWidth - (bankInfo[0].dataWidth % 16); -+ size = ((bankInfo[i].size << 20) / (dimmW/deviceW)); -+ -+ /* We can not change DRAM window settings while excecuting */ -+ /* code from it. That is why we skip the DRAM CS[0], saving */ -+ /* it to the ROM configuration routine */ -+ -+ numOfAllDevices += bankInfo[i].numberOfDevices; -+ if (i == MV_DRAM_CS_order[0]) -+ { -+ MV_U32 sizeToReg; -+ /* Translate the given window size to register format */ -+ sizeToReg = ctrlSizeToReg(size, SCSR_SIZE_ALIGNMENT); -+ /* Size parameter validity check. */ -+ if (-1 == sizeToReg) -+ { -+ mvOsOutput("DRAM: mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n" -+ ,i); -+ return MV_BAD_PARAM; -+ } -+ -+ DB(mvOsPrintf("Dram: Bank 0 Size - %x\n",sizeToReg);) -+ sizeToReg = (sizeToReg << SCSR_SIZE_OFFS); -+ sizeToReg |= SCSR_WIN_EN; -+ MV_REG_WRITE(DRAM_BUF_REG0, sizeToReg); -+ } -+ else -+ { -+ dramDecWin.addrWin.baseLow = base; -+ dramDecWin.addrWin.size = size; -+ dramDecWin.enable = MV_TRUE; -+ DB(mvOsPrintf("Dram: Enable window %d base 0x%x, size=0x%x\n",i, base, size)); -+ -+ /* Check if the DRAM size is more then 3GByte */ -+ if (base < 0xC0000000) -+ { -+ DB(mvOsPrintf("Dram: Enable window %d base 0x%x, size=0x%x\n",i, base, size)); -+ if (MV_OK != mvCpuIfTargetWinSet(i, &dramDecWin)) -+ { -+ mvOsPrintf("Dram: ERR. Fail to set bank %d!!!\n", SDRAM_CS0 + i); -+ return MV_ERROR; -+ } -+ } -+ } -+ -+ base += size; -+ -+ /* update the suportedCasLatencies mask */ -+ bankInfo[0].suportedCasLatencies &= bankInfo[i].suportedCasLatencies; -+ } -+ -+ /* calculate minimum CAS */ -+ minCas = minCasCalc(&bankInfo[0], &bankInfo[2], busClk, forcedCl); -+ if (0 == minCas) -+ { -+ mvOsOutput("Dram: Warn: Could not find CAS compatible to SysClk %dMhz\n", -+ (busClk / 1000000)); -+ -+ minCas = DDR2_CL_4; /* Continue with this CAS */ -+ mvOsOutput("Set default CAS latency 4\n"); -+ } -+ -+ /* calc SDRAM_CONFIG_REG and save it to temp register */ -+ temp = sdramConfigRegCalc(&bankInfo[0],&bankInfo[2], busClk); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. sdramConfigRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ -+ /* check if ECC is enabled by the user */ -+ if(eccDisable) -+ { -+ /* turn off ECC*/ -+ temp &= ~BIT18; -+ } -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG1, temp); -+ -+ /* calc SDRAM_MODE_REG and save it to temp register */ -+ temp = sdramModeRegCalc(minCas); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. sdramModeRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: sdramModeRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG2, temp); -+ -+ /* calc SDRAM_EXTENDED_MODE_REG and save it to temp register */ -+ temp = sdramExtModeRegCalc(&bankInfo[0], busClk); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. sdramExtModeRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: sdramExtModeRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG10, temp); -+ -+ /* calc D_UNIT_CONTROL_LOW and save it to temp register */ -+ TTMode = MV_FALSE; -+ DB(mvOsPrintf("Dram: numOfAllDevices = %x\n",numOfAllDevices);) -+ if( (numOfAllDevices > 9) && (bankInfo[0].registeredAddrAndControlInputs == MV_FALSE) ) -+ { -+ if ( ( (numOfAllDevices > 9) && (busClk > MV_BOARD_SYSCLK_200MHZ) ) || -+ (numOfAllDevices > 18) ) -+ { -+ mvOsOutput("Enable 2T "); -+ TTMode = MV_TRUE; -+ } -+ } -+ -+ temp = dunitCtrlLowRegCalc(&bankInfo[0], minCas, busClk, TTMode ); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. dunitCtrlLowRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: dunitCtrlLowRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG3, temp); -+ -+ /* calc D_UNIT_CONTROL_HIGH and save it to temp register */ -+ temp = dunitCtrlHighRegCalc(&bankInfo[0], busClk); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. dunitCtrlHighRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: dunitCtrlHighRegCalc - %x\n",temp);) -+ /* check if ECC is enabled by the user */ -+ if(eccDisable) -+ { -+ /* turn off sample stage if no ecc */ -+ temp &= ~SDRAM__D2P_EN;; -+ } -+ MV_REG_WRITE(DRAM_BUF_REG13, temp); -+ -+ /* calc SDRAM_ADDR_CTRL_REG and save it to temp register */ -+ temp = sdramAddrCtrlRegCalc(&bankInfo[0],&bankInfo[2]); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. sdramAddrCtrlRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: sdramAddrCtrlRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG4, temp); -+ -+ /* calc SDRAM_TIMING_CTRL_LOW_REG and save it to temp register */ -+ temp = sdramTimeCtrlLowRegCalc(&bankInfo[0], minCas, busClk); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. sdramTimeCtrlLowRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: sdramTimeCtrlLowRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG5, temp); -+ -+ /* calc SDRAM_TIMING_CTRL_HIGH_REG and save it to temp register */ -+ temp = sdramTimeCtrlHighRegCalc(&bankInfo[0], busClk); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. sdramTimeCtrlHighRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: sdramTimeCtrlHighRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG6, temp); -+ -+ sdramDDr2OdtConfig(bankInfo); -+ -+ /* calc DDR2_SDRAM_TIMING_LOW_REG and save it to temp register */ -+ temp = sdramDdr2TimeLoRegCalc(minCas); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. sdramDdr2TimeLoRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: sdramDdr2TimeLoRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG11, temp); -+ -+ /* calc DDR2_SDRAM_TIMING_HIGH_REG and save it to temp register */ -+ temp = sdramDdr2TimeHiRegCalc(minCas); -+ if(-1 == temp) -+ { -+ mvOsOutput("Dram: ERR. sdramDdr2TimeHiRegCalc failed !!!\n"); -+ return MV_ERROR; -+ } -+ DB(mvOsPrintf("Dram: sdramDdr2TimeHiRegCalc - %x\n",temp);) -+ MV_REG_WRITE(DRAM_BUF_REG12, temp); -+#endif -+ -+ /* Note that DDR SDRAM Address/Control and Data pad calibration */ -+ /* settings is done in mvSdramIfConfig.s */ -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvDramIfBankBaseGet - Get DRAM interface bank base. -+* -+* DESCRIPTION: -+* This function returns the 32 bit base address of a given DRAM bank. -+* -+* INPUT: -+* bankNum - Bank number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* DRAM bank size. If bank is disabled or paramter is invalid, the -+* function returns -1. -+* -+*******************************************************************************/ -+MV_U32 mvDramIfBankBaseGet(MV_U32 bankNum) -+{ -+ DB(mvOsPrintf("Dram: mvDramIfBankBaseGet Bank %d base addr is %x \n", -+ bankNum, mvCpuIfTargetWinBaseLowGet(SDRAM_CS0 + bankNum))); -+ return mvCpuIfTargetWinBaseLowGet(SDRAM_CS0 + bankNum); -+} -+ -+/******************************************************************************* -+* mvDramIfBankSizeGet - Get DRAM interface bank size. -+* -+* DESCRIPTION: -+* This function returns the size of a given DRAM bank. -+* -+* INPUT: -+* bankNum - Bank number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* DRAM bank size. If bank is disabled the function return '0'. In case -+* or paramter is invalid, the function returns -1. -+* -+*******************************************************************************/ -+MV_U32 mvDramIfBankSizeGet(MV_U32 bankNum) -+{ -+ DB(mvOsPrintf("Dram: mvDramIfBankSizeGet Bank %d size is %x \n", -+ bankNum, mvCpuIfTargetWinSizeGet(SDRAM_CS0 + bankNum))); -+ return mvCpuIfTargetWinSizeGet(SDRAM_CS0 + bankNum); -+} -+ -+ -+/******************************************************************************* -+* mvDramIfSizeGet - Get DRAM interface total size. -+* -+* DESCRIPTION: -+* This function get the DRAM total size. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* DRAM total size. In case or paramter is invalid, the function -+* returns -1. -+* -+*******************************************************************************/ -+MV_U32 mvDramIfSizeGet(MV_VOID) -+{ -+ MV_U32 size = 0, i; -+ -+ for(i = 0; i < MV_DRAM_MAX_CS; i++) -+ size += mvDramIfBankSizeGet(i); -+ -+ DB(mvOsPrintf("Dram: mvDramIfSizeGet size is %x \n",size)); -+ return size; -+} -+ -+/******************************************************************************* -+* mvDramIfSingleBitErrThresholdSet - Set single bit ECC threshold. -+* -+* DESCRIPTION: -+* The ECC single bit error threshold is the number of single bit -+* errors to happen before the Dunit generates an interrupt. -+* This function set single bit ECC threshold. -+* -+* INPUT: -+* threshold - threshold. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM if threshold is to big, MV_OK otherwise. -+* -+*******************************************************************************/ -+MV_STATUS mvDramIfSingleBitErrThresholdSet(MV_U32 threshold) -+{ -+ MV_U32 regVal; -+ -+ if (threshold > SECR_THRECC_MAX) -+ { -+ return MV_BAD_PARAM; -+ } -+ -+ regVal = MV_REG_READ(SDRAM_ECC_CONTROL_REG); -+ regVal &= ~SECR_THRECC_MASK; -+ regVal |= ((SECR_THRECC(threshold) & SECR_THRECC_MASK)); -+ MV_REG_WRITE(SDRAM_ECC_CONTROL_REG, regVal); -+ -+ return MV_OK; -+} -+ -+#ifndef MV_STATIC_DRAM_ON_BOARD -+/******************************************************************************* -+* minCasCalc - Calculate the Minimum CAS latency which can be used. -+* -+* DESCRIPTION: -+* Calculate the minimum CAS latency that can be used, base on the DRAM -+* parameters and the SDRAM bus Clock freq. -+* -+* INPUT: -+* busClk - the DRAM bus Clock. -+* pBankInfo - bank info parameters. -+* forcedCl - Forced CAS Latency multiplied by 10. If equal to zero, do not force. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* The minimum CAS Latency. The function returns 0 if max CAS latency -+* supported by banks is incompatible with system bus clock frequancy. -+* -+*******************************************************************************/ -+ -+static MV_U32 minCasCalc(MV_DRAM_BANK_INFO *pBankInfo,MV_DRAM_BANK_INFO *pBankInfo2, MV_U32 busClk, MV_U32 forcedCl) -+{ -+ MV_U32 count = 1, j; -+ MV_U32 busClkPs = 1000000000 / (busClk / 1000); /* in ps units */ -+ MV_U32 startBit, stopBit; -+ MV_U32 minCas0 = 0, minCas2 = 0; -+ -+ -+ /* DDR 2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * -+ Disco VI= * TBD | TBD | 5 | 4 | 3 | TBD | TBD | TBD * -+ Disco Duo= * TBD | 6 | 5 | 4 | 3 | TBD | TBD | TBD * -+ *********************************************************/ -+ -+ -+ /* If we are asked to use the forced CAL we change the suported CAL to be forcedCl only */ -+ if (forcedCl) -+ { -+ mvOsOutput("DRAM: Using forced CL %d.%d\n", (forcedCl / 10), (forcedCl % 10)); -+ -+ if (forcedCl == 30) -+ pBankInfo->suportedCasLatencies = 0x08; -+ else if (forcedCl == 40) -+ pBankInfo->suportedCasLatencies = 0x10; -+ else if (forcedCl == 50) -+ pBankInfo->suportedCasLatencies = 0x20; -+ else if (forcedCl == 60) -+ pBankInfo->suportedCasLatencies = 0x40; -+ else -+ { -+ mvOsPrintf("Forced CL %d.%d not supported. Set default CL 4\n", -+ (forcedCl / 10), (forcedCl % 10)); -+ pBankInfo->suportedCasLatencies = 0x10; -+ } -+ -+ return pBankInfo->suportedCasLatencies; -+ } -+ -+ /* go over the supported cas mask from Max Cas down and check if the */ -+ /* SysClk stands in its time requirments. */ -+ -+ DB(mvOsPrintf("Dram: minCasCalc supported mask = %x busClkPs = %x \n", -+ pBankInfo->suportedCasLatencies,busClkPs )); -+ count = 1; -+ for(j = 7; j > 0; j--) -+ { -+ if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) -+ { -+ /* Reset the bits for CL incompatible for the sysClk */ -+ switch (count) -+ { -+ case 1: -+ if (pBankInfo->minCycleTimeAtMaxCasLatPs > busClkPs) -+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ case 2: -+ if (pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps > busClkPs) -+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ case 3: -+ if (pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps > busClkPs) -+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ default: -+ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); -+ break; -+ } -+ } -+ } -+ -+ DB(mvOsPrintf("Dram: minCasCalc support = %x (after SysCC calc)\n", -+ pBankInfo->suportedCasLatencies )); -+ -+ count = 1; -+ DB(mvOsPrintf("Dram2: minCasCalc supported mask = %x busClkPs = %x \n", -+ pBankInfo2->suportedCasLatencies,busClkPs )); -+ for(j = 7; j > 0; j--) -+ { -+ if((pBankInfo2->suportedCasLatencies >> j) & BIT0 ) -+ { -+ /* Reset the bits for CL incompatible for the sysClk */ -+ switch (count) -+ { -+ case 1: -+ if (pBankInfo2->minCycleTimeAtMaxCasLatPs > busClkPs) -+ pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ case 2: -+ if (pBankInfo2->minCycleTimeAtMaxCasLatMinus1Ps > busClkPs) -+ pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ case 3: -+ if (pBankInfo2->minCycleTimeAtMaxCasLatMinus2Ps > busClkPs) -+ pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); -+ count++; -+ break; -+ default: -+ pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); -+ break; -+ } -+ } -+ } -+ -+ DB(mvOsPrintf("Dram2: minCasCalc support = %x (after SysCC calc)\n", -+ pBankInfo2->suportedCasLatencies )); -+ -+ startBit = 3; /* DDR2 support CL start with CL3 (bit 3) */ -+ stopBit = 6; /* DDR2 support CL stops with CL6 (bit 6) */ -+ -+ for(j = startBit; j <= stopBit ; j++) -+ { -+ if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) -+ { -+ DB(mvOsPrintf("Dram: minCasCalc choose CAS %x \n",(BIT0 << j))); -+ minCas0 = (BIT0 << j); -+ break; -+ } -+ } -+ -+ for(j = startBit; j <= stopBit ; j++) -+ { -+ if((pBankInfo2->suportedCasLatencies >> j) & BIT0 ) -+ { -+ DB(mvOsPrintf("Dram: minCasCalc choose CAS %x \n",(BIT0 << j))); -+ minCas2 = (BIT0 << j); -+ break; -+ } -+ } -+ -+ if (minCas2 > minCas0) -+ return minCas2; -+ else -+ return minCas0; -+ -+ return 0; -+} -+ -+/******************************************************************************* -+* sdramConfigRegCalc - Calculate sdram config register -+* -+* DESCRIPTION: Calculate sdram config register optimized value based -+* on the bank info parameters. -+* -+* INPUT: -+* busClk - the DRAM bus Clock. -+* pBankInfo - sdram bank parameters -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram config reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramConfigRegCalc(MV_DRAM_BANK_INFO *pBankInfo,MV_DRAM_BANK_INFO *pBankInfo2, MV_U32 busClk) -+{ -+ MV_U32 sdramConfig = 0; -+ MV_U32 refreshPeriod; -+ -+ busClk /= 1000000; /* we work with busClk in MHz */ -+ -+ sdramConfig = MV_REG_READ(SDRAM_CONFIG_REG); -+ -+ /* figure out the memory refresh internal */ -+ switch (pBankInfo->refreshInterval & 0xf) -+ { -+ case 0x0: /* refresh period is 15.625 usec */ -+ refreshPeriod = 15625; -+ break; -+ case 0x1: /* refresh period is 3.9 usec */ -+ refreshPeriod = 3900; -+ break; -+ case 0x2: /* refresh period is 7.8 usec */ -+ refreshPeriod = 7800; -+ break; -+ case 0x3: /* refresh period is 31.3 usec */ -+ refreshPeriod = 31300; -+ break; -+ case 0x4: /* refresh period is 62.5 usec */ -+ refreshPeriod = 62500; -+ break; -+ case 0x5: /* refresh period is 125 usec */ -+ refreshPeriod = 125000; -+ break; -+ default: /* refresh period undefined */ -+ mvOsPrintf("Dram: ERR. DRAM refresh period is unknown!\n"); -+ return -1; -+ } -+ -+ /* Now the refreshPeriod is in register format value */ -+ refreshPeriod = (busClk * refreshPeriod) / 1000; -+ -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc calculated refresh interval %0x\n", -+ refreshPeriod)); -+ -+ /* make sure the refresh value is only 14 bits */ -+ if(refreshPeriod > SDRAM_REFRESH_MAX) -+ { -+ refreshPeriod = SDRAM_REFRESH_MAX; -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc adjusted refresh interval %0x\n", -+ refreshPeriod)); -+ } -+ -+ /* Clear the refresh field */ -+ sdramConfig &= ~SDRAM_REFRESH_MASK; -+ -+ /* Set new value to refresh field */ -+ sdramConfig |= (refreshPeriod & SDRAM_REFRESH_MASK); -+ -+ /* registered DRAM ? */ -+ if ( pBankInfo->registeredAddrAndControlInputs ) -+ { -+ /* it's registered DRAM, so set the reg. DRAM bit */ -+ sdramConfig |= SDRAM_REGISTERED; -+ DB(mvOsPrintf("DRAM Attribute: Registered address and control inputs.\n");) -+ } -+ -+ /* ECC and IERR support */ -+ sdramConfig &= ~SDRAM_ECC_MASK; /* Clear ECC field */ -+ sdramConfig &= ~SDRAM_IERR_MASK; /* Clear IErr field */ -+ -+ if ( pBankInfo->errorCheckType ) -+ { -+ sdramConfig |= SDRAM_ECC_EN; -+ sdramConfig |= SDRAM_IERR_REPORTE; -+ DB(mvOsPrintf("Dram: mvDramIfDetect Enabling ECC\n")); -+ } -+ else -+ { -+ sdramConfig |= SDRAM_ECC_DIS; -+ sdramConfig |= SDRAM_IERR_IGNORE; -+ DB(mvOsPrintf("Dram: mvDramIfDetect Disabling ECC!\n")); -+ } -+ /* Set static default settings */ -+ sdramConfig |= SDRAM_CONFIG_DV; -+ -+ DB(mvOsPrintf("Dram: sdramConfigRegCalc set sdramConfig to 0x%x\n", -+ sdramConfig)); -+ -+ return sdramConfig; -+} -+ -+/******************************************************************************* -+* sdramModeRegCalc - Calculate sdram mode register -+* -+* DESCRIPTION: Calculate sdram mode register optimized value based -+* on the bank info parameters and the minCas. -+* -+* INPUT: -+* minCas - minimum CAS supported. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram mode reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramModeRegCalc(MV_U32 minCas) -+{ -+ MV_U32 sdramMode; -+ -+ sdramMode = MV_REG_READ(SDRAM_MODE_REG); -+ -+ /* Clear CAS Latency field */ -+ sdramMode &= ~SDRAM_CL_MASK; -+ -+ DB(mvOsPrintf("DRAM CAS Latency ");) -+ -+ switch (minCas) -+ { -+ case DDR2_CL_3: -+ sdramMode |= SDRAM_DDR2_CL_3; -+ DB(mvOsPrintf("3.\n");) -+ break; -+ case DDR2_CL_4: -+ sdramMode |= SDRAM_DDR2_CL_4; -+ DB(mvOsPrintf("4.\n");) -+ break; -+ case DDR2_CL_5: -+ sdramMode |= SDRAM_DDR2_CL_5; -+ DB(mvOsPrintf("5.\n");) -+ break; -+ case DDR2_CL_6: -+ sdramMode |= SDRAM_DDR2_CL_6; -+ DB(mvOsPrintf("6.\n");) -+ break; -+ default: -+ mvOsOutput("\nsdramModeRegCalc ERROR: Max. CL out of range\n"); -+ return -1; -+ } -+ -+ DB(mvOsPrintf("\nsdramModeRegCalc register 0x%x\n", sdramMode )); -+ -+ return sdramMode; -+} -+/******************************************************************************* -+* sdramExtModeRegCalc - Calculate sdram Extended mode register -+* -+* DESCRIPTION: -+* Return sdram Extended mode register value based -+* on the bank info parameters and bank presence. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* busClk - DRAM frequency -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram Extended mode reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramExtModeRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) -+{ -+ MV_U32 populateBanks = 0; -+ int bankNum; -+ -+ /* Represent the populate banks in binary form */ -+ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ if (0 != pBankInfo[bankNum].size) -+ { -+ populateBanks |= (1 << bankNum); -+ } -+ } -+ -+ switch(populateBanks) -+ { -+ case(BANK_PRESENT_CS0): -+ case(BANK_PRESENT_CS0_CS1): -+ return DDR_SDRAM_EXT_MODE_CS0_CS1_DV; -+ -+ case(BANK_PRESENT_CS0_CS2): -+ case(BANK_PRESENT_CS0_CS1_CS2): -+ case(BANK_PRESENT_CS0_CS2_CS3): -+ case(BANK_PRESENT_CS0_CS2_CS3_CS4): -+ if (busClk >= MV_BOARD_SYSCLK_267MHZ) -+ return DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV; -+ else -+ return DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV; -+ -+ default: -+ mvOsOutput("sdramExtModeRegCalc: Invalid DRAM bank presence\n"); -+ return -1; -+ } -+ return 0; -+} -+ -+/******************************************************************************* -+* dunitCtrlLowRegCalc - Calculate sdram dunit control low register -+* -+* DESCRIPTION: Calculate sdram dunit control low register optimized value based -+* on the bank info parameters and the minCas. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* minCas - minimum CAS supported. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram dunit control low reg value. -+* -+*******************************************************************************/ -+static MV_U32 dunitCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas, MV_U32 busClk, MV_STATUS TTMode) -+{ -+ MV_U32 dunitCtrlLow, cl; -+ MV_U32 sbOutR[4]={3,5,7,9} ; -+ MV_U32 sbOutU[4]={1,3,5,7} ; -+ -+ dunitCtrlLow = MV_REG_READ(SDRAM_DUNIT_CTRL_REG); -+ -+ DB(mvOsPrintf("Dram: dunitCtrlLowRegCalc\n")); -+ -+ /* Clear StBurstOutDel field */ -+ dunitCtrlLow &= ~SDRAM_SB_OUT_MASK; -+ -+ /* Clear StBurstInDel field */ -+ dunitCtrlLow &= ~SDRAM_SB_IN_MASK; -+ -+ /* Clear CtrlPos field */ -+ dunitCtrlLow &= ~SDRAM_CTRL_POS_MASK; -+ -+ /* Clear 2T field */ -+ dunitCtrlLow &= ~SDRAM_2T_MASK; -+ if (TTMode == MV_TRUE) -+ { -+ dunitCtrlLow |= SDRAM_2T_MODE; -+ } -+ -+ /* For proper sample of read data set the Dunit Control register's */ -+ /* stBurstInDel bits [27:24] */ -+ /* 200MHz - 267MHz None reg = CL + 1 */ -+ /* 200MHz - 267MHz reg = CL + 2 */ -+ /* > 267MHz None reg = CL + 2 */ -+ /* > 267MHz reg = CL + 3 */ -+ -+ /* For proper sample of read data set the Dunit Control register's */ -+ /* stBurstOutDel bits [23:20] */ -+ /********-********-********-********- -+ * CL=3 | CL=4 | CL=5 | CL=6 | -+ *********-********-********-********- -+ Not Reg. * 0001 | 0011 | 0101 | 0111 | -+ *********-********-********-********- -+ Registered * 0011 | 0101 | 0111 | 1001 | -+ *********-********-********-********/ -+ -+ /* Set Dunit Control low default value */ -+ dunitCtrlLow |= SDRAM_DUNIT_CTRL_LOW_DDR2_DV; -+ -+ switch (minCas) -+ { -+ case DDR2_CL_3: cl = 3; break; -+ case DDR2_CL_4: cl = 4; break; -+ case DDR2_CL_5: cl = 5; break; -+ case DDR2_CL_6: cl = 6; break; -+ default: -+ mvOsOutput("Dram: dunitCtrlLowRegCalc Max. CL out of range %d\n", minCas); -+ return -1; -+ } -+ -+ /* registerd DDR SDRAM? */ -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ { -+ dunitCtrlLow |= (sbOutR[cl-3]) << SDRAM_SB_OUT_DEL_OFFS; -+ } -+ else -+ { -+ dunitCtrlLow |= (sbOutU[cl-3]) << SDRAM_SB_OUT_DEL_OFFS; -+ } -+ -+ DB(mvOsPrintf("\n\ndunitCtrlLowRegCalc: CL = %d, frequencies=%d\n", cl, busClk)); -+ -+ if (busClk <= MV_BOARD_SYSCLK_267MHZ) -+ { -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ cl = cl + 2; -+ else -+ cl = cl + 1; -+ } -+ else -+ { -+ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) -+ cl = cl + 3; -+ else -+ cl = cl + 2; -+ } -+ -+ DB(mvOsPrintf("dunitCtrlLowRegCalc: SDRAM_SB_IN_DEL_OFFS = %d \n", cl)); -+ dunitCtrlLow |= cl << SDRAM_SB_IN_DEL_OFFS; -+ -+ DB(mvOsPrintf("Dram: Reg dunit control low = %x\n", dunitCtrlLow )); -+ -+ return dunitCtrlLow; -+} -+ -+/******************************************************************************* -+* dunitCtrlHighRegCalc - Calculate sdram dunit control high register -+* -+* DESCRIPTION: Calculate sdram dunit control high register optimized value based -+* on the bus clock. -+* -+* INPUT: -+* busClk - DRAM frequency. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram dunit control high reg value. -+* -+*******************************************************************************/ -+static MV_U32 dunitCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) -+{ -+ MV_U32 dunitCtrlHigh; -+ dunitCtrlHigh = MV_REG_READ(SDRAM_DUNIT_CTRL_HI_REG); -+ if(busClk > MV_BOARD_SYSCLK_300MHZ) -+ dunitCtrlHigh |= SDRAM__P2D_EN; -+ else -+ dunitCtrlHigh &= ~SDRAM__P2D_EN; -+ -+ if(busClk > MV_BOARD_SYSCLK_267MHZ) -+ dunitCtrlHigh |= (SDRAM__WR_MESH_DELAY_EN | SDRAM__PUP_ZERO_SKEW_EN | SDRAM__ADD_HALF_FCC_EN); -+ -+ /* If ECC support we turn on D2P sample */ -+ dunitCtrlHigh &= ~SDRAM__D2P_EN; /* Clear D2P bit */ -+ if (( pBankInfo->errorCheckType ) && (busClk > MV_BOARD_SYSCLK_267MHZ)) -+ dunitCtrlHigh |= SDRAM__D2P_EN; -+ -+ return dunitCtrlHigh; -+} -+ -+/******************************************************************************* -+* sdramAddrCtrlRegCalc - Calculate sdram address control register -+* -+* DESCRIPTION: Calculate sdram address control register optimized value based -+* on the bank info parameters and the minCas. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram address control reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramAddrCtrlRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_DRAM_BANK_INFO *pBankInfoDIMM1) -+{ -+ MV_U32 addrCtrl = 0; -+ -+ if (pBankInfoDIMM1->size) -+ { -+ switch (pBankInfoDIMM1->sdramWidth) -+ { -+ case 4: /* memory is x4 */ -+ mvOsOutput("sdramAddrCtrlRegCalc: Error - x4 not supported!\n"); -+ return -1; -+ break; -+ case 8: /* memory is x8 */ -+ addrCtrl |= SDRAM_ADDRSEL_X8(2) | SDRAM_ADDRSEL_X8(3); -+ DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device DIMM2 width x8\n")); -+ break; -+ case 16: -+ addrCtrl |= SDRAM_ADDRSEL_X16(2) | SDRAM_ADDRSEL_X16(3); -+ DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device DIMM2 width x16\n")); -+ break; -+ default: /* memory width unsupported */ -+ mvOsOutput("sdramAddrCtrlRegCalc: ERR. DRAM chip width is unknown!\n"); -+ return -1; -+ } -+ } -+ -+ switch (pBankInfo->sdramWidth) -+ { -+ case 4: /* memory is x4 */ -+ mvOsOutput("sdramAddrCtrlRegCalc: Error - x4 not supported!\n"); -+ return -1; -+ break; -+ case 8: /* memory is x8 */ -+ addrCtrl |= SDRAM_ADDRSEL_X8(0) | SDRAM_ADDRSEL_X8(1); -+ DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device width x8\n")); -+ break; -+ case 16: -+ addrCtrl |= SDRAM_ADDRSEL_X16(0) | SDRAM_ADDRSEL_X16(1); -+ DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device width x16\n")); -+ break; -+ default: /* memory width unsupported */ -+ mvOsOutput("sdramAddrCtrlRegCalc: ERR. DRAM chip width is unknown!\n"); -+ return -1; -+ } -+ -+ /* Note that density is in MB units */ -+ switch (pBankInfo->deviceDensity) -+ { -+ case 256: /* 256 Mbit */ -+ DB(mvOsPrintf("DRAM Device Density 256Mbit\n")); -+ addrCtrl |= SDRAM_DSIZE_256Mb(0) | SDRAM_DSIZE_256Mb(1); -+ break; -+ case 512: /* 512 Mbit */ -+ DB(mvOsPrintf("DRAM Device Density 512Mbit\n")); -+ addrCtrl |= SDRAM_DSIZE_512Mb(0) | SDRAM_DSIZE_512Mb(1); -+ break; -+ case 1024: /* 1 Gbit */ -+ DB(mvOsPrintf("DRAM Device Density 1Gbit\n")); -+ addrCtrl |= SDRAM_DSIZE_1Gb(0) | SDRAM_DSIZE_1Gb(1); -+ break; -+ case 2048: /* 2 Gbit */ -+ DB(mvOsPrintf("DRAM Device Density 2Gbit\n")); -+ addrCtrl |= SDRAM_DSIZE_2Gb(0) | SDRAM_DSIZE_2Gb(1); -+ break; -+ default: -+ mvOsOutput("Dram: sdramAddrCtrl unsupported RAM-Device size %d\n", -+ pBankInfo->deviceDensity); -+ return -1; -+ } -+ -+ if (pBankInfoDIMM1->size) -+ { -+ switch (pBankInfoDIMM1->deviceDensity) -+ { -+ case 256: /* 256 Mbit */ -+ DB(mvOsPrintf("DIMM2: DRAM Device Density 256Mbit\n")); -+ addrCtrl |= SDRAM_DSIZE_256Mb(2) | SDRAM_DSIZE_256Mb(3); -+ break; -+ case 512: /* 512 Mbit */ -+ DB(mvOsPrintf("DIMM2: DRAM Device Density 512Mbit\n")); -+ addrCtrl |= SDRAM_DSIZE_512Mb(2) | SDRAM_DSIZE_512Mb(3); -+ break; -+ case 1024: /* 1 Gbit */ -+ DB(mvOsPrintf("DIMM2: DRAM Device Density 1Gbit\n")); -+ addrCtrl |= SDRAM_DSIZE_1Gb(2) | SDRAM_DSIZE_1Gb(3); -+ break; -+ case 2048: /* 2 Gbit */ -+ DB(mvOsPrintf("DIMM2: DRAM Device Density 2Gbit\n")); -+ addrCtrl |= SDRAM_DSIZE_2Gb(2) | SDRAM_DSIZE_2Gb(3); -+ break; -+ default: -+ mvOsOutput("DIMM2: Dram: sdramAddrCtrl unsupported RAM-Device size %d\n", -+ pBankInfoDIMM1->deviceDensity); -+ return -1; -+ } -+ } -+ /* SDRAM address control */ -+ DB(mvOsPrintf("Dram: setting sdram address control with: %x \n", addrCtrl)); -+ -+ return addrCtrl; -+} -+ -+/******************************************************************************* -+* sdramTimeCtrlLowRegCalc - Calculate sdram timing control low register -+* -+* DESCRIPTION: -+* This function calculates sdram timing control low register -+* optimized value based on the bank info parameters and the minCas. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* minCas - minimum CAS supported. -+* busClk - Bus clock -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram timing control low reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramTimeCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas, MV_U32 busClk) -+{ -+ MV_U32 tRp = 0; -+ MV_U32 tRrd = 0; -+ MV_U32 tRcd = 0; -+ MV_U32 tRas = 0; -+ MV_U32 tWr = 0; -+ MV_U32 tWtr = 0; -+ MV_U32 tRtp = 0; -+ MV_U32 timeCtrlLow = 0; -+ -+ MV_U32 bankNum; -+ -+ busClk = busClk / 1000000; /* In MHz */ -+ -+ /* Scan all DRAM banks to find maximum timing values */ -+ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ tRp = MV_MAX(tRp, pBankInfo[bankNum].minRowPrechargeTime); -+ tRrd = MV_MAX(tRrd, pBankInfo[bankNum].minRowActiveToRowActive); -+ tRcd = MV_MAX(tRcd, pBankInfo[bankNum].minRasToCasDelay); -+ tRas = MV_MAX(tRas, pBankInfo[bankNum].minRasPulseWidth); -+ } -+ -+ /* Extract timing (in ns) from SPD value. We ignore the tenth ns part. */ -+ /* by shifting the data two bits right. */ -+ tRp = tRp >> 2; /* For example 0x50 -> 20ns */ -+ tRrd = tRrd >> 2; -+ tRcd = tRcd >> 2; -+ -+ /* Extract clock cycles from time parameter. We need to round up */ -+ tRp = ((busClk * tRp) / 1000) + (((busClk * tRp) % 1000) ? 1 : 0); -+ DB(mvOsPrintf("Dram Timing Low: tRp = %d ", tRp)); -+ tRrd = ((busClk * tRrd) / 1000) + (((busClk * tRrd) % 1000) ? 1 : 0); -+ /* JEDEC min reqeirments tRrd = 2 */ -+ if (tRrd < 2) -+ tRrd = 2; -+ DB(mvOsPrintf("tRrd = %d ", tRrd)); -+ tRcd = ((busClk * tRcd) / 1000) + (((busClk * tRcd) % 1000) ? 1 : 0); -+ DB(mvOsPrintf("tRcd = %d ", tRcd)); -+ tRas = ((busClk * tRas) / 1000) + (((busClk * tRas) % 1000) ? 1 : 0); -+ DB(mvOsPrintf("tRas = %d ", tRas)); -+ -+ /* tWr and tWtr is different for DDR1 and DDR2. tRtp is only for DDR2 */ -+ /* Scan all DRAM banks to find maximum timing values */ -+ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ tWr = MV_MAX(tWr, pBankInfo[bankNum].minWriteRecoveryTime); -+ tWtr = MV_MAX(tWtr, pBankInfo[bankNum].minWriteToReadCmdDelay); -+ tRtp = MV_MAX(tRtp, pBankInfo[bankNum].minReadToPrechCmdDelay); -+ } -+ -+ /* Extract timing (in ns) from SPD value. We ignore the tenth ns */ -+ /* part by shifting the data two bits right. */ -+ tWr = tWr >> 2; /* For example 0x50 -> 20ns */ -+ tWtr = tWtr >> 2; -+ tRtp = tRtp >> 2; -+ /* Extract clock cycles from time parameter. We need to round up */ -+ tWr = ((busClk * tWr) / 1000) + (((busClk * tWr) % 1000) ? 1 : 0); -+ DB(mvOsPrintf("tWr = %d ", tWr)); -+ tWtr = ((busClk * tWtr) / 1000) + (((busClk * tWtr) % 1000) ? 1 : 0); -+ /* JEDEC min reqeirments tWtr = 2 */ -+ if (tWtr < 2) -+ tWtr = 2; -+ DB(mvOsPrintf("tWtr = %d ", tWtr)); -+ tRtp = ((busClk * tRtp) / 1000) + (((busClk * tRtp) % 1000) ? 1 : 0); -+ /* JEDEC min reqeirments tRtp = 2 */ -+ if (tRtp < 2) -+ tRtp = 2; -+ DB(mvOsPrintf("tRtp = %d ", tRtp)); -+ -+ /* Note: value of 0 in register means one cycle, 1 means two and so on */ -+ timeCtrlLow = (((tRp - 1) << SDRAM_TRP_OFFS) | -+ ((tRrd - 1) << SDRAM_TRRD_OFFS) | -+ ((tRcd - 1) << SDRAM_TRCD_OFFS) | -+ (((tRas - 1) << SDRAM_TRAS_OFFS) & SDRAM_TRAS_MASK)| -+ ((tWr - 1) << SDRAM_TWR_OFFS) | -+ ((tWtr - 1) << SDRAM_TWTR_OFFS) | -+ ((tRtp - 1) << SDRAM_TRTP_OFFS)); -+ -+ /* Check extended tRas bit */ -+ if ((tRas - 1) & BIT4) -+ timeCtrlLow |= (1 << SDRAM_EXT_TRAS_OFFS); -+ -+ return timeCtrlLow; -+} -+ -+/******************************************************************************* -+* sdramTimeCtrlHighRegCalc - Calculate sdram timing control high register -+* -+* DESCRIPTION: -+* This function calculates sdram timing control high register -+* optimized value based on the bank info parameters and the bus clock. -+* -+* INPUT: -+* pBankInfo - sdram bank parameters -+* busClk - Bus clock -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* sdram timing control high reg value. -+* -+*******************************************************************************/ -+static MV_U32 sdramTimeCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) -+{ -+ MV_U32 tRfc; -+ MV_U32 timingHigh; -+ MV_U32 timeNs = 0; -+ MV_U32 bankNum; -+ -+ busClk = busClk / 1000000; /* In MHz */ -+ -+ /* Set DDR timing high register static configuration bits */ -+ timingHigh = MV_REG_READ(SDRAM_TIMING_CTRL_HIGH_REG); -+ -+ /* Set DDR timing high register default value */ -+ timingHigh |= SDRAM_TIMING_CTRL_HIGH_REG_DV; -+ -+ /* Clear tRfc field */ -+ timingHigh &= ~SDRAM_TRFC_MASK; -+ -+ /* Scan all DRAM banks to find maximum timing values */ -+ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ timeNs = MV_MAX(timeNs, pBankInfo[bankNum].minRefreshToActiveCmd); -+ DB(mvOsPrintf("Dram: Timing High: minRefreshToActiveCmd = %d\n", -+ pBankInfo[bankNum].minRefreshToActiveCmd)); -+ } -+ if(busClk >= 333 && mvCtrlModelGet() == MV_78XX0_A1_REV) -+ { -+ timingHigh |= 0x1 << SDRAM_TR2W_W2R_OFFS; -+ } -+ -+ tRfc = ((busClk * timeNs) / 1000) + (((busClk * timeNs) % 1000) ? 1 : 0); -+ /* Note: value of 0 in register means one cycle, 1 means two and so on */ -+ DB(mvOsPrintf("Dram: Timing High: tRfc = %d\n", tRfc)); -+ timingHigh |= (((tRfc - 1) & SDRAM_TRFC_MASK) << SDRAM_TRFC_OFFS); -+ DB(mvOsPrintf("Dram: Timing High: tRfc = %d\n", tRfc)); -+ -+ /* SDRAM timing high */ -+ DB(mvOsPrintf("Dram: setting timing high with: %x \n", timingHigh)); -+ -+ return timingHigh; -+} -+/******************************************************************************* -+* sdramDDr2OdtConfig - Set DRAM DDR2 On Die Termination registers. -+* -+* DESCRIPTION: -+* This function config DDR2 On Die Termination (ODT) registers. -+* -+* INPUT: -+* pBankInfo - bank info parameters. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* None -+*******************************************************************************/ -+static void sdramDDr2OdtConfig(MV_DRAM_BANK_INFO *pBankInfo) -+{ -+ MV_U32 populateBanks = 0; -+ MV_U32 odtCtrlLow, odtCtrlHigh, dunitOdtCtrl; -+ int bankNum; -+ -+ /* Represent the populate banks in binary form */ -+ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) -+ { -+ if (0 != pBankInfo[bankNum].size) -+ { -+ populateBanks |= (1 << bankNum); -+ } -+ } -+ -+ switch(populateBanks) -+ { -+ case(BANK_PRESENT_CS0): -+ case(BANK_PRESENT_CS0_CS1): -+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS1_DV; -+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS1_DV; -+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV; -+ break; -+ case(BANK_PRESENT_CS0_CS2): -+ case(BANK_PRESENT_CS0_CS1_CS2): -+ case(BANK_PRESENT_CS0_CS2_CS3): -+ case(BANK_PRESENT_CS0_CS2_CS3_CS4): -+ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV; -+ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS1_CS2_CS3_DV; -+ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV; -+ break; -+ default: -+ DB(mvOsPrintf("sdramDDr2OdtConfig: Invalid DRAM bank presence\n")); -+ return; -+ } -+ /* DDR2 SDRAM ODT ctrl low */ -+ DB(mvOsPrintf("Dram: DDR2 setting ODT ctrl low with: %x \n", odtCtrlLow)); -+ MV_REG_WRITE(DRAM_BUF_REG7, odtCtrlLow); -+ -+ /* DDR2 SDRAM ODT ctrl high */ -+ DB(mvOsPrintf("Dram: DDR2 setting ODT ctrl high with: %x \n", odtCtrlHigh)); -+ MV_REG_WRITE(DRAM_BUF_REG8, odtCtrlHigh); -+ -+ /* DDR2 DUNIT ODT ctrl */ -+ if ( ((mvCtrlModelGet() == MV_78XX0_DEV_ID) && (mvCtrlRevGet() == MV_78XX0_Y0_REV)) || -+ (mvCtrlModelGet() == MV_76100_DEV_ID) || -+ (mvCtrlModelGet() == MV_78100_DEV_ID) || -+ (mvCtrlModelGet() == MV_78200_DEV_ID) ) -+ dunitOdtCtrl &= ~(BIT9|BIT8); /* Clear ODT always on */ -+ -+ DB(mvOsPrintf("DUNIT: DDR2 setting ODT ctrl with: %x \n", dunitOdtCtrl)); -+ MV_REG_WRITE(DRAM_BUF_REG9, dunitOdtCtrl); -+ return; -+} -+/******************************************************************************* -+* sdramDdr2TimeLoRegCalc - Set DDR2 DRAM Timing Low registers. -+* -+* DESCRIPTION: -+* This function config DDR2 DRAM Timing low registers. -+* -+* INPUT: -+* minCas - minimum CAS supported. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* DDR2 sdram timing low reg value. -+*******************************************************************************/ -+static MV_U32 sdramDdr2TimeLoRegCalc(MV_U32 minCas) -+{ -+ MV_U8 cl = -1; -+ MV_U32 ddr2TimeLoReg; -+ -+ /* read and clear the feilds we are going to set */ -+ ddr2TimeLoReg = MV_REG_READ(SDRAM_DDR2_TIMING_LO_REG); -+ ddr2TimeLoReg &= ~(SD2TLR_TODT_ON_RD_MASK | -+ SD2TLR_TODT_OFF_RD_MASK | -+ SD2TLR_TODT_ON_CTRL_RD_MASK | -+ SD2TLR_TODT_OFF_CTRL_RD_MASK); -+ -+ if( minCas == DDR2_CL_3 ) -+ { -+ cl = 3; -+ } -+ else if( minCas == DDR2_CL_4 ) -+ { -+ cl = 4; -+ } -+ else if( minCas == DDR2_CL_5 ) -+ { -+ cl = 5; -+ } -+ else if( minCas == DDR2_CL_6 ) -+ { -+ cl = 6; -+ } -+ else -+ { -+ DB(mvOsPrintf("sdramDdr2TimeLoRegCalc: CAS latency %d unsupported. using CAS latency 4\n", -+ minCas)); -+ cl = 4; -+ } -+ -+ ddr2TimeLoReg |= ((cl-3) << SD2TLR_TODT_ON_RD_OFFS); -+ ddr2TimeLoReg |= ( cl << SD2TLR_TODT_OFF_RD_OFFS); -+ ddr2TimeLoReg |= ( cl << SD2TLR_TODT_ON_CTRL_RD_OFFS); -+ ddr2TimeLoReg |= ((cl+3) << SD2TLR_TODT_OFF_CTRL_RD_OFFS); -+ -+ /* DDR2 SDRAM timing low */ -+ DB(mvOsPrintf("Dram: DDR2 setting timing low with: %x \n", ddr2TimeLoReg)); -+ -+ return ddr2TimeLoReg; -+} -+ -+/******************************************************************************* -+* sdramDdr2TimeHiRegCalc - Set DDR2 DRAM Timing High registers. -+* -+* DESCRIPTION: -+* This function config DDR2 DRAM Timing high registers. -+* -+* INPUT: -+* minCas - minimum CAS supported. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* DDR2 sdram timing high reg value. -+*******************************************************************************/ -+static MV_U32 sdramDdr2TimeHiRegCalc(MV_U32 minCas) -+{ -+ MV_U8 cl = -1; -+ MV_U32 ddr2TimeHiReg; -+ -+ /* read and clear the feilds we are going to set */ -+ ddr2TimeHiReg = MV_REG_READ(SDRAM_DDR2_TIMING_HI_REG); -+ ddr2TimeHiReg &= ~(SD2THR_TODT_ON_WR_MASK | -+ SD2THR_TODT_OFF_WR_MASK | -+ SD2THR_TODT_ON_CTRL_WR_MASK | -+ SD2THR_TODT_OFF_CTRL_WR_MASK); -+ -+ if( minCas == DDR2_CL_3 ) -+ { -+ cl = 3; -+ } -+ else if( minCas == DDR2_CL_4 ) -+ { -+ cl = 4; -+ } -+ else if( minCas == DDR2_CL_5 ) -+ { -+ cl = 5; -+ } -+ else if( minCas == DDR2_CL_6 ) -+ { -+ cl = 6; -+ } -+ else -+ { -+ mvOsOutput("sdramDdr2TimeHiRegCalc: CAS latency %d unsupported. using CAS latency 4\n", -+ minCas); -+ cl = 4; -+ } -+ -+ ddr2TimeHiReg |= ((cl-3) << SD2THR_TODT_ON_WR_OFFS); -+ ddr2TimeHiReg |= ( cl << SD2THR_TODT_OFF_WR_OFFS); -+ ddr2TimeHiReg |= ( cl << SD2THR_TODT_ON_CTRL_WR_OFFS); -+ ddr2TimeHiReg |= ((cl+3) << SD2THR_TODT_OFF_CTRL_WR_OFFS); -+ -+ /* DDR2 SDRAM timin high */ -+ DB(mvOsPrintf("Dram: DDR2 setting timing high with: %x \n", ddr2TimeHiReg)); -+ -+ return ddr2TimeHiReg; -+} -+#endif -+ -+/******************************************************************************* -+* mvDramIfCalGet - Get CAS Latency -+* -+* DESCRIPTION: -+* This function get the CAS Latency. -+* -+* INPUT: -+* None -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* CAS latency times 10 (to avoid using floating point). -+* -+*******************************************************************************/ -+MV_U32 mvDramIfCalGet(void) -+{ -+ MV_U32 sdramCasLat, casLatMask; -+ -+ casLatMask = (MV_REG_READ(SDRAM_MODE_REG) & SDRAM_CL_MASK); -+ -+ switch (casLatMask) -+ { -+ case SDRAM_DDR2_CL_3: -+ sdramCasLat = 30; -+ break; -+ case SDRAM_DDR2_CL_4: -+ sdramCasLat = 40; -+ break; -+ case SDRAM_DDR2_CL_5: -+ sdramCasLat = 50; -+ break; -+ case SDRAM_DDR2_CL_6: -+ sdramCasLat = 60; -+ break; -+ default: -+ mvOsOutput("mvDramIfCalGet: Err, unknown DDR2 CAL\n"); -+ return -1; -+ } -+ -+ return sdramCasLat; -+} -+ -+ -+/******************************************************************************* -+* mvDramIfSelfRefreshSet - Put the dram in self refresh mode - -+* -+* DESCRIPTION: -+* add support in power management. -+* -+* -+* INPUT: -+* None -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* None -+* -+*******************************************************************************/ -+ -+MV_VOID mvDramIfSelfRefreshSet() -+{ -+ MV_U32 operReg; -+ -+ operReg = MV_REG_READ(SDRAM_OPERATION_REG); -+ MV_REG_WRITE(SDRAM_OPERATION_REG ,operReg |SDRAM_CMD_SLF_RFRSH); -+ /* Read until register is reset to 0 */ -+ while(MV_REG_READ(SDRAM_OPERATION_REG)); -+} -+/******************************************************************************* -+* mvDramIfDimGetSPDversion - return DIMM SPD version. -+* -+* DESCRIPTION: -+* This function prints the DRAM controller information. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+static void mvDramIfDimGetSPDversion(MV_U32 *pMajor, MV_U32 *pMinor, MV_U32 bankNum) -+{ -+ MV_DIMM_INFO dimmInfo; -+ if (bankNum >= MV_DRAM_MAX_CS ) -+ { -+ DB(mvOsPrintf("Dram: mvDramIfDimGetSPDversion bad params \n")); -+ return ; -+ } -+ memset(&dimmInfo,0,sizeof(dimmInfo)); -+ if ( MV_OK != dimmSpdGet((MV_U32)(bankNum/2), &dimmInfo)) -+ { -+ DB(mvOsPrintf("Dram: ERR dimmSpdGet failed to get dimm info \n")); -+ return ; -+ } -+ *pMajor = dimmInfo.spdRawData[DIMM_SPD_VERSION]/10; -+ *pMinor = dimmInfo.spdRawData[DIMM_SPD_VERSION]%10; -+} -+/******************************************************************************* -+* mvDramIfShow - Show DRAM controller information. -+* -+* DESCRIPTION: -+* This function prints the DRAM controller information. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+void mvDramIfShow(void) -+{ -+ int i, sdramCasLat, sdramCsSize; -+ MV_U32 Major=0, Minor=0; -+ -+ mvOsOutput("DRAM Controller info:\n"); -+ -+ mvOsOutput("Total DRAM "); -+ mvSizePrint(mvDramIfSizeGet()); -+ mvOsOutput("\n"); -+ -+ for(i = 0; i < MV_DRAM_MAX_CS; i++) -+ { -+ sdramCsSize = mvDramIfBankSizeGet(i); -+ if (sdramCsSize) -+ { -+ if (0 == (i & 1)) -+ { -+ mvDramIfDimGetSPDversion(&Major, &Minor,i); -+ mvOsOutput("DIMM %d version %d.%d\n", i/2, Major, Minor); -+ } -+ mvOsOutput("\tDRAM CS[%d] ", i); -+ mvSizePrint(sdramCsSize); -+ mvOsOutput("\n"); -+ } -+ } -+ sdramCasLat = mvDramIfCalGet(); -+ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_ECC_EN) -+ { -+ mvOsOutput("ECC enabled, "); -+ } -+ else -+ { -+ mvOsOutput("ECC Disabled, "); -+ } -+ -+ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_REGISTERED) -+ { -+ mvOsOutput("Registered DIMM\n"); -+ } -+ else -+ { -+ mvOsOutput("Non registered DIMM\n"); -+ } -+ -+ mvOsOutput("Configured CAS Latency %d.%d\n", sdramCasLat/10, sdramCasLat%10); -+} -+/******************************************************************************* -+* mvDramIfGetFirstCS - find the DRAM bank on the lower address -+* -+* -+* DESCRIPTION: -+* This function return the fisrt CS on address 0 -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* SDRAM_CS0 or SDRAM_CS2 -+* -+*******************************************************************************/ -+MV_U32 mvDramIfGetFirstCS(void) -+{ -+ MV_DRAM_BANK_INFO bankInfo[MV_DRAM_MAX_CS]; -+ -+ if (DRAM_CS_Order[0] == N_A) -+ { -+ mvDramBankInfoGet(SDRAM_CS0, &bankInfo[SDRAM_CS0]); -+#ifdef MV_INCLUDE_SDRAM_CS2 -+ mvDramBankInfoGet(SDRAM_CS2, &bankInfo[SDRAM_CS2]); -+#endif -+ -+#ifdef MV_INCLUDE_SDRAM_CS2 -+ if (bankInfo[SDRAM_CS0].size < bankInfo[SDRAM_CS2].size) -+ { -+ DRAM_CS_Order[0] = SDRAM_CS2; -+ DRAM_CS_Order[1] = SDRAM_CS3; -+ DRAM_CS_Order[2] = SDRAM_CS0; -+ DRAM_CS_Order[3] = SDRAM_CS1; -+ -+ return SDRAM_CS2; -+ } -+#endif -+ DRAM_CS_Order[0] = SDRAM_CS0; -+ DRAM_CS_Order[1] = SDRAM_CS1; -+#ifdef MV_INCLUDE_SDRAM_CS2 -+ DRAM_CS_Order[2] = SDRAM_CS2; -+ DRAM_CS_Order[3] = SDRAM_CS3; -+#endif -+ return SDRAM_CS0; -+ } -+ return DRAM_CS_Order[0]; -+} -+/******************************************************************************* -+* mvDramIfGetCSorder - -+* -+* -+* DESCRIPTION: -+* This function return the fisrt CS on address 0 -+* -+* INPUT: -+* CS number. -+* -+* OUTPUT: -+* CS order. -+* -+* RETURN: -+* SDRAM_CS0 or SDRAM_CS2 -+* -+* NOTE: mvDramIfGetFirstCS must be caled before this subroutine -+*******************************************************************************/ -+MV_U32 mvDramIfGetCSorder(MV_U32 csOrder ) -+{ -+ return DRAM_CS_Order[csOrder]; -+} -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,172 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvDramIfh -+#define __INCmvDramIfh -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* includes */ -+#include "ddr2/mvDramIfRegs.h" -+#include "ddr2/mvDramIfConfig.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+ -+/* defines */ -+/* DRAM Timing parameters */ -+#define SDRAM_TWR 15 /* ns tWr */ -+#define SDRAM_TRFC_64_512M_AT_200MHZ 70 /* ns tRfc for dens 64-512 @ 200MHz */ -+#define SDRAM_TRFC_64_512M 75 /* ns tRfc for dens 64-512 */ -+#define SDRAM_TRFC_1G 120 /* ns tRfc for dens 1GB */ -+#define SDRAM_TR2R_CYC 1 /* cycle for tR2r */ -+ -+#define CAL_AUTO_DETECT 0 /* Do not force CAS latancy (mvDramIfDetect) */ -+#define ECC_DISABLE 1 /* Force ECC to Disable */ -+#define ECC_ENABLE 0 /* Force ECC to ENABLE */ -+/* typedefs */ -+ -+/* enumeration for memory types */ -+typedef enum _mvMemoryType -+{ -+ MEM_TYPE_SDRAM, -+ MEM_TYPE_DDR1, -+ MEM_TYPE_DDR2 -+}MV_MEMORY_TYPE; -+ -+/* enumeration for DDR2 supported CAS Latencies */ -+typedef enum _mvDimmDdr2Cas -+{ -+ DDR2_CL_3 = 0x08, -+ DDR2_CL_4 = 0x10, -+ DDR2_CL_5 = 0x20, -+ DDR2_CL_6 = 0x40, -+ DDR2_CL_FAULT -+} MV_DIMM_DDR2_CAS; -+ -+ -+typedef struct _mvDramBankInfo -+{ -+ MV_MEMORY_TYPE memoryType; /* DDR1, DDR2 or SDRAM */ -+ -+ /* DIMM dimensions */ -+ MV_U32 numOfRowAddr; -+ MV_U32 numOfColAddr; -+ MV_U32 dataWidth; -+ MV_U32 errorCheckType; /* ECC , PARITY..*/ -+ MV_U32 sdramWidth; /* 4,8,16 or 32 */ -+ MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ -+ MV_U32 burstLengthSupported; -+ MV_U32 numOfBanksOnEachDevice; -+ MV_U32 suportedCasLatencies; -+ MV_U32 refreshInterval; -+ -+ /* DIMM timing parameters */ -+ MV_U32 minCycleTimeAtMaxCasLatPs; -+ MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; -+ MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; -+ MV_U32 minRowPrechargeTime; -+ MV_U32 minRowActiveToRowActive; -+ MV_U32 minRasToCasDelay; -+ MV_U32 minRasPulseWidth; -+ MV_U32 minWriteRecoveryTime; /* DDR2 only */ -+ MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ -+ MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ -+ MV_U32 minRefreshToActiveCmd; /* DDR2 only */ -+ -+ /* Parameters calculated from the extracted DIMM information */ -+ MV_U32 size; -+ MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit */ -+ MV_U32 numberOfDevices; -+ -+ /* DIMM attributes (MV_TRUE for yes) */ -+ MV_BOOL registeredAddrAndControlInputs; -+ MV_BOOL registeredDQMBinputs; -+ -+}MV_DRAM_BANK_INFO; -+ -+#include "ddr2/spd/mvSpd.h" -+ -+/* mvDramIf.h API list */ -+MV_VOID mvDramIfBasicAsmInit(MV_VOID); -+MV_STATUS mvDramIfDetect(MV_U32 forcedCl, MV_BOOL eccDisable); -+MV_VOID _mvDramIfConfig(int entryNum); -+ -+MV_U32 mvDramIfBankSizeGet(MV_U32 bankNum); -+MV_U32 mvDramIfBankBaseGet(MV_U32 bankNum); -+MV_U32 mvDramIfSizeGet(MV_VOID); -+MV_U32 mvDramIfCalGet(void); -+MV_STATUS mvDramIfSingleBitErrThresholdSet(MV_U32 threshold); -+MV_VOID mvDramIfSelfRefreshSet(void); -+void mvDramIfShow(void); -+MV_U32 mvDramIfGetFirstCS(void); -+MV_U32 mvDramIfGetCSorder(MV_U32 csOrder ); -+MV_U32 mvDramCsSizeGet(MV_U32 csNum); -+ -+#ifdef __cplusplus -+} -+#endif /* __cplusplus */ -+ -+#endif /* __INCmvDramIfh */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfBasicInit.S linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfBasicInit.S ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfBasicInit.S 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfBasicInit.S 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,986 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#define _ASMLANGUAGE -+#define MV_ASMLANGUAGE -+#include "mvSysHwConfig.h" -+#include "mvOsAsm.h" -+#include "boardEnv/mvBoardEnvSpec.h" -+#include "ctrlEnv/sys/mvCpuIfRegs.h" -+#include "mvDramIfConfig.h" -+#include "mvDramIfRegs.h" -+#include "pex/mvPexRegs.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+#include "ctrlEnv/mvCtrlEnvAsm.h" -+#include "mvCommon.h" -+ -+/* defines */ -+ -+#if defined(MV_STATIC_DRAM_ON_BOARD) -+.globl dramBoot1 -+dramBoot1: -+ .word 0 -+ -+/****************************************************************************** -+* -+* -+* -+* -+*******************************************************************************/ -+#if defined(DB_MV78XX0) || defined(DB_MV88F632X) -+/* DDR2 boards 512MB 333MHz */ -+#define STATIC_SDRAM0_BANK0_SIZE 0x1ffffff1 /* 0x1504 */ -+#define STATIC_SDRAM_CONFIG 0x43048C30 /* 0x1400 */ -+#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */ -+#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */ -+#define STATIC_DUNIT_CTRL_HI 0x0000FFFF /* 0x1424 */ -+#define STATIC_SDRAM_ADDR_CTRL 0x00000088 /* 0x1410 */ -+#define STATIC_SDRAM_TIME_CTRL_LOW 0x22125441 /* 0x1408 */ -+#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A29 /* 0x140c */ -+#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */ -+#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ -+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000E80F /* 0x149c */ -+#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */ -+#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ -+#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ -+ -+#elif defined(RD_MV78XX0_AMC) -+/* On board DDR2 512MB 400MHz CL5 */ -+#define STATIC_SDRAM0_BANK0_SIZE 0x1ffffff1 /* 0x1504 */ -+#define STATIC_SDRAM_CONFIG 0x43008C30 /* 0x1400 */ -+#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */ -+#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */ -+#define STATIC_DUNIT_CTRL_HI 0x0000F07F /* 0x1424 */ -+#define STATIC_SDRAM_ADDR_CTRL 0x000000DD /* 0x1410 */ -+#define STATIC_SDRAM_TIME_CTRL_LOW 0x23135441 /* 0x1408 */ -+#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A32 /* 0x140c */ -+#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */ -+#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ -+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000EB0F /* 0x149c */ -+#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */ -+#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ -+#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ -+ -+#elif defined(RD_MV78XX0_H3C) -+/* DDR2 boards 512MB 333MHz */ -+#define STATIC_SDRAM0_BANK0_SIZE 0x1ffffff1 /* 0x1504 */ -+#define STATIC_SDRAM_CONFIG 0x43048a25 /* 0x1400 */ -+#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */ -+#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */ -+#define STATIC_DUNIT_CTRL_HI 0x0000F07F /* 0x1424 */ -+#define STATIC_SDRAM_ADDR_CTRL 0x00000088 /* 0x1410 */ -+#define STATIC_SDRAM_TIME_CTRL_LOW 0x2202444e /* 0x1408 */ -+#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A22 /* 0x140c */ -+#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */ -+#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ -+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000EB0F /* 0x149c */ -+#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */ -+#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ -+#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ -+ -+#elif defined(RD_MV78XX0_PCAC) -+/* DDR2 boards 256MB 200MHz */ -+#define STATIC_SDRAM0_BANK0_SIZE 0x0ffffff1 /* 0x1504 */ -+#define STATIC_SDRAM_CONFIG 0x43000a25 /* 0x1400 */ -+#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */ -+#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */ -+#define STATIC_DUNIT_CTRL_HI 0x0000F07F /* 0x1424 */ -+#define STATIC_SDRAM_ADDR_CTRL 0x000000DD /* 0x1410 */ -+#define STATIC_SDRAM_TIME_CTRL_LOW 0x2202444e /* 0x1408 */ -+#define STATIC_SDRAM_TIME_CTRL_HI 0x00000822 /* 0x140c */ -+#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */ -+#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ -+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000EB0F /* 0x149c */ -+#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */ -+#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ -+#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ -+ -+#else -+/* DDR2 MV88F6281 boards 256MB 400MHz */ -+#define STATIC_SDRAM0_BANK0_SIZE 0x0FFFFFF1 /* 0x1504 */ -+#define STATIC_SDRAM_CONFIG 0x43000c30 /* 0x1400 */ -+#define STATIC_SDRAM_MODE 0x00000C52 /* 0x141c */ -+#define STATIC_DUNIT_CTRL_LOW 0x39543000 /* 0x1404 */ -+#define STATIC_DUNIT_CTRL_HI 0x0000F1FF /* 0x1424 */ -+#define STATIC_SDRAM_ADDR_CTRL 0x000000cc /* 0x1410 */ -+#define STATIC_SDRAM_TIME_CTRL_LOW 0x22125451 /* 0x1408 */ -+#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A33 /* 0x140c */ -+#define STATIC_SDRAM_ODT_CTRL_LOW 0x003C0000 /* 0x1494 */ -+#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ -+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000F80F /* 0x149c */ -+#define STATIC_SDRAM_EXT_MODE 0x00000042 /* 0x1420 */ -+#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ -+#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ -+#endif /* MV78XX0 */ -+ -+ .globl _mvDramIfStaticInit -+_mvDramIfStaticInit: -+ -+ mov r11, LR /* Save link register */ -+ mov r10, r2 -+ -+#ifdef MV78XX0 -+ MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) -+ orr r6, r6, #BIT4 /* Enable 2T mode */ -+ bic r6, r6, #BIT6 /* clear ctrlPos */ -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) -+#endif -+ -+ /*DDR SDRAM Initialization Control */ -+ ldr r6, =DSICR_INIT_EN -+ MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) -+2: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) -+ and r6, r6, #DSICR_INIT_EN -+ cmp r6, #0 -+ bne 2b -+ -+ /* If we boot from NAND jump to DRAM address */ -+ mov r5, #1 -+ ldr r6, =dramBoot1 -+ str r5, [r6] /* We started executing from DRAM */ -+ -+ ldr r6, dramBoot1 -+ cmp r6, #0 -+ bne 1f -+ -+ /* set all dram windows to 0 */ -+ mov r6, #0 -+ MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,0)) -+ MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,1)) -+ MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,2)) -+ MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,3)) -+ ldr r6, = STATIC_SDRAM0_BANK0_SIZE -+ MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,0)) -+ -+ -+ /* set all dram configuration in temp registers */ -+ ldr r6, = STATIC_SDRAM0_BANK0_SIZE -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG0) -+ ldr r6, = STATIC_SDRAM_CONFIG -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG1) -+ ldr r6, = STATIC_SDRAM_MODE -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG2) -+ ldr r6, = STATIC_DUNIT_CTRL_LOW -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG3) -+ ldr r6, = STATIC_SDRAM_ADDR_CTRL -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG4) -+ ldr r6, = STATIC_SDRAM_TIME_CTRL_LOW -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG5) -+ ldr r6, = STATIC_SDRAM_TIME_CTRL_HI -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG6) -+ ldr r6, = STATIC_SDRAM_ODT_CTRL_LOW -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG7) -+ ldr r6, = STATIC_SDRAM_ODT_CTRL_HI -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG8) -+ ldr r6, = STATIC_SDRAM_DUNIT_ODT_CTRL -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG9) -+ ldr r6, = STATIC_SDRAM_EXT_MODE -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG10) -+ ldr r6, = STATIC_SDRAM_DDR2_TIMING_LO -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG11) -+ ldr r6, = STATIC_SDRAM_DDR2_TIMING_HI -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG12) -+#ifndef MV_NAND_BOOT -+ ldr r6, = STATIC_DUNIT_CTRL_HI -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG13) -+#endif -+ -+ ldr sp,=0 -+ bl _mvDramIfConfig -+ ldr r0, =0 -+#ifdef MV78XX0 -+ bl _mvDramIfEccMemInit -+#endif -+1: -+ mov r2, r10 -+ mov PC, r11 /* r11 is saved link register */ -+ -+#else /* #if defined(MV_STATIC_DRAM_ON_BOARD) */ -+ -+.globl dramBoot1 -+dramBoot1: -+ .word 0 -+ -+/******************************************************************************* -+* mvDramIfBasicInit - Basic initialization of DRAM interface -+* -+* DESCRIPTION: -+* The function will initialize the DRAM for basic usage. The function -+* will use the TWSI assembly API to extract DIMM parameters according -+* to which DRAM interface will be initialized. -+* The function referes to the following DRAM parameters: -+* 1) DIMM is registered or not. -+* 2) DIMM width detection. -+* 3) DIMM density. -+* -+* INPUT: -+* r3 - required size for initial DRAM. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+* Note: -+* r4 holds I2C EEPROM address -+* r5 holds SDRAM register base address -+* r7 holds returned values -+* r8 holds SDRAM various configuration registers value. -+* r11 holds return function address. -+*******************************************************************************/ -+/* Setting the offsets of the I2C registers */ -+#define DIMM_TYPE_OFFSET 2 -+#define NUM_OF_ROWS_OFFSET 3 -+#define NUM_OF_COLS_OFFSET 4 -+#define NUM_OF_RANKS 5 -+#define DIMM_CONFIG_TYPE 11 -+#define SDRAM_WIDTH_OFFSET 13 -+#define NUM_OF_BANKS_OFFSET 17 -+#define SUPPORTED_CL_OFFSET 18 -+#define DIMM_TYPE_INFO_OFFSET 20 /* DDR2 only */ -+#define SDRAM_MODULES_ATTR_OFFSET 21 -+#define RANK_SIZE_OFFSET 31 -+ -+#define DRAM_DEV_DENSITY_128M 128 -+#define DRAM_DEV_DENSITY_256M 256 -+#define DRAM_DEV_DENSITY_512M 512 -+#define DRAM_DEV_DENSITY_1G 1024 -+#define DRAM_DEV_DENSITY_2G 2048 -+ -+#define DRAM_RANK_DENSITY_128M 0x20 -+#define DRAM_RANK_DENSITY_256M 0x40 -+#define DRAM_RANK_DENSITY_512M 0x80 -+#define DRAM_RANK_DENSITY_1G 0x1 -+#define DRAM_RANK_DENSITY_2G 0x2 -+ -+ .globl _mvDramIfBasicInit -+ .extern _i2cInit -+_mvDramIfBasicInit: -+ -+ mov r11, LR /* Save link register */ -+ -+ /* Set Dunit high control register */ -+ MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_HI_REG) -+ orr r6, r6, #BIT7 /* SDRAM__D2P_EN */ -+ orr r6, r6, #BIT8 /* SDRAM__P2D_EN */ -+#ifdef MV78XX0 -+ orr r6, r6, #BIT9 /* SDRAM__ADD_HALF_FCC_EN */ -+ orr r6, r6, #BIT10 /* SDRAM__PUP_ZERO_SKEW_EN */ -+ orr r6, r6, #BIT11 /* SDRAM__WR_MASH_DELAY_EN */ -+#endif -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_HI_REG) -+ -+#ifdef MV78XX0 -+ MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) -+ orr r6, r6, #BIT4 /* Enable 2T mode */ -+ bic r6, r6, #BIT6 /* clear ctrlPos */ -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) -+#endif -+ -+ /*DDR SDRAM Initialization Control */ -+ ldr r6, =DSICR_INIT_EN -+ MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) -+2: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) -+ and r6, r6, #DSICR_INIT_EN -+ cmp r6, #0 -+ bne 2b -+ -+ mov r5, #1 -+ ldr r8, =dramBoot1 -+ str r5, [r8] /* We started executing from DRAM */ -+ -+ /* If we boot from NAND jump to DRAM address */ -+ ldr r8, dramBoot1 -+ cmp r8, #0 -+ movne pc, r11 -+ -+ bl _i2cInit /* Initialize TWSI master */ -+ -+ /* Check if we have more then 1 dimm */ -+ ldr r6, =0 -+ MV_REG_WRITE_ASM (r6, r1, DRAM_BUF_REG14) -+#ifdef MV78XX0 -+ bl _is_Second_Dimm_Exist -+ beq single_dimm -+ ldr r6, =1 -+ MV_REG_WRITE_ASM (r6, r1, DRAM_BUF_REG14) -+single_dimm: -+ bl _i2cInit /* Initialize TWSI master */ -+#endif -+ -+ /* Get default SDRAM Config values */ -+ MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG) -+ -+ /* Get registered/non registered info from DIMM */ -+ bl _is_Registered -+ beq nonRegistered -+ -+setRegistered: -+ orr r8, r8, #SDRAM_REGISTERED /* Set registered bit(17) */ -+nonRegistered: -+#ifdef MV78XX0 -+ /* Get ECC/non ECC info from DIMM */ -+ bl _is_Ecc -+ beq setConfigReg -+ -+setEcc: -+ orr r8, r8, #SDRAM_ECC_EN /* Set ecc bit(18) */ -+#endif -+setConfigReg: -+ MV_REG_WRITE_ASM (r8, r5, DRAM_BUF_REG1) -+ -+ /* Set maximum CL supported by DIMM */ -+ bl _get_CAL -+ -+ /* r7 is DIMM supported CAS (e.g: 3 --> 0x1C) */ -+ clz r6, r7 -+ rsb r6, r6, #31 /* r6 = the bit number of MAX CAS supported */ -+ -+casDdr2: -+ ldr r7, =0x41 /* stBurstInDel|stBurstOutDel field value */ -+ ldr r3, =0x53 /* stBurstInDel|stBurstOutDel registered value*/ -+ ldr r8, =0x32 /* Assuming MAX CL = 3 */ -+ cmp r6, #3 /* If CL = 3 break */ -+ beq casDdr2Cont -+ -+ ldr r7, =0x53 /* stBurstInDel|stBurstOutDel field value */ -+ ldr r3, =0x65 /* stBurstInDel|stBurstOutDel registered value*/ -+ ldr r8, =0x42 /* Assuming MAX CL = 4 */ -+ cmp r6, #4 /* If CL = 4 break */ -+ beq casDdr2Cont -+ -+ ldr r7, =0x65 /* stBurstInDel|stBurstOutDel field value */ -+ ldr r3, =0x77 /* stBurstInDel|stBurstOutDel registered value*/ -+ ldr r8, =0x52 /* Assuming MAX CL = 5 */ -+ cmp r6, #5 /* If CL = 5 break */ -+ beq casDdr2Cont -+ -+ ldr r7, =0x77 /* stBurstInDel|stBurstOutDel field value */ -+ ldr r3, =0x89 /* stBurstInDel|stBurstOutDel registered value*/ -+ ldr r8, =0x62 /* Assuming MAX CL = 6 */ -+ cmp r6, #6 /* If CL = 5 break */ -+ beq casDdr2Cont -+ -+ /* This is an error. return */ -+ b exit_ddrAutoConfig /* This is an error !! */ -+casDdr2Cont: -+ -+ /* Get default SDRAM Mode values */ -+ MV_REG_READ_ASM (r6, r5, SDRAM_MODE_REG) -+ bic r6, r6, #(BIT6 | BIT5 | BIT4) /* Clear CL filed */ -+ orr r6, r6, r8 -+ MV_REG_WRITE_ASM (r6, r5, DRAM_BUF_REG2) -+ -+ /* Set Dunit control register according to max CL detected */ -+ MV_REG_READ_ASM (r6, r5, DRAM_BUF_REG1) -+ tst r6, #SDRAM_REGISTERED -+ beq setDunitReg -+ mov r7, r3 -+ -+setDunitReg: -+#ifdef MV78XX0 -+ /* Set SDRAM Extended Mode register for double DIMM */ -+ /* Check DRAM frequency for more then 267MHz set ODT Rtt to 50ohm */ -+ -+ MV_REG_READ_ASM (r4, r5, CPU_RESET_SAMPLE_L_REG) -+ ldr r5, =MSAR_SYSCLCK_MASK -+ and r4, r4, r5 -+ ldr r5, =MSAR_SYSCLCK_333 -+ cmp r4, r5 -+ ble Clock333 -+ add r7, r7, #0x10 -+Clock333: -+#endif -+ -+ MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) -+ bic r6, r6, #(0xff << 20) /* Clear SBout and SBin */ -+ orr r6, r6, #BIT4 /* Enable 2T mode */ -+ bic r6, r6, #BIT6 /* clear ctrlPos */ -+ orr r6, r6, r7, LSL #20 -+ MV_REG_WRITE_ASM (r6, r5, DRAM_BUF_REG3) -+ -+ /* Set Dunit high control register */ -+ MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_HI_REG) -+ orr r6, r6, #BIT7 /* SDRAM__D2P_EN */ -+ orr r6, r6, #BIT8 /* SDRAM__P2D_EN */ -+#ifdef MV78XX0 -+ orr r6, r6, #BIT9 /* SDRAM__ADD_HALF_FCC_EN */ -+ orr r6, r6, #BIT10 /* SDRAM__PUP_ZERO_SKEW_EN */ -+ orr r6, r6, #BIT11 /* SDRAM__WR_MASH_DELAY_EN */ -+#endif -+ MV_REG_WRITE_ASM (r6, r5, DRAM_BUF_REG13) -+ -+ /* DIMM density configuration*/ -+ /* Density = (1 << (rowNum + colNum)) * dramWidth * dramBankNum */ -+Density: -+ /* Get bank 0 and 1 density */ -+ ldr r6, =0 -+ bl _getDensity -+ -+ mov r8, r7 -+ mov r8, r8, LSR #20 /* Move density 20 bits to the right */ -+ /* For example 0x10000000 --> 0x1000 */ -+ -+ mov r3, #(SDRAM_DSIZE_256Mb(0) | SDRAM_DSIZE_256Mb(1)) -+ cmp r8, #DRAM_DEV_DENSITY_256M -+ beq get_bank_2_density -+ -+ mov r3, #(SDRAM_DSIZE_512Mb(0) | SDRAM_DSIZE_512Mb(1)) -+ cmp r8, #DRAM_DEV_DENSITY_512M -+ beq get_bank_2_density -+ -+ mov r3, #(SDRAM_DSIZE_1Gb(0) | SDRAM_DSIZE_1Gb(1)) -+ cmp r8, #DRAM_DEV_DENSITY_1G -+ beq get_bank_2_density -+ -+ mov r3, #(SDRAM_DSIZE_2Gb(0) | SDRAM_DSIZE_2Gb(1)) -+ cmp r8, #DRAM_DEV_DENSITY_2G -+ beq get_bank_2_density -+ -+ /* This is an error. return */ -+ b exit_ddrAutoConfig -+ -+get_bank_2_density: -+ /* Check for second dimm */ -+ MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14) -+ cmp r6, #1 -+ bne get_width -+ -+ /* Get bank 2 and 3 density */ -+ ldr r6, =2 -+ bl _getDensity -+ -+ mov r8, r7 -+ mov r8, r8, LSR #20 /* Move density 20 bits to the right */ -+ /* For example 0x10000000 --> 0x1000 */ -+ -+ orr r3, r3, #(SDRAM_DSIZE_256Mb(2) | SDRAM_DSIZE_256Mb(3)) -+ cmp r8, #DRAM_DEV_DENSITY_256M -+ beq get_width -+ -+ and r3, r3, #~(SDRAM_DSIZE_MASK(2) | SDRAM_DSIZE_MASK(3)) -+ orr r3, r3, #(SDRAM_DSIZE_512Mb(2) | SDRAM_DSIZE_512Mb(3)) -+ cmp r8, #DRAM_DEV_DENSITY_512M -+ beq get_width -+ -+ and r3, r3, #~(SDRAM_DSIZE_MASK(2) | SDRAM_DSIZE_MASK(3)) -+ orr r3, r3, #(SDRAM_DSIZE_1Gb(2) | SDRAM_DSIZE_1Gb(3)) -+ cmp r8, #DRAM_DEV_DENSITY_1G -+ beq get_width -+ -+ and r3, r3, #~(SDRAM_DSIZE_MASK(2) | SDRAM_DSIZE_MASK(3)) -+ orr r3, r3, #(SDRAM_DSIZE_2Gb(2) | SDRAM_DSIZE_2Gb(3)) -+ cmp r8, #DRAM_DEV_DENSITY_2G -+ beq get_width -+ -+ /* This is an error. return */ -+ b exit_ddrAutoConfig -+ -+ /* Get SDRAM width */ -+get_width: -+ /* Get bank 0 and 1 width */ -+ ldr r6, =0 -+ bl _get_width -+ -+ cmp r7, #8 /* x8 devices */ -+ beq get_bank_2_width -+ -+ orr r3, r3, #(SDRAM_ADDRSEL_X16(0) | SDRAM_ADDRSEL_X16(1)) /* x16 devices */ -+ cmp r7, #16 -+ beq get_bank_2_width -+ -+ /* This is an error. return */ -+ b exit_ddrAutoConfig -+ -+get_bank_2_width: -+ /* Check for second dimm */ -+ MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14) -+ cmp r6, #1 -+ bne densCont -+ -+ /* Get bank 2 and 3 width */ -+ ldr r6, =2 -+ bl _get_width -+ -+ cmp r7, #8 /* x8 devices */ -+ beq densCont -+ -+ orr r3, r3, #(SDRAM_ADDRSEL_X16(2) | SDRAM_ADDRSEL_X16(3)) /* x16 devices */ -+ cmp r7, #16 -+ beq densCont -+ -+ /* This is an error. return */ -+ b exit_ddrAutoConfig -+ -+densCont: -+ MV_REG_WRITE_ASM (r3, r5, DRAM_BUF_REG4) -+ -+ /* Set SDRAM timing control low register */ -+ ldr r4, =SDRAM_TIMING_CTRL_LOW_REG_DEFAULT -+ /* MV_REG_READ_ASM (r4, r5, SDRAM_TIMING_CTRL_LOW_REG) */ -+ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG5) -+ -+ /* Set SDRAM timing control high register */ -+ ldr r6, =SDRAM_TIMING_CTRL_HIGH_REG_DEFAULT -+ -+ MV_REG_READ_ASM (r4, r5, CPU_RESET_SAMPLE_L_REG) -+ ldr r5, =MSAR_SYSCLCK_MASK -+ and r4, r4, r5 -+ ldr r5, =MSAR_SYSCLCK_333 -+ cmp r4, r5 -+ blt timingHighClock333 -+ orr r6, r6, #BIT9 -+ -+timingHighClock333: -+ /* MV_REG_READ_ASM (r6, r5, SDRAM_TIMING_CTRL_HIGH_REG) */ -+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG6) -+ -+ /* Check for second dimm */ -+ MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14) -+ cmp r6, #1 -+ bne single_dimm_odt -+ -+ /* Set SDRAM ODT control low register for double DIMM*/ -+ ldr r4, =DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV -+ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG7) -+ -+ /* Set DUNIT ODT control register for double DIMM */ -+ ldr r4, =DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV -+ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG9) -+ -+#ifdef MV78XX0 -+ /* Set SDRAM Extended Mode register for double DIMM */ -+ /* Check DRAM frequency for more then 267MHz set ODT Rtt to 50ohm */ -+ -+ MV_REG_READ_ASM (r4, r5, CPU_RESET_SAMPLE_L_REG) -+ ldr r5, =MSAR_SYSCLCK_MASK -+ and r4, r4, r5 -+ ldr r5, =MSAR_SYSCLCK_267 -+ cmp r4, r5 -+ beq slow_dram_clock_rtt -+ ldr r5, =MSAR_SYSCLCK_300 -+ cmp r4, r5 -+ beq slow_dram_clock_rtt -+ ldr r5, =MSAR_SYSCLCK_333 -+ cmp r4, r5 -+ beq fast_dram_clock_rtt -+ ldr r5, =MSAR_SYSCLCK_400 -+ cmp r4, r5 -+ beq fast_dram_clock_rtt -+ -+ b slow_dram_clock_rtt -+ -+fast_dram_clock_rtt: -+ ldr r4, =DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV -+ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG10) -+ b odt_config_end -+#endif -+slow_dram_clock_rtt: -+ ldr r4, =DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV -+ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG10) -+ b odt_config_end -+ -+single_dimm_odt: -+ /* Set SDRAM ODT control low register */ -+ ldr r4, =DDR2_ODT_CTRL_LOW_CS0_CS1_DV -+ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG7) -+ -+ /* Set DUNIT ODT control register */ -+ ldr r4, =DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV -+ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG9) -+ -+ /* Set SDRAM Extended Mode register */ -+ ldr r4, =DDR_SDRAM_EXT_MODE_CS0_CS1_DV -+ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG10) -+ -+odt_config_end: -+ /* SDRAM ODT control high register is left as default */ -+ MV_REG_READ_ASM (r4, r5, DDR2_SDRAM_ODT_CTRL_HIGH_REG) -+ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG8) -+ -+ /*Read CL and set the DDR2 registers accordingly */ -+ MV_REG_READ_ASM (r6, r5, DRAM_BUF_REG2) -+ and r6, r6, #SDRAM_CL_MASK -+ mov r4, r6 -+ orr r4, r4, r6, LSL #4 -+ orr r4, r4, r6, LSL #8 -+ orr r4, r4, r6, LSL #12 -+ mov r5, #0x30000 -+ add r4, r4, r5 -+ sub r4, r4, #0x30 -+ /* Set SDRAM Ddr2 Timing Low register */ -+ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG11) -+ -+ /* Set SDRAM Ddr2 Timing High register */ -+ mov r4, r4, LSR #4 -+ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG12) -+ -+timeParamDone: -+ /* Close all windows */ -+ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) -+ and r6, r6,#~SCSR_SIZE_MASK -+ and r6, r6,#~1 -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) -+ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,1)) -+ and r6, r6,#~SCSR_SIZE_MASK -+ and r6, r6,#~1 -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,1)) -+ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) -+ and r6, r6,#~SCSR_SIZE_MASK -+ and r6, r6,#~1 -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) -+ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,3)) -+ and r6, r6,#~SCSR_SIZE_MASK -+ and r6, r6,#~1 -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,3)) -+ -+ /* Set sdram bank 0 size and enable it */ -+ ldr r6, =0 -+ bl _mvDramIfGetDimmSizeFromSpd -+#ifdef MV78XX0 -+ /* Check DRAM width */ -+ MV_REG_READ_ASM (r4, r5, SDRAM_CONFIG_REG) -+ ldr r5, =SDRAM_DWIDTH_MASK -+ and r4, r4, r5 -+ ldr r5, =SDRAM_DWIDTH_64BIT -+ cmp r4, r5 -+ beq dram_64bit_width -+ /* Utilize only 32bit width */ -+ mov r8, r8, LSR #1 -+#else -+ /* Utilize only 16bit width */ -+ mov r8, r8, LSR #2 -+#endif -+dram_64bit_width: -+ /* Update first dimm size return value R8 */ -+ MV_REG_READ_ASM (r5, r6, SDRAM_SIZE_REG(0,0)) -+ ldr r6, =~SCSR_SIZE_MASK -+ and r5, r5, r6 -+ orr r5, r5, r8 -+ MV_REG_WRITE_ASM(r5, r8, SDRAM_SIZE_REG(0,0)) -+ -+ /* Clear bank 2 size */ -+ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) -+ and r6, r6,#~SCSR_SIZE_MASK -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) -+ -+ /* Check for second dimm */ -+ MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14) -+ cmp r6, #1 -+ bne defualt_order -+ -+ /* Set sdram bank 2 size */ -+ ldr r6, =2 -+ bl _mvDramIfGetDimmSizeFromSpd -+#ifdef MV78XX0 -+ /* Check DRAM width */ -+ MV_REG_READ_ASM (r4, r5, SDRAM_CONFIG_REG) -+ ldr r5, =SDRAM_DWIDTH_MASK -+ and r4, r4, r5 -+ ldr r5, =SDRAM_DWIDTH_64BIT -+ cmp r4, r5 -+ beq dram_64bit_width2 -+ /* Utilize only 32bit width */ -+ mov r8, r8, LSR #1 -+#else -+ /* Utilize only 16bit width */ -+ mov r8, r8, LSR #2 -+#endif -+dram_64bit_width2: -+ /* Update first dimm size return value R8 */ -+ MV_REG_READ_ASM (r5, r6, SDRAM_SIZE_REG(0,2)) -+ ldr r6, =~SCSR_SIZE_MASK -+ and r5, r5, r6 -+ orr r5, r5, r8 -+ MV_REG_WRITE_ASM(r5, r8, SDRAM_SIZE_REG(0,2)) -+ -+ /* Close windows 1 and 3 */ -+ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,1)) -+ and r6, r6,#~1 -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,1)) -+ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,3)) -+ and r6, r6,#~1 -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,3)) -+ -+ /* Check dimm size for setting dram bank order */ -+ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) -+ MV_REG_READ_ASM (r4, r5, SDRAM_SIZE_REG(0,2)) -+ and r6, r6,#SCSR_SIZE_MASK -+ and r4, r4,#SCSR_SIZE_MASK -+ cmp r6, r4 -+ bge defualt_order -+ -+ /* Bank 2 is biger then bank 0 */ -+ ldr r6,=0 -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_BASE_ADDR_REG(0,2)) -+ -+ /* Open win 2 */ -+ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) -+ orr r6, r6,#1 -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) -+ -+ ldr sp,=0 -+ bl _mvDramIfConfig -+#ifdef MV78XX0 -+ /* Init ECC on CS 2 */ -+ ldr r0, =2 -+ bl _mvDramIfEccMemInit -+#endif -+ mov PC, r11 /* r11 is saved link register */ -+ -+defualt_order: -+ -+ /* Open win 0 */ -+ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) -+ orr r6, r6,#1 -+ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) -+ -+ ldr sp,=0 -+ bl _mvDramIfConfig -+#ifdef MV78XX0 -+ /* Init ECC on CS 0 */ -+ ldr r0, =0 -+ bl _mvDramIfEccMemInit -+#endif -+exit_ddrAutoConfig: -+ mov PC, r11 /* r11 is saved link register */ -+ -+ -+/***************************************************************************************/ -+/* r4 holds I2C EEPROM address -+ * r7 holds I2C EEPROM offset parameter for i2cRead and its --> returned value -+ * r8 holds SDRAM various configuration registers value. -+ * r13 holds Link register -+ */ -+/**************************/ -+_getDensity: -+ mov r13, LR /* Save link register */ -+ -+ /* Read SPD rank size from DIMM0 */ -+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ -+ -+ cmp r6, #0 -+ beq 1f -+ -+ /* Read SPD rank size from DIMM1 */ -+ mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM1 */ -+ -+1: -+ mov r7, #NUM_OF_ROWS_OFFSET /* offset 3 */ -+ bl _i2cRead -+ mov r8, r7 /* r8 save number of rows */ -+ -+ mov r7, #NUM_OF_COLS_OFFSET /* offset 4 */ -+ bl _i2cRead -+ add r8, r8, r7 /* r8 = number of rows + number of col */ -+ -+ mov r7, #0x1 -+ mov r8, r7, LSL r8 /* r8 = (1 << r8) */ -+ -+ mov r7, #SDRAM_WIDTH_OFFSET /* offset 13 */ -+ bl _i2cRead -+ mul r8, r7, r8 -+ -+ mov r7, #NUM_OF_BANKS_OFFSET /* offset 17 */ -+ bl _i2cRead -+ mul r7, r8, r7 -+ -+ mov PC, r13 -+ -+/**************************/ -+_get_width: -+ mov r13, LR /* Save link register */ -+ -+ /* Read SPD rank size from DIMM0 */ -+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ -+ -+ cmp r6, #0 -+ beq 1f -+ -+ /* Read SPD rank size from DIMM1 */ -+ mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM1 */ -+ -+1: -+ /* Get SDRAM width (SPD offset 13) */ -+ mov r7, #SDRAM_WIDTH_OFFSET -+ bl _i2cRead /* result in r7 */ -+ -+ mov PC, r13 -+ -+/**************************/ -+_get_CAL: -+ mov r13, LR /* Save link register */ -+ -+ /* Set maximum CL supported by DIMM */ -+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ -+ mov r7, #SUPPORTED_CL_OFFSET /* offset 18 */ -+ bl _i2cRead -+ -+ mov PC, r13 -+ -+/**************************/ -+/* R8 - sdram configuration register. -+ * Return value in flag if no-registered then Z-flag is set -+ */ -+_is_Registered: -+ mov r13, LR /* Save link register */ -+#if defined(MV645xx) -+ /* Get registered/non registered info from DIMM */ -+ tst r8, #SDRAM_DTYPE_DDR2 -+ bne regDdr2 -+ -+regDdr1: -+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ -+ mov r7, #SDRAM_MODULES_ATTR_OFFSET -+ bl _i2cRead /* result in r7 */ -+ -+ tst r7, #0x2 -+ b exit -+#endif -+regDdr2: -+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ -+ mov r7, #DIMM_TYPE_INFO_OFFSET -+ bl _i2cRead /* result in r7 */ -+ -+ tst r7, #0x11 /* DIMM type = regular RDIMM (0x01) */ -+ /* or Mini-RDIMM (0x10) */ -+exit: -+ mov PC, r13 -+ -+ -+/**************************/ -+/* Return value in flag if no-Ecc then Z-flag is set */ -+_is_Ecc: -+ mov r13, LR /* Save link register */ -+ -+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ -+ mov r7, #DIMM_CONFIG_TYPE -+ bl _i2cRead /* result in r7 */ -+ -+ tst r7, #0x2 /* bit 1 -> Data ECC */ -+ mov PC, r13 -+ -+/**************************/ -+/* Return value in flag if no second DIMM then Z-flag is set */ -+_is_Second_Dimm_Exist: -+ mov r13, LR /* Save link register */ -+ -+ mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM0 */ -+ mov r7, #DIMM_TYPE_OFFSET -+ bl _i2cRead /* result in r7 */ -+ -+ tst r7, #0x8 /* bit3 is '1' -> DDR 2 */ -+ mov PC, r13 -+ -+/******************************************************************************* -+* _mvDramIfGetDimmSizeFromSpd - read bank 0 dram's size -+* -+* DESCRIPTION: -+* The function will read the bank 0 dram size(SPD version 1.0 and above ) -+* -+* INPUT: -+* r6 - dram bank number. -+* -+* OUTPUT: -+* none -+*/ -+_mvDramIfGetDimmSizeFromSpd: -+ -+ mov r13, LR /* Save link register */ -+ -+ /* Read SPD rank size from DIMM0 */ -+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ -+ -+ cmp r6, #0 -+ beq 1f -+ -+ /* Read SPD rank size from DIMM1 */ -+ mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM1 */ -+ -+1: -+ mov r7, #RANK_SIZE_OFFSET /* offset 31 */ -+ bl _i2cRead -+ -+pass_read: -+ ldr r8, =(0x7 << SCSR_SIZE_OFFS) -+ cmp r7, #DRAM_RANK_DENSITY_128M -+ beq endDimmSize -+ -+ ldr r8, =(0xf << SCSR_SIZE_OFFS) -+ cmp r7, #DRAM_RANK_DENSITY_256M -+ beq endDimmSize -+ -+ ldr r8, =(0x1f << SCSR_SIZE_OFFS) -+ cmp r7, #DRAM_RANK_DENSITY_512M -+ beq endDimmSize -+ -+ ldr r8, =(0x3f << SCSR_SIZE_OFFS) -+ cmp r7, #DRAM_RANK_DENSITY_1G -+ beq endDimmSize -+ -+ ldr r8, =(0x7f << SCSR_SIZE_OFFS) /* DRAM_RANK_DENSITY_2G */ -+endDimmSize: -+ mov PC, r13 -+#endif -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.S linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.S ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.S 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.S 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,528 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+/******************************************************************************* -+* mvDramIfBasicAsm.s -+* -+* DESCRIPTION: -+* Memory full detection and best timing configuration is done in -+* C code. C runtime environment requires a stack. This module API -+* initialize DRAM interface chip select 0 for basic functionality for -+* the use of stack. -+* The module API assumes DRAM information is stored in I2C EEPROM reside -+* in a given I2C address MV_BOARD_DIMM0_I2C_ADDR. The I2C EEPROM -+* internal data structure is assumed to be orgenzied in common DRAM -+* vendor SPD structure. -+* NOTE: DFCDL values are assumed to be already initialized prior to -+* this module API activity. -+* -+* -+* DEPENDENCIES: -+* None. -+* -+*******************************************************************************/ -+ -+/* includes */ -+#define _ASMLANGUAGE -+#define MV_ASMLANGUAGE -+#include "mvOsAsm.h" -+#include "mvSysHwConfig.h" -+#include "mvDramIfRegs.h" -+#include "mvDramIfConfig.h" -+#include "ctrlEnv/sys/mvCpuIfRegs.h" -+#include "pex/mvPexRegs.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+#include "mvCommon.h" -+ -+/* defines */ -+ -+/* locals */ -+.data -+.globl _mvDramIfConfig -+.text -+.globl _mvDramIfMemInit -+ -+/******************************************************************************* -+* _mvDramIfConfig - Basic DRAM interface initialization. -+* -+* DESCRIPTION: -+* The function will initialize the following DRAM parameters using the -+* values prepared by mvDramIfDetect routine. Values are located -+* in predefined registers. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+ -+_mvDramIfConfig: -+ -+ /* Save register on stack */ -+ cmp sp, #0 -+ beq no_stack_s -+save_on_stack: -+ stmdb sp!, {r1, r2, r3, r4} -+no_stack_s: -+ -+ /* Dunit FTDLL Configuration Register */ -+ /* 0) Write to SDRAM FTDLL coniguration register */ -+ ldr r4, = SDRAM_FTDLL_REG_DEFAULT_LEFT; -+ ldr r1, =(INTER_REGS_BASE + SDRAM_FTDLL_CONFIG_LEFT_REG) -+ str r4, [r1] -+ ldr r4, = SDRAM_FTDLL_REG_DEFAULT_RIGHT; -+ ldr r1, =(INTER_REGS_BASE + SDRAM_FTDLL_CONFIG_RIGHT_REG) -+ str r4, [r1] -+ ldr r4, = SDRAM_FTDLL_REG_DEFAULT_UP; -+ ldr r1, =(INTER_REGS_BASE + SDRAM_FTDLL_CONFIG_UP_REG) -+ str r4, [r1] -+ -+ /* 1) Write to SDRAM coniguration register */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG1) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + SDRAM_CONFIG_REG) -+ str r4, [r1] -+ -+ /* 2) Write Dunit control low register */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG3) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + SDRAM_DUNIT_CTRL_REG) -+ str r4, [r1] -+ -+ /* 2) Write Dunit control high register */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG13) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + SDRAM_DUNIT_CTRL_HI_REG) -+ str r4, [r1] -+ -+ /* 3) Write SDRAM address control register */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG4) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + SDRAM_ADDR_CTRL_REG) -+ str r4, [r1] -+#if defined(MV_STATIC_DRAM_ON_BOARD) -+ /* 4) Write SDRAM bank 0 size register */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG0) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + SDRAM_SIZE_REG(0,0)) -+ str r4, [r1] -+#endif -+ -+ /* 5) Write SDRAM open pages control register */ -+ ldr r1, =(INTER_REGS_BASE + SDRAM_OPEN_PAGE_CTRL_REG) -+ ldr r4, =SDRAM_OPEN_PAGES_CTRL_REG_DV -+ str r4, [r1] -+ -+ /* 6) Write SDRAM timing Low register */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG5) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_LOW_REG) -+ str r4, [r1] -+ -+ /* 7) Write SDRAM timing High register */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG6) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_HIGH_REG) -+ str r4, [r1] -+ -+ /* Config DDR2 On Die Termination (ODT) registers */ -+ /* Write SDRAM DDR2 ODT control low register */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG7) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_LOW_REG) -+ str r4, [r1] -+ -+ /* Write SDRAM DDR2 ODT control high register */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG8) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_HIGH_REG) -+ str r4, [r1] -+ -+ /* Write SDRAM DDR2 Dunit ODT control register */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG9) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + DDR2_DUNIT_ODT_CONTROL_REG) -+ str r4, [r1] -+ -+ /* Write DDR2 SDRAM timing Low register */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG11) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + SDRAM_DDR2_TIMING_LO_REG) -+ str r4, [r1] -+ -+ /* Write DDR2 SDRAM timing High register */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG12) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + SDRAM_DDR2_TIMING_HI_REG) -+ str r4, [r1] -+ -+ /* 8) Write SDRAM mode register */ -+ /* The CPU must not attempt to change the SDRAM Mode register setting */ -+ /* prior to DRAM controller completion of the DRAM initialization */ -+ /* sequence. To guarantee this restriction, it is recommended that */ -+ /* the CPU sets the SDRAM Operation register to NOP command, performs */ -+ /* read polling until the register is back in Normal operation value, */ -+ /* and then sets SDRAM Mode register to its new value. */ -+ -+ /* 8.1 write 'nop' to SDRAM operation */ -+ mov r4, #0x5 /* 'NOP' command */ -+ MV_REG_WRITE_ASM(r4, r1, SDRAM_OPERATION_REG) -+ -+ /* 8.2 poll SDRAM operation. Make sure its back to normal operation */ -+_sdramOpPoll1: -+ ldr r4, [r1] -+ cmp r4, #0 /* '0' = Normal SDRAM Mode */ -+ bne _sdramOpPoll1 -+ -+ /* 8.3 Now its safe to write new value to SDRAM Mode register */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG2) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + SDRAM_MODE_REG) -+ str r4, [r1] -+ -+ /* 8.4 Make the Dunit write the DRAM its new mode */ -+ mov r4, #0x3 /* Mode Register Set command */ -+ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) -+ -+ /* 8.5 poll SDRAM operation. Make sure its back to normal operation */ -+_sdramOpPoll2: -+ ldr r4, [r1] -+ cmp r4, #0 /* '0' = Normal SDRAM Mode */ -+ bne _sdramOpPoll2 -+ -+ /* Now its safe to write new value to SDRAM Extended Mode regist */ -+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG10) -+ ldr r4, [r1] -+ ldr r1, =(INTER_REGS_BASE + SDRAM_EXTENDED_MODE_REG) -+ str r4, [r1] -+ -+ /* 9) Write SDRAM Extended mode register This operation should be */ -+ /* done for each memory bank */ -+ /* write 'nop' to SDRAM operation */ -+ mov r4, #0x5 /* 'NOP' command */ -+ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) -+ -+ /* poll SDRAM operation. Make sure its back to normal operation */ -+_sdramOpPoll3: -+ ldr r4, [r1] -+ cmp r4, #0 /* '0' = Normal SDRAM Mode */ -+ bne _sdramOpPoll3 -+ /* Go over each of the Banks */ -+ ldr r3, =0 /* r3 = DRAM bank Num */ -+ -+extModeLoop: -+ /* Set the SDRAM Operation Control to each of the DRAM banks */ -+ mov r4, r3 /* Do not swap the bank counter value */ -+ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_CTRL_REG) -+ -+ /* Make the Dunit write the DRAM its new mode */ -+ mov r4, #0x4 /* Extended Mode Register Set command */ -+ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) -+ -+ /* poll SDRAM operation. Make sure its back to normal operation */ -+_sdramOpPoll4: -+ ldr r4, [r1] -+ cmp r4, #0 /* '0' = Normal SDRAM Mode */ -+ bne _sdramOpPoll4 -+ -+ add r3, r3, #1 -+ cmp r3, #4 /* 4 = Number of banks */ -+ bne extModeLoop -+ -+extModeEnd: -+cmp sp, #0 -+ beq no_stack_l -+ mov r1, LR /* Save link register */ -+#if defined(MV78XX0) -+ bl _mvDramIfMemInit -+#endif -+ mov LR,r1 /* restore link register */ -+load_from_stack: -+ /* Restore registers */ -+ ldmia sp!, {r1, r2, r3, r4} -+no_stack_l: -+ -+ mov pc, lr -+ -+ -+/******************************************************************************* -+* _mvDramIfEccMemInit - Basic DRAM ECC initialization. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+#define XOR_CHAN0 0 /* XOR channel 0 used for memory initialization */ -+#define XOR_UNIT0 0 /* XOR unit 0 used for memory initialization */ -+#define XOR_ADDR_DEC_WIN0 0 /* Enable DRAM access using XOR decode window 0 */ -+/* XOR engine register offsets macros */ -+#define XOR_CONFIG_REG(chan) (XOR_UNIT_BASE(0) + 0x10 + ((chan) * 4)) -+#define XOR_ACTIVATION_REG(chan) (XOR_UNIT_BASE(0) + 0x20 + ((chan) * 4)) -+#define XOR_CAUSE_REG (XOR_UNIT_BASE(0) + 0x30) -+#define XOR_ERROR_CAUSE_REG (XOR_UNIT_BASE(0) + 0x50) -+#define XOR_ERROR_ADDR_REG (XOR_UNIT_BASE(0) + 0x60) -+#define XOR_INIT_VAL_LOW_REG (XOR_UNIT_BASE(0) + 0x2E0) -+#define XOR_INIT_VAL_HIGH_REG (XOR_UNIT_BASE(0) + 0x2E4) -+#define XOR_DST_PTR_REG(chan) (XOR_UNIT_BASE(0) + 0x2B0 + ((chan) * 4)) -+#define XOR_BLOCK_SIZE_REG(chan) (XOR_UNIT_BASE(0) + 0x2C0 + ((chan) * 4)) -+ -+/* XOR Engine Address Decoding Register Map */ -+#define XOR_WINDOW_CTRL_REG(unit,chan) (XOR_UNIT_BASE(unit)+(0x240 + ((chan) * 4))) -+#define XOR_BASE_ADDR_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x250 + ((winNum) * 4))) -+#define XOR_SIZE_MASK_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x270 + ((winNum) * 4))) -+ -+.globl _mvDramIfEccMemInit -+/******************************************************************************* -+* _mvDramIfEccMemInit - mem init for dram cs -+* -+* DESCRIPTION: -+* This function will clean the cs by ussing the XOR mem init. -+* -+* INPUT: -+* r0 - dram bank number. -+* -+* OUTPUT: -+* none -+*/ -+_mvDramIfEccMemInit: -+ -+ /* Save register on stack */ -+ cmp sp, #0 -+ beq no_stack_s1 -+save_on_stack1: -+ stmdb sp!, {r0,r1, r2, r3, r4, r5, r6} -+no_stack_s1: -+ -+ ldr r1, = 0 -+ -+ /* Disable all XOR address decode windows to avoid possible overlap */ -+ MV_REG_WRITE_ASM (r1, r5, (XOR_WINDOW_CTRL_REG(XOR_UNIT0,XOR_CHAN0))) -+ -+ /* Init r5 to first XOR_SIZE_MASK_REG */ -+ mov r5, r0, LSL #3 -+ add r5, r5,#0x1500 -+ add r5, r5,#0x04 -+ add r5, r5,#(INTER_REGS_BASE) -+ ldr r6, [r5] -+ HTOLL(r6,r5) -+ MV_REG_WRITE_ASM (r6, r5, XOR_SIZE_MASK_REG(XOR_UNIT0,XOR_ADDR_DEC_WIN0)) -+ -+ mov r5, r0, LSL #3 -+ add r5, r5,#0x1500 -+ add r5, r5,#(INTER_REGS_BASE) -+ ldr r6, [r5] -+ /* Update destination & size */ -+ MV_REG_WRITE_ASM(r6, r5, XOR_DST_PTR_REG(XOR_CHAN0)) -+ HTOLL(r6,r5) -+ /* Init r6 to first XOR_BASE_ADDR_REG */ -+ ldr r4, = 0xf -+ ldr r5, = 0x1 -+ mov r5, r5, LSL r0 -+ bic r4, r4, r5 -+ mov r4, r4, LSL #8 -+ -+ orr r6, r6, r4 -+ MV_REG_WRITE_ASM (r6, r5, XOR_BASE_ADDR_REG(XOR_UNIT0,XOR_ADDR_DEC_WIN0)) -+ -+ ldr r6, = 0xff0001 -+ MV_REG_WRITE_ASM (r6, r5, XOR_WINDOW_CTRL_REG(XOR_UNIT0,XOR_CHAN0)) -+ -+ /* Configure XOR engine for memory init function. */ -+ MV_REG_READ_ASM (r6, r5, XOR_CONFIG_REG(XOR_CHAN0)) -+ and r6, r6, #~0x7 /* Clear operation mode field */ -+ orr r6, r6, #0x4 /* Set operation to memory init */ -+ MV_REG_WRITE_ASM(r6, r5, XOR_CONFIG_REG(XOR_CHAN0)) -+ -+ /* Set initVal in the XOR Engine Initial Value Registers */ -+ ldr r6, = 0xfeedfeed -+ MV_REG_WRITE_ASM(r6, r5, XOR_INIT_VAL_LOW_REG) -+ ldr r6, = 0xfeedfeed -+ MV_REG_WRITE_ASM(r6, r5, XOR_INIT_VAL_HIGH_REG) -+ -+ /* Set block size using DRAM bank size */ -+ -+ mov r5, r0, LSL #3 -+ add r5, r5,#0x1500 -+ add r5, r5,#0x04 -+ add r5, r5,#(INTER_REGS_BASE) -+ -+ ldr r6, [r5] -+ HTOLL(r6,r5) -+ and r6, r6, #SCSR_SIZE_MASK -+ mov r5, r6, LSR #SCSR_SIZE_OFFS -+ add r5, r5, #1 -+ mov r6, r5, LSL #SCSR_SIZE_OFFS -+ MV_REG_WRITE_ASM(r6, r5, XOR_BLOCK_SIZE_REG(XOR_CHAN0)) -+ -+ /* Clean interrupt cause*/ -+ MV_REG_WRITE_ASM(r1, r5, XOR_CAUSE_REG) -+ -+ /* Clean error interrupt cause*/ -+ MV_REG_READ_ASM(r6, r5, XOR_ERROR_CAUSE_REG) -+ MV_REG_READ_ASM(r6, r5, XOR_ERROR_ADDR_REG) -+ -+ /* Start transfer */ -+ MV_REG_READ_ASM (r6, r5, XOR_ACTIVATION_REG(XOR_CHAN0)) -+ orr r6, r6, #0x1 /* Preform start command */ -+ MV_REG_WRITE_ASM(r6, r5, XOR_ACTIVATION_REG(XOR_CHAN0)) -+ -+ /* Wait for engine to finish */ -+waitForComplete: -+ MV_REG_READ_ASM(r6, r5, XOR_CAUSE_REG) -+ and r6, r6, #2 -+ cmp r6, #0 -+ beq waitForComplete -+ -+ /* Clear all error report registers */ -+ MV_REG_WRITE_ASM(r1, r5, SDRAM_SINGLE_BIT_ERR_CNTR_REG) -+ MV_REG_WRITE_ASM(r1, r5, SDRAM_DOUBLE_BIT_ERR_CNTR_REG) -+ -+ MV_REG_WRITE_ASM(r1, r5, SDRAM_ERROR_CAUSE_REG) -+ -+ cmp sp, #0 -+ beq no_stack_l1 -+load_from_stack1: -+ ldmia sp!, {r0, r1, r2, r3, r4, r5, r6} -+no_stack_l1: -+ mov pc, lr -+ -+ -+/******************************************************************************* -+* mvDramIfMemInit - Use XOR to clear all memory. -+* -+* DESCRIPTION: -+* Use assembler function _mvDramIfEccMemInit to fill all memory with FEADFEAD pattern. -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+#if defined(MV78XX0) -+ -+_mvDramIfMemInit: -+ stmdb sp!, {r0,r1, r2, r3, r4, r5, r6} -+ mov r6, LR /* Save link register */ -+ /* Check if dram bank 0 has to be init for ECC */ -+ MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,0)) -+ and r3, r0, #SCSR_WIN_EN -+ cmp r3, #0 -+ beq no_bank_0 -+ MV_REG_READ_ASM(r0, r5, SDRAM_BASE_ADDR_REG(0,0)) -+ cmp r0, #0 -+ beq no_bank_0 -+ mov r0,#0 -+ bl _mvDramIfEccMemInit -+ -+no_bank_0: -+ /* Check if dram bank 1 has to be init for ECC */ -+ MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,1)) -+ and r0, r0, #SCSR_WIN_EN -+ cmp r0, #0 -+ beq no_bank_1 -+ mov r0,#1 -+ bl _mvDramIfEccMemInit -+no_bank_1: -+ /* Check if dram bank 2 has to be init for ECC */ -+ MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,2)) -+ and r0, r0, #SCSR_WIN_EN -+ cmp r0, #0 -+ beq no_bank_2 -+ MV_REG_READ_ASM(r0, r5, SDRAM_BASE_ADDR_REG(0,2)) -+ cmp r0, #0 -+ beq no_bank_2 -+ mov r0,#2 -+ bl _mvDramIfEccMemInit -+ -+no_bank_2: -+ /* Check if dram bank 3 has to be init for ECC */ -+ MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,3)) -+ and r0, r0, #SCSR_WIN_EN -+ cmp r0, #0 -+ beq no_bank_3 -+ mov r0,#3 -+ bl _mvDramIfEccMemInit -+no_bank_3: -+ mov LR ,r6 /* restore link register */ -+ ldmia sp!, {r0, r1, r2, r3, r4, r5, r6} -+ mov pc, lr -+#endif -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,157 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvDramIfConfigh -+#define __INCmvDramIfConfigh -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* includes */ -+ -+/* defines */ -+ -+/* registers defaults values */ -+ -+#define SDRAM_CONFIG_DV (SDRAM_SRMODE_DRAM | BIT25 | BIT30) -+ -+#define SDRAM_DUNIT_CTRL_LOW_DDR2_DV \ -+ (SDRAM_SRCLK_KEPT | \ -+ SDRAM_CLK1DRV_NORMAL | \ -+ (BIT28 | BIT29)) -+ -+#define SDRAM_ADDR_CTRL_DV 2 -+ -+#define SDRAM_TIMING_CTRL_LOW_REG_DV \ -+ ((0x2 << SDRAM_TRCD_OFFS) | \ -+ (0x2 << SDRAM_TRP_OFFS) | \ -+ (0x1 << SDRAM_TWR_OFFS) | \ -+ (0x0 << SDRAM_TWTR_OFFS) | \ -+ (0x5 << SDRAM_TRAS_OFFS) | \ -+ (0x1 << SDRAM_TRRD_OFFS)) -+ -+/* Note: value of 0 in register means one cycle, 1 means two and so on */ -+#define SDRAM_TIMING_CTRL_HIGH_REG_DV \ -+ ((0x0 << SDRAM_TR2R_OFFS) | \ -+ (0x0 << SDRAM_TR2W_W2R_OFFS) | \ -+ (0x1 << SDRAM_TW2W_OFFS)) -+ -+#define SDRAM_OPEN_PAGES_CTRL_REG_DV SDRAM_OPEN_PAGE_EN -+ -+/* Presence Ctrl Low Ctrl High Dunit Ctrl Ext Mode */ -+/* CS0 0x84210000 0x00000000 0x0000780F 0x00000440 */ -+/* CS0+CS1 0x84210000 0x00000000 0x0000780F 0x00000440 */ -+/* CS0+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -+/* CS0+CS1+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -+/* CS0+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -+/* CS0+CS1+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ -+ -+#define DDR2_ODT_CTRL_LOW_CS0_CS1_DV 0x84210000 -+#define DDR2_ODT_CTRL_HIGH_CS0_CS1_DV 0x00000000 -+#define DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV 0x0000E80F -+#ifdef MV78XX0 -+#define DDR_SDRAM_EXT_MODE_CS0_CS1_DV 0x00000040 -+#else -+#define DDR_SDRAM_EXT_MODE_CS0_CS1_DV 0x00000440 -+#endif -+ -+#define DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV 0x030C030C -+#define DDR2_ODT_CTRL_HIGH_CS0_CS1_CS2_CS3_DV 0x00000000 -+#define DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV 0x0000F40F -+#ifdef MV78XX0 -+#define DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV 0x00000004 -+#define DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV 0x00000044 -+#else -+#define DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV 0x00000404 -+#define DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV 0x00000444 -+#endif -+ -+/* DDR SDRAM Adderss/Control and Data Pads Calibration default values */ -+#define DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \ -+ (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) -+ -+#define DDR2_DATA_PAD_STRENGTH_TYPICAL_DV \ -+ (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) -+ -+/* DDR SDRAM Mode Register default value */ -+#define DDR2_MODE_REG_DV (SDRAM_BURST_LEN_4 | SDRAM_WR_3_CYC) -+/* DDR SDRAM Timing parameter default values */ -+#define SDRAM_TIMING_CTRL_LOW_REG_DEFAULT 0x33136552 -+#define SDRAM_TRFC_DEFAULT_VALUE 0x34 -+#define SDRAM_TRFC_DEFAULT SDRAM_TRFC_DEFAULT_VALUE -+#define SDRAM_TW2W_DEFALT (0x1 << SDRAM_TW2W_OFFS) -+ -+#define SDRAM_TIMING_CTRL_HIGH_REG_DEFAULT (SDRAM_TRFC_DEFAULT | SDRAM_TW2W_DEFALT) -+ -+#define SDRAM_FTDLL_REG_DEFAULT_LEFT 0x88C800 -+#define SDRAM_FTDLL_REG_DEFAULT_RIGHT 0x88C800 -+#define SDRAM_FTDLL_REG_DEFAULT_UP 0x88C800 -+ -+#ifdef __cplusplus -+} -+#endif /* __cplusplus */ -+ -+#endif /* __INCmvDramIfh */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,423 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvDramIfRegsh -+#define __INCmvDramIfRegsh -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* DDR SDRAM Controller Address Decode Registers */ -+ /* SDRAM CSn Base Address Register (SCBAR) */ -+#define SDRAM_BASE_ADDR_REG(cpu,csNum) (0x1500 + ((csNum) * 8) + ((cpu) * 0x70)) -+#define SCBAR_BASE_OFFS 16 -+#define SCBAR_BASE_MASK (0xffff << SCBAR_BASE_OFFS) -+#define SCBAR_BASE_ALIGNMENT 0x10000 -+ -+/* SDRAM CSn Size Register (SCSR) */ -+#define SDRAM_SIZE_REG(cpu,csNum) (0x1504 + ((csNum) * 8) + ((cpu) * 0x70)) -+#define SCSR_SIZE_OFFS 24 -+#define SCSR_SIZE_MASK (0xff << SCSR_SIZE_OFFS) -+#define SCSR_SIZE_ALIGNMENT 0x1000000 -+#define SCSR_WIN_EN BIT0 -+ -+/* configuration register */ -+#define SDRAM_CONFIG_REG (DRAM_BASE + 0x1400) -+#define SDRAM_REFRESH_OFFS 0 -+#define SDRAM_REFRESH_MAX 0x3FFF -+#define SDRAM_REFRESH_MASK (SDRAM_REFRESH_MAX << SDRAM_REFRESH_OFFS) -+#define SDRAM_DWIDTH_OFFS 15 -+#define SDRAM_DWIDTH_MASK (1 << SDRAM_DWIDTH_OFFS) -+#define SDRAM_DWIDTH_32BIT (0 << SDRAM_DWIDTH_OFFS) -+#define SDRAM_DWIDTH_64BIT (1 << SDRAM_DWIDTH_OFFS) -+#define SDRAM_REGISTERED (1 << 17) -+#define SDRAM_ECC_OFFS 18 -+#define SDRAM_ECC_MASK (1 << SDRAM_ECC_OFFS) -+#define SDRAM_ECC_DIS (0 << SDRAM_ECC_OFFS) -+#define SDRAM_ECC_EN (1 << SDRAM_ECC_OFFS) -+#define SDRAM_IERR_OFFS 19 -+#define SDRAM_IERR_MASK (1 << SDRAM_IERR_OFFS) -+#define SDRAM_IERR_REPORTE (0 << SDRAM_IERR_OFFS) -+#define SDRAM_IERR_IGNORE (1 << SDRAM_IERR_OFFS) -+#define SDRAM_SRMODE_OFFS 24 -+#define SDRAM_SRMODE_MASK (1 << SDRAM_SRMODE_OFFS) -+#define SDRAM_SRMODE_POWER (0 << SDRAM_SRMODE_OFFS) -+#define SDRAM_SRMODE_DRAM (1 << SDRAM_SRMODE_OFFS) -+ -+/* dunit control low register */ -+#define SDRAM_DUNIT_CTRL_REG (DRAM_BASE + 0x1404) -+#define SDRAM_2T_OFFS 4 -+#define SDRAM_2T_MASK (1 << SDRAM_2T_OFFS) -+#define SDRAM_2T_MODE (1 << SDRAM_2T_OFFS) -+ -+#define SDRAM_SRCLK_OFFS 5 -+#define SDRAM_SRCLK_MASK (1 << SDRAM_SRCLK_OFFS) -+#define SDRAM_SRCLK_KEPT (0 << SDRAM_SRCLK_OFFS) -+#define SDRAM_SRCLK_GATED (1 << SDRAM_SRCLK_OFFS) -+#define SDRAM_CTRL_POS_OFFS 6 -+#define SDRAM_CTRL_POS_MASK (1 << SDRAM_CTRL_POS_OFFS) -+#define SDRAM_CTRL_POS_FALL (0 << SDRAM_CTRL_POS_OFFS) -+#define SDRAM_CTRL_POS_RISE (1 << SDRAM_CTRL_POS_OFFS) -+#define SDRAM_CLK1DRV_OFFS 12 -+#define SDRAM_CLK1DRV_MASK (1 << SDRAM_CLK1DRV_OFFS) -+#define SDRAM_CLK1DRV_HIGH_Z (0 << SDRAM_CLK1DRV_OFFS) -+#define SDRAM_CLK1DRV_NORMAL (1 << SDRAM_CLK1DRV_OFFS) -+#define SDRAM_CLK2DRV_OFFS 13 -+#define SDRAM_CLK2DRV_MASK (1 << SDRAM_CLK2DRV_OFFS) -+#define SDRAM_CLK2DRV_HIGH_Z (0 << SDRAM_CLK2DRV_OFFS) -+#define SDRAM_CLK2DRV_NORMAL (1 << SDRAM_CLK2DRV_OFFS) -+#define SDRAM_SB_OUT_DEL_OFFS 20 -+#define SDRAM_SB_OUT_DEL_MAX 0xf -+#define SDRAM_SB_OUT_MASK (SDRAM_SB_OUT_DEL_MAX<= MV_DRAM_MAX_CS )) -+ { -+ DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); -+ return MV_BAD_PARAM; -+ } -+ memset(pBankInfo, 0, sizeof(*pBankInfo)); -+ -+ if ( MV_OK != dimmSpdGet((MV_U32)(bankNum/2), &dimmInfo)) -+ { -+ DB(mvOsPrintf("Dram: ERR dimmSpdGet failed to get dimm info \n")); -+ return MV_FAIL; -+ } -+ if ((dimmInfo.numOfModuleBanks == 1) && ((bankNum % 2) == 1)) -+ { -+ DB(mvOsPrintf("Dram: ERR dimmSpdGet. Can't find DIMM bank 2 \n")); -+ return MV_FAIL; -+ } -+ /* convert Dimm info to Bank info */ -+ cpyDimm2BankInfo(&dimmInfo, pBankInfo); -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* cpyDimm2BankInfo - Convert a Dimm info struct into a bank info struct. -+* -+* DESCRIPTION: -+* Convert a Dimm info struct into a bank info struct. -+* -+* INPUT: -+* pDimmInfo - DIMM information structure. -+* -+* OUTPUT: -+* pBankInfo - DRAM bank information struct. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+static MV_VOID cpyDimm2BankInfo(MV_DIMM_INFO *pDimmInfo, -+ MV_DRAM_BANK_INFO *pBankInfo) -+{ -+ pBankInfo->memoryType = pDimmInfo->memoryType; -+ -+ /* DIMM dimensions */ -+ pBankInfo->numOfRowAddr = pDimmInfo->numOfRowAddr; -+ pBankInfo->numOfColAddr = pDimmInfo->numOfColAddr; -+ pBankInfo->dataWidth = pDimmInfo->dataWidth; -+ pBankInfo->errorCheckType = pDimmInfo->errorCheckType; -+ pBankInfo->sdramWidth = pDimmInfo->sdramWidth; -+ pBankInfo->errorCheckDataWidth = pDimmInfo->errorCheckDataWidth; -+ pBankInfo->numOfBanksOnEachDevice = pDimmInfo->numOfBanksOnEachDevice; -+ pBankInfo->suportedCasLatencies = pDimmInfo->suportedCasLatencies; -+ pBankInfo->refreshInterval = pDimmInfo->refreshInterval; -+ -+ /* DIMM timing parameters */ -+ pBankInfo->minCycleTimeAtMaxCasLatPs = pDimmInfo->minCycleTimeAtMaxCasLatPs; -+ pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps = -+ pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps; -+ pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps = -+ pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps; -+ -+ pBankInfo->minRowPrechargeTime = pDimmInfo->minRowPrechargeTime; -+ pBankInfo->minRowActiveToRowActive = pDimmInfo->minRowActiveToRowActive; -+ pBankInfo->minRasToCasDelay = pDimmInfo->minRasToCasDelay; -+ pBankInfo->minRasPulseWidth = pDimmInfo->minRasPulseWidth; -+ pBankInfo->minWriteRecoveryTime = pDimmInfo->minWriteRecoveryTime; -+ pBankInfo->minWriteToReadCmdDelay = pDimmInfo->minWriteToReadCmdDelay; -+ pBankInfo->minReadToPrechCmdDelay = pDimmInfo->minReadToPrechCmdDelay; -+ pBankInfo->minRefreshToActiveCmd = pDimmInfo->minRefreshToActiveCmd; -+ -+ /* Parameters calculated from the extracted DIMM information */ -+ pBankInfo->size = pDimmInfo->size/pDimmInfo->numOfModuleBanks; -+ pBankInfo->deviceDensity = pDimmInfo->deviceDensity; -+ pBankInfo->numberOfDevices = pDimmInfo->numberOfDevices / -+ pDimmInfo->numOfModuleBanks; -+ -+ /* DIMM attributes (MV_TRUE for yes) */ -+ -+ if ((pDimmInfo->memoryType == MEM_TYPE_SDRAM) || -+ (pDimmInfo->memoryType == MEM_TYPE_DDR1) ) -+ { -+ if (pDimmInfo->dimmAttributes & BIT1) -+ pBankInfo->registeredAddrAndControlInputs = MV_TRUE; -+ else -+ pBankInfo->registeredAddrAndControlInputs = MV_FALSE; -+ } -+ else /* pDimmInfo->memoryType == MEM_TYPE_DDR2 */ -+ { -+ if (pDimmInfo->dimmTypeInfo & (BIT0 | BIT4)) -+ pBankInfo->registeredAddrAndControlInputs = MV_TRUE; -+ else -+ pBankInfo->registeredAddrAndControlInputs = MV_FALSE; -+ } -+ -+ return; -+} -+/******************************************************************************* -+* dimmSpdCpy - Cpy SPD parameters from dimm 0 to dimm 1. -+* -+* DESCRIPTION: -+* Read the DIMM SPD parameters from dimm 0 into dimm 1 SPD. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+MV_STATUS dimmSpdCpy(MV_VOID) -+{ -+ MV_U32 i; -+ MV_U32 spdChecksum; -+ -+ MV_TWSI_SLAVE twsiSlave; -+ MV_U8 data[SPD_SIZE]; -+ -+ /* zero dimmInfo structure */ -+ memset(data, 0, SPD_SIZE); -+ -+ /* read the dimm eeprom */ -+ DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); -+ twsiSlave.slaveAddr.address = MV_BOARD_DIMM0_I2C_ADDR; -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ twsiSlave.offset = 0; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, &twsiSlave, data, SPD_SIZE) ) -+ { -+ DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 0\n")); -+ return MV_FAIL; -+ } -+ DB(puts("DRAM: Reading dimm info succeded.\n")); -+ -+ /* calculate SPD checksum */ -+ spdChecksum = 0; -+ -+ for(i = 0 ; i <= 62 ; i++) -+ { -+ spdChecksum += data[i]; -+ } -+ -+ if ((spdChecksum & 0xff) != data[63]) -+ { -+ DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", -+ (MV_U32)(spdChecksum & 0xff), data[63])); -+ } -+ else -+ { -+ DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); -+ } -+ -+ /* copy the SPD content 1:1 into the DIMM 1 SPD */ -+ twsiSlave.slaveAddr.address = MV_BOARD_DIMM1_I2C_ADDR; -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ twsiSlave.offset = 0; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ for(i = 0 ; i < SPD_SIZE ; i++) -+ { -+ twsiSlave.offset = i; -+ if( MV_OK != mvTwsiWrite (MV_BOARD_DIMM_I2C_CHANNEL, &twsiSlave, &data[i], 1) ) -+ { -+ mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 1 byte %d \n",i); -+ return MV_FAIL; -+ } -+ mvOsDelay(5); -+ } -+ -+ DB(puts("DRAM: Reading dimm info succeded.\n")); -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* dimmSpdGet - Get the SPD parameters. -+* -+* DESCRIPTION: -+* Read the DIMM SPD parameters into given struct parameter. -+* -+* INPUT: -+* dimmNum - DIMM number. See MV_BOARD_DIMM_NUM enumerator. -+* -+* OUTPUT: -+* pDimmInfo - DIMM information structure. -+* -+* RETURN: -+* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo) -+{ -+ MV_U32 i; -+ MV_U32 density = 1; -+ MV_U32 spdChecksum; -+ -+ MV_TWSI_SLAVE twsiSlave; -+ MV_U8 data[SPD_SIZE]; -+ -+ if((NULL == pDimmInfo)|| (dimmNum >= MAX_DIMM_NUM)) -+ { -+ DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); -+ return MV_BAD_PARAM; -+ } -+ -+ /* zero dimmInfo structure */ -+ memset(data, 0, SPD_SIZE); -+ -+ /* read the dimm eeprom */ -+ DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); -+ twsiSlave.slaveAddr.address = (dimmNum == 0) ? -+ MV_BOARD_DIMM0_I2C_ADDR : MV_BOARD_DIMM1_I2C_ADDR; -+ twsiSlave.slaveAddr.type = ADDR7_BIT; -+ twsiSlave.validOffset = MV_TRUE; -+ twsiSlave.offset = 0; -+ twsiSlave.moreThen256 = MV_FALSE; -+ -+ if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, &twsiSlave, data, SPD_SIZE) ) -+ { -+ DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum %d \n", dimmNum)); -+ return MV_FAIL; -+ } -+ DB(puts("DRAM: Reading dimm info succeded.\n")); -+ -+ /* calculate SPD checksum */ -+ spdChecksum = 0; -+ -+ for(i = 0 ; i <= 62 ; i++) -+ { -+ spdChecksum += data[i]; -+ } -+ -+ if ((spdChecksum & 0xff) != data[63]) -+ { -+ DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", -+ (MV_U32)(spdChecksum & 0xff), data[63])); -+ } -+ else -+ { -+ DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); -+ } -+ -+ /* copy the SPD content 1:1 into the dimmInfo structure*/ -+ for(i = 0 ; i < SPD_SIZE ; i++) -+ { -+ pDimmInfo->spdRawData[i] = data[i]; -+ DB(mvOsPrintf("SPD-EEPROM Byte %3d = %3x (%3d)\n",i, data[i], data[i])); -+ } -+ -+ DB(mvOsPrintf("DRAM SPD Information:\n")); -+ -+ /* Memory type (DDR / SDRAM) */ -+ switch (data[DIMM_MEM_TYPE]) -+ { -+ case (DIMM_MEM_TYPE_SDRAM): -+ pDimmInfo->memoryType = MEM_TYPE_SDRAM; -+ DB(mvOsPrintf("DRAM Memeory type SDRAM\n")); -+ break; -+ case (DIMM_MEM_TYPE_DDR1): -+ pDimmInfo->memoryType = MEM_TYPE_DDR1; -+ DB(mvOsPrintf("DRAM Memeory type DDR1\n")); -+ break; -+ case (DIMM_MEM_TYPE_DDR2): -+ pDimmInfo->memoryType = MEM_TYPE_DDR2; -+ DB(mvOsPrintf("DRAM Memeory type DDR2\n")); -+ break; -+ default: -+ mvOsPrintf("ERROR: Undefined memory type!\n"); -+ return MV_ERROR; -+ } -+ -+ -+ /* Number Of Row Addresses */ -+ pDimmInfo->numOfRowAddr = data[DIMM_ROW_NUM]; -+ DB(mvOsPrintf("DRAM numOfRowAddr[3] %d\n",pDimmInfo->numOfRowAddr)); -+ -+ /* Number Of Column Addresses */ -+ pDimmInfo->numOfColAddr = data[DIMM_COL_NUM]; -+ DB(mvOsPrintf("DRAM numOfColAddr[4] %d\n",pDimmInfo->numOfColAddr)); -+ -+ /* Number Of Module Banks */ -+ pDimmInfo->numOfModuleBanks = data[DIMM_MODULE_BANK_NUM]; -+ DB(mvOsPrintf("DRAM numOfModuleBanks[5] 0x%x\n", -+ pDimmInfo->numOfModuleBanks)); -+ -+ /* Number of module banks encoded differently for DDR2 */ -+ if (pDimmInfo->memoryType == MEM_TYPE_DDR2) -+ pDimmInfo->numOfModuleBanks = (pDimmInfo->numOfModuleBanks & 0x7)+1; -+ -+ /* Data Width */ -+ pDimmInfo->dataWidth = data[DIMM_DATA_WIDTH]; -+ DB(mvOsPrintf("DRAM dataWidth[6] 0x%x\n", pDimmInfo->dataWidth)); -+ -+ /* Minimum Cycle Time At Max CasLatancy */ -+ pDimmInfo->minCycleTimeAtMaxCasLatPs = cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS]); -+ -+ /* Error Check Type */ -+ pDimmInfo->errorCheckType = data[DIMM_ERR_CHECK_TYPE]; -+ DB(mvOsPrintf("DRAM errorCheckType[11] 0x%x\n", -+ pDimmInfo->errorCheckType)); -+ -+ /* Refresh Interval */ -+ pDimmInfo->refreshInterval = data[DIMM_REFRESH_INTERVAL]; -+ DB(mvOsPrintf("DRAM refreshInterval[12] 0x%x\n", -+ pDimmInfo->refreshInterval)); -+ -+ /* Sdram Width */ -+ pDimmInfo->sdramWidth = data[DIMM_SDRAM_WIDTH]; -+ DB(mvOsPrintf("DRAM sdramWidth[13] 0x%x\n",pDimmInfo->sdramWidth)); -+ -+ /* Error Check Data Width */ -+ pDimmInfo->errorCheckDataWidth = data[DIMM_ERR_CHECK_DATA_WIDTH]; -+ DB(mvOsPrintf("DRAM errorCheckDataWidth[14] 0x%x\n", -+ pDimmInfo->errorCheckDataWidth)); -+ -+ /* Burst Length Supported */ -+ /* SDRAM/DDR1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * -+ *********************************************************/ -+ /* DDR2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * -+ *********************************************************/ -+ -+ pDimmInfo->burstLengthSupported = data[DIMM_BURST_LEN_SUP]; -+ DB(mvOsPrintf("DRAM burstLengthSupported[16] 0x%x\n", -+ pDimmInfo->burstLengthSupported)); -+ -+ /* Number Of Banks On Each Device */ -+ pDimmInfo->numOfBanksOnEachDevice = data[DIMM_DEV_BANK_NUM]; -+ DB(mvOsPrintf("DRAM numOfBanksOnEachDevice[17] 0x%x\n", -+ pDimmInfo->numOfBanksOnEachDevice)); -+ -+ /* Suported Cas Latencies */ -+ -+ /* SDRAM: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * -+ ********************************************************/ -+ -+ /* DDR 1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * -+ *********************************************************/ -+ -+ /* DDR 2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * -+ *********************************************************/ -+ -+ pDimmInfo->suportedCasLatencies = data[DIMM_SUP_CAL]; -+ DB(mvOsPrintf("DRAM suportedCasLatencies[18] 0x%x\n", -+ pDimmInfo->suportedCasLatencies)); -+ -+ /* For DDR2 only, get the DIMM type information */ -+ if (pDimmInfo->memoryType == MEM_TYPE_DDR2) -+ { -+ pDimmInfo->dimmTypeInfo = data[DIMM_DDR2_TYPE_INFORMATION]; -+ DB(mvOsPrintf("DRAM dimmTypeInfo[20] (DDR2) 0x%x\n", -+ pDimmInfo->dimmTypeInfo)); -+ } -+ -+ /* SDRAM Modules Attributes */ -+ pDimmInfo->dimmAttributes = data[DIMM_BUF_ADDR_CONT_IN]; -+ DB(mvOsPrintf("DRAM dimmAttributes[21] 0x%x\n", -+ pDimmInfo->dimmAttributes)); -+ -+ /* Minimum Cycle Time At Max CasLatancy Minus 1*/ -+ pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps = -+ cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS1]); -+ -+ /* Minimum Cycle Time At Max CasLatancy Minus 2*/ -+ pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps = -+ cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS2]); -+ -+ pDimmInfo->minRowPrechargeTime = data[DIMM_MIN_ROW_PRECHARGE_TIME]; -+ DB(mvOsPrintf("DRAM minRowPrechargeTime[27] 0x%x\n", -+ pDimmInfo->minRowPrechargeTime)); -+ pDimmInfo->minRowActiveToRowActive = data[DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE]; -+ DB(mvOsPrintf("DRAM minRowActiveToRowActive[28] 0x%x\n", -+ pDimmInfo->minRowActiveToRowActive)); -+ pDimmInfo->minRasToCasDelay = data[DIMM_MIN_RAS_TO_CAS_DELAY]; -+ DB(mvOsPrintf("DRAM minRasToCasDelay[29] 0x%x\n", -+ pDimmInfo->minRasToCasDelay)); -+ pDimmInfo->minRasPulseWidth = data[DIMM_MIN_RAS_PULSE_WIDTH]; -+ DB(mvOsPrintf("DRAM minRasPulseWidth[30] 0x%x\n", -+ pDimmInfo->minRasPulseWidth)); -+ -+ /* DIMM Bank Density */ -+ pDimmInfo->dimmBankDensity = data[DIMM_BANK_DENSITY]; -+ DB(mvOsPrintf("DRAM dimmBankDensity[31] 0x%x\n", -+ pDimmInfo->dimmBankDensity)); -+ -+ /* Only DDR2 includes Write Recovery Time field. Other SDRAM ignore */ -+ pDimmInfo->minWriteRecoveryTime = data[DIMM_MIN_WRITE_RECOVERY_TIME]; -+ DB(mvOsPrintf("DRAM minWriteRecoveryTime[36] 0x%x\n", -+ pDimmInfo->minWriteRecoveryTime)); -+ -+ /* Only DDR2 includes Internal Write To Read Command Delay field. */ -+ pDimmInfo->minWriteToReadCmdDelay = data[DIMM_MIN_WRITE_TO_READ_CMD_DELAY]; -+ DB(mvOsPrintf("DRAM minWriteToReadCmdDelay[37] 0x%x\n", -+ pDimmInfo->minWriteToReadCmdDelay)); -+ -+ /* Only DDR2 includes Internal Read To Precharge Command Delay field. */ -+ pDimmInfo->minReadToPrechCmdDelay = data[DIMM_MIN_READ_TO_PRECH_CMD_DELAY]; -+ DB(mvOsPrintf("DRAM minReadToPrechCmdDelay[38] 0x%x\n", -+ pDimmInfo->minReadToPrechCmdDelay)); -+ -+ /* Only DDR2 includes Minimum Refresh to Activate/Refresh Command field */ -+ pDimmInfo->minRefreshToActiveCmd = data[DIMM_MIN_REFRESH_TO_ACTIVATE_CMD]; -+ DB(mvOsPrintf("DRAM minRefreshToActiveCmd[42] 0x%x\n", -+ pDimmInfo->minRefreshToActiveCmd)); -+ -+ /* calculating the sdram density. Representing device density from */ -+ /* bit 20 to allow representation of 4GB and above. */ -+ /* For example, if density is 512Mbit 0x20000000, will be represent in */ -+ /* deviceDensity by 0x20000000 >> 16 --> 0x00000200. Another example */ -+ /* is density 8GB 0x200000000 >> 16 --> 0x00002000. */ -+ density = (1 << ((pDimmInfo->numOfRowAddr + pDimmInfo->numOfColAddr) - 20)); -+ pDimmInfo->deviceDensity = density * -+ pDimmInfo->numOfBanksOnEachDevice * -+ pDimmInfo->sdramWidth; -+ DB(mvOsPrintf("DRAM deviceDensity %d\n",pDimmInfo->deviceDensity)); -+ -+ /* Number of devices includeing Error correction */ -+ pDimmInfo->numberOfDevices = (pDimmInfo->dataWidth/pDimmInfo->sdramWidth) * -+ pDimmInfo->numOfModuleBanks; -+ DB(mvOsPrintf("DRAM numberOfDevices %d\n", -+ pDimmInfo->numberOfDevices)); -+ -+ pDimmInfo->size = 0; -+ -+ /* Note that pDimmInfo->size is in MB units */ -+ if (pDimmInfo->memoryType == MEM_TYPE_SDRAM) -+ { -+ if (pDimmInfo->dimmBankDensity & BIT0) -+ pDimmInfo->size += 1024; /* Equal to 1GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT1) -+ pDimmInfo->size += 8; /* Equal to 8MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT2) -+ pDimmInfo->size += 16; /* Equal to 16MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT3) -+ pDimmInfo->size += 32; /* Equal to 32MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT4) -+ pDimmInfo->size += 64; /* Equal to 64MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT5) -+ pDimmInfo->size += 128; /* Equal to 128MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT6) -+ pDimmInfo->size += 256; /* Equal to 256MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT7) -+ pDimmInfo->size += 512; /* Equal to 512MB */ -+ } -+ else if (pDimmInfo->memoryType == MEM_TYPE_DDR1) -+ { -+ if (pDimmInfo->dimmBankDensity & BIT0) -+ pDimmInfo->size += 1024; /* Equal to 1GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT1) -+ pDimmInfo->size += 2048; /* Equal to 2GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT2) -+ pDimmInfo->size += 16; /* Equal to 16MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT3) -+ pDimmInfo->size += 32; /* Equal to 32MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT4) -+ pDimmInfo->size += 64; /* Equal to 64MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT5) -+ pDimmInfo->size += 128; /* Equal to 128MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT6) -+ pDimmInfo->size += 256; /* Equal to 256MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT7) -+ pDimmInfo->size += 512; /* Equal to 512MB */ -+ } -+ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ -+ { -+ if (pDimmInfo->dimmBankDensity & BIT0) -+ pDimmInfo->size += 1024; /* Equal to 1GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT1) -+ pDimmInfo->size += 2048; /* Equal to 2GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT2) -+ pDimmInfo->size += 4096; /* Equal to 4GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT3) -+ pDimmInfo->size += 8192; /* Equal to 8GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT4) -+ pDimmInfo->size += 16384; /* Equal to 16GB */ -+ else if (pDimmInfo->dimmBankDensity & BIT5) -+ pDimmInfo->size += 128; /* Equal to 128MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT6) -+ pDimmInfo->size += 256; /* Equal to 256MB */ -+ else if (pDimmInfo->dimmBankDensity & BIT7) -+ pDimmInfo->size += 512; /* Equal to 512MB */ -+ } -+ -+ pDimmInfo->size *= pDimmInfo->numOfModuleBanks; -+ -+ DB(mvOsPrintf("Dram: dimm size %dMB \n",pDimmInfo->size)); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* dimmSpdPrint - Print the SPD parameters. -+* -+* DESCRIPTION: -+* Print the Dimm SPD parameters. -+* -+* INPUT: -+* pDimmInfo - DIMM information structure. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_VOID dimmSpdPrint(MV_U32 dimmNum) -+{ -+ MV_DIMM_INFO dimmInfo; -+ MV_U32 i, temp = 0; -+ MV_U32 k, maskLeftOfPoint = 0, maskRightOfPoint = 0; -+ MV_U32 rightOfPoint = 0,leftOfPoint = 0, div, time_tmp, shift; -+ MV_U32 busClkPs; -+ MV_U8 trp_clocks=0, trcd_clocks, tras_clocks, trrd_clocks, -+ temp_buf[40], *spdRawData; -+ -+ busClkPs = 1000000000 / (mvBoardSysClkGet() / 100); /* in 10 ps units */ -+ -+ spdRawData = dimmInfo.spdRawData; -+ -+ if(MV_OK != dimmSpdGet(dimmNum, &dimmInfo)) -+ { -+ mvOsOutput("ERROR: Could not read SPD information!\n"); -+ return; -+ } -+ -+ /* find Manufactura of Dimm Module */ -+ mvOsOutput("\nManufacturer's JEDEC ID Code: "); -+ for(i = 0 ; i < DIMM_MODULE_MANU_SIZE ; i++) -+ { -+ mvOsOutput("%x",spdRawData[DIMM_MODULE_MANU_OFFS + i]); -+ } -+ mvOsOutput("\n"); -+ -+ /* Manufacturer's Specific Data */ -+ for(i = 0 ; i < DIMM_MODULE_ID_SIZE ; i++) -+ { -+ temp_buf[i] = spdRawData[DIMM_MODULE_ID_OFFS + i]; -+ } -+ mvOsOutput("Manufacturer's Specific Data: %s\n", temp_buf); -+ -+ /* Module Part Number */ -+ for(i = 0 ; i < DIMM_MODULE_VEN_SIZE ; i++) -+ { -+ temp_buf[i] = spdRawData[DIMM_MODULE_VEN_OFFS + i]; -+ } -+ mvOsOutput("Module Part Number: %s\n", temp_buf); -+ -+ /* Module Serial Number */ -+ for(i = 0; i < sizeof(MV_U32); i++) -+ { -+ temp |= spdRawData[95+i] << 8*i; -+ } -+ mvOsOutput("DIMM Serial No. %ld (%lx)\n", (long)temp, -+ (long)temp); -+ -+ /* find Manufac-Data of Dimm Module */ -+ mvOsOutput("Manufactoring Date: Year 20%d%d/ ww %d%d\n", -+ ((spdRawData[93] & 0xf0) >> 4), (spdRawData[93] & 0xf), -+ ((spdRawData[94] & 0xf0) >> 4), (spdRawData[94] & 0xf)); -+ /* find modul_revision of Dimm Module */ -+ mvOsOutput("Module Revision: %d.%d\n", -+ spdRawData[62]/10, spdRawData[62]%10); -+ -+ /* find manufac_place of Dimm Module */ -+ mvOsOutput("manufac_place: %d\n", spdRawData[72]); -+ -+ /* go over the first 35 I2C data bytes */ -+ for(i = 2 ; i <= 35 ; i++) -+ switch(i) -+ { -+ case 2: /* Memory type (DDR1/2 / SDRAM) */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ mvOsOutput("Dram Type is: SDRAM\n"); -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ mvOsOutput("Dram Type is: SDRAM DDR1\n"); -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) -+ mvOsOutput("Dram Type is: SDRAM DDR2\n"); -+ else -+ mvOsOutput("Dram Type unknown\n"); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 3: /* Number Of Row Addresses */ -+ mvOsOutput("Module Number of row addresses: %d\n", -+ dimmInfo.numOfRowAddr); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 4: /* Number Of Column Addresses */ -+ mvOsOutput("Module Number of col addresses: %d\n", -+ dimmInfo.numOfColAddr); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 5: /* Number Of Module Banks */ -+ mvOsOutput("Number of Banks on Mod.: %d\n", -+ dimmInfo.numOfModuleBanks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 6: /* Data Width */ -+ mvOsOutput("Module Data Width: %d bit\n", -+ dimmInfo.dataWidth); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 8: /* Voltage Interface */ -+ switch(spdRawData[i]) -+ { -+ case 0x0: -+ mvOsOutput("Module is TTL_5V_TOLERANT\n"); -+ break; -+ case 0x1: -+ mvOsOutput("Module is LVTTL\n"); -+ break; -+ case 0x2: -+ mvOsOutput("Module is HSTL_1_5V\n"); -+ break; -+ case 0x3: -+ mvOsOutput("Module is SSTL_3_3V\n"); -+ break; -+ case 0x4: -+ mvOsOutput("Module is SSTL_2_5V\n"); -+ break; -+ case 0x5: -+ if (dimmInfo.memoryType != MEM_TYPE_SDRAM) -+ { -+ mvOsOutput("Module is SSTL_1_8V\n"); -+ break; -+ } -+ default: -+ mvOsOutput("Module is VOLTAGE_UNKNOWN\n"); -+ break; -+ } -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 9: /* Minimum Cycle Time At Max CasLatancy */ -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ rightOfPoint = (spdRawData[i] & 0x0f) * 10; -+ -+ /* DDR2 addition of right of point */ -+ if ((spdRawData[i] & 0x0f) == 0xA) -+ { -+ rightOfPoint = 25; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xB) -+ { -+ rightOfPoint = 33; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xC) -+ { -+ rightOfPoint = 66; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xD) -+ { -+ rightOfPoint = 75; -+ } -+ mvOsOutput("Minimum Cycle Time At Max CL: %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 10: /* Clock To Data Out */ -+ div = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 10:100; -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / div; -+ rightOfPoint = time_tmp % div; -+ mvOsOutput("Clock To Data Out: %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 11: /* Error Check Type */ -+ mvOsOutput("Error Check Type (0=NONE): %d\n", -+ dimmInfo.errorCheckType); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 12: /* Refresh Interval */ -+ mvOsOutput("Refresh Rate: %x\n", -+ dimmInfo.refreshInterval); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 13: /* Sdram Width */ -+ mvOsOutput("Sdram Width: %d bits\n", -+ dimmInfo.sdramWidth); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 14: /* Error Check Data Width */ -+ mvOsOutput("Error Check Data Width: %d bits\n", -+ dimmInfo.errorCheckDataWidth); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 15: /* Minimum Clock Delay is unsupported */ -+ if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || -+ (dimmInfo.memoryType == MEM_TYPE_DDR1)) -+ { -+ mvOsOutput("Minimum Clk Delay back to back: %d\n", -+ spdRawData[i]); -+ } -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 16: /* Burst Length Supported */ -+ /* SDRAM/DDR1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * -+ *********************************************************/ -+ /* DDR2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * -+ *********************************************************/ -+ mvOsOutput("Burst Length Supported: "); -+ if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || -+ (dimmInfo.memoryType == MEM_TYPE_DDR1)) -+ { -+ if (dimmInfo.burstLengthSupported & BIT0) -+ mvOsOutput("1, "); -+ if (dimmInfo.burstLengthSupported & BIT1) -+ mvOsOutput("2, "); -+ } -+ if (dimmInfo.burstLengthSupported & BIT2) -+ mvOsOutput("4, "); -+ if (dimmInfo.burstLengthSupported & BIT3) -+ mvOsOutput("8, "); -+ -+ mvOsOutput(" Bit \n"); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 17: /* Number Of Banks On Each Device */ -+ mvOsOutput("Number Of Banks On Each Chip: %d\n", -+ dimmInfo.numOfBanksOnEachDevice); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 18: /* Suported Cas Latencies */ -+ -+ /* SDRAM: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * -+ ********************************************************/ -+ -+ /* DDR 1: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * -+ *********************************************************/ -+ -+ /* DDR 2: -+ *******-******-******-******-******-******-******-******* -+ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * -+ *******-******-******-******-******-******-******-******* -+ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * -+ *********************************************************/ -+ -+ mvOsOutput("Suported Cas Latencies: (CL) "); -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ for (k = 0; k <=7; k++) -+ { -+ if (dimmInfo.suportedCasLatencies & (1 << k)) -+ mvOsOutput("%d, ", k+1); -+ } -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ { -+ if (dimmInfo.suportedCasLatencies & BIT0) -+ mvOsOutput("1, "); -+ if (dimmInfo.suportedCasLatencies & BIT1) -+ mvOsOutput("1.5, "); -+ if (dimmInfo.suportedCasLatencies & BIT2) -+ mvOsOutput("2, "); -+ if (dimmInfo.suportedCasLatencies & BIT3) -+ mvOsOutput("2.5, "); -+ if (dimmInfo.suportedCasLatencies & BIT4) -+ mvOsOutput("3, "); -+ if (dimmInfo.suportedCasLatencies & BIT5) -+ mvOsOutput("3.5, "); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) -+ { -+ if (dimmInfo.suportedCasLatencies & BIT2) -+ mvOsOutput("2, "); -+ if (dimmInfo.suportedCasLatencies & BIT3) -+ mvOsOutput("3, "); -+ if (dimmInfo.suportedCasLatencies & BIT4) -+ mvOsOutput("4, "); -+ if (dimmInfo.suportedCasLatencies & BIT5) -+ mvOsOutput("5, "); -+ } -+ else -+ mvOsOutput("?.?, "); -+ mvOsOutput("\n"); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 20: /* DDR2 DIMM type info */ -+ if (dimmInfo.memoryType == MEM_TYPE_DDR2) -+ { -+ if (dimmInfo.dimmTypeInfo & (BIT0 | BIT4)) -+ mvOsOutput("Registered DIMM (RDIMM)\n"); -+ else if (dimmInfo.dimmTypeInfo & (BIT1 | BIT5)) -+ mvOsOutput("Unbuffered DIMM (UDIMM)\n"); -+ else -+ mvOsOutput("Unknown DIMM type.\n"); -+ } -+ -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 21: /* SDRAM Modules Attributes */ -+ mvOsOutput("\nModule Attributes (SPD Byte 21): \n"); -+ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ if (dimmInfo.dimmAttributes & BIT0) -+ mvOsOutput(" Buffered Addr/Control Input: Yes\n"); -+ else -+ mvOsOutput(" Buffered Addr/Control Input: No\n"); -+ -+ if (dimmInfo.dimmAttributes & BIT1) -+ mvOsOutput(" Registered Addr/Control Input: Yes\n"); -+ else -+ mvOsOutput(" Registered Addr/Control Input: No\n"); -+ -+ if (dimmInfo.dimmAttributes & BIT2) -+ mvOsOutput(" On-Card PLL (clock): Yes \n"); -+ else -+ mvOsOutput(" On-Card PLL (clock): No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT3) -+ mvOsOutput(" Bufferd DQMB Input: Yes \n"); -+ else -+ mvOsOutput(" Bufferd DQMB Inputs: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT4) -+ mvOsOutput(" Registered DQMB Inputs: Yes \n"); -+ else -+ mvOsOutput(" Registered DQMB Inputs: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT5) -+ mvOsOutput(" Differential Clock Input: Yes \n"); -+ else -+ mvOsOutput(" Differential Clock Input: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT6) -+ mvOsOutput(" redundant Row Addressing: Yes \n"); -+ else -+ mvOsOutput(" redundant Row Addressing: No \n"); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ { -+ if (dimmInfo.dimmAttributes & BIT0) -+ mvOsOutput(" Buffered Addr/Control Input: Yes\n"); -+ else -+ mvOsOutput(" Buffered Addr/Control Input: No\n"); -+ -+ if (dimmInfo.dimmAttributes & BIT1) -+ mvOsOutput(" Registered Addr/Control Input: Yes\n"); -+ else -+ mvOsOutput(" Registered Addr/Control Input: No\n"); -+ -+ if (dimmInfo.dimmAttributes & BIT2) -+ mvOsOutput(" On-Card PLL (clock): Yes \n"); -+ else -+ mvOsOutput(" On-Card PLL (clock): No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT3) -+ mvOsOutput(" FET Switch On-Card Enabled: Yes \n"); -+ else -+ mvOsOutput(" FET Switch On-Card Enabled: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT4) -+ mvOsOutput(" FET Switch External Enabled: Yes \n"); -+ else -+ mvOsOutput(" FET Switch External Enabled: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT5) -+ mvOsOutput(" Differential Clock Input: Yes \n"); -+ else -+ mvOsOutput(" Differential Clock Input: No \n"); -+ } -+ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ -+ { -+ mvOsOutput(" Number of Active Registers on the DIMM: %d\n", -+ (dimmInfo.dimmAttributes & 0x3) + 1); -+ -+ mvOsOutput(" Number of PLLs on the DIMM: %d\n", -+ ((dimmInfo.dimmAttributes) >> 2) & 0x3); -+ -+ if (dimmInfo.dimmAttributes & BIT4) -+ mvOsOutput(" FET Switch External Enabled: Yes \n"); -+ else -+ mvOsOutput(" FET Switch External Enabled: No \n"); -+ -+ if (dimmInfo.dimmAttributes & BIT6) -+ mvOsOutput(" Analysis probe installed: Yes \n"); -+ else -+ mvOsOutput(" Analysis probe installed: No \n"); -+ } -+ -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 22: /* Suported AutoPreCharge */ -+ mvOsOutput("\nModul Attributes (SPD Byte 22): \n"); -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ if ( spdRawData[i] & BIT0 ) -+ mvOsOutput(" Early Ras Precharge: Yes \n"); -+ else -+ mvOsOutput(" Early Ras Precharge: No \n"); -+ -+ if ( spdRawData[i] & BIT1 ) -+ mvOsOutput(" AutoPreCharge: Yes \n"); -+ else -+ mvOsOutput(" AutoPreCharge: No \n"); -+ -+ if ( spdRawData[i] & BIT2 ) -+ mvOsOutput(" Precharge All: Yes \n"); -+ else -+ mvOsOutput(" Precharge All: No \n"); -+ -+ if ( spdRawData[i] & BIT3 ) -+ mvOsOutput(" Write 1/ReadBurst: Yes \n"); -+ else -+ mvOsOutput(" Write 1/ReadBurst: No \n"); -+ -+ if ( spdRawData[i] & BIT4 ) -+ mvOsOutput(" lower VCC tolerance: 5%%\n"); -+ else -+ mvOsOutput(" lower VCC tolerance: 10%%\n"); -+ -+ if ( spdRawData[i] & BIT5 ) -+ mvOsOutput(" upper VCC tolerance: 5%%\n"); -+ else -+ mvOsOutput(" upper VCC tolerance: 10%%\n"); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ { -+ if ( spdRawData[i] & BIT0 ) -+ mvOsOutput(" Supports Weak Driver: Yes \n"); -+ else -+ mvOsOutput(" Supports Weak Driver: No \n"); -+ -+ if ( !(spdRawData[i] & BIT4) ) -+ mvOsOutput(" lower VCC tolerance: 0.2V\n"); -+ -+ if ( !(spdRawData[i] & BIT5) ) -+ mvOsOutput(" upper VCC tolerance: 0.2V\n"); -+ -+ if ( spdRawData[i] & BIT6 ) -+ mvOsOutput(" Concurrent Auto Preharge: Yes \n"); -+ else -+ mvOsOutput(" Concurrent Auto Preharge: No \n"); -+ -+ if ( spdRawData[i] & BIT7 ) -+ mvOsOutput(" Supports Fast AP: Yes \n"); -+ else -+ mvOsOutput(" Supports Fast AP: No \n"); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) -+ { -+ if ( spdRawData[i] & BIT0 ) -+ mvOsOutput(" Supports Weak Driver: Yes \n"); -+ else -+ mvOsOutput(" Supports Weak Driver: No \n"); -+ } -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 23: -+ /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */ -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ rightOfPoint = (spdRawData[i] & 0x0f) * 10; -+ -+ /* DDR2 addition of right of point */ -+ if ((spdRawData[i] & 0x0f) == 0xA) -+ { -+ rightOfPoint = 25; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xB) -+ { -+ rightOfPoint = 33; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xC) -+ { -+ rightOfPoint = 66; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xD) -+ { -+ rightOfPoint = 75; -+ } -+ -+ mvOsOutput("Minimum Cycle Time At 2nd highest CasLatancy" -+ "(0 = Not supported): %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint ); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 24: /* Clock To Data Out 2nd highest Cas Latency Value*/ -+ div = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? 10:100; -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / div; -+ rightOfPoint = time_tmp % div; -+ mvOsOutput("Clock To Data Out (2nd CL value): %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 25: -+ /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ leftOfPoint = (spdRawData[i] & 0xfc) >> 2; -+ rightOfPoint = (spdRawData[i] & 0x3) * 25; -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ rightOfPoint = (spdRawData[i] & 0x0f) * 10; -+ -+ /* DDR2 addition of right of point */ -+ if ((spdRawData[i] & 0x0f) == 0xA) -+ { -+ rightOfPoint = 25; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xB) -+ { -+ rightOfPoint = 33; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xC) -+ { -+ rightOfPoint = 66; -+ } -+ if ((spdRawData[i] & 0x0f) == 0xD) -+ { -+ rightOfPoint = 75; -+ } -+ } -+ mvOsOutput("Minimum Cycle Time At 3rd highest CasLatancy" -+ "(0 = Not supported): %d.%d [ns]\n", -+ leftOfPoint, rightOfPoint ); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 26: /* Clock To Data Out 3rd highest Cas Latency Value*/ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ leftOfPoint = (spdRawData[i] & 0xfc) >> 2; -+ rightOfPoint = (spdRawData[i] & 0x3) * 25; -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = 0; -+ rightOfPoint = time_tmp; -+ } -+ mvOsOutput("Clock To Data Out (3rd CL value): %d.%2d[ns]\n", -+ leftOfPoint, rightOfPoint ); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 27: /* Minimum Row Precharge Time */ -+ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; -+ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0xff : 0xfc; -+ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0x00 : 0x03; -+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); -+ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; -+ temp = ((leftOfPoint*100) + rightOfPoint);/* in 10ps Intervals*/ -+ trp_clocks = (temp + (busClkPs-1)) / busClkPs; -+ mvOsOutput("Minimum Row Precharge Time [ns]: %d.%d = " -+ "in Clk cycles %d\n", -+ leftOfPoint, rightOfPoint, trp_clocks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 28: /* Minimum Row Active to Row Active Time */ -+ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; -+ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0xff : 0xfc; -+ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0x00 : 0x03; -+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); -+ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; -+ temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ -+ trrd_clocks = (temp + (busClkPs-1)) / busClkPs; -+ mvOsOutput("Minimum Row Active -To- Row Active Delay [ns]: " -+ "%d.%d = in Clk cycles %d\n", -+ leftOfPoint, rightOfPoint, trp_clocks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 29: /* Minimum Ras-To-Cas Delay */ -+ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; -+ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0xff : 0xfc; -+ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? -+ 0x00 : 0x03; -+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); -+ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; -+ temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ -+ trcd_clocks = (temp + (busClkPs-1) )/ busClkPs; -+ mvOsOutput("Minimum Ras-To-Cas Delay [ns]: %d.%d = " -+ "in Clk cycles %d\n", -+ leftOfPoint, rightOfPoint, trp_clocks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 30: /* Minimum Ras Pulse Width */ -+ tras_clocks = (cas2ps(spdRawData[i])+(busClkPs-1)) / busClkPs; -+ mvOsOutput("Minimum Ras Pulse Width [ns]: %d = " -+ "in Clk cycles %d\n", spdRawData[i], tras_clocks); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 31: /* Module Bank Density */ -+ mvOsOutput("Module Bank Density (more than 1= Multisize-Module):"); -+ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ if (dimmInfo.dimmBankDensity & BIT0) -+ mvOsOutput("1GB, "); -+ if (dimmInfo.dimmBankDensity & BIT1) -+ mvOsOutput("8MB, "); -+ if (dimmInfo.dimmBankDensity & BIT2) -+ mvOsOutput("16MB, "); -+ if (dimmInfo.dimmBankDensity & BIT3) -+ mvOsOutput("32MB, "); -+ if (dimmInfo.dimmBankDensity & BIT4) -+ mvOsOutput("64MB, "); -+ if (dimmInfo.dimmBankDensity & BIT5) -+ mvOsOutput("128MB, "); -+ if (dimmInfo.dimmBankDensity & BIT6) -+ mvOsOutput("256MB, "); -+ if (dimmInfo.dimmBankDensity & BIT7) -+ mvOsOutput("512MB, "); -+ } -+ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) -+ { -+ if (dimmInfo.dimmBankDensity & BIT0) -+ mvOsOutput("1GB, "); -+ if (dimmInfo.dimmBankDensity & BIT1) -+ mvOsOutput("2GB, "); -+ if (dimmInfo.dimmBankDensity & BIT2) -+ mvOsOutput("16MB, "); -+ if (dimmInfo.dimmBankDensity & BIT3) -+ mvOsOutput("32MB, "); -+ if (dimmInfo.dimmBankDensity & BIT4) -+ mvOsOutput("64MB, "); -+ if (dimmInfo.dimmBankDensity & BIT5) -+ mvOsOutput("128MB, "); -+ if (dimmInfo.dimmBankDensity & BIT6) -+ mvOsOutput("256MB, "); -+ if (dimmInfo.dimmBankDensity & BIT7) -+ mvOsOutput("512MB, "); -+ } -+ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ -+ { -+ if (dimmInfo.dimmBankDensity & BIT0) -+ mvOsOutput("1GB, "); -+ if (dimmInfo.dimmBankDensity & BIT1) -+ mvOsOutput("2GB, "); -+ if (dimmInfo.dimmBankDensity & BIT2) -+ mvOsOutput("4GB, "); -+ if (dimmInfo.dimmBankDensity & BIT3) -+ mvOsOutput("8GB, "); -+ if (dimmInfo.dimmBankDensity & BIT4) -+ mvOsOutput("16GB, "); -+ if (dimmInfo.dimmBankDensity & BIT5) -+ mvOsOutput("128MB, "); -+ if (dimmInfo.dimmBankDensity & BIT6) -+ mvOsOutput("256MB, "); -+ if (dimmInfo.dimmBankDensity & BIT7) -+ mvOsOutput("512MB, "); -+ } -+ mvOsOutput("\n"); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 32: /* Address And Command Setup Time (measured in ns/1000) */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ rightOfPoint = (spdRawData[i] & 0x0f); -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ if(leftOfPoint > 7) -+ { -+ leftOfPoint *= -1; -+ } -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / 100; -+ rightOfPoint = time_tmp % 100; -+ } -+ mvOsOutput("Address And Command Setup Time [ns]: %d.%d\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 33: /* Address And Command Hold Time */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ rightOfPoint = (spdRawData[i] & 0x0f); -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ if(leftOfPoint > 7) -+ { -+ leftOfPoint *= -1; -+ } -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / 100; -+ rightOfPoint = time_tmp % 100; -+ } -+ mvOsOutput("Address And Command Hold Time [ns]: %d.%d\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 34: /* Data Input Setup Time */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ rightOfPoint = (spdRawData[i] & 0x0f); -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ if(leftOfPoint > 7) -+ { -+ leftOfPoint *= -1; -+ } -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / 100; -+ rightOfPoint = time_tmp % 100; -+ } -+ mvOsOutput("Data Input Setup Time [ns]: %d.%d\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 35: /* Data Input Hold Time */ -+ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) -+ { -+ rightOfPoint = (spdRawData[i] & 0x0f); -+ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; -+ if(leftOfPoint > 7) -+ { -+ leftOfPoint *= -1; -+ } -+ } -+ else /* DDR1 or DDR2 */ -+ { -+ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + -+ ((spdRawData[i] & 0x0f)); -+ leftOfPoint = time_tmp / 100; -+ rightOfPoint = time_tmp % 100; -+ } -+ mvOsOutput("Data Input Hold Time [ns]: %d.%d\n\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ -+ case 36: /* Relevant for DDR2 only: Write Recovery Time */ -+ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> 2); -+ rightOfPoint = (spdRawData[i] & maskRightOfPoint) * 25; -+ mvOsOutput("Write Recovery Time [ns]: %d.%d\n", -+ leftOfPoint, rightOfPoint); -+ break; -+/*----------------------------------------------------------------------------*/ -+ } -+ -+} -+ -+ -+/* -+ * translate ns.ns/10 coding of SPD timing values -+ * into ps unit values -+ */ -+/******************************************************************************* -+* cas2ps - Translate x.y ns parameter to pico-seconds values -+* -+* DESCRIPTION: -+* This function translates x.y nano seconds to its value in pico seconds. -+* For example 3.75ns will return 3750. -+* -+* INPUT: -+* spd_byte - DIMM SPD byte. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* value in pico seconds. -+* -+*******************************************************************************/ -+static MV_U32 cas2ps(MV_U8 spd_byte) -+{ -+ MV_U32 ns, ns10; -+ -+ /* isolate upper nibble */ -+ ns = (spd_byte >> 4) & 0x0F; -+ /* isolate lower nibble */ -+ ns10 = (spd_byte & 0x0F); -+ -+ if( ns10 < 10 ) { -+ ns10 *= 10; -+ } -+ else if( ns10 == 10 ) -+ ns10 = 25; -+ else if( ns10 == 11 ) -+ ns10 = 33; -+ else if( ns10 == 12 ) -+ ns10 = 66; -+ else if( ns10 == 13 ) -+ ns10 = 75; -+ else -+ { -+ mvOsOutput("cas2ps Err. unsupported cycle time.\n"); -+ } -+ -+ return (ns*1000 + ns10*10); -+} -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,192 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvDram -+#define __INCmvDram -+ -+#include "ddr2/mvDramIf.h" -+#include "twsi/mvTwsi.h" -+ -+#define MAX_DIMM_NUM 2 -+#define SPD_SIZE 128 -+ -+/* Dimm spd offsets */ -+#define DIMM_MEM_TYPE 2 -+#define DIMM_ROW_NUM 3 -+#define DIMM_COL_NUM 4 -+#define DIMM_MODULE_BANK_NUM 5 -+#define DIMM_DATA_WIDTH 6 -+#define DIMM_VOLT_IF 8 -+#define DIMM_MIN_CC_AT_MAX_CAS 9 -+#define DIMM_ERR_CHECK_TYPE 11 -+#define DIMM_REFRESH_INTERVAL 12 -+#define DIMM_SDRAM_WIDTH 13 -+#define DIMM_ERR_CHECK_DATA_WIDTH 14 -+#define DIMM_MIN_CLK_DEL 15 -+#define DIMM_BURST_LEN_SUP 16 -+#define DIMM_DEV_BANK_NUM 17 -+#define DIMM_SUP_CAL 18 -+#define DIMM_DDR2_TYPE_INFORMATION 20 /* DDR2 only */ -+#define DIMM_BUF_ADDR_CONT_IN 21 -+#define DIMM_MIN_CC_AT_MAX_CAS_MINUS1 23 -+#define DIMM_MIN_CC_AT_MAX_CAS_MINUS2 25 -+#define DIMM_MIN_ROW_PRECHARGE_TIME 27 -+#define DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE 28 -+#define DIMM_MIN_RAS_TO_CAS_DELAY 29 -+#define DIMM_MIN_RAS_PULSE_WIDTH 30 -+#define DIMM_BANK_DENSITY 31 -+#define DIMM_MIN_WRITE_RECOVERY_TIME 36 -+#define DIMM_MIN_WRITE_TO_READ_CMD_DELAY 37 -+#define DIMM_MIN_READ_TO_PRECH_CMD_DELAY 38 -+#define DIMM_MIN_REFRESH_TO_ACTIVATE_CMD 42 -+#define DIMM_SPD_VERSION 62 -+ -+/* Dimm Memory Type values */ -+#define DIMM_MEM_TYPE_SDRAM 0x4 -+#define DIMM_MEM_TYPE_DDR1 0x7 -+#define DIMM_MEM_TYPE_DDR2 0x8 -+ -+#define DIMM_MODULE_MANU_OFFS 64 -+#define DIMM_MODULE_MANU_SIZE 8 -+#define DIMM_MODULE_VEN_OFFS 73 -+#define DIMM_MODULE_VEN_SIZE 25 -+#define DIMM_MODULE_ID_OFFS 99 -+#define DIMM_MODULE_ID_SIZE 18 -+ -+/* enumeration for voltage levels. */ -+typedef enum _mvDimmVoltageIf -+{ -+ TTL_5V_TOLERANT, -+ LVTTL, -+ HSTL_1_5V, -+ SSTL_3_3V, -+ SSTL_2_5V, -+ VOLTAGE_UNKNOWN, -+} MV_DIMM_VOLTAGE_IF; -+ -+ -+/* enumaration for SDRAM CAS Latencies. */ -+typedef enum _mvDimmSdramCas -+{ -+ SD_CL_1 =1, -+ SD_CL_2, -+ SD_CL_3, -+ SD_CL_4, -+ SD_CL_5, -+ SD_CL_6, -+ SD_CL_7, -+ SD_FAULT -+}MV_DIMM_SDRAM_CAS; -+ -+ -+/* DIMM information structure */ -+typedef struct _mvDimmInfo -+{ -+ MV_MEMORY_TYPE memoryType; /* DDR or SDRAM */ -+ -+ MV_U8 spdRawData[SPD_SIZE]; /* Content of SPD-EEPROM copied 1:1 */ -+ -+ /* DIMM dimensions */ -+ MV_U32 numOfRowAddr; -+ MV_U32 numOfColAddr; -+ MV_U32 numOfModuleBanks; -+ MV_U32 dataWidth; -+ MV_U32 errorCheckType; /* ECC , PARITY..*/ -+ MV_U32 sdramWidth; /* 4,8,16 or 32 */ -+ MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ -+ MV_U32 burstLengthSupported; -+ MV_U32 numOfBanksOnEachDevice; -+ MV_U32 suportedCasLatencies; -+ MV_U32 refreshInterval; -+ MV_U32 dimmBankDensity; -+ MV_U32 dimmTypeInfo; /* DDR2 only */ -+ MV_U32 dimmAttributes; -+ -+ /* DIMM timing parameters */ -+ MV_U32 minCycleTimeAtMaxCasLatPs; -+ MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; -+ MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; -+ MV_U32 minRowPrechargeTime; -+ MV_U32 minRowActiveToRowActive; -+ MV_U32 minRasToCasDelay; -+ MV_U32 minRasPulseWidth; -+ MV_U32 minWriteRecoveryTime; /* DDR2 only */ -+ MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ -+ MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ -+ MV_U32 minRefreshToActiveCmd; /* DDR2 only */ -+ -+ /* Parameters calculated from the extracted DIMM information */ -+ MV_U32 size; /* 16,64,128,256 or 512 MByte in MB units */ -+ MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit in MB units */ -+ MV_U32 numberOfDevices; -+ -+} MV_DIMM_INFO; -+ -+ -+MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo); -+MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo); -+MV_VOID dimmSpdPrint(MV_U32 dimmNum); -+MV_STATUS dimmSpdCpy(MV_VOID); -+ -+#endif /* __INCmvDram */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEth.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEth.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEth.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEth.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,2952 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+/******************************************************************************* -+* mvEth.c - Marvell's Gigabit Ethernet controller low level driver -+* -+* DESCRIPTION: -+* This file introduce OS independent APIs to Marvell's Gigabit Ethernet -+* controller. This Gigabit Ethernet Controller driver API controls -+* 1) Operations (i.e. port Init, Finish, Up, Down, PhyReset etc'). -+* 2) Data flow (i.e. port Send, Receive etc'). -+* 3) MAC Filtering functions (ethSetMcastAddr, ethSetRxFilterMode, etc.) -+* 4) MIB counters support (ethReadMibCounter) -+* 5) Debug functions (ethPortRegs, ethPortCounters, ethPortQueues, etc.) -+* Each Gigabit Ethernet port is controlled via ETH_PORT_CTRL struct. -+* This struct includes configuration information as well as driver -+* internal data needed for its operations. -+* -+* Supported Features: -+* - OS independent. All required OS services are implemented via external -+* OS dependent components (like osLayer or ethOsg) -+* - The user is free from Rx/Tx queue managing. -+* - Simple Gigabit Ethernet port operation API. -+* - Simple Gigabit Ethernet port data flow API. -+* - Data flow and operation API support per queue functionality. -+* - Support cached descriptors for better performance. -+* - PHY access and control API. -+* - Port Configuration API. -+* - Full control over Special and Other Multicast MAC tables. -+* -+*******************************************************************************/ -+/* includes */ -+#include "mvTypes.h" -+#include "mv802_3.h" -+#include "mvDebug.h" -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "eth-phy/mvEthPhy.h" -+#include "eth/mvEth.h" -+#include "eth/gbe/mvEthGbe.h" -+#include "cpu/mvCpu.h" -+ -+#ifdef INCLUDE_SYNC_BARR -+#include "sys/mvCpuIf.h" -+#endif -+ -+#ifdef MV_RT_DEBUG -+# define ETH_DEBUG -+#endif -+ -+ -+/* locals */ -+MV_BOOL ethDescInSram; -+MV_BOOL ethDescSwCoher; -+ -+/* This array holds the control structure of each port */ -+ETH_PORT_CTRL* ethPortCtrl[MV_ETH_MAX_PORTS]; -+ -+/* Ethernet Port Local routines */ -+ -+static void ethInitRxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue); -+ -+static void ethInitTxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue); -+ -+static void ethSetUcastTable(int portNo, int queue); -+ -+static MV_BOOL ethSetUcastAddr (int ethPortNum, MV_U8 lastNibble, int queue); -+static MV_BOOL ethSetSpecialMcastAddr(int ethPortNum, MV_U8 lastByte, int queue); -+static MV_BOOL ethSetOtherMcastAddr(int ethPortNum, MV_U8 crc8, int queue); -+ -+static void ethFreeDescrMemory(ETH_PORT_CTRL* pEthPortCtrl, MV_BUF_INFO* pDescBuf); -+static MV_U8* ethAllocDescrMemory(ETH_PORT_CTRL* pEthPortCtrl, int size, -+ MV_ULONG* pPhysAddr, MV_U32 *memHandle); -+ -+static MV_U32 mvEthMruGet(MV_U32 maxRxPktSize); -+ -+static void mvEthPortSgmiiConfig(int port); -+ -+ -+ -+/******************************************************************************/ -+/* EthDrv Initialization functions */ -+/******************************************************************************/ -+ -+/******************************************************************************* -+* mvEthHalInit - Initialize the Giga Ethernet unit -+* -+* DESCRIPTION: -+* This function initialize the Giga Ethernet unit. -+* 1) Configure Address decode windows of the unit -+* 2) Set registers to HW default values. -+* 3) Clear and Disable interrupts -+* -+* INPUT: NONE -+* -+* RETURN: NONE -+* -+* NOTE: this function is called once in the boot process. -+*******************************************************************************/ -+void mvEthHalInit(void) -+{ -+ int port; -+ -+ /* Init static data structures */ -+ for (port=0; port 0) -+ { -+ isSram = MV_TRUE; -+ #if (INTEG_SRAM_COHER == MV_CACHE_COHER_SW) -+ isSwCoher = MV_TRUE; -+ #else -+ isSwCoher = MV_FALSE; -+ #endif -+ } -+#endif /* ETH_DESCR_IN_SRAM */ -+ -+ if(pIsSram != NULL) -+ *pIsSram = isSram; -+ -+ if(pIsSwCoher != NULL) -+ *pIsSwCoher = isSwCoher; -+} -+ -+ -+ -+/******************************************************************************/ -+/* Port Initialization functions */ -+/******************************************************************************/ -+ -+/******************************************************************************* -+* mvEthPortInit - Initialize the Ethernet port driver -+* -+* DESCRIPTION: -+* This function initialize the ethernet port. -+* 1) Allocate and initialize internal port Control structure. -+* 2) Create RX and TX descriptor rings for default RX and TX queues -+* 3) Disable RX and TX operations, clear cause registers and -+* mask all interrupts. -+* 4) Set all registers to default values and clean all MAC tables. -+* -+* INPUT: -+* int portNo - Ethernet port number -+* ETH_PORT_INIT *pEthPortInit - Ethernet port init structure -+* -+* RETURN: -+* void* - ethernet port handler, that should be passed to the most other -+* functions dealing with this port. -+* -+* NOTE: This function is called once per port when loading the eth module. -+*******************************************************************************/ -+void* mvEthPortInit(int portNo, MV_ETH_PORT_INIT *pEthPortInit) -+{ -+ int queue, descSize; -+ ETH_PORT_CTRL* pPortCtrl; -+ -+ /* Check validity of parameters */ -+ if( (portNo >= (int)mvCtrlEthMaxPortGet()) || -+ (pEthPortInit->rxDefQ >= MV_ETH_RX_Q_NUM) || -+ (pEthPortInit->maxRxPktSize < 1518) ) -+ { -+ mvOsPrintf("EthPort #%d: Bad initialization parameters\n", portNo); -+ return NULL; -+ } -+ if( (pEthPortInit->rxDescrNum[pEthPortInit->rxDefQ]) == 0) -+ { -+ mvOsPrintf("EthPort #%d: rxDefQ (%d) must be created\n", -+ portNo, pEthPortInit->rxDefQ); -+ return NULL; -+ } -+ -+ pPortCtrl = (ETH_PORT_CTRL*)mvOsMalloc( sizeof(ETH_PORT_CTRL) ); -+ if(pPortCtrl == NULL) -+ { -+ mvOsPrintf("EthDrv: Can't allocate %dB for port #%d control structure!\n", -+ (int)sizeof(ETH_PORT_CTRL), portNo); -+ return NULL; -+ } -+ -+ memset(pPortCtrl, 0, sizeof(ETH_PORT_CTRL) ); -+ ethPortCtrl[portNo] = pPortCtrl; -+ -+ pPortCtrl->portState = MV_UNDEFINED_STATE; -+ -+ pPortCtrl->portNo = portNo; -+ -+ pPortCtrl->osHandle = pEthPortInit->osHandle; -+ -+ /* Copy Configuration parameters */ -+ pPortCtrl->portConfig.maxRxPktSize = pEthPortInit->maxRxPktSize; -+ pPortCtrl->portConfig.rxDefQ = pEthPortInit->rxDefQ; -+ pPortCtrl->portConfig.ejpMode = 0; -+ -+ for( queue=0; queuerxQueueConfig[queue].descrNum = pEthPortInit->rxDescrNum[queue]; -+ } -+ for( queue=0; queuetxQueueConfig[queue].descrNum = pEthPortInit->txDescrNum[queue]; -+ } -+ -+ mvEthPortDisable(pPortCtrl); -+ -+ /* Set the board information regarding PHY address */ -+ mvEthPhyAddrSet(pPortCtrl, mvBoardPhyAddrGet(portNo) ); -+ -+ /* Create all requested RX queues */ -+ for(queue=0; queuerxQueueConfig[queue].descrNum == 0) -+ continue; -+ -+ /* Allocate memory for RX descriptors */ -+ descSize = ((pPortCtrl->rxQueueConfig[queue].descrNum * ETH_RX_DESC_ALIGNED_SIZE) + -+ CPU_D_CACHE_LINE_SIZE); -+ -+ pPortCtrl->rxQueue[queue].descBuf.bufVirtPtr = -+ ethAllocDescrMemory(pPortCtrl, descSize, -+ &pPortCtrl->rxQueue[queue].descBuf.bufPhysAddr, -+ &pPortCtrl->rxQueue[queue].descBuf.memHandle); -+ pPortCtrl->rxQueue[queue].descBuf.bufSize = descSize; -+ if(pPortCtrl->rxQueue[queue].descBuf.bufVirtPtr == NULL) -+ { -+ mvOsPrintf("EthPort #%d, rxQ=%d: Can't allocate %d bytes in %s for %d RX descr\n", -+ pPortCtrl->portNo, queue, descSize, -+ ethDescInSram ? "SRAM" : "DRAM", -+ pPortCtrl->rxQueueConfig[queue].descrNum); -+ return NULL; -+ } -+ -+ ethInitRxDescRing(pPortCtrl, queue); -+ } -+ /* Create TX queues */ -+ for(queue=0; queuetxQueueConfig[queue].descrNum == 0) -+ continue; -+ -+ /* Allocate memory for TX descriptors */ -+ descSize = ((pPortCtrl->txQueueConfig[queue].descrNum * ETH_TX_DESC_ALIGNED_SIZE) + -+ CPU_D_CACHE_LINE_SIZE); -+ -+ pPortCtrl->txQueue[queue].descBuf.bufVirtPtr = -+ ethAllocDescrMemory(pPortCtrl, descSize, -+ &pPortCtrl->txQueue[queue].descBuf.bufPhysAddr, -+ &pPortCtrl->txQueue[queue].descBuf.memHandle); -+ pPortCtrl->txQueue[queue].descBuf.bufSize = descSize; -+ if(pPortCtrl->txQueue[queue].descBuf.bufVirtPtr == NULL) -+ { -+ mvOsPrintf("EthPort #%d, txQ=%d: Can't allocate %d bytes in %s for %d TX descr\n", -+ pPortCtrl->portNo, queue, descSize, ethDescInSram ? "SRAM" : "DRAM", -+ pPortCtrl->txQueueConfig[queue].descrNum); -+ return NULL; -+ } -+ -+ ethInitTxDescRing(pPortCtrl, queue); -+ } -+ mvEthDefaultsSet(pPortCtrl); -+ -+ pPortCtrl->portState = MV_IDLE; -+ return pPortCtrl; -+} -+ -+/******************************************************************************* -+* ethPortFinish - Finish the Ethernet port driver -+* -+* DESCRIPTION: -+* This function finish the ethernet port. -+* 1) Down ethernet port if needed. -+* 2) Delete RX and TX descriptor rings for all created RX and TX queues -+* 3) Free internal port Control structure. -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet port handler -+* -+* RETURN: NONE. -+* -+*******************************************************************************/ -+void mvEthPortFinish(void* pPortHndl) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ int queue, portNo = pPortCtrl->portNo; -+ -+ if(pPortCtrl->portState == MV_ACTIVE) -+ { -+ mvOsPrintf("ethPort #%d: Warning !!! Finish port in Active state\n", -+ portNo); -+ mvEthPortDisable(pPortHndl); -+ } -+ -+ /* Free all allocated RX queues */ -+ for(queue=0; queuerxQueue[queue].descBuf); -+ } -+ -+ /* Free all allocated TX queues */ -+ for(queue=0; queuetxQueue[queue].descBuf); -+ } -+ -+ /* Free port control structure */ -+ mvOsFree(pPortCtrl); -+ -+ ethPortCtrl[portNo] = NULL; -+} -+ -+/******************************************************************************* -+* mvEthDefaultsSet - Set defaults to the ethernet port -+* -+* DESCRIPTION: -+* This function set default values to the ethernet port. -+* 1) Clear Cause registers and Mask all interrupts -+* 2) Clear all MAC tables -+* 3) Set defaults to all registers -+* 4) Reset all created RX and TX descriptors ring -+* 5) Reset PHY -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet port handler -+* -+* RETURN: MV_STATUS -+* MV_OK - Success, Others - Failure -+* NOTE: -+* This function update all the port configuration except those set -+* Initialy by the OsGlue by MV_ETH_PORT_INIT. -+* This function can be called after portDown to return the port setting -+* to defaults. -+*******************************************************************************/ -+MV_STATUS mvEthDefaultsSet(void* pPortHndl) -+{ -+ int ethPortNo, queue; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ MV_U32 txPrio; -+ MV_U32 portCfgReg, portCfgExtReg, portSerialCtrlReg, portSerialCtrl1Reg, portSdmaCfgReg; -+ MV_BOARD_MAC_SPEED boardMacCfg; -+ -+ ethPortNo = pPortCtrl->portNo; -+ -+ /* Clear Cause registers */ -+ MV_REG_WRITE(ETH_INTR_CAUSE_REG(ethPortNo),0); -+ MV_REG_WRITE(ETH_INTR_CAUSE_EXT_REG(ethPortNo),0); -+ -+ /* Mask all interrupts */ -+ MV_REG_WRITE(ETH_INTR_MASK_REG(ethPortNo),0); -+ MV_REG_WRITE(ETH_INTR_MASK_EXT_REG(ethPortNo),0); -+ -+ portCfgReg = PORT_CONFIG_VALUE; -+ portCfgExtReg = PORT_CONFIG_EXTEND_VALUE; -+ -+ boardMacCfg = mvBoardMacSpeedGet(ethPortNo); -+ -+ if(boardMacCfg == BOARD_MAC_SPEED_100M) -+ { -+ portSerialCtrlReg = PORT_SERIAL_CONTROL_100MB_FORCE_VALUE; -+ } -+ else if(boardMacCfg == BOARD_MAC_SPEED_1000M) -+ { -+ portSerialCtrlReg = PORT_SERIAL_CONTROL_1000MB_FORCE_VALUE; -+ } -+ else -+ { -+ portSerialCtrlReg = PORT_SERIAL_CONTROL_VALUE; -+ } -+ -+ /* build PORT_SDMA_CONFIG_REG */ -+ portSdmaCfgReg = ETH_TX_INTR_COAL_MASK(0); -+ portSdmaCfgReg |= ETH_TX_BURST_SIZE_MASK(ETH_BURST_SIZE_16_64BIT_VALUE); -+ -+#if ( (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WB) || \ -+ (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WT) ) -+ /* some devices have restricted RX burst size when using HW coherency */ -+ portSdmaCfgReg |= ETH_RX_BURST_SIZE_MASK(ETH_BURST_SIZE_4_64BIT_VALUE); -+#else -+ portSdmaCfgReg |= ETH_RX_BURST_SIZE_MASK(ETH_BURST_SIZE_16_64BIT_VALUE); -+#endif -+ -+#if defined(MV_CPU_BE) -+ /* big endian */ -+# if defined(MV_ARM) -+ portSdmaCfgReg |= (ETH_RX_NO_DATA_SWAP_MASK | -+ ETH_TX_NO_DATA_SWAP_MASK | -+ ETH_DESC_SWAP_MASK); -+# elif defined(MV_PPC) -+ portSdmaCfgReg |= (ETH_RX_DATA_SWAP_MASK | -+ ETH_TX_DATA_SWAP_MASK | -+ ETH_NO_DESC_SWAP_MASK); -+# else -+# error "Giga Ethernet Swap policy is not defined for the CPU_ARCH" -+# endif /* MV_ARM / MV_PPC */ -+ -+#else /* MV_CPU_LE */ -+ /* little endian */ -+ portSdmaCfgReg |= (ETH_RX_NO_DATA_SWAP_MASK | -+ ETH_TX_NO_DATA_SWAP_MASK | -+ ETH_NO_DESC_SWAP_MASK); -+#endif /* MV_CPU_BE / MV_CPU_LE */ -+ -+ pPortCtrl->portRxQueueCmdReg = 0; -+ pPortCtrl->portTxQueueCmdReg = 0; -+ -+#if (MV_ETH_VERSION >= 4) -+ if(pPortCtrl->portConfig.ejpMode == MV_TRUE) -+ { -+ MV_REG_WRITE(ETH_TXQ_CMD_1_REG(ethPortNo), ETH_TX_EJP_ENABLE_MASK); -+ } -+ else -+ { -+ MV_REG_WRITE(ETH_TXQ_CMD_1_REG(ethPortNo), 0) -+ } -+#endif /* (MV_ETH_VERSION >= 4) */ -+ -+ ethSetUcastTable(ethPortNo, -1); -+ mvEthSetSpecialMcastTable(ethPortNo, -1); -+ mvEthSetOtherMcastTable(ethPortNo, -1); -+ -+ portSerialCtrlReg &= ~ETH_MAX_RX_PACKET_SIZE_MASK; -+ -+ portSerialCtrlReg |= mvEthMruGet(pPortCtrl->portConfig.maxRxPktSize); -+ -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNo), portSerialCtrlReg); -+ -+ /* Update value of PortConfig register accordingly with all RxQueue types */ -+ pPortCtrl->portConfig.rxArpQ = pPortCtrl->portConfig.rxDefQ; -+ pPortCtrl->portConfig.rxBpduQ = pPortCtrl->portConfig.rxDefQ; -+ pPortCtrl->portConfig.rxTcpQ = pPortCtrl->portConfig.rxDefQ; -+ pPortCtrl->portConfig.rxUdpQ = pPortCtrl->portConfig.rxDefQ; -+ -+ portCfgReg &= ~ETH_DEF_RX_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_QUEUE_MASK(pPortCtrl->portConfig.rxDefQ); -+ -+ portCfgReg &= ~ETH_DEF_RX_ARP_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_ARP_QUEUE_MASK(pPortCtrl->portConfig.rxArpQ); -+ -+ portCfgReg &= ~ETH_DEF_RX_BPDU_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_BPDU_QUEUE_MASK(pPortCtrl->portConfig.rxBpduQ); -+ -+ portCfgReg &= ~ETH_DEF_RX_TCP_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_TCP_QUEUE_MASK(pPortCtrl->portConfig.rxTcpQ); -+ -+ portCfgReg &= ~ETH_DEF_RX_UDP_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_UDP_QUEUE_MASK(pPortCtrl->portConfig.rxUdpQ); -+ -+ /* Assignment of Tx CTRP of given queue */ -+ txPrio = 0; -+ -+ for(queue=0; queuetxQueue[queue]; -+ -+ if(pQueueCtrl->pFirstDescr != NULL) -+ { -+ ethResetTxDescRing(pPortCtrl, queue); -+ -+ MV_REG_WRITE(ETH_TXQ_TOKEN_COUNT_REG(ethPortNo, queue), -+ 0x3fffffff); -+ MV_REG_WRITE(ETH_TXQ_TOKEN_CFG_REG(ethPortNo, queue), -+ 0x03ffffff); -+ } -+ else -+ { -+ MV_REG_WRITE(ETH_TXQ_TOKEN_COUNT_REG(ethPortNo, queue), 0x0); -+ MV_REG_WRITE(ETH_TXQ_TOKEN_CFG_REG(ethPortNo, queue), 0x0); -+ } -+ } -+ -+ /* Assignment of Rx CRDP of given queue */ -+ for(queue=0; queueportNo; -+ -+ if( (pPortCtrl->portState != MV_ACTIVE) && -+ (pPortCtrl->portState != MV_PAUSED) ) -+ { -+ mvOsPrintf("ethDrv port%d: Unexpected port state %d\n", -+ ethPortNo, pPortCtrl->portState); -+ return MV_BAD_STATE; -+ } -+ -+ ethPortNo = pPortCtrl->portNo; -+ -+ /* Enable port RX. */ -+ MV_REG_WRITE(ETH_RX_QUEUE_COMMAND_REG(ethPortNo), pPortCtrl->portRxQueueCmdReg); -+ -+ /* Enable port TX. */ -+ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(ethPortNo)) = pPortCtrl->portTxQueueCmdReg; -+ -+ pPortCtrl->portState = MV_ACTIVE; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* ethPortDown - Stop the Ethernet port activity. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet port handler -+* -+* RETURN: MV_STATUS -+* MV_OK - Success, Others - Failure. -+* -+* NOTE : used for port link down. -+*******************************************************************************/ -+MV_STATUS mvEthPortDown(void* pEthPortHndl) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ int ethPortNum = pPortCtrl->portNo; -+ unsigned int regData; -+ volatile int uDelay, mDelay; -+ -+ /* Stop Rx port activity. Check port Rx activity. */ -+ regData = (MV_REG_READ(ETH_RX_QUEUE_COMMAND_REG(ethPortNum))) & ETH_RXQ_ENABLE_MASK; -+ if(regData != 0) -+ { -+ /* Issue stop command for active channels only */ -+ MV_REG_WRITE(ETH_RX_QUEUE_COMMAND_REG(ethPortNum), (regData << ETH_RXQ_DISABLE_OFFSET)); -+ } -+ -+ /* Stop Tx port activity. Check port Tx activity. */ -+ regData = (MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(ethPortNum))) & ETH_TXQ_ENABLE_MASK; -+ if(regData != 0) -+ { -+ /* Issue stop command for active channels only */ -+ MV_REG_WRITE(ETH_TX_QUEUE_COMMAND_REG(ethPortNum), -+ (regData << ETH_TXQ_DISABLE_OFFSET) ); -+ } -+ -+ /* Force link down */ -+/* -+ regData = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNum)); -+ regData &= ~(ETH_DO_NOT_FORCE_LINK_FAIL_MASK); -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNum), regData); -+*/ -+ /* Wait for all Rx activity to terminate. */ -+ mDelay = 0; -+ do -+ { -+ if(mDelay >= RX_DISABLE_TIMEOUT_MSEC) -+ { -+ mvOsPrintf("ethPort_%d: TIMEOUT for RX stopped !!! rxQueueCmd - 0x08%x\n", -+ ethPortNum, regData); -+ break; -+ } -+ mvOsDelay(1); -+ mDelay++; -+ -+ /* Check port RX Command register that all Rx queues are stopped */ -+ regData = MV_REG_READ(ETH_RX_QUEUE_COMMAND_REG(ethPortNum)); -+ } -+ while(regData & 0xFF); -+ -+ /* Wait for all Tx activity to terminate. */ -+ mDelay = 0; -+ do -+ { -+ if(mDelay >= TX_DISABLE_TIMEOUT_MSEC) -+ { -+ mvOsPrintf("ethPort_%d: TIMEOUT for TX stoped !!! txQueueCmd - 0x08%x\n", -+ ethPortNum, regData); -+ break; -+ } -+ mvOsDelay(1); -+ mDelay++; -+ -+ /* Check port TX Command register that all Tx queues are stopped */ -+ regData = MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(ethPortNum)); -+ } -+ while(regData & 0xFF); -+ -+ /* Double check to Verify that TX FIFO is Empty */ -+ mDelay = 0; -+ while(MV_TRUE) -+ { -+ do -+ { -+ if(mDelay >= TX_FIFO_EMPTY_TIMEOUT_MSEC) -+ { -+ mvOsPrintf("\n ethPort_%d: TIMEOUT for TX FIFO empty !!! portStatus - 0x08%x\n", -+ ethPortNum, regData); -+ break; -+ } -+ mvOsDelay(1); -+ mDelay++; -+ -+ regData = MV_REG_READ(ETH_PORT_STATUS_REG(ethPortNum)); -+ } -+ while( ((regData & ETH_TX_FIFO_EMPTY_MASK) == 0) || -+ ((regData & ETH_TX_IN_PROGRESS_MASK) != 0) ); -+ -+ if(mDelay >= TX_FIFO_EMPTY_TIMEOUT_MSEC) -+ break; -+ -+ /* Double check */ -+ regData = MV_REG_READ(ETH_PORT_STATUS_REG(ethPortNum)); -+ if( ((regData & ETH_TX_FIFO_EMPTY_MASK) != 0) && -+ ((regData & ETH_TX_IN_PROGRESS_MASK) == 0) ) -+ { -+ break; -+ } -+ else -+ mvOsPrintf("ethPort_%d: TX FIFO Empty double check failed. %d msec, portStatus=0x%x\n", -+ ethPortNum, mDelay, regData); -+ } -+ -+ /* Do NOT force link down */ -+/* -+ regData = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNum)); -+ regData |= (ETH_DO_NOT_FORCE_LINK_FAIL_MASK); -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNum), regData); -+*/ -+ /* Wait about 2500 tclk cycles */ -+ uDelay = (PORT_DISABLE_WAIT_TCLOCKS/(mvBoardTclkGet()/1000000)); -+ mvOsUDelay(uDelay); -+ -+ pPortCtrl->portState = MV_PAUSED; -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* ethPortEnable - Enable the Ethernet port and Start RX and TX. -+* -+* DESCRIPTION: -+* This routine enable the Ethernet port and Rx and Tx activity: -+* -+* Note: Each Rx and Tx queue descriptor's list must be initialized prior -+* to calling this function (use etherInitTxDescRing for Tx queues and -+* etherInitRxDescRing for Rx queues). -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet port handler -+* -+* RETURN: MV_STATUS -+* MV_OK - Success, Others - Failure. -+* -+* NOTE: main usage is to enable the port after ifconfig up. -+*******************************************************************************/ -+MV_STATUS mvEthPortEnable(void* pEthPortHndl) -+{ -+ int ethPortNo; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ MV_U32 portSerialCtrlReg; -+ -+ ethPortNo = pPortCtrl->portNo; -+ -+ /* Enable port */ -+ portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNo)); -+ portSerialCtrlReg |= (ETH_DO_NOT_FORCE_LINK_FAIL_MASK | ETH_PORT_ENABLE_MASK); -+ -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNo), portSerialCtrlReg); -+ -+ mvEthMibCountersClear(pEthPortHndl); -+ -+ pPortCtrl->portState = MV_PAUSED; -+ -+ /* If Link is UP, Start RX and TX traffic */ -+ if( MV_REG_READ( ETH_PORT_STATUS_REG(ethPortNo) ) & ETH_LINK_UP_MASK) -+ return( mvEthPortUp(pEthPortHndl) ); -+ -+ return MV_NOT_READY; -+} -+ -+ -+/******************************************************************************* -+* mvEthPortDisable - Stop RX and TX activities and Disable the Ethernet port. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet port handler -+* -+* RETURN: MV_STATUS -+* MV_OK - Success, Others - Failure. -+* -+* NOTE: main usage is to disable the port after ifconfig down. -+*******************************************************************************/ -+MV_STATUS mvEthPortDisable(void* pEthPortHndl) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ int ethPortNum = pPortCtrl->portNo; -+ unsigned int regData; -+ volatile int mvDelay; -+ -+ if(pPortCtrl->portState == MV_ACTIVE) -+ { -+ /* Stop RX and TX activities */ -+ mvEthPortDown(pEthPortHndl); -+ } -+ -+ /* Reset the Enable bit in the Serial Control Register */ -+ regData = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNum)); -+ regData &= ~(ETH_PORT_ENABLE_MASK); -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNum), regData); -+ -+ /* Wait about 2500 tclk cycles */ -+ mvDelay = (PORT_DISABLE_WAIT_TCLOCKS*(mvCpuPclkGet()/mvBoardTclkGet())); -+ for(mvDelay; mvDelay>0; mvDelay--); -+ -+ pPortCtrl->portState = MV_IDLE; -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthPortForceTxDone - Get next buffer from TX queue in spite of buffer ownership. -+* -+* DESCRIPTION: -+* This routine used to free buffers attached to the Tx ring and should -+* be called only when Giga Ethernet port is Down -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet Port handler. -+* int txQueue - Number of TX queue. -+* -+* OUTPUT: -+* MV_PKT_INFO *pPktInfo - Pointer to packet was sent. -+* -+* RETURN: -+* MV_EMPTY - There is no more buffers in this queue. -+* MV_OK - Buffer detached from the queue and pPktInfo structure -+* filled with relevant information. -+* -+*******************************************************************************/ -+MV_PKT_INFO* mvEthPortForceTxDone(void* pEthPortHndl, int txQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ MV_PKT_INFO* pPktInfo; -+ ETH_TX_DESC* pTxDesc; -+ int port = pPortCtrl->portNo; -+ -+ pQueueCtrl = &pPortCtrl->txQueue[txQueue]; -+ -+ while( (pQueueCtrl->pUsedDescr != pQueueCtrl->pCurrentDescr) || -+ (pQueueCtrl->resource == 0) ) -+ { -+ /* Free next descriptor */ -+ pQueueCtrl->resource++; -+ pTxDesc = (ETH_TX_DESC*)pQueueCtrl->pUsedDescr; -+ -+ /* pPktInfo is available only in descriptors which are last descriptors */ -+ pPktInfo = (MV_PKT_INFO*)pTxDesc->returnInfo; -+ if (pPktInfo) -+ pPktInfo->status = pTxDesc->cmdSts; -+ -+ pTxDesc->cmdSts = 0x0; -+ pTxDesc->returnInfo = 0x0; -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxDesc); -+ -+ pQueueCtrl->pUsedDescr = TX_NEXT_DESC_PTR(pTxDesc, pQueueCtrl); -+ -+ if (pPktInfo) -+ if (pPktInfo->status & ETH_TX_LAST_DESC_MASK) -+ return pPktInfo; -+ } -+ MV_REG_WRITE( ETH_TX_CUR_DESC_PTR_REG(port, txQueue), -+ (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); -+ return NULL; -+} -+ -+ -+ -+/******************************************************************************* -+* mvEthPortForceRx - Get next buffer from RX queue in spite of buffer ownership. -+* -+* DESCRIPTION: -+* This routine used to free buffers attached to the Rx ring and should -+* be called only when Giga Ethernet port is Down -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet Port handler. -+* int rxQueue - Number of Rx queue. -+* -+* OUTPUT: -+* MV_PKT_INFO *pPktInfo - Pointer to received packet. -+* -+* RETURN: -+* MV_EMPTY - There is no more buffers in this queue. -+* MV_OK - Buffer detached from the queue and pBufInfo structure -+* filled with relevant information. -+* -+*******************************************************************************/ -+MV_PKT_INFO* mvEthPortForceRx(void* pEthPortHndl, int rxQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ ETH_RX_DESC* pRxDesc; -+ MV_PKT_INFO* pPktInfo; -+ int port = pPortCtrl->portNo; -+ -+ pQueueCtrl = &pPortCtrl->rxQueue[rxQueue]; -+ -+ if(pQueueCtrl->resource == 0) -+ { -+ MV_REG_WRITE( ETH_RX_CUR_DESC_PTR_REG(port, rxQueue), -+ (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); -+ -+ return NULL; -+ } -+ /* Free next descriptor */ -+ pQueueCtrl->resource--; -+ pRxDesc = (ETH_RX_DESC*)pQueueCtrl->pCurrentDescr; -+ pPktInfo = (MV_PKT_INFO*)pRxDesc->returnInfo; -+ -+ pPktInfo->status = pRxDesc->cmdSts; -+ pRxDesc->cmdSts = 0x0; -+ pRxDesc->returnInfo = 0x0; -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxDesc); -+ -+ pQueueCtrl->pCurrentDescr = RX_NEXT_DESC_PTR(pRxDesc, pQueueCtrl); -+ return pPktInfo; -+} -+ -+ -+/******************************************************************************/ -+/* Port Configuration functions */ -+/******************************************************************************/ -+/******************************************************************************* -+* mvEthMruGet - Get MRU configuration for Max Rx packet size. -+* -+* INPUT: -+* MV_U32 maxRxPktSize - max packet size. -+* -+* RETURN: MV_U32 - MRU configuration. -+* -+*******************************************************************************/ -+static MV_U32 mvEthMruGet(MV_U32 maxRxPktSize) -+{ -+ MV_U32 portSerialCtrlReg = 0; -+ -+ if(maxRxPktSize > 9192) -+ portSerialCtrlReg |= ETH_MAX_RX_PACKET_9700BYTE; -+ else if(maxRxPktSize > 9022) -+ portSerialCtrlReg |= ETH_MAX_RX_PACKET_9192BYTE; -+ else if(maxRxPktSize > 1552) -+ portSerialCtrlReg |= ETH_MAX_RX_PACKET_9022BYTE; -+ else if(maxRxPktSize > 1522) -+ portSerialCtrlReg |= ETH_MAX_RX_PACKET_1552BYTE; -+ else if(maxRxPktSize > 1518) -+ portSerialCtrlReg |= ETH_MAX_RX_PACKET_1522BYTE; -+ else -+ portSerialCtrlReg |= ETH_MAX_RX_PACKET_1518BYTE; -+ -+ return portSerialCtrlReg; -+} -+ -+/******************************************************************************* -+* mvEthRxCoalSet - Sets coalescing interrupt mechanism on RX path -+* -+* DESCRIPTION: -+* This routine sets the RX coalescing interrupt mechanism parameter. -+* This parameter is a timeout counter, that counts in 64 tClk -+* chunks, that when timeout event occurs a maskable interrupt occurs. -+* The parameter is calculated using the tCLK frequency of the -+* MV-64xxx chip, and the required number is in micro seconds. -+* -+* INPUT: -+* void* pPortHndl - Ethernet Port handler. -+* MV_U32 uSec - Number of micro seconds between -+* RX interrupts -+* -+* RETURN: -+* None. -+* -+* COMMENT: -+* 1 sec - TCLK_RATE clocks -+* 1 uSec - TCLK_RATE / 1,000,000 clocks -+* -+* Register Value for N micro seconds - ((N * ( (TCLK_RATE / 1,000,000)) / 64) -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_U32 mvEthRxCoalSet (void* pPortHndl, MV_U32 uSec) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ MV_U32 coal = ((uSec * (mvBoardTclkGet() / 1000000)) / 64); -+ MV_U32 portSdmaCfgReg; -+ -+ portSdmaCfgReg = MV_REG_READ(ETH_SDMA_CONFIG_REG(pPortCtrl->portNo)); -+ portSdmaCfgReg &= ~ETH_RX_INTR_COAL_ALL_MASK; -+ -+ portSdmaCfgReg |= ETH_RX_INTR_COAL_MASK(coal); -+ -+#if (MV_ETH_VERSION >= 2) -+ /* Set additional bit if needed ETH_RX_INTR_COAL_MSB_BIT (25) */ -+ if(ETH_RX_INTR_COAL_MASK(coal) > ETH_RX_INTR_COAL_ALL_MASK) -+ portSdmaCfgReg |= ETH_RX_INTR_COAL_MSB_MASK; -+#endif /* MV_ETH_VERSION >= 2 */ -+ -+ MV_REG_WRITE (ETH_SDMA_CONFIG_REG(pPortCtrl->portNo), portSdmaCfgReg); -+ return coal; -+} -+ -+/******************************************************************************* -+* mvEthTxCoalSet - Sets coalescing interrupt mechanism on TX path -+* -+* DESCRIPTION: -+* This routine sets the TX coalescing interrupt mechanism parameter. -+* This parameter is a timeout counter, that counts in 64 tClk -+* chunks, that when timeout event occurs a maskable interrupt -+* occurs. -+* The parameter is calculated using the tCLK frequency of the -+* MV-64xxx chip, and the required number is in micro seconds. -+* -+* INPUT: -+* void* pPortHndl - Ethernet Port handler. -+* MV_U32 uSec - Number of micro seconds between -+* RX interrupts -+* -+* RETURN: -+* None. -+* -+* COMMENT: -+* 1 sec - TCLK_RATE clocks -+* 1 uSec - TCLK_RATE / 1,000,000 clocks -+* -+* Register Value for N micro seconds - ((N * ( (TCLK_RATE / 1,000,000)) / 64) -+* -+*******************************************************************************/ -+MV_U32 mvEthTxCoalSet(void* pPortHndl, MV_U32 uSec) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ MV_U32 coal = ((uSec * (mvBoardTclkGet() / 1000000)) / 64); -+ MV_U32 regVal; -+ -+ regVal = MV_REG_READ(ETH_TX_FIFO_URGENT_THRESH_REG(pPortCtrl->portNo)); -+ regVal &= ~ETH_TX_INTR_COAL_ALL_MASK; -+ regVal |= ETH_TX_INTR_COAL_MASK(coal); -+ -+ /* Set TX Coalescing mechanism */ -+ MV_REG_WRITE (ETH_TX_FIFO_URGENT_THRESH_REG(pPortCtrl->portNo), regVal); -+ return coal; -+} -+ -+/******************************************************************************* -+* mvEthCoalGet - Gets RX and TX coalescing values in micro seconds -+* -+* DESCRIPTION: -+* This routine gets the RX and TX coalescing interrupt values. -+* The parameter is calculated using the tCLK frequency of the -+* MV-64xxx chip, and the returned numbers are in micro seconds. -+* -+* INPUTs: -+* void* pPortHndl - Ethernet Port handler. -+* -+* OUTPUTs: -+* MV_U32* pRxCoal - Number of micro seconds between RX interrupts -+* MV_U32* pTxCoal - Number of micro seconds between TX interrupts -+* -+* RETURN: -+* MV_STATUS MV_OK - success -+* Others - failure. -+* -+* COMMENT: -+* 1 sec - TCLK_RATE clocks -+* 1 uSec - TCLK_RATE / 1,000,000 clocks -+* -+* Register Value for N micro seconds - ((N * ( (TCLK_RATE / 1,000,000)) / 64) -+* -+*******************************************************************************/ -+MV_STATUS mvEthCoalGet(void* pPortHndl, MV_U32* pRxCoal, MV_U32* pTxCoal) -+{ -+ MV_U32 regVal, coal, usec; -+ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ -+ /* get TX Coalescing */ -+ regVal = MV_REG_READ (ETH_TX_FIFO_URGENT_THRESH_REG(pPortCtrl->portNo)); -+ coal = ((regVal & ETH_TX_INTR_COAL_ALL_MASK) >> ETH_TX_INTR_COAL_OFFSET); -+ -+ usec = (coal * 64) / (mvBoardTclkGet() / 1000000); -+ if(pTxCoal != NULL) -+ *pTxCoal = usec; -+ -+ /* Get RX Coalescing */ -+ regVal = MV_REG_READ(ETH_SDMA_CONFIG_REG(pPortCtrl->portNo)); -+ coal = ((regVal & ETH_RX_INTR_COAL_ALL_MASK) >> ETH_RX_INTR_COAL_OFFSET); -+ -+#if (MV_ETH_VERSION >= 2) -+ if(regVal & ETH_RX_INTR_COAL_MSB_MASK) -+ { -+ /* Add MSB */ -+ coal |= (ETH_RX_INTR_COAL_ALL_MASK + 1); -+ } -+#endif /* MV_ETH_VERSION >= 2 */ -+ -+ usec = (coal * 64) / (mvBoardTclkGet() / 1000000); -+ if(pRxCoal != NULL) -+ *pRxCoal = usec; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthMaxRxSizeSet - -+* -+* DESCRIPTION: -+* Change maximum receive size of the port. This configuration will take place -+* after next call of ethPortSetDefaults() function. -+* -+* INPUT: -+* -+* RETURN: -+*******************************************************************************/ -+MV_STATUS mvEthMaxRxSizeSet(void* pPortHndl, int maxRxSize) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ MV_U32 portSerialCtrlReg; -+ -+ if((maxRxSize < 1518) || (maxRxSize & ~ETH_RX_BUFFER_MASK)) -+ return MV_BAD_PARAM; -+ -+ pPortCtrl->portConfig.maxRxPktSize = maxRxSize; -+ -+ portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(pPortCtrl->portNo)); -+ portSerialCtrlReg &= ~ETH_MAX_RX_PACKET_SIZE_MASK; -+ portSerialCtrlReg |= mvEthMruGet(pPortCtrl->portConfig.maxRxPktSize); -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(pPortCtrl->portNo), portSerialCtrlReg); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************/ -+/* MAC Filtering functions */ -+/******************************************************************************/ -+ -+/******************************************************************************* -+* mvEthRxFilterModeSet - Configure Fitering mode of Ethernet port -+* -+* DESCRIPTION: -+* This routine used to free buffers attached to the Rx ring and should -+* be called only when Giga Ethernet port is Down -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet Port handler. -+* MV_BOOL isPromisc - Promiscous mode -+* MV_TRUE - accept all Broadcast, Multicast -+* and Unicast packets -+* MV_FALSE - accept all Broadcast, -+* specially added Multicast and -+* single Unicast packets -+* -+* RETURN: MV_STATUS MV_OK - Success, Other - Failure -+* -+*******************************************************************************/ -+MV_STATUS mvEthRxFilterModeSet(void* pEthPortHndl, MV_BOOL isPromisc) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ int queue; -+ MV_U32 portCfgReg; -+ -+ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); -+ /* Set / Clear UPM bit in port configuration register */ -+ if(isPromisc) -+ { -+ /* Accept all multicast packets to RX default queue */ -+ queue = pPortCtrl->portConfig.rxDefQ; -+ portCfgReg |= ETH_UNICAST_PROMISCUOUS_MODE_MASK; -+ memset(pPortCtrl->mcastCount, 1, sizeof(pPortCtrl->mcastCount)); -+ MV_REG_WRITE(ETH_MAC_ADDR_LOW_REG(pPortCtrl->portNo),0xFFFF); -+ MV_REG_WRITE(ETH_MAC_ADDR_HIGH_REG(pPortCtrl->portNo),0xFFFFFFFF); -+ } -+ else -+ { -+ /* Reject all Multicast addresses */ -+ queue = -1; -+ portCfgReg &= ~ETH_UNICAST_PROMISCUOUS_MODE_MASK; -+ /* Clear all mcastCount */ -+ memset(pPortCtrl->mcastCount, 0, sizeof(pPortCtrl->mcastCount)); -+ } -+ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); -+ -+ /* Set Special Multicast and Other Multicast tables */ -+ mvEthSetSpecialMcastTable(pPortCtrl->portNo, queue); -+ mvEthSetOtherMcastTable(pPortCtrl->portNo, queue); -+ ethSetUcastTable(pPortCtrl->portNo, queue); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthMacAddrSet - This function Set the port Unicast address. -+* -+* DESCRIPTION: -+* This function Set the port Ethernet MAC address. This address -+* will be used to send Pause frames if enabled. Packets with this -+* address will be accepted and dispatched to default RX queue -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet port handler. -+* char* pAddr - Address to be set -+* -+* RETURN: MV_STATUS -+* MV_OK - Success, Other - Faulure -+* -+*******************************************************************************/ -+MV_STATUS mvEthMacAddrSet(void* pPortHndl, unsigned char *pAddr, int queue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ unsigned int macH; -+ unsigned int macL; -+ -+ if(queue >= MV_ETH_RX_Q_NUM) -+ { -+ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", queue); -+ return MV_BAD_PARAM; -+ } -+ -+ if(queue != -1) -+ { -+ macL = (pAddr[4] << 8) | (pAddr[5]); -+ macH = (pAddr[0] << 24)| (pAddr[1] << 16) | -+ (pAddr[2] << 8) | (pAddr[3] << 0); -+ -+ MV_REG_WRITE(ETH_MAC_ADDR_LOW_REG(pPortCtrl->portNo), macL); -+ MV_REG_WRITE(ETH_MAC_ADDR_HIGH_REG(pPortCtrl->portNo), macH); -+ } -+ -+ /* Accept frames of this address */ -+ ethSetUcastAddr(pPortCtrl->portNo, pAddr[5], queue); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthMacAddrGet - This function returns the port Unicast address. -+* -+* DESCRIPTION: -+* This function returns the port Ethernet MAC address. -+* -+* INPUT: -+* int portNo - Ethernet port number. -+* char* pAddr - Pointer where address will be written to -+* -+* RETURN: MV_STATUS -+* MV_OK - Success, Other - Faulure -+* -+*******************************************************************************/ -+MV_STATUS mvEthMacAddrGet(int portNo, unsigned char *pAddr) -+{ -+ unsigned int macH; -+ unsigned int macL; -+ -+ if(pAddr == NULL) -+ { -+ mvOsPrintf("mvEthMacAddrGet: NULL pointer.\n"); -+ return MV_BAD_PARAM; -+ } -+ -+ macH = MV_REG_READ(ETH_MAC_ADDR_HIGH_REG(portNo)); -+ macL = MV_REG_READ(ETH_MAC_ADDR_LOW_REG(portNo)); -+ pAddr[0] = (macH >> 24) & 0xff; -+ pAddr[1] = (macH >> 16) & 0xff; -+ pAddr[2] = (macH >> 8) & 0xff; -+ pAddr[3] = macH & 0xff; -+ pAddr[4] = (macL >> 8) & 0xff; -+ pAddr[5] = macL & 0xff; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthMcastCrc8Get - Calculate CRC8 of MAC address. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* MV_U8* pAddr - Address to calculate CRC-8 -+* -+* RETURN: MV_U8 - CRC-8 of this MAC address -+* -+*******************************************************************************/ -+MV_U8 mvEthMcastCrc8Get(MV_U8* pAddr) -+{ -+ unsigned int macH; -+ unsigned int macL; -+ int macArray[48]; -+ int crc[8]; -+ int i; -+ unsigned char crcResult = 0; -+ -+ /* Calculate CRC-8 out of the given address */ -+ macH = (pAddr[0] << 8) | (pAddr[1]); -+ macL = (pAddr[2] << 24)| (pAddr[3] << 16) | -+ (pAddr[4] << 8) | (pAddr[5] << 0); -+ -+ for(i=0; i<32; i++) -+ macArray[i] = (macL >> i) & 0x1; -+ -+ for(i=32; i<48; i++) -+ macArray[i] = (macH >> (i - 32)) & 0x1; -+ -+ crc[0] = macArray[45] ^ macArray[43] ^ macArray[40] ^ macArray[39] ^ -+ macArray[35] ^ macArray[34] ^ macArray[31] ^ macArray[30] ^ -+ macArray[28] ^ macArray[23] ^ macArray[21] ^ macArray[19] ^ -+ macArray[18] ^ macArray[16] ^ macArray[14] ^ macArray[12] ^ -+ macArray[8] ^ macArray[7] ^ macArray[6] ^ macArray[0]; -+ -+ crc[1] = macArray[46] ^ macArray[45] ^ macArray[44] ^ macArray[43] ^ -+ macArray[41] ^ macArray[39] ^ macArray[36] ^ macArray[34] ^ -+ macArray[32] ^ macArray[30] ^ macArray[29] ^ macArray[28] ^ -+ macArray[24] ^ macArray[23] ^ macArray[22] ^ macArray[21] ^ -+ macArray[20] ^ macArray[18] ^ macArray[17] ^ macArray[16] ^ -+ macArray[15] ^ macArray[14] ^ macArray[13] ^ macArray[12] ^ -+ macArray[9] ^ macArray[6] ^ macArray[1] ^ macArray[0]; -+ -+ crc[2] = macArray[47] ^ macArray[46] ^ macArray[44] ^ macArray[43] ^ -+ macArray[42] ^ macArray[39] ^ macArray[37] ^ macArray[34] ^ -+ macArray[33] ^ macArray[29] ^ macArray[28] ^ macArray[25] ^ -+ macArray[24] ^ macArray[22] ^ macArray[17] ^ macArray[15] ^ -+ macArray[13] ^ macArray[12] ^ macArray[10] ^ macArray[8] ^ -+ macArray[6] ^ macArray[2] ^ macArray[1] ^ macArray[0]; -+ -+ crc[3] = macArray[47] ^ macArray[45] ^ macArray[44] ^ macArray[43] ^ -+ macArray[40] ^ macArray[38] ^ macArray[35] ^ macArray[34] ^ -+ macArray[30] ^ macArray[29] ^ macArray[26] ^ macArray[25] ^ -+ macArray[23] ^ macArray[18] ^ macArray[16] ^ macArray[14] ^ -+ macArray[13] ^ macArray[11] ^ macArray[9] ^ macArray[7] ^ -+ macArray[3] ^ macArray[2] ^ macArray[1]; -+ -+ crc[4] = macArray[46] ^ macArray[45] ^ macArray[44] ^ macArray[41] ^ -+ macArray[39] ^ macArray[36] ^ macArray[35] ^ macArray[31] ^ -+ macArray[30] ^ macArray[27] ^ macArray[26] ^ macArray[24] ^ -+ macArray[19] ^ macArray[17] ^ macArray[15] ^ macArray[14] ^ -+ macArray[12] ^ macArray[10] ^ macArray[8] ^ macArray[4] ^ -+ macArray[3] ^ macArray[2]; -+ -+ crc[5] = macArray[47] ^ macArray[46] ^ macArray[45] ^ macArray[42] ^ -+ macArray[40] ^ macArray[37] ^ macArray[36] ^ macArray[32] ^ -+ macArray[31] ^ macArray[28] ^ macArray[27] ^ macArray[25] ^ -+ macArray[20] ^ macArray[18] ^ macArray[16] ^ macArray[15] ^ -+ macArray[13] ^ macArray[11] ^ macArray[9] ^ macArray[5] ^ -+ macArray[4] ^ macArray[3]; -+ -+ crc[6] = macArray[47] ^ macArray[46] ^ macArray[43] ^ macArray[41] ^ -+ macArray[38] ^ macArray[37] ^ macArray[33] ^ macArray[32] ^ -+ macArray[29] ^ macArray[28] ^ macArray[26] ^ macArray[21] ^ -+ macArray[19] ^ macArray[17] ^ macArray[16] ^ macArray[14] ^ -+ macArray[12] ^ macArray[10] ^ macArray[6] ^ macArray[5] ^ -+ macArray[4]; -+ -+ crc[7] = macArray[47] ^ macArray[44] ^ macArray[42] ^ macArray[39] ^ -+ macArray[38] ^ macArray[34] ^ macArray[33] ^ macArray[30] ^ -+ macArray[29] ^ macArray[27] ^ macArray[22] ^ macArray[20] ^ -+ macArray[18] ^ macArray[17] ^ macArray[15] ^ macArray[13] ^ -+ macArray[11] ^ macArray[7] ^ macArray[6] ^ macArray[5]; -+ -+ for(i=0; i<8; i++) -+ crcResult = crcResult | (crc[i] << i); -+ -+ return crcResult; -+} -+/******************************************************************************* -+* mvEthMcastAddrSet - Multicast address settings. -+* -+* DESCRIPTION: -+* This API controls the MV device MAC multicast support. -+* The MV device supports multicast using two tables: -+* 1) Special Multicast Table for MAC addresses of the form -+* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). -+* The MAC DA[7:0] bits are used as a pointer to the Special Multicast -+* Table entries in the DA-Filter table. -+* In this case, the function calls ethPortSmcAddr() routine to set the -+* Special Multicast Table. -+* 2) Other Multicast Table for multicast of another type. A CRC-8bit -+* is used as an index to the Other Multicast Table entries in the -+* DA-Filter table. -+* In this case, the function calculates the CRC-8bit value and calls -+* ethPortOmcAddr() routine to set the Other Multicast Table. -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet port handler. -+* MV_U8* pAddr - Address to be set -+* int queue - RX queue to capture all packets with this -+* Multicast MAC address. -+* -1 means delete this Multicast address. -+* -+* RETURN: MV_STATUS -+* MV_TRUE - Success, Other - Failure -+* -+*******************************************************************************/ -+MV_STATUS mvEthMcastAddrSet(void* pPortHndl, MV_U8 *pAddr, int queue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ unsigned char crcResult = 0; -+ -+ if(queue >= MV_ETH_RX_Q_NUM) -+ { -+ mvOsPrintf("ethPort %d: RX queue #%d is out of range\n", -+ pPortCtrl->portNo, queue); -+ return MV_BAD_PARAM; -+ } -+ -+ if((pAddr[0] == 0x01) && -+ (pAddr[1] == 0x00) && -+ (pAddr[2] == 0x5E) && -+ (pAddr[3] == 0x00) && -+ (pAddr[4] == 0x00)) -+ { -+ ethSetSpecialMcastAddr(pPortCtrl->portNo, pAddr[5], queue); -+ } -+ else -+ { -+ crcResult = mvEthMcastCrc8Get(pAddr); -+ -+ /* Check Add counter for this CRC value */ -+ if(queue == -1) -+ { -+ if(pPortCtrl->mcastCount[crcResult] == 0) -+ { -+ mvOsPrintf("ethPort #%d: No valid Mcast for crc8=0x%02x\n", -+ pPortCtrl->portNo, (unsigned)crcResult); -+ return MV_NO_SUCH; -+ } -+ -+ pPortCtrl->mcastCount[crcResult]--; -+ if(pPortCtrl->mcastCount[crcResult] != 0) -+ { -+ mvOsPrintf("ethPort #%d: After delete there are %d valid Mcast for crc8=0x%02x\n", -+ pPortCtrl->portNo, pPortCtrl->mcastCount[crcResult], -+ (unsigned)crcResult); -+ return MV_NO_CHANGE; -+ } -+ } -+ else -+ { -+ pPortCtrl->mcastCount[crcResult]++; -+ if(pPortCtrl->mcastCount[crcResult] > 1) -+ { -+ mvOsPrintf("ethPort #%d: Valid Mcast for crc8=0x%02x already exists\n", -+ pPortCtrl->portNo, (unsigned)crcResult); -+ return MV_NO_CHANGE; -+ } -+ } -+ ethSetOtherMcastAddr(pPortCtrl->portNo, crcResult, queue); -+ } -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* ethSetUcastTable - Unicast address settings. -+* -+* DESCRIPTION: -+* Set all entries in the Unicast MAC Table queue==-1 means reject all -+* INPUT: -+* -+* RETURN: -+* -+*******************************************************************************/ -+static void ethSetUcastTable(int portNo, int queue) -+{ -+ int offset; -+ MV_U32 regValue; -+ -+ if(queue == -1) -+ { -+ regValue = 0; -+ } -+ else -+ { -+ regValue = (((0x01 | (queue<<1)) << 0) | -+ ((0x01 | (queue<<1)) << 8) | -+ ((0x01 | (queue<<1)) << 16) | -+ ((0x01 | (queue<<1)) << 24)); -+ } -+ -+ for (offset=0; offset<=0xC; offset+=4) -+ MV_REG_WRITE((ETH_DA_FILTER_UCAST_BASE(portNo) + offset), regValue); -+} -+ -+/******************************************************************************* -+* mvEthSetSpecialMcastTable - Special Multicast address settings. -+* -+* DESCRIPTION: -+* Set all entries to the Special Multicast MAC Table. queue==-1 means reject all -+* INPUT: -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_VOID mvEthSetSpecialMcastTable(int portNo, int queue) -+{ -+ int offset; -+ MV_U32 regValue; -+ -+ if(queue == -1) -+ { -+ regValue = 0; -+ } -+ else -+ { -+ regValue = (((0x01 | (queue<<1)) << 0) | -+ ((0x01 | (queue<<1)) << 8) | -+ ((0x01 | (queue<<1)) << 16) | -+ ((0x01 | (queue<<1)) << 24)); -+ } -+ -+ for (offset=0; offset<=0xFC; offset+=4) -+ { -+ MV_REG_WRITE((ETH_DA_FILTER_SPEC_MCAST_BASE(portNo) + -+ offset), regValue); -+ } -+} -+ -+/******************************************************************************* -+* mvEthSetOtherMcastTable - Other Multicast address settings. -+* -+* DESCRIPTION: -+* Set all entries to the Other Multicast MAC Table. queue==-1 means reject all -+* INPUT: -+* -+* RETURN: -+* -+*******************************************************************************/ -+MV_VOID mvEthSetOtherMcastTable(int portNo, int queue) -+{ -+ int offset; -+ MV_U32 regValue; -+ -+ if(queue == -1) -+ { -+ regValue = 0; -+ } -+ else -+ { -+ regValue = (((0x01 | (queue<<1)) << 0) | -+ ((0x01 | (queue<<1)) << 8) | -+ ((0x01 | (queue<<1)) << 16) | -+ ((0x01 | (queue<<1)) << 24)); -+ } -+ -+ for (offset=0; offset<=0xFC; offset+=4) -+ { -+ MV_REG_WRITE((ETH_DA_FILTER_OTH_MCAST_BASE(portNo) + -+ offset), regValue); -+ } -+} -+ -+/******************************************************************************* -+* ethSetUcastAddr - This function Set the port unicast address table -+* -+* DESCRIPTION: -+* This function locates the proper entry in the Unicast table for the -+* specified MAC nibble and sets its properties according to function -+* parameters. -+* -+* INPUT: -+* int ethPortNum - Port number. -+* MV_U8 lastNibble - Unicast MAC Address last nibble. -+* int queue - Rx queue number for this MAC address. -+* value "-1" means remove address -+* -+* OUTPUT: -+* This function add/removes MAC addresses from the port unicast address -+* table. -+* -+* RETURN: -+* MV_TRUE is output succeeded. -+* MV_FALSE if option parameter is invalid. -+* -+*******************************************************************************/ -+static MV_BOOL ethSetUcastAddr(int portNo, MV_U8 lastNibble, int queue) -+{ -+ unsigned int unicastReg; -+ unsigned int tblOffset; -+ unsigned int regOffset; -+ -+ /* Locate the Unicast table entry */ -+ lastNibble = (0xf & lastNibble); -+ tblOffset = (lastNibble / 4) * 4; /* Register offset from unicast table base*/ -+ regOffset = lastNibble % 4; /* Entry offset within the above register */ -+ -+ -+ unicastReg = MV_REG_READ( (ETH_DA_FILTER_UCAST_BASE(portNo) + -+ tblOffset)); -+ -+ -+ if(queue == -1) -+ { -+ /* Clear accepts frame bit at specified unicast DA table entry */ -+ unicastReg &= ~(0xFF << (8*regOffset)); -+ } -+ else -+ { -+ unicastReg &= ~(0xFF << (8*regOffset)); -+ unicastReg |= ((0x01 | (queue<<1)) << (8*regOffset)); -+ } -+ MV_REG_WRITE( (ETH_DA_FILTER_UCAST_BASE(portNo) + tblOffset), -+ unicastReg); -+ -+ return MV_TRUE; -+} -+ -+/******************************************************************************* -+* ethSetSpecialMcastAddr - Special Multicast address settings. -+* -+* DESCRIPTION: -+* This routine controls the MV device special MAC multicast support. -+* The Special Multicast Table for MAC addresses supports MAC of the form -+* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). -+* The MAC DA[7:0] bits are used as a pointer to the Special Multicast -+* Table entries in the DA-Filter table. -+* This function set the Special Multicast Table appropriate entry -+* according to the argument given. -+* -+* INPUT: -+* int ethPortNum Port number. -+* unsigned char mcByte Multicast addr last byte (MAC DA[7:0] bits). -+* int queue Rx queue number for this MAC address. -+* int option 0 = Add, 1 = remove address. -+* -+* OUTPUT: -+* See description. -+* -+* RETURN: -+* MV_TRUE is output succeeded. -+* MV_FALSE if option parameter is invalid. -+* -+*******************************************************************************/ -+static MV_BOOL ethSetSpecialMcastAddr(int ethPortNum, MV_U8 lastByte, int queue) -+{ -+ unsigned int smcTableReg; -+ unsigned int tblOffset; -+ unsigned int regOffset; -+ -+ /* Locate the SMC table entry */ -+ tblOffset = (lastByte / 4); /* Register offset from SMC table base */ -+ regOffset = lastByte % 4; /* Entry offset within the above register */ -+ -+ smcTableReg = MV_REG_READ((ETH_DA_FILTER_SPEC_MCAST_BASE(ethPortNum) + tblOffset*4)); -+ -+ if(queue == -1) -+ { -+ /* Clear accepts frame bit at specified Special DA table entry */ -+ smcTableReg &= ~(0xFF << (8 * regOffset)); -+ } -+ else -+ { -+ smcTableReg &= ~(0xFF << (8 * regOffset)); -+ smcTableReg |= ((0x01 | (queue<<1)) << (8 * regOffset)); -+ } -+ MV_REG_WRITE((ETH_DA_FILTER_SPEC_MCAST_BASE(ethPortNum) + -+ tblOffset*4), smcTableReg); -+ -+ return MV_TRUE; -+} -+ -+/******************************************************************************* -+* ethSetOtherMcastAddr - Multicast address settings. -+* -+* DESCRIPTION: -+* This routine controls the MV device Other MAC multicast support. -+* The Other Multicast Table is used for multicast of another type. -+* A CRC-8bit is used as an index to the Other Multicast Table entries -+* in the DA-Filter table. -+* The function gets the CRC-8bit value from the calling routine and -+* set the Other Multicast Table appropriate entry according to the -+* CRC-8 argument given. -+* -+* INPUT: -+* int ethPortNum Port number. -+* MV_U8 crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1). -+* int queue Rx queue number for this MAC address. -+* -+* OUTPUT: -+* See description. -+* -+* RETURN: -+* MV_TRUE is output succeeded. -+* MV_FALSE if option parameter is invalid. -+* -+*******************************************************************************/ -+static MV_BOOL ethSetOtherMcastAddr(int ethPortNum, MV_U8 crc8, int queue) -+{ -+ unsigned int omcTableReg; -+ unsigned int tblOffset; -+ unsigned int regOffset; -+ -+ /* Locate the OMC table entry */ -+ tblOffset = (crc8 / 4) * 4; /* Register offset from OMC table base */ -+ regOffset = crc8 % 4; /* Entry offset within the above register */ -+ -+ omcTableReg = MV_REG_READ( -+ (ETH_DA_FILTER_OTH_MCAST_BASE(ethPortNum) + tblOffset)); -+ -+ if(queue == -1) -+ { -+ /* Clear accepts frame bit at specified Other DA table entry */ -+ omcTableReg &= ~(0xFF << (8 * regOffset)); -+ } -+ else -+ { -+ omcTableReg &= ~(0xFF << (8 * regOffset)); -+ omcTableReg |= ((0x01 | (queue<<1)) << (8 * regOffset)); -+ } -+ -+ MV_REG_WRITE((ETH_DA_FILTER_OTH_MCAST_BASE(ethPortNum) + tblOffset), -+ omcTableReg); -+ -+ return MV_TRUE; -+} -+ -+ -+/******************************************************************************/ -+/* MIB Counters functions */ -+/******************************************************************************/ -+ -+ -+/******************************************************************************* -+* mvEthMibCounterRead - Read a MIB counter -+* -+* DESCRIPTION: -+* This function reads a MIB counter of a specific ethernet port. -+* NOTE - Read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW or -+* ETH_MIB_GOOD_OCTETS_SENT_LOW counters will return 64 bits value, -+* so pHigh32 pointer should not be NULL in this case. -+* -+* INPUT: -+* int ethPortNum - Ethernet Port number. -+* unsigned int mibOffset - MIB counter offset. -+* -+* OUTPUT: -+* MV_U32* pHigh32 - pointer to place where 32 most significant bits -+* of the counter will be stored. -+* -+* RETURN: -+* 32 low sgnificant bits of MIB counter value. -+* -+*******************************************************************************/ -+MV_U32 mvEthMibCounterRead(void* pPortHandle, unsigned int mibOffset, -+ MV_U32* pHigh32) -+{ -+ int portNo; -+ MV_U32 valLow32, valHigh32; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ -+ portNo = pPortCtrl->portNo; -+ -+ valLow32 = MV_REG_READ(ETH_MIB_COUNTERS_BASE(portNo) + mibOffset); -+ -+ /* Implement FEr ETH. Erroneous Value when Reading the Upper 32-bits */ -+ /* of a 64-bit MIB Counter. */ -+ if( (mibOffset == ETH_MIB_GOOD_OCTETS_RECEIVED_LOW) || -+ (mibOffset == ETH_MIB_GOOD_OCTETS_SENT_LOW) ) -+ { -+ valHigh32 = MV_REG_READ(ETH_MIB_COUNTERS_BASE(portNo) + mibOffset + 4); -+ if(pHigh32 != NULL) -+ *pHigh32 = valHigh32; -+ } -+ return valLow32; -+} -+ -+/******************************************************************************* -+* mvEthMibCountersClear - Clear all MIB counters -+* -+* DESCRIPTION: -+* This function clears all MIB counters -+* -+* INPUT: -+* int ethPortNum - Ethernet Port number. -+* -+* -+* RETURN: void -+* -+*******************************************************************************/ -+void mvEthMibCountersClear(void* pPortHandle) -+{ -+ int i, portNo; -+ unsigned int dummy; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ -+ portNo = pPortCtrl->portNo; -+ -+ /* Perform dummy reads from MIB counters */ -+ for(i=ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i 0xFF) -+ { -+ mvOsPrintf("eth_%d: tos=0x%x is out of range\n", pPortCtrl->portNo, tos); -+ return -1; -+ } -+ regIdx = mvOsDivide(tos>>2, 10); -+ regOffs = mvOsReminder(tos>>2, 10); -+ -+ regValue = MV_REG_READ(ETH_DIFF_SERV_PRIO_REG(pPortCtrl->portNo, regIdx) ); -+ rxq = (regValue >> (regOffs*3)); -+ rxq &= 0x7; -+ -+ return rxq; -+} -+ -+/******************************************************************************* -+* mvEthTosToRxqSet - Map packets with special TOS value to special RX queue -+* -+* DESCRIPTION: -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* int tos - TOS value in the IP header of the packet -+* int rxq - RX Queue for packets with the configured TOS value -+* Negative value (-1) means no special processing for these packets, -+* so they will be processed as regular packets. -+* -+* RETURN: MV_STATUS -+*******************************************************************************/ -+MV_STATUS mvEthTosToRxqSet(void* pPortHandle, int tos, int rxq) -+{ -+ MV_U32 regValue; -+ int regIdx, regOffs; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ -+ if( (rxq < 0) || (rxq >= MV_ETH_RX_Q_NUM) ) -+ { -+ mvOsPrintf("eth_%d: RX queue #%d is out of range\n", pPortCtrl->portNo, rxq); -+ return MV_BAD_PARAM; -+ } -+ if(tos > 0xFF) -+ { -+ mvOsPrintf("eth_%d: tos=0x%x is out of range\n", pPortCtrl->portNo, tos); -+ return MV_BAD_PARAM; -+ } -+ regIdx = mvOsDivide(tos>>2, 10); -+ regOffs = mvOsReminder(tos>>2, 10); -+ -+ regValue = MV_REG_READ(ETH_DIFF_SERV_PRIO_REG(pPortCtrl->portNo, regIdx) ); -+ regValue &= ~(0x7 << (regOffs*3)); -+ regValue |= (rxq << (regOffs*3)); -+ -+ MV_REG_WRITE(ETH_DIFF_SERV_PRIO_REG(pPortCtrl->portNo, regIdx), regValue); -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthVlanPrioRxQueue - Configure RX queue to capture VLAN tagged packets with -+* special priority bits [0-2] -+* -+* DESCRIPTION: -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* int bpduQueue - Special queue to capture VLAN tagged packets with special -+* priority. -+* Negative value (-1) means no special processing for these packets, -+* so they will be processed as regular packets. -+* -+* RETURN: MV_STATUS -+* MV_OK - Success -+* MV_FAIL - Failed. -+* -+*******************************************************************************/ -+MV_STATUS mvEthVlanPrioRxQueue(void* pPortHandle, int vlanPrio, int vlanPrioQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ MV_U32 vlanPrioReg; -+ -+ if(vlanPrioQueue >= MV_ETH_RX_Q_NUM) -+ { -+ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", vlanPrioQueue); -+ return MV_BAD_PARAM; -+ } -+ if(vlanPrio >= 8) -+ { -+ mvOsPrintf("ethDrv: vlanPrio=%d is out of range\n", vlanPrio); -+ return MV_BAD_PARAM; -+ } -+ -+ vlanPrioReg = MV_REG_READ(ETH_VLAN_TAG_TO_PRIO_REG(pPortCtrl->portNo)); -+ vlanPrioReg &= ~(0x7 << (vlanPrio*3)); -+ vlanPrioReg |= (vlanPrioQueue << (vlanPrio*3)); -+ MV_REG_WRITE(ETH_VLAN_TAG_TO_PRIO_REG(pPortCtrl->portNo), vlanPrioReg); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvEthBpduRxQueue - Configure RX queue to capture BPDU packets. -+* -+* DESCRIPTION: -+* This function defines processing of BPDU packets. -+* BPDU packets can be accepted and captured to one of RX queues -+* or can be processing as regular Multicast packets. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* int bpduQueue - Special queue to capture BPDU packets (DA is equal to -+* 01-80-C2-00-00-00 through 01-80-C2-00-00-FF, -+* except for the Flow-Control Pause packets). -+* Negative value (-1) means no special processing for BPDU, -+* packets so they will be processed as regular Multicast packets. -+* -+* RETURN: MV_STATUS -+* MV_OK - Success -+* MV_FAIL - Failed. -+* -+*******************************************************************************/ -+MV_STATUS mvEthBpduRxQueue(void* pPortHandle, int bpduQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ MV_U32 portCfgReg; -+ MV_U32 portCfgExtReg; -+ -+ if(bpduQueue >= MV_ETH_RX_Q_NUM) -+ { -+ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", bpduQueue); -+ return MV_BAD_PARAM; -+ } -+ -+ portCfgExtReg = MV_REG_READ(ETH_PORT_CONFIG_EXTEND_REG(pPortCtrl->portNo)); -+ -+ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); -+ if(bpduQueue >= 0) -+ { -+ pPortCtrl->portConfig.rxBpduQ = bpduQueue; -+ -+ portCfgReg &= ~ETH_DEF_RX_BPDU_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_BPDU_QUEUE_MASK(pPortCtrl->portConfig.rxBpduQ); -+ -+ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); -+ -+ portCfgExtReg |= ETH_CAPTURE_SPAN_BPDU_ENABLE_MASK; -+ } -+ else -+ { -+ pPortCtrl->portConfig.rxBpduQ = -1; -+ /* no special processing for BPDU packets */ -+ portCfgExtReg &= (~ETH_CAPTURE_SPAN_BPDU_ENABLE_MASK); -+ } -+ -+ MV_REG_WRITE(ETH_PORT_CONFIG_EXTEND_REG(pPortCtrl->portNo), portCfgExtReg); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvEthArpRxQueue - Configure RX queue to capture ARP packets. -+* -+* DESCRIPTION: -+* This function defines processing of ARP (type=0x0806) packets. -+* ARP packets can be accepted and captured to one of RX queues -+* or can be processed as other Broadcast packets. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* int arpQueue - Special queue to capture ARP packets (type=0x806). -+* Negative value (-1) means discard ARP packets -+* -+* RETURN: MV_STATUS -+* MV_OK - Success -+* MV_FAIL - Failed. -+* -+*******************************************************************************/ -+MV_STATUS mvEthArpRxQueue(void* pPortHandle, int arpQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ MV_U32 portCfgReg; -+ -+ if(arpQueue >= MV_ETH_RX_Q_NUM) -+ { -+ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", arpQueue); -+ return MV_BAD_PARAM; -+ } -+ -+ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); -+ -+ if(arpQueue >= 0) -+ { -+ pPortCtrl->portConfig.rxArpQ = arpQueue; -+ portCfgReg &= ~ETH_DEF_RX_ARP_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_ARP_QUEUE_MASK(pPortCtrl->portConfig.rxArpQ); -+ -+ portCfgReg &= (~ETH_REJECT_ARP_BCAST_MASK); -+ } -+ else -+ { -+ pPortCtrl->portConfig.rxArpQ = -1; -+ portCfgReg |= ETH_REJECT_ARP_BCAST_MASK; -+ } -+ -+ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvEthTcpRxQueue - Configure RX queue to capture TCP packets. -+* -+* DESCRIPTION: -+* This function defines processing of TCP packets. -+* TCP packets can be accepted and captured to one of RX queues -+* or can be processed as regular Unicast packets. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* int tcpQueue - Special queue to capture TCP packets. Value "-1" -+* means no special processing for TCP packets, -+* so they will be processed as regular -+* -+* RETURN: MV_STATUS -+* MV_OK - Success -+* MV_FAIL - Failed. -+* -+*******************************************************************************/ -+MV_STATUS mvEthTcpRxQueue(void* pPortHandle, int tcpQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ MV_U32 portCfgReg; -+ -+ if(tcpQueue >= MV_ETH_RX_Q_NUM) -+ { -+ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", tcpQueue); -+ return MV_BAD_PARAM; -+ } -+ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); -+ -+ if(tcpQueue >= 0) -+ { -+ pPortCtrl->portConfig.rxTcpQ = tcpQueue; -+ portCfgReg &= ~ETH_DEF_RX_TCP_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_TCP_QUEUE_MASK(pPortCtrl->portConfig.rxTcpQ); -+ -+ portCfgReg |= ETH_CAPTURE_TCP_FRAMES_ENABLE_MASK; -+ } -+ else -+ { -+ pPortCtrl->portConfig.rxTcpQ = -1; -+ portCfgReg &= (~ETH_CAPTURE_TCP_FRAMES_ENABLE_MASK); -+ } -+ -+ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvEthUdpRxQueue - Configure RX queue to capture UDP packets. -+* -+* DESCRIPTION: -+* This function defines processing of UDP packets. -+* TCP packets can be accepted and captured to one of RX queues -+* or can be processed as regular Unicast packets. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* int udpQueue - Special queue to capture UDP packets. Value "-1" -+* means no special processing for UDP packets, -+* so they will be processed as regular -+* -+* RETURN: MV_STATUS -+* MV_OK - Success -+* MV_FAIL - Failed. -+* -+*******************************************************************************/ -+MV_STATUS mvEthUdpRxQueue(void* pPortHandle, int udpQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ MV_U32 portCfgReg; -+ -+ if(udpQueue >= MV_ETH_RX_Q_NUM) -+ { -+ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", udpQueue); -+ return MV_BAD_PARAM; -+ } -+ -+ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); -+ -+ if(udpQueue >= 0) -+ { -+ pPortCtrl->portConfig.rxUdpQ = udpQueue; -+ portCfgReg &= ~ETH_DEF_RX_UDP_QUEUE_ALL_MASK; -+ portCfgReg |= ETH_DEF_RX_UDP_QUEUE_MASK(pPortCtrl->portConfig.rxUdpQ); -+ -+ portCfgReg |= ETH_CAPTURE_UDP_FRAMES_ENABLE_MASK; -+ } -+ else -+ { -+ pPortCtrl->portConfig.rxUdpQ = -1; -+ portCfgReg &= ~ETH_CAPTURE_UDP_FRAMES_ENABLE_MASK; -+ } -+ -+ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************/ -+/* Speed, Duplex, FlowControl routines */ -+/******************************************************************************/ -+ -+/******************************************************************************* -+* mvEthSpeedDuplexSet - Set Speed and Duplex of the port. -+* -+* DESCRIPTION: -+* This function configure the port to work with desirable Duplex and Speed. -+* Changing of these parameters are allowed only when port is disabled. -+* This function disable the port if was enabled, change duplex and speed -+* and, enable the port back if needed. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* ETH_PORT_SPEED speed - Speed of the port. -+* ETH_PORT_SPEED duplex - Duplex of the port. -+* -+* RETURN: MV_STATUS -+* MV_OK - Success -+* MV_OUT_OF_RANGE - Failed. Port is out of valid range -+* MV_NOT_FOUND - Failed. Port is not initialized. -+* MV_BAD_PARAM - Input parameters (speed/duplex) in conflict. -+* MV_BAD_VALUE - Value of one of input parameters (speed, duplex) -+* is not valid -+* -+*******************************************************************************/ -+MV_STATUS mvEthSpeedDuplexSet(void* pPortHandle, MV_ETH_PORT_SPEED speed, -+ MV_ETH_PORT_DUPLEX duplex) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ int port = pPortCtrl->portNo; -+ MV_U32 portSerialCtrlReg; -+ -+ if( (port < 0) || (port >= (int)mvCtrlEthMaxPortGet()) ) -+ return MV_OUT_OF_RANGE; -+ -+ pPortCtrl = ethPortCtrl[port]; -+ if(pPortCtrl == NULL) -+ return MV_NOT_FOUND; -+ -+ /* Check validity */ -+ if( (speed == MV_ETH_SPEED_1000) && (duplex == MV_ETH_DUPLEX_HALF) ) -+ return MV_BAD_PARAM; -+ -+ portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port)); -+ /* Set Speed */ -+ switch(speed) -+ { -+ case MV_ETH_SPEED_AN: -+ portSerialCtrlReg &= ~ETH_DISABLE_SPEED_AUTO_NEG_MASK; -+ break; -+ -+ case MV_ETH_SPEED_10: -+ portSerialCtrlReg |= ETH_DISABLE_SPEED_AUTO_NEG_MASK; -+ portSerialCtrlReg &= ~ETH_SET_GMII_SPEED_1000_MASK; -+ portSerialCtrlReg &= ~ETH_SET_MII_SPEED_100_MASK; -+ break; -+ -+ case MV_ETH_SPEED_100: -+ portSerialCtrlReg |= ETH_DISABLE_SPEED_AUTO_NEG_MASK; -+ portSerialCtrlReg &= ~ETH_SET_GMII_SPEED_1000_MASK; -+ portSerialCtrlReg |= ETH_SET_MII_SPEED_100_MASK; -+ break; -+ -+ case MV_ETH_SPEED_1000: -+ portSerialCtrlReg |= ETH_DISABLE_SPEED_AUTO_NEG_MASK; -+ portSerialCtrlReg |= ETH_SET_GMII_SPEED_1000_MASK; -+ break; -+ -+ default: -+ mvOsPrintf("ethDrv: Unexpected Speed value %d\n", speed); -+ return MV_BAD_VALUE; -+ } -+ /* Set duplex */ -+ switch(duplex) -+ { -+ case MV_ETH_DUPLEX_AN: -+ portSerialCtrlReg &= ~ETH_DISABLE_DUPLEX_AUTO_NEG_MASK; -+ break; -+ -+ case MV_ETH_DUPLEX_HALF: -+ portSerialCtrlReg |= ETH_DISABLE_DUPLEX_AUTO_NEG_MASK; -+ portSerialCtrlReg &= ~ETH_SET_FULL_DUPLEX_MASK; -+ break; -+ -+ case MV_ETH_DUPLEX_FULL: -+ portSerialCtrlReg |= ETH_DISABLE_DUPLEX_AUTO_NEG_MASK; -+ portSerialCtrlReg |= ETH_SET_FULL_DUPLEX_MASK; -+ break; -+ -+ default: -+ mvOsPrintf("ethDrv: Unexpected Duplex value %d\n", duplex); -+ return MV_BAD_VALUE; -+ } -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(port), portSerialCtrlReg); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthFlowCtrlSet - Set Flow Control of the port. -+* -+* DESCRIPTION: -+* This function configure the port to work with desirable Duplex and -+* Speed. Changing of these parameters are allowed only when port is -+* disabled. This function disable the port if was enabled, change -+* duplex and speed and, enable the port back if needed. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* MV_ETH_PORT_FC flowControl - Flow control of the port. -+* -+* RETURN: MV_STATUS -+* MV_OK - Success -+* MV_OUT_OF_RANGE - Failed. Port is out of valid range -+* MV_NOT_FOUND - Failed. Port is not initialized. -+* MV_BAD_VALUE - Value flowControl parameters is not valid -+* -+*******************************************************************************/ -+MV_STATUS mvEthFlowCtrlSet(void* pPortHandle, MV_ETH_PORT_FC flowControl) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ int port = pPortCtrl->portNo; -+ MV_U32 portSerialCtrlReg; -+ -+ if( (port < 0) || (port >= (int)mvCtrlEthMaxPortGet() ) ) -+ return MV_OUT_OF_RANGE; -+ -+ pPortCtrl = ethPortCtrl[port]; -+ if(pPortCtrl == NULL) -+ return MV_NOT_FOUND; -+ -+ portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port)); -+ switch(flowControl) -+ { -+ case MV_ETH_FC_AN_ADV_DIS: -+ portSerialCtrlReg &= ~ETH_DISABLE_FC_AUTO_NEG_MASK; -+ portSerialCtrlReg &= ~ETH_ADVERTISE_SYM_FC_MASK; -+ break; -+ -+ case MV_ETH_FC_AN_ADV_SYM: -+ portSerialCtrlReg &= ~ETH_DISABLE_FC_AUTO_NEG_MASK; -+ portSerialCtrlReg |= ETH_ADVERTISE_SYM_FC_MASK; -+ break; -+ -+ case MV_ETH_FC_DISABLE: -+ portSerialCtrlReg |= ETH_DISABLE_FC_AUTO_NEG_MASK; -+ portSerialCtrlReg &= ~ETH_SET_FLOW_CTRL_MASK; -+ break; -+ -+ case MV_ETH_FC_ENABLE: -+ portSerialCtrlReg |= ETH_DISABLE_FC_AUTO_NEG_MASK; -+ portSerialCtrlReg |= ETH_SET_FLOW_CTRL_MASK; -+ break; -+ -+ default: -+ mvOsPrintf("ethDrv: Unexpected FlowControl value %d\n", flowControl); -+ return MV_BAD_VALUE; -+ } -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(port), portSerialCtrlReg); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthHeaderModeSet - Set port header mode. -+* -+* DESCRIPTION: -+* This function configures the port to work in Marvell-Header mode. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* MV_ETH_HEADER_MODE headerMode - The header mode to set the port in. -+* -+* RETURN: MV_STATUS -+* MV_OK - Success -+* MV_NOT_SUPPORTED- Feature not supported. -+* MV_OUT_OF_RANGE - Failed. Port is out of valid range -+* MV_NOT_FOUND - Failed. Port is not initialized. -+* MV_BAD_VALUE - Value of headerMode or numRxQueue parameter is not valid. -+* -+*******************************************************************************/ -+MV_STATUS mvEthHeaderModeSet(void* pPortHandle, MV_ETH_HEADER_MODE headerMode) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ int port = pPortCtrl->portNo; -+ MV_U32 mvHeaderReg; -+ MV_U32 numRxQ = MV_ETH_RX_Q_NUM; -+ -+ if((port < 0) || (port >= mvCtrlEthMaxPortGet())) -+ return MV_OUT_OF_RANGE; -+ -+ pPortCtrl = ethPortCtrl[port]; -+ if(pPortCtrl == NULL) -+ return MV_NOT_FOUND; -+ -+ mvHeaderReg = MV_REG_READ(ETH_PORT_MARVELL_HEADER_REG(port)); -+ /* Disable header mode. */ -+ mvHeaderReg &= ~ETH_MVHDR_EN_MASK; -+ -+ if(headerMode != MV_ETH_DISABLE_HEADER_MODE) -+ { -+ /* Enable Header mode. */ -+ mvHeaderReg |= ETH_MVHDR_EN_MASK; -+ -+ /* Clear DA-Prefix & MHMask fields.*/ -+ mvHeaderReg &= ~(ETH_MVHDR_DAPREFIX_MASK | ETH_MVHDR_MHMASK_MASK); -+ -+ if(numRxQ > 1) -+ { -+ switch (headerMode) -+ { -+ case(MV_ETH_ENABLE_HEADER_MODE_PRI_2_1): -+ mvHeaderReg |= ETH_MVHDR_DAPREFIX_PRI_1_2; -+ break; -+ case(MV_ETH_ENABLE_HEADER_MODE_PRI_DBNUM): -+ mvHeaderReg |= ETH_MVHDR_DAPREFIX_DBNUM_PRI; -+ break; -+ case(MV_ETH_ENABLE_HEADER_MODE_PRI_SPID): -+ mvHeaderReg |= ETH_MVHDR_DAPREFIX_SPID_PRI; -+ break; -+ default: -+ break; -+ } -+ -+ switch (numRxQ) -+ { -+ case (4): -+ mvHeaderReg |= ETH_MVHDR_MHMASK_4_QUEUE; -+ break; -+ case (8): -+ mvHeaderReg |= ETH_MVHDR_MHMASK_8_QUEUE; -+ break; -+ default: -+ break; -+ } -+ } -+ } -+ -+ MV_REG_WRITE(ETH_PORT_MARVELL_HEADER_REG(port), mvHeaderReg); -+ -+ return MV_OK; -+} -+ -+#if (MV_ETH_VERSION >= 4) -+/******************************************************************************* -+* mvEthEjpModeSet - Enable / Disable EJP policy for TX. -+* -+* DESCRIPTION: -+* This function -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* MV_BOOL TRUE - enable EJP mode -+* FALSE - disable EJP mode -+* -+* OUTPUT: MV_STATUS -+* MV_OK - Success -+* Other - Failure -+* -+* RETURN: None. -+* -+*******************************************************************************/ -+MV_STATUS mvEthEjpModeSet(void* pPortHandle, int mode) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ int port = pPortCtrl->portNo; -+ -+ if((port < 0) || (port >= mvCtrlEthMaxPortGet())) -+ return MV_OUT_OF_RANGE; -+ -+ pPortCtrl = ethPortCtrl[port]; -+ if(pPortCtrl == NULL) -+ return MV_NOT_FOUND; -+ -+ pPortCtrl->portConfig.ejpMode = mode; -+ if(mode) -+ { -+ /* EJP enabled */ -+ MV_REG_WRITE(ETH_TXQ_CMD_1_REG(port), ETH_TX_EJP_ENABLE_MASK); -+ } -+ else -+ { -+ /* EJP disabled */ -+ MV_REG_WRITE(ETH_TXQ_CMD_1_REG(port), 0); -+ } -+ mvOsPrintf("eth_%d: EJP %s - ETH_TXQ_CMD_1_REG: 0x%x = 0x%08x\n", -+ port, mode ? "Enabled" : "Disabled", ETH_TXQ_CMD_1_REG(port), -+ MV_REG_READ(ETH_TXQ_CMD_1_REG(port))); -+ -+ return MV_OK; -+} -+#endif /* MV_ETH_VERSION >= 4 */ -+ -+/******************************************************************************* -+* mvEthStatusGet - Get major properties of the port . -+* -+* DESCRIPTION: -+* This function get major properties of the port (link, speed, duplex, -+* flowControl, etc) and return them using the single structure. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* -+* OUTPUT: -+* MV_ETH_PORT_STATUS* pStatus - Pointer to structure, were port status -+* will be placed. -+* -+* RETURN: None. -+* -+*******************************************************************************/ -+void mvEthStatusGet(void* pPortHandle, MV_ETH_PORT_STATUS* pStatus) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ int port = pPortCtrl->portNo; -+ -+ MV_U32 regValue; -+ -+ regValue = MV_REG_READ( ETH_PORT_STATUS_REG(port) ); -+ -+ if(regValue & ETH_GMII_SPEED_1000_MASK) -+ pStatus->speed = MV_ETH_SPEED_1000; -+ else if(regValue & ETH_MII_SPEED_100_MASK) -+ pStatus->speed = MV_ETH_SPEED_100; -+ else -+ pStatus->speed = MV_ETH_SPEED_10; -+ -+ if(regValue & ETH_LINK_UP_MASK) -+ pStatus->isLinkUp = MV_TRUE; -+ else -+ pStatus->isLinkUp = MV_FALSE; -+ -+ if(regValue & ETH_FULL_DUPLEX_MASK) -+ pStatus->duplex = MV_ETH_DUPLEX_FULL; -+ else -+ pStatus->duplex = MV_ETH_DUPLEX_HALF; -+ -+ -+ if(regValue & ETH_ENABLE_RCV_FLOW_CTRL_MASK) -+ pStatus->flowControl = MV_ETH_FC_ENABLE; -+ else -+ pStatus->flowControl = MV_ETH_FC_DISABLE; -+} -+ -+ -+/******************************************************************************/ -+/* PHY Control Functions */ -+/******************************************************************************/ -+ -+ -+/******************************************************************************* -+* mvEthPhyAddrSet - Set the ethernet port PHY address. -+* -+* DESCRIPTION: -+* This routine set the ethernet port PHY address according to given -+* parameter. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* int phyAddr - PHY address -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+void mvEthPhyAddrSet(void* pPortHandle, int phyAddr) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ int port = pPortCtrl->portNo; -+ unsigned int regData; -+ -+ regData = MV_REG_READ(ETH_PHY_ADDR_REG(port)); -+ -+ regData &= ~ETH_PHY_ADDR_MASK; -+ regData |= phyAddr; -+ -+ MV_REG_WRITE(ETH_PHY_ADDR_REG(port), regData); -+ -+ return; -+} -+ -+/******************************************************************************* -+* mvEthPhyAddrGet - Get the ethernet port PHY address. -+* -+* DESCRIPTION: -+* This routine returns the given ethernet port PHY address. -+* -+* INPUT: -+* void* pPortHandle - Pointer to port specific handler; -+* -+* -+* RETURN: int - PHY address. -+* -+*******************************************************************************/ -+int mvEthPhyAddrGet(void* pPortHandle) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; -+ int port = pPortCtrl->portNo; -+ unsigned int regData; -+ -+ regData = MV_REG_READ(ETH_PHY_ADDR_REG(port)); -+ -+ return ((regData >> (5 * port)) & 0x1f); -+} -+ -+/******************************************************************************/ -+/* Descriptor handling Functions */ -+/******************************************************************************/ -+ -+/******************************************************************************* -+* etherInitRxDescRing - Curve a Rx chain desc list and buffer in memory. -+* -+* DESCRIPTION: -+* This function prepares a Rx chained list of descriptors and packet -+* buffers in a form of a ring. The routine must be called after port -+* initialization routine and before port start routine. -+* The Ethernet SDMA engine uses CPU bus addresses to access the various -+* devices in the system (i.e. DRAM). This function uses the ethernet -+* struct 'virtual to physical' routine (set by the user) to set the ring -+* with physical addresses. -+* -+* INPUT: -+* ETH_QUEUE_CTRL *pEthPortCtrl Ethernet Port Control srtuct. -+* int rxQueue Number of Rx queue. -+* int rxDescNum Number of Rx descriptors -+* MV_U8* rxDescBaseAddr Rx descriptors memory area base addr. -+* -+* OUTPUT: -+* The routine updates the Ethernet port control struct with information -+* regarding the Rx descriptors and buffers. -+* -+* RETURN: None -+* -+*******************************************************************************/ -+static void ethInitRxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue) -+{ -+ ETH_RX_DESC *pRxDescBase, *pRxDesc, *pRxPrevDesc; -+ int ix, rxDescNum = pPortCtrl->rxQueueConfig[queue].descrNum; -+ ETH_QUEUE_CTRL *pQueueCtrl = &pPortCtrl->rxQueue[queue]; -+ -+ /* Make sure descriptor address is cache line size aligned */ -+ pRxDescBase = (ETH_RX_DESC*)MV_ALIGN_UP((MV_ULONG)pQueueCtrl->descBuf.bufVirtPtr, -+ CPU_D_CACHE_LINE_SIZE); -+ -+ pRxDesc = (ETH_RX_DESC*)pRxDescBase; -+ pRxPrevDesc = pRxDesc; -+ -+ /* initialize the Rx descriptors ring */ -+ for (ix=0; ixbufSize = 0x0; -+ pRxDesc->byteCnt = 0x0; -+ pRxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; -+ pRxDesc->bufPtr = 0x0; -+ pRxDesc->returnInfo = 0x0; -+ pRxPrevDesc = pRxDesc; -+ if(ix == (rxDescNum-1)) -+ { -+ /* Closing Rx descriptors ring */ -+ pRxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pRxDescBase); -+ } -+ else -+ { -+ pRxDesc = (ETH_RX_DESC*)((MV_ULONG)pRxDesc + ETH_RX_DESC_ALIGNED_SIZE); -+ pRxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pRxDesc); -+ } -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxPrevDesc); -+ } -+ -+ pQueueCtrl->pCurrentDescr = pRxDescBase; -+ pQueueCtrl->pUsedDescr = pRxDescBase; -+ -+ pQueueCtrl->pFirstDescr = pRxDescBase; -+ pQueueCtrl->pLastDescr = pRxDesc; -+ pQueueCtrl->resource = 0; -+} -+ -+void ethResetRxDescRing(void* pPortHndl, int queue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->rxQueue[queue]; -+ ETH_RX_DESC* pRxDesc = (ETH_RX_DESC*)pQueueCtrl->pFirstDescr; -+ -+ pQueueCtrl->resource = 0; -+ if(pQueueCtrl->pFirstDescr != NULL) -+ { -+ while(MV_TRUE) -+ { -+ pRxDesc->bufSize = 0x0; -+ pRxDesc->byteCnt = 0x0; -+ pRxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; -+ pRxDesc->bufPtr = 0x0; -+ pRxDesc->returnInfo = 0x0; -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxDesc); -+ if( (void*)pRxDesc == pQueueCtrl->pLastDescr) -+ break; -+ pRxDesc = RX_NEXT_DESC_PTR(pRxDesc, pQueueCtrl); -+ } -+ pQueueCtrl->pCurrentDescr = pQueueCtrl->pFirstDescr; -+ pQueueCtrl->pUsedDescr = pQueueCtrl->pFirstDescr; -+ -+ /* Update RX Command register */ -+ pPortCtrl->portRxQueueCmdReg |= (1 << queue); -+ -+ /* update HW */ -+ MV_REG_WRITE( ETH_RX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), -+ (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); -+ } -+ else -+ { -+ /* Update RX Command register */ -+ pPortCtrl->portRxQueueCmdReg &= ~(1 << queue); -+ -+ /* update HW */ -+ MV_REG_WRITE( ETH_RX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), 0); -+ } -+} -+ -+/******************************************************************************* -+* etherInitTxDescRing - Curve a Tx chain desc list and buffer in memory. -+* -+* DESCRIPTION: -+* This function prepares a Tx chained list of descriptors and packet -+* buffers in a form of a ring. The routine must be called after port -+* initialization routine and before port start routine. -+* The Ethernet SDMA engine uses CPU bus addresses to access the various -+* devices in the system (i.e. DRAM). This function uses the ethernet -+* struct 'virtual to physical' routine (set by the user) to set the ring -+* with physical addresses. -+* -+* INPUT: -+* ETH_PORT_CTRL *pEthPortCtrl Ethernet Port Control srtuct. -+* int txQueue Number of Tx queue. -+* int txDescNum Number of Tx descriptors -+* int txBuffSize Size of Tx buffer -+* MV_U8* pTxDescBase Tx descriptors memory area base addr. -+* -+* OUTPUT: -+* The routine updates the Ethernet port control struct with information -+* regarding the Tx descriptors and buffers. -+* -+* RETURN: None. -+* -+*******************************************************************************/ -+static void ethInitTxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue) -+{ -+ ETH_TX_DESC *pTxDescBase, *pTxDesc, *pTxPrevDesc; -+ int ix, txDescNum = pPortCtrl->txQueueConfig[queue].descrNum; -+ ETH_QUEUE_CTRL *pQueueCtrl = &pPortCtrl->txQueue[queue]; -+ -+ /* Make sure descriptor address is cache line size aligned */ -+ pTxDescBase = (ETH_TX_DESC*)MV_ALIGN_UP((MV_ULONG)pQueueCtrl->descBuf.bufVirtPtr, -+ CPU_D_CACHE_LINE_SIZE); -+ -+ pTxDesc = (ETH_TX_DESC*)pTxDescBase; -+ pTxPrevDesc = pTxDesc; -+ -+ /* initialize the Tx descriptors ring */ -+ for (ix=0; ixbyteCnt = 0x0000; -+ pTxDesc->L4iChk = 0x0000; -+ pTxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; -+ pTxDesc->bufPtr = 0x0; -+ pTxDesc->returnInfo = 0x0; -+ -+ pTxPrevDesc = pTxDesc; -+ -+ if(ix == (txDescNum-1)) -+ { -+ /* Closing Tx descriptors ring */ -+ pTxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pTxDescBase); -+ } -+ else -+ { -+ pTxDesc = (ETH_TX_DESC*)((MV_ULONG)pTxDesc + ETH_TX_DESC_ALIGNED_SIZE); -+ pTxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pTxDesc); -+ } -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxPrevDesc); -+ } -+ -+ pQueueCtrl->pCurrentDescr = pTxDescBase; -+ pQueueCtrl->pUsedDescr = pTxDescBase; -+ -+ pQueueCtrl->pFirstDescr = pTxDescBase; -+ pQueueCtrl->pLastDescr = pTxDesc; -+ /* Leave one TX descriptor out of use */ -+ pQueueCtrl->resource = txDescNum - 1; -+} -+ -+void ethResetTxDescRing(void* pPortHndl, int queue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->txQueue[queue]; -+ ETH_TX_DESC* pTxDesc = (ETH_TX_DESC*)pQueueCtrl->pFirstDescr; -+ -+ pQueueCtrl->resource = 0; -+ if(pQueueCtrl->pFirstDescr != NULL) -+ { -+ while(MV_TRUE) -+ { -+ pTxDesc->byteCnt = 0x0000; -+ pTxDesc->L4iChk = 0x0000; -+ pTxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; -+ pTxDesc->bufPtr = 0x0; -+ pTxDesc->returnInfo = 0x0; -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxDesc); -+ pQueueCtrl->resource++; -+ if( (void*)pTxDesc == pQueueCtrl->pLastDescr) -+ break; -+ pTxDesc = TX_NEXT_DESC_PTR(pTxDesc, pQueueCtrl); -+ } -+ /* Leave one TX descriptor out of use */ -+ pQueueCtrl->resource--; -+ pQueueCtrl->pCurrentDescr = pQueueCtrl->pFirstDescr; -+ pQueueCtrl->pUsedDescr = pQueueCtrl->pFirstDescr; -+ -+ /* Update TX Command register */ -+ pPortCtrl->portTxQueueCmdReg |= MV_32BIT_LE_FAST(1 << queue); -+ /* update HW */ -+ MV_REG_WRITE( ETH_TX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), -+ (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); -+ } -+ else -+ { -+ /* Update TX Command register */ -+ pPortCtrl->portTxQueueCmdReg &= MV_32BIT_LE_FAST(~(1 << queue)); -+ /* update HW */ -+ MV_REG_WRITE( ETH_TX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), 0 ); -+ } -+} -+ -+/******************************************************************************* -+* ethAllocDescrMemory - Free memory allocated for RX and TX descriptors. -+* -+* DESCRIPTION: -+* This function allocates memory for RX and TX descriptors. -+* - If ETH_DESCR_IN_SRAM defined, allocate memory from SRAM. -+* - If ETH_DESCR_IN_SDRAM defined, allocate memory in SDRAM. -+* -+* INPUT: -+* int size - size of memory should be allocated. -+* -+* RETURN: None -+* -+*******************************************************************************/ -+static MV_U8* ethAllocDescrMemory(ETH_PORT_CTRL* pPortCtrl, int descSize, -+ MV_ULONG* pPhysAddr, MV_U32 *memHandle) -+{ -+ MV_U8* pVirt; -+ -+#if defined(ETH_DESCR_IN_SRAM) -+ if(ethDescInSram == MV_TRUE) -+ pVirt = (char*)mvSramMalloc(descSize, pPhysAddr); -+ else -+#endif /* ETH_DESCR_IN_SRAM */ -+ { -+#ifdef ETH_DESCR_UNCACHED -+ pVirt = (MV_U8*)mvOsIoUncachedMalloc(pPortCtrl->osHandle, descSize, -+ pPhysAddr,memHandle); -+#else -+ pVirt = (MV_U8*)mvOsIoCachedMalloc(pPortCtrl->osHandle, descSize, -+ pPhysAddr, memHandle); -+#endif /* ETH_DESCR_UNCACHED */ -+ } -+ memset(pVirt, 0, descSize); -+ -+ return pVirt; -+} -+ -+/******************************************************************************* -+* ethFreeDescrMemory - Free memory allocated for RX and TX descriptors. -+* -+* DESCRIPTION: -+* This function frees memory allocated for RX and TX descriptors. -+* - If ETH_DESCR_IN_SRAM defined, free memory using gtSramFree() function. -+* - If ETH_DESCR_IN_SDRAM defined, free memory using mvOsFree() function. -+* -+* INPUT: -+* void* pVirtAddr - virtual pointer to memory allocated for RX and TX -+* desriptors. -+* -+* RETURN: None -+* -+*******************************************************************************/ -+void ethFreeDescrMemory(ETH_PORT_CTRL* pPortCtrl, MV_BUF_INFO* pDescBuf) -+{ -+ if( (pDescBuf == NULL) || (pDescBuf->bufVirtPtr == NULL) ) -+ return; -+ -+#if defined(ETH_DESCR_IN_SRAM) -+ if( ethDescInSram ) -+ { -+ mvSramFree(pDescBuf->bufSize, pDescBuf->bufPhysAddr, pDescBuf->bufVirtPtr); -+ return; -+ } -+#endif /* ETH_DESCR_IN_SRAM */ -+ -+#ifdef ETH_DESCR_UNCACHED -+ mvOsIoUncachedFree(pPortCtrl->osHandle, pDescBuf->bufSize, pDescBuf->bufPhysAddr, -+ pDescBuf->bufVirtPtr,pDescBuf->memHandle); -+#else -+ mvOsIoCachedFree(pPortCtrl->osHandle, pDescBuf->bufSize, pDescBuf->bufPhysAddr, -+ pDescBuf->bufVirtPtr,pDescBuf->memHandle); -+#endif /* ETH_DESCR_UNCACHED */ -+} -+ -+/******************************************************************************/ -+/* Other Functions */ -+/******************************************************************************/ -+ -+void mvEthPortPowerUp(int port) -+{ -+ MV_U32 regVal; -+ -+ /* MAC Cause register should be cleared */ -+ MV_REG_WRITE(ETH_UNIT_INTR_CAUSE_REG(port), 0); -+ -+ if (mvBoardIsPortInSgmii(port)) -+ mvEthPortSgmiiConfig(port); -+ -+ /* Cancel Port Reset */ -+ regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)); -+ regVal &= (~ETH_PORT_RESET_MASK); -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal); -+ while( (MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)) & ETH_PORT_RESET_MASK) != 0); -+} -+ -+void mvEthPortPowerDown(int port) -+{ -+ MV_U32 regVal; -+ -+ /* Port must be DISABLED */ -+ regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port)); -+ if( (regVal & ETH_PORT_ENABLE_MASK) != 0) -+ { -+ mvOsPrintf("ethPort #%d: PowerDown - port must be Disabled (PSC=0x%x)\n", -+ port, regVal); -+ return; -+ } -+ -+ /* Port Reset (Read after write the register as a precaution) */ -+ regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)); -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal | ETH_PORT_RESET_MASK); -+ while((MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)) & ETH_PORT_RESET_MASK) == 0); -+} -+ -+static void mvEthPortSgmiiConfig(int port) -+{ -+ MV_U32 regVal; -+ -+ regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)); -+ -+ regVal |= (ETH_SGMII_MODE_MASK /*| ETH_INBAND_AUTO_NEG_ENABLE_MASK */); -+ regVal &= (~ETH_INBAND_AUTO_NEG_BYPASS_MASK); -+ -+ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal); -+} -+ -+ -+ -+ -+ -+ -+ -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,748 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+/******************************************************************************* -+* mvEthDebug.c - Source file for user friendly debug functions -+* -+* DESCRIPTION: -+* -+* DEPENDENCIES: -+* None. -+* -+*******************************************************************************/ -+ -+#include "mvOs.h" -+#include "mvCommon.h" -+#include "mvTypes.h" -+#include "mv802_3.h" -+#include "mvDebug.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "eth-phy/mvEthPhy.h" -+#include "eth/mvEth.h" -+#include "eth/gbe/mvEthDebug.h" -+ -+/* #define mvOsPrintf printf */ -+ -+void mvEthPortShow(void* pHndl); -+void mvEthQueuesShow(void* pHndl, int rxQueue, int txQueue, int mode); -+ -+/******************************************************************************/ -+/* Debug functions */ -+/******************************************************************************/ -+void ethRxCoal(int port, int usec) -+{ -+ void* pHndl; -+ -+ pHndl = mvEthPortHndlGet(port); -+ if(pHndl != NULL) -+ { -+ mvEthRxCoalSet(pHndl, usec); -+ } -+} -+ -+void ethTxCoal(int port, int usec) -+{ -+ void* pHndl; -+ -+ pHndl = mvEthPortHndlGet(port); -+ if(pHndl != NULL) -+ { -+ mvEthTxCoalSet(pHndl, usec); -+ } -+} -+ -+#if (MV_ETH_VERSION >= 4) -+void ethEjpModeSet(int port, int mode) -+{ -+ void* pHndl; -+ -+ pHndl = mvEthPortHndlGet(port); -+ if(pHndl != NULL) -+ { -+ mvEthEjpModeSet(pHndl, mode); -+ } -+} -+#endif /* (MV_ETH_VERSION >= 4) */ -+ -+void ethBpduRxQ(int port, int bpduQueue) -+{ -+ void* pHndl; -+ -+ pHndl = mvEthPortHndlGet(port); -+ if(pHndl != NULL) -+ { -+ mvEthBpduRxQueue(pHndl, bpduQueue); -+ } -+} -+ -+void ethArpRxQ(int port, int arpQueue) -+{ -+ void* pHndl; -+ -+ pHndl = mvEthPortHndlGet(port); -+ if(pHndl != NULL) -+ { -+ mvEthArpRxQueue(pHndl, arpQueue); -+ } -+} -+ -+void ethTcpRxQ(int port, int tcpQueue) -+{ -+ void* pHndl; -+ -+ pHndl = mvEthPortHndlGet(port); -+ if(pHndl != NULL) -+ { -+ mvEthTcpRxQueue(pHndl, tcpQueue); -+ } -+} -+ -+void ethUdpRxQ(int port, int udpQueue) -+{ -+ void* pHndl; -+ -+ pHndl = mvEthPortHndlGet(port); -+ if(pHndl != NULL) -+ { -+ mvEthUdpRxQueue(pHndl, udpQueue); -+ } -+} -+ -+void ethTxPolicyRegs(int port) -+{ -+ int queue; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)mvEthPortHndlGet(port); -+ -+ if(pPortCtrl == NULL) -+ { -+ return; -+ } -+ mvOsPrintf("Port #%d TX Policy: EJP=%d, TXQs: ", -+ port, pPortCtrl->portConfig.ejpMode); -+ for(queue=0; queuetxQueueConfig[queue].descrNum > 0) -+ mvOsPrintf("%d, ", queue); -+ } -+ mvOsPrintf("\n"); -+ -+ mvOsPrintf("\n\t TX policy Port #%d configuration registers\n", port); -+ -+ mvOsPrintf("ETH_TX_QUEUE_COMMAND_REG : 0x%X = 0x%08x\n", -+ ETH_TX_QUEUE_COMMAND_REG(port), -+ MV_REG_READ( ETH_TX_QUEUE_COMMAND_REG(port) ) ); -+ -+ mvOsPrintf("ETH_TX_FIXED_PRIO_CFG_REG : 0x%X = 0x%08x\n", -+ ETH_TX_FIXED_PRIO_CFG_REG(port), -+ MV_REG_READ( ETH_TX_FIXED_PRIO_CFG_REG(port) ) ); -+ -+ mvOsPrintf("ETH_TX_TOKEN_RATE_CFG_REG : 0x%X = 0x%08x\n", -+ ETH_TX_TOKEN_RATE_CFG_REG(port), -+ MV_REG_READ( ETH_TX_TOKEN_RATE_CFG_REG(port) ) ); -+ -+ mvOsPrintf("ETH_MAX_TRANSMIT_UNIT_REG : 0x%X = 0x%08x\n", -+ ETH_MAX_TRANSMIT_UNIT_REG(port), -+ MV_REG_READ( ETH_MAX_TRANSMIT_UNIT_REG(port) ) ); -+ -+ mvOsPrintf("ETH_TX_TOKEN_BUCKET_SIZE_REG : 0x%X = 0x%08x\n", -+ ETH_TX_TOKEN_BUCKET_SIZE_REG(port), -+ MV_REG_READ( ETH_TX_TOKEN_BUCKET_SIZE_REG(port) ) ); -+ -+ mvOsPrintf("ETH_TX_TOKEN_BUCKET_COUNT_REG : 0x%X = 0x%08x\n", -+ ETH_TX_TOKEN_BUCKET_COUNT_REG(port), -+ MV_REG_READ( ETH_TX_TOKEN_BUCKET_COUNT_REG(port) ) ); -+ -+ for(queue=0; queue> 24) & 0xff), ((macH >> 16) & 0xff), -+ ((macH >> 8) & 0xff), (macH & 0xff), -+ ((macL >> 8) & 0xff), (macL & 0xff) ); -+ -+ for (i=0; i<4; i++) -+ { -+ unicastReg = MV_REG_READ( (ETH_DA_FILTER_UCAST_BASE(port) + i*4)); -+ for(j=0; j<4; j++) -+ { -+ MV_U8 macEntry = (unicastReg >> (8*j)) & 0xFF; -+ -+ mvOsPrintf("%X: %8s, Q = %d\n", i*4+j, -+ (macEntry & BIT0) ? "Accept" : "Reject", (macEntry >> 1) & 0x7); -+ } -+ } -+} -+ -+void ethMcastAdd(int port, char* macStr, int queue) -+{ -+ void* pHndl; -+ MV_U8 macAddr[MV_MAC_ADDR_SIZE]; -+ -+ pHndl = mvEthPortHndlGet(port); -+ if(pHndl != NULL) -+ { -+ mvMacStrToHex(macStr, macAddr); -+ mvEthMcastAddrSet(pHndl, macAddr, queue); -+ } -+} -+ -+void ethPortMcast(int port) -+{ -+ int tblIdx, regIdx; -+ MV_U32 regVal; -+ -+ mvOsPrintf("\n\t Port #%d Special (IP) Multicast table: 01:00:5E:00:00:XX\n\n", -+ port); -+ -+ for(tblIdx=0; tblIdx<(256/4); tblIdx++) -+ { -+ regVal = MV_REG_READ((ETH_DA_FILTER_SPEC_MCAST_BASE(port) + tblIdx*4)); -+ for(regIdx=0; regIdx<4; regIdx++) -+ { -+ if((regVal & (0x01 << (regIdx*8))) != 0) -+ { -+ mvOsPrintf("0x%02X: Accepted, rxQ = %d\n", -+ tblIdx*4+regIdx, ((regVal >> (regIdx*8+1)) & 0x07)); -+ } -+ } -+ } -+ mvOsPrintf("\n\t Port #%d Other Multicast table\n\n", port); -+ for(tblIdx=0; tblIdx<(256/4); tblIdx++) -+ { -+ regVal = MV_REG_READ((ETH_DA_FILTER_OTH_MCAST_BASE(port) + tblIdx*4)); -+ for(regIdx=0; regIdx<4; regIdx++) -+ { -+ if((regVal & (0x01 << (regIdx*8))) != 0) -+ { -+ mvOsPrintf("Crc8=0x%02X: Accepted, rxQ = %d\n", -+ tblIdx*4+regIdx, ((regVal >> (regIdx*8+1)) & 0x07)); -+ } -+ } -+ } -+} -+ -+ -+/* Print status of Ethernet port */ -+void mvEthPortShow(void* pHndl) -+{ -+ MV_U32 regValue, rxCoal, txCoal; -+ int speed, queue, port; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pHndl; -+ -+ port = pPortCtrl->portNo; -+ -+ regValue = MV_REG_READ( ETH_PORT_STATUS_REG(port) ); -+ -+ mvOsPrintf("\n\t ethGiga #%d port Status: 0x%04x = 0x%08x\n\n", -+ port, ETH_PORT_STATUS_REG(port), regValue); -+ -+ mvOsPrintf("descInSram=%d, descSwCoher=%d\n", -+ ethDescInSram, ethDescSwCoher); -+ -+ if(regValue & ETH_GMII_SPEED_1000_MASK) -+ speed = 1000; -+ else if(regValue & ETH_MII_SPEED_100_MASK) -+ speed = 100; -+ else -+ speed = 10; -+ -+ mvEthCoalGet(pPortCtrl, &rxCoal, &txCoal); -+ -+ /* Link, Speed, Duplex, FlowControl */ -+ mvOsPrintf("Link=%s, Speed=%d, Duplex=%s, RxFlowControl=%s", -+ (regValue & ETH_LINK_UP_MASK) ? "UP" : "DOWN", -+ speed, -+ (regValue & ETH_FULL_DUPLEX_MASK) ? "FULL" : "HALF", -+ (regValue & ETH_ENABLE_RCV_FLOW_CTRL_MASK) ? "ENABLE" : "DISABLE"); -+ -+ mvOsPrintf("\n"); -+ -+ mvOsPrintf("RxCoal = %d usec, TxCoal = %d usec\n", -+ rxCoal, txCoal); -+ -+ mvOsPrintf("rxDefQ=%d, arpQ=%d, bpduQ=%d, tcpQ=%d, udpQ=%d\n\n", -+ pPortCtrl->portConfig.rxDefQ, pPortCtrl->portConfig.rxArpQ, -+ pPortCtrl->portConfig.rxBpduQ, -+ pPortCtrl->portConfig.rxTcpQ, pPortCtrl->portConfig.rxUdpQ); -+ -+ /* Print all RX and TX queues */ -+ for(queue=0; queuerxQueue[queue].pFirstDescr, -+ mvEthRxResourceGet(pPortCtrl, queue) ); -+ } -+ mvOsPrintf("\n"); -+ for(queue=0; queuetxQueue[queue].pFirstDescr, -+ mvEthTxResourceGet(pPortCtrl, queue) ); -+ } -+} -+ -+/* Print RX and TX queue of the Ethernet port */ -+void mvEthQueuesShow(void* pHndl, int rxQueue, int txQueue, int mode) -+{ -+ ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL*)pHndl; -+ ETH_QUEUE_CTRL *pQueueCtrl; -+ MV_U32 regValue; -+ ETH_RX_DESC *pRxDescr; -+ ETH_TX_DESC *pTxDescr; -+ int i, port = pPortCtrl->portNo; -+ -+ if( (rxQueue >=0) && (rxQueue < MV_ETH_RX_Q_NUM) ) -+ { -+ pQueueCtrl = &(pPortCtrl->rxQueue[rxQueue]); -+ mvOsPrintf("Port #%d, RX Queue #%d\n\n", port, rxQueue); -+ -+ mvOsPrintf("CURR_RX_DESC_PTR : 0x%X = 0x%08x\n", -+ ETH_RX_CUR_DESC_PTR_REG(port, rxQueue), -+ MV_REG_READ( ETH_RX_CUR_DESC_PTR_REG(port, rxQueue))); -+ -+ -+ if(pQueueCtrl->pFirstDescr != NULL) -+ { -+ mvOsPrintf("pFirstDescr=0x%lx, pLastDescr=0x%lx, numOfResources=%d\n", -+ (MV_ULONG)pQueueCtrl->pFirstDescr, (MV_ULONG)pQueueCtrl->pLastDescr, -+ pQueueCtrl->resource); -+ mvOsPrintf("pCurrDescr: 0x%lx, pUsedDescr: 0x%lx\n", -+ (MV_ULONG)pQueueCtrl->pCurrentDescr, -+ (MV_ULONG)pQueueCtrl->pUsedDescr); -+ -+ if(mode == 1) -+ { -+ pRxDescr = (ETH_RX_DESC*)pQueueCtrl->pFirstDescr; -+ i = 0; -+ do -+ { -+ mvOsPrintf("%3d. desc=%08x (%08x), cmd=%08x, data=%4d, buf=%4d, buf=%08x, pkt=%lx, os=%lx\n", -+ i, (MV_U32)pRxDescr, (MV_U32)ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pRxDescr), -+ pRxDescr->cmdSts, pRxDescr->byteCnt, (MV_U32)pRxDescr->bufSize, -+ (unsigned int)pRxDescr->bufPtr, (MV_ULONG)pRxDescr->returnInfo, -+ ((MV_PKT_INFO*)pRxDescr->returnInfo)->osInfo); -+ -+ ETH_DESCR_INV(pPortCtrl, pRxDescr); -+ pRxDescr = RX_NEXT_DESC_PTR(pRxDescr, pQueueCtrl); -+ i++; -+ } while (pRxDescr != pQueueCtrl->pFirstDescr); -+ } -+ } -+ else -+ mvOsPrintf("RX Queue #%d is NOT CREATED\n", rxQueue); -+ } -+ -+ if( (txQueue >=0) && (txQueue < MV_ETH_TX_Q_NUM) ) -+ { -+ pQueueCtrl = &(pPortCtrl->txQueue[txQueue]); -+ mvOsPrintf("Port #%d, TX Queue #%d\n\n", port, txQueue); -+ -+ regValue = MV_REG_READ( ETH_TX_CUR_DESC_PTR_REG(port, txQueue)); -+ mvOsPrintf("CURR_TX_DESC_PTR : 0x%X = 0x%08x\n", -+ ETH_TX_CUR_DESC_PTR_REG(port, txQueue), regValue); -+ -+ if(pQueueCtrl->pFirstDescr != NULL) -+ { -+ mvOsPrintf("pFirstDescr=0x%lx, pLastDescr=0x%lx, numOfResources=%d\n", -+ (MV_ULONG)pQueueCtrl->pFirstDescr, -+ (MV_ULONG)pQueueCtrl->pLastDescr, -+ pQueueCtrl->resource); -+ mvOsPrintf("pCurrDescr: 0x%lx, pUsedDescr: 0x%lx\n", -+ (MV_ULONG)pQueueCtrl->pCurrentDescr, -+ (MV_ULONG)pQueueCtrl->pUsedDescr); -+ -+ if(mode == 1) -+ { -+ pTxDescr = (ETH_TX_DESC*)pQueueCtrl->pFirstDescr; -+ i = 0; -+ do -+ { -+ mvOsPrintf("%3d. desc=%08x (%08x), cmd=%08x, data=%4d, buf=%08x, pkt=%lx, os=%lx\n", -+ i, (MV_U32)pTxDescr, (MV_U32)ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pTxDescr), -+ pTxDescr->cmdSts, pTxDescr->byteCnt, -+ (MV_U32)pTxDescr->bufPtr, (MV_ULONG)pTxDescr->returnInfo, -+ pTxDescr->returnInfo ? (((MV_PKT_INFO*)pTxDescr->returnInfo)->osInfo) : 0x0); -+ -+ ETH_DESCR_INV(pPortCtrl, pTxDescr); -+ pTxDescr = TX_NEXT_DESC_PTR(pTxDescr, pQueueCtrl); -+ i++; -+ } while (pTxDescr != pQueueCtrl->pFirstDescr); -+ } -+ } -+ else -+ mvOsPrintf("TX Queue #%d is NOT CREATED\n", txQueue); -+ } -+} -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,146 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#ifndef __MV_ETH_DEBUG_H__ -+#define __MV_ETH_DEBUG_H__ -+ -+#if 0 -+/* -+ ** Externs -+ */ -+void ethBpduRxQ(int port, int bpduQueue); -+void ethArpRxQ(int port, int bpduQueue); -+void ethTcpRxQ(int port, int bpduQueue); -+void ethUdpRxQ(int port, int bpduQueue); -+void ethMcastAdd(int port, char* macStr, int queue); -+ -+#ifdef INCLUDE_MULTI_QUEUE -+void ethRxPolicy( int port); -+void ethTxPolicy( int port); -+void ethTxPolDA(int port, char* macStr, int txQ, char* headerHexStr); -+void ethRxPolMode(int port, MV_ETH_PRIO_MODE prioMode); -+void ethRxPolQ(int port, int rxQueue, int rxQuota); -+#endif /* INCLUDE_MULTI_QUEUE */ -+ -+void print_egiga_stat(void *sc, unsigned int port); -+void ethPortStatus (int port); -+void ethPortQueues( int port, int rxQueue, int txQueue, int mode); -+void ethPortMcast(int port); -+void ethPortRegs(int port); -+void ethPortCounters(int port); -+void ethPortRmonCounters(int port); -+void ethRxCoal(int port, int usec); -+void ethTxCoal(int port, int usec); -+ -+void ethRegs(int port); -+void ethClearCounters(int port); -+void ethUcastSet(int port, char* macStr, int queue); -+void ethPortUcastShow(int port); -+ -+#ifdef CONFIG_MV_ETH_HEADER -+void run_com_header(const char *buffer); -+#endif -+ -+#ifdef INCLUDE_MULTI_QUEUE -+void ethRxPolMode(int port, MV_ETH_PRIO_MODE prioMode); -+void ethRxPolQ(int port, int queue, int quota); -+void ethRxPolicy(int port); -+void ethTxPolDef(int port, int txQ, char* headerHexStr); -+void ethTxPolDA(int port, char* macStr, int txQ, char* headerHexStr); -+void ethTxPolicy(int port); -+#endif /* INCLUDE_MULTI_QUEUE */ -+ -+#if (MV_ETH_VERSION >= 4) -+void ethEjpModeSet(int port, int mode) -+#endif -+#endif /* 0 */ -+ -+ -+ -+ -+void ethRxCoal(int port, int usec); -+void ethTxCoal(int port, int usec); -+#if (MV_ETH_VERSION >= 4) -+void ethEjpModeSet(int port, int mode); -+#endif /* (MV_ETH_VERSION >= 4) */ -+ -+void ethBpduRxQ(int port, int bpduQueue); -+void ethArpRxQ(int port, int arpQueue); -+void ethTcpRxQ(int port, int tcpQueue); -+void ethUdpRxQ(int port, int udpQueue); -+void ethTxPolicyRegs(int port); -+void ethPortRegs(int port); -+void ethRegs(int port); -+void ethClearCounters(int port); -+void ethPortCounters(int port); -+void ethPortRmonCounters(int port); -+void ethPortStatus(int port); -+void ethPortQueues(int port, int rxQueue, int txQueue, int mode); -+void ethUcastSet(int port, char* macStr, int queue); -+void ethPortUcastShow(int port); -+void ethMcastAdd(int port, char* macStr, int queue); -+void ethPortMcast(int port); -+void mvEthPortShow(void* pHndl); -+void mvEthQueuesShow(void* pHndl, int rxQueue, int txQueue, int mode); -+ -+#endif -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthGbe.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthGbe.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthGbe.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthGbe.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,751 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+/******************************************************************************* -+* mvEth.h - Header File for : Marvell Gigabit Ethernet Controller -+* -+* DESCRIPTION: -+* This header file contains macros typedefs and function declaration specific to -+* the Marvell Gigabit Ethernet Controller. -+* -+* DEPENDENCIES: -+* None. -+* -+*******************************************************************************/ -+ -+#ifndef __mvEthGbe_h__ -+#define __mvEthGbe_h__ -+ -+extern MV_BOOL ethDescInSram; -+extern MV_BOOL ethDescSwCoher; -+extern ETH_PORT_CTRL* ethPortCtrl[]; -+ -+static INLINE MV_ULONG ethDescVirtToPhy(ETH_QUEUE_CTRL* pQueueCtrl, MV_U8* pDesc) -+{ -+#if defined (ETH_DESCR_IN_SRAM) -+ if( ethDescInSram ) -+ return mvSramVirtToPhy(pDesc); -+ else -+#endif /* ETH_DESCR_IN_SRAM */ -+ return (pQueueCtrl->descBuf.bufPhysAddr + (pDesc - pQueueCtrl->descBuf.bufVirtPtr)); -+} -+/* Return port handler */ -+#define mvEthPortHndlGet(port) ethPortCtrl[port] -+ -+/* Used as WA for HW/SW race on TX */ -+static INLINE int mvEthPortTxEnable(void* pPortHndl, int queue, int max_deep) -+{ -+ int deep = 0; -+ MV_U32 txCurrReg, txEnReg; -+ ETH_TX_DESC* pTxLastDesc; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ -+ txEnReg = MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)); -+ if( (txEnReg & MV_32BIT_LE_FAST(ETH_TXQ_ENABLE_MASK)) == 0) -+ { -+ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) = pPortCtrl->portTxQueueCmdReg; -+ return 0; -+ } -+ -+ pQueueCtrl = &pPortCtrl->txQueue[queue]; -+ pTxLastDesc = pQueueCtrl->pCurrentDescr; -+ txCurrReg = MV_REG_READ(ETH_TX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue)); -+ if(ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pTxLastDesc) == txCurrReg) -+ { -+ /* All descriptors are processed, no chance for race */ -+ return 0; -+ } -+ -+ /* Check distance betwee HW and SW location: */ -+ /* If distance between HW and SW pointers is less than max_deep descriptors */ -+ /* Race condition is possible, so wait end of TX and restart TXQ */ -+ while(deep < max_deep) -+ { -+ pTxLastDesc = TX_PREV_DESC_PTR(pTxLastDesc, pQueueCtrl); -+ if(ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pTxLastDesc) == txCurrReg) -+ { -+ int count = 0; -+ -+ while( (txEnReg & MV_32BIT_LE_FAST(ETH_TXQ_ENABLE_MASK)) != 0) -+ { -+ count++; -+ if(count > 10000) -+ { -+ mvOsPrintf("mvEthPortTxEnable: timeout - TXQ_CMD=0x%08x\n", -+ MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) ); -+ break; -+ } -+ txEnReg = MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)); -+ } -+ -+ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) = pPortCtrl->portTxQueueCmdReg; -+ return count; -+ } -+ deep++; -+ } -+ /* Distance between HW and SW pointers is more than max_deep descriptors, */ -+ /* So NO race condition - do nothing */ -+ return -1; -+} -+ -+ -+/* defines */ -+#define ETH_CSUM_MIN_BYTE_COUNT 72 -+ -+/* Tailgate and Kirwood have only 2K TX FIFO */ -+#if (MV_ETH_VERSION == 2) || (MV_ETH_VERSION == 4) -+#define ETH_CSUM_MAX_BYTE_COUNT 1600 -+#else -+#define ETH_CSUM_MAX_BYTE_COUNT 9*1024 -+#endif /* MV_ETH_VERSION */ -+ -+#define ETH_MV_HEADER_SIZE 2 -+#define ETH_MV_TX_EN -+ -+/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */ -+#define MIN_TX_BUFF_LOAD 8 -+#define TX_BUF_OFFSET_IN_DESC (ETH_TX_DESC_ALIGNED_SIZE - MIN_TX_BUFF_LOAD) -+ -+/* Default port configuration value */ -+#define PORT_CONFIG_VALUE \ -+ ETH_DEF_RX_QUEUE_MASK(0) | \ -+ ETH_DEF_RX_ARP_QUEUE_MASK(0) | \ -+ ETH_DEF_RX_TCP_QUEUE_MASK(0) | \ -+ ETH_DEF_RX_UDP_QUEUE_MASK(0) | \ -+ ETH_DEF_RX_BPDU_QUEUE_MASK(0) | \ -+ ETH_RX_CHECKSUM_WITH_PSEUDO_HDR -+ -+/* Default port extend configuration value */ -+#define PORT_CONFIG_EXTEND_VALUE 0 -+ -+#define PORT_SERIAL_CONTROL_VALUE \ -+ ETH_DISABLE_FC_AUTO_NEG_MASK | \ -+ BIT9 | \ -+ ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ -+ ETH_MAX_RX_PACKET_1552BYTE | \ -+ ETH_SET_FULL_DUPLEX_MASK -+ -+#define PORT_SERIAL_CONTROL_100MB_FORCE_VALUE \ -+ ETH_FORCE_LINK_PASS_MASK | \ -+ ETH_DISABLE_DUPLEX_AUTO_NEG_MASK | \ -+ ETH_DISABLE_FC_AUTO_NEG_MASK | \ -+ BIT9 | \ -+ ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ -+ ETH_DISABLE_SPEED_AUTO_NEG_MASK | \ -+ ETH_SET_FULL_DUPLEX_MASK | \ -+ ETH_SET_MII_SPEED_100_MASK | \ -+ ETH_MAX_RX_PACKET_1552BYTE -+ -+ -+#define PORT_SERIAL_CONTROL_1000MB_FORCE_VALUE \ -+ ETH_FORCE_LINK_PASS_MASK | \ -+ ETH_DISABLE_DUPLEX_AUTO_NEG_MASK | \ -+ ETH_DISABLE_FC_AUTO_NEG_MASK | \ -+ BIT9 | \ -+ ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ -+ ETH_DISABLE_SPEED_AUTO_NEG_MASK | \ -+ ETH_SET_FULL_DUPLEX_MASK | \ -+ ETH_SET_GMII_SPEED_1000_MASK | \ -+ ETH_MAX_RX_PACKET_1552BYTE -+ -+#define PORT_SERIAL_CONTROL_SGMII_IBAN_VALUE \ -+ ETH_DISABLE_FC_AUTO_NEG_MASK | \ -+ BIT9 | \ -+ ETH_IN_BAND_AN_EN_MASK | \ -+ ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ -+ ETH_MAX_RX_PACKET_1552BYTE -+ -+/* Function headers: */ -+MV_VOID mvEthSetSpecialMcastTable(int portNo, int queue); -+MV_STATUS mvEthArpRxQueue(void* pPortHandle, int arpQueue); -+MV_STATUS mvEthUdpRxQueue(void* pPortHandle, int udpQueue); -+MV_STATUS mvEthTcpRxQueue(void* pPortHandle, int tcpQueue); -+MV_STATUS mvEthMacAddrGet(int portNo, unsigned char *pAddr); -+MV_VOID mvEthSetOtherMcastTable(int portNo, int queue); -+MV_STATUS mvEthHeaderModeSet(void* pPortHandle, MV_ETH_HEADER_MODE headerMode); -+/* Interrupt Coalesting functions */ -+MV_U32 mvEthRxCoalSet(void* pPortHndl, MV_U32 uSec); -+MV_U32 mvEthTxCoalSet(void* pPortHndl, MV_U32 uSec); -+MV_STATUS mvEthCoalGet(void* pPortHndl, MV_U32* pRxCoal, MV_U32* pTxCoal); -+ -+/******************************************************************************/ -+/* Data Flow functions */ -+/******************************************************************************/ -+static INLINE void mvEthPortTxRestart(void* pPortHndl) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ -+ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) = pPortCtrl->portTxQueueCmdReg; -+} -+ -+/* Get number of Free resources in specific TX queue */ -+static INLINE int mvEthTxResourceGet(void* pPortHndl, int txQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ -+ return (pPortCtrl->txQueue[txQueue].resource); -+} -+ -+/* Get number of Free resources in specific RX queue */ -+static INLINE int mvEthRxResourceGet(void* pPortHndl, int rxQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ -+ return (pPortCtrl->rxQueue[rxQueue].resource); -+} -+ -+static INLINE int mvEthTxQueueIsFull(void* pPortHndl, int txQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ -+ if(pPortCtrl->txQueue[txQueue].resource == 0) -+ return MV_TRUE; -+ -+ return MV_FALSE; -+} -+ -+/* Get number of Free resources in specific RX queue */ -+static INLINE int mvEthRxQueueIsFull(void* pPortHndl, int rxQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->rxQueue[rxQueue]; -+ -+ if( (pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) && -+ (pQueueCtrl->resource != 0) ) -+ return MV_TRUE; -+ -+ return MV_FALSE; -+} -+ -+static INLINE int mvEthTxQueueIsEmpty(void* pPortHndl, int txQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->txQueue[txQueue]; -+ -+ if( (pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) && -+ (pQueueCtrl->resource != 0) ) -+ { -+ return MV_TRUE; -+ } -+ return MV_FALSE; -+} -+ -+/* Get number of Free resources in specific RX queue */ -+static INLINE int mvEthRxQueueIsEmpty(void* pPortHndl, int rxQueue) -+{ -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; -+ -+ if(pPortCtrl->rxQueue[rxQueue].resource == 0) -+ return MV_TRUE; -+ -+ return MV_FALSE; -+} -+ -+/******************************************************************************* -+* mvEthPortTx - Send an Ethernet packet -+* -+* DESCRIPTION: -+* This routine send a given packet described by pPktInfo parameter. -+* Single buffer only. -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet Port handler. -+* int txQueue - Number of Tx queue. -+* MV_PKT_INFO *pPktInfo - User packet to send. -+* -+* RETURN: -+* MV_NO_RESOURCE - No enough resources to send this packet. -+* MV_ERROR - Unexpected Fatal error. -+* MV_OK - Packet send successfully. -+* -+*******************************************************************************/ -+static INLINE MV_STATUS mvEthPortTx(void* pEthPortHndl, int txQueue, MV_PKT_INFO* pPktInfo) -+{ -+ ETH_TX_DESC* pTxCurrDesc; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ int portNo; -+ MV_BUF_INFO* pBufInfo = pPktInfo->pFrags; -+ -+#ifdef ETH_DEBUG -+ if(pPortCtrl->portState != MV_ACTIVE) -+ return MV_BAD_STATE; -+#endif /* ETH_DEBUG */ -+ -+ portNo = pPortCtrl->portNo; -+ pQueueCtrl = &pPortCtrl->txQueue[txQueue]; -+ -+ /* Get the Tx Desc ring indexes */ -+ pTxCurrDesc = pQueueCtrl->pCurrentDescr; -+ -+ /* Check if there is enough resources to send the packet */ -+ if(pQueueCtrl->resource == 0) -+ return MV_NO_RESOURCE; -+ -+ pTxCurrDesc->byteCnt = pBufInfo->dataSize; -+ -+ /* Flash Buffer */ -+ if(pPktInfo->pktSize != 0) -+ { -+#ifdef MV_NETBSD -+ pTxCurrDesc->bufPtr = pBufInfo->bufPhysAddr; -+ ETH_PACKET_CACHE_FLUSH(pBufInfo->bufVirtPtr, pPktInfo->pktSize); -+#else -+ pTxCurrDesc->bufPtr = ETH_PACKET_CACHE_FLUSH(pBufInfo->bufVirtPtr, pPktInfo->pktSize); -+#endif -+ pPktInfo->pktSize = 0; -+ } -+ else -+ pTxCurrDesc->bufPtr = pBufInfo->bufPhysAddr; -+ -+ pTxCurrDesc->returnInfo = (MV_ULONG)pPktInfo; -+ -+ /* There is only one buffer in the packet */ -+ /* The OSG might set some bits for checksum offload, so add them to first descriptor */ -+ pTxCurrDesc->cmdSts = pPktInfo->status | -+ ETH_BUFFER_OWNED_BY_DMA | -+ ETH_TX_GENERATE_CRC_MASK | -+ ETH_TX_ENABLE_INTERRUPT_MASK | -+ ETH_TX_ZERO_PADDING_MASK | -+ ETH_TX_FIRST_DESC_MASK | -+ ETH_TX_LAST_DESC_MASK; -+ -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); -+ -+ pQueueCtrl->resource--; -+ pQueueCtrl->pCurrentDescr = TX_NEXT_DESC_PTR(pTxCurrDesc, pQueueCtrl); -+ -+ /* Apply send command */ -+ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(portNo)) = pPortCtrl->portTxQueueCmdReg; -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvEthPortSgTx - Send an Ethernet packet -+* -+* DESCRIPTION: -+* This routine send a given packet described by pBufInfo parameter. It -+* supports transmitting of a packet spaned over multiple buffers. -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet Port handler. -+* int txQueue - Number of Tx queue. -+* MV_PKT_INFO *pPktInfo - User packet to send. -+* -+* RETURN: -+* MV_NO_RESOURCE - No enough resources to send this packet. -+* MV_ERROR - Unexpected Fatal error. -+* MV_OK - Packet send successfully. -+* -+*******************************************************************************/ -+static INLINE MV_STATUS mvEthPortSgTx(void* pEthPortHndl, int txQueue, MV_PKT_INFO* pPktInfo) -+{ -+ ETH_TX_DESC* pTxFirstDesc; -+ ETH_TX_DESC* pTxCurrDesc; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ int portNo, bufCount; -+ MV_BUF_INFO* pBufInfo = pPktInfo->pFrags; -+ MV_U8* pTxBuf; -+ -+#ifdef ETH_DEBUG -+ if(pPortCtrl->portState != MV_ACTIVE) -+ return MV_BAD_STATE; -+#endif /* ETH_DEBUG */ -+ -+ portNo = pPortCtrl->portNo; -+ pQueueCtrl = &pPortCtrl->txQueue[txQueue]; -+ -+ /* Get the Tx Desc ring indexes */ -+ pTxCurrDesc = pQueueCtrl->pCurrentDescr; -+ -+ /* Check if there is enough resources to send the packet */ -+ if(pQueueCtrl->resource < pPktInfo->numFrags) -+ return MV_NO_RESOURCE; -+ -+ /* Remember first desc */ -+ pTxFirstDesc = pTxCurrDesc; -+ -+ bufCount = 0; -+ while(MV_TRUE) -+ { -+ if(pBufInfo[bufCount].dataSize <= MIN_TX_BUFF_LOAD) -+ { -+ /* Buffers with a payload smaller than MIN_TX_BUFF_LOAD (8 bytes) must be aligned */ -+ /* to 64-bit boundary. Two options here: */ -+ /* 1) Usually, copy the payload to the reserved 8 bytes inside descriptor. */ -+ /* 2) In the Half duplex workaround, the reserved 8 bytes inside descriptor are used */ -+ /* as a pointer to the aligned buffer, copy the small payload to this buffer. */ -+ pTxBuf = ((MV_U8*)pTxCurrDesc)+TX_BUF_OFFSET_IN_DESC; -+ mvOsBCopy(pBufInfo[bufCount].bufVirtPtr, pTxBuf, pBufInfo[bufCount].dataSize); -+ pTxCurrDesc->bufPtr = ethDescVirtToPhy(pQueueCtrl, pTxBuf); -+ } -+ else -+ { -+ /* Flash Buffer */ -+#ifdef MV_NETBSD -+ pTxCurrDesc->bufPtr = pBufInfo[bufCount].bufPhysAddr; -+ ETH_PACKET_CACHE_FLUSH(pBufInfo[bufCount].bufVirtPtr, pBufInfo[bufCount].dataSize); -+#else -+ pTxCurrDesc->bufPtr = ETH_PACKET_CACHE_FLUSH(pBufInfo[bufCount].bufVirtPtr, pBufInfo[bufCount].dataSize); -+#endif -+ } -+ -+ pTxCurrDesc->byteCnt = pBufInfo[bufCount].dataSize; -+ bufCount++; -+ -+ if(bufCount >= pPktInfo->numFrags) -+ break; -+ -+ if(bufCount > 1) -+ { -+ /* There is middle buffer of the packet Not First and Not Last */ -+ pTxCurrDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA; -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); -+ } -+ /* Go to next descriptor and next buffer */ -+ pTxCurrDesc = TX_NEXT_DESC_PTR(pTxCurrDesc, pQueueCtrl); -+ } -+ /* Set last desc with DMA ownership and interrupt enable. */ -+ pTxCurrDesc->returnInfo = (MV_ULONG)pPktInfo; -+ if(bufCount == 1) -+ { -+ /* There is only one buffer in the packet */ -+ /* The OSG might set some bits for checksum offload, so add them to first descriptor */ -+ pTxCurrDesc->cmdSts = pPktInfo->status | -+ ETH_BUFFER_OWNED_BY_DMA | -+ ETH_TX_GENERATE_CRC_MASK | -+ ETH_TX_ENABLE_INTERRUPT_MASK | -+ ETH_TX_ZERO_PADDING_MASK | -+ ETH_TX_FIRST_DESC_MASK | -+ ETH_TX_LAST_DESC_MASK; -+ -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); -+ } -+ else -+ { -+ /* Last but not First */ -+ pTxCurrDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA | -+ ETH_TX_ENABLE_INTERRUPT_MASK | -+ ETH_TX_ZERO_PADDING_MASK | -+ ETH_TX_LAST_DESC_MASK; -+ -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); -+ -+ /* Update First when more than one buffer in the packet */ -+ /* The OSG might set some bits for checksum offload, so add them to first descriptor */ -+ pTxFirstDesc->cmdSts = pPktInfo->status | -+ ETH_BUFFER_OWNED_BY_DMA | -+ ETH_TX_GENERATE_CRC_MASK | -+ ETH_TX_FIRST_DESC_MASK; -+ -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxFirstDesc); -+ } -+ /* Update txQueue state */ -+ pQueueCtrl->resource -= bufCount; -+ pQueueCtrl->pCurrentDescr = TX_NEXT_DESC_PTR(pTxCurrDesc, pQueueCtrl); -+ -+ /* Apply send command */ -+ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(portNo)) = pPortCtrl->portTxQueueCmdReg; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvEthPortTxDone - Free all used Tx descriptors and mBlks. -+* -+* DESCRIPTION: -+* This routine returns the transmitted packet information to the caller. -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet Port handler. -+* int txQueue - Number of Tx queue. -+* -+* OUTPUT: -+* MV_PKT_INFO *pPktInfo - Pointer to packet was sent. -+* -+* RETURN: -+* MV_NOT_FOUND - No transmitted packets to return. Transmit in progress. -+* MV_EMPTY - No transmitted packets to return. TX Queue is empty. -+* MV_ERROR - Unexpected Fatal error. -+* MV_OK - There is transmitted packet in the queue, -+* 'pPktInfo' filled with relevant information. -+* -+*******************************************************************************/ -+static INLINE MV_PKT_INFO* mvEthPortTxDone(void* pEthPortHndl, int txQueue) -+{ -+ ETH_TX_DESC* pTxCurrDesc; -+ ETH_TX_DESC* pTxUsedDesc; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ MV_PKT_INFO* pPktInfo; -+ MV_U32 commandStatus; -+ -+ pQueueCtrl = &pPortCtrl->txQueue[txQueue]; -+ -+ pTxUsedDesc = pQueueCtrl->pUsedDescr; -+ pTxCurrDesc = pQueueCtrl->pCurrentDescr; -+ -+ while(MV_TRUE) -+ { -+ /* No more used descriptors */ -+ commandStatus = pTxUsedDesc->cmdSts; -+ if (commandStatus & (ETH_BUFFER_OWNED_BY_DMA)) -+ { -+ ETH_DESCR_INV(pPortCtrl, pTxUsedDesc); -+ return NULL; -+ } -+ if( (pTxUsedDesc == pTxCurrDesc) && -+ (pQueueCtrl->resource != 0) ) -+ { -+ return NULL; -+ } -+ pQueueCtrl->resource++; -+ pQueueCtrl->pUsedDescr = TX_NEXT_DESC_PTR(pTxUsedDesc, pQueueCtrl); -+ if(commandStatus & (ETH_TX_LAST_DESC_MASK)) -+ { -+ pPktInfo = (MV_PKT_INFO*)pTxUsedDesc->returnInfo; -+ pPktInfo->status = commandStatus; -+ return pPktInfo; -+ } -+ pTxUsedDesc = pQueueCtrl->pUsedDescr; -+ } -+} -+ -+/******************************************************************************* -+* mvEthPortRx - Get new received packets from Rx queue. -+* -+* DESCRIPTION: -+* This routine returns the received data to the caller. There is no -+* data copying during routine operation. All information is returned -+* using pointer to packet information struct passed from the caller. -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet Port handler. -+* int rxQueue - Number of Rx queue. -+* -+* OUTPUT: -+* MV_PKT_INFO *pPktInfo - Pointer to received packet. -+* -+* RETURN: -+* MV_NO_RESOURCE - No free resources in RX queue. -+* MV_ERROR - Unexpected Fatal error. -+* MV_OK - New packet received and 'pBufInfo' structure filled -+* with relevant information. -+* -+*******************************************************************************/ -+static INLINE MV_PKT_INFO* mvEthPortRx(void* pEthPortHndl, int rxQueue) -+{ -+ ETH_RX_DESC *pRxCurrDesc; -+ MV_U32 commandStatus; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ MV_PKT_INFO* pPktInfo; -+ -+ pQueueCtrl = &(pPortCtrl->rxQueue[rxQueue]); -+ -+ /* Check resources */ -+ if(pQueueCtrl->resource == 0) -+ { -+ mvOsPrintf("ethPortRx: no more resources\n"); -+ return NULL; -+ } -+ while(MV_TRUE) -+ { -+ /* Get the Rx Desc ring 'curr and 'used' indexes */ -+ pRxCurrDesc = pQueueCtrl->pCurrentDescr; -+ -+ commandStatus = pRxCurrDesc->cmdSts; -+ if (commandStatus & (ETH_BUFFER_OWNED_BY_DMA)) -+ { -+ /* Nothing to receive... */ -+ ETH_DESCR_INV(pPortCtrl, pRxCurrDesc); -+ return NULL; -+ } -+ -+ /* Valid RX only if FIRST and LAST bits are set */ -+ if( (commandStatus & (ETH_RX_LAST_DESC_MASK | ETH_RX_FIRST_DESC_MASK)) == -+ (ETH_RX_LAST_DESC_MASK | ETH_RX_FIRST_DESC_MASK) ) -+ { -+ pPktInfo = (MV_PKT_INFO*)pRxCurrDesc->returnInfo; -+ pPktInfo->pFrags->dataSize = pRxCurrDesc->byteCnt - 4; -+ pPktInfo->status = commandStatus; -+ pPktInfo->fragIP = pRxCurrDesc->bufSize & ETH_RX_IP_FRAGMENTED_FRAME_MASK; -+ -+ pQueueCtrl->resource--; -+ /* Update 'curr' in data structure */ -+ pQueueCtrl->pCurrentDescr = RX_NEXT_DESC_PTR(pRxCurrDesc, pQueueCtrl); -+ -+#ifdef INCLUDE_SYNC_BARR -+ mvCpuIfSyncBarr(DRAM_TARGET); -+#endif -+ return pPktInfo; -+ } -+ else -+ { -+ ETH_RX_DESC* pRxUsedDesc = pQueueCtrl->pUsedDescr; -+ -+#ifdef ETH_DEBUG -+ mvOsPrintf("ethDrv: Unexpected Jumbo frame: " -+ "status=0x%08x, byteCnt=%d, pData=0x%x\n", -+ commandStatus, pRxCurrDesc->byteCnt, pRxCurrDesc->bufPtr); -+#endif /* ETH_DEBUG */ -+ -+ /* move buffer from pCurrentDescr position to pUsedDescr position */ -+ pRxUsedDesc->bufPtr = pRxCurrDesc->bufPtr; -+ pRxUsedDesc->returnInfo = pRxCurrDesc->returnInfo; -+ pRxUsedDesc->bufSize = pRxCurrDesc->bufSize & ETH_RX_BUFFER_MASK; -+ -+ /* Return the descriptor to DMA ownership */ -+ pRxUsedDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA | -+ ETH_RX_ENABLE_INTERRUPT_MASK; -+ -+ /* Flush descriptor and CPU pipe */ -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxUsedDesc); -+ -+ /* Move the used descriptor pointer to the next descriptor */ -+ pQueueCtrl->pUsedDescr = RX_NEXT_DESC_PTR(pRxUsedDesc, pQueueCtrl); -+ pQueueCtrl->pCurrentDescr = RX_NEXT_DESC_PTR(pRxCurrDesc, pQueueCtrl); -+ } -+ } -+} -+ -+/******************************************************************************* -+* mvEthPortRxDone - Returns a Rx buffer back to the Rx ring. -+* -+* DESCRIPTION: -+* This routine returns a Rx buffer back to the Rx ring. -+* -+* INPUT: -+* void* pEthPortHndl - Ethernet Port handler. -+* int rxQueue - Number of Rx queue. -+* MV_PKT_INFO *pPktInfo - Pointer to received packet. -+* -+* RETURN: -+* MV_ERROR - Unexpected Fatal error. -+* MV_OUT_OF_RANGE - RX queue is already FULL, so this buffer can't be -+* returned to this queue. -+* MV_FULL - Buffer returned successfully and RX queue became full. -+* More buffers should not be returned at the time. -+* MV_OK - Buffer returned successfully and there are more free -+* places in the queue. -+* -+*******************************************************************************/ -+static INLINE MV_STATUS mvEthPortRxDone(void* pEthPortHndl, int rxQueue, MV_PKT_INFO *pPktInfo) -+{ -+ ETH_RX_DESC* pRxUsedDesc; -+ ETH_QUEUE_CTRL* pQueueCtrl; -+ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; -+ -+ pQueueCtrl = &pPortCtrl->rxQueue[rxQueue]; -+ -+ /* Get 'used' Rx descriptor */ -+ pRxUsedDesc = pQueueCtrl->pUsedDescr; -+ -+ /* Check that ring is not FULL */ -+ if( (pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) && -+ (pQueueCtrl->resource != 0) ) -+ { -+ mvOsPrintf("%s %d: out of range Error resource=%d, curr=%p, used=%p\n", -+ __FUNCTION__, pPortCtrl->portNo, pQueueCtrl->resource, -+ pQueueCtrl->pCurrentDescr, pQueueCtrl->pUsedDescr); -+ return MV_OUT_OF_RANGE; -+ } -+ -+ pRxUsedDesc->bufPtr = pPktInfo->pFrags->bufPhysAddr; -+ pRxUsedDesc->returnInfo = (MV_ULONG)pPktInfo; -+ pRxUsedDesc->bufSize = pPktInfo->pFrags->bufSize & ETH_RX_BUFFER_MASK; -+ -+ /* Invalidate data buffer accordingly with pktSize */ -+ if(pPktInfo->pktSize != 0) -+ { -+ ETH_PACKET_CACHE_INVALIDATE(pPktInfo->pFrags->bufVirtPtr, pPktInfo->pktSize); -+ pPktInfo->pktSize = 0; -+ } -+ -+ /* Return the descriptor to DMA ownership */ -+ pRxUsedDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT_MASK; -+ -+ /* Flush descriptor and CPU pipe */ -+ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxUsedDesc); -+ -+ pQueueCtrl->resource++; -+ -+ /* Move the used descriptor pointer to the next descriptor */ -+ pQueueCtrl->pUsedDescr = RX_NEXT_DESC_PTR(pRxUsedDesc, pQueueCtrl); -+ -+ /* If ring became Full return MV_FULL */ -+ if(pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) -+ return MV_FULL; -+ -+ return MV_OK; -+} -+ -+ -+#endif /* __mvEthGbe_h__ */ -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,700 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCmvEthRegsh -+#define __INCmvEthRegsh -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+ -+/****************************************/ -+/* Ethernet Unit Registers */ -+/****************************************/ -+#define ETH_REG_BASE MV_ETH_REG_BASE -+ -+#define ETH_PHY_ADDR_REG(port) (ETH_REG_BASE(port) + 0x000) -+#define ETH_SMI_REG(port) (ETH_REG_BASE(port) + 0x004) -+#define ETH_UNIT_DEF_ADDR_REG(port) (ETH_REG_BASE(port) + 0x008) -+#define ETH_UNIT_DEF_ID_REG(port) (ETH_REG_BASE(port) + 0x00c) -+#define ETH_UNIT_RESERVED(port) (ETH_REG_BASE(port) + 0x014) -+#define ETH_UNIT_INTR_CAUSE_REG(port) (ETH_REG_BASE(port) + 0x080) -+#define ETH_UNIT_INTR_MASK_REG(port) (ETH_REG_BASE(port) + 0x084) -+ -+ -+#define ETH_UNIT_ERROR_ADDR_REG(port) (ETH_REG_BASE(port) + 0x094) -+#define ETH_UNIT_INT_ADDR_ERROR_REG(port) (ETH_REG_BASE(port) + 0x098) -+#define ETH_UNIT_CONTROL_REG(port) (ETH_REG_BASE(port) + 0x0B0) -+ -+#define ETH_PORT_CONFIG_REG(port) (ETH_REG_BASE(port) + 0x400) -+#define ETH_PORT_CONFIG_EXTEND_REG(port) (ETH_REG_BASE(port) + 0x404) -+#define ETH_MII_SERIAL_PARAM_REG(port) (ETH_REG_BASE(port) + 0x408) -+#define ETH_GMII_SERIAL_PARAM_REG(port) (ETH_REG_BASE(port) + 0x40c) -+#define ETH_VLAN_ETHER_TYPE_REG(port) (ETH_REG_BASE(port) + 0x410) -+#define ETH_MAC_ADDR_LOW_REG(port) (ETH_REG_BASE(port) + 0x414) -+#define ETH_MAC_ADDR_HIGH_REG(port) (ETH_REG_BASE(port) + 0x418) -+#define ETH_SDMA_CONFIG_REG(port) (ETH_REG_BASE(port) + 0x41c) -+#define ETH_DIFF_SERV_PRIO_REG(port, code) (ETH_REG_BASE(port) + 0x420 + ((code)<<2)) -+#define ETH_PORT_SERIAL_CTRL_REG(port) (ETH_REG_BASE(port) + 0x43c) -+#define ETH_VLAN_TAG_TO_PRIO_REG(port) (ETH_REG_BASE(port) + 0x440) -+#define ETH_PORT_STATUS_REG(port) (ETH_REG_BASE(port) + 0x444) -+ -+#define ETH_RX_QUEUE_COMMAND_REG(port) (ETH_REG_BASE(port) + 0x680) -+#define ETH_TX_QUEUE_COMMAND_REG(port) (ETH_REG_BASE(port) + 0x448) -+ -+#define ETH_PORT_SERIAL_CTRL_1_REG(port) (ETH_REG_BASE(port) + 0x44c) -+#define ETH_PORT_STATUS_1_REG(port) (ETH_REG_BASE(port) + 0x450) -+#define ETH_PORT_MARVELL_HEADER_REG(port) (ETH_REG_BASE(port) + 0x454) -+#define ETH_PORT_FIFO_PARAMS_REG(port) (ETH_REG_BASE(port) + 0x458) -+#define ETH_MAX_TOKEN_BUCKET_SIZE_REG(port) (ETH_REG_BASE(port) + 0x45c) -+#define ETH_INTR_CAUSE_REG(port) (ETH_REG_BASE(port) + 0x460) -+#define ETH_INTR_CAUSE_EXT_REG(port) (ETH_REG_BASE(port) + 0x464) -+#define ETH_INTR_MASK_REG(port) (ETH_REG_BASE(port) + 0x468) -+#define ETH_INTR_MASK_EXT_REG(port) (ETH_REG_BASE(port) + 0x46c) -+#define ETH_TX_FIFO_URGENT_THRESH_REG(port) (ETH_REG_BASE(port) + 0x474) -+#define ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (ETH_REG_BASE(port) + 0x47c) -+#define ETH_RX_DISCARD_PKTS_CNTR_REG(port) (ETH_REG_BASE(port) + 0x484) -+#define ETH_RX_OVERRUN_PKTS_CNTR_REG(port) (ETH_REG_BASE(port) + 0x488) -+#define ETH_INTERNAL_ADDR_ERROR_REG(port) (ETH_REG_BASE(port) + 0x494) -+#define ETH_TX_FIXED_PRIO_CFG_REG(port) (ETH_REG_BASE(port) + 0x4dc) -+#define ETH_TX_TOKEN_RATE_CFG_REG(port) (ETH_REG_BASE(port) + 0x4e0) -+#define ETH_TX_QUEUE_COMMAND1_REG(port) (ETH_REG_BASE(port) + 0x4e4) -+#define ETH_MAX_TRANSMIT_UNIT_REG(port) (ETH_REG_BASE(port) + 0x4e8) -+#define ETH_TX_TOKEN_BUCKET_SIZE_REG(port) (ETH_REG_BASE(port) + 0x4ec) -+#define ETH_TX_TOKEN_BUCKET_COUNT_REG(port) (ETH_REG_BASE(port) + 0x780) -+#define ETH_RX_DESCR_STAT_CMD_REG(port, q) (ETH_REG_BASE(port) + 0x600 + ((q)<<4)) -+#define ETH_RX_BYTE_COUNT_REG(port, q) (ETH_REG_BASE(port) + 0x604 + ((q)<<4)) -+#define ETH_RX_BUF_PTR_REG(port, q) (ETH_REG_BASE(port) + 0x608 + ((q)<<4)) -+#define ETH_RX_CUR_DESC_PTR_REG(port, q) (ETH_REG_BASE(port) + 0x60c + ((q)<<4)) -+#define ETH_TX_CUR_DESC_PTR_REG(port, q) (ETH_REG_BASE(port) + 0x6c0 + ((q)<<2)) -+ -+#define ETH_TXQ_TOKEN_COUNT_REG(port, q) (ETH_REG_BASE(port) + 0x700 + ((q)<<4)) -+#define ETH_TXQ_TOKEN_CFG_REG(port, q) (ETH_REG_BASE(port) + 0x704 + ((q)<<4)) -+#define ETH_TXQ_ARBITER_CFG_REG(port, q) (ETH_REG_BASE(port) + 0x708 + ((q)<<4)) -+ -+#if (MV_ETH_VERSION >= 4) -+#define ETH_TXQ_CMD_1_REG(port) (ETH_REG_BASE(port) + 0x4E4) -+#define ETH_EJP_TX_HI_IPG_REG(port) (ETH_REG_BASE(port) + 0x7A8) -+#define ETH_EJP_TX_LO_IPG_REG(port) (ETH_REG_BASE(port) + 0x7B8) -+#define ETH_EJP_HI_TKN_LO_PKT_REG(port) (ETH_REG_BASE(port) + 0x7C0) -+#define ETH_EJP_HI_TKN_ASYNC_PKT_REG(port) (ETH_REG_BASE(port) + 0x7C4) -+#define ETH_EJP_LO_TKN_ASYNC_PKT_REG(port) (ETH_REG_BASE(port) + 0x7C8) -+#define ETH_EJP_TX_SPEED_REG(port) (ETH_REG_BASE(port) + 0x7D0) -+#endif /* MV_ETH_VERSION >= 4 */ -+ -+#define ETH_MIB_COUNTERS_BASE(port) (ETH_REG_BASE(port) + 0x1000) -+#define ETH_DA_FILTER_SPEC_MCAST_BASE(port) (ETH_REG_BASE(port) + 0x1400) -+#define ETH_DA_FILTER_OTH_MCAST_BASE(port) (ETH_REG_BASE(port) + 0x1500) -+#define ETH_DA_FILTER_UCAST_BASE(port) (ETH_REG_BASE(port) + 0x1600) -+ -+/* Phy address register definitions */ -+#define ETH_PHY_ADDR_OFFS 0 -+#define ETH_PHY_ADDR_MASK (0x1f <= 4) -+#define ETH_TX_EJP_RESET_BIT 0 -+#define ETH_TX_EJP_RESET_MASK (1 << ETH_TX_EJP_RESET_BIT) -+ -+#define ETH_TX_EJP_ENABLE_BIT 2 -+#define ETH_TX_EJP_ENABLE_MASK (1 << ETH_TX_EJP_ENABLE_BIT) -+ -+#define ETH_TX_LEGACY_WRR_BIT 3 -+#define ETH_TX_LEGACY_WRR_MASK (1 << ETH_TX_LEGACY_WRR_BIT) -+#endif /* (MV_ETH_VERSION >= 4) */ -+ -+/***** BITs of Ethernet Port Status reg (PSR) *****/ -+#define ETH_LINK_UP_BIT 1 -+#define ETH_LINK_UP_MASK (1<= 4) -+MV_STATUS mvEthEjpModeSet(void* pPortHandle, int mode); -+#endif /* (MV_ETH_VERSION >= 4) */ -+ -+void mvEthStatusGet(void* pPortHandle, MV_ETH_PORT_STATUS* pStatus); -+ -+/* Marvell Header control */ -+MV_STATUS mvEthHeaderModeSet(void* pPortHandle, MV_ETH_HEADER_MODE headerMode); -+ -+/* PHY routines */ -+void mvEthPhyAddrSet(void* pPortHandle, int phyAddr); -+int mvEthPhyAddrGet(void* pPortHandle); -+ -+/* Power management routines */ -+void mvEthPortPowerDown(int port); -+void mvEthPortPowerUp(int port); -+ -+/******************** ETH PRIVATE ************************/ -+ -+/*#define UNCACHED_TX_BUFFERS*/ -+/*#define UNCACHED_RX_BUFFERS*/ -+ -+ -+/* Port attributes */ -+/* Size of a Tx/Rx descriptor used in chain list data structure */ -+#define ETH_RX_DESC_ALIGNED_SIZE 32 -+#define ETH_TX_DESC_ALIGNED_SIZE 32 -+ -+#define TX_DISABLE_TIMEOUT_MSEC 1000 -+#define RX_DISABLE_TIMEOUT_MSEC 1000 -+#define TX_FIFO_EMPTY_TIMEOUT_MSEC 10000 -+#define PORT_DISABLE_WAIT_TCLOCKS 5000 -+ -+/* Macros that save access to desc in order to find next desc pointer */ -+#define RX_NEXT_DESC_PTR(pRxDescr, pQueueCtrl) \ -+ ((pRxDescr) == (pQueueCtrl)->pLastDescr) ? \ -+ (ETH_RX_DESC*)((pQueueCtrl)->pFirstDescr) : \ -+ (ETH_RX_DESC*)(((MV_ULONG)(pRxDescr)) + ETH_RX_DESC_ALIGNED_SIZE) -+ -+#define TX_NEXT_DESC_PTR(pTxDescr, pQueueCtrl) \ -+ ((pTxDescr) == (pQueueCtrl)->pLastDescr) ? \ -+ (ETH_TX_DESC*)((pQueueCtrl)->pFirstDescr) : \ -+ (ETH_TX_DESC*)(((MV_ULONG)(pTxDescr)) + ETH_TX_DESC_ALIGNED_SIZE) -+ -+#define RX_PREV_DESC_PTR(pRxDescr, pQueueCtrl) \ -+ ((pRxDescr) == (pQueueCtrl)->pFirstDescr) ? \ -+ (ETH_RX_DESC*)((pQueueCtrl)->pLastDescr) : \ -+ (ETH_RX_DESC*)(((MV_ULONG)(pRxDescr)) - ETH_RX_DESC_ALIGNED_SIZE) -+ -+#define TX_PREV_DESC_PTR(pTxDescr, pQueueCtrl) \ -+ ((pTxDescr) == (pQueueCtrl)->pFirstDescr) ? \ -+ (ETH_TX_DESC*)((pQueueCtrl)->pLastDescr) : \ -+ (ETH_TX_DESC*)(((MV_ULONG)(pTxDescr)) - ETH_TX_DESC_ALIGNED_SIZE) -+ -+ -+/* Queue specific information */ -+typedef struct -+{ -+ void* pFirstDescr; -+ void* pLastDescr; -+ void* pCurrentDescr; -+ void* pUsedDescr; -+ int resource; -+ MV_BUF_INFO descBuf; -+} ETH_QUEUE_CTRL; -+ -+ -+/* Ethernet port specific infomation */ -+typedef struct _ethPortCtrl -+{ -+ int portNo; -+ ETH_QUEUE_CTRL rxQueue[MV_ETH_RX_Q_NUM]; /* Rx ring resource */ -+ ETH_QUEUE_CTRL txQueue[MV_ETH_TX_Q_NUM]; /* Tx ring resource */ -+ -+ MV_ETH_PORT_CFG portConfig; -+ MV_ETH_RX_Q_CFG rxQueueConfig[MV_ETH_RX_Q_NUM]; -+ MV_ETH_TX_Q_CFG txQueueConfig[MV_ETH_TX_Q_NUM]; -+ -+ /* Register images - For DP */ -+ MV_U32 portTxQueueCmdReg; /* Port active Tx queues summary */ -+ MV_U32 portRxQueueCmdReg; /* Port active Rx queues summary */ -+ -+ MV_STATE portState; -+ -+ MV_U8 mcastCount[256]; -+ MV_U32* hashPtr; -+ void *osHandle; -+} ETH_PORT_CTRL; -+ -+/************** MACROs ****************/ -+ -+/* MACROs to Flush / Invalidate TX / RX Buffers */ -+#if (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) && !defined(UNCACHED_TX_BUFFERS) -+# define ETH_PACKET_CACHE_FLUSH(pAddr, size) \ -+ mvOsCacheClear(NULL, (pAddr), (size)); \ -+ /*CPU_PIPE_FLUSH;*/ -+#else -+# define ETH_PACKET_CACHE_FLUSH(pAddr, size) \ -+ mvOsIoVirtToPhy(NULL, (pAddr)); -+#endif /* ETHER_DRAM_COHER == MV_CACHE_COHER_SW */ -+ -+#if ( (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) && !defined(UNCACHED_RX_BUFFERS) ) -+# define ETH_PACKET_CACHE_INVALIDATE(pAddr, size) \ -+ mvOsCacheInvalidate (NULL, (pAddr), (size)); \ -+ /*CPU_PIPE_FLUSH;*/ -+#else -+# define ETH_PACKET_CACHE_INVALIDATE(pAddr, size) -+#endif /* ETHER_DRAM_COHER == MV_CACHE_COHER_SW && !UNCACHED_RX_BUFFERS */ -+ -+#ifdef ETH_DESCR_UNCACHED -+ -+#define ETH_DESCR_FLUSH_INV(pPortCtrl, pDescr) -+#define ETH_DESCR_INV(pPortCtrl, pDescr) -+ -+#else -+ -+#define ETH_DESCR_FLUSH_INV(pPortCtrl, pDescr) \ -+ mvOsCacheLineFlushInv(pPortCtrl->osHandle, (MV_ULONG)(pDescr)) -+ -+#define ETH_DESCR_INV(pPortCtrl, pDescr) \ -+ mvOsCacheLineInv(pPortCtrl->osHandle, (MV_ULONG)(pDescr)) -+ -+#endif /* ETH_DESCR_UNCACHED */ -+ -+#include "eth/gbe/mvEthGbe.h" -+ -+#endif /* __mvEth_h__ */ -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvCompVer.txt linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvCompVer.txt ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvCompVer.txt 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvCompVer.txt 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,4 @@ -+Global HAL Version: FEROCEON_HAL_3_1_7 -+Unit HAL Version: 3.1.4 -+Description: This component includes an implementation of the unit HAL drivers -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,362 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "gpp/mvGpp.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+static MV_VOID gppRegSet(MV_U32 group, MV_U32 regOffs,MV_U32 mask,MV_U32 value); -+ -+/******************************************************************************* -+* mvGppTypeSet - Enable a GPP (OUT) pin -+* -+* DESCRIPTION: -+* -+* INPUT: -+* group - GPP group number -+* mask - 32bit mask value. Each set bit in the mask means that the type -+* of corresponding GPP will be set. Other GPPs are ignored. -+* value - 32bit value that describes GPP type per pin. -+* -+* OUTPUT: -+* None. -+* -+* EXAMPLE: -+* Set GPP8 to input and GPP15 to output. -+* mvGppTypeSet(0, (GPP8 | GPP15), -+* ((MV_GPP_IN & GPP8) | (MV_GPP_OUT & GPP15)) ); -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvGppTypeSet(MV_U32 group, MV_U32 mask, MV_U32 value) -+{ -+ if (group >= MV_GPP_MAX_GROUP) -+ { -+ DB(mvOsPrintf("mvGppTypeSet: ERR. invalid group number \n")); -+ return MV_BAD_PARAM; -+ } -+ -+ gppRegSet(group, GPP_DATA_OUT_EN_REG(group), mask, value); -+ -+ /* Workaround for Erratum FE-MISC-70*/ -+ if(mvCtrlRevGet()==MV_88F6XXX_A0_REV && (group == 1)) -+ { -+ mask &= 0x2; -+ gppRegSet(0, GPP_DATA_OUT_EN_REG(0), mask, value); -+ } /*End of WA*/ -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvGppBlinkEn - Set a GPP (IN) Pin list to blink every ~100ms -+* -+* DESCRIPTION: -+* -+* INPUT: -+* group - GPP group number -+* mask - 32bit mask value. Each set bit in the mask means that the type -+* of corresponding GPP will be set. Other GPPs are ignored. -+* value - 32bit value that describes GPP blink per pin. -+* -+* OUTPUT: -+* None. -+* -+* EXAMPLE: -+* Set GPP8 to be static and GPP15 to be blinking. -+* mvGppBlinkEn(0, (GPP8 | GPP15), -+* ((MV_GPP_OUT_STATIC & GPP8) | (MV_GPP_OUT_BLINK & GPP15)) ); -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvGppBlinkEn(MV_U32 group, MV_U32 mask, MV_U32 value) -+{ -+ if (group >= MV_GPP_MAX_GROUP) -+ { -+ DB(mvOsPrintf("mvGppBlinkEn: ERR. invalid group number \n")); -+ return MV_BAD_PARAM; -+ } -+ -+ gppRegSet(group, GPP_BLINK_EN_REG(group), mask, value); -+ -+ return MV_OK; -+ -+} -+/******************************************************************************* -+* mvGppPolaritySet - Set a GPP (IN) Pin list Polarity mode -+* -+* DESCRIPTION: -+* -+* INPUT: -+* group - GPP group number -+* mask - 32bit mask value. Each set bit in the mask means that the type -+* of corresponding GPP will be set. Other GPPs are ignored. -+* value - 32bit value that describes GPP polarity per pin. -+* -+* OUTPUT: -+* None. -+* -+* EXAMPLE: -+* Set GPP8 to the actual pin value and GPP15 to be inverted. -+* mvGppPolaritySet(0, (GPP8 | GPP15), -+* ((MV_GPP_IN_ORIGIN & GPP8) | (MV_GPP_IN_INVERT & GPP15)) ); -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvGppPolaritySet(MV_U32 group, MV_U32 mask, MV_U32 value) -+{ -+ if (group >= MV_GPP_MAX_GROUP) -+ { -+ DB(mvOsPrintf("mvGppPolaritySet: ERR. invalid group number \n")); -+ return MV_BAD_PARAM; -+ } -+ -+ gppRegSet(group, GPP_DATA_IN_POL_REG(group), mask, value); -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvGppPolarityGet - Get a value of relevant bits from GPP Polarity register. -+* -+* DESCRIPTION: -+* -+* INPUT: -+* group - GPP group number -+* mask - 32bit mask value. Each set bit in the mask means that the -+* returned value is valid for it. -+* -+* OUTPUT: -+* None. -+* -+* EXAMPLE: -+* Get GPP8 and GPP15 value. -+* mvGppPolarityGet(0, (GPP8 | GPP15)); -+* -+* RETURN: -+* 32bit value that describes GPP polatity mode per pin. -+* -+*******************************************************************************/ -+MV_U32 mvGppPolarityGet(MV_U32 group, MV_U32 mask) -+{ -+ MV_U32 regVal; -+ -+ if (group >= MV_GPP_MAX_GROUP) -+ { -+ DB(mvOsPrintf("mvGppActiveSet: Error invalid group number \n")); -+ return MV_ERROR; -+ } -+ regVal = MV_REG_READ(GPP_DATA_IN_POL_REG(group)); -+ -+ return (regVal & mask); -+} -+ -+/******************************************************************************* -+* mvGppValueGet - Get a GPP Pin list value. -+* -+* DESCRIPTION: -+* This function get GPP value. -+* -+* INPUT: -+* group - GPP group number -+* mask - 32bit mask value. Each set bit in the mask means that the -+* returned value is valid for it. -+* -+* OUTPUT: -+* None. -+* -+* EXAMPLE: -+* Get GPP8 and GPP15 value. -+* mvGppValueGet(0, (GPP8 | GPP15)); -+* -+* RETURN: -+* 32bit value that describes GPP activity mode per pin. -+* -+*******************************************************************************/ -+MV_U32 mvGppValueGet(MV_U32 group, MV_U32 mask) -+{ -+ MV_U32 gppData; -+ -+ gppData = MV_REG_READ(GPP_DATA_IN_REG(group)); -+ -+ gppData &= mask; -+ -+ return gppData; -+ -+} -+ -+/******************************************************************************* -+* mvGppValueSet - Set a GPP Pin list value. -+* -+* DESCRIPTION: -+* This function set value for given GPP pin list. -+* -+* INPUT: -+* group - GPP group number -+* mask - 32bit mask value. Each set bit in the mask means that the -+* value of corresponding GPP will be set accordingly. Other GPP -+* are not affected. -+* value - 32bit value that describes GPP value per pin. -+* -+* OUTPUT: -+* None. -+* -+* EXAMPLE: -+* Set GPP8 value of '0' and GPP15 value of '1'. -+* mvGppActiveSet(0, (GPP8 | GPP15), ((0 & GPP8) | (GPP15)) ); -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvGppValueSet (MV_U32 group, MV_U32 mask, MV_U32 value) -+{ -+ MV_U32 outEnable, tmp; -+ MV_U32 i; -+ -+ if (group >= MV_GPP_MAX_GROUP) -+ { -+ DB(mvOsPrintf("mvGppValueSet: Error invalid group number \n")); -+ return MV_BAD_PARAM; -+ } -+ -+ /* verify that the gpp pin is configured as output */ -+ /* Note that in the register out enabled -> bit = '0'. */ -+ outEnable = ~MV_REG_READ(GPP_DATA_OUT_EN_REG(group)); -+ -+ /* Workaround for Erratum FE-MISC-70*/ -+ if(mvCtrlRevGet()==MV_88F6XXX_A0_REV && (group == 1)) -+ { -+ tmp = ~MV_REG_READ(GPP_DATA_OUT_EN_REG(0)); -+ outEnable &= 0xfffffffd; -+ outEnable |= (tmp & 0x2); -+ } /*End of WA*/ -+ -+ for (i = 0 ; i < 32 ;i++) -+ { -+ if (((mask & (1 << i)) & (outEnable & (1 << i))) != (mask & (1 << i))) -+ { -+ mvOsPrintf("mvGppValueSet: Err. An attempt to set output "\ -+ "value to GPP %d in input mode.\n", i); -+ return MV_ERROR; -+ } -+ } -+ -+ gppRegSet(group, GPP_DATA_OUT_REG(group), mask, value); -+ -+ return MV_OK; -+ -+} -+/******************************************************************************* -+* gppRegSet - Set a specific GPP pin on a specific GPP register -+* -+* DESCRIPTION: -+* This function set a specific GPP pin on a specific GPP register -+* -+* INPUT: -+* regOffs - GPP Register offset -+* group - GPP group number -+* mask - 32bit mask value. Each set bit in the mask means that the -+* value of corresponding GPP will be set accordingly. Other GPP -+* are not affected. -+* value - 32bit value that describes GPP value per pin. -+* -+* OUTPUT: -+* None. -+* -+* EXAMPLE: -+* Set GPP8 value of '0' and GPP15 value of '1'. -+* mvGppActiveSet(0, (GPP8 | GPP15), ((0 & GPP8) | (1 & GPP15)) ); -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+static MV_VOID gppRegSet (MV_U32 group, MV_U32 regOffs,MV_U32 mask,MV_U32 value) -+{ -+ MV_U32 gppData; -+ -+ gppData = MV_REG_READ(regOffs); -+ -+ gppData &= ~mask; -+ -+ gppData |= (value & mask); -+ -+ MV_REG_WRITE(regOffs, gppData); -+} -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,118 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvGppH -+#define __INCmvGppH -+ -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+#include "gpp/mvGppRegs.h" -+ -+/* These macros describes the GPP type. Each of the GPPs pins can */ -+/* be assigned to act as a general purpose input or output pin. */ -+#define MV_GPP_IN 0xFFFFFFFF /* GPP input */ -+#define MV_GPP_OUT 0 /* GPP output */ -+ -+ -+/* These macros describes the GPP Out Enable. */ -+#define MV_GPP_OUT_DIS 0xFFFFFFFF /* Out pin disabled*/ -+#define MV_GPP_OUT_EN 0 /* Out pin enabled*/ -+ -+/* These macros describes the GPP Out Blinking. */ -+/* When set and the corresponding bit in GPIO Data Out Enable Control */ -+/* Register is enabled, the GPIO pin blinks every ~100 ms (a period of */ -+/* 2^24 TCLK clocks). */ -+#define MV_GPP_OUT_BLINK 0xFFFFFFFF /* Out pin blinking*/ -+#define MV_GPP_OUT_STATIC 0 /* Out pin static*/ -+ -+ -+/* These macros describes the GPP Polarity. */ -+/* When set to 1 GPIO Data In Register reflects the inverted value of the */ -+/* corresponding pin. */ -+ -+#define MV_GPP_IN_INVERT 0xFFFFFFFF /* Inverted value is got*/ -+#define MV_GPP_IN_ORIGIN 0 /* original value is got*/ -+ -+/* mvGppTypeSet - Set PP pin mode (IN or OUT) */ -+MV_STATUS mvGppTypeSet(MV_U32 group, MV_U32 mask, MV_U32 value); -+ -+/* mvGppBlinkEn - Set a GPP (IN) Pin list to blink every ~100ms */ -+MV_STATUS mvGppBlinkEn(MV_U32 group, MV_U32 mask, MV_U32 value); -+ -+/* mvGppPolaritySet - Set a GPP (IN) Pin list Polarity mode. */ -+MV_STATUS mvGppPolaritySet(MV_U32 group, MV_U32 mask, MV_U32 value); -+ -+/* mvGppPolarityGet - Get the Polarity of a GPP Pin */ -+MV_U32 mvGppPolarityGet(MV_U32 group, MV_U32 mask); -+ -+/* mvGppValueGet - Get a GPP Pin list value.*/ -+MV_U32 mvGppValueGet(MV_U32 group, MV_U32 mask); -+ -+ -+/* mvGppValueSet - Set a GPP Pin list value. */ -+MV_STATUS mvGppValueSet (MV_U32 group, MV_U32 mask, MV_U32 value); -+ -+#endif /* #ifndef __INCmvGppH */ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGppRegs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGppRegs.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGppRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGppRegs.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,116 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvGppRegsH -+#define __INCmvGppRegsH -+ -+#define MV_GPP0 BIT0 -+#define MV_GPP1 BIT1 -+#define MV_GPP2 BIT2 -+#define MV_GPP3 BIT3 -+#define MV_GPP4 BIT4 -+#define MV_GPP5 BIT5 -+#define MV_GPP6 BIT6 -+#define MV_GPP7 BIT7 -+#define MV_GPP8 BIT8 -+#define MV_GPP9 BIT9 -+#define MV_GPP10 BIT10 -+#define MV_GPP11 BIT11 -+#define MV_GPP12 BIT12 -+#define MV_GPP13 BIT13 -+#define MV_GPP14 BIT14 -+#define MV_GPP15 BIT15 -+#define MV_GPP16 BIT16 -+#define MV_GPP17 BIT17 -+#define MV_GPP18 BIT18 -+#define MV_GPP19 BIT19 -+#define MV_GPP20 BIT20 -+#define MV_GPP21 BIT21 -+#define MV_GPP22 BIT22 -+#define MV_GPP23 BIT23 -+#define MV_GPP24 BIT24 -+#define MV_GPP25 BIT25 -+#define MV_GPP26 BIT26 -+#define MV_GPP27 BIT27 -+#define MV_GPP28 BIT28 -+#define MV_GPP29 BIT29 -+#define MV_GPP30 BIT30 -+#define MV_GPP31 BIT31 -+ -+ -+/* registers offsets */ -+ -+#define GPP_DATA_OUT_REG(grp) ((grp == 0) ? 0x10100 : 0x10140) -+#define GPP_DATA_OUT_EN_REG(grp) ((grp == 0) ? 0x10104 : 0x10144) -+#define GPP_BLINK_EN_REG(grp) ((grp == 0) ? 0x10108 : 0x10148) -+#define GPP_DATA_IN_POL_REG(grp) ((grp == 0) ? 0x1010C : 0x1014c) -+#define GPP_DATA_IN_REG(grp) ((grp == 0) ? 0x10110 : 0x10150) -+#define GPP_INT_CAUSE_REG(grp) ((grp == 0) ? 0x10114 : 0x10154) -+#define GPP_INT_MASK_REG(grp) ((grp == 0) ? 0x10118 : 0x10158) -+#define GPP_INT_LVL_REG(grp) ((grp == 0) ? 0x1011c : 0x1015c) -+ -+#define GPP_DATA_OUT_SET_REG 0x10120 -+#define GPP_DATA_OUT_CLEAR_REG 0x10124 -+ -+#endif /* #ifndef __INCmvGppRegsH */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvCompVer.txt linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvCompVer.txt ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvCompVer.txt 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvCompVer.txt 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,4 @@ -+Global HAL Version: FEROCEON_HAL_3_1_7 -+Unit HAL Version: 3.1.2 -+Description: This component includes an implementation of the unit HAL drivers -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,1047 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#include "pci/mvPci.h" -+ -+#include "ctrlEnv/mvCtrlEnvLib.h" -+ -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+ -+ -+MV_VOID mvPciHalInit(MV_U32 pciIf, MV_PCI_MOD pciIfmod) -+{ -+ if (MV_PCI_MOD_HOST == pciIfmod) -+ { -+ -+ mvPciLocalBusNumSet(pciIf, PCI_HOST_BUS_NUM(pciIf)); -+ mvPciLocalDevNumSet(pciIf, PCI_HOST_DEV_NUM(pciIf)); -+ -+ /* Local device master Enable */ -+ mvPciMasterEnable(pciIf, MV_TRUE); -+ -+ /* Local device slave Enable */ -+ mvPciSlaveEnable(pciIf, mvPciLocalBusNumGet(pciIf), -+ mvPciLocalDevNumGet(pciIf), MV_TRUE); -+ } -+ /* enable CPU-2-PCI ordering */ -+ MV_REG_BIT_SET(PCI_CMD_REG(0), PCR_CPU_TO_PCI_ORDER_EN); -+} -+ -+/******************************************************************************* -+* mvPciCommandSet - Set PCI comman register value. -+* -+* DESCRIPTION: -+* This function sets a given PCI interface with its command register -+* value. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* command - 32bit value to be written to comamnd register. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM if pciIf is not in range otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciCommandSet(MV_U32 pciIf, MV_U32 command) -+{ -+ MV_U32 locBusNum, locDevNum, regVal; -+ -+ locBusNum = mvPciLocalBusNumGet(pciIf); -+ locDevNum = mvPciLocalDevNumGet(pciIf); -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciCommandSet: ERR. Invalid PCI IF num %d\n", pciIf); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Set command register */ -+ MV_REG_WRITE(PCI_CMD_REG(pciIf), command); -+ -+ /* Upodate device max outstanding split tarnsaction */ -+ if ((command & PCR_CPU_TO_PCI_ORDER_EN) && -+ (command & PCR_PCI_TO_CPU_ORDER_EN)) -+ { -+ /* Read PCI-X command register */ -+ regVal = mvPciConfigRead (pciIf, locBusNum, locDevNum, 0, PCIX_COMMAND); -+ -+ /* clear bits 22:20 */ -+ regVal &= 0xff8fffff; -+ -+ /* set reset value */ -+ regVal |= (0x3 << 20); -+ -+ /* Write back the value */ -+ mvPciConfigWrite (pciIf, locBusNum, locDevNum, 0, PCIX_COMMAND, regVal); -+ } -+ -+ return MV_OK; -+ -+ -+} -+ -+ -+/******************************************************************************* -+* mvPciModeGet - Get PCI interface mode. -+* -+* DESCRIPTION: -+* This function returns the given PCI interface mode. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* -+* OUTPUT: -+* pPciMode - Pointer to PCI mode structure. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciModeGet(MV_U32 pciIf, MV_PCI_MODE *pPciMode) -+{ -+ MV_U32 pciMode; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciModeGet: ERR. Invalid PCI interface %d\n", pciIf); -+ return MV_BAD_PARAM; -+ } -+ if (NULL == pPciMode) -+ { -+ mvOsPrintf("mvPciModeGet: ERR. pPciMode = NULL \n"); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Read pci mode register */ -+ pciMode = MV_REG_READ(PCI_MODE_REG(pciIf)); -+ -+ switch (pciMode & PMR_PCI_MODE_MASK) -+ { -+ case PMR_PCI_MODE_CONV: -+ pPciMode->pciType = MV_PCI_CONV; -+ -+ if (MV_REG_READ(PCI_DLL_CTRL_REG(pciIf)) & PDC_DLL_EN) -+ { -+ pPciMode->pciSpeed = 66000000; /* 66MHZ */ -+ } -+ else -+ { -+ pPciMode->pciSpeed = 33000000; /* 33MHZ */ -+ } -+ -+ break; -+ -+ case PMR_PCI_MODE_PCIX_66MHZ: -+ pPciMode->pciType = MV_PCIX; -+ pPciMode->pciSpeed = 66000000; /* 66MHZ */ -+ break; -+ -+ case PMR_PCI_MODE_PCIX_100MHZ: -+ pPciMode->pciType = MV_PCIX; -+ pPciMode->pciSpeed = 100000000; /* 100MHZ */ -+ break; -+ -+ case PMR_PCI_MODE_PCIX_133MHZ: -+ pPciMode->pciType = MV_PCIX; -+ pPciMode->pciSpeed = 133000000; /* 133MHZ */ -+ break; -+ -+ default: -+ { -+ mvOsPrintf("mvPciModeGet: ERR. Non existing mode !!\n"); -+ return MV_ERROR; -+ } -+ } -+ -+ switch (pciMode & PMR_PCI_64_MASK) -+ { -+ case PMR_PCI_64_64BIT: -+ pPciMode->pciWidth = MV_PCI_64; -+ break; -+ -+ case PMR_PCI_64_32BIT: -+ pPciMode->pciWidth = MV_PCI_32; -+ break; -+ -+ default: -+ { -+ mvOsPrintf("mvPciModeGet: ERR. Non existing mode !!\n"); -+ return MV_ERROR; -+ } -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvPciRetrySet - Set PCI retry counters -+* -+* DESCRIPTION: -+* This function specifies the number of times the PCI controller -+* retries a transaction before it quits. -+* Applies to the PCI Master when acting as a requester. -+* Applies to the PCI slave when acting as a completer (PCI-X mode). -+* A 0x00 value means a "retry forever". -+* -+* INPUT: -+* pciIf - PCI interface number. -+* counter - Number of times PCI controller retry. Use counter value -+* up to PRR_RETRY_CNTR_MAX. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciRetrySet(MV_U32 pciIf, MV_U32 counter) -+{ -+ MV_U32 pciRetry; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciRetrySet: ERR. Invalid PCI interface %d\n", pciIf); -+ return MV_BAD_PARAM; -+ } -+ -+ if (counter >= PRR_RETRY_CNTR_MAX) -+ { -+ mvOsPrintf("mvPciRetrySet: ERR. Invalid counter: %d\n", counter); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ /* Reading PCI retry register */ -+ pciRetry = MV_REG_READ(PCI_RETRY_REG(pciIf)); -+ -+ pciRetry &= ~PRR_RETRY_CNTR_MASK; -+ -+ pciRetry |= (counter << PRR_RETRY_CNTR_OFFS); -+ -+ /* write new value */ -+ MV_REG_WRITE(PCI_RETRY_REG(pciIf), pciRetry); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPciDiscardTimerSet - Set PCI discard timer -+* -+* DESCRIPTION: -+* This function set PCI discard timer. -+* In conventional PCI mode: -+* Specifies the number of PCLK cycles the PCI slave keeps a non-accessed -+* read buffers (non-completed delayed read) before invalidate the buffer. -+* Set to '0' to disable the timer. The PCI slave waits for delayed -+* read completion forever. -+* In PCI-X mode: -+* Specifies the number of PCLK cycles the PCI master waits for split -+* completion transaction, before it invalidates the pre-allocated read -+* buffer. -+* Set to '0' to disable the timer. The PCI master waits for split -+* completion forever. -+* NOTE: Must be set to a number greater than MV_PCI_MAX_DISCARD_CLK, -+* unless using the "wait for ever" setting 0x0. -+* NOTE: Must not be updated while there are pending read requests. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* pClkCycles - Number of PCI clock cycles. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciDiscardTimerSet(MV_U32 pciIf, MV_U32 pClkCycles) -+{ -+ MV_U32 pciDiscardTimer; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciDiscardTimerSet: ERR. Invalid PCI interface %d\n", -+ pciIf); -+ return MV_BAD_PARAM; -+ } -+ -+ if (pClkCycles >= PDTR_TIMER_MIN) -+ { -+ mvOsPrintf("mvPciDiscardTimerSet: ERR. Invalid Clk value: %d\n", -+ pClkCycles); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ /* Read PCI Discard Timer */ -+ pciDiscardTimer = MV_REG_READ(PCI_DISCARD_TIMER_REG(pciIf)); -+ -+ pciDiscardTimer &= ~PDTR_TIMER_MASK; -+ -+ pciDiscardTimer |= (pClkCycles << PDTR_TIMER_OFFS); -+ -+ /* Write new value */ -+ MV_REG_WRITE(PCI_DISCARD_TIMER_REG(pciIf), pciDiscardTimer); -+ -+ return MV_OK; -+ -+} -+ -+/* PCI Arbiter routines */ -+ -+/******************************************************************************* -+* mvPciArbEnable - PCI arbiter enable/disable -+* -+* DESCRIPTION: -+* This fuction enable/disables a given PCI interface arbiter. -+* NOTE: Arbiter setting can not be changed while in work. It should only -+* be set once. -+* INPUT: -+* pciIf - PCI interface number. -+* enable - Enable/disable parameter. If enable = MV_TRUE then enable. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvPciArbEnable(MV_U32 pciIf, MV_BOOL enable) -+{ -+ MV_U32 regVal; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciArbEnable: ERR. Invalid PCI interface %d\n", pciIf); -+ return MV_ERROR; -+ } -+ -+ /* Set PCI Arbiter Control register according to default configuration */ -+ regVal = MV_REG_READ(PCI_ARBITER_CTRL_REG(pciIf)); -+ -+ /* Make sure arbiter disabled before changing its values */ -+ MV_REG_BIT_RESET(PCI_ARBITER_CTRL_REG(pciIf), PACR_ARB_ENABLE); -+ -+ regVal &= ~PCI_ARBITER_CTRL_DEFAULT_MASK; -+ -+ regVal |= PCI_ARBITER_CTRL_DEFAULT; /* Set default configuration */ -+ -+ if (MV_TRUE == enable) -+ { -+ regVal |= PACR_ARB_ENABLE; -+ } -+ else -+ { -+ regVal &= ~PACR_ARB_ENABLE; -+ } -+ -+ /* Write to register */ -+ MV_REG_WRITE(PCI_ARBITER_CTRL_REG(pciIf), regVal); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPciArbParkDis - Disable arbiter parking on agent -+* -+* DESCRIPTION: -+* This function disables the PCI arbiter from parking on the given agent -+* list. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* pciAgentMask - When a bit in the mask is set to '1', parking on -+* the associated PCI master is disabled. Mask bit -+* refers to bit 0 - 6. For example disable parking on PCI -+* agent 3 set pciAgentMask 0x4 (bit 3 is set). -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+MV_STATUS mvPciArbParkDis(MV_U32 pciIf, MV_U32 pciAgentMask) -+{ -+ MV_U32 pciArbiterCtrl; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciArbParkDis: ERR. Invalid PCI interface %d\n", pciIf); -+ return MV_ERROR; -+ } -+ -+ /* Reading Arbiter Control register */ -+ pciArbiterCtrl = MV_REG_READ(PCI_ARBITER_CTRL_REG(pciIf)); -+ -+ /* Arbiter must be disabled before changing parking */ -+ MV_REG_BIT_RESET(PCI_ARBITER_CTRL_REG(pciIf), PACR_ARB_ENABLE); -+ -+ /* do the change */ -+ pciArbiterCtrl &= ~PACR_PARK_DIS_MASK; -+ pciArbiterCtrl |= (pciAgentMask << PACR_PARK_DIS_OFFS); -+ -+ /* writing new value ( if th earbiter was enabled before the change */ -+ /* here it will be reenabled */ -+ MV_REG_WRITE(PCI_ARBITER_CTRL_REG(pciIf), pciArbiterCtrl); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPciArbBrokDetectSet - Set PCI arbiter broken detection -+* -+* DESCRIPTION: -+* This function sets the maximum number of cycles that the arbiter -+* waits for a PCI master to respond to its grant assertion. If a -+* PCI agent fails to respond within this time, the PCI arbiter aborts -+* the transaction and performs a new arbitration cycle. -+* NOTE: Value must be greater than '1' for conventional PCI and -+* greater than '5' for PCI-X. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* pClkCycles - Number of PCI clock cycles. If equal to '0' the broken -+* master detection is disabled. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciArbBrokDetectSet(MV_U32 pciIf, MV_U32 pClkCycles) -+{ -+ MV_U32 pciArbiterCtrl; -+ MV_U32 pciMode; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciArbBrokDetectSet: ERR. Invalid PCI interface %d\n", -+ pciIf); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Checking PCI mode and if pClkCycles is legal value */ -+ pciMode = MV_REG_READ(PCI_MODE_REG(pciIf)); -+ pciMode &= PMR_PCI_MODE_MASK; -+ -+ if (PMR_PCI_MODE_CONV == pciMode) -+ { -+ if (pClkCycles < PACR_BROKEN_VAL_CONV_MIN) -+ return MV_ERROR; -+ } -+ else -+ { -+ if (pClkCycles < PACR_BROKEN_VAL_PCIX_MIN) -+ return MV_ERROR; -+ } -+ -+ pClkCycles <<= PACR_BROKEN_VAL_OFFS; -+ -+ /* Reading Arbiter Control register */ -+ pciArbiterCtrl = MV_REG_READ(PCI_ARBITER_CTRL_REG(pciIf)); -+ pciArbiterCtrl &= ~PACR_BROKEN_VAL_MASK; -+ pciArbiterCtrl |= pClkCycles; -+ -+ /* Arbiter must be disabled before changing broken detection */ -+ MV_REG_BIT_RESET(PCI_ARBITER_CTRL_REG(pciIf), PACR_ARB_ENABLE); -+ -+ /* writing new value ( if th earbiter was enabled before the change */ -+ /* here it will be reenabled */ -+ -+ MV_REG_WRITE(PCI_ARBITER_CTRL_REG(pciIf), pciArbiterCtrl); -+ -+ return MV_OK; -+} -+ -+/* PCI configuration space read write */ -+ -+/******************************************************************************* -+* mvPciConfigRead - Read from configuration space -+* -+* DESCRIPTION: -+* This function performs a 32 bit read from PCI configuration space. -+* It supports both type 0 and type 1 of Configuration Transactions -+* (local and over bridge). In order to read from local bus segment, use -+* bus number retrieved from mvPciLocalBusNumGet(). Other bus numbers -+* will result configuration transaction of type 1 (over bridge). -+* -+* INPUT: -+* pciIf - PCI interface number. -+* bus - PCI segment bus number. -+* dev - PCI device number. -+* func - Function number. -+* regOffs - Register offset. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit register data, 0xffffffff on error -+* -+*******************************************************************************/ -+MV_U32 mvPciConfigRead (MV_U32 pciIf, MV_U32 bus, MV_U32 dev, MV_U32 func, -+ MV_U32 regOff) -+{ -+ MV_U32 pciData = 0; -+ -+ /* Parameter checking */ -+ if (PCI_DEFAULT_IF != pciIf) -+ { -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciConfigRead: ERR. Invalid PCI interface %d\n",pciIf); -+ return 0xFFFFFFFF; -+ } -+ } -+ -+ if (dev >= MAX_PCI_DEVICES) -+ { -+ DB(mvOsPrintf("mvPciConfigRead: ERR. device number illigal %d\n", dev)); -+ return 0xFFFFFFFF; -+ } -+ -+ if (func >= MAX_PCI_FUNCS) -+ { -+ DB(mvOsPrintf("mvPciConfigRead: ERR. function number illigal %d\n", func)); -+ return 0xFFFFFFFF; -+ } -+ -+ if (bus >= MAX_PCI_BUSSES) -+ { -+ DB(mvOsPrintf("mvPciConfigRead: ERR. bus number illigal %d\n", bus)); -+ return MV_ERROR; -+ } -+ -+ -+ /* Creating PCI address to be passed */ -+ pciData |= (bus << PCAR_BUS_NUM_OFFS); -+ pciData |= (dev << PCAR_DEVICE_NUM_OFFS); -+ pciData |= (func << PCAR_FUNC_NUM_OFFS); -+ pciData |= (regOff & PCAR_REG_NUM_MASK); -+ -+ pciData |= PCAR_CONFIG_EN; -+ -+ /* Write the address to the PCI configuration address register */ -+ MV_REG_WRITE(PCI_CONFIG_ADDR_REG(pciIf), pciData); -+ -+ /* In order to let the PCI controller absorbed the address of the read */ -+ /* transaction we perform a validity check that the address was written */ -+ if(pciData != MV_REG_READ(PCI_CONFIG_ADDR_REG(pciIf))) -+ { -+ return MV_ERROR; -+ } -+ /* Read the Data returned in the PCI Data register */ -+ pciData = MV_REG_READ(PCI_CONFIG_DATA_REG(pciIf)); -+ -+ return pciData; -+} -+ -+/******************************************************************************* -+* mvPciConfigWrite - Write to configuration space -+* -+* DESCRIPTION: -+* This function performs a 32 bit write to PCI configuration space. -+* It supports both type 0 and type 1 of Configuration Transactions -+* (local and over bridge). In order to write to local bus segment, use -+* bus number retrieved from mvPciLocalBusNumGet(). Other bus numbers -+* will result configuration transaction of type 1 (over bridge). -+* -+* INPUT: -+* pciIf - PCI interface number. -+* bus - PCI segment bus number. -+* dev - PCI device number. -+* func - Function number. -+* regOffs - Register offset. -+* data - 32bit data. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciConfigWrite(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data) -+{ -+ MV_U32 pciData = 0; -+ -+ /* Parameter checking */ -+ if (PCI_DEFAULT_IF != pciIf) -+ { -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciConfigWrite: ERR. Invalid PCI interface %d\n", -+ pciIf); -+ return 0xFFFFFFFF; -+ } -+ } -+ -+ if (dev >= MAX_PCI_DEVICES) -+ { -+ mvOsPrintf("mvPciConfigWrite: ERR. device number illigal %d\n",dev); -+ return MV_BAD_PARAM; -+ } -+ -+ if (func >= MAX_PCI_FUNCS) -+ { -+ mvOsPrintf("mvPciConfigWrite: ERR. function number illigal %d\n", func); -+ return MV_ERROR; -+ } -+ -+ if (bus >= MAX_PCI_BUSSES) -+ { -+ mvOsPrintf("mvPciConfigWrite: ERR. bus number illigal %d\n", bus); -+ return MV_ERROR; -+ } -+ -+ /* Creating PCI address to be passed */ -+ pciData |= (bus << PCAR_BUS_NUM_OFFS); -+ pciData |= (dev << PCAR_DEVICE_NUM_OFFS); -+ pciData |= (func << PCAR_FUNC_NUM_OFFS); -+ pciData |= (regOff & PCAR_REG_NUM_MASK); -+ -+ pciData |= PCAR_CONFIG_EN; -+ -+ /* Write the address to the PCI configuration address register */ -+ MV_REG_WRITE(PCI_CONFIG_ADDR_REG(pciIf), pciData); -+ -+ /* In order to let the PCI controller absorbed the address of the read */ -+ /* transaction we perform a validity check that the address was written */ -+ if(pciData != MV_REG_READ(PCI_CONFIG_ADDR_REG(pciIf))) -+ { -+ return MV_ERROR; -+ } -+ -+ /* Write the Data passed to the PCI Data register */ -+ MV_REG_WRITE(PCI_CONFIG_DATA_REG(pciIf), data); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvPciMasterEnable - Enable/disale PCI interface master transactions. -+* -+* DESCRIPTION: -+* This function performs read modified write to PCI command status -+* (offset 0x4) to set/reset bit 2. After this bit is set, the PCI -+* master is allowed to gain ownership on the bus, otherwise it is -+* incapable to do so. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciMasterEnable(MV_U32 pciIf, MV_BOOL enable) -+{ -+ MV_U32 pciCommandStatus; -+ MV_U32 RegOffs; -+ MV_U32 localBus; -+ MV_U32 localDev; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciMasterEnable: ERR. Invalid PCI interface %d\n", pciIf); -+ return MV_ERROR; -+ } -+ -+ localBus = mvPciLocalBusNumGet(pciIf); -+ localDev = mvPciLocalDevNumGet(pciIf); -+ -+ RegOffs = PCI_STATUS_AND_COMMAND; -+ -+ pciCommandStatus = mvPciConfigRead(pciIf, localBus, localDev, 0, RegOffs); -+ -+ if (MV_TRUE == enable) -+ { -+ pciCommandStatus |= PSCR_MASTER_EN; -+ } -+ else -+ { -+ pciCommandStatus &= ~PSCR_MASTER_EN; -+ } -+ -+ mvPciConfigWrite(pciIf, localBus, localDev, 0, RegOffs, pciCommandStatus); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPciSlaveEnable - Enable/disale PCI interface slave transactions. -+* -+* DESCRIPTION: -+* This function performs read modified write to PCI command status -+* (offset 0x4) to set/reset bit 0 and 1. After those bits are set, -+* the PCI slave is allowed to respond to PCI IO space access (bit 0) -+* and PCI memory space access (bit 1). -+* -+* INPUT: -+* pciIf - PCI interface number. -+* dev - PCI device number. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciSlaveEnable(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, MV_BOOL enable) -+{ -+ MV_U32 pciCommandStatus; -+ MV_U32 RegOffs; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciSlaveEnable: ERR. Invalid PCI interface %d\n", pciIf); -+ return MV_BAD_PARAM; -+ } -+ if (dev >= MAX_PCI_DEVICES) -+ { -+ mvOsPrintf("mvPciLocalDevNumSet: ERR. device number illigal %d\n", dev); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ RegOffs = PCI_STATUS_AND_COMMAND; -+ -+ pciCommandStatus=mvPciConfigRead(pciIf, bus, dev, 0, RegOffs); -+ -+ if (MV_TRUE == enable) -+ { -+ pciCommandStatus |= (PSCR_IO_EN | PSCR_MEM_EN); -+ } -+ else -+ { -+ pciCommandStatus &= ~(PSCR_IO_EN | PSCR_MEM_EN); -+ } -+ -+ mvPciConfigWrite(pciIf, bus, dev, 0, RegOffs, pciCommandStatus); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvPciLocalBusNumSet - Set PCI interface local bus number. -+* -+* DESCRIPTION: -+* This function sets given PCI interface its local bus number. -+* Note: In case the PCI interface is PCI-X, the information is read-only. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* busNum - Bus number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_NOT_ALLOWED in case PCI interface is PCI-X. -+* MV_BAD_PARAM on bad parameters , -+* otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciLocalBusNumSet(MV_U32 pciIf, MV_U32 busNum) -+{ -+ MV_U32 pciP2PConfig; -+ MV_PCI_MODE pciMode; -+ MV_U32 localBus; -+ MV_U32 localDev; -+ -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciLocalBusNumSet: ERR. Invalid PCI interface %d\n",pciIf); -+ return MV_BAD_PARAM; -+ } -+ if (busNum >= MAX_PCI_BUSSES) -+ { -+ mvOsPrintf("mvPciLocalBusNumSet: ERR. bus number illigal %d\n", busNum); -+ return MV_ERROR; -+ -+ } -+ -+ localBus = mvPciLocalBusNumGet(pciIf); -+ localDev = mvPciLocalDevNumGet(pciIf); -+ -+ -+ /* PCI interface mode */ -+ mvPciModeGet(pciIf, &pciMode); -+ -+ /* if PCI type is PCI-X then it is not allowed to change the dev number */ -+ if (MV_PCIX == pciMode.pciType) -+ { -+ pciP2PConfig = mvPciConfigRead(pciIf, localBus, localDev, 0, PCIX_STATUS ); -+ -+ pciP2PConfig &= ~PXS_BN_MASK; -+ -+ pciP2PConfig |= (busNum << PXS_BN_OFFS) & PXS_BN_MASK; -+ -+ mvPciConfigWrite(pciIf, localBus, localDev, 0, PCIX_STATUS,pciP2PConfig ); -+ -+ } -+ else -+ { -+ pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); -+ -+ pciP2PConfig &= ~PPCR_BUS_NUM_MASK; -+ -+ pciP2PConfig |= (busNum << PPCR_BUS_NUM_OFFS) & PPCR_BUS_NUM_MASK; -+ -+ MV_REG_WRITE(PCI_P2P_CONFIG_REG(pciIf), pciP2PConfig); -+ -+ } -+ -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPciLocalBusNumGet - Get PCI interface local bus number. -+* -+* DESCRIPTION: -+* This function gets the local bus number of a given PCI interface. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Local bus number.0xffffffff on Error -+* -+*******************************************************************************/ -+MV_U32 mvPciLocalBusNumGet(MV_U32 pciIf) -+{ -+ MV_U32 pciP2PConfig; -+ -+ /* Parameter checking */ -+ if (PCI_DEFAULT_IF != pciIf) -+ { -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciLocalBusNumGet: ERR. Invalid PCI interface %d\n", -+ pciIf); -+ return 0xFFFFFFFF; -+ } -+ } -+ -+ pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); -+ pciP2PConfig &= PPCR_BUS_NUM_MASK; -+ return (pciP2PConfig >> PPCR_BUS_NUM_OFFS); -+} -+ -+ -+/******************************************************************************* -+* mvPciLocalDevNumSet - Set PCI interface local device number. -+* -+* DESCRIPTION: -+* This function sets given PCI interface its local device number. -+* Note: In case the PCI interface is PCI-X, the information is read-only. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* devNum - Device number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_NOT_ALLOWED in case PCI interface is PCI-X. MV_BAD_PARAM on bad parameters , -+* otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciLocalDevNumSet(MV_U32 pciIf, MV_U32 devNum) -+{ -+ MV_U32 pciP2PConfig; -+ MV_PCI_MODE pciMode; -+ MV_U32 localBus; -+ MV_U32 localDev; -+ -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciLocalDevNumSet: ERR. Invalid PCI interface %d\n",pciIf); -+ return MV_BAD_PARAM; -+ } -+ if (devNum >= MAX_PCI_DEVICES) -+ { -+ mvOsPrintf("mvPciLocalDevNumSet: ERR. device number illigal %d\n", -+ devNum); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ localBus = mvPciLocalBusNumGet(pciIf); -+ localDev = mvPciLocalDevNumGet(pciIf); -+ -+ /* PCI interface mode */ -+ mvPciModeGet(pciIf, &pciMode); -+ -+ /* if PCI type is PCIX then it is not allowed to change the dev number */ -+ if (MV_PCIX == pciMode.pciType) -+ { -+ pciP2PConfig = mvPciConfigRead(pciIf, localBus, localDev, 0, PCIX_STATUS ); -+ -+ pciP2PConfig &= ~PXS_DN_MASK; -+ -+ pciP2PConfig |= (devNum << PXS_DN_OFFS) & PXS_DN_MASK; -+ -+ mvPciConfigWrite(pciIf,localBus, localDev, 0, PCIX_STATUS,pciP2PConfig ); -+ } -+ else -+ { -+ pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); -+ -+ pciP2PConfig &= ~PPCR_DEV_NUM_MASK; -+ -+ pciP2PConfig |= (devNum << PPCR_DEV_NUM_OFFS) & PPCR_DEV_NUM_MASK; -+ -+ MV_REG_WRITE(PCI_P2P_CONFIG_REG(pciIf), pciP2PConfig); -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvPciLocalDevNumGet - Get PCI interface local device number. -+* -+* DESCRIPTION: -+* This function gets the local device number of a given PCI interface. -+* -+* INPUT: -+* pciIf - PCI interface number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Local device number. 0xffffffff on Error -+* -+*******************************************************************************/ -+MV_U32 mvPciLocalDevNumGet(MV_U32 pciIf) -+{ -+ MV_U32 pciP2PConfig; -+ -+ /* Parameter checking */ -+ -+ if (PCI_DEFAULT_IF != pciIf) -+ { -+ if (pciIf >= mvCtrlPciMaxIfGet()) -+ { -+ mvOsPrintf("mvPciLocalDevNumGet: ERR. Invalid PCI interface %d\n", -+ pciIf); -+ return 0xFFFFFFFF; -+ } -+ } -+ -+ pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); -+ -+ pciP2PConfig &= PPCR_DEV_NUM_MASK; -+ -+ return (pciP2PConfig >> PPCR_DEV_NUM_OFFS); -+} -+ -+ -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,185 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#ifndef __INCPCIH -+#define __INCPCIH -+ -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+#include "pci/mvPciRegs.h" -+ -+ -+/* NOTE not supported in this driver: -+ -+ Built In Self Test (BIST) -+ Vital Product Data (VPD) -+ Message Signaled Interrupt (MSI) -+ Power Management -+ Compact PCI Hot Swap -+ Header retarget -+ -+Registers not supported: -+1) PCI DLL Status and Control (PCI0 0x1D20, PCI1 0x1DA0) -+2) PCI/MPP Pads Calibration (CI0/MPP[31:16] 0x1D1C, PCI1/MPP[15:0] 0X1D9C) -+*/ -+ -+/* defines */ -+/* The number of supported PCI interfaces depend on Marvell controller */ -+/* device number. This device number ID is located on the PCI unit */ -+/* configuration header. This creates a loop where calling PCI */ -+/* configuration read/write routine results a call to get PCI configuration */ -+/* information etc. This macro defines a default PCI interface. This PCI */ -+/* interface is sure to exist. */ -+#define PCI_DEFAULT_IF 0 -+ -+ -+/* typedefs */ -+/* The Marvell controller supports both conventional PCI and PCI-X. */ -+/* This enumeration describes the PCI type. */ -+typedef enum _mvPciType -+{ -+ MV_PCI_CONV, /* Conventional PCI */ -+ MV_PCIX /* PCI-X */ -+}MV_PCI_TYPE; -+ -+typedef enum _mvPciMod -+{ -+ MV_PCI_MOD_HOST, -+ MV_PCI_MOD_DEVICE -+}MV_PCI_MOD; -+ -+ -+/* The Marvell controller supports both PCI width of 32 and 64 bit. */ -+/* This enumerator describes PCI width */ -+typedef enum _mvPciWidth -+{ -+ MV_PCI_32, /* PCI width 32bit */ -+ MV_PCI_64 /* PCI width 64bit */ -+}MV_PCI_WIDTH; -+ -+/* This structure describes the PCI unit configured type, speed and width. */ -+typedef struct _mvPciMode -+{ -+ MV_PCI_TYPE pciType; /* PCI type */ -+ MV_U32 pciSpeed; /* Assuming PCI base clock on board is 33MHz */ -+ MV_PCI_WIDTH pciWidth; /* PCI bus width */ -+}MV_PCI_MODE; -+ -+/* mvPciInit - Initialize PCI interfaces*/ -+MV_VOID mvPciHalInit(MV_U32 pciIf, MV_PCI_MOD pciIfmod); -+ -+/* mvPciCommandSet - Set PCI comman register value.*/ -+MV_STATUS mvPciCommandSet(MV_U32 pciIf, MV_U32 command); -+ -+/* mvPciModeGet - Get PCI interface mode.*/ -+MV_STATUS mvPciModeGet(MV_U32 pciIf, MV_PCI_MODE *pPciMode); -+ -+/* mvPciRetrySet - Set PCI retry counters*/ -+MV_STATUS mvPciRetrySet(MV_U32 pciIf, MV_U32 counter); -+ -+/* mvPciDiscardTimerSet - Set PCI discard timer*/ -+MV_STATUS mvPciDiscardTimerSet(MV_U32 pciIf, MV_U32 pClkCycles); -+ -+/* mvPciArbEnable - PCI arbiter enable/disable*/ -+MV_STATUS mvPciArbEnable(MV_U32 pciIf, MV_BOOL enable); -+ -+/* mvPciArbParkDis - Disable arbiter parking on agent */ -+MV_STATUS mvPciArbParkDis(MV_U32 pciIf, MV_U32 pciAgentMask); -+ -+/* mvPciArbBrokDetectSet - Set PCI arbiter broken detection */ -+MV_STATUS mvPciArbBrokDetectSet(MV_U32 pciIf, MV_U32 pClkCycles); -+ -+/* mvPciConfigRead - Read from configuration space */ -+MV_U32 mvPciConfigRead (MV_U32 pciIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func,MV_U32 regOff); -+ -+/* mvPciConfigWrite - Write to configuration space */ -+MV_STATUS mvPciConfigWrite(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data); -+ -+/* mvPciMasterEnable - Enable/disale PCI interface master transactions.*/ -+MV_STATUS mvPciMasterEnable(MV_U32 pciIf, MV_BOOL enable); -+ -+/* mvPciSlaveEnable - Enable/disale PCI interface slave transactions.*/ -+MV_STATUS mvPciSlaveEnable(MV_U32 pciIf, MV_U32 bus, MV_U32 dev,MV_BOOL enable); -+ -+/* mvPciLocalBusNumSet - Set PCI interface local bus number.*/ -+MV_STATUS mvPciLocalBusNumSet(MV_U32 pciIf, MV_U32 busNum); -+ -+/* mvPciLocalBusNumGet - Get PCI interface local bus number.*/ -+MV_U32 mvPciLocalBusNumGet(MV_U32 pciIf); -+ -+/* mvPciLocalDevNumSet - Set PCI interface local device number.*/ -+MV_STATUS mvPciLocalDevNumSet(MV_U32 pciIf, MV_U32 devNum); -+ -+/* mvPciLocalDevNumGet - Get PCI interface local device number.*/ -+MV_U32 mvPciLocalDevNumGet(MV_U32 pciIf); -+ -+ -+#endif /* #ifndef __INCPCIH */ -+ -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,411 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCPCIREGSH -+#define __INCPCIREGSH -+ -+ -+#include "pci-if/mvPciIfRegs.h" -+/* defines */ -+#define MAX_PCI_DEVICES 32 -+#define MAX_PCI_FUNCS 8 -+#define MAX_PCI_BUSSES 128 -+ -+/* enumerators */ -+ -+/* This enumerator described the possible PCI slave targets. */ -+/* PCI slave targets are designated memory/IO address spaces that the */ -+/* PCI slave targets can access. They are also refered as "targets" */ -+/* this enumeratoe order is determined by the content of : -+ PCI_BASE_ADDR_ENABLE_REG */ -+ -+ -+/* registers offsetes defines */ -+ -+ -+ -+/*************************/ -+/* PCI control registers */ -+/*************************/ -+/* maen : should add new registers */ -+#define PCI_CMD_REG(pciIf) (0x30c00 + ((pciIf) * 0x80)) -+#define PCI_MODE_REG(pciIf) (0x30d00 + ((pciIf) * 0x80)) -+#define PCI_RETRY_REG(pciIf) (0x30c04 + ((pciIf) * 0x80)) -+#define PCI_DISCARD_TIMER_REG(pciIf) (0x30d04 + ((pciIf) * 0x80)) -+#define PCI_ARBITER_CTRL_REG(pciIf) (0x31d00 + ((pciIf) * 0x80)) -+#define PCI_P2P_CONFIG_REG(pciIf) (0x31d14 + ((pciIf) * 0x80)) -+#define PCI_ACCESS_CTRL_BASEL_REG(pciIf, targetWin) \ -+ (0x31e00 + ((pciIf) * 0x80) + ((targetWin) * 0x10)) -+#define PCI_ACCESS_CTRL_BASEH_REG(pciIf, targetWin) \ -+ (0x31e04 + ((pciIf) * 0x80) + ((targetWin) * 0x10)) -+#define PCI_ACCESS_CTRL_SIZE_REG(pciIf, targetWin) \ -+ (0x31e08 + ((pciIf) * 0x80) + ((targetWin) * 0x10)) -+ -+#define PCI_DLL_CTRL_REG(pciIf) (0x31d20 + ((pciIf) * 0x80)) -+ -+/* PCI Dll Control (PDC)*/ -+#define PDC_DLL_EN BIT0 -+ -+ -+/* PCI Command Register (PCR) */ -+#define PCR_MASTER_BYTE_SWAP_EN BIT0 -+#define PCR_MASTER_WR_COMBINE_EN BIT4 -+#define PCR_MASTER_RD_COMBINE_EN BIT5 -+#define PCR_MASTER_WR_TRIG_WHOLE BIT6 -+#define PCR_MASTER_RD_TRIG_WHOLE BIT7 -+#define PCR_MASTER_MEM_RD_LINE_EN BIT8 -+#define PCR_MASTER_MEM_RD_MULT_EN BIT9 -+#define PCR_MASTER_WORD_SWAP_EN BIT10 -+#define PCR_SLAVE_WORD_SWAP_EN BIT11 -+#define PCR_NS_ACCORDING_RCV_TRANS BIT14 -+#define PCR_MASTER_PCIX_REQ64N_EN BIT15 -+#define PCR_SLAVE_BYTE_SWAP_EN BIT16 -+#define PCR_MASTER_DAC_EN BIT17 -+#define PCR_MASTER_M64_ALLIGN BIT18 -+#define PCR_ERRORS_PROPAGATION_EN BIT19 -+#define PCR_SLAVE_SWAP_ENABLE BIT20 -+#define PCR_MASTER_SWAP_ENABLE BIT21 -+#define PCR_MASTER_INT_SWAP_EN BIT22 -+#define PCR_LOOP_BACK_ENABLE BIT23 -+#define PCR_SLAVE_INTREG_SWAP_OFFS 24 -+#define PCR_SLAVE_INTREG_SWAP_MASK 0x3 -+#define PCR_SLAVE_INTREG_BYTE_SWAP \ -+ (MV_BYTE_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) -+#define PCR_SLAVE_INTREG_NO_SWAP \ -+ (MV_NO_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) -+#define PCR_SLAVE_INTREG_BYTE_WORD \ -+ (MV_BYTE_WORD_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) -+#define PCR_SLAVE_INTREG_WORD_SWAP \ -+ (MV_WORD_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) -+#define PCR_RESET_REASSERTION_EN BIT26 -+#define PCR_PCI_TO_CPU_REG_ORDER_EN BIT28 -+#define PCR_CPU_TO_PCI_ORDER_EN BIT29 -+#define PCR_PCI_TO_CPU_ORDER_EN BIT30 -+ -+/* PCI Mode Register (PMR) */ -+#define PMR_PCI_ID_OFFS 0 /* PCI Interface ID */ -+#define PMR_PCI_ID_MASK (0x1 << PMR_PCI_ID_OFFS) -+#define PMR_PCI_ID_PCI(pciNum) ((pciNum) << PCI_MODE_PCIID_OFFS) -+ -+#define PMR_PCI_64_OFFS 2 /* 64-bit PCI Interface */ -+#define PMR_PCI_64_MASK (0x1 << PMR_PCI_64_OFFS) -+#define PMR_PCI_64_64BIT (0x1 << PMR_PCI_64_OFFS) -+#define PMR_PCI_64_32BIT (0x0 << PMR_PCI_64_OFFS) -+ -+#define PMR_PCI_MODE_OFFS 4 /* PCI interface mode of operation */ -+#define PMR_PCI_MODE_MASK (0x3 << PMR_PCI_MODE_OFFS) -+#define PMR_PCI_MODE_CONV (0x0 << PMR_PCI_MODE_OFFS) -+#define PMR_PCI_MODE_PCIX_66MHZ (0x1 << PMR_PCI_MODE_OFFS) -+#define PMR_PCI_MODE_PCIX_100MHZ (0x2 << PMR_PCI_MODE_OFFS) -+#define PMR_PCI_MODE_PCIX_133MHZ (0x3 << PMR_PCI_MODE_OFFS) -+ -+#define PMR_EXP_ROM_SUPPORT BIT8 /* Expansion ROM Active */ -+ -+#define PMR_PCI_RESET_OFFS 31 /* PCI Interface Reset Indication */ -+#define PMR_PCI_RESET_MASK (0x1 << PMR_PCI_RESET_OFFS) -+#define PMR_PCI_RESET_PCIXRST (0x0 << PMR_PCI_RESET_OFFS) -+ -+ -+/* PCI Retry Register (PRR) */ -+#define PRR_RETRY_CNTR_OFFS 16 /* Retry Counter */ -+#define PRR_RETRY_CNTR_MAX 0xff -+#define PRR_RETRY_CNTR_MASK (PRR_RETRY_CNTR_MAX << PRR_RETRY_CNTR_OFFS) -+ -+ -+/* PCI Discard Timer Register (PDTR) */ -+#define PDTR_TIMER_OFFS 0 /* Timer */ -+#define PDTR_TIMER_MAX 0xffff -+#define PDTR_TIMER_MIN 0x7F -+#define PDTR_TIMER_MASK (PDTR_TIMER_MAX << PDTR_TIMER_OFFS) -+ -+ -+/* PCI Arbiter Control Register (PACR) */ -+#define PACR_BROKEN_DETECT_EN BIT1 /* Broken Detection Enable */ -+ -+#define PACR_BROKEN_VAL_OFFS 3 /* Broken Value */ -+#define PACR_BROKEN_VAL_MASK (0xf << PACR_BROKEN_VAL_OFFS) -+#define PACR_BROKEN_VAL_CONV_MIN 0x2 -+#define PACR_BROKEN_VAL_PCIX_MIN 0x6 -+ -+#define PACR_PARK_DIS_OFFS 14 /* Parking Disable */ -+#define PACR_PARK_DIS_MAX_AGENT 0x3f -+#define PACR_PARK_DIS_MASK (PACR_PARK_DIS_MAX_AGENT<= MV_PCI_START_IF)&&(pciIf < MV_PCI_MAX_IF + MV_PCI_START_IF)) -+ { -+ return PCI_IF_TYPE_CONVEN_PCIX; -+ } -+ else if ((pciIf >= MV_PEX_START_IF) && -+ (pciIf < MV_PEX_MAX_IF + MV_PEX_START_IF)) -+ { -+ return PCI_IF_TYPE_PEX; -+ -+ } -+ else -+ { -+ mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf); -+ } -+ -+ return 0xffffffff; -+ -+} -+ -+/******************************************************************************* -+* mvPciIfTypeGet - -+* -+* DESCRIPTION: -+* -+* INPUT: -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* -+*******************************************************************************/ -+ -+MV_U32 mvPciRealIfNumGet(MV_U32 pciIf) -+{ -+ -+ PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf); -+ -+ if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType) -+ { -+ return (pciIf - MV_PCI_START_IF); -+ } -+ else if (PCI_IF_TYPE_PEX == pciIfType) -+ { -+ return (pciIf - MV_PEX_START_IF); -+ -+ } -+ else -+ { -+ mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf); -+ } -+ -+ return 0xffffffff; -+ -+} -+ -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,134 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCPCIIFH -+#define __INCPCIIFH -+ -+#include "mvSysHwConfig.h" -+#include "pci-if/mvPciIfRegs.h" -+#if defined(MV_INCLUDE_PEX) -+#include "pex/mvPex.h" -+#endif -+#if defined(MV_INCLUDE_PCI) -+#include "pci/mvPci.h" -+#endif -+#include "ctrlEnv/mvCtrlEnvLib.h" -+#include "ctrlEnv/mvCtrlEnvAddrDec.h" -+ -+typedef enum _mvPCIIfType -+{ -+ PCI_IF_TYPE_CONVEN_PCIX, -+ PCI_IF_TYPE_PEX -+ -+}PCI_IF_TYPE; -+ -+typedef enum _mvPCIIfMode -+{ -+ PCI_IF_MODE_HOST, -+ PCI_IF_MODE_DEVICE -+}PCI_IF_MODE; -+ -+ -+/* Global Functions prototypes */ -+ -+/* mvPciIfInit - Initialize PCI interfaces*/ -+MV_STATUS mvPciIfInit(MV_U32 pciIf, PCI_IF_MODE pciIfmode); -+ -+/* mvPciIfConfigRead - Read from configuration space */ -+MV_U32 mvPciIfConfigRead (MV_U32 pciIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func,MV_U32 regOff); -+ -+/* mvPciIfConfigWrite - Write to configuration space */ -+MV_STATUS mvPciIfConfigWrite(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data); -+ -+/* mvPciIfMasterEnable - Enable/disale PCI interface master transactions.*/ -+MV_STATUS mvPciIfMasterEnable(MV_U32 pciIf, MV_BOOL enable); -+ -+/* mvPciIfSlaveEnable - Enable/disale PCI interface slave transactions.*/ -+MV_STATUS mvPciIfSlaveEnable(MV_U32 pciIf,MV_U32 bus, MV_U32 dev, -+ MV_BOOL enable); -+ -+/* mvPciIfLocalBusNumSet - Set PCI interface local bus number.*/ -+MV_STATUS mvPciIfLocalBusNumSet(MV_U32 pciIf, MV_U32 busNum); -+ -+/* mvPciIfLocalBusNumGet - Get PCI interface local bus number.*/ -+MV_U32 mvPciIfLocalBusNumGet(MV_U32 pciIf); -+ -+/* mvPciIfLocalDevNumSet - Set PCI interface local device number.*/ -+MV_STATUS mvPciIfLocalDevNumSet(MV_U32 pciIf, MV_U32 devNum); -+ -+/* mvPciIfLocalDevNumGet - Get PCI interface local device number.*/ -+MV_U32 mvPciIfLocalDevNumGet(MV_U32 pciIf); -+ -+/* mvPciIfTypeGet - Get PCI If type*/ -+PCI_IF_TYPE mvPciIfTypeGet(MV_U32 pciIf); -+ -+MV_U32 mvPciRealIfNumGet(MV_U32 pciIf); -+ -+/* mvPciIfAddrDecShow - Display address decode windows attributes */ -+MV_VOID mvPciIfAddrDecShow(MV_VOID); -+ -+#endif /* #ifndef __INCPCIIFH */ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,245 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCPCIIFREGSH -+#define __INCPCIIFREGSH -+ -+ -+/* defines */ -+#define MAX_PCI_DEVICES 32 -+#define MAX_PCI_FUNCS 8 -+#define MAX_PCI_BUSSES 128 -+ -+/***************************************/ -+/* PCI Configuration registers */ -+/***************************************/ -+ -+/*********************************************/ -+/* PCI Configuration, Function 0, Registers */ -+/*********************************************/ -+ -+ -+/* Standard registers */ -+#define PCI_DEVICE_AND_VENDOR_ID 0x000 -+#define PCI_STATUS_AND_COMMAND 0x004 -+#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 -+#define PCI_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE 0x00C -+#define PCI_MEMORY_BAR_BASE_ADDR(barNum) (0x010 + ((barNum) << 2)) -+#define PCI_SUBSYS_ID_AND_SUBSYS_VENDOR_ID 0x02C -+#define PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030 -+#define PCI_CAPABILTY_LIST_POINTER 0x034 -+#define PCI_INTERRUPT_PIN_AND_LINE 0x03C -+ -+ -+/* PCI Device and Vendor ID Register (PDVIR) */ -+#define PDVIR_VEN_ID_OFFS 0 /* Vendor ID */ -+#define PDVIR_VEN_ID_MASK (0xffff << PDVIR_VEN_ID_OFFS) -+ -+#define PDVIR_DEV_ID_OFFS 16 /* Device ID */ -+#define PDVIR_DEV_ID_MASK (0xffff << PDVIR_DEV_ID_OFFS) -+ -+/* PCI Status and Command Register (PSCR) */ -+#define PSCR_IO_EN BIT0 /* IO Enable */ -+#define PSCR_MEM_EN BIT1 /* Memory Enable */ -+#define PSCR_MASTER_EN BIT2 /* Master Enable */ -+#define PSCR_SPECIAL_EN BIT3 /* Special Cycle Enable */ -+#define PSCR_MEM_WRI_INV BIT4 /* Memory Write and Invalidate Enable */ -+#define PSCR_VGA BIT5 /* VGA Palette Snoops */ -+#define PSCR_PERR_EN BIT6 /* Parity Errors Respond Enable */ -+#define PSCR_ADDR_STEP BIT7 /* Address Stepping Enable (Wait Cycle En)*/ -+#define PSCR_SERR_EN BIT8 /* Ability to assert SERR# line */ -+#define PSCR_FAST_BTB_EN BIT9 /* generate fast back-to-back transactions*/ -+#define PSCR_CAP_LIST BIT20 /* Capability List Support */ -+#define PSCR_66MHZ_EN BIT21 /* 66 MHz Capable */ -+#define PSCR_UDF_EN BIT22 /* User definable features */ -+#define PSCR_TAR_FAST_BB BIT23 /* fast back-to-back transactions capable */ -+#define PSCR_DATA_PERR BIT24 /* Data Parity reported */ -+ -+#define PSCR_DEVSEL_TIM_OFFS 25 /* DEVSEL timing */ -+#define PSCR_DEVSEL_TIM_MASK (0x3 << PSCR_DEVSEL_TIM_OFFS) -+#define PSCR_DEVSEL_TIM_FAST (0x0 << PSCR_DEVSEL_TIM_OFFS) -+#define PSCR_DEVSEL_TIM_MED (0x1 << PSCR_DEVSEL_TIM_OFFS) -+#define PSCR_DEVSEL_TIM_SLOW (0x2 << PSCR_DEVSEL_TIM_OFFS) -+ -+#define PSCR_SLAVE_TABORT BIT27 /* Signalled Target Abort */ -+#define PSCR_MASTER_TABORT BIT28 /* Recieved Target Abort */ -+#define PSCR_MABORT BIT29 /* Recieved Master Abort */ -+#define PSCR_SYSERR BIT30 /* Signalled system error */ -+#define PSCR_DET_PARERR BIT31 /* Detect Parity Error */ -+ -+/* PCI configuration register offset=0x08 fields -+ (PCI_CLASS_CODE_AND_REVISION_ID)(PCCRI) */ -+ -+#define PCCRIR_REVID_OFFS 0 /* Revision ID */ -+#define PCCRIR_REVID_MASK (0xff << PCCRIR_REVID_OFFS) -+ -+#define PCCRIR_FULL_CLASS_OFFS 8 /* Full Class Code */ -+#define PCCRIR_FULL_CLASS_MASK (0xffffff << PCCRIR_FULL_CLASS_OFFS) -+ -+#define PCCRIR_PROGIF_OFFS 8 /* Prog .I/F*/ -+#define PCCRIR_PROGIF_MASK (0xff << PCCRIR_PROGIF_OFFS) -+ -+#define PCCRIR_SUB_CLASS_OFFS 16 /* Sub Class*/ -+#define PCCRIR_SUB_CLASS_MASK (0xff << PCCRIR_SUB_CLASS_OFFS) -+ -+#define PCCRIR_BASE_CLASS_OFFS 24 /* Base Class*/ -+#define PCCRIR_BASE_CLASS_MASK (0xff << PCCRIR_BASE_CLASS_OFFS) -+ -+/* PCI configuration register offset=0x0C fields -+ (PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE)(PBHTLTCL) */ -+ -+#define PBHTLTCLR_CACHELINE_OFFS 0 /* Specifies the cache line size */ -+#define PBHTLTCLR_CACHELINE_MASK (0xff << PBHTLTCLR_CACHELINE_OFFS) -+ -+#define PBHTLTCLR_LATTIMER_OFFS 8 /* latency timer */ -+#define PBHTLTCLR_LATTIMER_MASK (0xff << PBHTLTCLR_LATTIMER_OFFS) -+ -+#define PBHTLTCLR_HEADTYPE_FULL_OFFS 16 /* Full Header Type */ -+#define PBHTLTCLR_HEADTYPE_FULL_MASK (0xff << PBHTLTCLR_HEADTYPE_FULL_OFFS) -+ -+#define PBHTLTCLR_MULTI_FUNC BIT23 /* Multi/Single function */ -+ -+#define PBHTLTCLR_HEADER_OFFS 16 /* Header type */ -+#define PBHTLTCLR_HEADER_MASK (0x7f << PBHTLTCLR_HEADER_OFFS) -+#define PBHTLTCLR_HEADER_STANDARD (0x0 << PBHTLTCLR_HEADER_OFFS) -+#define PBHTLTCLR_HEADER_PCI2PCI_BRIDGE (0x1 << PBHTLTCLR_HEADER_OFFS) -+ -+ -+#define PBHTLTCLR_BISTCOMP_OFFS 24 /* BIST Completion Code */ -+#define PBHTLTCLR_BISTCOMP_MASK (0xf << PBHTLTCLR_BISTCOMP_OFFS) -+ -+#define PBHTLTCLR_BISTACT BIT30 /* BIST Activate bit */ -+#define PBHTLTCLR_BISTCAP BIT31 /* BIST Capable Bit */ -+ -+ -+/* PCI Bar Base Low Register (PBBLR) */ -+#define PBBLR_IOSPACE BIT0 /* Memory Space Indicator */ -+ -+#define PBBLR_TYPE_OFFS 1 /* BAR Type/Init Val. */ -+#define PBBLR_TYPE_MASK (0x3 << PBBLR_TYPE_OFFS) -+#define PBBLR_TYPE_32BIT_ADDR (0x0 << PBBLR_TYPE_OFFS) -+#define PBBLR_TYPE_64BIT_ADDR (0x2 << PBBLR_TYPE_OFFS) -+ -+#define PBBLR_PREFETCH_EN BIT3 /* Prefetch Enable */ -+ -+ -+#define PBBLR_MEM_BASE_OFFS 4 /* Memory Bar Base address. Corresponds to -+ address bits [31:4] */ -+#define PBBLR_MEM_BASE_MASK (0xfffffff << PBBLR_MEM_BASE_OFFS) -+ -+#define PBBLR_IO_BASE_OFFS 2 /* IO Bar Base address. Corresponds to -+ address bits [31:2] */ -+#define PBBLR_IO_BASE_MASK (0x3fffffff << PBBLR_IO_BASE_OFFS) -+ -+ -+#define PBBLR_BASE_OFFS 12 /* Base address. Address bits [31:12] */ -+#define PBBLR_BASE_MASK (0xfffff << PBBLR_BASE_OFFS) -+#define PBBLR_BASE_ALIGNMET (1 << PBBLR_BASE_OFFS) -+ -+ -+/* PCI Bar Base High Fegister (PBBHR) */ -+#define PBBHR_BASE_OFFS 0 /* Base address. Address bits [31:12] */ -+#define PBBHR_BASE_MASK (0xffffffff << PBBHR_BASE_OFFS) -+ -+ -+/* PCI configuration register offset=0x2C fields -+ (PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID)(PSISVI) */ -+ -+#define PSISVIR_VENID_OFFS 0 /* Subsystem Manufacturer Vendor ID Number */ -+#define PSISVIR_VENID_MASK (0xffff << PSISVIR_VENID_OFFS) -+ -+#define PSISVIR_DEVID_OFFS 16 /* Subsystem Device ID Number */ -+#define PSISVIR_DEVID_MASK (0xffff << PSISVIR_DEVID_OFFS) -+ -+/* PCI configuration register offset=0x30 fields -+ (PCI_EXPANSION_ROM_BASE_ADDR_REG)(PERBA) */ -+ -+#define PERBAR_EXPROMEN BIT0 /* Expansion ROM Enable */ -+ -+#define PERBAR_BASE_OFFS 12 /* Expansion ROM Base Address */ -+#define PERBAR_BASE_MASK (0xfffff << PERBAR_BASE_OFFS) -+ -+/* PCI configuration register offset=0x34 fields -+ (PCI_CAPABILTY_LIST_POINTER)(PCLP) */ -+ -+#define PCLPR_CAPPTR_OFFS 0 /* Capability List Pointer */ -+#define PCLPR_CAPPTR_MASK (0xff << PCLPR_CAPPTR_OFFS) -+ -+/* PCI configuration register offset=0x3C fields -+ (PCI_INTERRUPT_PIN_AND_LINE)(PIPL) */ -+ -+#define PIPLR_INTLINE_OFFS 0 /* Interrupt line (IRQ) */ -+#define PIPLR_INTLINE_MASK (0xff << PIPLR_INTLINE_OFFS) -+ -+#define PIPLR_INTPIN_OFFS 8 /* interrupt pin (A,B,C,D) */ -+#define PIPLR_INTPIN_MASK (0xff << PIPLR_INTPIN_OFFS) -+ -+#define PIPLR_MINGRANT_OFFS 16 /* Minimum Grant on 250 nano seconds units */ -+#define PIPLR_MINGRANT_MASK (0xff << PIPLR_MINGRANT_OFFS) -+ -+#define PIPLR_MAXLATEN_OFFS 24 /* Maximum latency on 250 nano seconds units */ -+#define PIPLR_MAXLATEN_MASK (0xff << PIPLR_MAXLATEN_OFFS) -+ -+#endif /* #ifndef __INCPCIIFREGSH */ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,1006 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+/* includes */ -+#include "mvPciUtils.h" -+ -+#include "ctrlEnv/mvCtrlEnvLib.h" -+ -+/* #define MV_DEBUG */ -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+ #define mvOsPrintf printf -+#else -+ #define DB(x) -+#endif -+ -+/* -+This module only support scanning of Header type 00h of pci devices -+There is no suppotr for Header type 01h of pci devices ( PCI bridges ) -+*/ -+ -+ -+static MV_STATUS pciDetectDevice(MV_U32 pciIf, -+ MV_U32 bus, -+ MV_U32 dev, -+ MV_U32 func, -+ MV_PCI_DEVICE *pPciAgent); -+ -+static MV_U32 pciDetectDeviceBars(MV_U32 pciIf, -+ MV_U32 bus, -+ MV_U32 dev, -+ MV_U32 func, -+ MV_PCI_DEVICE *pPciAgent); -+ -+ -+ -+ -+ -+ -+/******************************************************************************* -+* mvPciScan - Scan a PCI interface bus -+* -+* DESCRIPTION: -+* Performs a full scan on a PCI interface and returns all possible details -+* on the agents found on the bus. -+* -+* INPUT: -+* pciIf - PCI Interface -+* pPciAgents - Pointer to an Array of the pci agents to be detected -+* pPciAgentsNum - pPciAgents array maximum number of elements -+* -+* OUTPUT: -+* pPciAgents - Array of the pci agents detected on the bus -+* pPciAgentsNum - Number of pci agents detected on the bus -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+ -+MV_STATUS mvPciScan(MV_U32 pciIf, -+ MV_PCI_DEVICE *pPciAgents, -+ MV_U32 *pPciAgentsNum) -+{ -+ -+ MV_U32 devIndex,funcIndex=0,busIndex=0,detectedDevNum=0; -+ MV_U32 localBus=mvPciIfLocalBusNumGet(pciIf); -+ MV_PCI_DEVICE *pPciDevice; -+ MV_PCI_DEVICE *pMainDevice; -+ -+ DB(mvOsPrintf("mvPciScan: PCI interface num %d\n", pciIf)); -+ /* Parameter checking */ -+ if (pciIf >= mvCtrlPexMaxIfGet()) -+ { -+ DB(mvOsPrintf("mvPciScan: ERR. Invalid PCI interface num %d\n", pciIf)); -+ return MV_BAD_PARAM; -+ } -+ if (NULL == pPciAgents) -+ { -+ DB(mvOsPrintf("mvPciScan: ERR. pPciAgents=NULL \n")); -+ return MV_BAD_PARAM; -+ } -+ if (NULL == pPciAgentsNum) -+ { -+ DB(mvOsPrintf("mvPciScan: ERR. pPciAgentsNum=NULL \n")); -+ return MV_BAD_PARAM; -+ } -+ -+ -+ DB(mvOsPrintf("mvPciScan: PCI interface num %d mvPciMasterEnable\n", pciIf)); -+ /* Master enable the MV PCI master */ -+ if (MV_OK != mvPciIfMasterEnable(pciIf,MV_TRUE)) -+ { -+ DB(mvOsPrintf("mvPciScan: ERR. mvPciMasterEnable failed \n")); -+ return MV_ERROR; -+ -+ } -+ -+ DB(mvOsPrintf("mvPciScan: PCI interface num scan%d\n", pciIf)); -+ -+ /* go through all busses */ -+ for (busIndex=localBus ; busIndex < MAX_PCI_BUSSES ; busIndex++) -+ { -+ /* go through all possible devices on the local bus */ -+ for (devIndex=0 ; devIndex < MAX_PCI_DEVICES ; devIndex++) -+ { -+ /* always start with function equal to zero */ -+ funcIndex=0; -+ -+ pPciDevice=&pPciAgents[detectedDevNum]; -+ DB(mvOsPrintf("mvPciScan: PCI interface num scan%d:%d\n", busIndex, devIndex)); -+ -+ if (MV_ERROR == pciDetectDevice(pciIf, -+ busIndex, -+ devIndex, -+ funcIndex, -+ pPciDevice)) -+ { -+ /* no device detected , try the next address */ -+ continue; -+ } -+ -+ /* We are here ! means we have detected a device*/ -+ /* always we start with only one function per device */ -+ pMainDevice = pPciDevice; -+ pPciDevice->funtionsNum = 1; -+ -+ -+ /* move on */ -+ detectedDevNum++; -+ -+ -+ /* check if we have no more room for a new device */ -+ if (detectedDevNum == *pPciAgentsNum) -+ { -+ DB(mvOsPrintf("mvPciScan: ERR. array passed too small \n")); -+ return MV_ERROR; -+ } -+ -+ /* check the detected device if it is a multi functional device then -+ scan all device functions*/ -+ if (pPciDevice->isMultiFunction == MV_TRUE) -+ { -+ /* start with function number 1 because we have already detected -+ function 0 */ -+ for (funcIndex=1; funcIndexfuntionsNum++; -+ detectedDevNum++; -+ -+ /* check if we have no more room for a new device */ -+ if (detectedDevNum == *pPciAgentsNum) -+ { -+ DB(mvOsPrintf("mvPciScan: ERR. Array too small\n")); -+ return MV_ERROR; -+ } -+ -+ -+ } -+ } -+ -+ } -+ -+ } -+ -+ /* return the number of devices actually detected on the bus ! */ -+ *pPciAgentsNum = detectedDevNum; -+ -+ return MV_OK; -+ -+} -+ -+ -+/******************************************************************************* -+* pciDetectDevice - Detect a pci device parameters -+* -+* DESCRIPTION: -+* This function detect if a pci agent exist on certain address ! -+* and if exists then it fills all possible information on the -+* agent -+* -+* INPUT: -+* pciIf - PCI Interface -+* bus - Bus number -+* dev - Device number -+* func - Function number -+* -+* -+* -+* OUTPUT: -+* pPciAgent - pointer to the pci agent filled with its information -+* -+* RETURN: -+* MV_ERROR if no device , MV_OK otherwise -+* -+*******************************************************************************/ -+ -+static MV_STATUS pciDetectDevice(MV_U32 pciIf, -+ MV_U32 bus, -+ MV_U32 dev, -+ MV_U32 func, -+ MV_PCI_DEVICE *pPciAgent) -+{ -+ MV_U32 pciData; -+ -+ /* no Parameters checking ! because it is static function and it is assumed -+ that all parameters were checked in the calling function */ -+ -+ -+ /* Try read the PCI Vendor ID and Device ID */ -+ -+ /* We will scan only ourselves and the PCI slots that exist on the -+ board, because we may have a case that we have one slot that has -+ a Cardbus connector, and because CardBus answers all IDsels we want -+ to scan only this slot and ourseleves. -+ -+ */ -+ #if defined(MV_INCLUDE_PCI) -+ if ((PCI_IF_TYPE_CONVEN_PCIX == mvPciIfTypeGet(pciIf)) && -+ (DB_88F5181_DDR1_PRPMC != mvBoardIdGet()) && -+ (DB_88F5181_DDR1_PEXPCI != mvBoardIdGet()) && -+ (DB_88F5181_DDR1_MNG != mvBoardIdGet())) -+ { -+ -+ if (mvBoardIsOurPciSlot(bus, dev) == MV_FALSE) -+ { -+ return MV_ERROR; -+ } -+ } -+ #endif /* defined(MV_INCLUDE_PCI) */ -+ -+ pciData = mvPciIfConfigRead(pciIf, bus,dev,func, PCI_DEVICE_AND_VENDOR_ID); -+ -+ if (PCI_ERROR_CODE == pciData) -+ { -+ /* no device exist */ -+ return MV_ERROR; -+ } -+ -+ /* we are here ! means a device is detected */ -+ -+ /* fill basic information */ -+ pPciAgent->busNumber=bus; -+ pPciAgent->deviceNum=dev; -+ pPciAgent->function=func; -+ -+ /* Fill the PCI Vendor ID and Device ID */ -+ -+ pPciAgent->venID = (pciData & PDVIR_VEN_ID_MASK) >> PDVIR_VEN_ID_OFFS; -+ pPciAgent->deviceID = (pciData & PDVIR_DEV_ID_MASK) >> PDVIR_DEV_ID_OFFS; -+ -+ /* Read Status and command */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_STATUS_AND_COMMAND); -+ -+ -+ /* Fill related Status and Command information*/ -+ -+ if (pciData & PSCR_TAR_FAST_BB) -+ { -+ pPciAgent->isFastB2BCapable = MV_TRUE; -+ } -+ else -+ { -+ pPciAgent->isFastB2BCapable = MV_FALSE; -+ } -+ -+ if (pciData & PSCR_CAP_LIST) -+ { -+ pPciAgent->isCapListSupport=MV_TRUE; -+ } -+ else -+ { -+ pPciAgent->isCapListSupport=MV_FALSE; -+ } -+ -+ if (pciData & PSCR_66MHZ_EN) -+ { -+ pPciAgent->is66MHZCapable=MV_TRUE; -+ } -+ else -+ { -+ pPciAgent->is66MHZCapable=MV_FALSE; -+ } -+ -+ /* Read Class Code and Revision */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_CLASS_CODE_AND_REVISION_ID); -+ -+ -+ pPciAgent->baseClassCode = -+ (pciData & PCCRIR_BASE_CLASS_MASK) >> PCCRIR_BASE_CLASS_OFFS; -+ -+ pPciAgent->subClassCode = -+ (pciData & PCCRIR_SUB_CLASS_MASK) >> PCCRIR_SUB_CLASS_OFFS; -+ -+ pPciAgent->progIf = -+ (pciData & PCCRIR_PROGIF_MASK) >> PCCRIR_PROGIF_OFFS; -+ -+ pPciAgent->revisionID = -+ (pciData & PCCRIR_REVID_MASK) >> PCCRIR_REVID_OFFS; -+ -+ /* Read PCI_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE); -+ -+ -+ -+ pPciAgent->pciCacheLine= -+ (pciData & PBHTLTCLR_CACHELINE_MASK ) >> PBHTLTCLR_CACHELINE_OFFS; -+ pPciAgent->pciLatencyTimer= -+ (pciData & PBHTLTCLR_LATTIMER_MASK) >> PBHTLTCLR_LATTIMER_OFFS; -+ -+ switch (pciData & PBHTLTCLR_HEADER_MASK) -+ { -+ case PBHTLTCLR_HEADER_STANDARD: -+ -+ pPciAgent->pciHeader=MV_PCI_STANDARD; -+ break; -+ case PBHTLTCLR_HEADER_PCI2PCI_BRIDGE: -+ -+ pPciAgent->pciHeader=MV_PCI_PCI2PCI_BRIDGE; -+ break; -+ -+ } -+ -+ if (pciData & PBHTLTCLR_MULTI_FUNC) -+ { -+ pPciAgent->isMultiFunction=MV_TRUE; -+ } -+ else -+ { -+ pPciAgent->isMultiFunction=MV_FALSE; -+ } -+ -+ if (pciData & PBHTLTCLR_BISTCAP) -+ { -+ pPciAgent->isBISTCapable=MV_TRUE; -+ } -+ else -+ { -+ pPciAgent->isBISTCapable=MV_FALSE; -+ } -+ -+ -+ /* read this device pci bars */ -+ -+ pciDetectDeviceBars(pciIf, -+ bus,dev,func, -+ pPciAgent); -+ -+ -+ /* check if we are bridge*/ -+ if ((pPciAgent->baseClassCode == PCI_BRIDGE_CLASS)&& -+ (pPciAgent->subClassCode == P2P_BRIDGE_SUB_CLASS_CODE)) -+ { -+ -+ /* Read P2P_BUSSES_NUM */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ P2P_BUSSES_NUM); -+ -+ pPciAgent->p2pPrimBusNum = -+ (pciData & PBM_PRIME_BUS_NUM_MASK) >> PBM_PRIME_BUS_NUM_OFFS; -+ -+ pPciAgent->p2pSecBusNum = -+ (pciData & PBM_SEC_BUS_NUM_MASK) >> PBM_SEC_BUS_NUM_OFFS; -+ -+ pPciAgent->p2pSubBusNum = -+ (pciData & PBM_SUB_BUS_NUM_MASK) >> PBM_SUB_BUS_NUM_OFFS; -+ -+ pPciAgent->p2pSecLatencyTimer = -+ (pciData & PBM_SEC_LAT_TMR_MASK) >> PBM_SEC_LAT_TMR_OFFS; -+ -+ /* Read P2P_IO_BASE_LIMIT_SEC_STATUS */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ P2P_IO_BASE_LIMIT_SEC_STATUS); -+ -+ pPciAgent->p2pSecStatus = -+ (pciData & PIBLSS_SEC_STATUS_MASK) >> PIBLSS_SEC_STATUS_OFFS; -+ -+ -+ pPciAgent->p2pIObase = -+ (pciData & PIBLSS_IO_BASE_MASK) << PIBLSS_IO_LIMIT_OFFS; -+ -+ /* clear low address (should be zero)*/ -+ pPciAgent->p2pIObase &= PIBLSS_HIGH_ADDR_MASK; -+ -+ pPciAgent->p2pIOLimit = -+ (pciData & PIBLSS_IO_LIMIT_MASK); -+ -+ /* fill low address with 0xfff */ -+ pPciAgent->p2pIOLimit |= PIBLSS_LOW_ADDR_MASK; -+ -+ -+ switch ((pciData & PIBLSS_ADD_CAP_MASK) >> PIBLSS_ADD_CAP_OFFS) -+ { -+ case PIBLSS_ADD_CAP_16BIT: -+ -+ pPciAgent->bIO32 = MV_FALSE; -+ -+ break; -+ case PIBLSS_ADD_CAP_32BIT: -+ -+ pPciAgent->bIO32 = MV_TRUE; -+ -+ /* Read P2P_IO_BASE_LIMIT_UPPER_16 */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ P2P_IO_BASE_LIMIT_UPPER_16); -+ -+ pPciAgent->p2pIObase |= -+ (pciData & PRBU_IO_UPP_BASE_MASK) << PRBU_IO_UPP_LIMIT_OFFS; -+ -+ -+ pPciAgent->p2pIOLimit |= -+ (pciData & PRBU_IO_UPP_LIMIT_MASK); -+ -+ break; -+ -+ } -+ -+ -+ /* Read P2P_MEM_BASE_LIMIT */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ P2P_MEM_BASE_LIMIT); -+ -+ pPciAgent->p2pMemBase = -+ (pciData & PMBL_MEM_BASE_MASK) << PMBL_MEM_LIMIT_OFFS; -+ -+ /* clear low address */ -+ pPciAgent->p2pMemBase &= PMBL_HIGH_ADDR_MASK; -+ -+ pPciAgent->p2pMemLimit = -+ (pciData & PMBL_MEM_LIMIT_MASK); -+ -+ /* add 0xfffff */ -+ pPciAgent->p2pMemLimit |= PMBL_LOW_ADDR_MASK; -+ -+ -+ /* Read P2P_PREF_MEM_BASE_LIMIT */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ P2P_PREF_MEM_BASE_LIMIT); -+ -+ -+ pPciAgent->p2pPrefMemBase = -+ (pciData & PRMBL_PREF_MEM_BASE_MASK) << PRMBL_PREF_MEM_LIMIT_OFFS; -+ -+ /* get high address only */ -+ pPciAgent->p2pPrefMemBase &= PRMBL_HIGH_ADDR_MASK; -+ -+ -+ -+ pPciAgent->p2pPrefMemLimit = -+ (pciData & PRMBL_PREF_MEM_LIMIT_MASK); -+ -+ /* add 0xfffff */ -+ pPciAgent->p2pPrefMemLimit |= PRMBL_LOW_ADDR_MASK; -+ -+ switch (pciData & PRMBL_ADD_CAP_MASK) -+ { -+ case PRMBL_ADD_CAP_32BIT: -+ -+ pPciAgent->bPrefMem64 = MV_FALSE; -+ -+ /* Read P2P_PREF_BASE_UPPER_32 */ -+ pPciAgent->p2pPrefBaseUpper32Bits = 0; -+ -+ /* Read P2P_PREF_LIMIT_UPPER_32 */ -+ pPciAgent->p2pPrefLimitUpper32Bits = 0; -+ -+ break; -+ case PRMBL_ADD_CAP_64BIT: -+ -+ pPciAgent->bPrefMem64 = MV_TRUE; -+ -+ /* Read P2P_PREF_BASE_UPPER_32 */ -+ pPciAgent->p2pPrefBaseUpper32Bits = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ P2P_PREF_BASE_UPPER_32); -+ -+ /* Read P2P_PREF_LIMIT_UPPER_32 */ -+ pPciAgent->p2pPrefLimitUpper32Bits = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ P2P_PREF_LIMIT_UPPER_32); -+ -+ break; -+ -+ } -+ -+ } -+ else /* no bridge */ -+ { -+ /* Read PCI_SUBSYS_ID_AND_SUBSYS_VENDOR_ID */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_SUBSYS_ID_AND_SUBSYS_VENDOR_ID); -+ -+ -+ pPciAgent->subSysVenID = -+ (pciData & PSISVIR_VENID_MASK) >> PSISVIR_VENID_OFFS; -+ pPciAgent->subSysID = -+ (pciData & PSISVIR_DEVID_MASK) >> PSISVIR_DEVID_OFFS; -+ -+ -+ /* Read PCI_EXPANSION_ROM_BASE_ADDR_REG */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_EXPANSION_ROM_BASE_ADDR_REG); -+ -+ -+ if (pciData & PERBAR_EXPROMEN) -+ { -+ pPciAgent->isExpRom = MV_TRUE; -+ } -+ else -+ { -+ pPciAgent->isExpRom = MV_FALSE; -+ } -+ -+ pPciAgent->expRomAddr = -+ (pciData & PERBAR_BASE_MASK) >> PERBAR_BASE_OFFS; -+ -+ } -+ -+ -+ if (MV_TRUE == pPciAgent->isCapListSupport) -+ { -+ /* Read PCI_CAPABILTY_LIST_POINTER */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_CAPABILTY_LIST_POINTER); -+ -+ pPciAgent->capListPointer = -+ (pciData & PCLPR_CAPPTR_MASK) >> PCLPR_CAPPTR_OFFS; -+ -+ } -+ -+ /* Read PCI_INTERRUPT_PIN_AND_LINE */ -+ pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_INTERRUPT_PIN_AND_LINE); -+ -+ -+ pPciAgent->irqLine= -+ (pciData & PIPLR_INTLINE_MASK) >> PIPLR_INTLINE_OFFS; -+ -+ pPciAgent->intPin= -+ (MV_PCI_INT_PIN)(pciData & PIPLR_INTPIN_MASK) >> PIPLR_INTPIN_OFFS; -+ -+ pPciAgent->minGrant= -+ (pciData & PIPLR_MINGRANT_MASK) >> PIPLR_MINGRANT_OFFS; -+ pPciAgent->maxLatency= -+ (pciData & PIPLR_MAXLATEN_MASK) >> PIPLR_MAXLATEN_OFFS; -+ -+ mvPciClassNameGet(pPciAgent->baseClassCode, -+ (MV_8 *)pPciAgent->type); -+ -+ return MV_OK; -+ -+ -+} -+ -+/******************************************************************************* -+* pciDetectDeviceBars - Detect a pci device bars -+* -+* DESCRIPTION: -+* This function detects all pci agent bars -+* -+* INPUT: -+* pciIf - PCI Interface -+* bus - Bus number -+* dev - Device number -+* func - Function number -+* -+* -+* -+* OUTPUT: -+* pPciAgent - pointer to the pci agent filled with its information -+* -+* RETURN: -+* detected bars number -+* -+*******************************************************************************/ -+static MV_U32 pciDetectDeviceBars(MV_U32 pciIf, -+ MV_U32 bus, -+ MV_U32 dev, -+ MV_U32 func, -+ MV_PCI_DEVICE *pPciAgent) -+{ -+ MV_U32 pciData,barIndex,detectedBar=0; -+ MV_U32 tmpBaseHigh=0,tmpBaseLow=0; -+ MV_U32 pciMaxBars=0; -+ -+ pPciAgent->barsNum=0; -+ -+ /* check if we are bridge*/ -+ if ((pPciAgent->baseClassCode == PCI_BRIDGE_CLASS)&& -+ (pPciAgent->subClassCode == P2P_BRIDGE_SUB_CLASS_CODE)) -+ { -+ pciMaxBars = 2; -+ } -+ else /* no bridge */ -+ { -+ pciMaxBars = 6; -+ } -+ -+ /* read this device pci bars */ -+ for (barIndex = 0 ; barIndex < pciMaxBars ; barIndex++ ) -+ { -+ /* Read PCI_MEMORY_BAR_BASE_ADDR */ -+ tmpBaseLow = pciData = mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex)); -+ -+ pPciAgent->pciBar[detectedBar].barOffset = -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex); -+ -+ /* check if the bar is 32bit or 64bit bar */ -+ switch (pciData & PBBLR_TYPE_MASK) -+ { -+ case PBBLR_TYPE_32BIT_ADDR: -+ pPciAgent->pciBar[detectedBar].barType = PCI_32BIT_BAR; -+ break; -+ case PBBLR_TYPE_64BIT_ADDR: -+ pPciAgent->pciBar[detectedBar].barType = PCI_64BIT_BAR; -+ break; -+ -+ } -+ -+ /* check if it is memory or IO bar */ -+ if (pciData & PBBLR_IOSPACE) -+ { -+ pPciAgent->pciBar[detectedBar].barMapping=PCI_IO_BAR; -+ } -+ else -+ { -+ pPciAgent->pciBar[detectedBar].barMapping=PCI_MEMORY_BAR; -+ } -+ -+ /* if it is memory bar then check if it is prefetchable */ -+ if (PCI_MEMORY_BAR == pPciAgent->pciBar[detectedBar].barMapping) -+ { -+ if (pciData & PBBLR_PREFETCH_EN) -+ { -+ pPciAgent->pciBar[detectedBar].isPrefetchable = MV_TRUE; -+ } -+ else -+ { -+ pPciAgent->pciBar[detectedBar].isPrefetchable = MV_FALSE; -+ } -+ -+ pPciAgent->pciBar[detectedBar].barBaseLow = -+ pciData & PBBLR_MEM_BASE_MASK; -+ -+ -+ } -+ else /* IO Bar */ -+ { -+ pPciAgent->pciBar[detectedBar].barBaseLow = -+ pciData & PBBLR_IO_BASE_MASK; -+ -+ } -+ -+ pPciAgent->pciBar[detectedBar].barBaseHigh=0; -+ -+ if (PCI_64BIT_BAR == pPciAgent->pciBar[detectedBar].barType) -+ { -+ barIndex++; -+ -+ tmpBaseHigh = pPciAgent->pciBar[detectedBar].barBaseHigh = -+ mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex)); -+ -+ -+ } -+ -+ /* calculating full base address (64bit) */ -+ pPciAgent->pciBar[detectedBar].barBaseAddr = -+ (MV_U64)pPciAgent->pciBar[detectedBar].barBaseHigh; -+ -+ pPciAgent->pciBar[detectedBar].barBaseAddr <<= 32; -+ -+ pPciAgent->pciBar[detectedBar].barBaseAddr |= -+ (MV_U64)pPciAgent->pciBar[detectedBar].barBaseLow; -+ -+ -+ -+ /* get the sizes of the the bar */ -+ -+ pPciAgent->pciBar[detectedBar].barSizeHigh=0; -+ -+ if ((PCI_64BIT_BAR == pPciAgent->pciBar[detectedBar].barType) && -+ (PCI_MEMORY_BAR == pPciAgent->pciBar[detectedBar].barMapping)) -+ -+ { -+ /* write oxffffffff to the bar to get the size */ -+ /* start with sizelow ( original value was saved in tmpBaseLow ) */ -+ mvPciIfConfigWrite(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex-1), -+ 0xffffffff); -+ -+ /* read size */ -+ pPciAgent->pciBar[detectedBar].barSizeLow = -+ mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex-1)); -+ -+ -+ -+ /* restore original value */ -+ mvPciIfConfigWrite(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex-1), -+ tmpBaseLow); -+ -+ -+ /* now do the same for BaseHigh */ -+ -+ /* write oxffffffff to the bar to get the size */ -+ mvPciIfConfigWrite(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex), -+ 0xffffffff); -+ -+ /* read size */ -+ pPciAgent->pciBar[detectedBar].barSizeHigh = -+ mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex)); -+ -+ /* restore original value */ -+ mvPciIfConfigWrite(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex), -+ tmpBaseHigh); -+ -+ if ((0 == pPciAgent->pciBar[detectedBar].barSizeLow)&& -+ (0 == pPciAgent->pciBar[detectedBar].barSizeHigh)) -+ { -+ /* this bar is not applicable for this device, -+ ignore all previous settings and check the next bar*/ -+ -+ /* we though this was a 64bit bar , and it seems this -+ was wrong ! so decrement barIndex */ -+ barIndex--; -+ continue; -+ } -+ -+ /* calculate the full 64 bit size */ -+ -+ if (0 != pPciAgent->pciBar[detectedBar].barSizeHigh) -+ { -+ pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_MEM_BASE_MASK; -+ -+ pPciAgent->pciBar[detectedBar].barSizeLow = -+ ~pPciAgent->pciBar[detectedBar].barSizeLow + 1; -+ -+ pPciAgent->pciBar[detectedBar].barSizeHigh = 0; -+ -+ } -+ else -+ { -+ -+ pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_MEM_BASE_MASK; -+ -+ pPciAgent->pciBar[detectedBar].barSizeLow = -+ ~pPciAgent->pciBar[detectedBar].barSizeLow + 1; -+ -+ pPciAgent->pciBar[detectedBar].barSizeHigh = 0; -+ -+ } -+ -+ -+ -+ } -+ else /* 32bit bar */ -+ { -+ /* write oxffffffff to the bar to get the size */ -+ mvPciIfConfigWrite(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex), -+ 0xffffffff); -+ -+ /* read size */ -+ pPciAgent->pciBar[detectedBar].barSizeLow = -+ mvPciIfConfigRead(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex)); -+ -+ if (0 == pPciAgent->pciBar[detectedBar].barSizeLow) -+ { -+ /* this bar is not applicable for this device, -+ ignore all previous settings and check the next bar*/ -+ continue; -+ } -+ -+ -+ /* restore original value */ -+ mvPciIfConfigWrite(pciIf, -+ bus,dev,func, -+ PCI_MEMORY_BAR_BASE_ADDR(barIndex), -+ tmpBaseLow); -+ -+ /* calculate size low */ -+ -+ if (PCI_MEMORY_BAR == pPciAgent->pciBar[detectedBar].barMapping) -+ { -+ pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_MEM_BASE_MASK; -+ } -+ else -+ { -+ pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_IO_BASE_MASK; -+ } -+ -+ pPciAgent->pciBar[detectedBar].barSizeLow = -+ ~pPciAgent->pciBar[detectedBar].barSizeLow + 1; -+ -+ pPciAgent->pciBar[detectedBar].barSizeHigh = 0; -+ pPciAgent->pciBar[detectedBar].barSize = -+ (MV_U64)pPciAgent->pciBar[detectedBar].barSizeLow; -+ -+ -+ } -+ -+ /* we are here ! this means we have already detected a bar for -+ this device , now move on */ -+ -+ detectedBar++; -+ pPciAgent->barsNum++; -+ } -+ -+ return detectedBar; -+} -+ -+ -+/******************************************************************************* -+* mvPciClassNameGet - get PCI class name -+* -+* DESCRIPTION: -+* This function returns the PCI class name -+* -+* INPUT: -+* baseClassCode - Base Class Code. -+* -+* OUTPUT: -+* pType - the class name -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPciClassNameGet(MV_U32 baseClassCode, MV_8 *pType) -+{ -+ -+ switch(baseClassCode) -+ { -+ case 0x0: -+ strcpy(pType,"Old generation device"); -+ break; -+ case 0x1: -+ strcpy(pType,"Mass storage controller"); -+ break; -+ case 0x2: -+ strcpy(pType,"Network controller"); -+ break; -+ case 0x3: -+ strcpy(pType,"Display controller"); -+ break; -+ case 0x4: -+ strcpy(pType,"Multimedia device"); -+ break; -+ case 0x5: -+ strcpy(pType,"Memory controller"); -+ break; -+ case 0x6: -+ strcpy(pType,"Bridge Device"); -+ break; -+ case 0x7: -+ strcpy(pType,"Simple Communication controllers"); -+ break; -+ case 0x8: -+ strcpy(pType,"Base system peripherals"); -+ break; -+ case 0x9: -+ strcpy(pType,"Input Devices"); -+ break; -+ case 0xa: -+ strcpy(pType,"Docking stations"); -+ break; -+ case 0xb: -+ strcpy(pType,"Processors"); -+ break; -+ case 0xc: -+ strcpy(pType,"Serial bus controllers"); -+ break; -+ case 0xd: -+ strcpy(pType,"Wireless controllers"); -+ break; -+ case 0xe: -+ strcpy(pType,"Intelligent I/O controllers"); -+ break; -+ case 0xf: -+ strcpy(pType,"Satellite communication controllers"); -+ break; -+ case 0x10: -+ strcpy(pType,"Encryption/Decryption controllers"); -+ break; -+ case 0x11: -+ strcpy(pType,"Data acquisition and signal processing controllers"); -+ break; -+ default: -+ strcpy(pType,"Unknown device"); -+ break; -+ } -+ -+ return MV_OK; -+ -+} -+ -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,323 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvPciUtilsh -+#define __INCmvPciUtilsh -+ -+/* -+This module only support scanning of Header type 00h of pci devices -+There is no suppotr for Header type 01h of pci devices ( PCI bridges ) -+*/ -+ -+/* includes */ -+#include "mvSysHwConfig.h" -+#include "pci-if/mvPciIf.h" -+#include "pci/mvPciRegs.h" -+ -+ -+ -+/* PCI base address low bar mask */ -+#define PCI_ERROR_CODE 0xffffffff -+ -+#define PCI_BRIDGE_CLASS 0x6 -+#define P2P_BRIDGE_SUB_CLASS_CODE 0x4 -+ -+ -+#define P2P_BUSSES_NUM 0x18 -+#define P2P_IO_BASE_LIMIT_SEC_STATUS 0x1C -+#define P2P_MEM_BASE_LIMIT 0x20 -+#define P2P_PREF_MEM_BASE_LIMIT 0x24 -+#define P2P_PREF_BASE_UPPER_32 0x28 -+#define P2P_PREF_LIMIT_UPPER_32 0x2C -+#define P2P_IO_BASE_LIMIT_UPPER_16 0x30 -+#define P2P_EXP_ROM 0x38 -+ -+/* P2P_BUSSES_NUM (PBM) */ -+ -+#define PBM_PRIME_BUS_NUM_OFFS 0 -+#define PBM_PRIME_BUS_NUM_MASK (0xff << PBM_PRIME_BUS_NUM_OFFS) -+ -+#define PBM_SEC_BUS_NUM_OFFS 8 -+#define PBM_SEC_BUS_NUM_MASK (0xff << PBM_SEC_BUS_NUM_OFFS) -+ -+#define PBM_SUB_BUS_NUM_OFFS 16 -+#define PBM_SUB_BUS_NUM_MASK (0xff << PBM_SUB_BUS_NUM_OFFS) -+ -+#define PBM_SEC_LAT_TMR_OFFS 24 -+#define PBM_SEC_LAT_TMR_MASK (0xff << PBM_SEC_LAT_TMR_OFFS) -+ -+/* P2P_IO_BASE_LIMIT_SEC_STATUS (PIBLSS) */ -+ -+#define PIBLSS_IO_BASE_OFFS 0 -+#define PIBLSS_IO_BASE_MASK (0xff << PIBLSS_IO_BASE_OFFS) -+ -+#define PIBLSS_ADD_CAP_OFFS 0 -+#define PIBLSS_ADD_CAP_MASK (0x3 << PIBLSS_ADD_CAP_OFFS) -+#define PIBLSS_ADD_CAP_16BIT (0x0 << PIBLSS_ADD_CAP_OFFS) -+#define PIBLSS_ADD_CAP_32BIT (0x1 << PIBLSS_ADD_CAP_OFFS) -+ -+#define PIBLSS_LOW_ADDR_OFFS 0 -+#define PIBLSS_LOW_ADDR_MASK (0xFFF << PIBLSS_LOW_ADDR_OFFS) -+ -+#define PIBLSS_HIGH_ADDR_OFFS 12 -+#define PIBLSS_HIGH_ADDR_MASK (0xF << PIBLSS_HIGH_ADDR_OFFS) -+ -+#define PIBLSS_IO_LIMIT_OFFS 8 -+#define PIBLSS_IO_LIMIT_MASK (0xff << PIBLSS_IO_LIMIT_OFFS) -+ -+#define PIBLSS_SEC_STATUS_OFFS 16 -+#define PIBLSS_SEC_STATUS_MASK (0xffff << PIBLSS_SEC_STATUS_OFFS) -+ -+ -+/* P2P_MEM_BASE_LIMIT (PMBL)*/ -+ -+#define PMBL_MEM_BASE_OFFS 0 -+#define PMBL_MEM_BASE_MASK (0xffff << PMBL_MEM_BASE_OFFS) -+ -+#define PMBL_MEM_LIMIT_OFFS 16 -+#define PMBL_MEM_LIMIT_MASK (0xffff << PMBL_MEM_LIMIT_OFFS) -+ -+ -+#define PMBL_LOW_ADDR_OFFS 0 -+#define PMBL_LOW_ADDR_MASK (0xFFFFF << PMBL_LOW_ADDR_OFFS) -+ -+#define PMBL_HIGH_ADDR_OFFS 20 -+#define PMBL_HIGH_ADDR_MASK (0xFFF << PMBL_HIGH_ADDR_OFFS) -+ -+ -+/* P2P_PREF_MEM_BASE_LIMIT (PRMBL) */ -+ -+#define PRMBL_PREF_MEM_BASE_OFFS 0 -+#define PRMBL_PREF_MEM_BASE_MASK (0xffff << PRMBL_PREF_MEM_BASE_OFFS) -+ -+#define PRMBL_PREF_MEM_LIMIT_OFFS 16 -+#define PRMBL_PREF_MEM_LIMIT_MASK (0xffff<= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexModeGet: ERR. Invalid PEX interface %d\n",pexIf); -+ return MV_ERROR; -+ } -+ } -+ -+ pexData = MV_REG_READ(PEX_CTRL_REG(pexIf)); -+ -+ switch (pexData & PXCR_DEV_TYPE_CTRL_MASK) -+ { -+ case PXCR_DEV_TYPE_CTRL_CMPLX: -+ pexMode->pexType = MV_PEX_ROOT_COMPLEX; -+ break; -+ case PXCR_DEV_TYPE_CTRL_POINT: -+ pexMode->pexType = MV_PEX_END_POINT; -+ break; -+ -+ } -+ -+ /* Check if we have link */ -+ if (MV_REG_READ(PEX_STATUS_REG(pexIf)) & PXSR_DL_DOWN) -+ { -+ pexMode->pexLinkUp = MV_FALSE; -+ -+ /* If there is no link, the auto negotiation data is worthless */ -+ pexMode->pexWidth = MV_PEX_WITDH_INVALID; -+ } -+ else -+ { -+ pexMode->pexLinkUp = MV_TRUE; -+ -+ /* We have link. The link width is now valid */ -+ pexData = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG)); -+ pexMode->pexWidth = ((pexData & PXLCSR_NEG_LNK_WDTH_MASK) >> -+ PXLCSR_NEG_LNK_WDTH_OFFS); -+ } -+ -+ return MV_OK; -+} -+ -+ -+/* PEX configuration space read write */ -+ -+/******************************************************************************* -+* mvPexConfigRead - Read from configuration space -+* -+* DESCRIPTION: -+* This function performs a 32 bit read from PEX configuration space. -+* It supports both type 0 and type 1 of Configuration Transactions -+* (local and over bridge). In order to read from local bus segment, use -+* bus number retrieved from mvPexLocalBusNumGet(). Other bus numbers -+* will result configuration transaction of type 1 (over bridge). -+* -+* INPUT: -+* pexIf - PEX interface number. -+* bus - PEX segment bus number. -+* dev - PEX device number. -+* func - Function number. -+* regOffs - Register offset. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* 32bit register data, 0xffffffff on error -+* -+*******************************************************************************/ -+MV_U32 mvPexConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, -+ MV_U32 regOff) -+{ -+#if defined(PCIE_VIRTUAL_BRIDGE_SUPPORT) -+ return mvPexVrtBrgConfigRead (pexIf, bus, dev, func, regOff); -+} -+ -+MV_U32 mvPexHwConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, -+ MV_U32 regOff) -+{ -+#endif -+ MV_U32 pexData = 0; -+ MV_U32 localDev,localBus; -+ -+ /* Parameter checking */ -+ if (PEX_DEFAULT_IF != pexIf) -+ { -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexConfigRead: ERR. Invalid PEX interface %d\n",pexIf); -+ return 0xFFFFFFFF; -+ } -+ } -+ -+ if (dev >= MAX_PEX_DEVICES) -+ { -+ DB(mvOsPrintf("mvPexConfigRead: ERR. device number illigal %d\n", dev)); -+ return 0xFFFFFFFF; -+ } -+ -+ if (func >= MAX_PEX_FUNCS) -+ { -+ DB(mvOsPrintf("mvPexConfigRead: ERR. function num illigal %d\n", func)); -+ return 0xFFFFFFFF; -+ } -+ -+ if (bus >= MAX_PEX_BUSSES) -+ { -+ DB(mvOsPrintf("mvPexConfigRead: ERR. bus number illigal %d\n", bus)); -+ return MV_ERROR; -+ } -+ -+ DB(mvOsPrintf("mvPexConfigRead: pexIf %d, bus %d, dev %d, func %d, regOff 0x%x\n", -+ pexIf, bus, dev, func, regOff)); -+ -+ localDev = mvPexLocalDevNumGet(pexIf); -+ localBus = mvPexLocalBusNumGet(pexIf); -+ -+ /* Speed up the process. In case on no link, return MV_ERROR */ -+ if ((dev != localDev) || (bus != localBus)) -+ { -+ pexData = MV_REG_READ(PEX_STATUS_REG(pexIf)); -+ -+ if ((pexData & PXSR_DL_DOWN)) -+ { -+ return MV_ERROR; -+ } -+ } -+ -+ /* in PCI Express we have only one device number */ -+ /* and this number is the first number we encounter -+ else that the localDev*/ -+ /* spec pex define return on config read/write on any device */ -+ if (bus == localBus) -+ { -+ if (localDev == 0) -+ { -+ /* if local dev is 0 then the first number we encounter -+ after 0 is 1 */ -+ if ((dev != 1)&&(dev != localDev)) -+ { -+ return MV_ERROR; -+ } -+ } -+ else -+ { -+ /* if local dev is not 0 then the first number we encounter -+ is 0 */ -+ -+ if ((dev != 0)&&(dev != localDev)) -+ { -+ return MV_ERROR; -+ } -+ } -+ if(func != 0 ) /* i.e bridge */ -+ { -+ return MV_ERROR; -+ } -+ } -+ -+ -+ /* Creating PEX address to be passed */ -+ pexData = (bus << PXCAR_BUS_NUM_OFFS); -+ pexData |= (dev << PXCAR_DEVICE_NUM_OFFS); -+ pexData |= (func << PXCAR_FUNC_NUM_OFFS); -+ pexData |= (regOff & PXCAR_REG_NUM_MASK); /* lgacy register space */ -+ /* extended register space */ -+ pexData |=(((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >> -+ PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS); -+ -+ pexData |= PXCAR_CONFIG_EN; -+ -+ /* Write the address to the PEX configuration address register */ -+ MV_REG_WRITE(PEX_CFG_ADDR_REG(pexIf), pexData); -+ -+ DB(mvOsPrintf("mvPexConfigRead:address pexData=%x ",pexData)); -+ -+ -+ /* In order to let the PEX controller absorbed the address of the read */ -+ /* transaction we perform a validity check that the address was written */ -+ if(pexData != MV_REG_READ(PEX_CFG_ADDR_REG(pexIf))) -+ { -+ return MV_ERROR; -+ } -+ -+ /* cleaning Master Abort */ -+ MV_REG_BIT_SET(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_STATUS_AND_COMMAND), -+ PXSAC_MABORT); -+#if 0 -+ /* Guideline (GL# PCI Express-1) Erroneous Read Data on Configuration */ -+ /* This guideline is relevant for all devices except of the following devices: -+ 88F5281-BO and above, 88F5181L-A0 and above, 88F1281 A0 and above -+ 88F6183 A0 and above, 88F6183L */ -+ if ( ( (dev != localDev) || (bus != localBus) ) && -+ ( -+ !(MV_5281_DEV_ID == mvCtrlModelGet())&& -+ !((MV_5181_DEV_ID == mvCtrlModelGet())&& (mvCtrlRevGet() >= MV_5181L_A0_REV))&& -+ !(MV_1281_DEV_ID == mvCtrlModelGet())&& -+ !(MV_6183_DEV_ID == mvCtrlModelGet())&& -+ !(MV_6183L_DEV_ID == mvCtrlModelGet())&& -+ !(MV_6281_DEV_ID == mvCtrlModelGet())&& -+ !(MV_6192_DEV_ID == mvCtrlModelGet())&& -+ !(MV_6190_DEV_ID == mvCtrlModelGet())&& -+ !(MV_6180_DEV_ID == mvCtrlModelGet())&& -+ !(MV_78XX0_DEV_ID == mvCtrlModelGet()) -+ )) -+ { -+ -+ /* PCI-Express configuration read work-around */ -+ -+ /* we will use one of the Punit (AHBToMbus) windows to access the xbar -+ and read the data from there */ -+ /* -+ Need to configure the 2 free Punit (AHB to MBus bridge) -+ address decoding windows: -+ Configure the flash Window to handle Configuration space requests -+ for PEX0/1: -+ 1. write 0x7931/0x7941 to the flash window and the size, -+ 79-xbar attr (pci cfg), 3/4-xbar target (pex0/1), 1-WinEn -+ 2. write base to flash window -+ -+ Configuration transactions from the CPU should write/read the data -+ to/from address of the form: -+ addr[31:28] = 0x5 (for PEX0) or 0x6 (for PEX1) -+ addr[27:24] = extended register number -+ addr[23:16] = bus number -+ addr[15:11] = device number -+ addr[10:8] = function number -+ addr[7:0] = register number -+ */ -+ -+ #include "ctrlEnv/sys/mvAhbToMbus.h" -+ { -+ MV_U32 winNum; -+ MV_AHB_TO_MBUS_DEC_WIN originWin; -+ MV_U32 pciAddr=0; -+ MV_U32 remapLow=0,remapHigh=0; -+ -+ /* -+ We will use DEV_CS2\Flash window for this workarround -+ */ -+ -+ winNum = mvAhbToMbusWinTargetGet(PEX_CONFIG_RW_WA_TARGET); -+ -+ /* save remap values if exist */ -+ if ((1 == winNum)||(0 == winNum)) -+ { -+ remapLow = MV_REG_READ(AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum)); -+ remapHigh = MV_REG_READ(AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum)); -+ -+ } -+ -+ -+ /* save the original window values */ -+ mvAhbToMbusWinGet(winNum,&originWin); -+ -+ if (PEX_CONFIG_RW_WA_USE_ORIGINAL_WIN_VALUES) -+ { -+ /* set the window as xbar window */ -+ if (pexIf) -+ { -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), -+ (0x7931 | (((originWin.addrWin.size >> 16)-1) ) << 16)); -+ } -+ else -+ { -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), -+ (0x7941 | (((originWin.addrWin.size >> 16)-1) ) << 16)); -+ } -+ -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum), -+ originWin.addrWin.baseLow); -+ -+ /*pciAddr = originWin.addrWin.baseLow;*/ -+ pciAddr = (MV_U32)CPU_MEMIO_UNCACHED_ADDR( -+ (MV_U32)originWin.addrWin.baseLow); -+ -+ } -+ else -+ { -+ /* set the window as xbar window */ -+ if (pexIf) -+ { -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), -+ (0x7931 | (((PEX_CONFIG_RW_WA_SIZE >> 16)-1) ) << 16)); -+ } -+ else -+ { -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), -+ (0x7941 | (((PEX_CONFIG_RW_WA_SIZE >> 16)-1) ) << 16)); -+ } -+ -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum), -+ PEX_CONFIG_RW_WA_BASE); -+ -+ pciAddr = (MV_U32)CPU_MEMIO_UNCACHED_ADDR(PEX_CONFIG_RW_WA_BASE); -+ } -+ -+ -+ /* remap should be as base */ -+ if ((1 == winNum)||(0 == winNum)) -+ { -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum),pciAddr); -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum),0); -+ -+ } -+ -+ /* extended register space */ -+ pciAddr |= (bus << 16); -+ pciAddr |= (dev << 11); -+ pciAddr |= (func << 8); -+ pciAddr |= (regOff & PXCAR_REG_NUM_MASK); /* lgacy register space */ -+ -+ pexData = *(MV_U32*)pciAddr; -+ pexData = MV_32BIT_LE(pexData); /* Data always in LE */ -+ -+ /* restore the original window values */ -+ mvAhbToMbusWinSet(winNum,&originWin); -+ -+ /* restore original remap values*/ -+ if ((1 == winNum)||(0 == winNum)) -+ { -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum),remapLow); -+ MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum),remapHigh); -+ -+ } -+ } -+ } -+ else -+#endif -+ { -+ /* Read the Data returned in the PEX Data register */ -+ pexData = MV_REG_READ(PEX_CFG_DATA_REG(pexIf)); -+ -+ } -+ -+ DB(mvOsPrintf("mvPexConfigRead: got : %x \n",pexData)); -+ -+ return pexData; -+ -+} -+ -+/******************************************************************************* -+* mvPexConfigWrite - Write to configuration space -+* -+* DESCRIPTION: -+* This function performs a 32 bit write to PEX configuration space. -+* It supports both type 0 and type 1 of Configuration Transactions -+* (local and over bridge). In order to write to local bus segment, use -+* bus number retrieved from mvPexLocalBusNumGet(). Other bus numbers -+* will result configuration transaction of type 1 (over bridge). -+* -+* INPUT: -+* pexIf - PEX interface number. -+* bus - PEX segment bus number. -+* dev - PEX device number. -+* func - Function number. -+* regOffs - Register offset. -+* data - 32bit data. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data) -+{ -+#if defined(PCIE_VIRTUAL_BRIDGE_SUPPORT) -+ return mvPexVrtBrgConfigWrite (pexIf, bus, dev, func, regOff, data); -+} -+ -+MV_STATUS mvPexHwConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data) -+{ -+#endif -+ MV_U32 pexData = 0; -+ MV_U32 localDev,localBus; -+ -+ /* Parameter checking */ -+ if (PEX_DEFAULT_IF != pexIf) -+ { -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexConfigWrite: ERR. Invalid PEX interface %d\n", -+ pexIf); -+ return MV_ERROR; -+ } -+ } -+ -+ if (dev >= MAX_PEX_DEVICES) -+ { -+ mvOsPrintf("mvPexConfigWrite: ERR. device number illigal %d\n",dev); -+ return MV_BAD_PARAM; -+ } -+ -+ if (func >= MAX_PEX_FUNCS) -+ { -+ mvOsPrintf("mvPexConfigWrite: ERR. function number illigal %d\n", func); -+ return MV_ERROR; -+ } -+ -+ if (bus >= MAX_PEX_BUSSES) -+ { -+ mvOsPrintf("mvPexConfigWrite: ERR. bus number illigal %d\n", bus); -+ return MV_ERROR; -+ } -+ -+ -+ -+ localDev = mvPexLocalDevNumGet(pexIf); -+ localBus = mvPexLocalBusNumGet(pexIf); -+ -+ -+ /* in PCI Express we have only one device number other than ourselves*/ -+ /* and this number is the first number we encounter -+ else than the localDev that can be any valid dev number*/ -+ /* pex spec define return on config read/write on any device */ -+ if (bus == localBus) -+ { -+ -+ if (localDev == 0) -+ { -+ /* if local dev is 0 then the first number we encounter -+ after 0 is 1 */ -+ if ((dev != 1)&&(dev != localDev)) -+ { -+ return MV_ERROR; -+ } -+ -+ } -+ else -+ { -+ /* if local dev is not 0 then the first number we encounter -+ is 0 */ -+ -+ if ((dev != 0)&&(dev != localDev)) -+ { -+ return MV_ERROR; -+ } -+ } -+ -+ -+ } -+ -+ /* if we are not accessing ourselves , then check the link */ -+ if ((dev != localDev) || (bus != localBus) ) -+ { -+ /* workarround */ -+ /* when no link return MV_ERROR */ -+ -+ pexData = MV_REG_READ(PEX_STATUS_REG(pexIf)); -+ -+ if ((pexData & PXSR_DL_DOWN)) -+ { -+ return MV_ERROR; -+ } -+ -+ } -+ -+ pexData =0; -+ -+ /* Creating PEX address to be passed */ -+ pexData |= (bus << PXCAR_BUS_NUM_OFFS); -+ pexData |= (dev << PXCAR_DEVICE_NUM_OFFS); -+ pexData |= (func << PXCAR_FUNC_NUM_OFFS); -+ pexData |= (regOff & PXCAR_REG_NUM_MASK); /* lgacy register space */ -+ /* extended register space */ -+ pexData |=(((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >> -+ PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS); -+ pexData |= PXCAR_CONFIG_EN; -+ -+ DB(mvOsPrintf("mvPexConfigWrite: If=%x bus=%x func=%x dev=%x regOff=%x data=%x \n", -+ pexIf,bus,func,dev,regOff,data,pexData) ); -+ -+ /* Write the address to the PEX configuration address register */ -+ MV_REG_WRITE(PEX_CFG_ADDR_REG(pexIf), pexData); -+ -+ /* Clear CPU pipe. Important where CPU can perform OOO execution */ -+ CPU_PIPE_FLUSH; -+ -+ /* In order to let the PEX controller absorbed the address of the read */ -+ /* transaction we perform a validity check that the address was written */ -+ if(pexData != MV_REG_READ(PEX_CFG_ADDR_REG(pexIf))) -+ { -+ return MV_ERROR; -+ } -+ -+ /* Write the Data passed to the PEX Data register */ -+ MV_REG_WRITE(PEX_CFG_DATA_REG(pexIf), data); -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvPexMasterEnable - Enable/disale PEX interface master transactions. -+* -+* DESCRIPTION: -+* This function performs read modified write to PEX command status -+* (offset 0x4) to set/reset bit 2. After this bit is set, the PEX -+* master is allowed to gain ownership on the bus, otherwise it is -+* incapable to do so. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexMasterEnable(MV_U32 pexIf, MV_BOOL enable) -+{ -+ MV_U32 pexCommandStatus; -+ MV_U32 localBus; -+ MV_U32 localDev; -+ -+ /* Parameter checking */ -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexMasterEnable: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_ERROR; -+ } -+ -+ localBus = mvPexLocalBusNumGet(pexIf); -+ localDev = mvPexLocalDevNumGet(pexIf); -+ -+ pexCommandStatus = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, -+ PEX_STATUS_AND_COMMAND)); -+ -+ -+ if (MV_TRUE == enable) -+ { -+ pexCommandStatus |= PXSAC_MASTER_EN; -+ } -+ else -+ { -+ pexCommandStatus &= ~PXSAC_MASTER_EN; -+ } -+ -+ -+ MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_STATUS_AND_COMMAND), -+ pexCommandStatus); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPexSlaveEnable - Enable/disale PEX interface slave transactions. -+* -+* DESCRIPTION: -+* This function performs read modified write to PEX command status -+* (offset 0x4) to set/reset bit 0 and 1. After those bits are set, -+* the PEX slave is allowed to respond to PEX IO space access (bit 0) -+* and PEX memory space access (bit 1). -+* -+* INPUT: -+* pexIf - PEX interface number. -+* dev - PEX device number. -+* enable - Enable/disable parameter. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexSlaveEnable(MV_U32 pexIf, MV_U32 bus,MV_U32 dev, MV_BOOL enable) -+{ -+ MV_U32 pexCommandStatus; -+ MV_U32 RegOffs; -+ -+ /* Parameter checking */ -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexSlaveEnable: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ if (dev >= MAX_PEX_DEVICES) -+ { -+ mvOsPrintf("mvPexLocalDevNumSet: ERR. device number illigal %d\n", dev); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ -+ RegOffs = PEX_STATUS_AND_COMMAND; -+ -+ pexCommandStatus = mvPexConfigRead(pexIf, bus, dev, 0, RegOffs); -+ -+ if (MV_TRUE == enable) -+ { -+ pexCommandStatus |= (PXSAC_IO_EN | PXSAC_MEM_EN); -+ } -+ else -+ { -+ pexCommandStatus &= ~(PXSAC_IO_EN | PXSAC_MEM_EN); -+ } -+ -+ mvPexConfigWrite(pexIf, bus, dev, 0, RegOffs, pexCommandStatus); -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvPexLocalBusNumSet - Set PEX interface local bus number. -+* -+* DESCRIPTION: -+* This function sets given PEX interface its local bus number. -+* Note: In case the PEX interface is PEX-X, the information is read-only. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* busNum - Bus number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_NOT_ALLOWED in case PEX interface is PEX-X. -+* MV_BAD_PARAM on bad parameters , -+* otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexLocalBusNumSet(MV_U32 pexIf, MV_U32 busNum) -+{ -+ MV_U32 pexStatus; -+ MV_U32 localBus; -+ MV_U32 localDev; -+ -+ -+ /* Parameter checking */ -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexLocalBusNumSet: ERR. Invalid PEX interface %d\n",pexIf); -+ return MV_BAD_PARAM; -+ } -+ if (busNum >= MAX_PEX_BUSSES) -+ { -+ mvOsPrintf("mvPexLocalBusNumSet: ERR. bus number illigal %d\n", busNum); -+ return MV_ERROR; -+ -+ } -+ -+ localBus = mvPexLocalBusNumGet(pexIf); -+ localDev = mvPexLocalDevNumGet(pexIf); -+ -+ -+ -+ pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); -+ -+ pexStatus &= ~PXSR_PEX_BUS_NUM_MASK; -+ -+ pexStatus |= (busNum << PXSR_PEX_BUS_NUM_OFFS) & PXSR_PEX_BUS_NUM_MASK; -+ -+ MV_REG_WRITE(PEX_STATUS_REG(pexIf), pexStatus); -+ -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPexLocalBusNumGet - Get PEX interface local bus number. -+* -+* DESCRIPTION: -+* This function gets the local bus number of a given PEX interface. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Local bus number.0xffffffff on Error -+* -+*******************************************************************************/ -+MV_U32 mvPexLocalBusNumGet(MV_U32 pexIf) -+{ -+ MV_U32 pexStatus; -+ -+ /* Parameter checking */ -+ if (PEX_DEFAULT_IF != pexIf) -+ { -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexLocalBusNumGet: ERR. Invalid PEX interface %d\n",pexIf); -+ return 0xFFFFFFFF; -+ } -+ } -+ -+ -+ pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); -+ -+ pexStatus &= PXSR_PEX_BUS_NUM_MASK; -+ -+ return (pexStatus >> PXSR_PEX_BUS_NUM_OFFS); -+ -+} -+ -+ -+/******************************************************************************* -+* mvPexLocalDevNumSet - Set PEX interface local device number. -+* -+* DESCRIPTION: -+* This function sets given PEX interface its local device number. -+* Note: In case the PEX interface is PEX-X, the information is read-only. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* devNum - Device number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_NOT_ALLOWED in case PEX interface is PEX-X. -+* MV_BAD_PARAM on bad parameters , -+* otherwise MV_OK -+* -+*******************************************************************************/ -+MV_STATUS mvPexLocalDevNumSet(MV_U32 pexIf, MV_U32 devNum) -+{ -+ MV_U32 pexStatus; -+ MV_U32 localBus; -+ MV_U32 localDev; -+ -+ /* Parameter checking */ -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexLocalDevNumSet: ERR. Invalid PEX interface %d\n",pexIf); -+ return MV_BAD_PARAM; -+ } -+ if (devNum >= MAX_PEX_DEVICES) -+ { -+ mvOsPrintf("mvPexLocalDevNumSet: ERR. device number illigal %d\n", -+ devNum); -+ return MV_BAD_PARAM; -+ -+ } -+ -+ localBus = mvPexLocalBusNumGet(pexIf); -+ localDev = mvPexLocalDevNumGet(pexIf); -+ -+ -+ pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); -+ -+ pexStatus &= ~PXSR_PEX_DEV_NUM_MASK; -+ -+ pexStatus |= (devNum << PXSR_PEX_DEV_NUM_OFFS) & PXSR_PEX_DEV_NUM_MASK; -+ -+ MV_REG_WRITE(PEX_STATUS_REG(pexIf), pexStatus); -+ -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvPexLocalDevNumGet - Get PEX interface local device number. -+* -+* DESCRIPTION: -+* This function gets the local device number of a given PEX interface. -+* -+* INPUT: -+* pexIf - PEX interface number. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Local device number. 0xffffffff on Error -+* -+*******************************************************************************/ -+MV_U32 mvPexLocalDevNumGet(MV_U32 pexIf) -+{ -+ MV_U32 pexStatus; -+ -+ /* Parameter checking */ -+ -+ if (PEX_DEFAULT_IF != pexIf) -+ { -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexLocalDevNumGet: ERR. Invalid PEX interface %d\n", -+ pexIf); -+ return 0xFFFFFFFF; -+ } -+ } -+ -+ pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); -+ -+ pexStatus &= PXSR_PEX_DEV_NUM_MASK; -+ -+ return (pexStatus >> PXSR_PEX_DEV_NUM_OFFS); -+} -+ -+MV_VOID mvPexPhyRegRead(MV_U32 pexIf, MV_U32 regOffset, MV_U16 *value) -+{ -+ -+ MV_U32 regAddr; -+ if (pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexPhyRegRead: ERR. Invalid PEX interface %d\n", pexIf); -+ return; -+ } -+ regAddr = (BIT31 | ((regOffset & 0x3fff) << 16)); -+ MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexIf), regAddr); -+ *value = MV_REG_READ(PEX_PHY_ACCESS_REG(pexIf)); -+} -+ -+ -+MV_VOID mvPexPhyRegWrite(MV_U32 pexIf, MV_U32 regOffset, MV_U16 value) -+{ -+ -+ MV_U32 regAddr; -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexPhyRegWrite: ERR. Invalid PEX interface %d\n", pexIf); -+ return; -+ } -+ regAddr = (((regOffset & 0x3fff) << 16) | value); -+ MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexIf), regAddr); -+} -+ -+/******************************************************************************* -+* mvPexActiveStateLinkPMEnable -+* -+* DESCRIPTION: -+* Enable Active Link State Power Management -+* -+* INPUT: -+* pexIf - PEX interface number. -+* enable - MV_TRUE to enable ASPM, MV_FALSE to disable. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* MV_OK on success , MV_ERROR otherwise -+* -+*******************************************************************************/ -+MV_STATUS mvPexActiveStateLinkPMEnable(MV_U32 pexIf, MV_BOOL enable) -+{ -+ MV_U32 reg; -+ -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexActiveStateLinkPMEnable: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_ERROR; -+ } -+ -+ reg = MV_REG_READ(PEX_PWR_MNG_EXT_REG(pexIf)) & ~PXPMER_L1_ASPM_EN_MASK; -+ if(enable == MV_TRUE) -+ reg |= PXPMER_L1_ASPM_EN_MASK; -+ MV_REG_WRITE(PEX_PWR_MNG_EXT_REG(pexIf), reg); -+ -+ /* Enable / Disable L0/1 entry */ -+ reg = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG)) -+ & ~PXLCSR_ASPM_CNT_MASK; -+ if(enable == MV_TRUE) -+ reg |= PXLCSR_ASPM_CNT_L0S_L1S_ENT_SUPP; -+ MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG), reg); -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvPexForceX1 -+* -+* DESCRIPTION: -+* shut down lanes 1-3 if recognize that attached to an x1 end-point -+* INPUT: -+* pexIf - PEX interface number. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* MV_OK on success , MV_ERROR otherwise -+* -+*******************************************************************************/ -+MV_U32 mvPexForceX1(MV_U32 pexIf) -+{ -+ MV_U32 regData = 0; -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexForceX1: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_BAD_PARAM; -+ } -+ -+ regData = MV_REG_READ(PEX_CTRL_REG(pexIf)) & ~(PXCR_CONF_LINK_MASK) ; -+ regData |= PXCR_CONF_LINK_X1; -+ -+ MV_REG_WRITE(PEX_CTRL_REG(pexIf), regData); -+ return MV_OK; -+} -+ -+MV_BOOL mvPexIsPowerUp(MV_U32 pexIf) -+{ -+ if(pexIf >= mvCtrlPexMaxIfGet()) -+ { -+ mvOsPrintf("mvPexIsPowerUp: ERR. Invalid PEX interface %d\n", pexIf); -+ return MV_FALSE; -+ } -+ return mvCtrlPwrClckGet(PEX_UNIT_ID, pexIf); -+} -+ -+ -+MV_VOID mvPexPowerDown(MV_U32 pexIf) -+{ -+ if ( (mvCtrlModelGet() == MV_78XX0_DEV_ID) || -+ (mvCtrlModelGet() == MV_76100_DEV_ID) || -+ (mvCtrlModelGet() == MV_78100_DEV_ID) || -+ (mvCtrlModelGet() == MV_78200_DEV_ID) ) -+ { -+ mvCtrlPwrClckSet(PEX_UNIT_ID, pexIf, MV_FALSE); -+ } -+ else -+ { -+ MV_REG_WRITE((0x41B00 -(pexIf)*0x10000), 0x20800087); -+ } -+} -+ -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,168 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCPEXH -+#define __INCPEXH -+ -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "pex/mvPexRegs.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+ -+ -+ -+/* NOTE not supported in this driver:*/ -+ -+ -+/* defines */ -+/* The number of supported PEX interfaces depend on Marvell controller */ -+/* device number. This device number ID is located on the PEX unit */ -+/* configuration header. This creates a loop where calling PEX */ -+/* configuration read/write routine results a call to get PEX configuration */ -+/* information etc. This macro defines a default PEX interface. This PEX */ -+/* interface is sure to exist. */ -+#define PEX_DEFAULT_IF 0 -+ -+ -+/* typedefs */ -+/* The Marvell controller supports both root complex and end point devices */ -+/* This enumeration describes the PEX type. */ -+typedef enum _mvPexType -+{ -+ MV_PEX_ROOT_COMPLEX, /* root complex device */ -+ MV_PEX_END_POINT /* end point device */ -+}MV_PEX_TYPE; -+ -+typedef enum _mvPexWidth -+{ -+ MV_PEX_WITDH_X1 = 1, -+ MV_PEX_WITDH_X2, -+ MV_PEX_WITDH_X3, -+ MV_PEX_WITDH_X4, -+ MV_PEX_WITDH_INVALID -+}MV_PEX_WIDTH; -+ -+/* PEX Bar attributes */ -+typedef struct _mvPexMode -+{ -+ MV_PEX_TYPE pexType; -+ MV_PEX_WIDTH pexWidth; -+ MV_BOOL pexLinkUp; -+}MV_PEX_MODE; -+ -+ -+ -+/* Global Functions prototypes */ -+/* mvPexInit - Initialize PEX interfaces*/ -+MV_STATUS mvPexHalInit(MV_U32 pexIf, MV_PEX_TYPE pexType); -+ -+/* mvPexModeGet - Get Pex If mode */ -+MV_U32 mvPexModeGet(MV_U32 pexIf,MV_PEX_MODE *pexMode); -+ -+/* mvPexConfigRead - Read from configuration space */ -+MV_U32 mvPexConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func,MV_U32 regOff); -+ -+/* mvPexConfigWrite - Write to configuration space */ -+MV_STATUS mvPexConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data); -+ -+/* mvPexMasterEnable - Enable/disale PEX interface master transactions.*/ -+MV_STATUS mvPexMasterEnable(MV_U32 pexIf, MV_BOOL enable); -+ -+/* mvPexSlaveEnable - Enable/disale PEX interface slave transactions.*/ -+MV_STATUS mvPexSlaveEnable(MV_U32 pexIf, MV_U32 bus,MV_U32 dev, MV_BOOL enable); -+ -+/* mvPexLocalBusNumSet - Set PEX interface local bus number.*/ -+MV_STATUS mvPexLocalBusNumSet(MV_U32 pexIf, MV_U32 busNum); -+ -+/* mvPexLocalBusNumGet - Get PEX interface local bus number.*/ -+MV_U32 mvPexLocalBusNumGet(MV_U32 pexIf); -+ -+/* mvPexLocalDevNumSet - Set PEX interface local device number.*/ -+MV_STATUS mvPexLocalDevNumSet(MV_U32 pexIf, MV_U32 devNum); -+ -+/* mvPexLocalDevNumGet - Get PEX interface local device number.*/ -+MV_U32 mvPexLocalDevNumGet(MV_U32 pexIf); -+/* mvPexForceX1 - Force PEX interface to X1 mode. */ -+MV_U32 mvPexForceX1(MV_U32 pexIf); -+ -+/* mvPexIsPowerUp - Is PEX interface Power up? */ -+MV_BOOL mvPexIsPowerUp(MV_U32 pexIf); -+ -+/* mvPexPowerDown - Power Down */ -+MV_VOID mvPexPowerDown(MV_U32 pexIf); -+ -+/* mvPexPowerUp - Power Up */ -+MV_VOID mvPexPowerUp(MV_U32 pexIf); -+ -+/* mvPexPhyRegRead - Pex phy read */ -+MV_VOID mvPexPhyRegRead(MV_U32 pexIf, MV_U32 regOffset, MV_U16 *value); -+ -+/* mvPexPhyRegWrite - Pex phy write */ -+MV_VOID mvPexPhyRegWrite(MV_U32 pexIf, MV_U32 regOffset, MV_U16 value); -+ -+MV_STATUS mvPexActiveStateLinkPMEnable(MV_U32 pexIf, MV_BOOL enable); -+ -+#endif /* #ifndef __INCPEXH */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,751 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCPEXREGSH -+#define __INCPEXREGSH -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* defines */ -+#define MAX_PEX_DEVICES 32 -+#define MAX_PEX_FUNCS 8 -+#define MAX_PEX_BUSSES 256 -+ -+ -+ -+/*********************************************************/ -+/* PCI Express Configuration Cycles Generation Registers */ -+/*********************************************************/ -+ -+#define PEX_CFG_ADDR_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x18F8) -+#define PEX_CFG_DATA_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x18FC) -+#define PEX_PHY_ACCESS_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1B00) -+/* PCI Express Configuration Address Register */ -+/* PEX_CFG_ADDR_REG (PXCAR)*/ -+ -+#define PXCAR_REG_NUM_OFFS 2 -+#define PXCAR_REG_NUM_MAX 0x3F -+#define PXCAR_REG_NUM_MASK (PXCAR_REG_NUM_MAX << PXCAR_REG_NUM_OFFS) -+#define PXCAR_FUNC_NUM_OFFS 8 -+#define PXCAR_FUNC_NUM_MAX 0x7 -+#define PXCAR_FUNC_NUM_MASK (PXCAR_FUNC_NUM_MAX << PXCAR_FUNC_NUM_OFFS) -+#define PXCAR_DEVICE_NUM_OFFS 11 -+#define PXCAR_DEVICE_NUM_MAX 0x1F -+#define PXCAR_DEVICE_NUM_MASK (PXCAR_DEVICE_NUM_MAX << PXCAR_DEVICE_NUM_OFFS) -+#define PXCAR_BUS_NUM_OFFS 16 -+#define PXCAR_BUS_NUM_MAX 0xFF -+#define PXCAR_BUS_NUM_MASK (PXCAR_BUS_NUM_MAX << PXCAR_BUS_NUM_OFFS) -+#define PXCAR_EXT_REG_NUM_OFFS 24 -+#define PXCAR_EXT_REG_NUM_MAX 0xF -+ -+/* in pci express register address is now the legacy register address (8 bits) -+with the new extended register address (more 4 bits) , below is the mask of -+the upper 4 bits of the full register address */ -+ -+#define PXCAR_REAL_EXT_REG_NUM_OFFS 8 -+#define PXCAR_EXT_REG_NUM_MASK (PXCAR_EXT_REG_NUM_MAX << PXCAR_EXT_REG_NUM_OFFS) -+#define PXCAR_CONFIG_EN BIT31 -+ -+#define PXCAR_REAL_EXT_REG_NUM_OFFS 8 -+#define PXCAR_REAL_EXT_REG_NUM_MASK (0xF << PXCAR_REAL_EXT_REG_NUM_OFFS) -+ -+/* The traditional PCI spec defined 6-bit field to describe register offset.*/ -+/* The new PCI Express extend the register offset by an extra 4-bits. */ -+/* The below macro assign 10-bit register offset into the apprpreate */ -+/* fields in the CFG_ADDR_REG */ -+#define PXCAR_REG_OFFS_SET(regOffs) \ -+ ( (regOff & PXCAR_REG_NUM_MASK) | \ -+ ( ((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >> PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS) ) -+ -+/***********************************/ -+/* PCI Express Interrupt registers */ -+/***********************************/ -+#define PEX_CAUSE_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1900) -+#define PEX_MASK_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1910) -+ -+#define PXICR_TX_REQ_IN_DLDOWN_ERR BIT0 /* Transmit request while field */ -+ /* of the PCI Express */ -+/* PCI Express Interrupt Cause */ -+/* PEX_INT_CAUSE_REG (PXICR)*/ -+/* PEX_INT_MASK_REG*/ -+/* -+NOTE:All bits except bits[27:24] are Read/Write Clear only. A cause bit sets -+upon an error event occurrence. A write of 0 clears the bit. A write of 1 has -+no affect. Bits[24:27} are set and cleared upon reception of interrupt -+emulation messages. -+ -+Mask bit per cause bit. If a bit is set to 1, the corresponding event is -+enabled. Mask does not affect setting of the Interrupt Cause register bits; -+it only affects the assertion of the interrupt .*/ -+ -+ -+#define PXICR_MDIS_CAUSE BIT1 /* Attempt to generate PCI transaction -+ while master is disabled */ -+#define PXICR_ERR_WRTO_REG_CAUSE BIT3 /* Erroneous write attempt to -+ PCI Express internal register*/ -+#define PXICR_HIT_DFLT_WIN_ERR BIT4 /* Hit Default Window Error */ -+#define PXICR_RX_RAM_PAR_ERR BIT6 /* Rx RAM Parity Error */ -+#define PXICR_TX_RAM_PAR_ERR BIT7 /* Tx RAM Parity Error */ -+#define PXICR_COR_ERR_DET BIT8 /* Correctable Error Detected*/ -+#define PXICR_NF_ERR_DET BIT9 /* Non-Fatal Error Detected*/ -+#define PXICR_FERR_DET BIT10 /* Fatal Error Detected*/ -+#define PXICR_DSTATE_CHANGE BIT11 /* Dstate Change Indication*/ -+#define PXICR_BIST BIT12 /* PCI-Express BIST activated*/ -+#define PXICR_FLW_CTRL_PROT BIT14 /* Flow Control Protocol Error */ -+ -+#define PXICR_RCV_UR_CA_ERR BIT15 /* Received UR or CA status. */ -+#define PXICR_RCV_ERR_FATAL BIT16 /* Received ERR_FATAL message.*/ -+#define PXICR_RCV_ERR_NON_FATAL BIT17 /* Received ERR_NONFATAL message*/ -+#define PXICR_RCV_ERR_COR BIT18 /* Received ERR_COR message.*/ -+#define PXICR_RCV_CRS BIT19 /* Received CRS completion status*/ -+#define PXICR_SLV_HOT_RESET BIT20 /* Received Hot Reset Indication*/ -+#define PXICR_SLV_DIS_LINK BIT21 /* Slave Disable Link Indication*/ -+#define PXICR_SLV_LB BIT22 /* Slave Loopback Indication*/ -+#define PXICR_LINK_FAIL BIT23 /* Link Failure indication.*/ -+#define PXICR_RCV_INTA BIT24 /* IntA status.*/ -+#define PXICR_RCV_INTB BIT25 /* IntB status.*/ -+#define PXICR_RCV_INTC BIT26 /* IntC status.*/ -+#define PXICR_RCV_INTD BIT27 /* IntD status.*/ -+#define PXICR_RCV_PM_PME BIT28 /* Received PM_PME message. */ -+ -+ -+/********************************************/ -+/* PCI Express Control and Status Registers */ -+/********************************************/ -+#define PEX_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A00) -+#define PEX_STATUS_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A04) -+#define PEX_COMPLT_TMEOUT_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A10) -+#define PEX_PWR_MNG_EXT_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A18) -+#define PEX_FLOW_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A20) -+#define PEX_ACK_TMR_4X_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A30) -+#define PEX_ACK_TMR_1X_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A40) -+#define PEX_TL_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1AB0) -+ -+ -+#define PEX_RAM_PARITY_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A50) -+/* PCI Express Control Register */ -+/* PEX_CTRL_REG (PXCR) */ -+ -+#define PXCR_CONF_LINK_OFFS 0 -+#define PXCR_CONF_LINK_MASK (1 << PXCR_CONF_LINK_OFFS) -+#define PXCR_CONF_LINK_X4 (0 << PXCR_CONF_LINK_OFFS) -+#define PXCR_CONF_LINK_X1 (1 << PXCR_CONF_LINK_OFFS) -+#define PXCR_DEV_TYPE_CTRL_OFFS 1 /*PCI ExpressDevice Type Control*/ -+#define PXCR_DEV_TYPE_CTRL_MASK BIT1 -+#define PXCR_DEV_TYPE_CTRL_CMPLX (1 << PXCR_DEV_TYPE_CTRL_OFFS) -+#define PXCR_DEV_TYPE_CTRL_POINT (0 << PXCR_DEV_TYPE_CTRL_OFFS) -+#define PXCR_CFG_MAP_TO_MEM_EN BIT2 /* Configuration Header Mapping -+ to Memory Space Enable */ -+ -+#define PXCR_CFG_MAP_TO_MEM_EN BIT2 /* Configuration Header Mapping -+ to Memory Space Enable*/ -+ -+#define PXCR_RSRV1_OFFS 5 -+#define PXCR_RSRV1_MASK (0x7 << PXCR_RSRV1_OFFS) -+#define PXCR_RSRV1_VAL (0x0 << PXCR_RSRV1_OFFS) -+ -+#define PXCR_CONF_MAX_OUTSTND_OFFS 8 /*Maximum outstanding NP requests as a master*/ -+#define PXCR_CONF_MAX_OUTSTND_MASK (0x3 << PXCR_CONF_MAX_OUTSTND_OFFS) -+ -+ -+#define PXCR_CONF_NFTS_OFFS 16 /*number of FTS Ordered-Sets*/ -+#define PXCR_CONF_NFTS_MASK (0xff << PXCR_CONF_NFTS_OFFS) -+ -+#define PXCR_CONF_MSTR_HOT_RESET BIT24 /*Master Hot-Reset.*/ -+#define PXCR_CONF_MSTR_LB BIT26 /* Master Loopback */ -+#define PXCR_CONF_MSTR_DIS_SCRMB BIT27 /* Master Disable Scrambling*/ -+#define PXCR_CONF_DIRECT_DIS_SCRMB BIT28 /* Direct Disable Scrambling*/ -+ -+/* PCI Express Status Register */ -+/* PEX_STATUS_REG (PXSR) */ -+ -+#define PXSR_DL_DOWN BIT0 /* DL_Down indication.*/ -+ -+#define PXSR_PEX_BUS_NUM_OFFS 8 /* Bus Number Indication */ -+#define PXSR_PEX_BUS_NUM_MASK (0xff << PXSR_PEX_BUS_NUM_OFFS) -+ -+#define PXSR_PEX_DEV_NUM_OFFS 16 /* Device Number Indication */ -+#define PXSR_PEX_DEV_NUM_MASK (0x1f << PXSR_PEX_DEV_NUM_OFFS) -+ -+#define PXSR_PEX_SLV_HOT_RESET BIT24 /* Slave Hot Reset Indication*/ -+#define PXSR_PEX_SLV_DIS_LINK BIT25 /* Slave Disable Link Indication*/ -+#define PXSR_PEX_SLV_LB BIT26 /* Slave Loopback Indication*/ -+#define PXSR_PEX_SLV_DIS_SCRMB BIT27 /* Slave Disable Scrambling Indication*/ -+ -+ -+/* PCI Express Completion Timeout Register */ -+/* PEX_COMPLT_TMEOUT_REG (PXCTR)*/ -+ -+#define PXCTR_CMP_TO_THRSHLD_OFFS 0 /* Completion Timeout Threshold */ -+#define PXCTR_CMP_TO_THRSHLD_MASK (0xffff << PXCTR_CMP_TO_THRSHLD_OFFS) -+ -+/* PCI Express Power Management Extended Register */ -+/* PEX_PWR_MNG_EXT_REG (PXPMER) */ -+ -+#define PXPMER_L1_ASPM_EN_OFFS 1 -+#define PXPMER_L1_ASPM_EN_MASK (0x1 << PXPMER_L1_ASPM_EN_OFFS) -+ -+/* PCI Express Flow Control Register */ -+/* PEX_FLOW_CTRL_REG (PXFCR)*/ -+ -+#define PXFCR_PH_INIT_FC_OFFS 0 /*Posted Headers Flow Control Credit -+ Initial Value.*/ -+#define PXFCR_PH_INIT_FC_MASK (0xff << PXFCR_PH_INIT_FC_OFFS) -+ -+ -+#define PXFCR_NPH_INIT_FC_OFFS 8 /* Classified Non-Posted Headers -+ Flow Control Credit Initial Value*/ -+#define PXFCR_NPH_INIT_FC_MASK (0xff << PXFCR_NPH_INIT_FC_OFFS) -+ -+#define PXFCR_CH_INIT_FC_OFFS 16 /* Completion Headers Flow Control -+ Credit Initial Value Infinite*/ -+ -+#define PXFCR_CH_INIT_FC_MASK (0xff << PXFCR_CH_INIT_FC_OFFS) -+ -+#define PXFCR_FC_UPDATE_TO_OFFS 24 /* Flow Control Update Timeout */ -+#define PXFCR_FC_UPDATE_TO_MASK (0xff << PXFCR_FC_UPDATE_TO_OFFS) -+ -+/* PCI Express Acknowledge Timers (4X) Register */ -+/* PEX_ACK_TMR_4X_REG (PXAT4R) */ -+#define PXAT1R_ACK_LAT_TOX4_OFFS 0 /* Ack Latency Timer Timeout Value */ -+#define PXAT1R_ACK_LAT_TOX4_MASK (0xffff << PXAT4R_ACK_LAT_TOX1_OFFS) -+#define PXAT1R_ACK_RPLY_TOX4_OFFS 16 /* Ack Replay Timer Timeout Value */ -+#define PXAT1R_ACK_RPLY_TOX4_MASK (0xffff << PXAT1R_ACK_RPLY_TOX1_OFFS) -+ -+/* PCI Express Acknowledge Timers (1X) Register */ -+/* PEX_ACK_TMR_1X_REG (PXAT1R) */ -+ -+#define PXAT1R_ACK_LAT_TOX1_OFFS 0 /* Acknowledge Latency Timer Timeout -+ Value for 1X Link*/ -+#define PXAT1R_ACK_LAT_TOX1_MASK (0xffff << PXAT1R_ACK_LAT_TOX1_OFFS) -+ -+#define PXAT1R_ACK_RPLY_TOX1_OFFS 16 /* Acknowledge Replay Timer Timeout -+ Value for 1X*/ -+#define PXAT1R_ACK_RPLY_TOX1_MASK (0xffff << PXAT1R_ACK_RPLY_TOX1_OFFS) -+ -+ -+/* PCI Express TL Control Register */ -+/* PEX_TL_CTRL_REG (PXTCR) */ -+ -+#define PXTCR_TX_CMP_BUFF_NO_OFFS 8 /*Number of completion buffers in Tx*/ -+#define PXTCR_TX_CMP_BUFF_NO_MASK (0xf << PXTCR_TX_CMP_BUFF_NO_OFFS) -+ -+/* PCI Express Debug MAC Control Register */ -+/* PEX_DEBUG_MAC_CTRL_REG (PXDMCR) */ -+ -+#define PXDMCR_LINKUP BIT4 -+ -+ -+ -+/**********************************************/ -+/* PCI Express Configuration Header Registers */ -+/**********************************************/ -+#define PEX_CFG_DIRECT_ACCESS(pexIf,cfgReg) ((PEX_IF_BASE(pexIf)) + (cfgReg)) -+ -+#define PEX_DEVICE_AND_VENDOR_ID 0x000 -+#define PEX_STATUS_AND_COMMAND 0x004 -+#define PEX_CLASS_CODE_AND_REVISION_ID 0x008 -+#define PEX_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE 0x00C -+#define PEX_MEMORY_BAR_BASE_ADDR(barNum) (0x010 + ((barNum) << 2)) -+#define PEX_MV_BAR_BASE(barNum) (0x010 + (barNum) * 8) -+#define PEX_MV_BAR_BASE_HIGH(barNum) (0x014 + (barNum) * 8) -+#define PEX_BAR0_INTER_REG 0x010 -+#define PEX_BAR0_INTER_REG_HIGH 0x014 -+#define PEX_BAR1_REG 0x018 -+#define PEX_BAR1_REG_HIGH 0x01C -+#define PEX_BAR2_REG 0x020 -+#define PEX_BAR2_REG_HIGH 0x024 -+ -+#define PEX_SUBSYS_ID_AND_SUBSYS_VENDOR_ID 0x02C -+#define PEX_EXPANSION_ROM_BASE_ADDR_REG 0x030 -+#define PEX_CAPABILTY_LIST_POINTER 0x034 -+#define PEX_INTERRUPT_PIN_AND_LINE 0x03C -+ -+/* capability list */ -+#define PEX_POWER_MNG_CAPABILITY 0x040 -+#define PEX_POWER_MNG_STATUS_CONTROL 0x044 -+ -+#define PEX_MSI_MESSAGE_CONTROL 0x050 -+#define PEX_MSI_MESSAGE_ADDR 0x054 -+#define PEX_MSI_MESSAGE_HIGH_ADDR 0x058 -+#define PEX_MSI_MESSAGE_DATA 0x05C -+ -+#define PEX_CAPABILITY_REG 0x60 -+#define PEX_DEV_CAPABILITY_REG 0x64 -+#define PEX_DEV_CTRL_STAT_REG 0x68 -+#define PEX_LINK_CAPABILITY_REG 0x6C -+#define PEX_LINK_CTRL_STAT_REG 0x70 -+ -+#define PEX_ADV_ERR_RPRT_HDR_TRGT_REG 0x100 -+#define PEX_UNCORRECT_ERR_STAT_REG 0x104 -+#define PEX_UNCORRECT_ERR_MASK_REG 0x108 -+#define PEX_UNCORRECT_ERR_SERVITY_REG 0x10C -+#define PEX_CORRECT_ERR_STAT_REG 0x110 -+#define PEX_CORRECT_ERR_MASK_REG 0x114 -+#define PEX_ADV_ERR_CAPABILITY_CTRL_REG 0x118 -+#define PEX_HDR_LOG_FIRST_DWORD_REG 0x11C -+#define PEX_HDR_LOG_SECOND_DWORD_REG 0x120 -+#define PEX_HDR_LOG_THIRD_DWORD_REG 0x124 -+#define PEX_HDR_LOG_FOURTH_DWORD_REG 0x128 -+ -+ -+ -+/* PCI Express Device and Vendor ID Register*/ -+/*PEX_DEVICE_AND_VENDOR_ID (PXDAVI)*/ -+ -+#define PXDAVI_VEN_ID_OFFS 0 /* Vendor ID */ -+#define PXDAVI_VEN_ID_MASK (0xffff << PXDAVI_VEN_ID_OFFS) -+ -+#define PXDAVI_DEV_ID_OFFS 16 /* Device ID */ -+#define PXDAVI_DEV_ID_MASK (0xffff << PXDAVI_DEV_ID_OFFS) -+ -+ -+/* PCI Express Command and Status Register*/ -+/*PEX_STATUS_AND_COMMAND (PXSAC)*/ -+ -+#define PXSAC_IO_EN BIT0 /* IO Enable */ -+#define PXSAC_MEM_EN BIT1 /* Memory Enable */ -+#define PXSAC_MASTER_EN BIT2 /* Master Enable */ -+#define PXSAC_PERR_EN BIT6 /* Parity Errors Respond Enable */ -+#define PXSAC_SERR_EN BIT8 /* Ability to assert SERR# line */ -+#define PXSAC_INT_DIS BIT10 /* Interrupt Disable */ -+#define PXSAC_INT_STAT BIT19 /* Interrupt Status */ -+#define PXSAC_CAP_LIST BIT20 /* Capability List Support */ -+#define PXSAC_MAS_DATA_PERR BIT24 /* Master Data Parity Error */ -+#define PXSAC_SLAVE_TABORT BIT27 /* Signalled Target Abort */ -+#define PXSAC_RT_ABORT BIT28 /* Recieved Target Abort */ -+#define PXSAC_MABORT BIT29 /* Recieved Master Abort */ -+#define PXSAC_SYSERR BIT30 /* Signalled system error */ -+#define PXSAC_DET_PARERR BIT31 /* Detect Parity Error */ -+ -+ -+/* PCI Express Class Code and Revision ID Register*/ -+/*PEX_CLASS_CODE_AND_REVISION_ID (PXCCARI)*/ -+ -+#define PXCCARI_REVID_OFFS 0 /* Revision ID */ -+#define PXCCARI_REVID_MASK (0xff << PXCCARI_REVID_OFFS) -+ -+#define PXCCARI_FULL_CLASS_OFFS 8 /* Full Class Code */ -+#define PXCCARI_FULL_CLASS_MASK (0xffffff << PXCCARI_FULL_CLASS_OFFS) -+ -+#define PXCCARI_PROGIF_OFFS 8 /* Prog .I/F*/ -+#define PXCCARI_PROGIF_MASK (0xff << PXCCARI_PROGIF_OFFS) -+ -+#define PXCCARI_SUB_CLASS_OFFS 16 /* Sub Class*/ -+#define PXCCARI_SUB_CLASS_MASK (0xff << PXCCARI_SUB_CLASS_OFFS) -+ -+#define PXCCARI_BASE_CLASS_OFFS 24 /* Base Class*/ -+#define PXCCARI_BASE_CLASS_MASK (0xff << PXCCARI_BASE_CLASS_OFFS) -+ -+ -+/* PCI Express BIST, Header Type and Cache Line Size Register*/ -+/*PEX_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE (PXBHTLTCL)*/ -+ -+#define PXBHTLTCL_CACHELINE_OFFS 0 /* Specifies the cache line size */ -+#define PXBHTLTCL_CACHELINE_MASK (0xff << PXBHTLTCL_CACHELINE_OFFS) -+ -+#define PXBHTLTCL_HEADTYPE_FULL_OFFS 16 /* Full Header Type */ -+#define PXBHTLTCL_HEADTYPE_FULL_MASK (0xff << PXBHTLTCL_HEADTYPE_FULL_OFFS) -+ -+#define PXBHTLTCL_MULTI_FUNC BIT23 /* Multi/Single function */ -+ -+#define PXBHTLTCL_HEADER_OFFS 16 /* Header type */ -+#define PXBHTLTCL_HEADER_MASK (0x7f << PXBHTLTCL_HEADER_OFFS) -+#define PXBHTLTCL_HEADER_STANDARD (0x0 << PXBHTLTCL_HEADER_OFFS) -+#define PXBHTLTCL_HEADER_PCI2PCI_BRIDGE (0x1 << PXBHTLTCL_HEADER_OFFS) -+ -+ -+#define PXBHTLTCL_BISTCOMP_OFFS 24 /* BIST Completion Code */ -+#define PXBHTLTCL_BISTCOMP_MASK (0xf << PXBHTLTCL_BISTCOMP_OFFS) -+ -+#define PXBHTLTCL_BISTACT BIT30 /* BIST Activate bit */ -+#define PXBHTLTCL_BISTCAP BIT31 /* BIST Capable Bit */ -+#define PXBHTLTCL_BISTCAP_OFFS 31 -+#define PXBHTLTCL_BISTCAP_MASK BIT31 -+#define PXBHTLTCL_BISTCAP_VAL 0 -+ -+ -+/* PCI Express Subsystem Device and Vendor ID */ -+/*PEX_SUBSYS_ID_AND_SUBSYS_VENDOR_ID (PXSIASVI)*/ -+ -+#define PXSIASVI_VENID_OFFS 0 /* Subsystem Manufacturer Vendor ID Number */ -+#define PXSIASVI_VENID_MASK (0xffff << PXSIASVI_VENID_OFFS) -+ -+#define PXSIASVI_DEVID_OFFS 16 /* Subsystem Device ID Number */ -+#define PXSIASVI_DEVID_MASK (0xffff << PXSIASVI_DEVID_OFFS) -+ -+ -+/* PCI Express Capability List Pointer Register*/ -+/*PEX_CAPABILTY_LIST_POINTER (PXCLP)*/ -+ -+#define PXCLP_CAPPTR_OFFS 0 /* Capability List Pointer */ -+#define PXCLP_CAPPTR_MASK (0xff << PXCLP_CAPPTR_OFFS) -+ -+/* PCI Express Interrupt Pin and Line Register */ -+/*PEX_INTERRUPT_PIN_AND_LINE (PXIPAL)*/ -+ -+#define PXIPAL_INTLINE_OFFS 0 /* Interrupt line (IRQ) */ -+#define PXIPAL_INTLINE_MASK (0xff << PXIPAL_INTLINE_OFFS) -+ -+#define PXIPAL_INTPIN_OFFS 8 /* interrupt pin (A,B,C,D) */ -+#define PXIPAL_INTPIN_MASK (0xff << PXIPAL_INTPIN_OFFS) -+ -+ -+/* PCI Express Power Management Capability Header Register*/ -+/*PEX_POWER_MNG_CAPABILITY (PXPMC)*/ -+ -+#define PXPMC_CAP_ID_OFFS 0 /* Capability ID */ -+#define PXPMC_CAP_ID_MASK (0xff << PXPMC_CAP_ID_OFFS) -+ -+#define PXPMC_NEXT_PTR_OFFS 8 /* Next Item Pointer */ -+#define PXPMC_NEXT_PTR_MASK (0xff << PXPMC_NEXT_PTR_OFFS) -+ -+#define PXPMC_PMC_VER_OFFS 16 /* PCI Power Management Capability Version*/ -+#define PXPMC_PMC_VER_MASK (0x7 << PXPMC_PMC_VER_OFFS) -+ -+#define PXPMC_DSI BIT21/* Device Specific Initialization */ -+ -+#define PXPMC_AUX_CUR_OFFS 22 /* Auxiliary Current Requirements */ -+#define PXPMC_AUX_CUR_MASK (0x7 << PXPMC_AUX_CUR_OFFS) -+ -+#define PXPMC_D1_SUP BIT25 /* D1 Power Management support*/ -+ -+#define PXPMC_D2_SUP BIT26 /* D2 Power Management support*/ -+ -+#define PXPMC_PME_SUP_OFFS 27 /* PM Event generation support*/ -+#define PXPMC_PME_SUP_MASK (0x1f << PXPMC_PME_SUP_OFFS) -+ -+/* PCI Express Power Management Control and Status Register*/ -+/*PEX_POWER_MNG_STATUS_CONTROL (PXPMSC)*/ -+ -+#define PXPMSC_PM_STATE_OFFS 0 /* Power State */ -+#define PXPMSC_PM_STATE_MASK (0x3 << PXPMSC_PM_STATE_OFFS) -+#define PXPMSC_PM_STATE_D0 (0x0 << PXPMSC_PM_STATE_OFFS) -+#define PXPMSC_PM_STATE_D1 (0x1 << PXPMSC_PM_STATE_OFFS) -+#define PXPMSC_PM_STATE_D2 (0x2 << PXPMSC_PM_STATE_OFFS) -+#define PXPMSC_PM_STATE_D3 (0x3 << PXPMSC_PM_STATE_OFFS) -+ -+#define PXPMSC_PME_EN BIT8/* PM_PME Message Generation Enable */ -+ -+#define PXPMSC_PM_DATA_SEL_OFFS 9 /* Data Select*/ -+#define PXPMSC_PM_DATA_SEL_MASK (0xf << PXPMSC_PM_DATA_SEL_OFFS) -+ -+#define PXPMSC_PM_DATA_SCALE_OFFS 13 /* Data Scale */ -+#define PXPMSC_PM_DATA_SCALE_MASK (0x3 << PXPMSC_PM_DATA_SCALE_OFFS) -+ -+#define PXPMSC_PME_STAT BIT15/* PME Status */ -+ -+#define PXPMSC_PM_DATA_OFFS 24 /* State Data */ -+#define PXPMSC_PM_DATA_MASK (0xff << PXPMSC_PM_DATA_OFFS) -+ -+ -+/* PCI Express MSI Message Control Register*/ -+/*PEX_MSI_MESSAGE_CONTROL (PXMMC)*/ -+ -+#define PXMMC_CAP_ID_OFFS 0 /* Capability ID */ -+#define PXMMC_CAP_ID_MASK (0xff << PXMMC_CAP_ID_OFFS) -+ -+#define PXMMC_NEXT_PTR_OFFS 8 /* Next Item Pointer */ -+#define PXMMC_NEXT_PTR_MASK (0xff << PXMMC_NEXT_PTR_OFFS) -+ -+#define PXMMC_MSI_EN BIT18 /* MSI Enable */ -+ -+#define PXMMC_MULTI_CAP_OFFS 17 /* Multiple Message Capable */ -+#define PXMMC_MULTI_CAP_MASK (0x7 << PXMMC_MULTI_CAP_OFFS) -+ -+#define PXMMC_MULTI_EN_OFFS 20 /* Multiple Messages Enable */ -+#define PXMMC_MULTI_EN_MASK (0x7 << PXMMC_MULTI_EN_OFFS) -+ -+#define PXMMC_ADDR64 BIT23 /* 64-bit Addressing Capable */ -+ -+ -+/* PCI Express MSI Message Address Register*/ -+/*PEX_MSI_MESSAGE_ADDR (PXMMA)*/ -+ -+#define PXMMA_MSI_ADDR_OFFS 2 /* Message Address corresponds to -+ Address[31:2] of the MSI MWr TLP*/ -+#define PXMMA_MSI_ADDR_MASK (0x3fffffff << PXMMA_MSI_ADDR_OFFS) -+ -+ -+/* PCI Express MSI Message Address (High) Register */ -+/*PEX_MSI_MESSAGE_HIGH_ADDR (PXMMHA)*/ -+ -+#define PXMMA_MSI_ADDR_H_OFFS 0 /* Message Upper Address corresponds to -+ Address[63:32] of the MSI MWr TLP*/ -+#define PXMMA_MSI_ADDR_H_MASK (0xffffffff << PXMMA_MSI_ADDR_H_OFFS ) -+ -+ -+/* PCI Express MSI Message Data Register*/ -+/*PEX_MSI_MESSAGE_DATA (PXMMD)*/ -+ -+#define PXMMD_MSI_DATA_OFFS 0 /* Message Data */ -+#define PXMMD_MSI_DATA_MASK (0xffff << PXMMD_MSI_DATA_OFFS ) -+ -+ -+/* PCI Express Capability Register*/ -+/*PEX_CAPABILITY_REG (PXCR)*/ -+ -+#define PXCR_CAP_ID_OFFS 0 /* Capability ID*/ -+#define PXCR_CAP_ID_MASK (0xff << PXCR_CAP_ID_OFFS) -+ -+#define PXCR_NEXT_PTR_OFFS 8 /* Next Item Pointer*/ -+#define PXCR_NEXT_PTR_MASK (0xff << PXCR_NEXT_PTR_OFFS) -+ -+#define PXCR_CAP_VER_OFFS 16 /* Capability Version*/ -+#define PXCR_CAP_VER_MASK (0xf << PXCR_CAP_VER_OFFS) -+ -+#define PXCR_DEV_TYPE_OFFS 20 /* Device/Port Type*/ -+#define PXCR_DEV_TYPE_MASK (0xf << PXCR_DEV_TYPE_OFFS) -+ -+#define PXCR_SLOT_IMP BIT24 /* Slot Implemented*/ -+ -+#define PXCR_INT_MSG_NUM_OFFS 25 /* Interrupt Message Number*/ -+#define PXCR_INT_MSG_NUM_MASK (0x1f << PXCR_INT_MSG_NUM_OFFS) -+ -+ -+/* PCI Express Device Capabilities Register */ -+/*PEX_DEV_CAPABILITY_REG (PXDCR)*/ -+ -+#define PXDCR_MAX_PLD_SIZE_SUP_OFFS 0 /* Maximum Payload Size Supported*/ -+#define PXDCR_MAX_PLD_SIZE_SUP_MASK (0x7 << PXDCR_MAX_PLD_SIZE_SUP_OFFS) -+ -+#define PXDCR_EP_L0S_ACC_LAT_OFFS 6/* Endpoint L0s Acceptable Latency*/ -+#define PXDCR_EP_L0S_ACC_LAT_MASK (0x7 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+#define PXDCR_EP_L0S_ACC_LAT_64NS_LESS (0x0 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+#define PXDCR_EP_L0S_ACC_LAT_64NS_128NS (0x1 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+#define PXDCR_EP_L0S_ACC_LAT_128NS_256NS (0x2 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+#define PXDCR_EP_L0S_ACC_LAT_256NS_512NS (0x3 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+#define PXDCR_EP_L0S_ACC_LAT_512NS_1US (0x4 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+#define PXDCR_EP_L0S_ACC_LAT_1US_2US (0x5 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+#define PXDCR_EP_L0S_ACC_LAT_2US_4US (0x6 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+#define PXDCR_EP_L0S_ACC_LAT_4US_MORE (0x7 << PXDCR_EP_L0S_ACC_LAT_OFFS) -+ -+#define PXDCR_EP_L1_ACC_LAT_OFFS 9 /* Endpoint L1 Acceptable Latency*/ -+#define PXDCR_EP_L1_ACC_LAT_MASK (0x7 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXDCR_EP_L1_ACC_LAT_64NS_LESS (0x0 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXDCR_EP_L1_ACC_LAT_64NS_128NS (0x1 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXDCR_EP_L1_ACC_LAT_128NS_256NS (0x2 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXDCR_EP_L1_ACC_LAT_256NS_512NS (0x3 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXDCR_EP_L1_ACC_LAT_512NS_1US (0x4 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXDCR_EP_L1_ACC_LAT_1US_2US (0x5 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXDCR_EP_L1_ACC_LAT_2US_4US (0x6 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXDCR_EP_L1_ACC_LAT_4US_MORE (0x7 << PXDCR_EP_L1_ACC_LAT_OFFS) -+ -+ -+#define PXDCR_ATT_BUT_PRS_OFFS 12 /* Attention Button Present*/ -+#define PXDCR_ATT_BUT_PRS_MASK BIT12 -+#define PXDCR_ATT_BUT_PRS_IMPLEMENTED BIT12 -+ -+#define PXDCR_ATT_IND_PRS_OFFS 13 /* Attention Indicator Present*/ -+#define PXDCR_ATT_IND_PRS_MASK BIT13 -+#define PXDCR_ATT_IND_PRS_IMPLEMENTED BIT13 -+ -+#define PXDCR_PWR_IND_PRS_OFFS 14/* Power Indicator Present*/ -+#define PXDCR_PWR_IND_PRS_MASK BIT14 -+#define PXDCR_PWR_IND_PRS_IMPLEMENTED BIT14 -+ -+#define PXDCR_CAP_SPL_VAL_OFFS 18 /*Captured Slot Power Limit -+ Value*/ -+#define PXDCR_CAP_SPL_VAL_MASK (0xff << PXDCR_CAP_SPL_VAL_OFFS) -+ -+#define PXDCR_CAP_SP_LSCL_OFFS 26 /* Captured Slot Power Limit -+ Scale */ -+#define PXDCR_CAP_SP_LSCL_MASK (0x3 << PXDCR_CAP_SP_LSCL_OFFS) -+ -+/* PCI Express Device Control Status Register */ -+/*PEX_DEV_CTRL_STAT_REG (PXDCSR)*/ -+ -+#define PXDCSR_COR_ERR_REP_EN BIT0 /* Correctable Error Reporting Enable*/ -+#define PXDCSR_NF_ERR_REP_EN BIT1 /* Non-Fatal Error Reporting Enable*/ -+#define PXDCSR_F_ERR_REP_EN BIT2 /* Fatal Error Reporting Enable*/ -+#define PXDCSR_UR_REP_EN BIT3 /* Unsupported Request (UR) -+ Reporting Enable*/ -+#define PXDCSR_EN_RO BIT4 /* Enable Relaxed Ordering*/ -+ -+#define PXDCSR_MAX_PLD_SZ_OFFS 5 /* Maximum Payload Size*/ -+#define PXDCSR_MAX_PLD_SZ_MASK (0x7 << PXDCSR_MAX_PLD_SZ_OFFS) -+#define PXDCSR_MAX_PLD_SZ_128B (0x0 << PXDCSR_MAX_PLD_SZ_OFFS) -+#define PXDCSR_EN_NS BIT11 /* Enable No Snoop*/ -+ -+#define PXDCSR_MAX_RD_RQ_SZ_OFFS 12 /* Maximum Read Request Size*/ -+#define PXDCSR_MAX_RD_RQ_SZ_MASK (0x7 << PXDCSR_MAX_RD_RQ_SZ_OFFS) -+#define PXDCSR_MAX_RD_RQ_SZ_128B (0x0 << PXDCSR_MAX_RD_RQ_SZ_OFFS) -+#define PXDCSR_MAX_RD_RQ_SZ_256B (0x1 << PXDCSR_MAX_RD_RQ_SZ_OFFS) -+#define PXDCSR_MAX_RD_RQ_SZ_512B (0x2 << PXDCSR_MAX_RD_RQ_SZ_OFFS) -+#define PXDCSR_MAX_RD_RQ_SZ_1KB (0x3 << PXDCSR_MAX_RD_RQ_SZ_OFFS) -+#define PXDCSR_MAX_RD_RQ_SZ_2KB (0x4 << PXDCSR_MAX_RD_RQ_SZ_OFFS) -+#define PXDCSR_MAX_RD_RQ_SZ_4KB (0x5 << PXDCSR_MAX_RD_RQ_SZ_OFFS) -+ -+#define PXDCSR_COR_ERR_DET BIT16 /* Correctable Error Detected*/ -+#define PXDCSR_NF_ERR_DET BIT17 /* Non-Fatal Error Detected.*/ -+#define PXDCSR_F_ERR_DET BIT18 /* Fatal Error Detected.*/ -+#define PXDCSR_UR_DET BIT19 /* Unsupported Request Detected */ -+#define PXDCSR_AUX_PWR_DET BIT20 /* Reserved*/ -+ -+#define PXDCSR_TRANS_PEND_OFFS 21 /* Transactions Pending*/ -+#define PXDCSR_TRANS_PEND_MASK BIT21 -+#define PXDCSR_TRANS_PEND_NOT_COMPLETED (0x1 << PXDCSR_TRANS_PEND_OFFS) -+ -+ -+/* PCI Express Link Capabilities Register*/ -+/*PEX_LINK_CAPABILITY_REG (PXLCR)*/ -+ -+#define PXLCR_MAX_LINK_SPD_OFFS 0 /* Maximum Link Speed*/ -+#define PXLCR_MAX_LINK_SPD_MASK (0xf << PXLCR_MAX_LINK_SPD_OFFS) -+ -+#define PXLCR_MAX_LNK_WDTH_OFFS 3 /* Maximum Link Width*/ -+#define PXLCR_MAX_LNK_WDTH_MASK (0x3f << PXLCR_MAX_LNK_WDTH_OFFS) -+ -+#define PXLCR_ASPM_SUP_OFFS 10 /* Active State Link PM Support*/ -+#define PXLCR_ASPM_SUP_MASK (0x3 << PXLCR_ASPM_SUP_OFFS) -+ -+#define PXLCR_L0S_EXT_LAT_OFFS 12 /* L0s Exit Latency*/ -+#define PXLCR_L0S_EXT_LAT_MASK (0x7 << PXLCR_L0S_EXT_LAT_OFFS) -+#define PXLCR_L0S_EXT_LAT_64NS_LESS (0x0 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXLCR_L0S_EXT_LAT_64NS_128NS (0x1 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXLCR_L0S_EXT_LAT_128NS_256NS (0x2 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXLCR_L0S_EXT_LAT_256NS_512NS (0x3 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXLCR_L0S_EXT_LAT_512NS_1US (0x4 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXLCR_L0S_EXT_LAT_1US_2US (0x5 << PXDCR_EP_L1_ACC_LAT_OFFS) -+#define PXLCR_L0S_EXT_LAT_2US_4US (0x6 << PXDCR_EP_L1_ACC_LAT_OFFS) -+ -+#define PXLCR_POR_TNUM_OFFS 24 /* Port Number */ -+#define PXLCR_POR_TNUM_MASK (0xff << PXLCR_POR_TNUM_OFFS) -+ -+/* PCI Express Link Control Status Register */ -+/*PEX_LINK_CTRL_STAT_REG (PXLCSR)*/ -+ -+#define PXLCSR_ASPM_CNT_OFFS 0 /* Active State Link PM Control */ -+#define PXLCSR_ASPM_CNT_MASK (0x3 << PXLCSR_ASPM_CNT_OFFS) -+#define PXLCSR_ASPM_CNT_DISABLED (0x0 << PXLCSR_ASPM_CNT_OFFS) -+#define PXLCSR_ASPM_CNT_L0S_ENT_SUPP (0x1 << PXLCSR_ASPM_CNT_OFFS) -+#define PXLCSR_ASPM_CNT_L1S_ENT_SUPP (0x2 << PXLCSR_ASPM_CNT_OFFS) -+#define PXLCSR_ASPM_CNT_L0S_L1S_ENT_SUPP (0x3 << PXLCSR_ASPM_CNT_OFFS) -+ -+#define PXLCSR_RCB_OFFS 3 /* Read Completion Boundary */ -+#define PXLCSR_RCB_MASK BIT3 -+#define PXLCSR_RCB_64B (0 << PXLCSR_RCB_OFFS) -+#define PXLCSR_RCB_128B (1 << PXLCSR_RCB_OFFS) -+ -+#define PXLCSR_LNK_DIS BIT4 /* Link Disable */ -+#define PXLCSR_RETRN_LNK BIT5 /* Retrain Link */ -+#define PXLCSR_CMN_CLK_CFG BIT6 /* Common Clock Configuration */ -+#define PXLCSR_EXTD_SNC BIT7 /* Extended Sync */ -+ -+#define PXLCSR_LNK_SPD_OFFS 16 /* Link Speed */ -+#define PXLCSR_LNK_SPD_MASK (0xf << PXLCSR_LNK_SPD_OFFS) -+ -+#define PXLCSR_NEG_LNK_WDTH_OFFS 20 /* Negotiated Link Width */ -+#define PXLCSR_NEG_LNK_WDTH_MASK (0x3f << PXLCSR_NEG_LNK_WDTH_OFFS) -+#define PXLCSR_NEG_LNK_WDTH_X1 (0x1 << PXLCSR_NEG_LNK_WDTH_OFFS) -+ -+#define PXLCSR_LNK_TRN BIT27 /* Link Training */ -+ -+#define PXLCSR_SLT_CLK_CFG_OFFS 28 /* Slot Clock Configuration */ -+#define PXLCSR_SLT_CLK_CFG_MASK BIT28 -+#define PXLCSR_SLT_CLK_CFG_INDPNT (0x0 << PXLCSR_SLT_CLK_CFG_OFFS) -+#define PXLCSR_SLT_CLK_CFG_REF (0x1 << PXLCSR_SLT_CLK_CFG_OFFS) -+ -+/* PCI Express Advanced Error Report Header Register */ -+/*PEX_ADV_ERR_RPRT_HDR_TRGT_REG (PXAERHTR)*/ -+ -+/* PCI Express Uncorrectable Error Status Register*/ -+/*PEX_UNCORRECT_ERR_STAT_REG (PXUESR)*/ -+ -+/* PCI Express Uncorrectable Error Mask Register */ -+/*PEX_UNCORRECT_ERR_MASK_REG (PXUEMR)*/ -+ -+/* PCI Express Uncorrectable Error Severity Register */ -+/*PEX_UNCORRECT_ERR_SERVITY_REG (PXUESR)*/ -+ -+/* PCI Express Correctable Error Status Register */ -+/*PEX_CORRECT_ERR_STAT_REG (PXCESR)*/ -+ -+/* PCI Express Correctable Error Mask Register */ -+/*PEX_CORRECT_ERR_MASK_REG (PXCEMR)*/ -+ -+/* PCI Express Advanced Error Capability and Control Register*/ -+/*PEX_ADV_ERR_CAPABILITY_CTRL_REG (PXAECCR)*/ -+ -+/* PCI Express Header Log First DWORD Register*/ -+/*PEX_HDR_LOG_FIRST_DWORD_REG (PXHLFDR)*/ -+ -+/* PCI Express Header Log Second DWORD Register*/ -+/*PEX_HDR_LOG_SECOND_DWORD_REG (PXHLSDR)*/ -+ -+/* PCI Express Header Log Third DWORD Register*/ -+/*PEX_HDR_LOG_THIRD_DWORD_REG (PXHLTDR)*/ -+ -+/* PCI Express Header Log Fourth DWORD Register*/ -+/*PEX_HDR_LOG_FOURTH_DWORD_REG (PXHLFDR)*/ -+ -+#ifdef __cplusplus -+} -+#endif /* __cplusplus */ -+ -+#endif /* #ifndef __INCPEXREGSH */ -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,313 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "mvPex.h" -+ -+//#define MV_DEBUG -+/* defines */ -+#ifdef MV_DEBUG -+ #define DB(x) x -+#else -+ #define DB(x) -+#endif -+ -+/* locals */ -+typedef struct -+{ -+ MV_U32 data; -+ MV_U32 mask; -+}PEX_HEADER_DATA; -+ -+/* local function forwad decleration */ -+MV_U32 mvPexHwConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, -+ MV_U32 regOff); -+MV_STATUS mvPexHwConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data); -+void resetPexConfig(MV_U32 pexIf, MV_U32 bus, MV_U32 dev); -+ -+ -+PEX_HEADER_DATA configHdr[16] = -+{ -+{0x888811ab, 0x00000000}, /*[device ID, vendor ID] */ -+{0x00100007, 0x0000ffff}, /*[status register, command register] */ -+{0x0604000e, 0x00000000}, /*[programming interface, sub class code, class code, revision ID] */ -+{0x00010008, 0x00000000}, /*[BIST, header type, latency time, cache line] */ -+{0x00000000, 0x00000000}, /*[base address 0] */ -+{0x00000000, 0x00000000}, /*[base address 1] */ -+{0x00000000, 0x00ffffff}, /*[secondary latency timersubordinate bus number, secondary bus number, primary bus number] */ -+{0x0000f101, 0x00000000}, /*[secondary status ,IO limit, IO base] */ -+{0x9ff0a000, 0x00000000}, /*[memory limit, memory base] */ -+{0x0001fff1, 0x00000000}, /*[prefetch memory limit, prefetch memory base] */ -+{0xffffffff, 0x00000000}, /*[prefetch memory base upper] */ -+{0x00000000, 0x00000000}, /*[prefetch memory limit upper] */ -+{0xeffff000, 0x00000000}, /*[IO limit upper 16 bits, IO base upper 16 bits] */ -+{0x00000000, 0x00000000}, /*[reserved, capability pointer] */ -+{0x00000000, 0x00000000}, /*[expansion ROM base address] */ -+{0x00000000, 0x000000FF}, /*[bridge control, interrupt pin, interrupt line] */ -+}; -+ -+ -+#define HEADER_WRITE(data, offset) configHdr[offset/4].data = ((configHdr[offset/4].data & ~configHdr[offset/4].mask) | \ -+ (data & configHdr[offset/4].mask)) -+#define HEADER_READ(offset) configHdr[offset/4].data -+ -+/******************************************************************************* -+* mvVrtBrgPexInit - Initialize PEX interfaces -+* -+* DESCRIPTION: -+* -+* This function is responsible of intialization of the Pex Interface , It -+* configure the Pex Bars and Windows in the following manner: -+* -+* Assumptions : -+* Bar0 is always internal registers bar -+* Bar1 is always the DRAM bar -+* Bar2 is always the Device bar -+* -+* 1) Sets the Internal registers bar base by obtaining the base from -+* the CPU Interface -+* 2) Sets the DRAM bar base and size by getting the base and size from -+* the CPU Interface when the size is the sum of all enabled DRAM -+* chip selects and the base is the base of CS0 . -+* 3) Sets the Device bar base and size by getting these values from the -+* CPU Interface when the base is the base of the lowest base of the -+* Device chip selects, and the -+* -+* -+* INPUT: -+* -+* pexIf - PEX interface number. -+* -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK if function success otherwise MV_ERROR or MV_BAD_PARAM -+* -+*******************************************************************************/ -+MV_STATUS mvPexVrtBrgInit(MV_U32 pexIf) -+{ -+ /* reset PEX tree to recover previous U-boot/Boot configurations */ -+ MV_U32 localBus = mvPexLocalBusNumGet(pexIf); -+ -+ -+ resetPexConfig(pexIf, localBus, 1); -+ return MV_OK; -+} -+ -+ -+MV_U32 mvPexVrtBrgConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, -+ MV_U32 regOff) -+{ -+ -+ MV_U32 localBus = mvPexLocalBusNumGet(pexIf); -+ MV_U32 localDev = mvPexLocalDevNumGet(pexIf); -+ MV_U32 val; -+ if(bus == localBus) -+ { -+ if(dev > 1) -+ { -+/* on the local device allow only device #0 & #1 */ -+ return 0xffffffff; -+ } -+ else -+ if (dev == localDev) -+ { -+ /* read the memory controller registers */ -+ return mvPexHwConfigRead (pexIf, bus, dev, func, regOff); -+ } -+ else -+ { -+ /* access the virtual brg header */ -+ return HEADER_READ(regOff); -+ } -+ } -+ else -+ if(bus == (localBus + 1)) -+ { -+ /* access the device behind the virtual bridge */ -+ if((dev == localDev) || (dev > 1)) -+ { -+ return 0xffffffff; -+ } -+ else -+ { -+ /* access the device behind the virtual bridge, in this case -+ * change the bus number to the local bus number in order to -+ * generate type 0 config cycle -+ */ -+ mvPexLocalBusNumSet(pexIf, bus); -+ mvPexLocalDevNumSet(pexIf, 1); -+ val = mvPexHwConfigRead (pexIf, bus, 0, func, regOff); -+ mvPexLocalBusNumSet(pexIf, localBus); -+ mvPexLocalDevNumSet(pexIf, localDev); -+ return val; -+ } -+ } -+ /* for all other devices use the HW function to get the -+ * requested registers -+ */ -+ mvPexLocalDevNumSet(pexIf, 1); -+ val = mvPexHwConfigRead (pexIf, bus, dev, func, regOff); -+ mvPexLocalDevNumSet(pexIf, localDev); -+ return val; -+} -+ -+ -+MV_STATUS mvPexVrtBrgConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data) -+{ -+ MV_U32 localBus = mvPexLocalBusNumGet(pexIf); -+ MV_U32 localDev = mvPexLocalDevNumGet(pexIf); -+ MV_STATUS status; -+ -+ if(bus == localBus) -+ { -+ if(dev > 1) -+ { -+ /* on the local device allow only device #0 & #1 */ -+ return MV_ERROR; -+ } -+ else -+ if (dev == localDev) -+ { -+ /* read the memory controller registers */ -+ return mvPexHwConfigWrite (pexIf, bus, dev, func, regOff, data); -+ } -+ else -+ { -+ /* access the virtual brg header */ -+ HEADER_WRITE(data, regOff); -+ return MV_OK; -+ } -+ } -+ else -+ if(bus == (localBus + 1)) -+ { -+ /* access the device behind the virtual bridge */ -+ if((dev == localDev) || (dev > 1)) -+ { -+ return MV_ERROR; -+ } -+ else -+ { -+ /* access the device behind the virtual bridge, in this case -+ * change the bus number to the local bus number in order to -+ * generate type 0 config cycle -+ */ -+ //return mvPexHwConfigWrite (pexIf, localBus, dev, func, regOff, data); -+ mvPexLocalBusNumSet(pexIf, bus); -+ mvPexLocalDevNumSet(pexIf, 1); -+ status = mvPexHwConfigWrite (pexIf, bus, 0, func, regOff, data); -+ mvPexLocalBusNumSet(pexIf, localBus); -+ mvPexLocalDevNumSet(pexIf, localDev); -+ return status; -+ -+ } -+ } -+ /* for all other devices use the HW function to get the -+ * requested registers -+ */ -+ mvPexLocalDevNumSet(pexIf, 1); -+ status = mvPexHwConfigWrite (pexIf, bus, dev, func, regOff, data); -+ mvPexLocalDevNumSet(pexIf, localDev); -+ return status; -+} -+ -+ -+ -+ -+void resetPexConfig(MV_U32 pexIf, MV_U32 bus, MV_U32 dev) -+{ -+ MV_U32 tData; -+ MV_U32 i; -+ -+ /* restore the PEX configuration to initialization state */ -+ /* in case PEX P2P call recursive and reset config */ -+ tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x0); -+ if(tData != 0xffffffff) -+ { -+ /* agent had been found - check whether P2P */ -+ tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x8); -+ if((tData & 0xffff0000) == 0x06040000) -+ {/* P2P */ -+ /* get the sec bus and the subordinate */ -+ MV_U32 secBus; -+ tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x18); -+ secBus = ((tData >> 8) & 0xff); -+ /* now scan on sec bus */ -+ for(i = 0;i < 0xff;i++) -+ { -+ resetPexConfig(pexIf, secBus, i); -+ } -+ /* now reset this device */ -+ DB(mvOsPrintf("Reset bus %d dev %d\n", bus, dev)); -+ mvPexHwConfigWrite(pexIf, bus, dev, 0x0, 0x18, 0x0); -+ DB(mvOsPrintf("Reset bus %d dev %d\n", bus, dev)); -+ } -+ } -+} -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,82 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCVRTBRGPEXH -+#define __INCVRTBRGPEXH -+ -+ -+/* Global Functions prototypes */ -+/* mvPexInit - Initialize PEX interfaces*/ -+MV_STATUS mvPexVrtBrgInit(MV_U32 pexIf); -+ -+/* mvPexConfigRead - Read from configuration space */ -+MV_U32 mvPexVrtBrgConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func,MV_U32 regOff); -+ -+/* mvPexConfigWrite - Write to configuration space */ -+MV_STATUS mvPexVrtBrgConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, -+ MV_U32 func, MV_U32 regOff, MV_U32 data); -+ -+ -+#endif /* #ifndef __INCPEXH */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvCompVer.txt linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvCompVer.txt ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvCompVer.txt 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvCompVer.txt 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,4 @@ -+Global HAL Version: FEROCEON_HAL_3_1_7 -+Unit HAL Version: 3.1.3 -+Description: This component includes an implementation of the unit HAL drivers -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,1522 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#include "mvOs.h" -+#include "sflash/mvSFlash.h" -+#include "sflash/mvSFlashSpec.h" -+#include "spi/mvSpi.h" -+#include "spi/mvSpiCmnd.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+ -+/*#define MV_DEBUG*/ -+#ifdef MV_DEBUG -+#define DB(x) x -+#else -+#define DB(x) -+#endif -+ -+/* Globals */ -+static MV_SFLASH_DEVICE_PARAMS sflash[] = { -+ /* ST M25P32 SPI flash, 4MB, 64 sectors of 64K each */ -+ { -+ MV_M25P_WREN_CMND_OPCD, -+ MV_M25P_WRDI_CMND_OPCD, -+ MV_M25P_RDID_CMND_OPCD, -+ MV_M25P_RDSR_CMND_OPCD, -+ MV_M25P_WRSR_CMND_OPCD, -+ MV_M25P_READ_CMND_OPCD, -+ MV_M25P_FAST_RD_CMND_OPCD, -+ MV_M25P_PP_CMND_OPCD, -+ MV_M25P_SE_CMND_OPCD, -+ MV_M25P_BE_CMND_OPCD, -+ MV_M25P_RES_CMND_OPCD, -+ MV_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */ -+ MV_M25P32_SECTOR_SIZE, -+ MV_M25P32_SECTOR_NUMBER, -+ MV_M25P_PAGE_SIZE, -+ "ST M25P32", -+ MV_M25PXXX_ST_MANF_ID, -+ MV_M25P32_DEVICE_ID, -+ MV_M25P32_MAX_SPI_FREQ, -+ MV_M25P32_MAX_FAST_SPI_FREQ, -+ MV_M25P32_FAST_READ_DUMMY_BYTES -+ }, -+ /* ST M25P64 SPI flash, 8MB, 128 sectors of 64K each */ -+ { -+ MV_M25P_WREN_CMND_OPCD, -+ MV_M25P_WRDI_CMND_OPCD, -+ MV_M25P_RDID_CMND_OPCD, -+ MV_M25P_RDSR_CMND_OPCD, -+ MV_M25P_WRSR_CMND_OPCD, -+ MV_M25P_READ_CMND_OPCD, -+ MV_M25P_FAST_RD_CMND_OPCD, -+ MV_M25P_PP_CMND_OPCD, -+ MV_M25P_SE_CMND_OPCD, -+ MV_M25P_BE_CMND_OPCD, -+ MV_M25P_RES_CMND_OPCD, -+ MV_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */ -+ MV_M25P64_SECTOR_SIZE, -+ MV_M25P64_SECTOR_NUMBER, -+ MV_M25P_PAGE_SIZE, -+ "ST M25P64", -+ MV_M25PXXX_ST_MANF_ID, -+ MV_M25P64_DEVICE_ID, -+ MV_M25P64_MAX_SPI_FREQ, -+ MV_M25P64_MAX_FAST_SPI_FREQ, -+ MV_M25P64_FAST_READ_DUMMY_BYTES -+ }, -+ /* ST M25P128 SPI flash, 16MB, 64 sectors of 256K each */ -+ { -+ MV_M25P_WREN_CMND_OPCD, -+ MV_M25P_WRDI_CMND_OPCD, -+ MV_M25P_RDID_CMND_OPCD, -+ MV_M25P_RDSR_CMND_OPCD, -+ MV_M25P_WRSR_CMND_OPCD, -+ MV_M25P_READ_CMND_OPCD, -+ MV_M25P_FAST_RD_CMND_OPCD, -+ MV_M25P_PP_CMND_OPCD, -+ MV_M25P_SE_CMND_OPCD, -+ MV_M25P_BE_CMND_OPCD, -+ MV_M25P_RES_CMND_OPCD, -+ MV_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */ -+ MV_M25P128_SECTOR_SIZE, -+ MV_M25P128_SECTOR_NUMBER, -+ MV_M25P_PAGE_SIZE, -+ "ST M25P128", -+ MV_M25PXXX_ST_MANF_ID, -+ MV_M25P128_DEVICE_ID, -+ MV_M25P128_MAX_SPI_FREQ, -+ MV_M25P128_MAX_FAST_SPI_FREQ, -+ MV_M25P128_FAST_READ_DUMMY_BYTES -+ }, -+ /* Macronix MXIC MX25L6405 SPI flash, 8MB, 128 sectors of 64K each */ -+ { -+ MV_MX25L_WREN_CMND_OPCD, -+ MV_MX25L_WRDI_CMND_OPCD, -+ MV_MX25L_RDID_CMND_OPCD, -+ MV_MX25L_RDSR_CMND_OPCD, -+ MV_MX25L_WRSR_CMND_OPCD, -+ MV_MX25L_READ_CMND_OPCD, -+ MV_MX25L_FAST_RD_CMND_OPCD, -+ MV_MX25L_PP_CMND_OPCD, -+ MV_MX25L_SE_CMND_OPCD, -+ MV_MX25L_BE_CMND_OPCD, -+ MV_MX25L_RES_CMND_OPCD, -+ MV_MX25L_DP_CMND_OPCD, -+ MV_MX25L6405_SECTOR_SIZE, -+ MV_MX25L6405_SECTOR_NUMBER, -+ MV_MXIC_PAGE_SIZE, -+ "MXIC MX25L6405", -+ MV_MXIC_MANF_ID, -+ MV_MX25L6405_DEVICE_ID, -+ MV_MX25L6405_MAX_SPI_FREQ, -+ MV_MX25L6405_MAX_FAST_SPI_FREQ, -+ MV_MX25L6405_FAST_READ_DUMMY_BYTES -+ }, -+ /* SPANSION S25FL128P SPI flash, 16MB, 64 sectors of 256K each */ -+ { -+ MV_S25FL_WREN_CMND_OPCD, -+ MV_S25FL_WRDI_CMND_OPCD, -+ MV_S25FL_RDID_CMND_OPCD, -+ MV_S25FL_RDSR_CMND_OPCD, -+ MV_S25FL_WRSR_CMND_OPCD, -+ MV_S25FL_READ_CMND_OPCD, -+ MV_S25FL_FAST_RD_CMND_OPCD, -+ MV_S25FL_PP_CMND_OPCD, -+ MV_S25FL_SE_CMND_OPCD, -+ MV_S25FL_BE_CMND_OPCD, -+ MV_S25FL_RES_CMND_OPCD, -+ MV_S25FL_DP_CMND_OPCD, -+ MV_S25FL128_SECTOR_SIZE, -+ MV_S25FL128_SECTOR_NUMBER, -+ MV_S25FL_PAGE_SIZE, -+ "SPANSION S25FL128", -+ MV_SPANSION_MANF_ID, -+ MV_S25FL128_DEVICE_ID, -+ MV_S25FL128_MAX_SPI_FREQ, -+ MV_M25P128_MAX_FAST_SPI_FREQ, -+ MV_M25P128_FAST_READ_DUMMY_BYTES -+ } -+}; -+ -+/* Static Functions */ -+static MV_STATUS mvWriteEnable (MV_SFLASH_INFO * pFlinfo); -+static MV_STATUS mvStatusRegGet (MV_SFLASH_INFO * pFlinfo, MV_U8 * pStatReg); -+static MV_STATUS mvStatusRegSet (MV_SFLASH_INFO * pFlinfo, MV_U8 sr); -+static MV_STATUS mvWaitOnWipClear(MV_SFLASH_INFO * pFlinfo); -+static MV_STATUS mvSFlashPageWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, \ -+ MV_U8* pPageBuff, MV_U32 buffSize); -+static MV_STATUS mvSFlashWithDefaultsIdGet (MV_SFLASH_INFO * pFlinfo, \ -+ MV_U8* manId, MV_U16* devId); -+ -+/******************************************************************************* -+* mvWriteEnable - serialize the write enable sequence -+* -+* DESCRIPTION: -+* transmit the sequence for write enable -+* -+********************************************************************************/ -+static MV_STATUS mvWriteEnable(MV_SFLASH_INFO * pFlinfo) -+{ -+ MV_U8 cmd[MV_SFLASH_WREN_CMND_LENGTH]; -+ -+ -+ cmd[0] = sflash[pFlinfo->index].opcdWREN; -+ -+ return mvSpiWriteThenRead(cmd, MV_SFLASH_WREN_CMND_LENGTH, NULL, 0, 0); -+} -+ -+/******************************************************************************* -+* mvStatusRegGet - Retrieve the value of the status register -+* -+* DESCRIPTION: -+* perform the RDSR sequence to get the 8bit status register -+* -+********************************************************************************/ -+static MV_STATUS mvStatusRegGet(MV_SFLASH_INFO * pFlinfo, MV_U8 * pStatReg) -+{ -+ MV_STATUS ret; -+ MV_U8 cmd[MV_SFLASH_RDSR_CMND_LENGTH]; -+ MV_U8 sr[MV_SFLASH_RDSR_REPLY_LENGTH]; -+ -+ -+ -+ -+ cmd[0] = sflash[pFlinfo->index].opcdRDSR; -+ -+ if ((ret = mvSpiWriteThenRead(cmd, MV_SFLASH_RDSR_CMND_LENGTH, sr, -+ MV_SFLASH_RDSR_REPLY_LENGTH,0)) != MV_OK) -+ return ret; -+ -+ *pStatReg = sr[0]; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvWaitOnWipClear - Block waiting for the WIP (write in progress) to be cleared -+* -+* DESCRIPTION: -+* Block waiting for the WIP (write in progress) to be cleared -+* -+********************************************************************************/ -+static MV_STATUS mvWaitOnWipClear(MV_SFLASH_INFO * pFlinfo) -+{ -+ MV_STATUS ret; -+ MV_U32 i; -+ MV_U8 stat; -+ -+ for (i=0; iindex].opcdWRSR; -+ cmd[1] = sr; -+ -+ if ((ret = mvSpiWriteThenRead(cmd, MV_SFLASH_WRSR_CMND_LENGTH, NULL, 0, 0)) != MV_OK) -+ return ret; -+ -+ if ((ret = mvWaitOnWipClear(pFlinfo)) != MV_OK) -+ return ret; -+ -+ mvOsDelay(1); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSFlashPageWr - Write up to 256 Bytes in the same page -+* -+* DESCRIPTION: -+* Write a buffer up to the page size in length provided that the whole address -+* range is within the same page (alligned to page bounderies) -+* -+*******************************************************************************/ -+static MV_STATUS mvSFlashPageWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, -+ MV_U8* pPageBuff, MV_U32 buffSize) -+{ -+ MV_STATUS ret; -+ MV_U8 cmd[MV_SFLASH_PP_CMND_LENGTH]; -+ -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invalid parameter device index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* check that we do not cross the page bounderies */ -+ if (((offset & (sflash[pFlinfo->index].pageSize - 1)) + buffSize) > -+ sflash[pFlinfo->index].pageSize) -+ { -+ DB(mvOsPrintf("%s WARNING: Page allignment problem!\n", __FUNCTION__);) -+ return MV_OUT_OF_RANGE; -+ } -+ -+ /* Issue the Write enable command prior the page program command */ -+ if ((ret = mvWriteEnable(pFlinfo)) != MV_OK) -+ return ret; -+ -+ cmd[0] = sflash[pFlinfo->index].opcdPP; -+ cmd[1] = ((offset >> 16) & 0xFF); -+ cmd[2] = ((offset >> 8) & 0xFF); -+ cmd[3] = (offset & 0xFF); -+ -+ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_PP_CMND_LENGTH, pPageBuff, buffSize)) != MV_OK) -+ return ret; -+ -+ if ((ret = mvWaitOnWipClear(pFlinfo)) != MV_OK) -+ return ret; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSFlashWithDefaultsIdGet - Try to read the manufacturer and Device IDs from -+* the device using the default RDID opcode and the default WREN opcode. -+* -+* DESCRIPTION: -+* This is used to detect a generic device that uses the default opcodes -+* for the WREN and RDID. -+* -+********************************************************************************/ -+static MV_STATUS mvSFlashWithDefaultsIdGet (MV_SFLASH_INFO * pFlinfo, MV_U8* manId, MV_U16* devId) -+{ -+ MV_STATUS ret; -+ MV_U8 cmdRDID[MV_SFLASH_RDID_CMND_LENGTH]; -+ MV_U8 id[MV_SFLASH_RDID_REPLY_LENGTH]; -+ -+ -+ -+ /* Use the default RDID opcode to read the IDs */ -+ cmdRDID[0] = MV_SFLASH_DEFAULT_RDID_OPCD; /* unknown model try default */ -+ if ((ret = mvSpiWriteThenRead(cmdRDID, MV_SFLASH_RDID_CMND_LENGTH, id, MV_SFLASH_RDID_REPLY_LENGTH, 0)) != MV_OK) -+ return ret; -+ -+ *manId = id[0]; -+ *devId = 0; -+ *devId |= (id[1] << 8); -+ *devId |= id[2]; -+ -+ return MV_OK; -+} -+ -+/* -+##################################################################################### -+##################################################################################### -+*/ -+ -+/******************************************************************************* -+* mvSFlashInit - Initialize the serial flash device -+* -+* DESCRIPTION: -+* Perform the neccessary initialization and configuration -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* pFlinfo->baseAddr: base address in fast mode. -+* pFlinfo->index: Index of the flash in the sflash tabel. If the SPI -+* flash device does not support read Id command with -+* the standard opcode, then the user should supply this -+* as an input to skip the autodetection process!!!! -+* -+* OUTPUT: -+* pFlinfo: pointer to the Flash information structure after detection -+* pFlinfo->manufacturerId: Manufacturer ID -+* pFlinfo->deviceId: Device ID -+* pFlinfo->sectorSize: size of the sector (all sectors are the same). -+* pFlinfo->sectorNumber: number of sectors. -+* pFlinfo->pageSize: size of the page. -+* pFlinfo->index: Index of the detected flash in the sflash tabel -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashInit (MV_SFLASH_INFO * pFlinfo) -+{ -+ MV_STATUS ret; -+ MV_U8 manf; -+ MV_U16 dev; -+ MV_U32 indx; -+ MV_BOOL detectFlag = MV_FALSE; -+ -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Initialize the SPI interface with low frequency to make sure that the read ID succeeds */ -+ if ((ret = mvSpiInit(MV_SFLASH_BASIC_SPI_FREQ)) != MV_OK) -+ { -+ mvOsPrintf("%s ERROR: Failed to initialize the SPI interface!\n", __FUNCTION__); -+ return ret; -+ } -+ -+ /* First try to read the Manufacturer and Device IDs */ -+ if ((ret = mvSFlashIdGet(pFlinfo, &manf, &dev)) != MV_OK) -+ { -+ mvOsPrintf("%s ERROR: Failed to get the SFlash ID!\n", __FUNCTION__); -+ return ret; -+ } -+ -+ /* loop over the whole table and look for the appropriate SFLASH */ -+ for (indx=0; indxmanufacturerId = manf; -+ pFlinfo->deviceId = dev; -+ pFlinfo->index = indx; -+ detectFlag = MV_TRUE; -+ } -+ } -+ -+ if(!detectFlag) -+ { -+ mvOsPrintf("%s ERROR: Unknown SPI flash device!\n", __FUNCTION__); -+ return MV_FAIL; -+ } -+ -+ /* fill the info based on the model detected */ -+ pFlinfo->sectorSize = sflash[pFlinfo->index].sectorSize; -+ pFlinfo->sectorNumber = sflash[pFlinfo->index].sectorNumber; -+ pFlinfo->pageSize = sflash[pFlinfo->index].pageSize; -+ -+ /* Set the SPI frequency to the MAX allowed for the device for best performance */ -+ if ((ret = mvSpiBaudRateSet(sflash[pFlinfo->index].spiMaxFreq)) != MV_OK) -+ { -+ mvOsPrintf("%s ERROR: Failed to set the SPI frequency!\n", __FUNCTION__); -+ return ret; -+ } -+ -+ /* As default lock the SR */ -+ if ((ret = mvSFlashStatRegLock(pFlinfo, MV_TRUE)) != MV_OK) -+ return ret; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSFlashSectorErase - Erasse a single sector of the serial flash -+* -+* DESCRIPTION: -+* Issue the erase sector command and address -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* secNumber: sector Number to erase (0 -> (sectorNumber-1)) -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashSectorErase (MV_SFLASH_INFO * pFlinfo, MV_U32 secNumber) -+{ -+ MV_STATUS ret; -+ MV_U8 cmd[MV_SFLASH_SE_CMND_LENGTH]; -+ -+ MV_U32 secAddr = (secNumber * pFlinfo->sectorSize); -+#if 0 -+ MV_U32 i; -+ MV_U32 * pW = (MV_U32*) (secAddr + pFlinfo->baseAddr); -+ MV_U32 erasedWord = 0xFFFFFFFF; -+ MV_U32 wordsPerSector = (pFlinfo->sectorSize / sizeof(MV_U32)); -+ MV_BOOL eraseNeeded = MV_FALSE; -+#endif -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* check that the sector number is valid */ -+ if (secNumber >= pFlinfo->sectorNumber) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter sector number!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* we don't want to access SPI in direct mode from in-direct API, -+ becasue of timing issue between CS asserts. */ -+#if 0 -+ /* First compare to FF and check if erase is needed */ -+ for (i=0; iindex].opcdSE; -+ cmd[1] = ((secAddr >> 16) & 0xFF); -+ cmd[2] = ((secAddr >> 8) & 0xFF); -+ cmd[3] = (secAddr & 0xFF); -+ -+ /* Issue the Write enable command prior the sector erase command */ -+ if ((ret = mvWriteEnable(pFlinfo)) != MV_OK) -+ return ret; -+ -+ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_SE_CMND_LENGTH, NULL, 0)) != MV_OK) -+ return ret; -+ -+ if ((ret = mvWaitOnWipClear(pFlinfo)) != MV_OK) -+ return ret; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSFlashChipErase - Erasse the whole serial flash -+* -+* DESCRIPTION: -+* Issue the bulk (chip) erase command -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashChipErase (MV_SFLASH_INFO * pFlinfo) -+{ -+ MV_STATUS ret; -+ MV_U8 cmd[MV_SFLASH_BE_CMND_LENGTH]; -+ -+ -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ cmd[0] = sflash[pFlinfo->index].opcdBE; -+ -+ /* Issue the Write enable command prior the Bulk erase command */ -+ if ((ret = mvWriteEnable(pFlinfo)) != MV_OK) -+ return ret; -+ -+ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_BE_CMND_LENGTH, NULL, 0)) != MV_OK) -+ return ret; -+ -+ if ((ret = mvWaitOnChipEraseDone(pFlinfo)) != MV_OK) -+ return ret; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSFlashBlockRd - Read from the serial flash -+* -+* DESCRIPTION: -+* Issue the read command and address then perfom the needed read -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* offset: byte offset with the flash to start reading from -+* pReadBuff: pointer to the buffer to read the data in -+* buffSize: size of the buffer to read. -+* -+* OUTPUT: -+* pReadBuff: pointer to the buffer containing the read data -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, -+ MV_U8* pReadBuff, MV_U32 buffSize) -+{ -+ MV_U8 cmd[MV_SFLASH_READ_CMND_LENGTH]; -+ -+ -+ /* check for NULL pointer */ -+ if ((pFlinfo == NULL) || (pReadBuff == NULL)) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ cmd[0] = sflash[pFlinfo->index].opcdREAD; -+ cmd[1] = ((offset >> 16) & 0xFF); -+ cmd[2] = ((offset >> 8) & 0xFF); -+ cmd[3] = (offset & 0xFF); -+ -+ return mvSpiWriteThenRead(cmd, MV_SFLASH_READ_CMND_LENGTH, pReadBuff, buffSize, 0); -+} -+ -+/******************************************************************************* -+* mvSFlashFastBlockRd - Fast read from the serial flash -+* -+* DESCRIPTION: -+* Issue the fast read command and address then perfom the needed read -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* offset: byte offset with the flash to start reading from -+* pReadBuff: pointer to the buffer to read the data in -+* buffSize: size of the buffer to read. -+* -+* OUTPUT: -+* pReadBuff: pointer to the buffer containing the read data -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashFastBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, -+ MV_U8* pReadBuff, MV_U32 buffSize) -+{ -+ MV_U8 cmd[MV_SFLASH_READ_CMND_LENGTH]; -+ MV_STATUS ret; -+ -+ /* check for NULL pointer */ -+ if ((pFlinfo == NULL) || (pReadBuff == NULL)) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* Set the SPI frequency to the MAX allowed for fast-read operations */ -+ mvOsPrintf("Setting freq to %d.\n",sflash[pFlinfo->index].spiMaxFastFreq); -+ if ((ret = mvSpiBaudRateSet(sflash[pFlinfo->index].spiMaxFastFreq)) != MV_OK) -+ { -+ mvOsPrintf("%s ERROR: Failed to set the SPI fast frequency!\n", __FUNCTION__); -+ return ret; -+ } -+ -+ cmd[0] = sflash[pFlinfo->index].opcdFSTRD; -+ cmd[1] = ((offset >> 16) & 0xFF); -+ cmd[2] = ((offset >> 8) & 0xFF); -+ cmd[3] = (offset & 0xFF); -+ -+ -+ ret = mvSpiWriteThenRead(cmd, MV_SFLASH_READ_CMND_LENGTH, pReadBuff, buffSize, -+ sflash[pFlinfo->index].spiFastRdDummyBytes); -+ -+ /* Reset the SPI frequency to the MAX allowed for the device for best performance */ -+ if ((ret = mvSpiBaudRateSet(sflash[pFlinfo->index].spiMaxFreq)) != MV_OK) -+ { -+ mvOsPrintf("%s ERROR: Failed to set the SPI frequency!\n", __FUNCTION__); -+ return ret; -+ } -+ -+ return ret; -+} -+ -+ -+/******************************************************************************* -+* mvSFlashBlockWr - Write a buffer with any size -+* -+* DESCRIPTION: -+* write regardless of the page boundaries and size limit per Page -+* program command -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* offset: byte offset within the flash region -+* pWriteBuff: pointer to the buffer holding the data to program -+* buffSize: size of the buffer to write -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashBlockWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, -+ MV_U8* pWriteBuff, MV_U32 buffSize) -+{ -+ MV_STATUS ret; -+ MV_U32 data2write = buffSize; -+ MV_U32 preAllOffset = (offset & MV_SFLASH_PAGE_ALLIGN_MASK(MV_M25P_PAGE_SIZE)); -+ MV_U32 preAllSz = (preAllOffset ? (MV_M25P_PAGE_SIZE - preAllOffset) : 0); -+ MV_U32 writeOffset = offset; -+ -+ /* check for NULL pointer */ -+#ifndef CONFIG_MARVELL -+ if(NULL == pWriteBuff) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+#endif -+ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* check that the buffer size does not exceed the flash size */ -+ if ((offset + buffSize) > mvSFlashSizeGet(pFlinfo)) -+ { -+ DB(mvOsPrintf("%s WARNING: Write exceeds flash size!\n", __FUNCTION__);) -+ return MV_OUT_OF_RANGE; -+ } -+ -+ /* check if the total block size is less than the first chunk remainder */ -+ if (data2write < preAllSz) -+ preAllSz = data2write; -+ -+ /* check if programing does not start at a 64byte alligned offset */ -+ if (preAllSz) -+ { -+ if ((ret = mvSFlashPageWr(pFlinfo, writeOffset, pWriteBuff, preAllSz)) != MV_OK) -+ return ret; -+ -+ /* increment pointers and counters */ -+ writeOffset += preAllSz; -+ data2write -= preAllSz; -+ pWriteBuff += preAllSz; -+ } -+ -+ /* program the data that fits in complete page chunks */ -+ while (data2write >= sflash[pFlinfo->index].pageSize) -+ { -+ if ((ret = mvSFlashPageWr(pFlinfo, writeOffset, pWriteBuff, sflash[pFlinfo->index].pageSize)) != MV_OK) -+ return ret; -+ -+ /* increment pointers and counters */ -+ writeOffset += sflash[pFlinfo->index].pageSize; -+ data2write -= sflash[pFlinfo->index].pageSize; -+ pWriteBuff += sflash[pFlinfo->index].pageSize; -+ } -+ -+ /* program the last partial chunk */ -+ if (data2write) -+ { -+ if ((ret = mvSFlashPageWr(pFlinfo, writeOffset, pWriteBuff, data2write)) != MV_OK) -+ return ret; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSFlashIdGet - Get the manufacturer and device IDs. -+* -+* DESCRIPTION: -+* Get the Manufacturer and device IDs from the serial flash through -+* writing the RDID command then reading 3 bytes of data. In case that -+* this command was called for the first time in order to detect the -+* manufacturer and device IDs, then the default RDID opcode will be used -+* unless the device index is indicated by the user (in case the SPI flash -+* does not use the default RDID opcode). -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* pManId: pointer to the 8bit variable to hold the manufacturing ID -+* pDevId: pointer to the 16bit variable to hold the device ID -+* -+* OUTPUT: -+* pManId: pointer to the 8bit variable holding the manufacturing ID -+* pDevId: pointer to the 16bit variable holding the device ID -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashIdGet (MV_SFLASH_INFO * pFlinfo, MV_U8* pManId, MV_U16* pDevId) -+{ -+ MV_STATUS ret; -+ MV_U8 cmd[MV_SFLASH_RDID_CMND_LENGTH]; -+ MV_U8 id[MV_SFLASH_RDID_REPLY_LENGTH]; -+ -+ -+ -+ /* check for NULL pointer */ -+ if ((pFlinfo == NULL) || (pManId == NULL) || (pDevId == NULL)) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ return mvSFlashWithDefaultsIdGet(pFlinfo, pManId, pDevId); -+ else -+ cmd[0] = sflash[pFlinfo->index].opcdRDID; -+ -+ if ((ret = mvSpiWriteThenRead(cmd, MV_SFLASH_RDID_CMND_LENGTH, id, MV_SFLASH_RDID_REPLY_LENGTH, 0)) != MV_OK) -+ return ret; -+ -+ *pManId = id[0]; -+ *pDevId = 0; -+ *pDevId |= (id[1] << 8); -+ *pDevId |= id[2]; -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSFlashWpRegionSet - Set the Write-Protected region -+* -+* DESCRIPTION: -+* Set the Write-Protected region -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* wpRegion: which region will be protected -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashWpRegionSet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION wpRegion) -+{ -+ MV_U8 wpMask; -+ -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check if the chip is an ST flash; then WP supports only 3 bits */ -+ if (pFlinfo->manufacturerId == MV_M25PXXX_ST_MANF_ID) -+ { -+ switch (wpRegion) -+ { -+ case MV_WP_NONE: -+ wpMask = MV_M25P_STATUS_BP_NONE; -+ break; -+ -+ case MV_WP_UPR_1OF128: -+ DB(mvOsPrintf("%s WARNING: Invaild option for this flash chip!\n", __FUNCTION__);) -+ return MV_NOT_SUPPORTED; -+ -+ case MV_WP_UPR_1OF64: -+ wpMask = MV_M25P_STATUS_BP_1_OF_64; -+ break; -+ -+ case MV_WP_UPR_1OF32: -+ wpMask = MV_M25P_STATUS_BP_1_OF_32; -+ break; -+ -+ case MV_WP_UPR_1OF16: -+ wpMask = MV_M25P_STATUS_BP_1_OF_16; -+ break; -+ -+ case MV_WP_UPR_1OF8: -+ wpMask = MV_M25P_STATUS_BP_1_OF_8; -+ break; -+ -+ case MV_WP_UPR_1OF4: -+ wpMask = MV_M25P_STATUS_BP_1_OF_4; -+ break; -+ -+ case MV_WP_UPR_1OF2: -+ wpMask = MV_M25P_STATUS_BP_1_OF_2; -+ break; -+ -+ case MV_WP_ALL: -+ wpMask = MV_M25P_STATUS_BP_ALL; -+ break; -+ -+ default: -+ DB(mvOsPrintf("%s WARNING: Invaild parameter WP region!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ } -+ /* check if the manufacturer is MXIC then the WP is 4bits */ -+ else if (pFlinfo->manufacturerId == MV_MXIC_MANF_ID) -+ { -+ switch (wpRegion) -+ { -+ case MV_WP_NONE: -+ wpMask = MV_MX25L_STATUS_BP_NONE; -+ break; -+ -+ case MV_WP_UPR_1OF128: -+ wpMask = MV_MX25L_STATUS_BP_1_OF_128; -+ break; -+ -+ case MV_WP_UPR_1OF64: -+ wpMask = MV_MX25L_STATUS_BP_1_OF_64; -+ break; -+ -+ case MV_WP_UPR_1OF32: -+ wpMask = MV_MX25L_STATUS_BP_1_OF_32; -+ break; -+ -+ case MV_WP_UPR_1OF16: -+ wpMask = MV_MX25L_STATUS_BP_1_OF_16; -+ break; -+ -+ case MV_WP_UPR_1OF8: -+ wpMask = MV_MX25L_STATUS_BP_1_OF_8; -+ break; -+ -+ case MV_WP_UPR_1OF4: -+ wpMask = MV_MX25L_STATUS_BP_1_OF_4; -+ break; -+ -+ case MV_WP_UPR_1OF2: -+ wpMask = MV_MX25L_STATUS_BP_1_OF_2; -+ break; -+ -+ case MV_WP_ALL: -+ wpMask = MV_MX25L_STATUS_BP_ALL; -+ break; -+ -+ default: -+ DB(mvOsPrintf("%s WARNING: Invaild parameter WP region!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ } -+ /* check if the manufacturer is SPANSION then the WP is 4bits */ -+ else if (pFlinfo->manufacturerId == MV_SPANSION_MANF_ID) -+ { -+ switch (wpRegion) -+ { -+ case MV_WP_NONE: -+ wpMask = MV_S25FL_STATUS_BP_NONE; -+ break; -+ -+ case MV_WP_UPR_1OF128: -+ DB(mvOsPrintf("%s WARNING: Invaild option for this flash chip!\n", __FUNCTION__);) -+ return MV_NOT_SUPPORTED; -+ -+ case MV_WP_UPR_1OF64: -+ wpMask = MV_S25FL_STATUS_BP_1_OF_64; -+ break; -+ -+ case MV_WP_UPR_1OF32: -+ wpMask = MV_S25FL_STATUS_BP_1_OF_32; -+ break; -+ -+ case MV_WP_UPR_1OF16: -+ wpMask = MV_S25FL_STATUS_BP_1_OF_16; -+ break; -+ -+ case MV_WP_UPR_1OF8: -+ wpMask = MV_S25FL_STATUS_BP_1_OF_8; -+ break; -+ -+ case MV_WP_UPR_1OF4: -+ wpMask = MV_S25FL_STATUS_BP_1_OF_4; -+ break; -+ -+ case MV_WP_UPR_1OF2: -+ wpMask = MV_S25FL_STATUS_BP_1_OF_2; -+ break; -+ -+ case MV_WP_ALL: -+ wpMask = MV_S25FL_STATUS_BP_ALL; -+ break; -+ -+ -+ default: -+ DB(mvOsPrintf("%s WARNING: Invaild parameter WP region!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ } -+ else -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter Manufacturer ID!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* Verify that the SRWD bit is always set - register is s/w locked */ -+ wpMask |= MV_SFLASH_STATUS_REG_SRWD_MASK; -+ -+ return mvStatusRegSet(pFlinfo, wpMask); -+} -+ -+/******************************************************************************* -+* mvSFlashWpRegionGet - Get the Write-Protected region configured -+* -+* DESCRIPTION: -+* Get from the chip the Write-Protected region configured -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* pWpRegion: pointer to the variable to return the WP region in -+* -+* OUTPUT: -+* wpRegion: pointer to the variable holding the WP region configured -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashWpRegionGet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION * pWpRegion) -+{ -+ MV_STATUS ret; -+ MV_U8 reg; -+ -+ /* check for NULL pointer */ -+ if ((pFlinfo == NULL) || (pWpRegion == NULL)) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ if ((ret = mvStatusRegGet(pFlinfo, ®)) != MV_OK) -+ return ret; -+ -+ /* Check if the chip is an ST flash; then WP supports only 3 bits */ -+ if (pFlinfo->manufacturerId == MV_M25PXXX_ST_MANF_ID) -+ { -+ switch ((reg & MV_M25P_STATUS_REG_WP_MASK)) -+ { -+ case MV_M25P_STATUS_BP_NONE: -+ *pWpRegion = MV_WP_NONE; -+ break; -+ -+ case MV_M25P_STATUS_BP_1_OF_64: -+ *pWpRegion = MV_WP_UPR_1OF64; -+ break; -+ -+ case MV_M25P_STATUS_BP_1_OF_32: -+ *pWpRegion = MV_WP_UPR_1OF32; -+ break; -+ -+ case MV_M25P_STATUS_BP_1_OF_16: -+ *pWpRegion = MV_WP_UPR_1OF16; -+ break; -+ -+ case MV_M25P_STATUS_BP_1_OF_8: -+ *pWpRegion = MV_WP_UPR_1OF8; -+ break; -+ -+ case MV_M25P_STATUS_BP_1_OF_4: -+ *pWpRegion = MV_WP_UPR_1OF4; -+ break; -+ -+ case MV_M25P_STATUS_BP_1_OF_2: -+ *pWpRegion = MV_WP_UPR_1OF2; -+ break; -+ -+ case MV_M25P_STATUS_BP_ALL: -+ *pWpRegion = MV_WP_ALL; -+ break; -+ -+ default: -+ DB(mvOsPrintf("%s WARNING: Unidentified WP region in h/w!\n", __FUNCTION__);) -+ return MV_BAD_VALUE; -+ } -+ } -+ /* check if the manufacturer is MXIC then the WP is 4bits */ -+ else if (pFlinfo->manufacturerId == MV_MXIC_MANF_ID) -+ { -+ switch ((reg & MV_MX25L_STATUS_REG_WP_MASK)) -+ { -+ case MV_MX25L_STATUS_BP_NONE: -+ *pWpRegion = MV_WP_NONE; -+ break; -+ -+ case MV_MX25L_STATUS_BP_1_OF_128: -+ *pWpRegion = MV_WP_UPR_1OF128; -+ break; -+ -+ case MV_MX25L_STATUS_BP_1_OF_64: -+ *pWpRegion = MV_WP_UPR_1OF64; -+ break; -+ -+ case MV_MX25L_STATUS_BP_1_OF_32: -+ *pWpRegion = MV_WP_UPR_1OF32; -+ break; -+ -+ case MV_MX25L_STATUS_BP_1_OF_16: -+ *pWpRegion = MV_WP_UPR_1OF16; -+ break; -+ -+ case MV_MX25L_STATUS_BP_1_OF_8: -+ *pWpRegion = MV_WP_UPR_1OF8; -+ break; -+ -+ case MV_MX25L_STATUS_BP_1_OF_4: -+ *pWpRegion = MV_WP_UPR_1OF4; -+ break; -+ -+ case MV_MX25L_STATUS_BP_1_OF_2: -+ *pWpRegion = MV_WP_UPR_1OF2; -+ break; -+ -+ case MV_MX25L_STATUS_BP_ALL: -+ *pWpRegion = MV_WP_ALL; -+ break; -+ -+ default: -+ DB(mvOsPrintf("%s WARNING: Unidentified WP region in h/w!\n", __FUNCTION__);) -+ return MV_BAD_VALUE; -+ } -+ } -+ /* Check if the chip is an SPANSION flash; then WP supports only 3 bits */ -+ else if (pFlinfo->manufacturerId == MV_SPANSION_MANF_ID) -+ { -+ switch ((reg & MV_S25FL_STATUS_REG_WP_MASK)) -+ { -+ case MV_S25FL_STATUS_BP_NONE: -+ *pWpRegion = MV_WP_NONE; -+ break; -+ -+ case MV_S25FL_STATUS_BP_1_OF_64: -+ *pWpRegion = MV_WP_UPR_1OF64; -+ break; -+ -+ case MV_S25FL_STATUS_BP_1_OF_32: -+ *pWpRegion = MV_WP_UPR_1OF32; -+ break; -+ -+ case MV_S25FL_STATUS_BP_1_OF_16: -+ *pWpRegion = MV_WP_UPR_1OF16; -+ break; -+ -+ case MV_S25FL_STATUS_BP_1_OF_8: -+ *pWpRegion = MV_WP_UPR_1OF8; -+ break; -+ -+ case MV_S25FL_STATUS_BP_1_OF_4: -+ *pWpRegion = MV_WP_UPR_1OF4; -+ break; -+ -+ case MV_S25FL_STATUS_BP_1_OF_2: -+ *pWpRegion = MV_WP_UPR_1OF2; -+ break; -+ -+ case MV_S25FL_STATUS_BP_ALL: -+ *pWpRegion = MV_WP_ALL; -+ break; -+ -+ default: -+ DB(mvOsPrintf("%s WARNING: Unidentified WP region in h/w!\n", __FUNCTION__);) -+ return MV_BAD_VALUE; -+ } -+ } -+ else -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter Manufacturer ID!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSFlashStatRegLock - Lock the status register for writing - W/Vpp -+* pin should be low to take effect -+* -+* DESCRIPTION: -+* Lock the access to the Status Register for writing. This will -+* cause the flash to enter the hardware protection mode if the W/Vpp -+* is low. If the W/Vpp is hi, the chip will be in soft protection mode, but -+* the register will continue to be writable if WREN sequence was used. -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* srLock: enable/disable (MV_TRUE/MV_FALSE) status registor lock mechanism -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashStatRegLock (MV_SFLASH_INFO * pFlinfo, MV_BOOL srLock) -+{ -+ MV_STATUS ret; -+ MV_U8 reg; -+ -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ if ((ret = mvStatusRegGet(pFlinfo, ®)) != MV_OK) -+ return ret; -+ -+ if (srLock) -+ reg |= MV_SFLASH_STATUS_REG_SRWD_MASK; -+ else -+ reg &= ~MV_SFLASH_STATUS_REG_SRWD_MASK; -+ -+ return mvStatusRegSet(pFlinfo, reg); -+} -+ -+/******************************************************************************* -+* mvSFlashSizeGet - Get the size of the SPI flash -+* -+* DESCRIPTION: -+* based on the sector number and size of each sector calculate the total -+* size of the flash memory. -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Size of the flash in bytes. -+* -+* -+*******************************************************************************/ -+MV_U32 mvSFlashSizeGet (MV_SFLASH_INFO * pFlinfo) -+{ -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return 0; -+ } -+ -+ return (pFlinfo->sectorSize * pFlinfo->sectorNumber); -+} -+ -+/******************************************************************************* -+* mvSFlashPowerSaveEnter - Cause the falsh device to go into power save mode -+* -+* DESCRIPTION: -+* Enter a special power save mode. -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Size of the flash in bytes. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashPowerSaveEnter(MV_SFLASH_INFO * pFlinfo) -+{ -+ MV_STATUS ret; -+ MV_U8 cmd[MV_SFLASH_DP_CMND_LENGTH]; -+ -+ -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return 0; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* check that power save mode is supported in the specific device */ -+ if (sflash[pFlinfo->index].opcdPwrSave == MV_SFLASH_NO_SPECIFIC_OPCD) -+ { -+ DB(mvOsPrintf("%s WARNING: Power save not supported for this device!\n", __FUNCTION__);) -+ return MV_NOT_SUPPORTED; -+ } -+ -+ cmd[0] = sflash[pFlinfo->index].opcdPwrSave; -+ -+ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_DP_CMND_LENGTH, NULL, 0)) != MV_OK) -+ return ret; -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvSFlashPowerSaveExit - Cause the falsh device to exit the power save mode -+* -+* DESCRIPTION: -+* Exit the deep power save mode. -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Size of the flash in bytes. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSFlashPowerSaveExit (MV_SFLASH_INFO * pFlinfo) -+{ -+ MV_STATUS ret; -+ MV_U8 cmd[MV_SFLASH_RES_CMND_LENGTH]; -+ -+ -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return 0; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return MV_BAD_PARAM; -+ } -+ -+ /* check that power save mode is supported in the specific device */ -+ if (sflash[pFlinfo->index].opcdRES == MV_SFLASH_NO_SPECIFIC_OPCD) -+ { -+ DB(mvOsPrintf("%s WARNING: Read Electronic Signature not supported for this device!\n", __FUNCTION__);) -+ return MV_NOT_SUPPORTED; -+ } -+ -+ cmd[0] = sflash[pFlinfo->index].opcdRES; -+ -+ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_RES_CMND_LENGTH, NULL, 0)) != MV_OK) -+ return ret; -+ -+ /* add the delay needed for the device to wake up */ -+ mvOsDelay(MV_MXIC_DP_EXIT_DELAY); /* 30 ms */ -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvSFlashModelGet - Retreive the string with the device manufacturer and model -+* -+* DESCRIPTION: -+* Retreive the string with the device manufacturer and model -+* -+* INPUT: -+* pFlinfo: pointer to the Flash information structure -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* pointer to the string indicating the device manufacturer and model -+* -+* -+*******************************************************************************/ -+const MV_8 * mvSFlashModelGet (MV_SFLASH_INFO * pFlinfo) -+{ -+ static const MV_8 * unknModel = (const MV_8 *)"Unknown"; -+ -+ /* check for NULL pointer */ -+ if (pFlinfo == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return 0; -+ } -+ -+ /* Protection - check if the model was detected */ -+ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) -+ { -+ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) -+ return unknModel; -+ } -+ -+ return sflash[pFlinfo->index].deviceModel; -+} -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,166 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvSFlashH -+#define __INCmvSFlashH -+ -+#include "mvTypes.h" -+ -+/* MCAROS */ -+#define MV_SFLASH_PAGE_ALLIGN_MASK(pgSz) (pgSz-1) -+#define MV_ARRAY_SIZE(a) ((sizeof(a)) / (sizeof(a[0]))) -+ -+/* Constants */ -+#define MV_INVALID_DEVICE_NUMBER 0xFFFFFFFF -+/* 10 MHz is the minimum possible SPI frequency when tclk is set 200MHz*/ -+#define MV_SFLASH_BASIC_SPI_FREQ 10000000 -+/* enumerations */ -+typedef enum -+{ -+ MV_WP_NONE, /* Unprotect the whole chip */ -+ MV_WP_UPR_1OF128, /* Write protect the upper 1/128 part */ -+ MV_WP_UPR_1OF64, /* Write protect the upper 1/64 part */ -+ MV_WP_UPR_1OF32, /* Write protect the upper 1/32 part */ -+ MV_WP_UPR_1OF16, /* Write protect the upper 1/16 part */ -+ MV_WP_UPR_1OF8, /* Write protect the upper 1/8 part */ -+ MV_WP_UPR_1OF4, /* Write protect the upper 1/4 part */ -+ MV_WP_UPR_1OF2, /* Write protect the upper 1/2 part */ -+ MV_WP_ALL /* Write protect the whole chip */ -+} MV_SFLASH_WP_REGION; -+ -+/* Type Definitions */ -+typedef struct -+{ -+ MV_U8 opcdWREN; /* Write enable opcode */ -+ MV_U8 opcdWRDI; /* Write disable opcode */ -+ MV_U8 opcdRDID; /* Read ID opcode */ -+ MV_U8 opcdRDSR; /* Read Status Register opcode */ -+ MV_U8 opcdWRSR; /* Write Status register opcode */ -+ MV_U8 opcdREAD; /* Read opcode */ -+ MV_U8 opcdFSTRD; /* Fast Read opcode */ -+ MV_U8 opcdPP; /* Page program opcode */ -+ MV_U8 opcdSE; /* Sector erase opcode */ -+ MV_U8 opcdBE; /* Bulk erase opcode */ -+ MV_U8 opcdRES; /* Read electronic signature */ -+ MV_U8 opcdPwrSave; /* Go into power save mode */ -+ MV_U32 sectorSize; /* Size of each sector */ -+ MV_U32 sectorNumber; /* Number of sectors */ -+ MV_U32 pageSize; /* size of each page */ -+ const char * deviceModel; /* string with the device model */ -+ MV_U32 manufacturerId; /* The manufacturer ID */ -+ MV_U32 deviceId; /* Device ID */ -+ MV_U32 spiMaxFreq; /* The MAX frequency that can be used with the device */ -+ MV_U32 spiMaxFastFreq; /* The MAX frequency that can be used with the device for fast reads */ -+ MV_U32 spiFastRdDummyBytes; /* Number of dumy bytes to read before real data when working in fast read mode. */ -+} MV_SFLASH_DEVICE_PARAMS; -+ -+typedef struct -+{ -+ MV_U32 baseAddr; /* Flash Base Address used in fast mode */ -+ MV_U8 manufacturerId; /* Manufacturer ID */ -+ MV_U16 deviceId; /* Device ID */ -+ MV_U32 sectorSize; /* Size of each sector - all the same */ -+ MV_U32 sectorNumber; /* Number of sectors */ -+ MV_U32 pageSize; /* Page size - affect allignment */ -+ MV_U32 index; /* index of the device in the sflash table (internal parameter) */ -+} MV_SFLASH_INFO; -+ -+/* Function Prototypes */ -+/* Init */ -+MV_STATUS mvSFlashInit (MV_SFLASH_INFO * pFlinfo); -+ -+/* erase */ -+MV_STATUS mvSFlashSectorErase (MV_SFLASH_INFO * pFlinfo, MV_U32 secNumber); -+MV_STATUS mvSFlashChipErase (MV_SFLASH_INFO * pFlinfo); -+ -+/* Read */ -+MV_STATUS mvSFlashBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, -+ MV_U8* pReadBuff, MV_U32 buffSize); -+MV_STATUS mvSFlashFastBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, -+ MV_U8* pReadBuff, MV_U32 buffSize); -+ -+/* write regardless of the page boundaries and size limit per Page program command */ -+MV_STATUS mvSFlashBlockWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, -+ MV_U8* pWriteBuff, MV_U32 buffSize); -+/* Get IDs */ -+MV_STATUS mvSFlashIdGet (MV_SFLASH_INFO * pFlinfo, MV_U8* pManId, MV_U16* pDevId); -+ -+/* Set and Get the Write Protection region - if the Status register is not locked */ -+MV_STATUS mvSFlashWpRegionSet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION wpRegion); -+MV_STATUS mvSFlashWpRegionGet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION * pWpRegion); -+ -+/* Lock the status register for writing - W/Vpp pin should be low to take effect */ -+MV_STATUS mvSFlashStatRegLock (MV_SFLASH_INFO * pFlinfo, MV_BOOL srLock); -+ -+/* Get the regions sizes */ -+MV_U32 mvSFlashSizeGet (MV_SFLASH_INFO * pFlinfo); -+ -+/* Cause the falsh device to go into power save mode */ -+MV_STATUS mvSFlashPowerSaveEnter(MV_SFLASH_INFO * pFlinfo); -+MV_STATUS mvSFlashPowerSaveExit (MV_SFLASH_INFO * pFlinfo); -+ -+/* Retreive the string with the device manufacturer and model */ -+const MV_8 * mvSFlashModelGet (MV_SFLASH_INFO * pFlinfo); -+ -+#endif /* __INCmvSFlashH */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlashSpec.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlashSpec.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlashSpec.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlashSpec.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,233 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvSFlashSpecH -+#define __INCmvSFlashSpecH -+ -+/* Constants */ -+#define MV_SFLASH_READ_CMND_LENGTH 4 /* 1B opcode + 3B address */ -+#define MV_SFLASH_SE_CMND_LENGTH 4 /* 1B opcode + 3B address */ -+#define MV_SFLASH_BE_CMND_LENGTH 1 /* 1B opcode */ -+#define MV_SFLASH_PP_CMND_LENGTH 4 /* 1B opcode + 3B address */ -+#define MV_SFLASH_WREN_CMND_LENGTH 1 /* 1B opcode */ -+#define MV_SFLASH_WRDI_CMND_LENGTH 1 /* 1B opcode */ -+#define MV_SFLASH_RDID_CMND_LENGTH 1 /* 1B opcode */ -+#define MV_SFLASH_RDID_REPLY_LENGTH 3 /* 1B manf ID and 2B device ID */ -+#define MV_SFLASH_RDSR_CMND_LENGTH 1 /* 1B opcode */ -+#define MV_SFLASH_RDSR_REPLY_LENGTH 1 /* 1B status */ -+#define MV_SFLASH_WRSR_CMND_LENGTH 2 /* 1B opcode + 1B status value */ -+#define MV_SFLASH_DP_CMND_LENGTH 1 /* 1B opcode */ -+#define MV_SFLASH_RES_CMND_LENGTH 1 /* 1B opcode */ -+ -+/* Status Register Bit Masks */ -+#define MV_SFLASH_STATUS_REG_WIP_OFFSET 0 /* bit 0; write in progress */ -+#define MV_SFLASH_STATUS_REG_WP_OFFSET 2 /* bit 2-4; write protect option */ -+#define MV_SFLASH_STATUS_REG_SRWD_OFFSET 7 /* bit 7; lock status register write */ -+#define MV_SFLASH_STATUS_REG_WIP_MASK (0x1 << MV_SFLASH_STATUS_REG_WIP_OFFSET) -+#define MV_SFLASH_STATUS_REG_SRWD_MASK (0x1 << MV_SFLASH_STATUS_REG_SRWD_OFFSET) -+ -+#define MV_SFLASH_MAX_WAIT_LOOP 1000000 -+#define MV_SFLASH_CHIP_ERASE_MAX_WAIT_LOOP 0x50000000 -+ -+#define MV_SFLASH_DEFAULT_RDID_OPCD 0x9F /* Default Read ID */ -+#define MV_SFLASH_DEFAULT_WREN_OPCD 0x06 /* Default Write Enable */ -+#define MV_SFLASH_NO_SPECIFIC_OPCD 0x00 -+ -+/********************************/ -+/* ST M25Pxxx Device Specific */ -+/********************************/ -+ -+/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ -+#define MV_M25PXXX_ST_MANF_ID 0x20 -+#define MV_M25P32_DEVICE_ID 0x2016 -+#define MV_M25P32_MAX_SPI_FREQ 20000000 /* 20MHz */ -+#define MV_M25P32_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ -+#define MV_M25P32_FAST_READ_DUMMY_BYTES 1 -+#define MV_M25P64_DEVICE_ID 0x2017 -+#define MV_M25P64_MAX_SPI_FREQ 20000000 /* 20MHz */ -+#define MV_M25P64_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ -+#define MV_M25P64_FAST_READ_DUMMY_BYTES 1 -+#define MV_M25P128_DEVICE_ID 0x2018 -+#define MV_M25P128_MAX_SPI_FREQ 20000000 /* 20MHz */ -+#define MV_M25P128_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ -+#define MV_M25P128_FAST_READ_DUMMY_BYTES 1 -+ -+ -+/* Sector Sizes and population per device model*/ -+#define MV_M25P32_SECTOR_SIZE 0x10000 /* 64K */ -+#define MV_M25P64_SECTOR_SIZE 0x10000 /* 64K */ -+#define MV_M25P128_SECTOR_SIZE 0x40000 /* 256K */ -+#define MV_M25P32_SECTOR_NUMBER 64 -+#define MV_M25P64_SECTOR_NUMBER 128 -+#define MV_M25P128_SECTOR_NUMBER 64 -+#define MV_M25P_PAGE_SIZE 0x100 /* 256 byte */ -+ -+#define MV_M25P_WREN_CMND_OPCD 0x06 /* Write Enable */ -+#define MV_M25P_WRDI_CMND_OPCD 0x04 /* Write Disable */ -+#define MV_M25P_RDID_CMND_OPCD 0x9F /* Read ID */ -+#define MV_M25P_RDSR_CMND_OPCD 0x05 /* Read Status Register */ -+#define MV_M25P_WRSR_CMND_OPCD 0x01 /* Write Status Register */ -+#define MV_M25P_READ_CMND_OPCD 0x03 /* Sequential Read */ -+#define MV_M25P_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ -+#define MV_M25P_PP_CMND_OPCD 0x02 /* Page Program */ -+#define MV_M25P_SE_CMND_OPCD 0xD8 /* Sector Erase */ -+#define MV_M25P_BE_CMND_OPCD 0xC7 /* Bulk Erase */ -+#define MV_M25P_RES_CMND_OPCD 0xAB /* Read Electronic Signature */ -+ -+/* Status Register Write Protect Bit Masks - 3bits */ -+#define MV_M25P_STATUS_REG_WP_MASK (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_M25P_STATUS_BP_NONE (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_M25P_STATUS_BP_1_OF_64 (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_M25P_STATUS_BP_1_OF_32 (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_M25P_STATUS_BP_1_OF_16 (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_M25P_STATUS_BP_1_OF_8 (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_M25P_STATUS_BP_1_OF_4 (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_M25P_STATUS_BP_1_OF_2 (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_M25P_STATUS_BP_ALL (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+ -+/************************************/ -+/* MXIC MX25L6405 Device Specific */ -+/************************************/ -+ -+/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ -+#define MV_MXIC_MANF_ID 0xC2 -+#define MV_MX25L6405_DEVICE_ID 0x2017 -+#define MV_MX25L6405_MAX_SPI_FREQ 20000000 /* 20MHz */ -+#define MV_MX25L6405_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ -+#define MV_MX25L6405_FAST_READ_DUMMY_BYTES 1 -+#define MV_MXIC_DP_EXIT_DELAY 30 /* 30 ms */ -+ -+/* Sector Sizes and population per device model*/ -+#define MV_MX25L6405_SECTOR_SIZE 0x10000 /* 64K */ -+#define MV_MX25L6405_SECTOR_NUMBER 128 -+#define MV_MXIC_PAGE_SIZE 0x100 /* 256 byte */ -+ -+#define MV_MX25L_WREN_CMND_OPCD 0x06 /* Write Enable */ -+#define MV_MX25L_WRDI_CMND_OPCD 0x04 /* Write Disable */ -+#define MV_MX25L_RDID_CMND_OPCD 0x9F /* Read ID */ -+#define MV_MX25L_RDSR_CMND_OPCD 0x05 /* Read Status Register */ -+#define MV_MX25L_WRSR_CMND_OPCD 0x01 /* Write Status Register */ -+#define MV_MX25L_READ_CMND_OPCD 0x03 /* Sequential Read */ -+#define MV_MX25L_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ -+#define MV_MX25L_PP_CMND_OPCD 0x02 /* Page Program */ -+#define MV_MX25L_SE_CMND_OPCD 0xD8 /* Sector Erase */ -+#define MV_MX25L_BE_CMND_OPCD 0xC7 /* Bulk Erase */ -+#define MV_MX25L_DP_CMND_OPCD 0xB9 /* Deep Power Down */ -+#define MV_MX25L_RES_CMND_OPCD 0xAB /* Read Electronic Signature */ -+ -+/* Status Register Write Protect Bit Masks - 4bits */ -+#define MV_MX25L_STATUS_REG_WP_MASK (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_NONE (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_1_OF_128 (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_1_OF_64 (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_1_OF_32 (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_1_OF_16 (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_1_OF_8 (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_1_OF_4 (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_1_OF_2 (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_MX25L_STATUS_BP_ALL (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) -+ -+/************************************/ -+/* SPANSION S25FL128P Device Specific */ -+/************************************/ -+ -+/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ -+#define MV_SPANSION_MANF_ID 0x01 -+#define MV_S25FL128_DEVICE_ID 0x2018 -+#define MV_S25FL128_MAX_SPI_FREQ 33000000 /* 33MHz */ -+#define MV_S25FL128_MAX_FAST_SPI_FREQ 104000000 /* 104MHz */ -+#define MV_S25FL128_FAST_READ_DUMMY_BYTES 1 -+ -+/* Sector Sizes and population per device model*/ -+#define MV_S25FL128_SECTOR_SIZE 0x40000 /* 256K */ -+#define MV_S25FL128_SECTOR_NUMBER 64 -+#define MV_S25FL_PAGE_SIZE 0x100 /* 256 byte */ -+ -+#define MV_S25FL_WREN_CMND_OPCD 0x06 /* Write Enable */ -+#define MV_S25FL_WRDI_CMND_OPCD 0x04 /* Write Disable */ -+#define MV_S25FL_RDID_CMND_OPCD 0x9F /* Read ID */ -+#define MV_S25FL_RDSR_CMND_OPCD 0x05 /* Read Status Register */ -+#define MV_S25FL_WRSR_CMND_OPCD 0x01 /* Write Status Register */ -+#define MV_S25FL_READ_CMND_OPCD 0x03 /* Sequential Read */ -+#define MV_S25FL_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ -+#define MV_S25FL_PP_CMND_OPCD 0x02 /* Page Program */ -+#define MV_S25FL_SE_CMND_OPCD 0xD8 /* Sector Erase */ -+#define MV_S25FL_BE_CMND_OPCD 0xC7 /* Bulk Erase */ -+#define MV_S25FL_DP_CMND_OPCD 0xB9 /* Deep Power Down */ -+#define MV_S25FL_RES_CMND_OPCD 0xAB /* Read Electronic Signature */ -+ -+/* Status Register Write Protect Bit Masks - 4bits */ -+#define MV_S25FL_STATUS_REG_WP_MASK (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_NONE (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_1_OF_128 (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_1_OF_64 (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_1_OF_32 (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_1_OF_16 (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_1_OF_8 (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_1_OF_4 (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_1_OF_2 (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) -+#define MV_S25FL_STATUS_BP_ALL (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) -+ -+#endif /* __INCmvSFlashSpecH */ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvCompVer.txt linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvCompVer.txt ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvCompVer.txt 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvCompVer.txt 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,4 @@ -+Global HAL Version: FEROCEON_HAL_3_1_7 -+Unit HAL Version: 3.1.3 -+Description: This component includes an implementation of the unit HAL drivers -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,576 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "spi/mvSpi.h" -+#include "spi/mvSpiSpec.h" -+ -+#include "ctrlEnv/mvCtrlEnvLib.h" -+ -+/* #define MV_DEBUG */ -+#ifdef MV_DEBUG -+#define DB(x) x -+#define mvOsPrintf printf -+#else -+#define DB(x) -+#endif -+ -+ -+/******************************************************************************* -+* mvSpi16bitDataTxRx - Transmt and receive data -+* -+* DESCRIPTION: -+* Tx data and block waiting for data to be transmitted -+* -+********************************************************************************/ -+static MV_STATUS mvSpi16bitDataTxRx (MV_U16 txData, MV_U16 * pRxData) -+{ -+ MV_U32 i; -+ MV_BOOL ready = MV_FALSE; -+ -+ /* First clear the bit in the interrupt cause register */ -+ MV_REG_WRITE(MV_SPI_INT_CAUSE_REG, 0x0); -+ -+ /* Transmit data */ -+ MV_REG_WRITE(MV_SPI_DATA_OUT_REG, MV_16BIT_LE(txData)); -+ -+ /* wait with timeout for memory ready */ -+ for (i=0; i> 8) & 0xFF); -+ -+#elif defined(MV_CPU_BE) -+ -+ /* perform the data write to the buffer in two stages with 8bit each */ -+ MV_U8 * bptr = (MV_U8 *)pRxData; -+ MV_U16 data = MV_16BIT_LE(MV_REG_READ(MV_SPI_DATA_IN_REG)); -+ *bptr = ((data >> 8) & 0xFF); -+ ++bptr; -+ *bptr = (data & 0xFF); -+ -+#else -+ #error "CPU endianess isn't defined!\n" -+#endif -+ -+ } -+ else -+ *pRxData = MV_16BIT_LE(MV_REG_READ(MV_SPI_DATA_IN_REG)); -+ } -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvSpi8bitDataTxRx - Transmt and receive data (8bits) -+* -+* DESCRIPTION: -+* Tx data and block waiting for data to be transmitted -+* -+********************************************************************************/ -+static MV_STATUS mvSpi8bitDataTxRx (MV_U8 txData, MV_U8 * pRxData) -+{ -+ MV_U32 i; -+ MV_BOOL ready = MV_FALSE; -+ -+ /* First clear the bit in the interrupt cause register */ -+ MV_REG_WRITE(MV_SPI_INT_CAUSE_REG, 0x0); -+ -+ /* Transmit data */ -+ MV_REG_WRITE(MV_SPI_DATA_OUT_REG, txData); -+ -+ /* wait with timeout for memory ready */ -+ for (i=0; i serialBaudRate) -+ continue; -+ -+ /* check for exact fit */ -+ if ((cpuClk / preScale[i]) == serialBaudRate) -+ { -+ bestPrescaleIndx = i; -+ break; -+ } -+ -+ /* check if this is better than the previous one */ -+ if ((serialBaudRate - (cpuClk / preScale[i])) < minBaudOffset) -+ { -+ minBaudOffset = (serialBaudRate - (cpuClk / preScale[i])); -+ bestPrescaleIndx = i; -+ } -+ } -+ -+ if (bestPrescaleIndx > 14) -+ { -+ mvOsPrintf("%s ERROR: SPI baud rate prescale error!\n", __FUNCTION__); -+ return MV_OUT_OF_RANGE; -+ } -+ -+ /* configure the Prescale */ -+ tempReg = MV_REG_READ(MV_SPI_IF_CONFIG_REG); -+ tempReg = ((tempReg & ~MV_SPI_CLK_PRESCALE_MASK) | (bestPrescaleIndx + 0x12)); -+ MV_REG_WRITE(MV_SPI_IF_CONFIG_REG, tempReg); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSpiCsAssert - Assert the Chip Select pin indicating a new transfer -+* -+* DESCRIPTION: -+* Assert The chip select - used to select an external SPI device -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Success or Error code. -+* -+********************************************************************************/ -+MV_VOID mvSpiCsAssert(MV_VOID) -+{ -+ /* For devices in which the SPI is muxed on the MPP with other interfaces*/ -+ mvMPPConfigToSPI(); -+ mvOsUDelay(1); -+ MV_REG_BIT_SET(MV_SPI_IF_CTRL_REG, MV_SPI_CS_ENABLE_MASK); -+} -+ -+/******************************************************************************* -+* mvSpiCsDeassert - DeAssert the Chip Select pin indicating the end of a -+* SPI transfer sequence -+* -+* DESCRIPTION: -+* DeAssert the chip select pin -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Success or Error code. -+* -+********************************************************************************/ -+MV_VOID mvSpiCsDeassert(MV_VOID) -+{ -+ MV_REG_BIT_RESET(MV_SPI_IF_CTRL_REG, MV_SPI_CS_ENABLE_MASK); -+ -+ /* For devices in which the SPI is muxed on the MPP with other interfaces*/ -+ mvMPPConfigToDefault(); -+} -+ -+/******************************************************************************* -+* mvSpiRead - Read a buffer over the SPI interface -+* -+* DESCRIPTION: -+* Receive (read) a buffer over the SPI interface in 16bit chunks. If the -+* buffer size is odd, then the last chunk will be 8bits. Chip select is not -+* handled at this level. -+* -+* INPUT: -+* pRxBuff: Pointer to the buffer to hold the received data -+* buffSize: length of the pRxBuff -+* -+* OUTPUT: -+* pRxBuff: Pointer to the buffer with the received data -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSpiRead (MV_U8* pRxBuff, MV_U32 buffSize) -+{ -+ MV_STATUS ret; -+ MV_U32 bytesLeft = buffSize; -+ MV_U16* rxPtr = (MV_U16*)pRxBuff; -+ -+ /* check for null parameters */ -+ if (pRxBuff == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check that the buffer pointer and the buffer size are 16bit aligned */ -+ if ((((MV_U32)buffSize & 1) == 0) && (((MV_U32)pRxBuff & 1) == 0)) -+ { -+ /* Verify that the SPI mode is in 16bit mode */ -+ MV_REG_BIT_SET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); -+ -+ /* TX/RX as long we have complete 16bit chunks */ -+ while (bytesLeft >= MV_SPI_16_BIT_CHUNK_SIZE) -+ { -+ /* Transmitted and wait for the transfer to be completed */ -+ if ((ret = mvSpi16bitDataTxRx(MV_SPI_DUMMY_WRITE_16BITS, rxPtr)) != MV_OK) -+ return ret; -+ -+ /* increment the pointers */ -+ rxPtr++; -+ bytesLeft -= MV_SPI_16_BIT_CHUNK_SIZE; -+ } -+ -+ } -+ else -+ { -+ /* Verify that the SPI mode is in 8bit mode */ -+ MV_REG_BIT_RESET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); -+ -+ /* TX/RX in 8bit chanks */ -+ while (bytesLeft > 0) -+ { -+ /* Transmitted and wait for the transfer to be completed */ -+ if ((ret = mvSpi8bitDataTxRx(MV_SPI_DUMMY_WRITE_8BITS, pRxBuff)) != MV_OK) -+ return ret; -+ /* increment the pointers */ -+ pRxBuff++; -+ bytesLeft--; -+ } -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvSpiWrite - Transmit a buffer over the SPI interface -+* -+* DESCRIPTION: -+* Transmit a buffer over the SPI interface in 16bit chunks. If the -+* buffer size is odd, then the last chunk will be 8bits. No chip select -+* action is taken. -+* -+* INPUT: -+* pTxBuff: Pointer to the buffer holding the TX data -+* buffSize: length of the pTxBuff -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSpiWrite(MV_U8* pTxBuff, MV_U32 buffSize) -+{ -+ MV_STATUS ret; -+ MV_U32 bytesLeft = buffSize; -+ MV_U16* txPtr = (MV_U16*)pTxBuff; -+ -+ /* check for null parameters */ -+ if (pTxBuff == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check that the buffer pointer and the buffer size are 16bit aligned */ -+ if ((((MV_U32)buffSize & 1) == 0) && (((MV_U32)pTxBuff & 1) == 0)) -+ { -+ /* Verify that the SPI mode is in 16bit mode */ -+ MV_REG_BIT_SET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); -+ -+ /* TX/RX as long we have complete 16bit chunks */ -+ while (bytesLeft >= MV_SPI_16_BIT_CHUNK_SIZE) -+ { -+ /* Transmitted and wait for the transfer to be completed */ -+ if ((ret = mvSpi16bitDataTxRx(*txPtr, NULL)) != MV_OK) -+ return ret; -+ -+ /* increment the pointers */ -+ txPtr++; -+ bytesLeft -= MV_SPI_16_BIT_CHUNK_SIZE; -+ } -+ } -+ else -+ { -+ -+ /* Verify that the SPI mode is in 8bit mode */ -+ MV_REG_BIT_RESET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); -+ -+ /* TX/RX in 8bit chanks */ -+ while (bytesLeft > 0) -+ { -+ /* Transmitted and wait for the transfer to be completed */ -+ if ((ret = mvSpi8bitDataTxRx(*pTxBuff, NULL)) != MV_OK) -+ return ret; -+ -+ /* increment the pointers */ -+ pTxBuff++; -+ bytesLeft--; -+ } -+ } -+ -+ return MV_OK; -+} -+ -+ -+/******************************************************************************* -+* mvSpiReadWrite - Read and Write a buffer simultanuosely -+* -+* DESCRIPTION: -+* Transmit and receive a buffer over the SPI in 16bit chunks. If the -+* buffer size is odd, then the last chunk will be 8bits. The SPI chip -+* select is not handled implicitely. -+* -+* INPUT: -+* pRxBuff: Pointer to the buffer to write the RX info in -+* pTxBuff: Pointer to the buffer holding the TX info -+* buffSize: length of both the pTxBuff and pRxBuff -+* -+* OUTPUT: -+* pRxBuff: Pointer of the buffer holding the RX data -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSpiReadWrite(MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize) -+{ -+ MV_STATUS ret; -+ MV_U32 bytesLeft = buffSize; -+ MV_U16* txPtr = (MV_U16*)pTxBuff; -+ MV_U16* rxPtr = (MV_U16*)pRxBuff; -+ -+ /* check for null parameters */ -+ if ((pRxBuff == NULL) || (pTxBuff == NULL)) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* Check that the buffer pointer and the buffer size are 16bit aligned */ -+ if ((((MV_U32)buffSize & 1) == 0) && (((MV_U32)pTxBuff & 1) == 0) && (((MV_U32)pRxBuff & 1) == 0)) -+ { -+ /* Verify that the SPI mode is in 16bit mode */ -+ MV_REG_BIT_SET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); -+ -+ /* TX/RX as long we have complete 16bit chunks */ -+ while (bytesLeft >= MV_SPI_16_BIT_CHUNK_SIZE) -+ { -+ /* Transmitted and wait for the transfer to be completed */ -+ if ((ret = mvSpi16bitDataTxRx(*txPtr, rxPtr)) != MV_OK) -+ return ret; -+ -+ /* increment the pointers */ -+ txPtr++; -+ rxPtr++; -+ bytesLeft -= MV_SPI_16_BIT_CHUNK_SIZE; -+ } -+ } -+ else -+ { -+ /* Verify that the SPI mode is in 8bit mode */ -+ MV_REG_BIT_RESET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); -+ -+ /* TX/RX in 8bit chanks */ -+ while (bytesLeft > 0) -+ { -+ /* Transmitted and wait for the transfer to be completed */ -+ if ( (ret = mvSpi8bitDataTxRx(*pTxBuff, pRxBuff) ) != MV_OK) -+ return ret; -+ pRxBuff++; -+ pTxBuff++; -+ bytesLeft--; -+ } -+ } -+ -+ return MV_OK; -+} -+ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,94 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvSpihH -+#define __INCmvSpihH -+ -+#include "mvCommon.h" -+#include "mvOs.h" -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+ -+/* Function Prototypes */ -+/* Init */ -+MV_STATUS mvSpiInit (MV_U32 serialBaudRate); -+ -+/* Set the Frequency of the Spi clock */ -+MV_STATUS mvSpiBaudRateSet(MV_U32 serialBaudRate); -+ -+/* Assert the SPI chip select */ -+MV_VOID mvSpiCsAssert (MV_VOID); -+ -+/* De-assert the SPI chip select */ -+MV_VOID mvSpiCsDeassert (MV_VOID); -+ -+/* Simultanuous Read and write */ -+MV_STATUS mvSpiReadWrite (MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize); -+ -+/* serialize a buffer on the TX line - Rx is ignored */ -+MV_STATUS mvSpiWrite (MV_U8* pTxBuff, MV_U32 buffSize); -+ -+/* read from the RX line by writing dummy values to the TX line */ -+MV_STATUS mvSpiRead (MV_U8* pRxBuff, MV_U32 buffSize); -+ -+#endif /* __INCmvSpihH */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,249 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#include "spi/mvSpi.h" -+#include "spi/mvSpiSpec.h" -+ -+/*#define MV_DEBUG*/ -+#ifdef MV_DEBUG -+#define DB(x) x -+#else -+#define DB(x) -+#endif -+ -+ -+/******************************************************************************* -+* mvSpiReadAndWrite - Read and Write a buffer simultanuousely -+* -+* DESCRIPTION: -+* Transmit and receive a buffer over the SPI in 16bit chunks. If the -+* buffer size is odd, then the last chunk will be 8bits. -+* -+* INPUT: -+* pRxBuff: Pointer to the buffer to write the RX info in -+* pTxBuff: Pointer to the buffer holding the TX info -+* buffSize: length of both the pTxBuff and pRxBuff -+* -+* OUTPUT: -+* pRxBuff: Pointer of the buffer holding the RX data -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSpiReadAndWrite(MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize) -+{ -+ MV_STATUS ret; -+ -+ /* check for null parameters */ -+ if ((pRxBuff == NULL) || (pTxBuff == NULL) || (buffSize == 0)) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* First assert the chip select */ -+ mvSpiCsAssert(); -+ -+ ret = mvSpiReadWrite(pRxBuff, pTxBuff, buffSize); -+ -+ /* Finally deassert the chip select */ -+ mvSpiCsDeassert(); -+ -+ return ret; -+} -+ -+/******************************************************************************* -+* mvSpiWriteThenWrite - Serialize a command followed by the data over the TX line -+* -+* DESCRIPTION: -+* Assert the chip select line. Transmit the command buffer followed by -+* the data buffer. Then deassert the CS line. -+* -+* INPUT: -+* pCmndBuff: Pointer to the command buffer to transmit -+* cmndSize: length of the command size -+* pTxDataBuff: Pointer to the data buffer to transmit -+* txDataSize: length of the data buffer -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSpiWriteThenWrite (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pTxDataBuff, -+ MV_U32 txDataSize) -+{ -+ MV_STATUS ret = MV_OK, tempRet; -+ -+ /* check for null parameters */ -+#ifndef CONFIG_MARVELL -+ if(NULL == pTxDataBuff) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+#endif -+ -+ if (pCmndBuff == NULL) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* First assert the chip select */ -+ mvSpiCsAssert(); -+ -+ /* first write the command */ -+ if ((cmndSize) && (pCmndBuff != NULL)) -+ { -+ if ((tempRet = mvSpiWrite(pCmndBuff, cmndSize)) != MV_OK) -+ ret = tempRet; -+ } -+ -+ /* Then write the data buffer */ -+#ifndef CONFIG_MARVELL -+ if (txDataSize) -+#else -+ if ((txDataSize) && (pTxDataBuff != NULL)) -+#endif -+ { -+ if ((tempRet = mvSpiWrite(pTxDataBuff, txDataSize)) != MV_OK) -+ ret = tempRet; -+ } -+ -+ /* Finally deassert the chip select */ -+ mvSpiCsDeassert(); -+ -+ return ret; -+} -+ -+/******************************************************************************* -+* mvSpiWriteThenRead - Serialize a command then read a data buffer -+* -+* DESCRIPTION: -+* Assert the chip select line. Transmit the command buffer then read -+* the data buffer. Then deassert the CS line. -+* -+* INPUT: -+* pCmndBuff: Pointer to the command buffer to transmit -+* cmndSize: length of the command size -+* pRxDataBuff: Pointer to the buffer to read the data in -+* txDataSize: length of the data buffer -+* -+* OUTPUT: -+* pRxDataBuff: Pointer to the buffer holding the data -+* -+* RETURN: -+* Success or Error code. -+* -+* -+*******************************************************************************/ -+MV_STATUS mvSpiWriteThenRead (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pRxDataBuff, -+ MV_U32 rxDataSize,MV_U32 dummyBytesToRead) -+{ -+ MV_STATUS ret = MV_OK, tempRet; -+ MV_U8 dummyByte; -+ -+ /* check for null parameters */ -+ if ((pCmndBuff == NULL) && (pRxDataBuff == NULL)) -+ { -+ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); -+ return MV_BAD_PARAM; -+ } -+ -+ /* First assert the chip select */ -+ mvSpiCsAssert(); -+ -+ /* first write the command */ -+ if ((cmndSize) && (pCmndBuff != NULL)) -+ { -+ if ((tempRet = mvSpiWrite(pCmndBuff, cmndSize)) != MV_OK) -+ ret = tempRet; -+ } -+ -+ /* Read dummy bytes before real data. */ -+ while(dummyBytesToRead) -+ { -+ mvSpiRead(&dummyByte,1); -+ dummyBytesToRead--; -+ } -+ -+ /* Then write the data buffer */ -+ if ((rxDataSize) && (pRxDataBuff != NULL)) -+ { -+ if ((tempRet = mvSpiRead(pRxDataBuff, rxDataSize)) != MV_OK) -+ ret = tempRet; -+ } -+ -+ /* Finally deassert the chip select */ -+ mvSpiCsDeassert(); -+ -+ return ret; -+} -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,82 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvSpiCmndhH -+#define __INCmvSpiCmndhH -+ -+#include "mvTypes.h" -+ -+/* Function Prototypes */ -+ -+/* Simultanuous Read and write */ -+MV_STATUS mvSpiReadAndWrite (MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize); -+ -+/* write command - write a command and then write data */ -+MV_STATUS mvSpiWriteThenWrite (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pTxDataBuff, MV_U32 txDataSize); -+ -+/* read command - write a command and then read data by writing dummy data */ -+MV_STATUS mvSpiWriteThenRead (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pRxDataBuff, -+ MV_U32 rxDataSize,MV_U32 dummyBytesToRead); -+ -+#endif /* __INCmvSpiCmndhH */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiSpec.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiSpec.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiSpec.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiSpec.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,98 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+#ifndef __INCmvSpiSpecH -+#define __INCmvSpiSpecH -+ -+/* Constants */ -+#define MV_SPI_WAIT_RDY_MAX_LOOP 100000 -+#define MV_SPI_16_BIT_CHUNK_SIZE 2 -+#define MV_SPI_DUMMY_WRITE_16BITS 0xFFFF -+#define MV_SPI_DUMMY_WRITE_8BITS 0xFF -+ -+/* Marvell Flash Device Controller Registers */ -+#define MV_SPI_CTRLR_OFST 0x10600 -+#define MV_SPI_IF_CTRL_REG (MV_SPI_CTRLR_OFST + 0x00) -+#define MV_SPI_IF_CONFIG_REG (MV_SPI_CTRLR_OFST + 0x04) -+#define MV_SPI_DATA_OUT_REG (MV_SPI_CTRLR_OFST + 0x08) -+#define MV_SPI_DATA_IN_REG (MV_SPI_CTRLR_OFST + 0x0c) -+#define MV_SPI_INT_CAUSE_REG (MV_SPI_CTRLR_OFST + 0x10) -+#define MV_SPI_INT_CAUSE_MASK_REG (MV_SPI_CTRLR_OFST + 0x14) -+ -+/* Serial Memory Interface Control Register Masks */ -+#define MV_SPI_CS_ENABLE_OFFSET 0 /* bit 0 */ -+#define MV_SPI_MEMORY_READY_OFFSET 1 /* bit 1 */ -+#define MV_SPI_CS_ENABLE_MASK (0x1 << MV_SPI_CS_ENABLE_OFFSET) -+#define MV_SPI_MEMORY_READY_MASK (0x1 << MV_SPI_MEMORY_READY_OFFSET) -+ -+/* Serial Memory Interface Configuration Register Masks */ -+#define MV_SPI_CLK_PRESCALE_OFFSET 0 /* bit 0-4 */ -+#define MV_SPI_BYTE_LENGTH_OFFSET 5 /* bit 5 */ -+#define MV_SPI_ADDRESS_BURST_LENGTH_OFFSET 8 /* bit 8-9 */ -+#define MV_SPI_CLK_PRESCALE_MASK (0x1F << MV_SPI_CLK_PRESCALE_OFFSET) -+#define MV_SPI_BYTE_LENGTH_MASK (0x1 << MV_SPI_BYTE_LENGTH_OFFSET) -+#define MV_SPI_ADDRESS_BURST_LENGTH_MASK (0x3 << MV_SPI_ADDRESS_BURST_LENGTH_OFFSET) -+ -+#endif /* __INCmvSpiSpecH */ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvCompVer.txt linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvCompVer.txt ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvCompVer.txt 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvCompVer.txt 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,4 @@ -+Global HAL Version: FEROCEON_HAL_3_1_7 -+Unit HAL Version: 3.1.5 -+Description: This component includes an implementation of the unit HAL drivers -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.c ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,1023 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+#include "mvTwsi.h" -+#include "mvTwsiSpec.h" -+#include "cpu/mvCpu.h" -+ -+ -+/*#define MV_DEBUG*/ -+#ifdef MV_DEBUG -+#define DB(x) x -+#else -+#define DB(x) -+#endif -+ -+static MV_VOID twsiIntFlgClr(MV_U8 chanNum); -+static MV_BOOL twsiMainIntGet(MV_U8 chanNum); -+static MV_VOID twsiAckBitSet(MV_U8 chanNum); -+static MV_U32 twsiStsGet(MV_U8 chanNum); -+static MV_VOID twsiReset(MV_U8 chanNum); -+static MV_STATUS twsiAddr7BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command); -+static MV_STATUS twsiAddr10BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command); -+static MV_STATUS twsiDataTransmit(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize); -+static MV_STATUS twsiDataReceive(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize); -+static MV_STATUS twsiTargetOffsSet(MV_U8 chanNum, MV_U32 offset,MV_BOOL moreThen256); -+ -+ -+static MV_BOOL twsiTimeoutChk(MV_U32 timeout, const MV_8 *pString) -+{ -+ if(timeout >= TWSI_TIMEOUT_VALUE) -+ { -+ DB(mvOsPrintf("%s",pString)); -+ return MV_TRUE; -+ } -+ return MV_FALSE; -+ -+} -+/******************************************************************************* -+* mvTwsiStartBitSet - Set start bit on the bus -+* -+* DESCRIPTION: -+* This routine sets the start bit on the TWSI bus. -+* The routine first checks for interrupt flag condition, then it sets -+* the start bit in the TWSI Control register. -+* If the interrupt flag condition check previously was set, the function -+* will clear it. -+* The function then wait for the start bit to be cleared by the HW. -+* Then it waits for the interrupt flag to be set and eventually, the -+* TWSI status is checked to be 0x8 or 0x10(repeated start bit). -+* -+* INPUT: -+* chanNum - TWSI channel. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK is start bit was set successfuly on the bus. -+* MV_FAIL if interrupt flag was set before setting start bit. -+* -+*******************************************************************************/ -+MV_STATUS mvTwsiStartBitSet(MV_U8 chanNum) -+{ -+ MV_BOOL isIntFlag = MV_FALSE; -+ MV_U32 timeout, temp; -+ -+ DB(mvOsPrintf("TWSI: mvTwsiStartBitSet \n")); -+ /* check Int flag */ -+ if(twsiMainIntGet(chanNum)) -+ isIntFlag = MV_TRUE; -+ /* set start Bit */ -+ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); -+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp | TWSI_CONTROL_START_BIT); -+ -+ /* in case that the int flag was set before i.e. repeated start bit */ -+ if(isIntFlag){ -+ DB(mvOsPrintf("TWSI: mvTwsiStartBitSet repeated start Bit\n")); -+ twsiIntFlgClr(chanNum); -+ } -+ -+ /* wait for interrupt */ -+ timeout = 0; -+ while(!twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: mvTwsiStartBitSet ERROR - Start Clear bit TimeOut .\n")) -+ return MV_TIMEOUT; -+ -+ -+ /* check that start bit went down */ -+ if((MV_REG_READ(TWSI_CONTROL_REG(chanNum)) & TWSI_CONTROL_START_BIT) != 0) -+ { -+ mvOsPrintf("TWSI: mvTwsiStartBitSet ERROR - start bit didn't went down\n"); -+ return MV_FAIL; -+ } -+ -+ /* check the status */ -+ temp = twsiStsGet(chanNum); -+ if(( temp != TWSI_START_CON_TRA ) && ( temp != TWSI_REPEATED_START_CON_TRA )) -+ { -+ mvOsPrintf("TWSI: mvTwsiStartBitSet ERROR - status %x after Set Start Bit. \n",temp); -+ return MV_FAIL; -+ } -+ -+ return MV_OK; -+ -+} -+ -+/******************************************************************************* -+* mvTwsiStopBitSet - Set stop bit on the bus -+* -+* DESCRIPTION: -+* This routine set the stop bit on the TWSI bus. -+* The function then wait for the stop bit to be cleared by the HW. -+* Finally the function checks for status of 0xF8. -+* -+* INPUT: -+* chanNum - TWSI channel -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE is stop bit was set successfuly on the bus. -+* -+*******************************************************************************/ -+MV_STATUS mvTwsiStopBitSet(MV_U8 chanNum) -+{ -+ MV_U32 timeout, temp; -+ -+ /* Generate stop bit */ -+ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); -+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp | TWSI_CONTROL_STOP_BIT); -+ -+ twsiIntFlgClr(chanNum); -+ -+ /* wait for stop bit to come down */ -+ timeout = 0; -+ while( ((MV_REG_READ(TWSI_CONTROL_REG(chanNum)) & TWSI_CONTROL_STOP_BIT) != 0) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: mvTwsiStopBitSet ERROR - Stop bit TimeOut .\n")) -+ return MV_TIMEOUT; -+ -+ /* check that the stop bit went down */ -+ if((MV_REG_READ(TWSI_CONTROL_REG(chanNum)) & TWSI_CONTROL_STOP_BIT) != 0) -+ { -+ mvOsPrintf("TWSI: mvTwsiStopBitSet ERROR - stop bit didn't went down. \n"); -+ return MV_FAIL; -+ } -+ -+ /* check the status */ -+ temp = twsiStsGet(chanNum); -+ if( temp != TWSI_NO_REL_STS_INT_FLAG_IS_KEPT_0){ -+ mvOsPrintf("TWSI: mvTwsiStopBitSet ERROR - status %x after Stop Bit. \n", temp); -+ return MV_FAIL; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* twsiMainIntGet - Get twsi bit from main Interrupt cause. -+* -+* DESCRIPTION: -+* This routine returns the twsi interrupt flag value. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_TRUE is interrupt flag is set, MV_FALSE otherwise. -+* -+*******************************************************************************/ -+static MV_BOOL twsiMainIntGet(MV_U8 chanNum) -+{ -+ MV_U32 temp; -+ -+ /* get the int flag bit */ -+ -+ temp = MV_REG_READ(TWSI_CPU_MAIN_INT_CAUSE_REG); -+ if (temp & (TWSI0_CPU_MAIN_INT_BIT << chanNum)) -+ return MV_TRUE; -+ -+ return MV_FALSE; -+} -+/******************************************************************************* -+* twsiIntFlgClr - Clear Interrupt flag. -+* -+* DESCRIPTION: -+* This routine clears the interrupt flag. It does NOT poll the interrupt -+* to make sure the clear. After clearing the interrupt, it waits for at -+* least 1 miliseconds. -+* -+* INPUT: -+* chanNum - TWSI channel -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+static MV_VOID twsiIntFlgClr(MV_U8 chanNum) -+{ -+ MV_U32 temp; -+ -+ /* wait for 1 mili to prevent TWSI register write after write problems */ -+ mvOsDelay(1); -+ /* clear the int flag bit */ -+ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); -+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum),temp & ~(TWSI_CONTROL_INT_FLAG_SET)); -+ -+ /* wait for 1 mili sec for the clear to take effect */ -+ mvOsDelay(1); -+ -+ return; -+} -+ -+ -+/******************************************************************************* -+* twsiAckBitSet - Set acknowledge bit on the bus -+* -+* DESCRIPTION: -+* This routine set the acknowledge bit on the TWSI bus. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+static MV_VOID twsiAckBitSet(MV_U8 chanNum) -+{ -+ MV_U32 temp; -+ -+ /*Set the Ack bit */ -+ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); -+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp | TWSI_CONTROL_ACK); -+ -+ /* Add delay of 1ms */ -+ mvOsDelay(1); -+ return; -+} -+ -+ -+/******************************************************************************* -+* twsiInit - Initialize TWSI interface -+* -+* DESCRIPTION: -+* This routine: -+* -Reset the TWSI. -+* -Initialize the TWSI clock baud rate according to given frequancy -+* parameter based on Tclk frequancy and enables TWSI slave. -+* -Set the ack bit. -+* -Assign the TWSI slave address according to the TWSI address Type. -+* -+* -+* INPUT: -+* chanNum - TWSI channel -+* frequancy - TWSI frequancy in KHz. (up to 100KHZ) -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* Actual frequancy. -+* -+*******************************************************************************/ -+MV_U32 mvTwsiInit(MV_U8 chanNum, MV_HZ frequancy, MV_U32 Tclk, MV_TWSI_ADDR *pTwsiAddr, MV_BOOL generalCallEnable) -+{ -+ MV_U32 n,m,freq,margin,minMargin = 0xffffffff; -+ MV_U32 power; -+ MV_U32 actualFreq = 0,actualN = 0,actualM = 0,val; -+ -+ if(frequancy > 100000) -+ { -+ mvOsPrintf("Warning TWSI frequancy is too high, please use up tp 100Khz. \n"); -+ } -+ -+ DB(mvOsPrintf("TWSI: mvTwsiInit - Tclk = %d freq = %d\n",Tclk,frequancy)); -+ /* Calucalte N and M for the TWSI clock baud rate */ -+ for(n = 0 ; n < 8 ; n++) -+ { -+ for(m = 0 ; m < 16 ; m++) -+ { -+ power = 2 << n; /* power = 2^(n+1) */ -+ freq = Tclk/(10*(m+1)*power); -+ margin = MV_ABS(frequancy - freq); -+ if(margin < minMargin) -+ { -+ minMargin = margin; -+ actualFreq = freq; -+ actualN = n; -+ actualM = m; -+ } -+ } -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiInit - actN %d actM %d actFreq %d\n",actualN , actualM, actualFreq)); -+ /* Reset the TWSI logic */ -+ twsiReset(chanNum); -+ -+ /* Set the baud rate */ -+ val = ((actualM<< TWSI_BAUD_RATE_M_OFFS) | actualN << TWSI_BAUD_RATE_N_OFFS); -+ MV_REG_WRITE(TWSI_STATUS_BAUDE_RATE_REG(chanNum),val); -+ -+ /* Enable the TWSI and slave */ -+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), TWSI_CONTROL_ENA | TWSI_CONTROL_ACK); -+ -+ /* set the TWSI slave address */ -+ if( pTwsiAddr->type == ADDR10_BIT )/* 10 Bit deviceAddress */ -+ { -+ /* writing the 2 most significant bits of the 10 bit address*/ -+ val = ((pTwsiAddr->address & TWSI_SLAVE_ADDR_10BIT_MASK) >> TWSI_SLAVE_ADDR_10BIT_OFFS ); -+ /* bits 7:3 must be 0x11110 */ -+ val |= TWSI_SLAVE_ADDR_10BIT_CONST; -+ /* set GCE bit */ -+ if(generalCallEnable) -+ val |= TWSI_SLAVE_ADDR_GCE_ENA; -+ /* write slave address */ -+ MV_REG_WRITE(TWSI_SLAVE_ADDR_REG(chanNum),val); -+ -+ /* writing the 8 least significant bits of the 10 bit address*/ -+ val = (pTwsiAddr->address << TWSI_EXTENDED_SLAVE_OFFS) & TWSI_EXTENDED_SLAVE_MASK; -+ MV_REG_WRITE(TWSI_EXTENDED_SLAVE_ADDR_REG(chanNum), val); -+ } -+ else /*7 bit address*/ -+ { -+ /* set the 7 Bits address */ -+ MV_REG_WRITE(TWSI_EXTENDED_SLAVE_ADDR_REG(chanNum),0x0); -+ val = (pTwsiAddr->address << TWSI_SLAVE_ADDR_7BIT_OFFS) & TWSI_SLAVE_ADDR_7BIT_MASK; -+ MV_REG_WRITE(TWSI_SLAVE_ADDR_REG(chanNum), val); -+ } -+ -+ /* unmask twsi int */ -+ val = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); -+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), val | TWSI_CONTROL_INT_ENA); -+ /* Add delay of 1ms */ -+ mvOsDelay(1); -+ -+ return actualFreq; -+} -+ -+ -+/******************************************************************************* -+* twsiStsGet - Get the TWSI status value. -+* -+* DESCRIPTION: -+* This routine returns the TWSI status value. -+* -+* INPUT: -+* chanNum - TWSI channel -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_U32 - the TWSI status. -+* -+*******************************************************************************/ -+static MV_U32 twsiStsGet(MV_U8 chanNum) -+{ -+ return MV_REG_READ(TWSI_STATUS_BAUDE_RATE_REG(chanNum)); -+ -+} -+ -+/******************************************************************************* -+* twsiReset - Reset the TWSI. -+* -+* DESCRIPTION: -+* Resets the TWSI logic and sets all TWSI registers to their reset values. -+* -+* INPUT: -+* chanNum - TWSI channel -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None -+* -+*******************************************************************************/ -+static MV_VOID twsiReset(MV_U8 chanNum) -+{ -+ /* Reset the TWSI logic */ -+ MV_REG_WRITE(TWSI_SOFT_RESET_REG(chanNum),0); -+ -+ /* wait for 2 mili sec */ -+ mvOsDelay(2); -+ -+ return; -+} -+ -+ -+ -+ -+/******************************* POLICY ****************************************/ -+ -+ -+ -+/******************************************************************************* -+* mvTwsiAddrSet - Set address on TWSI bus. -+* -+* DESCRIPTION: -+* This function Set address (7 or 10 Bit address) on the Twsi Bus. -+* -+* INPUT: -+* chanNum - TWSI channel -+* pTwsiAddr - twsi address. -+* command - read / write . -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK - if setting the address completed succesfully. -+* MV_FAIL otherwmise. -+* -+*******************************************************************************/ -+MV_STATUS mvTwsiAddrSet(MV_U8 chanNum, MV_TWSI_ADDR *pTwsiAddr, MV_TWSI_CMD command) -+{ -+ DB(mvOsPrintf("TWSI: mvTwsiAddr7BitSet addr %x , type %d, cmd is %s\n",pTwsiAddr->address,\ -+ pTwsiAddr->type, ((command==MV_TWSI_WRITE)?"Write":"Read") )); -+ /* 10 Bit address */ -+ if(pTwsiAddr->type == ADDR10_BIT) -+ { -+ return twsiAddr10BitSet(chanNum, pTwsiAddr->address,command); -+ } -+ /* 7 Bit address */ -+ else -+ { -+ return twsiAddr7BitSet(chanNum, pTwsiAddr->address,command); -+ } -+ -+} -+ -+/******************************************************************************* -+* twsiAddr10BitSet - Set 10 Bit address on TWSI bus. -+* -+* DESCRIPTION: -+* There are two address phases: -+* 1) Write '11110' to data register bits [7:3] and 10-bit address MSB -+* (bits [9:8]) to data register bits [2:1] plus a write(0) or read(1) bit -+* to the Data register. Then it clears interrupt flag which drive -+* the address on the TWSI bus. The function then waits for interrupt -+* flag to be active and status 0x18 (write) or 0x40 (read) to be set. -+* 2) write the rest of 10-bit address to data register and clears -+* interrupt flag which drive the address on the TWSI bus. The -+* function then waits for interrupt flag to be active and status -+* 0xD0 (write) or 0xE0 (read) to be set. -+* -+* INPUT: -+* chanNum - TWSI channel -+* deviceAddress - twsi address. -+* command - read / write . -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK - if setting the address completed succesfully. -+* MV_FAIL otherwmise. -+* -+*******************************************************************************/ -+static MV_STATUS twsiAddr10BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command) -+{ -+ MV_U32 val,timeout; -+ -+ /* writing the 2 most significant bits of the 10 bit address*/ -+ val = ((deviceAddress & TWSI_DATA_ADDR_10BIT_MASK) >> TWSI_DATA_ADDR_10BIT_OFFS ); -+ /* bits 7:3 must be 0x11110 */ -+ val |= TWSI_DATA_ADDR_10BIT_CONST; -+ /* set command */ -+ val |= command; -+ MV_REG_WRITE(TWSI_DATA_REG(chanNum), val); -+ /* WA add a delay */ -+ mvOsDelay(1); -+ -+ /* clear Int flag */ -+ twsiIntFlgClr(chanNum); -+ -+ /* wait for Int to be Set */ -+ timeout = 0; -+ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiAddr10BitSet ERROR - 1st addr (10Bit) Int TimeOut.\n")) -+ return MV_TIMEOUT; -+ -+ /* check the status */ -+ val = twsiStsGet(chanNum); -+ if(( (val != TWSI_AD_PLS_RD_BIT_TRA_ACK_REC) && (command == MV_TWSI_READ ) ) || -+ ( (val != TWSI_AD_PLS_WR_BIT_TRA_ACK_REC) && (command == MV_TWSI_WRITE) )) -+ { -+ mvOsPrintf("TWSI: twsiAddr10BitSet ERROR - status %x 1st addr (10 Bit) in %s mode.\n"\ -+ ,val, ((command==MV_TWSI_WRITE)?"Write":"Read") ); -+ return MV_FAIL; -+ } -+ -+ /* set 8 LSB of the address */ -+ val = (deviceAddress << TWSI_DATA_ADDR_7BIT_OFFS) & TWSI_DATA_ADDR_7BIT_MASK; -+ MV_REG_WRITE(TWSI_DATA_REG(chanNum), val); -+ -+ /* clear Int flag */ -+ twsiIntFlgClr(chanNum); -+ -+ /* wait for Int to be Set */ -+ timeout = 0; -+ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiAddr10BitSet ERROR - 2nd (10 Bit) Int TimOut.\n")) -+ return MV_TIMEOUT; -+ -+ /* check the status */ -+ val = twsiStsGet(chanNum); -+ if(( (val != TWSI_SEC_AD_PLS_RD_BIT_TRA_ACK_REC) && (command == MV_TWSI_READ ) ) || -+ ( (val != TWSI_SEC_AD_PLS_WR_BIT_TRA_ACK_REC) && (command == MV_TWSI_WRITE) )) -+ { -+ mvOsPrintf("TWSI: twsiAddr10BitSet ERROR - status %x 2nd addr(10 Bit) in %s mode.\n"\ -+ ,val, ((command==MV_TWSI_WRITE)?"Write":"Read") ); -+ return MV_FAIL; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* twsiAddr7BitSet - Set 7 Bit address on TWSI bus. -+* -+* DESCRIPTION: -+* This function writes 7 bit address plus a write or read bit to the -+* Data register. Then it clears interrupt flag which drive the address on -+* the TWSI bus. The function then waits for interrupt flag to be active -+* and status 0x18 (write) or 0x40 (read) to be set. -+* -+* INPUT: -+* chanNum - TWSI channel -+* deviceAddress - twsi address. -+* command - read / write . -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK - if setting the address completed succesfully. -+* MV_FAIL otherwmise. -+* -+*******************************************************************************/ -+static MV_STATUS twsiAddr7BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command) -+{ -+ MV_U32 val,timeout; -+ -+ /* set the address */ -+ val = (deviceAddress << TWSI_DATA_ADDR_7BIT_OFFS) & TWSI_DATA_ADDR_7BIT_MASK; -+ /* set command */ -+ val |= command; -+ MV_REG_WRITE(TWSI_DATA_REG(chanNum), val); -+ /* WA add a delay */ -+ mvOsDelay(1); -+ -+ /* clear Int flag */ -+ twsiIntFlgClr(chanNum); -+ -+ /* wait for Int to be Set */ -+ timeout = 0; -+ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiAddr7BitSet ERROR - Addr (7 Bit) int TimeOut.\n")) -+ return MV_TIMEOUT; -+ -+ /* check the status */ -+ val = twsiStsGet(chanNum); -+ if(( (val != TWSI_AD_PLS_RD_BIT_TRA_ACK_REC) && (command == MV_TWSI_READ ) ) || -+ ( (val != TWSI_AD_PLS_WR_BIT_TRA_ACK_REC) && (command == MV_TWSI_WRITE) )) -+ { -+ /* only in debug, since in boot we try to read the SPD of both DRAM, and we don't -+ want error messeges in case DIMM doesn't exist. */ -+ DB(mvOsPrintf("TWSI: twsiAddr7BitSet ERROR - status %x addr (7 Bit) in %s mode.\n"\ -+ ,val,((command==MV_TWSI_WRITE)?"Write":"Read") )); -+ return MV_FAIL; -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* twsiDataWrite - Trnasmit a data block over TWSI bus. -+* -+* DESCRIPTION: -+* This function writes a given data block to TWSI bus in 8 bit granularity. -+* first The function waits for interrupt flag to be active then -+* For each 8-bit data: -+* The function writes data to data register. It then clears -+* interrupt flag which drives the data on the TWSI bus. -+* The function then waits for interrupt flag to be active and status -+* 0x28 to be set. -+* -+* -+* INPUT: -+* chanNum - TWSI channel -+* pBlock - Data block. -+* blockSize - number of chars in pBlock. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK - if transmiting the block completed succesfully, -+* MV_BAD_PARAM - if pBlock is NULL, -+* MV_FAIL otherwmise. -+* -+*******************************************************************************/ -+static MV_STATUS twsiDataTransmit(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize) -+{ -+ MV_U32 timeout, temp, blockSizeWr = blockSize; -+ -+ if(NULL == pBlock) -+ return MV_BAD_PARAM; -+ -+ /* wait for Int to be Set */ -+ timeout = 0; -+ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataTransmit ERROR - Read Data Int TimeOut.\n")) -+ return MV_TIMEOUT; -+ -+ while(blockSizeWr) -+ { -+ /* write the data*/ -+ MV_REG_WRITE(TWSI_DATA_REG(chanNum),(MV_U32)*pBlock); -+ DB(mvOsPrintf("TWSI: twsiDataTransmit place = %d write %x \n",\ -+ blockSize - blockSizeWr, *pBlock)); -+ pBlock++; -+ blockSizeWr--; -+ -+ twsiIntFlgClr(chanNum); -+ -+ /* wait for Int to be Set */ -+ timeout = 0; -+ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataTransmit ERROR - Read Data Int TimeOut.\n")) -+ return MV_TIMEOUT; -+ -+ /* check the status */ -+ temp = twsiStsGet(chanNum); -+ if(temp != TWSI_M_TRAN_DATA_BYTE_ACK_REC) -+ { -+ mvOsPrintf("TWSI: twsiDataTransmit ERROR - status %x in write trans\n",temp); -+ return MV_FAIL; -+ } -+ -+ } -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* twsiDataReceive - Receive data block from TWSI bus. -+* -+* DESCRIPTION: -+* This function receive data block from TWSI bus in 8bit granularity -+* into pBlock buffer. -+* first The function waits for interrupt flag to be active then -+* For each 8-bit data: -+* It clears the interrupt flag which allows the next data to be -+* received from TWSI bus. -+* The function waits for interrupt flag to be active, -+* and status reg is 0x50. -+* Then the function reads data from data register, and copies it to -+* the given buffer. -+* -+* INPUT: -+* chanNum - TWSI channel -+* blockSize - number of bytes to read. -+* -+* OUTPUT: -+* pBlock - Data block. -+* -+* RETURN: -+* MV_OK - if receive transaction completed succesfully, -+* MV_BAD_PARAM - if pBlock is NULL, -+* MV_FAIL otherwmise. -+* -+*******************************************************************************/ -+static MV_STATUS twsiDataReceive(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize) -+{ -+ MV_U32 timeout, temp, blockSizeRd = blockSize; -+ if(NULL == pBlock) -+ return MV_BAD_PARAM; -+ -+ /* wait for Int to be Set */ -+ timeout = 0; -+ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataReceive ERROR - Read Data int Time out .\n")) -+ return MV_TIMEOUT; -+ -+ while(blockSizeRd) -+ { -+ if(blockSizeRd == 1) -+ { -+ /* clear ack and Int flag */ -+ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); -+ temp &= ~(TWSI_CONTROL_ACK); -+ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp); -+ } -+ twsiIntFlgClr(chanNum); -+ /* wait for Int to be Set */ -+ timeout = 0; -+ while( (!twsiMainIntGet(chanNum)) && (timeout++ < TWSI_TIMEOUT_VALUE)); -+ -+ /* check for timeout */ -+ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataReceive ERROR - Read Data Int Time out .\n")) -+ return MV_TIMEOUT; -+ -+ /* check the status */ -+ temp = twsiStsGet(chanNum); -+ if((temp != TWSI_M_REC_RD_DATA_ACK_TRA) && (blockSizeRd !=1)) -+ { -+ mvOsPrintf("TWSI: twsiDataReceive ERROR - status %x in read trans \n",temp); -+ return MV_FAIL; -+ } -+ else if((temp != TWSI_M_REC_RD_DATA_ACK_NOT_TRA) && (blockSizeRd ==1)) -+ { -+ mvOsPrintf("TWSI: twsiDataReceive ERROR - status %x in Rd Terminate\n",temp); -+ return MV_FAIL; -+ } -+ -+ /* read the data*/ -+ *pBlock = (MV_U8)MV_REG_READ(TWSI_DATA_REG(chanNum)); -+ DB(mvOsPrintf("TWSI: twsiDataReceive place %d read %x \n",\ -+ blockSize - blockSizeRd,*pBlock)); -+ pBlock++; -+ blockSizeRd--; -+ } -+ -+ return MV_OK; -+} -+ -+ -+ -+/******************************************************************************* -+* twsiTargetOffsSet - Set TWST target offset on TWSI bus. -+* -+* DESCRIPTION: -+* The function support TWSI targets that have inside address space (for -+* example EEPROMs). The function: -+* 1) Convert the given offset into pBlock and size. -+* in case the offset should be set to a TWSI slave which support -+* more then 256 bytes offset, the offset setting will be done -+* in 2 transactions. -+* 2) Use twsiDataTransmit to place those on the bus. -+* -+* INPUT: -+* chanNum - TWSI channel -+* offset - offset to be set on the EEPROM device. -+* moreThen256 - whether the EEPROM device support more then 256 byte offset. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* MV_OK - if setting the offset completed succesfully. -+* MV_FAIL otherwmise. -+* -+*******************************************************************************/ -+static MV_STATUS twsiTargetOffsSet(MV_U8 chanNum, MV_U32 offset, MV_BOOL moreThen256) -+{ -+ MV_U8 offBlock[2]; -+ MV_U32 offSize; -+ -+ if(moreThen256 == MV_TRUE) -+ { -+ offBlock[0] = (offset >> 8) & 0xff; -+ offBlock[1] = offset & 0xff; -+ offSize = 2; -+ } -+ else -+ { -+ offBlock[0] = offset & 0xff; -+ offSize = 1; -+ } -+ DB(mvOsPrintf("TWSI: twsiTargetOffsSet offSize = %x addr1 = %x addr2 = %x\n",\ -+ offSize,offBlock[0],offBlock[1])); -+ return twsiDataTransmit(chanNum, offBlock, offSize); -+ -+} -+ -+/******************************************************************************* -+* mvTwsiRead - Read data block from a TWSI Slave. -+* -+* DESCRIPTION: -+* The function calls the following functions: -+* -) mvTwsiStartBitSet(); -+* if(EEPROM device) -+* -) mvTwsiAddrSet(w); -+* -) twsiTargetOffsSet(); -+* -) mvTwsiStartBitSet(); -+* -) mvTwsiAddrSet(r); -+* -) twsiDataReceive(); -+* -) mvTwsiStopBitSet(); -+* -+* INPUT: -+* chanNum - TWSI channel -+* pTwsiSlave - Twsi Slave structure. -+* blockSize - number of bytes to read. -+* -+* OUTPUT: -+* pBlock - Data block. -+* -+* RETURN: -+* MV_OK - if EEPROM read transaction completed succesfully, -+* MV_BAD_PARAM - if pBlock is NULL, -+* MV_FAIL otherwmise. -+* -+*******************************************************************************/ -+MV_STATUS mvTwsiRead(MV_U8 chanNum, MV_TWSI_SLAVE *pTwsiSlave, MV_U8 *pBlock, MV_U32 blockSize) -+{ -+ if((NULL == pBlock) || (NULL == pTwsiSlave)) -+ return MV_BAD_PARAM; -+ if(MV_OK != mvTwsiStartBitSet(chanNum)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ -+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiStartBitSet\n")); -+ -+ /* in case offset exsist (i.e. eeprom ) */ -+ if(MV_TRUE == pTwsiSlave->validOffset) -+ { -+ if(MV_OK != mvTwsiAddrSet(chanNum, &(pTwsiSlave->slaveAddr), MV_TWSI_WRITE)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiAddrSet\n")); -+ if(MV_OK != twsiTargetOffsSet(chanNum, pTwsiSlave->offset, pTwsiSlave->moreThen256)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after twsiTargetOffsSet\n")); -+ if(MV_OK != mvTwsiStartBitSet(chanNum)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiStartBitSet\n")); -+ } -+ if(MV_OK != mvTwsiAddrSet(chanNum, &(pTwsiSlave->slaveAddr), MV_TWSI_READ)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiAddrSet\n")); -+ if(MV_OK != twsiDataReceive(chanNum, pBlock, blockSize)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after twsiDataReceive\n")); -+ -+ if(MV_OK != mvTwsiStopBitSet(chanNum)) -+ { -+ return MV_FAIL; -+ } -+ -+ twsiAckBitSet(chanNum); -+ -+ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiStopBitSet\n")); -+ -+ return MV_OK; -+} -+ -+/******************************************************************************* -+* mvTwsiWrite - Write data block to a TWSI Slave. -+* -+* DESCRIPTION: -+* The function calls the following functions: -+* -) mvTwsiStartBitSet(); -+* -) mvTwsiAddrSet(); -+* -)if(EEPROM device) -+* -) twsiTargetOffsSet(); -+* -) twsiDataTransmit(); -+* -) mvTwsiStopBitSet(); -+* -+* INPUT: -+* chanNum - TWSI channel -+* eepromAddress - eeprom address. -+* blockSize - number of bytes to write. -+* pBlock - Data block. -+* -+* OUTPUT: -+* None -+* -+* RETURN: -+* MV_OK - if EEPROM read transaction completed succesfully. -+* MV_BAD_PARAM - if pBlock is NULL, -+* MV_FAIL otherwmise. -+* -+* NOTE: Part of the EEPROM, required that the offset will be aligned to the -+* max write burst supported. -+*******************************************************************************/ -+MV_STATUS mvTwsiWrite(MV_U8 chanNum, MV_TWSI_SLAVE *pTwsiSlave, MV_U8 *pBlock, MV_U32 blockSize) -+{ -+ if((NULL == pBlock) || (NULL == pTwsiSlave)) -+ return MV_BAD_PARAM; -+ -+ if(MV_OK != mvTwsiStartBitSet(chanNum)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ -+ DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after mvTwsiStartBitSet\n")); -+ if(MV_OK != mvTwsiAddrSet(chanNum, &(pTwsiSlave->slaveAddr), MV_TWSI_WRITE)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI :mvTwsiEepromWrite after mvTwsiAddrSet\n")); -+ -+ /* in case offset exsist (i.e. eeprom ) */ -+ if(MV_TRUE == pTwsiSlave->validOffset) -+ { -+ if(MV_OK != twsiTargetOffsSet(chanNum, pTwsiSlave->offset, pTwsiSlave->moreThen256)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after twsiTargetOffsSet\n")); -+ } -+ if(MV_OK != twsiDataTransmit(chanNum, pBlock, blockSize)) -+ { -+ mvTwsiStopBitSet(chanNum); -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after twsiDataTransmit\n")); -+ if(MV_OK != mvTwsiStopBitSet(chanNum)) -+ { -+ return MV_FAIL; -+ } -+ DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after mvTwsiStopBitSet\n")); -+ -+ return MV_OK; -+} -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,121 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+#ifndef __INCmvTwsiH -+#define __INCmvTwsiH -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* need to update this includes */ -+#include "twsi/mvTwsiSpec.h" -+#include "ctrlEnv/mvCtrlEnvLib.h" -+ -+ -+/* The TWSI interface supports both 7-bit and 10-bit addressing. */ -+/* This enumerator describes addressing type. */ -+typedef enum _mvTwsiAddrType -+{ -+ ADDR7_BIT, /* 7 bit address */ -+ ADDR10_BIT /* 10 bit address */ -+}MV_TWSI_ADDR_TYPE; -+ -+/* This structure describes TWSI address. */ -+typedef struct _mvTwsiAddr -+{ -+ MV_U32 address; /* address */ -+ MV_TWSI_ADDR_TYPE type; /* Address type */ -+}MV_TWSI_ADDR; -+ -+/* This structure describes a TWSI slave. */ -+typedef struct _mvTwsiSlave -+{ -+ MV_TWSI_ADDR slaveAddr; -+ MV_BOOL validOffset; /* whether the slave has offset (i.e. Eeprom etc.) */ -+ MV_U32 offset; /* offset in the slave. */ -+ MV_BOOL moreThen256; /* whether the ofset is bigger then 256 */ -+}MV_TWSI_SLAVE; -+ -+/* This enumerator describes TWSI protocol commands. */ -+typedef enum _mvTwsiCmd -+{ -+ MV_TWSI_WRITE, /* TWSI write command - 0 according to spec */ -+ MV_TWSI_READ /* TWSI read command - 1 according to spec */ -+}MV_TWSI_CMD; -+ -+MV_STATUS mvTwsiStartBitSet(MV_U8 chanNum); -+MV_STATUS mvTwsiStopBitSet(MV_U8 chanNum); -+MV_STATUS mvTwsiAddrSet(MV_U8 chanNum, MV_TWSI_ADDR *twsiAddr, MV_TWSI_CMD command); -+ -+MV_U32 mvTwsiInit(MV_U8 chanNum, MV_KHZ frequancy, MV_U32 Tclk, MV_TWSI_ADDR *twsiAddr, MV_BOOL generalCallEnable); -+MV_STATUS mvTwsiRead (MV_U8 chanNum, MV_TWSI_SLAVE *twsiSlave, MV_U8 *pBlock, MV_U32 blockSize); -+MV_STATUS mvTwsiWrite(MV_U8 chanNum, MV_TWSI_SLAVE *twsiSlave, MV_U8 *pBlock, MV_U32 blockSize); -+ -+ -+#ifdef __cplusplus -+} -+#endif /* __cplusplus */ -+ -+#endif /* __INCmvTwsiH */ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiEeprom.S linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiEeprom.S ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiEeprom.S 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiEeprom.S 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,457 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+ -+ -+/* includes */ -+#define MV_ASMLANGUAGE -+#include "ctrlEnv/mvCtrlEnvSpec.h" -+#include "boardEnv/mvBoardEnvSpec.h" -+#include "mvOsAsm.h" -+#include "mvTwsiSpec.h" -+#include "mvSysHwConfig.h" -+#include "ctrlEnv/sys/mvCpuIfRegs.h" -+#include "mvCommon.h" -+ -+#define I2C_CH MV_BOARD_DIMM_I2C_CHANNEL -+ -+/* defines */ -+/* defines */ -+ -+ -+ .data -+ .global _i2cInit -+ .global _i2cRead -+ -+ .text -+ -+/******************************************************************************* -+* _i2cInit - Initialize TWSI interface -+* -+* DESCRIPTION: -+* The function performs TWSI interface initialization. It resets the -+* TWSI state machine and initialize its clock to 100KHz assuming Tclock -+* of 133MHz. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+_i2cInit: -+ mov r9, LR /* Save link register */ -+ mov r0, #0 /* Make sure r0 is zero */ -+ -+ /* Reset the i2c Mechanism first */ -+ MV_REG_WRITE_ASM (r0, r1, TWSI_SOFT_RESET_REG(I2C_CH)) -+ -+ bl _twsiDelay -+ bl _twsiDelay -+ -+ /* Initializing the I2C mechanism. Assuming Tclock frequency */ -+ /* of 166MHz. The I2C frequency in that case will be 100KHz. */ -+ /* For this settings, M = 9 and N = 3. Set the baud-rate with the */ -+ /* value of 0x2b (freq of ==> 100KHz */ -+ /* see spec for more details about the calculation of this value) */ -+ mov r6, #(9 << 3 | 3) -+ MV_REG_WRITE_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) -+ -+ /* Enable the I2C master */ -+ /* Enable TWSI interrupt in main mask reg */ -+ mov r6, #0xC4 -+ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) -+ -+ /* Let the slow TWSI machine get used to the idea that it is enabled */ -+ bl _twsiDelay -+ -+ -+ mov PC, r9 /* r9 is saved link register */ -+ -+/******************************************************************************* -+* _twsiDelay - Perform delay. -+* -+* DESCRIPTION: -+* The function performs a delay to enable TWSI logic to stable. -+* -+* INPUT: -+* None. -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* None. -+* -+*******************************************************************************/ -+_twsiDelay: -+ mov r10, #0x100000 /*was 0x400*/ -+ -+_twsiDelayLoop: -+ subs r10, r10, #1 -+ bne _twsiDelayLoop -+ -+ mov PC, LR -+ -+/******************************************************************************* -+* _i2cRead - Read byte from I2C EEPROM device. -+* -+* DESCRIPTION: -+* The function returns a byte from I2C EEPROM device. -+* The EEPROM device is 7-bit address type. -+* -+* INPUT: -+* r4 has the DIMM0 base address with shift 1 bit to the left -+* r7 has the EEPROM offset -+* -+* OUTPUT: -+* None. -+* -+* RETURN: -+* r4 returns '0' if address can not be read. -+* r7 has byte value in case read is successful. -+* -+*******************************************************************************/ -+_i2cRead: -+ mov r9, LR /* Save link register */ -+ -+ /* Transmit the device address and desired offset within the EEPROM. */ -+ -+ /* Generate Start Bit */ -+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) -+ orr r6, r6, #TWSI_CONTROL_START_BIT -+ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) -+ -+ /* Wait for the interrupt flag (bit3) to be set */ -+ mov r10, #0x50000 -+loop_1: -+ subs r10, r10, #1 -+ beq loop_1_timeout -+#ifdef MV78XX0 -+ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) -+ tst r6, #BIT2 -+#else -+ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) -+ tst r6, #BIT5 -+#endif -+ beq loop_1 -+ -+loop_1_timeout: -+ -+ /* Wait for the start bit to be reset by HW */ -+ mov r10, #0x50000 -+loop_2: -+ subs r10, r10, #1 -+ beq loop_2_timeout -+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) -+ tst r6, #TWSI_CONTROL_START_BIT -+ bne loop_2 -+ -+loop_2_timeout: -+ -+ /* Wait for the status TWSI_START_CONDITION_TRA = 0x8 */ -+ mov r10, #0x50000 -+loop_3: -+ subs r10, r10, #1 -+ beq loop_3_timeout -+ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) -+ cmp r6, #0x08 -+ bne loop_3 -+ -+loop_3_timeout: -+ -+ /* writing the address of (DIMM0/1 << 1) with write indication */ -+ mov r6, r4, LSL #1 /* Write operation address bit 0 must be 0 */ -+ MV_REG_WRITE_ASM (r6, r1, TWSI_DATA_REG(I2C_CH)) -+ -+ bl _twsiDelay -+ /* Clear the interrupt flag */ -+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) -+ bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET -+ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) -+ bl _twsiDelay -+ -+ /* Waiting for the interrupt flag to be set which means that the -+ address has been transmitted */ -+loop_4: -+#ifdef MV78XX0 -+ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) -+ tst r6, #BIT2 -+#else -+ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) -+ tst r6, #BIT5 -+#endif -+ beq loop_4 /* if tst = 0, then the bit is not set yet */ -+ -+ /* Wait for status TWSI_ADDR_PLUS_WRITE_BIT_TRA_ACK_REC = 0x18 */ -+ mov r10, #0x50000 /* Set r10 to 0x50000 =~ 328,000 */ -+ -+loop_5: -+ subs r10, r10, #1 /* timeout count down */ -+ bne testStatus -+ mov r4, #0 /* r4 = 0 -> operation failed */ -+ b exit_i2cRead /* Exit if timeout (No DIMM) */ -+ -+testStatus: -+ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) -+ cmp r6, #0x18 -+ bne loop_5 -+ -+ -+ /* check if the offset is bigger than 256 byte*/ -+ tst r7, #0x80000000 -+ bne great_than_256 -+ -+ /* Write the offset to be read from the DIMM EEPROM */ -+ MV_REG_WRITE_ASM (r7, r1, TWSI_DATA_REG(I2C_CH)) -+ -+ b after_offset -+ -+great_than_256: -+ mov r10, r7, LSR #8 -+ and r10, r10, #0xff -+ /* Write the offset0 to be read from the EEPROM */ -+ MV_REG_WRITE_ASM (r10, r1, TWSI_DATA_REG(I2C_CH)) -+ -+ /* Clear the interrupt flag ==> signaling that the address can now -+ be transmited */ -+ -+ bl _twsiDelay -+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) -+ bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET -+ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) -+ bl _twsiDelay -+ -+ /* Wait for the interrupt to be set again ==> address has transmited */ -+loop_6_1: -+#ifdef MV78XX0 -+ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) -+ tst r6, #BIT2 -+#else -+ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) -+ tst r6, #BIT5 -+#endif -+ beq loop_6_1 -+ -+ /* Wait for status TWSI_MAS_TRAN_DATA_BYTE_ACK_REC = 0x28 */ -+loop_7_1: -+ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) -+ cmp r6, #0x28 -+ bne loop_7_1 -+ -+ -+ mov r10, r7 -+ and r10, r10, #0xff -+ /* Write the offset1 to be read from the EEPROM */ -+ MV_REG_WRITE_ASM (r10, r1, TWSI_DATA_REG(I2C_CH)) -+ -+ -+ -+after_offset: -+ -+ /* Clear the interrupt flag ==> signaling that the address can now -+ be transmited */ -+ -+ bl _twsiDelay -+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) -+ bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET -+ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) -+ bl _twsiDelay -+ -+ /* Wait for the interrupt to be set again ==> address has transmited */ -+loop_6: -+#ifdef MV78XX0 -+ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) -+ tst r6, #BIT2 -+#else -+ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) -+ tst r6, #BIT5 -+#endif -+ beq loop_6 -+ -+ /* Wait for status TWSI_MAS_TRAN_DATA_BYTE_ACK_REC = 0x28 */ -+loop_7: -+ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) -+ cmp r6, #0x28 -+ bne loop_7 -+ -+ /* Retransmit the device address with read indication to get the data */ -+ -+ /* generate a repeated start bit */ -+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) -+ orr r6, r6, #TWSI_CONTROL_START_BIT -+ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) -+ -+ -+ /* Clear the interrupt flag ==> the start bit will be transmitted. */ -+ bl _twsiDelay -+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) -+ bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET -+ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) -+ bl _twsiDelay -+ -+ /* Wait for the interrupt flag (bit3) to be set */ -+loop_9: -+#ifdef MV78XX0 -+ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) -+ tst r6, #BIT2 -+#else -+ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) -+ tst r6, #BIT5 -+#endif -+ beq loop_9 -+ -+ /* Wait for the start bit to be reset by HW */ -+loop_8: -+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) -+ tst r6, #TWSI_CONTROL_START_BIT -+ bne loop_8 -+ -+ /* Wait for status TWSI_REPEATED_START_CONDITION_TRA = 0x10 */ -+loop_10: -+ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) -+ cmp r6, #0x10 -+ bne loop_10 -+ -+ /* Writing the address of (DIMM0<<1) with read indication (bit0 is 1) */ -+ mov r6, r4, LSL #1 -+ orr r6, r6, #1 /* Read operation address bit 0 must be 1 */ -+ MV_REG_WRITE_ASM (r6, r1, TWSI_DATA_REG(I2C_CH)) -+ -+ /* Clear the interrupt flag ==> the address will be transmitted */ -+ bl _twsiDelay -+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) -+ bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET -+ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) -+ bl _twsiDelay -+ -+ /* Wait for the interrupt flag (bit3) to be set as a result of -+ transmitting the address. */ -+loop_11: -+#ifdef MV78XX0 -+ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) -+ tst r6, #BIT2 -+#else -+ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) -+ tst r6, #BIT5 -+#endif -+ beq loop_11 -+ -+ /* Wait for status TWSI_ADDR_PLUS_READ_BIT_TRA_ACK_REC = 0x40 */ -+loop_12: -+ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) -+ cmp r6, #0x40 -+ bne loop_12 -+ -+ /* Clear the interrupt flag and the Acknoledge bit */ -+ bl _twsiDelay -+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) -+ bic r6, r6, #(TWSI_CONTROL_INT_FLAG_SET | TWSI_CONTROL_ACK) -+ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) -+ bl _twsiDelay -+ -+ /* Wait for the interrupt flag (bit3) to be set */ -+loop_14: -+#ifdef MV78XX0 -+ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) -+ tst r6, #BIT2 -+#else -+ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) -+ tst r6, #BIT5 -+#endif -+ beq loop_14 -+ -+ /* Wait for status TWSI_MAS_REC_READ_DATA_ACK_NOT_TRA = 0x58 */ -+loop_15: -+ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) -+ cmp r6, #0x58 -+ bne loop_15 -+ -+ /* Store the data in r7. */ -+ MV_REG_READ_ASM (r7, r1, TWSI_DATA_REG(I2C_CH)) -+ -+ /* Generate stop bit */ -+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) -+ orr r6, r6, #TWSI_CONTROL_STOP_BIT -+ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) -+ -+ -+ /* Clear the interrupt flag */ -+ bl _twsiDelay -+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) -+ bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET -+ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) -+ bl _twsiDelay -+ -+ /* Wait for the stop bit to be reset by HW */ -+loop_16: -+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) -+ tst r6, #TWSI_CONTROL_INT_FLAG_SET -+ bne loop_16 -+ -+exit_i2cRead: -+ mov PC, r9 /* r9 is saved link register */ -diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiSpec.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiSpec.h ---- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiSpec.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiSpec.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,160 @@ -+/******************************************************************************* -+Copyright (C) Marvell International Ltd. and its affiliates -+ -+This software file (the "File") is owned and distributed by Marvell -+International Ltd. and/or its affiliates ("Marvell") under the following -+alternative licensing terms. Once you have made an election to distribute the -+File under one of the following license alternatives, please (i) delete this -+introductory statement regarding license alternatives, (ii) delete the two -+license alternatives that you have not elected to use and (iii) preserve the -+Marvell copyright notice above. -+ -+******************************************************************************** -+Marvell Commercial License Option -+ -+If you received this File from Marvell and you have entered into a commercial -+license agreement (a "Commercial License") with Marvell, the File is licensed -+to you under the terms of the applicable Commercial License. -+ -+******************************************************************************** -+Marvell GPL License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File in accordance with the terms and conditions of the General -+Public License Version 2, June 1991 (the "GPL License"), a copy of which is -+available along with the File in the license.txt file or by writing to the Free -+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. -+ -+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -+DISCLAIMED. The GPL License provides additional details about this warranty -+disclaimer. -+******************************************************************************** -+Marvell BSD License Option -+ -+If you received this File from Marvell, you may opt to use, redistribute and/or -+modify this File under the following licensing terms. -+Redistribution and use in source and binary forms, with or without modification, -+are permitted provided that the following conditions are met: -+ -+ * Redistributions of source code must retain the above copyright notice, -+ this list of conditions and the following disclaimer. -+ -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ -+ * Neither the name of Marvell nor the names of its contributors may be -+ used to endorse or promote products derived from this software without -+ specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ -+*******************************************************************************/ -+/****************************************/ -+/* TWSI Registers */ -+/****************************************/ -+#ifndef __INCmvTwsiSpech -+#define __INCmvTwsiSpech -+ -+#ifdef __cplusplus -+extern "C" { -+#endif /* __cplusplus */ -+ -+/* defines */ -+#define TWSI_SLAVE_ADDR_REG(chanNum) (TWSI_SLAVE_BASE(chanNum)+ 0x00) -+ -+#define TWSI_SLAVE_ADDR_GCE_ENA BIT0 -+#define TWSI_SLAVE_ADDR_7BIT_OFFS 0x1 -+#define TWSI_SLAVE_ADDR_7BIT_MASK (0xFF << TWSI_SLAVE_ADDR_7BIT_OFFS) -+#define TWSI_SLAVE_ADDR_10BIT_OFFS 0x7 -+#define TWSI_SLAVE_ADDR_10BIT_MASK 0x300 -+#define TWSI_SLAVE_ADDR_10BIT_CONST 0xF0 -+ -+ -+#define TWSI_EXTENDED_SLAVE_ADDR_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x10) -+#define TWSI_EXTENDED_SLAVE_OFFS 0 -+#define TWSI_EXTENDED_SLAVE_MASK (0xFF << TWSI_EXTENDED_SLAVE_OFFS) -+ -+ -+#define TWSI_DATA_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x04) -+#define TWSI_DATA_COMMAND_OFFS 0x0 -+#define TWSI_DATA_COMMAND_MASK (0x1 << TWSI_DATA_COMMAND_OFFS) -+#define TWSI_DATA_COMMAND_WR (0x1 << TWSI_DATA_COMMAND_OFFS) -+#define TWSI_DATA_COMMAND_RD (0x0 << TWSI_DATA_COMMAND_OFFS) -+#define TWSI_DATA_ADDR_7BIT_OFFS 0x1 -+#define TWSI_DATA_ADDR_7BIT_MASK (0xFF << TWSI_DATA_ADDR_7BIT_OFFS) -+#define TWSI_DATA_ADDR_10BIT_OFFS 0x7 -+#define TWSI_DATA_ADDR_10BIT_MASK 0x300 -+#define TWSI_DATA_ADDR_10BIT_CONST 0xF0 -+ -+ -+#define TWSI_CONTROL_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x08) -+#define TWSI_CONTROL_ACK BIT2 -+#define TWSI_CONTROL_INT_FLAG_SET BIT3 -+#define TWSI_CONTROL_STOP_BIT BIT4 -+#define TWSI_CONTROL_START_BIT BIT5 -+#define TWSI_CONTROL_ENA BIT6 -+#define TWSI_CONTROL_INT_ENA BIT7 -+ -+ -+#define TWSI_STATUS_BAUDE_RATE_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x0c) -+#define TWSI_BAUD_RATE_N_OFFS 0 -+#define TWSI_BAUD_RATE_N_MASK (0x7 << TWSI_BAUD_RATE_N_OFFS) -+#define TWSI_BAUD_RATE_M_OFFS 3 -+#define TWSI_BAUD_RATE_M_MASK (0xF << TWSI_BAUD_RATE_M_OFFS) -+ -+#define TWSI_SOFT_RESET_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x1c) -+ -+/* defines */ -+#define TWSI_TIMEOUT_VALUE 0x500 -+ -+/* TWSI status codes */ -+#define TWSI_BUS_ERROR 0x00 -+#define TWSI_START_CON_TRA 0x08 -+#define TWSI_REPEATED_START_CON_TRA 0x10 -+#define TWSI_AD_PLS_WR_BIT_TRA_ACK_REC 0x18 -+#define TWSI_AD_PLS_WR_BIT_TRA_ACK_NOT_REC 0x20 -+#define TWSI_M_TRAN_DATA_BYTE_ACK_REC 0x28 -+#define TWSI_M_TRAN_DATA_BYTE_ACK_NOT_REC 0x30 -+#define TWSI_M_LOST_ARB_DUR_AD_OR_DATA_TRA 0x38 -+#define TWSI_AD_PLS_RD_BIT_TRA_ACK_REC 0x40 -+#define TWSI_AD_PLS_RD_BIT_TRA_ACK_NOT_REC 0x48 -+#define TWSI_M_REC_RD_DATA_ACK_TRA 0x50 -+#define TWSI_M_REC_RD_DATA_ACK_NOT_TRA 0x58 -+#define TWSI_SLA_REC_AD_PLS_WR_BIT_ACK_TRA 0x60 -+#define TWSI_M_LOST_ARB_DUR_AD_TRA_AD_IS_TRGT_TO_SLA_ACK_TRA_W 0x68 -+#define TWSI_GNL_CALL_REC_ACK_TRA 0x70 -+#define TWSI_M_LOST_ARB_DUR_AD_TRA_GNL_CALL_AD_REC_ACK_TRA 0x78 -+#define TWSI_SLA_REC_WR_DATA_AF_REC_SLA_AD_ACK_TRAN 0x80 -+#define TWSI_SLA_REC_WR_DATA_AF_REC_SLA_AD_ACK_NOT_TRAN 0x88 -+#define TWSI_SLA_REC_WR_DATA_AF_REC_GNL_CALL_ACK_TRAN 0x90 -+#define TWSI_SLA_REC_WR_DATA_AF_REC_GNL_CALL_ACK_NOT_TRAN 0x98 -+#define TWSI_SLA_REC_STOP_OR_REPEATED_STRT_CON 0xA0 -+#define TWSI_SLA_REC_AD_PLS_RD_BIT_ACK_TRA 0xA8 -+#define TWSI_M_LOST_ARB_DUR_AD_TRA_AD_IS_TRGT_TO_SLA_ACK_TRA_R 0xB0 -+#define TWSI_SLA_TRA_RD_DATA_ACK_REC 0xB8 -+#define TWSI_SLA_TRA_RD_DATA_ACK_NOT_REC 0xC0 -+#define TWSI_SLA_TRA_LAST_RD_DATA_ACK_REC 0xC8 -+#define TWSI_SEC_AD_PLS_WR_BIT_TRA_ACK_REC 0xD0 -+#define TWSI_SEC_AD_PLS_WR_BIT_TRA_ACK_NOT_REC 0xD8 -+#define TWSI_SEC_AD_PLS_RD_BIT_TRA_ACK_REC 0xE0 -+#define TWSI_SEC_AD_PLS_RD_BIT_TRA_ACK_NOT_REC 0xE8 -+#define TWSI_NO_REL_STS_INT_FLAG_IS_KEPT_0 0xF8 -+ -+ -+#ifdef __cplusplus -+} -+#endif /* __cplusplus */ -+ -+#endif /* __INCmvTwsiSpech */ -diff -Nur linux-3.0.4.orig/crypto/ocf/ocf-bench.c linux-3.0.4/crypto/ocf/ocf-bench.c ---- linux-3.0.4.orig/crypto/ocf/ocf-bench.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/ocf-bench.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,514 @@ -+/* -+ * A loadable module that benchmarks the OCF crypto speed from kernel space. -+ * -+ * Copyright (C) 2004-2010 David McCullough -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * ALTERNATIVELY, provided that this notice is retained in full, this product -+ * may be distributed under the terms of the GNU General Public License (GPL), -+ * in which case the provisions of the GPL apply INSTEAD OF those given above. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ */ -+ -+ -+#include -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#ifdef I_HAVE_AN_XSCALE_WITH_INTEL_SDK -+#define BENCH_IXP_ACCESS_LIB 1 -+#endif -+#ifdef BENCH_IXP_ACCESS_LIB -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#endif -+ -+/* -+ * support for access lib version 1.4 -+ */ -+#ifndef IX_MBUF_PRIV -+#define IX_MBUF_PRIV(x) ((x)->priv) -+#endif -+ -+/* -+ * the number of simultaneously active requests -+ */ -+static int request_q_len = 40; -+module_param(request_q_len, int, 0); -+MODULE_PARM_DESC(request_q_len, "Number of outstanding requests"); -+ -+/* -+ * how many requests we want to have processed -+ */ -+static int request_num = 1024; -+module_param(request_num, int, 0); -+MODULE_PARM_DESC(request_num, "run for at least this many requests"); -+ -+/* -+ * the size of each request -+ */ -+static int request_size = 1488; -+module_param(request_size, int, 0); -+MODULE_PARM_DESC(request_size, "size of each request"); -+ -+/* -+ * OCF batching of requests -+ */ -+static int request_batch = 1; -+module_param(request_batch, int, 0); -+MODULE_PARM_DESC(request_batch, "enable OCF request batching"); -+ -+/* -+ * OCF immediate callback on completion -+ */ -+static int request_cbimm = 1; -+module_param(request_cbimm, int, 0); -+MODULE_PARM_DESC(request_cbimm, "enable OCF immediate callback on completion"); -+ -+/* -+ * a structure for each request -+ */ -+typedef struct { -+ struct work_struct work; -+#ifdef BENCH_IXP_ACCESS_LIB -+ IX_MBUF mbuf; -+#endif -+ unsigned char *buffer; -+} request_t; -+ -+static request_t *requests; -+ -+static spinlock_t ocfbench_counter_lock; -+static int outstanding; -+static int total; -+ -+/*************************************************************************/ -+/* -+ * OCF benchmark routines -+ */ -+ -+static uint64_t ocf_cryptoid; -+static unsigned long jstart, jstop; -+ -+static int ocf_init(void); -+static int ocf_cb(struct cryptop *crp); -+static void ocf_request(void *arg); -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void ocf_request_wq(struct work_struct *work); -+#endif -+ -+static int -+ocf_init(void) -+{ -+ int error; -+ struct cryptoini crie, cria; -+ struct cryptodesc crda, crde; -+ -+ memset(&crie, 0, sizeof(crie)); -+ memset(&cria, 0, sizeof(cria)); -+ memset(&crde, 0, sizeof(crde)); -+ memset(&crda, 0, sizeof(crda)); -+ -+ cria.cri_alg = CRYPTO_SHA1_HMAC; -+ cria.cri_klen = 20 * 8; -+ cria.cri_key = "0123456789abcdefghij"; -+ -+ //crie.cri_alg = CRYPTO_3DES_CBC; -+ crie.cri_alg = CRYPTO_AES_CBC; -+ crie.cri_klen = 24 * 8; -+ crie.cri_key = "0123456789abcdefghijklmn"; -+ -+ crie.cri_next = &cria; -+ -+ error = crypto_newsession(&ocf_cryptoid, &crie, -+ CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE); -+ if (error) { -+ printk("crypto_newsession failed %d\n", error); -+ return -1; -+ } -+ return 0; -+} -+ -+static int -+ocf_cb(struct cryptop *crp) -+{ -+ request_t *r = (request_t *) crp->crp_opaque; -+ unsigned long flags; -+ -+ if (crp->crp_etype) -+ printk("Error in OCF processing: %d\n", crp->crp_etype); -+ crypto_freereq(crp); -+ crp = NULL; -+ -+ /* do all requests but take at least 1 second */ -+ spin_lock_irqsave(&ocfbench_counter_lock, flags); -+ total++; -+ if (total > request_num && jstart + HZ < jiffies) { -+ outstanding--; -+ spin_unlock_irqrestore(&ocfbench_counter_lock, flags); -+ return 0; -+ } -+ spin_unlock_irqrestore(&ocfbench_counter_lock, flags); -+ -+ schedule_work(&r->work); -+ return 0; -+} -+ -+ -+static void -+ocf_request(void *arg) -+{ -+ request_t *r = arg; -+ struct cryptop *crp = crypto_getreq(2); -+ struct cryptodesc *crde, *crda; -+ unsigned long flags; -+ -+ if (!crp) { -+ spin_lock_irqsave(&ocfbench_counter_lock, flags); -+ outstanding--; -+ spin_unlock_irqrestore(&ocfbench_counter_lock, flags); -+ return; -+ } -+ -+ crde = crp->crp_desc; -+ crda = crde->crd_next; -+ -+ crda->crd_skip = 0; -+ crda->crd_flags = 0; -+ crda->crd_len = request_size; -+ crda->crd_inject = request_size; -+ crda->crd_alg = CRYPTO_SHA1_HMAC; -+ crda->crd_key = "0123456789abcdefghij"; -+ crda->crd_klen = 20 * 8; -+ -+ crde->crd_skip = 0; -+ crde->crd_flags = CRD_F_IV_EXPLICIT | CRD_F_ENCRYPT; -+ crde->crd_len = request_size; -+ crde->crd_inject = request_size; -+ //crde->crd_alg = CRYPTO_3DES_CBC; -+ crde->crd_alg = CRYPTO_AES_CBC; -+ crde->crd_key = "0123456789abcdefghijklmn"; -+ crde->crd_klen = 24 * 8; -+ -+ crp->crp_ilen = request_size + 64; -+ crp->crp_flags = 0; -+ if (request_batch) -+ crp->crp_flags |= CRYPTO_F_BATCH; -+ if (request_cbimm) -+ crp->crp_flags |= CRYPTO_F_CBIMM; -+ crp->crp_buf = (caddr_t) r->buffer; -+ crp->crp_callback = ocf_cb; -+ crp->crp_sid = ocf_cryptoid; -+ crp->crp_opaque = (caddr_t) r; -+ crypto_dispatch(crp); -+} -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void -+ocf_request_wq(struct work_struct *work) -+{ -+ request_t *r = container_of(work, request_t, work); -+ ocf_request(r); -+} -+#endif -+ -+static void -+ocf_done(void) -+{ -+ crypto_freesession(ocf_cryptoid); -+} -+ -+/*************************************************************************/ -+#ifdef BENCH_IXP_ACCESS_LIB -+/*************************************************************************/ -+/* -+ * CryptoAcc benchmark routines -+ */ -+ -+static IxCryptoAccCtx ixp_ctx; -+static UINT32 ixp_ctx_id; -+static IX_MBUF ixp_pri; -+static IX_MBUF ixp_sec; -+static int ixp_registered = 0; -+ -+static void ixp_register_cb(UINT32 ctx_id, IX_MBUF *bufp, -+ IxCryptoAccStatus status); -+static void ixp_perform_cb(UINT32 ctx_id, IX_MBUF *sbufp, IX_MBUF *dbufp, -+ IxCryptoAccStatus status); -+static void ixp_request(void *arg); -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void ixp_request_wq(struct work_struct *work); -+#endif -+ -+static int -+ixp_init(void) -+{ -+ IxCryptoAccStatus status; -+ -+ ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_3DES; -+ ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; -+ ixp_ctx.cipherCtx.cipherKeyLen = 24; -+ ixp_ctx.cipherCtx.cipherBlockLen = IX_CRYPTO_ACC_DES_BLOCK_64; -+ ixp_ctx.cipherCtx.cipherInitialVectorLen = IX_CRYPTO_ACC_DES_IV_64; -+ memcpy(ixp_ctx.cipherCtx.key.cipherKey, "0123456789abcdefghijklmn", 24); -+ -+ ixp_ctx.authCtx.authAlgo = IX_CRYPTO_ACC_AUTH_SHA1; -+ ixp_ctx.authCtx.authDigestLen = 12; -+ ixp_ctx.authCtx.aadLen = 0; -+ ixp_ctx.authCtx.authKeyLen = 20; -+ memcpy(ixp_ctx.authCtx.key.authKey, "0123456789abcdefghij", 20); -+ -+ ixp_ctx.useDifferentSrcAndDestMbufs = 0; -+ ixp_ctx.operation = IX_CRYPTO_ACC_OP_ENCRYPT_AUTH ; -+ -+ IX_MBUF_MLEN(&ixp_pri) = IX_MBUF_PKT_LEN(&ixp_pri) = 128; -+ IX_MBUF_MDATA(&ixp_pri) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); -+ IX_MBUF_MLEN(&ixp_sec) = IX_MBUF_PKT_LEN(&ixp_sec) = 128; -+ IX_MBUF_MDATA(&ixp_sec) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); -+ -+ status = ixCryptoAccCtxRegister(&ixp_ctx, &ixp_pri, &ixp_sec, -+ ixp_register_cb, ixp_perform_cb, &ixp_ctx_id); -+ -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) { -+ while (!ixp_registered) -+ schedule(); -+ return ixp_registered < 0 ? -1 : 0; -+ } -+ -+ printk("ixp: ixCryptoAccCtxRegister failed %d\n", status); -+ return -1; -+} -+ -+static void -+ixp_register_cb(UINT32 ctx_id, IX_MBUF *bufp, IxCryptoAccStatus status) -+{ -+ if (bufp) { -+ IX_MBUF_MLEN(bufp) = IX_MBUF_PKT_LEN(bufp) = 0; -+ kfree(IX_MBUF_MDATA(bufp)); -+ IX_MBUF_MDATA(bufp) = NULL; -+ } -+ -+ if (IX_CRYPTO_ACC_STATUS_WAIT == status) -+ return; -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) -+ ixp_registered = 1; -+ else -+ ixp_registered = -1; -+} -+ -+static void -+ixp_perform_cb( -+ UINT32 ctx_id, -+ IX_MBUF *sbufp, -+ IX_MBUF *dbufp, -+ IxCryptoAccStatus status) -+{ -+ request_t *r = NULL; -+ unsigned long flags; -+ -+ /* do all requests but take at least 1 second */ -+ spin_lock_irqsave(&ocfbench_counter_lock, flags); -+ total++; -+ if (total > request_num && jstart + HZ < jiffies) { -+ outstanding--; -+ spin_unlock_irqrestore(&ocfbench_counter_lock, flags); -+ return; -+ } -+ -+ if (!sbufp || !(r = IX_MBUF_PRIV(sbufp))) { -+ printk("crappo %p %p\n", sbufp, r); -+ outstanding--; -+ spin_unlock_irqrestore(&ocfbench_counter_lock, flags); -+ return; -+ } -+ spin_unlock_irqrestore(&ocfbench_counter_lock, flags); -+ -+ schedule_work(&r->work); -+} -+ -+static void -+ixp_request(void *arg) -+{ -+ request_t *r = arg; -+ IxCryptoAccStatus status; -+ unsigned long flags; -+ -+ memset(&r->mbuf, 0, sizeof(r->mbuf)); -+ IX_MBUF_MLEN(&r->mbuf) = IX_MBUF_PKT_LEN(&r->mbuf) = request_size + 64; -+ IX_MBUF_MDATA(&r->mbuf) = r->buffer; -+ IX_MBUF_PRIV(&r->mbuf) = r; -+ status = ixCryptoAccAuthCryptPerform(ixp_ctx_id, &r->mbuf, NULL, -+ 0, request_size, 0, request_size, request_size, r->buffer); -+ if (IX_CRYPTO_ACC_STATUS_SUCCESS != status) { -+ printk("status1 = %d\n", status); -+ spin_lock_irqsave(&ocfbench_counter_lock, flags); -+ outstanding--; -+ spin_unlock_irqrestore(&ocfbench_counter_lock, flags); -+ return; -+ } -+ return; -+} -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+static void -+ixp_request_wq(struct work_struct *work) -+{ -+ request_t *r = container_of(work, request_t, work); -+ ixp_request(r); -+} -+#endif -+ -+static void -+ixp_done(void) -+{ -+ /* we should free the session here but I am lazy :-) */ -+} -+ -+/*************************************************************************/ -+#endif /* BENCH_IXP_ACCESS_LIB */ -+/*************************************************************************/ -+ -+int -+ocfbench_init(void) -+{ -+ int i; -+ unsigned long mbps; -+ unsigned long flags; -+ -+ printk("Crypto Speed tests\n"); -+ -+ requests = kmalloc(sizeof(request_t) * request_q_len, GFP_KERNEL); -+ if (!requests) { -+ printk("malloc failed\n"); -+ return -EINVAL; -+ } -+ -+ for (i = 0; i < request_q_len; i++) { -+ /* +64 for return data */ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ INIT_WORK(&requests[i].work, ocf_request_wq); -+#else -+ INIT_WORK(&requests[i].work, ocf_request, &requests[i]); -+#endif -+ requests[i].buffer = kmalloc(request_size + 128, GFP_DMA); -+ if (!requests[i].buffer) { -+ printk("malloc failed\n"); -+ return -EINVAL; -+ } -+ memset(requests[i].buffer, '0' + i, request_size + 128); -+ } -+ -+ /* -+ * OCF benchmark -+ */ -+ printk("OCF: testing ...\n"); -+ if (ocf_init() == -1) -+ return -EINVAL; -+ -+ spin_lock_init(&ocfbench_counter_lock); -+ total = outstanding = 0; -+ jstart = jiffies; -+ for (i = 0; i < request_q_len; i++) { -+ spin_lock_irqsave(&ocfbench_counter_lock, flags); -+ outstanding++; -+ spin_unlock_irqrestore(&ocfbench_counter_lock, flags); -+ ocf_request(&requests[i]); -+ } -+ while (outstanding > 0) -+ schedule(); -+ jstop = jiffies; -+ -+ mbps = 0; -+ if (jstop > jstart) { -+ mbps = (unsigned long) total * (unsigned long) request_size * 8; -+ mbps /= ((jstop - jstart) * 1000) / HZ; -+ } -+ printk("OCF: %d requests of %d bytes in %d jiffies (%d.%03d Mbps)\n", -+ total, request_size, (int)(jstop - jstart), -+ ((int)mbps) / 1000, ((int)mbps) % 1000); -+ ocf_done(); -+ -+#ifdef BENCH_IXP_ACCESS_LIB -+ /* -+ * IXP benchmark -+ */ -+ printk("IXP: testing ...\n"); -+ ixp_init(); -+ total = outstanding = 0; -+ jstart = jiffies; -+ for (i = 0; i < request_q_len; i++) { -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ INIT_WORK(&requests[i].work, ixp_request_wq); -+#else -+ INIT_WORK(&requests[i].work, ixp_request, &requests[i]); -+#endif -+ spin_lock_irqsave(&ocfbench_counter_lock, flags); -+ outstanding++; -+ spin_unlock_irqrestore(&ocfbench_counter_lock, flags); -+ ixp_request(&requests[i]); -+ } -+ while (outstanding > 0) -+ schedule(); -+ jstop = jiffies; -+ -+ mbps = 0; -+ if (jstop > jstart) { -+ mbps = (unsigned long) total * (unsigned long) request_size * 8; -+ mbps /= ((jstop - jstart) * 1000) / HZ; -+ } -+ printk("IXP: %d requests of %d bytes in %d jiffies (%d.%03d Mbps)\n", -+ total, request_size, jstop - jstart, -+ ((int)mbps) / 1000, ((int)mbps) % 1000); -+ ixp_done(); -+#endif /* BENCH_IXP_ACCESS_LIB */ -+ -+ for (i = 0; i < request_q_len; i++) -+ kfree(requests[i].buffer); -+ kfree(requests); -+ return -EINVAL; /* always fail to load so it can be re-run quickly ;-) */ -+} -+ -+static void __exit ocfbench_exit(void) -+{ -+} -+ -+module_init(ocfbench_init); -+module_exit(ocfbench_exit); -+ -+MODULE_LICENSE("BSD"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("Benchmark various in-kernel crypto speeds"); -diff -Nur linux-3.0.4.orig/crypto/ocf/ocf-compat.h linux-3.0.4/crypto/ocf/ocf-compat.h ---- linux-3.0.4.orig/crypto/ocf/ocf-compat.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/ocf-compat.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,365 @@ -+#ifndef _BSD_COMPAT_H_ -+#define _BSD_COMPAT_H_ 1 -+/****************************************************************************/ -+/* -+ * Provide compat routines for older linux kernels and BSD kernels -+ * -+ * Written by David McCullough -+ * Copyright (C) 2010 David McCullough -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * ALTERNATIVELY, provided that this notice is retained in full, this file -+ * may be distributed under the terms of the GNU General Public License (GPL), -+ * in which case the provisions of the GPL apply INSTEAD OF those given above. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ */ -+/****************************************************************************/ -+#ifdef __KERNEL__ -+#include -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) -+#include -+#endif -+ -+/* -+ * fake some BSD driver interface stuff specifically for OCF use -+ */ -+ -+typedef struct ocf_device *device_t; -+ -+typedef struct { -+ int (*cryptodev_newsession)(device_t dev, u_int32_t *sidp, struct cryptoini *cri); -+ int (*cryptodev_freesession)(device_t dev, u_int64_t tid); -+ int (*cryptodev_process)(device_t dev, struct cryptop *crp, int hint); -+ int (*cryptodev_kprocess)(device_t dev, struct cryptkop *krp, int hint); -+} device_method_t; -+#define DEVMETHOD(id, func) id: func -+ -+struct ocf_device { -+ char name[32]; /* the driver name */ -+ char nameunit[32]; /* the driver name + HW instance */ -+ int unit; -+ device_method_t methods; -+ void *softc; -+}; -+ -+#define CRYPTODEV_NEWSESSION(dev, sid, cri) \ -+ ((*(dev)->methods.cryptodev_newsession)(dev,sid,cri)) -+#define CRYPTODEV_FREESESSION(dev, sid) \ -+ ((*(dev)->methods.cryptodev_freesession)(dev, sid)) -+#define CRYPTODEV_PROCESS(dev, crp, hint) \ -+ ((*(dev)->methods.cryptodev_process)(dev, crp, hint)) -+#define CRYPTODEV_KPROCESS(dev, krp, hint) \ -+ ((*(dev)->methods.cryptodev_kprocess)(dev, krp, hint)) -+ -+#define device_get_name(dev) ((dev)->name) -+#define device_get_nameunit(dev) ((dev)->nameunit) -+#define device_get_unit(dev) ((dev)->unit) -+#define device_get_softc(dev) ((dev)->softc) -+ -+#define softc_device_decl \ -+ struct ocf_device _device; \ -+ device_t -+ -+#define softc_device_init(_sc, _name, _unit, _methods) \ -+ if (1) {\ -+ strncpy((_sc)->_device.name, _name, sizeof((_sc)->_device.name) - 1); \ -+ snprintf((_sc)->_device.nameunit, sizeof((_sc)->_device.name), "%s%d", _name, _unit); \ -+ (_sc)->_device.unit = _unit; \ -+ (_sc)->_device.methods = _methods; \ -+ (_sc)->_device.softc = (void *) _sc; \ -+ *(device_t *)((softc_get_device(_sc))+1) = &(_sc)->_device; \ -+ } else -+ -+#define softc_get_device(_sc) (&(_sc)->_device) -+ -+/* -+ * iomem support for 2.4 and 2.6 kernels -+ */ -+#include -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+#define ocf_iomem_t unsigned long -+ -+/* -+ * implement simple workqueue like support for older kernels -+ */ -+ -+#include -+ -+#define work_struct tq_struct -+ -+#define INIT_WORK(wp, fp, ap) \ -+ do { \ -+ (wp)->sync = 0; \ -+ (wp)->routine = (fp); \ -+ (wp)->data = (ap); \ -+ } while (0) -+ -+#define schedule_work(wp) \ -+ do { \ -+ queue_task((wp), &tq_immediate); \ -+ mark_bh(IMMEDIATE_BH); \ -+ } while (0) -+ -+#define flush_scheduled_work() run_task_queue(&tq_immediate) -+ -+#else -+#define ocf_iomem_t void __iomem * -+ -+#include -+ -+#endif -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26) -+#include -+#elif LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) -+#define files_fdtable(files) (files) -+#endif -+ -+#ifdef MODULE_PARM -+#undef module_param /* just in case */ -+#define module_param(a,b,c) MODULE_PARM(a,"i") -+#endif -+ -+#define bzero(s,l) memset(s,0,l) -+#define bcopy(s,d,l) memcpy(d,s,l) -+#define bcmp(x, y, l) memcmp(x,y,l) -+ -+#define MIN(x,y) ((x) < (y) ? (x) : (y)) -+ -+#define device_printf(dev, a...) ({ \ -+ printk("%s: ", device_get_nameunit(dev)); printk(a); \ -+ }) -+ -+#undef printf -+#define printf(fmt...) printk(fmt) -+ -+#define KASSERT(c,p) if (!(c)) { printk p ; } else -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+#define ocf_daemonize(str) \ -+ daemonize(); \ -+ spin_lock_irq(¤t->sigmask_lock); \ -+ sigemptyset(¤t->blocked); \ -+ recalc_sigpending(current); \ -+ spin_unlock_irq(¤t->sigmask_lock); \ -+ sprintf(current->comm, str); -+#else -+#define ocf_daemonize(str) daemonize(str); -+#endif -+ -+#define TAILQ_INSERT_TAIL(q,d,m) list_add_tail(&(d)->m, (q)) -+#define TAILQ_EMPTY(q) list_empty(q) -+#define TAILQ_FOREACH(v, q, m) list_for_each_entry(v, q, m) -+ -+#define read_random(p,l) get_random_bytes(p,l) -+ -+#define DELAY(x) ((x) > 2000 ? mdelay((x)/1000) : udelay(x)) -+#define strtoul simple_strtoul -+ -+#define pci_get_vendor(dev) ((dev)->vendor) -+#define pci_get_device(dev) ((dev)->device) -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+#define pci_set_consistent_dma_mask(dev, mask) (0) -+#endif -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10) -+#define pci_dma_sync_single_for_cpu pci_dma_sync_single -+#endif -+ -+#ifndef DMA_32BIT_MASK -+#define DMA_32BIT_MASK 0x00000000ffffffffULL -+#endif -+ -+#ifndef htole32 -+#define htole32(x) cpu_to_le32(x) -+#endif -+#ifndef htobe32 -+#define htobe32(x) cpu_to_be32(x) -+#endif -+#ifndef htole16 -+#define htole16(x) cpu_to_le16(x) -+#endif -+#ifndef htobe16 -+#define htobe16(x) cpu_to_be16(x) -+#endif -+ -+/* older kernels don't have these */ -+ -+#include -+#if !defined(IRQ_NONE) && !defined(IRQ_RETVAL) -+#define IRQ_NONE -+#define IRQ_HANDLED -+#define IRQ_WAKE_THREAD -+#define IRQ_RETVAL -+#define irqreturn_t void -+typedef irqreturn_t (*irq_handler_t)(int irq, void *arg, struct pt_regs *regs); -+#endif -+#ifndef IRQF_SHARED -+#define IRQF_SHARED SA_SHIRQ -+#endif -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) -+# define strlcpy(dest,src,len) \ -+ ({strncpy(dest,src,(len)-1); ((char *)dest)[(len)-1] = '\0'; }) -+#endif -+ -+#ifndef MAX_ERRNO -+#define MAX_ERRNO 4095 -+#endif -+#ifndef IS_ERR_VALUE -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,5) -+#include -+#endif -+#ifndef IS_ERR_VALUE -+#define IS_ERR_VALUE(x) ((unsigned long)(x) >= (unsigned long)-MAX_ERRNO) -+#endif -+#endif -+ -+/* -+ * common debug for all -+ */ -+#if 1 -+#define dprintk(a...) do { if (debug) printk(a); } while(0) -+#else -+#define dprintk(a...) -+#endif -+ -+#ifndef SLAB_ATOMIC -+/* Changed in 2.6.20, must use GFP_ATOMIC now */ -+#define SLAB_ATOMIC GFP_ATOMIC -+#endif -+ -+/* -+ * need some additional support for older kernels */ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,2) -+#define pci_register_driver_compat(driver, rc) \ -+ do { \ -+ if ((rc) > 0) { \ -+ (rc) = 0; \ -+ } else if (rc == 0) { \ -+ (rc) = -ENODEV; \ -+ } else { \ -+ pci_unregister_driver(driver); \ -+ } \ -+ } while (0) -+#elif LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10) -+#define pci_register_driver_compat(driver,rc) ((rc) = (rc) < 0 ? (rc) : 0) -+#else -+#define pci_register_driver_compat(driver,rc) -+#endif -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) -+ -+#include -+#include -+ -+static inline void sg_set_page(struct scatterlist *sg, struct page *page, -+ unsigned int len, unsigned int offset) -+{ -+ sg->page = page; -+ sg->offset = offset; -+ sg->length = len; -+} -+ -+static inline void *sg_virt(struct scatterlist *sg) -+{ -+ return page_address(sg->page) + sg->offset; -+} -+ -+#define sg_init_table(sg, n) -+ -+#endif -+ -+#ifndef late_initcall -+#define late_initcall(init) module_init(init) -+#endif -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,4) || !defined(CONFIG_SMP) -+#define ocf_for_each_cpu(cpu) for ((cpu) = 0; (cpu) == 0; (cpu)++) -+#else -+#define ocf_for_each_cpu(cpu) for_each_present_cpu(cpu) -+#endif -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) -+#include -+#define kill_proc(p,s,v) send_sig(s,find_task_by_vpid(p),0) -+#endif -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,4) -+ -+struct ocf_thread { -+ struct task_struct *task; -+ int (*func)(void *arg); -+ void *arg; -+}; -+ -+/* thread startup helper func */ -+static inline int ocf_run_thread(void *arg) -+{ -+ struct ocf_thread *t = (struct ocf_thread *) arg; -+ if (!t) -+ return -1; /* very bad */ -+ t->task = current; -+ daemonize(); -+ spin_lock_irq(¤t->sigmask_lock); -+ sigemptyset(¤t->blocked); -+ recalc_sigpending(current); -+ spin_unlock_irq(¤t->sigmask_lock); -+ return (*t->func)(t->arg); -+} -+ -+#define kthread_create(f,a,fmt...) \ -+ ({ \ -+ struct ocf_thread t; \ -+ pid_t p; \ -+ t.task = NULL; \ -+ t.func = (f); \ -+ t.arg = (a); \ -+ p = kernel_thread(ocf_run_thread, &t, CLONE_FS|CLONE_FILES); \ -+ while (p != (pid_t) -1 && t.task == NULL) \ -+ schedule(); \ -+ if (t.task) \ -+ snprintf(t.task->comm, sizeof(t.task->comm), fmt); \ -+ (t.task); \ -+ }) -+ -+#define kthread_bind(t,cpu) /**/ -+ -+#define kthread_should_stop() (strcmp(current->comm, "stopping") == 0) -+ -+#define kthread_stop(t) \ -+ ({ \ -+ strcpy((t)->comm, "stopping"); \ -+ kill_proc((t)->pid, SIGTERM, 1); \ -+ do { \ -+ schedule(); \ -+ } while (kill_proc((t)->pid, SIGTERM, 1) == 0); \ -+ }) -+ -+#else -+#include -+#endif -+ -+#endif /* __KERNEL__ */ -+ -+/****************************************************************************/ -+#endif /* _BSD_COMPAT_H_ */ -diff -Nur linux-3.0.4.orig/crypto/ocf/ocfnull/Makefile linux-3.0.4/crypto/ocf/ocfnull/Makefile ---- linux-3.0.4.orig/crypto/ocf/ocfnull/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/ocfnull/Makefile 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,12 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+obj-$(CONFIG_OCF_OCFNULL) += ocfnull.o -+ -+obj ?= . -+EXTRA_CFLAGS += -I$(obj)/.. -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/ocfnull/ocfnull.c linux-3.0.4/crypto/ocf/ocfnull/ocfnull.c ---- linux-3.0.4.orig/crypto/ocf/ocfnull/ocfnull.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/ocfnull/ocfnull.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,204 @@ -+/* -+ * An OCF module for determining the cost of crypto versus the cost of -+ * IPSec processing outside of OCF. This modules gives us the effect of -+ * zero cost encryption, of course you will need to run it at both ends -+ * since it does no crypto at all. -+ * -+ * Written by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * ALTERNATIVELY, provided that this notice is retained in full, this product -+ * may be distributed under the terms of the GNU General Public License (GPL), -+ * in which case the provisions of the GPL apply INSTEAD OF those given above. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ */ -+ -+#include -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+static int32_t null_id = -1; -+static u_int32_t null_sesnum = 0; -+ -+static int null_process(device_t, struct cryptop *, int); -+static int null_newsession(device_t, u_int32_t *, struct cryptoini *); -+static int null_freesession(device_t, u_int64_t); -+ -+#define debug ocfnull_debug -+int ocfnull_debug = 0; -+module_param(ocfnull_debug, int, 0644); -+MODULE_PARM_DESC(ocfnull_debug, "Enable debug"); -+ -+/* -+ * dummy device structure -+ */ -+ -+static struct { -+ softc_device_decl sc_dev; -+} nulldev; -+ -+static device_method_t null_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, null_newsession), -+ DEVMETHOD(cryptodev_freesession,null_freesession), -+ DEVMETHOD(cryptodev_process, null_process), -+}; -+ -+/* -+ * Generate a new software session. -+ */ -+static int -+null_newsession(device_t arg, u_int32_t *sid, struct cryptoini *cri) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid == NULL || cri == NULL) { -+ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ if (null_sesnum == 0) -+ null_sesnum++; -+ *sid = null_sesnum++; -+ return 0; -+} -+ -+ -+/* -+ * Free a session. -+ */ -+static int -+null_freesession(device_t arg, u_int64_t tid) -+{ -+ u_int32_t sid = CRYPTO_SESID2LID(tid); -+ -+ dprintk("%s()\n", __FUNCTION__); -+ if (sid > null_sesnum) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ /* Silently accept and return */ -+ if (sid == 0) -+ return 0; -+ return 0; -+} -+ -+ -+/* -+ * Process a request. -+ */ -+static int -+null_process(device_t arg, struct cryptop *crp, int hint) -+{ -+ unsigned int lid; -+ -+ dprintk("%s()\n", __FUNCTION__); -+ -+ /* Sanity check */ -+ if (crp == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ -+ crp->crp_etype = 0; -+ -+ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { -+ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); -+ crp->crp_etype = EINVAL; -+ goto done; -+ } -+ -+ /* -+ * find the session we are using -+ */ -+ -+ lid = crp->crp_sid & 0xffffffff; -+ if (lid >= null_sesnum || lid == 0) { -+ crp->crp_etype = ENOENT; -+ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); -+ goto done; -+ } -+ -+done: -+ crypto_done(crp); -+ return 0; -+} -+ -+ -+/* -+ * our driver startup and shutdown routines -+ */ -+ -+static int -+null_init(void) -+{ -+ dprintk("%s(%p)\n", __FUNCTION__, null_init); -+ -+ memset(&nulldev, 0, sizeof(nulldev)); -+ softc_device_init(&nulldev, "ocfnull", 0, null_methods); -+ -+ null_id = crypto_get_driverid(softc_get_device(&nulldev), -+ CRYPTOCAP_F_HARDWARE); -+ if (null_id < 0) -+ panic("ocfnull: crypto device cannot initialize!"); -+ -+#define REGISTER(alg) \ -+ crypto_register(null_id,alg,0,0) -+ REGISTER(CRYPTO_DES_CBC); -+ REGISTER(CRYPTO_3DES_CBC); -+ REGISTER(CRYPTO_RIJNDAEL128_CBC); -+ REGISTER(CRYPTO_MD5); -+ REGISTER(CRYPTO_SHA1); -+ REGISTER(CRYPTO_MD5_HMAC); -+ REGISTER(CRYPTO_SHA1_HMAC); -+#undef REGISTER -+ -+ return 0; -+} -+ -+static void -+null_exit(void) -+{ -+ dprintk("%s()\n", __FUNCTION__); -+ crypto_unregister_all(null_id); -+ null_id = -1; -+} -+ -+module_init(null_init); -+module_exit(null_exit); -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("ocfnull - claims a lot but does nothing"); -diff -Nur linux-3.0.4.orig/crypto/ocf/pasemi/Makefile linux-3.0.4/crypto/ocf/pasemi/Makefile ---- linux-3.0.4.orig/crypto/ocf/pasemi/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/pasemi/Makefile 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,12 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+obj-$(CONFIG_OCF_PASEMI) += pasemi.o -+ -+obj ?= . -+EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/pasemi/pasemi.c linux-3.0.4/crypto/ocf/pasemi/pasemi.c ---- linux-3.0.4.orig/crypto/ocf/pasemi/pasemi.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/pasemi/pasemi.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,1007 @@ -+/* -+ * Copyright (C) 2007 PA Semi, Inc -+ * -+ * Driver for the PA Semi PWRficient DMA Crypto Engine -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "pasemi_fnu.h" -+ -+#define DRV_NAME "pasemi" -+ -+#define TIMER_INTERVAL 1000 -+ -+static void __devexit pasemi_dma_remove(struct pci_dev *pdev); -+static struct pasdma_status volatile * dma_status; -+ -+static int debug; -+module_param(debug, int, 0644); -+MODULE_PARM_DESC(debug, "Enable debug"); -+ -+static void pasemi_desc_start(struct pasemi_desc *desc, u64 hdr) -+{ -+ desc->postop = 0; -+ desc->quad[0] = hdr; -+ desc->quad_cnt = 1; -+ desc->size = 1; -+} -+ -+static void pasemi_desc_build(struct pasemi_desc *desc, u64 val) -+{ -+ desc->quad[desc->quad_cnt++] = val; -+ desc->size = (desc->quad_cnt + 1) / 2; -+} -+ -+static void pasemi_desc_hdr(struct pasemi_desc *desc, u64 hdr) -+{ -+ desc->quad[0] |= hdr; -+} -+ -+static int pasemi_desc_size(struct pasemi_desc *desc) -+{ -+ return desc->size; -+} -+ -+static void pasemi_ring_add_desc( -+ struct pasemi_fnu_txring *ring, -+ struct pasemi_desc *desc, -+ struct cryptop *crp) { -+ int i; -+ int ring_index = 2 * (ring->next_to_fill & (TX_RING_SIZE-1)); -+ -+ TX_DESC_INFO(ring, ring->next_to_fill).desc_size = desc->size; -+ TX_DESC_INFO(ring, ring->next_to_fill).desc_postop = desc->postop; -+ TX_DESC_INFO(ring, ring->next_to_fill).cf_crp = crp; -+ -+ for (i = 0; i < desc->quad_cnt; i += 2) { -+ ring_index = 2 * (ring->next_to_fill & (TX_RING_SIZE-1)); -+ ring->desc[ring_index] = desc->quad[i]; -+ ring->desc[ring_index + 1] = desc->quad[i + 1]; -+ ring->next_to_fill++; -+ } -+ -+ if (desc->quad_cnt & 1) -+ ring->desc[ring_index + 1] = 0; -+} -+ -+static void pasemi_ring_incr(struct pasemi_softc *sc, int chan_index, int incr) -+{ -+ out_le32(sc->dma_regs + PAS_DMA_TXCHAN_INCR(sc->base_chan + chan_index), -+ incr); -+} -+ -+/* -+ * Generate a new software session. -+ */ -+static int -+pasemi_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) -+{ -+ struct cryptoini *c, *encini = NULL, *macini = NULL; -+ struct pasemi_softc *sc = device_get_softc(dev); -+ struct pasemi_session *ses = NULL, **sespp; -+ int sesn, blksz = 0; -+ u64 ccmd = 0; -+ unsigned long flags; -+ struct pasemi_desc init_desc; -+ struct pasemi_fnu_txring *txring; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ if (sidp == NULL || cri == NULL || sc == NULL) { -+ DPRINTF("%s,%d - EINVAL\n", __FILE__, __LINE__); -+ return -EINVAL; -+ } -+ for (c = cri; c != NULL; c = c->cri_next) { -+ if (ALG_IS_SIG(c->cri_alg)) { -+ if (macini) -+ return -EINVAL; -+ macini = c; -+ } else if (ALG_IS_CIPHER(c->cri_alg)) { -+ if (encini) -+ return -EINVAL; -+ encini = c; -+ } else { -+ DPRINTF("UNKNOWN c->cri_alg %d\n", c->cri_alg); -+ return -EINVAL; -+ } -+ } -+ if (encini == NULL && macini == NULL) -+ return -EINVAL; -+ if (encini) { -+ /* validate key length */ -+ switch (encini->cri_alg) { -+ case CRYPTO_DES_CBC: -+ if (encini->cri_klen != 64) -+ return -EINVAL; -+ ccmd = DMA_CALGO_DES; -+ break; -+ case CRYPTO_3DES_CBC: -+ if (encini->cri_klen != 192) -+ return -EINVAL; -+ ccmd = DMA_CALGO_3DES; -+ break; -+ case CRYPTO_AES_CBC: -+ if (encini->cri_klen != 128 && -+ encini->cri_klen != 192 && -+ encini->cri_klen != 256) -+ return -EINVAL; -+ ccmd = DMA_CALGO_AES; -+ break; -+ case CRYPTO_ARC4: -+ if (encini->cri_klen != 128) -+ return -EINVAL; -+ ccmd = DMA_CALGO_ARC; -+ break; -+ default: -+ DPRINTF("UNKNOWN encini->cri_alg %d\n", -+ encini->cri_alg); -+ return -EINVAL; -+ } -+ } -+ -+ if (macini) { -+ switch (macini->cri_alg) { -+ case CRYPTO_MD5: -+ case CRYPTO_MD5_HMAC: -+ blksz = 16; -+ break; -+ case CRYPTO_SHA1: -+ case CRYPTO_SHA1_HMAC: -+ blksz = 20; -+ break; -+ default: -+ DPRINTF("UNKNOWN macini->cri_alg %d\n", -+ macini->cri_alg); -+ return -EINVAL; -+ } -+ if (((macini->cri_klen + 7) / 8) > blksz) { -+ DPRINTF("key length %d bigger than blksize %d not supported\n", -+ ((macini->cri_klen + 7) / 8), blksz); -+ return -EINVAL; -+ } -+ } -+ -+ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { -+ if (sc->sc_sessions[sesn] == NULL) { -+ sc->sc_sessions[sesn] = (struct pasemi_session *) -+ kzalloc(sizeof(struct pasemi_session), GFP_ATOMIC); -+ ses = sc->sc_sessions[sesn]; -+ break; -+ } else if (sc->sc_sessions[sesn]->used == 0) { -+ ses = sc->sc_sessions[sesn]; -+ break; -+ } -+ } -+ -+ if (ses == NULL) { -+ sespp = (struct pasemi_session **) -+ kzalloc(sc->sc_nsessions * 2 * -+ sizeof(struct pasemi_session *), GFP_ATOMIC); -+ if (sespp == NULL) -+ return -ENOMEM; -+ memcpy(sespp, sc->sc_sessions, -+ sc->sc_nsessions * sizeof(struct pasemi_session *)); -+ kfree(sc->sc_sessions); -+ sc->sc_sessions = sespp; -+ sesn = sc->sc_nsessions; -+ ses = sc->sc_sessions[sesn] = (struct pasemi_session *) -+ kzalloc(sizeof(struct pasemi_session), GFP_ATOMIC); -+ if (ses == NULL) -+ return -ENOMEM; -+ sc->sc_nsessions *= 2; -+ } -+ -+ ses->used = 1; -+ -+ ses->dma_addr = pci_map_single(sc->dma_pdev, (void *) ses->civ, -+ sizeof(struct pasemi_session), DMA_TO_DEVICE); -+ -+ /* enter the channel scheduler */ -+ spin_lock_irqsave(&sc->sc_chnlock, flags); -+ -+ /* ARC4 has to be processed by the even channel */ -+ if (encini && (encini->cri_alg == CRYPTO_ARC4)) -+ ses->chan = sc->sc_lastchn & ~1; -+ else -+ ses->chan = sc->sc_lastchn; -+ sc->sc_lastchn = (sc->sc_lastchn + 1) % sc->sc_num_channels; -+ -+ spin_unlock_irqrestore(&sc->sc_chnlock, flags); -+ -+ txring = &sc->tx[ses->chan]; -+ -+ if (encini) { -+ ses->ccmd = ccmd; -+ ses->keysz = (encini->cri_klen - 63) / 64; -+ memcpy(ses->key, encini->cri_key, (ses->keysz + 1) * 8); -+ -+ pasemi_desc_start(&init_desc, -+ XCT_CTRL_HDR(ses->chan, (encini && macini) ? 0x68 : 0x40, DMA_FN_CIV0)); -+ pasemi_desc_build(&init_desc, -+ XCT_FUN_SRC_PTR((encini && macini) ? 0x68 : 0x40, ses->dma_addr)); -+ } -+ if (macini) { -+ if (macini->cri_alg == CRYPTO_MD5_HMAC || -+ macini->cri_alg == CRYPTO_SHA1_HMAC) -+ memcpy(ses->hkey, macini->cri_key, blksz); -+ else { -+ /* Load initialization constants(RFC 1321, 3174) */ -+ ses->hiv[0] = 0x67452301efcdab89ULL; -+ ses->hiv[1] = 0x98badcfe10325476ULL; -+ ses->hiv[2] = 0xc3d2e1f000000000ULL; -+ } -+ ses->hseq = 0ULL; -+ } -+ -+ spin_lock_irqsave(&txring->fill_lock, flags); -+ -+ if (((txring->next_to_fill + pasemi_desc_size(&init_desc)) - -+ txring->next_to_clean) > TX_RING_SIZE) { -+ spin_unlock_irqrestore(&txring->fill_lock, flags); -+ return ERESTART; -+ } -+ -+ if (encini) { -+ pasemi_ring_add_desc(txring, &init_desc, NULL); -+ pasemi_ring_incr(sc, ses->chan, -+ pasemi_desc_size(&init_desc)); -+ } -+ -+ txring->sesn = sesn; -+ spin_unlock_irqrestore(&txring->fill_lock, flags); -+ -+ *sidp = PASEMI_SID(sesn); -+ return 0; -+} -+ -+/* -+ * Deallocate a session. -+ */ -+static int -+pasemi_freesession(device_t dev, u_int64_t tid) -+{ -+ struct pasemi_softc *sc = device_get_softc(dev); -+ int session; -+ u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (sc == NULL) -+ return -EINVAL; -+ session = PASEMI_SESSION(sid); -+ if (session >= sc->sc_nsessions || !sc->sc_sessions[session]) -+ return -EINVAL; -+ -+ pci_unmap_single(sc->dma_pdev, -+ sc->sc_sessions[session]->dma_addr, -+ sizeof(struct pasemi_session), DMA_TO_DEVICE); -+ memset(sc->sc_sessions[session], 0, -+ sizeof(struct pasemi_session)); -+ -+ return 0; -+} -+ -+static int -+pasemi_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ -+ int err = 0, ivsize, srclen = 0, reinit = 0, reinit_size = 0, chsel; -+ struct pasemi_softc *sc = device_get_softc(dev); -+ struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; -+ caddr_t ivp; -+ struct pasemi_desc init_desc, work_desc; -+ struct pasemi_session *ses; -+ struct sk_buff *skb; -+ struct uio *uiop; -+ unsigned long flags; -+ struct pasemi_fnu_txring *txring; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (crp == NULL || crp->crp_callback == NULL || sc == NULL) -+ return -EINVAL; -+ -+ crp->crp_etype = 0; -+ if (PASEMI_SESSION(crp->crp_sid) >= sc->sc_nsessions) -+ return -EINVAL; -+ -+ ses = sc->sc_sessions[PASEMI_SESSION(crp->crp_sid)]; -+ -+ crd1 = crp->crp_desc; -+ if (crd1 == NULL) { -+ err = -EINVAL; -+ goto errout; -+ } -+ crd2 = crd1->crd_next; -+ -+ if (ALG_IS_SIG(crd1->crd_alg)) { -+ maccrd = crd1; -+ if (crd2 == NULL) -+ enccrd = NULL; -+ else if (ALG_IS_CIPHER(crd2->crd_alg) && -+ (crd2->crd_flags & CRD_F_ENCRYPT) == 0) -+ enccrd = crd2; -+ else -+ goto erralg; -+ } else if (ALG_IS_CIPHER(crd1->crd_alg)) { -+ enccrd = crd1; -+ if (crd2 == NULL) -+ maccrd = NULL; -+ else if (ALG_IS_SIG(crd2->crd_alg) && -+ (crd1->crd_flags & CRD_F_ENCRYPT)) -+ maccrd = crd2; -+ else -+ goto erralg; -+ } else -+ goto erralg; -+ -+ chsel = ses->chan; -+ -+ txring = &sc->tx[chsel]; -+ -+ if (enccrd && !maccrd) { -+ if (enccrd->crd_alg == CRYPTO_ARC4) -+ reinit = 1; -+ reinit_size = 0x40; -+ srclen = crp->crp_ilen; -+ -+ pasemi_desc_start(&work_desc, XCT_FUN_O | XCT_FUN_I -+ | XCT_FUN_FUN(chsel)); -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) -+ pasemi_desc_hdr(&work_desc, XCT_FUN_CRM_ENC); -+ else -+ pasemi_desc_hdr(&work_desc, XCT_FUN_CRM_DEC); -+ } else if (enccrd && maccrd) { -+ if (enccrd->crd_alg == CRYPTO_ARC4) -+ reinit = 1; -+ reinit_size = 0x68; -+ -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) { -+ /* Encrypt -> Authenticate */ -+ pasemi_desc_start(&work_desc, XCT_FUN_O | XCT_FUN_I | XCT_FUN_CRM_ENC_SIG -+ | XCT_FUN_A | XCT_FUN_FUN(chsel)); -+ srclen = maccrd->crd_skip + maccrd->crd_len; -+ } else { -+ /* Authenticate -> Decrypt */ -+ pasemi_desc_start(&work_desc, XCT_FUN_O | XCT_FUN_I | XCT_FUN_CRM_SIG_DEC -+ | XCT_FUN_24BRES | XCT_FUN_FUN(chsel)); -+ pasemi_desc_build(&work_desc, 0); -+ pasemi_desc_build(&work_desc, 0); -+ pasemi_desc_build(&work_desc, 0); -+ work_desc.postop = PASEMI_CHECK_SIG; -+ srclen = crp->crp_ilen; -+ } -+ -+ pasemi_desc_hdr(&work_desc, XCT_FUN_SHL(maccrd->crd_skip / 4)); -+ pasemi_desc_hdr(&work_desc, XCT_FUN_CHL(enccrd->crd_skip - maccrd->crd_skip)); -+ } else if (!enccrd && maccrd) { -+ srclen = maccrd->crd_len; -+ -+ pasemi_desc_start(&init_desc, -+ XCT_CTRL_HDR(chsel, 0x58, DMA_FN_HKEY0)); -+ pasemi_desc_build(&init_desc, -+ XCT_FUN_SRC_PTR(0x58, ((struct pasemi_session *)ses->dma_addr)->hkey)); -+ -+ pasemi_desc_start(&work_desc, XCT_FUN_O | XCT_FUN_I | XCT_FUN_CRM_SIG -+ | XCT_FUN_A | XCT_FUN_FUN(chsel)); -+ } -+ -+ if (enccrd) { -+ switch (enccrd->crd_alg) { -+ case CRYPTO_3DES_CBC: -+ pasemi_desc_hdr(&work_desc, XCT_FUN_ALG_3DES | -+ XCT_FUN_BCM_CBC); -+ ivsize = sizeof(u64); -+ break; -+ case CRYPTO_DES_CBC: -+ pasemi_desc_hdr(&work_desc, XCT_FUN_ALG_DES | -+ XCT_FUN_BCM_CBC); -+ ivsize = sizeof(u64); -+ break; -+ case CRYPTO_AES_CBC: -+ pasemi_desc_hdr(&work_desc, XCT_FUN_ALG_AES | -+ XCT_FUN_BCM_CBC); -+ ivsize = 2 * sizeof(u64); -+ break; -+ case CRYPTO_ARC4: -+ pasemi_desc_hdr(&work_desc, XCT_FUN_ALG_ARC); -+ ivsize = 0; -+ break; -+ default: -+ printk(DRV_NAME ": unimplemented enccrd->crd_alg %d\n", -+ enccrd->crd_alg); -+ err = -EINVAL; -+ goto errout; -+ } -+ -+ ivp = (ivsize == sizeof(u64)) ? (caddr_t) &ses->civ[1] : (caddr_t) &ses->civ[0]; -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) { -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) -+ memcpy(ivp, enccrd->crd_iv, ivsize); -+ else -+ read_random(ivp, ivsize); -+ /* If IV is not present in the buffer already, it has to be copied there */ -+ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ enccrd->crd_inject, ivsize, ivp); -+ } else { -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) -+ /* IV is provided expicitly in descriptor */ -+ memcpy(ivp, enccrd->crd_iv, ivsize); -+ else -+ /* IV is provided in the packet */ -+ crypto_copydata(crp->crp_flags, crp->crp_buf, -+ enccrd->crd_inject, ivsize, -+ ivp); -+ } -+ } -+ -+ if (maccrd) { -+ switch (maccrd->crd_alg) { -+ case CRYPTO_MD5: -+ pasemi_desc_hdr(&work_desc, XCT_FUN_SIG_MD5 | -+ XCT_FUN_HSZ((crp->crp_ilen - maccrd->crd_inject) / 4)); -+ break; -+ case CRYPTO_SHA1: -+ pasemi_desc_hdr(&work_desc, XCT_FUN_SIG_SHA1 | -+ XCT_FUN_HSZ((crp->crp_ilen - maccrd->crd_inject) / 4)); -+ break; -+ case CRYPTO_MD5_HMAC: -+ pasemi_desc_hdr(&work_desc, XCT_FUN_SIG_HMAC_MD5 | -+ XCT_FUN_HSZ((crp->crp_ilen - maccrd->crd_inject) / 4)); -+ break; -+ case CRYPTO_SHA1_HMAC: -+ pasemi_desc_hdr(&work_desc, XCT_FUN_SIG_HMAC_SHA1 | -+ XCT_FUN_HSZ((crp->crp_ilen - maccrd->crd_inject) / 4)); -+ break; -+ default: -+ printk(DRV_NAME ": unimplemented maccrd->crd_alg %d\n", -+ maccrd->crd_alg); -+ err = -EINVAL; -+ goto errout; -+ } -+ } -+ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ /* using SKB buffers */ -+ skb = (struct sk_buff *)crp->crp_buf; -+ if (skb_shinfo(skb)->nr_frags) { -+ printk(DRV_NAME ": skb frags unimplemented\n"); -+ err = -EINVAL; -+ goto errout; -+ } -+ pasemi_desc_build( -+ &work_desc, -+ XCT_FUN_DST_PTR(skb->len, pci_map_single( -+ sc->dma_pdev, skb->data, -+ skb->len, DMA_TO_DEVICE))); -+ pasemi_desc_build( -+ &work_desc, -+ XCT_FUN_SRC_PTR( -+ srclen, pci_map_single( -+ sc->dma_pdev, skb->data, -+ srclen, DMA_TO_DEVICE))); -+ pasemi_desc_hdr(&work_desc, XCT_FUN_LLEN(srclen)); -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ /* using IOV buffers */ -+ uiop = (struct uio *)crp->crp_buf; -+ if (uiop->uio_iovcnt > 1) { -+ printk(DRV_NAME ": iov frags unimplemented\n"); -+ err = -EINVAL; -+ goto errout; -+ } -+ -+ /* crp_olen is never set; always use crp_ilen */ -+ pasemi_desc_build( -+ &work_desc, -+ XCT_FUN_DST_PTR(crp->crp_ilen, pci_map_single( -+ sc->dma_pdev, -+ uiop->uio_iov->iov_base, -+ crp->crp_ilen, DMA_TO_DEVICE))); -+ pasemi_desc_hdr(&work_desc, XCT_FUN_LLEN(srclen)); -+ -+ pasemi_desc_build( -+ &work_desc, -+ XCT_FUN_SRC_PTR(srclen, pci_map_single( -+ sc->dma_pdev, -+ uiop->uio_iov->iov_base, -+ srclen, DMA_TO_DEVICE))); -+ } else { -+ /* using contig buffers */ -+ pasemi_desc_build( -+ &work_desc, -+ XCT_FUN_DST_PTR(crp->crp_ilen, pci_map_single( -+ sc->dma_pdev, -+ crp->crp_buf, -+ crp->crp_ilen, DMA_TO_DEVICE))); -+ pasemi_desc_build( -+ &work_desc, -+ XCT_FUN_SRC_PTR(srclen, pci_map_single( -+ sc->dma_pdev, -+ crp->crp_buf, srclen, -+ DMA_TO_DEVICE))); -+ pasemi_desc_hdr(&work_desc, XCT_FUN_LLEN(srclen)); -+ } -+ -+ spin_lock_irqsave(&txring->fill_lock, flags); -+ -+ if (txring->sesn != PASEMI_SESSION(crp->crp_sid)) { -+ txring->sesn = PASEMI_SESSION(crp->crp_sid); -+ reinit = 1; -+ } -+ -+ if (enccrd) { -+ pasemi_desc_start(&init_desc, -+ XCT_CTRL_HDR(chsel, reinit ? reinit_size : 0x10, DMA_FN_CIV0)); -+ pasemi_desc_build(&init_desc, -+ XCT_FUN_SRC_PTR(reinit ? reinit_size : 0x10, ses->dma_addr)); -+ } -+ -+ if (((txring->next_to_fill + pasemi_desc_size(&init_desc) + -+ pasemi_desc_size(&work_desc)) - -+ txring->next_to_clean) > TX_RING_SIZE) { -+ spin_unlock_irqrestore(&txring->fill_lock, flags); -+ err = ERESTART; -+ goto errout; -+ } -+ -+ pasemi_ring_add_desc(txring, &init_desc, NULL); -+ pasemi_ring_add_desc(txring, &work_desc, crp); -+ -+ pasemi_ring_incr(sc, chsel, -+ pasemi_desc_size(&init_desc) + -+ pasemi_desc_size(&work_desc)); -+ -+ spin_unlock_irqrestore(&txring->fill_lock, flags); -+ -+ mod_timer(&txring->crypto_timer, jiffies + TIMER_INTERVAL); -+ -+ return 0; -+ -+erralg: -+ printk(DRV_NAME ": unsupported algorithm or algorithm order alg1 %d alg2 %d\n", -+ crd1->crd_alg, crd2->crd_alg); -+ err = -EINVAL; -+ -+errout: -+ if (err != ERESTART) { -+ crp->crp_etype = err; -+ crypto_done(crp); -+ } -+ return err; -+} -+ -+static int pasemi_clean_tx(struct pasemi_softc *sc, int chan) -+{ -+ int i, j, ring_idx; -+ struct pasemi_fnu_txring *ring = &sc->tx[chan]; -+ u16 delta_cnt; -+ int flags, loops = 10; -+ int desc_size; -+ struct cryptop *crp; -+ -+ spin_lock_irqsave(&ring->clean_lock, flags); -+ -+ while ((delta_cnt = (dma_status->tx_sta[sc->base_chan + chan] -+ & PAS_STATUS_PCNT_M) - ring->total_pktcnt) -+ && loops--) { -+ -+ for (i = 0; i < delta_cnt; i++) { -+ desc_size = TX_DESC_INFO(ring, ring->next_to_clean).desc_size; -+ crp = TX_DESC_INFO(ring, ring->next_to_clean).cf_crp; -+ if (crp) { -+ ring_idx = 2 * (ring->next_to_clean & (TX_RING_SIZE-1)); -+ if (TX_DESC_INFO(ring, ring->next_to_clean).desc_postop & PASEMI_CHECK_SIG) { -+ /* Need to make sure signature matched, -+ * if not - return error */ -+ if (!(ring->desc[ring_idx + 1] & (1ULL << 63))) -+ crp->crp_etype = -EINVAL; -+ } -+ crypto_done(TX_DESC_INFO(ring, -+ ring->next_to_clean).cf_crp); -+ TX_DESC_INFO(ring, ring->next_to_clean).cf_crp = NULL; -+ pci_unmap_single( -+ sc->dma_pdev, -+ XCT_PTR_ADDR_LEN(ring->desc[ring_idx + 1]), -+ PCI_DMA_TODEVICE); -+ -+ ring->desc[ring_idx] = ring->desc[ring_idx + 1] = 0; -+ -+ ring->next_to_clean++; -+ for (j = 1; j < desc_size; j++) { -+ ring_idx = 2 * -+ (ring->next_to_clean & -+ (TX_RING_SIZE-1)); -+ pci_unmap_single( -+ sc->dma_pdev, -+ XCT_PTR_ADDR_LEN(ring->desc[ring_idx]), -+ PCI_DMA_TODEVICE); -+ if (ring->desc[ring_idx + 1]) -+ pci_unmap_single( -+ sc->dma_pdev, -+ XCT_PTR_ADDR_LEN( -+ ring->desc[ -+ ring_idx + 1]), -+ PCI_DMA_TODEVICE); -+ ring->desc[ring_idx] = -+ ring->desc[ring_idx + 1] = 0; -+ ring->next_to_clean++; -+ } -+ } else { -+ for (j = 0; j < desc_size; j++) { -+ ring_idx = 2 * (ring->next_to_clean & (TX_RING_SIZE-1)); -+ ring->desc[ring_idx] = -+ ring->desc[ring_idx + 1] = 0; -+ ring->next_to_clean++; -+ } -+ } -+ } -+ -+ ring->total_pktcnt += delta_cnt; -+ } -+ spin_unlock_irqrestore(&ring->clean_lock, flags); -+ -+ return 0; -+} -+ -+static void sweepup_tx(struct pasemi_softc *sc) -+{ -+ int i; -+ -+ for (i = 0; i < sc->sc_num_channels; i++) -+ pasemi_clean_tx(sc, i); -+} -+ -+static irqreturn_t pasemi_intr(int irq, void *arg, struct pt_regs *regs) -+{ -+ struct pasemi_softc *sc = arg; -+ unsigned int reg; -+ int chan = irq - sc->base_irq; -+ int chan_index = sc->base_chan + chan; -+ u64 stat = dma_status->tx_sta[chan_index]; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (!(stat & PAS_STATUS_CAUSE_M)) -+ return IRQ_NONE; -+ -+ pasemi_clean_tx(sc, chan); -+ -+ stat = dma_status->tx_sta[chan_index]; -+ -+ reg = PAS_IOB_DMA_TXCH_RESET_PINTC | -+ PAS_IOB_DMA_TXCH_RESET_PCNT(sc->tx[chan].total_pktcnt); -+ -+ if (stat & PAS_STATUS_SOFT) -+ reg |= PAS_IOB_DMA_RXCH_RESET_SINTC; -+ -+ out_le32(sc->iob_regs + PAS_IOB_DMA_TXCH_RESET(chan_index), reg); -+ -+ -+ return IRQ_HANDLED; -+} -+ -+static int pasemi_dma_setup_tx_resources(struct pasemi_softc *sc, int chan) -+{ -+ u32 val; -+ int chan_index = chan + sc->base_chan; -+ int ret; -+ struct pasemi_fnu_txring *ring; -+ -+ ring = &sc->tx[chan]; -+ -+ spin_lock_init(&ring->fill_lock); -+ spin_lock_init(&ring->clean_lock); -+ -+ ring->desc_info = kzalloc(sizeof(struct pasemi_desc_info) * -+ TX_RING_SIZE, GFP_KERNEL); -+ if (!ring->desc_info) -+ return -ENOMEM; -+ -+ /* Allocate descriptors */ -+ ring->desc = dma_alloc_coherent(&sc->dma_pdev->dev, -+ TX_RING_SIZE * -+ 2 * sizeof(u64), -+ &ring->dma, GFP_KERNEL); -+ if (!ring->desc) -+ return -ENOMEM; -+ -+ memset((void *) ring->desc, 0, TX_RING_SIZE * 2 * sizeof(u64)); -+ -+ out_le32(sc->iob_regs + PAS_IOB_DMA_TXCH_RESET(chan_index), 0x30); -+ -+ ring->total_pktcnt = 0; -+ -+ out_le32(sc->dma_regs + PAS_DMA_TXCHAN_BASEL(chan_index), -+ PAS_DMA_TXCHAN_BASEL_BRBL(ring->dma)); -+ -+ val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->dma >> 32); -+ val |= PAS_DMA_TXCHAN_BASEU_SIZ(TX_RING_SIZE >> 2); -+ -+ out_le32(sc->dma_regs + PAS_DMA_TXCHAN_BASEU(chan_index), val); -+ -+ out_le32(sc->dma_regs + PAS_DMA_TXCHAN_CFG(chan_index), -+ PAS_DMA_TXCHAN_CFG_TY_FUNC | -+ PAS_DMA_TXCHAN_CFG_TATTR(chan) | -+ PAS_DMA_TXCHAN_CFG_WT(2)); -+ -+ /* enable tx channel */ -+ out_le32(sc->dma_regs + -+ PAS_DMA_TXCHAN_TCMDSTA(chan_index), -+ PAS_DMA_TXCHAN_TCMDSTA_EN); -+ -+ out_le32(sc->iob_regs + PAS_IOB_DMA_TXCH_CFG(chan_index), -+ PAS_IOB_DMA_TXCH_CFG_CNTTH(1000)); -+ -+ ring->next_to_fill = 0; -+ ring->next_to_clean = 0; -+ -+ snprintf(ring->irq_name, sizeof(ring->irq_name), -+ "%s%d", "crypto", chan); -+ -+ ring->irq = irq_create_mapping(NULL, sc->base_irq + chan); -+ ret = request_irq(ring->irq, (irq_handler_t) -+ pasemi_intr, IRQF_DISABLED, ring->irq_name, sc); -+ if (ret) { -+ printk(KERN_ERR DRV_NAME ": failed to hook irq %d ret %d\n", -+ ring->irq, ret); -+ ring->irq = -1; -+ return ret; -+ } -+ -+ setup_timer(&ring->crypto_timer, (void *) sweepup_tx, (unsigned long) sc); -+ -+ return 0; -+} -+ -+static device_method_t pasemi_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, pasemi_newsession), -+ DEVMETHOD(cryptodev_freesession, pasemi_freesession), -+ DEVMETHOD(cryptodev_process, pasemi_process), -+}; -+ -+/* Set up the crypto device structure, private data, -+ * and anything else we need before we start */ -+ -+static int __devinit -+pasemi_dma_probe(struct pci_dev *pdev, const struct pci_device_id *ent) -+{ -+ struct pasemi_softc *sc; -+ int ret, i; -+ -+ DPRINTF(KERN_ERR "%s()\n", __FUNCTION__); -+ -+ sc = kzalloc(sizeof(*sc), GFP_KERNEL); -+ if (!sc) -+ return -ENOMEM; -+ -+ softc_device_init(sc, DRV_NAME, 1, pasemi_methods); -+ -+ pci_set_drvdata(pdev, sc); -+ -+ spin_lock_init(&sc->sc_chnlock); -+ -+ sc->sc_sessions = (struct pasemi_session **) -+ kzalloc(PASEMI_INITIAL_SESSIONS * -+ sizeof(struct pasemi_session *), GFP_ATOMIC); -+ if (sc->sc_sessions == NULL) { -+ ret = -ENOMEM; -+ goto out; -+ } -+ -+ sc->sc_nsessions = PASEMI_INITIAL_SESSIONS; -+ sc->sc_lastchn = 0; -+ sc->base_irq = pdev->irq + 6; -+ sc->base_chan = 6; -+ sc->sc_cid = -1; -+ sc->dma_pdev = pdev; -+ -+ sc->iob_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL); -+ if (!sc->iob_pdev) { -+ dev_err(&pdev->dev, "Can't find I/O Bridge\n"); -+ ret = -ENODEV; -+ goto out; -+ } -+ -+ /* This is hardcoded and ugly, but we have some firmware versions -+ * who don't provide the register space in the device tree. Luckily -+ * they are at well-known locations so we can just do the math here. -+ */ -+ sc->dma_regs = -+ ioremap(0xe0000000 + (sc->dma_pdev->devfn << 12), 0x2000); -+ sc->iob_regs = -+ ioremap(0xe0000000 + (sc->iob_pdev->devfn << 12), 0x2000); -+ if (!sc->dma_regs || !sc->iob_regs) { -+ dev_err(&pdev->dev, "Can't map registers\n"); -+ ret = -ENODEV; -+ goto out; -+ } -+ -+ dma_status = __ioremap(0xfd800000, 0x1000, 0); -+ if (!dma_status) { -+ ret = -ENODEV; -+ dev_err(&pdev->dev, "Can't map dmastatus space\n"); -+ goto out; -+ } -+ -+ sc->tx = (struct pasemi_fnu_txring *) -+ kzalloc(sizeof(struct pasemi_fnu_txring) -+ * 8, GFP_KERNEL); -+ if (!sc->tx) { -+ ret = -ENOMEM; -+ goto out; -+ } -+ -+ /* Initialize the h/w */ -+ out_le32(sc->dma_regs + PAS_DMA_COM_CFG, -+ (in_le32(sc->dma_regs + PAS_DMA_COM_CFG) | -+ PAS_DMA_COM_CFG_FWF)); -+ out_le32(sc->dma_regs + PAS_DMA_COM_TXCMD, PAS_DMA_COM_TXCMD_EN); -+ -+ for (i = 0; i < PASEMI_FNU_CHANNELS; i++) { -+ sc->sc_num_channels++; -+ ret = pasemi_dma_setup_tx_resources(sc, i); -+ if (ret) -+ goto out; -+ } -+ -+ sc->sc_cid = crypto_get_driverid(softc_get_device(sc), -+ CRYPTOCAP_F_HARDWARE); -+ if (sc->sc_cid < 0) { -+ printk(KERN_ERR DRV_NAME ": could not get crypto driver id\n"); -+ ret = -ENXIO; -+ goto out; -+ } -+ -+ /* register algorithms with the framework */ -+ printk(DRV_NAME ":"); -+ -+ crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); -+ -+ return 0; -+ -+out: -+ pasemi_dma_remove(pdev); -+ return ret; -+} -+ -+#define MAX_RETRIES 5000 -+ -+static void pasemi_free_tx_resources(struct pasemi_softc *sc, int chan) -+{ -+ struct pasemi_fnu_txring *ring = &sc->tx[chan]; -+ int chan_index = chan + sc->base_chan; -+ int retries; -+ u32 stat; -+ -+ /* Stop the channel */ -+ out_le32(sc->dma_regs + -+ PAS_DMA_TXCHAN_TCMDSTA(chan_index), -+ PAS_DMA_TXCHAN_TCMDSTA_ST); -+ -+ for (retries = 0; retries < MAX_RETRIES; retries++) { -+ stat = in_le32(sc->dma_regs + -+ PAS_DMA_TXCHAN_TCMDSTA(chan_index)); -+ if (!(stat & PAS_DMA_TXCHAN_TCMDSTA_ACT)) -+ break; -+ cond_resched(); -+ } -+ -+ if (stat & PAS_DMA_TXCHAN_TCMDSTA_ACT) -+ dev_err(&sc->dma_pdev->dev, "Failed to stop tx channel %d\n", -+ chan_index); -+ -+ /* Disable the channel */ -+ out_le32(sc->dma_regs + -+ PAS_DMA_TXCHAN_TCMDSTA(chan_index), -+ 0); -+ -+ if (ring->desc_info) -+ kfree((void *) ring->desc_info); -+ if (ring->desc) -+ dma_free_coherent(&sc->dma_pdev->dev, -+ TX_RING_SIZE * -+ 2 * sizeof(u64), -+ (void *) ring->desc, ring->dma); -+ if (ring->irq != -1) -+ free_irq(ring->irq, sc); -+ -+ del_timer(&ring->crypto_timer); -+} -+ -+static void __devexit pasemi_dma_remove(struct pci_dev *pdev) -+{ -+ struct pasemi_softc *sc = pci_get_drvdata(pdev); -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (sc->sc_cid >= 0) { -+ crypto_unregister_all(sc->sc_cid); -+ } -+ -+ if (sc->tx) { -+ for (i = 0; i < sc->sc_num_channels; i++) -+ pasemi_free_tx_resources(sc, i); -+ -+ kfree(sc->tx); -+ } -+ if (sc->sc_sessions) { -+ for (i = 0; i < sc->sc_nsessions; i++) -+ kfree(sc->sc_sessions[i]); -+ kfree(sc->sc_sessions); -+ } -+ if (sc->iob_pdev) -+ pci_dev_put(sc->iob_pdev); -+ if (sc->dma_regs) -+ iounmap(sc->dma_regs); -+ if (sc->iob_regs) -+ iounmap(sc->iob_regs); -+ kfree(sc); -+} -+ -+static struct pci_device_id pasemi_dma_pci_tbl[] = { -+ { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa007) }, -+}; -+ -+MODULE_DEVICE_TABLE(pci, pasemi_dma_pci_tbl); -+ -+static struct pci_driver pasemi_dma_driver = { -+ .name = "pasemi_dma", -+ .id_table = pasemi_dma_pci_tbl, -+ .probe = pasemi_dma_probe, -+ .remove = __devexit_p(pasemi_dma_remove), -+}; -+ -+static void __exit pasemi_dma_cleanup_module(void) -+{ -+ pci_unregister_driver(&pasemi_dma_driver); -+ __iounmap(dma_status); -+ dma_status = NULL; -+} -+ -+int pasemi_dma_init_module(void) -+{ -+ return pci_register_driver(&pasemi_dma_driver); -+} -+ -+module_init(pasemi_dma_init_module); -+module_exit(pasemi_dma_cleanup_module); -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_AUTHOR("Egor Martovetsky egor@pasemi.com"); -+MODULE_DESCRIPTION("OCF driver for PA Semi PWRficient DMA Crypto Engine"); -diff -Nur linux-3.0.4.orig/crypto/ocf/pasemi/pasemi_fnu.h linux-3.0.4/crypto/ocf/pasemi/pasemi_fnu.h ---- linux-3.0.4.orig/crypto/ocf/pasemi/pasemi_fnu.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/pasemi/pasemi_fnu.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,410 @@ -+/* -+ * Copyright (C) 2007 PA Semi, Inc -+ * -+ * Driver for the PA Semi PWRficient DMA Crypto Engine, soft state and -+ * hardware register layouts. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef PASEMI_FNU_H -+#define PASEMI_FNU_H -+ -+#include -+ -+#define PASEMI_SESSION(sid) ((sid) & 0xffffffff) -+#define PASEMI_SID(sesn) ((sesn) & 0xffffffff) -+#define DPRINTF(a...) if (debug) { printk(DRV_NAME ": " a); } -+ -+/* Must be a power of two */ -+#define RX_RING_SIZE 512 -+#define TX_RING_SIZE 512 -+#define TX_DESC(ring, num) ((ring)->desc[2 * (num & (TX_RING_SIZE-1))]) -+#define TX_DESC_INFO(ring, num) ((ring)->desc_info[(num) & (TX_RING_SIZE-1)]) -+#define MAX_DESC_SIZE 8 -+#define PASEMI_INITIAL_SESSIONS 10 -+#define PASEMI_FNU_CHANNELS 8 -+ -+/* DMA descriptor */ -+struct pasemi_desc { -+ u64 quad[2*MAX_DESC_SIZE]; -+ int quad_cnt; -+ int size; -+ int postop; -+}; -+ -+/* -+ * Holds per descriptor data -+ */ -+struct pasemi_desc_info { -+ int desc_size; -+ int desc_postop; -+#define PASEMI_CHECK_SIG 0x1 -+ -+ struct cryptop *cf_crp; -+}; -+ -+/* -+ * Holds per channel data -+ */ -+struct pasemi_fnu_txring { -+ volatile u64 *desc; -+ volatile struct -+ pasemi_desc_info *desc_info; -+ dma_addr_t dma; -+ struct timer_list crypto_timer; -+ spinlock_t fill_lock; -+ spinlock_t clean_lock; -+ unsigned int next_to_fill; -+ unsigned int next_to_clean; -+ u16 total_pktcnt; -+ int irq; -+ int sesn; -+ char irq_name[10]; -+}; -+ -+/* -+ * Holds data specific to a single pasemi device. -+ */ -+struct pasemi_softc { -+ softc_device_decl sc_cdev; -+ struct pci_dev *dma_pdev; /* device backpointer */ -+ struct pci_dev *iob_pdev; /* device backpointer */ -+ void __iomem *dma_regs; -+ void __iomem *iob_regs; -+ int base_irq; -+ int base_chan; -+ int32_t sc_cid; /* crypto tag */ -+ int sc_nsessions; -+ struct pasemi_session **sc_sessions; -+ int sc_num_channels;/* number of crypto channels */ -+ -+ /* pointer to the array of txring datastructures, one txring per channel */ -+ struct pasemi_fnu_txring *tx; -+ -+ /* -+ * mutual exclusion for the channel scheduler -+ */ -+ spinlock_t sc_chnlock; -+ /* last channel used, for now use round-robin to allocate channels */ -+ int sc_lastchn; -+}; -+ -+struct pasemi_session { -+ u64 civ[2]; -+ u64 keysz; -+ u64 key[4]; -+ u64 ccmd; -+ u64 hkey[4]; -+ u64 hseq; -+ u64 giv[2]; -+ u64 hiv[4]; -+ -+ int used; -+ dma_addr_t dma_addr; -+ int chan; -+}; -+ -+/* status register layout in IOB region, at 0xfd800000 */ -+struct pasdma_status { -+ u64 rx_sta[64]; -+ u64 tx_sta[20]; -+}; -+ -+#define ALG_IS_CIPHER(alg) ((alg == CRYPTO_DES_CBC) || \ -+ (alg == CRYPTO_3DES_CBC) || \ -+ (alg == CRYPTO_AES_CBC) || \ -+ (alg == CRYPTO_ARC4) || \ -+ (alg == CRYPTO_NULL_CBC)) -+ -+#define ALG_IS_SIG(alg) ((alg == CRYPTO_MD5) || \ -+ (alg == CRYPTO_MD5_HMAC) || \ -+ (alg == CRYPTO_SHA1) || \ -+ (alg == CRYPTO_SHA1_HMAC) || \ -+ (alg == CRYPTO_NULL_HMAC)) -+ -+enum { -+ PAS_DMA_COM_TXCMD = 0x100, /* Transmit Command Register */ -+ PAS_DMA_COM_TXSTA = 0x104, /* Transmit Status Register */ -+ PAS_DMA_COM_RXCMD = 0x108, /* Receive Command Register */ -+ PAS_DMA_COM_RXSTA = 0x10c, /* Receive Status Register */ -+ PAS_DMA_COM_CFG = 0x114, /* DMA Configuration Register */ -+}; -+ -+/* All these registers live in the PCI configuration space for the DMA PCI -+ * device. Use the normal PCI config access functions for them. -+ */ -+ -+#define PAS_DMA_COM_CFG_FWF 0x18000000 -+ -+#define PAS_DMA_COM_TXCMD_EN 0x00000001 /* enable */ -+#define PAS_DMA_COM_TXSTA_ACT 0x00000001 /* active */ -+#define PAS_DMA_COM_RXCMD_EN 0x00000001 /* enable */ -+#define PAS_DMA_COM_RXSTA_ACT 0x00000001 /* active */ -+ -+#define _PAS_DMA_TXCHAN_STRIDE 0x20 /* Size per channel */ -+#define _PAS_DMA_TXCHAN_TCMDSTA 0x300 /* Command / Status */ -+#define _PAS_DMA_TXCHAN_CFG 0x304 /* Configuration */ -+#define _PAS_DMA_TXCHAN_DSCRBU 0x308 /* Descriptor BU Allocation */ -+#define _PAS_DMA_TXCHAN_INCR 0x310 /* Descriptor increment */ -+#define _PAS_DMA_TXCHAN_CNT 0x314 /* Descriptor count/offset */ -+#define _PAS_DMA_TXCHAN_BASEL 0x318 /* Descriptor ring base (low) */ -+#define _PAS_DMA_TXCHAN_BASEU 0x31c /* (high) */ -+#define PAS_DMA_TXCHAN_TCMDSTA(c) (0x300+(c)*_PAS_DMA_TXCHAN_STRIDE) -+#define PAS_DMA_TXCHAN_TCMDSTA_EN 0x00000001 /* Enabled */ -+#define PAS_DMA_TXCHAN_TCMDSTA_ST 0x00000002 /* Stop interface */ -+#define PAS_DMA_TXCHAN_TCMDSTA_ACT 0x00010000 /* Active */ -+#define PAS_DMA_TXCHAN_CFG(c) (0x304+(c)*_PAS_DMA_TXCHAN_STRIDE) -+#define PAS_DMA_TXCHAN_CFG_TY_FUNC 0x00000002 /* Type = interface */ -+#define PAS_DMA_TXCHAN_CFG_TY_IFACE 0x00000000 /* Type = interface */ -+#define PAS_DMA_TXCHAN_CFG_TATTR_M 0x0000003c -+#define PAS_DMA_TXCHAN_CFG_TATTR_S 2 -+#define PAS_DMA_TXCHAN_CFG_TATTR(x) (((x) << PAS_DMA_TXCHAN_CFG_TATTR_S) & \ -+ PAS_DMA_TXCHAN_CFG_TATTR_M) -+#define PAS_DMA_TXCHAN_CFG_WT_M 0x000001c0 -+#define PAS_DMA_TXCHAN_CFG_WT_S 6 -+#define PAS_DMA_TXCHAN_CFG_WT(x) (((x) << PAS_DMA_TXCHAN_CFG_WT_S) & \ -+ PAS_DMA_TXCHAN_CFG_WT_M) -+#define PAS_DMA_TXCHAN_CFG_LPSQ_FAST 0x00000400 -+#define PAS_DMA_TXCHAN_CFG_LPDQ_FAST 0x00000800 -+#define PAS_DMA_TXCHAN_CFG_CF 0x00001000 /* Clean first line */ -+#define PAS_DMA_TXCHAN_CFG_CL 0x00002000 /* Clean last line */ -+#define PAS_DMA_TXCHAN_CFG_UP 0x00004000 /* update tx descr when sent */ -+#define PAS_DMA_TXCHAN_INCR(c) (0x310+(c)*_PAS_DMA_TXCHAN_STRIDE) -+#define PAS_DMA_TXCHAN_BASEL(c) (0x318+(c)*_PAS_DMA_TXCHAN_STRIDE) -+#define PAS_DMA_TXCHAN_BASEL_BRBL_M 0xffffffc0 -+#define PAS_DMA_TXCHAN_BASEL_BRBL_S 0 -+#define PAS_DMA_TXCHAN_BASEL_BRBL(x) (((x) << PAS_DMA_TXCHAN_BASEL_BRBL_S) & \ -+ PAS_DMA_TXCHAN_BASEL_BRBL_M) -+#define PAS_DMA_TXCHAN_BASEU(c) (0x31c+(c)*_PAS_DMA_TXCHAN_STRIDE) -+#define PAS_DMA_TXCHAN_BASEU_BRBH_M 0x00000fff -+#define PAS_DMA_TXCHAN_BASEU_BRBH_S 0 -+#define PAS_DMA_TXCHAN_BASEU_BRBH(x) (((x) << PAS_DMA_TXCHAN_BASEU_BRBH_S) & \ -+ PAS_DMA_TXCHAN_BASEU_BRBH_M) -+/* # of cache lines worth of buffer ring */ -+#define PAS_DMA_TXCHAN_BASEU_SIZ_M 0x3fff0000 -+#define PAS_DMA_TXCHAN_BASEU_SIZ_S 16 /* 0 = 16K */ -+#define PAS_DMA_TXCHAN_BASEU_SIZ(x) (((x) << PAS_DMA_TXCHAN_BASEU_SIZ_S) & \ -+ PAS_DMA_TXCHAN_BASEU_SIZ_M) -+ -+#define PAS_STATUS_PCNT_M 0x000000000000ffffull -+#define PAS_STATUS_PCNT_S 0 -+#define PAS_STATUS_DCNT_M 0x00000000ffff0000ull -+#define PAS_STATUS_DCNT_S 16 -+#define PAS_STATUS_BPCNT_M 0x0000ffff00000000ull -+#define PAS_STATUS_BPCNT_S 32 -+#define PAS_STATUS_CAUSE_M 0xf000000000000000ull -+#define PAS_STATUS_TIMER 0x1000000000000000ull -+#define PAS_STATUS_ERROR 0x2000000000000000ull -+#define PAS_STATUS_SOFT 0x4000000000000000ull -+#define PAS_STATUS_INT 0x8000000000000000ull -+ -+#define PAS_IOB_DMA_RXCH_CFG(i) (0x1100 + (i)*4) -+#define PAS_IOB_DMA_RXCH_CFG_CNTTH_M 0x00000fff -+#define PAS_IOB_DMA_RXCH_CFG_CNTTH_S 0 -+#define PAS_IOB_DMA_RXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_RXCH_CFG_CNTTH_S) & \ -+ PAS_IOB_DMA_RXCH_CFG_CNTTH_M) -+#define PAS_IOB_DMA_TXCH_CFG(i) (0x1200 + (i)*4) -+#define PAS_IOB_DMA_TXCH_CFG_CNTTH_M 0x00000fff -+#define PAS_IOB_DMA_TXCH_CFG_CNTTH_S 0 -+#define PAS_IOB_DMA_TXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_TXCH_CFG_CNTTH_S) & \ -+ PAS_IOB_DMA_TXCH_CFG_CNTTH_M) -+#define PAS_IOB_DMA_RXCH_STAT(i) (0x1300 + (i)*4) -+#define PAS_IOB_DMA_RXCH_STAT_INTGEN 0x00001000 -+#define PAS_IOB_DMA_RXCH_STAT_CNTDEL_M 0x00000fff -+#define PAS_IOB_DMA_RXCH_STAT_CNTDEL_S 0 -+#define PAS_IOB_DMA_RXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_RXCH_STAT_CNTDEL_S) &\ -+ PAS_IOB_DMA_RXCH_STAT_CNTDEL_M) -+#define PAS_IOB_DMA_TXCH_STAT(i) (0x1400 + (i)*4) -+#define PAS_IOB_DMA_TXCH_STAT_INTGEN 0x00001000 -+#define PAS_IOB_DMA_TXCH_STAT_CNTDEL_M 0x00000fff -+#define PAS_IOB_DMA_TXCH_STAT_CNTDEL_S 0 -+#define PAS_IOB_DMA_TXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_TXCH_STAT_CNTDEL_S) &\ -+ PAS_IOB_DMA_TXCH_STAT_CNTDEL_M) -+#define PAS_IOB_DMA_RXCH_RESET(i) (0x1500 + (i)*4) -+#define PAS_IOB_DMA_RXCH_RESET_PCNT_M 0xffff0000 -+#define PAS_IOB_DMA_RXCH_RESET_PCNT_S 16 -+#define PAS_IOB_DMA_RXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_RXCH_RESET_PCNT_S) & \ -+ PAS_IOB_DMA_RXCH_RESET_PCNT_M) -+#define PAS_IOB_DMA_RXCH_RESET_PCNTRST 0x00000020 -+#define PAS_IOB_DMA_RXCH_RESET_DCNTRST 0x00000010 -+#define PAS_IOB_DMA_RXCH_RESET_TINTC 0x00000008 -+#define PAS_IOB_DMA_RXCH_RESET_DINTC 0x00000004 -+#define PAS_IOB_DMA_RXCH_RESET_SINTC 0x00000002 -+#define PAS_IOB_DMA_RXCH_RESET_PINTC 0x00000001 -+#define PAS_IOB_DMA_TXCH_RESET(i) (0x1600 + (i)*4) -+#define PAS_IOB_DMA_TXCH_RESET_PCNT_M 0xffff0000 -+#define PAS_IOB_DMA_TXCH_RESET_PCNT_S 16 -+#define PAS_IOB_DMA_TXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_TXCH_RESET_PCNT_S) & \ -+ PAS_IOB_DMA_TXCH_RESET_PCNT_M) -+#define PAS_IOB_DMA_TXCH_RESET_PCNTRST 0x00000020 -+#define PAS_IOB_DMA_TXCH_RESET_DCNTRST 0x00000010 -+#define PAS_IOB_DMA_TXCH_RESET_TINTC 0x00000008 -+#define PAS_IOB_DMA_TXCH_RESET_DINTC 0x00000004 -+#define PAS_IOB_DMA_TXCH_RESET_SINTC 0x00000002 -+#define PAS_IOB_DMA_TXCH_RESET_PINTC 0x00000001 -+ -+#define PAS_IOB_DMA_COM_TIMEOUTCFG 0x1700 -+#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M 0x00ffffff -+#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S 0 -+#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(x) (((x) << PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S) & \ -+ PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M) -+ -+/* Transmit descriptor fields */ -+#define XCT_MACTX_T 0x8000000000000000ull -+#define XCT_MACTX_ST 0x4000000000000000ull -+#define XCT_MACTX_NORES 0x0000000000000000ull -+#define XCT_MACTX_8BRES 0x1000000000000000ull -+#define XCT_MACTX_24BRES 0x2000000000000000ull -+#define XCT_MACTX_40BRES 0x3000000000000000ull -+#define XCT_MACTX_I 0x0800000000000000ull -+#define XCT_MACTX_O 0x0400000000000000ull -+#define XCT_MACTX_E 0x0200000000000000ull -+#define XCT_MACTX_VLAN_M 0x0180000000000000ull -+#define XCT_MACTX_VLAN_NOP 0x0000000000000000ull -+#define XCT_MACTX_VLAN_REMOVE 0x0080000000000000ull -+#define XCT_MACTX_VLAN_INSERT 0x0100000000000000ull -+#define XCT_MACTX_VLAN_REPLACE 0x0180000000000000ull -+#define XCT_MACTX_CRC_M 0x0060000000000000ull -+#define XCT_MACTX_CRC_NOP 0x0000000000000000ull -+#define XCT_MACTX_CRC_INSERT 0x0020000000000000ull -+#define XCT_MACTX_CRC_PAD 0x0040000000000000ull -+#define XCT_MACTX_CRC_REPLACE 0x0060000000000000ull -+#define XCT_MACTX_SS 0x0010000000000000ull -+#define XCT_MACTX_LLEN_M 0x00007fff00000000ull -+#define XCT_MACTX_LLEN_S 32ull -+#define XCT_MACTX_LLEN(x) ((((long)(x)) << XCT_MACTX_LLEN_S) & \ -+ XCT_MACTX_LLEN_M) -+#define XCT_MACTX_IPH_M 0x00000000f8000000ull -+#define XCT_MACTX_IPH_S 27ull -+#define XCT_MACTX_IPH(x) ((((long)(x)) << XCT_MACTX_IPH_S) & \ -+ XCT_MACTX_IPH_M) -+#define XCT_MACTX_IPO_M 0x0000000007c00000ull -+#define XCT_MACTX_IPO_S 22ull -+#define XCT_MACTX_IPO(x) ((((long)(x)) << XCT_MACTX_IPO_S) & \ -+ XCT_MACTX_IPO_M) -+#define XCT_MACTX_CSUM_M 0x0000000000000060ull -+#define XCT_MACTX_CSUM_NOP 0x0000000000000000ull -+#define XCT_MACTX_CSUM_TCP 0x0000000000000040ull -+#define XCT_MACTX_CSUM_UDP 0x0000000000000060ull -+#define XCT_MACTX_V6 0x0000000000000010ull -+#define XCT_MACTX_C 0x0000000000000004ull -+#define XCT_MACTX_AL2 0x0000000000000002ull -+ -+#define XCT_PTR_T 0x8000000000000000ull -+#define XCT_PTR_LEN_M 0x7ffff00000000000ull -+#define XCT_PTR_LEN_S 44 -+#define XCT_PTR_LEN(x) ((((long)(x)) << XCT_PTR_LEN_S) & \ -+ XCT_PTR_LEN_M) -+#define XCT_PTR_ADDR_M 0x00000fffffffffffull -+#define XCT_PTR_ADDR_S 0 -+#define XCT_PTR_ADDR(x) ((((long)(x)) << XCT_PTR_ADDR_S) & \ -+ XCT_PTR_ADDR_M) -+ -+/* Function descriptor fields */ -+#define XCT_FUN_T 0x8000000000000000ull -+#define XCT_FUN_ST 0x4000000000000000ull -+#define XCT_FUN_NORES 0x0000000000000000ull -+#define XCT_FUN_8BRES 0x1000000000000000ull -+#define XCT_FUN_24BRES 0x2000000000000000ull -+#define XCT_FUN_40BRES 0x3000000000000000ull -+#define XCT_FUN_I 0x0800000000000000ull -+#define XCT_FUN_O 0x0400000000000000ull -+#define XCT_FUN_E 0x0200000000000000ull -+#define XCT_FUN_FUN_S 54 -+#define XCT_FUN_FUN_M 0x01c0000000000000ull -+#define XCT_FUN_FUN(num) ((((long)(num)) << XCT_FUN_FUN_S) & \ -+ XCT_FUN_FUN_M) -+#define XCT_FUN_CRM_NOP 0x0000000000000000ull -+#define XCT_FUN_CRM_SIG 0x0008000000000000ull -+#define XCT_FUN_CRM_ENC 0x0010000000000000ull -+#define XCT_FUN_CRM_DEC 0x0018000000000000ull -+#define XCT_FUN_CRM_SIG_ENC 0x0020000000000000ull -+#define XCT_FUN_CRM_ENC_SIG 0x0028000000000000ull -+#define XCT_FUN_CRM_SIG_DEC 0x0030000000000000ull -+#define XCT_FUN_CRM_DEC_SIG 0x0038000000000000ull -+#define XCT_FUN_LLEN_M 0x0007ffff00000000ull -+#define XCT_FUN_LLEN_S 32ULL -+#define XCT_FUN_LLEN(x) ((((long)(x)) << XCT_FUN_LLEN_S) & \ -+ XCT_FUN_LLEN_M) -+#define XCT_FUN_SHL_M 0x00000000f8000000ull -+#define XCT_FUN_SHL_S 27ull -+#define XCT_FUN_SHL(x) ((((long)(x)) << XCT_FUN_SHL_S) & \ -+ XCT_FUN_SHL_M) -+#define XCT_FUN_CHL_M 0x0000000007c00000ull -+#define XCT_FUN_CHL_S 22ull -+#define XCT_FUN_CHL(x) ((((long)(x)) << XCT_FUN_CHL_S) & \ -+ XCT_FUN_CHL_M) -+#define XCT_FUN_HSZ_M 0x00000000003c0000ull -+#define XCT_FUN_HSZ_S 18ull -+#define XCT_FUN_HSZ(x) ((((long)(x)) << XCT_FUN_HSZ_S) & \ -+ XCT_FUN_HSZ_M) -+#define XCT_FUN_ALG_DES 0x0000000000000000ull -+#define XCT_FUN_ALG_3DES 0x0000000000008000ull -+#define XCT_FUN_ALG_AES 0x0000000000010000ull -+#define XCT_FUN_ALG_ARC 0x0000000000018000ull -+#define XCT_FUN_ALG_KASUMI 0x0000000000020000ull -+#define XCT_FUN_BCM_ECB 0x0000000000000000ull -+#define XCT_FUN_BCM_CBC 0x0000000000001000ull -+#define XCT_FUN_BCM_CFB 0x0000000000002000ull -+#define XCT_FUN_BCM_OFB 0x0000000000003000ull -+#define XCT_FUN_BCM_CNT 0x0000000000003800ull -+#define XCT_FUN_BCM_KAS_F8 0x0000000000002800ull -+#define XCT_FUN_BCM_KAS_F9 0x0000000000001800ull -+#define XCT_FUN_BCP_NO_PAD 0x0000000000000000ull -+#define XCT_FUN_BCP_ZRO 0x0000000000000200ull -+#define XCT_FUN_BCP_PL 0x0000000000000400ull -+#define XCT_FUN_BCP_INCR 0x0000000000000600ull -+#define XCT_FUN_SIG_MD5 (0ull << 4) -+#define XCT_FUN_SIG_SHA1 (2ull << 4) -+#define XCT_FUN_SIG_HMAC_MD5 (8ull << 4) -+#define XCT_FUN_SIG_HMAC_SHA1 (10ull << 4) -+#define XCT_FUN_A 0x0000000000000008ull -+#define XCT_FUN_C 0x0000000000000004ull -+#define XCT_FUN_AL2 0x0000000000000002ull -+#define XCT_FUN_SE 0x0000000000000001ull -+ -+#define XCT_FUN_SRC_PTR(len, addr) (XCT_PTR_LEN(len) | XCT_PTR_ADDR(addr)) -+#define XCT_FUN_DST_PTR(len, addr) (XCT_FUN_SRC_PTR(len, addr) | \ -+ 0x8000000000000000ull) -+ -+#define XCT_CTRL_HDR_FUN_NUM_M 0x01c0000000000000ull -+#define XCT_CTRL_HDR_FUN_NUM_S 54 -+#define XCT_CTRL_HDR_LEN_M 0x0007ffff00000000ull -+#define XCT_CTRL_HDR_LEN_S 32 -+#define XCT_CTRL_HDR_REG_M 0x00000000000000ffull -+#define XCT_CTRL_HDR_REG_S 0 -+ -+#define XCT_CTRL_HDR(funcN,len,reg) (0x9400000000000000ull | \ -+ ((((long)(funcN)) << XCT_CTRL_HDR_FUN_NUM_S) \ -+ & XCT_CTRL_HDR_FUN_NUM_M) | \ -+ ((((long)(len)) << \ -+ XCT_CTRL_HDR_LEN_S) & XCT_CTRL_HDR_LEN_M) | \ -+ ((((long)(reg)) << \ -+ XCT_CTRL_HDR_REG_S) & XCT_CTRL_HDR_REG_M)) -+ -+/* Function config command options */ -+#define DMA_CALGO_DES 0x00 -+#define DMA_CALGO_3DES 0x01 -+#define DMA_CALGO_AES 0x02 -+#define DMA_CALGO_ARC 0x03 -+ -+#define DMA_FN_CIV0 0x02 -+#define DMA_FN_CIV1 0x03 -+#define DMA_FN_HKEY0 0x0a -+ -+#define XCT_PTR_ADDR_LEN(ptr) ((ptr) & XCT_PTR_ADDR_M), \ -+ (((ptr) & XCT_PTR_LEN_M) >> XCT_PTR_LEN_S) -+ -+#endif /* PASEMI_FNU_H */ -diff -Nur linux-3.0.4.orig/crypto/ocf/random.c linux-3.0.4/crypto/ocf/random.c ---- linux-3.0.4.orig/crypto/ocf/random.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/random.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,317 @@ -+/* -+ * A system independant way of adding entropy to the kernels pool -+ * this way the drivers can focus on the real work and we can take -+ * care of pushing it to the appropriate place in the kernel. -+ * -+ * This should be fast and callable from timers/interrupts -+ * -+ * Written by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * ALTERNATIVELY, provided that this notice is retained in full, this product -+ * may be distributed under the terms of the GNU General Public License (GPL), -+ * in which case the provisions of the GPL apply INSTEAD OF those given above. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ */ -+ -+#include -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#ifdef CONFIG_OCF_FIPS -+#include "rndtest.h" -+#endif -+ -+#ifndef HAS_RANDOM_INPUT_WAIT -+#error "Please do not enable OCF_RANDOMHARVEST unless you have applied patches" -+#endif -+ -+/* -+ * a hack to access the debug levels from the crypto driver -+ */ -+extern int crypto_debug; -+#define debug crypto_debug -+ -+/* -+ * a list of all registered random providers -+ */ -+static LIST_HEAD(random_ops); -+static int started = 0; -+static int initted = 0; -+ -+struct random_op { -+ struct list_head random_list; -+ u_int32_t driverid; -+ int (*read_random)(void *arg, u_int32_t *buf, int len); -+ void *arg; -+}; -+ -+static int random_proc(void *arg); -+ -+static pid_t randomproc = (pid_t) -1; -+static spinlock_t random_lock; -+ -+/* -+ * just init the spin locks -+ */ -+static int -+crypto_random_init(void) -+{ -+ spin_lock_init(&random_lock); -+ initted = 1; -+ return(0); -+} -+ -+/* -+ * Add the given random reader to our list (if not present) -+ * and start the thread (if not already started) -+ * -+ * we have to assume that driver id is ok for now -+ */ -+int -+crypto_rregister( -+ u_int32_t driverid, -+ int (*read_random)(void *arg, u_int32_t *buf, int len), -+ void *arg) -+{ -+ unsigned long flags; -+ int ret = 0; -+ struct random_op *rops, *tmp; -+ -+ dprintk("%s,%d: %s(0x%x, %p, %p)\n", __FILE__, __LINE__, -+ __FUNCTION__, driverid, read_random, arg); -+ -+ if (!initted) -+ crypto_random_init(); -+ -+#if 0 -+ struct cryptocap *cap; -+ -+ cap = crypto_checkdriver(driverid); -+ if (!cap) -+ return EINVAL; -+#endif -+ -+ list_for_each_entry_safe(rops, tmp, &random_ops, random_list) { -+ if (rops->driverid == driverid && rops->read_random == read_random) -+ return EEXIST; -+ } -+ -+ rops = (struct random_op *) kmalloc(sizeof(*rops), GFP_KERNEL); -+ if (!rops) -+ return ENOMEM; -+ -+ rops->driverid = driverid; -+ rops->read_random = read_random; -+ rops->arg = arg; -+ -+ spin_lock_irqsave(&random_lock, flags); -+ list_add_tail(&rops->random_list, &random_ops); -+ if (!started) { -+ randomproc = kernel_thread(random_proc, NULL, CLONE_FS|CLONE_FILES); -+ if (randomproc < 0) { -+ ret = randomproc; -+ printk("crypto: crypto_rregister cannot start random thread; " -+ "error %d", ret); -+ } else -+ started = 1; -+ } -+ spin_unlock_irqrestore(&random_lock, flags); -+ -+ return ret; -+} -+EXPORT_SYMBOL(crypto_rregister); -+ -+int -+crypto_runregister_all(u_int32_t driverid) -+{ -+ struct random_op *rops, *tmp; -+ unsigned long flags; -+ -+ dprintk("%s,%d: %s(0x%x)\n", __FILE__, __LINE__, __FUNCTION__, driverid); -+ -+ list_for_each_entry_safe(rops, tmp, &random_ops, random_list) { -+ if (rops->driverid == driverid) { -+ list_del(&rops->random_list); -+ kfree(rops); -+ } -+ } -+ -+ spin_lock_irqsave(&random_lock, flags); -+ if (list_empty(&random_ops) && started) -+ kill_proc(randomproc, SIGKILL, 1); -+ spin_unlock_irqrestore(&random_lock, flags); -+ return(0); -+} -+EXPORT_SYMBOL(crypto_runregister_all); -+ -+/* -+ * while we can add entropy to random.c continue to read random data from -+ * the drivers and push it to random. -+ */ -+static int -+random_proc(void *arg) -+{ -+ int n; -+ int wantcnt; -+ int bufcnt = 0; -+ int retval = 0; -+ int *buf = NULL; -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ daemonize(); -+ spin_lock_irq(¤t->sigmask_lock); -+ sigemptyset(¤t->blocked); -+ recalc_sigpending(current); -+ spin_unlock_irq(¤t->sigmask_lock); -+ sprintf(current->comm, "ocf-random"); -+#else -+ daemonize("ocf-random"); -+ allow_signal(SIGKILL); -+#endif -+ -+ (void) get_fs(); -+ set_fs(get_ds()); -+ -+#ifdef CONFIG_OCF_FIPS -+#define NUM_INT (RNDTEST_NBYTES/sizeof(int)) -+#else -+#define NUM_INT 32 -+#endif -+ -+ /* -+ * some devices can transferr their RNG data direct into memory, -+ * so make sure it is device friendly -+ */ -+ buf = kmalloc(NUM_INT * sizeof(int), GFP_DMA); -+ if (NULL == buf) { -+ printk("crypto: RNG could not allocate memory\n"); -+ retval = -ENOMEM; -+ goto bad_alloc; -+ } -+ -+ wantcnt = NUM_INT; /* start by adding some entropy */ -+ -+ /* -+ * its possible due to errors or driver removal that we no longer -+ * have anything to do, if so exit or we will consume all the CPU -+ * doing nothing -+ */ -+ while (!list_empty(&random_ops)) { -+ struct random_op *rops, *tmp; -+ -+#ifdef CONFIG_OCF_FIPS -+ if (wantcnt) -+ wantcnt = NUM_INT; /* FIPs mode can do 20000 bits or none */ -+#endif -+ -+ /* see if we can get enough entropy to make the world -+ * a better place. -+ */ -+ while (bufcnt < wantcnt && bufcnt < NUM_INT) { -+ list_for_each_entry_safe(rops, tmp, &random_ops, random_list) { -+ -+ n = (*rops->read_random)(rops->arg, &buf[bufcnt], -+ NUM_INT - bufcnt); -+ -+ /* on failure remove the random number generator */ -+ if (n == -1) { -+ list_del(&rops->random_list); -+ printk("crypto: RNG (driverid=0x%x) failed, disabling\n", -+ rops->driverid); -+ kfree(rops); -+ } else if (n > 0) -+ bufcnt += n; -+ } -+ /* give up CPU for a bit, just in case as this is a loop */ -+ schedule(); -+ } -+ -+ -+#ifdef CONFIG_OCF_FIPS -+ if (bufcnt > 0 && rndtest_buf((unsigned char *) &buf[0])) { -+ dprintk("crypto: buffer had fips errors, discarding\n"); -+ bufcnt = 0; -+ } -+#endif -+ -+ /* -+ * if we have a certified buffer, we can send some data -+ * to /dev/random and move along -+ */ -+ if (bufcnt > 0) { -+ /* add what we have */ -+ random_input_words(buf, bufcnt, bufcnt*sizeof(int)*8); -+ bufcnt = 0; -+ } -+ -+ /* give up CPU for a bit so we don't hog while filling */ -+ schedule(); -+ -+ /* wait for needing more */ -+ wantcnt = random_input_wait(); -+ -+ if (wantcnt <= 0) -+ wantcnt = 0; /* try to get some info again */ -+ else -+ /* round up to one word or we can loop forever */ -+ wantcnt = (wantcnt + (sizeof(int)*8)) / (sizeof(int)*8); -+ if (wantcnt > NUM_INT) { -+ wantcnt = NUM_INT; -+ } -+ -+ if (signal_pending(current)) { -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ spin_lock_irq(¤t->sigmask_lock); -+#endif -+ flush_signals(current); -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ spin_unlock_irq(¤t->sigmask_lock); -+#endif -+ } -+ } -+ -+ kfree(buf); -+ -+bad_alloc: -+ spin_lock_irq(&random_lock); -+ randomproc = (pid_t) -1; -+ started = 0; -+ spin_unlock_irq(&random_lock); -+ -+ return retval; -+} -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/rndtest.c linux-3.0.4/crypto/ocf/rndtest.c ---- linux-3.0.4.orig/crypto/ocf/rndtest.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/rndtest.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,300 @@ -+/* $OpenBSD$ */ -+ -+/* -+ * OCF/Linux port done by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * The license and original author are listed below. -+ * -+ * Copyright (c) 2002 Jason L. Wright (jason@thought.net) -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. All advertising materials mentioning features or use of this software -+ * must display the following acknowledgement: -+ * This product includes software developed by Jason L. Wright -+ * 4. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "rndtest.h" -+ -+static struct rndtest_stats rndstats; -+ -+static void rndtest_test(struct rndtest_state *); -+ -+/* The tests themselves */ -+static int rndtest_monobit(struct rndtest_state *); -+static int rndtest_runs(struct rndtest_state *); -+static int rndtest_longruns(struct rndtest_state *); -+static int rndtest_chi_4(struct rndtest_state *); -+ -+static int rndtest_runs_check(struct rndtest_state *, int, int *); -+static void rndtest_runs_record(struct rndtest_state *, int, int *); -+ -+static const struct rndtest_testfunc { -+ int (*test)(struct rndtest_state *); -+} rndtest_funcs[] = { -+ { rndtest_monobit }, -+ { rndtest_runs }, -+ { rndtest_chi_4 }, -+ { rndtest_longruns }, -+}; -+ -+#define RNDTEST_NTESTS (sizeof(rndtest_funcs)/sizeof(rndtest_funcs[0])) -+ -+static void -+rndtest_test(struct rndtest_state *rsp) -+{ -+ int i, rv = 0; -+ -+ rndstats.rst_tests++; -+ for (i = 0; i < RNDTEST_NTESTS; i++) -+ rv |= (*rndtest_funcs[i].test)(rsp); -+ rsp->rs_discard = (rv != 0); -+} -+ -+ -+extern int crypto_debug; -+#define rndtest_verbose 2 -+#define rndtest_report(rsp, failure, fmt, a...) \ -+ { if (failure || crypto_debug) { printk("rng_test: " fmt "\n", a); } else; } -+ -+#define RNDTEST_MONOBIT_MINONES 9725 -+#define RNDTEST_MONOBIT_MAXONES 10275 -+ -+static int -+rndtest_monobit(struct rndtest_state *rsp) -+{ -+ int i, ones = 0, j; -+ u_int8_t r; -+ -+ for (i = 0; i < RNDTEST_NBYTES; i++) { -+ r = rsp->rs_buf[i]; -+ for (j = 0; j < 8; j++, r <<= 1) -+ if (r & 0x80) -+ ones++; -+ } -+ if (ones > RNDTEST_MONOBIT_MINONES && -+ ones < RNDTEST_MONOBIT_MAXONES) { -+ if (rndtest_verbose > 1) -+ rndtest_report(rsp, 0, "monobit pass (%d < %d < %d)", -+ RNDTEST_MONOBIT_MINONES, ones, -+ RNDTEST_MONOBIT_MAXONES); -+ return (0); -+ } else { -+ if (rndtest_verbose) -+ rndtest_report(rsp, 1, -+ "monobit failed (%d ones)", ones); -+ rndstats.rst_monobit++; -+ return (-1); -+ } -+} -+ -+#define RNDTEST_RUNS_NINTERVAL 6 -+ -+static const struct rndtest_runs_tabs { -+ u_int16_t min, max; -+} rndtest_runs_tab[] = { -+ { 2343, 2657 }, -+ { 1135, 1365 }, -+ { 542, 708 }, -+ { 251, 373 }, -+ { 111, 201 }, -+ { 111, 201 }, -+}; -+ -+static int -+rndtest_runs(struct rndtest_state *rsp) -+{ -+ int i, j, ones, zeros, rv = 0; -+ int onei[RNDTEST_RUNS_NINTERVAL], zeroi[RNDTEST_RUNS_NINTERVAL]; -+ u_int8_t c; -+ -+ bzero(onei, sizeof(onei)); -+ bzero(zeroi, sizeof(zeroi)); -+ ones = zeros = 0; -+ for (i = 0; i < RNDTEST_NBYTES; i++) { -+ c = rsp->rs_buf[i]; -+ for (j = 0; j < 8; j++, c <<= 1) { -+ if (c & 0x80) { -+ ones++; -+ rndtest_runs_record(rsp, zeros, zeroi); -+ zeros = 0; -+ } else { -+ zeros++; -+ rndtest_runs_record(rsp, ones, onei); -+ ones = 0; -+ } -+ } -+ } -+ rndtest_runs_record(rsp, ones, onei); -+ rndtest_runs_record(rsp, zeros, zeroi); -+ -+ rv |= rndtest_runs_check(rsp, 0, zeroi); -+ rv |= rndtest_runs_check(rsp, 1, onei); -+ -+ if (rv) -+ rndstats.rst_runs++; -+ -+ return (rv); -+} -+ -+static void -+rndtest_runs_record(struct rndtest_state *rsp, int len, int *intrv) -+{ -+ if (len == 0) -+ return; -+ if (len > RNDTEST_RUNS_NINTERVAL) -+ len = RNDTEST_RUNS_NINTERVAL; -+ len -= 1; -+ intrv[len]++; -+} -+ -+static int -+rndtest_runs_check(struct rndtest_state *rsp, int val, int *src) -+{ -+ int i, rv = 0; -+ -+ for (i = 0; i < RNDTEST_RUNS_NINTERVAL; i++) { -+ if (src[i] < rndtest_runs_tab[i].min || -+ src[i] > rndtest_runs_tab[i].max) { -+ rndtest_report(rsp, 1, -+ "%s interval %d failed (%d, %d-%d)", -+ val ? "ones" : "zeros", -+ i + 1, src[i], rndtest_runs_tab[i].min, -+ rndtest_runs_tab[i].max); -+ rv = -1; -+ } else { -+ rndtest_report(rsp, 0, -+ "runs pass %s interval %d (%d < %d < %d)", -+ val ? "ones" : "zeros", -+ i + 1, rndtest_runs_tab[i].min, src[i], -+ rndtest_runs_tab[i].max); -+ } -+ } -+ return (rv); -+} -+ -+static int -+rndtest_longruns(struct rndtest_state *rsp) -+{ -+ int i, j, ones = 0, zeros = 0, maxones = 0, maxzeros = 0; -+ u_int8_t c; -+ -+ for (i = 0; i < RNDTEST_NBYTES; i++) { -+ c = rsp->rs_buf[i]; -+ for (j = 0; j < 8; j++, c <<= 1) { -+ if (c & 0x80) { -+ zeros = 0; -+ ones++; -+ if (ones > maxones) -+ maxones = ones; -+ } else { -+ ones = 0; -+ zeros++; -+ if (zeros > maxzeros) -+ maxzeros = zeros; -+ } -+ } -+ } -+ -+ if (maxones < 26 && maxzeros < 26) { -+ rndtest_report(rsp, 0, "longruns pass (%d ones, %d zeros)", -+ maxones, maxzeros); -+ return (0); -+ } else { -+ rndtest_report(rsp, 1, "longruns fail (%d ones, %d zeros)", -+ maxones, maxzeros); -+ rndstats.rst_longruns++; -+ return (-1); -+ } -+} -+ -+/* -+ * chi^2 test over 4 bits: (this is called the poker test in FIPS 140-2, -+ * but it is really the chi^2 test over 4 bits (the poker test as described -+ * by Knuth vol 2 is something different, and I take him as authoritative -+ * on nomenclature over NIST). -+ */ -+#define RNDTEST_CHI4_K 16 -+#define RNDTEST_CHI4_K_MASK (RNDTEST_CHI4_K - 1) -+ -+/* -+ * The unnormalized values are used so that we don't have to worry about -+ * fractional precision. The "real" value is found by: -+ * (V - 1562500) * (16 / 5000) = Vn (where V is the unnormalized value) -+ */ -+#define RNDTEST_CHI4_VMIN 1563181 /* 2.1792 */ -+#define RNDTEST_CHI4_VMAX 1576929 /* 46.1728 */ -+ -+static int -+rndtest_chi_4(struct rndtest_state *rsp) -+{ -+ unsigned int freq[RNDTEST_CHI4_K], i, sum; -+ -+ for (i = 0; i < RNDTEST_CHI4_K; i++) -+ freq[i] = 0; -+ -+ /* Get number of occurances of each 4 bit pattern */ -+ for (i = 0; i < RNDTEST_NBYTES; i++) { -+ freq[(rsp->rs_buf[i] >> 4) & RNDTEST_CHI4_K_MASK]++; -+ freq[(rsp->rs_buf[i] >> 0) & RNDTEST_CHI4_K_MASK]++; -+ } -+ -+ for (i = 0, sum = 0; i < RNDTEST_CHI4_K; i++) -+ sum += freq[i] * freq[i]; -+ -+ if (sum >= 1563181 && sum <= 1576929) { -+ rndtest_report(rsp, 0, "chi^2(4): pass (sum %u)", sum); -+ return (0); -+ } else { -+ rndtest_report(rsp, 1, "chi^2(4): failed (sum %u)", sum); -+ rndstats.rst_chi++; -+ return (-1); -+ } -+} -+ -+int -+rndtest_buf(unsigned char *buf) -+{ -+ struct rndtest_state rsp; -+ -+ memset(&rsp, 0, sizeof(rsp)); -+ rsp.rs_buf = buf; -+ rndtest_test(&rsp); -+ return(rsp.rs_discard); -+} -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/rndtest.h linux-3.0.4/crypto/ocf/rndtest.h ---- linux-3.0.4.orig/crypto/ocf/rndtest.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/rndtest.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,54 @@ -+/* $FreeBSD: src/sys/dev/rndtest/rndtest.h,v 1.1 2003/03/11 22:54:44 sam Exp $ */ -+/* $OpenBSD$ */ -+ -+/* -+ * Copyright (c) 2002 Jason L. Wright (jason@thought.net) -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. All advertising materials mentioning features or use of this software -+ * must display the following acknowledgement: -+ * This product includes software developed by Jason L. Wright -+ * 4. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/* Some of the tests depend on these values */ -+#define RNDTEST_NBYTES 2500 -+#define RNDTEST_NBITS (8 * RNDTEST_NBYTES) -+ -+struct rndtest_state { -+ int rs_discard; /* discard/accept random data */ -+ u_int8_t *rs_buf; -+}; -+ -+struct rndtest_stats { -+ u_int32_t rst_discard; /* number of bytes discarded */ -+ u_int32_t rst_tests; /* number of test runs */ -+ u_int32_t rst_monobit; /* monobit test failures */ -+ u_int32_t rst_runs; /* 0/1 runs failures */ -+ u_int32_t rst_longruns; /* longruns failures */ -+ u_int32_t rst_chi; /* chi^2 failures */ -+}; -+ -+extern int rndtest_buf(unsigned char *buf); -diff -Nur linux-3.0.4.orig/crypto/ocf/safe/Makefile linux-3.0.4/crypto/ocf/safe/Makefile ---- linux-3.0.4.orig/crypto/ocf/safe/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/safe/Makefile 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,12 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+obj-$(CONFIG_OCF_SAFE) += safe.o -+ -+obj ?= . -+EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/safe/hmachack.h linux-3.0.4/crypto/ocf/safe/hmachack.h ---- linux-3.0.4.orig/crypto/ocf/safe/hmachack.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/safe/hmachack.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,37 @@ -+/* -+ * until we find a cleaner way, include the BSD md5/sha1 code -+ * here -+ */ -+#ifdef HMAC_HACK -+#define LITTLE_ENDIAN 1234 -+#define BIG_ENDIAN 4321 -+#ifdef __LITTLE_ENDIAN -+#define BYTE_ORDER LITTLE_ENDIAN -+#endif -+#ifdef __BIG_ENDIAN -+#define BYTE_ORDER BIG_ENDIAN -+#endif -+ -+u_int8_t hmac_ipad_buffer[64] = { -+ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, -+ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, -+ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, -+ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, -+ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, -+ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, -+ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, -+ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36 -+}; -+ -+u_int8_t hmac_opad_buffer[64] = { -+ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, -+ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, -+ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, -+ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, -+ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, -+ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, -+ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, -+ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C -+}; -+#endif /* HMAC_HACK */ -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/safe/md5.c linux-3.0.4/crypto/ocf/safe/md5.c ---- linux-3.0.4.orig/crypto/ocf/safe/md5.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/safe/md5.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,308 @@ -+/* $KAME: md5.c,v 1.5 2000/11/08 06:13:08 itojun Exp $ */ -+/* -+ * Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. Neither the name of the project nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ */ -+ -+#if 0 -+#include -+__FBSDID("$FreeBSD: src/sys/crypto/md5.c,v 1.9 2004/01/27 19:49:19 des Exp $"); -+ -+#include -+#include -+#include -+#include -+#include -+#endif -+ -+#define SHIFT(X, s) (((X) << (s)) | ((X) >> (32 - (s)))) -+ -+#define F(X, Y, Z) (((X) & (Y)) | ((~X) & (Z))) -+#define G(X, Y, Z) (((X) & (Z)) | ((Y) & (~Z))) -+#define H(X, Y, Z) ((X) ^ (Y) ^ (Z)) -+#define I(X, Y, Z) ((Y) ^ ((X) | (~Z))) -+ -+#define ROUND1(a, b, c, d, k, s, i) { \ -+ (a) = (a) + F((b), (c), (d)) + X[(k)] + T[(i)]; \ -+ (a) = SHIFT((a), (s)); \ -+ (a) = (b) + (a); \ -+} -+ -+#define ROUND2(a, b, c, d, k, s, i) { \ -+ (a) = (a) + G((b), (c), (d)) + X[(k)] + T[(i)]; \ -+ (a) = SHIFT((a), (s)); \ -+ (a) = (b) + (a); \ -+} -+ -+#define ROUND3(a, b, c, d, k, s, i) { \ -+ (a) = (a) + H((b), (c), (d)) + X[(k)] + T[(i)]; \ -+ (a) = SHIFT((a), (s)); \ -+ (a) = (b) + (a); \ -+} -+ -+#define ROUND4(a, b, c, d, k, s, i) { \ -+ (a) = (a) + I((b), (c), (d)) + X[(k)] + T[(i)]; \ -+ (a) = SHIFT((a), (s)); \ -+ (a) = (b) + (a); \ -+} -+ -+#define Sa 7 -+#define Sb 12 -+#define Sc 17 -+#define Sd 22 -+ -+#define Se 5 -+#define Sf 9 -+#define Sg 14 -+#define Sh 20 -+ -+#define Si 4 -+#define Sj 11 -+#define Sk 16 -+#define Sl 23 -+ -+#define Sm 6 -+#define Sn 10 -+#define So 15 -+#define Sp 21 -+ -+#define MD5_A0 0x67452301 -+#define MD5_B0 0xefcdab89 -+#define MD5_C0 0x98badcfe -+#define MD5_D0 0x10325476 -+ -+/* Integer part of 4294967296 times abs(sin(i)), where i is in radians. */ -+static const u_int32_t T[65] = { -+ 0, -+ 0xd76aa478, 0xe8c7b756, 0x242070db, 0xc1bdceee, -+ 0xf57c0faf, 0x4787c62a, 0xa8304613, 0xfd469501, -+ 0x698098d8, 0x8b44f7af, 0xffff5bb1, 0x895cd7be, -+ 0x6b901122, 0xfd987193, 0xa679438e, 0x49b40821, -+ -+ 0xf61e2562, 0xc040b340, 0x265e5a51, 0xe9b6c7aa, -+ 0xd62f105d, 0x2441453, 0xd8a1e681, 0xe7d3fbc8, -+ 0x21e1cde6, 0xc33707d6, 0xf4d50d87, 0x455a14ed, -+ 0xa9e3e905, 0xfcefa3f8, 0x676f02d9, 0x8d2a4c8a, -+ -+ 0xfffa3942, 0x8771f681, 0x6d9d6122, 0xfde5380c, -+ 0xa4beea44, 0x4bdecfa9, 0xf6bb4b60, 0xbebfbc70, -+ 0x289b7ec6, 0xeaa127fa, 0xd4ef3085, 0x4881d05, -+ 0xd9d4d039, 0xe6db99e5, 0x1fa27cf8, 0xc4ac5665, -+ -+ 0xf4292244, 0x432aff97, 0xab9423a7, 0xfc93a039, -+ 0x655b59c3, 0x8f0ccc92, 0xffeff47d, 0x85845dd1, -+ 0x6fa87e4f, 0xfe2ce6e0, 0xa3014314, 0x4e0811a1, -+ 0xf7537e82, 0xbd3af235, 0x2ad7d2bb, 0xeb86d391, -+}; -+ -+static const u_int8_t md5_paddat[MD5_BUFLEN] = { -+ 0x80, 0, 0, 0, 0, 0, 0, 0, -+ 0, 0, 0, 0, 0, 0, 0, 0, -+ 0, 0, 0, 0, 0, 0, 0, 0, -+ 0, 0, 0, 0, 0, 0, 0, 0, -+ 0, 0, 0, 0, 0, 0, 0, 0, -+ 0, 0, 0, 0, 0, 0, 0, 0, -+ 0, 0, 0, 0, 0, 0, 0, 0, -+ 0, 0, 0, 0, 0, 0, 0, 0, -+}; -+ -+static void md5_calc(u_int8_t *, md5_ctxt *); -+ -+void md5_init(ctxt) -+ md5_ctxt *ctxt; -+{ -+ ctxt->md5_n = 0; -+ ctxt->md5_i = 0; -+ ctxt->md5_sta = MD5_A0; -+ ctxt->md5_stb = MD5_B0; -+ ctxt->md5_stc = MD5_C0; -+ ctxt->md5_std = MD5_D0; -+ bzero(ctxt->md5_buf, sizeof(ctxt->md5_buf)); -+} -+ -+void md5_loop(ctxt, input, len) -+ md5_ctxt *ctxt; -+ u_int8_t *input; -+ u_int len; /* number of bytes */ -+{ -+ u_int gap, i; -+ -+ ctxt->md5_n += len * 8; /* byte to bit */ -+ gap = MD5_BUFLEN - ctxt->md5_i; -+ -+ if (len >= gap) { -+ bcopy((void *)input, (void *)(ctxt->md5_buf + ctxt->md5_i), -+ gap); -+ md5_calc(ctxt->md5_buf, ctxt); -+ -+ for (i = gap; i + MD5_BUFLEN <= len; i += MD5_BUFLEN) { -+ md5_calc((u_int8_t *)(input + i), ctxt); -+ } -+ -+ ctxt->md5_i = len - i; -+ bcopy((void *)(input + i), (void *)ctxt->md5_buf, ctxt->md5_i); -+ } else { -+ bcopy((void *)input, (void *)(ctxt->md5_buf + ctxt->md5_i), -+ len); -+ ctxt->md5_i += len; -+ } -+} -+ -+void md5_pad(ctxt) -+ md5_ctxt *ctxt; -+{ -+ u_int gap; -+ -+ /* Don't count up padding. Keep md5_n. */ -+ gap = MD5_BUFLEN - ctxt->md5_i; -+ if (gap > 8) { -+ bcopy(md5_paddat, -+ (void *)(ctxt->md5_buf + ctxt->md5_i), -+ gap - sizeof(ctxt->md5_n)); -+ } else { -+ /* including gap == 8 */ -+ bcopy(md5_paddat, (void *)(ctxt->md5_buf + ctxt->md5_i), -+ gap); -+ md5_calc(ctxt->md5_buf, ctxt); -+ bcopy((md5_paddat + gap), -+ (void *)ctxt->md5_buf, -+ MD5_BUFLEN - sizeof(ctxt->md5_n)); -+ } -+ -+ /* 8 byte word */ -+#if BYTE_ORDER == LITTLE_ENDIAN -+ bcopy(&ctxt->md5_n8[0], &ctxt->md5_buf[56], 8); -+#endif -+#if BYTE_ORDER == BIG_ENDIAN -+ ctxt->md5_buf[56] = ctxt->md5_n8[7]; -+ ctxt->md5_buf[57] = ctxt->md5_n8[6]; -+ ctxt->md5_buf[58] = ctxt->md5_n8[5]; -+ ctxt->md5_buf[59] = ctxt->md5_n8[4]; -+ ctxt->md5_buf[60] = ctxt->md5_n8[3]; -+ ctxt->md5_buf[61] = ctxt->md5_n8[2]; -+ ctxt->md5_buf[62] = ctxt->md5_n8[1]; -+ ctxt->md5_buf[63] = ctxt->md5_n8[0]; -+#endif -+ -+ md5_calc(ctxt->md5_buf, ctxt); -+} -+ -+void md5_result(digest, ctxt) -+ u_int8_t *digest; -+ md5_ctxt *ctxt; -+{ -+ /* 4 byte words */ -+#if BYTE_ORDER == LITTLE_ENDIAN -+ bcopy(&ctxt->md5_st8[0], digest, 16); -+#endif -+#if BYTE_ORDER == BIG_ENDIAN -+ digest[ 0] = ctxt->md5_st8[ 3]; digest[ 1] = ctxt->md5_st8[ 2]; -+ digest[ 2] = ctxt->md5_st8[ 1]; digest[ 3] = ctxt->md5_st8[ 0]; -+ digest[ 4] = ctxt->md5_st8[ 7]; digest[ 5] = ctxt->md5_st8[ 6]; -+ digest[ 6] = ctxt->md5_st8[ 5]; digest[ 7] = ctxt->md5_st8[ 4]; -+ digest[ 8] = ctxt->md5_st8[11]; digest[ 9] = ctxt->md5_st8[10]; -+ digest[10] = ctxt->md5_st8[ 9]; digest[11] = ctxt->md5_st8[ 8]; -+ digest[12] = ctxt->md5_st8[15]; digest[13] = ctxt->md5_st8[14]; -+ digest[14] = ctxt->md5_st8[13]; digest[15] = ctxt->md5_st8[12]; -+#endif -+} -+ -+static void md5_calc(b64, ctxt) -+ u_int8_t *b64; -+ md5_ctxt *ctxt; -+{ -+ u_int32_t A = ctxt->md5_sta; -+ u_int32_t B = ctxt->md5_stb; -+ u_int32_t C = ctxt->md5_stc; -+ u_int32_t D = ctxt->md5_std; -+#if BYTE_ORDER == LITTLE_ENDIAN -+ u_int32_t *X = (u_int32_t *)b64; -+#endif -+#if BYTE_ORDER == BIG_ENDIAN -+ /* 4 byte words */ -+ /* what a brute force but fast! */ -+ u_int32_t X[16]; -+ u_int8_t *y = (u_int8_t *)X; -+ y[ 0] = b64[ 3]; y[ 1] = b64[ 2]; y[ 2] = b64[ 1]; y[ 3] = b64[ 0]; -+ y[ 4] = b64[ 7]; y[ 5] = b64[ 6]; y[ 6] = b64[ 5]; y[ 7] = b64[ 4]; -+ y[ 8] = b64[11]; y[ 9] = b64[10]; y[10] = b64[ 9]; y[11] = b64[ 8]; -+ y[12] = b64[15]; y[13] = b64[14]; y[14] = b64[13]; y[15] = b64[12]; -+ y[16] = b64[19]; y[17] = b64[18]; y[18] = b64[17]; y[19] = b64[16]; -+ y[20] = b64[23]; y[21] = b64[22]; y[22] = b64[21]; y[23] = b64[20]; -+ y[24] = b64[27]; y[25] = b64[26]; y[26] = b64[25]; y[27] = b64[24]; -+ y[28] = b64[31]; y[29] = b64[30]; y[30] = b64[29]; y[31] = b64[28]; -+ y[32] = b64[35]; y[33] = b64[34]; y[34] = b64[33]; y[35] = b64[32]; -+ y[36] = b64[39]; y[37] = b64[38]; y[38] = b64[37]; y[39] = b64[36]; -+ y[40] = b64[43]; y[41] = b64[42]; y[42] = b64[41]; y[43] = b64[40]; -+ y[44] = b64[47]; y[45] = b64[46]; y[46] = b64[45]; y[47] = b64[44]; -+ y[48] = b64[51]; y[49] = b64[50]; y[50] = b64[49]; y[51] = b64[48]; -+ y[52] = b64[55]; y[53] = b64[54]; y[54] = b64[53]; y[55] = b64[52]; -+ y[56] = b64[59]; y[57] = b64[58]; y[58] = b64[57]; y[59] = b64[56]; -+ y[60] = b64[63]; y[61] = b64[62]; y[62] = b64[61]; y[63] = b64[60]; -+#endif -+ -+ ROUND1(A, B, C, D, 0, Sa, 1); ROUND1(D, A, B, C, 1, Sb, 2); -+ ROUND1(C, D, A, B, 2, Sc, 3); ROUND1(B, C, D, A, 3, Sd, 4); -+ ROUND1(A, B, C, D, 4, Sa, 5); ROUND1(D, A, B, C, 5, Sb, 6); -+ ROUND1(C, D, A, B, 6, Sc, 7); ROUND1(B, C, D, A, 7, Sd, 8); -+ ROUND1(A, B, C, D, 8, Sa, 9); ROUND1(D, A, B, C, 9, Sb, 10); -+ ROUND1(C, D, A, B, 10, Sc, 11); ROUND1(B, C, D, A, 11, Sd, 12); -+ ROUND1(A, B, C, D, 12, Sa, 13); ROUND1(D, A, B, C, 13, Sb, 14); -+ ROUND1(C, D, A, B, 14, Sc, 15); ROUND1(B, C, D, A, 15, Sd, 16); -+ -+ ROUND2(A, B, C, D, 1, Se, 17); ROUND2(D, A, B, C, 6, Sf, 18); -+ ROUND2(C, D, A, B, 11, Sg, 19); ROUND2(B, C, D, A, 0, Sh, 20); -+ ROUND2(A, B, C, D, 5, Se, 21); ROUND2(D, A, B, C, 10, Sf, 22); -+ ROUND2(C, D, A, B, 15, Sg, 23); ROUND2(B, C, D, A, 4, Sh, 24); -+ ROUND2(A, B, C, D, 9, Se, 25); ROUND2(D, A, B, C, 14, Sf, 26); -+ ROUND2(C, D, A, B, 3, Sg, 27); ROUND2(B, C, D, A, 8, Sh, 28); -+ ROUND2(A, B, C, D, 13, Se, 29); ROUND2(D, A, B, C, 2, Sf, 30); -+ ROUND2(C, D, A, B, 7, Sg, 31); ROUND2(B, C, D, A, 12, Sh, 32); -+ -+ ROUND3(A, B, C, D, 5, Si, 33); ROUND3(D, A, B, C, 8, Sj, 34); -+ ROUND3(C, D, A, B, 11, Sk, 35); ROUND3(B, C, D, A, 14, Sl, 36); -+ ROUND3(A, B, C, D, 1, Si, 37); ROUND3(D, A, B, C, 4, Sj, 38); -+ ROUND3(C, D, A, B, 7, Sk, 39); ROUND3(B, C, D, A, 10, Sl, 40); -+ ROUND3(A, B, C, D, 13, Si, 41); ROUND3(D, A, B, C, 0, Sj, 42); -+ ROUND3(C, D, A, B, 3, Sk, 43); ROUND3(B, C, D, A, 6, Sl, 44); -+ ROUND3(A, B, C, D, 9, Si, 45); ROUND3(D, A, B, C, 12, Sj, 46); -+ ROUND3(C, D, A, B, 15, Sk, 47); ROUND3(B, C, D, A, 2, Sl, 48); -+ -+ ROUND4(A, B, C, D, 0, Sm, 49); ROUND4(D, A, B, C, 7, Sn, 50); -+ ROUND4(C, D, A, B, 14, So, 51); ROUND4(B, C, D, A, 5, Sp, 52); -+ ROUND4(A, B, C, D, 12, Sm, 53); ROUND4(D, A, B, C, 3, Sn, 54); -+ ROUND4(C, D, A, B, 10, So, 55); ROUND4(B, C, D, A, 1, Sp, 56); -+ ROUND4(A, B, C, D, 8, Sm, 57); ROUND4(D, A, B, C, 15, Sn, 58); -+ ROUND4(C, D, A, B, 6, So, 59); ROUND4(B, C, D, A, 13, Sp, 60); -+ ROUND4(A, B, C, D, 4, Sm, 61); ROUND4(D, A, B, C, 11, Sn, 62); -+ ROUND4(C, D, A, B, 2, So, 63); ROUND4(B, C, D, A, 9, Sp, 64); -+ -+ ctxt->md5_sta += A; -+ ctxt->md5_stb += B; -+ ctxt->md5_stc += C; -+ ctxt->md5_std += D; -+} -diff -Nur linux-3.0.4.orig/crypto/ocf/safe/md5.h linux-3.0.4/crypto/ocf/safe/md5.h ---- linux-3.0.4.orig/crypto/ocf/safe/md5.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/safe/md5.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,76 @@ -+/* $FreeBSD: src/sys/crypto/md5.h,v 1.4 2002/03/20 05:13:50 alfred Exp $ */ -+/* $KAME: md5.h,v 1.4 2000/03/27 04:36:22 sumikawa Exp $ */ -+ -+/* -+ * Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. Neither the name of the project nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ */ -+ -+#ifndef _NETINET6_MD5_H_ -+#define _NETINET6_MD5_H_ -+ -+#define MD5_BUFLEN 64 -+ -+typedef struct { -+ union { -+ u_int32_t md5_state32[4]; -+ u_int8_t md5_state8[16]; -+ } md5_st; -+ -+#define md5_sta md5_st.md5_state32[0] -+#define md5_stb md5_st.md5_state32[1] -+#define md5_stc md5_st.md5_state32[2] -+#define md5_std md5_st.md5_state32[3] -+#define md5_st8 md5_st.md5_state8 -+ -+ union { -+ u_int64_t md5_count64; -+ u_int8_t md5_count8[8]; -+ } md5_count; -+#define md5_n md5_count.md5_count64 -+#define md5_n8 md5_count.md5_count8 -+ -+ u_int md5_i; -+ u_int8_t md5_buf[MD5_BUFLEN]; -+} md5_ctxt; -+ -+extern void md5_init(md5_ctxt *); -+extern void md5_loop(md5_ctxt *, u_int8_t *, u_int); -+extern void md5_pad(md5_ctxt *); -+extern void md5_result(u_int8_t *, md5_ctxt *); -+ -+/* compatibility */ -+#define MD5_CTX md5_ctxt -+#define MD5Init(x) md5_init((x)) -+#define MD5Update(x, y, z) md5_loop((x), (y), (z)) -+#define MD5Final(x, y) \ -+do { \ -+ md5_pad((y)); \ -+ md5_result((x), (y)); \ -+} while (0) -+ -+#endif /* ! _NETINET6_MD5_H_*/ -diff -Nur linux-3.0.4.orig/crypto/ocf/safe/safe.c linux-3.0.4/crypto/ocf/safe/safe.c ---- linux-3.0.4.orig/crypto/ocf/safe/safe.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/safe/safe.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,2230 @@ -+/*- -+ * Linux port done by David McCullough -+ * Copyright (C) 2004-2010 David McCullough -+ * The license and original author are listed below. -+ * -+ * Copyright (c) 2003 Sam Leffler, Errno Consulting -+ * Copyright (c) 2003 Global Technology Associates, Inc. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ * -+__FBSDID("$FreeBSD: src/sys/dev/safe/safe.c,v 1.18 2007/03/21 03:42:50 sam Exp $"); -+ */ -+ -+#include -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* -+ * SafeNet SafeXcel-1141 hardware crypto accelerator -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#if 1 -+#define DPRINTF(a) do { \ -+ if (debug) { \ -+ printk("%s: ", sc ? \ -+ device_get_nameunit(sc->sc_dev) : "safe"); \ -+ printk a; \ -+ } \ -+ } while (0) -+#else -+#define DPRINTF(a) -+#endif -+ -+/* -+ * until we find a cleaner way, include the BSD md5/sha1 code -+ * here -+ */ -+#define HMAC_HACK 1 -+#ifdef HMAC_HACK -+#include -+#include -+#include -+#include -+#include -+#endif /* HMAC_HACK */ -+ -+/* add proc entry for this */ -+struct safe_stats safestats; -+ -+#define debug safe_debug -+int safe_debug = 0; -+module_param(safe_debug, int, 0644); -+MODULE_PARM_DESC(safe_debug, "Enable debug"); -+ -+static void safe_callback(struct safe_softc *, struct safe_ringentry *); -+static void safe_feed(struct safe_softc *, struct safe_ringentry *); -+#if defined(CONFIG_OCF_RANDOMHARVEST) && !defined(SAFE_NO_RNG) -+static void safe_rng_init(struct safe_softc *); -+int safe_rngbufsize = 8; /* 32 bytes each read */ -+module_param(safe_rngbufsize, int, 0644); -+MODULE_PARM_DESC(safe_rngbufsize, "RNG polling buffer size (32-bit words)"); -+int safe_rngmaxalarm = 8; /* max alarms before reset */ -+module_param(safe_rngmaxalarm, int, 0644); -+MODULE_PARM_DESC(safe_rngmaxalarm, "RNG max alarms before reset"); -+#endif /* SAFE_NO_RNG */ -+ -+static void safe_totalreset(struct safe_softc *sc); -+static int safe_dmamap_aligned(struct safe_softc *sc, const struct safe_operand *op); -+static int safe_dmamap_uniform(struct safe_softc *sc, const struct safe_operand *op); -+static int safe_free_entry(struct safe_softc *sc, struct safe_ringentry *re); -+static int safe_kprocess(device_t dev, struct cryptkop *krp, int hint); -+static int safe_kstart(struct safe_softc *sc); -+static int safe_ksigbits(struct safe_softc *sc, struct crparam *cr); -+static void safe_kfeed(struct safe_softc *sc); -+static void safe_kpoll(unsigned long arg); -+static void safe_kload_reg(struct safe_softc *sc, u_int32_t off, -+ u_int32_t len, struct crparam *n); -+ -+static int safe_newsession(device_t, u_int32_t *, struct cryptoini *); -+static int safe_freesession(device_t, u_int64_t); -+static int safe_process(device_t, struct cryptop *, int); -+ -+static device_method_t safe_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, safe_newsession), -+ DEVMETHOD(cryptodev_freesession,safe_freesession), -+ DEVMETHOD(cryptodev_process, safe_process), -+ DEVMETHOD(cryptodev_kprocess, safe_kprocess), -+}; -+ -+#define READ_REG(sc,r) readl((sc)->sc_base_addr + (r)) -+#define WRITE_REG(sc,r,val) writel((val), (sc)->sc_base_addr + (r)) -+ -+#define SAFE_MAX_CHIPS 8 -+static struct safe_softc *safe_chip_idx[SAFE_MAX_CHIPS]; -+ -+/* -+ * split our buffers up into safe DMAable byte fragments to avoid lockup -+ * bug in 1141 HW on rev 1.0. -+ */ -+ -+static int -+pci_map_linear( -+ struct safe_softc *sc, -+ struct safe_operand *buf, -+ void *addr, -+ int len) -+{ -+ dma_addr_t tmp; -+ int chunk, tlen = len; -+ -+ tmp = pci_map_single(sc->sc_pcidev, addr, len, PCI_DMA_BIDIRECTIONAL); -+ -+ buf->mapsize += len; -+ while (len > 0) { -+ chunk = (len > sc->sc_max_dsize) ? sc->sc_max_dsize : len; -+ buf->segs[buf->nsegs].ds_addr = tmp; -+ buf->segs[buf->nsegs].ds_len = chunk; -+ buf->segs[buf->nsegs].ds_tlen = tlen; -+ buf->nsegs++; -+ tmp += chunk; -+ len -= chunk; -+ tlen = 0; -+ } -+ return 0; -+} -+ -+/* -+ * map in a given uio buffer (great on some arches :-) -+ */ -+ -+static int -+pci_map_uio(struct safe_softc *sc, struct safe_operand *buf, struct uio *uio) -+{ -+ struct iovec *iov = uio->uio_iov; -+ int n; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ buf->mapsize = 0; -+ buf->nsegs = 0; -+ -+ for (n = 0; n < uio->uio_iovcnt; n++) { -+ pci_map_linear(sc, buf, iov->iov_base, iov->iov_len); -+ iov++; -+ } -+ -+ /* identify this buffer by the first segment */ -+ buf->map = (void *) buf->segs[0].ds_addr; -+ return(0); -+} -+ -+/* -+ * map in a given sk_buff -+ */ -+ -+static int -+pci_map_skb(struct safe_softc *sc,struct safe_operand *buf,struct sk_buff *skb) -+{ -+ int i; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ buf->mapsize = 0; -+ buf->nsegs = 0; -+ -+ pci_map_linear(sc, buf, skb->data, skb_headlen(skb)); -+ -+ for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { -+ pci_map_linear(sc, buf, -+ page_address(skb_shinfo(skb)->frags[i].page) + -+ skb_shinfo(skb)->frags[i].page_offset, -+ skb_shinfo(skb)->frags[i].size); -+ } -+ -+ /* identify this buffer by the first segment */ -+ buf->map = (void *) buf->segs[0].ds_addr; -+ return(0); -+} -+ -+ -+#if 0 /* not needed at this time */ -+static void -+pci_sync_operand(struct safe_softc *sc, struct safe_operand *buf) -+{ -+ int i; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ for (i = 0; i < buf->nsegs; i++) -+ pci_dma_sync_single_for_cpu(sc->sc_pcidev, buf->segs[i].ds_addr, -+ buf->segs[i].ds_len, PCI_DMA_BIDIRECTIONAL); -+} -+#endif -+ -+static void -+pci_unmap_operand(struct safe_softc *sc, struct safe_operand *buf) -+{ -+ int i; -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ for (i = 0; i < buf->nsegs; i++) { -+ if (buf->segs[i].ds_tlen) { -+ DPRINTF(("%s - unmap %d 0x%x %d\n", __FUNCTION__, i, buf->segs[i].ds_addr, buf->segs[i].ds_tlen)); -+ pci_unmap_single(sc->sc_pcidev, buf->segs[i].ds_addr, -+ buf->segs[i].ds_tlen, PCI_DMA_BIDIRECTIONAL); -+ DPRINTF(("%s - unmap %d 0x%x %d done\n", __FUNCTION__, i, buf->segs[i].ds_addr, buf->segs[i].ds_tlen)); -+ } -+ buf->segs[i].ds_addr = 0; -+ buf->segs[i].ds_len = 0; -+ buf->segs[i].ds_tlen = 0; -+ } -+ buf->nsegs = 0; -+ buf->mapsize = 0; -+ buf->map = 0; -+} -+ -+ -+/* -+ * SafeXcel Interrupt routine -+ */ -+static irqreturn_t -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) -+safe_intr(int irq, void *arg) -+#else -+safe_intr(int irq, void *arg, struct pt_regs *regs) -+#endif -+{ -+ struct safe_softc *sc = arg; -+ int stat; -+ unsigned long flags; -+ -+ stat = READ_REG(sc, SAFE_HM_STAT); -+ -+ DPRINTF(("%s(stat=0x%x)\n", __FUNCTION__, stat)); -+ -+ if (stat == 0) /* shared irq, not for us */ -+ return IRQ_NONE; -+ -+ WRITE_REG(sc, SAFE_HI_CLR, stat); /* IACK */ -+ -+ if ((stat & SAFE_INT_PE_DDONE)) { -+ /* -+ * Descriptor(s) done; scan the ring and -+ * process completed operations. -+ */ -+ spin_lock_irqsave(&sc->sc_ringmtx, flags); -+ while (sc->sc_back != sc->sc_front) { -+ struct safe_ringentry *re = sc->sc_back; -+ -+#ifdef SAFE_DEBUG -+ if (debug) { -+ safe_dump_ringstate(sc, __func__); -+ safe_dump_request(sc, __func__, re); -+ } -+#endif -+ /* -+ * safe_process marks ring entries that were allocated -+ * but not used with a csr of zero. This insures the -+ * ring front pointer never needs to be set backwards -+ * in the event that an entry is allocated but not used -+ * because of a setup error. -+ */ -+ DPRINTF(("%s re->re_desc.d_csr=0x%x\n", __FUNCTION__, re->re_desc.d_csr)); -+ if (re->re_desc.d_csr != 0) { -+ if (!SAFE_PE_CSR_IS_DONE(re->re_desc.d_csr)) { -+ DPRINTF(("%s !CSR_IS_DONE\n", __FUNCTION__)); -+ break; -+ } -+ if (!SAFE_PE_LEN_IS_DONE(re->re_desc.d_len)) { -+ DPRINTF(("%s !LEN_IS_DONE\n", __FUNCTION__)); -+ break; -+ } -+ sc->sc_nqchip--; -+ safe_callback(sc, re); -+ } -+ if (++(sc->sc_back) == sc->sc_ringtop) -+ sc->sc_back = sc->sc_ring; -+ } -+ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); -+ } -+ -+ /* -+ * Check to see if we got any DMA Error -+ */ -+ if (stat & SAFE_INT_PE_ERROR) { -+ printk("%s: dmaerr dmastat %08x\n", device_get_nameunit(sc->sc_dev), -+ (int)READ_REG(sc, SAFE_PE_DMASTAT)); -+ safestats.st_dmaerr++; -+ safe_totalreset(sc); -+#if 0 -+ safe_feed(sc); -+#endif -+ } -+ -+ if (sc->sc_needwakeup) { /* XXX check high watermark */ -+ int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); -+ DPRINTF(("%s: wakeup crypto %x\n", __func__, -+ sc->sc_needwakeup)); -+ sc->sc_needwakeup &= ~wakeup; -+ crypto_unblock(sc->sc_cid, wakeup); -+ } -+ -+ return IRQ_HANDLED; -+} -+ -+/* -+ * safe_feed() - post a request to chip -+ */ -+static void -+safe_feed(struct safe_softc *sc, struct safe_ringentry *re) -+{ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+#ifdef SAFE_DEBUG -+ if (debug) { -+ safe_dump_ringstate(sc, __func__); -+ safe_dump_request(sc, __func__, re); -+ } -+#endif -+ sc->sc_nqchip++; -+ if (sc->sc_nqchip > safestats.st_maxqchip) -+ safestats.st_maxqchip = sc->sc_nqchip; -+ /* poke h/w to check descriptor ring, any value can be written */ -+ WRITE_REG(sc, SAFE_HI_RD_DESCR, 0); -+} -+ -+#define N(a) (sizeof(a) / sizeof (a[0])) -+static void -+safe_setup_enckey(struct safe_session *ses, caddr_t key) -+{ -+ int i; -+ -+ bcopy(key, ses->ses_key, ses->ses_klen / 8); -+ -+ /* PE is little-endian, insure proper byte order */ -+ for (i = 0; i < N(ses->ses_key); i++) -+ ses->ses_key[i] = htole32(ses->ses_key[i]); -+} -+ -+static void -+safe_setup_mackey(struct safe_session *ses, int algo, caddr_t key, int klen) -+{ -+#ifdef HMAC_HACK -+ MD5_CTX md5ctx; -+ SHA1_CTX sha1ctx; -+ int i; -+ -+ -+ for (i = 0; i < klen; i++) -+ key[i] ^= HMAC_IPAD_VAL; -+ -+ if (algo == CRYPTO_MD5_HMAC) { -+ MD5Init(&md5ctx); -+ MD5Update(&md5ctx, key, klen); -+ MD5Update(&md5ctx, hmac_ipad_buffer, MD5_HMAC_BLOCK_LEN - klen); -+ bcopy(md5ctx.md5_st8, ses->ses_hminner, sizeof(md5ctx.md5_st8)); -+ } else { -+ SHA1Init(&sha1ctx); -+ SHA1Update(&sha1ctx, key, klen); -+ SHA1Update(&sha1ctx, hmac_ipad_buffer, -+ SHA1_HMAC_BLOCK_LEN - klen); -+ bcopy(sha1ctx.h.b32, ses->ses_hminner, sizeof(sha1ctx.h.b32)); -+ } -+ -+ for (i = 0; i < klen; i++) -+ key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); -+ -+ if (algo == CRYPTO_MD5_HMAC) { -+ MD5Init(&md5ctx); -+ MD5Update(&md5ctx, key, klen); -+ MD5Update(&md5ctx, hmac_opad_buffer, MD5_HMAC_BLOCK_LEN - klen); -+ bcopy(md5ctx.md5_st8, ses->ses_hmouter, sizeof(md5ctx.md5_st8)); -+ } else { -+ SHA1Init(&sha1ctx); -+ SHA1Update(&sha1ctx, key, klen); -+ SHA1Update(&sha1ctx, hmac_opad_buffer, -+ SHA1_HMAC_BLOCK_LEN - klen); -+ bcopy(sha1ctx.h.b32, ses->ses_hmouter, sizeof(sha1ctx.h.b32)); -+ } -+ -+ for (i = 0; i < klen; i++) -+ key[i] ^= HMAC_OPAD_VAL; -+ -+#if 0 -+ /* -+ * this code prevents SHA working on a BE host, -+ * so it is obviously wrong. I think the byte -+ * swap setup we do with the chip fixes this for us -+ */ -+ -+ /* PE is little-endian, insure proper byte order */ -+ for (i = 0; i < N(ses->ses_hminner); i++) { -+ ses->ses_hminner[i] = htole32(ses->ses_hminner[i]); -+ ses->ses_hmouter[i] = htole32(ses->ses_hmouter[i]); -+ } -+#endif -+#else /* HMAC_HACK */ -+ printk("safe: md5/sha not implemented\n"); -+#endif /* HMAC_HACK */ -+} -+#undef N -+ -+/* -+ * Allocate a new 'session' and return an encoded session id. 'sidp' -+ * contains our registration id, and should contain an encoded session -+ * id on successful allocation. -+ */ -+static int -+safe_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) -+{ -+ struct safe_softc *sc = device_get_softc(dev); -+ struct cryptoini *c, *encini = NULL, *macini = NULL; -+ struct safe_session *ses = NULL; -+ int sesn; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (sidp == NULL || cri == NULL || sc == NULL) -+ return (EINVAL); -+ -+ for (c = cri; c != NULL; c = c->cri_next) { -+ if (c->cri_alg == CRYPTO_MD5_HMAC || -+ c->cri_alg == CRYPTO_SHA1_HMAC || -+ c->cri_alg == CRYPTO_NULL_HMAC) { -+ if (macini) -+ return (EINVAL); -+ macini = c; -+ } else if (c->cri_alg == CRYPTO_DES_CBC || -+ c->cri_alg == CRYPTO_3DES_CBC || -+ c->cri_alg == CRYPTO_AES_CBC || -+ c->cri_alg == CRYPTO_NULL_CBC) { -+ if (encini) -+ return (EINVAL); -+ encini = c; -+ } else -+ return (EINVAL); -+ } -+ if (encini == NULL && macini == NULL) -+ return (EINVAL); -+ if (encini) { /* validate key length */ -+ switch (encini->cri_alg) { -+ case CRYPTO_DES_CBC: -+ if (encini->cri_klen != 64) -+ return (EINVAL); -+ break; -+ case CRYPTO_3DES_CBC: -+ if (encini->cri_klen != 192) -+ return (EINVAL); -+ break; -+ case CRYPTO_AES_CBC: -+ if (encini->cri_klen != 128 && -+ encini->cri_klen != 192 && -+ encini->cri_klen != 256) -+ return (EINVAL); -+ break; -+ } -+ } -+ -+ if (sc->sc_sessions == NULL) { -+ ses = sc->sc_sessions = (struct safe_session *) -+ kmalloc(sizeof(struct safe_session), SLAB_ATOMIC); -+ if (ses == NULL) -+ return (ENOMEM); -+ memset(ses, 0, sizeof(struct safe_session)); -+ sesn = 0; -+ sc->sc_nsessions = 1; -+ } else { -+ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { -+ if (sc->sc_sessions[sesn].ses_used == 0) { -+ ses = &sc->sc_sessions[sesn]; -+ break; -+ } -+ } -+ -+ if (ses == NULL) { -+ sesn = sc->sc_nsessions; -+ ses = (struct safe_session *) -+ kmalloc((sesn + 1) * sizeof(struct safe_session), SLAB_ATOMIC); -+ if (ses == NULL) -+ return (ENOMEM); -+ memset(ses, 0, (sesn + 1) * sizeof(struct safe_session)); -+ bcopy(sc->sc_sessions, ses, sesn * -+ sizeof(struct safe_session)); -+ bzero(sc->sc_sessions, sesn * -+ sizeof(struct safe_session)); -+ kfree(sc->sc_sessions); -+ sc->sc_sessions = ses; -+ ses = &sc->sc_sessions[sesn]; -+ sc->sc_nsessions++; -+ } -+ } -+ -+ bzero(ses, sizeof(struct safe_session)); -+ ses->ses_used = 1; -+ -+ if (encini) { -+ ses->ses_klen = encini->cri_klen; -+ if (encini->cri_key != NULL) -+ safe_setup_enckey(ses, encini->cri_key); -+ } -+ -+ if (macini) { -+ ses->ses_mlen = macini->cri_mlen; -+ if (ses->ses_mlen == 0) { -+ if (macini->cri_alg == CRYPTO_MD5_HMAC) -+ ses->ses_mlen = MD5_HASH_LEN; -+ else -+ ses->ses_mlen = SHA1_HASH_LEN; -+ } -+ -+ if (macini->cri_key != NULL) { -+ safe_setup_mackey(ses, macini->cri_alg, macini->cri_key, -+ macini->cri_klen / 8); -+ } -+ } -+ -+ *sidp = SAFE_SID(device_get_unit(sc->sc_dev), sesn); -+ return (0); -+} -+ -+/* -+ * Deallocate a session. -+ */ -+static int -+safe_freesession(device_t dev, u_int64_t tid) -+{ -+ struct safe_softc *sc = device_get_softc(dev); -+ int session, ret; -+ u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (sc == NULL) -+ return (EINVAL); -+ -+ session = SAFE_SESSION(sid); -+ if (session < sc->sc_nsessions) { -+ bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session])); -+ ret = 0; -+ } else -+ ret = EINVAL; -+ return (ret); -+} -+ -+ -+static int -+safe_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ struct safe_softc *sc = device_get_softc(dev); -+ int err = 0, i, nicealign, uniform; -+ struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; -+ int bypass, oplen, ivsize; -+ caddr_t iv; -+ int16_t coffset; -+ struct safe_session *ses; -+ struct safe_ringentry *re; -+ struct safe_sarec *sa; -+ struct safe_pdesc *pd; -+ u_int32_t cmd0, cmd1, staterec, rand_iv[4]; -+ unsigned long flags; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { -+ safestats.st_invalid++; -+ return (EINVAL); -+ } -+ if (SAFE_SESSION(crp->crp_sid) >= sc->sc_nsessions) { -+ safestats.st_badsession++; -+ return (EINVAL); -+ } -+ -+ spin_lock_irqsave(&sc->sc_ringmtx, flags); -+ if (sc->sc_front == sc->sc_back && sc->sc_nqchip != 0) { -+ safestats.st_ringfull++; -+ sc->sc_needwakeup |= CRYPTO_SYMQ; -+ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); -+ return (ERESTART); -+ } -+ re = sc->sc_front; -+ -+ staterec = re->re_sa.sa_staterec; /* save */ -+ /* NB: zero everything but the PE descriptor */ -+ bzero(&re->re_sa, sizeof(struct safe_ringentry) - sizeof(re->re_desc)); -+ re->re_sa.sa_staterec = staterec; /* restore */ -+ -+ re->re_crp = crp; -+ re->re_sesn = SAFE_SESSION(crp->crp_sid); -+ -+ re->re_src.nsegs = 0; -+ re->re_dst.nsegs = 0; -+ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ re->re_src_skb = (struct sk_buff *)crp->crp_buf; -+ re->re_dst_skb = (struct sk_buff *)crp->crp_buf; -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ re->re_src_io = (struct uio *)crp->crp_buf; -+ re->re_dst_io = (struct uio *)crp->crp_buf; -+ } else { -+ safestats.st_badflags++; -+ err = EINVAL; -+ goto errout; /* XXX we don't handle contiguous blocks! */ -+ } -+ -+ sa = &re->re_sa; -+ ses = &sc->sc_sessions[re->re_sesn]; -+ -+ crd1 = crp->crp_desc; -+ if (crd1 == NULL) { -+ safestats.st_nodesc++; -+ err = EINVAL; -+ goto errout; -+ } -+ crd2 = crd1->crd_next; -+ -+ cmd0 = SAFE_SA_CMD0_BASIC; /* basic group operation */ -+ cmd1 = 0; -+ if (crd2 == NULL) { -+ if (crd1->crd_alg == CRYPTO_MD5_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1_HMAC || -+ crd1->crd_alg == CRYPTO_NULL_HMAC) { -+ maccrd = crd1; -+ enccrd = NULL; -+ cmd0 |= SAFE_SA_CMD0_OP_HASH; -+ } else if (crd1->crd_alg == CRYPTO_DES_CBC || -+ crd1->crd_alg == CRYPTO_3DES_CBC || -+ crd1->crd_alg == CRYPTO_AES_CBC || -+ crd1->crd_alg == CRYPTO_NULL_CBC) { -+ maccrd = NULL; -+ enccrd = crd1; -+ cmd0 |= SAFE_SA_CMD0_OP_CRYPT; -+ } else { -+ safestats.st_badalg++; -+ err = EINVAL; -+ goto errout; -+ } -+ } else { -+ if ((crd1->crd_alg == CRYPTO_MD5_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1_HMAC || -+ crd1->crd_alg == CRYPTO_NULL_HMAC) && -+ (crd2->crd_alg == CRYPTO_DES_CBC || -+ crd2->crd_alg == CRYPTO_3DES_CBC || -+ crd2->crd_alg == CRYPTO_AES_CBC || -+ crd2->crd_alg == CRYPTO_NULL_CBC) && -+ ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { -+ maccrd = crd1; -+ enccrd = crd2; -+ } else if ((crd1->crd_alg == CRYPTO_DES_CBC || -+ crd1->crd_alg == CRYPTO_3DES_CBC || -+ crd1->crd_alg == CRYPTO_AES_CBC || -+ crd1->crd_alg == CRYPTO_NULL_CBC) && -+ (crd2->crd_alg == CRYPTO_MD5_HMAC || -+ crd2->crd_alg == CRYPTO_SHA1_HMAC || -+ crd2->crd_alg == CRYPTO_NULL_HMAC) && -+ (crd1->crd_flags & CRD_F_ENCRYPT)) { -+ enccrd = crd1; -+ maccrd = crd2; -+ } else { -+ safestats.st_badalg++; -+ err = EINVAL; -+ goto errout; -+ } -+ cmd0 |= SAFE_SA_CMD0_OP_BOTH; -+ } -+ -+ if (enccrd) { -+ if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) -+ safe_setup_enckey(ses, enccrd->crd_key); -+ -+ if (enccrd->crd_alg == CRYPTO_DES_CBC) { -+ cmd0 |= SAFE_SA_CMD0_DES; -+ cmd1 |= SAFE_SA_CMD1_CBC; -+ ivsize = 2*sizeof(u_int32_t); -+ } else if (enccrd->crd_alg == CRYPTO_3DES_CBC) { -+ cmd0 |= SAFE_SA_CMD0_3DES; -+ cmd1 |= SAFE_SA_CMD1_CBC; -+ ivsize = 2*sizeof(u_int32_t); -+ } else if (enccrd->crd_alg == CRYPTO_AES_CBC) { -+ cmd0 |= SAFE_SA_CMD0_AES; -+ cmd1 |= SAFE_SA_CMD1_CBC; -+ if (ses->ses_klen == 128) -+ cmd1 |= SAFE_SA_CMD1_AES128; -+ else if (ses->ses_klen == 192) -+ cmd1 |= SAFE_SA_CMD1_AES192; -+ else -+ cmd1 |= SAFE_SA_CMD1_AES256; -+ ivsize = 4*sizeof(u_int32_t); -+ } else { -+ cmd0 |= SAFE_SA_CMD0_CRYPT_NULL; -+ ivsize = 0; -+ } -+ -+ /* -+ * Setup encrypt/decrypt state. When using basic ops -+ * we can't use an inline IV because hash/crypt offset -+ * must be from the end of the IV to the start of the -+ * crypt data and this leaves out the preceding header -+ * from the hash calculation. Instead we place the IV -+ * in the state record and set the hash/crypt offset to -+ * copy both the header+IV. -+ */ -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) { -+ cmd0 |= SAFE_SA_CMD0_OUTBOUND; -+ -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) -+ iv = enccrd->crd_iv; -+ else -+ read_random((iv = (caddr_t) &rand_iv[0]), sizeof(rand_iv)); -+ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ enccrd->crd_inject, ivsize, iv); -+ } -+ bcopy(iv, re->re_sastate.sa_saved_iv, ivsize); -+ /* make iv LE */ -+ for (i = 0; i < ivsize/sizeof(re->re_sastate.sa_saved_iv[0]); i++) -+ re->re_sastate.sa_saved_iv[i] = -+ cpu_to_le32(re->re_sastate.sa_saved_iv[i]); -+ cmd0 |= SAFE_SA_CMD0_IVLD_STATE | SAFE_SA_CMD0_SAVEIV; -+ re->re_flags |= SAFE_QFLAGS_COPYOUTIV; -+ } else { -+ cmd0 |= SAFE_SA_CMD0_INBOUND; -+ -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) { -+ bcopy(enccrd->crd_iv, -+ re->re_sastate.sa_saved_iv, ivsize); -+ } else { -+ crypto_copydata(crp->crp_flags, crp->crp_buf, -+ enccrd->crd_inject, ivsize, -+ (caddr_t)re->re_sastate.sa_saved_iv); -+ } -+ /* make iv LE */ -+ for (i = 0; i < ivsize/sizeof(re->re_sastate.sa_saved_iv[0]); i++) -+ re->re_sastate.sa_saved_iv[i] = -+ cpu_to_le32(re->re_sastate.sa_saved_iv[i]); -+ cmd0 |= SAFE_SA_CMD0_IVLD_STATE; -+ } -+ /* -+ * For basic encryption use the zero pad algorithm. -+ * This pads results to an 8-byte boundary and -+ * suppresses padding verification for inbound (i.e. -+ * decrypt) operations. -+ * -+ * NB: Not sure if the 8-byte pad boundary is a problem. -+ */ -+ cmd0 |= SAFE_SA_CMD0_PAD_ZERO; -+ -+ /* XXX assert key bufs have the same size */ -+ bcopy(ses->ses_key, sa->sa_key, sizeof(sa->sa_key)); -+ } -+ -+ if (maccrd) { -+ if (maccrd->crd_flags & CRD_F_KEY_EXPLICIT) { -+ safe_setup_mackey(ses, maccrd->crd_alg, -+ maccrd->crd_key, maccrd->crd_klen / 8); -+ } -+ -+ if (maccrd->crd_alg == CRYPTO_MD5_HMAC) { -+ cmd0 |= SAFE_SA_CMD0_MD5; -+ cmd1 |= SAFE_SA_CMD1_HMAC; /* NB: enable HMAC */ -+ } else if (maccrd->crd_alg == CRYPTO_SHA1_HMAC) { -+ cmd0 |= SAFE_SA_CMD0_SHA1; -+ cmd1 |= SAFE_SA_CMD1_HMAC; /* NB: enable HMAC */ -+ } else { -+ cmd0 |= SAFE_SA_CMD0_HASH_NULL; -+ } -+ /* -+ * Digest data is loaded from the SA and the hash -+ * result is saved to the state block where we -+ * retrieve it for return to the caller. -+ */ -+ /* XXX assert digest bufs have the same size */ -+ bcopy(ses->ses_hminner, sa->sa_indigest, -+ sizeof(sa->sa_indigest)); -+ bcopy(ses->ses_hmouter, sa->sa_outdigest, -+ sizeof(sa->sa_outdigest)); -+ -+ cmd0 |= SAFE_SA_CMD0_HSLD_SA | SAFE_SA_CMD0_SAVEHASH; -+ re->re_flags |= SAFE_QFLAGS_COPYOUTICV; -+ } -+ -+ if (enccrd && maccrd) { -+ /* -+ * The offset from hash data to the start of -+ * crypt data is the difference in the skips. -+ */ -+ bypass = maccrd->crd_skip; -+ coffset = enccrd->crd_skip - maccrd->crd_skip; -+ if (coffset < 0) { -+ DPRINTF(("%s: hash does not precede crypt; " -+ "mac skip %u enc skip %u\n", -+ __func__, maccrd->crd_skip, enccrd->crd_skip)); -+ safestats.st_skipmismatch++; -+ err = EINVAL; -+ goto errout; -+ } -+ oplen = enccrd->crd_skip + enccrd->crd_len; -+ if (maccrd->crd_skip + maccrd->crd_len != oplen) { -+ DPRINTF(("%s: hash amount %u != crypt amount %u\n", -+ __func__, maccrd->crd_skip + maccrd->crd_len, -+ oplen)); -+ safestats.st_lenmismatch++; -+ err = EINVAL; -+ goto errout; -+ } -+#ifdef SAFE_DEBUG -+ if (debug) { -+ printf("mac: skip %d, len %d, inject %d\n", -+ maccrd->crd_skip, maccrd->crd_len, -+ maccrd->crd_inject); -+ printf("enc: skip %d, len %d, inject %d\n", -+ enccrd->crd_skip, enccrd->crd_len, -+ enccrd->crd_inject); -+ printf("bypass %d coffset %d oplen %d\n", -+ bypass, coffset, oplen); -+ } -+#endif -+ if (coffset & 3) { /* offset must be 32-bit aligned */ -+ DPRINTF(("%s: coffset %u misaligned\n", -+ __func__, coffset)); -+ safestats.st_coffmisaligned++; -+ err = EINVAL; -+ goto errout; -+ } -+ coffset >>= 2; -+ if (coffset > 255) { /* offset must be <256 dwords */ -+ DPRINTF(("%s: coffset %u too big\n", -+ __func__, coffset)); -+ safestats.st_cofftoobig++; -+ err = EINVAL; -+ goto errout; -+ } -+ /* -+ * Tell the hardware to copy the header to the output. -+ * The header is defined as the data from the end of -+ * the bypass to the start of data to be encrypted. -+ * Typically this is the inline IV. Note that you need -+ * to do this even if src+dst are the same; it appears -+ * that w/o this bit the crypted data is written -+ * immediately after the bypass data. -+ */ -+ cmd1 |= SAFE_SA_CMD1_HDRCOPY; -+ /* -+ * Disable IP header mutable bit handling. This is -+ * needed to get correct HMAC calculations. -+ */ -+ cmd1 |= SAFE_SA_CMD1_MUTABLE; -+ } else { -+ if (enccrd) { -+ bypass = enccrd->crd_skip; -+ oplen = bypass + enccrd->crd_len; -+ } else { -+ bypass = maccrd->crd_skip; -+ oplen = bypass + maccrd->crd_len; -+ } -+ coffset = 0; -+ } -+ /* XXX verify multiple of 4 when using s/g */ -+ if (bypass > 96) { /* bypass offset must be <= 96 bytes */ -+ DPRINTF(("%s: bypass %u too big\n", __func__, bypass)); -+ safestats.st_bypasstoobig++; -+ err = EINVAL; -+ goto errout; -+ } -+ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ if (pci_map_skb(sc, &re->re_src, re->re_src_skb)) { -+ safestats.st_noload++; -+ err = ENOMEM; -+ goto errout; -+ } -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ if (pci_map_uio(sc, &re->re_src, re->re_src_io)) { -+ safestats.st_noload++; -+ err = ENOMEM; -+ goto errout; -+ } -+ } -+ nicealign = safe_dmamap_aligned(sc, &re->re_src); -+ uniform = safe_dmamap_uniform(sc, &re->re_src); -+ -+ DPRINTF(("src nicealign %u uniform %u nsegs %u\n", -+ nicealign, uniform, re->re_src.nsegs)); -+ if (re->re_src.nsegs > 1) { -+ re->re_desc.d_src = sc->sc_spalloc.dma_paddr + -+ ((caddr_t) sc->sc_spfree - (caddr_t) sc->sc_spring); -+ for (i = 0; i < re->re_src_nsegs; i++) { -+ /* NB: no need to check if there's space */ -+ pd = sc->sc_spfree; -+ if (++(sc->sc_spfree) == sc->sc_springtop) -+ sc->sc_spfree = sc->sc_spring; -+ -+ KASSERT((pd->pd_flags&3) == 0 || -+ (pd->pd_flags&3) == SAFE_PD_DONE, -+ ("bogus source particle descriptor; flags %x", -+ pd->pd_flags)); -+ pd->pd_addr = re->re_src_segs[i].ds_addr; -+ pd->pd_size = re->re_src_segs[i].ds_len; -+ pd->pd_flags = SAFE_PD_READY; -+ } -+ cmd0 |= SAFE_SA_CMD0_IGATHER; -+ } else { -+ /* -+ * No need for gather, reference the operand directly. -+ */ -+ re->re_desc.d_src = re->re_src_segs[0].ds_addr; -+ } -+ -+ if (enccrd == NULL && maccrd != NULL) { -+ /* -+ * Hash op; no destination needed. -+ */ -+ } else { -+ if (crp->crp_flags & (CRYPTO_F_IOV|CRYPTO_F_SKBUF)) { -+ if (!nicealign) { -+ safestats.st_iovmisaligned++; -+ err = EINVAL; -+ goto errout; -+ } -+ if (uniform != 1) { -+ device_printf(sc->sc_dev, "!uniform source\n"); -+ if (!uniform) { -+ /* -+ * There's no way to handle the DMA -+ * requirements with this uio. We -+ * could create a separate DMA area for -+ * the result and then copy it back, -+ * but for now we just bail and return -+ * an error. Note that uio requests -+ * > SAFE_MAX_DSIZE are handled because -+ * the DMA map and segment list for the -+ * destination wil result in a -+ * destination particle list that does -+ * the necessary scatter DMA. -+ */ -+ safestats.st_iovnotuniform++; -+ err = EINVAL; -+ goto errout; -+ } -+ } else -+ re->re_dst = re->re_src; -+ } else { -+ safestats.st_badflags++; -+ err = EINVAL; -+ goto errout; -+ } -+ -+ if (re->re_dst.nsegs > 1) { -+ re->re_desc.d_dst = sc->sc_dpalloc.dma_paddr + -+ ((caddr_t) sc->sc_dpfree - (caddr_t) sc->sc_dpring); -+ for (i = 0; i < re->re_dst_nsegs; i++) { -+ pd = sc->sc_dpfree; -+ KASSERT((pd->pd_flags&3) == 0 || -+ (pd->pd_flags&3) == SAFE_PD_DONE, -+ ("bogus dest particle descriptor; flags %x", -+ pd->pd_flags)); -+ if (++(sc->sc_dpfree) == sc->sc_dpringtop) -+ sc->sc_dpfree = sc->sc_dpring; -+ pd->pd_addr = re->re_dst_segs[i].ds_addr; -+ pd->pd_flags = SAFE_PD_READY; -+ } -+ cmd0 |= SAFE_SA_CMD0_OSCATTER; -+ } else { -+ /* -+ * No need for scatter, reference the operand directly. -+ */ -+ re->re_desc.d_dst = re->re_dst_segs[0].ds_addr; -+ } -+ } -+ -+ /* -+ * All done with setup; fillin the SA command words -+ * and the packet engine descriptor. The operation -+ * is now ready for submission to the hardware. -+ */ -+ sa->sa_cmd0 = cmd0 | SAFE_SA_CMD0_IPCI | SAFE_SA_CMD0_OPCI; -+ sa->sa_cmd1 = cmd1 -+ | (coffset << SAFE_SA_CMD1_OFFSET_S) -+ | SAFE_SA_CMD1_SAREV1 /* Rev 1 SA data structure */ -+ | SAFE_SA_CMD1_SRPCI -+ ; -+ /* -+ * NB: the order of writes is important here. In case the -+ * chip is scanning the ring because of an outstanding request -+ * it might nab this one too. In that case we need to make -+ * sure the setup is complete before we write the length -+ * field of the descriptor as it signals the descriptor is -+ * ready for processing. -+ */ -+ re->re_desc.d_csr = SAFE_PE_CSR_READY | SAFE_PE_CSR_SAPCI; -+ if (maccrd) -+ re->re_desc.d_csr |= SAFE_PE_CSR_LOADSA | SAFE_PE_CSR_HASHFINAL; -+ wmb(); -+ re->re_desc.d_len = oplen -+ | SAFE_PE_LEN_READY -+ | (bypass << SAFE_PE_LEN_BYPASS_S) -+ ; -+ -+ safestats.st_ipackets++; -+ safestats.st_ibytes += oplen; -+ -+ if (++(sc->sc_front) == sc->sc_ringtop) -+ sc->sc_front = sc->sc_ring; -+ -+ /* XXX honor batching */ -+ safe_feed(sc, re); -+ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); -+ return (0); -+ -+errout: -+ if (re->re_src.map != re->re_dst.map) -+ pci_unmap_operand(sc, &re->re_dst); -+ if (re->re_src.map) -+ pci_unmap_operand(sc, &re->re_src); -+ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); -+ if (err != ERESTART) { -+ crp->crp_etype = err; -+ crypto_done(crp); -+ } else { -+ sc->sc_needwakeup |= CRYPTO_SYMQ; -+ } -+ return (err); -+} -+ -+static void -+safe_callback(struct safe_softc *sc, struct safe_ringentry *re) -+{ -+ struct cryptop *crp = (struct cryptop *)re->re_crp; -+ struct cryptodesc *crd; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ safestats.st_opackets++; -+ safestats.st_obytes += re->re_dst.mapsize; -+ -+ if (re->re_desc.d_csr & SAFE_PE_CSR_STATUS) { -+ device_printf(sc->sc_dev, "csr 0x%x cmd0 0x%x cmd1 0x%x\n", -+ re->re_desc.d_csr, -+ re->re_sa.sa_cmd0, re->re_sa.sa_cmd1); -+ safestats.st_peoperr++; -+ crp->crp_etype = EIO; /* something more meaningful? */ -+ } -+ -+ if (re->re_dst.map != NULL && re->re_dst.map != re->re_src.map) -+ pci_unmap_operand(sc, &re->re_dst); -+ pci_unmap_operand(sc, &re->re_src); -+ -+ /* -+ * If result was written to a differet mbuf chain, swap -+ * it in as the return value and reclaim the original. -+ */ -+ if ((crp->crp_flags & CRYPTO_F_SKBUF) && re->re_src_skb != re->re_dst_skb) { -+ device_printf(sc->sc_dev, "no CRYPTO_F_SKBUF swapping support\n"); -+ /* kfree_skb(skb) */ -+ /* crp->crp_buf = (caddr_t)re->re_dst_skb */ -+ return; -+ } -+ -+ if (re->re_flags & SAFE_QFLAGS_COPYOUTICV) { -+ /* copy out ICV result */ -+ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { -+ if (!(crd->crd_alg == CRYPTO_MD5_HMAC || -+ crd->crd_alg == CRYPTO_SHA1_HMAC || -+ crd->crd_alg == CRYPTO_NULL_HMAC)) -+ continue; -+ if (crd->crd_alg == CRYPTO_SHA1_HMAC) { -+ /* -+ * SHA-1 ICV's are byte-swapped; fix 'em up -+ * before copy them to their destination. -+ */ -+ re->re_sastate.sa_saved_indigest[0] = -+ cpu_to_be32(re->re_sastate.sa_saved_indigest[0]); -+ re->re_sastate.sa_saved_indigest[1] = -+ cpu_to_be32(re->re_sastate.sa_saved_indigest[1]); -+ re->re_sastate.sa_saved_indigest[2] = -+ cpu_to_be32(re->re_sastate.sa_saved_indigest[2]); -+ } else { -+ re->re_sastate.sa_saved_indigest[0] = -+ cpu_to_le32(re->re_sastate.sa_saved_indigest[0]); -+ re->re_sastate.sa_saved_indigest[1] = -+ cpu_to_le32(re->re_sastate.sa_saved_indigest[1]); -+ re->re_sastate.sa_saved_indigest[2] = -+ cpu_to_le32(re->re_sastate.sa_saved_indigest[2]); -+ } -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, -+ sc->sc_sessions[re->re_sesn].ses_mlen, -+ (caddr_t)re->re_sastate.sa_saved_indigest); -+ break; -+ } -+ } -+ crypto_done(crp); -+} -+ -+ -+#if defined(CONFIG_OCF_RANDOMHARVEST) && !defined(SAFE_NO_RNG) -+#define SAFE_RNG_MAXWAIT 1000 -+ -+static void -+safe_rng_init(struct safe_softc *sc) -+{ -+ u_int32_t w, v; -+ int i; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ WRITE_REG(sc, SAFE_RNG_CTRL, 0); -+ /* use default value according to the manual */ -+ WRITE_REG(sc, SAFE_RNG_CNFG, 0x834); /* magic from SafeNet */ -+ WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); -+ -+ /* -+ * There is a bug in rev 1.0 of the 1140 that when the RNG -+ * is brought out of reset the ready status flag does not -+ * work until the RNG has finished its internal initialization. -+ * -+ * So in order to determine the device is through its -+ * initialization we must read the data register, using the -+ * status reg in the read in case it is initialized. Then read -+ * the data register until it changes from the first read. -+ * Once it changes read the data register until it changes -+ * again. At this time the RNG is considered initialized. -+ * This could take between 750ms - 1000ms in time. -+ */ -+ i = 0; -+ w = READ_REG(sc, SAFE_RNG_OUT); -+ do { -+ v = READ_REG(sc, SAFE_RNG_OUT); -+ if (v != w) { -+ w = v; -+ break; -+ } -+ DELAY(10); -+ } while (++i < SAFE_RNG_MAXWAIT); -+ -+ /* Wait Until data changes again */ -+ i = 0; -+ do { -+ v = READ_REG(sc, SAFE_RNG_OUT); -+ if (v != w) -+ break; -+ DELAY(10); -+ } while (++i < SAFE_RNG_MAXWAIT); -+} -+ -+static __inline void -+safe_rng_disable_short_cycle(struct safe_softc *sc) -+{ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ WRITE_REG(sc, SAFE_RNG_CTRL, -+ READ_REG(sc, SAFE_RNG_CTRL) &~ SAFE_RNG_CTRL_SHORTEN); -+} -+ -+static __inline void -+safe_rng_enable_short_cycle(struct safe_softc *sc) -+{ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ WRITE_REG(sc, SAFE_RNG_CTRL, -+ READ_REG(sc, SAFE_RNG_CTRL) | SAFE_RNG_CTRL_SHORTEN); -+} -+ -+static __inline u_int32_t -+safe_rng_read(struct safe_softc *sc) -+{ -+ int i; -+ -+ i = 0; -+ while (READ_REG(sc, SAFE_RNG_STAT) != 0 && ++i < SAFE_RNG_MAXWAIT) -+ ; -+ return READ_REG(sc, SAFE_RNG_OUT); -+} -+ -+static int -+safe_read_random(void *arg, u_int32_t *buf, int maxwords) -+{ -+ struct safe_softc *sc = (struct safe_softc *) arg; -+ int i, rc; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ safestats.st_rng++; -+ /* -+ * Fetch the next block of data. -+ */ -+ if (maxwords > safe_rngbufsize) -+ maxwords = safe_rngbufsize; -+ if (maxwords > SAFE_RNG_MAXBUFSIZ) -+ maxwords = SAFE_RNG_MAXBUFSIZ; -+retry: -+ /* read as much as we can */ -+ for (rc = 0; rc < maxwords; rc++) { -+ if (READ_REG(sc, SAFE_RNG_STAT) != 0) -+ break; -+ buf[rc] = READ_REG(sc, SAFE_RNG_OUT); -+ } -+ if (rc == 0) -+ return 0; -+ /* -+ * Check the comparator alarm count and reset the h/w if -+ * it exceeds our threshold. This guards against the -+ * hardware oscillators resonating with external signals. -+ */ -+ if (READ_REG(sc, SAFE_RNG_ALM_CNT) > safe_rngmaxalarm) { -+ u_int32_t freq_inc, w; -+ -+ DPRINTF(("%s: alarm count %u exceeds threshold %u\n", __func__, -+ (unsigned)READ_REG(sc, SAFE_RNG_ALM_CNT), safe_rngmaxalarm)); -+ safestats.st_rngalarm++; -+ safe_rng_enable_short_cycle(sc); -+ freq_inc = 18; -+ for (i = 0; i < 64; i++) { -+ w = READ_REG(sc, SAFE_RNG_CNFG); -+ freq_inc = ((w + freq_inc) & 0x3fL); -+ w = ((w & ~0x3fL) | freq_inc); -+ WRITE_REG(sc, SAFE_RNG_CNFG, w); -+ -+ WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); -+ -+ (void) safe_rng_read(sc); -+ DELAY(25); -+ -+ if (READ_REG(sc, SAFE_RNG_ALM_CNT) == 0) { -+ safe_rng_disable_short_cycle(sc); -+ goto retry; -+ } -+ freq_inc = 1; -+ } -+ safe_rng_disable_short_cycle(sc); -+ } else -+ WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); -+ -+ return(rc); -+} -+#endif /* defined(CONFIG_OCF_RANDOMHARVEST) && !defined(SAFE_NO_RNG) */ -+ -+ -+/* -+ * Resets the board. Values in the regesters are left as is -+ * from the reset (i.e. initial values are assigned elsewhere). -+ */ -+static void -+safe_reset_board(struct safe_softc *sc) -+{ -+ u_int32_t v; -+ /* -+ * Reset the device. The manual says no delay -+ * is needed between marking and clearing reset. -+ */ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ v = READ_REG(sc, SAFE_PE_DMACFG) &~ -+ (SAFE_PE_DMACFG_PERESET | SAFE_PE_DMACFG_PDRRESET | -+ SAFE_PE_DMACFG_SGRESET); -+ WRITE_REG(sc, SAFE_PE_DMACFG, v -+ | SAFE_PE_DMACFG_PERESET -+ | SAFE_PE_DMACFG_PDRRESET -+ | SAFE_PE_DMACFG_SGRESET); -+ WRITE_REG(sc, SAFE_PE_DMACFG, v); -+} -+ -+/* -+ * Initialize registers we need to touch only once. -+ */ -+static void -+safe_init_board(struct safe_softc *sc) -+{ -+ u_int32_t v, dwords; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ v = READ_REG(sc, SAFE_PE_DMACFG); -+ v &=~ ( SAFE_PE_DMACFG_PEMODE -+ | SAFE_PE_DMACFG_FSENA /* failsafe enable */ -+ | SAFE_PE_DMACFG_GPRPCI /* gather ring on PCI */ -+ | SAFE_PE_DMACFG_SPRPCI /* scatter ring on PCI */ -+ | SAFE_PE_DMACFG_ESDESC /* endian-swap descriptors */ -+ | SAFE_PE_DMACFG_ESPDESC /* endian-swap part. desc's */ -+ | SAFE_PE_DMACFG_ESSA /* endian-swap SA's */ -+ | SAFE_PE_DMACFG_ESPACKET /* swap the packet data */ -+ ); -+ v |= SAFE_PE_DMACFG_FSENA /* failsafe enable */ -+ | SAFE_PE_DMACFG_GPRPCI /* gather ring on PCI */ -+ | SAFE_PE_DMACFG_SPRPCI /* scatter ring on PCI */ -+ | SAFE_PE_DMACFG_ESDESC /* endian-swap descriptors */ -+ | SAFE_PE_DMACFG_ESPDESC /* endian-swap part. desc's */ -+ | SAFE_PE_DMACFG_ESSA /* endian-swap SA's */ -+#if 0 -+ | SAFE_PE_DMACFG_ESPACKET /* swap the packet data */ -+#endif -+ ; -+ WRITE_REG(sc, SAFE_PE_DMACFG, v); -+ -+#ifdef __BIG_ENDIAN -+ /* tell the safenet that we are 4321 and not 1234 */ -+ WRITE_REG(sc, SAFE_ENDIAN, 0xe4e41b1b); -+#endif -+ -+ if (sc->sc_chiprev == SAFE_REV(1,0)) { -+ /* -+ * Avoid large PCI DMA transfers. Rev 1.0 has a bug where -+ * "target mode transfers" done while the chip is DMA'ing -+ * >1020 bytes cause the hardware to lockup. To avoid this -+ * we reduce the max PCI transfer size and use small source -+ * particle descriptors (<= 256 bytes). -+ */ -+ WRITE_REG(sc, SAFE_DMA_CFG, 256); -+ device_printf(sc->sc_dev, -+ "Reduce max DMA size to %u words for rev %u.%u WAR\n", -+ (unsigned) ((READ_REG(sc, SAFE_DMA_CFG)>>2) & 0xff), -+ (unsigned) SAFE_REV_MAJ(sc->sc_chiprev), -+ (unsigned) SAFE_REV_MIN(sc->sc_chiprev)); -+ sc->sc_max_dsize = 256; -+ } else { -+ sc->sc_max_dsize = SAFE_MAX_DSIZE; -+ } -+ -+ /* NB: operands+results are overlaid */ -+ WRITE_REG(sc, SAFE_PE_PDRBASE, sc->sc_ringalloc.dma_paddr); -+ WRITE_REG(sc, SAFE_PE_RDRBASE, sc->sc_ringalloc.dma_paddr); -+ /* -+ * Configure ring entry size and number of items in the ring. -+ */ -+ KASSERT((sizeof(struct safe_ringentry) % sizeof(u_int32_t)) == 0, -+ ("PE ring entry not 32-bit aligned!")); -+ dwords = sizeof(struct safe_ringentry) / sizeof(u_int32_t); -+ WRITE_REG(sc, SAFE_PE_RINGCFG, -+ (dwords << SAFE_PE_RINGCFG_OFFSET_S) | SAFE_MAX_NQUEUE); -+ WRITE_REG(sc, SAFE_PE_RINGPOLL, 0); /* disable polling */ -+ -+ WRITE_REG(sc, SAFE_PE_GRNGBASE, sc->sc_spalloc.dma_paddr); -+ WRITE_REG(sc, SAFE_PE_SRNGBASE, sc->sc_dpalloc.dma_paddr); -+ WRITE_REG(sc, SAFE_PE_PARTSIZE, -+ (SAFE_TOTAL_DPART<<16) | SAFE_TOTAL_SPART); -+ /* -+ * NB: destination particles are fixed size. We use -+ * an mbuf cluster and require all results go to -+ * clusters or smaller. -+ */ -+ WRITE_REG(sc, SAFE_PE_PARTCFG, sc->sc_max_dsize); -+ -+ /* it's now safe to enable PE mode, do it */ -+ WRITE_REG(sc, SAFE_PE_DMACFG, v | SAFE_PE_DMACFG_PEMODE); -+ -+ /* -+ * Configure hardware to use level-triggered interrupts and -+ * to interrupt after each descriptor is processed. -+ */ -+ WRITE_REG(sc, SAFE_HI_CFG, SAFE_HI_CFG_LEVEL); -+ WRITE_REG(sc, SAFE_HI_CLR, 0xffffffff); -+ WRITE_REG(sc, SAFE_HI_DESC_CNT, 1); -+ WRITE_REG(sc, SAFE_HI_MASK, SAFE_INT_PE_DDONE | SAFE_INT_PE_ERROR); -+} -+ -+ -+/* -+ * Clean up after a chip crash. -+ * It is assumed that the caller in splimp() -+ */ -+static void -+safe_cleanchip(struct safe_softc *sc) -+{ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (sc->sc_nqchip != 0) { -+ struct safe_ringentry *re = sc->sc_back; -+ -+ while (re != sc->sc_front) { -+ if (re->re_desc.d_csr != 0) -+ safe_free_entry(sc, re); -+ if (++re == sc->sc_ringtop) -+ re = sc->sc_ring; -+ } -+ sc->sc_back = re; -+ sc->sc_nqchip = 0; -+ } -+} -+ -+/* -+ * free a safe_q -+ * It is assumed that the caller is within splimp(). -+ */ -+static int -+safe_free_entry(struct safe_softc *sc, struct safe_ringentry *re) -+{ -+ struct cryptop *crp; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ /* -+ * Free header MCR -+ */ -+ if ((re->re_dst_skb != NULL) && (re->re_src_skb != re->re_dst_skb)) -+#ifdef NOTYET -+ m_freem(re->re_dst_m); -+#else -+ printk("%s,%d: SKB not supported\n", __FILE__, __LINE__); -+#endif -+ -+ crp = (struct cryptop *)re->re_crp; -+ -+ re->re_desc.d_csr = 0; -+ -+ crp->crp_etype = EFAULT; -+ crypto_done(crp); -+ return(0); -+} -+ -+/* -+ * Routine to reset the chip and clean up. -+ * It is assumed that the caller is in splimp() -+ */ -+static void -+safe_totalreset(struct safe_softc *sc) -+{ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ safe_reset_board(sc); -+ safe_init_board(sc); -+ safe_cleanchip(sc); -+} -+ -+/* -+ * Is the operand suitable aligned for direct DMA. Each -+ * segment must be aligned on a 32-bit boundary and all -+ * but the last segment must be a multiple of 4 bytes. -+ */ -+static int -+safe_dmamap_aligned(struct safe_softc *sc, const struct safe_operand *op) -+{ -+ int i; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ for (i = 0; i < op->nsegs; i++) { -+ if (op->segs[i].ds_addr & 3) -+ return (0); -+ if (i != (op->nsegs - 1) && (op->segs[i].ds_len & 3)) -+ return (0); -+ } -+ return (1); -+} -+ -+/* -+ * Is the operand suitable for direct DMA as the destination -+ * of an operation. The hardware requires that each ``particle'' -+ * but the last in an operation result have the same size. We -+ * fix that size at SAFE_MAX_DSIZE bytes. This routine returns -+ * 0 if some segment is not a multiple of of this size, 1 if all -+ * segments are exactly this size, or 2 if segments are at worst -+ * a multple of this size. -+ */ -+static int -+safe_dmamap_uniform(struct safe_softc *sc, const struct safe_operand *op) -+{ -+ int result = 1; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (op->nsegs > 0) { -+ int i; -+ -+ for (i = 0; i < op->nsegs-1; i++) { -+ if (op->segs[i].ds_len % sc->sc_max_dsize) -+ return (0); -+ if (op->segs[i].ds_len != sc->sc_max_dsize) -+ result = 2; -+ } -+ } -+ return (result); -+} -+ -+static int -+safe_kprocess(device_t dev, struct cryptkop *krp, int hint) -+{ -+ struct safe_softc *sc = device_get_softc(dev); -+ struct safe_pkq *q; -+ unsigned long flags; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (sc == NULL) { -+ krp->krp_status = EINVAL; -+ goto err; -+ } -+ -+ if (krp->krp_op != CRK_MOD_EXP) { -+ krp->krp_status = EOPNOTSUPP; -+ goto err; -+ } -+ -+ q = (struct safe_pkq *) kmalloc(sizeof(*q), GFP_KERNEL); -+ if (q == NULL) { -+ krp->krp_status = ENOMEM; -+ goto err; -+ } -+ memset(q, 0, sizeof(*q)); -+ q->pkq_krp = krp; -+ INIT_LIST_HEAD(&q->pkq_list); -+ -+ spin_lock_irqsave(&sc->sc_pkmtx, flags); -+ list_add_tail(&q->pkq_list, &sc->sc_pkq); -+ safe_kfeed(sc); -+ spin_unlock_irqrestore(&sc->sc_pkmtx, flags); -+ return (0); -+ -+err: -+ crypto_kdone(krp); -+ return (0); -+} -+ -+#define SAFE_CRK_PARAM_BASE 0 -+#define SAFE_CRK_PARAM_EXP 1 -+#define SAFE_CRK_PARAM_MOD 2 -+ -+static int -+safe_kstart(struct safe_softc *sc) -+{ -+ struct cryptkop *krp = sc->sc_pkq_cur->pkq_krp; -+ int exp_bits, mod_bits, base_bits; -+ u_int32_t op, a_off, b_off, c_off, d_off; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (krp->krp_iparams < 3 || krp->krp_oparams != 1) { -+ krp->krp_status = EINVAL; -+ return (1); -+ } -+ -+ base_bits = safe_ksigbits(sc, &krp->krp_param[SAFE_CRK_PARAM_BASE]); -+ if (base_bits > 2048) -+ goto too_big; -+ if (base_bits <= 0) /* 5. base not zero */ -+ goto too_small; -+ -+ exp_bits = safe_ksigbits(sc, &krp->krp_param[SAFE_CRK_PARAM_EXP]); -+ if (exp_bits > 2048) -+ goto too_big; -+ if (exp_bits <= 0) /* 1. exponent word length > 0 */ -+ goto too_small; /* 4. exponent not zero */ -+ -+ mod_bits = safe_ksigbits(sc, &krp->krp_param[SAFE_CRK_PARAM_MOD]); -+ if (mod_bits > 2048) -+ goto too_big; -+ if (mod_bits <= 32) /* 2. modulus word length > 1 */ -+ goto too_small; /* 8. MSW of modulus != zero */ -+ if (mod_bits < exp_bits) /* 3 modulus len >= exponent len */ -+ goto too_small; -+ if ((krp->krp_param[SAFE_CRK_PARAM_MOD].crp_p[0] & 1) == 0) -+ goto bad_domain; /* 6. modulus is odd */ -+ if (mod_bits > krp->krp_param[krp->krp_iparams].crp_nbits) -+ goto too_small; /* make sure result will fit */ -+ -+ /* 7. modulus > base */ -+ if (mod_bits < base_bits) -+ goto too_small; -+ if (mod_bits == base_bits) { -+ u_int8_t *basep, *modp; -+ int i; -+ -+ basep = krp->krp_param[SAFE_CRK_PARAM_BASE].crp_p + -+ ((base_bits + 7) / 8) - 1; -+ modp = krp->krp_param[SAFE_CRK_PARAM_MOD].crp_p + -+ ((mod_bits + 7) / 8) - 1; -+ -+ for (i = 0; i < (mod_bits + 7) / 8; i++, basep--, modp--) { -+ if (*modp < *basep) -+ goto too_small; -+ if (*modp > *basep) -+ break; -+ } -+ } -+ -+ /* And on the 9th step, he rested. */ -+ -+ WRITE_REG(sc, SAFE_PK_A_LEN, (exp_bits + 31) / 32); -+ WRITE_REG(sc, SAFE_PK_B_LEN, (mod_bits + 31) / 32); -+ if (mod_bits > 1024) { -+ op = SAFE_PK_FUNC_EXP4; -+ a_off = 0x000; -+ b_off = 0x100; -+ c_off = 0x200; -+ d_off = 0x300; -+ } else { -+ op = SAFE_PK_FUNC_EXP16; -+ a_off = 0x000; -+ b_off = 0x080; -+ c_off = 0x100; -+ d_off = 0x180; -+ } -+ sc->sc_pk_reslen = b_off - a_off; -+ sc->sc_pk_resoff = d_off; -+ -+ /* A is exponent, B is modulus, C is base, D is result */ -+ safe_kload_reg(sc, a_off, b_off - a_off, -+ &krp->krp_param[SAFE_CRK_PARAM_EXP]); -+ WRITE_REG(sc, SAFE_PK_A_ADDR, a_off >> 2); -+ safe_kload_reg(sc, b_off, b_off - a_off, -+ &krp->krp_param[SAFE_CRK_PARAM_MOD]); -+ WRITE_REG(sc, SAFE_PK_B_ADDR, b_off >> 2); -+ safe_kload_reg(sc, c_off, b_off - a_off, -+ &krp->krp_param[SAFE_CRK_PARAM_BASE]); -+ WRITE_REG(sc, SAFE_PK_C_ADDR, c_off >> 2); -+ WRITE_REG(sc, SAFE_PK_D_ADDR, d_off >> 2); -+ -+ WRITE_REG(sc, SAFE_PK_FUNC, op | SAFE_PK_FUNC_RUN); -+ -+ return (0); -+ -+too_big: -+ krp->krp_status = E2BIG; -+ return (1); -+too_small: -+ krp->krp_status = ERANGE; -+ return (1); -+bad_domain: -+ krp->krp_status = EDOM; -+ return (1); -+} -+ -+static int -+safe_ksigbits(struct safe_softc *sc, struct crparam *cr) -+{ -+ u_int plen = (cr->crp_nbits + 7) / 8; -+ int i, sig = plen * 8; -+ u_int8_t c, *p = cr->crp_p; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ for (i = plen - 1; i >= 0; i--) { -+ c = p[i]; -+ if (c != 0) { -+ while ((c & 0x80) == 0) { -+ sig--; -+ c <<= 1; -+ } -+ break; -+ } -+ sig -= 8; -+ } -+ return (sig); -+} -+ -+static void -+safe_kfeed(struct safe_softc *sc) -+{ -+ struct safe_pkq *q, *tmp; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (list_empty(&sc->sc_pkq) && sc->sc_pkq_cur == NULL) -+ return; -+ if (sc->sc_pkq_cur != NULL) -+ return; -+ list_for_each_entry_safe(q, tmp, &sc->sc_pkq, pkq_list) { -+ sc->sc_pkq_cur = q; -+ list_del(&q->pkq_list); -+ if (safe_kstart(sc) != 0) { -+ crypto_kdone(q->pkq_krp); -+ kfree(q); -+ sc->sc_pkq_cur = NULL; -+ } else { -+ /* op started, start polling */ -+ mod_timer(&sc->sc_pkto, jiffies + 1); -+ break; -+ } -+ } -+} -+ -+static void -+safe_kpoll(unsigned long arg) -+{ -+ struct safe_softc *sc = NULL; -+ struct safe_pkq *q; -+ struct crparam *res; -+ int i; -+ u_int32_t buf[64]; -+ unsigned long flags; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (arg >= SAFE_MAX_CHIPS) -+ return; -+ sc = safe_chip_idx[arg]; -+ if (!sc) { -+ DPRINTF(("%s() - bad callback\n", __FUNCTION__)); -+ return; -+ } -+ -+ spin_lock_irqsave(&sc->sc_pkmtx, flags); -+ if (sc->sc_pkq_cur == NULL) -+ goto out; -+ if (READ_REG(sc, SAFE_PK_FUNC) & SAFE_PK_FUNC_RUN) { -+ /* still running, check back later */ -+ mod_timer(&sc->sc_pkto, jiffies + 1); -+ goto out; -+ } -+ -+ q = sc->sc_pkq_cur; -+ res = &q->pkq_krp->krp_param[q->pkq_krp->krp_iparams]; -+ bzero(buf, sizeof(buf)); -+ bzero(res->crp_p, (res->crp_nbits + 7) / 8); -+ for (i = 0; i < sc->sc_pk_reslen >> 2; i++) -+ buf[i] = le32_to_cpu(READ_REG(sc, SAFE_PK_RAM_START + -+ sc->sc_pk_resoff + (i << 2))); -+ bcopy(buf, res->crp_p, (res->crp_nbits + 7) / 8); -+ /* -+ * reduce the bits that need copying if possible -+ */ -+ res->crp_nbits = min(res->crp_nbits,sc->sc_pk_reslen * 8); -+ res->crp_nbits = safe_ksigbits(sc, res); -+ -+ for (i = SAFE_PK_RAM_START; i < SAFE_PK_RAM_END; i += 4) -+ WRITE_REG(sc, i, 0); -+ -+ crypto_kdone(q->pkq_krp); -+ kfree(q); -+ sc->sc_pkq_cur = NULL; -+ -+ safe_kfeed(sc); -+out: -+ spin_unlock_irqrestore(&sc->sc_pkmtx, flags); -+} -+ -+static void -+safe_kload_reg(struct safe_softc *sc, u_int32_t off, u_int32_t len, -+ struct crparam *n) -+{ -+ u_int32_t buf[64], i; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ bzero(buf, sizeof(buf)); -+ bcopy(n->crp_p, buf, (n->crp_nbits + 7) / 8); -+ -+ for (i = 0; i < len >> 2; i++) -+ WRITE_REG(sc, SAFE_PK_RAM_START + off + (i << 2), -+ cpu_to_le32(buf[i])); -+} -+ -+#ifdef SAFE_DEBUG -+static void -+safe_dump_dmastatus(struct safe_softc *sc, const char *tag) -+{ -+ printf("%s: ENDIAN 0x%x SRC 0x%x DST 0x%x STAT 0x%x\n" -+ , tag -+ , READ_REG(sc, SAFE_DMA_ENDIAN) -+ , READ_REG(sc, SAFE_DMA_SRCADDR) -+ , READ_REG(sc, SAFE_DMA_DSTADDR) -+ , READ_REG(sc, SAFE_DMA_STAT) -+ ); -+} -+ -+static void -+safe_dump_intrstate(struct safe_softc *sc, const char *tag) -+{ -+ printf("%s: HI_CFG 0x%x HI_MASK 0x%x HI_DESC_CNT 0x%x HU_STAT 0x%x HM_STAT 0x%x\n" -+ , tag -+ , READ_REG(sc, SAFE_HI_CFG) -+ , READ_REG(sc, SAFE_HI_MASK) -+ , READ_REG(sc, SAFE_HI_DESC_CNT) -+ , READ_REG(sc, SAFE_HU_STAT) -+ , READ_REG(sc, SAFE_HM_STAT) -+ ); -+} -+ -+static void -+safe_dump_ringstate(struct safe_softc *sc, const char *tag) -+{ -+ u_int32_t estat = READ_REG(sc, SAFE_PE_ERNGSTAT); -+ -+ /* NB: assume caller has lock on ring */ -+ printf("%s: ERNGSTAT %x (next %u) back %lu front %lu\n", -+ tag, -+ estat, (estat >> SAFE_PE_ERNGSTAT_NEXT_S), -+ (unsigned long)(sc->sc_back - sc->sc_ring), -+ (unsigned long)(sc->sc_front - sc->sc_ring)); -+} -+ -+static void -+safe_dump_request(struct safe_softc *sc, const char* tag, struct safe_ringentry *re) -+{ -+ int ix, nsegs; -+ -+ ix = re - sc->sc_ring; -+ printf("%s: %p (%u): csr %x src %x dst %x sa %x len %x\n" -+ , tag -+ , re, ix -+ , re->re_desc.d_csr -+ , re->re_desc.d_src -+ , re->re_desc.d_dst -+ , re->re_desc.d_sa -+ , re->re_desc.d_len -+ ); -+ if (re->re_src.nsegs > 1) { -+ ix = (re->re_desc.d_src - sc->sc_spalloc.dma_paddr) / -+ sizeof(struct safe_pdesc); -+ for (nsegs = re->re_src.nsegs; nsegs; nsegs--) { -+ printf(" spd[%u] %p: %p size %u flags %x" -+ , ix, &sc->sc_spring[ix] -+ , (caddr_t)(uintptr_t) sc->sc_spring[ix].pd_addr -+ , sc->sc_spring[ix].pd_size -+ , sc->sc_spring[ix].pd_flags -+ ); -+ if (sc->sc_spring[ix].pd_size == 0) -+ printf(" (zero!)"); -+ printf("\n"); -+ if (++ix == SAFE_TOTAL_SPART) -+ ix = 0; -+ } -+ } -+ if (re->re_dst.nsegs > 1) { -+ ix = (re->re_desc.d_dst - sc->sc_dpalloc.dma_paddr) / -+ sizeof(struct safe_pdesc); -+ for (nsegs = re->re_dst.nsegs; nsegs; nsegs--) { -+ printf(" dpd[%u] %p: %p flags %x\n" -+ , ix, &sc->sc_dpring[ix] -+ , (caddr_t)(uintptr_t) sc->sc_dpring[ix].pd_addr -+ , sc->sc_dpring[ix].pd_flags -+ ); -+ if (++ix == SAFE_TOTAL_DPART) -+ ix = 0; -+ } -+ } -+ printf("sa: cmd0 %08x cmd1 %08x staterec %x\n", -+ re->re_sa.sa_cmd0, re->re_sa.sa_cmd1, re->re_sa.sa_staterec); -+ printf("sa: key %x %x %x %x %x %x %x %x\n" -+ , re->re_sa.sa_key[0] -+ , re->re_sa.sa_key[1] -+ , re->re_sa.sa_key[2] -+ , re->re_sa.sa_key[3] -+ , re->re_sa.sa_key[4] -+ , re->re_sa.sa_key[5] -+ , re->re_sa.sa_key[6] -+ , re->re_sa.sa_key[7] -+ ); -+ printf("sa: indigest %x %x %x %x %x\n" -+ , re->re_sa.sa_indigest[0] -+ , re->re_sa.sa_indigest[1] -+ , re->re_sa.sa_indigest[2] -+ , re->re_sa.sa_indigest[3] -+ , re->re_sa.sa_indigest[4] -+ ); -+ printf("sa: outdigest %x %x %x %x %x\n" -+ , re->re_sa.sa_outdigest[0] -+ , re->re_sa.sa_outdigest[1] -+ , re->re_sa.sa_outdigest[2] -+ , re->re_sa.sa_outdigest[3] -+ , re->re_sa.sa_outdigest[4] -+ ); -+ printf("sr: iv %x %x %x %x\n" -+ , re->re_sastate.sa_saved_iv[0] -+ , re->re_sastate.sa_saved_iv[1] -+ , re->re_sastate.sa_saved_iv[2] -+ , re->re_sastate.sa_saved_iv[3] -+ ); -+ printf("sr: hashbc %u indigest %x %x %x %x %x\n" -+ , re->re_sastate.sa_saved_hashbc -+ , re->re_sastate.sa_saved_indigest[0] -+ , re->re_sastate.sa_saved_indigest[1] -+ , re->re_sastate.sa_saved_indigest[2] -+ , re->re_sastate.sa_saved_indigest[3] -+ , re->re_sastate.sa_saved_indigest[4] -+ ); -+} -+ -+static void -+safe_dump_ring(struct safe_softc *sc, const char *tag) -+{ -+ unsigned long flags; -+ -+ spin_lock_irqsave(&sc->sc_ringmtx, flags); -+ printf("\nSafeNet Ring State:\n"); -+ safe_dump_intrstate(sc, tag); -+ safe_dump_dmastatus(sc, tag); -+ safe_dump_ringstate(sc, tag); -+ if (sc->sc_nqchip) { -+ struct safe_ringentry *re = sc->sc_back; -+ do { -+ safe_dump_request(sc, tag, re); -+ if (++re == sc->sc_ringtop) -+ re = sc->sc_ring; -+ } while (re != sc->sc_front); -+ } -+ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); -+} -+#endif /* SAFE_DEBUG */ -+ -+ -+static int safe_probe(struct pci_dev *dev, const struct pci_device_id *ent) -+{ -+ struct safe_softc *sc = NULL; -+ u32 mem_start, mem_len, cmd; -+ int i, rc, devinfo; -+ dma_addr_t raddr; -+ static int num_chips = 0; -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ if (pci_enable_device(dev) < 0) -+ return(-ENODEV); -+ -+ if (!dev->irq) { -+ printk("safe: found device with no IRQ assigned. check BIOS settings!"); -+ pci_disable_device(dev); -+ return(-ENODEV); -+ } -+ -+ if (pci_set_mwi(dev)) { -+ printk("safe: pci_set_mwi failed!"); -+ return(-ENODEV); -+ } -+ -+ sc = (struct safe_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); -+ if (!sc) -+ return(-ENOMEM); -+ memset(sc, 0, sizeof(*sc)); -+ -+ softc_device_init(sc, "safe", num_chips, safe_methods); -+ -+ sc->sc_irq = -1; -+ sc->sc_cid = -1; -+ sc->sc_pcidev = dev; -+ if (num_chips < SAFE_MAX_CHIPS) { -+ safe_chip_idx[device_get_unit(sc->sc_dev)] = sc; -+ num_chips++; -+ } -+ -+ INIT_LIST_HEAD(&sc->sc_pkq); -+ spin_lock_init(&sc->sc_pkmtx); -+ -+ pci_set_drvdata(sc->sc_pcidev, sc); -+ -+ /* we read its hardware registers as memory */ -+ mem_start = pci_resource_start(sc->sc_pcidev, 0); -+ mem_len = pci_resource_len(sc->sc_pcidev, 0); -+ -+ sc->sc_base_addr = (ocf_iomem_t) ioremap(mem_start, mem_len); -+ if (!sc->sc_base_addr) { -+ device_printf(sc->sc_dev, "failed to ioremap 0x%x-0x%x\n", -+ mem_start, mem_start + mem_len - 1); -+ goto out; -+ } -+ -+ /* fix up the bus size */ -+ if (pci_set_dma_mask(sc->sc_pcidev, DMA_32BIT_MASK)) { -+ device_printf(sc->sc_dev, "No usable DMA configuration, aborting.\n"); -+ goto out; -+ } -+ if (pci_set_consistent_dma_mask(sc->sc_pcidev, DMA_32BIT_MASK)) { -+ device_printf(sc->sc_dev, "No usable consistent DMA configuration, aborting.\n"); -+ goto out; -+ } -+ -+ pci_set_master(sc->sc_pcidev); -+ -+ pci_read_config_dword(sc->sc_pcidev, PCI_COMMAND, &cmd); -+ -+ if (!(cmd & PCI_COMMAND_MEMORY)) { -+ device_printf(sc->sc_dev, "failed to enable memory mapping\n"); -+ goto out; -+ } -+ -+ if (!(cmd & PCI_COMMAND_MASTER)) { -+ device_printf(sc->sc_dev, "failed to enable bus mastering\n"); -+ goto out; -+ } -+ -+ rc = request_irq(dev->irq, safe_intr, IRQF_SHARED, "safe", sc); -+ if (rc) { -+ device_printf(sc->sc_dev, "failed to hook irq %d\n", sc->sc_irq); -+ goto out; -+ } -+ sc->sc_irq = dev->irq; -+ -+ sc->sc_chiprev = READ_REG(sc, SAFE_DEVINFO) & -+ (SAFE_DEVINFO_REV_MAJ | SAFE_DEVINFO_REV_MIN); -+ -+ /* -+ * Allocate packet engine descriptors. -+ */ -+ sc->sc_ringalloc.dma_vaddr = pci_alloc_consistent(sc->sc_pcidev, -+ SAFE_MAX_NQUEUE * sizeof (struct safe_ringentry), -+ &sc->sc_ringalloc.dma_paddr); -+ if (!sc->sc_ringalloc.dma_vaddr) { -+ device_printf(sc->sc_dev, "cannot allocate PE descriptor ring\n"); -+ goto out; -+ } -+ -+ /* -+ * Hookup the static portion of all our data structures. -+ */ -+ sc->sc_ring = (struct safe_ringentry *) sc->sc_ringalloc.dma_vaddr; -+ sc->sc_ringtop = sc->sc_ring + SAFE_MAX_NQUEUE; -+ sc->sc_front = sc->sc_ring; -+ sc->sc_back = sc->sc_ring; -+ raddr = sc->sc_ringalloc.dma_paddr; -+ bzero(sc->sc_ring, SAFE_MAX_NQUEUE * sizeof(struct safe_ringentry)); -+ for (i = 0; i < SAFE_MAX_NQUEUE; i++) { -+ struct safe_ringentry *re = &sc->sc_ring[i]; -+ -+ re->re_desc.d_sa = raddr + -+ offsetof(struct safe_ringentry, re_sa); -+ re->re_sa.sa_staterec = raddr + -+ offsetof(struct safe_ringentry, re_sastate); -+ -+ raddr += sizeof (struct safe_ringentry); -+ } -+ spin_lock_init(&sc->sc_ringmtx); -+ -+ /* -+ * Allocate scatter and gather particle descriptors. -+ */ -+ sc->sc_spalloc.dma_vaddr = pci_alloc_consistent(sc->sc_pcidev, -+ SAFE_TOTAL_SPART * sizeof (struct safe_pdesc), -+ &sc->sc_spalloc.dma_paddr); -+ if (!sc->sc_spalloc.dma_vaddr) { -+ device_printf(sc->sc_dev, "cannot allocate source particle descriptor ring\n"); -+ goto out; -+ } -+ sc->sc_spring = (struct safe_pdesc *) sc->sc_spalloc.dma_vaddr; -+ sc->sc_springtop = sc->sc_spring + SAFE_TOTAL_SPART; -+ sc->sc_spfree = sc->sc_spring; -+ bzero(sc->sc_spring, SAFE_TOTAL_SPART * sizeof(struct safe_pdesc)); -+ -+ sc->sc_dpalloc.dma_vaddr = pci_alloc_consistent(sc->sc_pcidev, -+ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), -+ &sc->sc_dpalloc.dma_paddr); -+ if (!sc->sc_dpalloc.dma_vaddr) { -+ device_printf(sc->sc_dev, "cannot allocate destination particle descriptor ring\n"); -+ goto out; -+ } -+ sc->sc_dpring = (struct safe_pdesc *) sc->sc_dpalloc.dma_vaddr; -+ sc->sc_dpringtop = sc->sc_dpring + SAFE_TOTAL_DPART; -+ sc->sc_dpfree = sc->sc_dpring; -+ bzero(sc->sc_dpring, SAFE_TOTAL_DPART * sizeof(struct safe_pdesc)); -+ -+ sc->sc_cid = crypto_get_driverid(softc_get_device(sc), CRYPTOCAP_F_HARDWARE); -+ if (sc->sc_cid < 0) { -+ device_printf(sc->sc_dev, "could not get crypto driver id\n"); -+ goto out; -+ } -+ -+ printf("%s:", device_get_nameunit(sc->sc_dev)); -+ -+ devinfo = READ_REG(sc, SAFE_DEVINFO); -+ if (devinfo & SAFE_DEVINFO_RNG) { -+ sc->sc_flags |= SAFE_FLAGS_RNG; -+ printf(" rng"); -+ } -+ if (devinfo & SAFE_DEVINFO_PKEY) { -+ printf(" key"); -+ sc->sc_flags |= SAFE_FLAGS_KEY; -+ crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0); -+#if 0 -+ crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0); -+#endif -+ init_timer(&sc->sc_pkto); -+ sc->sc_pkto.function = safe_kpoll; -+ sc->sc_pkto.data = (unsigned long) device_get_unit(sc->sc_dev); -+ } -+ if (devinfo & SAFE_DEVINFO_DES) { -+ printf(" des/3des"); -+ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); -+ } -+ if (devinfo & SAFE_DEVINFO_AES) { -+ printf(" aes"); -+ crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); -+ } -+ if (devinfo & SAFE_DEVINFO_MD5) { -+ printf(" md5"); -+ crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); -+ } -+ if (devinfo & SAFE_DEVINFO_SHA1) { -+ printf(" sha1"); -+ crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); -+ } -+ printf(" null"); -+ crypto_register(sc->sc_cid, CRYPTO_NULL_CBC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_NULL_HMAC, 0, 0); -+ /* XXX other supported algorithms */ -+ printf("\n"); -+ -+ safe_reset_board(sc); /* reset h/w */ -+ safe_init_board(sc); /* init h/w */ -+ -+#if defined(CONFIG_OCF_RANDOMHARVEST) && !defined(SAFE_NO_RNG) -+ if (sc->sc_flags & SAFE_FLAGS_RNG) { -+ safe_rng_init(sc); -+ crypto_rregister(sc->sc_cid, safe_read_random, sc); -+ } -+#endif /* SAFE_NO_RNG */ -+ -+ return (0); -+ -+out: -+ if (sc->sc_cid >= 0) -+ crypto_unregister_all(sc->sc_cid); -+ if (sc->sc_irq != -1) -+ free_irq(sc->sc_irq, sc); -+ if (sc->sc_ringalloc.dma_vaddr) -+ pci_free_consistent(sc->sc_pcidev, -+ SAFE_MAX_NQUEUE * sizeof (struct safe_ringentry), -+ sc->sc_ringalloc.dma_vaddr, sc->sc_ringalloc.dma_paddr); -+ if (sc->sc_spalloc.dma_vaddr) -+ pci_free_consistent(sc->sc_pcidev, -+ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), -+ sc->sc_spalloc.dma_vaddr, sc->sc_spalloc.dma_paddr); -+ if (sc->sc_dpalloc.dma_vaddr) -+ pci_free_consistent(sc->sc_pcidev, -+ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), -+ sc->sc_dpalloc.dma_vaddr, sc->sc_dpalloc.dma_paddr); -+ kfree(sc); -+ return(-ENODEV); -+} -+ -+static void safe_remove(struct pci_dev *dev) -+{ -+ struct safe_softc *sc = pci_get_drvdata(dev); -+ -+ DPRINTF(("%s()\n", __FUNCTION__)); -+ -+ /* XXX wait/abort active ops */ -+ -+ WRITE_REG(sc, SAFE_HI_MASK, 0); /* disable interrupts */ -+ -+ del_timer_sync(&sc->sc_pkto); -+ -+ crypto_unregister_all(sc->sc_cid); -+ -+ safe_cleanchip(sc); -+ -+ if (sc->sc_irq != -1) -+ free_irq(sc->sc_irq, sc); -+ if (sc->sc_ringalloc.dma_vaddr) -+ pci_free_consistent(sc->sc_pcidev, -+ SAFE_MAX_NQUEUE * sizeof (struct safe_ringentry), -+ sc->sc_ringalloc.dma_vaddr, sc->sc_ringalloc.dma_paddr); -+ if (sc->sc_spalloc.dma_vaddr) -+ pci_free_consistent(sc->sc_pcidev, -+ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), -+ sc->sc_spalloc.dma_vaddr, sc->sc_spalloc.dma_paddr); -+ if (sc->sc_dpalloc.dma_vaddr) -+ pci_free_consistent(sc->sc_pcidev, -+ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), -+ sc->sc_dpalloc.dma_vaddr, sc->sc_dpalloc.dma_paddr); -+ sc->sc_irq = -1; -+ sc->sc_ringalloc.dma_vaddr = NULL; -+ sc->sc_spalloc.dma_vaddr = NULL; -+ sc->sc_dpalloc.dma_vaddr = NULL; -+} -+ -+static struct pci_device_id safe_pci_tbl[] = { -+ { PCI_VENDOR_SAFENET, PCI_PRODUCT_SAFEXCEL, -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, -+ { }, -+}; -+MODULE_DEVICE_TABLE(pci, safe_pci_tbl); -+ -+static struct pci_driver safe_driver = { -+ .name = "safe", -+ .id_table = safe_pci_tbl, -+ .probe = safe_probe, -+ .remove = safe_remove, -+ /* add PM stuff here one day */ -+}; -+ -+static int __init safe_init (void) -+{ -+ struct safe_softc *sc = NULL; -+ int rc; -+ -+ DPRINTF(("%s(%p)\n", __FUNCTION__, safe_init)); -+ -+ rc = pci_register_driver(&safe_driver); -+ pci_register_driver_compat(&safe_driver, rc); -+ -+ return rc; -+} -+ -+static void __exit safe_exit (void) -+{ -+ pci_unregister_driver(&safe_driver); -+} -+ -+module_init(safe_init); -+module_exit(safe_exit); -+ -+MODULE_LICENSE("BSD"); -+MODULE_AUTHOR("David McCullough "); -+MODULE_DESCRIPTION("OCF driver for safenet PCI crypto devices"); -diff -Nur linux-3.0.4.orig/crypto/ocf/safe/safereg.h linux-3.0.4/crypto/ocf/safe/safereg.h ---- linux-3.0.4.orig/crypto/ocf/safe/safereg.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/safe/safereg.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,421 @@ -+/*- -+ * Copyright (c) 2003 Sam Leffler, Errno Consulting -+ * Copyright (c) 2003 Global Technology Associates, Inc. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ * -+ * $FreeBSD: src/sys/dev/safe/safereg.h,v 1.1 2003/07/21 21:46:07 sam Exp $ -+ */ -+#ifndef _SAFE_SAFEREG_H_ -+#define _SAFE_SAFEREG_H_ -+ -+/* -+ * Register definitions for SafeNet SafeXcel-1141 crypto device. -+ * Definitions from revision 1.3 (Nov 6 2002) of the User's Manual. -+ */ -+ -+#define BS_BAR 0x10 /* DMA base address register */ -+#define BS_TRDY_TIMEOUT 0x40 /* TRDY timeout */ -+#define BS_RETRY_TIMEOUT 0x41 /* DMA retry timeout */ -+ -+#define PCI_VENDOR_SAFENET 0x16ae /* SafeNet, Inc. */ -+ -+/* SafeNet */ -+#define PCI_PRODUCT_SAFEXCEL 0x1141 /* 1141 */ -+ -+#define SAFE_PE_CSR 0x0000 /* Packet Enginge Ctrl/Status */ -+#define SAFE_PE_SRC 0x0004 /* Packet Engine Source */ -+#define SAFE_PE_DST 0x0008 /* Packet Engine Destination */ -+#define SAFE_PE_SA 0x000c /* Packet Engine SA */ -+#define SAFE_PE_LEN 0x0010 /* Packet Engine Length */ -+#define SAFE_PE_DMACFG 0x0040 /* Packet Engine DMA Configuration */ -+#define SAFE_PE_DMASTAT 0x0044 /* Packet Engine DMA Status */ -+#define SAFE_PE_PDRBASE 0x0048 /* Packet Engine Descriptor Ring Base */ -+#define SAFE_PE_RDRBASE 0x004c /* Packet Engine Result Ring Base */ -+#define SAFE_PE_RINGCFG 0x0050 /* Packet Engine Ring Configuration */ -+#define SAFE_PE_RINGPOLL 0x0054 /* Packet Engine Ring Poll */ -+#define SAFE_PE_IRNGSTAT 0x0058 /* Packet Engine Internal Ring Status */ -+#define SAFE_PE_ERNGSTAT 0x005c /* Packet Engine External Ring Status */ -+#define SAFE_PE_IOTHRESH 0x0060 /* Packet Engine I/O Threshold */ -+#define SAFE_PE_GRNGBASE 0x0064 /* Packet Engine Gather Ring Base */ -+#define SAFE_PE_SRNGBASE 0x0068 /* Packet Engine Scatter Ring Base */ -+#define SAFE_PE_PARTSIZE 0x006c /* Packet Engine Particlar Ring Size */ -+#define SAFE_PE_PARTCFG 0x0070 /* Packet Engine Particle Ring Config */ -+#define SAFE_CRYPTO_CTRL 0x0080 /* Crypto Control */ -+#define SAFE_DEVID 0x0084 /* Device ID */ -+#define SAFE_DEVINFO 0x0088 /* Device Info */ -+#define SAFE_HU_STAT 0x00a0 /* Host Unmasked Status */ -+#define SAFE_HM_STAT 0x00a4 /* Host Masked Status (read-only) */ -+#define SAFE_HI_CLR 0x00a4 /* Host Clear Interrupt (write-only) */ -+#define SAFE_HI_MASK 0x00a8 /* Host Mask Control */ -+#define SAFE_HI_CFG 0x00ac /* Interrupt Configuration */ -+#define SAFE_HI_RD_DESCR 0x00b4 /* Force Descriptor Read */ -+#define SAFE_HI_DESC_CNT 0x00b8 /* Host Descriptor Done Count */ -+#define SAFE_DMA_ENDIAN 0x00c0 /* Master Endian Status */ -+#define SAFE_DMA_SRCADDR 0x00c4 /* DMA Source Address Status */ -+#define SAFE_DMA_DSTADDR 0x00c8 /* DMA Destination Address Status */ -+#define SAFE_DMA_STAT 0x00cc /* DMA Current Status */ -+#define SAFE_DMA_CFG 0x00d4 /* DMA Configuration/Status */ -+#define SAFE_ENDIAN 0x00e0 /* Endian Configuration */ -+#define SAFE_PK_A_ADDR 0x0800 /* Public Key A Address */ -+#define SAFE_PK_B_ADDR 0x0804 /* Public Key B Address */ -+#define SAFE_PK_C_ADDR 0x0808 /* Public Key C Address */ -+#define SAFE_PK_D_ADDR 0x080c /* Public Key D Address */ -+#define SAFE_PK_A_LEN 0x0810 /* Public Key A Length */ -+#define SAFE_PK_B_LEN 0x0814 /* Public Key B Length */ -+#define SAFE_PK_SHIFT 0x0818 /* Public Key Shift */ -+#define SAFE_PK_FUNC 0x081c /* Public Key Function */ -+#define SAFE_PK_RAM_START 0x1000 /* Public Key RAM start address */ -+#define SAFE_PK_RAM_END 0x1fff /* Public Key RAM end address */ -+ -+#define SAFE_RNG_OUT 0x0100 /* RNG Output */ -+#define SAFE_RNG_STAT 0x0104 /* RNG Status */ -+#define SAFE_RNG_CTRL 0x0108 /* RNG Control */ -+#define SAFE_RNG_A 0x010c /* RNG A */ -+#define SAFE_RNG_B 0x0110 /* RNG B */ -+#define SAFE_RNG_X_LO 0x0114 /* RNG X [31:0] */ -+#define SAFE_RNG_X_MID 0x0118 /* RNG X [63:32] */ -+#define SAFE_RNG_X_HI 0x011c /* RNG X [80:64] */ -+#define SAFE_RNG_X_CNTR 0x0120 /* RNG Counter */ -+#define SAFE_RNG_ALM_CNT 0x0124 /* RNG Alarm Count */ -+#define SAFE_RNG_CNFG 0x0128 /* RNG Configuration */ -+#define SAFE_RNG_LFSR1_LO 0x012c /* RNG LFSR1 [31:0] */ -+#define SAFE_RNG_LFSR1_HI 0x0130 /* RNG LFSR1 [47:32] */ -+#define SAFE_RNG_LFSR2_LO 0x0134 /* RNG LFSR1 [31:0] */ -+#define SAFE_RNG_LFSR2_HI 0x0138 /* RNG LFSR1 [47:32] */ -+ -+#define SAFE_PE_CSR_READY 0x00000001 /* ready for processing */ -+#define SAFE_PE_CSR_DONE 0x00000002 /* h/w completed processing */ -+#define SAFE_PE_CSR_LOADSA 0x00000004 /* load SA digests */ -+#define SAFE_PE_CSR_HASHFINAL 0x00000010 /* do hash pad & write result */ -+#define SAFE_PE_CSR_SABUSID 0x000000c0 /* bus id for SA */ -+#define SAFE_PE_CSR_SAPCI 0x00000040 /* PCI bus id for SA */ -+#define SAFE_PE_CSR_NXTHDR 0x0000ff00 /* next hdr value for IPsec */ -+#define SAFE_PE_CSR_FPAD 0x0000ff00 /* fixed pad for basic ops */ -+#define SAFE_PE_CSR_STATUS 0x00ff0000 /* operation result status */ -+#define SAFE_PE_CSR_AUTH_FAIL 0x00010000 /* ICV mismatch (inbound) */ -+#define SAFE_PE_CSR_PAD_FAIL 0x00020000 /* pad verify fail (inbound) */ -+#define SAFE_PE_CSR_SEQ_FAIL 0x00040000 /* sequence number (inbound) */ -+#define SAFE_PE_CSR_XERROR 0x00080000 /* extended error follows */ -+#define SAFE_PE_CSR_XECODE 0x00f00000 /* extended error code */ -+#define SAFE_PE_CSR_XECODE_S 20 -+#define SAFE_PE_CSR_XECODE_BADCMD 0 /* invalid command */ -+#define SAFE_PE_CSR_XECODE_BADALG 1 /* invalid algorithm */ -+#define SAFE_PE_CSR_XECODE_ALGDIS 2 /* algorithm disabled */ -+#define SAFE_PE_CSR_XECODE_ZEROLEN 3 /* zero packet length */ -+#define SAFE_PE_CSR_XECODE_DMAERR 4 /* bus DMA error */ -+#define SAFE_PE_CSR_XECODE_PIPEABORT 5 /* secondary bus DMA error */ -+#define SAFE_PE_CSR_XECODE_BADSPI 6 /* IPsec SPI mismatch */ -+#define SAFE_PE_CSR_XECODE_TIMEOUT 10 /* failsafe timeout */ -+#define SAFE_PE_CSR_PAD 0xff000000 /* ESP padding control/status */ -+#define SAFE_PE_CSR_PAD_MIN 0x00000000 /* minimum IPsec padding */ -+#define SAFE_PE_CSR_PAD_16 0x08000000 /* pad to 16-byte boundary */ -+#define SAFE_PE_CSR_PAD_32 0x10000000 /* pad to 32-byte boundary */ -+#define SAFE_PE_CSR_PAD_64 0x20000000 /* pad to 64-byte boundary */ -+#define SAFE_PE_CSR_PAD_128 0x40000000 /* pad to 128-byte boundary */ -+#define SAFE_PE_CSR_PAD_256 0x80000000 /* pad to 256-byte boundary */ -+ -+/* -+ * Check the CSR to see if the PE has returned ownership to -+ * the host. Note that before processing a descriptor this -+ * must be done followed by a check of the SAFE_PE_LEN register -+ * status bits to avoid premature processing of a descriptor -+ * on its way back to the host. -+ */ -+#define SAFE_PE_CSR_IS_DONE(_csr) \ -+ (((_csr) & (SAFE_PE_CSR_READY | SAFE_PE_CSR_DONE)) == SAFE_PE_CSR_DONE) -+ -+#define SAFE_PE_LEN_LENGTH 0x000fffff /* total length (bytes) */ -+#define SAFE_PE_LEN_READY 0x00400000 /* ready for processing */ -+#define SAFE_PE_LEN_DONE 0x00800000 /* h/w completed processing */ -+#define SAFE_PE_LEN_BYPASS 0xff000000 /* bypass offset (bytes) */ -+#define SAFE_PE_LEN_BYPASS_S 24 -+ -+#define SAFE_PE_LEN_IS_DONE(_len) \ -+ (((_len) & (SAFE_PE_LEN_READY | SAFE_PE_LEN_DONE)) == SAFE_PE_LEN_DONE) -+ -+/* NB: these apply to HU_STAT, HM_STAT, HI_CLR, and HI_MASK */ -+#define SAFE_INT_PE_CDONE 0x00000002 /* PE context done */ -+#define SAFE_INT_PE_DDONE 0x00000008 /* PE descriptor done */ -+#define SAFE_INT_PE_ERROR 0x00000010 /* PE error */ -+#define SAFE_INT_PE_ODONE 0x00000020 /* PE operation done */ -+ -+#define SAFE_HI_CFG_PULSE 0x00000001 /* use pulse interrupt */ -+#define SAFE_HI_CFG_LEVEL 0x00000000 /* use level interrupt */ -+#define SAFE_HI_CFG_AUTOCLR 0x00000002 /* auto-clear pulse interrupt */ -+ -+#define SAFE_ENDIAN_PASS 0x000000e4 /* straight pass-thru */ -+#define SAFE_ENDIAN_SWAB 0x0000001b /* swap bytes in 32-bit word */ -+ -+#define SAFE_PE_DMACFG_PERESET 0x00000001 /* reset packet engine */ -+#define SAFE_PE_DMACFG_PDRRESET 0x00000002 /* reset PDR counters/ptrs */ -+#define SAFE_PE_DMACFG_SGRESET 0x00000004 /* reset scatter/gather cache */ -+#define SAFE_PE_DMACFG_FSENA 0x00000008 /* enable failsafe reset */ -+#define SAFE_PE_DMACFG_PEMODE 0x00000100 /* packet engine mode */ -+#define SAFE_PE_DMACFG_SAPREC 0x00000200 /* SA precedes packet */ -+#define SAFE_PE_DMACFG_PKFOLL 0x00000400 /* packet follows descriptor */ -+#define SAFE_PE_DMACFG_GPRBID 0x00003000 /* gather particle ring busid */ -+#define SAFE_PE_DMACFG_GPRPCI 0x00001000 /* PCI gather particle ring */ -+#define SAFE_PE_DMACFG_SPRBID 0x0000c000 /* scatter part. ring busid */ -+#define SAFE_PE_DMACFG_SPRPCI 0x00004000 /* PCI scatter part. ring */ -+#define SAFE_PE_DMACFG_ESDESC 0x00010000 /* endian swap descriptors */ -+#define SAFE_PE_DMACFG_ESSA 0x00020000 /* endian swap SA data */ -+#define SAFE_PE_DMACFG_ESPACKET 0x00040000 /* endian swap packet data */ -+#define SAFE_PE_DMACFG_ESPDESC 0x00080000 /* endian swap particle desc. */ -+#define SAFE_PE_DMACFG_NOPDRUP 0x00100000 /* supp. PDR ownership update */ -+#define SAFE_PD_EDMACFG_PCIMODE 0x01000000 /* PCI target mode */ -+ -+#define SAFE_PE_DMASTAT_PEIDONE 0x00000001 /* PE core input done */ -+#define SAFE_PE_DMASTAT_PEODONE 0x00000002 /* PE core output done */ -+#define SAFE_PE_DMASTAT_ENCDONE 0x00000004 /* encryption done */ -+#define SAFE_PE_DMASTAT_IHDONE 0x00000008 /* inner hash done */ -+#define SAFE_PE_DMASTAT_OHDONE 0x00000010 /* outer hash (HMAC) done */ -+#define SAFE_PE_DMASTAT_PADFLT 0x00000020 /* crypto pad fault */ -+#define SAFE_PE_DMASTAT_ICVFLT 0x00000040 /* ICV fault */ -+#define SAFE_PE_DMASTAT_SPIMIS 0x00000080 /* SPI mismatch */ -+#define SAFE_PE_DMASTAT_CRYPTO 0x00000100 /* crypto engine timeout */ -+#define SAFE_PE_DMASTAT_CQACT 0x00000200 /* command queue active */ -+#define SAFE_PE_DMASTAT_IRACT 0x00000400 /* input request active */ -+#define SAFE_PE_DMASTAT_ORACT 0x00000800 /* output request active */ -+#define SAFE_PE_DMASTAT_PEISIZE 0x003ff000 /* PE input size:32-bit words */ -+#define SAFE_PE_DMASTAT_PEOSIZE 0xffc00000 /* PE out. size:32-bit words */ -+ -+#define SAFE_PE_RINGCFG_SIZE 0x000003ff /* ring size (descriptors) */ -+#define SAFE_PE_RINGCFG_OFFSET 0xffff0000 /* offset btw desc's (dwords) */ -+#define SAFE_PE_RINGCFG_OFFSET_S 16 -+ -+#define SAFE_PE_RINGPOLL_POLL 0x00000fff /* polling frequency/divisor */ -+#define SAFE_PE_RINGPOLL_RETRY 0x03ff0000 /* polling frequency/divisor */ -+#define SAFE_PE_RINGPOLL_CONT 0x80000000 /* continuously poll */ -+ -+#define SAFE_PE_IRNGSTAT_CQAVAIL 0x00000001 /* command queue available */ -+ -+#define SAFE_PE_ERNGSTAT_NEXT 0x03ff0000 /* index of next packet desc. */ -+#define SAFE_PE_ERNGSTAT_NEXT_S 16 -+ -+#define SAFE_PE_IOTHRESH_INPUT 0x000003ff /* input threshold (dwords) */ -+#define SAFE_PE_IOTHRESH_OUTPUT 0x03ff0000 /* output threshold (dwords) */ -+ -+#define SAFE_PE_PARTCFG_SIZE 0x0000ffff /* scatter particle size */ -+#define SAFE_PE_PARTCFG_GBURST 0x00030000 /* gather particle burst */ -+#define SAFE_PE_PARTCFG_GBURST_2 0x00000000 -+#define SAFE_PE_PARTCFG_GBURST_4 0x00010000 -+#define SAFE_PE_PARTCFG_GBURST_8 0x00020000 -+#define SAFE_PE_PARTCFG_GBURST_16 0x00030000 -+#define SAFE_PE_PARTCFG_SBURST 0x000c0000 /* scatter particle burst */ -+#define SAFE_PE_PARTCFG_SBURST_2 0x00000000 -+#define SAFE_PE_PARTCFG_SBURST_4 0x00040000 -+#define SAFE_PE_PARTCFG_SBURST_8 0x00080000 -+#define SAFE_PE_PARTCFG_SBURST_16 0x000c0000 -+ -+#define SAFE_PE_PARTSIZE_SCAT 0xffff0000 /* scatter particle ring size */ -+#define SAFE_PE_PARTSIZE_GATH 0x0000ffff /* gather particle ring size */ -+ -+#define SAFE_CRYPTO_CTRL_3DES 0x00000001 /* enable 3DES support */ -+#define SAFE_CRYPTO_CTRL_PKEY 0x00010000 /* enable public key support */ -+#define SAFE_CRYPTO_CTRL_RNG 0x00020000 /* enable RNG support */ -+ -+#define SAFE_DEVINFO_REV_MIN 0x0000000f /* minor rev for chip */ -+#define SAFE_DEVINFO_REV_MAJ 0x000000f0 /* major rev for chip */ -+#define SAFE_DEVINFO_REV_MAJ_S 4 -+#define SAFE_DEVINFO_DES 0x00000100 /* DES/3DES support present */ -+#define SAFE_DEVINFO_ARC4 0x00000200 /* ARC4 support present */ -+#define SAFE_DEVINFO_AES 0x00000400 /* AES support present */ -+#define SAFE_DEVINFO_MD5 0x00001000 /* MD5 support present */ -+#define SAFE_DEVINFO_SHA1 0x00002000 /* SHA-1 support present */ -+#define SAFE_DEVINFO_RIPEMD 0x00004000 /* RIPEMD support present */ -+#define SAFE_DEVINFO_DEFLATE 0x00010000 /* Deflate support present */ -+#define SAFE_DEVINFO_SARAM 0x00100000 /* on-chip SA RAM present */ -+#define SAFE_DEVINFO_EMIBUS 0x00200000 /* EMI bus present */ -+#define SAFE_DEVINFO_PKEY 0x00400000 /* public key support present */ -+#define SAFE_DEVINFO_RNG 0x00800000 /* RNG present */ -+ -+#define SAFE_REV(_maj, _min) (((_maj) << SAFE_DEVINFO_REV_MAJ_S) | (_min)) -+#define SAFE_REV_MAJ(_chiprev) \ -+ (((_chiprev) & SAFE_DEVINFO_REV_MAJ) >> SAFE_DEVINFO_REV_MAJ_S) -+#define SAFE_REV_MIN(_chiprev) ((_chiprev) & SAFE_DEVINFO_REV_MIN) -+ -+#define SAFE_PK_FUNC_MULT 0x00000001 /* Multiply function */ -+#define SAFE_PK_FUNC_SQUARE 0x00000004 /* Square function */ -+#define SAFE_PK_FUNC_ADD 0x00000010 /* Add function */ -+#define SAFE_PK_FUNC_SUB 0x00000020 /* Subtract function */ -+#define SAFE_PK_FUNC_LSHIFT 0x00000040 /* Left-shift function */ -+#define SAFE_PK_FUNC_RSHIFT 0x00000080 /* Right-shift function */ -+#define SAFE_PK_FUNC_DIV 0x00000100 /* Divide function */ -+#define SAFE_PK_FUNC_CMP 0x00000400 /* Compare function */ -+#define SAFE_PK_FUNC_COPY 0x00000800 /* Copy function */ -+#define SAFE_PK_FUNC_EXP16 0x00002000 /* Exponentiate (4-bit ACT) */ -+#define SAFE_PK_FUNC_EXP4 0x00004000 /* Exponentiate (2-bit ACT) */ -+#define SAFE_PK_FUNC_RUN 0x00008000 /* start/status */ -+ -+#define SAFE_RNG_STAT_BUSY 0x00000001 /* busy, data not valid */ -+ -+#define SAFE_RNG_CTRL_PRE_LFSR 0x00000001 /* enable output pre-LFSR */ -+#define SAFE_RNG_CTRL_TST_MODE 0x00000002 /* enable test mode */ -+#define SAFE_RNG_CTRL_TST_RUN 0x00000004 /* start test state machine */ -+#define SAFE_RNG_CTRL_ENA_RING1 0x00000008 /* test entropy oscillator #1 */ -+#define SAFE_RNG_CTRL_ENA_RING2 0x00000010 /* test entropy oscillator #2 */ -+#define SAFE_RNG_CTRL_DIS_ALARM 0x00000020 /* disable RNG alarm reports */ -+#define SAFE_RNG_CTRL_TST_CLOCK 0x00000040 /* enable test clock */ -+#define SAFE_RNG_CTRL_SHORTEN 0x00000080 /* shorten state timers */ -+#define SAFE_RNG_CTRL_TST_ALARM 0x00000100 /* simulate alarm state */ -+#define SAFE_RNG_CTRL_RST_LFSR 0x00000200 /* reset LFSR */ -+ -+/* -+ * Packet engine descriptor. Note that d_csr is a copy of the -+ * SAFE_PE_CSR register and all definitions apply, and d_len -+ * is a copy of the SAFE_PE_LEN register and all definitions apply. -+ * d_src and d_len may point directly to contiguous data or to a -+ * list of ``particle descriptors'' when using scatter/gather i/o. -+ */ -+struct safe_desc { -+ u_int32_t d_csr; /* per-packet control/status */ -+ u_int32_t d_src; /* source address */ -+ u_int32_t d_dst; /* destination address */ -+ u_int32_t d_sa; /* SA address */ -+ u_int32_t d_len; /* length, bypass, status */ -+}; -+ -+/* -+ * Scatter/Gather particle descriptor. -+ * -+ * NB: scatter descriptors do not specify a size; this is fixed -+ * by the setting of the SAFE_PE_PARTCFG register. -+ */ -+struct safe_pdesc { -+ u_int32_t pd_addr; /* particle address */ -+#ifdef __BIG_ENDIAN -+ u_int16_t pd_flags; /* control word */ -+ u_int16_t pd_size; /* particle size (bytes) */ -+#else -+ u_int16_t pd_flags; /* control word */ -+ u_int16_t pd_size; /* particle size (bytes) */ -+#endif -+}; -+ -+#define SAFE_PD_READY 0x0001 /* ready for processing */ -+#define SAFE_PD_DONE 0x0002 /* h/w completed processing */ -+ -+/* -+ * Security Association (SA) Record (Rev 1). One of these is -+ * required for each operation processed by the packet engine. -+ */ -+struct safe_sarec { -+ u_int32_t sa_cmd0; -+ u_int32_t sa_cmd1; -+ u_int32_t sa_resv0; -+ u_int32_t sa_resv1; -+ u_int32_t sa_key[8]; /* DES/3DES/AES key */ -+ u_int32_t sa_indigest[5]; /* inner digest */ -+ u_int32_t sa_outdigest[5]; /* outer digest */ -+ u_int32_t sa_spi; /* SPI */ -+ u_int32_t sa_seqnum; /* sequence number */ -+ u_int32_t sa_seqmask[2]; /* sequence number mask */ -+ u_int32_t sa_resv2; -+ u_int32_t sa_staterec; /* address of state record */ -+ u_int32_t sa_resv3[2]; -+ u_int32_t sa_samgmt0; /* SA management field 0 */ -+ u_int32_t sa_samgmt1; /* SA management field 0 */ -+}; -+ -+#define SAFE_SA_CMD0_OP 0x00000007 /* operation code */ -+#define SAFE_SA_CMD0_OP_CRYPT 0x00000000 /* encrypt/decrypt (basic) */ -+#define SAFE_SA_CMD0_OP_BOTH 0x00000001 /* encrypt-hash/hash-decrypto */ -+#define SAFE_SA_CMD0_OP_HASH 0x00000003 /* hash (outbound-only) */ -+#define SAFE_SA_CMD0_OP_ESP 0x00000000 /* ESP in/out (proto) */ -+#define SAFE_SA_CMD0_OP_AH 0x00000001 /* AH in/out (proto) */ -+#define SAFE_SA_CMD0_INBOUND 0x00000008 /* inbound operation */ -+#define SAFE_SA_CMD0_OUTBOUND 0x00000000 /* outbound operation */ -+#define SAFE_SA_CMD0_GROUP 0x00000030 /* operation group */ -+#define SAFE_SA_CMD0_BASIC 0x00000000 /* basic operation */ -+#define SAFE_SA_CMD0_PROTO 0x00000010 /* protocol/packet operation */ -+#define SAFE_SA_CMD0_BUNDLE 0x00000020 /* bundled operation (resvd) */ -+#define SAFE_SA_CMD0_PAD 0x000000c0 /* crypto pad method */ -+#define SAFE_SA_CMD0_PAD_IPSEC 0x00000000 /* IPsec padding */ -+#define SAFE_SA_CMD0_PAD_PKCS7 0x00000040 /* PKCS#7 padding */ -+#define SAFE_SA_CMD0_PAD_CONS 0x00000080 /* constant padding */ -+#define SAFE_SA_CMD0_PAD_ZERO 0x000000c0 /* zero padding */ -+#define SAFE_SA_CMD0_CRYPT_ALG 0x00000f00 /* symmetric crypto algorithm */ -+#define SAFE_SA_CMD0_DES 0x00000000 /* DES crypto algorithm */ -+#define SAFE_SA_CMD0_3DES 0x00000100 /* 3DES crypto algorithm */ -+#define SAFE_SA_CMD0_AES 0x00000300 /* AES crypto algorithm */ -+#define SAFE_SA_CMD0_CRYPT_NULL 0x00000f00 /* null crypto algorithm */ -+#define SAFE_SA_CMD0_HASH_ALG 0x0000f000 /* hash algorithm */ -+#define SAFE_SA_CMD0_MD5 0x00000000 /* MD5 hash algorithm */ -+#define SAFE_SA_CMD0_SHA1 0x00001000 /* SHA-1 hash algorithm */ -+#define SAFE_SA_CMD0_HASH_NULL 0x0000f000 /* null hash algorithm */ -+#define SAFE_SA_CMD0_HDR_PROC 0x00080000 /* header processing */ -+#define SAFE_SA_CMD0_IBUSID 0x00300000 /* input bus id */ -+#define SAFE_SA_CMD0_IPCI 0x00100000 /* PCI input bus id */ -+#define SAFE_SA_CMD0_OBUSID 0x00c00000 /* output bus id */ -+#define SAFE_SA_CMD0_OPCI 0x00400000 /* PCI output bus id */ -+#define SAFE_SA_CMD0_IVLD 0x03000000 /* IV loading */ -+#define SAFE_SA_CMD0_IVLD_NONE 0x00000000 /* IV no load (reuse) */ -+#define SAFE_SA_CMD0_IVLD_IBUF 0x01000000 /* IV load from input buffer */ -+#define SAFE_SA_CMD0_IVLD_STATE 0x02000000 /* IV load from state */ -+#define SAFE_SA_CMD0_HSLD 0x0c000000 /* hash state loading */ -+#define SAFE_SA_CMD0_HSLD_SA 0x00000000 /* hash state load from SA */ -+#define SAFE_SA_CMD0_HSLD_STATE 0x08000000 /* hash state load from state */ -+#define SAFE_SA_CMD0_HSLD_NONE 0x0c000000 /* hash state no load */ -+#define SAFE_SA_CMD0_SAVEIV 0x10000000 /* save IV */ -+#define SAFE_SA_CMD0_SAVEHASH 0x20000000 /* save hash state */ -+#define SAFE_SA_CMD0_IGATHER 0x40000000 /* input gather */ -+#define SAFE_SA_CMD0_OSCATTER 0x80000000 /* output scatter */ -+ -+#define SAFE_SA_CMD1_HDRCOPY 0x00000002 /* copy header to output */ -+#define SAFE_SA_CMD1_PAYCOPY 0x00000004 /* copy payload to output */ -+#define SAFE_SA_CMD1_PADCOPY 0x00000008 /* copy pad to output */ -+#define SAFE_SA_CMD1_IPV4 0x00000000 /* IPv4 protocol */ -+#define SAFE_SA_CMD1_IPV6 0x00000010 /* IPv6 protocol */ -+#define SAFE_SA_CMD1_MUTABLE 0x00000020 /* mutable bit processing */ -+#define SAFE_SA_CMD1_SRBUSID 0x000000c0 /* state record bus id */ -+#define SAFE_SA_CMD1_SRPCI 0x00000040 /* state record from PCI */ -+#define SAFE_SA_CMD1_CRMODE 0x00000300 /* crypto mode */ -+#define SAFE_SA_CMD1_ECB 0x00000000 /* ECB crypto mode */ -+#define SAFE_SA_CMD1_CBC 0x00000100 /* CBC crypto mode */ -+#define SAFE_SA_CMD1_OFB 0x00000200 /* OFB crypto mode */ -+#define SAFE_SA_CMD1_CFB 0x00000300 /* CFB crypto mode */ -+#define SAFE_SA_CMD1_CRFEEDBACK 0x00000c00 /* crypto feedback mode */ -+#define SAFE_SA_CMD1_64BIT 0x00000000 /* 64-bit crypto feedback */ -+#define SAFE_SA_CMD1_8BIT 0x00000400 /* 8-bit crypto feedback */ -+#define SAFE_SA_CMD1_1BIT 0x00000800 /* 1-bit crypto feedback */ -+#define SAFE_SA_CMD1_128BIT 0x00000c00 /* 128-bit crypto feedback */ -+#define SAFE_SA_CMD1_OPTIONS 0x00001000 /* HMAC/options mutable bit */ -+#define SAFE_SA_CMD1_HMAC SAFE_SA_CMD1_OPTIONS -+#define SAFE_SA_CMD1_SAREV1 0x00008000 /* SA Revision 1 */ -+#define SAFE_SA_CMD1_OFFSET 0x00ff0000 /* hash/crypto offset(dwords) */ -+#define SAFE_SA_CMD1_OFFSET_S 16 -+#define SAFE_SA_CMD1_AESKEYLEN 0x0f000000 /* AES key length */ -+#define SAFE_SA_CMD1_AES128 0x02000000 /* 128-bit AES key */ -+#define SAFE_SA_CMD1_AES192 0x03000000 /* 192-bit AES key */ -+#define SAFE_SA_CMD1_AES256 0x04000000 /* 256-bit AES key */ -+ -+/* -+ * Security Associate State Record (Rev 1). -+ */ -+struct safe_sastate { -+ u_int32_t sa_saved_iv[4]; /* saved IV (DES/3DES/AES) */ -+ u_int32_t sa_saved_hashbc; /* saved hash byte count */ -+ u_int32_t sa_saved_indigest[5]; /* saved inner digest */ -+}; -+#endif /* _SAFE_SAFEREG_H_ */ -diff -Nur linux-3.0.4.orig/crypto/ocf/safe/safevar.h linux-3.0.4/crypto/ocf/safe/safevar.h ---- linux-3.0.4.orig/crypto/ocf/safe/safevar.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/safe/safevar.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,229 @@ -+/*- -+ * The linux port of this code done by David McCullough -+ * Copyright (C) 2004-2010 David McCullough -+ * The license and original author are listed below. -+ * -+ * Copyright (c) 2003 Sam Leffler, Errno Consulting -+ * Copyright (c) 2003 Global Technology Associates, Inc. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ * -+ * $FreeBSD: src/sys/dev/safe/safevar.h,v 1.2 2006/05/17 18:34:26 pjd Exp $ -+ */ -+#ifndef _SAFE_SAFEVAR_H_ -+#define _SAFE_SAFEVAR_H_ -+ -+/* Maximum queue length */ -+#ifndef SAFE_MAX_NQUEUE -+#define SAFE_MAX_NQUEUE 60 -+#endif -+ -+#define SAFE_MAX_PART 64 /* Maximum scatter/gather depth */ -+#define SAFE_DMA_BOUNDARY 0 /* No boundary for source DMA ops */ -+#define SAFE_MAX_DSIZE 2048 /* MCLBYTES Fixed scatter particle size */ -+#define SAFE_MAX_SSIZE 0x0ffff /* Maximum gather particle size */ -+#define SAFE_MAX_DMA 0xfffff /* Maximum PE operand size (20 bits) */ -+/* total src+dst particle descriptors */ -+#define SAFE_TOTAL_DPART (SAFE_MAX_NQUEUE * SAFE_MAX_PART) -+#define SAFE_TOTAL_SPART (SAFE_MAX_NQUEUE * SAFE_MAX_PART) -+ -+#define SAFE_RNG_MAXBUFSIZ 128 /* 32-bit words */ -+ -+#define SAFE_CARD(sid) (((sid) & 0xf0000000) >> 28) -+#define SAFE_SESSION(sid) ( (sid) & 0x0fffffff) -+#define SAFE_SID(crd, sesn) (((crd) << 28) | ((sesn) & 0x0fffffff)) -+ -+#define SAFE_DEF_RTY 0xff /* PCI Retry Timeout */ -+#define SAFE_DEF_TOUT 0xff /* PCI TRDY Timeout */ -+#define SAFE_DEF_CACHELINE 0x01 /* Cache Line setting */ -+ -+#ifdef __KERNEL__ -+/* -+ * State associated with the allocation of each chunk -+ * of memory setup for DMA. -+ */ -+struct safe_dma_alloc { -+ dma_addr_t dma_paddr; -+ void *dma_vaddr; -+}; -+ -+/* -+ * Cryptographic operand state. One of these exists for each -+ * source and destination operand passed in from the crypto -+ * subsystem. When possible source and destination operands -+ * refer to the same memory. More often they are distinct. -+ * We track the virtual address of each operand as well as -+ * where each is mapped for DMA. -+ */ -+struct safe_operand { -+ union { -+ struct sk_buff *skb; -+ struct uio *io; -+ } u; -+ void *map; -+ int mapsize; /* total number of bytes in segs */ -+ struct { -+ dma_addr_t ds_addr; -+ int ds_len; -+ int ds_tlen; -+ } segs[SAFE_MAX_PART]; -+ int nsegs; -+}; -+ -+/* -+ * Packet engine ring entry and cryptographic operation state. -+ * The packet engine requires a ring of descriptors that contain -+ * pointers to various cryptographic state. However the ring -+ * configuration register allows you to specify an arbitrary size -+ * for ring entries. We use this feature to collect most of the -+ * state for each cryptographic request into one spot. Other than -+ * ring entries only the ``particle descriptors'' (scatter/gather -+ * lists) and the actual operand data are kept separate. The -+ * particle descriptors must also be organized in rings. The -+ * operand data can be located aribtrarily (modulo alignment constraints). -+ * -+ * Note that the descriptor ring is mapped onto the PCI bus so -+ * the hardware can DMA data. This means the entire ring must be -+ * contiguous. -+ */ -+struct safe_ringentry { -+ struct safe_desc re_desc; /* command descriptor */ -+ struct safe_sarec re_sa; /* SA record */ -+ struct safe_sastate re_sastate; /* SA state record */ -+ -+ struct cryptop *re_crp; /* crypto operation */ -+ -+ struct safe_operand re_src; /* source operand */ -+ struct safe_operand re_dst; /* destination operand */ -+ -+ int re_sesn; /* crypto session ID */ -+ int re_flags; -+#define SAFE_QFLAGS_COPYOUTIV 0x1 /* copy back on completion */ -+#define SAFE_QFLAGS_COPYOUTICV 0x2 /* copy back on completion */ -+}; -+ -+#define re_src_skb re_src.u.skb -+#define re_src_io re_src.u.io -+#define re_src_map re_src.map -+#define re_src_nsegs re_src.nsegs -+#define re_src_segs re_src.segs -+#define re_src_mapsize re_src.mapsize -+ -+#define re_dst_skb re_dst.u.skb -+#define re_dst_io re_dst.u.io -+#define re_dst_map re_dst.map -+#define re_dst_nsegs re_dst.nsegs -+#define re_dst_segs re_dst.segs -+#define re_dst_mapsize re_dst.mapsize -+ -+struct rndstate_test; -+ -+struct safe_session { -+ u_int32_t ses_used; -+ u_int32_t ses_klen; /* key length in bits */ -+ u_int32_t ses_key[8]; /* DES/3DES/AES key */ -+ u_int32_t ses_mlen; /* hmac length in bytes */ -+ u_int32_t ses_hminner[5]; /* hmac inner state */ -+ u_int32_t ses_hmouter[5]; /* hmac outer state */ -+}; -+ -+struct safe_pkq { -+ struct list_head pkq_list; -+ struct cryptkop *pkq_krp; -+}; -+ -+struct safe_softc { -+ softc_device_decl sc_dev; -+ u32 sc_irq; -+ -+ struct pci_dev *sc_pcidev; -+ ocf_iomem_t sc_base_addr; -+ -+ u_int sc_chiprev; /* major/minor chip revision */ -+ int sc_flags; /* device specific flags */ -+#define SAFE_FLAGS_KEY 0x01 /* has key accelerator */ -+#define SAFE_FLAGS_RNG 0x02 /* hardware rng */ -+ int sc_suspended; -+ int sc_needwakeup; /* notify crypto layer */ -+ int32_t sc_cid; /* crypto tag */ -+ -+ struct safe_dma_alloc sc_ringalloc; /* PE ring allocation state */ -+ struct safe_ringentry *sc_ring; /* PE ring */ -+ struct safe_ringentry *sc_ringtop; /* PE ring top */ -+ struct safe_ringentry *sc_front; /* next free entry */ -+ struct safe_ringentry *sc_back; /* next pending entry */ -+ int sc_nqchip; /* # passed to chip */ -+ spinlock_t sc_ringmtx; /* PE ring lock */ -+ struct safe_pdesc *sc_spring; /* src particle ring */ -+ struct safe_pdesc *sc_springtop; /* src particle ring top */ -+ struct safe_pdesc *sc_spfree; /* next free src particle */ -+ struct safe_dma_alloc sc_spalloc; /* src particle ring state */ -+ struct safe_pdesc *sc_dpring; /* dest particle ring */ -+ struct safe_pdesc *sc_dpringtop; /* dest particle ring top */ -+ struct safe_pdesc *sc_dpfree; /* next free dest particle */ -+ struct safe_dma_alloc sc_dpalloc; /* dst particle ring state */ -+ int sc_nsessions; /* # of sessions */ -+ struct safe_session *sc_sessions; /* sessions */ -+ -+ struct timer_list sc_pkto; /* PK polling */ -+ spinlock_t sc_pkmtx; /* PK lock */ -+ struct list_head sc_pkq; /* queue of PK requests */ -+ struct safe_pkq *sc_pkq_cur; /* current processing request */ -+ u_int32_t sc_pk_reslen, sc_pk_resoff; -+ -+ int sc_max_dsize; /* maximum safe DMA size */ -+}; -+#endif /* __KERNEL__ */ -+ -+struct safe_stats { -+ u_int64_t st_ibytes; -+ u_int64_t st_obytes; -+ u_int32_t st_ipackets; -+ u_int32_t st_opackets; -+ u_int32_t st_invalid; /* invalid argument */ -+ u_int32_t st_badsession; /* invalid session id */ -+ u_int32_t st_badflags; /* flags indicate !(mbuf | uio) */ -+ u_int32_t st_nodesc; /* op submitted w/o descriptors */ -+ u_int32_t st_badalg; /* unsupported algorithm */ -+ u_int32_t st_ringfull; /* PE descriptor ring full */ -+ u_int32_t st_peoperr; /* PE marked error */ -+ u_int32_t st_dmaerr; /* PE DMA error */ -+ u_int32_t st_bypasstoobig; /* bypass > 96 bytes */ -+ u_int32_t st_skipmismatch; /* enc part begins before auth part */ -+ u_int32_t st_lenmismatch; /* enc length different auth length */ -+ u_int32_t st_coffmisaligned; /* crypto offset not 32-bit aligned */ -+ u_int32_t st_cofftoobig; /* crypto offset > 255 words */ -+ u_int32_t st_iovmisaligned; /* iov op not aligned */ -+ u_int32_t st_iovnotuniform; /* iov op not suitable */ -+ u_int32_t st_unaligned; /* unaligned src caused copy */ -+ u_int32_t st_notuniform; /* non-uniform src caused copy */ -+ u_int32_t st_nomap; /* bus_dmamap_create failed */ -+ u_int32_t st_noload; /* bus_dmamap_load_* failed */ -+ u_int32_t st_nombuf; /* MGET* failed */ -+ u_int32_t st_nomcl; /* MCLGET* failed */ -+ u_int32_t st_maxqchip; /* max mcr1 ops out for processing */ -+ u_int32_t st_rng; /* RNG requests */ -+ u_int32_t st_rngalarm; /* RNG alarm requests */ -+ u_int32_t st_noicvcopy; /* ICV data copies suppressed */ -+}; -+#endif /* _SAFE_SAFEVAR_H_ */ -diff -Nur linux-3.0.4.orig/crypto/ocf/safe/sha1.c linux-3.0.4/crypto/ocf/safe/sha1.c ---- linux-3.0.4.orig/crypto/ocf/safe/sha1.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/safe/sha1.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,279 @@ -+/* $KAME: sha1.c,v 1.5 2000/11/08 06:13:08 itojun Exp $ */ -+/* -+ * Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. Neither the name of the project nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ */ -+ -+/* -+ * FIPS pub 180-1: Secure Hash Algorithm (SHA-1) -+ * based on: http://csrc.nist.gov/fips/fip180-1.txt -+ * implemented by Jun-ichiro itojun Itoh -+ */ -+ -+#if 0 -+#include -+__FBSDID("$FreeBSD: src/sys/crypto/sha1.c,v 1.9 2003/06/10 21:36:57 obrien Exp $"); -+ -+#include -+#include -+#include -+#include -+ -+#include -+#endif -+ -+/* sanity check */ -+#if BYTE_ORDER != BIG_ENDIAN -+# if BYTE_ORDER != LITTLE_ENDIAN -+# define unsupported 1 -+# endif -+#endif -+ -+#ifndef unsupported -+ -+/* constant table */ -+static u_int32_t _K[] = { 0x5a827999, 0x6ed9eba1, 0x8f1bbcdc, 0xca62c1d6 }; -+#define K(t) _K[(t) / 20] -+ -+#define F0(b, c, d) (((b) & (c)) | ((~(b)) & (d))) -+#define F1(b, c, d) (((b) ^ (c)) ^ (d)) -+#define F2(b, c, d) (((b) & (c)) | ((b) & (d)) | ((c) & (d))) -+#define F3(b, c, d) (((b) ^ (c)) ^ (d)) -+ -+#define S(n, x) (((x) << (n)) | ((x) >> (32 - n))) -+ -+#undef H -+#define H(n) (ctxt->h.b32[(n)]) -+#define COUNT (ctxt->count) -+#define BCOUNT (ctxt->c.b64[0] / 8) -+#define W(n) (ctxt->m.b32[(n)]) -+ -+#define PUTBYTE(x) { \ -+ ctxt->m.b8[(COUNT % 64)] = (x); \ -+ COUNT++; \ -+ COUNT %= 64; \ -+ ctxt->c.b64[0] += 8; \ -+ if (COUNT % 64 == 0) \ -+ sha1_step(ctxt); \ -+ } -+ -+#define PUTPAD(x) { \ -+ ctxt->m.b8[(COUNT % 64)] = (x); \ -+ COUNT++; \ -+ COUNT %= 64; \ -+ if (COUNT % 64 == 0) \ -+ sha1_step(ctxt); \ -+ } -+ -+static void sha1_step(struct sha1_ctxt *); -+ -+static void -+sha1_step(ctxt) -+ struct sha1_ctxt *ctxt; -+{ -+ u_int32_t a, b, c, d, e; -+ size_t t, s; -+ u_int32_t tmp; -+ -+#if BYTE_ORDER == LITTLE_ENDIAN -+ struct sha1_ctxt tctxt; -+ bcopy(&ctxt->m.b8[0], &tctxt.m.b8[0], 64); -+ ctxt->m.b8[0] = tctxt.m.b8[3]; ctxt->m.b8[1] = tctxt.m.b8[2]; -+ ctxt->m.b8[2] = tctxt.m.b8[1]; ctxt->m.b8[3] = tctxt.m.b8[0]; -+ ctxt->m.b8[4] = tctxt.m.b8[7]; ctxt->m.b8[5] = tctxt.m.b8[6]; -+ ctxt->m.b8[6] = tctxt.m.b8[5]; ctxt->m.b8[7] = tctxt.m.b8[4]; -+ ctxt->m.b8[8] = tctxt.m.b8[11]; ctxt->m.b8[9] = tctxt.m.b8[10]; -+ ctxt->m.b8[10] = tctxt.m.b8[9]; ctxt->m.b8[11] = tctxt.m.b8[8]; -+ ctxt->m.b8[12] = tctxt.m.b8[15]; ctxt->m.b8[13] = tctxt.m.b8[14]; -+ ctxt->m.b8[14] = tctxt.m.b8[13]; ctxt->m.b8[15] = tctxt.m.b8[12]; -+ ctxt->m.b8[16] = tctxt.m.b8[19]; ctxt->m.b8[17] = tctxt.m.b8[18]; -+ ctxt->m.b8[18] = tctxt.m.b8[17]; ctxt->m.b8[19] = tctxt.m.b8[16]; -+ ctxt->m.b8[20] = tctxt.m.b8[23]; ctxt->m.b8[21] = tctxt.m.b8[22]; -+ ctxt->m.b8[22] = tctxt.m.b8[21]; ctxt->m.b8[23] = tctxt.m.b8[20]; -+ ctxt->m.b8[24] = tctxt.m.b8[27]; ctxt->m.b8[25] = tctxt.m.b8[26]; -+ ctxt->m.b8[26] = tctxt.m.b8[25]; ctxt->m.b8[27] = tctxt.m.b8[24]; -+ ctxt->m.b8[28] = tctxt.m.b8[31]; ctxt->m.b8[29] = tctxt.m.b8[30]; -+ ctxt->m.b8[30] = tctxt.m.b8[29]; ctxt->m.b8[31] = tctxt.m.b8[28]; -+ ctxt->m.b8[32] = tctxt.m.b8[35]; ctxt->m.b8[33] = tctxt.m.b8[34]; -+ ctxt->m.b8[34] = tctxt.m.b8[33]; ctxt->m.b8[35] = tctxt.m.b8[32]; -+ ctxt->m.b8[36] = tctxt.m.b8[39]; ctxt->m.b8[37] = tctxt.m.b8[38]; -+ ctxt->m.b8[38] = tctxt.m.b8[37]; ctxt->m.b8[39] = tctxt.m.b8[36]; -+ ctxt->m.b8[40] = tctxt.m.b8[43]; ctxt->m.b8[41] = tctxt.m.b8[42]; -+ ctxt->m.b8[42] = tctxt.m.b8[41]; ctxt->m.b8[43] = tctxt.m.b8[40]; -+ ctxt->m.b8[44] = tctxt.m.b8[47]; ctxt->m.b8[45] = tctxt.m.b8[46]; -+ ctxt->m.b8[46] = tctxt.m.b8[45]; ctxt->m.b8[47] = tctxt.m.b8[44]; -+ ctxt->m.b8[48] = tctxt.m.b8[51]; ctxt->m.b8[49] = tctxt.m.b8[50]; -+ ctxt->m.b8[50] = tctxt.m.b8[49]; ctxt->m.b8[51] = tctxt.m.b8[48]; -+ ctxt->m.b8[52] = tctxt.m.b8[55]; ctxt->m.b8[53] = tctxt.m.b8[54]; -+ ctxt->m.b8[54] = tctxt.m.b8[53]; ctxt->m.b8[55] = tctxt.m.b8[52]; -+ ctxt->m.b8[56] = tctxt.m.b8[59]; ctxt->m.b8[57] = tctxt.m.b8[58]; -+ ctxt->m.b8[58] = tctxt.m.b8[57]; ctxt->m.b8[59] = tctxt.m.b8[56]; -+ ctxt->m.b8[60] = tctxt.m.b8[63]; ctxt->m.b8[61] = tctxt.m.b8[62]; -+ ctxt->m.b8[62] = tctxt.m.b8[61]; ctxt->m.b8[63] = tctxt.m.b8[60]; -+#endif -+ -+ a = H(0); b = H(1); c = H(2); d = H(3); e = H(4); -+ -+ for (t = 0; t < 20; t++) { -+ s = t & 0x0f; -+ if (t >= 16) { -+ W(s) = S(1, W((s+13) & 0x0f) ^ W((s+8) & 0x0f) ^ W((s+2) & 0x0f) ^ W(s)); -+ } -+ tmp = S(5, a) + F0(b, c, d) + e + W(s) + K(t); -+ e = d; d = c; c = S(30, b); b = a; a = tmp; -+ } -+ for (t = 20; t < 40; t++) { -+ s = t & 0x0f; -+ W(s) = S(1, W((s+13) & 0x0f) ^ W((s+8) & 0x0f) ^ W((s+2) & 0x0f) ^ W(s)); -+ tmp = S(5, a) + F1(b, c, d) + e + W(s) + K(t); -+ e = d; d = c; c = S(30, b); b = a; a = tmp; -+ } -+ for (t = 40; t < 60; t++) { -+ s = t & 0x0f; -+ W(s) = S(1, W((s+13) & 0x0f) ^ W((s+8) & 0x0f) ^ W((s+2) & 0x0f) ^ W(s)); -+ tmp = S(5, a) + F2(b, c, d) + e + W(s) + K(t); -+ e = d; d = c; c = S(30, b); b = a; a = tmp; -+ } -+ for (t = 60; t < 80; t++) { -+ s = t & 0x0f; -+ W(s) = S(1, W((s+13) & 0x0f) ^ W((s+8) & 0x0f) ^ W((s+2) & 0x0f) ^ W(s)); -+ tmp = S(5, a) + F3(b, c, d) + e + W(s) + K(t); -+ e = d; d = c; c = S(30, b); b = a; a = tmp; -+ } -+ -+ H(0) = H(0) + a; -+ H(1) = H(1) + b; -+ H(2) = H(2) + c; -+ H(3) = H(3) + d; -+ H(4) = H(4) + e; -+ -+ bzero(&ctxt->m.b8[0], 64); -+} -+ -+/*------------------------------------------------------------*/ -+ -+void -+sha1_init(ctxt) -+ struct sha1_ctxt *ctxt; -+{ -+ bzero(ctxt, sizeof(struct sha1_ctxt)); -+ H(0) = 0x67452301; -+ H(1) = 0xefcdab89; -+ H(2) = 0x98badcfe; -+ H(3) = 0x10325476; -+ H(4) = 0xc3d2e1f0; -+} -+ -+void -+sha1_pad(ctxt) -+ struct sha1_ctxt *ctxt; -+{ -+ size_t padlen; /*pad length in bytes*/ -+ size_t padstart; -+ -+ PUTPAD(0x80); -+ -+ padstart = COUNT % 64; -+ padlen = 64 - padstart; -+ if (padlen < 8) { -+ bzero(&ctxt->m.b8[padstart], padlen); -+ COUNT += padlen; -+ COUNT %= 64; -+ sha1_step(ctxt); -+ padstart = COUNT % 64; /* should be 0 */ -+ padlen = 64 - padstart; /* should be 64 */ -+ } -+ bzero(&ctxt->m.b8[padstart], padlen - 8); -+ COUNT += (padlen - 8); -+ COUNT %= 64; -+#if BYTE_ORDER == BIG_ENDIAN -+ PUTPAD(ctxt->c.b8[0]); PUTPAD(ctxt->c.b8[1]); -+ PUTPAD(ctxt->c.b8[2]); PUTPAD(ctxt->c.b8[3]); -+ PUTPAD(ctxt->c.b8[4]); PUTPAD(ctxt->c.b8[5]); -+ PUTPAD(ctxt->c.b8[6]); PUTPAD(ctxt->c.b8[7]); -+#else -+ PUTPAD(ctxt->c.b8[7]); PUTPAD(ctxt->c.b8[6]); -+ PUTPAD(ctxt->c.b8[5]); PUTPAD(ctxt->c.b8[4]); -+ PUTPAD(ctxt->c.b8[3]); PUTPAD(ctxt->c.b8[2]); -+ PUTPAD(ctxt->c.b8[1]); PUTPAD(ctxt->c.b8[0]); -+#endif -+} -+ -+void -+sha1_loop(ctxt, input, len) -+ struct sha1_ctxt *ctxt; -+ const u_int8_t *input; -+ size_t len; -+{ -+ size_t gaplen; -+ size_t gapstart; -+ size_t off; -+ size_t copysiz; -+ -+ off = 0; -+ -+ while (off < len) { -+ gapstart = COUNT % 64; -+ gaplen = 64 - gapstart; -+ -+ copysiz = (gaplen < len - off) ? gaplen : len - off; -+ bcopy(&input[off], &ctxt->m.b8[gapstart], copysiz); -+ COUNT += copysiz; -+ COUNT %= 64; -+ ctxt->c.b64[0] += copysiz * 8; -+ if (COUNT % 64 == 0) -+ sha1_step(ctxt); -+ off += copysiz; -+ } -+} -+ -+void -+sha1_result(ctxt, digest0) -+ struct sha1_ctxt *ctxt; -+ caddr_t digest0; -+{ -+ u_int8_t *digest; -+ -+ digest = (u_int8_t *)digest0; -+ sha1_pad(ctxt); -+#if BYTE_ORDER == BIG_ENDIAN -+ bcopy(&ctxt->h.b8[0], digest, 20); -+#else -+ digest[0] = ctxt->h.b8[3]; digest[1] = ctxt->h.b8[2]; -+ digest[2] = ctxt->h.b8[1]; digest[3] = ctxt->h.b8[0]; -+ digest[4] = ctxt->h.b8[7]; digest[5] = ctxt->h.b8[6]; -+ digest[6] = ctxt->h.b8[5]; digest[7] = ctxt->h.b8[4]; -+ digest[8] = ctxt->h.b8[11]; digest[9] = ctxt->h.b8[10]; -+ digest[10] = ctxt->h.b8[9]; digest[11] = ctxt->h.b8[8]; -+ digest[12] = ctxt->h.b8[15]; digest[13] = ctxt->h.b8[14]; -+ digest[14] = ctxt->h.b8[13]; digest[15] = ctxt->h.b8[12]; -+ digest[16] = ctxt->h.b8[19]; digest[17] = ctxt->h.b8[18]; -+ digest[18] = ctxt->h.b8[17]; digest[19] = ctxt->h.b8[16]; -+#endif -+} -+ -+#endif /*unsupported*/ -diff -Nur linux-3.0.4.orig/crypto/ocf/safe/sha1.h linux-3.0.4/crypto/ocf/safe/sha1.h ---- linux-3.0.4.orig/crypto/ocf/safe/sha1.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/safe/sha1.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,72 @@ -+/* $FreeBSD: src/sys/crypto/sha1.h,v 1.8 2002/03/20 05:13:50 alfred Exp $ */ -+/* $KAME: sha1.h,v 1.5 2000/03/27 04:36:23 sumikawa Exp $ */ -+ -+/* -+ * Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project. -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. Neither the name of the project nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ */ -+/* -+ * FIPS pub 180-1: Secure Hash Algorithm (SHA-1) -+ * based on: http://csrc.nist.gov/fips/fip180-1.txt -+ * implemented by Jun-ichiro itojun Itoh -+ */ -+ -+#ifndef _NETINET6_SHA1_H_ -+#define _NETINET6_SHA1_H_ -+ -+struct sha1_ctxt { -+ union { -+ u_int8_t b8[20]; -+ u_int32_t b32[5]; -+ } h; -+ union { -+ u_int8_t b8[8]; -+ u_int64_t b64[1]; -+ } c; -+ union { -+ u_int8_t b8[64]; -+ u_int32_t b32[16]; -+ } m; -+ u_int8_t count; -+}; -+ -+#ifdef __KERNEL__ -+extern void sha1_init(struct sha1_ctxt *); -+extern void sha1_pad(struct sha1_ctxt *); -+extern void sha1_loop(struct sha1_ctxt *, const u_int8_t *, size_t); -+extern void sha1_result(struct sha1_ctxt *, caddr_t); -+ -+/* compatibilty with other SHA1 source codes */ -+typedef struct sha1_ctxt SHA1_CTX; -+#define SHA1Init(x) sha1_init((x)) -+#define SHA1Update(x, y, z) sha1_loop((x), (y), (z)) -+#define SHA1Final(x, y) sha1_result((y), (x)) -+#endif /* __KERNEL__ */ -+ -+#define SHA1_RESULTLEN (160/8) -+ -+#endif /*_NETINET6_SHA1_H_*/ -diff -Nur linux-3.0.4.orig/crypto/ocf/talitos/Makefile linux-3.0.4/crypto/ocf/talitos/Makefile ---- linux-3.0.4.orig/crypto/ocf/talitos/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/talitos/Makefile 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,12 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+obj-$(CONFIG_OCF_TALITOS) += talitos.o -+ -+obj ?= . -+EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/talitos/talitos.c linux-3.0.4/crypto/ocf/talitos/talitos.c ---- linux-3.0.4.orig/crypto/ocf/talitos/talitos.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/talitos/talitos.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,1355 @@ -+/* -+ * crypto/ocf/talitos/talitos.c -+ * -+ * An OCF-Linux module that uses Freescale's SEC to do the crypto. -+ * Based on crypto/ocf/hifn and crypto/ocf/safe OCF drivers -+ * -+ * Copyright (c) 2006 Freescale Semiconductor, Inc. -+ * -+ * This code written by Kim A. B. Phillips -+ * some code copied from files with the following: -+ * Copyright (C) 2004-2007 David McCullough -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * --------------------------------------------------------------------------- -+ * -+ * NOTES: -+ * -+ * The Freescale SEC (also known as 'talitos') resides on the -+ * internal bus, and runs asynchronous to the processor core. It has -+ * a wide gamut of cryptographic acceleration features, including single- -+ * pass IPsec (also known as algorithm chaining). To properly utilize -+ * all of the SEC's performance enhancing features, further reworking -+ * of higher level code (framework, applications) will be necessary. -+ * -+ * The following table shows which SEC version is present in which devices: -+ * -+ * Devices SEC version -+ * -+ * 8272, 8248 SEC 1.0 -+ * 885, 875 SEC 1.2 -+ * 8555E, 8541E SEC 2.0 -+ * 8349E SEC 2.01 -+ * 8548E SEC 2.1 -+ * -+ * The following table shows the features offered by each SEC version: -+ * -+ * Max. chan- -+ * version Bus I/F Clock nels DEU AESU AFEU MDEU PKEU RNG KEU -+ * -+ * SEC 1.0 internal 64b 100MHz 4 1 1 1 1 1 1 0 -+ * SEC 1.2 internal 32b 66MHz 1 1 1 0 1 0 0 0 -+ * SEC 2.0 internal 64b 166MHz 4 1 1 1 1 1 1 0 -+ * SEC 2.01 internal 64b 166MHz 4 1 1 1 1 1 1 0 -+ * SEC 2.1 internal 64b 333MHz 4 1 1 1 1 1 1 1 -+ * -+ * Each execution unit in the SEC has two modes of execution; channel and -+ * slave/debug. This driver employs the channel infrastructure in the -+ * device for convenience. Only the RNG is directly accessed due to the -+ * convenience of its random fifo pool. The relationship between the -+ * channels and execution units is depicted in the following diagram: -+ * -+ * ------- ------------ -+ * ---| ch0 |---| | -+ * ------- | | -+ * | |------+-------+-------+-------+------------ -+ * ------- | | | | | | | -+ * ---| ch1 |---| | | | | | | -+ * ------- | | ------ ------ ------ ------ ------ -+ * |controller| |DEU | |AESU| |MDEU| |PKEU| ... |RNG | -+ * ------- | | ------ ------ ------ ------ ------ -+ * ---| ch2 |---| | | | | | | -+ * ------- | | | | | | | -+ * | |------+-------+-------+-------+------------ -+ * ------- | | -+ * ---| ch3 |---| | -+ * ------- ------------ -+ * -+ * Channel ch0 may drive an aes operation to the aes unit (AESU), -+ * and, at the same time, ch1 may drive a message digest operation -+ * to the mdeu. Each channel has an input descriptor FIFO, and the -+ * FIFO can contain, e.g. on the 8541E, up to 24 entries, before a -+ * a buffer overrun error is triggered. The controller is responsible -+ * for fetching the data from descriptor pointers, and passing the -+ * data to the appropriate EUs. The controller also writes the -+ * cryptographic operation's result to memory. The SEC notifies -+ * completion by triggering an interrupt and/or setting the 1st byte -+ * of the hdr field to 0xff. -+ * -+ * TODO: -+ * o support more algorithms -+ * o support more versions of the SEC -+ * o add support for linux 2.4 -+ * o scatter-gather (sg) support -+ * o add support for public key ops (PKEU) -+ * o add statistics -+ */ -+ -+#include -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include /* dma_map_single() */ -+#include -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,15) -+#include -+#endif -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) -+#include -+#endif -+ -+#include -+#include -+ -+#define DRV_NAME "talitos" -+ -+#include "talitos_dev.h" -+#include "talitos_soft.h" -+ -+#define read_random(p,l) get_random_bytes(p,l) -+ -+const char talitos_driver_name[] = "Talitos OCF"; -+const char talitos_driver_version[] = "0.2"; -+ -+static int talitos_newsession(device_t dev, u_int32_t *sidp, -+ struct cryptoini *cri); -+static int talitos_freesession(device_t dev, u_int64_t tid); -+static int talitos_process(device_t dev, struct cryptop *crp, int hint); -+static void dump_talitos_status(struct talitos_softc *sc); -+static int talitos_submit(struct talitos_softc *sc, struct talitos_desc *td, -+ int chsel); -+static void talitos_doneprocessing(struct talitos_softc *sc); -+static void talitos_init_device(struct talitos_softc *sc); -+static void talitos_reset_device_master(struct talitos_softc *sc); -+static void talitos_reset_device(struct talitos_softc *sc); -+static void talitos_errorprocessing(struct talitos_softc *sc); -+#ifdef CONFIG_PPC_MERGE -+static int talitos_probe(struct of_device *ofdev, const struct of_device_id *match); -+static int talitos_remove(struct of_device *ofdev); -+#else -+static int talitos_probe(struct platform_device *pdev); -+static int talitos_remove(struct platform_device *pdev); -+#endif -+#ifdef CONFIG_OCF_RANDOMHARVEST -+static int talitos_read_random(void *arg, u_int32_t *buf, int maxwords); -+static void talitos_rng_init(struct talitos_softc *sc); -+#endif -+ -+static device_method_t talitos_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, talitos_newsession), -+ DEVMETHOD(cryptodev_freesession,talitos_freesession), -+ DEVMETHOD(cryptodev_process, talitos_process), -+}; -+ -+#define debug talitos_debug -+int talitos_debug = 0; -+module_param(talitos_debug, int, 0644); -+MODULE_PARM_DESC(talitos_debug, "Enable debug"); -+ -+static inline void talitos_write(volatile unsigned *addr, u32 val) -+{ -+ out_be32(addr, val); -+} -+ -+static inline u32 talitos_read(volatile unsigned *addr) -+{ -+ u32 val; -+ val = in_be32(addr); -+ return val; -+} -+ -+static void dump_talitos_status(struct talitos_softc *sc) -+{ -+ unsigned int v, v_hi, i, *ptr; -+ v = talitos_read(sc->sc_base_addr + TALITOS_MCR); -+ v_hi = talitos_read(sc->sc_base_addr + TALITOS_MCR_HI); -+ printk(KERN_INFO "%s: MCR 0x%08x_%08x\n", -+ device_get_nameunit(sc->sc_cdev), v, v_hi); -+ v = talitos_read(sc->sc_base_addr + TALITOS_IMR); -+ v_hi = talitos_read(sc->sc_base_addr + TALITOS_IMR_HI); -+ printk(KERN_INFO "%s: IMR 0x%08x_%08x\n", -+ device_get_nameunit(sc->sc_cdev), v, v_hi); -+ v = talitos_read(sc->sc_base_addr + TALITOS_ISR); -+ v_hi = talitos_read(sc->sc_base_addr + TALITOS_ISR_HI); -+ printk(KERN_INFO "%s: ISR 0x%08x_%08x\n", -+ device_get_nameunit(sc->sc_cdev), v, v_hi); -+ for (i = 0; i < sc->sc_num_channels; i++) { -+ v = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + -+ TALITOS_CH_CDPR); -+ v_hi = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + -+ TALITOS_CH_CDPR_HI); -+ printk(KERN_INFO "%s: CDPR ch%d 0x%08x_%08x\n", -+ device_get_nameunit(sc->sc_cdev), i, v, v_hi); -+ } -+ for (i = 0; i < sc->sc_num_channels; i++) { -+ v = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + -+ TALITOS_CH_CCPSR); -+ v_hi = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + -+ TALITOS_CH_CCPSR_HI); -+ printk(KERN_INFO "%s: CCPSR ch%d 0x%08x_%08x\n", -+ device_get_nameunit(sc->sc_cdev), i, v, v_hi); -+ } -+ ptr = sc->sc_base_addr + TALITOS_CH_DESCBUF; -+ for (i = 0; i < 16; i++) { -+ v = talitos_read(ptr++); v_hi = talitos_read(ptr++); -+ printk(KERN_INFO "%s: DESCBUF ch0 0x%08x_%08x (tdp%02d)\n", -+ device_get_nameunit(sc->sc_cdev), v, v_hi, i); -+ } -+ return; -+} -+ -+ -+#ifdef CONFIG_OCF_RANDOMHARVEST -+/* -+ * pull random numbers off the RNG FIFO, not exceeding amount available -+ */ -+static int -+talitos_read_random(void *arg, u_int32_t *buf, int maxwords) -+{ -+ struct talitos_softc *sc = (struct talitos_softc *) arg; -+ int rc; -+ u_int32_t v; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ /* check for things like FIFO underflow */ -+ v = talitos_read(sc->sc_base_addr + TALITOS_RNGISR_HI); -+ if (unlikely(v)) { -+ printk(KERN_ERR "%s: RNGISR_HI error %08x\n", -+ device_get_nameunit(sc->sc_cdev), v); -+ return 0; -+ } -+ /* -+ * OFL is number of available 64-bit words, -+ * shift and convert to a 32-bit word count -+ */ -+ v = talitos_read(sc->sc_base_addr + TALITOS_RNGSR_HI); -+ v = (v & TALITOS_RNGSR_HI_OFL) >> (16 - 1); -+ if (maxwords > v) -+ maxwords = v; -+ for (rc = 0; rc < maxwords; rc++) { -+ buf[rc] = talitos_read(sc->sc_base_addr + -+ TALITOS_RNG_FIFO + rc*sizeof(u_int32_t)); -+ } -+ if (maxwords & 1) { -+ /* -+ * RNG will complain with an AE in the RNGISR -+ * if we don't complete the pairs of 32-bit reads -+ * to its 64-bit register based FIFO -+ */ -+ v = talitos_read(sc->sc_base_addr + -+ TALITOS_RNG_FIFO + rc*sizeof(u_int32_t)); -+ } -+ -+ return rc; -+} -+ -+static void -+talitos_rng_init(struct talitos_softc *sc) -+{ -+ u_int32_t v; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ /* reset RNG EU */ -+ v = talitos_read(sc->sc_base_addr + TALITOS_RNGRCR_HI); -+ v |= TALITOS_RNGRCR_HI_SR; -+ talitos_write(sc->sc_base_addr + TALITOS_RNGRCR_HI, v); -+ while ((talitos_read(sc->sc_base_addr + TALITOS_RNGSR_HI) -+ & TALITOS_RNGSR_HI_RD) == 0) -+ cpu_relax(); -+ /* -+ * we tell the RNG to start filling the RNG FIFO -+ * by writing the RNGDSR -+ */ -+ v = talitos_read(sc->sc_base_addr + TALITOS_RNGDSR_HI); -+ talitos_write(sc->sc_base_addr + TALITOS_RNGDSR_HI, v); -+ /* -+ * 64 bits of data will be pushed onto the FIFO every -+ * 256 SEC cycles until the FIFO is full. The RNG then -+ * attempts to keep the FIFO full. -+ */ -+ v = talitos_read(sc->sc_base_addr + TALITOS_RNGISR_HI); -+ if (v) { -+ printk(KERN_ERR "%s: RNGISR_HI error %08x\n", -+ device_get_nameunit(sc->sc_cdev), v); -+ return; -+ } -+ /* -+ * n.b. we need to add a FIPS test here - if the RNG is going -+ * to fail, it's going to fail at reset time -+ */ -+ return; -+} -+#endif /* CONFIG_OCF_RANDOMHARVEST */ -+ -+/* -+ * Generate a new software session. -+ */ -+static int -+talitos_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) -+{ -+ struct cryptoini *c, *encini = NULL, *macini = NULL; -+ struct talitos_softc *sc = device_get_softc(dev); -+ struct talitos_session *ses = NULL; -+ int sesn; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ if (sidp == NULL || cri == NULL || sc == NULL) { -+ DPRINTF("%s,%d - EINVAL\n", __FILE__, __LINE__); -+ return EINVAL; -+ } -+ for (c = cri; c != NULL; c = c->cri_next) { -+ if (c->cri_alg == CRYPTO_MD5 || -+ c->cri_alg == CRYPTO_MD5_HMAC || -+ c->cri_alg == CRYPTO_SHA1 || -+ c->cri_alg == CRYPTO_SHA1_HMAC || -+ c->cri_alg == CRYPTO_NULL_HMAC) { -+ if (macini) -+ return EINVAL; -+ macini = c; -+ } else if (c->cri_alg == CRYPTO_DES_CBC || -+ c->cri_alg == CRYPTO_3DES_CBC || -+ c->cri_alg == CRYPTO_AES_CBC || -+ c->cri_alg == CRYPTO_NULL_CBC) { -+ if (encini) -+ return EINVAL; -+ encini = c; -+ } else { -+ DPRINTF("UNKNOWN c->cri_alg %d\n", encini->cri_alg); -+ return EINVAL; -+ } -+ } -+ if (encini == NULL && macini == NULL) -+ return EINVAL; -+ if (encini) { -+ /* validate key length */ -+ switch (encini->cri_alg) { -+ case CRYPTO_DES_CBC: -+ if (encini->cri_klen != 64) -+ return EINVAL; -+ break; -+ case CRYPTO_3DES_CBC: -+ if (encini->cri_klen != 192) { -+ return EINVAL; -+ } -+ break; -+ case CRYPTO_AES_CBC: -+ if (encini->cri_klen != 128 && -+ encini->cri_klen != 192 && -+ encini->cri_klen != 256) -+ return EINVAL; -+ break; -+ default: -+ DPRINTF("UNKNOWN encini->cri_alg %d\n", -+ encini->cri_alg); -+ return EINVAL; -+ } -+ } -+ -+ if (sc->sc_sessions == NULL) { -+ ses = sc->sc_sessions = (struct talitos_session *) -+ kmalloc(sizeof(struct talitos_session), SLAB_ATOMIC); -+ if (ses == NULL) -+ return ENOMEM; -+ memset(ses, 0, sizeof(struct talitos_session)); -+ sesn = 0; -+ sc->sc_nsessions = 1; -+ } else { -+ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { -+ if (sc->sc_sessions[sesn].ses_used == 0) { -+ ses = &sc->sc_sessions[sesn]; -+ break; -+ } -+ } -+ -+ if (ses == NULL) { -+ /* allocating session */ -+ sesn = sc->sc_nsessions; -+ ses = (struct talitos_session *) kmalloc( -+ (sesn + 1) * sizeof(struct talitos_session), -+ SLAB_ATOMIC); -+ if (ses == NULL) -+ return ENOMEM; -+ memset(ses, 0, -+ (sesn + 1) * sizeof(struct talitos_session)); -+ memcpy(ses, sc->sc_sessions, -+ sesn * sizeof(struct talitos_session)); -+ memset(sc->sc_sessions, 0, -+ sesn * sizeof(struct talitos_session)); -+ kfree(sc->sc_sessions); -+ sc->sc_sessions = ses; -+ ses = &sc->sc_sessions[sesn]; -+ sc->sc_nsessions++; -+ } -+ } -+ -+ ses->ses_used = 1; -+ -+ if (encini) { -+ ses->ses_klen = (encini->cri_klen + 7) / 8; -+ memcpy(ses->ses_key, encini->cri_key, ses->ses_klen); -+ if (macini) { -+ /* doing hash on top of cipher */ -+ ses->ses_hmac_len = (macini->cri_klen + 7) / 8; -+ memcpy(ses->ses_hmac, macini->cri_key, -+ ses->ses_hmac_len); -+ } -+ } else if (macini) { -+ /* doing hash */ -+ ses->ses_klen = (macini->cri_klen + 7) / 8; -+ memcpy(ses->ses_key, macini->cri_key, ses->ses_klen); -+ } -+ -+ /* back compat way of determining MSC result len */ -+ if (macini) { -+ ses->ses_mlen = macini->cri_mlen; -+ if (ses->ses_mlen == 0) { -+ if (macini->cri_alg == CRYPTO_MD5_HMAC) -+ ses->ses_mlen = MD5_HASH_LEN; -+ else -+ ses->ses_mlen = SHA1_HASH_LEN; -+ } -+ } -+ -+ /* really should make up a template td here, -+ * and only fill things like i/o and direction in process() */ -+ -+ /* assign session ID */ -+ *sidp = TALITOS_SID(sc->sc_num, sesn); -+ return 0; -+} -+ -+/* -+ * Deallocate a session. -+ */ -+static int -+talitos_freesession(device_t dev, u_int64_t tid) -+{ -+ struct talitos_softc *sc = device_get_softc(dev); -+ int session, ret; -+ u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; -+ -+ if (sc == NULL) -+ return EINVAL; -+ session = TALITOS_SESSION(sid); -+ if (session < sc->sc_nsessions) { -+ memset(&sc->sc_sessions[session], 0, -+ sizeof(sc->sc_sessions[session])); -+ ret = 0; -+ } else -+ ret = EINVAL; -+ return ret; -+} -+ -+/* -+ * launch device processing - it will come back with done notification -+ * in the form of an interrupt and/or HDR_DONE_BITS in header -+ */ -+static int -+talitos_submit( -+ struct talitos_softc *sc, -+ struct talitos_desc *td, -+ int chsel) -+{ -+ u_int32_t v; -+ -+ v = dma_map_single(NULL, td, sizeof(*td), DMA_TO_DEVICE); -+ talitos_write(sc->sc_base_addr + -+ chsel*TALITOS_CH_OFFSET + TALITOS_CH_FF, 0); -+ talitos_write(sc->sc_base_addr + -+ chsel*TALITOS_CH_OFFSET + TALITOS_CH_FF_HI, v); -+ return 0; -+} -+ -+static int -+talitos_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ int i, err = 0, ivsize; -+ struct talitos_softc *sc = device_get_softc(dev); -+ struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; -+ caddr_t iv; -+ struct talitos_session *ses; -+ struct talitos_desc *td; -+ unsigned long flags; -+ /* descriptor mappings */ -+ int hmac_key, hmac_data, cipher_iv, cipher_key, -+ in_fifo, out_fifo, cipher_iv_out; -+ static int chsel = -1; -+ u_int32_t rand_iv[4]; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { -+ return EINVAL; -+ } -+ crp->crp_etype = 0; -+ if (TALITOS_SESSION(crp->crp_sid) >= sc->sc_nsessions) { -+ return EINVAL; -+ } -+ -+ ses = &sc->sc_sessions[TALITOS_SESSION(crp->crp_sid)]; -+ -+ /* enter the channel scheduler */ -+ spin_lock_irqsave(&sc->sc_chnfifolock[sc->sc_num_channels], flags); -+ -+ /* reuse channel that already had/has requests for the required EU */ -+ for (i = 0; i < sc->sc_num_channels; i++) { -+ if (sc->sc_chnlastalg[i] == crp->crp_desc->crd_alg) -+ break; -+ } -+ if (i == sc->sc_num_channels) { -+ /* -+ * haven't seen this algo the last sc_num_channels or more -+ * use round robin in this case -+ * nb: sc->sc_num_channels must be power of 2 -+ */ -+ chsel = (chsel + 1) & (sc->sc_num_channels - 1); -+ } else { -+ /* -+ * matches channel with same target execution unit; -+ * use same channel in this case -+ */ -+ chsel = i; -+ } -+ sc->sc_chnlastalg[chsel] = crp->crp_desc->crd_alg; -+ -+ /* release the channel scheduler lock */ -+ spin_unlock_irqrestore(&sc->sc_chnfifolock[sc->sc_num_channels], flags); -+ -+ /* acquire the selected channel fifo lock */ -+ spin_lock_irqsave(&sc->sc_chnfifolock[chsel], flags); -+ -+ /* find and reserve next available descriptor-cryptop pair */ -+ for (i = 0; i < sc->sc_chfifo_len; i++) { -+ if (sc->sc_chnfifo[chsel][i].cf_desc.hdr == 0) { -+ /* -+ * ensure correct descriptor formation by -+ * avoiding inadvertently setting "optional" entries -+ * e.g. not using "optional" dptr2 for MD/HMAC descs -+ */ -+ memset(&sc->sc_chnfifo[chsel][i].cf_desc, -+ 0, sizeof(*td)); -+ /* reserve it with done notification request bit */ -+ sc->sc_chnfifo[chsel][i].cf_desc.hdr |= -+ TALITOS_DONE_NOTIFY; -+ break; -+ } -+ } -+ spin_unlock_irqrestore(&sc->sc_chnfifolock[chsel], flags); -+ -+ if (i == sc->sc_chfifo_len) { -+ /* fifo full */ -+ err = ERESTART; -+ goto errout; -+ } -+ -+ td = &sc->sc_chnfifo[chsel][i].cf_desc; -+ sc->sc_chnfifo[chsel][i].cf_crp = crp; -+ -+ crd1 = crp->crp_desc; -+ if (crd1 == NULL) { -+ err = EINVAL; -+ goto errout; -+ } -+ crd2 = crd1->crd_next; -+ /* prevent compiler warning */ -+ hmac_key = 0; -+ hmac_data = 0; -+ if (crd2 == NULL) { -+ td->hdr |= TD_TYPE_COMMON_NONSNOOP_NO_AFEU; -+ /* assign descriptor dword ptr mappings for this desc. type */ -+ cipher_iv = 1; -+ cipher_key = 2; -+ in_fifo = 3; -+ cipher_iv_out = 5; -+ if (crd1->crd_alg == CRYPTO_MD5_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1 || -+ crd1->crd_alg == CRYPTO_MD5) { -+ out_fifo = 5; -+ maccrd = crd1; -+ enccrd = NULL; -+ } else if (crd1->crd_alg == CRYPTO_DES_CBC || -+ crd1->crd_alg == CRYPTO_3DES_CBC || -+ crd1->crd_alg == CRYPTO_AES_CBC || -+ crd1->crd_alg == CRYPTO_ARC4) { -+ out_fifo = 4; -+ maccrd = NULL; -+ enccrd = crd1; -+ } else { -+ DPRINTF("UNKNOWN crd1->crd_alg %d\n", crd1->crd_alg); -+ err = EINVAL; -+ goto errout; -+ } -+ } else { -+ if (sc->sc_desc_types & TALITOS_HAS_DT_IPSEC_ESP) { -+ td->hdr |= TD_TYPE_IPSEC_ESP; -+ } else { -+ DPRINTF("unimplemented: multiple descriptor ipsec\n"); -+ err = EINVAL; -+ goto errout; -+ } -+ /* assign descriptor dword ptr mappings for this desc. type */ -+ hmac_key = 0; -+ hmac_data = 1; -+ cipher_iv = 2; -+ cipher_key = 3; -+ in_fifo = 4; -+ out_fifo = 5; -+ cipher_iv_out = 6; -+ if ((crd1->crd_alg == CRYPTO_MD5_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1_HMAC || -+ crd1->crd_alg == CRYPTO_MD5 || -+ crd1->crd_alg == CRYPTO_SHA1) && -+ (crd2->crd_alg == CRYPTO_DES_CBC || -+ crd2->crd_alg == CRYPTO_3DES_CBC || -+ crd2->crd_alg == CRYPTO_AES_CBC || -+ crd2->crd_alg == CRYPTO_ARC4) && -+ ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { -+ maccrd = crd1; -+ enccrd = crd2; -+ } else if ((crd1->crd_alg == CRYPTO_DES_CBC || -+ crd1->crd_alg == CRYPTO_ARC4 || -+ crd1->crd_alg == CRYPTO_3DES_CBC || -+ crd1->crd_alg == CRYPTO_AES_CBC) && -+ (crd2->crd_alg == CRYPTO_MD5_HMAC || -+ crd2->crd_alg == CRYPTO_SHA1_HMAC || -+ crd2->crd_alg == CRYPTO_MD5 || -+ crd2->crd_alg == CRYPTO_SHA1) && -+ (crd1->crd_flags & CRD_F_ENCRYPT)) { -+ enccrd = crd1; -+ maccrd = crd2; -+ } else { -+ /* We cannot order the SEC as requested */ -+ printk("%s: cannot do the order\n", -+ device_get_nameunit(sc->sc_cdev)); -+ err = EINVAL; -+ goto errout; -+ } -+ } -+ /* assign in_fifo and out_fifo based on input/output struct type */ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ /* using SKB buffers */ -+ struct sk_buff *skb = (struct sk_buff *)crp->crp_buf; -+ if (skb_shinfo(skb)->nr_frags) { -+ printk("%s: skb frags unimplemented\n", -+ device_get_nameunit(sc->sc_cdev)); -+ err = EINVAL; -+ goto errout; -+ } -+ td->ptr[in_fifo].ptr = dma_map_single(NULL, skb->data, -+ skb->len, DMA_TO_DEVICE); -+ td->ptr[in_fifo].len = skb->len; -+ td->ptr[out_fifo].ptr = dma_map_single(NULL, skb->data, -+ skb->len, DMA_TO_DEVICE); -+ td->ptr[out_fifo].len = skb->len; -+ td->ptr[hmac_data].ptr = dma_map_single(NULL, skb->data, -+ skb->len, DMA_TO_DEVICE); -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ /* using IOV buffers */ -+ struct uio *uiop = (struct uio *)crp->crp_buf; -+ if (uiop->uio_iovcnt > 1) { -+ printk("%s: iov frags unimplemented\n", -+ device_get_nameunit(sc->sc_cdev)); -+ err = EINVAL; -+ goto errout; -+ } -+ td->ptr[in_fifo].ptr = dma_map_single(NULL, -+ uiop->uio_iov->iov_base, crp->crp_ilen, DMA_TO_DEVICE); -+ td->ptr[in_fifo].len = crp->crp_ilen; -+ /* crp_olen is never set; always use crp_ilen */ -+ td->ptr[out_fifo].ptr = dma_map_single(NULL, -+ uiop->uio_iov->iov_base, -+ crp->crp_ilen, DMA_TO_DEVICE); -+ td->ptr[out_fifo].len = crp->crp_ilen; -+ } else { -+ /* using contig buffers */ -+ td->ptr[in_fifo].ptr = dma_map_single(NULL, -+ crp->crp_buf, crp->crp_ilen, DMA_TO_DEVICE); -+ td->ptr[in_fifo].len = crp->crp_ilen; -+ td->ptr[out_fifo].ptr = dma_map_single(NULL, -+ crp->crp_buf, crp->crp_ilen, DMA_TO_DEVICE); -+ td->ptr[out_fifo].len = crp->crp_ilen; -+ } -+ if (enccrd) { -+ switch (enccrd->crd_alg) { -+ case CRYPTO_3DES_CBC: -+ td->hdr |= TALITOS_MODE0_DEU_3DES; -+ /* FALLTHROUGH */ -+ case CRYPTO_DES_CBC: -+ td->hdr |= TALITOS_SEL0_DEU -+ | TALITOS_MODE0_DEU_CBC; -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) -+ td->hdr |= TALITOS_MODE0_DEU_ENC; -+ ivsize = 2*sizeof(u_int32_t); -+ DPRINTF("%cDES ses %d ch %d len %d\n", -+ (td->hdr & TALITOS_MODE0_DEU_3DES)?'3':'1', -+ (u32)TALITOS_SESSION(crp->crp_sid), -+ chsel, td->ptr[in_fifo].len); -+ break; -+ case CRYPTO_AES_CBC: -+ td->hdr |= TALITOS_SEL0_AESU -+ | TALITOS_MODE0_AESU_CBC; -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) -+ td->hdr |= TALITOS_MODE0_AESU_ENC; -+ ivsize = 4*sizeof(u_int32_t); -+ DPRINTF("AES ses %d ch %d len %d\n", -+ (u32)TALITOS_SESSION(crp->crp_sid), -+ chsel, td->ptr[in_fifo].len); -+ break; -+ default: -+ printk("%s: unimplemented enccrd->crd_alg %d\n", -+ device_get_nameunit(sc->sc_cdev), enccrd->crd_alg); -+ err = EINVAL; -+ goto errout; -+ } -+ /* -+ * Setup encrypt/decrypt state. When using basic ops -+ * we can't use an inline IV because hash/crypt offset -+ * must be from the end of the IV to the start of the -+ * crypt data and this leaves out the preceding header -+ * from the hash calculation. Instead we place the IV -+ * in the state record and set the hash/crypt offset to -+ * copy both the header+IV. -+ */ -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) { -+ td->hdr |= TALITOS_DIR_OUTBOUND; -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) -+ iv = enccrd->crd_iv; -+ else -+ read_random((iv = (caddr_t) rand_iv), sizeof(rand_iv)); -+ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ enccrd->crd_inject, ivsize, iv); -+ } -+ } else { -+ td->hdr |= TALITOS_DIR_INBOUND; -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) { -+ iv = enccrd->crd_iv; -+ } else { -+ iv = (caddr_t) rand_iv; -+ crypto_copydata(crp->crp_flags, crp->crp_buf, -+ enccrd->crd_inject, ivsize, iv); -+ } -+ } -+ td->ptr[cipher_iv].ptr = dma_map_single(NULL, iv, ivsize, -+ DMA_TO_DEVICE); -+ td->ptr[cipher_iv].len = ivsize; -+ /* -+ * we don't need the cipher iv out length/pointer -+ * field to do ESP IPsec. Therefore we set the len field as 0, -+ * which tells the SEC not to do anything with this len/ptr -+ * field. Previously, when length/pointer as pointing to iv, -+ * it gave us corruption of packets. -+ */ -+ td->ptr[cipher_iv_out].len = 0; -+ } -+ if (enccrd && maccrd) { -+ /* this is ipsec only for now */ -+ td->hdr |= TALITOS_SEL1_MDEU -+ | TALITOS_MODE1_MDEU_INIT -+ | TALITOS_MODE1_MDEU_PAD; -+ switch (maccrd->crd_alg) { -+ case CRYPTO_MD5: -+ td->hdr |= TALITOS_MODE1_MDEU_MD5; -+ break; -+ case CRYPTO_MD5_HMAC: -+ td->hdr |= TALITOS_MODE1_MDEU_MD5_HMAC; -+ break; -+ case CRYPTO_SHA1: -+ td->hdr |= TALITOS_MODE1_MDEU_SHA1; -+ break; -+ case CRYPTO_SHA1_HMAC: -+ td->hdr |= TALITOS_MODE1_MDEU_SHA1_HMAC; -+ break; -+ default: -+ /* We cannot order the SEC as requested */ -+ printk("%s: cannot do the order\n", -+ device_get_nameunit(sc->sc_cdev)); -+ err = EINVAL; -+ goto errout; -+ } -+ if ((maccrd->crd_alg == CRYPTO_MD5_HMAC) || -+ (maccrd->crd_alg == CRYPTO_SHA1_HMAC)) { -+ /* -+ * The offset from hash data to the start of -+ * crypt data is the difference in the skips. -+ */ -+ /* ipsec only for now */ -+ td->ptr[hmac_key].ptr = dma_map_single(NULL, -+ ses->ses_hmac, ses->ses_hmac_len, DMA_TO_DEVICE); -+ td->ptr[hmac_key].len = ses->ses_hmac_len; -+ td->ptr[in_fifo].ptr += enccrd->crd_skip; -+ td->ptr[in_fifo].len = enccrd->crd_len; -+ td->ptr[out_fifo].ptr += enccrd->crd_skip; -+ td->ptr[out_fifo].len = enccrd->crd_len; -+ /* bytes of HMAC to postpend to ciphertext */ -+ td->ptr[out_fifo].extent = ses->ses_mlen; -+ td->ptr[hmac_data].ptr += maccrd->crd_skip; -+ td->ptr[hmac_data].len = enccrd->crd_skip - maccrd->crd_skip; -+ } -+ if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) { -+ printk("%s: CRD_F_KEY_EXPLICIT unimplemented\n", -+ device_get_nameunit(sc->sc_cdev)); -+ } -+ } -+ if (!enccrd && maccrd) { -+ /* single MD5 or SHA */ -+ td->hdr |= TALITOS_SEL0_MDEU -+ | TALITOS_MODE0_MDEU_INIT -+ | TALITOS_MODE0_MDEU_PAD; -+ switch (maccrd->crd_alg) { -+ case CRYPTO_MD5: -+ td->hdr |= TALITOS_MODE0_MDEU_MD5; -+ DPRINTF("MD5 ses %d ch %d len %d\n", -+ (u32)TALITOS_SESSION(crp->crp_sid), -+ chsel, td->ptr[in_fifo].len); -+ break; -+ case CRYPTO_MD5_HMAC: -+ td->hdr |= TALITOS_MODE0_MDEU_MD5_HMAC; -+ break; -+ case CRYPTO_SHA1: -+ td->hdr |= TALITOS_MODE0_MDEU_SHA1; -+ DPRINTF("SHA1 ses %d ch %d len %d\n", -+ (u32)TALITOS_SESSION(crp->crp_sid), -+ chsel, td->ptr[in_fifo].len); -+ break; -+ case CRYPTO_SHA1_HMAC: -+ td->hdr |= TALITOS_MODE0_MDEU_SHA1_HMAC; -+ break; -+ default: -+ /* We cannot order the SEC as requested */ -+ DPRINTF("cannot do the order\n"); -+ err = EINVAL; -+ goto errout; -+ } -+ -+ if (crp->crp_flags & CRYPTO_F_IOV) -+ td->ptr[out_fifo].ptr += maccrd->crd_inject; -+ -+ if ((maccrd->crd_alg == CRYPTO_MD5_HMAC) || -+ (maccrd->crd_alg == CRYPTO_SHA1_HMAC)) { -+ td->ptr[hmac_key].ptr = dma_map_single(NULL, -+ ses->ses_hmac, ses->ses_hmac_len, -+ DMA_TO_DEVICE); -+ td->ptr[hmac_key].len = ses->ses_hmac_len; -+ } -+ } -+ else { -+ /* using process key (session data has duplicate) */ -+ td->ptr[cipher_key].ptr = dma_map_single(NULL, -+ enccrd->crd_key, (enccrd->crd_klen + 7) / 8, -+ DMA_TO_DEVICE); -+ td->ptr[cipher_key].len = (enccrd->crd_klen + 7) / 8; -+ } -+ /* descriptor complete - GO! */ -+ return talitos_submit(sc, td, chsel); -+ -+errout: -+ if (err != ERESTART) { -+ crp->crp_etype = err; -+ crypto_done(crp); -+ } -+ return err; -+} -+ -+/* go through all channels descriptors, notifying OCF what has -+ * _and_hasn't_ successfully completed and reset the device -+ * (otherwise it's up to decoding desc hdrs!) -+ */ -+static void talitos_errorprocessing(struct talitos_softc *sc) -+{ -+ unsigned long flags; -+ int i, j; -+ -+ /* disable further scheduling until under control */ -+ spin_lock_irqsave(&sc->sc_chnfifolock[sc->sc_num_channels], flags); -+ -+ if (debug) dump_talitos_status(sc); -+ /* go through descriptors, try and salvage those successfully done, -+ * and EIO those that weren't -+ */ -+ for (i = 0; i < sc->sc_num_channels; i++) { -+ spin_lock_irqsave(&sc->sc_chnfifolock[i], flags); -+ for (j = 0; j < sc->sc_chfifo_len; j++) { -+ if (sc->sc_chnfifo[i][j].cf_desc.hdr) { -+ if ((sc->sc_chnfifo[i][j].cf_desc.hdr -+ & TALITOS_HDR_DONE_BITS) -+ != TALITOS_HDR_DONE_BITS) { -+ /* this one didn't finish */ -+ /* signify in crp->etype */ -+ sc->sc_chnfifo[i][j].cf_crp->crp_etype -+ = EIO; -+ } -+ } else -+ continue; /* free entry */ -+ /* either way, notify ocf */ -+ crypto_done(sc->sc_chnfifo[i][j].cf_crp); -+ /* and tag it available again -+ * -+ * memset to ensure correct descriptor formation by -+ * avoiding inadvertently setting "optional" entries -+ * e.g. not using "optional" dptr2 MD/HMAC processing -+ */ -+ memset(&sc->sc_chnfifo[i][j].cf_desc, -+ 0, sizeof(struct talitos_desc)); -+ } -+ spin_unlock_irqrestore(&sc->sc_chnfifolock[i], flags); -+ } -+ /* reset and initialize the SEC h/w device */ -+ talitos_reset_device(sc); -+ talitos_init_device(sc); -+#ifdef CONFIG_OCF_RANDOMHARVEST -+ if (sc->sc_exec_units & TALITOS_HAS_EU_RNG) -+ talitos_rng_init(sc); -+#endif -+ -+ /* Okay. Stand by. */ -+ spin_unlock_irqrestore(&sc->sc_chnfifolock[sc->sc_num_channels], flags); -+ -+ return; -+} -+ -+/* go through all channels descriptors, notifying OCF what's been done */ -+static void talitos_doneprocessing(struct talitos_softc *sc) -+{ -+ unsigned long flags; -+ int i, j; -+ -+ /* go through descriptors looking for done bits */ -+ for (i = 0; i < sc->sc_num_channels; i++) { -+ spin_lock_irqsave(&sc->sc_chnfifolock[i], flags); -+ for (j = 0; j < sc->sc_chfifo_len; j++) { -+ /* descriptor has done bits set? */ -+ if ((sc->sc_chnfifo[i][j].cf_desc.hdr -+ & TALITOS_HDR_DONE_BITS) -+ == TALITOS_HDR_DONE_BITS) { -+ /* notify ocf */ -+ crypto_done(sc->sc_chnfifo[i][j].cf_crp); -+ /* and tag it available again -+ * -+ * memset to ensure correct descriptor formation by -+ * avoiding inadvertently setting "optional" entries -+ * e.g. not using "optional" dptr2 MD/HMAC processing -+ */ -+ memset(&sc->sc_chnfifo[i][j].cf_desc, -+ 0, sizeof(struct talitos_desc)); -+ } -+ } -+ spin_unlock_irqrestore(&sc->sc_chnfifolock[i], flags); -+ } -+ return; -+} -+ -+static irqreturn_t -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) -+talitos_intr(int irq, void *arg) -+#else -+talitos_intr(int irq, void *arg, struct pt_regs *regs) -+#endif -+{ -+ struct talitos_softc *sc = arg; -+ u_int32_t v, v_hi; -+ -+ /* ack */ -+ v = talitos_read(sc->sc_base_addr + TALITOS_ISR); -+ v_hi = talitos_read(sc->sc_base_addr + TALITOS_ISR_HI); -+ talitos_write(sc->sc_base_addr + TALITOS_ICR, v); -+ talitos_write(sc->sc_base_addr + TALITOS_ICR_HI, v_hi); -+ -+ if (unlikely(v & TALITOS_ISR_ERROR)) { -+ /* Okay, Houston, we've had a problem here. */ -+ printk(KERN_DEBUG "%s: got error interrupt - ISR 0x%08x_%08x\n", -+ device_get_nameunit(sc->sc_cdev), v, v_hi); -+ talitos_errorprocessing(sc); -+ } else -+ if (likely(v & TALITOS_ISR_DONE)) { -+ talitos_doneprocessing(sc); -+ } -+ return IRQ_HANDLED; -+} -+ -+/* -+ * Initialize registers we need to touch only once. -+ */ -+static void -+talitos_init_device(struct talitos_softc *sc) -+{ -+ u_int32_t v; -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ /* init all channels */ -+ for (i = 0; i < sc->sc_num_channels; i++) { -+ v = talitos_read(sc->sc_base_addr + -+ i*TALITOS_CH_OFFSET + TALITOS_CH_CCCR_HI); -+ v |= TALITOS_CH_CCCR_HI_CDWE -+ | TALITOS_CH_CCCR_HI_CDIE; /* invoke interrupt if done */ -+ talitos_write(sc->sc_base_addr + -+ i*TALITOS_CH_OFFSET + TALITOS_CH_CCCR_HI, v); -+ } -+ /* enable all interrupts */ -+ v = talitos_read(sc->sc_base_addr + TALITOS_IMR); -+ v |= TALITOS_IMR_ALL; -+ talitos_write(sc->sc_base_addr + TALITOS_IMR, v); -+ v = talitos_read(sc->sc_base_addr + TALITOS_IMR_HI); -+ v |= TALITOS_IMR_HI_ERRONLY; -+ talitos_write(sc->sc_base_addr + TALITOS_IMR_HI, v); -+ return; -+} -+ -+/* -+ * set the master reset bit on the device. -+ */ -+static void -+talitos_reset_device_master(struct talitos_softc *sc) -+{ -+ u_int32_t v; -+ -+ /* Reset the device by writing 1 to MCR:SWR and waiting 'til cleared */ -+ v = talitos_read(sc->sc_base_addr + TALITOS_MCR); -+ talitos_write(sc->sc_base_addr + TALITOS_MCR, v | TALITOS_MCR_SWR); -+ -+ while (talitos_read(sc->sc_base_addr + TALITOS_MCR) & TALITOS_MCR_SWR) -+ cpu_relax(); -+ -+ return; -+} -+ -+/* -+ * Resets the device. Values in the registers are left as is -+ * from the reset (i.e. initial values are assigned elsewhere). -+ */ -+static void -+talitos_reset_device(struct talitos_softc *sc) -+{ -+ u_int32_t v; -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ /* -+ * Master reset -+ * errata documentation: warning: certain SEC interrupts -+ * are not fully cleared by writing the MCR:SWR bit, -+ * set bit twice to completely reset -+ */ -+ talitos_reset_device_master(sc); /* once */ -+ talitos_reset_device_master(sc); /* and once again */ -+ -+ /* reset all channels */ -+ for (i = 0; i < sc->sc_num_channels; i++) { -+ v = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + -+ TALITOS_CH_CCCR); -+ talitos_write(sc->sc_base_addr + i*TALITOS_CH_OFFSET + -+ TALITOS_CH_CCCR, v | TALITOS_CH_CCCR_RESET); -+ } -+} -+ -+/* Set up the crypto device structure, private data, -+ * and anything else we need before we start */ -+#ifdef CONFIG_PPC_MERGE -+static int talitos_probe(struct of_device *ofdev, const struct of_device_id *match) -+#else -+static int talitos_probe(struct platform_device *pdev) -+#endif -+{ -+ struct talitos_softc *sc = NULL; -+ struct resource *r; -+#ifdef CONFIG_PPC_MERGE -+ struct device *device = &ofdev->dev; -+ struct device_node *np = ofdev->node; -+ const unsigned int *prop; -+ int err; -+ struct resource res; -+#endif -+ static int num_chips = 0; -+ int rc; -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ -+ sc = (struct talitos_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); -+ if (!sc) -+ return -ENOMEM; -+ memset(sc, 0, sizeof(*sc)); -+ -+ softc_device_init(sc, DRV_NAME, num_chips, talitos_methods); -+ -+ sc->sc_irq = -1; -+ sc->sc_cid = -1; -+#ifndef CONFIG_PPC_MERGE -+ sc->sc_dev = pdev; -+#endif -+ sc->sc_num = num_chips++; -+ -+#ifdef CONFIG_PPC_MERGE -+ dev_set_drvdata(device, sc); -+#else -+ platform_set_drvdata(sc->sc_dev, sc); -+#endif -+ -+ /* get the irq line */ -+#ifdef CONFIG_PPC_MERGE -+ err = of_address_to_resource(np, 0, &res); -+ if (err) -+ return -EINVAL; -+ r = &res; -+ -+ sc->sc_irq = irq_of_parse_and_map(np, 0); -+#else -+ /* get a pointer to the register memory */ -+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ -+ sc->sc_irq = platform_get_irq(pdev, 0); -+#endif -+ rc = request_irq(sc->sc_irq, talitos_intr, 0, -+ device_get_nameunit(sc->sc_cdev), sc); -+ if (rc) { -+ printk(KERN_ERR "%s: failed to hook irq %d\n", -+ device_get_nameunit(sc->sc_cdev), sc->sc_irq); -+ sc->sc_irq = -1; -+ goto out; -+ } -+ -+ sc->sc_base_addr = (ocf_iomem_t) ioremap(r->start, (r->end - r->start)); -+ if (!sc->sc_base_addr) { -+ printk(KERN_ERR "%s: failed to ioremap\n", -+ device_get_nameunit(sc->sc_cdev)); -+ goto out; -+ } -+ -+ /* figure out our SEC's properties and capabilities */ -+ sc->sc_chiprev = (u64)talitos_read(sc->sc_base_addr + TALITOS_ID) << 32 -+ | talitos_read(sc->sc_base_addr + TALITOS_ID_HI); -+ DPRINTF("sec id 0x%llx\n", sc->sc_chiprev); -+ -+#ifdef CONFIG_PPC_MERGE -+ /* get SEC properties from device tree, defaulting to SEC 2.0 */ -+ -+ prop = of_get_property(np, "num-channels", NULL); -+ sc->sc_num_channels = prop ? *prop : TALITOS_NCHANNELS_SEC_2_0; -+ -+ prop = of_get_property(np, "channel-fifo-len", NULL); -+ sc->sc_chfifo_len = prop ? *prop : TALITOS_CHFIFOLEN_SEC_2_0; -+ -+ prop = of_get_property(np, "exec-units-mask", NULL); -+ sc->sc_exec_units = prop ? *prop : TALITOS_HAS_EUS_SEC_2_0; -+ -+ prop = of_get_property(np, "descriptor-types-mask", NULL); -+ sc->sc_desc_types = prop ? *prop : TALITOS_HAS_DESCTYPES_SEC_2_0; -+#else -+ /* bulk should go away with openfirmware flat device tree support */ -+ if (sc->sc_chiprev & TALITOS_ID_SEC_2_0) { -+ sc->sc_num_channels = TALITOS_NCHANNELS_SEC_2_0; -+ sc->sc_chfifo_len = TALITOS_CHFIFOLEN_SEC_2_0; -+ sc->sc_exec_units = TALITOS_HAS_EUS_SEC_2_0; -+ sc->sc_desc_types = TALITOS_HAS_DESCTYPES_SEC_2_0; -+ } else { -+ printk(KERN_ERR "%s: failed to id device\n", -+ device_get_nameunit(sc->sc_cdev)); -+ goto out; -+ } -+#endif -+ -+ /* + 1 is for the meta-channel lock used by the channel scheduler */ -+ sc->sc_chnfifolock = (spinlock_t *) kmalloc( -+ (sc->sc_num_channels + 1) * sizeof(spinlock_t), GFP_KERNEL); -+ if (!sc->sc_chnfifolock) -+ goto out; -+ for (i = 0; i < sc->sc_num_channels + 1; i++) { -+ spin_lock_init(&sc->sc_chnfifolock[i]); -+ } -+ -+ sc->sc_chnlastalg = (int *) kmalloc( -+ sc->sc_num_channels * sizeof(int), GFP_KERNEL); -+ if (!sc->sc_chnlastalg) -+ goto out; -+ memset(sc->sc_chnlastalg, 0, sc->sc_num_channels * sizeof(int)); -+ -+ sc->sc_chnfifo = (struct desc_cryptop_pair **) kmalloc( -+ sc->sc_num_channels * sizeof(struct desc_cryptop_pair *), -+ GFP_KERNEL); -+ if (!sc->sc_chnfifo) -+ goto out; -+ for (i = 0; i < sc->sc_num_channels; i++) { -+ sc->sc_chnfifo[i] = (struct desc_cryptop_pair *) kmalloc( -+ sc->sc_chfifo_len * sizeof(struct desc_cryptop_pair), -+ GFP_KERNEL); -+ if (!sc->sc_chnfifo[i]) -+ goto out; -+ memset(sc->sc_chnfifo[i], 0, -+ sc->sc_chfifo_len * sizeof(struct desc_cryptop_pair)); -+ } -+ -+ /* reset and initialize the SEC h/w device */ -+ talitos_reset_device(sc); -+ talitos_init_device(sc); -+ -+ sc->sc_cid = crypto_get_driverid(softc_get_device(sc),CRYPTOCAP_F_HARDWARE); -+ if (sc->sc_cid < 0) { -+ printk(KERN_ERR "%s: could not get crypto driver id\n", -+ device_get_nameunit(sc->sc_cdev)); -+ goto out; -+ } -+ -+ /* register algorithms with the framework */ -+ printk("%s:", device_get_nameunit(sc->sc_cdev)); -+ -+ if (sc->sc_exec_units & TALITOS_HAS_EU_RNG) { -+ printk(" rng"); -+#ifdef CONFIG_OCF_RANDOMHARVEST -+ talitos_rng_init(sc); -+ crypto_rregister(sc->sc_cid, talitos_read_random, sc); -+#endif -+ } -+ if (sc->sc_exec_units & TALITOS_HAS_EU_DEU) { -+ printk(" des/3des"); -+ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); -+ } -+ if (sc->sc_exec_units & TALITOS_HAS_EU_AESU) { -+ printk(" aes"); -+ crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); -+ } -+ if (sc->sc_exec_units & TALITOS_HAS_EU_MDEU) { -+ printk(" md5"); -+ crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0); -+ /* HMAC support only with IPsec for now */ -+ crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); -+ printk(" sha1"); -+ crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0); -+ /* HMAC support only with IPsec for now */ -+ crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); -+ } -+ printk("\n"); -+ return 0; -+ -+out: -+#ifndef CONFIG_PPC_MERGE -+ talitos_remove(pdev); -+#endif -+ return -ENOMEM; -+} -+ -+#ifdef CONFIG_PPC_MERGE -+static int talitos_remove(struct of_device *ofdev) -+#else -+static int talitos_remove(struct platform_device *pdev) -+#endif -+{ -+#ifdef CONFIG_PPC_MERGE -+ struct talitos_softc *sc = dev_get_drvdata(&ofdev->dev); -+#else -+ struct talitos_softc *sc = platform_get_drvdata(pdev); -+#endif -+ int i; -+ -+ DPRINTF("%s()\n", __FUNCTION__); -+ if (sc->sc_cid >= 0) -+ crypto_unregister_all(sc->sc_cid); -+ if (sc->sc_chnfifo) { -+ for (i = 0; i < sc->sc_num_channels; i++) -+ if (sc->sc_chnfifo[i]) -+ kfree(sc->sc_chnfifo[i]); -+ kfree(sc->sc_chnfifo); -+ } -+ if (sc->sc_chnlastalg) -+ kfree(sc->sc_chnlastalg); -+ if (sc->sc_chnfifolock) -+ kfree(sc->sc_chnfifolock); -+ if (sc->sc_irq != -1) -+ free_irq(sc->sc_irq, sc); -+ if (sc->sc_base_addr) -+ iounmap((void *) sc->sc_base_addr); -+ kfree(sc); -+ return 0; -+} -+ -+#ifdef CONFIG_PPC_MERGE -+static struct of_device_id talitos_match[] = { -+ { -+ .type = "crypto", -+ .compatible = "talitos", -+ }, -+ {}, -+}; -+ -+MODULE_DEVICE_TABLE(of, talitos_match); -+ -+static struct of_platform_driver talitos_driver = { -+ .name = DRV_NAME, -+ .match_table = talitos_match, -+ .probe = talitos_probe, -+ .remove = talitos_remove, -+}; -+ -+static int __init talitos_init(void) -+{ -+ return of_register_platform_driver(&talitos_driver); -+} -+ -+static void __exit talitos_exit(void) -+{ -+ of_unregister_platform_driver(&talitos_driver); -+} -+#else -+/* Structure for a platform device driver */ -+static struct platform_driver talitos_driver = { -+ .probe = talitos_probe, -+ .remove = talitos_remove, -+ .driver = { -+ .name = "fsl-sec2", -+ } -+}; -+ -+static int __init talitos_init(void) -+{ -+ return platform_driver_register(&talitos_driver); -+} -+ -+static void __exit talitos_exit(void) -+{ -+ platform_driver_unregister(&talitos_driver); -+} -+#endif -+ -+module_init(talitos_init); -+module_exit(talitos_exit); -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_AUTHOR("kim.phillips@freescale.com"); -+MODULE_DESCRIPTION("OCF driver for Freescale SEC (talitos)"); -diff -Nur linux-3.0.4.orig/crypto/ocf/talitos/talitos_dev.h linux-3.0.4/crypto/ocf/talitos/talitos_dev.h ---- linux-3.0.4.orig/crypto/ocf/talitos/talitos_dev.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/talitos/talitos_dev.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,277 @@ -+/* -+ * Freescale SEC (talitos) device dependent data structures -+ * -+ * Copyright (c) 2006 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ */ -+ -+/* device ID register values */ -+#define TALITOS_ID_SEC_2_0 0x40 -+#define TALITOS_ID_SEC_2_1 0x40 /* cross ref with IP block revision reg */ -+ -+/* -+ * following num_channels, channel-fifo-depth, exec-unit-mask, and -+ * descriptor-types-mask are for forward-compatibility with openfirmware -+ * flat device trees -+ */ -+ -+/* -+ * num_channels : the number of channels available in each SEC version. -+ */ -+ -+/* n.b. this driver requires these values be a power of 2 */ -+#define TALITOS_NCHANNELS_SEC_1_0 4 -+#define TALITOS_NCHANNELS_SEC_1_2 1 -+#define TALITOS_NCHANNELS_SEC_2_0 4 -+#define TALITOS_NCHANNELS_SEC_2_01 4 -+#define TALITOS_NCHANNELS_SEC_2_1 4 -+#define TALITOS_NCHANNELS_SEC_2_4 4 -+ -+/* -+ * channel-fifo-depth : The number of descriptor -+ * pointers a channel fetch fifo can hold. -+ */ -+#define TALITOS_CHFIFOLEN_SEC_1_0 1 -+#define TALITOS_CHFIFOLEN_SEC_1_2 1 -+#define TALITOS_CHFIFOLEN_SEC_2_0 24 -+#define TALITOS_CHFIFOLEN_SEC_2_01 24 -+#define TALITOS_CHFIFOLEN_SEC_2_1 24 -+#define TALITOS_CHFIFOLEN_SEC_2_4 24 -+ -+/* -+ * exec-unit-mask : The bitmask representing what Execution Units (EUs) -+ * are available. EU information should be encoded following the SEC's -+ * EU_SEL0 bitfield documentation, i.e. as follows: -+ * -+ * bit 31 = set if SEC permits no-EU selection (should be always set) -+ * bit 30 = set if SEC has the ARC4 EU (AFEU) -+ * bit 29 = set if SEC has the des/3des EU (DEU) -+ * bit 28 = set if SEC has the message digest EU (MDEU) -+ * bit 27 = set if SEC has the random number generator EU (RNG) -+ * bit 26 = set if SEC has the public key EU (PKEU) -+ * bit 25 = set if SEC has the aes EU (AESU) -+ * bit 24 = set if SEC has the Kasumi EU (KEU) -+ * -+ */ -+#define TALITOS_HAS_EU_NONE (1<<0) -+#define TALITOS_HAS_EU_AFEU (1<<1) -+#define TALITOS_HAS_EU_DEU (1<<2) -+#define TALITOS_HAS_EU_MDEU (1<<3) -+#define TALITOS_HAS_EU_RNG (1<<4) -+#define TALITOS_HAS_EU_PKEU (1<<5) -+#define TALITOS_HAS_EU_AESU (1<<6) -+#define TALITOS_HAS_EU_KEU (1<<7) -+ -+/* the corresponding masks for each SEC version */ -+#define TALITOS_HAS_EUS_SEC_1_0 0x7f -+#define TALITOS_HAS_EUS_SEC_1_2 0x4d -+#define TALITOS_HAS_EUS_SEC_2_0 0x7f -+#define TALITOS_HAS_EUS_SEC_2_01 0x7f -+#define TALITOS_HAS_EUS_SEC_2_1 0xff -+#define TALITOS_HAS_EUS_SEC_2_4 0x7f -+ -+/* -+ * descriptor-types-mask : The bitmask representing what descriptors -+ * are available. Descriptor type information should be encoded -+ * following the SEC's Descriptor Header Dword DESC_TYPE field -+ * documentation, i.e. as follows: -+ * -+ * bit 0 = set if SEC supports the aesu_ctr_nonsnoop desc. type -+ * bit 1 = set if SEC supports the ipsec_esp descriptor type -+ * bit 2 = set if SEC supports the common_nonsnoop desc. type -+ * bit 3 = set if SEC supports the 802.11i AES ccmp desc. type -+ * bit 4 = set if SEC supports the hmac_snoop_no_afeu desc. type -+ * bit 5 = set if SEC supports the srtp descriptor type -+ * bit 6 = set if SEC supports the non_hmac_snoop_no_afeu desc.type -+ * bit 7 = set if SEC supports the pkeu_assemble descriptor type -+ * bit 8 = set if SEC supports the aesu_key_expand_output desc.type -+ * bit 9 = set if SEC supports the pkeu_ptmul descriptor type -+ * bit 10 = set if SEC supports the common_nonsnoop_afeu desc. type -+ * bit 11 = set if SEC supports the pkeu_ptadd_dbl descriptor type -+ * -+ * ..and so on and so forth. -+ */ -+#define TALITOS_HAS_DT_AESU_CTR_NONSNOOP (1<<0) -+#define TALITOS_HAS_DT_IPSEC_ESP (1<<1) -+#define TALITOS_HAS_DT_COMMON_NONSNOOP (1<<2) -+ -+/* the corresponding masks for each SEC version */ -+#define TALITOS_HAS_DESCTYPES_SEC_2_0 0x01010ebf -+#define TALITOS_HAS_DESCTYPES_SEC_2_1 0x012b0ebf -+ -+/* -+ * a TALITOS_xxx_HI address points to the low data bits (32-63) of the register -+ */ -+ -+/* global register offset addresses */ -+#define TALITOS_ID 0x1020 -+#define TALITOS_ID_HI 0x1024 -+#define TALITOS_MCR 0x1030 /* master control register */ -+#define TALITOS_MCR_HI 0x1038 /* master control register */ -+#define TALITOS_MCR_SWR 0x1 -+#define TALITOS_IMR 0x1008 /* interrupt mask register */ -+#define TALITOS_IMR_ALL 0x00010fff /* enable all interrupts mask */ -+#define TALITOS_IMR_ERRONLY 0x00010aaa /* enable error interrupts */ -+#define TALITOS_IMR_HI 0x100C /* interrupt mask register */ -+#define TALITOS_IMR_HI_ALL 0x00323333 /* enable all interrupts mask */ -+#define TALITOS_IMR_HI_ERRONLY 0x00222222 /* enable error interrupts */ -+#define TALITOS_ISR 0x1010 /* interrupt status register */ -+#define TALITOS_ISR_ERROR 0x00010faa /* errors mask */ -+#define TALITOS_ISR_DONE 0x00000055 /* channel(s) done mask */ -+#define TALITOS_ISR_HI 0x1014 /* interrupt status register */ -+#define TALITOS_ICR 0x1018 /* interrupt clear register */ -+#define TALITOS_ICR_HI 0x101C /* interrupt clear register */ -+ -+/* channel register address stride */ -+#define TALITOS_CH_OFFSET 0x100 -+ -+/* channel register offset addresses and bits */ -+#define TALITOS_CH_CCCR 0x1108 /* Crypto-Channel Config Register */ -+#define TALITOS_CH_CCCR_RESET 0x1 /* Channel Reset bit */ -+#define TALITOS_CH_CCCR_HI 0x110c /* Crypto-Channel Config Register */ -+#define TALITOS_CH_CCCR_HI_CDWE 0x10 /* Channel done writeback enable bit */ -+#define TALITOS_CH_CCCR_HI_NT 0x4 /* Notification type bit */ -+#define TALITOS_CH_CCCR_HI_CDIE 0x2 /* Channel Done Interrupt Enable bit */ -+#define TALITOS_CH_CCPSR 0x1110 /* Crypto-Channel Pointer Status Reg */ -+#define TALITOS_CH_CCPSR_HI 0x1114 /* Crypto-Channel Pointer Status Reg */ -+#define TALITOS_CH_FF 0x1148 /* Fetch FIFO */ -+#define TALITOS_CH_FF_HI 0x114c /* Fetch FIFO's FETCH_ADRS */ -+#define TALITOS_CH_CDPR 0x1140 /* Crypto-Channel Pointer Status Reg */ -+#define TALITOS_CH_CDPR_HI 0x1144 /* Crypto-Channel Pointer Status Reg */ -+#define TALITOS_CH_DESCBUF 0x1180 /* (thru 11bf) Crypto-Channel -+ * Descriptor Buffer (debug) */ -+ -+/* execution unit register offset addresses and bits */ -+#define TALITOS_DEUSR 0x2028 /* DEU status register */ -+#define TALITOS_DEUSR_HI 0x202c /* DEU status register */ -+#define TALITOS_DEUISR 0x2030 /* DEU interrupt status register */ -+#define TALITOS_DEUISR_HI 0x2034 /* DEU interrupt status register */ -+#define TALITOS_DEUICR 0x2038 /* DEU interrupt control register */ -+#define TALITOS_DEUICR_HI 0x203c /* DEU interrupt control register */ -+#define TALITOS_AESUISR 0x4030 /* AESU interrupt status register */ -+#define TALITOS_AESUISR_HI 0x4034 /* AESU interrupt status register */ -+#define TALITOS_AESUICR 0x4038 /* AESU interrupt control register */ -+#define TALITOS_AESUICR_HI 0x403c /* AESU interrupt control register */ -+#define TALITOS_MDEUISR 0x6030 /* MDEU interrupt status register */ -+#define TALITOS_MDEUISR_HI 0x6034 /* MDEU interrupt status register */ -+#define TALITOS_RNGSR 0xa028 /* RNG status register */ -+#define TALITOS_RNGSR_HI 0xa02c /* RNG status register */ -+#define TALITOS_RNGSR_HI_RD 0x1 /* RNG Reset done */ -+#define TALITOS_RNGSR_HI_OFL 0xff0000/* number of dwords in RNG output FIFO*/ -+#define TALITOS_RNGDSR 0xa010 /* RNG data size register */ -+#define TALITOS_RNGDSR_HI 0xa014 /* RNG data size register */ -+#define TALITOS_RNG_FIFO 0xa800 /* RNG FIFO - pool of random numbers */ -+#define TALITOS_RNGISR 0xa030 /* RNG Interrupt status register */ -+#define TALITOS_RNGISR_HI 0xa034 /* RNG Interrupt status register */ -+#define TALITOS_RNGRCR 0xa018 /* RNG Reset control register */ -+#define TALITOS_RNGRCR_HI 0xa01c /* RNG Reset control register */ -+#define TALITOS_RNGRCR_HI_SR 0x1 /* RNG RNGRCR:Software Reset */ -+ -+/* descriptor pointer entry */ -+struct talitos_desc_ptr { -+ u16 len; /* length */ -+ u8 extent; /* jump (to s/g link table) and extent */ -+ u8 res; /* reserved */ -+ u32 ptr; /* pointer */ -+}; -+ -+/* descriptor */ -+struct talitos_desc { -+ u32 hdr; /* header */ -+ u32 res; /* reserved */ -+ struct talitos_desc_ptr ptr[7]; /* ptr/len pair array */ -+}; -+ -+/* talitos descriptor header (hdr) bits */ -+ -+/* primary execution unit select */ -+#define TALITOS_SEL0_AFEU 0x10000000 -+#define TALITOS_SEL0_DEU 0x20000000 -+#define TALITOS_SEL0_MDEU 0x30000000 -+#define TALITOS_SEL0_RNG 0x40000000 -+#define TALITOS_SEL0_PKEU 0x50000000 -+#define TALITOS_SEL0_AESU 0x60000000 -+ -+/* primary execution unit mode (MODE0) and derivatives */ -+#define TALITOS_MODE0_AESU_CBC 0x00200000 -+#define TALITOS_MODE0_AESU_ENC 0x00100000 -+#define TALITOS_MODE0_DEU_CBC 0x00400000 -+#define TALITOS_MODE0_DEU_3DES 0x00200000 -+#define TALITOS_MODE0_DEU_ENC 0x00100000 -+#define TALITOS_MODE0_MDEU_INIT 0x01000000 /* init starting regs */ -+#define TALITOS_MODE0_MDEU_HMAC 0x00800000 -+#define TALITOS_MODE0_MDEU_PAD 0x00400000 /* PD */ -+#define TALITOS_MODE0_MDEU_MD5 0x00200000 -+#define TALITOS_MODE0_MDEU_SHA256 0x00100000 -+#define TALITOS_MODE0_MDEU_SHA1 0x00000000 /* SHA-160 */ -+#define TALITOS_MODE0_MDEU_MD5_HMAC \ -+ (TALITOS_MODE0_MDEU_MD5 | TALITOS_MODE0_MDEU_HMAC) -+#define TALITOS_MODE0_MDEU_SHA256_HMAC \ -+ (TALITOS_MODE0_MDEU_SHA256 | TALITOS_MODE0_MDEU_HMAC) -+#define TALITOS_MODE0_MDEU_SHA1_HMAC \ -+ (TALITOS_MODE0_MDEU_SHA1 | TALITOS_MODE0_MDEU_HMAC) -+ -+/* secondary execution unit select (SEL1) */ -+/* it's MDEU or nothing */ -+#define TALITOS_SEL1_MDEU 0x00030000 -+ -+/* secondary execution unit mode (MODE1) and derivatives */ -+#define TALITOS_MODE1_MDEU_INIT 0x00001000 /* init starting regs */ -+#define TALITOS_MODE1_MDEU_HMAC 0x00000800 -+#define TALITOS_MODE1_MDEU_PAD 0x00000400 /* PD */ -+#define TALITOS_MODE1_MDEU_MD5 0x00000200 -+#define TALITOS_MODE1_MDEU_SHA256 0x00000100 -+#define TALITOS_MODE1_MDEU_SHA1 0x00000000 /* SHA-160 */ -+#define TALITOS_MODE1_MDEU_MD5_HMAC \ -+ (TALITOS_MODE1_MDEU_MD5 | TALITOS_MODE1_MDEU_HMAC) -+#define TALITOS_MODE1_MDEU_SHA256_HMAC \ -+ (TALITOS_MODE1_MDEU_SHA256 | TALITOS_MODE1_MDEU_HMAC) -+#define TALITOS_MODE1_MDEU_SHA1_HMAC \ -+ (TALITOS_MODE1_MDEU_SHA1 | TALITOS_MODE1_MDEU_HMAC) -+ -+/* direction of overall data flow (DIR) */ -+#define TALITOS_DIR_OUTBOUND 0x00000000 -+#define TALITOS_DIR_INBOUND 0x00000002 -+ -+/* done notification (DN) */ -+#define TALITOS_DONE_NOTIFY 0x00000001 -+ -+/* descriptor types */ -+/* odd numbers here are valid on SEC2 and greater only (e.g. ipsec_esp) */ -+#define TD_TYPE_AESU_CTR_NONSNOOP (0 << 3) -+#define TD_TYPE_IPSEC_ESP (1 << 3) -+#define TD_TYPE_COMMON_NONSNOOP_NO_AFEU (2 << 3) -+#define TD_TYPE_HMAC_SNOOP_NO_AFEU (4 << 3) -+ -+#define TALITOS_HDR_DONE_BITS 0xff000000 -+ -+#define DPRINTF(a...) do { \ -+ if (debug) { \ -+ printk("%s: ", sc ? \ -+ device_get_nameunit(sc->sc_cdev) : "talitos"); \ -+ printk(a); \ -+ } \ -+ } while (0) -diff -Nur linux-3.0.4.orig/crypto/ocf/talitos/talitos_soft.h linux-3.0.4/crypto/ocf/talitos/talitos_soft.h ---- linux-3.0.4.orig/crypto/ocf/talitos/talitos_soft.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/talitos/talitos_soft.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,76 @@ -+/* -+ * Freescale SEC data structures for integration with ocf-linux -+ * -+ * Copyright (c) 2006 Freescale Semiconductor, Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/* -+ * paired descriptor and associated crypto operation -+ */ -+struct desc_cryptop_pair { -+ struct talitos_desc cf_desc; /* descriptor ptr */ -+ struct cryptop *cf_crp; /* cryptop ptr */ -+}; -+ -+/* -+ * Holds data specific to a single talitos device. -+ */ -+struct talitos_softc { -+ softc_device_decl sc_cdev; -+ struct platform_device *sc_dev; /* device backpointer */ -+ ocf_iomem_t sc_base_addr; -+ int sc_irq; -+ int sc_num; /* if we have multiple chips */ -+ int32_t sc_cid; /* crypto tag */ -+ u64 sc_chiprev; /* major/minor chip revision */ -+ int sc_nsessions; -+ struct talitos_session *sc_sessions; -+ int sc_num_channels;/* number of crypto channels */ -+ int sc_chfifo_len; /* channel fetch fifo len */ -+ int sc_exec_units; /* execution units mask */ -+ int sc_desc_types; /* descriptor types mask */ -+ /* -+ * mutual exclusion for intra-channel resources, e.g. fetch fifos -+ * the last entry is a meta-channel lock used by the channel scheduler -+ */ -+ spinlock_t *sc_chnfifolock; -+ /* sc_chnlastalgo contains last algorithm for that channel */ -+ int *sc_chnlastalg; -+ /* sc_chnfifo holds pending descriptor--crypto operation pairs */ -+ struct desc_cryptop_pair **sc_chnfifo; -+}; -+ -+struct talitos_session { -+ u_int32_t ses_used; -+ u_int32_t ses_klen; /* key length in bits */ -+ u_int32_t ses_key[8]; /* DES/3DES/AES key */ -+ u_int32_t ses_hmac[5]; /* hmac inner state */ -+ u_int32_t ses_hmac_len; /* hmac length */ -+ u_int32_t ses_mlen; /* desired hash result len (12=ipsec or 16) */ -+}; -+ -+#define TALITOS_SESSION(sid) ((sid) & 0x0fffffff) -+#define TALITOS_SID(crd, sesn) (((crd) << 28) | ((sesn) & 0x0fffffff)) -diff -Nur linux-3.0.4.orig/crypto/ocf/ubsec_ssb/Makefile linux-3.0.4/crypto/ocf/ubsec_ssb/Makefile ---- linux-3.0.4.orig/crypto/ocf/ubsec_ssb/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/ubsec_ssb/Makefile 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,12 @@ -+# for SGlinux builds -+-include $(ROOTDIR)/modules/.config -+ -+obj-$(CONFIG_OCF_UBSEC_SSB) += ubsec_ssb.o -+ -+obj ?= . -+EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ -+ -+ifdef TOPDIR -+-include $(TOPDIR)/Rules.make -+endif -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/ubsec_ssb/bsdqueue.h linux-3.0.4/crypto/ocf/ubsec_ssb/bsdqueue.h ---- linux-3.0.4.orig/crypto/ocf/ubsec_ssb/bsdqueue.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/ubsec_ssb/bsdqueue.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,527 @@ -+/* $OpenBSD: queue.h,v 1.32 2007/04/30 18:42:34 pedro Exp $ */ -+/* $NetBSD: queue.h,v 1.11 1996/05/16 05:17:14 mycroft Exp $ */ -+ -+/* -+ * Copyright (c) 1991, 1993 -+ * The Regents of the University of California. All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. Neither the name of the University nor the names of its contributors -+ * may be used to endorse or promote products derived from this software -+ * without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE -+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -+ * SUCH DAMAGE. -+ * -+ * @(#)queue.h 8.5 (Berkeley) 8/20/94 -+ */ -+ -+#ifndef _BSD_SYS_QUEUE_H_ -+#define _BSD_SYS_QUEUE_H_ -+ -+/* -+ * This file defines five types of data structures: singly-linked lists, -+ * lists, simple queues, tail queues, and circular queues. -+ * -+ * -+ * A singly-linked list is headed by a single forward pointer. The elements -+ * are singly linked for minimum space and pointer manipulation overhead at -+ * the expense of O(n) removal for arbitrary elements. New elements can be -+ * added to the list after an existing element or at the head of the list. -+ * Elements being removed from the head of the list should use the explicit -+ * macro for this purpose for optimum efficiency. A singly-linked list may -+ * only be traversed in the forward direction. Singly-linked lists are ideal -+ * for applications with large datasets and few or no removals or for -+ * implementing a LIFO queue. -+ * -+ * A list is headed by a single forward pointer (or an array of forward -+ * pointers for a hash table header). The elements are doubly linked -+ * so that an arbitrary element can be removed without a need to -+ * traverse the list. New elements can be added to the list before -+ * or after an existing element or at the head of the list. A list -+ * may only be traversed in the forward direction. -+ * -+ * A simple queue is headed by a pair of pointers, one the head of the -+ * list and the other to the tail of the list. The elements are singly -+ * linked to save space, so elements can only be removed from the -+ * head of the list. New elements can be added to the list before or after -+ * an existing element, at the head of the list, or at the end of the -+ * list. A simple queue may only be traversed in the forward direction. -+ * -+ * A tail queue is headed by a pair of pointers, one to the head of the -+ * list and the other to the tail of the list. The elements are doubly -+ * linked so that an arbitrary element can be removed without a need to -+ * traverse the list. New elements can be added to the list before or -+ * after an existing element, at the head of the list, or at the end of -+ * the list. A tail queue may be traversed in either direction. -+ * -+ * A circle queue is headed by a pair of pointers, one to the head of the -+ * list and the other to the tail of the list. The elements are doubly -+ * linked so that an arbitrary element can be removed without a need to -+ * traverse the list. New elements can be added to the list before or after -+ * an existing element, at the head of the list, or at the end of the list. -+ * A circle queue may be traversed in either direction, but has a more -+ * complex end of list detection. -+ * -+ * For details on the use of these macros, see the queue(3) manual page. -+ */ -+ -+#if defined(QUEUE_MACRO_DEBUG) || (defined(_KERNEL) && defined(DIAGNOSTIC)) -+#define _Q_INVALIDATE(a) (a) = ((void *)-1) -+#else -+#define _Q_INVALIDATE(a) -+#endif -+ -+/* -+ * Singly-linked List definitions. -+ */ -+#define BSD_SLIST_HEAD(name, type) \ -+struct name { \ -+ struct type *slh_first; /* first element */ \ -+} -+ -+#define BSD_SLIST_HEAD_INITIALIZER(head) \ -+ { NULL } -+ -+#define BSD_SLIST_ENTRY(type) \ -+struct { \ -+ struct type *sle_next; /* next element */ \ -+} -+ -+/* -+ * Singly-linked List access methods. -+ */ -+#define BSD_SLIST_FIRST(head) ((head)->slh_first) -+#define BSD_SLIST_END(head) NULL -+#define BSD_SLIST_EMPTY(head) (BSD_SLIST_FIRST(head) == BSD_SLIST_END(head)) -+#define BSD_SLIST_NEXT(elm, field) ((elm)->field.sle_next) -+ -+#define BSD_SLIST_FOREACH(var, head, field) \ -+ for((var) = BSD_SLIST_FIRST(head); \ -+ (var) != BSD_SLIST_END(head); \ -+ (var) = BSD_SLIST_NEXT(var, field)) -+ -+#define BSD_SLIST_FOREACH_PREVPTR(var, varp, head, field) \ -+ for ((varp) = &BSD_SLIST_FIRST((head)); \ -+ ((var) = *(varp)) != BSD_SLIST_END(head); \ -+ (varp) = &BSD_SLIST_NEXT((var), field)) -+ -+/* -+ * Singly-linked List functions. -+ */ -+#define BSD_SLIST_INIT(head) { \ -+ BSD_SLIST_FIRST(head) = BSD_SLIST_END(head); \ -+} -+ -+#define BSD_SLIST_INSERT_AFTER(slistelm, elm, field) do { \ -+ (elm)->field.sle_next = (slistelm)->field.sle_next; \ -+ (slistelm)->field.sle_next = (elm); \ -+} while (0) -+ -+#define BSD_SLIST_INSERT_HEAD(head, elm, field) do { \ -+ (elm)->field.sle_next = (head)->slh_first; \ -+ (head)->slh_first = (elm); \ -+} while (0) -+ -+#define BSD_SLIST_REMOVE_NEXT(head, elm, field) do { \ -+ (elm)->field.sle_next = (elm)->field.sle_next->field.sle_next; \ -+} while (0) -+ -+#define BSD_SLIST_REMOVE_HEAD(head, field) do { \ -+ (head)->slh_first = (head)->slh_first->field.sle_next; \ -+} while (0) -+ -+#define BSD_SLIST_REMOVE(head, elm, type, field) do { \ -+ if ((head)->slh_first == (elm)) { \ -+ BSD_SLIST_REMOVE_HEAD((head), field); \ -+ } else { \ -+ struct type *curelm = (head)->slh_first; \ -+ \ -+ while (curelm->field.sle_next != (elm)) \ -+ curelm = curelm->field.sle_next; \ -+ curelm->field.sle_next = \ -+ curelm->field.sle_next->field.sle_next; \ -+ _Q_INVALIDATE((elm)->field.sle_next); \ -+ } \ -+} while (0) -+ -+/* -+ * List definitions. -+ */ -+#define BSD_LIST_HEAD(name, type) \ -+struct name { \ -+ struct type *lh_first; /* first element */ \ -+} -+ -+#define BSD_LIST_HEAD_INITIALIZER(head) \ -+ { NULL } -+ -+#define BSD_LIST_ENTRY(type) \ -+struct { \ -+ struct type *le_next; /* next element */ \ -+ struct type **le_prev; /* address of previous next element */ \ -+} -+ -+/* -+ * List access methods -+ */ -+#define BSD_LIST_FIRST(head) ((head)->lh_first) -+#define BSD_LIST_END(head) NULL -+#define BSD_LIST_EMPTY(head) (BSD_LIST_FIRST(head) == BSD_LIST_END(head)) -+#define BSD_LIST_NEXT(elm, field) ((elm)->field.le_next) -+ -+#define BSD_LIST_FOREACH(var, head, field) \ -+ for((var) = BSD_LIST_FIRST(head); \ -+ (var)!= BSD_LIST_END(head); \ -+ (var) = BSD_LIST_NEXT(var, field)) -+ -+/* -+ * List functions. -+ */ -+#define BSD_LIST_INIT(head) do { \ -+ BSD_LIST_FIRST(head) = BSD_LIST_END(head); \ -+} while (0) -+ -+#define BSD_LIST_INSERT_AFTER(listelm, elm, field) do { \ -+ if (((elm)->field.le_next = (listelm)->field.le_next) != NULL) \ -+ (listelm)->field.le_next->field.le_prev = \ -+ &(elm)->field.le_next; \ -+ (listelm)->field.le_next = (elm); \ -+ (elm)->field.le_prev = &(listelm)->field.le_next; \ -+} while (0) -+ -+#define BSD_LIST_INSERT_BEFORE(listelm, elm, field) do { \ -+ (elm)->field.le_prev = (listelm)->field.le_prev; \ -+ (elm)->field.le_next = (listelm); \ -+ *(listelm)->field.le_prev = (elm); \ -+ (listelm)->field.le_prev = &(elm)->field.le_next; \ -+} while (0) -+ -+#define BSD_LIST_INSERT_HEAD(head, elm, field) do { \ -+ if (((elm)->field.le_next = (head)->lh_first) != NULL) \ -+ (head)->lh_first->field.le_prev = &(elm)->field.le_next;\ -+ (head)->lh_first = (elm); \ -+ (elm)->field.le_prev = &(head)->lh_first; \ -+} while (0) -+ -+#define BSD_LIST_REMOVE(elm, field) do { \ -+ if ((elm)->field.le_next != NULL) \ -+ (elm)->field.le_next->field.le_prev = \ -+ (elm)->field.le_prev; \ -+ *(elm)->field.le_prev = (elm)->field.le_next; \ -+ _Q_INVALIDATE((elm)->field.le_prev); \ -+ _Q_INVALIDATE((elm)->field.le_next); \ -+} while (0) -+ -+#define BSD_LIST_REPLACE(elm, elm2, field) do { \ -+ if (((elm2)->field.le_next = (elm)->field.le_next) != NULL) \ -+ (elm2)->field.le_next->field.le_prev = \ -+ &(elm2)->field.le_next; \ -+ (elm2)->field.le_prev = (elm)->field.le_prev; \ -+ *(elm2)->field.le_prev = (elm2); \ -+ _Q_INVALIDATE((elm)->field.le_prev); \ -+ _Q_INVALIDATE((elm)->field.le_next); \ -+} while (0) -+ -+/* -+ * Simple queue definitions. -+ */ -+#define BSD_SIMPLEQ_HEAD(name, type) \ -+struct name { \ -+ struct type *sqh_first; /* first element */ \ -+ struct type **sqh_last; /* addr of last next element */ \ -+} -+ -+#define BSD_SIMPLEQ_HEAD_INITIALIZER(head) \ -+ { NULL, &(head).sqh_first } -+ -+#define BSD_SIMPLEQ_ENTRY(type) \ -+struct { \ -+ struct type *sqe_next; /* next element */ \ -+} -+ -+/* -+ * Simple queue access methods. -+ */ -+#define BSD_SIMPLEQ_FIRST(head) ((head)->sqh_first) -+#define BSD_SIMPLEQ_END(head) NULL -+#define BSD_SIMPLEQ_EMPTY(head) (BSD_SIMPLEQ_FIRST(head) == BSD_SIMPLEQ_END(head)) -+#define BSD_SIMPLEQ_NEXT(elm, field) ((elm)->field.sqe_next) -+ -+#define BSD_SIMPLEQ_FOREACH(var, head, field) \ -+ for((var) = BSD_SIMPLEQ_FIRST(head); \ -+ (var) != BSD_SIMPLEQ_END(head); \ -+ (var) = BSD_SIMPLEQ_NEXT(var, field)) -+ -+/* -+ * Simple queue functions. -+ */ -+#define BSD_SIMPLEQ_INIT(head) do { \ -+ (head)->sqh_first = NULL; \ -+ (head)->sqh_last = &(head)->sqh_first; \ -+} while (0) -+ -+#define BSD_SIMPLEQ_INSERT_HEAD(head, elm, field) do { \ -+ if (((elm)->field.sqe_next = (head)->sqh_first) == NULL) \ -+ (head)->sqh_last = &(elm)->field.sqe_next; \ -+ (head)->sqh_first = (elm); \ -+} while (0) -+ -+#define BSD_SIMPLEQ_INSERT_TAIL(head, elm, field) do { \ -+ (elm)->field.sqe_next = NULL; \ -+ *(head)->sqh_last = (elm); \ -+ (head)->sqh_last = &(elm)->field.sqe_next; \ -+} while (0) -+ -+#define BSD_SIMPLEQ_INSERT_AFTER(head, listelm, elm, field) do { \ -+ if (((elm)->field.sqe_next = (listelm)->field.sqe_next) == NULL)\ -+ (head)->sqh_last = &(elm)->field.sqe_next; \ -+ (listelm)->field.sqe_next = (elm); \ -+} while (0) -+ -+#define BSD_SIMPLEQ_REMOVE_HEAD(head, field) do { \ -+ if (((head)->sqh_first = (head)->sqh_first->field.sqe_next) == NULL) \ -+ (head)->sqh_last = &(head)->sqh_first; \ -+} while (0) -+ -+/* -+ * Tail queue definitions. -+ */ -+#define BSD_TAILQ_HEAD(name, type) \ -+struct name { \ -+ struct type *tqh_first; /* first element */ \ -+ struct type **tqh_last; /* addr of last next element */ \ -+} -+ -+#define BSD_TAILQ_HEAD_INITIALIZER(head) \ -+ { NULL, &(head).tqh_first } -+ -+#define BSD_TAILQ_ENTRY(type) \ -+struct { \ -+ struct type *tqe_next; /* next element */ \ -+ struct type **tqe_prev; /* address of previous next element */ \ -+} -+ -+/* -+ * tail queue access methods -+ */ -+#define BSD_TAILQ_FIRST(head) ((head)->tqh_first) -+#define BSD_TAILQ_END(head) NULL -+#define BSD_TAILQ_NEXT(elm, field) ((elm)->field.tqe_next) -+#define BSD_TAILQ_LAST(head, headname) \ -+ (*(((struct headname *)((head)->tqh_last))->tqh_last)) -+/* XXX */ -+#define BSD_TAILQ_PREV(elm, headname, field) \ -+ (*(((struct headname *)((elm)->field.tqe_prev))->tqh_last)) -+#define BSD_TAILQ_EMPTY(head) \ -+ (BSD_TAILQ_FIRST(head) == BSD_TAILQ_END(head)) -+ -+#define BSD_TAILQ_FOREACH(var, head, field) \ -+ for((var) = BSD_TAILQ_FIRST(head); \ -+ (var) != BSD_TAILQ_END(head); \ -+ (var) = BSD_TAILQ_NEXT(var, field)) -+ -+#define BSD_TAILQ_FOREACH_REVERSE(var, head, headname, field) \ -+ for((var) = BSD_TAILQ_LAST(head, headname); \ -+ (var) != BSD_TAILQ_END(head); \ -+ (var) = BSD_TAILQ_PREV(var, headname, field)) -+ -+/* -+ * Tail queue functions. -+ */ -+#define BSD_TAILQ_INIT(head) do { \ -+ (head)->tqh_first = NULL; \ -+ (head)->tqh_last = &(head)->tqh_first; \ -+} while (0) -+ -+#define BSD_TAILQ_INSERT_HEAD(head, elm, field) do { \ -+ if (((elm)->field.tqe_next = (head)->tqh_first) != NULL) \ -+ (head)->tqh_first->field.tqe_prev = \ -+ &(elm)->field.tqe_next; \ -+ else \ -+ (head)->tqh_last = &(elm)->field.tqe_next; \ -+ (head)->tqh_first = (elm); \ -+ (elm)->field.tqe_prev = &(head)->tqh_first; \ -+} while (0) -+ -+#define BSD_TAILQ_INSERT_TAIL(head, elm, field) do { \ -+ (elm)->field.tqe_next = NULL; \ -+ (elm)->field.tqe_prev = (head)->tqh_last; \ -+ *(head)->tqh_last = (elm); \ -+ (head)->tqh_last = &(elm)->field.tqe_next; \ -+} while (0) -+ -+#define BSD_TAILQ_INSERT_AFTER(head, listelm, elm, field) do { \ -+ if (((elm)->field.tqe_next = (listelm)->field.tqe_next) != NULL)\ -+ (elm)->field.tqe_next->field.tqe_prev = \ -+ &(elm)->field.tqe_next; \ -+ else \ -+ (head)->tqh_last = &(elm)->field.tqe_next; \ -+ (listelm)->field.tqe_next = (elm); \ -+ (elm)->field.tqe_prev = &(listelm)->field.tqe_next; \ -+} while (0) -+ -+#define BSD_TAILQ_INSERT_BEFORE(listelm, elm, field) do { \ -+ (elm)->field.tqe_prev = (listelm)->field.tqe_prev; \ -+ (elm)->field.tqe_next = (listelm); \ -+ *(listelm)->field.tqe_prev = (elm); \ -+ (listelm)->field.tqe_prev = &(elm)->field.tqe_next; \ -+} while (0) -+ -+#define BSD_TAILQ_REMOVE(head, elm, field) do { \ -+ if (((elm)->field.tqe_next) != NULL) \ -+ (elm)->field.tqe_next->field.tqe_prev = \ -+ (elm)->field.tqe_prev; \ -+ else \ -+ (head)->tqh_last = (elm)->field.tqe_prev; \ -+ *(elm)->field.tqe_prev = (elm)->field.tqe_next; \ -+ _Q_INVALIDATE((elm)->field.tqe_prev); \ -+ _Q_INVALIDATE((elm)->field.tqe_next); \ -+} while (0) -+ -+#define BSD_TAILQ_REPLACE(head, elm, elm2, field) do { \ -+ if (((elm2)->field.tqe_next = (elm)->field.tqe_next) != NULL) \ -+ (elm2)->field.tqe_next->field.tqe_prev = \ -+ &(elm2)->field.tqe_next; \ -+ else \ -+ (head)->tqh_last = &(elm2)->field.tqe_next; \ -+ (elm2)->field.tqe_prev = (elm)->field.tqe_prev; \ -+ *(elm2)->field.tqe_prev = (elm2); \ -+ _Q_INVALIDATE((elm)->field.tqe_prev); \ -+ _Q_INVALIDATE((elm)->field.tqe_next); \ -+} while (0) -+ -+/* -+ * Circular queue definitions. -+ */ -+#define BSD_CIRCLEQ_HEAD(name, type) \ -+struct name { \ -+ struct type *cqh_first; /* first element */ \ -+ struct type *cqh_last; /* last element */ \ -+} -+ -+#define BSD_CIRCLEQ_HEAD_INITIALIZER(head) \ -+ { BSD_CIRCLEQ_END(&head), BSD_CIRCLEQ_END(&head) } -+ -+#define BSD_CIRCLEQ_ENTRY(type) \ -+struct { \ -+ struct type *cqe_next; /* next element */ \ -+ struct type *cqe_prev; /* previous element */ \ -+} -+ -+/* -+ * Circular queue access methods -+ */ -+#define BSD_CIRCLEQ_FIRST(head) ((head)->cqh_first) -+#define BSD_CIRCLEQ_LAST(head) ((head)->cqh_last) -+#define BSD_CIRCLEQ_END(head) ((void *)(head)) -+#define BSD_CIRCLEQ_NEXT(elm, field) ((elm)->field.cqe_next) -+#define BSD_CIRCLEQ_PREV(elm, field) ((elm)->field.cqe_prev) -+#define BSD_CIRCLEQ_EMPTY(head) \ -+ (BSD_CIRCLEQ_FIRST(head) == BSD_CIRCLEQ_END(head)) -+ -+#define BSD_CIRCLEQ_FOREACH(var, head, field) \ -+ for((var) = BSD_CIRCLEQ_FIRST(head); \ -+ (var) != BSD_CIRCLEQ_END(head); \ -+ (var) = BSD_CIRCLEQ_NEXT(var, field)) -+ -+#define BSD_CIRCLEQ_FOREACH_REVERSE(var, head, field) \ -+ for((var) = BSD_CIRCLEQ_LAST(head); \ -+ (var) != BSD_CIRCLEQ_END(head); \ -+ (var) = BSD_CIRCLEQ_PREV(var, field)) -+ -+/* -+ * Circular queue functions. -+ */ -+#define BSD_CIRCLEQ_INIT(head) do { \ -+ (head)->cqh_first = BSD_CIRCLEQ_END(head); \ -+ (head)->cqh_last = BSD_CIRCLEQ_END(head); \ -+} while (0) -+ -+#define BSD_CIRCLEQ_INSERT_AFTER(head, listelm, elm, field) do { \ -+ (elm)->field.cqe_next = (listelm)->field.cqe_next; \ -+ (elm)->field.cqe_prev = (listelm); \ -+ if ((listelm)->field.cqe_next == BSD_CIRCLEQ_END(head)) \ -+ (head)->cqh_last = (elm); \ -+ else \ -+ (listelm)->field.cqe_next->field.cqe_prev = (elm); \ -+ (listelm)->field.cqe_next = (elm); \ -+} while (0) -+ -+#define BSD_CIRCLEQ_INSERT_BEFORE(head, listelm, elm, field) do { \ -+ (elm)->field.cqe_next = (listelm); \ -+ (elm)->field.cqe_prev = (listelm)->field.cqe_prev; \ -+ if ((listelm)->field.cqe_prev == BSD_CIRCLEQ_END(head)) \ -+ (head)->cqh_first = (elm); \ -+ else \ -+ (listelm)->field.cqe_prev->field.cqe_next = (elm); \ -+ (listelm)->field.cqe_prev = (elm); \ -+} while (0) -+ -+#define BSD_CIRCLEQ_INSERT_HEAD(head, elm, field) do { \ -+ (elm)->field.cqe_next = (head)->cqh_first; \ -+ (elm)->field.cqe_prev = BSD_CIRCLEQ_END(head); \ -+ if ((head)->cqh_last == BSD_CIRCLEQ_END(head)) \ -+ (head)->cqh_last = (elm); \ -+ else \ -+ (head)->cqh_first->field.cqe_prev = (elm); \ -+ (head)->cqh_first = (elm); \ -+} while (0) -+ -+#define BSD_CIRCLEQ_INSERT_TAIL(head, elm, field) do { \ -+ (elm)->field.cqe_next = BSD_CIRCLEQ_END(head); \ -+ (elm)->field.cqe_prev = (head)->cqh_last; \ -+ if ((head)->cqh_first == BSD_CIRCLEQ_END(head)) \ -+ (head)->cqh_first = (elm); \ -+ else \ -+ (head)->cqh_last->field.cqe_next = (elm); \ -+ (head)->cqh_last = (elm); \ -+} while (0) -+ -+#define BSD_CIRCLEQ_REMOVE(head, elm, field) do { \ -+ if ((elm)->field.cqe_next == BSD_CIRCLEQ_END(head)) \ -+ (head)->cqh_last = (elm)->field.cqe_prev; \ -+ else \ -+ (elm)->field.cqe_next->field.cqe_prev = \ -+ (elm)->field.cqe_prev; \ -+ if ((elm)->field.cqe_prev == BSD_CIRCLEQ_END(head)) \ -+ (head)->cqh_first = (elm)->field.cqe_next; \ -+ else \ -+ (elm)->field.cqe_prev->field.cqe_next = \ -+ (elm)->field.cqe_next; \ -+ _Q_INVALIDATE((elm)->field.cqe_prev); \ -+ _Q_INVALIDATE((elm)->field.cqe_next); \ -+} while (0) -+ -+#define BSD_CIRCLEQ_REPLACE(head, elm, elm2, field) do { \ -+ if (((elm2)->field.cqe_next = (elm)->field.cqe_next) == \ -+ BSD_CIRCLEQ_END(head)) \ -+ (head).cqh_last = (elm2); \ -+ else \ -+ (elm2)->field.cqe_next->field.cqe_prev = (elm2); \ -+ if (((elm2)->field.cqe_prev = (elm)->field.cqe_prev) == \ -+ BSD_CIRCLEQ_END(head)) \ -+ (head).cqh_first = (elm2); \ -+ else \ -+ (elm2)->field.cqe_prev->field.cqe_next = (elm2); \ -+ _Q_INVALIDATE((elm)->field.cqe_prev); \ -+ _Q_INVALIDATE((elm)->field.cqe_next); \ -+} while (0) -+ -+#endif /* !_BSD_SYS_QUEUE_H_ */ -diff -Nur linux-3.0.4.orig/crypto/ocf/ubsec_ssb/ubsec_ssb.c linux-3.0.4/crypto/ocf/ubsec_ssb/ubsec_ssb.c ---- linux-3.0.4.orig/crypto/ocf/ubsec_ssb/ubsec_ssb.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/ubsec_ssb/ubsec_ssb.c 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,2220 @@ -+ -+/* -+ * Copyright (c) 2008 Daniel Mueller (daniel@danm.de) -+ * Copyright (c) 2007 David McCullough (david_mccullough@securecomputing.com) -+ * Copyright (c) 2000 Jason L. Wright (jason@thought.net) -+ * Copyright (c) 2000 Theo de Raadt (deraadt@openbsd.org) -+ * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com) -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored in part by the Defense Advanced Research Projects -+ * Agency (DARPA) and Air Force Research Laboratory, Air Force -+ * Materiel Command, USAF, under agreement number F30602-01-2-0537. -+ * -+ */ -+#undef UBSEC_DEBUG -+#undef UBSEC_VERBOSE_DEBUG -+ -+#ifdef UBSEC_VERBOSE_DEBUG -+#define UBSEC_DEBUG -+#endif -+ -+/* -+ * uBsec BCM5365 hardware crypto accelerator -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+/* -+ * BSD queue -+ */ -+//#include "bsdqueue.h" -+ -+/* -+ * OCF -+ */ -+#include -+#include -+ -+#define HMAC_HACK 1 -+ -+#define HMAC_HACK 1 -+#ifdef HMAC_HACK -+#include -+#include -+#include -+#include -+#include -+#endif -+ -+#include "bsdqueue.h" -+#include "ubsecreg.h" -+#include "ubsecvar.h" -+ -+#define DRV_MODULE_NAME "ubsec_ssb" -+#define PFX DRV_MODULE_NAME ": " -+#define DRV_MODULE_VERSION "0.02" -+#define DRV_MODULE_RELDATE "Feb 21, 2009" -+ -+#if 1 -+#define DPRINTF(a...) \ -+ if (debug) \ -+ { \ -+ printk(DRV_MODULE_NAME ": " a); \ -+ } -+#else -+#define DPRINTF(a...) -+#endif -+ -+/* -+ * Prototypes -+ */ -+static irqreturn_t ubsec_ssb_isr(int, void *, struct pt_regs *); -+static int __devinit ubsec_ssb_probe(struct ssb_device *sdev, -+ const struct ssb_device_id *ent); -+static void __devexit ubsec_ssb_remove(struct ssb_device *sdev); -+int ubsec_attach(struct ssb_device *sdev, const struct ssb_device_id *ent, -+ struct device *self); -+static void ubsec_setup_mackey(struct ubsec_session *ses, int algo, -+ caddr_t key, int klen); -+static int dma_map_skb(struct ubsec_softc *sc, -+ struct ubsec_dma_alloc* q_map, struct sk_buff *skb, int *mlen); -+static int dma_map_uio(struct ubsec_softc *sc, -+ struct ubsec_dma_alloc *q_map, struct uio *uio, int *mlen); -+static void dma_unmap(struct ubsec_softc *sc, -+ struct ubsec_dma_alloc *q_map, int mlen); -+static int ubsec_dmamap_aligned(struct ubsec_softc *sc, -+ const struct ubsec_dma_alloc *q_map, int mlen); -+ -+#ifdef UBSEC_DEBUG -+static int proc_read(char *buf, char **start, off_t offset, -+ int size, int *peof, void *data); -+#endif -+ -+void ubsec_reset_board(struct ubsec_softc *); -+void ubsec_init_board(struct ubsec_softc *); -+void ubsec_cleanchip(struct ubsec_softc *); -+void ubsec_totalreset(struct ubsec_softc *); -+int ubsec_free_q(struct ubsec_softc*, struct ubsec_q *); -+ -+static int ubsec_newsession(device_t, u_int32_t *, struct cryptoini *); -+static int ubsec_freesession(device_t, u_int64_t); -+static int ubsec_process(device_t, struct cryptop *, int); -+ -+void ubsec_callback(struct ubsec_softc *, struct ubsec_q *); -+void ubsec_feed(struct ubsec_softc *); -+void ubsec_mcopy(struct sk_buff *, struct sk_buff *, int, int); -+void ubsec_dma_free(struct ubsec_softc *, struct ubsec_dma_alloc *); -+int ubsec_dma_malloc(struct ubsec_softc *, struct ubsec_dma_alloc *, -+ size_t, int); -+ -+/* DEBUG crap... */ -+void ubsec_dump_pb(struct ubsec_pktbuf *); -+void ubsec_dump_mcr(struct ubsec_mcr *); -+ -+#define READ_REG(sc,r) \ -+ ssb_read32((sc)->sdev, (r)); -+#define WRITE_REG(sc,r,val) \ -+ ssb_write32((sc)->sdev, (r), (val)); -+#define READ_REG_SDEV(sdev,r) \ -+ ssb_read32((sdev), (r)); -+#define WRITE_REG_SDEV(sdev,r,val) \ -+ ssb_write32((sdev), (r), (val)); -+ -+#define SWAP32(x) (x) = htole32(ntohl((x))) -+#define HTOLE32(x) (x) = htole32(x) -+ -+#ifdef __LITTLE_ENDIAN -+#define letoh16(x) (x) -+#define letoh32(x) (x) -+#endif -+ -+static int debug; -+module_param(debug, int, 0644); -+MODULE_PARM_DESC(debug, "Enable debug output"); -+ -+#define UBSEC_SSB_MAX_CHIPS 1 -+static struct ubsec_softc *ubsec_chip_idx[UBSEC_SSB_MAX_CHIPS]; -+static struct ubsec_stats ubsecstats; -+ -+#ifdef UBSEC_DEBUG -+static struct proc_dir_entry *procdebug; -+#endif -+ -+static struct ssb_device_id ubsec_ssb_tbl[] = { -+ /* Broadcom BCM5365P IPSec Core */ -+ SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_IPSEC, SSB_ANY_REV), -+ SSB_DEVTABLE_END -+}; -+ -+static struct ssb_driver ubsec_ssb_driver = { -+ .name = DRV_MODULE_NAME, -+ .id_table = ubsec_ssb_tbl, -+ .probe = ubsec_ssb_probe, -+ .remove = __devexit_p(ubsec_ssb_remove), -+ /* -+ .suspend = ubsec_ssb_suspend, -+ .resume = ubsec_ssb_resume -+ */ -+}; -+ -+static device_method_t ubsec_ssb_methods = { -+ /* crypto device methods */ -+ DEVMETHOD(cryptodev_newsession, ubsec_newsession), -+ DEVMETHOD(cryptodev_freesession,ubsec_freesession), -+ DEVMETHOD(cryptodev_process, ubsec_process), -+}; -+ -+#ifdef UBSEC_DEBUG -+static int -+proc_read(char *buf, char **start, off_t offset, -+ int size, int *peof, void *data) -+{ -+ int i = 0, byteswritten = 0, ret; -+ unsigned int stat, ctrl; -+#ifdef UBSEC_VERBOSE_DEBUG -+ struct ubsec_q *q; -+ struct ubsec_dma *dmap; -+#endif -+ -+ while ((i < UBSEC_SSB_MAX_CHIPS) && (ubsec_chip_idx[i] != NULL)) -+ { -+ struct ubsec_softc *sc = ubsec_chip_idx[i]; -+ -+ stat = READ_REG(sc, BS_STAT); -+ ctrl = READ_REG(sc, BS_CTRL); -+ ret = snprintf((buf + byteswritten), -+ (size - byteswritten) , -+ "DEV %d, DMASTAT %08x, DMACTRL %08x\n", i, stat, ctrl); -+ -+ byteswritten += ret; -+ -+#ifdef UBSEC_VERBOSE_DEBUG -+ printf("DEV %d, DMASTAT %08x, DMACTRL %08x\n", i, stat, ctrl); -+ -+ /* Dump all queues MCRs */ -+ if (!BSD_SIMPLEQ_EMPTY(&sc->sc_qchip)) { -+ BSD_SIMPLEQ_FOREACH(q, &sc->sc_qchip, q_next) -+ { -+ dmap = q->q_dma; -+ ubsec_dump_mcr(&dmap->d_dma->d_mcr); -+ } -+ } -+#endif -+ -+ i++; -+ } -+ -+ *peof = 1; -+ -+ return byteswritten; -+} -+#endif -+ -+/* -+ * map in a given sk_buff -+ */ -+static int -+dma_map_skb(struct ubsec_softc *sc, struct ubsec_dma_alloc* q_map, struct sk_buff *skb, int *mlen) -+{ -+ int i = 0; -+ dma_addr_t tmp; -+ -+#ifdef UBSEC_DEBUG -+ DPRINTF("%s()\n", __FUNCTION__); -+#endif -+ -+ /* -+ * We support only a limited number of fragments. -+ */ -+ if (unlikely((skb_shinfo(skb)->nr_frags + 1) >= UBS_MAX_SCATTER)) -+ { -+ printk(KERN_ERR "Only %d scatter fragments are supported.\n", UBS_MAX_SCATTER); -+ return (-ENOMEM); -+ } -+ -+#ifdef UBSEC_VERBOSE_DEBUG -+ DPRINTF("%s - map %d 0x%x %d\n", __FUNCTION__, 0, (unsigned int)skb->data, skb_headlen(skb)); -+#endif -+ -+ /* first data package */ -+ tmp = dma_map_single(sc->sc_dv, -+ skb->data, -+ skb_headlen(skb), -+ DMA_BIDIRECTIONAL); -+ -+ q_map[i].dma_paddr = tmp; -+ q_map[i].dma_vaddr = skb->data; -+ q_map[i].dma_size = skb_headlen(skb); -+ -+ if (unlikely(tmp == 0)) -+ { -+ printk(KERN_ERR "Could not map memory region for dma.\n"); -+ return (-EINVAL); -+ } -+ -+#ifdef UBSEC_VERBOSE_DEBUG -+ DPRINTF("%s - map %d done physical addr 0x%x\n", __FUNCTION__, 0, (unsigned int)tmp); -+#endif -+ -+ -+ /* all other data packages */ -+ for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { -+ -+#ifdef UBSEC_VERBOSE_DEBUG -+ DPRINTF("%s - map %d 0x%x %d\n", __FUNCTION__, i + 1, -+ (unsigned int)page_address(skb_shinfo(skb)->frags[i].page) + -+ skb_shinfo(skb)->frags[i].page_offset, skb_shinfo(skb)->frags[i].size); -+#endif -+ -+ tmp = dma_map_single(sc->sc_dv, -+ page_address(skb_shinfo(skb)->frags[i].page) + -+ skb_shinfo(skb)->frags[i].page_offset, -+ skb_shinfo(skb)->frags[i].size, -+ DMA_BIDIRECTIONAL); -+ -+ q_map[i + 1].dma_paddr = tmp; -+ q_map[i + 1].dma_vaddr = (void*)(page_address(skb_shinfo(skb)->frags[i].page) + -+ skb_shinfo(skb)->frags[i].page_offset); -+ q_map[i + 1].dma_size = skb_shinfo(skb)->frags[i].size; -+ -+ if (unlikely(tmp == 0)) -+ { -+ printk(KERN_ERR "Could not map memory region for dma.\n"); -+ return (-EINVAL); -+ } -+ -+#ifdef UBSEC_VERBOSE_DEBUG -+ DPRINTF("%s - map %d done physical addr 0x%x\n", __FUNCTION__, i + 1, (unsigned int)tmp); -+#endif -+ -+ } -+ *mlen = i + 1; -+ -+ return(0); -+} -+ -+/* -+ * map in a given uio buffer -+ */ -+ -+static int -+dma_map_uio(struct ubsec_softc *sc, struct ubsec_dma_alloc *q_map, struct uio *uio, int *mlen) -+{ -+ struct iovec *iov = uio->uio_iov; -+ int n; -+ dma_addr_t tmp; -+ -+#ifdef UBSEC_DEBUG -+ DPRINTF("%s()\n", __FUNCTION__); -+#endif -+ -+ /* -+ * We support only a limited number of fragments. -+ */ -+ if (unlikely(uio->uio_iovcnt >= UBS_MAX_SCATTER)) -+ { -+ printk(KERN_ERR "Only %d scatter fragments are supported.\n", UBS_MAX_SCATTER); -+ return (-ENOMEM); -+ } -+ -+ for (n = 0; n < uio->uio_iovcnt; n++) { -+#ifdef UBSEC_VERBOSE_DEBUG -+ DPRINTF("%s - map %d 0x%x %d\n", __FUNCTION__, n, (unsigned int)iov->iov_base, iov->iov_len); -+#endif -+ tmp = dma_map_single(sc->sc_dv, -+ iov->iov_base, -+ iov->iov_len, -+ DMA_BIDIRECTIONAL); -+ -+ q_map[n].dma_paddr = tmp; -+ q_map[n].dma_vaddr = iov->iov_base; -+ q_map[n].dma_size = iov->iov_len; -+ -+ if (unlikely(tmp == 0)) -+ { -+ printk(KERN_ERR "Could not map memory region for dma.\n"); -+ return (-EINVAL); -+ } -+ -+#ifdef UBSEC_VERBOSE_DEBUG -+ DPRINTF("%s - map %d done physical addr 0x%x\n", __FUNCTION__, n, (unsigned int)tmp); -+#endif -+ -+ iov++; -+ } -+ *mlen = n; -+ -+ return(0); -+} -+ -+static void -+dma_unmap(struct ubsec_softc *sc, struct ubsec_dma_alloc *q_map, int mlen) -+{ -+ int i; -+ -+#ifdef UBSEC_DEBUG -+ DPRINTF("%s()\n", __FUNCTION__); -+#endif -+ -+ for(i = 0; i < mlen; i++) -+ { -+#ifdef UBSEC_VERBOSE_DEBUG -+ DPRINTF("%s - unmap %d 0x%x %d\n", __FUNCTION__, i, (unsigned int)q_map[i].dma_paddr, q_map[i].dma_size); -+#endif -+ dma_unmap_single(sc->sc_dv, -+ q_map[i].dma_paddr, -+ q_map[i].dma_size, -+ DMA_BIDIRECTIONAL); -+ } -+ return; -+} -+ -+/* -+ * Is the operand suitable aligned for direct DMA. Each -+ * segment must be aligned on a 32-bit boundary and all -+ * but the last segment must be a multiple of 4 bytes. -+ */ -+static int -+ubsec_dmamap_aligned(struct ubsec_softc *sc, const struct ubsec_dma_alloc *q_map, int mlen) -+{ -+ int i; -+ -+#ifdef UBSEC_DEBUG -+ DPRINTF("%s()\n", __FUNCTION__); -+#endif -+ -+ for (i = 0; i < mlen; i++) { -+ if (q_map[i].dma_paddr & 3) -+ return (0); -+ if (i != (mlen - 1) && (q_map[i].dma_size & 3)) -+ return (0); -+ } -+ return (1); -+} -+ -+ -+#define N(a) (sizeof(a) / sizeof (a[0])) -+static void -+ubsec_setup_mackey(struct ubsec_session *ses, int algo, caddr_t key, int klen) -+{ -+#ifdef HMAC_HACK -+ MD5_CTX md5ctx; -+ SHA1_CTX sha1ctx; -+ int i; -+ -+#ifdef UBSEC_DEBUG -+ DPRINTF("%s()\n", __FUNCTION__); -+#endif -+ -+ for (i = 0; i < klen; i++) -+ key[i] ^= HMAC_IPAD_VAL; -+ -+ if (algo == CRYPTO_MD5_HMAC) { -+ MD5Init(&md5ctx); -+ MD5Update(&md5ctx, key, klen); -+ MD5Update(&md5ctx, hmac_ipad_buffer, MD5_HMAC_BLOCK_LEN - klen); -+ bcopy(md5ctx.md5_st8, ses->ses_hminner, sizeof(md5ctx.md5_st8)); -+ } else { -+ SHA1Init(&sha1ctx); -+ SHA1Update(&sha1ctx, key, klen); -+ SHA1Update(&sha1ctx, hmac_ipad_buffer, -+ SHA1_HMAC_BLOCK_LEN - klen); -+ bcopy(sha1ctx.h.b32, ses->ses_hminner, sizeof(sha1ctx.h.b32)); -+ } -+ -+ for (i = 0; i < klen; i++) -+ key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); -+ -+ if (algo == CRYPTO_MD5_HMAC) { -+ MD5Init(&md5ctx); -+ MD5Update(&md5ctx, key, klen); -+ MD5Update(&md5ctx, hmac_opad_buffer, MD5_HMAC_BLOCK_LEN - klen); -+ bcopy(md5ctx.md5_st8, ses->ses_hmouter, sizeof(md5ctx.md5_st8)); -+ } else { -+ SHA1Init(&sha1ctx); -+ SHA1Update(&sha1ctx, key, klen); -+ SHA1Update(&sha1ctx, hmac_opad_buffer, -+ SHA1_HMAC_BLOCK_LEN - klen); -+ bcopy(sha1ctx.h.b32, ses->ses_hmouter, sizeof(sha1ctx.h.b32)); -+ } -+ -+ for (i = 0; i < klen; i++) -+ key[i] ^= HMAC_OPAD_VAL; -+ -+#else /* HMAC_HACK */ -+ DPRINTF("md5/sha not implemented\n"); -+#endif /* HMAC_HACK */ -+} -+#undef N -+ -+static int -+__devinit ubsec_ssb_probe(struct ssb_device *sdev, -+ const struct ssb_device_id *ent) -+{ -+ int err; -+ -+#ifdef UBSEC_DEBUG -+ DPRINTF("%s()\n", __FUNCTION__); -+#endif -+ -+ err = ssb_bus_powerup(sdev->bus, 0); -+ if (err) { -+ dev_err(sdev->dev, "Failed to powerup the bus\n"); -+ goto err_out; -+ } -+ -+ err = request_irq(sdev->irq, (irq_handler_t)ubsec_ssb_isr, -+ IRQF_DISABLED | IRQF_SHARED, DRV_MODULE_NAME, sdev); -+ if (err) { -+ dev_err(sdev->dev, "Could not request irq\n"); -+ goto err_out_powerdown; -+ } -+ -+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,36)) -+ err = dma_set_mask(sdev->dma_dev, DMA_BIT_MASK(32)) || -+ dma_set_coherent_mask(sdev->dma_dev, DMA_BIT_MASK(32)); -+#else -+ err = ssb_dma_set_mask(sdev, DMA_32BIT_MASK); -+#endif -+ if (err) { -+ dev_err(sdev->dev, -+ "Required 32BIT DMA mask unsupported by the system.\n"); -+ goto err_out_free_irq; -+ } -+ -+ printk(KERN_INFO "Sentry5(tm) ROBOGateway(tm) IPSec Core at IRQ %u\n", -+ sdev->irq); -+ -+ DPRINTF("Vendor: %x, core id: %x, revision: %x\n", -+ sdev->id.vendor, sdev->id.coreid, sdev->id.revision); -+ -+ ssb_device_enable(sdev, 0); -+ -+ if (ubsec_attach(sdev, ent, sdev->dev) != 0) -+ goto err_out_disable; -+ -+#ifdef UBSEC_DEBUG -+ procdebug = create_proc_entry(DRV_MODULE_NAME, S_IRUSR, NULL); -+ if (procdebug) -+ { -+ procdebug->read_proc = proc_read; -+ procdebug->data = NULL; -+ } else -+ DPRINTF("Unable to create proc file.\n"); -+#endif -+ -+ return 0; -+ -+err_out_disable: -+ ssb_device_disable(sdev, 0); -+ -+err_out_free_irq: -+ free_irq(sdev->irq, sdev); -+ -+err_out_powerdown: -+ ssb_bus_may_powerdown(sdev->bus); -+ -+err_out: -+ return err; -+} -+ -+static void __devexit ubsec_ssb_remove(struct ssb_device *sdev) { -+ -+ struct ubsec_softc *sc; -+ unsigned int ctrlflgs; -+ struct ubsec_dma *dmap; -+ u_int32_t i; -+ -+#ifdef UBSEC_DEBUG -+ DPRINTF("%s()\n", __FUNCTION__); -+#endif -+ -+ ctrlflgs = READ_REG_SDEV(sdev, BS_CTRL); -+ /* disable all IPSec Core interrupts globally */ -+ ctrlflgs ^= (BS_CTRL_MCR1INT | BS_CTRL_MCR2INT | -+ BS_CTRL_DMAERR); -+ WRITE_REG_SDEV(sdev, BS_CTRL, ctrlflgs); -+ -+ free_irq(sdev->irq, sdev); -+ -+ sc = (struct ubsec_softc *)ssb_get_drvdata(sdev); -+ -+ /* unregister all crypto algorithms */ -+ crypto_unregister_all(sc->sc_cid); -+ -+ /* Free queue / dma memory */ -+ for (i = 0; i < UBS_MAX_NQUEUE; i++) { -+ struct ubsec_q *q; -+ -+ q = sc->sc_queuea[i]; -+ if (q != NULL) -+ { -+ dmap = q->q_dma; -+ if (dmap != NULL) -+ { -+ ubsec_dma_free(sc, &dmap->d_alloc); -+ q->q_dma = NULL; -+ } -+ kfree(q); -+ } -+ sc->sc_queuea[i] = NULL; -+ } -+ -+ ssb_device_disable(sdev, 0); -+ ssb_bus_may_powerdown(sdev->bus); -+ ssb_set_drvdata(sdev, NULL); -+ -+#ifdef UBSEC_DEBUG -+ if (procdebug) -+ remove_proc_entry(DRV_MODULE_NAME, NULL); -+#endif -+ -+} -+ -+ -+int -+ubsec_attach(struct ssb_device *sdev, const struct ssb_device_id *ent, -+ struct device *self) -+{ -+ struct ubsec_softc *sc = NULL; -+ struct ubsec_dma *dmap; -+ u_int32_t i; -+ static int num_chips = 0; -+ -+#ifdef UBSEC_DEBUG -+ DPRINTF("%s()\n", __FUNCTION__); -+#endif -+ -+ sc = (struct ubsec_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); -+ if (!sc) -+ return(-ENOMEM); -+ memset(sc, 0, sizeof(*sc)); -+ -+ sc->sc_dv = sdev->dev; -+ sc->sdev = sdev; -+ -+ spin_lock_init(&sc->sc_ringmtx); -+ -+ softc_device_init(sc, "ubsec_ssb", num_chips, ubsec_ssb_methods); -+ -+ /* Maybe someday there are boards with more than one chip available */ -+ if (num_chips < UBSEC_SSB_MAX_CHIPS) { -+ ubsec_chip_idx[device_get_unit(sc->sc_dev)] = sc; -+ num_chips++; -+ } -+ -+ ssb_set_drvdata(sdev, sc); -+ -+ BSD_SIMPLEQ_INIT(&sc->sc_queue); -+ BSD_SIMPLEQ_INIT(&sc->sc_qchip); -+ BSD_SIMPLEQ_INIT(&sc->sc_queue2); -+ BSD_SIMPLEQ_INIT(&sc->sc_qchip2); -+ BSD_SIMPLEQ_INIT(&sc->sc_q2free); -+ -+ sc->sc_statmask = BS_STAT_MCR1_DONE | BS_STAT_DMAERR; -+ -+ sc->sc_cid = crypto_get_driverid(softc_get_device(sc), CRYPTOCAP_F_HARDWARE); -+ if (sc->sc_cid < 0) { -+ device_printf(sc->sc_dev, "could not get crypto driver id\n"); -+ return -1; -+ } -+ -+ BSD_SIMPLEQ_INIT(&sc->sc_freequeue); -+ dmap = sc->sc_dmaa; -+ for (i = 0; i < UBS_MAX_NQUEUE; i++, dmap++) { -+ struct ubsec_q *q; -+ -+ q = (struct ubsec_q *)kmalloc(sizeof(struct ubsec_q), GFP_KERNEL); -+ if (q == NULL) { -+ printf(": can't allocate queue buffers\n"); -+ break; -+ } -+ -+ if (ubsec_dma_malloc(sc, &dmap->d_alloc, sizeof(struct ubsec_dmachunk),0)) { -+ printf(": can't allocate dma buffers\n"); -+ kfree(q); -+ break; -+ } -+ dmap->d_dma = (struct ubsec_dmachunk *)dmap->d_alloc.dma_vaddr; -+ -+ q->q_dma = dmap; -+ sc->sc_queuea[i] = q; -+ -+ BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); -+ } -+ -+ /* -+ * Reset Broadcom chip -+ */ -+ ubsec_reset_board(sc); -+ -+ /* -+ * Init Broadcom chip -+ */ -+ ubsec_init_board(sc); -+ -+ /* supported crypto algorithms */ -+ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); -+ -+ if (sc->sc_flags & UBS_FLAGS_AES) { -+ crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); -+ printf(KERN_INFO DRV_MODULE_NAME ": DES 3DES AES128 AES192 AES256 MD5_HMAC SHA1_HMAC\n"); -+ } -+ else -+ printf(KERN_INFO DRV_MODULE_NAME ": DES 3DES MD5_HMAC SHA1_HMAC\n"); -+ -+ crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); -+ crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); -+ -+ return 0; -+} -+ -+/* -+ * UBSEC Interrupt routine -+ */ -+static irqreturn_t -+ubsec_ssb_isr(int irq, void *arg, struct pt_regs *regs) -+{ -+ struct ubsec_softc *sc = NULL; -+ volatile u_int32_t stat; -+ struct ubsec_q *q; -+ struct ubsec_dma *dmap; -+ int npkts = 0, i; -+ -+#ifdef UBSEC_VERBOSE_DEBUG -+ DPRINTF("%s()\n", __FUNCTION__); -+#endif -+ -+ sc = (struct ubsec_softc *)ssb_get_drvdata(arg); -+ -+ stat = READ_REG(sc, BS_STAT); -+ -+ stat &= sc->sc_statmask; -+ if (stat == 0) -+ return IRQ_NONE; -+ -+ WRITE_REG(sc, BS_STAT, stat); /* IACK */ -+ -+ /* -+ * Check to see if we have any packets waiting for us -+ */ -+ if ((stat & BS_STAT_MCR1_DONE)) { -+ while (!BSD_SIMPLEQ_EMPTY(&sc->sc_qchip)) { -+ q = BSD_SIMPLEQ_FIRST(&sc->sc_qchip); -+ dmap = q->q_dma; -+ -+ if ((dmap->d_dma->d_mcr.mcr_flags & htole16(UBS_MCR_DONE)) == 0) -+ { -+ DPRINTF("error while processing MCR. Flags = %x\n", dmap->d_dma->d_mcr.mcr_flags); -+ break; -+ } -+ -+ BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q_next); -+ -+ npkts = q->q_nstacked_mcrs; -+ /* -+ * search for further sc_qchip ubsec_q's that share -+ * the same MCR, and complete them too, they must be -+ * at the top. -+ */ -+ for (i = 0; i < npkts; i++) { -+ if(q->q_stacked_mcr[i]) -+ ubsec_callback(sc, q->q_stacked_mcr[i]); -+ else -+ break; -+ } -+ ubsec_callback(sc, q); -+ } -+ -+ /* -+ * Don't send any more packet to chip if there has been -+ * a DMAERR. -+ */ -+ if (likely(!(stat & BS_STAT_DMAERR))) -+ ubsec_feed(sc); -+ else -+ DPRINTF("DMA error occurred. Stop feeding crypto chip.\n"); -+ } -+ -+ /* -+ * Check to see if we got any DMA Error -+ */ -+ if (stat & BS_STAT_DMAERR) { -+ volatile u_int32_t a = READ_REG(sc, BS_ERR); -+ -+ printf(KERN_ERR "%s: dmaerr %s@%08x\n", DRV_MODULE_NAME, -+ (a & BS_ERR_READ) ? "read" : "write", a & BS_ERR_ADDR); -+ -+ ubsecstats.hst_dmaerr++; -+ ubsec_totalreset(sc); -+ ubsec_feed(sc); -+ } -+ -+ return IRQ_HANDLED; -+} -+ -+/* -+ * ubsec_feed() - aggregate and post requests to chip -+ * It is assumed that the caller set splnet() -+ */ -+void -+ubsec_feed(struct ubsec_softc *sc) -+{ -+#ifdef UBSEC_VERBOSE_DEBUG -+ static int max; -+#endif -+ struct ubsec_q *q, *q2; -+ int npkts, i; -+ void *v; -+ u_int32_t stat; -+ -+ npkts = sc->sc_nqueue; -+ if (npkts > UBS_MAX_AGGR) -+ npkts = UBS_MAX_AGGR; -+ if (npkts < 2) -+ goto feed1; -+ -+ stat = READ_REG(sc, BS_STAT); -+ -+ if (stat & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) { -+ if(stat & BS_STAT_DMAERR) { -+ ubsec_totalreset(sc); -+ ubsecstats.hst_dmaerr++; -+ } -+ return; -+ } -+ -+#ifdef UBSEC_VERBOSE_DEBUG -+ DPRINTF("merging %d records\n", npkts); -+ -+ /* XXX temporary aggregation statistics reporting code */ -+ if (max < npkts) { -+ max = npkts; -+ DPRINTF("%s: new max aggregate %d\n", DRV_MODULE_NAME, max); -+ } -+#endif /* UBSEC_VERBOSE_DEBUG */ -+ -+ q = BSD_SIMPLEQ_FIRST(&sc->sc_queue); -+ BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next); -+ --sc->sc_nqueue; -+ -+#if 0 -+ /* -+ * XXX -+ * We use dma_map_single() - no sync required! -+ */ -+ -+ bus_dmamap_sync(sc->sc_dmat, q->q_src_map, -+ 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE); -+ if (q->q_dst_map != NULL) -+ bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, -+ 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD); -+#endif -+ -+ q->q_nstacked_mcrs = npkts - 1; /* Number of packets stacked */ -+ -+ for (i = 0; i < q->q_nstacked_mcrs; i++) { -+ q2 = BSD_SIMPLEQ_FIRST(&sc->sc_queue); -+ -+#if 0 -+ bus_dmamap_sync(sc->sc_dmat, q2->q_src_map, -+ 0, q2->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE); -+ if (q2->q_dst_map != NULL) -+ bus_dmamap_sync(sc->sc_dmat, q2->q_dst_map, -+ 0, q2->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD); -+#endif -+ BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next); -+ --sc->sc_nqueue; -+ -+ v = ((char *)&q2->q_dma->d_dma->d_mcr) + sizeof(struct ubsec_mcr) - -+ sizeof(struct ubsec_mcr_add); -+ bcopy(v, &q->q_dma->d_dma->d_mcradd[i], sizeof(struct ubsec_mcr_add)); -+ q->q_stacked_mcr[i] = q2; -+ } -+ q->q_dma->d_dma->d_mcr.mcr_pkts = htole16(npkts); -+ BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); -+#if 0 -+ bus_dmamap_sync(sc->sc_dmat, q->q_dma->d_alloc.dma_map, -+ 0, q->q_dma->d_alloc.dma_map->dm_mapsize, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+#endif -+ WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + -+ offsetof(struct ubsec_dmachunk, d_mcr)); -+#ifdef UBSEC_VERBOSE_DEBUG -+ DPRINTF("feed (1): q->chip %p %08x %08x\n", q, -+ (u_int32_t)q->q_dma->d_alloc.dma_paddr, -+ (u_int32_t)(q->q_dma->d_alloc.dma_paddr + -+ offsetof(struct ubsec_dmachunk, d_mcr))); -+#endif /* UBSEC_DEBUG */ -+ return; -+ -+feed1: -+ while (!BSD_SIMPLEQ_EMPTY(&sc->sc_queue)) { -+ stat = READ_REG(sc, BS_STAT); -+ -+ if (stat & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) { -+ if(stat & BS_STAT_DMAERR) { -+ ubsec_totalreset(sc); -+ ubsecstats.hst_dmaerr++; -+ } -+ break; -+ } -+ -+ q = BSD_SIMPLEQ_FIRST(&sc->sc_queue); -+ -+#if 0 -+ bus_dmamap_sync(sc->sc_dmat, q->q_src_map, -+ 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE); -+ if (q->q_dst_map != NULL) -+ bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, -+ 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD); -+ bus_dmamap_sync(sc->sc_dmat, q->q_dma->d_alloc.dma_map, -+ 0, q->q_dma->d_alloc.dma_map->dm_mapsize, -+ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); -+#endif -+ -+ WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + -+ offsetof(struct ubsec_dmachunk, d_mcr)); -+#ifdef UBSEC_VERBOSE_DEBUG -+ DPRINTF("feed (2): q->chip %p %08x %08x\n", q, -+ (u_int32_t)q->q_dma->d_alloc.dma_paddr, -+ (u_int32_t)(q->q_dma->d_alloc.dma_paddr + -+ offsetof(struct ubsec_dmachunk, d_mcr))); -+#endif /* UBSEC_DEBUG */ -+ BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next); -+ --sc->sc_nqueue; -+ BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); -+ } -+} -+ -+/* -+ * Allocate a new 'session' and return an encoded session id. 'sidp' -+ * contains our registration id, and should contain an encoded session -+ * id on successful allocation. -+ */ -+static int -+ubsec_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) -+{ -+ struct cryptoini *c, *encini = NULL, *macini = NULL; -+ struct ubsec_softc *sc = NULL; -+ struct ubsec_session *ses = NULL; -+ int sesn, i; -+ -+#ifdef UBSEC_DEBUG -+ DPRINTF("%s()\n", __FUNCTION__); -+#endif -+ -+ if (sidp == NULL || cri == NULL) -+ return (EINVAL); -+ -+ sc = device_get_softc(dev); -+ -+ if (sc == NULL) -+ return (EINVAL); -+ -+ for (c = cri; c != NULL; c = c->cri_next) { -+ if (c->cri_alg == CRYPTO_MD5_HMAC || -+ c->cri_alg == CRYPTO_SHA1_HMAC) { -+ if (macini) -+ return (EINVAL); -+ macini = c; -+ } else if (c->cri_alg == CRYPTO_DES_CBC || -+ c->cri_alg == CRYPTO_3DES_CBC || -+ c->cri_alg == CRYPTO_AES_CBC) { -+ if (encini) -+ return (EINVAL); -+ encini = c; -+ } else -+ return (EINVAL); -+ } -+ if (encini == NULL && macini == NULL) -+ return (EINVAL); -+ -+ if (sc->sc_sessions == NULL) { -+ ses = sc->sc_sessions = (struct ubsec_session *)kmalloc( -+ sizeof(struct ubsec_session), SLAB_ATOMIC); -+ if (ses == NULL) -+ return (ENOMEM); -+ memset(ses, 0, sizeof(struct ubsec_session)); -+ sesn = 0; -+ sc->sc_nsessions = 1; -+ } else { -+ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { -+ if (sc->sc_sessions[sesn].ses_used == 0) { -+ ses = &sc->sc_sessions[sesn]; -+ break; -+ } -+ } -+ -+ if (ses == NULL) { -+ sesn = sc->sc_nsessions; -+ ses = (struct ubsec_session *)kmalloc((sesn + 1) * -+ sizeof(struct ubsec_session), SLAB_ATOMIC); -+ if (ses == NULL) -+ return (ENOMEM); -+ memset(ses, 0, (sesn + 1) * sizeof(struct ubsec_session)); -+ bcopy(sc->sc_sessions, ses, sesn * -+ sizeof(struct ubsec_session)); -+ bzero(sc->sc_sessions, sesn * -+ sizeof(struct ubsec_session)); -+ kfree(sc->sc_sessions); -+ sc->sc_sessions = ses; -+ ses = &sc->sc_sessions[sesn]; -+ sc->sc_nsessions++; -+ } -+ } -+ -+ bzero(ses, sizeof(struct ubsec_session)); -+ ses->ses_used = 1; -+ if (encini) { -+ /* get an IV */ -+ /* XXX may read fewer than requested */ -+ read_random(ses->ses_iv, sizeof(ses->ses_iv)); -+ -+ /* Go ahead and compute key in ubsec's byte order */ -+ if (encini->cri_alg == CRYPTO_DES_CBC) { -+ /* DES uses the same key three times: -+ * 1st encrypt -> 2nd decrypt -> 3nd encrypt */ -+ bcopy(encini->cri_key, &ses->ses_key[0], 8); -+ bcopy(encini->cri_key, &ses->ses_key[2], 8); -+ bcopy(encini->cri_key, &ses->ses_key[4], 8); -+ ses->ses_keysize = 192; /* Fake! Actually its only 64bits .. -+ oh no it is even less: 54bits. */ -+ } else if(encini->cri_alg == CRYPTO_3DES_CBC) { -+ bcopy(encini->cri_key, ses->ses_key, 24); -+ ses->ses_keysize = 192; -+ } else if(encini->cri_alg == CRYPTO_AES_CBC) { -+ ses->ses_keysize = encini->cri_klen; -+ -+ if (ses->ses_keysize != 128 && -+ ses->ses_keysize != 192 && -+ ses->ses_keysize != 256) -+ { -+ DPRINTF("unsupported AES key size: %d\n", ses->ses_keysize); -+ return (EINVAL); -+ } -+ bcopy(encini->cri_key, ses->ses_key, (ses->ses_keysize / 8)); -+ } -+ -+ /* Hardware requires the keys in little endian byte order */ -+ for (i=0; i < (ses->ses_keysize / 32); i++) -+ SWAP32(ses->ses_key[i]); -+ } -+ -+ if (macini) { -+ ses->ses_mlen = macini->cri_mlen; -+ -+ if (ses->ses_mlen == 0 || -+ ses->ses_mlen > SHA1_HASH_LEN) { -+ -+ if (macini->cri_alg == CRYPTO_MD5_HMAC || -+ macini->cri_alg == CRYPTO_SHA1_HMAC) -+ { -+ ses->ses_mlen = DEFAULT_HMAC_LEN; -+ } else -+ { -+ /* -+ * Reserved for future usage. MD5/SHA1 calculations have -+ * different hash sizes. -+ */ -+ printk(KERN_ERR DRV_MODULE_NAME ": unsupported hash operation with mac/hash len: %d\n", ses->ses_mlen); -+ return (EINVAL); -+ } -+ -+ } -+ -+ if (macini->cri_key != NULL) { -+ ubsec_setup_mackey(ses, macini->cri_alg, macini->cri_key, -+ macini->cri_klen / 8); -+ } -+ } -+ -+ *sidp = UBSEC_SID(device_get_unit(sc->sc_dev), sesn); -+ return (0); -+} -+ -+/* -+ * Deallocate a session. -+ */ -+static int -+ubsec_freesession(device_t dev, u_int64_t tid) -+{ -+ struct ubsec_softc *sc = device_get_softc(dev); -+ int session; -+ u_int32_t sid = ((u_int32_t)tid) & 0xffffffff; -+ -+#ifdef UBSEC_DEBUG -+ DPRINTF("%s()\n", __FUNCTION__); -+#endif -+ -+ if (sc == NULL) -+ return (EINVAL); -+ -+ session = UBSEC_SESSION(sid); -+ if (session < sc->sc_nsessions) { -+ bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session])); -+ return (0); -+ } else -+ return (EINVAL); -+} -+ -+static int -+ubsec_process(device_t dev, struct cryptop *crp, int hint) -+{ -+ struct ubsec_q *q = NULL; -+ int err = 0, i, j, nicealign; -+ struct ubsec_softc *sc = device_get_softc(dev); -+ struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; -+ int encoffset = 0, macoffset = 0, cpskip, cpoffset; -+ int sskip, dskip, stheend, dtheend, ivsize = 8; -+ int16_t coffset; -+ struct ubsec_session *ses; -+ struct ubsec_generic_ctx ctx; -+ struct ubsec_dma *dmap = NULL; -+ unsigned long flags; -+ -+#ifdef UBSEC_DEBUG -+ DPRINTF("%s()\n", __FUNCTION__); -+#endif -+ -+ if (unlikely(crp == NULL || crp->crp_callback == NULL)) { -+ ubsecstats.hst_invalid++; -+ return (EINVAL); -+ } -+ -+ if (unlikely(sc == NULL)) -+ return (EINVAL); -+ -+#ifdef UBSEC_VERBOSE_DEBUG -+ DPRINTF("spin_lock_irqsave\n"); -+#endif -+ spin_lock_irqsave(&sc->sc_ringmtx, flags); -+ //spin_lock_irq(&sc->sc_ringmtx); -+ -+ if (BSD_SIMPLEQ_EMPTY(&sc->sc_freequeue)) { -+ ubsecstats.hst_queuefull++; -+#ifdef UBSEC_VERBOSE_DEBUG -+ DPRINTF("spin_unlock_irqrestore\n"); -+#endif -+ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); -+ //spin_unlock_irq(&sc->sc_ringmtx); -+ err = ENOMEM; -+ goto errout2; -+ } -+ -+ q = BSD_SIMPLEQ_FIRST(&sc->sc_freequeue); -+ BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q_next); -+#ifdef UBSEC_VERBOSE_DEBUG -+ DPRINTF("spin_unlock_irqrestore\n"); -+#endif -+ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); -+ //spin_unlock_irq(&sc->sc_ringmtx); -+ -+ dmap = q->q_dma; /* Save dma pointer */ -+ bzero(q, sizeof(struct ubsec_q)); -+ bzero(&ctx, sizeof(ctx)); -+ -+ q->q_sesn = UBSEC_SESSION(crp->crp_sid); -+ q->q_dma = dmap; -+ ses = &sc->sc_sessions[q->q_sesn]; -+ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ q->q_src_m = (struct sk_buff *)crp->crp_buf; -+ q->q_dst_m = (struct sk_buff *)crp->crp_buf; -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+ q->q_src_io = (struct uio *)crp->crp_buf; -+ q->q_dst_io = (struct uio *)crp->crp_buf; -+ } else { -+ err = EINVAL; -+ goto errout; /* XXX we don't handle contiguous blocks! */ -+ } -+ -+ bzero(&dmap->d_dma->d_mcr, sizeof(struct ubsec_mcr)); -+ -+ dmap->d_dma->d_mcr.mcr_pkts = htole16(1); -+ dmap->d_dma->d_mcr.mcr_flags = 0; -+ q->q_crp = crp; -+ -+ crd1 = crp->crp_desc; -+ if (crd1 == NULL) { -+ err = EINVAL; -+ goto errout; -+ } -+ crd2 = crd1->crd_next; -+ -+ if (crd2 == NULL) { -+ if (crd1->crd_alg == CRYPTO_MD5_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1_HMAC) { -+ maccrd = crd1; -+ enccrd = NULL; -+ } else if (crd1->crd_alg == CRYPTO_DES_CBC || -+ crd1->crd_alg == CRYPTO_3DES_CBC || -+ crd1->crd_alg == CRYPTO_AES_CBC) { -+ maccrd = NULL; -+ enccrd = crd1; -+ } else { -+ err = EINVAL; -+ goto errout; -+ } -+ } else { -+ if ((crd1->crd_alg == CRYPTO_MD5_HMAC || -+ crd1->crd_alg == CRYPTO_SHA1_HMAC) && -+ (crd2->crd_alg == CRYPTO_DES_CBC || -+ crd2->crd_alg == CRYPTO_3DES_CBC || -+ crd2->crd_alg == CRYPTO_AES_CBC) && -+ ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { -+ maccrd = crd1; -+ enccrd = crd2; -+ } else if ((crd1->crd_alg == CRYPTO_DES_CBC || -+ crd1->crd_alg == CRYPTO_3DES_CBC || -+ crd1->crd_alg == CRYPTO_AES_CBC) && -+ (crd2->crd_alg == CRYPTO_MD5_HMAC || -+ crd2->crd_alg == CRYPTO_SHA1_HMAC) && -+ (crd1->crd_flags & CRD_F_ENCRYPT)) { -+ enccrd = crd1; -+ maccrd = crd2; -+ } else { -+ /* -+ * We cannot order the ubsec as requested -+ */ -+ printk(KERN_ERR DRV_MODULE_NAME ": got wrong algorithm/signature order.\n"); -+ err = EINVAL; -+ goto errout; -+ } -+ } -+ -+ /* Encryption/Decryption requested */ -+ if (enccrd) { -+ encoffset = enccrd->crd_skip; -+ -+ if (enccrd->crd_alg == CRYPTO_DES_CBC || -+ enccrd->crd_alg == CRYPTO_3DES_CBC) -+ { -+ ctx.pc_flags |= htole16(UBS_PKTCTX_ENC_3DES); -+ ctx.pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC_DES); -+ ivsize = 8; /* [3]DES uses 64bit IVs */ -+ } else { -+ ctx.pc_flags |= htole16(UBS_PKTCTX_ENC_AES); -+ ctx.pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC_AES); -+ ivsize = 16; /* AES uses 128bit IVs / [3]DES 64bit IVs */ -+ -+ switch(ses->ses_keysize) -+ { -+ case 128: -+ ctx.pc_flags |= htole16(UBS_PKTCTX_AES128); -+ break; -+ case 192: -+ ctx.pc_flags |= htole16(UBS_PKTCTX_AES192); -+ break; -+ case 256: -+ ctx.pc_flags |= htole16(UBS_PKTCTX_AES256); -+ break; -+ default: -+ DPRINTF("invalid AES key size: %d\n", ses->ses_keysize); -+ err = EINVAL; -+ goto errout; -+ } -+ } -+ -+ if (enccrd->crd_flags & CRD_F_ENCRYPT) { -+ /* Direction: Outbound */ -+ -+ q->q_flags |= UBSEC_QFLAGS_COPYOUTIV; -+ -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) { -+ bcopy(enccrd->crd_iv, ctx.pc_iv, ivsize); -+ } else { -+ for(i=0; i < (ivsize / 4); i++) -+ ctx.pc_iv[i] = ses->ses_iv[i]; -+ } -+ -+ /* If there is no IV in the buffer -> copy it here */ -+ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { -+ if (crp->crp_flags & CRYPTO_F_SKBUF) -+ /* -+ m_copyback(q->q_src_m, -+ enccrd->crd_inject, -+ 8, ctx.pc_iv); -+ */ -+ crypto_copyback(crp->crp_flags, (caddr_t)q->q_src_m, -+ enccrd->crd_inject, ivsize, (caddr_t)ctx.pc_iv); -+ else if (crp->crp_flags & CRYPTO_F_IOV) -+ /* -+ cuio_copyback(q->q_src_io, -+ enccrd->crd_inject, -+ 8, ctx.pc_iv); -+ */ -+ crypto_copyback(crp->crp_flags, (caddr_t)q->q_src_io, -+ enccrd->crd_inject, ivsize, (caddr_t)ctx.pc_iv); -+ } -+ } else { -+ /* Direction: Inbound */ -+ -+ ctx.pc_flags |= htole16(UBS_PKTCTX_INBOUND); -+ -+ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) -+ bcopy(enccrd->crd_iv, ctx.pc_iv, ivsize); -+ else if (crp->crp_flags & CRYPTO_F_SKBUF) -+ /* -+ m_copydata(q->q_src_m, enccrd->crd_inject, -+ 8, (caddr_t)ctx.pc_iv); -+ */ -+ crypto_copydata(crp->crp_flags, (caddr_t)q->q_src_m, -+ enccrd->crd_inject, ivsize, -+ (caddr_t)ctx.pc_iv); -+ else if (crp->crp_flags & CRYPTO_F_IOV) -+ /* -+ cuio_copydata(q->q_src_io, -+ enccrd->crd_inject, 8, -+ (caddr_t)ctx.pc_iv); -+ */ -+ crypto_copydata(crp->crp_flags, (caddr_t)q->q_src_io, -+ enccrd->crd_inject, ivsize, -+ (caddr_t)ctx.pc_iv); -+ -+ } -+ -+ /* Even though key & IV sizes differ from cipher to cipher -+ * copy / swap the full array lengths. Let the compiler unroll -+ * the loop to increase the cpu pipeline performance... */ -+ for(i=0; i < 8; i++) -+ ctx.pc_key[i] = ses->ses_key[i]; -+ for(i=0; i < 4; i++) -+ SWAP32(ctx.pc_iv[i]); -+ } -+ -+ /* Authentication requested */ -+ if (maccrd) { -+ macoffset = maccrd->crd_skip; -+ -+ if (maccrd->crd_alg == CRYPTO_MD5_HMAC) -+ ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_MD5); -+ else -+ ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_SHA1); -+ -+ for (i = 0; i < 5; i++) { -+ ctx.pc_hminner[i] = ses->ses_hminner[i]; -+ ctx.pc_hmouter[i] = ses->ses_hmouter[i]; -+ -+ HTOLE32(ctx.pc_hminner[i]); -+ HTOLE32(ctx.pc_hmouter[i]); -+ } -+ } -+ -+ if (enccrd && maccrd) { -+ /* -+ * ubsec cannot handle packets where the end of encryption -+ * and authentication are not the same, or where the -+ * encrypted part begins before the authenticated part. -+ */ -+ if (((encoffset + enccrd->crd_len) != -+ (macoffset + maccrd->crd_len)) || -+ (enccrd->crd_skip < maccrd->crd_skip)) { -+ err = EINVAL; -+ goto errout; -+ } -+ sskip = maccrd->crd_skip; -+ cpskip = dskip = enccrd->crd_skip; -+ stheend = maccrd->crd_len; -+ dtheend = enccrd->crd_len; -+ coffset = enccrd->crd_skip - maccrd->crd_skip; -+ cpoffset = cpskip + dtheend; -+#ifdef UBSEC_DEBUG -+ DPRINTF("mac: skip %d, len %d, inject %d\n", -+ maccrd->crd_skip, maccrd->crd_len, maccrd->crd_inject); -+ DPRINTF("enc: skip %d, len %d, inject %d\n", -+ enccrd->crd_skip, enccrd->crd_len, enccrd->crd_inject); -+ DPRINTF("src: skip %d, len %d\n", sskip, stheend); -+ DPRINTF("dst: skip %d, len %d\n", dskip, dtheend); -+ DPRINTF("ubs: coffset %d, pktlen %d, cpskip %d, cpoffset %d\n", -+ coffset, stheend, cpskip, cpoffset); -+#endif -+ } else { -+ cpskip = dskip = sskip = macoffset + encoffset; -+ dtheend = stheend = (enccrd)?enccrd->crd_len:maccrd->crd_len; -+ cpoffset = cpskip + dtheend; -+ coffset = 0; -+ } -+ ctx.pc_offset = htole16(coffset >> 2); -+ -+#if 0 -+ if (bus_dmamap_create(sc->sc_dmat, 0xfff0, UBS_MAX_SCATTER, -+ 0xfff0, 0, BUS_DMA_NOWAIT, &q->q_src_map) != 0) { -+ err = ENOMEM; -+ goto errout; -+ } -+#endif -+ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) { -+#if 0 -+ if (bus_dmamap_load_mbuf(sc->sc_dmat, q->q_src_map, -+ q->q_src_m, BUS_DMA_NOWAIT) != 0) { -+ bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); -+ q->q_src_map = NULL; -+ err = ENOMEM; -+ goto errout; -+ } -+#endif -+ err = dma_map_skb(sc, q->q_src_map, q->q_src_m, &q->q_src_len); -+ if (unlikely(err != 0)) -+ goto errout; -+ -+ } else if (crp->crp_flags & CRYPTO_F_IOV) { -+#if 0 -+ if (bus_dmamap_load_uio(sc->sc_dmat, q->q_src_map, -+ q->q_src_io, BUS_DMA_NOWAIT) != 0) { -+ bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); -+ q->q_src_map = NULL; -+ err = ENOMEM; -+ goto errout; -+ } -+#endif -+ err = dma_map_uio(sc, q->q_src_map, q->q_src_io, &q->q_src_len); -+ if (unlikely(err != 0)) -+ goto errout; -+ } -+ -+ /* -+ * Check alignment -+ */ -+ nicealign = ubsec_dmamap_aligned(sc, q->q_src_map, q->q_src_len); -+ -+ dmap->d_dma->d_mcr.mcr_pktlen = htole16(stheend); -+ -+#ifdef UBSEC_DEBUG -+ DPRINTF("src skip: %d\n", sskip); -+#endif -+ for (i = j = 0; i < q->q_src_len; i++) { -+ struct ubsec_pktbuf *pb; -+ size_t packl = q->q_src_map[i].dma_size; -+ dma_addr_t packp = q->q_src_map[i].dma_paddr; -+ -+ if (sskip >= packl) { -+ sskip -= packl; -+ continue; -+ } -+ -+ packl -= sskip; -+ packp += sskip; -+ sskip = 0; -+ -+ /* maximum fragment size is 0xfffc */ -+ if (packl > 0xfffc) { -+ DPRINTF("Error: fragment size is bigger than 0xfffc.\n"); -+ err = EIO; -+ goto errout; -+ } -+ -+ if (j == 0) -+ pb = &dmap->d_dma->d_mcr.mcr_ipktbuf; -+ else -+ pb = &dmap->d_dma->d_sbuf[j - 1]; -+ -+ pb->pb_addr = htole32(packp); -+ -+ if (stheend) { -+ if (packl > stheend) { -+ pb->pb_len = htole32(stheend); -+ stheend = 0; -+ } else { -+ pb->pb_len = htole32(packl); -+ stheend -= packl; -+ } -+ } else -+ pb->pb_len = htole32(packl); -+ -+ if ((i + 1) == q->q_src_len) -+ pb->pb_next = 0; -+ else -+ pb->pb_next = htole32(dmap->d_alloc.dma_paddr + -+ offsetof(struct ubsec_dmachunk, d_sbuf[j])); -+ j++; -+ } -+ -+ if (enccrd == NULL && maccrd != NULL) { -+ /* Authentication only */ -+ dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr = 0; -+ dmap->d_dma->d_mcr.mcr_opktbuf.pb_len = 0; -+ dmap->d_dma->d_mcr.mcr_opktbuf.pb_next = -+ htole32(dmap->d_alloc.dma_paddr + -+ offsetof(struct ubsec_dmachunk, d_macbuf[0])); -+#ifdef UBSEC_DEBUG -+ DPRINTF("opkt: %x %x %x\n", -+ dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr, -+ dmap->d_dma->d_mcr.mcr_opktbuf.pb_len, -+ dmap->d_dma->d_mcr.mcr_opktbuf.pb_next); -+#endif -+ } else { -+ if (crp->crp_flags & CRYPTO_F_IOV) { -+ if (!nicealign) { -+ err = EINVAL; -+ goto errout; -+ } -+#if 0 -+ if (bus_dmamap_create(sc->sc_dmat, 0xfff0, -+ UBS_MAX_SCATTER, 0xfff0, 0, BUS_DMA_NOWAIT, -+ &q->q_dst_map) != 0) { -+ err = ENOMEM; -+ goto errout; -+ } -+ if (bus_dmamap_load_uio(sc->sc_dmat, q->q_dst_map, -+ q->q_dst_io, BUS_DMA_NOWAIT) != 0) { -+ bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); -+ q->q_dst_map = NULL; -+ goto errout; -+ } -+#endif -+ -+ /* HW shall copy the result into the source memory */ -+ for(i = 0; i < q->q_src_len; i++) -+ q->q_dst_map[i] = q->q_src_map[i]; -+ -+ q->q_dst_len = q->q_src_len; -+ q->q_has_dst = 0; -+ -+ } else if (crp->crp_flags & CRYPTO_F_SKBUF) { -+ if (nicealign) { -+ -+ /* HW shall copy the result into the source memory */ -+ q->q_dst_m = q->q_src_m; -+ for(i = 0; i < q->q_src_len; i++) -+ q->q_dst_map[i] = q->q_src_map[i]; -+ -+ q->q_dst_len = q->q_src_len; -+ q->q_has_dst = 0; -+ -+ } else { -+#ifdef NOTYET -+ int totlen, len; -+ struct sk_buff *m, *top, **mp; -+ -+ totlen = q->q_src_map->dm_mapsize; -+ if (q->q_src_m->m_flags & M_PKTHDR) { -+ len = MHLEN; -+ MGETHDR(m, M_DONTWAIT, MT_DATA); -+ } else { -+ len = MLEN; -+ MGET(m, M_DONTWAIT, MT_DATA); -+ } -+ if (m == NULL) { -+ err = ENOMEM; -+ goto errout; -+ } -+ if (len == MHLEN) -+ M_DUP_PKTHDR(m, q->q_src_m); -+ if (totlen >= MINCLSIZE) { -+ MCLGET(m, M_DONTWAIT); -+ if (m->m_flags & M_EXT) -+ len = MCLBYTES; -+ } -+ m->m_len = len; -+ top = NULL; -+ mp = ⊤ -+ -+ while (totlen > 0) { -+ if (top) { -+ MGET(m, M_DONTWAIT, MT_DATA); -+ if (m == NULL) { -+ m_freem(top); -+ err = ENOMEM; -+ goto errout; -+ } -+ len = MLEN; -+ } -+ if (top && totlen >= MINCLSIZE) { -+ MCLGET(m, M_DONTWAIT); -+ if (m->m_flags & M_EXT) -+ len = MCLBYTES; -+ } -+ m->m_len = len = min(totlen, len); -+ totlen -= len; -+ *mp = m; -+ mp = &m->m_next; -+ } -+ q->q_dst_m = top; -+ ubsec_mcopy(q->q_src_m, q->q_dst_m, -+ cpskip, cpoffset); -+ if (bus_dmamap_create(sc->sc_dmat, 0xfff0, -+ UBS_MAX_SCATTER, 0xfff0, 0, BUS_DMA_NOWAIT, -+ &q->q_dst_map) != 0) { -+ err = ENOMEM; -+ goto errout; -+ } -+ if (bus_dmamap_load_mbuf(sc->sc_dmat, -+ q->q_dst_map, q->q_dst_m, -+ BUS_DMA_NOWAIT) != 0) { -+ bus_dmamap_destroy(sc->sc_dmat, -+ q->q_dst_map); -+ q->q_dst_map = NULL; -+ err = ENOMEM; -+ goto errout; -+ } -+#else -+ device_printf(sc->sc_dev, -+ "%s,%d: CRYPTO_F_SKBUF unaligned not implemented\n", -+ __FILE__, __LINE__); -+ err = EINVAL; -+ goto errout; -+#endif -+ } -+ } else { -+ err = EINVAL; -+ goto errout; -+ } -+ -+#ifdef UBSEC_DEBUG -+ DPRINTF("dst skip: %d\n", dskip); -+#endif -+ for (i = j = 0; i < q->q_dst_len; i++) { -+ struct ubsec_pktbuf *pb; -+ size_t packl = q->q_dst_map[i].dma_size; -+ dma_addr_t packp = q->q_dst_map[i].dma_paddr; -+ -+ if (dskip >= packl) { -+ dskip -= packl; -+ continue; -+ } -+ -+ packl -= dskip; -+ packp += dskip; -+ dskip = 0; -+ -+ if (packl > 0xfffc) { -+ DPRINTF("Error: fragment size is bigger than 0xfffc.\n"); -+ err = EIO; -+ goto errout; -+ } -+ -+ if (j == 0) -+ pb = &dmap->d_dma->d_mcr.mcr_opktbuf; -+ else -+ pb = &dmap->d_dma->d_dbuf[j - 1]; -+ -+ pb->pb_addr = htole32(packp); -+ -+ if (dtheend) { -+ if (packl > dtheend) { -+ pb->pb_len = htole32(dtheend); -+ dtheend = 0; -+ } else { -+ pb->pb_len = htole32(packl); -+ dtheend -= packl; -+ } -+ } else -+ pb->pb_len = htole32(packl); -+ -+ if ((i + 1) == q->q_dst_len) { -+ if (maccrd) -+ /* Authentication: -+ * The last fragment of the output buffer -+ * contains the HMAC. */ -+ pb->pb_next = htole32(dmap->d_alloc.dma_paddr + -+ offsetof(struct ubsec_dmachunk, d_macbuf[0])); -+ else -+ pb->pb_next = 0; -+ } else -+ pb->pb_next = htole32(dmap->d_alloc.dma_paddr + -+ offsetof(struct ubsec_dmachunk, d_dbuf[j])); -+ j++; -+ } -+ } -+ -+ dmap->d_dma->d_mcr.mcr_cmdctxp = htole32(dmap->d_alloc.dma_paddr + -+ offsetof(struct ubsec_dmachunk, d_ctx)); -+ -+ if (sc->sc_flags & UBS_FLAGS_LONGCTX) { -+ /* new Broadcom cards with dynamic long command context structure */ -+ -+ if (enccrd != NULL && -+ enccrd->crd_alg == CRYPTO_AES_CBC) -+ { -+ struct ubsec_pktctx_aes128 *ctxaes128; -+ struct ubsec_pktctx_aes192 *ctxaes192; -+ struct ubsec_pktctx_aes256 *ctxaes256; -+ -+ switch(ses->ses_keysize) -+ { -+ /* AES 128bit */ -+ case 128: -+ ctxaes128 = (struct ubsec_pktctx_aes128 *) -+ (dmap->d_alloc.dma_vaddr + -+ offsetof(struct ubsec_dmachunk, d_ctx)); -+ -+ ctxaes128->pc_len = htole16(sizeof(struct ubsec_pktctx_aes128)); -+ ctxaes128->pc_type = ctx.pc_type; -+ ctxaes128->pc_flags = ctx.pc_flags; -+ ctxaes128->pc_offset = ctx.pc_offset; -+ for (i = 0; i < 4; i++) -+ ctxaes128->pc_aeskey[i] = ctx.pc_key[i]; -+ for (i = 0; i < 5; i++) -+ ctxaes128->pc_hminner[i] = ctx.pc_hminner[i]; -+ for (i = 0; i < 5; i++) -+ ctxaes128->pc_hmouter[i] = ctx.pc_hmouter[i]; -+ for (i = 0; i < 4; i++) -+ ctxaes128->pc_iv[i] = ctx.pc_iv[i]; -+ break; -+ -+ /* AES 192bit */ -+ case 192: -+ ctxaes192 = (struct ubsec_pktctx_aes192 *) -+ (dmap->d_alloc.dma_vaddr + -+ offsetof(struct ubsec_dmachunk, d_ctx)); -+ -+ ctxaes192->pc_len = htole16(sizeof(struct ubsec_pktctx_aes192)); -+ ctxaes192->pc_type = ctx.pc_type; -+ ctxaes192->pc_flags = ctx.pc_flags; -+ ctxaes192->pc_offset = ctx.pc_offset; -+ for (i = 0; i < 6; i++) -+ ctxaes192->pc_aeskey[i] = ctx.pc_key[i]; -+ for (i = 0; i < 5; i++) -+ ctxaes192->pc_hminner[i] = ctx.pc_hminner[i]; -+ for (i = 0; i < 5; i++) -+ ctxaes192->pc_hmouter[i] = ctx.pc_hmouter[i]; -+ for (i = 0; i < 4; i++) -+ ctxaes192->pc_iv[i] = ctx.pc_iv[i]; -+ break; -+ -+ /* AES 256bit */ -+ case 256: -+ ctxaes256 = (struct ubsec_pktctx_aes256 *) -+ (dmap->d_alloc.dma_vaddr + -+ offsetof(struct ubsec_dmachunk, d_ctx)); -+ -+ ctxaes256->pc_len = htole16(sizeof(struct ubsec_pktctx_aes256)); -+ ctxaes256->pc_type = ctx.pc_type; -+ ctxaes256->pc_flags = ctx.pc_flags; -+ ctxaes256->pc_offset = ctx.pc_offset; -+ for (i = 0; i < 8; i++) -+ ctxaes256->pc_aeskey[i] = ctx.pc_key[i]; -+ for (i = 0; i < 5; i++) -+ ctxaes256->pc_hminner[i] = ctx.pc_hminner[i]; -+ for (i = 0; i < 5; i++) -+ ctxaes256->pc_hmouter[i] = ctx.pc_hmouter[i]; -+ for (i = 0; i < 4; i++) -+ ctxaes256->pc_iv[i] = ctx.pc_iv[i]; -+ break; -+ -+ } -+ } else { -+ /* -+ * [3]DES / MD5_HMAC / SHA1_HMAC -+ * -+ * MD5_HMAC / SHA1_HMAC can use the IPSEC 3DES operation without -+ * encryption. -+ */ -+ struct ubsec_pktctx_des *ctxdes; -+ -+ ctxdes = (struct ubsec_pktctx_des *)(dmap->d_alloc.dma_vaddr + -+ offsetof(struct ubsec_dmachunk, d_ctx)); -+ -+ ctxdes->pc_len = htole16(sizeof(struct ubsec_pktctx_des)); -+ ctxdes->pc_type = ctx.pc_type; -+ ctxdes->pc_flags = ctx.pc_flags; -+ ctxdes->pc_offset = ctx.pc_offset; -+ for (i = 0; i < 6; i++) -+ ctxdes->pc_deskey[i] = ctx.pc_key[i]; -+ for (i = 0; i < 5; i++) -+ ctxdes->pc_hminner[i] = ctx.pc_hminner[i]; -+ for (i = 0; i < 5; i++) -+ ctxdes->pc_hmouter[i] = ctx.pc_hmouter[i]; -+ ctxdes->pc_iv[0] = ctx.pc_iv[0]; -+ ctxdes->pc_iv[1] = ctx.pc_iv[1]; -+ } -+ } else -+ { -+ /* old Broadcom card with fixed small command context structure */ -+ -+ /* -+ * [3]DES / MD5_HMAC / SHA1_HMAC -+ */ -+ struct ubsec_pktctx *ctxs; -+ -+ ctxs = (struct ubsec_pktctx *)(dmap->d_alloc.dma_vaddr + -+ offsetof(struct ubsec_dmachunk, d_ctx)); -+ -+ /* transform generic context into small context */ -+ for (i = 0; i < 6; i++) -+ ctxs->pc_deskey[i] = ctx.pc_key[i]; -+ for (i = 0; i < 5; i++) -+ ctxs->pc_hminner[i] = ctx.pc_hminner[i]; -+ for (i = 0; i < 5; i++) -+ ctxs->pc_hmouter[i] = ctx.pc_hmouter[i]; -+ ctxs->pc_iv[0] = ctx.pc_iv[0]; -+ ctxs->pc_iv[1] = ctx.pc_iv[1]; -+ ctxs->pc_flags = ctx.pc_flags; -+ ctxs->pc_offset = ctx.pc_offset; -+ } -+ -+#ifdef UBSEC_VERBOSE_DEBUG -+ DPRINTF("spin_lock_irqsave\n"); -+#endif -+ spin_lock_irqsave(&sc->sc_ringmtx, flags); -+ //spin_lock_irq(&sc->sc_ringmtx); -+ -+ BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_queue, q, q_next); -+ sc->sc_nqueue++; -+ ubsecstats.hst_ipackets++; -+ ubsecstats.hst_ibytes += stheend; -+ ubsec_feed(sc); -+ -+#ifdef UBSEC_VERBOSE_DEBUG -+ DPRINTF("spin_unlock_irqrestore\n"); -+#endif -+ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); -+ //spin_unlock_irq(&sc->sc_ringmtx); -+ -+ return (0); -+ -+errout: -+ if (q != NULL) { -+#ifdef NOTYET -+ if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) -+ m_freem(q->q_dst_m); -+#endif -+ -+ if ((q->q_has_dst == 1) && q->q_dst_len > 0) { -+#if 0 -+ bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); -+ bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); -+#endif -+ dma_unmap(sc, q->q_dst_map, q->q_dst_len); -+ } -+ if (q->q_src_len > 0) { -+#if 0 -+ bus_dmamap_unload(sc->sc_dmat, q->q_src_map); -+ bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); -+#endif -+ dma_unmap(sc, q->q_src_map, q->q_src_len); -+ } -+ -+#ifdef UBSEC_VERBOSE_DEBUG -+ DPRINTF("spin_lock_irqsave\n"); -+#endif -+ spin_lock_irqsave(&sc->sc_ringmtx, flags); -+ //spin_lock_irq(&sc->sc_ringmtx); -+ -+ BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); -+ -+#ifdef UBSEC_VERBOSE_DEBUG -+ DPRINTF("spin_unlock_irqrestore\n"); -+#endif -+ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); -+ //spin_unlock_irq(&sc->sc_ringmtx); -+ -+ } -+ if (err == EINVAL) -+ ubsecstats.hst_invalid++; -+ else -+ ubsecstats.hst_nomem++; -+errout2: -+ crp->crp_etype = err; -+ crypto_done(crp); -+ -+#ifdef UBSEC_DEBUG -+ DPRINTF("%s() err = %x\n", __FUNCTION__, err); -+#endif -+ -+ return (0); -+} -+ -+void -+ubsec_callback(struct ubsec_softc *sc, struct ubsec_q *q) -+{ -+ struct cryptop *crp = (struct cryptop *)q->q_crp; -+ struct cryptodesc *crd; -+ struct ubsec_dma *dmap = q->q_dma; -+ int ivsize = 8; -+ -+#ifdef UBSEC_DEBUG -+ DPRINTF("%s()\n", __FUNCTION__); -+#endif -+ -+ ubsecstats.hst_opackets++; -+ ubsecstats.hst_obytes += dmap->d_alloc.dma_size; -+ -+#if 0 -+ bus_dmamap_sync(sc->sc_dmat, dmap->d_alloc.dma_map, 0, -+ dmap->d_alloc.dma_map->dm_mapsize, -+ BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); -+ if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { -+ bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, -+ 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_POSTREAD); -+ bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); -+ bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); -+ } -+ bus_dmamap_sync(sc->sc_dmat, q->q_src_map, -+ 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); -+ bus_dmamap_unload(sc->sc_dmat, q->q_src_map); -+ bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); -+#endif -+ -+ if ((q->q_has_dst == 1) && q->q_dst_len > 0) -+ dma_unmap(sc, q->q_dst_map, q->q_dst_len); -+ -+ dma_unmap(sc, q->q_src_map, q->q_src_len); -+ -+#ifdef NOTYET -+ if ((crp->crp_flags & CRYPTO_F_SKBUF) && (q->q_src_m != q->q_dst_m)) { -+ m_freem(q->q_src_m); -+ crp->crp_buf = (caddr_t)q->q_dst_m; -+ } -+#endif -+ -+ /* copy out IV for future use */ -+ if (q->q_flags & UBSEC_QFLAGS_COPYOUTIV) { -+ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { -+ if (crd->crd_alg != CRYPTO_DES_CBC && -+ crd->crd_alg != CRYPTO_3DES_CBC && -+ crd->crd_alg != CRYPTO_AES_CBC) -+ continue; -+ -+ if (crd->crd_alg == CRYPTO_AES_CBC) -+ ivsize = 16; -+ else -+ ivsize = 8; -+ -+ if (crp->crp_flags & CRYPTO_F_SKBUF) -+#if 0 -+ m_copydata((struct sk_buff *)crp->crp_buf, -+ crd->crd_skip + crd->crd_len - 8, 8, -+ (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv); -+#endif -+ crypto_copydata(crp->crp_flags, (caddr_t)crp->crp_buf, -+ crd->crd_skip + crd->crd_len - ivsize, ivsize, -+ (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv); -+ -+ else if (crp->crp_flags & CRYPTO_F_IOV) { -+#if 0 -+ cuio_copydata((struct uio *)crp->crp_buf, -+ crd->crd_skip + crd->crd_len - 8, 8, -+ (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv); -+#endif -+ crypto_copydata(crp->crp_flags, (caddr_t)crp->crp_buf, -+ crd->crd_skip + crd->crd_len - ivsize, ivsize, -+ (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv); -+ -+ } -+ break; -+ } -+ } -+ -+ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { -+ if (crd->crd_alg != CRYPTO_MD5_HMAC && -+ crd->crd_alg != CRYPTO_SHA1_HMAC) -+ continue; -+#if 0 -+ if (crp->crp_flags & CRYPTO_F_SKBUF) -+ m_copyback((struct sk_buff *)crp->crp_buf, -+ crd->crd_inject, 12, -+ dmap->d_dma->d_macbuf); -+#endif -+#if 0 -+ /* BUG? it does not honor the mac len.. */ -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, 12, -+ (caddr_t)dmap->d_dma->d_macbuf); -+#endif -+ crypto_copyback(crp->crp_flags, crp->crp_buf, -+ crd->crd_inject, -+ sc->sc_sessions[q->q_sesn].ses_mlen, -+ (caddr_t)dmap->d_dma->d_macbuf); -+#if 0 -+ else if (crp->crp_flags & CRYPTO_F_IOV && crp->crp_mac) -+ bcopy((caddr_t)dmap->d_dma->d_macbuf, -+ crp->crp_mac, 12); -+#endif -+ break; -+ } -+ BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); -+ crypto_done(crp); -+} -+ -+void -+ubsec_mcopy(struct sk_buff *srcm, struct sk_buff *dstm, int hoffset, int toffset) -+{ -+ int i, j, dlen, slen; -+ caddr_t dptr, sptr; -+ -+ j = 0; -+ sptr = srcm->data; -+ slen = srcm->len; -+ dptr = dstm->data; -+ dlen = dstm->len; -+ -+ while (1) { -+ for (i = 0; i < min(slen, dlen); i++) { -+ if (j < hoffset || j >= toffset) -+ *dptr++ = *sptr++; -+ slen--; -+ dlen--; -+ j++; -+ } -+ if (slen == 0) { -+ srcm = srcm->next; -+ if (srcm == NULL) -+ return; -+ sptr = srcm->data; -+ slen = srcm->len; -+ } -+ if (dlen == 0) { -+ dstm = dstm->next; -+ if (dstm == NULL) -+ return; -+ dptr = dstm->data; -+ dlen = dstm->len; -+ } -+ } -+} -+ -+int -+ubsec_dma_malloc(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma, -+ size_t size, int mapflags) -+{ -+ dma->dma_vaddr = dma_alloc_coherent(sc->sc_dv, -+ size, &dma->dma_paddr, GFP_KERNEL); -+ -+ if (likely(dma->dma_vaddr)) -+ { -+ dma->dma_size = size; -+ return (0); -+ } -+ -+ DPRINTF("could not allocate %d bytes of coherent memory.\n", size); -+ -+ return (1); -+} -+ -+void -+ubsec_dma_free(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma) -+{ -+ dma_free_coherent(sc->sc_dv, dma->dma_size, dma->dma_vaddr, -+ dma->dma_paddr); -+} -+ -+/* -+ * Resets the board. Values in the regesters are left as is -+ * from the reset (i.e. initial values are assigned elsewhere). -+ */ -+void -+ubsec_reset_board(struct ubsec_softc *sc) -+{ -+ volatile u_int32_t ctrl; -+ -+#ifdef UBSEC_DEBUG -+ DPRINTF("%s()\n", __FUNCTION__); -+#endif -+ DPRINTF("Send reset signal to chip.\n"); -+ -+ ctrl = READ_REG(sc, BS_CTRL); -+ ctrl |= BS_CTRL_RESET; -+ WRITE_REG(sc, BS_CTRL, ctrl); -+ -+ /* -+ * Wait aprox. 30 PCI clocks = 900 ns = 0.9 us -+ */ -+ DELAY(10); -+} -+ -+/* -+ * Init Broadcom registers -+ */ -+void -+ubsec_init_board(struct ubsec_softc *sc) -+{ -+ u_int32_t ctrl; -+ -+#ifdef UBSEC_DEBUG -+ DPRINTF("%s()\n", __FUNCTION__); -+#endif -+ DPRINTF("Initialize chip.\n"); -+ -+ ctrl = READ_REG(sc, BS_CTRL); -+ ctrl &= ~(BS_CTRL_BE32 | BS_CTRL_BE64); -+ ctrl |= BS_CTRL_LITTLE_ENDIAN | BS_CTRL_MCR1INT | BS_CTRL_DMAERR; -+ -+ WRITE_REG(sc, BS_CTRL, ctrl); -+ -+ /* Set chip capabilities (BCM5365P) */ -+ sc->sc_flags |= UBS_FLAGS_LONGCTX | UBS_FLAGS_AES; -+} -+ -+/* -+ * Clean up after a chip crash. -+ * It is assumed that the caller has spin_lock_irq(sc_ringmtx). -+ */ -+void -+ubsec_cleanchip(struct ubsec_softc *sc) -+{ -+ struct ubsec_q *q; -+ -+#ifdef UBSEC_DEBUG -+ DPRINTF("%s()\n", __FUNCTION__); -+#endif -+ DPRINTF("Clean up queues after chip crash.\n"); -+ -+ while (!BSD_SIMPLEQ_EMPTY(&sc->sc_qchip)) { -+ q = BSD_SIMPLEQ_FIRST(&sc->sc_qchip); -+ BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q_next); -+ ubsec_free_q(sc, q); -+ } -+} -+ -+/* -+ * free a ubsec_q -+ * It is assumed that the caller has spin_lock_irq(sc_ringmtx). -+ */ -+int -+ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q) -+{ -+ struct ubsec_q *q2; -+ struct cryptop *crp; -+ int npkts; -+ int i; -+ -+#ifdef UBSEC_DEBUG -+ DPRINTF("%s()\n", __FUNCTION__); -+#endif -+ -+ npkts = q->q_nstacked_mcrs; -+ -+ for (i = 0; i < npkts; i++) { -+ if(q->q_stacked_mcr[i]) { -+ q2 = q->q_stacked_mcr[i]; -+ -+ if ((q2->q_dst_m != NULL) && (q2->q_src_m != q2->q_dst_m)) -+#ifdef NOTYET -+ m_freem(q2->q_dst_m); -+#else -+ printk(KERN_ERR "%s,%d: SKB not supported\n", __FILE__, __LINE__); -+#endif -+ -+ crp = (struct cryptop *)q2->q_crp; -+ -+ BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q2, q_next); -+ -+ crp->crp_etype = EFAULT; -+ crypto_done(crp); -+ } else { -+ break; -+ } -+ } -+ -+ /* -+ * Free header MCR -+ */ -+ if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) -+#ifdef NOTYET -+ m_freem(q->q_dst_m); -+#else -+ printk(KERN_ERR "%s,%d: SKB not supported\n", __FILE__, __LINE__); -+#endif -+ -+ crp = (struct cryptop *)q->q_crp; -+ -+ BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); -+ -+ crp->crp_etype = EFAULT; -+ crypto_done(crp); -+ return(0); -+} -+ -+/* -+ * Routine to reset the chip and clean up. -+ * It is assumed that the caller has spin_lock_irq(sc_ringmtx). -+ */ -+void -+ubsec_totalreset(struct ubsec_softc *sc) -+{ -+ -+#ifdef UBSEC_DEBUG -+ DPRINTF("%s()\n", __FUNCTION__); -+#endif -+ DPRINTF("initiate total chip reset.. \n"); -+ ubsec_reset_board(sc); -+ ubsec_init_board(sc); -+ ubsec_cleanchip(sc); -+} -+ -+void -+ubsec_dump_pb(struct ubsec_pktbuf *pb) -+{ -+ printf("addr 0x%x (0x%x) next 0x%x\n", -+ pb->pb_addr, pb->pb_len, pb->pb_next); -+} -+ -+void -+ubsec_dump_mcr(struct ubsec_mcr *mcr) -+{ -+ struct ubsec_mcr_add *ma; -+ int i; -+ -+ printf("MCR:\n"); -+ printf(" pkts: %u, flags 0x%x\n", -+ letoh16(mcr->mcr_pkts), letoh16(mcr->mcr_flags)); -+ ma = (struct ubsec_mcr_add *)&mcr->mcr_cmdctxp; -+ for (i = 0; i < letoh16(mcr->mcr_pkts); i++) { -+ printf(" %d: ctx 0x%x len 0x%x rsvd 0x%x\n", i, -+ letoh32(ma->mcr_cmdctxp), letoh16(ma->mcr_pktlen), -+ letoh16(ma->mcr_reserved)); -+ printf(" %d: ipkt ", i); -+ ubsec_dump_pb(&ma->mcr_ipktbuf); -+ printf(" %d: opkt ", i); -+ ubsec_dump_pb(&ma->mcr_opktbuf); -+ ma++; -+ } -+ printf("END MCR\n"); -+} -+ -+static int __init mod_init(void) { -+ return ssb_driver_register(&ubsec_ssb_driver); -+} -+ -+static void __exit mod_exit(void) { -+ ssb_driver_unregister(&ubsec_ssb_driver); -+} -+ -+module_init(mod_init); -+module_exit(mod_exit); -+ -+// Meta information -+MODULE_AUTHOR("Daniel Mueller "); -+MODULE_LICENSE("BSD"); -+MODULE_DESCRIPTION("OCF driver for BCM5365P IPSec Core"); -+MODULE_VERSION(DRV_MODULE_VERSION); -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/ubsec_ssb/ubsecreg.h linux-3.0.4/crypto/ocf/ubsec_ssb/ubsecreg.h ---- linux-3.0.4.orig/crypto/ocf/ubsec_ssb/ubsecreg.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/ubsec_ssb/ubsecreg.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,233 @@ -+ -+/* -+ * Copyright (c) 2008 Daniel Mueller (daniel@danm.de) -+ * Copyright (c) 2000 Theo de Raadt -+ * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com) -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored in part by the Defense Advanced Research Projects -+ * Agency (DARPA) and Air Force Research Laboratory, Air Force -+ * Materiel Command, USAF, under agreement number F30602-01-2-0537. -+ * -+ */ -+ -+/* -+ * Register definitions for 5601 BlueSteel Networks Ubiquitous Broadband -+ * Security "uBSec" chip. Definitions from revision 2.8 of the product -+ * datasheet. -+ */ -+ -+#define BS_BAR 0x10 /* DMA base address register */ -+#define BS_TRDY_TIMEOUT 0x40 /* TRDY timeout */ -+#define BS_RETRY_TIMEOUT 0x41 /* DMA retry timeout */ -+ -+#define UBS_PCI_RTY_SHIFT 8 -+#define UBS_PCI_RTY_MASK 0xff -+#define UBS_PCI_RTY(misc) \ -+ (((misc) >> UBS_PCI_RTY_SHIFT) & UBS_PCI_RTY_MASK) -+ -+#define UBS_PCI_TOUT_SHIFT 0 -+#define UBS_PCI_TOUT_MASK 0xff -+#define UBS_PCI_TOUT(misc) \ -+ (((misc) >> PCI_TOUT_SHIFT) & PCI_TOUT_MASK) -+ -+/* -+ * DMA Control & Status Registers (offset from BS_BAR) -+ */ -+#define BS_MCR1 0x20 /* DMA Master Command Record 1 */ -+#define BS_CTRL 0x24 /* DMA Control */ -+#define BS_STAT 0x28 /* DMA Status */ -+#define BS_ERR 0x2c /* DMA Error Address */ -+#define BS_DEV_ID 0x34 /* IPSec Device ID */ -+ -+/* BS_CTRL - DMA Control */ -+#define BS_CTRL_RESET 0x80000000 /* hardware reset, 5805/5820 */ -+#define BS_CTRL_MCR2INT 0x40000000 /* enable intr MCR for MCR2 */ -+#define BS_CTRL_MCR1INT 0x20000000 /* enable intr MCR for MCR1 */ -+#define BS_CTRL_OFM 0x10000000 /* Output fragment mode */ -+#define BS_CTRL_BE32 0x08000000 /* big-endian, 32bit bytes */ -+#define BS_CTRL_BE64 0x04000000 /* big-endian, 64bit bytes */ -+#define BS_CTRL_DMAERR 0x02000000 /* enable intr DMA error */ -+#define BS_CTRL_RNG_M 0x01800000 /* RNG mode */ -+#define BS_CTRL_RNG_1 0x00000000 /* 1bit rn/one slow clock */ -+#define BS_CTRL_RNG_4 0x00800000 /* 1bit rn/four slow clocks */ -+#define BS_CTRL_RNG_8 0x01000000 /* 1bit rn/eight slow clocks */ -+#define BS_CTRL_RNG_16 0x01800000 /* 1bit rn/16 slow clocks */ -+#define BS_CTRL_SWNORM 0x00400000 /* 582[01], sw normalization */ -+#define BS_CTRL_FRAG_M 0x0000ffff /* output fragment size mask */ -+#define BS_CTRL_LITTLE_ENDIAN (BS_CTRL_BE32 | BS_CTRL_BE64) -+ -+/* BS_STAT - DMA Status */ -+#define BS_STAT_MCR1_BUSY 0x80000000 /* MCR1 is busy */ -+#define BS_STAT_MCR1_FULL 0x40000000 /* MCR1 is full */ -+#define BS_STAT_MCR1_DONE 0x20000000 /* MCR1 is done */ -+#define BS_STAT_DMAERR 0x10000000 /* DMA error */ -+#define BS_STAT_MCR2_FULL 0x08000000 /* MCR2 is full */ -+#define BS_STAT_MCR2_DONE 0x04000000 /* MCR2 is done */ -+#define BS_STAT_MCR1_ALLEMPTY 0x02000000 /* 5821, MCR1 is empty */ -+#define BS_STAT_MCR2_ALLEMPTY 0x01000000 /* 5821, MCR2 is empty */ -+ -+/* BS_ERR - DMA Error Address */ -+#define BS_ERR_ADDR 0xfffffffc /* error address mask */ -+#define BS_ERR_READ 0x00000002 /* fault was on read */ -+ -+struct ubsec_pktctx { -+ u_int32_t pc_deskey[6]; /* 3DES key */ -+ u_int32_t pc_hminner[5]; /* hmac inner state */ -+ u_int32_t pc_hmouter[5]; /* hmac outer state */ -+ u_int32_t pc_iv[2]; /* [3]DES iv */ -+ u_int16_t pc_flags; /* flags, below */ -+ u_int16_t pc_offset; /* crypto offset */ -+} __attribute__ ((packed)); -+ -+#define UBS_PKTCTX_ENC_3DES 0x8000 /* use 3des */ -+#define UBS_PKTCTX_ENC_AES 0x8000 /* use aes */ -+#define UBS_PKTCTX_ENC_NONE 0x0000 /* no encryption */ -+#define UBS_PKTCTX_INBOUND 0x4000 /* inbound packet */ -+#define UBS_PKTCTX_AUTH 0x3000 /* authentication mask */ -+#define UBS_PKTCTX_AUTH_NONE 0x0000 /* no authentication */ -+#define UBS_PKTCTX_AUTH_MD5 0x1000 /* use hmac-md5 */ -+#define UBS_PKTCTX_AUTH_SHA1 0x2000 /* use hmac-sha1 */ -+#define UBS_PKTCTX_AES128 0x0 /* AES 128bit keys */ -+#define UBS_PKTCTX_AES192 0x100 /* AES 192bit keys */ -+#define UBS_PKTCTX_AES256 0x200 /* AES 256bit keys */ -+ -+struct ubsec_pktctx_des { -+ volatile u_int16_t pc_len; /* length of ctx struct */ -+ volatile u_int16_t pc_type; /* context type */ -+ volatile u_int16_t pc_flags; /* flags, same as above */ -+ volatile u_int16_t pc_offset; /* crypto/auth offset */ -+ volatile u_int32_t pc_deskey[6]; /* 3DES key */ -+ volatile u_int32_t pc_iv[2]; /* [3]DES iv */ -+ volatile u_int32_t pc_hminner[5]; /* hmac inner state */ -+ volatile u_int32_t pc_hmouter[5]; /* hmac outer state */ -+} __attribute__ ((packed)); -+ -+struct ubsec_pktctx_aes128 { -+ volatile u_int16_t pc_len; /* length of ctx struct */ -+ volatile u_int16_t pc_type; /* context type */ -+ volatile u_int16_t pc_flags; /* flags, same as above */ -+ volatile u_int16_t pc_offset; /* crypto/auth offset */ -+ volatile u_int32_t pc_aeskey[4]; /* AES 128bit key */ -+ volatile u_int32_t pc_iv[4]; /* AES iv */ -+ volatile u_int32_t pc_hminner[5]; /* hmac inner state */ -+ volatile u_int32_t pc_hmouter[5]; /* hmac outer state */ -+} __attribute__ ((packed)); -+ -+struct ubsec_pktctx_aes192 { -+ volatile u_int16_t pc_len; /* length of ctx struct */ -+ volatile u_int16_t pc_type; /* context type */ -+ volatile u_int16_t pc_flags; /* flags, same as above */ -+ volatile u_int16_t pc_offset; /* crypto/auth offset */ -+ volatile u_int32_t pc_aeskey[6]; /* AES 192bit key */ -+ volatile u_int32_t pc_iv[4]; /* AES iv */ -+ volatile u_int32_t pc_hminner[5]; /* hmac inner state */ -+ volatile u_int32_t pc_hmouter[5]; /* hmac outer state */ -+} __attribute__ ((packed)); -+ -+struct ubsec_pktctx_aes256 { -+ volatile u_int16_t pc_len; /* length of ctx struct */ -+ volatile u_int16_t pc_type; /* context type */ -+ volatile u_int16_t pc_flags; /* flags, same as above */ -+ volatile u_int16_t pc_offset; /* crypto/auth offset */ -+ volatile u_int32_t pc_aeskey[8]; /* AES 256bit key */ -+ volatile u_int32_t pc_iv[4]; /* AES iv */ -+ volatile u_int32_t pc_hminner[5]; /* hmac inner state */ -+ volatile u_int32_t pc_hmouter[5]; /* hmac outer state */ -+} __attribute__ ((packed)); -+ -+#define UBS_PKTCTX_TYPE_IPSEC_DES 0x0000 -+#define UBS_PKTCTX_TYPE_IPSEC_AES 0x0040 -+ -+struct ubsec_pktbuf { -+ volatile u_int32_t pb_addr; /* address of buffer start */ -+ volatile u_int32_t pb_next; /* pointer to next pktbuf */ -+ volatile u_int32_t pb_len; /* packet length */ -+} __attribute__ ((packed)); -+#define UBS_PKTBUF_LEN 0x0000ffff /* length mask */ -+ -+struct ubsec_mcr { -+ volatile u_int16_t mcr_pkts; /* #pkts in this mcr */ -+ volatile u_int16_t mcr_flags; /* mcr flags (below) */ -+ volatile u_int32_t mcr_cmdctxp; /* command ctx pointer */ -+ struct ubsec_pktbuf mcr_ipktbuf; /* input chain header */ -+ volatile u_int16_t mcr_reserved; -+ volatile u_int16_t mcr_pktlen; -+ struct ubsec_pktbuf mcr_opktbuf; /* output chain header */ -+} __attribute__ ((packed)); -+ -+struct ubsec_mcr_add { -+ volatile u_int32_t mcr_cmdctxp; /* command ctx pointer */ -+ struct ubsec_pktbuf mcr_ipktbuf; /* input chain header */ -+ volatile u_int16_t mcr_reserved; -+ volatile u_int16_t mcr_pktlen; -+ struct ubsec_pktbuf mcr_opktbuf; /* output chain header */ -+} __attribute__ ((packed)); -+ -+#define UBS_MCR_DONE 0x0001 /* mcr has been processed */ -+#define UBS_MCR_ERROR 0x0002 /* error in processing */ -+#define UBS_MCR_ERRORCODE 0xff00 /* error type */ -+ -+struct ubsec_ctx_keyop { -+ volatile u_int16_t ctx_len; /* command length */ -+ volatile u_int16_t ctx_op; /* operation code */ -+ volatile u_int8_t ctx_pad[60]; /* padding */ -+} __attribute__ ((packed)); -+#define UBS_CTXOP_DHPKGEN 0x01 /* dh public key generation */ -+#define UBS_CTXOP_DHSSGEN 0x02 /* dh shared secret gen. */ -+#define UBS_CTXOP_RSAPUB 0x03 /* rsa public key op */ -+#define UBS_CTXOP_RSAPRIV 0x04 /* rsa private key op */ -+#define UBS_CTXOP_DSASIGN 0x05 /* dsa signing op */ -+#define UBS_CTXOP_DSAVRFY 0x06 /* dsa verification */ -+#define UBS_CTXOP_RNGBYPASS 0x41 /* rng direct test mode */ -+#define UBS_CTXOP_RNGSHA1 0x42 /* rng sha1 test mode */ -+#define UBS_CTXOP_MODADD 0x43 /* modular addition */ -+#define UBS_CTXOP_MODSUB 0x44 /* modular subtraction */ -+#define UBS_CTXOP_MODMUL 0x45 /* modular multiplication */ -+#define UBS_CTXOP_MODRED 0x46 /* modular reduction */ -+#define UBS_CTXOP_MODEXP 0x47 /* modular exponentiation */ -+#define UBS_CTXOP_MODINV 0x48 /* modular inverse */ -+ -+struct ubsec_ctx_rngbypass { -+ volatile u_int16_t rbp_len; /* command length, 64 */ -+ volatile u_int16_t rbp_op; /* rng bypass, 0x41 */ -+ volatile u_int8_t rbp_pad[60]; /* padding */ -+} __attribute__ ((packed)); -+ -+/* modexp: C = (M ^ E) mod N */ -+struct ubsec_ctx_modexp { -+ volatile u_int16_t me_len; /* command length */ -+ volatile u_int16_t me_op; /* modexp, 0x47 */ -+ volatile u_int16_t me_E_len; /* E (bits) */ -+ volatile u_int16_t me_N_len; /* N (bits) */ -+ u_int8_t me_N[2048/8]; /* N */ -+} __attribute__ ((packed)); -+ -+struct ubsec_ctx_rsapriv { -+ volatile u_int16_t rpr_len; /* command length */ -+ volatile u_int16_t rpr_op; /* rsaprivate, 0x04 */ -+ volatile u_int16_t rpr_q_len; /* q (bits) */ -+ volatile u_int16_t rpr_p_len; /* p (bits) */ -+ u_int8_t rpr_buf[5 * 1024 / 8]; /* parameters: */ -+ /* p, q, dp, dq, pinv */ -+} __attribute__ ((packed)); -diff -Nur linux-3.0.4.orig/crypto/ocf/ubsec_ssb/ubsecvar.h linux-3.0.4/crypto/ocf/ubsec_ssb/ubsecvar.h ---- linux-3.0.4.orig/crypto/ocf/ubsec_ssb/ubsecvar.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/ubsec_ssb/ubsecvar.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,228 @@ -+ -+/* -+ * Copyright (c) 2008 Daniel Mueller (daniel@danm.de) -+ * Copyright (c) 2000 Theo de Raadt -+ * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com) -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR -+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, -+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF -+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * Effort sponsored in part by the Defense Advanced Research Projects -+ * Agency (DARPA) and Air Force Research Laboratory, Air Force -+ * Materiel Command, USAF, under agreement number F30602-01-2-0537. -+ * -+ */ -+ -+/* Maximum queue length */ -+#ifndef UBS_MAX_NQUEUE -+#define UBS_MAX_NQUEUE 60 -+#endif -+ -+#define UBS_MAX_SCATTER 64 /* Maximum scatter/gather depth */ -+ -+#ifndef UBS_MAX_AGGR -+#define UBS_MAX_AGGR 5 /* Maximum aggregation count */ -+#endif -+ -+#define UBSEC_CARD(sid) (((sid) & 0xf0000000) >> 28) -+#define UBSEC_SESSION(sid) ( (sid) & 0x0fffffff) -+#define UBSEC_SID(crd, sesn) (((crd) << 28) | ((sesn) & 0x0fffffff)) -+ -+#define UBS_DEF_RTY 0xff /* PCI Retry Timeout */ -+#define UBS_DEF_TOUT 0xff /* PCI TRDY Timeout */ -+#define UBS_DEF_CACHELINE 0x01 /* Cache Line setting */ -+ -+#define DEFAULT_HMAC_LEN 12 -+ -+struct ubsec_dma_alloc { -+ dma_addr_t dma_paddr; -+ void *dma_vaddr; -+ /* -+ bus_dmamap_t dma_map; -+ bus_dma_segment_t dma_seg; -+ */ -+ size_t dma_size; -+ /* -+ int dma_nseg; -+ */ -+}; -+ -+struct ubsec_q2 { -+ BSD_SIMPLEQ_ENTRY(ubsec_q2) q_next; -+ struct ubsec_dma_alloc q_mcr; -+ struct ubsec_dma_alloc q_ctx; -+ u_int q_type; -+}; -+ -+struct ubsec_q2_rng { -+ struct ubsec_q2 rng_q; -+ struct ubsec_dma_alloc rng_buf; -+ int rng_used; -+}; -+ -+/* C = (M ^ E) mod N */ -+#define UBS_MODEXP_PAR_M 0 -+#define UBS_MODEXP_PAR_E 1 -+#define UBS_MODEXP_PAR_N 2 -+struct ubsec_q2_modexp { -+ struct ubsec_q2 me_q; -+ struct cryptkop * me_krp; -+ struct ubsec_dma_alloc me_M; -+ struct ubsec_dma_alloc me_E; -+ struct ubsec_dma_alloc me_C; -+ struct ubsec_dma_alloc me_epb; -+ int me_modbits; -+ int me_shiftbits; -+ int me_normbits; -+}; -+ -+#define UBS_RSAPRIV_PAR_P 0 -+#define UBS_RSAPRIV_PAR_Q 1 -+#define UBS_RSAPRIV_PAR_DP 2 -+#define UBS_RSAPRIV_PAR_DQ 3 -+#define UBS_RSAPRIV_PAR_PINV 4 -+#define UBS_RSAPRIV_PAR_MSGIN 5 -+#define UBS_RSAPRIV_PAR_MSGOUT 6 -+struct ubsec_q2_rsapriv { -+ struct ubsec_q2 rpr_q; -+ struct cryptkop * rpr_krp; -+ struct ubsec_dma_alloc rpr_msgin; -+ struct ubsec_dma_alloc rpr_msgout; -+}; -+ -+#define UBSEC_RNG_BUFSIZ 16 /* measured in 32bit words */ -+ -+struct ubsec_dmachunk { -+ struct ubsec_mcr d_mcr; -+ struct ubsec_mcr_add d_mcradd[UBS_MAX_AGGR-1]; -+ struct ubsec_pktbuf d_sbuf[UBS_MAX_SCATTER-1]; -+ struct ubsec_pktbuf d_dbuf[UBS_MAX_SCATTER-1]; -+ u_int32_t d_macbuf[5]; -+ union { -+ struct ubsec_pktctx_aes256 ctxaes256; -+ struct ubsec_pktctx_aes192 ctxaes192; -+ struct ubsec_pktctx_des ctxdes; -+ struct ubsec_pktctx_aes128 ctxaes128; -+ struct ubsec_pktctx ctx; -+ } d_ctx; -+}; -+ -+struct ubsec_dma { -+ BSD_SIMPLEQ_ENTRY(ubsec_dma) d_next; -+ struct ubsec_dmachunk *d_dma; -+ struct ubsec_dma_alloc d_alloc; -+}; -+ -+#define UBS_FLAGS_KEY 0x01 /* has key accelerator */ -+#define UBS_FLAGS_LONGCTX 0x02 /* uses long ipsec ctx */ -+#define UBS_FLAGS_BIGKEY 0x04 /* 2048bit keys */ -+#define UBS_FLAGS_HWNORM 0x08 /* hardware normalization */ -+#define UBS_FLAGS_RNG 0x10 /* hardware rng */ -+#define UBS_FLAGS_AES 0x20 /* hardware AES support */ -+ -+struct ubsec_q { -+ BSD_SIMPLEQ_ENTRY(ubsec_q) q_next; -+ int q_nstacked_mcrs; -+ struct ubsec_q *q_stacked_mcr[UBS_MAX_AGGR-1]; -+ struct cryptop *q_crp; -+ struct ubsec_dma *q_dma; -+ -+ //struct mbuf *q_src_m, *q_dst_m; -+ struct sk_buff *q_src_m, *q_dst_m; -+ struct uio *q_src_io, *q_dst_io; -+ -+ /* -+ bus_dmamap_t q_src_map; -+ bus_dmamap_t q_dst_map; -+ */ -+ -+ /* DMA addresses for In-/Out packages */ -+ int q_src_len; -+ int q_dst_len; -+ struct ubsec_dma_alloc q_src_map[UBS_MAX_SCATTER]; -+ struct ubsec_dma_alloc q_dst_map[UBS_MAX_SCATTER]; -+ int q_has_dst; -+ -+ int q_sesn; -+ int q_flags; -+}; -+ -+struct ubsec_softc { -+ softc_device_decl sc_dev; -+ struct ssb_device *sdev; /* device backpointer */ -+ -+ struct device *sc_dv; /* generic device */ -+ void *sc_ih; /* interrupt handler cookie */ -+ int sc_flags; /* device specific flags */ -+ u_int32_t sc_statmask; /* interrupt status mask */ -+ int32_t sc_cid; /* crypto tag */ -+ BSD_SIMPLEQ_HEAD(,ubsec_q) sc_queue; /* packet queue, mcr1 */ -+ int sc_nqueue; /* count enqueued, mcr1 */ -+ BSD_SIMPLEQ_HEAD(,ubsec_q) sc_qchip; /* on chip, mcr1 */ -+ BSD_SIMPLEQ_HEAD(,ubsec_q) sc_freequeue; /* list of free queue elements */ -+ BSD_SIMPLEQ_HEAD(,ubsec_q2) sc_queue2; /* packet queue, mcr2 */ -+ int sc_nqueue2; /* count enqueued, mcr2 */ -+ BSD_SIMPLEQ_HEAD(,ubsec_q2) sc_qchip2; /* on chip, mcr2 */ -+ int sc_nsessions; /* # of sessions */ -+ struct ubsec_session *sc_sessions; /* sessions */ -+ int sc_rnghz; /* rng poll time */ -+ struct ubsec_q2_rng sc_rng; -+ struct ubsec_dma sc_dmaa[UBS_MAX_NQUEUE]; -+ struct ubsec_q *sc_queuea[UBS_MAX_NQUEUE]; -+ BSD_SIMPLEQ_HEAD(,ubsec_q2) sc_q2free; /* free list */ -+ spinlock_t sc_ringmtx; /* PE ring lock */ -+}; -+ -+#define UBSEC_QFLAGS_COPYOUTIV 0x1 -+ -+struct ubsec_session { -+ u_int32_t ses_used; -+ u_int32_t ses_key[8]; /* 3DES/AES key */ -+ u_int32_t ses_hminner[5]; /* hmac inner state */ -+ u_int32_t ses_hmouter[5]; /* hmac outer state */ -+ u_int32_t ses_iv[4]; /* [3]DES/AES iv */ -+ u_int32_t ses_keysize; /* AES key size */ -+ u_int32_t ses_mlen; /* hmac/hash length */ -+}; -+ -+struct ubsec_stats { -+ u_int64_t hst_ibytes; -+ u_int64_t hst_obytes; -+ u_int32_t hst_ipackets; -+ u_int32_t hst_opackets; -+ u_int32_t hst_invalid; -+ u_int32_t hst_nomem; -+ u_int32_t hst_queuefull; -+ u_int32_t hst_dmaerr; -+ u_int32_t hst_mcrerr; -+ u_int32_t hst_nodmafree; -+}; -+ -+struct ubsec_generic_ctx { -+ u_int32_t pc_key[8]; /* [3]DES/AES key */ -+ u_int32_t pc_hminner[5]; /* hmac inner state */ -+ u_int32_t pc_hmouter[5]; /* hmac outer state */ -+ u_int32_t pc_iv[4]; /* [3]DES/AES iv */ -+ u_int16_t pc_flags; /* flags, below */ -+ u_int16_t pc_offset; /* crypto offset */ -+ u_int16_t pc_type; /* Cryptographic operation */ -+}; -+ -diff -Nur linux-3.0.4.orig/crypto/ocf/uio.h linux-3.0.4/crypto/ocf/uio.h ---- linux-3.0.4.orig/crypto/ocf/uio.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/crypto/ocf/uio.h 2011-07-20 02:01:53.000000000 +0200 -@@ -0,0 +1,54 @@ -+#ifndef _OCF_UIO_H_ -+#define _OCF_UIO_H_ -+ -+#include -+ -+/* -+ * The linux uio.h doesn't have all we need. To be fully api compatible -+ * with the BSD cryptodev, we need to keep this around. Perhaps this can -+ * be moved back into the linux/uio.h -+ * -+ * Linux port done by David McCullough -+ * Copyright (C) 2006-2010 David McCullough -+ * Copyright (C) 2004-2005 Intel Corporation. -+ * -+ * LICENSE TERMS -+ * -+ * The free distribution and use of this software in both source and binary -+ * form is allowed (with or without changes) provided that: -+ * -+ * 1. distributions of this source code include the above copyright -+ * notice, this list of conditions and the following disclaimer; -+ * -+ * 2. distributions in binary form include the above copyright -+ * notice, this list of conditions and the following disclaimer -+ * in the documentation and/or other associated materials; -+ * -+ * 3. the copyright holder's name is not used to endorse products -+ * built using this software without specific written permission. -+ * -+ * ALTERNATIVELY, provided that this notice is retained in full, this product -+ * may be distributed under the terms of the GNU General Public License (GPL), -+ * in which case the provisions of the GPL apply INSTEAD OF those given above. -+ * -+ * DISCLAIMER -+ * -+ * This software is provided 'as is' with no explicit or implied warranties -+ * in respect of its properties, including, but not limited to, correctness -+ * and/or fitness for purpose. -+ * --------------------------------------------------------------------------- -+ */ -+ -+struct uio { -+ struct iovec *uio_iov; -+ int uio_iovcnt; -+ off_t uio_offset; -+ int uio_resid; -+#if 0 -+ enum uio_seg uio_segflg; -+ enum uio_rw uio_rw; -+ struct thread *uio_td; -+#endif -+}; -+ -+#endif -diff -Nur linux-3.0.4.orig/drivers/char/random.c linux-3.0.4/drivers/char/random.c ---- linux-3.0.4.orig/drivers/char/random.c 2011-08-29 22:56:30.000000000 +0200 -+++ linux-3.0.4/drivers/char/random.c 2011-10-17 04:36:27.356574299 +0200 -@@ -130,6 +130,9 @@ - * void add_interrupt_randomness(int irq); - * void add_disk_randomness(struct gendisk *disk); - * -+ * void random_input_words(__u32 *buf, size_t wordcount, int ent_count) -+ * int random_input_wait(void); -+ * - * add_input_randomness() uses the input layer interrupt timing, as well as - * the event type information from the hardware. - * -@@ -147,6 +150,13 @@ - * seek times do not make for good sources of entropy, as their seek - * times are usually fairly consistent. - * -+ * random_input_words() just provides a raw block of entropy to the input -+ * pool, such as from a hardware entropy generator. -+ * -+ * random_input_wait() suspends the caller until such time as the -+ * entropy pool falls below the write threshold, and returns a count of how -+ * much entropy (in bits) is needed to sustain the pool. -+ * - * All of these routines try to estimate how many bits of randomness a - * particular randomness source. They do this by keeping track of the - * first and second order deltas of the event timings. -@@ -722,6 +732,63 @@ - } - #endif - -+/* -+ * random_input_words - add bulk entropy to pool -+ * -+ * @buf: buffer to add -+ * @wordcount: number of __u32 words to add -+ * @ent_count: total amount of entropy (in bits) to credit -+ * -+ * this provides bulk input of entropy to the input pool -+ * -+ */ -+void random_input_words(__u32 *buf, size_t wordcount, int ent_count) -+{ -+ mix_pool_bytes(&input_pool, buf, wordcount*4); -+ -+ credit_entropy_bits(&input_pool, ent_count); -+ -+ DEBUG_ENT("crediting %d bits => %d\n", -+ ent_count, input_pool.entropy_count); -+ /* -+ * Wake up waiting processes if we have enough -+ * entropy. -+ */ -+ if (input_pool.entropy_count >= random_read_wakeup_thresh) -+ wake_up_interruptible(&random_read_wait); -+} -+EXPORT_SYMBOL(random_input_words); -+ -+/* -+ * random_input_wait - wait until random needs entropy -+ * -+ * this function sleeps until the /dev/random subsystem actually -+ * needs more entropy, and then return the amount of entropy -+ * that it would be nice to have added to the system. -+ */ -+int random_input_wait(void) -+{ -+ int count; -+ -+ wait_event_interruptible(random_write_wait, -+ input_pool.entropy_count < random_write_wakeup_thresh); -+ -+ count = random_write_wakeup_thresh - input_pool.entropy_count; -+ -+ /* likely we got woken up due to a signal */ -+ if (count <= 0) count = random_read_wakeup_thresh; -+ -+ DEBUG_ENT("requesting %d bits from input_wait()er %d<%d\n", -+ count, -+ input_pool.entropy_count, random_write_wakeup_thresh); -+ -+ return count; -+} -+EXPORT_SYMBOL(random_input_wait); -+ -+ -+#define EXTRACT_SIZE 10 -+ - /********************************************************************* - * - * Entropy extraction routines -diff -Nur linux-3.0.4.orig/drivers/char/random.c.orig linux-3.0.4/drivers/char/random.c.orig ---- linux-3.0.4.orig/drivers/char/random.c.orig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/drivers/char/random.c.orig 2011-08-29 22:56:30.000000000 +0200 -@@ -0,0 +1,1349 @@ -+/* -+ * random.c -- A strong random number generator -+ * -+ * Copyright Matt Mackall , 2003, 2004, 2005 -+ * -+ * Copyright Theodore Ts'o, 1994, 1995, 1996, 1997, 1998, 1999. All -+ * rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, and the entire permission notice in its entirety, -+ * including the disclaimer of warranties. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The name of the author may not be used to endorse or promote -+ * products derived from this software without specific prior -+ * written permission. -+ * -+ * ALTERNATIVELY, this product may be distributed under the terms of -+ * the GNU General Public License, in which case the provisions of the GPL are -+ * required INSTEAD OF the above restrictions. (This clause is -+ * necessary due to a potential bad interaction between the GPL and -+ * the restrictions contained in a BSD-style copyright.) -+ * -+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED -+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ALL OF -+ * WHICH ARE HEREBY DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT -+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE -+ * USE OF THIS SOFTWARE, EVEN IF NOT ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ */ -+ -+/* -+ * (now, with legal B.S. out of the way.....) -+ * -+ * This routine gathers environmental noise from device drivers, etc., -+ * and returns good random numbers, suitable for cryptographic use. -+ * Besides the obvious cryptographic uses, these numbers are also good -+ * for seeding TCP sequence numbers, and other places where it is -+ * desirable to have numbers which are not only random, but hard to -+ * predict by an attacker. -+ * -+ * Theory of operation -+ * =================== -+ * -+ * Computers are very predictable devices. Hence it is extremely hard -+ * to produce truly random numbers on a computer --- as opposed to -+ * pseudo-random numbers, which can easily generated by using a -+ * algorithm. Unfortunately, it is very easy for attackers to guess -+ * the sequence of pseudo-random number generators, and for some -+ * applications this is not acceptable. So instead, we must try to -+ * gather "environmental noise" from the computer's environment, which -+ * must be hard for outside attackers to observe, and use that to -+ * generate random numbers. In a Unix environment, this is best done -+ * from inside the kernel. -+ * -+ * Sources of randomness from the environment include inter-keyboard -+ * timings, inter-interrupt timings from some interrupts, and other -+ * events which are both (a) non-deterministic and (b) hard for an -+ * outside observer to measure. Randomness from these sources are -+ * added to an "entropy pool", which is mixed using a CRC-like function. -+ * This is not cryptographically strong, but it is adequate assuming -+ * the randomness is not chosen maliciously, and it is fast enough that -+ * the overhead of doing it on every interrupt is very reasonable. -+ * As random bytes are mixed into the entropy pool, the routines keep -+ * an *estimate* of how many bits of randomness have been stored into -+ * the random number generator's internal state. -+ * -+ * When random bytes are desired, they are obtained by taking the SHA -+ * hash of the contents of the "entropy pool". The SHA hash avoids -+ * exposing the internal state of the entropy pool. It is believed to -+ * be computationally infeasible to derive any useful information -+ * about the input of SHA from its output. Even if it is possible to -+ * analyze SHA in some clever way, as long as the amount of data -+ * returned from the generator is less than the inherent entropy in -+ * the pool, the output data is totally unpredictable. For this -+ * reason, the routine decreases its internal estimate of how many -+ * bits of "true randomness" are contained in the entropy pool as it -+ * outputs random numbers. -+ * -+ * If this estimate goes to zero, the routine can still generate -+ * random numbers; however, an attacker may (at least in theory) be -+ * able to infer the future output of the generator from prior -+ * outputs. This requires successful cryptanalysis of SHA, which is -+ * not believed to be feasible, but there is a remote possibility. -+ * Nonetheless, these numbers should be useful for the vast majority -+ * of purposes. -+ * -+ * Exported interfaces ---- output -+ * =============================== -+ * -+ * There are three exported interfaces; the first is one designed to -+ * be used from within the kernel: -+ * -+ * void get_random_bytes(void *buf, int nbytes); -+ * -+ * This interface will return the requested number of random bytes, -+ * and place it in the requested buffer. -+ * -+ * The two other interfaces are two character devices /dev/random and -+ * /dev/urandom. /dev/random is suitable for use when very high -+ * quality randomness is desired (for example, for key generation or -+ * one-time pads), as it will only return a maximum of the number of -+ * bits of randomness (as estimated by the random number generator) -+ * contained in the entropy pool. -+ * -+ * The /dev/urandom device does not have this limit, and will return -+ * as many bytes as are requested. As more and more random bytes are -+ * requested without giving time for the entropy pool to recharge, -+ * this will result in random numbers that are merely cryptographically -+ * strong. For many applications, however, this is acceptable. -+ * -+ * Exported interfaces ---- input -+ * ============================== -+ * -+ * The current exported interfaces for gathering environmental noise -+ * from the devices are: -+ * -+ * void add_input_randomness(unsigned int type, unsigned int code, -+ * unsigned int value); -+ * void add_interrupt_randomness(int irq); -+ * void add_disk_randomness(struct gendisk *disk); -+ * -+ * add_input_randomness() uses the input layer interrupt timing, as well as -+ * the event type information from the hardware. -+ * -+ * add_interrupt_randomness() uses the inter-interrupt timing as random -+ * inputs to the entropy pool. Note that not all interrupts are good -+ * sources of randomness! For example, the timer interrupts is not a -+ * good choice, because the periodicity of the interrupts is too -+ * regular, and hence predictable to an attacker. Network Interface -+ * Controller interrupts are a better measure, since the timing of the -+ * NIC interrupts are more unpredictable. -+ * -+ * add_disk_randomness() uses what amounts to the seek time of block -+ * layer request events, on a per-disk_devt basis, as input to the -+ * entropy pool. Note that high-speed solid state drives with very low -+ * seek times do not make for good sources of entropy, as their seek -+ * times are usually fairly consistent. -+ * -+ * All of these routines try to estimate how many bits of randomness a -+ * particular randomness source. They do this by keeping track of the -+ * first and second order deltas of the event timings. -+ * -+ * Ensuring unpredictability at system startup -+ * ============================================ -+ * -+ * When any operating system starts up, it will go through a sequence -+ * of actions that are fairly predictable by an adversary, especially -+ * if the start-up does not involve interaction with a human operator. -+ * This reduces the actual number of bits of unpredictability in the -+ * entropy pool below the value in entropy_count. In order to -+ * counteract this effect, it helps to carry information in the -+ * entropy pool across shut-downs and start-ups. To do this, put the -+ * following lines an appropriate script which is run during the boot -+ * sequence: -+ * -+ * echo "Initializing random number generator..." -+ * random_seed=/var/run/random-seed -+ * # Carry a random seed from start-up to start-up -+ * # Load and then save the whole entropy pool -+ * if [ -f $random_seed ]; then -+ * cat $random_seed >/dev/urandom -+ * else -+ * touch $random_seed -+ * fi -+ * chmod 600 $random_seed -+ * dd if=/dev/urandom of=$random_seed count=1 bs=512 -+ * -+ * and the following lines in an appropriate script which is run as -+ * the system is shutdown: -+ * -+ * # Carry a random seed from shut-down to start-up -+ * # Save the whole entropy pool -+ * echo "Saving random seed..." -+ * random_seed=/var/run/random-seed -+ * touch $random_seed -+ * chmod 600 $random_seed -+ * dd if=/dev/urandom of=$random_seed count=1 bs=512 -+ * -+ * For example, on most modern systems using the System V init -+ * scripts, such code fragments would be found in -+ * /etc/rc.d/init.d/random. On older Linux systems, the correct script -+ * location might be in /etc/rcb.d/rc.local or /etc/rc.d/rc.0. -+ * -+ * Effectively, these commands cause the contents of the entropy pool -+ * to be saved at shut-down time and reloaded into the entropy pool at -+ * start-up. (The 'dd' in the addition to the bootup script is to -+ * make sure that /etc/random-seed is different for every start-up, -+ * even if the system crashes without executing rc.0.) Even with -+ * complete knowledge of the start-up activities, predicting the state -+ * of the entropy pool requires knowledge of the previous history of -+ * the system. -+ * -+ * Configuring the /dev/random driver under Linux -+ * ============================================== -+ * -+ * The /dev/random driver under Linux uses minor numbers 8 and 9 of -+ * the /dev/mem major number (#1). So if your system does not have -+ * /dev/random and /dev/urandom created already, they can be created -+ * by using the commands: -+ * -+ * mknod /dev/random c 1 8 -+ * mknod /dev/urandom c 1 9 -+ * -+ * Acknowledgements: -+ * ================= -+ * -+ * Ideas for constructing this random number generator were derived -+ * from Pretty Good Privacy's random number generator, and from private -+ * discussions with Phil Karn. Colin Plumb provided a faster random -+ * number generator, which speed up the mixing function of the entropy -+ * pool, taken from PGPfone. Dale Worley has also contributed many -+ * useful ideas and suggestions to improve this driver. -+ * -+ * Any flaws in the design are solely my responsibility, and should -+ * not be attributed to the Phil, Colin, or any of authors of PGP. -+ * -+ * Further background information on this topic may be obtained from -+ * RFC 1750, "Randomness Recommendations for Security", by Donald -+ * Eastlake, Steve Crocker, and Jeff Schiller. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#ifdef CONFIG_GENERIC_HARDIRQS -+# include -+#endif -+ -+#include -+#include -+#include -+#include -+ -+/* -+ * Configuration information -+ */ -+#define INPUT_POOL_WORDS 128 -+#define OUTPUT_POOL_WORDS 32 -+#define SEC_XFER_SIZE 512 -+#define EXTRACT_SIZE 10 -+ -+/* -+ * The minimum number of bits of entropy before we wake up a read on -+ * /dev/random. Should be enough to do a significant reseed. -+ */ -+static int random_read_wakeup_thresh = 64; -+ -+/* -+ * If the entropy count falls under this number of bits, then we -+ * should wake up processes which are selecting or polling on write -+ * access to /dev/random. -+ */ -+static int random_write_wakeup_thresh = 128; -+ -+/* -+ * When the input pool goes over trickle_thresh, start dropping most -+ * samples to avoid wasting CPU time and reduce lock contention. -+ */ -+ -+static int trickle_thresh __read_mostly = INPUT_POOL_WORDS * 28; -+ -+static DEFINE_PER_CPU(int, trickle_count); -+ -+/* -+ * A pool of size .poolwords is stirred with a primitive polynomial -+ * of degree .poolwords over GF(2). The taps for various sizes are -+ * defined below. They are chosen to be evenly spaced (minimum RMS -+ * distance from evenly spaced; the numbers in the comments are a -+ * scaled squared error sum) except for the last tap, which is 1 to -+ * get the twisting happening as fast as possible. -+ */ -+static struct poolinfo { -+ int poolwords; -+ int tap1, tap2, tap3, tap4, tap5; -+} poolinfo_table[] = { -+ /* x^128 + x^103 + x^76 + x^51 +x^25 + x + 1 -- 105 */ -+ { 128, 103, 76, 51, 25, 1 }, -+ /* x^32 + x^26 + x^20 + x^14 + x^7 + x + 1 -- 15 */ -+ { 32, 26, 20, 14, 7, 1 }, -+#if 0 -+ /* x^2048 + x^1638 + x^1231 + x^819 + x^411 + x + 1 -- 115 */ -+ { 2048, 1638, 1231, 819, 411, 1 }, -+ -+ /* x^1024 + x^817 + x^615 + x^412 + x^204 + x + 1 -- 290 */ -+ { 1024, 817, 615, 412, 204, 1 }, -+ -+ /* x^1024 + x^819 + x^616 + x^410 + x^207 + x^2 + 1 -- 115 */ -+ { 1024, 819, 616, 410, 207, 2 }, -+ -+ /* x^512 + x^411 + x^308 + x^208 + x^104 + x + 1 -- 225 */ -+ { 512, 411, 308, 208, 104, 1 }, -+ -+ /* x^512 + x^409 + x^307 + x^206 + x^102 + x^2 + 1 -- 95 */ -+ { 512, 409, 307, 206, 102, 2 }, -+ /* x^512 + x^409 + x^309 + x^205 + x^103 + x^2 + 1 -- 95 */ -+ { 512, 409, 309, 205, 103, 2 }, -+ -+ /* x^256 + x^205 + x^155 + x^101 + x^52 + x + 1 -- 125 */ -+ { 256, 205, 155, 101, 52, 1 }, -+ -+ /* x^128 + x^103 + x^78 + x^51 + x^27 + x^2 + 1 -- 70 */ -+ { 128, 103, 78, 51, 27, 2 }, -+ -+ /* x^64 + x^52 + x^39 + x^26 + x^14 + x + 1 -- 15 */ -+ { 64, 52, 39, 26, 14, 1 }, -+#endif -+}; -+ -+#define POOLBITS poolwords*32 -+#define POOLBYTES poolwords*4 -+ -+/* -+ * For the purposes of better mixing, we use the CRC-32 polynomial as -+ * well to make a twisted Generalized Feedback Shift Reigster -+ * -+ * (See M. Matsumoto & Y. Kurita, 1992. Twisted GFSR generators. ACM -+ * Transactions on Modeling and Computer Simulation 2(3):179-194. -+ * Also see M. Matsumoto & Y. Kurita, 1994. Twisted GFSR generators -+ * II. ACM Transactions on Mdeling and Computer Simulation 4:254-266) -+ * -+ * Thanks to Colin Plumb for suggesting this. -+ * -+ * We have not analyzed the resultant polynomial to prove it primitive; -+ * in fact it almost certainly isn't. Nonetheless, the irreducible factors -+ * of a random large-degree polynomial over GF(2) are more than large enough -+ * that periodicity is not a concern. -+ * -+ * The input hash is much less sensitive than the output hash. All -+ * that we want of it is that it be a good non-cryptographic hash; -+ * i.e. it not produce collisions when fed "random" data of the sort -+ * we expect to see. As long as the pool state differs for different -+ * inputs, we have preserved the input entropy and done a good job. -+ * The fact that an intelligent attacker can construct inputs that -+ * will produce controlled alterations to the pool's state is not -+ * important because we don't consider such inputs to contribute any -+ * randomness. The only property we need with respect to them is that -+ * the attacker can't increase his/her knowledge of the pool's state. -+ * Since all additions are reversible (knowing the final state and the -+ * input, you can reconstruct the initial state), if an attacker has -+ * any uncertainty about the initial state, he/she can only shuffle -+ * that uncertainty about, but never cause any collisions (which would -+ * decrease the uncertainty). -+ * -+ * The chosen system lets the state of the pool be (essentially) the input -+ * modulo the generator polymnomial. Now, for random primitive polynomials, -+ * this is a universal class of hash functions, meaning that the chance -+ * of a collision is limited by the attacker's knowledge of the generator -+ * polynomail, so if it is chosen at random, an attacker can never force -+ * a collision. Here, we use a fixed polynomial, but we *can* assume that -+ * ###--> it is unknown to the processes generating the input entropy. <-### -+ * Because of this important property, this is a good, collision-resistant -+ * hash; hash collisions will occur no more often than chance. -+ */ -+ -+/* -+ * Static global variables -+ */ -+static DECLARE_WAIT_QUEUE_HEAD(random_read_wait); -+static DECLARE_WAIT_QUEUE_HEAD(random_write_wait); -+static struct fasync_struct *fasync; -+ -+#if 0 -+static int debug; -+module_param(debug, bool, 0644); -+#define DEBUG_ENT(fmt, arg...) do { \ -+ if (debug) \ -+ printk(KERN_DEBUG "random %04d %04d %04d: " \ -+ fmt,\ -+ input_pool.entropy_count,\ -+ blocking_pool.entropy_count,\ -+ nonblocking_pool.entropy_count,\ -+ ## arg); } while (0) -+#else -+#define DEBUG_ENT(fmt, arg...) do {} while (0) -+#endif -+ -+/********************************************************************** -+ * -+ * OS independent entropy store. Here are the functions which handle -+ * storing entropy in an entropy pool. -+ * -+ **********************************************************************/ -+ -+struct entropy_store; -+struct entropy_store { -+ /* read-only data: */ -+ struct poolinfo *poolinfo; -+ __u32 *pool; -+ const char *name; -+ struct entropy_store *pull; -+ int limit; -+ -+ /* read-write data: */ -+ spinlock_t lock; -+ unsigned add_ptr; -+ int entropy_count; -+ int input_rotate; -+ __u8 last_data[EXTRACT_SIZE]; -+}; -+ -+static __u32 input_pool_data[INPUT_POOL_WORDS]; -+static __u32 blocking_pool_data[OUTPUT_POOL_WORDS]; -+static __u32 nonblocking_pool_data[OUTPUT_POOL_WORDS]; -+ -+static struct entropy_store input_pool = { -+ .poolinfo = &poolinfo_table[0], -+ .name = "input", -+ .limit = 1, -+ .lock = __SPIN_LOCK_UNLOCKED(&input_pool.lock), -+ .pool = input_pool_data -+}; -+ -+static struct entropy_store blocking_pool = { -+ .poolinfo = &poolinfo_table[1], -+ .name = "blocking", -+ .limit = 1, -+ .pull = &input_pool, -+ .lock = __SPIN_LOCK_UNLOCKED(&blocking_pool.lock), -+ .pool = blocking_pool_data -+}; -+ -+static struct entropy_store nonblocking_pool = { -+ .poolinfo = &poolinfo_table[1], -+ .name = "nonblocking", -+ .pull = &input_pool, -+ .lock = __SPIN_LOCK_UNLOCKED(&nonblocking_pool.lock), -+ .pool = nonblocking_pool_data -+}; -+ -+/* -+ * This function adds bytes into the entropy "pool". It does not -+ * update the entropy estimate. The caller should call -+ * credit_entropy_bits if this is appropriate. -+ * -+ * The pool is stirred with a primitive polynomial of the appropriate -+ * degree, and then twisted. We twist by three bits at a time because -+ * it's cheap to do so and helps slightly in the expected case where -+ * the entropy is concentrated in the low-order bits. -+ */ -+static void mix_pool_bytes_extract(struct entropy_store *r, const void *in, -+ int nbytes, __u8 out[64]) -+{ -+ static __u32 const twist_table[8] = { -+ 0x00000000, 0x3b6e20c8, 0x76dc4190, 0x4db26158, -+ 0xedb88320, 0xd6d6a3e8, 0x9b64c2b0, 0xa00ae278 }; -+ unsigned long i, j, tap1, tap2, tap3, tap4, tap5; -+ int input_rotate; -+ int wordmask = r->poolinfo->poolwords - 1; -+ const char *bytes = in; -+ __u32 w; -+ unsigned long flags; -+ -+ /* Taps are constant, so we can load them without holding r->lock. */ -+ tap1 = r->poolinfo->tap1; -+ tap2 = r->poolinfo->tap2; -+ tap3 = r->poolinfo->tap3; -+ tap4 = r->poolinfo->tap4; -+ tap5 = r->poolinfo->tap5; -+ -+ spin_lock_irqsave(&r->lock, flags); -+ input_rotate = r->input_rotate; -+ i = r->add_ptr; -+ -+ /* mix one byte at a time to simplify size handling and churn faster */ -+ while (nbytes--) { -+ w = rol32(*bytes++, input_rotate & 31); -+ i = (i - 1) & wordmask; -+ -+ /* XOR in the various taps */ -+ w ^= r->pool[i]; -+ w ^= r->pool[(i + tap1) & wordmask]; -+ w ^= r->pool[(i + tap2) & wordmask]; -+ w ^= r->pool[(i + tap3) & wordmask]; -+ w ^= r->pool[(i + tap4) & wordmask]; -+ w ^= r->pool[(i + tap5) & wordmask]; -+ -+ /* Mix the result back in with a twist */ -+ r->pool[i] = (w >> 3) ^ twist_table[w & 7]; -+ -+ /* -+ * Normally, we add 7 bits of rotation to the pool. -+ * At the beginning of the pool, add an extra 7 bits -+ * rotation, so that successive passes spread the -+ * input bits across the pool evenly. -+ */ -+ input_rotate += i ? 7 : 14; -+ } -+ -+ r->input_rotate = input_rotate; -+ r->add_ptr = i; -+ -+ if (out) -+ for (j = 0; j < 16; j++) -+ ((__u32 *)out)[j] = r->pool[(i - j) & wordmask]; -+ -+ spin_unlock_irqrestore(&r->lock, flags); -+} -+ -+static void mix_pool_bytes(struct entropy_store *r, const void *in, int bytes) -+{ -+ mix_pool_bytes_extract(r, in, bytes, NULL); -+} -+ -+/* -+ * Credit (or debit) the entropy store with n bits of entropy -+ */ -+static void credit_entropy_bits(struct entropy_store *r, int nbits) -+{ -+ unsigned long flags; -+ int entropy_count; -+ -+ if (!nbits) -+ return; -+ -+ spin_lock_irqsave(&r->lock, flags); -+ -+ DEBUG_ENT("added %d entropy credits to %s\n", nbits, r->name); -+ entropy_count = r->entropy_count; -+ entropy_count += nbits; -+ if (entropy_count < 0) { -+ DEBUG_ENT("negative entropy/overflow\n"); -+ entropy_count = 0; -+ } else if (entropy_count > r->poolinfo->POOLBITS) -+ entropy_count = r->poolinfo->POOLBITS; -+ r->entropy_count = entropy_count; -+ -+ /* should we wake readers? */ -+ if (r == &input_pool && entropy_count >= random_read_wakeup_thresh) { -+ wake_up_interruptible(&random_read_wait); -+ kill_fasync(&fasync, SIGIO, POLL_IN); -+ } -+ spin_unlock_irqrestore(&r->lock, flags); -+} -+ -+/********************************************************************* -+ * -+ * Entropy input management -+ * -+ *********************************************************************/ -+ -+/* There is one of these per entropy source */ -+struct timer_rand_state { -+ cycles_t last_time; -+ long last_delta, last_delta2; -+ unsigned dont_count_entropy:1; -+}; -+ -+#ifndef CONFIG_GENERIC_HARDIRQS -+ -+static struct timer_rand_state *irq_timer_state[NR_IRQS]; -+ -+static struct timer_rand_state *get_timer_rand_state(unsigned int irq) -+{ -+ return irq_timer_state[irq]; -+} -+ -+static void set_timer_rand_state(unsigned int irq, -+ struct timer_rand_state *state) -+{ -+ irq_timer_state[irq] = state; -+} -+ -+#else -+ -+static struct timer_rand_state *get_timer_rand_state(unsigned int irq) -+{ -+ struct irq_desc *desc; -+ -+ desc = irq_to_desc(irq); -+ -+ return desc->timer_rand_state; -+} -+ -+static void set_timer_rand_state(unsigned int irq, -+ struct timer_rand_state *state) -+{ -+ struct irq_desc *desc; -+ -+ desc = irq_to_desc(irq); -+ -+ desc->timer_rand_state = state; -+} -+#endif -+ -+static struct timer_rand_state input_timer_state; -+ -+/* -+ * This function adds entropy to the entropy "pool" by using timing -+ * delays. It uses the timer_rand_state structure to make an estimate -+ * of how many bits of entropy this call has added to the pool. -+ * -+ * The number "num" is also added to the pool - it should somehow describe -+ * the type of event which just happened. This is currently 0-255 for -+ * keyboard scan codes, and 256 upwards for interrupts. -+ * -+ */ -+static void add_timer_randomness(struct timer_rand_state *state, unsigned num) -+{ -+ struct { -+ cycles_t cycles; -+ long jiffies; -+ unsigned num; -+ } sample; -+ long delta, delta2, delta3; -+ -+ preempt_disable(); -+ /* if over the trickle threshold, use only 1 in 4096 samples */ -+ if (input_pool.entropy_count > trickle_thresh && -+ ((__this_cpu_inc_return(trickle_count) - 1) & 0xfff)) -+ goto out; -+ -+ sample.jiffies = jiffies; -+ sample.cycles = get_cycles(); -+ sample.num = num; -+ mix_pool_bytes(&input_pool, &sample, sizeof(sample)); -+ -+ /* -+ * Calculate number of bits of randomness we probably added. -+ * We take into account the first, second and third-order deltas -+ * in order to make our estimate. -+ */ -+ -+ if (!state->dont_count_entropy) { -+ delta = sample.jiffies - state->last_time; -+ state->last_time = sample.jiffies; -+ -+ delta2 = delta - state->last_delta; -+ state->last_delta = delta; -+ -+ delta3 = delta2 - state->last_delta2; -+ state->last_delta2 = delta2; -+ -+ if (delta < 0) -+ delta = -delta; -+ if (delta2 < 0) -+ delta2 = -delta2; -+ if (delta3 < 0) -+ delta3 = -delta3; -+ if (delta > delta2) -+ delta = delta2; -+ if (delta > delta3) -+ delta = delta3; -+ -+ /* -+ * delta is now minimum absolute delta. -+ * Round down by 1 bit on general principles, -+ * and limit entropy entimate to 12 bits. -+ */ -+ credit_entropy_bits(&input_pool, -+ min_t(int, fls(delta>>1), 11)); -+ } -+out: -+ preempt_enable(); -+} -+ -+void add_input_randomness(unsigned int type, unsigned int code, -+ unsigned int value) -+{ -+ static unsigned char last_value; -+ -+ /* ignore autorepeat and the like */ -+ if (value == last_value) -+ return; -+ -+ DEBUG_ENT("input event\n"); -+ last_value = value; -+ add_timer_randomness(&input_timer_state, -+ (type << 4) ^ code ^ (code >> 4) ^ value); -+} -+EXPORT_SYMBOL_GPL(add_input_randomness); -+ -+void add_interrupt_randomness(int irq) -+{ -+ struct timer_rand_state *state; -+ -+ state = get_timer_rand_state(irq); -+ -+ if (state == NULL) -+ return; -+ -+ DEBUG_ENT("irq event %d\n", irq); -+ add_timer_randomness(state, 0x100 + irq); -+} -+ -+#ifdef CONFIG_BLOCK -+void add_disk_randomness(struct gendisk *disk) -+{ -+ if (!disk || !disk->random) -+ return; -+ /* first major is 1, so we get >= 0x200 here */ -+ DEBUG_ENT("disk event %d:%d\n", -+ MAJOR(disk_devt(disk)), MINOR(disk_devt(disk))); -+ -+ add_timer_randomness(disk->random, 0x100 + disk_devt(disk)); -+} -+#endif -+ -+/********************************************************************* -+ * -+ * Entropy extraction routines -+ * -+ *********************************************************************/ -+ -+static ssize_t extract_entropy(struct entropy_store *r, void *buf, -+ size_t nbytes, int min, int rsvd); -+ -+/* -+ * This utility inline function is responsible for transferring entropy -+ * from the primary pool to the secondary extraction pool. We make -+ * sure we pull enough for a 'catastrophic reseed'. -+ */ -+static void xfer_secondary_pool(struct entropy_store *r, size_t nbytes) -+{ -+ __u32 tmp[OUTPUT_POOL_WORDS]; -+ -+ if (r->pull && r->entropy_count < nbytes * 8 && -+ r->entropy_count < r->poolinfo->POOLBITS) { -+ /* If we're limited, always leave two wakeup worth's BITS */ -+ int rsvd = r->limit ? 0 : random_read_wakeup_thresh/4; -+ int bytes = nbytes; -+ -+ /* pull at least as many as BYTES as wakeup BITS */ -+ bytes = max_t(int, bytes, random_read_wakeup_thresh / 8); -+ /* but never more than the buffer size */ -+ bytes = min_t(int, bytes, sizeof(tmp)); -+ -+ DEBUG_ENT("going to reseed %s with %d bits " -+ "(%d of %d requested)\n", -+ r->name, bytes * 8, nbytes * 8, r->entropy_count); -+ -+ bytes = extract_entropy(r->pull, tmp, bytes, -+ random_read_wakeup_thresh / 8, rsvd); -+ mix_pool_bytes(r, tmp, bytes); -+ credit_entropy_bits(r, bytes*8); -+ } -+} -+ -+/* -+ * These functions extracts randomness from the "entropy pool", and -+ * returns it in a buffer. -+ * -+ * The min parameter specifies the minimum amount we can pull before -+ * failing to avoid races that defeat catastrophic reseeding while the -+ * reserved parameter indicates how much entropy we must leave in the -+ * pool after each pull to avoid starving other readers. -+ * -+ * Note: extract_entropy() assumes that .poolwords is a multiple of 16 words. -+ */ -+ -+static size_t account(struct entropy_store *r, size_t nbytes, int min, -+ int reserved) -+{ -+ unsigned long flags; -+ -+ /* Hold lock while accounting */ -+ spin_lock_irqsave(&r->lock, flags); -+ -+ BUG_ON(r->entropy_count > r->poolinfo->POOLBITS); -+ DEBUG_ENT("trying to extract %d bits from %s\n", -+ nbytes * 8, r->name); -+ -+ /* Can we pull enough? */ -+ if (r->entropy_count / 8 < min + reserved) { -+ nbytes = 0; -+ } else { -+ /* If limited, never pull more than available */ -+ if (r->limit && nbytes + reserved >= r->entropy_count / 8) -+ nbytes = r->entropy_count/8 - reserved; -+ -+ if (r->entropy_count / 8 >= nbytes + reserved) -+ r->entropy_count -= nbytes*8; -+ else -+ r->entropy_count = reserved; -+ -+ if (r->entropy_count < random_write_wakeup_thresh) { -+ wake_up_interruptible(&random_write_wait); -+ kill_fasync(&fasync, SIGIO, POLL_OUT); -+ } -+ } -+ -+ DEBUG_ENT("debiting %d entropy credits from %s%s\n", -+ nbytes * 8, r->name, r->limit ? "" : " (unlimited)"); -+ -+ spin_unlock_irqrestore(&r->lock, flags); -+ -+ return nbytes; -+} -+ -+static void extract_buf(struct entropy_store *r, __u8 *out) -+{ -+ int i; -+ __u32 hash[5], workspace[SHA_WORKSPACE_WORDS]; -+ __u8 extract[64]; -+ -+ /* Generate a hash across the pool, 16 words (512 bits) at a time */ -+ sha_init(hash); -+ for (i = 0; i < r->poolinfo->poolwords; i += 16) -+ sha_transform(hash, (__u8 *)(r->pool + i), workspace); -+ -+ /* -+ * We mix the hash back into the pool to prevent backtracking -+ * attacks (where the attacker knows the state of the pool -+ * plus the current outputs, and attempts to find previous -+ * ouputs), unless the hash function can be inverted. By -+ * mixing at least a SHA1 worth of hash data back, we make -+ * brute-forcing the feedback as hard as brute-forcing the -+ * hash. -+ */ -+ mix_pool_bytes_extract(r, hash, sizeof(hash), extract); -+ -+ /* -+ * To avoid duplicates, we atomically extract a portion of the -+ * pool while mixing, and hash one final time. -+ */ -+ sha_transform(hash, extract, workspace); -+ memset(extract, 0, sizeof(extract)); -+ memset(workspace, 0, sizeof(workspace)); -+ -+ /* -+ * In case the hash function has some recognizable output -+ * pattern, we fold it in half. Thus, we always feed back -+ * twice as much data as we output. -+ */ -+ hash[0] ^= hash[3]; -+ hash[1] ^= hash[4]; -+ hash[2] ^= rol32(hash[2], 16); -+ memcpy(out, hash, EXTRACT_SIZE); -+ memset(hash, 0, sizeof(hash)); -+} -+ -+static ssize_t extract_entropy(struct entropy_store *r, void *buf, -+ size_t nbytes, int min, int reserved) -+{ -+ ssize_t ret = 0, i; -+ __u8 tmp[EXTRACT_SIZE]; -+ unsigned long flags; -+ -+ xfer_secondary_pool(r, nbytes); -+ nbytes = account(r, nbytes, min, reserved); -+ -+ while (nbytes) { -+ extract_buf(r, tmp); -+ -+ if (fips_enabled) { -+ spin_lock_irqsave(&r->lock, flags); -+ if (!memcmp(tmp, r->last_data, EXTRACT_SIZE)) -+ panic("Hardware RNG duplicated output!\n"); -+ memcpy(r->last_data, tmp, EXTRACT_SIZE); -+ spin_unlock_irqrestore(&r->lock, flags); -+ } -+ i = min_t(int, nbytes, EXTRACT_SIZE); -+ memcpy(buf, tmp, i); -+ nbytes -= i; -+ buf += i; -+ ret += i; -+ } -+ -+ /* Wipe data just returned from memory */ -+ memset(tmp, 0, sizeof(tmp)); -+ -+ return ret; -+} -+ -+static ssize_t extract_entropy_user(struct entropy_store *r, void __user *buf, -+ size_t nbytes) -+{ -+ ssize_t ret = 0, i; -+ __u8 tmp[EXTRACT_SIZE]; -+ -+ xfer_secondary_pool(r, nbytes); -+ nbytes = account(r, nbytes, 0, 0); -+ -+ while (nbytes) { -+ if (need_resched()) { -+ if (signal_pending(current)) { -+ if (ret == 0) -+ ret = -ERESTARTSYS; -+ break; -+ } -+ schedule(); -+ } -+ -+ extract_buf(r, tmp); -+ i = min_t(int, nbytes, EXTRACT_SIZE); -+ if (copy_to_user(buf, tmp, i)) { -+ ret = -EFAULT; -+ break; -+ } -+ -+ nbytes -= i; -+ buf += i; -+ ret += i; -+ } -+ -+ /* Wipe data just returned from memory */ -+ memset(tmp, 0, sizeof(tmp)); -+ -+ return ret; -+} -+ -+/* -+ * This function is the exported kernel interface. It returns some -+ * number of good random numbers, suitable for seeding TCP sequence -+ * numbers, etc. -+ */ -+void get_random_bytes(void *buf, int nbytes) -+{ -+ extract_entropy(&nonblocking_pool, buf, nbytes, 0, 0); -+} -+EXPORT_SYMBOL(get_random_bytes); -+ -+/* -+ * init_std_data - initialize pool with system data -+ * -+ * @r: pool to initialize -+ * -+ * This function clears the pool's entropy count and mixes some system -+ * data into the pool to prepare it for use. The pool is not cleared -+ * as that can only decrease the entropy in the pool. -+ */ -+static void init_std_data(struct entropy_store *r) -+{ -+ ktime_t now; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&r->lock, flags); -+ r->entropy_count = 0; -+ spin_unlock_irqrestore(&r->lock, flags); -+ -+ now = ktime_get_real(); -+ mix_pool_bytes(r, &now, sizeof(now)); -+ mix_pool_bytes(r, utsname(), sizeof(*(utsname()))); -+} -+ -+static int rand_initialize(void) -+{ -+ init_std_data(&input_pool); -+ init_std_data(&blocking_pool); -+ init_std_data(&nonblocking_pool); -+ return 0; -+} -+module_init(rand_initialize); -+ -+void rand_initialize_irq(int irq) -+{ -+ struct timer_rand_state *state; -+ -+ state = get_timer_rand_state(irq); -+ -+ if (state) -+ return; -+ -+ /* -+ * If kzalloc returns null, we just won't use that entropy -+ * source. -+ */ -+ state = kzalloc(sizeof(struct timer_rand_state), GFP_KERNEL); -+ if (state) -+ set_timer_rand_state(irq, state); -+} -+ -+#ifdef CONFIG_BLOCK -+void rand_initialize_disk(struct gendisk *disk) -+{ -+ struct timer_rand_state *state; -+ -+ /* -+ * If kzalloc returns null, we just won't use that entropy -+ * source. -+ */ -+ state = kzalloc(sizeof(struct timer_rand_state), GFP_KERNEL); -+ if (state) -+ disk->random = state; -+} -+#endif -+ -+static ssize_t -+random_read(struct file *file, char __user *buf, size_t nbytes, loff_t *ppos) -+{ -+ ssize_t n, retval = 0, count = 0; -+ -+ if (nbytes == 0) -+ return 0; -+ -+ while (nbytes > 0) { -+ n = nbytes; -+ if (n > SEC_XFER_SIZE) -+ n = SEC_XFER_SIZE; -+ -+ DEBUG_ENT("reading %d bits\n", n*8); -+ -+ n = extract_entropy_user(&blocking_pool, buf, n); -+ -+ DEBUG_ENT("read got %d bits (%d still needed)\n", -+ n*8, (nbytes-n)*8); -+ -+ if (n == 0) { -+ if (file->f_flags & O_NONBLOCK) { -+ retval = -EAGAIN; -+ break; -+ } -+ -+ DEBUG_ENT("sleeping?\n"); -+ -+ wait_event_interruptible(random_read_wait, -+ input_pool.entropy_count >= -+ random_read_wakeup_thresh); -+ -+ DEBUG_ENT("awake\n"); -+ -+ if (signal_pending(current)) { -+ retval = -ERESTARTSYS; -+ break; -+ } -+ -+ continue; -+ } -+ -+ if (n < 0) { -+ retval = n; -+ break; -+ } -+ count += n; -+ buf += n; -+ nbytes -= n; -+ break; /* This break makes the device work */ -+ /* like a named pipe */ -+ } -+ -+ return (count ? count : retval); -+} -+ -+static ssize_t -+urandom_read(struct file *file, char __user *buf, size_t nbytes, loff_t *ppos) -+{ -+ return extract_entropy_user(&nonblocking_pool, buf, nbytes); -+} -+ -+static unsigned int -+random_poll(struct file *file, poll_table * wait) -+{ -+ unsigned int mask; -+ -+ poll_wait(file, &random_read_wait, wait); -+ poll_wait(file, &random_write_wait, wait); -+ mask = 0; -+ if (input_pool.entropy_count >= random_read_wakeup_thresh) -+ mask |= POLLIN | POLLRDNORM; -+ if (input_pool.entropy_count < random_write_wakeup_thresh) -+ mask |= POLLOUT | POLLWRNORM; -+ return mask; -+} -+ -+static int -+write_pool(struct entropy_store *r, const char __user *buffer, size_t count) -+{ -+ size_t bytes; -+ __u32 buf[16]; -+ const char __user *p = buffer; -+ -+ while (count > 0) { -+ bytes = min(count, sizeof(buf)); -+ if (copy_from_user(&buf, p, bytes)) -+ return -EFAULT; -+ -+ count -= bytes; -+ p += bytes; -+ -+ mix_pool_bytes(r, buf, bytes); -+ cond_resched(); -+ } -+ -+ return 0; -+} -+ -+static ssize_t random_write(struct file *file, const char __user *buffer, -+ size_t count, loff_t *ppos) -+{ -+ size_t ret; -+ -+ ret = write_pool(&blocking_pool, buffer, count); -+ if (ret) -+ return ret; -+ ret = write_pool(&nonblocking_pool, buffer, count); -+ if (ret) -+ return ret; -+ -+ return (ssize_t)count; -+} -+ -+static long random_ioctl(struct file *f, unsigned int cmd, unsigned long arg) -+{ -+ int size, ent_count; -+ int __user *p = (int __user *)arg; -+ int retval; -+ -+ switch (cmd) { -+ case RNDGETENTCNT: -+ /* inherently racy, no point locking */ -+ if (put_user(input_pool.entropy_count, p)) -+ return -EFAULT; -+ return 0; -+ case RNDADDTOENTCNT: -+ if (!capable(CAP_SYS_ADMIN)) -+ return -EPERM; -+ if (get_user(ent_count, p)) -+ return -EFAULT; -+ credit_entropy_bits(&input_pool, ent_count); -+ return 0; -+ case RNDADDENTROPY: -+ if (!capable(CAP_SYS_ADMIN)) -+ return -EPERM; -+ if (get_user(ent_count, p++)) -+ return -EFAULT; -+ if (ent_count < 0) -+ return -EINVAL; -+ if (get_user(size, p++)) -+ return -EFAULT; -+ retval = write_pool(&input_pool, (const char __user *)p, -+ size); -+ if (retval < 0) -+ return retval; -+ credit_entropy_bits(&input_pool, ent_count); -+ return 0; -+ case RNDZAPENTCNT: -+ case RNDCLEARPOOL: -+ /* Clear the entropy pool counters. */ -+ if (!capable(CAP_SYS_ADMIN)) -+ return -EPERM; -+ rand_initialize(); -+ return 0; -+ default: -+ return -EINVAL; -+ } -+} -+ -+static int random_fasync(int fd, struct file *filp, int on) -+{ -+ return fasync_helper(fd, filp, on, &fasync); -+} -+ -+const struct file_operations random_fops = { -+ .read = random_read, -+ .write = random_write, -+ .poll = random_poll, -+ .unlocked_ioctl = random_ioctl, -+ .fasync = random_fasync, -+ .llseek = noop_llseek, -+}; -+ -+const struct file_operations urandom_fops = { -+ .read = urandom_read, -+ .write = random_write, -+ .unlocked_ioctl = random_ioctl, -+ .fasync = random_fasync, -+ .llseek = noop_llseek, -+}; -+ -+/*************************************************************** -+ * Random UUID interface -+ * -+ * Used here for a Boot ID, but can be useful for other kernel -+ * drivers. -+ ***************************************************************/ -+ -+/* -+ * Generate random UUID -+ */ -+void generate_random_uuid(unsigned char uuid_out[16]) -+{ -+ get_random_bytes(uuid_out, 16); -+ /* Set UUID version to 4 --- truly random generation */ -+ uuid_out[6] = (uuid_out[6] & 0x0F) | 0x40; -+ /* Set the UUID variant to DCE */ -+ uuid_out[8] = (uuid_out[8] & 0x3F) | 0x80; -+} -+EXPORT_SYMBOL(generate_random_uuid); -+ -+/******************************************************************** -+ * -+ * Sysctl interface -+ * -+ ********************************************************************/ -+ -+#ifdef CONFIG_SYSCTL -+ -+#include -+ -+static int min_read_thresh = 8, min_write_thresh; -+static int max_read_thresh = INPUT_POOL_WORDS * 32; -+static int max_write_thresh = INPUT_POOL_WORDS * 32; -+static char sysctl_bootid[16]; -+ -+/* -+ * These functions is used to return both the bootid UUID, and random -+ * UUID. The difference is in whether table->data is NULL; if it is, -+ * then a new UUID is generated and returned to the user. -+ * -+ * If the user accesses this via the proc interface, it will be returned -+ * as an ASCII string in the standard UUID format. If accesses via the -+ * sysctl system call, it is returned as 16 bytes of binary data. -+ */ -+static int proc_do_uuid(ctl_table *table, int write, -+ void __user *buffer, size_t *lenp, loff_t *ppos) -+{ -+ ctl_table fake_table; -+ unsigned char buf[64], tmp_uuid[16], *uuid; -+ -+ uuid = table->data; -+ if (!uuid) { -+ uuid = tmp_uuid; -+ uuid[8] = 0; -+ } -+ if (uuid[8] == 0) -+ generate_random_uuid(uuid); -+ -+ sprintf(buf, "%pU", uuid); -+ -+ fake_table.data = buf; -+ fake_table.maxlen = sizeof(buf); -+ -+ return proc_dostring(&fake_table, write, buffer, lenp, ppos); -+} -+ -+static int sysctl_poolsize = INPUT_POOL_WORDS * 32; -+ctl_table random_table[] = { -+ { -+ .procname = "poolsize", -+ .data = &sysctl_poolsize, -+ .maxlen = sizeof(int), -+ .mode = 0444, -+ .proc_handler = proc_dointvec, -+ }, -+ { -+ .procname = "entropy_avail", -+ .maxlen = sizeof(int), -+ .mode = 0444, -+ .proc_handler = proc_dointvec, -+ .data = &input_pool.entropy_count, -+ }, -+ { -+ .procname = "read_wakeup_threshold", -+ .data = &random_read_wakeup_thresh, -+ .maxlen = sizeof(int), -+ .mode = 0644, -+ .proc_handler = proc_dointvec_minmax, -+ .extra1 = &min_read_thresh, -+ .extra2 = &max_read_thresh, -+ }, -+ { -+ .procname = "write_wakeup_threshold", -+ .data = &random_write_wakeup_thresh, -+ .maxlen = sizeof(int), -+ .mode = 0644, -+ .proc_handler = proc_dointvec_minmax, -+ .extra1 = &min_write_thresh, -+ .extra2 = &max_write_thresh, -+ }, -+ { -+ .procname = "boot_id", -+ .data = &sysctl_bootid, -+ .maxlen = 16, -+ .mode = 0444, -+ .proc_handler = proc_do_uuid, -+ }, -+ { -+ .procname = "uuid", -+ .maxlen = 16, -+ .mode = 0444, -+ .proc_handler = proc_do_uuid, -+ }, -+ { } -+}; -+#endif /* CONFIG_SYSCTL */ -+ -+static u32 random_int_secret[MD5_MESSAGE_BYTES / 4] ____cacheline_aligned; -+ -+static int __init random_int_secret_init(void) -+{ -+ get_random_bytes(random_int_secret, sizeof(random_int_secret)); -+ return 0; -+} -+late_initcall(random_int_secret_init); -+ -+/* -+ * Get a random word for internal kernel use only. Similar to urandom but -+ * with the goal of minimal entropy pool depletion. As a result, the random -+ * value is not cryptographically secure but for several uses the cost of -+ * depleting entropy is too high -+ */ -+DEFINE_PER_CPU(__u32 [MD5_DIGEST_WORDS], get_random_int_hash); -+unsigned int get_random_int(void) -+{ -+ __u32 *hash = get_cpu_var(get_random_int_hash); -+ unsigned int ret; -+ -+ hash[0] += current->pid + jiffies + get_cycles(); -+ md5_transform(hash, random_int_secret); -+ ret = hash[0]; -+ put_cpu_var(get_random_int_hash); -+ -+ return ret; -+} -+ -+/* -+ * randomize_range() returns a start address such that -+ * -+ * [...... .....] -+ * start end -+ * -+ * a with size "len" starting at the return value is inside in the -+ * area defined by [start, end], but is otherwise randomized. -+ */ -+unsigned long -+randomize_range(unsigned long start, unsigned long end, unsigned long len) -+{ -+ unsigned long range = end - len - start; -+ -+ if (end <= start + len) -+ return 0; -+ return PAGE_ALIGN(get_random_int() % range + start); -+} -diff -Nur linux-3.0.4.orig/fs/fcntl.c linux-3.0.4/fs/fcntl.c ---- linux-3.0.4.orig/fs/fcntl.c 2011-08-29 22:56:30.000000000 +0200 -+++ linux-3.0.4/fs/fcntl.c 2011-10-17 04:36:27.356574299 +0200 -@@ -142,6 +142,7 @@ - } - return ret; - } -+EXPORT_SYMBOL(sys_dup); - - #define SETFL_MASK (O_APPEND | O_NONBLOCK | O_NDELAY | O_DIRECT | O_NOATIME) - -diff -Nur linux-3.0.4.orig/include/linux/miscdevice.h linux-3.0.4/include/linux/miscdevice.h ---- linux-3.0.4.orig/include/linux/miscdevice.h 2011-08-29 22:56:30.000000000 +0200 -+++ linux-3.0.4/include/linux/miscdevice.h 2011-10-17 04:36:27.356574299 +0200 -@@ -18,6 +18,7 @@ - #define APOLLO_MOUSE_MINOR 7 - #define PC110PAD_MINOR 9 - /*#define ADB_MOUSE_MINOR 10 FIXME OBSOLETE */ -+#define CRYPTODEV_MINOR 70 /* /dev/crypto */ - #define WATCHDOG_MINOR 130 /* Watchdog timer */ - #define TEMP_MINOR 131 /* Temperature Sensor */ - #define RTC_MINOR 135 -diff -Nur linux-3.0.4.orig/include/linux/random.h linux-3.0.4/include/linux/random.h ---- linux-3.0.4.orig/include/linux/random.h 2011-08-29 22:56:30.000000000 +0200 -+++ linux-3.0.4/include/linux/random.h 2011-10-17 04:36:27.356574299 +0200 -@@ -54,6 +54,10 @@ - unsigned int value); - extern void add_interrupt_randomness(int irq); - -+extern void random_input_words(__u32 *buf, size_t wordcount, int ent_count); -+extern int random_input_wait(void); -+#define HAS_RANDOM_INPUT_WAIT 1 -+ - extern void get_random_bytes(void *buf, int nbytes); - void generate_random_uuid(unsigned char uuid_out[16]); - -diff -Nur linux-3.0.4.orig/kernel/pid.c linux-3.0.4/kernel/pid.c ---- linux-3.0.4.orig/kernel/pid.c 2011-08-29 22:56:30.000000000 +0200 -+++ linux-3.0.4/kernel/pid.c 2011-10-17 04:36:27.356574299 +0200 -@@ -427,6 +427,7 @@ - { - return find_task_by_pid_ns(vnr, current->nsproxy->pid_ns); - } -+EXPORT_SYMBOL(find_task_by_vpid); - - struct pid *get_task_pid(struct task_struct *task, enum pid_type type) - { -diff -Nur linux-3.0.4.orig/kernel/pid.c.orig linux-3.0.4/kernel/pid.c.orig ---- linux-3.0.4.orig/kernel/pid.c.orig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.0.4/kernel/pid.c.orig 2011-08-29 22:56:30.000000000 +0200 -@@ -0,0 +1,570 @@ -+/* -+ * Generic pidhash and scalable, time-bounded PID allocator -+ * -+ * (C) 2002-2003 William Irwin, IBM -+ * (C) 2004 William Irwin, Oracle -+ * (C) 2002-2004 Ingo Molnar, Red Hat -+ * -+ * pid-structures are backing objects for tasks sharing a given ID to chain -+ * against. There is very little to them aside from hashing them and -+ * parking tasks using given ID's on a list. -+ * -+ * The hash is always changed with the tasklist_lock write-acquired, -+ * and the hash is only accessed with the tasklist_lock at least -+ * read-acquired, so there's no additional SMP locking needed here. -+ * -+ * We have a list of bitmap pages, which bitmaps represent the PID space. -+ * Allocating and freeing PIDs is completely lockless. The worst-case -+ * allocation scenario when all but one out of 1 million PIDs possible are -+ * allocated already: the scanning of 32 list entries and at most PAGE_SIZE -+ * bytes. The typical fastpath is a single successful setbit. Freeing is O(1). -+ * -+ * Pid namespaces: -+ * (C) 2007 Pavel Emelyanov , OpenVZ, SWsoft Inc. -+ * (C) 2007 Sukadev Bhattiprolu , IBM -+ * Many thanks to Oleg Nesterov for comments and help -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define pid_hashfn(nr, ns) \ -+ hash_long((unsigned long)nr + (unsigned long)ns, pidhash_shift) -+static struct hlist_head *pid_hash; -+static unsigned int pidhash_shift = 4; -+struct pid init_struct_pid = INIT_STRUCT_PID; -+ -+int pid_max = PID_MAX_DEFAULT; -+ -+#define RESERVED_PIDS 300 -+ -+int pid_max_min = RESERVED_PIDS + 1; -+int pid_max_max = PID_MAX_LIMIT; -+ -+#define BITS_PER_PAGE (PAGE_SIZE*8) -+#define BITS_PER_PAGE_MASK (BITS_PER_PAGE-1) -+ -+static inline int mk_pid(struct pid_namespace *pid_ns, -+ struct pidmap *map, int off) -+{ -+ return (map - pid_ns->pidmap)*BITS_PER_PAGE + off; -+} -+ -+#define find_next_offset(map, off) \ -+ find_next_zero_bit((map)->page, BITS_PER_PAGE, off) -+ -+/* -+ * PID-map pages start out as NULL, they get allocated upon -+ * first use and are never deallocated. This way a low pid_max -+ * value does not cause lots of bitmaps to be allocated, but -+ * the scheme scales to up to 4 million PIDs, runtime. -+ */ -+struct pid_namespace init_pid_ns = { -+ .kref = { -+ .refcount = ATOMIC_INIT(2), -+ }, -+ .pidmap = { -+ [ 0 ... PIDMAP_ENTRIES-1] = { ATOMIC_INIT(BITS_PER_PAGE), NULL } -+ }, -+ .last_pid = 0, -+ .level = 0, -+ .child_reaper = &init_task, -+}; -+EXPORT_SYMBOL_GPL(init_pid_ns); -+ -+int is_container_init(struct task_struct *tsk) -+{ -+ int ret = 0; -+ struct pid *pid; -+ -+ rcu_read_lock(); -+ pid = task_pid(tsk); -+ if (pid != NULL && pid->numbers[pid->level].nr == 1) -+ ret = 1; -+ rcu_read_unlock(); -+ -+ return ret; -+} -+EXPORT_SYMBOL(is_container_init); -+ -+/* -+ * Note: disable interrupts while the pidmap_lock is held as an -+ * interrupt might come in and do read_lock(&tasklist_lock). -+ * -+ * If we don't disable interrupts there is a nasty deadlock between -+ * detach_pid()->free_pid() and another cpu that does -+ * spin_lock(&pidmap_lock) followed by an interrupt routine that does -+ * read_lock(&tasklist_lock); -+ * -+ * After we clean up the tasklist_lock and know there are no -+ * irq handlers that take it we can leave the interrupts enabled. -+ * For now it is easier to be safe than to prove it can't happen. -+ */ -+ -+static __cacheline_aligned_in_smp DEFINE_SPINLOCK(pidmap_lock); -+ -+static void free_pidmap(struct upid *upid) -+{ -+ int nr = upid->nr; -+ struct pidmap *map = upid->ns->pidmap + nr / BITS_PER_PAGE; -+ int offset = nr & BITS_PER_PAGE_MASK; -+ -+ clear_bit(offset, map->page); -+ atomic_inc(&map->nr_free); -+} -+ -+/* -+ * If we started walking pids at 'base', is 'a' seen before 'b'? -+ */ -+static int pid_before(int base, int a, int b) -+{ -+ /* -+ * This is the same as saying -+ * -+ * (a - base + MAXUINT) % MAXUINT < (b - base + MAXUINT) % MAXUINT -+ * and that mapping orders 'a' and 'b' with respect to 'base'. -+ */ -+ return (unsigned)(a - base) < (unsigned)(b - base); -+} -+ -+/* -+ * We might be racing with someone else trying to set pid_ns->last_pid. -+ * We want the winner to have the "later" value, because if the -+ * "earlier" value prevails, then a pid may get reused immediately. -+ * -+ * Since pids rollover, it is not sufficient to just pick the bigger -+ * value. We have to consider where we started counting from. -+ * -+ * 'base' is the value of pid_ns->last_pid that we observed when -+ * we started looking for a pid. -+ * -+ * 'pid' is the pid that we eventually found. -+ */ -+static void set_last_pid(struct pid_namespace *pid_ns, int base, int pid) -+{ -+ int prev; -+ int last_write = base; -+ do { -+ prev = last_write; -+ last_write = cmpxchg(&pid_ns->last_pid, prev, pid); -+ } while ((prev != last_write) && (pid_before(base, last_write, pid))); -+} -+ -+static int alloc_pidmap(struct pid_namespace *pid_ns) -+{ -+ int i, offset, max_scan, pid, last = pid_ns->last_pid; -+ struct pidmap *map; -+ -+ pid = last + 1; -+ if (pid >= pid_max) -+ pid = RESERVED_PIDS; -+ offset = pid & BITS_PER_PAGE_MASK; -+ map = &pid_ns->pidmap[pid/BITS_PER_PAGE]; -+ /* -+ * If last_pid points into the middle of the map->page we -+ * want to scan this bitmap block twice, the second time -+ * we start with offset == 0 (or RESERVED_PIDS). -+ */ -+ max_scan = DIV_ROUND_UP(pid_max, BITS_PER_PAGE) - !offset; -+ for (i = 0; i <= max_scan; ++i) { -+ if (unlikely(!map->page)) { -+ void *page = kzalloc(PAGE_SIZE, GFP_KERNEL); -+ /* -+ * Free the page if someone raced with us -+ * installing it: -+ */ -+ spin_lock_irq(&pidmap_lock); -+ if (!map->page) { -+ map->page = page; -+ page = NULL; -+ } -+ spin_unlock_irq(&pidmap_lock); -+ kfree(page); -+ if (unlikely(!map->page)) -+ break; -+ } -+ if (likely(atomic_read(&map->nr_free))) { -+ do { -+ if (!test_and_set_bit(offset, map->page)) { -+ atomic_dec(&map->nr_free); -+ set_last_pid(pid_ns, last, pid); -+ return pid; -+ } -+ offset = find_next_offset(map, offset); -+ pid = mk_pid(pid_ns, map, offset); -+ } while (offset < BITS_PER_PAGE && pid < pid_max); -+ } -+ if (map < &pid_ns->pidmap[(pid_max-1)/BITS_PER_PAGE]) { -+ ++map; -+ offset = 0; -+ } else { -+ map = &pid_ns->pidmap[0]; -+ offset = RESERVED_PIDS; -+ if (unlikely(last == offset)) -+ break; -+ } -+ pid = mk_pid(pid_ns, map, offset); -+ } -+ return -1; -+} -+ -+int next_pidmap(struct pid_namespace *pid_ns, unsigned int last) -+{ -+ int offset; -+ struct pidmap *map, *end; -+ -+ if (last >= PID_MAX_LIMIT) -+ return -1; -+ -+ offset = (last + 1) & BITS_PER_PAGE_MASK; -+ map = &pid_ns->pidmap[(last + 1)/BITS_PER_PAGE]; -+ end = &pid_ns->pidmap[PIDMAP_ENTRIES]; -+ for (; map < end; map++, offset = 0) { -+ if (unlikely(!map->page)) -+ continue; -+ offset = find_next_bit((map)->page, BITS_PER_PAGE, offset); -+ if (offset < BITS_PER_PAGE) -+ return mk_pid(pid_ns, map, offset); -+ } -+ return -1; -+} -+ -+void put_pid(struct pid *pid) -+{ -+ struct pid_namespace *ns; -+ -+ if (!pid) -+ return; -+ -+ ns = pid->numbers[pid->level].ns; -+ if ((atomic_read(&pid->count) == 1) || -+ atomic_dec_and_test(&pid->count)) { -+ kmem_cache_free(ns->pid_cachep, pid); -+ put_pid_ns(ns); -+ } -+} -+EXPORT_SYMBOL_GPL(put_pid); -+ -+static void delayed_put_pid(struct rcu_head *rhp) -+{ -+ struct pid *pid = container_of(rhp, struct pid, rcu); -+ put_pid(pid); -+} -+ -+void free_pid(struct pid *pid) -+{ -+ /* We can be called with write_lock_irq(&tasklist_lock) held */ -+ int i; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&pidmap_lock, flags); -+ for (i = 0; i <= pid->level; i++) -+ hlist_del_rcu(&pid->numbers[i].pid_chain); -+ spin_unlock_irqrestore(&pidmap_lock, flags); -+ -+ for (i = 0; i <= pid->level; i++) -+ free_pidmap(pid->numbers + i); -+ -+ call_rcu(&pid->rcu, delayed_put_pid); -+} -+ -+struct pid *alloc_pid(struct pid_namespace *ns) -+{ -+ struct pid *pid; -+ enum pid_type type; -+ int i, nr; -+ struct pid_namespace *tmp; -+ struct upid *upid; -+ -+ pid = kmem_cache_alloc(ns->pid_cachep, GFP_KERNEL); -+ if (!pid) -+ goto out; -+ -+ tmp = ns; -+ for (i = ns->level; i >= 0; i--) { -+ nr = alloc_pidmap(tmp); -+ if (nr < 0) -+ goto out_free; -+ -+ pid->numbers[i].nr = nr; -+ pid->numbers[i].ns = tmp; -+ tmp = tmp->parent; -+ } -+ -+ get_pid_ns(ns); -+ pid->level = ns->level; -+ atomic_set(&pid->count, 1); -+ for (type = 0; type < PIDTYPE_MAX; ++type) -+ INIT_HLIST_HEAD(&pid->tasks[type]); -+ -+ upid = pid->numbers + ns->level; -+ spin_lock_irq(&pidmap_lock); -+ for ( ; upid >= pid->numbers; --upid) -+ hlist_add_head_rcu(&upid->pid_chain, -+ &pid_hash[pid_hashfn(upid->nr, upid->ns)]); -+ spin_unlock_irq(&pidmap_lock); -+ -+out: -+ return pid; -+ -+out_free: -+ while (++i <= ns->level) -+ free_pidmap(pid->numbers + i); -+ -+ kmem_cache_free(ns->pid_cachep, pid); -+ pid = NULL; -+ goto out; -+} -+ -+struct pid *find_pid_ns(int nr, struct pid_namespace *ns) -+{ -+ struct hlist_node *elem; -+ struct upid *pnr; -+ -+ hlist_for_each_entry_rcu(pnr, elem, -+ &pid_hash[pid_hashfn(nr, ns)], pid_chain) -+ if (pnr->nr == nr && pnr->ns == ns) -+ return container_of(pnr, struct pid, -+ numbers[ns->level]); -+ -+ return NULL; -+} -+EXPORT_SYMBOL_GPL(find_pid_ns); -+ -+struct pid *find_vpid(int nr) -+{ -+ return find_pid_ns(nr, current->nsproxy->pid_ns); -+} -+EXPORT_SYMBOL_GPL(find_vpid); -+ -+/* -+ * attach_pid() must be called with the tasklist_lock write-held. -+ */ -+void attach_pid(struct task_struct *task, enum pid_type type, -+ struct pid *pid) -+{ -+ struct pid_link *link; -+ -+ link = &task->pids[type]; -+ link->pid = pid; -+ hlist_add_head_rcu(&link->node, &pid->tasks[type]); -+} -+ -+static void __change_pid(struct task_struct *task, enum pid_type type, -+ struct pid *new) -+{ -+ struct pid_link *link; -+ struct pid *pid; -+ int tmp; -+ -+ link = &task->pids[type]; -+ pid = link->pid; -+ -+ hlist_del_rcu(&link->node); -+ link->pid = new; -+ -+ for (tmp = PIDTYPE_MAX; --tmp >= 0; ) -+ if (!hlist_empty(&pid->tasks[tmp])) -+ return; -+ -+ free_pid(pid); -+} -+ -+void detach_pid(struct task_struct *task, enum pid_type type) -+{ -+ __change_pid(task, type, NULL); -+} -+ -+void change_pid(struct task_struct *task, enum pid_type type, -+ struct pid *pid) -+{ -+ __change_pid(task, type, pid); -+ attach_pid(task, type, pid); -+} -+ -+/* transfer_pid is an optimization of attach_pid(new), detach_pid(old) */ -+void transfer_pid(struct task_struct *old, struct task_struct *new, -+ enum pid_type type) -+{ -+ new->pids[type].pid = old->pids[type].pid; -+ hlist_replace_rcu(&old->pids[type].node, &new->pids[type].node); -+} -+ -+struct task_struct *pid_task(struct pid *pid, enum pid_type type) -+{ -+ struct task_struct *result = NULL; -+ if (pid) { -+ struct hlist_node *first; -+ first = rcu_dereference_check(hlist_first_rcu(&pid->tasks[type]), -+ rcu_read_lock_held() || -+ lockdep_tasklist_lock_is_held()); -+ if (first) -+ result = hlist_entry(first, struct task_struct, pids[(type)].node); -+ } -+ return result; -+} -+EXPORT_SYMBOL(pid_task); -+ -+/* -+ * Must be called under rcu_read_lock(). -+ */ -+struct task_struct *find_task_by_pid_ns(pid_t nr, struct pid_namespace *ns) -+{ -+ rcu_lockdep_assert(rcu_read_lock_held()); -+ return pid_task(find_pid_ns(nr, ns), PIDTYPE_PID); -+} -+ -+struct task_struct *find_task_by_vpid(pid_t vnr) -+{ -+ return find_task_by_pid_ns(vnr, current->nsproxy->pid_ns); -+} -+ -+struct pid *get_task_pid(struct task_struct *task, enum pid_type type) -+{ -+ struct pid *pid; -+ rcu_read_lock(); -+ if (type != PIDTYPE_PID) -+ task = task->group_leader; -+ pid = get_pid(task->pids[type].pid); -+ rcu_read_unlock(); -+ return pid; -+} -+EXPORT_SYMBOL_GPL(get_task_pid); -+ -+struct task_struct *get_pid_task(struct pid *pid, enum pid_type type) -+{ -+ struct task_struct *result; -+ rcu_read_lock(); -+ result = pid_task(pid, type); -+ if (result) -+ get_task_struct(result); -+ rcu_read_unlock(); -+ return result; -+} -+EXPORT_SYMBOL_GPL(get_pid_task); -+ -+struct pid *find_get_pid(pid_t nr) -+{ -+ struct pid *pid; -+ -+ rcu_read_lock(); -+ pid = get_pid(find_vpid(nr)); -+ rcu_read_unlock(); -+ -+ return pid; -+} -+EXPORT_SYMBOL_GPL(find_get_pid); -+ -+pid_t pid_nr_ns(struct pid *pid, struct pid_namespace *ns) -+{ -+ struct upid *upid; -+ pid_t nr = 0; -+ -+ if (pid && ns->level <= pid->level) { -+ upid = &pid->numbers[ns->level]; -+ if (upid->ns == ns) -+ nr = upid->nr; -+ } -+ return nr; -+} -+ -+pid_t pid_vnr(struct pid *pid) -+{ -+ return pid_nr_ns(pid, current->nsproxy->pid_ns); -+} -+EXPORT_SYMBOL_GPL(pid_vnr); -+ -+pid_t __task_pid_nr_ns(struct task_struct *task, enum pid_type type, -+ struct pid_namespace *ns) -+{ -+ pid_t nr = 0; -+ -+ rcu_read_lock(); -+ if (!ns) -+ ns = current->nsproxy->pid_ns; -+ if (likely(pid_alive(task))) { -+ if (type != PIDTYPE_PID) -+ task = task->group_leader; -+ nr = pid_nr_ns(task->pids[type].pid, ns); -+ } -+ rcu_read_unlock(); -+ -+ return nr; -+} -+EXPORT_SYMBOL(__task_pid_nr_ns); -+ -+pid_t task_tgid_nr_ns(struct task_struct *tsk, struct pid_namespace *ns) -+{ -+ return pid_nr_ns(task_tgid(tsk), ns); -+} -+EXPORT_SYMBOL(task_tgid_nr_ns); -+ -+struct pid_namespace *task_active_pid_ns(struct task_struct *tsk) -+{ -+ return ns_of_pid(task_pid(tsk)); -+} -+EXPORT_SYMBOL_GPL(task_active_pid_ns); -+ -+/* -+ * Used by proc to find the first pid that is greater than or equal to nr. -+ * -+ * If there is a pid at nr this function is exactly the same as find_pid_ns. -+ */ -+struct pid *find_ge_pid(int nr, struct pid_namespace *ns) -+{ -+ struct pid *pid; -+ -+ do { -+ pid = find_pid_ns(nr, ns); -+ if (pid) -+ break; -+ nr = next_pidmap(ns, nr); -+ } while (nr > 0); -+ -+ return pid; -+} -+ -+/* -+ * The pid hash table is scaled according to the amount of memory in the -+ * machine. From a minimum of 16 slots up to 4096 slots at one gigabyte or -+ * more. -+ */ -+void __init pidhash_init(void) -+{ -+ int i, pidhash_size; -+ -+ pid_hash = alloc_large_system_hash("PID", sizeof(*pid_hash), 0, 18, -+ HASH_EARLY | HASH_SMALL, -+ &pidhash_shift, NULL, 4096); -+ pidhash_size = 1 << pidhash_shift; -+ -+ for (i = 0; i < pidhash_size; i++) -+ INIT_HLIST_HEAD(&pid_hash[i]); -+} -+ -+void __init pidmap_init(void) -+{ -+ /* bump default and minimum pid_max based on number of cpus */ -+ pid_max = min(pid_max_max, max_t(int, pid_max, -+ PIDS_PER_CPU_DEFAULT * num_possible_cpus())); -+ pid_max_min = max_t(int, pid_max_min, -+ PIDS_PER_CPU_MIN * num_possible_cpus()); -+ pr_info("pid_max: default: %u minimum: %u\n", pid_max, pid_max_min); -+ -+ init_pid_ns.pidmap[0].page = kzalloc(PAGE_SIZE, GFP_KERNEL); -+ /* Reserve PID 0. We never call free_pidmap(0) */ -+ set_bit(0, init_pid_ns.pidmap[0].page); -+ atomic_dec(&init_pid_ns.pidmap[0].nr_free); -+ -+ init_pid_ns.pid_cachep = KMEM_CACHE(pid, -+ SLAB_HWCACHE_ALIGN | SLAB_PANIC); -+} diff --git a/target/linux/patches/3.0.8/sparc-include.patch b/target/linux/patches/3.0.8/sparc-include.patch deleted file mode 100644 index 2f8ffd061..000000000 --- a/target/linux/patches/3.0.8/sparc-include.patch +++ /dev/null @@ -1,11 +0,0 @@ -diff -Nur linux-2.6.39-rc7.orig/arch/sparc/boot/btfixupprep.c linux-2.6.39-rc7/arch/sparc/boot/btfixupprep.c ---- linux-2.6.39-rc7.orig/arch/sparc/boot/btfixupprep.c 2011-05-10 04:33:54.000000000 +0200 -+++ linux-2.6.39-rc7/arch/sparc/boot/btfixupprep.c 2011-05-21 13:34:40.000000000 +0200 -@@ -25,7 +25,6 @@ - #include - #include - #include --#include - - #define MAXSYMS 1024 - diff --git a/target/linux/patches/3.0.8/startup.patch b/target/linux/patches/3.0.8/startup.patch deleted file mode 100644 index 68e8987b0..000000000 --- a/target/linux/patches/3.0.8/startup.patch +++ /dev/null @@ -1,20 +0,0 @@ -diff -Nur linux-2.6.34.orig/init/main.c linux-2.6.34/init/main.c ---- linux-2.6.34.orig/init/main.c 2010-05-16 23:17:36.000000000 +0200 -+++ linux-2.6.34/init/main.c 2010-05-20 20:13:26.321613615 +0200 -@@ -842,6 +842,7 @@ - printk(KERN_WARNING "Failed to execute %s. Attempting " - "defaults...\n", execute_command); - } -+ run_init_process("/init"); - run_init_process("/sbin/init"); - run_init_process("/etc/init"); - run_init_process("/bin/init"); -@@ -889,6 +890,8 @@ - if (sys_open((const char __user *) "/dev/console", O_RDWR, 0) < 0) - printk(KERN_WARNING "Warning: unable to open an initial console.\n"); - -+ printk(KERN_WARNING "Starting Linux (built with OpenADK).\n"); -+ - (void) sys_dup(0); - (void) sys_dup(0); - /* diff --git a/target/linux/patches/3.0.8/usb-defaults-off.patch b/target/linux/patches/3.0.8/usb-defaults-off.patch deleted file mode 100644 index 31367108a..000000000 --- a/target/linux/patches/3.0.8/usb-defaults-off.patch +++ /dev/null @@ -1,32 +0,0 @@ -diff -Nur linux-2.6.37.orig//drivers/usb/core/Kconfig linux-2.6.37/drivers/usb/core/Kconfig ---- linux-2.6.37.orig//drivers/usb/core/Kconfig 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/usb/core/Kconfig 2011-04-12 19:04:23.000000000 +0200 -@@ -59,7 +59,7 @@ - config USB_DEVICE_CLASS - bool "USB device class-devices (DEPRECATED)" - depends on USB -- default y -+ default n - ---help--- - Userspace access to USB devices is granted by device-nodes exported - directly from the usbdev in sysfs. Old versions of the driver -diff -Nur linux-2.6.37.orig//drivers/usb/host/Kconfig linux-2.6.37/drivers/usb/host/Kconfig ---- linux-2.6.37.orig//drivers/usb/host/Kconfig 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/usb/host/Kconfig 2011-04-12 19:04:48.000000000 +0200 -@@ -62,6 +62,7 @@ - config USB_EHCI_ROOT_HUB_TT - bool "Root Hub Transaction Translators" - depends on USB_EHCI_HCD -+ default n - ---help--- - Some EHCI chips have vendor-specific extensions to integrate - transaction translators, so that no OHCI or UHCI companion -@@ -74,7 +75,7 @@ - config USB_EHCI_TT_NEWSCHED - bool "Improved Transaction Translator scheduling" - depends on USB_EHCI_HCD -- default y -+ default n - ---help--- - This changes the periodic scheduling code to fill more of the low - and full speed bandwidth available from the Transaction Translator diff --git a/target/linux/patches/3.0.8/uuid.patch b/target/linux/patches/3.0.8/uuid.patch deleted file mode 100644 index 2529fdab5..000000000 --- a/target/linux/patches/3.0.8/uuid.patch +++ /dev/null @@ -1,255 +0,0 @@ -diff -Nur linux-2.6.38.4.orig/block/genhd.c linux-2.6.38.4/block/genhd.c ---- linux-2.6.38.4.orig/block/genhd.c 2011-04-21 23:34:46.000000000 +0200 -+++ linux-2.6.38.4/block/genhd.c 2011-04-27 19:21:18.668912036 +0200 -@@ -34,7 +34,7 @@ - static DEFINE_MUTEX(ext_devt_mutex); - static DEFINE_IDR(ext_devt_idr); - --static struct device_type disk_type; -+struct device_type disk_type; - - static void disk_add_events(struct gendisk *disk); - static void disk_del_events(struct gendisk *disk); -@@ -1118,7 +1118,7 @@ - return NULL; - } - --static struct device_type disk_type = { -+struct device_type disk_type = { - .name = "disk", - .groups = disk_attr_groups, - .release = disk_release, -diff -Nur linux-2.6.38.4.orig/init/do_mounts.c linux-2.6.38.4/init/do_mounts.c ---- linux-2.6.38.4.orig/init/do_mounts.c 2011-04-21 23:34:46.000000000 +0200 -+++ linux-2.6.38.4/init/do_mounts.c 2011-04-27 19:26:52.721413000 +0200 -@@ -32,6 +32,132 @@ - - dev_t ROOT_DEV; - -+#ifdef CONFIG_EXT2_FS -+/* support for root=UUID=ce40d6b2-18eb-4a75-aefe-7ddb0995ce63 bootargs */ -+ -+#include -+ -+__u8 root_dev_uuid[16]; -+int root_dev_type; /* 0 = normal (/dev/hda1, 0301); 1 = UUID; 3 = bad */ -+ -+/* imported from block/genhd.c after removing its static qualifier */ -+extern struct device_type disk_type; -+ -+/* helper function */ -+static __u8 __init fromhex(char c) -+{ -+ if (c >= '0' && c <= '9') -+ return (c - '0'); -+ c &= ~32; -+ if (c >= 'A' && c <= 'F') -+ return (c - 'A' + 10); -+ return (0xFF); -+} -+ -+static void __init parse_uuid(const char *s) -+{ -+ int i; -+ __u8 j, k; -+ -+ if (strlen(s) != 36 || s[8] != '-' || s[13] != '-' || -+ s[18] != '-' || s[23] != '-') -+ goto bad_uuid; -+ for (i = 0; i < 16; i++) { -+ if (*s == '-') -+ ++s; -+ j = fromhex(*s++); -+ k = fromhex(*s++); -+ if (j == 0xFF || k == 0xFF) -+ goto bad_uuid; -+ root_dev_uuid[i] = (j << 4) | k; -+ } -+ return; -+ bad_uuid: -+ /* we cannot panic here, defer */ -+ root_dev_type = 3; -+} -+ -+/* from drivers/md/md.c */ -+static void __init initcode_bi_complete(struct bio *bio, int error) -+{ -+ complete((struct completion*)bio->bi_private); -+} -+ -+static int __init initcode_sync_page_read(struct block_device *bdev, -+ sector_t sector, int size, struct page *page) -+{ -+ struct bio *bio = bio_alloc(GFP_NOIO, 1); -+ struct completion event; -+ int ret, rw = READ; -+ -+ rw |= REQ_SYNC; -+ -+ bio->bi_bdev = bdev; -+ bio->bi_sector = sector; -+ bio_add_page(bio, page, size, 0); -+ init_completion(&event); -+ bio->bi_private = &event; -+ bio->bi_end_io = initcode_bi_complete; -+ submit_bio(rw, bio); -+ wait_for_completion(&event); -+ -+ ret = test_bit(BIO_UPTODATE, &bio->bi_flags); -+ bio_put(bio); -+ /* 0 = failure */ -+ return ret; -+} -+ -+/* most of this taken from fs/ext2/super.c */ -+static int __init check_dev(struct gendisk *thedisk, dev_t devt, -+ int blocksize, struct page *page) -+{ -+ struct ext2_super_block * es; -+ struct block_device *bdev; -+ unsigned long sb_block = 1; -+ unsigned long logic_sb_block; -+ unsigned long offset = 0; -+ int rv = /* not found */ 0; -+ char bff[22]; -+ -+ bdev = bdget(devt); -+ if (blkdev_get(bdev, FMODE_READ, NULL)) { -+ printk(KERN_ERR "VFS: opening block device %s failed!\n", -+ format_dev_t(bff, devt)); -+ return (0); -+ } -+ -+ if (blocksize != BLOCK_SIZE) { -+ logic_sb_block = (sb_block*BLOCK_SIZE) / blocksize; -+ offset = (sb_block*BLOCK_SIZE) % blocksize; -+ } else { -+ logic_sb_block = sb_block; -+ } -+ -+// printk(KERN_ERR "D: attempting to read %d @%lu from " -+// "bdev %p devt %08X %s\n", blocksize, logic_sb_block, -+// bdev, devt, format_dev_t(bff, devt)); -+ if (!initcode_sync_page_read(bdev, logic_sb_block, blocksize, page)) { -+// printk(KERN_ERR "D: failed!\n"); -+ goto out; -+ } -+ es = (struct ext2_super_block *)(((char *)page_address(page)) + offset); -+ if (le16_to_cpu(es->s_magic) == EXT2_SUPER_MAGIC) { -+// printk(KERN_ERR "D: has uuid " -+// "%02X%02X%02X%02X-%02X%02X-%02X%02X-%02X%02X-%02X%02X%02X%02X%02X%02X\n", -+// es->s_uuid[0], es->s_uuid[1], es->s_uuid[2], es->s_uuid[3], -+// es->s_uuid[4], es->s_uuid[5], es->s_uuid[6], es->s_uuid[7], -+// es->s_uuid[8], es->s_uuid[9], es->s_uuid[10], es->s_uuid[11], -+// es->s_uuid[12], es->s_uuid[13], es->s_uuid[14], es->s_uuid[15]); -+ if (!memcmp(es->s_uuid, root_dev_uuid, 16)) -+ rv = /* found */ 1; -+ } -+// else printk(KERN_ERR "D: bad ext2fs magic\n"); -+ out: -+ blkdev_put(bdev, FMODE_READ); -+ return (rv); -+} -+#endif /* CONFIG_EXT2_FS for UUID support */ -+ - static int __init load_ramdisk(char *str) - { - rd_doload = simple_strtol(str,NULL,0) & 3; -@@ -218,6 +344,13 @@ - static int __init root_dev_setup(char *line) - { - strlcpy(saved_root_name, line, sizeof(saved_root_name)); -+#ifdef CONFIG_EXT2_FS -+ root_dev_type = 0; -+ if (!strncmp(line, "UUID=", 5)) { -+ root_dev_type = 1; -+ parse_uuid(line + 5); -+ } -+#endif /* CONFIG_EXT2_FS for UUID support */ - return 1; - } - -@@ -403,6 +536,83 @@ - - void __init mount_root(void) - { -+#ifdef CONFIG_EXT2_FS -+ /* UUID support */ -+// printk_all_partitions(); -+ if (root_dev_type == 1) { -+ int blocksize; -+ -+ /* from block/genhd.c printk_all_partitions */ -+ struct class_dev_iter iter; -+ struct device *dev; -+ -+ /* from drivers/md/md.c */ -+ struct page *sb_page; -+ -+ if (!(sb_page = alloc_page(GFP_KERNEL))) { -+ printk(KERN_ERR "VFS: no memory for bio page\n"); -+ goto nomemforbio; -+ } -+ -+// printk(KERN_ERR "D: root is: " -+// "%02X%02X%02X%02X-%02X%02X-%02X%02X-%02X%02X-%02X%02X%02X%02X%02X%02X\n", -+// root_dev_uuid[0], root_dev_uuid[1], root_dev_uuid[2], root_dev_uuid[3], -+// root_dev_uuid[4], root_dev_uuid[5], root_dev_uuid[6], root_dev_uuid[7], -+// root_dev_uuid[8], root_dev_uuid[9], root_dev_uuid[10], root_dev_uuid[11], -+// root_dev_uuid[12], root_dev_uuid[13], root_dev_uuid[14], root_dev_uuid[15]); -+ /* from block/genhd.c printk_all_partitions */ -+// printk(KERN_ERR "D: begin iter\n"); -+ class_dev_iter_init(&iter, &block_class, NULL, &disk_type); -+ while (root_dev_type && (dev = class_dev_iter_next(&iter))) { -+// char bff[22]; -+ struct gendisk *disk = dev_to_disk(dev); -+ struct disk_part_iter piter; -+ struct hd_struct *part; -+ if (get_capacity(disk) == 0 || -+ (disk->flags & GENHD_FL_SUPPRESS_PARTITION_INFO)) { -+// printk(KERN_ERR "D: ignoring\n"); -+ continue; -+ } -+ blocksize = queue_logical_block_size(disk->queue); -+// printk(KERN_ERR "D: gendisk, blocksize %d " -+// "name '%s' devt %08X %s #part %d\n", blocksize, -+// disk->disk_name, dev->devt, -+// format_dev_t(bff, dev->devt), -+// disk_max_parts(disk)); -+ disk_part_iter_init(&piter, disk, DISK_PITER_INCL_PART0); -+ while (root_dev_type && (part = disk_part_iter_next(&piter))) { -+ /* avoid empty or too small partitions */ -+// printk(KERN_ERR "D: part #%d start %llu " -+// "nr %llu\n", part->partno, -+// (__u64)part->start_sect, -+// (__u64)part->nr_sects); -+ if (part->nr_sects < 8) -+ continue; -+ if (check_dev(disk, MKDEV(MAJOR(dev->devt), -+ MINOR(dev->devt) + part->partno), -+ blocksize, sb_page)) { -+ ROOT_DEV = part_devt(part); -+// printk(KERN_ERR "D: got match!\n"); -+ // comment out below for debugging -+ root_dev_type = 0; -+ } -+ } -+ disk_part_iter_exit(&piter); -+ } -+// printk(KERN_ERR "D: end iter\n"); -+ class_dev_iter_exit(&iter); -+ put_page(sb_page); -+ } -+ nomemforbio: -+ if (root_dev_type == 1) -+ printk(KERN_ERR "VFS: Unable to find root by UUID %s.\n", -+ saved_root_name + 5); -+ else if (root_dev_type == 3) -+ /* execute deferred panic from parse_uuid */ -+ panic("Badly formatted UUID %s was supplied as kernel " -+ "parameter root", saved_root_name + 5); -+#endif /* CONFIG_EXT2_FS for UUID support */ -+ - #ifdef CONFIG_ROOT_NFS - if (MAJOR(ROOT_DEV) == UNNAMED_MAJOR) { - if (mount_nfs_root()) diff --git a/target/linux/patches/3.0.8/vga-cons-default-off.patch b/target/linux/patches/3.0.8/vga-cons-default-off.patch deleted file mode 100644 index 178aeeeb9..000000000 --- a/target/linux/patches/3.0.8/vga-cons-default-off.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff -Nur linux-2.6.37.orig//drivers/video/console/Kconfig linux-2.6.37/drivers/video/console/Kconfig ---- linux-2.6.37.orig//drivers/video/console/Kconfig 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/drivers/video/console/Kconfig 2011-04-12 16:29:34.000000000 +0200 -@@ -7,7 +7,7 @@ - config VGA_CONSOLE - bool "VGA text console" if EMBEDDED || !X86 - depends on !4xx && !8xx && !SPARC && !M68K && !PARISC && !FRV && !SUPERH && !BLACKFIN && !AVR32 && !MN10300 && (!ARM || ARCH_FOOTBRIDGE || ARCH_INTEGRATOR || ARCH_NETWINDER) -- default y -+ default n - help - Saying Y here will allow you to use Linux in text mode through a - display that complies with the generic VGA standard. Virtually diff --git a/target/linux/patches/3.0.8/wlan-cf.patch b/target/linux/patches/3.0.8/wlan-cf.patch deleted file mode 100644 index fc20759e2..000000000 --- a/target/linux/patches/3.0.8/wlan-cf.patch +++ /dev/null @@ -1,11 +0,0 @@ -diff -Nur linux-2.6.39.orig/drivers/net/wireless/hostap/hostap_cs.c linux-2.6.39/drivers/net/wireless/hostap/hostap_cs.c ---- linux-2.6.39.orig/drivers/net/wireless/hostap/hostap_cs.c 2011-05-19 06:06:34.000000000 +0200 -+++ linux-2.6.39/drivers/net/wireless/hostap/hostap_cs.c 2011-09-12 02:46:26.987984145 +0200 -@@ -623,6 +623,7 @@ - static struct pcmcia_device_id hostap_cs_ids[] = { - PCMCIA_DEVICE_MANF_CARD(0x000b, 0x7100), - PCMCIA_DEVICE_MANF_CARD(0x000b, 0x7300), -+ PCMCIA_DEVICE_MANF_CARD(0x0004, 0x2003), - PCMCIA_DEVICE_MANF_CARD(0x0101, 0x0777), - PCMCIA_DEVICE_MANF_CARD(0x0126, 0x8000), - PCMCIA_DEVICE_MANF_CARD(0x0138, 0x0002), diff --git a/target/linux/patches/3.0.8/x86-build.patch b/target/linux/patches/3.0.8/x86-build.patch deleted file mode 100644 index 339140f41..000000000 --- a/target/linux/patches/3.0.8/x86-build.patch +++ /dev/null @@ -1,11 +0,0 @@ -diff -Nur linux-2.6.39-rc6.orig/arch/x86/boot/tools/build.c linux-2.6.39-rc6/arch/x86/boot/tools/build.c ---- linux-2.6.39-rc6.orig/arch/x86/boot/tools/build.c 2011-05-04 04:59:13.000000000 +0200 -+++ linux-2.6.39-rc6/arch/x86/boot/tools/build.c 2011-05-05 20:10:07.000000000 +0200 -@@ -29,7 +29,6 @@ - #include - #include - #include --#include - #include - #include - #include diff --git a/target/linux/patches/3.0.8/zlib-inflate.patch b/target/linux/patches/3.0.8/zlib-inflate.patch deleted file mode 100644 index 58e1f6d21..000000000 --- a/target/linux/patches/3.0.8/zlib-inflate.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff -Nur linux-2.6.37.orig/lib/Kconfig linux-2.6.37/lib/Kconfig ---- linux-2.6.37.orig/lib/Kconfig 2011-01-05 01:50:19.000000000 +0100 -+++ linux-2.6.37/lib/Kconfig 2011-03-01 20:10:29.833370667 +0100 -@@ -95,7 +95,7 @@ - # compression support is select'ed if needed - # - config ZLIB_INFLATE -- tristate -+ boolean - - config ZLIB_DEFLATE - tristate diff --git a/target/linux/patches/3.0.9/bsd-compatibility.patch b/target/linux/patches/3.0.9/bsd-compatibility.patch new file mode 100644 index 000000000..9e91a62de --- /dev/null +++ b/target/linux/patches/3.0.9/bsd-compatibility.patch @@ -0,0 +1,2512 @@ +diff -Nur linux-2.6.36.orig/scripts/Makefile.lib linux-2.6.36/scripts/Makefile.lib +--- linux-2.6.36.orig/scripts/Makefile.lib 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/scripts/Makefile.lib 2010-11-28 18:34:22.000000000 +0100 +@@ -216,7 +216,12 @@ + size_append = printf $(shell \ + dec_size=0; \ + for F in $1; do \ +- fsize=$$(stat -c "%s" $$F); \ ++ if stat -qs .>/dev/null 2>&1; then \ ++ statcmd='stat -f %z'; \ ++ else \ ++ statcmd='stat -c %s'; \ ++ fi; \ ++ fsize=$$($$statcmd $$F); \ + dec_size=$$(expr $$dec_size + $$fsize); \ + done; \ + printf "%08x\n" $$dec_size | \ +diff -Nur linux-2.6.36.orig/scripts/mod/mk_elfconfig.c linux-2.6.36/scripts/mod/mk_elfconfig.c +--- linux-2.6.36.orig/scripts/mod/mk_elfconfig.c 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/scripts/mod/mk_elfconfig.c 2010-11-28 18:33:24.000000000 +0100 +@@ -1,7 +1,18 @@ + #include + #include + #include +-#include ++ ++#define EI_NIDENT (16) ++#define ELFMAG "\177ELF" ++ ++#define SELFMAG 4 ++#define EI_CLASS 4 ++#define ELFCLASS32 1 /* 32-bit objects */ ++#define ELFCLASS64 2 /* 64-bit objects */ ++ ++#define EI_DATA 5 /* Data encoding byte index */ ++#define ELFDATA2LSB 1 /* 2's complement, little endian */ ++#define ELFDATA2MSB 2 /* 2's complement, big endian */ + + int + main(int argc, char **argv) +diff -Nur linux-2.6.36.orig/scripts/mod/modpost.h linux-2.6.36/scripts/mod/modpost.h +--- linux-2.6.36.orig/scripts/mod/modpost.h 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/scripts/mod/modpost.h 2010-11-28 18:33:24.000000000 +0100 +@@ -7,7 +7,2453 @@ + #include + #include + #include +-#include ++ ++ ++/* This file defines standard ELF types, structures, and macros. ++ Copyright (C) 1995-1999,2000,2001,2002,2003 Free Software Foundation, Inc. ++ This file is part of the GNU C Library. ++ ++ The GNU C Library is free software; you can redistribute it and/or ++ modify it under the terms of the GNU Lesser General Public ++ License as published by the Free Software Foundation; either ++ version 2.1 of the License, or (at your option) any later version. ++ ++ The GNU C Library is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ Lesser General Public License for more details. ++ ++ You should have received a copy of the GNU Lesser General Public ++ License along with the GNU C Library; if not, write to the Free ++ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA ++ 02111-1307 USA. */ ++ ++#ifndef _ELF_H ++#define _ELF_H 1 ++ ++__BEGIN_DECLS ++ ++/* Standard ELF types. */ ++ ++#include ++ ++/* Type for a 16-bit quantity. */ ++typedef uint16_t Elf32_Half; ++typedef uint16_t Elf64_Half; ++ ++/* Types for signed and unsigned 32-bit quantities. */ ++typedef uint32_t Elf32_Word; ++typedef int32_t Elf32_Sword; ++typedef uint32_t Elf64_Word; ++typedef int32_t Elf64_Sword; ++ ++/* Types for signed and unsigned 64-bit quantities. */ ++typedef uint64_t Elf32_Xword; ++typedef int64_t Elf32_Sxword; ++typedef uint64_t Elf64_Xword; ++typedef int64_t Elf64_Sxword; ++ ++/* Type of addresses. */ ++typedef uint32_t Elf32_Addr; ++typedef uint64_t Elf64_Addr; ++ ++/* Type of file offsets. */ ++typedef uint32_t Elf32_Off; ++typedef uint64_t Elf64_Off; ++ ++/* Type for section indices, which are 16-bit quantities. */ ++typedef uint16_t Elf32_Section; ++typedef uint16_t Elf64_Section; ++ ++/* Type for version symbol information. */ ++typedef Elf32_Half Elf32_Versym; ++typedef Elf64_Half Elf64_Versym; ++ ++ ++/* The ELF file header. This appears at the start of every ELF file. */ ++ ++#define EI_NIDENT (16) ++ ++typedef struct ++{ ++ unsigned char e_ident[EI_NIDENT]; /* Magic number and other info */ ++ Elf32_Half e_type; /* Object file type */ ++ Elf32_Half e_machine; /* Architecture */ ++ Elf32_Word e_version; /* Object file version */ ++ Elf32_Addr e_entry; /* Entry point virtual address */ ++ Elf32_Off e_phoff; /* Program header table file offset */ ++ Elf32_Off e_shoff; /* Section header table file offset */ ++ Elf32_Word e_flags; /* Processor-specific flags */ ++ Elf32_Half e_ehsize; /* ELF header size in bytes */ ++ Elf32_Half e_phentsize; /* Program header table entry size */ ++ Elf32_Half e_phnum; /* Program header table entry count */ ++ Elf32_Half e_shentsize; /* Section header table entry size */ ++ Elf32_Half e_shnum; /* Section header table entry count */ ++ Elf32_Half e_shstrndx; /* Section header string table index */ ++} Elf32_Ehdr; ++ ++typedef struct ++{ ++ unsigned char e_ident[EI_NIDENT]; /* Magic number and other info */ ++ Elf64_Half e_type; /* Object file type */ ++ Elf64_Half e_machine; /* Architecture */ ++ Elf64_Word e_version; /* Object file version */ ++ Elf64_Addr e_entry; /* Entry point virtual address */ ++ Elf64_Off e_phoff; /* Program header table file offset */ ++ Elf64_Off e_shoff; /* Section header table file offset */ ++ Elf64_Word e_flags; /* Processor-specific flags */ ++ Elf64_Half e_ehsize; /* ELF header size in bytes */ ++ Elf64_Half e_phentsize; /* Program header table entry size */ ++ Elf64_Half e_phnum; /* Program header table entry count */ ++ Elf64_Half e_shentsize; /* Section header table entry size */ ++ Elf64_Half e_shnum; /* Section header table entry count */ ++ Elf64_Half e_shstrndx; /* Section header string table index */ ++} Elf64_Ehdr; ++ ++/* Fields in the e_ident array. The EI_* macros are indices into the ++ array. The macros under each EI_* macro are the values the byte ++ may have. */ ++ ++#define EI_MAG0 0 /* File identification byte 0 index */ ++#define ELFMAG0 0x7f /* Magic number byte 0 */ ++ ++#define EI_MAG1 1 /* File identification byte 1 index */ ++#define ELFMAG1 'E' /* Magic number byte 1 */ ++ ++#define EI_MAG2 2 /* File identification byte 2 index */ ++#define ELFMAG2 'L' /* Magic number byte 2 */ ++ ++#define EI_MAG3 3 /* File identification byte 3 index */ ++#define ELFMAG3 'F' /* Magic number byte 3 */ ++ ++/* Conglomeration of the identification bytes, for easy testing as a word. */ ++#define ELFMAG "\177ELF" ++#define SELFMAG 4 ++ ++#define EI_CLASS 4 /* File class byte index */ ++#define ELFCLASSNONE 0 /* Invalid class */ ++#define ELFCLASS32 1 /* 32-bit objects */ ++#define ELFCLASS64 2 /* 64-bit objects */ ++#define ELFCLASSNUM 3 ++ ++#define EI_DATA 5 /* Data encoding byte index */ ++#define ELFDATANONE 0 /* Invalid data encoding */ ++#define ELFDATA2LSB 1 /* 2's complement, little endian */ ++#define ELFDATA2MSB 2 /* 2's complement, big endian */ ++#define ELFDATANUM 3 ++ ++#define EI_VERSION 6 /* File version byte index */ ++ /* Value must be EV_CURRENT */ ++ ++#define EI_OSABI 7 /* OS ABI identification */ ++#define ELFOSABI_NONE 0 /* UNIX System V ABI */ ++#define ELFOSABI_SYSV 0 /* Alias. */ ++#define ELFOSABI_HPUX 1 /* HP-UX */ ++#define ELFOSABI_NETBSD 2 /* NetBSD. */ ++#define ELFOSABI_LINUX 3 /* Linux. */ ++#define ELFOSABI_SOLARIS 6 /* Sun Solaris. */ ++#define ELFOSABI_AIX 7 /* IBM AIX. */ ++#define ELFOSABI_IRIX 8 /* SGI Irix. */ ++#define ELFOSABI_FREEBSD 9 /* FreeBSD. */ ++#define ELFOSABI_TRU64 10 /* Compaq TRU64 UNIX. */ ++#define ELFOSABI_MODESTO 11 /* Novell Modesto. */ ++#define ELFOSABI_OPENBSD 12 /* OpenBSD. */ ++#define ELFOSABI_ARM 97 /* ARM */ ++#define ELFOSABI_STANDALONE 255 /* Standalone (embedded) application */ ++ ++#define EI_ABIVERSION 8 /* ABI version */ ++ ++#define EI_PAD 9 /* Byte index of padding bytes */ ++ ++/* Legal values for e_type (object file type). */ ++ ++#define ET_NONE 0 /* No file type */ ++#define ET_REL 1 /* Relocatable file */ ++#define ET_EXEC 2 /* Executable file */ ++#define ET_DYN 3 /* Shared object file */ ++#define ET_CORE 4 /* Core file */ ++#define ET_NUM 5 /* Number of defined types */ ++#define ET_LOOS 0xfe00 /* OS-specific range start */ ++#define ET_HIOS 0xfeff /* OS-specific range end */ ++#define ET_LOPROC 0xff00 /* Processor-specific range start */ ++#define ET_HIPROC 0xffff /* Processor-specific range end */ ++ ++/* Legal values for e_machine (architecture). */ ++ ++#define EM_NONE 0 /* No machine */ ++#define EM_M32 1 /* AT&T WE 32100 */ ++#define EM_SPARC 2 /* SUN SPARC */ ++#define EM_386 3 /* Intel 80386 */ ++#define EM_68K 4 /* Motorola m68k family */ ++#define EM_88K 5 /* Motorola m88k family */ ++#define EM_860 7 /* Intel 80860 */ ++#define EM_MIPS 8 /* MIPS R3000 big-endian */ ++#define EM_S370 9 /* IBM System/370 */ ++#define EM_MIPS_RS3_LE 10 /* MIPS R3000 little-endian */ ++ ++#define EM_PARISC 15 /* HPPA */ ++#define EM_VPP500 17 /* Fujitsu VPP500 */ ++#define EM_SPARC32PLUS 18 /* Sun's "v8plus" */ ++#define EM_960 19 /* Intel 80960 */ ++#define EM_PPC 20 /* PowerPC */ ++#define EM_PPC64 21 /* PowerPC 64-bit */ ++#define EM_S390 22 /* IBM S390 */ ++ ++#define EM_V800 36 /* NEC V800 series */ ++#define EM_FR20 37 /* Fujitsu FR20 */ ++#define EM_RH32 38 /* TRW RH-32 */ ++#define EM_RCE 39 /* Motorola RCE */ ++#define EM_ARM 40 /* ARM */ ++#define EM_FAKE_ALPHA 41 /* Digital Alpha */ ++#define EM_SH 42 /* Hitachi SH */ ++#define EM_SPARCV9 43 /* SPARC v9 64-bit */ ++#define EM_TRICORE 44 /* Siemens Tricore */ ++#define EM_ARC 45 /* Argonaut RISC Core */ ++#define EM_H8_300 46 /* Hitachi H8/300 */ ++#define EM_H8_300H 47 /* Hitachi H8/300H */ ++#define EM_H8S 48 /* Hitachi H8S */ ++#define EM_H8_500 49 /* Hitachi H8/500 */ ++#define EM_IA_64 50 /* Intel Merced */ ++#define EM_MIPS_X 51 /* Stanford MIPS-X */ ++#define EM_COLDFIRE 52 /* Motorola Coldfire */ ++#define EM_68HC12 53 /* Motorola M68HC12 */ ++#define EM_MMA 54 /* Fujitsu MMA Multimedia Accelerator*/ ++#define EM_PCP 55 /* Siemens PCP */ ++#define EM_NCPU 56 /* Sony nCPU embeeded RISC */ ++#define EM_NDR1 57 /* Denso NDR1 microprocessor */ ++#define EM_STARCORE 58 /* Motorola Start*Core processor */ ++#define EM_ME16 59 /* Toyota ME16 processor */ ++#define EM_ST100 60 /* STMicroelectronic ST100 processor */ ++#define EM_TINYJ 61 /* Advanced Logic Corp. Tinyj emb.fam*/ ++#define EM_X86_64 62 /* AMD x86-64 architecture */ ++#define EM_PDSP 63 /* Sony DSP Processor */ ++ ++#define EM_FX66 66 /* Siemens FX66 microcontroller */ ++#define EM_ST9PLUS 67 /* STMicroelectronics ST9+ 8/16 mc */ ++#define EM_ST7 68 /* STmicroelectronics ST7 8 bit mc */ ++#define EM_68HC16 69 /* Motorola MC68HC16 microcontroller */ ++#define EM_68HC11 70 /* Motorola MC68HC11 microcontroller */ ++#define EM_68HC08 71 /* Motorola MC68HC08 microcontroller */ ++#define EM_68HC05 72 /* Motorola MC68HC05 microcontroller */ ++#define EM_SVX 73 /* Silicon Graphics SVx */ ++#define EM_ST19 74 /* STMicroelectronics ST19 8 bit mc */ ++#define EM_VAX 75 /* Digital VAX */ ++#define EM_CRIS 76 /* Axis Communications 32-bit embedded processor */ ++#define EM_JAVELIN 77 /* Infineon Technologies 32-bit embedded processor */ ++#define EM_FIREPATH 78 /* Element 14 64-bit DSP Processor */ ++#define EM_ZSP 79 /* LSI Logic 16-bit DSP Processor */ ++#define EM_MMIX 80 /* Donald Knuth's educational 64-bit processor */ ++#define EM_HUANY 81 /* Harvard University machine-independent object files */ ++#define EM_PRISM 82 /* SiTera Prism */ ++#define EM_AVR 83 /* Atmel AVR 8-bit microcontroller */ ++#define EM_FR30 84 /* Fujitsu FR30 */ ++#define EM_D10V 85 /* Mitsubishi D10V */ ++#define EM_D30V 86 /* Mitsubishi D30V */ ++#define EM_V850 87 /* NEC v850 */ ++#define EM_M32R 88 /* Mitsubishi M32R */ ++#define EM_MN10300 89 /* Matsushita MN10300 */ ++#define EM_MN10200 90 /* Matsushita MN10200 */ ++#define EM_PJ 91 /* picoJava */ ++#define EM_OPENRISC 92 /* OpenRISC 32-bit embedded processor */ ++#define EM_ARC_A5 93 /* ARC Cores Tangent-A5 */ ++#define EM_XTENSA 94 /* Tensilica Xtensa Architecture */ ++#define EM_NUM 95 ++ ++/* If it is necessary to assign new unofficial EM_* values, please ++ pick large random numbers (0x8523, 0xa7f2, etc.) to minimize the ++ chances of collision with official or non-GNU unofficial values. */ ++ ++#define EM_ALPHA 0x9026 ++ ++/* Legal values for e_version (version). */ ++ ++#define EV_NONE 0 /* Invalid ELF version */ ++#define EV_CURRENT 1 /* Current version */ ++#define EV_NUM 2 ++ ++/* Section header. */ ++ ++typedef struct ++{ ++ Elf32_Word sh_name; /* Section name (string tbl index) */ ++ Elf32_Word sh_type; /* Section type */ ++ Elf32_Word sh_flags; /* Section flags */ ++ Elf32_Addr sh_addr; /* Section virtual addr at execution */ ++ Elf32_Off sh_offset; /* Section file offset */ ++ Elf32_Word sh_size; /* Section size in bytes */ ++ Elf32_Word sh_link; /* Link to another section */ ++ Elf32_Word sh_info; /* Additional section information */ ++ Elf32_Word sh_addralign; /* Section alignment */ ++ Elf32_Word sh_entsize; /* Entry size if section holds table */ ++} Elf32_Shdr; ++ ++typedef struct ++{ ++ Elf64_Word sh_name; /* Section name (string tbl index) */ ++ Elf64_Word sh_type; /* Section type */ ++ Elf64_Xword sh_flags; /* Section flags */ ++ Elf64_Addr sh_addr; /* Section virtual addr at execution */ ++ Elf64_Off sh_offset; /* Section file offset */ ++ Elf64_Xword sh_size; /* Section size in bytes */ ++ Elf64_Word sh_link; /* Link to another section */ ++ Elf64_Word sh_info; /* Additional section information */ ++ Elf64_Xword sh_addralign; /* Section alignment */ ++ Elf64_Xword sh_entsize; /* Entry size if section holds table */ ++} Elf64_Shdr; ++ ++/* Special section indices. */ ++ ++#define SHN_UNDEF 0 /* Undefined section */ ++#define SHN_LORESERVE 0xff00 /* Start of reserved indices */ ++#define SHN_LOPROC 0xff00 /* Start of processor-specific */ ++#define SHN_HIPROC 0xff1f /* End of processor-specific */ ++#define SHN_LOOS 0xff20 /* Start of OS-specific */ ++#define SHN_HIOS 0xff3f /* End of OS-specific */ ++#define SHN_ABS 0xfff1 /* Associated symbol is absolute */ ++#define SHN_COMMON 0xfff2 /* Associated symbol is common */ ++#define SHN_XINDEX 0xffff /* Index is in extra table. */ ++#define SHN_HIRESERVE 0xffff /* End of reserved indices */ ++ ++/* Legal values for sh_type (section type). */ ++ ++#define SHT_NULL 0 /* Section header table entry unused */ ++#define SHT_PROGBITS 1 /* Program data */ ++#define SHT_SYMTAB 2 /* Symbol table */ ++#define SHT_STRTAB 3 /* String table */ ++#define SHT_RELA 4 /* Relocation entries with addends */ ++#define SHT_HASH 5 /* Symbol hash table */ ++#define SHT_DYNAMIC 6 /* Dynamic linking information */ ++#define SHT_NOTE 7 /* Notes */ ++#define SHT_NOBITS 8 /* Program space with no data (bss) */ ++#define SHT_REL 9 /* Relocation entries, no addends */ ++#define SHT_SHLIB 10 /* Reserved */ ++#define SHT_DYNSYM 11 /* Dynamic linker symbol table */ ++#define SHT_INIT_ARRAY 14 /* Array of constructors */ ++#define SHT_FINI_ARRAY 15 /* Array of destructors */ ++#define SHT_PREINIT_ARRAY 16 /* Array of pre-constructors */ ++#define SHT_GROUP 17 /* Section group */ ++#define SHT_SYMTAB_SHNDX 18 /* Extended section indeces */ ++#define SHT_NUM 19 /* Number of defined types. */ ++#define SHT_LOOS 0x60000000 /* Start OS-specific */ ++#define SHT_GNU_LIBLIST 0x6ffffff7 /* Prelink library list */ ++#define SHT_CHECKSUM 0x6ffffff8 /* Checksum for DSO content. */ ++#define SHT_LOSUNW 0x6ffffffa /* Sun-specific low bound. */ ++#define SHT_SUNW_move 0x6ffffffa ++#define SHT_SUNW_COMDAT 0x6ffffffb ++#define SHT_SUNW_syminfo 0x6ffffffc ++#define SHT_GNU_verdef 0x6ffffffd /* Version definition section. */ ++#define SHT_GNU_verneed 0x6ffffffe /* Version needs section. */ ++#define SHT_GNU_versym 0x6fffffff /* Version symbol table. */ ++#define SHT_HISUNW 0x6fffffff /* Sun-specific high bound. */ ++#define SHT_HIOS 0x6fffffff /* End OS-specific type */ ++#define SHT_LOPROC 0x70000000 /* Start of processor-specific */ ++#define SHT_HIPROC 0x7fffffff /* End of processor-specific */ ++#define SHT_LOUSER 0x80000000 /* Start of application-specific */ ++#define SHT_HIUSER 0x8fffffff /* End of application-specific */ ++ ++/* Legal values for sh_flags (section flags). */ ++ ++#define SHF_WRITE (1 << 0) /* Writable */ ++#define SHF_ALLOC (1 << 1) /* Occupies memory during execution */ ++#define SHF_EXECINSTR (1 << 2) /* Executable */ ++#define SHF_MERGE (1 << 4) /* Might be merged */ ++#define SHF_STRINGS (1 << 5) /* Contains nul-terminated strings */ ++#define SHF_INFO_LINK (1 << 6) /* `sh_info' contains SHT index */ ++#define SHF_LINK_ORDER (1 << 7) /* Preserve order after combining */ ++#define SHF_OS_NONCONFORMING (1 << 8) /* Non-standard OS specific handling ++ required */ ++#define SHF_GROUP (1 << 9) /* Section is member of a group. */ ++#define SHF_TLS (1 << 10) /* Section hold thread-local data. */ ++#define SHF_MASKOS 0x0ff00000 /* OS-specific. */ ++#define SHF_MASKPROC 0xf0000000 /* Processor-specific */ ++ ++/* Section group handling. */ ++#define GRP_COMDAT 0x1 /* Mark group as COMDAT. */ ++ ++/* Symbol table entry. */ ++ ++typedef struct ++{ ++ Elf32_Word st_name; /* Symbol name (string tbl index) */ ++ Elf32_Addr st_value; /* Symbol value */ ++ Elf32_Word st_size; /* Symbol size */ ++ unsigned char st_info; /* Symbol type and binding */ ++ unsigned char st_other; /* Symbol visibility */ ++ Elf32_Section st_shndx; /* Section index */ ++} Elf32_Sym; ++ ++typedef struct ++{ ++ Elf64_Word st_name; /* Symbol name (string tbl index) */ ++ unsigned char st_info; /* Symbol type and binding */ ++ unsigned char st_other; /* Symbol visibility */ ++ Elf64_Section st_shndx; /* Section index */ ++ Elf64_Addr st_value; /* Symbol value */ ++ Elf64_Xword st_size; /* Symbol size */ ++} Elf64_Sym; ++ ++/* The syminfo section if available contains additional information about ++ every dynamic symbol. */ ++ ++typedef struct ++{ ++ Elf32_Half si_boundto; /* Direct bindings, symbol bound to */ ++ Elf32_Half si_flags; /* Per symbol flags */ ++} Elf32_Syminfo; ++ ++typedef struct ++{ ++ Elf64_Half si_boundto; /* Direct bindings, symbol bound to */ ++ Elf64_Half si_flags; /* Per symbol flags */ ++} Elf64_Syminfo; ++ ++/* Possible values for si_boundto. */ ++#define SYMINFO_BT_SELF 0xffff /* Symbol bound to self */ ++#define SYMINFO_BT_PARENT 0xfffe /* Symbol bound to parent */ ++#define SYMINFO_BT_LOWRESERVE 0xff00 /* Beginning of reserved entries */ ++ ++/* Possible bitmasks for si_flags. */ ++#define SYMINFO_FLG_DIRECT 0x0001 /* Direct bound symbol */ ++#define SYMINFO_FLG_PASSTHRU 0x0002 /* Pass-thru symbol for translator */ ++#define SYMINFO_FLG_COPY 0x0004 /* Symbol is a copy-reloc */ ++#define SYMINFO_FLG_LAZYLOAD 0x0008 /* Symbol bound to object to be lazy ++ loaded */ ++/* Syminfo version values. */ ++#define SYMINFO_NONE 0 ++#define SYMINFO_CURRENT 1 ++#define SYMINFO_NUM 2 ++ ++ ++/* How to extract and insert information held in the st_info field. */ ++ ++#define ELF32_ST_BIND(val) (((unsigned char) (val)) >> 4) ++#define ELF32_ST_TYPE(val) ((val) & 0xf) ++#define ELF32_ST_INFO(bind, type) (((bind) << 4) + ((type) & 0xf)) ++ ++/* Both Elf32_Sym and Elf64_Sym use the same one-byte st_info field. */ ++#define ELF64_ST_BIND(val) ELF32_ST_BIND (val) ++#define ELF64_ST_TYPE(val) ELF32_ST_TYPE (val) ++#define ELF64_ST_INFO(bind, type) ELF32_ST_INFO ((bind), (type)) ++ ++/* Legal values for ST_BIND subfield of st_info (symbol binding). */ ++ ++#define STB_LOCAL 0 /* Local symbol */ ++#define STB_GLOBAL 1 /* Global symbol */ ++#define STB_WEAK 2 /* Weak symbol */ ++#define STB_NUM 3 /* Number of defined types. */ ++#define STB_LOOS 10 /* Start of OS-specific */ ++#define STB_HIOS 12 /* End of OS-specific */ ++#define STB_LOPROC 13 /* Start of processor-specific */ ++#define STB_HIPROC 15 /* End of processor-specific */ ++ ++/* Legal values for ST_TYPE subfield of st_info (symbol type). */ ++ ++#define STT_NOTYPE 0 /* Symbol type is unspecified */ ++#define STT_OBJECT 1 /* Symbol is a data object */ ++#define STT_FUNC 2 /* Symbol is a code object */ ++#define STT_SECTION 3 /* Symbol associated with a section */ ++#define STT_FILE 4 /* Symbol's name is file name */ ++#define STT_COMMON 5 /* Symbol is a common data object */ ++#define STT_TLS 6 /* Symbol is thread-local data object*/ ++#define STT_NUM 7 /* Number of defined types. */ ++#define STT_LOOS 10 /* Start of OS-specific */ ++#define STT_HIOS 12 /* End of OS-specific */ ++#define STT_LOPROC 13 /* Start of processor-specific */ ++#define STT_HIPROC 15 /* End of processor-specific */ ++ ++ ++/* Symbol table indices are found in the hash buckets and chain table ++ of a symbol hash table section. This special index value indicates ++ the end of a chain, meaning no further symbols are found in that bucket. */ ++ ++#define STN_UNDEF 0 /* End of a chain. */ ++ ++ ++/* How to extract and insert information held in the st_other field. */ ++ ++#define ELF32_ST_VISIBILITY(o) ((o) & 0x03) ++ ++/* For ELF64 the definitions are the same. */ ++#define ELF64_ST_VISIBILITY(o) ELF32_ST_VISIBILITY (o) ++ ++/* Symbol visibility specification encoded in the st_other field. */ ++#define STV_DEFAULT 0 /* Default symbol visibility rules */ ++#define STV_INTERNAL 1 /* Processor specific hidden class */ ++#define STV_HIDDEN 2 /* Sym unavailable in other modules */ ++#define STV_PROTECTED 3 /* Not preemptible, not exported */ ++ ++ ++/* Relocation table entry without addend (in section of type SHT_REL). */ ++ ++typedef struct ++{ ++ Elf32_Addr r_offset; /* Address */ ++ Elf32_Word r_info; /* Relocation type and symbol index */ ++} Elf32_Rel; ++ ++/* I have seen two different definitions of the Elf64_Rel and ++ Elf64_Rela structures, so we'll leave them out until Novell (or ++ whoever) gets their act together. */ ++/* The following, at least, is used on Sparc v9, MIPS, and Alpha. */ ++ ++typedef struct ++{ ++ Elf64_Addr r_offset; /* Address */ ++ Elf64_Xword r_info; /* Relocation type and symbol index */ ++} Elf64_Rel; ++ ++/* Relocation table entry with addend (in section of type SHT_RELA). */ ++ ++typedef struct ++{ ++ Elf32_Addr r_offset; /* Address */ ++ Elf32_Word r_info; /* Relocation type and symbol index */ ++ Elf32_Sword r_addend; /* Addend */ ++} Elf32_Rela; ++ ++typedef struct ++{ ++ Elf64_Addr r_offset; /* Address */ ++ Elf64_Xword r_info; /* Relocation type and symbol index */ ++ Elf64_Sxword r_addend; /* Addend */ ++} Elf64_Rela; ++ ++/* How to extract and insert information held in the r_info field. */ ++ ++#define ELF32_R_SYM(val) ((val) >> 8) ++#define ELF32_R_TYPE(val) ((val) & 0xff) ++#define ELF32_R_INFO(sym, type) (((sym) << 8) + ((type) & 0xff)) ++ ++#define ELF64_R_SYM(i) ((i) >> 32) ++#define ELF64_R_TYPE(i) ((i) & 0xffffffff) ++#define ELF64_R_INFO(sym,type) ((((Elf64_Xword) (sym)) << 32) + (type)) ++ ++/* Program segment header. */ ++ ++typedef struct ++{ ++ Elf32_Word p_type; /* Segment type */ ++ Elf32_Off p_offset; /* Segment file offset */ ++ Elf32_Addr p_vaddr; /* Segment virtual address */ ++ Elf32_Addr p_paddr; /* Segment physical address */ ++ Elf32_Word p_filesz; /* Segment size in file */ ++ Elf32_Word p_memsz; /* Segment size in memory */ ++ Elf32_Word p_flags; /* Segment flags */ ++ Elf32_Word p_align; /* Segment alignment */ ++} Elf32_Phdr; ++ ++typedef struct ++{ ++ Elf64_Word p_type; /* Segment type */ ++ Elf64_Word p_flags; /* Segment flags */ ++ Elf64_Off p_offset; /* Segment file offset */ ++ Elf64_Addr p_vaddr; /* Segment virtual address */ ++ Elf64_Addr p_paddr; /* Segment physical address */ ++ Elf64_Xword p_filesz; /* Segment size in file */ ++ Elf64_Xword p_memsz; /* Segment size in memory */ ++ Elf64_Xword p_align; /* Segment alignment */ ++} Elf64_Phdr; ++ ++/* Legal values for p_type (segment type). */ ++ ++#define PT_NULL 0 /* Program header table entry unused */ ++#define PT_LOAD 1 /* Loadable program segment */ ++#define PT_DYNAMIC 2 /* Dynamic linking information */ ++#define PT_INTERP 3 /* Program interpreter */ ++#define PT_NOTE 4 /* Auxiliary information */ ++#define PT_SHLIB 5 /* Reserved */ ++#define PT_PHDR 6 /* Entry for header table itself */ ++#define PT_TLS 7 /* Thread-local storage segment */ ++#define PT_NUM 8 /* Number of defined types */ ++#define PT_LOOS 0x60000000 /* Start of OS-specific */ ++#define PT_GNU_EH_FRAME 0x6474e550 /* GCC .eh_frame_hdr segment */ ++#define PT_GNU_STACK 0x6474e551 /* Indicates stack executability */ ++#define PT_LOSUNW 0x6ffffffa ++#define PT_SUNWBSS 0x6ffffffa /* Sun Specific segment */ ++#define PT_SUNWSTACK 0x6ffffffb /* Stack segment */ ++#define PT_HISUNW 0x6fffffff ++#define PT_HIOS 0x6fffffff /* End of OS-specific */ ++#define PT_LOPROC 0x70000000 /* Start of processor-specific */ ++#define PT_HIPROC 0x7fffffff /* End of processor-specific */ ++ ++/* Legal values for p_flags (segment flags). */ ++ ++#define PF_X (1 << 0) /* Segment is executable */ ++#define PF_W (1 << 1) /* Segment is writable */ ++#define PF_R (1 << 2) /* Segment is readable */ ++#define PF_MASKOS 0x0ff00000 /* OS-specific */ ++#define PF_MASKPROC 0xf0000000 /* Processor-specific */ ++ ++/* Legal values for note segment descriptor types for core files. */ ++ ++#define NT_PRSTATUS 1 /* Contains copy of prstatus struct */ ++#define NT_FPREGSET 2 /* Contains copy of fpregset struct */ ++#define NT_PRPSINFO 3 /* Contains copy of prpsinfo struct */ ++#define NT_PRXREG 4 /* Contains copy of prxregset struct */ ++#define NT_TASKSTRUCT 4 /* Contains copy of task structure */ ++#define NT_PLATFORM 5 /* String from sysinfo(SI_PLATFORM) */ ++#define NT_AUXV 6 /* Contains copy of auxv array */ ++#define NT_GWINDOWS 7 /* Contains copy of gwindows struct */ ++#define NT_ASRS 8 /* Contains copy of asrset struct */ ++#define NT_PSTATUS 10 /* Contains copy of pstatus struct */ ++#define NT_PSINFO 13 /* Contains copy of psinfo struct */ ++#define NT_PRCRED 14 /* Contains copy of prcred struct */ ++#define NT_UTSNAME 15 /* Contains copy of utsname struct */ ++#define NT_LWPSTATUS 16 /* Contains copy of lwpstatus struct */ ++#define NT_LWPSINFO 17 /* Contains copy of lwpinfo struct */ ++#define NT_PRFPXREG 20 /* Contains copy of fprxregset struct*/ ++ ++/* Legal values for the note segment descriptor types for object files. */ ++ ++#define NT_VERSION 1 /* Contains a version string. */ ++ ++ ++/* Dynamic section entry. */ ++ ++typedef struct ++{ ++ Elf32_Sword d_tag; /* Dynamic entry type */ ++ union ++ { ++ Elf32_Word d_val; /* Integer value */ ++ Elf32_Addr d_ptr; /* Address value */ ++ } d_un; ++} Elf32_Dyn; ++ ++typedef struct ++{ ++ Elf64_Sxword d_tag; /* Dynamic entry type */ ++ union ++ { ++ Elf64_Xword d_val; /* Integer value */ ++ Elf64_Addr d_ptr; /* Address value */ ++ } d_un; ++} Elf64_Dyn; ++ ++/* Legal values for d_tag (dynamic entry type). */ ++ ++#define DT_NULL 0 /* Marks end of dynamic section */ ++#define DT_NEEDED 1 /* Name of needed library */ ++#define DT_PLTRELSZ 2 /* Size in bytes of PLT relocs */ ++#define DT_PLTGOT 3 /* Processor defined value */ ++#define DT_HASH 4 /* Address of symbol hash table */ ++#define DT_STRTAB 5 /* Address of string table */ ++#define DT_SYMTAB 6 /* Address of symbol table */ ++#define DT_RELA 7 /* Address of Rela relocs */ ++#define DT_RELASZ 8 /* Total size of Rela relocs */ ++#define DT_RELAENT 9 /* Size of one Rela reloc */ ++#define DT_STRSZ 10 /* Size of string table */ ++#define DT_SYMENT 11 /* Size of one symbol table entry */ ++#define DT_INIT 12 /* Address of init function */ ++#define DT_FINI 13 /* Address of termination function */ ++#define DT_SONAME 14 /* Name of shared object */ ++#define DT_RPATH 15 /* Library search path (deprecated) */ ++#define DT_SYMBOLIC 16 /* Start symbol search here */ ++#define DT_REL 17 /* Address of Rel relocs */ ++#define DT_RELSZ 18 /* Total size of Rel relocs */ ++#define DT_RELENT 19 /* Size of one Rel reloc */ ++#define DT_PLTREL 20 /* Type of reloc in PLT */ ++#define DT_DEBUG 21 /* For debugging; unspecified */ ++#define DT_TEXTREL 22 /* Reloc might modify .text */ ++#define DT_JMPREL 23 /* Address of PLT relocs */ ++#define DT_BIND_NOW 24 /* Process relocations of object */ ++#define DT_INIT_ARRAY 25 /* Array with addresses of init fct */ ++#define DT_FINI_ARRAY 26 /* Array with addresses of fini fct */ ++#define DT_INIT_ARRAYSZ 27 /* Size in bytes of DT_INIT_ARRAY */ ++#define DT_FINI_ARRAYSZ 28 /* Size in bytes of DT_FINI_ARRAY */ ++#define DT_RUNPATH 29 /* Library search path */ ++#define DT_FLAGS 30 /* Flags for the object being loaded */ ++#define DT_ENCODING 32 /* Start of encoded range */ ++#define DT_PREINIT_ARRAY 32 /* Array with addresses of preinit fct*/ ++#define DT_PREINIT_ARRAYSZ 33 /* size in bytes of DT_PREINIT_ARRAY */ ++#define DT_NUM 34 /* Number used */ ++#define DT_LOOS 0x6000000d /* Start of OS-specific */ ++#define DT_HIOS 0x6ffff000 /* End of OS-specific */ ++#define DT_LOPROC 0x70000000 /* Start of processor-specific */ ++#define DT_HIPROC 0x7fffffff /* End of processor-specific */ ++#define DT_PROCNUM DT_MIPS_NUM /* Most used by any processor */ ++ ++/* DT_* entries which fall between DT_VALRNGHI & DT_VALRNGLO use the ++ Dyn.d_un.d_val field of the Elf*_Dyn structure. This follows Sun's ++ approach. */ ++#define DT_VALRNGLO 0x6ffffd00 ++#define DT_GNU_PRELINKED 0x6ffffdf5 /* Prelinking timestamp */ ++#define DT_GNU_CONFLICTSZ 0x6ffffdf6 /* Size of conflict section */ ++#define DT_GNU_LIBLISTSZ 0x6ffffdf7 /* Size of library list */ ++#define DT_CHECKSUM 0x6ffffdf8 ++#define DT_PLTPADSZ 0x6ffffdf9 ++#define DT_MOVEENT 0x6ffffdfa ++#define DT_MOVESZ 0x6ffffdfb ++#define DT_FEATURE_1 0x6ffffdfc /* Feature selection (DTF_*). */ ++#define DT_POSFLAG_1 0x6ffffdfd /* Flags for DT_* entries, effecting ++ the following DT_* entry. */ ++#define DT_SYMINSZ 0x6ffffdfe /* Size of syminfo table (in bytes) */ ++#define DT_SYMINENT 0x6ffffdff /* Entry size of syminfo */ ++#define DT_VALRNGHI 0x6ffffdff ++#define DT_VALTAGIDX(tag) (DT_VALRNGHI - (tag)) /* Reverse order! */ ++#define DT_VALNUM 12 ++ ++/* DT_* entries which fall between DT_ADDRRNGHI & DT_ADDRRNGLO use the ++ Dyn.d_un.d_ptr field of the Elf*_Dyn structure. ++ ++ If any adjustment is made to the ELF object after it has been ++ built these entries will need to be adjusted. */ ++#define DT_ADDRRNGLO 0x6ffffe00 ++#define DT_GNU_CONFLICT 0x6ffffef8 /* Start of conflict section */ ++#define DT_GNU_LIBLIST 0x6ffffef9 /* Library list */ ++#define DT_CONFIG 0x6ffffefa /* Configuration information. */ ++#define DT_DEPAUDIT 0x6ffffefb /* Dependency auditing. */ ++#define DT_AUDIT 0x6ffffefc /* Object auditing. */ ++#define DT_PLTPAD 0x6ffffefd /* PLT padding. */ ++#define DT_MOVETAB 0x6ffffefe /* Move table. */ ++#define DT_SYMINFO 0x6ffffeff /* Syminfo table. */ ++#define DT_ADDRRNGHI 0x6ffffeff ++#define DT_ADDRTAGIDX(tag) (DT_ADDRRNGHI - (tag)) /* Reverse order! */ ++#define DT_ADDRNUM 10 ++ ++/* The versioning entry types. The next are defined as part of the ++ GNU extension. */ ++#define DT_VERSYM 0x6ffffff0 ++ ++#define DT_RELACOUNT 0x6ffffff9 ++#define DT_RELCOUNT 0x6ffffffa ++ ++/* These were chosen by Sun. */ ++#define DT_FLAGS_1 0x6ffffffb /* State flags, see DF_1_* below. */ ++#define DT_VERDEF 0x6ffffffc /* Address of version definition ++ table */ ++#define DT_VERDEFNUM 0x6ffffffd /* Number of version definitions */ ++#define DT_VERNEED 0x6ffffffe /* Address of table with needed ++ versions */ ++#define DT_VERNEEDNUM 0x6fffffff /* Number of needed versions */ ++#define DT_VERSIONTAGIDX(tag) (DT_VERNEEDNUM - (tag)) /* Reverse order! */ ++#define DT_VERSIONTAGNUM 16 ++ ++/* Sun added these machine-independent extensions in the "processor-specific" ++ range. Be compatible. */ ++#define DT_AUXILIARY 0x7ffffffd /* Shared object to load before self */ ++#define DT_FILTER 0x7fffffff /* Shared object to get values from */ ++#define DT_EXTRATAGIDX(tag) ((Elf32_Word)-((Elf32_Sword) (tag) <<1>>1)-1) ++#define DT_EXTRANUM 3 ++ ++/* Values of `d_un.d_val' in the DT_FLAGS entry. */ ++#define DF_ORIGIN 0x00000001 /* Object may use DF_ORIGIN */ ++#define DF_SYMBOLIC 0x00000002 /* Symbol resolutions starts here */ ++#define DF_TEXTREL 0x00000004 /* Object contains text relocations */ ++#define DF_BIND_NOW 0x00000008 /* No lazy binding for this object */ ++#define DF_STATIC_TLS 0x00000010 /* Module uses the static TLS model */ ++ ++/* State flags selectable in the `d_un.d_val' element of the DT_FLAGS_1 ++ entry in the dynamic section. */ ++#define DF_1_NOW 0x00000001 /* Set RTLD_NOW for this object. */ ++#define DF_1_GLOBAL 0x00000002 /* Set RTLD_GLOBAL for this object. */ ++#define DF_1_GROUP 0x00000004 /* Set RTLD_GROUP for this object. */ ++#define DF_1_NODELETE 0x00000008 /* Set RTLD_NODELETE for this object.*/ ++#define DF_1_LOADFLTR 0x00000010 /* Trigger filtee loading at runtime.*/ ++#define DF_1_INITFIRST 0x00000020 /* Set RTLD_INITFIRST for this object*/ ++#define DF_1_NOOPEN 0x00000040 /* Set RTLD_NOOPEN for this object. */ ++#define DF_1_ORIGIN 0x00000080 /* $ORIGIN must be handled. */ ++#define DF_1_DIRECT 0x00000100 /* Direct binding enabled. */ ++#define DF_1_TRANS 0x00000200 ++#define DF_1_INTERPOSE 0x00000400 /* Object is used to interpose. */ ++#define DF_1_NODEFLIB 0x00000800 /* Ignore default lib search path. */ ++#define DF_1_NODUMP 0x00001000 /* Object can't be dldump'ed. */ ++#define DF_1_CONFALT 0x00002000 /* Configuration alternative created.*/ ++#define DF_1_ENDFILTEE 0x00004000 /* Filtee terminates filters search. */ ++#define DF_1_DISPRELDNE 0x00008000 /* Disp reloc applied at build time. */ ++#define DF_1_DISPRELPND 0x00010000 /* Disp reloc applied at run-time. */ ++ ++/* Flags for the feature selection in DT_FEATURE_1. */ ++#define DTF_1_PARINIT 0x00000001 ++#define DTF_1_CONFEXP 0x00000002 ++ ++/* Flags in the DT_POSFLAG_1 entry effecting only the next DT_* entry. */ ++#define DF_P1_LAZYLOAD 0x00000001 /* Lazyload following object. */ ++#define DF_P1_GROUPPERM 0x00000002 /* Symbols from next object are not ++ generally available. */ ++ ++/* Version definition sections. */ ++ ++typedef struct ++{ ++ Elf32_Half vd_version; /* Version revision */ ++ Elf32_Half vd_flags; /* Version information */ ++ Elf32_Half vd_ndx; /* Version Index */ ++ Elf32_Half vd_cnt; /* Number of associated aux entries */ ++ Elf32_Word vd_hash; /* Version name hash value */ ++ Elf32_Word vd_aux; /* Offset in bytes to verdaux array */ ++ Elf32_Word vd_next; /* Offset in bytes to next verdef ++ entry */ ++} Elf32_Verdef; ++ ++typedef struct ++{ ++ Elf64_Half vd_version; /* Version revision */ ++ Elf64_Half vd_flags; /* Version information */ ++ Elf64_Half vd_ndx; /* Version Index */ ++ Elf64_Half vd_cnt; /* Number of associated aux entries */ ++ Elf64_Word vd_hash; /* Version name hash value */ ++ Elf64_Word vd_aux; /* Offset in bytes to verdaux array */ ++ Elf64_Word vd_next; /* Offset in bytes to next verdef ++ entry */ ++} Elf64_Verdef; ++ ++ ++/* Legal values for vd_version (version revision). */ ++#define VER_DEF_NONE 0 /* No version */ ++#define VER_DEF_CURRENT 1 /* Current version */ ++#define VER_DEF_NUM 2 /* Given version number */ ++ ++/* Legal values for vd_flags (version information flags). */ ++#define VER_FLG_BASE 0x1 /* Version definition of file itself */ ++#define VER_FLG_WEAK 0x2 /* Weak version identifier */ ++ ++/* Versym symbol index values. */ ++#define VER_NDX_LOCAL 0 /* Symbol is local. */ ++#define VER_NDX_GLOBAL 1 /* Symbol is global. */ ++#define VER_NDX_LORESERVE 0xff00 /* Beginning of reserved entries. */ ++#define VER_NDX_ELIMINATE 0xff01 /* Symbol is to be eliminated. */ ++ ++/* Auxialiary version information. */ ++ ++typedef struct ++{ ++ Elf32_Word vda_name; /* Version or dependency names */ ++ Elf32_Word vda_next; /* Offset in bytes to next verdaux ++ entry */ ++} Elf32_Verdaux; ++ ++typedef struct ++{ ++ Elf64_Word vda_name; /* Version or dependency names */ ++ Elf64_Word vda_next; /* Offset in bytes to next verdaux ++ entry */ ++} Elf64_Verdaux; ++ ++ ++/* Version dependency section. */ ++ ++typedef struct ++{ ++ Elf32_Half vn_version; /* Version of structure */ ++ Elf32_Half vn_cnt; /* Number of associated aux entries */ ++ Elf32_Word vn_file; /* Offset of filename for this ++ dependency */ ++ Elf32_Word vn_aux; /* Offset in bytes to vernaux array */ ++ Elf32_Word vn_next; /* Offset in bytes to next verneed ++ entry */ ++} Elf32_Verneed; ++ ++typedef struct ++{ ++ Elf64_Half vn_version; /* Version of structure */ ++ Elf64_Half vn_cnt; /* Number of associated aux entries */ ++ Elf64_Word vn_file; /* Offset of filename for this ++ dependency */ ++ Elf64_Word vn_aux; /* Offset in bytes to vernaux array */ ++ Elf64_Word vn_next; /* Offset in bytes to next verneed ++ entry */ ++} Elf64_Verneed; ++ ++ ++/* Legal values for vn_version (version revision). */ ++#define VER_NEED_NONE 0 /* No version */ ++#define VER_NEED_CURRENT 1 /* Current version */ ++#define VER_NEED_NUM 2 /* Given version number */ ++ ++/* Auxiliary needed version information. */ ++ ++typedef struct ++{ ++ Elf32_Word vna_hash; /* Hash value of dependency name */ ++ Elf32_Half vna_flags; /* Dependency specific information */ ++ Elf32_Half vna_other; /* Unused */ ++ Elf32_Word vna_name; /* Dependency name string offset */ ++ Elf32_Word vna_next; /* Offset in bytes to next vernaux ++ entry */ ++} Elf32_Vernaux; ++ ++typedef struct ++{ ++ Elf64_Word vna_hash; /* Hash value of dependency name */ ++ Elf64_Half vna_flags; /* Dependency specific information */ ++ Elf64_Half vna_other; /* Unused */ ++ Elf64_Word vna_name; /* Dependency name string offset */ ++ Elf64_Word vna_next; /* Offset in bytes to next vernaux ++ entry */ ++} Elf64_Vernaux; ++ ++ ++/* Legal values for vna_flags. */ ++#define VER_FLG_WEAK 0x2 /* Weak version identifier */ ++ ++ ++/* Auxiliary vector. */ ++ ++/* This vector is normally only used by the program interpreter. The ++ usual definition in an ABI supplement uses the name auxv_t. The ++ vector is not usually defined in a standard file, but it ++ can't hurt. We rename it to avoid conflicts. The sizes of these ++ types are an arrangement between the exec server and the program ++ interpreter, so we don't fully specify them here. */ ++ ++typedef struct ++{ ++ int a_type; /* Entry type */ ++ union ++ { ++ long int a_val; /* Integer value */ ++ void *a_ptr; /* Pointer value */ ++ void (*a_fcn) (void); /* Function pointer value */ ++ } a_un; ++} Elf32_auxv_t; ++ ++typedef struct ++{ ++ long int a_type; /* Entry type */ ++ union ++ { ++ long int a_val; /* Integer value */ ++ void *a_ptr; /* Pointer value */ ++ void (*a_fcn) (void); /* Function pointer value */ ++ } a_un; ++} Elf64_auxv_t; ++ ++/* Legal values for a_type (entry type). */ ++ ++#define AT_NULL 0 /* End of vector */ ++#define AT_IGNORE 1 /* Entry should be ignored */ ++#define AT_EXECFD 2 /* File descriptor of program */ ++#define AT_PHDR 3 /* Program headers for program */ ++#define AT_PHENT 4 /* Size of program header entry */ ++#define AT_PHNUM 5 /* Number of program headers */ ++#define AT_PAGESZ 6 /* System page size */ ++#define AT_BASE 7 /* Base address of interpreter */ ++#define AT_FLAGS 8 /* Flags */ ++#define AT_ENTRY 9 /* Entry point of program */ ++#define AT_NOTELF 10 /* Program is not ELF */ ++#define AT_UID 11 /* Real uid */ ++#define AT_EUID 12 /* Effective uid */ ++#define AT_GID 13 /* Real gid */ ++#define AT_EGID 14 /* Effective gid */ ++#define AT_CLKTCK 17 /* Frequency of times() */ ++ ++/* Some more special a_type values describing the hardware. */ ++#define AT_PLATFORM 15 /* String identifying platform. */ ++#define AT_HWCAP 16 /* Machine dependent hints about ++ processor capabilities. */ ++ ++/* This entry gives some information about the FPU initialization ++ performed by the kernel. */ ++#define AT_FPUCW 18 /* Used FPU control word. */ ++ ++/* Cache block sizes. */ ++#define AT_DCACHEBSIZE 19 /* Data cache block size. */ ++#define AT_ICACHEBSIZE 20 /* Instruction cache block size. */ ++#define AT_UCACHEBSIZE 21 /* Unified cache block size. */ ++ ++/* A special ignored value for PPC, used by the kernel to control the ++ interpretation of the AUXV. Must be > 16. */ ++#define AT_IGNOREPPC 22 /* Entry should be ignored. */ ++ ++#define AT_SECURE 23 /* Boolean, was exec setuid-like? */ ++ ++/* Pointer to the global system page used for system calls and other ++ nice things. */ ++#define AT_SYSINFO 32 ++#define AT_SYSINFO_EHDR 33 ++ ++ ++/* Note section contents. Each entry in the note section begins with ++ a header of a fixed form. */ ++ ++typedef struct ++{ ++ Elf32_Word n_namesz; /* Length of the note's name. */ ++ Elf32_Word n_descsz; /* Length of the note's descriptor. */ ++ Elf32_Word n_type; /* Type of the note. */ ++} Elf32_Nhdr; ++ ++typedef struct ++{ ++ Elf64_Word n_namesz; /* Length of the note's name. */ ++ Elf64_Word n_descsz; /* Length of the note's descriptor. */ ++ Elf64_Word n_type; /* Type of the note. */ ++} Elf64_Nhdr; ++ ++/* Known names of notes. */ ++ ++/* Solaris entries in the note section have this name. */ ++#define ELF_NOTE_SOLARIS "SUNW Solaris" ++ ++/* Note entries for GNU systems have this name. */ ++#define ELF_NOTE_GNU "GNU" ++ ++ ++/* Defined types of notes for Solaris. */ ++ ++/* Value of descriptor (one word) is desired pagesize for the binary. */ ++#define ELF_NOTE_PAGESIZE_HINT 1 ++ ++ ++/* Defined note types for GNU systems. */ ++ ++/* ABI information. The descriptor consists of words: ++ word 0: OS descriptor ++ word 1: major version of the ABI ++ word 2: minor version of the ABI ++ word 3: subminor version of the ABI ++*/ ++#define ELF_NOTE_ABI 1 ++ ++/* Known OSes. These value can appear in word 0 of an ELF_NOTE_ABI ++ note section entry. */ ++#define ELF_NOTE_OS_LINUX 0 ++#define ELF_NOTE_OS_GNU 1 ++#define ELF_NOTE_OS_SOLARIS2 2 ++#define ELF_NOTE_OS_FREEBSD 3 ++ ++ ++/* Move records. */ ++typedef struct ++{ ++ Elf32_Xword m_value; /* Symbol value. */ ++ Elf32_Word m_info; /* Size and index. */ ++ Elf32_Word m_poffset; /* Symbol offset. */ ++ Elf32_Half m_repeat; /* Repeat count. */ ++ Elf32_Half m_stride; /* Stride info. */ ++} Elf32_Move; ++ ++typedef struct ++{ ++ Elf64_Xword m_value; /* Symbol value. */ ++ Elf64_Xword m_info; /* Size and index. */ ++ Elf64_Xword m_poffset; /* Symbol offset. */ ++ Elf64_Half m_repeat; /* Repeat count. */ ++ Elf64_Half m_stride; /* Stride info. */ ++} Elf64_Move; ++ ++/* Macro to construct move records. */ ++#define ELF32_M_SYM(info) ((info) >> 8) ++#define ELF32_M_SIZE(info) ((unsigned char) (info)) ++#define ELF32_M_INFO(sym, size) (((sym) << 8) + (unsigned char) (size)) ++ ++#define ELF64_M_SYM(info) ELF32_M_SYM (info) ++#define ELF64_M_SIZE(info) ELF32_M_SIZE (info) ++#define ELF64_M_INFO(sym, size) ELF32_M_INFO (sym, size) ++ ++ ++/* Motorola 68k specific definitions. */ ++ ++/* Values for Elf32_Ehdr.e_flags. */ ++#define EF_CPU32 0x00810000 ++ ++/* m68k relocs. */ ++ ++#define R_68K_NONE 0 /* No reloc */ ++#define R_68K_32 1 /* Direct 32 bit */ ++#define R_68K_16 2 /* Direct 16 bit */ ++#define R_68K_8 3 /* Direct 8 bit */ ++#define R_68K_PC32 4 /* PC relative 32 bit */ ++#define R_68K_PC16 5 /* PC relative 16 bit */ ++#define R_68K_PC8 6 /* PC relative 8 bit */ ++#define R_68K_GOT32 7 /* 32 bit PC relative GOT entry */ ++#define R_68K_GOT16 8 /* 16 bit PC relative GOT entry */ ++#define R_68K_GOT8 9 /* 8 bit PC relative GOT entry */ ++#define R_68K_GOT32O 10 /* 32 bit GOT offset */ ++#define R_68K_GOT16O 11 /* 16 bit GOT offset */ ++#define R_68K_GOT8O 12 /* 8 bit GOT offset */ ++#define R_68K_PLT32 13 /* 32 bit PC relative PLT address */ ++#define R_68K_PLT16 14 /* 16 bit PC relative PLT address */ ++#define R_68K_PLT8 15 /* 8 bit PC relative PLT address */ ++#define R_68K_PLT32O 16 /* 32 bit PLT offset */ ++#define R_68K_PLT16O 17 /* 16 bit PLT offset */ ++#define R_68K_PLT8O 18 /* 8 bit PLT offset */ ++#define R_68K_COPY 19 /* Copy symbol at runtime */ ++#define R_68K_GLOB_DAT 20 /* Create GOT entry */ ++#define R_68K_JMP_SLOT 21 /* Create PLT entry */ ++#define R_68K_RELATIVE 22 /* Adjust by program base */ ++/* Keep this the last entry. */ ++#define R_68K_NUM 23 ++ ++/* Intel 80386 specific definitions. */ ++ ++/* i386 relocs. */ ++ ++#define R_386_NONE 0 /* No reloc */ ++#define R_386_32 1 /* Direct 32 bit */ ++#define R_386_PC32 2 /* PC relative 32 bit */ ++#define R_386_GOT32 3 /* 32 bit GOT entry */ ++#define R_386_PLT32 4 /* 32 bit PLT address */ ++#define R_386_COPY 5 /* Copy symbol at runtime */ ++#define R_386_GLOB_DAT 6 /* Create GOT entry */ ++#define R_386_JMP_SLOT 7 /* Create PLT entry */ ++#define R_386_RELATIVE 8 /* Adjust by program base */ ++#define R_386_GOTOFF 9 /* 32 bit offset to GOT */ ++#define R_386_GOTPC 10 /* 32 bit PC relative offset to GOT */ ++#define R_386_32PLT 11 ++#define R_386_TLS_TPOFF 14 /* Offset in static TLS block */ ++#define R_386_TLS_IE 15 /* Address of GOT entry for static TLS ++ block offset */ ++#define R_386_TLS_GOTIE 16 /* GOT entry for static TLS block ++ offset */ ++#define R_386_TLS_LE 17 /* Offset relative to static TLS ++ block */ ++#define R_386_TLS_GD 18 /* Direct 32 bit for GNU version of ++ general dynamic thread local data */ ++#define R_386_TLS_LDM 19 /* Direct 32 bit for GNU version of ++ local dynamic thread local data ++ in LE code */ ++#define R_386_16 20 ++#define R_386_PC16 21 ++#define R_386_8 22 ++#define R_386_PC8 23 ++#define R_386_TLS_GD_32 24 /* Direct 32 bit for general dynamic ++ thread local data */ ++#define R_386_TLS_GD_PUSH 25 /* Tag for pushl in GD TLS code */ ++#define R_386_TLS_GD_CALL 26 /* Relocation for call to ++ __tls_get_addr() */ ++#define R_386_TLS_GD_POP 27 /* Tag for popl in GD TLS code */ ++#define R_386_TLS_LDM_32 28 /* Direct 32 bit for local dynamic ++ thread local data in LE code */ ++#define R_386_TLS_LDM_PUSH 29 /* Tag for pushl in LDM TLS code */ ++#define R_386_TLS_LDM_CALL 30 /* Relocation for call to ++ __tls_get_addr() in LDM code */ ++#define R_386_TLS_LDM_POP 31 /* Tag for popl in LDM TLS code */ ++#define R_386_TLS_LDO_32 32 /* Offset relative to TLS block */ ++#define R_386_TLS_IE_32 33 /* GOT entry for negated static TLS ++ block offset */ ++#define R_386_TLS_LE_32 34 /* Negated offset relative to static ++ TLS block */ ++#define R_386_TLS_DTPMOD32 35 /* ID of module containing symbol */ ++#define R_386_TLS_DTPOFF32 36 /* Offset in TLS block */ ++#define R_386_TLS_TPOFF32 37 /* Negated offset in static TLS block */ ++/* Keep this the last entry. */ ++#define R_386_NUM 38 ++ ++/* SUN SPARC specific definitions. */ ++ ++/* Legal values for ST_TYPE subfield of st_info (symbol type). */ ++ ++#define STT_REGISTER 13 /* Global register reserved to app. */ ++ ++/* Values for Elf64_Ehdr.e_flags. */ ++ ++#define EF_SPARCV9_MM 3 ++#define EF_SPARCV9_TSO 0 ++#define EF_SPARCV9_PSO 1 ++#define EF_SPARCV9_RMO 2 ++#define EF_SPARC_LEDATA 0x800000 /* little endian data */ ++#define EF_SPARC_EXT_MASK 0xFFFF00 ++#define EF_SPARC_32PLUS 0x000100 /* generic V8+ features */ ++#define EF_SPARC_SUN_US1 0x000200 /* Sun UltraSPARC1 extensions */ ++#define EF_SPARC_HAL_R1 0x000400 /* HAL R1 extensions */ ++#define EF_SPARC_SUN_US3 0x000800 /* Sun UltraSPARCIII extensions */ ++ ++/* SPARC relocs. */ ++ ++#define R_SPARC_NONE 0 /* No reloc */ ++#define R_SPARC_8 1 /* Direct 8 bit */ ++#define R_SPARC_16 2 /* Direct 16 bit */ ++#define R_SPARC_32 3 /* Direct 32 bit */ ++#define R_SPARC_DISP8 4 /* PC relative 8 bit */ ++#define R_SPARC_DISP16 5 /* PC relative 16 bit */ ++#define R_SPARC_DISP32 6 /* PC relative 32 bit */ ++#define R_SPARC_WDISP30 7 /* PC relative 30 bit shifted */ ++#define R_SPARC_WDISP22 8 /* PC relative 22 bit shifted */ ++#define R_SPARC_HI22 9 /* High 22 bit */ ++#define R_SPARC_22 10 /* Direct 22 bit */ ++#define R_SPARC_13 11 /* Direct 13 bit */ ++#define R_SPARC_LO10 12 /* Truncated 10 bit */ ++#define R_SPARC_GOT10 13 /* Truncated 10 bit GOT entry */ ++#define R_SPARC_GOT13 14 /* 13 bit GOT entry */ ++#define R_SPARC_GOT22 15 /* 22 bit GOT entry shifted */ ++#define R_SPARC_PC10 16 /* PC relative 10 bit truncated */ ++#define R_SPARC_PC22 17 /* PC relative 22 bit shifted */ ++#define R_SPARC_WPLT30 18 /* 30 bit PC relative PLT address */ ++#define R_SPARC_COPY 19 /* Copy symbol at runtime */ ++#define R_SPARC_GLOB_DAT 20 /* Create GOT entry */ ++#define R_SPARC_JMP_SLOT 21 /* Create PLT entry */ ++#define R_SPARC_RELATIVE 22 /* Adjust by program base */ ++#define R_SPARC_UA32 23 /* Direct 32 bit unaligned */ ++ ++/* Additional Sparc64 relocs. */ ++ ++#define R_SPARC_PLT32 24 /* Direct 32 bit ref to PLT entry */ ++#define R_SPARC_HIPLT22 25 /* High 22 bit PLT entry */ ++#define R_SPARC_LOPLT10 26 /* Truncated 10 bit PLT entry */ ++#define R_SPARC_PCPLT32 27 /* PC rel 32 bit ref to PLT entry */ ++#define R_SPARC_PCPLT22 28 /* PC rel high 22 bit PLT entry */ ++#define R_SPARC_PCPLT10 29 /* PC rel trunc 10 bit PLT entry */ ++#define R_SPARC_10 30 /* Direct 10 bit */ ++#define R_SPARC_11 31 /* Direct 11 bit */ ++#define R_SPARC_64 32 /* Direct 64 bit */ ++#define R_SPARC_OLO10 33 /* 10bit with secondary 13bit addend */ ++#define R_SPARC_HH22 34 /* Top 22 bits of direct 64 bit */ ++#define R_SPARC_HM10 35 /* High middle 10 bits of ... */ ++#define R_SPARC_LM22 36 /* Low middle 22 bits of ... */ ++#define R_SPARC_PC_HH22 37 /* Top 22 bits of pc rel 64 bit */ ++#define R_SPARC_PC_HM10 38 /* High middle 10 bit of ... */ ++#define R_SPARC_PC_LM22 39 /* Low miggle 22 bits of ... */ ++#define R_SPARC_WDISP16 40 /* PC relative 16 bit shifted */ ++#define R_SPARC_WDISP19 41 /* PC relative 19 bit shifted */ ++#define R_SPARC_7 43 /* Direct 7 bit */ ++#define R_SPARC_5 44 /* Direct 5 bit */ ++#define R_SPARC_6 45 /* Direct 6 bit */ ++#define R_SPARC_DISP64 46 /* PC relative 64 bit */ ++#define R_SPARC_PLT64 47 /* Direct 64 bit ref to PLT entry */ ++#define R_SPARC_HIX22 48 /* High 22 bit complemented */ ++#define R_SPARC_LOX10 49 /* Truncated 11 bit complemented */ ++#define R_SPARC_H44 50 /* Direct high 12 of 44 bit */ ++#define R_SPARC_M44 51 /* Direct mid 22 of 44 bit */ ++#define R_SPARC_L44 52 /* Direct low 10 of 44 bit */ ++#define R_SPARC_REGISTER 53 /* Global register usage */ ++#define R_SPARC_UA64 54 /* Direct 64 bit unaligned */ ++#define R_SPARC_UA16 55 /* Direct 16 bit unaligned */ ++#define R_SPARC_TLS_GD_HI22 56 ++#define R_SPARC_TLS_GD_LO10 57 ++#define R_SPARC_TLS_GD_ADD 58 ++#define R_SPARC_TLS_GD_CALL 59 ++#define R_SPARC_TLS_LDM_HI22 60 ++#define R_SPARC_TLS_LDM_LO10 61 ++#define R_SPARC_TLS_LDM_ADD 62 ++#define R_SPARC_TLS_LDM_CALL 63 ++#define R_SPARC_TLS_LDO_HIX22 64 ++#define R_SPARC_TLS_LDO_LOX10 65 ++#define R_SPARC_TLS_LDO_ADD 66 ++#define R_SPARC_TLS_IE_HI22 67 ++#define R_SPARC_TLS_IE_LO10 68 ++#define R_SPARC_TLS_IE_LD 69 ++#define R_SPARC_TLS_IE_LDX 70 ++#define R_SPARC_TLS_IE_ADD 71 ++#define R_SPARC_TLS_LE_HIX22 72 ++#define R_SPARC_TLS_LE_LOX10 73 ++#define R_SPARC_TLS_DTPMOD32 74 ++#define R_SPARC_TLS_DTPMOD64 75 ++#define R_SPARC_TLS_DTPOFF32 76 ++#define R_SPARC_TLS_DTPOFF64 77 ++#define R_SPARC_TLS_TPOFF32 78 ++#define R_SPARC_TLS_TPOFF64 79 ++/* Keep this the last entry. */ ++#define R_SPARC_NUM 80 ++ ++/* For Sparc64, legal values for d_tag of Elf64_Dyn. */ ++ ++#define DT_SPARC_REGISTER 0x70000001 ++#define DT_SPARC_NUM 2 ++ ++/* Bits present in AT_HWCAP, primarily for Sparc32. */ ++ ++#define HWCAP_SPARC_FLUSH 1 /* The cpu supports flush insn. */ ++#define HWCAP_SPARC_STBAR 2 ++#define HWCAP_SPARC_SWAP 4 ++#define HWCAP_SPARC_MULDIV 8 ++#define HWCAP_SPARC_V9 16 /* The cpu is v9, so v8plus is ok. */ ++#define HWCAP_SPARC_ULTRA3 32 ++ ++/* MIPS R3000 specific definitions. */ ++ ++/* Legal values for e_flags field of Elf32_Ehdr. */ ++ ++#define EF_MIPS_NOREORDER 1 /* A .noreorder directive was used */ ++#define EF_MIPS_PIC 2 /* Contains PIC code */ ++#define EF_MIPS_CPIC 4 /* Uses PIC calling sequence */ ++#define EF_MIPS_XGOT 8 ++#define EF_MIPS_64BIT_WHIRL 16 ++#define EF_MIPS_ABI2 32 ++#define EF_MIPS_ABI_ON32 64 ++#define EF_MIPS_ARCH 0xf0000000 /* MIPS architecture level */ ++ ++/* Legal values for MIPS architecture level. */ ++ ++#define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ ++#define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ ++#define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ ++#define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ ++#define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ ++#define EF_MIPS_ARCH_32 0x60000000 /* MIPS32 code. */ ++#define EF_MIPS_ARCH_64 0x70000000 /* MIPS64 code. */ ++ ++/* The following are non-official names and should not be used. */ ++ ++#define E_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ ++#define E_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ ++#define E_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ ++#define E_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ ++#define E_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ ++#define E_MIPS_ARCH_32 0x60000000 /* MIPS32 code. */ ++#define E_MIPS_ARCH_64 0x70000000 /* MIPS64 code. */ ++ ++/* Special section indices. */ ++ ++#define SHN_MIPS_ACOMMON 0xff00 /* Allocated common symbols */ ++#define SHN_MIPS_TEXT 0xff01 /* Allocated test symbols. */ ++#define SHN_MIPS_DATA 0xff02 /* Allocated data symbols. */ ++#define SHN_MIPS_SCOMMON 0xff03 /* Small common symbols */ ++#define SHN_MIPS_SUNDEFINED 0xff04 /* Small undefined symbols */ ++ ++/* Legal values for sh_type field of Elf32_Shdr. */ ++ ++#define SHT_MIPS_LIBLIST 0x70000000 /* Shared objects used in link */ ++#define SHT_MIPS_MSYM 0x70000001 ++#define SHT_MIPS_CONFLICT 0x70000002 /* Conflicting symbols */ ++#define SHT_MIPS_GPTAB 0x70000003 /* Global data area sizes */ ++#define SHT_MIPS_UCODE 0x70000004 /* Reserved for SGI/MIPS compilers */ ++#define SHT_MIPS_DEBUG 0x70000005 /* MIPS ECOFF debugging information*/ ++#define SHT_MIPS_REGINFO 0x70000006 /* Register usage information */ ++#define SHT_MIPS_PACKAGE 0x70000007 ++#define SHT_MIPS_PACKSYM 0x70000008 ++#define SHT_MIPS_RELD 0x70000009 ++#define SHT_MIPS_IFACE 0x7000000b ++#define SHT_MIPS_CONTENT 0x7000000c ++#define SHT_MIPS_OPTIONS 0x7000000d /* Miscellaneous options. */ ++#define SHT_MIPS_SHDR 0x70000010 ++#define SHT_MIPS_FDESC 0x70000011 ++#define SHT_MIPS_EXTSYM 0x70000012 ++#define SHT_MIPS_DENSE 0x70000013 ++#define SHT_MIPS_PDESC 0x70000014 ++#define SHT_MIPS_LOCSYM 0x70000015 ++#define SHT_MIPS_AUXSYM 0x70000016 ++#define SHT_MIPS_OPTSYM 0x70000017 ++#define SHT_MIPS_LOCSTR 0x70000018 ++#define SHT_MIPS_LINE 0x70000019 ++#define SHT_MIPS_RFDESC 0x7000001a ++#define SHT_MIPS_DELTASYM 0x7000001b ++#define SHT_MIPS_DELTAINST 0x7000001c ++#define SHT_MIPS_DELTACLASS 0x7000001d ++#define SHT_MIPS_DWARF 0x7000001e /* DWARF debugging information. */ ++#define SHT_MIPS_DELTADECL 0x7000001f ++#define SHT_MIPS_SYMBOL_LIB 0x70000020 ++#define SHT_MIPS_EVENTS 0x70000021 /* Event section. */ ++#define SHT_MIPS_TRANSLATE 0x70000022 ++#define SHT_MIPS_PIXIE 0x70000023 ++#define SHT_MIPS_XLATE 0x70000024 ++#define SHT_MIPS_XLATE_DEBUG 0x70000025 ++#define SHT_MIPS_WHIRL 0x70000026 ++#define SHT_MIPS_EH_REGION 0x70000027 ++#define SHT_MIPS_XLATE_OLD 0x70000028 ++#define SHT_MIPS_PDR_EXCEPTION 0x70000029 ++ ++/* Legal values for sh_flags field of Elf32_Shdr. */ ++ ++#define SHF_MIPS_GPREL 0x10000000 /* Must be part of global data area */ ++#define SHF_MIPS_MERGE 0x20000000 ++#define SHF_MIPS_ADDR 0x40000000 ++#define SHF_MIPS_STRINGS 0x80000000 ++#define SHF_MIPS_NOSTRIP 0x08000000 ++#define SHF_MIPS_LOCAL 0x04000000 ++#define SHF_MIPS_NAMES 0x02000000 ++#define SHF_MIPS_NODUPE 0x01000000 ++ ++ ++/* Symbol tables. */ ++ ++/* MIPS specific values for `st_other'. */ ++#define STO_MIPS_DEFAULT 0x0 ++#define STO_MIPS_INTERNAL 0x1 ++#define STO_MIPS_HIDDEN 0x2 ++#define STO_MIPS_PROTECTED 0x3 ++#define STO_MIPS_SC_ALIGN_UNUSED 0xff ++ ++/* MIPS specific values for `st_info'. */ ++#define STB_MIPS_SPLIT_COMMON 13 ++ ++/* Entries found in sections of type SHT_MIPS_GPTAB. */ ++ ++typedef union ++{ ++ struct ++ { ++ Elf32_Word gt_current_g_value; /* -G value used for compilation */ ++ Elf32_Word gt_unused; /* Not used */ ++ } gt_header; /* First entry in section */ ++ struct ++ { ++ Elf32_Word gt_g_value; /* If this value were used for -G */ ++ Elf32_Word gt_bytes; /* This many bytes would be used */ ++ } gt_entry; /* Subsequent entries in section */ ++} Elf32_gptab; ++ ++/* Entry found in sections of type SHT_MIPS_REGINFO. */ ++ ++typedef struct ++{ ++ Elf32_Word ri_gprmask; /* General registers used */ ++ Elf32_Word ri_cprmask[4]; /* Coprocessor registers used */ ++ Elf32_Sword ri_gp_value; /* $gp register value */ ++} Elf32_RegInfo; ++ ++/* Entries found in sections of type SHT_MIPS_OPTIONS. */ ++ ++typedef struct ++{ ++ unsigned char kind; /* Determines interpretation of the ++ variable part of descriptor. */ ++ unsigned char size; /* Size of descriptor, including header. */ ++ Elf32_Section section; /* Section header index of section affected, ++ 0 for global options. */ ++ Elf32_Word info; /* Kind-specific information. */ ++} Elf_Options; ++ ++/* Values for `kind' field in Elf_Options. */ ++ ++#define ODK_NULL 0 /* Undefined. */ ++#define ODK_REGINFO 1 /* Register usage information. */ ++#define ODK_EXCEPTIONS 2 /* Exception processing options. */ ++#define ODK_PAD 3 /* Section padding options. */ ++#define ODK_HWPATCH 4 /* Hardware workarounds performed */ ++#define ODK_FILL 5 /* record the fill value used by the linker. */ ++#define ODK_TAGS 6 /* reserve space for desktop tools to write. */ ++#define ODK_HWAND 7 /* HW workarounds. 'AND' bits when merging. */ ++#define ODK_HWOR 8 /* HW workarounds. 'OR' bits when merging. */ ++ ++/* Values for `info' in Elf_Options for ODK_EXCEPTIONS entries. */ ++ ++#define OEX_FPU_MIN 0x1f /* FPE's which MUST be enabled. */ ++#define OEX_FPU_MAX 0x1f00 /* FPE's which MAY be enabled. */ ++#define OEX_PAGE0 0x10000 /* page zero must be mapped. */ ++#define OEX_SMM 0x20000 /* Force sequential memory mode? */ ++#define OEX_FPDBUG 0x40000 /* Force floating point debug mode? */ ++#define OEX_PRECISEFP OEX_FPDBUG ++#define OEX_DISMISS 0x80000 /* Dismiss invalid address faults? */ ++ ++#define OEX_FPU_INVAL 0x10 ++#define OEX_FPU_DIV0 0x08 ++#define OEX_FPU_OFLO 0x04 ++#define OEX_FPU_UFLO 0x02 ++#define OEX_FPU_INEX 0x01 ++ ++/* Masks for `info' in Elf_Options for an ODK_HWPATCH entry. */ ++ ++#define OHW_R4KEOP 0x1 /* R4000 end-of-page patch. */ ++#define OHW_R8KPFETCH 0x2 /* may need R8000 prefetch patch. */ ++#define OHW_R5KEOP 0x4 /* R5000 end-of-page patch. */ ++#define OHW_R5KCVTL 0x8 /* R5000 cvt.[ds].l bug. clean=1. */ ++ ++#define OPAD_PREFIX 0x1 ++#define OPAD_POSTFIX 0x2 ++#define OPAD_SYMBOL 0x4 ++ ++/* Entry found in `.options' section. */ ++ ++typedef struct ++{ ++ Elf32_Word hwp_flags1; /* Extra flags. */ ++ Elf32_Word hwp_flags2; /* Extra flags. */ ++} Elf_Options_Hw; ++ ++/* Masks for `info' in ElfOptions for ODK_HWAND and ODK_HWOR entries. */ ++ ++#define OHWA0_R4KEOP_CHECKED 0x00000001 ++#define OHWA1_R4KEOP_CLEAN 0x00000002 ++ ++/* MIPS relocs. */ ++ ++#define R_MIPS_NONE 0 /* No reloc */ ++#define R_MIPS_16 1 /* Direct 16 bit */ ++#define R_MIPS_32 2 /* Direct 32 bit */ ++#define R_MIPS_REL32 3 /* PC relative 32 bit */ ++#define R_MIPS_26 4 /* Direct 26 bit shifted */ ++#define R_MIPS_HI16 5 /* High 16 bit */ ++#define R_MIPS_LO16 6 /* Low 16 bit */ ++#define R_MIPS_GPREL16 7 /* GP relative 16 bit */ ++#define R_MIPS_LITERAL 8 /* 16 bit literal entry */ ++#define R_MIPS_GOT16 9 /* 16 bit GOT entry */ ++#define R_MIPS_PC16 10 /* PC relative 16 bit */ ++#define R_MIPS_CALL16 11 /* 16 bit GOT entry for function */ ++#define R_MIPS_GPREL32 12 /* GP relative 32 bit */ ++ ++#define R_MIPS_SHIFT5 16 ++#define R_MIPS_SHIFT6 17 ++#define R_MIPS_64 18 ++#define R_MIPS_GOT_DISP 19 ++#define R_MIPS_GOT_PAGE 20 ++#define R_MIPS_GOT_OFST 21 ++#define R_MIPS_GOT_HI16 22 ++#define R_MIPS_GOT_LO16 23 ++#define R_MIPS_SUB 24 ++#define R_MIPS_INSERT_A 25 ++#define R_MIPS_INSERT_B 26 ++#define R_MIPS_DELETE 27 ++#define R_MIPS_HIGHER 28 ++#define R_MIPS_HIGHEST 29 ++#define R_MIPS_CALL_HI16 30 ++#define R_MIPS_CALL_LO16 31 ++#define R_MIPS_SCN_DISP 32 ++#define R_MIPS_REL16 33 ++#define R_MIPS_ADD_IMMEDIATE 34 ++#define R_MIPS_PJUMP 35 ++#define R_MIPS_RELGOT 36 ++#define R_MIPS_JALR 37 ++/* Keep this the last entry. */ ++#define R_MIPS_NUM 38 ++ ++/* Legal values for p_type field of Elf32_Phdr. */ ++ ++#define PT_MIPS_REGINFO 0x70000000 /* Register usage information */ ++#define PT_MIPS_RTPROC 0x70000001 /* Runtime procedure table. */ ++#define PT_MIPS_OPTIONS 0x70000002 ++ ++/* Special program header types. */ ++ ++#define PF_MIPS_LOCAL 0x10000000 ++ ++/* Legal values for d_tag field of Elf32_Dyn. */ ++ ++#define DT_MIPS_RLD_VERSION 0x70000001 /* Runtime linker interface version */ ++#define DT_MIPS_TIME_STAMP 0x70000002 /* Timestamp */ ++#define DT_MIPS_ICHECKSUM 0x70000003 /* Checksum */ ++#define DT_MIPS_IVERSION 0x70000004 /* Version string (string tbl index) */ ++#define DT_MIPS_FLAGS 0x70000005 /* Flags */ ++#define DT_MIPS_BASE_ADDRESS 0x70000006 /* Base address */ ++#define DT_MIPS_MSYM 0x70000007 ++#define DT_MIPS_CONFLICT 0x70000008 /* Address of CONFLICT section */ ++#define DT_MIPS_LIBLIST 0x70000009 /* Address of LIBLIST section */ ++#define DT_MIPS_LOCAL_GOTNO 0x7000000a /* Number of local GOT entries */ ++#define DT_MIPS_CONFLICTNO 0x7000000b /* Number of CONFLICT entries */ ++#define DT_MIPS_LIBLISTNO 0x70000010 /* Number of LIBLIST entries */ ++#define DT_MIPS_SYMTABNO 0x70000011 /* Number of DYNSYM entries */ ++#define DT_MIPS_UNREFEXTNO 0x70000012 /* First external DYNSYM */ ++#define DT_MIPS_GOTSYM 0x70000013 /* First GOT entry in DYNSYM */ ++#define DT_MIPS_HIPAGENO 0x70000014 /* Number of GOT page table entries */ ++#define DT_MIPS_RLD_MAP 0x70000016 /* Address of run time loader map. */ ++#define DT_MIPS_DELTA_CLASS 0x70000017 /* Delta C++ class definition. */ ++#define DT_MIPS_DELTA_CLASS_NO 0x70000018 /* Number of entries in ++ DT_MIPS_DELTA_CLASS. */ ++#define DT_MIPS_DELTA_INSTANCE 0x70000019 /* Delta C++ class instances. */ ++#define DT_MIPS_DELTA_INSTANCE_NO 0x7000001a /* Number of entries in ++ DT_MIPS_DELTA_INSTANCE. */ ++#define DT_MIPS_DELTA_RELOC 0x7000001b /* Delta relocations. */ ++#define DT_MIPS_DELTA_RELOC_NO 0x7000001c /* Number of entries in ++ DT_MIPS_DELTA_RELOC. */ ++#define DT_MIPS_DELTA_SYM 0x7000001d /* Delta symbols that Delta ++ relocations refer to. */ ++#define DT_MIPS_DELTA_SYM_NO 0x7000001e /* Number of entries in ++ DT_MIPS_DELTA_SYM. */ ++#define DT_MIPS_DELTA_CLASSSYM 0x70000020 /* Delta symbols that hold the ++ class declaration. */ ++#define DT_MIPS_DELTA_CLASSSYM_NO 0x70000021 /* Number of entries in ++ DT_MIPS_DELTA_CLASSSYM. */ ++#define DT_MIPS_CXX_FLAGS 0x70000022 /* Flags indicating for C++ flavor. */ ++#define DT_MIPS_PIXIE_INIT 0x70000023 ++#define DT_MIPS_SYMBOL_LIB 0x70000024 ++#define DT_MIPS_LOCALPAGE_GOTIDX 0x70000025 ++#define DT_MIPS_LOCAL_GOTIDX 0x70000026 ++#define DT_MIPS_HIDDEN_GOTIDX 0x70000027 ++#define DT_MIPS_PROTECTED_GOTIDX 0x70000028 ++#define DT_MIPS_OPTIONS 0x70000029 /* Address of .options. */ ++#define DT_MIPS_INTERFACE 0x7000002a /* Address of .interface. */ ++#define DT_MIPS_DYNSTR_ALIGN 0x7000002b ++#define DT_MIPS_INTERFACE_SIZE 0x7000002c /* Size of the .interface section. */ ++#define DT_MIPS_RLD_TEXT_RESOLVE_ADDR 0x7000002d /* Address of rld_text_rsolve ++ function stored in GOT. */ ++#define DT_MIPS_PERF_SUFFIX 0x7000002e /* Default suffix of dso to be added ++ by rld on dlopen() calls. */ ++#define DT_MIPS_COMPACT_SIZE 0x7000002f /* (O32)Size of compact rel section. */ ++#define DT_MIPS_GP_VALUE 0x70000030 /* GP value for aux GOTs. */ ++#define DT_MIPS_AUX_DYNAMIC 0x70000031 /* Address of aux .dynamic. */ ++#define DT_MIPS_NUM 0x32 ++ ++/* Legal values for DT_MIPS_FLAGS Elf32_Dyn entry. */ ++ ++#define RHF_NONE 0 /* No flags */ ++#define RHF_QUICKSTART (1 << 0) /* Use quickstart */ ++#define RHF_NOTPOT (1 << 1) /* Hash size not power of 2 */ ++#define RHF_NO_LIBRARY_REPLACEMENT (1 << 2) /* Ignore LD_LIBRARY_PATH */ ++#define RHF_NO_MOVE (1 << 3) ++#define RHF_SGI_ONLY (1 << 4) ++#define RHF_GUARANTEE_INIT (1 << 5) ++#define RHF_DELTA_C_PLUS_PLUS (1 << 6) ++#define RHF_GUARANTEE_START_INIT (1 << 7) ++#define RHF_PIXIE (1 << 8) ++#define RHF_DEFAULT_DELAY_LOAD (1 << 9) ++#define RHF_REQUICKSTART (1 << 10) ++#define RHF_REQUICKSTARTED (1 << 11) ++#define RHF_CORD (1 << 12) ++#define RHF_NO_UNRES_UNDEF (1 << 13) ++#define RHF_RLD_ORDER_SAFE (1 << 14) ++ ++/* Entries found in sections of type SHT_MIPS_LIBLIST. */ ++ ++typedef struct ++{ ++ Elf32_Word l_name; /* Name (string table index) */ ++ Elf32_Word l_time_stamp; /* Timestamp */ ++ Elf32_Word l_checksum; /* Checksum */ ++ Elf32_Word l_version; /* Interface version */ ++ Elf32_Word l_flags; /* Flags */ ++} Elf32_Lib; ++ ++typedef struct ++{ ++ Elf64_Word l_name; /* Name (string table index) */ ++ Elf64_Word l_time_stamp; /* Timestamp */ ++ Elf64_Word l_checksum; /* Checksum */ ++ Elf64_Word l_version; /* Interface version */ ++ Elf64_Word l_flags; /* Flags */ ++} Elf64_Lib; ++ ++ ++/* Legal values for l_flags. */ ++ ++#define LL_NONE 0 ++#define LL_EXACT_MATCH (1 << 0) /* Require exact match */ ++#define LL_IGNORE_INT_VER (1 << 1) /* Ignore interface version */ ++#define LL_REQUIRE_MINOR (1 << 2) ++#define LL_EXPORTS (1 << 3) ++#define LL_DELAY_LOAD (1 << 4) ++#define LL_DELTA (1 << 5) ++ ++/* Entries found in sections of type SHT_MIPS_CONFLICT. */ ++ ++typedef Elf32_Addr Elf32_Conflict; ++ ++ ++/* HPPA specific definitions. */ ++ ++/* Legal values for e_flags field of Elf32_Ehdr. */ ++ ++#define EF_PARISC_TRAPNIL 0x00010000 /* Trap nil pointer dereference. */ ++#define EF_PARISC_EXT 0x00020000 /* Program uses arch. extensions. */ ++#define EF_PARISC_LSB 0x00040000 /* Program expects little endian. */ ++#define EF_PARISC_WIDE 0x00080000 /* Program expects wide mode. */ ++#define EF_PARISC_NO_KABP 0x00100000 /* No kernel assisted branch ++ prediction. */ ++#define EF_PARISC_LAZYSWAP 0x00400000 /* Allow lazy swapping. */ ++#define EF_PARISC_ARCH 0x0000ffff /* Architecture version. */ ++ ++/* Defined values for `e_flags & EF_PARISC_ARCH' are: */ ++ ++#define EFA_PARISC_1_0 0x020b /* PA-RISC 1.0 big-endian. */ ++#define EFA_PARISC_1_1 0x0210 /* PA-RISC 1.1 big-endian. */ ++#define EFA_PARISC_2_0 0x0214 /* PA-RISC 2.0 big-endian. */ ++ ++/* Additional section indeces. */ ++ ++#define SHN_PARISC_ANSI_COMMON 0xff00 /* Section for tenatively declared ++ symbols in ANSI C. */ ++#define SHN_PARISC_HUGE_COMMON 0xff01 /* Common blocks in huge model. */ ++ ++/* Legal values for sh_type field of Elf32_Shdr. */ ++ ++#define SHT_PARISC_EXT 0x70000000 /* Contains product specific ext. */ ++#define SHT_PARISC_UNWIND 0x70000001 /* Unwind information. */ ++#define SHT_PARISC_DOC 0x70000002 /* Debug info for optimized code. */ ++ ++/* Legal values for sh_flags field of Elf32_Shdr. */ ++ ++#define SHF_PARISC_SHORT 0x20000000 /* Section with short addressing. */ ++#define SHF_PARISC_HUGE 0x40000000 /* Section far from gp. */ ++#define SHF_PARISC_SBP 0x80000000 /* Static branch prediction code. */ ++ ++/* Legal values for ST_TYPE subfield of st_info (symbol type). */ ++ ++#define STT_PARISC_MILLICODE 13 /* Millicode function entry point. */ ++ ++#define STT_HP_OPAQUE (STT_LOOS + 0x1) ++#define STT_HP_STUB (STT_LOOS + 0x2) ++ ++/* HPPA relocs. */ ++ ++#define R_PARISC_NONE 0 /* No reloc. */ ++#define R_PARISC_DIR32 1 /* Direct 32-bit reference. */ ++#define R_PARISC_DIR21L 2 /* Left 21 bits of eff. address. */ ++#define R_PARISC_DIR17R 3 /* Right 17 bits of eff. address. */ ++#define R_PARISC_DIR17F 4 /* 17 bits of eff. address. */ ++#define R_PARISC_DIR14R 6 /* Right 14 bits of eff. address. */ ++#define R_PARISC_PCREL32 9 /* 32-bit rel. address. */ ++#define R_PARISC_PCREL21L 10 /* Left 21 bits of rel. address. */ ++#define R_PARISC_PCREL17R 11 /* Right 17 bits of rel. address. */ ++#define R_PARISC_PCREL17F 12 /* 17 bits of rel. address. */ ++#define R_PARISC_PCREL14R 14 /* Right 14 bits of rel. address. */ ++#define R_PARISC_DPREL21L 18 /* Left 21 bits of rel. address. */ ++#define R_PARISC_DPREL14R 22 /* Right 14 bits of rel. address. */ ++#define R_PARISC_GPREL21L 26 /* GP-relative, left 21 bits. */ ++#define R_PARISC_GPREL14R 30 /* GP-relative, right 14 bits. */ ++#define R_PARISC_LTOFF21L 34 /* LT-relative, left 21 bits. */ ++#define R_PARISC_LTOFF14R 38 /* LT-relative, right 14 bits. */ ++#define R_PARISC_SECREL32 41 /* 32 bits section rel. address. */ ++#define R_PARISC_SEGBASE 48 /* No relocation, set segment base. */ ++#define R_PARISC_SEGREL32 49 /* 32 bits segment rel. address. */ ++#define R_PARISC_PLTOFF21L 50 /* PLT rel. address, left 21 bits. */ ++#define R_PARISC_PLTOFF14R 54 /* PLT rel. address, right 14 bits. */ ++#define R_PARISC_LTOFF_FPTR32 57 /* 32 bits LT-rel. function pointer. */ ++#define R_PARISC_LTOFF_FPTR21L 58 /* LT-rel. fct ptr, left 21 bits. */ ++#define R_PARISC_LTOFF_FPTR14R 62 /* LT-rel. fct ptr, right 14 bits. */ ++#define R_PARISC_FPTR64 64 /* 64 bits function address. */ ++#define R_PARISC_PLABEL32 65 /* 32 bits function address. */ ++#define R_PARISC_PCREL64 72 /* 64 bits PC-rel. address. */ ++#define R_PARISC_PCREL22F 74 /* 22 bits PC-rel. address. */ ++#define R_PARISC_PCREL14WR 75 /* PC-rel. address, right 14 bits. */ ++#define R_PARISC_PCREL14DR 76 /* PC rel. address, right 14 bits. */ ++#define R_PARISC_PCREL16F 77 /* 16 bits PC-rel. address. */ ++#define R_PARISC_PCREL16WF 78 /* 16 bits PC-rel. address. */ ++#define R_PARISC_PCREL16DF 79 /* 16 bits PC-rel. address. */ ++#define R_PARISC_DIR64 80 /* 64 bits of eff. address. */ ++#define R_PARISC_DIR14WR 83 /* 14 bits of eff. address. */ ++#define R_PARISC_DIR14DR 84 /* 14 bits of eff. address. */ ++#define R_PARISC_DIR16F 85 /* 16 bits of eff. address. */ ++#define R_PARISC_DIR16WF 86 /* 16 bits of eff. address. */ ++#define R_PARISC_DIR16DF 87 /* 16 bits of eff. address. */ ++#define R_PARISC_GPREL64 88 /* 64 bits of GP-rel. address. */ ++#define R_PARISC_GPREL14WR 91 /* GP-rel. address, right 14 bits. */ ++#define R_PARISC_GPREL14DR 92 /* GP-rel. address, right 14 bits. */ ++#define R_PARISC_GPREL16F 93 /* 16 bits GP-rel. address. */ ++#define R_PARISC_GPREL16WF 94 /* 16 bits GP-rel. address. */ ++#define R_PARISC_GPREL16DF 95 /* 16 bits GP-rel. address. */ ++#define R_PARISC_LTOFF64 96 /* 64 bits LT-rel. address. */ ++#define R_PARISC_LTOFF14WR 99 /* LT-rel. address, right 14 bits. */ ++#define R_PARISC_LTOFF14DR 100 /* LT-rel. address, right 14 bits. */ ++#define R_PARISC_LTOFF16F 101 /* 16 bits LT-rel. address. */ ++#define R_PARISC_LTOFF16WF 102 /* 16 bits LT-rel. address. */ ++#define R_PARISC_LTOFF16DF 103 /* 16 bits LT-rel. address. */ ++#define R_PARISC_SECREL64 104 /* 64 bits section rel. address. */ ++#define R_PARISC_SEGREL64 112 /* 64 bits segment rel. address. */ ++#define R_PARISC_PLTOFF14WR 115 /* PLT-rel. address, right 14 bits. */ ++#define R_PARISC_PLTOFF14DR 116 /* PLT-rel. address, right 14 bits. */ ++#define R_PARISC_PLTOFF16F 117 /* 16 bits LT-rel. address. */ ++#define R_PARISC_PLTOFF16WF 118 /* 16 bits PLT-rel. address. */ ++#define R_PARISC_PLTOFF16DF 119 /* 16 bits PLT-rel. address. */ ++#define R_PARISC_LTOFF_FPTR64 120 /* 64 bits LT-rel. function ptr. */ ++#define R_PARISC_LTOFF_FPTR14WR 123 /* LT-rel. fct. ptr., right 14 bits. */ ++#define R_PARISC_LTOFF_FPTR14DR 124 /* LT-rel. fct. ptr., right 14 bits. */ ++#define R_PARISC_LTOFF_FPTR16F 125 /* 16 bits LT-rel. function ptr. */ ++#define R_PARISC_LTOFF_FPTR16WF 126 /* 16 bits LT-rel. function ptr. */ ++#define R_PARISC_LTOFF_FPTR16DF 127 /* 16 bits LT-rel. function ptr. */ ++#define R_PARISC_LORESERVE 128 ++#define R_PARISC_COPY 128 /* Copy relocation. */ ++#define R_PARISC_IPLT 129 /* Dynamic reloc, imported PLT */ ++#define R_PARISC_EPLT 130 /* Dynamic reloc, exported PLT */ ++#define R_PARISC_TPREL32 153 /* 32 bits TP-rel. address. */ ++#define R_PARISC_TPREL21L 154 /* TP-rel. address, left 21 bits. */ ++#define R_PARISC_TPREL14R 158 /* TP-rel. address, right 14 bits. */ ++#define R_PARISC_LTOFF_TP21L 162 /* LT-TP-rel. address, left 21 bits. */ ++#define R_PARISC_LTOFF_TP14R 166 /* LT-TP-rel. address, right 14 bits.*/ ++#define R_PARISC_LTOFF_TP14F 167 /* 14 bits LT-TP-rel. address. */ ++#define R_PARISC_TPREL64 216 /* 64 bits TP-rel. address. */ ++#define R_PARISC_TPREL14WR 219 /* TP-rel. address, right 14 bits. */ ++#define R_PARISC_TPREL14DR 220 /* TP-rel. address, right 14 bits. */ ++#define R_PARISC_TPREL16F 221 /* 16 bits TP-rel. address. */ ++#define R_PARISC_TPREL16WF 222 /* 16 bits TP-rel. address. */ ++#define R_PARISC_TPREL16DF 223 /* 16 bits TP-rel. address. */ ++#define R_PARISC_LTOFF_TP64 224 /* 64 bits LT-TP-rel. address. */ ++#define R_PARISC_LTOFF_TP14WR 227 /* LT-TP-rel. address, right 14 bits.*/ ++#define R_PARISC_LTOFF_TP14DR 228 /* LT-TP-rel. address, right 14 bits.*/ ++#define R_PARISC_LTOFF_TP16F 229 /* 16 bits LT-TP-rel. address. */ ++#define R_PARISC_LTOFF_TP16WF 230 /* 16 bits LT-TP-rel. address. */ ++#define R_PARISC_LTOFF_TP16DF 231 /* 16 bits LT-TP-rel. address. */ ++#define R_PARISC_HIRESERVE 255 ++ ++/* Legal values for p_type field of Elf32_Phdr/Elf64_Phdr. */ ++ ++#define PT_HP_TLS (PT_LOOS + 0x0) ++#define PT_HP_CORE_NONE (PT_LOOS + 0x1) ++#define PT_HP_CORE_VERSION (PT_LOOS + 0x2) ++#define PT_HP_CORE_KERNEL (PT_LOOS + 0x3) ++#define PT_HP_CORE_COMM (PT_LOOS + 0x4) ++#define PT_HP_CORE_PROC (PT_LOOS + 0x5) ++#define PT_HP_CORE_LOADABLE (PT_LOOS + 0x6) ++#define PT_HP_CORE_STACK (PT_LOOS + 0x7) ++#define PT_HP_CORE_SHM (PT_LOOS + 0x8) ++#define PT_HP_CORE_MMF (PT_LOOS + 0x9) ++#define PT_HP_PARALLEL (PT_LOOS + 0x10) ++#define PT_HP_FASTBIND (PT_LOOS + 0x11) ++#define PT_HP_OPT_ANNOT (PT_LOOS + 0x12) ++#define PT_HP_HSL_ANNOT (PT_LOOS + 0x13) ++#define PT_HP_STACK (PT_LOOS + 0x14) ++ ++#define PT_PARISC_ARCHEXT 0x70000000 ++#define PT_PARISC_UNWIND 0x70000001 ++ ++/* Legal values for p_flags field of Elf32_Phdr/Elf64_Phdr. */ ++ ++#define PF_PARISC_SBP 0x08000000 ++ ++#define PF_HP_PAGE_SIZE 0x00100000 ++#define PF_HP_FAR_SHARED 0x00200000 ++#define PF_HP_NEAR_SHARED 0x00400000 ++#define PF_HP_CODE 0x01000000 ++#define PF_HP_MODIFY 0x02000000 ++#define PF_HP_LAZYSWAP 0x04000000 ++#define PF_HP_SBP 0x08000000 ++ ++ ++/* Alpha specific definitions. */ ++ ++/* Legal values for e_flags field of Elf64_Ehdr. */ ++ ++#define EF_ALPHA_32BIT 1 /* All addresses must be < 2GB. */ ++#define EF_ALPHA_CANRELAX 2 /* Relocations for relaxing exist. */ ++ ++/* Legal values for sh_type field of Elf64_Shdr. */ ++ ++/* These two are primerily concerned with ECOFF debugging info. */ ++#define SHT_ALPHA_DEBUG 0x70000001 ++#define SHT_ALPHA_REGINFO 0x70000002 ++ ++/* Legal values for sh_flags field of Elf64_Shdr. */ ++ ++#define SHF_ALPHA_GPREL 0x10000000 ++ ++/* Legal values for st_other field of Elf64_Sym. */ ++#define STO_ALPHA_NOPV 0x80 /* No PV required. */ ++#define STO_ALPHA_STD_GPLOAD 0x88 /* PV only used for initial ldgp. */ ++ ++/* Alpha relocs. */ ++ ++#define R_ALPHA_NONE 0 /* No reloc */ ++#define R_ALPHA_REFLONG 1 /* Direct 32 bit */ ++#define R_ALPHA_REFQUAD 2 /* Direct 64 bit */ ++#define R_ALPHA_GPREL32 3 /* GP relative 32 bit */ ++#define R_ALPHA_LITERAL 4 /* GP relative 16 bit w/optimization */ ++#define R_ALPHA_LITUSE 5 /* Optimization hint for LITERAL */ ++#define R_ALPHA_GPDISP 6 /* Add displacement to GP */ ++#define R_ALPHA_BRADDR 7 /* PC+4 relative 23 bit shifted */ ++#define R_ALPHA_HINT 8 /* PC+4 relative 16 bit shifted */ ++#define R_ALPHA_SREL16 9 /* PC relative 16 bit */ ++#define R_ALPHA_SREL32 10 /* PC relative 32 bit */ ++#define R_ALPHA_SREL64 11 /* PC relative 64 bit */ ++#define R_ALPHA_GPRELHIGH 17 /* GP relative 32 bit, high 16 bits */ ++#define R_ALPHA_GPRELLOW 18 /* GP relative 32 bit, low 16 bits */ ++#define R_ALPHA_GPREL16 19 /* GP relative 16 bit */ ++#define R_ALPHA_COPY 24 /* Copy symbol at runtime */ ++#define R_ALPHA_GLOB_DAT 25 /* Create GOT entry */ ++#define R_ALPHA_JMP_SLOT 26 /* Create PLT entry */ ++#define R_ALPHA_RELATIVE 27 /* Adjust by program base */ ++#define R_ALPHA_TLS_GD_HI 28 ++#define R_ALPHA_TLSGD 29 ++#define R_ALPHA_TLS_LDM 30 ++#define R_ALPHA_DTPMOD64 31 ++#define R_ALPHA_GOTDTPREL 32 ++#define R_ALPHA_DTPREL64 33 ++#define R_ALPHA_DTPRELHI 34 ++#define R_ALPHA_DTPRELLO 35 ++#define R_ALPHA_DTPREL16 36 ++#define R_ALPHA_GOTTPREL 37 ++#define R_ALPHA_TPREL64 38 ++#define R_ALPHA_TPRELHI 39 ++#define R_ALPHA_TPRELLO 40 ++#define R_ALPHA_TPREL16 41 ++/* Keep this the last entry. */ ++#define R_ALPHA_NUM 46 ++ ++/* Magic values of the LITUSE relocation addend. */ ++#define LITUSE_ALPHA_ADDR 0 ++#define LITUSE_ALPHA_BASE 1 ++#define LITUSE_ALPHA_BYTOFF 2 ++#define LITUSE_ALPHA_JSR 3 ++#define LITUSE_ALPHA_TLS_GD 4 ++#define LITUSE_ALPHA_TLS_LDM 5 ++ ++ ++/* PowerPC specific declarations */ ++ ++/* Values for Elf32/64_Ehdr.e_flags. */ ++#define EF_PPC_EMB 0x80000000 /* PowerPC embedded flag */ ++ ++/* Cygnus local bits below */ ++#define EF_PPC_RELOCATABLE 0x00010000 /* PowerPC -mrelocatable flag*/ ++#define EF_PPC_RELOCATABLE_LIB 0x00008000 /* PowerPC -mrelocatable-lib ++ flag */ ++ ++/* PowerPC relocations defined by the ABIs */ ++#define R_PPC_NONE 0 ++#define R_PPC_ADDR32 1 /* 32bit absolute address */ ++#define R_PPC_ADDR24 2 /* 26bit address, 2 bits ignored. */ ++#define R_PPC_ADDR16 3 /* 16bit absolute address */ ++#define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */ ++#define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */ ++#define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */ ++#define R_PPC_ADDR14 7 /* 16bit address, 2 bits ignored */ ++#define R_PPC_ADDR14_BRTAKEN 8 ++#define R_PPC_ADDR14_BRNTAKEN 9 ++#define R_PPC_REL24 10 /* PC relative 26 bit */ ++#define R_PPC_REL14 11 /* PC relative 16 bit */ ++#define R_PPC_REL14_BRTAKEN 12 ++#define R_PPC_REL14_BRNTAKEN 13 ++#define R_PPC_GOT16 14 ++#define R_PPC_GOT16_LO 15 ++#define R_PPC_GOT16_HI 16 ++#define R_PPC_GOT16_HA 17 ++#define R_PPC_PLTREL24 18 ++#define R_PPC_COPY 19 ++#define R_PPC_GLOB_DAT 20 ++#define R_PPC_JMP_SLOT 21 ++#define R_PPC_RELATIVE 22 ++#define R_PPC_LOCAL24PC 23 ++#define R_PPC_UADDR32 24 ++#define R_PPC_UADDR16 25 ++#define R_PPC_REL32 26 ++#define R_PPC_PLT32 27 ++#define R_PPC_PLTREL32 28 ++#define R_PPC_PLT16_LO 29 ++#define R_PPC_PLT16_HI 30 ++#define R_PPC_PLT16_HA 31 ++#define R_PPC_SDAREL16 32 ++#define R_PPC_SECTOFF 33 ++#define R_PPC_SECTOFF_LO 34 ++#define R_PPC_SECTOFF_HI 35 ++#define R_PPC_SECTOFF_HA 36 ++ ++/* PowerPC relocations defined for the TLS access ABI. */ ++#define R_PPC_TLS 67 /* none (sym+add)@tls */ ++#define R_PPC_DTPMOD32 68 /* word32 (sym+add)@dtpmod */ ++#define R_PPC_TPREL16 69 /* half16* (sym+add)@tprel */ ++#define R_PPC_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */ ++#define R_PPC_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */ ++#define R_PPC_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */ ++#define R_PPC_TPREL32 73 /* word32 (sym+add)@tprel */ ++#define R_PPC_DTPREL16 74 /* half16* (sym+add)@dtprel */ ++#define R_PPC_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */ ++#define R_PPC_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */ ++#define R_PPC_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */ ++#define R_PPC_DTPREL32 78 /* word32 (sym+add)@dtprel */ ++#define R_PPC_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */ ++#define R_PPC_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */ ++#define R_PPC_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */ ++#define R_PPC_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */ ++#define R_PPC_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */ ++#define R_PPC_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */ ++#define R_PPC_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */ ++#define R_PPC_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */ ++#define R_PPC_GOT_TPREL16 87 /* half16* (sym+add)@got@tprel */ ++#define R_PPC_GOT_TPREL16_LO 88 /* half16 (sym+add)@got@tprel@l */ ++#define R_PPC_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */ ++#define R_PPC_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */ ++#define R_PPC_GOT_DTPREL16 91 /* half16* (sym+add)@got@dtprel */ ++#define R_PPC_GOT_DTPREL16_LO 92 /* half16* (sym+add)@got@dtprel@l */ ++#define R_PPC_GOT_DTPREL16_HI 93 /* half16* (sym+add)@got@dtprel@h */ ++#define R_PPC_GOT_DTPREL16_HA 94 /* half16* (sym+add)@got@dtprel@ha */ ++ ++/* Keep this the last entry. */ ++#define R_PPC_NUM 95 ++ ++/* The remaining relocs are from the Embedded ELF ABI, and are not ++ in the SVR4 ELF ABI. */ ++#define R_PPC_EMB_NADDR32 101 ++#define R_PPC_EMB_NADDR16 102 ++#define R_PPC_EMB_NADDR16_LO 103 ++#define R_PPC_EMB_NADDR16_HI 104 ++#define R_PPC_EMB_NADDR16_HA 105 ++#define R_PPC_EMB_SDAI16 106 ++#define R_PPC_EMB_SDA2I16 107 ++#define R_PPC_EMB_SDA2REL 108 ++#define R_PPC_EMB_SDA21 109 /* 16 bit offset in SDA */ ++#define R_PPC_EMB_MRKREF 110 ++#define R_PPC_EMB_RELSEC16 111 ++#define R_PPC_EMB_RELST_LO 112 ++#define R_PPC_EMB_RELST_HI 113 ++#define R_PPC_EMB_RELST_HA 114 ++#define R_PPC_EMB_BIT_FLD 115 ++#define R_PPC_EMB_RELSDA 116 /* 16 bit relative offset in SDA */ ++ ++/* Diab tool relocations. */ ++#define R_PPC_DIAB_SDA21_LO 180 /* like EMB_SDA21, but lower 16 bit */ ++#define R_PPC_DIAB_SDA21_HI 181 /* like EMB_SDA21, but high 16 bit */ ++#define R_PPC_DIAB_SDA21_HA 182 /* like EMB_SDA21, adjusted high 16 */ ++#define R_PPC_DIAB_RELSDA_LO 183 /* like EMB_RELSDA, but lower 16 bit */ ++#define R_PPC_DIAB_RELSDA_HI 184 /* like EMB_RELSDA, but high 16 bit */ ++#define R_PPC_DIAB_RELSDA_HA 185 /* like EMB_RELSDA, adjusted high 16 */ ++ ++/* This is a phony reloc to handle any old fashioned TOC16 references ++ that may still be in object files. */ ++#define R_PPC_TOC16 255 ++ ++ ++/* PowerPC64 relocations defined by the ABIs */ ++#define R_PPC64_NONE R_PPC_NONE ++#define R_PPC64_ADDR32 R_PPC_ADDR32 /* 32bit absolute address */ ++#define R_PPC64_ADDR24 R_PPC_ADDR24 /* 26bit address, word aligned */ ++#define R_PPC64_ADDR16 R_PPC_ADDR16 /* 16bit absolute address */ ++#define R_PPC64_ADDR16_LO R_PPC_ADDR16_LO /* lower 16bits of address */ ++#define R_PPC64_ADDR16_HI R_PPC_ADDR16_HI /* high 16bits of address. */ ++#define R_PPC64_ADDR16_HA R_PPC_ADDR16_HA /* adjusted high 16bits. */ ++#define R_PPC64_ADDR14 R_PPC_ADDR14 /* 16bit address, word aligned */ ++#define R_PPC64_ADDR14_BRTAKEN R_PPC_ADDR14_BRTAKEN ++#define R_PPC64_ADDR14_BRNTAKEN R_PPC_ADDR14_BRNTAKEN ++#define R_PPC64_REL24 R_PPC_REL24 /* PC-rel. 26 bit, word aligned */ ++#define R_PPC64_REL14 R_PPC_REL14 /* PC relative 16 bit */ ++#define R_PPC64_REL14_BRTAKEN R_PPC_REL14_BRTAKEN ++#define R_PPC64_REL14_BRNTAKEN R_PPC_REL14_BRNTAKEN ++#define R_PPC64_GOT16 R_PPC_GOT16 ++#define R_PPC64_GOT16_LO R_PPC_GOT16_LO ++#define R_PPC64_GOT16_HI R_PPC_GOT16_HI ++#define R_PPC64_GOT16_HA R_PPC_GOT16_HA ++ ++#define R_PPC64_COPY R_PPC_COPY ++#define R_PPC64_GLOB_DAT R_PPC_GLOB_DAT ++#define R_PPC64_JMP_SLOT R_PPC_JMP_SLOT ++#define R_PPC64_RELATIVE R_PPC_RELATIVE ++ ++#define R_PPC64_UADDR32 R_PPC_UADDR32 ++#define R_PPC64_UADDR16 R_PPC_UADDR16 ++#define R_PPC64_REL32 R_PPC_REL32 ++#define R_PPC64_PLT32 R_PPC_PLT32 ++#define R_PPC64_PLTREL32 R_PPC_PLTREL32 ++#define R_PPC64_PLT16_LO R_PPC_PLT16_LO ++#define R_PPC64_PLT16_HI R_PPC_PLT16_HI ++#define R_PPC64_PLT16_HA R_PPC_PLT16_HA ++ ++#define R_PPC64_SECTOFF R_PPC_SECTOFF ++#define R_PPC64_SECTOFF_LO R_PPC_SECTOFF_LO ++#define R_PPC64_SECTOFF_HI R_PPC_SECTOFF_HI ++#define R_PPC64_SECTOFF_HA R_PPC_SECTOFF_HA ++#define R_PPC64_ADDR30 37 /* word30 (S + A - P) >> 2 */ ++#define R_PPC64_ADDR64 38 /* doubleword64 S + A */ ++#define R_PPC64_ADDR16_HIGHER 39 /* half16 #higher(S + A) */ ++#define R_PPC64_ADDR16_HIGHERA 40 /* half16 #highera(S + A) */ ++#define R_PPC64_ADDR16_HIGHEST 41 /* half16 #highest(S + A) */ ++#define R_PPC64_ADDR16_HIGHESTA 42 /* half16 #highesta(S + A) */ ++#define R_PPC64_UADDR64 43 /* doubleword64 S + A */ ++#define R_PPC64_REL64 44 /* doubleword64 S + A - P */ ++#define R_PPC64_PLT64 45 /* doubleword64 L + A */ ++#define R_PPC64_PLTREL64 46 /* doubleword64 L + A - P */ ++#define R_PPC64_TOC16 47 /* half16* S + A - .TOC */ ++#define R_PPC64_TOC16_LO 48 /* half16 #lo(S + A - .TOC.) */ ++#define R_PPC64_TOC16_HI 49 /* half16 #hi(S + A - .TOC.) */ ++#define R_PPC64_TOC16_HA 50 /* half16 #ha(S + A - .TOC.) */ ++#define R_PPC64_TOC 51 /* doubleword64 .TOC */ ++#define R_PPC64_PLTGOT16 52 /* half16* M + A */ ++#define R_PPC64_PLTGOT16_LO 53 /* half16 #lo(M + A) */ ++#define R_PPC64_PLTGOT16_HI 54 /* half16 #hi(M + A) */ ++#define R_PPC64_PLTGOT16_HA 55 /* half16 #ha(M + A) */ ++ ++#define R_PPC64_ADDR16_DS 56 /* half16ds* (S + A) >> 2 */ ++#define R_PPC64_ADDR16_LO_DS 57 /* half16ds #lo(S + A) >> 2 */ ++#define R_PPC64_GOT16_DS 58 /* half16ds* (G + A) >> 2 */ ++#define R_PPC64_GOT16_LO_DS 59 /* half16ds #lo(G + A) >> 2 */ ++#define R_PPC64_PLT16_LO_DS 60 /* half16ds #lo(L + A) >> 2 */ ++#define R_PPC64_SECTOFF_DS 61 /* half16ds* (R + A) >> 2 */ ++#define R_PPC64_SECTOFF_LO_DS 62 /* half16ds #lo(R + A) >> 2 */ ++#define R_PPC64_TOC16_DS 63 /* half16ds* (S + A - .TOC.) >> 2 */ ++#define R_PPC64_TOC16_LO_DS 64 /* half16ds #lo(S + A - .TOC.) >> 2 */ ++#define R_PPC64_PLTGOT16_DS 65 /* half16ds* (M + A) >> 2 */ ++#define R_PPC64_PLTGOT16_LO_DS 66 /* half16ds #lo(M + A) >> 2 */ ++ ++/* PowerPC64 relocations defined for the TLS access ABI. */ ++#define R_PPC64_TLS 67 /* none (sym+add)@tls */ ++#define R_PPC64_DTPMOD64 68 /* doubleword64 (sym+add)@dtpmod */ ++#define R_PPC64_TPREL16 69 /* half16* (sym+add)@tprel */ ++#define R_PPC64_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */ ++#define R_PPC64_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */ ++#define R_PPC64_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */ ++#define R_PPC64_TPREL64 73 /* doubleword64 (sym+add)@tprel */ ++#define R_PPC64_DTPREL16 74 /* half16* (sym+add)@dtprel */ ++#define R_PPC64_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */ ++#define R_PPC64_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */ ++#define R_PPC64_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */ ++#define R_PPC64_DTPREL64 78 /* doubleword64 (sym+add)@dtprel */ ++#define R_PPC64_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */ ++#define R_PPC64_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */ ++#define R_PPC64_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */ ++#define R_PPC64_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */ ++#define R_PPC64_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */ ++#define R_PPC64_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */ ++#define R_PPC64_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */ ++#define R_PPC64_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */ ++#define R_PPC64_GOT_TPREL16_DS 87 /* half16ds* (sym+add)@got@tprel */ ++#define R_PPC64_GOT_TPREL16_LO_DS 88 /* half16ds (sym+add)@got@tprel@l */ ++#define R_PPC64_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */ ++#define R_PPC64_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */ ++#define R_PPC64_GOT_DTPREL16_DS 91 /* half16ds* (sym+add)@got@dtprel */ ++#define R_PPC64_GOT_DTPREL16_LO_DS 92 /* half16ds (sym+add)@got@dtprel@l */ ++#define R_PPC64_GOT_DTPREL16_HI 93 /* half16 (sym+add)@got@dtprel@h */ ++#define R_PPC64_GOT_DTPREL16_HA 94 /* half16 (sym+add)@got@dtprel@ha */ ++#define R_PPC64_TPREL16_DS 95 /* half16ds* (sym+add)@tprel */ ++#define R_PPC64_TPREL16_LO_DS 96 /* half16ds (sym+add)@tprel@l */ ++#define R_PPC64_TPREL16_HIGHER 97 /* half16 (sym+add)@tprel@higher */ ++#define R_PPC64_TPREL16_HIGHERA 98 /* half16 (sym+add)@tprel@highera */ ++#define R_PPC64_TPREL16_HIGHEST 99 /* half16 (sym+add)@tprel@highest */ ++#define R_PPC64_TPREL16_HIGHESTA 100 /* half16 (sym+add)@tprel@highesta */ ++#define R_PPC64_DTPREL16_DS 101 /* half16ds* (sym+add)@dtprel */ ++#define R_PPC64_DTPREL16_LO_DS 102 /* half16ds (sym+add)@dtprel@l */ ++#define R_PPC64_DTPREL16_HIGHER 103 /* half16 (sym+add)@dtprel@higher */ ++#define R_PPC64_DTPREL16_HIGHERA 104 /* half16 (sym+add)@dtprel@highera */ ++#define R_PPC64_DTPREL16_HIGHEST 105 /* half16 (sym+add)@dtprel@highest */ ++#define R_PPC64_DTPREL16_HIGHESTA 106 /* half16 (sym+add)@dtprel@highesta */ ++ ++/* Keep this the last entry. */ ++#define R_PPC64_NUM 107 ++ ++/* PowerPC64 specific values for the Dyn d_tag field. */ ++#define DT_PPC64_GLINK (DT_LOPROC + 0) ++#define DT_PPC64_NUM 1 ++ ++ ++/* ARM specific declarations */ ++ ++/* Processor specific flags for the ELF header e_flags field. */ ++#define EF_ARM_RELEXEC 0x01 ++#define EF_ARM_HASENTRY 0x02 ++#define EF_ARM_INTERWORK 0x04 ++#define EF_ARM_APCS_26 0x08 ++#define EF_ARM_APCS_FLOAT 0x10 ++#define EF_ARM_PIC 0x20 ++#define EF_ARM_ALIGN8 0x40 /* 8-bit structure alignment is in use */ ++#define EF_ARM_NEW_ABI 0x80 ++#define EF_ARM_OLD_ABI 0x100 ++ ++/* Other constants defined in the ARM ELF spec. version B-01. */ ++/* NB. These conflict with values defined above. */ ++#define EF_ARM_SYMSARESORTED 0x04 ++#define EF_ARM_DYNSYMSUSESEGIDX 0x08 ++#define EF_ARM_MAPSYMSFIRST 0x10 ++#define EF_ARM_EABIMASK 0XFF000000 ++ ++#define EF_ARM_EABI_VERSION(flags) ((flags) & EF_ARM_EABIMASK) ++#define EF_ARM_EABI_UNKNOWN 0x00000000 ++#define EF_ARM_EABI_VER1 0x01000000 ++#define EF_ARM_EABI_VER2 0x02000000 ++ ++/* Additional symbol types for Thumb */ ++#define STT_ARM_TFUNC 0xd ++ ++/* ARM-specific values for sh_flags */ ++#define SHF_ARM_ENTRYSECT 0x10000000 /* Section contains an entry point */ ++#define SHF_ARM_COMDEF 0x80000000 /* Section may be multiply defined ++ in the input to a link step */ ++ ++/* ARM-specific program header flags */ ++#define PF_ARM_SB 0x10000000 /* Segment contains the location ++ addressed by the static base */ ++ ++/* ARM relocs. */ ++#define R_ARM_NONE 0 /* No reloc */ ++#define R_ARM_PC24 1 /* PC relative 26 bit branch */ ++#define R_ARM_ABS32 2 /* Direct 32 bit */ ++#define R_ARM_REL32 3 /* PC relative 32 bit */ ++#define R_ARM_PC13 4 ++#define R_ARM_ABS16 5 /* Direct 16 bit */ ++#define R_ARM_ABS12 6 /* Direct 12 bit */ ++#define R_ARM_THM_ABS5 7 ++#define R_ARM_ABS8 8 /* Direct 8 bit */ ++#define R_ARM_SBREL32 9 ++#define R_ARM_THM_PC22 10 ++#define R_ARM_THM_PC8 11 ++#define R_ARM_AMP_VCALL9 12 ++#define R_ARM_SWI24 13 ++#define R_ARM_THM_SWI8 14 ++#define R_ARM_XPC25 15 ++#define R_ARM_THM_XPC22 16 ++#define R_ARM_COPY 20 /* Copy symbol at runtime */ ++#define R_ARM_GLOB_DAT 21 /* Create GOT entry */ ++#define R_ARM_JUMP_SLOT 22 /* Create PLT entry */ ++#define R_ARM_RELATIVE 23 /* Adjust by program base */ ++#define R_ARM_GOTOFF 24 /* 32 bit offset to GOT */ ++#define R_ARM_GOTPC 25 /* 32 bit PC relative offset to GOT */ ++#define R_ARM_GOT32 26 /* 32 bit GOT entry */ ++#define R_ARM_PLT32 27 /* 32 bit PLT address */ ++#define R_ARM_ALU_PCREL_7_0 32 ++#define R_ARM_ALU_PCREL_15_8 33 ++#define R_ARM_ALU_PCREL_23_15 34 ++#define R_ARM_LDR_SBREL_11_0 35 ++#define R_ARM_ALU_SBREL_19_12 36 ++#define R_ARM_ALU_SBREL_27_20 37 ++#define R_ARM_GNU_VTENTRY 100 ++#define R_ARM_GNU_VTINHERIT 101 ++#define R_ARM_THM_PC11 102 /* thumb unconditional branch */ ++#define R_ARM_THM_PC9 103 /* thumb conditional branch */ ++#define R_ARM_RXPC25 249 ++#define R_ARM_RSBREL32 250 ++#define R_ARM_THM_RPC22 251 ++#define R_ARM_RREL32 252 ++#define R_ARM_RABS22 253 ++#define R_ARM_RPC24 254 ++#define R_ARM_RBASE 255 ++/* Keep this the last entry. */ ++#define R_ARM_NUM 256 ++ ++/* IA-64 specific declarations. */ ++ ++/* Processor specific flags for the Ehdr e_flags field. */ ++#define EF_IA_64_MASKOS 0x0000000f /* os-specific flags */ ++#define EF_IA_64_ABI64 0x00000010 /* 64-bit ABI */ ++#define EF_IA_64_ARCH 0xff000000 /* arch. version mask */ ++ ++/* Processor specific values for the Phdr p_type field. */ ++#define PT_IA_64_ARCHEXT (PT_LOPROC + 0) /* arch extension bits */ ++#define PT_IA_64_UNWIND (PT_LOPROC + 1) /* ia64 unwind bits */ ++ ++/* Processor specific flags for the Phdr p_flags field. */ ++#define PF_IA_64_NORECOV 0x80000000 /* spec insns w/o recovery */ ++ ++/* Processor specific values for the Shdr sh_type field. */ ++#define SHT_IA_64_EXT (SHT_LOPROC + 0) /* extension bits */ ++#define SHT_IA_64_UNWIND (SHT_LOPROC + 1) /* unwind bits */ ++ ++/* Processor specific flags for the Shdr sh_flags field. */ ++#define SHF_IA_64_SHORT 0x10000000 /* section near gp */ ++#define SHF_IA_64_NORECOV 0x20000000 /* spec insns w/o recovery */ ++ ++/* Processor specific values for the Dyn d_tag field. */ ++#define DT_IA_64_PLT_RESERVE (DT_LOPROC + 0) ++#define DT_IA_64_NUM 1 ++ ++/* IA-64 relocations. */ ++#define R_IA64_NONE 0x00 /* none */ ++#define R_IA64_IMM14 0x21 /* symbol + addend, add imm14 */ ++#define R_IA64_IMM22 0x22 /* symbol + addend, add imm22 */ ++#define R_IA64_IMM64 0x23 /* symbol + addend, mov imm64 */ ++#define R_IA64_DIR32MSB 0x24 /* symbol + addend, data4 MSB */ ++#define R_IA64_DIR32LSB 0x25 /* symbol + addend, data4 LSB */ ++#define R_IA64_DIR64MSB 0x26 /* symbol + addend, data8 MSB */ ++#define R_IA64_DIR64LSB 0x27 /* symbol + addend, data8 LSB */ ++#define R_IA64_GPREL22 0x2a /* @gprel(sym + add), add imm22 */ ++#define R_IA64_GPREL64I 0x2b /* @gprel(sym + add), mov imm64 */ ++#define R_IA64_GPREL32MSB 0x2c /* @gprel(sym + add), data4 MSB */ ++#define R_IA64_GPREL32LSB 0x2d /* @gprel(sym + add), data4 LSB */ ++#define R_IA64_GPREL64MSB 0x2e /* @gprel(sym + add), data8 MSB */ ++#define R_IA64_GPREL64LSB 0x2f /* @gprel(sym + add), data8 LSB */ ++#define R_IA64_LTOFF22 0x32 /* @ltoff(sym + add), add imm22 */ ++#define R_IA64_LTOFF64I 0x33 /* @ltoff(sym + add), mov imm64 */ ++#define R_IA64_PLTOFF22 0x3a /* @pltoff(sym + add), add imm22 */ ++#define R_IA64_PLTOFF64I 0x3b /* @pltoff(sym + add), mov imm64 */ ++#define R_IA64_PLTOFF64MSB 0x3e /* @pltoff(sym + add), data8 MSB */ ++#define R_IA64_PLTOFF64LSB 0x3f /* @pltoff(sym + add), data8 LSB */ ++#define R_IA64_FPTR64I 0x43 /* @fptr(sym + add), mov imm64 */ ++#define R_IA64_FPTR32MSB 0x44 /* @fptr(sym + add), data4 MSB */ ++#define R_IA64_FPTR32LSB 0x45 /* @fptr(sym + add), data4 LSB */ ++#define R_IA64_FPTR64MSB 0x46 /* @fptr(sym + add), data8 MSB */ ++#define R_IA64_FPTR64LSB 0x47 /* @fptr(sym + add), data8 LSB */ ++#define R_IA64_PCREL60B 0x48 /* @pcrel(sym + add), brl */ ++#define R_IA64_PCREL21B 0x49 /* @pcrel(sym + add), ptb, call */ ++#define R_IA64_PCREL21M 0x4a /* @pcrel(sym + add), chk.s */ ++#define R_IA64_PCREL21F 0x4b /* @pcrel(sym + add), fchkf */ ++#define R_IA64_PCREL32MSB 0x4c /* @pcrel(sym + add), data4 MSB */ ++#define R_IA64_PCREL32LSB 0x4d /* @pcrel(sym + add), data4 LSB */ ++#define R_IA64_PCREL64MSB 0x4e /* @pcrel(sym + add), data8 MSB */ ++#define R_IA64_PCREL64LSB 0x4f /* @pcrel(sym + add), data8 LSB */ ++#define R_IA64_LTOFF_FPTR22 0x52 /* @ltoff(@fptr(s+a)), imm22 */ ++#define R_IA64_LTOFF_FPTR64I 0x53 /* @ltoff(@fptr(s+a)), imm64 */ ++#define R_IA64_LTOFF_FPTR32MSB 0x54 /* @ltoff(@fptr(s+a)), data4 MSB */ ++#define R_IA64_LTOFF_FPTR32LSB 0x55 /* @ltoff(@fptr(s+a)), data4 LSB */ ++#define R_IA64_LTOFF_FPTR64MSB 0x56 /* @ltoff(@fptr(s+a)), data8 MSB */ ++#define R_IA64_LTOFF_FPTR64LSB 0x57 /* @ltoff(@fptr(s+a)), data8 LSB */ ++#define R_IA64_SEGREL32MSB 0x5c /* @segrel(sym + add), data4 MSB */ ++#define R_IA64_SEGREL32LSB 0x5d /* @segrel(sym + add), data4 LSB */ ++#define R_IA64_SEGREL64MSB 0x5e /* @segrel(sym + add), data8 MSB */ ++#define R_IA64_SEGREL64LSB 0x5f /* @segrel(sym + add), data8 LSB */ ++#define R_IA64_SECREL32MSB 0x64 /* @secrel(sym + add), data4 MSB */ ++#define R_IA64_SECREL32LSB 0x65 /* @secrel(sym + add), data4 LSB */ ++#define R_IA64_SECREL64MSB 0x66 /* @secrel(sym + add), data8 MSB */ ++#define R_IA64_SECREL64LSB 0x67 /* @secrel(sym + add), data8 LSB */ ++#define R_IA64_REL32MSB 0x6c /* data 4 + REL */ ++#define R_IA64_REL32LSB 0x6d /* data 4 + REL */ ++#define R_IA64_REL64MSB 0x6e /* data 8 + REL */ ++#define R_IA64_REL64LSB 0x6f /* data 8 + REL */ ++#define R_IA64_LTV32MSB 0x74 /* symbol + addend, data4 MSB */ ++#define R_IA64_LTV32LSB 0x75 /* symbol + addend, data4 LSB */ ++#define R_IA64_LTV64MSB 0x76 /* symbol + addend, data8 MSB */ ++#define R_IA64_LTV64LSB 0x77 /* symbol + addend, data8 LSB */ ++#define R_IA64_PCREL21BI 0x79 /* @pcrel(sym + add), 21bit inst */ ++#define R_IA64_PCREL22 0x7a /* @pcrel(sym + add), 22bit inst */ ++#define R_IA64_PCREL64I 0x7b /* @pcrel(sym + add), 64bit inst */ ++#define R_IA64_IPLTMSB 0x80 /* dynamic reloc, imported PLT, MSB */ ++#define R_IA64_IPLTLSB 0x81 /* dynamic reloc, imported PLT, LSB */ ++#define R_IA64_COPY 0x84 /* copy relocation */ ++#define R_IA64_SUB 0x85 /* Addend and symbol difference */ ++#define R_IA64_LTOFF22X 0x86 /* LTOFF22, relaxable. */ ++#define R_IA64_LDXMOV 0x87 /* Use of LTOFF22X. */ ++#define R_IA64_TPREL14 0x91 /* @tprel(sym + add), imm14 */ ++#define R_IA64_TPREL22 0x92 /* @tprel(sym + add), imm22 */ ++#define R_IA64_TPREL64I 0x93 /* @tprel(sym + add), imm64 */ ++#define R_IA64_TPREL64MSB 0x96 /* @tprel(sym + add), data8 MSB */ ++#define R_IA64_TPREL64LSB 0x97 /* @tprel(sym + add), data8 LSB */ ++#define R_IA64_LTOFF_TPREL22 0x9a /* @ltoff(@tprel(s+a)), imm2 */ ++#define R_IA64_DTPMOD64MSB 0xa6 /* @dtpmod(sym + add), data8 MSB */ ++#define R_IA64_DTPMOD64LSB 0xa7 /* @dtpmod(sym + add), data8 LSB */ ++#define R_IA64_LTOFF_DTPMOD22 0xaa /* @ltoff(@dtpmod(sym + add)), imm22 */ ++#define R_IA64_DTPREL14 0xb1 /* @dtprel(sym + add), imm14 */ ++#define R_IA64_DTPREL22 0xb2 /* @dtprel(sym + add), imm22 */ ++#define R_IA64_DTPREL64I 0xb3 /* @dtprel(sym + add), imm64 */ ++#define R_IA64_DTPREL32MSB 0xb4 /* @dtprel(sym + add), data4 MSB */ ++#define R_IA64_DTPREL32LSB 0xb5 /* @dtprel(sym + add), data4 LSB */ ++#define R_IA64_DTPREL64MSB 0xb6 /* @dtprel(sym + add), data8 MSB */ ++#define R_IA64_DTPREL64LSB 0xb7 /* @dtprel(sym + add), data8 LSB */ ++#define R_IA64_LTOFF_DTPREL22 0xba /* @ltoff(@dtprel(s+a)), imm22 */ ++ ++/* SH specific declarations */ ++ ++/* SH relocs. */ ++#define R_SH_NONE 0 ++#define R_SH_DIR32 1 ++#define R_SH_REL32 2 ++#define R_SH_DIR8WPN 3 ++#define R_SH_IND12W 4 ++#define R_SH_DIR8WPL 5 ++#define R_SH_DIR8WPZ 6 ++#define R_SH_DIR8BP 7 ++#define R_SH_DIR8W 8 ++#define R_SH_DIR8L 9 ++#define R_SH_SWITCH16 25 ++#define R_SH_SWITCH32 26 ++#define R_SH_USES 27 ++#define R_SH_COUNT 28 ++#define R_SH_ALIGN 29 ++#define R_SH_CODE 30 ++#define R_SH_DATA 31 ++#define R_SH_LABEL 32 ++#define R_SH_SWITCH8 33 ++#define R_SH_GNU_VTINHERIT 34 ++#define R_SH_GNU_VTENTRY 35 ++#define R_SH_TLS_GD_32 144 ++#define R_SH_TLS_LD_32 145 ++#define R_SH_TLS_LDO_32 146 ++#define R_SH_TLS_IE_32 147 ++#define R_SH_TLS_LE_32 148 ++#define R_SH_TLS_DTPMOD32 149 ++#define R_SH_TLS_DTPOFF32 150 ++#define R_SH_TLS_TPOFF32 151 ++#define R_SH_GOT32 160 ++#define R_SH_PLT32 161 ++#define R_SH_COPY 162 ++#define R_SH_GLOB_DAT 163 ++#define R_SH_JMP_SLOT 164 ++#define R_SH_RELATIVE 165 ++#define R_SH_GOTOFF 166 ++#define R_SH_GOTPC 167 ++/* Keep this the last entry. */ ++#define R_SH_NUM 256 ++ ++/* Additional s390 relocs */ ++ ++#define R_390_NONE 0 /* No reloc. */ ++#define R_390_8 1 /* Direct 8 bit. */ ++#define R_390_12 2 /* Direct 12 bit. */ ++#define R_390_16 3 /* Direct 16 bit. */ ++#define R_390_32 4 /* Direct 32 bit. */ ++#define R_390_PC32 5 /* PC relative 32 bit. */ ++#define R_390_GOT12 6 /* 12 bit GOT offset. */ ++#define R_390_GOT32 7 /* 32 bit GOT offset. */ ++#define R_390_PLT32 8 /* 32 bit PC relative PLT address. */ ++#define R_390_COPY 9 /* Copy symbol at runtime. */ ++#define R_390_GLOB_DAT 10 /* Create GOT entry. */ ++#define R_390_JMP_SLOT 11 /* Create PLT entry. */ ++#define R_390_RELATIVE 12 /* Adjust by program base. */ ++#define R_390_GOTOFF32 13 /* 32 bit offset to GOT. */ ++#define R_390_GOTPC 14 /* 32 bit PC relative offset to GOT. */ ++#define R_390_GOT16 15 /* 16 bit GOT offset. */ ++#define R_390_PC16 16 /* PC relative 16 bit. */ ++#define R_390_PC16DBL 17 /* PC relative 16 bit shifted by 1. */ ++#define R_390_PLT16DBL 18 /* 16 bit PC rel. PLT shifted by 1. */ ++#define R_390_PC32DBL 19 /* PC relative 32 bit shifted by 1. */ ++#define R_390_PLT32DBL 20 /* 32 bit PC rel. PLT shifted by 1. */ ++#define R_390_GOTPCDBL 21 /* 32 bit PC rel. GOT shifted by 1. */ ++#define R_390_64 22 /* Direct 64 bit. */ ++#define R_390_PC64 23 /* PC relative 64 bit. */ ++#define R_390_GOT64 24 /* 64 bit GOT offset. */ ++#define R_390_PLT64 25 /* 64 bit PC relative PLT address. */ ++#define R_390_GOTENT 26 /* 32 bit PC rel. to GOT entry >> 1. */ ++#define R_390_GOTOFF16 27 /* 16 bit offset to GOT. */ ++#define R_390_GOTOFF64 28 /* 64 bit offset to GOT. */ ++#define R_390_GOTPLT12 29 /* 12 bit offset to jump slot. */ ++#define R_390_GOTPLT16 30 /* 16 bit offset to jump slot. */ ++#define R_390_GOTPLT32 31 /* 32 bit offset to jump slot. */ ++#define R_390_GOTPLT64 32 /* 64 bit offset to jump slot. */ ++#define R_390_GOTPLTENT 33 /* 32 bit rel. offset to jump slot. */ ++#define R_390_PLTOFF16 34 /* 16 bit offset from GOT to PLT. */ ++#define R_390_PLTOFF32 35 /* 32 bit offset from GOT to PLT. */ ++#define R_390_PLTOFF64 36 /* 16 bit offset from GOT to PLT. */ ++#define R_390_TLS_LOAD 37 /* Tag for load insn in TLS code. */ ++#define R_390_TLS_GDCALL 38 /* Tag for function call in general ++ dynamic TLS code. */ ++#define R_390_TLS_LDCALL 39 /* Tag for function call in local ++ dynamic TLS code. */ ++#define R_390_TLS_GD32 40 /* Direct 32 bit for general dynamic ++ thread local data. */ ++#define R_390_TLS_GD64 41 /* Direct 64 bit for general dynamic ++ thread local data. */ ++#define R_390_TLS_GOTIE12 42 /* 12 bit GOT offset for static TLS ++ block offset. */ ++#define R_390_TLS_GOTIE32 43 /* 32 bit GOT offset for static TLS ++ block offset. */ ++#define R_390_TLS_GOTIE64 44 /* 64 bit GOT offset for static TLS ++ block offset. */ ++#define R_390_TLS_LDM32 45 /* Direct 32 bit for local dynamic ++ thread local data in LE code. */ ++#define R_390_TLS_LDM64 46 /* Direct 64 bit for local dynamic ++ thread local data in LE code. */ ++#define R_390_TLS_IE32 47 /* 32 bit address of GOT entry for ++ negated static TLS block offset. */ ++#define R_390_TLS_IE64 48 /* 64 bit address of GOT entry for ++ negated static TLS block offset. */ ++#define R_390_TLS_IEENT 49 /* 32 bit rel. offset to GOT entry for ++ negated static TLS block offset. */ ++#define R_390_TLS_LE32 50 /* 32 bit negated offset relative to ++ static TLS block. */ ++#define R_390_TLS_LE64 51 /* 64 bit negated offset relative to ++ static TLS block. */ ++#define R_390_TLS_LDO32 52 /* 32 bit offset relative to TLS ++ block. */ ++#define R_390_TLS_LDO64 53 /* 64 bit offset relative to TLS ++ block. */ ++#define R_390_TLS_DTPMOD 54 /* ID of module containing symbol. */ ++#define R_390_TLS_DTPOFF 55 /* Offset in TLS block. */ ++#define R_390_TLS_TPOFF 56 /* Negated offset in static TLS ++ block. */ ++ ++/* Keep this the last entry. */ ++#define R_390_NUM 57 ++ ++/* CRIS relocations. */ ++#define R_CRIS_NONE 0 ++#define R_CRIS_8 1 ++#define R_CRIS_16 2 ++#define R_CRIS_32 3 ++#define R_CRIS_8_PCREL 4 ++#define R_CRIS_16_PCREL 5 ++#define R_CRIS_32_PCREL 6 ++#define R_CRIS_GNU_VTINHERIT 7 ++#define R_CRIS_GNU_VTENTRY 8 ++#define R_CRIS_COPY 9 ++#define R_CRIS_GLOB_DAT 10 ++#define R_CRIS_JUMP_SLOT 11 ++#define R_CRIS_RELATIVE 12 ++#define R_CRIS_16_GOT 13 ++#define R_CRIS_32_GOT 14 ++#define R_CRIS_16_GOTPLT 15 ++#define R_CRIS_32_GOTPLT 16 ++#define R_CRIS_32_GOTREL 17 ++#define R_CRIS_32_PLT_GOTREL 18 ++#define R_CRIS_32_PLT_PCREL 19 ++ ++#define R_CRIS_NUM 20 ++ ++/* AMD x86-64 relocations. */ ++#define R_X86_64_NONE 0 /* No reloc */ ++#define R_X86_64_64 1 /* Direct 64 bit */ ++#define R_X86_64_PC32 2 /* PC relative 32 bit signed */ ++#define R_X86_64_GOT32 3 /* 32 bit GOT entry */ ++#define R_X86_64_PLT32 4 /* 32 bit PLT address */ ++#define R_X86_64_COPY 5 /* Copy symbol at runtime */ ++#define R_X86_64_GLOB_DAT 6 /* Create GOT entry */ ++#define R_X86_64_JUMP_SLOT 7 /* Create PLT entry */ ++#define R_X86_64_RELATIVE 8 /* Adjust by program base */ ++#define R_X86_64_GOTPCREL 9 /* 32 bit signed PC relative ++ offset to GOT */ ++#define R_X86_64_32 10 /* Direct 32 bit zero extended */ ++#define R_X86_64_32S 11 /* Direct 32 bit sign extended */ ++#define R_X86_64_16 12 /* Direct 16 bit zero extended */ ++#define R_X86_64_PC16 13 /* 16 bit sign extended pc relative */ ++#define R_X86_64_8 14 /* Direct 8 bit sign extended */ ++#define R_X86_64_PC8 15 /* 8 bit sign extended pc relative */ ++#define R_X86_64_DTPMOD64 16 /* ID of module containing symbol */ ++#define R_X86_64_DTPOFF64 17 /* Offset in module's TLS block */ ++#define R_X86_64_TPOFF64 18 /* Offset in initial TLS block */ ++#define R_X86_64_TLSGD 19 /* 32 bit signed PC relative offset ++ to two GOT entries for GD symbol */ ++#define R_X86_64_TLSLD 20 /* 32 bit signed PC relative offset ++ to two GOT entries for LD symbol */ ++#define R_X86_64_DTPOFF32 21 /* Offset in TLS block */ ++#define R_X86_64_GOTTPOFF 22 /* 32 bit signed PC relative offset ++ to GOT entry for IE symbol */ ++#define R_X86_64_TPOFF32 23 /* Offset in initial TLS block */ ++ ++#define R_X86_64_NUM 24 ++ ++__END_DECLS ++ ++#endif /* elf.h */ + + #include "elfconfig.h" + +@@ -195,3 +2641,4 @@ + void fatal(const char *fmt, ...); + void warn(const char *fmt, ...); + void merror(const char *fmt, ...); ++ +diff -Nur linux-2.6.36.orig/scripts/mod/sumversion.c linux-2.6.36/scripts/mod/sumversion.c +--- linux-2.6.36.orig/scripts/mod/sumversion.c 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/scripts/mod/sumversion.c 2010-11-28 18:33:24.000000000 +0100 +@@ -1,4 +1,4 @@ +-#include ++/* #include */ + #ifdef __sun__ + #include + #else diff --git a/target/linux/patches/3.0.9/cris-etrax.patch b/target/linux/patches/3.0.9/cris-etrax.patch new file mode 100644 index 000000000..a80d9a8b8 --- /dev/null +++ b/target/linux/patches/3.0.9/cris-etrax.patch @@ -0,0 +1,12 @@ +diff -Nur linux-2.6.39.orig/arch/cris/arch-v32/drivers/i2c.h linux-2.6.39/arch/cris/arch-v32/drivers/i2c.h +--- linux-2.6.39.orig/arch/cris/arch-v32/drivers/i2c.h 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/arch/cris/arch-v32/drivers/i2c.h 2011-08-24 19:15:05.000000000 +0200 +@@ -2,7 +2,7 @@ + #include + + /* High level I2C actions */ +-int __init i2c_init(void); ++static int __init i2c_init(void); + int i2c_write(unsigned char theSlave, void *data, size_t nbytes); + int i2c_read(unsigned char theSlave, void *data, size_t nbytes); + int i2c_writereg(unsigned char theSlave, unsigned char theReg, unsigned char theValue); diff --git a/target/linux/patches/3.0.9/defaults.patch b/target/linux/patches/3.0.9/defaults.patch new file mode 100644 index 000000000..58aae610b --- /dev/null +++ b/target/linux/patches/3.0.9/defaults.patch @@ -0,0 +1,22 @@ +diff -Nur linux-3.0.4.orig/fs/Kconfig linux-3.0.4/fs/Kconfig +--- linux-3.0.4.orig/fs/Kconfig 2011-08-29 22:56:30.000000000 +0200 ++++ linux-3.0.4/fs/Kconfig 2011-10-15 22:08:44.000000000 +0200 +@@ -47,7 +47,7 @@ + def_bool n + + config EXPORTFS +- tristate ++ def_bool y + + config FILE_LOCKING + bool "Enable POSIX file locking API" if EXPERT +diff -Nur linux-3.0.4.orig/fs/notify/Kconfig linux-3.0.4/fs/notify/Kconfig +--- linux-3.0.4.orig/fs/notify/Kconfig 2011-08-29 22:56:30.000000000 +0200 ++++ linux-3.0.4/fs/notify/Kconfig 2011-10-15 22:02:00.000000000 +0200 +@@ -1,5 +1,5 @@ + config FSNOTIFY +- def_bool n ++ def_bool y + + source "fs/notify/dnotify/Kconfig" + source "fs/notify/inotify/Kconfig" diff --git a/target/linux/patches/3.0.9/fon2100.patch b/target/linux/patches/3.0.9/fon2100.patch new file mode 100644 index 000000000..038ff7020 --- /dev/null +++ b/target/linux/patches/3.0.9/fon2100.patch @@ -0,0 +1,6279 @@ +diff -Nur linux-2.6.39-rc7.orig/arch/mips/Kbuild.platforms linux-2.6.39-rc7/arch/mips/Kbuild.platforms +--- linux-2.6.39-rc7.orig/arch/mips/Kbuild.platforms 2011-05-10 04:33:54.000000000 +0200 ++++ linux-2.6.39-rc7/arch/mips/Kbuild.platforms 2011-05-15 21:34:57.000000000 +0200 +@@ -6,6 +6,7 @@ + platforms += bcm47xx + platforms += bcm63xx + platforms += cavium-octeon ++platforms += ar231x + platforms += cobalt + platforms += dec + platforms += emma +diff -Nur linux-2.6.39-rc7.orig/arch/mips/Kconfig linux-2.6.39-rc7/arch/mips/Kconfig +--- linux-2.6.39-rc7.orig/arch/mips/Kconfig 2011-05-10 04:33:54.000000000 +0200 ++++ linux-2.6.39-rc7/arch/mips/Kconfig 2011-05-16 12:11:11.000000000 +0200 +@@ -121,6 +121,21 @@ + help + Support for BCM63XX based boards + ++config ATHEROS_AR231X ++ bool "Atheros 231x/531x SoC support" ++ select CEVT_R4K ++ select CSRC_R4K ++ select DMA_NONCOHERENT ++ select IRQ_CPU ++ select SYS_HAS_CPU_MIPS32_R1 ++ select SYS_SUPPORTS_BIG_ENDIAN ++ select SYS_SUPPORTS_32BIT_KERNEL ++ select GENERIC_GPIO ++ select SYS_HAS_EARLY_PRINTK ++ select SYS_SUPPORTS_ZBOOT ++ help ++ Support for AR231x and AR531x based boards ++ + config MIPS_COBALT + bool "Cobalt Server" + select CEVT_R4K +@@ -738,6 +753,7 @@ + + endchoice + ++source "arch/mips/ar231x/Kconfig" + source "arch/mips/alchemy/Kconfig" + source "arch/mips/ath79/Kconfig" + source "arch/mips/bcm63xx/Kconfig" +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/Kconfig linux-2.6.39-rc7/arch/mips/ar231x/Kconfig +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/Kconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/Kconfig 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,27 @@ ++config ATHEROS_AR5312 ++ bool "Atheros 5312/2312+ support" ++ depends on ATHEROS_AR231X ++ default y ++ ++config ATHEROS_AR2315 ++ bool "Atheros 2315+ support" ++ depends on ATHEROS_AR231X ++ select DMA_NONCOHERENT ++ select CEVT_R4K ++ select CSRC_R4K ++ select IRQ_CPU ++ select SYS_HAS_CPU_MIPS32_R1 ++ select SYS_SUPPORTS_32BIT_KERNEL ++ select SYS_SUPPORTS_BIG_ENDIAN ++ select GENERIC_GPIO ++ default y ++ ++config ATHEROS_AR2315_PCI ++ bool "PCI support" ++ depends on ATHEROS_AR2315 ++ select HW_HAS_PCI ++ select PCI ++ select USB_ARCH_HAS_HCD ++ select USB_ARCH_HAS_OHCI ++ select USB_ARCH_HAS_EHCI ++ default n +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/Makefile linux-2.6.39-rc7/arch/mips/ar231x/Makefile +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/Makefile 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,17 @@ ++# ++# This file is subject to the terms and conditions of the GNU General Public ++# License. See the file "COPYING" in the main directory of this archive ++# for more details. ++# ++# Copyright (C) 2006 FON Technology, SL. ++# Copyright (C) 2006 Imre Kaloz ++# Copyright (C) 2006-2009 Felix Fietkau ++# ++ ++obj-y += board.o prom.o devices.o ++ ++obj-$(CONFIG_EARLY_PRINTK) += early_printk.o ++ ++obj-$(CONFIG_ATHEROS_AR5312) += ar5312.o ++obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o ++obj-$(CONFIG_ATHEROS_AR2315_PCI) += pci.o +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/Platform linux-2.6.39-rc7/arch/mips/ar231x/Platform +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/Platform 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/Platform 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,6 @@ ++# ++# Atheros AR5312/AR2312 WiSoC ++# ++platform-$(CONFIG_ATHEROS_AR231X) += ar231x/ ++cflags-$(CONFIG_ATHEROS_AR231X) += -I$(srctree)/arch/mips/include/asm/mach-ar231x ++load-$(CONFIG_ATHEROS_AR231X) += 0xffffffff80041000 +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/ar2315.c linux-2.6.39-rc7/arch/mips/ar231x/ar2315.c +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/ar2315.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/ar2315.c 2011-05-15 21:47:07.000000000 +0200 +@@ -0,0 +1,654 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. ++ * Copyright (C) 2006 FON Technology, SL. ++ * Copyright (C) 2006 Imre Kaloz ++ * Copyright (C) 2006 Felix Fietkau ++ */ ++ ++/* ++ * Platform devices for Atheros SoCs ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include "devices.h" ++#include "ar2315.h" ++ ++static u32 gpiointmask = 0, gpiointval = 0; ++ ++static inline void ar2315_gpio_irq(void) ++{ ++ u32 pend; ++ int bit = -1; ++ ++ /* only do one gpio interrupt at a time */ ++ pend = (ar231x_read_reg(AR2315_GPIO_DI) ^ gpiointval) & gpiointmask; ++ ++ if (pend) { ++ bit = fls(pend) - 1; ++ pend &= ~(1 << bit); ++ gpiointval ^= (1 << bit); ++ } ++ ++ if (!pend) ++ ar231x_write_reg(AR2315_ISR, AR2315_ISR_GPIO); ++ ++ /* Enable interrupt with edge detection */ ++ if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(bit)) != AR2315_GPIO_CR_I(bit)) ++ return; ++ ++ if (bit >= 0) ++ do_IRQ(AR531X_GPIO_IRQ_BASE + bit); ++} ++ ++#ifdef CONFIG_ATHEROS_AR2315_PCI ++static inline void pci_abort_irq(void) ++{ ++ ar231x_write_reg(AR2315_PCI_INT_STATUS, AR2315_PCI_ABORT_INT); ++} ++ ++static inline void pci_ack_irq(void) ++{ ++ ar231x_write_reg(AR2315_PCI_INT_STATUS, AR2315_PCI_EXT_INT); ++} ++ ++void ar2315_pci_irq(int irq) ++{ ++ if (ar231x_read_reg(AR2315_PCI_INT_STATUS) == AR2315_PCI_ABORT_INT) ++ pci_abort_irq(); ++ else { ++ do_IRQ(irq); ++ pci_ack_irq(); ++ } ++} ++#endif /* CONFIG_ATHEROS_AR2315_PCI */ ++ ++/* ++ * Called when an interrupt is received, this function ++ * determines exactly which interrupt it was, and it ++ * invokes the appropriate handler. ++ * ++ * Implicitly, we also define interrupt priority by ++ * choosing which to dispatch first. ++ */ ++static asmlinkage void ++ar2315_irq_dispatch(void) ++{ ++ int pending = read_c0_status() & read_c0_cause(); ++ ++ if (pending & CAUSEF_IP3) ++ do_IRQ(AR2315_IRQ_WLAN0_INTRS); ++ else if (pending & CAUSEF_IP4) ++ do_IRQ(AR2315_IRQ_ENET0_INTRS); ++#ifdef CONFIG_ATHEROS_AR2315_PCI ++ else if (pending & CAUSEF_IP5) ++ ar2315_pci_irq(AR2315_IRQ_LCBUS_PCI); ++#endif ++ else if (pending & CAUSEF_IP2) { ++ unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) & ar231x_read_reg(AR2315_IMR); ++ ++ if (misc_intr & AR2315_ISR_SPI) ++ do_IRQ(AR531X_MISC_IRQ_SPI); ++ else if (misc_intr & AR2315_ISR_TIMER) ++ do_IRQ(AR531X_MISC_IRQ_TIMER); ++ else if (misc_intr & AR2315_ISR_AHB) ++ do_IRQ(AR531X_MISC_IRQ_AHB_PROC); ++ else if (misc_intr & AR2315_ISR_GPIO) ++ ar2315_gpio_irq(); ++ else if (misc_intr & AR2315_ISR_UART0) ++ do_IRQ(AR531X_MISC_IRQ_UART0); ++ else if (misc_intr & AR2315_ISR_WD) ++ do_IRQ(AR531X_MISC_IRQ_WATCHDOG); ++ else ++ do_IRQ(AR531X_MISC_IRQ_NONE); ++ } else if (pending & CAUSEF_IP7) ++ do_IRQ(AR531X_IRQ_CPU_CLOCK); ++} ++ ++static void ar2315_set_gpiointmask(int gpio, int level) ++{ ++ u32 reg; ++ ++ reg = ar231x_read_reg(AR2315_GPIO_INT); ++ reg &= ~(AR2315_GPIO_INT_M | AR2315_GPIO_INT_LVL_M); ++ reg |= gpio | AR2315_GPIO_INT_LVL(level); ++ ar231x_write_reg(AR2315_GPIO_INT, reg); ++} ++ ++static void ar2315_gpio_intr_enable(struct irq_data *d) ++{ ++ unsigned int gpio = d->irq - AR531X_GPIO_IRQ_BASE; ++ ++ /* Enable interrupt with edge detection */ ++ if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(gpio)) != AR2315_GPIO_CR_I(gpio)) ++ return; ++ ++ gpiointmask |= (1 << gpio); ++ ar2315_set_gpiointmask(gpio, 3); ++} ++ ++static void ar2315_gpio_intr_disable(struct irq_data *d) ++{ ++ unsigned int gpio = d->irq - AR531X_GPIO_IRQ_BASE; ++ ++ /* Disable interrupt */ ++ gpiointmask &= ~(1 << gpio); ++ ar2315_set_gpiointmask(gpio, 0); ++} ++ ++static struct irq_chip ar2315_gpio_intr_controller = { ++ .name = "AR2315-GPIO", ++ .irq_ack = ar2315_gpio_intr_disable, ++ .irq_mask_ack = ar2315_gpio_intr_disable, ++ .irq_mask = ar2315_gpio_intr_disable, ++ .irq_unmask = ar2315_gpio_intr_enable, ++}; ++ ++static void ++ar2315_misc_intr_enable(struct irq_data *d) ++{ ++ unsigned int imr; ++ ++ imr = ar231x_read_reg(AR2315_IMR); ++ switch(d->irq) { ++ case AR531X_MISC_IRQ_SPI: ++ imr |= AR2315_ISR_SPI; ++ break; ++ case AR531X_MISC_IRQ_TIMER: ++ imr |= AR2315_ISR_TIMER; ++ break; ++ case AR531X_MISC_IRQ_AHB_PROC: ++ imr |= AR2315_ISR_AHB; ++ break; ++ case AR531X_MISC_IRQ_GPIO: ++ imr |= AR2315_ISR_GPIO; ++ break; ++ case AR531X_MISC_IRQ_UART0: ++ imr |= AR2315_ISR_UART0; ++ break; ++ case AR531X_MISC_IRQ_WATCHDOG: ++ imr |= AR2315_ISR_WD; ++ break; ++ default: ++ break; ++ } ++ ar231x_write_reg(AR2315_IMR, imr); ++} ++ ++static void ++ar2315_misc_intr_disable(struct irq_data *d) ++{ ++ unsigned int imr; ++ ++ imr = ar231x_read_reg(AR2315_IMR); ++ switch(d->irq) { ++ case AR531X_MISC_IRQ_SPI: ++ imr &= ~AR2315_ISR_SPI; ++ break; ++ case AR531X_MISC_IRQ_TIMER: ++ imr &= ~AR2315_ISR_TIMER; ++ break; ++ case AR531X_MISC_IRQ_AHB_PROC: ++ imr &= ~AR2315_ISR_AHB; ++ break; ++ case AR531X_MISC_IRQ_GPIO: ++ imr &= ~AR2315_ISR_GPIO; ++ break; ++ case AR531X_MISC_IRQ_UART0: ++ imr &= ~AR2315_ISR_UART0; ++ break; ++ case AR531X_MISC_IRQ_WATCHDOG: ++ imr &= ~AR2315_ISR_WD; ++ break; ++ default: ++ break; ++ } ++ ar231x_write_reg(AR2315_IMR, imr); ++} ++ ++ ++static struct irq_chip ar2315_misc_intr_controller = { ++ .name = "AR2315-MISC", ++ .irq_mask = ar2315_misc_intr_disable, ++ .irq_unmask = ar2315_misc_intr_enable, ++}; ++ ++static irqreturn_t ar2315_ahb_proc_handler(int cpl, void *dev_id) ++{ ++ ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET); ++ ar231x_read_reg(AR2315_AHB_ERR1); ++ ++ printk(KERN_ERR "AHB fatal error\n"); ++ machine_restart("AHB error"); /* Catastrophic failure */ ++ ++ return IRQ_HANDLED; ++} ++ ++static struct irqaction ar2315_ahb_proc_interrupt = { ++ .handler = ar2315_ahb_proc_handler, ++ .flags = IRQF_DISABLED, ++ .name = "ar2315_ahb_proc_interrupt", ++}; ++ ++static struct irqaction cascade = { ++ .handler = no_action, ++ .flags = IRQF_DISABLED, ++ .name = "cascade", ++}; ++ ++void ++ar2315_irq_init(void) ++{ ++ int i; ++ ++ if (!is_2315()) ++ return; ++ ++ ar231x_irq_dispatch = ar2315_irq_dispatch; ++ gpiointval = ar231x_read_reg(AR2315_GPIO_DI); ++ for (i = 0; i < AR531X_MISC_IRQ_COUNT; i++) { ++ int irq = AR531X_MISC_IRQ_BASE + i; ++ irq_set_chip_and_handler(irq, &ar2315_misc_intr_controller, ++ handle_level_irq); ++ } ++ for (i = 0; i < AR531X_GPIO_IRQ_COUNT; i++) { ++ int irq = AR531X_GPIO_IRQ_BASE + i; ++ irq_set_chip_and_handler(irq, &ar2315_gpio_intr_controller, ++ handle_level_irq); ++ } ++ setup_irq(AR531X_MISC_IRQ_GPIO, &cascade); ++ setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar2315_ahb_proc_interrupt); ++ setup_irq(AR2315_IRQ_MISC_INTRS, &cascade); ++} ++ ++const struct ar231x_gpiodev ar2315_gpiodev; ++ ++static u32 ++ar2315_gpio_get_output(void) ++{ ++ u32 reg; ++ reg = ar231x_read_reg(AR2315_GPIO_CR); ++ reg &= ar2315_gpiodev.valid_mask; ++ return reg; ++} ++ ++static u32 ++ar2315_gpio_set_output(u32 mask, u32 val) ++{ ++ u32 reg; ++ ++ reg = ar231x_read_reg(AR2315_GPIO_CR); ++ reg &= ~mask; ++ reg |= val; ++ ar231x_write_reg(AR2315_GPIO_CR, reg); ++ return reg; ++} ++ ++static u32 ++ar2315_gpio_get(void) ++{ ++ u32 reg; ++ reg = ar231x_read_reg(AR2315_GPIO_DI); ++ reg &= ar2315_gpiodev.valid_mask; ++ return reg; ++} ++ ++static u32 ++ar2315_gpio_set(u32 mask, u32 value) ++{ ++ u32 reg; ++ reg = ar231x_read_reg(AR2315_GPIO_DO); ++ reg &= ~mask; ++ reg |= value; ++ ar231x_write_reg(AR2315_GPIO_DO, reg); ++ return reg; ++} ++ ++const struct ar231x_gpiodev ar2315_gpiodev = { ++ .valid_mask = (1 << 22) - 1, ++ .get_output = ar2315_gpio_get_output, ++ .set_output = ar2315_gpio_set_output, ++ .get = ar2315_gpio_get, ++ .set = ar2315_gpio_set, ++}; ++ ++static struct ar231x_eth ar2315_eth_data = { ++ .reset_base = AR2315_RESET, ++ .reset_mac = AR2315_RESET_ENET0, ++ .reset_phy = AR2315_RESET_EPHY0, ++ .phy_base = KSEG1ADDR(AR2315_ENET0), ++ .config = &ar231x_board, ++}; ++ ++static struct resource ar2315_spiflash_res[] = { ++ { ++ .name = "flash_base", ++ .flags = IORESOURCE_MEM, ++ .start = KSEG1ADDR(AR2315_SPI_READ), ++ .end = KSEG1ADDR(AR2315_SPI_READ) + 0x1000000 - 1, ++ }, ++ { ++ .name = "flash_regs", ++ .flags = IORESOURCE_MEM, ++ .start = 0x11300000, ++ .end = 0x11300012, ++ }, ++}; ++ ++static struct platform_device ar2315_spiflash = { ++ .id = 0, ++ .name = "spiflash", ++ .resource = ar2315_spiflash_res, ++ .num_resources = ARRAY_SIZE(ar2315_spiflash_res) ++}; ++ ++static struct platform_device ar2315_wdt = { ++ .id = 0, ++ .name = "ar2315_wdt", ++}; ++ ++#define SPI_FLASH_CTL 0x00 ++#define SPI_FLASH_OPCODE 0x04 ++#define SPI_FLASH_DATA 0x08 ++ ++static inline u32 ++spiflash_read_reg(int reg) ++{ ++ return ar231x_read_reg(AR2315_SPI + reg); ++} ++ ++static inline void ++spiflash_write_reg(int reg, u32 data) ++{ ++ ar231x_write_reg(AR2315_SPI + reg, data); ++} ++ ++static u32 ++spiflash_wait_status(void) ++{ ++ u32 reg; ++ ++ do { ++ reg = spiflash_read_reg(SPI_FLASH_CTL); ++ } while (reg & SPI_CTL_BUSY); ++ ++ return reg; ++} ++ ++static u8 ++spiflash_probe(void) ++{ ++ u32 reg; ++ ++ reg = spiflash_wait_status(); ++ reg &= ~SPI_CTL_TX_RX_CNT_MASK; ++ reg |= (1 << 4) | 4 | SPI_CTL_START; ++ ++ spiflash_write_reg(SPI_FLASH_OPCODE, 0xab); ++ spiflash_write_reg(SPI_FLASH_CTL, reg); ++ ++ reg = spiflash_wait_status(); ++ reg = spiflash_read_reg(SPI_FLASH_DATA); ++ reg &= 0xff; ++ ++ return (u8) reg; ++} ++ ++ ++#define STM_8MBIT_SIGNATURE 0x13 ++#define STM_16MBIT_SIGNATURE 0x14 ++#define STM_32MBIT_SIGNATURE 0x15 ++#define STM_64MBIT_SIGNATURE 0x16 ++#define STM_128MBIT_SIGNATURE 0x17 ++ ++static u8 __init * ++ar2315_flash_limit(void) ++{ ++ u32 flash_size = 0; ++ ++ /* probe the flash chip size */ ++ switch(spiflash_probe()) { ++ case STM_8MBIT_SIGNATURE: ++ flash_size = 0x00100000; ++ break; ++ case STM_16MBIT_SIGNATURE: ++ flash_size = 0x00200000; ++ break; ++ case STM_32MBIT_SIGNATURE: ++ flash_size = 0x00400000; ++ break; ++ case STM_64MBIT_SIGNATURE: ++ flash_size = 0x00800000; ++ break; ++ case STM_128MBIT_SIGNATURE: ++ flash_size = 0x01000000; ++ break; ++ } ++ ++ ar2315_spiflash_res[0].end = ar2315_spiflash_res[0].start + ++ flash_size - 1; ++ return (u8 *) ar2315_spiflash_res[0].end + 1; ++} ++ ++#ifdef CONFIG_LEDS_GPIO ++static struct gpio_led ar2315_leds[6]; ++static struct gpio_led_platform_data ar2315_led_data = { ++ .leds = (void *) ar2315_leds, ++}; ++ ++static struct platform_device ar2315_gpio_leds = { ++ .name = "leds-gpio", ++ .id = -1, ++ .dev = { ++ .platform_data = (void *) &ar2315_led_data, ++ } ++}; ++ ++static void __init ++ar2315_init_gpio(void) ++{ ++ static char led_names[6][6]; ++ int i, led = 0; ++ ++ ar2315_led_data.num_leds = 0; ++ for(i = 1; i < 8; i++) ++ { ++ if((i == AR2315_RESET_GPIO) || ++ (i == ar231x_board.config->resetConfigGpio)) ++ continue; ++ ++ if(i == ar231x_board.config->sysLedGpio) ++ strcpy(led_names[led], "wlan"); ++ else ++ sprintf(led_names[led], "gpio%d", i); ++ ++ ar2315_leds[led].name = led_names[led]; ++ ar2315_leds[led].gpio = i; ++ ar2315_leds[led].active_low = 0; ++ led++; ++ } ++ ar2315_led_data.num_leds = led; ++ platform_device_register(&ar2315_gpio_leds); ++} ++#else ++static inline void ar2315_init_gpio(void) ++{ ++} ++#endif ++ ++int __init ++ar2315_init_devices(void) ++{ ++ if (!is_2315()) ++ return 0; ++ ++ /* Find board configuration */ ++ ar231x_find_config(ar2315_flash_limit()); ++ ar2315_eth_data.macaddr = ar231x_board.config->enet0_mac; ++ ++ ar2315_init_gpio(); ++ platform_device_register(&ar2315_wdt); ++ platform_device_register(&ar2315_spiflash); ++ ar231x_add_ethernet(0, KSEG1ADDR(AR2315_ENET0), AR2315_IRQ_ENET0_INTRS, ++ &ar2315_eth_data); ++ ar231x_add_wmac(0, AR2315_WLAN0, AR2315_IRQ_WLAN0_INTRS); ++ ++ return 0; ++} ++ ++static void ++ar2315_restart(char *command) ++{ ++ void (*mips_reset_vec)(void) = (void *) 0xbfc00000; ++ ++ local_irq_disable(); ++ ++ /* try reset the system via reset control */ ++ ar231x_write_reg(AR2315_COLD_RESET,AR2317_RESET_SYSTEM); ++ ++ /* Cold reset does not work on the AR2315/6, use the GPIO reset bits a workaround. ++ * give it some time to attempt a gpio based hardware reset ++ * (atheros reference design workaround) */ ++ gpio_direction_output(AR2315_RESET_GPIO, 0); ++ mdelay(100); ++ ++ /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic ++ * workaround. Attempt to jump to the mips reset location - ++ * the boot loader itself might be able to recover the system */ ++ mips_reset_vec(); ++} ++ ++ ++/* ++ * This table is indexed by bits 5..4 of the CLOCKCTL1 register ++ * to determine the predevisor value. ++ */ ++static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = { 1, 2, 4, 5 }; ++static int __initdata PLLC_DIVIDE_TABLE[5] = { 2, 3, 4, 6, 3 }; ++ ++static unsigned int __init ++ar2315_sys_clk(unsigned int clockCtl) ++{ ++ unsigned int pllcCtrl,cpuDiv; ++ unsigned int pllcOut,refdiv,fdiv,divby2; ++ unsigned int clkDiv; ++ ++ pllcCtrl = ar231x_read_reg(AR2315_PLLC_CTL); ++ refdiv = (pllcCtrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S; ++ refdiv = CLOCKCTL1_PREDIVIDE_TABLE[refdiv]; ++ fdiv = (pllcCtrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S; ++ divby2 = (pllcCtrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S; ++ divby2 += 1; ++ pllcOut = (40000000/refdiv)*(2*divby2)*fdiv; ++ ++ ++ /* clkm input selected */ ++ switch(clockCtl & CPUCLK_CLK_SEL_M) { ++ case 0: ++ case 1: ++ clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKM_DIV_M) >> PLLC_CLKM_DIV_S]; ++ break; ++ case 2: ++ clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKC_DIV_M) >> PLLC_CLKC_DIV_S]; ++ break; ++ default: ++ pllcOut = 40000000; ++ clkDiv = 1; ++ break; ++ } ++ cpuDiv = (clockCtl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S; ++ cpuDiv = cpuDiv * 2 ?: 1; ++ return (pllcOut/(clkDiv * cpuDiv)); ++} ++ ++static inline unsigned int ++ar2315_cpu_frequency(void) ++{ ++ return ar2315_sys_clk(ar231x_read_reg(AR2315_CPUCLK)); ++} ++ ++static inline unsigned int ++ar2315_apb_frequency(void) ++{ ++ return ar2315_sys_clk(ar231x_read_reg(AR2315_AMBACLK)); ++} ++ ++void __init ++ar2315_time_init(void) ++{ ++ if (!is_2315()) ++ return; ++ ++ mips_hpt_frequency = ar2315_cpu_frequency() / 2; ++} ++ ++void __init ++ar2315_prom_init(void) ++{ ++ u32 memsize, memcfg, devid; ++ ++ if (!is_2315()) ++ return; ++ ++ memcfg = ar231x_read_reg(AR2315_MEM_CFG); ++ memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S); ++ memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S); ++ memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S); ++ memsize <<= 3; ++ add_memory_region(0, memsize, BOOT_MEM_RAM); ++ ++ /* Detect the hardware based on the device ID */ ++ devid = ar231x_read_reg(AR2315_SREV) & AR2315_REV_CHIP; ++ switch(devid) { ++ case 0x90: ++ case 0x91: ++ ar231x_devtype = DEV_TYPE_AR2317; ++ break; ++ default: ++ ar231x_devtype = DEV_TYPE_AR2315; ++ break; ++ } ++ ar231x_gpiodev = &ar2315_gpiodev; ++ ar231x_board.devid = devid; ++} ++ ++void __init ++ar2315_plat_setup(void) ++{ ++ u32 config; ++ ++ if (!is_2315()) ++ return; ++ ++ /* Clear any lingering AHB errors */ ++ config = read_c0_config(); ++ write_c0_config(config & ~0x3); ++ ar231x_write_reg(AR2315_AHB_ERR0,AHB_ERROR_DET); ++ ar231x_read_reg(AR2315_AHB_ERR1); ++ ar231x_write_reg(AR2315_WDC, AR2315_WDC_IGNORE_EXPIRATION); ++ ++ _machine_restart = ar2315_restart; ++ ar231x_serial_setup(KSEG1ADDR(AR2315_UART0), ar2315_apb_frequency()); ++} +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/ar2315.h linux-2.6.39-rc7/arch/mips/ar231x/ar2315.h +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/ar2315.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/ar2315.h 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,37 @@ ++#ifndef __AR2315_H ++#define __AR2315_H ++ ++#ifdef CONFIG_ATHEROS_AR2315 ++ ++extern void ar2315_irq_init(void); ++extern int ar2315_init_devices(void); ++extern void ar2315_prom_init(void); ++extern void ar2315_plat_setup(void); ++extern void ar2315_time_init(void); ++ ++#else ++ ++static inline void ar2315_irq_init(void) ++{ ++} ++ ++static inline int ar2315_init_devices(void) ++{ ++ return 0; ++} ++ ++static inline void ar2315_prom_init(void) ++{ ++} ++ ++static inline void ar2315_plat_setup(void) ++{ ++} ++ ++static inline void ar2315_time_init(void) ++{ ++} ++ ++#endif ++ ++#endif +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/ar5312.c linux-2.6.39-rc7/arch/mips/ar231x/ar5312.c +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/ar5312.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/ar5312.c 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,538 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. ++ * Copyright (C) 2006 FON Technology, SL. ++ * Copyright (C) 2006 Imre Kaloz ++ * Copyright (C) 2006-2009 Felix Fietkau ++ */ ++ ++/* ++ * Platform devices for Atheros SoCs ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include "devices.h" ++#include "ar5312.h" ++ ++static void ++ar5312_misc_irq_dispatch(void) ++{ ++ unsigned int ar231x_misc_intrs = ar231x_read_reg(AR531X_ISR) & ar231x_read_reg(AR531X_IMR); ++ ++ if (ar231x_misc_intrs & AR531X_ISR_TIMER) { ++ do_IRQ(AR531X_MISC_IRQ_TIMER); ++ (void)ar231x_read_reg(AR531X_TIMER); ++ } else if (ar231x_misc_intrs & AR531X_ISR_AHBPROC) ++ do_IRQ(AR531X_MISC_IRQ_AHB_PROC); ++ else if ((ar231x_misc_intrs & AR531X_ISR_UART0)) ++ do_IRQ(AR531X_MISC_IRQ_UART0); ++ else if (ar231x_misc_intrs & AR531X_ISR_WD) ++ do_IRQ(AR531X_MISC_IRQ_WATCHDOG); ++ else ++ do_IRQ(AR531X_MISC_IRQ_NONE); ++} ++ ++static asmlinkage void ++ar5312_irq_dispatch(void) ++{ ++ int pending = read_c0_status() & read_c0_cause(); ++ ++ if (pending & CAUSEF_IP2) ++ do_IRQ(AR5312_IRQ_WLAN0_INTRS); ++ else if (pending & CAUSEF_IP3) ++ do_IRQ(AR5312_IRQ_ENET0_INTRS); ++ else if (pending & CAUSEF_IP4) ++ do_IRQ(AR5312_IRQ_ENET1_INTRS); ++ else if (pending & CAUSEF_IP5) ++ do_IRQ(AR5312_IRQ_WLAN1_INTRS); ++ else if (pending & CAUSEF_IP6) ++ ar5312_misc_irq_dispatch(); ++ else if (pending & CAUSEF_IP7) ++ do_IRQ(AR531X_IRQ_CPU_CLOCK); ++} ++ ++ ++/* Enable the specified AR531X_MISC_IRQ interrupt */ ++static void ++ar5312_misc_intr_enable(struct irq_data *d) ++{ ++ unsigned int imr; ++ ++ imr = ar231x_read_reg(AR531X_IMR); ++ imr |= (1 << (d->irq - AR531X_MISC_IRQ_BASE - 1)); ++ ar231x_write_reg(AR531X_IMR, imr); ++} ++ ++/* Disable the specified AR531X_MISC_IRQ interrupt */ ++static void ++ar5312_misc_intr_disable(struct irq_data *d) ++{ ++ unsigned int imr; ++ ++ imr = ar231x_read_reg(AR531X_IMR); ++ imr &= ~(1 << (d->irq - AR531X_MISC_IRQ_BASE - 1)); ++ ar231x_write_reg(AR531X_IMR, imr); ++ ar231x_read_reg(AR531X_IMR); /* flush write buffer */ ++} ++ ++static struct irq_chip ar5312_misc_intr_controller = { ++ .name = "AR5312-MISC", ++ .irq_mask = ar5312_misc_intr_disable, ++ .irq_unmask = ar5312_misc_intr_enable, ++}; ++ ++ ++static irqreturn_t ar5312_ahb_proc_handler(int cpl, void *dev_id) ++{ ++ u32 proc1 = ar231x_read_reg(AR531X_PROC1); ++ u32 procAddr = ar231x_read_reg(AR531X_PROCADDR); /* clears error state */ ++ u32 dma1 = ar231x_read_reg(AR531X_DMA1); ++ u32 dmaAddr = ar231x_read_reg(AR531X_DMAADDR); /* clears error state */ ++ ++ printk("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n", ++ procAddr, proc1, dmaAddr, dma1); ++ ++ machine_restart("AHB error"); /* Catastrophic failure */ ++ return IRQ_HANDLED; ++} ++ ++ ++static struct irqaction ar5312_ahb_proc_interrupt = { ++ .handler = ar5312_ahb_proc_handler, ++ .flags = IRQF_DISABLED, ++ .name = "ar5312_ahb_proc_interrupt", ++}; ++ ++ ++static struct irqaction cascade = { ++ .handler = no_action, ++ .flags = IRQF_DISABLED, ++ .name = "cascade", ++}; ++ ++void __init ar5312_irq_init(void) ++{ ++ int i; ++ ++ if (!is_5312()) ++ return; ++ ++ ar231x_irq_dispatch = ar5312_irq_dispatch; ++ for (i = 0; i < AR531X_MISC_IRQ_COUNT; i++) { ++ int irq = AR531X_MISC_IRQ_BASE + i; ++ irq_set_chip_and_handler(irq, &ar5312_misc_intr_controller, ++ handle_level_irq); ++ } ++ setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt); ++ setup_irq(AR5312_IRQ_MISC_INTRS, &cascade); ++} ++ ++const struct ar231x_gpiodev ar5312_gpiodev; ++ ++static u32 ++ar5312_gpio_get_output(void) ++{ ++ u32 reg; ++ reg = ~(ar231x_read_reg(AR531X_GPIO_CR)); ++ reg &= ar5312_gpiodev.valid_mask; ++ return reg; ++} ++ ++static u32 ++ar5312_gpio_set_output(u32 mask, u32 val) ++{ ++ u32 reg; ++ ++ reg = ar231x_read_reg(AR531X_GPIO_CR); ++ reg |= mask; ++ reg &= ~val; ++ ar231x_write_reg(AR531X_GPIO_CR, reg); ++ return reg; ++} ++ ++static u32 ++ar5312_gpio_get(void) ++{ ++ u32 reg; ++ reg = ar231x_read_reg(AR531X_GPIO_DI); ++ reg &= ar5312_gpiodev.valid_mask; ++ return reg; ++} ++ ++static u32 ++ar5312_gpio_set(u32 mask, u32 value) ++{ ++ u32 reg; ++ reg = ar231x_read_reg(AR531X_GPIO_DO); ++ reg &= ~mask; ++ reg |= value; ++ ar231x_write_reg(AR531X_GPIO_DO, reg); ++ return reg; ++} ++ ++const struct ar231x_gpiodev ar5312_gpiodev = { ++ .valid_mask = (1 << 8) - 1, ++ .get_output = ar5312_gpio_get_output, ++ .set_output = ar5312_gpio_set_output, ++ .get = ar5312_gpio_get, ++ .set = ar5312_gpio_set, ++}; ++ ++static struct physmap_flash_data ar5312_flash_data = { ++ .width = 2, ++}; ++ ++static struct resource ar5312_flash_resource = { ++ .start = AR531X_FLASH, ++ .end = AR531X_FLASH + 0x800000 - 1, ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct ar231x_eth ar5312_eth0_data = { ++ .reset_base = AR531X_RESET, ++ .reset_mac = AR531X_RESET_ENET0, ++ .reset_phy = AR531X_RESET_EPHY0, ++ .phy_base = KSEG1ADDR(AR531X_ENET0), ++ .config = &ar231x_board, ++}; ++ ++static struct ar231x_eth ar5312_eth1_data = { ++ .reset_base = AR531X_RESET, ++ .reset_mac = AR531X_RESET_ENET1, ++ .reset_phy = AR531X_RESET_EPHY1, ++ .phy_base = KSEG1ADDR(AR531X_ENET1), ++ .config = &ar231x_board, ++}; ++ ++static struct platform_device ar5312_physmap_flash = { ++ .name = "physmap-flash", ++ .id = 0, ++ .dev.platform_data = &ar5312_flash_data, ++ .resource = &ar5312_flash_resource, ++ .num_resources = 1, ++}; ++ ++#ifdef CONFIG_LEDS_GPIO ++static struct gpio_led ar5312_leds[] = { ++ { .name = "wlan", .gpio = 0, .active_low = 1, }, ++}; ++ ++static const struct gpio_led_platform_data ar5312_led_data = { ++ .num_leds = ARRAY_SIZE(ar5312_leds), ++ .leds = (void *) ar5312_leds, ++}; ++ ++static struct platform_device ar5312_gpio_leds = { ++ .name = "leds-gpio", ++ .id = -1, ++ .dev.platform_data = (void *) &ar5312_led_data, ++}; ++#endif ++ ++/* ++ * NB: This mapping size is larger than the actual flash size, ++ * but this shouldn't be a problem here, because the flash ++ * will simply be mapped multiple times. ++ */ ++static char __init *ar5312_flash_limit(void) ++{ ++ u32 ctl; ++ /* ++ * Configure flash bank 0. ++ * Assume 8M window size. Flash will be aliased if it's smaller ++ */ ++ ctl = FLASHCTL_E | ++ FLASHCTL_AC_8M | ++ FLASHCTL_RBLE | ++ (0x01 << FLASHCTL_IDCY_S) | ++ (0x07 << FLASHCTL_WST1_S) | ++ (0x07 << FLASHCTL_WST2_S) | ++ (ar231x_read_reg(AR531X_FLASHCTL0) & FLASHCTL_MW); ++ ++ ar231x_write_reg(AR531X_FLASHCTL0, ctl); ++ ++ /* Disable other flash banks */ ++ ar231x_write_reg(AR531X_FLASHCTL1, ++ ar231x_read_reg(AR531X_FLASHCTL1) & ~(FLASHCTL_E | FLASHCTL_AC)); ++ ++ ar231x_write_reg(AR531X_FLASHCTL2, ++ ar231x_read_reg(AR531X_FLASHCTL2) & ~(FLASHCTL_E | FLASHCTL_AC)); ++ ++ return (char *) KSEG1ADDR(AR531X_FLASH + 0x800000); ++} ++ ++int __init ar5312_init_devices(void) ++{ ++ struct ar231x_boarddata *config; ++ u32 fctl = 0; ++ const u8 *radio; ++ u8 *c; ++ ++ if (!is_5312()) ++ return 0; ++ ++ /* Locate board/radio config data */ ++ ar231x_find_config(ar5312_flash_limit()); ++ config = ar231x_board.config; ++ ++ ++ /* ++ * Chip IDs and hardware detection for some Atheros ++ * models are really broken! ++ * ++ * Atheros uses a disabled WMAC0 and Silicon ID of AR5312 ++ * as indication for AR2312, which is otherwise ++ * indistinguishable from the real AR5312. ++ */ ++ if (ar231x_board.radio) { ++ radio = ar231x_board.radio + AR531X_RADIO_MASK_OFF; ++ if ((*((const u32 *) radio) & AR531X_RADIO0_MASK) == 0) ++ config->flags |= BD_ISCASPER; ++ } else ++ radio = NULL; ++ ++ /* AR2313 has CPU minor rev. 10 */ ++ if ((current_cpu_data.processor_id & 0xff) == 0x0a) ++ ar231x_devtype = DEV_TYPE_AR2313; ++ ++ /* AR2312 shares the same Silicon ID as AR5312 */ ++ else if (config->flags & BD_ISCASPER) ++ ar231x_devtype = DEV_TYPE_AR2312; ++ ++ /* Everything else is probably AR5312 or compatible */ ++ else ++ ar231x_devtype = DEV_TYPE_AR5312; ++ ++ /* fixup flash width */ ++ fctl = ar231x_read_reg(AR531X_FLASHCTL) & FLASHCTL_MW; ++ switch (fctl) { ++ case FLASHCTL_MWx16: ++ ar5312_flash_data.width = 2; ++ break; ++ case FLASHCTL_MWx8: ++ default: ++ ar5312_flash_data.width = 1; ++ break; ++ } ++ ++ platform_device_register(&ar5312_physmap_flash); ++ ++#ifdef CONFIG_LEDS_GPIO ++ ar5312_leds[0].gpio = config->sysLedGpio; ++ platform_device_register(&ar5312_gpio_leds); ++#endif ++ ++ /* Fix up MAC addresses if necessary */ ++ if (!memcmp(config->enet0_mac, "\xff\xff\xff\xff\xff\xff", 6)) ++ memcpy(config->enet0_mac, config->enet1_mac, 6); ++ ++ /* If ENET0 and ENET1 have the same mac address, ++ * increment the one from ENET1 */ ++ if (memcmp(config->enet0_mac, config->enet1_mac, 6) == 0) { ++ c = config->enet1_mac + 5; ++ while ((c >= config->enet1_mac) && !(++(*c))) ++ c--; ++ } ++ ++ switch(ar231x_devtype) { ++ case DEV_TYPE_AR5312: ++ ar5312_eth0_data.macaddr = config->enet0_mac; ++ ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET0), ++ AR5312_IRQ_ENET0_INTRS, &ar5312_eth0_data); ++ ++ ar5312_eth1_data.macaddr = config->enet1_mac; ++ ar231x_add_ethernet(1, KSEG1ADDR(AR531X_ENET1), ++ AR5312_IRQ_ENET1_INTRS, &ar5312_eth1_data); ++ ++ if (!ar231x_board.radio) ++ return 0; ++ ++ if ((*((u32 *) radio) & AR531X_RADIO0_MASK) && ++ (config->flags & BD_WLAN0)) ++ ar231x_add_wmac(0, AR531X_WLAN0, ++ AR5312_IRQ_WLAN0_INTRS); ++ ++ break; ++ /* ++ * AR2312/3 ethernet uses the PHY of ENET0, but the MAC ++ * of ENET1. Atheros calls it 'twisted' for a reason :) ++ */ ++ case DEV_TYPE_AR2312: ++ case DEV_TYPE_AR2313: ++ ar5312_eth1_data.phy_base = ar5312_eth0_data.phy_base; ++ ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy; ++ ar5312_eth1_data.macaddr = config->enet0_mac; ++ ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET1), ++ AR5312_IRQ_ENET1_INTRS, &ar5312_eth1_data); ++ ++ if (!ar231x_board.radio) ++ return 0; ++ break; ++ default: ++ break; ++ } ++ ++ if ((*((u32 *) radio) & AR531X_RADIO1_MASK) && ++ (config->flags & BD_WLAN1)) ++ ar231x_add_wmac(1, AR531X_WLAN1, ++ AR5312_IRQ_WLAN1_INTRS); ++ ++ return 0; ++} ++ ++ ++static void ar5312_restart(char *command) ++{ ++ /* reset the system */ ++ local_irq_disable(); ++ while(1) { ++ ar231x_write_reg(AR531X_RESET, AR531X_RESET_SYSTEM); ++ } ++} ++ ++ ++/* ++ * This table is indexed by bits 5..4 of the CLOCKCTL1 register ++ * to determine the predevisor value. ++ */ ++static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = { 1, 2, 4, 5 }; ++ ++ ++static int __init ++ar5312_cpu_frequency(void) ++{ ++ unsigned int result; ++ unsigned int predivide_mask, predivide_shift; ++ unsigned int multiplier_mask, multiplier_shift; ++ unsigned int clockCtl1, preDivideSelect, preDivisor, multiplier; ++ unsigned int doubler_mask; ++ u16 devid; ++ ++ /* Trust the bootrom's idea of cpu frequency. */ ++ if ((result = ar231x_read_reg(AR5312_SCRATCH))) ++ return result; ++ ++ devid = ar231x_read_reg(AR531X_REV); ++ devid &= AR531X_REV_MAJ; ++ devid >>= AR531X_REV_MAJ_S; ++ if (devid == AR531X_REV_MAJ_AR2313) { ++ predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK; ++ predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT; ++ multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK; ++ multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT; ++ doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK; ++ } else { /* AR5312 and AR2312 */ ++ predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK; ++ predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT; ++ multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK; ++ multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT; ++ doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK; ++ } ++ ++ /* ++ * Clocking is derived from a fixed 40MHz input clock. ++ * ++ * cpuFreq = InputClock * MULT (where MULT is PLL multiplier) ++ * sysFreq = cpuFreq / 4 (used for APB clock, serial, ++ * flash, Timer, Watchdog Timer) ++ * ++ * cntFreq = cpuFreq / 2 (use for CPU count/compare) ++ * ++ * So, for example, with a PLL multiplier of 5, we have ++ * ++ * cpuFreq = 200MHz ++ * sysFreq = 50MHz ++ * cntFreq = 100MHz ++ * ++ * We compute the CPU frequency, based on PLL settings. ++ */ ++ ++ clockCtl1 = ar231x_read_reg(AR5312_CLOCKCTL1); ++ preDivideSelect = (clockCtl1 & predivide_mask) >> predivide_shift; ++ preDivisor = CLOCKCTL1_PREDIVIDE_TABLE[preDivideSelect]; ++ multiplier = (clockCtl1 & multiplier_mask) >> multiplier_shift; ++ ++ if (clockCtl1 & doubler_mask) { ++ multiplier = multiplier << 1; ++ } ++ return (40000000 / preDivisor) * multiplier; ++} ++ ++static inline int ++ar5312_sys_frequency(void) ++{ ++ return ar5312_cpu_frequency() / 4; ++} ++ ++void __init ++ar5312_time_init(void) ++{ ++ if (!is_5312()) ++ return; ++ ++ mips_hpt_frequency = ar5312_cpu_frequency() / 2; ++} ++ ++ ++void __init ++ar5312_prom_init(void) ++{ ++ u32 memsize, memcfg, bank0AC, bank1AC; ++ u32 devid; ++ ++ if (!is_5312()) ++ return; ++ ++ /* Detect memory size */ ++ memcfg = ar231x_read_reg(AR531X_MEM_CFG1); ++ bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S; ++ bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S; ++ memsize = (bank0AC ? (1 << (bank0AC+1)) : 0) ++ + (bank1AC ? (1 << (bank1AC+1)) : 0); ++ memsize <<= 20; ++ add_memory_region(0, memsize, BOOT_MEM_RAM); ++ ++ devid = ar231x_read_reg(AR531X_REV); ++ devid >>= AR531X_REV_WMAC_MIN_S; ++ devid &= AR531X_REV_CHIP; ++ ar231x_board.devid = (u16) devid; ++ ar231x_gpiodev = &ar5312_gpiodev; ++} ++ ++void __init ++ar5312_plat_setup(void) ++{ ++ if (!is_5312()) ++ return; ++ ++ /* Clear any lingering AHB errors */ ++ ar231x_read_reg(AR531X_PROCADDR); ++ ar231x_read_reg(AR531X_DMAADDR); ++ ar231x_write_reg(AR531X_WD_CTRL, AR531X_WD_CTRL_IGNORE_EXPIRATION); ++ ++ _machine_restart = ar5312_restart; ++ ar231x_serial_setup(KSEG1ADDR(AR531X_UART0), ar5312_sys_frequency()); ++} ++ +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/ar5312.h linux-2.6.39-rc7/arch/mips/ar231x/ar5312.h +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/ar5312.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/ar5312.h 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,38 @@ ++#ifndef __AR5312_H ++#define __AR5312_H ++ ++#ifdef CONFIG_ATHEROS_AR5312 ++ ++extern void ar5312_irq_init(void); ++extern int ar5312_init_devices(void); ++extern void ar5312_prom_init(void); ++extern void ar5312_plat_setup(void); ++extern void ar5312_time_init(void); ++extern void ar5312_time_init(void); ++ ++#else ++ ++static inline void ar5312_irq_init(void) ++{ ++} ++ ++static inline int ar5312_init_devices(void) ++{ ++ return 0; ++} ++ ++static inline void ar5312_prom_init(void) ++{ ++} ++ ++static inline void ar5312_plat_setup(void) ++{ ++} ++ ++static inline void ar5312_time_init(void) ++{ ++} ++ ++#endif ++ ++#endif +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/board.c linux-2.6.39-rc7/arch/mips/ar231x/board.c +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/board.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/board.c 2011-05-15 22:16:11.000000000 +0200 +@@ -0,0 +1,261 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. ++ * Copyright (C) 2006 FON Technology, SL. ++ * Copyright (C) 2006 Imre Kaloz ++ * Copyright (C) 2006-2009 Felix Fietkau ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include "devices.h" ++#include "ar5312.h" ++#include "ar2315.h" ++ ++void (*ar231x_irq_dispatch)(void); ++ ++static inline bool ++check_radio_magic(u8 *addr) ++{ ++ addr += 0x7a; /* offset for flash magic */ ++ if ((addr[0] == 0x5a) && (addr[1] == 0xa5)) { ++ return 1; ++ } ++ return 0; ++} ++ ++static inline bool ++check_board_data(u8 *flash_limit, u8 *addr, bool broken) ++{ ++ /* config magic found */ ++ if (*((u32 *)addr) == AR531X_BD_MAGIC) ++ return 1; ++ ++ if (!broken) ++ return 0; ++ ++ if (check_radio_magic(addr + 0xf8)) ++ ar231x_board.radio = addr + 0xf8; ++ if ((addr < flash_limit + 0x10000) && ++ check_radio_magic(addr + 0x10000)) ++ ar231x_board.radio = addr + 0x10000; ++ ++ if (ar231x_board.radio) { ++ /* broken board data detected, use radio data to find the offset, ++ * user will fix this */ ++ return 1; ++ } ++ return 0; ++} ++ ++static u8 * ++find_board_config(u8 *flash_limit, bool broken) ++{ ++ u8 *addr; ++ int found = 0; ++ ++ for (addr = flash_limit - 0x1000; ++ addr >= flash_limit - 0x30000; ++ addr -= 0x1000) { ++ ++ if (check_board_data(flash_limit, addr, broken)) { ++ found = 1; ++ break; ++ } ++ } ++ ++ if (!found) ++ addr = NULL; ++ ++ return addr; ++} ++ ++static u8 * ++find_radio_config(u8 *flash_limit, u8 *board_config) ++{ ++ int found; ++ u8 *radio_config; ++ ++ /* ++ * Now find the start of Radio Configuration data, using heuristics: ++ * Search forward from Board Configuration data by 0x1000 bytes ++ * at a time until we find non-0xffffffff. ++ */ ++ found = 0; ++ for (radio_config = board_config + 0x1000; ++ (radio_config < flash_limit); ++ radio_config += 0x1000) { ++ if ((*(u32 *)radio_config != 0xffffffff) && ++ check_radio_magic(radio_config)) { ++ found = 1; ++ break; ++ } ++ } ++ ++ /* AR2316 relocates radio config to new location */ ++ if (!found) { ++ for (radio_config = board_config + 0xf8; ++ (radio_config < flash_limit - 0x1000 + 0xf8); ++ radio_config += 0x1000) { ++ if ((*(u32 *)radio_config != 0xffffffff) && ++ check_radio_magic(radio_config)) { ++ found = 1; ++ break; ++ } ++ } ++ } ++ ++ if (!found) { ++ printk("Could not find Radio Configuration data\n"); ++ radio_config = 0; ++ } ++ ++ return (u8 *) radio_config; ++} ++ ++int __init ++ar231x_find_config(u8 *flash_limit) ++{ ++ struct ar231x_boarddata *config; ++ unsigned int rcfg_size; ++ int broken_boarddata = 0, i, tmp; ++ u8 *bcfg, *rcfg; ++ u8 *board_data; ++ u8 *radio_data; ++ u32 offset; ++ ++ ar231x_board.config = NULL; ++ ar231x_board.radio = NULL; ++ /* Copy the board and radio data to RAM, because accessing the mapped ++ * memory of the flash directly after booting is not safe */ ++ ++ /* Try to find valid board and radio data */ ++ bcfg = find_board_config(flash_limit, false); ++ ++ /* If that fails, try to at least find valid radio data */ ++ if (!bcfg) { ++ bcfg = find_board_config(flash_limit, true); ++ broken_boarddata = 1; ++ } ++ ++ if (!bcfg) { ++ printk(KERN_WARNING "WARNING: No board configuration data found!\n"); ++ return -ENODEV; ++ } ++ ++ board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL); ++ ar231x_board.config = (struct ar231x_boarddata *) board_data; ++ memcpy(board_data, bcfg, 0x100); ++ if (broken_boarddata) { ++ printk(KERN_WARNING "WARNING: broken board data detected\n"); ++ config = ar231x_board.config; ++ if (!memcmp(config->enet0_mac, "\x00\x00\x00\x00\x00\x00", 6)) { ++ printk(KERN_INFO "Fixing up empty mac addresses\n"); ++ config->resetConfigGpio = 0xffff; ++ config->sysLedGpio = 0xffff; ++ random_ether_addr(config->wlan0_mac); ++ config->wlan0_mac[0] &= ~0x06; ++ random_ether_addr(config->enet0_mac); ++ random_ether_addr(config->enet1_mac); ++ } ++ } ++ ++ ++ /* Radio config starts 0x100 bytes after board config, regardless ++ * of what the physical layout on the flash chip looks like */ ++ ++ if (ar231x_board.radio) ++ rcfg = (u8 *) ar231x_board.radio; ++ else ++ rcfg = find_radio_config(flash_limit, bcfg); ++ ++ if (!rcfg) ++ return -ENODEV; ++ ++ radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff); ++ ar231x_board.radio = radio_data; ++ offset = radio_data - board_data; ++ printk(KERN_INFO "Radio config found at offset 0x%x(0x%x)\n", rcfg - bcfg, offset); ++ rcfg_size = BOARD_CONFIG_BUFSZ - offset; ++ memcpy(radio_data, rcfg, rcfg_size); ++ ++ for (tmp = 0xff, i = 0; i < ETH_ALEN; i++) ++ tmp &= radio_data[i + 0x1d * 2]; ++ if (tmp == 0xff) { ++ u16 *eep = (u16 *)radio_data, *bcfgs = (u16 *)bcfg; ++ printk(KERN_INFO "Radio MAC is blank; using board-data\n"); ++ eep[0x1f] = bcfgs[0x30]; ++ eep[0x1e] = bcfgs[0x34]; ++ eep[0x1d] = bcfgs[0x32]; ++ } ++ ++ return 0; ++} ++ ++static void ++ar231x_halt(void) ++{ ++ local_irq_disable(); ++ while (1); ++} ++ ++void __init ++plat_mem_setup(void) ++{ ++ _machine_halt = ar231x_halt; ++ pm_power_off = ar231x_halt; ++ ++ ar5312_plat_setup(); ++ ar2315_plat_setup(); ++ ++ /* Disable data watchpoints */ ++ write_c0_watchlo0(0); ++} ++ ++ ++asmlinkage void ++plat_irq_dispatch(void) ++{ ++ ar231x_irq_dispatch(); ++} ++ ++void __init ++plat_time_init(void) ++{ ++ ar5312_time_init(); ++ ar2315_time_init(); ++} ++ ++unsigned int __cpuinit ++get_c0_compare_int(void) ++{ ++ return CP0_LEGACY_COMPARE_IRQ; ++} ++ ++void __init ++arch_init_irq(void) ++{ ++ clear_c0_status(ST0_IM); ++ mips_cpu_irq_init(); ++ ++ /* Initialize interrupt controllers */ ++ ar5312_irq_init(); ++ ar2315_irq_init(); ++} ++ ++ +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/devices.c linux-2.6.39-rc7/arch/mips/ar231x/devices.c +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/devices.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/devices.c 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,175 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "devices.h" ++#include "ar5312.h" ++#include "ar2315.h" ++ ++struct ar231x_board_config ar231x_board; ++int ar231x_devtype = DEV_TYPE_UNKNOWN; ++const struct ar231x_gpiodev *ar231x_gpiodev; ++EXPORT_SYMBOL(ar231x_gpiodev); ++ ++static struct resource ar231x_eth0_res[] = { ++ { ++ .name = "eth0_membase", ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = "eth0_irq", ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static struct resource ar231x_eth1_res[] = { ++ { ++ .name = "eth1_membase", ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = "eth1_irq", ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static struct platform_device ar231x_eth[] = { ++ { ++ .id = 0, ++ .name = "ar231x-eth", ++ .resource = ar231x_eth0_res, ++ .num_resources = ARRAY_SIZE(ar231x_eth0_res) ++ }, ++ { ++ .id = 1, ++ .name = "ar231x-eth", ++ .resource = ar231x_eth1_res, ++ .num_resources = ARRAY_SIZE(ar231x_eth1_res) ++ } ++}; ++ ++static struct resource ar231x_wmac0_res[] = { ++ { ++ .name = "wmac0_membase", ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = "wmac0_irq", ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static struct resource ar231x_wmac1_res[] = { ++ { ++ .name = "wmac1_membase", ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = "wmac1_irq", ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++ ++static struct platform_device ar231x_wmac[] = { ++ { ++ .id = 0, ++ .name = "ar231x-wmac", ++ .resource = ar231x_wmac0_res, ++ .num_resources = ARRAY_SIZE(ar231x_wmac0_res), ++ .dev.platform_data = &ar231x_board, ++ }, ++ { ++ .id = 1, ++ .name = "ar231x-wmac", ++ .resource = ar231x_wmac1_res, ++ .num_resources = ARRAY_SIZE(ar231x_wmac1_res), ++ .dev.platform_data = &ar231x_board, ++ }, ++}; ++ ++static const char *devtype_strings[] = { ++ [DEV_TYPE_AR5312] = "Atheros AR5312", ++ [DEV_TYPE_AR2312] = "Atheros AR2312", ++ [DEV_TYPE_AR2313] = "Atheros AR2313", ++ [DEV_TYPE_AR2315] = "Atheros AR2315", ++ [DEV_TYPE_AR2316] = "Atheros AR2316", ++ [DEV_TYPE_AR2317] = "Atheros AR2317", ++ [DEV_TYPE_UNKNOWN] = "Atheros (unknown)", ++}; ++ ++const char *get_system_type(void) ++{ ++ if ((ar231x_devtype >= ARRAY_SIZE(devtype_strings)) || ++ !devtype_strings[ar231x_devtype]) ++ return devtype_strings[DEV_TYPE_UNKNOWN]; ++ return devtype_strings[ar231x_devtype]; ++} ++ ++ ++int __init ++ar231x_add_ethernet(int nr, u32 base, int irq, void *pdata) ++{ ++ struct resource *res; ++ ++ ar231x_eth[nr].dev.platform_data = pdata; ++ res = &ar231x_eth[nr].resource[0]; ++ res->start = base; ++ res->end = base + 0x2000 - 1; ++ res++; ++ res->start = irq; ++ res->end = irq; ++ return platform_device_register(&ar231x_eth[nr]); ++} ++ ++void __init ++ar231x_serial_setup(u32 mapbase, unsigned int uartclk) ++{ ++ struct uart_port s; ++ ++ memset(&s, 0, sizeof(s)); ++ ++ s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST; ++ s.iotype = UPIO_MEM; ++ s.irq = AR531X_MISC_IRQ_UART0; ++ s.regshift = 2; ++ s.mapbase = mapbase; ++ s.uartclk = uartclk; ++ s.membase = (void __iomem *)s.mapbase; ++ ++ early_serial_setup(&s); ++} ++ ++int __init ++ar231x_add_wmac(int nr, u32 base, int irq) ++{ ++ struct resource *res; ++ ++ ar231x_wmac[nr].dev.platform_data = &ar231x_board; ++ res = &ar231x_wmac[nr].resource[0]; ++ res->start = base; ++ res->end = base + 0x10000 - 1; ++ res++; ++ res->start = irq; ++ res->end = irq; ++ return platform_device_register(&ar231x_wmac[nr]); ++} ++ ++static int __init ar231x_register_devices(void) ++{ ++ static struct resource res = { ++ .start = 0xFFFFFFFF, ++ }; ++ ++ platform_device_register_simple("GPIODEV", 0, &res, 1); ++ ar5312_init_devices(); ++ ar2315_init_devices(); ++ ++ return 0; ++} ++ ++device_initcall(ar231x_register_devices); +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/devices.h linux-2.6.39-rc7/arch/mips/ar231x/devices.h +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/devices.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/devices.h 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,37 @@ ++#ifndef __AR231X_DEVICES_H ++#define __AR231X_DEVICES_H ++ ++enum { ++ /* handled by ar5312.c */ ++ DEV_TYPE_AR2312, ++ DEV_TYPE_AR2313, ++ DEV_TYPE_AR5312, ++ ++ /* handled by ar2315.c */ ++ DEV_TYPE_AR2315, ++ DEV_TYPE_AR2316, ++ DEV_TYPE_AR2317, ++ ++ DEV_TYPE_UNKNOWN ++}; ++ ++extern int ar231x_devtype; ++extern struct ar231x_board_config ar231x_board; ++extern asmlinkage void (*ar231x_irq_dispatch)(void); ++ ++extern int ar231x_find_config(u8 *flash_limit); ++extern void ar231x_serial_setup(u32 mapbase, unsigned int uartclk); ++extern int ar231x_add_wmac(int nr, u32 base, int irq); ++extern int ar231x_add_ethernet(int nr, u32 base, int irq, void *pdata); ++ ++static inline bool is_2315(void) ++{ ++ return (current_cpu_data.cputype == CPU_4KEC); ++} ++ ++static inline bool is_5312(void) ++{ ++ return !is_2315(); ++} ++ ++#endif +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/early_printk.c linux-2.6.39-rc7/arch/mips/ar231x/early_printk.c +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/early_printk.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/early_printk.c 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,44 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2010 Gabor Juhos ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include "devices.h" ++ ++static inline void prom_uart_wr(void __iomem *base, unsigned reg, ++ unsigned char ch) ++{ ++ __raw_writeb(ch, base + 4 * reg); ++} ++ ++static inline unsigned char prom_uart_rr(void __iomem *base, unsigned reg) ++{ ++ return __raw_readb(base + 4 * reg); ++} ++ ++void prom_putchar(unsigned char ch) ++{ ++ static void __iomem *base; ++ ++ if (unlikely(base == NULL)) { ++ if (is_2315()) ++ base = (void __iomem *)(KSEG1ADDR(AR2315_UART0)); ++ else ++ base = (void __iomem *)(KSEG1ADDR(AR531X_UART0)); ++ } ++ ++ while ((prom_uart_rr(base, UART_LSR) & UART_LSR_THRE) == 0); ++ prom_uart_wr(base, UART_TX, ch); ++ while ((prom_uart_rr(base, UART_LSR) & UART_LSR_THRE) == 0); ++} ++ +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/pci.c linux-2.6.39-rc7/arch/mips/ar231x/pci.c +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/pci.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/pci.c 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,230 @@ ++/* ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "devices.h" ++ ++#define AR531X_MEM_BASE 0x80800000UL ++#define AR531X_MEM_SIZE 0x00ffffffUL ++#define AR531X_IO_SIZE 0x00007fffUL ++ ++static unsigned long configspace; ++ ++static int config_access(int devfn, int where, int size, u32 *ptr, bool write) ++{ ++ unsigned long flags; ++ int func = PCI_FUNC(devfn); ++ int dev = PCI_SLOT(devfn); ++ u32 value = 0; ++ int err = 0; ++ u32 addr; ++ ++ if (((dev != 0) && (dev != 3)) || (func > 2)) ++ return PCIBIOS_DEVICE_NOT_FOUND; ++ ++ /* Select Configuration access */ ++ local_irq_save(flags); ++ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, 0, AR2315_PCIMISC_CFG_SEL); ++ mb(); ++ ++ addr = (u32) configspace + (1 << (13 + dev)) + (func << 8) + where; ++ if (size == 1) ++ addr ^= 0x3; ++ else if (size == 2) ++ addr ^= 0x2; ++ ++ if (write) { ++ value = *ptr; ++ if (size == 1) ++ err = put_dbe(value, (u8 *) addr); ++ else if (size == 2) ++ err = put_dbe(value, (u16 *) addr); ++ else if (size == 4) ++ err = put_dbe(value, (u32 *) addr); ++ } else { ++ if (size == 1) ++ err = get_dbe(value, (u8 *) addr); ++ else if (size == 2) ++ err = get_dbe(value, (u16 *) addr); ++ else if (size == 4) ++ err = get_dbe(value, (u32 *) addr); ++ if (err) ++ *ptr = 0xffffffff; ++ else ++ *ptr = value; ++ } ++ ++ /* Select Memory access */ ++ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_CFG_SEL, 0); ++ local_irq_restore(flags); ++ ++ return (err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL); ++} ++ ++static int ar231x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * value) ++{ ++ return config_access(devfn, where, size, value, 0); ++} ++ ++static int ar231x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value) ++{ ++ return config_access(devfn, where, size, &value, 1); ++} ++ ++struct pci_ops ar231x_pci_ops = { ++ .read = ar231x_pci_read, ++ .write = ar231x_pci_write, ++}; ++ ++static struct resource ar231x_mem_resource = { ++ .name = "AR531x PCI MEM", ++ .start = AR531X_MEM_BASE, ++ .end = AR531X_MEM_BASE + AR531X_MEM_SIZE - AR531X_IO_SIZE - 1 + 0x4000000, ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct resource ar231x_io_resource = { ++ .name = "AR531x PCI I/O", ++ .start = AR531X_MEM_BASE + AR531X_MEM_SIZE - AR531X_IO_SIZE, ++ .end = AR531X_MEM_BASE + AR531X_MEM_SIZE - 1, ++ .flags = IORESOURCE_IO, ++}; ++ ++struct pci_controller ar231x_pci_controller = { ++ .pci_ops = &ar231x_pci_ops, ++ .mem_resource = &ar231x_mem_resource, ++ .io_resource = &ar231x_io_resource, ++ .mem_offset = 0x00000000UL, ++ .io_offset = 0x00000000UL, ++}; ++ ++int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++{ ++ return AR2315_IRQ_LCBUS_PCI; ++} ++ ++int pcibios_plat_dev_init(struct pci_dev *dev) ++{ ++ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 5); ++ pci_write_config_word(dev, 0x40, 0); ++ ++ /* Clear any pending Abort or external Interrupts ++ * and enable interrupt processing */ ++ ar231x_mask_reg(AR2315_PCI_INTEN_REG, AR2315_PCI_INT_ENABLE, 0); ++ ar231x_write_reg(AR2315_PCI_INT_STATUS, (AR2315_PCI_ABORT_INT | AR2315_PCI_EXT_INT)); ++ ar231x_write_reg(AR2315_PCI_INT_MASK, (AR2315_PCI_ABORT_INT | AR2315_PCI_EXT_INT)); ++ ar231x_mask_reg(AR2315_PCI_INTEN_REG, 0, AR2315_PCI_INT_ENABLE); ++ ++ return 0; ++} ++ ++static void ++ar2315_pci_fixup(struct pci_dev *dev) ++{ ++ unsigned int devfn = dev->devfn; ++ ++ if (dev->bus->number != 0) ++ return; ++ ++ /* Only fix up the PCI host settings */ ++ if ((PCI_SLOT(devfn) != 3) || (PCI_FUNC(devfn) != 0)) ++ return; ++ ++ /* Fix up MBARs */ ++ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, HOST_PCI_MBAR0); ++ pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, HOST_PCI_MBAR1); ++ pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, HOST_PCI_MBAR2); ++ pci_write_config_dword(dev, PCI_COMMAND, ++ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL | ++ PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | ++ PCI_COMMAND_FAST_BACK); ++} ++DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, ar2315_pci_fixup); ++ ++static int __init ++ar2315_pci_init(void) ++{ ++ u32 reg; ++ ++ if (ar231x_devtype != DEV_TYPE_AR2315) ++ return -ENODEV; ++ ++ configspace = (unsigned long) ioremap_nocache(0x80000000, 1*1024*1024); /* Remap PCI config space */ ++ ar231x_pci_controller.io_map_base = ++ (unsigned long) ioremap_nocache(AR531X_MEM_BASE + AR531X_MEM_SIZE, AR531X_IO_SIZE); ++ set_io_port_base(ar231x_pci_controller.io_map_base); /* PCI I/O space */ ++ ++ reg = ar231x_mask_reg(AR2315_RESET, 0, AR2315_RESET_PCIDMA); ++ msleep(10); ++ ++ reg &= ~AR2315_RESET_PCIDMA; ++ ar231x_write_reg(AR2315_RESET, reg); ++ msleep(10); ++ ++ ar231x_mask_reg(AR2315_ENDIAN_CTL, 0, ++ AR2315_CONFIG_PCIAHB | AR2315_CONFIG_PCIAHB_BRIDGE); ++ ++ ar231x_write_reg(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM | ++ (AR2315_PCICLK_IN_FREQ_DIV_6 << AR2315_PCICLK_DIV_S)); ++ ar231x_mask_reg(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI); ++ ar231x_mask_reg(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK | AR2315_IF_MASK, ++ AR2315_IF_PCI | AR2315_IF_PCI_HOST | AR2315_IF_PCI_INTR | ++ (AR2315_IF_PCI_CLK_OUTPUT_CLK << AR2315_IF_PCI_CLK_SHIFT)); ++ ++ /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */ ++ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE, ++ AR2315_PCIRST_LOW); ++ msleep(100); ++ ++ /* Bring the PCI out of reset */ ++ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE, ++ AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8); ++ ++ ar231x_write_reg(AR2315_PCI_UNCACHE_CFG, ++ 0x1E | /* 1GB uncached */ ++ (1 << 5) | /* Enable uncached */ ++ (0x2 << 30) /* Base: 0x80000000 */ ++ ); ++ ar231x_read_reg(AR2315_PCI_UNCACHE_CFG); ++ ++ msleep(500); ++ ++ /* dirty hack - anyone with a datasheet that knows the memory map ? */ ++ ioport_resource.start = 0x10000000; ++ ioport_resource.end = 0xffffffff; ++ iomem_resource.start = 0x10000000; ++ iomem_resource.end = 0xffffffff; ++ ++ register_pci_controller(&ar231x_pci_controller); ++ ++ return 0; ++} ++ ++arch_initcall(ar2315_pci_init); +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/prom.c linux-2.6.39-rc7/arch/mips/ar231x/prom.c +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/prom.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/prom.c 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,37 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright MontaVista Software Inc ++ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. ++ * Copyright (C) 2006 FON Technology, SL. ++ * Copyright (C) 2006 Imre Kaloz ++ * Copyright (C) 2006 Felix Fietkau ++ */ ++ ++/* ++ * Prom setup file for ar531x ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include "ar5312.h" ++#include "ar2315.h" ++ ++void __init prom_init(void) ++{ ++ ar5312_prom_init(); ++ ar2315_prom_init(); ++} ++ ++void __init prom_free_prom_memory(void) ++{ ++} +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/reset.c linux-2.6.39-rc7/arch/mips/ar231x/reset.c +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/reset.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/reset.c 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,161 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "devices.h" ++ ++#define AR531X_RESET_GPIO_IRQ (AR531X_GPIO_IRQ(ar231x_board.config->resetConfigGpio)) ++ ++struct event_t { ++ struct work_struct wq; ++ int set; ++ unsigned long jiffies; ++}; ++ ++static struct timer_list rst_button_timer; ++static unsigned long seen; ++ ++struct sock *uevent_sock = NULL; ++EXPORT_SYMBOL_GPL(uevent_sock); ++extern u64 uevent_next_seqnum(void); ++ ++static int no_release_workaround = 1; ++module_param(no_release_workaround, int, 0); ++ ++static inline void ++add_msg(struct sk_buff *skb, char *msg) ++{ ++ char *scratch; ++ scratch = skb_put(skb, strlen(msg) + 1); ++ sprintf(scratch, msg); ++} ++ ++static void ++hotplug_button(struct work_struct *wq) ++{ ++ struct sk_buff *skb; ++ struct event_t *event; ++ size_t len; ++ char *scratch, *s; ++ char buf[128]; ++ ++ event = container_of(wq, struct event_t, wq); ++ if (!uevent_sock) ++ goto done; ++ ++ /* allocate message with the maximum possible size */ ++ s = event->set ? "pressed" : "released"; ++ len = strlen(s) + 2; ++ skb = alloc_skb(NLMSG_GOODSIZE, GFP_KERNEL); ++ if (!skb) ++ goto done; ++ ++ /* add header */ ++ scratch = skb_put(skb, len); ++ sprintf(scratch, "%s@",s); ++ ++ /* copy keys to our continuous event payload buffer */ ++ add_msg(skb, "HOME=/"); ++ add_msg(skb, "PATH=/sbin:/bin:/usr/sbin:/usr/bin"); ++ add_msg(skb, "SUBSYSTEM=button"); ++ add_msg(skb, "BUTTON=reset"); ++ add_msg(skb, (event->set ? "ACTION=pressed" : "ACTION=released")); ++ sprintf(buf, "SEEN=%ld", (event->jiffies - seen)/HZ); ++ add_msg(skb, buf); ++ snprintf(buf, 128, "SEQNUM=%llu", uevent_next_seqnum()); ++ add_msg(skb, buf); ++ ++ NETLINK_CB(skb).dst_group = 1; ++ netlink_broadcast(uevent_sock, skb, 0, 1, GFP_KERNEL); ++ ++done: ++ kfree(event); ++} ++ ++static void ++reset_button_poll(unsigned long unused) ++{ ++ struct event_t *event; ++ int gpio = ~0; ++ ++ if(!no_release_workaround) ++ return; ++ ++ gpio = ar231x_gpiodev->get(); ++ gpio &= (1 << (AR531X_RESET_GPIO_IRQ - AR531X_GPIO_IRQ_BASE)); ++ if(gpio) { ++ rst_button_timer.expires = jiffies + (HZ / 4); ++ add_timer(&rst_button_timer); ++ return; ++ } ++ ++ event = (struct event_t *) kzalloc(sizeof(struct event_t), GFP_ATOMIC); ++ if (!event) ++ return; ++ ++ event->set = 0; ++ event->jiffies = jiffies; ++ INIT_WORK(&event->wq, hotplug_button); ++ schedule_work(&event->wq); ++} ++ ++static irqreturn_t ++button_handler(int irq, void *dev_id) ++{ ++ static int pressed = 0; ++ struct event_t *event; ++ u32 gpio = ~0; ++ ++ event = (struct event_t *) kzalloc(sizeof(struct event_t), GFP_ATOMIC); ++ if (!event) ++ return IRQ_NONE; ++ ++ pressed = !pressed; ++ ++ gpio = ar231x_gpiodev->get() & (1 << (irq - AR531X_GPIO_IRQ_BASE)); ++ ++ event->set = gpio; ++ if(!event->set) ++ no_release_workaround = 0; ++ ++ event->jiffies = jiffies; ++ ++ INIT_WORK(&event->wq, hotplug_button); ++ schedule_work(&event->wq); ++ ++ seen = jiffies; ++ if(event->set && no_release_workaround) ++ mod_timer(&rst_button_timer, jiffies + (HZ / 4)); ++ ++ return IRQ_HANDLED; ++} ++ ++ ++static int __init ++ar231x_init_reset(void) ++{ ++ seen = jiffies; ++ ++ if (ar231x_board.config->resetConfigGpio == 0xffff) ++ return -ENODEV; ++ ++ init_timer(&rst_button_timer); ++ rst_button_timer.function = reset_button_poll; ++ rst_button_timer.expires = jiffies + HZ / 50; ++ add_timer(&rst_button_timer); ++ ++ request_irq(AR531X_RESET_GPIO_IRQ, &button_handler, IRQF_SAMPLE_RANDOM, "ar231x_reset", NULL); ++ ++ return 0; ++} ++ ++module_init(ar231x_init_reset); +diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar2315_regs.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar2315_regs.h +--- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar2315_regs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar2315_regs.h 2011-05-15 21:44:12.000000000 +0200 +@@ -0,0 +1,580 @@ ++/* ++ * Register definitions for AR2315+ ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. ++ * Copyright (C) 2006 FON Technology, SL. ++ * Copyright (C) 2006 Imre Kaloz ++ * Copyright (C) 2006-2008 Felix Fietkau ++ */ ++ ++#ifndef __AR2315_REG_H ++#define __AR2315_REG_H ++ ++/* ++ * IRQs ++ */ ++#define AR2315_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */ ++#define AR2315_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */ ++#define AR2315_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */ ++#define AR2315_IRQ_LCBUS_PCI MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */ ++#define AR2315_IRQ_WLAN0_POLL MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */ ++ ++/* ++ * Address map ++ */ ++#define AR2315_SPI_READ 0x08000000 /* SPI FLASH */ ++#define AR2315_WLAN0 0x10000000 /* Wireless MMR */ ++#define AR2315_PCI 0x10100000 /* PCI MMR */ ++#define AR2315_SDRAMCTL 0x10300000 /* SDRAM MMR */ ++#define AR2315_LOCAL 0x10400000 /* LOCAL BUS MMR */ ++#define AR2315_ENET0 0x10500000 /* ETHERNET MMR */ ++#define AR2315_DSLBASE 0x11000000 /* RESET CONTROL MMR */ ++#define AR2315_UART0 0x11100003 /* UART MMR */ ++#define AR2315_SPI 0x11300000 /* SPI FLASH MMR */ ++#define AR2315_PCIEXT 0x80000000 /* pci external */ ++ ++/* ++ * Reset Register ++ */ ++#define AR2315_COLD_RESET (AR2315_DSLBASE + 0x0000) ++ ++#define AR2315_RESET_COLD_AHB 0x00000001 ++#define AR2315_RESET_COLD_APB 0x00000002 ++#define AR2315_RESET_COLD_CPU 0x00000004 ++#define AR2315_RESET_COLD_CPUWARM 0x00000008 ++#define AR2315_RESET_SYSTEM (RESET_COLD_CPU | RESET_COLD_APB | RESET_COLD_AHB) /* full system */ ++#define AR2317_RESET_SYSTEM 0x00000010 ++ ++ ++#define AR2315_RESET (AR2315_DSLBASE + 0x0004) ++ ++#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001 /* warm reset WLAN0 MAC */ ++#define AR2315_RESET_WARM_WLAN0_BB 0x00000002 /* warm reset WLAN0 BaseBand */ ++#define AR2315_RESET_MPEGTS_RSVD 0x00000004 /* warm reset MPEG-TS */ ++#define AR2315_RESET_PCIDMA 0x00000008 /* warm reset PCI ahb/dma */ ++#define AR2315_RESET_MEMCTL 0x00000010 /* warm reset memory controller */ ++#define AR2315_RESET_LOCAL 0x00000020 /* warm reset local bus */ ++#define AR2315_RESET_I2C_RSVD 0x00000040 /* warm reset I2C bus */ ++#define AR2315_RESET_SPI 0x00000080 /* warm reset SPI interface */ ++#define AR2315_RESET_UART0 0x00000100 /* warm reset UART0 */ ++#define AR2315_RESET_IR_RSVD 0x00000200 /* warm reset IR interface */ ++#define AR2315_RESET_EPHY0 0x00000400 /* cold reset ENET0 phy */ ++#define AR2315_RESET_ENET0 0x00000800 /* cold reset ENET0 mac */ ++ ++/* ++ * AHB master arbitration control ++ */ ++#define AR2315_AHB_ARB_CTL (AR2315_DSLBASE + 0x0008) ++ ++#define AR2315_ARB_CPU 0x00000001 /* CPU, default */ ++#define AR2315_ARB_WLAN 0x00000002 /* WLAN */ ++#define AR2315_ARB_MPEGTS_RSVD 0x00000004 /* MPEG-TS */ ++#define AR2315_ARB_LOCAL 0x00000008 /* LOCAL */ ++#define AR2315_ARB_PCI 0x00000010 /* PCI */ ++#define AR2315_ARB_ETHERNET 0x00000020 /* Ethernet */ ++#define AR2315_ARB_RETRY 0x00000100 /* retry policy, debug only */ ++ ++/* ++ * Config Register ++ */ ++#define AR2315_ENDIAN_CTL (AR2315_DSLBASE + 0x000c) ++ ++#define AR2315_CONFIG_AHB 0x00000001 /* EC - AHB bridge endianess */ ++#define AR2315_CONFIG_WLAN 0x00000002 /* WLAN byteswap */ ++#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004 /* MPEG-TS byteswap */ ++#define AR2315_CONFIG_PCI 0x00000008 /* PCI byteswap */ ++#define AR2315_CONFIG_MEMCTL 0x00000010 /* Memory controller endianess */ ++#define AR2315_CONFIG_LOCAL 0x00000020 /* Local bus byteswap */ ++#define AR2315_CONFIG_ETHERNET 0x00000040 /* Ethernet byteswap */ ++ ++#define AR2315_CONFIG_MERGE 0x00000200 /* CPU write buffer merge */ ++#define AR2315_CONFIG_CPU 0x00000400 /* CPU big endian */ ++#define AR2315_CONFIG_PCIAHB 0x00000800 ++#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000 ++#define AR2315_CONFIG_SPI 0x00008000 /* SPI byteswap */ ++#define AR2315_CONFIG_CPU_DRAM 0x00010000 ++#define AR2315_CONFIG_CPU_PCI 0x00020000 ++#define AR2315_CONFIG_CPU_MMR 0x00040000 ++#define AR2315_CONFIG_BIG 0x00000400 ++ ++ ++/* ++ * NMI control ++ */ ++#define AR2315_NMI_CTL (AR2315_DSLBASE + 0x0010) ++ ++#define AR2315_NMI_EN 1 ++ ++/* ++ * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR531X 1.0). ++ */ ++#define AR2315_SREV (AR2315_DSLBASE + 0x0014) ++ ++#define AR2315_REV_MAJ 0x00f0 ++#define AR2315_REV_MAJ_S 4 ++#define AR2315_REV_MIN 0x000f ++#define AR2315_REV_MIN_S 0 ++#define AR2315_REV_CHIP (AR2315_REV_MAJ|AR2315_REV_MIN) ++ ++/* ++ * Interface Enable ++ */ ++#define AR2315_IF_CTL (AR2315_DSLBASE + 0x0018) ++ ++#define AR2315_IF_MASK 0x00000007 ++#define AR2315_IF_DISABLED 0 ++#define AR2315_IF_PCI 1 ++#define AR2315_IF_TS_LOCAL 2 ++#define AR2315_IF_ALL 3 /* only for emulation with separate pins */ ++#define AR2315_IF_LOCAL_HOST 0x00000008 ++#define AR2315_IF_PCI_HOST 0x00000010 ++#define AR2315_IF_PCI_INTR 0x00000020 ++#define AR2315_IF_PCI_CLK_MASK 0x00030000 ++#define AR2315_IF_PCI_CLK_INPUT 0 ++#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1 ++#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2 ++#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3 ++#define AR2315_IF_PCI_CLK_SHIFT 16 ++ ++/* ++ * APB Interrupt control ++ */ ++ ++#define AR2315_ISR (AR2315_DSLBASE + 0x0020) ++#define AR2315_IMR (AR2315_DSLBASE + 0x0024) ++#define AR2315_GISR (AR2315_DSLBASE + 0x0028) ++ ++#define AR2315_ISR_UART0 0x0001 /* high speed UART */ ++#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */ ++#define AR2315_ISR_SPI 0x0004 /* SPI bus */ ++#define AR2315_ISR_AHB 0x0008 /* AHB error */ ++#define AR2315_ISR_APB 0x0010 /* APB error */ ++#define AR2315_ISR_TIMER 0x0020 /* timer */ ++#define AR2315_ISR_GPIO 0x0040 /* GPIO */ ++#define AR2315_ISR_WD 0x0080 /* watchdog */ ++#define AR2315_ISR_IR_RSVD 0x0100 /* IR */ ++ ++#define AR2315_GISR_MISC 0x0001 ++#define AR2315_GISR_WLAN0 0x0002 ++#define AR2315_GISR_MPEGTS_RSVD 0x0004 ++#define AR2315_GISR_LOCALPCI 0x0008 ++#define AR2315_GISR_WMACPOLL 0x0010 ++#define AR2315_GISR_TIMER 0x0020 ++#define AR2315_GISR_ETHERNET 0x0040 ++ ++/* ++ * Interrupt routing from IO to the processor IP bits ++ * Define our inter mask and level ++ */ ++#define AR2315_INTR_MISCIO SR_IBIT3 ++#define AR2315_INTR_WLAN0 SR_IBIT4 ++#define AR2315_INTR_ENET0 SR_IBIT5 ++#define AR2315_INTR_LOCALPCI SR_IBIT6 ++#define AR2315_INTR_WMACPOLL SR_IBIT7 ++#define AR2315_INTR_COMPARE SR_IBIT8 ++ ++/* ++ * Timers ++ */ ++#define AR2315_TIMER (AR2315_DSLBASE + 0x0030) ++#define AR2315_RELOAD (AR2315_DSLBASE + 0x0034) ++#define AR2315_WD (AR2315_DSLBASE + 0x0038) ++#define AR2315_WDC (AR2315_DSLBASE + 0x003c) ++ ++#define AR2315_WDC_IGNORE_EXPIRATION 0x00000000 ++#define AR2315_WDC_NMI 0x00000001 /* NMI on watchdog */ ++#define AR2315_WDC_RESET 0x00000002 /* reset on watchdog */ ++ ++/* ++ * CPU Performance Counters ++ */ ++#define AR2315_PERFCNT0 (AR2315_DSLBASE + 0x0048) ++#define AR2315_PERFCNT1 (AR2315_DSLBASE + 0x004c) ++ ++#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */ ++#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */ ++#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */ ++#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */ ++#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */ ++#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */ ++#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */ ++ ++#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */ ++#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */ ++#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */ ++#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */ ++#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */ ++#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */ ++#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */ ++ ++/* ++ * AHB Error Reporting. ++ */ ++#define AR2315_AHB_ERR0 (AR2315_DSLBASE + 0x0050) /* error */ ++#define AR2315_AHB_ERR1 (AR2315_DSLBASE + 0x0054) /* haddr */ ++#define AR2315_AHB_ERR2 (AR2315_DSLBASE + 0x0058) /* hwdata */ ++#define AR2315_AHB_ERR3 (AR2315_DSLBASE + 0x005c) /* hrdata */ ++#define AR2315_AHB_ERR4 (AR2315_DSLBASE + 0x0060) /* status */ ++ ++#define AHB_ERROR_DET 1 /* AHB Error has been detected, */ ++ /* write 1 to clear all bits in ERR0 */ ++#define AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */ ++#define AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */ ++ ++#define AR2315_PROCERR_HMAST 0x0000000f ++#define AR2315_PROCERR_HMAST_DFLT 0 ++#define AR2315_PROCERR_HMAST_WMAC 1 ++#define AR2315_PROCERR_HMAST_ENET 2 ++#define AR2315_PROCERR_HMAST_PCIENDPT 3 ++#define AR2315_PROCERR_HMAST_LOCAL 4 ++#define AR2315_PROCERR_HMAST_CPU 5 ++#define AR2315_PROCERR_HMAST_PCITGT 6 ++ ++#define AR2315_PROCERR_HMAST_S 0 ++#define AR2315_PROCERR_HWRITE 0x00000010 ++#define AR2315_PROCERR_HSIZE 0x00000060 ++#define AR2315_PROCERR_HSIZE_S 5 ++#define AR2315_PROCERR_HTRANS 0x00000180 ++#define AR2315_PROCERR_HTRANS_S 7 ++#define AR2315_PROCERR_HBURST 0x00000e00 ++#define AR2315_PROCERR_HBURST_S 9 ++ ++/* ++ * Clock Control ++ */ ++#define AR2315_PLLC_CTL (AR2315_DSLBASE + 0x0064) ++#define AR2315_PLLV_CTL (AR2315_DSLBASE + 0x0068) ++#define AR2315_CPUCLK (AR2315_DSLBASE + 0x006c) ++#define AR2315_AMBACLK (AR2315_DSLBASE + 0x0070) ++#define AR2315_SYNCCLK (AR2315_DSLBASE + 0x0074) ++#define AR2315_DSL_SLEEP_CTL (AR2315_DSLBASE + 0x0080) ++#define AR2315_DSL_SLEEP_DUR (AR2315_DSLBASE + 0x0084) ++ ++/* PLLc Control fields */ ++#define PLLC_REF_DIV_M 0x00000003 ++#define PLLC_REF_DIV_S 0 ++#define PLLC_FDBACK_DIV_M 0x0000007C ++#define PLLC_FDBACK_DIV_S 2 ++#define PLLC_ADD_FDBACK_DIV_M 0x00000080 ++#define PLLC_ADD_FDBACK_DIV_S 7 ++#define PLLC_CLKC_DIV_M 0x0001c000 ++#define PLLC_CLKC_DIV_S 14 ++#define PLLC_CLKM_DIV_M 0x00700000 ++#define PLLC_CLKM_DIV_S 20 ++ ++/* CPU CLK Control fields */ ++#define CPUCLK_CLK_SEL_M 0x00000003 ++#define CPUCLK_CLK_SEL_S 0 ++#define CPUCLK_CLK_DIV_M 0x0000000c ++#define CPUCLK_CLK_DIV_S 2 ++ ++/* AMBA CLK Control fields */ ++#define AMBACLK_CLK_SEL_M 0x00000003 ++#define AMBACLK_CLK_SEL_S 0 ++#define AMBACLK_CLK_DIV_M 0x0000000c ++#define AMBACLK_CLK_DIV_S 2 ++ ++/* ++ * GPIO ++ */ ++#define AR2315_GPIO_DI (AR2315_DSLBASE + 0x0088) ++#define AR2315_GPIO_DO (AR2315_DSLBASE + 0x0090) ++#define AR2315_GPIO_CR (AR2315_DSLBASE + 0x0098) ++#define AR2315_GPIO_INT (AR2315_DSLBASE + 0x00a0) ++ ++#define AR2315_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */ ++#define AR2315_GPIO_CR_O(x) (1 << (x)) /* output */ ++#define AR2315_GPIO_CR_I(x) (0) /* input */ ++ ++#define AR2315_GPIO_INT_S(x) (x) /* interrupt enable */ ++#define AR2315_GPIO_INT_M (0x3F) /* mask for int */ ++#define AR2315_GPIO_INT_LVL(x) ((x) << 6) /* interrupt level */ ++#define AR2315_GPIO_INT_LVL_M ((0x3) << 6) /* mask for int level */ ++ ++#define AR2315_GPIO_INT_MAX_Y 1 /* Maximum value of Y for AR5313_GPIO_INT_* macros */ ++#define AR2315_GPIO_INT_LVL_OFF 0 /* Triggerring off */ ++#define AR2315_GPIO_INT_LVL_LOW 1 /* Low Level Triggered */ ++#define AR2315_GPIO_INT_LVL_HIGH 2 /* High Level Triggered */ ++#define AR2315_GPIO_INT_LVL_EDGE 3 /* Edge Triggered */ ++ ++#define AR2315_RESET_GPIO 5 ++#define AR2315_NUM_GPIO 22 ++ ++/* ++ * PCI Clock Control ++ */ ++#define AR2315_PCICLK (AR2315_DSLBASE + 0x00a4) ++ ++#define AR2315_PCICLK_INPUT_M 0x3 ++#define AR2315_PCICLK_INPUT_S 0 ++ ++#define AR2315_PCICLK_PLLC_CLKM 0 ++#define AR2315_PCICLK_PLLC_CLKM1 1 ++#define AR2315_PCICLK_PLLC_CLKC 2 ++#define AR2315_PCICLK_REF_CLK 3 ++ ++#define AR2315_PCICLK_DIV_M 0xc ++#define AR2315_PCICLK_DIV_S 2 ++ ++#define AR2315_PCICLK_IN_FREQ 0 ++#define AR2315_PCICLK_IN_FREQ_DIV_6 1 ++#define AR2315_PCICLK_IN_FREQ_DIV_8 2 ++#define AR2315_PCICLK_IN_FREQ_DIV_10 3 ++ ++/* ++ * Observation Control Register ++ */ ++#define AR2315_OCR (AR2315_DSLBASE + 0x00b0) ++#define OCR_GPIO0_IRIN 0x0040 ++#define OCR_GPIO1_IROUT 0x0080 ++#define OCR_GPIO3_RXCLR 0x0200 ++ ++/* ++ * General Clock Control ++ */ ++ ++#define AR2315_MISCCLK (AR2315_DSLBASE + 0x00b4) ++#define MISCCLK_PLLBYPASS_EN 0x00000001 ++#define MISCCLK_PROCREFCLK 0x00000002 ++ ++/* ++ * SDRAM Controller ++ * - No read or write buffers are included. ++ */ ++#define AR2315_MEM_CFG (AR2315_SDRAMCTL + 0x00) ++#define AR2315_MEM_CTRL (AR2315_SDRAMCTL + 0x0c) ++#define AR2315_MEM_REF (AR2315_SDRAMCTL + 0x10) ++ ++#define SDRAM_DATA_WIDTH_M 0x00006000 ++#define SDRAM_DATA_WIDTH_S 13 ++ ++#define SDRAM_COL_WIDTH_M 0x00001E00 ++#define SDRAM_COL_WIDTH_S 9 ++ ++#define SDRAM_ROW_WIDTH_M 0x000001E0 ++#define SDRAM_ROW_WIDTH_S 5 ++ ++#define SDRAM_BANKADDR_BITS_M 0x00000018 ++#define SDRAM_BANKADDR_BITS_S 3 ++ ++/* ++ * SPI Flash Interface Registers ++ */ ++ ++#define AR2315_SPI_CTL (AR2315_SPI + 0x00) ++#define AR2315_SPI_OPCODE (AR2315_SPI + 0x04) ++#define AR2315_SPI_DATA (AR2315_SPI + 0x08) ++ ++#define SPI_CTL_START 0x00000100 ++#define SPI_CTL_BUSY 0x00010000 ++#define SPI_CTL_TXCNT_MASK 0x0000000f ++#define SPI_CTL_RXCNT_MASK 0x000000f0 ++#define SPI_CTL_TX_RX_CNT_MASK 0x000000ff ++#define SPI_CTL_SIZE_MASK 0x00060000 ++ ++#define SPI_CTL_CLK_SEL_MASK 0x03000000 ++#define SPI_OPCODE_MASK 0x000000ff ++ ++/* ++ * PCI Bus Interface Registers ++ */ ++#define AR2315_PCI_1MS_REG (AR2315_PCI + 0x0008) ++#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */ ++ ++#define AR2315_PCI_MISC_CONFIG (AR2315_PCI + 0x000c) ++#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */ ++#define AR2315_PCIMISC_CFG_SEL 0x00000002 /* mem or config cycles */ ++#define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */ ++#define AR2315_PCIMISC_RST_MODE 0x00000030 ++#define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */ ++#define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */ ++#define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */ ++#define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */ ++#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */ ++#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */ ++#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */ ++#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache disable */ ++ ++#define AR2315_PCI_OUT_TSTAMP (AR2315_PCI + 0x0010) ++ ++#define AR2315_PCI_UNCACHE_CFG (AR2315_PCI + 0x0014) ++ ++#define AR2315_PCI_IN_EN (AR2315_PCI + 0x0100) ++#define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */ ++#define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */ ++#define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */ ++#define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */ ++ ++#define AR2315_PCI_IN_DIS (AR2315_PCI + 0x0104) ++#define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */ ++#define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */ ++#define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */ ++#define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */ ++ ++#define AR2315_PCI_IN_PTR (AR2315_PCI + 0x0200) ++ ++#define AR2315_PCI_OUT_EN (AR2315_PCI + 0x0400) ++#define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */ ++ ++#define AR2315_PCI_OUT_DIS (AR2315_PCI + 0x0404) ++#define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */ ++ ++#define AR2315_PCI_OUT_PTR (AR2315_PCI + 0x0408) ++ ++#define AR2315_PCI_INT_STATUS (AR2315_PCI + 0x0500) /* write one to clr */ ++#define AR2315_PCI_TXINT 0x00000001 /* Desc In Completed */ ++#define AR2315_PCI_TXOK 0x00000002 /* Desc In OK */ ++#define AR2315_PCI_TXERR 0x00000004 /* Desc In ERR */ ++#define AR2315_PCI_TXEOL 0x00000008 /* Desc In End-of-List */ ++#define AR2315_PCI_RXINT 0x00000010 /* Desc Out Completed */ ++#define AR2315_PCI_RXOK 0x00000020 /* Desc Out OK */ ++#define AR2315_PCI_RXERR 0x00000040 /* Desc Out ERR */ ++#define AR2315_PCI_RXEOL 0x00000080 /* Desc Out EOL */ ++#define AR2315_PCI_TXOOD 0x00000200 /* Desc In Out-of-Desc */ ++#define AR2315_PCI_MASK 0x0000FFFF /* Desc Mask */ ++#define AR2315_PCI_EXT_INT 0x02000000 ++#define AR2315_PCI_ABORT_INT 0x04000000 ++ ++#define AR2315_PCI_INT_MASK (AR2315_PCI + 0x0504) /* same as INT_STATUS */ ++ ++#define AR2315_PCI_INTEN_REG (AR2315_PCI + 0x0508) ++#define AR2315_PCI_INT_DISABLE 0x00 /* disable pci interrupts */ ++#define AR2315_PCI_INT_ENABLE 0x01 /* enable pci interrupts */ ++ ++#define AR2315_PCI_HOST_IN_EN (AR2315_PCI + 0x0800) ++#define AR2315_PCI_HOST_IN_DIS (AR2315_PCI + 0x0804) ++#define AR2315_PCI_HOST_IN_PTR (AR2315_PCI + 0x0810) ++#define AR2315_PCI_HOST_OUT_EN (AR2315_PCI + 0x0900) ++#define AR2315_PCI_HOST_OUT_DIS (AR2315_PCI + 0x0904) ++#define AR2315_PCI_HOST_OUT_PTR (AR2315_PCI + 0x0908) ++ ++ ++/* ++ * Local Bus Interface Registers ++ */ ++#define AR2315_LB_CONFIG (AR2315_LOCAL + 0x0000) ++#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */ ++#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */ ++#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */ ++#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */ ++#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */ ++#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */ ++#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */ ++#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */ ++#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */ ++#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */ ++#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */ ++#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */ ++#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */ ++#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */ ++#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */ ++#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */ ++#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */ ++#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */ ++#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */ ++#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */ ++#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */ ++#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */ ++#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */ ++#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */ ++#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */ ++ ++#define AR2315_LB_CLKSEL (AR2315_LOCAL + 0x0004) ++#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */ ++ ++#define AR2315_LB_1MS (AR2315_LOCAL + 0x0008) ++#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */ ++ ++#define AR2315_LB_MISCCFG (AR2315_LOCAL + 0x000C) ++#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */ ++#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */ ++#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */ ++#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */ ++#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */ ++#define AR2315_LBM_TIMEOUT_MASK 0x00FFFF80 ++#define AR2315_LBM_TIMEOUT_SHFT 7 ++#define AR2315_LBM_PORTMUX 0x07000000 ++ ++ ++#define AR2315_LB_RXTSOFF (AR2315_LOCAL + 0x0010) ++ ++#define AR2315_LB_TX_CHAIN_EN (AR2315_LOCAL + 0x0100) ++#define AR2315_LB_TXEN_0 0x01 ++#define AR2315_LB_TXEN_1 0x02 ++#define AR2315_LB_TXEN_2 0x04 ++#define AR2315_LB_TXEN_3 0x08 ++ ++#define AR2315_LB_TX_CHAIN_DIS (AR2315_LOCAL + 0x0104) ++#define AR2315_LB_TX_DESC_PTR (AR2315_LOCAL + 0x0200) ++ ++#define AR2315_LB_RX_CHAIN_EN (AR2315_LOCAL + 0x0400) ++#define AR2315_LB_RXEN 0x01 ++ ++#define AR2315_LB_RX_CHAIN_DIS (AR2315_LOCAL + 0x0404) ++#define AR2315_LB_RX_DESC_PTR (AR2315_LOCAL + 0x0408) ++ ++#define AR2315_LB_INT_STATUS (AR2315_LOCAL + 0x0500) ++#define AR2315_INT_TX_DESC 0x0001 ++#define AR2315_INT_TX_OK 0x0002 ++#define AR2315_INT_TX_ERR 0x0004 ++#define AR2315_INT_TX_EOF 0x0008 ++#define AR2315_INT_RX_DESC 0x0010 ++#define AR2315_INT_RX_OK 0x0020 ++#define AR2315_INT_RX_ERR 0x0040 ++#define AR2315_INT_RX_EOF 0x0080 ++#define AR2315_INT_TX_TRUNC 0x0100 ++#define AR2315_INT_TX_STARVE 0x0200 ++#define AR2315_INT_LB_TIMEOUT 0x0400 ++#define AR2315_INT_LB_ERR 0x0800 ++#define AR2315_INT_MBOX_WR 0x1000 ++#define AR2315_INT_MBOX_RD 0x2000 ++ ++/* Bit definitions for INT MASK are the same as INT_STATUS */ ++#define AR2315_LB_INT_MASK (AR2315_LOCAL + 0x0504) ++ ++#define AR2315_LB_INT_EN (AR2315_LOCAL + 0x0508) ++#define AR2315_LB_MBOX (AR2315_LOCAL + 0x0600) ++ ++/* ++ * IR Interface Registers ++ */ ++#define AR2315_IR_PKTDATA (AR2315_IR + 0x0000) ++ ++#define AR2315_IR_PKTLEN (AR2315_IR + 0x07fc) /* 0 - 63 */ ++ ++#define AR2315_IR_CONTROL (AR2315_IR + 0x0800) ++#define AR2315_IRCTL_TX 0x00000000 /* use as tranmitter */ ++#define AR2315_IRCTL_RX 0x00000001 /* use as receiver */ ++#define AR2315_IRCTL_SAMPLECLK_MASK 0x00003ffe /* Sample clk divisor mask */ ++#define AR2315_IRCTL_SAMPLECLK_SHFT 1 ++#define AR2315_IRCTL_OUTPUTCLK_MASK 0x03ffc000 /* Output clk divisor mask */ ++#define AR2315_IRCTL_OUTPUTCLK_SHFT 14 ++ ++#define AR2315_IR_STATUS (AR2315_IR + 0x0804) ++#define AR2315_IRSTS_RX 0x00000001 /* receive in progress */ ++#define AR2315_IRSTS_TX 0x00000002 /* transmit in progress */ ++ ++#define AR2315_IR_CONFIG (AR2315_IR + 0x0808) ++#define AR2315_IRCFG_INVIN 0x00000001 /* invert input polarity */ ++#define AR2315_IRCFG_INVOUT 0x00000002 /* invert output polarity */ ++#define AR2315_IRCFG_SEQ_START_WIN_SEL 0x00000004 /* 1 => 28, 0 => 7 */ ++#define AR2315_IRCFG_SEQ_START_THRESH 0x000000f0 /* */ ++#define AR2315_IRCFG_SEQ_END_UNIT_SEL 0x00000100 /* */ ++#define AR2315_IRCFG_SEQ_END_UNIT_THRESH 0x00007e00 /* */ ++#define AR2315_IRCFG_SEQ_END_WIN_SEL 0x00008000 /* */ ++#define AR2315_IRCFG_SEQ_END_WIN_THRESH 0x001f0000 /* */ ++#define AR2315_IRCFG_NUM_BACKOFF_WORDS 0x01e00000 /* */ ++ ++#define HOST_PCI_DEV_ID 3 ++#define HOST_PCI_MBAR0 0x10000000 ++#define HOST_PCI_MBAR1 0x20000000 ++#define HOST_PCI_MBAR2 0x30000000 ++ ++#define HOST_PCI_SDRAM_BASEADDR HOST_PCI_MBAR1 ++#define PCI_DEVICE_MEM_SPACE 0x800000 ++ ++#endif /* __AR2315_REG_H */ +diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar2315_spiflash.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar2315_spiflash.h +--- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar2315_spiflash.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar2315_spiflash.h 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,116 @@ ++/* ++ * SPI Flash Memory support header file. ++ * ++ * Copyright (c) 2005, Atheros Communications Inc. ++ * Copyright (C) 2006 FON Technology, SL. ++ * Copyright (C) 2006 Imre Kaloz ++ * Copyright (C) 2006-2009 Felix Fietkau ++ * ++ * This code is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++#ifndef __AR2315_SPIFLASH_H ++#define __AR2315_SPIFLASH_H ++ ++#define STM_PAGE_SIZE 256 ++ ++#define SFI_WRITE_BUFFER_SIZE 4 ++#define SFI_FLASH_ADDR_MASK 0x00ffffff ++ ++#define STM_8MBIT_SIGNATURE 0x13 ++#define STM_M25P80_BYTE_COUNT 1048576 ++#define STM_M25P80_SECTOR_COUNT 16 ++#define STM_M25P80_SECTOR_SIZE 0x10000 ++ ++#define STM_16MBIT_SIGNATURE 0x14 ++#define STM_M25P16_BYTE_COUNT 2097152 ++#define STM_M25P16_SECTOR_COUNT 32 ++#define STM_M25P16_SECTOR_SIZE 0x10000 ++ ++#define STM_32MBIT_SIGNATURE 0x15 ++#define STM_M25P32_BYTE_COUNT 4194304 ++#define STM_M25P32_SECTOR_COUNT 64 ++#define STM_M25P32_SECTOR_SIZE 0x10000 ++ ++#define STM_64MBIT_SIGNATURE 0x16 ++#define STM_M25P64_BYTE_COUNT 8388608 ++#define STM_M25P64_SECTOR_COUNT 128 ++#define STM_M25P64_SECTOR_SIZE 0x10000 ++ ++#define STM_128MBIT_SIGNATURE 0x17 ++#define STM_M25P128_BYTE_COUNT 16777216 ++#define STM_M25P128_SECTOR_COUNT 256 ++#define STM_M25P128_SECTOR_SIZE 0x10000 ++ ++#define STM_1MB_BYTE_COUNT STM_M25P80_BYTE_COUNT ++#define STM_1MB_SECTOR_COUNT STM_M25P80_SECTOR_COUNT ++#define STM_1MB_SECTOR_SIZE STM_M25P80_SECTOR_SIZE ++#define STM_2MB_BYTE_COUNT STM_M25P16_BYTE_COUNT ++#define STM_2MB_SECTOR_COUNT STM_M25P16_SECTOR_COUNT ++#define STM_2MB_SECTOR_SIZE STM_M25P16_SECTOR_SIZE ++#define STM_4MB_BYTE_COUNT STM_M25P32_BYTE_COUNT ++#define STM_4MB_SECTOR_COUNT STM_M25P32_SECTOR_COUNT ++#define STM_4MB_SECTOR_SIZE STM_M25P32_SECTOR_SIZE ++#define STM_8MB_BYTE_COUNT STM_M25P64_BYTE_COUNT ++#define STM_8MB_SECTOR_COUNT STM_M25P64_SECTOR_COUNT ++#define STM_8MB_SECTOR_SIZE STM_M25P64_SECTOR_SIZE ++#define STM_16MB_BYTE_COUNT STM_M25P128_BYTE_COUNT ++#define STM_16MB_SECTOR_COUNT STM_M25P128_SECTOR_COUNT ++#define STM_16MB_SECTOR_SIZE STM_M25P128_SECTOR_SIZE ++ ++/* ++ * ST Microelectronics Opcodes for Serial Flash ++ */ ++ ++#define STM_OP_WR_ENABLE 0x06 /* Write Enable */ ++#define STM_OP_WR_DISABLE 0x04 /* Write Disable */ ++#define STM_OP_RD_STATUS 0x05 /* Read Status */ ++#define STM_OP_WR_STATUS 0x01 /* Write Status */ ++#define STM_OP_RD_DATA 0x03 /* Read Data */ ++#define STM_OP_FAST_RD_DATA 0x0b /* Fast Read Data */ ++#define STM_OP_PAGE_PGRM 0x02 /* Page Program */ ++#define STM_OP_SECTOR_ERASE 0xd8 /* Sector Erase */ ++#define STM_OP_BULK_ERASE 0xc7 /* Bulk Erase */ ++#define STM_OP_DEEP_PWRDOWN 0xb9 /* Deep Power-Down Mode */ ++#define STM_OP_RD_SIG 0xab /* Read Electronic Signature */ ++ ++#define STM_STATUS_WIP 0x01 /* Write-In-Progress */ ++#define STM_STATUS_WEL 0x02 /* Write Enable Latch */ ++#define STM_STATUS_BP0 0x04 /* Block Protect 0 */ ++#define STM_STATUS_BP1 0x08 /* Block Protect 1 */ ++#define STM_STATUS_BP2 0x10 /* Block Protect 2 */ ++#define STM_STATUS_SRWD 0x80 /* Status Register Write Disable */ ++ ++/* ++ * SPI Flash Interface Registers ++ */ ++#define AR531XPLUS_SPI_READ 0x08000000 ++#define AR531XPLUS_SPI_MMR 0x11300000 ++#define AR531XPLUS_SPI_MMR_SIZE 12 ++ ++#define AR531XPLUS_SPI_CTL 0x00 ++#define AR531XPLUS_SPI_OPCODE 0x04 ++#define AR531XPLUS_SPI_DATA 0x08 ++ ++#define SPI_FLASH_READ AR531XPLUS_SPI_READ ++#define SPI_FLASH_MMR AR531XPLUS_SPI_MMR ++#define SPI_FLASH_MMR_SIZE AR531XPLUS_SPI_MMR_SIZE ++#define SPI_FLASH_CTL AR531XPLUS_SPI_CTL ++#define SPI_FLASH_OPCODE AR531XPLUS_SPI_OPCODE ++#define SPI_FLASH_DATA AR531XPLUS_SPI_DATA ++ ++#define SPI_CTL_START 0x00000100 ++#define SPI_CTL_BUSY 0x00010000 ++#define SPI_CTL_TXCNT_MASK 0x0000000f ++#define SPI_CTL_RXCNT_MASK 0x000000f0 ++#define SPI_CTL_TX_RX_CNT_MASK 0x000000ff ++#define SPI_CTL_SIZE_MASK 0x00060000 ++ ++#define SPI_CTL_CLK_SEL_MASK 0x03000000 ++#define SPI_OPCODE_MASK 0x000000ff ++ ++#define SPI_STATUS_WIP STM_STATUS_WIP ++ ++#endif +diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar231x.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar231x.h +--- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar231x.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar231x.h 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,54 @@ ++#ifndef __AR531X_H ++#define __AR531X_H ++ ++#define AR531X_MISC_IRQ_BASE 0x20 ++#define AR531X_GPIO_IRQ_BASE 0x30 ++ ++/* Software's idea of interrupts handled by "CPU Interrupt Controller" */ ++#define AR531X_IRQ_NONE MIPS_CPU_IRQ_BASE+0 ++#define AR531X_IRQ_CPU_CLOCK MIPS_CPU_IRQ_BASE+7 /* C0_CAUSE: 0x8000 */ ++ ++/* Miscellaneous interrupts, which share IP6 */ ++#define AR531X_MISC_IRQ_NONE AR531X_MISC_IRQ_BASE+0 ++#define AR531X_MISC_IRQ_TIMER AR531X_MISC_IRQ_BASE+1 ++#define AR531X_MISC_IRQ_AHB_PROC AR531X_MISC_IRQ_BASE+2 ++#define AR531X_MISC_IRQ_AHB_DMA AR531X_MISC_IRQ_BASE+3 ++#define AR531X_MISC_IRQ_GPIO AR531X_MISC_IRQ_BASE+4 ++#define AR531X_MISC_IRQ_UART0 AR531X_MISC_IRQ_BASE+5 ++#define AR531X_MISC_IRQ_UART0_DMA AR531X_MISC_IRQ_BASE+6 ++#define AR531X_MISC_IRQ_WATCHDOG AR531X_MISC_IRQ_BASE+7 ++#define AR531X_MISC_IRQ_LOCAL AR531X_MISC_IRQ_BASE+8 ++#define AR531X_MISC_IRQ_SPI AR531X_MISC_IRQ_BASE+9 ++#define AR531X_MISC_IRQ_COUNT 10 ++ ++/* GPIO Interrupts [0..7], share AR531X_MISC_IRQ_GPIO */ ++#define AR531X_GPIO_IRQ_NONE AR531X_GPIO_IRQ_BASE+0 ++#define AR531X_GPIO_IRQ(n) AR531X_GPIO_IRQ_BASE+n ++#define AR531X_GPIO_IRQ_COUNT 22 ++ ++static inline u32 ++ar231x_read_reg(u32 reg) ++{ ++ return __raw_readl((u32 *) KSEG1ADDR(reg)); ++} ++ ++static inline void ++ar231x_write_reg(u32 reg, u32 val) ++{ ++ __raw_writel(val, (u32 *) KSEG1ADDR(reg)); ++} ++ ++static inline u32 ++ar231x_mask_reg(u32 reg, u32 mask, u32 val) ++{ ++ u32 ret; ++ ++ ret = ar231x_read_reg(reg); ++ ret &= ~mask; ++ ret |= val; ++ ar231x_write_reg(reg, ret); ++ ++ return ret; ++} ++ ++#endif +diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar231x_platform.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar231x_platform.h +--- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar231x_platform.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar231x_platform.h 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,83 @@ ++#ifndef __AR531X_PLATFORM_H ++#define __AR531X_PLATFORM_H ++ ++/* ++ * This is board-specific data that is stored in a "fixed" location in flash. ++ * It is shared across operating systems, so it should not be changed lightly. ++ * The main reason we need it is in order to extract the ethernet MAC ++ * address(es). ++ */ ++struct ar231x_boarddata { ++ u32 magic; /* board data is valid */ ++#define AR531X_BD_MAGIC 0x35333131 /* "5311", for all 531x platforms */ ++ u16 cksum; /* checksum (starting with BD_REV 2) */ ++ u16 rev; /* revision of this struct */ ++#define BD_REV 4 ++ char boardName[64]; /* Name of board */ ++ u16 major; /* Board major number */ ++ u16 minor; /* Board minor number */ ++ u32 flags; /* Board configuration */ ++#define BD_ENET0 0x00000001 /* ENET0 is stuffed */ ++#define BD_ENET1 0x00000002 /* ENET1 is stuffed */ ++#define BD_UART1 0x00000004 /* UART1 is stuffed */ ++#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */ ++#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */ ++#define BD_SYSLED 0x00000020 /* System LED stuffed */ ++#define BD_EXTUARTCLK 0x00000040 /* External UART clock */ ++#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */ ++#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */ ++#define BD_WLAN0 0x00000200 /* Enable WLAN0 */ ++#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ memCap for testing */ ++#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */ ++#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */ ++#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */ ++#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */ ++#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */ ++#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */ ++#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */ ++ u16 resetConfigGpio; /* Reset factory GPIO pin */ ++ u16 sysLedGpio; /* System LED GPIO pin */ ++ ++ u32 cpuFreq; /* CPU core frequency in Hz */ ++ u32 sysFreq; /* System frequency in Hz */ ++ u32 cntFreq; /* Calculated C0_COUNT frequency */ ++ ++ u8 wlan0_mac[6]; ++ u8 enet0_mac[6]; ++ u8 enet1_mac[6]; ++ ++ u16 pciId; /* Pseudo PCIID for common code */ ++ u16 memCap; /* cap bank1 in MB */ ++ ++ /* version 3 */ ++ u8 wlan1_mac[6]; /* (ar5212) */ ++}; ++ ++#define BOARD_CONFIG_BUFSZ 0x1000 ++ ++/* ++ * Platform device information for the Wireless MAC ++ */ ++struct ar231x_board_config { ++ u16 devid; ++ ++ /* board config data */ ++ struct ar231x_boarddata *config; ++ ++ /* radio calibration data */ ++ const char *radio; ++}; ++ ++/* ++ * Platform device information for the Ethernet MAC ++ */ ++struct ar231x_eth { ++ u32 reset_base; ++ u32 reset_mac; ++ u32 reset_phy; ++ u32 phy_base; ++ struct ar231x_board_config *config; ++ char *macaddr; ++}; ++ ++#endif /* __AR531X_PLATFORM_H */ +diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar5312_regs.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar5312_regs.h +--- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar5312_regs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar5312_regs.h 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,236 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. ++ * Copyright (C) 2006 Imre Kaloz ++ * Copyright (C) 2006 Felix Fietkau ++ */ ++ ++#ifndef AR5312_H ++#define AR5312_H ++ ++#include ++ ++/* ++ * IRQs ++ */ ++ ++#define AR5312_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */ ++#define AR5312_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */ ++#define AR5312_IRQ_ENET1_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */ ++#define AR5312_IRQ_WLAN1_INTRS MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */ ++#define AR5312_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */ ++ ++ ++/* Address Map */ ++#define AR531X_WLAN0 0x18000000 ++#define AR531X_WLAN1 0x18500000 ++#define AR531X_ENET0 0x18100000 ++#define AR531X_ENET1 0x18200000 ++#define AR531X_SDRAMCTL 0x18300000 ++#define AR531X_FLASHCTL 0x18400000 ++#define AR531X_APBBASE 0x1c000000 ++#define AR531X_FLASH 0x1e000000 ++#define AR531X_UART0 0xbc000003 /* UART MMR */ ++ ++/* ++ * AR531X_NUM_ENET_MAC defines the number of ethernet MACs that ++ * should be considered available. The AR5312 supports 2 enet MACS, ++ * even though many reference boards only actually use 1 of them ++ * (i.e. Only MAC 0 is actually connected to an enet PHY or PHY switch. ++ * The AR2312 supports 1 enet MAC. ++ */ ++#define AR531X_NUM_ENET_MAC 2 ++ ++/* ++ * Need these defines to determine true number of ethernet MACs ++ */ ++#define AR5212_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */ ++#define AR5212_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */ ++#define AR5212_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */ ++#define AR531X_RADIO_MASK_OFF 0xc8 ++#define AR531X_RADIO0_MASK 0x0003 ++#define AR531X_RADIO1_MASK 0x000c ++#define AR531X_RADIO1_S 2 ++ ++/* ++ * AR531X_NUM_WMAC defines the number of Wireless MACs that\ ++ * should be considered available. ++ */ ++#define AR531X_NUM_WMAC 2 ++ ++/* Reset/Timer Block Address Map */ ++#define AR531X_RESETTMR (AR531X_APBBASE + 0x3000) ++#define AR531X_TIMER (AR531X_RESETTMR + 0x0000) /* countdown timer */ ++#define AR531X_WD_CTRL (AR531X_RESETTMR + 0x0008) /* watchdog cntrl */ ++#define AR531X_WD_TIMER (AR531X_RESETTMR + 0x000c) /* watchdog timer */ ++#define AR531X_ISR (AR531X_RESETTMR + 0x0010) /* Intr Status Reg */ ++#define AR531X_IMR (AR531X_RESETTMR + 0x0014) /* Intr Mask Reg */ ++#define AR531X_RESET (AR531X_RESETTMR + 0x0020) ++#define AR5312_CLOCKCTL1 (AR531X_RESETTMR + 0x0064) ++#define AR5312_SCRATCH (AR531X_RESETTMR + 0x006c) ++#define AR531X_PROCADDR (AR531X_RESETTMR + 0x0070) ++#define AR531X_PROC1 (AR531X_RESETTMR + 0x0074) ++#define AR531X_DMAADDR (AR531X_RESETTMR + 0x0078) ++#define AR531X_DMA1 (AR531X_RESETTMR + 0x007c) ++#define AR531X_ENABLE (AR531X_RESETTMR + 0x0080) /* interface enb */ ++#define AR531X_REV (AR531X_RESETTMR + 0x0090) /* revision */ ++ ++/* AR531X_WD_CTRL register bit field definitions */ ++#define AR531X_WD_CTRL_IGNORE_EXPIRATION 0x0000 ++#define AR531X_WD_CTRL_NMI 0x0001 ++#define AR531X_WD_CTRL_RESET 0x0002 ++ ++/* AR531X_ISR register bit field definitions */ ++#define AR531X_ISR_NONE 0x0000 ++#define AR531X_ISR_TIMER 0x0001 ++#define AR531X_ISR_AHBPROC 0x0002 ++#define AR531X_ISR_AHBDMA 0x0004 ++#define AR531X_ISR_GPIO 0x0008 ++#define AR531X_ISR_UART0 0x0010 ++#define AR531X_ISR_UART0DMA 0x0020 ++#define AR531X_ISR_WD 0x0040 ++#define AR531X_ISR_LOCAL 0x0080 ++ ++/* AR531X_RESET register bit field definitions */ ++#define AR531X_RESET_SYSTEM 0x00000001 /* cold reset full system */ ++#define AR531X_RESET_PROC 0x00000002 /* cold reset MIPS core */ ++#define AR531X_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */ ++#define AR531X_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */ ++#define AR531X_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */ ++#define AR531X_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */ ++#define AR531X_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */ ++#define AR531X_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */ ++#define AR531X_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */ ++#define AR531X_RESET_APB 0x00000400 /* cold reset APB (ar5312) */ ++#define AR531X_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */ ++#define AR531X_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */ ++#define AR531X_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */ ++#define AR531X_RESET_NMI 0x00010000 /* send an NMI to the processor */ ++#define AR531X_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */ ++#define AR531X_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */ ++#define AR531X_RESET_LOCAL_BUS 0x00080000 /* reset local bus */ ++#define AR531X_RESET_WDOG 0x00100000 /* last reset was a watchdog */ ++ ++#define AR531X_RESET_WMAC0_BITS \ ++ AR531X_RESET_WLAN0 |\ ++ AR531X_RESET_WARM_WLAN0_MAC |\ ++ AR531X_RESET_WARM_WLAN0_BB ++ ++#define AR531X_RESERT_WMAC1_BITS \ ++ AR531X_RESET_WLAN1 |\ ++ AR531X_RESET_WARM_WLAN1_MAC |\ ++ AR531X_RESET_WARM_WLAN1_BB ++ ++/* AR5312_CLOCKCTL1 register bit field definitions */ ++#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030 ++#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4 ++#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00 ++#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8 ++#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000 ++ ++/* Valid for AR5312 and AR2312 */ ++#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030 ++#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4 ++#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00 ++#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8 ++#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000 ++ ++/* Valid for AR2313 */ ++#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000 ++#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12 ++#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000 ++#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16 ++#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000 ++ ++ ++/* AR531X_ENABLE register bit field definitions */ ++#define AR531X_ENABLE_WLAN0 0x0001 ++#define AR531X_ENABLE_ENET0 0x0002 ++#define AR531X_ENABLE_ENET1 0x0004 ++#define AR531X_ENABLE_UART_AND_WLAN1_PIO 0x0008 /* UART, and WLAN1 PIOs */ ++#define AR531X_ENABLE_WLAN1_DMA 0x0010 /* WLAN1 DMAs */ ++#define AR531X_ENABLE_WLAN1 \ ++ (AR531X_ENABLE_UART_AND_WLAN1_PIO | AR531X_ENABLE_WLAN1_DMA) ++ ++/* AR531X_REV register bit field definitions */ ++#define AR531X_REV_WMAC_MAJ 0xf000 ++#define AR531X_REV_WMAC_MAJ_S 12 ++#define AR531X_REV_WMAC_MIN 0x0f00 ++#define AR531X_REV_WMAC_MIN_S 8 ++#define AR531X_REV_MAJ 0x00f0 ++#define AR531X_REV_MAJ_S 4 ++#define AR531X_REV_MIN 0x000f ++#define AR531X_REV_MIN_S 0 ++#define AR531X_REV_CHIP (AR531X_REV_MAJ|AR531X_REV_MIN) ++ ++/* Major revision numbers, bits 7..4 of Revision ID register */ ++#define AR531X_REV_MAJ_AR5312 0x4 ++#define AR531X_REV_MAJ_AR2313 0x5 ++ ++/* Minor revision numbers, bits 3..0 of Revision ID register */ ++#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */ ++#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */ ++ ++/* AR531X_FLASHCTL register bit field definitions */ ++#define FLASHCTL_IDCY 0x0000000f /* Idle cycle turn around time */ ++#define FLASHCTL_IDCY_S 0 ++#define FLASHCTL_WST1 0x000003e0 /* Wait state 1 */ ++#define FLASHCTL_WST1_S 5 ++#define FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */ ++#define FLASHCTL_WST2 0x0000f800 /* Wait state 2 */ ++#define FLASHCTL_WST2_S 11 ++#define FLASHCTL_AC 0x00070000 /* Flash address check (added) */ ++#define FLASHCTL_AC_S 16 ++#define FLASHCTL_AC_128K 0x00000000 ++#define FLASHCTL_AC_256K 0x00010000 ++#define FLASHCTL_AC_512K 0x00020000 ++#define FLASHCTL_AC_1M 0x00030000 ++#define FLASHCTL_AC_2M 0x00040000 ++#define FLASHCTL_AC_4M 0x00050000 ++#define FLASHCTL_AC_8M 0x00060000 ++#define FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */ ++#define FLASHCTL_E 0x00080000 /* Flash bank enable (added) */ ++#define FLASHCTL_BUSERR 0x01000000 /* Bus transfer error status flag */ ++#define FLASHCTL_WPERR 0x02000000 /* Write protect error status flag */ ++#define FLASHCTL_WP 0x04000000 /* Write protect */ ++#define FLASHCTL_BM 0x08000000 /* Burst mode */ ++#define FLASHCTL_MW 0x30000000 /* Memory width */ ++#define FLASHCTL_MWx8 0x00000000 /* Memory width x8 */ ++#define FLASHCTL_MWx16 0x10000000 /* Memory width x16 */ ++#define FLASHCTL_MWx32 0x20000000 /* Memory width x32 (not supported) */ ++#define FLASHCTL_ATNR 0x00000000 /* Access type == no retry */ ++#define FLASHCTL_ATR 0x80000000 /* Access type == retry every */ ++#define FLASHCTL_ATR4 0xc0000000 /* Access type == retry every 4 */ ++ ++/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */ ++#define AR531X_FLASHCTL0 (AR531X_FLASHCTL + 0x00) ++#define AR531X_FLASHCTL1 (AR531X_FLASHCTL + 0x04) ++#define AR531X_FLASHCTL2 (AR531X_FLASHCTL + 0x08) ++ ++/* ARM SDRAM Controller -- just enough to determine memory size */ ++#define AR531X_MEM_CFG1 (AR531X_SDRAMCTL + 0x04) ++#define MEM_CFG1_AC0 0x00000700 /* bank 0: SDRAM addr check (added) */ ++#define MEM_CFG1_AC0_S 8 ++#define MEM_CFG1_AC1 0x00007000 /* bank 1: SDRAM addr check (added) */ ++#define MEM_CFG1_AC1_S 12 ++ ++/* GPIO Address Map */ ++#define AR531X_GPIO (AR531X_APBBASE + 0x2000) ++#define AR531X_GPIO_DO (AR531X_GPIO + 0x00) /* output register */ ++#define AR531X_GPIO_DI (AR531X_GPIO + 0x04) /* intput register */ ++#define AR531X_GPIO_CR (AR531X_GPIO + 0x08) /* control register */ ++ ++/* GPIO Control Register bit field definitions */ ++#define AR531X_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */ ++#define AR531X_GPIO_CR_O(x) (0 << (x)) /* mask for output */ ++#define AR531X_GPIO_CR_I(x) (1 << (x)) /* mask for input */ ++#define AR531X_GPIO_CR_INT(x) (1 << ((x)+8)) /* mask for interrupt */ ++#define AR531X_GPIO_CR_UART(x) (1 << ((x)+16)) /* uart multiplex */ ++#define AR531X_NUM_GPIO 8 ++ ++ ++#endif ++ +diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h +--- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,84 @@ ++/* ++ * Atheros SoC specific CPU feature overrides ++ * ++ * Copyright (C) 2008 Gabor Juhos ++ * ++ * This file was derived from: include/asm-mips/cpu-features.h ++ * Copyright (C) 2003, 2004 Ralf Baechle ++ * Copyright (C) 2004 Maciej W. Rozycki ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ */ ++#ifndef __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H ++#define __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H ++ ++/* ++ * The ATHEROS SoCs have MIPS 4Kc/4KEc core. ++ */ ++#define cpu_has_tlb 1 ++#define cpu_has_4kex 1 ++#define cpu_has_3k_cache 0 ++#define cpu_has_4k_cache 1 ++#define cpu_has_tx39_cache 0 ++#define cpu_has_sb1_cache 0 ++#define cpu_has_fpu 0 ++#define cpu_has_32fpr 0 ++#define cpu_has_counter 1 ++/* #define cpu_has_watch ? */ ++/* #define cpu_has_divec ? */ ++/* #define cpu_has_vce ? */ ++/* #define cpu_has_cache_cdex_p ? */ ++/* #define cpu_has_cache_cdex_s ? */ ++/* #define cpu_has_prefetch ? */ ++/* #define cpu_has_mcheck ? */ ++#define cpu_has_ejtag 1 ++ ++#if !defined(CONFIG_ATHEROS_AR5312) ++# define cpu_has_llsc 1 ++#else ++/* ++ * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the ++ * ll/sc instructions. ++ */ ++# define cpu_has_llsc 0 ++#endif ++ ++#define cpu_has_mips16 0 ++#define cpu_has_mdmx 0 ++#define cpu_has_mips3d 0 ++#define cpu_has_smartmips 0 ++ ++/* #define cpu_has_vtag_icache ? */ ++/* #define cpu_has_dc_aliases ? */ ++/* #define cpu_has_ic_fills_f_dc ? */ ++/* #define cpu_has_pindexed_dcache ? */ ++ ++/* #define cpu_icache_snoops_remote_store ? */ ++ ++#define cpu_has_mips32r1 1 ++ ++#if !defined(CONFIG_ATHEROS_AR5312) ++# define cpu_has_mips32r2 1 ++#endif ++ ++#define cpu_has_mips64r1 0 ++#define cpu_has_mips64r2 0 ++ ++#define cpu_has_dsp 0 ++#define cpu_has_mipsmt 0 ++ ++/* #define cpu_has_nofpuex ? */ ++#define cpu_has_64bits 0 ++#define cpu_has_64bit_zero_reg 0 ++#define cpu_has_64bit_gp_regs 0 ++#define cpu_has_64bit_addresses 0 ++ ++/* #define cpu_has_inclusive_pcaches ? */ ++ ++/* #define cpu_dcache_line_size() ? */ ++/* #define cpu_icache_line_size() ? */ ++ ++#endif /* __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H */ +diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/dma-coherence.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/dma-coherence.h +--- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/dma-coherence.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/dma-coherence.h 2011-05-15 21:41:19.000000000 +0200 +@@ -0,0 +1,76 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2006 Ralf Baechle ++ * Copyright (C) 2007 Felix Fietkau ++ * ++ */ ++#ifndef __ASM_MACH_GENERIC_DMA_COHERENCE_H ++#define __ASM_MACH_GENERIC_DMA_COHERENCE_H ++ ++#define PCI_DMA_OFFSET 0x20000000 ++ ++#include ++ ++static inline dma_addr_t ar231x_dev_offset(struct device *dev) ++{ ++#ifdef CONFIG_PCI ++ extern struct bus_type pci_bus_type; ++ ++ if (dev && dev->bus == &pci_bus_type) ++ return PCI_DMA_OFFSET; ++ else ++#endif ++ return 0; ++} ++ ++static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size) ++{ ++ return virt_to_phys(addr) + ar231x_dev_offset(dev); ++} ++ ++static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page) ++{ ++ return page_to_phys(page) + ar231x_dev_offset(dev); ++} ++ ++static inline unsigned long plat_dma_addr_to_phys(struct device *dev, ++ dma_addr_t dma_addr) ++{ ++ return dma_addr - ar231x_dev_offset(dev); ++} ++ ++static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, ++ size_t size, enum dma_data_direction direction) ++{ ++} ++ ++static inline int plat_dma_supported(struct device *dev, u64 mask) ++{ ++ return 1; ++} ++ ++static inline void plat_extra_sync_for_device(struct device *dev) ++{ ++ return; ++} ++ ++static inline int plat_dma_mapping_error(struct device *dev, ++ dma_addr_t dma_addr) ++{ ++ return 0; ++} ++ ++static inline int plat_device_is_coherent(struct device *dev) ++{ ++#ifdef CONFIG_DMA_COHERENT ++ return 1; ++#endif ++#ifdef CONFIG_DMA_NONCOHERENT ++ return 0; ++#endif ++} ++ ++#endif /* __ASM_MACH_GENERIC_DMA_COHERENCE_H */ +diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/gpio.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/gpio.h +--- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/gpio.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/gpio.h 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,84 @@ ++#ifndef _ATHEROS_GPIO_H_ ++#define _ATHEROS_GPIO_H_ ++ ++#include ++ ++struct ar231x_gpiodev { ++ u32 valid_mask; ++ u32 (*get_output)(void); ++ u32 (*set_output)(u32 mask, u32 val); ++ u32 (*get)(void); ++ u32 (*set)(u32 mask, u32 val); ++}; ++ ++extern const struct ar231x_gpiodev *ar231x_gpiodev; ++ ++/* ++ * Wrappers for the generic GPIO layer ++ */ ++ ++static inline int gpio_direction_input(unsigned gpio) { ++ u32 mask = 1 << gpio; ++ ++ if (!(ar231x_gpiodev->valid_mask & mask)) ++ return -ENXIO; ++ ++ ar231x_gpiodev->set_output(mask, 0); ++ return 0; ++} ++ ++static inline void gpio_set_value(unsigned gpio, int value) { ++ u32 mask = 1 << gpio; ++ ++ if (!(ar231x_gpiodev->valid_mask & mask)) ++ return; ++ ++ ar231x_gpiodev->set(mask, (!!value) * mask); ++} ++ ++static inline int gpio_direction_output(unsigned gpio, int value) { ++ u32 mask = 1 << gpio; ++ ++ if (!(ar231x_gpiodev->valid_mask & mask)) ++ return -ENXIO; ++ ++ ar231x_gpiodev->set_output(mask, mask); ++ ar231x_gpiodev->set(mask, (!!value) * mask); ++ return 0; ++} ++ ++/* Reads the gpio pin. Unchecked function */ ++static inline int gpio_get_value(unsigned gpio) { ++ u32 mask = 1 << gpio; ++ ++ if (!(ar231x_gpiodev->valid_mask & mask)) ++ return 0; ++ ++ return !!(ar231x_gpiodev->get() & mask); ++} ++ ++static inline int gpio_request(unsigned gpio, const char *label) { ++ return 0; ++} ++ ++static inline void gpio_free(unsigned gpio) { ++} ++ ++/* Returns IRQ to attach for gpio. Unchecked function */ ++static inline int gpio_to_irq(unsigned gpio) { ++ return AR531X_GPIO_IRQ(gpio); ++} ++ ++/* Returns gpio for IRQ attached. Unchecked function */ ++static inline int irq_to_gpio(unsigned irq) { ++ return (irq - (AR531X_GPIO_IRQ(0))); ++} ++ ++static inline int gpio_set_debounce(unsigned gpio, unsigned debounce) ++{ ++ return -ENOSYS; ++} ++ ++#include /* cansleep wrappers */ ++ ++#endif +diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/reset.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/reset.h +--- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/reset.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/reset.h 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,6 @@ ++#ifndef __AR531X_RESET_H ++#define __AR531X_RESET_H ++ ++void ar531x_disable_reset_button(void); ++ ++#endif /* __AR531X_RESET_H */ +diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/war.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/war.h +--- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/war.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/war.h 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,25 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2008 Felix Fietkau ++ */ ++#ifndef __ASM_MIPS_MACH_ATHEROS_WAR_H ++#define __ASM_MIPS_MACH_ATHEROS_WAR_H ++ ++#define R4600_V1_INDEX_ICACHEOP_WAR 0 ++#define R4600_V1_HIT_CACHEOP_WAR 0 ++#define R4600_V2_HIT_CACHEOP_WAR 0 ++#define R5432_CP0_INTERRUPT_WAR 0 ++#define BCM1250_M3_WAR 0 ++#define SIBYTE_1956_WAR 0 ++#define MIPS4K_ICACHE_REFILL_WAR 0 ++#define MIPS_CACHE_SYNC_WAR 0 ++#define TX49XX_ICACHE_INDEX_INV_WAR 0 ++#define RM9000_CDEX_SMP_WAR 0 ++#define ICACHE_REFILLS_WORKAROUND_WAR 0 ++#define R10000_LLSC_WAR 0 ++#define MIPS34K_MISSED_ITLB_WAR 0 ++ ++#endif /* __ASM_MIPS_MACH_ATHEROS_WAR_H */ +diff -Nur linux-2.6.39-rc7.orig/arch/mips/kernel/cevt-r4k.c linux-2.6.39-rc7/arch/mips/kernel/cevt-r4k.c +--- linux-2.6.39-rc7.orig/arch/mips/kernel/cevt-r4k.c 2011-05-10 04:33:54.000000000 +0200 ++++ linux-2.6.39-rc7/arch/mips/kernel/cevt-r4k.c 2011-05-15 21:34:57.000000000 +0200 +@@ -168,20 +168,23 @@ + struct clock_event_device *cd; + unsigned int irq; + +- if (!cpu_has_counter || !mips_hpt_frequency) +- return -ENXIO; +- +- if (!c0_compare_int_usable()) +- return -ENXIO; +- + /* + * With vectored interrupts things are getting platform specific. + * get_c0_compare_int is a hook to allow a platform to return the + * interrupt number of it's liking. + */ + irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; +- if (get_c0_compare_int) ++ if (get_c0_compare_int) { + irq = get_c0_compare_int(); ++ if ((irq >= MIPS_CPU_IRQ_BASE) && (irq < MIPS_CPU_IRQ_BASE + 8)) ++ cp0_compare_irq = irq - MIPS_CPU_IRQ_BASE; ++ } ++ ++ if (!cpu_has_counter || !mips_hpt_frequency) ++ return -ENXIO; ++ ++ if (!c0_compare_int_usable()) ++ return -ENXIO; + + cd = &per_cpu(mips_clockevent_device, cpu); + +diff -Nur linux-2.6.39-rc7.orig/drivers/mtd/devices/Kconfig linux-2.6.39-rc7/drivers/mtd/devices/Kconfig +--- linux-2.6.39-rc7.orig/drivers/mtd/devices/Kconfig 2011-05-10 04:33:54.000000000 +0200 ++++ linux-2.6.39-rc7/drivers/mtd/devices/Kconfig 2011-05-15 21:34:57.000000000 +0200 +@@ -112,6 +112,10 @@ + Set up your spi devices with the right board-specific platform data, + if you want to specify device partitioning. + ++config MTD_AR2315 ++ tristate "Atheros AR2315+ SPI Flash support" ++ depends on ATHEROS_AR2315 ++ + config MTD_SLRAM + tristate "Uncached system RAM" + help +diff -Nur linux-2.6.39-rc7.orig/drivers/mtd/devices/Makefile linux-2.6.39-rc7/drivers/mtd/devices/Makefile +--- linux-2.6.39-rc7.orig/drivers/mtd/devices/Makefile 2011-05-10 04:33:54.000000000 +0200 ++++ linux-2.6.39-rc7/drivers/mtd/devices/Makefile 2011-05-15 21:34:57.000000000 +0200 +@@ -17,3 +17,4 @@ + obj-$(CONFIG_MTD_DATAFLASH) += mtd_dataflash.o + obj-$(CONFIG_MTD_M25P80) += m25p80.o + obj-$(CONFIG_MTD_SST25L) += sst25l.o ++obj-$(CONFIG_MTD_AR2315) += ar2315.o +diff -Nur linux-2.6.39-rc7.orig/drivers/mtd/devices/ar2315.c linux-2.6.39-rc7/drivers/mtd/devices/ar2315.c +--- linux-2.6.39-rc7.orig/drivers/mtd/devices/ar2315.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/drivers/mtd/devices/ar2315.c 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,517 @@ ++ ++/* ++ * MTD driver for the SPI Flash Memory support on Atheros AR2315 ++ * ++ * Copyright (c) 2005-2006 Atheros Communications Inc. ++ * Copyright (C) 2006-2007 FON Technology, SL. ++ * Copyright (C) 2006-2007 Imre Kaloz ++ * Copyright (C) 2006-2009 Felix Fietkau ++ * ++ * This code is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++ ++#define SPIFLASH "spiflash: " ++#define busy_wait(_priv, _condition, _wait) do { \ ++ while (_condition) { \ ++ spin_unlock_bh(&_priv->lock); \ ++ if (_wait > 1) \ ++ msleep(_wait); \ ++ else if ((_wait == 1) && need_resched()) \ ++ schedule(); \ ++ else \ ++ udelay(1); \ ++ spin_lock_bh(&_priv->lock); \ ++ } \ ++} while (0) ++ ++enum { ++ FLASH_NONE, ++ FLASH_1MB, ++ FLASH_2MB, ++ FLASH_4MB, ++ FLASH_8MB, ++ FLASH_16MB, ++}; ++ ++/* Flash configuration table */ ++struct flashconfig { ++ u32 byte_cnt; ++ u32 sector_cnt; ++ u32 sector_size; ++}; ++ ++const struct flashconfig flashconfig_tbl[] = { ++ [FLASH_NONE] = { 0, 0, 0}, ++ [FLASH_1MB] = { STM_1MB_BYTE_COUNT, STM_1MB_SECTOR_COUNT, STM_1MB_SECTOR_SIZE}, ++ [FLASH_2MB] = { STM_2MB_BYTE_COUNT, STM_2MB_SECTOR_COUNT, STM_2MB_SECTOR_SIZE}, ++ [FLASH_4MB] = { STM_4MB_BYTE_COUNT, STM_4MB_SECTOR_COUNT, STM_4MB_SECTOR_SIZE}, ++ [FLASH_8MB] = { STM_8MB_BYTE_COUNT, STM_8MB_SECTOR_COUNT, STM_8MB_SECTOR_SIZE}, ++ [FLASH_16MB] = { STM_16MB_BYTE_COUNT, STM_16MB_SECTOR_COUNT, STM_16MB_SECTOR_SIZE} ++}; ++ ++/* Mapping of generic opcodes to STM serial flash opcodes */ ++enum { ++ SPI_WRITE_ENABLE, ++ SPI_WRITE_DISABLE, ++ SPI_RD_STATUS, ++ SPI_WR_STATUS, ++ SPI_RD_DATA, ++ SPI_FAST_RD_DATA, ++ SPI_PAGE_PROGRAM, ++ SPI_SECTOR_ERASE, ++ SPI_BULK_ERASE, ++ SPI_DEEP_PWRDOWN, ++ SPI_RD_SIG, ++}; ++ ++struct opcodes { ++ __u16 code; ++ __s8 tx_cnt; ++ __s8 rx_cnt; ++}; ++const struct opcodes stm_opcodes[] = { ++ [SPI_WRITE_ENABLE] = {STM_OP_WR_ENABLE, 1, 0}, ++ [SPI_WRITE_DISABLE] = {STM_OP_WR_DISABLE, 1, 0}, ++ [SPI_RD_STATUS] = {STM_OP_RD_STATUS, 1, 1}, ++ [SPI_WR_STATUS] = {STM_OP_WR_STATUS, 1, 0}, ++ [SPI_RD_DATA] = {STM_OP_RD_DATA, 4, 4}, ++ [SPI_FAST_RD_DATA] = {STM_OP_FAST_RD_DATA, 5, 0}, ++ [SPI_PAGE_PROGRAM] = {STM_OP_PAGE_PGRM, 8, 0}, ++ [SPI_SECTOR_ERASE] = {STM_OP_SECTOR_ERASE, 4, 0}, ++ [SPI_BULK_ERASE] = {STM_OP_BULK_ERASE, 1, 0}, ++ [SPI_DEEP_PWRDOWN] = {STM_OP_DEEP_PWRDOWN, 1, 0}, ++ [SPI_RD_SIG] = {STM_OP_RD_SIG, 4, 1}, ++}; ++ ++/* Driver private data structure */ ++struct spiflash_priv { ++ struct mtd_info mtd; ++ void *readaddr; /* memory mapped data for read */ ++ void *mmraddr; /* memory mapped register space */ ++ wait_queue_head_t wq; ++ spinlock_t lock; ++ int state; ++}; ++ ++#define to_spiflash(_mtd) container_of(_mtd, struct spiflash_priv, mtd) ++ ++enum { ++ FL_READY, ++ FL_READING, ++ FL_ERASING, ++ FL_WRITING ++}; ++ ++/***************************************************************************************************/ ++ ++static u32 ++spiflash_read_reg(struct spiflash_priv *priv, int reg) ++{ ++ return ar231x_read_reg((u32) priv->mmraddr + reg); ++} ++ ++static void ++spiflash_write_reg(struct spiflash_priv *priv, int reg, u32 data) ++{ ++ ar231x_write_reg((u32) priv->mmraddr + reg, data); ++} ++ ++static u32 ++spiflash_wait_busy(struct spiflash_priv *priv) ++{ ++ u32 reg; ++ ++ busy_wait(priv, (reg = spiflash_read_reg(priv, SPI_FLASH_CTL)) & ++ SPI_CTL_BUSY, 0); ++ return reg; ++} ++ ++static u32 ++spiflash_sendcmd (struct spiflash_priv *priv, int opcode, u32 addr) ++{ ++ const struct opcodes *op; ++ u32 reg, mask; ++ ++ op = &stm_opcodes[opcode]; ++ reg = spiflash_wait_busy(priv); ++ spiflash_write_reg(priv, SPI_FLASH_OPCODE, ++ ((u32) op->code) | (addr << 8)); ++ ++ reg &= ~SPI_CTL_TX_RX_CNT_MASK; ++ reg |= SPI_CTL_START | op->tx_cnt | (op->rx_cnt << 4); ++ ++ spiflash_write_reg(priv, SPI_FLASH_CTL, reg); ++ spiflash_wait_busy(priv); ++ ++ if (!op->rx_cnt) ++ return 0; ++ ++ reg = spiflash_read_reg(priv, SPI_FLASH_DATA); ++ ++ switch (op->rx_cnt) { ++ case 1: ++ mask = 0x000000ff; ++ break; ++ case 2: ++ mask = 0x0000ffff; ++ break; ++ case 3: ++ mask = 0x00ffffff; ++ break; ++ default: ++ mask = 0xffffffff; ++ break; ++ } ++ reg &= mask; ++ ++ return reg; ++} ++ ++ ++/* ++ * Probe SPI flash device ++ * Function returns 0 for failure. ++ * and flashconfig_tbl array index for success. ++ */ ++static int ++spiflash_probe_chip (struct spiflash_priv *priv) ++{ ++ u32 sig; ++ int flash_size; ++ ++ /* Read the signature on the flash device */ ++ spin_lock_bh(&priv->lock); ++ sig = spiflash_sendcmd(priv, SPI_RD_SIG, 0); ++ spin_unlock_bh(&priv->lock); ++ ++ switch (sig) { ++ case STM_8MBIT_SIGNATURE: ++ flash_size = FLASH_1MB; ++ break; ++ case STM_16MBIT_SIGNATURE: ++ flash_size = FLASH_2MB; ++ break; ++ case STM_32MBIT_SIGNATURE: ++ flash_size = FLASH_4MB; ++ break; ++ case STM_64MBIT_SIGNATURE: ++ flash_size = FLASH_8MB; ++ break; ++ case STM_128MBIT_SIGNATURE: ++ flash_size = FLASH_16MB; ++ break; ++ default: ++ printk (KERN_WARNING SPIFLASH "Read of flash device signature failed!\n"); ++ return 0; ++ } ++ ++ return flash_size; ++} ++ ++ ++/* wait until the flash chip is ready and grab a lock */ ++static int spiflash_wait_ready(struct spiflash_priv *priv, int state) ++{ ++ DECLARE_WAITQUEUE(wait, current); ++ ++retry: ++ spin_lock_bh(&priv->lock); ++ if (priv->state != FL_READY) { ++ set_current_state(TASK_UNINTERRUPTIBLE); ++ add_wait_queue(&priv->wq, &wait); ++ spin_unlock_bh(&priv->lock); ++ schedule(); ++ remove_wait_queue(&priv->wq, &wait); ++ ++ if(signal_pending(current)) ++ return 0; ++ ++ goto retry; ++ } ++ priv->state = state; ++ ++ return 1; ++} ++ ++static inline void spiflash_done(struct spiflash_priv *priv) ++{ ++ priv->state = FL_READY; ++ spin_unlock_bh(&priv->lock); ++ wake_up(&priv->wq); ++} ++ ++static void ++spiflash_wait_complete(struct spiflash_priv *priv, unsigned int timeout) ++{ ++ busy_wait(priv, spiflash_sendcmd(priv, SPI_RD_STATUS, 0) & ++ SPI_STATUS_WIP, timeout); ++ spiflash_done(priv); ++} ++ ++ ++ ++static int ++spiflash_erase (struct mtd_info *mtd, struct erase_info *instr) ++{ ++ struct spiflash_priv *priv = to_spiflash(mtd); ++ const struct opcodes *op; ++ u32 temp, reg; ++ ++ if (instr->addr + instr->len > mtd->size) ++ return -EINVAL; ++ ++ if (!spiflash_wait_ready(priv, FL_ERASING)) ++ return -EINTR; ++ ++ spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0); ++ reg = spiflash_wait_busy(priv); ++ ++ op = &stm_opcodes[SPI_SECTOR_ERASE]; ++ temp = ((u32)instr->addr << 8) | (u32)(op->code); ++ spiflash_write_reg(priv, SPI_FLASH_OPCODE, temp); ++ ++ reg &= ~SPI_CTL_TX_RX_CNT_MASK; ++ reg |= op->tx_cnt | SPI_CTL_START; ++ spiflash_write_reg(priv, SPI_FLASH_CTL, reg); ++ ++ spiflash_wait_complete(priv, 20); ++ ++ instr->state = MTD_ERASE_DONE; ++ mtd_erase_callback(instr); ++ ++ return 0; ++} ++ ++static int ++spiflash_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf) ++{ ++ struct spiflash_priv *priv = to_spiflash(mtd); ++ u8 *read_addr; ++ ++ if (!len) ++ return 0; ++ ++ if (from + len > mtd->size) ++ return -EINVAL; ++ ++ *retlen = len; ++ ++ if (!spiflash_wait_ready(priv, FL_READING)) ++ return -EINTR; ++ ++ read_addr = (u8 *)(priv->readaddr + from); ++ memcpy_fromio(buf, read_addr, len); ++ spiflash_done(priv); ++ ++ return 0; ++} ++ ++static int ++spiflash_write (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u8 *buf) ++{ ++ struct spiflash_priv *priv = to_spiflash(mtd); ++ u32 opcode, bytes_left; ++ ++ *retlen = 0; ++ ++ if (!len) ++ return 0; ++ ++ if (to + len > mtd->size) ++ return -EINVAL; ++ ++ bytes_left = len; ++ ++ do { ++ u32 read_len, reg, page_offset, spi_data = 0; ++ ++ read_len = min(bytes_left, sizeof(u32)); ++ ++ /* 32-bit writes cannot span across a page boundary ++ * (256 bytes). This types of writes require two page ++ * program operations to handle it correctly. The STM part ++ * will write the overflow data to the beginning of the ++ * current page as opposed to the subsequent page. ++ */ ++ page_offset = (to & (STM_PAGE_SIZE - 1)) + read_len; ++ ++ if (page_offset > STM_PAGE_SIZE) ++ read_len -= (page_offset - STM_PAGE_SIZE); ++ ++ if (!spiflash_wait_ready(priv, FL_WRITING)) ++ return -EINTR; ++ ++ spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0); ++ spi_data = 0; ++ switch (read_len) { ++ case 4: ++ spi_data |= buf[3] << 24; ++ /* fall through */ ++ case 3: ++ spi_data |= buf[2] << 16; ++ /* fall through */ ++ case 2: ++ spi_data |= buf[1] << 8; ++ /* fall through */ ++ case 1: ++ spi_data |= buf[0] & 0xff; ++ break; ++ default: ++ break; ++ } ++ ++ spiflash_write_reg(priv, SPI_FLASH_DATA, spi_data); ++ opcode = stm_opcodes[SPI_PAGE_PROGRAM].code | ++ (to & 0x00ffffff) << 8; ++ spiflash_write_reg(priv, SPI_FLASH_OPCODE, opcode); ++ ++ reg = spiflash_read_reg(priv, SPI_FLASH_CTL); ++ reg &= ~SPI_CTL_TX_RX_CNT_MASK; ++ reg |= (read_len + 4) | SPI_CTL_START; ++ spiflash_write_reg(priv, SPI_FLASH_CTL, reg); ++ ++ spiflash_wait_complete(priv, 1); ++ ++ bytes_left -= read_len; ++ to += read_len; ++ buf += read_len; ++ ++ *retlen += read_len; ++ } while (bytes_left != 0); ++ ++ return 0; ++} ++ ++ ++#ifdef CONFIG_MTD_PARTITIONS ++static const char *part_probe_types[] = { "cmdlinepart", "RedBoot", "MyLoader", NULL }; ++#endif ++ ++ ++static int ++spiflash_probe(struct platform_device *pdev) ++{ ++ struct spiflash_priv *priv; ++ struct mtd_partition *parts; ++ struct mtd_info *mtd; ++ int index, num_parts; ++ int result = 0; ++ ++ priv = kzalloc(sizeof(struct spiflash_priv), GFP_KERNEL); ++ spin_lock_init(&priv->lock); ++ init_waitqueue_head(&priv->wq); ++ priv->state = FL_READY; ++ mtd = &priv->mtd; ++ ++ priv->mmraddr = ioremap_nocache(SPI_FLASH_MMR, SPI_FLASH_MMR_SIZE); ++ if (!priv->mmraddr) { ++ printk(KERN_WARNING SPIFLASH "Failed to map flash device\n"); ++ goto error; ++ } ++ ++ index = spiflash_probe_chip(priv); ++ if (!index) { ++ printk (KERN_WARNING SPIFLASH "Found no serial flash device\n"); ++ goto error; ++ } ++ ++ priv->readaddr = ioremap_nocache(SPI_FLASH_READ, flashconfig_tbl[index].byte_cnt); ++ if (!priv->readaddr) { ++ printk (KERN_WARNING SPIFLASH "Failed to map flash device\n"); ++ goto error; ++ } ++ ++ platform_set_drvdata(pdev, priv); ++ mtd->name = "spiflash"; ++ mtd->type = MTD_NORFLASH; ++ mtd->flags = (MTD_CAP_NORFLASH|MTD_WRITEABLE); ++ mtd->size = flashconfig_tbl[index].byte_cnt; ++ mtd->erasesize = flashconfig_tbl[index].sector_size; ++ mtd->writesize = 1; ++ mtd->numeraseregions = 0; ++ mtd->eraseregions = NULL; ++ mtd->erase = spiflash_erase; ++ mtd->read = spiflash_read; ++ mtd->write = spiflash_write; ++ mtd->owner = THIS_MODULE; ++ ++#ifdef CONFIG_MTD_PARTITIONS ++ /* parse redboot partitions */ ++ num_parts = parse_mtd_partitions(mtd, part_probe_types, &parts, 0); ++ if (!num_parts) ++ goto error; ++ ++ result = add_mtd_partitions(mtd, parts, num_parts); ++#endif ++ ++ return result; ++ ++error: ++ if (priv->mmraddr) ++ iounmap(priv->mmraddr); ++ kfree(priv); ++ return -ENXIO; ++} ++ ++static int ++spiflash_remove (struct platform_device *pdev) ++{ ++ struct spiflash_priv *priv = platform_get_drvdata(pdev); ++ struct mtd_info *mtd = &priv->mtd; ++ ++ del_mtd_partitions(mtd); ++ iounmap(priv->mmraddr); ++ iounmap(priv->readaddr); ++ kfree(priv); ++ ++ return 0; ++} ++ ++struct platform_driver spiflash_driver = { ++ .driver.name = "spiflash", ++ .probe = spiflash_probe, ++ .remove = spiflash_remove, ++}; ++ ++int __init ++spiflash_init (void) ++{ ++ return platform_driver_register(&spiflash_driver); ++} ++ ++void __exit ++spiflash_exit (void) ++{ ++ return platform_driver_unregister(&spiflash_driver); ++} ++ ++module_init (spiflash_init); ++module_exit (spiflash_exit); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("OpenWrt.org, Atheros Communications Inc"); ++MODULE_DESCRIPTION("MTD driver for SPI Flash on Atheros SOC"); ++ +diff -Nur linux-2.6.39-rc7.orig/drivers/mtd/redboot.c linux-2.6.39-rc7/drivers/mtd/redboot.c +--- linux-2.6.39-rc7.orig/drivers/mtd/redboot.c 2011-05-10 04:33:54.000000000 +0200 ++++ linux-2.6.39-rc7/drivers/mtd/redboot.c 2011-05-15 21:34:57.000000000 +0200 +@@ -55,6 +55,22 @@ + return 1; + } + ++static uint32_t mtd_get_offset_erasesize(struct mtd_info *mtd, uint64_t offset) ++{ ++ struct mtd_erase_region_info *regions = mtd->eraseregions; ++ int i; ++ ++ for (i = 0; i < mtd->numeraseregions; i++) { ++ if (regions[i].offset + ++ regions[i].numblocks * regions[i].erasesize <= offset) ++ continue; ++ ++ return regions[i].erasesize; ++ } ++ ++ return mtd->erasesize; ++} ++ + static int parse_redboot_partitions(struct mtd_info *master, + struct mtd_partition **pparts, + unsigned long fis_origin) +@@ -70,36 +86,38 @@ + int namelen = 0; + int nulllen = 0; + int numslots; ++ int first_slot; + unsigned long offset; + #ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED + static char nullstring[] = "unallocated"; + #endif + ++ buf = vmalloc(master->erasesize); ++ if (!buf) ++ return -ENOMEM; ++ ++ restart: + if ( directory < 0 ) { + offset = master->size + directory * master->erasesize; +- while (master->block_isbad && ++ while (master->block_isbad && + master->block_isbad(master, offset)) { + if (!offset) { + nogood: + printk(KERN_NOTICE "Failed to find a non-bad block to check for RedBoot partition table\n"); ++ vfree(buf); + return -EIO; + } + offset -= master->erasesize; + } + } else { + offset = directory * master->erasesize; +- while (master->block_isbad && ++ while (master->block_isbad && + master->block_isbad(master, offset)) { + offset += master->erasesize; + if (offset == master->size) + goto nogood; + } + } +- buf = vmalloc(master->erasesize); +- +- if (!buf) +- return -ENOMEM; +- + printk(KERN_NOTICE "Searching for RedBoot partition table in %s at offset 0x%lx\n", + master->name, offset); + +@@ -171,13 +189,21 @@ + } + if (i == numslots) { + /* Didn't find it */ ++ if (offset + master->erasesize < master->size) { ++ /* not at the end of the flash yet, maybe next block :) */ ++ directory++; ++ goto restart; ++ } + printk(KERN_NOTICE "No RedBoot partition table detected in %s\n", + master->name); + ret = 0; + goto out; + } + +- for (i = 0; i < numslots; i++) { ++ first_slot = (buf[i].flash_base & (master->erasesize - 1)) / ++ sizeof(struct fis_image_desc); ++ ++ for (i = first_slot; i < first_slot + numslots; i++) { + struct fis_list *new_fl, **prev; + + if (buf[i].name[0] == 0xff) { +diff -Nur linux-2.6.39-rc7.orig/drivers/net/Kconfig linux-2.6.39-rc7/drivers/net/Kconfig +--- linux-2.6.39-rc7.orig/drivers/net/Kconfig 2011-05-10 04:33:54.000000000 +0200 ++++ linux-2.6.39-rc7/drivers/net/Kconfig 2011-05-15 21:34:57.000000000 +0200 +@@ -251,6 +251,12 @@ + help + Select this if your platform comes with an external 93CX6 eeprom. + ++config AR231X_ETHERNET ++ tristate "AR231x Ethernet support" ++ depends on ATHEROS_AR231X ++ help ++ Support for the AR231x/531x ethernet controller ++ + config MACE + tristate "MACE (Power Mac ethernet) support" + depends on PPC_PMAC && PPC32 +diff -Nur linux-2.6.39-rc7.orig/drivers/net/Makefile linux-2.6.39-rc7/drivers/net/Makefile +--- linux-2.6.39-rc7.orig/drivers/net/Makefile 2011-05-10 04:33:54.000000000 +0200 ++++ linux-2.6.39-rc7/drivers/net/Makefile 2011-05-15 21:34:57.000000000 +0200 +@@ -226,6 +226,7 @@ + obj-$(CONFIG_KORINA) += korina.o + obj-$(CONFIG_MIPS_JAZZ_SONIC) += jazzsonic.o + obj-$(CONFIG_MIPS_AU1X00_ENET) += au1000_eth.o ++obj-$(CONFIG_AR231X_ETHERNET) += ar231x.o + obj-$(CONFIG_MIPS_SIM_NET) += mipsnet.o + obj-$(CONFIG_SGI_IOC3_ETH) += ioc3-eth.o + obj-$(CONFIG_DECLANCE) += declance.o +diff -Nur linux-2.6.39-rc7.orig/drivers/net/ar231x.c linux-2.6.39-rc7/drivers/net/ar231x.c +--- linux-2.6.39-rc7.orig/drivers/net/ar231x.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/drivers/net/ar231x.c 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,1293 @@ ++/* ++ * ar231x.c: Linux driver for the Atheros AR231x Ethernet device. ++ * ++ * Copyright (C) 2004 by Sameer Dekate ++ * Copyright (C) 2006 Imre Kaloz ++ * Copyright (C) 2006-2009 Felix Fietkau ++ * ++ * Thanks to Atheros for providing hardware and documentation ++ * enabling me to write this driver. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * Additional credits: ++ * This code is taken from John Taylor's Sibyte driver and then ++ * modified for the AR2313. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define AR2313_MTU 1692 ++#define AR2313_PRIOS 1 ++#define AR2313_QUEUES (2*AR2313_PRIOS) ++#define AR2313_DESCR_ENTRIES 64 ++ ++ ++#ifndef min ++#define min(a,b) (((a)<(b))?(a):(b)) ++#endif ++ ++#ifndef SMP_CACHE_BYTES ++#define SMP_CACHE_BYTES L1_CACHE_BYTES ++#endif ++ ++#define AR2313_MBOX_SET_BIT 0x8 ++ ++#include "ar231x.h" ++ ++/* ++ * New interrupt handler strategy: ++ * ++ * An old interrupt handler worked using the traditional method of ++ * replacing an skbuff with a new one when a packet arrives. However ++ * the rx rings do not need to contain a static number of buffer ++ * descriptors, thus it makes sense to move the memory allocation out ++ * of the main interrupt handler and do it in a bottom half handler ++ * and only allocate new buffers when the number of buffers in the ++ * ring is below a certain threshold. In order to avoid starving the ++ * NIC under heavy load it is however necessary to force allocation ++ * when hitting a minimum threshold. The strategy for alloction is as ++ * follows: ++ * ++ * RX_LOW_BUF_THRES - allocate buffers in the bottom half ++ * RX_PANIC_LOW_THRES - we are very low on buffers, allocate ++ * the buffers in the interrupt handler ++ * RX_RING_THRES - maximum number of buffers in the rx ring ++ * ++ * One advantagous side effect of this allocation approach is that the ++ * entire rx processing can be done without holding any spin lock ++ * since the rx rings and registers are totally independent of the tx ++ * ring and its registers. This of course includes the kmalloc's of ++ * new skb's. Thus start_xmit can run in parallel with rx processing ++ * and the memory allocation on SMP systems. ++ * ++ * Note that running the skb reallocation in a bottom half opens up ++ * another can of races which needs to be handled properly. In ++ * particular it can happen that the interrupt handler tries to run ++ * the reallocation while the bottom half is either running on another ++ * CPU or was interrupted on the same CPU. To get around this the ++ * driver uses bitops to prevent the reallocation routines from being ++ * reentered. ++ * ++ * TX handling can also be done without holding any spin lock, wheee ++ * this is fun! since tx_csm is only written to by the interrupt ++ * handler. ++ */ ++ ++/* ++ * Threshold values for RX buffer allocation - the low water marks for ++ * when to start refilling the rings are set to 75% of the ring ++ * sizes. It seems to make sense to refill the rings entirely from the ++ * intrrupt handler once it gets below the panic threshold, that way ++ * we don't risk that the refilling is moved to another CPU when the ++ * one running the interrupt handler just got the slab code hot in its ++ * cache. ++ */ ++#define RX_RING_SIZE AR2313_DESCR_ENTRIES ++#define RX_PANIC_THRES (RX_RING_SIZE/4) ++#define RX_LOW_THRES ((3*RX_RING_SIZE)/4) ++#define CRC_LEN 4 ++#define RX_OFFSET 2 ++ ++#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) ++#define VLAN_HDR 4 ++#else ++#define VLAN_HDR 0 ++#endif ++ ++#define AR2313_BUFSIZE (AR2313_MTU + VLAN_HDR + ETH_HLEN + CRC_LEN + RX_OFFSET) ++ ++#ifdef MODULE ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Sameer Dekate , Imre Kaloz , Felix Fietkau "); ++MODULE_DESCRIPTION("AR231x Ethernet driver"); ++#endif ++ ++#define virt_to_phys(x) ((u32)(x) & 0x1fffffff) ++ ++// prototypes ++static void ar231x_halt(struct net_device *dev); ++static void rx_tasklet_func(unsigned long data); ++static void rx_tasklet_cleanup(struct net_device *dev); ++static void ar231x_multicast_list(struct net_device *dev); ++static void ar231x_tx_timeout(struct net_device *dev); ++ ++static int ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum); ++static int ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, u16 value); ++static int ar231x_mdiobus_reset(struct mii_bus *bus); ++static int ar231x_mdiobus_probe (struct net_device *dev); ++static void ar231x_adjust_link(struct net_device *dev); ++ ++#ifndef ERR ++#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args) ++#endif ++ ++#ifdef CONFIG_NET_POLL_CONTROLLER ++static void ++ar231x_netpoll(struct net_device *dev) ++{ ++ unsigned long flags; ++ ++ local_irq_save(flags); ++ ar231x_interrupt(dev->irq, dev); ++ local_irq_restore(flags); ++} ++#endif ++ ++static const struct net_device_ops ar231x_ops = { ++ .ndo_open = ar231x_open, ++ .ndo_stop = ar231x_close, ++ .ndo_start_xmit = ar231x_start_xmit, ++ .ndo_set_multicast_list = ar231x_multicast_list, ++ .ndo_do_ioctl = ar231x_ioctl, ++ .ndo_change_mtu = eth_change_mtu, ++ .ndo_validate_addr = eth_validate_addr, ++ .ndo_set_mac_address = eth_mac_addr, ++ .ndo_tx_timeout = ar231x_tx_timeout, ++#ifdef CONFIG_NET_POLL_CONTROLLER ++ .ndo_poll_controller = ar231x_netpoll, ++#endif ++}; ++ ++int __init ar231x_probe(struct platform_device *pdev) ++{ ++ struct net_device *dev; ++ struct ar231x_private *sp; ++ struct resource *res; ++ unsigned long ar_eth_base; ++ char buf[64]; ++ ++ dev = alloc_etherdev(sizeof(struct ar231x_private)); ++ ++ if (dev == NULL) { ++ printk(KERN_ERR ++ "ar231x: Unable to allocate net_device structure!\n"); ++ return -ENOMEM; ++ } ++ ++ platform_set_drvdata(pdev, dev); ++ ++ sp = netdev_priv(dev); ++ sp->dev = dev; ++ sp->cfg = pdev->dev.platform_data; ++ ++ sprintf(buf, "eth%d_membase", pdev->id); ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, buf); ++ if (!res) ++ return -ENODEV; ++ ++ sp->link = 0; ++ ar_eth_base = res->start; ++ ++ sprintf(buf, "eth%d_irq", pdev->id); ++ dev->irq = platform_get_irq_byname(pdev, buf); ++ ++ spin_lock_init(&sp->lock); ++ ++ dev->features |= NETIF_F_HIGHDMA; ++ dev->netdev_ops = &ar231x_ops; ++ ++ tasklet_init(&sp->rx_tasklet, rx_tasklet_func, (unsigned long) dev); ++ tasklet_disable(&sp->rx_tasklet); ++ ++ sp->eth_regs = ++ ioremap_nocache(virt_to_phys(ar_eth_base), sizeof(*sp->eth_regs)); ++ if (!sp->eth_regs) { ++ printk("Can't remap eth registers\n"); ++ return (-ENXIO); ++ } ++ ++ /* ++ * When there's only one MAC, PHY regs are typically on ENET0, ++ * even though the MAC might be on ENET1. ++ * Needto remap PHY regs separately in this case ++ */ ++ if (virt_to_phys(ar_eth_base) == virt_to_phys(sp->phy_regs)) ++ sp->phy_regs = sp->eth_regs; ++ else { ++ sp->phy_regs = ++ ioremap_nocache(virt_to_phys(sp->cfg->phy_base), ++ sizeof(*sp->phy_regs)); ++ if (!sp->phy_regs) { ++ printk("Can't remap phy registers\n"); ++ return (-ENXIO); ++ } ++ } ++ ++ sp->dma_regs = ++ ioremap_nocache(virt_to_phys(ar_eth_base + 0x1000), ++ sizeof(*sp->dma_regs)); ++ dev->base_addr = (unsigned int) sp->dma_regs; ++ if (!sp->dma_regs) { ++ printk("Can't remap DMA registers\n"); ++ return (-ENXIO); ++ } ++ ++ sp->int_regs = ioremap_nocache(virt_to_phys(sp->cfg->reset_base), 4); ++ if (!sp->int_regs) { ++ printk("Can't remap INTERRUPT registers\n"); ++ return (-ENXIO); ++ } ++ ++ strncpy(sp->name, "Atheros AR231x", sizeof(sp->name) - 1); ++ sp->name[sizeof(sp->name) - 1] = '\0'; ++ memcpy(dev->dev_addr, sp->cfg->macaddr, 6); ++ ++ if (ar231x_init(dev)) { ++ /* ++ * ar231x_init() calls ar231x_init_cleanup() on error. ++ */ ++ kfree(dev); ++ return -ENODEV; ++ } ++ ++ if (register_netdev(dev)) { ++ printk("%s: register_netdev failed\n", __func__); ++ return -1; ++ } ++ ++ printk("%s: %s: %02x:%02x:%02x:%02x:%02x:%02x, irq %d\n", ++ dev->name, sp->name, ++ dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], ++ dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5], dev->irq); ++ ++ sp->mii_bus = mdiobus_alloc(); ++ if (sp->mii_bus == NULL) ++ return -1; ++ ++ sp->mii_bus->priv = dev; ++ sp->mii_bus->read = ar231x_mdiobus_read; ++ sp->mii_bus->write = ar231x_mdiobus_write; ++ sp->mii_bus->reset = ar231x_mdiobus_reset; ++ sp->mii_bus->name = "ar231x_eth_mii"; ++ snprintf(sp->mii_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id); ++ sp->mii_bus->irq = kmalloc(sizeof(int), GFP_KERNEL); ++ *sp->mii_bus->irq = PHY_POLL; ++ ++ mdiobus_register(sp->mii_bus); ++ ++ if (ar231x_mdiobus_probe(dev) != 0) { ++ printk(KERN_ERR "%s: mdiobus_probe failed\n", dev->name); ++ rx_tasklet_cleanup(dev); ++ ar231x_init_cleanup(dev); ++ unregister_netdev(dev); ++ kfree(dev); ++ return -ENODEV; ++ } ++ ++ /* start link poll timer */ ++ ar231x_setup_timer(dev); ++ ++ return 0; ++} ++ ++ ++static void ar231x_multicast_list(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ unsigned int filter; ++ ++ filter = sp->eth_regs->mac_control; ++ ++ if (dev->flags & IFF_PROMISC) ++ filter |= MAC_CONTROL_PR; ++ else ++ filter &= ~MAC_CONTROL_PR; ++ if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 0)) ++ filter |= MAC_CONTROL_PM; ++ else ++ filter &= ~MAC_CONTROL_PM; ++ ++ sp->eth_regs->mac_control = filter; ++} ++ ++static void rx_tasklet_cleanup(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ ++ /* ++ * Tasklet may be scheduled. Need to get it removed from the list ++ * since we're about to free the struct. ++ */ ++ ++ sp->unloading = 1; ++ tasklet_enable(&sp->rx_tasklet); ++ tasklet_kill(&sp->rx_tasklet); ++} ++ ++static int __devexit ar231x_remove(struct platform_device *pdev) ++{ ++ struct net_device *dev = platform_get_drvdata(pdev); ++ struct ar231x_private *sp = netdev_priv(dev); ++ rx_tasklet_cleanup(dev); ++ ar231x_init_cleanup(dev); ++ unregister_netdev(dev); ++ mdiobus_unregister(sp->mii_bus); ++ mdiobus_free(sp->mii_bus); ++ kfree(dev); ++ return 0; ++} ++ ++ ++/* ++ * Restart the AR2313 ethernet controller. ++ */ ++static int ar231x_restart(struct net_device *dev) ++{ ++ /* disable interrupts */ ++ disable_irq(dev->irq); ++ ++ /* stop mac */ ++ ar231x_halt(dev); ++ ++ /* initialize */ ++ ar231x_init(dev); ++ ++ /* enable interrupts */ ++ enable_irq(dev->irq); ++ ++ return 0; ++} ++ ++static struct platform_driver ar231x_driver = { ++ .driver.name = "ar231x-eth", ++ .probe = ar231x_probe, ++ .remove = __devexit_p(ar231x_remove), ++}; ++ ++int __init ar231x_module_init(void) ++{ ++ return platform_driver_register(&ar231x_driver); ++} ++ ++void __exit ar231x_module_cleanup(void) ++{ ++ platform_driver_unregister(&ar231x_driver); ++} ++ ++module_init(ar231x_module_init); ++module_exit(ar231x_module_cleanup); ++ ++ ++static void ar231x_free_descriptors(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ if (sp->rx_ring != NULL) { ++ kfree((void *) KSEG0ADDR(sp->rx_ring)); ++ sp->rx_ring = NULL; ++ sp->tx_ring = NULL; ++ } ++} ++ ++ ++static int ar231x_allocate_descriptors(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ int size; ++ int j; ++ ar231x_descr_t *space; ++ ++ if (sp->rx_ring != NULL) { ++ printk("%s: already done.\n", __FUNCTION__); ++ return 0; ++ } ++ ++ size = ++ (sizeof(ar231x_descr_t) * (AR2313_DESCR_ENTRIES * AR2313_QUEUES)); ++ space = kmalloc(size, GFP_KERNEL); ++ if (space == NULL) ++ return 1; ++ ++ /* invalidate caches */ ++ dma_cache_inv((unsigned int) space, size); ++ ++ /* now convert pointer to KSEG1 */ ++ space = (ar231x_descr_t *) KSEG1ADDR(space); ++ ++ memset((void *) space, 0, size); ++ ++ sp->rx_ring = space; ++ space += AR2313_DESCR_ENTRIES; ++ ++ sp->tx_ring = space; ++ space += AR2313_DESCR_ENTRIES; ++ ++ /* Initialize the transmit Descriptors */ ++ for (j = 0; j < AR2313_DESCR_ENTRIES; j++) { ++ ar231x_descr_t *td = &sp->tx_ring[j]; ++ td->status = 0; ++ td->devcs = DMA_TX1_CHAINED; ++ td->addr = 0; ++ td->descr = ++ virt_to_phys(&sp-> ++ tx_ring[(j + 1) & (AR2313_DESCR_ENTRIES - 1)]); ++ } ++ ++ return 0; ++} ++ ++ ++/* ++ * Generic cleanup handling data allocated during init. Used when the ++ * module is unloaded or if an error occurs during initialization ++ */ ++static void ar231x_init_cleanup(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ struct sk_buff *skb; ++ int j; ++ ++ ar231x_free_descriptors(dev); ++ ++ if (sp->eth_regs) ++ iounmap((void *) sp->eth_regs); ++ if (sp->dma_regs) ++ iounmap((void *) sp->dma_regs); ++ ++ if (sp->rx_skb) { ++ for (j = 0; j < AR2313_DESCR_ENTRIES; j++) { ++ skb = sp->rx_skb[j]; ++ if (skb) { ++ sp->rx_skb[j] = NULL; ++ dev_kfree_skb(skb); ++ } ++ } ++ kfree(sp->rx_skb); ++ sp->rx_skb = NULL; ++ } ++ ++ if (sp->tx_skb) { ++ for (j = 0; j < AR2313_DESCR_ENTRIES; j++) { ++ skb = sp->tx_skb[j]; ++ if (skb) { ++ sp->tx_skb[j] = NULL; ++ dev_kfree_skb(skb); ++ } ++ } ++ kfree(sp->tx_skb); ++ sp->tx_skb = NULL; ++ } ++} ++ ++static int ar231x_setup_timer(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ ++ init_timer(&sp->link_timer); ++ ++ sp->link_timer.function = ar231x_link_timer_fn; ++ sp->link_timer.data = (int) dev; ++ sp->link_timer.expires = jiffies + HZ; ++ ++ add_timer(&sp->link_timer); ++ return 0; ++ ++} ++ ++static void ar231x_link_timer_fn(unsigned long data) ++{ ++ struct net_device *dev = (struct net_device *) data; ++ struct ar231x_private *sp = netdev_priv(dev); ++ ++ // see if the link status changed ++ // This was needed to make sure we set the PHY to the ++ // autonegotiated value of half or full duplex. ++ ar231x_check_link(dev); ++ ++ // Loop faster when we don't have link. ++ // This was needed to speed up the AP bootstrap time. ++ if (sp->link == 0) { ++ mod_timer(&sp->link_timer, jiffies + HZ / 2); ++ } else { ++ mod_timer(&sp->link_timer, jiffies + LINK_TIMER); ++ } ++} ++ ++static void ar231x_check_link(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ u16 phyData; ++ ++ phyData = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_BMSR); ++ if (sp->phyData != phyData) { ++ if (phyData & BMSR_LSTATUS) { ++ /* link is present, ready link partner ability to deterine ++ duplexity */ ++ int duplex = 0; ++ u16 reg; ++ ++ sp->link = 1; ++ reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_BMCR); ++ if (reg & BMCR_ANENABLE) { ++ /* auto neg enabled */ ++ reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_LPA); ++ duplex = (reg & (LPA_100FULL | LPA_10FULL)) ? 1 : 0; ++ } else { ++ /* no auto neg, just read duplex config */ ++ duplex = (reg & BMCR_FULLDPLX) ? 1 : 0; ++ } ++ ++ printk(KERN_INFO "%s: Configuring MAC for %s duplex\n", ++ dev->name, (duplex) ? "full" : "half"); ++ ++ if (duplex) { ++ /* full duplex */ ++ sp->eth_regs->mac_control = ++ ((sp->eth_regs-> ++ mac_control | MAC_CONTROL_F) & ~MAC_CONTROL_DRO); ++ } else { ++ /* half duplex */ ++ sp->eth_regs->mac_control = ++ ((sp->eth_regs-> ++ mac_control | MAC_CONTROL_DRO) & ~MAC_CONTROL_F); ++ } ++ } else { ++ /* no link */ ++ sp->link = 0; ++ } ++ sp->phyData = phyData; ++ } ++} ++ ++static int ar231x_reset_reg(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ unsigned int ethsal, ethsah; ++ unsigned int flags; ++ ++ *sp->int_regs |= sp->cfg->reset_mac; ++ mdelay(10); ++ *sp->int_regs &= ~sp->cfg->reset_mac; ++ mdelay(10); ++ *sp->int_regs |= sp->cfg->reset_phy; ++ mdelay(10); ++ *sp->int_regs &= ~sp->cfg->reset_phy; ++ mdelay(10); ++ ++ sp->dma_regs->bus_mode = (DMA_BUS_MODE_SWR); ++ mdelay(10); ++ sp->dma_regs->bus_mode = ++ ((32 << DMA_BUS_MODE_PBL_SHIFT) | DMA_BUS_MODE_BLE); ++ ++ /* enable interrupts */ ++ sp->dma_regs->intr_ena = (DMA_STATUS_AIS | ++ DMA_STATUS_NIS | ++ DMA_STATUS_RI | ++ DMA_STATUS_TI | DMA_STATUS_FBE); ++ sp->dma_regs->xmt_base = virt_to_phys(sp->tx_ring); ++ sp->dma_regs->rcv_base = virt_to_phys(sp->rx_ring); ++ sp->dma_regs->control = ++ (DMA_CONTROL_SR | DMA_CONTROL_ST | DMA_CONTROL_SF); ++ ++ sp->eth_regs->flow_control = (FLOW_CONTROL_FCE); ++ sp->eth_regs->vlan_tag = (0x8100); ++ ++ /* Enable Ethernet Interface */ ++ flags = (MAC_CONTROL_TE | /* transmit enable */ ++ MAC_CONTROL_PM | /* pass mcast */ ++ MAC_CONTROL_F | /* full duplex */ ++ MAC_CONTROL_HBD); /* heart beat disabled */ ++ ++ if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */ ++ flags |= MAC_CONTROL_PR; ++ } ++ sp->eth_regs->mac_control = flags; ++ ++ /* Set all Ethernet station address registers to their initial values */ ++ ethsah = ((((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) | ++ (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF)); ++ ++ ethsal = ((((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) | ++ (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) | ++ (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) | ++ (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF)); ++ ++ sp->eth_regs->mac_addr[0] = ethsah; ++ sp->eth_regs->mac_addr[1] = ethsal; ++ ++ mdelay(10); ++ ++ return (0); ++} ++ ++ ++static int ar231x_init(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ int ecode = 0; ++ ++ /* ++ * Allocate descriptors ++ */ ++ if (ar231x_allocate_descriptors(dev)) { ++ printk("%s: %s: ar231x_allocate_descriptors failed\n", ++ dev->name, __FUNCTION__); ++ ecode = -EAGAIN; ++ goto init_error; ++ } ++ ++ /* ++ * Get the memory for the skb rings. ++ */ ++ if (sp->rx_skb == NULL) { ++ sp->rx_skb = ++ kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES, ++ GFP_KERNEL); ++ if (!(sp->rx_skb)) { ++ printk("%s: %s: rx_skb kmalloc failed\n", ++ dev->name, __FUNCTION__); ++ ecode = -EAGAIN; ++ goto init_error; ++ } ++ } ++ memset(sp->rx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES); ++ ++ if (sp->tx_skb == NULL) { ++ sp->tx_skb = ++ kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES, ++ GFP_KERNEL); ++ if (!(sp->tx_skb)) { ++ printk("%s: %s: tx_skb kmalloc failed\n", ++ dev->name, __FUNCTION__); ++ ecode = -EAGAIN; ++ goto init_error; ++ } ++ } ++ memset(sp->tx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES); ++ ++ /* ++ * Set tx_csm before we start receiving interrupts, otherwise ++ * the interrupt handler might think it is supposed to process ++ * tx ints before we are up and running, which may cause a null ++ * pointer access in the int handler. ++ */ ++ sp->rx_skbprd = 0; ++ sp->cur_rx = 0; ++ sp->tx_prd = 0; ++ sp->tx_csm = 0; ++ ++ /* ++ * Zero the stats before starting the interface ++ */ ++ memset(&dev->stats, 0, sizeof(dev->stats)); ++ ++ /* ++ * We load the ring here as there seem to be no way to tell the ++ * firmware to wipe the ring without re-initializing it. ++ */ ++ ar231x_load_rx_ring(dev, RX_RING_SIZE); ++ ++ /* ++ * Init hardware ++ */ ++ ar231x_reset_reg(dev); ++ ++ /* ++ * Get the IRQ ++ */ ++ ecode = ++ request_irq(dev->irq, &ar231x_interrupt, ++ IRQF_DISABLED | IRQF_SAMPLE_RANDOM, ++ dev->name, dev); ++ if (ecode) { ++ printk(KERN_WARNING "%s: %s: Requested IRQ %d is busy\n", ++ dev->name, __FUNCTION__, dev->irq); ++ goto init_error; ++ } ++ ++ ++ tasklet_enable(&sp->rx_tasklet); ++ ++ return 0; ++ ++ init_error: ++ ar231x_init_cleanup(dev); ++ return ecode; ++} ++ ++/* ++ * Load the rx ring. ++ * ++ * Loading rings is safe without holding the spin lock since this is ++ * done only before the device is enabled, thus no interrupts are ++ * generated and by the interrupt handler/tasklet handler. ++ */ ++static void ar231x_load_rx_ring(struct net_device *dev, int nr_bufs) ++{ ++ ++ struct ar231x_private *sp = netdev_priv(dev); ++ short i, idx; ++ ++ idx = sp->rx_skbprd; ++ ++ for (i = 0; i < nr_bufs; i++) { ++ struct sk_buff *skb; ++ ar231x_descr_t *rd; ++ ++ if (sp->rx_skb[idx]) ++ break; ++ ++ skb = netdev_alloc_skb(dev, AR2313_BUFSIZE); ++ if (!skb) { ++ printk("\n\n\n\n %s: No memory in system\n\n\n\n", ++ __FUNCTION__); ++ break; ++ } ++ ++ /* ++ * Make sure IP header starts on a fresh cache line. ++ */ ++ skb->dev = dev; ++ skb_reserve(skb, RX_OFFSET); ++ sp->rx_skb[idx] = skb; ++ ++ rd = (ar231x_descr_t *) & sp->rx_ring[idx]; ++ ++ /* initialize dma descriptor */ ++ rd->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) | ++ DMA_RX1_CHAINED); ++ rd->addr = virt_to_phys(skb->data); ++ rd->descr = ++ virt_to_phys(&sp-> ++ rx_ring[(idx + 1) & (AR2313_DESCR_ENTRIES - 1)]); ++ rd->status = DMA_RX_OWN; ++ ++ idx = DSC_NEXT(idx); ++ } ++ ++ if (i) ++ sp->rx_skbprd = idx; ++ ++ return; ++} ++ ++#define AR2313_MAX_PKTS_PER_CALL 64 ++ ++static int ar231x_rx_int(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ struct sk_buff *skb, *skb_new; ++ ar231x_descr_t *rxdesc; ++ unsigned int status; ++ u32 idx; ++ int pkts = 0; ++ int rval; ++ ++ idx = sp->cur_rx; ++ ++ /* process at most the entire ring and then wait for another interrupt ++ */ ++ while (1) { ++ ++ rxdesc = &sp->rx_ring[idx]; ++ status = rxdesc->status; ++ if (status & DMA_RX_OWN) { ++ /* SiByte owns descriptor or descr not yet filled in */ ++ rval = 0; ++ break; ++ } ++ ++ if (++pkts > AR2313_MAX_PKTS_PER_CALL) { ++ rval = 1; ++ break; ++ } ++ ++ if ((status & DMA_RX_ERROR) && !(status & DMA_RX_LONG)) { ++ dev->stats.rx_errors++; ++ dev->stats.rx_dropped++; ++ ++ /* add statistics counters */ ++ if (status & DMA_RX_ERR_CRC) ++ dev->stats.rx_crc_errors++; ++ if (status & DMA_RX_ERR_COL) ++ dev->stats.rx_over_errors++; ++ if (status & DMA_RX_ERR_LENGTH) ++ dev->stats.rx_length_errors++; ++ if (status & DMA_RX_ERR_RUNT) ++ dev->stats.rx_over_errors++; ++ if (status & DMA_RX_ERR_DESC) ++ dev->stats.rx_over_errors++; ++ ++ } else { ++ /* alloc new buffer. */ ++ skb_new = netdev_alloc_skb(dev, AR2313_BUFSIZE + RX_OFFSET); ++ if (skb_new != NULL) { ++ ++ skb = sp->rx_skb[idx]; ++ /* set skb */ ++ skb_put(skb, ++ ((status >> DMA_RX_LEN_SHIFT) & 0x3fff) - CRC_LEN); ++ ++ dev->stats.rx_bytes += skb->len; ++ skb->protocol = eth_type_trans(skb, dev); ++ /* pass the packet to upper layers */ ++ netif_rx(skb); ++ ++ skb_new->dev = dev; ++ /* 16 bit align */ ++ skb_reserve(skb_new, RX_OFFSET); ++ /* reset descriptor's curr_addr */ ++ rxdesc->addr = virt_to_phys(skb_new->data); ++ ++ dev->stats.rx_packets++; ++ sp->rx_skb[idx] = skb_new; ++ } else { ++ dev->stats.rx_dropped++; ++ } ++ } ++ ++ rxdesc->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) | ++ DMA_RX1_CHAINED); ++ rxdesc->status = DMA_RX_OWN; ++ ++ idx = DSC_NEXT(idx); ++ } ++ ++ sp->cur_rx = idx; ++ ++ return rval; ++} ++ ++ ++static void ar231x_tx_int(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ u32 idx; ++ struct sk_buff *skb; ++ ar231x_descr_t *txdesc; ++ unsigned int status = 0; ++ ++ idx = sp->tx_csm; ++ ++ while (idx != sp->tx_prd) { ++ txdesc = &sp->tx_ring[idx]; ++ ++ if ((status = txdesc->status) & DMA_TX_OWN) { ++ /* ar231x dma still owns descr */ ++ break; ++ } ++ /* done with this descriptor */ ++ dma_unmap_single(NULL, txdesc->addr, ++ txdesc->devcs & DMA_TX1_BSIZE_MASK, ++ DMA_TO_DEVICE); ++ txdesc->status = 0; ++ ++ if (status & DMA_TX_ERROR) { ++ dev->stats.tx_errors++; ++ dev->stats.tx_dropped++; ++ if (status & DMA_TX_ERR_UNDER) ++ dev->stats.tx_fifo_errors++; ++ if (status & DMA_TX_ERR_HB) ++ dev->stats.tx_heartbeat_errors++; ++ if (status & (DMA_TX_ERR_LOSS | DMA_TX_ERR_LINK)) ++ dev->stats.tx_carrier_errors++; ++ if (status & (DMA_TX_ERR_LATE | ++ DMA_TX_ERR_COL | ++ DMA_TX_ERR_JABBER | DMA_TX_ERR_DEFER)) ++ dev->stats.tx_aborted_errors++; ++ } else { ++ /* transmit OK */ ++ dev->stats.tx_packets++; ++ } ++ ++ skb = sp->tx_skb[idx]; ++ sp->tx_skb[idx] = NULL; ++ idx = DSC_NEXT(idx); ++ dev->stats.tx_bytes += skb->len; ++ dev_kfree_skb_irq(skb); ++ } ++ ++ sp->tx_csm = idx; ++ ++ return; ++} ++ ++ ++static void rx_tasklet_func(unsigned long data) ++{ ++ struct net_device *dev = (struct net_device *) data; ++ struct ar231x_private *sp = netdev_priv(dev); ++ ++ if (sp->unloading) { ++ return; ++ } ++ ++ if (ar231x_rx_int(dev)) { ++ tasklet_hi_schedule(&sp->rx_tasklet); ++ } else { ++ unsigned long flags; ++ spin_lock_irqsave(&sp->lock, flags); ++ sp->dma_regs->intr_ena |= DMA_STATUS_RI; ++ spin_unlock_irqrestore(&sp->lock, flags); ++ } ++} ++ ++static void rx_schedule(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ ++ sp->dma_regs->intr_ena &= ~DMA_STATUS_RI; ++ ++ tasklet_hi_schedule(&sp->rx_tasklet); ++} ++ ++static irqreturn_t ar231x_interrupt(int irq, void *dev_id) ++{ ++ struct net_device *dev = (struct net_device *) dev_id; ++ struct ar231x_private *sp = netdev_priv(dev); ++ unsigned int status, enabled; ++ ++ /* clear interrupt */ ++ /* ++ * Don't clear RI bit if currently disabled. ++ */ ++ status = sp->dma_regs->status; ++ enabled = sp->dma_regs->intr_ena; ++ sp->dma_regs->status = status & enabled; ++ ++ if (status & DMA_STATUS_NIS) { ++ /* normal status */ ++ /* ++ * Don't schedule rx processing if interrupt ++ * is already disabled. ++ */ ++ if (status & enabled & DMA_STATUS_RI) { ++ /* receive interrupt */ ++ rx_schedule(dev); ++ } ++ if (status & DMA_STATUS_TI) { ++ /* transmit interrupt */ ++ ar231x_tx_int(dev); ++ } ++ } ++ ++ /* abnormal status */ ++ if (status & (DMA_STATUS_FBE | DMA_STATUS_TPS)) { ++ ar231x_restart(dev); ++ } ++ return IRQ_HANDLED; ++} ++ ++ ++static int ar231x_open(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ unsigned int ethsal, ethsah; ++ ++ /* reset the hardware, in case the MAC address changed */ ++ ethsah = ((((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) | ++ (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF)); ++ ++ ethsal = ((((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) | ++ (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) | ++ (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) | ++ (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF)); ++ ++ sp->eth_regs->mac_addr[0] = ethsah; ++ sp->eth_regs->mac_addr[1] = ethsal; ++ ++ mdelay(10); ++ ++ dev->mtu = 1500; ++ netif_start_queue(dev); ++ ++ sp->eth_regs->mac_control |= MAC_CONTROL_RE; ++ ++ return 0; ++} ++ ++static void ar231x_tx_timeout(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ unsigned long flags; ++ ++ spin_lock_irqsave(&sp->lock, flags); ++ ar231x_restart(dev); ++ spin_unlock_irqrestore(&sp->lock, flags); ++} ++ ++static void ar231x_halt(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ int j; ++ ++ tasklet_disable(&sp->rx_tasklet); ++ ++ /* kill the MAC */ ++ sp->eth_regs->mac_control &= ~(MAC_CONTROL_RE | /* disable Receives */ ++ MAC_CONTROL_TE); /* disable Transmits */ ++ /* stop dma */ ++ sp->dma_regs->control = 0; ++ sp->dma_regs->bus_mode = DMA_BUS_MODE_SWR; ++ ++ /* place phy and MAC in reset */ ++ *sp->int_regs |= (sp->cfg->reset_mac | sp->cfg->reset_phy); ++ ++ /* free buffers on tx ring */ ++ for (j = 0; j < AR2313_DESCR_ENTRIES; j++) { ++ struct sk_buff *skb; ++ ar231x_descr_t *txdesc; ++ ++ txdesc = &sp->tx_ring[j]; ++ txdesc->descr = 0; ++ ++ skb = sp->tx_skb[j]; ++ if (skb) { ++ dev_kfree_skb(skb); ++ sp->tx_skb[j] = NULL; ++ } ++ } ++} ++ ++/* ++ * close should do nothing. Here's why. It's called when ++ * 'ifconfig bond0 down' is run. If it calls free_irq then ++ * the irq is gone forever ! When bond0 is made 'up' again, ++ * the ar231x_open () does not call request_irq (). Worse, ++ * the call to ar231x_halt() generates a WDOG reset due to ++ * the write to 'sp->int_regs' and the box reboots. ++ * Commenting this out is good since it allows the ++ * system to resume when bond0 is made up again. ++ */ ++static int ar231x_close(struct net_device *dev) ++{ ++#if 0 ++ /* ++ * Disable interrupts ++ */ ++ disable_irq(dev->irq); ++ ++ /* ++ * Without (or before) releasing irq and stopping hardware, this ++ * is an absolute non-sense, by the way. It will be reset instantly ++ * by the first irq. ++ */ ++ netif_stop_queue(dev); ++ ++ /* stop the MAC and DMA engines */ ++ ar231x_halt(dev); ++ ++ /* release the interrupt */ ++ free_irq(dev->irq, dev); ++ ++#endif ++ return 0; ++} ++ ++static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ ar231x_descr_t *td; ++ u32 idx; ++ ++ idx = sp->tx_prd; ++ td = &sp->tx_ring[idx]; ++ ++ if (td->status & DMA_TX_OWN) { ++ /* free skbuf and lie to the caller that we sent it out */ ++ dev->stats.tx_dropped++; ++ dev_kfree_skb(skb); ++ ++ /* restart transmitter in case locked */ ++ sp->dma_regs->xmt_poll = 0; ++ return 0; ++ } ++ ++ /* Setup the transmit descriptor. */ ++ td->devcs = ((skb->len << DMA_TX1_BSIZE_SHIFT) | ++ (DMA_TX1_LS | DMA_TX1_IC | DMA_TX1_CHAINED)); ++ td->addr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE); ++ td->status = DMA_TX_OWN; ++ ++ /* kick transmitter last */ ++ sp->dma_regs->xmt_poll = 0; ++ ++ sp->tx_skb[idx] = skb; ++ idx = DSC_NEXT(idx); ++ sp->tx_prd = idx; ++ ++ return 0; ++} ++ ++static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) ++{ ++ struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_data; ++ struct ar231x_private *sp = netdev_priv(dev); ++ int ret; ++ ++ switch (cmd) { ++ ++ case SIOCETHTOOL: ++ spin_lock_irq(&sp->lock); ++ ret = phy_ethtool_ioctl(sp->phy_dev, (void *) ifr->ifr_data); ++ spin_unlock_irq(&sp->lock); ++ return ret; ++ ++ case SIOCSIFHWADDR: ++ if (copy_from_user ++ (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr))) ++ return -EFAULT; ++ return 0; ++ ++ case SIOCGIFHWADDR: ++ if (copy_to_user ++ (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr))) ++ return -EFAULT; ++ return 0; ++ ++ case SIOCGMIIPHY: ++ case SIOCGMIIREG: ++ case SIOCSMIIREG: ++ return phy_mii_ioctl(sp->phy_dev, data, cmd); ++ ++ default: ++ break; ++ } ++ ++ return -EOPNOTSUPP; ++} ++ ++static void ar231x_adjust_link(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ unsigned int mc; ++ ++ if (!sp->phy_dev->link) ++ return; ++ ++ if (sp->phy_dev->duplex != sp->oldduplex) { ++ mc = readl(&sp->eth_regs->mac_control); ++ mc &= ~(MAC_CONTROL_F | MAC_CONTROL_DRO); ++ if (sp->phy_dev->duplex) ++ mc |= MAC_CONTROL_F; ++ else ++ mc |= MAC_CONTROL_DRO; ++ writel(mc, &sp->eth_regs->mac_control); ++ sp->oldduplex = sp->phy_dev->duplex; ++ } ++} ++ ++#define MII_ADDR(phy, reg) \ ++ ((reg << MII_ADDR_REG_SHIFT) | (phy << MII_ADDR_PHY_SHIFT)) ++ ++static int ++ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum) ++{ ++ struct net_device *const dev = bus->priv; ++ struct ar231x_private *sp = netdev_priv(dev); ++ volatile ETHERNET_STRUCT *ethernet = sp->phy_regs; ++ ++ ethernet->mii_addr = MII_ADDR(phy_addr, regnum); ++ while (ethernet->mii_addr & MII_ADDR_BUSY); ++ return (ethernet->mii_data >> MII_DATA_SHIFT); ++} ++ ++static int ++ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, ++ u16 value) ++{ ++ struct net_device *const dev = bus->priv; ++ struct ar231x_private *sp = netdev_priv(dev); ++ volatile ETHERNET_STRUCT *ethernet = sp->phy_regs; ++ ++ while (ethernet->mii_addr & MII_ADDR_BUSY); ++ ethernet->mii_data = value << MII_DATA_SHIFT; ++ ethernet->mii_addr = MII_ADDR(phy_addr, regnum) | MII_ADDR_WRITE; ++ ++ return 0; ++} ++ ++static int ar231x_mdiobus_reset(struct mii_bus *bus) ++{ ++ struct net_device *const dev = bus->priv; ++ ++ ar231x_reset_reg(dev); ++ ++ return 0; ++} ++ ++static int ar231x_mdiobus_probe (struct net_device *dev) ++{ ++ struct ar231x_private *const sp = netdev_priv(dev); ++ struct phy_device *phydev = NULL; ++ int phy_addr; ++ ++ /* find the first (lowest address) PHY on the current MAC's MII bus */ ++ for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) ++ if (sp->mii_bus->phy_map[phy_addr]) { ++ phydev = sp->mii_bus->phy_map[phy_addr]; ++ sp->phy = phy_addr; ++ break; /* break out with first one found */ ++ } ++ ++ if (!phydev) { ++ printk (KERN_ERR "ar231x: %s: no PHY found\n", dev->name); ++ return -1; ++ } ++ ++ /* now we are supposed to have a proper phydev, to attach to... */ ++ BUG_ON(!phydev); ++ BUG_ON(phydev->attached_dev); ++ ++ phydev = phy_connect(dev, dev_name(&phydev->dev), &ar231x_adjust_link, 0, ++ PHY_INTERFACE_MODE_MII); ++ ++ if (IS_ERR(phydev)) { ++ printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name); ++ return PTR_ERR(phydev); ++ } ++ ++ /* mask with MAC supported features */ ++ phydev->supported &= (SUPPORTED_10baseT_Half ++ | SUPPORTED_10baseT_Full ++ | SUPPORTED_100baseT_Half ++ | SUPPORTED_100baseT_Full ++ | SUPPORTED_Autoneg ++ /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */ ++ | SUPPORTED_MII ++ | SUPPORTED_TP); ++ ++ phydev->advertising = phydev->supported; ++ ++ sp->oldduplex = -1; ++ sp->phy_dev = phydev; ++ ++ printk(KERN_INFO "%s: attached PHY driver [%s] " ++ "(mii_bus:phy_addr=%s)\n", ++ dev->name, phydev->drv->name, dev_name(&phydev->dev)); ++ ++ return 0; ++} ++ +diff -Nur linux-2.6.39-rc7.orig/drivers/net/ar231x.h linux-2.6.39-rc7/drivers/net/ar231x.h +--- linux-2.6.39-rc7.orig/drivers/net/ar231x.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/drivers/net/ar231x.h 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,302 @@ ++/* ++ * ar231x.h: Linux driver for the Atheros AR231x Ethernet device. ++ * ++ * Copyright (C) 2004 by Sameer Dekate ++ * Copyright (C) 2006 Imre Kaloz ++ * Copyright (C) 2006-2009 Felix Fietkau ++ * ++ * Thanks to Atheros for providing hardware and documentation ++ * enabling me to write this driver. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#ifndef _AR2313_H_ ++#define _AR2313_H_ ++ ++#include ++#include ++#include ++#include ++ ++/* ++ * probe link timer - 5 secs ++ */ ++#define LINK_TIMER (5*HZ) ++ ++#define IS_DMA_TX_INT(X) (((X) & (DMA_STATUS_TI)) != 0) ++#define IS_DMA_RX_INT(X) (((X) & (DMA_STATUS_RI)) != 0) ++#define IS_DRIVER_OWNED(X) (((X) & (DMA_TX_OWN)) == 0) ++ ++#define AR2313_TX_TIMEOUT (HZ/4) ++ ++/* ++ * Rings ++ */ ++#define DSC_RING_ENTRIES_SIZE (AR2313_DESCR_ENTRIES * sizeof(struct desc)) ++#define DSC_NEXT(idx) ((idx + 1) & (AR2313_DESCR_ENTRIES - 1)) ++ ++#define AR2313_MBGET 2 ++#define AR2313_MBSET 3 ++#define AR2313_PCI_RECONFIG 4 ++#define AR2313_PCI_DUMP 5 ++#define AR2313_TEST_PANIC 6 ++#define AR2313_TEST_NULLPTR 7 ++#define AR2313_READ_DATA 8 ++#define AR2313_WRITE_DATA 9 ++#define AR2313_GET_VERSION 10 ++#define AR2313_TEST_HANG 11 ++#define AR2313_SYNC 12 ++ ++#define DMA_RX_ERR_CRC BIT(1) ++#define DMA_RX_ERR_DRIB BIT(2) ++#define DMA_RX_ERR_MII BIT(3) ++#define DMA_RX_EV2 BIT(5) ++#define DMA_RX_ERR_COL BIT(6) ++#define DMA_RX_LONG BIT(7) ++#define DMA_RX_LS BIT(8) /* last descriptor */ ++#define DMA_RX_FS BIT(9) /* first descriptor */ ++#define DMA_RX_MF BIT(10) /* multicast frame */ ++#define DMA_RX_ERR_RUNT BIT(11) /* runt frame */ ++#define DMA_RX_ERR_LENGTH BIT(12) /* length error */ ++#define DMA_RX_ERR_DESC BIT(14) /* descriptor error */ ++#define DMA_RX_ERROR BIT(15) /* error summary */ ++#define DMA_RX_LEN_MASK 0x3fff0000 ++#define DMA_RX_LEN_SHIFT 16 ++#define DMA_RX_FILT BIT(30) ++#define DMA_RX_OWN BIT(31) /* desc owned by DMA controller */ ++ ++#define DMA_RX1_BSIZE_MASK 0x000007ff ++#define DMA_RX1_BSIZE_SHIFT 0 ++#define DMA_RX1_CHAINED BIT(24) ++#define DMA_RX1_RER BIT(25) ++ ++#define DMA_TX_ERR_UNDER BIT(1) /* underflow error */ ++#define DMA_TX_ERR_DEFER BIT(2) /* excessive deferral */ ++#define DMA_TX_COL_MASK 0x78 ++#define DMA_TX_COL_SHIFT 3 ++#define DMA_TX_ERR_HB BIT(7) /* hearbeat failure */ ++#define DMA_TX_ERR_COL BIT(8) /* excessive collisions */ ++#define DMA_TX_ERR_LATE BIT(9) /* late collision */ ++#define DMA_TX_ERR_LINK BIT(10) /* no carrier */ ++#define DMA_TX_ERR_LOSS BIT(11) /* loss of carrier */ ++#define DMA_TX_ERR_JABBER BIT(14) /* transmit jabber timeout */ ++#define DMA_TX_ERROR BIT(15) /* frame aborted */ ++#define DMA_TX_OWN BIT(31) /* descr owned by DMA controller */ ++ ++#define DMA_TX1_BSIZE_MASK 0x000007ff ++#define DMA_TX1_BSIZE_SHIFT 0 ++#define DMA_TX1_CHAINED BIT(24) /* chained descriptors */ ++#define DMA_TX1_TER BIT(25) /* transmit end of ring */ ++#define DMA_TX1_FS BIT(29) /* first segment */ ++#define DMA_TX1_LS BIT(30) /* last segment */ ++#define DMA_TX1_IC BIT(31) /* interrupt on completion */ ++ ++#define RCVPKT_LENGTH(X) (X >> 16) /* Received pkt Length */ ++ ++#define MAC_CONTROL_RE BIT(2) /* receive enable */ ++#define MAC_CONTROL_TE BIT(3) /* transmit enable */ ++#define MAC_CONTROL_DC BIT(5) /* Deferral check */ ++#define MAC_CONTROL_ASTP BIT(8) /* Auto pad strip */ ++#define MAC_CONTROL_DRTY BIT(10) /* Disable retry */ ++#define MAC_CONTROL_DBF BIT(11) /* Disable bcast frames */ ++#define MAC_CONTROL_LCC BIT(12) /* late collision ctrl */ ++#define MAC_CONTROL_HP BIT(13) /* Hash Perfect filtering */ ++#define MAC_CONTROL_HASH BIT(14) /* Unicast hash filtering */ ++#define MAC_CONTROL_HO BIT(15) /* Hash only filtering */ ++#define MAC_CONTROL_PB BIT(16) /* Pass Bad frames */ ++#define MAC_CONTROL_IF BIT(17) /* Inverse filtering */ ++#define MAC_CONTROL_PR BIT(18) /* promiscuous mode (valid frames only) */ ++#define MAC_CONTROL_PM BIT(19) /* pass multicast */ ++#define MAC_CONTROL_F BIT(20) /* full-duplex */ ++#define MAC_CONTROL_DRO BIT(23) /* Disable Receive Own */ ++#define MAC_CONTROL_HBD BIT(28) /* heart-beat disabled (MUST BE SET) */ ++#define MAC_CONTROL_BLE BIT(30) /* big endian mode */ ++#define MAC_CONTROL_RA BIT(31) /* receive all (valid and invalid frames) */ ++ ++#define MII_ADDR_BUSY BIT(0) ++#define MII_ADDR_WRITE BIT(1) ++#define MII_ADDR_REG_SHIFT 6 ++#define MII_ADDR_PHY_SHIFT 11 ++#define MII_DATA_SHIFT 0 ++ ++#define FLOW_CONTROL_FCE BIT(1) ++ ++#define DMA_BUS_MODE_SWR BIT(0) /* software reset */ ++#define DMA_BUS_MODE_BLE BIT(7) /* big endian mode */ ++#define DMA_BUS_MODE_PBL_SHIFT 8 /* programmable burst length 32 */ ++#define DMA_BUS_MODE_DBO BIT(20) /* big-endian descriptors */ ++ ++#define DMA_STATUS_TI BIT(0) /* transmit interrupt */ ++#define DMA_STATUS_TPS BIT(1) /* transmit process stopped */ ++#define DMA_STATUS_TU BIT(2) /* transmit buffer unavailable */ ++#define DMA_STATUS_TJT BIT(3) /* transmit buffer timeout */ ++#define DMA_STATUS_UNF BIT(5) /* transmit underflow */ ++#define DMA_STATUS_RI BIT(6) /* receive interrupt */ ++#define DMA_STATUS_RU BIT(7) /* receive buffer unavailable */ ++#define DMA_STATUS_RPS BIT(8) /* receive process stopped */ ++#define DMA_STATUS_ETI BIT(10) /* early transmit interrupt */ ++#define DMA_STATUS_FBE BIT(13) /* fatal bus interrupt */ ++#define DMA_STATUS_ERI BIT(14) /* early receive interrupt */ ++#define DMA_STATUS_AIS BIT(15) /* abnormal interrupt summary */ ++#define DMA_STATUS_NIS BIT(16) /* normal interrupt summary */ ++#define DMA_STATUS_RS_SHIFT 17 /* receive process state */ ++#define DMA_STATUS_TS_SHIFT 20 /* transmit process state */ ++#define DMA_STATUS_EB_SHIFT 23 /* error bits */ ++ ++#define DMA_CONTROL_SR BIT(1) /* start receive */ ++#define DMA_CONTROL_ST BIT(13) /* start transmit */ ++#define DMA_CONTROL_SF BIT(21) /* store and forward */ ++ ++ ++typedef struct { ++ volatile unsigned int status; // OWN, Device control and status. ++ volatile unsigned int devcs; // pkt Control bits + Length ++ volatile unsigned int addr; // Current Address. ++ volatile unsigned int descr; // Next descriptor in chain. ++} ar231x_descr_t; ++ ++ ++ ++// ++// New Combo structure for Both Eth0 AND eth1 ++// ++typedef struct { ++ volatile unsigned int mac_control; /* 0x00 */ ++ volatile unsigned int mac_addr[2]; /* 0x04 - 0x08 */ ++ volatile unsigned int mcast_table[2]; /* 0x0c - 0x10 */ ++ volatile unsigned int mii_addr; /* 0x14 */ ++ volatile unsigned int mii_data; /* 0x18 */ ++ volatile unsigned int flow_control; /* 0x1c */ ++ volatile unsigned int vlan_tag; /* 0x20 */ ++ volatile unsigned int pad[7]; /* 0x24 - 0x3c */ ++ volatile unsigned int ucast_table[8]; /* 0x40-0x5c */ ++ ++} ETHERNET_STRUCT; ++ ++/******************************************************************** ++ * Interrupt controller ++ ********************************************************************/ ++ ++typedef struct { ++ volatile unsigned int wdog_control; /* 0x08 */ ++ volatile unsigned int wdog_timer; /* 0x0c */ ++ volatile unsigned int misc_status; /* 0x10 */ ++ volatile unsigned int misc_mask; /* 0x14 */ ++ volatile unsigned int global_status; /* 0x18 */ ++ volatile unsigned int reserved; /* 0x1c */ ++ volatile unsigned int reset_control; /* 0x20 */ ++} INTERRUPT; ++ ++/******************************************************************** ++ * DMA controller ++ ********************************************************************/ ++typedef struct { ++ volatile unsigned int bus_mode; /* 0x00 (CSR0) */ ++ volatile unsigned int xmt_poll; /* 0x04 (CSR1) */ ++ volatile unsigned int rcv_poll; /* 0x08 (CSR2) */ ++ volatile unsigned int rcv_base; /* 0x0c (CSR3) */ ++ volatile unsigned int xmt_base; /* 0x10 (CSR4) */ ++ volatile unsigned int status; /* 0x14 (CSR5) */ ++ volatile unsigned int control; /* 0x18 (CSR6) */ ++ volatile unsigned int intr_ena; /* 0x1c (CSR7) */ ++ volatile unsigned int rcv_missed; /* 0x20 (CSR8) */ ++ volatile unsigned int reserved[11]; /* 0x24-0x4c (CSR9-19) */ ++ volatile unsigned int cur_tx_buf_addr; /* 0x50 (CSR20) */ ++ volatile unsigned int cur_rx_buf_addr; /* 0x50 (CSR21) */ ++} DMA; ++ ++/* ++ * Struct private for the Sibyte. ++ * ++ * Elements are grouped so variables used by the tx handling goes ++ * together, and will go into the same cache lines etc. in order to ++ * avoid cache line contention between the rx and tx handling on SMP. ++ * ++ * Frequently accessed variables are put at the beginning of the ++ * struct to help the compiler generate better/shorter code. ++ */ ++struct ar231x_private { ++ struct net_device *dev; ++ int version; ++ u32 mb[2]; ++ ++ volatile ETHERNET_STRUCT *phy_regs; ++ volatile ETHERNET_STRUCT *eth_regs; ++ volatile DMA *dma_regs; ++ volatile u32 *int_regs; ++ struct ar231x_eth *cfg; ++ ++ spinlock_t lock; /* Serialise access to device */ ++ ++ /* ++ * RX and TX descriptors, must be adjacent ++ */ ++ ar231x_descr_t *rx_ring; ++ ar231x_descr_t *tx_ring; ++ ++ ++ struct sk_buff **rx_skb; ++ struct sk_buff **tx_skb; ++ ++ /* ++ * RX elements ++ */ ++ u32 rx_skbprd; ++ u32 cur_rx; ++ ++ /* ++ * TX elements ++ */ ++ u32 tx_prd; ++ u32 tx_csm; ++ ++ /* ++ * Misc elements ++ */ ++ char name[48]; ++ struct { ++ u32 address; ++ u32 length; ++ char *mapping; ++ } desc; ++ ++ ++ struct timer_list link_timer; ++ unsigned short phy; /* merlot phy = 1, samsung phy = 0x1f */ ++ unsigned short mac; ++ unsigned short link; /* 0 - link down, 1 - link up */ ++ u16 phyData; ++ ++ struct tasklet_struct rx_tasklet; ++ int unloading; ++ ++ struct phy_device *phy_dev; ++ struct mii_bus *mii_bus; ++ int oldduplex; ++}; ++ ++ ++/* ++ * Prototypes ++ */ ++static int ar231x_init(struct net_device *dev); ++#ifdef TX_TIMEOUT ++static void ar231x_tx_timeout(struct net_device *dev); ++#endif ++static int ar231x_restart(struct net_device *dev); ++static void ar231x_load_rx_ring(struct net_device *dev, int bufs); ++static irqreturn_t ar231x_interrupt(int irq, void *dev_id); ++static int ar231x_open(struct net_device *dev); ++static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev); ++static int ar231x_close(struct net_device *dev); ++static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr, ++ int cmd); ++static void ar231x_init_cleanup(struct net_device *dev); ++static int ar231x_setup_timer(struct net_device *dev); ++static void ar231x_link_timer_fn(unsigned long data); ++static void ar231x_check_link(struct net_device *dev); ++#endif /* _AR2313_H_ */ +diff -Nur linux-2.6.39-rc7.orig/drivers/watchdog/Kconfig linux-2.6.39-rc7/drivers/watchdog/Kconfig +--- linux-2.6.39-rc7.orig/drivers/watchdog/Kconfig 2011-05-10 04:33:54.000000000 +0200 ++++ linux-2.6.39-rc7/drivers/watchdog/Kconfig 2011-05-15 21:34:57.000000000 +0200 +@@ -990,6 +990,12 @@ + To compile this driver as a loadable module, choose M here. + The module will be called bcm63xx_wdt. + ++config ATHEROS_WDT ++ tristate "Atheros wisoc Watchdog Timer" ++ depends on ATHEROS_AR231X ++ help ++ Hardware driver for the Atheros wisoc Watchdog Timer. ++ + # PARISC Architecture + + # POWERPC Architecture +diff -Nur linux-2.6.39-rc7.orig/drivers/watchdog/Makefile linux-2.6.39-rc7/drivers/watchdog/Makefile +--- linux-2.6.39-rc7.orig/drivers/watchdog/Makefile 2011-05-10 04:33:54.000000000 +0200 ++++ linux-2.6.39-rc7/drivers/watchdog/Makefile 2011-05-15 21:34:57.000000000 +0200 +@@ -120,6 +120,7 @@ + obj-$(CONFIG_PNX833X_WDT) += pnx833x_wdt.o + obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o + obj-$(CONFIG_AR7_WDT) += ar7_wdt.o ++obj-$(CONFIG_ATHEROS_WDT) += ar2315-wtd.o + obj-$(CONFIG_TXX9_WDT) += txx9wdt.o + obj-$(CONFIG_OCTEON_WDT) += octeon-wdt.o + octeon-wdt-y := octeon-wdt-main.o octeon-wdt-nmi.o +diff -Nur linux-2.6.39-rc7.orig/drivers/watchdog/ar2315-wtd.c linux-2.6.39-rc7/drivers/watchdog/ar2315-wtd.c +--- linux-2.6.39-rc7.orig/drivers/watchdog/ar2315-wtd.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/drivers/watchdog/ar2315-wtd.c 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,200 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ * Copyright (C) 2008 John Crispin ++ * Based on EP93xx and ifxmips wdt driver ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define CLOCK_RATE 40000000 ++#define HEARTBEAT(x) (x < 1 || x > 90)?(20):(x) ++ ++static int wdt_timeout = 20; ++static int started = 0; ++static int in_use = 0; ++ ++static void ++ar2315_wdt_enable(void) ++{ ++ ar231x_write_reg(AR2315_WD, wdt_timeout * CLOCK_RATE); ++ ar231x_write_reg(AR2315_ISR, 0x80); ++} ++ ++static ssize_t ++ar2315_wdt_write(struct file *file, const char __user *data, size_t len, loff_t *ppos) ++{ ++ if(len) ++ ar2315_wdt_enable(); ++ return len; ++} ++ ++static int ++ar2315_wdt_open(struct inode *inode, struct file *file) ++{ ++ if(in_use) ++ return -EBUSY; ++ ar2315_wdt_enable(); ++ in_use = started = 1; ++ return nonseekable_open(inode, file); ++} ++ ++static int ++ar2315_wdt_release(struct inode *inode, struct file *file) ++{ ++ in_use = 0; ++ return 0; ++} ++ ++static irqreturn_t ++ar2315_wdt_interrupt(int irq, void *dev_id) ++{ ++ if(started) ++ { ++ printk(KERN_CRIT "watchdog expired, rebooting system\n"); ++ emergency_restart(); ++ } else { ++ ar231x_write_reg(AR2315_WDC, 0); ++ ar231x_write_reg(AR2315_WD, 0); ++ ar231x_write_reg(AR2315_ISR, 0x80); ++ } ++ return IRQ_HANDLED; ++} ++ ++static struct watchdog_info ident = { ++ .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, ++ .identity = "ar2315 Watchdog", ++}; ++ ++static int ++ar2315_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) ++{ ++ int new_wdt_timeout; ++ int ret = -ENOIOCTLCMD; ++ ++ switch(cmd) ++ { ++ case WDIOC_GETSUPPORT: ++ ret = copy_to_user((struct watchdog_info __user *)arg, &ident, sizeof(ident)) ? -EFAULT : 0; ++ break; ++ ++ case WDIOC_KEEPALIVE: ++ ar2315_wdt_enable(); ++ ret = 0; ++ break; ++ ++ case WDIOC_SETTIMEOUT: ++ if((ret = get_user(new_wdt_timeout, (int __user *)arg))) ++ break; ++ wdt_timeout = HEARTBEAT(new_wdt_timeout); ++ ar2315_wdt_enable(); ++ break; ++ ++ case WDIOC_GETTIMEOUT: ++ ret = put_user(wdt_timeout, (int __user *)arg); ++ break; ++ } ++ return ret; ++} ++ ++static struct file_operations ar2315_wdt_fops = { ++ .owner = THIS_MODULE, ++ .llseek = no_llseek, ++ .write = ar2315_wdt_write, ++ .unlocked_ioctl = ar2315_wdt_ioctl, ++ .open = ar2315_wdt_open, ++ .release = ar2315_wdt_release, ++}; ++ ++static struct miscdevice ar2315_wdt_miscdev = { ++ .minor = WATCHDOG_MINOR, ++ .name = "watchdog", ++ .fops = &ar2315_wdt_fops, ++}; ++ ++static int ++ar2315_wdt_probe(struct platform_device *dev) ++{ ++ int ret = 0; ++ ++ ar2315_wdt_enable(); ++ ret = request_irq(AR531X_MISC_IRQ_WATCHDOG, ar2315_wdt_interrupt, IRQF_DISABLED, "ar2315_wdt", NULL); ++ if(ret) ++ { ++ printk(KERN_ERR "ar2315wdt: failed to register inetrrupt\n"); ++ goto out; ++ } ++ ++ ret = misc_register(&ar2315_wdt_miscdev); ++ if(ret) ++ printk(KERN_ERR "ar2315wdt: failed to register miscdev\n"); ++ ++out: ++ return ret; ++} ++ ++static int ++ar2315_wdt_remove(struct platform_device *dev) ++{ ++ misc_deregister(&ar2315_wdt_miscdev); ++ free_irq(AR531X_MISC_IRQ_WATCHDOG, NULL); ++ return 0; ++} ++ ++static struct platform_driver ar2315_wdt_driver = { ++ .probe = ar2315_wdt_probe, ++ .remove = ar2315_wdt_remove, ++ .driver = { ++ .name = "ar2315_wdt", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static int __init ++init_ar2315_wdt(void) ++{ ++ int ret = platform_driver_register(&ar2315_wdt_driver); ++ if(ret) ++ printk(KERN_INFO "ar2315_wdt: error registering platfom driver!"); ++ return ret; ++} ++ ++static void __exit ++exit_ar2315_wdt(void) ++{ ++ platform_driver_unregister(&ar2315_wdt_driver); ++} ++ ++module_init(init_ar2315_wdt); ++module_exit(exit_ar2315_wdt); diff --git a/target/linux/patches/3.0.9/gemalto.patch b/target/linux/patches/3.0.9/gemalto.patch new file mode 100644 index 000000000..f3c223b5e --- /dev/null +++ b/target/linux/patches/3.0.9/gemalto.patch @@ -0,0 +1,11 @@ +diff -Nur linux-2.6.36.orig/drivers/tty/serial/serial_cs.c linux-2.6.36/drivers/serial/serial_cs.c +--- linux-2.6.36.orig/drivers/tty/serial/serial_cs.c 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/drivers/tty/serial/serial_cs.c 2010-12-13 23:03:40.000000000 +0100 +@@ -794,6 +794,7 @@ + PCMCIA_DEVICE_MANF_CARD(0x0137, 0x0025), + PCMCIA_DEVICE_MANF_CARD(0x0137, 0x0045), + PCMCIA_DEVICE_MANF_CARD(0x0137, 0x0052), ++ PCMCIA_DEVICE_MANF_CARD(0x0157, 0x0100), /* Gemalto SCR */ + PCMCIA_DEVICE_MANF_CARD(0x016c, 0x0006), /* Psion 56K+Fax */ + PCMCIA_DEVICE_MANF_CARD(0x0200, 0x0001), /* MultiMobile */ + PCMCIA_DEVICE_PROD_ID134("ADV", "TECH", "COMpad-32/85", 0x67459937, 0x916d02ba, 0x8fbe92ae), diff --git a/target/linux/patches/3.0.9/mips-malta.patch b/target/linux/patches/3.0.9/mips-malta.patch new file mode 100644 index 000000000..cc8789dca --- /dev/null +++ b/target/linux/patches/3.0.9/mips-malta.patch @@ -0,0 +1,135 @@ +http://lkml.indiana.edu/hypermail/linux/kernel/1105.3/02199.html + +diff -Nur linux-2.6.39.orig/arch/mips/include/asm/smp-ops.h linux-2.6.39/arch/mips/include/asm/smp-ops.h +--- linux-2.6.39.orig/arch/mips/include/asm/smp-ops.h 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/arch/mips/include/asm/smp-ops.h 2011-08-29 04:39:03.360480881 +0200 +@@ -56,8 +56,43 @@ + + #endif /* !CONFIG_SMP */ + +-extern struct plat_smp_ops up_smp_ops; +-extern struct plat_smp_ops cmp_smp_ops; +-extern struct plat_smp_ops vsmp_smp_ops; ++static inline int register_up_smp_ops(void) ++{ ++#ifdef CONFIG_SMP_UP ++ extern struct plat_smp_ops up_smp_ops; ++ ++ register_smp_ops(&up_smp_ops); ++ ++ return 0; ++#else ++ return -ENODEV; ++#endif ++} ++ ++static inline int register_cmp_smp_ops(void) ++{ ++#ifdef CONFIG_MIPS_CMP ++ extern struct plat_smp_ops cmp_smp_ops; ++ ++ register_smp_ops(&cmp_smp_ops); ++ ++ return 0; ++#else ++ return -ENODEV; ++#endif ++} ++ ++static inline int register_vsmp_smp_ops(void) ++{ ++#ifdef CONFIG_MIPS_MT_SMP ++ extern struct plat_smp_ops vsmp_smp_ops; ++ ++ register_smp_ops(&vsmp_smp_ops); ++ ++ return 0; ++#else ++ return -ENODEV; ++#endif ++} + + #endif /* __ASM_SMP_OPS_H */ +diff -Nur linux-2.6.39.orig/arch/mips/mipssim/sim_setup.c linux-2.6.39/arch/mips/mipssim/sim_setup.c +--- linux-2.6.39.orig/arch/mips/mipssim/sim_setup.c 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/arch/mips/mipssim/sim_setup.c 2011-08-29 04:39:03.390480572 +0200 +@@ -59,18 +59,17 @@ + + prom_meminit(); + +-#ifdef CONFIG_MIPS_MT_SMP +- if (cpu_has_mipsmt) +- register_smp_ops(&vsmp_smp_ops); +- else +- register_smp_ops(&up_smp_ops); +-#endif ++ if (cpu_has_mipsmt) { ++ if (!register_vsmp_smp_ops()) ++ return; ++ + #ifdef CONFIG_MIPS_MT_SMTC +- if (cpu_has_mipsmt) + register_smp_ops(&ssmtc_smp_ops); +- else +- register_smp_ops(&up_smp_ops); ++ return; + #endif ++ } ++ ++ register_up_smp_ops(); + } + + static void __init serial_init(void) +diff -Nur linux-2.6.39.orig/arch/mips/mti-malta/malta-init.c linux-2.6.39/arch/mips/mti-malta/malta-init.c +--- linux-2.6.39.orig/arch/mips/mti-malta/malta-init.c 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/arch/mips/mti-malta/malta-init.c 2011-08-29 04:39:03.700480601 +0200 +@@ -29,6 +29,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -358,15 +359,14 @@ + #ifdef CONFIG_SERIAL_8250_CONSOLE + console_config(); + #endif +-#ifdef CONFIG_MIPS_CMP + /* Early detection of CMP support */ + if (gcmp_probe(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ)) +- register_smp_ops(&cmp_smp_ops); +- else +-#endif +-#ifdef CONFIG_MIPS_MT_SMP +- register_smp_ops(&vsmp_smp_ops); +-#endif ++ if (!register_cmp_smp_ops()) ++ return; ++ ++ if (!register_vsmp_smp_ops()) ++ return; ++ + #ifdef CONFIG_MIPS_MT_SMTC + register_smp_ops(&msmtc_smp_ops); + #endif +diff -Nur linux-2.6.39.orig/arch/mips/pmc-sierra/msp71xx/msp_setup.c linux-2.6.39/arch/mips/pmc-sierra/msp71xx/msp_setup.c +--- linux-2.6.39.orig/arch/mips/pmc-sierra/msp71xx/msp_setup.c 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/arch/mips/pmc-sierra/msp71xx/msp_setup.c 2011-08-29 04:39:03.790480302 +0200 +@@ -228,13 +228,11 @@ + */ + msp_serial_setup(); + +-#ifdef CONFIG_MIPS_MT_SMP +- register_smp_ops(&vsmp_smp_ops); +-#endif +- ++ if (register_vsmp_smp_ops()) { + #ifdef CONFIG_MIPS_MT_SMTC +- register_smp_ops(&msp_smtc_smp_ops); ++ register_smp_ops(&msp_smtc_smp_ops); + #endif ++ } + + #ifdef CONFIG_PMCTWILED + /* diff --git a/target/linux/patches/3.0.9/mmc-host.patch b/target/linux/patches/3.0.9/mmc-host.patch new file mode 100644 index 000000000..3d0e37add --- /dev/null +++ b/target/linux/patches/3.0.9/mmc-host.patch @@ -0,0 +1,36 @@ +diff -Nur linux-2.6.39-rc6.orig/drivers/mmc/host/Kconfig linux-2.6.39-rc6/drivers/mmc/host/Kconfig +--- linux-2.6.39-rc6.orig/drivers/mmc/host/Kconfig 2011-05-04 04:59:13.000000000 +0200 ++++ linux-2.6.39-rc6/drivers/mmc/host/Kconfig 2011-05-10 23:39:01.000000000 +0200 +@@ -253,13 +253,6 @@ + + If unsure, say N. + +-choice +- prompt "Atmel SD/MMC Driver" +- depends on AVR32 || ARCH_AT91 +- default MMC_ATMELMCI if AVR32 +- help +- Choose which driver to use for the Atmel MCI Silicon +- + config MMC_AT91 + tristate "AT91 SD/MMC Card Interface support" + depends on ARCH_AT91 +@@ -268,18 +261,6 @@ + + If unsure, say N. + +-config MMC_ATMELMCI +- tristate "Atmel Multimedia Card Interface support" +- depends on AVR32 || ARCH_AT91 +- help +- This selects the Atmel Multimedia Card Interface driver. If +- you have an AT32 (AVR32) or AT91 platform with a Multimedia +- Card slot, say Y or M here. +- +- If unsure, say N. +- +-endchoice +- + config MMC_ATMELMCI_DMA + bool "Atmel MCI DMA support (EXPERIMENTAL)" + depends on MMC_ATMELMCI && (AVR32 || ARCH_AT91SAM9G45) && DMA_ENGINE && EXPERIMENTAL diff --git a/target/linux/patches/3.0.9/non-static.patch b/target/linux/patches/3.0.9/non-static.patch new file mode 100644 index 000000000..a967703d0 --- /dev/null +++ b/target/linux/patches/3.0.9/non-static.patch @@ -0,0 +1,33 @@ +diff -Nur linux-2.6.39-rc6.orig/fs/namei.c linux-2.6.39-rc6/fs/namei.c +--- linux-2.6.39-rc6.orig/fs/namei.c 2011-05-04 04:59:13.000000000 +0200 ++++ linux-2.6.39-rc6/fs/namei.c 2011-05-05 11:30:14.000000000 +0200 +@@ -1769,7 +1769,7 @@ + * needs parent already locked. Doesn't follow mounts. + * SMP-safe. + */ +-static struct dentry *lookup_hash(struct nameidata *nd) ++struct dentry *lookup_hash(struct nameidata *nd) + { + return __lookup_hash(&nd->last, nd->path.dentry, nd); + } +diff -Nur linux-2.6.39-rc6.orig/fs/splice.c linux-2.6.39-rc6/fs/splice.c +--- linux-2.6.39-rc6.orig/fs/splice.c 2011-05-04 04:59:13.000000000 +0200 ++++ linux-2.6.39-rc6/fs/splice.c 2011-05-05 11:31:04.000000000 +0200 +@@ -1081,7 +1081,7 @@ + /* + * Attempt to initiate a splice from pipe to file. + */ +-static long do_splice_from(struct pipe_inode_info *pipe, struct file *out, ++long do_splice_from(struct pipe_inode_info *pipe, struct file *out, + loff_t *ppos, size_t len, unsigned int flags) + { + ssize_t (*splice_write)(struct pipe_inode_info *, struct file *, +@@ -1109,7 +1109,7 @@ + /* + * Attempt to initiate a splice from a file to a pipe. + */ +-static long do_splice_to(struct file *in, loff_t *ppos, ++long do_splice_to(struct file *in, loff_t *ppos, + struct pipe_inode_info *pipe, size_t len, + unsigned int flags) + { diff --git a/target/linux/patches/3.0.9/ocf-20110720.patch b/target/linux/patches/3.0.9/ocf-20110720.patch new file mode 100644 index 000000000..b5a257324 --- /dev/null +++ b/target/linux/patches/3.0.9/ocf-20110720.patch @@ -0,0 +1,99170 @@ +diff -Nur linux-3.0.4.orig/crypto/Kconfig linux-3.0.4/crypto/Kconfig +--- linux-3.0.4.orig/crypto/Kconfig 2011-08-29 22:56:30.000000000 +0200 ++++ linux-3.0.4/crypto/Kconfig 2011-10-17 04:36:27.356574299 +0200 +@@ -860,3 +860,6 @@ + source "drivers/crypto/Kconfig" + + endif # if CRYPTO ++ ++source "crypto/ocf/Kconfig" ++ +diff -Nur linux-3.0.4.orig/crypto/Kconfig.orig linux-3.0.4/crypto/Kconfig.orig +--- linux-3.0.4.orig/crypto/Kconfig.orig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/Kconfig.orig 2011-08-29 22:56:30.000000000 +0200 +@@ -0,0 +1,862 @@ ++# ++# Generic algorithms support ++# ++config XOR_BLOCKS ++ tristate ++ ++# ++# async_tx api: hardware offloaded memory transfer/transform support ++# ++source "crypto/async_tx/Kconfig" ++ ++# ++# Cryptographic API Configuration ++# ++menuconfig CRYPTO ++ tristate "Cryptographic API" ++ help ++ This option provides the core Cryptographic API. ++ ++if CRYPTO ++ ++comment "Crypto core or helper" ++ ++config CRYPTO_FIPS ++ bool "FIPS 200 compliance" ++ depends on CRYPTO_ANSI_CPRNG && !CRYPTO_MANAGER_DISABLE_TESTS ++ help ++ This options enables the fips boot option which is ++ required if you want to system to operate in a FIPS 200 ++ certification. You should say no unless you know what ++ this is. ++ ++config CRYPTO_ALGAPI ++ tristate ++ select CRYPTO_ALGAPI2 ++ help ++ This option provides the API for cryptographic algorithms. ++ ++config CRYPTO_ALGAPI2 ++ tristate ++ ++config CRYPTO_AEAD ++ tristate ++ select CRYPTO_AEAD2 ++ select CRYPTO_ALGAPI ++ ++config CRYPTO_AEAD2 ++ tristate ++ select CRYPTO_ALGAPI2 ++ ++config CRYPTO_BLKCIPHER ++ tristate ++ select CRYPTO_BLKCIPHER2 ++ select CRYPTO_ALGAPI ++ ++config CRYPTO_BLKCIPHER2 ++ tristate ++ select CRYPTO_ALGAPI2 ++ select CRYPTO_RNG2 ++ select CRYPTO_WORKQUEUE ++ ++config CRYPTO_HASH ++ tristate ++ select CRYPTO_HASH2 ++ select CRYPTO_ALGAPI ++ ++config CRYPTO_HASH2 ++ tristate ++ select CRYPTO_ALGAPI2 ++ ++config CRYPTO_RNG ++ tristate ++ select CRYPTO_RNG2 ++ select CRYPTO_ALGAPI ++ ++config CRYPTO_RNG2 ++ tristate ++ select CRYPTO_ALGAPI2 ++ ++config CRYPTO_PCOMP ++ tristate ++ select CRYPTO_PCOMP2 ++ select CRYPTO_ALGAPI ++ ++config CRYPTO_PCOMP2 ++ tristate ++ select CRYPTO_ALGAPI2 ++ ++config CRYPTO_MANAGER ++ tristate "Cryptographic algorithm manager" ++ select CRYPTO_MANAGER2 ++ help ++ Create default cryptographic template instantiations such as ++ cbc(aes). ++ ++config CRYPTO_MANAGER2 ++ def_tristate CRYPTO_MANAGER || (CRYPTO_MANAGER!=n && CRYPTO_ALGAPI=y) ++ select CRYPTO_AEAD2 ++ select CRYPTO_HASH2 ++ select CRYPTO_BLKCIPHER2 ++ select CRYPTO_PCOMP2 ++ ++config CRYPTO_MANAGER_DISABLE_TESTS ++ bool "Disable run-time self tests" ++ default y ++ depends on CRYPTO_MANAGER2 ++ help ++ Disable run-time self tests that normally take place at ++ algorithm registration. ++ ++config CRYPTO_GF128MUL ++ tristate "GF(2^128) multiplication functions (EXPERIMENTAL)" ++ help ++ Efficient table driven implementation of multiplications in the ++ field GF(2^128). This is needed by some cypher modes. This ++ option will be selected automatically if you select such a ++ cipher mode. Only select this option by hand if you expect to load ++ an external module that requires these functions. ++ ++config CRYPTO_NULL ++ tristate "Null algorithms" ++ select CRYPTO_ALGAPI ++ select CRYPTO_BLKCIPHER ++ select CRYPTO_HASH ++ help ++ These are 'Null' algorithms, used by IPsec, which do nothing. ++ ++config CRYPTO_PCRYPT ++ tristate "Parallel crypto engine (EXPERIMENTAL)" ++ depends on SMP && EXPERIMENTAL ++ select PADATA ++ select CRYPTO_MANAGER ++ select CRYPTO_AEAD ++ help ++ This converts an arbitrary crypto algorithm into a parallel ++ algorithm that executes in kernel threads. ++ ++config CRYPTO_WORKQUEUE ++ tristate ++ ++config CRYPTO_CRYPTD ++ tristate "Software async crypto daemon" ++ select CRYPTO_BLKCIPHER ++ select CRYPTO_HASH ++ select CRYPTO_MANAGER ++ select CRYPTO_WORKQUEUE ++ help ++ This is a generic software asynchronous crypto daemon that ++ converts an arbitrary synchronous software crypto algorithm ++ into an asynchronous algorithm that executes in a kernel thread. ++ ++config CRYPTO_AUTHENC ++ tristate "Authenc support" ++ select CRYPTO_AEAD ++ select CRYPTO_BLKCIPHER ++ select CRYPTO_MANAGER ++ select CRYPTO_HASH ++ help ++ Authenc: Combined mode wrapper for IPsec. ++ This is required for IPSec. ++ ++config CRYPTO_TEST ++ tristate "Testing module" ++ depends on m ++ select CRYPTO_MANAGER ++ help ++ Quick & dirty crypto test module. ++ ++comment "Authenticated Encryption with Associated Data" ++ ++config CRYPTO_CCM ++ tristate "CCM support" ++ select CRYPTO_CTR ++ select CRYPTO_AEAD ++ help ++ Support for Counter with CBC MAC. Required for IPsec. ++ ++config CRYPTO_GCM ++ tristate "GCM/GMAC support" ++ select CRYPTO_CTR ++ select CRYPTO_AEAD ++ select CRYPTO_GHASH ++ help ++ Support for Galois/Counter Mode (GCM) and Galois Message ++ Authentication Code (GMAC). Required for IPSec. ++ ++config CRYPTO_SEQIV ++ tristate "Sequence Number IV Generator" ++ select CRYPTO_AEAD ++ select CRYPTO_BLKCIPHER ++ select CRYPTO_RNG ++ help ++ This IV generator generates an IV based on a sequence number by ++ xoring it with a salt. This algorithm is mainly useful for CTR ++ ++comment "Block modes" ++ ++config CRYPTO_CBC ++ tristate "CBC support" ++ select CRYPTO_BLKCIPHER ++ select CRYPTO_MANAGER ++ help ++ CBC: Cipher Block Chaining mode ++ This block cipher algorithm is required for IPSec. ++ ++config CRYPTO_CTR ++ tristate "CTR support" ++ select CRYPTO_BLKCIPHER ++ select CRYPTO_SEQIV ++ select CRYPTO_MANAGER ++ help ++ CTR: Counter mode ++ This block cipher algorithm is required for IPSec. ++ ++config CRYPTO_CTS ++ tristate "CTS support" ++ select CRYPTO_BLKCIPHER ++ help ++ CTS: Cipher Text Stealing ++ This is the Cipher Text Stealing mode as described by ++ Section 8 of rfc2040 and referenced by rfc3962. ++ (rfc3962 includes errata information in its Appendix A) ++ This mode is required for Kerberos gss mechanism support ++ for AES encryption. ++ ++config CRYPTO_ECB ++ tristate "ECB support" ++ select CRYPTO_BLKCIPHER ++ select CRYPTO_MANAGER ++ help ++ ECB: Electronic CodeBook mode ++ This is the simplest block cipher algorithm. It simply encrypts ++ the input block by block. ++ ++config CRYPTO_LRW ++ tristate "LRW support (EXPERIMENTAL)" ++ depends on EXPERIMENTAL ++ select CRYPTO_BLKCIPHER ++ select CRYPTO_MANAGER ++ select CRYPTO_GF128MUL ++ help ++ LRW: Liskov Rivest Wagner, a tweakable, non malleable, non movable ++ narrow block cipher mode for dm-crypt. Use it with cipher ++ specification string aes-lrw-benbi, the key must be 256, 320 or 384. ++ The first 128, 192 or 256 bits in the key are used for AES and the ++ rest is used to tie each cipher block to its logical position. ++ ++config CRYPTO_PCBC ++ tristate "PCBC support" ++ select CRYPTO_BLKCIPHER ++ select CRYPTO_MANAGER ++ help ++ PCBC: Propagating Cipher Block Chaining mode ++ This block cipher algorithm is required for RxRPC. ++ ++config CRYPTO_XTS ++ tristate "XTS support (EXPERIMENTAL)" ++ depends on EXPERIMENTAL ++ select CRYPTO_BLKCIPHER ++ select CRYPTO_MANAGER ++ select CRYPTO_GF128MUL ++ help ++ XTS: IEEE1619/D16 narrow block cipher use with aes-xts-plain, ++ key size 256, 384 or 512 bits. This implementation currently ++ can't handle a sectorsize which is not a multiple of 16 bytes. ++ ++comment "Hash modes" ++ ++config CRYPTO_HMAC ++ tristate "HMAC support" ++ select CRYPTO_HASH ++ select CRYPTO_MANAGER ++ help ++ HMAC: Keyed-Hashing for Message Authentication (RFC2104). ++ This is required for IPSec. ++ ++config CRYPTO_XCBC ++ tristate "XCBC support" ++ depends on EXPERIMENTAL ++ select CRYPTO_HASH ++ select CRYPTO_MANAGER ++ help ++ XCBC: Keyed-Hashing with encryption algorithm ++ http://www.ietf.org/rfc/rfc3566.txt ++ http://csrc.nist.gov/encryption/modes/proposedmodes/ ++ xcbc-mac/xcbc-mac-spec.pdf ++ ++config CRYPTO_VMAC ++ tristate "VMAC support" ++ depends on EXPERIMENTAL ++ select CRYPTO_HASH ++ select CRYPTO_MANAGER ++ help ++ VMAC is a message authentication algorithm designed for ++ very high speed on 64-bit architectures. ++ ++ See also: ++ ++ ++comment "Digest" ++ ++config CRYPTO_CRC32C ++ tristate "CRC32c CRC algorithm" ++ select CRYPTO_HASH ++ help ++ Castagnoli, et al Cyclic Redundancy-Check Algorithm. Used ++ by iSCSI for header and data digests and by others. ++ See Castagnoli93. Module will be crc32c. ++ ++config CRYPTO_CRC32C_INTEL ++ tristate "CRC32c INTEL hardware acceleration" ++ depends on X86 ++ select CRYPTO_HASH ++ help ++ In Intel processor with SSE4.2 supported, the processor will ++ support CRC32C implementation using hardware accelerated CRC32 ++ instruction. This option will create 'crc32c-intel' module, ++ which will enable any routine to use the CRC32 instruction to ++ gain performance compared with software implementation. ++ Module will be crc32c-intel. ++ ++config CRYPTO_GHASH ++ tristate "GHASH digest algorithm" ++ select CRYPTO_SHASH ++ select CRYPTO_GF128MUL ++ help ++ GHASH is message digest algorithm for GCM (Galois/Counter Mode). ++ ++config CRYPTO_MD4 ++ tristate "MD4 digest algorithm" ++ select CRYPTO_HASH ++ help ++ MD4 message digest algorithm (RFC1320). ++ ++config CRYPTO_MD5 ++ tristate "MD5 digest algorithm" ++ select CRYPTO_HASH ++ help ++ MD5 message digest algorithm (RFC1321). ++ ++config CRYPTO_MICHAEL_MIC ++ tristate "Michael MIC keyed digest algorithm" ++ select CRYPTO_HASH ++ help ++ Michael MIC is used for message integrity protection in TKIP ++ (IEEE 802.11i). This algorithm is required for TKIP, but it ++ should not be used for other purposes because of the weakness ++ of the algorithm. ++ ++config CRYPTO_RMD128 ++ tristate "RIPEMD-128 digest algorithm" ++ select CRYPTO_HASH ++ help ++ RIPEMD-128 (ISO/IEC 10118-3:2004). ++ ++ RIPEMD-128 is a 128-bit cryptographic hash function. It should only ++ to be used as a secure replacement for RIPEMD. For other use cases ++ RIPEMD-160 should be used. ++ ++ Developed by Hans Dobbertin, Antoon Bosselaers and Bart Preneel. ++ See ++ ++config CRYPTO_RMD160 ++ tristate "RIPEMD-160 digest algorithm" ++ select CRYPTO_HASH ++ help ++ RIPEMD-160 (ISO/IEC 10118-3:2004). ++ ++ RIPEMD-160 is a 160-bit cryptographic hash function. It is intended ++ to be used as a secure replacement for the 128-bit hash functions ++ MD4, MD5 and it's predecessor RIPEMD ++ (not to be confused with RIPEMD-128). ++ ++ It's speed is comparable to SHA1 and there are no known attacks ++ against RIPEMD-160. ++ ++ Developed by Hans Dobbertin, Antoon Bosselaers and Bart Preneel. ++ See ++ ++config CRYPTO_RMD256 ++ tristate "RIPEMD-256 digest algorithm" ++ select CRYPTO_HASH ++ help ++ RIPEMD-256 is an optional extension of RIPEMD-128 with a ++ 256 bit hash. It is intended for applications that require ++ longer hash-results, without needing a larger security level ++ (than RIPEMD-128). ++ ++ Developed by Hans Dobbertin, Antoon Bosselaers and Bart Preneel. ++ See ++ ++config CRYPTO_RMD320 ++ tristate "RIPEMD-320 digest algorithm" ++ select CRYPTO_HASH ++ help ++ RIPEMD-320 is an optional extension of RIPEMD-160 with a ++ 320 bit hash. It is intended for applications that require ++ longer hash-results, without needing a larger security level ++ (than RIPEMD-160). ++ ++ Developed by Hans Dobbertin, Antoon Bosselaers and Bart Preneel. ++ See ++ ++config CRYPTO_SHA1 ++ tristate "SHA1 digest algorithm" ++ select CRYPTO_HASH ++ help ++ SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2). ++ ++config CRYPTO_SHA256 ++ tristate "SHA224 and SHA256 digest algorithm" ++ select CRYPTO_HASH ++ help ++ SHA256 secure hash standard (DFIPS 180-2). ++ ++ This version of SHA implements a 256 bit hash with 128 bits of ++ security against collision attacks. ++ ++ This code also includes SHA-224, a 224 bit hash with 112 bits ++ of security against collision attacks. ++ ++config CRYPTO_SHA512 ++ tristate "SHA384 and SHA512 digest algorithms" ++ select CRYPTO_HASH ++ help ++ SHA512 secure hash standard (DFIPS 180-2). ++ ++ This version of SHA implements a 512 bit hash with 256 bits of ++ security against collision attacks. ++ ++ This code also includes SHA-384, a 384 bit hash with 192 bits ++ of security against collision attacks. ++ ++config CRYPTO_TGR192 ++ tristate "Tiger digest algorithms" ++ select CRYPTO_HASH ++ help ++ Tiger hash algorithm 192, 160 and 128-bit hashes ++ ++ Tiger is a hash function optimized for 64-bit processors while ++ still having decent performance on 32-bit processors. ++ Tiger was developed by Ross Anderson and Eli Biham. ++ ++ See also: ++ . ++ ++config CRYPTO_WP512 ++ tristate "Whirlpool digest algorithms" ++ select CRYPTO_HASH ++ help ++ Whirlpool hash algorithm 512, 384 and 256-bit hashes ++ ++ Whirlpool-512 is part of the NESSIE cryptographic primitives. ++ Whirlpool will be part of the ISO/IEC 10118-3:2003(E) standard ++ ++ See also: ++ ++ ++config CRYPTO_GHASH_CLMUL_NI_INTEL ++ tristate "GHASH digest algorithm (CLMUL-NI accelerated)" ++ depends on (X86 || UML_X86) && 64BIT ++ select CRYPTO_SHASH ++ select CRYPTO_CRYPTD ++ help ++ GHASH is message digest algorithm for GCM (Galois/Counter Mode). ++ The implementation is accelerated by CLMUL-NI of Intel. ++ ++comment "Ciphers" ++ ++config CRYPTO_AES ++ tristate "AES cipher algorithms" ++ select CRYPTO_ALGAPI ++ help ++ AES cipher algorithms (FIPS-197). AES uses the Rijndael ++ algorithm. ++ ++ Rijndael appears to be consistently a very good performer in ++ both hardware and software across a wide range of computing ++ environments regardless of its use in feedback or non-feedback ++ modes. Its key setup time is excellent, and its key agility is ++ good. Rijndael's very low memory requirements make it very well ++ suited for restricted-space environments, in which it also ++ demonstrates excellent performance. Rijndael's operations are ++ among the easiest to defend against power and timing attacks. ++ ++ The AES specifies three key sizes: 128, 192 and 256 bits ++ ++ See for more information. ++ ++config CRYPTO_AES_586 ++ tristate "AES cipher algorithms (i586)" ++ depends on (X86 || UML_X86) && !64BIT ++ select CRYPTO_ALGAPI ++ select CRYPTO_AES ++ help ++ AES cipher algorithms (FIPS-197). AES uses the Rijndael ++ algorithm. ++ ++ Rijndael appears to be consistently a very good performer in ++ both hardware and software across a wide range of computing ++ environments regardless of its use in feedback or non-feedback ++ modes. Its key setup time is excellent, and its key agility is ++ good. Rijndael's very low memory requirements make it very well ++ suited for restricted-space environments, in which it also ++ demonstrates excellent performance. Rijndael's operations are ++ among the easiest to defend against power and timing attacks. ++ ++ The AES specifies three key sizes: 128, 192 and 256 bits ++ ++ See for more information. ++ ++config CRYPTO_AES_X86_64 ++ tristate "AES cipher algorithms (x86_64)" ++ depends on (X86 || UML_X86) && 64BIT ++ select CRYPTO_ALGAPI ++ select CRYPTO_AES ++ help ++ AES cipher algorithms (FIPS-197). AES uses the Rijndael ++ algorithm. ++ ++ Rijndael appears to be consistently a very good performer in ++ both hardware and software across a wide range of computing ++ environments regardless of its use in feedback or non-feedback ++ modes. Its key setup time is excellent, and its key agility is ++ good. Rijndael's very low memory requirements make it very well ++ suited for restricted-space environments, in which it also ++ demonstrates excellent performance. Rijndael's operations are ++ among the easiest to defend against power and timing attacks. ++ ++ The AES specifies three key sizes: 128, 192 and 256 bits ++ ++ See for more information. ++ ++config CRYPTO_AES_NI_INTEL ++ tristate "AES cipher algorithms (AES-NI)" ++ depends on (X86 || UML_X86) ++ select CRYPTO_AES_X86_64 if 64BIT ++ select CRYPTO_AES_586 if !64BIT ++ select CRYPTO_CRYPTD ++ select CRYPTO_ALGAPI ++ help ++ Use Intel AES-NI instructions for AES algorithm. ++ ++ AES cipher algorithms (FIPS-197). AES uses the Rijndael ++ algorithm. ++ ++ Rijndael appears to be consistently a very good performer in ++ both hardware and software across a wide range of computing ++ environments regardless of its use in feedback or non-feedback ++ modes. Its key setup time is excellent, and its key agility is ++ good. Rijndael's very low memory requirements make it very well ++ suited for restricted-space environments, in which it also ++ demonstrates excellent performance. Rijndael's operations are ++ among the easiest to defend against power and timing attacks. ++ ++ The AES specifies three key sizes: 128, 192 and 256 bits ++ ++ See for more information. ++ ++ In addition to AES cipher algorithm support, the acceleration ++ for some popular block cipher mode is supported too, including ++ ECB, CBC, LRW, PCBC, XTS. The 64 bit version has additional ++ acceleration for CTR. ++ ++config CRYPTO_ANUBIS ++ tristate "Anubis cipher algorithm" ++ select CRYPTO_ALGAPI ++ help ++ Anubis cipher algorithm. ++ ++ Anubis is a variable key length cipher which can use keys from ++ 128 bits to 320 bits in length. It was evaluated as a entrant ++ in the NESSIE competition. ++ ++ See also: ++ ++ ++ ++config CRYPTO_ARC4 ++ tristate "ARC4 cipher algorithm" ++ select CRYPTO_ALGAPI ++ help ++ ARC4 cipher algorithm. ++ ++ ARC4 is a stream cipher using keys ranging from 8 bits to 2048 ++ bits in length. This algorithm is required for driver-based ++ WEP, but it should not be for other purposes because of the ++ weakness of the algorithm. ++ ++config CRYPTO_BLOWFISH ++ tristate "Blowfish cipher algorithm" ++ select CRYPTO_ALGAPI ++ help ++ Blowfish cipher algorithm, by Bruce Schneier. ++ ++ This is a variable key length cipher which can use keys from 32 ++ bits to 448 bits in length. It's fast, simple and specifically ++ designed for use on "large microprocessors". ++ ++ See also: ++ ++ ++config CRYPTO_CAMELLIA ++ tristate "Camellia cipher algorithms" ++ depends on CRYPTO ++ select CRYPTO_ALGAPI ++ help ++ Camellia cipher algorithms module. ++ ++ Camellia is a symmetric key block cipher developed jointly ++ at NTT and Mitsubishi Electric Corporation. ++ ++ The Camellia specifies three key sizes: 128, 192 and 256 bits. ++ ++ See also: ++ ++ ++config CRYPTO_CAST5 ++ tristate "CAST5 (CAST-128) cipher algorithm" ++ select CRYPTO_ALGAPI ++ help ++ The CAST5 encryption algorithm (synonymous with CAST-128) is ++ described in RFC2144. ++ ++config CRYPTO_CAST6 ++ tristate "CAST6 (CAST-256) cipher algorithm" ++ select CRYPTO_ALGAPI ++ help ++ The CAST6 encryption algorithm (synonymous with CAST-256) is ++ described in RFC2612. ++ ++config CRYPTO_DES ++ tristate "DES and Triple DES EDE cipher algorithms" ++ select CRYPTO_ALGAPI ++ help ++ DES cipher algorithm (FIPS 46-2), and Triple DES EDE (FIPS 46-3). ++ ++config CRYPTO_FCRYPT ++ tristate "FCrypt cipher algorithm" ++ select CRYPTO_ALGAPI ++ select CRYPTO_BLKCIPHER ++ help ++ FCrypt algorithm used by RxRPC. ++ ++config CRYPTO_KHAZAD ++ tristate "Khazad cipher algorithm" ++ select CRYPTO_ALGAPI ++ help ++ Khazad cipher algorithm. ++ ++ Khazad was a finalist in the initial NESSIE competition. It is ++ an algorithm optimized for 64-bit processors with good performance ++ on 32-bit processors. Khazad uses an 128 bit key size. ++ ++ See also: ++ ++ ++config CRYPTO_SALSA20 ++ tristate "Salsa20 stream cipher algorithm (EXPERIMENTAL)" ++ depends on EXPERIMENTAL ++ select CRYPTO_BLKCIPHER ++ help ++ Salsa20 stream cipher algorithm. ++ ++ Salsa20 is a stream cipher submitted to eSTREAM, the ECRYPT ++ Stream Cipher Project. See ++ ++ The Salsa20 stream cipher algorithm is designed by Daniel J. ++ Bernstein . See ++ ++config CRYPTO_SALSA20_586 ++ tristate "Salsa20 stream cipher algorithm (i586) (EXPERIMENTAL)" ++ depends on (X86 || UML_X86) && !64BIT ++ depends on EXPERIMENTAL ++ select CRYPTO_BLKCIPHER ++ help ++ Salsa20 stream cipher algorithm. ++ ++ Salsa20 is a stream cipher submitted to eSTREAM, the ECRYPT ++ Stream Cipher Project. See ++ ++ The Salsa20 stream cipher algorithm is designed by Daniel J. ++ Bernstein . See ++ ++config CRYPTO_SALSA20_X86_64 ++ tristate "Salsa20 stream cipher algorithm (x86_64) (EXPERIMENTAL)" ++ depends on (X86 || UML_X86) && 64BIT ++ depends on EXPERIMENTAL ++ select CRYPTO_BLKCIPHER ++ help ++ Salsa20 stream cipher algorithm. ++ ++ Salsa20 is a stream cipher submitted to eSTREAM, the ECRYPT ++ Stream Cipher Project. See ++ ++ The Salsa20 stream cipher algorithm is designed by Daniel J. ++ Bernstein . See ++ ++config CRYPTO_SEED ++ tristate "SEED cipher algorithm" ++ select CRYPTO_ALGAPI ++ help ++ SEED cipher algorithm (RFC4269). ++ ++ SEED is a 128-bit symmetric key block cipher that has been ++ developed by KISA (Korea Information Security Agency) as a ++ national standard encryption algorithm of the Republic of Korea. ++ It is a 16 round block cipher with the key size of 128 bit. ++ ++ See also: ++ ++ ++config CRYPTO_SERPENT ++ tristate "Serpent cipher algorithm" ++ select CRYPTO_ALGAPI ++ help ++ Serpent cipher algorithm, by Anderson, Biham & Knudsen. ++ ++ Keys are allowed to be from 0 to 256 bits in length, in steps ++ of 8 bits. Also includes the 'Tnepres' algorithm, a reversed ++ variant of Serpent for compatibility with old kerneli.org code. ++ ++ See also: ++ ++ ++config CRYPTO_TEA ++ tristate "TEA, XTEA and XETA cipher algorithms" ++ select CRYPTO_ALGAPI ++ help ++ TEA cipher algorithm. ++ ++ Tiny Encryption Algorithm is a simple cipher that uses ++ many rounds for security. It is very fast and uses ++ little memory. ++ ++ Xtendend Tiny Encryption Algorithm is a modification to ++ the TEA algorithm to address a potential key weakness ++ in the TEA algorithm. ++ ++ Xtendend Encryption Tiny Algorithm is a mis-implementation ++ of the XTEA algorithm for compatibility purposes. ++ ++config CRYPTO_TWOFISH ++ tristate "Twofish cipher algorithm" ++ select CRYPTO_ALGAPI ++ select CRYPTO_TWOFISH_COMMON ++ help ++ Twofish cipher algorithm. ++ ++ Twofish was submitted as an AES (Advanced Encryption Standard) ++ candidate cipher by researchers at CounterPane Systems. It is a ++ 16 round block cipher supporting key sizes of 128, 192, and 256 ++ bits. ++ ++ See also: ++ ++ ++config CRYPTO_TWOFISH_COMMON ++ tristate ++ help ++ Common parts of the Twofish cipher algorithm shared by the ++ generic c and the assembler implementations. ++ ++config CRYPTO_TWOFISH_586 ++ tristate "Twofish cipher algorithms (i586)" ++ depends on (X86 || UML_X86) && !64BIT ++ select CRYPTO_ALGAPI ++ select CRYPTO_TWOFISH_COMMON ++ help ++ Twofish cipher algorithm. ++ ++ Twofish was submitted as an AES (Advanced Encryption Standard) ++ candidate cipher by researchers at CounterPane Systems. It is a ++ 16 round block cipher supporting key sizes of 128, 192, and 256 ++ bits. ++ ++ See also: ++ ++ ++config CRYPTO_TWOFISH_X86_64 ++ tristate "Twofish cipher algorithm (x86_64)" ++ depends on (X86 || UML_X86) && 64BIT ++ select CRYPTO_ALGAPI ++ select CRYPTO_TWOFISH_COMMON ++ help ++ Twofish cipher algorithm (x86_64). ++ ++ Twofish was submitted as an AES (Advanced Encryption Standard) ++ candidate cipher by researchers at CounterPane Systems. It is a ++ 16 round block cipher supporting key sizes of 128, 192, and 256 ++ bits. ++ ++ See also: ++ ++ ++comment "Compression" ++ ++config CRYPTO_DEFLATE ++ tristate "Deflate compression algorithm" ++ select CRYPTO_ALGAPI ++ select ZLIB_INFLATE ++ select ZLIB_DEFLATE ++ help ++ This is the Deflate algorithm (RFC1951), specified for use in ++ IPSec with the IPCOMP protocol (RFC3173, RFC2394). ++ ++ You will most probably want this if using IPSec. ++ ++config CRYPTO_ZLIB ++ tristate "Zlib compression algorithm" ++ select CRYPTO_PCOMP ++ select ZLIB_INFLATE ++ select ZLIB_DEFLATE ++ select NLATTR ++ help ++ This is the zlib algorithm. ++ ++config CRYPTO_LZO ++ tristate "LZO compression algorithm" ++ select CRYPTO_ALGAPI ++ select LZO_COMPRESS ++ select LZO_DECOMPRESS ++ help ++ This is the LZO algorithm. ++ ++comment "Random Number Generation" ++ ++config CRYPTO_ANSI_CPRNG ++ tristate "Pseudo Random Number Generation for Cryptographic modules" ++ default m ++ select CRYPTO_AES ++ select CRYPTO_RNG ++ help ++ This option enables the generic pseudo random number generator ++ for cryptographic modules. Uses the Algorithm specified in ++ ANSI X9.31 A.2.4. Note that this option must be enabled if ++ CRYPTO_FIPS is selected ++ ++config CRYPTO_USER_API ++ tristate ++ ++config CRYPTO_USER_API_HASH ++ tristate "User-space interface for hash algorithms" ++ depends on NET ++ select CRYPTO_HASH ++ select CRYPTO_USER_API ++ help ++ This option enables the user-spaces interface for hash ++ algorithms. ++ ++config CRYPTO_USER_API_SKCIPHER ++ tristate "User-space interface for symmetric key cipher algorithms" ++ depends on NET ++ select CRYPTO_BLKCIPHER ++ select CRYPTO_USER_API ++ help ++ This option enables the user-spaces interface for symmetric ++ key cipher algorithms. ++ ++source "drivers/crypto/Kconfig" ++ ++endif # if CRYPTO +diff -Nur linux-3.0.4.orig/crypto/Makefile linux-3.0.4/crypto/Makefile +--- linux-3.0.4.orig/crypto/Makefile 2011-08-29 22:56:30.000000000 +0200 ++++ linux-3.0.4/crypto/Makefile 2011-10-17 04:36:27.356574299 +0200 +@@ -89,6 +89,8 @@ + obj-$(CONFIG_CRYPTO_USER_API_HASH) += algif_hash.o + obj-$(CONFIG_CRYPTO_USER_API_SKCIPHER) += algif_skcipher.o + ++obj-$(CONFIG_OCF_OCF) += ocf/ ++ + # + # generic algorithms and the async_tx api + # +diff -Nur linux-3.0.4.orig/crypto/ocf/Config.in linux-3.0.4/crypto/ocf/Config.in +--- linux-3.0.4.orig/crypto/ocf/Config.in 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/Config.in 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,38 @@ ++############################################################################# ++ ++mainmenu_option next_comment ++comment 'OCF Configuration' ++tristate 'OCF (Open Cryptograhic Framework)' CONFIG_OCF_OCF ++dep_mbool ' enable fips RNG checks (fips check on RNG data before use)' \ ++ CONFIG_OCF_FIPS $CONFIG_OCF_OCF ++dep_mbool ' enable harvesting entropy for /dev/random' \ ++ CONFIG_OCF_RANDOMHARVEST $CONFIG_OCF_OCF ++dep_tristate ' cryptodev (user space support)' \ ++ CONFIG_OCF_CRYPTODEV $CONFIG_OCF_OCF ++dep_tristate ' cryptosoft (software crypto engine)' \ ++ CONFIG_OCF_CRYPTOSOFT $CONFIG_OCF_OCF ++dep_tristate ' safenet (HW crypto engine)' \ ++ CONFIG_OCF_SAFE $CONFIG_OCF_OCF ++dep_tristate ' IXP4xx (HW crypto engine)' \ ++ CONFIG_OCF_IXP4XX $CONFIG_OCF_OCF ++dep_mbool ' Enable IXP4xx HW to perform SHA1 and MD5 hashing (very slow)' \ ++ CONFIG_OCF_IXP4XX_SHA1_MD5 $CONFIG_OCF_IXP4XX ++dep_tristate ' hifn (HW crypto engine)' \ ++ CONFIG_OCF_HIFN $CONFIG_OCF_OCF ++dep_tristate ' talitos (HW crypto engine)' \ ++ CONFIG_OCF_TALITOS $CONFIG_OCF_OCF ++dep_tristate ' pasemi (HW crypto engine)' \ ++ CONFIG_OCF_PASEMI $CONFIG_OCF_OCF ++dep_tristate ' ep80579 (HW crypto engine)' \ ++ CONFIG_OCF_EP80579 $CONFIG_OCF_OCF ++dep_tristate ' Micronas c7108 (HW crypto engine)' \ ++ CONFIG_OCF_C7108 $CONFIG_OCF_OCF ++dep_tristate ' uBsec BCM5365 (HW crypto engine)' ++ CONFIG_OCF_UBSEC_SSB $CONFIG_OCF_OCF ++dep_tristate ' ocfnull (does no crypto)' \ ++ CONFIG_OCF_OCFNULL $CONFIG_OCF_OCF ++dep_tristate ' ocf-bench (HW crypto in-kernel benchmark)' \ ++ CONFIG_OCF_BENCH $CONFIG_OCF_OCF ++endmenu ++ ++############################################################################# +diff -Nur linux-3.0.4.orig/crypto/ocf/Kconfig linux-3.0.4/crypto/ocf/Kconfig +--- linux-3.0.4.orig/crypto/ocf/Kconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/Kconfig 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,125 @@ ++menu "OCF Configuration" ++ ++config OCF_OCF ++ tristate "OCF (Open Cryptograhic Framework)" ++ help ++ A linux port of the OpenBSD/FreeBSD crypto framework. ++ ++config OCF_RANDOMHARVEST ++ bool "crypto random --- harvest entropy for /dev/random" ++ depends on OCF_OCF ++ help ++ Includes code to harvest random numbers from devices that support it. ++ ++config OCF_FIPS ++ bool "enable fips RNG checks" ++ depends on OCF_OCF && OCF_RANDOMHARVEST ++ help ++ Run all RNG provided data through a fips check before ++ adding it /dev/random's entropy pool. ++ ++config OCF_CRYPTODEV ++ tristate "cryptodev (user space support)" ++ depends on OCF_OCF ++ help ++ The user space API to access crypto hardware. ++ ++config OCF_CRYPTOSOFT ++ tristate "cryptosoft (software crypto engine)" ++ depends on OCF_OCF ++ help ++ A software driver for the OCF framework that uses ++ the kernel CryptoAPI. ++ ++config OCF_SAFE ++ tristate "safenet (HW crypto engine)" ++ depends on OCF_OCF ++ help ++ A driver for a number of the safenet Excel crypto accelerators. ++ Currently tested and working on the 1141 and 1741. ++ ++config OCF_IXP4XX ++ tristate "IXP4xx (HW crypto engine)" ++ depends on OCF_OCF ++ help ++ XScale IXP4xx crypto accelerator driver. Requires the ++ Intel Access library. ++ ++config OCF_IXP4XX_SHA1_MD5 ++ bool "IXP4xx SHA1 and MD5 Hashing" ++ depends on OCF_IXP4XX ++ help ++ Allows the IXP4xx crypto accelerator to perform SHA1 and MD5 hashing. ++ Note: this is MUCH slower than using cryptosoft (software crypto engine). ++ ++config OCF_HIFN ++ tristate "hifn (HW crypto engine)" ++ depends on OCF_OCF ++ help ++ OCF driver for various HIFN based crypto accelerators. ++ (7951, 7955, 7956, 7751, 7811) ++ ++config OCF_HIFNHIPP ++ tristate "Hifn HIPP (HW packet crypto engine)" ++ depends on OCF_OCF ++ help ++ OCF driver for various HIFN (HIPP) based crypto accelerators ++ (7855) ++ ++config OCF_TALITOS ++ tristate "talitos (HW crypto engine)" ++ depends on OCF_OCF ++ help ++ OCF driver for Freescale's security engine (SEC/talitos). ++ ++config OCF_PASEMI ++ tristate "pasemi (HW crypto engine)" ++ depends on OCF_OCF && PPC_PASEMI ++ help ++ OCF driver for the PA Semi PWRficient DMA Engine ++ ++config OCF_EP80579 ++ tristate "ep80579 (HW crypto engine)" ++ depends on OCF_OCF ++ help ++ OCF driver for the Intel EP80579 Integrated Processor Product Line. ++ ++config OCF_CRYPTOCTEON ++ tristate "cryptocteon (HW crypto engine)" ++ depends on OCF_OCF ++ help ++ OCF driver for the Cavium OCTEON Processors. ++ ++config OCF_KIRKWOOD ++ tristate "kirkwood (HW crypto engine)" ++ depends on OCF_OCF ++ help ++ OCF driver for the Marvell Kirkwood (88F6xxx) Processors. ++ ++config OCF_C7108 ++ tristate "Micronas 7108 (HW crypto engine)" ++ depends on OCF_OCF ++ help ++ OCF driver for the Microna 7108 Cipher processors. ++ ++config OCF_UBSEC_SSB ++ tristate "uBsec BCM5365 (HW crypto engine)" ++ depends on OCF_OCF ++ help ++ OCF driver for uBsec BCM5365 hardware crypto accelerator. ++ ++config OCF_OCFNULL ++ tristate "ocfnull (fake crypto engine)" ++ depends on OCF_OCF ++ help ++ OCF driver for measuring ipsec overheads (does no crypto) ++ ++config OCF_BENCH ++ tristate "ocf-bench (HW crypto in-kernel benchmark)" ++ depends on OCF_OCF ++ help ++ A very simple encryption test for the in-kernel interface ++ of OCF. Also includes code to benchmark the IXP Access library ++ for comparison. ++ ++endmenu +diff -Nur linux-3.0.4.orig/crypto/ocf/Makefile linux-3.0.4/crypto/ocf/Makefile +--- linux-3.0.4.orig/crypto/ocf/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/Makefile 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,145 @@ ++# for SGlinux builds ++-include $(ROOTDIR)/modules/.config ++ ++OCF_OBJS = crypto.o criov.o ++ ++ifdef CONFIG_OCF_RANDOMHARVEST ++ OCF_OBJS += random.o ++endif ++ ++ifdef CONFIG_OCF_FIPS ++ OCF_OBJS += rndtest.o ++endif ++ ++# Add in autoconf.h to get #defines for CONFIG_xxx ++AUTOCONF_H=$(ROOTDIR)/modules/autoconf.h ++ifeq ($(AUTOCONF_H), $(wildcard $(AUTOCONF_H))) ++ EXTRA_CFLAGS += -include $(AUTOCONF_H) ++ export EXTRA_CFLAGS ++endif ++ ++ifndef obj ++ obj ?= . ++ _obj = subdir ++ mod-subdirs := safe hifn ixp4xx talitos ocfnull ++ export-objs += crypto.o criov.o random.o ++ list-multi += ocf.o ++ _slash := ++else ++ _obj = obj ++ _slash := / ++endif ++ ++EXTRA_CFLAGS += -I$(obj)/. ++ ++obj-$(CONFIG_OCF_OCF) += ocf.o ++obj-$(CONFIG_OCF_CRYPTODEV) += cryptodev.o ++obj-$(CONFIG_OCF_CRYPTOSOFT) += cryptosoft.o ++obj-$(CONFIG_OCF_BENCH) += ocf-bench.o ++ ++$(_obj)-$(CONFIG_OCF_SAFE) += safe$(_slash) ++$(_obj)-$(CONFIG_OCF_HIFN) += hifn$(_slash) ++$(_obj)-$(CONFIG_OCF_IXP4XX) += ixp4xx$(_slash) ++$(_obj)-$(CONFIG_OCF_TALITOS) += talitos$(_slash) ++$(_obj)-$(CONFIG_OCF_PASEMI) += pasemi$(_slash) ++$(_obj)-$(CONFIG_OCF_EP80579) += ep80579$(_slash) ++$(_obj)-$(CONFIG_OCF_CRYPTOCTEON) += cryptocteon$(_slash) ++$(_obj)-$(CONFIG_OCF_KIRKWOOD) += kirkwood$(_slash) ++$(_obj)-$(CONFIG_OCF_OCFNULL) += ocfnull$(_slash) ++$(_obj)-$(CONFIG_OCF_C7108) += c7108$(_slash) ++$(_obj)-$(CONFIG_OCF_UBSEC_SSB) += ubsec_ssb$(_slash) ++ ++ocf-objs := $(OCF_OBJS) ++ ++dummy: ++ @echo "Please consult the README for how to build OCF." ++ @echo "If you can't wait then the following should do it:" ++ @echo "" ++ @echo " make ocf_modules" ++ @echo " sudo make ocf_install" ++ @echo "" ++ @exit 1 ++ ++$(list-multi) dummy1: $(ocf-objs) ++ $(LD) -r -o $@ $(ocf-objs) ++ ++.PHONY: ++clean: ++ rm -f *.o *.ko .*.o.flags .*.ko.cmd .*.o.cmd .*.mod.o.cmd *.mod.c ++ rm -f */*.o */*.ko */.*.o.cmd */.*.ko.cmd */.*.mod.o.cmd */*.mod.c */.*.o.flags ++ rm -f */modules.order */modules.builtin modules.order modules.builtin ++ ++ifdef TOPDIR ++-include $(TOPDIR)/Rules.make ++endif ++ ++# ++# targets to build easily on the current machine ++# ++ ++ocf_make: ++ make -C /lib/modules/$(shell uname -r)/build M=`pwd` $(OCF_TARGET) CONFIG_OCF_OCF=m ++ make -C /lib/modules/$(shell uname -r)/build M=`pwd` $(OCF_TARGET) CONFIG_OCF_OCF=m CONFIG_OCF_CRYPTOSOFT=m ++ -make -C /lib/modules/$(shell uname -r)/build M=`pwd` $(OCF_TARGET) CONFIG_OCF_OCF=m CONFIG_OCF_BENCH=m ++ -make -C /lib/modules/$(shell uname -r)/build M=`pwd` $(OCF_TARGET) CONFIG_OCF_OCF=m CONFIG_OCF_OCFNULL=m ++ -make -C /lib/modules/$(shell uname -r)/build M=`pwd` $(OCF_TARGET) CONFIG_OCF_OCF=m CONFIG_OCF_HIFN=m ++ ++ocf_modules: ++ $(MAKE) ocf_make OCF_TARGET=modules ++ ++ocf_install: ++ $(MAKE) ocf_make OCF_TARGET="modules modules_install" ++ depmod ++ mkdir -p /usr/include/crypto ++ cp cryptodev.h /usr/include/crypto/. ++ ++# ++# generate full kernel patches for 2.4 and 2.6 kernels to make patching ++# your kernel easier ++# ++ ++.PHONY: patch ++patch: ++ patchbase=.; \ ++ [ -d $$patchbase/patches ] || patchbase=..; \ ++ patch=ocf-linux-base.patch; \ ++ patch24=ocf-linux-24.patch; \ ++ patch26=ocf-linux-26.patch; \ ++ ( \ ++ find . -name Makefile; \ ++ find . -name Config.in; \ ++ find . -name Kconfig; \ ++ find . -name README; \ ++ find . -name '*.[ch]' | grep -v '.mod.c'; \ ++ ) | while read t; do \ ++ diff -Nau /dev/null $$t | sed 's?^+++ \./?+++ linux/crypto/ocf/?'; \ ++ done > $$patch; \ ++ cat $$patchbase/patches/linux-2.4.35-ocf.patch $$patch > $$patch24; \ ++ cat $$patchbase/patches/linux-2.6.38-ocf.patch $$patch > $$patch26; \ ++ ++# ++# this target probably does nothing for anyone but me - davidm ++# ++ ++.PHONY: release ++release: ++ REL=`date +%Y%m%d`; RELDIR=/tmp/ocf-linux-$$REL; \ ++ CURDIR=`pwd`; \ ++ rm -rf /tmp/ocf-linux-$$REL*; \ ++ mkdir -p $$RELDIR/ocf; \ ++ mkdir -p $$RELDIR/patches; \ ++ mkdir -p $$RELDIR/crypto-tools; \ ++ cp README* $$RELDIR/.; \ ++ cp patches/[!C]* $$RELDIR/patches/.; \ ++ cp tools/[!C]* $$RELDIR/crypto-tools/.; \ ++ cp -r [!C]* Config.in $$RELDIR/ocf/.; \ ++ rm -rf $$RELDIR/ocf/patches $$RELDIR/ocf/tools; \ ++ rm -f $$RELDIR/ocf/README*; \ ++ cp $$CURDIR/../../user/crypto-tools/[!C]* $$RELDIR/crypto-tools/.; \ ++ make -C $$RELDIR/crypto-tools clean; \ ++ make -C $$RELDIR/ocf clean; \ ++ find $$RELDIR/ocf -name CVS | xargs rm -rf; \ ++ cd $$RELDIR/..; \ ++ tar cvf ocf-linux-$$REL.tar ocf-linux-$$REL; \ ++ gzip -9 ocf-linux-$$REL.tar ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/c7108/Makefile linux-3.0.4/crypto/ocf/c7108/Makefile +--- linux-3.0.4.orig/crypto/ocf/c7108/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/c7108/Makefile 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,12 @@ ++# for SGlinux builds ++-include $(ROOTDIR)/modules/.config ++ ++obj-$(CONFIG_OCF_C7108) += aes-7108.o ++ ++obj ?= . ++EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ ++ ++ifdef TOPDIR ++-include $(TOPDIR)/Rules.make ++endif ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/c7108/aes-7108.c linux-3.0.4/crypto/ocf/c7108/aes-7108.c +--- linux-3.0.4.orig/crypto/ocf/c7108/aes-7108.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/c7108/aes-7108.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,839 @@ ++/* ++ * Copyright (C) 2006 Micronas USA ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored in part by the Defense Advanced Research Projects ++ * Agency (DARPA) and Air Force Research Laboratory, Air Force ++ * Materiel Command, USAF, under agreement number F30602-01-2-0537. ++ * ++ */ ++ ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* Runtime mode */ ++static int c7108_crypto_mode = C7108_AES_CTRL_MODE_CTR; ++//static int c7108_crypto_mode = C7108_AES_CTRL_MODE_CBC; ++ ++static int32_t c7108_id = -1; ++static struct cipher_7108 **c7108_sessions = NULL; ++static u_int32_t c7108_sesnum = 0; ++static unsigned long iobar; ++ ++/* Crypto entry points */ ++static int c7108_process(void *, struct cryptop *, int); ++static int c7108_newsession(void *, u_int32_t *, struct cryptoini *); ++static int c7108_freesession(void *, u_int64_t); ++ ++/* Globals */ ++static int debug = 0; ++static spinlock_t csr_mutex; ++ ++/* Generic controller-based lock */ ++#define AES_LOCK()\ ++ spin_lock(&csr_mutex) ++#define AES_UNLOCK()\ ++ spin_unlock(&csr_mutex) ++ ++/* 7108 AES register access */ ++#define c7108_reg_wr8(a,d) iowrite8(d, (void*)(iobar+(a))) ++#define c7108_reg_wr16(a,d) iowrite16(d, (void*)(iobar+(a))) ++#define c7108_reg_wr32(a,d) iowrite32(d, (void*)(iobar+(a))) ++#define c7108_reg_rd8(a) ioread8((void*)(iobar+(a))) ++#define c7108_reg_rd16(a) ioread16((void*)(iobar+(a))) ++#define c7108_reg_rd32(a) ioread32((void*)(iobar+(a))) ++ ++static int ++c7108_xlate_key(int klen, u8* k8ptr, u32* k32ptr) ++{ ++ int i, nw=0; ++ nw = ((klen >= 256) ? 8 : (klen >= 192) ? 6 : 4); ++ for ( i = 0; i < nw; i++) { ++ k32ptr[i] = (k8ptr[i+3] << 24) | (k8ptr[i+2] << 16) | ++ (k8ptr[i+1] << 8) | k8ptr[i]; ++ ++ } ++ return 0; ++} ++ ++static int ++c7108_cache_key(int klen, u32* k32ptr, u8* k8ptr) ++{ ++ int i, nb=0; ++ u8* ptr = (u8*)k32ptr; ++ nb = ((klen >= 256) ? 32 : (klen >= 192) ? 24 : 16); ++ for ( i = 0; i < nb; i++) ++ k8ptr[i] = ptr[i]; ++ return 0; ++} ++ ++static int ++c7108_aes_setup_dma(u32 src, u32 dst, u32 len) ++{ ++ if (len < 16) { ++ printk("len < 16\n"); ++ return -10; ++ } ++ if (len % 16) { ++ printk("len not multiple of 16\n"); ++ return -11; ++ } ++ c7108_reg_wr16(C7108_AES_DMA_SRC0_LO, (u16) src); ++ c7108_reg_wr16(C7108_AES_DMA_SRC0_HI, (u16)((src & 0xffff0000) >> 16)); ++ c7108_reg_wr16(C7108_AES_DMA_DST0_LO, (u16) dst); ++ c7108_reg_wr16(C7108_AES_DMA_DST0_HI, (u16)((dst & 0xffff0000) >> 16)); ++ c7108_reg_wr16(C7108_AES_DMA_LEN, (u16) ((len / 16) - 1)); ++ ++ return 0; ++} ++ ++static int ++c7108_aes_set_hw_iv(u8 iv[16]) ++{ ++ c7108_reg_wr16(C7108_AES_IV0_LO, (u16) ((iv[1] << 8) | iv[0])); ++ c7108_reg_wr16(C7108_AES_IV0_HI, (u16) ((iv[3] << 8) | iv[2])); ++ c7108_reg_wr16(C7108_AES_IV1_LO, (u16) ((iv[5] << 8) | iv[4])); ++ c7108_reg_wr16(C7108_AES_IV1_HI, (u16) ((iv[7] << 8) | iv[6])); ++ c7108_reg_wr16(C7108_AES_IV2_LO, (u16) ((iv[9] << 8) | iv[8])); ++ c7108_reg_wr16(C7108_AES_IV2_HI, (u16) ((iv[11] << 8) | iv[10])); ++ c7108_reg_wr16(C7108_AES_IV3_LO, (u16) ((iv[13] << 8) | iv[12])); ++ c7108_reg_wr16(C7108_AES_IV3_HI, (u16) ((iv[15] << 8) | iv[14])); ++ ++ return 0; ++} ++ ++static void ++c7108_aes_read_dkey(u32 * dkey) ++{ ++ dkey[0] = (c7108_reg_rd16(C7108_AES_EKEY0_HI) << 16) | ++ c7108_reg_rd16(C7108_AES_EKEY0_LO); ++ dkey[1] = (c7108_reg_rd16(C7108_AES_EKEY1_HI) << 16) | ++ c7108_reg_rd16(C7108_AES_EKEY1_LO); ++ dkey[2] = (c7108_reg_rd16(C7108_AES_EKEY2_HI) << 16) | ++ c7108_reg_rd16(C7108_AES_EKEY2_LO); ++ dkey[3] = (c7108_reg_rd16(C7108_AES_EKEY3_HI) << 16) | ++ c7108_reg_rd16(C7108_AES_EKEY3_LO); ++ dkey[4] = (c7108_reg_rd16(C7108_AES_EKEY4_HI) << 16) | ++ c7108_reg_rd16(C7108_AES_EKEY4_LO); ++ dkey[5] = (c7108_reg_rd16(C7108_AES_EKEY5_HI) << 16) | ++ c7108_reg_rd16(C7108_AES_EKEY5_LO); ++ dkey[6] = (c7108_reg_rd16(C7108_AES_EKEY6_HI) << 16) | ++ c7108_reg_rd16(C7108_AES_EKEY6_LO); ++ dkey[7] = (c7108_reg_rd16(C7108_AES_EKEY7_HI) << 16) | ++ c7108_reg_rd16(C7108_AES_EKEY7_LO); ++} ++ ++static int ++c7108_aes_cipher(int op, ++ u32 dst, ++ u32 src, ++ u32 len, ++ int klen, ++ u16 mode, ++ u32 key[8], ++ u8 iv[16]) ++{ ++ int rv = 0, cnt=0; ++ u16 ctrl = 0, stat = 0; ++ ++ AES_LOCK(); ++ ++ /* Setup key length */ ++ if (klen == 128) { ++ ctrl |= C7108_AES_KEY_LEN_128; ++ } else if (klen == 192) { ++ ctrl |= C7108_AES_KEY_LEN_192; ++ } else if (klen == 256) { ++ ctrl |= C7108_AES_KEY_LEN_256; ++ } else { ++ AES_UNLOCK(); ++ return -3; ++ } ++ ++ /* Check opcode */ ++ if (C7108_AES_ENCRYPT == op) { ++ ctrl |= C7108_AES_ENCRYPT; ++ } else if (C7108_AES_DECRYPT == op) { ++ ctrl |= C7108_AES_DECRYPT; ++ } else { ++ AES_UNLOCK(); ++ return -4; ++ } ++ ++ /* check mode */ ++ if ( (mode != C7108_AES_CTRL_MODE_CBC) && ++ (mode != C7108_AES_CTRL_MODE_CFB) && ++ (mode != C7108_AES_CTRL_MODE_OFB) && ++ (mode != C7108_AES_CTRL_MODE_CTR) && ++ (mode != C7108_AES_CTRL_MODE_ECB) ) { ++ AES_UNLOCK(); ++ return -5; ++ } ++ ++ /* Now set mode */ ++ ctrl |= mode; ++ ++ /* For CFB, OFB, and CTR, neither backward key ++ * expansion nor key inversion is required. ++ */ ++ if ( (C7108_AES_DECRYPT == op) && ++ (C7108_AES_CTRL_MODE_CBC == mode || ++ C7108_AES_CTRL_MODE_ECB == mode ) ){ ++ ++ /* Program Key */ ++ c7108_reg_wr16(C7108_AES_KEY0_LO, (u16) key[4]); ++ c7108_reg_wr16(C7108_AES_KEY0_HI, (u16) (key[4] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY1_LO, (u16) key[5]); ++ c7108_reg_wr16(C7108_AES_KEY1_HI, (u16) (key[5] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY2_LO, (u16) key[6]); ++ c7108_reg_wr16(C7108_AES_KEY2_HI, (u16) (key[6] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY3_LO, (u16) key[7]); ++ c7108_reg_wr16(C7108_AES_KEY3_HI, (u16) (key[7] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY6_LO, (u16) key[2]); ++ c7108_reg_wr16(C7108_AES_KEY6_HI, (u16) (key[2] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY7_LO, (u16) key[3]); ++ c7108_reg_wr16(C7108_AES_KEY7_HI, (u16) (key[3] >> 16)); ++ ++ ++ if (192 == klen) { ++ c7108_reg_wr16(C7108_AES_KEY4_LO, (u16) key[7]); ++ c7108_reg_wr16(C7108_AES_KEY4_HI, (u16) (key[7] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY5_LO, (u16) key[7]); ++ c7108_reg_wr16(C7108_AES_KEY5_HI, (u16) (key[7] >> 16)); ++ ++ } else if (256 == klen) { ++ /* 256 */ ++ c7108_reg_wr16(C7108_AES_KEY4_LO, (u16) key[0]); ++ c7108_reg_wr16(C7108_AES_KEY4_HI, (u16) (key[0] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY5_LO, (u16) key[1]); ++ c7108_reg_wr16(C7108_AES_KEY5_HI, (u16) (key[1] >> 16)); ++ ++ } ++ ++ } else { ++ /* Program Key */ ++ c7108_reg_wr16(C7108_AES_KEY0_LO, (u16) key[0]); ++ c7108_reg_wr16(C7108_AES_KEY0_HI, (u16) (key[0] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY1_LO, (u16) key[1]); ++ c7108_reg_wr16(C7108_AES_KEY1_HI, (u16) (key[1] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY2_LO, (u16) key[2]); ++ c7108_reg_wr16(C7108_AES_KEY2_HI, (u16) (key[2] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY3_LO, (u16) key[3]); ++ c7108_reg_wr16(C7108_AES_KEY3_HI, (u16) (key[3] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY4_LO, (u16) key[4]); ++ c7108_reg_wr16(C7108_AES_KEY4_HI, (u16) (key[4] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY5_LO, (u16) key[5]); ++ c7108_reg_wr16(C7108_AES_KEY5_HI, (u16) (key[5] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY6_LO, (u16) key[6]); ++ c7108_reg_wr16(C7108_AES_KEY6_HI, (u16) (key[6] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY7_LO, (u16) key[7]); ++ c7108_reg_wr16(C7108_AES_KEY7_HI, (u16) (key[7] >> 16)); ++ ++ } ++ ++ /* Set IV always */ ++ c7108_aes_set_hw_iv(iv); ++ ++ /* Program DMA addresses */ ++ if ((rv = c7108_aes_setup_dma(src, dst, len)) < 0) { ++ AES_UNLOCK(); ++ return rv; ++ } ++ ++ ++ /* Start AES cipher */ ++ c7108_reg_wr16(C7108_AES_CTRL, ctrl | C7108_AES_GO); ++ ++ //printk("Ctrl: 0x%x\n", ctrl | C7108_AES_GO); ++ do { ++ /* TODO: interrupt mode */ ++ // printk("aes_stat=0x%x\n", stat); ++ //udelay(100); ++ } while ((cnt++ < 1000000) && ++ !((stat=c7108_reg_rd16(C7108_AES_CTRL))&C7108_AES_OP_DONE)); ++ ++ ++ if ((mode == C7108_AES_CTRL_MODE_ECB)|| ++ (mode == C7108_AES_CTRL_MODE_CBC)) { ++ /* Save out key when the lock is held ... */ ++ c7108_aes_read_dkey(key); ++ } ++ ++ AES_UNLOCK(); ++ return 0; ++ ++} ++ ++/* ++ * Generate a new crypto device session. ++ */ ++static int ++c7108_newsession(void *arg, u_int32_t *sid, struct cryptoini *cri) ++{ ++ struct cipher_7108 **swd; ++ u_int32_t i; ++ char *algo; ++ int mode, xfm_type; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (sid == NULL || cri == NULL) { ++ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ if (c7108_sessions) { ++ for (i = 1; i < c7108_sesnum; i++) ++ if (c7108_sessions[i] == NULL) ++ break; ++ } else ++ i = 1; /* NB: to silence compiler warning */ ++ ++ if (c7108_sessions == NULL || i == c7108_sesnum) { ++ if (c7108_sessions == NULL) { ++ i = 1; /* We leave c7108_sessions[0] empty */ ++ c7108_sesnum = CRYPTO_SW_SESSIONS; ++ } else ++ c7108_sesnum *= 2; ++ ++ swd = kmalloc(c7108_sesnum * sizeof(struct cipher_7108 *), ++ GFP_ATOMIC); ++ if (swd == NULL) { ++ /* Reset session number */ ++ if (c7108_sesnum == CRYPTO_SW_SESSIONS) ++ c7108_sesnum = 0; ++ else ++ c7108_sesnum /= 2; ++ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ memset(swd, 0, c7108_sesnum * sizeof(struct cipher_7108 *)); ++ ++ /* Copy existing sessions */ ++ if (c7108_sessions) { ++ memcpy(swd, c7108_sessions, ++ (c7108_sesnum / 2) * sizeof(struct cipher_7108 *)); ++ kfree(c7108_sessions); ++ } ++ ++ c7108_sessions = swd; ++ ++ } ++ ++ swd = &c7108_sessions[i]; ++ *sid = i; ++ ++ while (cri) { ++ *swd = (struct cipher_7108 *) ++ kmalloc(sizeof(struct cipher_7108), GFP_ATOMIC); ++ if (*swd == NULL) { ++ c7108_freesession(NULL, i); ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ memset(*swd, 0, sizeof(struct cipher_7108)); ++ ++ algo = NULL; ++ mode = 0; ++ xfm_type = HW_TYPE_CIPHER; ++ ++ switch (cri->cri_alg) { ++ ++ case CRYPTO_AES_CBC: ++ algo = "aes"; ++ mode = CRYPTO_TFM_MODE_CBC; ++ c7108_crypto_mode = C7108_AES_CTRL_MODE_CBC; ++ break; ++#if 0 ++ case CRYPTO_AES_CTR: ++ algo = "aes_ctr"; ++ mode = CRYPTO_TFM_MODE_CBC; ++ c7108_crypto_mode = C7108_AES_CTRL_MODE_CTR; ++ break; ++ case CRYPTO_AES_ECB: ++ algo = "aes_ecb"; ++ mode = CRYPTO_TFM_MODE_CBC; ++ c7108_crypto_mode = C7108_AES_CTRL_MODE_ECB; ++ break; ++ case CRYPTO_AES_OFB: ++ algo = "aes_ofb"; ++ mode = CRYPTO_TFM_MODE_CBC; ++ c7108_crypto_mode = C7108_AES_CTRL_MODE_OFB; ++ break; ++ case CRYPTO_AES_CFB: ++ algo = "aes_cfb"; ++ mode = CRYPTO_TFM_MODE_CBC; ++ c7108_crypto_mode = C7108_AES_CTRL_MODE_CFB; ++ break; ++#endif ++ default: ++ printk("unsupported crypto algorithm: %d\n", ++ cri->cri_alg); ++ return -EINVAL; ++ break; ++ } ++ ++ ++ if (!algo || !*algo) { ++ printk("cypher_7108_crypto: Unknown algo 0x%x\n", ++ cri->cri_alg); ++ c7108_freesession(NULL, i); ++ return EINVAL; ++ } ++ ++ if (xfm_type == HW_TYPE_CIPHER) { ++ if (debug) { ++ dprintk("%s key:", __FUNCTION__); ++ for (i = 0; i < (cri->cri_klen + 7) / 8; i++) ++ dprintk("%s0x%02x", (i % 8) ? " " : "\n ", ++ cri->cri_key[i]); ++ dprintk("\n"); ++ } ++ ++ } else if (xfm_type == SW_TYPE_HMAC || ++ xfm_type == SW_TYPE_HASH) { ++ printk("cypher_7108_crypto: HMAC unsupported!\n"); ++ return -EINVAL; ++ c7108_freesession(NULL, i); ++ } else { ++ printk("cypher_7108_crypto: " ++ "Unhandled xfm_type %d\n", xfm_type); ++ c7108_freesession(NULL, i); ++ return EINVAL; ++ } ++ ++ (*swd)->cri_alg = cri->cri_alg; ++ (*swd)->xfm_type = xfm_type; ++ ++ cri = cri->cri_next; ++ swd = &((*swd)->next); ++ } ++ return 0; ++} ++ ++/* ++ * Free a session. ++ */ ++static int ++c7108_freesession(void *arg, u_int64_t tid) ++{ ++ struct cipher_7108 *swd; ++ u_int32_t sid = CRYPTO_SESID2LID(tid); ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (sid > c7108_sesnum || c7108_sessions == NULL || ++ c7108_sessions[sid] == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return(EINVAL); ++ } ++ ++ /* Silently accept and return */ ++ if (sid == 0) ++ return(0); ++ ++ while ((swd = c7108_sessions[sid]) != NULL) { ++ c7108_sessions[sid] = swd->next; ++ kfree(swd); ++ } ++ return 0; ++} ++ ++/* ++ * Process a hardware request. ++ */ ++static int ++c7108_process(void *arg, struct cryptop *crp, int hint) ++{ ++ struct cryptodesc *crd; ++ struct cipher_7108 *sw; ++ u_int32_t lid; ++ int type; ++ u32 hwkey[8]; ++ ++#define SCATTERLIST_MAX 16 ++ struct scatterlist sg[SCATTERLIST_MAX]; ++ int sg_num, sg_len, skip; ++ struct sk_buff *skb = NULL; ++ struct uio *uiop = NULL; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ /* Sanity check */ ++ if (crp == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ crp->crp_etype = 0; ++ ++ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ crp->crp_etype = EINVAL; ++ goto done; ++ } ++ ++ lid = crp->crp_sid & 0xffffffff; ++ if (lid >= c7108_sesnum || lid == 0 || c7108_sessions == NULL || ++ c7108_sessions[lid] == NULL) { ++ crp->crp_etype = ENOENT; ++ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); ++ goto done; ++ } ++ ++ /* ++ * do some error checking outside of the loop for SKB and IOV ++ * processing this leaves us with valid skb or uiop pointers ++ * for later ++ */ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ skb = (struct sk_buff *) crp->crp_buf; ++ if (skb_shinfo(skb)->nr_frags >= SCATTERLIST_MAX) { ++ printk("%s,%d: %d nr_frags > SCATTERLIST_MAX", ++ __FILE__, __LINE__, ++ skb_shinfo(skb)->nr_frags); ++ goto done; ++ } ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ uiop = (struct uio *) crp->crp_buf; ++ if (uiop->uio_iovcnt > SCATTERLIST_MAX) { ++ printk("%s,%d: %d uio_iovcnt > SCATTERLIST_MAX", ++ __FILE__, __LINE__, ++ uiop->uio_iovcnt); ++ goto done; ++ } ++ } ++ ++ /* Go through crypto descriptors, processing as we go */ ++ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { ++ /* ++ * Find the crypto context. ++ * ++ * XXX Note that the logic here prevents us from having ++ * XXX the same algorithm multiple times in a session ++ * XXX (or rather, we can but it won't give us the right ++ * XXX results). To do that, we'd need some way of differentiating ++ * XXX between the various instances of an algorithm (so we can ++ * XXX locate the correct crypto context). ++ */ ++ for (sw = c7108_sessions[lid]; ++ sw && sw->cri_alg != crd->crd_alg; ++ sw = sw->next) ++ ; ++ ++ /* No such context ? */ ++ if (sw == NULL) { ++ crp->crp_etype = EINVAL; ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ goto done; ++ } ++ ++ skip = crd->crd_skip; ++ ++ /* ++ * setup the SG list skip from the start of the buffer ++ */ ++ memset(sg, 0, sizeof(sg)); ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ int i, len; ++ type = CRYPTO_BUF_SKBUF; ++ ++ sg_num = 0; ++ sg_len = 0; ++ ++ if (skip < skb_headlen(skb)) { ++ //sg[sg_num].page = virt_to_page(skb->data + skip); ++ //sg[sg_num].offset = offset_in_page(skb->data + skip); ++ len = skb_headlen(skb) - skip; ++ if (len + sg_len > crd->crd_len) ++ len = crd->crd_len - sg_len; ++ //sg[sg_num].length = len; ++ sg_set_page(&sg[sg_num], virt_to_page(skb->data + skip), len, offset_in_page(skb->data + skip)); ++ sg_len += sg[sg_num].length; ++ sg_num++; ++ skip = 0; ++ } else ++ skip -= skb_headlen(skb); ++ ++ for (i = 0; sg_len < crd->crd_len && ++ i < skb_shinfo(skb)->nr_frags && ++ sg_num < SCATTERLIST_MAX; i++) { ++ if (skip < skb_shinfo(skb)->frags[i].size) { ++ //sg[sg_num].page = skb_shinfo(skb)->frags[i].page; ++ //sg[sg_num].offset = skb_shinfo(skb)->frags[i].page_offset + skip; ++ len = skb_shinfo(skb)->frags[i].size - skip; ++ if (len + sg_len > crd->crd_len) ++ len = crd->crd_len - sg_len; ++ //sg[sg_num].length = len; ++ sg_set_page(&sg[sg_num], skb_shinfo(skb)->frags[i].page, len, skb_shinfo(skb)->frags[i].page_offset + skip); ++ sg_len += sg[sg_num].length; ++ sg_num++; ++ skip = 0; ++ } else ++ skip -= skb_shinfo(skb)->frags[i].size; ++ } ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ int len; ++ type = CRYPTO_BUF_IOV; ++ sg_len = 0; ++ for (sg_num = 0; sg_len < crd->crd_len && ++ sg_num < uiop->uio_iovcnt && ++ sg_num < SCATTERLIST_MAX; sg_num++) { ++ if (skip < uiop->uio_iov[sg_num].iov_len) { ++ //sg[sg_num].page = virt_to_page(uiop->uio_iov[sg_num].iov_base+skip); ++ //sg[sg_num].offset = offset_in_page(uiop->uio_iov[sg_num].iov_base+skip); ++ len = uiop->uio_iov[sg_num].iov_len - skip; ++ if (len + sg_len > crd->crd_len) ++ len = crd->crd_len - sg_len; ++ //sg[sg_num].length = len; ++ sg_set_page(&sg[sg_num], virt_to_page(uiop->uio_iov[sg_num].iov_base+skip), len, offset_in_page(uiop->uio_iov[sg_num].iov_base+skip)); ++ sg_len += sg[sg_num].length; ++ skip = 0; ++ } else ++ skip -= uiop->uio_iov[sg_num].iov_len; ++ } ++ } else { ++ type = CRYPTO_BUF_CONTIG; ++ //sg[0].page = virt_to_page(crp->crp_buf + skip); ++ //sg[0].offset = offset_in_page(crp->crp_buf + skip); ++ sg_len = (crp->crp_ilen - skip); ++ if (sg_len > crd->crd_len) ++ sg_len = crd->crd_len; ++ //sg[0].length = sg_len; ++ sg_set_page(&sg[0], virt_to_page(crp->crp_buf + skip), sg_len, offset_in_page(crp->crp_buf + skip)); ++ sg_num = 1; ++ } ++ ++ ++ switch (sw->xfm_type) { ++ ++ case HW_TYPE_CIPHER: { ++ ++ unsigned char iv[64]; ++ unsigned char *ivp = iv; ++ int i; ++ int ivsize = 16; /* fixed for AES */ ++ int blocksize = 16; /* fixed for AES */ ++ ++ if (sg_len < blocksize) { ++ crp->crp_etype = EINVAL; ++ dprintk("%s,%d: EINVAL len %d < %d\n", ++ __FILE__, __LINE__, ++ sg_len, ++ blocksize); ++ goto done; ++ } ++ ++ if (ivsize > sizeof(iv)) { ++ crp->crp_etype = EINVAL; ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ goto done; ++ } ++ ++ if (crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ ++ ++ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { ++ ivp = crd->crd_iv; ++ } else { ++ get_random_bytes(ivp, ivsize); ++ } ++ /* ++ * do we have to copy the IV back to the buffer ? ++ */ ++ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { ++ crypto_copyback(crp->crp_buf, ++ crd->crd_inject, ++ ivsize, ++ (caddr_t)ivp); ++ } ++ ++ c7108_xlate_key(crd->crd_klen, ++ (u8*)crd->crd_key, (u32*)hwkey); ++ ++ /* Encrypt SG list */ ++ for (i = 0; i < sg_num; i++) { ++ sg[i].dma_address = ++ dma_map_single(NULL, ++ kmap(sg_page(&sg[i])) + sg[i].offset, sg_len, DMA_BIDIRECTIONAL); ++#if 0 ++ printk("sg[%d]:0x%08x, off 0x%08x " ++ "kmap 0x%08x phys 0x%08x\n", ++ i, sg[i].page, sg[i].offset, ++ kmap(sg[i].page) + sg[i].offset, ++ sg[i].dma_address); ++#endif ++ c7108_aes_cipher(C7108_AES_ENCRYPT, ++ sg[i].dma_address, ++ sg[i].dma_address, ++ sg_len, ++ crd->crd_klen, ++ c7108_crypto_mode, ++ hwkey, ++ ivp); ++ ++ if ((c7108_crypto_mode == C7108_AES_CTRL_MODE_CBC)|| ++ (c7108_crypto_mode == C7108_AES_CTRL_MODE_ECB)) { ++ /* Read back expanded key and cache it in key ++ * context. ++ * NOTE: for ECB/CBC modes only (not CTR, CFB, OFB) ++ * where you set the key once. ++ */ ++ c7108_cache_key(crd->crd_klen, ++ (u32*)hwkey, (u8*)crd->crd_key); ++#if 0 ++ printk("%s expanded key:", __FUNCTION__); ++ for (i = 0; i < (crd->crd_klen + 7) / 8; i++) ++ printk("%s0x%02x", (i % 8) ? " " : "\n ", ++ crd->crd_key[i]); ++ printk("\n"); ++#endif ++ } ++ } ++ } ++ else { /*decrypt */ ++ ++ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { ++ ivp = crd->crd_iv; ++ } else { ++ crypto_copydata(crp->crp_buf, crd->crd_inject, ++ ivsize, (caddr_t)ivp); ++ } ++ ++ c7108_xlate_key(crd->crd_klen, ++ (u8*)crd->crd_key, (u32*)hwkey); ++ ++ /* Decrypt SG list */ ++ for (i = 0; i < sg_num; i++) { ++ sg[i].dma_address = ++ dma_map_single(NULL, ++ kmap(sg_page(&sg[i])) + sg[i].offset, ++ sg_len, DMA_BIDIRECTIONAL); ++ ++#if 0 ++ printk("sg[%d]:0x%08x, off 0x%08x " ++ "kmap 0x%08x phys 0x%08x\n", ++ i, sg[i].page, sg[i].offset, ++ kmap(sg[i].page) + sg[i].offset, ++ sg[i].dma_address); ++#endif ++ c7108_aes_cipher(C7108_AES_DECRYPT, ++ sg[i].dma_address, ++ sg[i].dma_address, ++ sg_len, ++ crd->crd_klen, ++ c7108_crypto_mode, ++ hwkey, ++ ivp); ++ } ++ } ++ } break; ++ case SW_TYPE_HMAC: ++ case SW_TYPE_HASH: ++ crp->crp_etype = EINVAL; ++ goto done; ++ break; ++ ++ case SW_TYPE_COMP: ++ crp->crp_etype = EINVAL; ++ goto done; ++ break; ++ ++ default: ++ /* Unknown/unsupported algorithm */ ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ crp->crp_etype = EINVAL; ++ goto done; ++ } ++ } ++ ++done: ++ crypto_done(crp); ++ return 0; ++} ++ ++static struct { ++ softc_device_decl sc_dev; ++} a7108dev; ++ ++static device_method_t a7108_methods = { ++/* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, c7108_newsession), ++ DEVMETHOD(cryptodev_freesession, c7108_freesession), ++ DEVMETHOD(cryptodev_process, c7108_process), ++ DEVMETHOD(cryptodev_kprocess, NULL) ++}; ++ ++static int ++cypher_7108_crypto_init(void) ++{ ++ dprintk("%s(%p)\n", __FUNCTION__, cypher_7108_crypto_init); ++ ++ iobar = (unsigned long)ioremap(CCU_AES_REG_BASE, 0x4000); ++ printk("7108: AES @ 0x%08x (0x%08x phys) %s mode\n", ++ iobar, CCU_AES_REG_BASE, ++ c7108_crypto_mode & C7108_AES_CTRL_MODE_CBC ? "CBC" : ++ c7108_crypto_mode & C7108_AES_CTRL_MODE_ECB ? "ECB" : ++ c7108_crypto_mode & C7108_AES_CTRL_MODE_CTR ? "CTR" : ++ c7108_crypto_mode & C7108_AES_CTRL_MODE_CFB ? "CFB" : ++ c7108_crypto_mode & C7108_AES_CTRL_MODE_OFB ? "OFB" : "???"); ++ csr_mutex = SPIN_LOCK_UNLOCKED; ++ ++ memset(&a7108dev, 0, sizeof(a7108dev)); ++ softc_device_init(&a7108dev, "aes7108", 0, a7108_methods); ++ ++ c7108_id = crypto_get_driverid(softc_get_device(&a7108dev), CRYPTOCAP_F_HARDWARE); ++ if (c7108_id < 0) ++ panic("7108: crypto device cannot initialize!"); ++ ++// crypto_register(c7108_id, CRYPTO_AES_CBC, 0, 0, c7108_newsession, c7108_freesession, c7108_process, NULL); ++ crypto_register(c7108_id, CRYPTO_AES_CBC, 0, 0); ++ ++ return(0); ++} ++ ++static void ++cypher_7108_crypto_exit(void) ++{ ++ dprintk("%s()\n", __FUNCTION__); ++ crypto_unregister_all(c7108_id); ++ c7108_id = -1; ++} ++ ++module_init(cypher_7108_crypto_init); ++module_exit(cypher_7108_crypto_exit); ++ ++MODULE_LICENSE("Dual BSD/GPL"); ++MODULE_DESCRIPTION("Cypher 7108 Crypto (OCF module for kernel crypto)"); +diff -Nur linux-3.0.4.orig/crypto/ocf/c7108/aes-7108.h linux-3.0.4/crypto/ocf/c7108/aes-7108.h +--- linux-3.0.4.orig/crypto/ocf/c7108/aes-7108.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/c7108/aes-7108.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,134 @@ ++/* ++ * Copyright (C) 2006 Micronas USA ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored in part by the Defense Advanced Research Projects ++ * Agency (DARPA) and Air Force Research Laboratory, Air Force ++ * Materiel Command, USAF, under agreement number F30602-01-2-0537. ++ * ++ */ ++ ++#ifndef __AES_7108_H__ ++#define __AES_7108_H__ ++ ++/* Cypher 7108 AES Controller Hardware */ ++#define CCU_REG_BASE 0x1b500000 ++#define CCU_AES_REG_BASE (CCU_REG_BASE + 0x100) ++#define C7108_AES_KEY0_LO (0x0000) ++#define C7108_AES_KEY0_HI (0x0004) ++#define C7108_AES_KEY1_LO (0x0008) ++#define C7108_AES_KEY1_HI (0x000c) ++#define C7108_AES_KEY2_LO (0x0010) ++#define C7108_AES_KEY2_HI (0x0014) ++#define C7108_AES_KEY3_LO (0x0018) ++#define C7108_AES_KEY3_HI (0x001c) ++#define C7108_AES_KEY4_LO (0x0020) ++#define C7108_AES_KEY4_HI (0x0024) ++#define C7108_AES_KEY5_LO (0x0028) ++#define C7108_AES_KEY5_HI (0x002c) ++#define C7108_AES_KEY6_LO (0x0030) ++#define C7108_AES_KEY6_HI (0x0034) ++#define C7108_AES_KEY7_LO (0x0038) ++#define C7108_AES_KEY7_HI (0x003c) ++#define C7108_AES_IV0_LO (0x0040) ++#define C7108_AES_IV0_HI (0x0044) ++#define C7108_AES_IV1_LO (0x0048) ++#define C7108_AES_IV1_HI (0x004c) ++#define C7108_AES_IV2_LO (0x0050) ++#define C7108_AES_IV2_HI (0x0054) ++#define C7108_AES_IV3_LO (0x0058) ++#define C7108_AES_IV3_HI (0x005c) ++ ++#define C7108_AES_DMA_SRC0_LO (0x0068) /* Bits 0:15 */ ++#define C7108_AES_DMA_SRC0_HI (0x006c) /* Bits 27:16 */ ++#define C7108_AES_DMA_DST0_LO (0x0070) /* Bits 0:15 */ ++#define C7108_AES_DMA_DST0_HI (0x0074) /* Bits 27:16 */ ++#define C7108_AES_DMA_LEN (0x0078) /*Bytes:(Count+1)x16 */ ++ ++/* AES/Copy engine control register */ ++#define C7108_AES_CTRL (0x007c) /* AES control */ ++#define C7108_AES_CTRL_RS (1<<0) /* Which set of src/dst to use */ ++ ++/* AES Cipher mode, controlled by setting Bits 2:0 */ ++#define C7108_AES_CTRL_MODE_CBC 0 ++#define C7108_AES_CTRL_MODE_CFB (1<<0) ++#define C7108_AES_CTRL_MODE_OFB (1<<1) ++#define C7108_AES_CTRL_MODE_CTR ((1<<0)|(1<<1)) ++#define C7108_AES_CTRL_MODE_ECB (1<<2) ++ ++/* AES Key length , Bits 5:4 */ ++#define C7108_AES_KEY_LEN_128 0 /* 00 */ ++#define C7108_AES_KEY_LEN_192 (1<<4) /* 01 */ ++#define C7108_AES_KEY_LEN_256 (1<<5) /* 10 */ ++ ++/* AES Operation (crypt/decrypt), Bit 3 */ ++#define C7108_AES_DECRYPT (1<<3) /* Clear for encrypt */ ++#define C7108_AES_ENCRYPT 0 ++#define C7108_AES_INTR (1<<13) /* Set on done trans from 0->1*/ ++#define C7108_AES_GO (1<<14) /* Run */ ++#define C7108_AES_OP_DONE (1<<15) /* Set when complete */ ++ ++ ++/* Expanded key registers */ ++#define C7108_AES_EKEY0_LO (0x0080) ++#define C7108_AES_EKEY0_HI (0x0084) ++#define C7108_AES_EKEY1_LO (0x0088) ++#define C7108_AES_EKEY1_HI (0x008c) ++#define C7108_AES_EKEY2_LO (0x0090) ++#define C7108_AES_EKEY2_HI (0x0094) ++#define C7108_AES_EKEY3_LO (0x0098) ++#define C7108_AES_EKEY3_HI (0x009c) ++#define C7108_AES_EKEY4_LO (0x00a0) ++#define C7108_AES_EKEY4_HI (0x00a4) ++#define C7108_AES_EKEY5_LO (0x00a8) ++#define C7108_AES_EKEY5_HI (0x00ac) ++#define C7108_AES_EKEY6_LO (0x00b0) ++#define C7108_AES_EKEY6_HI (0x00b4) ++#define C7108_AES_EKEY7_LO (0x00b8) ++#define C7108_AES_EKEY7_HI (0x00bc) ++#define C7108_AES_OK (0x00fc) /* Reset: "OK" */ ++ ++#define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK) ++ ++/* Software session entry */ ++ ++#define HW_TYPE_CIPHER 0 ++#define SW_TYPE_HMAC 1 ++#define SW_TYPE_AUTH2 2 ++#define SW_TYPE_HASH 3 ++#define SW_TYPE_COMP 4 ++ ++struct cipher_7108 { ++ int xfm_type; ++ int cri_alg; ++ union { ++ struct { ++ char sw_key[HMAC_BLOCK_LEN]; ++ int sw_klen; ++ int sw_authlen; ++ } hmac; ++ } u; ++ struct cipher_7108 *next; ++}; ++ ++ ++ ++#endif /* __C7108_AES_7108_H__ */ +diff -Nur linux-3.0.4.orig/crypto/ocf/criov.c linux-3.0.4/crypto/ocf/criov.c +--- linux-3.0.4.orig/crypto/ocf/criov.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/criov.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,216 @@ ++/* $OpenBSD: criov.c,v 1.9 2002/01/29 15:48:29 jason Exp $ */ ++ ++/* ++ * Linux port done by David McCullough ++ * Copyright (C) 2006-2010 David McCullough ++ * Copyright (C) 2004-2005 Intel Corporation. ++ * The license and original author are listed below. ++ * ++ * Copyright (c) 1999 Theo de Raadt ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++__FBSDID("$FreeBSD: src/sys/opencrypto/criov.c,v 1.5 2006/06/04 22:15:13 pjd Exp $"); ++ */ ++ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++/* ++ * This macro is only for avoiding code duplication, as we need to skip ++ * given number of bytes in the same way in three functions below. ++ */ ++#define CUIO_SKIP() do { \ ++ KASSERT(off >= 0, ("%s: off %d < 0", __func__, off)); \ ++ KASSERT(len >= 0, ("%s: len %d < 0", __func__, len)); \ ++ while (off > 0) { \ ++ KASSERT(iol >= 0, ("%s: empty in skip", __func__)); \ ++ if (off < iov->iov_len) \ ++ break; \ ++ off -= iov->iov_len; \ ++ iol--; \ ++ iov++; \ ++ } \ ++} while (0) ++ ++void ++cuio_copydata(struct uio* uio, int off, int len, caddr_t cp) ++{ ++ struct iovec *iov = uio->uio_iov; ++ int iol = uio->uio_iovcnt; ++ unsigned count; ++ ++ CUIO_SKIP(); ++ while (len > 0) { ++ KASSERT(iol >= 0, ("%s: empty", __func__)); ++ count = min((int)(iov->iov_len - off), len); ++ memcpy(cp, ((caddr_t)iov->iov_base) + off, count); ++ len -= count; ++ cp += count; ++ off = 0; ++ iol--; ++ iov++; ++ } ++} ++ ++void ++cuio_copyback(struct uio* uio, int off, int len, caddr_t cp) ++{ ++ struct iovec *iov = uio->uio_iov; ++ int iol = uio->uio_iovcnt; ++ unsigned count; ++ ++ CUIO_SKIP(); ++ while (len > 0) { ++ KASSERT(iol >= 0, ("%s: empty", __func__)); ++ count = min((int)(iov->iov_len - off), len); ++ memcpy(((caddr_t)iov->iov_base) + off, cp, count); ++ len -= count; ++ cp += count; ++ off = 0; ++ iol--; ++ iov++; ++ } ++} ++ ++/* ++ * Return a pointer to iov/offset of location in iovec list. ++ */ ++struct iovec * ++cuio_getptr(struct uio *uio, int loc, int *off) ++{ ++ struct iovec *iov = uio->uio_iov; ++ int iol = uio->uio_iovcnt; ++ ++ while (loc >= 0) { ++ /* Normal end of search */ ++ if (loc < iov->iov_len) { ++ *off = loc; ++ return (iov); ++ } ++ ++ loc -= iov->iov_len; ++ if (iol == 0) { ++ if (loc == 0) { ++ /* Point at the end of valid data */ ++ *off = iov->iov_len; ++ return (iov); ++ } else ++ return (NULL); ++ } else { ++ iov++, iol--; ++ } ++ } ++ ++ return (NULL); ++} ++ ++EXPORT_SYMBOL(cuio_copyback); ++EXPORT_SYMBOL(cuio_copydata); ++EXPORT_SYMBOL(cuio_getptr); ++ ++ ++static void ++skb_copy_bits_back(struct sk_buff *skb, int offset, caddr_t cp, int len) ++{ ++ int i; ++ if (offset < skb_headlen(skb)) { ++ memcpy(skb->data + offset, cp, min_t(int, skb_headlen(skb), len)); ++ len -= skb_headlen(skb); ++ cp += skb_headlen(skb); ++ } ++ offset -= skb_headlen(skb); ++ for (i = 0; len > 0 && i < skb_shinfo(skb)->nr_frags; i++) { ++ if (offset < skb_shinfo(skb)->frags[i].size) { ++ memcpy(page_address(skb_shinfo(skb)->frags[i].page) + ++ skb_shinfo(skb)->frags[i].page_offset, ++ cp, min_t(int, skb_shinfo(skb)->frags[i].size, len)); ++ len -= skb_shinfo(skb)->frags[i].size; ++ cp += skb_shinfo(skb)->frags[i].size; ++ } ++ offset -= skb_shinfo(skb)->frags[i].size; ++ } ++} ++ ++void ++crypto_copyback(int flags, caddr_t buf, int off, int size, caddr_t in) ++{ ++ ++ if ((flags & CRYPTO_F_SKBUF) != 0) ++ skb_copy_bits_back((struct sk_buff *)buf, off, in, size); ++ else if ((flags & CRYPTO_F_IOV) != 0) ++ cuio_copyback((struct uio *)buf, off, size, in); ++ else ++ bcopy(in, buf + off, size); ++} ++ ++void ++crypto_copydata(int flags, caddr_t buf, int off, int size, caddr_t out) ++{ ++ ++ if ((flags & CRYPTO_F_SKBUF) != 0) ++ skb_copy_bits((struct sk_buff *)buf, off, out, size); ++ else if ((flags & CRYPTO_F_IOV) != 0) ++ cuio_copydata((struct uio *)buf, off, size, out); ++ else ++ bcopy(buf + off, out, size); ++} ++ ++int ++crypto_apply(int flags, caddr_t buf, int off, int len, ++ int (*f)(void *, void *, u_int), void *arg) ++{ ++#if 0 ++ int error; ++ ++ if ((flags & CRYPTO_F_SKBUF) != 0) ++ error = XXXXXX((struct mbuf *)buf, off, len, f, arg); ++ else if ((flags & CRYPTO_F_IOV) != 0) ++ error = cuio_apply((struct uio *)buf, off, len, f, arg); ++ else ++ error = (*f)(arg, buf + off, len); ++ return (error); ++#else ++ KASSERT(0, ("crypto_apply not implemented!\n")); ++#endif ++ return 0; ++} ++ ++EXPORT_SYMBOL(crypto_copyback); ++EXPORT_SYMBOL(crypto_copydata); ++EXPORT_SYMBOL(crypto_apply); ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/crypto.c linux-3.0.4/crypto/ocf/crypto.c +--- linux-3.0.4.orig/crypto/ocf/crypto.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/crypto.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,1766 @@ ++/*- ++ * Linux port done by David McCullough ++ * Copyright (C) 2006-2010 David McCullough ++ * Copyright (C) 2004-2005 Intel Corporation. ++ * The license and original author are listed below. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * Copyright (c) 2002-2006 Sam Leffler. All rights reserved. ++ * ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#if 0 ++#include ++__FBSDID("$FreeBSD: src/sys/opencrypto/crypto.c,v 1.27 2007/03/21 03:42:51 sam Exp $"); ++#endif ++ ++/* ++ * Cryptographic Subsystem. ++ * ++ * This code is derived from the Openbsd Cryptographic Framework (OCF) ++ * that has the copyright shown below. Very little of the original ++ * code remains. ++ */ ++/*- ++ * The author of this code is Angelos D. Keromytis (angelos@cis.upenn.edu) ++ * ++ * This code was written by Angelos D. Keromytis in Athens, Greece, in ++ * February 2000. Network Security Technologies Inc. (NSTI) kindly ++ * supported the development of this code. ++ * ++ * Copyright (c) 2000, 2001 Angelos D. Keromytis ++ * ++ * Permission to use, copy, and modify this software with or without fee ++ * is hereby granted, provided that this entire notice is included in ++ * all source code copies of any software which is or includes a copy or ++ * modification of this software. ++ * ++ * THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR ++ * IMPLIED WARRANTY. IN PARTICULAR, NONE OF THE AUTHORS MAKES ANY ++ * REPRESENTATION OR WARRANTY OF ANY KIND CONCERNING THE ++ * MERCHANTABILITY OF THIS SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR ++ * PURPOSE. ++ * ++__FBSDID("$FreeBSD: src/sys/opencrypto/crypto.c,v 1.16 2005/01/07 02:29:16 imp Exp $"); ++ */ ++ ++ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,4) ++#include ++#endif ++#include ++ ++/* ++ * keep track of whether or not we have been initialised, a big ++ * issue if we are linked into the kernel and a driver gets started before ++ * us ++ */ ++static int crypto_initted = 0; ++ ++/* ++ * Crypto drivers register themselves by allocating a slot in the ++ * crypto_drivers table with crypto_get_driverid() and then registering ++ * each algorithm they support with crypto_register() and crypto_kregister(). ++ */ ++ ++/* ++ * lock on driver table ++ * we track its state as spin_is_locked does not do anything on non-SMP boxes ++ */ ++static spinlock_t crypto_drivers_lock; ++static int crypto_drivers_locked; /* for non-SMP boxes */ ++ ++#define CRYPTO_DRIVER_LOCK() \ ++ ({ \ ++ spin_lock_irqsave(&crypto_drivers_lock, d_flags); \ ++ crypto_drivers_locked = 1; \ ++ dprintk("%s,%d: DRIVER_LOCK()\n", __FILE__, __LINE__); \ ++ }) ++#define CRYPTO_DRIVER_UNLOCK() \ ++ ({ \ ++ dprintk("%s,%d: DRIVER_UNLOCK()\n", __FILE__, __LINE__); \ ++ crypto_drivers_locked = 0; \ ++ spin_unlock_irqrestore(&crypto_drivers_lock, d_flags); \ ++ }) ++#define CRYPTO_DRIVER_ASSERT() \ ++ ({ \ ++ if (!crypto_drivers_locked) { \ ++ dprintk("%s,%d: DRIVER_ASSERT!\n", __FILE__, __LINE__); \ ++ } \ ++ }) ++ ++/* ++ * Crypto device/driver capabilities structure. ++ * ++ * Synchronization: ++ * (d) - protected by CRYPTO_DRIVER_LOCK() ++ * (q) - protected by CRYPTO_Q_LOCK() ++ * Not tagged fields are read-only. ++ */ ++struct cryptocap { ++ device_t cc_dev; /* (d) device/driver */ ++ u_int32_t cc_sessions; /* (d) # of sessions */ ++ u_int32_t cc_koperations; /* (d) # os asym operations */ ++ /* ++ * Largest possible operator length (in bits) for each type of ++ * encryption algorithm. XXX not used ++ */ ++ u_int16_t cc_max_op_len[CRYPTO_ALGORITHM_MAX + 1]; ++ u_int8_t cc_alg[CRYPTO_ALGORITHM_MAX + 1]; ++ u_int8_t cc_kalg[CRK_ALGORITHM_MAX + 1]; ++ ++ int cc_flags; /* (d) flags */ ++#define CRYPTOCAP_F_CLEANUP 0x80000000 /* needs resource cleanup */ ++ int cc_qblocked; /* (q) symmetric q blocked */ ++ int cc_kqblocked; /* (q) asymmetric q blocked */ ++ ++ int cc_unqblocked; /* (q) symmetric q blocked */ ++ int cc_unkqblocked; /* (q) asymmetric q blocked */ ++}; ++static struct cryptocap *crypto_drivers = NULL; ++static int crypto_drivers_num = 0; ++ ++/* ++ * There are two queues for crypto requests; one for symmetric (e.g. ++ * cipher) operations and one for asymmetric (e.g. MOD)operations. ++ * A single mutex is used to lock access to both queues. We could ++ * have one per-queue but having one simplifies handling of block/unblock ++ * operations. ++ */ ++static LIST_HEAD(crp_q); /* crypto request queue */ ++static LIST_HEAD(crp_kq); /* asym request queue */ ++ ++static spinlock_t crypto_q_lock; ++ ++int crypto_all_qblocked = 0; /* protect with Q_LOCK */ ++module_param(crypto_all_qblocked, int, 0444); ++MODULE_PARM_DESC(crypto_all_qblocked, "Are all crypto queues blocked"); ++ ++int crypto_all_kqblocked = 0; /* protect with Q_LOCK */ ++module_param(crypto_all_kqblocked, int, 0444); ++MODULE_PARM_DESC(crypto_all_kqblocked, "Are all asym crypto queues blocked"); ++ ++#define CRYPTO_Q_LOCK() \ ++ ({ \ ++ spin_lock_irqsave(&crypto_q_lock, q_flags); \ ++ dprintk("%s,%d: Q_LOCK()\n", __FILE__, __LINE__); \ ++ }) ++#define CRYPTO_Q_UNLOCK() \ ++ ({ \ ++ dprintk("%s,%d: Q_UNLOCK()\n", __FILE__, __LINE__); \ ++ spin_unlock_irqrestore(&crypto_q_lock, q_flags); \ ++ }) ++ ++/* ++ * There are two queues for processing completed crypto requests; one ++ * for the symmetric and one for the asymmetric ops. We only need one ++ * but have two to avoid type futzing (cryptop vs. cryptkop). A single ++ * mutex is used to lock access to both queues. Note that this lock ++ * must be separate from the lock on request queues to insure driver ++ * callbacks don't generate lock order reversals. ++ */ ++static LIST_HEAD(crp_ret_q); /* callback queues */ ++static LIST_HEAD(crp_ret_kq); ++ ++static spinlock_t crypto_ret_q_lock; ++#define CRYPTO_RETQ_LOCK() \ ++ ({ \ ++ spin_lock_irqsave(&crypto_ret_q_lock, r_flags); \ ++ dprintk("%s,%d: RETQ_LOCK\n", __FILE__, __LINE__); \ ++ }) ++#define CRYPTO_RETQ_UNLOCK() \ ++ ({ \ ++ dprintk("%s,%d: RETQ_UNLOCK\n", __FILE__, __LINE__); \ ++ spin_unlock_irqrestore(&crypto_ret_q_lock, r_flags); \ ++ }) ++#define CRYPTO_RETQ_EMPTY() (list_empty(&crp_ret_q) && list_empty(&crp_ret_kq)) ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) ++static kmem_cache_t *cryptop_zone; ++static kmem_cache_t *cryptodesc_zone; ++#else ++static struct kmem_cache *cryptop_zone; ++static struct kmem_cache *cryptodesc_zone; ++#endif ++ ++#define debug crypto_debug ++int crypto_debug = 0; ++module_param(crypto_debug, int, 0644); ++MODULE_PARM_DESC(crypto_debug, "Enable debug"); ++EXPORT_SYMBOL(crypto_debug); ++ ++/* ++ * Maximum number of outstanding crypto requests before we start ++ * failing requests. We need this to prevent DOS when too many ++ * requests are arriving for us to keep up. Otherwise we will ++ * run the system out of memory. Since crypto is slow, we are ++ * usually the bottleneck that needs to say, enough is enough. ++ * ++ * We cannot print errors when this condition occurs, we are already too ++ * slow, printing anything will just kill us ++ */ ++ ++static int crypto_q_cnt = 0; ++module_param(crypto_q_cnt, int, 0444); ++MODULE_PARM_DESC(crypto_q_cnt, ++ "Current number of outstanding crypto requests"); ++ ++static int crypto_q_max = 1000; ++module_param(crypto_q_max, int, 0644); ++MODULE_PARM_DESC(crypto_q_max, ++ "Maximum number of outstanding crypto requests"); ++ ++#define bootverbose crypto_verbose ++static int crypto_verbose = 0; ++module_param(crypto_verbose, int, 0644); ++MODULE_PARM_DESC(crypto_verbose, ++ "Enable verbose crypto startup"); ++ ++int crypto_usercrypto = 1; /* userland may do crypto reqs */ ++module_param(crypto_usercrypto, int, 0644); ++MODULE_PARM_DESC(crypto_usercrypto, ++ "Enable/disable user-mode access to crypto support"); ++ ++int crypto_userasymcrypto = 1; /* userland may do asym crypto reqs */ ++module_param(crypto_userasymcrypto, int, 0644); ++MODULE_PARM_DESC(crypto_userasymcrypto, ++ "Enable/disable user-mode access to asymmetric crypto support"); ++ ++int crypto_devallowsoft = 0; /* only use hardware crypto */ ++module_param(crypto_devallowsoft, int, 0644); ++MODULE_PARM_DESC(crypto_devallowsoft, ++ "Enable/disable use of software crypto support"); ++ ++/* ++ * This parameter controls the maximum number of crypto operations to ++ * do consecutively in the crypto kernel thread before scheduling to allow ++ * other processes to run. Without it, it is possible to get into a ++ * situation where the crypto thread never allows any other processes to run. ++ * Default to 1000 which should be less than one second. ++ */ ++static int crypto_max_loopcount = 1000; ++module_param(crypto_max_loopcount, int, 0644); ++MODULE_PARM_DESC(crypto_max_loopcount, ++ "Maximum number of crypto ops to do before yielding to other processes"); ++ ++#ifndef CONFIG_NR_CPUS ++#define CONFIG_NR_CPUS 1 ++#endif ++ ++static struct task_struct *cryptoproc[CONFIG_NR_CPUS]; ++static struct task_struct *cryptoretproc[CONFIG_NR_CPUS]; ++static DECLARE_WAIT_QUEUE_HEAD(cryptoproc_wait); ++static DECLARE_WAIT_QUEUE_HEAD(cryptoretproc_wait); ++ ++static int crypto_proc(void *arg); ++static int crypto_ret_proc(void *arg); ++static int crypto_invoke(struct cryptocap *cap, struct cryptop *crp, int hint); ++static int crypto_kinvoke(struct cryptkop *krp, int flags); ++static void crypto_exit(void); ++static int crypto_init(void); ++ ++static struct cryptostats cryptostats; ++ ++static struct cryptocap * ++crypto_checkdriver(u_int32_t hid) ++{ ++ if (crypto_drivers == NULL) ++ return NULL; ++ return (hid >= crypto_drivers_num ? NULL : &crypto_drivers[hid]); ++} ++ ++/* ++ * Compare a driver's list of supported algorithms against another ++ * list; return non-zero if all algorithms are supported. ++ */ ++static int ++driver_suitable(const struct cryptocap *cap, const struct cryptoini *cri) ++{ ++ const struct cryptoini *cr; ++ ++ /* See if all the algorithms are supported. */ ++ for (cr = cri; cr; cr = cr->cri_next) ++ if (cap->cc_alg[cr->cri_alg] == 0) ++ return 0; ++ return 1; ++} ++ ++ ++/* ++ * Select a driver for a new session that supports the specified ++ * algorithms and, optionally, is constrained according to the flags. ++ * The algorithm we use here is pretty stupid; just use the ++ * first driver that supports all the algorithms we need. If there ++ * are multiple drivers we choose the driver with the fewest active ++ * sessions. We prefer hardware-backed drivers to software ones. ++ * ++ * XXX We need more smarts here (in real life too, but that's ++ * XXX another story altogether). ++ */ ++static struct cryptocap * ++crypto_select_driver(const struct cryptoini *cri, int flags) ++{ ++ struct cryptocap *cap, *best; ++ int match, hid; ++ ++ CRYPTO_DRIVER_ASSERT(); ++ ++ /* ++ * Look first for hardware crypto devices if permitted. ++ */ ++ if (flags & CRYPTOCAP_F_HARDWARE) ++ match = CRYPTOCAP_F_HARDWARE; ++ else ++ match = CRYPTOCAP_F_SOFTWARE; ++ best = NULL; ++again: ++ for (hid = 0; hid < crypto_drivers_num; hid++) { ++ cap = &crypto_drivers[hid]; ++ /* ++ * If it's not initialized, is in the process of ++ * going away, or is not appropriate (hardware ++ * or software based on match), then skip. ++ */ ++ if (cap->cc_dev == NULL || ++ (cap->cc_flags & CRYPTOCAP_F_CLEANUP) || ++ (cap->cc_flags & match) == 0) ++ continue; ++ ++ /* verify all the algorithms are supported. */ ++ if (driver_suitable(cap, cri)) { ++ if (best == NULL || ++ cap->cc_sessions < best->cc_sessions) ++ best = cap; ++ } ++ } ++ if (best != NULL) ++ return best; ++ if (match == CRYPTOCAP_F_HARDWARE && (flags & CRYPTOCAP_F_SOFTWARE)) { ++ /* sort of an Algol 68-style for loop */ ++ match = CRYPTOCAP_F_SOFTWARE; ++ goto again; ++ } ++ return best; ++} ++ ++/* ++ * Create a new session. The crid argument specifies a crypto ++ * driver to use or constraints on a driver to select (hardware ++ * only, software only, either). Whatever driver is selected ++ * must be capable of the requested crypto algorithms. ++ */ ++int ++crypto_newsession(u_int64_t *sid, struct cryptoini *cri, int crid) ++{ ++ struct cryptocap *cap; ++ u_int32_t hid, lid; ++ int err; ++ unsigned long d_flags; ++ ++ CRYPTO_DRIVER_LOCK(); ++ if ((crid & (CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE)) == 0) { ++ /* ++ * Use specified driver; verify it is capable. ++ */ ++ cap = crypto_checkdriver(crid); ++ if (cap != NULL && !driver_suitable(cap, cri)) ++ cap = NULL; ++ } else { ++ /* ++ * No requested driver; select based on crid flags. ++ */ ++ cap = crypto_select_driver(cri, crid); ++ /* ++ * if NULL then can't do everything in one session. ++ * XXX Fix this. We need to inject a "virtual" session ++ * XXX layer right about here. ++ */ ++ } ++ if (cap != NULL) { ++ /* Call the driver initialization routine. */ ++ hid = cap - crypto_drivers; ++ lid = hid; /* Pass the driver ID. */ ++ cap->cc_sessions++; ++ CRYPTO_DRIVER_UNLOCK(); ++ err = CRYPTODEV_NEWSESSION(cap->cc_dev, &lid, cri); ++ CRYPTO_DRIVER_LOCK(); ++ if (err == 0) { ++ (*sid) = (cap->cc_flags & 0xff000000) ++ | (hid & 0x00ffffff); ++ (*sid) <<= 32; ++ (*sid) |= (lid & 0xffffffff); ++ } else ++ cap->cc_sessions--; ++ } else ++ err = EINVAL; ++ CRYPTO_DRIVER_UNLOCK(); ++ return err; ++} ++ ++static void ++crypto_remove(struct cryptocap *cap) ++{ ++ CRYPTO_DRIVER_ASSERT(); ++ if (cap->cc_sessions == 0 && cap->cc_koperations == 0) ++ bzero(cap, sizeof(*cap)); ++} ++ ++/* ++ * Delete an existing session (or a reserved session on an unregistered ++ * driver). ++ */ ++int ++crypto_freesession(u_int64_t sid) ++{ ++ struct cryptocap *cap; ++ u_int32_t hid; ++ int err = 0; ++ unsigned long d_flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ CRYPTO_DRIVER_LOCK(); ++ ++ if (crypto_drivers == NULL) { ++ err = EINVAL; ++ goto done; ++ } ++ ++ /* Determine two IDs. */ ++ hid = CRYPTO_SESID2HID(sid); ++ ++ if (hid >= crypto_drivers_num) { ++ dprintk("%s - INVALID DRIVER NUM %d\n", __FUNCTION__, hid); ++ err = ENOENT; ++ goto done; ++ } ++ cap = &crypto_drivers[hid]; ++ ++ if (cap->cc_dev) { ++ CRYPTO_DRIVER_UNLOCK(); ++ /* Call the driver cleanup routine, if available, unlocked. */ ++ err = CRYPTODEV_FREESESSION(cap->cc_dev, sid); ++ CRYPTO_DRIVER_LOCK(); ++ } ++ ++ if (cap->cc_sessions) ++ cap->cc_sessions--; ++ ++ if (cap->cc_flags & CRYPTOCAP_F_CLEANUP) ++ crypto_remove(cap); ++ ++done: ++ CRYPTO_DRIVER_UNLOCK(); ++ return err; ++} ++ ++/* ++ * Return an unused driver id. Used by drivers prior to registering ++ * support for the algorithms they handle. ++ */ ++int32_t ++crypto_get_driverid(device_t dev, int flags) ++{ ++ struct cryptocap *newdrv; ++ int i; ++ unsigned long d_flags; ++ ++ if ((flags & (CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE)) == 0) { ++ printf("%s: no flags specified when registering driver\n", ++ device_get_nameunit(dev)); ++ return -1; ++ } ++ ++ CRYPTO_DRIVER_LOCK(); ++ ++ for (i = 0; i < crypto_drivers_num; i++) { ++ if (crypto_drivers[i].cc_dev == NULL && ++ (crypto_drivers[i].cc_flags & CRYPTOCAP_F_CLEANUP) == 0) { ++ break; ++ } ++ } ++ ++ /* Out of entries, allocate some more. */ ++ if (i == crypto_drivers_num) { ++ /* Be careful about wrap-around. */ ++ if (2 * crypto_drivers_num <= crypto_drivers_num) { ++ CRYPTO_DRIVER_UNLOCK(); ++ printk("crypto: driver count wraparound!\n"); ++ return -1; ++ } ++ ++ newdrv = kmalloc(2 * crypto_drivers_num * sizeof(struct cryptocap), ++ GFP_KERNEL); ++ if (newdrv == NULL) { ++ CRYPTO_DRIVER_UNLOCK(); ++ printk("crypto: no space to expand driver table!\n"); ++ return -1; ++ } ++ ++ memcpy(newdrv, crypto_drivers, ++ crypto_drivers_num * sizeof(struct cryptocap)); ++ memset(&newdrv[crypto_drivers_num], 0, ++ crypto_drivers_num * sizeof(struct cryptocap)); ++ ++ crypto_drivers_num *= 2; ++ ++ kfree(crypto_drivers); ++ crypto_drivers = newdrv; ++ } ++ ++ /* NB: state is zero'd on free */ ++ crypto_drivers[i].cc_sessions = 1; /* Mark */ ++ crypto_drivers[i].cc_dev = dev; ++ crypto_drivers[i].cc_flags = flags; ++ if (bootverbose) ++ printf("crypto: assign %s driver id %u, flags %u\n", ++ device_get_nameunit(dev), i, flags); ++ ++ CRYPTO_DRIVER_UNLOCK(); ++ ++ return i; ++} ++ ++/* ++ * Lookup a driver by name. We match against the full device ++ * name and unit, and against just the name. The latter gives ++ * us a simple widlcarding by device name. On success return the ++ * driver/hardware identifier; otherwise return -1. ++ */ ++int ++crypto_find_driver(const char *match) ++{ ++ int i, len = strlen(match); ++ unsigned long d_flags; ++ ++ CRYPTO_DRIVER_LOCK(); ++ for (i = 0; i < crypto_drivers_num; i++) { ++ device_t dev = crypto_drivers[i].cc_dev; ++ if (dev == NULL || ++ (crypto_drivers[i].cc_flags & CRYPTOCAP_F_CLEANUP)) ++ continue; ++ if (strncmp(match, device_get_nameunit(dev), len) == 0 || ++ strncmp(match, device_get_name(dev), len) == 0) ++ break; ++ } ++ CRYPTO_DRIVER_UNLOCK(); ++ return i < crypto_drivers_num ? i : -1; ++} ++ ++/* ++ * Return the device_t for the specified driver or NULL ++ * if the driver identifier is invalid. ++ */ ++device_t ++crypto_find_device_byhid(int hid) ++{ ++ struct cryptocap *cap = crypto_checkdriver(hid); ++ return cap != NULL ? cap->cc_dev : NULL; ++} ++ ++/* ++ * Return the device/driver capabilities. ++ */ ++int ++crypto_getcaps(int hid) ++{ ++ struct cryptocap *cap = crypto_checkdriver(hid); ++ return cap != NULL ? cap->cc_flags : 0; ++} ++ ++/* ++ * Register support for a key-related algorithm. This routine ++ * is called once for each algorithm supported a driver. ++ */ ++int ++crypto_kregister(u_int32_t driverid, int kalg, u_int32_t flags) ++{ ++ struct cryptocap *cap; ++ int err; ++ unsigned long d_flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ CRYPTO_DRIVER_LOCK(); ++ ++ cap = crypto_checkdriver(driverid); ++ if (cap != NULL && ++ (CRK_ALGORITM_MIN <= kalg && kalg <= CRK_ALGORITHM_MAX)) { ++ /* ++ * XXX Do some performance testing to determine placing. ++ * XXX We probably need an auxiliary data structure that ++ * XXX describes relative performances. ++ */ ++ ++ cap->cc_kalg[kalg] = flags | CRYPTO_ALG_FLAG_SUPPORTED; ++ if (bootverbose) ++ printf("crypto: %s registers key alg %u flags %u\n" ++ , device_get_nameunit(cap->cc_dev) ++ , kalg ++ , flags ++ ); ++ err = 0; ++ } else ++ err = EINVAL; ++ ++ CRYPTO_DRIVER_UNLOCK(); ++ return err; ++} ++ ++/* ++ * Register support for a non-key-related algorithm. This routine ++ * is called once for each such algorithm supported by a driver. ++ */ ++int ++crypto_register(u_int32_t driverid, int alg, u_int16_t maxoplen, ++ u_int32_t flags) ++{ ++ struct cryptocap *cap; ++ int err; ++ unsigned long d_flags; ++ ++ dprintk("%s(id=0x%x, alg=%d, maxoplen=%d, flags=0x%x)\n", __FUNCTION__, ++ driverid, alg, maxoplen, flags); ++ ++ CRYPTO_DRIVER_LOCK(); ++ ++ cap = crypto_checkdriver(driverid); ++ /* NB: algorithms are in the range [1..max] */ ++ if (cap != NULL && ++ (CRYPTO_ALGORITHM_MIN <= alg && alg <= CRYPTO_ALGORITHM_MAX)) { ++ /* ++ * XXX Do some performance testing to determine placing. ++ * XXX We probably need an auxiliary data structure that ++ * XXX describes relative performances. ++ */ ++ ++ cap->cc_alg[alg] = flags | CRYPTO_ALG_FLAG_SUPPORTED; ++ cap->cc_max_op_len[alg] = maxoplen; ++ if (bootverbose) ++ printf("crypto: %s registers alg %u flags %u maxoplen %u\n" ++ , device_get_nameunit(cap->cc_dev) ++ , alg ++ , flags ++ , maxoplen ++ ); ++ cap->cc_sessions = 0; /* Unmark */ ++ err = 0; ++ } else ++ err = EINVAL; ++ ++ CRYPTO_DRIVER_UNLOCK(); ++ return err; ++} ++ ++static void ++driver_finis(struct cryptocap *cap) ++{ ++ u_int32_t ses, kops; ++ ++ CRYPTO_DRIVER_ASSERT(); ++ ++ ses = cap->cc_sessions; ++ kops = cap->cc_koperations; ++ bzero(cap, sizeof(*cap)); ++ if (ses != 0 || kops != 0) { ++ /* ++ * If there are pending sessions, ++ * just mark as invalid. ++ */ ++ cap->cc_flags |= CRYPTOCAP_F_CLEANUP; ++ cap->cc_sessions = ses; ++ cap->cc_koperations = kops; ++ } ++} ++ ++/* ++ * Unregister a crypto driver. If there are pending sessions using it, ++ * leave enough information around so that subsequent calls using those ++ * sessions will correctly detect the driver has been unregistered and ++ * reroute requests. ++ */ ++int ++crypto_unregister(u_int32_t driverid, int alg) ++{ ++ struct cryptocap *cap; ++ int i, err; ++ unsigned long d_flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ CRYPTO_DRIVER_LOCK(); ++ ++ cap = crypto_checkdriver(driverid); ++ if (cap != NULL && ++ (CRYPTO_ALGORITHM_MIN <= alg && alg <= CRYPTO_ALGORITHM_MAX) && ++ cap->cc_alg[alg] != 0) { ++ cap->cc_alg[alg] = 0; ++ cap->cc_max_op_len[alg] = 0; ++ ++ /* Was this the last algorithm ? */ ++ for (i = 1; i <= CRYPTO_ALGORITHM_MAX; i++) ++ if (cap->cc_alg[i] != 0) ++ break; ++ ++ if (i == CRYPTO_ALGORITHM_MAX + 1) ++ driver_finis(cap); ++ err = 0; ++ } else ++ err = EINVAL; ++ CRYPTO_DRIVER_UNLOCK(); ++ return err; ++} ++ ++/* ++ * Unregister all algorithms associated with a crypto driver. ++ * If there are pending sessions using it, leave enough information ++ * around so that subsequent calls using those sessions will ++ * correctly detect the driver has been unregistered and reroute ++ * requests. ++ */ ++int ++crypto_unregister_all(u_int32_t driverid) ++{ ++ struct cryptocap *cap; ++ int err; ++ unsigned long d_flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ CRYPTO_DRIVER_LOCK(); ++ cap = crypto_checkdriver(driverid); ++ if (cap != NULL) { ++ driver_finis(cap); ++ err = 0; ++ } else ++ err = EINVAL; ++ CRYPTO_DRIVER_UNLOCK(); ++ ++ return err; ++} ++ ++/* ++ * Clear blockage on a driver. The what parameter indicates whether ++ * the driver is now ready for cryptop's and/or cryptokop's. ++ */ ++int ++crypto_unblock(u_int32_t driverid, int what) ++{ ++ struct cryptocap *cap; ++ int err; ++ unsigned long q_flags; ++ ++ CRYPTO_Q_LOCK(); ++ cap = crypto_checkdriver(driverid); ++ if (cap != NULL) { ++ if (what & CRYPTO_SYMQ) { ++ cap->cc_qblocked = 0; ++ cap->cc_unqblocked = 0; ++ crypto_all_qblocked = 0; ++ } ++ if (what & CRYPTO_ASYMQ) { ++ cap->cc_kqblocked = 0; ++ cap->cc_unkqblocked = 0; ++ crypto_all_kqblocked = 0; ++ } ++ wake_up_interruptible(&cryptoproc_wait); ++ err = 0; ++ } else ++ err = EINVAL; ++ CRYPTO_Q_UNLOCK(); //DAVIDM should this be a driver lock ++ ++ return err; ++} ++ ++/* ++ * Add a crypto request to a queue, to be processed by the kernel thread. ++ */ ++int ++crypto_dispatch(struct cryptop *crp) ++{ ++ struct cryptocap *cap; ++ int result = -1; ++ unsigned long q_flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ cryptostats.cs_ops++; ++ ++ CRYPTO_Q_LOCK(); ++ if (crypto_q_cnt >= crypto_q_max) { ++ cryptostats.cs_drops++; ++ CRYPTO_Q_UNLOCK(); ++ return ENOMEM; ++ } ++ crypto_q_cnt++; ++ ++ /* make sure we are starting a fresh run on this crp. */ ++ crp->crp_flags &= ~CRYPTO_F_DONE; ++ crp->crp_etype = 0; ++ ++ /* ++ * Caller marked the request to be processed immediately; dispatch ++ * it directly to the driver unless the driver is currently blocked. ++ */ ++ if ((crp->crp_flags & CRYPTO_F_BATCH) == 0) { ++ int hid = CRYPTO_SESID2HID(crp->crp_sid); ++ cap = crypto_checkdriver(hid); ++ /* Driver cannot disappear when there is an active session. */ ++ KASSERT(cap != NULL, ("%s: Driver disappeared.", __func__)); ++ if (!cap->cc_qblocked) { ++ crypto_all_qblocked = 0; ++ crypto_drivers[hid].cc_unqblocked = 1; ++ CRYPTO_Q_UNLOCK(); ++ result = crypto_invoke(cap, crp, 0); ++ CRYPTO_Q_LOCK(); ++ if (result == ERESTART) ++ if (crypto_drivers[hid].cc_unqblocked) ++ crypto_drivers[hid].cc_qblocked = 1; ++ crypto_drivers[hid].cc_unqblocked = 0; ++ } ++ } ++ if (result == ERESTART) { ++ /* ++ * The driver ran out of resources, mark the ++ * driver ``blocked'' for cryptop's and put ++ * the request back in the queue. It would ++ * best to put the request back where we got ++ * it but that's hard so for now we put it ++ * at the front. This should be ok; putting ++ * it at the end does not work. ++ */ ++ list_add(&crp->crp_next, &crp_q); ++ cryptostats.cs_blocks++; ++ result = 0; ++ } else if (result == -1) { ++ TAILQ_INSERT_TAIL(&crp_q, crp, crp_next); ++ result = 0; ++ } ++ wake_up_interruptible(&cryptoproc_wait); ++ CRYPTO_Q_UNLOCK(); ++ return result; ++} ++ ++/* ++ * Add an asymetric crypto request to a queue, ++ * to be processed by the kernel thread. ++ */ ++int ++crypto_kdispatch(struct cryptkop *krp) ++{ ++ int error; ++ unsigned long q_flags; ++ ++ cryptostats.cs_kops++; ++ ++ error = crypto_kinvoke(krp, krp->krp_crid); ++ if (error == ERESTART) { ++ CRYPTO_Q_LOCK(); ++ TAILQ_INSERT_TAIL(&crp_kq, krp, krp_next); ++ wake_up_interruptible(&cryptoproc_wait); ++ CRYPTO_Q_UNLOCK(); ++ error = 0; ++ } ++ return error; ++} ++ ++/* ++ * Verify a driver is suitable for the specified operation. ++ */ ++static __inline int ++kdriver_suitable(const struct cryptocap *cap, const struct cryptkop *krp) ++{ ++ return (cap->cc_kalg[krp->krp_op] & CRYPTO_ALG_FLAG_SUPPORTED) != 0; ++} ++ ++/* ++ * Select a driver for an asym operation. The driver must ++ * support the necessary algorithm. The caller can constrain ++ * which device is selected with the flags parameter. The ++ * algorithm we use here is pretty stupid; just use the first ++ * driver that supports the algorithms we need. If there are ++ * multiple suitable drivers we choose the driver with the ++ * fewest active operations. We prefer hardware-backed ++ * drivers to software ones when either may be used. ++ */ ++static struct cryptocap * ++crypto_select_kdriver(const struct cryptkop *krp, int flags) ++{ ++ struct cryptocap *cap, *best, *blocked; ++ int match, hid; ++ ++ CRYPTO_DRIVER_ASSERT(); ++ ++ /* ++ * Look first for hardware crypto devices if permitted. ++ */ ++ if (flags & CRYPTOCAP_F_HARDWARE) ++ match = CRYPTOCAP_F_HARDWARE; ++ else ++ match = CRYPTOCAP_F_SOFTWARE; ++ best = NULL; ++ blocked = NULL; ++again: ++ for (hid = 0; hid < crypto_drivers_num; hid++) { ++ cap = &crypto_drivers[hid]; ++ /* ++ * If it's not initialized, is in the process of ++ * going away, or is not appropriate (hardware ++ * or software based on match), then skip. ++ */ ++ if (cap->cc_dev == NULL || ++ (cap->cc_flags & CRYPTOCAP_F_CLEANUP) || ++ (cap->cc_flags & match) == 0) ++ continue; ++ ++ /* verify all the algorithms are supported. */ ++ if (kdriver_suitable(cap, krp)) { ++ if (best == NULL || ++ cap->cc_koperations < best->cc_koperations) ++ best = cap; ++ } ++ } ++ if (best != NULL) ++ return best; ++ if (match == CRYPTOCAP_F_HARDWARE && (flags & CRYPTOCAP_F_SOFTWARE)) { ++ /* sort of an Algol 68-style for loop */ ++ match = CRYPTOCAP_F_SOFTWARE; ++ goto again; ++ } ++ return best; ++} ++ ++/* ++ * Dispatch an assymetric crypto request. ++ */ ++static int ++crypto_kinvoke(struct cryptkop *krp, int crid) ++{ ++ struct cryptocap *cap = NULL; ++ int error; ++ unsigned long d_flags; ++ ++ KASSERT(krp != NULL, ("%s: krp == NULL", __func__)); ++ KASSERT(krp->krp_callback != NULL, ++ ("%s: krp->crp_callback == NULL", __func__)); ++ ++ CRYPTO_DRIVER_LOCK(); ++ if ((crid & (CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE)) == 0) { ++ cap = crypto_checkdriver(crid); ++ if (cap != NULL) { ++ /* ++ * Driver present, it must support the necessary ++ * algorithm and, if s/w drivers are excluded, ++ * it must be registered as hardware-backed. ++ */ ++ if (!kdriver_suitable(cap, krp) || ++ (!crypto_devallowsoft && ++ (cap->cc_flags & CRYPTOCAP_F_HARDWARE) == 0)) ++ cap = NULL; ++ } ++ } else { ++ /* ++ * No requested driver; select based on crid flags. ++ */ ++ if (!crypto_devallowsoft) /* NB: disallow s/w drivers */ ++ crid &= ~CRYPTOCAP_F_SOFTWARE; ++ cap = crypto_select_kdriver(krp, crid); ++ } ++ if (cap != NULL && !cap->cc_kqblocked) { ++ krp->krp_hid = cap - crypto_drivers; ++ cap->cc_koperations++; ++ CRYPTO_DRIVER_UNLOCK(); ++ error = CRYPTODEV_KPROCESS(cap->cc_dev, krp, 0); ++ CRYPTO_DRIVER_LOCK(); ++ if (error == ERESTART) { ++ cap->cc_koperations--; ++ CRYPTO_DRIVER_UNLOCK(); ++ return (error); ++ } ++ /* return the actual device used */ ++ krp->krp_crid = krp->krp_hid; ++ } else { ++ /* ++ * NB: cap is !NULL if device is blocked; in ++ * that case return ERESTART so the operation ++ * is resubmitted if possible. ++ */ ++ error = (cap == NULL) ? ENODEV : ERESTART; ++ } ++ CRYPTO_DRIVER_UNLOCK(); ++ ++ if (error) { ++ krp->krp_status = error; ++ crypto_kdone(krp); ++ } ++ return 0; ++} ++ ++ ++/* ++ * Dispatch a crypto request to the appropriate crypto devices. ++ */ ++static int ++crypto_invoke(struct cryptocap *cap, struct cryptop *crp, int hint) ++{ ++ KASSERT(crp != NULL, ("%s: crp == NULL", __func__)); ++ KASSERT(crp->crp_callback != NULL, ++ ("%s: crp->crp_callback == NULL", __func__)); ++ KASSERT(crp->crp_desc != NULL, ("%s: crp->crp_desc == NULL", __func__)); ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++#ifdef CRYPTO_TIMING ++ if (crypto_timing) ++ crypto_tstat(&cryptostats.cs_invoke, &crp->crp_tstamp); ++#endif ++ if (cap->cc_flags & CRYPTOCAP_F_CLEANUP) { ++ struct cryptodesc *crd; ++ u_int64_t nid; ++ ++ /* ++ * Driver has unregistered; migrate the session and return ++ * an error to the caller so they'll resubmit the op. ++ * ++ * XXX: What if there are more already queued requests for this ++ * session? ++ */ ++ crypto_freesession(crp->crp_sid); ++ ++ for (crd = crp->crp_desc; crd->crd_next; crd = crd->crd_next) ++ crd->CRD_INI.cri_next = &(crd->crd_next->CRD_INI); ++ ++ /* XXX propagate flags from initial session? */ ++ if (crypto_newsession(&nid, &(crp->crp_desc->CRD_INI), ++ CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE) == 0) ++ crp->crp_sid = nid; ++ ++ crp->crp_etype = EAGAIN; ++ crypto_done(crp); ++ return 0; ++ } else { ++ /* ++ * Invoke the driver to process the request. ++ */ ++ return CRYPTODEV_PROCESS(cap->cc_dev, crp, hint); ++ } ++} ++ ++/* ++ * Release a set of crypto descriptors. ++ */ ++void ++crypto_freereq(struct cryptop *crp) ++{ ++ struct cryptodesc *crd; ++ ++ if (crp == NULL) ++ return; ++ ++#ifdef DIAGNOSTIC ++ { ++ struct cryptop *crp2; ++ unsigned long q_flags; ++ ++ CRYPTO_Q_LOCK(); ++ TAILQ_FOREACH(crp2, &crp_q, crp_next) { ++ KASSERT(crp2 != crp, ++ ("Freeing cryptop from the crypto queue (%p).", ++ crp)); ++ } ++ CRYPTO_Q_UNLOCK(); ++ CRYPTO_RETQ_LOCK(); ++ TAILQ_FOREACH(crp2, &crp_ret_q, crp_next) { ++ KASSERT(crp2 != crp, ++ ("Freeing cryptop from the return queue (%p).", ++ crp)); ++ } ++ CRYPTO_RETQ_UNLOCK(); ++ } ++#endif ++ ++ while ((crd = crp->crp_desc) != NULL) { ++ crp->crp_desc = crd->crd_next; ++ kmem_cache_free(cryptodesc_zone, crd); ++ } ++ kmem_cache_free(cryptop_zone, crp); ++} ++ ++/* ++ * Acquire a set of crypto descriptors. ++ */ ++struct cryptop * ++crypto_getreq(int num) ++{ ++ struct cryptodesc *crd; ++ struct cryptop *crp; ++ ++ crp = kmem_cache_alloc(cryptop_zone, SLAB_ATOMIC); ++ if (crp != NULL) { ++ memset(crp, 0, sizeof(*crp)); ++ INIT_LIST_HEAD(&crp->crp_next); ++ init_waitqueue_head(&crp->crp_waitq); ++ while (num--) { ++ crd = kmem_cache_alloc(cryptodesc_zone, SLAB_ATOMIC); ++ if (crd == NULL) { ++ crypto_freereq(crp); ++ return NULL; ++ } ++ memset(crd, 0, sizeof(*crd)); ++ crd->crd_next = crp->crp_desc; ++ crp->crp_desc = crd; ++ } ++ } ++ return crp; ++} ++ ++/* ++ * Invoke the callback on behalf of the driver. ++ */ ++void ++crypto_done(struct cryptop *crp) ++{ ++ unsigned long q_flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if ((crp->crp_flags & CRYPTO_F_DONE) == 0) { ++ crp->crp_flags |= CRYPTO_F_DONE; ++ CRYPTO_Q_LOCK(); ++ crypto_q_cnt--; ++ CRYPTO_Q_UNLOCK(); ++ } else ++ printk("crypto: crypto_done op already done, flags 0x%x", ++ crp->crp_flags); ++ if (crp->crp_etype != 0) ++ cryptostats.cs_errs++; ++ /* ++ * CBIMM means unconditionally do the callback immediately; ++ * CBIFSYNC means do the callback immediately only if the ++ * operation was done synchronously. Both are used to avoid ++ * doing extraneous context switches; the latter is mostly ++ * used with the software crypto driver. ++ */ ++ if ((crp->crp_flags & CRYPTO_F_CBIMM) || ++ ((crp->crp_flags & CRYPTO_F_CBIFSYNC) && ++ (CRYPTO_SESID2CAPS(crp->crp_sid) & CRYPTOCAP_F_SYNC))) { ++ /* ++ * Do the callback directly. This is ok when the ++ * callback routine does very little (e.g. the ++ * /dev/crypto callback method just does a wakeup). ++ */ ++ crp->crp_callback(crp); ++ } else { ++ unsigned long r_flags; ++ /* ++ * Normal case; queue the callback for the thread. ++ */ ++ CRYPTO_RETQ_LOCK(); ++ wake_up_interruptible(&cryptoretproc_wait);/* shared wait channel */ ++ TAILQ_INSERT_TAIL(&crp_ret_q, crp, crp_next); ++ CRYPTO_RETQ_UNLOCK(); ++ } ++} ++ ++/* ++ * Invoke the callback on behalf of the driver. ++ */ ++void ++crypto_kdone(struct cryptkop *krp) ++{ ++ struct cryptocap *cap; ++ unsigned long d_flags; ++ ++ if ((krp->krp_flags & CRYPTO_KF_DONE) != 0) ++ printk("crypto: crypto_kdone op already done, flags 0x%x", ++ krp->krp_flags); ++ krp->krp_flags |= CRYPTO_KF_DONE; ++ if (krp->krp_status != 0) ++ cryptostats.cs_kerrs++; ++ ++ CRYPTO_DRIVER_LOCK(); ++ /* XXX: What if driver is loaded in the meantime? */ ++ if (krp->krp_hid < crypto_drivers_num) { ++ cap = &crypto_drivers[krp->krp_hid]; ++ cap->cc_koperations--; ++ KASSERT(cap->cc_koperations >= 0, ("cc_koperations < 0")); ++ if (cap->cc_flags & CRYPTOCAP_F_CLEANUP) ++ crypto_remove(cap); ++ } ++ CRYPTO_DRIVER_UNLOCK(); ++ ++ /* ++ * CBIMM means unconditionally do the callback immediately; ++ * This is used to avoid doing extraneous context switches ++ */ ++ if ((krp->krp_flags & CRYPTO_KF_CBIMM)) { ++ /* ++ * Do the callback directly. This is ok when the ++ * callback routine does very little (e.g. the ++ * /dev/crypto callback method just does a wakeup). ++ */ ++ krp->krp_callback(krp); ++ } else { ++ unsigned long r_flags; ++ /* ++ * Normal case; queue the callback for the thread. ++ */ ++ CRYPTO_RETQ_LOCK(); ++ wake_up_interruptible(&cryptoretproc_wait);/* shared wait channel */ ++ TAILQ_INSERT_TAIL(&crp_ret_kq, krp, krp_next); ++ CRYPTO_RETQ_UNLOCK(); ++ } ++} ++ ++int ++crypto_getfeat(int *featp) ++{ ++ int hid, kalg, feat = 0; ++ unsigned long d_flags; ++ ++ CRYPTO_DRIVER_LOCK(); ++ for (hid = 0; hid < crypto_drivers_num; hid++) { ++ const struct cryptocap *cap = &crypto_drivers[hid]; ++ ++ if ((cap->cc_flags & CRYPTOCAP_F_SOFTWARE) && ++ !crypto_devallowsoft) { ++ continue; ++ } ++ for (kalg = 0; kalg < CRK_ALGORITHM_MAX; kalg++) ++ if (cap->cc_kalg[kalg] & CRYPTO_ALG_FLAG_SUPPORTED) ++ feat |= 1 << kalg; ++ } ++ CRYPTO_DRIVER_UNLOCK(); ++ *featp = feat; ++ return (0); ++} ++ ++/* ++ * Crypto thread, dispatches crypto requests. ++ */ ++static int ++crypto_proc(void *arg) ++{ ++ struct cryptop *crp, *submit; ++ struct cryptkop *krp, *krpp; ++ struct cryptocap *cap; ++ u_int32_t hid; ++ int result, hint; ++ unsigned long q_flags; ++ int loopcount = 0; ++ ++ set_current_state(TASK_INTERRUPTIBLE); ++ ++ CRYPTO_Q_LOCK(); ++ for (;;) { ++ /* ++ * we need to make sure we don't get into a busy loop with nothing ++ * to do, the two crypto_all_*blocked vars help us find out when ++ * we are all full and can do nothing on any driver or Q. If so we ++ * wait for an unblock. ++ */ ++ crypto_all_qblocked = !list_empty(&crp_q); ++ ++ /* ++ * Find the first element in the queue that can be ++ * processed and look-ahead to see if multiple ops ++ * are ready for the same driver. ++ */ ++ submit = NULL; ++ hint = 0; ++ list_for_each_entry(crp, &crp_q, crp_next) { ++ hid = CRYPTO_SESID2HID(crp->crp_sid); ++ cap = crypto_checkdriver(hid); ++ /* ++ * Driver cannot disappear when there is an active ++ * session. ++ */ ++ KASSERT(cap != NULL, ("%s:%u Driver disappeared.", ++ __func__, __LINE__)); ++ if (cap == NULL || cap->cc_dev == NULL) { ++ /* Op needs to be migrated, process it. */ ++ if (submit == NULL) ++ submit = crp; ++ break; ++ } ++ if (!cap->cc_qblocked) { ++ if (submit != NULL) { ++ /* ++ * We stop on finding another op, ++ * regardless whether its for the same ++ * driver or not. We could keep ++ * searching the queue but it might be ++ * better to just use a per-driver ++ * queue instead. ++ */ ++ if (CRYPTO_SESID2HID(submit->crp_sid) == hid) ++ hint = CRYPTO_HINT_MORE; ++ break; ++ } else { ++ submit = crp; ++ if ((submit->crp_flags & CRYPTO_F_BATCH) == 0) ++ break; ++ /* keep scanning for more are q'd */ ++ } ++ } ++ } ++ if (submit != NULL) { ++ hid = CRYPTO_SESID2HID(submit->crp_sid); ++ crypto_all_qblocked = 0; ++ list_del(&submit->crp_next); ++ crypto_drivers[hid].cc_unqblocked = 1; ++ cap = crypto_checkdriver(hid); ++ CRYPTO_Q_UNLOCK(); ++ KASSERT(cap != NULL, ("%s:%u Driver disappeared.", ++ __func__, __LINE__)); ++ result = crypto_invoke(cap, submit, hint); ++ CRYPTO_Q_LOCK(); ++ if (result == ERESTART) { ++ /* ++ * The driver ran out of resources, mark the ++ * driver ``blocked'' for cryptop's and put ++ * the request back in the queue. It would ++ * best to put the request back where we got ++ * it but that's hard so for now we put it ++ * at the front. This should be ok; putting ++ * it at the end does not work. ++ */ ++ /* XXX validate sid again? */ ++ list_add(&submit->crp_next, &crp_q); ++ cryptostats.cs_blocks++; ++ if (crypto_drivers[hid].cc_unqblocked) ++ crypto_drivers[hid].cc_qblocked=0; ++ crypto_drivers[hid].cc_unqblocked=0; ++ } ++ crypto_drivers[hid].cc_unqblocked = 0; ++ } ++ ++ crypto_all_kqblocked = !list_empty(&crp_kq); ++ ++ /* As above, but for key ops */ ++ krp = NULL; ++ list_for_each_entry(krpp, &crp_kq, krp_next) { ++ cap = crypto_checkdriver(krpp->krp_hid); ++ if (cap == NULL || cap->cc_dev == NULL) { ++ /* ++ * Operation needs to be migrated, invalidate ++ * the assigned device so it will reselect a ++ * new one below. Propagate the original ++ * crid selection flags if supplied. ++ */ ++ krp->krp_hid = krp->krp_crid & ++ (CRYPTOCAP_F_SOFTWARE|CRYPTOCAP_F_HARDWARE); ++ if (krp->krp_hid == 0) ++ krp->krp_hid = ++ CRYPTOCAP_F_SOFTWARE|CRYPTOCAP_F_HARDWARE; ++ break; ++ } ++ if (!cap->cc_kqblocked) { ++ krp = krpp; ++ break; ++ } ++ } ++ if (krp != NULL) { ++ crypto_all_kqblocked = 0; ++ list_del(&krp->krp_next); ++ crypto_drivers[krp->krp_hid].cc_kqblocked = 1; ++ CRYPTO_Q_UNLOCK(); ++ result = crypto_kinvoke(krp, krp->krp_hid); ++ CRYPTO_Q_LOCK(); ++ if (result == ERESTART) { ++ /* ++ * The driver ran out of resources, mark the ++ * driver ``blocked'' for cryptkop's and put ++ * the request back in the queue. It would ++ * best to put the request back where we got ++ * it but that's hard so for now we put it ++ * at the front. This should be ok; putting ++ * it at the end does not work. ++ */ ++ /* XXX validate sid again? */ ++ list_add(&krp->krp_next, &crp_kq); ++ cryptostats.cs_kblocks++; ++ } else ++ crypto_drivers[krp->krp_hid].cc_kqblocked = 0; ++ } ++ ++ if (submit == NULL && krp == NULL) { ++ /* ++ * Nothing more to be processed. Sleep until we're ++ * woken because there are more ops to process. ++ * This happens either by submission or by a driver ++ * becoming unblocked and notifying us through ++ * crypto_unblock. Note that when we wakeup we ++ * start processing each queue again from the ++ * front. It's not clear that it's important to ++ * preserve this ordering since ops may finish ++ * out of order if dispatched to different devices ++ * and some become blocked while others do not. ++ */ ++ dprintk("%s - sleeping (qe=%d qb=%d kqe=%d kqb=%d)\n", ++ __FUNCTION__, ++ list_empty(&crp_q), crypto_all_qblocked, ++ list_empty(&crp_kq), crypto_all_kqblocked); ++ loopcount = 0; ++ CRYPTO_Q_UNLOCK(); ++ wait_event_interruptible(cryptoproc_wait, ++ !(list_empty(&crp_q) || crypto_all_qblocked) || ++ !(list_empty(&crp_kq) || crypto_all_kqblocked) || ++ kthread_should_stop()); ++ if (signal_pending (current)) { ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++ spin_lock_irq(¤t->sigmask_lock); ++#endif ++ flush_signals(current); ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++ spin_unlock_irq(¤t->sigmask_lock); ++#endif ++ } ++ CRYPTO_Q_LOCK(); ++ dprintk("%s - awake\n", __FUNCTION__); ++ if (kthread_should_stop()) ++ break; ++ cryptostats.cs_intrs++; ++ } else if (loopcount > crypto_max_loopcount) { ++ /* ++ * Give other processes a chance to run if we've ++ * been using the CPU exclusively for a while. ++ */ ++ loopcount = 0; ++ CRYPTO_Q_UNLOCK(); ++ schedule(); ++ CRYPTO_Q_LOCK(); ++ } ++ loopcount++; ++ } ++ CRYPTO_Q_UNLOCK(); ++ return 0; ++} ++ ++/* ++ * Crypto returns thread, does callbacks for processed crypto requests. ++ * Callbacks are done here, rather than in the crypto drivers, because ++ * callbacks typically are expensive and would slow interrupt handling. ++ */ ++static int ++crypto_ret_proc(void *arg) ++{ ++ struct cryptop *crpt; ++ struct cryptkop *krpt; ++ unsigned long r_flags; ++ ++ set_current_state(TASK_INTERRUPTIBLE); ++ ++ CRYPTO_RETQ_LOCK(); ++ for (;;) { ++ /* Harvest return q's for completed ops */ ++ crpt = NULL; ++ if (!list_empty(&crp_ret_q)) ++ crpt = list_entry(crp_ret_q.next, typeof(*crpt), crp_next); ++ if (crpt != NULL) ++ list_del(&crpt->crp_next); ++ ++ krpt = NULL; ++ if (!list_empty(&crp_ret_kq)) ++ krpt = list_entry(crp_ret_kq.next, typeof(*krpt), krp_next); ++ if (krpt != NULL) ++ list_del(&krpt->krp_next); ++ ++ if (crpt != NULL || krpt != NULL) { ++ CRYPTO_RETQ_UNLOCK(); ++ /* ++ * Run callbacks unlocked. ++ */ ++ if (crpt != NULL) ++ crpt->crp_callback(crpt); ++ if (krpt != NULL) ++ krpt->krp_callback(krpt); ++ CRYPTO_RETQ_LOCK(); ++ } else { ++ /* ++ * Nothing more to be processed. Sleep until we're ++ * woken because there are more returns to process. ++ */ ++ dprintk("%s - sleeping\n", __FUNCTION__); ++ CRYPTO_RETQ_UNLOCK(); ++ wait_event_interruptible(cryptoretproc_wait, ++ !list_empty(&crp_ret_q) || ++ !list_empty(&crp_ret_kq) || ++ kthread_should_stop()); ++ if (signal_pending (current)) { ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++ spin_lock_irq(¤t->sigmask_lock); ++#endif ++ flush_signals(current); ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++ spin_unlock_irq(¤t->sigmask_lock); ++#endif ++ } ++ CRYPTO_RETQ_LOCK(); ++ dprintk("%s - awake\n", __FUNCTION__); ++ if (kthread_should_stop()) { ++ dprintk("%s - EXITING!\n", __FUNCTION__); ++ break; ++ } ++ cryptostats.cs_rets++; ++ } ++ } ++ CRYPTO_RETQ_UNLOCK(); ++ return 0; ++} ++ ++ ++#if 0 /* should put this into /proc or something */ ++static void ++db_show_drivers(void) ++{ ++ int hid; ++ ++ db_printf("%12s %4s %4s %8s %2s %2s\n" ++ , "Device" ++ , "Ses" ++ , "Kops" ++ , "Flags" ++ , "QB" ++ , "KB" ++ ); ++ for (hid = 0; hid < crypto_drivers_num; hid++) { ++ const struct cryptocap *cap = &crypto_drivers[hid]; ++ if (cap->cc_dev == NULL) ++ continue; ++ db_printf("%-12s %4u %4u %08x %2u %2u\n" ++ , device_get_nameunit(cap->cc_dev) ++ , cap->cc_sessions ++ , cap->cc_koperations ++ , cap->cc_flags ++ , cap->cc_qblocked ++ , cap->cc_kqblocked ++ ); ++ } ++} ++ ++DB_SHOW_COMMAND(crypto, db_show_crypto) ++{ ++ struct cryptop *crp; ++ ++ db_show_drivers(); ++ db_printf("\n"); ++ ++ db_printf("%4s %8s %4s %4s %4s %4s %8s %8s\n", ++ "HID", "Caps", "Ilen", "Olen", "Etype", "Flags", ++ "Desc", "Callback"); ++ TAILQ_FOREACH(crp, &crp_q, crp_next) { ++ db_printf("%4u %08x %4u %4u %4u %04x %8p %8p\n" ++ , (int) CRYPTO_SESID2HID(crp->crp_sid) ++ , (int) CRYPTO_SESID2CAPS(crp->crp_sid) ++ , crp->crp_ilen, crp->crp_olen ++ , crp->crp_etype ++ , crp->crp_flags ++ , crp->crp_desc ++ , crp->crp_callback ++ ); ++ } ++ if (!TAILQ_EMPTY(&crp_ret_q)) { ++ db_printf("\n%4s %4s %4s %8s\n", ++ "HID", "Etype", "Flags", "Callback"); ++ TAILQ_FOREACH(crp, &crp_ret_q, crp_next) { ++ db_printf("%4u %4u %04x %8p\n" ++ , (int) CRYPTO_SESID2HID(crp->crp_sid) ++ , crp->crp_etype ++ , crp->crp_flags ++ , crp->crp_callback ++ ); ++ } ++ } ++} ++ ++DB_SHOW_COMMAND(kcrypto, db_show_kcrypto) ++{ ++ struct cryptkop *krp; ++ ++ db_show_drivers(); ++ db_printf("\n"); ++ ++ db_printf("%4s %5s %4s %4s %8s %4s %8s\n", ++ "Op", "Status", "#IP", "#OP", "CRID", "HID", "Callback"); ++ TAILQ_FOREACH(krp, &crp_kq, krp_next) { ++ db_printf("%4u %5u %4u %4u %08x %4u %8p\n" ++ , krp->krp_op ++ , krp->krp_status ++ , krp->krp_iparams, krp->krp_oparams ++ , krp->krp_crid, krp->krp_hid ++ , krp->krp_callback ++ ); ++ } ++ if (!TAILQ_EMPTY(&crp_ret_q)) { ++ db_printf("%4s %5s %8s %4s %8s\n", ++ "Op", "Status", "CRID", "HID", "Callback"); ++ TAILQ_FOREACH(krp, &crp_ret_kq, krp_next) { ++ db_printf("%4u %5u %08x %4u %8p\n" ++ , krp->krp_op ++ , krp->krp_status ++ , krp->krp_crid, krp->krp_hid ++ , krp->krp_callback ++ ); ++ } ++ } ++} ++#endif ++ ++ ++static int ++crypto_init(void) ++{ ++ int error; ++ unsigned long cpu; ++ ++ dprintk("%s(%p)\n", __FUNCTION__, (void *) crypto_init); ++ ++ if (crypto_initted) ++ return 0; ++ crypto_initted = 1; ++ ++ spin_lock_init(&crypto_drivers_lock); ++ spin_lock_init(&crypto_q_lock); ++ spin_lock_init(&crypto_ret_q_lock); ++ ++ cryptop_zone = kmem_cache_create("cryptop", sizeof(struct cryptop), ++ 0, SLAB_HWCACHE_ALIGN, NULL ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) ++ , NULL ++#endif ++ ); ++ ++ cryptodesc_zone = kmem_cache_create("cryptodesc", sizeof(struct cryptodesc), ++ 0, SLAB_HWCACHE_ALIGN, NULL ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) ++ , NULL ++#endif ++ ); ++ ++ if (cryptodesc_zone == NULL || cryptop_zone == NULL) { ++ printk("crypto: crypto_init cannot setup crypto zones\n"); ++ error = ENOMEM; ++ goto bad; ++ } ++ ++ crypto_drivers_num = CRYPTO_DRIVERS_INITIAL; ++ crypto_drivers = kmalloc(crypto_drivers_num * sizeof(struct cryptocap), ++ GFP_KERNEL); ++ if (crypto_drivers == NULL) { ++ printk("crypto: crypto_init cannot setup crypto drivers\n"); ++ error = ENOMEM; ++ goto bad; ++ } ++ ++ memset(crypto_drivers, 0, crypto_drivers_num * sizeof(struct cryptocap)); ++ ++ ocf_for_each_cpu(cpu) { ++ cryptoproc[cpu] = kthread_create(crypto_proc, (void *) cpu, ++ "ocf_%d", (int) cpu); ++ if (IS_ERR(cryptoproc[cpu])) { ++ error = PTR_ERR(cryptoproc[cpu]); ++ printk("crypto: crypto_init cannot start crypto thread; error %d", ++ error); ++ goto bad; ++ } ++ kthread_bind(cryptoproc[cpu], cpu); ++ wake_up_process(cryptoproc[cpu]); ++ ++ cryptoretproc[cpu] = kthread_create(crypto_ret_proc, (void *) cpu, ++ "ocf_ret_%d", (int) cpu); ++ if (IS_ERR(cryptoretproc[cpu])) { ++ error = PTR_ERR(cryptoretproc[cpu]); ++ printk("crypto: crypto_init cannot start cryptoret thread; error %d", ++ error); ++ goto bad; ++ } ++ kthread_bind(cryptoretproc[cpu], cpu); ++ wake_up_process(cryptoretproc[cpu]); ++ } ++ ++ return 0; ++bad: ++ crypto_exit(); ++ return error; ++} ++ ++ ++static void ++crypto_exit(void) ++{ ++ int cpu; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ /* ++ * Terminate any crypto threads. ++ */ ++ ocf_for_each_cpu(cpu) { ++ kthread_stop(cryptoproc[cpu]); ++ kthread_stop(cryptoretproc[cpu]); ++ } ++ ++ /* ++ * Reclaim dynamically allocated resources. ++ */ ++ if (crypto_drivers != NULL) ++ kfree(crypto_drivers); ++ ++ if (cryptodesc_zone != NULL) ++ kmem_cache_destroy(cryptodesc_zone); ++ if (cryptop_zone != NULL) ++ kmem_cache_destroy(cryptop_zone); ++} ++ ++ ++EXPORT_SYMBOL(crypto_newsession); ++EXPORT_SYMBOL(crypto_freesession); ++EXPORT_SYMBOL(crypto_get_driverid); ++EXPORT_SYMBOL(crypto_kregister); ++EXPORT_SYMBOL(crypto_register); ++EXPORT_SYMBOL(crypto_unregister); ++EXPORT_SYMBOL(crypto_unregister_all); ++EXPORT_SYMBOL(crypto_unblock); ++EXPORT_SYMBOL(crypto_dispatch); ++EXPORT_SYMBOL(crypto_kdispatch); ++EXPORT_SYMBOL(crypto_freereq); ++EXPORT_SYMBOL(crypto_getreq); ++EXPORT_SYMBOL(crypto_done); ++EXPORT_SYMBOL(crypto_kdone); ++EXPORT_SYMBOL(crypto_getfeat); ++EXPORT_SYMBOL(crypto_userasymcrypto); ++EXPORT_SYMBOL(crypto_getcaps); ++EXPORT_SYMBOL(crypto_find_driver); ++EXPORT_SYMBOL(crypto_find_device_byhid); ++ ++module_init(crypto_init); ++module_exit(crypto_exit); ++ ++MODULE_LICENSE("BSD"); ++MODULE_AUTHOR("David McCullough "); ++MODULE_DESCRIPTION("OCF (OpenBSD Cryptographic Framework)"); +diff -Nur linux-3.0.4.orig/crypto/ocf/cryptocteon/Makefile linux-3.0.4/crypto/ocf/cryptocteon/Makefile +--- linux-3.0.4.orig/crypto/ocf/cryptocteon/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/cryptocteon/Makefile 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,17 @@ ++# for SGlinux builds ++-include $(ROOTDIR)/modules/.config ++ ++obj-$(CONFIG_OCF_CRYPTOCTEON) += cryptocteon.o ++ ++obj ?= . ++EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ ++ ++ifdef CONFIG_OCF_CRYPTOCTEON ++# you need the cavium crypto component installed ++EXTRA_CFLAGS += -I$(ROOTDIR)/prop/include ++endif ++ ++ifdef TOPDIR ++-include $(TOPDIR)/Rules.make ++endif ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/cryptocteon/README.txt linux-3.0.4/crypto/ocf/cryptocteon/README.txt +--- linux-3.0.4.orig/crypto/ocf/cryptocteon/README.txt 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/cryptocteon/README.txt 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,11 @@ ++ ++You will need the CRYPTO package installed to build this driver, and ++potentially the ADK. ++ ++cavium_crypto sourced from: ++ ++ adk/components/source/cavium_ipsec_kame/cavium_ipsec.c ++ ++and significantly modified to suit use with OCF. All original ++copyright/ownership headers retained. ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/cryptocteon/cavium_crypto.c linux-3.0.4/crypto/ocf/cryptocteon/cavium_crypto.c +--- linux-3.0.4.orig/crypto/ocf/cryptocteon/cavium_crypto.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/cryptocteon/cavium_crypto.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,2283 @@ ++/* ++ * Copyright (c) 2009 David McCullough ++ * ++ * Copyright (c) 2003-2007 Cavium Networks (support@cavium.com). All rights ++ * reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * 1. Redistributions of source code must retain the above copyright notice, ++ * this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright notice, ++ * this list of conditions and the following disclaimer in the documentation ++ * and/or other materials provided with the distribution. ++ * 3. All advertising materials mentioning features or use of this software ++ * must display the following acknowledgement: ++ * This product includes software developed by Cavium Networks ++ * 4. Cavium Networks' name may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * This Software, including technical data, may be subject to U.S. export ++ * control laws, including the U.S. Export Administration Act and its ++ * associated regulations, and may be subject to export or import regulations ++ * in other countries. You warrant that You will comply strictly in all ++ * respects with all such regulations and acknowledge that you have the ++ * responsibility to obtain licenses to export, re-export or import the ++ * Software. ++ * ++ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" AND ++ * WITH ALL FAULTS AND CAVIUM MAKES NO PROMISES, REPRESENTATIONS OR WARRANTIES, ++ * EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO THE ++ * SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR ++ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM ++ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, ++ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF ++ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR ++ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR ++ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. ++*/ ++/****************************************************************************/ ++ ++#include ++#include ++#include "octeon-asm.h" ++ ++/****************************************************************************/ ++ ++extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *); ++extern void octeon_crypto_disable(struct octeon_cop2_state *, unsigned long); ++ ++#define SG_INIT(s, p, i, l) \ ++ { \ ++ (i) = 0; \ ++ (l) = (s)[0].length; \ ++ (p) = (typeof(p)) sg_virt((s)); \ ++ CVMX_PREFETCH0((p)); \ ++ } ++ ++#define SG_CONSUME(s, p, i, l) \ ++ { \ ++ (p)++; \ ++ (l) -= sizeof(*(p)); \ ++ if ((l) < 0) { \ ++ dprintk("%s, %d: l = %d\n", __FILE__, __LINE__, l); \ ++ } else if ((l) == 0) { \ ++ (i)++; \ ++ (l) = (s)[0].length; \ ++ (p) = (typeof(p)) sg_virt(s); \ ++ CVMX_PREFETCH0((p)); \ ++ } \ ++ } ++ ++#define ESP_HEADER_LENGTH 8 ++#define DES_CBC_IV_LENGTH 8 ++#define AES_CBC_IV_LENGTH 16 ++#define ESP_HMAC_LEN 12 ++ ++#define ESP_HEADER_LENGTH 8 ++#define DES_CBC_IV_LENGTH 8 ++ ++/****************************************************************************/ ++ ++#define CVM_LOAD_SHA_UNIT(dat, next) { \ ++ if (next == 0) { \ ++ next = 1; \ ++ CVMX_MT_HSH_DAT (dat, 0); \ ++ } else if (next == 1) { \ ++ next = 2; \ ++ CVMX_MT_HSH_DAT (dat, 1); \ ++ } else if (next == 2) { \ ++ next = 3; \ ++ CVMX_MT_HSH_DAT (dat, 2); \ ++ } else if (next == 3) { \ ++ next = 4; \ ++ CVMX_MT_HSH_DAT (dat, 3); \ ++ } else if (next == 4) { \ ++ next = 5; \ ++ CVMX_MT_HSH_DAT (dat, 4); \ ++ } else if (next == 5) { \ ++ next = 6; \ ++ CVMX_MT_HSH_DAT (dat, 5); \ ++ } else if (next == 6) { \ ++ next = 7; \ ++ CVMX_MT_HSH_DAT (dat, 6); \ ++ } else { \ ++ CVMX_MT_HSH_STARTSHA (dat); \ ++ next = 0; \ ++ } \ ++} ++ ++#define CVM_LOAD2_SHA_UNIT(dat1, dat2, next) { \ ++ if (next == 0) { \ ++ CVMX_MT_HSH_DAT (dat1, 0); \ ++ CVMX_MT_HSH_DAT (dat2, 1); \ ++ next = 2; \ ++ } else if (next == 1) { \ ++ CVMX_MT_HSH_DAT (dat1, 1); \ ++ CVMX_MT_HSH_DAT (dat2, 2); \ ++ next = 3; \ ++ } else if (next == 2) { \ ++ CVMX_MT_HSH_DAT (dat1, 2); \ ++ CVMX_MT_HSH_DAT (dat2, 3); \ ++ next = 4; \ ++ } else if (next == 3) { \ ++ CVMX_MT_HSH_DAT (dat1, 3); \ ++ CVMX_MT_HSH_DAT (dat2, 4); \ ++ next = 5; \ ++ } else if (next == 4) { \ ++ CVMX_MT_HSH_DAT (dat1, 4); \ ++ CVMX_MT_HSH_DAT (dat2, 5); \ ++ next = 6; \ ++ } else if (next == 5) { \ ++ CVMX_MT_HSH_DAT (dat1, 5); \ ++ CVMX_MT_HSH_DAT (dat2, 6); \ ++ next = 7; \ ++ } else if (next == 6) { \ ++ CVMX_MT_HSH_DAT (dat1, 6); \ ++ CVMX_MT_HSH_STARTSHA (dat2); \ ++ next = 0; \ ++ } else { \ ++ CVMX_MT_HSH_STARTSHA (dat1); \ ++ CVMX_MT_HSH_DAT (dat2, 0); \ ++ next = 1; \ ++ } \ ++} ++ ++/****************************************************************************/ ++ ++#define CVM_LOAD_MD5_UNIT(dat, next) { \ ++ if (next == 0) { \ ++ next = 1; \ ++ CVMX_MT_HSH_DAT (dat, 0); \ ++ } else if (next == 1) { \ ++ next = 2; \ ++ CVMX_MT_HSH_DAT (dat, 1); \ ++ } else if (next == 2) { \ ++ next = 3; \ ++ CVMX_MT_HSH_DAT (dat, 2); \ ++ } else if (next == 3) { \ ++ next = 4; \ ++ CVMX_MT_HSH_DAT (dat, 3); \ ++ } else if (next == 4) { \ ++ next = 5; \ ++ CVMX_MT_HSH_DAT (dat, 4); \ ++ } else if (next == 5) { \ ++ next = 6; \ ++ CVMX_MT_HSH_DAT (dat, 5); \ ++ } else if (next == 6) { \ ++ next = 7; \ ++ CVMX_MT_HSH_DAT (dat, 6); \ ++ } else { \ ++ CVMX_MT_HSH_STARTMD5 (dat); \ ++ next = 0; \ ++ } \ ++} ++ ++#define CVM_LOAD2_MD5_UNIT(dat1, dat2, next) { \ ++ if (next == 0) { \ ++ CVMX_MT_HSH_DAT (dat1, 0); \ ++ CVMX_MT_HSH_DAT (dat2, 1); \ ++ next = 2; \ ++ } else if (next == 1) { \ ++ CVMX_MT_HSH_DAT (dat1, 1); \ ++ CVMX_MT_HSH_DAT (dat2, 2); \ ++ next = 3; \ ++ } else if (next == 2) { \ ++ CVMX_MT_HSH_DAT (dat1, 2); \ ++ CVMX_MT_HSH_DAT (dat2, 3); \ ++ next = 4; \ ++ } else if (next == 3) { \ ++ CVMX_MT_HSH_DAT (dat1, 3); \ ++ CVMX_MT_HSH_DAT (dat2, 4); \ ++ next = 5; \ ++ } else if (next == 4) { \ ++ CVMX_MT_HSH_DAT (dat1, 4); \ ++ CVMX_MT_HSH_DAT (dat2, 5); \ ++ next = 6; \ ++ } else if (next == 5) { \ ++ CVMX_MT_HSH_DAT (dat1, 5); \ ++ CVMX_MT_HSH_DAT (dat2, 6); \ ++ next = 7; \ ++ } else if (next == 6) { \ ++ CVMX_MT_HSH_DAT (dat1, 6); \ ++ CVMX_MT_HSH_STARTMD5 (dat2); \ ++ next = 0; \ ++ } else { \ ++ CVMX_MT_HSH_STARTMD5 (dat1); \ ++ CVMX_MT_HSH_DAT (dat2, 0); \ ++ next = 1; \ ++ } \ ++} ++ ++/****************************************************************************/ ++ ++static inline uint64_t ++swap64(uint64_t a) ++{ ++ return ((a >> 56) | ++ (((a >> 48) & 0xfful) << 8) | ++ (((a >> 40) & 0xfful) << 16) | ++ (((a >> 32) & 0xfful) << 24) | ++ (((a >> 24) & 0xfful) << 32) | ++ (((a >> 16) & 0xfful) << 40) | ++ (((a >> 8) & 0xfful) << 48) | (((a >> 0) & 0xfful) << 56)); ++} ++ ++/****************************************************************************/ ++ ++void ++octo_calc_hash(__u8 auth, unsigned char *key, uint64_t *inner, uint64_t *outer) ++{ ++ uint8_t hash_key[64]; ++ uint64_t *key1; ++ register uint64_t xor1 = 0x3636363636363636ULL; ++ register uint64_t xor2 = 0x5c5c5c5c5c5c5c5cULL; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ memset(hash_key, 0, sizeof(hash_key)); ++ memcpy(hash_key, (uint8_t *) key, (auth ? 20 : 16)); ++ key1 = (uint64_t *) hash_key; ++ flags = octeon_crypto_enable(&state); ++ if (auth) { ++ CVMX_MT_HSH_IV(0x67452301EFCDAB89ULL, 0); ++ CVMX_MT_HSH_IV(0x98BADCFE10325476ULL, 1); ++ CVMX_MT_HSH_IV(0xC3D2E1F000000000ULL, 2); ++ } else { ++ CVMX_MT_HSH_IV(0x0123456789ABCDEFULL, 0); ++ CVMX_MT_HSH_IV(0xFEDCBA9876543210ULL, 1); ++ } ++ ++ CVMX_MT_HSH_DAT((*key1 ^ xor1), 0); ++ key1++; ++ CVMX_MT_HSH_DAT((*key1 ^ xor1), 1); ++ key1++; ++ CVMX_MT_HSH_DAT((*key1 ^ xor1), 2); ++ key1++; ++ CVMX_MT_HSH_DAT((*key1 ^ xor1), 3); ++ key1++; ++ CVMX_MT_HSH_DAT((*key1 ^ xor1), 4); ++ key1++; ++ CVMX_MT_HSH_DAT((*key1 ^ xor1), 5); ++ key1++; ++ CVMX_MT_HSH_DAT((*key1 ^ xor1), 6); ++ key1++; ++ if (auth) ++ CVMX_MT_HSH_STARTSHA((*key1 ^ xor1)); ++ else ++ CVMX_MT_HSH_STARTMD5((*key1 ^ xor1)); ++ ++ CVMX_MF_HSH_IV(inner[0], 0); ++ CVMX_MF_HSH_IV(inner[1], 1); ++ if (auth) { ++ inner[2] = 0; ++ CVMX_MF_HSH_IV(((uint64_t *) inner)[2], 2); ++ } ++ ++ memset(hash_key, 0, sizeof(hash_key)); ++ memcpy(hash_key, (uint8_t *) key, (auth ? 20 : 16)); ++ key1 = (uint64_t *) hash_key; ++ if (auth) { ++ CVMX_MT_HSH_IV(0x67452301EFCDAB89ULL, 0); ++ CVMX_MT_HSH_IV(0x98BADCFE10325476ULL, 1); ++ CVMX_MT_HSH_IV(0xC3D2E1F000000000ULL, 2); ++ } else { ++ CVMX_MT_HSH_IV(0x0123456789ABCDEFULL, 0); ++ CVMX_MT_HSH_IV(0xFEDCBA9876543210ULL, 1); ++ } ++ ++ CVMX_MT_HSH_DAT((*key1 ^ xor2), 0); ++ key1++; ++ CVMX_MT_HSH_DAT((*key1 ^ xor2), 1); ++ key1++; ++ CVMX_MT_HSH_DAT((*key1 ^ xor2), 2); ++ key1++; ++ CVMX_MT_HSH_DAT((*key1 ^ xor2), 3); ++ key1++; ++ CVMX_MT_HSH_DAT((*key1 ^ xor2), 4); ++ key1++; ++ CVMX_MT_HSH_DAT((*key1 ^ xor2), 5); ++ key1++; ++ CVMX_MT_HSH_DAT((*key1 ^ xor2), 6); ++ key1++; ++ if (auth) ++ CVMX_MT_HSH_STARTSHA((*key1 ^ xor2)); ++ else ++ CVMX_MT_HSH_STARTMD5((*key1 ^ xor2)); ++ ++ CVMX_MF_HSH_IV(outer[0], 0); ++ CVMX_MF_HSH_IV(outer[1], 1); ++ if (auth) { ++ outer[2] = 0; ++ CVMX_MF_HSH_IV(outer[2], 2); ++ } ++ octeon_crypto_disable(&state, flags); ++ return; ++} ++ ++/****************************************************************************/ ++/* DES functions */ ++ ++int ++octo_des_cbc_encrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ uint64_t *data; ++ int data_i, data_l; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || ++ (crypt_off & 0x7) || (crypt_off + crypt_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data, data_i, data_l); ++ ++ CVMX_PREFETCH0(ivp); ++ CVMX_PREFETCH0(od->octo_enckey); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* load 3DES Key */ ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); ++ if (od->octo_encklen == 24) { ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ } else if (od->octo_encklen == 8) { ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); ++ } else { ++ octeon_crypto_disable(&state, flags); ++ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); ++ return -EINVAL; ++ } ++ ++ CVMX_MT_3DES_IV(* (uint64_t *) ivp); ++ ++ while (crypt_off > 0) { ++ SG_CONSUME(sg, data, data_i, data_l); ++ crypt_off -= 8; ++ } ++ ++ while (crypt_len > 0) { ++ CVMX_MT_3DES_ENC_CBC(*data); ++ CVMX_MF_3DES_RESULT(*data); ++ SG_CONSUME(sg, data, data_i, data_l); ++ crypt_len -= 8; ++ } ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++ ++int ++octo_des_cbc_decrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ uint64_t *data; ++ int data_i, data_l; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || ++ (crypt_off & 0x7) || (crypt_off + crypt_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data, data_i, data_l); ++ ++ CVMX_PREFETCH0(ivp); ++ CVMX_PREFETCH0(od->octo_enckey); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* load 3DES Key */ ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); ++ if (od->octo_encklen == 24) { ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ } else if (od->octo_encklen == 8) { ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); ++ } else { ++ octeon_crypto_disable(&state, flags); ++ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); ++ return -EINVAL; ++ } ++ ++ CVMX_MT_3DES_IV(* (uint64_t *) ivp); ++ ++ while (crypt_off > 0) { ++ SG_CONSUME(sg, data, data_i, data_l); ++ crypt_off -= 8; ++ } ++ ++ while (crypt_len > 0) { ++ CVMX_MT_3DES_DEC_CBC(*data); ++ CVMX_MF_3DES_RESULT(*data); ++ SG_CONSUME(sg, data, data_i, data_l); ++ crypt_len -= 8; ++ } ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++/****************************************************************************/ ++/* AES functions */ ++ ++int ++octo_aes_cbc_encrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ uint64_t *data, *pdata; ++ int data_i, data_l; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || ++ (crypt_off & 0x7) || (crypt_off + crypt_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data, data_i, data_l); ++ ++ CVMX_PREFETCH0(ivp); ++ CVMX_PREFETCH0(od->octo_enckey); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* load AES Key */ ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); ++ ++ if (od->octo_encklen == 16) { ++ CVMX_MT_AES_KEY(0x0, 2); ++ CVMX_MT_AES_KEY(0x0, 3); ++ } else if (od->octo_encklen == 24) { ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ CVMX_MT_AES_KEY(0x0, 3); ++ } else if (od->octo_encklen == 32) { ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); ++ } else { ++ octeon_crypto_disable(&state, flags); ++ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); ++ return -EINVAL; ++ } ++ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); ++ ++ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); ++ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); ++ ++ while (crypt_off > 0) { ++ SG_CONSUME(sg, data, data_i, data_l); ++ crypt_off -= 8; ++ } ++ ++ while (crypt_len > 0) { ++ pdata = data; ++ CVMX_MT_AES_ENC_CBC0(*data); ++ SG_CONSUME(sg, data, data_i, data_l); ++ CVMX_MT_AES_ENC_CBC1(*data); ++ CVMX_MF_AES_RESULT(*pdata, 0); ++ CVMX_MF_AES_RESULT(*data, 1); ++ SG_CONSUME(sg, data, data_i, data_l); ++ crypt_len -= 16; ++ } ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++ ++int ++octo_aes_cbc_decrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ uint64_t *data, *pdata; ++ int data_i, data_l; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || ++ (crypt_off & 0x7) || (crypt_off + crypt_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data, data_i, data_l); ++ ++ CVMX_PREFETCH0(ivp); ++ CVMX_PREFETCH0(od->octo_enckey); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* load AES Key */ ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); ++ ++ if (od->octo_encklen == 16) { ++ CVMX_MT_AES_KEY(0x0, 2); ++ CVMX_MT_AES_KEY(0x0, 3); ++ } else if (od->octo_encklen == 24) { ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ CVMX_MT_AES_KEY(0x0, 3); ++ } else if (od->octo_encklen == 32) { ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); ++ } else { ++ octeon_crypto_disable(&state, flags); ++ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); ++ return -EINVAL; ++ } ++ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); ++ ++ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); ++ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); ++ ++ while (crypt_off > 0) { ++ SG_CONSUME(sg, data, data_i, data_l); ++ crypt_off -= 8; ++ } ++ ++ while (crypt_len > 0) { ++ pdata = data; ++ CVMX_MT_AES_DEC_CBC0(*data); ++ SG_CONSUME(sg, data, data_i, data_l); ++ CVMX_MT_AES_DEC_CBC1(*data); ++ CVMX_MF_AES_RESULT(*pdata, 0); ++ CVMX_MF_AES_RESULT(*data, 1); ++ SG_CONSUME(sg, data, data_i, data_l); ++ crypt_len -= 16; ++ } ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++/****************************************************************************/ ++/* MD5 */ ++ ++int ++octo_null_md5_encrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ register int next = 0; ++ uint64_t *data; ++ uint64_t tmp1, tmp2; ++ int data_i, data_l, alen = auth_len; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ++ (auth_off & 0x7) || (auth_off + auth_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data, data_i, data_l); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* Load MD5 IV */ ++ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); ++ ++ while (auth_off > 0) { ++ SG_CONSUME(sg, data, data_i, data_l); ++ auth_off -= 8; ++ } ++ ++ while (auth_len > 0) { ++ CVM_LOAD_MD5_UNIT(*data, next); ++ auth_len -= 8; ++ SG_CONSUME(sg, data, data_i, data_l); ++ } ++ ++ /* finish the hash */ ++ CVMX_PREFETCH0(od->octo_hmouter); ++#if 0 ++ if (unlikely(inplen)) { ++ uint64_t tmp = 0; ++ uint8_t *p = (uint8_t *) & tmp; ++ p[inplen] = 0x80; ++ do { ++ inplen--; ++ p[inplen] = ((uint8_t *) data)[inplen]; ++ } while (inplen); ++ CVM_LOAD_MD5_UNIT(tmp, next); ++ } else { ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++ } ++#else ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++#endif ++ ++ /* Finish Inner hash */ ++ while (next != 7) { ++ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); ++ } ++ CVMX_ES64(tmp1, ((alen + 64) << 3)); ++ CVM_LOAD_MD5_UNIT(tmp1, next); ++ ++ /* Get the inner hash of HMAC */ ++ CVMX_MF_HSH_IV(tmp1, 0); ++ CVMX_MF_HSH_IV(tmp2, 1); ++ ++ /* Initialize hash unit */ ++ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); ++ ++ CVMX_MT_HSH_DAT(tmp1, 0); ++ CVMX_MT_HSH_DAT(tmp2, 1); ++ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); ++ CVMX_MT_HSH_DATZ(3); ++ CVMX_MT_HSH_DATZ(4); ++ CVMX_MT_HSH_DATZ(5); ++ CVMX_MT_HSH_DATZ(6); ++ CVMX_ES64(tmp1, ((64 + 16) << 3)); ++ CVMX_MT_HSH_STARTMD5(tmp1); ++ ++ /* save the HMAC */ ++ SG_INIT(sg, data, data_i, data_l); ++ while (icv_off > 0) { ++ SG_CONSUME(sg, data, data_i, data_l); ++ icv_off -= 8; ++ } ++ CVMX_MF_HSH_IV(*data, 0); ++ SG_CONSUME(sg, data, data_i, data_l); ++ CVMX_MF_HSH_IV(tmp1, 1); ++ *(uint32_t *)data = (uint32_t) (tmp1 >> 32); ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++/****************************************************************************/ ++/* SHA1 */ ++ ++int ++octo_null_sha1_encrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ register int next = 0; ++ uint64_t *data; ++ uint64_t tmp1, tmp2, tmp3; ++ int data_i, data_l, alen = auth_len; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ++ (auth_off & 0x7) || (auth_off + auth_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data, data_i, data_l); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* Load SHA1 IV */ ++ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); ++ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); ++ ++ while (auth_off > 0) { ++ SG_CONSUME(sg, data, data_i, data_l); ++ auth_off -= 8; ++ } ++ ++ while (auth_len > 0) { ++ CVM_LOAD_SHA_UNIT(*data, next); ++ auth_len -= 8; ++ SG_CONSUME(sg, data, data_i, data_l); ++ } ++ ++ /* finish the hash */ ++ CVMX_PREFETCH0(od->octo_hmouter); ++#if 0 ++ if (unlikely(inplen)) { ++ uint64_t tmp = 0; ++ uint8_t *p = (uint8_t *) & tmp; ++ p[inplen] = 0x80; ++ do { ++ inplen--; ++ p[inplen] = ((uint8_t *) data)[inplen]; ++ } while (inplen); ++ CVM_LOAD_MD5_UNIT(tmp, next); ++ } else { ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++ } ++#else ++ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); ++#endif ++ ++ /* Finish Inner hash */ ++ while (next != 7) { ++ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); ++ } ++ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); ++ ++ /* Get the inner hash of HMAC */ ++ CVMX_MF_HSH_IV(tmp1, 0); ++ CVMX_MF_HSH_IV(tmp2, 1); ++ tmp3 = 0; ++ CVMX_MF_HSH_IV(tmp3, 2); ++ ++ /* Initialize hash unit */ ++ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); ++ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); ++ ++ CVMX_MT_HSH_DAT(tmp1, 0); ++ CVMX_MT_HSH_DAT(tmp2, 1); ++ tmp3 |= 0x0000000080000000; ++ CVMX_MT_HSH_DAT(tmp3, 2); ++ CVMX_MT_HSH_DATZ(3); ++ CVMX_MT_HSH_DATZ(4); ++ CVMX_MT_HSH_DATZ(5); ++ CVMX_MT_HSH_DATZ(6); ++ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); ++ ++ /* save the HMAC */ ++ SG_INIT(sg, data, data_i, data_l); ++ while (icv_off > 0) { ++ SG_CONSUME(sg, data, data_i, data_l); ++ icv_off -= 8; ++ } ++ CVMX_MF_HSH_IV(*data, 0); ++ SG_CONSUME(sg, data, data_i, data_l); ++ CVMX_MF_HSH_IV(tmp1, 1); ++ *(uint32_t *)data = (uint32_t) (tmp1 >> 32); ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++/****************************************************************************/ ++/* DES MD5 */ ++ ++int ++octo_des_cbc_md5_encrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ register int next = 0; ++ union { ++ uint32_t data32[2]; ++ uint64_t data64[1]; ++ } mydata; ++ uint64_t *data = &mydata.data64[0]; ++ uint32_t *data32; ++ uint64_t tmp1, tmp2; ++ int data_i, data_l, alen = auth_len; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || ++ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || ++ (crypt_len & 0x7) || ++ (auth_len & 0x7) || ++ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data32, data_i, data_l); ++ ++ CVMX_PREFETCH0(ivp); ++ CVMX_PREFETCH0(od->octo_enckey); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* load 3DES Key */ ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); ++ if (od->octo_encklen == 24) { ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ } else if (od->octo_encklen == 8) { ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); ++ } else { ++ octeon_crypto_disable(&state, flags); ++ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); ++ return -EINVAL; ++ } ++ ++ CVMX_MT_3DES_IV(* (uint64_t *) ivp); ++ ++ /* Load MD5 IV */ ++ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); ++ ++ while (crypt_off > 0 && auth_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ crypt_off -= 4; ++ auth_off -= 4; ++ } ++ ++ while (crypt_len > 0 || auth_len > 0) { ++ uint32_t *first = data32; ++ mydata.data32[0] = *first; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata.data32[1] = *data32; ++ if (crypt_off <= 0) { ++ if (crypt_len > 0) { ++ CVMX_MT_3DES_ENC_CBC(*data); ++ CVMX_MF_3DES_RESULT(*data); ++ crypt_len -= 8; ++ } ++ } else ++ crypt_off -= 8; ++ if (auth_off <= 0) { ++ if (auth_len > 0) { ++ CVM_LOAD_MD5_UNIT(*data, next); ++ auth_len -= 8; ++ } ++ } else ++ auth_off -= 8; ++ *first = mydata.data32[0]; ++ *data32 = mydata.data32[1]; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ } ++ ++ /* finish the hash */ ++ CVMX_PREFETCH0(od->octo_hmouter); ++#if 0 ++ if (unlikely(inplen)) { ++ uint64_t tmp = 0; ++ uint8_t *p = (uint8_t *) & tmp; ++ p[inplen] = 0x80; ++ do { ++ inplen--; ++ p[inplen] = ((uint8_t *) data)[inplen]; ++ } while (inplen); ++ CVM_LOAD_MD5_UNIT(tmp, next); ++ } else { ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++ } ++#else ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++#endif ++ ++ /* Finish Inner hash */ ++ while (next != 7) { ++ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); ++ } ++ CVMX_ES64(tmp1, ((alen + 64) << 3)); ++ CVM_LOAD_MD5_UNIT(tmp1, next); ++ ++ /* Get the inner hash of HMAC */ ++ CVMX_MF_HSH_IV(tmp1, 0); ++ CVMX_MF_HSH_IV(tmp2, 1); ++ ++ /* Initialize hash unit */ ++ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); ++ ++ CVMX_MT_HSH_DAT(tmp1, 0); ++ CVMX_MT_HSH_DAT(tmp2, 1); ++ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); ++ CVMX_MT_HSH_DATZ(3); ++ CVMX_MT_HSH_DATZ(4); ++ CVMX_MT_HSH_DATZ(5); ++ CVMX_MT_HSH_DATZ(6); ++ CVMX_ES64(tmp1, ((64 + 16) << 3)); ++ CVMX_MT_HSH_STARTMD5(tmp1); ++ ++ /* save the HMAC */ ++ SG_INIT(sg, data32, data_i, data_l); ++ while (icv_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ icv_off -= 4; ++ } ++ CVMX_MF_HSH_IV(tmp1, 0); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ SG_CONSUME(sg, data32, data_i, data_l); ++ *data32 = (uint32_t) tmp1; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVMX_MF_HSH_IV(tmp1, 1); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++int ++octo_des_cbc_md5_decrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ register int next = 0; ++ union { ++ uint32_t data32[2]; ++ uint64_t data64[1]; ++ } mydata; ++ uint64_t *data = &mydata.data64[0]; ++ uint32_t *data32; ++ uint64_t tmp1, tmp2; ++ int data_i, data_l, alen = auth_len; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || ++ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || ++ (crypt_len & 0x7) || ++ (auth_len & 0x7) || ++ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data32, data_i, data_l); ++ ++ CVMX_PREFETCH0(ivp); ++ CVMX_PREFETCH0(od->octo_enckey); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* load 3DES Key */ ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); ++ if (od->octo_encklen == 24) { ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ } else if (od->octo_encklen == 8) { ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); ++ } else { ++ octeon_crypto_disable(&state, flags); ++ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); ++ return -EINVAL; ++ } ++ ++ CVMX_MT_3DES_IV(* (uint64_t *) ivp); ++ ++ /* Load MD5 IV */ ++ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); ++ ++ while (crypt_off > 0 && auth_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ crypt_off -= 4; ++ auth_off -= 4; ++ } ++ ++ while (crypt_len > 0 || auth_len > 0) { ++ uint32_t *first = data32; ++ mydata.data32[0] = *first; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata.data32[1] = *data32; ++ if (auth_off <= 0) { ++ if (auth_len > 0) { ++ CVM_LOAD_MD5_UNIT(*data, next); ++ auth_len -= 8; ++ } ++ } else ++ auth_off -= 8; ++ if (crypt_off <= 0) { ++ if (crypt_len > 0) { ++ CVMX_MT_3DES_DEC_CBC(*data); ++ CVMX_MF_3DES_RESULT(*data); ++ crypt_len -= 8; ++ } ++ } else ++ crypt_off -= 8; ++ *first = mydata.data32[0]; ++ *data32 = mydata.data32[1]; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ } ++ ++ /* finish the hash */ ++ CVMX_PREFETCH0(od->octo_hmouter); ++#if 0 ++ if (unlikely(inplen)) { ++ uint64_t tmp = 0; ++ uint8_t *p = (uint8_t *) & tmp; ++ p[inplen] = 0x80; ++ do { ++ inplen--; ++ p[inplen] = ((uint8_t *) data)[inplen]; ++ } while (inplen); ++ CVM_LOAD_MD5_UNIT(tmp, next); ++ } else { ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++ } ++#else ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++#endif ++ ++ /* Finish Inner hash */ ++ while (next != 7) { ++ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); ++ } ++ CVMX_ES64(tmp1, ((alen + 64) << 3)); ++ CVM_LOAD_MD5_UNIT(tmp1, next); ++ ++ /* Get the inner hash of HMAC */ ++ CVMX_MF_HSH_IV(tmp1, 0); ++ CVMX_MF_HSH_IV(tmp2, 1); ++ ++ /* Initialize hash unit */ ++ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); ++ ++ CVMX_MT_HSH_DAT(tmp1, 0); ++ CVMX_MT_HSH_DAT(tmp2, 1); ++ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); ++ CVMX_MT_HSH_DATZ(3); ++ CVMX_MT_HSH_DATZ(4); ++ CVMX_MT_HSH_DATZ(5); ++ CVMX_MT_HSH_DATZ(6); ++ CVMX_ES64(tmp1, ((64 + 16) << 3)); ++ CVMX_MT_HSH_STARTMD5(tmp1); ++ ++ /* save the HMAC */ ++ SG_INIT(sg, data32, data_i, data_l); ++ while (icv_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ icv_off -= 4; ++ } ++ CVMX_MF_HSH_IV(tmp1, 0); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ SG_CONSUME(sg, data32, data_i, data_l); ++ *data32 = (uint32_t) tmp1; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVMX_MF_HSH_IV(tmp1, 1); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++/****************************************************************************/ ++/* DES SHA */ ++ ++int ++octo_des_cbc_sha1_encrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ register int next = 0; ++ union { ++ uint32_t data32[2]; ++ uint64_t data64[1]; ++ } mydata; ++ uint64_t *data = &mydata.data64[0]; ++ uint32_t *data32; ++ uint64_t tmp1, tmp2, tmp3; ++ int data_i, data_l, alen = auth_len; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || ++ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || ++ (crypt_len & 0x7) || ++ (auth_len & 0x7) || ++ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data32, data_i, data_l); ++ ++ CVMX_PREFETCH0(ivp); ++ CVMX_PREFETCH0(od->octo_enckey); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* load 3DES Key */ ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); ++ if (od->octo_encklen == 24) { ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ } else if (od->octo_encklen == 8) { ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); ++ } else { ++ octeon_crypto_disable(&state, flags); ++ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); ++ return -EINVAL; ++ } ++ ++ CVMX_MT_3DES_IV(* (uint64_t *) ivp); ++ ++ /* Load SHA1 IV */ ++ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); ++ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); ++ ++ while (crypt_off > 0 && auth_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ crypt_off -= 4; ++ auth_off -= 4; ++ } ++ ++ while (crypt_len > 0 || auth_len > 0) { ++ uint32_t *first = data32; ++ mydata.data32[0] = *first; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata.data32[1] = *data32; ++ if (crypt_off <= 0) { ++ if (crypt_len > 0) { ++ CVMX_MT_3DES_ENC_CBC(*data); ++ CVMX_MF_3DES_RESULT(*data); ++ crypt_len -= 8; ++ } ++ } else ++ crypt_off -= 8; ++ if (auth_off <= 0) { ++ if (auth_len > 0) { ++ CVM_LOAD_SHA_UNIT(*data, next); ++ auth_len -= 8; ++ } ++ } else ++ auth_off -= 8; ++ *first = mydata.data32[0]; ++ *data32 = mydata.data32[1]; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ } ++ ++ /* finish the hash */ ++ CVMX_PREFETCH0(od->octo_hmouter); ++#if 0 ++ if (unlikely(inplen)) { ++ uint64_t tmp = 0; ++ uint8_t *p = (uint8_t *) & tmp; ++ p[inplen] = 0x80; ++ do { ++ inplen--; ++ p[inplen] = ((uint8_t *) data)[inplen]; ++ } while (inplen); ++ CVM_LOAD_SHA_UNIT(tmp, next); ++ } else { ++ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); ++ } ++#else ++ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); ++#endif ++ ++ /* Finish Inner hash */ ++ while (next != 7) { ++ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); ++ } ++ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); ++ ++ /* Get the inner hash of HMAC */ ++ CVMX_MF_HSH_IV(tmp1, 0); ++ CVMX_MF_HSH_IV(tmp2, 1); ++ tmp3 = 0; ++ CVMX_MF_HSH_IV(tmp3, 2); ++ ++ /* Initialize hash unit */ ++ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); ++ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); ++ ++ CVMX_MT_HSH_DAT(tmp1, 0); ++ CVMX_MT_HSH_DAT(tmp2, 1); ++ tmp3 |= 0x0000000080000000; ++ CVMX_MT_HSH_DAT(tmp3, 2); ++ CVMX_MT_HSH_DATZ(3); ++ CVMX_MT_HSH_DATZ(4); ++ CVMX_MT_HSH_DATZ(5); ++ CVMX_MT_HSH_DATZ(6); ++ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); ++ ++ /* save the HMAC */ ++ SG_INIT(sg, data32, data_i, data_l); ++ while (icv_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ icv_off -= 4; ++ } ++ CVMX_MF_HSH_IV(tmp1, 0); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ SG_CONSUME(sg, data32, data_i, data_l); ++ *data32 = (uint32_t) tmp1; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVMX_MF_HSH_IV(tmp1, 1); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++int ++octo_des_cbc_sha1_decrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ register int next = 0; ++ union { ++ uint32_t data32[2]; ++ uint64_t data64[1]; ++ } mydata; ++ uint64_t *data = &mydata.data64[0]; ++ uint32_t *data32; ++ uint64_t tmp1, tmp2, tmp3; ++ int data_i, data_l, alen = auth_len; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || ++ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || ++ (crypt_len & 0x7) || ++ (auth_len & 0x7) || ++ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data32, data_i, data_l); ++ ++ CVMX_PREFETCH0(ivp); ++ CVMX_PREFETCH0(od->octo_enckey); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* load 3DES Key */ ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); ++ if (od->octo_encklen == 24) { ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ } else if (od->octo_encklen == 8) { ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); ++ } else { ++ octeon_crypto_disable(&state, flags); ++ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); ++ return -EINVAL; ++ } ++ ++ CVMX_MT_3DES_IV(* (uint64_t *) ivp); ++ ++ /* Load SHA1 IV */ ++ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); ++ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); ++ ++ while (crypt_off > 0 && auth_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ crypt_off -= 4; ++ auth_off -= 4; ++ } ++ ++ while (crypt_len > 0 || auth_len > 0) { ++ uint32_t *first = data32; ++ mydata.data32[0] = *first; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata.data32[1] = *data32; ++ if (auth_off <= 0) { ++ if (auth_len > 0) { ++ CVM_LOAD_SHA_UNIT(*data, next); ++ auth_len -= 8; ++ } ++ } else ++ auth_off -= 8; ++ if (crypt_off <= 0) { ++ if (crypt_len > 0) { ++ CVMX_MT_3DES_DEC_CBC(*data); ++ CVMX_MF_3DES_RESULT(*data); ++ crypt_len -= 8; ++ } ++ } else ++ crypt_off -= 8; ++ *first = mydata.data32[0]; ++ *data32 = mydata.data32[1]; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ } ++ ++ /* finish the hash */ ++ CVMX_PREFETCH0(od->octo_hmouter); ++#if 0 ++ if (unlikely(inplen)) { ++ uint64_t tmp = 0; ++ uint8_t *p = (uint8_t *) & tmp; ++ p[inplen] = 0x80; ++ do { ++ inplen--; ++ p[inplen] = ((uint8_t *) data)[inplen]; ++ } while (inplen); ++ CVM_LOAD_SHA_UNIT(tmp, next); ++ } else { ++ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); ++ } ++#else ++ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); ++#endif ++ ++ /* Finish Inner hash */ ++ while (next != 7) { ++ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); ++ } ++ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); ++ ++ /* Get the inner hash of HMAC */ ++ CVMX_MF_HSH_IV(tmp1, 0); ++ CVMX_MF_HSH_IV(tmp2, 1); ++ tmp3 = 0; ++ CVMX_MF_HSH_IV(tmp3, 2); ++ ++ /* Initialize hash unit */ ++ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); ++ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); ++ ++ CVMX_MT_HSH_DAT(tmp1, 0); ++ CVMX_MT_HSH_DAT(tmp2, 1); ++ tmp3 |= 0x0000000080000000; ++ CVMX_MT_HSH_DAT(tmp3, 2); ++ CVMX_MT_HSH_DATZ(3); ++ CVMX_MT_HSH_DATZ(4); ++ CVMX_MT_HSH_DATZ(5); ++ CVMX_MT_HSH_DATZ(6); ++ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); ++ /* save the HMAC */ ++ SG_INIT(sg, data32, data_i, data_l); ++ while (icv_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ icv_off -= 4; ++ } ++ CVMX_MF_HSH_IV(tmp1, 0); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ SG_CONSUME(sg, data32, data_i, data_l); ++ *data32 = (uint32_t) tmp1; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVMX_MF_HSH_IV(tmp1, 1); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++/****************************************************************************/ ++/* AES MD5 */ ++ ++int ++octo_aes_cbc_md5_encrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ register int next = 0; ++ union { ++ uint32_t data32[2]; ++ uint64_t data64[1]; ++ } mydata[2]; ++ uint64_t *pdata = &mydata[0].data64[0]; ++ uint64_t *data = &mydata[1].data64[0]; ++ uint32_t *data32; ++ uint64_t tmp1, tmp2; ++ int data_i, data_l, alen = auth_len; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || ++ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || ++ (crypt_len & 0x7) || ++ (auth_len & 0x7) || ++ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data32, data_i, data_l); ++ ++ CVMX_PREFETCH0(ivp); ++ CVMX_PREFETCH0(od->octo_enckey); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* load AES Key */ ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); ++ ++ if (od->octo_encklen == 16) { ++ CVMX_MT_AES_KEY(0x0, 2); ++ CVMX_MT_AES_KEY(0x0, 3); ++ } else if (od->octo_encklen == 24) { ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ CVMX_MT_AES_KEY(0x0, 3); ++ } else if (od->octo_encklen == 32) { ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); ++ } else { ++ octeon_crypto_disable(&state, flags); ++ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); ++ return -EINVAL; ++ } ++ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); ++ ++ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); ++ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); ++ ++ /* Load MD5 IV */ ++ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); ++ ++ while (crypt_off > 0 && auth_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ crypt_off -= 4; ++ auth_off -= 4; ++ } ++ ++ /* align auth and crypt */ ++ while (crypt_off > 0 && auth_len > 0) { ++ mydata[0].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata[0].data32[1] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVM_LOAD_MD5_UNIT(*pdata, next); ++ crypt_off -= 8; ++ auth_len -= 8; ++ } ++ ++ while (crypt_len > 0) { ++ uint32_t *pdata32[3]; ++ ++ pdata32[0] = data32; ++ mydata[0].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ ++ pdata32[1] = data32; ++ mydata[0].data32[1] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ ++ pdata32[2] = data32; ++ mydata[1].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ ++ mydata[1].data32[1] = *data32; ++ ++ CVMX_MT_AES_ENC_CBC0(*pdata); ++ CVMX_MT_AES_ENC_CBC1(*data); ++ CVMX_MF_AES_RESULT(*pdata, 0); ++ CVMX_MF_AES_RESULT(*data, 1); ++ crypt_len -= 16; ++ ++ if (auth_len > 0) { ++ CVM_LOAD_MD5_UNIT(*pdata, next); ++ auth_len -= 8; ++ } ++ if (auth_len > 0) { ++ CVM_LOAD_MD5_UNIT(*data, next); ++ auth_len -= 8; ++ } ++ ++ *pdata32[0] = mydata[0].data32[0]; ++ *pdata32[1] = mydata[0].data32[1]; ++ *pdata32[2] = mydata[1].data32[0]; ++ *data32 = mydata[1].data32[1]; ++ ++ SG_CONSUME(sg, data32, data_i, data_l); ++ } ++ ++ /* finish any left over hashing */ ++ while (auth_len > 0) { ++ mydata[0].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata[0].data32[1] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVM_LOAD_MD5_UNIT(*pdata, next); ++ auth_len -= 8; ++ } ++ ++ /* finish the hash */ ++ CVMX_PREFETCH0(od->octo_hmouter); ++#if 0 ++ if (unlikely(inplen)) { ++ uint64_t tmp = 0; ++ uint8_t *p = (uint8_t *) & tmp; ++ p[inplen] = 0x80; ++ do { ++ inplen--; ++ p[inplen] = ((uint8_t *) data)[inplen]; ++ } while (inplen); ++ CVM_LOAD_MD5_UNIT(tmp, next); ++ } else { ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++ } ++#else ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++#endif ++ ++ /* Finish Inner hash */ ++ while (next != 7) { ++ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); ++ } ++ CVMX_ES64(tmp1, ((alen + 64) << 3)); ++ CVM_LOAD_MD5_UNIT(tmp1, next); ++ ++ /* Get the inner hash of HMAC */ ++ CVMX_MF_HSH_IV(tmp1, 0); ++ CVMX_MF_HSH_IV(tmp2, 1); ++ ++ /* Initialize hash unit */ ++ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); ++ ++ CVMX_MT_HSH_DAT(tmp1, 0); ++ CVMX_MT_HSH_DAT(tmp2, 1); ++ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); ++ CVMX_MT_HSH_DATZ(3); ++ CVMX_MT_HSH_DATZ(4); ++ CVMX_MT_HSH_DATZ(5); ++ CVMX_MT_HSH_DATZ(6); ++ CVMX_ES64(tmp1, ((64 + 16) << 3)); ++ CVMX_MT_HSH_STARTMD5(tmp1); ++ ++ /* save the HMAC */ ++ SG_INIT(sg, data32, data_i, data_l); ++ while (icv_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ icv_off -= 4; ++ } ++ CVMX_MF_HSH_IV(tmp1, 0); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ SG_CONSUME(sg, data32, data_i, data_l); ++ *data32 = (uint32_t) tmp1; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVMX_MF_HSH_IV(tmp1, 1); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++int ++octo_aes_cbc_md5_decrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ register int next = 0; ++ union { ++ uint32_t data32[2]; ++ uint64_t data64[1]; ++ } mydata[2]; ++ uint64_t *pdata = &mydata[0].data64[0]; ++ uint64_t *data = &mydata[1].data64[0]; ++ uint32_t *data32; ++ uint64_t tmp1, tmp2; ++ int data_i, data_l, alen = auth_len; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || ++ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || ++ (crypt_len & 0x7) || ++ (auth_len & 0x7) || ++ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data32, data_i, data_l); ++ ++ CVMX_PREFETCH0(ivp); ++ CVMX_PREFETCH0(od->octo_enckey); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* load AES Key */ ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); ++ ++ if (od->octo_encklen == 16) { ++ CVMX_MT_AES_KEY(0x0, 2); ++ CVMX_MT_AES_KEY(0x0, 3); ++ } else if (od->octo_encklen == 24) { ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ CVMX_MT_AES_KEY(0x0, 3); ++ } else if (od->octo_encklen == 32) { ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); ++ } else { ++ octeon_crypto_disable(&state, flags); ++ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); ++ return -EINVAL; ++ } ++ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); ++ ++ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); ++ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); ++ ++ /* Load MD5 IV */ ++ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); ++ ++ while (crypt_off > 0 && auth_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ crypt_off -= 4; ++ auth_off -= 4; ++ } ++ ++ /* align auth and crypt */ ++ while (crypt_off > 0 && auth_len > 0) { ++ mydata[0].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata[0].data32[1] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVM_LOAD_MD5_UNIT(*pdata, next); ++ crypt_off -= 8; ++ auth_len -= 8; ++ } ++ ++ while (crypt_len > 0) { ++ uint32_t *pdata32[3]; ++ ++ pdata32[0] = data32; ++ mydata[0].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ pdata32[1] = data32; ++ mydata[0].data32[1] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ pdata32[2] = data32; ++ mydata[1].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata[1].data32[1] = *data32; ++ ++ if (auth_len > 0) { ++ CVM_LOAD_MD5_UNIT(*pdata, next); ++ auth_len -= 8; ++ } ++ ++ if (auth_len > 0) { ++ CVM_LOAD_MD5_UNIT(*data, next); ++ auth_len -= 8; ++ } ++ ++ CVMX_MT_AES_DEC_CBC0(*pdata); ++ CVMX_MT_AES_DEC_CBC1(*data); ++ CVMX_MF_AES_RESULT(*pdata, 0); ++ CVMX_MF_AES_RESULT(*data, 1); ++ crypt_len -= 16; ++ ++ *pdata32[0] = mydata[0].data32[0]; ++ *pdata32[1] = mydata[0].data32[1]; ++ *pdata32[2] = mydata[1].data32[0]; ++ *data32 = mydata[1].data32[1]; ++ ++ SG_CONSUME(sg, data32, data_i, data_l); ++ } ++ ++ /* finish left over hash if any */ ++ while (auth_len > 0) { ++ mydata[0].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata[0].data32[1] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVM_LOAD_MD5_UNIT(*pdata, next); ++ auth_len -= 8; ++ } ++ ++ ++ /* finish the hash */ ++ CVMX_PREFETCH0(od->octo_hmouter); ++#if 0 ++ if (unlikely(inplen)) { ++ uint64_t tmp = 0; ++ uint8_t *p = (uint8_t *) & tmp; ++ p[inplen] = 0x80; ++ do { ++ inplen--; ++ p[inplen] = ((uint8_t *) data)[inplen]; ++ } while (inplen); ++ CVM_LOAD_MD5_UNIT(tmp, next); ++ } else { ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++ } ++#else ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++#endif ++ ++ /* Finish Inner hash */ ++ while (next != 7) { ++ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); ++ } ++ CVMX_ES64(tmp1, ((alen + 64) << 3)); ++ CVM_LOAD_MD5_UNIT(tmp1, next); ++ ++ /* Get the inner hash of HMAC */ ++ CVMX_MF_HSH_IV(tmp1, 0); ++ CVMX_MF_HSH_IV(tmp2, 1); ++ ++ /* Initialize hash unit */ ++ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); ++ ++ CVMX_MT_HSH_DAT(tmp1, 0); ++ CVMX_MT_HSH_DAT(tmp2, 1); ++ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); ++ CVMX_MT_HSH_DATZ(3); ++ CVMX_MT_HSH_DATZ(4); ++ CVMX_MT_HSH_DATZ(5); ++ CVMX_MT_HSH_DATZ(6); ++ CVMX_ES64(tmp1, ((64 + 16) << 3)); ++ CVMX_MT_HSH_STARTMD5(tmp1); ++ ++ /* save the HMAC */ ++ SG_INIT(sg, data32, data_i, data_l); ++ while (icv_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ icv_off -= 4; ++ } ++ CVMX_MF_HSH_IV(tmp1, 0); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ SG_CONSUME(sg, data32, data_i, data_l); ++ *data32 = (uint32_t) tmp1; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVMX_MF_HSH_IV(tmp1, 1); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++/****************************************************************************/ ++/* AES SHA1 */ ++ ++int ++octo_aes_cbc_sha1_encrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ register int next = 0; ++ union { ++ uint32_t data32[2]; ++ uint64_t data64[1]; ++ } mydata[2]; ++ uint64_t *pdata = &mydata[0].data64[0]; ++ uint64_t *data = &mydata[1].data64[0]; ++ uint32_t *data32; ++ uint64_t tmp1, tmp2, tmp3; ++ int data_i, data_l, alen = auth_len; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s(a_off=%d a_len=%d c_off=%d c_len=%d icv_off=%d)\n", ++ __FUNCTION__, auth_off, auth_len, crypt_off, crypt_len, icv_off); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || ++ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || ++ (crypt_len & 0x7) || ++ (auth_len & 0x7) || ++ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data32, data_i, data_l); ++ ++ CVMX_PREFETCH0(ivp); ++ CVMX_PREFETCH0(od->octo_enckey); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* load AES Key */ ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); ++ ++ if (od->octo_encklen == 16) { ++ CVMX_MT_AES_KEY(0x0, 2); ++ CVMX_MT_AES_KEY(0x0, 3); ++ } else if (od->octo_encklen == 24) { ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ CVMX_MT_AES_KEY(0x0, 3); ++ } else if (od->octo_encklen == 32) { ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); ++ } else { ++ octeon_crypto_disable(&state, flags); ++ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); ++ return -EINVAL; ++ } ++ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); ++ ++ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); ++ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); ++ ++ /* Load SHA IV */ ++ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); ++ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); ++ ++ while (crypt_off > 0 && auth_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ crypt_off -= 4; ++ auth_off -= 4; ++ } ++ ++ /* align auth and crypt */ ++ while (crypt_off > 0 && auth_len > 0) { ++ mydata[0].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata[0].data32[1] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVM_LOAD_SHA_UNIT(*pdata, next); ++ crypt_off -= 8; ++ auth_len -= 8; ++ } ++ ++ while (crypt_len > 0) { ++ uint32_t *pdata32[3]; ++ ++ pdata32[0] = data32; ++ mydata[0].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ pdata32[1] = data32; ++ mydata[0].data32[1] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ pdata32[2] = data32; ++ mydata[1].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata[1].data32[1] = *data32; ++ ++ CVMX_MT_AES_ENC_CBC0(*pdata); ++ CVMX_MT_AES_ENC_CBC1(*data); ++ CVMX_MF_AES_RESULT(*pdata, 0); ++ CVMX_MF_AES_RESULT(*data, 1); ++ crypt_len -= 16; ++ ++ if (auth_len > 0) { ++ CVM_LOAD_SHA_UNIT(*pdata, next); ++ auth_len -= 8; ++ } ++ if (auth_len > 0) { ++ CVM_LOAD_SHA_UNIT(*data, next); ++ auth_len -= 8; ++ } ++ ++ *pdata32[0] = mydata[0].data32[0]; ++ *pdata32[1] = mydata[0].data32[1]; ++ *pdata32[2] = mydata[1].data32[0]; ++ *data32 = mydata[1].data32[1]; ++ ++ SG_CONSUME(sg, data32, data_i, data_l); ++ } ++ ++ /* finish and hashing */ ++ while (auth_len > 0) { ++ mydata[0].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata[0].data32[1] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVM_LOAD_SHA_UNIT(*pdata, next); ++ auth_len -= 8; ++ } ++ ++ /* finish the hash */ ++ CVMX_PREFETCH0(od->octo_hmouter); ++#if 0 ++ if (unlikely(inplen)) { ++ uint64_t tmp = 0; ++ uint8_t *p = (uint8_t *) & tmp; ++ p[inplen] = 0x80; ++ do { ++ inplen--; ++ p[inplen] = ((uint8_t *) data)[inplen]; ++ } while (inplen); ++ CVM_LOAD_SHA_UNIT(tmp, next); ++ } else { ++ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); ++ } ++#else ++ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); ++#endif ++ ++ /* Finish Inner hash */ ++ while (next != 7) { ++ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); ++ } ++ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); ++ ++ /* Get the inner hash of HMAC */ ++ CVMX_MF_HSH_IV(tmp1, 0); ++ CVMX_MF_HSH_IV(tmp2, 1); ++ tmp3 = 0; ++ CVMX_MF_HSH_IV(tmp3, 2); ++ ++ /* Initialize hash unit */ ++ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); ++ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); ++ ++ CVMX_MT_HSH_DAT(tmp1, 0); ++ CVMX_MT_HSH_DAT(tmp2, 1); ++ tmp3 |= 0x0000000080000000; ++ CVMX_MT_HSH_DAT(tmp3, 2); ++ CVMX_MT_HSH_DATZ(3); ++ CVMX_MT_HSH_DATZ(4); ++ CVMX_MT_HSH_DATZ(5); ++ CVMX_MT_HSH_DATZ(6); ++ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); ++ ++ /* finish the hash */ ++ CVMX_PREFETCH0(od->octo_hmouter); ++#if 0 ++ if (unlikely(inplen)) { ++ uint64_t tmp = 0; ++ uint8_t *p = (uint8_t *) & tmp; ++ p[inplen] = 0x80; ++ do { ++ inplen--; ++ p[inplen] = ((uint8_t *) data)[inplen]; ++ } while (inplen); ++ CVM_LOAD_MD5_UNIT(tmp, next); ++ } else { ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++ } ++#else ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++#endif ++ ++ /* save the HMAC */ ++ SG_INIT(sg, data32, data_i, data_l); ++ while (icv_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ icv_off -= 4; ++ } ++ CVMX_MF_HSH_IV(tmp1, 0); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ SG_CONSUME(sg, data32, data_i, data_l); ++ *data32 = (uint32_t) tmp1; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVMX_MF_HSH_IV(tmp1, 1); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++int ++octo_aes_cbc_sha1_decrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ register int next = 0; ++ union { ++ uint32_t data32[2]; ++ uint64_t data64[1]; ++ } mydata[2]; ++ uint64_t *pdata = &mydata[0].data64[0]; ++ uint64_t *data = &mydata[1].data64[0]; ++ uint32_t *data32; ++ uint64_t tmp1, tmp2, tmp3; ++ int data_i, data_l, alen = auth_len; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s(a_off=%d a_len=%d c_off=%d c_len=%d icv_off=%d)\n", ++ __FUNCTION__, auth_off, auth_len, crypt_off, crypt_len, icv_off); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || ++ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || ++ (crypt_len & 0x7) || ++ (auth_len & 0x7) || ++ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data32, data_i, data_l); ++ ++ CVMX_PREFETCH0(ivp); ++ CVMX_PREFETCH0(od->octo_enckey); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* load AES Key */ ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); ++ ++ if (od->octo_encklen == 16) { ++ CVMX_MT_AES_KEY(0x0, 2); ++ CVMX_MT_AES_KEY(0x0, 3); ++ } else if (od->octo_encklen == 24) { ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ CVMX_MT_AES_KEY(0x0, 3); ++ } else if (od->octo_encklen == 32) { ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); ++ } else { ++ octeon_crypto_disable(&state, flags); ++ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); ++ return -EINVAL; ++ } ++ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); ++ ++ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); ++ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); ++ ++ /* Load SHA1 IV */ ++ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); ++ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); ++ ++ while (crypt_off > 0 && auth_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ crypt_off -= 4; ++ auth_off -= 4; ++ } ++ ++ /* align auth and crypt */ ++ while (crypt_off > 0 && auth_len > 0) { ++ mydata[0].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata[0].data32[1] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVM_LOAD_SHA_UNIT(*pdata, next); ++ crypt_off -= 8; ++ auth_len -= 8; ++ } ++ ++ while (crypt_len > 0) { ++ uint32_t *pdata32[3]; ++ ++ pdata32[0] = data32; ++ mydata[0].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ pdata32[1] = data32; ++ mydata[0].data32[1] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ pdata32[2] = data32; ++ mydata[1].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata[1].data32[1] = *data32; ++ ++ if (auth_len > 0) { ++ CVM_LOAD_SHA_UNIT(*pdata, next); ++ auth_len -= 8; ++ } ++ if (auth_len > 0) { ++ CVM_LOAD_SHA_UNIT(*data, next); ++ auth_len -= 8; ++ } ++ ++ CVMX_MT_AES_DEC_CBC0(*pdata); ++ CVMX_MT_AES_DEC_CBC1(*data); ++ CVMX_MF_AES_RESULT(*pdata, 0); ++ CVMX_MF_AES_RESULT(*data, 1); ++ crypt_len -= 16; ++ ++ *pdata32[0] = mydata[0].data32[0]; ++ *pdata32[1] = mydata[0].data32[1]; ++ *pdata32[2] = mydata[1].data32[0]; ++ *data32 = mydata[1].data32[1]; ++ ++ SG_CONSUME(sg, data32, data_i, data_l); ++ } ++ ++ /* finish and leftover hashing */ ++ while (auth_len > 0) { ++ mydata[0].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata[0].data32[1] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVM_LOAD_SHA_UNIT(*pdata, next); ++ auth_len -= 8; ++ } ++ ++ /* finish the hash */ ++ CVMX_PREFETCH0(od->octo_hmouter); ++#if 0 ++ if (unlikely(inplen)) { ++ uint64_t tmp = 0; ++ uint8_t *p = (uint8_t *) & tmp; ++ p[inplen] = 0x80; ++ do { ++ inplen--; ++ p[inplen] = ((uint8_t *) data)[inplen]; ++ } while (inplen); ++ CVM_LOAD_SHA_UNIT(tmp, next); ++ } else { ++ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); ++ } ++#else ++ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); ++#endif ++ ++ /* Finish Inner hash */ ++ while (next != 7) { ++ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); ++ } ++ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); ++ ++ /* Get the inner hash of HMAC */ ++ CVMX_MF_HSH_IV(tmp1, 0); ++ CVMX_MF_HSH_IV(tmp2, 1); ++ tmp3 = 0; ++ CVMX_MF_HSH_IV(tmp3, 2); ++ ++ /* Initialize hash unit */ ++ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); ++ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); ++ ++ CVMX_MT_HSH_DAT(tmp1, 0); ++ CVMX_MT_HSH_DAT(tmp2, 1); ++ tmp3 |= 0x0000000080000000; ++ CVMX_MT_HSH_DAT(tmp3, 2); ++ CVMX_MT_HSH_DATZ(3); ++ CVMX_MT_HSH_DATZ(4); ++ CVMX_MT_HSH_DATZ(5); ++ CVMX_MT_HSH_DATZ(6); ++ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); ++ ++ /* finish the hash */ ++ CVMX_PREFETCH0(od->octo_hmouter); ++#if 0 ++ if (unlikely(inplen)) { ++ uint64_t tmp = 0; ++ uint8_t *p = (uint8_t *) & tmp; ++ p[inplen] = 0x80; ++ do { ++ inplen--; ++ p[inplen] = ((uint8_t *) data)[inplen]; ++ } while (inplen); ++ CVM_LOAD_MD5_UNIT(tmp, next); ++ } else { ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++ } ++#else ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++#endif ++ ++ /* save the HMAC */ ++ SG_INIT(sg, data32, data_i, data_l); ++ while (icv_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ icv_off -= 4; ++ } ++ CVMX_MF_HSH_IV(tmp1, 0); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ SG_CONSUME(sg, data32, data_i, data_l); ++ *data32 = (uint32_t) tmp1; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVMX_MF_HSH_IV(tmp1, 1); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++/****************************************************************************/ +diff -Nur linux-3.0.4.orig/crypto/ocf/cryptocteon/cryptocteon.c linux-3.0.4/crypto/ocf/cryptocteon/cryptocteon.c +--- linux-3.0.4.orig/crypto/ocf/cryptocteon/cryptocteon.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/cryptocteon/cryptocteon.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,575 @@ ++/* ++ * Octeon Crypto for OCF ++ * ++ * Written by David McCullough ++ * Copyright (C) 2009-2010 David McCullough ++ * ++ * LICENSE TERMS ++ * ++ * The free distribution and use of this software in both source and binary ++ * form is allowed (with or without changes) provided that: ++ * ++ * 1. distributions of this source code include the above copyright ++ * notice, this list of conditions and the following disclaimer; ++ * ++ * 2. distributions in binary form include the above copyright ++ * notice, this list of conditions and the following disclaimer ++ * in the documentation and/or other associated materials; ++ * ++ * 3. the copyright holder's name is not used to endorse products ++ * built using this software without specific written permission. ++ * ++ * DISCLAIMER ++ * ++ * This software is provided 'as is' with no explicit or implied warranties ++ * in respect of its properties, including, but not limited to, correctness ++ * and/or fitness for purpose. ++ * --------------------------------------------------------------------------- ++ */ ++ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++struct { ++ softc_device_decl sc_dev; ++} octo_softc; ++ ++#define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK) ++ ++struct octo_sess { ++ int octo_encalg; ++ #define MAX_CIPHER_KEYLEN 64 ++ char octo_enckey[MAX_CIPHER_KEYLEN]; ++ int octo_encklen; ++ ++ int octo_macalg; ++ #define MAX_HASH_KEYLEN 64 ++ char octo_mackey[MAX_HASH_KEYLEN]; ++ int octo_macklen; ++ int octo_mackey_set; ++ ++ int octo_mlen; ++ int octo_ivsize; ++ ++ int (*octo_encrypt)(struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp); ++ int (*octo_decrypt)(struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp); ++ ++ uint64_t octo_hminner[3]; ++ uint64_t octo_hmouter[3]; ++}; ++ ++int32_t octo_id = -1; ++module_param(octo_id, int, 0444); ++MODULE_PARM_DESC(octo_id, "Read-Only OCF ID for cryptocteon driver"); ++ ++static struct octo_sess **octo_sessions = NULL; ++static u_int32_t octo_sesnum = 0; ++ ++static int octo_process(device_t, struct cryptop *, int); ++static int octo_newsession(device_t, u_int32_t *, struct cryptoini *); ++static int octo_freesession(device_t, u_int64_t); ++ ++static device_method_t octo_methods = { ++ /* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, octo_newsession), ++ DEVMETHOD(cryptodev_freesession,octo_freesession), ++ DEVMETHOD(cryptodev_process, octo_process), ++}; ++ ++#define debug octo_debug ++int octo_debug = 0; ++module_param(octo_debug, int, 0644); ++MODULE_PARM_DESC(octo_debug, "Enable debug"); ++ ++ ++#include "cavium_crypto.c" ++ ++ ++/* ++ * Generate a new octo session. We artifically limit it to a single ++ * hash/cipher or hash-cipher combo just to make it easier, most callers ++ * do not expect more than this anyway. ++ */ ++static int ++octo_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) ++{ ++ struct cryptoini *c, *encini = NULL, *macini = NULL; ++ struct octo_sess **ocd; ++ int i; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (sid == NULL || cri == NULL) { ++ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ /* ++ * To keep it simple, we only handle hash, cipher or hash/cipher in a ++ * session, you cannot currently do multiple ciphers/hashes in one ++ * session even though it would be possibel to code this driver to ++ * handle it. ++ */ ++ for (i = 0, c = cri; c && i < 2; i++) { ++ if (c->cri_alg == CRYPTO_MD5_HMAC || ++ c->cri_alg == CRYPTO_SHA1_HMAC || ++ c->cri_alg == CRYPTO_NULL_HMAC) { ++ if (macini) { ++ break; ++ } ++ macini = c; ++ } ++ if (c->cri_alg == CRYPTO_DES_CBC || ++ c->cri_alg == CRYPTO_3DES_CBC || ++ c->cri_alg == CRYPTO_AES_CBC || ++ c->cri_alg == CRYPTO_NULL_CBC) { ++ if (encini) { ++ break; ++ } ++ encini = c; ++ } ++ c = c->cri_next; ++ } ++ if (!macini && !encini) { ++ dprintk("%s,%d - EINVAL bad cipher/hash or combination\n", ++ __FILE__, __LINE__); ++ return EINVAL; ++ } ++ if (c) { ++ dprintk("%s,%d - EINVAL cannot handle chained cipher/hash combos\n", ++ __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ /* ++ * So we have something we can do, lets setup the session ++ */ ++ ++ if (octo_sessions) { ++ for (i = 1; i < octo_sesnum; i++) ++ if (octo_sessions[i] == NULL) ++ break; ++ } else ++ i = 1; /* NB: to silence compiler warning */ ++ ++ if (octo_sessions == NULL || i == octo_sesnum) { ++ if (octo_sessions == NULL) { ++ i = 1; /* We leave octo_sessions[0] empty */ ++ octo_sesnum = CRYPTO_SW_SESSIONS; ++ } else ++ octo_sesnum *= 2; ++ ++ ocd = kmalloc(octo_sesnum * sizeof(struct octo_sess *), SLAB_ATOMIC); ++ if (ocd == NULL) { ++ /* Reset session number */ ++ if (octo_sesnum == CRYPTO_SW_SESSIONS) ++ octo_sesnum = 0; ++ else ++ octo_sesnum /= 2; ++ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ memset(ocd, 0, octo_sesnum * sizeof(struct octo_sess *)); ++ ++ /* Copy existing sessions */ ++ if (octo_sessions) { ++ memcpy(ocd, octo_sessions, ++ (octo_sesnum / 2) * sizeof(struct octo_sess *)); ++ kfree(octo_sessions); ++ } ++ ++ octo_sessions = ocd; ++ } ++ ++ ocd = &octo_sessions[i]; ++ *sid = i; ++ ++ ++ *ocd = (struct octo_sess *) kmalloc(sizeof(struct octo_sess), SLAB_ATOMIC); ++ if (*ocd == NULL) { ++ octo_freesession(NULL, i); ++ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ memset(*ocd, 0, sizeof(struct octo_sess)); ++ ++ if (encini && encini->cri_key) { ++ (*ocd)->octo_encklen = (encini->cri_klen + 7) / 8; ++ memcpy((*ocd)->octo_enckey, encini->cri_key, (*ocd)->octo_encklen); ++ } ++ ++ if (macini && macini->cri_key) { ++ (*ocd)->octo_macklen = (macini->cri_klen + 7) / 8; ++ memcpy((*ocd)->octo_mackey, macini->cri_key, (*ocd)->octo_macklen); ++ } ++ ++ (*ocd)->octo_mlen = 0; ++ if (encini && encini->cri_mlen) ++ (*ocd)->octo_mlen = encini->cri_mlen; ++ else if (macini && macini->cri_mlen) ++ (*ocd)->octo_mlen = macini->cri_mlen; ++ else ++ (*ocd)->octo_mlen = 12; ++ ++ /* ++ * point c at the enc if it exists, otherwise the mac ++ */ ++ c = encini ? encini : macini; ++ ++ switch (c->cri_alg) { ++ case CRYPTO_DES_CBC: ++ case CRYPTO_3DES_CBC: ++ (*ocd)->octo_ivsize = 8; ++ switch (macini ? macini->cri_alg : -1) { ++ case CRYPTO_MD5_HMAC: ++ (*ocd)->octo_encrypt = octo_des_cbc_md5_encrypt; ++ (*ocd)->octo_decrypt = octo_des_cbc_md5_decrypt; ++ octo_calc_hash(0, macini->cri_key, (*ocd)->octo_hminner, ++ (*ocd)->octo_hmouter); ++ break; ++ case CRYPTO_SHA1_HMAC: ++ (*ocd)->octo_encrypt = octo_des_cbc_sha1_encrypt; ++ (*ocd)->octo_decrypt = octo_des_cbc_sha1_decrypt; ++ octo_calc_hash(1, macini->cri_key, (*ocd)->octo_hminner, ++ (*ocd)->octo_hmouter); ++ break; ++ case -1: ++ (*ocd)->octo_encrypt = octo_des_cbc_encrypt; ++ (*ocd)->octo_decrypt = octo_des_cbc_decrypt; ++ break; ++ default: ++ octo_freesession(NULL, i); ++ dprintk("%s,%d: EINVALn", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ break; ++ case CRYPTO_AES_CBC: ++ (*ocd)->octo_ivsize = 16; ++ switch (macini ? macini->cri_alg : -1) { ++ case CRYPTO_MD5_HMAC: ++ (*ocd)->octo_encrypt = octo_aes_cbc_md5_encrypt; ++ (*ocd)->octo_decrypt = octo_aes_cbc_md5_decrypt; ++ octo_calc_hash(0, macini->cri_key, (*ocd)->octo_hminner, ++ (*ocd)->octo_hmouter); ++ break; ++ case CRYPTO_SHA1_HMAC: ++ (*ocd)->octo_encrypt = octo_aes_cbc_sha1_encrypt; ++ (*ocd)->octo_decrypt = octo_aes_cbc_sha1_decrypt; ++ octo_calc_hash(1, macini->cri_key, (*ocd)->octo_hminner, ++ (*ocd)->octo_hmouter); ++ break; ++ case -1: ++ (*ocd)->octo_encrypt = octo_aes_cbc_encrypt; ++ (*ocd)->octo_decrypt = octo_aes_cbc_decrypt; ++ break; ++ default: ++ octo_freesession(NULL, i); ++ dprintk("%s,%d: EINVALn", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ break; ++ case CRYPTO_MD5_HMAC: ++ (*ocd)->octo_encrypt = octo_null_md5_encrypt; ++ (*ocd)->octo_decrypt = octo_null_md5_encrypt; /* encrypt == decrypt */ ++ octo_calc_hash(0, macini->cri_key, (*ocd)->octo_hminner, ++ (*ocd)->octo_hmouter); ++ break; ++ case CRYPTO_SHA1_HMAC: ++ (*ocd)->octo_encrypt = octo_null_sha1_encrypt; ++ (*ocd)->octo_decrypt = octo_null_sha1_encrypt; /* encrypt == decrypt */ ++ octo_calc_hash(1, macini->cri_key, (*ocd)->octo_hminner, ++ (*ocd)->octo_hmouter); ++ break; ++ default: ++ octo_freesession(NULL, i); ++ dprintk("%s,%d: EINVALn", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ (*ocd)->octo_encalg = encini ? encini->cri_alg : -1; ++ (*ocd)->octo_macalg = macini ? macini->cri_alg : -1; ++ ++ return 0; ++} ++ ++/* ++ * Free a session. ++ */ ++static int ++octo_freesession(device_t dev, u_int64_t tid) ++{ ++ u_int32_t sid = CRYPTO_SESID2LID(tid); ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (sid > octo_sesnum || octo_sessions == NULL || ++ octo_sessions[sid] == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return(EINVAL); ++ } ++ ++ /* Silently accept and return */ ++ if (sid == 0) ++ return(0); ++ ++ if (octo_sessions[sid]) ++ kfree(octo_sessions[sid]); ++ octo_sessions[sid] = NULL; ++ return 0; ++} ++ ++/* ++ * Process a request. ++ */ ++static int ++octo_process(device_t dev, struct cryptop *crp, int hint) ++{ ++ struct cryptodesc *crd; ++ struct octo_sess *od; ++ u_int32_t lid; ++#define SCATTERLIST_MAX 16 ++ struct scatterlist sg[SCATTERLIST_MAX]; ++ int sg_num, sg_len; ++ struct sk_buff *skb = NULL; ++ struct uio *uiop = NULL; ++ struct cryptodesc *enccrd = NULL, *maccrd = NULL; ++ unsigned char *ivp = NULL; ++ unsigned char iv_data[HASH_MAX_LEN]; ++ int auth_off = 0, auth_len = 0, crypt_off = 0, crypt_len = 0, icv_off = 0; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ /* Sanity check */ ++ if (crp == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ crp->crp_etype = 0; ++ ++ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ crp->crp_etype = EINVAL; ++ goto done; ++ } ++ ++ lid = crp->crp_sid & 0xffffffff; ++ if (lid >= octo_sesnum || lid == 0 || octo_sessions == NULL || ++ octo_sessions[lid] == NULL) { ++ crp->crp_etype = ENOENT; ++ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); ++ goto done; ++ } ++ od = octo_sessions[lid]; ++ ++ /* ++ * do some error checking outside of the loop for SKB and IOV processing ++ * this leaves us with valid skb or uiop pointers for later ++ */ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ skb = (struct sk_buff *) crp->crp_buf; ++ if (skb_shinfo(skb)->nr_frags >= SCATTERLIST_MAX) { ++ printk("%s,%d: %d nr_frags > SCATTERLIST_MAX", __FILE__, __LINE__, ++ skb_shinfo(skb)->nr_frags); ++ goto done; ++ } ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ uiop = (struct uio *) crp->crp_buf; ++ if (uiop->uio_iovcnt > SCATTERLIST_MAX) { ++ printk("%s,%d: %d uio_iovcnt > SCATTERLIST_MAX", __FILE__, __LINE__, ++ uiop->uio_iovcnt); ++ goto done; ++ } ++ } ++ ++ /* point our enccrd and maccrd appropriately */ ++ crd = crp->crp_desc; ++ if (crd->crd_alg == od->octo_encalg) enccrd = crd; ++ if (crd->crd_alg == od->octo_macalg) maccrd = crd; ++ crd = crd->crd_next; ++ if (crd) { ++ if (crd->crd_alg == od->octo_encalg) enccrd = crd; ++ if (crd->crd_alg == od->octo_macalg) maccrd = crd; ++ crd = crd->crd_next; ++ } ++ if (crd) { ++ crp->crp_etype = EINVAL; ++ dprintk("%s,%d: ENOENT - descriptors do not match session\n", ++ __FILE__, __LINE__); ++ goto done; ++ } ++ ++ if (enccrd) { ++ if (enccrd->crd_flags & CRD_F_ENCRYPT) { ++ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) ++ ivp = enccrd->crd_iv; ++ else ++ read_random((ivp = iv_data), od->octo_ivsize); ++ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ enccrd->crd_inject, od->octo_ivsize, ivp); ++ } else { ++ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) { ++ ivp = enccrd->crd_iv; ++ } else { ++ ivp = iv_data; ++ crypto_copydata(crp->crp_flags, crp->crp_buf, ++ enccrd->crd_inject, od->octo_ivsize, (caddr_t) ivp); ++ } ++ } ++ ++ if (maccrd) { ++ auth_off = maccrd->crd_skip; ++ auth_len = maccrd->crd_len; ++ icv_off = maccrd->crd_inject; ++ } ++ ++ crypt_off = enccrd->crd_skip; ++ crypt_len = enccrd->crd_len; ++ } else { /* if (maccrd) */ ++ auth_off = maccrd->crd_skip; ++ auth_len = maccrd->crd_len; ++ icv_off = maccrd->crd_inject; ++ } ++ ++ ++ /* ++ * setup the SG list to cover the buffer ++ */ ++ memset(sg, 0, sizeof(sg)); ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ int i, len; ++ ++ sg_num = 0; ++ sg_len = 0; ++ ++ len = skb_headlen(skb); ++ sg_set_page(&sg[sg_num], virt_to_page(skb->data), len, ++ offset_in_page(skb->data)); ++ sg_len += len; ++ sg_num++; ++ ++ for (i = 0; i < skb_shinfo(skb)->nr_frags && sg_num < SCATTERLIST_MAX; ++ i++) { ++ len = skb_shinfo(skb)->frags[i].size; ++ sg_set_page(&sg[sg_num], skb_shinfo(skb)->frags[i].page, ++ len, skb_shinfo(skb)->frags[i].page_offset); ++ sg_len += len; ++ sg_num++; ++ } ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ int len; ++ ++ sg_len = 0; ++ for (sg_num = 0; sg_len < crp->crp_ilen && ++ sg_num < uiop->uio_iovcnt && ++ sg_num < SCATTERLIST_MAX; sg_num++) { ++ len = uiop->uio_iov[sg_num].iov_len; ++ sg_set_page(&sg[sg_num], ++ virt_to_page(uiop->uio_iov[sg_num].iov_base), len, ++ offset_in_page(uiop->uio_iov[sg_num].iov_base)); ++ sg_len += len; ++ } ++ } else { ++ sg_len = crp->crp_ilen; ++ sg_set_page(&sg[0], virt_to_page(crp->crp_buf), sg_len, ++ offset_in_page(crp->crp_buf)); ++ sg_num = 1; ++ } ++ ++ ++ /* ++ * setup a new explicit key ++ */ ++ if (enccrd) { ++ if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) { ++ od->octo_encklen = (enccrd->crd_klen + 7) / 8; ++ memcpy(od->octo_enckey, enccrd->crd_key, od->octo_encklen); ++ } ++ } ++ if (maccrd) { ++ if (maccrd->crd_flags & CRD_F_KEY_EXPLICIT) { ++ od->octo_macklen = (maccrd->crd_klen + 7) / 8; ++ memcpy(od->octo_mackey, maccrd->crd_key, od->octo_macklen); ++ od->octo_mackey_set = 0; ++ } ++ if (!od->octo_mackey_set) { ++ octo_calc_hash(maccrd->crd_alg == CRYPTO_MD5_HMAC ? 0 : 1, ++ maccrd->crd_key, od->octo_hminner, od->octo_hmouter); ++ od->octo_mackey_set = 1; ++ } ++ } ++ ++ ++ if (!enccrd || (enccrd->crd_flags & CRD_F_ENCRYPT)) ++ (*od->octo_encrypt)(od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ else ++ (*od->octo_decrypt)(od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ ++done: ++ crypto_done(crp); ++ return 0; ++} ++ ++static int ++cryptocteon_init(void) ++{ ++ dprintk("%s(%p)\n", __FUNCTION__, cryptocteon_init); ++ ++ softc_device_init(&octo_softc, "cryptocteon", 0, octo_methods); ++ ++ octo_id = crypto_get_driverid(softc_get_device(&octo_softc), ++ CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SYNC); ++ if (octo_id < 0) { ++ printk("Cryptocteon device cannot initialize!"); ++ return -ENODEV; ++ } ++ ++ crypto_register(octo_id, CRYPTO_MD5_HMAC, 0,0); ++ crypto_register(octo_id, CRYPTO_SHA1_HMAC, 0,0); ++ //crypto_register(octo_id, CRYPTO_MD5, 0,0); ++ //crypto_register(octo_id, CRYPTO_SHA1, 0,0); ++ crypto_register(octo_id, CRYPTO_DES_CBC, 0,0); ++ crypto_register(octo_id, CRYPTO_3DES_CBC, 0,0); ++ crypto_register(octo_id, CRYPTO_AES_CBC, 0,0); ++ ++ return(0); ++} ++ ++static void ++cryptocteon_exit(void) ++{ ++ dprintk("%s()\n", __FUNCTION__); ++ crypto_unregister_all(octo_id); ++ octo_id = -1; ++} ++ ++module_init(cryptocteon_init); ++module_exit(cryptocteon_exit); ++ ++MODULE_LICENSE("BSD"); ++MODULE_AUTHOR("David McCullough "); ++MODULE_DESCRIPTION("Cryptocteon (OCF module for Cavium OCTEON crypto)"); +diff -Nur linux-3.0.4.orig/crypto/ocf/cryptodev.c linux-3.0.4/crypto/ocf/cryptodev.c +--- linux-3.0.4.orig/crypto/ocf/cryptodev.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/cryptodev.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,1069 @@ ++/* $OpenBSD: cryptodev.c,v 1.52 2002/06/19 07:22:46 deraadt Exp $ */ ++ ++/*- ++ * Linux port done by David McCullough ++ * Copyright (C) 2006-2010 David McCullough ++ * Copyright (C) 2004-2005 Intel Corporation. ++ * The license and original author are listed below. ++ * ++ * Copyright (c) 2001 Theo de Raadt ++ * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored in part by the Defense Advanced Research Projects ++ * Agency (DARPA) and Air Force Research Laboratory, Air Force ++ * Materiel Command, USAF, under agreement number F30602-01-2-0537. ++ * ++__FBSDID("$FreeBSD: src/sys/opencrypto/cryptodev.c,v 1.34 2007/05/09 19:37:02 gnn Exp $"); ++ */ ++ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++extern asmlinkage long sys_dup(unsigned int fildes); ++ ++#define debug cryptodev_debug ++int cryptodev_debug = 0; ++module_param(cryptodev_debug, int, 0644); ++MODULE_PARM_DESC(cryptodev_debug, "Enable cryptodev debug"); ++ ++struct csession_info { ++ u_int16_t blocksize; ++ u_int16_t minkey, maxkey; ++ ++ u_int16_t keysize; ++ /* u_int16_t hashsize; */ ++ u_int16_t authsize; ++ u_int16_t authkey; ++ /* u_int16_t ctxsize; */ ++}; ++ ++struct csession { ++ struct list_head list; ++ u_int64_t sid; ++ u_int32_t ses; ++ ++ wait_queue_head_t waitq; ++ ++ u_int32_t cipher; ++ ++ u_int32_t mac; ++ ++ caddr_t key; ++ int keylen; ++ u_char tmp_iv[EALG_MAX_BLOCK_LEN]; ++ ++ caddr_t mackey; ++ int mackeylen; ++ ++ struct csession_info info; ++ ++ struct iovec iovec; ++ struct uio uio; ++ int error; ++}; ++ ++struct fcrypt { ++ struct list_head csessions; ++ int sesn; ++}; ++ ++static struct csession *csefind(struct fcrypt *, u_int); ++static int csedelete(struct fcrypt *, struct csession *); ++static struct csession *cseadd(struct fcrypt *, struct csession *); ++static struct csession *csecreate(struct fcrypt *, u_int64_t, ++ struct cryptoini *crie, struct cryptoini *cria, struct csession_info *); ++static int csefree(struct csession *); ++ ++static int cryptodev_op(struct csession *, struct crypt_op *); ++static int cryptodev_key(struct crypt_kop *); ++static int cryptodev_find(struct crypt_find_op *); ++ ++static int cryptodev_cb(void *); ++static int cryptodev_open(struct inode *inode, struct file *filp); ++ ++/* ++ * Check a crypto identifier to see if it requested ++ * a valid crid and it's capabilities match. ++ */ ++static int ++checkcrid(int crid) ++{ ++ int hid = crid & ~(CRYPTOCAP_F_SOFTWARE | CRYPTOCAP_F_HARDWARE); ++ int typ = crid & (CRYPTOCAP_F_SOFTWARE | CRYPTOCAP_F_HARDWARE); ++ int caps = 0; ++ ++ /* if the user hasn't selected a driver, then just call newsession */ ++ if (hid == 0 && typ != 0) ++ return 0; ++ ++ caps = crypto_getcaps(hid); ++ ++ /* didn't find anything with capabilities */ ++ if (caps == 0) { ++ dprintk("%s: hid=%x typ=%x not matched\n", __FUNCTION__, hid, typ); ++ return EINVAL; ++ } ++ ++ /* the user didn't specify SW or HW, so the driver is ok */ ++ if (typ == 0) ++ return 0; ++ ++ /* if the type specified didn't match */ ++ if (typ != (caps & (CRYPTOCAP_F_SOFTWARE | CRYPTOCAP_F_HARDWARE))) { ++ dprintk("%s: hid=%x typ=%x caps=%x not matched\n", __FUNCTION__, ++ hid, typ, caps); ++ return EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int ++cryptodev_op(struct csession *cse, struct crypt_op *cop) ++{ ++ struct cryptop *crp = NULL; ++ struct cryptodesc *crde = NULL, *crda = NULL; ++ int error = 0; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (cop->len > CRYPTO_MAX_DATA_LEN) { ++ dprintk("%s: %d > %d\n", __FUNCTION__, cop->len, CRYPTO_MAX_DATA_LEN); ++ return (E2BIG); ++ } ++ ++ if (cse->info.blocksize && (cop->len % cse->info.blocksize) != 0) { ++ dprintk("%s: blocksize=%d len=%d\n", __FUNCTION__, cse->info.blocksize, ++ cop->len); ++ return (EINVAL); ++ } ++ ++ cse->uio.uio_iov = &cse->iovec; ++ cse->uio.uio_iovcnt = 1; ++ cse->uio.uio_offset = 0; ++#if 0 ++ cse->uio.uio_resid = cop->len; ++ cse->uio.uio_segflg = UIO_SYSSPACE; ++ cse->uio.uio_rw = UIO_WRITE; ++ cse->uio.uio_td = td; ++#endif ++ cse->uio.uio_iov[0].iov_len = cop->len; ++ if (cse->info.authsize) ++ cse->uio.uio_iov[0].iov_len += cse->info.authsize; ++ cse->uio.uio_iov[0].iov_base = kmalloc(cse->uio.uio_iov[0].iov_len, ++ GFP_KERNEL); ++ ++ if (cse->uio.uio_iov[0].iov_base == NULL) { ++ dprintk("%s: iov_base kmalloc(%d) failed\n", __FUNCTION__, ++ (int)cse->uio.uio_iov[0].iov_len); ++ return (ENOMEM); ++ } ++ ++ crp = crypto_getreq((cse->info.blocksize != 0) + (cse->info.authsize != 0)); ++ if (crp == NULL) { ++ dprintk("%s: ENOMEM\n", __FUNCTION__); ++ error = ENOMEM; ++ goto bail; ++ } ++ ++ if (cse->info.authsize && cse->info.blocksize) { ++ if (cop->op == COP_ENCRYPT) { ++ crde = crp->crp_desc; ++ crda = crde->crd_next; ++ } else { ++ crda = crp->crp_desc; ++ crde = crda->crd_next; ++ } ++ } else if (cse->info.authsize) { ++ crda = crp->crp_desc; ++ } else if (cse->info.blocksize) { ++ crde = crp->crp_desc; ++ } else { ++ dprintk("%s: bad request\n", __FUNCTION__); ++ error = EINVAL; ++ goto bail; ++ } ++ ++ if ((error = copy_from_user(cse->uio.uio_iov[0].iov_base, cop->src, ++ cop->len))) { ++ dprintk("%s: bad copy\n", __FUNCTION__); ++ goto bail; ++ } ++ ++ if (crda) { ++ crda->crd_skip = 0; ++ crda->crd_len = cop->len; ++ crda->crd_inject = cop->len; ++ ++ crda->crd_alg = cse->mac; ++ crda->crd_key = cse->mackey; ++ crda->crd_klen = cse->mackeylen * 8; ++ } ++ ++ if (crde) { ++ if (cop->op == COP_ENCRYPT) ++ crde->crd_flags |= CRD_F_ENCRYPT; ++ else ++ crde->crd_flags &= ~CRD_F_ENCRYPT; ++ crde->crd_len = cop->len; ++ crde->crd_inject = 0; ++ ++ crde->crd_alg = cse->cipher; ++ crde->crd_key = cse->key; ++ crde->crd_klen = cse->keylen * 8; ++ } ++ ++ crp->crp_ilen = cse->uio.uio_iov[0].iov_len; ++ crp->crp_flags = CRYPTO_F_IOV | CRYPTO_F_CBIMM ++ | (cop->flags & COP_F_BATCH); ++ crp->crp_buf = (caddr_t)&cse->uio; ++ crp->crp_callback = (int (*) (struct cryptop *)) cryptodev_cb; ++ crp->crp_sid = cse->sid; ++ crp->crp_opaque = (void *)cse; ++ ++ if (cop->iv) { ++ if (crde == NULL) { ++ error = EINVAL; ++ dprintk("%s no crde\n", __FUNCTION__); ++ goto bail; ++ } ++ if (cse->cipher == CRYPTO_ARC4) { /* XXX use flag? */ ++ error = EINVAL; ++ dprintk("%s arc4 with IV\n", __FUNCTION__); ++ goto bail; ++ } ++ if ((error = copy_from_user(cse->tmp_iv, cop->iv, ++ cse->info.blocksize))) { ++ dprintk("%s bad iv copy\n", __FUNCTION__); ++ goto bail; ++ } ++ memcpy(crde->crd_iv, cse->tmp_iv, cse->info.blocksize); ++ crde->crd_flags |= CRD_F_IV_EXPLICIT | CRD_F_IV_PRESENT; ++ crde->crd_skip = 0; ++ } else if (cse->cipher == CRYPTO_ARC4) { /* XXX use flag? */ ++ crde->crd_skip = 0; ++ } else if (crde) { ++ crde->crd_flags |= CRD_F_IV_PRESENT; ++ crde->crd_skip = cse->info.blocksize; ++ crde->crd_len -= cse->info.blocksize; ++ } ++ ++ if (cop->mac && crda == NULL) { ++ error = EINVAL; ++ dprintk("%s no crda\n", __FUNCTION__); ++ goto bail; ++ } ++ ++ /* ++ * Let the dispatch run unlocked, then, interlock against the ++ * callback before checking if the operation completed and going ++ * to sleep. This insures drivers don't inherit our lock which ++ * results in a lock order reversal between crypto_dispatch forced ++ * entry and the crypto_done callback into us. ++ */ ++ error = crypto_dispatch(crp); ++ if (error) { ++ dprintk("%s error in crypto_dispatch\n", __FUNCTION__); ++ goto bail; ++ } ++ ++ dprintk("%s about to WAIT\n", __FUNCTION__); ++ /* ++ * we really need to wait for driver to complete to maintain ++ * state, luckily interrupts will be remembered ++ */ ++ do { ++ error = wait_event_interruptible(crp->crp_waitq, ++ ((crp->crp_flags & CRYPTO_F_DONE) != 0)); ++ /* ++ * we can't break out of this loop or we will leave behind ++ * a huge mess, however, staying here means if your driver ++ * is broken user applications can hang and not be killed. ++ * The solution, fix your driver :-) ++ */ ++ if (error) { ++ schedule(); ++ error = 0; ++ } ++ } while ((crp->crp_flags & CRYPTO_F_DONE) == 0); ++ dprintk("%s finished WAITING error=%d\n", __FUNCTION__, error); ++ ++ if (crp->crp_etype != 0) { ++ error = crp->crp_etype; ++ dprintk("%s error in crp processing\n", __FUNCTION__); ++ goto bail; ++ } ++ ++ if (cse->error) { ++ error = cse->error; ++ dprintk("%s error in cse processing\n", __FUNCTION__); ++ goto bail; ++ } ++ ++ if (cop->dst && (error = copy_to_user(cop->dst, ++ cse->uio.uio_iov[0].iov_base, cop->len))) { ++ dprintk("%s bad dst copy\n", __FUNCTION__); ++ goto bail; ++ } ++ ++ if (cop->mac && ++ (error=copy_to_user(cop->mac, ++ (caddr_t)cse->uio.uio_iov[0].iov_base + cop->len, ++ cse->info.authsize))) { ++ dprintk("%s bad mac copy\n", __FUNCTION__); ++ goto bail; ++ } ++ ++bail: ++ if (crp) ++ crypto_freereq(crp); ++ if (cse->uio.uio_iov[0].iov_base) ++ kfree(cse->uio.uio_iov[0].iov_base); ++ ++ return (error); ++} ++ ++static int ++cryptodev_cb(void *op) ++{ ++ struct cryptop *crp = (struct cryptop *) op; ++ struct csession *cse = (struct csession *)crp->crp_opaque; ++ int error; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ error = crp->crp_etype; ++ if (error == EAGAIN) { ++ crp->crp_flags &= ~CRYPTO_F_DONE; ++#ifdef NOTYET ++ /* ++ * DAVIDM I am fairly sure that we should turn this into a batch ++ * request to stop bad karma/lockup, revisit ++ */ ++ crp->crp_flags |= CRYPTO_F_BATCH; ++#endif ++ return crypto_dispatch(crp); ++ } ++ if (error != 0 || (crp->crp_flags & CRYPTO_F_DONE)) { ++ cse->error = error; ++ wake_up_interruptible(&crp->crp_waitq); ++ } ++ return (0); ++} ++ ++static int ++cryptodevkey_cb(void *op) ++{ ++ struct cryptkop *krp = (struct cryptkop *) op; ++ dprintk("%s()\n", __FUNCTION__); ++ wake_up_interruptible(&krp->krp_waitq); ++ return (0); ++} ++ ++static int ++cryptodev_key(struct crypt_kop *kop) ++{ ++ struct cryptkop *krp = NULL; ++ int error = EINVAL; ++ int in, out, size, i; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (kop->crk_iparams + kop->crk_oparams > CRK_MAXPARAM) { ++ dprintk("%s params too big\n", __FUNCTION__); ++ return (EFBIG); ++ } ++ ++ in = kop->crk_iparams; ++ out = kop->crk_oparams; ++ switch (kop->crk_op) { ++ case CRK_MOD_EXP: ++ if (in == 3 && out == 1) ++ break; ++ return (EINVAL); ++ case CRK_MOD_EXP_CRT: ++ if (in == 6 && out == 1) ++ break; ++ return (EINVAL); ++ case CRK_DSA_SIGN: ++ if (in == 5 && out == 2) ++ break; ++ return (EINVAL); ++ case CRK_DSA_VERIFY: ++ if (in == 7 && out == 0) ++ break; ++ return (EINVAL); ++ case CRK_DH_COMPUTE_KEY: ++ if (in == 3 && out == 1) ++ break; ++ return (EINVAL); ++ default: ++ return (EINVAL); ++ } ++ ++ krp = (struct cryptkop *)kmalloc(sizeof *krp, GFP_KERNEL); ++ if (!krp) ++ return (ENOMEM); ++ bzero(krp, sizeof *krp); ++ krp->krp_op = kop->crk_op; ++ krp->krp_status = kop->crk_status; ++ krp->krp_iparams = kop->crk_iparams; ++ krp->krp_oparams = kop->crk_oparams; ++ krp->krp_crid = kop->crk_crid; ++ krp->krp_status = 0; ++ krp->krp_flags = CRYPTO_KF_CBIMM; ++ krp->krp_callback = (int (*) (struct cryptkop *)) cryptodevkey_cb; ++ init_waitqueue_head(&krp->krp_waitq); ++ ++ for (i = 0; i < CRK_MAXPARAM; i++) ++ krp->krp_param[i].crp_nbits = kop->crk_param[i].crp_nbits; ++ for (i = 0; i < krp->krp_iparams + krp->krp_oparams; i++) { ++ size = (krp->krp_param[i].crp_nbits + 7) / 8; ++ if (size == 0) ++ continue; ++ krp->krp_param[i].crp_p = (caddr_t) kmalloc(size, GFP_KERNEL); ++ if (i >= krp->krp_iparams) ++ continue; ++ error = copy_from_user(krp->krp_param[i].crp_p, ++ kop->crk_param[i].crp_p, size); ++ if (error) ++ goto fail; ++ } ++ ++ error = crypto_kdispatch(krp); ++ if (error) ++ goto fail; ++ ++ do { ++ error = wait_event_interruptible(krp->krp_waitq, ++ ((krp->krp_flags & CRYPTO_KF_DONE) != 0)); ++ /* ++ * we can't break out of this loop or we will leave behind ++ * a huge mess, however, staying here means if your driver ++ * is broken user applications can hang and not be killed. ++ * The solution, fix your driver :-) ++ */ ++ if (error) { ++ schedule(); ++ error = 0; ++ } ++ } while ((krp->krp_flags & CRYPTO_KF_DONE) == 0); ++ ++ dprintk("%s finished WAITING error=%d\n", __FUNCTION__, error); ++ ++ kop->crk_crid = krp->krp_crid; /* device that did the work */ ++ if (krp->krp_status != 0) { ++ error = krp->krp_status; ++ goto fail; ++ } ++ ++ for (i = krp->krp_iparams; i < krp->krp_iparams + krp->krp_oparams; i++) { ++ size = (krp->krp_param[i].crp_nbits + 7) / 8; ++ if (size == 0) ++ continue; ++ error = copy_to_user(kop->crk_param[i].crp_p, krp->krp_param[i].crp_p, ++ size); ++ if (error) ++ goto fail; ++ } ++ ++fail: ++ if (krp) { ++ kop->crk_status = krp->krp_status; ++ for (i = 0; i < CRK_MAXPARAM; i++) { ++ if (krp->krp_param[i].crp_p) ++ kfree(krp->krp_param[i].crp_p); ++ } ++ kfree(krp); ++ } ++ return (error); ++} ++ ++static int ++cryptodev_find(struct crypt_find_op *find) ++{ ++ device_t dev; ++ ++ if (find->crid != -1) { ++ dev = crypto_find_device_byhid(find->crid); ++ if (dev == NULL) ++ return (ENOENT); ++ strlcpy(find->name, device_get_nameunit(dev), ++ sizeof(find->name)); ++ } else { ++ find->crid = crypto_find_driver(find->name); ++ if (find->crid == -1) ++ return (ENOENT); ++ } ++ return (0); ++} ++ ++static struct csession * ++csefind(struct fcrypt *fcr, u_int ses) ++{ ++ struct csession *cse; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ list_for_each_entry(cse, &fcr->csessions, list) ++ if (cse->ses == ses) ++ return (cse); ++ return (NULL); ++} ++ ++static int ++csedelete(struct fcrypt *fcr, struct csession *cse_del) ++{ ++ struct csession *cse; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ list_for_each_entry(cse, &fcr->csessions, list) { ++ if (cse == cse_del) { ++ list_del(&cse->list); ++ return (1); ++ } ++ } ++ return (0); ++} ++ ++static struct csession * ++cseadd(struct fcrypt *fcr, struct csession *cse) ++{ ++ dprintk("%s()\n", __FUNCTION__); ++ list_add_tail(&cse->list, &fcr->csessions); ++ cse->ses = fcr->sesn++; ++ return (cse); ++} ++ ++static struct csession * ++csecreate(struct fcrypt *fcr, u_int64_t sid, struct cryptoini *crie, ++ struct cryptoini *cria, struct csession_info *info) ++{ ++ struct csession *cse; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ cse = (struct csession *) kmalloc(sizeof(struct csession), GFP_KERNEL); ++ if (cse == NULL) ++ return NULL; ++ memset(cse, 0, sizeof(struct csession)); ++ ++ INIT_LIST_HEAD(&cse->list); ++ init_waitqueue_head(&cse->waitq); ++ ++ cse->key = crie->cri_key; ++ cse->keylen = crie->cri_klen/8; ++ cse->mackey = cria->cri_key; ++ cse->mackeylen = cria->cri_klen/8; ++ cse->sid = sid; ++ cse->cipher = crie->cri_alg; ++ cse->mac = cria->cri_alg; ++ cse->info = *info; ++ cseadd(fcr, cse); ++ return (cse); ++} ++ ++static int ++csefree(struct csession *cse) ++{ ++ int error; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ error = crypto_freesession(cse->sid); ++ if (cse->key) ++ kfree(cse->key); ++ if (cse->mackey) ++ kfree(cse->mackey); ++ kfree(cse); ++ return(error); ++} ++ ++static int ++cryptodev_ioctl( ++ struct inode *inode, ++ struct file *filp, ++ unsigned int cmd, ++ unsigned long arg) ++{ ++ struct cryptoini cria, crie; ++ struct fcrypt *fcr = filp->private_data; ++ struct csession *cse; ++ struct csession_info info; ++ struct session2_op sop; ++ struct crypt_op cop; ++ struct crypt_kop kop; ++ struct crypt_find_op fop; ++ u_int64_t sid; ++ u_int32_t ses = 0; ++ int feat, fd, error = 0, crid; ++ mm_segment_t fs; ++ ++ dprintk("%s(cmd=%x arg=%lx)\n", __FUNCTION__, cmd, arg); ++ ++ switch (cmd) { ++ ++ case CRIOGET: { ++ dprintk("%s(CRIOGET)\n", __FUNCTION__); ++ fs = get_fs(); ++ set_fs(get_ds()); ++ for (fd = 0; fd < files_fdtable(current->files)->max_fds; fd++) ++ if (files_fdtable(current->files)->fd[fd] == filp) ++ break; ++ fd = sys_dup(fd); ++ set_fs(fs); ++ put_user(fd, (int *) arg); ++ return IS_ERR_VALUE(fd) ? fd : 0; ++ } ++ ++#define CIOCGSESSSTR (cmd == CIOCGSESSION ? "CIOCGSESSION" : "CIOCGSESSION2") ++ case CIOCGSESSION: ++ case CIOCGSESSION2: ++ dprintk("%s(%s)\n", __FUNCTION__, CIOCGSESSSTR); ++ memset(&crie, 0, sizeof(crie)); ++ memset(&cria, 0, sizeof(cria)); ++ memset(&info, 0, sizeof(info)); ++ memset(&sop, 0, sizeof(sop)); ++ ++ if (copy_from_user(&sop, (void*)arg, (cmd == CIOCGSESSION) ? ++ sizeof(struct session_op) : sizeof(sop))) { ++ dprintk("%s(%s) - bad copy\n", __FUNCTION__, CIOCGSESSSTR); ++ error = EFAULT; ++ goto bail; ++ } ++ ++ switch (sop.cipher) { ++ case 0: ++ dprintk("%s(%s) - no cipher\n", __FUNCTION__, CIOCGSESSSTR); ++ break; ++ case CRYPTO_NULL_CBC: ++ info.blocksize = NULL_BLOCK_LEN; ++ info.minkey = NULL_MIN_KEY_LEN; ++ info.maxkey = NULL_MAX_KEY_LEN; ++ break; ++ case CRYPTO_DES_CBC: ++ info.blocksize = DES_BLOCK_LEN; ++ info.minkey = DES_MIN_KEY_LEN; ++ info.maxkey = DES_MAX_KEY_LEN; ++ break; ++ case CRYPTO_3DES_CBC: ++ info.blocksize = DES3_BLOCK_LEN; ++ info.minkey = DES3_MIN_KEY_LEN; ++ info.maxkey = DES3_MAX_KEY_LEN; ++ break; ++ case CRYPTO_BLF_CBC: ++ info.blocksize = BLOWFISH_BLOCK_LEN; ++ info.minkey = BLOWFISH_MIN_KEY_LEN; ++ info.maxkey = BLOWFISH_MAX_KEY_LEN; ++ break; ++ case CRYPTO_CAST_CBC: ++ info.blocksize = CAST128_BLOCK_LEN; ++ info.minkey = CAST128_MIN_KEY_LEN; ++ info.maxkey = CAST128_MAX_KEY_LEN; ++ break; ++ case CRYPTO_SKIPJACK_CBC: ++ info.blocksize = SKIPJACK_BLOCK_LEN; ++ info.minkey = SKIPJACK_MIN_KEY_LEN; ++ info.maxkey = SKIPJACK_MAX_KEY_LEN; ++ break; ++ case CRYPTO_AES_CBC: ++ info.blocksize = AES_BLOCK_LEN; ++ info.minkey = AES_MIN_KEY_LEN; ++ info.maxkey = AES_MAX_KEY_LEN; ++ break; ++ case CRYPTO_ARC4: ++ info.blocksize = ARC4_BLOCK_LEN; ++ info.minkey = ARC4_MIN_KEY_LEN; ++ info.maxkey = ARC4_MAX_KEY_LEN; ++ break; ++ case CRYPTO_CAMELLIA_CBC: ++ info.blocksize = CAMELLIA_BLOCK_LEN; ++ info.minkey = CAMELLIA_MIN_KEY_LEN; ++ info.maxkey = CAMELLIA_MAX_KEY_LEN; ++ break; ++ default: ++ dprintk("%s(%s) - bad cipher\n", __FUNCTION__, CIOCGSESSSTR); ++ error = EINVAL; ++ goto bail; ++ } ++ ++ switch (sop.mac) { ++ case 0: ++ dprintk("%s(%s) - no mac\n", __FUNCTION__, CIOCGSESSSTR); ++ break; ++ case CRYPTO_NULL_HMAC: ++ info.authsize = NULL_HASH_LEN; ++ break; ++ case CRYPTO_MD5: ++ info.authsize = MD5_HASH_LEN; ++ break; ++ case CRYPTO_SHA1: ++ info.authsize = SHA1_HASH_LEN; ++ break; ++ case CRYPTO_SHA2_256: ++ info.authsize = SHA2_256_HASH_LEN; ++ break; ++ case CRYPTO_SHA2_384: ++ info.authsize = SHA2_384_HASH_LEN; ++ break; ++ case CRYPTO_SHA2_512: ++ info.authsize = SHA2_512_HASH_LEN; ++ break; ++ case CRYPTO_RIPEMD160: ++ info.authsize = RIPEMD160_HASH_LEN; ++ break; ++ case CRYPTO_MD5_HMAC: ++ info.authsize = MD5_HASH_LEN; ++ info.authkey = 16; ++ break; ++ case CRYPTO_SHA1_HMAC: ++ info.authsize = SHA1_HASH_LEN; ++ info.authkey = 20; ++ break; ++ case CRYPTO_SHA2_256_HMAC: ++ info.authsize = SHA2_256_HASH_LEN; ++ info.authkey = 32; ++ break; ++ case CRYPTO_SHA2_384_HMAC: ++ info.authsize = SHA2_384_HASH_LEN; ++ info.authkey = 48; ++ break; ++ case CRYPTO_SHA2_512_HMAC: ++ info.authsize = SHA2_512_HASH_LEN; ++ info.authkey = 64; ++ break; ++ case CRYPTO_RIPEMD160_HMAC: ++ info.authsize = RIPEMD160_HASH_LEN; ++ info.authkey = 20; ++ break; ++ default: ++ dprintk("%s(%s) - bad mac\n", __FUNCTION__, CIOCGSESSSTR); ++ error = EINVAL; ++ goto bail; ++ } ++ ++ if (info.blocksize) { ++ crie.cri_alg = sop.cipher; ++ crie.cri_klen = sop.keylen * 8; ++ if ((info.maxkey && sop.keylen > info.maxkey) || ++ sop.keylen < info.minkey) { ++ dprintk("%s(%s) - bad key\n", __FUNCTION__, CIOCGSESSSTR); ++ error = EINVAL; ++ goto bail; ++ } ++ ++ crie.cri_key = (u_int8_t *) kmalloc(crie.cri_klen/8+1, GFP_KERNEL); ++ if (copy_from_user(crie.cri_key, sop.key, ++ crie.cri_klen/8)) { ++ dprintk("%s(%s) - bad copy\n", __FUNCTION__, CIOCGSESSSTR); ++ error = EFAULT; ++ goto bail; ++ } ++ if (info.authsize) ++ crie.cri_next = &cria; ++ } ++ ++ if (info.authsize) { ++ cria.cri_alg = sop.mac; ++ cria.cri_klen = sop.mackeylen * 8; ++ if (info.authkey && sop.mackeylen != info.authkey) { ++ dprintk("%s(%s) - mackeylen %d != %d\n", __FUNCTION__, ++ CIOCGSESSSTR, sop.mackeylen, info.authkey); ++ error = EINVAL; ++ goto bail; ++ } ++ ++ if (cria.cri_klen) { ++ cria.cri_key = (u_int8_t *) kmalloc(cria.cri_klen/8,GFP_KERNEL); ++ if (copy_from_user(cria.cri_key, sop.mackey, ++ cria.cri_klen / 8)) { ++ dprintk("%s(%s) - bad copy\n", __FUNCTION__, CIOCGSESSSTR); ++ error = EFAULT; ++ goto bail; ++ } ++ } ++ } ++ ++ /* NB: CIOGSESSION2 has the crid */ ++ if (cmd == CIOCGSESSION2) { ++ crid = sop.crid; ++ error = checkcrid(crid); ++ if (error) { ++ dprintk("%s(%s) - checkcrid %x\n", __FUNCTION__, ++ CIOCGSESSSTR, error); ++ goto bail; ++ } ++ } else { ++ /* allow either HW or SW to be used */ ++ crid = CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE; ++ } ++ error = crypto_newsession(&sid, (info.blocksize ? &crie : &cria), crid); ++ if (error) { ++ dprintk("%s(%s) - newsession %d\n",__FUNCTION__,CIOCGSESSSTR,error); ++ goto bail; ++ } ++ ++ cse = csecreate(fcr, sid, &crie, &cria, &info); ++ if (cse == NULL) { ++ crypto_freesession(sid); ++ error = EINVAL; ++ dprintk("%s(%s) - csecreate failed\n", __FUNCTION__, CIOCGSESSSTR); ++ goto bail; ++ } ++ sop.ses = cse->ses; ++ ++ if (cmd == CIOCGSESSION2) { ++ /* return hardware/driver id */ ++ sop.crid = CRYPTO_SESID2HID(cse->sid); ++ } ++ ++ if (copy_to_user((void*)arg, &sop, (cmd == CIOCGSESSION) ? ++ sizeof(struct session_op) : sizeof(sop))) { ++ dprintk("%s(%s) - bad copy\n", __FUNCTION__, CIOCGSESSSTR); ++ error = EFAULT; ++ } ++bail: ++ if (error) { ++ dprintk("%s(%s) - bail %d\n", __FUNCTION__, CIOCGSESSSTR, error); ++ if (crie.cri_key) ++ kfree(crie.cri_key); ++ if (cria.cri_key) ++ kfree(cria.cri_key); ++ } ++ break; ++ case CIOCFSESSION: ++ dprintk("%s(CIOCFSESSION)\n", __FUNCTION__); ++ get_user(ses, (uint32_t*)arg); ++ cse = csefind(fcr, ses); ++ if (cse == NULL) { ++ error = EINVAL; ++ dprintk("%s(CIOCFSESSION) - Fail %d\n", __FUNCTION__, error); ++ break; ++ } ++ csedelete(fcr, cse); ++ error = csefree(cse); ++ break; ++ case CIOCCRYPT: ++ dprintk("%s(CIOCCRYPT)\n", __FUNCTION__); ++ if(copy_from_user(&cop, (void*)arg, sizeof(cop))) { ++ dprintk("%s(CIOCCRYPT) - bad copy\n", __FUNCTION__); ++ error = EFAULT; ++ goto bail; ++ } ++ cse = csefind(fcr, cop.ses); ++ if (cse == NULL) { ++ error = EINVAL; ++ dprintk("%s(CIOCCRYPT) - Fail %d\n", __FUNCTION__, error); ++ break; ++ } ++ error = cryptodev_op(cse, &cop); ++ if(copy_to_user((void*)arg, &cop, sizeof(cop))) { ++ dprintk("%s(CIOCCRYPT) - bad return copy\n", __FUNCTION__); ++ error = EFAULT; ++ goto bail; ++ } ++ break; ++ case CIOCKEY: ++ case CIOCKEY2: ++ dprintk("%s(CIOCKEY)\n", __FUNCTION__); ++ if (!crypto_userasymcrypto) ++ return (EPERM); /* XXX compat? */ ++ if(copy_from_user(&kop, (void*)arg, sizeof(kop))) { ++ dprintk("%s(CIOCKEY) - bad copy\n", __FUNCTION__); ++ error = EFAULT; ++ goto bail; ++ } ++ if (cmd == CIOCKEY) { ++ /* NB: crypto core enforces s/w driver use */ ++ kop.crk_crid = ++ CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE; ++ } ++ error = cryptodev_key(&kop); ++ if(copy_to_user((void*)arg, &kop, sizeof(kop))) { ++ dprintk("%s(CIOCGKEY) - bad return copy\n", __FUNCTION__); ++ error = EFAULT; ++ goto bail; ++ } ++ break; ++ case CIOCASYMFEAT: ++ dprintk("%s(CIOCASYMFEAT)\n", __FUNCTION__); ++ if (!crypto_userasymcrypto) { ++ /* ++ * NB: if user asym crypto operations are ++ * not permitted return "no algorithms" ++ * so well-behaved applications will just ++ * fallback to doing them in software. ++ */ ++ feat = 0; ++ } else ++ error = crypto_getfeat(&feat); ++ if (!error) { ++ error = copy_to_user((void*)arg, &feat, sizeof(feat)); ++ } ++ break; ++ case CIOCFINDDEV: ++ if (copy_from_user(&fop, (void*)arg, sizeof(fop))) { ++ dprintk("%s(CIOCFINDDEV) - bad copy\n", __FUNCTION__); ++ error = EFAULT; ++ goto bail; ++ } ++ error = cryptodev_find(&fop); ++ if (copy_to_user((void*)arg, &fop, sizeof(fop))) { ++ dprintk("%s(CIOCFINDDEV) - bad return copy\n", __FUNCTION__); ++ error = EFAULT; ++ goto bail; ++ } ++ break; ++ default: ++ dprintk("%s(unknown ioctl 0x%x)\n", __FUNCTION__, cmd); ++ error = EINVAL; ++ break; ++ } ++ return(-error); ++} ++ ++#ifdef HAVE_UNLOCKED_IOCTL ++static long ++cryptodev_unlocked_ioctl( ++ struct file *filp, ++ unsigned int cmd, ++ unsigned long arg) ++{ ++ return cryptodev_ioctl(NULL, filp, cmd, arg); ++} ++#endif ++ ++static int ++cryptodev_open(struct inode *inode, struct file *filp) ++{ ++ struct fcrypt *fcr; ++ ++ dprintk("%s()\n", __FUNCTION__); ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35) ++ /* ++ * on 2.6.35 private_data points to a miscdevice structure, we override ++ * it, which is currently safe to do. ++ */ ++ if (filp->private_data) { ++ printk("cryptodev: Private data already exists - %p!\n", filp->private_data); ++ return(-ENODEV); ++ } ++#endif ++ ++ fcr = kmalloc(sizeof(*fcr), GFP_KERNEL); ++ if (!fcr) { ++ dprintk("%s() - malloc failed\n", __FUNCTION__); ++ return(-ENOMEM); ++ } ++ memset(fcr, 0, sizeof(*fcr)); ++ ++ INIT_LIST_HEAD(&fcr->csessions); ++ filp->private_data = fcr; ++ return(0); ++} ++ ++static int ++cryptodev_release(struct inode *inode, struct file *filp) ++{ ++ struct fcrypt *fcr = filp->private_data; ++ struct csession *cse, *tmp; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (!filp) { ++ printk("cryptodev: No private data on release\n"); ++ return(0); ++ } ++ ++ list_for_each_entry_safe(cse, tmp, &fcr->csessions, list) { ++ list_del(&cse->list); ++ (void)csefree(cse); ++ } ++ filp->private_data = NULL; ++ kfree(fcr); ++ return(0); ++} ++ ++static struct file_operations cryptodev_fops = { ++ .owner = THIS_MODULE, ++ .open = cryptodev_open, ++ .release = cryptodev_release, ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36) ++ .ioctl = cryptodev_ioctl, ++#endif ++#ifdef HAVE_UNLOCKED_IOCTL ++ .unlocked_ioctl = cryptodev_unlocked_ioctl, ++#endif ++}; ++ ++static struct miscdevice cryptodev = { ++ .minor = CRYPTODEV_MINOR, ++ .name = "crypto", ++ .fops = &cryptodev_fops, ++}; ++ ++static int __init ++cryptodev_init(void) ++{ ++ int rc; ++ ++ dprintk("%s(%p)\n", __FUNCTION__, cryptodev_init); ++ rc = misc_register(&cryptodev); ++ if (rc) { ++ printk(KERN_ERR "cryptodev: registration of /dev/crypto failed\n"); ++ return(rc); ++ } ++ ++ return(0); ++} ++ ++static void __exit ++cryptodev_exit(void) ++{ ++ dprintk("%s()\n", __FUNCTION__); ++ misc_deregister(&cryptodev); ++} ++ ++module_init(cryptodev_init); ++module_exit(cryptodev_exit); ++ ++MODULE_LICENSE("BSD"); ++MODULE_AUTHOR("David McCullough "); ++MODULE_DESCRIPTION("Cryptodev (user interface to OCF)"); +diff -Nur linux-3.0.4.orig/crypto/ocf/cryptodev.h linux-3.0.4/crypto/ocf/cryptodev.h +--- linux-3.0.4.orig/crypto/ocf/cryptodev.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/cryptodev.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,480 @@ ++/* $FreeBSD: src/sys/opencrypto/cryptodev.h,v 1.25 2007/05/09 19:37:02 gnn Exp $ */ ++/* $OpenBSD: cryptodev.h,v 1.31 2002/06/11 11:14:29 beck Exp $ */ ++ ++/*- ++ * Linux port done by David McCullough ++ * Copyright (C) 2006-2010 David McCullough ++ * Copyright (C) 2004-2005 Intel Corporation. ++ * The license and original author are listed below. ++ * ++ * The author of this code is Angelos D. Keromytis (angelos@cis.upenn.edu) ++ * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting ++ * ++ * This code was written by Angelos D. Keromytis in Athens, Greece, in ++ * February 2000. Network Security Technologies Inc. (NSTI) kindly ++ * supported the development of this code. ++ * ++ * Copyright (c) 2000 Angelos D. Keromytis ++ * ++ * Permission to use, copy, and modify this software with or without fee ++ * is hereby granted, provided that this entire notice is included in ++ * all source code copies of any software which is or includes a copy or ++ * modification of this software. ++ * ++ * THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR ++ * IMPLIED WARRANTY. IN PARTICULAR, NONE OF THE AUTHORS MAKES ANY ++ * REPRESENTATION OR WARRANTY OF ANY KIND CONCERNING THE ++ * MERCHANTABILITY OF THIS SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR ++ * PURPOSE. ++ * ++ * Copyright (c) 2001 Theo de Raadt ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored in part by the Defense Advanced Research Projects ++ * Agency (DARPA) and Air Force Research Laboratory, Air Force ++ * Materiel Command, USAF, under agreement number F30602-01-2-0537. ++ * ++ */ ++ ++#ifndef _CRYPTO_CRYPTO_H_ ++#define _CRYPTO_CRYPTO_H_ ++ ++/* Some initial values */ ++#define CRYPTO_DRIVERS_INITIAL 4 ++#define CRYPTO_SW_SESSIONS 32 ++ ++/* Hash values */ ++#define NULL_HASH_LEN 0 ++#define MD5_HASH_LEN 16 ++#define SHA1_HASH_LEN 20 ++#define RIPEMD160_HASH_LEN 20 ++#define SHA2_256_HASH_LEN 32 ++#define SHA2_384_HASH_LEN 48 ++#define SHA2_512_HASH_LEN 64 ++#define MD5_KPDK_HASH_LEN 16 ++#define SHA1_KPDK_HASH_LEN 20 ++/* Maximum hash algorithm result length */ ++#define HASH_MAX_LEN SHA2_512_HASH_LEN /* Keep this updated */ ++ ++/* HMAC values */ ++#define NULL_HMAC_BLOCK_LEN 1 ++#define MD5_HMAC_BLOCK_LEN 64 ++#define SHA1_HMAC_BLOCK_LEN 64 ++#define RIPEMD160_HMAC_BLOCK_LEN 64 ++#define SHA2_256_HMAC_BLOCK_LEN 64 ++#define SHA2_384_HMAC_BLOCK_LEN 128 ++#define SHA2_512_HMAC_BLOCK_LEN 128 ++/* Maximum HMAC block length */ ++#define HMAC_MAX_BLOCK_LEN SHA2_512_HMAC_BLOCK_LEN /* Keep this updated */ ++#define HMAC_IPAD_VAL 0x36 ++#define HMAC_OPAD_VAL 0x5C ++ ++/* Encryption algorithm block sizes */ ++#define NULL_BLOCK_LEN 1 ++#define DES_BLOCK_LEN 8 ++#define DES3_BLOCK_LEN 8 ++#define BLOWFISH_BLOCK_LEN 8 ++#define SKIPJACK_BLOCK_LEN 8 ++#define CAST128_BLOCK_LEN 8 ++#define RIJNDAEL128_BLOCK_LEN 16 ++#define AES_BLOCK_LEN RIJNDAEL128_BLOCK_LEN ++#define CAMELLIA_BLOCK_LEN 16 ++#define ARC4_BLOCK_LEN 1 ++#define EALG_MAX_BLOCK_LEN AES_BLOCK_LEN /* Keep this updated */ ++ ++/* Encryption algorithm min and max key sizes */ ++#define NULL_MIN_KEY_LEN 0 ++#define NULL_MAX_KEY_LEN 0 ++#define DES_MIN_KEY_LEN 8 ++#define DES_MAX_KEY_LEN 8 ++#define DES3_MIN_KEY_LEN 24 ++#define DES3_MAX_KEY_LEN 24 ++#define BLOWFISH_MIN_KEY_LEN 4 ++#define BLOWFISH_MAX_KEY_LEN 56 ++#define SKIPJACK_MIN_KEY_LEN 10 ++#define SKIPJACK_MAX_KEY_LEN 10 ++#define CAST128_MIN_KEY_LEN 5 ++#define CAST128_MAX_KEY_LEN 16 ++#define RIJNDAEL128_MIN_KEY_LEN 16 ++#define RIJNDAEL128_MAX_KEY_LEN 32 ++#define AES_MIN_KEY_LEN RIJNDAEL128_MIN_KEY_LEN ++#define AES_MAX_KEY_LEN RIJNDAEL128_MAX_KEY_LEN ++#define CAMELLIA_MIN_KEY_LEN 16 ++#define CAMELLIA_MAX_KEY_LEN 32 ++#define ARC4_MIN_KEY_LEN 1 ++#define ARC4_MAX_KEY_LEN 256 ++ ++/* Max size of data that can be processed */ ++#define CRYPTO_MAX_DATA_LEN 64*1024 - 1 ++ ++#define CRYPTO_ALGORITHM_MIN 1 ++#define CRYPTO_DES_CBC 1 ++#define CRYPTO_3DES_CBC 2 ++#define CRYPTO_BLF_CBC 3 ++#define CRYPTO_CAST_CBC 4 ++#define CRYPTO_SKIPJACK_CBC 5 ++#define CRYPTO_MD5_HMAC 6 ++#define CRYPTO_SHA1_HMAC 7 ++#define CRYPTO_RIPEMD160_HMAC 8 ++#define CRYPTO_MD5_KPDK 9 ++#define CRYPTO_SHA1_KPDK 10 ++#define CRYPTO_RIJNDAEL128_CBC 11 /* 128 bit blocksize */ ++#define CRYPTO_AES_CBC 11 /* 128 bit blocksize -- the same as above */ ++#define CRYPTO_ARC4 12 ++#define CRYPTO_MD5 13 ++#define CRYPTO_SHA1 14 ++#define CRYPTO_NULL_HMAC 15 ++#define CRYPTO_NULL_CBC 16 ++#define CRYPTO_DEFLATE_COMP 17 /* Deflate compression algorithm */ ++#define CRYPTO_SHA2_256_HMAC 18 ++#define CRYPTO_SHA2_384_HMAC 19 ++#define CRYPTO_SHA2_512_HMAC 20 ++#define CRYPTO_CAMELLIA_CBC 21 ++#define CRYPTO_SHA2_256 22 ++#define CRYPTO_SHA2_384 23 ++#define CRYPTO_SHA2_512 24 ++#define CRYPTO_RIPEMD160 25 ++#define CRYPTO_LZS_COMP 26 ++#define CRYPTO_ALGORITHM_MAX 26 /* Keep updated - see above */ ++ ++/* Algorithm flags */ ++#define CRYPTO_ALG_FLAG_SUPPORTED 0x01 /* Algorithm is supported */ ++#define CRYPTO_ALG_FLAG_RNG_ENABLE 0x02 /* Has HW RNG for DH/DSA */ ++#define CRYPTO_ALG_FLAG_DSA_SHA 0x04 /* Can do SHA on msg */ ++ ++/* ++ * Crypto driver/device flags. They can set in the crid ++ * parameter when creating a session or submitting a key ++ * op to affect the device/driver assigned. If neither ++ * of these are specified then the crid is assumed to hold ++ * the driver id of an existing (and suitable) device that ++ * must be used to satisfy the request. ++ */ ++#define CRYPTO_FLAG_HARDWARE 0x01000000 /* hardware accelerated */ ++#define CRYPTO_FLAG_SOFTWARE 0x02000000 /* software implementation */ ++ ++/* NB: deprecated */ ++struct session_op { ++ u_int32_t cipher; /* ie. CRYPTO_DES_CBC */ ++ u_int32_t mac; /* ie. CRYPTO_MD5_HMAC */ ++ ++ u_int32_t keylen; /* cipher key */ ++ caddr_t key; ++ int mackeylen; /* mac key */ ++ caddr_t mackey; ++ ++ u_int32_t ses; /* returns: session # */ ++}; ++ ++struct session2_op { ++ u_int32_t cipher; /* ie. CRYPTO_DES_CBC */ ++ u_int32_t mac; /* ie. CRYPTO_MD5_HMAC */ ++ ++ u_int32_t keylen; /* cipher key */ ++ caddr_t key; ++ int mackeylen; /* mac key */ ++ caddr_t mackey; ++ ++ u_int32_t ses; /* returns: session # */ ++ int crid; /* driver id + flags (rw) */ ++ int pad[4]; /* for future expansion */ ++}; ++ ++struct crypt_op { ++ u_int32_t ses; ++ u_int16_t op; /* i.e. COP_ENCRYPT */ ++#define COP_NONE 0 ++#define COP_ENCRYPT 1 ++#define COP_DECRYPT 2 ++ u_int16_t flags; ++#define COP_F_BATCH 0x0008 /* Batch op if possible */ ++ u_int len; ++ caddr_t src, dst; /* become iov[] inside kernel */ ++ caddr_t mac; /* must be big enough for chosen MAC */ ++ caddr_t iv; ++}; ++ ++/* ++ * Parameters for looking up a crypto driver/device by ++ * device name or by id. The latter are returned for ++ * created sessions (crid) and completed key operations. ++ */ ++struct crypt_find_op { ++ int crid; /* driver id + flags */ ++ char name[32]; /* device/driver name */ ++}; ++ ++/* bignum parameter, in packed bytes, ... */ ++struct crparam { ++ caddr_t crp_p; ++ u_int crp_nbits; ++}; ++ ++#define CRK_MAXPARAM 8 ++ ++struct crypt_kop { ++ u_int crk_op; /* ie. CRK_MOD_EXP or other */ ++ u_int crk_status; /* return status */ ++ u_short crk_iparams; /* # of input parameters */ ++ u_short crk_oparams; /* # of output parameters */ ++ u_int crk_crid; /* NB: only used by CIOCKEY2 (rw) */ ++ struct crparam crk_param[CRK_MAXPARAM]; ++}; ++#define CRK_ALGORITM_MIN 0 ++#define CRK_MOD_EXP 0 ++#define CRK_MOD_EXP_CRT 1 ++#define CRK_DSA_SIGN 2 ++#define CRK_DSA_VERIFY 3 ++#define CRK_DH_COMPUTE_KEY 4 ++#define CRK_ALGORITHM_MAX 4 /* Keep updated - see below */ ++ ++#define CRF_MOD_EXP (1 << CRK_MOD_EXP) ++#define CRF_MOD_EXP_CRT (1 << CRK_MOD_EXP_CRT) ++#define CRF_DSA_SIGN (1 << CRK_DSA_SIGN) ++#define CRF_DSA_VERIFY (1 << CRK_DSA_VERIFY) ++#define CRF_DH_COMPUTE_KEY (1 << CRK_DH_COMPUTE_KEY) ++ ++/* ++ * done against open of /dev/crypto, to get a cloned descriptor. ++ * Please use F_SETFD against the cloned descriptor. ++ */ ++#define CRIOGET _IOWR('c', 100, u_int32_t) ++#define CRIOASYMFEAT CIOCASYMFEAT ++#define CRIOFINDDEV CIOCFINDDEV ++ ++/* the following are done against the cloned descriptor */ ++#define CIOCGSESSION _IOWR('c', 101, struct session_op) ++#define CIOCFSESSION _IOW('c', 102, u_int32_t) ++#define CIOCCRYPT _IOWR('c', 103, struct crypt_op) ++#define CIOCKEY _IOWR('c', 104, struct crypt_kop) ++#define CIOCASYMFEAT _IOR('c', 105, u_int32_t) ++#define CIOCGSESSION2 _IOWR('c', 106, struct session2_op) ++#define CIOCKEY2 _IOWR('c', 107, struct crypt_kop) ++#define CIOCFINDDEV _IOWR('c', 108, struct crypt_find_op) ++ ++struct cryptotstat { ++ struct timespec acc; /* total accumulated time */ ++ struct timespec min; /* min time */ ++ struct timespec max; /* max time */ ++ u_int32_t count; /* number of observations */ ++}; ++ ++struct cryptostats { ++ u_int32_t cs_ops; /* symmetric crypto ops submitted */ ++ u_int32_t cs_errs; /* symmetric crypto ops that failed */ ++ u_int32_t cs_kops; /* asymetric/key ops submitted */ ++ u_int32_t cs_kerrs; /* asymetric/key ops that failed */ ++ u_int32_t cs_intrs; /* crypto swi thread activations */ ++ u_int32_t cs_rets; /* crypto return thread activations */ ++ u_int32_t cs_blocks; /* symmetric op driver block */ ++ u_int32_t cs_kblocks; /* symmetric op driver block */ ++ /* ++ * When CRYPTO_TIMING is defined at compile time and the ++ * sysctl debug.crypto is set to 1, the crypto system will ++ * accumulate statistics about how long it takes to process ++ * crypto requests at various points during processing. ++ */ ++ struct cryptotstat cs_invoke; /* crypto_dipsatch -> crypto_invoke */ ++ struct cryptotstat cs_done; /* crypto_invoke -> crypto_done */ ++ struct cryptotstat cs_cb; /* crypto_done -> callback */ ++ struct cryptotstat cs_finis; /* callback -> callback return */ ++ ++ u_int32_t cs_drops; /* crypto ops dropped due to congestion */ ++}; ++ ++#ifdef __KERNEL__ ++ ++/* Standard initialization structure beginning */ ++struct cryptoini { ++ int cri_alg; /* Algorithm to use */ ++ int cri_klen; /* Key length, in bits */ ++ int cri_mlen; /* Number of bytes we want from the ++ entire hash. 0 means all. */ ++ caddr_t cri_key; /* key to use */ ++ u_int8_t cri_iv[EALG_MAX_BLOCK_LEN]; /* IV to use */ ++ struct cryptoini *cri_next; ++}; ++ ++/* Describe boundaries of a single crypto operation */ ++struct cryptodesc { ++ int crd_skip; /* How many bytes to ignore from start */ ++ int crd_len; /* How many bytes to process */ ++ int crd_inject; /* Where to inject results, if applicable */ ++ int crd_flags; ++ ++#define CRD_F_ENCRYPT 0x01 /* Set when doing encryption */ ++#define CRD_F_IV_PRESENT 0x02 /* When encrypting, IV is already in ++ place, so don't copy. */ ++#define CRD_F_IV_EXPLICIT 0x04 /* IV explicitly provided */ ++#define CRD_F_DSA_SHA_NEEDED 0x08 /* Compute SHA-1 of buffer for DSA */ ++#define CRD_F_KEY_EXPLICIT 0x10 /* Key explicitly provided */ ++#define CRD_F_COMP 0x0f /* Set when doing compression */ ++ ++ struct cryptoini CRD_INI; /* Initialization/context data */ ++#define crd_iv CRD_INI.cri_iv ++#define crd_key CRD_INI.cri_key ++#define crd_alg CRD_INI.cri_alg ++#define crd_klen CRD_INI.cri_klen ++#define crd_mlen CRD_INI.cri_mlen ++ ++ struct cryptodesc *crd_next; ++}; ++ ++/* Structure describing complete operation */ ++struct cryptop { ++ struct list_head crp_next; ++ wait_queue_head_t crp_waitq; ++ ++ u_int64_t crp_sid; /* Session ID */ ++ int crp_ilen; /* Input data total length */ ++ int crp_olen; /* Result total length */ ++ ++ int crp_etype; /* ++ * Error type (zero means no error). ++ * All error codes except EAGAIN ++ * indicate possible data corruption (as in, ++ * the data have been touched). On all ++ * errors, the crp_sid may have changed ++ * (reset to a new one), so the caller ++ * should always check and use the new ++ * value on future requests. ++ */ ++ int crp_flags; ++ ++#define CRYPTO_F_SKBUF 0x0001 /* Input/output are skbuf chains */ ++#define CRYPTO_F_IOV 0x0002 /* Input/output are uio */ ++#define CRYPTO_F_REL 0x0004 /* Must return data in same place */ ++#define CRYPTO_F_BATCH 0x0008 /* Batch op if possible */ ++#define CRYPTO_F_CBIMM 0x0010 /* Do callback immediately */ ++#define CRYPTO_F_DONE 0x0020 /* Operation completed */ ++#define CRYPTO_F_CBIFSYNC 0x0040 /* Do CBIMM if op is synchronous */ ++ ++ caddr_t crp_buf; /* Data to be processed */ ++ caddr_t crp_opaque; /* Opaque pointer, passed along */ ++ struct cryptodesc *crp_desc; /* Linked list of processing descriptors */ ++ ++ int (*crp_callback)(struct cryptop *); /* Callback function */ ++}; ++ ++#define CRYPTO_BUF_CONTIG 0x0 ++#define CRYPTO_BUF_IOV 0x1 ++#define CRYPTO_BUF_SKBUF 0x2 ++ ++#define CRYPTO_OP_DECRYPT 0x0 ++#define CRYPTO_OP_ENCRYPT 0x1 ++ ++/* ++ * Hints passed to process methods. ++ */ ++#define CRYPTO_HINT_MORE 0x1 /* more ops coming shortly */ ++ ++struct cryptkop { ++ struct list_head krp_next; ++ wait_queue_head_t krp_waitq; ++ ++ int krp_flags; ++#define CRYPTO_KF_DONE 0x0001 /* Operation completed */ ++#define CRYPTO_KF_CBIMM 0x0002 /* Do callback immediately */ ++ ++ u_int krp_op; /* ie. CRK_MOD_EXP or other */ ++ u_int krp_status; /* return status */ ++ u_short krp_iparams; /* # of input parameters */ ++ u_short krp_oparams; /* # of output parameters */ ++ u_int krp_crid; /* desired device, etc. */ ++ u_int32_t krp_hid; ++ struct crparam krp_param[CRK_MAXPARAM]; /* kvm */ ++ int (*krp_callback)(struct cryptkop *); ++}; ++ ++#include ++ ++/* ++ * Session ids are 64 bits. The lower 32 bits contain a "local id" which ++ * is a driver-private session identifier. The upper 32 bits contain a ++ * "hardware id" used by the core crypto code to identify the driver and ++ * a copy of the driver's capabilities that can be used by client code to ++ * optimize operation. ++ */ ++#define CRYPTO_SESID2HID(_sid) (((_sid) >> 32) & 0x00ffffff) ++#define CRYPTO_SESID2CAPS(_sid) (((_sid) >> 32) & 0xff000000) ++#define CRYPTO_SESID2LID(_sid) (((u_int32_t) (_sid)) & 0xffffffff) ++ ++extern int crypto_newsession(u_int64_t *sid, struct cryptoini *cri, int hard); ++extern int crypto_freesession(u_int64_t sid); ++#define CRYPTOCAP_F_HARDWARE CRYPTO_FLAG_HARDWARE ++#define CRYPTOCAP_F_SOFTWARE CRYPTO_FLAG_SOFTWARE ++#define CRYPTOCAP_F_SYNC 0x04000000 /* operates synchronously */ ++extern int32_t crypto_get_driverid(device_t dev, int flags); ++extern int crypto_find_driver(const char *); ++extern device_t crypto_find_device_byhid(int hid); ++extern int crypto_getcaps(int hid); ++extern int crypto_register(u_int32_t driverid, int alg, u_int16_t maxoplen, ++ u_int32_t flags); ++extern int crypto_kregister(u_int32_t, int, u_int32_t); ++extern int crypto_unregister(u_int32_t driverid, int alg); ++extern int crypto_unregister_all(u_int32_t driverid); ++extern int crypto_dispatch(struct cryptop *crp); ++extern int crypto_kdispatch(struct cryptkop *); ++#define CRYPTO_SYMQ 0x1 ++#define CRYPTO_ASYMQ 0x2 ++extern int crypto_unblock(u_int32_t, int); ++extern void crypto_done(struct cryptop *crp); ++extern void crypto_kdone(struct cryptkop *); ++extern int crypto_getfeat(int *); ++ ++extern void crypto_freereq(struct cryptop *crp); ++extern struct cryptop *crypto_getreq(int num); ++ ++extern int crypto_usercrypto; /* userland may do crypto requests */ ++extern int crypto_userasymcrypto; /* userland may do asym crypto reqs */ ++extern int crypto_devallowsoft; /* only use hardware crypto */ ++ ++/* ++ * random number support, crypto_unregister_all will unregister ++ */ ++extern int crypto_rregister(u_int32_t driverid, ++ int (*read_random)(void *arg, u_int32_t *buf, int len), void *arg); ++extern int crypto_runregister_all(u_int32_t driverid); ++ ++/* ++ * Crypto-related utility routines used mainly by drivers. ++ * ++ * XXX these don't really belong here; but for now they're ++ * kept apart from the rest of the system. ++ */ ++struct uio; ++extern void cuio_copydata(struct uio* uio, int off, int len, caddr_t cp); ++extern void cuio_copyback(struct uio* uio, int off, int len, caddr_t cp); ++extern struct iovec *cuio_getptr(struct uio *uio, int loc, int *off); ++ ++extern void crypto_copyback(int flags, caddr_t buf, int off, int size, ++ caddr_t in); ++extern void crypto_copydata(int flags, caddr_t buf, int off, int size, ++ caddr_t out); ++extern int crypto_apply(int flags, caddr_t buf, int off, int len, ++ int (*f)(void *, void *, u_int), void *arg); ++ ++#endif /* __KERNEL__ */ ++#endif /* _CRYPTO_CRYPTO_H_ */ +diff -Nur linux-3.0.4.orig/crypto/ocf/cryptosoft.c linux-3.0.4/crypto/ocf/cryptosoft.c +--- linux-3.0.4.orig/crypto/ocf/cryptosoft.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/cryptosoft.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,1320 @@ ++/* ++ * An OCF module that uses the linux kernel cryptoapi, based on the ++ * original cryptosoft for BSD by Angelos D. Keromytis (angelos@cis.upenn.edu) ++ * but is mostly unrecognisable, ++ * ++ * Written by David McCullough ++ * Copyright (C) 2004-2011 David McCullough ++ * Copyright (C) 2004-2005 Intel Corporation. ++ * ++ * LICENSE TERMS ++ * ++ * The free distribution and use of this software in both source and binary ++ * form is allowed (with or without changes) provided that: ++ * ++ * 1. distributions of this source code include the above copyright ++ * notice, this list of conditions and the following disclaimer; ++ * ++ * 2. distributions in binary form include the above copyright ++ * notice, this list of conditions and the following disclaimer ++ * in the documentation and/or other associated materials; ++ * ++ * 3. the copyright holder's name is not used to endorse products ++ * built using this software without specific written permission. ++ * ++ * ALTERNATIVELY, provided that this notice is retained in full, this product ++ * may be distributed under the terms of the GNU General Public License (GPL), ++ * in which case the provisions of the GPL apply INSTEAD OF those given above. ++ * ++ * DISCLAIMER ++ * ++ * This software is provided 'as is' with no explicit or implied warranties ++ * in respect of its properties, including, but not limited to, correctness ++ * and/or fitness for purpose. ++ * --------------------------------------------------------------------------- ++ */ ++ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,10) ++#include ++#endif ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29) ++#include ++#endif ++ ++#include ++#include ++ ++struct { ++ softc_device_decl sc_dev; ++} swcr_softc; ++ ++#define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK) ++ ++#define SW_TYPE_CIPHER 0x01 ++#define SW_TYPE_HMAC 0x02 ++#define SW_TYPE_HASH 0x04 ++#define SW_TYPE_COMP 0x08 ++#define SW_TYPE_BLKCIPHER 0x10 ++#define SW_TYPE_ALG_MASK 0x1f ++ ++#define SW_TYPE_ASYNC 0x8000 ++ ++#define SW_TYPE_INUSE 0x10000000 ++ ++/* We change some of the above if we have an async interface */ ++ ++#define SW_TYPE_ALG_AMASK (SW_TYPE_ALG_MASK | SW_TYPE_ASYNC) ++ ++#define SW_TYPE_ABLKCIPHER (SW_TYPE_BLKCIPHER | SW_TYPE_ASYNC) ++#define SW_TYPE_AHASH (SW_TYPE_HASH | SW_TYPE_ASYNC) ++#define SW_TYPE_AHMAC (SW_TYPE_HMAC | SW_TYPE_ASYNC) ++ ++#define SCATTERLIST_MAX 16 ++ ++struct swcr_data { ++ struct work_struct workq; ++ int sw_type; ++ int sw_alg; ++ struct crypto_tfm *sw_tfm; ++ spinlock_t sw_tfm_lock; ++ union { ++ struct { ++ char *sw_key; ++ int sw_klen; ++ int sw_mlen; ++ } hmac; ++ void *sw_comp_buf; ++ } u; ++ struct swcr_data *sw_next; ++}; ++ ++struct swcr_req { ++ struct swcr_data *sw_head; ++ struct swcr_data *sw; ++ struct cryptop *crp; ++ struct cryptodesc *crd; ++ struct scatterlist sg[SCATTERLIST_MAX]; ++ unsigned char iv[EALG_MAX_BLOCK_LEN]; ++ char result[HASH_MAX_LEN]; ++ void *crypto_req; ++}; ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) ++static kmem_cache_t *swcr_req_cache; ++#else ++static struct kmem_cache *swcr_req_cache; ++#endif ++ ++#ifndef CRYPTO_TFM_MODE_CBC ++/* ++ * As of linux-2.6.21 this is no longer defined, and presumably no longer ++ * needed to be passed into the crypto core code. ++ */ ++#define CRYPTO_TFM_MODE_CBC 0 ++#define CRYPTO_TFM_MODE_ECB 0 ++#endif ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) ++ /* ++ * Linux 2.6.19 introduced a new Crypto API, setup macro's to convert new ++ * API into old API. ++ */ ++ ++ /* Symmetric/Block Cipher */ ++ struct blkcipher_desc ++ { ++ struct crypto_tfm *tfm; ++ void *info; ++ }; ++ #define ecb(X) #X , CRYPTO_TFM_MODE_ECB ++ #define cbc(X) #X , CRYPTO_TFM_MODE_CBC ++ #define crypto_has_blkcipher(X, Y, Z) crypto_alg_available(X, 0) ++ #define crypto_blkcipher_cast(X) X ++ #define crypto_blkcipher_tfm(X) X ++ #define crypto_alloc_blkcipher(X, Y, Z) crypto_alloc_tfm(X, mode) ++ #define crypto_blkcipher_ivsize(X) crypto_tfm_alg_ivsize(X) ++ #define crypto_blkcipher_blocksize(X) crypto_tfm_alg_blocksize(X) ++ #define crypto_blkcipher_setkey(X, Y, Z) crypto_cipher_setkey(X, Y, Z) ++ #define crypto_blkcipher_encrypt_iv(W, X, Y, Z) \ ++ crypto_cipher_encrypt_iv((W)->tfm, X, Y, Z, (u8 *)((W)->info)) ++ #define crypto_blkcipher_decrypt_iv(W, X, Y, Z) \ ++ crypto_cipher_decrypt_iv((W)->tfm, X, Y, Z, (u8 *)((W)->info)) ++ #define crypto_blkcipher_set_flags(x, y) /* nop */ ++ #define crypto_free_blkcipher(x) crypto_free_tfm(x) ++ #define crypto_free_comp crypto_free_tfm ++ #define crypto_free_hash crypto_free_tfm ++ ++ /* Hash/HMAC/Digest */ ++ struct hash_desc ++ { ++ struct crypto_tfm *tfm; ++ }; ++ #define hmac(X) #X , 0 ++ #define crypto_has_hash(X, Y, Z) crypto_alg_available(X, 0) ++ #define crypto_hash_cast(X) X ++ #define crypto_hash_tfm(X) X ++ #define crypto_alloc_hash(X, Y, Z) crypto_alloc_tfm(X, mode) ++ #define crypto_hash_digestsize(X) crypto_tfm_alg_digestsize(X) ++ #define crypto_hash_digest(W, X, Y, Z) \ ++ crypto_digest_digest((W)->tfm, X, sg_num, Z) ++ ++ /* Asymmetric Cipher */ ++ #define crypto_has_cipher(X, Y, Z) crypto_alg_available(X, 0) ++ ++ /* Compression */ ++ #define crypto_has_comp(X, Y, Z) crypto_alg_available(X, 0) ++ #define crypto_comp_tfm(X) X ++ #define crypto_comp_cast(X) X ++ #define crypto_alloc_comp(X, Y, Z) crypto_alloc_tfm(X, mode) ++ #define plain(X) #X , 0 ++#else ++ #define ecb(X) "ecb(" #X ")" , 0 ++ #define cbc(X) "cbc(" #X ")" , 0 ++ #define hmac(X) "hmac(" #X ")" , 0 ++ #define plain(X) #X , 0 ++#endif /* if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) */ ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22) ++/* no ablkcipher in older kernels */ ++#define crypto_alloc_ablkcipher(a,b,c) (NULL) ++#define crypto_ablkcipher_tfm(x) ((struct crypto_tfm *)(x)) ++#define crypto_ablkcipher_set_flags(a, b) /* nop */ ++#define crypto_ablkcipher_setkey(x, y, z) (-EINVAL) ++#define crypto_has_ablkcipher(a,b,c) (0) ++#else ++#define HAVE_ABLKCIPHER ++#endif ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,32) ++/* no ahash in older kernels */ ++#define crypto_ahash_tfm(x) ((struct crypto_tfm *)(x)) ++#define crypto_alloc_ahash(a,b,c) (NULL) ++#define crypto_ahash_digestsize(x) 0 ++#else ++#define HAVE_AHASH ++#endif ++ ++struct crypto_details { ++ char *alg_name; ++ int mode; ++ int sw_type; ++}; ++ ++static struct crypto_details crypto_details[] = { ++ [CRYPTO_DES_CBC] = { cbc(des), SW_TYPE_BLKCIPHER, }, ++ [CRYPTO_3DES_CBC] = { cbc(des3_ede), SW_TYPE_BLKCIPHER, }, ++ [CRYPTO_BLF_CBC] = { cbc(blowfish), SW_TYPE_BLKCIPHER, }, ++ [CRYPTO_CAST_CBC] = { cbc(cast5), SW_TYPE_BLKCIPHER, }, ++ [CRYPTO_SKIPJACK_CBC] = { cbc(skipjack), SW_TYPE_BLKCIPHER, }, ++ [CRYPTO_MD5_HMAC] = { hmac(md5), SW_TYPE_HMAC, }, ++ [CRYPTO_SHA1_HMAC] = { hmac(sha1), SW_TYPE_HMAC, }, ++ [CRYPTO_RIPEMD160_HMAC] = { hmac(ripemd160), SW_TYPE_HMAC, }, ++ [CRYPTO_MD5_KPDK] = { plain(md5-kpdk), SW_TYPE_HASH, }, ++ [CRYPTO_SHA1_KPDK] = { plain(sha1-kpdk), SW_TYPE_HASH, }, ++ [CRYPTO_AES_CBC] = { cbc(aes), SW_TYPE_BLKCIPHER, }, ++ [CRYPTO_ARC4] = { ecb(arc4), SW_TYPE_BLKCIPHER, }, ++ [CRYPTO_MD5] = { plain(md5), SW_TYPE_HASH, }, ++ [CRYPTO_SHA1] = { plain(sha1), SW_TYPE_HASH, }, ++ [CRYPTO_NULL_HMAC] = { hmac(digest_null), SW_TYPE_HMAC, }, ++ [CRYPTO_NULL_CBC] = { cbc(cipher_null), SW_TYPE_BLKCIPHER, }, ++ [CRYPTO_DEFLATE_COMP] = { plain(deflate), SW_TYPE_COMP, }, ++ [CRYPTO_SHA2_256_HMAC] = { hmac(sha256), SW_TYPE_HMAC, }, ++ [CRYPTO_SHA2_384_HMAC] = { hmac(sha384), SW_TYPE_HMAC, }, ++ [CRYPTO_SHA2_512_HMAC] = { hmac(sha512), SW_TYPE_HMAC, }, ++ [CRYPTO_CAMELLIA_CBC] = { cbc(camellia), SW_TYPE_BLKCIPHER, }, ++ [CRYPTO_SHA2_256] = { plain(sha256), SW_TYPE_HASH, }, ++ [CRYPTO_SHA2_384] = { plain(sha384), SW_TYPE_HASH, }, ++ [CRYPTO_SHA2_512] = { plain(sha512), SW_TYPE_HASH, }, ++ [CRYPTO_RIPEMD160] = { plain(ripemd160), SW_TYPE_HASH, }, ++}; ++ ++int32_t swcr_id = -1; ++module_param(swcr_id, int, 0444); ++MODULE_PARM_DESC(swcr_id, "Read-Only OCF ID for cryptosoft driver"); ++ ++int swcr_fail_if_compression_grows = 1; ++module_param(swcr_fail_if_compression_grows, int, 0644); ++MODULE_PARM_DESC(swcr_fail_if_compression_grows, ++ "Treat compression that results in more data as a failure"); ++ ++int swcr_no_ahash = 0; ++module_param(swcr_no_ahash, int, 0644); ++MODULE_PARM_DESC(swcr_no_ahash, ++ "Do not use async hash/hmac even if available"); ++ ++int swcr_no_ablk = 0; ++module_param(swcr_no_ablk, int, 0644); ++MODULE_PARM_DESC(swcr_no_ablk, ++ "Do not use async blk ciphers even if available"); ++ ++static struct swcr_data **swcr_sessions = NULL; ++static u_int32_t swcr_sesnum = 0; ++ ++static int swcr_process(device_t, struct cryptop *, int); ++static int swcr_newsession(device_t, u_int32_t *, struct cryptoini *); ++static int swcr_freesession(device_t, u_int64_t); ++ ++static device_method_t swcr_methods = { ++ /* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, swcr_newsession), ++ DEVMETHOD(cryptodev_freesession,swcr_freesession), ++ DEVMETHOD(cryptodev_process, swcr_process), ++}; ++ ++#define debug swcr_debug ++int swcr_debug = 0; ++module_param(swcr_debug, int, 0644); ++MODULE_PARM_DESC(swcr_debug, "Enable debug"); ++ ++static void swcr_process_req(struct swcr_req *req); ++ ++/* ++ * somethings just need to be run with user context no matter whether ++ * the kernel compression libs use vmalloc/vfree for example. ++ */ ++ ++typedef struct { ++ struct work_struct wq; ++ void (*func)(void *arg); ++ void *arg; ++} execute_later_t; ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++static void ++doing_it_now(struct work_struct *wq) ++{ ++ execute_later_t *w = container_of(wq, execute_later_t, wq); ++ (w->func)(w->arg); ++ kfree(w); ++} ++#else ++static void ++doing_it_now(void *arg) ++{ ++ execute_later_t *w = (execute_later_t *) arg; ++ (w->func)(w->arg); ++ kfree(w); ++} ++#endif ++ ++static void ++execute_later(void (fn)(void *), void *arg) ++{ ++ execute_later_t *w; ++ ++ w = (execute_later_t *) kmalloc(sizeof(execute_later_t), SLAB_ATOMIC); ++ if (w) { ++ memset(w, '\0', sizeof(w)); ++ w->func = fn; ++ w->arg = arg; ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++ INIT_WORK(&w->wq, doing_it_now); ++#else ++ INIT_WORK(&w->wq, doing_it_now, w); ++#endif ++ schedule_work(&w->wq); ++ } ++} ++ ++/* ++ * Generate a new software session. ++ */ ++static int ++swcr_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) ++{ ++ struct swcr_data **swd; ++ u_int32_t i; ++ int error; ++ char *algo; ++ int mode; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (sid == NULL || cri == NULL) { ++ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ if (swcr_sessions) { ++ for (i = 1; i < swcr_sesnum; i++) ++ if (swcr_sessions[i] == NULL) ++ break; ++ } else ++ i = 1; /* NB: to silence compiler warning */ ++ ++ if (swcr_sessions == NULL || i == swcr_sesnum) { ++ if (swcr_sessions == NULL) { ++ i = 1; /* We leave swcr_sessions[0] empty */ ++ swcr_sesnum = CRYPTO_SW_SESSIONS; ++ } else ++ swcr_sesnum *= 2; ++ ++ swd = kmalloc(swcr_sesnum * sizeof(struct swcr_data *), SLAB_ATOMIC); ++ if (swd == NULL) { ++ /* Reset session number */ ++ if (swcr_sesnum == CRYPTO_SW_SESSIONS) ++ swcr_sesnum = 0; ++ else ++ swcr_sesnum /= 2; ++ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ memset(swd, 0, swcr_sesnum * sizeof(struct swcr_data *)); ++ ++ /* Copy existing sessions */ ++ if (swcr_sessions) { ++ memcpy(swd, swcr_sessions, ++ (swcr_sesnum / 2) * sizeof(struct swcr_data *)); ++ kfree(swcr_sessions); ++ } ++ ++ swcr_sessions = swd; ++ } ++ ++ swd = &swcr_sessions[i]; ++ *sid = i; ++ ++ while (cri) { ++ *swd = (struct swcr_data *) kmalloc(sizeof(struct swcr_data), ++ SLAB_ATOMIC); ++ if (*swd == NULL) { ++ swcr_freesession(NULL, i); ++ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ memset(*swd, 0, sizeof(struct swcr_data)); ++ ++ if (cri->cri_alg < 0 || ++ cri->cri_alg>=sizeof(crypto_details)/sizeof(crypto_details[0])){ ++ printk("cryptosoft: Unknown algorithm 0x%x\n", cri->cri_alg); ++ swcr_freesession(NULL, i); ++ return EINVAL; ++ } ++ ++ algo = crypto_details[cri->cri_alg].alg_name; ++ if (!algo || !*algo) { ++ printk("cryptosoft: Unsupported algorithm 0x%x\n", cri->cri_alg); ++ swcr_freesession(NULL, i); ++ return EINVAL; ++ } ++ ++ mode = crypto_details[cri->cri_alg].mode; ++ (*swd)->sw_type = crypto_details[cri->cri_alg].sw_type; ++ (*swd)->sw_alg = cri->cri_alg; ++ ++ spin_lock_init(&(*swd)->sw_tfm_lock); ++ ++ /* Algorithm specific configuration */ ++ switch (cri->cri_alg) { ++ case CRYPTO_NULL_CBC: ++ cri->cri_klen = 0; /* make it work with crypto API */ ++ break; ++ default: ++ break; ++ } ++ ++ if ((*swd)->sw_type & SW_TYPE_BLKCIPHER) { ++ dprintk("%s crypto_alloc_*blkcipher(%s, 0x%x)\n", __FUNCTION__, ++ algo, mode); ++ ++ /* try async first */ ++ (*swd)->sw_tfm = swcr_no_ablk ? NULL : ++ crypto_ablkcipher_tfm(crypto_alloc_ablkcipher(algo, 0, 0)); ++ if ((*swd)->sw_tfm && !IS_ERR((*swd)->sw_tfm)) { ++ dprintk("%s %s cipher is async\n", __FUNCTION__, algo); ++ (*swd)->sw_type |= SW_TYPE_ASYNC; ++ } else { ++ (*swd)->sw_tfm = crypto_blkcipher_tfm( ++ crypto_alloc_blkcipher(algo, 0, CRYPTO_ALG_ASYNC)); ++ if ((*swd)->sw_tfm && !IS_ERR((*swd)->sw_tfm)) ++ dprintk("%s %s cipher is sync\n", __FUNCTION__, algo); ++ } ++ if (!(*swd)->sw_tfm || IS_ERR((*swd)->sw_tfm)) { ++ int err; ++ dprintk("cryptosoft: crypto_alloc_blkcipher failed(%s, 0x%x)\n", ++ algo,mode); ++ err = IS_ERR((*swd)->sw_tfm) ? -(PTR_ERR((*swd)->sw_tfm)) : EINVAL; ++ (*swd)->sw_tfm = NULL; /* ensure NULL */ ++ swcr_freesession(NULL, i); ++ return err; ++ } ++ ++ if (debug) { ++ dprintk("%s key:cri->cri_klen=%d,(cri->cri_klen + 7)/8=%d", ++ __FUNCTION__, cri->cri_klen, (cri->cri_klen + 7) / 8); ++ for (i = 0; i < (cri->cri_klen + 7) / 8; i++) ++ dprintk("%s0x%x", (i % 8) ? " " : "\n ", ++ cri->cri_key[i] & 0xff); ++ dprintk("\n"); ++ } ++ if ((*swd)->sw_type & SW_TYPE_ASYNC) { ++ /* OCF doesn't enforce keys */ ++ crypto_ablkcipher_set_flags( ++ __crypto_ablkcipher_cast((*swd)->sw_tfm), ++ CRYPTO_TFM_REQ_WEAK_KEY); ++ error = crypto_ablkcipher_setkey( ++ __crypto_ablkcipher_cast((*swd)->sw_tfm), ++ cri->cri_key, (cri->cri_klen + 7) / 8); ++ } else { ++ /* OCF doesn't enforce keys */ ++ crypto_blkcipher_set_flags( ++ crypto_blkcipher_cast((*swd)->sw_tfm), ++ CRYPTO_TFM_REQ_WEAK_KEY); ++ error = crypto_blkcipher_setkey( ++ crypto_blkcipher_cast((*swd)->sw_tfm), ++ cri->cri_key, (cri->cri_klen + 7) / 8); ++ } ++ if (error) { ++ printk("cryptosoft: setkey failed %d (crt_flags=0x%x)\n", error, ++ (*swd)->sw_tfm->crt_flags); ++ swcr_freesession(NULL, i); ++ return error; ++ } ++ } else if ((*swd)->sw_type & (SW_TYPE_HMAC | SW_TYPE_HASH)) { ++ dprintk("%s crypto_alloc_*hash(%s, 0x%x)\n", __FUNCTION__, ++ algo, mode); ++ ++ /* try async first */ ++ (*swd)->sw_tfm = swcr_no_ahash ? NULL : ++ crypto_ahash_tfm(crypto_alloc_ahash(algo, 0, 0)); ++ if ((*swd)->sw_tfm) { ++ dprintk("%s %s hash is async\n", __FUNCTION__, algo); ++ (*swd)->sw_type |= SW_TYPE_ASYNC; ++ } else { ++ dprintk("%s %s hash is sync\n", __FUNCTION__, algo); ++ (*swd)->sw_tfm = crypto_hash_tfm( ++ crypto_alloc_hash(algo, 0, CRYPTO_ALG_ASYNC)); ++ } ++ ++ if (!(*swd)->sw_tfm) { ++ dprintk("cryptosoft: crypto_alloc_hash failed(%s,0x%x)\n", ++ algo, mode); ++ swcr_freesession(NULL, i); ++ return EINVAL; ++ } ++ ++ (*swd)->u.hmac.sw_klen = (cri->cri_klen + 7) / 8; ++ (*swd)->u.hmac.sw_key = (char *)kmalloc((*swd)->u.hmac.sw_klen, ++ SLAB_ATOMIC); ++ if ((*swd)->u.hmac.sw_key == NULL) { ++ swcr_freesession(NULL, i); ++ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ memcpy((*swd)->u.hmac.sw_key, cri->cri_key, (*swd)->u.hmac.sw_klen); ++ if (cri->cri_mlen) { ++ (*swd)->u.hmac.sw_mlen = cri->cri_mlen; ++ } else if ((*swd)->sw_type & SW_TYPE_ASYNC) { ++ (*swd)->u.hmac.sw_mlen = crypto_ahash_digestsize( ++ __crypto_ahash_cast((*swd)->sw_tfm)); ++ } else { ++ (*swd)->u.hmac.sw_mlen = crypto_hash_digestsize( ++ crypto_hash_cast((*swd)->sw_tfm)); ++ } ++ } else if ((*swd)->sw_type & SW_TYPE_COMP) { ++ (*swd)->sw_tfm = crypto_comp_tfm( ++ crypto_alloc_comp(algo, 0, CRYPTO_ALG_ASYNC)); ++ if (!(*swd)->sw_tfm) { ++ dprintk("cryptosoft: crypto_alloc_comp failed(%s,0x%x)\n", ++ algo, mode); ++ swcr_freesession(NULL, i); ++ return EINVAL; ++ } ++ (*swd)->u.sw_comp_buf = kmalloc(CRYPTO_MAX_DATA_LEN, SLAB_ATOMIC); ++ if ((*swd)->u.sw_comp_buf == NULL) { ++ swcr_freesession(NULL, i); ++ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ } else { ++ printk("cryptosoft: Unhandled sw_type %d\n", (*swd)->sw_type); ++ swcr_freesession(NULL, i); ++ return EINVAL; ++ } ++ ++ cri = cri->cri_next; ++ swd = &((*swd)->sw_next); ++ } ++ return 0; ++} ++ ++/* ++ * Free a session. ++ */ ++static int ++swcr_freesession(device_t dev, u_int64_t tid) ++{ ++ struct swcr_data *swd; ++ u_int32_t sid = CRYPTO_SESID2LID(tid); ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (sid > swcr_sesnum || swcr_sessions == NULL || ++ swcr_sessions[sid] == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return(EINVAL); ++ } ++ ++ /* Silently accept and return */ ++ if (sid == 0) ++ return(0); ++ ++ while ((swd = swcr_sessions[sid]) != NULL) { ++ swcr_sessions[sid] = swd->sw_next; ++ if (swd->sw_tfm) { ++ switch (swd->sw_type & SW_TYPE_ALG_AMASK) { ++#ifdef HAVE_AHASH ++ case SW_TYPE_AHMAC: ++ case SW_TYPE_AHASH: ++ crypto_free_ahash(__crypto_ahash_cast(swd->sw_tfm)); ++ break; ++#endif ++#ifdef HAVE_ABLKCIPHER ++ case SW_TYPE_ABLKCIPHER: ++ crypto_free_ablkcipher(__crypto_ablkcipher_cast(swd->sw_tfm)); ++ break; ++#endif ++ case SW_TYPE_BLKCIPHER: ++ crypto_free_blkcipher(crypto_blkcipher_cast(swd->sw_tfm)); ++ break; ++ case SW_TYPE_HMAC: ++ case SW_TYPE_HASH: ++ crypto_free_hash(crypto_hash_cast(swd->sw_tfm)); ++ break; ++ case SW_TYPE_COMP: ++ if (in_interrupt()) ++ execute_later((void (*)(void *))crypto_free_comp, (void *)crypto_comp_cast(swd->sw_tfm)); ++ else ++ crypto_free_comp(crypto_comp_cast(swd->sw_tfm)); ++ break; ++ default: ++ crypto_free_tfm(swd->sw_tfm); ++ break; ++ } ++ swd->sw_tfm = NULL; ++ } ++ if (swd->sw_type & SW_TYPE_COMP) { ++ if (swd->u.sw_comp_buf) ++ kfree(swd->u.sw_comp_buf); ++ } else { ++ if (swd->u.hmac.sw_key) ++ kfree(swd->u.hmac.sw_key); ++ } ++ kfree(swd); ++ } ++ return 0; ++} ++ ++static void swcr_process_req_complete(struct swcr_req *req) ++{ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (req->sw->sw_type & SW_TYPE_INUSE) { ++ unsigned long flags; ++ spin_lock_irqsave(&req->sw->sw_tfm_lock, flags); ++ req->sw->sw_type &= ~SW_TYPE_INUSE; ++ spin_unlock_irqrestore(&req->sw->sw_tfm_lock, flags); ++ } ++ ++ if (req->crp->crp_etype) ++ goto done; ++ ++ switch (req->sw->sw_type & SW_TYPE_ALG_AMASK) { ++#if defined(HAVE_AHASH) ++ case SW_TYPE_AHMAC: ++ case SW_TYPE_AHASH: ++ crypto_copyback(req->crp->crp_flags, req->crp->crp_buf, ++ req->crd->crd_inject, req->sw->u.hmac.sw_mlen, req->result); ++ ahash_request_free(req->crypto_req); ++ break; ++#endif ++#if defined(HAVE_ABLKCIPHER) ++ case SW_TYPE_ABLKCIPHER: ++ ablkcipher_request_free(req->crypto_req); ++ break; ++#endif ++ case SW_TYPE_CIPHER: ++ case SW_TYPE_HMAC: ++ case SW_TYPE_HASH: ++ case SW_TYPE_COMP: ++ case SW_TYPE_BLKCIPHER: ++ break; ++ default: ++ req->crp->crp_etype = EINVAL; ++ goto done; ++ } ++ ++ req->crd = req->crd->crd_next; ++ if (req->crd) { ++ swcr_process_req(req); ++ return; ++ } ++ ++done: ++ dprintk("%s crypto_done %p\n", __FUNCTION__, req); ++ crypto_done(req->crp); ++ kmem_cache_free(swcr_req_cache, req); ++} ++ ++#if defined(HAVE_ABLKCIPHER) || defined(HAVE_AHASH) ++static void swcr_process_callback(struct crypto_async_request *creq, int err) ++{ ++ struct swcr_req *req = creq->data; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (err) { ++ if (err == -EINPROGRESS) ++ return; ++ dprintk("%s() fail %d\n", __FUNCTION__, -err); ++ req->crp->crp_etype = -err; ++ } ++ ++ swcr_process_req_complete(req); ++} ++#endif /* defined(HAVE_ABLKCIPHER) || defined(HAVE_AHASH) */ ++ ++ ++static void swcr_process_req(struct swcr_req *req) ++{ ++ struct swcr_data *sw; ++ struct cryptop *crp = req->crp; ++ struct cryptodesc *crd = req->crd; ++ struct sk_buff *skb = (struct sk_buff *) crp->crp_buf; ++ struct uio *uiop = (struct uio *) crp->crp_buf; ++ int sg_num, sg_len, skip; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ /* ++ * Find the crypto context. ++ * ++ * XXX Note that the logic here prevents us from having ++ * XXX the same algorithm multiple times in a session ++ * XXX (or rather, we can but it won't give us the right ++ * XXX results). To do that, we'd need some way of differentiating ++ * XXX between the various instances of an algorithm (so we can ++ * XXX locate the correct crypto context). ++ */ ++ for (sw = req->sw_head; sw && sw->sw_alg != crd->crd_alg; sw = sw->sw_next) ++ ; ++ ++ /* No such context ? */ ++ if (sw == NULL) { ++ crp->crp_etype = EINVAL; ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ goto done; ++ } ++ ++ /* ++ * for some types we need to ensure only one user as info is stored in ++ * the tfm during an operation that can get corrupted ++ */ ++ switch (sw->sw_type & SW_TYPE_ALG_AMASK) { ++#ifdef HAVE_AHASH ++ case SW_TYPE_AHMAC: ++ case SW_TYPE_AHASH: ++#endif ++ case SW_TYPE_HMAC: ++ case SW_TYPE_HASH: { ++ unsigned long flags; ++ spin_lock_irqsave(&sw->sw_tfm_lock, flags); ++ if (sw->sw_type & SW_TYPE_INUSE) { ++ spin_unlock_irqrestore(&sw->sw_tfm_lock, flags); ++ execute_later((void (*)(void *))swcr_process_req, (void *)req); ++ return; ++ } ++ sw->sw_type |= SW_TYPE_INUSE; ++ spin_unlock_irqrestore(&sw->sw_tfm_lock, flags); ++ } break; ++ } ++ ++ req->sw = sw; ++ skip = crd->crd_skip; ++ ++ /* ++ * setup the SG list skip from the start of the buffer ++ */ ++ memset(req->sg, 0, sizeof(req->sg)); ++ sg_init_table(req->sg, SCATTERLIST_MAX); ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ int i, len; ++ ++ sg_num = 0; ++ sg_len = 0; ++ ++ if (skip < skb_headlen(skb)) { ++ len = skb_headlen(skb) - skip; ++ if (len + sg_len > crd->crd_len) ++ len = crd->crd_len - sg_len; ++ sg_set_page(&req->sg[sg_num], ++ virt_to_page(skb->data + skip), len, ++ offset_in_page(skb->data + skip)); ++ sg_len += len; ++ sg_num++; ++ skip = 0; ++ } else ++ skip -= skb_headlen(skb); ++ ++ for (i = 0; sg_len < crd->crd_len && ++ i < skb_shinfo(skb)->nr_frags && ++ sg_num < SCATTERLIST_MAX; i++) { ++ if (skip < skb_shinfo(skb)->frags[i].size) { ++ len = skb_shinfo(skb)->frags[i].size - skip; ++ if (len + sg_len > crd->crd_len) ++ len = crd->crd_len - sg_len; ++ sg_set_page(&req->sg[sg_num], ++ skb_shinfo(skb)->frags[i].page, ++ len, ++ skb_shinfo(skb)->frags[i].page_offset + skip); ++ sg_len += len; ++ sg_num++; ++ skip = 0; ++ } else ++ skip -= skb_shinfo(skb)->frags[i].size; ++ } ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ int len; ++ ++ sg_len = 0; ++ for (sg_num = 0; sg_len < crd->crd_len && ++ sg_num < uiop->uio_iovcnt && ++ sg_num < SCATTERLIST_MAX; sg_num++) { ++ if (skip <= uiop->uio_iov[sg_num].iov_len) { ++ len = uiop->uio_iov[sg_num].iov_len - skip; ++ if (len + sg_len > crd->crd_len) ++ len = crd->crd_len - sg_len; ++ sg_set_page(&req->sg[sg_num], ++ virt_to_page(uiop->uio_iov[sg_num].iov_base+skip), ++ len, ++ offset_in_page(uiop->uio_iov[sg_num].iov_base+skip)); ++ sg_len += len; ++ skip = 0; ++ } else ++ skip -= uiop->uio_iov[sg_num].iov_len; ++ } ++ } else { ++ sg_len = (crp->crp_ilen - skip); ++ if (sg_len > crd->crd_len) ++ sg_len = crd->crd_len; ++ sg_set_page(&req->sg[0], virt_to_page(crp->crp_buf + skip), ++ sg_len, offset_in_page(crp->crp_buf + skip)); ++ sg_num = 1; ++ } ++ ++ switch (sw->sw_type & SW_TYPE_ALG_AMASK) { ++ ++#ifdef HAVE_AHASH ++ case SW_TYPE_AHMAC: ++ case SW_TYPE_AHASH: ++ { ++ int ret; ++ ++ /* check we have room for the result */ ++ if (crp->crp_ilen - crd->crd_inject < sw->u.hmac.sw_mlen) { ++ dprintk("cryptosoft: EINVAL crp_ilen=%d, len=%d, inject=%d " ++ "digestsize=%d\n", crp->crp_ilen, crd->crd_skip + sg_len, ++ crd->crd_inject, sw->u.hmac.sw_mlen); ++ crp->crp_etype = EINVAL; ++ goto done; ++ } ++ ++ req->crypto_req = ++ ahash_request_alloc(__crypto_ahash_cast(sw->sw_tfm),GFP_ATOMIC); ++ if (!req->crypto_req) { ++ crp->crp_etype = ENOMEM; ++ dprintk("%s,%d: ENOMEM ahash_request_alloc", __FILE__, __LINE__); ++ goto done; ++ } ++ ++ ahash_request_set_callback(req->crypto_req, ++ CRYPTO_TFM_REQ_MAY_BACKLOG, swcr_process_callback, req); ++ ++ memset(req->result, 0, sizeof(req->result)); ++ ++ if (sw->sw_type & SW_TYPE_AHMAC) ++ crypto_ahash_setkey(__crypto_ahash_cast(sw->sw_tfm), ++ sw->u.hmac.sw_key, sw->u.hmac.sw_klen); ++ ahash_request_set_crypt(req->crypto_req, req->sg, req->result, sg_len); ++ ret = crypto_ahash_digest(req->crypto_req); ++ switch (ret) { ++ case -EINPROGRESS: ++ case -EBUSY: ++ return; ++ default: ++ case 0: ++ dprintk("hash OP %s %d\n", ret ? "failed" : "success", ret); ++ crp->crp_etype = ret; ++ goto done; ++ } ++ } break; ++#endif /* HAVE_AHASH */ ++ ++#ifdef HAVE_ABLKCIPHER ++ case SW_TYPE_ABLKCIPHER: { ++ int ret; ++ unsigned char *ivp = req->iv; ++ int ivsize = ++ crypto_ablkcipher_ivsize(__crypto_ablkcipher_cast(sw->sw_tfm)); ++ ++ if (sg_len < crypto_ablkcipher_blocksize( ++ __crypto_ablkcipher_cast(sw->sw_tfm))) { ++ crp->crp_etype = EINVAL; ++ dprintk("%s,%d: EINVAL len %d < %d\n", __FILE__, __LINE__, ++ sg_len, crypto_ablkcipher_blocksize( ++ __crypto_ablkcipher_cast(sw->sw_tfm))); ++ goto done; ++ } ++ ++ if (ivsize > sizeof(req->iv)) { ++ crp->crp_etype = EINVAL; ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ goto done; ++ } ++ ++ req->crypto_req = ablkcipher_request_alloc( ++ __crypto_ablkcipher_cast(sw->sw_tfm), GFP_ATOMIC); ++ if (!req->crypto_req) { ++ crp->crp_etype = ENOMEM; ++ dprintk("%s,%d: ENOMEM ablkcipher_request_alloc", ++ __FILE__, __LINE__); ++ goto done; ++ } ++ ++ ablkcipher_request_set_callback(req->crypto_req, ++ CRYPTO_TFM_REQ_MAY_BACKLOG, swcr_process_callback, req); ++ ++ if (crd->crd_flags & CRD_F_KEY_EXPLICIT) { ++ int i, error; ++ ++ if (debug) { ++ dprintk("%s key:", __FUNCTION__); ++ for (i = 0; i < (crd->crd_klen + 7) / 8; i++) ++ dprintk("%s0x%x", (i % 8) ? " " : "\n ", ++ crd->crd_key[i] & 0xff); ++ dprintk("\n"); ++ } ++ /* OCF doesn't enforce keys */ ++ crypto_ablkcipher_set_flags(__crypto_ablkcipher_cast(sw->sw_tfm), ++ CRYPTO_TFM_REQ_WEAK_KEY); ++ error = crypto_ablkcipher_setkey( ++ __crypto_ablkcipher_cast(sw->sw_tfm), crd->crd_key, ++ (crd->crd_klen + 7) / 8); ++ if (error) { ++ dprintk("cryptosoft: setkey failed %d (crt_flags=0x%x)\n", ++ error, sw->sw_tfm->crt_flags); ++ crp->crp_etype = -error; ++ } ++ } ++ ++ if (crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ ++ ++ if (crd->crd_flags & CRD_F_IV_EXPLICIT) ++ ivp = crd->crd_iv; ++ else ++ get_random_bytes(ivp, ivsize); ++ /* ++ * do we have to copy the IV back to the buffer ? ++ */ ++ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ crd->crd_inject, ivsize, (caddr_t)ivp); ++ } ++ ablkcipher_request_set_crypt(req->crypto_req, req->sg, req->sg, ++ sg_len, ivp); ++ ret = crypto_ablkcipher_encrypt(req->crypto_req); ++ ++ } else { /*decrypt */ ++ ++ if (crd->crd_flags & CRD_F_IV_EXPLICIT) ++ ivp = crd->crd_iv; ++ else ++ crypto_copydata(crp->crp_flags, crp->crp_buf, ++ crd->crd_inject, ivsize, (caddr_t)ivp); ++ ablkcipher_request_set_crypt(req->crypto_req, req->sg, req->sg, ++ sg_len, ivp); ++ ret = crypto_ablkcipher_decrypt(req->crypto_req); ++ } ++ ++ switch (ret) { ++ case -EINPROGRESS: ++ case -EBUSY: ++ return; ++ default: ++ case 0: ++ dprintk("crypto OP %s %d\n", ret ? "failed" : "success", ret); ++ crp->crp_etype = ret; ++ goto done; ++ } ++ } break; ++#endif /* HAVE_ABLKCIPHER */ ++ ++ case SW_TYPE_BLKCIPHER: { ++ unsigned char iv[EALG_MAX_BLOCK_LEN]; ++ unsigned char *ivp = iv; ++ struct blkcipher_desc desc; ++ int ivsize = crypto_blkcipher_ivsize(crypto_blkcipher_cast(sw->sw_tfm)); ++ ++ if (sg_len < crypto_blkcipher_blocksize( ++ crypto_blkcipher_cast(sw->sw_tfm))) { ++ crp->crp_etype = EINVAL; ++ dprintk("%s,%d: EINVAL len %d < %d\n", __FILE__, __LINE__, ++ sg_len, crypto_blkcipher_blocksize( ++ crypto_blkcipher_cast(sw->sw_tfm))); ++ goto done; ++ } ++ ++ if (ivsize > sizeof(iv)) { ++ crp->crp_etype = EINVAL; ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ goto done; ++ } ++ ++ if (crd->crd_flags & CRD_F_KEY_EXPLICIT) { ++ int i, error; ++ ++ if (debug) { ++ dprintk("%s key:", __FUNCTION__); ++ for (i = 0; i < (crd->crd_klen + 7) / 8; i++) ++ dprintk("%s0x%x", (i % 8) ? " " : "\n ", ++ crd->crd_key[i] & 0xff); ++ dprintk("\n"); ++ } ++ /* OCF doesn't enforce keys */ ++ crypto_blkcipher_set_flags(crypto_blkcipher_cast(sw->sw_tfm), ++ CRYPTO_TFM_REQ_WEAK_KEY); ++ error = crypto_blkcipher_setkey( ++ crypto_blkcipher_cast(sw->sw_tfm), crd->crd_key, ++ (crd->crd_klen + 7) / 8); ++ if (error) { ++ dprintk("cryptosoft: setkey failed %d (crt_flags=0x%x)\n", ++ error, sw->sw_tfm->crt_flags); ++ crp->crp_etype = -error; ++ } ++ } ++ ++ memset(&desc, 0, sizeof(desc)); ++ desc.tfm = crypto_blkcipher_cast(sw->sw_tfm); ++ ++ if (crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ ++ ++ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { ++ ivp = crd->crd_iv; ++ } else { ++ get_random_bytes(ivp, ivsize); ++ } ++ /* ++ * do we have to copy the IV back to the buffer ? ++ */ ++ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ crd->crd_inject, ivsize, (caddr_t)ivp); ++ } ++ desc.info = ivp; ++ crypto_blkcipher_encrypt_iv(&desc, req->sg, req->sg, sg_len); ++ ++ } else { /*decrypt */ ++ ++ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { ++ ivp = crd->crd_iv; ++ } else { ++ crypto_copydata(crp->crp_flags, crp->crp_buf, ++ crd->crd_inject, ivsize, (caddr_t)ivp); ++ } ++ desc.info = ivp; ++ crypto_blkcipher_decrypt_iv(&desc, req->sg, req->sg, sg_len); ++ } ++ } break; ++ ++ case SW_TYPE_HMAC: ++ case SW_TYPE_HASH: ++ { ++ char result[HASH_MAX_LEN]; ++ struct hash_desc desc; ++ ++ /* check we have room for the result */ ++ if (crp->crp_ilen - crd->crd_inject < sw->u.hmac.sw_mlen) { ++ dprintk("cryptosoft: EINVAL crp_ilen=%d, len=%d, inject=%d " ++ "digestsize=%d\n", crp->crp_ilen, crd->crd_skip + sg_len, ++ crd->crd_inject, sw->u.hmac.sw_mlen); ++ crp->crp_etype = EINVAL; ++ goto done; ++ } ++ ++ memset(&desc, 0, sizeof(desc)); ++ desc.tfm = crypto_hash_cast(sw->sw_tfm); ++ ++ memset(result, 0, sizeof(result)); ++ ++ if (sw->sw_type & SW_TYPE_HMAC) { ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) ++ crypto_hmac(sw->sw_tfm, sw->u.hmac.sw_key, &sw->u.hmac.sw_klen, ++ req->sg, sg_num, result); ++#else ++ crypto_hash_setkey(desc.tfm, sw->u.hmac.sw_key, ++ sw->u.hmac.sw_klen); ++ crypto_hash_digest(&desc, req->sg, sg_len, result); ++#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) */ ++ ++ } else { /* SW_TYPE_HASH */ ++ crypto_hash_digest(&desc, req->sg, sg_len, result); ++ } ++ ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ crd->crd_inject, sw->u.hmac.sw_mlen, result); ++ } ++ break; ++ ++ case SW_TYPE_COMP: { ++ void *ibuf = NULL; ++ void *obuf = sw->u.sw_comp_buf; ++ int ilen = sg_len, olen = CRYPTO_MAX_DATA_LEN; ++ int ret = 0; ++ ++ /* ++ * we need to use an additional copy if there is more than one ++ * input chunk since the kernel comp routines do not handle ++ * SG yet. Otherwise we just use the input buffer as is. ++ * Rather than allocate another buffer we just split the tmp ++ * buffer we already have. ++ * Perhaps we should just use zlib directly ? ++ */ ++ if (sg_num > 1) { ++ int blk; ++ ++ ibuf = obuf; ++ for (blk = 0; blk < sg_num; blk++) { ++ memcpy(obuf, sg_virt(&req->sg[blk]), ++ req->sg[blk].length); ++ obuf += req->sg[blk].length; ++ } ++ olen -= sg_len; ++ } else ++ ibuf = sg_virt(&req->sg[0]); ++ ++ if (crd->crd_flags & CRD_F_ENCRYPT) { /* compress */ ++ ret = crypto_comp_compress(crypto_comp_cast(sw->sw_tfm), ++ ibuf, ilen, obuf, &olen); ++ if (!ret && olen > crd->crd_len) { ++ dprintk("cryptosoft: ERANGE compress %d into %d\n", ++ crd->crd_len, olen); ++ if (swcr_fail_if_compression_grows) ++ ret = ERANGE; ++ } ++ } else { /* decompress */ ++ ret = crypto_comp_decompress(crypto_comp_cast(sw->sw_tfm), ++ ibuf, ilen, obuf, &olen); ++ if (!ret && (olen + crd->crd_inject) > crp->crp_olen) { ++ dprintk("cryptosoft: ETOOSMALL decompress %d into %d, " ++ "space for %d,at offset %d\n", ++ crd->crd_len, olen, crp->crp_olen, crd->crd_inject); ++ ret = ETOOSMALL; ++ } ++ } ++ if (ret) ++ dprintk("%s,%d: ret = %d\n", __FILE__, __LINE__, ret); ++ ++ /* ++ * on success copy result back, ++ * linux crpyto API returns -errno, we need to fix that ++ */ ++ crp->crp_etype = ret < 0 ? -ret : ret; ++ if (ret == 0) { ++ /* copy back the result and return it's size */ ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ crd->crd_inject, olen, obuf); ++ crp->crp_olen = olen; ++ } ++ } break; ++ ++ default: ++ /* Unknown/unsupported algorithm */ ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ crp->crp_etype = EINVAL; ++ goto done; ++ } ++ ++done: ++ swcr_process_req_complete(req); ++} ++ ++ ++/* ++ * Process a crypto request. ++ */ ++static int ++swcr_process(device_t dev, struct cryptop *crp, int hint) ++{ ++ struct swcr_req *req = NULL; ++ u_int32_t lid; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ /* Sanity check */ ++ if (crp == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ crp->crp_etype = 0; ++ ++ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ crp->crp_etype = EINVAL; ++ goto done; ++ } ++ ++ lid = crp->crp_sid & 0xffffffff; ++ if (lid >= swcr_sesnum || lid == 0 || swcr_sessions == NULL || ++ swcr_sessions[lid] == NULL) { ++ crp->crp_etype = ENOENT; ++ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); ++ goto done; ++ } ++ ++ /* ++ * do some error checking outside of the loop for SKB and IOV processing ++ * this leaves us with valid skb or uiop pointers for later ++ */ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ struct sk_buff *skb = (struct sk_buff *) crp->crp_buf; ++ if (skb_shinfo(skb)->nr_frags >= SCATTERLIST_MAX) { ++ printk("%s,%d: %d nr_frags > SCATTERLIST_MAX", __FILE__, __LINE__, ++ skb_shinfo(skb)->nr_frags); ++ goto done; ++ } ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ struct uio *uiop = (struct uio *) crp->crp_buf; ++ if (uiop->uio_iovcnt > SCATTERLIST_MAX) { ++ printk("%s,%d: %d uio_iovcnt > SCATTERLIST_MAX", __FILE__, __LINE__, ++ uiop->uio_iovcnt); ++ goto done; ++ } ++ } ++ ++ /* ++ * setup a new request ready for queuing ++ */ ++ req = kmem_cache_alloc(swcr_req_cache, SLAB_ATOMIC); ++ if (req == NULL) { ++ dprintk("%s,%d: ENOMEM\n", __FILE__, __LINE__); ++ crp->crp_etype = ENOMEM; ++ goto done; ++ } ++ memset(req, 0, sizeof(*req)); ++ ++ req->sw_head = swcr_sessions[lid]; ++ req->crp = crp; ++ req->crd = crp->crp_desc; ++ ++ swcr_process_req(req); ++ return 0; ++ ++done: ++ crypto_done(crp); ++ if (req) ++ kmem_cache_free(swcr_req_cache, req); ++ return 0; ++} ++ ++ ++static int ++cryptosoft_init(void) ++{ ++ int i, sw_type, mode; ++ char *algo; ++ ++ dprintk("%s(%p)\n", __FUNCTION__, cryptosoft_init); ++ ++ swcr_req_cache = kmem_cache_create("cryptosoft_req", ++ sizeof(struct swcr_req), 0, SLAB_HWCACHE_ALIGN, NULL ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) ++ , NULL ++#endif ++ ); ++ if (!swcr_req_cache) { ++ printk("cryptosoft: failed to create request cache\n"); ++ return -ENOENT; ++ } ++ ++ softc_device_init(&swcr_softc, "cryptosoft", 0, swcr_methods); ++ ++ swcr_id = crypto_get_driverid(softc_get_device(&swcr_softc), ++ CRYPTOCAP_F_SOFTWARE | CRYPTOCAP_F_SYNC); ++ if (swcr_id < 0) { ++ printk("cryptosoft: Software crypto device cannot initialize!"); ++ return -ENODEV; ++ } ++ ++#define REGISTER(alg) \ ++ crypto_register(swcr_id, alg, 0,0) ++ ++ for (i = 0; i < sizeof(crypto_details)/sizeof(crypto_details[0]); i++) { ++ int found; ++ ++ algo = crypto_details[i].alg_name; ++ if (!algo || !*algo) { ++ dprintk("%s:Algorithm %d not supported\n", __FUNCTION__, i); ++ continue; ++ } ++ ++ mode = crypto_details[i].mode; ++ sw_type = crypto_details[i].sw_type; ++ ++ found = 0; ++ switch (sw_type & SW_TYPE_ALG_MASK) { ++ case SW_TYPE_CIPHER: ++ found = crypto_has_cipher(algo, 0, CRYPTO_ALG_ASYNC); ++ break; ++ case SW_TYPE_HMAC: ++ found = crypto_has_hash(algo, 0, swcr_no_ahash?CRYPTO_ALG_ASYNC:0); ++ break; ++ case SW_TYPE_HASH: ++ found = crypto_has_hash(algo, 0, swcr_no_ahash?CRYPTO_ALG_ASYNC:0); ++ break; ++ case SW_TYPE_COMP: ++ found = crypto_has_comp(algo, 0, CRYPTO_ALG_ASYNC); ++ break; ++ case SW_TYPE_BLKCIPHER: ++ found = crypto_has_blkcipher(algo, 0, CRYPTO_ALG_ASYNC); ++ if (!found && !swcr_no_ablk) ++ found = crypto_has_ablkcipher(algo, 0, 0); ++ break; ++ } ++ if (found) { ++ REGISTER(i); ++ } else { ++ dprintk("%s:Algorithm Type %d not supported (algorithm %d:'%s')\n", ++ __FUNCTION__, sw_type, i, algo); ++ } ++ } ++ return 0; ++} ++ ++static void ++cryptosoft_exit(void) ++{ ++ dprintk("%s()\n", __FUNCTION__); ++ crypto_unregister_all(swcr_id); ++ swcr_id = -1; ++ kmem_cache_destroy(swcr_req_cache); ++} ++ ++late_initcall(cryptosoft_init); ++module_exit(cryptosoft_exit); ++ ++MODULE_LICENSE("Dual BSD/GPL"); ++MODULE_AUTHOR("David McCullough "); ++MODULE_DESCRIPTION("Cryptosoft (OCF module for kernel crypto)"); +diff -Nur linux-3.0.4.orig/crypto/ocf/ep80579/Makefile linux-3.0.4/crypto/ocf/ep80579/Makefile +--- linux-3.0.4.orig/crypto/ocf/ep80579/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/ep80579/Makefile 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,119 @@ ++######################################################################### ++# ++# Targets supported ++# all - builds everything and installs ++# install - identical to all ++# depend - build dependencies ++# clean - clears derived objects except the .depend files ++# distclean- clears all derived objects and the .depend file ++# ++# @par ++# This file is provided under a dual BSD/GPLv2 license. When using or ++# redistributing this file, you may do so under either license. ++# ++# GPL LICENSE SUMMARY ++# ++# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. ++# ++# This program is free software; you can redistribute it and/or modify ++# it under the terms of version 2 of the GNU General Public License as ++# published by the Free Software Foundation. ++# ++# This program is distributed in the hope that it will be useful, but ++# WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++# General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++# The full GNU General Public License is included in this distribution ++# in the file called LICENSE.GPL. ++# ++# Contact Information: ++# Intel Corporation ++# ++# BSD LICENSE ++# ++# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. ++# All rights reserved. ++# ++# Redistribution and use in source and binary forms, with or without ++# modification, are permitted provided that the following conditions ++# are met: ++# ++# * Redistributions of source code must retain the above copyright ++# notice, this list of conditions and the following disclaimer. ++# * Redistributions in binary form must reproduce the above copyright ++# notice, this list of conditions and the following disclaimer in ++# the documentation and/or other materials provided with the ++# distribution. ++# * Neither the name of Intel Corporation nor the names of its ++# contributors may be used to endorse or promote products derived ++# from this software without specific prior written permission. ++# ++# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++# ++# ++# version: Security.L.1.0.2-229 ++############################################################################ ++ ++ ++####################Common variables and definitions######################## ++ ++ifndef ICP_ROOT ++$(warning ICP_ROOT is undefined. Please set the path to EP80579 release package directory \ ++ "-> setenv ICP_ROOT ") ++all fastdep: ++ : ++else ++ ++ifndef KERNEL_SOURCE_ROOT ++$(error KERNEL_SOURCE_ROOT is undefined. Please set the path to the kernel source directory \ ++ "-> setenv KERNEL_SOURCE_ROOT ") ++endif ++ ++# Ensure The ENV_DIR environmental var is defined. ++ifndef ICP_ENV_DIR ++$(error ICP_ENV_DIR is undefined. Please set the path to EP80579 driver environment.mk file \ ++ "-> setenv ICP_ENV_DIR ") ++endif ++ ++#Add your project environment Makefile ++include ${ICP_ENV_DIR}/environment.mk ++ ++#include the makefile with all the default and common Make variable definitions ++include ${ICP_BUILDSYSTEM_PATH}/build_files/common.mk ++ ++#Add the name for the executable, Library or Module output definitions ++OUTPUT_NAME= icp_ocf ++ ++# List of Source Files to be compiled ++SOURCES= icp_common.c icp_sym.c icp_asym.c icp_ocf_linux.c ++ ++#common includes between all supported OSes ++INCLUDES= -I ${ICP_API_DIR} -I${ICP_LAC_API} \ ++-I${ICP_OCF_SRC_DIR} ++ ++# The location of the os level makefile needs to be changed. ++include ${ICP_ENV_DIR}/${ICP_OS}_${ICP_OS_LEVEL}.mk ++ ++# On the line directly below list the outputs you wish to build for, ++# e.g "lib_static lib_shared exe module" as shown below ++install: module ++ ++###################Include rules makefiles######################## ++include ${ICP_BUILDSYSTEM_PATH}/build_files/rules.mk ++###################End of Rules inclusion######################### ++ ++endif +diff -Nur linux-3.0.4.orig/crypto/ocf/ep80579/environment.mk linux-3.0.4/crypto/ocf/ep80579/environment.mk +--- linux-3.0.4.orig/crypto/ocf/ep80579/environment.mk 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/ep80579/environment.mk 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,78 @@ ++ ########################################################################### ++ # ++# This file is provided under a dual BSD/GPLv2 license. When using or ++# redistributing this file, you may do so under either license. ++# ++# GPL LICENSE SUMMARY ++# ++# Copyright(c) 2007,2008 Intel Corporation. All rights reserved. ++# ++# This program is free software; you can redistribute it and/or modify ++# it under the terms of version 2 of the GNU General Public License as ++# published by the Free Software Foundation. ++# ++# This program is distributed in the hope that it will be useful, but ++# WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++# General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++# The full GNU General Public License is included in this distribution ++# in the file called LICENSE.GPL. ++# ++# Contact Information: ++# Intel Corporation ++# ++# BSD LICENSE ++# ++# Copyright(c) 2007,2008 Intel Corporation. All rights reserved. ++# All rights reserved. ++# ++# Redistribution and use in source and binary forms, with or without ++# modification, are permitted provided that the following conditions ++# are met: ++# ++# * Redistributions of source code must retain the above copyright ++# notice, this list of conditions and the following disclaimer. ++# * Redistributions in binary form must reproduce the above copyright ++# notice, this list of conditions and the following disclaimer in ++# the documentation and/or other materials provided with the ++# distribution. ++# * Neither the name of Intel Corporation nor the names of its ++# contributors may be used to endorse or promote products derived ++# from this software without specific prior written permission. ++# ++# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++# ++# ++# version: Security.L.1.0.130 ++ # ++ ########################################################################### ++ ++ ++ICP_LAC_API=$(ICP_ROOT)/Acceleration/include/lac ++ICP_BTR_API=$(ICP_ROOT)/Acceleration/include/btr ++ICP_API_DIR=$(ICP_ROOT)/Acceleration/include ++ICP_OCF_SHIM_DIR?=$(KERNEL_SOURCE_ROOT)/crypto/ocf/ ++ifeq ($(wildcard $(ICP_OCF_SHIM_DIR)),) ++ICP_OCF_SHIM_DIR?=$(ROOTDIR)/modules/ocf/ ++endif ++ ++ICP_OS_LEVEL?=kernel_space ++ ++ICP_OS?=linux_2.6 ++ ++ICP_CORE?=ia ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/ep80579/icp_asym.c linux-3.0.4/crypto/ocf/ep80579/icp_asym.c +--- linux-3.0.4.orig/crypto/ocf/ep80579/icp_asym.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/ep80579/icp_asym.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,1334 @@ ++/*************************************************************************** ++ * ++ * This file is provided under a dual BSD/GPLv2 license. When using or ++ * redistributing this file, you may do so under either license. ++ * ++ * GPL LICENSE SUMMARY ++ * ++ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ * The full GNU General Public License is included in this distribution ++ * in the file called LICENSE.GPL. ++ * ++ * Contact Information: ++ * Intel Corporation ++ * ++ * BSD LICENSE ++ * ++ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * * Neither the name of Intel Corporation nor the names of its ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * ++ * version: Security.L.1.0.2-229 ++ * ++ ***************************************************************************/ ++ ++#include "icp_ocf.h" ++ ++/*The following define values (containing the word 'INDEX') are used to find ++the index of each input buffer of the crypto_kop struct (see OCF cryptodev.h). ++These values were found through analysis of the OCF OpenSSL patch. If the ++calling program uses different input buffer positions, these defines will have ++to be changed.*/ ++ ++/*DIFFIE HELLMAN buffer index values*/ ++#define ICP_DH_KRP_PARAM_PRIME_INDEX (0) ++#define ICP_DH_KRP_PARAM_BASE_INDEX (1) ++#define ICP_DH_KRP_PARAM_PRIVATE_VALUE_INDEX (2) ++#define ICP_DH_KRP_PARAM_RESULT_INDEX (3) ++ ++/*MOD EXP buffer index values*/ ++#define ICP_MOD_EXP_KRP_PARAM_BASE_INDEX (0) ++#define ICP_MOD_EXP_KRP_PARAM_EXPONENT_INDEX (1) ++#define ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX (2) ++#define ICP_MOD_EXP_KRP_PARAM_RESULT_INDEX (3) ++ ++/*MOD EXP CRT buffer index values*/ ++#define ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_P_INDEX (0) ++#define ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_Q_INDEX (1) ++#define ICP_MOD_EXP_CRT_KRP_PARAM_I_INDEX (2) ++#define ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DP_INDEX (3) ++#define ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DQ_INDEX (4) ++#define ICP_MOD_EXP_CRT_KRP_PARAM_COEFF_QINV_INDEX (5) ++#define ICP_MOD_EXP_CRT_KRP_PARAM_RESULT_INDEX (6) ++ ++/*DSA sign buffer index values*/ ++#define ICP_DSA_SIGN_KRP_PARAM_DGST_INDEX (0) ++#define ICP_DSA_SIGN_KRP_PARAM_PRIME_P_INDEX (1) ++#define ICP_DSA_SIGN_KRP_PARAM_PRIME_Q_INDEX (2) ++#define ICP_DSA_SIGN_KRP_PARAM_G_INDEX (3) ++#define ICP_DSA_SIGN_KRP_PARAM_X_INDEX (4) ++#define ICP_DSA_SIGN_KRP_PARAM_R_RESULT_INDEX (5) ++#define ICP_DSA_SIGN_KRP_PARAM_S_RESULT_INDEX (6) ++ ++/*DSA verify buffer index values*/ ++#define ICP_DSA_VERIFY_KRP_PARAM_DGST_INDEX (0) ++#define ICP_DSA_VERIFY_KRP_PARAM_PRIME_P_INDEX (1) ++#define ICP_DSA_VERIFY_KRP_PARAM_PRIME_Q_INDEX (2) ++#define ICP_DSA_VERIFY_KRP_PARAM_G_INDEX (3) ++#define ICP_DSA_VERIFY_KRP_PARAM_PUBKEY_INDEX (4) ++#define ICP_DSA_VERIFY_KRP_PARAM_SIG_R_INDEX (5) ++#define ICP_DSA_VERIFY_KRP_PARAM_SIG_S_INDEX (6) ++ ++/*DSA sign prime Q vs random number K size check values*/ ++#define DONT_RUN_LESS_THAN_CHECK (0) ++#define FAIL_A_IS_GREATER_THAN_B (1) ++#define FAIL_A_IS_EQUAL_TO_B (1) ++#define SUCCESS_A_IS_LESS_THAN_B (0) ++#define DSA_SIGN_RAND_GEN_VAL_CHECK_MAX_ITERATIONS (500) ++ ++/* We need to set a cryptokp success value just in case it is set or allocated ++ and not set to zero outside of this module */ ++#define CRYPTO_OP_SUCCESS (0) ++ ++/*Function to compute Diffie Hellman (DH) phase 1 or phase 2 key values*/ ++static int icp_ocfDrvDHComputeKey(struct cryptkop *krp); ++ ++/*Function to compute a Modular Exponentiation (Mod Exp)*/ ++static int icp_ocfDrvModExp(struct cryptkop *krp); ++ ++/*Function to compute a Mod Exp using the Chinease Remainder Theorem*/ ++static int icp_ocfDrvModExpCRT(struct cryptkop *krp); ++ ++/*Helper function to compute whether the first big number argument is less than ++ the second big number argument */ ++static int ++icp_ocfDrvCheckALessThanB(CpaFlatBuffer * pK, CpaFlatBuffer * pQ, int *doCheck); ++ ++/*Function to sign an input with DSA R and S keys*/ ++static int icp_ocfDrvDsaSign(struct cryptkop *krp); ++ ++/*Function to Verify a DSA buffer signature*/ ++static int icp_ocfDrvDsaVerify(struct cryptkop *krp); ++ ++/*Callback function for DH operation*/ ++static void ++icp_ocfDrvDhP1CallBack(void *callbackTag, ++ CpaStatus status, ++ void *pOpData, CpaFlatBuffer * pLocalOctetStringPV); ++ ++/*Callback function for ME operation*/ ++static void ++icp_ocfDrvModExpCallBack(void *callbackTag, ++ CpaStatus status, ++ void *pOpData, CpaFlatBuffer * pResult); ++ ++/*Callback function for ME CRT operation*/ ++static void ++icp_ocfDrvModExpCRTCallBack(void *callbackTag, ++ CpaStatus status, ++ void *pOpData, CpaFlatBuffer * pOutputData); ++ ++/*Callback function for DSA sign operation*/ ++static void ++icp_ocfDrvDsaRSSignCallBack(void *callbackTag, ++ CpaStatus status, ++ void *pOpData, ++ CpaBoolean protocolStatus, ++ CpaFlatBuffer * pR, CpaFlatBuffer * pS); ++ ++/*Callback function for DSA Verify operation*/ ++static void ++icp_ocfDrvDsaVerifyCallBack(void *callbackTag, ++ CpaStatus status, ++ void *pOpData, CpaBoolean verifyStatus); ++ ++/* Name : icp_ocfDrvPkeProcess ++ * ++ * Description : This function will choose which PKE process to follow ++ * based on the input arguments ++ */ ++int icp_ocfDrvPkeProcess(icp_device_t dev, struct cryptkop *krp, int hint) ++{ ++ CpaStatus lacStatus = CPA_STATUS_SUCCESS; ++ ++ if (NULL == krp) { ++ DPRINTK("%s(): Invalid input parameters, cryptkop = %p\n", ++ __FUNCTION__, krp); ++ return EINVAL; ++ } ++ ++ if (CPA_TRUE == icp_atomic_read(&icp_ocfDrvIsExiting)) { ++ krp->krp_status = ECANCELED; ++ return ECANCELED; ++ } ++ ++ switch (krp->krp_op) { ++ case CRK_DH_COMPUTE_KEY: ++ DPRINTK("%s() doing DH_COMPUTE_KEY\n", __FUNCTION__); ++ lacStatus = icp_ocfDrvDHComputeKey(krp); ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): icp_ocfDrvDHComputeKey failed " ++ "(%d).\n", __FUNCTION__, lacStatus); ++ krp->krp_status = ECANCELED; ++ return ECANCELED; ++ } ++ ++ break; ++ ++ case CRK_MOD_EXP: ++ DPRINTK("%s() doing MOD_EXP \n", __FUNCTION__); ++ lacStatus = icp_ocfDrvModExp(krp); ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): icp_ocfDrvModExp failed (%d).\n", ++ __FUNCTION__, lacStatus); ++ krp->krp_status = ECANCELED; ++ return ECANCELED; ++ } ++ ++ break; ++ ++ case CRK_MOD_EXP_CRT: ++ DPRINTK("%s() doing MOD_EXP_CRT \n", __FUNCTION__); ++ lacStatus = icp_ocfDrvModExpCRT(krp); ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): icp_ocfDrvModExpCRT " ++ "failed (%d).\n", __FUNCTION__, lacStatus); ++ krp->krp_status = ECANCELED; ++ return ECANCELED; ++ } ++ ++ break; ++ ++ case CRK_DSA_SIGN: ++ DPRINTK("%s() doing DSA_SIGN \n", __FUNCTION__); ++ lacStatus = icp_ocfDrvDsaSign(krp); ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): icp_ocfDrvDsaSign " ++ "failed (%d).\n", __FUNCTION__, lacStatus); ++ krp->krp_status = ECANCELED; ++ return ECANCELED; ++ } ++ ++ break; ++ ++ case CRK_DSA_VERIFY: ++ DPRINTK("%s() doing DSA_VERIFY \n", __FUNCTION__); ++ lacStatus = icp_ocfDrvDsaVerify(krp); ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): icp_ocfDrvDsaVerify " ++ "failed (%d).\n", __FUNCTION__, lacStatus); ++ krp->krp_status = ECANCELED; ++ return ECANCELED; ++ } ++ ++ break; ++ ++ default: ++ EPRINTK("%s(): Asymettric function not " ++ "supported (%d).\n", __FUNCTION__, krp->krp_op); ++ krp->krp_status = EOPNOTSUPP; ++ return EOPNOTSUPP; ++ } ++ ++ return ICP_OCF_DRV_STATUS_SUCCESS; ++} ++ ++/* Name : icp_ocfDrvSwapBytes ++ * ++ * Description : This function is used to swap the byte order of a buffer. ++ * It has been seen that in general we are passed little endian byte order ++ * buffers, but LAC only accepts big endian byte order buffers. ++ */ ++static void inline icp_ocfDrvSwapBytes(u_int8_t * num, u_int32_t buff_len_bytes) ++{ ++ ++ int i; ++ u_int8_t *end_ptr; ++ u_int8_t hold_val; ++ ++ end_ptr = num + (buff_len_bytes - 1); ++ buff_len_bytes = buff_len_bytes >> 1; ++ for (i = 0; i < buff_len_bytes; i++) { ++ hold_val = *num; ++ *num = *end_ptr; ++ num++; ++ *end_ptr = hold_val; ++ end_ptr--; ++ } ++} ++ ++/* Name : icp_ocfDrvDHComputeKey ++ * ++ * Description : This function will map Diffie Hellman calls from OCF ++ * to the LAC API. OCF uses this function for Diffie Hellman Phase1 and ++ * Phase2. LAC has a separate Diffie Hellman Phase2 call, however both phases ++ * break down to a modular exponentiation. ++ */ ++static int icp_ocfDrvDHComputeKey(struct cryptkop *krp) ++{ ++ CpaStatus lacStatus = CPA_STATUS_SUCCESS; ++ void *callbackTag = NULL; ++ CpaCyDhPhase1KeyGenOpData *pPhase1OpData = NULL; ++ CpaFlatBuffer *pLocalOctetStringPV = NULL; ++ uint32_t dh_prime_len_bytes = 0, dh_prime_len_bits = 0; ++ ++ /* Input checks - check prime is a multiple of 8 bits to allow for ++ allocation later */ ++ dh_prime_len_bits = ++ (krp->krp_param[ICP_DH_KRP_PARAM_PRIME_INDEX].crp_nbits); ++ ++ /* LAC can reject prime lengths based on prime key sizes, we just ++ need to make sure we can allocate space for the base and ++ exponent buffers correctly */ ++ if ((dh_prime_len_bits % NUM_BITS_IN_BYTE) != 0) { ++ APRINTK("%s(): Warning Prime number buffer size is not a " ++ "multiple of 8 bits\n", __FUNCTION__); ++ } ++ ++ /* Result storage space should be the same size as the prime as this ++ value can take up the same amount of storage space */ ++ if (dh_prime_len_bits != ++ krp->krp_param[ICP_DH_KRP_PARAM_RESULT_INDEX].crp_nbits) { ++ DPRINTK("%s(): Return Buffer must be the same size " ++ "as the Prime buffer\n", __FUNCTION__); ++ krp->krp_status = EINVAL; ++ return EINVAL; ++ } ++ /* Switch to size in bytes */ ++ BITS_TO_BYTES(dh_prime_len_bytes, dh_prime_len_bits); ++ ++ callbackTag = krp; ++ ++/*All allocations are set to ICP_M_NOWAIT due to the possibility of getting ++called in interrupt context*/ ++ pPhase1OpData = icp_kmem_cache_zalloc(drvDH_zone, ICP_M_NOWAIT); ++ if (NULL == pPhase1OpData) { ++ APRINTK("%s():Failed to get memory for key gen data\n", ++ __FUNCTION__); ++ krp->krp_status = ENOMEM; ++ return ENOMEM; ++ } ++ ++ pLocalOctetStringPV = ++ icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); ++ if (NULL == pLocalOctetStringPV) { ++ APRINTK("%s():Failed to get memory for pLocalOctetStringPV\n", ++ __FUNCTION__); ++ ICP_CACHE_FREE(drvDH_zone, pPhase1OpData); ++ krp->krp_status = ENOMEM; ++ return ENOMEM; ++ } ++ ++ /* Link parameters */ ++ pPhase1OpData->primeP.pData = ++ krp->krp_param[ICP_DH_KRP_PARAM_PRIME_INDEX].crp_p; ++ ++ pPhase1OpData->primeP.dataLenInBytes = dh_prime_len_bytes; ++ ++ icp_ocfDrvSwapBytes(pPhase1OpData->primeP.pData, dh_prime_len_bytes); ++ ++ pPhase1OpData->baseG.pData = ++ krp->krp_param[ICP_DH_KRP_PARAM_BASE_INDEX].crp_p; ++ ++ BITS_TO_BYTES(pPhase1OpData->baseG.dataLenInBytes, ++ krp->krp_param[ICP_DH_KRP_PARAM_BASE_INDEX].crp_nbits); ++ ++ icp_ocfDrvSwapBytes(pPhase1OpData->baseG.pData, ++ pPhase1OpData->baseG.dataLenInBytes); ++ ++ pPhase1OpData->privateValueX.pData = ++ krp->krp_param[ICP_DH_KRP_PARAM_PRIVATE_VALUE_INDEX].crp_p; ++ ++ BITS_TO_BYTES(pPhase1OpData->privateValueX.dataLenInBytes, ++ krp->krp_param[ICP_DH_KRP_PARAM_PRIVATE_VALUE_INDEX]. ++ crp_nbits); ++ ++ icp_ocfDrvSwapBytes(pPhase1OpData->privateValueX.pData, ++ pPhase1OpData->privateValueX.dataLenInBytes); ++ ++ /* Output parameters */ ++ pLocalOctetStringPV->pData = ++ krp->krp_param[ICP_DH_KRP_PARAM_RESULT_INDEX].crp_p; ++ ++ BITS_TO_BYTES(pLocalOctetStringPV->dataLenInBytes, ++ krp->krp_param[ICP_DH_KRP_PARAM_RESULT_INDEX].crp_nbits); ++ ++ lacStatus = cpaCyDhKeyGenPhase1(CPA_INSTANCE_HANDLE_SINGLE, ++ icp_ocfDrvDhP1CallBack, ++ callbackTag, pPhase1OpData, ++ pLocalOctetStringPV); ++ ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): DH Phase 1 Key Gen failed (%d).\n", ++ __FUNCTION__, lacStatus); ++ icp_ocfDrvFreeFlatBuffer(pLocalOctetStringPV); ++ ICP_CACHE_FREE(drvDH_zone, pPhase1OpData); ++ } ++ ++ return lacStatus; ++} ++ ++/* Name : icp_ocfDrvModExp ++ * ++ * Description : This function will map ordinary Modular Exponentiation calls ++ * from OCF to the LAC API. ++ * ++ */ ++static int icp_ocfDrvModExp(struct cryptkop *krp) ++{ ++ CpaStatus lacStatus = CPA_STATUS_SUCCESS; ++ void *callbackTag = NULL; ++ CpaCyLnModExpOpData *pModExpOpData = NULL; ++ CpaFlatBuffer *pResult = NULL; ++ ++ if ((krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX].crp_nbits % ++ NUM_BITS_IN_BYTE) != 0) { ++ DPRINTK("%s(): Warning - modulus buffer size (%d) is not a " ++ "multiple of 8 bits\n", __FUNCTION__, ++ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX]. ++ crp_nbits); ++ } ++ ++ /* Result storage space should be the same size as the prime as this ++ value can take up the same amount of storage space */ ++ if (krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX].crp_nbits > ++ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_RESULT_INDEX].crp_nbits) { ++ APRINTK("%s(): Return Buffer size must be the same or" ++ " greater than the Modulus buffer\n", __FUNCTION__); ++ krp->krp_status = EINVAL; ++ return EINVAL; ++ } ++ ++ callbackTag = krp; ++ ++ pModExpOpData = icp_kmem_cache_zalloc(drvLnModExp_zone, ICP_M_NOWAIT); ++ if (NULL == pModExpOpData) { ++ APRINTK("%s():Failed to get memory for key gen data\n", ++ __FUNCTION__); ++ krp->krp_status = ENOMEM; ++ return ENOMEM; ++ } ++ ++ pResult = icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); ++ if (NULL == pResult) { ++ APRINTK("%s():Failed to get memory for ModExp result\n", ++ __FUNCTION__); ++ ICP_CACHE_FREE(drvLnModExp_zone, pModExpOpData); ++ krp->krp_status = ENOMEM; ++ return ENOMEM; ++ } ++ ++ /* Link parameters */ ++ pModExpOpData->modulus.pData = ++ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX].crp_p; ++ BITS_TO_BYTES(pModExpOpData->modulus.dataLenInBytes, ++ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX]. ++ crp_nbits); ++ ++ icp_ocfDrvSwapBytes(pModExpOpData->modulus.pData, ++ pModExpOpData->modulus.dataLenInBytes); ++ ++ DPRINTK("%s : base (%d)\n", __FUNCTION__, krp-> ++ krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX].crp_nbits); ++ pModExpOpData->base.pData = ++ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX].crp_p; ++ BITS_TO_BYTES(pModExpOpData->base.dataLenInBytes, ++ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX]. ++ crp_nbits); ++ icp_ocfDrvSwapBytes(pModExpOpData->base.pData, ++ pModExpOpData->base.dataLenInBytes); ++ ++ pModExpOpData->exponent.pData = ++ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_EXPONENT_INDEX].crp_p; ++ BITS_TO_BYTES(pModExpOpData->exponent.dataLenInBytes, ++ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_EXPONENT_INDEX]. ++ crp_nbits); ++ ++ icp_ocfDrvSwapBytes(pModExpOpData->exponent.pData, ++ pModExpOpData->exponent.dataLenInBytes); ++ /* Output parameters */ ++ pResult->pData = ++ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_RESULT_INDEX].crp_p, ++ BITS_TO_BYTES(pResult->dataLenInBytes, ++ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_RESULT_INDEX]. ++ crp_nbits); ++ ++ lacStatus = cpaCyLnModExp(CPA_INSTANCE_HANDLE_SINGLE, ++ icp_ocfDrvModExpCallBack, ++ callbackTag, pModExpOpData, pResult); ++ ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): Mod Exp Operation failed (%d).\n", ++ __FUNCTION__, lacStatus); ++ krp->krp_status = ECANCELED; ++ icp_ocfDrvFreeFlatBuffer(pResult); ++ ICP_CACHE_FREE(drvLnModExp_zone, pModExpOpData); ++ } ++ ++ return lacStatus; ++} ++ ++/* Name : icp_ocfDrvModExpCRT ++ * ++ * Description : This function will map ordinary Modular Exponentiation Chinese ++ * Remainder Theorem implementaion calls from OCF to the LAC API. ++ * ++ * Note : Mod Exp CRT for this driver is accelerated through LAC RSA type 2 ++ * decrypt operation. Therefore P and Q input values must always be prime ++ * numbers. Although basic primality checks are done in LAC, it is up to the ++ * user to do any correct prime number checking before passing the inputs. ++ */ ++static int icp_ocfDrvModExpCRT(struct cryptkop *krp) ++{ ++ CpaStatus lacStatus = CPA_STATUS_SUCCESS; ++ CpaCyRsaDecryptOpData *rsaDecryptOpData = NULL; ++ void *callbackTag = NULL; ++ CpaFlatBuffer *pOutputData = NULL; ++ ++ /*Parameter input checks are all done by LAC, no need to repeat ++ them here. */ ++ callbackTag = krp; ++ ++ rsaDecryptOpData = ++ icp_kmem_cache_zalloc(drvRSADecrypt_zone, ICP_M_NOWAIT); ++ if (NULL == rsaDecryptOpData) { ++ APRINTK("%s():Failed to get memory" ++ " for MOD EXP CRT Op data struct\n", __FUNCTION__); ++ krp->krp_status = ENOMEM; ++ return ENOMEM; ++ } ++ ++ rsaDecryptOpData->pRecipientPrivateKey ++ = icp_kmem_cache_zalloc(drvRSAPrivateKey_zone, ICP_M_NOWAIT); ++ if (NULL == rsaDecryptOpData->pRecipientPrivateKey) { ++ APRINTK("%s():Failed to get memory for MOD EXP CRT" ++ " private key values struct\n", __FUNCTION__); ++ ICP_CACHE_FREE(drvRSADecrypt_zone, rsaDecryptOpData); ++ krp->krp_status = ENOMEM; ++ return ENOMEM; ++ } ++ ++ rsaDecryptOpData->pRecipientPrivateKey-> ++ version = CPA_CY_RSA_VERSION_TWO_PRIME; ++ rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRepType = CPA_CY_RSA_PRIVATE_KEY_REP_TYPE_2; ++ ++ pOutputData = icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); ++ if (NULL == pOutputData) { ++ APRINTK("%s():Failed to get memory" ++ " for MOD EXP CRT output data\n", __FUNCTION__); ++ ICP_CACHE_FREE(drvRSAPrivateKey_zone, ++ rsaDecryptOpData->pRecipientPrivateKey); ++ ICP_CACHE_FREE(drvRSADecrypt_zone, rsaDecryptOpData); ++ krp->krp_status = ENOMEM; ++ return ENOMEM; ++ } ++ ++ rsaDecryptOpData->pRecipientPrivateKey-> ++ version = CPA_CY_RSA_VERSION_TWO_PRIME; ++ rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRepType = CPA_CY_RSA_PRIVATE_KEY_REP_TYPE_2; ++ ++ /* Link parameters */ ++ rsaDecryptOpData->inputData.pData = ++ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_I_INDEX].crp_p; ++ BITS_TO_BYTES(rsaDecryptOpData->inputData.dataLenInBytes, ++ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_I_INDEX]. ++ crp_nbits); ++ ++ icp_ocfDrvSwapBytes(rsaDecryptOpData->inputData.pData, ++ rsaDecryptOpData->inputData.dataLenInBytes); ++ ++ rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2.prime1P.pData = ++ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_P_INDEX].crp_p; ++ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2. ++ prime1P.dataLenInBytes, ++ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_P_INDEX]. ++ crp_nbits); ++ ++ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.prime1P.pData, ++ rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.prime1P.dataLenInBytes); ++ ++ rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2.prime2Q.pData = ++ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_Q_INDEX].crp_p; ++ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2. ++ prime2Q.dataLenInBytes, ++ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_Q_INDEX]. ++ crp_nbits); ++ ++ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.prime2Q.pData, ++ rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.prime2Q.dataLenInBytes); ++ ++ rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.exponent1Dp.pData = ++ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DP_INDEX].crp_p; ++ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2. ++ exponent1Dp.dataLenInBytes, ++ krp-> ++ krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DP_INDEX]. ++ crp_nbits); ++ ++ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.exponent1Dp.pData, ++ rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.exponent1Dp.dataLenInBytes); ++ ++ rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.exponent2Dq.pData = ++ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DQ_INDEX].crp_p; ++ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.exponent2Dq.dataLenInBytes, ++ krp-> ++ krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DQ_INDEX]. ++ crp_nbits); ++ ++ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.exponent2Dq.pData, ++ rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.exponent2Dq.dataLenInBytes); ++ ++ rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.coefficientQInv.pData = ++ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_COEFF_QINV_INDEX].crp_p; ++ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.coefficientQInv.dataLenInBytes, ++ krp-> ++ krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_COEFF_QINV_INDEX]. ++ crp_nbits); ++ ++ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.coefficientQInv.pData, ++ rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.coefficientQInv.dataLenInBytes); ++ ++ /* Output Parameter */ ++ pOutputData->pData = ++ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_RESULT_INDEX].crp_p; ++ BITS_TO_BYTES(pOutputData->dataLenInBytes, ++ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_RESULT_INDEX]. ++ crp_nbits); ++ ++ lacStatus = cpaCyRsaDecrypt(CPA_INSTANCE_HANDLE_SINGLE, ++ icp_ocfDrvModExpCRTCallBack, ++ callbackTag, rsaDecryptOpData, pOutputData); ++ ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): Mod Exp CRT Operation failed (%d).\n", ++ __FUNCTION__, lacStatus); ++ krp->krp_status = ECANCELED; ++ icp_ocfDrvFreeFlatBuffer(pOutputData); ++ ICP_CACHE_FREE(drvRSAPrivateKey_zone, ++ rsaDecryptOpData->pRecipientPrivateKey); ++ ICP_CACHE_FREE(drvRSADecrypt_zone, rsaDecryptOpData); ++ } ++ ++ return lacStatus; ++} ++ ++/* Name : icp_ocfDrvCheckALessThanB ++ * ++ * Description : This function will check whether the first argument is less ++ * than the second. It is used to check whether the DSA RS sign Random K ++ * value is less than the Prime Q value (as defined in the specification) ++ * ++ */ ++static int ++icp_ocfDrvCheckALessThanB(CpaFlatBuffer * pK, CpaFlatBuffer * pQ, int *doCheck) ++{ ++ ++ uint8_t *MSB_K = pK->pData; ++ uint8_t *MSB_Q = pQ->pData; ++ uint32_t buffer_lengths_in_bytes = pQ->dataLenInBytes; ++ ++ if (DONT_RUN_LESS_THAN_CHECK == *doCheck) { ++ return FAIL_A_IS_GREATER_THAN_B; ++ } ++ ++/*Check MSBs ++if A == B, check next MSB ++if A > B, return A_IS_GREATER_THAN_B ++if A < B, return A_IS_LESS_THAN_B (success) ++*/ ++ while (*MSB_K == *MSB_Q) { ++ MSB_K++; ++ MSB_Q++; ++ ++ buffer_lengths_in_bytes--; ++ if (0 == buffer_lengths_in_bytes) { ++ DPRINTK("%s() Buffers have equal value!!\n", ++ __FUNCTION__); ++ return FAIL_A_IS_EQUAL_TO_B; ++ } ++ ++ } ++ ++ if (*MSB_K < *MSB_Q) { ++ return SUCCESS_A_IS_LESS_THAN_B; ++ } else { ++ return FAIL_A_IS_GREATER_THAN_B; ++ } ++ ++} ++ ++/* Name : icp_ocfDrvDsaSign ++ * ++ * Description : This function will map DSA RS Sign from OCF to the LAC API. ++ * ++ * NOTE: From looking at OCF patch to OpenSSL and even the number of input ++ * parameters, OCF expects us to generate the random seed value. This value ++ * is generated and passed to LAC, however the number is discared in the ++ * callback and not returned to the user. ++ */ ++static int icp_ocfDrvDsaSign(struct cryptkop *krp) ++{ ++ CpaStatus lacStatus = CPA_STATUS_SUCCESS; ++ CpaCyDsaRSSignOpData *dsaRsSignOpData = NULL; ++ void *callbackTag = NULL; ++ CpaCyRandGenOpData randGenOpData; ++ int primeQSizeInBytes = 0; ++ int doCheck = 0; ++ CpaFlatBuffer randData; ++ CpaBoolean protocolStatus = CPA_FALSE; ++ CpaFlatBuffer *pR = NULL; ++ CpaFlatBuffer *pS = NULL; ++ ++ callbackTag = krp; ++ ++ BITS_TO_BYTES(primeQSizeInBytes, ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_Q_INDEX]. ++ crp_nbits); ++ ++ if (DSA_RS_SIGN_PRIMEQ_SIZE_IN_BYTES != primeQSizeInBytes) { ++ APRINTK("%s(): DSA PRIME Q size not equal to the " ++ "FIPS defined 20bytes, = %d\n", ++ __FUNCTION__, primeQSizeInBytes); ++ krp->krp_status = EDOM; ++ return EDOM; ++ } ++ ++ dsaRsSignOpData = ++ icp_kmem_cache_zalloc(drvDSARSSign_zone, ICP_M_NOWAIT); ++ if (NULL == dsaRsSignOpData) { ++ APRINTK("%s():Failed to get memory" ++ " for DSA RS Sign Op data struct\n", __FUNCTION__); ++ krp->krp_status = ENOMEM; ++ return ENOMEM; ++ } ++ ++ dsaRsSignOpData->K.pData = ++ icp_kmem_cache_alloc(drvDSARSSignKValue_zone, ICP_M_NOWAIT); ++ ++ if (NULL == dsaRsSignOpData->K.pData) { ++ APRINTK("%s():Failed to get memory" ++ " for DSA RS Sign Op Random value\n", __FUNCTION__); ++ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); ++ krp->krp_status = ENOMEM; ++ return ENOMEM; ++ } ++ ++ pR = icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); ++ if (NULL == pR) { ++ APRINTK("%s():Failed to get memory" ++ " for DSA signature R\n", __FUNCTION__); ++ ICP_CACHE_FREE(drvDSARSSignKValue_zone, ++ dsaRsSignOpData->K.pData); ++ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); ++ krp->krp_status = ENOMEM; ++ return ENOMEM; ++ } ++ ++ pS = icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); ++ if (NULL == pS) { ++ APRINTK("%s():Failed to get memory" ++ " for DSA signature S\n", __FUNCTION__); ++ icp_ocfDrvFreeFlatBuffer(pR); ++ ICP_CACHE_FREE(drvDSARSSignKValue_zone, ++ dsaRsSignOpData->K.pData); ++ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); ++ krp->krp_status = ENOMEM; ++ return ENOMEM; ++ } ++ ++ /*link prime number parameter for ease of processing */ ++ dsaRsSignOpData->P.pData = ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_P_INDEX].crp_p; ++ BITS_TO_BYTES(dsaRsSignOpData->P.dataLenInBytes, ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_P_INDEX]. ++ crp_nbits); ++ ++ icp_ocfDrvSwapBytes(dsaRsSignOpData->P.pData, ++ dsaRsSignOpData->P.dataLenInBytes); ++ ++ dsaRsSignOpData->Q.pData = ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_Q_INDEX].crp_p; ++ BITS_TO_BYTES(dsaRsSignOpData->Q.dataLenInBytes, ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_Q_INDEX]. ++ crp_nbits); ++ ++ icp_ocfDrvSwapBytes(dsaRsSignOpData->Q.pData, ++ dsaRsSignOpData->Q.dataLenInBytes); ++ ++ /*generate random number with equal buffer size to Prime value Q, ++ but value less than Q */ ++ dsaRsSignOpData->K.dataLenInBytes = dsaRsSignOpData->Q.dataLenInBytes; ++ ++ randGenOpData.generateBits = CPA_TRUE; ++ randGenOpData.lenInBytes = dsaRsSignOpData->K.dataLenInBytes; ++ ++ icp_ocfDrvPtrAndLenToFlatBuffer(dsaRsSignOpData->K.pData, ++ dsaRsSignOpData->K.dataLenInBytes, ++ &randData); ++ ++ doCheck = 0; ++ while (icp_ocfDrvCheckALessThanB(&(dsaRsSignOpData->K), ++ &(dsaRsSignOpData->Q), &doCheck)) { ++ ++ if (CPA_STATUS_SUCCESS ++ != cpaCyRandGen(CPA_INSTANCE_HANDLE_SINGLE, ++ NULL, NULL, &randGenOpData, &randData)) { ++ APRINTK("%s(): ERROR - Failed to generate DSA RS Sign K" ++ "value\n", __FUNCTION__); ++ icp_ocfDrvFreeFlatBuffer(pS); ++ icp_ocfDrvFreeFlatBuffer(pR); ++ ICP_CACHE_FREE(drvDSARSSignKValue_zone, ++ dsaRsSignOpData->K.pData); ++ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); ++ krp->krp_status = EAGAIN; ++ return EAGAIN; ++ } ++ ++ doCheck++; ++ if (DSA_SIGN_RAND_GEN_VAL_CHECK_MAX_ITERATIONS == doCheck) { ++ APRINTK("%s(): ERROR - Failed to find DSA RS Sign K " ++ "value less than Q value\n", __FUNCTION__); ++ icp_ocfDrvFreeFlatBuffer(pS); ++ icp_ocfDrvFreeFlatBuffer(pR); ++ ICP_CACHE_FREE(drvDSARSSignKValue_zone, ++ dsaRsSignOpData->K.pData); ++ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); ++ krp->krp_status = EAGAIN; ++ return EAGAIN; ++ } ++ ++ } ++ /*Rand Data - no need to swap bytes for pK */ ++ ++ /* Link parameters */ ++ dsaRsSignOpData->G.pData = ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_G_INDEX].crp_p; ++ BITS_TO_BYTES(dsaRsSignOpData->G.dataLenInBytes, ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_G_INDEX].crp_nbits); ++ ++ icp_ocfDrvSwapBytes(dsaRsSignOpData->G.pData, ++ dsaRsSignOpData->G.dataLenInBytes); ++ ++ dsaRsSignOpData->X.pData = ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_X_INDEX].crp_p; ++ BITS_TO_BYTES(dsaRsSignOpData->X.dataLenInBytes, ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_X_INDEX].crp_nbits); ++ icp_ocfDrvSwapBytes(dsaRsSignOpData->X.pData, ++ dsaRsSignOpData->X.dataLenInBytes); ++ ++ /*OpenSSL dgst parameter is left in big endian byte order, ++ therefore no byte swap is required */ ++ dsaRsSignOpData->M.pData = ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_DGST_INDEX].crp_p; ++ BITS_TO_BYTES(dsaRsSignOpData->M.dataLenInBytes, ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_DGST_INDEX]. ++ crp_nbits); ++ ++ /* Output Parameters */ ++ pS->pData = krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_S_RESULT_INDEX].crp_p; ++ BITS_TO_BYTES(pS->dataLenInBytes, ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_S_RESULT_INDEX]. ++ crp_nbits); ++ ++ pR->pData = krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_R_RESULT_INDEX].crp_p; ++ BITS_TO_BYTES(pR->dataLenInBytes, ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_R_RESULT_INDEX]. ++ crp_nbits); ++ ++ lacStatus = cpaCyDsaSignRS(CPA_INSTANCE_HANDLE_SINGLE, ++ icp_ocfDrvDsaRSSignCallBack, ++ callbackTag, dsaRsSignOpData, ++ &protocolStatus, pR, pS); ++ ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): DSA RS Sign Operation failed (%d).\n", ++ __FUNCTION__, lacStatus); ++ krp->krp_status = ECANCELED; ++ icp_ocfDrvFreeFlatBuffer(pS); ++ icp_ocfDrvFreeFlatBuffer(pR); ++ ICP_CACHE_FREE(drvDSARSSignKValue_zone, ++ dsaRsSignOpData->K.pData); ++ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); ++ } ++ ++ return lacStatus; ++} ++ ++/* Name : icp_ocfDrvDsaVerify ++ * ++ * Description : This function will map DSA RS Verify from OCF to the LAC API. ++ * ++ */ ++static int icp_ocfDrvDsaVerify(struct cryptkop *krp) ++{ ++ CpaStatus lacStatus = CPA_STATUS_SUCCESS; ++ CpaCyDsaVerifyOpData *dsaVerifyOpData = NULL; ++ void *callbackTag = NULL; ++ CpaBoolean verifyStatus = CPA_FALSE; ++ ++ callbackTag = krp; ++ ++ dsaVerifyOpData = ++ icp_kmem_cache_zalloc(drvDSAVerify_zone, ICP_M_NOWAIT); ++ if (NULL == dsaVerifyOpData) { ++ APRINTK("%s():Failed to get memory" ++ " for DSA Verify Op data struct\n", __FUNCTION__); ++ krp->krp_status = ENOMEM; ++ return ENOMEM; ++ } ++ ++ /* Link parameters */ ++ dsaVerifyOpData->P.pData = ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PRIME_P_INDEX].crp_p; ++ BITS_TO_BYTES(dsaVerifyOpData->P.dataLenInBytes, ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PRIME_P_INDEX]. ++ crp_nbits); ++ icp_ocfDrvSwapBytes(dsaVerifyOpData->P.pData, ++ dsaVerifyOpData->P.dataLenInBytes); ++ ++ dsaVerifyOpData->Q.pData = ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PRIME_Q_INDEX].crp_p; ++ BITS_TO_BYTES(dsaVerifyOpData->Q.dataLenInBytes, ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PRIME_Q_INDEX]. ++ crp_nbits); ++ icp_ocfDrvSwapBytes(dsaVerifyOpData->Q.pData, ++ dsaVerifyOpData->Q.dataLenInBytes); ++ ++ dsaVerifyOpData->G.pData = ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_G_INDEX].crp_p; ++ BITS_TO_BYTES(dsaVerifyOpData->G.dataLenInBytes, ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_G_INDEX]. ++ crp_nbits); ++ icp_ocfDrvSwapBytes(dsaVerifyOpData->G.pData, ++ dsaVerifyOpData->G.dataLenInBytes); ++ ++ dsaVerifyOpData->Y.pData = ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PUBKEY_INDEX].crp_p; ++ BITS_TO_BYTES(dsaVerifyOpData->Y.dataLenInBytes, ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PUBKEY_INDEX]. ++ crp_nbits); ++ icp_ocfDrvSwapBytes(dsaVerifyOpData->Y.pData, ++ dsaVerifyOpData->Y.dataLenInBytes); ++ ++ /*OpenSSL dgst parameter is left in big endian byte order, ++ therefore no byte swap is required */ ++ dsaVerifyOpData->M.pData = ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_DGST_INDEX].crp_p; ++ BITS_TO_BYTES(dsaVerifyOpData->M.dataLenInBytes, ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_DGST_INDEX]. ++ crp_nbits); ++ ++ dsaVerifyOpData->R.pData = ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_SIG_R_INDEX].crp_p; ++ BITS_TO_BYTES(dsaVerifyOpData->R.dataLenInBytes, ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_SIG_R_INDEX]. ++ crp_nbits); ++ icp_ocfDrvSwapBytes(dsaVerifyOpData->R.pData, ++ dsaVerifyOpData->R.dataLenInBytes); ++ ++ dsaVerifyOpData->S.pData = ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_SIG_S_INDEX].crp_p; ++ BITS_TO_BYTES(dsaVerifyOpData->S.dataLenInBytes, ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_SIG_S_INDEX]. ++ crp_nbits); ++ icp_ocfDrvSwapBytes(dsaVerifyOpData->S.pData, ++ dsaVerifyOpData->S.dataLenInBytes); ++ ++ lacStatus = cpaCyDsaVerify(CPA_INSTANCE_HANDLE_SINGLE, ++ icp_ocfDrvDsaVerifyCallBack, ++ callbackTag, dsaVerifyOpData, &verifyStatus); ++ ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): DSA Verify Operation failed (%d).\n", ++ __FUNCTION__, lacStatus); ++ ICP_CACHE_FREE(drvDSAVerify_zone, dsaVerifyOpData); ++ krp->krp_status = ECANCELED; ++ } ++ ++ return lacStatus; ++} ++ ++/* Name : icp_ocfDrvDhP1Callback ++ * ++ * Description : When this function returns it signifies that the LAC ++ * component has completed the DH operation. ++ */ ++static void ++icp_ocfDrvDhP1CallBack(void *callbackTag, ++ CpaStatus status, ++ void *pOpData, CpaFlatBuffer * pLocalOctetStringPV) ++{ ++ struct cryptkop *krp = NULL; ++ CpaCyDhPhase1KeyGenOpData *pPhase1OpData = NULL; ++ ++ if (NULL == callbackTag) { ++ DPRINTK("%s(): Invalid input parameters - " ++ "callbackTag data is NULL\n", __FUNCTION__); ++ return; ++ } ++ krp = (struct cryptkop *)callbackTag; ++ ++ if (NULL == pOpData) { ++ DPRINTK("%s(): Invalid input parameters - " ++ "Operation Data is NULL\n", __FUNCTION__); ++ krp->krp_status = ECANCELED; ++ crypto_kdone(krp); ++ return; ++ } ++ pPhase1OpData = (CpaCyDhPhase1KeyGenOpData *) pOpData; ++ ++ if (NULL == pLocalOctetStringPV) { ++ DPRINTK("%s(): Invalid input parameters - " ++ "pLocalOctetStringPV Data is NULL\n", __FUNCTION__); ++ memset(pPhase1OpData, 0, sizeof(CpaCyDhPhase1KeyGenOpData)); ++ ICP_CACHE_FREE(drvDH_zone, pPhase1OpData); ++ krp->krp_status = ECANCELED; ++ crypto_kdone(krp); ++ return; ++ } ++ ++ if (CPA_STATUS_SUCCESS == status) { ++ krp->krp_status = CRYPTO_OP_SUCCESS; ++ } else { ++ APRINTK("%s(): Diffie Hellman Phase1 Key Gen failed - " ++ "Operation Status = %d\n", __FUNCTION__, status); ++ krp->krp_status = ECANCELED; ++ } ++ ++ icp_ocfDrvSwapBytes(pLocalOctetStringPV->pData, ++ pLocalOctetStringPV->dataLenInBytes); ++ ++ icp_ocfDrvFreeFlatBuffer(pLocalOctetStringPV); ++ memset(pPhase1OpData, 0, sizeof(CpaCyDhPhase1KeyGenOpData)); ++ ICP_CACHE_FREE(drvDH_zone, pPhase1OpData); ++ ++ crypto_kdone(krp); ++ ++ return; ++} ++ ++/* Name : icp_ocfDrvModExpCallBack ++ * ++ * Description : When this function returns it signifies that the LAC ++ * component has completed the Mod Exp operation. ++ */ ++static void ++icp_ocfDrvModExpCallBack(void *callbackTag, ++ CpaStatus status, ++ void *pOpdata, CpaFlatBuffer * pResult) ++{ ++ struct cryptkop *krp = NULL; ++ CpaCyLnModExpOpData *pLnModExpOpData = NULL; ++ ++ if (NULL == callbackTag) { ++ DPRINTK("%s(): Invalid input parameters - " ++ "callbackTag data is NULL\n", __FUNCTION__); ++ return; ++ } ++ krp = (struct cryptkop *)callbackTag; ++ ++ if (NULL == pOpdata) { ++ DPRINTK("%s(): Invalid Mod Exp input parameters - " ++ "Operation Data is NULL\n", __FUNCTION__); ++ krp->krp_status = ECANCELED; ++ crypto_kdone(krp); ++ return; ++ } ++ pLnModExpOpData = (CpaCyLnModExpOpData *) pOpdata; ++ ++ if (NULL == pResult) { ++ DPRINTK("%s(): Invalid input parameters - " ++ "pResult data is NULL\n", __FUNCTION__); ++ krp->krp_status = ECANCELED; ++ memset(pLnModExpOpData, 0, sizeof(CpaCyLnModExpOpData)); ++ ICP_CACHE_FREE(drvLnModExp_zone, pLnModExpOpData); ++ crypto_kdone(krp); ++ return; ++ } ++ ++ if (CPA_STATUS_SUCCESS == status) { ++ krp->krp_status = CRYPTO_OP_SUCCESS; ++ } else { ++ APRINTK("%s(): LAC Mod Exp Operation failed - " ++ "Operation Status = %d\n", __FUNCTION__, status); ++ krp->krp_status = ECANCELED; ++ } ++ ++ icp_ocfDrvSwapBytes(pResult->pData, pResult->dataLenInBytes); ++ ++ /*switch base size value back to original */ ++ if (pLnModExpOpData->base.pData == ++ (uint8_t *) & (krp-> ++ krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX]. ++ crp_nbits)) { ++ *((uint32_t *) pLnModExpOpData->base.pData) = ++ ntohl(*((uint32_t *) pLnModExpOpData->base.pData)); ++ } ++ icp_ocfDrvFreeFlatBuffer(pResult); ++ memset(pLnModExpOpData, 0, sizeof(CpaCyLnModExpOpData)); ++ ICP_CACHE_FREE(drvLnModExp_zone, pLnModExpOpData); ++ ++ crypto_kdone(krp); ++ ++ return; ++ ++} ++ ++/* Name : icp_ocfDrvModExpCRTCallBack ++ * ++ * Description : When this function returns it signifies that the LAC ++ * component has completed the Mod Exp CRT operation. ++ */ ++static void ++icp_ocfDrvModExpCRTCallBack(void *callbackTag, ++ CpaStatus status, ++ void *pOpData, CpaFlatBuffer * pOutputData) ++{ ++ struct cryptkop *krp = NULL; ++ CpaCyRsaDecryptOpData *pDecryptData = NULL; ++ ++ if (NULL == callbackTag) { ++ DPRINTK("%s(): Invalid input parameters - " ++ "callbackTag data is NULL\n", __FUNCTION__); ++ return; ++ } ++ ++ krp = (struct cryptkop *)callbackTag; ++ ++ if (NULL == pOpData) { ++ DPRINTK("%s(): Invalid input parameters - " ++ "Operation Data is NULL\n", __FUNCTION__); ++ krp->krp_status = ECANCELED; ++ crypto_kdone(krp); ++ return; ++ } ++ pDecryptData = (CpaCyRsaDecryptOpData *) pOpData; ++ ++ if (NULL == pOutputData) { ++ DPRINTK("%s(): Invalid input parameter - " ++ "pOutputData is NULL\n", __FUNCTION__); ++ memset(pDecryptData->pRecipientPrivateKey, 0, ++ sizeof(CpaCyRsaPrivateKey)); ++ ICP_CACHE_FREE(drvRSAPrivateKey_zone, ++ pDecryptData->pRecipientPrivateKey); ++ memset(pDecryptData, 0, sizeof(CpaCyRsaDecryptOpData)); ++ ICP_CACHE_FREE(drvRSADecrypt_zone, pDecryptData); ++ krp->krp_status = ECANCELED; ++ crypto_kdone(krp); ++ return; ++ } ++ ++ if (CPA_STATUS_SUCCESS == status) { ++ krp->krp_status = CRYPTO_OP_SUCCESS; ++ } else { ++ APRINTK("%s(): LAC Mod Exp CRT operation failed - " ++ "Operation Status = %d\n", __FUNCTION__, status); ++ krp->krp_status = ECANCELED; ++ } ++ ++ icp_ocfDrvSwapBytes(pOutputData->pData, pOutputData->dataLenInBytes); ++ ++ icp_ocfDrvFreeFlatBuffer(pOutputData); ++ memset(pDecryptData->pRecipientPrivateKey, 0, ++ sizeof(CpaCyRsaPrivateKey)); ++ ICP_CACHE_FREE(drvRSAPrivateKey_zone, ++ pDecryptData->pRecipientPrivateKey); ++ memset(pDecryptData, 0, sizeof(CpaCyRsaDecryptOpData)); ++ ICP_CACHE_FREE(drvRSADecrypt_zone, pDecryptData); ++ ++ crypto_kdone(krp); ++ ++ return; ++} ++ ++/* Name : icp_ocfDrvDsaRSSignCallBack ++ * ++ * Description : When this function returns it signifies that the LAC ++ * component has completed the DSA RS sign operation. ++ */ ++static void ++icp_ocfDrvDsaRSSignCallBack(void *callbackTag, ++ CpaStatus status, ++ void *pOpData, ++ CpaBoolean protocolStatus, ++ CpaFlatBuffer * pR, CpaFlatBuffer * pS) ++{ ++ struct cryptkop *krp = NULL; ++ CpaCyDsaRSSignOpData *pSignData = NULL; ++ ++ if (NULL == callbackTag) { ++ DPRINTK("%s(): Invalid input parameters - " ++ "callbackTag data is NULL\n", __FUNCTION__); ++ return; ++ } ++ ++ krp = (struct cryptkop *)callbackTag; ++ ++ if (NULL == pOpData) { ++ DPRINTK("%s(): Invalid input parameters - " ++ "Operation Data is NULL\n", __FUNCTION__); ++ krp->krp_status = ECANCELED; ++ crypto_kdone(krp); ++ return; ++ } ++ pSignData = (CpaCyDsaRSSignOpData *) pOpData; ++ ++ if (NULL == pR) { ++ DPRINTK("%s(): Invalid input parameter - " ++ "pR sign is NULL\n", __FUNCTION__); ++ icp_ocfDrvFreeFlatBuffer(pS); ++ ICP_CACHE_FREE(drvDSARSSign_zone, pSignData); ++ krp->krp_status = ECANCELED; ++ crypto_kdone(krp); ++ return; ++ } ++ ++ if (NULL == pS) { ++ DPRINTK("%s(): Invalid input parameter - " ++ "pS sign is NULL\n", __FUNCTION__); ++ icp_ocfDrvFreeFlatBuffer(pR); ++ ICP_CACHE_FREE(drvDSARSSign_zone, pSignData); ++ krp->krp_status = ECANCELED; ++ crypto_kdone(krp); ++ return; ++ } ++ ++ if (CPA_STATUS_SUCCESS != status) { ++ APRINTK("%s(): LAC DSA RS Sign operation failed - " ++ "Operation Status = %d\n", __FUNCTION__, status); ++ krp->krp_status = ECANCELED; ++ } else { ++ krp->krp_status = CRYPTO_OP_SUCCESS; ++ ++ if (CPA_TRUE != protocolStatus) { ++ DPRINTK("%s(): LAC DSA RS Sign operation failed due " ++ "to protocol error\n", __FUNCTION__); ++ krp->krp_status = EIO; ++ } ++ } ++ ++ /* Swap bytes only when the callback status is successful and ++ protocolStatus is set to true */ ++ if (CPA_STATUS_SUCCESS == status && CPA_TRUE == protocolStatus) { ++ icp_ocfDrvSwapBytes(pR->pData, pR->dataLenInBytes); ++ icp_ocfDrvSwapBytes(pS->pData, pS->dataLenInBytes); ++ } ++ ++ icp_ocfDrvFreeFlatBuffer(pR); ++ icp_ocfDrvFreeFlatBuffer(pS); ++ memset(pSignData->K.pData, 0, pSignData->K.dataLenInBytes); ++ ICP_CACHE_FREE(drvDSARSSignKValue_zone, pSignData->K.pData); ++ memset(pSignData, 0, sizeof(CpaCyDsaRSSignOpData)); ++ ICP_CACHE_FREE(drvDSARSSign_zone, pSignData); ++ crypto_kdone(krp); ++ ++ return; ++} ++ ++/* Name : icp_ocfDrvDsaVerifyCallback ++ * ++ * Description : When this function returns it signifies that the LAC ++ * component has completed the DSA Verify operation. ++ */ ++static void ++icp_ocfDrvDsaVerifyCallBack(void *callbackTag, ++ CpaStatus status, ++ void *pOpData, CpaBoolean verifyStatus) ++{ ++ ++ struct cryptkop *krp = NULL; ++ CpaCyDsaVerifyOpData *pVerData = NULL; ++ ++ if (NULL == callbackTag) { ++ DPRINTK("%s(): Invalid input parameters - " ++ "callbackTag data is NULL\n", __FUNCTION__); ++ return; ++ } ++ ++ krp = (struct cryptkop *)callbackTag; ++ ++ if (NULL == pOpData) { ++ DPRINTK("%s(): Invalid input parameters - " ++ "Operation Data is NULL\n", __FUNCTION__); ++ krp->krp_status = ECANCELED; ++ crypto_kdone(krp); ++ return; ++ } ++ pVerData = (CpaCyDsaVerifyOpData *) pOpData; ++ ++ if (CPA_STATUS_SUCCESS != status) { ++ APRINTK("%s(): LAC DSA Verify operation failed - " ++ "Operation Status = %d\n", __FUNCTION__, status); ++ krp->krp_status = ECANCELED; ++ } else { ++ krp->krp_status = CRYPTO_OP_SUCCESS; ++ ++ if (CPA_TRUE != verifyStatus) { ++ DPRINTK("%s(): DSA signature invalid\n", __FUNCTION__); ++ krp->krp_status = EIO; ++ } ++ } ++ ++ /* Swap bytes only when the callback status is successful and ++ verifyStatus is set to true */ ++ /*Just swapping back the key values for now. Possibly all ++ swapped buffers need to be reverted */ ++ if (CPA_STATUS_SUCCESS == status && CPA_TRUE == verifyStatus) { ++ icp_ocfDrvSwapBytes(pVerData->R.pData, ++ pVerData->R.dataLenInBytes); ++ icp_ocfDrvSwapBytes(pVerData->S.pData, ++ pVerData->S.dataLenInBytes); ++ } ++ ++ memset(pVerData, 0, sizeof(CpaCyDsaVerifyOpData)); ++ ICP_CACHE_FREE(drvDSAVerify_zone, pVerData); ++ crypto_kdone(krp); ++ ++ return; ++} +diff -Nur linux-3.0.4.orig/crypto/ocf/ep80579/icp_common.c linux-3.0.4/crypto/ocf/ep80579/icp_common.c +--- linux-3.0.4.orig/crypto/ocf/ep80579/icp_common.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/ep80579/icp_common.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,773 @@ ++/************************************************************************* ++ * ++ * This file is provided under a dual BSD/GPLv2 license. When using or ++ * redistributing this file, you may do so under either license. ++ * ++ * GPL LICENSE SUMMARY ++ * ++ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ * The full GNU General Public License is included in this distribution ++ * in the file called LICENSE.GPL. ++ * ++ * Contact Information: ++ * Intel Corporation ++ * ++ * BSD LICENSE ++ * ++ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * * Neither the name of Intel Corporation nor the names of its ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * ++ * version: Security.L.1.0.2-229 ++ * ++ ***************************************************************************/ ++ ++/* ++ * An OCF module that uses Intel® QuickAssist Integrated Accelerator to do the ++ * crypto. ++ * ++ * This driver requires the ICP Access Library that is available from Intel in ++ * order to operate. ++ */ ++ ++#include "icp_ocf.h" ++ ++#define ICP_OCF_COMP_NAME "ICP_OCF" ++#define ICP_OCF_VER_MAIN (2) ++#define ICP_OCF_VER_MJR (1) ++#define ICP_OCF_VER_MNR (0) ++ ++#define MAX_DEREG_RETRIES (100) ++#define DEFAULT_DEREG_RETRIES (10) ++#define DEFAULT_DEREG_DELAY_IN_JIFFIES (10) ++ ++/* This defines the maximum number of sessions possible between OCF ++ and the OCF EP80579 Driver. If set to zero, there is no limit. */ ++#define DEFAULT_OCF_TO_DRV_MAX_SESSION_COUNT (0) ++#define NUM_SUPPORTED_CAPABILITIES (21) ++ ++/*Slab zone names*/ ++#define ICP_SESSION_DATA_NAME "icp_ocf.SesDat" ++#define ICP_OP_DATA_NAME "icp_ocf.OpDat" ++#define ICP_DH_NAME "icp_ocf.DH" ++#define ICP_MODEXP_NAME "icp_ocf.ModExp" ++#define ICP_RSA_DECRYPT_NAME "icp_ocf.RSAdec" ++#define ICP_RSA_PKEY_NAME "icp_ocf.RSApk" ++#define ICP_DSA_SIGN_NAME "icp_ocf.DSAsg" ++#define ICP_DSA_VER_NAME "icp_ocf.DSAver" ++#define ICP_RAND_VAL_NAME "icp_ocf.DSArnd" ++#define ICP_FLAT_BUFF_NAME "icp_ocf.FB" ++ ++/*Slabs zones*/ ++icp_kmem_cache drvSessionData_zone = NULL; ++icp_kmem_cache drvOpData_zone = NULL; ++icp_kmem_cache drvDH_zone = NULL; ++icp_kmem_cache drvLnModExp_zone = NULL; ++icp_kmem_cache drvRSADecrypt_zone = NULL; ++icp_kmem_cache drvRSAPrivateKey_zone = NULL; ++icp_kmem_cache drvDSARSSign_zone = NULL; ++icp_kmem_cache drvDSARSSignKValue_zone = NULL; ++icp_kmem_cache drvDSAVerify_zone = NULL; ++ ++/*Slab zones for flatbuffers and bufferlist*/ ++icp_kmem_cache drvFlatBuffer_zone = NULL; ++ ++static inline int icp_cache_null_check(void) ++{ ++ return (drvSessionData_zone && drvOpData_zone ++ && drvDH_zone && drvLnModExp_zone && drvRSADecrypt_zone ++ && drvRSAPrivateKey_zone && drvDSARSSign_zone ++ && drvDSARSSign_zone && drvDSARSSignKValue_zone ++ && drvDSAVerify_zone && drvFlatBuffer_zone); ++} ++ ++/*Function to free all allocated slab caches before exiting the module*/ ++static void icp_ocfDrvFreeCaches(void); ++ ++int32_t icp_ocfDrvDriverId = INVALID_DRIVER_ID; ++ ++/* Module parameter - gives the number of times LAC deregistration shall be ++ re-tried */ ++int num_dereg_retries = DEFAULT_DEREG_RETRIES; ++ ++/* Module parameter - gives the delay time in jiffies before a LAC session ++ shall be attempted to be deregistered again */ ++int dereg_retry_delay_in_jiffies = DEFAULT_DEREG_DELAY_IN_JIFFIES; ++ ++/* Module parameter - gives the maximum number of sessions possible between ++ OCF and the OCF EP80579 Driver. If set to zero, there is no limit.*/ ++int max_sessions = DEFAULT_OCF_TO_DRV_MAX_SESSION_COUNT; ++ ++/* This is set when the module is removed from the system, no further ++ processing can take place if this is set */ ++icp_atomic_t icp_ocfDrvIsExiting = ICP_ATOMIC_INIT(0); ++ ++/* This is used to show how many lac sessions were not deregistered*/ ++icp_atomic_t lac_session_failed_dereg_count = ICP_ATOMIC_INIT(0); ++ ++/* This is used to track the number of registered sessions between OCF and ++ * and the OCF EP80579 driver, when max_session is set to value other than ++ * zero. This ensures that the max_session set for the OCF and the driver ++ * is equal to the LAC registered sessions */ ++icp_atomic_t num_ocf_to_drv_registered_sessions = ICP_ATOMIC_INIT(0); ++ ++/* Head of linked list used to store session data */ ++icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead; ++icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead_FreeMemList; ++ ++icp_spinlock_t icp_ocfDrvSymSessInfoListSpinlock; ++ ++/*Below pointer is only used in linux, FreeBSD uses the name to ++create its own variable name*/ ++icp_workqueue *icp_ocfDrvFreeLacSessionWorkQ = NULL; ++ICP_WORKQUEUE_DEFINE_THREAD(icp_ocfDrvFreeLacSessionWorkQ); ++ ++struct icp_drvBuffListInfo defBuffListInfo; ++ ++/* Name : icp_ocfDrvInit ++ * ++ * Description : This function will register all the symmetric and asymmetric ++ * functionality that will be accelerated by the hardware. It will also ++ * get a unique driver ID from the OCF and initialise all slab caches ++ */ ++ICP_MODULE_INIT_FUNC(icp_ocfDrvInit) ++{ ++ int ocfStatus = 0; ++ ++ IPRINTK("=== %s ver %d.%d.%d ===\n", ICP_OCF_COMP_NAME, ++ ICP_OCF_VER_MAIN, ICP_OCF_VER_MJR, ICP_OCF_VER_MNR); ++ ++ if (MAX_DEREG_RETRIES < num_dereg_retries) { ++ EPRINTK("Session deregistration retry count set to greater " ++ "than %d", MAX_DEREG_RETRIES); ++ icp_module_return_code(EINVAL); ++ } ++ ++ /* Initialize and Start the Cryptographic component */ ++ if (CPA_STATUS_SUCCESS != ++ cpaCyStartInstance(CPA_INSTANCE_HANDLE_SINGLE)) { ++ EPRINTK("Failed to initialize and start the instance " ++ "of the Cryptographic component.\n"); ++ return icp_module_return_code(EINVAL); ++ } ++ ++ icp_spin_lock_init(&icp_ocfDrvSymSessInfoListSpinlock); ++ ++ /* Set the default size of BufferList to allocate */ ++ memset(&defBuffListInfo, 0, sizeof(struct icp_drvBuffListInfo)); ++ if (ICP_OCF_DRV_STATUS_SUCCESS != ++ icp_ocfDrvBufferListMemInfo(ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS, ++ &defBuffListInfo)) { ++ EPRINTK("Failed to get bufferlist memory info.\n"); ++ return icp_module_return_code(ENOMEM); ++ } ++ ++ /*Register OCF EP80579 Driver with OCF */ ++ icp_ocfDrvDriverId = ICP_CRYPTO_GET_DRIVERID(); ++ ++ if (icp_ocfDrvDriverId < 0) { ++ EPRINTK("%s : ICP driver failed to register with OCF!\n", ++ __FUNCTION__); ++ return icp_module_return_code(ENODEV); ++ } ++ ++ /*Create all the slab caches used by the OCF EP80579 Driver */ ++ drvSessionData_zone = ++ ICP_CACHE_CREATE(ICP_SESSION_DATA_NAME, struct icp_drvSessionData); ++ ++ /* ++ * Allocation of the OpData includes the allocation space for meta data. ++ * The memory after the opData structure is reserved for this meta data. ++ */ ++ drvOpData_zone = ++ icp_kmem_cache_create(ICP_OP_DATA_NAME, ++ sizeof(struct icp_drvOpData) + ++ defBuffListInfo.metaSize, ++ ICP_KERNEL_CACHE_ALIGN, ++ ICP_KERNEL_CACHE_NOINIT); ++ ++ drvDH_zone = ICP_CACHE_CREATE(ICP_DH_NAME, CpaCyDhPhase1KeyGenOpData); ++ ++ drvLnModExp_zone = ++ ICP_CACHE_CREATE(ICP_MODEXP_NAME, CpaCyLnModExpOpData); ++ ++ drvRSADecrypt_zone = ++ ICP_CACHE_CREATE(ICP_RSA_DECRYPT_NAME, CpaCyRsaDecryptOpData); ++ ++ drvRSAPrivateKey_zone = ++ ICP_CACHE_CREATE(ICP_RSA_PKEY_NAME, CpaCyRsaPrivateKey); ++ ++ drvDSARSSign_zone = ++ ICP_CACHE_CREATE(ICP_DSA_SIGN_NAME, CpaCyDsaRSSignOpData); ++ ++ /*too awkward to use a macro here */ ++ drvDSARSSignKValue_zone = ++ ICP_CACHE_CREATE(ICP_RAND_VAL_NAME, ++ DSA_RS_SIGN_PRIMEQ_SIZE_IN_BYTES); ++ ++ drvDSAVerify_zone = ++ ICP_CACHE_CREATE(ICP_DSA_VER_NAME, CpaCyDsaVerifyOpData); ++ ++ drvFlatBuffer_zone = ++ ICP_CACHE_CREATE(ICP_FLAT_BUFF_NAME, CpaFlatBuffer); ++ ++ if (0 == icp_cache_null_check()) { ++ icp_ocfDrvFreeCaches(); ++ EPRINTK("%s() line %d: Not enough memory!\n", ++ __FUNCTION__, __LINE__); ++ return ENOMEM; ++ } ++ ++ /* Register the ICP symmetric crypto support. */ ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_NULL_CBC, ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_DES_CBC, ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_3DES_CBC, ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_AES_CBC, ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_ARC4, ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_MD5, ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_MD5_HMAC, ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA1, ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA1_HMAC, ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_256, ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_256_HMAC, ++ ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_384, ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_384_HMAC, ++ ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_512, ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_512_HMAC, ++ ocfStatus); ++ ++ /* Register the ICP asymmetric algorithm support */ ++ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_DH_COMPUTE_KEY, ++ ocfStatus); ++ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_MOD_EXP, ocfStatus); ++ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_MOD_EXP_CRT, ocfStatus); ++ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_DSA_SIGN, ocfStatus); ++ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_DSA_VERIFY, ocfStatus); ++ ++ /* Register the ICP random number generator support */ ++ ICP_REG_RAND_WITH_OCF(icp_ocfDrvDriverId, ++ icp_ocfDrvReadRandom, NULL, ocfStatus); ++ ++ if (OCF_ZERO_FUNCTIONALITY_REGISTERED == ocfStatus) { ++ DPRINTK("%s: Failed to register any device capabilities\n", ++ __FUNCTION__); ++ icp_ocfDrvFreeCaches(); ++ icp_ocfDrvDriverId = INVALID_DRIVER_ID; ++ return icp_module_return_code(ECANCELED); ++ } ++ ++ DPRINTK("%s: Registered %d of %d device capabilities\n", ++ __FUNCTION__, ocfStatus, NUM_SUPPORTED_CAPABILITIES); ++ ++ /*Session data linked list used during module exit */ ++ ICP_INIT_LIST_HEAD(&icp_ocfDrvGlobalSymListHead); ++ ICP_INIT_LIST_HEAD(&icp_ocfDrvGlobalSymListHead_FreeMemList); ++ ++ ICP_WORKQUEUE_CREATE(icp_ocfDrvFreeLacSessionWorkQ, "icpwq"); ++ if (ICP_WORKQUEUE_NULL_CHECK(icp_ocfDrvFreeLacSessionWorkQ)) { ++ EPRINTK("%s: Failed to create single " ++ "thread workqueue\n", __FUNCTION__); ++ icp_ocfDrvFreeCaches(); ++ icp_ocfDrvDriverId = INVALID_DRIVER_ID; ++ return icp_module_return_code(ENOMEM); ++ } ++ ++ return icp_module_return_code(0); ++} ++ ++/* Name : icp_ocfDrvExit ++ * ++ * Description : This function will deregister all the symmetric sessions ++ * registered with the LAC component. It will also deregister all symmetric ++ * and asymmetric functionality that can be accelerated by the hardware via OCF ++ * and random number generation if it is enabled. ++ */ ++ICP_MODULE_EXIT_FUNC(icp_ocfDrvExit) ++{ ++ CpaStatus lacStatus = CPA_STATUS_SUCCESS; ++ struct icp_drvSessionData *sessionData = NULL; ++ struct icp_drvSessionData *tempSessionData = NULL; ++ int i, remaining_delay_time_in_jiffies = 0; ++ ++ /* For FreeBSD the invariant macro below makes function to return */ ++ /* with EBUSY value in the case of any session which has been regi- */ ++ /* stered with LAC not being deregistered. */ ++ /* The Linux implementation is empty since it is purely to compensate */ ++ /* for a limitation of the FreeBSD 7.1 Opencrypto framework. */ ++ ++ ICP_MODULE_EXIT_INV(); ++ ++ /* There is a possibility of a process or new session command being */ ++ /* sent before this variable is incremented. The aim of this variable */ ++ /* is to stop a loop of calls creating a deadlock situation which */ ++ /* would prevent the driver from exiting. */ ++ icp_atomic_set(&icp_ocfDrvIsExiting, 1); ++ ++ /*Existing sessions will be routed to another driver after these calls */ ++ crypto_unregister_all(icp_ocfDrvDriverId); ++ crypto_runregister_all(icp_ocfDrvDriverId); ++ ++ if (ICP_WORKQUEUE_NULL_CHECK(icp_ocfDrvFreeLacSessionWorkQ)) { ++ DPRINTK("%s: workqueue already " ++ "destroyed, therefore module exit " ++ " function already called. Exiting.\n", __FUNCTION__); ++ return ICP_MODULE_EXIT_FUNC_RETURN_VAL; ++ } ++ /*If any sessions are waiting to be deregistered, do that. This also ++ flushes the work queue */ ++ ICP_WORKQUEUE_DESTROY(icp_ocfDrvFreeLacSessionWorkQ); ++ ++ /*ENTER CRITICAL SECTION */ ++ icp_spin_lockbh_lock(&icp_ocfDrvSymSessInfoListSpinlock); ++ ++ ICP_LIST_FOR_EACH_ENTRY_SAFE(tempSessionData, sessionData, ++ &icp_ocfDrvGlobalSymListHead, listNode) { ++ for (i = 0; i < num_dereg_retries; i++) { ++ /*No harm if bad input - LAC will handle error cases */ ++ if (ICP_SESSION_RUNNING == tempSessionData->inUse) { ++ lacStatus = ++ cpaCySymRemoveSession ++ (CPA_INSTANCE_HANDLE_SINGLE, ++ tempSessionData->sessHandle); ++ if (CPA_STATUS_SUCCESS == lacStatus) { ++ /* Succesfully deregistered */ ++ break; ++ } else if (CPA_STATUS_RETRY != lacStatus) { ++ icp_atomic_inc ++ (&lac_session_failed_dereg_count); ++ break; ++ } ++ ++ /*schedule_timout returns the time left for completion if ++ * this task is set to TASK_INTERRUPTIBLE */ ++ remaining_delay_time_in_jiffies = ++ dereg_retry_delay_in_jiffies; ++ while (0 > remaining_delay_time_in_jiffies) { ++ remaining_delay_time_in_jiffies = ++ icp_schedule_timeout ++ (&icp_ocfDrvSymSessInfoListSpinlock, ++ remaining_delay_time_in_jiffies); ++ } ++ ++ DPRINTK ++ ("%s(): Retry %d to deregistrate the session\n", ++ __FUNCTION__, i); ++ } ++ } ++ ++ /*remove from current list */ ++ ICP_LIST_DEL(tempSessionData, listNode); ++ /*add to free mem linked list */ ++ ICP_LIST_ADD(tempSessionData, ++ &icp_ocfDrvGlobalSymListHead_FreeMemList, ++ listNode); ++ ++ } ++ ++ /*EXIT CRITICAL SECTION */ ++ icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock); ++ ++ /*set back to initial values */ ++ sessionData = NULL; ++ /*still have a reference in our list! */ ++ tempSessionData = NULL; ++ /*free memory */ ++ ++ ICP_LIST_FOR_EACH_ENTRY_SAFE(tempSessionData, sessionData, ++ &icp_ocfDrvGlobalSymListHead_FreeMemList, ++ listNode) { ++ ++ ICP_LIST_DEL(tempSessionData, listNode); ++ /* Free allocated CpaCySymSessionCtx */ ++ if (NULL != tempSessionData->sessHandle) { ++ icp_kfree(tempSessionData->sessHandle); ++ } ++ memset(tempSessionData, 0, sizeof(struct icp_drvSessionData)); ++ ICP_CACHE_FREE(drvSessionData_zone, tempSessionData); ++ } ++ ++ if (0 != icp_atomic_read(&lac_session_failed_dereg_count)) { ++ DPRINTK("%s(): %d LAC sessions were not deregistered " ++ "correctly. This is not a clean exit! \n", ++ __FUNCTION__, ++ icp_atomic_read(&lac_session_failed_dereg_count)); ++ } ++ ++ icp_ocfDrvFreeCaches(); ++ icp_ocfDrvDriverId = INVALID_DRIVER_ID; ++ ++ icp_spin_lock_destroy(&icp_ocfDrvSymSessInfoListSpinlock); ++ ++ /* Shutdown the Cryptographic component */ ++ lacStatus = cpaCyStopInstance(CPA_INSTANCE_HANDLE_SINGLE); ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ DPRINTK("%s(): Failed to stop instance of the " ++ "Cryptographic component.(status == %d)\n", ++ __FUNCTION__, lacStatus); ++ } ++ ++ return ICP_MODULE_EXIT_FUNC_RETURN_VAL; ++} ++ ++/* Name : icp_ocfDrvFreeCaches ++ * ++ * Description : This function deregisters all slab caches ++ */ ++static void icp_ocfDrvFreeCaches(void) ++{ ++ icp_atomic_set(&icp_ocfDrvIsExiting, 1); ++ ++ /*Sym Zones */ ++ ICP_CACHE_DESTROY(drvSessionData_zone); ++ ICP_CACHE_DESTROY(drvOpData_zone); ++ ++ /*Asym zones */ ++ ICP_CACHE_DESTROY(drvDH_zone); ++ ICP_CACHE_DESTROY(drvLnModExp_zone); ++ ICP_CACHE_DESTROY(drvRSADecrypt_zone); ++ ICP_CACHE_DESTROY(drvRSAPrivateKey_zone); ++ ICP_CACHE_DESTROY(drvDSARSSignKValue_zone); ++ ICP_CACHE_DESTROY(drvDSARSSign_zone); ++ ICP_CACHE_DESTROY(drvDSAVerify_zone); ++ ++ /*FlatBuffer and BufferList Zones */ ++ ICP_CACHE_DESTROY(drvFlatBuffer_zone); ++ ++} ++ ++/* Name : icp_ocfDrvDeregRetry ++ * ++ * Description : This function will try to farm the session deregistration ++ * off to a work queue. If it fails, nothing more can be done and it ++ * returns an error ++ */ ++int icp_ocfDrvDeregRetry(CpaCySymSessionCtx sessionToDeregister) ++{ ++ struct icp_ocfDrvFreeLacSession *workstore = NULL; ++ ++ DPRINTK("%s(): Retry - Deregistering session (%p)\n", ++ __FUNCTION__, sessionToDeregister); ++ ++ /*make sure the session is not available to be allocated during this ++ process */ ++ icp_atomic_inc(&lac_session_failed_dereg_count); ++ ++ /*Farm off to work queue */ ++ workstore = ++ icp_kmalloc(sizeof(struct icp_ocfDrvFreeLacSession), ICP_M_NOWAIT); ++ if (NULL == workstore) { ++ DPRINTK("%s(): unable to free session - no memory available " ++ "for work queue\n", __FUNCTION__); ++ return ENOMEM; ++ } ++ ++ workstore->sessionToDeregister = sessionToDeregister; ++ ++ icp_init_work(&(workstore->work), ++ icp_ocfDrvDeferedFreeLacSessionTaskFn, workstore); ++ ++ ICP_WORKQUEUE_ENQUEUE(icp_ocfDrvFreeLacSessionWorkQ, ++ &(workstore->work)); ++ ++ return ICP_OCF_DRV_STATUS_SUCCESS; ++ ++} ++ ++/* Name : icp_ocfDrvDeferedFreeLacSessionProcess ++ * ++ * Description : This function will retry (module input parameter) ++ * 'num_dereg_retries' times to deregister any symmetric session that recieves a ++ * CPA_STATUS_RETRY message from the LAC component. This function is run in ++ * Thread context because it is called from a worker thread ++ */ ++void icp_ocfDrvDeferedFreeLacSessionProcess(void *arg) ++{ ++ struct icp_ocfDrvFreeLacSession *workstore = NULL; ++ CpaCySymSessionCtx sessionToDeregister = NULL; ++ int i = 0; ++ int remaining_delay_time_in_jiffies = 0; ++ CpaStatus lacStatus = CPA_STATUS_SUCCESS; ++ ++ workstore = (struct icp_ocfDrvFreeLacSession *)arg; ++ if (NULL == workstore) { ++ DPRINTK("%s() function called with null parameter \n", ++ __FUNCTION__); ++ return; ++ } ++ ++ sessionToDeregister = workstore->sessionToDeregister; ++ icp_kfree(workstore); ++ ++ /*if exiting, give deregistration one more blast only */ ++ if (icp_atomic_read(&icp_ocfDrvIsExiting) == CPA_TRUE) { ++ lacStatus = cpaCySymRemoveSession(CPA_INSTANCE_HANDLE_SINGLE, ++ sessionToDeregister); ++ ++ if (lacStatus != CPA_STATUS_SUCCESS) { ++ DPRINTK("%s() Failed to Dereg LAC session %p " ++ "during module exit\n", __FUNCTION__, ++ sessionToDeregister); ++ return; ++ } ++ ++ icp_atomic_dec(&lac_session_failed_dereg_count); ++ return; ++ } ++ ++ for (i = 0; i <= num_dereg_retries; i++) { ++ lacStatus = cpaCySymRemoveSession(CPA_INSTANCE_HANDLE_SINGLE, ++ sessionToDeregister); ++ ++ if (lacStatus == CPA_STATUS_SUCCESS) { ++ icp_atomic_dec(&lac_session_failed_dereg_count); ++ return; ++ } ++ if (lacStatus != CPA_STATUS_RETRY) { ++ DPRINTK("%s() Failed to deregister session - lacStatus " ++ " = %d", __FUNCTION__, lacStatus); ++ break; ++ } ++ ++ /*schedule_timout returns the time left for completion if this ++ task is set to TASK_INTERRUPTIBLE */ ++ remaining_delay_time_in_jiffies = dereg_retry_delay_in_jiffies; ++ while (0 < remaining_delay_time_in_jiffies) { ++ remaining_delay_time_in_jiffies = ++ icp_schedule_timeout(NULL, ++ remaining_delay_time_in_jiffies); ++ } ++ ++ } ++ ++ DPRINTK("%s(): Unable to deregister session\n", __FUNCTION__); ++ DPRINTK("%s(): Number of unavailable LAC sessions = %d\n", __FUNCTION__, ++ icp_atomic_read(&lac_session_failed_dereg_count)); ++} ++ ++/* Name : icp_ocfDrvPtrAndLenToFlatBuffer ++ * ++ * Description : This function converts a "pointer and length" buffer ++ * structure to Fredericksburg Flat Buffer (CpaFlatBuffer) format. ++ * ++ * This function assumes that the data passed in are valid. ++ */ ++inline void ++icp_ocfDrvPtrAndLenToFlatBuffer(void *pData, uint32_t len, ++ CpaFlatBuffer * pFlatBuffer) ++{ ++ pFlatBuffer->pData = pData; ++ pFlatBuffer->dataLenInBytes = len; ++} ++ ++/* Name : icp_ocfDrvPtrAndLenToBufferList ++ * ++ * Description : This function converts a "pointer and length" buffer ++ * structure to Fredericksburg Scatter/Gather Buffer (CpaBufferList) format. ++ * ++ * This function assumes that the data passed in are valid. ++ */ ++inline void ++icp_ocfDrvPtrAndLenToBufferList(void *pDataIn, uint32_t length, ++ CpaBufferList * pBufferList) ++{ ++ pBufferList->numBuffers = 1; ++ pBufferList->pBuffers->pData = pDataIn; ++ pBufferList->pBuffers->dataLenInBytes = length; ++} ++ ++/* Name : icp_ocfDrvBufferListToPtrAndLen ++ * ++ * Description : This function converts Fredericksburg Scatter/Gather Buffer ++ * (CpaBufferList) format to a "pointer and length" buffer structure. ++ * ++ * This function assumes that the data passed in are valid. ++ */ ++inline void ++icp_ocfDrvBufferListToPtrAndLen(CpaBufferList * pBufferList, ++ void **ppDataOut, uint32_t * pLength) ++{ ++ *ppDataOut = pBufferList->pBuffers->pData; ++ *pLength = pBufferList->pBuffers->dataLenInBytes; ++} ++ ++/* Name : icp_ocfDrvBufferListMemInfo ++ * ++ * Description : This function will set the number of flat buffers in ++ * bufferlist, the size of memory to allocate for the pPrivateMetaData ++ * member of the CpaBufferList. ++ */ ++int ++icp_ocfDrvBufferListMemInfo(uint16_t numBuffers, ++ struct icp_drvBuffListInfo *buffListInfo) ++{ ++ buffListInfo->numBuffers = numBuffers; ++ ++ if (CPA_STATUS_SUCCESS != ++ cpaCyBufferListGetMetaSize(CPA_INSTANCE_HANDLE_SINGLE, ++ buffListInfo->numBuffers, ++ &(buffListInfo->metaSize))) { ++ EPRINTK("%s() Failed to get buffer list meta size.\n", ++ __FUNCTION__); ++ return ICP_OCF_DRV_STATUS_FAIL; ++ } ++ ++ return ICP_OCF_DRV_STATUS_SUCCESS; ++} ++ ++/* Name : icp_ocfDrvFreeFlatBuffer ++ * ++ * Description : This function will deallocate flat buffer. ++ */ ++inline void icp_ocfDrvFreeFlatBuffer(CpaFlatBuffer * pFlatBuffer) ++{ ++ if (pFlatBuffer != NULL) { ++ memset(pFlatBuffer, 0, sizeof(CpaFlatBuffer)); ++ ICP_CACHE_FREE(drvFlatBuffer_zone, pFlatBuffer); ++ } ++} ++ ++/* Name : icp_ocfDrvAllocMetaData ++ * ++ * Description : This function will allocate memory for the ++ * pPrivateMetaData member of CpaBufferList. ++ */ ++inline int ++icp_ocfDrvAllocMetaData(CpaBufferList * pBufferList, ++ struct icp_drvOpData *pOpData) ++{ ++ Cpa32U metaSize = 0; ++ ++ if (pBufferList->numBuffers <= ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) { ++ uint8_t *pOpDataStartAddr = (uint8_t *) pOpData; ++ ++ if (0 == defBuffListInfo.metaSize) { ++ pBufferList->pPrivateMetaData = NULL; ++ return ICP_OCF_DRV_STATUS_SUCCESS; ++ } ++ /* ++ * The meta data allocation has been included as part of the ++ * op data. It has been pre-allocated in memory just after the ++ * icp_drvOpData structure. ++ */ ++ pBufferList->pPrivateMetaData = (void *)(pOpDataStartAddr + ++ sizeof(struct ++ icp_drvOpData)); ++ } else { ++ if (CPA_STATUS_SUCCESS != ++ cpaCyBufferListGetMetaSize(CPA_INSTANCE_HANDLE_SINGLE, ++ pBufferList->numBuffers, ++ &metaSize)) { ++ EPRINTK("%s() Failed to get buffer list meta size.\n", ++ __FUNCTION__); ++ return ICP_OCF_DRV_STATUS_FAIL; ++ } ++ ++ if (0 == metaSize) { ++ pBufferList->pPrivateMetaData = NULL; ++ return ICP_OCF_DRV_STATUS_SUCCESS; ++ } ++ ++ pBufferList->pPrivateMetaData = ++ icp_kmalloc(metaSize, ICP_M_NOWAIT); ++ } ++ if (NULL == pBufferList->pPrivateMetaData) { ++ EPRINTK("%s() Failed to allocate pPrivateMetaData.\n", ++ __FUNCTION__); ++ return ICP_OCF_DRV_STATUS_FAIL; ++ } ++ ++ return ICP_OCF_DRV_STATUS_SUCCESS; ++} ++ ++/* Name : icp_ocfDrvFreeMetaData ++ * ++ * Description : This function will deallocate pPrivateMetaData memory. ++ */ ++inline void icp_ocfDrvFreeMetaData(CpaBufferList * pBufferList) ++{ ++ if (NULL == pBufferList->pPrivateMetaData) { ++ return; ++ } ++ ++ /* ++ * Only free the meta data if the BufferList has more than ++ * ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS number of buffers. ++ * Otherwise, the meta data shall be freed when the icp_drvOpData is ++ * freed. ++ */ ++ if (ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS < pBufferList->numBuffers) { ++ icp_kfree(pBufferList->pPrivateMetaData); ++ } ++} ++ ++/* Module declaration, init and exit functions */ ++ICP_DECLARE_MODULE(icp_ocf, icp_ocfDrvInit, icp_ocfDrvExit); ++ICP_MODULE_DESCRIPTION("OCF Driver for Intel Quick Assist crypto acceleration"); ++ICP_MODULE_VERSION(icp_ocf, ICP_OCF_VER_MJR); ++ICP_MODULE_LICENSE("Dual BSD/GPL"); ++ICP_MODULE_AUTHOR("Intel"); ++ ++/* Module parameters */ ++ICP_MODULE_PARAM_INT(icp_ocf, num_dereg_retries, ++ "Number of times to retry LAC Sym Session Deregistration. " ++ "Default 10, Max 100"); ++ICP_MODULE_PARAM_INT(icp_ocf, dereg_retry_delay_in_jiffies, "Delay in jiffies " ++ "(added to a schedule() function call) before a LAC Sym " ++ "Session Dereg is retried. Default 10"); ++ICP_MODULE_PARAM_INT(icp_ocf, max_sessions, ++ "This sets the maximum number of sessions " ++ "between OCF and this driver. If this value is set to zero," ++ "max session count checking is disabled. Default is zero(0)"); ++ ++/* Module dependencies */ ++#define MODULE_MIN_VER 1 ++#define CRYPTO_MAX_VER 3 ++#define LAC_MAX_VER 2 ++ ++ICP_MODULE_DEPEND(icp_ocf, crypto, MODULE_MIN_VER, MODULE_MIN_VER, ++ CRYPTO_MAX_VER); ++ICP_MODULE_DEPEND(icp_ocf, cryptodev, MODULE_MIN_VER, MODULE_MIN_VER, ++ CRYPTO_MAX_VER); ++ICP_MODULE_DEPEND(icp_ocf, icp_crypto, MODULE_MIN_VER, MODULE_MIN_VER, ++ LAC_MAX_VER); +diff -Nur linux-3.0.4.orig/crypto/ocf/ep80579/icp_ocf.h linux-3.0.4/crypto/ocf/ep80579/icp_ocf.h +--- linux-3.0.4.orig/crypto/ocf/ep80579/icp_ocf.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/ep80579/icp_ocf.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,376 @@ ++/*************************************************************************** ++ * ++ * This file is provided under a dual BSD/GPLv2 license. When using or ++ * redistributing this file, you may do so under either license. ++ * ++ * GPL LICENSE SUMMARY ++ * ++ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ * The full GNU General Public License is included in this distribution ++ * in the file called LICENSE.GPL. ++ * ++ * Contact Information: ++ * Intel Corporation ++ * ++ * BSD LICENSE ++ * ++ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * * Neither the name of Intel Corporation nor the names of its ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * ++ * version: Security.L.1.0.2-229 ++ * ++ ***************************************************************************/ ++ ++/* ++ * OCF driver header file for the Intel ICP processor. ++ */ ++ ++#ifndef ICP_OCF_H_ ++#define ICP_OCF_H_ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "icp_os.h" ++ ++#define NUM_BITS_IN_BYTE (8) ++#define NUM_BITS_IN_BYTE_MINUS_ONE (NUM_BITS_IN_BYTE -1) ++#define INVALID_DRIVER_ID (-1) ++#define RETURN_RAND_NUM_GEN_FAILED (-1) ++ ++/*This is the max block cipher initialisation vector*/ ++#define MAX_IV_LEN_IN_BYTES (20) ++/*This is used to check whether the OCF to this driver session limit has ++ been disabled*/ ++#define NO_OCF_TO_DRV_MAX_SESSIONS (0) ++ ++/*OCF values mapped here*/ ++#define ICP_SHA1_DIGEST_SIZE_IN_BYTES (SHA1_HASH_LEN) ++#define ICP_SHA256_DIGEST_SIZE_IN_BYTES (SHA2_256_HASH_LEN) ++#define ICP_SHA384_DIGEST_SIZE_IN_BYTES (SHA2_384_HASH_LEN) ++#define ICP_SHA512_DIGEST_SIZE_IN_BYTES (SHA2_512_HASH_LEN) ++#define ICP_MD5_DIGEST_SIZE_IN_BYTES (MD5_HASH_LEN) ++#define ARC4_COUNTER_LEN (ARC4_BLOCK_LEN) ++ ++#define OCF_REGISTRATION_STATUS_SUCCESS (0) ++#define OCF_ZERO_FUNCTIONALITY_REGISTERED (0) ++#define ICP_OCF_DRV_NO_CRYPTO_PROCESS_ERROR (0) ++#define ICP_OCF_DRV_STATUS_SUCCESS (0) ++#define ICP_OCF_DRV_STATUS_FAIL (1) ++ ++/*Turn on/off debug options*/ ++#define ICP_OCF_PRINT_DEBUG_MESSAGES (0) ++#define ICP_OCF_PRINT_KERN_ALERT (1) ++#define ICP_OCF_PRINT_KERN_ERRS (1) ++ ++#if ICP_OCF_PRINT_DEBUG_MESSAGES == 1 ++#define DPRINTK(args...) \ ++{ \ ++ ICP_IPRINTK(args); \ ++} ++ ++#else //ICP_OCF_PRINT_DEBUG_MESSAGES == 1 ++ ++#define DPRINTK(args...) ++ ++#endif //ICP_OCF_PRINT_DEBUG_MESSAGES == 1 ++ ++#if ICP_OCF_PRINT_KERN_ALERT == 1 ++#define APRINTK(args...) \ ++{ \ ++ ICP_APRINTK(args); \ ++} ++ ++#else //ICP_OCF_PRINT_KERN_ALERT == 1 ++ ++#define APRINTK(args...) ++ ++#endif //ICP_OCF_PRINT_KERN_ALERT == 1 ++ ++#if ICP_OCF_PRINT_KERN_ERRS == 1 ++#define EPRINTK(args...) \ ++{ \ ++ ICP_EPRINTK(args); \ ++} ++ ++#else //ICP_OCF_PRINT_KERN_ERRS == 1 ++ ++#define EPRINTK(args...) ++ ++#endif //ICP_OCF_PRINT_KERN_ERRS == 1 ++ ++#define IPRINTK(args...) \ ++{ \ ++ ICP_IPRINTK(args); \ ++} ++ ++/*DSA Prime Q size in bytes (as defined in the standard) */ ++#define DSA_RS_SIGN_PRIMEQ_SIZE_IN_BYTES (20) ++ ++#define BITS_TO_BYTES(bytes, bits) \ ++ bytes = (bits + NUM_BITS_IN_BYTE_MINUS_ONE) / NUM_BITS_IN_BYTE ++ ++typedef enum { ++ ICP_OCF_DRV_ALG_CIPHER = 0, ++ ICP_OCF_DRV_ALG_HASH ++} icp_ocf_drv_alg_type_t; ++ ++typedef ICP_LIST_HEAD(icp_drvSessionListHead_s, ++ icp_drvSessionData) icp_drvSessionListHead_t; ++ ++/*Values used to derisk chances of performs being called against ++deregistered sessions (for which the slab page has been reclaimed) ++This is not a fix - since page frames are reclaimed from a slab, one cannot ++rely on that memory not being re-used by another app.*/ ++typedef enum { ++ ICP_SESSION_INITIALISED = 0x5C5C5C, ++ ICP_SESSION_RUNNING = 0x005C00, ++ ICP_SESSION_DEREGISTERED = 0xC5C5C5 ++} usage_derisk; ++ ++/* This struct is required for deferred session ++ deregistration as a work queue function can ++ only have one argument*/ ++struct icp_ocfDrvFreeLacSession { ++ CpaCySymSessionCtx sessionToDeregister; ++ icp_workstruct work; ++}; ++ ++/* ++This is the OCF<->OCF_DRV session object: ++ ++1.listNode ++ The first member is a listNode. These session objects are added to a linked ++ list in order to make it easier to remove them all at session exit time. ++ ++2.inUse ++ The second member is used to give the session object state and derisk the ++ possibility of OCF batch calls executing against a deregistered session (as ++ described above). ++ ++3.sessHandle ++ The third member is a LAC<->OCF_DRV session handle (initialised with the first ++ perform request for that session). ++ ++4.lacSessCtx ++ The fourth is the LAC session context. All the parameters for this structure ++ are only known when the first perform request for this session occurs. That is ++ why the OCF EP80579 Driver only registers a new LAC session at perform time ++*/ ++struct icp_drvSessionData { ++ ICP_LIST_ENTRY(icp_drvSessionData) listNode; ++ usage_derisk inUse; ++ CpaCySymSessionCtx sessHandle; ++ CpaCySymSessionSetupData lacSessCtx; ++}; ++ ++/* These are all defined in icp_common.c */ ++extern icp_atomic_t lac_session_failed_dereg_count; ++extern icp_atomic_t icp_ocfDrvIsExiting; ++extern icp_atomic_t num_ocf_to_drv_registered_sessions; ++ ++extern int32_t icp_ocfDrvDriverId; ++ ++extern icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead; ++extern icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead_FreeMemList; ++extern icp_workqueue *icp_ocfDrvFreeLacSessionWorkQ; ++extern icp_spinlock_t icp_ocfDrvSymSessInfoListSpinlock; ++ ++/*Slab zones for symettric functionality, instantiated in icp_common.c*/ ++extern icp_kmem_cache drvSessionData_zone; ++extern icp_kmem_cache drvOpData_zone; ++ ++/*Slabs zones for asymettric functionality, instantiated in icp_common.c*/ ++extern icp_kmem_cache drvDH_zone; ++extern icp_kmem_cache drvLnModExp_zone; ++extern icp_kmem_cache drvRSADecrypt_zone; ++extern icp_kmem_cache drvRSAPrivateKey_zone; ++extern icp_kmem_cache drvDSARSSign_zone; ++extern icp_kmem_cache drvDSARSSignKValue_zone; ++extern icp_kmem_cache drvDSAVerify_zone; ++ ++/* Module parameters defined in icp_cpmmon.c*/ ++ ++/* Module parameters - gives the number of times LAC deregistration shall be ++ re-tried */ ++extern int num_dereg_retries; ++ ++/* Module parameter - gives the delay time in jiffies before a LAC session ++ shall be attempted to be deregistered again */ ++extern int dereg_retry_delay_in_jiffies; ++ ++/* Module parameter - gives the maximum number of sessions possible between ++ OCF and the OCF EP80579 Driver. If set to zero, there is no limit.*/ ++extern int max_sessions; ++ ++/*Slab zones for flatbuffers and bufferlist*/ ++extern icp_kmem_cache drvFlatBuffer_zone; ++ ++#define ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS (16) ++ ++struct icp_drvBuffListInfo { ++ Cpa16U numBuffers; ++ Cpa32U metaSize; ++ Cpa32U metaOffset; ++ Cpa32U buffListSize; ++}; ++ ++extern struct icp_drvBuffListInfo defBuffListInfo; ++ ++/* This struct is used to keep a reference to the relevant node in the list ++ of sessionData structs, to the buffer type required by OCF and to the OCF ++ provided crp struct that needs to be returned. All this info is needed in ++ the callback function.*/ ++struct icp_drvOpData { ++ CpaCySymOpData lacOpData; ++ uint32_t digestSizeInBytes; ++ struct cryptop *crp; ++ uint8_t bufferType; ++ uint8_t ivData[MAX_IV_LEN_IN_BYTES]; ++ uint16_t numBufferListArray; ++ CpaBufferList srcBuffer; ++ CpaFlatBuffer bufferListArray[ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS]; ++ CpaBoolean verifyResult; ++}; ++ ++/* Create a new session between OCF and this driver*/ ++int icp_ocfDrvNewSession(icp_device_t dev, uint32_t * sild, ++ struct cryptoini *cri); ++ ++/* Free a session between this driver and the Quick Assist Framework*/ ++int icp_ocfDrvFreeLACSession(icp_device_t dev, uint64_t sid); ++ ++/* Defer freeing a Quick Assist session*/ ++void icp_ocfDrvDeferedFreeLacSessionProcess(void *arg); ++ ++/* Process OCF cryptographic request for a symmetric algorithm*/ ++int icp_ocfDrvSymProcess(icp_device_t dev, struct cryptop *crp, int hint); ++ ++/* Process OCF cryptographic request for an asymmetric algorithm*/ ++int icp_ocfDrvPkeProcess(icp_device_t dev, struct cryptkop *krp, int hint); ++ ++/* Populate a buffer with random data*/ ++int icp_ocfDrvReadRandom(void *arg, uint32_t * buf, int maxwords); ++ ++/* Retry Quick Assist session deregistration*/ ++int icp_ocfDrvDeregRetry(CpaCySymSessionCtx sessionToDeregister); ++ ++/* Convert an OS scatter gather list to a CPA buffer list*/ ++int icp_ocfDrvPacketBuffToBufferList(icp_packet_buffer_t * pPacketBuffer, ++ CpaBufferList * bufferList); ++ ++/* Convert a CPA buffer list to an OS scatter gather list*/ ++int icp_ocfDrvBufferListToPacketBuff(CpaBufferList * bufferList, ++ icp_packet_buffer_t ** pPacketBuffer); ++ ++/* Get the number of buffers in an OS scatter gather list*/ ++uint16_t icp_ocfDrvGetPacketBuffFrags(icp_packet_buffer_t * pPacketBuffer); ++ ++/* Convert a single OS buffer to a CPA Flat Buffer*/ ++void icp_ocfDrvSinglePacketBuffToFlatBuffer(icp_packet_buffer_t * pPacketBuffer, ++ CpaFlatBuffer * pFlatBuffer); ++ ++/* Add pointer and length to a CPA Flat Buffer structure*/ ++void icp_ocfDrvPtrAndLenToFlatBuffer(void *pData, uint32_t len, ++ CpaFlatBuffer * pFlatBuffer); ++ ++/* Convert pointer and length values to a CPA buffer list*/ ++void icp_ocfDrvPtrAndLenToBufferList(void *pDataIn, uint32_t length, ++ CpaBufferList * pBufferList); ++ ++/* Convert a CPA buffer list to pointer and length values*/ ++void icp_ocfDrvBufferListToPtrAndLen(CpaBufferList * pBufferList, ++ void **ppDataOut, uint32_t * pLength); ++ ++/* Set the number of flat buffers in bufferlist and the size of memory ++ to allocate for the pPrivateMetaData member of the CpaBufferList.*/ ++int icp_ocfDrvBufferListMemInfo(uint16_t numBuffers, ++ struct icp_drvBuffListInfo *buffListInfo); ++ ++/* Find pointer position of the digest within an OS scatter gather list*/ ++uint8_t *icp_ocfDrvPacketBufferDigestPointerFind(struct icp_drvOpData ++ *drvOpData, ++ int offsetInBytes, ++ uint32_t digestSizeInBytes); ++ ++/*This top level function is used to find a pointer to where a digest is ++ stored/needs to be inserted. */ ++uint8_t *icp_ocfDrvDigestPointerFind(struct icp_drvOpData *drvOpData, ++ struct cryptodesc *crp_desc); ++ ++/* Free a CPA flat buffer*/ ++void icp_ocfDrvFreeFlatBuffer(CpaFlatBuffer * pFlatBuffer); ++ ++/* This function will allocate memory for the pPrivateMetaData ++ member of CpaBufferList. */ ++int icp_ocfDrvAllocMetaData(CpaBufferList * pBufferList, ++ struct icp_drvOpData *pOpData); ++ ++/* Free data allocated for the pPrivateMetaData ++ member of CpaBufferList.*/ ++void icp_ocfDrvFreeMetaData(CpaBufferList * pBufferList); ++ ++#define ICP_CACHE_CREATE(cache_ID, cache_name) \ ++ icp_kmem_cache_create(cache_ID, sizeof(cache_name),ICP_KERNEL_CACHE_ALIGN,\ ++ ICP_KERNEL_CACHE_NOINIT) ++ ++#define ICP_CACHE_FREE(args...) \ ++ icp_kmem_cache_free (args) ++ ++#define ICP_CACHE_DESTROY(slab_zone)\ ++{\ ++ if(NULL != slab_zone){\ ++ icp_kmem_cache_destroy(slab_zone);\ ++ slab_zone = NULL;\ ++ }\ ++} ++ ++#endif ++/* ICP_OCF_H_ */ +diff -Nur linux-3.0.4.orig/crypto/ocf/ep80579/icp_sym.c linux-3.0.4/crypto/ocf/ep80579/icp_sym.c +--- linux-3.0.4.orig/crypto/ocf/ep80579/icp_sym.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/ep80579/icp_sym.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,1153 @@ ++/*************************************************************************** ++ * ++ * This file is provided under a dual BSD/GPLv2 license. When using or ++ * redistributing this file, you may do so under either license. ++ * ++ * GPL LICENSE SUMMARY ++ * ++ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ * The full GNU General Public License is included in this distribution ++ * in the file called LICENSE.GPL. ++ * ++ * Contact Information: ++ * Intel Corporation ++ * ++ * BSD LICENSE ++ * ++ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * * Neither the name of Intel Corporation nor the names of its ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * ++ * version: Security.L.1.0.2-229 ++ * ++ ***************************************************************************/ ++/* ++ * An OCF module that uses the API for Intel® QuickAssist Technology to do the ++ * cryptography. ++ * ++ * This driver requires the ICP Access Library that is available from Intel in ++ * order to operate. ++ */ ++ ++#include "icp_ocf.h" ++ ++/*This is the call back function for all symmetric cryptographic processes. ++ Its main functionality is to free driver crypto operation structure and to ++ call back to OCF*/ ++static void ++icp_ocfDrvSymCallBack(void *callbackTag, ++ CpaStatus status, ++ const CpaCySymOp operationType, ++ void *pOpData, ++ CpaBufferList * pDstBuffer, CpaBoolean verifyResult); ++ ++/*This function is used to extract crypto processing information from the OCF ++ inputs, so as that it may be passed onto LAC*/ ++static int ++icp_ocfDrvProcessDataSetup(struct icp_drvOpData *drvOpData, ++ struct cryptodesc *crp_desc); ++ ++/*This function checks whether the crp_desc argument pertains to a digest or a ++ cipher operation*/ ++static int icp_ocfDrvAlgCheck(struct cryptodesc *crp_desc); ++ ++/*This function copies all the passed in session context information and stores ++ it in a LAC context structure*/ ++static int ++icp_ocfDrvAlgorithmSetup(struct cryptoini *cri, ++ CpaCySymSessionSetupData * lacSessCtx); ++ ++/*This function is used to free an OCF->OCF_DRV session object*/ ++static void icp_ocfDrvFreeOCFSession(struct icp_drvSessionData *sessionData); ++ ++/*max IOV buffs supported in a UIO structure*/ ++#define NUM_IOV_SUPPORTED (1) ++ ++/* Name : icp_ocfDrvSymCallBack ++ * ++ * Description : When this function returns it signifies that the LAC ++ * component has completed the relevant symmetric operation. ++ * ++ * Notes : The callbackTag is a pointer to an icp_drvOpData. This memory ++ * object was passed to LAC for the cryptographic processing and contains all ++ * the relevant information for cleaning up buffer handles etc. so that the ++ * OCF EP80579 Driver portion of this crypto operation can be fully completed. ++ */ ++static void ++icp_ocfDrvSymCallBack(void *callbackTag, ++ CpaStatus status, ++ const CpaCySymOp operationType, ++ void *pOpData, ++ CpaBufferList * pDstBuffer, CpaBoolean verifyResult) ++{ ++ struct cryptop *crp = NULL; ++ struct icp_drvOpData *temp_drvOpData = ++ (struct icp_drvOpData *)callbackTag; ++ uint64_t *tempBasePtr = NULL; ++ uint32_t tempLen = 0; ++ ++ if (NULL == temp_drvOpData) { ++ DPRINTK("%s(): The callback from the LAC component" ++ " has failed due to Null userOpaque data" ++ "(status == %d).\n", __FUNCTION__, status); ++ DPRINTK("%s(): Unable to call OCF back! \n", __FUNCTION__); ++ return; ++ } ++ ++ crp = temp_drvOpData->crp; ++ crp->crp_etype = ICP_OCF_DRV_NO_CRYPTO_PROCESS_ERROR; ++ ++ if (NULL == pOpData) { ++ DPRINTK("%s(): The callback from the LAC component" ++ " has failed due to Null Symmetric Op data" ++ "(status == %d).\n", __FUNCTION__, status); ++ crp->crp_etype = ECANCELED; ++ crypto_done(crp); ++ return; ++ } ++ ++ if (NULL == pDstBuffer) { ++ DPRINTK("%s(): The callback from the LAC component" ++ " has failed due to Null Dst Bufferlist data" ++ "(status == %d).\n", __FUNCTION__, status); ++ crp->crp_etype = ECANCELED; ++ crypto_done(crp); ++ return; ++ } ++ ++ if (CPA_STATUS_SUCCESS == status) { ++ ++ if (temp_drvOpData->bufferType == ICP_CRYPTO_F_PACKET_BUF) { ++ if (ICP_OCF_DRV_STATUS_SUCCESS != ++ icp_ocfDrvBufferListToPacketBuff(pDstBuffer, ++ (icp_packet_buffer_t ++ **) ++ & (crp->crp_buf))) { ++ EPRINTK("%s(): BufferList to SkBuff " ++ "conversion error.\n", __FUNCTION__); ++ crp->crp_etype = EPERM; ++ } ++ } else { ++ icp_ocfDrvBufferListToPtrAndLen(pDstBuffer, ++ (void **)&tempBasePtr, ++ &tempLen); ++ crp->crp_olen = (int)tempLen; ++ } ++ ++ } else { ++ DPRINTK("%s(): The callback from the LAC component has failed" ++ "(status == %d).\n", __FUNCTION__, status); ++ ++ crp->crp_etype = ECANCELED; ++ } ++ ++ if (temp_drvOpData->numBufferListArray > ++ ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) { ++ icp_kfree(pDstBuffer->pBuffers); ++ } ++ icp_ocfDrvFreeMetaData(pDstBuffer); ++ ICP_CACHE_FREE(drvOpData_zone, temp_drvOpData); ++ ++ /* Invoke the OCF callback function */ ++ crypto_done(crp); ++ ++ return; ++} ++ ++/* Name : icp_ocfDrvNewSession ++ * ++ * Description : This function will create a new Driver<->OCF session ++ * ++ * Notes : LAC session registration happens during the first perform call. ++ * That is the first time we know all information about a given session. ++ */ ++int icp_ocfDrvNewSession(icp_device_t dev, uint32_t * sid, ++ struct cryptoini *cri) ++{ ++ struct icp_drvSessionData *sessionData = NULL; ++ uint32_t delete_session = 0; ++ ++ /* The SID passed in should be our driver ID. We can return the */ ++ /* local ID (LID) which is a unique identifier which we can use */ ++ /* to differentiate between the encrypt/decrypt LAC session handles */ ++ if (NULL == sid) { ++ EPRINTK("%s(): Invalid input parameters - NULL sid.\n", ++ __FUNCTION__); ++ return EINVAL; ++ } ++ ++ if (NULL == cri) { ++ EPRINTK("%s(): Invalid input parameters - NULL cryptoini.\n", ++ __FUNCTION__); ++ return EINVAL; ++ } ++ ++ if (icp_ocfDrvDriverId != *sid) { ++ EPRINTK("%s(): Invalid input parameters - bad driver ID\n", ++ __FUNCTION__); ++ EPRINTK("\t sid = 0x08%p \n \t cri = 0x08%p \n", sid, cri); ++ return EINVAL; ++ } ++ ++ sessionData = icp_kmem_cache_zalloc(drvSessionData_zone, ICP_M_NOWAIT); ++ if (NULL == sessionData) { ++ DPRINTK("%s():No memory for Session Data\n", __FUNCTION__); ++ return ENOMEM; ++ } ++ ++ /*ENTER CRITICAL SECTION */ ++ icp_spin_lockbh_lock(&icp_ocfDrvSymSessInfoListSpinlock); ++ /*put this check in the spinlock so no new sessions can be added to the ++ linked list when we are exiting */ ++ if (CPA_TRUE == icp_atomic_read(&icp_ocfDrvIsExiting)) { ++ delete_session++; ++ ++ } else if (NO_OCF_TO_DRV_MAX_SESSIONS != max_sessions) { ++ if (icp_atomic_read(&num_ocf_to_drv_registered_sessions) >= ++ (max_sessions - ++ icp_atomic_read(&lac_session_failed_dereg_count))) { ++ delete_session++; ++ } else { ++ icp_atomic_inc(&num_ocf_to_drv_registered_sessions); ++ /* Add to session data linked list */ ++ ICP_LIST_ADD(sessionData, &icp_ocfDrvGlobalSymListHead, ++ listNode); ++ } ++ ++ } else if (NO_OCF_TO_DRV_MAX_SESSIONS == max_sessions) { ++ ICP_LIST_ADD(sessionData, &icp_ocfDrvGlobalSymListHead, ++ listNode); ++ } ++ ++ sessionData->inUse = ICP_SESSION_INITIALISED; ++ ++ /*EXIT CRITICAL SECTION */ ++ icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock); ++ ++ if (delete_session) { ++ DPRINTK("%s():No Session handles available\n", __FUNCTION__); ++ ICP_CACHE_FREE(drvSessionData_zone, sessionData); ++ return EPERM; ++ } ++ ++ if (ICP_OCF_DRV_STATUS_SUCCESS != ++ icp_ocfDrvAlgorithmSetup(cri, &(sessionData->lacSessCtx))) { ++ DPRINTK("%s():algorithm not supported\n", __FUNCTION__); ++ icp_ocfDrvFreeOCFSession(sessionData); ++ return EINVAL; ++ } ++ ++ if (cri->cri_next) { ++ if (cri->cri_next->cri_next != NULL) { ++ DPRINTK("%s():only two chained algorithms supported\n", ++ __FUNCTION__); ++ icp_ocfDrvFreeOCFSession(sessionData); ++ return EPERM; ++ } ++ ++ if (ICP_OCF_DRV_STATUS_SUCCESS != ++ icp_ocfDrvAlgorithmSetup(cri->cri_next, ++ &(sessionData->lacSessCtx))) { ++ DPRINTK("%s():second algorithm not supported\n", ++ __FUNCTION__); ++ icp_ocfDrvFreeOCFSession(sessionData); ++ return EINVAL; ++ } ++ ++ sessionData->lacSessCtx.symOperation = ++ CPA_CY_SYM_OP_ALGORITHM_CHAINING; ++ } ++ ++ *sid = (uint32_t) sessionData; ++ ++ return ICP_OCF_DRV_STATUS_SUCCESS; ++} ++ ++/* Name : icp_ocfDrvAlgorithmSetup ++ * ++ * Description : This function builds the session context data from the ++ * information supplied through OCF. Algorithm chain order and whether the ++ * session is Encrypt/Decrypt can only be found out at perform time however, so ++ * the session is registered with LAC at that time. ++ */ ++static int ++icp_ocfDrvAlgorithmSetup(struct cryptoini *cri, ++ CpaCySymSessionSetupData * lacSessCtx) ++{ ++ ++ lacSessCtx->sessionPriority = CPA_CY_PRIORITY_NORMAL; ++ ++ switch (cri->cri_alg) { ++ ++ case CRYPTO_NULL_CBC: ++ DPRINTK("%s(): NULL CBC\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; ++ lacSessCtx->cipherSetupData.cipherAlgorithm = ++ CPA_CY_SYM_CIPHER_NULL; ++ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = ++ cri->cri_klen / NUM_BITS_IN_BYTE; ++ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; ++ break; ++ ++ case CRYPTO_DES_CBC: ++ DPRINTK("%s(): DES CBC\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; ++ lacSessCtx->cipherSetupData.cipherAlgorithm = ++ CPA_CY_SYM_CIPHER_DES_CBC; ++ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = ++ cri->cri_klen / NUM_BITS_IN_BYTE; ++ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; ++ break; ++ ++ case CRYPTO_3DES_CBC: ++ DPRINTK("%s(): 3DES CBC\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; ++ lacSessCtx->cipherSetupData.cipherAlgorithm = ++ CPA_CY_SYM_CIPHER_3DES_CBC; ++ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = ++ cri->cri_klen / NUM_BITS_IN_BYTE; ++ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; ++ break; ++ ++ case CRYPTO_AES_CBC: ++ DPRINTK("%s(): AES CBC\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; ++ lacSessCtx->cipherSetupData.cipherAlgorithm = ++ CPA_CY_SYM_CIPHER_AES_CBC; ++ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = ++ cri->cri_klen / NUM_BITS_IN_BYTE; ++ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; ++ break; ++ ++ case CRYPTO_ARC4: ++ DPRINTK("%s(): ARC4\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; ++ lacSessCtx->cipherSetupData.cipherAlgorithm = ++ CPA_CY_SYM_CIPHER_ARC4; ++ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = ++ cri->cri_klen / NUM_BITS_IN_BYTE; ++ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; ++ break; ++ ++ case CRYPTO_SHA1: ++ DPRINTK("%s(): SHA1\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; ++ lacSessCtx->hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_SHA1; ++ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; ++ lacSessCtx->hashSetupData.digestResultLenInBytes = ++ (cri->cri_mlen ? ++ cri->cri_mlen : ICP_SHA1_DIGEST_SIZE_IN_BYTES); ++ ++ break; ++ ++ case CRYPTO_SHA1_HMAC: ++ DPRINTK("%s(): SHA1_HMAC\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; ++ lacSessCtx->hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_SHA1; ++ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; ++ lacSessCtx->hashSetupData.digestResultLenInBytes = ++ (cri->cri_mlen ? ++ cri->cri_mlen : ICP_SHA1_DIGEST_SIZE_IN_BYTES); ++ lacSessCtx->hashSetupData.authModeSetupData.authKey = ++ cri->cri_key; ++ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = ++ cri->cri_klen / NUM_BITS_IN_BYTE; ++ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; ++ ++ break; ++ ++ case CRYPTO_SHA2_256: ++ DPRINTK("%s(): SHA256\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; ++ lacSessCtx->hashSetupData.hashAlgorithm = ++ CPA_CY_SYM_HASH_SHA256; ++ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; ++ lacSessCtx->hashSetupData.digestResultLenInBytes = ++ (cri->cri_mlen ? ++ cri->cri_mlen : ICP_SHA256_DIGEST_SIZE_IN_BYTES); ++ ++ break; ++ ++ case CRYPTO_SHA2_256_HMAC: ++ DPRINTK("%s(): SHA256_HMAC\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; ++ lacSessCtx->hashSetupData.hashAlgorithm = ++ CPA_CY_SYM_HASH_SHA256; ++ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; ++ lacSessCtx->hashSetupData.digestResultLenInBytes = ++ (cri->cri_mlen ? ++ cri->cri_mlen : ICP_SHA256_DIGEST_SIZE_IN_BYTES); ++ lacSessCtx->hashSetupData.authModeSetupData.authKey = ++ cri->cri_key; ++ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = ++ cri->cri_klen / NUM_BITS_IN_BYTE; ++ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; ++ ++ break; ++ ++ case CRYPTO_SHA2_384: ++ DPRINTK("%s(): SHA384\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; ++ lacSessCtx->hashSetupData.hashAlgorithm = ++ CPA_CY_SYM_HASH_SHA384; ++ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; ++ lacSessCtx->hashSetupData.digestResultLenInBytes = ++ (cri->cri_mlen ? ++ cri->cri_mlen : ICP_SHA384_DIGEST_SIZE_IN_BYTES); ++ ++ break; ++ ++ case CRYPTO_SHA2_384_HMAC: ++ DPRINTK("%s(): SHA384_HMAC\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; ++ lacSessCtx->hashSetupData.hashAlgorithm = ++ CPA_CY_SYM_HASH_SHA384; ++ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; ++ lacSessCtx->hashSetupData.digestResultLenInBytes = ++ (cri->cri_mlen ? ++ cri->cri_mlen : ICP_SHA384_DIGEST_SIZE_IN_BYTES); ++ lacSessCtx->hashSetupData.authModeSetupData.authKey = ++ cri->cri_key; ++ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = ++ cri->cri_klen / NUM_BITS_IN_BYTE; ++ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; ++ ++ break; ++ ++ case CRYPTO_SHA2_512: ++ DPRINTK("%s(): SHA512\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; ++ lacSessCtx->hashSetupData.hashAlgorithm = ++ CPA_CY_SYM_HASH_SHA512; ++ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; ++ lacSessCtx->hashSetupData.digestResultLenInBytes = ++ (cri->cri_mlen ? ++ cri->cri_mlen : ICP_SHA512_DIGEST_SIZE_IN_BYTES); ++ ++ break; ++ ++ case CRYPTO_SHA2_512_HMAC: ++ DPRINTK("%s(): SHA512_HMAC\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; ++ lacSessCtx->hashSetupData.hashAlgorithm = ++ CPA_CY_SYM_HASH_SHA512; ++ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; ++ lacSessCtx->hashSetupData.digestResultLenInBytes = ++ (cri->cri_mlen ? ++ cri->cri_mlen : ICP_SHA512_DIGEST_SIZE_IN_BYTES); ++ lacSessCtx->hashSetupData.authModeSetupData.authKey = ++ cri->cri_key; ++ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = ++ cri->cri_klen / NUM_BITS_IN_BYTE; ++ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; ++ ++ break; ++ ++ case CRYPTO_MD5: ++ DPRINTK("%s(): MD5\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; ++ lacSessCtx->hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_MD5; ++ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; ++ lacSessCtx->hashSetupData.digestResultLenInBytes = ++ (cri->cri_mlen ? ++ cri->cri_mlen : ICP_MD5_DIGEST_SIZE_IN_BYTES); ++ ++ break; ++ ++ case CRYPTO_MD5_HMAC: ++ DPRINTK("%s(): MD5_HMAC\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; ++ lacSessCtx->hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_MD5; ++ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; ++ lacSessCtx->hashSetupData.digestResultLenInBytes = ++ (cri->cri_mlen ? ++ cri->cri_mlen : ICP_MD5_DIGEST_SIZE_IN_BYTES); ++ lacSessCtx->hashSetupData.authModeSetupData.authKey = ++ cri->cri_key; ++ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = ++ cri->cri_klen / NUM_BITS_IN_BYTE; ++ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; ++ ++ break; ++ ++ default: ++ DPRINTK("%s(): ALG Setup FAIL\n", __FUNCTION__); ++ return ICP_OCF_DRV_STATUS_FAIL; ++ } ++ ++ return ICP_OCF_DRV_STATUS_SUCCESS; ++} ++ ++/* Name : icp_ocfDrvFreeOCFSession ++ * ++ * Description : This function deletes all existing Session data representing ++ * the Cryptographic session established between OCF and this driver. This ++ * also includes freeing the memory allocated for the session context. The ++ * session object is also removed from the session linked list. ++ */ ++static void icp_ocfDrvFreeOCFSession(struct icp_drvSessionData *sessionData) ++{ ++ ++ sessionData->inUse = ICP_SESSION_DEREGISTERED; ++ ++ /*ENTER CRITICAL SECTION */ ++ icp_spin_lockbh_lock(&icp_ocfDrvSymSessInfoListSpinlock); ++ ++ if (CPA_TRUE == icp_atomic_read(&icp_ocfDrvIsExiting)) { ++ /*If the Driver is exiting, allow that process to ++ handle any deletions */ ++ /*EXIT CRITICAL SECTION */ ++ icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock); ++ return; ++ } ++ ++ icp_atomic_dec(&num_ocf_to_drv_registered_sessions); ++ ++ ICP_LIST_DEL(sessionData, listNode); ++ ++ /*EXIT CRITICAL SECTION */ ++ icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock); ++ ++ if (NULL != sessionData->sessHandle) { ++ icp_kfree(sessionData->sessHandle); ++ } ++ ICP_CACHE_FREE(drvSessionData_zone, sessionData); ++} ++ ++/* Name : icp_ocfDrvFreeLACSession ++ * ++ * Description : This attempts to deregister a LAC session. If it fails, the ++ * deregistation retry function is called. ++ */ ++int icp_ocfDrvFreeLACSession(icp_device_t dev, uint64_t sid) ++{ ++ CpaCySymSessionCtx sessionToDeregister = NULL; ++ struct icp_drvSessionData *sessionData = NULL; ++ CpaStatus lacStatus = CPA_STATUS_SUCCESS; ++ int retval = 0; ++ ++ sessionData = (struct icp_drvSessionData *)CRYPTO_SESID2LID(sid); ++ if (NULL == sessionData) { ++ EPRINTK("%s(): OCF Free session called with Null Session ID.\n", ++ __FUNCTION__); ++ return EINVAL; ++ } ++ ++ sessionToDeregister = sessionData->sessHandle; ++ ++ if ((ICP_SESSION_INITIALISED != sessionData->inUse) && ++ (ICP_SESSION_RUNNING != sessionData->inUse) && ++ (ICP_SESSION_DEREGISTERED != sessionData->inUse)) { ++ DPRINTK("%s() Session not initialised.\n", __FUNCTION__); ++ return EINVAL; ++ } ++ ++ if (ICP_SESSION_RUNNING == sessionData->inUse) { ++ lacStatus = cpaCySymRemoveSession(CPA_INSTANCE_HANDLE_SINGLE, ++ sessionToDeregister); ++ if (CPA_STATUS_RETRY == lacStatus) { ++ if (ICP_OCF_DRV_STATUS_SUCCESS != ++ icp_ocfDrvDeregRetry(&sessionToDeregister)) { ++ /* the retry function increments the ++ dereg failed count */ ++ DPRINTK("%s(): LAC failed to deregister the " ++ "session. (localSessionId= %p)\n", ++ __FUNCTION__, sessionToDeregister); ++ retval = EPERM; ++ } ++ ++ } else if (CPA_STATUS_SUCCESS != lacStatus) { ++ DPRINTK("%s(): LAC failed to deregister the session. " ++ "localSessionId= %p, lacStatus = %d\n", ++ __FUNCTION__, sessionToDeregister, lacStatus); ++ icp_atomic_inc(&lac_session_failed_dereg_count); ++ retval = EPERM; ++ } ++ } else { ++ DPRINTK("%s() Session not registered with LAC.\n", ++ __FUNCTION__); ++ } ++ ++ icp_ocfDrvFreeOCFSession(sessionData); ++ return retval; ++ ++} ++ ++/* Name : icp_ocfDrvAlgCheck ++ * ++ * Description : This function checks whether the cryptodesc argument pertains ++ * to a sym or hash function ++ */ ++static int icp_ocfDrvAlgCheck(struct cryptodesc *crp_desc) ++{ ++ ++ if (crp_desc->crd_alg == CRYPTO_3DES_CBC || ++ crp_desc->crd_alg == CRYPTO_AES_CBC || ++ crp_desc->crd_alg == CRYPTO_DES_CBC || ++ crp_desc->crd_alg == CRYPTO_NULL_CBC || ++ crp_desc->crd_alg == CRYPTO_ARC4) { ++ return ICP_OCF_DRV_ALG_CIPHER; ++ } ++ ++ return ICP_OCF_DRV_ALG_HASH; ++} ++ ++/* Name : icp_ocfDrvSymProcess ++ * ++ * Description : This function will map symmetric functionality calls from OCF ++ * to the LAC API. It will also allocate memory to store the session context. ++ * ++ * Notes: If it is the first perform call for a given session, then a LAC ++ * session is registered. After the session is registered, no checks as ++ * to whether session paramaters have changed (e.g. alg chain order) are ++ * done. ++ */ ++int icp_ocfDrvSymProcess(icp_device_t dev, struct cryptop *crp, int hint) ++{ ++ struct icp_drvSessionData *sessionData = NULL; ++ struct icp_drvOpData *drvOpData = NULL; ++ CpaStatus lacStatus = CPA_STATUS_SUCCESS; ++ Cpa32U sessionCtxSizeInBytes = 0; ++ ++ if (NULL == crp) { ++ DPRINTK("%s(): Invalid input parameters, cryptop is NULL\n", ++ __FUNCTION__); ++ return EINVAL; ++ } ++ ++ if (NULL == crp->crp_desc) { ++ DPRINTK("%s(): Invalid input parameters, no crp_desc attached " ++ "to crp\n", __FUNCTION__); ++ crp->crp_etype = EINVAL; ++ return EINVAL; ++ } ++ ++ if (NULL == crp->crp_buf) { ++ DPRINTK("%s(): Invalid input parameters, no buffer attached " ++ "to crp\n", __FUNCTION__); ++ crp->crp_etype = EINVAL; ++ return EINVAL; ++ } ++ ++ if (CPA_TRUE == icp_atomic_read(&icp_ocfDrvIsExiting)) { ++ crp->crp_etype = EFAULT; ++ return EFAULT; ++ } ++ ++ sessionData = (struct icp_drvSessionData *) ++ (CRYPTO_SESID2LID(crp->crp_sid)); ++ if (NULL == sessionData) { ++ DPRINTK("%s(): Invalid input parameters, Null Session ID \n", ++ __FUNCTION__); ++ crp->crp_etype = EINVAL; ++ return EINVAL; ++ } ++ ++/*If we get a request against a deregisted session, cancel operation*/ ++ if (ICP_SESSION_DEREGISTERED == sessionData->inUse) { ++ DPRINTK("%s(): Session ID %d was deregistered \n", ++ __FUNCTION__, (int)(CRYPTO_SESID2LID(crp->crp_sid))); ++ crp->crp_etype = EFAULT; ++ return EFAULT; ++ } ++ ++/*If none of the session states are set, then the session structure was either ++ not initialised properly or we are reading from a freed memory area (possible ++ due to OCF batch mode not removing queued requests against deregistered ++ sessions*/ ++ if (ICP_SESSION_INITIALISED != sessionData->inUse && ++ ICP_SESSION_RUNNING != sessionData->inUse) { ++ DPRINTK("%s(): Session - ID %d - not properly initialised or " ++ "memory freed back to the kernel \n", ++ __FUNCTION__, (int)(CRYPTO_SESID2LID(crp->crp_sid))); ++ crp->crp_etype = EINVAL; ++ return EINVAL; ++ } ++ ++ /*For the below checks, remember error checking is already done in LAC. ++ We're not validating inputs subsequent to registration */ ++ if (sessionData->inUse == ICP_SESSION_INITIALISED) { ++ DPRINTK("%s(): Initialising session\n", __FUNCTION__); ++ ++ if (NULL != crp->crp_desc->crd_next) { ++ if (ICP_OCF_DRV_ALG_CIPHER == ++ icp_ocfDrvAlgCheck(crp->crp_desc)) { ++ ++ sessionData->lacSessCtx.algChainOrder = ++ CPA_CY_SYM_ALG_CHAIN_ORDER_CIPHER_THEN_HASH; ++ ++ if (crp->crp_desc->crd_flags & CRD_F_ENCRYPT) { ++ sessionData->lacSessCtx.cipherSetupData. ++ cipherDirection = ++ CPA_CY_SYM_CIPHER_DIRECTION_ENCRYPT; ++ } else { ++ sessionData->lacSessCtx.cipherSetupData. ++ cipherDirection = ++ CPA_CY_SYM_CIPHER_DIRECTION_DECRYPT; ++ } ++ } else { ++ sessionData->lacSessCtx.algChainOrder = ++ CPA_CY_SYM_ALG_CHAIN_ORDER_HASH_THEN_CIPHER; ++ ++ if (crp->crp_desc->crd_next->crd_flags & ++ CRD_F_ENCRYPT) { ++ sessionData->lacSessCtx.cipherSetupData. ++ cipherDirection = ++ CPA_CY_SYM_CIPHER_DIRECTION_ENCRYPT; ++ } else { ++ sessionData->lacSessCtx.cipherSetupData. ++ cipherDirection = ++ CPA_CY_SYM_CIPHER_DIRECTION_DECRYPT; ++ } ++ ++ } ++ ++ } else if (ICP_OCF_DRV_ALG_CIPHER == ++ icp_ocfDrvAlgCheck(crp->crp_desc)) { ++ if (crp->crp_desc->crd_flags & CRD_F_ENCRYPT) { ++ sessionData->lacSessCtx.cipherSetupData. ++ cipherDirection = ++ CPA_CY_SYM_CIPHER_DIRECTION_ENCRYPT; ++ } else { ++ sessionData->lacSessCtx.cipherSetupData. ++ cipherDirection = ++ CPA_CY_SYM_CIPHER_DIRECTION_DECRYPT; ++ } ++ ++ } ++ ++ /*No action required for standalone Auth here */ ++ ++ /* Allocate memory for SymSessionCtx before the Session Registration */ ++ lacStatus = ++ cpaCySymSessionCtxGetSize(CPA_INSTANCE_HANDLE_SINGLE, ++ &(sessionData->lacSessCtx), ++ &sessionCtxSizeInBytes); ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): cpaCySymSessionCtxGetSize failed - %d\n", ++ __FUNCTION__, lacStatus); ++ crp->crp_etype = EINVAL; ++ return EINVAL; ++ } ++ sessionData->sessHandle = ++ icp_kmalloc(sessionCtxSizeInBytes, ICP_M_NOWAIT); ++ if (NULL == sessionData->sessHandle) { ++ EPRINTK ++ ("%s(): Failed to get memory for SymSessionCtx\n", ++ __FUNCTION__); ++ crp->crp_etype = ENOMEM; ++ return ENOMEM; ++ } ++ ++ lacStatus = cpaCySymInitSession(CPA_INSTANCE_HANDLE_SINGLE, ++ icp_ocfDrvSymCallBack, ++ &(sessionData->lacSessCtx), ++ sessionData->sessHandle); ++ ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): cpaCySymInitSession failed -%d \n", ++ __FUNCTION__, lacStatus); ++ crp->crp_etype = EFAULT; ++ return EFAULT; ++ } ++ ++ sessionData->inUse = ICP_SESSION_RUNNING; ++ } ++ ++ drvOpData = icp_kmem_cache_zalloc(drvOpData_zone, ICP_M_NOWAIT); ++ if (NULL == drvOpData) { ++ EPRINTK("%s():Failed to get memory for drvOpData\n", ++ __FUNCTION__); ++ crp->crp_etype = ENOMEM; ++ return ENOMEM; ++ } ++ ++ drvOpData->lacOpData.pSessionCtx = sessionData->sessHandle; ++ drvOpData->digestSizeInBytes = sessionData->lacSessCtx.hashSetupData. ++ digestResultLenInBytes; ++ drvOpData->crp = crp; ++ ++ /* Set the default buffer list array memory allocation */ ++ drvOpData->srcBuffer.pBuffers = drvOpData->bufferListArray; ++ drvOpData->numBufferListArray = ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS; ++ ++ if (ICP_OCF_DRV_STATUS_SUCCESS != ++ icp_ocfDrvProcessDataSetup(drvOpData, drvOpData->crp->crp_desc)) { ++ crp->crp_etype = EINVAL; ++ goto err; ++ } ++ ++ if (drvOpData->crp->crp_desc->crd_next != NULL) { ++ if (icp_ocfDrvProcessDataSetup(drvOpData, drvOpData->crp-> ++ crp_desc->crd_next)) { ++ crp->crp_etype = EINVAL; ++ goto err; ++ } ++ ++ } ++ ++ /* ++ * Allocate buffer list array memory if the data fragment is more than ++ * the default number (ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) and not ++ * calculated already ++ */ ++ if (crp->crp_flags & ICP_CRYPTO_F_PACKET_BUF) { ++ if (NULL == drvOpData->lacOpData.pDigestResult) { ++ drvOpData->numBufferListArray = ++ icp_ocfDrvGetPacketBuffFrags((icp_packet_buffer_t *) ++ crp->crp_buf); ++ } ++ ++ if (ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS < ++ drvOpData->numBufferListArray) { ++ DPRINTK("%s() numBufferListArray more than default\n", ++ __FUNCTION__); ++ drvOpData->srcBuffer.pBuffers = NULL; ++ drvOpData->srcBuffer.pBuffers = ++ icp_kmalloc(drvOpData->numBufferListArray * ++ sizeof(CpaFlatBuffer), ICP_M_NOWAIT); ++ if (NULL == drvOpData->srcBuffer.pBuffers) { ++ EPRINTK("%s() Failed to get memory for " ++ "pBuffers\n", __FUNCTION__); ++ ICP_CACHE_FREE(drvOpData_zone, drvOpData); ++ crp->crp_etype = ENOMEM; ++ return ENOMEM; ++ } ++ } ++ } ++ ++ /* ++ * Check the type of buffer structure we got and convert it into ++ * CpaBufferList format. ++ */ ++ if (crp->crp_flags & ICP_CRYPTO_F_PACKET_BUF) { ++ if (ICP_OCF_DRV_STATUS_SUCCESS != ++ icp_ocfDrvPacketBuffToBufferList((icp_packet_buffer_t *) ++ crp->crp_buf, ++ &(drvOpData->srcBuffer))) { ++ EPRINTK("%s():Failed to translate from packet buffer " ++ "to bufferlist\n", __FUNCTION__); ++ crp->crp_etype = EINVAL; ++ goto err; ++ } ++ ++ drvOpData->bufferType = ICP_CRYPTO_F_PACKET_BUF; ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ /* OCF only supports IOV of one entry. */ ++ if (NUM_IOV_SUPPORTED == ++ ((struct uio *)(crp->crp_buf))->uio_iovcnt) { ++ ++ icp_ocfDrvPtrAndLenToBufferList(((struct uio *)(crp-> ++ crp_buf))-> ++ uio_iov[0].iov_base, ++ ((struct uio *)(crp-> ++ crp_buf))-> ++ uio_iov[0].iov_len, ++ &(drvOpData-> ++ srcBuffer)); ++ ++ drvOpData->bufferType = CRYPTO_F_IOV; ++ ++ } else { ++ DPRINTK("%s():Unable to handle IOVs with lengths of " ++ "greater than one!\n", __FUNCTION__); ++ crp->crp_etype = EINVAL; ++ goto err; ++ } ++ ++ } else { ++ icp_ocfDrvPtrAndLenToBufferList(crp->crp_buf, ++ crp->crp_ilen, ++ &(drvOpData->srcBuffer)); ++ ++ drvOpData->bufferType = CRYPTO_BUF_CONTIG; ++ } ++ ++ /* Allocate srcBuffer's private meta data */ ++ if (ICP_OCF_DRV_STATUS_SUCCESS != ++ icp_ocfDrvAllocMetaData(&(drvOpData->srcBuffer), drvOpData)) { ++ EPRINTK("%s() icp_ocfDrvAllocMetaData failed\n", __FUNCTION__); ++ memset(&(drvOpData->lacOpData), 0, sizeof(CpaCySymOpData)); ++ crp->crp_etype = EINVAL; ++ goto err; ++ } ++ ++ /* Perform "in-place" crypto operation */ ++ lacStatus = cpaCySymPerformOp(CPA_INSTANCE_HANDLE_SINGLE, ++ (void *)drvOpData, ++ &(drvOpData->lacOpData), ++ &(drvOpData->srcBuffer), ++ &(drvOpData->srcBuffer), ++ &(drvOpData->verifyResult)); ++ if (CPA_STATUS_RETRY == lacStatus) { ++ DPRINTK("%s(): cpaCySymPerformOp retry, lacStatus = %d\n", ++ __FUNCTION__, lacStatus); ++ memset(&(drvOpData->lacOpData), 0, sizeof(CpaCySymOpData)); ++ crp->crp_etype = ERESTART; ++ goto err; ++ } ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): cpaCySymPerformOp failed, lacStatus = %d\n", ++ __FUNCTION__, lacStatus); ++ memset(&(drvOpData->lacOpData), 0, sizeof(CpaCySymOpData)); ++ crp->crp_etype = EINVAL; ++ goto err; ++ } ++ ++ return 0; //OCF success status value ++ ++ err: ++ if (drvOpData->numBufferListArray > ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) { ++ icp_kfree(drvOpData->srcBuffer.pBuffers); ++ } ++ icp_ocfDrvFreeMetaData(&(drvOpData->srcBuffer)); ++ ICP_CACHE_FREE(drvOpData_zone, drvOpData); ++ ++ return crp->crp_etype; ++} ++ ++/* Name : icp_ocfDrvProcessDataSetup ++ * ++ * Description : This function will setup all the cryptographic operation data ++ * that is required by LAC to execute the operation. ++ */ ++static int icp_ocfDrvProcessDataSetup(struct icp_drvOpData *drvOpData, ++ struct cryptodesc *crp_desc) ++{ ++ CpaCyRandGenOpData randGenOpData; ++ CpaFlatBuffer randData; ++ ++ drvOpData->lacOpData.packetType = CPA_CY_SYM_PACKET_TYPE_FULL; ++ ++ /* Convert from the cryptop to the ICP LAC crypto parameters */ ++ switch (crp_desc->crd_alg) { ++ case CRYPTO_NULL_CBC: ++ drvOpData->lacOpData. ++ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; ++ drvOpData->lacOpData. ++ messageLenToCipherInBytes = crp_desc->crd_len; ++ drvOpData->verifyResult = CPA_FALSE; ++ drvOpData->lacOpData.ivLenInBytes = NULL_BLOCK_LEN; ++ break; ++ case CRYPTO_DES_CBC: ++ drvOpData->lacOpData. ++ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; ++ drvOpData->lacOpData. ++ messageLenToCipherInBytes = crp_desc->crd_len; ++ drvOpData->verifyResult = CPA_FALSE; ++ drvOpData->lacOpData.ivLenInBytes = DES_BLOCK_LEN; ++ break; ++ case CRYPTO_3DES_CBC: ++ drvOpData->lacOpData. ++ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; ++ drvOpData->lacOpData. ++ messageLenToCipherInBytes = crp_desc->crd_len; ++ drvOpData->verifyResult = CPA_FALSE; ++ drvOpData->lacOpData.ivLenInBytes = DES3_BLOCK_LEN; ++ break; ++ case CRYPTO_ARC4: ++ drvOpData->lacOpData. ++ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; ++ drvOpData->lacOpData. ++ messageLenToCipherInBytes = crp_desc->crd_len; ++ drvOpData->verifyResult = CPA_FALSE; ++ drvOpData->lacOpData.ivLenInBytes = ARC4_COUNTER_LEN; ++ break; ++ case CRYPTO_AES_CBC: ++ drvOpData->lacOpData. ++ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; ++ drvOpData->lacOpData. ++ messageLenToCipherInBytes = crp_desc->crd_len; ++ drvOpData->verifyResult = CPA_FALSE; ++ drvOpData->lacOpData.ivLenInBytes = RIJNDAEL128_BLOCK_LEN; ++ break; ++ case CRYPTO_SHA1: ++ case CRYPTO_SHA1_HMAC: ++ case CRYPTO_SHA2_256: ++ case CRYPTO_SHA2_256_HMAC: ++ case CRYPTO_SHA2_384: ++ case CRYPTO_SHA2_384_HMAC: ++ case CRYPTO_SHA2_512: ++ case CRYPTO_SHA2_512_HMAC: ++ case CRYPTO_MD5: ++ case CRYPTO_MD5_HMAC: ++ drvOpData->lacOpData. ++ hashStartSrcOffsetInBytes = crp_desc->crd_skip; ++ drvOpData->lacOpData. ++ messageLenToHashInBytes = crp_desc->crd_len; ++ drvOpData->lacOpData. ++ pDigestResult = ++ icp_ocfDrvDigestPointerFind(drvOpData, crp_desc); ++ ++ if (NULL == drvOpData->lacOpData.pDigestResult) { ++ DPRINTK("%s(): ERROR - could not calculate " ++ "Digest Result memory address\n", __FUNCTION__); ++ return ICP_OCF_DRV_STATUS_FAIL; ++ } ++ ++ drvOpData->lacOpData.digestVerify = CPA_FALSE; ++ break; ++ default: ++ DPRINTK("%s(): Crypto process error - algorithm not " ++ "found \n", __FUNCTION__); ++ return ICP_OCF_DRV_STATUS_FAIL; ++ } ++ ++ /* Figure out what the IV is supposed to be */ ++ if ((crp_desc->crd_alg == CRYPTO_DES_CBC) || ++ (crp_desc->crd_alg == CRYPTO_3DES_CBC) || ++ (crp_desc->crd_alg == CRYPTO_AES_CBC)) { ++ /*ARC4 doesn't use an IV */ ++ if (crp_desc->crd_flags & CRD_F_IV_EXPLICIT) { ++ /* Explicit IV provided to OCF */ ++ drvOpData->lacOpData.pIv = crp_desc->crd_iv; ++ } else { ++ /* IV is not explicitly provided to OCF */ ++ ++ /* Point the LAC OP Data IV pointer to our allocated ++ storage location for this session. */ ++ drvOpData->lacOpData.pIv = drvOpData->ivData; ++ ++ if ((crp_desc->crd_flags & CRD_F_ENCRYPT) && ++ ((crp_desc->crd_flags & CRD_F_IV_PRESENT) == 0)) { ++ ++ /* Encrypting - need to create IV */ ++ randGenOpData.generateBits = CPA_TRUE; ++ randGenOpData.lenInBytes = MAX_IV_LEN_IN_BYTES; ++ ++ icp_ocfDrvPtrAndLenToFlatBuffer((Cpa8U *) ++ drvOpData-> ++ ivData, ++ MAX_IV_LEN_IN_BYTES, ++ &randData); ++ ++ if (CPA_STATUS_SUCCESS != ++ cpaCyRandGen(CPA_INSTANCE_HANDLE_SINGLE, ++ NULL, NULL, ++ &randGenOpData, &randData)) { ++ DPRINTK("%s(): ERROR - Failed to" ++ " generate" ++ " Initialisation Vector\n", ++ __FUNCTION__); ++ return ICP_OCF_DRV_STATUS_FAIL; ++ } ++ ++ crypto_copyback(drvOpData->crp-> ++ crp_flags, ++ drvOpData->crp->crp_buf, ++ crp_desc->crd_inject, ++ drvOpData->lacOpData. ++ ivLenInBytes, ++ (caddr_t) (drvOpData->lacOpData. ++ pIv)); ++ } else { ++ /* Reading IV from buffer */ ++ crypto_copydata(drvOpData->crp-> ++ crp_flags, ++ drvOpData->crp->crp_buf, ++ crp_desc->crd_inject, ++ drvOpData->lacOpData. ++ ivLenInBytes, ++ (caddr_t) (drvOpData->lacOpData. ++ pIv)); ++ } ++ ++ } ++ ++ } ++ ++ return ICP_OCF_DRV_STATUS_SUCCESS; ++} ++ ++/* Name : icp_ocfDrvDigestPointerFind ++ * ++ * Description : This function is used to find the memory address of where the ++ * digest information shall be stored in. Input buffer types are an skbuff, iov ++ * or flat buffer. The address is found using the buffer data start address and ++ * an offset. ++ * ++ * Note: In the case of a linux skbuff, the digest address may exist within ++ * a memory space linked to from the start buffer. These linked memory spaces ++ * must be traversed by the data length offset in order to find the digest start ++ * address. Whether there is enough space for the digest must also be checked. ++ */ ++uint8_t *icp_ocfDrvDigestPointerFind(struct icp_drvOpData * drvOpData, ++ struct cryptodesc * crp_desc) ++{ ++ ++ int offsetInBytes = crp_desc->crd_inject; ++ uint32_t digestSizeInBytes = drvOpData->digestSizeInBytes; ++ uint8_t *flat_buffer_base = NULL; ++ int flat_buffer_length = 0; ++ ++ if (drvOpData->crp->crp_flags & ICP_CRYPTO_F_PACKET_BUF) { ++ ++ return icp_ocfDrvPacketBufferDigestPointerFind(drvOpData, ++ offsetInBytes, ++ digestSizeInBytes); ++ ++ } else { ++ /* IOV or flat buffer */ ++ if (drvOpData->crp->crp_flags & CRYPTO_F_IOV) { ++ /*single IOV check has already been done */ ++ flat_buffer_base = ((struct uio *) ++ (drvOpData->crp->crp_buf))-> ++ uio_iov[0].iov_base; ++ flat_buffer_length = ((struct uio *) ++ (drvOpData->crp->crp_buf))-> ++ uio_iov[0].iov_len; ++ } else { ++ flat_buffer_base = (uint8_t *) drvOpData->crp->crp_buf; ++ flat_buffer_length = drvOpData->crp->crp_ilen; ++ } ++ ++ if (flat_buffer_length < (offsetInBytes + digestSizeInBytes)) { ++ DPRINTK("%s() Not enough space for Digest " ++ "(IOV/Flat Buffer) \n", __FUNCTION__); ++ return NULL; ++ } else { ++ return (uint8_t *) (flat_buffer_base + offsetInBytes); ++ } ++ } ++ DPRINTK("%s() Should not reach this point\n", __FUNCTION__); ++ return NULL; ++} +diff -Nur linux-3.0.4.orig/crypto/ocf/ep80579/linux_2.6_kernel_space.mk linux-3.0.4/crypto/ocf/ep80579/linux_2.6_kernel_space.mk +--- linux-3.0.4.orig/crypto/ocf/ep80579/linux_2.6_kernel_space.mk 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/ep80579/linux_2.6_kernel_space.mk 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,69 @@ ++################### ++# @par ++# This file is provided under a dual BSD/GPLv2 license. When using or ++# redistributing this file, you may do so under either license. ++# ++# GPL LICENSE SUMMARY ++# ++# Copyright(c) 2007,2008 Intel Corporation. All rights reserved. ++# ++# This program is free software; you can redistribute it and/or modify ++# it under the terms of version 2 of the GNU General Public License as ++# published by the Free Software Foundation. ++# ++# This program is distributed in the hope that it will be useful, but ++# WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++# General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++# The full GNU General Public License is included in this distribution ++# in the file called LICENSE.GPL. ++# ++# Contact Information: ++# Intel Corporation ++# ++# BSD LICENSE ++# ++# Copyright(c) 2007,2008 Intel Corporation. All rights reserved. ++# All rights reserved. ++# ++# Redistribution and use in source and binary forms, with or without ++# modification, are permitted provided that the following conditions ++# are met: ++# ++# * Redistributions of source code must retain the above copyright ++# notice, this list of conditions and the following disclaimer. ++# * Redistributions in binary form must reproduce the above copyright ++# notice, this list of conditions and the following disclaimer in ++# the documentation and/or other materials provided with the ++# distribution. ++# * Neither the name of Intel Corporation nor the names of its ++# contributors may be used to endorse or promote products derived ++# from this software without specific prior written permission. ++# ++# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++# ++# ++# version: Security.L.1.0.130 ++################### ++ ++#specific include directories in kernel space ++INCLUDES+=#e.g. -I$(OSAL_DIR)/include \ ++ ++#Extra Flags Specific in kernel space e.g. include path or debug flags etc. e.g to add an include path EXTRA_CFLAGS += -I$(src)/../include ++EXTRA_CFLAGS += $(INCLUDES) -O2 -Wall ++EXTRA_LDFLAGS +=-whole-archive ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/hifn/Makefile linux-3.0.4/crypto/ocf/hifn/Makefile +--- linux-3.0.4.orig/crypto/ocf/hifn/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/hifn/Makefile 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,13 @@ ++# for SGlinux builds ++-include $(ROOTDIR)/modules/.config ++ ++obj-$(CONFIG_OCF_HIFN) += hifn7751.o ++obj-$(CONFIG_OCF_HIFNHIPP) += hifnHIPP.o ++ ++obj ?= . ++EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ ++ ++ifdef TOPDIR ++-include $(TOPDIR)/Rules.make ++endif ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/hifn/hifn7751.c linux-3.0.4/crypto/ocf/hifn/hifn7751.c +--- linux-3.0.4.orig/crypto/ocf/hifn/hifn7751.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/hifn/hifn7751.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,2954 @@ ++/* $OpenBSD: hifn7751.c,v 1.120 2002/05/17 00:33:34 deraadt Exp $ */ ++ ++/*- ++ * Invertex AEON / Hifn 7751 driver ++ * Copyright (c) 1999 Invertex Inc. All rights reserved. ++ * Copyright (c) 1999 Theo de Raadt ++ * Copyright (c) 2000-2001 Network Security Technologies, Inc. ++ * http://www.netsec.net ++ * Copyright (c) 2003 Hifn Inc. ++ * ++ * This driver is based on a previous driver by Invertex, for which they ++ * requested: Please send any comments, feedback, bug-fixes, or feature ++ * requests to software@invertex.com. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored in part by the Defense Advanced Research Projects ++ * Agency (DARPA) and Air Force Research Laboratory, Air Force ++ * Materiel Command, USAF, under agreement number F30602-01-2-0537. ++ * ++ * ++__FBSDID("$FreeBSD: src/sys/dev/hifn/hifn7751.c,v 1.40 2007/03/21 03:42:49 sam Exp $"); ++ */ ++ ++/* ++ * Driver for various Hifn encryption processors. ++ */ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#if 1 ++#define DPRINTF(a...) if (hifn_debug) { \ ++ printk("%s: ", sc ? \ ++ device_get_nameunit(sc->sc_dev) : "hifn"); \ ++ printk(a); \ ++ } else ++#else ++#define DPRINTF(a...) ++#endif ++ ++static inline int ++pci_get_revid(struct pci_dev *dev) ++{ ++ u8 rid = 0; ++ pci_read_config_byte(dev, PCI_REVISION_ID, &rid); ++ return rid; ++} ++ ++static struct hifn_stats hifnstats; ++ ++#define debug hifn_debug ++int hifn_debug = 0; ++module_param(hifn_debug, int, 0644); ++MODULE_PARM_DESC(hifn_debug, "Enable debug"); ++ ++int hifn_maxbatch = 1; ++module_param(hifn_maxbatch, int, 0644); ++MODULE_PARM_DESC(hifn_maxbatch, "max ops to batch w/o interrupt"); ++ ++int hifn_cache_linesize = 0x10; ++module_param(hifn_cache_linesize, int, 0444); ++MODULE_PARM_DESC(hifn_cache_linesize, "PCI config cache line size"); ++ ++#ifdef MODULE_PARM ++char *hifn_pllconfig = NULL; ++MODULE_PARM(hifn_pllconfig, "s"); ++#else ++char hifn_pllconfig[32]; /* This setting is RO after loading */ ++module_param_string(hifn_pllconfig, hifn_pllconfig, 32, 0444); ++#endif ++MODULE_PARM_DESC(hifn_pllconfig, "PLL config, ie., pci66, ext33, ..."); ++ ++#ifdef HIFN_VULCANDEV ++#include ++#include ++ ++static struct cdevsw vulcanpk_cdevsw; /* forward declaration */ ++#endif ++ ++/* ++ * Prototypes and count for the pci_device structure ++ */ ++static int hifn_probe(struct pci_dev *dev, const struct pci_device_id *ent); ++static void hifn_remove(struct pci_dev *dev); ++ ++static int hifn_newsession(device_t, u_int32_t *, struct cryptoini *); ++static int hifn_freesession(device_t, u_int64_t); ++static int hifn_process(device_t, struct cryptop *, int); ++ ++static device_method_t hifn_methods = { ++ /* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, hifn_newsession), ++ DEVMETHOD(cryptodev_freesession,hifn_freesession), ++ DEVMETHOD(cryptodev_process, hifn_process), ++}; ++ ++static void hifn_reset_board(struct hifn_softc *, int); ++static void hifn_reset_puc(struct hifn_softc *); ++static void hifn_puc_wait(struct hifn_softc *); ++static int hifn_enable_crypto(struct hifn_softc *); ++static void hifn_set_retry(struct hifn_softc *sc); ++static void hifn_init_dma(struct hifn_softc *); ++static void hifn_init_pci_registers(struct hifn_softc *); ++static int hifn_sramsize(struct hifn_softc *); ++static int hifn_dramsize(struct hifn_softc *); ++static int hifn_ramtype(struct hifn_softc *); ++static void hifn_sessions(struct hifn_softc *); ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) ++static irqreturn_t hifn_intr(int irq, void *arg); ++#else ++static irqreturn_t hifn_intr(int irq, void *arg, struct pt_regs *regs); ++#endif ++static u_int hifn_write_command(struct hifn_command *, u_int8_t *); ++static u_int32_t hifn_next_signature(u_int32_t a, u_int cnt); ++static void hifn_callback(struct hifn_softc *, struct hifn_command *, u_int8_t *); ++static int hifn_crypto(struct hifn_softc *, struct hifn_command *, struct cryptop *, int); ++static int hifn_readramaddr(struct hifn_softc *, int, u_int8_t *); ++static int hifn_writeramaddr(struct hifn_softc *, int, u_int8_t *); ++static int hifn_dmamap_load_src(struct hifn_softc *, struct hifn_command *); ++static int hifn_dmamap_load_dst(struct hifn_softc *, struct hifn_command *); ++static int hifn_init_pubrng(struct hifn_softc *); ++static void hifn_tick(unsigned long arg); ++static void hifn_abort(struct hifn_softc *); ++static void hifn_alloc_slot(struct hifn_softc *, int *, int *, int *, int *); ++ ++static void hifn_write_reg_0(struct hifn_softc *, bus_size_t, u_int32_t); ++static void hifn_write_reg_1(struct hifn_softc *, bus_size_t, u_int32_t); ++ ++#ifdef CONFIG_OCF_RANDOMHARVEST ++static int hifn_read_random(void *arg, u_int32_t *buf, int len); ++#endif ++ ++#define HIFN_MAX_CHIPS 8 ++static struct hifn_softc *hifn_chip_idx[HIFN_MAX_CHIPS]; ++ ++static __inline u_int32_t ++READ_REG_0(struct hifn_softc *sc, bus_size_t reg) ++{ ++ u_int32_t v = readl(sc->sc_bar0 + reg); ++ sc->sc_bar0_lastreg = (bus_size_t) -1; ++ return (v); ++} ++#define WRITE_REG_0(sc, reg, val) hifn_write_reg_0(sc, reg, val) ++ ++static __inline u_int32_t ++READ_REG_1(struct hifn_softc *sc, bus_size_t reg) ++{ ++ u_int32_t v = readl(sc->sc_bar1 + reg); ++ sc->sc_bar1_lastreg = (bus_size_t) -1; ++ return (v); ++} ++#define WRITE_REG_1(sc, reg, val) hifn_write_reg_1(sc, reg, val) ++ ++/* ++ * map in a given buffer (great on some arches :-) ++ */ ++ ++static int ++pci_map_uio(struct hifn_softc *sc, struct hifn_operand *buf, struct uio *uio) ++{ ++ struct iovec *iov = uio->uio_iov; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ buf->mapsize = 0; ++ for (buf->nsegs = 0; buf->nsegs < uio->uio_iovcnt; ) { ++ buf->segs[buf->nsegs].ds_addr = pci_map_single(sc->sc_pcidev, ++ iov->iov_base, iov->iov_len, ++ PCI_DMA_BIDIRECTIONAL); ++ buf->segs[buf->nsegs].ds_len = iov->iov_len; ++ buf->mapsize += iov->iov_len; ++ iov++; ++ buf->nsegs++; ++ } ++ /* identify this buffer by the first segment */ ++ buf->map = (void *) buf->segs[0].ds_addr; ++ return(0); ++} ++ ++/* ++ * map in a given sk_buff ++ */ ++ ++static int ++pci_map_skb(struct hifn_softc *sc,struct hifn_operand *buf,struct sk_buff *skb) ++{ ++ int i; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ buf->mapsize = 0; ++ ++ buf->segs[0].ds_addr = pci_map_single(sc->sc_pcidev, ++ skb->data, skb_headlen(skb), PCI_DMA_BIDIRECTIONAL); ++ buf->segs[0].ds_len = skb_headlen(skb); ++ buf->mapsize += buf->segs[0].ds_len; ++ ++ buf->nsegs = 1; ++ ++ for (i = 0; i < skb_shinfo(skb)->nr_frags; ) { ++ buf->segs[buf->nsegs].ds_len = skb_shinfo(skb)->frags[i].size; ++ buf->segs[buf->nsegs].ds_addr = pci_map_single(sc->sc_pcidev, ++ page_address(skb_shinfo(skb)->frags[i].page) + ++ skb_shinfo(skb)->frags[i].page_offset, ++ buf->segs[buf->nsegs].ds_len, PCI_DMA_BIDIRECTIONAL); ++ buf->mapsize += buf->segs[buf->nsegs].ds_len; ++ buf->nsegs++; ++ } ++ ++ /* identify this buffer by the first segment */ ++ buf->map = (void *) buf->segs[0].ds_addr; ++ return(0); ++} ++ ++/* ++ * map in a given contiguous buffer ++ */ ++ ++static int ++pci_map_buf(struct hifn_softc *sc,struct hifn_operand *buf, void *b, int len) ++{ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ buf->mapsize = 0; ++ buf->segs[0].ds_addr = pci_map_single(sc->sc_pcidev, ++ b, len, PCI_DMA_BIDIRECTIONAL); ++ buf->segs[0].ds_len = len; ++ buf->mapsize += buf->segs[0].ds_len; ++ buf->nsegs = 1; ++ ++ /* identify this buffer by the first segment */ ++ buf->map = (void *) buf->segs[0].ds_addr; ++ return(0); ++} ++ ++#if 0 /* not needed at this time */ ++static void ++pci_sync_iov(struct hifn_softc *sc, struct hifn_operand *buf) ++{ ++ int i; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ for (i = 0; i < buf->nsegs; i++) ++ pci_dma_sync_single_for_cpu(sc->sc_pcidev, buf->segs[i].ds_addr, ++ buf->segs[i].ds_len, PCI_DMA_BIDIRECTIONAL); ++} ++#endif ++ ++static void ++pci_unmap_buf(struct hifn_softc *sc, struct hifn_operand *buf) ++{ ++ int i; ++ DPRINTF("%s()\n", __FUNCTION__); ++ for (i = 0; i < buf->nsegs; i++) { ++ pci_unmap_single(sc->sc_pcidev, buf->segs[i].ds_addr, ++ buf->segs[i].ds_len, PCI_DMA_BIDIRECTIONAL); ++ buf->segs[i].ds_addr = 0; ++ buf->segs[i].ds_len = 0; ++ } ++ buf->nsegs = 0; ++ buf->mapsize = 0; ++ buf->map = 0; ++} ++ ++static const char* ++hifn_partname(struct hifn_softc *sc) ++{ ++ /* XXX sprintf numbers when not decoded */ ++ switch (pci_get_vendor(sc->sc_pcidev)) { ++ case PCI_VENDOR_HIFN: ++ switch (pci_get_device(sc->sc_pcidev)) { ++ case PCI_PRODUCT_HIFN_6500: return "Hifn 6500"; ++ case PCI_PRODUCT_HIFN_7751: return "Hifn 7751"; ++ case PCI_PRODUCT_HIFN_7811: return "Hifn 7811"; ++ case PCI_PRODUCT_HIFN_7951: return "Hifn 7951"; ++ case PCI_PRODUCT_HIFN_7955: return "Hifn 7955"; ++ case PCI_PRODUCT_HIFN_7956: return "Hifn 7956"; ++ } ++ return "Hifn unknown-part"; ++ case PCI_VENDOR_INVERTEX: ++ switch (pci_get_device(sc->sc_pcidev)) { ++ case PCI_PRODUCT_INVERTEX_AEON: return "Invertex AEON"; ++ } ++ return "Invertex unknown-part"; ++ case PCI_VENDOR_NETSEC: ++ switch (pci_get_device(sc->sc_pcidev)) { ++ case PCI_PRODUCT_NETSEC_7751: return "NetSec 7751"; ++ } ++ return "NetSec unknown-part"; ++ } ++ return "Unknown-vendor unknown-part"; ++} ++ ++static u_int ++checkmaxmin(struct pci_dev *dev, const char *what, u_int v, u_int min, u_int max) ++{ ++ struct hifn_softc *sc = pci_get_drvdata(dev); ++ if (v > max) { ++ device_printf(sc->sc_dev, "Warning, %s %u out of range, " ++ "using max %u\n", what, v, max); ++ v = max; ++ } else if (v < min) { ++ device_printf(sc->sc_dev, "Warning, %s %u out of range, " ++ "using min %u\n", what, v, min); ++ v = min; ++ } ++ return v; ++} ++ ++/* ++ * Select PLL configuration for 795x parts. This is complicated in ++ * that we cannot determine the optimal parameters without user input. ++ * The reference clock is derived from an external clock through a ++ * multiplier. The external clock is either the host bus (i.e. PCI) ++ * or an external clock generator. When using the PCI bus we assume ++ * the clock is either 33 or 66 MHz; for an external source we cannot ++ * tell the speed. ++ * ++ * PLL configuration is done with a string: "pci" for PCI bus, or "ext" ++ * for an external source, followed by the frequency. We calculate ++ * the appropriate multiplier and PLL register contents accordingly. ++ * When no configuration is given we default to "pci66" since that ++ * always will allow the card to work. If a card is using the PCI ++ * bus clock and in a 33MHz slot then it will be operating at half ++ * speed until the correct information is provided. ++ * ++ * We use a default setting of "ext66" because according to Mike Ham ++ * of HiFn, almost every board in existence has an external crystal ++ * populated at 66Mhz. Using PCI can be a problem on modern motherboards, ++ * because PCI33 can have clocks from 0 to 33Mhz, and some have ++ * non-PCI-compliant spread-spectrum clocks, which can confuse the pll. ++ */ ++static void ++hifn_getpllconfig(struct pci_dev *dev, u_int *pll) ++{ ++ const char *pllspec = hifn_pllconfig; ++ u_int freq, mul, fl, fh; ++ u_int32_t pllconfig; ++ char *nxt; ++ ++ if (pllspec == NULL) ++ pllspec = "ext66"; ++ fl = 33, fh = 66; ++ pllconfig = 0; ++ if (strncmp(pllspec, "ext", 3) == 0) { ++ pllspec += 3; ++ pllconfig |= HIFN_PLL_REF_SEL; ++ switch (pci_get_device(dev)) { ++ case PCI_PRODUCT_HIFN_7955: ++ case PCI_PRODUCT_HIFN_7956: ++ fl = 20, fh = 100; ++ break; ++#ifdef notyet ++ case PCI_PRODUCT_HIFN_7954: ++ fl = 20, fh = 66; ++ break; ++#endif ++ } ++ } else if (strncmp(pllspec, "pci", 3) == 0) ++ pllspec += 3; ++ freq = strtoul(pllspec, &nxt, 10); ++ if (nxt == pllspec) ++ freq = 66; ++ else ++ freq = checkmaxmin(dev, "frequency", freq, fl, fh); ++ /* ++ * Calculate multiplier. We target a Fck of 266 MHz, ++ * allowing only even values, possibly rounded down. ++ * Multipliers > 8 must set the charge pump current. ++ */ ++ mul = checkmaxmin(dev, "PLL divisor", (266 / freq) &~ 1, 2, 12); ++ pllconfig |= (mul / 2 - 1) << HIFN_PLL_ND_SHIFT; ++ if (mul > 8) ++ pllconfig |= HIFN_PLL_IS; ++ *pll = pllconfig; ++} ++ ++/* ++ * Attach an interface that successfully probed. ++ */ ++static int ++hifn_probe(struct pci_dev *dev, const struct pci_device_id *ent) ++{ ++ struct hifn_softc *sc = NULL; ++ char rbase; ++ u_int16_t ena, rev; ++ int rseg, rc; ++ unsigned long mem_start, mem_len; ++ static int num_chips = 0; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ if (pci_enable_device(dev) < 0) ++ return(-ENODEV); ++ ++ if (pci_set_mwi(dev)) ++ return(-ENODEV); ++ ++ if (!dev->irq) { ++ printk("hifn: found device with no IRQ assigned. check BIOS settings!"); ++ pci_disable_device(dev); ++ return(-ENODEV); ++ } ++ ++ sc = (struct hifn_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); ++ if (!sc) ++ return(-ENOMEM); ++ memset(sc, 0, sizeof(*sc)); ++ ++ softc_device_init(sc, "hifn", num_chips, hifn_methods); ++ ++ sc->sc_pcidev = dev; ++ sc->sc_irq = -1; ++ sc->sc_cid = -1; ++ sc->sc_num = num_chips++; ++ if (sc->sc_num < HIFN_MAX_CHIPS) ++ hifn_chip_idx[sc->sc_num] = sc; ++ ++ pci_set_drvdata(sc->sc_pcidev, sc); ++ ++ spin_lock_init(&sc->sc_mtx); ++ ++ /* XXX handle power management */ ++ ++ /* ++ * The 7951 and 795x have a random number generator and ++ * public key support; note this. ++ */ ++ if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && ++ (pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 || ++ pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 || ++ pci_get_device(dev) == PCI_PRODUCT_HIFN_7956)) ++ sc->sc_flags = HIFN_HAS_RNG | HIFN_HAS_PUBLIC; ++ /* ++ * The 7811 has a random number generator and ++ * we also note it's identity 'cuz of some quirks. ++ */ ++ if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && ++ pci_get_device(dev) == PCI_PRODUCT_HIFN_7811) ++ sc->sc_flags |= HIFN_IS_7811 | HIFN_HAS_RNG; ++ ++ /* ++ * The 795x parts support AES. ++ */ ++ if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && ++ (pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 || ++ pci_get_device(dev) == PCI_PRODUCT_HIFN_7956)) { ++ sc->sc_flags |= HIFN_IS_7956 | HIFN_HAS_AES; ++ /* ++ * Select PLL configuration. This depends on the ++ * bus and board design and must be manually configured ++ * if the default setting is unacceptable. ++ */ ++ hifn_getpllconfig(dev, &sc->sc_pllconfig); ++ } ++ ++ /* ++ * Setup PCI resources. Note that we record the bus ++ * tag and handle for each register mapping, this is ++ * used by the READ_REG_0, WRITE_REG_0, READ_REG_1, ++ * and WRITE_REG_1 macros throughout the driver. ++ */ ++ mem_start = pci_resource_start(sc->sc_pcidev, 0); ++ mem_len = pci_resource_len(sc->sc_pcidev, 0); ++ sc->sc_bar0 = (ocf_iomem_t) ioremap(mem_start, mem_len); ++ if (!sc->sc_bar0) { ++ device_printf(sc->sc_dev, "cannot map bar%d register space\n", 0); ++ goto fail; ++ } ++ sc->sc_bar0_lastreg = (bus_size_t) -1; ++ ++ mem_start = pci_resource_start(sc->sc_pcidev, 1); ++ mem_len = pci_resource_len(sc->sc_pcidev, 1); ++ sc->sc_bar1 = (ocf_iomem_t) ioremap(mem_start, mem_len); ++ if (!sc->sc_bar1) { ++ device_printf(sc->sc_dev, "cannot map bar%d register space\n", 1); ++ goto fail; ++ } ++ sc->sc_bar1_lastreg = (bus_size_t) -1; ++ ++ /* fix up the bus size */ ++ if (pci_set_dma_mask(dev, DMA_32BIT_MASK)) { ++ device_printf(sc->sc_dev, "No usable DMA configuration, aborting.\n"); ++ goto fail; ++ } ++ if (pci_set_consistent_dma_mask(dev, DMA_32BIT_MASK)) { ++ device_printf(sc->sc_dev, ++ "No usable consistent DMA configuration, aborting.\n"); ++ goto fail; ++ } ++ ++ hifn_set_retry(sc); ++ ++ /* ++ * Setup the area where the Hifn DMA's descriptors ++ * and associated data structures. ++ */ ++ sc->sc_dma = (struct hifn_dma *) pci_alloc_consistent(dev, ++ sizeof(*sc->sc_dma), ++ &sc->sc_dma_physaddr); ++ if (!sc->sc_dma) { ++ device_printf(sc->sc_dev, "cannot alloc sc_dma\n"); ++ goto fail; ++ } ++ bzero(sc->sc_dma, sizeof(*sc->sc_dma)); ++ ++ /* ++ * Reset the board and do the ``secret handshake'' ++ * to enable the crypto support. Then complete the ++ * initialization procedure by setting up the interrupt ++ * and hooking in to the system crypto support so we'll ++ * get used for system services like the crypto device, ++ * IPsec, RNG device, etc. ++ */ ++ hifn_reset_board(sc, 0); ++ ++ if (hifn_enable_crypto(sc) != 0) { ++ device_printf(sc->sc_dev, "crypto enabling failed\n"); ++ goto fail; ++ } ++ hifn_reset_puc(sc); ++ ++ hifn_init_dma(sc); ++ hifn_init_pci_registers(sc); ++ ++ pci_set_master(sc->sc_pcidev); ++ ++ /* XXX can't dynamically determine ram type for 795x; force dram */ ++ if (sc->sc_flags & HIFN_IS_7956) ++ sc->sc_drammodel = 1; ++ else if (hifn_ramtype(sc)) ++ goto fail; ++ ++ if (sc->sc_drammodel == 0) ++ hifn_sramsize(sc); ++ else ++ hifn_dramsize(sc); ++ ++ /* ++ * Workaround for NetSec 7751 rev A: half ram size because two ++ * of the address lines were left floating ++ */ ++ if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC && ++ pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751 && ++ pci_get_revid(dev) == 0x61) /*XXX???*/ ++ sc->sc_ramsize >>= 1; ++ ++ /* ++ * Arrange the interrupt line. ++ */ ++ rc = request_irq(dev->irq, hifn_intr, IRQF_SHARED, "hifn", sc); ++ if (rc) { ++ device_printf(sc->sc_dev, "could not map interrupt: %d\n", rc); ++ goto fail; ++ } ++ sc->sc_irq = dev->irq; ++ ++ hifn_sessions(sc); ++ ++ /* ++ * NB: Keep only the low 16 bits; this masks the chip id ++ * from the 7951. ++ */ ++ rev = READ_REG_1(sc, HIFN_1_REVID) & 0xffff; ++ ++ rseg = sc->sc_ramsize / 1024; ++ rbase = 'K'; ++ if (sc->sc_ramsize >= (1024 * 1024)) { ++ rbase = 'M'; ++ rseg /= 1024; ++ } ++ device_printf(sc->sc_dev, "%s, rev %u, %d%cB %cram", ++ hifn_partname(sc), rev, ++ rseg, rbase, sc->sc_drammodel ? 'd' : 's'); ++ if (sc->sc_flags & HIFN_IS_7956) ++ printf(", pll=0x%x<%s clk, %ux mult>", ++ sc->sc_pllconfig, ++ sc->sc_pllconfig & HIFN_PLL_REF_SEL ? "ext" : "pci", ++ 2 + 2*((sc->sc_pllconfig & HIFN_PLL_ND) >> 11)); ++ printf("\n"); ++ ++ sc->sc_cid = crypto_get_driverid(softc_get_device(sc),CRYPTOCAP_F_HARDWARE); ++ if (sc->sc_cid < 0) { ++ device_printf(sc->sc_dev, "could not get crypto driver id\n"); ++ goto fail; ++ } ++ ++ WRITE_REG_0(sc, HIFN_0_PUCNFG, ++ READ_REG_0(sc, HIFN_0_PUCNFG) | HIFN_PUCNFG_CHIPID); ++ ena = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; ++ ++ switch (ena) { ++ case HIFN_PUSTAT_ENA_2: ++ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0); ++ if (sc->sc_flags & HIFN_HAS_AES) ++ crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); ++ /*FALLTHROUGH*/ ++ case HIFN_PUSTAT_ENA_1: ++ crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); ++ break; ++ } ++ ++ if (sc->sc_flags & (HIFN_HAS_PUBLIC | HIFN_HAS_RNG)) ++ hifn_init_pubrng(sc); ++ ++ init_timer(&sc->sc_tickto); ++ sc->sc_tickto.function = hifn_tick; ++ sc->sc_tickto.data = (unsigned long) sc->sc_num; ++ mod_timer(&sc->sc_tickto, jiffies + HZ); ++ ++ return (0); ++ ++fail: ++ if (sc->sc_cid >= 0) ++ crypto_unregister_all(sc->sc_cid); ++ if (sc->sc_irq != -1) ++ free_irq(sc->sc_irq, sc); ++ if (sc->sc_dma) { ++ /* Turn off DMA polling */ ++ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | ++ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); ++ ++ pci_free_consistent(sc->sc_pcidev, ++ sizeof(*sc->sc_dma), ++ sc->sc_dma, sc->sc_dma_physaddr); ++ } ++ kfree(sc); ++ return (-ENXIO); ++} ++ ++/* ++ * Detach an interface that successfully probed. ++ */ ++static void ++hifn_remove(struct pci_dev *dev) ++{ ++ struct hifn_softc *sc = pci_get_drvdata(dev); ++ unsigned long l_flags; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ KASSERT(sc != NULL, ("hifn_detach: null software carrier!")); ++ ++ /* disable interrupts */ ++ HIFN_LOCK(sc); ++ WRITE_REG_1(sc, HIFN_1_DMA_IER, 0); ++ HIFN_UNLOCK(sc); ++ ++ /*XXX other resources */ ++ del_timer_sync(&sc->sc_tickto); ++ ++ /* Turn off DMA polling */ ++ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | ++ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); ++ ++ crypto_unregister_all(sc->sc_cid); ++ ++ free_irq(sc->sc_irq, sc); ++ ++ pci_free_consistent(sc->sc_pcidev, sizeof(*sc->sc_dma), ++ sc->sc_dma, sc->sc_dma_physaddr); ++} ++ ++ ++static int ++hifn_init_pubrng(struct hifn_softc *sc) ++{ ++ int i; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ if ((sc->sc_flags & HIFN_IS_7811) == 0) { ++ /* Reset 7951 public key/rng engine */ ++ WRITE_REG_1(sc, HIFN_1_PUB_RESET, ++ READ_REG_1(sc, HIFN_1_PUB_RESET) | HIFN_PUBRST_RESET); ++ ++ for (i = 0; i < 100; i++) { ++ DELAY(1000); ++ if ((READ_REG_1(sc, HIFN_1_PUB_RESET) & ++ HIFN_PUBRST_RESET) == 0) ++ break; ++ } ++ ++ if (i == 100) { ++ device_printf(sc->sc_dev, "public key init failed\n"); ++ return (1); ++ } ++ } ++ ++ /* Enable the rng, if available */ ++#ifdef CONFIG_OCF_RANDOMHARVEST ++ if (sc->sc_flags & HIFN_HAS_RNG) { ++ if (sc->sc_flags & HIFN_IS_7811) { ++ u_int32_t r; ++ r = READ_REG_1(sc, HIFN_1_7811_RNGENA); ++ if (r & HIFN_7811_RNGENA_ENA) { ++ r &= ~HIFN_7811_RNGENA_ENA; ++ WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); ++ } ++ WRITE_REG_1(sc, HIFN_1_7811_RNGCFG, ++ HIFN_7811_RNGCFG_DEFL); ++ r |= HIFN_7811_RNGENA_ENA; ++ WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); ++ } else ++ WRITE_REG_1(sc, HIFN_1_RNG_CONFIG, ++ READ_REG_1(sc, HIFN_1_RNG_CONFIG) | ++ HIFN_RNGCFG_ENA); ++ ++ sc->sc_rngfirst = 1; ++ crypto_rregister(sc->sc_cid, hifn_read_random, sc); ++ } ++#endif ++ ++ /* Enable public key engine, if available */ ++ if (sc->sc_flags & HIFN_HAS_PUBLIC) { ++ WRITE_REG_1(sc, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE); ++ sc->sc_dmaier |= HIFN_DMAIER_PUBDONE; ++ WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); ++#ifdef HIFN_VULCANDEV ++ sc->sc_pkdev = make_dev(&vulcanpk_cdevsw, 0, ++ UID_ROOT, GID_WHEEL, 0666, ++ "vulcanpk"); ++ sc->sc_pkdev->si_drv1 = sc; ++#endif ++ } ++ ++ return (0); ++} ++ ++#ifdef CONFIG_OCF_RANDOMHARVEST ++static int ++hifn_read_random(void *arg, u_int32_t *buf, int len) ++{ ++ struct hifn_softc *sc = (struct hifn_softc *) arg; ++ u_int32_t sts; ++ int i, rc = 0; ++ ++ if (len <= 0) ++ return rc; ++ ++ if (sc->sc_flags & HIFN_IS_7811) { ++ /* ONLY VALID ON 7811!!!! */ ++ for (i = 0; i < 5; i++) { ++ sts = READ_REG_1(sc, HIFN_1_7811_RNGSTS); ++ if (sts & HIFN_7811_RNGSTS_UFL) { ++ device_printf(sc->sc_dev, ++ "RNG underflow: disabling\n"); ++ /* DAVIDM perhaps return -1 */ ++ break; ++ } ++ if ((sts & HIFN_7811_RNGSTS_RDY) == 0) ++ break; ++ ++ /* ++ * There are at least two words in the RNG FIFO ++ * at this point. ++ */ ++ if (rc < len) ++ buf[rc++] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); ++ if (rc < len) ++ buf[rc++] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); ++ } ++ } else ++ buf[rc++] = READ_REG_1(sc, HIFN_1_RNG_DATA); ++ ++ /* NB: discard first data read */ ++ if (sc->sc_rngfirst) { ++ sc->sc_rngfirst = 0; ++ rc = 0; ++ } ++ ++ return(rc); ++} ++#endif /* CONFIG_OCF_RANDOMHARVEST */ ++ ++static void ++hifn_puc_wait(struct hifn_softc *sc) ++{ ++ int i; ++ int reg = HIFN_0_PUCTRL; ++ ++ if (sc->sc_flags & HIFN_IS_7956) { ++ reg = HIFN_0_PUCTRL2; ++ } ++ ++ for (i = 5000; i > 0; i--) { ++ DELAY(1); ++ if (!(READ_REG_0(sc, reg) & HIFN_PUCTRL_RESET)) ++ break; ++ } ++ if (!i) ++ device_printf(sc->sc_dev, "proc unit did not reset(0x%x)\n", ++ READ_REG_0(sc, HIFN_0_PUCTRL)); ++} ++ ++/* ++ * Reset the processing unit. ++ */ ++static void ++hifn_reset_puc(struct hifn_softc *sc) ++{ ++ /* Reset processing unit */ ++ int reg = HIFN_0_PUCTRL; ++ ++ if (sc->sc_flags & HIFN_IS_7956) { ++ reg = HIFN_0_PUCTRL2; ++ } ++ WRITE_REG_0(sc, reg, HIFN_PUCTRL_DMAENA); ++ ++ hifn_puc_wait(sc); ++} ++ ++/* ++ * Set the Retry and TRDY registers; note that we set them to ++ * zero because the 7811 locks up when forced to retry (section ++ * 3.6 of "Specification Update SU-0014-04". Not clear if we ++ * should do this for all Hifn parts, but it doesn't seem to hurt. ++ */ ++static void ++hifn_set_retry(struct hifn_softc *sc) ++{ ++ DPRINTF("%s()\n", __FUNCTION__); ++ /* NB: RETRY only responds to 8-bit reads/writes */ ++ pci_write_config_byte(sc->sc_pcidev, HIFN_RETRY_TIMEOUT, 0); ++ pci_write_config_byte(sc->sc_pcidev, HIFN_TRDY_TIMEOUT, 0); ++ /* piggy back the cache line setting here */ ++ pci_write_config_byte(sc->sc_pcidev, PCI_CACHE_LINE_SIZE, hifn_cache_linesize); ++} ++ ++/* ++ * Resets the board. Values in the regesters are left as is ++ * from the reset (i.e. initial values are assigned elsewhere). ++ */ ++static void ++hifn_reset_board(struct hifn_softc *sc, int full) ++{ ++ u_int32_t reg; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ /* ++ * Set polling in the DMA configuration register to zero. 0x7 avoids ++ * resetting the board and zeros out the other fields. ++ */ ++ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | ++ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); ++ ++ /* ++ * Now that polling has been disabled, we have to wait 1 ms ++ * before resetting the board. ++ */ ++ DELAY(1000); ++ ++ /* Reset the DMA unit */ ++ if (full) { ++ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE); ++ DELAY(1000); ++ } else { ++ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, ++ HIFN_DMACNFG_MODE | HIFN_DMACNFG_MSTRESET); ++ hifn_reset_puc(sc); ++ } ++ ++ KASSERT(sc->sc_dma != NULL, ("hifn_reset_board: null DMA tag!")); ++ bzero(sc->sc_dma, sizeof(*sc->sc_dma)); ++ ++ /* Bring dma unit out of reset */ ++ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | ++ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); ++ ++ hifn_puc_wait(sc); ++ hifn_set_retry(sc); ++ ++ if (sc->sc_flags & HIFN_IS_7811) { ++ for (reg = 0; reg < 1000; reg++) { ++ if (READ_REG_1(sc, HIFN_1_7811_MIPSRST) & ++ HIFN_MIPSRST_CRAMINIT) ++ break; ++ DELAY(1000); ++ } ++ if (reg == 1000) ++ device_printf(sc->sc_dev, ": cram init timeout\n"); ++ } else { ++ /* set up DMA configuration register #2 */ ++ /* turn off all PK and BAR0 swaps */ ++ WRITE_REG_1(sc, HIFN_1_DMA_CNFG2, ++ (3 << HIFN_DMACNFG2_INIT_WRITE_BURST_SHIFT)| ++ (3 << HIFN_DMACNFG2_INIT_READ_BURST_SHIFT)| ++ (2 << HIFN_DMACNFG2_TGT_WRITE_BURST_SHIFT)| ++ (2 << HIFN_DMACNFG2_TGT_READ_BURST_SHIFT)); ++ } ++} ++ ++static u_int32_t ++hifn_next_signature(u_int32_t a, u_int cnt) ++{ ++ int i; ++ u_int32_t v; ++ ++ for (i = 0; i < cnt; i++) { ++ ++ /* get the parity */ ++ v = a & 0x80080125; ++ v ^= v >> 16; ++ v ^= v >> 8; ++ v ^= v >> 4; ++ v ^= v >> 2; ++ v ^= v >> 1; ++ ++ a = (v & 1) ^ (a << 1); ++ } ++ ++ return a; ++} ++ ++ ++/* ++ * Checks to see if crypto is already enabled. If crypto isn't enable, ++ * "hifn_enable_crypto" is called to enable it. The check is important, ++ * as enabling crypto twice will lock the board. ++ */ ++static int ++hifn_enable_crypto(struct hifn_softc *sc) ++{ ++ u_int32_t dmacfg, ramcfg, encl, addr, i; ++ char offtbl[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00 }; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ ramcfg = READ_REG_0(sc, HIFN_0_PUCNFG); ++ dmacfg = READ_REG_1(sc, HIFN_1_DMA_CNFG); ++ ++ /* ++ * The RAM config register's encrypt level bit needs to be set before ++ * every read performed on the encryption level register. ++ */ ++ WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); ++ ++ encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; ++ ++ /* ++ * Make sure we don't re-unlock. Two unlocks kills chip until the ++ * next reboot. ++ */ ++ if (encl == HIFN_PUSTAT_ENA_1 || encl == HIFN_PUSTAT_ENA_2) { ++#ifdef HIFN_DEBUG ++ if (hifn_debug) ++ device_printf(sc->sc_dev, ++ "Strong crypto already enabled!\n"); ++#endif ++ goto report; ++ } ++ ++ if (encl != 0 && encl != HIFN_PUSTAT_ENA_0) { ++#ifdef HIFN_DEBUG ++ if (hifn_debug) ++ device_printf(sc->sc_dev, ++ "Unknown encryption level 0x%x\n", encl); ++#endif ++ return 1; ++ } ++ ++ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_UNLOCK | ++ HIFN_DMACNFG_MSTRESET | HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); ++ DELAY(1000); ++ addr = READ_REG_1(sc, HIFN_UNLOCK_SECRET1); ++ DELAY(1000); ++ WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, 0); ++ DELAY(1000); ++ ++ for (i = 0; i <= 12; i++) { ++ addr = hifn_next_signature(addr, offtbl[i] + 0x101); ++ WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, addr); ++ ++ DELAY(1000); ++ } ++ ++ WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); ++ encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; ++ ++#ifdef HIFN_DEBUG ++ if (hifn_debug) { ++ if (encl != HIFN_PUSTAT_ENA_1 && encl != HIFN_PUSTAT_ENA_2) ++ device_printf(sc->sc_dev, "Engine is permanently " ++ "locked until next system reset!\n"); ++ else ++ device_printf(sc->sc_dev, "Engine enabled " ++ "successfully!\n"); ++ } ++#endif ++ ++report: ++ WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg); ++ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, dmacfg); ++ ++ switch (encl) { ++ case HIFN_PUSTAT_ENA_1: ++ case HIFN_PUSTAT_ENA_2: ++ break; ++ case HIFN_PUSTAT_ENA_0: ++ default: ++ device_printf(sc->sc_dev, "disabled\n"); ++ break; ++ } ++ ++ return 0; ++} ++ ++/* ++ * Give initial values to the registers listed in the "Register Space" ++ * section of the HIFN Software Development reference manual. ++ */ ++static void ++hifn_init_pci_registers(struct hifn_softc *sc) ++{ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ /* write fixed values needed by the Initialization registers */ ++ WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA); ++ WRITE_REG_0(sc, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD); ++ WRITE_REG_0(sc, HIFN_0_PUIER, HIFN_PUIER_DSTOVER); ++ ++ /* write all 4 ring address registers */ ++ WRITE_REG_1(sc, HIFN_1_DMA_CRAR, sc->sc_dma_physaddr + ++ offsetof(struct hifn_dma, cmdr[0])); ++ WRITE_REG_1(sc, HIFN_1_DMA_SRAR, sc->sc_dma_physaddr + ++ offsetof(struct hifn_dma, srcr[0])); ++ WRITE_REG_1(sc, HIFN_1_DMA_DRAR, sc->sc_dma_physaddr + ++ offsetof(struct hifn_dma, dstr[0])); ++ WRITE_REG_1(sc, HIFN_1_DMA_RRAR, sc->sc_dma_physaddr + ++ offsetof(struct hifn_dma, resr[0])); ++ ++ DELAY(2000); ++ ++ /* write status register */ ++ WRITE_REG_1(sc, HIFN_1_DMA_CSR, ++ HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS | ++ HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS | ++ HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST | ++ HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER | ++ HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST | ++ HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER | ++ HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST | ++ HIFN_DMACSR_S_WAIT | ++ HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST | ++ HIFN_DMACSR_C_WAIT | ++ HIFN_DMACSR_ENGINE | ++ ((sc->sc_flags & HIFN_HAS_PUBLIC) ? ++ HIFN_DMACSR_PUBDONE : 0) | ++ ((sc->sc_flags & HIFN_IS_7811) ? ++ HIFN_DMACSR_ILLW | HIFN_DMACSR_ILLR : 0)); ++ ++ sc->sc_d_busy = sc->sc_r_busy = sc->sc_s_busy = sc->sc_c_busy = 0; ++ sc->sc_dmaier |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT | ++ HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER | ++ HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT | ++ ((sc->sc_flags & HIFN_IS_7811) ? ++ HIFN_DMAIER_ILLW | HIFN_DMAIER_ILLR : 0); ++ sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; ++ WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); ++ ++ ++ if (sc->sc_flags & HIFN_IS_7956) { ++ u_int32_t pll; ++ ++ WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING | ++ HIFN_PUCNFG_TCALLPHASES | ++ HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32); ++ ++ /* turn off the clocks and insure bypass is set */ ++ pll = READ_REG_1(sc, HIFN_1_PLL); ++ pll = (pll &~ (HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL)) ++ | HIFN_PLL_BP | HIFN_PLL_MBSET; ++ WRITE_REG_1(sc, HIFN_1_PLL, pll); ++ DELAY(10*1000); /* 10ms */ ++ ++ /* change configuration */ ++ pll = (pll &~ HIFN_PLL_CONFIG) | sc->sc_pllconfig; ++ WRITE_REG_1(sc, HIFN_1_PLL, pll); ++ DELAY(10*1000); /* 10ms */ ++ ++ /* disable bypass */ ++ pll &= ~HIFN_PLL_BP; ++ WRITE_REG_1(sc, HIFN_1_PLL, pll); ++ /* enable clocks with new configuration */ ++ pll |= HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL; ++ WRITE_REG_1(sc, HIFN_1_PLL, pll); ++ } else { ++ WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING | ++ HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES | ++ HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 | ++ (sc->sc_drammodel ? HIFN_PUCNFG_DRAM : HIFN_PUCNFG_SRAM)); ++ } ++ ++ WRITE_REG_0(sc, HIFN_0_PUISR, HIFN_PUISR_DSTOVER); ++ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | ++ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST | ++ ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) | ++ ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL)); ++} ++ ++/* ++ * The maximum number of sessions supported by the card ++ * is dependent on the amount of context ram, which ++ * encryption algorithms are enabled, and how compression ++ * is configured. This should be configured before this ++ * routine is called. ++ */ ++static void ++hifn_sessions(struct hifn_softc *sc) ++{ ++ u_int32_t pucnfg; ++ int ctxsize; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ pucnfg = READ_REG_0(sc, HIFN_0_PUCNFG); ++ ++ if (pucnfg & HIFN_PUCNFG_COMPSING) { ++ if (pucnfg & HIFN_PUCNFG_ENCCNFG) ++ ctxsize = 128; ++ else ++ ctxsize = 512; ++ /* ++ * 7955/7956 has internal context memory of 32K ++ */ ++ if (sc->sc_flags & HIFN_IS_7956) ++ sc->sc_maxses = 32768 / ctxsize; ++ else ++ sc->sc_maxses = 1 + ++ ((sc->sc_ramsize - 32768) / ctxsize); ++ } else ++ sc->sc_maxses = sc->sc_ramsize / 16384; ++ ++ if (sc->sc_maxses > 2048) ++ sc->sc_maxses = 2048; ++} ++ ++/* ++ * Determine ram type (sram or dram). Board should be just out of a reset ++ * state when this is called. ++ */ ++static int ++hifn_ramtype(struct hifn_softc *sc) ++{ ++ u_int8_t data[8], dataexpect[8]; ++ int i; ++ ++ for (i = 0; i < sizeof(data); i++) ++ data[i] = dataexpect[i] = 0x55; ++ if (hifn_writeramaddr(sc, 0, data)) ++ return (-1); ++ if (hifn_readramaddr(sc, 0, data)) ++ return (-1); ++ if (bcmp(data, dataexpect, sizeof(data)) != 0) { ++ sc->sc_drammodel = 1; ++ return (0); ++ } ++ ++ for (i = 0; i < sizeof(data); i++) ++ data[i] = dataexpect[i] = 0xaa; ++ if (hifn_writeramaddr(sc, 0, data)) ++ return (-1); ++ if (hifn_readramaddr(sc, 0, data)) ++ return (-1); ++ if (bcmp(data, dataexpect, sizeof(data)) != 0) { ++ sc->sc_drammodel = 1; ++ return (0); ++ } ++ ++ return (0); ++} ++ ++#define HIFN_SRAM_MAX (32 << 20) ++#define HIFN_SRAM_STEP_SIZE 16384 ++#define HIFN_SRAM_GRANULARITY (HIFN_SRAM_MAX / HIFN_SRAM_STEP_SIZE) ++ ++static int ++hifn_sramsize(struct hifn_softc *sc) ++{ ++ u_int32_t a; ++ u_int8_t data[8]; ++ u_int8_t dataexpect[sizeof(data)]; ++ int32_t i; ++ ++ for (i = 0; i < sizeof(data); i++) ++ data[i] = dataexpect[i] = i ^ 0x5a; ++ ++ for (i = HIFN_SRAM_GRANULARITY - 1; i >= 0; i--) { ++ a = i * HIFN_SRAM_STEP_SIZE; ++ bcopy(&i, data, sizeof(i)); ++ hifn_writeramaddr(sc, a, data); ++ } ++ ++ for (i = 0; i < HIFN_SRAM_GRANULARITY; i++) { ++ a = i * HIFN_SRAM_STEP_SIZE; ++ bcopy(&i, dataexpect, sizeof(i)); ++ if (hifn_readramaddr(sc, a, data) < 0) ++ return (0); ++ if (bcmp(data, dataexpect, sizeof(data)) != 0) ++ return (0); ++ sc->sc_ramsize = a + HIFN_SRAM_STEP_SIZE; ++ } ++ ++ return (0); ++} ++ ++/* ++ * XXX For dram boards, one should really try all of the ++ * HIFN_PUCNFG_DSZ_*'s. This just assumes that PUCNFG ++ * is already set up correctly. ++ */ ++static int ++hifn_dramsize(struct hifn_softc *sc) ++{ ++ u_int32_t cnfg; ++ ++ if (sc->sc_flags & HIFN_IS_7956) { ++ /* ++ * 7955/7956 have a fixed internal ram of only 32K. ++ */ ++ sc->sc_ramsize = 32768; ++ } else { ++ cnfg = READ_REG_0(sc, HIFN_0_PUCNFG) & ++ HIFN_PUCNFG_DRAMMASK; ++ sc->sc_ramsize = 1 << ((cnfg >> 13) + 18); ++ } ++ return (0); ++} ++ ++static void ++hifn_alloc_slot(struct hifn_softc *sc, int *cmdp, int *srcp, int *dstp, int *resp) ++{ ++ struct hifn_dma *dma = sc->sc_dma; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ if (dma->cmdi == HIFN_D_CMD_RSIZE) { ++ dma->cmdi = 0; ++ dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); ++ wmb(); ++ dma->cmdr[HIFN_D_CMD_RSIZE].l |= htole32(HIFN_D_VALID); ++ HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, ++ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); ++ } ++ *cmdp = dma->cmdi++; ++ dma->cmdk = dma->cmdi; ++ ++ if (dma->srci == HIFN_D_SRC_RSIZE) { ++ dma->srci = 0; ++ dma->srcr[HIFN_D_SRC_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); ++ wmb(); ++ dma->srcr[HIFN_D_SRC_RSIZE].l |= htole32(HIFN_D_VALID); ++ HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, ++ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); ++ } ++ *srcp = dma->srci++; ++ dma->srck = dma->srci; ++ ++ if (dma->dsti == HIFN_D_DST_RSIZE) { ++ dma->dsti = 0; ++ dma->dstr[HIFN_D_DST_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); ++ wmb(); ++ dma->dstr[HIFN_D_DST_RSIZE].l |= htole32(HIFN_D_VALID); ++ HIFN_DSTR_SYNC(sc, HIFN_D_DST_RSIZE, ++ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); ++ } ++ *dstp = dma->dsti++; ++ dma->dstk = dma->dsti; ++ ++ if (dma->resi == HIFN_D_RES_RSIZE) { ++ dma->resi = 0; ++ dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); ++ wmb(); ++ dma->resr[HIFN_D_RES_RSIZE].l |= htole32(HIFN_D_VALID); ++ HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, ++ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); ++ } ++ *resp = dma->resi++; ++ dma->resk = dma->resi; ++} ++ ++static int ++hifn_writeramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) ++{ ++ struct hifn_dma *dma = sc->sc_dma; ++ hifn_base_command_t wc; ++ const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; ++ int r, cmdi, resi, srci, dsti; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ wc.masks = htole16(3 << 13); ++ wc.session_num = htole16(addr >> 14); ++ wc.total_source_count = htole16(8); ++ wc.total_dest_count = htole16(addr & 0x3fff); ++ ++ hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); ++ ++ WRITE_REG_1(sc, HIFN_1_DMA_CSR, ++ HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | ++ HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); ++ ++ /* build write command */ ++ bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); ++ *(hifn_base_command_t *)dma->command_bufs[cmdi] = wc; ++ bcopy(data, &dma->test_src, sizeof(dma->test_src)); ++ ++ dma->srcr[srci].p = htole32(sc->sc_dma_physaddr ++ + offsetof(struct hifn_dma, test_src)); ++ dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr ++ + offsetof(struct hifn_dma, test_dst)); ++ ++ dma->cmdr[cmdi].l = htole32(16 | masks); ++ dma->srcr[srci].l = htole32(8 | masks); ++ dma->dstr[dsti].l = htole32(4 | masks); ++ dma->resr[resi].l = htole32(4 | masks); ++ ++ for (r = 10000; r >= 0; r--) { ++ DELAY(10); ++ if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) ++ break; ++ } ++ if (r == 0) { ++ device_printf(sc->sc_dev, "writeramaddr -- " ++ "result[%d](addr %d) still valid\n", resi, addr); ++ r = -1; ++ return (-1); ++ } else ++ r = 0; ++ ++ WRITE_REG_1(sc, HIFN_1_DMA_CSR, ++ HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | ++ HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); ++ ++ return (r); ++} ++ ++static int ++hifn_readramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) ++{ ++ struct hifn_dma *dma = sc->sc_dma; ++ hifn_base_command_t rc; ++ const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; ++ int r, cmdi, srci, dsti, resi; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ rc.masks = htole16(2 << 13); ++ rc.session_num = htole16(addr >> 14); ++ rc.total_source_count = htole16(addr & 0x3fff); ++ rc.total_dest_count = htole16(8); ++ ++ hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); ++ ++ WRITE_REG_1(sc, HIFN_1_DMA_CSR, ++ HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | ++ HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); ++ ++ bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); ++ *(hifn_base_command_t *)dma->command_bufs[cmdi] = rc; ++ ++ dma->srcr[srci].p = htole32(sc->sc_dma_physaddr + ++ offsetof(struct hifn_dma, test_src)); ++ dma->test_src = 0; ++ dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr + ++ offsetof(struct hifn_dma, test_dst)); ++ dma->test_dst = 0; ++ dma->cmdr[cmdi].l = htole32(8 | masks); ++ dma->srcr[srci].l = htole32(8 | masks); ++ dma->dstr[dsti].l = htole32(8 | masks); ++ dma->resr[resi].l = htole32(HIFN_MAX_RESULT | masks); ++ ++ for (r = 10000; r >= 0; r--) { ++ DELAY(10); ++ if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) ++ break; ++ } ++ if (r == 0) { ++ device_printf(sc->sc_dev, "readramaddr -- " ++ "result[%d](addr %d) still valid\n", resi, addr); ++ r = -1; ++ } else { ++ r = 0; ++ bcopy(&dma->test_dst, data, sizeof(dma->test_dst)); ++ } ++ ++ WRITE_REG_1(sc, HIFN_1_DMA_CSR, ++ HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | ++ HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); ++ ++ return (r); ++} ++ ++/* ++ * Initialize the descriptor rings. ++ */ ++static void ++hifn_init_dma(struct hifn_softc *sc) ++{ ++ struct hifn_dma *dma = sc->sc_dma; ++ int i; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ hifn_set_retry(sc); ++ ++ /* initialize static pointer values */ ++ for (i = 0; i < HIFN_D_CMD_RSIZE; i++) ++ dma->cmdr[i].p = htole32(sc->sc_dma_physaddr + ++ offsetof(struct hifn_dma, command_bufs[i][0])); ++ for (i = 0; i < HIFN_D_RES_RSIZE; i++) ++ dma->resr[i].p = htole32(sc->sc_dma_physaddr + ++ offsetof(struct hifn_dma, result_bufs[i][0])); ++ ++ dma->cmdr[HIFN_D_CMD_RSIZE].p = ++ htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, cmdr[0])); ++ dma->srcr[HIFN_D_SRC_RSIZE].p = ++ htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, srcr[0])); ++ dma->dstr[HIFN_D_DST_RSIZE].p = ++ htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, dstr[0])); ++ dma->resr[HIFN_D_RES_RSIZE].p = ++ htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, resr[0])); ++ ++ dma->cmdu = dma->srcu = dma->dstu = dma->resu = 0; ++ dma->cmdi = dma->srci = dma->dsti = dma->resi = 0; ++ dma->cmdk = dma->srck = dma->dstk = dma->resk = 0; ++} ++ ++/* ++ * Writes out the raw command buffer space. Returns the ++ * command buffer size. ++ */ ++static u_int ++hifn_write_command(struct hifn_command *cmd, u_int8_t *buf) ++{ ++ struct hifn_softc *sc = NULL; ++ u_int8_t *buf_pos; ++ hifn_base_command_t *base_cmd; ++ hifn_mac_command_t *mac_cmd; ++ hifn_crypt_command_t *cry_cmd; ++ int using_mac, using_crypt, len, ivlen; ++ u_int32_t dlen, slen; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ buf_pos = buf; ++ using_mac = cmd->base_masks & HIFN_BASE_CMD_MAC; ++ using_crypt = cmd->base_masks & HIFN_BASE_CMD_CRYPT; ++ ++ base_cmd = (hifn_base_command_t *)buf_pos; ++ base_cmd->masks = htole16(cmd->base_masks); ++ slen = cmd->src_mapsize; ++ if (cmd->sloplen) ++ dlen = cmd->dst_mapsize - cmd->sloplen + sizeof(u_int32_t); ++ else ++ dlen = cmd->dst_mapsize; ++ base_cmd->total_source_count = htole16(slen & HIFN_BASE_CMD_LENMASK_LO); ++ base_cmd->total_dest_count = htole16(dlen & HIFN_BASE_CMD_LENMASK_LO); ++ dlen >>= 16; ++ slen >>= 16; ++ base_cmd->session_num = htole16( ++ ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) | ++ ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M)); ++ buf_pos += sizeof(hifn_base_command_t); ++ ++ if (using_mac) { ++ mac_cmd = (hifn_mac_command_t *)buf_pos; ++ dlen = cmd->maccrd->crd_len; ++ mac_cmd->source_count = htole16(dlen & 0xffff); ++ dlen >>= 16; ++ mac_cmd->masks = htole16(cmd->mac_masks | ++ ((dlen << HIFN_MAC_CMD_SRCLEN_S) & HIFN_MAC_CMD_SRCLEN_M)); ++ mac_cmd->header_skip = htole16(cmd->maccrd->crd_skip); ++ mac_cmd->reserved = 0; ++ buf_pos += sizeof(hifn_mac_command_t); ++ } ++ ++ if (using_crypt) { ++ cry_cmd = (hifn_crypt_command_t *)buf_pos; ++ dlen = cmd->enccrd->crd_len; ++ cry_cmd->source_count = htole16(dlen & 0xffff); ++ dlen >>= 16; ++ cry_cmd->masks = htole16(cmd->cry_masks | ++ ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) & HIFN_CRYPT_CMD_SRCLEN_M)); ++ cry_cmd->header_skip = htole16(cmd->enccrd->crd_skip); ++ cry_cmd->reserved = 0; ++ buf_pos += sizeof(hifn_crypt_command_t); ++ } ++ ++ if (using_mac && cmd->mac_masks & HIFN_MAC_CMD_NEW_KEY) { ++ bcopy(cmd->mac, buf_pos, HIFN_MAC_KEY_LENGTH); ++ buf_pos += HIFN_MAC_KEY_LENGTH; ++ } ++ ++ if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_KEY) { ++ switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) { ++ case HIFN_CRYPT_CMD_ALG_3DES: ++ bcopy(cmd->ck, buf_pos, HIFN_3DES_KEY_LENGTH); ++ buf_pos += HIFN_3DES_KEY_LENGTH; ++ break; ++ case HIFN_CRYPT_CMD_ALG_DES: ++ bcopy(cmd->ck, buf_pos, HIFN_DES_KEY_LENGTH); ++ buf_pos += HIFN_DES_KEY_LENGTH; ++ break; ++ case HIFN_CRYPT_CMD_ALG_RC4: ++ len = 256; ++ do { ++ int clen; ++ ++ clen = MIN(cmd->cklen, len); ++ bcopy(cmd->ck, buf_pos, clen); ++ len -= clen; ++ buf_pos += clen; ++ } while (len > 0); ++ bzero(buf_pos, 4); ++ buf_pos += 4; ++ break; ++ case HIFN_CRYPT_CMD_ALG_AES: ++ /* ++ * AES keys are variable 128, 192 and ++ * 256 bits (16, 24 and 32 bytes). ++ */ ++ bcopy(cmd->ck, buf_pos, cmd->cklen); ++ buf_pos += cmd->cklen; ++ break; ++ } ++ } ++ ++ if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_IV) { ++ switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) { ++ case HIFN_CRYPT_CMD_ALG_AES: ++ ivlen = HIFN_AES_IV_LENGTH; ++ break; ++ default: ++ ivlen = HIFN_IV_LENGTH; ++ break; ++ } ++ bcopy(cmd->iv, buf_pos, ivlen); ++ buf_pos += ivlen; ++ } ++ ++ if ((cmd->base_masks & (HIFN_BASE_CMD_MAC|HIFN_BASE_CMD_CRYPT)) == 0) { ++ bzero(buf_pos, 8); ++ buf_pos += 8; ++ } ++ ++ return (buf_pos - buf); ++} ++ ++static int ++hifn_dmamap_aligned(struct hifn_operand *op) ++{ ++ struct hifn_softc *sc = NULL; ++ int i; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ for (i = 0; i < op->nsegs; i++) { ++ if (op->segs[i].ds_addr & 3) ++ return (0); ++ if ((i != (op->nsegs - 1)) && (op->segs[i].ds_len & 3)) ++ return (0); ++ } ++ return (1); ++} ++ ++static __inline int ++hifn_dmamap_dstwrap(struct hifn_softc *sc, int idx) ++{ ++ struct hifn_dma *dma = sc->sc_dma; ++ ++ if (++idx == HIFN_D_DST_RSIZE) { ++ dma->dstr[idx].l = htole32(HIFN_D_VALID | HIFN_D_JUMP | ++ HIFN_D_MASKDONEIRQ); ++ HIFN_DSTR_SYNC(sc, idx, ++ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ++ idx = 0; ++ } ++ return (idx); ++} ++ ++static int ++hifn_dmamap_load_dst(struct hifn_softc *sc, struct hifn_command *cmd) ++{ ++ struct hifn_dma *dma = sc->sc_dma; ++ struct hifn_operand *dst = &cmd->dst; ++ u_int32_t p, l; ++ int idx, used = 0, i; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ idx = dma->dsti; ++ for (i = 0; i < dst->nsegs - 1; i++) { ++ dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); ++ dma->dstr[idx].l = htole32(HIFN_D_MASKDONEIRQ | dst->segs[i].ds_len); ++ wmb(); ++ dma->dstr[idx].l |= htole32(HIFN_D_VALID); ++ HIFN_DSTR_SYNC(sc, idx, ++ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ++ used++; ++ ++ idx = hifn_dmamap_dstwrap(sc, idx); ++ } ++ ++ if (cmd->sloplen == 0) { ++ p = dst->segs[i].ds_addr; ++ l = HIFN_D_MASKDONEIRQ | HIFN_D_LAST | ++ dst->segs[i].ds_len; ++ } else { ++ p = sc->sc_dma_physaddr + ++ offsetof(struct hifn_dma, slop[cmd->slopidx]); ++ l = HIFN_D_MASKDONEIRQ | HIFN_D_LAST | ++ sizeof(u_int32_t); ++ ++ if ((dst->segs[i].ds_len - cmd->sloplen) != 0) { ++ dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); ++ dma->dstr[idx].l = htole32(HIFN_D_MASKDONEIRQ | ++ (dst->segs[i].ds_len - cmd->sloplen)); ++ wmb(); ++ dma->dstr[idx].l |= htole32(HIFN_D_VALID); ++ HIFN_DSTR_SYNC(sc, idx, ++ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ++ used++; ++ ++ idx = hifn_dmamap_dstwrap(sc, idx); ++ } ++ } ++ dma->dstr[idx].p = htole32(p); ++ dma->dstr[idx].l = htole32(l); ++ wmb(); ++ dma->dstr[idx].l |= htole32(HIFN_D_VALID); ++ HIFN_DSTR_SYNC(sc, idx, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ++ used++; ++ ++ idx = hifn_dmamap_dstwrap(sc, idx); ++ ++ dma->dsti = idx; ++ dma->dstu += used; ++ return (idx); ++} ++ ++static __inline int ++hifn_dmamap_srcwrap(struct hifn_softc *sc, int idx) ++{ ++ struct hifn_dma *dma = sc->sc_dma; ++ ++ if (++idx == HIFN_D_SRC_RSIZE) { ++ dma->srcr[idx].l = htole32(HIFN_D_VALID | ++ HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); ++ HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, ++ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); ++ idx = 0; ++ } ++ return (idx); ++} ++ ++static int ++hifn_dmamap_load_src(struct hifn_softc *sc, struct hifn_command *cmd) ++{ ++ struct hifn_dma *dma = sc->sc_dma; ++ struct hifn_operand *src = &cmd->src; ++ int idx, i; ++ u_int32_t last = 0; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ idx = dma->srci; ++ for (i = 0; i < src->nsegs; i++) { ++ if (i == src->nsegs - 1) ++ last = HIFN_D_LAST; ++ ++ dma->srcr[idx].p = htole32(src->segs[i].ds_addr); ++ dma->srcr[idx].l = htole32(src->segs[i].ds_len | ++ HIFN_D_MASKDONEIRQ | last); ++ wmb(); ++ dma->srcr[idx].l |= htole32(HIFN_D_VALID); ++ HIFN_SRCR_SYNC(sc, idx, ++ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); ++ ++ idx = hifn_dmamap_srcwrap(sc, idx); ++ } ++ dma->srci = idx; ++ dma->srcu += src->nsegs; ++ return (idx); ++} ++ ++ ++static int ++hifn_crypto( ++ struct hifn_softc *sc, ++ struct hifn_command *cmd, ++ struct cryptop *crp, ++ int hint) ++{ ++ struct hifn_dma *dma = sc->sc_dma; ++ u_int32_t cmdlen, csr; ++ int cmdi, resi, err = 0; ++ unsigned long l_flags; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ /* ++ * need 1 cmd, and 1 res ++ * ++ * NB: check this first since it's easy. ++ */ ++ HIFN_LOCK(sc); ++ if ((dma->cmdu + 1) > HIFN_D_CMD_RSIZE || ++ (dma->resu + 1) > HIFN_D_RES_RSIZE) { ++#ifdef HIFN_DEBUG ++ if (hifn_debug) { ++ device_printf(sc->sc_dev, ++ "cmd/result exhaustion, cmdu %u resu %u\n", ++ dma->cmdu, dma->resu); ++ } ++#endif ++ hifnstats.hst_nomem_cr++; ++ sc->sc_needwakeup |= CRYPTO_SYMQ; ++ HIFN_UNLOCK(sc); ++ return (ERESTART); ++ } ++ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ if (pci_map_skb(sc, &cmd->src, cmd->src_skb)) { ++ hifnstats.hst_nomem_load++; ++ err = ENOMEM; ++ goto err_srcmap1; ++ } ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ if (pci_map_uio(sc, &cmd->src, cmd->src_io)) { ++ hifnstats.hst_nomem_load++; ++ err = ENOMEM; ++ goto err_srcmap1; ++ } ++ } else { ++ if (pci_map_buf(sc, &cmd->src, cmd->src_buf, crp->crp_ilen)) { ++ hifnstats.hst_nomem_load++; ++ err = ENOMEM; ++ goto err_srcmap1; ++ } ++ } ++ ++ if (hifn_dmamap_aligned(&cmd->src)) { ++ cmd->sloplen = cmd->src_mapsize & 3; ++ cmd->dst = cmd->src; ++ } else { ++ if (crp->crp_flags & CRYPTO_F_IOV) { ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ err = EINVAL; ++ goto err_srcmap; ++ } else if (crp->crp_flags & CRYPTO_F_SKBUF) { ++#ifdef NOTYET ++ int totlen, len; ++ struct mbuf *m, *m0, *mlast; ++ ++ KASSERT(cmd->dst_m == cmd->src_m, ++ ("hifn_crypto: dst_m initialized improperly")); ++ hifnstats.hst_unaligned++; ++ /* ++ * Source is not aligned on a longword boundary. ++ * Copy the data to insure alignment. If we fail ++ * to allocate mbufs or clusters while doing this ++ * we return ERESTART so the operation is requeued ++ * at the crypto later, but only if there are ++ * ops already posted to the hardware; otherwise we ++ * have no guarantee that we'll be re-entered. ++ */ ++ totlen = cmd->src_mapsize; ++ if (cmd->src_m->m_flags & M_PKTHDR) { ++ len = MHLEN; ++ MGETHDR(m0, M_DONTWAIT, MT_DATA); ++ if (m0 && !m_dup_pkthdr(m0, cmd->src_m, M_DONTWAIT)) { ++ m_free(m0); ++ m0 = NULL; ++ } ++ } else { ++ len = MLEN; ++ MGET(m0, M_DONTWAIT, MT_DATA); ++ } ++ if (m0 == NULL) { ++ hifnstats.hst_nomem_mbuf++; ++ err = dma->cmdu ? ERESTART : ENOMEM; ++ goto err_srcmap; ++ } ++ if (totlen >= MINCLSIZE) { ++ MCLGET(m0, M_DONTWAIT); ++ if ((m0->m_flags & M_EXT) == 0) { ++ hifnstats.hst_nomem_mcl++; ++ err = dma->cmdu ? ERESTART : ENOMEM; ++ m_freem(m0); ++ goto err_srcmap; ++ } ++ len = MCLBYTES; ++ } ++ totlen -= len; ++ m0->m_pkthdr.len = m0->m_len = len; ++ mlast = m0; ++ ++ while (totlen > 0) { ++ MGET(m, M_DONTWAIT, MT_DATA); ++ if (m == NULL) { ++ hifnstats.hst_nomem_mbuf++; ++ err = dma->cmdu ? ERESTART : ENOMEM; ++ m_freem(m0); ++ goto err_srcmap; ++ } ++ len = MLEN; ++ if (totlen >= MINCLSIZE) { ++ MCLGET(m, M_DONTWAIT); ++ if ((m->m_flags & M_EXT) == 0) { ++ hifnstats.hst_nomem_mcl++; ++ err = dma->cmdu ? ERESTART : ENOMEM; ++ mlast->m_next = m; ++ m_freem(m0); ++ goto err_srcmap; ++ } ++ len = MCLBYTES; ++ } ++ ++ m->m_len = len; ++ m0->m_pkthdr.len += len; ++ totlen -= len; ++ ++ mlast->m_next = m; ++ mlast = m; ++ } ++ cmd->dst_m = m0; ++#else ++ device_printf(sc->sc_dev, ++ "%s,%d: CRYPTO_F_SKBUF unaligned not implemented\n", ++ __FILE__, __LINE__); ++ err = EINVAL; ++ goto err_srcmap; ++#endif ++ } else { ++ device_printf(sc->sc_dev, ++ "%s,%d: unaligned contig buffers not implemented\n", ++ __FILE__, __LINE__); ++ err = EINVAL; ++ goto err_srcmap; ++ } ++ } ++ ++ if (cmd->dst_map == NULL) { ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ if (pci_map_skb(sc, &cmd->dst, cmd->dst_skb)) { ++ hifnstats.hst_nomem_map++; ++ err = ENOMEM; ++ goto err_dstmap1; ++ } ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ if (pci_map_uio(sc, &cmd->dst, cmd->dst_io)) { ++ hifnstats.hst_nomem_load++; ++ err = ENOMEM; ++ goto err_dstmap1; ++ } ++ } else { ++ if (pci_map_buf(sc, &cmd->dst, cmd->dst_buf, crp->crp_ilen)) { ++ hifnstats.hst_nomem_load++; ++ err = ENOMEM; ++ goto err_dstmap1; ++ } ++ } ++ } ++ ++#ifdef HIFN_DEBUG ++ if (hifn_debug) { ++ device_printf(sc->sc_dev, ++ "Entering cmd: stat %8x ien %8x u %d/%d/%d/%d n %d/%d\n", ++ READ_REG_1(sc, HIFN_1_DMA_CSR), ++ READ_REG_1(sc, HIFN_1_DMA_IER), ++ dma->cmdu, dma->srcu, dma->dstu, dma->resu, ++ cmd->src_nsegs, cmd->dst_nsegs); ++ } ++#endif ++ ++#if 0 ++ if (cmd->src_map == cmd->dst_map) { ++ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, ++ BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); ++ } else { ++ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, ++ BUS_DMASYNC_PREWRITE); ++ bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, ++ BUS_DMASYNC_PREREAD); ++ } ++#endif ++ ++ /* ++ * need N src, and N dst ++ */ ++ if ((dma->srcu + cmd->src_nsegs) > HIFN_D_SRC_RSIZE || ++ (dma->dstu + cmd->dst_nsegs + 1) > HIFN_D_DST_RSIZE) { ++#ifdef HIFN_DEBUG ++ if (hifn_debug) { ++ device_printf(sc->sc_dev, ++ "src/dst exhaustion, srcu %u+%u dstu %u+%u\n", ++ dma->srcu, cmd->src_nsegs, ++ dma->dstu, cmd->dst_nsegs); ++ } ++#endif ++ hifnstats.hst_nomem_sd++; ++ err = ERESTART; ++ goto err_dstmap; ++ } ++ ++ if (dma->cmdi == HIFN_D_CMD_RSIZE) { ++ dma->cmdi = 0; ++ dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); ++ wmb(); ++ dma->cmdr[HIFN_D_CMD_RSIZE].l |= htole32(HIFN_D_VALID); ++ HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, ++ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); ++ } ++ cmdi = dma->cmdi++; ++ cmdlen = hifn_write_command(cmd, dma->command_bufs[cmdi]); ++ HIFN_CMD_SYNC(sc, cmdi, BUS_DMASYNC_PREWRITE); ++ ++ /* .p for command/result already set */ ++ dma->cmdr[cmdi].l = htole32(cmdlen | HIFN_D_LAST | ++ HIFN_D_MASKDONEIRQ); ++ wmb(); ++ dma->cmdr[cmdi].l |= htole32(HIFN_D_VALID); ++ HIFN_CMDR_SYNC(sc, cmdi, ++ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); ++ dma->cmdu++; ++ ++ /* ++ * We don't worry about missing an interrupt (which a "command wait" ++ * interrupt salvages us from), unless there is more than one command ++ * in the queue. ++ */ ++ if (dma->cmdu > 1) { ++ sc->sc_dmaier |= HIFN_DMAIER_C_WAIT; ++ WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); ++ } ++ ++ hifnstats.hst_ipackets++; ++ hifnstats.hst_ibytes += cmd->src_mapsize; ++ ++ hifn_dmamap_load_src(sc, cmd); ++ ++ /* ++ * Unlike other descriptors, we don't mask done interrupt from ++ * result descriptor. ++ */ ++#ifdef HIFN_DEBUG ++ if (hifn_debug) ++ device_printf(sc->sc_dev, "load res\n"); ++#endif ++ if (dma->resi == HIFN_D_RES_RSIZE) { ++ dma->resi = 0; ++ dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); ++ wmb(); ++ dma->resr[HIFN_D_RES_RSIZE].l |= htole32(HIFN_D_VALID); ++ HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, ++ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ++ } ++ resi = dma->resi++; ++ KASSERT(dma->hifn_commands[resi] == NULL, ++ ("hifn_crypto: command slot %u busy", resi)); ++ dma->hifn_commands[resi] = cmd; ++ HIFN_RES_SYNC(sc, resi, BUS_DMASYNC_PREREAD); ++ if ((hint & CRYPTO_HINT_MORE) && sc->sc_curbatch < hifn_maxbatch) { ++ dma->resr[resi].l = htole32(HIFN_MAX_RESULT | ++ HIFN_D_LAST | HIFN_D_MASKDONEIRQ); ++ wmb(); ++ dma->resr[resi].l |= htole32(HIFN_D_VALID); ++ sc->sc_curbatch++; ++ if (sc->sc_curbatch > hifnstats.hst_maxbatch) ++ hifnstats.hst_maxbatch = sc->sc_curbatch; ++ hifnstats.hst_totbatch++; ++ } else { ++ dma->resr[resi].l = htole32(HIFN_MAX_RESULT | HIFN_D_LAST); ++ wmb(); ++ dma->resr[resi].l |= htole32(HIFN_D_VALID); ++ sc->sc_curbatch = 0; ++ } ++ HIFN_RESR_SYNC(sc, resi, ++ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ++ dma->resu++; ++ ++ if (cmd->sloplen) ++ cmd->slopidx = resi; ++ ++ hifn_dmamap_load_dst(sc, cmd); ++ ++ csr = 0; ++ if (sc->sc_c_busy == 0) { ++ csr |= HIFN_DMACSR_C_CTRL_ENA; ++ sc->sc_c_busy = 1; ++ } ++ if (sc->sc_s_busy == 0) { ++ csr |= HIFN_DMACSR_S_CTRL_ENA; ++ sc->sc_s_busy = 1; ++ } ++ if (sc->sc_r_busy == 0) { ++ csr |= HIFN_DMACSR_R_CTRL_ENA; ++ sc->sc_r_busy = 1; ++ } ++ if (sc->sc_d_busy == 0) { ++ csr |= HIFN_DMACSR_D_CTRL_ENA; ++ sc->sc_d_busy = 1; ++ } ++ if (csr) ++ WRITE_REG_1(sc, HIFN_1_DMA_CSR, csr); ++ ++#ifdef HIFN_DEBUG ++ if (hifn_debug) { ++ device_printf(sc->sc_dev, "command: stat %8x ier %8x\n", ++ READ_REG_1(sc, HIFN_1_DMA_CSR), ++ READ_REG_1(sc, HIFN_1_DMA_IER)); ++ } ++#endif ++ ++ sc->sc_active = 5; ++ HIFN_UNLOCK(sc); ++ KASSERT(err == 0, ("hifn_crypto: success with error %u", err)); ++ return (err); /* success */ ++ ++err_dstmap: ++ if (cmd->src_map != cmd->dst_map) ++ pci_unmap_buf(sc, &cmd->dst); ++err_dstmap1: ++err_srcmap: ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ if (cmd->src_skb != cmd->dst_skb) ++#ifdef NOTYET ++ m_freem(cmd->dst_m); ++#else ++ device_printf(sc->sc_dev, ++ "%s,%d: CRYPTO_F_SKBUF src != dst not implemented\n", ++ __FILE__, __LINE__); ++#endif ++ } ++ pci_unmap_buf(sc, &cmd->src); ++err_srcmap1: ++ HIFN_UNLOCK(sc); ++ return (err); ++} ++ ++static void ++hifn_tick(unsigned long arg) ++{ ++ struct hifn_softc *sc; ++ unsigned long l_flags; ++ ++ if (arg >= HIFN_MAX_CHIPS) ++ return; ++ sc = hifn_chip_idx[arg]; ++ if (!sc) ++ return; ++ ++ HIFN_LOCK(sc); ++ if (sc->sc_active == 0) { ++ struct hifn_dma *dma = sc->sc_dma; ++ u_int32_t r = 0; ++ ++ if (dma->cmdu == 0 && sc->sc_c_busy) { ++ sc->sc_c_busy = 0; ++ r |= HIFN_DMACSR_C_CTRL_DIS; ++ } ++ if (dma->srcu == 0 && sc->sc_s_busy) { ++ sc->sc_s_busy = 0; ++ r |= HIFN_DMACSR_S_CTRL_DIS; ++ } ++ if (dma->dstu == 0 && sc->sc_d_busy) { ++ sc->sc_d_busy = 0; ++ r |= HIFN_DMACSR_D_CTRL_DIS; ++ } ++ if (dma->resu == 0 && sc->sc_r_busy) { ++ sc->sc_r_busy = 0; ++ r |= HIFN_DMACSR_R_CTRL_DIS; ++ } ++ if (r) ++ WRITE_REG_1(sc, HIFN_1_DMA_CSR, r); ++ } else ++ sc->sc_active--; ++ HIFN_UNLOCK(sc); ++ mod_timer(&sc->sc_tickto, jiffies + HZ); ++} ++ ++static irqreturn_t ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) ++hifn_intr(int irq, void *arg) ++#else ++hifn_intr(int irq, void *arg, struct pt_regs *regs) ++#endif ++{ ++ struct hifn_softc *sc = arg; ++ struct hifn_dma *dma; ++ u_int32_t dmacsr, restart; ++ int i, u; ++ unsigned long l_flags; ++ ++ dmacsr = READ_REG_1(sc, HIFN_1_DMA_CSR); ++ ++ /* Nothing in the DMA unit interrupted */ ++ if ((dmacsr & sc->sc_dmaier) == 0) ++ return IRQ_NONE; ++ ++ HIFN_LOCK(sc); ++ ++ dma = sc->sc_dma; ++ ++#ifdef HIFN_DEBUG ++ if (hifn_debug) { ++ device_printf(sc->sc_dev, ++ "irq: stat %08x ien %08x damier %08x i %d/%d/%d/%d k %d/%d/%d/%d u %d/%d/%d/%d\n", ++ dmacsr, READ_REG_1(sc, HIFN_1_DMA_IER), sc->sc_dmaier, ++ dma->cmdi, dma->srci, dma->dsti, dma->resi, ++ dma->cmdk, dma->srck, dma->dstk, dma->resk, ++ dma->cmdu, dma->srcu, dma->dstu, dma->resu); ++ } ++#endif ++ ++ WRITE_REG_1(sc, HIFN_1_DMA_CSR, dmacsr & sc->sc_dmaier); ++ ++ if ((sc->sc_flags & HIFN_HAS_PUBLIC) && ++ (dmacsr & HIFN_DMACSR_PUBDONE)) ++ WRITE_REG_1(sc, HIFN_1_PUB_STATUS, ++ READ_REG_1(sc, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE); ++ ++ restart = dmacsr & (HIFN_DMACSR_D_OVER | HIFN_DMACSR_R_OVER); ++ if (restart) ++ device_printf(sc->sc_dev, "overrun %x\n", dmacsr); ++ ++ if (sc->sc_flags & HIFN_IS_7811) { ++ if (dmacsr & HIFN_DMACSR_ILLR) ++ device_printf(sc->sc_dev, "illegal read\n"); ++ if (dmacsr & HIFN_DMACSR_ILLW) ++ device_printf(sc->sc_dev, "illegal write\n"); ++ } ++ ++ restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT | ++ HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT); ++ if (restart) { ++ device_printf(sc->sc_dev, "abort, resetting.\n"); ++ hifnstats.hst_abort++; ++ hifn_abort(sc); ++ HIFN_UNLOCK(sc); ++ return IRQ_HANDLED; ++ } ++ ++ if ((dmacsr & HIFN_DMACSR_C_WAIT) && (dma->cmdu == 0)) { ++ /* ++ * If no slots to process and we receive a "waiting on ++ * command" interrupt, we disable the "waiting on command" ++ * (by clearing it). ++ */ ++ sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; ++ WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); ++ } ++ ++ /* clear the rings */ ++ i = dma->resk; u = dma->resu; ++ while (u != 0) { ++ HIFN_RESR_SYNC(sc, i, ++ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); ++ if (dma->resr[i].l & htole32(HIFN_D_VALID)) { ++ HIFN_RESR_SYNC(sc, i, ++ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ++ break; ++ } ++ ++ if (i != HIFN_D_RES_RSIZE) { ++ struct hifn_command *cmd; ++ u_int8_t *macbuf = NULL; ++ ++ HIFN_RES_SYNC(sc, i, BUS_DMASYNC_POSTREAD); ++ cmd = dma->hifn_commands[i]; ++ KASSERT(cmd != NULL, ++ ("hifn_intr: null command slot %u", i)); ++ dma->hifn_commands[i] = NULL; ++ ++ if (cmd->base_masks & HIFN_BASE_CMD_MAC) { ++ macbuf = dma->result_bufs[i]; ++ macbuf += 12; ++ } ++ ++ hifn_callback(sc, cmd, macbuf); ++ hifnstats.hst_opackets++; ++ u--; ++ } ++ ++ if (++i == (HIFN_D_RES_RSIZE + 1)) ++ i = 0; ++ } ++ dma->resk = i; dma->resu = u; ++ ++ i = dma->srck; u = dma->srcu; ++ while (u != 0) { ++ if (i == HIFN_D_SRC_RSIZE) ++ i = 0; ++ HIFN_SRCR_SYNC(sc, i, ++ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); ++ if (dma->srcr[i].l & htole32(HIFN_D_VALID)) { ++ HIFN_SRCR_SYNC(sc, i, ++ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ++ break; ++ } ++ i++, u--; ++ } ++ dma->srck = i; dma->srcu = u; ++ ++ i = dma->cmdk; u = dma->cmdu; ++ while (u != 0) { ++ HIFN_CMDR_SYNC(sc, i, ++ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); ++ if (dma->cmdr[i].l & htole32(HIFN_D_VALID)) { ++ HIFN_CMDR_SYNC(sc, i, ++ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ++ break; ++ } ++ if (i != HIFN_D_CMD_RSIZE) { ++ u--; ++ HIFN_CMD_SYNC(sc, i, BUS_DMASYNC_POSTWRITE); ++ } ++ if (++i == (HIFN_D_CMD_RSIZE + 1)) ++ i = 0; ++ } ++ dma->cmdk = i; dma->cmdu = u; ++ ++ HIFN_UNLOCK(sc); ++ ++ if (sc->sc_needwakeup) { /* XXX check high watermark */ ++ int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); ++#ifdef HIFN_DEBUG ++ if (hifn_debug) ++ device_printf(sc->sc_dev, ++ "wakeup crypto (%x) u %d/%d/%d/%d\n", ++ sc->sc_needwakeup, ++ dma->cmdu, dma->srcu, dma->dstu, dma->resu); ++#endif ++ sc->sc_needwakeup &= ~wakeup; ++ crypto_unblock(sc->sc_cid, wakeup); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++/* ++ * Allocate a new 'session' and return an encoded session id. 'sidp' ++ * contains our registration id, and should contain an encoded session ++ * id on successful allocation. ++ */ ++static int ++hifn_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) ++{ ++ struct hifn_softc *sc = device_get_softc(dev); ++ struct cryptoini *c; ++ int mac = 0, cry = 0, sesn; ++ struct hifn_session *ses = NULL; ++ unsigned long l_flags; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ KASSERT(sc != NULL, ("hifn_newsession: null softc")); ++ if (sidp == NULL || cri == NULL || sc == NULL) { ++ DPRINTF("%s,%d: %s - EINVAL\n", __FILE__, __LINE__, __FUNCTION__); ++ return (EINVAL); ++ } ++ ++ HIFN_LOCK(sc); ++ if (sc->sc_sessions == NULL) { ++ ses = sc->sc_sessions = (struct hifn_session *)kmalloc(sizeof(*ses), ++ SLAB_ATOMIC); ++ if (ses == NULL) { ++ HIFN_UNLOCK(sc); ++ return (ENOMEM); ++ } ++ sesn = 0; ++ sc->sc_nsessions = 1; ++ } else { ++ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { ++ if (!sc->sc_sessions[sesn].hs_used) { ++ ses = &sc->sc_sessions[sesn]; ++ break; ++ } ++ } ++ ++ if (ses == NULL) { ++ sesn = sc->sc_nsessions; ++ ses = (struct hifn_session *)kmalloc((sesn + 1) * sizeof(*ses), ++ SLAB_ATOMIC); ++ if (ses == NULL) { ++ HIFN_UNLOCK(sc); ++ return (ENOMEM); ++ } ++ bcopy(sc->sc_sessions, ses, sesn * sizeof(*ses)); ++ bzero(sc->sc_sessions, sesn * sizeof(*ses)); ++ kfree(sc->sc_sessions); ++ sc->sc_sessions = ses; ++ ses = &sc->sc_sessions[sesn]; ++ sc->sc_nsessions++; ++ } ++ } ++ HIFN_UNLOCK(sc); ++ ++ bzero(ses, sizeof(*ses)); ++ ses->hs_used = 1; ++ ++ for (c = cri; c != NULL; c = c->cri_next) { ++ switch (c->cri_alg) { ++ case CRYPTO_MD5: ++ case CRYPTO_SHA1: ++ case CRYPTO_MD5_HMAC: ++ case CRYPTO_SHA1_HMAC: ++ if (mac) { ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ return (EINVAL); ++ } ++ mac = 1; ++ ses->hs_mlen = c->cri_mlen; ++ if (ses->hs_mlen == 0) { ++ switch (c->cri_alg) { ++ case CRYPTO_MD5: ++ case CRYPTO_MD5_HMAC: ++ ses->hs_mlen = 16; ++ break; ++ case CRYPTO_SHA1: ++ case CRYPTO_SHA1_HMAC: ++ ses->hs_mlen = 20; ++ break; ++ } ++ } ++ break; ++ case CRYPTO_DES_CBC: ++ case CRYPTO_3DES_CBC: ++ case CRYPTO_AES_CBC: ++ case CRYPTO_ARC4: ++ if (cry) { ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ return (EINVAL); ++ } ++ cry = 1; ++ break; ++ default: ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ return (EINVAL); ++ } ++ } ++ if (mac == 0 && cry == 0) { ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ return (EINVAL); ++ } ++ ++ *sidp = HIFN_SID(device_get_unit(sc->sc_dev), sesn); ++ ++ return (0); ++} ++ ++/* ++ * Deallocate a session. ++ * XXX this routine should run a zero'd mac/encrypt key into context ram. ++ * XXX to blow away any keys already stored there. ++ */ ++static int ++hifn_freesession(device_t dev, u_int64_t tid) ++{ ++ struct hifn_softc *sc = device_get_softc(dev); ++ int session, error; ++ u_int32_t sid = CRYPTO_SESID2LID(tid); ++ unsigned long l_flags; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ KASSERT(sc != NULL, ("hifn_freesession: null softc")); ++ if (sc == NULL) { ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ return (EINVAL); ++ } ++ ++ HIFN_LOCK(sc); ++ session = HIFN_SESSION(sid); ++ if (session < sc->sc_nsessions) { ++ bzero(&sc->sc_sessions[session], sizeof(struct hifn_session)); ++ error = 0; ++ } else { ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ error = EINVAL; ++ } ++ HIFN_UNLOCK(sc); ++ ++ return (error); ++} ++ ++static int ++hifn_process(device_t dev, struct cryptop *crp, int hint) ++{ ++ struct hifn_softc *sc = device_get_softc(dev); ++ struct hifn_command *cmd = NULL; ++ int session, err, ivlen; ++ struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ if (crp == NULL || crp->crp_callback == NULL) { ++ hifnstats.hst_invalid++; ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ return (EINVAL); ++ } ++ session = HIFN_SESSION(crp->crp_sid); ++ ++ if (sc == NULL || session >= sc->sc_nsessions) { ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ err = EINVAL; ++ goto errout; ++ } ++ ++ cmd = kmalloc(sizeof(struct hifn_command), SLAB_ATOMIC); ++ if (cmd == NULL) { ++ hifnstats.hst_nomem++; ++ err = ENOMEM; ++ goto errout; ++ } ++ memset(cmd, 0, sizeof(*cmd)); ++ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ cmd->src_skb = (struct sk_buff *)crp->crp_buf; ++ cmd->dst_skb = (struct sk_buff *)crp->crp_buf; ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ cmd->src_io = (struct uio *)crp->crp_buf; ++ cmd->dst_io = (struct uio *)crp->crp_buf; ++ } else { ++ cmd->src_buf = crp->crp_buf; ++ cmd->dst_buf = crp->crp_buf; ++ } ++ ++ crd1 = crp->crp_desc; ++ if (crd1 == NULL) { ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ err = EINVAL; ++ goto errout; ++ } ++ crd2 = crd1->crd_next; ++ ++ if (crd2 == NULL) { ++ if (crd1->crd_alg == CRYPTO_MD5_HMAC || ++ crd1->crd_alg == CRYPTO_SHA1_HMAC || ++ crd1->crd_alg == CRYPTO_SHA1 || ++ crd1->crd_alg == CRYPTO_MD5) { ++ maccrd = crd1; ++ enccrd = NULL; ++ } else if (crd1->crd_alg == CRYPTO_DES_CBC || ++ crd1->crd_alg == CRYPTO_3DES_CBC || ++ crd1->crd_alg == CRYPTO_AES_CBC || ++ crd1->crd_alg == CRYPTO_ARC4) { ++ if ((crd1->crd_flags & CRD_F_ENCRYPT) == 0) ++ cmd->base_masks |= HIFN_BASE_CMD_DECODE; ++ maccrd = NULL; ++ enccrd = crd1; ++ } else { ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ err = EINVAL; ++ goto errout; ++ } ++ } else { ++ if ((crd1->crd_alg == CRYPTO_MD5_HMAC || ++ crd1->crd_alg == CRYPTO_SHA1_HMAC || ++ crd1->crd_alg == CRYPTO_MD5 || ++ crd1->crd_alg == CRYPTO_SHA1) && ++ (crd2->crd_alg == CRYPTO_DES_CBC || ++ crd2->crd_alg == CRYPTO_3DES_CBC || ++ crd2->crd_alg == CRYPTO_AES_CBC || ++ crd2->crd_alg == CRYPTO_ARC4) && ++ ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { ++ cmd->base_masks = HIFN_BASE_CMD_DECODE; ++ maccrd = crd1; ++ enccrd = crd2; ++ } else if ((crd1->crd_alg == CRYPTO_DES_CBC || ++ crd1->crd_alg == CRYPTO_ARC4 || ++ crd1->crd_alg == CRYPTO_3DES_CBC || ++ crd1->crd_alg == CRYPTO_AES_CBC) && ++ (crd2->crd_alg == CRYPTO_MD5_HMAC || ++ crd2->crd_alg == CRYPTO_SHA1_HMAC || ++ crd2->crd_alg == CRYPTO_MD5 || ++ crd2->crd_alg == CRYPTO_SHA1) && ++ (crd1->crd_flags & CRD_F_ENCRYPT)) { ++ enccrd = crd1; ++ maccrd = crd2; ++ } else { ++ /* ++ * We cannot order the 7751 as requested ++ */ ++ DPRINTF("%s,%d: %s %d,%d,%d - EINVAL\n",__FILE__,__LINE__,__FUNCTION__, crd1->crd_alg, crd2->crd_alg, crd1->crd_flags & CRD_F_ENCRYPT); ++ err = EINVAL; ++ goto errout; ++ } ++ } ++ ++ if (enccrd) { ++ cmd->enccrd = enccrd; ++ cmd->base_masks |= HIFN_BASE_CMD_CRYPT; ++ switch (enccrd->crd_alg) { ++ case CRYPTO_ARC4: ++ cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_RC4; ++ break; ++ case CRYPTO_DES_CBC: ++ cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_DES | ++ HIFN_CRYPT_CMD_MODE_CBC | ++ HIFN_CRYPT_CMD_NEW_IV; ++ break; ++ case CRYPTO_3DES_CBC: ++ cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_3DES | ++ HIFN_CRYPT_CMD_MODE_CBC | ++ HIFN_CRYPT_CMD_NEW_IV; ++ break; ++ case CRYPTO_AES_CBC: ++ cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_AES | ++ HIFN_CRYPT_CMD_MODE_CBC | ++ HIFN_CRYPT_CMD_NEW_IV; ++ break; ++ default: ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ err = EINVAL; ++ goto errout; ++ } ++ if (enccrd->crd_alg != CRYPTO_ARC4) { ++ ivlen = ((enccrd->crd_alg == CRYPTO_AES_CBC) ? ++ HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH); ++ if (enccrd->crd_flags & CRD_F_ENCRYPT) { ++ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) ++ bcopy(enccrd->crd_iv, cmd->iv, ivlen); ++ else ++ read_random(cmd->iv, ivlen); ++ ++ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) ++ == 0) { ++ crypto_copyback(crp->crp_flags, ++ crp->crp_buf, enccrd->crd_inject, ++ ivlen, cmd->iv); ++ } ++ } else { ++ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) ++ bcopy(enccrd->crd_iv, cmd->iv, ivlen); ++ else { ++ crypto_copydata(crp->crp_flags, ++ crp->crp_buf, enccrd->crd_inject, ++ ivlen, cmd->iv); ++ } ++ } ++ } ++ ++ if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) ++ cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY; ++ cmd->ck = enccrd->crd_key; ++ cmd->cklen = enccrd->crd_klen >> 3; ++ cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY; ++ ++ /* ++ * Need to specify the size for the AES key in the masks. ++ */ ++ if ((cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) == ++ HIFN_CRYPT_CMD_ALG_AES) { ++ switch (cmd->cklen) { ++ case 16: ++ cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_128; ++ break; ++ case 24: ++ cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_192; ++ break; ++ case 32: ++ cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_256; ++ break; ++ default: ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ err = EINVAL; ++ goto errout; ++ } ++ } ++ } ++ ++ if (maccrd) { ++ cmd->maccrd = maccrd; ++ cmd->base_masks |= HIFN_BASE_CMD_MAC; ++ ++ switch (maccrd->crd_alg) { ++ case CRYPTO_MD5: ++ cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | ++ HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | ++ HIFN_MAC_CMD_POS_IPSEC; ++ break; ++ case CRYPTO_MD5_HMAC: ++ cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | ++ HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | ++ HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; ++ break; ++ case CRYPTO_SHA1: ++ cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | ++ HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | ++ HIFN_MAC_CMD_POS_IPSEC; ++ break; ++ case CRYPTO_SHA1_HMAC: ++ cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | ++ HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | ++ HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; ++ break; ++ } ++ ++ if (maccrd->crd_alg == CRYPTO_SHA1_HMAC || ++ maccrd->crd_alg == CRYPTO_MD5_HMAC) { ++ cmd->mac_masks |= HIFN_MAC_CMD_NEW_KEY; ++ bcopy(maccrd->crd_key, cmd->mac, maccrd->crd_klen >> 3); ++ bzero(cmd->mac + (maccrd->crd_klen >> 3), ++ HIFN_MAC_KEY_LENGTH - (maccrd->crd_klen >> 3)); ++ } ++ } ++ ++ cmd->crp = crp; ++ cmd->session_num = session; ++ cmd->softc = sc; ++ ++ err = hifn_crypto(sc, cmd, crp, hint); ++ if (!err) { ++ return 0; ++ } else if (err == ERESTART) { ++ /* ++ * There weren't enough resources to dispatch the request ++ * to the part. Notify the caller so they'll requeue this ++ * request and resubmit it again soon. ++ */ ++#ifdef HIFN_DEBUG ++ if (hifn_debug) ++ device_printf(sc->sc_dev, "requeue request\n"); ++#endif ++ kfree(cmd); ++ sc->sc_needwakeup |= CRYPTO_SYMQ; ++ return (err); ++ } ++ ++errout: ++ if (cmd != NULL) ++ kfree(cmd); ++ if (err == EINVAL) ++ hifnstats.hst_invalid++; ++ else ++ hifnstats.hst_nomem++; ++ crp->crp_etype = err; ++ crypto_done(crp); ++ return (err); ++} ++ ++static void ++hifn_abort(struct hifn_softc *sc) ++{ ++ struct hifn_dma *dma = sc->sc_dma; ++ struct hifn_command *cmd; ++ struct cryptop *crp; ++ int i, u; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ i = dma->resk; u = dma->resu; ++ while (u != 0) { ++ cmd = dma->hifn_commands[i]; ++ KASSERT(cmd != NULL, ("hifn_abort: null command slot %u", i)); ++ dma->hifn_commands[i] = NULL; ++ crp = cmd->crp; ++ ++ if ((dma->resr[i].l & htole32(HIFN_D_VALID)) == 0) { ++ /* Salvage what we can. */ ++ u_int8_t *macbuf; ++ ++ if (cmd->base_masks & HIFN_BASE_CMD_MAC) { ++ macbuf = dma->result_bufs[i]; ++ macbuf += 12; ++ } else ++ macbuf = NULL; ++ hifnstats.hst_opackets++; ++ hifn_callback(sc, cmd, macbuf); ++ } else { ++#if 0 ++ if (cmd->src_map == cmd->dst_map) { ++ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, ++ BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); ++ } else { ++ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, ++ BUS_DMASYNC_POSTWRITE); ++ bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, ++ BUS_DMASYNC_POSTREAD); ++ } ++#endif ++ ++ if (cmd->src_skb != cmd->dst_skb) { ++#ifdef NOTYET ++ m_freem(cmd->src_m); ++ crp->crp_buf = (caddr_t)cmd->dst_m; ++#else ++ device_printf(sc->sc_dev, ++ "%s,%d: CRYPTO_F_SKBUF src != dst not implemented\n", ++ __FILE__, __LINE__); ++#endif ++ } ++ ++ /* non-shared buffers cannot be restarted */ ++ if (cmd->src_map != cmd->dst_map) { ++ /* ++ * XXX should be EAGAIN, delayed until ++ * after the reset. ++ */ ++ crp->crp_etype = ENOMEM; ++ pci_unmap_buf(sc, &cmd->dst); ++ } else ++ crp->crp_etype = ENOMEM; ++ ++ pci_unmap_buf(sc, &cmd->src); ++ ++ kfree(cmd); ++ if (crp->crp_etype != EAGAIN) ++ crypto_done(crp); ++ } ++ ++ if (++i == HIFN_D_RES_RSIZE) ++ i = 0; ++ u--; ++ } ++ dma->resk = i; dma->resu = u; ++ ++ hifn_reset_board(sc, 1); ++ hifn_init_dma(sc); ++ hifn_init_pci_registers(sc); ++} ++ ++static void ++hifn_callback(struct hifn_softc *sc, struct hifn_command *cmd, u_int8_t *macbuf) ++{ ++ struct hifn_dma *dma = sc->sc_dma; ++ struct cryptop *crp = cmd->crp; ++ struct cryptodesc *crd; ++ int i, u; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++#if 0 ++ if (cmd->src_map == cmd->dst_map) { ++ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, ++ BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); ++ } else { ++ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, ++ BUS_DMASYNC_POSTWRITE); ++ bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, ++ BUS_DMASYNC_POSTREAD); ++ } ++#endif ++ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ if (cmd->src_skb != cmd->dst_skb) { ++#ifdef NOTYET ++ crp->crp_buf = (caddr_t)cmd->dst_m; ++ totlen = cmd->src_mapsize; ++ for (m = cmd->dst_m; m != NULL; m = m->m_next) { ++ if (totlen < m->m_len) { ++ m->m_len = totlen; ++ totlen = 0; ++ } else ++ totlen -= m->m_len; ++ } ++ cmd->dst_m->m_pkthdr.len = cmd->src_m->m_pkthdr.len; ++ m_freem(cmd->src_m); ++#else ++ device_printf(sc->sc_dev, ++ "%s,%d: CRYPTO_F_SKBUF src != dst not implemented\n", ++ __FILE__, __LINE__); ++#endif ++ } ++ } ++ ++ if (cmd->sloplen != 0) { ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ cmd->src_mapsize - cmd->sloplen, cmd->sloplen, ++ (caddr_t)&dma->slop[cmd->slopidx]); ++ } ++ ++ i = dma->dstk; u = dma->dstu; ++ while (u != 0) { ++ if (i == HIFN_D_DST_RSIZE) ++ i = 0; ++#if 0 ++ bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, ++ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); ++#endif ++ if (dma->dstr[i].l & htole32(HIFN_D_VALID)) { ++#if 0 ++ bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, ++ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ++#endif ++ break; ++ } ++ i++, u--; ++ } ++ dma->dstk = i; dma->dstu = u; ++ ++ hifnstats.hst_obytes += cmd->dst_mapsize; ++ ++ if (macbuf != NULL) { ++ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { ++ int len; ++ ++ if (crd->crd_alg != CRYPTO_MD5 && ++ crd->crd_alg != CRYPTO_SHA1 && ++ crd->crd_alg != CRYPTO_MD5_HMAC && ++ crd->crd_alg != CRYPTO_SHA1_HMAC) { ++ continue; ++ } ++ len = cmd->softc->sc_sessions[cmd->session_num].hs_mlen; ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ crd->crd_inject, len, macbuf); ++ break; ++ } ++ } ++ ++ if (cmd->src_map != cmd->dst_map) ++ pci_unmap_buf(sc, &cmd->dst); ++ pci_unmap_buf(sc, &cmd->src); ++ kfree(cmd); ++ crypto_done(crp); ++} ++ ++/* ++ * 7811 PB3 rev/2 parts lock-up on burst writes to Group 0 ++ * and Group 1 registers; avoid conditions that could create ++ * burst writes by doing a read in between the writes. ++ * ++ * NB: The read we interpose is always to the same register; ++ * we do this because reading from an arbitrary (e.g. last) ++ * register may not always work. ++ */ ++static void ++hifn_write_reg_0(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) ++{ ++ if (sc->sc_flags & HIFN_IS_7811) { ++ if (sc->sc_bar0_lastreg == reg - 4) ++ readl(sc->sc_bar0 + HIFN_0_PUCNFG); ++ sc->sc_bar0_lastreg = reg; ++ } ++ writel(val, sc->sc_bar0 + reg); ++} ++ ++static void ++hifn_write_reg_1(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) ++{ ++ if (sc->sc_flags & HIFN_IS_7811) { ++ if (sc->sc_bar1_lastreg == reg - 4) ++ readl(sc->sc_bar1 + HIFN_1_REVID); ++ sc->sc_bar1_lastreg = reg; ++ } ++ writel(val, sc->sc_bar1 + reg); ++} ++ ++ ++static struct pci_device_id hifn_pci_tbl[] = { ++ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7951, ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, ++ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7955, ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, ++ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7956, ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, ++ { PCI_VENDOR_NETSEC, PCI_PRODUCT_NETSEC_7751, ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, ++ { PCI_VENDOR_INVERTEX, PCI_PRODUCT_INVERTEX_AEON, ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, ++ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7811, ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, ++ /* ++ * Other vendors share this PCI ID as well, such as ++ * http://www.powercrypt.com, and obviously they also ++ * use the same key. ++ */ ++ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7751, ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, ++ { 0, 0, 0, 0, 0, 0, } ++}; ++MODULE_DEVICE_TABLE(pci, hifn_pci_tbl); ++ ++static struct pci_driver hifn_driver = { ++ .name = "hifn", ++ .id_table = hifn_pci_tbl, ++ .probe = hifn_probe, ++ .remove = hifn_remove, ++ /* add PM stuff here one day */ ++}; ++ ++static int __init hifn_init (void) ++{ ++ struct hifn_softc *sc = NULL; ++ int rc; ++ ++ DPRINTF("%s(%p)\n", __FUNCTION__, hifn_init); ++ ++ rc = pci_register_driver(&hifn_driver); ++ pci_register_driver_compat(&hifn_driver, rc); ++ ++ return rc; ++} ++ ++static void __exit hifn_exit (void) ++{ ++ pci_unregister_driver(&hifn_driver); ++} ++ ++module_init(hifn_init); ++module_exit(hifn_exit); ++ ++MODULE_LICENSE("BSD"); ++MODULE_AUTHOR("David McCullough "); ++MODULE_DESCRIPTION("OCF driver for hifn PCI crypto devices"); +diff -Nur linux-3.0.4.orig/crypto/ocf/hifn/hifn7751reg.h linux-3.0.4/crypto/ocf/hifn/hifn7751reg.h +--- linux-3.0.4.orig/crypto/ocf/hifn/hifn7751reg.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/hifn/hifn7751reg.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,540 @@ ++/* $FreeBSD: src/sys/dev/hifn/hifn7751reg.h,v 1.7 2007/03/21 03:42:49 sam Exp $ */ ++/* $OpenBSD: hifn7751reg.h,v 1.35 2002/04/08 17:49:42 jason Exp $ */ ++ ++/*- ++ * Invertex AEON / Hifn 7751 driver ++ * Copyright (c) 1999 Invertex Inc. All rights reserved. ++ * Copyright (c) 1999 Theo de Raadt ++ * Copyright (c) 2000-2001 Network Security Technologies, Inc. ++ * http://www.netsec.net ++ * ++ * Please send any comments, feedback, bug-fixes, or feature requests to ++ * software@invertex.com. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored in part by the Defense Advanced Research Projects ++ * Agency (DARPA) and Air Force Research Laboratory, Air Force ++ * Materiel Command, USAF, under agreement number F30602-01-2-0537. ++ * ++ */ ++#ifndef __HIFN_H__ ++#define __HIFN_H__ ++ ++/* ++ * Some PCI configuration space offset defines. The names were made ++ * identical to the names used by the Linux kernel. ++ */ ++#define HIFN_BAR0 PCIR_BAR(0) /* PUC register map */ ++#define HIFN_BAR1 PCIR_BAR(1) /* DMA register map */ ++#define HIFN_TRDY_TIMEOUT 0x40 ++#define HIFN_RETRY_TIMEOUT 0x41 ++ ++/* ++ * PCI vendor and device identifiers ++ * (the names are preserved from their OpenBSD source). ++ */ ++#define PCI_VENDOR_HIFN 0x13a3 /* Hifn */ ++#define PCI_PRODUCT_HIFN_7751 0x0005 /* 7751 */ ++#define PCI_PRODUCT_HIFN_6500 0x0006 /* 6500 */ ++#define PCI_PRODUCT_HIFN_7811 0x0007 /* 7811 */ ++#define PCI_PRODUCT_HIFN_7855 0x001f /* 7855 */ ++#define PCI_PRODUCT_HIFN_7951 0x0012 /* 7951 */ ++#define PCI_PRODUCT_HIFN_7955 0x0020 /* 7954/7955 */ ++#define PCI_PRODUCT_HIFN_7956 0x001d /* 7956 */ ++ ++#define PCI_VENDOR_INVERTEX 0x14e1 /* Invertex */ ++#define PCI_PRODUCT_INVERTEX_AEON 0x0005 /* AEON */ ++ ++#define PCI_VENDOR_NETSEC 0x1660 /* NetSec */ ++#define PCI_PRODUCT_NETSEC_7751 0x7751 /* 7751 */ ++ ++/* ++ * The values below should multiple of 4 -- and be large enough to handle ++ * any command the driver implements. ++ * ++ * MAX_COMMAND = base command + mac command + encrypt command + ++ * mac-key + rc4-key ++ * MAX_RESULT = base result + mac result + mac + encrypt result ++ * ++ * ++ */ ++#define HIFN_MAX_COMMAND (8 + 8 + 8 + 64 + 260) ++#define HIFN_MAX_RESULT (8 + 4 + 20 + 4) ++ ++/* ++ * hifn_desc_t ++ * ++ * Holds an individual descriptor for any of the rings. ++ */ ++typedef struct hifn_desc { ++ volatile u_int32_t l; /* length and status bits */ ++ volatile u_int32_t p; ++} hifn_desc_t; ++ ++/* ++ * Masks for the "length" field of struct hifn_desc. ++ */ ++#define HIFN_D_LENGTH 0x0000ffff /* length bit mask */ ++#define HIFN_D_MASKDONEIRQ 0x02000000 /* mask the done interrupt */ ++#define HIFN_D_DESTOVER 0x04000000 /* destination overflow */ ++#define HIFN_D_OVER 0x08000000 /* overflow */ ++#define HIFN_D_LAST 0x20000000 /* last descriptor in chain */ ++#define HIFN_D_JUMP 0x40000000 /* jump descriptor */ ++#define HIFN_D_VALID 0x80000000 /* valid bit */ ++ ++ ++/* ++ * Processing Unit Registers (offset from BASEREG0) ++ */ ++#define HIFN_0_PUDATA 0x00 /* Processing Unit Data */ ++#define HIFN_0_PUCTRL 0x04 /* Processing Unit Control */ ++#define HIFN_0_PUISR 0x08 /* Processing Unit Interrupt Status */ ++#define HIFN_0_PUCNFG 0x0c /* Processing Unit Configuration */ ++#define HIFN_0_PUIER 0x10 /* Processing Unit Interrupt Enable */ ++#define HIFN_0_PUSTAT 0x14 /* Processing Unit Status/Chip ID */ ++#define HIFN_0_FIFOSTAT 0x18 /* FIFO Status */ ++#define HIFN_0_FIFOCNFG 0x1c /* FIFO Configuration */ ++#define HIFN_0_PUCTRL2 0x28 /* Processing Unit Control (2nd map) */ ++#define HIFN_0_MUTE1 0x80 ++#define HIFN_0_MUTE2 0x90 ++#define HIFN_0_SPACESIZE 0x100 /* Register space size */ ++ ++/* Processing Unit Control Register (HIFN_0_PUCTRL) */ ++#define HIFN_PUCTRL_CLRSRCFIFO 0x0010 /* clear source fifo */ ++#define HIFN_PUCTRL_STOP 0x0008 /* stop pu */ ++#define HIFN_PUCTRL_LOCKRAM 0x0004 /* lock ram */ ++#define HIFN_PUCTRL_DMAENA 0x0002 /* enable dma */ ++#define HIFN_PUCTRL_RESET 0x0001 /* Reset processing unit */ ++ ++/* Processing Unit Interrupt Status Register (HIFN_0_PUISR) */ ++#define HIFN_PUISR_CMDINVAL 0x8000 /* Invalid command interrupt */ ++#define HIFN_PUISR_DATAERR 0x4000 /* Data error interrupt */ ++#define HIFN_PUISR_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ ++#define HIFN_PUISR_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ ++#define HIFN_PUISR_DSTOVER 0x0200 /* Destination overrun interrupt */ ++#define HIFN_PUISR_SRCCMD 0x0080 /* Source command interrupt */ ++#define HIFN_PUISR_SRCCTX 0x0040 /* Source context interrupt */ ++#define HIFN_PUISR_SRCDATA 0x0020 /* Source data interrupt */ ++#define HIFN_PUISR_DSTDATA 0x0010 /* Destination data interrupt */ ++#define HIFN_PUISR_DSTRESULT 0x0004 /* Destination result interrupt */ ++ ++/* Processing Unit Configuration Register (HIFN_0_PUCNFG) */ ++#define HIFN_PUCNFG_DRAMMASK 0xe000 /* DRAM size mask */ ++#define HIFN_PUCNFG_DSZ_256K 0x0000 /* 256k dram */ ++#define HIFN_PUCNFG_DSZ_512K 0x2000 /* 512k dram */ ++#define HIFN_PUCNFG_DSZ_1M 0x4000 /* 1m dram */ ++#define HIFN_PUCNFG_DSZ_2M 0x6000 /* 2m dram */ ++#define HIFN_PUCNFG_DSZ_4M 0x8000 /* 4m dram */ ++#define HIFN_PUCNFG_DSZ_8M 0xa000 /* 8m dram */ ++#define HIFN_PUNCFG_DSZ_16M 0xc000 /* 16m dram */ ++#define HIFN_PUCNFG_DSZ_32M 0xe000 /* 32m dram */ ++#define HIFN_PUCNFG_DRAMREFRESH 0x1800 /* DRAM refresh rate mask */ ++#define HIFN_PUCNFG_DRFR_512 0x0000 /* 512 divisor of ECLK */ ++#define HIFN_PUCNFG_DRFR_256 0x0800 /* 256 divisor of ECLK */ ++#define HIFN_PUCNFG_DRFR_128 0x1000 /* 128 divisor of ECLK */ ++#define HIFN_PUCNFG_TCALLPHASES 0x0200 /* your guess is as good as mine... */ ++#define HIFN_PUCNFG_TCDRVTOTEM 0x0100 /* your guess is as good as mine... */ ++#define HIFN_PUCNFG_BIGENDIAN 0x0080 /* DMA big endian mode */ ++#define HIFN_PUCNFG_BUS32 0x0040 /* Bus width 32bits */ ++#define HIFN_PUCNFG_BUS16 0x0000 /* Bus width 16 bits */ ++#define HIFN_PUCNFG_CHIPID 0x0020 /* Allow chipid from PUSTAT */ ++#define HIFN_PUCNFG_DRAM 0x0010 /* Context RAM is DRAM */ ++#define HIFN_PUCNFG_SRAM 0x0000 /* Context RAM is SRAM */ ++#define HIFN_PUCNFG_COMPSING 0x0004 /* Enable single compression context */ ++#define HIFN_PUCNFG_ENCCNFG 0x0002 /* Encryption configuration */ ++ ++/* Processing Unit Interrupt Enable Register (HIFN_0_PUIER) */ ++#define HIFN_PUIER_CMDINVAL 0x8000 /* Invalid command interrupt */ ++#define HIFN_PUIER_DATAERR 0x4000 /* Data error interrupt */ ++#define HIFN_PUIER_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ ++#define HIFN_PUIER_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ ++#define HIFN_PUIER_DSTOVER 0x0200 /* Destination overrun interrupt */ ++#define HIFN_PUIER_SRCCMD 0x0080 /* Source command interrupt */ ++#define HIFN_PUIER_SRCCTX 0x0040 /* Source context interrupt */ ++#define HIFN_PUIER_SRCDATA 0x0020 /* Source data interrupt */ ++#define HIFN_PUIER_DSTDATA 0x0010 /* Destination data interrupt */ ++#define HIFN_PUIER_DSTRESULT 0x0004 /* Destination result interrupt */ ++ ++/* Processing Unit Status Register/Chip ID (HIFN_0_PUSTAT) */ ++#define HIFN_PUSTAT_CMDINVAL 0x8000 /* Invalid command interrupt */ ++#define HIFN_PUSTAT_DATAERR 0x4000 /* Data error interrupt */ ++#define HIFN_PUSTAT_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ ++#define HIFN_PUSTAT_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ ++#define HIFN_PUSTAT_DSTOVER 0x0200 /* Destination overrun interrupt */ ++#define HIFN_PUSTAT_SRCCMD 0x0080 /* Source command interrupt */ ++#define HIFN_PUSTAT_SRCCTX 0x0040 /* Source context interrupt */ ++#define HIFN_PUSTAT_SRCDATA 0x0020 /* Source data interrupt */ ++#define HIFN_PUSTAT_DSTDATA 0x0010 /* Destination data interrupt */ ++#define HIFN_PUSTAT_DSTRESULT 0x0004 /* Destination result interrupt */ ++#define HIFN_PUSTAT_CHIPREV 0x00ff /* Chip revision mask */ ++#define HIFN_PUSTAT_CHIPENA 0xff00 /* Chip enabled mask */ ++#define HIFN_PUSTAT_ENA_2 0x1100 /* Level 2 enabled */ ++#define HIFN_PUSTAT_ENA_1 0x1000 /* Level 1 enabled */ ++#define HIFN_PUSTAT_ENA_0 0x3000 /* Level 0 enabled */ ++#define HIFN_PUSTAT_REV_2 0x0020 /* 7751 PT6/2 */ ++#define HIFN_PUSTAT_REV_3 0x0030 /* 7751 PT6/3 */ ++ ++/* FIFO Status Register (HIFN_0_FIFOSTAT) */ ++#define HIFN_FIFOSTAT_SRC 0x7f00 /* Source FIFO available */ ++#define HIFN_FIFOSTAT_DST 0x007f /* Destination FIFO available */ ++ ++/* FIFO Configuration Register (HIFN_0_FIFOCNFG) */ ++#define HIFN_FIFOCNFG_THRESHOLD 0x0400 /* must be written as this value */ ++ ++/* ++ * DMA Interface Registers (offset from BASEREG1) ++ */ ++#define HIFN_1_DMA_CRAR 0x0c /* DMA Command Ring Address */ ++#define HIFN_1_DMA_SRAR 0x1c /* DMA Source Ring Address */ ++#define HIFN_1_DMA_RRAR 0x2c /* DMA Result Ring Address */ ++#define HIFN_1_DMA_DRAR 0x3c /* DMA Destination Ring Address */ ++#define HIFN_1_DMA_CSR 0x40 /* DMA Status and Control */ ++#define HIFN_1_DMA_IER 0x44 /* DMA Interrupt Enable */ ++#define HIFN_1_DMA_CNFG 0x48 /* DMA Configuration */ ++#define HIFN_1_PLL 0x4c /* 7955/7956: PLL config */ ++#define HIFN_1_7811_RNGENA 0x60 /* 7811: rng enable */ ++#define HIFN_1_7811_RNGCFG 0x64 /* 7811: rng config */ ++#define HIFN_1_7811_RNGDAT 0x68 /* 7811: rng data */ ++#define HIFN_1_7811_RNGSTS 0x6c /* 7811: rng status */ ++#define HIFN_1_DMA_CNFG2 0x6c /* 7955/7956: dma config #2 */ ++#define HIFN_1_7811_MIPSRST 0x94 /* 7811: MIPS reset */ ++#define HIFN_1_REVID 0x98 /* Revision ID */ ++ ++#define HIFN_1_PUB_RESET 0x204 /* Public/RNG Reset */ ++#define HIFN_1_PUB_BASE 0x300 /* Public Base Address */ ++#define HIFN_1_PUB_OPLEN 0x304 /* 7951-compat Public Operand Length */ ++#define HIFN_1_PUB_OP 0x308 /* 7951-compat Public Operand */ ++#define HIFN_1_PUB_STATUS 0x30c /* 7951-compat Public Status */ ++#define HIFN_1_PUB_IEN 0x310 /* Public Interrupt enable */ ++#define HIFN_1_RNG_CONFIG 0x314 /* RNG config */ ++#define HIFN_1_RNG_DATA 0x318 /* RNG data */ ++#define HIFN_1_PUB_MODE 0x320 /* PK mode */ ++#define HIFN_1_PUB_FIFO_OPLEN 0x380 /* first element of oplen fifo */ ++#define HIFN_1_PUB_FIFO_OP 0x384 /* first element of op fifo */ ++#define HIFN_1_PUB_MEM 0x400 /* start of Public key memory */ ++#define HIFN_1_PUB_MEMEND 0xbff /* end of Public key memory */ ++ ++/* DMA Status and Control Register (HIFN_1_DMA_CSR) */ ++#define HIFN_DMACSR_D_CTRLMASK 0xc0000000 /* Destinition Ring Control */ ++#define HIFN_DMACSR_D_CTRL_NOP 0x00000000 /* Dest. Control: no-op */ ++#define HIFN_DMACSR_D_CTRL_DIS 0x40000000 /* Dest. Control: disable */ ++#define HIFN_DMACSR_D_CTRL_ENA 0x80000000 /* Dest. Control: enable */ ++#define HIFN_DMACSR_D_ABORT 0x20000000 /* Destinition Ring PCIAbort */ ++#define HIFN_DMACSR_D_DONE 0x10000000 /* Destinition Ring Done */ ++#define HIFN_DMACSR_D_LAST 0x08000000 /* Destinition Ring Last */ ++#define HIFN_DMACSR_D_WAIT 0x04000000 /* Destinition Ring Waiting */ ++#define HIFN_DMACSR_D_OVER 0x02000000 /* Destinition Ring Overflow */ ++#define HIFN_DMACSR_R_CTRL 0x00c00000 /* Result Ring Control */ ++#define HIFN_DMACSR_R_CTRL_NOP 0x00000000 /* Result Control: no-op */ ++#define HIFN_DMACSR_R_CTRL_DIS 0x00400000 /* Result Control: disable */ ++#define HIFN_DMACSR_R_CTRL_ENA 0x00800000 /* Result Control: enable */ ++#define HIFN_DMACSR_R_ABORT 0x00200000 /* Result Ring PCI Abort */ ++#define HIFN_DMACSR_R_DONE 0x00100000 /* Result Ring Done */ ++#define HIFN_DMACSR_R_LAST 0x00080000 /* Result Ring Last */ ++#define HIFN_DMACSR_R_WAIT 0x00040000 /* Result Ring Waiting */ ++#define HIFN_DMACSR_R_OVER 0x00020000 /* Result Ring Overflow */ ++#define HIFN_DMACSR_S_CTRL 0x0000c000 /* Source Ring Control */ ++#define HIFN_DMACSR_S_CTRL_NOP 0x00000000 /* Source Control: no-op */ ++#define HIFN_DMACSR_S_CTRL_DIS 0x00004000 /* Source Control: disable */ ++#define HIFN_DMACSR_S_CTRL_ENA 0x00008000 /* Source Control: enable */ ++#define HIFN_DMACSR_S_ABORT 0x00002000 /* Source Ring PCI Abort */ ++#define HIFN_DMACSR_S_DONE 0x00001000 /* Source Ring Done */ ++#define HIFN_DMACSR_S_LAST 0x00000800 /* Source Ring Last */ ++#define HIFN_DMACSR_S_WAIT 0x00000400 /* Source Ring Waiting */ ++#define HIFN_DMACSR_ILLW 0x00000200 /* Illegal write (7811 only) */ ++#define HIFN_DMACSR_ILLR 0x00000100 /* Illegal read (7811 only) */ ++#define HIFN_DMACSR_C_CTRL 0x000000c0 /* Command Ring Control */ ++#define HIFN_DMACSR_C_CTRL_NOP 0x00000000 /* Command Control: no-op */ ++#define HIFN_DMACSR_C_CTRL_DIS 0x00000040 /* Command Control: disable */ ++#define HIFN_DMACSR_C_CTRL_ENA 0x00000080 /* Command Control: enable */ ++#define HIFN_DMACSR_C_ABORT 0x00000020 /* Command Ring PCI Abort */ ++#define HIFN_DMACSR_C_DONE 0x00000010 /* Command Ring Done */ ++#define HIFN_DMACSR_C_LAST 0x00000008 /* Command Ring Last */ ++#define HIFN_DMACSR_C_WAIT 0x00000004 /* Command Ring Waiting */ ++#define HIFN_DMACSR_PUBDONE 0x00000002 /* Public op done (7951 only) */ ++#define HIFN_DMACSR_ENGINE 0x00000001 /* Command Ring Engine IRQ */ ++ ++/* DMA Interrupt Enable Register (HIFN_1_DMA_IER) */ ++#define HIFN_DMAIER_D_ABORT 0x20000000 /* Destination Ring PCIAbort */ ++#define HIFN_DMAIER_D_DONE 0x10000000 /* Destination Ring Done */ ++#define HIFN_DMAIER_D_LAST 0x08000000 /* Destination Ring Last */ ++#define HIFN_DMAIER_D_WAIT 0x04000000 /* Destination Ring Waiting */ ++#define HIFN_DMAIER_D_OVER 0x02000000 /* Destination Ring Overflow */ ++#define HIFN_DMAIER_R_ABORT 0x00200000 /* Result Ring PCI Abort */ ++#define HIFN_DMAIER_R_DONE 0x00100000 /* Result Ring Done */ ++#define HIFN_DMAIER_R_LAST 0x00080000 /* Result Ring Last */ ++#define HIFN_DMAIER_R_WAIT 0x00040000 /* Result Ring Waiting */ ++#define HIFN_DMAIER_R_OVER 0x00020000 /* Result Ring Overflow */ ++#define HIFN_DMAIER_S_ABORT 0x00002000 /* Source Ring PCI Abort */ ++#define HIFN_DMAIER_S_DONE 0x00001000 /* Source Ring Done */ ++#define HIFN_DMAIER_S_LAST 0x00000800 /* Source Ring Last */ ++#define HIFN_DMAIER_S_WAIT 0x00000400 /* Source Ring Waiting */ ++#define HIFN_DMAIER_ILLW 0x00000200 /* Illegal write (7811 only) */ ++#define HIFN_DMAIER_ILLR 0x00000100 /* Illegal read (7811 only) */ ++#define HIFN_DMAIER_C_ABORT 0x00000020 /* Command Ring PCI Abort */ ++#define HIFN_DMAIER_C_DONE 0x00000010 /* Command Ring Done */ ++#define HIFN_DMAIER_C_LAST 0x00000008 /* Command Ring Last */ ++#define HIFN_DMAIER_C_WAIT 0x00000004 /* Command Ring Waiting */ ++#define HIFN_DMAIER_PUBDONE 0x00000002 /* public op done (7951 only) */ ++#define HIFN_DMAIER_ENGINE 0x00000001 /* Engine IRQ */ ++ ++/* DMA Configuration Register (HIFN_1_DMA_CNFG) */ ++#define HIFN_DMACNFG_BIGENDIAN 0x10000000 /* big endian mode */ ++#define HIFN_DMACNFG_POLLFREQ 0x00ff0000 /* Poll frequency mask */ ++#define HIFN_DMACNFG_UNLOCK 0x00000800 ++#define HIFN_DMACNFG_POLLINVAL 0x00000700 /* Invalid Poll Scalar */ ++#define HIFN_DMACNFG_LAST 0x00000010 /* Host control LAST bit */ ++#define HIFN_DMACNFG_MODE 0x00000004 /* DMA mode */ ++#define HIFN_DMACNFG_DMARESET 0x00000002 /* DMA Reset # */ ++#define HIFN_DMACNFG_MSTRESET 0x00000001 /* Master Reset # */ ++ ++/* DMA Configuration Register (HIFN_1_DMA_CNFG2) */ ++#define HIFN_DMACNFG2_PKSWAP32 (1 << 19) /* swap the OPLEN/OP reg */ ++#define HIFN_DMACNFG2_PKSWAP8 (1 << 18) /* swap the bits of OPLEN/OP */ ++#define HIFN_DMACNFG2_BAR0_SWAP32 (1<<17) /* swap the bytes of BAR0 */ ++#define HIFN_DMACNFG2_BAR1_SWAP8 (1<<16) /* swap the bits of BAR0 */ ++#define HIFN_DMACNFG2_INIT_WRITE_BURST_SHIFT 12 ++#define HIFN_DMACNFG2_INIT_READ_BURST_SHIFT 8 ++#define HIFN_DMACNFG2_TGT_WRITE_BURST_SHIFT 4 ++#define HIFN_DMACNFG2_TGT_READ_BURST_SHIFT 0 ++ ++/* 7811 RNG Enable Register (HIFN_1_7811_RNGENA) */ ++#define HIFN_7811_RNGENA_ENA 0x00000001 /* enable RNG */ ++ ++/* 7811 RNG Config Register (HIFN_1_7811_RNGCFG) */ ++#define HIFN_7811_RNGCFG_PRE1 0x00000f00 /* first prescalar */ ++#define HIFN_7811_RNGCFG_OPRE 0x00000080 /* output prescalar */ ++#define HIFN_7811_RNGCFG_DEFL 0x00000f80 /* 2 words/ 1/100 sec */ ++ ++/* 7811 RNG Status Register (HIFN_1_7811_RNGSTS) */ ++#define HIFN_7811_RNGSTS_RDY 0x00004000 /* two numbers in FIFO */ ++#define HIFN_7811_RNGSTS_UFL 0x00001000 /* rng underflow */ ++ ++/* 7811 MIPS Reset Register (HIFN_1_7811_MIPSRST) */ ++#define HIFN_MIPSRST_BAR2SIZE 0xffff0000 /* sdram size */ ++#define HIFN_MIPSRST_GPRAMINIT 0x00008000 /* gpram can be accessed */ ++#define HIFN_MIPSRST_CRAMINIT 0x00004000 /* ctxram can be accessed */ ++#define HIFN_MIPSRST_LED2 0x00000400 /* external LED2 */ ++#define HIFN_MIPSRST_LED1 0x00000200 /* external LED1 */ ++#define HIFN_MIPSRST_LED0 0x00000100 /* external LED0 */ ++#define HIFN_MIPSRST_MIPSDIS 0x00000004 /* disable MIPS */ ++#define HIFN_MIPSRST_MIPSRST 0x00000002 /* warm reset MIPS */ ++#define HIFN_MIPSRST_MIPSCOLD 0x00000001 /* cold reset MIPS */ ++ ++/* Public key reset register (HIFN_1_PUB_RESET) */ ++#define HIFN_PUBRST_RESET 0x00000001 /* reset public/rng unit */ ++ ++/* Public operation register (HIFN_1_PUB_OP) */ ++#define HIFN_PUBOP_AOFFSET 0x0000003e /* A offset */ ++#define HIFN_PUBOP_BOFFSET 0x00000fc0 /* B offset */ ++#define HIFN_PUBOP_MOFFSET 0x0003f000 /* M offset */ ++#define HIFN_PUBOP_OP_MASK 0x003c0000 /* Opcode: */ ++#define HIFN_PUBOP_OP_NOP 0x00000000 /* NOP */ ++#define HIFN_PUBOP_OP_ADD 0x00040000 /* ADD */ ++#define HIFN_PUBOP_OP_ADDC 0x00080000 /* ADD w/carry */ ++#define HIFN_PUBOP_OP_SUB 0x000c0000 /* SUB */ ++#define HIFN_PUBOP_OP_SUBC 0x00100000 /* SUB w/carry */ ++#define HIFN_PUBOP_OP_MODADD 0x00140000 /* Modular ADD */ ++#define HIFN_PUBOP_OP_MODSUB 0x00180000 /* Modular SUB */ ++#define HIFN_PUBOP_OP_INCA 0x001c0000 /* INC A */ ++#define HIFN_PUBOP_OP_DECA 0x00200000 /* DEC A */ ++#define HIFN_PUBOP_OP_MULT 0x00240000 /* MULT */ ++#define HIFN_PUBOP_OP_MODMULT 0x00280000 /* Modular MULT */ ++#define HIFN_PUBOP_OP_MODRED 0x002c0000 /* Modular Red */ ++#define HIFN_PUBOP_OP_MODEXP 0x00300000 /* Modular Exp */ ++ ++/* Public operand length register (HIFN_1_PUB_OPLEN) */ ++#define HIFN_PUBOPLEN_MODLEN 0x0000007f ++#define HIFN_PUBOPLEN_EXPLEN 0x0003ff80 ++#define HIFN_PUBOPLEN_REDLEN 0x003c0000 ++ ++/* Public status register (HIFN_1_PUB_STATUS) */ ++#define HIFN_PUBSTS_DONE 0x00000001 /* operation done */ ++#define HIFN_PUBSTS_CARRY 0x00000002 /* carry */ ++#define HIFN_PUBSTS_FIFO_EMPTY 0x00000100 /* fifo empty */ ++#define HIFN_PUBSTS_FIFO_FULL 0x00000200 /* fifo full */ ++#define HIFN_PUBSTS_FIFO_OVFL 0x00000400 /* fifo overflow */ ++#define HIFN_PUBSTS_FIFO_WRITE 0x000f0000 /* fifo write */ ++#define HIFN_PUBSTS_FIFO_READ 0x0f000000 /* fifo read */ ++ ++/* Public interrupt enable register (HIFN_1_PUB_IEN) */ ++#define HIFN_PUBIEN_DONE 0x00000001 /* operation done interrupt */ ++ ++/* Random number generator config register (HIFN_1_RNG_CONFIG) */ ++#define HIFN_RNGCFG_ENA 0x00000001 /* enable rng */ ++ ++/* ++ * Register offsets in register set 1 ++ */ ++ ++#define HIFN_UNLOCK_SECRET1 0xf4 ++#define HIFN_UNLOCK_SECRET2 0xfc ++ ++/* ++ * PLL config register ++ * ++ * This register is present only on 7954/7955/7956 parts. It must be ++ * programmed according to the bus interface method used by the h/w. ++ * Note that the parts require a stable clock. Since the PCI clock ++ * may vary the reference clock must usually be used. To avoid ++ * overclocking the core logic, setup must be done carefully, refer ++ * to the driver for details. The exact multiplier required varies ++ * by part and system configuration; refer to the Hifn documentation. ++ */ ++#define HIFN_PLL_REF_SEL 0x00000001 /* REF/HBI clk selection */ ++#define HIFN_PLL_BP 0x00000002 /* bypass (used during setup) */ ++/* bit 2 reserved */ ++#define HIFN_PLL_PK_CLK_SEL 0x00000008 /* public key clk select */ ++#define HIFN_PLL_PE_CLK_SEL 0x00000010 /* packet engine clk select */ ++/* bits 5-9 reserved */ ++#define HIFN_PLL_MBSET 0x00000400 /* must be set to 1 */ ++#define HIFN_PLL_ND 0x00003800 /* Fpll_ref multiplier select */ ++#define HIFN_PLL_ND_SHIFT 11 ++#define HIFN_PLL_ND_2 0x00000000 /* 2x */ ++#define HIFN_PLL_ND_4 0x00000800 /* 4x */ ++#define HIFN_PLL_ND_6 0x00001000 /* 6x */ ++#define HIFN_PLL_ND_8 0x00001800 /* 8x */ ++#define HIFN_PLL_ND_10 0x00002000 /* 10x */ ++#define HIFN_PLL_ND_12 0x00002800 /* 12x */ ++/* bits 14-15 reserved */ ++#define HIFN_PLL_IS 0x00010000 /* charge pump current select */ ++/* bits 17-31 reserved */ ++ ++/* ++ * Board configuration specifies only these bits. ++ */ ++#define HIFN_PLL_CONFIG (HIFN_PLL_IS|HIFN_PLL_ND|HIFN_PLL_REF_SEL) ++ ++/* ++ * Public Key Engine Mode Register ++ */ ++#define HIFN_PKMODE_HOSTINVERT (1 << 0) /* HOST INVERT */ ++#define HIFN_PKMODE_ENHANCED (1 << 1) /* Enable enhanced mode */ ++ ++ ++/********************************************************************* ++ * Structs for board commands ++ * ++ *********************************************************************/ ++ ++/* ++ * Structure to help build up the command data structure. ++ */ ++typedef struct hifn_base_command { ++ volatile u_int16_t masks; ++ volatile u_int16_t session_num; ++ volatile u_int16_t total_source_count; ++ volatile u_int16_t total_dest_count; ++} hifn_base_command_t; ++ ++#define HIFN_BASE_CMD_MAC 0x0400 ++#define HIFN_BASE_CMD_CRYPT 0x0800 ++#define HIFN_BASE_CMD_DECODE 0x2000 ++#define HIFN_BASE_CMD_SRCLEN_M 0xc000 ++#define HIFN_BASE_CMD_SRCLEN_S 14 ++#define HIFN_BASE_CMD_DSTLEN_M 0x3000 ++#define HIFN_BASE_CMD_DSTLEN_S 12 ++#define HIFN_BASE_CMD_LENMASK_HI 0x30000 ++#define HIFN_BASE_CMD_LENMASK_LO 0x0ffff ++ ++/* ++ * Structure to help build up the command data structure. ++ */ ++typedef struct hifn_crypt_command { ++ volatile u_int16_t masks; ++ volatile u_int16_t header_skip; ++ volatile u_int16_t source_count; ++ volatile u_int16_t reserved; ++} hifn_crypt_command_t; ++ ++#define HIFN_CRYPT_CMD_ALG_MASK 0x0003 /* algorithm: */ ++#define HIFN_CRYPT_CMD_ALG_DES 0x0000 /* DES */ ++#define HIFN_CRYPT_CMD_ALG_3DES 0x0001 /* 3DES */ ++#define HIFN_CRYPT_CMD_ALG_RC4 0x0002 /* RC4 */ ++#define HIFN_CRYPT_CMD_ALG_AES 0x0003 /* AES */ ++#define HIFN_CRYPT_CMD_MODE_MASK 0x0018 /* Encrypt mode: */ ++#define HIFN_CRYPT_CMD_MODE_ECB 0x0000 /* ECB */ ++#define HIFN_CRYPT_CMD_MODE_CBC 0x0008 /* CBC */ ++#define HIFN_CRYPT_CMD_MODE_CFB 0x0010 /* CFB */ ++#define HIFN_CRYPT_CMD_MODE_OFB 0x0018 /* OFB */ ++#define HIFN_CRYPT_CMD_CLR_CTX 0x0040 /* clear context */ ++#define HIFN_CRYPT_CMD_NEW_KEY 0x0800 /* expect new key */ ++#define HIFN_CRYPT_CMD_NEW_IV 0x1000 /* expect new iv */ ++ ++#define HIFN_CRYPT_CMD_SRCLEN_M 0xc000 ++#define HIFN_CRYPT_CMD_SRCLEN_S 14 ++ ++#define HIFN_CRYPT_CMD_KSZ_MASK 0x0600 /* AES key size: */ ++#define HIFN_CRYPT_CMD_KSZ_128 0x0000 /* 128 bit */ ++#define HIFN_CRYPT_CMD_KSZ_192 0x0200 /* 192 bit */ ++#define HIFN_CRYPT_CMD_KSZ_256 0x0400 /* 256 bit */ ++ ++/* ++ * Structure to help build up the command data structure. ++ */ ++typedef struct hifn_mac_command { ++ volatile u_int16_t masks; ++ volatile u_int16_t header_skip; ++ volatile u_int16_t source_count; ++ volatile u_int16_t reserved; ++} hifn_mac_command_t; ++ ++#define HIFN_MAC_CMD_ALG_MASK 0x0001 ++#define HIFN_MAC_CMD_ALG_SHA1 0x0000 ++#define HIFN_MAC_CMD_ALG_MD5 0x0001 ++#define HIFN_MAC_CMD_MODE_MASK 0x000c ++#define HIFN_MAC_CMD_MODE_HMAC 0x0000 ++#define HIFN_MAC_CMD_MODE_SSL_MAC 0x0004 ++#define HIFN_MAC_CMD_MODE_HASH 0x0008 ++#define HIFN_MAC_CMD_MODE_FULL 0x0004 ++#define HIFN_MAC_CMD_TRUNC 0x0010 ++#define HIFN_MAC_CMD_RESULT 0x0020 ++#define HIFN_MAC_CMD_APPEND 0x0040 ++#define HIFN_MAC_CMD_SRCLEN_M 0xc000 ++#define HIFN_MAC_CMD_SRCLEN_S 14 ++ ++/* ++ * MAC POS IPsec initiates authentication after encryption on encodes ++ * and before decryption on decodes. ++ */ ++#define HIFN_MAC_CMD_POS_IPSEC 0x0200 ++#define HIFN_MAC_CMD_NEW_KEY 0x0800 ++ ++/* ++ * The poll frequency and poll scalar defines are unshifted values used ++ * to set fields in the DMA Configuration Register. ++ */ ++#ifndef HIFN_POLL_FREQUENCY ++#define HIFN_POLL_FREQUENCY 0x1 ++#endif ++ ++#ifndef HIFN_POLL_SCALAR ++#define HIFN_POLL_SCALAR 0x0 ++#endif ++ ++#define HIFN_MAX_SEGLEN 0xffff /* maximum dma segment len */ ++#define HIFN_MAX_DMALEN 0x3ffff /* maximum dma length */ ++#endif /* __HIFN_H__ */ +diff -Nur linux-3.0.4.orig/crypto/ocf/hifn/hifn7751var.h linux-3.0.4/crypto/ocf/hifn/hifn7751var.h +--- linux-3.0.4.orig/crypto/ocf/hifn/hifn7751var.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/hifn/hifn7751var.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,368 @@ ++/* $FreeBSD: src/sys/dev/hifn/hifn7751var.h,v 1.9 2007/03/21 03:42:49 sam Exp $ */ ++/* $OpenBSD: hifn7751var.h,v 1.42 2002/04/08 17:49:42 jason Exp $ */ ++ ++/*- ++ * Invertex AEON / Hifn 7751 driver ++ * Copyright (c) 1999 Invertex Inc. All rights reserved. ++ * Copyright (c) 1999 Theo de Raadt ++ * Copyright (c) 2000-2001 Network Security Technologies, Inc. ++ * http://www.netsec.net ++ * ++ * Please send any comments, feedback, bug-fixes, or feature requests to ++ * software@invertex.com. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored in part by the Defense Advanced Research Projects ++ * Agency (DARPA) and Air Force Research Laboratory, Air Force ++ * Materiel Command, USAF, under agreement number F30602-01-2-0537. ++ * ++ */ ++ ++#ifndef __HIFN7751VAR_H__ ++#define __HIFN7751VAR_H__ ++ ++#ifdef __KERNEL__ ++ ++/* ++ * Some configurable values for the driver. By default command+result ++ * descriptor rings are the same size. The src+dst descriptor rings ++ * are sized at 3.5x the number of potential commands. Slower parts ++ * (e.g. 7951) tend to run out of src descriptors; faster parts (7811) ++ * src+cmd/result descriptors. It's not clear that increasing the size ++ * of the descriptor rings helps performance significantly as other ++ * factors tend to come into play (e.g. copying misaligned packets). ++ */ ++#define HIFN_D_CMD_RSIZE 24 /* command descriptors */ ++#define HIFN_D_SRC_RSIZE ((HIFN_D_CMD_RSIZE * 7) / 2) /* source descriptors */ ++#define HIFN_D_RES_RSIZE HIFN_D_CMD_RSIZE /* result descriptors */ ++#define HIFN_D_DST_RSIZE HIFN_D_SRC_RSIZE /* destination descriptors */ ++ ++/* ++ * Length values for cryptography ++ */ ++#define HIFN_DES_KEY_LENGTH 8 ++#define HIFN_3DES_KEY_LENGTH 24 ++#define HIFN_MAX_CRYPT_KEY_LENGTH HIFN_3DES_KEY_LENGTH ++#define HIFN_IV_LENGTH 8 ++#define HIFN_AES_IV_LENGTH 16 ++#define HIFN_MAX_IV_LENGTH HIFN_AES_IV_LENGTH ++ ++/* ++ * Length values for authentication ++ */ ++#define HIFN_MAC_KEY_LENGTH 64 ++#define HIFN_MD5_LENGTH 16 ++#define HIFN_SHA1_LENGTH 20 ++#define HIFN_MAC_TRUNC_LENGTH 12 ++ ++#define MAX_SCATTER 64 ++ ++/* ++ * Data structure to hold all 4 rings and any other ring related data. ++ */ ++struct hifn_dma { ++ /* ++ * Descriptor rings. We add +1 to the size to accomidate the ++ * jump descriptor. ++ */ ++ struct hifn_desc cmdr[HIFN_D_CMD_RSIZE+1]; ++ struct hifn_desc srcr[HIFN_D_SRC_RSIZE+1]; ++ struct hifn_desc dstr[HIFN_D_DST_RSIZE+1]; ++ struct hifn_desc resr[HIFN_D_RES_RSIZE+1]; ++ ++ struct hifn_command *hifn_commands[HIFN_D_RES_RSIZE]; ++ ++ u_char command_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_COMMAND]; ++ u_char result_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_RESULT]; ++ u_int32_t slop[HIFN_D_CMD_RSIZE]; ++ ++ u_int64_t test_src, test_dst; ++ ++ /* ++ * Our current positions for insertion and removal from the desriptor ++ * rings. ++ */ ++ int cmdi, srci, dsti, resi; ++ volatile int cmdu, srcu, dstu, resu; ++ int cmdk, srck, dstk, resk; ++}; ++ ++struct hifn_session { ++ int hs_used; ++ int hs_mlen; ++}; ++ ++#define HIFN_RING_SYNC(sc, r, i, f) \ ++ /* DAVIDM bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, (f)) */ ++ ++#define HIFN_CMDR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), cmdr, (i), (f)) ++#define HIFN_RESR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), resr, (i), (f)) ++#define HIFN_SRCR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), srcr, (i), (f)) ++#define HIFN_DSTR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), dstr, (i), (f)) ++ ++#define HIFN_CMD_SYNC(sc, i, f) \ ++ /* DAVIDM bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, (f)) */ ++ ++#define HIFN_RES_SYNC(sc, i, f) \ ++ /* DAVIDM bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, (f)) */ ++ ++typedef int bus_size_t; ++ ++/* ++ * Holds data specific to a single HIFN board. ++ */ ++struct hifn_softc { ++ softc_device_decl sc_dev; ++ ++ struct pci_dev *sc_pcidev; /* PCI device pointer */ ++ spinlock_t sc_mtx; /* per-instance lock */ ++ ++ int sc_num; /* for multiple devs */ ++ ++ ocf_iomem_t sc_bar0; ++ bus_size_t sc_bar0_lastreg;/* bar0 last reg written */ ++ ocf_iomem_t sc_bar1; ++ bus_size_t sc_bar1_lastreg;/* bar1 last reg written */ ++ ++ int sc_irq; ++ ++ u_int32_t sc_dmaier; ++ u_int32_t sc_drammodel; /* 1=dram, 0=sram */ ++ u_int32_t sc_pllconfig; /* 7954/7955/7956 PLL config */ ++ ++ struct hifn_dma *sc_dma; ++ dma_addr_t sc_dma_physaddr;/* physical address of sc_dma */ ++ ++ int sc_dmansegs; ++ int32_t sc_cid; ++ int sc_maxses; ++ int sc_nsessions; ++ struct hifn_session *sc_sessions; ++ int sc_ramsize; ++ int sc_flags; ++#define HIFN_HAS_RNG 0x1 /* includes random number generator */ ++#define HIFN_HAS_PUBLIC 0x2 /* includes public key support */ ++#define HIFN_HAS_AES 0x4 /* includes AES support */ ++#define HIFN_IS_7811 0x8 /* Hifn 7811 part */ ++#define HIFN_IS_7956 0x10 /* Hifn 7956/7955 don't have SDRAM */ ++ ++ struct timer_list sc_tickto; /* for managing DMA */ ++ ++ int sc_rngfirst; ++ int sc_rnghz; /* RNG polling frequency */ ++ ++ int sc_c_busy; /* command ring busy */ ++ int sc_s_busy; /* source data ring busy */ ++ int sc_d_busy; /* destination data ring busy */ ++ int sc_r_busy; /* result ring busy */ ++ int sc_active; /* for initial countdown */ ++ int sc_needwakeup; /* ops q'd wating on resources */ ++ int sc_curbatch; /* # ops submitted w/o int */ ++ int sc_suspended; ++#ifdef HIFN_VULCANDEV ++ struct cdev *sc_pkdev; ++#endif ++}; ++ ++#define HIFN_LOCK(_sc) spin_lock_irqsave(&(_sc)->sc_mtx, l_flags) ++#define HIFN_UNLOCK(_sc) spin_unlock_irqrestore(&(_sc)->sc_mtx, l_flags) ++ ++/* ++ * hifn_command_t ++ * ++ * This is the control structure used to pass commands to hifn_encrypt(). ++ * ++ * flags ++ * ----- ++ * Flags is the bitwise "or" values for command configuration. A single ++ * encrypt direction needs to be set: ++ * ++ * HIFN_ENCODE or HIFN_DECODE ++ * ++ * To use cryptography, a single crypto algorithm must be included: ++ * ++ * HIFN_CRYPT_3DES or HIFN_CRYPT_DES ++ * ++ * To use authentication is used, a single MAC algorithm must be included: ++ * ++ * HIFN_MAC_MD5 or HIFN_MAC_SHA1 ++ * ++ * By default MD5 uses a 16 byte hash and SHA-1 uses a 20 byte hash. ++ * If the value below is set, hash values are truncated or assumed ++ * truncated to 12 bytes: ++ * ++ * HIFN_MAC_TRUNC ++ * ++ * Keys for encryption and authentication can be sent as part of a command, ++ * or the last key value used with a particular session can be retrieved ++ * and used again if either of these flags are not specified. ++ * ++ * HIFN_CRYPT_NEW_KEY, HIFN_MAC_NEW_KEY ++ * ++ * session_num ++ * ----------- ++ * A number between 0 and 2048 (for DRAM models) or a number between ++ * 0 and 768 (for SRAM models). Those who don't want to use session ++ * numbers should leave value at zero and send a new crypt key and/or ++ * new MAC key on every command. If you use session numbers and ++ * don't send a key with a command, the last key sent for that same ++ * session number will be used. ++ * ++ * Warning: Using session numbers and multiboard at the same time ++ * is currently broken. ++ * ++ * mbuf ++ * ---- ++ * Either fill in the mbuf pointer and npa=0 or ++ * fill packp[] and packl[] and set npa to > 0 ++ * ++ * mac_header_skip ++ * --------------- ++ * The number of bytes of the source_buf that are skipped over before ++ * authentication begins. This must be a number between 0 and 2^16-1 ++ * and can be used by IPsec implementers to skip over IP headers. ++ * *** Value ignored if authentication not used *** ++ * ++ * crypt_header_skip ++ * ----------------- ++ * The number of bytes of the source_buf that are skipped over before ++ * the cryptographic operation begins. This must be a number between 0 ++ * and 2^16-1. For IPsec, this number will always be 8 bytes larger ++ * than the auth_header_skip (to skip over the ESP header). ++ * *** Value ignored if cryptography not used *** ++ * ++ */ ++struct hifn_operand { ++ union { ++ struct sk_buff *skb; ++ struct uio *io; ++ unsigned char *buf; ++ } u; ++ void *map; ++ bus_size_t mapsize; ++ int nsegs; ++ struct { ++ dma_addr_t ds_addr; ++ int ds_len; ++ } segs[MAX_SCATTER]; ++}; ++ ++struct hifn_command { ++ u_int16_t session_num; ++ u_int16_t base_masks, cry_masks, mac_masks; ++ u_int8_t iv[HIFN_MAX_IV_LENGTH], *ck, mac[HIFN_MAC_KEY_LENGTH]; ++ int cklen; ++ int sloplen, slopidx; ++ ++ struct hifn_operand src; ++ struct hifn_operand dst; ++ ++ struct hifn_softc *softc; ++ struct cryptop *crp; ++ struct cryptodesc *enccrd, *maccrd; ++}; ++ ++#define src_skb src.u.skb ++#define src_io src.u.io ++#define src_map src.map ++#define src_mapsize src.mapsize ++#define src_segs src.segs ++#define src_nsegs src.nsegs ++#define src_buf src.u.buf ++ ++#define dst_skb dst.u.skb ++#define dst_io dst.u.io ++#define dst_map dst.map ++#define dst_mapsize dst.mapsize ++#define dst_segs dst.segs ++#define dst_nsegs dst.nsegs ++#define dst_buf dst.u.buf ++ ++/* ++ * Return values for hifn_crypto() ++ */ ++#define HIFN_CRYPTO_SUCCESS 0 ++#define HIFN_CRYPTO_BAD_INPUT (-1) ++#define HIFN_CRYPTO_RINGS_FULL (-2) ++ ++/************************************************************************** ++ * ++ * Function: hifn_crypto ++ * ++ * Purpose: Called by external drivers to begin an encryption on the ++ * HIFN board. ++ * ++ * Blocking/Non-blocking Issues ++ * ============================ ++ * The driver cannot block in hifn_crypto (no calls to tsleep) currently. ++ * hifn_crypto() returns HIFN_CRYPTO_RINGS_FULL if there is not enough ++ * room in any of the rings for the request to proceed. ++ * ++ * Return Values ++ * ============= ++ * 0 for success, negative values on error ++ * ++ * Defines for negative error codes are: ++ * ++ * HIFN_CRYPTO_BAD_INPUT : The passed in command had invalid settings. ++ * HIFN_CRYPTO_RINGS_FULL : All DMA rings were full and non-blocking ++ * behaviour was requested. ++ * ++ *************************************************************************/ ++ ++/* ++ * Convert back and forth from 'sid' to 'card' and 'session' ++ */ ++#define HIFN_CARD(sid) (((sid) & 0xf0000000) >> 28) ++#define HIFN_SESSION(sid) ((sid) & 0x000007ff) ++#define HIFN_SID(crd,ses) (((crd) << 28) | ((ses) & 0x7ff)) ++ ++#endif /* _KERNEL */ ++ ++struct hifn_stats { ++ u_int64_t hst_ibytes; ++ u_int64_t hst_obytes; ++ u_int32_t hst_ipackets; ++ u_int32_t hst_opackets; ++ u_int32_t hst_invalid; ++ u_int32_t hst_nomem; /* malloc or one of hst_nomem_* */ ++ u_int32_t hst_abort; ++ u_int32_t hst_noirq; /* IRQ for no reason */ ++ u_int32_t hst_totbatch; /* ops submitted w/o interrupt */ ++ u_int32_t hst_maxbatch; /* max ops submitted together */ ++ u_int32_t hst_unaligned; /* unaligned src caused copy */ ++ /* ++ * The following divides hst_nomem into more specific buckets. ++ */ ++ u_int32_t hst_nomem_map; /* bus_dmamap_create failed */ ++ u_int32_t hst_nomem_load; /* bus_dmamap_load_* failed */ ++ u_int32_t hst_nomem_mbuf; /* MGET* failed */ ++ u_int32_t hst_nomem_mcl; /* MCLGET* failed */ ++ u_int32_t hst_nomem_cr; /* out of command/result descriptor */ ++ u_int32_t hst_nomem_sd; /* out of src/dst descriptors */ ++}; ++ ++#endif /* __HIFN7751VAR_H__ */ +diff -Nur linux-3.0.4.orig/crypto/ocf/hifn/hifnHIPP.c linux-3.0.4/crypto/ocf/hifn/hifnHIPP.c +--- linux-3.0.4.orig/crypto/ocf/hifn/hifnHIPP.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/hifn/hifnHIPP.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,420 @@ ++/*- ++ * Driver for Hifn HIPP-I/II chipset ++ * Copyright (c) 2006 Michael Richardson ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored by Hifn Inc. ++ * ++ */ ++ ++/* ++ * Driver for various Hifn encryption processors. ++ */ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "hifnHIPPreg.h" ++#include "hifnHIPPvar.h" ++ ++#if 1 ++#define DPRINTF(a...) if (hipp_debug) { \ ++ printk("%s: ", sc ? \ ++ device_get_nameunit(sc->sc_dev) : "hifn"); \ ++ printk(a); \ ++ } else ++#else ++#define DPRINTF(a...) ++#endif ++ ++typedef int bus_size_t; ++ ++static inline int ++pci_get_revid(struct pci_dev *dev) ++{ ++ u8 rid = 0; ++ pci_read_config_byte(dev, PCI_REVISION_ID, &rid); ++ return rid; ++} ++ ++#define debug hipp_debug ++int hipp_debug = 0; ++module_param(hipp_debug, int, 0644); ++MODULE_PARM_DESC(hipp_debug, "Enable debug"); ++ ++int hipp_maxbatch = 1; ++module_param(hipp_maxbatch, int, 0644); ++MODULE_PARM_DESC(hipp_maxbatch, "max ops to batch w/o interrupt"); ++ ++static int hipp_probe(struct pci_dev *dev, const struct pci_device_id *ent); ++static void hipp_remove(struct pci_dev *dev); ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) ++static irqreturn_t hipp_intr(int irq, void *arg); ++#else ++static irqreturn_t hipp_intr(int irq, void *arg, struct pt_regs *regs); ++#endif ++ ++static int hipp_num_chips = 0; ++static struct hipp_softc *hipp_chip_idx[HIPP_MAX_CHIPS]; ++ ++static int hipp_newsession(device_t, u_int32_t *, struct cryptoini *); ++static int hipp_freesession(device_t, u_int64_t); ++static int hipp_process(device_t, struct cryptop *, int); ++ ++static device_method_t hipp_methods = { ++ /* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, hipp_newsession), ++ DEVMETHOD(cryptodev_freesession,hipp_freesession), ++ DEVMETHOD(cryptodev_process, hipp_process), ++}; ++ ++static __inline u_int32_t ++READ_REG(struct hipp_softc *sc, unsigned int barno, bus_size_t reg) ++{ ++ u_int32_t v = readl(sc->sc_bar[barno] + reg); ++ //sc->sc_bar0_lastreg = (bus_size_t) -1; ++ return (v); ++} ++static __inline void ++WRITE_REG(struct hipp_softc *sc, unsigned int barno, bus_size_t reg, u_int32_t val) ++{ ++ writel(val, sc->sc_bar[barno] + reg); ++} ++ ++#define READ_REG_0(sc, reg) READ_REG(sc, 0, reg) ++#define WRITE_REG_0(sc, reg, val) WRITE_REG(sc,0, reg, val) ++#define READ_REG_1(sc, reg) READ_REG(sc, 1, reg) ++#define WRITE_REG_1(sc, reg, val) WRITE_REG(sc,1, reg, val) ++ ++static int ++hipp_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) ++{ ++ return EINVAL; ++} ++ ++static int ++hipp_freesession(device_t dev, u_int64_t tid) ++{ ++ return EINVAL; ++} ++ ++static int ++hipp_process(device_t dev, struct cryptop *crp, int hint) ++{ ++ return EINVAL; ++} ++ ++static const char* ++hipp_partname(struct hipp_softc *sc, char buf[128], size_t blen) ++{ ++ char *n = NULL; ++ ++ switch (pci_get_vendor(sc->sc_pcidev)) { ++ case PCI_VENDOR_HIFN: ++ switch (pci_get_device(sc->sc_pcidev)) { ++ case PCI_PRODUCT_HIFN_7855: n = "Hifn 7855"; ++ case PCI_PRODUCT_HIFN_8155: n = "Hifn 8155"; ++ case PCI_PRODUCT_HIFN_6500: n = "Hifn 6500"; ++ } ++ } ++ ++ if(n==NULL) { ++ snprintf(buf, blen, "VID=%02x,PID=%02x", ++ pci_get_vendor(sc->sc_pcidev), ++ pci_get_device(sc->sc_pcidev)); ++ } else { ++ buf[0]='\0'; ++ strncat(buf, n, blen); ++ } ++ return buf; ++} ++ ++struct hipp_fs_entry { ++ struct attribute attr; ++ /* other stuff */ ++}; ++ ++ ++static ssize_t ++cryptoid_show(struct device *dev, ++ struct device_attribute *attr, ++ char *buf) ++{ ++ struct hipp_softc *sc; ++ ++ sc = pci_get_drvdata(to_pci_dev (dev)); ++ return sprintf (buf, "%d\n", sc->sc_cid); ++} ++ ++struct device_attribute hipp_dev_cryptoid = __ATTR_RO(cryptoid); ++ ++/* ++ * Attach an interface that successfully probed. ++ */ ++static int ++hipp_probe(struct pci_dev *dev, const struct pci_device_id *ent) ++{ ++ struct hipp_softc *sc = NULL; ++ int i; ++ //char rbase; ++ //u_int16_t ena; ++ int rev; ++ //int rseg; ++ int rc; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ if (pci_enable_device(dev) < 0) ++ return(-ENODEV); ++ ++ if (pci_set_mwi(dev)) ++ return(-ENODEV); ++ ++ if (!dev->irq) { ++ printk("hifn: found device with no IRQ assigned. check BIOS settings!"); ++ pci_disable_device(dev); ++ return(-ENODEV); ++ } ++ ++ sc = (struct hipp_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); ++ if (!sc) ++ return(-ENOMEM); ++ memset(sc, 0, sizeof(*sc)); ++ ++ softc_device_init(sc, "hifn-hipp", hipp_num_chips, hipp_methods); ++ ++ sc->sc_pcidev = dev; ++ sc->sc_irq = -1; ++ sc->sc_cid = -1; ++ sc->sc_num = hipp_num_chips++; ++ ++ if (sc->sc_num < HIPP_MAX_CHIPS) ++ hipp_chip_idx[sc->sc_num] = sc; ++ ++ pci_set_drvdata(sc->sc_pcidev, sc); ++ ++ spin_lock_init(&sc->sc_mtx); ++ ++ /* ++ * Setup PCI resources. ++ * The READ_REG_0, WRITE_REG_0, READ_REG_1, ++ * and WRITE_REG_1 macros throughout the driver are used ++ * to permit better debugging. ++ */ ++ for(i=0; i<4; i++) { ++ unsigned long mem_start, mem_len; ++ mem_start = pci_resource_start(sc->sc_pcidev, i); ++ mem_len = pci_resource_len(sc->sc_pcidev, i); ++ sc->sc_barphy[i] = (caddr_t)mem_start; ++ sc->sc_bar[i] = (ocf_iomem_t) ioremap(mem_start, mem_len); ++ if (!sc->sc_bar[i]) { ++ device_printf(sc->sc_dev, "cannot map bar%d register space\n", i); ++ goto fail; ++ } ++ } ++ ++ //hipp_reset_board(sc, 0); ++ pci_set_master(sc->sc_pcidev); ++ ++ /* ++ * Arrange the interrupt line. ++ */ ++ rc = request_irq(dev->irq, hipp_intr, IRQF_SHARED, "hifn", sc); ++ if (rc) { ++ device_printf(sc->sc_dev, "could not map interrupt: %d\n", rc); ++ goto fail; ++ } ++ sc->sc_irq = dev->irq; ++ ++ rev = READ_REG_1(sc, HIPP_1_REVID) & 0xffff; ++ ++ { ++ char b[32]; ++ device_printf(sc->sc_dev, "%s, rev %u", ++ hipp_partname(sc, b, sizeof(b)), rev); ++ } ++ ++#if 0 ++ if (sc->sc_flags & HIFN_IS_7956) ++ printf(", pll=0x%x<%s clk, %ux mult>", ++ sc->sc_pllconfig, ++ sc->sc_pllconfig & HIFN_PLL_REF_SEL ? "ext" : "pci", ++ 2 + 2*((sc->sc_pllconfig & HIFN_PLL_ND) >> 11)); ++#endif ++ printf("\n"); ++ ++ sc->sc_cid = crypto_get_driverid(softc_get_device(sc),CRYPTOCAP_F_HARDWARE); ++ if (sc->sc_cid < 0) { ++ device_printf(sc->sc_dev, "could not get crypto driver id\n"); ++ goto fail; ++ } ++ ++#if 0 /* cannot work with a non-GPL module */ ++ /* make a sysfs entry to let the world know what entry we got */ ++ sysfs_create_file(&sc->sc_pcidev->dev.kobj, &hipp_dev_cryptoid.attr); ++#endif ++ ++#if 0 ++ init_timer(&sc->sc_tickto); ++ sc->sc_tickto.function = hifn_tick; ++ sc->sc_tickto.data = (unsigned long) sc->sc_num; ++ mod_timer(&sc->sc_tickto, jiffies + HZ); ++#endif ++ ++#if 0 /* no code here yet ?? */ ++ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); ++#endif ++ ++ return (0); ++ ++fail: ++ if (sc->sc_cid >= 0) ++ crypto_unregister_all(sc->sc_cid); ++ if (sc->sc_irq != -1) ++ free_irq(sc->sc_irq, sc); ++ ++#if 0 ++ if (sc->sc_dma) { ++ /* Turn off DMA polling */ ++ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | ++ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); ++ ++ pci_free_consistent(sc->sc_pcidev, ++ sizeof(*sc->sc_dma), ++ sc->sc_dma, sc->sc_dma_physaddr); ++ } ++#endif ++ kfree(sc); ++ return (-ENXIO); ++} ++ ++/* ++ * Detach an interface that successfully probed. ++ */ ++static void ++hipp_remove(struct pci_dev *dev) ++{ ++ struct hipp_softc *sc = pci_get_drvdata(dev); ++ unsigned long l_flags; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ /* disable interrupts */ ++ HIPP_LOCK(sc); ++ ++#if 0 ++ WRITE_REG_1(sc, HIFN_1_DMA_IER, 0); ++ HIFN_UNLOCK(sc); ++ ++ /*XXX other resources */ ++ del_timer_sync(&sc->sc_tickto); ++ ++ /* Turn off DMA polling */ ++ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | ++ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); ++#endif ++ ++ crypto_unregister_all(sc->sc_cid); ++ ++ free_irq(sc->sc_irq, sc); ++ ++#if 0 ++ pci_free_consistent(sc->sc_pcidev, sizeof(*sc->sc_dma), ++ sc->sc_dma, sc->sc_dma_physaddr); ++#endif ++} ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) ++static irqreturn_t hipp_intr(int irq, void *arg) ++#else ++static irqreturn_t hipp_intr(int irq, void *arg, struct pt_regs *regs) ++#endif ++{ ++ struct hipp_softc *sc = arg; ++ ++ sc = sc; /* shut up compiler */ ++ ++ return IRQ_HANDLED; ++} ++ ++static struct pci_device_id hipp_pci_tbl[] = { ++ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7855, ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, ++ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_8155, ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, ++}; ++MODULE_DEVICE_TABLE(pci, hipp_pci_tbl); ++ ++static struct pci_driver hipp_driver = { ++ .name = "hipp", ++ .id_table = hipp_pci_tbl, ++ .probe = hipp_probe, ++ .remove = hipp_remove, ++ /* add PM stuff here one day */ ++}; ++ ++static int __init hipp_init (void) ++{ ++ struct hipp_softc *sc = NULL; ++ int rc; ++ ++ DPRINTF("%s(%p)\n", __FUNCTION__, hipp_init); ++ ++ rc = pci_register_driver(&hipp_driver); ++ pci_register_driver_compat(&hipp_driver, rc); ++ ++ return rc; ++} ++ ++static void __exit hipp_exit (void) ++{ ++ pci_unregister_driver(&hipp_driver); ++} ++ ++module_init(hipp_init); ++module_exit(hipp_exit); ++ ++MODULE_LICENSE("BSD"); ++MODULE_AUTHOR("Michael Richardson "); ++MODULE_DESCRIPTION("OCF driver for hifn HIPP-I/II PCI crypto devices"); +diff -Nur linux-3.0.4.orig/crypto/ocf/hifn/hifnHIPPreg.h linux-3.0.4/crypto/ocf/hifn/hifnHIPPreg.h +--- linux-3.0.4.orig/crypto/ocf/hifn/hifnHIPPreg.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/hifn/hifnHIPPreg.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,46 @@ ++/*- ++ * Hifn HIPP-I/HIPP-II (7855/8155) driver. ++ * Copyright (c) 2006 Michael Richardson ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored by Hifn inc. ++ * ++ */ ++ ++#ifndef __HIFNHIPP_H__ ++#define __HIFNHIPP_H__ ++ ++/* ++ * PCI vendor and device identifiers ++ */ ++#define PCI_VENDOR_HIFN 0x13a3 /* Hifn */ ++#define PCI_PRODUCT_HIFN_6500 0x0006 /* 6500 */ ++#define PCI_PRODUCT_HIFN_7855 0x001f /* 7855 */ ++#define PCI_PRODUCT_HIFN_8155 0x999 /* XXX 8155 */ ++ ++#define HIPP_1_REVID 0x01 /* BOGUS */ ++ ++#endif /* __HIPP_H__ */ +diff -Nur linux-3.0.4.orig/crypto/ocf/hifn/hifnHIPPvar.h linux-3.0.4/crypto/ocf/hifn/hifnHIPPvar.h +--- linux-3.0.4.orig/crypto/ocf/hifn/hifnHIPPvar.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/hifn/hifnHIPPvar.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,93 @@ ++/* ++ * Hifn HIPP-I/HIPP-II (7855/8155) driver. ++ * Copyright (c) 2006 Michael Richardson * ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored by Hifn inc. ++ * ++ */ ++ ++#ifndef __HIFNHIPPVAR_H__ ++#define __HIFNHIPPVAR_H__ ++ ++#define HIPP_MAX_CHIPS 8 ++ ++/* ++ * Holds data specific to a single Hifn HIPP-I board. ++ */ ++struct hipp_softc { ++ softc_device_decl sc_dev; ++ ++ struct pci_dev *sc_pcidev; /* device backpointer */ ++ ocf_iomem_t sc_bar[5]; ++ caddr_t sc_barphy[5]; /* physical address */ ++ int sc_num; /* for multiple devs */ ++ spinlock_t sc_mtx; /* per-instance lock */ ++ int32_t sc_cid; ++ int sc_irq; ++ ++#if 0 ++ ++ u_int32_t sc_dmaier; ++ u_int32_t sc_drammodel; /* 1=dram, 0=sram */ ++ u_int32_t sc_pllconfig; /* 7954/7955/7956 PLL config */ ++ ++ struct hifn_dma *sc_dma; ++ dma_addr_t sc_dma_physaddr;/* physical address of sc_dma */ ++ ++ int sc_dmansegs; ++ int sc_maxses; ++ int sc_nsessions; ++ struct hifn_session *sc_sessions; ++ int sc_ramsize; ++ int sc_flags; ++#define HIFN_HAS_RNG 0x1 /* includes random number generator */ ++#define HIFN_HAS_PUBLIC 0x2 /* includes public key support */ ++#define HIFN_HAS_AES 0x4 /* includes AES support */ ++#define HIFN_IS_7811 0x8 /* Hifn 7811 part */ ++#define HIFN_IS_7956 0x10 /* Hifn 7956/7955 don't have SDRAM */ ++ ++ struct timer_list sc_tickto; /* for managing DMA */ ++ ++ int sc_rngfirst; ++ int sc_rnghz; /* RNG polling frequency */ ++ ++ int sc_c_busy; /* command ring busy */ ++ int sc_s_busy; /* source data ring busy */ ++ int sc_d_busy; /* destination data ring busy */ ++ int sc_r_busy; /* result ring busy */ ++ int sc_active; /* for initial countdown */ ++ int sc_needwakeup; /* ops q'd wating on resources */ ++ int sc_curbatch; /* # ops submitted w/o int */ ++ int sc_suspended; ++ struct miscdevice sc_miscdev; ++#endif ++}; ++ ++#define HIPP_LOCK(_sc) spin_lock_irqsave(&(_sc)->sc_mtx, l_flags) ++#define HIPP_UNLOCK(_sc) spin_unlock_irqrestore(&(_sc)->sc_mtx, l_flags) ++ ++#endif /* __HIFNHIPPVAR_H__ */ +diff -Nur linux-3.0.4.orig/crypto/ocf/ixp4xx/.#ixp4xx.c.1.46 linux-3.0.4/crypto/ocf/ixp4xx/.#ixp4xx.c.1.46 +--- linux-3.0.4.orig/crypto/ocf/ixp4xx/.#ixp4xx.c.1.46 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/ixp4xx/.#ixp4xx.c.1.46 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,1323 @@ ++/* ++ * An OCF module that uses Intels IXP CryptACC API to do the crypto. ++ * This driver requires the IXP400 Access Library that is available ++ * from Intel in order to operate (or compile). ++ * ++ * Written by David McCullough ++ * Copyright (C) 2006-2007 David McCullough ++ * Copyright (C) 2004-2005 Intel Corporation. ++ * ++ * LICENSE TERMS ++ * ++ * The free distribution and use of this software in both source and binary ++ * form is allowed (with or without changes) provided that: ++ * ++ * 1. distributions of this source code include the above copyright ++ * notice, this list of conditions and the following disclaimer; ++ * ++ * 2. distributions in binary form include the above copyright ++ * notice, this list of conditions and the following disclaimer ++ * in the documentation and/or other associated materials; ++ * ++ * 3. the copyright holder's name is not used to endorse products ++ * built using this software without specific written permission. ++ * ++ * ALTERNATIVELY, provided that this notice is retained in full, this product ++ * may be distributed under the terms of the GNU General Public License (GPL), ++ * in which case the provisions of the GPL apply INSTEAD OF those given above. ++ * ++ * DISCLAIMER ++ * ++ * This software is provided 'as is' with no explicit or implied warranties ++ * in respect of its properties, including, but not limited to, correctness ++ * and/or fitness for purpose. ++ */ ++ ++#ifndef AUTOCONF_INCLUDED ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#ifndef IX_MBUF_PRIV ++#define IX_MBUF_PRIV(x) ((x)->priv) ++#endif ++ ++struct ixp_data; ++ ++struct ixp_q { ++ struct list_head ixp_q_list; ++ struct ixp_data *ixp_q_data; ++ struct cryptop *ixp_q_crp; ++ struct cryptodesc *ixp_q_ccrd; ++ struct cryptodesc *ixp_q_acrd; ++ IX_MBUF ixp_q_mbuf; ++ UINT8 *ixp_hash_dest; /* Location for hash in client buffer */ ++ UINT8 *ixp_hash_src; /* Location of hash in internal buffer */ ++ unsigned char ixp_q_iv_data[IX_CRYPTO_ACC_MAX_CIPHER_IV_LENGTH]; ++ unsigned char *ixp_q_iv; ++}; ++ ++struct ixp_data { ++ int ixp_registered; /* is the context registered */ ++ int ixp_crd_flags; /* detect direction changes */ ++ ++ int ixp_cipher_alg; ++ int ixp_auth_alg; ++ ++ UINT32 ixp_ctx_id; ++ UINT32 ixp_hash_key_id; /* used when hashing */ ++ IxCryptoAccCtx ixp_ctx; ++ IX_MBUF ixp_pri_mbuf; ++ IX_MBUF ixp_sec_mbuf; ++ ++ struct work_struct ixp_pending_work; ++ struct work_struct ixp_registration_work; ++ struct list_head ixp_q; /* unprocessed requests */ ++}; ++ ++#ifdef __ixp46X ++ ++#define MAX_IOP_SIZE 64 /* words */ ++#define MAX_OOP_SIZE 128 ++ ++#define MAX_PARAMS 3 ++ ++struct ixp_pkq { ++ struct list_head pkq_list; ++ struct cryptkop *pkq_krp; ++ ++ IxCryptoAccPkeEauInOperands pkq_op; ++ IxCryptoAccPkeEauOpResult pkq_result; ++ ++ UINT32 pkq_ibuf0[MAX_IOP_SIZE]; ++ UINT32 pkq_ibuf1[MAX_IOP_SIZE]; ++ UINT32 pkq_ibuf2[MAX_IOP_SIZE]; ++ UINT32 pkq_obuf[MAX_OOP_SIZE]; ++}; ++ ++static LIST_HEAD(ixp_pkq); /* current PK wait list */ ++static struct ixp_pkq *ixp_pk_cur; ++static spinlock_t ixp_pkq_lock; ++ ++#endif /* __ixp46X */ ++ ++static int ixp_blocked = 0; ++ ++static int32_t ixp_id = -1; ++static struct ixp_data **ixp_sessions = NULL; ++static u_int32_t ixp_sesnum = 0; ++ ++static int ixp_process(device_t, struct cryptop *, int); ++static int ixp_newsession(device_t, u_int32_t *, struct cryptoini *); ++static int ixp_freesession(device_t, u_int64_t); ++#ifdef __ixp46X ++static int ixp_kprocess(device_t, struct cryptkop *krp, int hint); ++#endif ++ ++static struct kmem_cache *qcache; ++ ++#define debug ixp_debug ++static int ixp_debug = 0; ++module_param(ixp_debug, int, 0644); ++MODULE_PARM_DESC(ixp_debug, "Enable debug"); ++ ++static int ixp_init_crypto = 1; ++module_param(ixp_init_crypto, int, 0444); /* RO after load/boot */ ++MODULE_PARM_DESC(ixp_init_crypto, "Call ixCryptoAccInit (default is 1)"); ++ ++static void ixp_process_pending(void *arg); ++static void ixp_registration(void *arg); ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++static void ixp_process_pending_wq(struct work_struct *work); ++static void ixp_registration_wq(struct work_struct *work); ++#endif ++ ++/* ++ * dummy device structure ++ */ ++ ++static struct { ++ softc_device_decl sc_dev; ++} ixpdev; ++ ++static device_method_t ixp_methods = { ++ /* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, ixp_newsession), ++ DEVMETHOD(cryptodev_freesession,ixp_freesession), ++ DEVMETHOD(cryptodev_process, ixp_process), ++#ifdef __ixp46X ++ DEVMETHOD(cryptodev_kprocess, ixp_kprocess), ++#endif ++}; ++ ++/* ++ * Generate a new software session. ++ */ ++static int ++ixp_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) ++{ ++ struct ixp_data *ixp; ++ u_int32_t i; ++#define AUTH_LEN(cri, def) \ ++ (cri->cri_mlen ? cri->cri_mlen : (def)) ++ ++ dprintk("%s():alg %d\n", __FUNCTION__,cri->cri_alg); ++ if (sid == NULL || cri == NULL) { ++ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ if (ixp_sessions) { ++ for (i = 1; i < ixp_sesnum; i++) ++ if (ixp_sessions[i] == NULL) ++ break; ++ } else ++ i = 1; /* NB: to silence compiler warning */ ++ ++ if (ixp_sessions == NULL || i == ixp_sesnum) { ++ struct ixp_data **ixpd; ++ ++ if (ixp_sessions == NULL) { ++ i = 1; /* We leave ixp_sessions[0] empty */ ++ ixp_sesnum = CRYPTO_SW_SESSIONS; ++ } else ++ ixp_sesnum *= 2; ++ ++ ixpd = kmalloc(ixp_sesnum * sizeof(struct ixp_data *), SLAB_ATOMIC); ++ if (ixpd == NULL) { ++ /* Reset session number */ ++ if (ixp_sesnum == CRYPTO_SW_SESSIONS) ++ ixp_sesnum = 0; ++ else ++ ixp_sesnum /= 2; ++ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ memset(ixpd, 0, ixp_sesnum * sizeof(struct ixp_data *)); ++ ++ /* Copy existing sessions */ ++ if (ixp_sessions) { ++ memcpy(ixpd, ixp_sessions, ++ (ixp_sesnum / 2) * sizeof(struct ixp_data *)); ++ kfree(ixp_sessions); ++ } ++ ++ ixp_sessions = ixpd; ++ } ++ ++ ixp_sessions[i] = (struct ixp_data *) kmalloc(sizeof(struct ixp_data), ++ SLAB_ATOMIC); ++ if (ixp_sessions[i] == NULL) { ++ ixp_freesession(NULL, i); ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ ++ *sid = i; ++ ++ ixp = ixp_sessions[i]; ++ memset(ixp, 0, sizeof(*ixp)); ++ ++ ixp->ixp_cipher_alg = -1; ++ ixp->ixp_auth_alg = -1; ++ ixp->ixp_ctx_id = -1; ++ INIT_LIST_HEAD(&ixp->ixp_q); ++ ++ ixp->ixp_ctx.useDifferentSrcAndDestMbufs = 0; ++ ++ while (cri) { ++ switch (cri->cri_alg) { ++ case CRYPTO_DES_CBC: ++ ixp->ixp_cipher_alg = cri->cri_alg; ++ ixp->ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_DES; ++ ixp->ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; ++ ixp->ixp_ctx.cipherCtx.cipherKeyLen = (cri->cri_klen + 7) / 8; ++ ixp->ixp_ctx.cipherCtx.cipherBlockLen = IX_CRYPTO_ACC_DES_BLOCK_64; ++ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen = ++ IX_CRYPTO_ACC_DES_IV_64; ++ memcpy(ixp->ixp_ctx.cipherCtx.key.cipherKey, ++ cri->cri_key, (cri->cri_klen + 7) / 8); ++ break; ++ ++ case CRYPTO_3DES_CBC: ++ ixp->ixp_cipher_alg = cri->cri_alg; ++ ixp->ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_3DES; ++ ixp->ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; ++ ixp->ixp_ctx.cipherCtx.cipherKeyLen = (cri->cri_klen + 7) / 8; ++ ixp->ixp_ctx.cipherCtx.cipherBlockLen = IX_CRYPTO_ACC_DES_BLOCK_64; ++ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen = ++ IX_CRYPTO_ACC_DES_IV_64; ++ memcpy(ixp->ixp_ctx.cipherCtx.key.cipherKey, ++ cri->cri_key, (cri->cri_klen + 7) / 8); ++ break; ++ ++ case CRYPTO_RIJNDAEL128_CBC: ++ ixp->ixp_cipher_alg = cri->cri_alg; ++ ixp->ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_AES; ++ ixp->ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; ++ ixp->ixp_ctx.cipherCtx.cipherKeyLen = (cri->cri_klen + 7) / 8; ++ ixp->ixp_ctx.cipherCtx.cipherBlockLen = 16; ++ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen = 16; ++ memcpy(ixp->ixp_ctx.cipherCtx.key.cipherKey, ++ cri->cri_key, (cri->cri_klen + 7) / 8); ++ break; ++ ++ case CRYPTO_MD5: ++ case CRYPTO_MD5_HMAC: ++ ixp->ixp_auth_alg = cri->cri_alg; ++ ixp->ixp_ctx.authCtx.authAlgo = IX_CRYPTO_ACC_AUTH_MD5; ++ ixp->ixp_ctx.authCtx.authDigestLen = AUTH_LEN(cri, MD5_HASH_LEN); ++ ixp->ixp_ctx.authCtx.aadLen = 0; ++ /* Only MD5_HMAC needs a key */ ++ if (cri->cri_alg == CRYPTO_MD5_HMAC) { ++ ixp->ixp_ctx.authCtx.authKeyLen = (cri->cri_klen + 7) / 8; ++ if (ixp->ixp_ctx.authCtx.authKeyLen > ++ sizeof(ixp->ixp_ctx.authCtx.key.authKey)) { ++ printk( ++ "ixp4xx: Invalid key length for MD5_HMAC - %d bits\n", ++ cri->cri_klen); ++ ixp_freesession(NULL, i); ++ return EINVAL; ++ } ++ memcpy(ixp->ixp_ctx.authCtx.key.authKey, ++ cri->cri_key, (cri->cri_klen + 7) / 8); ++ } ++ break; ++ ++ case CRYPTO_SHA1: ++ case CRYPTO_SHA1_HMAC: ++ ixp->ixp_auth_alg = cri->cri_alg; ++ ixp->ixp_ctx.authCtx.authAlgo = IX_CRYPTO_ACC_AUTH_SHA1; ++ ixp->ixp_ctx.authCtx.authDigestLen = AUTH_LEN(cri, SHA1_HASH_LEN); ++ ixp->ixp_ctx.authCtx.aadLen = 0; ++ /* Only SHA1_HMAC needs a key */ ++ if (cri->cri_alg == CRYPTO_SHA1_HMAC) { ++ ixp->ixp_ctx.authCtx.authKeyLen = (cri->cri_klen + 7) / 8; ++ if (ixp->ixp_ctx.authCtx.authKeyLen > ++ sizeof(ixp->ixp_ctx.authCtx.key.authKey)) { ++ printk( ++ "ixp4xx: Invalid key length for SHA1_HMAC - %d bits\n", ++ cri->cri_klen); ++ ixp_freesession(NULL, i); ++ return EINVAL; ++ } ++ memcpy(ixp->ixp_ctx.authCtx.key.authKey, ++ cri->cri_key, (cri->cri_klen + 7) / 8); ++ } ++ break; ++ ++ default: ++ printk("ixp: unknown algo 0x%x\n", cri->cri_alg); ++ ixp_freesession(NULL, i); ++ return EINVAL; ++ } ++ cri = cri->cri_next; ++ } ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++ INIT_WORK(&ixp->ixp_pending_work, ixp_process_pending_wq); ++ INIT_WORK(&ixp->ixp_registration_work, ixp_registration_wq); ++#else ++ INIT_WORK(&ixp->ixp_pending_work, ixp_process_pending, ixp); ++ INIT_WORK(&ixp->ixp_registration_work, ixp_registration, ixp); ++#endif ++ ++ return 0; ++} ++ ++ ++/* ++ * Free a session. ++ */ ++static int ++ixp_freesession(device_t dev, u_int64_t tid) ++{ ++ u_int32_t sid = CRYPTO_SESID2LID(tid); ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (sid > ixp_sesnum || ixp_sessions == NULL || ++ ixp_sessions[sid] == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ /* Silently accept and return */ ++ if (sid == 0) ++ return 0; ++ ++ if (ixp_sessions[sid]) { ++ if (ixp_sessions[sid]->ixp_ctx_id != -1) { ++ ixCryptoAccCtxUnregister(ixp_sessions[sid]->ixp_ctx_id); ++ ixp_sessions[sid]->ixp_ctx_id = -1; ++ } ++ ++ flush_scheduled_work(); ++ ++ kfree(ixp_sessions[sid]); ++ } ++ ixp_sessions[sid] = NULL; ++ if (ixp_blocked) { ++ ixp_blocked = 0; ++ crypto_unblock(ixp_id, CRYPTO_SYMQ); ++ } ++ return 0; ++} ++ ++ ++/* ++ * callback for when hash processing is complete ++ */ ++ ++static void ++ixp_hash_perform_cb( ++ UINT32 hash_key_id, ++ IX_MBUF *bufp, ++ IxCryptoAccStatus status) ++{ ++ struct ixp_q *q; ++ ++ dprintk("%s(%u, %p, 0x%x)\n", __FUNCTION__, hash_key_id, bufp, status); ++ ++ if (bufp == NULL) { ++ printk("ixp: NULL buf in %s\n", __FUNCTION__); ++ return; ++ } ++ ++ q = IX_MBUF_PRIV(bufp); ++ if (q == NULL) { ++ printk("ixp: NULL priv in %s\n", __FUNCTION__); ++ return; ++ } ++ ++ if (status == IX_CRYPTO_ACC_STATUS_SUCCESS) { ++ /* On success, need to copy hash back into original client buffer */ ++ memcpy(q->ixp_hash_dest, q->ixp_hash_src, ++ (q->ixp_q_data->ixp_auth_alg == CRYPTO_SHA1) ? ++ SHA1_HASH_LEN : MD5_HASH_LEN); ++ } ++ else { ++ printk("ixp: hash perform failed status=%d\n", status); ++ q->ixp_q_crp->crp_etype = EINVAL; ++ } ++ ++ /* Free internal buffer used for hashing */ ++ kfree(IX_MBUF_MDATA(&q->ixp_q_mbuf)); ++ ++ crypto_done(q->ixp_q_crp); ++ kmem_cache_free(qcache, q); ++} ++ ++/* ++ * setup a request and perform it ++ */ ++static void ++ixp_q_process(struct ixp_q *q) ++{ ++ IxCryptoAccStatus status; ++ struct ixp_data *ixp = q->ixp_q_data; ++ int auth_off = 0; ++ int auth_len = 0; ++ int crypt_off = 0; ++ int crypt_len = 0; ++ int icv_off = 0; ++ char *crypt_func; ++ ++ dprintk("%s(%p)\n", __FUNCTION__, q); ++ ++ if (q->ixp_q_ccrd) { ++ if (q->ixp_q_ccrd->crd_flags & CRD_F_IV_EXPLICIT) { ++ q->ixp_q_iv = q->ixp_q_ccrd->crd_iv; ++ } else { ++ q->ixp_q_iv = q->ixp_q_iv_data; ++ crypto_copydata(q->ixp_q_crp->crp_flags, q->ixp_q_crp->crp_buf, ++ q->ixp_q_ccrd->crd_inject, ++ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen, ++ (caddr_t) q->ixp_q_iv); ++ } ++ ++ if (q->ixp_q_acrd) { ++ auth_off = q->ixp_q_acrd->crd_skip; ++ auth_len = q->ixp_q_acrd->crd_len; ++ icv_off = q->ixp_q_acrd->crd_inject; ++ } ++ ++ crypt_off = q->ixp_q_ccrd->crd_skip; ++ crypt_len = q->ixp_q_ccrd->crd_len; ++ } else { /* if (q->ixp_q_acrd) */ ++ auth_off = q->ixp_q_acrd->crd_skip; ++ auth_len = q->ixp_q_acrd->crd_len; ++ icv_off = q->ixp_q_acrd->crd_inject; ++ } ++ ++ if (q->ixp_q_crp->crp_flags & CRYPTO_F_SKBUF) { ++ struct sk_buff *skb = (struct sk_buff *) q->ixp_q_crp->crp_buf; ++ if (skb_shinfo(skb)->nr_frags) { ++ /* ++ * DAVIDM fix this limitation one day by using ++ * a buffer pool and chaining, it is not currently ++ * needed for current user/kernel space acceleration ++ */ ++ printk("ixp: Cannot handle fragmented skb's yet !\n"); ++ q->ixp_q_crp->crp_etype = ENOENT; ++ goto done; ++ } ++ IX_MBUF_MLEN(&q->ixp_q_mbuf) = ++ IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = skb->len; ++ IX_MBUF_MDATA(&q->ixp_q_mbuf) = skb->data; ++ } else if (q->ixp_q_crp->crp_flags & CRYPTO_F_IOV) { ++ struct uio *uiop = (struct uio *) q->ixp_q_crp->crp_buf; ++ if (uiop->uio_iovcnt != 1) { ++ /* ++ * DAVIDM fix this limitation one day by using ++ * a buffer pool and chaining, it is not currently ++ * needed for current user/kernel space acceleration ++ */ ++ printk("ixp: Cannot handle more than 1 iovec yet !\n"); ++ q->ixp_q_crp->crp_etype = ENOENT; ++ goto done; ++ } ++ IX_MBUF_MLEN(&q->ixp_q_mbuf) = ++ IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = uiop->uio_iov[0].iov_len; ++ IX_MBUF_MDATA(&q->ixp_q_mbuf) = uiop->uio_iov[0].iov_base; ++ } else /* contig buffer */ { ++ IX_MBUF_MLEN(&q->ixp_q_mbuf) = ++ IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = q->ixp_q_crp->crp_ilen; ++ IX_MBUF_MDATA(&q->ixp_q_mbuf) = q->ixp_q_crp->crp_buf; ++ } ++ ++ IX_MBUF_PRIV(&q->ixp_q_mbuf) = q; ++ ++ if (ixp->ixp_auth_alg == CRYPTO_SHA1 || ixp->ixp_auth_alg == CRYPTO_MD5) { ++ /* ++ * For SHA1 and MD5 hash, need to create an internal buffer that is big ++ * enough to hold the original data + the appropriate padding for the ++ * hash algorithm. ++ */ ++ UINT8 *tbuf = NULL; ++ ++ IX_MBUF_MLEN(&q->ixp_q_mbuf) = IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = ++ ((IX_MBUF_MLEN(&q->ixp_q_mbuf) * 8) + 72 + 511) / 8; ++ tbuf = kmalloc(IX_MBUF_MLEN(&q->ixp_q_mbuf), SLAB_ATOMIC); ++ ++ if (IX_MBUF_MDATA(&q->ixp_q_mbuf) == NULL) { ++ printk("ixp: kmalloc(%u, SLAB_ATOMIC) failed\n", ++ IX_MBUF_MLEN(&q->ixp_q_mbuf)); ++ q->ixp_q_crp->crp_etype = ENOMEM; ++ goto done; ++ } ++ memcpy(tbuf, &(IX_MBUF_MDATA(&q->ixp_q_mbuf))[auth_off], auth_len); ++ ++ /* Set location in client buffer to copy hash into */ ++ q->ixp_hash_dest = ++ &(IX_MBUF_MDATA(&q->ixp_q_mbuf))[auth_off + auth_len]; ++ ++ IX_MBUF_MDATA(&q->ixp_q_mbuf) = tbuf; ++ ++ /* Set location in internal buffer for where hash starts */ ++ q->ixp_hash_src = &(IX_MBUF_MDATA(&q->ixp_q_mbuf))[auth_len]; ++ ++ crypt_func = "ixCryptoAccHashPerform"; ++ status = ixCryptoAccHashPerform(ixp->ixp_ctx.authCtx.authAlgo, ++ &q->ixp_q_mbuf, ixp_hash_perform_cb, 0, auth_len, auth_len, ++ &ixp->ixp_hash_key_id); ++ } ++ else { ++ crypt_func = "ixCryptoAccAuthCryptPerform"; ++ status = ixCryptoAccAuthCryptPerform(ixp->ixp_ctx_id, &q->ixp_q_mbuf, ++ NULL, auth_off, auth_len, crypt_off, crypt_len, icv_off, ++ q->ixp_q_iv); ++ } ++ ++ if (IX_CRYPTO_ACC_STATUS_QUEUE_FULL == status) { ++ q->ixp_q_crp->crp_etype = ENOMEM; ++ goto done; ++ } ++ ++ if (IX_CRYPTO_ACC_STATUS_SUCCESS != status) { ++ printk("ixp: %s failed %u\n", crypt_func, status); ++ q->ixp_q_crp->crp_etype = EINVAL; ++ } ++ ++done: ++ crypto_done(q->ixp_q_crp); ++ kmem_cache_free(qcache, q); ++} ++ ++ ++/* ++ * because we cannot process the Q from the Register callback ++ * we do it here on a task Q. ++ */ ++ ++static void ++ixp_process_pending(void *arg) ++{ ++ struct ixp_data *ixp = arg; ++ struct ixp_q *q = NULL; ++ ++ dprintk("%s(%p)\n", __FUNCTION__, arg); ++ ++ if (!ixp) ++ return; ++ ++ while (!list_empty(&ixp->ixp_q)) { ++ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); ++ list_del(&q->ixp_q_list); ++ ixp_q_process(q); ++ } ++} ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++static void ++ixp_process_pending_wq(struct work_struct *work) ++{ ++ struct ixp_data *ixp = container_of(work, struct ixp_data, ++ ixp_pending_work); ++ ixp_process_pending(ixp); ++} ++#endif ++ ++/* ++ * callback for when context registration is complete ++ */ ++ ++static void ++ixp_register_cb(UINT32 ctx_id, IX_MBUF *bufp, IxCryptoAccStatus status) ++{ ++ int i; ++ struct ixp_data *ixp; ++ struct ixp_q *q; ++ ++ dprintk("%s(%d, %p, %d)\n", __FUNCTION__, ctx_id, bufp, status); ++ ++ /* ++ * free any buffer passed in to this routine ++ */ ++ if (bufp) { ++ IX_MBUF_MLEN(bufp) = IX_MBUF_PKT_LEN(bufp) = 0; ++ kfree(IX_MBUF_MDATA(bufp)); ++ IX_MBUF_MDATA(bufp) = NULL; ++ } ++ ++ for (i = 0; i < ixp_sesnum; i++) { ++ ixp = ixp_sessions[i]; ++ if (ixp && ixp->ixp_ctx_id == ctx_id) ++ break; ++ } ++ if (i >= ixp_sesnum) { ++ printk("ixp: invalid context id %d\n", ctx_id); ++ return; ++ } ++ ++ if (IX_CRYPTO_ACC_STATUS_WAIT == status) { ++ /* this is normal to free the first of two buffers */ ++ dprintk("ixp: register not finished yet.\n"); ++ return; ++ } ++ ++ if (IX_CRYPTO_ACC_STATUS_SUCCESS != status) { ++ printk("ixp: register failed 0x%x\n", status); ++ while (!list_empty(&ixp->ixp_q)) { ++ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); ++ list_del(&q->ixp_q_list); ++ q->ixp_q_crp->crp_etype = EINVAL; ++ crypto_done(q->ixp_q_crp); ++ kmem_cache_free(qcache, q); ++ } ++ return; ++ } ++ ++ /* ++ * we are now registered, we cannot start processing the Q here ++ * or we get strange errors with AES (DES/3DES seem to be ok). ++ */ ++ ixp->ixp_registered = 1; ++ schedule_work(&ixp->ixp_pending_work); ++} ++ ++ ++/* ++ * callback for when data processing is complete ++ */ ++ ++static void ++ixp_perform_cb( ++ UINT32 ctx_id, ++ IX_MBUF *sbufp, ++ IX_MBUF *dbufp, ++ IxCryptoAccStatus status) ++{ ++ struct ixp_q *q; ++ ++ dprintk("%s(%d, %p, %p, 0x%x)\n", __FUNCTION__, ctx_id, sbufp, ++ dbufp, status); ++ ++ if (sbufp == NULL) { ++ printk("ixp: NULL sbuf in ixp_perform_cb\n"); ++ return; ++ } ++ ++ q = IX_MBUF_PRIV(sbufp); ++ if (q == NULL) { ++ printk("ixp: NULL priv in ixp_perform_cb\n"); ++ return; ++ } ++ ++ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { ++ printk("ixp: perform failed status=%d\n", status); ++ q->ixp_q_crp->crp_etype = EINVAL; ++ } ++ ++ crypto_done(q->ixp_q_crp); ++ kmem_cache_free(qcache, q); ++} ++ ++ ++/* ++ * registration is not callable at IRQ time, so we defer ++ * to a task queue, this routines completes the registration for us ++ * when the task queue runs ++ * ++ * Unfortunately this means we cannot tell OCF that the driver is blocked, ++ * we do that on the next request. ++ */ ++ ++static void ++ixp_registration(void *arg) ++{ ++ struct ixp_data *ixp = arg; ++ struct ixp_q *q = NULL; ++ IX_MBUF *pri = NULL, *sec = NULL; ++ int status = IX_CRYPTO_ACC_STATUS_SUCCESS; ++ ++ if (!ixp) { ++ printk("ixp: ixp_registration with no arg\n"); ++ return; ++ } ++ ++ if (ixp->ixp_ctx_id != -1) { ++ ixCryptoAccCtxUnregister(ixp->ixp_ctx_id); ++ ixp->ixp_ctx_id = -1; ++ } ++ ++ if (list_empty(&ixp->ixp_q)) { ++ printk("ixp: ixp_registration with no Q\n"); ++ return; ++ } ++ ++ /* ++ * setup the primary and secondary buffers ++ */ ++ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); ++ if (q->ixp_q_acrd) { ++ pri = &ixp->ixp_pri_mbuf; ++ sec = &ixp->ixp_sec_mbuf; ++ IX_MBUF_MLEN(pri) = IX_MBUF_PKT_LEN(pri) = 128; ++ IX_MBUF_MDATA(pri) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); ++ IX_MBUF_MLEN(sec) = IX_MBUF_PKT_LEN(sec) = 128; ++ IX_MBUF_MDATA(sec) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); ++ } ++ ++ /* Only need to register if a crypt op or HMAC op */ ++ if (!(ixp->ixp_auth_alg == CRYPTO_SHA1 || ++ ixp->ixp_auth_alg == CRYPTO_MD5)) { ++ status = ixCryptoAccCtxRegister( ++ &ixp->ixp_ctx, ++ pri, sec, ++ ixp_register_cb, ++ ixp_perform_cb, ++ &ixp->ixp_ctx_id); ++ } ++ else { ++ /* Otherwise we start processing pending q */ ++ schedule_work(&ixp->ixp_pending_work); ++ } ++ ++ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) ++ return; ++ ++ if (IX_CRYPTO_ACC_STATUS_EXCEED_MAX_TUNNELS == status) { ++ printk("ixp: ixCryptoAccCtxRegister failed (out of tunnels)\n"); ++ ixp_blocked = 1; ++ /* perhaps we should return EGAIN on queued ops ? */ ++ return; ++ } ++ ++ printk("ixp: ixCryptoAccCtxRegister failed %d\n", status); ++ ixp->ixp_ctx_id = -1; ++ ++ /* ++ * everything waiting is toasted ++ */ ++ while (!list_empty(&ixp->ixp_q)) { ++ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); ++ list_del(&q->ixp_q_list); ++ q->ixp_q_crp->crp_etype = ENOENT; ++ crypto_done(q->ixp_q_crp); ++ kmem_cache_free(qcache, q); ++ } ++} ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++static void ++ixp_registration_wq(struct work_struct *work) ++{ ++ struct ixp_data *ixp = container_of(work, struct ixp_data, ++ ixp_registration_work); ++ ixp_registration(ixp); ++} ++#endif ++ ++/* ++ * Process a request. ++ */ ++static int ++ixp_process(device_t dev, struct cryptop *crp, int hint) ++{ ++ struct ixp_data *ixp; ++ unsigned int lid; ++ struct ixp_q *q = NULL; ++ int status; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ /* Sanity check */ ++ if (crp == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ crp->crp_etype = 0; ++ ++ if (ixp_blocked) ++ return ERESTART; ++ ++ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ crp->crp_etype = EINVAL; ++ goto done; ++ } ++ ++ /* ++ * find the session we are using ++ */ ++ ++ lid = crp->crp_sid & 0xffffffff; ++ if (lid >= ixp_sesnum || lid == 0 || ixp_sessions == NULL || ++ ixp_sessions[lid] == NULL) { ++ crp->crp_etype = ENOENT; ++ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); ++ goto done; ++ } ++ ixp = ixp_sessions[lid]; ++ ++ /* ++ * setup a new request ready for queuing ++ */ ++ q = kmem_cache_alloc(qcache, SLAB_ATOMIC); ++ if (q == NULL) { ++ dprintk("%s,%d: ENOMEM\n", __FILE__, __LINE__); ++ crp->crp_etype = ENOMEM; ++ goto done; ++ } ++ /* ++ * save some cycles by only zeroing the important bits ++ */ ++ memset(&q->ixp_q_mbuf, 0, sizeof(q->ixp_q_mbuf)); ++ q->ixp_q_ccrd = NULL; ++ q->ixp_q_acrd = NULL; ++ q->ixp_q_crp = crp; ++ q->ixp_q_data = ixp; ++ ++ /* ++ * point the cipher and auth descriptors appropriately ++ * check that we have something to do ++ */ ++ if (crp->crp_desc->crd_alg == ixp->ixp_cipher_alg) ++ q->ixp_q_ccrd = crp->crp_desc; ++ else if (crp->crp_desc->crd_alg == ixp->ixp_auth_alg) ++ q->ixp_q_acrd = crp->crp_desc; ++ else { ++ crp->crp_etype = ENOENT; ++ dprintk("%s,%d: bad desc match: ENOENT\n", __FILE__, __LINE__); ++ goto done; ++ } ++ if (crp->crp_desc->crd_next) { ++ if (crp->crp_desc->crd_next->crd_alg == ixp->ixp_cipher_alg) ++ q->ixp_q_ccrd = crp->crp_desc->crd_next; ++ else if (crp->crp_desc->crd_next->crd_alg == ixp->ixp_auth_alg) ++ q->ixp_q_acrd = crp->crp_desc->crd_next; ++ else { ++ crp->crp_etype = ENOENT; ++ dprintk("%s,%d: bad desc match: ENOENT\n", __FILE__, __LINE__); ++ goto done; ++ } ++ } ++ ++ /* ++ * If there is a direction change for this context then we mark it as ++ * unregistered and re-register is for the new direction. This is not ++ * a very expensive operation and currently only tends to happen when ++ * user-space application are doing benchmarks ++ * ++ * DM - we should be checking for pending requests before unregistering. ++ */ ++ if (q->ixp_q_ccrd && ixp->ixp_registered && ++ ixp->ixp_crd_flags != (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT)) { ++ dprintk("%s - detected direction change on session\n", __FUNCTION__); ++ ixp->ixp_registered = 0; ++ } ++ ++ /* ++ * if we are registered, call straight into the perform code ++ */ ++ if (ixp->ixp_registered) { ++ ixp_q_process(q); ++ return 0; ++ } ++ ++ /* ++ * the only part of the context not set in newsession is the direction ++ * dependent parts ++ */ ++ if (q->ixp_q_ccrd) { ++ ixp->ixp_crd_flags = (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT); ++ if (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT) { ++ ixp->ixp_ctx.operation = q->ixp_q_acrd ? ++ IX_CRYPTO_ACC_OP_ENCRYPT_AUTH : IX_CRYPTO_ACC_OP_ENCRYPT; ++ } else { ++ ixp->ixp_ctx.operation = q->ixp_q_acrd ? ++ IX_CRYPTO_ACC_OP_AUTH_DECRYPT : IX_CRYPTO_ACC_OP_DECRYPT; ++ } ++ } else { ++ /* q->ixp_q_acrd must be set if we are here */ ++ ixp->ixp_ctx.operation = IX_CRYPTO_ACC_OP_AUTH_CALC; ++ } ++ ++ status = list_empty(&ixp->ixp_q); ++ list_add_tail(&q->ixp_q_list, &ixp->ixp_q); ++ if (status) ++ schedule_work(&ixp->ixp_registration_work); ++ return 0; ++ ++done: ++ if (q) ++ kmem_cache_free(qcache, q); ++ crypto_done(crp); ++ return 0; ++} ++ ++ ++#ifdef __ixp46X ++/* ++ * key processing support for the ixp465 ++ */ ++ ++ ++/* ++ * copy a BN (LE) into a buffer (BE) an fill out the op appropriately ++ * assume zeroed and only copy bits that are significant ++ */ ++ ++static int ++ixp_copy_ibuf(struct crparam *p, IxCryptoAccPkeEauOperand *op, UINT32 *buf) ++{ ++ unsigned char *src = (unsigned char *) p->crp_p; ++ unsigned char *dst; ++ int len, bits = p->crp_nbits; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (bits > MAX_IOP_SIZE * sizeof(UINT32) * 8) { ++ dprintk("%s - ibuf too big (%d > %d)\n", __FUNCTION__, ++ bits, MAX_IOP_SIZE * sizeof(UINT32) * 8); ++ return -1; ++ } ++ ++ len = (bits + 31) / 32; /* the number UINT32's needed */ ++ ++ dst = (unsigned char *) &buf[len]; ++ dst--; ++ ++ while (bits > 0) { ++ *dst-- = *src++; ++ bits -= 8; ++ } ++ ++#if 0 /* no need to zero remaining bits as it is done during request alloc */ ++ while (dst > (unsigned char *) buf) ++ *dst-- = '\0'; ++#endif ++ ++ op->pData = buf; ++ op->dataLen = len; ++ return 0; ++} ++ ++/* ++ * copy out the result, be as forgiving as we can about small output buffers ++ */ ++ ++static int ++ixp_copy_obuf(struct crparam *p, IxCryptoAccPkeEauOpResult *op, UINT32 *buf) ++{ ++ unsigned char *dst = (unsigned char *) p->crp_p; ++ unsigned char *src = (unsigned char *) buf; ++ int len, z, bits = p->crp_nbits; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ len = op->dataLen * sizeof(UINT32); ++ ++ /* skip leading zeroes to be small buffer friendly */ ++ z = 0; ++ while (z < len && src[z] == '\0') ++ z++; ++ ++ src += len; ++ src--; ++ len -= z; ++ ++ while (len > 0 && bits > 0) { ++ *dst++ = *src--; ++ len--; ++ bits -= 8; ++ } ++ ++ while (bits > 0) { ++ *dst++ = '\0'; ++ bits -= 8; ++ } ++ ++ if (len > 0) { ++ dprintk("%s - obuf is %d (z=%d, ob=%d) bytes too small\n", ++ __FUNCTION__, len, z, p->crp_nbits / 8); ++ return -1; ++ } ++ ++ return 0; ++} ++ ++ ++/* ++ * the parameter offsets for exp_mod ++ */ ++ ++#define IXP_PARAM_BASE 0 ++#define IXP_PARAM_EXP 1 ++#define IXP_PARAM_MOD 2 ++#define IXP_PARAM_RES 3 ++ ++/* ++ * key processing complete callback, is also used to start processing ++ * by passing a NULL for pResult ++ */ ++ ++static void ++ixp_kperform_cb( ++ IxCryptoAccPkeEauOperation operation, ++ IxCryptoAccPkeEauOpResult *pResult, ++ BOOL carryOrBorrow, ++ IxCryptoAccStatus status) ++{ ++ struct ixp_pkq *q, *tmp; ++ unsigned long flags; ++ ++ dprintk("%s(0x%x, %p, %d, 0x%x)\n", __FUNCTION__, operation, pResult, ++ carryOrBorrow, status); ++ ++ /* handle a completed request */ ++ if (pResult) { ++ if (ixp_pk_cur && &ixp_pk_cur->pkq_result == pResult) { ++ q = ixp_pk_cur; ++ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { ++ dprintk("%s() - op failed 0x%x\n", __FUNCTION__, status); ++ q->pkq_krp->krp_status = ERANGE; /* could do better */ ++ } else { ++ /* copy out the result */ ++ if (ixp_copy_obuf(&q->pkq_krp->krp_param[IXP_PARAM_RES], ++ &q->pkq_result, q->pkq_obuf)) ++ q->pkq_krp->krp_status = ERANGE; ++ } ++ crypto_kdone(q->pkq_krp); ++ kfree(q); ++ ixp_pk_cur = NULL; ++ } else ++ printk("%s - callback with invalid result pointer\n", __FUNCTION__); ++ } ++ ++ spin_lock_irqsave(&ixp_pkq_lock, flags); ++ if (ixp_pk_cur || list_empty(&ixp_pkq)) { ++ spin_unlock_irqrestore(&ixp_pkq_lock, flags); ++ return; ++ } ++ ++ list_for_each_entry_safe(q, tmp, &ixp_pkq, pkq_list) { ++ ++ list_del(&q->pkq_list); ++ ixp_pk_cur = q; ++ ++ spin_unlock_irqrestore(&ixp_pkq_lock, flags); ++ ++ status = ixCryptoAccPkeEauPerform( ++ IX_CRYPTO_ACC_OP_EAU_MOD_EXP, ++ &q->pkq_op, ++ ixp_kperform_cb, ++ &q->pkq_result); ++ ++ if (status == IX_CRYPTO_ACC_STATUS_SUCCESS) { ++ dprintk("%s() - ixCryptoAccPkeEauPerform SUCCESS\n", __FUNCTION__); ++ return; /* callback will return here for callback */ ++ } else if (status == IX_CRYPTO_ACC_STATUS_RETRY) { ++ printk("%s() - ixCryptoAccPkeEauPerform RETRY\n", __FUNCTION__); ++ } else { ++ printk("%s() - ixCryptoAccPkeEauPerform failed %d\n", ++ __FUNCTION__, status); ++ } ++ q->pkq_krp->krp_status = ERANGE; /* could do better */ ++ crypto_kdone(q->pkq_krp); ++ kfree(q); ++ spin_lock_irqsave(&ixp_pkq_lock, flags); ++ } ++ spin_unlock_irqrestore(&ixp_pkq_lock, flags); ++} ++ ++ ++static int ++ixp_kprocess(device_t dev, struct cryptkop *krp, int hint) ++{ ++ struct ixp_pkq *q; ++ int rc = 0; ++ unsigned long flags; ++ ++ dprintk("%s l1=%d l2=%d l3=%d l4=%d\n", __FUNCTION__, ++ krp->krp_param[IXP_PARAM_BASE].crp_nbits, ++ krp->krp_param[IXP_PARAM_EXP].crp_nbits, ++ krp->krp_param[IXP_PARAM_MOD].crp_nbits, ++ krp->krp_param[IXP_PARAM_RES].crp_nbits); ++ ++ ++ if (krp->krp_op != CRK_MOD_EXP) { ++ krp->krp_status = EOPNOTSUPP; ++ goto err; ++ } ++ ++ q = (struct ixp_pkq *) kmalloc(sizeof(*q), GFP_KERNEL); ++ if (q == NULL) { ++ krp->krp_status = ENOMEM; ++ goto err; ++ } ++ ++ /* ++ * The PKE engine does not appear to zero the output buffer ++ * appropriately, so we need to do it all here. ++ */ ++ memset(q, 0, sizeof(*q)); ++ ++ q->pkq_krp = krp; ++ INIT_LIST_HEAD(&q->pkq_list); ++ ++ if (ixp_copy_ibuf(&krp->krp_param[IXP_PARAM_BASE], &q->pkq_op.modExpOpr.M, ++ q->pkq_ibuf0)) ++ rc = 1; ++ if (!rc && ixp_copy_ibuf(&krp->krp_param[IXP_PARAM_EXP], ++ &q->pkq_op.modExpOpr.e, q->pkq_ibuf1)) ++ rc = 2; ++ if (!rc && ixp_copy_ibuf(&krp->krp_param[IXP_PARAM_MOD], ++ &q->pkq_op.modExpOpr.N, q->pkq_ibuf2)) ++ rc = 3; ++ ++ if (rc) { ++ kfree(q); ++ krp->krp_status = ERANGE; ++ goto err; ++ } ++ ++ q->pkq_result.pData = q->pkq_obuf; ++ q->pkq_result.dataLen = ++ (krp->krp_param[IXP_PARAM_RES].crp_nbits + 31) / 32; ++ ++ spin_lock_irqsave(&ixp_pkq_lock, flags); ++ list_add_tail(&q->pkq_list, &ixp_pkq); ++ spin_unlock_irqrestore(&ixp_pkq_lock, flags); ++ ++ if (!ixp_pk_cur) ++ ixp_kperform_cb(0, NULL, 0, 0); ++ return (0); ++ ++err: ++ crypto_kdone(krp); ++ return (0); ++} ++ ++ ++ ++#ifdef CONFIG_OCF_RANDOMHARVEST ++/* ++ * We run the random number generator output through SHA so that it ++ * is FIPS compliant. ++ */ ++ ++static volatile int sha_done = 0; ++static unsigned char sha_digest[20]; ++ ++static void ++ixp_hash_cb(UINT8 *digest, IxCryptoAccStatus status) ++{ ++ dprintk("%s(%p, %d)\n", __FUNCTION__, digest, status); ++ if (sha_digest != digest) ++ printk("digest error\n"); ++ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) ++ sha_done = 1; ++ else ++ sha_done = -status; ++} ++ ++static int ++ixp_read_random(void *arg, u_int32_t *buf, int maxwords) ++{ ++ IxCryptoAccStatus status; ++ int i, n, rc; ++ ++ dprintk("%s(%p, %d)\n", __FUNCTION__, buf, maxwords); ++ memset(buf, 0, maxwords * sizeof(*buf)); ++ status = ixCryptoAccPkePseudoRandomNumberGet(maxwords, buf); ++ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { ++ dprintk("%s: ixCryptoAccPkePseudoRandomNumberGet failed %d\n", ++ __FUNCTION__, status); ++ return 0; ++ } ++ ++ /* ++ * run the random data through SHA to make it look more random ++ */ ++ ++ n = sizeof(sha_digest); /* process digest bytes at a time */ ++ ++ rc = 0; ++ for (i = 0; i < maxwords; i += n / sizeof(*buf)) { ++ if ((maxwords - i) * sizeof(*buf) < n) ++ n = (maxwords - i) * sizeof(*buf); ++ sha_done = 0; ++ status = ixCryptoAccPkeHashPerform(IX_CRYPTO_ACC_AUTH_SHA1, ++ (UINT8 *) &buf[i], n, ixp_hash_cb, sha_digest); ++ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { ++ dprintk("ixCryptoAccPkeHashPerform failed %d\n", status); ++ return -EIO; ++ } ++ while (!sha_done) ++ schedule(); ++ if (sha_done < 0) { ++ dprintk("ixCryptoAccPkeHashPerform failed CB %d\n", -sha_done); ++ return 0; ++ } ++ memcpy(&buf[i], sha_digest, n); ++ rc += n / sizeof(*buf);; ++ } ++ ++ return rc; ++} ++#endif /* CONFIG_OCF_RANDOMHARVEST */ ++ ++#endif /* __ixp46X */ ++ ++ ++ ++/* ++ * our driver startup and shutdown routines ++ */ ++ ++static int ++ixp_init(void) ++{ ++ dprintk("%s(%p)\n", __FUNCTION__, ixp_init); ++ ++ if (ixp_init_crypto && ixCryptoAccInit() != IX_CRYPTO_ACC_STATUS_SUCCESS) ++ printk("ixCryptoAccInit failed, assuming already initialised!\n"); ++ ++ qcache = kmem_cache_create("ixp4xx_q", sizeof(struct ixp_q), 0, ++ SLAB_HWCACHE_ALIGN, NULL ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) ++ , NULL ++#endif ++ ); ++ if (!qcache) { ++ printk("failed to create Qcache\n"); ++ return -ENOENT; ++ } ++ ++ memset(&ixpdev, 0, sizeof(ixpdev)); ++ softc_device_init(&ixpdev, "ixp4xx", 0, ixp_methods); ++ ++ ixp_id = crypto_get_driverid(softc_get_device(&ixpdev), ++ CRYPTOCAP_F_HARDWARE); ++ if (ixp_id < 0) ++ panic("IXP/OCF crypto device cannot initialize!"); ++ ++#define REGISTER(alg) \ ++ crypto_register(ixp_id,alg,0,0) ++ ++ REGISTER(CRYPTO_DES_CBC); ++ REGISTER(CRYPTO_3DES_CBC); ++ REGISTER(CRYPTO_RIJNDAEL128_CBC); ++#ifdef CONFIG_OCF_IXP4XX_SHA1_MD5 ++ REGISTER(CRYPTO_MD5); ++ REGISTER(CRYPTO_SHA1); ++#endif ++ REGISTER(CRYPTO_MD5_HMAC); ++ REGISTER(CRYPTO_SHA1_HMAC); ++#undef REGISTER ++ ++#ifdef __ixp46X ++ spin_lock_init(&ixp_pkq_lock); ++ /* ++ * we do not enable the go fast options here as they can potentially ++ * allow timing based attacks ++ * ++ * http://www.openssl.org/news/secadv_20030219.txt ++ */ ++ ixCryptoAccPkeEauExpConfig(0, 0); ++ crypto_kregister(ixp_id, CRK_MOD_EXP, 0); ++#ifdef CONFIG_OCF_RANDOMHARVEST ++ crypto_rregister(ixp_id, ixp_read_random, NULL); ++#endif ++#endif ++ ++ return 0; ++} ++ ++static void ++ixp_exit(void) ++{ ++ dprintk("%s()\n", __FUNCTION__); ++ crypto_unregister_all(ixp_id); ++ ixp_id = -1; ++ kmem_cache_destroy(qcache); ++ qcache = NULL; ++} ++ ++module_init(ixp_init); ++module_exit(ixp_exit); ++ ++MODULE_LICENSE("Dual BSD/GPL"); ++MODULE_AUTHOR("David McCullough "); ++MODULE_DESCRIPTION("ixp (OCF module for IXP4xx crypto)"); +diff -Nur linux-3.0.4.orig/crypto/ocf/ixp4xx/Makefile linux-3.0.4/crypto/ocf/ixp4xx/Makefile +--- linux-3.0.4.orig/crypto/ocf/ixp4xx/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/ixp4xx/Makefile 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,104 @@ ++# for SGlinux builds ++-include $(ROOTDIR)/modules/.config ++ ++# ++# You will need to point this at your Intel ixp425 includes, this portion ++# of the Makefile only really works under SGLinux with the appropriate libs ++# installed. They can be downloaded from http://www.snapgear.org/ ++# ++ifeq ($(CONFIG_CPU_IXP46X),y) ++IXPLATFORM = ixp46X ++else ++ifeq ($(CONFIG_CPU_IXP43X),y) ++IXPLATFORM = ixp43X ++else ++IXPLATFORM = ixp42X ++endif ++endif ++ ++ifdef CONFIG_IXP400_LIB_2_4 ++IX_XSCALE_SW = $(ROOTDIR)/modules/ixp425/ixp400-2.4/ixp400_xscale_sw ++OSAL_DIR = $(ROOTDIR)/modules/ixp425/ixp400-2.4/ixp_osal ++endif ++ifdef CONFIG_IXP400_LIB_2_1 ++IX_XSCALE_SW = $(ROOTDIR)/modules/ixp425/ixp400-2.1/ixp400_xscale_sw ++OSAL_DIR = $(ROOTDIR)/modules/ixp425/ixp400-2.1/ixp_osal ++endif ++ifdef CONFIG_IXP400_LIB_2_0 ++IX_XSCALE_SW = $(ROOTDIR)/modules/ixp425/ixp400-2.0/ixp400_xscale_sw ++OSAL_DIR = $(ROOTDIR)/modules/ixp425/ixp400-2.0/ixp_osal ++endif ++ifdef IX_XSCALE_SW ++ifdef CONFIG_IXP400_LIB_2_4 ++IXP_CFLAGS = \ ++ -I$(ROOTDIR)/. \ ++ -I$(IX_XSCALE_SW)/src/include \ ++ -I$(OSAL_DIR)/common/include/ \ ++ -I$(OSAL_DIR)/common/include/modules/ \ ++ -I$(OSAL_DIR)/common/include/modules/ddk/ \ ++ -I$(OSAL_DIR)/common/include/modules/bufferMgt/ \ ++ -I$(OSAL_DIR)/common/include/modules/ioMem/ \ ++ -I$(OSAL_DIR)/common/os/linux/include/ \ ++ -I$(OSAL_DIR)/common/os/linux/include/core/ \ ++ -I$(OSAL_DIR)/common/os/linux/include/modules/ \ ++ -I$(OSAL_DIR)/common/os/linux/include/modules/ddk/ \ ++ -I$(OSAL_DIR)/common/os/linux/include/modules/bufferMgt/ \ ++ -I$(OSAL_DIR)/common/os/linux/include/modules/ioMem/ \ ++ -I$(OSAL_DIR)/platforms/$(IXPLATFORM)/include/ \ ++ -I$(OSAL_DIR)/platforms/$(IXPLATFORM)/os/linux/include/ \ ++ -DENABLE_IOMEM -DENABLE_BUFFERMGT -DENABLE_DDK \ ++ -DUSE_IXP4XX_CRYPTO ++else ++IXP_CFLAGS = \ ++ -I$(ROOTDIR)/. \ ++ -I$(IX_XSCALE_SW)/src/include \ ++ -I$(OSAL_DIR)/ \ ++ -I$(OSAL_DIR)/os/linux/include/ \ ++ -I$(OSAL_DIR)/os/linux/include/modules/ \ ++ -I$(OSAL_DIR)/os/linux/include/modules/ioMem/ \ ++ -I$(OSAL_DIR)/os/linux/include/modules/bufferMgt/ \ ++ -I$(OSAL_DIR)/os/linux/include/core/ \ ++ -I$(OSAL_DIR)/os/linux/include/platforms/ \ ++ -I$(OSAL_DIR)/os/linux/include/platforms/ixp400/ \ ++ -I$(OSAL_DIR)/os/linux/include/platforms/ixp400/ixp425 \ ++ -I$(OSAL_DIR)/os/linux/include/platforms/ixp400/ixp465 \ ++ -I$(OSAL_DIR)/os/linux/include/core/ \ ++ -I$(OSAL_DIR)/include/ \ ++ -I$(OSAL_DIR)/include/modules/ \ ++ -I$(OSAL_DIR)/include/modules/bufferMgt/ \ ++ -I$(OSAL_DIR)/include/modules/ioMem/ \ ++ -I$(OSAL_DIR)/include/platforms/ \ ++ -I$(OSAL_DIR)/include/platforms/ixp400/ \ ++ -DUSE_IXP4XX_CRYPTO ++endif ++endif ++ifdef CONFIG_IXP400_LIB_1_4 ++IXP_CFLAGS = \ ++ -I$(ROOTDIR)/. \ ++ -I$(ROOTDIR)/modules/ixp425/ixp400-1.4/ixp400_xscale_sw/src/include \ ++ -I$(ROOTDIR)/modules/ixp425/ixp400-1.4/ixp400_xscale_sw/src/linux \ ++ -DUSE_IXP4XX_CRYPTO ++endif ++ifndef IXPDIR ++IXPDIR = ixp-version-is-not-supported ++endif ++ ++ifeq ($(CONFIG_CPU_IXP46X),y) ++IXP_CFLAGS += -D__ixp46X ++else ++ifeq ($(CONFIG_CPU_IXP43X),y) ++IXP_CFLAGS += -D__ixp43X ++else ++IXP_CFLAGS += -D__ixp42X ++endif ++endif ++ ++obj-$(CONFIG_OCF_IXP4XX) += ixp4xx.o ++ ++obj ?= . ++EXTRA_CFLAGS += $(IXP_CFLAGS) -I$(obj)/.. -I$(obj)/. ++ ++ifdef TOPDIR ++-include $(TOPDIR)/Rules.make ++endif ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/ixp4xx/ixp4xx.c linux-3.0.4/crypto/ocf/ixp4xx/ixp4xx.c +--- linux-3.0.4.orig/crypto/ocf/ixp4xx/ixp4xx.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/ixp4xx/ixp4xx.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,1339 @@ ++/* ++ * An OCF module that uses Intels IXP CryptACC API to do the crypto. ++ * This driver requires the IXP400 Access Library that is available ++ * from Intel in order to operate (or compile). ++ * ++ * Written by David McCullough ++ * Copyright (C) 2006-2011 David McCullough ++ * Copyright (C) 2004-2005 Intel Corporation. ++ * ++ * LICENSE TERMS ++ * ++ * The free distribution and use of this software in both source and binary ++ * form is allowed (with or without changes) provided that: ++ * ++ * 1. distributions of this source code include the above copyright ++ * notice, this list of conditions and the following disclaimer; ++ * ++ * 2. distributions in binary form include the above copyright ++ * notice, this list of conditions and the following disclaimer ++ * in the documentation and/or other associated materials; ++ * ++ * 3. the copyright holder's name is not used to endorse products ++ * built using this software without specific written permission. ++ * ++ * ALTERNATIVELY, provided that this notice is retained in full, this product ++ * may be distributed under the terms of the GNU General Public License (GPL), ++ * in which case the provisions of the GPL apply INSTEAD OF those given above. ++ * ++ * DISCLAIMER ++ * ++ * This software is provided 'as is' with no explicit or implied warranties ++ * in respect of its properties, including, but not limited to, correctness ++ * and/or fitness for purpose. ++ */ ++ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#ifndef IX_MBUF_PRIV ++#define IX_MBUF_PRIV(x) ((x)->priv) ++#endif ++ ++struct ixp_data; ++ ++struct ixp_q { ++ struct list_head ixp_q_list; ++ struct ixp_data *ixp_q_data; ++ struct cryptop *ixp_q_crp; ++ struct cryptodesc *ixp_q_ccrd; ++ struct cryptodesc *ixp_q_acrd; ++ IX_MBUF ixp_q_mbuf; ++ UINT8 *ixp_hash_dest; /* Location for hash in client buffer */ ++ UINT8 *ixp_hash_src; /* Location of hash in internal buffer */ ++ unsigned char ixp_q_iv_data[IX_CRYPTO_ACC_MAX_CIPHER_IV_LENGTH]; ++ unsigned char *ixp_q_iv; ++}; ++ ++struct ixp_data { ++ int ixp_registered; /* is the context registered */ ++ int ixp_crd_flags; /* detect direction changes */ ++ ++ int ixp_cipher_alg; ++ int ixp_auth_alg; ++ ++ UINT32 ixp_ctx_id; ++ UINT32 ixp_hash_key_id; /* used when hashing */ ++ IxCryptoAccCtx ixp_ctx; ++ IX_MBUF ixp_pri_mbuf; ++ IX_MBUF ixp_sec_mbuf; ++ ++ struct work_struct ixp_pending_work; ++ struct work_struct ixp_registration_work; ++ struct list_head ixp_q; /* unprocessed requests */ ++}; ++ ++#ifdef __ixp46X ++ ++#define MAX_IOP_SIZE 64 /* words */ ++#define MAX_OOP_SIZE 128 ++ ++#define MAX_PARAMS 3 ++ ++struct ixp_pkq { ++ struct list_head pkq_list; ++ struct cryptkop *pkq_krp; ++ ++ IxCryptoAccPkeEauInOperands pkq_op; ++ IxCryptoAccPkeEauOpResult pkq_result; ++ ++ UINT32 pkq_ibuf0[MAX_IOP_SIZE]; ++ UINT32 pkq_ibuf1[MAX_IOP_SIZE]; ++ UINT32 pkq_ibuf2[MAX_IOP_SIZE]; ++ UINT32 pkq_obuf[MAX_OOP_SIZE]; ++}; ++ ++static LIST_HEAD(ixp_pkq); /* current PK wait list */ ++static struct ixp_pkq *ixp_pk_cur; ++static spinlock_t ixp_pkq_lock; ++ ++#endif /* __ixp46X */ ++ ++static int ixp_blocked = 0; ++ ++static int32_t ixp_id = -1; ++static struct ixp_data **ixp_sessions = NULL; ++static u_int32_t ixp_sesnum = 0; ++ ++static int ixp_process(device_t, struct cryptop *, int); ++static int ixp_newsession(device_t, u_int32_t *, struct cryptoini *); ++static int ixp_freesession(device_t, u_int64_t); ++#ifdef __ixp46X ++static int ixp_kprocess(device_t, struct cryptkop *krp, int hint); ++#endif ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) ++static kmem_cache_t *qcache; ++#else ++static struct kmem_cache *qcache; ++#endif ++ ++#define debug ixp_debug ++static int ixp_debug = 0; ++module_param(ixp_debug, int, 0644); ++MODULE_PARM_DESC(ixp_debug, "Enable debug"); ++ ++static int ixp_init_crypto = 1; ++module_param(ixp_init_crypto, int, 0444); /* RO after load/boot */ ++MODULE_PARM_DESC(ixp_init_crypto, "Call ixCryptoAccInit (default is 1)"); ++ ++static void ixp_process_pending(void *arg); ++static void ixp_registration(void *arg); ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++static void ixp_process_pending_wq(struct work_struct *work); ++static void ixp_registration_wq(struct work_struct *work); ++#endif ++ ++/* ++ * dummy device structure ++ */ ++ ++static struct { ++ softc_device_decl sc_dev; ++} ixpdev; ++ ++static device_method_t ixp_methods = { ++ /* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, ixp_newsession), ++ DEVMETHOD(cryptodev_freesession,ixp_freesession), ++ DEVMETHOD(cryptodev_process, ixp_process), ++#ifdef __ixp46X ++ DEVMETHOD(cryptodev_kprocess, ixp_kprocess), ++#endif ++}; ++ ++/* ++ * Generate a new software session. ++ */ ++static int ++ixp_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) ++{ ++ struct ixp_data *ixp; ++ u_int32_t i; ++#define AUTH_LEN(cri, def) \ ++ (cri->cri_mlen ? cri->cri_mlen : (def)) ++ ++ dprintk("%s():alg %d\n", __FUNCTION__,cri->cri_alg); ++ if (sid == NULL || cri == NULL) { ++ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ if (ixp_sessions) { ++ for (i = 1; i < ixp_sesnum; i++) ++ if (ixp_sessions[i] == NULL) ++ break; ++ } else ++ i = 1; /* NB: to silence compiler warning */ ++ ++ if (ixp_sessions == NULL || i == ixp_sesnum) { ++ struct ixp_data **ixpd; ++ ++ if (ixp_sessions == NULL) { ++ i = 1; /* We leave ixp_sessions[0] empty */ ++ ixp_sesnum = CRYPTO_SW_SESSIONS; ++ } else ++ ixp_sesnum *= 2; ++ ++ ixpd = kmalloc(ixp_sesnum * sizeof(struct ixp_data *), SLAB_ATOMIC); ++ if (ixpd == NULL) { ++ /* Reset session number */ ++ if (ixp_sesnum == CRYPTO_SW_SESSIONS) ++ ixp_sesnum = 0; ++ else ++ ixp_sesnum /= 2; ++ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ memset(ixpd, 0, ixp_sesnum * sizeof(struct ixp_data *)); ++ ++ /* Copy existing sessions */ ++ if (ixp_sessions) { ++ memcpy(ixpd, ixp_sessions, ++ (ixp_sesnum / 2) * sizeof(struct ixp_data *)); ++ kfree(ixp_sessions); ++ } ++ ++ ixp_sessions = ixpd; ++ } ++ ++ ixp_sessions[i] = (struct ixp_data *) kmalloc(sizeof(struct ixp_data), ++ SLAB_ATOMIC); ++ if (ixp_sessions[i] == NULL) { ++ ixp_freesession(NULL, i); ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ ++ *sid = i; ++ ++ ixp = ixp_sessions[i]; ++ memset(ixp, 0, sizeof(*ixp)); ++ ++ ixp->ixp_cipher_alg = -1; ++ ixp->ixp_auth_alg = -1; ++ ixp->ixp_ctx_id = -1; ++ INIT_LIST_HEAD(&ixp->ixp_q); ++ ++ ixp->ixp_ctx.useDifferentSrcAndDestMbufs = 0; ++ ++ while (cri) { ++ switch (cri->cri_alg) { ++ case CRYPTO_DES_CBC: ++ ixp->ixp_cipher_alg = cri->cri_alg; ++ ixp->ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_DES; ++ ixp->ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; ++ ixp->ixp_ctx.cipherCtx.cipherKeyLen = (cri->cri_klen + 7) / 8; ++ ixp->ixp_ctx.cipherCtx.cipherBlockLen = IX_CRYPTO_ACC_DES_BLOCK_64; ++ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen = ++ IX_CRYPTO_ACC_DES_IV_64; ++ memcpy(ixp->ixp_ctx.cipherCtx.key.cipherKey, ++ cri->cri_key, (cri->cri_klen + 7) / 8); ++ break; ++ ++ case CRYPTO_3DES_CBC: ++ ixp->ixp_cipher_alg = cri->cri_alg; ++ ixp->ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_3DES; ++ ixp->ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; ++ ixp->ixp_ctx.cipherCtx.cipherKeyLen = (cri->cri_klen + 7) / 8; ++ ixp->ixp_ctx.cipherCtx.cipherBlockLen = IX_CRYPTO_ACC_DES_BLOCK_64; ++ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen = ++ IX_CRYPTO_ACC_DES_IV_64; ++ memcpy(ixp->ixp_ctx.cipherCtx.key.cipherKey, ++ cri->cri_key, (cri->cri_klen + 7) / 8); ++ break; ++ ++ case CRYPTO_RIJNDAEL128_CBC: ++ ixp->ixp_cipher_alg = cri->cri_alg; ++ ixp->ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_AES; ++ ixp->ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; ++ ixp->ixp_ctx.cipherCtx.cipherKeyLen = (cri->cri_klen + 7) / 8; ++ ixp->ixp_ctx.cipherCtx.cipherBlockLen = 16; ++ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen = 16; ++ memcpy(ixp->ixp_ctx.cipherCtx.key.cipherKey, ++ cri->cri_key, (cri->cri_klen + 7) / 8); ++ break; ++ ++ case CRYPTO_MD5: ++ case CRYPTO_MD5_HMAC: ++ ixp->ixp_auth_alg = cri->cri_alg; ++ ixp->ixp_ctx.authCtx.authAlgo = IX_CRYPTO_ACC_AUTH_MD5; ++ ixp->ixp_ctx.authCtx.authDigestLen = AUTH_LEN(cri, MD5_HASH_LEN); ++ ixp->ixp_ctx.authCtx.aadLen = 0; ++ /* Only MD5_HMAC needs a key */ ++ if (cri->cri_alg == CRYPTO_MD5_HMAC) { ++ ixp->ixp_ctx.authCtx.authKeyLen = (cri->cri_klen + 7) / 8; ++ if (ixp->ixp_ctx.authCtx.authKeyLen > ++ sizeof(ixp->ixp_ctx.authCtx.key.authKey)) { ++ printk( ++ "ixp4xx: Invalid key length for MD5_HMAC - %d bits\n", ++ cri->cri_klen); ++ ixp_freesession(NULL, i); ++ return EINVAL; ++ } ++ memcpy(ixp->ixp_ctx.authCtx.key.authKey, ++ cri->cri_key, (cri->cri_klen + 7) / 8); ++ } ++ break; ++ ++ case CRYPTO_SHA1: ++ case CRYPTO_SHA1_HMAC: ++ ixp->ixp_auth_alg = cri->cri_alg; ++ ixp->ixp_ctx.authCtx.authAlgo = IX_CRYPTO_ACC_AUTH_SHA1; ++ ixp->ixp_ctx.authCtx.authDigestLen = AUTH_LEN(cri, SHA1_HASH_LEN); ++ ixp->ixp_ctx.authCtx.aadLen = 0; ++ /* Only SHA1_HMAC needs a key */ ++ if (cri->cri_alg == CRYPTO_SHA1_HMAC) { ++ ixp->ixp_ctx.authCtx.authKeyLen = (cri->cri_klen + 7) / 8; ++ if (ixp->ixp_ctx.authCtx.authKeyLen > ++ sizeof(ixp->ixp_ctx.authCtx.key.authKey)) { ++ printk( ++ "ixp4xx: Invalid key length for SHA1_HMAC - %d bits\n", ++ cri->cri_klen); ++ ixp_freesession(NULL, i); ++ return EINVAL; ++ } ++ memcpy(ixp->ixp_ctx.authCtx.key.authKey, ++ cri->cri_key, (cri->cri_klen + 7) / 8); ++ } ++ break; ++ ++ default: ++ printk("ixp: unknown algo 0x%x\n", cri->cri_alg); ++ ixp_freesession(NULL, i); ++ return EINVAL; ++ } ++ cri = cri->cri_next; ++ } ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++ INIT_WORK(&ixp->ixp_pending_work, ixp_process_pending_wq); ++ INIT_WORK(&ixp->ixp_registration_work, ixp_registration_wq); ++#else ++ INIT_WORK(&ixp->ixp_pending_work, ixp_process_pending, ixp); ++ INIT_WORK(&ixp->ixp_registration_work, ixp_registration, ixp); ++#endif ++ ++ return 0; ++} ++ ++ ++/* ++ * Free a session. ++ */ ++static int ++ixp_freesession(device_t dev, u_int64_t tid) ++{ ++ u_int32_t sid = CRYPTO_SESID2LID(tid); ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (sid > ixp_sesnum || ixp_sessions == NULL || ++ ixp_sessions[sid] == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ /* Silently accept and return */ ++ if (sid == 0) ++ return 0; ++ ++ if (ixp_sessions[sid]) { ++ if (ixp_sessions[sid]->ixp_ctx_id != -1) { ++ ixCryptoAccCtxUnregister(ixp_sessions[sid]->ixp_ctx_id); ++ ixp_sessions[sid]->ixp_ctx_id = -1; ++ } ++ kfree(ixp_sessions[sid]); ++ } ++ ixp_sessions[sid] = NULL; ++ if (ixp_blocked) { ++ ixp_blocked = 0; ++ crypto_unblock(ixp_id, CRYPTO_SYMQ); ++ } ++ return 0; ++} ++ ++ ++/* ++ * callback for when hash processing is complete ++ */ ++ ++static void ++ixp_hash_perform_cb( ++ UINT32 hash_key_id, ++ IX_MBUF *bufp, ++ IxCryptoAccStatus status) ++{ ++ struct ixp_q *q; ++ ++ dprintk("%s(%u, %p, 0x%x)\n", __FUNCTION__, hash_key_id, bufp, status); ++ ++ if (bufp == NULL) { ++ printk("ixp: NULL buf in %s\n", __FUNCTION__); ++ return; ++ } ++ ++ q = IX_MBUF_PRIV(bufp); ++ if (q == NULL) { ++ printk("ixp: NULL priv in %s\n", __FUNCTION__); ++ return; ++ } ++ ++ if (status == IX_CRYPTO_ACC_STATUS_SUCCESS) { ++ /* On success, need to copy hash back into original client buffer */ ++ memcpy(q->ixp_hash_dest, q->ixp_hash_src, ++ (q->ixp_q_data->ixp_auth_alg == CRYPTO_SHA1) ? ++ SHA1_HASH_LEN : MD5_HASH_LEN); ++ } ++ else { ++ printk("ixp: hash perform failed status=%d\n", status); ++ q->ixp_q_crp->crp_etype = EINVAL; ++ } ++ ++ /* Free internal buffer used for hashing */ ++ kfree(IX_MBUF_MDATA(&q->ixp_q_mbuf)); ++ ++ crypto_done(q->ixp_q_crp); ++ kmem_cache_free(qcache, q); ++} ++ ++/* ++ * setup a request and perform it ++ */ ++static void ++ixp_q_process(struct ixp_q *q) ++{ ++ IxCryptoAccStatus status; ++ struct ixp_data *ixp = q->ixp_q_data; ++ int auth_off = 0; ++ int auth_len = 0; ++ int crypt_off = 0; ++ int crypt_len = 0; ++ int icv_off = 0; ++ char *crypt_func; ++ ++ dprintk("%s(%p)\n", __FUNCTION__, q); ++ ++ if (q->ixp_q_ccrd) { ++ if (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT) { ++ if (q->ixp_q_ccrd->crd_flags & CRD_F_IV_EXPLICIT) { ++ q->ixp_q_iv = q->ixp_q_ccrd->crd_iv; ++ } else { ++ q->ixp_q_iv = q->ixp_q_iv_data; ++ read_random(q->ixp_q_iv, ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen); ++ } ++ if ((q->ixp_q_ccrd->crd_flags & CRD_F_IV_PRESENT) == 0) ++ crypto_copyback(q->ixp_q_crp->crp_flags, q->ixp_q_crp->crp_buf, ++ q->ixp_q_ccrd->crd_inject, ++ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen, ++ (caddr_t) q->ixp_q_iv); ++ } else { ++ if (q->ixp_q_ccrd->crd_flags & CRD_F_IV_EXPLICIT) ++ q->ixp_q_iv = q->ixp_q_ccrd->crd_iv; ++ else { ++ q->ixp_q_iv = q->ixp_q_iv_data; ++ crypto_copydata(q->ixp_q_crp->crp_flags, q->ixp_q_crp->crp_buf, ++ q->ixp_q_ccrd->crd_inject, ++ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen, ++ (caddr_t) q->ixp_q_iv); ++ } ++ } ++ ++ if (q->ixp_q_acrd) { ++ auth_off = q->ixp_q_acrd->crd_skip; ++ auth_len = q->ixp_q_acrd->crd_len; ++ icv_off = q->ixp_q_acrd->crd_inject; ++ } ++ ++ crypt_off = q->ixp_q_ccrd->crd_skip; ++ crypt_len = q->ixp_q_ccrd->crd_len; ++ } else { /* if (q->ixp_q_acrd) */ ++ auth_off = q->ixp_q_acrd->crd_skip; ++ auth_len = q->ixp_q_acrd->crd_len; ++ icv_off = q->ixp_q_acrd->crd_inject; ++ } ++ ++ if (q->ixp_q_crp->crp_flags & CRYPTO_F_SKBUF) { ++ struct sk_buff *skb = (struct sk_buff *) q->ixp_q_crp->crp_buf; ++ if (skb_shinfo(skb)->nr_frags) { ++ /* ++ * DAVIDM fix this limitation one day by using ++ * a buffer pool and chaining, it is not currently ++ * needed for current user/kernel space acceleration ++ */ ++ printk("ixp: Cannot handle fragmented skb's yet !\n"); ++ q->ixp_q_crp->crp_etype = ENOENT; ++ goto done; ++ } ++ IX_MBUF_MLEN(&q->ixp_q_mbuf) = ++ IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = skb->len; ++ IX_MBUF_MDATA(&q->ixp_q_mbuf) = skb->data; ++ } else if (q->ixp_q_crp->crp_flags & CRYPTO_F_IOV) { ++ struct uio *uiop = (struct uio *) q->ixp_q_crp->crp_buf; ++ if (uiop->uio_iovcnt != 1) { ++ /* ++ * DAVIDM fix this limitation one day by using ++ * a buffer pool and chaining, it is not currently ++ * needed for current user/kernel space acceleration ++ */ ++ printk("ixp: Cannot handle more than 1 iovec yet !\n"); ++ q->ixp_q_crp->crp_etype = ENOENT; ++ goto done; ++ } ++ IX_MBUF_MLEN(&q->ixp_q_mbuf) = ++ IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = uiop->uio_iov[0].iov_len; ++ IX_MBUF_MDATA(&q->ixp_q_mbuf) = uiop->uio_iov[0].iov_base; ++ } else /* contig buffer */ { ++ IX_MBUF_MLEN(&q->ixp_q_mbuf) = ++ IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = q->ixp_q_crp->crp_ilen; ++ IX_MBUF_MDATA(&q->ixp_q_mbuf) = q->ixp_q_crp->crp_buf; ++ } ++ ++ IX_MBUF_PRIV(&q->ixp_q_mbuf) = q; ++ ++ if (ixp->ixp_auth_alg == CRYPTO_SHA1 || ixp->ixp_auth_alg == CRYPTO_MD5) { ++ /* ++ * For SHA1 and MD5 hash, need to create an internal buffer that is big ++ * enough to hold the original data + the appropriate padding for the ++ * hash algorithm. ++ */ ++ UINT8 *tbuf = NULL; ++ ++ IX_MBUF_MLEN(&q->ixp_q_mbuf) = IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = ++ ((IX_MBUF_MLEN(&q->ixp_q_mbuf) * 8) + 72 + 511) / 8; ++ tbuf = kmalloc(IX_MBUF_MLEN(&q->ixp_q_mbuf), SLAB_ATOMIC); ++ ++ if (IX_MBUF_MDATA(&q->ixp_q_mbuf) == NULL) { ++ printk("ixp: kmalloc(%u, SLAB_ATOMIC) failed\n", ++ IX_MBUF_MLEN(&q->ixp_q_mbuf)); ++ q->ixp_q_crp->crp_etype = ENOMEM; ++ goto done; ++ } ++ memcpy(tbuf, &(IX_MBUF_MDATA(&q->ixp_q_mbuf))[auth_off], auth_len); ++ ++ /* Set location in client buffer to copy hash into */ ++ q->ixp_hash_dest = ++ &(IX_MBUF_MDATA(&q->ixp_q_mbuf))[auth_off + auth_len]; ++ ++ IX_MBUF_MDATA(&q->ixp_q_mbuf) = tbuf; ++ ++ /* Set location in internal buffer for where hash starts */ ++ q->ixp_hash_src = &(IX_MBUF_MDATA(&q->ixp_q_mbuf))[auth_len]; ++ ++ crypt_func = "ixCryptoAccHashPerform"; ++ status = ixCryptoAccHashPerform(ixp->ixp_ctx.authCtx.authAlgo, ++ &q->ixp_q_mbuf, ixp_hash_perform_cb, 0, auth_len, auth_len, ++ &ixp->ixp_hash_key_id); ++ } ++ else { ++ crypt_func = "ixCryptoAccAuthCryptPerform"; ++ status = ixCryptoAccAuthCryptPerform(ixp->ixp_ctx_id, &q->ixp_q_mbuf, ++ NULL, auth_off, auth_len, crypt_off, crypt_len, icv_off, ++ q->ixp_q_iv); ++ } ++ ++ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) ++ return; ++ ++ if (IX_CRYPTO_ACC_STATUS_QUEUE_FULL == status) { ++ q->ixp_q_crp->crp_etype = ENOMEM; ++ goto done; ++ } ++ ++ printk("ixp: %s failed %u\n", crypt_func, status); ++ q->ixp_q_crp->crp_etype = EINVAL; ++ ++done: ++ crypto_done(q->ixp_q_crp); ++ kmem_cache_free(qcache, q); ++} ++ ++ ++/* ++ * because we cannot process the Q from the Register callback ++ * we do it here on a task Q. ++ */ ++ ++static void ++ixp_process_pending(void *arg) ++{ ++ struct ixp_data *ixp = arg; ++ struct ixp_q *q = NULL; ++ ++ dprintk("%s(%p)\n", __FUNCTION__, arg); ++ ++ if (!ixp) ++ return; ++ ++ while (!list_empty(&ixp->ixp_q)) { ++ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); ++ list_del(&q->ixp_q_list); ++ ixp_q_process(q); ++ } ++} ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++static void ++ixp_process_pending_wq(struct work_struct *work) ++{ ++ struct ixp_data *ixp = container_of(work, struct ixp_data, ixp_pending_work); ++ ixp_process_pending(ixp); ++} ++#endif ++ ++/* ++ * callback for when context registration is complete ++ */ ++ ++static void ++ixp_register_cb(UINT32 ctx_id, IX_MBUF *bufp, IxCryptoAccStatus status) ++{ ++ int i; ++ struct ixp_data *ixp; ++ struct ixp_q *q; ++ ++ dprintk("%s(%d, %p, %d)\n", __FUNCTION__, ctx_id, bufp, status); ++ ++ /* ++ * free any buffer passed in to this routine ++ */ ++ if (bufp) { ++ IX_MBUF_MLEN(bufp) = IX_MBUF_PKT_LEN(bufp) = 0; ++ kfree(IX_MBUF_MDATA(bufp)); ++ IX_MBUF_MDATA(bufp) = NULL; ++ } ++ ++ for (i = 0; i < ixp_sesnum; i++) { ++ ixp = ixp_sessions[i]; ++ if (ixp && ixp->ixp_ctx_id == ctx_id) ++ break; ++ } ++ if (i >= ixp_sesnum) { ++ printk("ixp: invalid context id %d\n", ctx_id); ++ return; ++ } ++ ++ if (IX_CRYPTO_ACC_STATUS_WAIT == status) { ++ /* this is normal to free the first of two buffers */ ++ dprintk("ixp: register not finished yet.\n"); ++ return; ++ } ++ ++ if (IX_CRYPTO_ACC_STATUS_SUCCESS != status) { ++ printk("ixp: register failed 0x%x\n", status); ++ while (!list_empty(&ixp->ixp_q)) { ++ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); ++ list_del(&q->ixp_q_list); ++ q->ixp_q_crp->crp_etype = EINVAL; ++ crypto_done(q->ixp_q_crp); ++ kmem_cache_free(qcache, q); ++ } ++ return; ++ } ++ ++ /* ++ * we are now registered, we cannot start processing the Q here ++ * or we get strange errors with AES (DES/3DES seem to be ok). ++ */ ++ ixp->ixp_registered = 1; ++ schedule_work(&ixp->ixp_pending_work); ++} ++ ++ ++/* ++ * callback for when data processing is complete ++ */ ++ ++static void ++ixp_perform_cb( ++ UINT32 ctx_id, ++ IX_MBUF *sbufp, ++ IX_MBUF *dbufp, ++ IxCryptoAccStatus status) ++{ ++ struct ixp_q *q; ++ ++ dprintk("%s(%d, %p, %p, 0x%x)\n", __FUNCTION__, ctx_id, sbufp, ++ dbufp, status); ++ ++ if (sbufp == NULL) { ++ printk("ixp: NULL sbuf in ixp_perform_cb\n"); ++ return; ++ } ++ ++ q = IX_MBUF_PRIV(sbufp); ++ if (q == NULL) { ++ printk("ixp: NULL priv in ixp_perform_cb\n"); ++ return; ++ } ++ ++ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { ++ printk("ixp: perform failed status=%d\n", status); ++ q->ixp_q_crp->crp_etype = EINVAL; ++ } ++ ++ crypto_done(q->ixp_q_crp); ++ kmem_cache_free(qcache, q); ++} ++ ++ ++/* ++ * registration is not callable at IRQ time, so we defer ++ * to a task queue, this routines completes the registration for us ++ * when the task queue runs ++ * ++ * Unfortunately this means we cannot tell OCF that the driver is blocked, ++ * we do that on the next request. ++ */ ++ ++static void ++ixp_registration(void *arg) ++{ ++ struct ixp_data *ixp = arg; ++ struct ixp_q *q = NULL; ++ IX_MBUF *pri = NULL, *sec = NULL; ++ int status = IX_CRYPTO_ACC_STATUS_SUCCESS; ++ ++ if (!ixp) { ++ printk("ixp: ixp_registration with no arg\n"); ++ return; ++ } ++ ++ if (ixp->ixp_ctx_id != -1) { ++ ixCryptoAccCtxUnregister(ixp->ixp_ctx_id); ++ ixp->ixp_ctx_id = -1; ++ } ++ ++ if (list_empty(&ixp->ixp_q)) { ++ printk("ixp: ixp_registration with no Q\n"); ++ return; ++ } ++ ++ /* ++ * setup the primary and secondary buffers ++ */ ++ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); ++ if (q->ixp_q_acrd) { ++ pri = &ixp->ixp_pri_mbuf; ++ sec = &ixp->ixp_sec_mbuf; ++ IX_MBUF_MLEN(pri) = IX_MBUF_PKT_LEN(pri) = 128; ++ IX_MBUF_MDATA(pri) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); ++ IX_MBUF_MLEN(sec) = IX_MBUF_PKT_LEN(sec) = 128; ++ IX_MBUF_MDATA(sec) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); ++ } ++ ++ /* Only need to register if a crypt op or HMAC op */ ++ if (!(ixp->ixp_auth_alg == CRYPTO_SHA1 || ++ ixp->ixp_auth_alg == CRYPTO_MD5)) { ++ status = ixCryptoAccCtxRegister( ++ &ixp->ixp_ctx, ++ pri, sec, ++ ixp_register_cb, ++ ixp_perform_cb, ++ &ixp->ixp_ctx_id); ++ } ++ else { ++ /* Otherwise we start processing pending q */ ++ schedule_work(&ixp->ixp_pending_work); ++ } ++ ++ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) ++ return; ++ ++ if (IX_CRYPTO_ACC_STATUS_EXCEED_MAX_TUNNELS == status) { ++ printk("ixp: ixCryptoAccCtxRegister failed (out of tunnels)\n"); ++ ixp_blocked = 1; ++ /* perhaps we should return EGAIN on queued ops ? */ ++ return; ++ } ++ ++ printk("ixp: ixCryptoAccCtxRegister failed %d\n", status); ++ ixp->ixp_ctx_id = -1; ++ ++ /* ++ * everything waiting is toasted ++ */ ++ while (!list_empty(&ixp->ixp_q)) { ++ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); ++ list_del(&q->ixp_q_list); ++ q->ixp_q_crp->crp_etype = ENOENT; ++ crypto_done(q->ixp_q_crp); ++ kmem_cache_free(qcache, q); ++ } ++} ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++static void ++ixp_registration_wq(struct work_struct *work) ++{ ++ struct ixp_data *ixp = container_of(work, struct ixp_data, ++ ixp_registration_work); ++ ixp_registration(ixp); ++} ++#endif ++ ++/* ++ * Process a request. ++ */ ++static int ++ixp_process(device_t dev, struct cryptop *crp, int hint) ++{ ++ struct ixp_data *ixp; ++ unsigned int lid; ++ struct ixp_q *q = NULL; ++ int status; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ /* Sanity check */ ++ if (crp == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ crp->crp_etype = 0; ++ ++ if (ixp_blocked) ++ return ERESTART; ++ ++ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ crp->crp_etype = EINVAL; ++ goto done; ++ } ++ ++ /* ++ * find the session we are using ++ */ ++ ++ lid = crp->crp_sid & 0xffffffff; ++ if (lid >= ixp_sesnum || lid == 0 || ixp_sessions == NULL || ++ ixp_sessions[lid] == NULL) { ++ crp->crp_etype = ENOENT; ++ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); ++ goto done; ++ } ++ ixp = ixp_sessions[lid]; ++ ++ /* ++ * setup a new request ready for queuing ++ */ ++ q = kmem_cache_alloc(qcache, SLAB_ATOMIC); ++ if (q == NULL) { ++ dprintk("%s,%d: ENOMEM\n", __FILE__, __LINE__); ++ crp->crp_etype = ENOMEM; ++ goto done; ++ } ++ /* ++ * save some cycles by only zeroing the important bits ++ */ ++ memset(&q->ixp_q_mbuf, 0, sizeof(q->ixp_q_mbuf)); ++ q->ixp_q_ccrd = NULL; ++ q->ixp_q_acrd = NULL; ++ q->ixp_q_crp = crp; ++ q->ixp_q_data = ixp; ++ ++ /* ++ * point the cipher and auth descriptors appropriately ++ * check that we have something to do ++ */ ++ if (crp->crp_desc->crd_alg == ixp->ixp_cipher_alg) ++ q->ixp_q_ccrd = crp->crp_desc; ++ else if (crp->crp_desc->crd_alg == ixp->ixp_auth_alg) ++ q->ixp_q_acrd = crp->crp_desc; ++ else { ++ crp->crp_etype = ENOENT; ++ dprintk("%s,%d: bad desc match: ENOENT\n", __FILE__, __LINE__); ++ goto done; ++ } ++ if (crp->crp_desc->crd_next) { ++ if (crp->crp_desc->crd_next->crd_alg == ixp->ixp_cipher_alg) ++ q->ixp_q_ccrd = crp->crp_desc->crd_next; ++ else if (crp->crp_desc->crd_next->crd_alg == ixp->ixp_auth_alg) ++ q->ixp_q_acrd = crp->crp_desc->crd_next; ++ else { ++ crp->crp_etype = ENOENT; ++ dprintk("%s,%d: bad desc match: ENOENT\n", __FILE__, __LINE__); ++ goto done; ++ } ++ } ++ ++ /* ++ * If there is a direction change for this context then we mark it as ++ * unregistered and re-register is for the new direction. This is not ++ * a very expensive operation and currently only tends to happen when ++ * user-space application are doing benchmarks ++ * ++ * DM - we should be checking for pending requests before unregistering. ++ */ ++ if (q->ixp_q_ccrd && ixp->ixp_registered && ++ ixp->ixp_crd_flags != (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT)) { ++ dprintk("%s - detected direction change on session\n", __FUNCTION__); ++ ixp->ixp_registered = 0; ++ } ++ ++ /* ++ * if we are registered, call straight into the perform code ++ */ ++ if (ixp->ixp_registered) { ++ ixp_q_process(q); ++ return 0; ++ } ++ ++ /* ++ * the only part of the context not set in newsession is the direction ++ * dependent parts ++ */ ++ if (q->ixp_q_ccrd) { ++ ixp->ixp_crd_flags = (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT); ++ if (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT) { ++ ixp->ixp_ctx.operation = q->ixp_q_acrd ? ++ IX_CRYPTO_ACC_OP_ENCRYPT_AUTH : IX_CRYPTO_ACC_OP_ENCRYPT; ++ } else { ++ ixp->ixp_ctx.operation = q->ixp_q_acrd ? ++ IX_CRYPTO_ACC_OP_AUTH_DECRYPT : IX_CRYPTO_ACC_OP_DECRYPT; ++ } ++ } else { ++ /* q->ixp_q_acrd must be set if we are here */ ++ ixp->ixp_ctx.operation = IX_CRYPTO_ACC_OP_AUTH_CALC; ++ } ++ ++ status = list_empty(&ixp->ixp_q); ++ list_add_tail(&q->ixp_q_list, &ixp->ixp_q); ++ if (status) ++ schedule_work(&ixp->ixp_registration_work); ++ return 0; ++ ++done: ++ if (q) ++ kmem_cache_free(qcache, q); ++ crypto_done(crp); ++ return 0; ++} ++ ++ ++#ifdef __ixp46X ++/* ++ * key processing support for the ixp465 ++ */ ++ ++ ++/* ++ * copy a BN (LE) into a buffer (BE) an fill out the op appropriately ++ * assume zeroed and only copy bits that are significant ++ */ ++ ++static int ++ixp_copy_ibuf(struct crparam *p, IxCryptoAccPkeEauOperand *op, UINT32 *buf) ++{ ++ unsigned char *src = (unsigned char *) p->crp_p; ++ unsigned char *dst; ++ int len, bits = p->crp_nbits; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (bits > MAX_IOP_SIZE * sizeof(UINT32) * 8) { ++ dprintk("%s - ibuf too big (%d > %d)\n", __FUNCTION__, ++ bits, MAX_IOP_SIZE * sizeof(UINT32) * 8); ++ return -1; ++ } ++ ++ len = (bits + 31) / 32; /* the number UINT32's needed */ ++ ++ dst = (unsigned char *) &buf[len]; ++ dst--; ++ ++ while (bits > 0) { ++ *dst-- = *src++; ++ bits -= 8; ++ } ++ ++#if 0 /* no need to zero remaining bits as it is done during request alloc */ ++ while (dst > (unsigned char *) buf) ++ *dst-- = '\0'; ++#endif ++ ++ op->pData = buf; ++ op->dataLen = len; ++ return 0; ++} ++ ++/* ++ * copy out the result, be as forgiving as we can about small output buffers ++ */ ++ ++static int ++ixp_copy_obuf(struct crparam *p, IxCryptoAccPkeEauOpResult *op, UINT32 *buf) ++{ ++ unsigned char *dst = (unsigned char *) p->crp_p; ++ unsigned char *src = (unsigned char *) buf; ++ int len, z, bits = p->crp_nbits; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ len = op->dataLen * sizeof(UINT32); ++ ++ /* skip leading zeroes to be small buffer friendly */ ++ z = 0; ++ while (z < len && src[z] == '\0') ++ z++; ++ ++ src += len; ++ src--; ++ len -= z; ++ ++ while (len > 0 && bits > 0) { ++ *dst++ = *src--; ++ len--; ++ bits -= 8; ++ } ++ ++ while (bits > 0) { ++ *dst++ = '\0'; ++ bits -= 8; ++ } ++ ++ if (len > 0) { ++ dprintk("%s - obuf is %d (z=%d, ob=%d) bytes too small\n", ++ __FUNCTION__, len, z, p->crp_nbits / 8); ++ return -1; ++ } ++ ++ return 0; ++} ++ ++ ++/* ++ * the parameter offsets for exp_mod ++ */ ++ ++#define IXP_PARAM_BASE 0 ++#define IXP_PARAM_EXP 1 ++#define IXP_PARAM_MOD 2 ++#define IXP_PARAM_RES 3 ++ ++/* ++ * key processing complete callback, is also used to start processing ++ * by passing a NULL for pResult ++ */ ++ ++static void ++ixp_kperform_cb( ++ IxCryptoAccPkeEauOperation operation, ++ IxCryptoAccPkeEauOpResult *pResult, ++ BOOL carryOrBorrow, ++ IxCryptoAccStatus status) ++{ ++ struct ixp_pkq *q, *tmp; ++ unsigned long flags; ++ ++ dprintk("%s(0x%x, %p, %d, 0x%x)\n", __FUNCTION__, operation, pResult, ++ carryOrBorrow, status); ++ ++ /* handle a completed request */ ++ if (pResult) { ++ if (ixp_pk_cur && &ixp_pk_cur->pkq_result == pResult) { ++ q = ixp_pk_cur; ++ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { ++ dprintk("%s() - op failed 0x%x\n", __FUNCTION__, status); ++ q->pkq_krp->krp_status = ERANGE; /* could do better */ ++ } else { ++ /* copy out the result */ ++ if (ixp_copy_obuf(&q->pkq_krp->krp_param[IXP_PARAM_RES], ++ &q->pkq_result, q->pkq_obuf)) ++ q->pkq_krp->krp_status = ERANGE; ++ } ++ crypto_kdone(q->pkq_krp); ++ kfree(q); ++ ixp_pk_cur = NULL; ++ } else ++ printk("%s - callback with invalid result pointer\n", __FUNCTION__); ++ } ++ ++ spin_lock_irqsave(&ixp_pkq_lock, flags); ++ if (ixp_pk_cur || list_empty(&ixp_pkq)) { ++ spin_unlock_irqrestore(&ixp_pkq_lock, flags); ++ return; ++ } ++ ++ list_for_each_entry_safe(q, tmp, &ixp_pkq, pkq_list) { ++ ++ list_del(&q->pkq_list); ++ ixp_pk_cur = q; ++ ++ spin_unlock_irqrestore(&ixp_pkq_lock, flags); ++ ++ status = ixCryptoAccPkeEauPerform( ++ IX_CRYPTO_ACC_OP_EAU_MOD_EXP, ++ &q->pkq_op, ++ ixp_kperform_cb, ++ &q->pkq_result); ++ ++ if (status == IX_CRYPTO_ACC_STATUS_SUCCESS) { ++ dprintk("%s() - ixCryptoAccPkeEauPerform SUCCESS\n", __FUNCTION__); ++ return; /* callback will return here for callback */ ++ } else if (status == IX_CRYPTO_ACC_STATUS_RETRY) { ++ printk("%s() - ixCryptoAccPkeEauPerform RETRY\n", __FUNCTION__); ++ } else { ++ printk("%s() - ixCryptoAccPkeEauPerform failed %d\n", ++ __FUNCTION__, status); ++ } ++ q->pkq_krp->krp_status = ERANGE; /* could do better */ ++ crypto_kdone(q->pkq_krp); ++ kfree(q); ++ spin_lock_irqsave(&ixp_pkq_lock, flags); ++ } ++ spin_unlock_irqrestore(&ixp_pkq_lock, flags); ++} ++ ++ ++static int ++ixp_kprocess(device_t dev, struct cryptkop *krp, int hint) ++{ ++ struct ixp_pkq *q; ++ int rc = 0; ++ unsigned long flags; ++ ++ dprintk("%s l1=%d l2=%d l3=%d l4=%d\n", __FUNCTION__, ++ krp->krp_param[IXP_PARAM_BASE].crp_nbits, ++ krp->krp_param[IXP_PARAM_EXP].crp_nbits, ++ krp->krp_param[IXP_PARAM_MOD].crp_nbits, ++ krp->krp_param[IXP_PARAM_RES].crp_nbits); ++ ++ ++ if (krp->krp_op != CRK_MOD_EXP) { ++ krp->krp_status = EOPNOTSUPP; ++ goto err; ++ } ++ ++ q = (struct ixp_pkq *) kmalloc(sizeof(*q), GFP_KERNEL); ++ if (q == NULL) { ++ krp->krp_status = ENOMEM; ++ goto err; ++ } ++ ++ /* ++ * The PKE engine does not appear to zero the output buffer ++ * appropriately, so we need to do it all here. ++ */ ++ memset(q, 0, sizeof(*q)); ++ ++ q->pkq_krp = krp; ++ INIT_LIST_HEAD(&q->pkq_list); ++ ++ if (ixp_copy_ibuf(&krp->krp_param[IXP_PARAM_BASE], &q->pkq_op.modExpOpr.M, ++ q->pkq_ibuf0)) ++ rc = 1; ++ if (!rc && ixp_copy_ibuf(&krp->krp_param[IXP_PARAM_EXP], ++ &q->pkq_op.modExpOpr.e, q->pkq_ibuf1)) ++ rc = 2; ++ if (!rc && ixp_copy_ibuf(&krp->krp_param[IXP_PARAM_MOD], ++ &q->pkq_op.modExpOpr.N, q->pkq_ibuf2)) ++ rc = 3; ++ ++ if (rc) { ++ kfree(q); ++ krp->krp_status = ERANGE; ++ goto err; ++ } ++ ++ q->pkq_result.pData = q->pkq_obuf; ++ q->pkq_result.dataLen = ++ (krp->krp_param[IXP_PARAM_RES].crp_nbits + 31) / 32; ++ ++ spin_lock_irqsave(&ixp_pkq_lock, flags); ++ list_add_tail(&q->pkq_list, &ixp_pkq); ++ spin_unlock_irqrestore(&ixp_pkq_lock, flags); ++ ++ if (!ixp_pk_cur) ++ ixp_kperform_cb(0, NULL, 0, 0); ++ return (0); ++ ++err: ++ crypto_kdone(krp); ++ return (0); ++} ++ ++ ++ ++#ifdef CONFIG_OCF_RANDOMHARVEST ++/* ++ * We run the random number generator output through SHA so that it ++ * is FIPS compliant. ++ */ ++ ++static volatile int sha_done = 0; ++static unsigned char sha_digest[20]; ++ ++static void ++ixp_hash_cb(UINT8 *digest, IxCryptoAccStatus status) ++{ ++ dprintk("%s(%p, %d)\n", __FUNCTION__, digest, status); ++ if (sha_digest != digest) ++ printk("digest error\n"); ++ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) ++ sha_done = 1; ++ else ++ sha_done = -status; ++} ++ ++static int ++ixp_read_random(void *arg, u_int32_t *buf, int maxwords) ++{ ++ IxCryptoAccStatus status; ++ int i, n, rc; ++ ++ dprintk("%s(%p, %d)\n", __FUNCTION__, buf, maxwords); ++ memset(buf, 0, maxwords * sizeof(*buf)); ++ status = ixCryptoAccPkePseudoRandomNumberGet(maxwords, buf); ++ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { ++ dprintk("%s: ixCryptoAccPkePseudoRandomNumberGet failed %d\n", ++ __FUNCTION__, status); ++ return 0; ++ } ++ ++ /* ++ * run the random data through SHA to make it look more random ++ */ ++ ++ n = sizeof(sha_digest); /* process digest bytes at a time */ ++ ++ rc = 0; ++ for (i = 0; i < maxwords; i += n / sizeof(*buf)) { ++ if ((maxwords - i) * sizeof(*buf) < n) ++ n = (maxwords - i) * sizeof(*buf); ++ sha_done = 0; ++ status = ixCryptoAccPkeHashPerform(IX_CRYPTO_ACC_AUTH_SHA1, ++ (UINT8 *) &buf[i], n, ixp_hash_cb, sha_digest); ++ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { ++ dprintk("ixCryptoAccPkeHashPerform failed %d\n", status); ++ return -EIO; ++ } ++ while (!sha_done) ++ schedule(); ++ if (sha_done < 0) { ++ dprintk("ixCryptoAccPkeHashPerform failed CB %d\n", -sha_done); ++ return 0; ++ } ++ memcpy(&buf[i], sha_digest, n); ++ rc += n / sizeof(*buf);; ++ } ++ ++ return rc; ++} ++#endif /* CONFIG_OCF_RANDOMHARVEST */ ++ ++#endif /* __ixp46X */ ++ ++ ++ ++/* ++ * our driver startup and shutdown routines ++ */ ++ ++static int ++ixp_init(void) ++{ ++ dprintk("%s(%p)\n", __FUNCTION__, ixp_init); ++ ++ if (ixp_init_crypto && ixCryptoAccInit() != IX_CRYPTO_ACC_STATUS_SUCCESS) ++ printk("ixCryptoAccInit failed, assuming already initialised!\n"); ++ ++ qcache = kmem_cache_create("ixp4xx_q", sizeof(struct ixp_q), 0, ++ SLAB_HWCACHE_ALIGN, NULL ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) ++ , NULL ++#endif ++ ); ++ if (!qcache) { ++ printk("failed to create Qcache\n"); ++ return -ENOENT; ++ } ++ ++ memset(&ixpdev, 0, sizeof(ixpdev)); ++ softc_device_init(&ixpdev, "ixp4xx", 0, ixp_methods); ++ ++ ixp_id = crypto_get_driverid(softc_get_device(&ixpdev), ++ CRYPTOCAP_F_HARDWARE); ++ if (ixp_id < 0) ++ panic("IXP/OCF crypto device cannot initialize!"); ++ ++#define REGISTER(alg) \ ++ crypto_register(ixp_id,alg,0,0) ++ ++ REGISTER(CRYPTO_DES_CBC); ++ REGISTER(CRYPTO_3DES_CBC); ++ REGISTER(CRYPTO_RIJNDAEL128_CBC); ++#ifdef CONFIG_OCF_IXP4XX_SHA1_MD5 ++ REGISTER(CRYPTO_MD5); ++ REGISTER(CRYPTO_SHA1); ++#endif ++ REGISTER(CRYPTO_MD5_HMAC); ++ REGISTER(CRYPTO_SHA1_HMAC); ++#undef REGISTER ++ ++#ifdef __ixp46X ++ spin_lock_init(&ixp_pkq_lock); ++ /* ++ * we do not enable the go fast options here as they can potentially ++ * allow timing based attacks ++ * ++ * http://www.openssl.org/news/secadv_20030219.txt ++ */ ++ ixCryptoAccPkeEauExpConfig(0, 0); ++ crypto_kregister(ixp_id, CRK_MOD_EXP, 0); ++#ifdef CONFIG_OCF_RANDOMHARVEST ++ crypto_rregister(ixp_id, ixp_read_random, NULL); ++#endif ++#endif ++ ++ return 0; ++} ++ ++static void ++ixp_exit(void) ++{ ++ dprintk("%s()\n", __FUNCTION__); ++ crypto_unregister_all(ixp_id); ++ ixp_id = -1; ++ kmem_cache_destroy(qcache); ++ qcache = NULL; ++} ++ ++module_init(ixp_init); ++module_exit(ixp_exit); ++ ++MODULE_LICENSE("Dual BSD/GPL"); ++MODULE_AUTHOR("David McCullough "); ++MODULE_DESCRIPTION("ixp (OCF module for IXP4xx crypto)"); +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/Makefile linux-3.0.4/crypto/ocf/kirkwood/Makefile +--- linux-3.0.4.orig/crypto/ocf/kirkwood/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/Makefile 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,19 @@ ++# for SGlinux builds ++-include $(ROOTDIR)/modules/.config ++ ++obj-$(CONFIG_OCF_KIRKWOOD) += mv_cesa.o ++ ++mv_cesa-y := cesa/mvCesa.o cesa/mvLru.o cesa/mvMD5.o cesa/mvSHA1.o cesa/AES/mvAesAlg.o cesa/AES/mvAesApi.o cesa/mvCesaDebug.o cesa_ocf_drv.o ++ ++# Extra objects required by the CESA driver ++mv_cesa-y += mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.o mvHal/kw_family/boardEnv/mvBoardEnvLib.o mvHal/mv_hal/twsi/mvTwsi.o mvHal/kw_family/ctrlEnv/sys/mvCpuIf.o mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.o mvHal/kw_family/ctrlEnv/sys/mvSysDram.o mvHal/linux_oss/mvOs.o mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.o mvHal/mv_hal/gpp/mvGpp.o mvHal/kw_family/ctrlEnv/sys/mvSysPex.o mvHal/mv_hal/pex/mvPex.o mvHal/kw_family/boardEnv/mvBoardEnvSpec.o mvHal/common/mvCommon.o mvHal/common/mvDebug.o mvHal/kw_family/ctrlEnv/sys/mvSysCesa.o ++ ++ifdef src ++EXTRA_CFLAGS += -I$(src)/.. -I$(src)/cesa -I$(src)/mvHal -I$(src)/mvHal/common -I$(src)/mvHal/kw_family -I$(src)/mvHal/mv_hal -I$(src)/mvHal/linux_oss -I$(src) ++endif ++ ++EXTRA_CFLAGS += -DMV_LINUX -DMV_CPU_LE -DMV_ARM -DMV_INCLUDE_CESA -DMV_INCLUDE_PEX -DMV_CACHE_COHERENCY=3 ++ifdef TOPDIR ++-include $(TOPDIR)/Rules.make ++endif ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/AES/mvAes.h linux-3.0.4/crypto/ocf/kirkwood/cesa/AES/mvAes.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/AES/mvAes.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/cesa/AES/mvAes.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,62 @@ ++/* mvAes.h v2.0 August '99 ++ * Reference ANSI C code ++ */ ++ ++/* AES Cipher header file for ANSI C Submissions ++ Lawrence E. Bassham III ++ Computer Security Division ++ National Institute of Standards and Technology ++ ++ April 15, 1998 ++ ++ This sample is to assist implementers developing to the Cryptographic ++API Profile for AES Candidate Algorithm Submissions. Please consult this ++document as a cross-reference. ++ ++ ANY CHANGES, WHERE APPROPRIATE, TO INFORMATION PROVIDED IN THIS FILE ++MUST BE DOCUMENTED. CHANGES ARE ONLY APPROPRIATE WHERE SPECIFIED WITH ++THE STRING "CHANGE POSSIBLE". FUNCTION CALLS AND THEIR PARAMETERS CANNOT ++BE CHANGED. STRUCTURES CAN BE ALTERED TO ALLOW IMPLEMENTERS TO INCLUDE ++IMPLEMENTATION SPECIFIC INFORMATION. ++*/ ++ ++/* Includes: ++ Standard include files ++*/ ++ ++#include "mvOs.h" ++ ++ ++/* Error Codes - CHANGE POSSIBLE: inclusion of additional error codes */ ++ ++/* Key direction is invalid, e.g., unknown value */ ++#define AES_BAD_KEY_DIR -1 ++ ++/* Key material not of correct length */ ++#define AES_BAD_KEY_MAT -2 ++ ++/* Key passed is not valid */ ++#define AES_BAD_KEY_INSTANCE -3 ++ ++/* Params struct passed to cipherInit invalid */ ++#define AES_BAD_CIPHER_MODE -4 ++ ++/* Cipher in wrong state (e.g., not initialized) */ ++#define AES_BAD_CIPHER_STATE -5 ++ ++#define AES_BAD_CIPHER_INSTANCE -7 ++ ++ ++/* Function protoypes */ ++/* CHANGED: makeKey(): parameter blockLen added ++ this parameter is absolutely necessary if you want to ++ setup the round keys in a variable block length setting ++ cipherInit(): parameter blockLen added (for obvious reasons) ++ */ ++int aesMakeKey(MV_U8 *expandedKey, MV_U8 *keyMaterial, int keyLen, int blockLen); ++int aesBlockEncrypt128(MV_U8 mode, MV_U8 *IV, MV_U8 *expandedKey, int keyLen, ++ MV_U32 *plain, int numBlocks, MV_U32 *cipher); ++int aesBlockDecrypt128(MV_U8 mode, MV_U8 *IV, MV_U8 *expandedKey, int keyLen, ++ MV_U32 *plain, int numBlocks, MV_U32 *cipher); ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.c linux-3.0.4/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,317 @@ ++/* rijndael-alg-ref.c v2.0 August '99 ++ * Reference ANSI C code ++ * authors: Paulo Barreto ++ * Vincent Rijmen, K.U.Leuven ++ * ++ * This code is placed in the public domain. ++ */ ++ ++#include "mvOs.h" ++ ++#include "mvAesAlg.h" ++ ++#include "mvAesBoxes.dat" ++ ++ ++MV_U8 mul1(MV_U8 aa, MV_U8 bb); ++void KeyAddition(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC], MV_U8 BC); ++void ShiftRow128Enc(MV_U8 a[4][MAXBC]); ++void ShiftRow128Dec(MV_U8 a[4][MAXBC]); ++void Substitution(MV_U8 a[4][MAXBC], MV_U8 box[256]); ++void MixColumn(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC]); ++void InvMixColumn(MV_U8 a[4][MAXBC]); ++ ++ ++#define mul(aa, bb) (mask[bb] & Alogtable[aa + Logtable[bb]]) ++ ++MV_U8 mul1(MV_U8 aa, MV_U8 bb) ++{ ++ return mask[bb] & Alogtable[aa + Logtable[bb]]; ++} ++ ++ ++void KeyAddition(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC], MV_U8 BC) ++{ ++ /* Exor corresponding text input and round key input bytes ++ */ ++ ((MV_U32*)(&(a[0][0])))[0] ^= ((MV_U32*)(&(rk[0][0])))[0]; ++ ((MV_U32*)(&(a[1][0])))[0] ^= ((MV_U32*)(&(rk[1][0])))[0]; ++ ((MV_U32*)(&(a[2][0])))[0] ^= ((MV_U32*)(&(rk[2][0])))[0]; ++ ((MV_U32*)(&(a[3][0])))[0] ^= ((MV_U32*)(&(rk[3][0])))[0]; ++ ++} ++ ++void ShiftRow128Enc(MV_U8 a[4][MAXBC]) { ++ /* Row 0 remains unchanged ++ * The other three rows are shifted a variable amount ++ */ ++ MV_U8 tmp[MAXBC]; ++ ++ tmp[0] = a[1][1]; ++ tmp[1] = a[1][2]; ++ tmp[2] = a[1][3]; ++ tmp[3] = a[1][0]; ++ ++ ((MV_U32*)(&(a[1][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; ++ /* ++ a[1][0] = tmp[0]; ++ a[1][1] = tmp[1]; ++ a[1][2] = tmp[2]; ++ a[1][3] = tmp[3]; ++ */ ++ tmp[0] = a[2][2]; ++ tmp[1] = a[2][3]; ++ tmp[2] = a[2][0]; ++ tmp[3] = a[2][1]; ++ ++ ((MV_U32*)(&(a[2][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; ++ /* ++ a[2][0] = tmp[0]; ++ a[2][1] = tmp[1]; ++ a[2][2] = tmp[2]; ++ a[2][3] = tmp[3]; ++ */ ++ tmp[0] = a[3][3]; ++ tmp[1] = a[3][0]; ++ tmp[2] = a[3][1]; ++ tmp[3] = a[3][2]; ++ ++ ((MV_U32*)(&(a[3][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; ++ /* ++ a[3][0] = tmp[0]; ++ a[3][1] = tmp[1]; ++ a[3][2] = tmp[2]; ++ a[3][3] = tmp[3]; ++ */ ++} ++ ++void ShiftRow128Dec(MV_U8 a[4][MAXBC]) { ++ /* Row 0 remains unchanged ++ * The other three rows are shifted a variable amount ++ */ ++ MV_U8 tmp[MAXBC]; ++ ++ tmp[0] = a[1][3]; ++ tmp[1] = a[1][0]; ++ tmp[2] = a[1][1]; ++ tmp[3] = a[1][2]; ++ ++ ((MV_U32*)(&(a[1][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; ++ /* ++ a[1][0] = tmp[0]; ++ a[1][1] = tmp[1]; ++ a[1][2] = tmp[2]; ++ a[1][3] = tmp[3]; ++ */ ++ ++ tmp[0] = a[2][2]; ++ tmp[1] = a[2][3]; ++ tmp[2] = a[2][0]; ++ tmp[3] = a[2][1]; ++ ++ ((MV_U32*)(&(a[2][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; ++ /* ++ a[2][0] = tmp[0]; ++ a[2][1] = tmp[1]; ++ a[2][2] = tmp[2]; ++ a[2][3] = tmp[3]; ++ */ ++ ++ tmp[0] = a[3][1]; ++ tmp[1] = a[3][2]; ++ tmp[2] = a[3][3]; ++ tmp[3] = a[3][0]; ++ ++ ((MV_U32*)(&(a[3][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; ++ /* ++ a[3][0] = tmp[0]; ++ a[3][1] = tmp[1]; ++ a[3][2] = tmp[2]; ++ a[3][3] = tmp[3]; ++ */ ++} ++ ++void Substitution(MV_U8 a[4][MAXBC], MV_U8 box[256]) { ++ /* Replace every byte of the input by the byte at that place ++ * in the nonlinear S-box ++ */ ++ int i, j; ++ ++ for(i = 0; i < 4; i++) ++ for(j = 0; j < 4; j++) a[i][j] = box[a[i][j]] ; ++} ++ ++void MixColumn(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC]) { ++ /* Mix the four bytes of every column in a linear way ++ */ ++ MV_U8 b[4][MAXBC]; ++ int i, j; ++ ++ for(j = 0; j < 4; j++){ ++ b[0][j] = mul(25,a[0][j]) ^ mul(1,a[1][j]) ^ a[2][j] ^ a[3][j]; ++ b[1][j] = mul(25,a[1][j]) ^ mul(1,a[2][j]) ^ a[3][j] ^ a[0][j]; ++ b[2][j] = mul(25,a[2][j]) ^ mul(1,a[3][j]) ^ a[0][j] ^ a[1][j]; ++ b[3][j] = mul(25,a[3][j]) ^ mul(1,a[0][j]) ^ a[1][j] ^ a[2][j]; ++ } ++ for(i = 0; i < 4; i++) ++ /*for(j = 0; j < BC; j++) a[i][j] = b[i][j];*/ ++ ((MV_U32*)(&(a[i][0])))[0] = ((MV_U32*)(&(b[i][0])))[0] ^ ((MV_U32*)(&(rk[i][0])))[0];; ++} ++ ++void InvMixColumn(MV_U8 a[4][MAXBC]) { ++ /* Mix the four bytes of every column in a linear way ++ * This is the opposite operation of Mixcolumn ++ */ ++ MV_U8 b[4][MAXBC]; ++ int i, j; ++ ++ for(j = 0; j < 4; j++){ ++ b[0][j] = mul(223,a[0][j]) ^ mul(104,a[1][j]) ^ mul(238,a[2][j]) ^ mul(199,a[3][j]); ++ b[1][j] = mul(223,a[1][j]) ^ mul(104,a[2][j]) ^ mul(238,a[3][j]) ^ mul(199,a[0][j]); ++ b[2][j] = mul(223,a[2][j]) ^ mul(104,a[3][j]) ^ mul(238,a[0][j]) ^ mul(199,a[1][j]); ++ b[3][j] = mul(223,a[3][j]) ^ mul(104,a[0][j]) ^ mul(238,a[1][j]) ^ mul(199,a[2][j]); ++ } ++ for(i = 0; i < 4; i++) ++ /*for(j = 0; j < BC; j++) a[i][j] = b[i][j];*/ ++ ((MV_U32*)(&(a[i][0])))[0] = ((MV_U32*)(&(b[i][0])))[0]; ++} ++ ++int rijndaelKeySched (MV_U8 k[4][MAXKC], int keyBits, int blockBits, MV_U8 W[MAXROUNDS+1][4][MAXBC]) ++{ ++ /* Calculate the necessary round keys ++ * The number of calculations depends on keyBits and blockBits ++ */ ++ int KC, BC, ROUNDS; ++ int i, j, t, rconpointer = 0; ++ MV_U8 tk[4][MAXKC]; ++ ++ switch (keyBits) { ++ case 128: KC = 4; break; ++ case 192: KC = 6; break; ++ case 256: KC = 8; break; ++ default : return (-1); ++ } ++ ++ switch (blockBits) { ++ case 128: BC = 4; break; ++ case 192: BC = 6; break; ++ case 256: BC = 8; break; ++ default : return (-2); ++ } ++ ++ switch (keyBits >= blockBits ? keyBits : blockBits) { ++ case 128: ROUNDS = 10; break; ++ case 192: ROUNDS = 12; break; ++ case 256: ROUNDS = 14; break; ++ default : return (-3); /* this cannot happen */ ++ } ++ ++ ++ for(j = 0; j < KC; j++) ++ for(i = 0; i < 4; i++) ++ tk[i][j] = k[i][j]; ++ t = 0; ++ /* copy values into round key array */ ++ for(j = 0; (j < KC) && (t < (ROUNDS+1)*BC); j++, t++) ++ for(i = 0; i < 4; i++) W[t / BC][i][t % BC] = tk[i][j]; ++ ++ while (t < (ROUNDS+1)*BC) { /* while not enough round key material calculated */ ++ /* calculate new values */ ++ for(i = 0; i < 4; i++) ++ tk[i][0] ^= S[tk[(i+1)%4][KC-1]]; ++ tk[0][0] ^= rcon[rconpointer++]; ++ ++ if (KC != 8) ++ for(j = 1; j < KC; j++) ++ for(i = 0; i < 4; i++) tk[i][j] ^= tk[i][j-1]; ++ else { ++ for(j = 1; j < KC/2; j++) ++ for(i = 0; i < 4; i++) tk[i][j] ^= tk[i][j-1]; ++ for(i = 0; i < 4; i++) tk[i][KC/2] ^= S[tk[i][KC/2 - 1]]; ++ for(j = KC/2 + 1; j < KC; j++) ++ for(i = 0; i < 4; i++) tk[i][j] ^= tk[i][j-1]; ++ } ++ /* copy values into round key array */ ++ for(j = 0; (j < KC) && (t < (ROUNDS+1)*BC); j++, t++) ++ for(i = 0; i < 4; i++) W[t / BC][i][t % BC] = tk[i][j]; ++ } ++ ++ return 0; ++} ++ ++ ++ ++int rijndaelEncrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds) ++{ ++ /* Encryption of one block. ++ */ ++ int r, BC, ROUNDS; ++ ++ BC = 4; ++ ROUNDS = rounds; ++ ++ /* begin with a key addition ++ */ ++ ++ KeyAddition(a,rk[0],BC); ++ ++ /* ROUNDS-1 ordinary rounds ++ */ ++ for(r = 1; r < ROUNDS; r++) { ++ Substitution(a,S); ++ ShiftRow128Enc(a); ++ MixColumn(a, rk[r]); ++ /*KeyAddition(a,rk[r],BC);*/ ++ } ++ ++ /* Last round is special: there is no MixColumn ++ */ ++ Substitution(a,S); ++ ShiftRow128Enc(a); ++ KeyAddition(a,rk[ROUNDS],BC); ++ ++ return 0; ++} ++ ++ ++int rijndaelDecrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds) ++{ ++ int r, BC, ROUNDS; ++ ++ BC = 4; ++ ROUNDS = rounds; ++ ++ /* To decrypt: apply the inverse operations of the encrypt routine, ++ * in opposite order ++ * ++ * (KeyAddition is an involution: it 's equal to its inverse) ++ * (the inverse of Substitution with table S is Substitution with the inverse table of S) ++ * (the inverse of Shiftrow is Shiftrow over a suitable distance) ++ */ ++ ++ /* First the special round: ++ * without InvMixColumn ++ * with extra KeyAddition ++ */ ++ KeyAddition(a,rk[ROUNDS],BC); ++ ShiftRow128Dec(a); ++ Substitution(a,Si); ++ ++ /* ROUNDS-1 ordinary rounds ++ */ ++ for(r = ROUNDS-1; r > 0; r--) { ++ KeyAddition(a,rk[r],BC); ++ InvMixColumn(a); ++ ShiftRow128Dec(a); ++ Substitution(a,Si); ++ ++ } ++ ++ /* End with the extra key addition ++ */ ++ ++ KeyAddition(a,rk[0],BC); ++ ++ return 0; ++} ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.h linux-3.0.4/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,19 @@ ++/* rijndael-alg-ref.h v2.0 August '99 ++ * Reference ANSI C code ++ * authors: Paulo Barreto ++ * Vincent Rijmen, K.U.Leuven ++ */ ++#ifndef __RIJNDAEL_ALG_H ++#define __RIJNDAEL_ALG_H ++ ++#define MAXBC (128/32) ++#define MAXKC (256/32) ++#define MAXROUNDS 14 ++ ++ ++int rijndaelKeySched (MV_U8 k[4][MAXKC], int keyBits, int blockBits, MV_U8 rk[MAXROUNDS+1][4][MAXBC]); ++ ++int rijndaelEncrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds); ++int rijndaelDecrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds); ++ ++#endif /* __RIJNDAEL_ALG_H */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/AES/mvAesApi.c linux-3.0.4/crypto/ocf/kirkwood/cesa/AES/mvAesApi.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/AES/mvAesApi.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/cesa/AES/mvAesApi.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,312 @@ ++/* rijndael-api-ref.c v2.1 April 2000 ++ * Reference ANSI C code ++ * authors: v2.0 Paulo Barreto ++ * Vincent Rijmen, K.U.Leuven ++ * v2.1 Vincent Rijmen, K.U.Leuven ++ * ++ * This code is placed in the public domain. ++ */ ++#include "mvOs.h" ++ ++#include "mvAes.h" ++#include "mvAesAlg.h" ++ ++ ++/* Defines: ++ Add any additional defines you need ++*/ ++ ++#define MODE_ECB 1 /* Are we ciphering in ECB mode? */ ++#define MODE_CBC 2 /* Are we ciphering in CBC mode? */ ++#define MODE_CFB1 3 /* Are we ciphering in 1-bit CFB mode? */ ++ ++ ++int aesMakeKey(MV_U8 *expandedKey, MV_U8 *keyMaterial, int keyLen, int blockLen) ++{ ++ MV_U8 W[MAXROUNDS+1][4][MAXBC]; ++ MV_U8 k[4][MAXKC]; ++ MV_U8 j; ++ int i, rounds, KC; ++ ++ if (expandedKey == NULL) ++ { ++ return AES_BAD_KEY_INSTANCE; ++ } ++ ++ if (!((keyLen == 128) || (keyLen == 192) || (keyLen == 256))) ++ { ++ return AES_BAD_KEY_MAT; ++ } ++ ++ if (keyMaterial == NULL) ++ { ++ return AES_BAD_KEY_MAT; ++ } ++ ++ /* initialize key schedule: */ ++ for(i=0; i= 3) ++MV_U32 cesaChainLength = 0; ++int chainReqNum = 0; ++MV_U32 chainIndex = 0; ++MV_CESA_REQ* pNextActiveChain = 0; ++MV_CESA_REQ* pEndCurrChain = 0; ++MV_BOOL isFirstReq = MV_TRUE; ++#endif ++ ++static INLINE MV_U8* mvCesaSramAddrGet(void) ++{ ++#ifdef MV_CESA_NO_SRAM ++ return (MV_U8*)cesaSramVirtPtr; ++#else ++ return (MV_U8*)cesaCryptEngBase; ++#endif /* MV_CESA_NO_SRAM */ ++} ++ ++static INLINE MV_ULONG mvCesaSramVirtToPhys(void* pDev, MV_U8* pSramVirt) ++{ ++#ifdef MV_CESA_NO_SRAM ++ return (MV_ULONG)mvOsIoVirtToPhy(NULL, pSramVirt); ++#else ++ return (MV_ULONG)pSramVirt; ++#endif /* MV_CESA_NO_SRAM */ ++} ++ ++/* Internal Function prototypes */ ++ ++static INLINE void mvCesaSramDescrBuild(MV_U32 config, int frag, ++ int cryptoOffset, int ivOffset, int cryptoLength, ++ int macOffset, int digestOffset, int macLength, int macTotalLen, ++ MV_CESA_REQ *pCesaReq, MV_DMA_DESC* pDmaDesc); ++ ++static INLINE void mvCesaSramSaUpdate(short sid, MV_DMA_DESC *pDmaDesc); ++ ++static INLINE int mvCesaDmaCopyPrepare(MV_CESA_MBUF* pMbuf, MV_U8* pSramBuf, ++ MV_DMA_DESC* pDmaDesc, MV_BOOL isToMbuf, ++ int offset, int copySize, MV_BOOL skipFlush); ++ ++static void mvCesaHmacIvGet(MV_CESA_MAC_MODE macMode, unsigned char key[], int keyLength, ++ unsigned char innerIV[], unsigned char outerIV[]); ++ ++static MV_STATUS mvCesaFragAuthComplete(MV_CESA_REQ* pReq, MV_CESA_SA* pSA, ++ int macDataSize); ++ ++static MV_CESA_COMMAND* mvCesaCtrModeInit(void); ++ ++static MV_STATUS mvCesaCtrModePrepare(MV_CESA_COMMAND *pCtrModeCmd, MV_CESA_COMMAND *pCmd); ++static MV_STATUS mvCesaCtrModeComplete(MV_CESA_COMMAND *pOrgCmd, MV_CESA_COMMAND *pCmd); ++static void mvCesaCtrModeFinish(MV_CESA_COMMAND *pCmd); ++ ++static INLINE MV_STATUS mvCesaReqProcess(MV_CESA_REQ* pReq); ++static MV_STATUS mvCesaFragReqProcess(MV_CESA_REQ* pReq, MV_U8 frag); ++ ++static INLINE MV_STATUS mvCesaParamCheck(MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, MV_U8* pFixOffset); ++static INLINE MV_STATUS mvCesaFragParamCheck(MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd); ++ ++static INLINE void mvCesaFragSizeFind(MV_CESA_SA* pSA, MV_CESA_REQ* pReq, ++ int cryptoOffset, int macOffset, ++ int* pCopySize, int* pCryptoDataSize, int* pMacDataSize); ++static MV_STATUS mvCesaMbufCacheUnmap(MV_CESA_MBUF* pMbuf, int offset, int size); ++ ++ ++/* Go to the next request in the request queue */ ++static INLINE MV_CESA_REQ* MV_CESA_REQ_NEXT_PTR(MV_CESA_REQ* pReq) ++{ ++ if(pReq == pCesaReqLast) ++ return pCesaReqFirst; ++ ++ return pReq+1; ++} ++ ++#if (MV_CESA_VERSION >= 3) ++/* Go to the previous request in the request queue */ ++static INLINE MV_CESA_REQ* MV_CESA_REQ_PREV_PTR(MV_CESA_REQ* pReq) ++{ ++ if(pReq == pCesaReqFirst) ++ return pCesaReqLast; ++ ++ return pReq-1; ++} ++ ++#endif ++ ++ ++static INLINE void mvCesaReqProcessStart(MV_CESA_REQ* pReq) ++{ ++ int frag; ++ ++#if (MV_CESA_VERSION >= 3) ++ pReq->state = MV_CESA_CHAIN; ++#else ++ pReq->state = MV_CESA_PROCESS; ++#endif ++ cesaStats.startCount++; ++ ++ if(pReq->fragMode == MV_CESA_FRAG_NONE) ++ { ++ frag = 0; ++ } ++ else ++ { ++ frag = pReq->frags.nextFrag; ++ pReq->frags.nextFrag++; ++ } ++#if (MV_CESA_VERSION >= 2) ++ /* Enable TDMA engine */ ++ MV_REG_WRITE(MV_CESA_TDMA_CURR_DESC_PTR_REG, 0); ++ MV_REG_WRITE(MV_CESA_TDMA_NEXT_DESC_PTR_REG, ++ (MV_U32)mvCesaVirtToPhys(&pReq->dmaDescBuf, pReq->dma[frag].pDmaFirst)); ++#else ++ /* Enable IDMA engine */ ++ MV_REG_WRITE(IDMA_CURR_DESC_PTR_REG(0), 0); ++ MV_REG_WRITE(IDMA_NEXT_DESC_PTR_REG(0), ++ (MV_U32)mvCesaVirtToPhys(&pReq->dmaDescBuf, pReq->dma[frag].pDmaFirst)); ++#endif /* MV_CESA_VERSION >= 2 */ ++ ++#if defined(MV_BRIDGE_SYNC_REORDER) ++ mvOsBridgeReorderWA(); ++#endif ++ ++ /* Start Accelerator */ ++ MV_REG_WRITE(MV_CESA_CMD_REG, MV_CESA_CMD_CHAN_ENABLE_MASK); ++} ++ ++ ++/******************************************************************************* ++* mvCesaHalInit - Initialize the CESA driver ++* ++* DESCRIPTION: ++* This function initialize the CESA driver. ++* 1) Session database ++* 2) Request queue ++* 4) DMA descriptor lists - one list per request. Each list ++* has MV_CESA_MAX_DMA_DESC descriptors. ++* ++* INPUT: ++* numOfSession - maximum number of supported sessions ++* queueDepth - number of elements in the request queue. ++* pSramBase - virtual address of Sram ++* osHandle - A handle used by the OS to allocate memory for the ++* module (Passed to the OS Services layer) ++* ++* RETURN: ++* MV_OK - Success ++* MV_NO_RESOURCE - Fail, can't allocate resources: ++* Session database, request queue, ++* DMA descriptors list, LRU cache database. ++* MV_NOT_ALIGNED - Sram base address is not 8 byte aligned. ++* ++*******************************************************************************/ ++MV_STATUS mvCesaHalInit (int numOfSession, int queueDepth, char* pSramBase, MV_U32 cryptEngBase, ++ void *osHandle) ++{ ++ int i, req; ++ MV_U32 descOffsetReg, configReg; ++ MV_CESA_SRAM_SA *pSramSA; ++ ++ ++ mvOsPrintf("mvCesaInit: sessions=%d, queue=%d, pSram=%p\n", ++ numOfSession, queueDepth, pSramBase); ++ ++ cesaOsHandle = osHandle; ++ /* Create Session database */ ++ pCesaSAD = mvOsMalloc(sizeof(MV_CESA_SA)*numOfSession); ++ if(pCesaSAD == NULL) ++ { ++ mvOsPrintf("mvCesaInit: Can't allocate %u bytes for %d SAs\n", ++ sizeof(MV_CESA_SA)*numOfSession, numOfSession); ++ mvCesaFinish(); ++ return MV_NO_RESOURCE; ++ } ++ memset(pCesaSAD, 0, sizeof(MV_CESA_SA)*numOfSession); ++ cesaMaxSA = numOfSession; ++ ++ /* Allocate imag of sramSA in the DRAM */ ++ cesaSramSaBuf.bufSize = sizeof(MV_CESA_SRAM_SA)*numOfSession + ++ CPU_D_CACHE_LINE_SIZE; ++ ++ cesaSramSaBuf.bufVirtPtr = mvOsIoCachedMalloc(osHandle,cesaSramSaBuf.bufSize, ++ &cesaSramSaBuf.bufPhysAddr, ++ &cesaSramSaBuf.memHandle); ++ ++ if(cesaSramSaBuf.bufVirtPtr == NULL) ++ { ++ mvOsPrintf("mvCesaInit: Can't allocate %d bytes for sramSA structures\n", ++ cesaSramSaBuf.bufSize); ++ mvCesaFinish(); ++ return MV_NO_RESOURCE; ++ } ++ memset(cesaSramSaBuf.bufVirtPtr, 0, cesaSramSaBuf.bufSize); ++ pSramSA = (MV_CESA_SRAM_SA*)MV_ALIGN_UP((MV_ULONG)cesaSramSaBuf.bufVirtPtr, ++ CPU_D_CACHE_LINE_SIZE); ++ for(i=0; i= 3) ++ cesaChainLength = MAX_CESA_CHAIN_LENGTH; ++#endif ++ /* pSramBase must be 8 byte aligned */ ++ if( MV_IS_NOT_ALIGN((MV_ULONG)pSramBase, 8) ) ++ { ++ mvOsPrintf("mvCesaInit: pSramBase (%p) must be 8 byte aligned\n", ++ pSramBase); ++ mvCesaFinish(); ++ return MV_NOT_ALIGNED; ++ } ++ cesaSramVirtPtr = (MV_CESA_SRAM_MAP*)pSramBase; ++ ++ cesaCryptEngBase = cryptEngBase; ++ ++ /*memset(cesaSramVirtPtr, 0, sizeof(MV_CESA_SRAM_MAP));*/ ++ ++ /* Clear registers */ ++ MV_REG_WRITE( MV_CESA_CFG_REG, 0); ++ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); ++ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, 0); ++ ++ /* Initialize DMA descriptor lists for all requests in Request queue */ ++ descOffsetReg = configReg = 0; ++ for(req=0; reqcesaDescBuf.bufSize = sizeof(MV_CESA_DESC)*MV_CESA_MAX_REQ_FRAGS + ++ CPU_D_CACHE_LINE_SIZE; ++ ++ pReq->cesaDescBuf.bufVirtPtr = ++ mvOsIoCachedMalloc(osHandle,pReq->cesaDescBuf.bufSize, ++ &pReq->cesaDescBuf.bufPhysAddr, ++ &pReq->cesaDescBuf.memHandle); ++ ++ if(pReq->cesaDescBuf.bufVirtPtr == NULL) ++ { ++ mvOsPrintf("mvCesaInit: req=%d, Can't allocate %d bytes for CESA descriptors\n", ++ req, pReq->cesaDescBuf.bufSize); ++ mvCesaFinish(); ++ return MV_NO_RESOURCE; ++ } ++ memset(pReq->cesaDescBuf.bufVirtPtr, 0, pReq->cesaDescBuf.bufSize); ++ pReq->pCesaDesc = (MV_CESA_DESC*)MV_ALIGN_UP((MV_ULONG)pReq->cesaDescBuf.bufVirtPtr, ++ CPU_D_CACHE_LINE_SIZE); ++ ++ pReq->dmaDescBuf.bufSize = sizeof(MV_DMA_DESC)*MV_CESA_MAX_DMA_DESC*MV_CESA_MAX_REQ_FRAGS + ++ CPU_D_CACHE_LINE_SIZE; ++ ++ pReq->dmaDescBuf.bufVirtPtr = ++ mvOsIoCachedMalloc(osHandle,pReq->dmaDescBuf.bufSize, ++ &pReq->dmaDescBuf.bufPhysAddr, ++ &pReq->dmaDescBuf.memHandle); ++ ++ if(pReq->dmaDescBuf.bufVirtPtr == NULL) ++ { ++ mvOsPrintf("mvCesaInit: req=%d, Can't allocate %d bytes for DMA descriptor list\n", ++ req, pReq->dmaDescBuf.bufSize); ++ mvCesaFinish(); ++ return MV_NO_RESOURCE; ++ } ++ memset(pReq->dmaDescBuf.bufVirtPtr, 0, pReq->dmaDescBuf.bufSize); ++ pDmaDesc = (MV_DMA_DESC*)MV_ALIGN_UP((MV_ULONG)pReq->dmaDescBuf.bufVirtPtr, ++ CPU_D_CACHE_LINE_SIZE); ++ ++ for(frag=0; fragdma[frag]; ++ ++ pDma->pDmaFirst = pDmaDesc; ++ pDma->pDmaLast = NULL; ++ ++ for(i=0; ipDmaFirst[i].phyNextDescPtr = ++ MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, &pDmaDesc[i+1])); ++ } ++ pDma->pDmaFirst[i].phyNextDescPtr = 0; ++ mvOsCacheFlush(NULL, &pDma->pDmaFirst[0], MV_CESA_MAX_DMA_DESC*sizeof(MV_DMA_DESC)); ++ ++ pDmaDesc += MV_CESA_MAX_DMA_DESC; ++ } ++ } ++ /*mvCesaCryptoIvSet(NULL, MV_CESA_MAX_IV_LENGTH);*/ ++ descOffsetReg = (MV_U16)((MV_U8*)&cesaSramVirtPtr->desc - mvCesaSramAddrGet()); ++ MV_REG_WRITE(MV_CESA_CHAN_DESC_OFFSET_REG, descOffsetReg); ++ ++ configReg |= (MV_CESA_CFG_WAIT_DMA_MASK | MV_CESA_CFG_ACT_DMA_MASK); ++#if (MV_CESA_VERSION >= 3) ++ configReg |= MV_CESA_CFG_CHAIN_MODE_MASK; ++#endif ++ ++#if (MV_CESA_VERSION >= 2) ++ /* Initialize TDMA engine */ ++ MV_REG_WRITE(MV_CESA_TDMA_CTRL_REG, MV_CESA_TDMA_CTRL_VALUE); ++ MV_REG_WRITE(MV_CESA_TDMA_BYTE_COUNT_REG, 0); ++ MV_REG_WRITE(MV_CESA_TDMA_CURR_DESC_PTR_REG, 0); ++#else ++ /* Initialize IDMA #0 engine */ ++ MV_REG_WRITE(IDMA_CTRL_LOW_REG(0), 0); ++ MV_REG_WRITE(IDMA_BYTE_COUNT_REG(0), 0); ++ MV_REG_WRITE(IDMA_CURR_DESC_PTR_REG(0), 0); ++ MV_REG_WRITE(IDMA_CTRL_HIGH_REG(0), ICCHR_ENDIAN_LITTLE ++#ifdef MV_CPU_LE ++ | ICCHR_DESC_BYTE_SWAP_EN ++#endif ++ ); ++ /* Clear Cause Byte of IDMA channel to be used */ ++ MV_REG_WRITE( IDMA_CAUSE_REG, ~ICICR_CAUSE_MASK_ALL(0)); ++ MV_REG_WRITE(IDMA_CTRL_LOW_REG(0), MV_CESA_IDMA_CTRL_LOW_VALUE); ++#endif /* (MV_CESA_VERSION >= 2) */ ++ ++ /* Set CESA configuration registers */ ++ MV_REG_WRITE( MV_CESA_CFG_REG, configReg); ++ mvCesaDebugStatsClear(); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCesaFinish - Shutdown the CESA driver ++* ++* DESCRIPTION: ++* This function shutdown the CESA driver and free all allocted resources. ++* ++* INPUT: None ++* ++* RETURN: ++* MV_OK - Success ++* Other - Fail ++* ++*******************************************************************************/ ++MV_STATUS mvCesaFinish (void) ++{ ++ int req; ++ MV_CESA_REQ* pReq; ++ ++ mvOsPrintf("mvCesaFinish: \n"); ++ ++ cesaSramVirtPtr = NULL; ++ ++ /* Free all resources: DMA list, etc. */ ++ for(req=0; reqdmaDescBuf.bufVirtPtr != NULL) ++ { ++ mvOsIoCachedFree(cesaOsHandle,pReq->dmaDescBuf.bufSize, ++ pReq->dmaDescBuf.bufPhysAddr, ++ pReq->dmaDescBuf.bufVirtPtr, ++ pReq->dmaDescBuf.memHandle); ++ } ++ if(pReq->cesaDescBuf.bufVirtPtr != NULL) ++ { ++ mvOsIoCachedFree(cesaOsHandle,pReq->cesaDescBuf.bufSize, ++ pReq->cesaDescBuf.bufPhysAddr, ++ pReq->cesaDescBuf.bufVirtPtr, ++ pReq->cesaDescBuf.memHandle); ++ } ++ } ++#if (MV_CESA_VERSION < 2) ++ MV_REG_WRITE(IDMA_CTRL_LOW_REG(0), 0); ++#endif /* (MV_CESA_VERSION < 2) */ ++ ++ /* Free request queue */ ++ if(pCesaReqFirst != NULL) ++ { ++ mvOsFree(pCesaReqFirst); ++ pCesaReqFirst = pCesaReqLast = NULL; ++ pCesaReqEmpty = pCesaReqProcess = NULL; ++ cesaQueueDepth = cesaReqResources = 0; ++ } ++ /* Free SA database */ ++ if(pCesaSAD != NULL) ++ { ++ mvOsFree(pCesaSAD); ++ pCesaSAD = NULL; ++ cesaMaxSA = 0; ++ } ++ MV_REG_WRITE( MV_CESA_CFG_REG, 0); ++ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); ++ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, 0); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCesaCryptoIvSet - Set IV value for Crypto algorithm working in CBC mode ++* ++* DESCRIPTION: ++* This function set IV value using by Crypto algorithms in CBC mode. ++* Each channel has its own IV value. ++* This function gets IV value from the caller. If no IV value passed from ++* the caller or only part of IV passed, the function will init the rest part ++* of IV value (or the whole IV) by random value. ++* ++* INPUT: ++* MV_U8* pIV - Pointer to IV value supplied by user. If pIV==NULL ++* the function will generate random IV value. ++* int ivSize - size (in bytes) of IV provided by user. If ivSize is ++* smaller than maximum IV size, the function will complete ++* IV by random value. ++* ++* RETURN: ++* MV_OK - Success ++* Other - Fail ++* ++*******************************************************************************/ ++MV_STATUS mvCesaCryptoIvSet(MV_U8* pIV, int ivSize) ++{ ++ MV_U8* pSramIV; ++#if defined(MV646xx) ++ mvOsPrintf("mvCesaCryptoIvSet: ERR. shouldn't use this call on MV64660\n"); ++#endif ++ pSramIV = cesaSramVirtPtr->cryptoIV; ++ if(ivSize > MV_CESA_MAX_IV_LENGTH) ++ { ++ mvOsPrintf("mvCesaCryptoIvSet: ivSize (%d) is too large\n", ivSize); ++ ivSize = MV_CESA_MAX_IV_LENGTH; ++ } ++ if(pIV != NULL) ++ { ++ memcpy(pSramIV, pIV, ivSize); ++ ivSize = MV_CESA_MAX_IV_LENGTH - ivSize; ++ pSramIV += ivSize; ++ } ++ ++ while(ivSize > 0) ++ { ++ int size, mv_random = mvOsRand(); ++ ++ size = MV_MIN(ivSize, sizeof(mv_random)); ++ memcpy(pSramIV, (void*)&mv_random, size); ++ ++ pSramIV += size; ++ ivSize -= size; ++ } ++/* ++ mvOsCacheFlush(NULL, cesaSramVirtPtr->cryptoIV, ++ MV_CESA_MAX_IV_LENGTH); ++ mvOsCacheInvalidate(NULL, cesaSramVirtPtr->cryptoIV, ++ MV_CESA_MAX_IV_LENGTH); ++*/ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCesaSessionOpen - Open new uni-directional crypto session ++* ++* DESCRIPTION: ++* This function open new session. ++* ++* INPUT: ++* MV_CESA_OPEN_SESSION *pSession - pointer to new session input parameters ++* ++* OUTPUT: ++* short *pSid - session ID, should be used for all future ++* requests over this session. ++* ++* RETURN: ++* MV_OK - Session opend successfully. ++* MV_FULL - All sessions are in use, no free place in ++* SA database. ++* MV_BAD_PARAM - One of session input parameters is invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvCesaSessionOpen(MV_CESA_OPEN_SESSION *pSession, short* pSid) ++{ ++ short sid; ++ MV_U32 config = 0; ++ int digestSize; ++ ++ cesaStats.openedCount++; ++ ++ /* Find free entry in SAD */ ++ for(sid=0; sidoperation >= MV_CESA_MAX_OPERATION) ++ { ++ mvOsPrintf("mvCesaSessionOpen: Unexpected operation %d\n", ++ pSession->operation); ++ return MV_BAD_PARAM; ++ } ++ config |= (pSession->operation << MV_CESA_OPERATION_OFFSET); ++ ++ if( (pSession->direction != MV_CESA_DIR_ENCODE) && ++ (pSession->direction != MV_CESA_DIR_DECODE) ) ++ { ++ mvOsPrintf("mvCesaSessionOpen: Unexpected direction %d\n", ++ pSession->direction); ++ return MV_BAD_PARAM; ++ } ++ config |= (pSession->direction << MV_CESA_DIRECTION_BIT); ++ /* Clear SA entry */ ++ /* memset(&pCesaSAD[sid], 0, sizeof(pCesaSAD[sid])); */ ++ ++ /* Check AUTH parameters and update SA entry */ ++ if(pSession->operation != MV_CESA_CRYPTO_ONLY) ++ { ++ /* For HMAC (MD5 and SHA1) - Maximum Key size is 64 bytes */ ++ if( (pSession->macMode == MV_CESA_MAC_HMAC_MD5) || ++ (pSession->macMode == MV_CESA_MAC_HMAC_SHA1) ) ++ { ++ if(pSession->macKeyLength > MV_CESA_MAX_MAC_KEY_LENGTH) ++ { ++ mvOsPrintf("mvCesaSessionOpen: macKeyLength %d is too large\n", ++ pSession->macKeyLength); ++ return MV_BAD_PARAM; ++ } ++ mvCesaHmacIvGet(pSession->macMode, pSession->macKey, pSession->macKeyLength, ++ pCesaSAD[sid].pSramSA->macInnerIV, ++ pCesaSAD[sid].pSramSA->macOuterIV); ++ pCesaSAD[sid].macKeyLength = pSession->macKeyLength; ++ } ++ switch(pSession->macMode) ++ { ++ case MV_CESA_MAC_MD5: ++ case MV_CESA_MAC_HMAC_MD5: ++ digestSize = MV_CESA_MD5_DIGEST_SIZE; ++ break; ++ ++ case MV_CESA_MAC_SHA1: ++ case MV_CESA_MAC_HMAC_SHA1: ++ digestSize = MV_CESA_SHA1_DIGEST_SIZE; ++ break; ++ ++ default: ++ mvOsPrintf("mvCesaSessionOpen: Unexpected macMode %d\n", ++ pSession->macMode); ++ return MV_BAD_PARAM; ++ } ++ config |= (pSession->macMode << MV_CESA_MAC_MODE_OFFSET); ++ ++ /* Supported digest sizes: MD5 - 16 bytes (128 bits), */ ++ /* SHA1 - 20 bytes (160 bits) or 12 bytes (96 bits) for both */ ++ if( (pSession->digestSize != digestSize) && (pSession->digestSize != 12)) ++ { ++ mvOsPrintf("mvCesaSessionOpen: Unexpected digest size %d\n", ++ pSession->digestSize); ++ mvOsPrintf("\t Valid values [bytes]: MD5-16, SHA1-20, Both-12\n"); ++ return MV_BAD_PARAM; ++ } ++ pCesaSAD[sid].digestSize = pSession->digestSize; ++ ++ if(pCesaSAD[sid].digestSize == 12) ++ { ++ /* Set MV_CESA_MAC_DIGEST_SIZE_BIT if digest size is 96 bits */ ++ config |= (MV_CESA_MAC_DIGEST_96B << MV_CESA_MAC_DIGEST_SIZE_BIT); ++ } ++ } ++ ++ /* Check CRYPTO parameters and update SA entry */ ++ if(pSession->operation != MV_CESA_MAC_ONLY) ++ { ++ switch(pSession->cryptoAlgorithm) ++ { ++ case MV_CESA_CRYPTO_DES: ++ pCesaSAD[sid].cryptoKeyLength = MV_CESA_DES_KEY_LENGTH; ++ pCesaSAD[sid].cryptoBlockSize = MV_CESA_DES_BLOCK_SIZE; ++ break; ++ ++ case MV_CESA_CRYPTO_3DES: ++ pCesaSAD[sid].cryptoKeyLength = MV_CESA_3DES_KEY_LENGTH; ++ pCesaSAD[sid].cryptoBlockSize = MV_CESA_DES_BLOCK_SIZE; ++ /* Only EDE mode is supported */ ++ config |= (MV_CESA_CRYPTO_3DES_EDE << ++ MV_CESA_CRYPTO_3DES_MODE_BIT); ++ break; ++ ++ case MV_CESA_CRYPTO_AES: ++ switch(pSession->cryptoKeyLength) ++ { ++ case 16: ++ pCesaSAD[sid].cryptoKeyLength = MV_CESA_AES_128_KEY_LENGTH; ++ config |= (MV_CESA_CRYPTO_AES_KEY_128 << ++ MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET); ++ break; ++ ++ case 24: ++ pCesaSAD[sid].cryptoKeyLength = MV_CESA_AES_192_KEY_LENGTH; ++ config |= (MV_CESA_CRYPTO_AES_KEY_192 << ++ MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET); ++ break; ++ ++ case 32: ++ default: ++ pCesaSAD[sid].cryptoKeyLength = MV_CESA_AES_256_KEY_LENGTH; ++ config |= (MV_CESA_CRYPTO_AES_KEY_256 << ++ MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET); ++ break; ++ } ++ pCesaSAD[sid].cryptoBlockSize = MV_CESA_AES_BLOCK_SIZE; ++ break; ++ ++ default: ++ mvOsPrintf("mvCesaSessionOpen: Unexpected cryptoAlgorithm %d\n", ++ pSession->cryptoAlgorithm); ++ return MV_BAD_PARAM; ++ } ++ config |= (pSession->cryptoAlgorithm << MV_CESA_CRYPTO_ALG_OFFSET); ++ ++ if(pSession->cryptoKeyLength != pCesaSAD[sid].cryptoKeyLength) ++ { ++ mvOsPrintf("cesaSessionOpen: Wrong CryptoKeySize %d != %d\n", ++ pSession->cryptoKeyLength, pCesaSAD[sid].cryptoKeyLength); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Copy Crypto key */ ++ if( (pSession->cryptoAlgorithm == MV_CESA_CRYPTO_AES) && ++ (pSession->direction == MV_CESA_DIR_DECODE)) ++ { ++ /* Crypto Key for AES decode is computed from original key material */ ++ /* and depend on cryptoKeyLength (128/192/256 bits) */ ++ aesMakeKey(pCesaSAD[sid].pSramSA->cryptoKey, pSession->cryptoKey, ++ pSession->cryptoKeyLength*8, MV_CESA_AES_BLOCK_SIZE*8); ++ } ++ else ++ { ++ /*panic("mvCesaSessionOpen2");*/ ++ memcpy(pCesaSAD[sid].pSramSA->cryptoKey, pSession->cryptoKey, ++ pCesaSAD[sid].cryptoKeyLength); ++ ++ } ++ ++ switch(pSession->cryptoMode) ++ { ++ case MV_CESA_CRYPTO_ECB: ++ pCesaSAD[sid].cryptoIvSize = 0; ++ break; ++ ++ case MV_CESA_CRYPTO_CBC: ++ pCesaSAD[sid].cryptoIvSize = pCesaSAD[sid].cryptoBlockSize; ++ break; ++ ++ case MV_CESA_CRYPTO_CTR: ++ /* Supported only for AES algorithm */ ++ if(pSession->cryptoAlgorithm != MV_CESA_CRYPTO_AES) ++ { ++ mvOsPrintf("mvCesaSessionOpen: CRYPTO CTR mode supported for AES only\n"); ++ return MV_BAD_PARAM; ++ } ++ pCesaSAD[sid].cryptoIvSize = 0; ++ pCesaSAD[sid].ctrMode = 1; ++ /* Replace to ECB mode for HW */ ++ pSession->cryptoMode = MV_CESA_CRYPTO_ECB; ++ break; ++ ++ default: ++ mvOsPrintf("mvCesaSessionOpen: Unexpected cryptoMode %d\n", ++ pSession->cryptoMode); ++ return MV_BAD_PARAM; ++ } ++ ++ config |= (pSession->cryptoMode << MV_CESA_CRYPTO_MODE_BIT); ++ } ++ pCesaSAD[sid].config = config; ++ ++ mvOsCacheFlush(NULL, pCesaSAD[sid].pSramSA, sizeof(MV_CESA_SRAM_SA)); ++ if(pSid != NULL) ++ *pSid = sid; ++ ++ pCesaSAD[sid].valid = 1; ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCesaSessionClose - Close active crypto session ++* ++* DESCRIPTION: ++* This function closes existing session ++* ++* INPUT: ++* short sid - Unique identifier of the session to be closed ++* ++* RETURN: ++* MV_OK - Session closed successfully. ++* MV_BAD_PARAM - Session identifier is out of valid range. ++* MV_NOT_FOUND - There is no active session with such ID. ++* ++*******************************************************************************/ ++MV_STATUS mvCesaSessionClose(short sid) ++{ ++ cesaStats.closedCount++; ++ ++ if(sid >= cesaMaxSA) ++ { ++ mvOsPrintf("CESA Error: sid (%d) is too big\n", sid); ++ return MV_BAD_PARAM; ++ } ++ if(pCesaSAD[sid].valid == 0) ++ { ++ mvOsPrintf("CESA Warning: Session (sid=%d) is invalid\n", sid); ++ return MV_NOT_FOUND; ++ } ++ if(cesaLastSid == sid) ++ cesaLastSid = -1; ++ ++ pCesaSAD[sid].valid = 0; ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCesaAction - Perform crypto operation ++* ++* DESCRIPTION: ++* This function set new CESA request FIFO queue for further HW processing. ++* The function checks request parameters before set new request to the queue. ++* If one of the CESA channels is ready for processing the request will be ++* passed to HW. When request processing is finished the CESA interrupt will ++* be generated by HW. The caller should call mvCesaReadyGet() function to ++* complete request processing and get result. ++* ++* INPUT: ++* MV_CESA_COMMAND *pCmd - pointer to new CESA request. ++* It includes pointers to Source and Destination ++* buffers, session identifier get from ++* mvCesaSessionOpen() function, pointer to caller ++* private data and all needed crypto parameters. ++* ++* RETURN: ++* MV_OK - request successfully added to request queue ++* and will be processed. ++* MV_NO_MORE - request successfully added to request queue and will ++* be processed, but request queue became Full and next ++* request will not be accepted. ++* MV_NO_RESOURCE - request queue is FULL and the request can not ++* be processed. ++* MV_OUT_OF_CPU_MEM - memory allocation needed for request processing is ++* failed. Request can not be processed. ++* MV_NOT_ALLOWED - This mixed request (CRYPTO+MAC) can not be processed ++* as one request and should be splitted for two requests: ++* CRYPTO_ONLY and MAC_ONLY. ++* MV_BAD_PARAM - One of the request parameters is out of valid range. ++* The request can not be processed. ++* ++*******************************************************************************/ ++MV_STATUS mvCesaAction (MV_CESA_COMMAND *pCmd) ++{ ++ MV_STATUS status; ++ MV_CESA_REQ* pReq = pCesaReqEmpty; ++ int sid = pCmd->sessionId; ++ MV_CESA_SA* pSA = &pCesaSAD[sid]; ++#if (MV_CESA_VERSION >= 3) ++ MV_CESA_REQ* pFromReq; ++ MV_CESA_REQ* pToReq; ++#endif ++ cesaStats.reqCount++; ++ ++ /* Check that the request queue is not FULL */ ++ if(cesaReqResources == 0) ++ return MV_NO_RESOURCE; ++ ++ if( (sid >= cesaMaxSA) || (!pSA->valid) ) ++ { ++ mvOsPrintf("CESA Action Error: Session sid=%d is INVALID\n", sid); ++ return MV_BAD_PARAM; ++ } ++ pSA->count++; ++ ++ if(pSA->ctrMode) ++ { ++ /* AES in CTR mode can't be mixed with Authentication */ ++ if( (pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) ++ { ++ mvOsPrintf("mvCesaAction : CRYPTO CTR mode can't be mixed with AUTH\n"); ++ return MV_NOT_ALLOWED; ++ } ++ /* All other request parameters should not be checked because key stream */ ++ /* (not user data) processed by AES HW engine */ ++ pReq->pOrgCmd = pCmd; ++ /* Allocate temporary pCmd structure for Key stream */ ++ pCmd = mvCesaCtrModeInit(); ++ if(pCmd == NULL) ++ return MV_OUT_OF_CPU_MEM; ++ ++ /* Prepare Key stream */ ++ mvCesaCtrModePrepare(pCmd, pReq->pOrgCmd); ++ pReq->fixOffset = 0; ++ } ++ else ++ { ++ /* Check request parameters and calculae fixOffset */ ++ status = mvCesaParamCheck(pSA, pCmd, &pReq->fixOffset); ++ if(status != MV_OK) ++ { ++ return status; ++ } ++ } ++ pReq->pCmd = pCmd; ++ ++ /* Check if the packet need fragmentation */ ++ if(pCmd->pSrc->mbufSize <= sizeof(cesaSramVirtPtr->buf) ) ++ { ++ /* request size is smaller than single buffer size */ ++ pReq->fragMode = MV_CESA_FRAG_NONE; ++ ++ /* Prepare NOT fragmented packets */ ++ status = mvCesaReqProcess(pReq); ++ if(status != MV_OK) ++ { ++ mvOsPrintf("CesaReady: ReqProcess error: pReq=%p, status=0x%x\n", ++ pReq, status); ++ } ++#if (MV_CESA_VERSION >= 3) ++ pReq->frags.numFrag = 1; ++#endif ++ } ++ else ++ { ++ MV_U8 frag = 0; ++ ++ /* request size is larger than buffer size - needs fragmentation */ ++ ++ /* Check restrictions for processing fragmented packets */ ++ status = mvCesaFragParamCheck(pSA, pCmd); ++ if(status != MV_OK) ++ return status; ++ ++ pReq->fragMode = MV_CESA_FRAG_FIRST; ++ pReq->frags.nextFrag = 0; ++ ++ /* Prepare Process Fragmented packets */ ++ while(pReq->fragMode != MV_CESA_FRAG_LAST) ++ { ++ if(frag >= MV_CESA_MAX_REQ_FRAGS) ++ { ++ mvOsPrintf("mvCesaAction Error: Too large request frag=%d\n", frag); ++ return MV_OUT_OF_CPU_MEM; ++ } ++ status = mvCesaFragReqProcess(pReq, frag); ++ if(status == MV_OK) { ++#if (MV_CESA_VERSION >= 3) ++ if(frag) { ++ pReq->dma[frag-1].pDmaLast->phyNextDescPtr = ++ MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, pReq->dma[frag].pDmaFirst)); ++ mvOsCacheFlush(NULL, pReq->dma[frag-1].pDmaLast, sizeof(MV_DMA_DESC)); ++ } ++#endif ++ frag++; ++ } ++ } ++ pReq->frags.numFrag = frag; ++#if (MV_CESA_VERSION >= 3) ++ if(chainReqNum) { ++ chainReqNum += pReq->frags.numFrag; ++ if(chainReqNum >= MAX_CESA_CHAIN_LENGTH) ++ chainReqNum = MAX_CESA_CHAIN_LENGTH; ++ } ++#endif ++ } ++ ++ pReq->state = MV_CESA_PENDING; ++ ++ pCesaReqEmpty = MV_CESA_REQ_NEXT_PTR(pReq); ++ cesaReqResources -= 1; ++ ++/* #ifdef CESA_DEBUG */ ++ if( (cesaQueueDepth - cesaReqResources) > cesaStats.maxReqCount) ++ cesaStats.maxReqCount = (cesaQueueDepth - cesaReqResources); ++/* #endif CESA_DEBUG */ ++ ++ cesaLastSid = sid; ++ ++#if (MV_CESA_VERSION >= 3) ++ /* Are we within chain bounderies and follows the first request ? */ ++ if((chainReqNum > 0) && (chainReqNum < MAX_CESA_CHAIN_LENGTH)) { ++ if(chainIndex) { ++ pFromReq = MV_CESA_REQ_PREV_PTR(pReq); ++ pToReq = pReq; ++ pReq->state = MV_CESA_CHAIN; ++ /* assume concatenating is possible */ ++ pFromReq->dma[pFromReq->frags.numFrag-1].pDmaLast->phyNextDescPtr = ++ MV_32BIT_LE(mvCesaVirtToPhys(&pToReq->dmaDescBuf, pToReq->dma[0].pDmaFirst)); ++ mvOsCacheFlush(NULL, pFromReq->dma[pFromReq->frags.numFrag-1].pDmaLast, sizeof(MV_DMA_DESC)); ++ ++ /* align active & next pointers */ ++ if(pNextActiveChain->state != MV_CESA_PENDING) ++ pEndCurrChain = pNextActiveChain = MV_CESA_REQ_NEXT_PTR(pReq); ++ } ++ else { /* we have only one chain, start new one */ ++ chainReqNum = 0; ++ chainIndex++; ++ /* align active & next pointers */ ++ if(pNextActiveChain->state != MV_CESA_PENDING) ++ pEndCurrChain = pNextActiveChain = pReq; ++ } ++ } ++ else { ++ /* In case we concatenate full chain */ ++ if(chainReqNum == MAX_CESA_CHAIN_LENGTH) { ++ chainIndex++; ++ if(pNextActiveChain->state != MV_CESA_PENDING) ++ pEndCurrChain = pNextActiveChain = pReq; ++ chainReqNum = 0; ++ } ++ ++ pReq = pCesaReqProcess; ++ if(pReq->state == MV_CESA_PENDING) { ++ pNextActiveChain = pReq; ++ pEndCurrChain = MV_CESA_REQ_NEXT_PTR(pReq); ++ /* Start Process new request */ ++ mvCesaReqProcessStart(pReq); ++ } ++ } ++ ++ chainReqNum++; ++ ++ if((chainIndex < MAX_CESA_CHAIN_LENGTH) && (chainReqNum > cesaStats.maxChainUsage)) ++ cesaStats.maxChainUsage = chainReqNum; ++ ++#else ++ ++ /* Check status of CESA channels and process requests if possible */ ++ pReq = pCesaReqProcess; ++ if(pReq->state == MV_CESA_PENDING) ++ { ++ /* Start Process new request */ ++ mvCesaReqProcessStart(pReq); ++ } ++#endif ++ /* If request queue became FULL - return MV_NO_MORE */ ++ if(cesaReqResources == 0) ++ return MV_NO_MORE; ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvCesaReadyGet - Get crypto request that processing is finished ++* ++* DESCRIPTION: ++* This function complete request processing and return ready request to ++* caller. To don't miss interrupts the caller must call this function ++* while MV_OK or MV_TERMINATE values returned. ++* ++* INPUT: ++* MV_U32 chanMap - map of CESA channels finished thier job ++* accordingly with CESA Cause register. ++* MV_CESA_RESULT* pResult - pointer to structure contains information ++* about ready request. It includes pointer to ++* user private structure "pReqPrv", session identifier ++* for this request "sessionId" and return code. ++* Return code set to MV_FAIL if calculated digest value ++* on decode direction is different than digest value ++* in the packet. ++* ++* RETURN: ++* MV_OK - Success, ready request is returned. ++* MV_NOT_READY - Next request is not ready yet. New interrupt will ++* be generated for futher request processing. ++* MV_EMPTY - There is no more request for processing. ++* MV_BUSY - Fragmented request is not ready yet. ++* MV_TERMINATE - Call this function once more to complete processing ++* of fragmented request. ++* ++*******************************************************************************/ ++MV_STATUS mvCesaReadyGet(MV_CESA_RESULT* pResult) ++{ ++ MV_STATUS status, readyStatus = MV_NOT_READY; ++ MV_U32 statusReg; ++ MV_CESA_REQ* pReq; ++ MV_CESA_SA* pSA; ++ ++#if (MV_CESA_VERSION >= 3) ++ if(isFirstReq == MV_TRUE) { ++ if(chainIndex == 0) ++ chainReqNum = 0; ++ ++ isFirstReq = MV_FALSE; ++ ++ if(pNextActiveChain->state == MV_CESA_PENDING) { ++ /* Start request Process */ ++ mvCesaReqProcessStart(pNextActiveChain); ++ pEndCurrChain = pNextActiveChain; ++ if(chainIndex > 0) ++ chainIndex--; ++ /* Update pNextActiveChain to next chain head */ ++ while(pNextActiveChain->state == MV_CESA_CHAIN) ++ pNextActiveChain = MV_CESA_REQ_NEXT_PTR(pNextActiveChain); ++ } ++ } ++ ++ /* Check if there are more processed requests - can we remove pEndCurrChain ??? */ ++ if(pCesaReqProcess == pEndCurrChain) { ++ isFirstReq = MV_TRUE; ++ pEndCurrChain = pNextActiveChain; ++#else ++ if(pCesaReqProcess->state != MV_CESA_PROCESS) { ++#endif ++ return MV_EMPTY; ++ } ++ ++#ifdef CESA_DEBUG ++ statusReg = MV_REG_READ(MV_CESA_STATUS_REG); ++ if( statusReg & MV_CESA_STATUS_ACTIVE_MASK ) ++ { ++ mvOsPrintf("mvCesaReadyGet: Not Ready, Status = 0x%x\n", statusReg); ++ cesaStats.notReadyCount++; ++ return MV_NOT_READY; ++ } ++#endif /* CESA_DEBUG */ ++ ++ cesaStats.readyCount++; ++ ++ pReq = pCesaReqProcess; ++ pSA = &pCesaSAD[pReq->pCmd->sessionId]; ++ ++ pResult->retCode = MV_OK; ++ if(pReq->fragMode != MV_CESA_FRAG_NONE) ++ { ++ MV_U8* pNewDigest; ++ int frag; ++#if (MV_CESA_VERSION >= 3) ++ pReq->frags.nextFrag = 1; ++ while(pReq->frags.nextFrag <= pReq->frags.numFrag) { ++#endif ++ frag = (pReq->frags.nextFrag - 1); ++ ++ /* Restore DMA descriptor list */ ++ pReq->dma[frag].pDmaLast->phyNextDescPtr = ++ MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, &pReq->dma[frag].pDmaLast[1])); ++ pReq->dma[frag].pDmaLast = NULL; ++ ++ /* Special processing for finished fragmented request */ ++ if(pReq->frags.nextFrag >= pReq->frags.numFrag) ++ { ++ mvCesaMbufCacheUnmap(pReq->pCmd->pDst, 0, pReq->pCmd->pDst->mbufSize); ++ ++ /* Fragmented packet is ready */ ++ if( (pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) ++ { ++ int macDataSize = pReq->pCmd->macLength - pReq->frags.macSize; ++ ++ if(macDataSize != 0) ++ { ++ /* Calculate all other blocks by SW */ ++ mvCesaFragAuthComplete(pReq, pSA, macDataSize); ++ } ++ ++ /* Copy new digest from SRAM to the Destination buffer */ ++ pNewDigest = cesaSramVirtPtr->buf + pReq->frags.newDigestOffset; ++ status = mvCesaCopyToMbuf(pNewDigest, pReq->pCmd->pDst, ++ pReq->pCmd->digestOffset, pSA->digestSize); ++ ++ /* For decryption: Compare new digest value with original one */ ++ if((pSA->config & MV_CESA_DIRECTION_MASK) == ++ (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) ++ { ++ if( memcmp(pNewDigest, pReq->frags.orgDigest, pSA->digestSize) != 0) ++ { ++/* ++ mvOsPrintf("Digest error: chan=%d, newDigest=%p, orgDigest=%p, status = 0x%x\n", ++ chan, pNewDigest, pReq->frags.orgDigest, MV_REG_READ(MV_CESA_STATUS_REG)); ++*/ ++ /* Signiture verification is failed */ ++ pResult->retCode = MV_FAIL; ++ } ++ } ++ } ++ readyStatus = MV_OK; ++ } ++#if (MV_CESA_VERSION >= 3) ++ pReq->frags.nextFrag++; ++ } ++#endif ++ } ++ else ++ { ++ mvCesaMbufCacheUnmap(pReq->pCmd->pDst, 0, pReq->pCmd->pDst->mbufSize); ++ ++ /* Restore DMA descriptor list */ ++ pReq->dma[0].pDmaLast->phyNextDescPtr = ++ MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, &pReq->dma[0].pDmaLast[1])); ++ pReq->dma[0].pDmaLast = NULL; ++ if( ((pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) && ++ ((pSA->config & MV_CESA_DIRECTION_MASK) == ++ (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) ) ++ { ++ /* For AUTH on decode : Check Digest result in Status register */ ++ statusReg = MV_REG_READ(MV_CESA_STATUS_REG); ++ if(statusReg & MV_CESA_STATUS_DIGEST_ERR_MASK) ++ { ++/* ++ mvOsPrintf("Digest error: chan=%d, status = 0x%x\n", ++ chan, statusReg); ++*/ ++ /* Signiture verification is failed */ ++ pResult->retCode = MV_FAIL; ++ } ++ } ++ readyStatus = MV_OK; ++ } ++ ++ if(readyStatus == MV_OK) ++ { ++ /* If Request is ready - Prepare pResult structure */ ++ pResult->pReqPrv = pReq->pCmd->pReqPrv; ++ pResult->sessionId = pReq->pCmd->sessionId; ++ ++ pReq->state = MV_CESA_IDLE; ++ pCesaReqProcess = MV_CESA_REQ_NEXT_PTR(pReq); ++ cesaReqResources++; ++ ++ if(pSA->ctrMode) ++ { ++ /* For AES CTR mode - complete processing and free allocated resources */ ++ mvCesaCtrModeComplete(pReq->pOrgCmd, pReq->pCmd); ++ mvCesaCtrModeFinish(pReq->pCmd); ++ pReq->pOrgCmd = NULL; ++ } ++ } ++ ++#if (MV_CESA_VERSION < 3) ++ if(pCesaReqProcess->state == MV_CESA_PROCESS) ++ { ++ /* Start request Process */ ++ mvCesaReqProcessStart(pCesaReqProcess); ++ if(readyStatus == MV_NOT_READY) ++ readyStatus = MV_BUSY; ++ } ++ else if(pCesaReqProcess != pCesaReqEmpty) ++ { ++ /* Start process new request from the queue */ ++ mvCesaReqProcessStart(pCesaReqProcess); ++ } ++#endif ++ return readyStatus; ++} ++ ++/***************** Functions to work with CESA_MBUF structure ******************/ ++ ++/******************************************************************************* ++* mvCesaMbufOffset - Locate offset in the Mbuf structure ++* ++* DESCRIPTION: ++* This function locates offset inside Multi-Bufeer structure. ++* It get fragment number and place in the fragment where the offset ++* is located. ++* ++* ++* INPUT: ++* MV_CESA_MBUF* pMbuf - Pointer to multi-buffer structure ++* int offset - Offset from the beginning of the data presented by ++* the Mbuf structure. ++* ++* OUTPUT: ++* int* pBufOffset - Offset from the beginning of the fragment where ++* the offset is located. ++* ++* RETURN: ++* int - Number of fragment, where the offset is located\ ++* ++*******************************************************************************/ ++int mvCesaMbufOffset(MV_CESA_MBUF* pMbuf, int offset, int* pBufOffset) ++{ ++ int frag = 0; ++ ++ while(offset > 0) ++ { ++ if(frag >= pMbuf->numFrags) ++ { ++ mvOsPrintf("mvCesaMbufOffset: Error: frag (%d) > numFrags (%d)\n", ++ frag, pMbuf->numFrags); ++ return MV_INVALID; ++ } ++ if(offset < pMbuf->pFrags[frag].bufSize) ++ { ++ break; ++ } ++ offset -= pMbuf->pFrags[frag].bufSize; ++ frag++; ++ } ++ if(pBufOffset != NULL) ++ *pBufOffset = offset; ++ ++ return frag; ++} ++ ++/******************************************************************************* ++* mvCesaCopyFromMbuf - Copy data from the Mbuf structure to continuous buffer ++* ++* DESCRIPTION: ++* ++* ++* INPUT: ++* MV_U8* pDstBuf - Pointer to continuous buffer, where data is ++* copied to. ++* MV_CESA_MBUF* pSrcMbuf - Pointer to multi-buffer structure where data is ++* copied from. ++* int offset - Offset in the Mbuf structure where located first ++* byte of data should be copied. ++* int size - Size of data should be copied ++* ++* RETURN: ++* MV_OK - Success, all data is copied successfully. ++* MV_OUT_OF_RANGE - Failed, offset is out of Multi-buffer data range. ++* No data is copied. ++* MV_EMPTY - Multi-buffer structure has not enough data to copy ++* Data from the offset to end of Mbuf data is copied. ++* ++*******************************************************************************/ ++MV_STATUS mvCesaCopyFromMbuf(MV_U8* pDstBuf, MV_CESA_MBUF* pSrcMbuf, ++ int offset, int size) ++{ ++ int frag, fragOffset, bufSize; ++ MV_U8* pBuf; ++ ++ if(size == 0) ++ return MV_OK; ++ ++ frag = mvCesaMbufOffset(pSrcMbuf, offset, &fragOffset); ++ if(frag == MV_INVALID) ++ { ++ mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); ++ return MV_OUT_OF_RANGE; ++ } ++ ++ bufSize = pSrcMbuf->pFrags[frag].bufSize - fragOffset; ++ pBuf = pSrcMbuf->pFrags[frag].bufVirtPtr + fragOffset; ++ while(MV_TRUE) ++ { ++ if(size <= bufSize) ++ { ++ memcpy(pDstBuf, pBuf, size); ++ return MV_OK; ++ } ++ memcpy(pDstBuf, pBuf, bufSize); ++ size -= bufSize; ++ frag++; ++ pDstBuf += bufSize; ++ if(frag >= pSrcMbuf->numFrags) ++ break; ++ ++ bufSize = pSrcMbuf->pFrags[frag].bufSize; ++ pBuf = pSrcMbuf->pFrags[frag].bufVirtPtr; ++ } ++ mvOsPrintf("mvCesaCopyFromMbuf: Mbuf is EMPTY - %d bytes isn't copied\n", ++ size); ++ return MV_EMPTY; ++} ++ ++/******************************************************************************* ++* mvCesaCopyToMbuf - Copy data from continuous buffer to the Mbuf structure ++* ++* DESCRIPTION: ++* ++* ++* INPUT: ++* MV_U8* pSrcBuf - Pointer to continuous buffer, where data is ++* copied from. ++* MV_CESA_MBUF* pDstMbuf - Pointer to multi-buffer structure where data is ++* copied to. ++* int offset - Offset in the Mbuf structure where located first ++* byte of data should be copied. ++* int size - Size of data should be copied ++* ++* RETURN: ++* MV_OK - Success, all data is copied successfully. ++* MV_OUT_OF_RANGE - Failed, offset is out of Multi-buffer data range. ++* No data is copied. ++* MV_FULL - Multi-buffer structure has not enough place to copy ++* all data. Data from the offset to end of Mbuf data ++* is copied. ++* ++*******************************************************************************/ ++MV_STATUS mvCesaCopyToMbuf(MV_U8* pSrcBuf, MV_CESA_MBUF* pDstMbuf, ++ int offset, int size) ++{ ++ int frag, fragOffset, bufSize; ++ MV_U8* pBuf; ++ ++ if(size == 0) ++ return MV_OK; ++ ++ frag = mvCesaMbufOffset(pDstMbuf, offset, &fragOffset); ++ if(frag == MV_INVALID) ++ { ++ mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); ++ return MV_OUT_OF_RANGE; ++ } ++ ++ bufSize = pDstMbuf->pFrags[frag].bufSize - fragOffset; ++ pBuf = pDstMbuf->pFrags[frag].bufVirtPtr + fragOffset; ++ while(MV_TRUE) ++ { ++ if(size <= bufSize) ++ { ++ memcpy(pBuf, pSrcBuf, size); ++ return MV_OK; ++ } ++ memcpy(pBuf, pSrcBuf, bufSize); ++ size -= bufSize; ++ frag++; ++ pSrcBuf += bufSize; ++ if(frag >= pDstMbuf->numFrags) ++ break; ++ ++ bufSize = pDstMbuf->pFrags[frag].bufSize; ++ pBuf = pDstMbuf->pFrags[frag].bufVirtPtr; ++ } ++ mvOsPrintf("mvCesaCopyToMbuf: Mbuf is FULL - %d bytes isn't copied\n", ++ size); ++ return MV_FULL; ++} ++ ++/******************************************************************************* ++* mvCesaMbufCopy - Copy data from one Mbuf structure to the other Mbuf structure ++* ++* DESCRIPTION: ++* ++* ++* INPUT: ++* ++* MV_CESA_MBUF* pDstMbuf - Pointer to multi-buffer structure where data is ++* copied to. ++* int dstMbufOffset - Offset in the dstMbuf structure where first byte ++* of data should be copied to. ++* MV_CESA_MBUF* pSrcMbuf - Pointer to multi-buffer structure where data is ++* copied from. ++* int srcMbufOffset - Offset in the srcMbuf structure where first byte ++* of data should be copied from. ++* int size - Size of data should be copied ++* ++* RETURN: ++* MV_OK - Success, all data is copied successfully. ++* MV_OUT_OF_RANGE - Failed, srcMbufOffset or dstMbufOffset is out of ++* srcMbuf or dstMbuf structure correspondently. ++* No data is copied. ++* MV_BAD_SIZE - srcMbuf or dstMbuf structure is too small to copy ++* all data. Partial data is copied ++* ++*******************************************************************************/ ++MV_STATUS mvCesaMbufCopy(MV_CESA_MBUF* pMbufDst, int dstMbufOffset, ++ MV_CESA_MBUF* pMbufSrc, int srcMbufOffset, int size) ++{ ++ int srcFrag, dstFrag, srcSize, dstSize, srcOffset, dstOffset; ++ int copySize; ++ MV_U8 *pSrc, *pDst; ++ ++ if(size == 0) ++ return MV_OK; ++ ++ srcFrag = mvCesaMbufOffset(pMbufSrc, srcMbufOffset, &srcOffset); ++ if(srcFrag == MV_INVALID) ++ { ++ mvOsPrintf("CESA srcMbuf Error: offset (%d) out of range\n", srcMbufOffset); ++ return MV_OUT_OF_RANGE; ++ } ++ pSrc = pMbufSrc->pFrags[srcFrag].bufVirtPtr + srcOffset; ++ srcSize = pMbufSrc->pFrags[srcFrag].bufSize - srcOffset; ++ ++ dstFrag = mvCesaMbufOffset(pMbufDst, dstMbufOffset, &dstOffset); ++ if(dstFrag == MV_INVALID) ++ { ++ mvOsPrintf("CESA dstMbuf Error: offset (%d) out of range\n", dstMbufOffset); ++ return MV_OUT_OF_RANGE; ++ } ++ pDst = pMbufDst->pFrags[dstFrag].bufVirtPtr + dstOffset; ++ dstSize = pMbufDst->pFrags[dstFrag].bufSize - dstOffset; ++ ++ while(size > 0) ++ { ++ copySize = MV_MIN(srcSize, dstSize); ++ if(size <= copySize) ++ { ++ memcpy(pDst, pSrc, size); ++ return MV_OK; ++ } ++ memcpy(pDst, pSrc, copySize); ++ size -= copySize; ++ srcSize -= copySize; ++ dstSize -= copySize; ++ ++ if(srcSize == 0) ++ { ++ srcFrag++; ++ if(srcFrag >= pMbufSrc->numFrags) ++ break; ++ ++ pSrc = pMbufSrc->pFrags[srcFrag].bufVirtPtr; ++ srcSize = pMbufSrc->pFrags[srcFrag].bufSize; ++ } ++ ++ if(dstSize == 0) ++ { ++ dstFrag++; ++ if(dstFrag >= pMbufDst->numFrags) ++ break; ++ ++ pDst = pMbufDst->pFrags[dstFrag].bufVirtPtr; ++ dstSize = pMbufDst->pFrags[dstFrag].bufSize; ++ } ++ } ++ mvOsPrintf("mvCesaMbufCopy: BAD size - %d bytes isn't copied\n", ++ size); ++ ++ return MV_BAD_SIZE; ++} ++ ++static MV_STATUS mvCesaMbufCacheUnmap(MV_CESA_MBUF* pMbuf, int offset, int size) ++{ ++ int frag, fragOffset, bufSize; ++ MV_U8* pBuf; ++ ++ if(size == 0) ++ return MV_OK; ++ ++ frag = mvCesaMbufOffset(pMbuf, offset, &fragOffset); ++ if(frag == MV_INVALID) ++ { ++ mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); ++ return MV_OUT_OF_RANGE; ++ } ++ ++ bufSize = pMbuf->pFrags[frag].bufSize - fragOffset; ++ pBuf = pMbuf->pFrags[frag].bufVirtPtr + fragOffset; ++ while(MV_TRUE) ++ { ++ if(size <= bufSize) ++ { ++ mvOsCacheUnmap(NULL, mvOsIoVirtToPhy(NULL, pBuf), size); ++ return MV_OK; ++ } ++ ++ mvOsCacheUnmap(NULL, mvOsIoVirtToPhy(NULL, pBuf), bufSize); ++ size -= bufSize; ++ frag++; ++ if(frag >= pMbuf->numFrags) ++ break; ++ ++ bufSize = pMbuf->pFrags[frag].bufSize; ++ pBuf = pMbuf->pFrags[frag].bufVirtPtr; ++ } ++ mvOsPrintf("%s: Mbuf is FULL - %d bytes isn't Unmapped\n", ++ __FUNCTION__, size); ++ return MV_FULL; ++} ++ ++ ++/*************************************** Local Functions ******************************/ ++ ++/******************************************************************************* ++* mvCesaFragReqProcess - Process fragmented request ++* ++* DESCRIPTION: ++* This function processes a fragment of fragmented request (First, Middle or Last) ++* ++* ++* INPUT: ++* MV_CESA_REQ* pReq - Pointer to the request in the request queue. ++* ++* RETURN: ++* MV_OK - The fragment is successfully passed to HW for processing. ++* MV_TERMINATE - Means, that HW finished its work on this packet and no more ++* interrupts will be generated for this request. ++* Function mvCesaReadyGet() must be called to complete request ++* processing and get request result. ++* ++*******************************************************************************/ ++static MV_STATUS mvCesaFragReqProcess(MV_CESA_REQ* pReq, MV_U8 frag) ++{ ++ int i, copySize, cryptoDataSize, macDataSize, sid; ++ int cryptoIvOffset, digestOffset; ++ MV_U32 config; ++ MV_CESA_COMMAND* pCmd = pReq->pCmd; ++ MV_CESA_SA* pSA; ++ MV_CESA_MBUF* pMbuf; ++ MV_DMA_DESC* pDmaDesc = pReq->dma[frag].pDmaFirst; ++ MV_U8* pSramBuf = cesaSramVirtPtr->buf; ++ int macTotalLen = 0; ++ int fixOffset, cryptoOffset, macOffset; ++ ++ cesaStats.fragCount++; ++ ++ sid = pReq->pCmd->sessionId; ++ ++ pSA = &pCesaSAD[sid]; ++ ++ cryptoIvOffset = digestOffset = 0; ++ i = macDataSize = 0; ++ cryptoDataSize = 0; ++ ++ /* First fragment processing */ ++ if(pReq->fragMode == MV_CESA_FRAG_FIRST) ++ { ++ /* pReq->frags monitors processing of fragmented request between fragments */ ++ pReq->frags.bufOffset = 0; ++ pReq->frags.cryptoSize = 0; ++ pReq->frags.macSize = 0; ++ ++ config = pSA->config | (MV_CESA_FRAG_FIRST << MV_CESA_FRAG_MODE_OFFSET); ++ ++ /* fixOffset can be not equal to zero only for FIRST fragment */ ++ fixOffset = pReq->fixOffset; ++ /* For FIRST fragment crypto and mac offsets are taken from pCmd */ ++ cryptoOffset = pCmd->cryptoOffset; ++ macOffset = pCmd->macOffset; ++ ++ copySize = sizeof(cesaSramVirtPtr->buf) - pReq->fixOffset; ++ ++ /* Find fragment size: Must meet all requirements for CRYPTO and MAC ++ * cryptoDataSize - size of data will be encrypted/decrypted in this fragment ++ * macDataSize - size of data will be signed/verified in this fragment ++ * copySize - size of data will be copied from srcMbuf to SRAM and ++ * back to dstMbuf for this fragment ++ */ ++ mvCesaFragSizeFind(pSA, pReq, cryptoOffset, macOffset, ++ ©Size, &cryptoDataSize, &macDataSize); ++ ++ if( (pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) ++ { ++ /* CryptoIV special processing */ ++ if( (pSA->config & MV_CESA_CRYPTO_MODE_MASK) == ++ (MV_CESA_CRYPTO_CBC << MV_CESA_CRYPTO_MODE_BIT) ) ++ { ++ /* In CBC mode for encode direction when IV from user */ ++ if( (pCmd->ivFromUser) && ++ ((pSA->config & MV_CESA_DIRECTION_MASK) == ++ (MV_CESA_DIR_ENCODE << MV_CESA_DIRECTION_BIT)) ) ++ { ++ ++ /* For Crypto Encode in CBC mode HW always takes IV from SRAM IVPointer, ++ * (not from IVBufPointer). So when ivFromUser==1, we should copy IV from user place ++ * in the buffer to SRAM IVPointer ++ */ ++ i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->cryptoIV, &pDmaDesc[i], ++ MV_FALSE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); ++ } ++ ++ /* Special processing when IV is not located in the first fragment */ ++ if(pCmd->ivOffset > (copySize - pSA->cryptoIvSize)) ++ { ++ /* Prepare dummy place for cryptoIV in SRAM */ ++ cryptoIvOffset = cesaSramVirtPtr->tempCryptoIV - mvCesaSramAddrGet(); ++ ++ /* For Decryption: Copy IV value from pCmd->ivOffset to Special SRAM place */ ++ if((pSA->config & MV_CESA_DIRECTION_MASK) == ++ (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) ++ { ++ i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->tempCryptoIV, &pDmaDesc[i], ++ MV_FALSE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); ++ } ++ else ++ { ++ /* For Encryption when IV is NOT from User: */ ++ /* Copy IV from SRAM to buffer (pCmd->ivOffset) */ ++ if(pCmd->ivFromUser == 0) ++ { ++ /* copy IV value from cryptoIV to Buffer (pCmd->ivOffset) */ ++ i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->cryptoIV, &pDmaDesc[i], ++ MV_TRUE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); ++ } ++ } ++ } ++ else ++ { ++ cryptoIvOffset = pCmd->ivOffset; ++ } ++ } ++ } ++ ++ if( (pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) ++ { ++ /* MAC digest special processing on Decode direction */ ++ if((pSA->config & MV_CESA_DIRECTION_MASK) == ++ (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) ++ { ++ /* Save digest from pCmd->digestOffset */ ++ mvCesaCopyFromMbuf(pReq->frags.orgDigest, ++ pCmd->pSrc, pCmd->digestOffset, pSA->digestSize); ++ ++ /* If pCmd->digestOffset is not located on the first */ ++ if(pCmd->digestOffset > (copySize - pSA->digestSize)) ++ { ++ MV_U8 digestZero[MV_CESA_MAX_DIGEST_SIZE]; ++ ++ /* Set zeros to pCmd->digestOffset (DRAM) */ ++ memset(digestZero, 0, MV_CESA_MAX_DIGEST_SIZE); ++ mvCesaCopyToMbuf(digestZero, pCmd->pSrc, pCmd->digestOffset, pSA->digestSize); ++ ++ /* Prepare dummy place for digest in SRAM */ ++ digestOffset = cesaSramVirtPtr->tempDigest - mvCesaSramAddrGet(); ++ } ++ else ++ { ++ digestOffset = pCmd->digestOffset; ++ } ++ } ++ } ++ /* Update SA in SRAM */ ++ if(cesaLastSid != sid) ++ { ++ mvCesaSramSaUpdate(sid, &pDmaDesc[i]); ++ i++; ++ } ++ ++ pReq->fragMode = MV_CESA_FRAG_MIDDLE; ++ } ++ else ++ { ++ /* Continue fragment */ ++ fixOffset = 0; ++ cryptoOffset = 0; ++ macOffset = 0; ++ if( (pCmd->pSrc->mbufSize - pReq->frags.bufOffset) <= sizeof(cesaSramVirtPtr->buf)) ++ { ++ /* Last fragment */ ++ config = pSA->config | (MV_CESA_FRAG_LAST << MV_CESA_FRAG_MODE_OFFSET); ++ pReq->fragMode = MV_CESA_FRAG_LAST; ++ copySize = pCmd->pSrc->mbufSize - pReq->frags.bufOffset; ++ ++ if( (pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) ++ { ++ macDataSize = pCmd->macLength - pReq->frags.macSize; ++ ++ /* If pCmd->digestOffset is not located on last fragment */ ++ if(pCmd->digestOffset < pReq->frags.bufOffset) ++ { ++ /* Prepare dummy place for digest in SRAM */ ++ digestOffset = cesaSramVirtPtr->tempDigest - mvCesaSramAddrGet(); ++ } ++ else ++ { ++ digestOffset = pCmd->digestOffset - pReq->frags.bufOffset; ++ } ++ pReq->frags.newDigestOffset = digestOffset; ++ macTotalLen = pCmd->macLength; ++ ++ /* HW can't calculate the Digest correctly for fragmented packets ++ * in the following cases: ++ * - MV88F5182 || ++ * - MV88F5181L when total macLength more that 16 Kbytes || ++ * - total macLength more that 64 Kbytes ++ */ ++ if( (mvCtrlModelGet() == MV_5182_DEV_ID) || ++ ( (mvCtrlModelGet() == MV_5181_DEV_ID) && ++ (mvCtrlRevGet() >= MV_5181L_A0_REV) && ++ (pCmd->macLength >= (1 << 14)) ) ) ++ { ++ return MV_TERMINATE; ++ } ++ } ++ if( (pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET) ) ++ { ++ cryptoDataSize = pCmd->cryptoLength - pReq->frags.cryptoSize; ++ } ++ ++ /* cryptoIvOffset - don't care */ ++ } ++ else ++ { ++ /* WA for MV88F5182 SHA1 and MD5 fragmentation mode */ ++ if( (mvCtrlModelGet() == MV_5182_DEV_ID) && ++ (((pSA->config & MV_CESA_MAC_MODE_MASK) == ++ (MV_CESA_MAC_MD5 << MV_CESA_MAC_MODE_OFFSET)) || ++ ((pSA->config & MV_CESA_MAC_MODE_MASK) == ++ (MV_CESA_MAC_SHA1 << MV_CESA_MAC_MODE_OFFSET))) ) ++ { ++ pReq->frags.newDigestOffset = cesaSramVirtPtr->tempDigest - mvCesaSramAddrGet(); ++ pReq->fragMode = MV_CESA_FRAG_LAST; ++ ++ return MV_TERMINATE; ++ } ++ /* Middle fragment */ ++ config = pSA->config | (MV_CESA_FRAG_MIDDLE << MV_CESA_FRAG_MODE_OFFSET); ++ copySize = sizeof(cesaSramVirtPtr->buf); ++ /* digestOffset and cryptoIvOffset - don't care */ ++ ++ /* Find fragment size */ ++ mvCesaFragSizeFind(pSA, pReq, cryptoOffset, macOffset, ++ ©Size, &cryptoDataSize, &macDataSize); ++ } ++ } ++ /********* Prepare DMA descriptors to copy from pSrc to SRAM *********/ ++ pMbuf = pCmd->pSrc; ++ i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], ++ MV_FALSE, pReq->frags.bufOffset, copySize, pCmd->skipFlush); ++ ++ /* Prepare CESA descriptor to copy from DRAM to SRAM by DMA */ ++ mvCesaSramDescrBuild(config, frag, ++ cryptoOffset + fixOffset, cryptoIvOffset + fixOffset, ++ cryptoDataSize, macOffset + fixOffset, ++ digestOffset + fixOffset, macDataSize, macTotalLen, ++ pReq, &pDmaDesc[i]); ++ i++; ++ ++ /* Add special descriptor Ownership for CPU */ ++ pDmaDesc[i].byteCnt = 0; ++ pDmaDesc[i].phySrcAdd = 0; ++ pDmaDesc[i].phyDestAdd = 0; ++ i++; ++ ++ /********* Prepare DMA descriptors to copy from SRAM to pDst *********/ ++ pMbuf = pCmd->pDst; ++ i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], ++ MV_TRUE, pReq->frags.bufOffset, copySize, pCmd->skipFlush); ++ ++ /* Next field of Last DMA descriptor must be NULL */ ++ pDmaDesc[i-1].phyNextDescPtr = 0; ++ pReq->dma[frag].pDmaLast = &pDmaDesc[i-1]; ++ mvOsCacheFlush(NULL, pReq->dma[frag].pDmaFirst, ++ i*sizeof(MV_DMA_DESC)); ++ ++ /*mvCesaDebugDescriptor(&cesaSramVirtPtr->desc[frag]);*/ ++ ++ pReq->frags.bufOffset += copySize; ++ pReq->frags.cryptoSize += cryptoDataSize; ++ pReq->frags.macSize += macDataSize; ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvCesaReqProcess - Process regular (Non-fragmented) request ++* ++* DESCRIPTION: ++* This function processes the whole (not fragmented) request ++* ++* INPUT: ++* MV_CESA_REQ* pReq - Pointer to the request in the request queue. ++* ++* RETURN: ++* MV_OK - The request is successfully passed to HW for processing. ++* Other - Failure. The request will not be processed ++* ++*******************************************************************************/ ++static MV_STATUS mvCesaReqProcess(MV_CESA_REQ* pReq) ++{ ++ MV_CESA_MBUF *pMbuf; ++ MV_DMA_DESC *pDmaDesc; ++ MV_U8 *pSramBuf; ++ int sid, i, fixOffset; ++ MV_CESA_SA *pSA; ++ MV_CESA_COMMAND *pCmd = pReq->pCmd; ++ ++ cesaStats.procCount++; ++ ++ sid = pCmd->sessionId; ++ pSA = &pCesaSAD[sid]; ++ pDmaDesc = pReq->dma[0].pDmaFirst; ++ pSramBuf = cesaSramVirtPtr->buf; ++ fixOffset = pReq->fixOffset; ++ ++/* ++ mvOsPrintf("mvCesaReqProcess: sid=%d, pSA=%p, pDmaDesc=%p, pSramBuf=%p\n", ++ sid, pSA, pDmaDesc, pSramBuf); ++*/ ++ i = 0; ++ ++ /* Crypto IV Special processing in CBC mode for Encryption direction */ ++ if( ((pSA->config & MV_CESA_OPERATION_MASK) != (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) && ++ ((pSA->config & MV_CESA_CRYPTO_MODE_MASK) == (MV_CESA_CRYPTO_CBC << MV_CESA_CRYPTO_MODE_BIT)) && ++ ((pSA->config & MV_CESA_DIRECTION_MASK) == (MV_CESA_DIR_ENCODE << MV_CESA_DIRECTION_BIT)) && ++ (pCmd->ivFromUser) ) ++ { ++ /* For Crypto Encode in CBC mode HW always takes IV from SRAM IVPointer, ++ * (not from IVBufPointer). So when ivFromUser==1, we should copy IV from user place ++ * in the buffer to SRAM IVPointer ++ */ ++ i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->cryptoIV, &pDmaDesc[i], ++ MV_FALSE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); ++ } ++ ++ /* Update SA in SRAM */ ++ if(cesaLastSid != sid) ++ { ++ mvCesaSramSaUpdate(sid, &pDmaDesc[i]); ++ i++; ++ } ++ ++ /********* Prepare DMA descriptors to copy from pSrc to SRAM *********/ ++ pMbuf = pCmd->pSrc; ++ i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], ++ MV_FALSE, 0, pMbuf->mbufSize, pCmd->skipFlush); ++ ++ /* Prepare Security Accelerator descriptor to SRAM words 0 - 7 */ ++ mvCesaSramDescrBuild(pSA->config, 0, pCmd->cryptoOffset + fixOffset, ++ pCmd->ivOffset + fixOffset, pCmd->cryptoLength, ++ pCmd->macOffset + fixOffset, pCmd->digestOffset + fixOffset, ++ pCmd->macLength, pCmd->macLength, pReq, &pDmaDesc[i]); ++ i++; ++ ++ /* Add special descriptor Ownership for CPU */ ++ pDmaDesc[i].byteCnt = 0; ++ pDmaDesc[i].phySrcAdd = 0; ++ pDmaDesc[i].phyDestAdd = 0; ++ i++; ++ ++ /********* Prepare DMA descriptors to copy from SRAM to pDst *********/ ++ pMbuf = pCmd->pDst; ++ i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], ++ MV_TRUE, 0, pMbuf->mbufSize, pCmd->skipFlush); ++ ++ /* Next field of Last DMA descriptor must be NULL */ ++ pDmaDesc[i-1].phyNextDescPtr = 0; ++ pReq->dma[0].pDmaLast = &pDmaDesc[i-1]; ++ mvOsCacheFlush(NULL, pReq->dma[0].pDmaFirst, i*sizeof(MV_DMA_DESC)); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvCesaSramDescrBuild - Set CESA descriptor in SRAM ++* ++* DESCRIPTION: ++* This function builds CESA descriptor in SRAM from all Command parameters ++* ++* ++* INPUT: ++* int chan - CESA channel uses the descriptor ++* MV_U32 config - 32 bits of WORD_0 in CESA descriptor structure ++* int cryptoOffset - Offset from the beginning of SRAM buffer where ++* data for encryption/decription is started. ++* int ivOffset - Offset of crypto IV from the SRAM base. Valid only ++* for first fragment. ++* int cryptoLength - Size (in bytes) of data for encryption/descryption ++* operation on this fragment. ++* int macOffset - Offset from the beginning of SRAM buffer where ++* data for Authentication is started ++* int digestOffset - Offset from the beginning of SRAM buffer where ++* digest is located. Valid for first and last fragments. ++* int macLength - Size (in bytes) of data for Authentication ++* operation on this fragment. ++* int macTotalLen - Toatl size (in bytes) of data for Authentication ++* operation on the whole request (packet). Valid for ++* last fragment only. ++* ++* RETURN: None ++* ++*******************************************************************************/ ++static void mvCesaSramDescrBuild(MV_U32 config, int frag, ++ int cryptoOffset, int ivOffset, int cryptoLength, ++ int macOffset, int digestOffset, int macLength, ++ int macTotalLen, MV_CESA_REQ* pReq, MV_DMA_DESC* pDmaDesc) ++{ ++ MV_CESA_DESC* pCesaDesc = &pReq->pCesaDesc[frag]; ++ MV_CESA_DESC* pSramDesc = pSramDesc = &cesaSramVirtPtr->desc; ++ MV_U16 sramBufOffset = (MV_U16)((MV_U8*)cesaSramVirtPtr->buf - mvCesaSramAddrGet()); ++ ++ pCesaDesc->config = MV_32BIT_LE(config); ++ ++ if( (config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET) ) ++ { ++ /* word 1 */ ++ pCesaDesc->cryptoSrcOffset = MV_16BIT_LE(sramBufOffset + cryptoOffset); ++ pCesaDesc->cryptoDstOffset = MV_16BIT_LE(sramBufOffset + cryptoOffset); ++ /* word 2 */ ++ pCesaDesc->cryptoDataLen = MV_16BIT_LE(cryptoLength); ++ /* word 3 */ ++ pCesaDesc->cryptoKeyOffset = MV_16BIT_LE((MV_U16)(cesaSramVirtPtr->sramSA.cryptoKey - ++ mvCesaSramAddrGet())); ++ /* word 4 */ ++ pCesaDesc->cryptoIvOffset = MV_16BIT_LE((MV_U16)(cesaSramVirtPtr->cryptoIV - ++ mvCesaSramAddrGet())); ++ pCesaDesc->cryptoIvBufOffset = MV_16BIT_LE(sramBufOffset + ivOffset); ++ } ++ ++ if( (config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) ++ { ++ /* word 5 */ ++ pCesaDesc->macSrcOffset = MV_16BIT_LE(sramBufOffset + macOffset); ++ pCesaDesc->macTotalLen = MV_16BIT_LE(macTotalLen); ++ ++ /* word 6 */ ++ pCesaDesc->macDigestOffset = MV_16BIT_LE(sramBufOffset + digestOffset); ++ pCesaDesc->macDataLen = MV_16BIT_LE(macLength); ++ ++ /* word 7 */ ++ pCesaDesc->macInnerIvOffset = MV_16BIT_LE((MV_U16)(cesaSramVirtPtr->sramSA.macInnerIV - ++ mvCesaSramAddrGet())); ++ pCesaDesc->macOuterIvOffset = MV_16BIT_LE((MV_U16)(cesaSramVirtPtr->sramSA.macOuterIV - ++ mvCesaSramAddrGet())); ++ } ++ /* Prepare DMA descriptor to CESA descriptor from DRAM to SRAM */ ++ pDmaDesc->phySrcAdd = MV_32BIT_LE(mvCesaVirtToPhys(&pReq->cesaDescBuf, pCesaDesc)); ++ pDmaDesc->phyDestAdd = MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (MV_U8*)pSramDesc)); ++ pDmaDesc->byteCnt = MV_32BIT_LE(sizeof(MV_CESA_DESC) | BIT31); ++ ++ /* flush Source buffer */ ++ mvOsCacheFlush(NULL, pCesaDesc, sizeof(MV_CESA_DESC)); ++} ++ ++/******************************************************************************* ++* mvCesaSramSaUpdate - Move required SA information to SRAM if needed. ++* ++* DESCRIPTION: ++* Copy to SRAM values of the required SA. ++* ++* ++* INPUT: ++* short sid - Session ID needs SRAM Cache update ++* MV_DMA_DESC *pDmaDesc - Pointer to DMA descriptor used to ++* copy SA values from DRAM to SRAM. ++* ++* RETURN: ++* MV_OK - Cache entry for this SA copied to SRAM. ++* MV_NO_CHANGE - Cache entry for this SA already exist in SRAM ++* ++*******************************************************************************/ ++static INLINE void mvCesaSramSaUpdate(short sid, MV_DMA_DESC *pDmaDesc) ++{ ++ MV_CESA_SA *pSA = &pCesaSAD[sid]; ++ ++ /* Prepare DMA descriptor to Copy CACHE_SA from SA database in DRAM to SRAM */ ++ pDmaDesc->byteCnt = MV_32BIT_LE(sizeof(MV_CESA_SRAM_SA) | BIT31); ++ pDmaDesc->phySrcAdd = MV_32BIT_LE(mvCesaVirtToPhys(&cesaSramSaBuf, pSA->pSramSA)); ++ pDmaDesc->phyDestAdd = ++ MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (MV_U8*)&cesaSramVirtPtr->sramSA)); ++ ++ /* Source buffer is already flushed during OpenSession*/ ++ /*mvOsCacheFlush(NULL, &pSA->sramSA, sizeof(MV_CESA_SRAM_SA));*/ ++} ++ ++/******************************************************************************* ++* mvCesaDmaCopyPrepare - prepare DMA descriptor list to copy data presented by ++* Mbuf structure from DRAM to SRAM ++* ++* DESCRIPTION: ++* ++* ++* INPUT: ++* MV_CESA_MBUF* pMbuf - pointer to Mbuf structure contains request ++* data in DRAM ++* MV_U8* pSramBuf - pointer to buffer in SRAM where data should ++* be copied to. ++* MV_DMA_DESC* pDmaDesc - pointer to first DMA descriptor for this copy. ++* The function set number of DMA descriptors needed ++* to copy the copySize bytes from Mbuf. ++* MV_BOOL isToMbuf - Copy direction. ++* MV_TRUE means copy from SRAM buffer to Mbuf in DRAM. ++* MV_FALSE means copy from Mbuf in DRAM to SRAM buffer. ++* int offset - Offset in the Mbuf structure that copy should be ++* started from. ++* int copySize - Size of data should be copied. ++* ++* RETURN: ++* int - number of DMA descriptors used for the copy. ++* ++*******************************************************************************/ ++#ifndef MV_NETBSD ++static INLINE int mvCesaDmaCopyPrepare(MV_CESA_MBUF* pMbuf, MV_U8* pSramBuf, ++ MV_DMA_DESC* pDmaDesc, MV_BOOL isToMbuf, ++ int offset, int copySize, MV_BOOL skipFlush) ++{ ++ int bufOffset, bufSize, size, frag, i; ++ MV_U8* pBuf; ++ ++ i = 0; ++ ++ /* Calculate start place for copy: fragment number and offset in the fragment */ ++ frag = mvCesaMbufOffset(pMbuf, offset, &bufOffset); ++ bufSize = pMbuf->pFrags[frag].bufSize - bufOffset; ++ pBuf = pMbuf->pFrags[frag].bufVirtPtr + bufOffset; ++ ++ /* Size accumulate total copy size */ ++ size = 0; ++ ++ /* Create DMA lists to copy mBuf from pSrc to SRAM */ ++ while(size < copySize) ++ { ++ /* Find copy size for each DMA descriptor */ ++ bufSize = MV_MIN(bufSize, (copySize - size)); ++ pDmaDesc[i].byteCnt = MV_32BIT_LE(bufSize | BIT31); ++ if(isToMbuf) ++ { ++ pDmaDesc[i].phyDestAdd = MV_32BIT_LE(mvOsIoVirtToPhy(NULL, pBuf)); ++ pDmaDesc[i].phySrcAdd = ++ MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (pSramBuf + size))); ++ /* invalidate the buffer */ ++ if(skipFlush == MV_FALSE) ++ mvOsCacheInvalidate(NULL, pBuf, bufSize); ++ } ++ else ++ { ++ pDmaDesc[i].phySrcAdd = MV_32BIT_LE(mvOsIoVirtToPhy(NULL, pBuf)); ++ pDmaDesc[i].phyDestAdd = ++ MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (pSramBuf + size))); ++ /* flush the buffer */ ++ if(skipFlush == MV_FALSE) ++ mvOsCacheFlush(NULL, pBuf, bufSize); ++ } ++ ++ /* Count number of used DMA descriptors */ ++ i++; ++ size += bufSize; ++ ++ /* go to next fragment in the Mbuf */ ++ frag++; ++ pBuf = pMbuf->pFrags[frag].bufVirtPtr; ++ bufSize = pMbuf->pFrags[frag].bufSize; ++ } ++ return i; ++} ++#else /* MV_NETBSD */ ++static int mvCesaDmaCopyPrepare(MV_CESA_MBUF* pMbuf, MV_U8* pSramBuf, ++ MV_DMA_DESC* pDmaDesc, MV_BOOL isToMbuf, ++ int offset, int copySize, MV_BOOL skipFlush) ++{ ++ int bufOffset, bufSize, thisSize, size, frag, i; ++ MV_ULONG bufPhys, sramPhys; ++ MV_U8* pBuf; ++ ++ /* ++ * Calculate start place for copy: fragment number and offset in ++ * the fragment ++ */ ++ frag = mvCesaMbufOffset(pMbuf, offset, &bufOffset); ++ ++ /* ++ * Get SRAM physical address only once. We can update it in-place ++ * as we build the descriptor chain. ++ */ ++ sramPhys = mvCesaSramVirtToPhys(NULL, pSramBuf); ++ ++ /* ++ * 'size' accumulates total copy size, 'i' counts desccriptors. ++ */ ++ size = i = 0; ++ ++ /* Create DMA lists to copy mBuf from pSrc to SRAM */ ++ while (size < copySize) { ++ /* ++ * Calculate # of bytes to copy from the current fragment, ++ * and the pointer to the start of data ++ */ ++ bufSize = pMbuf->pFrags[frag].bufSize - bufOffset; ++ pBuf = pMbuf->pFrags[frag].bufVirtPtr + bufOffset; ++ bufOffset = 0; /* First frag may be non-zero */ ++ frag++; ++ ++ /* ++ * As long as there is data in the current fragment... ++ */ ++ while (bufSize > 0) { ++ /* ++ * Ensure we don't cross an MMU page boundary. ++ * XXX: This is NetBSD-specific, but it is a ++ * quick and dirty way to fix the problem. ++ * A true HAL would rely on the OS-specific ++ * driver to do this... ++ */ ++ thisSize = PAGE_SIZE - ++ (((MV_ULONG)pBuf) & (PAGE_SIZE - 1)); ++ thisSize = MV_MIN(bufSize, thisSize); ++ /* ++ * Make sure we don't copy more than requested ++ */ ++ if (thisSize > (copySize - size)) { ++ thisSize = copySize - size; ++ bufSize = 0; ++ } ++ ++ /* ++ * Physicall address of this fragment ++ */ ++ bufPhys = MV_32BIT_LE(mvOsIoVirtToPhy(NULL, pBuf)); ++ ++ /* ++ * Set up the descriptor ++ */ ++ pDmaDesc[i].byteCnt = MV_32BIT_LE(thisSize | BIT31); ++ if(isToMbuf) { ++ pDmaDesc[i].phyDestAdd = bufPhys; ++ pDmaDesc[i].phySrcAdd = MV_32BIT_LE(sramPhys); ++ /* invalidate the buffer */ ++ if(skipFlush == MV_FALSE) ++ mvOsCacheInvalidate(NULL, pBuf, thisSize); ++ } else { ++ pDmaDesc[i].phySrcAdd = bufPhys; ++ pDmaDesc[i].phyDestAdd = MV_32BIT_LE(sramPhys); ++ /* flush the buffer */ ++ if(skipFlush == MV_FALSE) ++ mvOsCacheFlush(NULL, pBuf, thisSize); ++ } ++ ++ pDmaDesc[i].phyNextDescPtr = ++ MV_32BIT_LE(mvOsIoVirtToPhy(NULL,(&pDmaDesc[i+1]))); ++ ++ /* flush the DMA desc */ ++ mvOsCacheFlush(NULL, &pDmaDesc[i], sizeof(MV_DMA_DESC)); ++ ++ /* Update state */ ++ bufSize -= thisSize; ++ sramPhys += thisSize; ++ pBuf += thisSize; ++ size += thisSize; ++ i++; ++ } ++ } ++ ++ return i; ++} ++#endif /* MV_NETBSD */ ++/******************************************************************************* ++* mvCesaHmacIvGet - Calculate Inner and Outter values from HMAC key ++* ++* DESCRIPTION: ++* This function calculate Inner and Outer values used for HMAC algorithm. ++* This operation allows improve performance fro the whole HMAC processing. ++* ++* INPUT: ++* MV_CESA_MAC_MODE macMode - Authentication mode: HMAC_MD5 or HMAC_SHA1. ++* unsigned char key[] - Pointer to HMAC key. ++* int keyLength - Size of HMAC key (maximum 64 bytes) ++* ++* OUTPUT: ++* unsigned char innerIV[] - HASH(key^inner) ++* unsigned char outerIV[] - HASH(key^outter) ++* ++* RETURN: None ++* ++*******************************************************************************/ ++static void mvCesaHmacIvGet(MV_CESA_MAC_MODE macMode, unsigned char key[], int keyLength, ++ unsigned char innerIV[], unsigned char outerIV[]) ++{ ++ unsigned char inner[MV_CESA_MAX_MAC_KEY_LENGTH]; ++ unsigned char outer[MV_CESA_MAX_MAC_KEY_LENGTH]; ++ int i, digestSize = 0; ++#if defined(MV_CPU_LE) || defined(MV_PPC) ++ MV_U32 swapped32, val32, *pVal32; ++#endif ++ for(i=0; ipFrags[frag].bufVirtPtr + fragOffset; ++ size = pMbuf->pFrags[frag].bufSize - fragOffset; ++ ++ /* Complete Inner part */ ++ while(macLeftSize > 0) ++ { ++ if(macLeftSize <= size) ++ { ++ mvSHA1Update(&ctx, pData, macLeftSize); ++ break; ++ } ++ mvSHA1Update(&ctx, pData, size); ++ macLeftSize -= size; ++ frag++; ++ pData = pMbuf->pFrags[frag].bufVirtPtr; ++ size = pMbuf->pFrags[frag].bufSize; ++ } ++ mvSHA1Final(pDigest, &ctx); ++/* ++ mvOsPrintf("mvCesaFragSha1Complete: pOuterIV=%p, macLeftSize=%d, macTotalSize=%d\n", ++ pOuterIV, macLeftSize, macTotalSize); ++ mvDebugMemDump(pDigest, MV_CESA_SHA1_DIGEST_SIZE, 1); ++*/ ++ ++ if(pOuterIV != NULL) ++ { ++ /* If HMAC - Complete Outer part */ ++ for(i=0; ipFrags[frag].bufVirtPtr + fragOffset; ++ size = pMbuf->pFrags[frag].bufSize - fragOffset; ++ ++ /* Complete Inner part */ ++ while(macLeftSize > 0) ++ { ++ if(macLeftSize <= size) ++ { ++ mvMD5Update(&ctx, pData, macLeftSize); ++ break; ++ } ++ mvMD5Update(&ctx, pData, size); ++ macLeftSize -= size; ++ frag++; ++ pData = pMbuf->pFrags[frag].bufVirtPtr; ++ size = pMbuf->pFrags[frag].bufSize; ++ } ++ mvMD5Final(pDigest, &ctx); ++ ++/* ++ mvOsPrintf("mvCesaFragMd5Complete: pOuterIV=%p, macLeftSize=%d, macTotalSize=%d\n", ++ pOuterIV, macLeftSize, macTotalSize); ++ mvDebugMemDump(pDigest, MV_CESA_MD5_DIGEST_SIZE, 1); ++*/ ++ if(pOuterIV != NULL) ++ { ++ /* Complete Outer part */ ++ for(i=0; ipCmd; ++ MV_U8* pDigest; ++ MV_CESA_MAC_MODE macMode; ++ MV_U8* pOuterIV = NULL; ++ ++ /* Copy data from Source fragment to Destination */ ++ if(pCmd->pSrc != pCmd->pDst) ++ { ++ mvCesaMbufCopy(pCmd->pDst, pReq->frags.bufOffset, ++ pCmd->pSrc, pReq->frags.bufOffset, macDataSize); ++ } ++ ++/* ++ mvCesaCopyFromMbuf(cesaSramVirtPtr->buf[0], pCmd->pSrc, pReq->frags.bufOffset, macDataSize); ++ mvCesaCopyToMbuf(cesaSramVirtPtr->buf[0], pCmd->pDst, pReq->frags.bufOffset, macDataSize); ++*/ ++ pDigest = (mvCesaSramAddrGet() + pReq->frags.newDigestOffset); ++ ++ macMode = (pSA->config & MV_CESA_MAC_MODE_MASK) >> MV_CESA_MAC_MODE_OFFSET; ++/* ++ mvOsPrintf("macDataSize=%d, macLength=%d, digestOffset=%d, macMode=%d\n", ++ macDataSize, pCmd->macLength, pCmd->digestOffset, macMode); ++*/ ++ switch(macMode) ++ { ++ case MV_CESA_MAC_HMAC_MD5: ++ pOuterIV = pSA->pSramSA->macOuterIV; ++ ++ case MV_CESA_MAC_MD5: ++ mvCesaFragMd5Complete(pCmd->pDst, pReq->frags.bufOffset, pOuterIV, ++ macDataSize, pCmd->macLength, pDigest); ++ break; ++ ++ case MV_CESA_MAC_HMAC_SHA1: ++ pOuterIV = pSA->pSramSA->macOuterIV; ++ ++ case MV_CESA_MAC_SHA1: ++ mvCesaFragSha1Complete(pCmd->pDst, pReq->frags.bufOffset, pOuterIV, ++ macDataSize, pCmd->macLength, pDigest); ++ break; ++ ++ default: ++ mvOsPrintf("mvCesaFragAuthComplete: Unexpected macMode %d\n", macMode); ++ return MV_BAD_PARAM; ++ } ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCesaCtrModeInit - ++* ++* DESCRIPTION: ++* ++* ++* INPUT: NONE ++* ++* ++* RETURN: ++* MV_CESA_COMMAND* ++* ++*******************************************************************************/ ++static MV_CESA_COMMAND* mvCesaCtrModeInit(void) ++{ ++ MV_CESA_MBUF *pMbuf; ++ MV_U8 *pBuf; ++ MV_CESA_COMMAND *pCmd; ++ ++ pBuf = mvOsMalloc(sizeof(MV_CESA_COMMAND) + ++ sizeof(MV_CESA_MBUF) + sizeof(MV_BUF_INFO) + 100); ++ if(pBuf == NULL) ++ { ++ mvOsPrintf("mvCesaSessionOpen: Can't allocate %u bytes for CTR Mode\n", ++ sizeof(MV_CESA_COMMAND) + sizeof(MV_CESA_MBUF) + sizeof(MV_BUF_INFO) ); ++ return NULL; ++ } ++ pCmd = (MV_CESA_COMMAND*)pBuf; ++ pBuf += sizeof(MV_CESA_COMMAND); ++ ++ pMbuf = (MV_CESA_MBUF*)pBuf; ++ pBuf += sizeof(MV_CESA_MBUF); ++ ++ pMbuf->pFrags = (MV_BUF_INFO*)pBuf; ++ ++ pMbuf->numFrags = 1; ++ pCmd->pSrc = pMbuf; ++ pCmd->pDst = pMbuf; ++/* ++ mvOsPrintf("CtrModeInit: pCmd=%p, pSrc=%p, pDst=%p, pFrags=%p\n", ++ pCmd, pCmd->pSrc, pCmd->pDst, ++ pMbuf->pFrags); ++*/ ++ return pCmd; ++} ++ ++/******************************************************************************* ++* mvCesaCtrModePrepare - ++* ++* DESCRIPTION: ++* ++* ++* INPUT: ++* MV_CESA_COMMAND *pCtrModeCmd, MV_CESA_COMMAND *pCmd ++* ++* RETURN: ++* MV_STATUS ++* ++*******************************************************************************/ ++static MV_STATUS mvCesaCtrModePrepare(MV_CESA_COMMAND *pCtrModeCmd, MV_CESA_COMMAND *pCmd) ++{ ++ MV_CESA_MBUF *pMbuf; ++ MV_U8 *pBuf, *pIV; ++ MV_U32 counter, *pCounter; ++ int cryptoSize = MV_ALIGN_UP(pCmd->cryptoLength, MV_CESA_AES_BLOCK_SIZE); ++/* ++ mvOsPrintf("CtrModePrepare: pCmd=%p, pCtrSrc=%p, pCtrDst=%p, pOrgCmd=%p, pOrgSrc=%p, pOrgDst=%p\n", ++ pCmd, pCmd->pSrc, pCmd->pDst, ++ pCtrModeCmd, pCtrModeCmd->pSrc, pCtrModeCmd->pDst); ++*/ ++ pMbuf = pCtrModeCmd->pSrc; ++ ++ /* Allocate buffer for Key stream */ ++ pBuf = mvOsIoCachedMalloc(cesaOsHandle,cryptoSize, ++ &pMbuf->pFrags[0].bufPhysAddr, ++ &pMbuf->pFrags[0].memHandle); ++ if(pBuf == NULL) ++ { ++ mvOsPrintf("mvCesaCtrModePrepare: Can't allocate %d bytes\n", cryptoSize); ++ return MV_OUT_OF_CPU_MEM; ++ } ++ memset(pBuf, 0, cryptoSize); ++ mvOsCacheFlush(NULL, pBuf, cryptoSize); ++ ++ pMbuf->pFrags[0].bufVirtPtr = pBuf; ++ pMbuf->mbufSize = cryptoSize; ++ pMbuf->pFrags[0].bufSize = cryptoSize; ++ ++ pCtrModeCmd->pReqPrv = pCmd->pReqPrv; ++ pCtrModeCmd->sessionId = pCmd->sessionId; ++ ++ /* ivFromUser and ivOffset are don't care */ ++ pCtrModeCmd->cryptoOffset = 0; ++ pCtrModeCmd->cryptoLength = cryptoSize; ++ ++ /* digestOffset, macOffset and macLength are don't care */ ++ ++ mvCesaCopyFromMbuf(pBuf, pCmd->pSrc, pCmd->ivOffset, MV_CESA_AES_BLOCK_SIZE); ++ pCounter = (MV_U32*)(pBuf + (MV_CESA_AES_BLOCK_SIZE - sizeof(counter))); ++ counter = *pCounter; ++ counter = MV_32BIT_BE(counter); ++ pIV = pBuf; ++ cryptoSize -= MV_CESA_AES_BLOCK_SIZE; ++ ++ /* fill key stream */ ++ while(cryptoSize > 0) ++ { ++ pBuf += MV_CESA_AES_BLOCK_SIZE; ++ memcpy(pBuf, pIV, MV_CESA_AES_BLOCK_SIZE - sizeof(counter)); ++ pCounter = (MV_U32*)(pBuf + (MV_CESA_AES_BLOCK_SIZE - sizeof(counter))); ++ counter++; ++ *pCounter = MV_32BIT_BE(counter); ++ cryptoSize -= MV_CESA_AES_BLOCK_SIZE; ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCesaCtrModeComplete - ++* ++* DESCRIPTION: ++* ++* ++* INPUT: ++* MV_CESA_COMMAND *pOrgCmd, MV_CESA_COMMAND *pCmd ++* ++* RETURN: ++* MV_STATUS ++* ++*******************************************************************************/ ++static MV_STATUS mvCesaCtrModeComplete(MV_CESA_COMMAND *pOrgCmd, MV_CESA_COMMAND *pCmd) ++{ ++ int srcFrag, dstFrag, srcOffset, dstOffset, keyOffset, srcSize, dstSize; ++ int cryptoSize = pCmd->cryptoLength; ++ MV_U8 *pSrc, *pDst, *pKey; ++ MV_STATUS status = MV_OK; ++/* ++ mvOsPrintf("CtrModeComplete: pCmd=%p, pCtrSrc=%p, pCtrDst=%p, pOrgCmd=%p, pOrgSrc=%p, pOrgDst=%p\n", ++ pCmd, pCmd->pSrc, pCmd->pDst, ++ pOrgCmd, pOrgCmd->pSrc, pOrgCmd->pDst); ++*/ ++ /* XOR source data with key stream to destination data */ ++ pKey = pCmd->pDst->pFrags[0].bufVirtPtr; ++ keyOffset = 0; ++ ++ if( (pOrgCmd->pSrc != pOrgCmd->pDst) && ++ (pOrgCmd->cryptoOffset > 0) ) ++ { ++ /* Copy Prefix from source buffer to destination buffer */ ++ ++ status = mvCesaMbufCopy(pOrgCmd->pDst, 0, ++ pOrgCmd->pSrc, 0, pOrgCmd->cryptoOffset); ++/* ++ status = mvCesaCopyFromMbuf(tempBuf, pOrgCmd->pSrc, ++ 0, pOrgCmd->cryptoOffset); ++ status = mvCesaCopyToMbuf(tempBuf, pOrgCmd->pDst, ++ 0, pOrgCmd->cryptoOffset); ++*/ ++ } ++ ++ srcFrag = mvCesaMbufOffset(pOrgCmd->pSrc, pOrgCmd->cryptoOffset, &srcOffset); ++ pSrc = pOrgCmd->pSrc->pFrags[srcFrag].bufVirtPtr; ++ srcSize = pOrgCmd->pSrc->pFrags[srcFrag].bufSize; ++ ++ dstFrag = mvCesaMbufOffset(pOrgCmd->pDst, pOrgCmd->cryptoOffset, &dstOffset); ++ pDst = pOrgCmd->pDst->pFrags[dstFrag].bufVirtPtr; ++ dstSize = pOrgCmd->pDst->pFrags[dstFrag].bufSize; ++ ++ while(cryptoSize > 0) ++ { ++ pDst[dstOffset] = (pSrc[srcOffset] ^ pKey[keyOffset]); ++ ++ cryptoSize--; ++ dstOffset++; ++ srcOffset++; ++ keyOffset++; ++ ++ if(srcOffset >= srcSize) ++ { ++ srcFrag++; ++ srcOffset = 0; ++ pSrc = pOrgCmd->pSrc->pFrags[srcFrag].bufVirtPtr; ++ srcSize = pOrgCmd->pSrc->pFrags[srcFrag].bufSize; ++ } ++ ++ if(dstOffset >= dstSize) ++ { ++ dstFrag++; ++ dstOffset = 0; ++ pDst = pOrgCmd->pDst->pFrags[dstFrag].bufVirtPtr; ++ dstSize = pOrgCmd->pDst->pFrags[dstFrag].bufSize; ++ } ++ } ++ ++ if(pOrgCmd->pSrc != pOrgCmd->pDst) ++ { ++ /* Copy Suffix from source buffer to destination buffer */ ++ srcOffset = pOrgCmd->cryptoOffset + pOrgCmd->cryptoLength; ++ ++ if( (pOrgCmd->pDst->mbufSize - srcOffset) > 0) ++ { ++ status = mvCesaMbufCopy(pOrgCmd->pDst, srcOffset, ++ pOrgCmd->pSrc, srcOffset, ++ pOrgCmd->pDst->mbufSize - srcOffset); ++ } ++ ++/* ++ status = mvCesaCopyFromMbuf(tempBuf, pOrgCmd->pSrc, ++ srcOffset, pOrgCmd->pSrc->mbufSize - srcOffset); ++ status = mvCesaCopyToMbuf(tempBuf, pOrgCmd->pDst, ++ srcOffset, pOrgCmd->pDst->mbufSize - srcOffset); ++*/ ++ } ++ ++ /* Free buffer used for Key stream */ ++ mvOsIoCachedFree(cesaOsHandle,pCmd->pDst->pFrags[0].bufSize, ++ pCmd->pDst->pFrags[0].bufPhysAddr, ++ pCmd->pDst->pFrags[0].bufVirtPtr, ++ pCmd->pDst->pFrags[0].memHandle); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCesaCtrModeFinish - ++* ++* DESCRIPTION: ++* ++* ++* INPUT: ++* MV_CESA_COMMAND* pCmd ++* ++* RETURN: ++* MV_STATUS ++* ++*******************************************************************************/ ++static void mvCesaCtrModeFinish(MV_CESA_COMMAND* pCmd) ++{ ++ mvOsFree(pCmd); ++} ++ ++/******************************************************************************* ++* mvCesaParamCheck - ++* ++* DESCRIPTION: ++* ++* ++* INPUT: ++* MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, MV_U8* pFixOffset ++* ++* RETURN: ++* MV_STATUS ++* ++*******************************************************************************/ ++static MV_STATUS mvCesaParamCheck(MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, ++ MV_U8* pFixOffset) ++{ ++ MV_U8 fixOffset = 0xFF; ++ ++ /* Check AUTH operation parameters */ ++ if( ((pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET)) ) ++ { ++ /* MAC offset should be at least 4 byte aligned */ ++ if( MV_IS_NOT_ALIGN(pCmd->macOffset, 4) ) ++ { ++ mvOsPrintf("mvCesaAction: macOffset %d must be 4 byte aligned\n", ++ pCmd->macOffset); ++ return MV_BAD_PARAM; ++ } ++ /* Digest offset must be 4 byte aligned */ ++ if( MV_IS_NOT_ALIGN(pCmd->digestOffset, 4) ) ++ { ++ mvOsPrintf("mvCesaAction: digestOffset %d must be 4 byte aligned\n", ++ pCmd->digestOffset); ++ return MV_BAD_PARAM; ++ } ++ /* In addition all offsets should be the same alignment: 8 or 4 */ ++ if(fixOffset == 0xFF) ++ { ++ fixOffset = (pCmd->macOffset % 8); ++ } ++ else ++ { ++ if( (pCmd->macOffset % 8) != fixOffset) ++ { ++ mvOsPrintf("mvCesaAction: macOffset %d mod 8 must be equal %d\n", ++ pCmd->macOffset, fixOffset); ++ return MV_BAD_PARAM; ++ } ++ } ++ if( (pCmd->digestOffset % 8) != fixOffset) ++ { ++ mvOsPrintf("mvCesaAction: digestOffset %d mod 8 must be equal %d\n", ++ pCmd->digestOffset, fixOffset); ++ return MV_BAD_PARAM; ++ } ++ } ++ /* Check CRYPTO operation parameters */ ++ if( ((pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) ) ++ { ++ /* CryptoOffset should be at least 4 byte aligned */ ++ if( MV_IS_NOT_ALIGN(pCmd->cryptoOffset, 4) ) ++ { ++ mvOsPrintf("CesaAction: cryptoOffset=%d must be 4 byte aligned\n", ++ pCmd->cryptoOffset); ++ return MV_BAD_PARAM; ++ } ++ /* cryptoLength should be the whole number of blocks */ ++ if( MV_IS_NOT_ALIGN(pCmd->cryptoLength, pSA->cryptoBlockSize) ) ++ { ++ mvOsPrintf("mvCesaAction: cryptoLength=%d must be %d byte aligned\n", ++ pCmd->cryptoLength, pSA->cryptoBlockSize); ++ return MV_BAD_PARAM; ++ } ++ if(fixOffset == 0xFF) ++ { ++ fixOffset = (pCmd->cryptoOffset % 8); ++ } ++ else ++ { ++ /* In addition all offsets should be the same alignment: 8 or 4 */ ++ if( (pCmd->cryptoOffset % 8) != fixOffset) ++ { ++ mvOsPrintf("mvCesaAction: cryptoOffset %d mod 8 must be equal %d \n", ++ pCmd->cryptoOffset, fixOffset); ++ return MV_BAD_PARAM; ++ } ++ } ++ ++ /* check for CBC mode */ ++ if(pSA->cryptoIvSize > 0) ++ { ++ /* cryptoIV must not be part of CryptoLength */ ++ if( ((pCmd->ivOffset + pSA->cryptoIvSize) > pCmd->cryptoOffset) && ++ (pCmd->ivOffset < (pCmd->cryptoOffset + pCmd->cryptoLength)) ) ++ { ++ mvOsPrintf("mvCesaFragParamCheck: cryptoIvOffset (%d) is part of cryptoLength (%d+%d)\n", ++ pCmd->ivOffset, pCmd->macOffset, pCmd->macLength); ++ return MV_BAD_PARAM; ++ } ++ ++ /* ivOffset must be 4 byte aligned */ ++ if( MV_IS_NOT_ALIGN(pCmd->ivOffset, 4) ) ++ { ++ mvOsPrintf("CesaAction: ivOffset=%d must be 4 byte aligned\n", ++ pCmd->ivOffset); ++ return MV_BAD_PARAM; ++ } ++ /* In addition all offsets should be the same alignment: 8 or 4 */ ++ if( (pCmd->ivOffset % 8) != fixOffset) ++ { ++ mvOsPrintf("mvCesaAction: ivOffset %d mod 8 must be %d\n", ++ pCmd->ivOffset, fixOffset); ++ return MV_BAD_PARAM; ++ } ++ } ++ } ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCesaFragParamCheck - ++* ++* DESCRIPTION: ++* ++* ++* INPUT: ++* MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd ++* ++* RETURN: ++* MV_STATUS ++* ++*******************************************************************************/ ++static MV_STATUS mvCesaFragParamCheck(MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd) ++{ ++ int offset; ++ ++ if( ((pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET)) ) ++ { ++ /* macOffset must be less that SRAM buffer size */ ++ if(pCmd->macOffset > (sizeof(cesaSramVirtPtr->buf) - MV_CESA_AUTH_BLOCK_SIZE)) ++ { ++ mvOsPrintf("mvCesaFragParamCheck: macOffset is too large (%d)\n", ++ pCmd->macOffset); ++ return MV_BAD_PARAM; ++ } ++ /* macOffset+macSize must be more than mbufSize - SRAM buffer size */ ++ if( ((pCmd->macOffset + pCmd->macLength) > pCmd->pSrc->mbufSize) || ++ ((pCmd->pSrc->mbufSize - (pCmd->macOffset + pCmd->macLength)) >= ++ sizeof(cesaSramVirtPtr->buf)) ) ++ { ++ mvOsPrintf("mvCesaFragParamCheck: macLength is too large (%d), mbufSize=%d\n", ++ pCmd->macLength, pCmd->pSrc->mbufSize); ++ return MV_BAD_PARAM; ++ } ++ } ++ ++ if( ((pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) ) ++ { ++ /* cryptoOffset must be less that SRAM buffer size */ ++ /* 4 for possible fixOffset */ ++ if( (pCmd->cryptoOffset + 4) > (sizeof(cesaSramVirtPtr->buf) - pSA->cryptoBlockSize)) ++ { ++ mvOsPrintf("mvCesaFragParamCheck: cryptoOffset is too large (%d)\n", ++ pCmd->cryptoOffset); ++ return MV_BAD_PARAM; ++ } ++ ++ /* cryptoOffset+cryptoSize must be more than mbufSize - SRAM buffer size */ ++ if( ((pCmd->cryptoOffset + pCmd->cryptoLength) > pCmd->pSrc->mbufSize) || ++ ((pCmd->pSrc->mbufSize - (pCmd->cryptoOffset + pCmd->cryptoLength)) >= ++ (sizeof(cesaSramVirtPtr->buf) - pSA->cryptoBlockSize)) ) ++ { ++ mvOsPrintf("mvCesaFragParamCheck: cryptoLength is too large (%d), mbufSize=%d\n", ++ pCmd->cryptoLength, pCmd->pSrc->mbufSize); ++ return MV_BAD_PARAM; ++ } ++ } ++ ++ /* When MAC_THEN_CRYPTO or CRYPTO_THEN_MAC */ ++ if( ((pSA->config & MV_CESA_OPERATION_MASK) == ++ (MV_CESA_MAC_THEN_CRYPTO << MV_CESA_OPERATION_OFFSET)) || ++ ((pSA->config & MV_CESA_OPERATION_MASK) == ++ (MV_CESA_CRYPTO_THEN_MAC << MV_CESA_OPERATION_OFFSET)) ) ++ { ++ if( (mvCtrlModelGet() == MV_5182_DEV_ID) || ++ ( (mvCtrlModelGet() == MV_5181_DEV_ID) && ++ (mvCtrlRevGet() >= MV_5181L_A0_REV) && ++ (pCmd->macLength >= (1 << 14)) ) ) ++ { ++ return MV_NOT_ALLOWED; ++ } ++ ++ /* abs(cryptoOffset-macOffset) must be aligned cryptoBlockSize */ ++ if(pCmd->cryptoOffset > pCmd->macOffset) ++ { ++ offset = pCmd->cryptoOffset - pCmd->macOffset; ++ } ++ else ++ { ++ offset = pCmd->macOffset - pCmd->cryptoOffset; ++ } ++ ++ if( MV_IS_NOT_ALIGN(offset, pSA->cryptoBlockSize) ) ++ { ++/* ++ mvOsPrintf("mvCesaFragParamCheck: (cryptoOffset - macOffset) must be %d byte aligned\n", ++ pSA->cryptoBlockSize); ++*/ ++ return MV_NOT_ALLOWED; ++ } ++ /* Digest must not be part of CryptoLength */ ++ if( ((pCmd->digestOffset + pSA->digestSize) > pCmd->cryptoOffset) && ++ (pCmd->digestOffset < (pCmd->cryptoOffset + pCmd->cryptoLength)) ) ++ { ++/* ++ mvOsPrintf("mvCesaFragParamCheck: digestOffset (%d) is part of cryptoLength (%d+%d)\n", ++ pCmd->digestOffset, pCmd->cryptoOffset, pCmd->cryptoLength); ++*/ ++ return MV_NOT_ALLOWED; ++ } ++ } ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCesaFragSizeFind - ++* ++* DESCRIPTION: ++* ++* ++* INPUT: ++* MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, ++* int cryptoOffset, int macOffset, ++* ++* OUTPUT: ++* int* pCopySize, int* pCryptoDataSize, int* pMacDataSize ++* ++* RETURN: ++* MV_STATUS ++* ++*******************************************************************************/ ++static void mvCesaFragSizeFind(MV_CESA_SA* pSA, MV_CESA_REQ* pReq, ++ int cryptoOffset, int macOffset, ++ int* pCopySize, int* pCryptoDataSize, int* pMacDataSize) ++{ ++ MV_CESA_COMMAND *pCmd = pReq->pCmd; ++ int cryptoDataSize, macDataSize, copySize; ++ ++ cryptoDataSize = macDataSize = 0; ++ copySize = *pCopySize; ++ ++ if( (pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET) ) ++ { ++ cryptoDataSize = MV_MIN( (copySize - cryptoOffset), ++ (pCmd->cryptoLength - (pReq->frags.cryptoSize + 1)) ); ++ ++ /* cryptoSize for each fragment must be the whole number of blocksSize */ ++ if( MV_IS_NOT_ALIGN(cryptoDataSize, pSA->cryptoBlockSize) ) ++ { ++ cryptoDataSize = MV_ALIGN_DOWN(cryptoDataSize, pSA->cryptoBlockSize); ++ copySize = cryptoOffset + cryptoDataSize; ++ } ++ } ++ if( (pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) ++ { ++ macDataSize = MV_MIN( (copySize - macOffset), ++ (pCmd->macLength - (pReq->frags.macSize + 1))); ++ ++ /* macSize for each fragment (except last) must be the whole number of blocksSize */ ++ if( MV_IS_NOT_ALIGN(macDataSize, MV_CESA_AUTH_BLOCK_SIZE) ) ++ { ++ macDataSize = MV_ALIGN_DOWN(macDataSize, MV_CESA_AUTH_BLOCK_SIZE); ++ copySize = macOffset + macDataSize; ++ } ++ cryptoDataSize = copySize - cryptoOffset; ++ } ++ *pCopySize = copySize; ++ ++ if(pCryptoDataSize != NULL) ++ *pCryptoDataSize = cryptoDataSize; ++ ++ if(pMacDataSize != NULL) ++ *pMacDataSize = macDataSize; ++} +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvCesa.h linux-3.0.4/crypto/ocf/kirkwood/cesa/mvCesa.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvCesa.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/cesa/mvCesa.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,412 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++/******************************************************************************* ++* mvCesa.h - Header File for Cryptographic Engines and Security Accelerator ++* ++* DESCRIPTION: ++* This header file contains macros typedefs and function declaration for ++* the Marvell Cryptographic Engines and Security Accelerator. ++* ++*******************************************************************************/ ++ ++#ifndef __mvCesa_h__ ++#define __mvCesa_h__ ++ ++#include "mvOs.h" ++#include "mvCommon.h" ++#include "mvDebug.h" ++ ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++ ++#include "cesa/mvMD5.h" ++#include "cesa/mvSHA1.h" ++ ++#include "cesa/mvCesa.h" ++#include "cesa/AES/mvAes.h" ++#include "mvSysHwConfig.h" ++ ++#ifdef MV_INCLUDE_IDMA ++#include "idma/mvIdma.h" ++#include "idma/mvIdmaRegs.h" ++#else ++/* Redefine MV_DMA_DESC structure */ ++typedef struct _mvDmaDesc ++{ ++ MV_U32 byteCnt; /* The total number of bytes to transfer */ ++ MV_U32 phySrcAdd; /* The physical source address */ ++ MV_U32 phyDestAdd; /* The physical destination address */ ++ MV_U32 phyNextDescPtr; /* If we are using chain mode DMA transfer, */ ++ /* then this pointer should point to the */ ++ /* physical address of the next descriptor, */ ++ /* otherwise it should be NULL. */ ++}MV_DMA_DESC; ++#endif /* MV_INCLUDE_IDMA */ ++ ++#include "cesa/mvCesaRegs.h" ++ ++#define MV_CESA_AUTH_BLOCK_SIZE 64 /* bytes */ ++ ++#define MV_CESA_MD5_DIGEST_SIZE 16 /* bytes */ ++#define MV_CESA_SHA1_DIGEST_SIZE 20 /* bytes */ ++ ++#define MV_CESA_MAX_DIGEST_SIZE MV_CESA_SHA1_DIGEST_SIZE ++ ++#define MV_CESA_DES_KEY_LENGTH 8 /* bytes = 64 bits */ ++#define MV_CESA_3DES_KEY_LENGTH 24 /* bytes = 192 bits */ ++#define MV_CESA_AES_128_KEY_LENGTH 16 /* bytes = 128 bits */ ++#define MV_CESA_AES_192_KEY_LENGTH 24 /* bytes = 192 bits */ ++#define MV_CESA_AES_256_KEY_LENGTH 32 /* bytes = 256 bits */ ++ ++#define MV_CESA_MAX_CRYPTO_KEY_LENGTH MV_CESA_AES_256_KEY_LENGTH ++ ++#define MV_CESA_DES_BLOCK_SIZE 8 /* bytes = 64 bits */ ++#define MV_CESA_3DES_BLOCK_SIZE 8 /* bytes = 64 bits */ ++ ++#define MV_CESA_AES_BLOCK_SIZE 16 /* bytes = 128 bits */ ++ ++#define MV_CESA_MAX_IV_LENGTH MV_CESA_AES_BLOCK_SIZE ++ ++#define MV_CESA_MAX_MAC_KEY_LENGTH 64 /* bytes */ ++ ++typedef struct ++{ ++ MV_U8 cryptoKey[MV_CESA_MAX_CRYPTO_KEY_LENGTH]; ++ MV_U8 macKey[MV_CESA_MAX_MAC_KEY_LENGTH]; ++ MV_CESA_OPERATION operation; ++ MV_CESA_DIRECTION direction; ++ MV_CESA_CRYPTO_ALG cryptoAlgorithm; ++ MV_CESA_CRYPTO_MODE cryptoMode; ++ MV_U8 cryptoKeyLength; ++ MV_CESA_MAC_MODE macMode; ++ MV_U8 macKeyLength; ++ MV_U8 digestSize; ++ ++} MV_CESA_OPEN_SESSION; ++ ++typedef struct ++{ ++ MV_BUF_INFO *pFrags; ++ MV_U16 numFrags; ++ MV_U16 mbufSize; ++ ++} MV_CESA_MBUF; ++ ++typedef struct ++{ ++ void* pReqPrv; /* instead of reqId */ ++ MV_U32 retCode; ++ MV_16 sessionId; ++ ++} MV_CESA_RESULT; ++ ++typedef void (*MV_CESA_CALLBACK) (MV_CESA_RESULT* pResult); ++ ++ ++typedef struct ++{ ++ void* pReqPrv; /* instead of reqId */ ++ MV_CESA_MBUF* pSrc; ++ MV_CESA_MBUF* pDst; ++ MV_CESA_CALLBACK* pFuncCB; ++ MV_16 sessionId; ++ MV_U16 ivFromUser; ++ MV_U16 ivOffset; ++ MV_U16 cryptoOffset; ++ MV_U16 cryptoLength; ++ MV_U16 digestOffset; ++ MV_U16 macOffset; ++ MV_U16 macLength; ++ MV_BOOL skipFlush; ++} MV_CESA_COMMAND; ++ ++ ++ ++MV_STATUS mvCesaHalInit (int numOfSession, int queueDepth, char* pSramBase, MV_U32 cryptEngBase, void *osHandle); ++MV_STATUS mvCesaFinish (void); ++MV_STATUS mvCesaSessionOpen(MV_CESA_OPEN_SESSION *pSession, short* pSid); ++MV_STATUS mvCesaSessionClose(short sid); ++MV_STATUS mvCesaCryptoIvSet(MV_U8* pIV, int ivSize); ++ ++MV_STATUS mvCesaAction (MV_CESA_COMMAND* pCmd); ++ ++MV_U32 mvCesaInProcessGet(void); ++MV_STATUS mvCesaReadyDispatch(void); ++MV_STATUS mvCesaReadyGet(MV_CESA_RESULT* pResult); ++MV_BOOL mvCesaIsReady(void); ++ ++int mvCesaMbufOffset(MV_CESA_MBUF* pMbuf, int offset, int* pBufOffset); ++MV_STATUS mvCesaCopyFromMbuf(MV_U8* pDst, MV_CESA_MBUF* pSrcMbuf, ++ int offset, int size); ++MV_STATUS mvCesaCopyToMbuf(MV_U8* pSrc, MV_CESA_MBUF* pDstMbuf, ++ int offset, int size); ++MV_STATUS mvCesaMbufCopy(MV_CESA_MBUF* pMbufDst, int dstMbufOffset, ++ MV_CESA_MBUF* pMbufSrc, int srcMbufOffset, int size); ++ ++/********** Debug functions ********/ ++ ++void mvCesaDebugMbuf(const char* str, MV_CESA_MBUF *pMbuf, int offset, int size); ++void mvCesaDebugSA(short sid, int mode); ++void mvCesaDebugStats(void); ++void mvCesaDebugStatsClear(void); ++void mvCesaDebugRegs(void); ++void mvCesaDebugStatus(void); ++void mvCesaDebugQueue(int mode); ++void mvCesaDebugSram(int mode); ++void mvCesaDebugSAD(int mode); ++ ++ ++/******** CESA Private definitions ********/ ++#if (MV_CESA_VERSION >= 2) ++#if (MV_CACHE_COHERENCY == MV_CACHE_COHER_SW) ++#define MV_CESA_TDMA_CTRL_VALUE MV_CESA_TDMA_DST_BURST_MASK(MV_CESA_TDMA_BURST_128B) \ ++ | MV_CESA_TDMA_SRC_BURST_MASK(MV_CESA_TDMA_BURST_128B) \ ++ | MV_CESA_TDMA_OUTSTAND_READ_EN_MASK \ ++ | MV_CESA_TDMA_NO_BYTE_SWAP_MASK \ ++ | MV_CESA_TDMA_ENABLE_MASK ++#else ++#define MV_CESA_TDMA_CTRL_VALUE MV_CESA_TDMA_DST_BURST_MASK(MV_CESA_TDMA_BURST_32B) \ ++ | MV_CESA_TDMA_SRC_BURST_MASK(MV_CESA_TDMA_BURST_128B) \ ++ /*| MV_CESA_TDMA_OUTSTAND_READ_EN_MASK */\ ++ | MV_CESA_TDMA_ENABLE_MASK ++ ++#endif ++#else ++#define MV_CESA_IDMA_CTRL_LOW_VALUE ICCLR_DST_BURST_LIM_128BYTE \ ++ | ICCLR_SRC_BURST_LIM_128BYTE \ ++ | ICCLR_INT_MODE_MASK \ ++ | ICCLR_BLOCK_MODE \ ++ | ICCLR_CHAN_ENABLE \ ++ | ICCLR_DESC_MODE_16M ++#endif /* MV_CESA_VERSION >= 2 */ ++ ++#define MV_CESA_MAX_PKT_SIZE (64 * 1024) ++#define MV_CESA_MAX_MBUF_FRAGS 20 ++ ++#define MV_CESA_MAX_REQ_FRAGS ( (MV_CESA_MAX_PKT_SIZE / MV_CESA_MAX_BUF_SIZE) + 1) ++ ++#define MV_CESA_MAX_DMA_DESC (MV_CESA_MAX_MBUF_FRAGS*2 + 5) ++ ++#define MAX_CESA_CHAIN_LENGTH 20 ++ ++typedef enum ++{ ++ MV_CESA_IDLE = 0, ++ MV_CESA_PENDING, ++ MV_CESA_PROCESS, ++ MV_CESA_READY, ++#if (MV_CESA_VERSION >= 3) ++ MV_CESA_CHAIN, ++#endif ++} MV_CESA_STATE; ++ ++ ++/* Session database */ ++ ++/* Map of Key materials of the session in SRAM. ++ * Each field must be 8 byte aligned ++ * Total size: 32 + 24 + 24 = 80 bytes ++ */ ++typedef struct ++{ ++ MV_U8 cryptoKey[MV_CESA_MAX_CRYPTO_KEY_LENGTH]; ++ MV_U8 macInnerIV[MV_CESA_MAX_DIGEST_SIZE]; ++ MV_U8 reservedInner[4]; ++ MV_U8 macOuterIV[MV_CESA_MAX_DIGEST_SIZE]; ++ MV_U8 reservedOuter[4]; ++ ++} MV_CESA_SRAM_SA; ++ ++typedef struct ++{ ++ MV_CESA_SRAM_SA* pSramSA; ++ MV_U32 config; ++ MV_U8 cryptoKeyLength; ++ MV_U8 cryptoIvSize; ++ MV_U8 cryptoBlockSize; ++ MV_U8 digestSize; ++ MV_U8 macKeyLength; ++ MV_U8 valid; ++ MV_U8 ctrMode; ++ MV_U32 count; ++ ++} MV_CESA_SA; ++ ++/* DMA list management */ ++typedef struct ++{ ++ MV_DMA_DESC* pDmaFirst; ++ MV_DMA_DESC* pDmaLast; ++ ++} MV_CESA_DMA; ++ ++ ++typedef struct ++{ ++ MV_U8 numFrag; ++ MV_U8 nextFrag; ++ int bufOffset; ++ int cryptoSize; ++ int macSize; ++ int newDigestOffset; ++ MV_U8 orgDigest[MV_CESA_MAX_DIGEST_SIZE]; ++ ++} MV_CESA_FRAGS; ++ ++/* Request queue */ ++typedef struct ++{ ++ MV_U8 state; ++ MV_U8 fragMode; ++ MV_U8 fixOffset; ++ MV_CESA_COMMAND* pCmd; ++ MV_CESA_COMMAND* pOrgCmd; ++ MV_BUF_INFO dmaDescBuf; ++ MV_CESA_DMA dma[MV_CESA_MAX_REQ_FRAGS]; ++ MV_BUF_INFO cesaDescBuf; ++ MV_CESA_DESC* pCesaDesc; ++ MV_CESA_FRAGS frags; ++ ++ ++} MV_CESA_REQ; ++ ++ ++/* SRAM map */ ++/* Total SRAM size calculation */ ++/* SRAM size = ++ * MV_CESA_MAX_BUF_SIZE + ++ * sizeof(MV_CESA_DESC) + ++ * MV_CESA_MAX_IV_LENGTH + ++ * MV_CESA_MAX_IV_LENGTH + ++ * MV_CESA_MAX_DIGEST_SIZE + ++ * sizeof(MV_CESA_SRAM_SA) ++ * = 1600 + 32 + 16 + 16 + 24 + 80 + 280 (reserved) = 2048 bytes ++ * = 3200 + 32 + 16 + 16 + 24 + 80 + 728 (reserved) = 4096 bytes ++ */ ++typedef struct ++{ ++ MV_U8 buf[MV_CESA_MAX_BUF_SIZE]; ++ MV_CESA_DESC desc; ++ MV_U8 cryptoIV[MV_CESA_MAX_IV_LENGTH]; ++ MV_U8 tempCryptoIV[MV_CESA_MAX_IV_LENGTH]; ++ MV_U8 tempDigest[MV_CESA_MAX_DIGEST_SIZE+4]; ++ MV_CESA_SRAM_SA sramSA; ++ ++} MV_CESA_SRAM_MAP; ++ ++ ++typedef struct ++{ ++ MV_U32 openedCount; ++ MV_U32 closedCount; ++ MV_U32 fragCount; ++ MV_U32 reqCount; ++ MV_U32 maxReqCount; ++ MV_U32 procCount; ++ MV_U32 readyCount; ++ MV_U32 notReadyCount; ++ MV_U32 startCount; ++#if (MV_CESA_VERSION >= 3) ++ MV_U32 maxChainUsage; ++#endif ++ ++} MV_CESA_STATS; ++ ++ ++/* External variables */ ++ ++extern MV_CESA_STATS cesaStats; ++extern MV_CESA_FRAGS cesaFrags; ++ ++extern MV_BUF_INFO cesaSramSaBuf; ++ ++extern MV_CESA_SA* pCesaSAD; ++extern MV_U16 cesaMaxSA; ++ ++extern MV_CESA_REQ* pCesaReqFirst; ++extern MV_CESA_REQ* pCesaReqLast; ++extern MV_CESA_REQ* pCesaReqEmpty; ++extern MV_CESA_REQ* pCesaReqProcess; ++extern int cesaQueueDepth; ++extern int cesaReqResources; ++#if (MV_CESA_VERSION>= 3) ++extern MV_U32 cesaChainLength; ++#endif ++ ++extern MV_CESA_SRAM_MAP* cesaSramVirtPtr; ++extern MV_U32 cesaSramPhysAddr; ++ ++static INLINE MV_ULONG mvCesaVirtToPhys(MV_BUF_INFO* pBufInfo, void* pVirt) ++{ ++ return (pBufInfo->bufPhysAddr + ((MV_U8*)pVirt - pBufInfo->bufVirtPtr)); ++} ++ ++/* Additional DEBUG functions */ ++void mvCesaDebugSramSA(MV_CESA_SRAM_SA* pSramSA, int mode); ++void mvCesaDebugCmd(MV_CESA_COMMAND* pCmd, int mode); ++void mvCesaDebugDescriptor(MV_CESA_DESC* pDesc); ++ ++ ++ ++#endif /* __mvCesa_h__ */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvCesaDebug.c linux-3.0.4/crypto/ocf/kirkwood/cesa/mvCesaDebug.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvCesaDebug.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/cesa/mvCesaDebug.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,484 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#include "mvOs.h" ++#include "mvDebug.h" ++ ++#include "cesa/mvMD5.h" ++#include "cesa/mvSHA1.h" ++ ++#include "cesa/mvCesa.h" ++#include "cesa/mvCesaRegs.h" ++#include "cesa/AES/mvAes.h" ++ ++static const char* mvCesaDebugStateStr(MV_CESA_STATE state) ++{ ++ switch(state) ++ { ++ case MV_CESA_IDLE: ++ return "Idle"; ++ ++ case MV_CESA_PENDING: ++ return "Pend"; ++ ++ case MV_CESA_PROCESS: ++ return "Proc"; ++ ++ case MV_CESA_READY: ++ return "Ready"; ++ ++ default: ++ break; ++ } ++ return "Unknown"; ++} ++ ++static const char* mvCesaDebugOperStr(MV_CESA_OPERATION oper) ++{ ++ switch(oper) ++ { ++ case MV_CESA_MAC_ONLY: ++ return "MacOnly"; ++ ++ case MV_CESA_CRYPTO_ONLY: ++ return "CryptoOnly"; ++ ++ case MV_CESA_MAC_THEN_CRYPTO: ++ return "MacCrypto"; ++ ++ case MV_CESA_CRYPTO_THEN_MAC: ++ return "CryptoMac"; ++ ++ default: ++ break; ++ } ++ return "Null"; ++} ++ ++static const char* mvCesaDebugCryptoAlgStr(MV_CESA_CRYPTO_ALG cryptoAlg) ++{ ++ switch(cryptoAlg) ++ { ++ case MV_CESA_CRYPTO_DES: ++ return "DES"; ++ ++ case MV_CESA_CRYPTO_3DES: ++ return "3DES"; ++ ++ case MV_CESA_CRYPTO_AES: ++ return "AES"; ++ ++ default: ++ break; ++ } ++ return "Null"; ++} ++ ++static const char* mvCesaDebugMacModeStr(MV_CESA_MAC_MODE macMode) ++{ ++ switch(macMode) ++ { ++ case MV_CESA_MAC_MD5: ++ return "MD5"; ++ ++ case MV_CESA_MAC_SHA1: ++ return "SHA1"; ++ ++ case MV_CESA_MAC_HMAC_MD5: ++ return "HMAC-MD5"; ++ ++ case MV_CESA_MAC_HMAC_SHA1: ++ return "HMAC_SHA1"; ++ ++ default: ++ break; ++ } ++ return "Null"; ++} ++ ++void mvCesaDebugCmd(MV_CESA_COMMAND* pCmd, int mode) ++{ ++ mvOsPrintf("pCmd=%p, pReqPrv=%p, pSrc=%p, pDst=%p, pCB=%p, sid=%d\n", ++ pCmd, pCmd->pReqPrv, pCmd->pSrc, pCmd->pDst, ++ pCmd->pFuncCB, pCmd->sessionId); ++ mvOsPrintf("isUser=%d, ivOffs=%d, crOffs=%d, crLen=%d, digest=%d, macOffs=%d, macLen=%d\n", ++ pCmd->ivFromUser, pCmd->ivOffset, pCmd->cryptoOffset, pCmd->cryptoLength, ++ pCmd->digestOffset, pCmd->macOffset, pCmd->macLength); ++} ++ ++/* no need to use in tool */ ++void mvCesaDebugMbuf(const char* str, MV_CESA_MBUF *pMbuf, int offset, int size) ++{ ++ int frag, len, fragOffset; ++ ++ if(str != NULL) ++ mvOsPrintf("%s: pMbuf=%p, numFrags=%d, mbufSize=%d\n", ++ str, pMbuf, pMbuf->numFrags, pMbuf->mbufSize); ++ ++ frag = mvCesaMbufOffset(pMbuf, offset, &fragOffset); ++ if(frag == MV_INVALID) ++ { ++ mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); ++ return; ++ } ++ ++ for(; fragnumFrags; frag++) ++ { ++ mvOsPrintf("#%2d. bufVirt=%p, bufSize=%d\n", ++ frag, pMbuf->pFrags[frag].bufVirtPtr, ++ pMbuf->pFrags[frag].bufSize); ++ if(size > 0) ++ { ++ len = MV_MIN(pMbuf->pFrags[frag].bufSize, size); ++ mvDebugMemDump(pMbuf->pFrags[frag].bufVirtPtr+fragOffset, len, 1); ++ size -= len; ++ fragOffset = 0; ++ } ++ } ++} ++ ++void mvCesaDebugRegs(void) ++{ ++ mvOsPrintf("\t CESA Registers:\n"); ++ ++ mvOsPrintf("MV_CESA_CMD_REG : 0x%X = 0x%08x\n", ++ MV_CESA_CMD_REG, ++ MV_REG_READ( MV_CESA_CMD_REG ) ); ++ ++ mvOsPrintf("MV_CESA_CHAN_DESC_OFFSET_REG : 0x%X = 0x%08x\n", ++ MV_CESA_CHAN_DESC_OFFSET_REG, ++ MV_REG_READ(MV_CESA_CHAN_DESC_OFFSET_REG) ); ++ ++ mvOsPrintf("MV_CESA_CFG_REG : 0x%X = 0x%08x\n", ++ MV_CESA_CFG_REG, ++ MV_REG_READ( MV_CESA_CFG_REG ) ); ++ ++ mvOsPrintf("MV_CESA_STATUS_REG : 0x%X = 0x%08x\n", ++ MV_CESA_STATUS_REG, ++ MV_REG_READ( MV_CESA_STATUS_REG ) ); ++ ++ mvOsPrintf("MV_CESA_ISR_CAUSE_REG : 0x%X = 0x%08x\n", ++ MV_CESA_ISR_CAUSE_REG, ++ MV_REG_READ( MV_CESA_ISR_CAUSE_REG ) ); ++ ++ mvOsPrintf("MV_CESA_ISR_MASK_REG : 0x%X = 0x%08x\n", ++ MV_CESA_ISR_MASK_REG, ++ MV_REG_READ( MV_CESA_ISR_MASK_REG ) ); ++#if (MV_CESA_VERSION >= 2) ++ mvOsPrintf("MV_CESA_TDMA_CTRL_REG : 0x%X = 0x%08x\n", ++ MV_CESA_TDMA_CTRL_REG, ++ MV_REG_READ( MV_CESA_TDMA_CTRL_REG ) ); ++ ++ mvOsPrintf("MV_CESA_TDMA_BYTE_COUNT_REG : 0x%X = 0x%08x\n", ++ MV_CESA_TDMA_BYTE_COUNT_REG, ++ MV_REG_READ( MV_CESA_TDMA_BYTE_COUNT_REG ) ); ++ ++ mvOsPrintf("MV_CESA_TDMA_SRC_ADDR_REG : 0x%X = 0x%08x\n", ++ MV_CESA_TDMA_SRC_ADDR_REG, ++ MV_REG_READ( MV_CESA_TDMA_SRC_ADDR_REG ) ); ++ ++ mvOsPrintf("MV_CESA_TDMA_DST_ADDR_REG : 0x%X = 0x%08x\n", ++ MV_CESA_TDMA_DST_ADDR_REG, ++ MV_REG_READ( MV_CESA_TDMA_DST_ADDR_REG ) ); ++ ++ mvOsPrintf("MV_CESA_TDMA_NEXT_DESC_PTR_REG : 0x%X = 0x%08x\n", ++ MV_CESA_TDMA_NEXT_DESC_PTR_REG, ++ MV_REG_READ( MV_CESA_TDMA_NEXT_DESC_PTR_REG ) ); ++ ++ mvOsPrintf("MV_CESA_TDMA_CURR_DESC_PTR_REG : 0x%X = 0x%08x\n", ++ MV_CESA_TDMA_CURR_DESC_PTR_REG, ++ MV_REG_READ( MV_CESA_TDMA_CURR_DESC_PTR_REG ) ); ++ ++ mvOsPrintf("MV_CESA_TDMA_ERROR_CAUSE_REG : 0x%X = 0x%08x\n", ++ MV_CESA_TDMA_ERROR_CAUSE_REG, ++ MV_REG_READ( MV_CESA_TDMA_ERROR_CAUSE_REG ) ); ++ ++ mvOsPrintf("MV_CESA_TDMA_ERROR_MASK_REG : 0x%X = 0x%08x\n", ++ MV_CESA_TDMA_ERROR_MASK_REG, ++ MV_REG_READ( MV_CESA_TDMA_ERROR_CAUSE_REG ) ); ++ ++#endif ++} ++ ++void mvCesaDebugStatus(void) ++{ ++ mvOsPrintf("\n\t CESA Status\n\n"); ++ ++ mvOsPrintf("pReqQ=%p, qDepth=%d, reqSize=%ld bytes, qRes=%d, ", ++ pCesaReqFirst, cesaQueueDepth, sizeof(MV_CESA_REQ), ++ cesaReqResources); ++#if (MV_CESA_VERSION >= 3) ++ mvOsPrintf("chainLength=%u\n",cesaChainLength); ++#else ++ mvOsPrintf("\n"); ++#endif ++ ++ mvOsPrintf("pSAD=%p, maxSA=%d, sizeSA=%ld bytes\n", ++ pCesaSAD, cesaMaxSA, sizeof(MV_CESA_SA)); ++ ++ mvOsPrintf("\n"); ++ ++ mvCesaDebugRegs(); ++ mvCesaDebugStats(); ++ mvCesaDebugStatsClear(); ++} ++ ++void mvCesaDebugDescriptor(MV_CESA_DESC* pDesc) ++{ ++ mvOsPrintf("config=0x%08x, crSrcOffs=0x%04x, crDstOffs=0x%04x\n", ++ pDesc->config, pDesc->cryptoSrcOffset, pDesc->cryptoDstOffset); ++ ++ mvOsPrintf("crLen=0x%04x, crKeyOffs=0x%04x, ivOffs=0x%04x, ivBufOffs=0x%04x\n", ++ pDesc->cryptoDataLen, pDesc->cryptoKeyOffset, ++ pDesc->cryptoIvOffset, pDesc->cryptoIvBufOffset); ++ ++ mvOsPrintf("macSrc=0x%04x, digest=0x%04x, macLen=0x%04x, inIv=0x%04x, outIv=0x%04x\n", ++ pDesc->macSrcOffset, pDesc->macDigestOffset, pDesc->macDataLen, ++ pDesc->macInnerIvOffset, pDesc->macOuterIvOffset); ++} ++ ++void mvCesaDebugQueue(int mode) ++{ ++ mvOsPrintf("\n\t CESA Request Queue:\n\n"); ++ ++ mvOsPrintf("pFirstReq=%p, pLastReq=%p, qDepth=%d, reqSize=%ld bytes\n", ++ pCesaReqFirst, pCesaReqLast, cesaQueueDepth, sizeof(MV_CESA_REQ)); ++ ++ mvOsPrintf("pEmpty=%p, pProcess=%p, qResources=%d\n", ++ pCesaReqEmpty, pCesaReqProcess, ++ cesaReqResources); ++ ++ if(mode != 0) ++ { ++ int count = 0; ++ MV_CESA_REQ* pReq = pCesaReqFirst; ++ ++ for(count=0; countstate), ++ pReq->fragMode, pReq->pCmd, pReq->dma[0].pDmaFirst, &pReq->pCesaDesc[0]); ++ if(pReq->fragMode != MV_CESA_FRAG_NONE) ++ { ++ int frag; ++ ++ mvOsPrintf("pFrags=%p, num=%d, next=%d, bufOffset=%d, cryptoSize=%d, macSize=%d\n", ++ &pReq->frags, pReq->frags.numFrag, pReq->frags.nextFrag, ++ pReq->frags.bufOffset, pReq->frags.cryptoSize, pReq->frags.macSize); ++ for(frag=0; fragfrags.numFrag; frag++) ++ { ++ mvOsPrintf("#%d: pDmaFirst=%p, pDesc=%p\n", frag, ++ pReq->dma[frag].pDmaFirst, &pReq->pCesaDesc[frag]); ++ } ++ } ++ if(mode > 1) ++ { ++ /* Print out Command */ ++ mvCesaDebugCmd(pReq->pCmd, mode); ++ ++ /* Print out Descriptor */ ++ mvCesaDebugDescriptor(&pReq->pCesaDesc[0]); ++ } ++ pReq++; ++ } ++ } ++} ++ ++ ++void mvCesaDebugSramSA(MV_CESA_SRAM_SA* pSramSA, int mode) ++{ ++ if(pSramSA == NULL) ++ { ++ mvOsPrintf("cesaSramSA: Unexpected pSramSA=%p\n", pSramSA); ++ return; ++ } ++ mvOsPrintf("pSramSA=%p, sizeSramSA=%ld bytes\n", ++ pSramSA, sizeof(MV_CESA_SRAM_SA)); ++ ++ if(mode != 0) ++ { ++ mvOsPrintf("cryptoKey=%p, maxCryptoKey=%d bytes\n", ++ pSramSA->cryptoKey, MV_CESA_MAX_CRYPTO_KEY_LENGTH); ++ mvDebugMemDump(pSramSA->cryptoKey, MV_CESA_MAX_CRYPTO_KEY_LENGTH, 1); ++ ++ mvOsPrintf("macInnerIV=%p, maxInnerIV=%d bytes\n", ++ pSramSA->macInnerIV, MV_CESA_MAX_DIGEST_SIZE); ++ mvDebugMemDump(pSramSA->macInnerIV, MV_CESA_MAX_DIGEST_SIZE, 1); ++ ++ mvOsPrintf("macOuterIV=%p, maxOuterIV=%d bytes\n", ++ pSramSA->macOuterIV, MV_CESA_MAX_DIGEST_SIZE); ++ mvDebugMemDump(pSramSA->macOuterIV, MV_CESA_MAX_DIGEST_SIZE, 1); ++ } ++} ++ ++void mvCesaDebugSA(short sid, int mode) ++{ ++ MV_CESA_OPERATION oper; ++ MV_CESA_DIRECTION dir; ++ MV_CESA_CRYPTO_ALG cryptoAlg; ++ MV_CESA_CRYPTO_MODE cryptoMode; ++ MV_CESA_MAC_MODE macMode; ++ MV_CESA_SA* pSA = &pCesaSAD[sid]; ++ ++ if( (pSA->valid) || ((pSA->count != 0) && (mode > 0)) || (mode >= 2) ) ++ { ++ mvOsPrintf("\n\nCESA SA Entry #%d (%p) - %s (count=%d)\n", ++ sid, pSA, ++ pSA->valid ? "Valid" : "Invalid", pSA->count); ++ ++ oper = (pSA->config & MV_CESA_OPERATION_MASK) >> MV_CESA_OPERATION_OFFSET; ++ dir = (pSA->config & MV_CESA_DIRECTION_MASK) >> MV_CESA_DIRECTION_BIT; ++ mvOsPrintf("%s - %s ", mvCesaDebugOperStr(oper), ++ (dir == MV_CESA_DIR_ENCODE) ? "Encode" : "Decode"); ++ if(oper != MV_CESA_MAC_ONLY) ++ { ++ cryptoAlg = (pSA->config & MV_CESA_CRYPTO_ALG_MASK) >> MV_CESA_CRYPTO_ALG_OFFSET; ++ cryptoMode = (pSA->config & MV_CESA_CRYPTO_MODE_MASK) >> MV_CESA_CRYPTO_MODE_BIT; ++ mvOsPrintf("- %s - %s ", mvCesaDebugCryptoAlgStr(cryptoAlg), ++ (cryptoMode == MV_CESA_CRYPTO_ECB) ? "ECB" : "CBC"); ++ } ++ if(oper != MV_CESA_CRYPTO_ONLY) ++ { ++ macMode = (pSA->config & MV_CESA_MAC_MODE_MASK) >> MV_CESA_MAC_MODE_OFFSET; ++ mvOsPrintf("- %s ", mvCesaDebugMacModeStr(macMode)); ++ } ++ mvOsPrintf("\n"); ++ ++ if(mode > 0) ++ { ++ mvOsPrintf("config=0x%08x, cryptoKeySize=%d, digestSize=%d\n", ++ pCesaSAD[sid].config, pCesaSAD[sid].cryptoKeyLength, ++ pCesaSAD[sid].digestSize); ++ ++ mvCesaDebugSramSA(pCesaSAD[sid].pSramSA, mode); ++ } ++ } ++} ++ ++ ++/**/ ++void mvCesaDebugSram(int mode) ++{ ++ mvOsPrintf("\n\t SRAM contents: size=%ld, pVirt=%p\n\n", ++ sizeof(MV_CESA_SRAM_MAP), cesaSramVirtPtr); ++ ++ mvOsPrintf("\n\t Sram buffer: size=%d, pVirt=%p\n", ++ MV_CESA_MAX_BUF_SIZE, cesaSramVirtPtr->buf); ++ if(mode != 0) ++ mvDebugMemDump(cesaSramVirtPtr->buf, 64, 1); ++ ++ mvOsPrintf("\n"); ++ mvOsPrintf("\n\t Sram descriptor: size=%ld, pVirt=%p\n", ++ sizeof(MV_CESA_DESC), &cesaSramVirtPtr->desc); ++ if(mode != 0) ++ { ++ mvOsPrintf("\n"); ++ mvCesaDebugDescriptor(&cesaSramVirtPtr->desc); ++ } ++ mvOsPrintf("\n\t Sram IV: size=%d, pVirt=%p\n", ++ MV_CESA_MAX_IV_LENGTH, &cesaSramVirtPtr->cryptoIV); ++ if(mode != 0) ++ { ++ mvOsPrintf("\n"); ++ mvDebugMemDump(cesaSramVirtPtr->cryptoIV, MV_CESA_MAX_IV_LENGTH, 1); ++ } ++ mvOsPrintf("\n"); ++ mvCesaDebugSramSA(&cesaSramVirtPtr->sramSA, 0); ++} ++ ++void mvCesaDebugSAD(int mode) ++{ ++ int sid; ++ ++ mvOsPrintf("\n\t Cesa SAD status: pSAD=%p, maxSA=%d\n", ++ pCesaSAD, cesaMaxSA); ++ ++ for(sid=0; sid= 3) ++ mvOsPrintf("maxChainUsage=%u\n",cesaStats.maxChainUsage); ++#endif ++ mvOsPrintf("\n"); ++ mvOsPrintf("proc=%u, ready=%u, notReady=%u\n", ++ cesaStats.procCount, cesaStats.readyCount, cesaStats.notReadyCount); ++} ++ ++void mvCesaDebugStatsClear(void) ++{ ++ memset(&cesaStats, 0, sizeof(cesaStats)); ++} +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvCesaRegs.h linux-3.0.4/crypto/ocf/kirkwood/cesa/mvCesaRegs.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvCesaRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/cesa/mvCesaRegs.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,357 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __mvCesaRegs_h__ ++#define __mvCesaRegs_h__ ++ ++#include "mvTypes.h" ++ ++typedef struct ++{ ++ /* word 0 */ ++ MV_U32 config; ++ /* word 1 */ ++ MV_U16 cryptoSrcOffset; ++ MV_U16 cryptoDstOffset; ++ /* word 2 */ ++ MV_U16 cryptoDataLen; ++ MV_U16 reserved1; ++ /* word 3 */ ++ MV_U16 cryptoKeyOffset; ++ MV_U16 reserved2; ++ /* word 4 */ ++ MV_U16 cryptoIvOffset; ++ MV_U16 cryptoIvBufOffset; ++ /* word 5 */ ++ MV_U16 macSrcOffset; ++ MV_U16 macTotalLen; ++ /* word 6 */ ++ MV_U16 macDigestOffset; ++ MV_U16 macDataLen; ++ /* word 7 */ ++ MV_U16 macInnerIvOffset; ++ MV_U16 macOuterIvOffset; ++ ++} MV_CESA_DESC; ++ ++/* operation */ ++typedef enum ++{ ++ MV_CESA_MAC_ONLY = 0, ++ MV_CESA_CRYPTO_ONLY = 1, ++ MV_CESA_MAC_THEN_CRYPTO = 2, ++ MV_CESA_CRYPTO_THEN_MAC = 3, ++ ++ MV_CESA_MAX_OPERATION ++ ++} MV_CESA_OPERATION; ++ ++#define MV_CESA_OPERATION_OFFSET 0 ++#define MV_CESA_OPERATION_MASK (0x3 << MV_CESA_OPERATION_OFFSET) ++ ++/* mac algorithm */ ++typedef enum ++{ ++ MV_CESA_MAC_NULL = 0, ++ MV_CESA_MAC_MD5 = 4, ++ MV_CESA_MAC_SHA1 = 5, ++ MV_CESA_MAC_HMAC_MD5 = 6, ++ MV_CESA_MAC_HMAC_SHA1 = 7, ++ ++} MV_CESA_MAC_MODE; ++ ++#define MV_CESA_MAC_MODE_OFFSET 4 ++#define MV_CESA_MAC_MODE_MASK (0x7 << MV_CESA_MAC_MODE_OFFSET) ++ ++typedef enum ++{ ++ MV_CESA_MAC_DIGEST_FULL = 0, ++ MV_CESA_MAC_DIGEST_96B = 1, ++ ++} MV_CESA_MAC_DIGEST_SIZE; ++ ++#define MV_CESA_MAC_DIGEST_SIZE_BIT 7 ++#define MV_CESA_MAC_DIGEST_SIZE_MASK (1 << MV_CESA_MAC_DIGEST_SIZE_BIT) ++ ++ ++typedef enum ++{ ++ MV_CESA_CRYPTO_NULL = 0, ++ MV_CESA_CRYPTO_DES = 1, ++ MV_CESA_CRYPTO_3DES = 2, ++ MV_CESA_CRYPTO_AES = 3, ++ ++} MV_CESA_CRYPTO_ALG; ++ ++#define MV_CESA_CRYPTO_ALG_OFFSET 8 ++#define MV_CESA_CRYPTO_ALG_MASK (0x3 << MV_CESA_CRYPTO_ALG_OFFSET) ++ ++ ++/* direction */ ++typedef enum ++{ ++ MV_CESA_DIR_ENCODE = 0, ++ MV_CESA_DIR_DECODE = 1, ++ ++} MV_CESA_DIRECTION; ++ ++#define MV_CESA_DIRECTION_BIT 12 ++#define MV_CESA_DIRECTION_MASK (1 << MV_CESA_DIRECTION_BIT) ++ ++/* crypto IV mode */ ++typedef enum ++{ ++ MV_CESA_CRYPTO_ECB = 0, ++ MV_CESA_CRYPTO_CBC = 1, ++ ++ /* NO HW Support */ ++ MV_CESA_CRYPTO_CTR = 10, ++ ++} MV_CESA_CRYPTO_MODE; ++ ++#define MV_CESA_CRYPTO_MODE_BIT 16 ++#define MV_CESA_CRYPTO_MODE_MASK (1 << MV_CESA_CRYPTO_MODE_BIT) ++ ++/* 3DES mode */ ++typedef enum ++{ ++ MV_CESA_CRYPTO_3DES_EEE = 0, ++ MV_CESA_CRYPTO_3DES_EDE = 1, ++ ++} MV_CESA_CRYPTO_3DES_MODE; ++ ++#define MV_CESA_CRYPTO_3DES_MODE_BIT 20 ++#define MV_CESA_CRYPTO_3DES_MODE_MASK (1 << MV_CESA_CRYPTO_3DES_MODE_BIT) ++ ++ ++/* AES Key Length */ ++typedef enum ++{ ++ MV_CESA_CRYPTO_AES_KEY_128 = 0, ++ MV_CESA_CRYPTO_AES_KEY_192 = 1, ++ MV_CESA_CRYPTO_AES_KEY_256 = 2, ++ ++} MV_CESA_CRYPTO_AES_KEY_LEN; ++ ++#define MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET 24 ++#define MV_CESA_CRYPTO_AES_KEY_LEN_MASK (0x3 << MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET) ++ ++/* Fragmentation mode */ ++typedef enum ++{ ++ MV_CESA_FRAG_NONE = 0, ++ MV_CESA_FRAG_FIRST = 1, ++ MV_CESA_FRAG_LAST = 2, ++ MV_CESA_FRAG_MIDDLE = 3, ++ ++} MV_CESA_FRAG_MODE; ++ ++#define MV_CESA_FRAG_MODE_OFFSET 30 ++#define MV_CESA_FRAG_MODE_MASK (0x3 << MV_CESA_FRAG_MODE_OFFSET) ++/*---------------------------------------------------------------------------*/ ++ ++/********** Security Accelerator Command Register **************/ ++#define MV_CESA_CMD_REG (MV_CESA_REG_BASE + 0xE00) ++ ++#define MV_CESA_CMD_CHAN_ENABLE_BIT 0 ++#define MV_CESA_CMD_CHAN_ENABLE_MASK (1 << MV_CESA_CMD_CHAN_ENABLE_BIT) ++ ++#define MV_CESA_CMD_CHAN_DISABLE_BIT 2 ++#define MV_CESA_CMD_CHAN_DISABLE_MASK (1 << MV_CESA_CMD_CHAN_DISABLE_BIT) ++ ++/********** Security Accelerator Descriptor Pointers Register **********/ ++#define MV_CESA_CHAN_DESC_OFFSET_REG (MV_CESA_REG_BASE + 0xE04) ++ ++/********** Security Accelerator Configuration Register **********/ ++#define MV_CESA_CFG_REG (MV_CESA_REG_BASE + 0xE08) ++ ++#define MV_CESA_CFG_STOP_DIGEST_ERR_BIT 0 ++#define MV_CESA_CFG_STOP_DIGEST_ERR_MASK (1 << MV_CESA_CFG_STOP_DIGEST_ERR_BIT) ++ ++#define MV_CESA_CFG_WAIT_DMA_BIT 7 ++#define MV_CESA_CFG_WAIT_DMA_MASK (1 << MV_CESA_CFG_WAIT_DMA_BIT) ++ ++#define MV_CESA_CFG_ACT_DMA_BIT 9 ++#define MV_CESA_CFG_ACT_DMA_MASK (1 << MV_CESA_CFG_ACT_DMA_BIT) ++ ++#define MV_CESA_CFG_CHAIN_MODE_BIT 11 ++#define MV_CESA_CFG_CHAIN_MODE_MASK (1 << MV_CESA_CFG_CHAIN_MODE_BIT) ++ ++/********** Security Accelerator Status Register ***********/ ++#define MV_CESA_STATUS_REG (MV_CESA_REG_BASE + 0xE0C) ++ ++#define MV_CESA_STATUS_ACTIVE_BIT 0 ++#define MV_CESA_STATUS_ACTIVE_MASK (1 << MV_CESA_STATUS_ACTIVE_BIT) ++ ++#define MV_CESA_STATUS_DIGEST_ERR_BIT 8 ++#define MV_CESA_STATUS_DIGEST_ERR_MASK (1 << MV_CESA_STATUS_DIGEST_ERR_BIT) ++ ++ ++/* Cryptographic Engines and Security Accelerator Interrupt Cause Register */ ++#define MV_CESA_ISR_CAUSE_REG (MV_CESA_REG_BASE + 0xE20) ++ ++/* Cryptographic Engines and Security Accelerator Interrupt Mask Register */ ++#define MV_CESA_ISR_MASK_REG (MV_CESA_REG_BASE + 0xE24) ++ ++#define MV_CESA_CAUSE_AUTH_MASK (1 << 0) ++#define MV_CESA_CAUSE_DES_MASK (1 << 1) ++#define MV_CESA_CAUSE_AES_ENCR_MASK (1 << 2) ++#define MV_CESA_CAUSE_AES_DECR_MASK (1 << 3) ++#define MV_CESA_CAUSE_DES_ALL_MASK (1 << 4) ++ ++#define MV_CESA_CAUSE_ACC_BIT 5 ++#define MV_CESA_CAUSE_ACC_MASK (1 << MV_CESA_CAUSE_ACC_BIT) ++ ++#define MV_CESA_CAUSE_ACC_DMA_BIT 7 ++#define MV_CESA_CAUSE_ACC_DMA_MASK (1 << MV_CESA_CAUSE_ACC_DMA_BIT) ++#define MV_CESA_CAUSE_ACC_DMA_ALL_MASK (3 << MV_CESA_CAUSE_ACC_DMA_BIT) ++ ++#define MV_CESA_CAUSE_DMA_COMPL_BIT 9 ++#define MV_CESA_CAUSE_DMA_COMPL_MASK (1 << MV_CESA_CAUSE_DMA_COMPL_BIT) ++ ++#define MV_CESA_CAUSE_DMA_OWN_ERR_BIT 10 ++#define MV_CESA_CAUSE_DMA_OWN_ERR_MASK (1 < MV_CESA_CAUSE_DMA_OWN_ERR_BIT) ++ ++#define MV_CESA_CAUSE_DMA_CHAIN_PKT_BIT 11 ++#define MV_CESA_CAUSE_DMA_CHAIN_PKT_MASK (1 < MV_CESA_CAUSE_DMA_CHAIN_PKT_BIT) ++ ++ ++#define MV_CESA_AUTH_DATA_IN_REG (MV_CESA_REG_BASE + 0xd38) ++#define MV_CESA_AUTH_BIT_COUNT_LOW_REG (MV_CESA_REG_BASE + 0xd20) ++#define MV_CESA_AUTH_BIT_COUNT_HIGH_REG (MV_CESA_REG_BASE + 0xd24) ++ ++#define MV_CESA_AUTH_INIT_VAL_DIGEST_REG(i) (MV_CESA_REG_BASE + 0xd00 + (i<<2)) ++ ++#define MV_CESA_AUTH_INIT_VAL_DIGEST_A_REG (MV_CESA_REG_BASE + 0xd00) ++#define MV_CESA_AUTH_INIT_VAL_DIGEST_B_REG (MV_CESA_REG_BASE + 0xd04) ++#define MV_CESA_AUTH_INIT_VAL_DIGEST_C_REG (MV_CESA_REG_BASE + 0xd08) ++#define MV_CESA_AUTH_INIT_VAL_DIGEST_D_REG (MV_CESA_REG_BASE + 0xd0c) ++#define MV_CESA_AUTH_INIT_VAL_DIGEST_E_REG (MV_CESA_REG_BASE + 0xd10) ++#define MV_CESA_AUTH_COMMAND_REG (MV_CESA_REG_BASE + 0xd18) ++ ++#define MV_CESA_AUTH_ALGORITHM_BIT 0 ++#define MV_CESA_AUTH_ALGORITHM_MD5 (0< ++wait_queue_head_t cesaTest_waitq; ++spinlock_t cesaLock; ++ ++#define CESA_TEST_LOCK(flags) spin_lock_irqsave( &cesaLock, flags) ++#define CESA_TEST_UNLOCK(flags) spin_unlock_irqrestore( &cesaLock, flags); ++ ++#define CESA_TEST_WAIT_INIT() init_waitqueue_head(&cesaTest_waitq) ++#define CESA_TEST_WAKE_UP() wake_up(&cesaTest_waitq) ++#define CESA_TEST_WAIT(cond, ms) wait_event_timeout(cesaTest_waitq, (cond), msecs_to_jiffies(ms)) ++ ++#define CESA_TEST_TICK_GET() jiffies ++#define CESA_TEST_TICK_TO_MS(tick) jiffies_to_msecs(tick) ++ ++#elif defined(MV_NETBSD) ++ ++#include ++#include ++static int cesaLock; ++ ++#define CESA_TEST_LOCK(flags) flags = splnet() ++#define CESA_TEST_UNLOCK(flags) splx(flags) ++ ++#define CESA_TEST_WAIT_INIT() /* nothing */ ++#define CESA_TEST_WAKE_UP() wakeup(&cesaLock) ++#define CESA_TEST_WAIT(cond, ms) \ ++do { \ ++ while (!(cond)) \ ++ tsleep(&cesaLock, PWAIT, "cesatest",mstohz(ms)); \ ++} while (/*CONSTCOND*/0) ++ ++#define CESA_TEST_TICK_GET() hardclock_ticks ++#define CESA_TEST_TICK_TO_MS(tick) ((1000/hz)*(tick)) ++ ++#define request_irq(i,h,t,n,a) \ ++ !mv_intr_establish((i),IPL_NET,(int(*)(void *))(h),(a)) ++ ++#else ++#error "Only Linux, VxWorks, or NetBSD OS are supported" ++#endif ++ ++#include "mvDebug.h" ++ ++#include "mvSysHwConfig.h" ++#include "boardEnv/mvBoardEnvLib.h" ++#include "ctrlEnv/sys/mvCpuIf.h" ++#include "cntmr/mvCntmr.h" ++#include "cesa/mvCesa.h" ++#include "cesa/mvCesaRegs.h" ++#include "cesa/mvMD5.h" ++#include "cesa/mvSHA1.h" ++ ++#if defined(CONFIG_MV646xx) ++#include "marvell_pic.h" ++#endif ++ ++#define MV_CESA_USE_TIMER_ID 0 ++#define CESA_DEF_BUF_SIZE 1500 ++#define CESA_DEF_BUF_NUM 1 ++#define CESA_DEF_SESSION_NUM 32 ++ ++#define CESA_DEF_ITER_NUM 100 ++ ++#define CESA_DEF_REQ_SIZE 256 ++ ++ ++/* CESA Tests Debug */ ++#undef CESA_TEST_DEBUG ++ ++#ifdef CESA_TEST_DEBUG ++ ++# define CESA_TEST_DEBUG_PRINT(msg) mvOsPrintf msg ++# define CESA_TEST_DEBUG_CODE(code) code ++ ++typedef struct ++{ ++ int type; /* 0 - isrEmpty, 1 - cesaReadyGet, 2 - cesaAction */ ++ MV_U32 timeStamp; ++ MV_U32 cause; ++ MV_U32 realCause; ++ MV_U32 dmaCause; ++ int resources; ++ MV_CESA_REQ* pReqReady; ++ MV_CESA_REQ* pReqEmpty; ++ MV_CESA_REQ* pReqProcess; ++} MV_CESA_TEST_TRACE; ++ ++#define MV_CESA_TEST_TRACE_SIZE 25 ++ ++static int cesaTestTraceIdx = 0; ++static MV_CESA_TEST_TRACE cesaTestTrace[MV_CESA_TEST_TRACE_SIZE]; ++ ++static void cesaTestTraceAdd(int type, MV_U32 cause) ++{ ++ cesaTestTrace[cesaTestTraceIdx].type = type; ++ cesaTestTrace[cesaTestTraceIdx].cause = cause; ++ cesaTestTrace[cesaTestTraceIdx].realCause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); ++ cesaTestTrace[cesaTestTraceIdx].dmaCause = MV_REG_READ(IDMA_CAUSE_REG); ++ cesaTestTrace[cesaTestTraceIdx].resources = cesaReqResources; ++ cesaTestTrace[cesaTestTraceIdx].pReqReady = pCesaReqReady; ++ cesaTestTrace[cesaTestTraceIdx].pReqEmpty = pCesaReqEmpty; ++ cesaTestTrace[cesaTestTraceIdx].pReqProcess = pCesaReqProcess; ++ cesaTestTrace[cesaTestTraceIdx].timeStamp = mvCntmrRead(MV_CESA_USE_TIMER_ID); ++ cesaTestTraceIdx++; ++ if(cesaTestTraceIdx == MV_CESA_TEST_TRACE_SIZE) ++ cesaTestTraceIdx = 0; ++} ++ ++#else ++ ++# define CESA_TEST_DEBUG_PRINT(msg) ++# define CESA_TEST_DEBUG_CODE(code) ++ ++#endif /* CESA_TEST_DEBUG */ ++ ++int cesaExpReqId=0; ++int cesaCbIter=0; ++ ++int cesaIdx; ++int cesaIteration; ++int cesaRateSize; ++int cesaReqSize; ++unsigned long cesaTaskId; ++int cesaBufNum; ++int cesaBufSize; ++int cesaCheckOffset; ++int cesaCheckSize; ++int cesaCheckMode; ++int cesaTestIdx; ++int cesaCaseIdx; ++ ++ ++MV_U32 cesaTestIsrCount = 0; ++MV_U32 cesaTestIsrMissCount = 0; ++ ++MV_U32 cesaCryptoError = 0; ++MV_U32 cesaReqIdError = 0; ++MV_U32 cesaError = 0; ++ ++char* cesaHexBuffer = NULL; ++ ++char* cesaBinBuffer = NULL; ++char* cesaExpBinBuffer = NULL; ++ ++char* cesaInputHexStr = NULL; ++char* cesaOutputHexStr = NULL; ++ ++MV_BUF_INFO cesaReqBufs[CESA_DEF_REQ_SIZE]; ++ ++MV_CESA_COMMAND* cesaCmdRing; ++MV_CESA_RESULT cesaResult; ++ ++int cesaTestFull = 0; ++ ++MV_BOOL cesaIsReady = MV_FALSE; ++MV_U32 cesaCycles = 0; ++MV_U32 cesaBeginTicks = 0; ++MV_U32 cesaEndTicks = 0; ++MV_U32 cesaRate = 0; ++MV_U32 cesaRateAfterDot = 0; ++ ++void *cesaTestOSHandle = NULL; ++ ++enum ++{ ++ CESA_FAST_CHECK_MODE = 0, ++ CESA_FULL_CHECK_MODE, ++ CESA_NULL_CHECK_MODE, ++ CESA_SHOW_CHECK_MODE, ++ CESA_SW_SHOW_CHECK_MODE, ++ CESA_SW_NULL_CHECK_MODE, ++ ++ CESA_MAX_CHECK_MODE ++}; ++ ++enum ++{ ++ DES_TEST_TYPE = 0, ++ TRIPLE_DES_TEST_TYPE = 1, ++ AES_TEST_TYPE = 2, ++ MD5_TEST_TYPE = 3, ++ SHA_TEST_TYPE = 4, ++ COMBINED_TEST_TYPE = 5, ++ ++ MAX_TEST_TYPE ++}; ++ ++/* Tests data base */ ++typedef struct ++{ ++ short sid; ++ char cryptoAlgorithm; /* DES/3DES/AES */ ++ char cryptoMode; /* ECB or CBC */ ++ char macAlgorithm; /* MD5 / SHA1 */ ++ char operation; /* CRYPTO/HMAC/CRYPTO+HMAC/HMAC+CRYPTO */ ++ char direction; /* ENCODE(SIGN)/DECODE(VERIFY) */ ++ unsigned char* pCryptoKey; ++ int cryptoKeySize; ++ unsigned char* pMacKey; ++ int macKeySize; ++ const char* name; ++ ++} MV_CESA_TEST_SESSION; ++ ++typedef struct ++{ ++ MV_CESA_TEST_SESSION* pSessions; ++ int numSessions; ++ ++} MV_CESA_TEST_DB_ENTRY; ++ ++typedef struct ++{ ++ char* plainHexStr; ++ char* cipherHexStr; ++ unsigned char* pCryptoIV; ++ int cryptoLength; ++ int macLength; ++ int digestOffset; ++ ++} MV_CESA_TEST_CASE; ++ ++typedef struct ++{ ++ int size; ++ const char* outputHexStr; ++ ++} MV_CESA_SIZE_TEST; ++ ++static unsigned char cryptoKey1[] = {0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, ++ 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, ++ 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef}; ++ ++static unsigned char cryptoKey7[] = {0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef}; ++static unsigned char iv1[] = {0x12, 0x34, 0x56, 0x78, 0x90, 0xab, 0xcd, 0xef}; ++ ++ ++static unsigned char cryptoKey2[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, ++ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F}; ++ ++static unsigned char cryptoKey3[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, ++ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, ++ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17}; ++ ++static unsigned char cryptoKey4[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, ++ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, ++ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, ++ 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f}; ++ ++static unsigned char cryptoKey5[] = {0x56, 0xe4, 0x7a, 0x38, 0xc5, 0x59, 0x89, 0x74, ++ 0xbc, 0x46, 0x90, 0x3d, 0xba, 0x29, 0x03, 0x49}; ++ ++ ++static unsigned char key3des1[] = {0x01, 0x23, 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF, ++ 0x23, 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF, 0x01, ++ 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF, 0x01, 0x23}; ++ ++/* Input ASCII string: The quick brown fox jump */ ++static char plain3des1[] = "54686520717566636B2062726F776E20666F78206A756D70"; ++static char cipher3des1[] = "A826FD8CE53B855FCCE21C8112256FE668D5C05DD9B6B900"; ++ ++static unsigned char key3des2[] = {0x62, 0x7f, 0x46, 0x0e, 0x08, 0x10, 0x4a, 0x10, ++ 0x43, 0xcd, 0x26, 0x5d, 0x58, 0x40, 0xea, 0xf1, ++ 0x31, 0x3e, 0xdf, 0x97, 0xdf, 0x2a, 0x8a, 0x8c}; ++ ++static unsigned char iv3des2[] = {0x8e, 0x29, 0xf7, 0x5e, 0xa7, 0x7e, 0x54, 0x75}; ++ ++static char plain3des2[] = "326a494cd33fe756"; ++ ++static char cipher3desCbc2[] = "8e29f75ea77e5475" ++ "b22b8d66de970692"; ++ ++static unsigned char key3des3[] = {0x37, 0xae, 0x5e, 0xbf, 0x46, 0xdf, 0xf2, 0xdc, ++ 0x07, 0x54, 0xb9, 0x4f, 0x31, 0xcb, 0xb3, 0x85, ++ 0x5e, 0x7f, 0xd3, 0x6d, 0xc8, 0x70, 0xbf, 0xae}; ++ ++static unsigned char iv3des3[] = {0x3d, 0x1d, 0xe3, 0xcc, 0x13, 0x2e, 0x3b, 0x65}; ++ ++static char plain3des3[] = "84401f78fe6c10876d8ea23094ea5309"; ++ ++static char cipher3desCbc3[] = "3d1de3cc132e3b65" ++ "7b1f7c7e3b1c948ebd04a75ffba7d2f5"; ++ ++static unsigned char iv5[] = {0x8c, 0xe8, 0x2e, 0xef, 0xbe, 0xa0, 0xda, 0x3c, ++ 0x44, 0x69, 0x9e, 0xd7, 0xdb, 0x51, 0xb7, 0xd9}; ++ ++static unsigned char aesCtrKey[] = {0x76, 0x91, 0xBE, 0x03, 0x5E, 0x50, 0x20, 0xA8, ++ 0xAC, 0x6E, 0x61, 0x85, 0x29, 0xF9, 0xA0, 0xDC}; ++ ++static unsigned char mdKey1[] = {0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, ++ 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b}; ++ ++static unsigned char mdKey2[] = {0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, ++ 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa}; ++ ++static unsigned char shaKey1[] = {0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, ++ 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, ++ 0x0b, 0x0b, 0x0b, 0x0b}; ++ ++static unsigned char shaKey2[] = {0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, ++ 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, ++ 0xaa, 0xaa, 0xaa, 0xaa}; ++ ++static unsigned char mdKey4[] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, ++ 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10}; ++ ++static unsigned char shaKey4[] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, ++ 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10, ++ 0x11, 0x12, 0x13, 0x14}; ++ ++ ++static MV_CESA_TEST_SESSION desTestSessions[] = ++{ ++/*000*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey7, sizeof(cryptoKey7)/sizeof(cryptoKey7[0]), ++ NULL, 0, ++ "DES ECB encode", ++ }, ++/*001*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_DECODE, ++ cryptoKey7, sizeof(cryptoKey7)/sizeof(cryptoKey7[0]), ++ NULL, 0, ++ "DES ECB decode", ++ }, ++/*002*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_CBC, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey7, sizeof(cryptoKey7)/sizeof(cryptoKey7[0]), ++ NULL, 0, ++ "DES CBC encode" ++ }, ++/*003*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_CBC, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_DECODE, ++ cryptoKey7, sizeof(cryptoKey7)/sizeof(cryptoKey7[0]), ++ NULL, 0, ++ "DES CBC decode" ++ }, ++/*004*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ NULL, 0, NULL, 0, ++ "NULL Crypto Algorithm encode" ++ }, ++}; ++ ++ ++static MV_CESA_TEST_SESSION tripleDesTestSessions[] = ++{ ++/*100*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), ++ NULL, 0, ++ "3DES ECB encode", ++ }, ++/*101*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_DECODE, ++ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), ++ NULL, 0, ++ "3DES ECB decode", ++ }, ++/*102*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), ++ NULL, 0, ++ "3DES CBC encode" ++ }, ++/*103*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_DECODE, ++ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), ++ NULL, 0, ++ "3DES CBC decode" ++ }, ++/*104*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ key3des1, sizeof(key3des1), ++ NULL, 0, ++ "3DES ECB encode" ++ }, ++/*105*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ key3des2, sizeof(key3des2), ++ NULL, 0, ++ "3DES ECB encode" ++ }, ++/*106*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ key3des3, sizeof(key3des3), ++ NULL, 0, ++ "3DES ECB encode" ++ }, ++}; ++ ++ ++static MV_CESA_TEST_SESSION aesTestSessions[] = ++{ ++/*200*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey2, sizeof(cryptoKey2)/sizeof(cryptoKey2[0]), ++ NULL, 0, ++ "AES-128 ECB encode" ++ }, ++/*201*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_DECODE, ++ cryptoKey2, sizeof(cryptoKey2)/sizeof(cryptoKey2[0]), ++ NULL, 0, ++ "AES-128 ECB decode" ++ }, ++/*202*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey5, sizeof(cryptoKey5)/sizeof(cryptoKey5[0]), ++ NULL, 0, ++ "AES-128 CBC encode" ++ }, ++/*203*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_DECODE, ++ cryptoKey5, sizeof(cryptoKey5)/sizeof(cryptoKey5[0]), ++ NULL, 0, ++ "AES-128 CBC decode" ++ }, ++/*204*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey3, sizeof(cryptoKey3)/sizeof(cryptoKey3[0]), ++ NULL, 0, ++ "AES-192 ECB encode" ++ }, ++/*205*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_DECODE, ++ cryptoKey3, sizeof(cryptoKey3)/sizeof(cryptoKey3[0]), ++ NULL, 0, ++ "AES-192 ECB decode" ++ }, ++/*206*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey4, sizeof(cryptoKey4)/sizeof(cryptoKey4[0]), ++ NULL, 0, ++ "AES-256 ECB encode" ++ }, ++/*207*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_DECODE, ++ cryptoKey4, sizeof(cryptoKey4)/sizeof(cryptoKey4[0]), ++ NULL, 0, ++ "AES-256 ECB decode" ++ }, ++/*208*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CTR, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ aesCtrKey, sizeof(aesCtrKey)/sizeof(aesCtrKey[0]), ++ NULL, 0, ++ "AES-128 CTR encode" ++ }, ++}; ++ ++ ++static MV_CESA_TEST_SESSION md5TestSessions[] = ++{ ++/*300*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, ++ MV_CESA_DIR_ENCODE, ++ NULL, 0, ++ mdKey1, sizeof(mdKey1), ++ "HMAC-MD5 Generate Signature" ++ }, ++/*301*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, ++ MV_CESA_DIR_DECODE, ++ NULL, 0, ++ mdKey1, sizeof(mdKey1), ++ "HMAC-MD5 Verify Signature" ++ }, ++/*302*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, ++ MV_CESA_DIR_ENCODE, ++ NULL, 0, ++ mdKey2, sizeof(mdKey2), ++ "HMAC-MD5 Generate Signature" ++ }, ++/*303*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, ++ MV_CESA_DIR_DECODE, ++ NULL, 0, ++ mdKey2, sizeof(mdKey2), ++ "HMAC-MD5 Verify Signature" ++ }, ++/*304*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, ++ MV_CESA_DIR_ENCODE, ++ NULL, 0, ++ mdKey4, sizeof(mdKey4), ++ "HMAC-MD5 Generate Signature" ++ }, ++/*305*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_MD5, MV_CESA_MAC_ONLY, ++ MV_CESA_DIR_ENCODE, ++ NULL, 0, ++ NULL, 0, ++ "HASH-MD5 Generate Signature" ++ }, ++}; ++ ++ ++static MV_CESA_TEST_SESSION shaTestSessions[] = ++{ ++/*400*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, ++ MV_CESA_DIR_ENCODE, ++ NULL, 0, ++ shaKey1, sizeof(shaKey1), ++ "HMAC-SHA1 Generate Signature" ++ }, ++/*401*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, ++ MV_CESA_DIR_DECODE, ++ NULL, 0, ++ shaKey1, sizeof(shaKey1), ++ "HMAC-SHA1 Verify Signature" ++ }, ++/*402*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, ++ MV_CESA_DIR_ENCODE, ++ NULL, 0, ++ shaKey2, sizeof(shaKey2), ++ "HMAC-SHA1 Generate Signature" ++ }, ++/*403*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, ++ MV_CESA_DIR_DECODE, ++ NULL, 0, ++ shaKey2, sizeof(shaKey2), ++ "HMAC-SHA1 Verify Signature" ++ }, ++/*404*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, ++ MV_CESA_DIR_ENCODE, ++ NULL, 0, ++ shaKey4, sizeof(shaKey4), ++ "HMAC-SHA1 Generate Signature" ++ }, ++/*405*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_SHA1, MV_CESA_MAC_ONLY, ++ MV_CESA_DIR_ENCODE, ++ NULL, 0, ++ NULL, 0, ++ "HASH-SHA1 Generate Signature" ++ }, ++}; ++ ++static MV_CESA_TEST_SESSION combinedTestSessions[] = ++{ ++/*500*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey1, MV_CESA_DES_KEY_LENGTH, ++ mdKey4, sizeof(mdKey4), ++ "DES + MD5 encode" ++ }, ++/*501*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey1, MV_CESA_DES_KEY_LENGTH, ++ shaKey4, sizeof(shaKey4), ++ "DES + SHA1 encode" ++ }, ++/*502*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), ++ mdKey4, sizeof(mdKey4), ++ "3DES + MD5 encode" ++ }, ++/*503*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), ++ shaKey4, sizeof(shaKey4), ++ "3DES + SHA1 encode" ++ }, ++/*504*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, ++ MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), ++ mdKey4, sizeof(mdKey4), ++ "3DES CBC + MD5 encode" ++ }, ++/*505*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, ++ MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), ++ shaKey4, sizeof(shaKey4), ++ "3DES CBC + SHA1 encode" ++ }, ++/*506*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, ++ MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey5, sizeof(cryptoKey5)/sizeof(cryptoKey5[0]), ++ mdKey4, sizeof(mdKey4), ++ "AES-128 CBC + MD5 encode" ++ }, ++/*507*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, ++ MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey5, sizeof(cryptoKey5)/sizeof(cryptoKey5[0]), ++ shaKey4, sizeof(shaKey4), ++ "AES-128 CBC + SHA1 encode" ++ }, ++/*508*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_THEN_CRYPTO, ++ MV_CESA_DIR_DECODE, ++ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), ++ mdKey4, sizeof(mdKey4), ++ "HMAC-MD5 + 3DES decode" ++ }, ++}; ++ ++ ++static MV_CESA_TEST_DB_ENTRY cesaTestsDB[MAX_TEST_TYPE+1] = ++{ ++ { desTestSessions, sizeof(desTestSessions)/sizeof(desTestSessions[0]) }, ++ { tripleDesTestSessions, sizeof(tripleDesTestSessions)/sizeof(tripleDesTestSessions[0]) }, ++ { aesTestSessions, sizeof(aesTestSessions)/sizeof(aesTestSessions[0]) }, ++ { md5TestSessions, sizeof(md5TestSessions)/sizeof(md5TestSessions[0]) }, ++ { shaTestSessions, sizeof(shaTestSessions)/sizeof(shaTestSessions[0]) }, ++ { combinedTestSessions, sizeof(combinedTestSessions)/sizeof(combinedTestSessions[0]) }, ++ { NULL, 0 } ++}; ++ ++ ++char cesaNullPlainHexText[] = "000000000000000000000000000000000000000000000000"; ++ ++char cesaPlainAsciiText[] = "Now is the time for all "; ++char cesaPlainHexEbc[] = "4e6f77206973207468652074696d6520666f7220616c6c20"; ++char cesaCipherHexEcb[] = "3fa40e8a984d48156a271787ab8883f9893d51ec4b563b53"; ++char cesaPlainHexCbc[] = "1234567890abcdef4e6f77206973207468652074696d6520666f7220616c6c20"; ++char cesaCipherHexCbc[] = "1234567890abcdefe5c7cdde872bf27c43e934008c389c0f683788499a7c05f6"; ++ ++char cesaAesPlainHexEcb[] = "000102030405060708090a0b0c0d0e0f"; ++char cesaAes128cipherHexEcb[] = "0a940bb5416ef045f1c39458c653ea5a"; ++char cesaAes192cipherHexEcb[] = "0060bffe46834bb8da5cf9a61ff220ae"; ++char cesaAes256cipherHexEcb[] = "5a6e045708fb7196f02e553d02c3a692"; ++ ++char cesaAsciiStr1[] = "Hi There"; ++char cesaDataHexStr1[] = "4869205468657265"; ++char cesaHmacMd5digestHex1[] = "9294727a3638bb1c13f48ef8158bfc9d"; ++char cesaHmacSha1digestHex1[] = "b617318655057264e28bc0b6fb378c8ef146be00"; ++char cesaDataAndMd5digest1[] = "48692054686572659294727a3638bb1c13f48ef8158bfc9d"; ++char cesaDataAndSha1digest1[] = "4869205468657265b617318655057264e28bc0b6fb378c8ef146be00"; ++ ++char cesaAesPlainText[] = "a0a1a2a3a4a5a6a7a8a9aaabacadaeaf" ++ "b0b1b2b3b4b5b6b7b8b9babbbcbdbebf" ++ "c0c1c2c3c4c5c6c7c8c9cacbcccdcecf" ++ "d0d1d2d3d4d5d6d7d8d9dadbdcdddedf"; ++ ++char cesaAes128CipherCbc[] = "c30e32ffedc0774e6aff6af0869f71aa" ++ "0f3af07a9a31a9c684db207eb0ef8e4e" ++ "35907aa632c3ffdf868bb7b29d3d46ad" ++ "83ce9f9a102ee99d49a53e87f4c3da55"; ++ ++char cesaAesIvPlainText[] = "8ce82eefbea0da3c44699ed7db51b7d9" ++ "a0a1a2a3a4a5a6a7a8a9aaabacadaeaf" ++ "b0b1b2b3b4b5b6b7b8b9babbbcbdbebf" ++ "c0c1c2c3c4c5c6c7c8c9cacbcccdcecf" ++ "d0d1d2d3d4d5d6d7d8d9dadbdcdddedf"; ++ ++char cesaAes128IvCipherCbc[] = "8ce82eefbea0da3c44699ed7db51b7d9" ++ "c30e32ffedc0774e6aff6af0869f71aa" ++ "0f3af07a9a31a9c684db207eb0ef8e4e" ++ "35907aa632c3ffdf868bb7b29d3d46ad" ++ "83ce9f9a102ee99d49a53e87f4c3da55"; ++ ++char cesaAesCtrPlain[] = "00E0017B27777F3F4A1786F000000001" ++ "000102030405060708090A0B0C0D0E0F" ++ "101112131415161718191A1B1C1D1E1F" ++ "20212223"; ++ ++char cesaAesCtrCipher[] = "00E0017B27777F3F4A1786F000000001" ++ "C1CF48A89F2FFDD9CF4652E9EFDB72D7" ++ "4540A42BDE6D7836D59A5CEAAEF31053" ++ "25B2072F"; ++ ++ ++ ++/* Input cesaHmacHex3 is '0xdd' repeated 50 times */ ++char cesaHmacMd5digestHex3[] = "56be34521d144c88dbb8c733f0e8b3f6"; ++char cesaHmacSha1digestHex3[] = "125d7342b9ac11cd91a39af48aa17b4f63f175d3"; ++char cesaDataHexStr3[50*2+1] = ""; ++char cesaDataAndMd5digest3[sizeof(cesaDataHexStr3)+sizeof(cesaHmacMd5digestHex3)+8*2+1] = ""; ++char cesaDataAndSha1digest3[sizeof(cesaDataHexStr3)+sizeof(cesaHmacSha1digestHex3)+8*2+1] = ""; ++ ++/* Ascii string is "abc" */ ++char hashHexStr3[] = "616263"; ++char hashMd5digest3[] = "900150983cd24fb0d6963f7d28e17f72"; ++char hashSha1digest3[] = "a9993e364706816aba3e25717850c26c9cd0d89d"; ++ ++char hashHexStr80[] = "31323334353637383930" ++ "31323334353637383930" ++ "31323334353637383930" ++ "31323334353637383930" ++ "31323334353637383930" ++ "31323334353637383930" ++ "31323334353637383930" ++ "31323334353637383930"; ++ ++char hashMd5digest80[] = "57edf4a22be3c955ac49da2e2107b67a"; ++ ++char tripleDesThenMd5digest80[] = "b7726a03aad490bd6c5a452a89a1b271"; ++char tripleDesThenSha1digest80[] = "b2ddeaca91030eab5b95a234ef2c0f6e738ff883"; ++ ++char cbc3desThenMd5digest80[] = "6f463057e1a90e0e91ae505b527bcec0"; ++char cbc3desThenSha1digest80[] = "1b002ed050be743aa98860cf35659646bb8efcc0"; ++ ++char cbcAes128ThenMd5digest80[] = "6b6e863ac5a71d15e3e9b1c86c9ba05f"; ++char cbcAes128ThenSha1digest80[] = "13558472d1fc1c90dffec6e5136c7203452d509b"; ++ ++ ++static MV_CESA_TEST_CASE cesaTestCases[] = ++{ ++ /* plainHexStr cipherHexStr IV crypto mac digest */ ++ /* Length Length Offset */ ++ /*0*/ { NULL, NULL, NULL, 0, 0, -1 }, ++ /*1*/ { cesaPlainHexEbc, cesaCipherHexEcb, NULL, 24, 0, -1 }, ++ /*2*/ { cesaPlainHexCbc, cesaCipherHexCbc, NULL, 24, 0, -1 }, ++ /*3*/ { cesaAesPlainHexEcb, cesaAes128cipherHexEcb, NULL, 16, 0, -1 }, ++ /*4*/ { cesaAesPlainHexEcb, cesaAes192cipherHexEcb, NULL, 16, 0, -1 }, ++ /*5*/ { cesaAesPlainHexEcb, cesaAes256cipherHexEcb, NULL, 16, 0, -1 }, ++ /*6*/ { cesaDataHexStr1, cesaHmacMd5digestHex1, NULL, 0, 8, -1 }, ++ /*7*/ { NULL, cesaDataAndMd5digest1, NULL, 0, 8, -1 }, ++ /*8*/ { cesaDataHexStr3, cesaHmacMd5digestHex3, NULL, 0, 50, -1 }, ++ /*9*/ { NULL, cesaDataAndMd5digest3, NULL, 0, 50, -1 }, ++/*10*/ { cesaAesPlainText, cesaAes128IvCipherCbc, iv5, 64, 0, -1 }, ++/*11*/ { cesaDataHexStr1, cesaHmacSha1digestHex1, NULL, 0, 8, -1 }, ++/*12*/ { NULL, cesaDataAndSha1digest1, NULL, 0, 8, -1 }, ++/*13*/ { cesaDataHexStr3, cesaHmacSha1digestHex3, NULL, 0, 50, -1 }, ++/*14*/ { NULL, cesaDataAndSha1digest3, NULL, 0, 50, -1 }, ++/*15*/ { hashHexStr3, hashMd5digest3, NULL, 0, 3, -1 }, ++/*16*/ { hashHexStr3, hashSha1digest3, NULL, 0, 3, -1 }, ++/*17*/ { hashHexStr80, tripleDesThenMd5digest80, NULL, 80, 80, -1 }, ++/*18*/ { hashHexStr80, tripleDesThenSha1digest80, NULL, 80, 80, -1 }, ++/*19*/ { hashHexStr80, cbc3desThenMd5digest80, iv1, 80, 80, -1 }, ++/*20*/ { hashHexStr80, cbc3desThenSha1digest80, iv1, 80, 80, -1 }, ++/*21*/ { hashHexStr80, cbcAes128ThenMd5digest80, iv5, 80, 80, -1 }, ++/*22*/ { hashHexStr80, cbcAes128ThenSha1digest80, iv5, 80, 80, -1 }, ++/*23*/ { cesaAesCtrPlain, cesaAesCtrCipher, NULL, 36, 0, -1 }, ++/*24*/ { cesaAesIvPlainText, cesaAes128IvCipherCbc, NULL, 64, 0, -1 }, ++/*25*/ { plain3des1, cipher3des1, NULL, 0, 0, -1 }, ++/*26*/ { plain3des2, cipher3desCbc2, iv3des2,0, 0, -1 }, ++/*27*/ { plain3des3, cipher3desCbc3, iv3des3,0, 0, -1 }, ++}; ++ ++ ++/* Key = 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, ++ * 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa ++ * Input 0xdd repeated "size" times ++ */ ++static MV_CESA_SIZE_TEST mdMultiSizeTest302[] = ++{ ++ { 80, "7a031a640c14a4872814930b1ef3a5b2" }, ++ { 512, "5488e6c5a14dc72a79f28312ca5b939b" }, ++ { 1000, "d00814f586a8b78a05724239d2531821" }, ++ { 1001, "bf07df7b7f49d3f5b5ecacd4e9e63281" }, ++ { 1002, "1ed4a1a802e87817a819d4e37bb4d0f7" }, ++ { 1003, "5972ab64a4f265ee371dac2f2f137f90" }, ++ { 1004, "71f95e7ec3aa7df2548e90898abdb28e" }, ++ { 1005, "e082790b4857fcfc266e92e59e608814" }, ++ { 1006, "9500f02fd8ac7fde8b10e4fece9a920d" }, ++ { 1336, "e42edcce57d0b75b01aa09d71427948b" }, ++ { 1344, "bb5454ada0deb49ba0a97ffd60f57071" }, ++ { 1399, "0f44d793e744b24d53f44f295082ee8c" }, ++ { 1400, "359de8a03a9b707928c6c60e0e8d79f1" }, ++ { 1401, "e913858b484cbe2b384099ea88d8855b" }, ++ { 1402, "d9848a164af53620e0540c1d7d87629e" }, ++ { 1403, "0c9ee1c2c9ef45e9b625c26cbaf3e822" }, ++ { 1404, "12edd4f609416e3c936170360561b064" }, ++ { 1405, "7fc912718a05446395345009132bf562" }, ++ { 1406, "882f17425e579ff0d85a91a59f308aa0" }, ++ { 1407, "005cae408630a2fb5db82ad9db7e59da" }, ++ { 1408, "64655f8b404b3fea7a3e3e609bc5088f" }, ++ { 1409, "4a145284a7f74e01b6bb1a0ec6a0dd80" }, ++ { 2048, "67caf64475650732def374ebb8bde3fd" }, ++ { 2049, "6c84f11f472825f7e6cd125c2981884b" }, ++ { 2050, "8999586754a73a99efbe4dbad2816d41" }, ++ { 2051, "ba6946b610e098d286bc81091659dfff" }, ++ { 2052, "d0afa01c92d4d13def2b024f36faed83" }, ++ { 3072, "61d8beac61806afa2585d74a9a0e6974" }, ++ { 3074, "f6501a28dcc24d1e4770505c51a87ed3" }, ++ { 3075, "ea4a6929be67e33e61ff475369248b73" }, ++ { 4048, "aa8c4d68f282a07e7385acdfa69f4bed" }, ++ { 4052, "afb5ed2c0e1d430ea59e59ed5ed6b18a" }, ++ { 4058, "9e8553f9bdd43aebe0bd729f0e600c99" }, ++ { 6144, "f628f3e5d183fe5cdd3a5abee39cf872" }, ++ { 6150, "89a3efcea9a2f25f919168ad4a1fd292" }, ++ { 6400, "cdd176b7fb747873efa4da5e32bdf88f" }, ++ { 6528, "b1d707b027354aca152c45ee559ccd3f" }, ++ { 8192, "c600ea4429ac47f9941f09182166e51a" }, ++ {16384, "16e8754bfbeb4c649218422792267a37" }, ++ {18432, "0fd0607521b0aa8b52219cfbe215f63e" }, ++ { 0, NULL }, ++}; ++ ++/* Key = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, ++ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 ++ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") ++ */ ++static MV_CESA_SIZE_TEST mdMultiSizeTest304[] = ++{ ++ { 80, "a456c4723fee6068530af5a2afa71627" }, ++ { 512, "f85c2a2344f5de68b432208ad13e5794" }, ++ { 1000, "35464d6821fd4a293a41eb84e274c8c5" }, ++ { 1001, "c08eedbdce60cceb54bc2d732bb32c8b" }, ++ { 1002, "5664f71800c011cc311cb6943339c1b8" }, ++ { 1003, "779c723b044c585dc7802b13e8501bdc" }, ++ { 1004, "55e500766a2c307bc5c5fdd15e4cacd4" }, ++ { 1005, "d5f978954f5c38529d1679d2b714f068" }, ++ { 1006, "cd3efc827ce628b7281b72172693abf9" }, ++ { 1336, "6f04479910785878ae6335b8d1e87edf" }, ++ { 1344, "b6d27b50c2bce1ba2a8e1b5cc4324368" }, ++ { 1399, "65f70a1d4c86e5eaeb0704c8a7816795" }, ++ { 1400, "3394b5adc4cb3ff98843ca260a44a88a" }, ++ { 1401, "3a06f3582033a66a4e57e0603ce94e74" }, ++ { 1402, "e4d97f5ed51edc48abfa46eeb5c31752" }, ++ { 1403, "3d05e40b080ee3bedf293cb87b7140e7" }, ++ { 1404, "8cf294fc3cd153ab18dccb2a52cbf244" }, ++ { 1405, "d1487bd42f6edd9b4dab316631159221" }, ++ { 1406, "0527123b6bf6936cf5d369dc18c6c70f" }, ++ { 1407, "3224a06639db70212a0cd1ae1fcc570a" }, ++ { 1408, "a9e13335612c0356f5e2c27086e86c43" }, ++ { 1409, "a86d1f37d1ed8a3552e9a4f04dceea98" }, ++ { 2048, "396905c9b961cd0f6152abfb69c4449c" }, ++ { 2049, "49f39bff85d9dcf059fadb89efc4a70f" }, ++ { 2050, "3a2b4823bc4d0415656550226a63e34a" }, ++ { 2051, "dec60580d406c782540f398ad0bcc7e0" }, ++ { 2052, "32f76610a14310309eb748fe025081bf" }, ++ { 3072, "45edc1a42bf9d708a621076b63b774da" }, ++ { 3074, "9be1b333fe7c0c9f835fb369dc45f778" }, ++ { 3075, "8c06fcac7bd0e7b7a17fd6508c09a549" }, ++ { 4048, "0ddaef848184bf0ad98507a10f1e90e4" }, ++ { 4052, "81976bcaeb274223983996c137875cb8" }, ++ { 4058, "0b0a7a1c82bc7cbc64d8b7cd2dc2bb22" }, ++ { 6144, "1c24056f52725ede2dff0d7f9fc9855f" }, ++ { 6150, "b7f4b65681c4e43ee68ca466ca9ca4ec" }, ++ { 6400, "443bbaab9f7331ddd4bf11b659cd43c8" }, ++ { 6528, "216f44f23047cfee03a7a64f88f9a995" }, ++ { 8192, "ac7a993b2cad54879dba1bde63e39097" }, ++ { 8320, "55ed7be9682d6c0025b3221a62088d08" }, ++ {16384, "c6c722087653b62007aea668277175e5" }, ++ {18432, "f1faca8e907872c809e14ffbd85792d6" }, ++ { 0, NULL }, ++}; ++ ++/* HASH-MD5 ++ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") ++ * repeated "size" times ++ */ ++static MV_CESA_SIZE_TEST mdMultiSizeTest305[] = ++{ ++ { 80, "57edf4a22be3c955ac49da2e2107b67a" }, ++ { 512, "c729ae8f0736cc377a9767a660eaa04e" }, ++ { 1000, "f1257a8659eb92d36fe14c6bf3852a6a" }, ++ { 1001, "f8a46fe8ea04fdc8c7de0e84042d3878" }, ++ { 1002, "da188dd67bff87d58aa3c02af2d0cc0f" }, ++ { 1003, "961753017feee04c9b93a8e51658a829" }, ++ { 1004, "dd68c4338608dcc87807a711636bf2af" }, ++ { 1005, "e338d567d3ce66bf69ada29658a8759b" }, ++ { 1006, "443c9811e8b92599b0b149e8d7ec700a" }, ++ { 1336, "89a98511706008ba4cbd0b4a24fa5646" }, ++ { 1344, "335a919805f370b9e402a62c6fe01739" }, ++ { 1399, "5d18d0eddcd84212fe28d812b5e80e3b" }, ++ { 1400, "6b695c240d2dffd0dffc99459ca76db6" }, ++ { 1401, "49590f61298a76719bc93a57a30136f5" }, ++ { 1402, "94c2999fa3ef1910a683d69b2b8476f2" }, ++ { 1403, "37073a02ab00ecba2645c57c228860db" }, ++ { 1404, "1bcd06994fce28b624f0c5fdc2dcdd2b" }, ++ { 1405, "11b93671a64c95079e8cf9e7cddc8b3d" }, ++ { 1406, "4b6695772a4c66313fa4871017d05f36" }, ++ { 1407, "d1539b97fbfda1c075624e958de19c5b" }, ++ { 1408, "b801b9b69920907cd018e8063092ede9" }, ++ { 1409, "b765f1406cfe78e238273ed01bbcaf7e" }, ++ { 2048, "1d7e2c64ac29e2b3fb4c272844ed31f5" }, ++ { 2049, "71d38fac49c6b1f4478d8d88447bcdd0" }, ++ { 2050, "141c34a5592b1bebfa731e0b23d0cdba" }, ++ { 2051, "c5e1853f21c59f5d6039bd13d4b380d8" }, ++ { 2052, "dd44a0d128b63d4b5cccd967906472d7" }, ++ { 3072, "37d158e33b21390822739d13db7b87fe" }, ++ { 3074, "aef3b209d01d39d0597fe03634bbf441" }, ++ { 3075, "335ffb428eabf210bada96d74d5a4012" }, ++ { 4048, "2434c2b43d798d2819487a886261fc64" }, ++ { 4052, "ac2fa84a8a33065b2e92e36432e861f8" }, ++ { 4058, "856781f85616c341c3533d090c1e1e84" }, ++ { 6144, "e5d134c652c18bf19833e115f7a82e9b" }, ++ { 6150, "a09a353be7795fac2401dac5601872e6" }, ++ { 6400, "08b9033ac6a1821398f50af75a2dbc83" }, ++ { 6528, "3d47aa193a8540c091e7e02f779e6751" }, ++ { 8192, "d3164e710c0626f6f395b38f20141cb7" }, ++ { 8320, "b727589d9183ff4e8491dd24466974a3" }, ++ {16384, "3f54d970793d2274d5b20d10a69938ac" }, ++ {18432, "f558511dcf81985b7a1bb57fad970531" }, ++ { 0, NULL }, ++}; ++ ++ ++/* Key = 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, ++ * 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa ++ * 0xaa, 0xaa, 0xaa, 0xaa ++ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") ++ */ ++static MV_CESA_SIZE_TEST shaMultiSizeTest402[] = ++{ ++ { 80, "e812f370e659705a1649940d1f78cd7af18affd3" }, ++ { 512, "e547f886b2c15d995ed76a8a924cb408c8080f66" }, ++ { 1000, "239443194409f1a5342ecde1a092c8f3a3ed790a" }, ++ { 1001, "f278ab9a102850a9f48dc4e9e6822afe2d0c52b5" }, ++ { 1002, "8bcc667df5ab6ece988b3af361d09747c77f4e72" }, ++ { 1003, "0fae6046c7dc1d3e356b25af836f6077a363f338" }, ++ { 1004, "0ea48401cc92ae6bc92ae76685269cb0167fbe1a" }, ++ { 1005, "ecbcd7c879b295bafcd8766cbeac58cc371e31d1" }, ++ { 1006, "eb4a4a3d07d1e9a15e6f1ab8a9c47f243e27324c" }, ++ { 1336, "f5950ee1d77c10e9011d2149699c9366fe52529c" }, ++ { 1344, "b04263604a63c351b0b3b9cf1785b4bdba6c8838" }, ++ { 1399, "8cb1cff61d5b784045974a2fc69386e3b8d24218" }, ++ { 1400, "9bb2f3fcbeddb2b90f0be797cd647334a2816d51" }, ++ { 1401, "23ae462a7a0cb440f7445791079a5d75a535dd33" }, ++ { 1402, "832974b524a4d3f9cc2f45a3cabf5ccef65cd2aa" }, ++ { 1403, "d1c683742fe404c3c20d5704a5430e7832a7ec95" }, ++ { 1404, "867c79042e64f310628e219d8b85594cd0c7adc3" }, ++ { 1405, "c9d81d49d13d94358f56ccfd61af02b36c69f7c3" }, ++ { 1406, "0df43daab2786172f9b8d07d61f14a070cf1287a" }, ++ { 1407, "0fd8f3ad7f169534b274d4c66bbddd89f759e391" }, ++ { 1408, "3987511182b18473a564436003139b808fa46343" }, ++ { 1409, "ef667e063c9e9f539a8987a8d0bd3066ee85d901" }, ++ { 2048, "921109c99f3fedaca21727156d5f2b4460175327" }, ++ { 2049, "47188600dd165eb45f27c27196d3c46f4f042c1b" }, ++ { 2050, "8831939904009338de10e7fa670847041387807d" }, ++ { 2051, "2f8ebb5db2997d614e767be1050366f3641e7520" }, ++ { 2052, "669e51cd730dae158d3bef8adba075bd95a0d011" }, ++ { 3072, "cfee66cfd83abc8451af3c96c6b35a41cc6c55f5" }, ++ { 3074, "216ea26f02976a261b7d21a4dd3085157bedfabd" }, ++ { 3075, "bd612ebba021fd8e012b14c3bd60c8c5161fabc0" }, ++ { 4048, "c2564c1fdf2d5e9d7dde7aace2643428e90662e8" }, ++ { 4052, "91ce61fe924b445dfe7b5a1dcd10a27caec16df6" }, ++ { 4058, "db2a9be5ee8124f091c7ebd699266c5de223c164" }, ++ { 6144, "855109903feae2ba3a7a05a326b8a171116eb368" }, ++ { 6150, "37520bb3a668294d9c7b073e7e3daf8fee248a78" }, ++ { 6400, "60a353c841b6d2b1a05890349dad2fa33c7536b7" }, ++ { 6528, "9e53a43a69bb42d7c8522ca8bd632e421d5edb36" }, ++ { 8192, "a918cb0da862eaea0a33ee0efea50243e6b4927c" }, ++ { 8320, "29a5dcf55d1db29cd113fcf0572ae414f1c71329" }, ++ {16384, "6fb27966138e0c8d5a0d65ace817ebd53633cee1" }, ++ {18432, "ca09900d891c7c9ae2a559b10f63a217003341c1" }, ++ { 0, NULL }, ++}; ++ ++/* Key = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, ++ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 ++ * 0x11, 0x12, 0x13, 0x14 ++ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") ++ */ ++static MV_CESA_SIZE_TEST shaMultiSizeTest404[] = ++{ ++ { 80, "beaf20a34b06a87558d156c0949bc3957d40222e" }, ++ { 512, "3353955358d886bc2940a3c7f337ff7dafb59c7b" }, ++ { 1000, "8737a542c5e9b2b6244b757ebb69d5bd602a829f" }, ++ { 1001, "fd9e7582d8a5d3c9fe3b923e4e6a41b07a1eb4d4" }, ++ { 1002, "a146d14a6fc3c274ff600568f4d75b977989e00d" }, ++ { 1003, "be22601bbc027ddef2dec97d30b3dc424fd803c5" }, ++ { 1004, "3e71fe99b2fe2b7bfdf4dbf0c7f3da25d7ea35e7" }, ++ { 1005, "2c422735d7295408fddd76f5e8a83a2a8da13df3" }, ++ { 1006, "6d875319049314b61855101a647b9ba3313428e6" }, ++ { 1336, "c1631ea80bad9dc43a180712461b65a0598c711c" }, ++ { 1344, "816069bf91d34581005746e2e0283d0f9c7b7605" }, ++ { 1399, "4e139866dc61cfcb8b67ca2ebd637b3a538593af" }, ++ { 1400, "ff2a0f8dd2b02c5417910f6f55d33a78e081a723" }, ++ { 1401, "ab00c12be62336964cbce31ae97fe2a0002984d5" }, ++ { 1402, "61349e7f999f3a1acc56c3e9a5060a9c4a7b05b6" }, ++ { 1403, "3edbc0f61e435bc1317fa27d840076093fb79353" }, ++ { 1404, "d052c6dfdbe63d45dab23ef9893e2aa4636aca1e" }, ++ { 1405, "0cc16b7388d67bf0add15a31e6e6c753cfae4987" }, ++ { 1406, "c96ba7eaad74253c38c22101b558d2850b1d1b90" }, ++ { 1407, "3445428a40d2c6556e7c55797ad8d323b61a48d9" }, ++ { 1408, "8d6444f937a09317c89834187b8ea9b8d3a8c56b" }, ++ { 1409, "c700acd3ecd19014ea2bdb4d42510c467e088475" }, ++ { 2048, "ee27d2a0cb77470c2f496212dfd68b5bb7b04e4b" }, ++ { 2049, "683762d7a02983b26a6d046e6451d9cd82c25932" }, ++ { 2050, "0fd20f1d55a9ee18363c2a6fd54aa13aee69992f" }, ++ { 2051, "86c267d8cc4bc8d59090e4f8b303da960fd228b7" }, ++ { 2052, "452395ae05b3ec503eea34f86fc0832485ad97c1" }, ++ { 3072, "75198e3cfd0b9bcff2dabdf8e38e6fdaa33ca49a" }, ++ { 3074, "4e24785ef080141ce4aab4675986d9acea624d7c" }, ++ { 3075, "3a20c5978dd637ec0e809bf84f0d9ccf30bc65bf" }, ++ { 4048, "3c32da256be7a7554922bf5fed51b0d2d09e59ad" }, ++ { 4052, "fff898426ea16e54325ae391a32c6c9bce4c23c0" }, ++ { 4058, "c800b9e562e1c91e1310116341a3c91d37f848ec" }, ++ { 6144, "d91d509d0cc4376c2d05bf9a5097717a373530e6" }, ++ { 6150, "d957030e0f13c5df07d9eec298542d8f94a07f12" }, ++ { 6400, "bb745313c3d7dc17b3f955e5534ad500a1082613" }, ++ { 6528, "77905f80d9ca82080bbb3e5654896dabfcfd1bdb" }, ++ { 8192, "5237fd9a81830c974396f99f32047586612ff3c0" }, ++ { 8320, "57668e28d5f2dba0839518a11db0f6af3d7e08bf" }, ++ {16384, "62e093fde467f0748087beea32e9af97d5c61241" }, ++ {18432, "845fb33130c7d6ea554fd5aacb9c50cf7ccb5929" }, ++ { 0, NULL }, ++}; ++ ++/* HASH-SHA1 ++ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") ++ * repeated "size" times ++ */ ++static MV_CESA_SIZE_TEST shaMultiSizeTest405[] = ++{ ++ { 80, "50abf5706a150990a08b2c5ea40fa0e585554732" }, ++ { 512, "f14516a08948fa27917a974d219741a697ba0087" }, ++ { 1000, "0bd18c378d5788817eb4f1e5dc07d867efa5cbf4" }, ++ { 1001, "ca29b85c35db1b8aef83c977893a11159d1b7aa2" }, ++ { 1002, "d83bc973eaaedb8a31437994dabbb3304b0be086" }, ++ { 1003, "2cf7bbef0acd6c00536b5c58ca470df9a3a90b6c" }, ++ { 1004, "e4375d09b1223385a8a393066f8209acfd936a80" }, ++ { 1005, "1029b38043e027745d019ce1d2d68e3d8b9d8f99" }, ++ { 1006, "deea16dcebbd8ac137e2b984deb639b9fb5e9680" }, ++ { 1336, "ea031b065fff63dcfb6a41956e4777520cdbc55d" }, ++ { 1344, "b52096c6445e6c0a8355995c70dc36ae186c863c" }, ++ { 1399, "cde2f6f8379870db4b32cf17471dc828a8dbff2b" }, ++ { 1400, "e53ff664064bc09fe5054c650806bd42d8179518" }, ++ { 1401, "d1156db5ddafcace64cdb510ff0d4af9b9a8ad64" }, ++ { 1402, "34ede0e9a909dd84a2ae291539105c0507b958e1" }, ++ { 1403, "a772ca3536da77e6ad3251e4f9e1234a4d7b87c0" }, ++ { 1404, "29740fd2b04e7a8bfd32242db6233156ad699948" }, ++ { 1405, "65b17397495b70ce4865dad93bf991b74c97cce1" }, ++ { 1406, "a7ee89cd0754061fdb91af7ea6abad2c69d542e3" }, ++ { 1407, "3eebf82f7420188e23d328b7ce93580b279a5715" }, ++ { 1408, "e08d3363a8b9a490dfb3a4c453452b8f114deeec" }, ++ { 1409, "95d74df739181a4ff30b8c39e28793a36598e924" }, ++ { 2048, "aa40262509c2abf84aab0197f83187fc90056d91" }, ++ { 2049, "7dec28ef105bc313bade8d9a7cdeac58b99de5ea" }, ++ { 2050, "d2e30f77ec81197de20f56588a156094ecb88450" }, ++ { 2051, "6b22ccc874833e96551a39da0c0edcaa0d969d92" }, ++ { 2052, "f843141e57875cd669af58744bc60aa9ea59549c" }, ++ { 3072, "09c5fedeaa62c132e673cc3c608a00142273d086" }, ++ { 3074, "b09e95eea9c7b1b007a58accec488301901a7f3d" }, ++ { 3075, "e6226b77b4ada287a8c9bbcf4ed71eec5ce632dc" }, ++ { 4048, "e99394894f855821951ddddf5bfc628547435f5c" }, ++ { 4052, "32d2f1af38be9cfba6cd03d55a254d0b3e1eb382" }, ++ { 4058, "d906552a4f2aca3a22e1fecccbcd183d7289d0ef" }, ++ { 6144, "2e7f62d35a860988e1224dc0543204af19316041" }, ++ { 6150, "d6b89698ee133df46fec9d552fadc328aa5a1b51" }, ++ { 6400, "dff50e90c46853988fa3a4b4ce5dda6945aae976" }, ++ { 6528, "9e63ec0430b96db02d38bc78357a2f63de2ab7f8" }, ++ { 8192, "971eb71ed60394d5ab5abb12e88420bdd41b5992" }, ++ { 8320, "91606a31b46afeaac965cecf87297e791b211013" }, ++ {16384, "547f830a5ec1f5f170ce818f156b1002cabc7569" }, ++ {18432, "f16f272787f3b8d539652e4dc315af6ab4fda0ef" }, ++ { 0, NULL }, ++}; ++ ++/* CryptoKey = 0x01234567, 0x89abcdef, ++ * 0x01234567, 0x89abcdef, ++ * 0x01234567, 0x89abcdef; ++ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, ++ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 ++ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") ++ * Note: only sizes aligned to 3DES block size (8 bytes) allowed ++ */ ++static MV_CESA_SIZE_TEST tripleDesMdMultiSizeTest502[] = ++{ ++ { 64, "9586962a2aaaef28803dec2e17807a7f" }, ++ { 80, "b7726a03aad490bd6c5a452a89a1b271" }, ++ { 352, "f1ed9563aecc3c0d2766eb2bed3b4e4c" }, ++ { 512, "0f9decb11ab40fe86f4d4d9397bc020e" }, ++ { 1000, "3ba69deac12cab8ff9dff7dbd9669927" }, ++ { 1336, "6cf47bf1e80e03e2c1d0945bc50d37d2" }, ++ { 1344, "4be388dab21ceb3fa1b8d302e9b821f7" }, ++ { 1400, "a58b79fb21dd9bfc6ec93e3b99fb0ef1" }, ++ { 1408, "8bc97379fc2ac3237effcdd4f7a86528" }, ++ { 2048, "1339f03ab3076f25a20bc4cba16eb5bf" }, ++ { 3072, "731204d2d90c4b36ae41f5e1fb874288" }, ++ { 4048, "c028d998cfda5642547b7e1ed5ea16e4" }, ++ { 6144, "b1b19cd910cc51bd22992f1e59f1e068" }, ++ { 6400, "44e4613496ba622deb0e7cb768135a2f" }, ++ { 6528, "3b06b0a86f8db9cd67f9448dfcf10549" }, ++ { 8192, "d581780b7163138a0f412be681457d82" }, ++ {16384, "03b8ac05527faaf1bed03df149c65ccf" }, ++ {18432, "677c8a86a41dab6c5d81b85b8fb10ff6" }, ++ { 0, NULL }, ++}; ++ ++ ++/* CryptoKey = 0x01234567, 0x89abcdef, ++ * 0x01234567, 0x89abcdef, ++ * 0x01234567, 0x89abcdef; ++ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, ++ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 ++ * 0x11, 0x12, 0x13, 0x14 ++ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") ++ * Note: only sizes aligned to 3DES block size (8 bytes) allowed ++ */ ++static MV_CESA_SIZE_TEST tripleDesShaMultiSizeTest503[] = ++{ ++ { 64, "44a1e9bcbfc1429630d9ea68b7a48b0427a684f2" }, ++ { 80, "b2ddeaca91030eab5b95a234ef2c0f6e738ff883" }, ++ { 352, "4b91864c7ff629bdff75d9726421f76705452aaf" }, ++ { 512, "6dd37faceeb2aa98ba74f4242ed6734a4d546af5" }, ++ { 1000, "463661c30300be512a9df40904f0757cde5f1141" }, ++ { 1336, "b931f831d9034fe59c65176400b039fe9c1f44a5" }, ++ { 1344, "af8866b1cd4a4887d6185bfe72470ffdfb3648e1" }, ++ { 1400, "49c6caf07296d5e31d2504d088bc5b20c3ee7cdb" }, ++ { 1408, "fcae8deedbc6ebf0763575dc7e9de075b448a0f4" }, ++ { 2048, "edece5012146c1faa0dd10f50b183ba5d2af58ac" }, ++ { 3072, "5b83625adb43a488b8d64fecf39bb766818547b7" }, ++ { 4048, "d2c533678d26c970293af60f14c8279dc708bfc9" }, ++ { 6144, "b8f67af4f991b08b725f969b049ebf813bfacc5c" }, ++ { 6400, "d9a6c7f746ac7a60ef2edbed2841cf851c25cfb0" }, ++ { 6528, "376792b8c8d18161d15579fb7829e6e3a27e9946" }, ++ { 8192, "d890eabdca195b34ef8724b28360cffa92ae5655" }, ++ {16384, "a167ee52639ec7bf19aee9c6e8f76667c14134b9" }, ++ {18432, "e4396ab56f67296b220985a12078f4a0e365d2cc" }, ++ { 0, NULL }, ++}; ++ ++/* CryptoKey = 0x01234567, 0x89abcdef, ++ * 0x01234567, 0x89abcdef, ++ * 0x01234567, 0x89abcdef ++ * IV = 0x12345678, 0x90abcdef ++ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, ++ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 ++ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") ++ * Note: only sizes aligned to 3DES block size (8 bytes) allowed ++ */ ++static MV_CESA_SIZE_TEST cbc3desMdMultiSizeTest504[] = ++{ ++ { 64, "8d10e00802460ede0058c139ba48bd2d" }, ++ { 80, "6f463057e1a90e0e91ae505b527bcec0" }, ++ { 352, "4938d48bdf86aece2c6851e7c6079788" }, ++ { 512, "516705d59f3cf810ebf2a13a23a7d42e" }, ++ { 1000, "a5a000ee5c830e67ddc6a2d2e5644b31" }, ++ { 1336, "44af60087b74ed07950088efbe3b126a" }, ++ { 1344, "1f5b39e0577920af731dabbfcf6dfc2a" }, ++ { 1400, "6804ea640e29b9cd39e08bc37dbce734" }, ++ { 1408, "4fb436624b02516fc9d1535466574bf9" }, ++ { 2048, "c909b0985c423d8d86719f701e9e83db" }, ++ { 3072, "cfe0bc34ef97213ee3d3f8b10122db21" }, ++ { 4048, "03ea10b5ae4ddeb20aed6af373082ed1" }, ++ { 6144, "b9a0ff4f87fc14b3c2dc6f0ed0998fdf" }, ++ { 6400, "6995f85d9d4985dd99e974ec7dda9dd6" }, ++ { 6528, "bbbb548ce2fa3d58467f6a6a5168a0e6" }, ++ { 8192, "afe101fbe745bb449ae4f50d10801456" }, ++ {16384, "9741706d0b1c923340c4660ff97cacdf" }, ++ {18432, "b0217becb73cb8f61fd79c7ce9d023fb" }, ++ { 0, NULL }, ++}; ++ ++ ++/* CryptoKey = 0x01234567, 0x89abcdef, ++ * 0x01234567, 0x89abcdef, ++ * 0x01234567, 0x89abcdef; ++ * IV = 0x12345678, 0x90abcdef ++ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, ++ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 ++ * 0x11, 0x12, 0x13, 0x14 ++ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") ++ * Note: only sizes aligned to 3DES block size (8 bytes) allowed ++ */ ++static MV_CESA_SIZE_TEST cbc3desShaMultiSizeTest505[] = ++{ ++ { 64, "409187e5bdb0be4a7754ca3747f7433dc4f01b98" }, ++ { 80, "1b002ed050be743aa98860cf35659646bb8efcc0" }, ++ { 352, "6cbf7ebe50fa4fa6eecc19eca23f9eae553ccfff" }, ++ { 512, "cfb5253fb4bf72b743320c30c7e48c54965853b0" }, ++ { 1000, "95e04e1ca2937e7c5a9aba9e42d2bcdb8a7af21f" }, ++ { 1336, "3b5c1f5eee5837ebf67b83ae01405542d77a6627" }, ++ { 1344, "2b3d42ab25615437f98a1ee310b81d07a02badc2" }, ++ { 1400, "7f8687df7c1af44e4baf3c934b6cca5ab6bc993e" }, ++ { 1408, "473a581c5f04f7527d50793c845471ac87e86430" }, ++ { 2048, "e41d20cae7ebe34e6e828ed62b1e5734019037bb" }, ++ { 3072, "275664afd7a561d804e6b0d204e53939cde653ae" }, ++ { 4048, "0d220cc5b34aeeb46bbbd637dde6290b5a8285a3" }, ++ { 6144, "cb393ddcc8b1c206060625b7d822ef9839e67bc5" }, ++ { 6400, "dd3317e2a627fc04800f74a4b05bfda00fab0347" }, ++ { 6528, "8a74c3b2441ab3f5a7e08895cc432566219a7c41" }, ++ { 8192, "b8e6ef3a549ed0e005bd5b8b1a5fe6689e9711a7" }, ++ {16384, "55f59404008276cdac0e2ba0d193af2d40eac5ce" }, ++ {18432, "86ae6c4fc72369a54cce39938e2d0296cd9c6ec5" }, ++ { 0, NULL }, ++}; ++ ++ ++/* CryptoKey = 0x01234567, 0x89abcdef, ++ * 0x01234567, 0x89abcdef, ++ * 0x01234567, 0x89abcdef ++ * IV = 0x12345678, 0x90abcdef ++ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, ++ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 ++ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") ++ * Note: only sizes aligned to AES block size (16 bytes) allowed ++ */ ++static MV_CESA_SIZE_TEST cbcAes128md5multiSizeTest506[] = ++{ ++ { 16, "7ca4c2ba866751598720c5c4aa0d6786" }, ++ { 64, "7dba7fb988e80da609b1fea7254bced8" }, ++ { 80, "6b6e863ac5a71d15e3e9b1c86c9ba05f" }, ++ { 352, "a1ceb9c2e3021002400d525187a9f38c" }, ++ { 512, "596c055c1c55db748379223164075641" }, ++ { 1008, "f920989c02f3b3603f53c99d89492377" }, ++ { 1344, "2e496b73759d77ed32ea222dbd2e7b41" }, ++ { 1408, "7178c046b3a8d772efdb6a71c4991ea4" }, ++ { 2048, "a917f0099c69eb94079a8421714b6aad" }, ++ { 3072, "693cd5033d7f5391d3c958519fa9e934" }, ++ { 4048, "139dca91bcff65b3c40771749052906b" }, ++ { 6144, "428d9cef6df4fb70a6e9b6bbe4819e55" }, ++ { 6400, "9c0b909e76daa811e12b1fc17000a0c4" }, ++ { 6528, "ad876f6297186a7be1f1b907ed860eda" }, ++ { 8192, "479cbbaca37dd3191ea1f3e8134a0ef4" }, ++ {16384, "60fda559c74f91df538100c9842f2f15" }, ++ {18432, "4a3eb1cba1fa45f3981270953f720c42" }, ++ { 0, NULL }, ++}; ++ ++ ++/* CryptoKey = 0x01234567, 0x89abcdef, ++ * 0x01234567, 0x89abcdef, ++ * 0x01234567, 0x89abcdef; ++ * IV = 0x12345678, 0x90abcdef ++ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, ++ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 ++ * 0x11, 0x12, 0x13, 0x14 ++ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") ++ * Note: only sizes aligned to AES block size (16 bytes) allowed ++ */ ++static MV_CESA_SIZE_TEST cbcAes128sha1multiSizeTest507[] = ++{ ++ { 16, "9aa8dc1c45f0946daf78057fa978759c625c1fee" }, ++ { 64, "9f588fc1ede851e5f8b20256abc9979465ae2189" }, ++ { 80, "13558472d1fc1c90dffec6e5136c7203452d509b" }, ++ { 352, "6b93518e006cfaa1f7adb24615e7291fb0a27e06" }, ++ { 512, "096874951a77fbbf333e49d80c096ee2016e09bd" }, ++ { 1008, "696fc203c2e4b5ae0ec5d1db3f623c490bc6dbac" }, ++ { 1344, "79bf77509935ccd3528caaac6a5eb6481f74029b" }, ++ { 1408, "627f9462b95fc188e8cfa7eec15119bdc5d4fcf1" }, ++ { 2048, "3d50d0c005feba92fe41502d609fced9c882b4d1" }, ++ { 3072, "758807e5b983e3a91c06fb218fe0f73f77111e94" }, ++ { 4048, "ca90e85242e33f005da3504416a52098d0d31fb2" }, ++ { 6144, "8044c1d4fd06642dfc46990b4f18b61ef1e972cf" }, ++ { 6400, "166f1f4ea57409f04feba9fb1e39af0e00bd6f43" }, ++ { 6528, "0389016a39485d6e330f8b4215ddf718b404f7e9" }, ++ { 8192, "6df7ee2a8b61d6f7f860ce8dbf778f0c2a5b508b" }, ++ {16384, "a70a6d8dfa1f91ded621c3dbaed34162bc48783f" }, ++ {18432, "8dfad627922ce15df1eed10bdbed49244efa57db" }, ++ { 0, NULL }, ++}; ++ ++ ++void cesaTestPrintStatus(void); ++ ++ ++/*------------------------- LOCAL FUNCTIONs ---------------------------------*/ ++MV_STATUS testCmd(int sid, int iter, MV_CESA_COMMAND* pCmd, ++ MV_CESA_TEST_SESSION* pTestSession, MV_U8* pIV, int ivSize); ++MV_STATUS testClose(int idx); ++MV_STATUS testOpen(int idx); ++void close_session(int sid); ++void cesaTestCheckReady(const MV_CESA_RESULT *r); ++void cesaCheckReady(MV_CESA_RESULT* r); ++void printTestResults(int idx, MV_STATUS status, int checkMode); ++void cesaLastResult(void); ++void cesaTestPrintReq(int req, int offset, int size); ++ ++void cesaTestPrintStatus(void); ++void cesaTestPrintSession(int idx); ++void sizeTest(int testIdx, int iter, int checkMode); ++void multiTest(int iter, int reqSize, int checkMode); ++void oneTest(int testIdx, int caseIdx,int iter, int reqSize, int checkMode); ++void multiSizeTest(int idx, int iter, int checkMode, char* inputData); ++void cesaTest(int iter, int reqSize, int checkMode); ++void cesaOneTest(int testIdx, int caseIdx,int iter, int reqSize, int checkMode); ++void combiTest(int iter, int reqSize, int checkMode); ++void shaTest(int iter, int reqSize, int checkMode); ++void mdTest(int iter, int reqSize, int checkMode); ++void aesTest(int iter, int reqSize, int checkMode); ++void tripleDesTest(int iter, int reqSize, int checkMode); ++void desTest(int iter, int reqSize, int checkMode); ++void cesaTestStop(void); ++MV_STATUS testRun(int idx, int caseIdx, int iter,int reqSize, int checkMode); ++void cesaTestStart(int bufNum, int bufSize); ++ ++ ++static MV_U32 getRate(MV_U32* remainder) ++{ ++ MV_U32 kBits, milliSec, rate; ++ ++ milliSec = 0; ++ if( (cesaEndTicks - cesaBeginTicks) > 0) ++ { ++ milliSec = CESA_TEST_TICK_TO_MS(cesaEndTicks - cesaBeginTicks); ++ } ++ if(milliSec == 0) ++ { ++ if(remainder != NULL) ++ *remainder = 0; ++ return 0; ++ } ++ ++ kBits = (cesaIteration*cesaRateSize*8)/1000; ++ rate = kBits/milliSec; ++ if(remainder != NULL) ++ *remainder = ((kBits % milliSec)*10)/milliSec; ++ ++ return rate; ++} ++ ++static char* extractMbuf(MV_CESA_MBUF *pMbuf, ++ int offset, int size, char* hexStr) ++{ ++ mvCesaCopyFromMbuf((MV_U8*)cesaBinBuffer, pMbuf, offset, size); ++ mvBinToHex((const MV_U8*)cesaBinBuffer, hexStr, size); ++ ++ return hexStr; ++} ++ ++static MV_BOOL cesaCheckMbuf(MV_CESA_MBUF *pMbuf, ++ const char* hexString, int offset, ++ int checkSize) ++{ ++ MV_BOOL isFailed = MV_FALSE; ++ MV_STATUS status; ++ int size = strlen(hexString)/2; ++ int checkedSize = 0; ++/* ++ mvOsPrintf("cesaCheckMbuf: pMbuf=%p, offset=%d, checkSize=%d, mBufSize=%d\n", ++ pMbuf, offset, checkSize, pMbuf->mbufSize); ++*/ ++ if(pMbuf->mbufSize < (checkSize + offset)) ++ { ++ mvOsPrintf("checkSize (%d) is too large: offset=%d, mbufSize=%d\n", ++ checkSize, offset, pMbuf->mbufSize); ++ return MV_TRUE; ++ } ++ status = mvCesaCopyFromMbuf((MV_U8*)cesaBinBuffer, pMbuf, offset, checkSize); ++ if(status != MV_OK) ++ { ++ mvOsPrintf("CesaTest: Can't copy %d bytes from Mbuf=%p to checkBuf=%p\n", ++ checkSize, pMbuf, cesaBinBuffer); ++ return MV_TRUE; ++ } ++/* ++ mvDebugMemDump(cesaBinBuffer, size, 1); ++*/ ++ mvHexToBin(hexString, (MV_U8*)cesaExpBinBuffer, size); ++ ++ /* Compare buffers */ ++ while(checkSize > checkedSize) ++ { ++ size = MV_MIN(size, (checkSize - checkedSize)); ++ if(memcmp(cesaExpBinBuffer, &cesaBinBuffer[checkedSize], size) != 0) ++ { ++ mvOsPrintf("CheckMbuf failed: checkSize=%d, size=%d, checkedSize=%d\n", ++ checkSize, size, checkedSize); ++ mvDebugMemDump(&cesaBinBuffer[checkedSize], size, 1); ++ mvDebugMemDump(cesaExpBinBuffer, size, 1); ++ ++ isFailed = MV_TRUE; ++ break; ++ } ++ checkedSize += size; ++ } ++ ++ return isFailed; ++} ++ ++static MV_STATUS cesaSetMbuf(MV_CESA_MBUF *pMbuf, ++ const char* hexString, ++ int offset, int reqSize) ++{ ++ MV_STATUS status = MV_OK; ++ int copySize, size = strlen(hexString)/2; ++ ++ mvHexToBin(hexString, (MV_U8*)cesaBinBuffer, size); ++ ++ copySize = 0; ++ while(reqSize > copySize) ++ { ++ size = MV_MIN(size, (reqSize - copySize)); ++ ++ status = mvCesaCopyToMbuf((MV_U8*)cesaBinBuffer, pMbuf, offset+copySize, size); ++ if(status != MV_OK) ++ { ++ mvOsPrintf("cesaSetMbuf Error: Copy %d of %d bytes to MBuf\n", ++ copySize, reqSize); ++ break; ++ } ++ copySize += size; ++ } ++ pMbuf->mbufSize = offset+copySize; ++ return status; ++} ++ ++static MV_CESA_TEST_SESSION* getTestSessionDb(int idx, int* pTestIdx) ++{ ++ int testIdx, dbIdx = idx/100; ++ ++ if(dbIdx > MAX_TEST_TYPE) ++ { ++ mvOsPrintf("Wrong index %d - No such test type\n", idx); ++ return NULL; ++ } ++ testIdx = idx % 100; ++ ++ if(testIdx >= cesaTestsDB[dbIdx].numSessions) ++ { ++ mvOsPrintf("Wrong index %d - No such test\n", idx); ++ return NULL; ++ } ++ if(pTestIdx != NULL) ++ *pTestIdx = testIdx; ++ ++ return cesaTestsDB[dbIdx].pSessions; ++} ++ ++/* Debug */ ++void cesaTestPrintReq(int req, int offset, int size) ++{ ++ MV_CESA_MBUF* pMbuf; ++ ++ mvOsPrintf("cesaTestPrintReq: req=%d, offset=%d, size=%d\n", ++ req, offset, size); ++ mvDebugMemDump(cesaCmdRing, 128, 4); ++ ++ pMbuf = cesaCmdRing[req].pSrc; ++ mvCesaDebugMbuf("src", pMbuf, offset,size); ++ pMbuf = cesaCmdRing[req].pDst; ++ mvCesaDebugMbuf("dst", pMbuf, offset, size); ++ ++ cesaTestPrintStatus(); ++} ++ ++void cesaLastResult(void) ++{ ++ mvOsPrintf("Last Result: ReqId = %d, SessionId = %d, rc = (%d)\n", ++ (MV_U32)cesaResult.pReqPrv, cesaResult.sessionId, ++ cesaResult.retCode); ++} ++ ++void printTestResults(int idx, MV_STATUS status, int checkMode) ++{ ++ int testIdx; ++ MV_CESA_TEST_SESSION* pTestSessions = getTestSessionDb(idx, &testIdx); ++ ++ if(pTestSessions == NULL) ++ return; ++ ++ mvOsPrintf("%-35s %4dx%-4d : ", pTestSessions[testIdx].name, ++ cesaIteration, cesaReqSize); ++ if( (status == MV_OK) && ++ (cesaCryptoError == 0) && ++ (cesaError == 0) && ++ (cesaReqIdError == 0) ) ++ { ++ mvOsPrintf("Passed, Rate=%3u.%u Mbps (%5u cpp)\n", ++ cesaRate, cesaRateAfterDot, cesaEndTicks - cesaBeginTicks); ++ } ++ else ++ { ++ mvOsPrintf("Failed, Status = 0x%x\n", status); ++ if(cesaCryptoError > 0) ++ mvOsPrintf("cryptoError : %d\n", cesaCryptoError); ++ if(cesaReqIdError > 0) ++ mvOsPrintf("reqIdError : %d\n", cesaReqIdError); ++ if(cesaError > 0) ++ mvOsPrintf("cesaError : %d\n", cesaError); ++ } ++ if(cesaTestIsrMissCount > 0) ++ mvOsPrintf("cesaIsrMissed : %d\n", cesaTestIsrMissCount); ++} ++ ++void cesaCheckReady(MV_CESA_RESULT* r) ++{ ++ int reqId; ++ MV_CESA_MBUF *pMbuf; ++ MV_BOOL isFailed; ++ ++ cesaResult = *r; ++ reqId = (int)cesaResult.pReqPrv; ++ pMbuf = cesaCmdRing[reqId].pDst; ++ ++/* ++ mvOsPrintf("cesaCheckReady: reqId=%d, checkOffset=%d, checkSize=%d\n", ++ reqId, cesaCheckOffset, cesaCheckSize); ++*/ ++ /* Check expected reqId */ ++ if(reqId != cesaExpReqId) ++ { ++ cesaReqIdError++; ++/* ++ mvOsPrintf("CESA reqId Error: cbIter=%d (%d), reqId=%d, expReqId=%d\n", ++ cesaCbIter, cesaIteration, reqId, cesaExpReqId); ++*/ ++ } ++ else ++ { ++ if( (cesaCheckMode == CESA_FULL_CHECK_MODE) || ++ (cesaCheckMode == CESA_FAST_CHECK_MODE) ) ++ { ++ if(cesaResult.retCode != MV_OK) ++ { ++ cesaError++; ++ ++ mvOsPrintf("CESA Error: cbIter=%d (%d), reqId=%d, rc=%d\n", ++ cesaCbIter, cesaIteration, reqId, cesaResult.retCode); ++ } ++ else ++ { ++ if( (cesaCheckSize > 0) && (cesaOutputHexStr != NULL) ) ++ { ++ /* Check expected output */ ++ ++ isFailed = cesaCheckMbuf(pMbuf, cesaOutputHexStr, cesaCheckOffset, cesaCheckSize); ++ if(isFailed) ++ { ++ mvOsPrintf("CESA Crypto Error: cbIter=%d (%d), reqId=%d\n", ++ cesaCbIter, cesaIteration, reqId); ++ ++ CESA_TEST_DEBUG_PRINT(("Error: reqId=%d, reqSize=%d, checkOffset=%d, checkSize=%d\n", ++ reqId, cesaReqSize, cesaCheckOffset, cesaCheckSize)); ++ ++ CESA_TEST_DEBUG_PRINT(("Output str: %s\n", cesaOutputHexStr)); ++ ++ CESA_TEST_DEBUG_CODE( mvCesaDebugMbuf("error", pMbuf, 0, cesaCheckOffset+cesaCheckSize) ); ++ ++ cesaCryptoError++; ++ } ++ } ++ } ++ } ++ } ++ if(cesaCheckMode == CESA_SHOW_CHECK_MODE) ++ { ++ extractMbuf(pMbuf, cesaCheckOffset, cesaCheckSize, cesaHexBuffer); ++ mvOsPrintf("%4d, %s\n", cesaCheckOffset, cesaHexBuffer); ++ } ++ ++ cesaCbIter++; ++ if(cesaCbIter >= cesaIteration) ++ { ++ cesaCbIter = 0; ++ cesaExpReqId = 0; ++ cesaIsReady = MV_TRUE; ++ ++ cesaEndTicks = CESA_TEST_TICK_GET(); ++ cesaRate = getRate(&cesaRateAfterDot); ++ } ++ else ++ { ++ cesaExpReqId = reqId + 1; ++ if(cesaExpReqId == CESA_DEF_REQ_SIZE) ++ cesaExpReqId = 0; ++ } ++} ++ ++ ++#ifdef MV_NETBSD ++static int cesaTestReadyIsr(void *arg) ++#else ++#ifdef __KERNEL__ ++static irqreturn_t cesaTestReadyIsr( int irq , void *dev_id) ++#endif ++#ifdef MV_VXWORKS ++void cesaTestReadyIsr(void) ++#endif ++#endif ++{ ++ MV_U32 cause; ++ MV_STATUS status; ++ MV_CESA_RESULT result; ++ ++ cesaTestIsrCount++; ++ /* Clear cause register */ ++ cause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); ++ if( (cause & MV_CESA_CAUSE_ACC_DMA_ALL_MASK) == 0) ++ { ++ mvOsPrintf("cesaTestReadyIsr: cause=0x%x\n", cause); ++#ifdef MV_NETBSD ++ return 0; ++#else ++#ifdef __KERNEL__ ++ return 1; ++#else ++ return; ++#endif ++#endif ++ } ++ ++ MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); ++ ++ while(MV_TRUE) ++ { ++ /* Get Ready requests */ ++ status = mvCesaReadyGet(&result); ++ if(status == MV_OK) ++ cesaCheckReady(&result); ++ ++ break; ++ } ++ if( (cesaTestFull == 1) && (status != MV_BUSY) ) ++ { ++ cesaTestFull = 0; ++ CESA_TEST_WAKE_UP(); ++ } ++ ++#ifdef __KERNEL__ ++ return 1; ++#endif ++} ++ ++void ++cesaTestCheckReady(const MV_CESA_RESULT *r) ++{ ++ MV_CESA_RESULT result = *r; ++ ++ cesaCheckReady(&result); ++ ++ if (cesaTestFull == 1) { ++ cesaTestFull = 0; ++ CESA_TEST_WAKE_UP(); ++ } ++} ++ ++static INLINE int open_session(MV_CESA_OPEN_SESSION* pOs) ++{ ++ MV_U16 sid; ++ MV_STATUS status; ++ ++ status = mvCesaSessionOpen(pOs, (short*)&sid); ++ if(status != MV_OK) ++ { ++ mvOsPrintf("CesaTest: Can't open new session - status = 0x%x\n", ++ status); ++ return -1; ++ } ++ ++ return (int)sid; ++} ++ ++void close_session(int sid) ++{ ++ MV_STATUS status; ++ ++ status = mvCesaSessionClose(sid); ++ if(status != MV_OK) ++ { ++ mvOsPrintf("CesaTest: Can't close session %d - status = 0x%x\n", ++ sid, status); ++ } ++} ++ ++MV_STATUS testOpen(int idx) ++{ ++ MV_CESA_OPEN_SESSION os; ++ int sid, i, testIdx; ++ MV_CESA_TEST_SESSION* pTestSession; ++ MV_U16 digestSize = 0; ++ ++ pTestSession = getTestSessionDb(idx, &testIdx); ++ if(pTestSession == NULL) ++ { ++ mvOsPrintf("Test %d is not exist\n", idx); ++ return MV_BAD_PARAM; ++ } ++ pTestSession = &pTestSession[testIdx]; ++ ++ if(pTestSession->sid != -1) ++ { ++ mvOsPrintf("Session for test %d already created: sid=%d\n", ++ idx, pTestSession->sid); ++ return MV_OK; ++ } ++ ++ os.cryptoAlgorithm = pTestSession->cryptoAlgorithm; ++ os.macMode = pTestSession->macAlgorithm; ++ switch(os.macMode) ++ { ++ case MV_CESA_MAC_MD5: ++ case MV_CESA_MAC_HMAC_MD5: ++ digestSize = MV_CESA_MD5_DIGEST_SIZE; ++ break; ++ ++ case MV_CESA_MAC_SHA1: ++ case MV_CESA_MAC_HMAC_SHA1: ++ digestSize = MV_CESA_SHA1_DIGEST_SIZE; ++ break; ++ ++ case MV_CESA_MAC_NULL: ++ digestSize = 0; ++ } ++ os.cryptoMode = pTestSession->cryptoMode; ++ os.direction = pTestSession->direction; ++ os.operation = pTestSession->operation; ++ ++ for(i=0; icryptoKeySize; i++) ++ os.cryptoKey[i] = pTestSession->pCryptoKey[i]; ++ ++ os.cryptoKeyLength = pTestSession->cryptoKeySize; ++ ++ for(i=0; imacKeySize; i++) ++ os.macKey[i] = pTestSession->pMacKey[i]; ++ ++ os.macKeyLength = pTestSession->macKeySize; ++ os.digestSize = digestSize; ++ ++ sid = open_session(&os); ++ if(sid == -1) ++ { ++ mvOsPrintf("Can't open session for test %d: rc=0x%x\n", ++ idx, cesaResult.retCode); ++ return cesaResult.retCode; ++ } ++ CESA_TEST_DEBUG_PRINT(("Opened session: sid = %d\n", sid)); ++ pTestSession->sid = sid; ++ return MV_OK; ++} ++ ++MV_STATUS testClose(int idx) ++{ ++ int testIdx; ++ MV_CESA_TEST_SESSION* pTestSession; ++ ++ pTestSession = getTestSessionDb(idx, &testIdx); ++ if(pTestSession == NULL) ++ { ++ mvOsPrintf("Test %d is not exist\n", idx); ++ return MV_BAD_PARAM; ++ } ++ pTestSession = &pTestSession[testIdx]; ++ ++ if(pTestSession->sid == -1) ++ { ++ mvOsPrintf("Test session %d is not opened\n", idx); ++ return MV_NO_SUCH; ++ } ++ ++ close_session(pTestSession->sid); ++ pTestSession->sid = -1; ++ ++ return MV_OK; ++} ++ ++MV_STATUS testCmd(int sid, int iter, MV_CESA_COMMAND* pCmd, ++ MV_CESA_TEST_SESSION* pTestSession, MV_U8* pIV, int ivSize) ++{ ++ int cmdReqId = 0; ++ int i; ++ MV_STATUS rc = MV_OK; ++ char ivZeroHex[] = "0000"; ++ ++ if(iter == 0) ++ iter = CESA_DEF_ITER_NUM; ++ ++ if(pCmd == NULL) ++ { ++ mvOsPrintf("testCmd failed: pCmd=NULL\n"); ++ return MV_BAD_PARAM; ++ } ++ pCmd->sessionId = sid; ++ ++ cesaCryptoError = 0; ++ cesaReqIdError = 0; ++ cesaError = 0; ++ cesaTestIsrMissCount = 0; ++ cesaIsReady = MV_FALSE; ++ cesaIteration = iter; ++ ++ if(cesaInputHexStr == NULL) ++ cesaInputHexStr = cesaPlainHexEbc; ++ ++ for(i=0; ipSrc = (MV_CESA_MBUF*)(cesaCmdRing[i].pSrc); ++ if(pIV != NULL) ++ { ++ /* If IV from SA - set IV in Source buffer to zeros */ ++ cesaSetMbuf(pCmd->pSrc, ivZeroHex, 0, pCmd->cryptoOffset); ++ cesaSetMbuf(pCmd->pSrc, cesaInputHexStr, pCmd->cryptoOffset, ++ (cesaReqSize - pCmd->cryptoOffset)); ++ } ++ else ++ { ++ cesaSetMbuf(pCmd->pSrc, cesaInputHexStr, 0, cesaReqSize); ++ } ++ pCmd->pDst = (MV_CESA_MBUF*)(cesaCmdRing[i].pDst); ++ cesaSetMbuf(pCmd->pDst, cesaNullPlainHexText, 0, cesaReqSize); ++ ++ memcpy(&cesaCmdRing[i], pCmd, sizeof(*pCmd)); ++ } ++ ++ if(cesaCheckMode == CESA_SW_SHOW_CHECK_MODE) ++ { ++ MV_U8 pDigest[MV_CESA_MAX_DIGEST_SIZE]; ++ ++ if(pTestSession->macAlgorithm == MV_CESA_MAC_MD5) ++ { ++ mvMD5(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, pDigest); ++ mvOsPrintf("SW HASH_MD5: reqSize=%d, macLength=%d\n", ++ cesaReqSize, pCmd->macLength); ++ mvDebugMemDump(pDigest, MV_CESA_MD5_DIGEST_SIZE, 1); ++ return MV_OK; ++ } ++ if(pTestSession->macAlgorithm == MV_CESA_MAC_SHA1) ++ { ++ mvSHA1(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, pDigest); ++ mvOsPrintf("SW HASH_SHA1: reqSize=%d, macLength=%d\n", ++ cesaReqSize, pCmd->macLength); ++ mvDebugMemDump(pDigest, MV_CESA_SHA1_DIGEST_SIZE, 1); ++ return MV_OK; ++ } ++ } ++ ++ cesaBeginTicks = CESA_TEST_TICK_GET(); ++ CESA_TEST_DEBUG_CODE( memset(cesaTestTrace, 0, sizeof(cesaTestTrace)); ++ cesaTestTraceIdx = 0; ++ ); ++ ++ if(cesaCheckMode == CESA_SW_NULL_CHECK_MODE) ++ { ++ volatile MV_U8 pDigest[MV_CESA_MAX_DIGEST_SIZE]; ++ ++ for(i=0; imacAlgorithm == MV_CESA_MAC_MD5) ++ { ++ mvMD5(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, (unsigned char*)pDigest); ++ } ++ if(pTestSession->macAlgorithm == MV_CESA_MAC_SHA1) ++ { ++ mvSHA1(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, (MV_U8 *)pDigest); ++ } ++ } ++ cesaEndTicks = CESA_TEST_TICK_GET(); ++ cesaRate = getRate(&cesaRateAfterDot); ++ cesaIsReady = MV_TRUE; ++ ++ return MV_OK; ++ } ++ ++ /*cesaTestIsrCount = 0;*/ ++ /*mvCesaDebugStatsClear();*/ ++ ++#ifndef MV_NETBSD ++ MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); ++#endif ++ ++ for(i=0; ipReqPrv = (void*)cmdReqId; ++ ++ CESA_TEST_LOCK(flags); ++ ++ rc = mvCesaAction(pCmd); ++ if(rc == MV_NO_RESOURCE) ++ cesaTestFull = 1; ++ ++ CESA_TEST_UNLOCK(flags); ++ ++ if(rc == MV_NO_RESOURCE) ++ { ++ CESA_TEST_LOCK(flags); ++ CESA_TEST_WAIT( (cesaTestFull == 0), 100); ++ CESA_TEST_UNLOCK(flags); ++ if(cesaTestFull == 1) ++ { ++ mvOsPrintf("CESA Test timeout: i=%d, iter=%d, cesaTestFull=%d\n", ++ i, iter, cesaTestFull); ++ cesaTestFull = 0; ++ return MV_TIMEOUT; ++ } ++ ++ CESA_TEST_LOCK(flags); ++ ++ rc = mvCesaAction(pCmd); ++ ++ CESA_TEST_UNLOCK(flags); ++ } ++ if( (rc != MV_OK) && (rc != MV_NO_MORE) ) ++ { ++ mvOsPrintf("mvCesaAction failed: rc=%d\n", rc); ++ return rc; ++ } ++ ++ cmdReqId++; ++ if(cmdReqId >= CESA_DEF_REQ_SIZE) ++ cmdReqId = 0; ++ ++#ifdef MV_LINUX ++ /* Reschedule each 16 requests */ ++ if( (i & 0xF) == 0) ++ schedule(); ++#endif ++ } ++ return MV_OK; ++} ++ ++void cesaTestStart(int bufNum, int bufSize) ++{ ++ int i, j, idx; ++ MV_CESA_MBUF *pMbufSrc, *pMbufDst; ++ MV_BUF_INFO *pFragsSrc, *pFragsDst; ++ char *pBuf; ++#ifndef MV_NETBSD ++ int numOfSessions, queueDepth; ++ char *pSram; ++ MV_STATUS status; ++ MV_CPU_DEC_WIN addrDecWin; ++#endif ++ ++ cesaCmdRing = mvOsMalloc(sizeof(MV_CESA_COMMAND) * CESA_DEF_REQ_SIZE); ++ if(cesaCmdRing == NULL) ++ { ++ mvOsPrintf("testStart: Can't allocate %ld bytes of memory\n", ++ sizeof(MV_CESA_COMMAND) * CESA_DEF_REQ_SIZE); ++ return; ++ } ++ memset(cesaCmdRing, 0, sizeof(MV_CESA_COMMAND) * CESA_DEF_REQ_SIZE); ++ ++ if(bufNum == 0) ++ bufNum = CESA_DEF_BUF_NUM; ++ ++ if(bufSize == 0) ++ bufSize = CESA_DEF_BUF_SIZE; ++ ++ cesaBufNum = bufNum; ++ cesaBufSize = bufSize; ++ mvOsPrintf("CESA test started: bufNum = %d, bufSize = %d\n", ++ bufNum, bufSize); ++ ++ cesaHexBuffer = mvOsMalloc(2*bufNum*bufSize); ++ if(cesaHexBuffer == NULL) ++ { ++ mvOsPrintf("testStart: Can't malloc %d bytes for cesaHexBuffer.\n", ++ 2*bufNum*bufSize); ++ return; ++ } ++ memset(cesaHexBuffer, 0, (2*bufNum*bufSize)); ++ ++ cesaBinBuffer = mvOsMalloc(bufNum*bufSize); ++ if(cesaBinBuffer == NULL) ++ { ++ mvOsPrintf("testStart: Can't malloc %d bytes for cesaBinBuffer\n", ++ bufNum*bufSize); ++ return; ++ } ++ memset(cesaBinBuffer, 0, (bufNum*bufSize)); ++ ++ cesaExpBinBuffer = mvOsMalloc(bufNum*bufSize); ++ if(cesaExpBinBuffer == NULL) ++ { ++ mvOsPrintf("testStart: Can't malloc %d bytes for cesaExpBinBuffer\n", ++ bufNum*bufSize); ++ return; ++ } ++ memset(cesaExpBinBuffer, 0, (bufNum*bufSize)); ++ ++ CESA_TEST_WAIT_INIT(); ++ ++ pMbufSrc = mvOsMalloc(sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); ++ pFragsSrc = mvOsMalloc(sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); ++ ++ pMbufDst = mvOsMalloc(sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); ++ pFragsDst = mvOsMalloc(sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); ++ ++ if( (pMbufSrc == NULL) || (pFragsSrc == NULL) || ++ (pMbufDst == NULL) || (pFragsDst == NULL) ) ++ { ++ mvOsPrintf("testStart: Can't malloc Src and Dst pMbuf and pFrags structures.\n"); ++ /* !!!! Dima cesaTestCleanup();*/ ++ return; ++ } ++ ++ memset(pMbufSrc, 0, sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); ++ memset(pFragsSrc, 0, sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); ++ ++ memset(pMbufDst, 0, sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); ++ memset(pFragsDst, 0, sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); ++ ++ mvOsPrintf("Cesa Test Start: pMbufSrc=%p, pFragsSrc=%p, pMbufDst=%p, pFragsDst=%p\n", ++ pMbufSrc, pFragsSrc, pMbufDst, pFragsDst); ++ ++ idx = 0; ++ for(i=0; ipFrags = &pFragsSrc[idx]; ++ cesaCmdRing[i].pSrc->numFrags = bufNum; ++ cesaCmdRing[i].pSrc->mbufSize = 0; ++ ++ cesaCmdRing[i].pDst = &pMbufDst[i]; ++ cesaCmdRing[i].pDst->pFrags = &pFragsDst[idx]; ++ cesaCmdRing[i].pDst->numFrags = bufNum; ++ cesaCmdRing[i].pDst->mbufSize = 0; ++ ++ for(j=0; jpFrags[j].bufVirtPtr = (MV_U8*)pBuf; ++ cesaCmdRing[i].pSrc->pFrags[j].bufSize = bufSize; ++ pBuf += bufSize; ++ cesaCmdRing[i].pDst->pFrags[j].bufVirtPtr = (MV_U8*)pBuf; ++ cesaCmdRing[i].pDst->pFrags[j].bufSize = bufSize; ++ pBuf += bufSize; ++ } ++ idx += bufNum; ++ } ++ ++#ifndef MV_NETBSD ++ if (mvCpuIfTargetWinGet(CRYPT_ENG, &addrDecWin) == MV_OK) ++ pSram = (char*)addrDecWin.addrWin.baseLow; ++ else ++ { ++ mvOsPrintf("mvCesaInit: ERR. mvCpuIfTargetWinGet failed\n"); ++ return; ++ } ++ ++#ifdef MV_CESA_NO_SRAM ++ pSram = mvOsMalloc(4*1024+8); ++ if(pSram == NULL) ++ { ++ mvOsPrintf("CesaTest: can't allocate %d bytes for SRAM simulation\n", ++ 4*1024+8); ++ /* !!!! Dima cesaTestCleanup();*/ ++ return; ++ } ++ pSram = (MV_U8*)MV_ALIGN_UP((MV_U32)pSram, 8); ++#endif /* MV_CESA_NO_SRAM */ ++ ++ numOfSessions = CESA_DEF_SESSION_NUM; ++ queueDepth = CESA_DEF_REQ_SIZE - MV_CESA_MAX_CHAN; ++ ++ status = mvCesaInit(numOfSessions, queueDepth, pSram, NULL); ++ if(status != MV_OK) ++ { ++ mvOsPrintf("mvCesaInit is Failed: status = 0x%x\n", status); ++ /* !!!! Dima cesaTestCleanup();*/ ++ return; ++ } ++#endif /* !MV_NETBSD */ ++ ++ /* Prepare data for tests */ ++ for(i=0; i<50; i++) ++ strcat((char*)cesaDataHexStr3, "dd"); ++ ++ strcpy((char*)cesaDataAndMd5digest3, cesaDataHexStr3); ++ strcpy((char*)cesaDataAndSha1digest3, cesaDataHexStr3); ++ ++ /* Digest must be 8 byte aligned */ ++ for(; i<56; i++) ++ { ++ strcat((char*)cesaDataAndMd5digest3, "00"); ++ strcat((char*)cesaDataAndSha1digest3, "00"); ++ } ++ strcat((char*)cesaDataAndMd5digest3, cesaHmacMd5digestHex3); ++ strcat((char*)cesaDataAndSha1digest3, cesaHmacSha1digestHex3); ++ ++#ifndef MV_NETBSD ++ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); ++ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, MV_CESA_CAUSE_ACC_DMA_MASK); ++#endif ++ ++#ifdef MV_VXWORKS ++ { ++ MV_STATUS status; ++ ++ status = intConnect((VOIDFUNCPTR *)INT_LVL_CESA, cesaTestReadyIsr, (int)NULL); ++ if (status != OK) ++ { ++ mvOsPrintf("CESA: Can't connect CESA (%d) interrupt, status=0x%x \n", ++ INT_LVL_CESA, status); ++ /* !!!! Dima cesaTestCleanup();*/ ++ return; ++ } ++ cesaSemId = semMCreate(SEM_Q_PRIORITY | SEM_INVERSION_SAFE | SEM_DELETE_SAFE); ++ if(cesaSemId == NULL) ++ { ++ mvOsPrintf("cesaTestStart: Can't create semaphore\n"); ++ return; ++ } ++ intEnable(INT_LVL_CESA); ++ } ++#endif /* MV_VXWORKS */ ++ ++#if !defined(MV_NETBSD) && defined(__KERNEL__) ++ if( request_irq(CESA_IRQ, cesaTestReadyIsr, (SA_INTERRUPT) , "cesa_test", NULL ) ) ++ { ++ mvOsPrintf( "cannot assign irq\n" ); ++ /* !!!! Dima cesaTestCleanup();*/ ++ return; ++ } ++ spin_lock_init( &cesaLock ); ++#endif ++} ++ ++MV_STATUS testRun(int idx, int caseIdx, int iter, ++ int reqSize, int checkMode) ++{ ++ int testIdx, count, sid, digestSize; ++ int blockSize; ++ MV_CESA_TEST_SESSION* pTestSession; ++ MV_CESA_COMMAND cmd; ++ MV_STATUS status; ++ ++ memset(&cmd, 0, sizeof(cmd)); ++ ++ pTestSession = getTestSessionDb(idx, &testIdx); ++ if(pTestSession == NULL) ++ { ++ mvOsPrintf("Test %d is not exist\n", idx); ++ return MV_BAD_PARAM; ++ } ++ pTestSession = &pTestSession[testIdx]; ++ ++ sid = pTestSession->sid; ++ if(sid == -1) ++ { ++ mvOsPrintf("Test %d is not opened\n", idx); ++ return MV_BAD_STATE; ++ } ++ switch(pTestSession->cryptoAlgorithm) ++ { ++ case MV_CESA_CRYPTO_DES: ++ case MV_CESA_CRYPTO_3DES: ++ blockSize = MV_CESA_DES_BLOCK_SIZE; ++ break; ++ ++ case MV_CESA_CRYPTO_AES: ++ blockSize = MV_CESA_AES_BLOCK_SIZE; ++ break; ++ ++ case MV_CESA_CRYPTO_NULL: ++ blockSize = 0; ++ break; ++ ++ default: ++ mvOsPrintf("cesaTestRun: Bad CryptoAlgorithm=%d\n", ++ pTestSession->cryptoAlgorithm); ++ return MV_BAD_PARAM; ++ } ++ switch(pTestSession->macAlgorithm) ++ { ++ case MV_CESA_MAC_MD5: ++ case MV_CESA_MAC_HMAC_MD5: ++ digestSize = MV_CESA_MD5_DIGEST_SIZE; ++ break; ++ ++ case MV_CESA_MAC_SHA1: ++ case MV_CESA_MAC_HMAC_SHA1: ++ digestSize = MV_CESA_SHA1_DIGEST_SIZE; ++ break; ++ default: ++ digestSize = 0; ++ } ++ ++ if(iter == 0) ++ iter = CESA_DEF_ITER_NUM; ++ ++ if(pTestSession->direction == MV_CESA_DIR_ENCODE) ++ { ++ cesaOutputHexStr = cesaTestCases[caseIdx].cipherHexStr; ++ cesaInputHexStr = cesaTestCases[caseIdx].plainHexStr; ++ } ++ else ++ { ++ cesaOutputHexStr = cesaTestCases[caseIdx].plainHexStr; ++ cesaInputHexStr = cesaTestCases[caseIdx].cipherHexStr; ++ } ++ ++ cmd.sessionId = sid; ++ if(checkMode == CESA_FAST_CHECK_MODE) ++ { ++ cmd.cryptoLength = cesaTestCases[caseIdx].cryptoLength; ++ cmd.macLength = cesaTestCases[caseIdx].macLength; ++ } ++ else ++ { ++ cmd.cryptoLength = reqSize; ++ cmd.macLength = reqSize; ++ } ++ cesaRateSize = cmd.cryptoLength; ++ cesaReqSize = cmd.cryptoLength; ++ cmd.cryptoOffset = 0; ++ if(pTestSession->operation != MV_CESA_MAC_ONLY) ++ { ++ if( (pTestSession->cryptoMode == MV_CESA_CRYPTO_CBC) || ++ (pTestSession->cryptoMode == MV_CESA_CRYPTO_CTR) ) ++ { ++ cmd.ivOffset = 0; ++ cmd.cryptoOffset = blockSize; ++ if(cesaTestCases[caseIdx].pCryptoIV == NULL) ++ { ++ cmd.ivFromUser = 1; ++ } ++ else ++ { ++ cmd.ivFromUser = 0; ++ mvCesaCryptoIvSet(cesaTestCases[caseIdx].pCryptoIV, blockSize); ++ } ++ cesaReqSize = cmd.cryptoOffset + cmd.cryptoLength; ++ } ++ } ++ ++/* ++ mvOsPrintf("ivFromUser=%d, cryptoLength=%d, cesaReqSize=%d, cryptoOffset=%d\n", ++ cmd.ivFromUser, cmd.cryptoLength, cesaReqSize, cmd.cryptoOffset); ++*/ ++ if(pTestSession->operation != MV_CESA_CRYPTO_ONLY) ++ { ++ cmd.macOffset = cmd.cryptoOffset; ++ ++ if(cesaTestCases[caseIdx].digestOffset == -1) ++ { ++ cmd.digestOffset = cmd.macOffset + cmd.macLength; ++ cmd.digestOffset = MV_ALIGN_UP(cmd.digestOffset, 8); ++ } ++ else ++ { ++ cmd.digestOffset = cesaTestCases[caseIdx].digestOffset; ++ } ++ if( (cmd.digestOffset + digestSize) > cesaReqSize) ++ cesaReqSize = cmd.digestOffset + digestSize; ++ } ++ ++ cesaCheckMode = checkMode; ++ ++ if(checkMode == CESA_NULL_CHECK_MODE) ++ { ++ cesaCheckSize = 0; ++ cesaCheckOffset = 0; ++ } ++ else ++ { ++ if(pTestSession->operation == MV_CESA_CRYPTO_ONLY) ++ { ++ cesaCheckOffset = 0; ++ cesaCheckSize = cmd.cryptoLength; ++ } ++ else ++ { ++ cesaCheckSize = digestSize; ++ cesaCheckOffset = cmd.digestOffset; ++ } ++ } ++/* ++ mvOsPrintf("reqSize=%d, checkSize=%d, checkOffset=%d, checkMode=%d\n", ++ cesaReqSize, cesaCheckSize, cesaCheckOffset, cesaCheckMode); ++ ++ mvOsPrintf("blockSize=%d, ivOffset=%d, ivFromUser=%d, crOffset=%d, crLength=%d\n", ++ blockSize, cmd.ivOffset, cmd.ivFromUser, ++ cmd.cryptoOffset, cmd.cryptoLength); ++ ++ mvOsPrintf("macOffset=%d, digestOffset=%d, macLength=%d\n", ++ cmd.macOffset, cmd.digestOffset, cmd.macLength); ++*/ ++ status = testCmd(sid, iter, &cmd, pTestSession, ++ cesaTestCases[caseIdx].pCryptoIV, blockSize); ++ ++ if(status != MV_OK) ++ return status; ++ ++ /* Wait when all callbacks is received */ ++ count = 0; ++ while(cesaIsReady == MV_FALSE) ++ { ++ mvOsSleep(10); ++ count++; ++ if(count > 100) ++ { ++ mvOsPrintf("testRun: Timeout occured\n"); ++ return MV_TIMEOUT; ++ } ++ } ++ ++ return MV_OK; ++} ++ ++ ++void cesaTestStop(void) ++{ ++ MV_CESA_MBUF *pMbufSrc, *pMbufDst; ++ MV_BUF_INFO *pFragsSrc, *pFragsDst; ++ int i; ++ ++ /* Release all allocated memories */ ++ pMbufSrc = (MV_CESA_MBUF*)(cesaCmdRing[0].pSrc); ++ pFragsSrc = cesaCmdRing[0].pSrc->pFrags; ++ ++ pMbufDst = (MV_CESA_MBUF*)(cesaCmdRing[0].pDst); ++ pFragsDst = cesaCmdRing[0].pDst->pFrags; ++ ++ mvOsFree(pMbufSrc); ++ mvOsFree(pMbufDst); ++ mvOsFree(pFragsSrc); ++ mvOsFree(pFragsDst); ++ ++ for(i=0; i 0) ++ cryptoError++; ++ if(cesaReqIdError > 0) ++ reqIdError++; ++ ++ testClose(idx); ++ } ++ } ++ if(cryptoError > 0) ++ mvOsPrintf("cryptoError : %d\n", cryptoError); ++ if(reqIdError > 0) ++ mvOsPrintf("reqIdError : %d\n", reqIdError); ++ ++ if(openErrors > 0) ++ { ++ mvOsPrintf("Open Errors = %d\n", openErrors); ++ for(i=0; i<100; i++) ++ { ++ if(openErrDisp[i] != 0) ++ mvOsPrintf("Error %d - occurs %d times\n", i, openErrDisp[i]); ++ } ++ } ++} ++ ++ ++void loopback_test(int idx, int iter, int size, char* pPlainData) ++{ ++} ++ ++ ++#if defined(MV_VXWORKS) ++int testMode = 0; ++unsigned __TASKCONV cesaTask(void* args) ++{ ++ int reqSize = cesaReqSize; ++ ++ if(testMode == 0) ++ { ++ cesaOneTest(cesaTestIdx, cesaCaseIdx, cesaIteration, ++ reqSize, cesaCheckMode); ++ } ++ else ++ { ++ if(testMode == 1) ++ { ++ cesaTest(cesaIteration, reqSize, cesaCheckMode); ++ combiTest(cesaIteration, reqSize, cesaCheckMode); ++ } ++ else ++ { ++ multiSizeTest(cesaIdx, cesaIteration, cesaCheckMode, NULL); ++ } ++ } ++ return 0; ++} ++ ++void oneTest(int testIdx, int caseIdx, ++ int iter, int reqSize, int checkMode) ++{ ++ long rc; ++ ++ cesaIteration = iter; ++ cesaReqSize = cesaRateSize = reqSize; ++ cesaCheckMode = checkMode; ++ testMode = 0; ++ cesaTestIdx = testIdx; ++ cesaCaseIdx = caseIdx; ++ rc = mvOsTaskCreate("CESA_T", 100, 4*1024, cesaTask, NULL, &cesaTaskId); ++ if (rc != MV_OK) ++ { ++ mvOsPrintf("hMW: Can't create CESA multiCmd test task, rc = %ld\n", rc); ++ } ++} ++ ++void multiTest(int iter, int reqSize, int checkMode) ++{ ++ long rc; ++ ++ cesaIteration = iter; ++ cesaCheckMode = checkMode; ++ cesaReqSize = reqSize; ++ testMode = 1; ++ rc = mvOsTaskCreate("CESA_T", 100, 4*1024, cesaTask, NULL, &cesaTaskId); ++ if (rc != MV_OK) ++ { ++ mvOsPrintf("hMW: Can't create CESA multiCmd test task, rc = %ld\n", rc); ++ } ++} ++ ++void sizeTest(int testIdx, int iter, int checkMode) ++{ ++ long rc; ++ ++ cesaIteration = iter; ++ cesaCheckMode = checkMode; ++ testMode = 2; ++ cesaIdx = testIdx; ++ rc = mvOsTaskCreate("CESA_T", 100, 4*1024, cesaTask, NULL, &cesaTaskId); ++ if (rc != MV_OK) ++ { ++ mvOsPrintf("hMW: Can't create CESA test task, rc = %ld\n", rc); ++ } ++} ++ ++#endif /* MV_VXWORKS */ ++ ++extern void mvCesaDebugSA(short sid, int mode); ++void cesaTestPrintSession(int idx) ++{ ++ int testIdx; ++ MV_CESA_TEST_SESSION* pTestSession; ++ ++ pTestSession = getTestSessionDb(idx, &testIdx); ++ if(pTestSession == NULL) ++ { ++ mvOsPrintf("Test %d is not exist\n", idx); ++ return; ++ } ++ pTestSession = &pTestSession[testIdx]; ++ ++ if(pTestSession->sid == -1) ++ { ++ mvOsPrintf("Test session %d is not opened\n", idx); ++ return; ++ } ++ ++ mvCesaDebugSA(pTestSession->sid, 1); ++} ++ ++void cesaTestPrintStatus(void) ++{ ++ mvOsPrintf("\n\t Cesa Test Status\n\n"); ++ ++ mvOsPrintf("isrCount=%d\n", ++ cesaTestIsrCount); ++ ++#ifdef CESA_TEST_DEBUG ++ { ++ int i, j; ++ j = cesaTestTraceIdx; ++ mvOsPrintf("No Type Cause rCause iCause Res Time pReady pProc pEmpty\n"); ++ for(i=0; itable = mvOsMalloc(numOfEntries*sizeof(MV_LRU_ENTRY)); ++ if(pLruCache->table == NULL) ++ { ++ mvOsFree(pLruCache); ++ return NULL; ++ } ++ memset(pLruCache->table, 0, numOfEntries*sizeof(MV_LRU_ENTRY)); ++ pLruCache->tableSize = numOfEntries; ++ ++ for(i=0; itable[i].next = i+1; ++ pLruCache->table[i].prev = i-1; ++ } ++ pLruCache->least = 0; ++ pLruCache->most = numOfEntries-1; ++ ++ return pLruCache; ++} ++ ++void mvLruCacheFinish(MV_LRU_CACHE* pLruCache) ++{ ++ mvOsFree(pLruCache->table); ++ mvOsFree(pLruCache); ++} ++ ++/* Update LRU cache database after using cache Index */ ++void mvLruCacheIdxUpdate(MV_LRU_CACHE* pLruHndl, int cacheIdx) ++{ ++ int prev, next; ++ ++ if(cacheIdx == pLruHndl->most) ++ return; ++ ++ next = pLruHndl->table[cacheIdx].next; ++ if(cacheIdx == pLruHndl->least) ++ { ++ pLruHndl->least = next; ++ } ++ else ++ { ++ prev = pLruHndl->table[cacheIdx].prev; ++ ++ pLruHndl->table[next].prev = prev; ++ pLruHndl->table[prev].next = next; ++ } ++ ++ pLruHndl->table[pLruHndl->most].next = cacheIdx; ++ pLruHndl->table[cacheIdx].prev = pLruHndl->most; ++ pLruHndl->most = cacheIdx; ++} ++ ++/* Delete LRU cache entry */ ++void mvLruCacheIdxDelete(MV_LRU_CACHE* pLruHndl, int cacheIdx) ++{ ++ int prev, next; ++ ++ if(cacheIdx == pLruHndl->least) ++ return; ++ ++ prev = pLruHndl->table[cacheIdx].prev; ++ if(cacheIdx == pLruHndl->most) ++ { ++ pLruHndl->most = prev; ++ } ++ else ++ { ++ next = pLruHndl->table[cacheIdx].next; ++ ++ pLruHndl->table[next].prev = prev; ++ pLruHndl->table[prev].next = next; ++ } ++ pLruHndl->table[pLruHndl->least].prev = cacheIdx; ++ pLruHndl->table[cacheIdx].next = pLruHndl->least; ++ pLruHndl->least = cacheIdx; ++} +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvLru.h linux-3.0.4/crypto/ocf/kirkwood/cesa/mvLru.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvLru.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/cesa/mvLru.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,112 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++/******************************************************************************* ++* mvLru.h - Header File for Least Recently Used Cache algorithm ++* ++* DESCRIPTION: ++* This header file contains macros typedefs and function declaration for ++* the Least Recently Used Cache algorithm. ++* ++*******************************************************************************/ ++ ++#ifndef __mvLru_h__ ++#define __mvLru_h__ ++ ++ ++typedef struct ++{ ++ int next; ++ int prev; ++} MV_LRU_ENTRY; ++ ++typedef struct ++{ ++ int least; ++ int most; ++ MV_LRU_ENTRY* table; ++ int tableSize; ++ ++}MV_LRU_CACHE; ++ ++ ++/* Find Cache index for replacement LRU */ ++static INLINE int mvLruCacheIdxFind(MV_LRU_CACHE* pLruHndl) ++{ ++ return pLruHndl->least; ++} ++ ++/* Init LRU cache module */ ++MV_LRU_CACHE* mvLruCacheInit(int numOfEntries); ++ ++/* Finish LRU cache module */ ++void mvLruCacheFinish(MV_LRU_CACHE* pLruHndl); ++ ++/* Update LRU cache database after using cache Index */ ++void mvLruCacheIdxUpdate(MV_LRU_CACHE* pLruHndl, int cacheIdx); ++ ++/* Delete LRU cache entry */ ++void mvLruCacheIdxDelete(MV_LRU_CACHE* pLruHndl, int cacheIdx); ++ ++ ++#endif /* __mvLru_h__ */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvMD5.c linux-3.0.4/crypto/ocf/kirkwood/cesa/mvMD5.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvMD5.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/cesa/mvMD5.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,349 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#include "mvOs.h" ++#include "mvMD5.h" ++ ++static void mvMD5Transform(MV_U32 buf[4], MV_U32 const in[MV_MD5_MAC_LEN]); ++ ++#ifdef MV_CPU_LE ++#define mvByteReverse(buf, len) /* Nothing */ ++#else ++static void mvByteReverse(unsigned char *buf, unsigned longs); ++ ++/* ++ * Note: this code is harmless on little-endian machines. ++ */ ++static void mvByteReverse(unsigned char *buf, unsigned longs) ++{ ++ MV_U32 t; ++ ++ do ++ { ++ t = (MV_U32) ((unsigned) buf[3] << 8 | buf[2]) << 16 | ++ ((unsigned) buf[1] << 8 | buf[0]); ++ *(MV_U32 *) buf = t; ++ buf += 4; ++ } while (--longs); ++} ++#endif ++ ++/* ++ * Start MD5 accumulation. Set bit count to 0 and buffer to mysterious ++ * initialization constants. ++ */ ++void mvMD5Init(MV_MD5_CONTEXT *ctx) ++{ ++ ctx->buf[0] = 0x67452301; ++ ctx->buf[1] = 0xefcdab89; ++ ctx->buf[2] = 0x98badcfe; ++ ctx->buf[3] = 0x10325476; ++ ++ ctx->bits[0] = 0; ++ ctx->bits[1] = 0; ++} ++ ++/* ++ * Update context to reflect the concatenation of another buffer full ++ * of bytes. ++ */ ++void mvMD5Update(MV_MD5_CONTEXT *ctx, unsigned char const *buf, unsigned len) ++{ ++ MV_U32 t; ++ ++ /* Update bitcount */ ++ ++ t = ctx->bits[0]; ++ if ((ctx->bits[0] = t + ((MV_U32) len << 3)) < t) ++ ctx->bits[1]++; /* Carry from low to high */ ++ ctx->bits[1] += len >> 29; ++ ++ t = (t >> 3) & 0x3f; /* Bytes already in shsInfo->data */ ++ ++ /* Handle any leading odd-sized chunks */ ++ ++ if (t) ++ { ++ unsigned char *p = (unsigned char *) ctx->in + t; ++ ++ t = 64 - t; ++ if (len < t) ++ { ++ memcpy(p, buf, len); ++ return; ++ } ++ memcpy(p, buf, t); ++ mvByteReverse(ctx->in, MV_MD5_MAC_LEN); ++ mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in); ++ buf += t; ++ len -= t; ++ } ++ /* Process data in 64-byte chunks */ ++ ++ while (len >= 64) ++ { ++ memcpy(ctx->in, buf, 64); ++ mvByteReverse(ctx->in, MV_MD5_MAC_LEN); ++ mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in); ++ buf += 64; ++ len -= 64; ++ } ++ ++ /* Handle any remaining bytes of data. */ ++ ++ memcpy(ctx->in, buf, len); ++} ++ ++/* ++ * Final wrapup - pad to 64-byte boundary with the bit pattern ++ * 1 0* (64-bit count of bits processed, MSB-first) ++ */ ++void mvMD5Final(unsigned char digest[MV_MD5_MAC_LEN], MV_MD5_CONTEXT *ctx) ++{ ++ unsigned count; ++ unsigned char *p; ++ ++ /* Compute number of bytes mod 64 */ ++ count = (ctx->bits[0] >> 3) & 0x3F; ++ ++ /* Set the first char of padding to 0x80. This is safe since there is ++ always at least one byte free */ ++ p = ctx->in + count; ++ *p++ = 0x80; ++ ++ /* Bytes of padding needed to make 64 bytes */ ++ count = 64 - 1 - count; ++ ++ /* Pad out to 56 mod 64 */ ++ if (count < 8) ++ { ++ /* Two lots of padding: Pad the first block to 64 bytes */ ++ memset(p, 0, count); ++ mvByteReverse(ctx->in, MV_MD5_MAC_LEN); ++ mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in); ++ ++ /* Now fill the next block with 56 bytes */ ++ memset(ctx->in, 0, 56); ++ } ++ else ++ { ++ /* Pad block to 56 bytes */ ++ memset(p, 0, count - 8); ++ } ++ mvByteReverse(ctx->in, 14); ++ ++ /* Append length in bits and transform */ ++ ((MV_U32 *) ctx->in)[14] = ctx->bits[0]; ++ ((MV_U32 *) ctx->in)[15] = ctx->bits[1]; ++ ++ mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in); ++ mvByteReverse((unsigned char *) ctx->buf, 4); ++ memcpy(digest, ctx->buf, MV_MD5_MAC_LEN); ++ memset(ctx, 0, sizeof(ctx)); /* In case it's sensitive */ ++} ++ ++/* The four core functions - F1 is optimized somewhat */ ++ ++/* #define F1(x, y, z) (x & y | ~x & z) */ ++#define F1(x, y, z) (z ^ (x & (y ^ z))) ++#define F2(x, y, z) F1(z, x, y) ++#define F3(x, y, z) (x ^ y ^ z) ++#define F4(x, y, z) (y ^ (x | ~z)) ++ ++/* This is the central step in the MD5 algorithm. */ ++#define MD5STEP(f, w, x, y, z, data, s) \ ++ ( w += f(x, y, z) + data, w = w<>(32-s), w += x ) ++ ++/* ++ * The core of the MD5 algorithm, this alters an existing MD5 hash to ++ * reflect the addition of 16 longwords of new data. MD5Update blocks ++ * the data and converts bytes into longwords for this routine. ++ */ ++static void mvMD5Transform(MV_U32 buf[4], MV_U32 const in[MV_MD5_MAC_LEN]) ++{ ++ register MV_U32 a, b, c, d; ++ ++ a = buf[0]; ++ b = buf[1]; ++ c = buf[2]; ++ d = buf[3]; ++ ++ MD5STEP(F1, a, b, c, d, in[0] + 0xd76aa478, 7); ++ MD5STEP(F1, d, a, b, c, in[1] + 0xe8c7b756, 12); ++ MD5STEP(F1, c, d, a, b, in[2] + 0x242070db, 17); ++ MD5STEP(F1, b, c, d, a, in[3] + 0xc1bdceee, 22); ++ MD5STEP(F1, a, b, c, d, in[4] + 0xf57c0faf, 7); ++ MD5STEP(F1, d, a, b, c, in[5] + 0x4787c62a, 12); ++ MD5STEP(F1, c, d, a, b, in[6] + 0xa8304613, 17); ++ MD5STEP(F1, b, c, d, a, in[7] + 0xfd469501, 22); ++ MD5STEP(F1, a, b, c, d, in[8] + 0x698098d8, 7); ++ MD5STEP(F1, d, a, b, c, in[9] + 0x8b44f7af, 12); ++ MD5STEP(F1, c, d, a, b, in[10] + 0xffff5bb1, 17); ++ MD5STEP(F1, b, c, d, a, in[11] + 0x895cd7be, 22); ++ MD5STEP(F1, a, b, c, d, in[12] + 0x6b901122, 7); ++ MD5STEP(F1, d, a, b, c, in[13] + 0xfd987193, 12); ++ MD5STEP(F1, c, d, a, b, in[14] + 0xa679438e, 17); ++ MD5STEP(F1, b, c, d, a, in[15] + 0x49b40821, 22); ++ ++ MD5STEP(F2, a, b, c, d, in[1] + 0xf61e2562, 5); ++ MD5STEP(F2, d, a, b, c, in[6] + 0xc040b340, 9); ++ MD5STEP(F2, c, d, a, b, in[11] + 0x265e5a51, 14); ++ MD5STEP(F2, b, c, d, a, in[0] + 0xe9b6c7aa, 20); ++ MD5STEP(F2, a, b, c, d, in[5] + 0xd62f105d, 5); ++ MD5STEP(F2, d, a, b, c, in[10] + 0x02441453, 9); ++ MD5STEP(F2, c, d, a, b, in[15] + 0xd8a1e681, 14); ++ MD5STEP(F2, b, c, d, a, in[4] + 0xe7d3fbc8, 20); ++ MD5STEP(F2, a, b, c, d, in[9] + 0x21e1cde6, 5); ++ MD5STEP(F2, d, a, b, c, in[14] + 0xc33707d6, 9); ++ MD5STEP(F2, c, d, a, b, in[3] + 0xf4d50d87, 14); ++ MD5STEP(F2, b, c, d, a, in[8] + 0x455a14ed, 20); ++ MD5STEP(F2, a, b, c, d, in[13] + 0xa9e3e905, 5); ++ MD5STEP(F2, d, a, b, c, in[2] + 0xfcefa3f8, 9); ++ MD5STEP(F2, c, d, a, b, in[7] + 0x676f02d9, 14); ++ MD5STEP(F2, b, c, d, a, in[12] + 0x8d2a4c8a, 20); ++ ++ MD5STEP(F3, a, b, c, d, in[5] + 0xfffa3942, 4); ++ MD5STEP(F3, d, a, b, c, in[8] + 0x8771f681, 11); ++ MD5STEP(F3, c, d, a, b, in[11] + 0x6d9d6122, 16); ++ MD5STEP(F3, b, c, d, a, in[14] + 0xfde5380c, 23); ++ MD5STEP(F3, a, b, c, d, in[1] + 0xa4beea44, 4); ++ MD5STEP(F3, d, a, b, c, in[4] + 0x4bdecfa9, 11); ++ MD5STEP(F3, c, d, a, b, in[7] + 0xf6bb4b60, 16); ++ MD5STEP(F3, b, c, d, a, in[10] + 0xbebfbc70, 23); ++ MD5STEP(F3, a, b, c, d, in[13] + 0x289b7ec6, 4); ++ MD5STEP(F3, d, a, b, c, in[0] + 0xeaa127fa, 11); ++ MD5STEP(F3, c, d, a, b, in[3] + 0xd4ef3085, 16); ++ MD5STEP(F3, b, c, d, a, in[6] + 0x04881d05, 23); ++ MD5STEP(F3, a, b, c, d, in[9] + 0xd9d4d039, 4); ++ MD5STEP(F3, d, a, b, c, in[12] + 0xe6db99e5, 11); ++ MD5STEP(F3, c, d, a, b, in[15] + 0x1fa27cf8, 16); ++ MD5STEP(F3, b, c, d, a, in[2] + 0xc4ac5665, 23); ++ ++ MD5STEP(F4, a, b, c, d, in[0] + 0xf4292244, 6); ++ MD5STEP(F4, d, a, b, c, in[7] + 0x432aff97, 10); ++ MD5STEP(F4, c, d, a, b, in[14] + 0xab9423a7, 15); ++ MD5STEP(F4, b, c, d, a, in[5] + 0xfc93a039, 21); ++ MD5STEP(F4, a, b, c, d, in[12] + 0x655b59c3, 6); ++ MD5STEP(F4, d, a, b, c, in[3] + 0x8f0ccc92, 10); ++ MD5STEP(F4, c, d, a, b, in[10] + 0xffeff47d, 15); ++ MD5STEP(F4, b, c, d, a, in[1] + 0x85845dd1, 21); ++ MD5STEP(F4, a, b, c, d, in[8] + 0x6fa87e4f, 6); ++ MD5STEP(F4, d, a, b, c, in[15] + 0xfe2ce6e0, 10); ++ MD5STEP(F4, c, d, a, b, in[6] + 0xa3014314, 15); ++ MD5STEP(F4, b, c, d, a, in[13] + 0x4e0811a1, 21); ++ MD5STEP(F4, a, b, c, d, in[4] + 0xf7537e82, 6); ++ MD5STEP(F4, d, a, b, c, in[11] + 0xbd3af235, 10); ++ MD5STEP(F4, c, d, a, b, in[2] + 0x2ad7d2bb, 15); ++ MD5STEP(F4, b, c, d, a, in[9] + 0xeb86d391, 21); ++ ++ buf[0] += a; ++ buf[1] += b; ++ buf[2] += c; ++ buf[3] += d; ++} ++ ++void mvMD5(unsigned char const *buf, unsigned len, unsigned char* digest) ++{ ++ MV_MD5_CONTEXT ctx; ++ ++ mvMD5Init(&ctx); ++ mvMD5Update(&ctx, buf, len); ++ mvMD5Final(digest, &ctx); ++} ++ ++ ++void mvHmacMd5(unsigned char const* text, int text_len, ++ unsigned char const* key, int key_len, ++ unsigned char* digest) ++{ ++ int i; ++ MV_MD5_CONTEXT ctx; ++ unsigned char k_ipad[64+1]; /* inner padding - key XORd with ipad */ ++ unsigned char k_opad[64+1]; /* outer padding - key XORd with opad */ ++ ++ /* start out by storing key in pads */ ++ memset(k_ipad, 0, 64); ++ memcpy(k_ipad, key, key_len); ++ memset(k_opad, 0, 64); ++ memcpy(k_opad, key, key_len); ++ ++ /* XOR key with ipad and opad values */ ++ for (i=0; i<64; i++) ++ { ++ k_ipad[i] ^= 0x36; ++ k_opad[i] ^= 0x5c; ++ } ++ ++ /* perform inner MD5 */ ++ mvMD5Init(&ctx); /* init ctx for 1st pass */ ++ mvMD5Update(&ctx, k_ipad, 64); /* start with inner pad */ ++ mvMD5Update(&ctx, text, text_len); /* then text of datagram */ ++ mvMD5Final(digest, &ctx); /* finish up 1st pass */ ++ ++ /* perform outer MD5 */ ++ mvMD5Init(&ctx); /* init ctx for 2nd pass */ ++ mvMD5Update(&ctx, k_opad, 64); /* start with outer pad */ ++ mvMD5Update(&ctx, digest, 16); /* then results of 1st hash */ ++ mvMD5Final(digest, &ctx); /* finish up 2nd pass */ ++} +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvMD5.h linux-3.0.4/crypto/ocf/kirkwood/cesa/mvMD5.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvMD5.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/cesa/mvMD5.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,93 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __mvMD5_h__ ++#define __mvMD5_h__ ++ ++#include "mvMD5.h" ++ ++#define MV_MD5_MAC_LEN 16 ++ ++ ++typedef struct ++{ ++ MV_U32 buf[4]; ++ MV_U32 bits[2]; ++ MV_U8 in[64]; ++ ++} MV_MD5_CONTEXT; ++ ++void mvMD5Init(MV_MD5_CONTEXT *context); ++void mvMD5Update(MV_MD5_CONTEXT *context, unsigned char const *buf, ++ unsigned len); ++void mvMD5Final(unsigned char digest[16], MV_MD5_CONTEXT *context); ++ ++void mvMD5(unsigned char const *buf, unsigned len, unsigned char* digest); ++ ++void mvHmacMd5(unsigned char const* text, int text_len, ++ unsigned char const* key, int key_len, ++ unsigned char* digest); ++ ++ ++#endif /* __mvMD5_h__ */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvSHA1.c linux-3.0.4/crypto/ocf/kirkwood/cesa/mvSHA1.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvSHA1.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/cesa/mvSHA1.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,239 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#include "mvOs.h" ++#include "mvSHA1.h" ++ ++#define SHA1HANDSOFF ++ ++typedef union ++{ ++ MV_U8 c[64]; ++ MV_U32 l[16]; ++ ++} CHAR64LONG16; ++ ++static void mvSHA1Transform(MV_U32 state[5], const MV_U8 *buffer); ++ ++#define rol(value, bits) (((value) << (bits)) | ((value) >> (32 - (bits)))) ++ ++ ++#ifdef MV_CPU_LE ++#define blk0(i) (block->l[i] = (rol(block->l[i], 24) & 0xFF00FF00) | \ ++ (rol(block->l[i], 8) & 0x00FF00FF)) ++#else ++#define blk0(i) block->l[i] ++#endif ++#define blk(i) (block->l[i & 15] = rol(block->l[(i + 13) & 15] ^ \ ++ block->l[(i + 8) & 15] ^ block->l[(i + 2) & 15] ^ block->l[i & 15], 1)) ++ ++/* (R0+R1), R2, R3, R4 are the different operations used in SHA1 */ ++#define R0(v,w,x,y,z,i) \ ++ z += ((w & (x ^ y)) ^ y) + blk0(i) + 0x5A827999 + rol(v, 5); \ ++ w = rol(w, 30); ++#define R1(v,w,x,y,z,i) \ ++ z += ((w & (x ^ y)) ^ y) + blk(i) + 0x5A827999 + rol(v, 5); \ ++ w = rol(w, 30); ++#define R2(v,w,x,y,z,i) \ ++ z += (w ^ x ^ y) + blk(i) + 0x6ED9EBA1 + rol(v, 5); w = rol(w, 30); ++#define R3(v,w,x,y,z,i) \ ++ z += (((w | x) & y) | (w & x)) + blk(i) + 0x8F1BBCDC + rol(v, 5); \ ++ w = rol(w, 30); ++#define R4(v,w,x,y,z,i) \ ++ z += (w ^ x ^ y) + blk(i) + 0xCA62C1D6 + rol(v, 5); \ ++ w=rol(w, 30); ++ ++/* Hash a single 512-bit block. This is the core of the algorithm. */ ++static void mvSHA1Transform(MV_U32 state[5], const MV_U8 *buffer) ++{ ++ MV_U32 a, b, c, d, e; ++ CHAR64LONG16* block; ++ ++#ifdef SHA1HANDSOFF ++ static MV_U32 workspace[16]; ++ ++ block = (CHAR64LONG16 *) workspace; ++ memcpy(block, buffer, 64); ++#else ++ block = (CHAR64LONG16 *) buffer; ++#endif ++ /* Copy context->state[] to working vars */ ++ a = state[0]; ++ b = state[1]; ++ c = state[2]; ++ d = state[3]; ++ e = state[4]; ++ /* 4 rounds of 20 operations each. Loop unrolled. */ ++ R0(a,b,c,d,e, 0); R0(e,a,b,c,d, 1); R0(d,e,a,b,c, 2); R0(c,d,e,a,b, 3); ++ R0(b,c,d,e,a, 4); R0(a,b,c,d,e, 5); R0(e,a,b,c,d, 6); R0(d,e,a,b,c, 7); ++ R0(c,d,e,a,b, 8); R0(b,c,d,e,a, 9); R0(a,b,c,d,e,10); R0(e,a,b,c,d,11); ++ R0(d,e,a,b,c,12); R0(c,d,e,a,b,13); R0(b,c,d,e,a,14); R0(a,b,c,d,e,15); ++ R1(e,a,b,c,d,16); R1(d,e,a,b,c,17); R1(c,d,e,a,b,18); R1(b,c,d,e,a,19); ++ R2(a,b,c,d,e,20); R2(e,a,b,c,d,21); R2(d,e,a,b,c,22); R2(c,d,e,a,b,23); ++ R2(b,c,d,e,a,24); R2(a,b,c,d,e,25); R2(e,a,b,c,d,26); R2(d,e,a,b,c,27); ++ R2(c,d,e,a,b,28); R2(b,c,d,e,a,29); R2(a,b,c,d,e,30); R2(e,a,b,c,d,31); ++ R2(d,e,a,b,c,32); R2(c,d,e,a,b,33); R2(b,c,d,e,a,34); R2(a,b,c,d,e,35); ++ R2(e,a,b,c,d,36); R2(d,e,a,b,c,37); R2(c,d,e,a,b,38); R2(b,c,d,e,a,39); ++ R3(a,b,c,d,e,40); R3(e,a,b,c,d,41); R3(d,e,a,b,c,42); R3(c,d,e,a,b,43); ++ R3(b,c,d,e,a,44); R3(a,b,c,d,e,45); R3(e,a,b,c,d,46); R3(d,e,a,b,c,47); ++ R3(c,d,e,a,b,48); R3(b,c,d,e,a,49); R3(a,b,c,d,e,50); R3(e,a,b,c,d,51); ++ R3(d,e,a,b,c,52); R3(c,d,e,a,b,53); R3(b,c,d,e,a,54); R3(a,b,c,d,e,55); ++ R3(e,a,b,c,d,56); R3(d,e,a,b,c,57); R3(c,d,e,a,b,58); R3(b,c,d,e,a,59); ++ R4(a,b,c,d,e,60); R4(e,a,b,c,d,61); R4(d,e,a,b,c,62); R4(c,d,e,a,b,63); ++ R4(b,c,d,e,a,64); R4(a,b,c,d,e,65); R4(e,a,b,c,d,66); R4(d,e,a,b,c,67); ++ R4(c,d,e,a,b,68); R4(b,c,d,e,a,69); R4(a,b,c,d,e,70); R4(e,a,b,c,d,71); ++ R4(d,e,a,b,c,72); R4(c,d,e,a,b,73); R4(b,c,d,e,a,74); R4(a,b,c,d,e,75); ++ R4(e,a,b,c,d,76); R4(d,e,a,b,c,77); R4(c,d,e,a,b,78); R4(b,c,d,e,a,79); ++ /* Add the working vars back into context.state[] */ ++ state[0] += a; ++ state[1] += b; ++ state[2] += c; ++ state[3] += d; ++ state[4] += e; ++ /* Wipe variables */ ++ a = b = c = d = e = 0; ++} ++ ++void mvSHA1Init(MV_SHA1_CTX* context) ++{ ++ /* SHA1 initialization constants */ ++ context->state[0] = 0x67452301; ++ context->state[1] = 0xEFCDAB89; ++ context->state[2] = 0x98BADCFE; ++ context->state[3] = 0x10325476; ++ context->state[4] = 0xC3D2E1F0; ++ context->count[0] = context->count[1] = 0; ++} ++ ++ ++/* Run your data through this. */ ++void mvSHA1Update(MV_SHA1_CTX *context, MV_U8 const *data, ++ unsigned int len) ++{ ++ MV_U32 i, j; ++ ++ j = (context->count[0] >> 3) & 63; ++ if ((context->count[0] += len << 3) < (len << 3)) ++ context->count[1]++; ++ context->count[1] += (len >> 29); ++ if ((j + len) > 63) ++ { ++ memcpy(&context->buffer[j], data, (i = 64-j)); ++ mvSHA1Transform(context->state, context->buffer); ++ for ( ; i + 63 < len; i += 64) ++ { ++ mvSHA1Transform(context->state, &data[i]); ++ } ++ j = 0; ++ } ++ else ++ { ++ i = 0; ++ } ++ memcpy(&context->buffer[j], &data[i], len - i); ++} ++ ++void mvSHA1Final(MV_U8* digest, MV_SHA1_CTX* context) ++{ ++ MV_U32 i; ++ MV_U8 finalcount[8]; ++ ++ for (i = 0; i < 8; i++) ++ { ++ finalcount[i] = (unsigned char)((context->count[(i >= 4 ? 0 : 1)] >> ++ ((3-(i & 3)) * 8) ) & 255); /* Endian independent */ ++ } ++ mvSHA1Update(context, (const unsigned char *) "\200", 1); ++ while ((context->count[0] & 504) != 448) ++ { ++ mvSHA1Update(context, (const unsigned char *) "\0", 1); ++ } ++ mvSHA1Update(context, finalcount, 8); /* Should cause a mvSHA1Transform() ++ */ ++ for (i = 0; i < 20; i++) ++ { ++ digest[i] = (unsigned char) ++ ((context->state[i >> 2] >> ((3 - (i & 3)) * 8)) & 255); ++ } ++ /* Wipe variables */ ++ i = 0; ++ memset(context->buffer, 0, 64); ++ memset(context->state, 0, 20); ++ memset(context->count, 0, 8); ++ memset(finalcount, 0, 8); ++ ++#ifdef SHA1HANDSOFF /* make SHA1Transform overwrite it's own static vars */ ++ mvSHA1Transform(context->state, context->buffer); ++#endif ++} ++ ++ ++void mvSHA1(MV_U8 const *buf, unsigned int len, MV_U8* digest) ++{ ++ MV_SHA1_CTX ctx; ++ ++ mvSHA1Init(&ctx); ++ mvSHA1Update(&ctx, buf, len); ++ mvSHA1Final(digest, &ctx); ++} +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvSHA1.h linux-3.0.4/crypto/ocf/kirkwood/cesa/mvSHA1.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa/mvSHA1.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/cesa/mvSHA1.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,88 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __mvSHA1_h__ ++#define __mvSHA1_h__ ++ ++#include "mvSHA1.h" ++ ++#define MV_SHA1_MAC_LEN 20 ++ ++ ++typedef struct ++{ ++ MV_U32 state[5]; ++ MV_U32 count[2]; ++ MV_U8 buffer[64]; ++ ++} MV_SHA1_CTX; ++ ++void mvSHA1Init(MV_SHA1_CTX *context); ++void mvSHA1Update(MV_SHA1_CTX *context, MV_U8 const *buf, unsigned int len); ++void mvSHA1Final(MV_U8* digest, MV_SHA1_CTX *context); ++ ++void mvSHA1(MV_U8 const *buf, unsigned int len, MV_U8* digest); ++ ++ ++#endif /* __mvSHA1_h__ */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/cesa_ocf_drv.c linux-3.0.4/crypto/ocf/kirkwood/cesa_ocf_drv.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/cesa_ocf_drv.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/cesa_ocf_drv.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,1297 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++*******************************************************************************/ ++ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "ctrlEnv/sys/mvSysCesa.h" ++#include "cesa/mvCesa.h" /* moved here before cryptodev.h due to include dependencies */ ++#include ++#include ++#include ++#include ++#include "mvDebug.h" ++ ++#include "cesa/mvMD5.h" ++#include "cesa/mvSHA1.h" ++ ++#include "cesa/mvCesaRegs.h" ++#include "cesa/AES/mvAes.h" ++#include "cesa/mvLru.h" ++ ++#undef RT_DEBUG ++#ifdef RT_DEBUG ++static int debug = 1; ++module_param(debug, int, 1); ++MODULE_PARM_DESC(debug, "Enable debug"); ++#undef dprintk ++#define dprintk(a...) if (debug) { printk(a); } else ++#else ++static int debug = 0; ++#undef dprintk ++#define dprintk(a...) ++#endif ++ ++ ++/* TDMA Regs */ ++#define WINDOW_BASE(i) 0xA00 + (i << 3) ++#define WINDOW_CTRL(i) 0xA04 + (i << 3) ++ ++/* interrupt handling */ ++#undef CESA_OCF_POLLING ++#undef CESA_OCF_TASKLET ++ ++#if defined(CESA_OCF_POLLING) && defined(CESA_OCF_TASKLET) ++#error "don't use both tasklet and polling mode" ++#endif ++ ++extern int cesaReqResources; ++/* support for spliting action into 2 actions */ ++#define CESA_OCF_SPLIT ++ ++/* general defines */ ++#define CESA_OCF_MAX_SES 128 ++#define CESA_Q_SIZE 64 ++ ++ ++/* data structures */ ++struct cesa_ocf_data { ++ int cipher_alg; ++ int auth_alg; ++ int encrypt_tn_auth; ++#define auth_tn_decrypt encrypt_tn_auth ++ int ivlen; ++ int digestlen; ++ short sid_encrypt; ++ short sid_decrypt; ++ /* fragment workaround sessions */ ++ short frag_wa_encrypt; ++ short frag_wa_decrypt; ++ short frag_wa_auth; ++}; ++ ++/* CESA device data */ ++struct cesa_dev { ++ void __iomem *sram; ++ void __iomem *reg; ++ struct mv_cesa_platform_data *plat_data; ++ int irq; ++}; ++ ++#define DIGEST_BUF_SIZE 32 ++struct cesa_ocf_process { ++ MV_CESA_COMMAND cesa_cmd; ++ MV_CESA_MBUF cesa_mbuf; ++ MV_BUF_INFO cesa_bufs[MV_CESA_MAX_MBUF_FRAGS]; ++ char digest[DIGEST_BUF_SIZE]; ++ int digest_len; ++ struct cryptop *crp; ++ int need_cb; ++}; ++ ++/* global variables */ ++static int32_t cesa_ocf_id = -1; ++static struct cesa_ocf_data *cesa_ocf_sessions[CESA_OCF_MAX_SES]; ++static spinlock_t cesa_lock; ++static struct cesa_dev cesa_device; ++ ++/* static APIs */ ++static int cesa_ocf_process (device_t, struct cryptop *, int); ++static int cesa_ocf_newsession (device_t, u_int32_t *, struct cryptoini *); ++static int cesa_ocf_freesession (device_t, u_int64_t); ++static void cesa_callback (unsigned long); ++static irqreturn_t cesa_interrupt_handler (int, void *); ++#ifdef CESA_OCF_POLLING ++static void cesa_interrupt_polling(void); ++#endif ++#ifdef CESA_OCF_TASKLET ++static struct tasklet_struct cesa_ocf_tasklet; ++#endif ++ ++static struct timeval tt_start; ++static struct timeval tt_end; ++ ++/* ++ * dummy device structure ++ */ ++ ++static struct { ++ softc_device_decl sc_dev; ++} mv_cesa_dev; ++ ++static device_method_t mv_cesa_methods = { ++ /* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, cesa_ocf_newsession), ++ DEVMETHOD(cryptodev_freesession,cesa_ocf_freesession), ++ DEVMETHOD(cryptodev_process, cesa_ocf_process), ++ DEVMETHOD(cryptodev_kprocess, NULL), ++}; ++ ++ ++ ++/* Add debug Trace */ ++#undef CESA_OCF_TRACE_DEBUG ++#ifdef CESA_OCF_TRACE_DEBUG ++ ++#define MV_CESA_USE_TIMER_ID 0 ++ ++typedef struct ++{ ++ int type; /* 0 - isrEmpty, 1 - cesaReadyGet, 2 - cesaAction */ ++ MV_U32 timeStamp; ++ MV_U32 cause; ++ MV_U32 realCause; ++ MV_U32 dmaCause; ++ int resources; ++ MV_CESA_REQ* pReqReady; ++ MV_CESA_REQ* pReqEmpty; ++ MV_CESA_REQ* pReqProcess; ++} MV_CESA_TEST_TRACE; ++ ++#define MV_CESA_TEST_TRACE_SIZE 50 ++ ++static int cesaTestTraceIdx = 0; ++static MV_CESA_TEST_TRACE cesaTestTrace[MV_CESA_TEST_TRACE_SIZE]; ++ ++static void cesaTestTraceAdd(int type) ++{ ++ cesaTestTrace[cesaTestTraceIdx].type = type; ++ cesaTestTrace[cesaTestTraceIdx].realCause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); ++ //cesaTestTrace[cesaTestTraceIdx].idmaCause = MV_REG_READ(IDMA_CAUSE_REG); ++ cesaTestTrace[cesaTestTraceIdx].resources = cesaReqResources; ++ cesaTestTrace[cesaTestTraceIdx].pReqReady = pCesaReqReady; ++ cesaTestTrace[cesaTestTraceIdx].pReqEmpty = pCesaReqEmpty; ++ cesaTestTrace[cesaTestTraceIdx].pReqProcess = pCesaReqProcess; ++ cesaTestTrace[cesaTestTraceIdx].timeStamp = mvCntmrRead(MV_CESA_USE_TIMER_ID); ++ cesaTestTraceIdx++; ++ if(cesaTestTraceIdx == MV_CESA_TEST_TRACE_SIZE) ++ cesaTestTraceIdx = 0; ++} ++ ++#else /* CESA_OCF_TRACE_DEBUG */ ++ ++#define cesaTestTraceAdd(x) ++ ++#endif /* CESA_OCF_TRACE_DEBUG */ ++ ++unsigned int ++get_usec(unsigned int start) ++{ ++ if(start) { ++ do_gettimeofday (&tt_start); ++ return 0; ++ } ++ else { ++ do_gettimeofday (&tt_end); ++ tt_end.tv_sec -= tt_start.tv_sec; ++ tt_end.tv_usec -= tt_start.tv_usec; ++ if (tt_end.tv_usec < 0) { ++ tt_end.tv_usec += 1000 * 1000; ++ tt_end.tv_sec -= 1; ++ } ++ } ++ printk("time taken is %d\n", (unsigned int)(tt_end.tv_usec + tt_end.tv_sec * 1000000)); ++ return (tt_end.tv_usec + tt_end.tv_sec * 1000000); ++} ++ ++#ifdef RT_DEBUG ++/* ++ * check that the crp action match the current session ++ */ ++static int ++ocf_check_action(struct cryptop *crp, struct cesa_ocf_data *cesa_ocf_cur_ses) { ++ int count = 0; ++ int encrypt = 0, decrypt = 0, auth = 0; ++ struct cryptodesc *crd; ++ ++ /* Go through crypto descriptors, processing as we go */ ++ for (crd = crp->crp_desc; crd; crd = crd->crd_next, count++) { ++ if(count > 2) { ++ printk("%s,%d: session mode is not supported.\n", __FILE__, __LINE__); ++ return 1; ++ } ++ ++ /* Encryption /Decryption */ ++ if(crd->crd_alg == cesa_ocf_cur_ses->cipher_alg) { ++ /* check that the action is compatible with session */ ++ if(encrypt || decrypt) { ++ printk("%s,%d: session mode is not supported.\n", __FILE__, __LINE__); ++ return 1; ++ } ++ ++ if(crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ ++ if( (count == 2) && (cesa_ocf_cur_ses->encrypt_tn_auth) ) { ++ printk("%s,%d: sequence isn't supported by this session.\n", __FILE__, __LINE__); ++ return 1; ++ } ++ encrypt++; ++ } ++ else { /* decrypt */ ++ if( (count == 2) && !(cesa_ocf_cur_ses->auth_tn_decrypt) ) { ++ printk("%s,%d: sequence isn't supported by this session.\n", __FILE__, __LINE__); ++ return 1; ++ } ++ decrypt++; ++ } ++ ++ } ++ /* Authentication */ ++ else if(crd->crd_alg == cesa_ocf_cur_ses->auth_alg) { ++ /* check that the action is compatible with session */ ++ if(auth) { ++ printk("%s,%d: session mode is not supported.\n", __FILE__, __LINE__); ++ return 1; ++ } ++ if( (count == 2) && (decrypt) && (cesa_ocf_cur_ses->auth_tn_decrypt)) { ++ printk("%s,%d: sequence isn't supported by this session.\n", __FILE__, __LINE__); ++ return 1; ++ } ++ if( (count == 2) && (encrypt) && !(cesa_ocf_cur_ses->encrypt_tn_auth)) { ++ printk("%s,%d: sequence isn't supported by this session.\n", __FILE__, __LINE__); ++ return 1; ++ } ++ auth++; ++ } ++ else { ++ printk("%s,%d: Alg isn't supported by this session.\n", __FILE__, __LINE__); ++ return 1; ++ } ++ } ++ return 0; ++ ++} ++#endif ++ ++/* ++ * Process a request. ++ */ ++static int ++cesa_ocf_process(device_t dev, struct cryptop *crp, int hint) ++{ ++ struct cesa_ocf_process *cesa_ocf_cmd = NULL; ++ struct cesa_ocf_process *cesa_ocf_cmd_wa = NULL; ++ MV_CESA_COMMAND *cesa_cmd; ++ struct cryptodesc *crd; ++ struct cesa_ocf_data *cesa_ocf_cur_ses; ++ int sid = 0, temp_len = 0, i; ++ int encrypt = 0, decrypt = 0, auth = 0; ++ int status; ++ struct sk_buff *skb = NULL; ++ struct uio *uiop = NULL; ++ unsigned char *ivp; ++ MV_BUF_INFO *p_buf_info; ++ MV_CESA_MBUF *p_mbuf_info; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if( cesaReqResources <= 1 ) { ++ dprintk("%s,%d: ERESTART\n", __FILE__, __LINE__); ++ return ERESTART; ++ } ++ ++#ifdef RT_DEBUG ++ /* Sanity check */ ++ if (crp == NULL) { ++ printk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ if (crp->crp_desc == NULL || crp->crp_buf == NULL ) { ++ printk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ crp->crp_etype = EINVAL; ++ return EINVAL; ++ } ++ ++ sid = crp->crp_sid & 0xffffffff; ++ if ((sid >= CESA_OCF_MAX_SES) || (cesa_ocf_sessions[sid] == NULL)) { ++ crp->crp_etype = ENOENT; ++ printk("%s,%d: ENOENT session %d \n", __FILE__, __LINE__, sid); ++ return EINVAL; ++ } ++#endif ++ ++ sid = crp->crp_sid & 0xffffffff; ++ crp->crp_etype = 0; ++ cesa_ocf_cur_ses = cesa_ocf_sessions[sid]; ++ ++#ifdef RT_DEBUG ++ if(ocf_check_action(crp, cesa_ocf_cur_ses)){ ++ goto p_error; ++ } ++#endif ++ ++ /* malloc a new cesa process */ ++ cesa_ocf_cmd = kmalloc(sizeof(struct cesa_ocf_process), GFP_ATOMIC); ++ ++ if (cesa_ocf_cmd == NULL) { ++ printk("%s,%d: ENOBUFS \n", __FILE__, __LINE__); ++ goto p_error; ++ } ++ memset(cesa_ocf_cmd, 0, sizeof(struct cesa_ocf_process)); ++ ++ /* init cesa_process */ ++ cesa_ocf_cmd->crp = crp; ++ /* always call callback */ ++ cesa_ocf_cmd->need_cb = 1; ++ ++ /* init cesa_cmd for usage of the HALs */ ++ cesa_cmd = &cesa_ocf_cmd->cesa_cmd; ++ cesa_cmd->pReqPrv = (void *)cesa_ocf_cmd; ++ cesa_cmd->sessionId = cesa_ocf_cur_ses->sid_encrypt; /* defualt use encrypt */ ++ ++ /* prepare src buffer */ ++ /* we send the entire buffer to the HAL, even if only part of it should be encrypt/auth. */ ++ /* if not using seesions for both encrypt and auth, then it will be wiser to to copy only */ ++ /* from skip to crd_len. */ ++ p_buf_info = cesa_ocf_cmd->cesa_bufs; ++ p_mbuf_info = &cesa_ocf_cmd->cesa_mbuf; ++ ++ p_buf_info += 2; /* save 2 first buffers for IV and digest - ++ we won't append them to the end since, they ++ might be places in an unaligned addresses. */ ++ ++ p_mbuf_info->pFrags = p_buf_info; ++ temp_len = 0; ++ ++ /* handle SKB */ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ ++ dprintk("%s,%d: handle SKB.\n", __FILE__, __LINE__); ++ skb = (struct sk_buff *) crp->crp_buf; ++ ++ if (skb_shinfo(skb)->nr_frags >= (MV_CESA_MAX_MBUF_FRAGS - 1)) { ++ printk("%s,%d: %d nr_frags > MV_CESA_MAX_MBUF_FRAGS", __FILE__, __LINE__, skb_shinfo(skb)->nr_frags); ++ goto p_error; ++ } ++ ++ p_mbuf_info->mbufSize = skb->len; ++ temp_len = skb->len; ++ /* first skb fragment */ ++ p_buf_info->bufSize = skb_headlen(skb); ++ p_buf_info->bufVirtPtr = skb->data; ++ p_buf_info++; ++ ++ /* now handle all other skb fragments */ ++ for ( i = 0; i < skb_shinfo(skb)->nr_frags; i++ ) { ++ skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; ++ p_buf_info->bufSize = frag->size; ++ p_buf_info->bufVirtPtr = page_address(frag->page) + frag->page_offset; ++ p_buf_info++; ++ } ++ p_mbuf_info->numFrags = skb_shinfo(skb)->nr_frags + 1; ++ } ++ /* handle UIO */ ++ else if(crp->crp_flags & CRYPTO_F_IOV) { ++ ++ dprintk("%s,%d: handle UIO.\n", __FILE__, __LINE__); ++ uiop = (struct uio *) crp->crp_buf; ++ ++ if (uiop->uio_iovcnt > (MV_CESA_MAX_MBUF_FRAGS - 1)) { ++ printk("%s,%d: %d uio_iovcnt > MV_CESA_MAX_MBUF_FRAGS \n", __FILE__, __LINE__, uiop->uio_iovcnt); ++ goto p_error; ++ } ++ ++ p_mbuf_info->mbufSize = crp->crp_ilen; ++ p_mbuf_info->numFrags = uiop->uio_iovcnt; ++ for(i = 0; i < uiop->uio_iovcnt; i++) { ++ p_buf_info->bufVirtPtr = uiop->uio_iov[i].iov_base; ++ p_buf_info->bufSize = uiop->uio_iov[i].iov_len; ++ temp_len += p_buf_info->bufSize; ++ dprintk("%s,%d: buf %x-> addr %x, size %x \n" ++ , __FILE__, __LINE__, i, (unsigned int)p_buf_info->bufVirtPtr, p_buf_info->bufSize); ++ p_buf_info++; ++ } ++ ++ } ++ /* handle CONTIG */ ++ else { ++ dprintk("%s,%d: handle CONTIG.\n", __FILE__, __LINE__); ++ p_mbuf_info->numFrags = 1; ++ p_mbuf_info->mbufSize = crp->crp_ilen; ++ p_buf_info->bufVirtPtr = crp->crp_buf; ++ p_buf_info->bufSize = crp->crp_ilen; ++ temp_len = crp->crp_ilen; ++ p_buf_info++; ++ } ++ ++ /* Support up to 64K why? cause! */ ++ if(crp->crp_ilen > 64*1024) { ++ printk("%s,%d: buf too big %x \n", __FILE__, __LINE__, crp->crp_ilen); ++ goto p_error; ++ } ++ ++ if( temp_len != crp->crp_ilen ) { ++ printk("%s,%d: warning size don't match.(%x %x) \n", __FILE__, __LINE__, temp_len, crp->crp_ilen); ++ } ++ ++ cesa_cmd->pSrc = p_mbuf_info; ++ cesa_cmd->pDst = p_mbuf_info; ++ ++ /* restore p_buf_info to point to first available buf */ ++ p_buf_info = cesa_ocf_cmd->cesa_bufs; ++ p_buf_info += 1; ++ ++ ++ /* Go through crypto descriptors, processing as we go */ ++ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { ++ ++ /* Encryption /Decryption */ ++ if(crd->crd_alg == cesa_ocf_cur_ses->cipher_alg) { ++ ++ dprintk("%s,%d: cipher", __FILE__, __LINE__); ++ ++ cesa_cmd->cryptoOffset = crd->crd_skip; ++ cesa_cmd->cryptoLength = crd->crd_len; ++ ++ if(crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ ++ dprintk(" encrypt \n"); ++ encrypt++; ++ ++ /* handle IV */ ++ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { /* IV from USER */ ++ dprintk("%s,%d: IV from USER (offset %x) \n", __FILE__, __LINE__, crd->crd_inject); ++ cesa_cmd->ivFromUser = 1; ++ ivp = crd->crd_iv; ++ ++ /* ++ * do we have to copy the IV back to the buffer ? ++ */ ++ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { ++ dprintk("%s,%d: copy the IV back to the buffer\n", __FILE__, __LINE__); ++ cesa_cmd->ivOffset = crd->crd_inject; ++ crypto_copyback(crp->crp_flags, crp->crp_buf, crd->crd_inject, cesa_ocf_cur_ses->ivlen, ivp); ++ } ++ else { ++ dprintk("%s,%d: don't copy the IV back to the buffer \n", __FILE__, __LINE__); ++ p_mbuf_info->numFrags++; ++ p_mbuf_info->mbufSize += cesa_ocf_cur_ses->ivlen; ++ p_mbuf_info->pFrags = p_buf_info; ++ ++ p_buf_info->bufVirtPtr = ivp; ++ p_buf_info->bufSize = cesa_ocf_cur_ses->ivlen; ++ p_buf_info--; ++ ++ /* offsets */ ++ cesa_cmd->ivOffset = 0; ++ cesa_cmd->cryptoOffset += cesa_ocf_cur_ses->ivlen; ++ if(auth) { ++ cesa_cmd->macOffset += cesa_ocf_cur_ses->ivlen; ++ cesa_cmd->digestOffset += cesa_ocf_cur_ses->ivlen; ++ } ++ } ++ } ++ else { /* random IV */ ++ dprintk("%s,%d: random IV \n", __FILE__, __LINE__); ++ cesa_cmd->ivFromUser = 0; ++ ++ /* ++ * do we have to copy the IV back to the buffer ? ++ */ ++ /* in this mode the HAL will always copy the IV */ ++ /* given by the session to the ivOffset */ ++ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { ++ cesa_cmd->ivOffset = crd->crd_inject; ++ } ++ else { ++ /* if IV isn't copy, then how will the user know which IV did we use??? */ ++ printk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ goto p_error; ++ } ++ } ++ } ++ else { /* decrypt */ ++ dprintk(" decrypt \n"); ++ decrypt++; ++ cesa_cmd->sessionId = cesa_ocf_cur_ses->sid_decrypt; ++ ++ /* handle IV */ ++ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { ++ dprintk("%s,%d: IV from USER \n", __FILE__, __LINE__); ++ /* append the IV buf to the mbuf */ ++ cesa_cmd->ivFromUser = 1; ++ p_mbuf_info->numFrags++; ++ p_mbuf_info->mbufSize += cesa_ocf_cur_ses->ivlen; ++ p_mbuf_info->pFrags = p_buf_info; ++ ++ p_buf_info->bufVirtPtr = crd->crd_iv; ++ p_buf_info->bufSize = cesa_ocf_cur_ses->ivlen; ++ p_buf_info--; ++ ++ /* offsets */ ++ cesa_cmd->ivOffset = 0; ++ cesa_cmd->cryptoOffset += cesa_ocf_cur_ses->ivlen; ++ if(auth) { ++ cesa_cmd->macOffset += cesa_ocf_cur_ses->ivlen; ++ cesa_cmd->digestOffset += cesa_ocf_cur_ses->ivlen; ++ } ++ } ++ else { ++ dprintk("%s,%d: IV inside the buffer \n", __FILE__, __LINE__); ++ cesa_cmd->ivFromUser = 0; ++ cesa_cmd->ivOffset = crd->crd_inject; ++ } ++ } ++ ++ } ++ /* Authentication */ ++ else if(crd->crd_alg == cesa_ocf_cur_ses->auth_alg) { ++ dprintk("%s,%d: Authentication \n", __FILE__, __LINE__); ++ auth++; ++ cesa_cmd->macOffset = crd->crd_skip; ++ cesa_cmd->macLength = crd->crd_len; ++ ++ /* digest + mac */ ++ cesa_cmd->digestOffset = crd->crd_inject; ++ } ++ else { ++ printk("%s,%d: Alg isn't supported by this session.\n", __FILE__, __LINE__); ++ goto p_error; ++ } ++ } ++ ++ dprintk("\n"); ++ dprintk("%s,%d: Sending Action: \n", __FILE__, __LINE__); ++ dprintk("%s,%d: IV from user: %d. IV offset %x \n", __FILE__, __LINE__, cesa_cmd->ivFromUser, cesa_cmd->ivOffset); ++ dprintk("%s,%d: crypt offset %x len %x \n", __FILE__, __LINE__, cesa_cmd->cryptoOffset, cesa_cmd->cryptoLength); ++ dprintk("%s,%d: Auth offset %x len %x \n", __FILE__, __LINE__, cesa_cmd->macOffset, cesa_cmd->macLength); ++ dprintk("%s,%d: set digest in offset %x . \n", __FILE__, __LINE__, cesa_cmd->digestOffset); ++ if(debug) { ++ mvCesaDebugMbuf("SRC BUFFER", cesa_cmd->pSrc, 0, cesa_cmd->pSrc->mbufSize); ++ } ++ ++ ++ /* send action to HAL */ ++ spin_lock_irqsave(&cesa_lock, flags); ++ status = mvCesaAction(cesa_cmd); ++ spin_unlock_irqrestore(&cesa_lock, flags); ++ ++ /* action not allowed */ ++ if(status == MV_NOT_ALLOWED) { ++#ifdef CESA_OCF_SPLIT ++ /* if both encrypt and auth try to split */ ++ if(auth && (encrypt || decrypt)) { ++ MV_CESA_COMMAND *cesa_cmd_wa; ++ ++ /* malloc a new cesa process and init it */ ++ cesa_ocf_cmd_wa = kmalloc(sizeof(struct cesa_ocf_process), GFP_ATOMIC); ++ ++ if (cesa_ocf_cmd_wa == NULL) { ++ printk("%s,%d: ENOBUFS \n", __FILE__, __LINE__); ++ goto p_error; ++ } ++ memcpy(cesa_ocf_cmd_wa, cesa_ocf_cmd, sizeof(struct cesa_ocf_process)); ++ cesa_cmd_wa = &cesa_ocf_cmd_wa->cesa_cmd; ++ cesa_cmd_wa->pReqPrv = (void *)cesa_ocf_cmd_wa; ++ cesa_ocf_cmd_wa->need_cb = 0; ++ ++ /* break requests to two operation, first operation completion won't call callback */ ++ if((decrypt) && (cesa_ocf_cur_ses->auth_tn_decrypt)) { ++ cesa_cmd_wa->sessionId = cesa_ocf_cur_ses->frag_wa_auth; ++ cesa_cmd->sessionId = cesa_ocf_cur_ses->frag_wa_decrypt; ++ } ++ else if((decrypt) && !(cesa_ocf_cur_ses->auth_tn_decrypt)) { ++ cesa_cmd_wa->sessionId = cesa_ocf_cur_ses->frag_wa_decrypt; ++ cesa_cmd->sessionId = cesa_ocf_cur_ses->frag_wa_auth; ++ } ++ else if((encrypt) && (cesa_ocf_cur_ses->encrypt_tn_auth)) { ++ cesa_cmd_wa->sessionId = cesa_ocf_cur_ses->frag_wa_encrypt; ++ cesa_cmd->sessionId = cesa_ocf_cur_ses->frag_wa_auth; ++ } ++ else if((encrypt) && !(cesa_ocf_cur_ses->encrypt_tn_auth)){ ++ cesa_cmd_wa->sessionId = cesa_ocf_cur_ses->frag_wa_auth; ++ cesa_cmd->sessionId = cesa_ocf_cur_ses->frag_wa_encrypt; ++ } ++ else { ++ printk("%s,%d: Unsupporterd fragment wa mode \n", __FILE__, __LINE__); ++ goto p_error; ++ } ++ ++ /* send the 2 actions to the HAL */ ++ spin_lock_irqsave(&cesa_lock, flags); ++ status = mvCesaAction(cesa_cmd_wa); ++ spin_unlock_irqrestore(&cesa_lock, flags); ++ ++ if((status != MV_NO_MORE) && (status != MV_OK)) { ++ printk("%s,%d: cesa action failed, status = 0x%x\n", __FILE__, __LINE__, status); ++ goto p_error; ++ } ++ spin_lock_irqsave(&cesa_lock, flags); ++ status = mvCesaAction(cesa_cmd); ++ spin_unlock_irqrestore(&cesa_lock, flags); ++ ++ } ++ /* action not allowed and can't split */ ++ else ++#endif ++ { ++ goto p_error; ++ } ++ } ++ ++ /* Hal Q is full, send again. This should never happen */ ++ if(status == MV_NO_RESOURCE) { ++ printk("%s,%d: cesa no more resources \n", __FILE__, __LINE__); ++ if(cesa_ocf_cmd) ++ kfree(cesa_ocf_cmd); ++ if(cesa_ocf_cmd_wa) ++ kfree(cesa_ocf_cmd_wa); ++ return ERESTART; ++ } ++ else if((status != MV_NO_MORE) && (status != MV_OK)) { ++ printk("%s,%d: cesa action failed, status = 0x%x\n", __FILE__, __LINE__, status); ++ goto p_error; ++ } ++ ++ ++#ifdef CESA_OCF_POLLING ++ cesa_interrupt_polling(); ++#endif ++ cesaTestTraceAdd(5); ++ ++ return 0; ++p_error: ++ crp->crp_etype = EINVAL; ++ if(cesa_ocf_cmd) ++ kfree(cesa_ocf_cmd); ++ if(cesa_ocf_cmd_wa) ++ kfree(cesa_ocf_cmd_wa); ++ return EINVAL; ++} ++ ++/* ++ * cesa callback. ++ */ ++static void ++cesa_callback(unsigned long dummy) ++{ ++ struct cesa_ocf_process *cesa_ocf_cmd = NULL; ++ struct cryptop *crp = NULL; ++ MV_CESA_RESULT result[MV_CESA_MAX_CHAN]; ++ int res_idx = 0,i; ++ MV_STATUS status; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++#ifdef CESA_OCF_TASKLET ++ disable_irq(cesa_device.irq); ++#endif ++ while(MV_TRUE) { ++ ++ /* Get Ready requests */ ++ spin_lock(&cesa_lock); ++ status = mvCesaReadyGet(&result[res_idx]); ++ spin_unlock(&cesa_lock); ++ ++ cesaTestTraceAdd(2); ++ ++ if(status != MV_OK) { ++#ifdef CESA_OCF_POLLING ++ if(status == MV_BUSY) { /* Fragment */ ++ cesa_interrupt_polling(); ++ return; ++ } ++#endif ++ break; ++ } ++ res_idx++; ++ break; ++ } ++ ++ for(i = 0; i < res_idx; i++) { ++ ++ if(!result[i].pReqPrv) { ++ printk("%s,%d: warning private is NULL\n", __FILE__, __LINE__); ++ break; ++ } ++ ++ cesa_ocf_cmd = result[i].pReqPrv; ++ crp = cesa_ocf_cmd->crp; ++ ++ // ignore HMAC error. ++ //if(result->retCode) ++ // crp->crp_etype = EIO; ++ ++#if defined(CESA_OCF_POLLING) ++ if(!cesa_ocf_cmd->need_cb){ ++ cesa_interrupt_polling(); ++ } ++#endif ++ if(cesa_ocf_cmd->need_cb) { ++ if(debug) { ++ mvCesaDebugMbuf("DST BUFFER", cesa_ocf_cmd->cesa_cmd.pDst, 0, cesa_ocf_cmd->cesa_cmd.pDst->mbufSize); ++ } ++ crypto_done(crp); ++ } ++ kfree(cesa_ocf_cmd); ++ } ++#ifdef CESA_OCF_TASKLET ++ enable_irq(cesa_device.irq); ++#endif ++ ++ cesaTestTraceAdd(3); ++ ++ return; ++} ++ ++#ifdef CESA_OCF_POLLING ++static void ++cesa_interrupt_polling(void) ++{ ++ u32 cause; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ /* Read cause register */ ++ do { ++ cause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); ++ cause &= MV_CESA_CAUSE_ACC_DMA_ALL_MASK; ++ ++ } while (cause == 0); ++ ++ /* clear interrupts */ ++ MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); ++ ++ cesa_callback(0); ++ ++ return; ++} ++ ++#endif ++ ++/* ++ * cesa Interrupt polling routine. ++ */ ++static irqreturn_t ++cesa_interrupt_handler(int irq, void *arg) ++{ ++ u32 cause; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ cesaTestTraceAdd(0); ++ ++ /* Read cause register */ ++ cause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); ++ ++ if( (cause & MV_CESA_CAUSE_ACC_DMA_ALL_MASK) == 0) ++ { ++ /* Empty interrupt */ ++ dprintk("%s,%d: cesaTestReadyIsr: cause=0x%x\n", __FILE__, __LINE__, cause); ++ return IRQ_HANDLED; ++ } ++ ++ /* clear interrupts */ ++ MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); ++ ++ cesaTestTraceAdd(1); ++#ifdef CESA_OCF_TASKLET ++ tasklet_hi_schedule(&cesa_ocf_tasklet); ++#else ++ cesa_callback(0); ++#endif ++ return IRQ_HANDLED; ++} ++ ++/* ++ * Open a session. ++ */ ++static int ++/*cesa_ocf_newsession(void *arg, u_int32_t *sid, struct cryptoini *cri)*/ ++cesa_ocf_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) ++{ ++ u32 status = 0, i; ++ u32 count = 0, auth = 0, encrypt =0; ++ struct cesa_ocf_data *cesa_ocf_cur_ses; ++ MV_CESA_OPEN_SESSION cesa_session; ++ MV_CESA_OPEN_SESSION *cesa_ses = &cesa_session; ++ ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (sid == NULL || cri == NULL) { ++ printk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ /* leave first empty like in other implementations */ ++ for (i = 1; i < CESA_OCF_MAX_SES; i++) { ++ if (cesa_ocf_sessions[i] == NULL) ++ break; ++ } ++ ++ if(i >= CESA_OCF_MAX_SES) { ++ printk("%s,%d: no more sessions \n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ cesa_ocf_sessions[i] = (struct cesa_ocf_data *) kmalloc(sizeof(struct cesa_ocf_data), GFP_ATOMIC); ++ if (cesa_ocf_sessions[i] == NULL) { ++ cesa_ocf_freesession(NULL, i); ++ printk("%s,%d: ENOBUFS \n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ dprintk("%s,%d: new session %d \n", __FILE__, __LINE__, i); ++ ++ *sid = i; ++ cesa_ocf_cur_ses = cesa_ocf_sessions[i]; ++ memset(cesa_ocf_cur_ses, 0, sizeof(struct cesa_ocf_data)); ++ cesa_ocf_cur_ses->sid_encrypt = -1; ++ cesa_ocf_cur_ses->sid_decrypt = -1; ++ cesa_ocf_cur_ses->frag_wa_encrypt = -1; ++ cesa_ocf_cur_ses->frag_wa_decrypt = -1; ++ cesa_ocf_cur_ses->frag_wa_auth = -1; ++ ++ /* init the session */ ++ memset(cesa_ses, 0, sizeof(MV_CESA_OPEN_SESSION)); ++ count = 1; ++ while (cri) { ++ if(count > 2) { ++ printk("%s,%d: don't support more then 2 operations\n", __FILE__, __LINE__); ++ goto error; ++ } ++ switch (cri->cri_alg) { ++ case CRYPTO_AES_CBC: ++ dprintk("%s,%d: (%d) AES CBC \n", __FILE__, __LINE__, count); ++ cesa_ocf_cur_ses->cipher_alg = cri->cri_alg; ++ cesa_ocf_cur_ses->ivlen = MV_CESA_AES_BLOCK_SIZE; ++ cesa_ses->cryptoAlgorithm = MV_CESA_CRYPTO_AES; ++ cesa_ses->cryptoMode = MV_CESA_CRYPTO_CBC; ++ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { ++ printk("%s,%d: CRYPTO key too long.\n", __FILE__, __LINE__); ++ goto error; ++ } ++ memcpy(cesa_ses->cryptoKey, cri->cri_key, cri->cri_klen/8); ++ dprintk("%s,%d: key length %d \n", __FILE__, __LINE__, cri->cri_klen/8); ++ cesa_ses->cryptoKeyLength = cri->cri_klen/8; ++ encrypt += count; ++ break; ++ case CRYPTO_3DES_CBC: ++ dprintk("%s,%d: (%d) 3DES CBC \n", __FILE__, __LINE__, count); ++ cesa_ocf_cur_ses->cipher_alg = cri->cri_alg; ++ cesa_ocf_cur_ses->ivlen = MV_CESA_3DES_BLOCK_SIZE; ++ cesa_ses->cryptoAlgorithm = MV_CESA_CRYPTO_3DES; ++ cesa_ses->cryptoMode = MV_CESA_CRYPTO_CBC; ++ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { ++ printk("%s,%d: CRYPTO key too long.\n", __FILE__, __LINE__); ++ goto error; ++ } ++ memcpy(cesa_ses->cryptoKey, cri->cri_key, cri->cri_klen/8); ++ cesa_ses->cryptoKeyLength = cri->cri_klen/8; ++ encrypt += count; ++ break; ++ case CRYPTO_DES_CBC: ++ dprintk("%s,%d: (%d) DES CBC \n", __FILE__, __LINE__, count); ++ cesa_ocf_cur_ses->cipher_alg = cri->cri_alg; ++ cesa_ocf_cur_ses->ivlen = MV_CESA_DES_BLOCK_SIZE; ++ cesa_ses->cryptoAlgorithm = MV_CESA_CRYPTO_DES; ++ cesa_ses->cryptoMode = MV_CESA_CRYPTO_CBC; ++ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { ++ printk("%s,%d: CRYPTO key too long.\n", __FILE__, __LINE__); ++ goto error; ++ } ++ memcpy(cesa_ses->cryptoKey, cri->cri_key, cri->cri_klen/8); ++ cesa_ses->cryptoKeyLength = cri->cri_klen/8; ++ encrypt += count; ++ break; ++ case CRYPTO_MD5: ++ case CRYPTO_MD5_HMAC: ++ dprintk("%s,%d: (%d) %sMD5 CBC \n", __FILE__, __LINE__, count, (cri->cri_alg != CRYPTO_MD5)? "H-":" "); ++ cesa_ocf_cur_ses->auth_alg = cri->cri_alg; ++ cesa_ocf_cur_ses->digestlen = (cri->cri_alg == CRYPTO_MD5)? MV_CESA_MD5_DIGEST_SIZE : 12; ++ cesa_ses->macMode = (cri->cri_alg == CRYPTO_MD5)? MV_CESA_MAC_MD5 : MV_CESA_MAC_HMAC_MD5; ++ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { ++ printk("%s,%d: MAC key too long. \n", __FILE__, __LINE__); ++ goto error; ++ } ++ cesa_ses->macKeyLength = cri->cri_klen/8; ++ memcpy(cesa_ses->macKey, cri->cri_key, cri->cri_klen/8); ++ cesa_ses->digestSize = cesa_ocf_cur_ses->digestlen; ++ auth += count; ++ break; ++ case CRYPTO_SHA1: ++ case CRYPTO_SHA1_HMAC: ++ dprintk("%s,%d: (%d) %sSHA1 CBC \n", __FILE__, __LINE__, count, (cri->cri_alg != CRYPTO_SHA1)? "H-":" "); ++ cesa_ocf_cur_ses->auth_alg = cri->cri_alg; ++ cesa_ocf_cur_ses->digestlen = (cri->cri_alg == CRYPTO_SHA1)? MV_CESA_SHA1_DIGEST_SIZE : 12; ++ cesa_ses->macMode = (cri->cri_alg == CRYPTO_SHA1)? MV_CESA_MAC_SHA1 : MV_CESA_MAC_HMAC_SHA1; ++ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { ++ printk("%s,%d: MAC key too long. \n", __FILE__, __LINE__); ++ goto error; ++ } ++ cesa_ses->macKeyLength = cri->cri_klen/8; ++ memcpy(cesa_ses->macKey, cri->cri_key, cri->cri_klen/8); ++ cesa_ses->digestSize = cesa_ocf_cur_ses->digestlen; ++ auth += count; ++ break; ++ default: ++ printk("%s,%d: unknown algo 0x%x\n", __FILE__, __LINE__, cri->cri_alg); ++ goto error; ++ } ++ cri = cri->cri_next; ++ count++; ++ } ++ ++ if((encrypt > 2) || (auth > 2)) { ++ printk("%s,%d: session mode is not supported.\n", __FILE__, __LINE__); ++ goto error; ++ } ++ /* create new sessions in HAL */ ++ if(encrypt) { ++ cesa_ses->operation = MV_CESA_CRYPTO_ONLY; ++ /* encrypt session */ ++ if(auth == 1) { ++ cesa_ses->operation = MV_CESA_MAC_THEN_CRYPTO; ++ } ++ else if(auth == 2) { ++ cesa_ses->operation = MV_CESA_CRYPTO_THEN_MAC; ++ cesa_ocf_cur_ses->encrypt_tn_auth = 1; ++ } ++ else { ++ cesa_ses->operation = MV_CESA_CRYPTO_ONLY; ++ } ++ cesa_ses->direction = MV_CESA_DIR_ENCODE; ++ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->sid_encrypt); ++ if(status != MV_OK) { ++ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); ++ goto error; ++ } ++ /* decrypt session */ ++ if( cesa_ses->operation == MV_CESA_MAC_THEN_CRYPTO ) { ++ cesa_ses->operation = MV_CESA_CRYPTO_THEN_MAC; ++ } ++ else if( cesa_ses->operation == MV_CESA_CRYPTO_THEN_MAC ) { ++ cesa_ses->operation = MV_CESA_MAC_THEN_CRYPTO; ++ } ++ cesa_ses->direction = MV_CESA_DIR_DECODE; ++ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->sid_decrypt); ++ if(status != MV_OK) { ++ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); ++ goto error; ++ } ++ ++ /* preapre one action sessions for case we will need to split an action */ ++#ifdef CESA_OCF_SPLIT ++ if(( cesa_ses->operation == MV_CESA_MAC_THEN_CRYPTO ) || ++ ( cesa_ses->operation == MV_CESA_CRYPTO_THEN_MAC )) { ++ /* open one session for encode and one for decode */ ++ cesa_ses->operation = MV_CESA_CRYPTO_ONLY; ++ cesa_ses->direction = MV_CESA_DIR_ENCODE; ++ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->frag_wa_encrypt); ++ if(status != MV_OK) { ++ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); ++ goto error; ++ } ++ ++ cesa_ses->direction = MV_CESA_DIR_DECODE; ++ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->frag_wa_decrypt); ++ if(status != MV_OK) { ++ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); ++ goto error; ++ } ++ /* open one session for auth */ ++ cesa_ses->operation = MV_CESA_MAC_ONLY; ++ cesa_ses->direction = MV_CESA_DIR_ENCODE; ++ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->frag_wa_auth); ++ if(status != MV_OK) { ++ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); ++ goto error; ++ } ++ } ++#endif ++ } ++ else { /* only auth */ ++ cesa_ses->operation = MV_CESA_MAC_ONLY; ++ cesa_ses->direction = MV_CESA_DIR_ENCODE; ++ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->sid_encrypt); ++ if(status != MV_OK) { ++ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); ++ goto error; ++ } ++ } ++ ++ return 0; ++error: ++ cesa_ocf_freesession(NULL, *sid); ++ return EINVAL; ++ ++} ++ ++ ++/* ++ * Free a session. ++ */ ++static int ++cesa_ocf_freesession(device_t dev, u_int64_t tid) ++{ ++ struct cesa_ocf_data *cesa_ocf_cur_ses; ++ u_int32_t sid = CRYPTO_SESID2LID(tid); ++ //unsigned long flags; ++ ++ dprintk("%s() %d \n", __FUNCTION__, sid); ++ if ( (sid >= CESA_OCF_MAX_SES) || (cesa_ocf_sessions[sid] == NULL) ) { ++ printk("%s,%d: EINVAL can't free session %d \n", __FILE__, __LINE__, sid); ++ return(EINVAL); ++ } ++ ++ /* Silently accept and return */ ++ if (sid == 0) ++ return(0); ++ ++ /* release session from HAL */ ++ cesa_ocf_cur_ses = cesa_ocf_sessions[sid]; ++ if (cesa_ocf_cur_ses->sid_encrypt != -1) { ++ mvCesaSessionClose(cesa_ocf_cur_ses->sid_encrypt); ++ } ++ if (cesa_ocf_cur_ses->sid_decrypt != -1) { ++ mvCesaSessionClose(cesa_ocf_cur_ses->sid_decrypt); ++ } ++ if (cesa_ocf_cur_ses->frag_wa_encrypt != -1) { ++ mvCesaSessionClose(cesa_ocf_cur_ses->frag_wa_encrypt); ++ } ++ if (cesa_ocf_cur_ses->frag_wa_decrypt != -1) { ++ mvCesaSessionClose(cesa_ocf_cur_ses->frag_wa_decrypt); ++ } ++ if (cesa_ocf_cur_ses->frag_wa_auth != -1) { ++ mvCesaSessionClose(cesa_ocf_cur_ses->frag_wa_auth); ++ } ++ ++ kfree(cesa_ocf_cur_ses); ++ cesa_ocf_sessions[sid] = NULL; ++ ++ return 0; ++} ++ ++ ++/* TDMA Window setup */ ++ ++static void __init ++setup_tdma_mbus_windows(struct cesa_dev *dev) ++{ ++ int i; ++ ++ for (i = 0; i < 4; i++) { ++ writel(0, dev->reg + WINDOW_BASE(i)); ++ writel(0, dev->reg + WINDOW_CTRL(i)); ++ } ++ ++ for (i = 0; i < dev->plat_data->dram->num_cs; i++) { ++ struct mbus_dram_window *cs = dev->plat_data->dram->cs + i; ++ writel( ++ ((cs->size - 1) & 0xffff0000) | ++ (cs->mbus_attr << 8) | ++ (dev->plat_data->dram->mbus_dram_target_id << 4) | 1, ++ dev->reg + WINDOW_CTRL(i) ++ ); ++ writel(cs->base, dev->reg + WINDOW_BASE(i)); ++ } ++} ++ ++/* ++ * our driver startup and shutdown routines ++ */ ++static int ++mv_cesa_ocf_init(struct platform_device *pdev) ++{ ++#if defined(CONFIG_MV78200) || defined(CONFIG_MV632X) ++ if (MV_FALSE == mvSocUnitIsMappedToThisCpu(CESA)) ++ { ++ dprintk("CESA is not mapped to this CPU\n"); ++ return -ENODEV; ++ } ++#endif ++ ++ dprintk("%s\n", __FUNCTION__); ++ memset(&mv_cesa_dev, 0, sizeof(mv_cesa_dev)); ++ softc_device_init(&mv_cesa_dev, "MV CESA", 0, mv_cesa_methods); ++ cesa_ocf_id = crypto_get_driverid(softc_get_device(&mv_cesa_dev),CRYPTOCAP_F_HARDWARE); ++ ++ if (cesa_ocf_id < 0) ++ panic("MV CESA crypto device cannot initialize!"); ++ ++ dprintk("%s,%d: cesa ocf device id is %d \n", __FILE__, __LINE__, cesa_ocf_id); ++ ++ /* CESA unit is auto power on off */ ++#if 0 ++ if (MV_FALSE == mvCtrlPwrClckGet(CESA_UNIT_ID,0)) ++ { ++ printk("\nWarning CESA %d is Powered Off\n",0); ++ return EINVAL; ++ } ++#endif ++ ++ memset(&cesa_device, 0, sizeof(struct cesa_dev)); ++ /* Get the IRQ, and crypto memory regions */ ++ { ++ struct resource *res; ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram"); ++ ++ if (!res) ++ return -ENXIO; ++ ++ cesa_device.sram = ioremap(res->start, res->end - res->start + 1); ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); ++ ++ if (!res) { ++ iounmap(cesa_device.sram); ++ return -ENXIO; ++ } ++ cesa_device.reg = ioremap(res->start, res->end - res->start + 1); ++ cesa_device.irq = platform_get_irq(pdev, 0); ++ cesa_device.plat_data = pdev->dev.platform_data; ++ setup_tdma_mbus_windows(&cesa_device); ++ ++ } ++ ++ ++ if( MV_OK != mvCesaInit(CESA_OCF_MAX_SES*5, CESA_Q_SIZE, cesa_device.reg, ++ NULL) ) { ++ printk("%s,%d: mvCesaInit Failed. \n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ /* clear and unmask Int */ ++ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); ++#ifndef CESA_OCF_POLLING ++ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, MV_CESA_CAUSE_ACC_DMA_MASK); ++#endif ++#ifdef CESA_OCF_TASKLET ++ tasklet_init(&cesa_ocf_tasklet, cesa_callback, (unsigned int) 0); ++#endif ++ /* register interrupt */ ++ if( request_irq( cesa_device.irq, cesa_interrupt_handler, ++ (IRQF_DISABLED) , "cesa", &cesa_ocf_id) < 0) { ++ printk("%s,%d: cannot assign irq %x\n", __FILE__, __LINE__, cesa_device.reg); ++ return EINVAL; ++ } ++ ++ ++ memset(cesa_ocf_sessions, 0, sizeof(struct cesa_ocf_data *) * CESA_OCF_MAX_SES); ++ ++#define REGISTER(alg) \ ++ crypto_register(cesa_ocf_id, alg, 0,0) ++ REGISTER(CRYPTO_AES_CBC); ++ REGISTER(CRYPTO_DES_CBC); ++ REGISTER(CRYPTO_3DES_CBC); ++ REGISTER(CRYPTO_MD5); ++ REGISTER(CRYPTO_MD5_HMAC); ++ REGISTER(CRYPTO_SHA1); ++ REGISTER(CRYPTO_SHA1_HMAC); ++#undef REGISTER ++ ++ return 0; ++} ++ ++static void ++mv_cesa_ocf_exit(struct platform_device *pdev) ++{ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ crypto_unregister_all(cesa_ocf_id); ++ cesa_ocf_id = -1; ++ iounmap(cesa_device.reg); ++ iounmap(cesa_device.sram); ++ free_irq(cesa_device.irq, NULL); ++ ++ /* mask and clear Int */ ++ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, 0); ++ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); ++ ++ ++ if( MV_OK != mvCesaFinish() ) { ++ printk("%s,%d: mvCesaFinish Failed. \n", __FILE__, __LINE__); ++ return; ++ } ++} ++ ++ ++void cesa_ocf_debug(void) ++{ ++ ++#ifdef CESA_OCF_TRACE_DEBUG ++ { ++ int i, j; ++ j = cesaTestTraceIdx; ++ mvOsPrintf("No Type rCause iCause Proc Isr Res Time pReady pProc pEmpty\n"); ++ for(i=0; i= _1G) ++ { ++ mvOsOutput("%3dGB ", size / _1G); ++ size %= _1G; ++ if(size) ++ mvOsOutput("+"); ++ } ++ if(size >= _1M ) ++ { ++ mvOsOutput("%3dMB ", size / _1M); ++ size %= _1M; ++ if(size) ++ mvOsOutput("+"); ++ } ++ if(size >= _1K) ++ { ++ mvOsOutput("%3dKB ", size / _1K); ++ size %= _1K; ++ if(size) ++ mvOsOutput("+"); ++ } ++ if(size > 0) ++ { ++ mvOsOutput("%3dB ", size); ++ } ++} ++ ++/******************************************************************************* ++* mvHexToBin - Convert hex to binary ++* ++* DESCRIPTION: ++* This function Convert hex to binary. ++* ++* INPUT: ++* pHexStr - hex buffer pointer. ++* size - Size to convert. ++* ++* OUTPUT: ++* pBin - Binary buffer pointer. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvHexToBin(const char* pHexStr, MV_U8* pBin, int size) ++{ ++ int j, i; ++ char tmp[3]; ++ MV_U8 byte; ++ ++ for(j=0, i=0; j> 1; ++ result++; ++ } ++ return result; ++} ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvCommon.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvCommon.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvCommon.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvCommon.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,308 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++ ++#ifndef __INCmvCommonh ++#define __INCmvCommonh ++ ++#include "mvTypes.h" ++ ++/* Swap tool */ ++ ++/* 16bit nibble swap. For example 0x1234 -> 0x2143 */ ++#define MV_NIBBLE_SWAP_16BIT(X) (((X&0xf) << 4) | \ ++ ((X&0xf0) >> 4) | \ ++ ((X&0xf00) << 4) | \ ++ ((X&0xf000) >> 4)) ++ ++/* 32bit nibble swap. For example 0x12345678 -> 0x21436587 */ ++#define MV_NIBBLE_SWAP_32BIT(X) (((X&0xf) << 4) | \ ++ ((X&0xf0) >> 4) | \ ++ ((X&0xf00) << 4) | \ ++ ((X&0xf000) >> 4) | \ ++ ((X&0xf0000) << 4) | \ ++ ((X&0xf00000) >> 4) | \ ++ ((X&0xf000000) << 4) | \ ++ ((X&0xf0000000) >> 4)) ++ ++/* 16bit byte swap. For example 0x1122 -> 0x2211 */ ++#define MV_BYTE_SWAP_16BIT(X) ((((X)&0xff)<<8) | (((X)&0xff00)>>8)) ++ ++/* 32bit byte swap. For example 0x11223344 -> 0x44332211 */ ++#define MV_BYTE_SWAP_32BIT(X) ((((X)&0xff)<<24) | \ ++ (((X)&0xff00)<<8) | \ ++ (((X)&0xff0000)>>8) | \ ++ (((X)&0xff000000)>>24)) ++ ++/* 64bit byte swap. For example 0x11223344.55667788 -> 0x88776655.44332211 */ ++#define MV_BYTE_SWAP_64BIT(X) ((l64) ((((X)&0xffULL)<<56) | \ ++ (((X)&0xff00ULL)<<40) | \ ++ (((X)&0xff0000ULL)<<24) | \ ++ (((X)&0xff000000ULL)<<8) | \ ++ (((X)&0xff00000000ULL)>>8) | \ ++ (((X)&0xff0000000000ULL)>>24) | \ ++ (((X)&0xff000000000000ULL)>>40) | \ ++ (((X)&0xff00000000000000ULL)>>56))) ++ ++/* Endianess macros. */ ++#if defined(MV_CPU_LE) ++ #define MV_16BIT_LE(X) (X) ++ #define MV_32BIT_LE(X) (X) ++ #define MV_64BIT_LE(X) (X) ++ #define MV_16BIT_BE(X) MV_BYTE_SWAP_16BIT(X) ++ #define MV_32BIT_BE(X) MV_BYTE_SWAP_32BIT(X) ++ #define MV_64BIT_BE(X) MV_BYTE_SWAP_64BIT(X) ++#elif defined(MV_CPU_BE) ++ #define MV_16BIT_LE(X) MV_BYTE_SWAP_16BIT(X) ++ #define MV_32BIT_LE(X) MV_BYTE_SWAP_32BIT(X) ++ #define MV_64BIT_LE(X) MV_BYTE_SWAP_64BIT(X) ++ #define MV_16BIT_BE(X) (X) ++ #define MV_32BIT_BE(X) (X) ++ #define MV_64BIT_BE(X) (X) ++#else ++ #error "CPU endianess isn't defined!\n" ++#endif ++ ++ ++/* Bit field definitions */ ++#define NO_BIT 0x00000000 ++#define BIT0 0x00000001 ++#define BIT1 0x00000002 ++#define BIT2 0x00000004 ++#define BIT3 0x00000008 ++#define BIT4 0x00000010 ++#define BIT5 0x00000020 ++#define BIT6 0x00000040 ++#define BIT7 0x00000080 ++#define BIT8 0x00000100 ++#define BIT9 0x00000200 ++#define BIT10 0x00000400 ++#define BIT11 0x00000800 ++#define BIT12 0x00001000 ++#define BIT13 0x00002000 ++#define BIT14 0x00004000 ++#define BIT15 0x00008000 ++#define BIT16 0x00010000 ++#define BIT17 0x00020000 ++#define BIT18 0x00040000 ++#define BIT19 0x00080000 ++#define BIT20 0x00100000 ++#define BIT21 0x00200000 ++#define BIT22 0x00400000 ++#define BIT23 0x00800000 ++#define BIT24 0x01000000 ++#define BIT25 0x02000000 ++#define BIT26 0x04000000 ++#define BIT27 0x08000000 ++#define BIT28 0x10000000 ++#define BIT29 0x20000000 ++#define BIT30 0x40000000 ++#define BIT31 0x80000000 ++ ++/* Handy sizes */ ++#define _1K 0x00000400 ++#define _2K 0x00000800 ++#define _4K 0x00001000 ++#define _8K 0x00002000 ++#define _16K 0x00004000 ++#define _32K 0x00008000 ++#define _64K 0x00010000 ++#define _128K 0x00020000 ++#define _256K 0x00040000 ++#define _512K 0x00080000 ++ ++#define _1M 0x00100000 ++#define _2M 0x00200000 ++#define _4M 0x00400000 ++#define _8M 0x00800000 ++#define _16M 0x01000000 ++#define _32M 0x02000000 ++#define _64M 0x04000000 ++#define _128M 0x08000000 ++#define _256M 0x10000000 ++#define _512M 0x20000000 ++ ++#define _1G 0x40000000 ++#define _2G 0x80000000 ++ ++/* Tclock and Sys clock define */ ++#define _100MHz 100000000 ++#define _125MHz 125000000 ++#define _133MHz 133333334 ++#define _150MHz 150000000 ++#define _160MHz 160000000 ++#define _166MHz 166666667 ++#define _175MHz 175000000 ++#define _178MHz 178000000 ++#define _183MHz 183333334 ++#define _187MHz 187000000 ++#define _192MHz 192000000 ++#define _194MHz 194000000 ++#define _200MHz 200000000 ++#define _233MHz 233333334 ++#define _250MHz 250000000 ++#define _266MHz 266666667 ++#define _300MHz 300000000 ++ ++/* For better address window table readability */ ++#define EN MV_TRUE ++#define DIS MV_FALSE ++#define N_A -1 /* Not applicable */ ++ ++/* Cache configuration options for memory (DRAM, SRAM, ... ) */ ++ ++/* Memory uncached, HW or SW cache coherency is not needed */ ++#define MV_UNCACHED 0 ++/* Memory cached, HW cache coherency supported in WriteThrough mode */ ++#define MV_CACHE_COHER_HW_WT 1 ++/* Memory cached, HW cache coherency supported in WriteBack mode */ ++#define MV_CACHE_COHER_HW_WB 2 ++/* Memory cached, No HW cache coherency, Cache coherency must be in SW */ ++#define MV_CACHE_COHER_SW 3 ++ ++ ++/* Macro for testing aligment. Positive if number is NOT aligned */ ++#define MV_IS_NOT_ALIGN(number, align) ((number) & ((align) - 1)) ++ ++/* Macro for alignment up. For example, MV_ALIGN_UP(0x0330, 0x20) = 0x0340 */ ++#define MV_ALIGN_UP(number, align) \ ++(((number) & ((align) - 1)) ? (((number) + (align)) & ~((align)-1)) : (number)) ++ ++/* Macro for alignment down. For example, MV_ALIGN_UP(0x0330, 0x20) = 0x0320 */ ++#define MV_ALIGN_DOWN(number, align) ((number) & ~((align)-1)) ++ ++/* This macro returns absolute value */ ++#define MV_ABS(number) (((int)(number) < 0) ? -(int)(number) : (int)(number)) ++ ++ ++/* Bit fields manipulation macros */ ++ ++/* An integer word which its 'x' bit is set */ ++#define MV_BIT_MASK(bitNum) (1 << (bitNum) ) ++ ++/* Checks wheter bit 'x' in integer word is set */ ++#define MV_BIT_CHECK(word, bitNum) ( (word) & MV_BIT_MASK(bitNum) ) ++ ++/* Clear (reset) bit 'x' in integer word (RMW - Read-Modify-Write) */ ++#define MV_BIT_CLEAR(word, bitNum) ( (word) &= ~(MV_BIT_MASK(bitNum)) ) ++ ++/* Set bit 'x' in integer word (RMW) */ ++#define MV_BIT_SET(word, bitNum) ( (word) |= MV_BIT_MASK(bitNum) ) ++ ++/* Invert bit 'x' in integer word (RMW) */ ++#define MV_BIT_INV(word, bitNum) ( (word) ^= MV_BIT_MASK(bitNum) ) ++ ++/* Get the min between 'a' or 'b' */ ++#define MV_MIN(a,b) (((a) < (b)) ? (a) : (b)) ++ ++/* Get the max between 'a' or 'b' */ ++#define MV_MAX(a,b) (((a) < (b)) ? (b) : (a)) ++ ++/* Temporary */ ++#define mvOsDivide(num, div) \ ++({ \ ++ int i=0, rem=(num); \ ++ \ ++ while(rem >= (div)) \ ++ { \ ++ rem -= (div); \ ++ i++; \ ++ } \ ++ (i); \ ++}) ++ ++/* Temporary */ ++#define mvOsReminder(num, div) \ ++({ \ ++ int rem = (num); \ ++ \ ++ while(rem >= (div)) \ ++ rem -= (div); \ ++ (rem); \ ++}) ++ ++#define MV_IP_QUAD(ipAddr) ((ipAddr >> 24) & 0xFF), ((ipAddr >> 16) & 0xFF), \ ++ ((ipAddr >> 8) & 0xFF), ((ipAddr >> 0) & 0xFF) ++ ++#define MV_IS_POWER_OF_2(num) ((num != 0) && ((num & (num - 1)) == 0)) ++ ++#ifndef MV_ASMLANGUAGE ++/* mvCommon API list */ ++ ++MV_VOID mvHexToBin(const char* pHexStr, MV_U8* pBin, int size); ++void mvAsciiToHex(const char* asciiStr, char* hexStr); ++void mvBinToHex(const MV_U8* bin, char* hexStr, int size); ++void mvBinToAscii(const MV_U8* bin, char* asciiStr, int size); ++ ++MV_STATUS mvMacStrToHex(const char* macStr, MV_U8* macHex); ++MV_STATUS mvMacHexToStr(MV_U8* macHex, char* macStr); ++void mvSizePrint(MV_U32); ++ ++MV_U32 mvLog2(MV_U32 num); ++ ++#endif /* MV_ASMLANGUAGE */ ++ ++ ++#endif /* __INCmvCommonh */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvCompVer.txt linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvCompVer.txt +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvCompVer.txt 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvCompVer.txt 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,4 @@ ++Global HAL Version: FEROCEON_HAL_3_1_7 ++Unit HAL Version: 3.1.4 ++Description: This component includes an implementation of the unit HAL drivers ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvDebug.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvDebug.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvDebug.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvDebug.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,326 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++ ++/* includes */ ++#include "mvOs.h" ++#include "mv802_3.h" ++#include "mvCommon.h" ++#include "mvDebug.h" ++ ++/* Global variables effect on behave MV_DEBUG_PRINT and MV_DEBUG_CODE macros ++ * mvDebug - map of bits (one for each module) bit=1 means enable ++ * debug code and messages for this module ++ * mvModuleDebug - array of 32 bits varables one for each module ++ */ ++MV_U32 mvDebug = 0; ++MV_U32 mvDebugModules[MV_MODULE_MAX]; ++ ++/* Init mvModuleDebug array to default values */ ++void mvDebugInit(void) ++{ ++ int bit; ++ ++ mvDebug = 0; ++ for(bit=0; bit 0) ++ { ++ mvOsPrintf("%08x: ", memAddr); ++ i = 0; ++ /* 32 bytes in the line */ ++ while(i < 32) ++ { ++ if(memAddr >= (MV_U32)addr) ++ { ++ switch(access) ++ { ++ case 1: ++ if( memAddr == CPU_PHY_MEM(memAddr) ) ++ { ++ mvOsPrintf("%02x ", MV_MEMIO8_READ(memAddr)); ++ } ++ else ++ { ++ mvOsPrintf("%02x ", *((MV_U8*)memAddr)); ++ } ++ break; ++ ++ case 2: ++ if( memAddr == CPU_PHY_MEM(memAddr) ) ++ { ++ mvOsPrintf("%04x ", MV_MEMIO16_READ(memAddr)); ++ } ++ else ++ { ++ mvOsPrintf("%04x ", *((MV_U16*)memAddr)); ++ } ++ break; ++ ++ case 4: ++ if( memAddr == CPU_PHY_MEM(memAddr) ) ++ { ++ mvOsPrintf("%08x ", MV_MEMIO32_READ(memAddr)); ++ } ++ else ++ { ++ mvOsPrintf("%08x ", *((MV_U32*)memAddr)); ++ } ++ break; ++ } ++ } ++ else ++ { ++ for(j=0; j<(access*2+1); j++) ++ mvOsPrintf(" "); ++ } ++ i += access; ++ memAddr += access; ++ size -= access; ++ if(size <= 0) ++ break; ++ } ++ mvOsPrintf("\n"); ++ } ++} ++ ++void mvDebugPrintBufInfo(BUF_INFO* pBufInfo, int size, int access) ++{ ++ if(pBufInfo == NULL) ++ { ++ mvOsPrintf("\n!!! pBufInfo = NULL\n"); ++ return; ++ } ++ mvOsPrintf("\n*** pBufInfo=0x%x, cmdSts=0x%08x, pBuf=0x%x, bufSize=%d\n", ++ (unsigned int)pBufInfo, ++ (unsigned int)pBufInfo->cmdSts, ++ (unsigned int)pBufInfo->pBuff, ++ (unsigned int)pBufInfo->bufSize); ++ mvOsPrintf("pData=0x%x, byteCnt=%d, pNext=0x%x, uInfo1=0x%x, uInfo2=0x%x\n", ++ (unsigned int)pBufInfo->pData, ++ (unsigned int)pBufInfo->byteCnt, ++ (unsigned int)pBufInfo->pNextBufInfo, ++ (unsigned int)pBufInfo->userInfo1, ++ (unsigned int)pBufInfo->userInfo2); ++ if(pBufInfo->pData != NULL) ++ { ++ if(size > pBufInfo->byteCnt) ++ size = pBufInfo->byteCnt; ++ mvDebugMemDump(pBufInfo->pData, size, access); ++ } ++} ++ ++void mvDebugPrintPktInfo(MV_PKT_INFO* pPktInfo, int size, int access) ++{ ++ int frag, len; ++ ++ if(pPktInfo == NULL) ++ { ++ mvOsPrintf("\n!!! pPktInfo = NULL\n"); ++ return; ++ } ++ mvOsPrintf("\npPkt=%p, stat=0x%08x, numFr=%d, size=%d, pFr=%p, osInfo=0x%lx\n", ++ pPktInfo, pPktInfo->status, pPktInfo->numFrags, pPktInfo->pktSize, ++ pPktInfo->pFrags, pPktInfo->osInfo); ++ ++ for(frag=0; fragnumFrags; frag++) ++ { ++ mvOsPrintf("#%2d. bufVirt=%p, bufSize=%d\n", ++ frag, pPktInfo->pFrags[frag].bufVirtPtr, ++ pPktInfo->pFrags[frag].bufSize); ++ if(size > 0) ++ { ++ len = MV_MIN((int)pPktInfo->pFrags[frag].bufSize, size); ++ mvDebugMemDump(pPktInfo->pFrags[frag].bufVirtPtr, len, access); ++ size -= len; ++ } ++ } ++ ++} ++ ++void mvDebugPrintIpAddr(MV_U32 ipAddr) ++{ ++ mvOsPrintf("%d.%d.%d.%d", ((ipAddr >> 24) & 0xFF), ((ipAddr >> 16) & 0xFF), ++ ((ipAddr >> 8) & 0xFF), ((ipAddr >> 0) & 0xFF)); ++} ++ ++void mvDebugPrintMacAddr(const MV_U8* pMacAddr) ++{ ++ int i; ++ ++ mvOsPrintf("%02x", (unsigned int)pMacAddr[0]); ++ for(i=1; ibegin = 0; ++ pTimeEntry->count = count; ++ pTimeEntry->end = 0; ++ pTimeEntry->left = pTimeEntry->count; ++ pTimeEntry->total = 0; ++ pTimeEntry->min = 0xFFFFFFFF; ++ pTimeEntry->max = 0x0; ++ strncpy(pTimeEntry->name, pName, sizeof(pTimeEntry->name)-1); ++ pTimeEntry->name[sizeof(pTimeEntry->name)-1] = '\0'; ++} ++ ++/* Print out MV_DEBUG_TIMES entry */ ++void mvDebugPrintTimeEntry(MV_DEBUG_TIMES* pTimeEntry, MV_BOOL isTitle) ++{ ++ int num; ++ ++ if(isTitle == MV_TRUE) ++ mvOsPrintf("Event NumOfEvents TotalTime Average Min Max\n"); ++ ++ num = pTimeEntry->count-pTimeEntry->left; ++ if(num > 0) ++ { ++ mvOsPrintf("%-11s %6u 0x%08lx %6lu %6lu %6lu\n", ++ pTimeEntry->name, num, pTimeEntry->total, pTimeEntry->total/num, ++ pTimeEntry->min, pTimeEntry->max); ++ } ++} ++ ++/* Update MV_DEBUG_TIMES entry */ ++void mvDebugUpdateTimeEntry(MV_DEBUG_TIMES* pTimeEntry) ++{ ++ MV_U32 delta; ++ ++ if(pTimeEntry->left > 0) ++ { ++ if(pTimeEntry->end <= pTimeEntry->begin) ++ { ++ delta = pTimeEntry->begin - pTimeEntry->end; ++ } ++ else ++ { ++ delta = ((MV_U32)0x10000 - pTimeEntry->end) + pTimeEntry->begin; ++ } ++ pTimeEntry->total += delta; ++ ++ if(delta < pTimeEntry->min) ++ pTimeEntry->min = delta; ++ ++ if(delta > pTimeEntry->max) ++ pTimeEntry->max = delta; ++ ++ pTimeEntry->left--; ++ } ++} ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvDebug.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvDebug.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvDebug.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvDebug.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,178 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++ ++#ifndef __INCmvDebugh ++#define __INCmvDebugh ++ ++/* includes */ ++#include "mvTypes.h" ++ ++typedef enum ++{ ++ MV_MODULE_INVALID = -1, ++ MV_MODULE_ETH = 0, ++ MV_MODULE_IDMA, ++ MV_MODULE_XOR, ++ MV_MODULE_TWASI, ++ MV_MODULE_MGI, ++ MV_MODULE_USB, ++ MV_MODULE_CESA, ++ ++ MV_MODULE_MAX ++}MV_MODULE_ID; ++ ++/* Define generic flags useful for most of modules */ ++#define MV_DEBUG_FLAG_ALL (0) ++#define MV_DEBUG_FLAG_INIT (1 << 0) ++#define MV_DEBUG_FLAG_RX (1 << 1) ++#define MV_DEBUG_FLAG_TX (1 << 2) ++#define MV_DEBUG_FLAG_ERR (1 << 3) ++#define MV_DEBUG_FLAG_TRACE (1 << 4) ++#define MV_DEBUG_FLAG_DUMP (1 << 5) ++#define MV_DEBUG_FLAG_CACHE (1 << 6) ++#define MV_DEBUG_FLAG_IOCTL (1 << 7) ++#define MV_DEBUG_FLAG_STATS (1 << 8) ++ ++extern MV_U32 mvDebug; ++extern MV_U32 mvDebugModules[MV_MODULE_MAX]; ++ ++#ifdef MV_DEBUG ++# define MV_DEBUG_PRINT(module, flags, msg) mvOsPrintf msg ++# define MV_DEBUG_CODE(module, flags, code) code ++#elif defined(MV_RT_DEBUG) ++# define MV_DEBUG_PRINT(module, flags, msg) \ ++ if( (mvDebug & (1<<(module))) && \ ++ ((mvDebugModules[(module)] & (flags)) == (flags)) ) \ ++ mvOsPrintf msg ++# define MV_DEBUG_CODE(module, flags, code) \ ++ if( (mvDebug & (1<<(module))) && \ ++ ((mvDebugModules[(module)] & (flags)) == (flags)) ) \ ++ code ++#else ++# define MV_DEBUG_PRINT(module, flags, msg) ++# define MV_DEBUG_CODE(module, flags, code) ++#endif ++ ++ ++ ++/* typedefs */ ++ ++/* time measurement structure used to check how much time pass between ++ * two points ++ */ ++typedef struct { ++ char name[20]; /* name of the entry */ ++ unsigned long begin; /* time measured on begin point */ ++ unsigned long end; /* time measured on end point */ ++ unsigned long total; /* Accumulated time */ ++ unsigned long left; /* The rest measurement actions */ ++ unsigned long count; /* Maximum measurement actions */ ++ unsigned long min; /* Minimum time from begin to end */ ++ unsigned long max; /* Maximum time from begin to end */ ++} MV_DEBUG_TIMES; ++ ++ ++/* mvDebug.h API list */ ++ ++/****** Error Recording ******/ ++ ++/* Dump memory in specific format: ++ * address: X1X1X1X1 X2X2X2X2 ... X8X8X8X8 ++ */ ++void mvDebugMemDump(void* addr, int size, int access); ++ ++void mvDebugPrintBufInfo(BUF_INFO* pBufInfo, int size, int access); ++ ++void mvDebugPrintPktInfo(MV_PKT_INFO* pPktInfo, int size, int access); ++ ++void mvDebugPrintIpAddr(MV_U32 ipAddr); ++ ++void mvDebugPrintMacAddr(const MV_U8* pMacAddr); ++ ++/**** There are three functions deals with MV_DEBUG_TIMES structure ****/ ++ ++/* Reset MV_DEBUG_TIMES entry */ ++void mvDebugResetTimeEntry(MV_DEBUG_TIMES* pTimeEntry, int count, char* name); ++ ++/* Update MV_DEBUG_TIMES entry */ ++void mvDebugUpdateTimeEntry(MV_DEBUG_TIMES* pTimeEntry); ++ ++/* Print out MV_DEBUG_TIMES entry */ ++void mvDebugPrintTimeEntry(MV_DEBUG_TIMES* pTimeEntry, MV_BOOL isTitle); ++ ++ ++/******** General ***********/ ++ ++/* Change value of mvDebugPrint global variable */ ++ ++void mvDebugInit(void); ++void mvDebugModuleEnable(MV_MODULE_ID module, MV_BOOL isEnable); ++void mvDebugModuleSetFlags(MV_MODULE_ID module, MV_U32 flags); ++void mvDebugModuleClearFlags(MV_MODULE_ID module, MV_U32 flags); ++ ++ ++#endif /* __INCmvDebug.h */ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,225 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvDeviceIdh ++#define __INCmvDeviceIdh ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++/* defines */ ++#define MARVELL_VEN_ID 0x11ab ++ ++/* Disco-3 */ ++#define MV64460_DEV_ID 0x6480 ++#define MV64460B_DEV_ID 0x6485 ++#define MV64430_DEV_ID 0x6420 ++ ++/* Disco-5 */ ++#define MV64560_DEV_ID 0x6450 ++ ++/* Disco-6 */ ++#define MV64660_DEV_ID 0x6460 ++ ++/* Orion */ ++#define MV_1181_DEV_ID 0x1181 ++#define MV_5181_DEV_ID 0x5181 ++#define MV_5281_DEV_ID 0x5281 ++#define MV_5182_DEV_ID 0x5182 ++#define MV_8660_DEV_ID 0x8660 ++#define MV_5180_DEV_ID 0x5180 ++#define MV_5082_DEV_ID 0x5082 ++#define MV_1281_DEV_ID 0x1281 ++#define MV_6082_DEV_ID 0x6082 ++#define MV_6183_DEV_ID 0x6183 ++#define MV_6183L_DEV_ID 0x6083 ++ ++#define MV_5281_D0_REV 0x4 ++#define MV_5281_D0_ID ((MV_5281_DEV_ID << 16) | MV_5281_D0_REV) ++#define MV_5281_D0_NAME "88F5281 D0" ++ ++#define MV_5281_D1_REV 0x5 ++#define MV_5281_D1_ID ((MV_5281_DEV_ID << 16) | MV_5281_D1_REV) ++#define MV_5281_D1_NAME "88F5281 D1" ++ ++#define MV_5281_D2_REV 0x6 ++#define MV_5281_D2_ID ((MV_5281_DEV_ID << 16) | MV_5281_D2_REV) ++#define MV_5281_D2_NAME "88F5281 D2" ++ ++ ++#define MV_5181L_A0_REV 0x8 /* need for PCIE Er */ ++#define MV_5181_A1_REV 0x1 /* for USB Er ..*/ ++#define MV_5181_B0_REV 0x2 ++#define MV_5181_B1_REV 0x3 ++#define MV_5182_A1_REV 0x1 ++#define MV_5180N_B1_REV 0x3 ++#define MV_5181L_A0_ID ((MV_5181_DEV_ID << 16) | MV_5181L_A0_REV) ++ ++ ++ ++/* kw */ ++#define MV_6281_DEV_ID 0x6281 ++#define MV_6192_DEV_ID 0x6192 ++#define MV_6190_DEV_ID 0x6190 ++#define MV_6180_DEV_ID 0x6180 ++ ++#define MV_6281_A0_REV 0x2 ++#define MV_6281_A0_ID ((MV_6281_DEV_ID << 16) | MV_6281_A0_REV) ++#define MV_6281_A0_NAME "88F6281 A0" ++ ++#define MV_6192_A0_REV 0x2 ++#define MV_6192_A0_ID ((MV_6192_DEV_ID << 16) | MV_6192_A0_REV) ++#define MV_6192_A0_NAME "88F6192 A0" ++ ++#define MV_6190_A0_REV 0x2 ++#define MV_6190_A0_ID ((MV_6190_DEV_ID << 16) | MV_6190_A0_REV) ++#define MV_6190_A0_NAME "88F6190 A0" ++ ++#define MV_6180_A0_REV 0x2 ++#define MV_6180_A0_ID ((MV_6180_DEV_ID << 16) | MV_6180_A0_REV) ++#define MV_6180_A0_NAME "88F6180 A0" ++ ++#define MV_6281_A1_REV 0x3 ++#define MV_6281_A1_ID ((MV_6281_DEV_ID << 16) | MV_6281_A1_REV) ++#define MV_6281_A1_NAME "88F6281 A1" ++ ++#define MV_6192_A1_REV 0x3 ++#define MV_6192_A1_ID ((MV_6192_DEV_ID << 16) | MV_6192_A1_REV) ++#define MV_6192_A1_NAME "88F6192 A1" ++ ++#define MV_6190_A1_REV 0x3 ++#define MV_6190_A1_ID ((MV_6190_DEV_ID << 16) | MV_6190_A1_REV) ++#define MV_6190_A1_NAME "88F6190 A1" ++ ++#define MV_6180_A1_REV 0x3 ++#define MV_6180_A1_ID ((MV_6180_DEV_ID << 16) | MV_6180_A1_REV) ++#define MV_6180_A1_NAME "88F6180 A1" ++ ++#define MV_88F6XXX_A0_REV 0x2 ++#define MV_88F6XXX_A1_REV 0x3 ++/* Disco-Duo */ ++#define MV_78XX0_ZY_DEV_ID 0x6381 ++#define MV_78XX0_ZY_NAME "MV78X00" ++ ++#define MV_78XX0_Z0_REV 0x1 ++#define MV_78XX0_Z0_ID ((MV_78XX0_ZY_DEV_ID << 16) | MV_78XX0_Z0_REV) ++#define MV_78XX0_Z0_NAME "78X00 Z0" ++ ++#define MV_78XX0_Y0_REV 0x2 ++#define MV_78XX0_Y0_ID ((MV_78XX0_ZY_DEV_ID << 16) | MV_78XX0_Y0_REV) ++#define MV_78XX0_Y0_NAME "78X00 Y0" ++ ++#define MV_78XX0_DEV_ID 0x7800 ++#define MV_78XX0_NAME "MV78X00" ++ ++#define MV_76100_DEV_ID 0x7610 ++#define MV_78200_DEV_ID 0x7820 ++#define MV_78100_DEV_ID 0x7810 ++#define MV_78XX0_A0_REV 0x1 ++#define MV_78XX0_A1_REV 0x2 ++ ++#define MV_76100_NAME "MV76100" ++#define MV_78100_NAME "MV78100" ++#define MV_78200_NAME "MV78200" ++ ++#define MV_76100_A0_ID ((MV_76100_DEV_ID << 16) | MV_78XX0_A0_REV) ++#define MV_78100_A0_ID ((MV_78100_DEV_ID << 16) | MV_78XX0_A0_REV) ++#define MV_78200_A0_ID ((MV_78200_DEV_ID << 16) | MV_78XX0_A0_REV) ++ ++#define MV_76100_A1_ID ((MV_76100_DEV_ID << 16) | MV_78XX0_A1_REV) ++#define MV_78100_A1_ID ((MV_78100_DEV_ID << 16) | MV_78XX0_A1_REV) ++#define MV_78200_A1_ID ((MV_78200_DEV_ID << 16) | MV_78XX0_A1_REV) ++ ++#define MV_76100_A0_NAME "MV76100 A0" ++#define MV_78100_A0_NAME "MV78100 A0" ++#define MV_78200_A0_NAME "MV78200 A0" ++#define MV_78XX0_A0_NAME "MV78XX0 A0" ++ ++#define MV_76100_A1_NAME "MV76100 A1" ++#define MV_78100_A1_NAME "MV78100 A1" ++#define MV_78200_A1_NAME "MV78200 A1" ++#define MV_78XX0_A1_NAME "MV78XX0 A1" ++ ++/*MV88F632X family*/ ++#define MV_6321_DEV_ID 0x6321 ++#define MV_6322_DEV_ID 0x6322 ++#define MV_6323_DEV_ID 0x6323 ++ ++#define MV_6321_NAME "88F6321" ++#define MV_6322_NAME "88F6322" ++#define MV_6323_NAME "88F6323" ++ ++#define MV_632X_A1_REV 0x2 ++ ++#define MV_6321_A1_ID ((MV_6321_DEV_ID << 16) | MV_632X_A1_REV) ++#define MV_6322_A1_ID ((MV_6322_DEV_ID << 16) | MV_632X_A1_REV) ++#define MV_6323_A1_ID ((MV_6323_DEV_ID << 16) | MV_632X_A1_REV) ++ ++#define MV_6321_A1_NAME "88F6321 A1" ++#define MV_6322_A1_NAME "88F6322 A1" ++#define MV_6323_A1_NAME "88F6323 A1" ++ ++ ++#endif /* __INCmvDeviceIdh */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvHalVer.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvHalVer.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvHalVer.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvHalVer.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,73 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvHalVerh ++#define __INCmvHalVerh ++ ++/* Defines */ ++#define MV_HAL_VERSION "FEROCEON_HAL_3_1_7" ++#define MV_RELEASE_BASELINE "SoCandControllers_FEROCEON_RELEASE_7_9_2009_KW_4_3_4_DD_2_1_4_6183_1_1_4" ++ ++#endif /* __INCmvHalVerh */ +\ No newline at end of file +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvStack.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvStack.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvStack.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvStack.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,100 @@ ++/******************************************************************************* ++* Copyright 2003, Marvell Semiconductor Israel LTD. * ++* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL. * ++* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT * ++* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE * ++* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL. * ++* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED, * ++* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE. * ++* * ++* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, * ++* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL * ++* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K. * ++* (MJKK), MARVELL SEMICONDUCTOR ISRAEL LTD (MSIL). * ++******************************************************************************** ++* mvQueue.c ++* ++* FILENAME: $Workfile: mvStack.c $ ++* REVISION: $Revision: 1.1 $ ++* LAST UPDATE: $Modtime: $ ++* ++* DESCRIPTION: ++* This file implements simple Stack LIFO functionality. ++*******************************************************************************/ ++ ++/* includes */ ++#include "mvOs.h" ++#include "mvTypes.h" ++#include "mvDebug.h" ++#include "mvStack.h" ++ ++/* defines */ ++ ++ ++/* Public functions */ ++ ++ ++/* Purpose: Create new stack ++ * Inputs: ++ * - MV_U32 noOfElements - maximum number of elements in the stack. ++ * Each element 4 bytes size ++ * Return: void* - pointer to created stack. ++ */ ++void* mvStackCreate(int numOfElements) ++{ ++ MV_STACK* pStack; ++ MV_U32* pStackElements; ++ ++ pStack = (MV_STACK*)mvOsMalloc(sizeof(MV_STACK)); ++ pStackElements = (MV_U32*)mvOsMalloc(numOfElements*sizeof(MV_U32)); ++ if( (pStack == NULL) || (pStackElements == NULL) ) ++ { ++ mvOsPrintf("mvStack: Can't create new stack\n"); ++ return NULL; ++ } ++ memset(pStackElements, 0, numOfElements*sizeof(MV_U32)); ++ pStack->numOfElements = numOfElements; ++ pStack->stackIdx = 0; ++ pStack->stackElements = pStackElements; ++ ++ return pStack; ++} ++ ++/* Purpose: Delete existing stack ++ * Inputs: ++ * - void* stackHndl - Stack handle as returned by "mvStackCreate()" function ++ * ++ * Return: MV_STATUS MV_NOT_FOUND - Failure. StackHandle is not valid. ++ * MV_OK - Success. ++ */ ++MV_STATUS mvStackDelete(void* stackHndl) ++{ ++ MV_STACK* pStack = (MV_STACK*)stackHndl; ++ ++ if( (pStack == NULL) || (pStack->stackElements == NULL) ) ++ return MV_NOT_FOUND; ++ ++ mvOsFree(pStack->stackElements); ++ mvOsFree(pStack); ++ ++ return MV_OK; ++} ++ ++ ++/* PrintOut status of the stack */ ++void mvStackStatus(void* stackHndl, MV_BOOL isPrintElements) ++{ ++ int i; ++ MV_STACK* pStack = (MV_STACK*)stackHndl; ++ ++ mvOsPrintf("StackHandle=%p, pElements=%p, numElements=%d, stackIdx=%d\n", ++ stackHndl, pStack->stackElements, pStack->numOfElements, ++ pStack->stackIdx); ++ if(isPrintElements == MV_TRUE) ++ { ++ for(i=0; istackIdx; i++) ++ { ++ mvOsPrintf("%3d. Value=0x%x\n", i, pStack->stackElements[i]); ++ } ++ } ++} +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvStack.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvStack.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvStack.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvStack.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,140 @@ ++/******************************************************************************* ++* Copyright 2003, Marvell Semiconductor Israel LTD. * ++* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL. * ++* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT * ++* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE * ++* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL. * ++* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED, * ++* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE. * ++* * ++* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, * ++* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL * ++* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K. * ++* (MJKK), MARVELL SEMICONDUCTOR ISRAEL LTD (MSIL). * ++******************************************************************************** ++* mvStack.h - Header File for : ++* ++* FILENAME: $Workfile: mvStack.h $ ++* REVISION: $Revision: 1.1 $ ++* LAST UPDATE: $Modtime: $ ++* ++* DESCRIPTION: ++* This file defines simple Stack (LIFO) functionality. ++* ++*******************************************************************************/ ++ ++#ifndef __mvStack_h__ ++#define __mvStack_h__ ++ ++ ++/* includes */ ++#include "mvTypes.h" ++ ++ ++/* defines */ ++ ++ ++/* typedefs */ ++/* Data structure describes general purpose Stack */ ++typedef struct ++{ ++ int stackIdx; ++ int numOfElements; ++ MV_U32* stackElements; ++} MV_STACK; ++ ++static INLINE MV_BOOL mvStackIsFull(void* stackHndl) ++{ ++ MV_STACK* pStack = (MV_STACK*)stackHndl; ++ ++ if(pStack->stackIdx == pStack->numOfElements) ++ return MV_TRUE; ++ ++ return MV_FALSE; ++} ++ ++static INLINE MV_BOOL mvStackIsEmpty(void* stackHndl) ++{ ++ MV_STACK* pStack = (MV_STACK*)stackHndl; ++ ++ if(pStack->stackIdx == 0) ++ return MV_TRUE; ++ ++ return MV_FALSE; ++} ++/* Purpose: Push new element to stack ++ * Inputs: ++ * - void* stackHndl - Stack handle as returned by "mvStackCreate()" function. ++ * - MV_U32 value - New element. ++ * ++ * Return: MV_STATUS MV_FULL - Failure. Stack is full. ++ * MV_OK - Success. Element is put to stack. ++ */ ++static INLINE void mvStackPush(void* stackHndl, MV_U32 value) ++{ ++ MV_STACK* pStack = (MV_STACK*)stackHndl; ++ ++#ifdef MV_RT_DEBUG ++ if(pStack->stackIdx == pStack->numOfElements) ++ { ++ mvOsPrintf("mvStackPush: Stack is FULL\n"); ++ return; ++ } ++#endif /* MV_RT_DEBUG */ ++ ++ pStack->stackElements[pStack->stackIdx] = value; ++ pStack->stackIdx++; ++} ++ ++/* Purpose: Pop element from the top of stack and copy it to "pValue" ++ * Inputs: ++ * - void* stackHndl - Stack handle as returned by "mvStackCreate()" function. ++ * - MV_U32 value - Element in the top of stack. ++ * ++ * Return: MV_STATUS MV_EMPTY - Failure. Stack is empty. ++ * MV_OK - Success. Element is removed from the stack and ++ * copied to pValue argument ++ */ ++static INLINE MV_U32 mvStackPop(void* stackHndl) ++{ ++ MV_STACK* pStack = (MV_STACK*)stackHndl; ++ ++#ifdef MV_RT_DEBUG ++ if(pStack->stackIdx == 0) ++ { ++ mvOsPrintf("mvStackPop: Stack is EMPTY\n"); ++ return 0; ++ } ++#endif /* MV_RT_DEBUG */ ++ ++ pStack->stackIdx--; ++ return pStack->stackElements[pStack->stackIdx]; ++} ++ ++static INLINE int mvStackIndex(void* stackHndl) ++{ ++ MV_STACK* pStack = (MV_STACK*)stackHndl; ++ ++ return pStack->stackIdx; ++} ++ ++static INLINE int mvStackFreeElements(void* stackHndl) ++{ ++ MV_STACK* pStack = (MV_STACK*)stackHndl; ++ ++ return (pStack->numOfElements - pStack->stackIdx); ++} ++ ++/* mvStack.h API list */ ++ ++/* Create new Stack */ ++void* mvStackCreate(int numOfElements); ++ ++/* Delete existing stack */ ++MV_STATUS mvStackDelete(void* stackHndl); ++ ++/* Print status of the stack */ ++void mvStackStatus(void* stackHndl, MV_BOOL isPrintElements); ++ ++#endif /* __mvStack_h__ */ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvTypes.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvTypes.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/common/mvTypes.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/common/mvTypes.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,245 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvTypesh ++#define __INCmvTypesh ++ ++/* Defines */ ++ ++/* The following is a list of Marvell status */ ++#define MV_ERROR (-1) ++#define MV_OK (0x00) /* Operation succeeded */ ++#define MV_FAIL (0x01) /* Operation failed */ ++#define MV_BAD_VALUE (0x02) /* Illegal value (general) */ ++#define MV_OUT_OF_RANGE (0x03) /* The value is out of range */ ++#define MV_BAD_PARAM (0x04) /* Illegal parameter in function called */ ++#define MV_BAD_PTR (0x05) /* Illegal pointer value */ ++#define MV_BAD_SIZE (0x06) /* Illegal size */ ++#define MV_BAD_STATE (0x07) /* Illegal state of state machine */ ++#define MV_SET_ERROR (0x08) /* Set operation failed */ ++#define MV_GET_ERROR (0x09) /* Get operation failed */ ++#define MV_CREATE_ERROR (0x0A) /* Fail while creating an item */ ++#define MV_NOT_FOUND (0x0B) /* Item not found */ ++#define MV_NO_MORE (0x0C) /* No more items found */ ++#define MV_NO_SUCH (0x0D) /* No such item */ ++#define MV_TIMEOUT (0x0E) /* Time Out */ ++#define MV_NO_CHANGE (0x0F) /* Parameter(s) is already in this value */ ++#define MV_NOT_SUPPORTED (0x10) /* This request is not support */ ++#define MV_NOT_IMPLEMENTED (0x11) /* Request supported but not implemented */ ++#define MV_NOT_INITIALIZED (0x12) /* The item is not initialized */ ++#define MV_NO_RESOURCE (0x13) /* Resource not available (memory ...) */ ++#define MV_FULL (0x14) /* Item is full (Queue or table etc...) */ ++#define MV_EMPTY (0x15) /* Item is empty (Queue or table etc...) */ ++#define MV_INIT_ERROR (0x16) /* Error occured while INIT process */ ++#define MV_HW_ERROR (0x17) /* Hardware error */ ++#define MV_TX_ERROR (0x18) /* Transmit operation not succeeded */ ++#define MV_RX_ERROR (0x19) /* Recieve operation not succeeded */ ++#define MV_NOT_READY (0x1A) /* The other side is not ready yet */ ++#define MV_ALREADY_EXIST (0x1B) /* Tried to create existing item */ ++#define MV_OUT_OF_CPU_MEM (0x1C) /* Cpu memory allocation failed. */ ++#define MV_NOT_STARTED (0x1D) /* Not started yet */ ++#define MV_BUSY (0x1E) /* Item is busy. */ ++#define MV_TERMINATE (0x1F) /* Item terminates it's work. */ ++#define MV_NOT_ALIGNED (0x20) /* Wrong alignment */ ++#define MV_NOT_ALLOWED (0x21) /* Operation NOT allowed */ ++#define MV_WRITE_PROTECT (0x22) /* Write protected */ ++ ++ ++#define MV_INVALID (int)(-1) ++ ++#define MV_FALSE 0 ++#define MV_TRUE (!(MV_FALSE)) ++ ++ ++#ifndef NULL ++#define NULL ((void*)0) ++#endif ++ ++ ++#ifndef MV_ASMLANGUAGE ++/* typedefs */ ++ ++typedef char MV_8; ++typedef unsigned char MV_U8; ++ ++typedef int MV_32; ++typedef unsigned int MV_U32; ++ ++typedef short MV_16; ++typedef unsigned short MV_U16; ++ ++#ifdef MV_PPC64 ++typedef long MV_64; ++typedef unsigned long MV_U64; ++#else ++typedef long long MV_64; ++typedef unsigned long long MV_U64; ++#endif ++ ++typedef long MV_LONG; /* 32/64 */ ++typedef unsigned long MV_ULONG; /* 32/64 */ ++ ++typedef int MV_STATUS; ++typedef int MV_BOOL; ++typedef void MV_VOID; ++typedef float MV_FLOAT; ++ ++typedef int (*MV_FUNCPTR) (void); /* ptr to function returning int */ ++typedef void (*MV_VOIDFUNCPTR) (void); /* ptr to function returning void */ ++typedef double (*MV_DBLFUNCPTR) (void); /* ptr to function returning double*/ ++typedef float (*MV_FLTFUNCPTR) (void); /* ptr to function returning float */ ++ ++typedef MV_U32 MV_KHZ; ++typedef MV_U32 MV_MHZ; ++typedef MV_U32 MV_HZ; ++ ++ ++/* This enumerator describes the set of commands that can be applied on */ ++/* an engine (e.g. IDMA, XOR). Appling a comman depends on the current */ ++/* status (see MV_STATE enumerator) */ ++/* Start can be applied only when status is IDLE */ ++/* Stop can be applied only when status is IDLE, ACTIVE or PAUSED */ ++/* Pause can be applied only when status is ACTIVE */ ++/* Restart can be applied only when status is PAUSED */ ++typedef enum _mvCommand ++{ ++ MV_START, /* Start */ ++ MV_STOP, /* Stop */ ++ MV_PAUSE, /* Pause */ ++ MV_RESTART /* Restart */ ++} MV_COMMAND; ++ ++/* This enumerator describes the set of state conditions. */ ++/* Moving from one state to other is stricted. */ ++typedef enum _mvState ++{ ++ MV_IDLE, ++ MV_ACTIVE, ++ MV_PAUSED, ++ MV_UNDEFINED_STATE ++} MV_STATE; ++ ++ ++/* This structure describes address space window. Window base can be */ ++/* 64 bit, window size up to 4GB */ ++typedef struct _mvAddrWin ++{ ++ MV_U32 baseLow; /* 32bit base low */ ++ MV_U32 baseHigh; /* 32bit base high */ ++ MV_U32 size; /* 32bit size */ ++}MV_ADDR_WIN; ++ ++/* This binary enumerator describes protection attribute status */ ++typedef enum _mvProtRight ++{ ++ ALLOWED, /* Protection attribute allowed */ ++ FORBIDDEN /* Protection attribute forbidden */ ++}MV_PROT_RIGHT; ++ ++/* Unified struct for Rx and Tx packet operations. The user is required to */ ++/* be familier only with Tx/Rx descriptor command status. */ ++typedef struct _bufInfo ++{ ++ MV_U32 cmdSts; /* Tx/Rx command status */ ++ MV_U16 byteCnt; /* Size of valid data in the buffer */ ++ MV_U16 bufSize; /* Total size of the buffer */ ++ MV_U8 *pBuff; /* Pointer to Buffer */ ++ MV_U8 *pData; /* Pointer to data in the Buffer */ ++ MV_U32 userInfo1; /* Tx/Rx attached user information 1 */ ++ MV_U32 userInfo2; /* Tx/Rx attached user information 2 */ ++ struct _bufInfo *pNextBufInfo; /* Next buffer in packet */ ++} BUF_INFO; ++ ++/* This structure contains information describing one of buffers ++ * (fragments) they are built Ethernet packet. ++ */ ++typedef struct ++{ ++ MV_U8* bufVirtPtr; ++ MV_ULONG bufPhysAddr; ++ MV_U32 bufSize; ++ MV_U32 dataSize; ++ MV_U32 memHandle; ++ MV_32 bufAddrShift; ++} MV_BUF_INFO; ++ ++/* This structure contains information describing Ethernet packet. ++ * The packet can be divided for few buffers (fragments) ++ */ ++typedef struct ++{ ++ MV_ULONG osInfo; ++ MV_BUF_INFO *pFrags; ++ MV_U32 status; ++ MV_U16 pktSize; ++ MV_U16 numFrags; ++ MV_U32 ownerId; ++ MV_U32 fragIP; ++} MV_PKT_INFO; ++ ++#endif /* MV_ASMLANGUAGE */ ++ ++#endif /* __INCmvTypesh */ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/dbg-trace.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/dbg-trace.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/dbg-trace.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/dbg-trace.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,110 @@ ++#include ++#include ++#include ++#include "dbg-trace.h" ++ ++#define TRACE_ARR_LEN 800 ++#define STR_LEN 128 ++struct trace { ++ struct timeval tv; ++ char str[STR_LEN]; ++ unsigned int callback_val1; ++ unsigned int callback_val2; ++ char valid; ++}; ++static unsigned int (*trc_callback1) (unsigned char) = NULL; ++static unsigned int (*trc_callback2) (unsigned char) = NULL; ++static unsigned char trc_param1 = 0; ++static unsigned char trc_param2 = 0; ++struct trace *trc_arr; ++static int trc_index; ++static int trc_active = 0; ++ ++void TRC_START() ++{ ++ trc_active = 1; ++} ++ ++void TRC_STOP() ++{ ++ trc_active = 0; ++} ++ ++void TRC_INIT(void *callback1, void *callback2, unsigned char callback1_param, unsigned char callback2_param) ++{ ++ printk("Marvell debug tracing is on\n"); ++ trc_arr = (struct trace *)kmalloc(TRACE_ARR_LEN*sizeof(struct trace),GFP_KERNEL); ++ if(trc_arr == NULL) ++ { ++ printk("Can't allocate Debug Trace buffer\n"); ++ return; ++ } ++ memset(trc_arr,0,TRACE_ARR_LEN*sizeof(struct trace)); ++ trc_index = 0; ++ trc_callback1 = callback1; ++ trc_callback2 = callback2; ++ trc_param1 = callback1_param; ++ trc_param2 = callback2_param; ++} ++void TRC_REC(char *fmt,...) ++{ ++ va_list args; ++ struct trace *trc = &trc_arr[trc_index]; ++ ++ if(trc_active == 0) ++ return; ++ ++ do_gettimeofday(&trc->tv); ++ if(trc_callback1) ++ trc->callback_val1 = trc_callback1(trc_param1); ++ if(trc_callback2) ++ trc->callback_val2 = trc_callback2(trc_param2); ++ va_start(args, fmt); ++ vsprintf(trc->str,fmt,args); ++ va_end(args); ++ trc->valid = 1; ++ if((++trc_index) == TRACE_ARR_LEN) { ++ trc_index = 0; ++ } ++} ++void TRC_OUTPUT(void) ++{ ++ int i,j; ++ struct trace *p; ++ printk("\n\nTrace %d items\n",TRACE_ARR_LEN); ++ for(i=0,j=trc_index; ivalid) { ++ unsigned long uoffs; ++ struct trace *plast; ++ if(p == &trc_arr[0]) ++ plast = &trc_arr[TRACE_ARR_LEN-1]; ++ else ++ plast = p-1; ++ if(p->tv.tv_sec == ((plast)->tv.tv_sec)) ++ uoffs = (p->tv.tv_usec - ((plast)->tv.tv_usec)); ++ else ++ uoffs = (1000000 - ((plast)->tv.tv_usec)) + ++ ((p->tv.tv_sec - ((plast)->tv.tv_sec) - 1) * 1000000) + ++ p->tv.tv_usec; ++ printk("%03d: [+%ld usec]", j, (unsigned long)uoffs); ++ if(trc_callback1) ++ printk("[%u]",p->callback_val1); ++ if(trc_callback2) ++ printk("[%u]",p->callback_val2); ++ printk(": %s",p->str); ++ } ++ p->valid = 0; ++ } ++ memset(trc_arr,0,TRACE_ARR_LEN*sizeof(struct trace)); ++ trc_index = 0; ++} ++void TRC_RELEASE(void) ++{ ++ kfree(trc_arr); ++ trc_index = 0; ++} ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/dbg-trace.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/dbg-trace.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/dbg-trace.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/dbg-trace.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,24 @@ ++ ++#ifndef _MV_DBG_TRCE_H_ ++#define _MV_DBG_TRCE_H_ ++ ++#ifdef CONFIG_MV_DBG_TRACE ++void TRC_INIT(void *callback1, void *callback2, ++ unsigned char callback1_param, unsigned char callback2_param); ++void TRC_REC(char *fmt,...); ++void TRC_OUTPUT(void); ++void TRC_RELEASE(void); ++void TRC_START(void); ++void TRC_STOP(void); ++ ++#else ++#define TRC_INIT(x1,x2,x3,x4) ++#define TRC_REC(X...) ++#define TRC_OUTPUT() ++#define TRC_RELEASE() ++#define TRC_START() ++#define TRC_STOP() ++#endif ++ ++ ++#endif +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,2513 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#include "boardEnv/mvBoardEnvLib.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "ctrlEnv/sys/mvCpuIf.h" ++#include "cpu/mvCpu.h" ++#include "cntmr/mvCntmr.h" ++#include "gpp/mvGpp.h" ++#include "twsi/mvTwsi.h" ++#include "pex/mvPex.h" ++#include "device/mvDevice.h" ++#include "eth/gbe/mvEthRegs.h" ++ ++/* defines */ ++/* #define MV_DEBUG */ ++#ifdef MV_DEBUG ++ #define DB(x) x ++#else ++ #define DB(x) ++#endif ++ ++extern MV_CPU_ARM_CLK _cpuARMDDRCLK[]; ++ ++#define CODE_IN_ROM MV_FALSE ++#define CODE_IN_RAM MV_TRUE ++ ++extern MV_BOARD_INFO* boardInfoTbl[]; ++#define BOARD_INFO(boardId) boardInfoTbl[boardId - BOARD_ID_BASE] ++ ++/* Locals */ ++static MV_DEV_CS_INFO* boardGetDevEntry(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); ++ ++MV_U32 tClkRate = -1; ++ ++ ++/******************************************************************************* ++* mvBoardEnvInit - Init board ++* ++* DESCRIPTION: ++* In this function the board environment take care of device bank ++* initialization. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvBoardEnvInit(MV_VOID) ++{ ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardEnvInit:Board unknown.\n"); ++ return; ++ ++ } ++ ++ /* Set GPP Out value */ ++ MV_REG_WRITE(GPP_DATA_OUT_REG(0), BOARD_INFO(boardId)->gppOutValLow); ++ MV_REG_WRITE(GPP_DATA_OUT_REG(1), BOARD_INFO(boardId)->gppOutValHigh); ++ ++ /* set GPP polarity */ ++ mvGppPolaritySet(0, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValLow); ++ mvGppPolaritySet(1, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValHigh); ++ ++ /* Workaround for Erratum FE-MISC-70*/ ++ if(mvCtrlRevGet()==MV_88F6XXX_A0_REV) ++ { ++ BOARD_INFO(boardId)->gppOutEnValLow &= 0xfffffffd; ++ BOARD_INFO(boardId)->gppOutEnValLow |= (BOARD_INFO(boardId)->gppOutEnValHigh) & 0x00000002; ++ } /*End of WA*/ ++ ++ /* Set GPP Out Enable*/ ++ mvGppTypeSet(0, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValLow); ++ mvGppTypeSet(1, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValHigh); ++ ++ /* Nand CE */ ++ MV_REG_BIT_SET(NAND_CTRL_REG, NAND_ACTCEBOOT_BIT); ++} ++ ++/******************************************************************************* ++* mvBoardModelGet - Get Board model ++* ++* DESCRIPTION: ++* This function returns 16bit describing board model. ++* Board model is constructed of one byte major and minor numbers in the ++* following manner: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* String describing board model. ++* ++*******************************************************************************/ ++MV_U16 mvBoardModelGet(MV_VOID) ++{ ++ return (mvBoardIdGet() >> 16); ++} ++ ++/******************************************************************************* ++* mbBoardRevlGet - Get Board revision ++* ++* DESCRIPTION: ++* This function returns a 32bit describing the board revision. ++* Board revision is constructed of 4bytes. 2bytes describes major number ++* and the other 2bytes describes minor munber. ++* For example for board revision 3.4 the function will return ++* 0x00030004. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* String describing board model. ++* ++*******************************************************************************/ ++MV_U16 mvBoardRevGet(MV_VOID) ++{ ++ return (mvBoardIdGet() & 0xFFFF); ++} ++ ++/******************************************************************************* ++* mvBoardNameGet - Get Board name ++* ++* DESCRIPTION: ++* This function returns a string describing the board model and revision. ++* String is extracted from board I2C EEPROM. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* pNameBuff - Buffer to contain board name string. Minimum size 32 chars. ++* ++* RETURN: ++* ++* MV_ERROR if informantion can not be read. ++*******************************************************************************/ ++MV_STATUS mvBoardNameGet(char *pNameBuff) ++{ ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsSPrintf (pNameBuff, "Board unknown.\n"); ++ return MV_ERROR; ++ ++ } ++ ++ mvOsSPrintf (pNameBuff, "%s",BOARD_INFO(boardId)->boardName); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvBoardIsPortInSgmii - ++* ++* DESCRIPTION: ++* This routine returns MV_TRUE for port number works in SGMII or MV_FALSE ++* For all other options. ++* ++* INPUT: ++* ethPortNum - Ethernet port number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE - port in SGMII. ++* MV_FALSE - other. ++* ++*******************************************************************************/ ++MV_BOOL mvBoardIsPortInSgmii(MV_U32 ethPortNum) ++{ ++ MV_BOOL ethPortSgmiiSupport[BOARD_ETH_PORT_NUM] = MV_ETH_PORT_SGMII; ++ ++ if(ethPortNum >= BOARD_ETH_PORT_NUM) ++ { ++ mvOsPrintf ("Invalid portNo=%d\n", ethPortNum); ++ return MV_FALSE; ++ } ++ return ethPortSgmiiSupport[ethPortNum]; ++} ++ ++/******************************************************************************* ++* mvBoardIsPortInGmii - ++* ++* DESCRIPTION: ++* This routine returns MV_TRUE for port number works in GMII or MV_FALSE ++* For all other options. ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE - port in GMII. ++* MV_FALSE - other. ++* ++*******************************************************************************/ ++MV_BOOL mvBoardIsPortInGmii(MV_VOID) ++{ ++ MV_U32 devClassId, devClass = 0; ++ if (mvBoardMppGroupTypeGet(devClass) == MV_BOARD_AUTO) ++ { ++ /* Get MPP module ID */ ++ devClassId = mvBoarModuleTypeGet(devClass); ++ if (MV_BOARD_MODULE_GMII_ID == devClassId) ++ return MV_TRUE; ++ } ++ else if (mvBoardMppGroupTypeGet(devClass) == MV_BOARD_GMII) ++ return MV_TRUE; ++ ++ return MV_FALSE; ++} ++/******************************************************************************* ++* mvBoardPhyAddrGet - Get the phy address ++* ++* DESCRIPTION: ++* This routine returns the Phy address of a given ethernet port. ++* ++* INPUT: ++* ethPortNum - Ethernet port number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit describing Phy address, -1 if the port number is wrong. ++* ++*******************************************************************************/ ++MV_32 mvBoardPhyAddrGet(MV_U32 ethPortNum) ++{ ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardPhyAddrGet: Board unknown.\n"); ++ return MV_ERROR; ++ } ++ ++ return BOARD_INFO(boardId)->pBoardMacInfo[ethPortNum].boardEthSmiAddr; ++} ++ ++/******************************************************************************* ++* mvBoardMacSpeedGet - Get the Mac speed ++* ++* DESCRIPTION: ++* This routine returns the Mac speed if pre define of a given ethernet port. ++* ++* INPUT: ++* ethPortNum - Ethernet port number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BOARD_MAC_SPEED, -1 if the port number is wrong. ++* ++*******************************************************************************/ ++MV_BOARD_MAC_SPEED mvBoardMacSpeedGet(MV_U32 ethPortNum) ++{ ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardMacSpeedGet: Board unknown.\n"); ++ return MV_ERROR; ++ } ++ ++ return BOARD_INFO(boardId)->pBoardMacInfo[ethPortNum].boardMacSpeed; ++} ++ ++/******************************************************************************* ++* mvBoardLinkStatusIrqGet - Get the IRQ number for the link status indication ++* ++* DESCRIPTION: ++* This routine returns the IRQ number for the link status indication. ++* ++* INPUT: ++* ethPortNum - Ethernet port number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* the number of the IRQ for the link status indication, -1 if the port ++* number is wrong or if not relevant. ++* ++*******************************************************************************/ ++MV_32 mvBoardLinkStatusIrqGet(MV_U32 ethPortNum) ++{ ++ MV_U32 boardId = mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardLinkStatusIrqGet: Board unknown.\n"); ++ return MV_ERROR; ++ } ++ ++ return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].linkStatusIrq; ++} ++ ++/******************************************************************************* ++* mvBoardSwitchPortGet - Get the mapping between the board connector and the ++* Ethernet Switch port ++* ++* DESCRIPTION: ++* This routine returns the matching Switch port. ++* ++* INPUT: ++* ethPortNum - Ethernet port number. ++* boardPortNum - logical number of the connector on the board ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* the matching Switch port, -1 if the port number is wrong or if not relevant. ++* ++*******************************************************************************/ ++MV_32 mvBoardSwitchPortGet(MV_U32 ethPortNum, MV_U8 boardPortNum) ++{ ++ MV_U32 boardId = mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardSwitchPortGet: Board unknown.\n"); ++ return MV_ERROR; ++ } ++ if (boardPortNum >= BOARD_ETH_SWITCH_PORT_NUM) ++ { ++ mvOsPrintf("mvBoardSwitchPortGet: Illegal board port number.\n"); ++ return MV_ERROR; ++ } ++ ++ return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].qdPort[boardPortNum]; ++} ++ ++/******************************************************************************* ++* mvBoardSwitchCpuPortGet - Get the the Ethernet Switch CPU port ++* ++* DESCRIPTION: ++* This routine returns the Switch CPU port. ++* ++* INPUT: ++* ethPortNum - Ethernet port number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* the Switch CPU port, -1 if the port number is wrong or if not relevant. ++* ++*******************************************************************************/ ++MV_32 mvBoardSwitchCpuPortGet(MV_U32 ethPortNum) ++{ ++ MV_U32 boardId = mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardSwitchCpuPortGet: Board unknown.\n"); ++ return MV_ERROR; ++ } ++ ++ return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].qdCpuPort; ++} ++ ++/******************************************************************************* ++* mvBoardIsSwitchConnected - Get switch connection status ++* DESCRIPTION: ++* This routine returns port's connection status ++* ++* INPUT: ++* ethPortNum - Ethernet port number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 1 - if ethPortNum is connected to switch, 0 otherwise ++* ++*******************************************************************************/ ++MV_32 mvBoardIsSwitchConnected(MV_U32 ethPortNum) ++{ ++ MV_U32 boardId = mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardIsSwitchConnected: Board unknown.\n"); ++ return MV_ERROR; ++ } ++ ++ if(ethPortNum >= BOARD_INFO(boardId)->numBoardMacInfo) ++ { ++ mvOsPrintf("mvBoardIsSwitchConnected: Illegal port number(%u)\n", ethPortNum); ++ return MV_ERROR; ++ } ++ ++ if((MV_32)(BOARD_INFO(boardId)->pSwitchInfo)) ++ return (MV_32)(BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].switchOnPort == ethPortNum); ++ else ++ return 0; ++} ++/******************************************************************************* ++* mvBoardSmiScanModeGet - Get Switch SMI scan mode ++* ++* DESCRIPTION: ++* This routine returns Switch SMI scan mode. ++* ++* INPUT: ++* ethPortNum - Ethernet port number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 1 for SMI_MANUAL_MODE, -1 if the port number is wrong or if not relevant. ++* ++*******************************************************************************/ ++MV_32 mvBoardSmiScanModeGet(MV_U32 ethPortNum) ++{ ++ MV_U32 boardId = mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardSmiScanModeGet: Board unknown.\n"); ++ return MV_ERROR; ++ } ++ ++ return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].smiScanMode; ++} ++/******************************************************************************* ++* mvBoardSpecInitGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: Return MV_TRUE and parameters in case board need spesific phy init, ++* otherwise return MV_FALSE. ++* ++* ++*******************************************************************************/ ++ ++MV_BOOL mvBoardSpecInitGet(MV_U32* regOff, MV_U32* data) ++{ ++ return MV_FALSE; ++} ++ ++/******************************************************************************* ++* mvBoardTclkGet - Get the board Tclk (Controller clock) ++* ++* DESCRIPTION: ++* This routine extract the controller core clock. ++* This function uses the controller counters to make identification. ++* Note: In order to avoid interference, make sure task context switch ++* and interrupts will not occure during this function operation ++* ++* INPUT: ++* countNum - Counter number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit clock cycles in Hertz. ++* ++*******************************************************************************/ ++MV_U32 mvBoardTclkGet(MV_VOID) ++{ ++ if(mvCtrlModelGet()==MV_6281_DEV_ID) ++ { ++#if defined(TCLK_AUTO_DETECT) ++ MV_U32 tmpTClkRate = MV_BOARD_TCLK_166MHZ; ++ ++ tmpTClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); ++ tmpTClkRate &= MSAR_TCLCK_MASK; ++ ++ switch (tmpTClkRate) ++ { ++ case MSAR_TCLCK_166: ++ return MV_BOARD_TCLK_166MHZ; ++ break; ++ case MSAR_TCLCK_200: ++ return MV_BOARD_TCLK_200MHZ; ++ break; ++ } ++#else ++ return MV_BOARD_TCLK_200MHZ; ++#endif ++ } ++ ++ return MV_BOARD_TCLK_166MHZ; ++ ++} ++/******************************************************************************* ++* mvBoardSysClkGet - Get the board SysClk (CPU bus clock) ++* ++* DESCRIPTION: ++* This routine extract the CPU bus clock. ++* ++* INPUT: ++* countNum - Counter number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit clock cycles in Hertz. ++* ++*******************************************************************************/ ++static MV_U32 mvBoard6180SysClkGet(MV_VOID) ++{ ++ MV_U32 sysClkRate=0; ++ MV_CPU_ARM_CLK _cpu6180_ddr_l2_CLK[] = MV_CPU6180_DDR_L2_CLCK_TBL; ++ ++ sysClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); ++ sysClkRate = sysClkRate & MSAR_CPUCLCK_MASK_6180; ++ sysClkRate = sysClkRate >> MSAR_CPUCLCK_OFFS_6180; ++ ++ sysClkRate = _cpu6180_ddr_l2_CLK[sysClkRate].ddrClk; ++ ++ return sysClkRate; ++ ++} ++ ++MV_U32 mvBoardSysClkGet(MV_VOID) ++{ ++#ifdef SYSCLK_AUTO_DETECT ++ MV_U32 sysClkRate, tmp, pClkRate, indexDdrRtio; ++ MV_U32 cpuCLK[] = MV_CPU_CLCK_TBL; ++ MV_U32 ddrRtio[][2] = MV_DDR_CLCK_RTIO_TBL; ++ ++ if(mvCtrlModelGet() == MV_6180_DEV_ID) ++ return mvBoard6180SysClkGet(); ++ ++ tmp = MV_REG_READ(MPP_SAMPLE_AT_RESET); ++ pClkRate = MSAR_CPUCLCK_EXTRACT(tmp); ++ pClkRate = cpuCLK[pClkRate]; ++ ++ indexDdrRtio = tmp & MSAR_DDRCLCK_RTIO_MASK; ++ indexDdrRtio = indexDdrRtio >> MSAR_DDRCLCK_RTIO_OFFS; ++ if(ddrRtio[indexDdrRtio][0] != 0) ++ sysClkRate = ((pClkRate * ddrRtio[indexDdrRtio][1]) / ddrRtio[indexDdrRtio][0]); ++ else ++ sysClkRate = 0; ++ return sysClkRate; ++#else ++ return MV_BOARD_DEFAULT_SYSCLK; ++#endif ++} ++ ++ ++/******************************************************************************* ++* mvBoardPexBridgeIntPinGet - Get PEX to PCI bridge interrupt pin number ++* ++* DESCRIPTION: ++* Multi-ported PCI Express bridges that is implemented on the board ++* collapse interrupts across multiple conventional PCI/PCI-X buses. ++* A dual-headed PCI Express bridge would map (or "swizzle") the ++* interrupts per the following table (in accordance with the respective ++* logical PCI/PCI-X bridge's Device Number), collapse the INTA#-INTD# ++* signals from its two logical PCI/PCI-X bridges, collapse the ++* INTA#-INTD# signals from any internal sources, and convert the ++* signals to in-band PCI Express messages. 10 ++* This function returns the upstream interrupt as it was converted by ++* the bridge, according to board configuration and the following table: ++* PCI dev num ++* Interrupt pin 7, 8, 9 ++* A -> A D C ++* B -> B A D ++* C -> C B A ++* D -> D C B ++* ++* ++* INPUT: ++* devNum - PCI/PCIX device number. ++* intPin - PCI Int pin ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Int pin connected to the Interrupt controller ++* ++*******************************************************************************/ ++MV_U32 mvBoardPexBridgeIntPinGet(MV_U32 devNum, MV_U32 intPin) ++{ ++ MV_U32 realIntPin = ((intPin + (3 - (devNum % 4))) %4 ); ++ ++ if (realIntPin == 0) return 4; ++ else return realIntPin; ++ ++} ++ ++/******************************************************************************* ++* mvBoardDebugLedNumGet - Get number of debug Leds ++* ++* DESCRIPTION: ++* INPUT: ++* boardId ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_U32 mvBoardDebugLedNumGet(MV_U32 boardId) ++{ ++ return BOARD_INFO(boardId)->activeLedsNumber; ++} ++ ++/******************************************************************************* ++* mvBoardDebugLeg - Set the board debug Leds ++* ++* DESCRIPTION: turn on/off status leds. ++* Note: assume MPP leds are part of group 0 only. ++* ++* INPUT: ++* hexNum - Number to be displied in hex by Leds. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvBoardDebugLed(MV_U32 hexNum) ++{ ++ MV_U32 val = 0,totalMask, currentBitMask = 1,i; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ if (BOARD_INFO(boardId)->pLedGppPin == NULL) ++ return; ++ ++ totalMask = (1 << BOARD_INFO(boardId)->activeLedsNumber) -1; ++ hexNum &= totalMask; ++ totalMask = 0; ++ ++ for (i = 0 ; i < BOARD_INFO(boardId)->activeLedsNumber ; i++) ++ { ++ if (hexNum & currentBitMask) ++ { ++ val |= (1 << BOARD_INFO(boardId)->pLedGppPin[i]); ++ } ++ ++ totalMask |= (1 << BOARD_INFO(boardId)->pLedGppPin[i]); ++ ++ currentBitMask = (currentBitMask << 1); ++ } ++ ++ if (BOARD_INFO(boardId)->ledsPolarity) ++ { ++ mvGppValueSet(0, totalMask, val); ++ } ++ else ++ { ++ mvGppValueSet(0, totalMask, ~val); ++ } ++} ++ ++ ++/******************************************************************************* ++* mvBoarGpioPinGet - mvBoarGpioPinGet ++* ++* DESCRIPTION: ++* ++* INPUT: ++* class - MV_BOARD_GPP_CLASS enum. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* GPIO pin number. The function return -1 for bad parameters. ++* ++*******************************************************************************/ ++MV_32 mvBoarGpioPinNumGet(MV_BOARD_GPP_CLASS class, MV_U32 index) ++{ ++ MV_U32 boardId, i; ++ MV_U32 indexFound = 0; ++ ++ boardId = mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardRTCGpioPinGet:Board unknown.\n"); ++ return MV_ERROR; ++ ++ } ++ ++ for (i = 0; i < BOARD_INFO(boardId)->numBoardGppInfo; i++) ++ if (BOARD_INFO(boardId)->pBoardGppInfo[i].devClass == class) { ++ if (indexFound == index) ++ return (MV_U32)BOARD_INFO(boardId)->pBoardGppInfo[i].gppPinNum; ++ else ++ indexFound++; ++ ++ } ++ ++ return MV_ERROR; ++} ++ ++ ++/******************************************************************************* ++* mvBoardRTCGpioPinGet - mvBoardRTCGpioPinGet ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* GPIO pin number. The function return -1 for bad parameters. ++* ++*******************************************************************************/ ++MV_32 mvBoardRTCGpioPinGet(MV_VOID) ++{ ++ return mvBoarGpioPinNumGet(BOARD_GPP_RTC, 0); ++} ++ ++ ++/******************************************************************************* ++* mvBoardReset - mvBoardReset ++* ++* DESCRIPTION: ++* Reset the board ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None ++* ++*******************************************************************************/ ++MV_VOID mvBoardReset(MV_VOID) ++{ ++ MV_32 resetPin; ++ ++ /* Get gpp reset pin if define */ ++ resetPin = mvBoardResetGpioPinGet(); ++ if (resetPin != MV_ERROR) ++ { ++ MV_REG_BIT_RESET( GPP_DATA_OUT_REG(0) ,(1 << resetPin)); ++ MV_REG_BIT_RESET( GPP_DATA_OUT_EN_REG(0) ,(1 << resetPin)); ++ ++ } ++ else ++ { ++ /* No gpp reset pin was found, try to reset ussing ++ system reset out */ ++ MV_REG_BIT_SET( CPU_RSTOUTN_MASK_REG , BIT2); ++ MV_REG_BIT_SET( CPU_SYS_SOFT_RST_REG , BIT0); ++ } ++} ++ ++/******************************************************************************* ++* mvBoardResetGpioPinGet - mvBoardResetGpioPinGet ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* GPIO pin number. The function return -1 for bad parameters. ++* ++*******************************************************************************/ ++MV_32 mvBoardResetGpioPinGet(MV_VOID) ++{ ++ return mvBoarGpioPinNumGet(BOARD_GPP_RESET, 0); ++} ++/******************************************************************************* ++* mvBoardSDIOGpioPinGet - mvBoardSDIOGpioPinGet ++* ++* DESCRIPTION: ++* used for hotswap detection ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* GPIO pin number. The function return -1 for bad parameters. ++* ++*******************************************************************************/ ++MV_32 mvBoardSDIOGpioPinGet(MV_VOID) ++{ ++ return mvBoarGpioPinNumGet(BOARD_GPP_SDIO_DETECT, 0); ++} ++ ++/******************************************************************************* ++* mvBoardUSBVbusGpioPinGet - return Vbus input GPP ++* ++* DESCRIPTION: ++* ++* INPUT: ++* int devNo. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* GPIO pin number. The function return -1 for bad parameters. ++* ++*******************************************************************************/ ++MV_32 mvBoardUSBVbusGpioPinGet(MV_32 devId) ++{ ++ return mvBoarGpioPinNumGet(BOARD_GPP_USB_VBUS, devId); ++} ++ ++/******************************************************************************* ++* mvBoardUSBVbusEnGpioPinGet - return Vbus Enable output GPP ++* ++* DESCRIPTION: ++* ++* INPUT: ++* int devNo. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* GPIO pin number. The function return -1 for bad parameters. ++* ++*******************************************************************************/ ++MV_32 mvBoardUSBVbusEnGpioPinGet(MV_32 devId) ++{ ++ return mvBoarGpioPinNumGet(BOARD_GPP_USB_VBUS_EN, devId); ++} ++ ++ ++/******************************************************************************* ++* mvBoardGpioIntMaskGet - Get GPIO mask for interrupt pins ++* ++* DESCRIPTION: ++* This function returns a 32-bit mask of GPP pins that connected to ++* interrupt generating sources on board. ++* For example if UART channel A is hardwired to GPP pin 8 and ++* UART channel B is hardwired to GPP pin 4 the fuinction will return ++* the value 0x000000110 ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* See description. The function return -1 if board is not identified. ++* ++*******************************************************************************/ ++MV_32 mvBoardGpioIntMaskLowGet(MV_VOID) ++{ ++ MV_U32 boardId; ++ ++ boardId = mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardGpioIntMaskGet:Board unknown.\n"); ++ return MV_ERROR; ++ ++ } ++ ++ return BOARD_INFO(boardId)->intsGppMaskLow; ++} ++MV_32 mvBoardGpioIntMaskHighGet(MV_VOID) ++{ ++ MV_U32 boardId; ++ ++ boardId = mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardGpioIntMaskGet:Board unknown.\n"); ++ return MV_ERROR; ++ ++ } ++ ++ return BOARD_INFO(boardId)->intsGppMaskHigh; ++} ++ ++ ++/******************************************************************************* ++* mvBoardMppGet - Get board dependent MPP register value ++* ++* DESCRIPTION: ++* MPP settings are derived from board design. ++* MPP group consist of 8 MPPs. An MPP group represent MPP ++* control register. ++* This function retrieves board dependend MPP register value. ++* ++* INPUT: ++* mppGroupNum - MPP group number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit value describing MPP control register value. ++* ++*******************************************************************************/ ++MV_32 mvBoardMppGet(MV_U32 mppGroupNum) ++{ ++ MV_U32 boardId; ++ ++ boardId = mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardMppGet:Board unknown.\n"); ++ return MV_ERROR; ++ ++ } ++ ++ return BOARD_INFO(boardId)->pBoardMppConfigValue[0].mppGroup[mppGroupNum]; ++} ++ ++ ++/******************************************************************************* ++* mvBoardMppGroupId - If MPP group type is AUTO then identify it using twsi ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_VOID mvBoardMppGroupIdUpdate(MV_VOID) ++{ ++ ++ MV_BOARD_MPP_GROUP_CLASS devClass; ++ MV_BOARD_MODULE_ID_CLASS devClassId; ++ MV_BOARD_MPP_TYPE_CLASS mppGroupType; ++ MV_U32 devId; ++ MV_U32 maxMppGrp = 1; ++ ++ devId = mvCtrlModelGet(); ++ ++ switch(devId){ ++ case MV_6281_DEV_ID: ++ maxMppGrp = MV_6281_MPP_MAX_MODULE; ++ break; ++ case MV_6192_DEV_ID: ++ maxMppGrp = MV_6192_MPP_MAX_MODULE; ++ break; ++ case MV_6190_DEV_ID: ++ maxMppGrp = MV_6190_MPP_MAX_MODULE; ++ break; ++ case MV_6180_DEV_ID: ++ maxMppGrp = MV_6180_MPP_MAX_MODULE; ++ break; ++ } ++ ++ for (devClass = 0; devClass < maxMppGrp; devClass++) ++ { ++ /* If MPP group can be defined by the module connected to it */ ++ if (mvBoardMppGroupTypeGet(devClass) == MV_BOARD_AUTO) ++ { ++ /* Get MPP module ID */ ++ devClassId = mvBoarModuleTypeGet(devClass); ++ if (MV_ERROR != devClassId) ++ { ++ switch(devClassId) ++ { ++ case MV_BOARD_MODULE_TDM_ID: ++ case MV_BOARD_MODULE_TDM_5CHAN_ID: ++ mppGroupType = MV_BOARD_TDM; ++ break; ++ case MV_BOARD_MODULE_AUDIO_ID: ++ mppGroupType = MV_BOARD_AUDIO; ++ break; ++ case MV_BOARD_MODULE_RGMII_ID: ++ mppGroupType = MV_BOARD_RGMII; ++ break; ++ case MV_BOARD_MODULE_GMII_ID: ++ mppGroupType = MV_BOARD_GMII; ++ break; ++ case MV_BOARD_MODULE_TS_ID: ++ mppGroupType = MV_BOARD_TS; ++ break; ++ case MV_BOARD_MODULE_MII_ID: ++ mppGroupType = MV_BOARD_MII; ++ break; ++ default: ++ mppGroupType = MV_BOARD_OTHER; ++ break; ++ } ++ } ++ else ++ /* The module bay is empty */ ++ mppGroupType = MV_BOARD_OTHER; ++ ++ /* Update MPP group type */ ++ mvBoardMppGroupTypeSet(devClass, mppGroupType); ++ } ++ ++ /* Update MPP output voltage for RGMII 1.8V. Set port to GMII for GMII module */ ++ if ((mvBoardMppGroupTypeGet(devClass) == MV_BOARD_RGMII)) ++ MV_REG_BIT_SET(MPP_OUTPUT_DRIVE_REG,MPP_1_8_RGMII1_OUTPUT_DRIVE | MPP_1_8_RGMII0_OUTPUT_DRIVE); ++ else ++ { ++ if ((mvBoardMppGroupTypeGet(devClass) == MV_BOARD_GMII)) ++ { ++ MV_REG_BIT_RESET(MPP_OUTPUT_DRIVE_REG, BIT7 | BIT15); ++ MV_REG_BIT_RESET(ETH_PORT_SERIAL_CTRL_1_REG(0),BIT3); ++ MV_REG_BIT_RESET(ETH_PORT_SERIAL_CTRL_1_REG(1),BIT3); ++ } ++ else if ((mvBoardMppGroupTypeGet(devClass) == MV_BOARD_MII)) ++ { ++ /* Assumption that the MDC & MDIO should be 3.3V */ ++ MV_REG_BIT_RESET(MPP_OUTPUT_DRIVE_REG, BIT7 | BIT15); ++ /* Assumption that only ETH1 can be MII when using modules on DB */ ++ MV_REG_BIT_RESET(ETH_PORT_SERIAL_CTRL_1_REG(1),BIT3); ++ } ++ } ++ } ++} ++ ++/******************************************************************************* ++* mvBoardMppGroupTypeGet ++* ++* DESCRIPTION: ++* ++* INPUT: ++* mppGroupClass - MPP group number 0 for MPP[35:20] or 1 for MPP[49:36]. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_BOARD_MPP_TYPE_CLASS mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass) ++{ ++ MV_U32 boardId; ++ ++ boardId = mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardMppGet:Board unknown.\n"); ++ return MV_ERROR; ++ ++ } ++ ++ if (mppGroupClass == MV_BOARD_MPP_GROUP_1) ++ return BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup1; ++ else ++ return BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup2; ++} ++ ++/******************************************************************************* ++* mvBoardMppGroupTypeSet ++* ++* DESCRIPTION: ++* ++* INPUT: ++* mppGroupClass - MPP group number 0 for MPP[35:20] or 1 for MPP[49:36]. ++* mppGroupType - MPP group type for MPP[35:20] or for MPP[49:36]. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_VOID mvBoardMppGroupTypeSet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass, ++ MV_BOARD_MPP_TYPE_CLASS mppGroupType) ++{ ++ MV_U32 boardId; ++ ++ boardId = mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardMppGet:Board unknown.\n"); ++ } ++ ++ if (mppGroupClass == MV_BOARD_MPP_GROUP_1) ++ BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup1 = mppGroupType; ++ else ++ BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup2 = mppGroupType; ++ ++} ++ ++/******************************************************************************* ++* mvBoardMppMuxSet - Update MPP mux ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_VOID mvBoardMppMuxSet(MV_VOID) ++{ ++ ++ MV_BOARD_MPP_GROUP_CLASS devClass; ++ MV_BOARD_MPP_TYPE_CLASS mppGroupType; ++ MV_U32 devId; ++ MV_U8 muxVal = 0xf; ++ MV_U32 maxMppGrp = 1; ++ MV_TWSI_SLAVE twsiSlave; ++ MV_TWSI_ADDR slave; ++ ++ devId = mvCtrlModelGet(); ++ ++ switch(devId){ ++ case MV_6281_DEV_ID: ++ maxMppGrp = MV_6281_MPP_MAX_MODULE; ++ break; ++ case MV_6192_DEV_ID: ++ maxMppGrp = MV_6192_MPP_MAX_MODULE; ++ break; ++ case MV_6190_DEV_ID: ++ maxMppGrp = MV_6190_MPP_MAX_MODULE; ++ break; ++ case MV_6180_DEV_ID: ++ maxMppGrp = MV_6180_MPP_MAX_MODULE; ++ break; ++ } ++ ++ for (devClass = 0; devClass < maxMppGrp; devClass++) ++ { ++ mppGroupType = mvBoardMppGroupTypeGet(devClass); ++ ++ switch(mppGroupType) ++ { ++ case MV_BOARD_TDM: ++ muxVal &= ~(devClass ? (0x2 << (devClass * 2)):0x0); ++ break; ++ case MV_BOARD_AUDIO: ++ muxVal &= ~(devClass ? 0x7 : 0x0); /*old Z0 value 0xd:0x0*/ ++ break; ++ case MV_BOARD_TS: ++ muxVal &= ~(devClass ? (0x2 << (devClass * 2)):0x0); ++ break; ++ default: ++ muxVal |= (devClass ? 0xf : 0); ++ break; ++ } ++ } ++ ++ /* TWSI init */ ++ slave.type = ADDR7_BIT; ++ slave.address = 0; ++ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); ++ ++ /* Read MPP module ID */ ++ DB(mvOsPrintf("Board: twsi exp set\n")); ++ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(MV_BOARD_MUX_I2C_ADDR_ENTRY); ++ twsiSlave.slaveAddr.type = mvBoardTwsiExpAddrTypeGet(MV_BOARD_MUX_I2C_ADDR_ENTRY); ++ twsiSlave.validOffset = MV_TRUE; ++ /* Offset is the first command after the address which indicate the register number to be read ++ in next operation */ ++ twsiSlave.offset = 2; ++ twsiSlave.moreThen256 = MV_FALSE; ++ ++ ++ ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) ++ { ++ DB(mvOsPrintf("Board: twsi exp out val fail\n")); ++ return; ++ } ++ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); ++ ++ /* Change twsi exp to output */ ++ twsiSlave.offset = 6; ++ muxVal = 0; ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) ++ { ++ DB(mvOsPrintf("Board: twsi exp change to out fail\n")); ++ return; ++ } ++ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); ++ ++} ++ ++/******************************************************************************* ++* mvBoardTdmMppSet - set MPPs in TDM module ++* ++* DESCRIPTION: ++* ++* INPUT: type of second telephony device ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_VOID mvBoardTdmMppSet(MV_32 chType) ++{ ++ ++ MV_BOARD_MPP_GROUP_CLASS devClass; ++ MV_BOARD_MPP_TYPE_CLASS mppGroupType; ++ MV_U32 devId; ++ MV_U8 muxVal = 1; ++ MV_U8 muxValMask = 1; ++ MV_U8 twsiVal; ++ MV_U32 maxMppGrp = 1; ++ MV_TWSI_SLAVE twsiSlave; ++ MV_TWSI_ADDR slave; ++ ++ devId = mvCtrlModelGet(); ++ ++ switch(devId){ ++ case MV_6281_DEV_ID: ++ maxMppGrp = MV_6281_MPP_MAX_MODULE; ++ break; ++ case MV_6192_DEV_ID: ++ maxMppGrp = MV_6192_MPP_MAX_MODULE; ++ break; ++ case MV_6190_DEV_ID: ++ maxMppGrp = MV_6190_MPP_MAX_MODULE; ++ break; ++ case MV_6180_DEV_ID: ++ maxMppGrp = MV_6180_MPP_MAX_MODULE; ++ break; ++ } ++ ++ for (devClass = 0; devClass < maxMppGrp; devClass++) ++ { ++ mppGroupType = mvBoardMppGroupTypeGet(devClass); ++ if(mppGroupType == MV_BOARD_TDM) ++ break; ++ } ++ ++ if(devClass == maxMppGrp) ++ return; /* TDM module not found */ ++ ++ /* TWSI init */ ++ slave.type = ADDR7_BIT; ++ slave.address = 0; ++ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); ++ ++ /* Read MPP module ID */ ++ DB(mvOsPrintf("Board: twsi exp set\n")); ++ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(devClass); ++ twsiSlave.slaveAddr.type = ADDR7_BIT; ++ twsiSlave.validOffset = MV_TRUE; ++ /* Offset is the first command after the address which indicate the register number to be read ++ in next operation */ ++ twsiSlave.offset = 3; ++ twsiSlave.moreThen256 = MV_FALSE; ++ ++ if(mvBoardIdGet() == RD_88F6281A_ID) ++ { ++ muxVal = 0xc; ++ muxValMask = 0xf3; ++ } ++ ++ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); ++ muxVal = (twsiVal & muxValMask) | muxVal; ++ ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) ++ { ++ mvOsPrintf("Board: twsi exp out val fail\n"); ++ return; ++ } ++ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); ++ ++ /* Change twsi exp to output */ ++ twsiSlave.offset = 7; ++ muxVal = 0xfe; ++ if(mvBoardIdGet() == RD_88F6281A_ID) ++ muxVal = 0xf3; ++ ++ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); ++ muxVal = (twsiVal & muxVal); ++ ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) ++ { ++ mvOsPrintf("Board: twsi exp change to out fail\n"); ++ return; ++ } ++ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); ++ /* reset the line to 0 */ ++ twsiSlave.offset = 3; ++ muxVal = 0; ++ muxValMask = 1; ++ ++ if(mvBoardIdGet() == RD_88F6281A_ID) { ++ muxVal = 0x0; ++ muxValMask = 0xf3; ++ } ++ ++ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); ++ muxVal = (twsiVal & muxValMask) | muxVal; ++ ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) ++ { ++ mvOsPrintf("Board: twsi exp out val fail\n"); ++ return; ++ } ++ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); ++ ++ mvOsDelay(20); ++ ++ /* set the line to 1 */ ++ twsiSlave.offset = 3; ++ muxVal = 1; ++ muxValMask = 1; ++ ++ if(mvBoardIdGet() == RD_88F6281A_ID) ++ { ++ muxVal = 0xc; ++ muxValMask = 0xf3; ++ if(chType) /* FXS - issue reset properly */ ++ { ++ MV_REG_BIT_SET(GPP_DATA_OUT_REG(1), MV_GPP12); ++ mvOsDelay(50); ++ MV_REG_BIT_RESET(GPP_DATA_OUT_REG(1), MV_GPP12); ++ } ++ else /* FXO - issue reset via TDM_CODEC_RST*/ ++ { ++ /* change MPP44 type to TDM_CODEC_RST(0x2) */ ++ MV_REG_WRITE(MPP_CONTROL_REG5, ((MV_REG_READ(MPP_CONTROL_REG5) & 0xFFF0FFFF) | BIT17)); ++ } ++ } ++ ++ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); ++ muxVal = (twsiVal & muxValMask) | muxVal; ++ ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) ++ { ++ mvOsPrintf("Board: twsi exp out val fail\n"); ++ return; ++ } ++ ++ /* TBD - 5 channels */ ++#if defined(MV_TDM_5CHANNELS) ++ /* change MPP38 type to GPIO(0x0) & polarity for TDM_STROBE */ ++ MV_REG_WRITE(MPP_CONTROL_REG4, (MV_REG_READ(MPP_CONTROL_REG4) & 0xF0FFFFFF)); ++ mvGppPolaritySet(1, MV_GPP6, 0); ++ ++ twsiSlave.offset = 6; ++ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(2); ++ ++ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); ++ muxVal = (twsiVal & ~BIT2); ++ ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) ++ { ++ mvOsPrintf("Board: twsi exp change to out fail\n"); ++ return; ++ } ++ ++ ++ twsiSlave.offset = 2; ++ ++ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); ++ muxVal = (twsiVal & ~BIT2); ++ ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) ++ { ++ mvOsPrintf("Board: twsi exp change to out fail\n"); ++ return; ++ } ++#endif ++ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); ++ ++ ++} ++/******************************************************************************* ++* mvBoardVoiceConnModeGet - return SLIC/DAA connection & interrupt modes ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++*******************************************************************************/ ++ ++MV_VOID mvBoardVoiceConnModeGet(MV_32* connMode, MV_32* irqMode) ++{ ++ switch(mvBoardIdGet()) ++ { ++ case RD_88F6281A_ID: ++ *connMode = DAISY_CHAIN_MODE; ++ *irqMode = INTERRUPT_TO_TDM; ++ break; ++ case DB_88F6281A_BP_ID: ++ *connMode = DUAL_CHIP_SELECT_MODE; ++ *irqMode = INTERRUPT_TO_TDM; ++ break; ++ case RD_88F6192A_ID: ++ *connMode = DUAL_CHIP_SELECT_MODE; ++ *irqMode = INTERRUPT_TO_TDM; ++ break; ++ case DB_88F6192A_BP_ID: ++ *connMode = DUAL_CHIP_SELECT_MODE; ++ *irqMode = INTERRUPT_TO_TDM; ++ break; ++ default: ++ *connMode = *irqMode = -1; ++ mvOsPrintf("mvBoardVoiceAssembleModeGet: TDM not supported(boardId=0x%x)\n",mvBoardIdGet()); ++ } ++ return; ++ ++} ++ ++/******************************************************************************* ++* mvBoardMppModuleTypePrint - print module detect ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_VOID mvBoardMppModuleTypePrint(MV_VOID) ++{ ++ ++ MV_BOARD_MPP_GROUP_CLASS devClass; ++ MV_BOARD_MPP_TYPE_CLASS mppGroupType; ++ MV_U32 devId; ++ MV_U32 maxMppGrp = 1; ++ ++ devId = mvCtrlModelGet(); ++ ++ switch(devId){ ++ case MV_6281_DEV_ID: ++ maxMppGrp = MV_6281_MPP_MAX_MODULE; ++ break; ++ case MV_6192_DEV_ID: ++ maxMppGrp = MV_6192_MPP_MAX_MODULE; ++ break; ++ case MV_6190_DEV_ID: ++ maxMppGrp = MV_6190_MPP_MAX_MODULE; ++ break; ++ case MV_6180_DEV_ID: ++ maxMppGrp = MV_6180_MPP_MAX_MODULE; ++ break; ++ } ++ ++ for (devClass = 0; devClass < maxMppGrp; devClass++) ++ { ++ mppGroupType = mvBoardMppGroupTypeGet(devClass); ++ ++ switch(mppGroupType) ++ { ++ case MV_BOARD_TDM: ++ if(devId != MV_6190_DEV_ID) ++ mvOsPrintf("Module %d is TDM\n", devClass); ++ break; ++ case MV_BOARD_AUDIO: ++ if(devId != MV_6190_DEV_ID) ++ mvOsPrintf("Module %d is AUDIO\n", devClass); ++ break; ++ case MV_BOARD_RGMII: ++ if(devId != MV_6190_DEV_ID) ++ mvOsPrintf("Module %d is RGMII\n", devClass); ++ break; ++ case MV_BOARD_GMII: ++ if(devId != MV_6190_DEV_ID) ++ mvOsPrintf("Module %d is GMII\n", devClass); ++ break; ++ case MV_BOARD_TS: ++ if(devId != MV_6190_DEV_ID) ++ mvOsPrintf("Module %d is TS\n", devClass); ++ break; ++ default: ++ break; ++ } ++ } ++} ++ ++/* Board devices API managments */ ++ ++/******************************************************************************* ++* mvBoardGetDeviceNumber - Get number of device of some type on the board ++* ++* DESCRIPTION: ++* ++* INPUT: ++* devType - The device type ( Flash,RTC , etc .. ) ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* If the device is found on the board the then the functions returns the ++* number of those devices else the function returns 0 ++* ++* ++*******************************************************************************/ ++MV_32 mvBoardGetDevicesNumber(MV_BOARD_DEV_CLASS devClass) ++{ ++ MV_U32 foundIndex=0,devNum; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardGetDeviceNumber:Board unknown.\n"); ++ return 0xFFFFFFFF; ++ ++ } ++ ++ for (devNum = START_DEV_CS; devNum < BOARD_INFO(boardId)->numBoardDeviceIf; devNum++) ++ { ++ if (BOARD_INFO(boardId)->pDevCsInfo[devNum].devClass == devClass) ++ { ++ foundIndex++; ++ } ++ } ++ ++ return foundIndex; ++ ++} ++ ++/******************************************************************************* ++* mvBoardGetDeviceBaseAddr - Get base address of a device existing on the board ++* ++* DESCRIPTION: ++* ++* INPUT: ++* devIndex - The device sequential number on the board ++* devType - The device type ( Flash,RTC , etc .. ) ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* If the device is found on the board the then the functions returns the ++* Base address else the function returns 0xffffffff ++* ++* ++*******************************************************************************/ ++MV_32 mvBoardGetDeviceBaseAddr(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) ++{ ++ MV_DEV_CS_INFO* devEntry; ++ devEntry = boardGetDevEntry(devNum,devClass); ++ if (devEntry != NULL) ++ { ++ return mvCpuIfTargetWinBaseLowGet(DEV_TO_TARGET(devEntry->deviceCS)); ++ ++ } ++ ++ return 0xFFFFFFFF; ++} ++ ++/******************************************************************************* ++* mvBoardGetDeviceBusWidth - Get Bus width of a device existing on the board ++* ++* DESCRIPTION: ++* ++* INPUT: ++* devIndex - The device sequential number on the board ++* devType - The device type ( Flash,RTC , etc .. ) ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* If the device is found on the board the then the functions returns the ++* Bus width else the function returns 0xffffffff ++* ++* ++*******************************************************************************/ ++MV_32 mvBoardGetDeviceBusWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) ++{ ++ MV_DEV_CS_INFO* devEntry; ++ ++ devEntry = boardGetDevEntry(devNum,devClass); ++ if (devEntry != NULL) ++ { ++ return 8; ++ } ++ ++ return 0xFFFFFFFF; ++ ++} ++ ++/******************************************************************************* ++* mvBoardGetDeviceWidth - Get dev width of a device existing on the board ++* ++* DESCRIPTION: ++* ++* INPUT: ++* devIndex - The device sequential number on the board ++* devType - The device type ( Flash,RTC , etc .. ) ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* If the device is found on the board the then the functions returns the ++* dev width else the function returns 0xffffffff ++* ++* ++*******************************************************************************/ ++MV_32 mvBoardGetDeviceWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) ++{ ++ MV_DEV_CS_INFO* devEntry; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("Board unknown.\n"); ++ return 0xFFFFFFFF; ++ } ++ ++ devEntry = boardGetDevEntry(devNum,devClass); ++ if (devEntry != NULL) ++ return devEntry->devWidth; ++ ++ return MV_ERROR; ++ ++} ++ ++/******************************************************************************* ++* mvBoardGetDeviceWinSize - Get the window size of a device existing on the board ++* ++* DESCRIPTION: ++* ++* INPUT: ++* devIndex - The device sequential number on the board ++* devType - The device type ( Flash,RTC , etc .. ) ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* If the device is found on the board the then the functions returns the ++* window size else the function returns 0xffffffff ++* ++* ++*******************************************************************************/ ++MV_32 mvBoardGetDeviceWinSize(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) ++{ ++ MV_DEV_CS_INFO* devEntry; ++ MV_U32 boardId = mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("Board unknown.\n"); ++ return 0xFFFFFFFF; ++ } ++ ++ devEntry = boardGetDevEntry(devNum,devClass); ++ if (devEntry != NULL) ++ { ++ return mvCpuIfTargetWinSizeGet(DEV_TO_TARGET(devEntry->deviceCS)); ++ } ++ ++ return 0xFFFFFFFF; ++} ++ ++ ++/******************************************************************************* ++* boardGetDevEntry - returns the entry pointer of a device on the board ++* ++* DESCRIPTION: ++* ++* INPUT: ++* devIndex - The device sequential number on the board ++* devType - The device type ( Flash,RTC , etc .. ) ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* If the device is found on the board the then the functions returns the ++* dev number else the function returns 0x0 ++* ++* ++*******************************************************************************/ ++static MV_DEV_CS_INFO* boardGetDevEntry(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) ++{ ++ MV_U32 foundIndex=0,devIndex; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("boardGetDevEntry: Board unknown.\n"); ++ return NULL; ++ ++ } ++ ++ for (devIndex = START_DEV_CS; devIndex < BOARD_INFO(boardId)->numBoardDeviceIf; devIndex++) ++ { ++ /* TBR */ ++ /*if (BOARD_INFO(boardId)->pDevCsInfo[devIndex].deviceCS == MV_BOOTDEVICE_INDEX) ++ continue;*/ ++ ++ if (BOARD_INFO(boardId)->pDevCsInfo[devIndex].devClass == devClass) ++ { ++ if (foundIndex == devNum) ++ { ++ return &(BOARD_INFO(boardId)->pDevCsInfo[devIndex]); ++ } ++ foundIndex++; ++ } ++ } ++ ++ /* device not found */ ++ return NULL; ++} ++ ++/* Get device CS number */ ++ ++MV_U32 boardGetDevCSNum(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) ++{ ++ MV_DEV_CS_INFO* devEntry; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("Board unknown.\n"); ++ return 0xFFFFFFFF; ++ ++ } ++ ++ ++ devEntry = boardGetDevEntry(devNum,devClass); ++ if (devEntry != NULL) ++ return devEntry->deviceCS; ++ ++ return 0xFFFFFFFF; ++ ++} ++ ++/******************************************************************************* ++* mvBoardRtcTwsiAddrTypeGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++* ++*******************************************************************************/ ++MV_U8 mvBoardRtcTwsiAddrTypeGet() ++{ ++ int i; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) ++ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_RTC) ++ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; ++ return (MV_ERROR); ++} ++ ++/******************************************************************************* ++* mvBoardRtcTwsiAddrGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++* ++*******************************************************************************/ ++MV_U8 mvBoardRtcTwsiAddrGet() ++{ ++ int i; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) ++ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_RTC) ++ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; ++ return (0xFF); ++} ++ ++/******************************************************************************* ++* mvBoardA2DTwsiAddrTypeGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++* ++*******************************************************************************/ ++MV_U8 mvBoardA2DTwsiAddrTypeGet() ++{ ++ int i; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) ++ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_AUDIO_DEC) ++ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; ++ return (MV_ERROR); ++} ++ ++/******************************************************************************* ++* mvBoardA2DTwsiAddrGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++* ++*******************************************************************************/ ++MV_U8 mvBoardA2DTwsiAddrGet() ++{ ++ int i; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) ++ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_AUDIO_DEC) ++ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; ++ return (0xFF); ++} ++ ++/******************************************************************************* ++* mvBoardTwsiExpAddrTypeGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++* ++*******************************************************************************/ ++MV_U8 mvBoardTwsiExpAddrTypeGet(MV_U32 index) ++{ ++ int i; ++ MV_U32 indexFound = 0; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) ++ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_EXP) ++ { ++ if (indexFound == index) ++ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; ++ else ++ indexFound++; ++ } ++ ++ return (MV_ERROR); ++} ++ ++/******************************************************************************* ++* mvBoardTwsiExpAddrGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++* ++*******************************************************************************/ ++MV_U8 mvBoardTwsiExpAddrGet(MV_U32 index) ++{ ++ int i; ++ MV_U32 indexFound = 0; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) ++ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_EXP) ++ { ++ if (indexFound == index) ++ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; ++ else ++ indexFound++; ++ } ++ ++ return (0xFF); ++} ++ ++ ++/******************************************************************************* ++* mvBoardTwsiSatRAddrTypeGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++* ++*******************************************************************************/ ++MV_U8 mvBoardTwsiSatRAddrTypeGet(MV_U32 index) ++{ ++ int i; ++ MV_U32 indexFound = 0; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) ++ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_SATR) ++ { ++ if (indexFound == index) ++ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; ++ else ++ indexFound++; ++ } ++ ++ return (MV_ERROR); ++} ++ ++/******************************************************************************* ++* mvBoardTwsiSatRAddrGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++* ++*******************************************************************************/ ++MV_U8 mvBoardTwsiSatRAddrGet(MV_U32 index) ++{ ++ int i; ++ MV_U32 indexFound = 0; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) ++ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_SATR) ++ { ++ if (indexFound == index) ++ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; ++ else ++ indexFound++; ++ } ++ ++ return (0xFF); ++} ++ ++/******************************************************************************* ++* mvBoardNandWidthGet - ++* ++* DESCRIPTION: Get the width of the first NAND device in byte. ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: 1, 2, 4 or MV_ERROR ++* ++* ++*******************************************************************************/ ++/* */ ++MV_32 mvBoardNandWidthGet(void) ++{ ++ MV_U32 devNum; ++ MV_U32 devWidth; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ for (devNum = START_DEV_CS; devNum < BOARD_INFO(boardId)->numBoardDeviceIf; devNum++) ++ { ++ devWidth = mvBoardGetDeviceWidth(devNum, BOARD_DEV_NAND_FLASH); ++ if (devWidth != MV_ERROR) ++ return (devWidth / 8); ++ } ++ ++ /* NAND wasn't found */ ++ return MV_ERROR; ++} ++ ++MV_U32 gBoardId = -1; ++ ++/******************************************************************************* ++* mvBoardIdGet - Get Board model ++* ++* DESCRIPTION: ++* This function returns board ID. ++* Board ID is 32bit word constructed of board model (16bit) and ++* board revision (16bit) in the following way: 0xMMMMRRRR. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit board ID number, '-1' if board is undefined. ++* ++*******************************************************************************/ ++MV_U32 mvBoardIdGet(MV_VOID) ++{ ++ MV_U32 tmpBoardId = -1; ++ ++ if(gBoardId == -1) ++ { ++ #if defined(DB_88F6281A) ++ tmpBoardId = DB_88F6281A_BP_ID; ++ #elif defined(RD_88F6281A) ++ tmpBoardId = RD_88F6281A_ID; ++ #elif defined(DB_88F6192A) ++ tmpBoardId = DB_88F6192A_BP_ID; ++ #elif defined(DB_88F6190A) ++ tmpBoardId = DB_88F6190A_BP_ID; ++ #elif defined(RD_88F6192A) ++ tmpBoardId = RD_88F6192A_ID; ++ #elif defined(RD_88F6190A) ++ tmpBoardId = RD_88F6190A_ID; ++ #elif defined(DB_88F6180A) ++ tmpBoardId = DB_88F6180A_BP_ID; ++ #elif defined(RD_88F6281A_PCAC) ++ tmpBoardId = RD_88F6281A_PCAC_ID; ++ #elif defined(RD_88F6281A_SHEEVA_PLUG) ++ tmpBoardId = SHEEVA_PLUG_ID; ++ #elif defined(DB_CUSTOMER) ++ tmpBoardId = DB_CUSTOMER_ID; ++ #endif ++ gBoardId = tmpBoardId; ++ } ++ ++ return gBoardId; ++} ++ ++ ++/******************************************************************************* ++* mvBoarModuleTypeGet - mvBoarModuleTypeGet ++* ++* DESCRIPTION: ++* ++* INPUT: ++* group num - MV_BOARD_MPP_GROUP_CLASS enum ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* module num - MV_BOARD_MODULE_CLASS enum ++* ++*******************************************************************************/ ++MV_BOARD_MODULE_ID_CLASS mvBoarModuleTypeGet(MV_BOARD_MPP_GROUP_CLASS devClass) ++{ ++ MV_TWSI_SLAVE twsiSlave; ++ MV_TWSI_ADDR slave; ++ MV_U8 data; ++ ++ /* TWSI init */ ++ slave.type = ADDR7_BIT; ++ slave.address = 0; ++ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); ++ ++ /* Read MPP module ID */ ++ DB(mvOsPrintf("Board: Read MPP module ID\n")); ++ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(devClass); ++ twsiSlave.slaveAddr.type = mvBoardTwsiExpAddrTypeGet(devClass); ++ twsiSlave.validOffset = MV_TRUE; ++ /* Offset is the first command after the address which indicate the register number to be read ++ in next operation */ ++ twsiSlave.offset = 0; ++ twsiSlave.moreThen256 = MV_FALSE; ++ ++ ++ ++ if( MV_OK != mvTwsiRead (0, &twsiSlave, &data, 1) ) ++ { ++ DB(mvOsPrintf("Board: Read MPP module ID fail\n")); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Board: Read MPP module ID succeded\n")); ++ ++ return data; ++} ++ ++/******************************************************************************* ++* mvBoarTwsiSatRGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* device num - one of three devices ++* reg num - 0 or 1 ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* reg value ++* ++*******************************************************************************/ ++MV_U8 mvBoarTwsiSatRGet(MV_U8 devNum, MV_U8 regNum) ++{ ++ MV_TWSI_SLAVE twsiSlave; ++ MV_TWSI_ADDR slave; ++ MV_U8 data; ++ ++ /* TWSI init */ ++ slave.type = ADDR7_BIT; ++ slave.address = 0; ++ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); ++ ++ /* Read MPP module ID */ ++ DB(mvOsPrintf("Board: Read S@R device read\n")); ++ twsiSlave.slaveAddr.address = mvBoardTwsiSatRAddrGet(devNum); ++ twsiSlave.slaveAddr.type = mvBoardTwsiSatRAddrTypeGet(devNum); ++ twsiSlave.validOffset = MV_TRUE; ++ /* Use offset as command */ ++ twsiSlave.offset = regNum; ++ twsiSlave.moreThen256 = MV_FALSE; ++ ++ if( MV_OK != mvTwsiRead (0, &twsiSlave, &data, 1) ) ++ { ++ DB(mvOsPrintf("Board: Read S@R fail\n")); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Board: Read S@R succeded\n")); ++ ++ return data; ++} ++ ++/******************************************************************************* ++* mvBoarTwsiSatRSet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* devNum - one of three devices ++* regNum - 0 or 1 ++* regVal - value ++* ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* reg value ++* ++*******************************************************************************/ ++MV_STATUS mvBoarTwsiSatRSet(MV_U8 devNum, MV_U8 regNum, MV_U8 regVal) ++{ ++ MV_TWSI_SLAVE twsiSlave; ++ MV_TWSI_ADDR slave; ++ ++ /* TWSI init */ ++ slave.type = ADDR7_BIT; ++ slave.address = 0; ++ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); ++ ++ /* Read MPP module ID */ ++ twsiSlave.slaveAddr.address = mvBoardTwsiSatRAddrGet(devNum); ++ twsiSlave.slaveAddr.type = mvBoardTwsiSatRAddrTypeGet(devNum); ++ twsiSlave.validOffset = MV_TRUE; ++ DB(mvOsPrintf("Board: Write S@R device addr %x, type %x, data %x\n", twsiSlave.slaveAddr.address,\ ++ twsiSlave.slaveAddr.type, regVal)); ++ /* Use offset as command */ ++ twsiSlave.offset = regNum; ++ twsiSlave.moreThen256 = MV_FALSE; ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, ®Val, 1) ) ++ { ++ DB(mvOsPrintf("Board: Write S@R fail\n")); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Board: Write S@R succeded\n")); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvBoardSlicGpioPinGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++* ++*******************************************************************************/ ++MV_32 mvBoardSlicGpioPinGet(MV_U32 slicNum) ++{ ++ MV_U32 boardId; ++ boardId = mvBoardIdGet(); ++ ++ switch (boardId) ++ { ++ case DB_88F6281A_BP_ID: ++ case RD_88F6281A_ID: ++ default: ++ return MV_ERROR; ++ break; ++ ++ } ++} ++ ++/******************************************************************************* ++* mvBoardFanPowerControl - Turn on/off the fan power control on the RD-6281A ++* ++* DESCRIPTION: ++* ++* INPUT: ++* mode - MV_TRUE = on ; MV_FALSE = off ++* ++* OUTPUT: ++* MV_STATUS - MV_OK , MV_ERROR. ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_STATUS mvBoardFanPowerControl(MV_BOOL mode) ++{ ++ ++ MV_U8 val = 1, twsiVal; ++ MV_TWSI_SLAVE twsiSlave; ++ MV_TWSI_ADDR slave; ++ ++ if(mvBoardIdGet() != RD_88F6281A_ID) ++ return MV_ERROR; ++ ++ /* TWSI init */ ++ slave.type = ADDR7_BIT; ++ slave.address = 0; ++ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); ++ ++ /* Read MPP module ID */ ++ DB(mvOsPrintf("Board: twsi exp set\n")); ++ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(1); ++ twsiSlave.slaveAddr.type = ADDR7_BIT; ++ twsiSlave.validOffset = MV_TRUE; ++ /* Offset is the first command after the address which indicate the register number to be read ++ in next operation */ ++ twsiSlave.offset = 3; ++ twsiSlave.moreThen256 = MV_FALSE; ++ if(mode == MV_TRUE) ++ val = 0x1; ++ else ++ val = 0; ++ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); ++ val = (twsiVal & 0xfe) | val; ++ ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) ++ { ++ DB(mvOsPrintf("Board: twsi exp out val fail\n")); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); ++ ++ /* Change twsi exp to output */ ++ twsiSlave.offset = 7; ++ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); ++ val = (twsiVal & 0xfe); ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) ++ { ++ DB(mvOsPrintf("Board: twsi exp change to out fail\n")); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvBoardHDDPowerControl - Turn on/off the HDD power control on the RD-6281A ++* ++* DESCRIPTION: ++* ++* INPUT: ++* mode - MV_TRUE = on ; MV_FALSE = off ++* ++* OUTPUT: ++* MV_STATUS - MV_OK , MV_ERROR. ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_STATUS mvBoardHDDPowerControl(MV_BOOL mode) ++{ ++ ++ MV_U8 val = 1, twsiVal; ++ MV_TWSI_SLAVE twsiSlave; ++ MV_TWSI_ADDR slave; ++ ++ if(mvBoardIdGet() != RD_88F6281A_ID) ++ return MV_ERROR; ++ ++ /* TWSI init */ ++ slave.type = ADDR7_BIT; ++ slave.address = 0; ++ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); ++ ++ /* Read MPP module ID */ ++ DB(mvOsPrintf("Board: twsi exp set\n")); ++ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(1); ++ twsiSlave.slaveAddr.type = ADDR7_BIT; ++ twsiSlave.validOffset = MV_TRUE; ++ /* Offset is the first command after the address which indicate the register number to be read ++ in next operation */ ++ twsiSlave.offset = 3; ++ twsiSlave.moreThen256 = MV_FALSE; ++ if(mode == MV_TRUE) ++ val = 0x2; ++ else ++ val = 0; ++ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); ++ val = (twsiVal & 0xfd) | val; ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) ++ { ++ DB(mvOsPrintf("Board: twsi exp out val fail\n")); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); ++ ++ /* Change twsi exp to output */ ++ twsiSlave.offset = 7; ++ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); ++ val = (twsiVal & 0xfd); ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) ++ { ++ DB(mvOsPrintf("Board: twsi exp change to out fail\n")); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvBoardSDioWPControl - Turn on/off the SDIO WP on the RD-6281A ++* ++* DESCRIPTION: ++* ++* INPUT: ++* mode - MV_TRUE = on ; MV_FALSE = off ++* ++* OUTPUT: ++* MV_STATUS - MV_OK , MV_ERROR. ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_STATUS mvBoardSDioWPControl(MV_BOOL mode) ++{ ++ ++ MV_U8 val = 1, twsiVal; ++ MV_TWSI_SLAVE twsiSlave; ++ MV_TWSI_ADDR slave; ++ ++ if(mvBoardIdGet() != RD_88F6281A_ID) ++ return MV_ERROR; ++ ++ /* TWSI init */ ++ slave.type = ADDR7_BIT; ++ slave.address = 0; ++ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); ++ ++ /* Read MPP module ID */ ++ DB(mvOsPrintf("Board: twsi exp set\n")); ++ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(0); ++ twsiSlave.slaveAddr.type = ADDR7_BIT; ++ twsiSlave.validOffset = MV_TRUE; ++ /* Offset is the first command after the address which indicate the register number to be read ++ in next operation */ ++ twsiSlave.offset = 3; ++ twsiSlave.moreThen256 = MV_FALSE; ++ if(mode == MV_TRUE) ++ val = 0x10; ++ else ++ val = 0; ++ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); ++ val = (twsiVal & 0xef) | val; ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) ++ { ++ DB(mvOsPrintf("Board: twsi exp out val fail\n")); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); ++ ++ /* Change twsi exp to output */ ++ twsiSlave.offset = 7; ++ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); ++ val = (twsiVal & 0xef); ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) ++ { ++ DB(mvOsPrintf("Board: twsi exp change to out fail\n")); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); ++ return MV_OK; ++} ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,376 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++#ifndef __INCmvBoardEnvLibh ++#define __INCmvBoardEnvLibh ++ ++/* defines */ ++/* The below constant macros defines the board I2C EEPROM data offsets */ ++ ++ ++ ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "mvSysHwConfig.h" ++#include "boardEnv/mvBoardEnvSpec.h" ++ ++ ++/* DUART stuff for Tclk detection only */ ++#define DUART_BAUD_RATE 115200 ++#define MAX_CLOCK_MARGINE 5000000 /* Maximum detected clock margine */ ++ ++/* Voice devices assembly modes */ ++#define DAISY_CHAIN_MODE 1 ++#define DUAL_CHIP_SELECT_MODE 0 ++#define INTERRUPT_TO_MPP 1 ++#define INTERRUPT_TO_TDM 0 ++ ++ ++#define BOARD_ETH_PORT_NUM MV_ETH_MAX_PORTS ++#define BOARD_ETH_SWITCH_PORT_NUM 5 ++ ++#define MV_BOARD_MAX_USB_IF 1 ++#define MV_BOARD_MAX_MPP 7 ++#define MV_BOARD_NAME_LEN 0x20 ++ ++typedef struct _boardData ++{ ++ MV_U32 magic; ++ MV_U16 boardId; ++ MV_U8 boardVer; ++ MV_U8 boardRev; ++ MV_U32 reserved1; ++ MV_U32 reserved2; ++ ++}BOARD_DATA; ++ ++typedef enum _devBoardMppGroupClass ++{ ++ MV_BOARD_MPP_GROUP_1, ++ MV_BOARD_MPP_GROUP_2, ++ MV_BOARD_MAX_MPP_GROUP ++}MV_BOARD_MPP_GROUP_CLASS; ++ ++typedef enum _devBoardMppTypeClass ++{ ++ MV_BOARD_AUTO, ++ MV_BOARD_TDM, ++ MV_BOARD_AUDIO, ++ MV_BOARD_RGMII, ++ MV_BOARD_GMII, ++ MV_BOARD_TS, ++ MV_BOARD_MII, ++ MV_BOARD_OTHER ++}MV_BOARD_MPP_TYPE_CLASS; ++ ++typedef enum _devBoardModuleIdClass ++{ ++ MV_BOARD_MODULE_TDM_ID = 1, ++ MV_BOARD_MODULE_AUDIO_ID, ++ MV_BOARD_MODULE_RGMII_ID, ++ MV_BOARD_MODULE_GMII_ID, ++ MV_BOARD_MODULE_TS_ID, ++ MV_BOARD_MODULE_MII_ID, ++ MV_BOARD_MODULE_TDM_5CHAN_ID, ++ MV_BOARD_MODULE_OTHER_ID ++}MV_BOARD_MODULE_ID_CLASS; ++ ++typedef struct _boardMppTypeInfo ++{ ++ MV_BOARD_MPP_TYPE_CLASS boardMppGroup1; ++ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2; ++ ++}MV_BOARD_MPP_TYPE_INFO; ++ ++ ++typedef enum _devBoardClass ++{ ++ BOARD_DEV_NOR_FLASH, ++ BOARD_DEV_NAND_FLASH, ++ BOARD_DEV_SEVEN_SEG, ++ BOARD_DEV_FPGA, ++ BOARD_DEV_SRAM, ++ BOARD_DEV_SPI_FLASH, ++ BOARD_DEV_OTHER, ++}MV_BOARD_DEV_CLASS; ++ ++typedef enum _devTwsiBoardClass ++{ ++ BOARD_TWSI_RTC, ++ BOARD_DEV_TWSI_EXP, ++ BOARD_DEV_TWSI_SATR, ++ BOARD_TWSI_AUDIO_DEC, ++ BOARD_TWSI_OTHER ++}MV_BOARD_TWSI_CLASS; ++ ++typedef enum _devGppBoardClass ++{ ++ BOARD_GPP_RTC, ++ BOARD_GPP_MV_SWITCH, ++ BOARD_GPP_USB_VBUS, ++ BOARD_GPP_USB_VBUS_EN, ++ BOARD_GPP_USB_OC, ++ BOARD_GPP_USB_HOST_DEVICE, ++ BOARD_GPP_REF_CLCK, ++ BOARD_GPP_VOIP_SLIC, ++ BOARD_GPP_LIFELINE, ++ BOARD_GPP_BUTTON, ++ BOARD_GPP_TS_BUTTON_C, ++ BOARD_GPP_TS_BUTTON_U, ++ BOARD_GPP_TS_BUTTON_D, ++ BOARD_GPP_TS_BUTTON_L, ++ BOARD_GPP_TS_BUTTON_R, ++ BOARD_GPP_POWER_BUTTON, ++ BOARD_GPP_RESTOR_BUTTON, ++ BOARD_GPP_WPS_BUTTON, ++ BOARD_GPP_HDD0_POWER, ++ BOARD_GPP_HDD1_POWER, ++ BOARD_GPP_FAN_POWER, ++ BOARD_GPP_RESET, ++ BOARD_GPP_POWER_ON_LED, ++ BOARD_GPP_HDD_POWER, ++ BOARD_GPP_SDIO_POWER, ++ BOARD_GPP_SDIO_DETECT, ++ BOARD_GPP_SDIO_WP, ++ BOARD_GPP_SWITCH_PHY_INT, ++ BOARD_GPP_TSU_DIRCTION, ++ BOARD_GPP_OTHER ++}MV_BOARD_GPP_CLASS; ++ ++ ++typedef struct _devCsInfo ++{ ++ MV_U8 deviceCS; ++ MV_U32 params; ++ MV_U32 devClass; /* MV_BOARD_DEV_CLASS */ ++ MV_U8 devWidth; ++ ++}MV_DEV_CS_INFO; ++ ++ ++#define MV_BOARD_PHY_FORCE_10MB 0x0 ++#define MV_BOARD_PHY_FORCE_100MB 0x1 ++#define MV_BOARD_PHY_FORCE_1000MB 0x2 ++#define MV_BOARD_PHY_SPEED_AUTO 0x3 ++ ++typedef struct _boardSwitchInfo ++{ ++ MV_32 linkStatusIrq; ++ MV_32 qdPort[BOARD_ETH_SWITCH_PORT_NUM]; ++ MV_32 qdCpuPort; ++ MV_32 smiScanMode; /* 1 for SMI_MANUAL_MODE, 0 otherwise */ ++ MV_32 switchOnPort; ++ ++}MV_BOARD_SWITCH_INFO; ++ ++typedef struct _boardLedInfo ++{ ++ MV_U8 activeLedsNumber; ++ MV_U8 ledsPolarity; /* '0' or '1' to turn on led */ ++ MV_U8* gppPinNum; /* Pointer to GPP values */ ++ ++}MV_BOARD_LED_INFO; ++ ++typedef struct _boardGppInfo ++{ ++ MV_BOARD_GPP_CLASS devClass; ++ MV_U8 gppPinNum; ++ ++}MV_BOARD_GPP_INFO; ++ ++ ++typedef struct _boardTwsiInfo ++{ ++ MV_BOARD_TWSI_CLASS devClass; ++ MV_U8 twsiDevAddr; ++ MV_U8 twsiDevAddrType; ++ ++}MV_BOARD_TWSI_INFO; ++ ++ ++typedef enum _boardMacSpeed ++{ ++ BOARD_MAC_SPEED_10M, ++ BOARD_MAC_SPEED_100M, ++ BOARD_MAC_SPEED_1000M, ++ BOARD_MAC_SPEED_AUTO, ++ ++}MV_BOARD_MAC_SPEED; ++ ++typedef struct _boardMacInfo ++{ ++ MV_BOARD_MAC_SPEED boardMacSpeed; ++ MV_U8 boardEthSmiAddr; ++ ++}MV_BOARD_MAC_INFO; ++ ++typedef struct _boardMppInfo ++{ ++ MV_U32 mppGroup[MV_BOARD_MAX_MPP]; ++ ++}MV_BOARD_MPP_INFO; ++ ++typedef struct _boardInfo ++{ ++ char boardName[MV_BOARD_NAME_LEN]; ++ MV_U8 numBoardMppTypeValue; ++ MV_BOARD_MPP_TYPE_INFO* pBoardMppTypeValue; ++ MV_U8 numBoardMppConfigValue; ++ MV_BOARD_MPP_INFO* pBoardMppConfigValue; ++ MV_U32 intsGppMaskLow; ++ MV_U32 intsGppMaskHigh; ++ MV_U8 numBoardDeviceIf; ++ MV_DEV_CS_INFO* pDevCsInfo; ++ MV_U8 numBoardTwsiDev; ++ MV_BOARD_TWSI_INFO* pBoardTwsiDev; ++ MV_U8 numBoardMacInfo; ++ MV_BOARD_MAC_INFO* pBoardMacInfo; ++ MV_U8 numBoardGppInfo; ++ MV_BOARD_GPP_INFO* pBoardGppInfo; ++ MV_U8 activeLedsNumber; ++ MV_U8* pLedGppPin; ++ MV_U8 ledsPolarity; /* '0' or '1' to turn on led */ ++ /* GPP values */ ++ MV_U32 gppOutEnValLow; ++ MV_U32 gppOutEnValHigh; ++ MV_U32 gppOutValLow; ++ MV_U32 gppOutValHigh; ++ MV_U32 gppPolarityValLow; ++ MV_U32 gppPolarityValHigh; ++ ++ /* Switch Configuration */ ++ MV_BOARD_SWITCH_INFO* pSwitchInfo; ++}MV_BOARD_INFO; ++ ++ ++ ++MV_VOID mvBoardEnvInit(MV_VOID); ++MV_U32 mvBoardIdGet(MV_VOID); ++MV_U16 mvBoardModelGet(MV_VOID); ++MV_U16 mvBoardRevGet(MV_VOID); ++MV_STATUS mvBoardNameGet(char *pNameBuff); ++MV_32 mvBoardPhyAddrGet(MV_U32 ethPortNum); ++MV_BOARD_MAC_SPEED mvBoardMacSpeedGet(MV_U32 ethPortNum); ++MV_32 mvBoardLinkStatusIrqGet(MV_U32 ethPortNum); ++MV_32 mvBoardSwitchPortGet(MV_U32 ethPortNum, MV_U8 boardPortNum); ++MV_32 mvBoardSwitchCpuPortGet(MV_U32 ethPortNum); ++MV_32 mvBoardIsSwitchConnected(MV_U32 ethPortNum); ++MV_32 mvBoardSmiScanModeGet(MV_U32 ethPortNum); ++MV_BOOL mvBoardIsPortInSgmii(MV_U32 ethPortNum); ++MV_BOOL mvBoardIsPortInGmii(MV_VOID); ++MV_U32 mvBoardTclkGet(MV_VOID); ++MV_U32 mvBoardSysClkGet(MV_VOID); ++MV_U32 mvBoardDebugLedNumGet(MV_U32 boardId); ++MV_VOID mvBoardDebugLed(MV_U32 hexNum); ++MV_32 mvBoardMppGet(MV_U32 mppGroupNum); ++ ++MV_U8 mvBoardRtcTwsiAddrTypeGet(MV_VOID); ++MV_U8 mvBoardRtcTwsiAddrGet(MV_VOID); ++ ++MV_U8 mvBoardA2DTwsiAddrTypeGet(MV_VOID); ++MV_U8 mvBoardA2DTwsiAddrGet(MV_VOID); ++ ++MV_U8 mvBoardTwsiExpAddrGet(MV_U32 index); ++MV_U8 mvBoardTwsiSatRAddrTypeGet(MV_U32 index); ++MV_U8 mvBoardTwsiSatRAddrGet(MV_U32 index); ++MV_U8 mvBoardTwsiExpAddrTypeGet(MV_U32 index); ++MV_BOARD_MODULE_ID_CLASS mvBoarModuleTypeGet(MV_BOARD_MPP_GROUP_CLASS devClass); ++MV_BOARD_MPP_TYPE_CLASS mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass); ++MV_VOID mvBoardMppGroupTypeSet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass, ++ MV_BOARD_MPP_TYPE_CLASS mppGroupType); ++MV_VOID mvBoardMppGroupIdUpdate(MV_VOID); ++MV_VOID mvBoardMppMuxSet(MV_VOID); ++MV_VOID mvBoardTdmMppSet(MV_32 chType); ++MV_VOID mvBoardVoiceConnModeGet(MV_32* connMode, MV_32* irqMode); ++ ++MV_VOID mvBoardMppModuleTypePrint(MV_VOID); ++MV_VOID mvBoardReset(MV_VOID); ++MV_U8 mvBoarTwsiSatRGet(MV_U8 devNum, MV_U8 regNum); ++MV_STATUS mvBoarTwsiSatRSet(MV_U8 devNum, MV_U8 regNum, MV_U8 regVal); ++MV_BOOL mvBoardSpecInitGet(MV_U32* regOff, MV_U32* data); ++/* Board devices API managments */ ++MV_32 mvBoardGetDevicesNumber(MV_BOARD_DEV_CLASS devClass); ++MV_32 mvBoardGetDeviceBaseAddr(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); ++MV_32 mvBoardGetDeviceBusWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); ++MV_32 mvBoardGetDeviceWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); ++MV_32 mvBoardGetDeviceWinSize(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); ++MV_U32 boardGetDevCSNum(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); ++ ++/* Gpio Pin Connections API */ ++MV_32 mvBoardUSBVbusGpioPinGet(int devId); ++MV_32 mvBoardUSBVbusEnGpioPinGet(int devId); ++MV_U32 mvBoardPexBridgeIntPinGet(MV_U32 devNum, MV_U32 intPin); ++ ++MV_32 mvBoardResetGpioPinGet(MV_VOID); ++MV_32 mvBoardRTCGpioPinGet(MV_VOID); ++MV_32 mvBoardGpioIntMaskLowGet(MV_VOID); ++MV_32 mvBoardGpioIntMaskHighGet(MV_VOID); ++MV_32 mvBoardSlicGpioPinGet(MV_U32 slicNum); ++ ++MV_32 mvBoardSDIOGpioPinGet(MV_VOID); ++MV_STATUS mvBoardSDioWPControl(MV_BOOL mode); ++MV_32 mvBoarGpioPinNumGet(MV_BOARD_GPP_CLASS class, MV_U32 index); ++ ++MV_32 mvBoardNandWidthGet(void); ++MV_STATUS mvBoardFanPowerControl(MV_BOOL mode); ++MV_STATUS mvBoardHDDPowerControl(MV_BOOL mode); ++#endif /* __INCmvBoardEnvLibh */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,848 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++#include "mvCommon.h" ++#include "mvBoardEnvLib.h" ++#include "mvBoardEnvSpec.h" ++#include "twsi/mvTwsi.h" ++ ++#define DB_88F6281A_BOARD_PCI_IF_NUM 0x0 ++#define DB_88F6281A_BOARD_TWSI_DEF_NUM 0x7 ++#define DB_88F6281A_BOARD_MAC_INFO_NUM 0x2 ++#define DB_88F6281A_BOARD_GPP_INFO_NUM 0x3 ++#define DB_88F6281A_BOARD_MPP_CONFIG_NUM 0x1 ++#define DB_88F6281A_BOARD_MPP_GROUP_TYPE_NUM 0x1 ++#if defined(MV_NAND) && defined(MV_NAND_BOOT) ++ #define DB_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1 ++#elif defined(MV_NAND) && defined(MV_SPI_BOOT) ++ #define DB_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x2 ++#else ++ #define DB_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1 ++#endif ++#define DB_88F6281A_BOARD_DEBUG_LED_NUM 0x0 ++ ++ ++MV_BOARD_TWSI_INFO db88f6281AInfoBoardTwsiDev[] = ++ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ ++ { ++ {BOARD_DEV_TWSI_EXP, 0x20, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_EXP, 0x21, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_SATR, 0x4D, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_SATR, 0x4E, ADDR7_BIT}, ++ {BOARD_TWSI_AUDIO_DEC, 0x4A, ADDR7_BIT} ++ }; ++ ++MV_BOARD_MAC_INFO db88f6281AInfoBoardMacInfo[] = ++ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ ++ { ++ {BOARD_MAC_SPEED_AUTO, 0x8}, ++ {BOARD_MAC_SPEED_AUTO, 0x9} ++ }; ++ ++MV_BOARD_MPP_TYPE_INFO db88f6281AInfoBoardMppTypeInfo[] = ++ /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, ++ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ ++ {{MV_BOARD_AUTO, MV_BOARD_AUTO} ++ }; ++ ++MV_BOARD_GPP_INFO db88f6281AInfoBoardGppInfo[] = ++ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ ++ { ++ {BOARD_GPP_TSU_DIRCTION, 33} ++ /*muxed with TDM/Audio module via IOexpender ++ {BOARD_GPP_SDIO_DETECT, 38}, ++ {BOARD_GPP_USB_VBUS, 49}*/ ++ }; ++ ++MV_DEV_CS_INFO db88f6281AInfoBoardDeCsInfo[] = ++ /*{deviceCS, params, devType, devWidth}*/ ++#if defined(MV_NAND) && defined(MV_NAND_BOOT) ++ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ ++#elif defined(MV_NAND) && defined(MV_SPI_BOOT) ++ { ++ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ ++ {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ ++ }; ++#else ++ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ ++#endif ++ ++MV_BOARD_MPP_INFO db88f6281AInfoBoardMppConfigValue[] = ++ {{{ ++ DB_88F6281A_MPP0_7, ++ DB_88F6281A_MPP8_15, ++ DB_88F6281A_MPP16_23, ++ DB_88F6281A_MPP24_31, ++ DB_88F6281A_MPP32_39, ++ DB_88F6281A_MPP40_47, ++ DB_88F6281A_MPP48_55 ++ }}}; ++ ++ ++MV_BOARD_INFO db88f6281AInfo = { ++ "DB-88F6281A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ ++ DB_88F6281A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ ++ db88f6281AInfoBoardMppTypeInfo, ++ DB_88F6281A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ ++ db88f6281AInfoBoardMppConfigValue, ++ 0, /* intsGppMaskLow */ ++ 0, /* intsGppMaskHigh */ ++ DB_88F6281A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ ++ db88f6281AInfoBoardDeCsInfo, ++ DB_88F6281A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ ++ db88f6281AInfoBoardTwsiDev, ++ DB_88F6281A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ ++ db88f6281AInfoBoardMacInfo, ++ DB_88F6281A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ ++ db88f6281AInfoBoardGppInfo, ++ DB_88F6281A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ ++ NULL, ++ 0, /* ledsPolarity */ ++ DB_88F6281A_OE_LOW, /* gppOutEnLow */ ++ DB_88F6281A_OE_HIGH, /* gppOutEnHigh */ ++ DB_88F6281A_OE_VAL_LOW, /* gppOutValLow */ ++ DB_88F6281A_OE_VAL_HIGH, /* gppOutValHigh */ ++ 0, /* gppPolarityValLow */ ++ BIT6, /* gppPolarityValHigh */ ++ NULL /* pSwitchInfo */ ++}; ++ ++ ++#define RD_88F6281A_BOARD_PCI_IF_NUM 0x0 ++#define RD_88F6281A_BOARD_TWSI_DEF_NUM 0x2 ++#define RD_88F6281A_BOARD_MAC_INFO_NUM 0x2 ++#define RD_88F6281A_BOARD_GPP_INFO_NUM 0x5 ++#define RD_88F6281A_BOARD_MPP_GROUP_TYPE_NUM 0x1 ++#define RD_88F6281A_BOARD_MPP_CONFIG_NUM 0x1 ++#if defined(MV_NAND) && defined(MV_NAND_BOOT) ++ #define RD_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1 ++#elif defined(MV_NAND) && defined(MV_SPI_BOOT) ++ #define RD_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x2 ++#else ++ #define RD_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1 ++#endif ++#define RD_88F6281A_BOARD_DEBUG_LED_NUM 0x0 ++ ++MV_BOARD_MAC_INFO rd88f6281AInfoBoardMacInfo[] = ++ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ ++ {{BOARD_MAC_SPEED_1000M, 0xa}, ++ {BOARD_MAC_SPEED_AUTO, 0xb} ++ }; ++ ++MV_BOARD_SWITCH_INFO rd88f6281AInfoBoardSwitchInfo[] = ++ /* MV_32 linkStatusIrq, {MV_32 qdPort0, MV_32 qdPort1, MV_32 qdPort2, MV_32 qdPort3, MV_32 qdPort4}, ++ MV_32 qdCpuPort, MV_32 smiScanMode, MV_32 switchOnPort} */ ++ {{38, {0, 1, 2, 3, -1}, 5, 2, 0}, ++ {-1, {-1}, -1, -1, -1}}; ++ ++MV_BOARD_TWSI_INFO rd88f6281AInfoBoardTwsiDev[] = ++ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ ++ { ++ {BOARD_DEV_TWSI_EXP, 0xFF, ADDR7_BIT}, /* dummy entry to align with modules indexes */ ++ {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT} ++ }; ++ ++MV_BOARD_MPP_TYPE_INFO rd88f6281AInfoBoardMppTypeInfo[] = ++ {{MV_BOARD_RGMII, MV_BOARD_TDM} ++ }; ++ ++MV_DEV_CS_INFO rd88f6281AInfoBoardDeCsInfo[] = ++ /*{deviceCS, params, devType, devWidth}*/ ++#if defined(MV_NAND) && defined(MV_NAND_BOOT) ++ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ ++#elif defined(MV_NAND) && defined(MV_SPI_BOOT) ++ { ++ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ ++ {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ ++ }; ++#else ++ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ ++#endif ++ ++MV_BOARD_GPP_INFO rd88f6281AInfoBoardGppInfo[] = ++ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ ++ {{BOARD_GPP_SDIO_DETECT, 28}, ++ {BOARD_GPP_USB_OC, 29}, ++ {BOARD_GPP_WPS_BUTTON, 35}, ++ {BOARD_GPP_MV_SWITCH, 38}, ++ {BOARD_GPP_USB_VBUS, 49} ++ }; ++ ++MV_BOARD_MPP_INFO rd88f6281AInfoBoardMppConfigValue[] = ++ {{{ ++ RD_88F6281A_MPP0_7, ++ RD_88F6281A_MPP8_15, ++ RD_88F6281A_MPP16_23, ++ RD_88F6281A_MPP24_31, ++ RD_88F6281A_MPP32_39, ++ RD_88F6281A_MPP40_47, ++ RD_88F6281A_MPP48_55 ++ }}}; ++ ++MV_BOARD_INFO rd88f6281AInfo = { ++ "RD-88F6281A", /* boardName[MAX_BOARD_NAME_LEN] */ ++ RD_88F6281A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ ++ rd88f6281AInfoBoardMppTypeInfo, ++ RD_88F6281A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ ++ rd88f6281AInfoBoardMppConfigValue, ++ 0, /* intsGppMaskLow */ ++ (1 << 3), /* intsGppMaskHigh */ ++ RD_88F6281A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ ++ rd88f6281AInfoBoardDeCsInfo, ++ RD_88F6281A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ ++ rd88f6281AInfoBoardTwsiDev, ++ RD_88F6281A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ ++ rd88f6281AInfoBoardMacInfo, ++ RD_88F6281A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ ++ rd88f6281AInfoBoardGppInfo, ++ RD_88F6281A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ ++ NULL, ++ 0, /* ledsPolarity */ ++ RD_88F6281A_OE_LOW, /* gppOutEnLow */ ++ RD_88F6281A_OE_HIGH, /* gppOutEnHigh */ ++ RD_88F6281A_OE_VAL_LOW, /* gppOutValLow */ ++ RD_88F6281A_OE_VAL_HIGH, /* gppOutValHigh */ ++ 0, /* gppPolarityValLow */ ++ BIT6, /* gppPolarityValHigh */ ++ rd88f6281AInfoBoardSwitchInfo /* pSwitchInfo */ ++}; ++ ++ ++#define DB_88F6192A_BOARD_PCI_IF_NUM 0x0 ++#define DB_88F6192A_BOARD_TWSI_DEF_NUM 0x7 ++#define DB_88F6192A_BOARD_MAC_INFO_NUM 0x2 ++#define DB_88F6192A_BOARD_GPP_INFO_NUM 0x3 ++#define DB_88F6192A_BOARD_MPP_GROUP_TYPE_NUM 0x1 ++#define DB_88F6192A_BOARD_MPP_CONFIG_NUM 0x1 ++#if defined(MV_NAND) && defined(MV_NAND_BOOT) ++ #define DB_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x1 ++#elif defined(MV_NAND) && defined(MV_SPI_BOOT) ++ #define DB_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x2 ++#else ++ #define DB_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x1 ++#endif ++#define DB_88F6192A_BOARD_DEBUG_LED_NUM 0x0 ++ ++MV_BOARD_TWSI_INFO db88f6192AInfoBoardTwsiDev[] = ++ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ ++ { ++ {BOARD_DEV_TWSI_EXP, 0x20, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_EXP, 0x21, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_SATR, 0x4D, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_SATR, 0x4E, ADDR7_BIT}, ++ {BOARD_TWSI_AUDIO_DEC, 0x4A, ADDR7_BIT} ++ }; ++ ++MV_BOARD_MAC_INFO db88f6192AInfoBoardMacInfo[] = ++ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ ++ { ++ {BOARD_MAC_SPEED_AUTO, 0x8}, ++ {BOARD_MAC_SPEED_AUTO, 0x9} ++ }; ++ ++MV_BOARD_MPP_TYPE_INFO db88f6192AInfoBoardMppTypeInfo[] = ++ /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, ++ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ ++ {{MV_BOARD_AUTO, MV_BOARD_OTHER} ++ }; ++ ++MV_DEV_CS_INFO db88f6192AInfoBoardDeCsInfo[] = ++ /*{deviceCS, params, devType, devWidth}*/ ++#if defined(MV_NAND) && defined(MV_NAND_BOOT) ++ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ ++#elif defined(MV_NAND) && defined(MV_SPI_BOOT) ++ { ++ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ ++ {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ ++ }; ++#else ++ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ ++#endif ++ ++MV_BOARD_GPP_INFO db88f6192AInfoBoardGppInfo[] = ++ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ ++ { ++ {BOARD_GPP_SDIO_WP, 20}, ++ {BOARD_GPP_USB_VBUS, 22}, ++ {BOARD_GPP_SDIO_DETECT, 23}, ++ }; ++ ++MV_BOARD_MPP_INFO db88f6192AInfoBoardMppConfigValue[] = ++ {{{ ++ DB_88F6192A_MPP0_7, ++ DB_88F6192A_MPP8_15, ++ DB_88F6192A_MPP16_23, ++ DB_88F6192A_MPP24_31, ++ DB_88F6192A_MPP32_35 ++ }}}; ++ ++MV_BOARD_INFO db88f6192AInfo = { ++ "DB-88F6192A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ ++ DB_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ ++ db88f6192AInfoBoardMppTypeInfo, ++ DB_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ ++ db88f6192AInfoBoardMppConfigValue, ++ 0, /* intsGppMaskLow */ ++ (1 << 3), /* intsGppMaskHigh */ ++ DB_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ ++ db88f6192AInfoBoardDeCsInfo, ++ DB_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ ++ db88f6192AInfoBoardTwsiDev, ++ DB_88F6192A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ ++ db88f6192AInfoBoardMacInfo, ++ DB_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ ++ db88f6192AInfoBoardGppInfo, ++ DB_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ ++ NULL, ++ 0, /* ledsPolarity */ ++ DB_88F6192A_OE_LOW, /* gppOutEnLow */ ++ DB_88F6192A_OE_HIGH, /* gppOutEnHigh */ ++ DB_88F6192A_OE_VAL_LOW, /* gppOutValLow */ ++ DB_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */ ++ 0, /* gppPolarityValLow */ ++ 0, /* gppPolarityValHigh */ ++ NULL /* pSwitchInfo */ ++}; ++ ++#define DB_88F6190A_BOARD_MAC_INFO_NUM 0x1 ++ ++MV_BOARD_INFO db88f6190AInfo = { ++ "DB-88F6190A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ ++ DB_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ ++ db88f6192AInfoBoardMppTypeInfo, ++ DB_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ ++ db88f6192AInfoBoardMppConfigValue, ++ 0, /* intsGppMaskLow */ ++ (1 << 3), /* intsGppMaskHigh */ ++ DB_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ ++ db88f6192AInfoBoardDeCsInfo, ++ DB_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ ++ db88f6192AInfoBoardTwsiDev, ++ DB_88F6190A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ ++ db88f6192AInfoBoardMacInfo, ++ DB_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ ++ db88f6192AInfoBoardGppInfo, ++ DB_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ ++ NULL, ++ 0, /* ledsPolarity */ ++ DB_88F6192A_OE_LOW, /* gppOutEnLow */ ++ DB_88F6192A_OE_HIGH, /* gppOutEnHigh */ ++ DB_88F6192A_OE_VAL_LOW, /* gppOutValLow */ ++ DB_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */ ++ 0, /* gppPolarityValLow */ ++ 0, /* gppPolarityValHigh */ ++ NULL /* pSwitchInfo */ ++}; ++ ++#define RD_88F6192A_BOARD_PCI_IF_NUM 0x0 ++#define RD_88F6192A_BOARD_TWSI_DEF_NUM 0x0 ++#define RD_88F6192A_BOARD_MAC_INFO_NUM 0x1 ++#define RD_88F6192A_BOARD_GPP_INFO_NUM 0xE ++#define RD_88F6192A_BOARD_MPP_GROUP_TYPE_NUM 0x1 ++#define RD_88F6192A_BOARD_MPP_CONFIG_NUM 0x1 ++#define RD_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x1 ++#define RD_88F6192A_BOARD_DEBUG_LED_NUM 0x3 ++ ++MV_U8 rd88f6192AInfoBoardDebugLedIf[] = ++ {17, 28, 29}; ++ ++MV_BOARD_MAC_INFO rd88f6192AInfoBoardMacInfo[] = ++ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ ++ {{BOARD_MAC_SPEED_AUTO, 0x8} ++ }; ++ ++MV_BOARD_MPP_TYPE_INFO rd88f6192AInfoBoardMppTypeInfo[] = ++ /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, ++ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ ++ {{MV_BOARD_OTHER, MV_BOARD_OTHER} ++ }; ++ ++MV_DEV_CS_INFO rd88f6192AInfoBoardDeCsInfo[] = ++ /*{deviceCS, params, devType, devWidth}*/ ++ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ ++ ++MV_BOARD_GPP_INFO rd88f6192AInfoBoardGppInfo[] = ++ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ ++ { ++ {BOARD_GPP_USB_VBUS_EN, 10}, ++ {BOARD_GPP_USB_HOST_DEVICE, 11}, ++ {BOARD_GPP_RESET, 14}, ++ {BOARD_GPP_POWER_ON_LED, 15}, ++ {BOARD_GPP_HDD_POWER, 16}, ++ {BOARD_GPP_WPS_BUTTON, 24}, ++ {BOARD_GPP_TS_BUTTON_C, 25}, ++ {BOARD_GPP_USB_VBUS, 26}, ++ {BOARD_GPP_USB_OC, 27}, ++ {BOARD_GPP_TS_BUTTON_U, 30}, ++ {BOARD_GPP_TS_BUTTON_R, 31}, ++ {BOARD_GPP_TS_BUTTON_L, 32}, ++ {BOARD_GPP_TS_BUTTON_D, 34}, ++ {BOARD_GPP_FAN_POWER, 35} ++ }; ++ ++MV_BOARD_MPP_INFO rd88f6192AInfoBoardMppConfigValue[] = ++ {{{ ++ RD_88F6192A_MPP0_7, ++ RD_88F6192A_MPP8_15, ++ RD_88F6192A_MPP16_23, ++ RD_88F6192A_MPP24_31, ++ RD_88F6192A_MPP32_35 ++ }}}; ++ ++MV_BOARD_INFO rd88f6192AInfo = { ++ "RD-88F6192A-NAS", /* boardName[MAX_BOARD_NAME_LEN] */ ++ RD_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ ++ rd88f6192AInfoBoardMppTypeInfo, ++ RD_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ ++ rd88f6192AInfoBoardMppConfigValue, ++ 0, /* intsGppMaskLow */ ++ (1 << 3), /* intsGppMaskHigh */ ++ RD_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ ++ rd88f6192AInfoBoardDeCsInfo, ++ RD_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ ++ NULL, ++ RD_88F6192A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ ++ rd88f6192AInfoBoardMacInfo, ++ RD_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ ++ rd88f6192AInfoBoardGppInfo, ++ RD_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ ++ rd88f6192AInfoBoardDebugLedIf, ++ 0, /* ledsPolarity */ ++ RD_88F6192A_OE_LOW, /* gppOutEnLow */ ++ RD_88F6192A_OE_HIGH, /* gppOutEnHigh */ ++ RD_88F6192A_OE_VAL_LOW, /* gppOutValLow */ ++ RD_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */ ++ 0, /* gppPolarityValLow */ ++ 0, /* gppPolarityValHigh */ ++ NULL /* pSwitchInfo */ ++}; ++ ++MV_BOARD_INFO rd88f6190AInfo = { ++ "RD-88F6190A-NAS", /* boardName[MAX_BOARD_NAME_LEN] */ ++ RD_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ ++ rd88f6192AInfoBoardMppTypeInfo, ++ RD_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ ++ rd88f6192AInfoBoardMppConfigValue, ++ 0, /* intsGppMaskLow */ ++ (1 << 3), /* intsGppMaskHigh */ ++ RD_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ ++ rd88f6192AInfoBoardDeCsInfo, ++ RD_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ ++ NULL, ++ RD_88F6192A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ ++ rd88f6192AInfoBoardMacInfo, ++ RD_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ ++ rd88f6192AInfoBoardGppInfo, ++ RD_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ ++ rd88f6192AInfoBoardDebugLedIf, ++ 0, /* ledsPolarity */ ++ RD_88F6192A_OE_LOW, /* gppOutEnLow */ ++ RD_88F6192A_OE_HIGH, /* gppOutEnHigh */ ++ RD_88F6192A_OE_VAL_LOW, /* gppOutValLow */ ++ RD_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */ ++ 0, /* gppPolarityValLow */ ++ 0, /* gppPolarityValHigh */ ++ NULL /* pSwitchInfo */ ++}; ++ ++#define DB_88F6180A_BOARD_PCI_IF_NUM 0x0 ++#define DB_88F6180A_BOARD_TWSI_DEF_NUM 0x5 ++#define DB_88F6180A_BOARD_MAC_INFO_NUM 0x1 ++#define DB_88F6180A_BOARD_GPP_INFO_NUM 0x0 ++#define DB_88F6180A_BOARD_MPP_GROUP_TYPE_NUM 0x2 ++#define DB_88F6180A_BOARD_MPP_CONFIG_NUM 0x1 ++#define DB_88F6180A_BOARD_DEVICE_CONFIG_NUM 0x1 ++#define DB_88F6180A_BOARD_DEBUG_LED_NUM 0x0 ++ ++MV_BOARD_TWSI_INFO db88f6180AInfoBoardTwsiDev[] = ++ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ ++ { ++ {BOARD_DEV_TWSI_EXP, 0x20, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_EXP, 0x21, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, ++ {BOARD_TWSI_AUDIO_DEC, 0x4A, ADDR7_BIT} ++ }; ++ ++MV_BOARD_MAC_INFO db88f6180AInfoBoardMacInfo[] = ++ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ ++ {{BOARD_MAC_SPEED_AUTO, 0x8} ++ }; ++ ++MV_BOARD_GPP_INFO db88f6180AInfoBoardGppInfo[] = ++ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ ++ { ++ /* Muxed with TDM/Audio module via IOexpender ++ {BOARD_GPP_USB_VBUS, 6} */ ++ }; ++ ++MV_BOARD_MPP_TYPE_INFO db88f6180AInfoBoardMppTypeInfo[] = ++ /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, ++ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ ++ {{MV_BOARD_OTHER, MV_BOARD_AUTO} ++ }; ++ ++MV_DEV_CS_INFO db88f6180AInfoBoardDeCsInfo[] = ++ /*{deviceCS, params, devType, devWidth}*/ ++#if defined(MV_NAND_BOOT) ++ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ ++#else ++ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ ++#endif ++ ++MV_BOARD_MPP_INFO db88f6180AInfoBoardMppConfigValue[] = ++ {{{ ++ DB_88F6180A_MPP0_7, ++ DB_88F6180A_MPP8_15, ++ DB_88F6180A_MPP16_23, ++ DB_88F6180A_MPP24_31, ++ DB_88F6180A_MPP32_39, ++ DB_88F6180A_MPP40_44 ++ }}}; ++ ++MV_BOARD_INFO db88f6180AInfo = { ++ "DB-88F6180A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ ++ DB_88F6180A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ ++ db88f6180AInfoBoardMppTypeInfo, ++ DB_88F6180A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ ++ db88f6180AInfoBoardMppConfigValue, ++ 0, /* intsGppMaskLow */ ++ 0, /* intsGppMaskHigh */ ++ DB_88F6180A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ ++ db88f6180AInfoBoardDeCsInfo, ++ DB_88F6180A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ ++ db88f6180AInfoBoardTwsiDev, ++ DB_88F6180A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ ++ db88f6180AInfoBoardMacInfo, ++ DB_88F6180A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ ++ NULL, ++ DB_88F6180A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ ++ NULL, ++ 0, /* ledsPolarity */ ++ DB_88F6180A_OE_LOW, /* gppOutEnLow */ ++ DB_88F6180A_OE_HIGH, /* gppOutEnHigh */ ++ DB_88F6180A_OE_VAL_LOW, /* gppOutValLow */ ++ DB_88F6180A_OE_VAL_HIGH, /* gppOutValHigh */ ++ 0, /* gppPolarityValLow */ ++ 0, /* gppPolarityValHigh */ ++ NULL /* pSwitchInfo */ ++}; ++ ++ ++#define RD_88F6281A_PCAC_BOARD_PCI_IF_NUM 0x0 ++#define RD_88F6281A_PCAC_BOARD_TWSI_DEF_NUM 0x1 ++#define RD_88F6281A_PCAC_BOARD_MAC_INFO_NUM 0x1 ++#define RD_88F6281A_PCAC_BOARD_GPP_INFO_NUM 0x0 ++#define RD_88F6281A_PCAC_BOARD_MPP_GROUP_TYPE_NUM 0x1 ++#define RD_88F6281A_PCAC_BOARD_MPP_CONFIG_NUM 0x1 ++#if defined(MV_NAND) && defined(MV_NAND_BOOT) ++ #define RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM 0x1 ++#elif defined(MV_NAND) && defined(MV_SPI_BOOT) ++ #define RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM 0x2 ++#else ++ #define RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM 0x1 ++#endif ++#define RD_88F6281A_PCAC_BOARD_DEBUG_LED_NUM 0x4 ++ ++MV_U8 rd88f6281APcacInfoBoardDebugLedIf[] = ++ {38, 39, 40, 41}; ++ ++MV_BOARD_MAC_INFO rd88f6281APcacInfoBoardMacInfo[] = ++ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ ++ {{BOARD_MAC_SPEED_AUTO, 0x8} ++ }; ++ ++MV_BOARD_TWSI_INFO rd88f6281APcacInfoBoardTwsiDev[] = ++ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ ++ { ++ {BOARD_TWSI_OTHER, 0xa7, ADDR7_BIT} ++ }; ++ ++MV_BOARD_MPP_TYPE_INFO rd88f6281APcacInfoBoardMppTypeInfo[] = ++ {{MV_BOARD_OTHER, MV_BOARD_OTHER} ++ }; ++ ++MV_DEV_CS_INFO rd88f6281APcacInfoBoardDeCsInfo[] = ++ /*{deviceCS, params, devType, devWidth}*/ ++#if defined(MV_NAND) && defined(MV_NAND_BOOT) ++ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ ++#elif defined(MV_NAND) && defined(MV_SPI_BOOT) ++ { ++ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ ++ {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ ++ }; ++#else ++ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ ++#endif ++ ++MV_BOARD_MPP_INFO rd88f6281APcacInfoBoardMppConfigValue[] = ++ {{{ ++ RD_88F6281A_PCAC_MPP0_7, ++ RD_88F6281A_PCAC_MPP8_15, ++ RD_88F6281A_PCAC_MPP16_23, ++ RD_88F6281A_PCAC_MPP24_31, ++ RD_88F6281A_PCAC_MPP32_39, ++ RD_88F6281A_PCAC_MPP40_47, ++ RD_88F6281A_PCAC_MPP48_55 ++ }}}; ++ ++MV_BOARD_INFO rd88f6281APcacInfo = { ++ "RD-88F6281A-PCAC", /* boardName[MAX_BOARD_NAME_LEN] */ ++ RD_88F6281A_PCAC_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ ++ rd88f6281APcacInfoBoardMppTypeInfo, ++ RD_88F6281A_PCAC_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ ++ rd88f6281APcacInfoBoardMppConfigValue, ++ 0, /* intsGppMaskLow */ ++ (1 << 3), /* intsGppMaskHigh */ ++ RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ ++ rd88f6281APcacInfoBoardDeCsInfo, ++ RD_88F6281A_PCAC_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ ++ rd88f6281APcacInfoBoardTwsiDev, ++ RD_88F6281A_PCAC_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ ++ rd88f6281APcacInfoBoardMacInfo, ++ RD_88F6281A_PCAC_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ ++ 0, ++ RD_88F6281A_PCAC_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ ++ NULL, ++ 0, /* ledsPolarity */ ++ RD_88F6281A_PCAC_OE_LOW, /* gppOutEnLow */ ++ RD_88F6281A_PCAC_OE_HIGH, /* gppOutEnHigh */ ++ RD_88F6281A_PCAC_OE_VAL_LOW, /* gppOutValLow */ ++ RD_88F6281A_PCAC_OE_VAL_HIGH, /* gppOutValHigh */ ++ 0, /* gppPolarityValLow */ ++ 0, /* gppPolarityValHigh */ ++ NULL /* pSwitchInfo */ ++}; ++ ++ ++/* 6281 Sheeva Plug*/ ++ ++#define SHEEVA_PLUG_BOARD_PCI_IF_NUM 0x0 ++#define SHEEVA_PLUG_BOARD_TWSI_DEF_NUM 0x0 ++#define SHEEVA_PLUG_BOARD_MAC_INFO_NUM 0x1 ++#define SHEEVA_PLUG_BOARD_GPP_INFO_NUM 0x0 ++#define SHEEVA_PLUG_BOARD_MPP_GROUP_TYPE_NUN 0x1 ++#define SHEEVA_PLUG_BOARD_MPP_CONFIG_NUM 0x1 ++#define SHEEVA_PLUG_BOARD_DEVICE_CONFIG_NUM 0x1 ++#define SHEEVA_PLUG_BOARD_DEBUG_LED_NUM 0x1 ++ ++MV_U8 sheevaPlugInfoBoardDebugLedIf[] = ++ {49}; ++ ++MV_BOARD_MAC_INFO sheevaPlugInfoBoardMacInfo[] = ++ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ ++ {{BOARD_MAC_SPEED_AUTO, 0x0}}; ++ ++MV_BOARD_TWSI_INFO sheevaPlugInfoBoardTwsiDev[] = ++ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ ++ {{BOARD_TWSI_OTHER, 0x0, ADDR7_BIT}}; ++ ++MV_BOARD_MPP_TYPE_INFO sheevaPlugInfoBoardMppTypeInfo[] = ++ {{MV_BOARD_OTHER, MV_BOARD_OTHER} ++ }; ++ ++MV_DEV_CS_INFO sheevaPlugInfoBoardDeCsInfo[] = ++ /*{deviceCS, params, devType, devWidth}*/ ++ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ ++ ++MV_BOARD_MPP_INFO sheevaPlugInfoBoardMppConfigValue[] = ++ {{{ ++ RD_SHEEVA_PLUG_MPP0_7, ++ RD_SHEEVA_PLUG_MPP8_15, ++ RD_SHEEVA_PLUG_MPP16_23, ++ RD_SHEEVA_PLUG_MPP24_31, ++ RD_SHEEVA_PLUG_MPP32_39, ++ RD_SHEEVA_PLUG_MPP40_47, ++ RD_SHEEVA_PLUG_MPP48_55 ++ }}}; ++ ++MV_BOARD_INFO sheevaPlugInfo = { ++ "SHEEVA PLUG", /* boardName[MAX_BOARD_NAME_LEN] */ ++ SHEEVA_PLUG_BOARD_MPP_GROUP_TYPE_NUN, /* numBoardMppGroupType */ ++ sheevaPlugInfoBoardMppTypeInfo, ++ SHEEVA_PLUG_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ ++ sheevaPlugInfoBoardMppConfigValue, ++ 0, /* intsGppMaskLow */ ++ 0, /* intsGppMaskHigh */ ++ SHEEVA_PLUG_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ ++ sheevaPlugInfoBoardDeCsInfo, ++ SHEEVA_PLUG_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ ++ sheevaPlugInfoBoardTwsiDev, ++ SHEEVA_PLUG_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ ++ sheevaPlugInfoBoardMacInfo, ++ SHEEVA_PLUG_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ ++ 0, ++ SHEEVA_PLUG_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ ++ sheevaPlugInfoBoardDebugLedIf, ++ 0, /* ledsPolarity */ ++ RD_SHEEVA_PLUG_OE_LOW, /* gppOutEnLow */ ++ RD_SHEEVA_PLUG_OE_HIGH, /* gppOutEnHigh */ ++ RD_SHEEVA_PLUG_OE_VAL_LOW, /* gppOutValLow */ ++ RD_SHEEVA_PLUG_OE_VAL_HIGH, /* gppOutValHigh */ ++ 0, /* gppPolarityValLow */ ++ 0, /* gppPolarityValHigh */ ++ NULL /* pSwitchInfo */ ++}; ++ ++/* Customer specific board place holder*/ ++ ++#define DB_CUSTOMER_BOARD_PCI_IF_NUM 0x0 ++#define DB_CUSTOMER_BOARD_TWSI_DEF_NUM 0x0 ++#define DB_CUSTOMER_BOARD_MAC_INFO_NUM 0x0 ++#define DB_CUSTOMER_BOARD_GPP_INFO_NUM 0x0 ++#define DB_CUSTOMER_BOARD_MPP_GROUP_TYPE_NUN 0x0 ++#define DB_CUSTOMER_BOARD_MPP_CONFIG_NUM 0x0 ++#if defined(MV_NAND) && defined(MV_NAND_BOOT) ++ #define DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM 0x0 ++#elif defined(MV_NAND) && defined(MV_SPI_BOOT) ++ #define DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM 0x0 ++#else ++ #define DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM 0x0 ++#endif ++#define DB_CUSTOMER_BOARD_DEBUG_LED_NUM 0x0 ++ ++MV_U8 dbCustomerInfoBoardDebugLedIf[] = ++ {0}; ++ ++MV_BOARD_MAC_INFO dbCustomerInfoBoardMacInfo[] = ++ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ ++ {{BOARD_MAC_SPEED_AUTO, 0x0}}; ++ ++MV_BOARD_TWSI_INFO dbCustomerInfoBoardTwsiDev[] = ++ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ ++ {{BOARD_TWSI_OTHER, 0x0, ADDR7_BIT}}; ++ ++MV_BOARD_MPP_TYPE_INFO dbCustomerInfoBoardMppTypeInfo[] = ++ {{MV_BOARD_OTHER, MV_BOARD_OTHER} ++ }; ++ ++MV_DEV_CS_INFO dbCustomerInfoBoardDeCsInfo[] = ++ /*{deviceCS, params, devType, devWidth}*/ ++#if defined(MV_NAND) && defined(MV_NAND_BOOT) ++ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ ++#elif defined(MV_NAND) && defined(MV_SPI_BOOT) ++ { ++ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ ++ {2, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ ++ }; ++#else ++ {{2, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ ++#endif ++ ++MV_BOARD_MPP_INFO dbCustomerInfoBoardMppConfigValue[] = ++ {{{ ++ DB_CUSTOMER_MPP0_7, ++ DB_CUSTOMER_MPP8_15, ++ DB_CUSTOMER_MPP16_23, ++ DB_CUSTOMER_MPP24_31, ++ DB_CUSTOMER_MPP32_39, ++ DB_CUSTOMER_MPP40_47, ++ DB_CUSTOMER_MPP48_55 ++ }}}; ++ ++MV_BOARD_INFO dbCustomerInfo = { ++ "DB-CUSTOMER", /* boardName[MAX_BOARD_NAME_LEN] */ ++ DB_CUSTOMER_BOARD_MPP_GROUP_TYPE_NUN, /* numBoardMppGroupType */ ++ dbCustomerInfoBoardMppTypeInfo, ++ DB_CUSTOMER_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ ++ dbCustomerInfoBoardMppConfigValue, ++ 0, /* intsGppMaskLow */ ++ 0, /* intsGppMaskHigh */ ++ DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ ++ dbCustomerInfoBoardDeCsInfo, ++ DB_CUSTOMER_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ ++ dbCustomerInfoBoardTwsiDev, ++ DB_CUSTOMER_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ ++ dbCustomerInfoBoardMacInfo, ++ DB_CUSTOMER_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ ++ 0, ++ DB_CUSTOMER_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ ++ NULL, ++ 0, /* ledsPolarity */ ++ DB_CUSTOMER_OE_LOW, /* gppOutEnLow */ ++ DB_CUSTOMER_OE_HIGH, /* gppOutEnHigh */ ++ DB_CUSTOMER_OE_VAL_LOW, /* gppOutValLow */ ++ DB_CUSTOMER_OE_VAL_HIGH, /* gppOutValHigh */ ++ 0, /* gppPolarityValLow */ ++ 0, /* gppPolarityValHigh */ ++ NULL /* pSwitchInfo */ ++}; ++ ++MV_BOARD_INFO* boardInfoTbl[] = { ++ &db88f6281AInfo, ++ &rd88f6281AInfo, ++ &db88f6192AInfo, ++ &rd88f6192AInfo, ++ &db88f6180AInfo, ++ &db88f6190AInfo, ++ &rd88f6190AInfo, ++ &rd88f6281APcacInfo, ++ &dbCustomerInfo, ++ &sheevaPlugInfo ++ }; ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,262 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvBoardEnvSpech ++#define __INCmvBoardEnvSpech ++ ++#include "mvSysHwConfig.h" ++ ++ ++/* For future use */ ++#define BD_ID_DATA_START_OFFS 0x0 ++#define BD_DETECT_SEQ_OFFS 0x0 ++#define BD_SYS_NUM_OFFS 0x4 ++#define BD_NAME_OFFS 0x8 ++ ++/* I2C bus addresses */ ++#define MV_BOARD_CTRL_I2C_ADDR 0x0 /* Controller slave addr */ ++#define MV_BOARD_CTRL_I2C_ADDR_TYPE ADDR7_BIT ++#define MV_BOARD_DIMM0_I2C_ADDR 0x56 ++#define MV_BOARD_DIMM0_I2C_ADDR_TYPE ADDR7_BIT ++#define MV_BOARD_DIMM1_I2C_ADDR 0x54 ++#define MV_BOARD_DIMM1_I2C_ADDR_TYPE ADDR7_BIT ++#define MV_BOARD_EEPROM_I2C_ADDR 0x51 ++#define MV_BOARD_EEPROM_I2C_ADDR_TYPE ADDR7_BIT ++#define MV_BOARD_MAIN_EEPROM_I2C_ADDR 0x50 ++#define MV_BOARD_MAIN_EEPROM_I2C_ADDR_TYPE ADDR7_BIT ++#define MV_BOARD_MUX_I2C_ADDR_ENTRY 0x2 ++#define MV_BOARD_DIMM_I2C_CHANNEL 0x0 ++ ++#define BOOT_FLASH_INDEX 0 ++#define MAIN_FLASH_INDEX 1 ++ ++#define BOARD_ETH_START_PORT_NUM 0 ++ ++/* Supported clocks */ ++#define MV_BOARD_TCLK_100MHZ 100000000 ++#define MV_BOARD_TCLK_125MHZ 125000000 ++#define MV_BOARD_TCLK_133MHZ 133333333 ++#define MV_BOARD_TCLK_150MHZ 150000000 ++#define MV_BOARD_TCLK_166MHZ 166666667 ++#define MV_BOARD_TCLK_200MHZ 200000000 ++ ++#define MV_BOARD_SYSCLK_100MHZ 100000000 ++#define MV_BOARD_SYSCLK_125MHZ 125000000 ++#define MV_BOARD_SYSCLK_133MHZ 133333333 ++#define MV_BOARD_SYSCLK_150MHZ 150000000 ++#define MV_BOARD_SYSCLK_166MHZ 166666667 ++#define MV_BOARD_SYSCLK_200MHZ 200000000 ++#define MV_BOARD_SYSCLK_233MHZ 233333333 ++#define MV_BOARD_SYSCLK_250MHZ 250000000 ++#define MV_BOARD_SYSCLK_267MHZ 266666667 ++#define MV_BOARD_SYSCLK_300MHZ 300000000 ++#define MV_BOARD_SYSCLK_333MHZ 333333334 ++#define MV_BOARD_SYSCLK_400MHZ 400000000 ++ ++#define MV_BOARD_REFCLK_25MHZ 25000000 ++ ++/* Board specific */ ++/* =============================== */ ++ ++/* boards ID numbers */ ++ ++#define BOARD_ID_BASE 0x0 ++ ++/* New board ID numbers */ ++#define DB_88F6281A_BP_ID (BOARD_ID_BASE) ++#define DB_88F6281_BP_MLL_ID 1680 ++#define RD_88F6281A_ID (BOARD_ID_BASE+0x1) ++#define RD_88F6281_MLL_ID 1682 ++#define DB_88F6192A_BP_ID (BOARD_ID_BASE+0x2) ++#define RD_88F6192A_ID (BOARD_ID_BASE+0x3) ++#define RD_88F6192_MLL_ID 1681 ++#define DB_88F6180A_BP_ID (BOARD_ID_BASE+0x4) ++#define DB_88F6190A_BP_ID (BOARD_ID_BASE+0x5) ++#define RD_88F6190A_ID (BOARD_ID_BASE+0x6) ++#define RD_88F6281A_PCAC_ID (BOARD_ID_BASE+0x7) ++#define DB_CUSTOMER_ID (BOARD_ID_BASE+0x8) ++#define SHEEVA_PLUG_ID (BOARD_ID_BASE+0x9) ++#define MV_MAX_BOARD_ID (SHEEVA_PLUG_ID + 1) ++ ++/* DB-88F6281A-BP */ ++#if defined(MV_NAND) ++ #define DB_88F6281A_MPP0_7 0x21111111 ++#else ++ #define DB_88F6281A_MPP0_7 0x21112220 ++#endif ++#define DB_88F6281A_MPP8_15 0x11113311 ++#define DB_88F6281A_MPP16_23 0x00551111 ++#define DB_88F6281A_MPP24_31 0x00000000 ++#define DB_88F6281A_MPP32_39 0x00000000 ++#define DB_88F6281A_MPP40_47 0x00000000 ++#define DB_88F6281A_MPP48_55 0x00000000 ++#define DB_88F6281A_OE_LOW 0x0 ++#if defined(MV_TDM_5CHANNELS) ++ #define DB_88F6281A_OE_HIGH (BIT6) ++#else ++#define DB_88F6281A_OE_HIGH 0x0 ++#endif ++#define DB_88F6281A_OE_VAL_LOW 0x0 ++#define DB_88F6281A_OE_VAL_HIGH 0x0 ++ ++/* RD-88F6281A */ ++#if defined(MV_NAND) ++ #define RD_88F6281A_MPP0_7 0x21111111 ++#else ++ #define RD_88F6281A_MPP0_7 0x21112220 ++#endif ++#define RD_88F6281A_MPP8_15 0x11113311 ++#define RD_88F6281A_MPP16_23 0x33331111 ++#define RD_88F6281A_MPP24_31 0x33003333 ++#define RD_88F6281A_MPP32_39 0x20440533 ++#define RD_88F6281A_MPP40_47 0x22202222 ++#define RD_88F6281A_MPP48_55 0x00000002 ++#define RD_88F6281A_OE_LOW (BIT28 | BIT29) ++#define RD_88F6281A_OE_HIGH (BIT3 | BIT6 | BIT17) ++#define RD_88F6281A_OE_VAL_LOW 0x0 ++#define RD_88F6281A_OE_VAL_HIGH 0x0 ++ ++/* DB-88F6192A-BP */ ++#if defined(MV_NAND) ++ #define DB_88F6192A_MPP0_7 0x21111111 ++#else ++ #define DB_88F6192A_MPP0_7 0x21112220 ++#endif ++#define DB_88F6192A_MPP8_15 0x11113311 ++#define DB_88F6192A_MPP16_23 0x00501111 ++#define DB_88F6192A_MPP24_31 0x00000000 ++#define DB_88F6192A_MPP32_35 0x00000000 ++#define DB_88F6192A_OE_LOW (BIT22 | BIT23) ++#define DB_88F6192A_OE_HIGH 0x0 ++#define DB_88F6192A_OE_VAL_LOW 0x0 ++#define DB_88F6192A_OE_VAL_HIGH 0x0 ++ ++/* RD-88F6192A */ ++#define RD_88F6192A_MPP0_7 0x01222222 ++#define RD_88F6192A_MPP8_15 0x00000011 ++#define RD_88F6192A_MPP16_23 0x05550000 ++#define RD_88F6192A_MPP24_31 0x0 ++#define RD_88F6192A_MPP32_35 0x0 ++#define RD_88F6192A_OE_LOW (BIT11 | BIT14 | BIT24 | BIT25 | BIT26 | BIT27 | BIT30 | BIT31) ++#define RD_88F6192A_OE_HIGH (BIT0 | BIT2) ++#define RD_88F6192A_OE_VAL_LOW 0x18400 ++#define RD_88F6192A_OE_VAL_HIGH 0x8 ++ ++/* DB-88F6180A-BP */ ++#if defined(MV_NAND) ++ #define DB_88F6180A_MPP0_7 0x21111111 ++#else ++ #define DB_88F6180A_MPP0_7 0x01112222 ++#endif ++#define DB_88F6180A_MPP8_15 0x11113311 ++#define DB_88F6180A_MPP16_23 0x00001111 ++#define DB_88F6180A_MPP24_31 0x0 ++#define DB_88F6180A_MPP32_39 0x4444c000 ++#define DB_88F6180A_MPP40_44 0x00044444 ++#define DB_88F6180A_OE_LOW 0x0 ++#define DB_88F6180A_OE_HIGH 0x0 ++#define DB_88F6180A_OE_VAL_LOW 0x0 ++#define DB_88F6180A_OE_VAL_HIGH 0x0 ++ ++/* RD-88F6281A_PCAC */ ++#define RD_88F6281A_PCAC_MPP0_7 0x21111111 ++#define RD_88F6281A_PCAC_MPP8_15 0x00003311 ++#define RD_88F6281A_PCAC_MPP16_23 0x00001100 ++#define RD_88F6281A_PCAC_MPP24_31 0x00000000 ++#define RD_88F6281A_PCAC_MPP32_39 0x00000000 ++#define RD_88F6281A_PCAC_MPP40_47 0x00000000 ++#define RD_88F6281A_PCAC_MPP48_55 0x00000000 ++#define RD_88F6281A_PCAC_OE_LOW 0x0 ++#define RD_88F6281A_PCAC_OE_HIGH 0x0 ++#define RD_88F6281A_PCAC_OE_VAL_LOW 0x0 ++#define RD_88F6281A_PCAC_OE_VAL_HIGH 0x0 ++ ++/* SHEEVA PLUG */ ++#define RD_SHEEVA_PLUG_MPP0_7 0x01111111 ++#define RD_SHEEVA_PLUG_MPP8_15 0x11113322 ++#define RD_SHEEVA_PLUG_MPP16_23 0x00001111 ++#define RD_SHEEVA_PLUG_MPP24_31 0x00100000 ++#define RD_SHEEVA_PLUG_MPP32_39 0x00000000 ++#define RD_SHEEVA_PLUG_MPP40_47 0x00000000 ++#define RD_SHEEVA_PLUG_MPP48_55 0x00000000 ++#define RD_SHEEVA_PLUG_OE_LOW 0x0 ++#define RD_SHEEVA_PLUG_OE_HIGH 0x0 ++#define RD_SHEEVA_PLUG_OE_VAL_LOW (BIT29) ++#define RD_SHEEVA_PLUG_OE_VAL_HIGH ((~(BIT17 | BIT16 | BIT15)) | BIT14) ++ ++/* DB-CUSTOMER */ ++#define DB_CUSTOMER_MPP0_7 0x21111111 ++#define DB_CUSTOMER_MPP8_15 0x00003311 ++#define DB_CUSTOMER_MPP16_23 0x00001100 ++#define DB_CUSTOMER_MPP24_31 0x00000000 ++#define DB_CUSTOMER_MPP32_39 0x00000000 ++#define DB_CUSTOMER_MPP40_47 0x00000000 ++#define DB_CUSTOMER_MPP48_55 0x00000000 ++#define DB_CUSTOMER_OE_LOW 0x0 ++#define DB_CUSTOMER_OE_HIGH (~((BIT6) | (BIT7) | (BIT8) | (BIT9))) ++#define DB_CUSTOMER_OE_VAL_LOW 0x0 ++#define DB_CUSTOMER_OE_VAL_HIGH 0x0 ++ ++#endif /* __INCmvBoardEnvSpech */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,320 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#include "cpu/mvCpu.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "ctrlEnv/mvCtrlEnvRegs.h" ++#include "ctrlEnv/sys/mvCpuIfRegs.h" ++ ++/* defines */ ++#ifdef MV_DEBUG ++ #define DB(x) x ++#else ++ #define DB(x) ++#endif ++ ++/* locals */ ++ ++/******************************************************************************* ++* mvCpuPclkGet - Get the CPU pClk (pipe clock) ++* ++* DESCRIPTION: ++* This routine extract the CPU core clock. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit clock cycles in MHertz. ++* ++*******************************************************************************/ ++/* 6180 have different clk reset sampling */ ++ ++static MV_U32 mvCpu6180PclkGet(MV_VOID) ++{ ++ MV_U32 tmpPClkRate=0; ++ MV_CPU_ARM_CLK cpu6180_ddr_l2_CLK[] = MV_CPU6180_DDR_L2_CLCK_TBL; ++ ++ tmpPClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); ++ tmpPClkRate = tmpPClkRate & MSAR_CPUCLCK_MASK_6180; ++ tmpPClkRate = tmpPClkRate >> MSAR_CPUCLCK_OFFS_6180; ++ ++ tmpPClkRate = cpu6180_ddr_l2_CLK[tmpPClkRate].cpuClk; ++ ++ return tmpPClkRate; ++} ++ ++ ++MV_U32 mvCpuPclkGet(MV_VOID) ++{ ++#if defined(PCLCK_AUTO_DETECT) ++ MV_U32 tmpPClkRate=0; ++ MV_U32 cpuCLK[] = MV_CPU_CLCK_TBL; ++ ++ if(mvCtrlModelGet() == MV_6180_DEV_ID) ++ return mvCpu6180PclkGet(); ++ ++ tmpPClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); ++ tmpPClkRate = MSAR_CPUCLCK_EXTRACT(tmpPClkRate); ++ tmpPClkRate = cpuCLK[tmpPClkRate]; ++ ++ return tmpPClkRate; ++#else ++ return MV_DEFAULT_PCLK ++#endif ++} ++ ++/******************************************************************************* ++* mvCpuL2ClkGet - Get the CPU L2 (CPU bus clock) ++* ++* DESCRIPTION: ++* This routine extract the CPU L2 clock. ++* ++* RETURN: ++* 32bit clock cycles in Hertz. ++* ++*******************************************************************************/ ++static MV_U32 mvCpu6180L2ClkGet(MV_VOID) ++{ ++ MV_U32 L2ClkRate=0; ++ MV_CPU_ARM_CLK _cpu6180_ddr_l2_CLK[] = MV_CPU6180_DDR_L2_CLCK_TBL; ++ ++ L2ClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); ++ L2ClkRate = L2ClkRate & MSAR_CPUCLCK_MASK_6180; ++ L2ClkRate = L2ClkRate >> MSAR_CPUCLCK_OFFS_6180; ++ ++ L2ClkRate = _cpu6180_ddr_l2_CLK[L2ClkRate].l2Clk; ++ ++ return L2ClkRate; ++ ++} ++ ++MV_U32 mvCpuL2ClkGet(MV_VOID) ++{ ++#ifdef L2CLK_AUTO_DETECT ++ MV_U32 L2ClkRate, tmp, pClkRate, indexL2Rtio; ++ MV_U32 L2Rtio[][2] = MV_L2_CLCK_RTIO_TBL; ++ ++ if(mvCtrlModelGet() == MV_6180_DEV_ID) ++ return mvCpu6180L2ClkGet(); ++ ++ pClkRate = mvCpuPclkGet(); ++ ++ tmp = MV_REG_READ(MPP_SAMPLE_AT_RESET); ++ indexL2Rtio = MSAR_L2CLCK_EXTRACT(tmp); ++ ++ L2ClkRate = ((pClkRate * L2Rtio[indexL2Rtio][1]) / L2Rtio[indexL2Rtio][0]); ++ ++ return L2ClkRate; ++#else ++ return MV_BOARD_DEFAULT_L2CLK; ++#endif ++} ++ ++ ++/******************************************************************************* ++* mvCpuNameGet - Get CPU name ++* ++* DESCRIPTION: ++* This function returns a string describing the CPU model and revision. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* pNameBuff - Buffer to contain board name string. Minimum size 32 chars. ++* ++* RETURN: ++* None. ++*******************************************************************************/ ++MV_VOID mvCpuNameGet(char *pNameBuff) ++{ ++ MV_U32 cpuModel; ++ ++ cpuModel = mvOsCpuPartGet(); ++ ++ /* The CPU module is indicated in the Processor Version Register (PVR) */ ++ switch(cpuModel) ++ { ++ case CPU_PART_MRVL131: ++ mvOsSPrintf(pNameBuff, "%s (Rev %d)", "Marvell Feroceon",mvOsCpuRevGet()); ++ break; ++ case CPU_PART_ARM926: ++ mvOsSPrintf(pNameBuff, "%s (Rev %d)", "ARM926",mvOsCpuRevGet()); ++ break; ++ case CPU_PART_ARM946: ++ mvOsSPrintf(pNameBuff, "%s (Rev %d)", "ARM946",mvOsCpuRevGet()); ++ break; ++ default: ++ mvOsSPrintf(pNameBuff,"??? (0x%04x) (Rev %d)",cpuModel,mvOsCpuRevGet()); ++ break; ++ } /* switch */ ++ ++ return; ++} ++ ++ ++#define MV_PROC_STR_SIZE 50 ++ ++static void mvCpuIfGetL2EccMode(MV_8 *buf) ++{ ++ MV_U32 regVal = MV_REG_READ(CPU_L2_CONFIG_REG); ++ if (regVal & BIT2) ++ mvOsSPrintf(buf, "L2 ECC Enabled"); ++ else ++ mvOsSPrintf(buf, "L2 ECC Disabled"); ++} ++ ++static void mvCpuIfGetL2Mode(MV_8 *buf) ++{ ++ MV_U32 regVal = 0; ++ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ ++ if (regVal & BIT22) ++ mvOsSPrintf(buf, "L2 Enabled"); ++ else ++ mvOsSPrintf(buf, "L2 Disabled"); ++} ++ ++static void mvCpuIfGetL2PrefetchMode(MV_8 *buf) ++{ ++ MV_U32 regVal = 0; ++ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ ++ if (regVal & BIT24) ++ mvOsSPrintf(buf, "L2 Prefetch Disabled"); ++ else ++ mvOsSPrintf(buf, "L2 Prefetch Enabled"); ++} ++ ++static void mvCpuIfGetWriteAllocMode(MV_8 *buf) ++{ ++ MV_U32 regVal = 0; ++ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ ++ if (regVal & BIT28) ++ mvOsSPrintf(buf, "Write Allocate Enabled"); ++ else ++ mvOsSPrintf(buf, "Write Allocate Disabled"); ++} ++ ++static void mvCpuIfGetCpuStreamMode(MV_8 *buf) ++{ ++ MV_U32 regVal = 0; ++ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ ++ if (regVal & BIT29) ++ mvOsSPrintf(buf, "CPU Streaming Enabled"); ++ else ++ mvOsSPrintf(buf, "CPU Streaming Disabled"); ++} ++ ++static void mvCpuIfPrintCpuRegs(void) ++{ ++ MV_U32 regVal = 0; ++ ++ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ ++ mvOsPrintf("Extra Feature Reg = 0x%x\n",regVal); ++ ++ __asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (regVal)); /* Read Control register */ ++ mvOsPrintf("Control Reg = 0x%x\n",regVal); ++ ++ __asm volatile ("mrc p15, 0, %0, c0, c0, 0" : "=r" (regVal)); /* Read ID Code register */ ++ mvOsPrintf("ID Code Reg = 0x%x\n",regVal); ++ ++ __asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=r" (regVal)); /* Read Cache Type register */ ++ mvOsPrintf("Cache Type Reg = 0x%x\n",regVal); ++ ++} ++ ++MV_U32 mvCpuIfPrintSystemConfig(MV_8 *buffer, MV_U32 index) ++{ ++ MV_U32 count = 0; ++ ++ MV_8 L2_ECC_str[MV_PROC_STR_SIZE]; ++ MV_8 L2_En_str[MV_PROC_STR_SIZE]; ++ MV_8 L2_Prefetch_str[MV_PROC_STR_SIZE]; ++ MV_8 Write_Alloc_str[MV_PROC_STR_SIZE]; ++ MV_8 Cpu_Stream_str[MV_PROC_STR_SIZE]; ++ ++ mvCpuIfGetL2Mode(L2_En_str); ++ mvCpuIfGetL2EccMode(L2_ECC_str); ++ mvCpuIfGetL2PrefetchMode(L2_Prefetch_str); ++ mvCpuIfGetWriteAllocMode(Write_Alloc_str); ++ mvCpuIfGetCpuStreamMode(Cpu_Stream_str); ++ mvCpuIfPrintCpuRegs(); ++ ++ count += mvOsSPrintf(buffer + count + index, "%s\n", L2_En_str); ++ count += mvOsSPrintf(buffer + count + index, "%s\n", L2_ECC_str); ++ count += mvOsSPrintf(buffer + count + index, "%s\n", L2_Prefetch_str); ++ count += mvOsSPrintf(buffer + count + index, "%s\n", Write_Alloc_str); ++ count += mvOsSPrintf(buffer + count + index, "%s\n", Cpu_Stream_str); ++ return count; ++} ++ ++MV_U32 whoAmI(MV_VOID) ++{ ++ return 0; ++} ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,99 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvCpuh ++#define __INCmvCpuh ++ ++#include "mvCommon.h" ++#include "mvOs.h" ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++ ++/* defines */ ++#define CPU_PART_MRVL131 0x131 ++#define CPU_PART_ARM926 0x926 ++#define CPU_PART_ARM946 0x946 ++#define MV_CPU_ARM_CLK_ELM_SIZE 12 ++#define MV_CPU_ARM_CLK_RATIO_OFF 8 ++#define MV_CPU_ARM_CLK_DDR_OFF 4 ++ ++#ifndef MV_ASMLANGUAGE ++typedef struct _mvCpuArmClk ++{ ++ MV_U32 cpuClk; /* CPU clock in MHz */ ++ MV_U32 ddrClk; /* DDR clock in MHz */ ++ MV_U32 l2Clk; /* CPU DDR clock ratio */ ++ ++}MV_CPU_ARM_CLK; ++ ++MV_U32 mvCpuPclkGet(MV_VOID); ++MV_VOID mvCpuNameGet(char *pNameBuff); ++MV_U32 mvCpuL2ClkGet(MV_VOID); ++MV_U32 mvCpuIfPrintSystemConfig(MV_8 *buffer, MV_U32 index); ++MV_U32 whoAmI(MV_VOID); ++ ++#endif /* MV_ASMLANGUAGE */ ++ ++ ++#endif /* __INCmvCpuh */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,296 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++/******************************************************************************* ++* mvCtrlEnvAddrDec.h - Marvell controller address decode library ++* ++* DESCRIPTION: ++* ++* DEPENDENCIES: ++* None. ++* ++*******************************************************************************/ ++ ++/* includes */ ++#include "ctrlEnv/mvCtrlEnvAddrDec.h" ++#include "ctrlEnv/sys/mvAhbToMbusRegs.h" ++#include "ddr2/mvDramIfRegs.h" ++#include "pex/mvPexRegs.h" ++ ++#define MV_DEBUG ++ ++/* defines */ ++#ifdef MV_DEBUG ++ #define DB(x) x ++#else ++ #define DB(x) ++#endif ++ ++/* Default Attributes array */ ++MV_TARGET_ATTRIB mvTargetDefaultsArray[] = TARGETS_DEF_ARRAY; ++extern MV_TARGET *sampleAtResetTargetArray; ++/* Dram\AHBToMbus\PEX share regsiter */ ++ ++#define CTRL_DEC_BASE_OFFS 16 ++#define CTRL_DEC_BASE_MASK (0xffff << CTRL_DEC_BASE_OFFS) ++#define CTRL_DEC_BASE_ALIGNMENT 0x10000 ++ ++#define CTRL_DEC_SIZE_OFFS 16 ++#define CTRL_DEC_SIZE_MASK (0xffff << CTRL_DEC_SIZE_OFFS) ++#define CTRL_DEC_SIZE_ALIGNMENT 0x10000 ++ ++#define CTRL_DEC_WIN_EN BIT0 ++ ++ ++ ++/******************************************************************************* ++* mvCtrlAddrDecToReg - Get address decode register format values ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_STATUS mvCtrlAddrDecToReg(MV_ADDR_WIN *pAddrDecWin, MV_DEC_REGS *pAddrDecRegs) ++{ ++ ++ MV_U32 baseToReg=0 , sizeToReg=0; ++ ++ /* BaseLow[31:16] => base register [31:16] */ ++ baseToReg = pAddrDecWin->baseLow & CTRL_DEC_BASE_MASK; ++ ++ /* Write to address decode Base Address Register */ ++ pAddrDecRegs->baseReg &= ~CTRL_DEC_BASE_MASK; ++ pAddrDecRegs->baseReg |= baseToReg; ++ ++ /* Get size register value according to window size */ ++ sizeToReg = ctrlSizeToReg(pAddrDecWin->size, CTRL_DEC_SIZE_ALIGNMENT); ++ ++ /* Size parameter validity check. */ ++ if (-1 == sizeToReg) ++ { ++ return MV_BAD_PARAM; ++ } ++ ++ /* set size */ ++ pAddrDecRegs->sizeReg &= ~CTRL_DEC_SIZE_MASK; ++ pAddrDecRegs->sizeReg |= (sizeToReg << CTRL_DEC_SIZE_OFFS); ++ ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvCtrlRegToAddrDec - Extract address decode struct from registers. ++* ++* DESCRIPTION: ++* This function extract address decode struct from address decode ++* registers given as parameters. ++* ++* INPUT: ++* pAddrDecRegs - Address decode register struct. ++* ++* OUTPUT: ++* pAddrDecWin - Target window data structure. ++* ++* RETURN: ++* MV_BAD_PARAM if address decode registers data is invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvCtrlRegToAddrDec(MV_DEC_REGS *pAddrDecRegs, MV_ADDR_WIN *pAddrDecWin) ++{ ++ MV_U32 sizeRegVal; ++ ++ sizeRegVal = (pAddrDecRegs->sizeReg & CTRL_DEC_SIZE_MASK) >> ++ CTRL_DEC_SIZE_OFFS; ++ ++ pAddrDecWin->size = ctrlRegToSize(sizeRegVal, CTRL_DEC_SIZE_ALIGNMENT); ++ ++ ++ /* Extract base address */ ++ /* Base register [31:16] ==> baseLow[31:16] */ ++ pAddrDecWin->baseLow = pAddrDecRegs->baseReg & CTRL_DEC_BASE_MASK; ++ ++ pAddrDecWin->baseHigh = 0; ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvCtrlAttribGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++* ++*******************************************************************************/ ++ ++MV_STATUS mvCtrlAttribGet(MV_TARGET target, ++ MV_TARGET_ATTRIB *targetAttrib) ++{ ++ ++ targetAttrib->attrib = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].attrib; ++ targetAttrib->targetId = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId; ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvCtrlGetAttrib - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_TARGET mvCtrlTargetGet(MV_TARGET_ATTRIB *targetAttrib) ++{ ++ MV_TARGET target; ++ MV_TARGET x; ++ for (target = SDRAM_CS0; target < MAX_TARGETS ; target ++) ++ { ++ x = MV_CHANGE_BOOT_CS(target); ++ if ((mvTargetDefaultsArray[x].attrib == targetAttrib->attrib) && ++ (mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId == targetAttrib->targetId)) ++ { ++ /* found it */ ++ break; ++ } ++ } ++ ++ return target; ++} ++ ++MV_STATUS mvCtrlAddrDecToParams(MV_DEC_WIN *pAddrDecWin, ++ MV_DEC_WIN_PARAMS *pWinParam) ++{ ++ MV_U32 baseToReg=0, sizeToReg=0; ++ ++ /* BaseLow[31:16] => base register [31:16] */ ++ baseToReg = pAddrDecWin->addrWin.baseLow & CTRL_DEC_BASE_MASK; ++ ++ /* Write to address decode Base Address Register */ ++ pWinParam->baseAddr &= ~CTRL_DEC_BASE_MASK; ++ pWinParam->baseAddr |= baseToReg; ++ ++ /* Get size register value according to window size */ ++ sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, CTRL_DEC_SIZE_ALIGNMENT); ++ ++ /* Size parameter validity check. */ ++ if (-1 == sizeToReg) ++ { ++ mvOsPrintf("mvCtrlAddrDecToParams: ERR. ctrlSizeToReg failed.\n"); ++ return MV_BAD_PARAM; ++ } ++ pWinParam->size = sizeToReg; ++ ++ pWinParam->attrib = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(pAddrDecWin->target)].attrib; ++ pWinParam->targetId = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(pAddrDecWin->target)].targetId; ++ ++ return MV_OK; ++} ++ ++MV_STATUS mvCtrlParamsToAddrDec(MV_DEC_WIN_PARAMS *pWinParam, ++ MV_DEC_WIN *pAddrDecWin) ++{ ++ MV_TARGET_ATTRIB targetAttrib; ++ ++ pAddrDecWin->addrWin.baseLow = pWinParam->baseAddr; ++ ++ /* Upper 32bit address base is supported under PCI High Address remap */ ++ pAddrDecWin->addrWin.baseHigh = 0; ++ ++ /* Prepare sizeReg to ctrlRegToSize function */ ++ pAddrDecWin->addrWin.size = ctrlRegToSize(pWinParam->size, CTRL_DEC_SIZE_ALIGNMENT); ++ ++ if (-1 == pAddrDecWin->addrWin.size) ++ { ++ DB(mvOsPrintf("mvCtrlParamsToAddrDec: ERR. ctrlRegToSize failed.\n")); ++ return MV_BAD_PARAM; ++ } ++ targetAttrib.targetId = pWinParam->targetId; ++ targetAttrib.attrib = pWinParam->attrib; ++ ++ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); ++ ++ return MV_OK; ++} ++ ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,203 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvCtrlEnvAddrDech ++#define __INCmvCtrlEnvAddrDech ++ ++/* includes */ ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "ctrlEnv/mvCtrlEnvRegs.h" ++ ++ ++/* defines */ ++/* DUnit attributes */ ++#define ATMWCR_WIN_DUNIT_CS0_OFFS 0 ++#define ATMWCR_WIN_DUNIT_CS0_MASK BIT0 ++#define ATMWCR_WIN_DUNIT_CS0_REQ (0 << ATMWCR_WIN_DUNIT_CS0_OFFS) ++ ++#define ATMWCR_WIN_DUNIT_CS1_OFFS 1 ++#define ATMWCR_WIN_DUNIT_CS1_MASK BIT1 ++#define ATMWCR_WIN_DUNIT_CS1_REQ (0 << ATMWCR_WIN_DUNIT_CS1_OFFS) ++ ++#define ATMWCR_WIN_DUNIT_CS2_OFFS 2 ++#define ATMWCR_WIN_DUNIT_CS2_MASK BIT2 ++#define ATMWCR_WIN_DUNIT_CS2_REQ (0 << ATMWCR_WIN_DUNIT_CS2_OFFS) ++ ++#define ATMWCR_WIN_DUNIT_CS3_OFFS 3 ++#define ATMWCR_WIN_DUNIT_CS3_MASK BIT3 ++#define ATMWCR_WIN_DUNIT_CS3_REQ (0 << ATMWCR_WIN_DUNIT_CS3_OFFS) ++ ++/* RUnit (Device) attributes */ ++#define ATMWCR_WIN_RUNIT_DEVCS0_OFFS 0 ++#define ATMWCR_WIN_RUNIT_DEVCS0_MASK BIT0 ++#define ATMWCR_WIN_RUNIT_DEVCS0_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS0_OFFS) ++ ++#define ATMWCR_WIN_RUNIT_DEVCS1_OFFS 1 ++#define ATMWCR_WIN_RUNIT_DEVCS1_MASK BIT1 ++#define ATMWCR_WIN_RUNIT_DEVCS1_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS1_OFFS) ++ ++#define ATMWCR_WIN_RUNIT_DEVCS2_OFFS 2 ++#define ATMWCR_WIN_RUNIT_DEVCS2_MASK BIT2 ++#define ATMWCR_WIN_RUNIT_DEVCS2_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS2_OFFS) ++ ++#define ATMWCR_WIN_RUNIT_BOOTCS_OFFS 4 ++#define ATMWCR_WIN_RUNIT_BOOTCS_MASK BIT4 ++#define ATMWCR_WIN_RUNIT_BOOTCS_REQ (0 << ATMWCR_WIN_RUNIT_BOOTCS_OFFS) ++ ++/* LMaster (PCI) attributes */ ++#define ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS 0 ++#define ATMWCR_WIN_LUNIT_BYTE_SWP_MASK BIT0 ++#define ATMWCR_WIN_LUNIT_BYTE_SWP (0 << ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS) ++#define ATMWCR_WIN_LUNIT_BYTE_NO_SWP (1 << ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS) ++ ++ ++#define ATMWCR_WIN_LUNIT_WORD_SWP_OFFS 1 ++#define ATMWCR_WIN_LUNIT_WORD_SWP_MASK BIT1 ++#define ATMWCR_WIN_LUNIT_WORD_SWP (0 << ATMWCR_WIN_LUNIT_WORD_SWP_OFFS) ++#define ATMWCR_WIN_LUNIT_WORD_NO_SWP (1 << ATMWCR_WIN_LUNIT_WORD_SWP_OFFS) ++ ++#define ATMWCR_WIN_LUNIT_NO_SNOOP BIT2 ++ ++#define ATMWCR_WIN_LUNIT_TYPE_OFFS 3 ++#define ATMWCR_WIN_LUNIT_TYPE_MASK BIT3 ++#define ATMWCR_WIN_LUNIT_TYPE_IO (0 << ATMWCR_WIN_LUNIT_TYPE_OFFS) ++#define ATMWCR_WIN_LUNIT_TYPE_MEM (1 << ATMWCR_WIN_LUNIT_TYPE_OFFS) ++ ++#define ATMWCR_WIN_LUNIT_FORCE64_OFFS 4 ++#define ATMWCR_WIN_LUNIT_FORCE64_MASK BIT4 ++#define ATMWCR_WIN_LUNIT_FORCE64 (0 << ATMWCR_WIN_LUNIT_FORCE64_OFFS) ++ ++#define ATMWCR_WIN_LUNIT_ORDERING_OFFS 6 ++#define ATMWCR_WIN_LUNIT_ORDERING_MASK BIT6 ++#define ATMWCR_WIN_LUNIT_ORDERING (1 << ATMWCR_WIN_LUNIT_FORCE64_OFFS) ++ ++/* PEX Attributes */ ++#define ATMWCR_WIN_PEX_TYPE_OFFS 3 ++#define ATMWCR_WIN_PEX_TYPE_MASK BIT3 ++#define ATMWCR_WIN_PEX_TYPE_IO (0 << ATMWCR_WIN_PEX_TYPE_OFFS) ++#define ATMWCR_WIN_PEX_TYPE_MEM (1 << ATMWCR_WIN_PEX_TYPE_OFFS) ++ ++/* typedefs */ ++ ++/* Unsupported attributes for address decode: */ ++/* 2) PCI0/1_REQ64n control */ ++ ++typedef struct _mvDecRegs ++{ ++ MV_U32 baseReg; ++ MV_U32 baseRegHigh; ++ MV_U32 sizeReg; ++ ++}MV_DEC_REGS; ++ ++typedef struct _mvTargetAttrib ++{ ++ MV_U8 attrib; /* chip select attributes */ ++ MV_TARGET_ID targetId; /* Target Id of this MV_TARGET */ ++ ++}MV_TARGET_ATTRIB; ++ ++ ++/* This structure describes address decode window */ ++typedef struct _mvDecWin ++{ ++ MV_TARGET target; /* Target for addr decode window */ ++ MV_ADDR_WIN addrWin; /* Address window of target */ ++ MV_BOOL enable; /* Window enable/disable */ ++}MV_DEC_WIN; ++ ++typedef struct _mvDecWinParams ++{ ++ MV_TARGET_ID targetId; /* Target ID field */ ++ MV_U8 attrib; /* Attribute field */ ++ MV_U32 baseAddr; /* Base address in register format */ ++ MV_U32 size; /* Size in register format */ ++}MV_DEC_WIN_PARAMS; ++ ++ ++/* mvCtrlEnvAddrDec API list */ ++ ++MV_STATUS mvCtrlAddrDecToReg(MV_ADDR_WIN *pAddrDecWin, ++ MV_DEC_REGS *pAddrDecRegs); ++ ++MV_STATUS mvCtrlRegToAddrDec(MV_DEC_REGS *pAddrDecRegs, ++ MV_ADDR_WIN *pAddrDecWin); ++ ++MV_STATUS mvCtrlAttribGet(MV_TARGET target, ++ MV_TARGET_ATTRIB *targetAttrib); ++ ++MV_TARGET mvCtrlTargetGet(MV_TARGET_ATTRIB *targetAttrib); ++ ++ ++MV_STATUS mvCtrlAddrDecToParams(MV_DEC_WIN *pAddrDecWin, ++ MV_DEC_WIN_PARAMS *pWinParam); ++ ++MV_STATUS mvCtrlParamsToAddrDec(MV_DEC_WIN_PARAMS *pWinParam, ++ MV_DEC_WIN *pAddrDecWin); ++ ++ ++ ++ ++#endif /* __INCmvCtrlEnvAddrDech */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,98 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvCtrlEnvAsmh ++#define __INCmvCtrlEnvAsmh ++#include "pex/mvPexRegs.h" ++ ++#define CHIP_BOND_REG 0x10034 ++#define PCKG_OPT_MASK_AS #3 ++#define PXCCARI_REVID_MASK_AS #PXCCARI_REVID_MASK ++ ++/* Read device ID into toReg bits 15:0 from 0xd0000000 */ ++/* defines */ ++#define MV_DV_CTRL_MODEL_GET_ASM(toReg, tmpReg) \ ++ MV_DV_REG_READ_ASM(toReg, tmpReg, CHIP_BOND_REG);\ ++ and toReg, toReg, PCKG_OPT_MASK_AS /* Mask for package ID */ ++ ++/* Read device ID into toReg bits 15:0 from 0xf1000000*/ ++#define MV_CTRL_MODEL_GET_ASM(toReg, tmpReg) \ ++ MV_REG_READ_ASM(toReg, tmpReg, CHIP_BOND_REG);\ ++ and toReg, toReg, PCKG_OPT_MASK_AS /* Mask for package ID */ ++ ++/* Read Revision into toReg bits 7:0 0xd0000000*/ ++#define MV_DV_CTRL_REV_GET_ASM(toReg, tmpReg) \ ++ /* Read device revision */ \ ++ MV_DV_REG_READ_ASM(toReg, tmpReg, PEX_CFG_DIRECT_ACCESS(0,PEX_CLASS_CODE_AND_REVISION_ID));\ ++ and toReg, toReg, PXCCARI_REVID_MASK_AS /* Mask for calss ID */ ++ ++/* Read Revision into toReg bits 7:0 0xf1000000*/ ++#define MV_CTRL_REV_GET_ASM(toReg, tmpReg) \ ++ /* Read device revision */ \ ++ MV_REG_READ_ASM(toReg, tmpReg, PEX_CFG_DIRECT_ACCESS(0,PEX_CLASS_CODE_AND_REVISION_ID));\ ++ and toReg, toReg, PXCCARI_REVID_MASK_AS /* Mask for calss ID */ ++ ++ ++#endif /* __INCmvCtrlEnvAsmh */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,1825 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++/* includes */ ++#include "mvCommon.h" ++#include "mvCtrlEnvLib.h" ++#include "ctrlEnv/sys/mvCpuIf.h" ++ ++#if defined(MV_INCLUDE_PEX) ++#include "pex/mvPex.h" ++#include "ctrlEnv/sys/mvSysPex.h" ++#endif ++ ++#if defined(MV_INCLUDE_GIG_ETH) ++#include "ctrlEnv/sys/mvSysGbe.h" ++#endif ++ ++#if defined(MV_INCLUDE_XOR) ++#include "ctrlEnv/sys/mvSysXor.h" ++#endif ++ ++#if defined(MV_INCLUDE_SATA) ++#include "ctrlEnv/sys/mvSysSata.h" ++#endif ++ ++#if defined(MV_INCLUDE_USB) ++#include "ctrlEnv/sys/mvSysUsb.h" ++#endif ++ ++#if defined(MV_INCLUDE_AUDIO) ++#include "ctrlEnv/sys/mvSysAudio.h" ++#endif ++ ++#if defined(MV_INCLUDE_CESA) ++#include "ctrlEnv/sys/mvSysCesa.h" ++#endif ++ ++#if defined(MV_INCLUDE_TS) ++#include "ctrlEnv/sys/mvSysTs.h" ++#endif ++ ++/* defines */ ++#ifdef MV_DEBUG ++ #define DB(x) x ++#else ++ #define DB(x) ++#endif ++ ++/******************************************************************************* ++* mvCtrlEnvInit - Initialize Marvell controller environment. ++* ++* DESCRIPTION: ++* This function get environment information and initialize controller ++* internal/external environment. For example ++* 1) MPP settings according to board MPP macros. ++* NOTE: It is the user responsibility to shut down all DMA channels ++* in device and disable controller sub units interrupts during ++* boot process. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_STATUS mvCtrlEnvInit(MV_VOID) ++{ ++ MV_U32 mppGroup; ++ MV_U32 devId; ++ MV_U32 boardId; ++ MV_U32 i; ++ MV_U32 maxMppGrp = 1; ++ MV_U32 mppVal = 0; ++ MV_U32 bootVal = 0; ++ MV_U32 mppGroupType = 0; ++ MV_U32 mppGroup1[][3] = MPP_GROUP_1_TYPE; ++ MV_U32 mppGroup2[][3] = MPP_GROUP_2_TYPE; ++ ++ devId = mvCtrlModelGet(); ++ boardId= mvBoardIdGet(); ++ ++ switch(devId){ ++ case MV_6281_DEV_ID: ++ maxMppGrp = MV_6281_MPP_MAX_GROUP; ++ break; ++ case MV_6192_DEV_ID: ++ maxMppGrp = MV_6192_MPP_MAX_GROUP; ++ break; ++ case MV_6190_DEV_ID: ++ maxMppGrp = MV_6190_MPP_MAX_GROUP; ++ break; ++ case MV_6180_DEV_ID: ++ maxMppGrp = MV_6180_MPP_MAX_GROUP; ++ break; ++ } ++ ++ /* MPP Init */ ++ /* We split mpp init to 3 phases: ++ * 1. We init mpp[19:0] from the board info. mpp[23:20] will be over write ++ * in phase 2. ++ * 2. We detect the mpp group type and according the mpp values [35:20]. ++ * 3. We detect the mpp group type and according the mpp values [49:36]. ++ */ ++ /* Mpp phase 1 mpp[19:0] */ ++ /* Read MPP group from board level and assign to MPP register */ ++ for (mppGroup = 0; mppGroup < 3; mppGroup++) ++ { ++ mppVal = mvBoardMppGet(mppGroup); ++ if (mppGroup == 0) ++ { ++ bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); ++ if (mvCtrlIsBootFromSPI()) ++ { ++ mppVal &= ~0xffff; ++ bootVal &= 0xffff; ++ mppVal |= bootVal; ++ } ++ else if (mvCtrlIsBootFromSPIUseNAND()) ++ { ++ mppVal &= ~0xf0000000; ++ bootVal &= 0xf0000000; ++ mppVal |= bootVal; ++ } ++ else if (mvCtrlIsBootFromNAND()) ++ { ++ mppVal &= ~0xffffff; ++ bootVal &= 0xffffff; ++ mppVal |= bootVal; ++ } ++ } ++ ++ if (mppGroup == 2) ++ { ++ bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); ++ if (mvCtrlIsBootFromNAND()) ++ { ++ mppVal &= ~0xff00; ++ bootVal &= 0xff00; ++ mppVal |= bootVal; ++ } ++ } ++ ++ MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal); ++ } ++ ++ /* Identify MPPs group */ ++ mvBoardMppGroupIdUpdate(); ++ ++ /* Update MPPs mux relevent only on Marvell DB */ ++ if ((boardId == DB_88F6281A_BP_ID) || ++ (boardId == DB_88F6180A_BP_ID)) ++ mvBoardMppMuxSet(); ++ ++ mppGroupType = mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_1); ++ ++ /* Mpp phase 2 */ ++ /* Read MPP group from board level and assign to MPP register */ ++ if (devId != MV_6180_DEV_ID) ++ { ++ i = 0; ++ for (mppGroup = 2; mppGroup < 5; mppGroup++) ++ { ++ if ((mppGroupType == MV_BOARD_OTHER) || ++ (boardId == RD_88F6281A_ID) || ++ (boardId == RD_88F6192A_ID) || ++ (boardId == RD_88F6190A_ID) || ++ (boardId == RD_88F6281A_PCAC_ID) || ++ (boardId == SHEEVA_PLUG_ID)) ++ mppVal = mvBoardMppGet(mppGroup); ++ else ++ { ++ mppVal = mppGroup1[mppGroupType][i]; ++ i++; ++ } ++ ++ /* Group 2 is shared mpp[23:16] */ ++ if (mppGroup == 2) ++ { ++ bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); ++ mppVal &= ~0xffff; ++ bootVal &= 0xffff; ++ mppVal |= bootVal; ++ } ++ ++ MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal); ++ } ++ } ++ ++ if ((devId == MV_6192_DEV_ID) || (devId == MV_6190_DEV_ID)) ++ return MV_OK; ++ ++ /* Mpp phase 3 */ ++ mppGroupType = mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_2); ++ /* Read MPP group from board level and assign to MPP register */ ++ i = 0; ++ for (mppGroup = 4; mppGroup < 7; mppGroup++) ++ { ++ if ((mppGroupType == MV_BOARD_OTHER) || ++ (boardId == RD_88F6281A_ID) || ++ (boardId == RD_88F6281A_PCAC_ID) || ++ (boardId == SHEEVA_PLUG_ID)) ++ mppVal = mvBoardMppGet(mppGroup); ++ else ++ { ++ mppVal = mppGroup2[mppGroupType][i]; ++ i++; ++ } ++ ++ /* Group 4 is shared mpp[35:32] */ ++ if (mppGroup == 4) ++ { ++ bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); ++ mppVal &= ~0xffff; ++ bootVal &= 0xffff; ++ mppVal |= bootVal; ++ } ++ ++ MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal); ++ } ++ /* Update SSCG configuration register*/ ++ if(mvBoardIdGet() == DB_88F6281A_BP_ID || mvBoardIdGet() == DB_88F6192A_BP_ID || ++ mvBoardIdGet() == DB_88F6190A_BP_ID || mvBoardIdGet() == DB_88F6180A_BP_ID) ++ MV_REG_WRITE(0x100d8, 0x53); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCtrlMppRegGet - return reg address of mpp group ++* ++* DESCRIPTION: ++* ++* INPUT: ++* mppGroup - MPP group. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_U32 - Register address. ++* ++*******************************************************************************/ ++MV_U32 mvCtrlMppRegGet(MV_U32 mppGroup) ++{ ++ MV_U32 ret; ++ ++ switch(mppGroup){ ++ case (0): ret = MPP_CONTROL_REG0; ++ break; ++ case (1): ret = MPP_CONTROL_REG1; ++ break; ++ case (2): ret = MPP_CONTROL_REG2; ++ break; ++ case (3): ret = MPP_CONTROL_REG3; ++ break; ++ case (4): ret = MPP_CONTROL_REG4; ++ break; ++ case (5): ret = MPP_CONTROL_REG5; ++ break; ++ case (6): ret = MPP_CONTROL_REG6; ++ break; ++ default: ret = MPP_CONTROL_REG0; ++ break; ++ } ++ return ret; ++} ++#if defined(MV_INCLUDE_PEX) ++/******************************************************************************* ++* mvCtrlPexMaxIfGet - Get Marvell controller number of PEX interfaces. ++* ++* DESCRIPTION: ++* This function returns Marvell controller number of PEX interfaces. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Marvell controller number of PEX interfaces. If controller ++* ID is undefined the function returns '0'. ++* ++*******************************************************************************/ ++MV_U32 mvCtrlPexMaxIfGet(MV_VOID) ++{ ++ ++ return MV_PEX_MAX_IF; ++} ++#endif ++ ++#if defined(MV_INCLUDE_GIG_ETH) ++/******************************************************************************* ++* mvCtrlEthMaxPortGet - Get Marvell controller number of etherent ports. ++* ++* DESCRIPTION: ++* This function returns Marvell controller number of etherent port. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Marvell controller number of etherent port. ++* ++*******************************************************************************/ ++MV_U32 mvCtrlEthMaxPortGet(MV_VOID) ++{ ++ MV_U32 devId; ++ ++ devId = mvCtrlModelGet(); ++ ++ switch(devId){ ++ case MV_6281_DEV_ID: ++ return MV_6281_ETH_MAX_PORTS; ++ break; ++ case MV_6192_DEV_ID: ++ return MV_6192_ETH_MAX_PORTS; ++ break; ++ case MV_6190_DEV_ID: ++ return MV_6190_ETH_MAX_PORTS; ++ break; ++ case MV_6180_DEV_ID: ++ return MV_6180_ETH_MAX_PORTS; ++ break; ++ } ++ return 0; ++ ++} ++#endif ++ ++#if defined(MV_INCLUDE_XOR) ++/******************************************************************************* ++* mvCtrlXorMaxChanGet - Get Marvell controller number of XOR channels. ++* ++* DESCRIPTION: ++* This function returns Marvell controller number of XOR channels. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Marvell controller number of XOR channels. ++* ++*******************************************************************************/ ++MV_U32 mvCtrlXorMaxChanGet(MV_VOID) ++{ ++ return MV_XOR_MAX_CHAN; ++} ++#endif ++ ++#if defined(MV_INCLUDE_USB) ++/******************************************************************************* ++* mvCtrlUsbHostMaxGet - Get number of Marvell Usb controllers ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* returns number of Marvell USB controllers. ++* ++*******************************************************************************/ ++MV_U32 mvCtrlUsbMaxGet(void) ++{ ++ return MV_USB_MAX_PORTS; ++} ++#endif ++ ++ ++#if defined(MV_INCLUDE_NAND) ++/******************************************************************************* ++* mvCtrlNandSupport - Return if this controller has integrated NAND flash support ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if NAND is supported and MV_FALSE otherwise ++* ++*******************************************************************************/ ++MV_U32 mvCtrlNandSupport(MV_VOID) ++{ ++ MV_U32 devId; ++ ++ devId = mvCtrlModelGet(); ++ ++ switch(devId){ ++ case MV_6281_DEV_ID: ++ return MV_6281_NAND; ++ break; ++ case MV_6192_DEV_ID: ++ return MV_6192_NAND; ++ break; ++ case MV_6190_DEV_ID: ++ return MV_6190_NAND; ++ break; ++ case MV_6180_DEV_ID: ++ return MV_6180_NAND; ++ break; ++ } ++ return 0; ++ ++} ++#endif ++ ++#if defined(MV_INCLUDE_SDIO) ++/******************************************************************************* ++* mvCtrlSdioSupport - Return if this controller has integrated SDIO flash support ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if SDIO is supported and MV_FALSE otherwise ++* ++*******************************************************************************/ ++MV_U32 mvCtrlSdioSupport(MV_VOID) ++{ ++ MV_U32 devId; ++ ++ devId = mvCtrlModelGet(); ++ ++ switch(devId){ ++ case MV_6281_DEV_ID: ++ return MV_6281_SDIO; ++ break; ++ case MV_6192_DEV_ID: ++ return MV_6192_SDIO; ++ break; ++ case MV_6190_DEV_ID: ++ return MV_6190_SDIO; ++ break; ++ case MV_6180_DEV_ID: ++ return MV_6180_SDIO; ++ break; ++ } ++ return 0; ++ ++} ++#endif ++ ++#if defined(MV_INCLUDE_TS) ++/******************************************************************************* ++* mvCtrlTsSupport - Return if this controller has integrated TS flash support ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if TS is supported and MV_FALSE otherwise ++* ++*******************************************************************************/ ++MV_U32 mvCtrlTsSupport(MV_VOID) ++{ ++ MV_U32 devId; ++ ++ devId = mvCtrlModelGet(); ++ ++ switch(devId){ ++ case MV_6281_DEV_ID: ++ return MV_6281_TS; ++ break; ++ case MV_6192_DEV_ID: ++ return MV_6192_TS; ++ break; ++ case MV_6190_DEV_ID: ++ return MV_6190_TS; ++ break; ++ case MV_6180_DEV_ID: ++ return MV_6180_TS; ++ break; ++ } ++ return 0; ++} ++#endif ++ ++#if defined(MV_INCLUDE_AUDIO) ++/******************************************************************************* ++* mvCtrlAudioSupport - Return if this controller has integrated AUDIO flash support ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if AUDIO is supported and MV_FALSE otherwise ++* ++*******************************************************************************/ ++MV_U32 mvCtrlAudioSupport(MV_VOID) ++{ ++ MV_U32 devId; ++ ++ devId = mvCtrlModelGet(); ++ ++ switch(devId){ ++ case MV_6281_DEV_ID: ++ return MV_6281_AUDIO; ++ break; ++ case MV_6192_DEV_ID: ++ return MV_6192_AUDIO; ++ break; ++ case MV_6190_DEV_ID: ++ return MV_6190_AUDIO; ++ break; ++ case MV_6180_DEV_ID: ++ return MV_6180_AUDIO; ++ break; ++ } ++ return 0; ++ ++} ++#endif ++ ++#if defined(MV_INCLUDE_TDM) ++/******************************************************************************* ++* mvCtrlTdmSupport - Return if this controller has integrated TDM flash support ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if TDM is supported and MV_FALSE otherwise ++* ++*******************************************************************************/ ++MV_U32 mvCtrlTdmSupport(MV_VOID) ++{ ++ MV_U32 devId; ++ ++ devId = mvCtrlModelGet(); ++ ++ switch(devId){ ++ case MV_6281_DEV_ID: ++ return MV_6281_TDM; ++ break; ++ case MV_6192_DEV_ID: ++ return MV_6192_TDM; ++ break; ++ case MV_6190_DEV_ID: ++ return MV_6190_TDM; ++ break; ++ case MV_6180_DEV_ID: ++ return MV_6180_TDM; ++ break; ++ } ++ return 0; ++ ++} ++#endif ++ ++/******************************************************************************* ++* mvCtrlModelGet - Get Marvell controller device model (Id) ++* ++* DESCRIPTION: ++* This function returns 16bit describing the device model (ID) as defined ++* in PCI Device and Vendor ID configuration register offset 0x0. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 16bit desscribing Marvell controller ID ++* ++*******************************************************************************/ ++MV_U16 mvCtrlModelGet(MV_VOID) ++{ ++ MV_U32 devId; ++ ++ devId = MV_REG_READ(CHIP_BOND_REG); ++ devId &= PCKG_OPT_MASK; ++ ++ switch(devId){ ++ case 2: ++ return MV_6281_DEV_ID; ++ break; ++ case 1: ++ if (((MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0,PEX_DEVICE_AND_VENDOR_ID))& 0xffff0000) >> 16) ++ == MV_6190_DEV_ID) ++ return MV_6190_DEV_ID; ++ else ++ return MV_6192_DEV_ID; ++ break; ++ case 0: ++ return MV_6180_DEV_ID; ++ break; ++ } ++ ++ return 0; ++} ++/******************************************************************************* ++* mvCtrlRevGet - Get Marvell controller device revision number ++* ++* DESCRIPTION: ++* This function returns 8bit describing the device revision as defined ++* in PCI Express Class Code and Revision ID Register. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 8bit desscribing Marvell controller revision number ++* ++*******************************************************************************/ ++MV_U8 mvCtrlRevGet(MV_VOID) ++{ ++ MV_U8 revNum; ++#if defined(MV_INCLUDE_CLK_PWR_CNTRL) ++ /* Check pex power state */ ++ MV_U32 pexPower; ++ pexPower = mvCtrlPwrClckGet(PEX_UNIT_ID,0); ++ if (pexPower == MV_FALSE) ++ mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_TRUE); ++#endif ++ revNum = (MV_U8)MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0,PCI_CLASS_CODE_AND_REVISION_ID)); ++#if defined(MV_INCLUDE_CLK_PWR_CNTRL) ++ /* Return to power off state */ ++ if (pexPower == MV_FALSE) ++ mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_FALSE); ++#endif ++ return ((revNum & PCCRIR_REVID_MASK) >> PCCRIR_REVID_OFFS); ++} ++ ++/******************************************************************************* ++* mvCtrlNameGet - Get Marvell controller name ++* ++* DESCRIPTION: ++* This function returns a string describing the device model and revision. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* pNameBuff - Buffer to contain device name string. Minimum size 30 chars. ++* ++* RETURN: ++* ++* MV_ERROR if informantion can not be read. ++*******************************************************************************/ ++MV_STATUS mvCtrlNameGet(char *pNameBuff) ++{ ++ mvOsSPrintf (pNameBuff, "%s%x Rev %d", SOC_NAME_PREFIX, ++ mvCtrlModelGet(), mvCtrlRevGet()); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCtrlModelRevGet - Get Controller Model (Device ID) and Revision ++* ++* DESCRIPTION: ++* This function returns 32bit value describing both Device ID and Revision ++* as defined in PCI Express Device and Vendor ID Register and device revision ++* as defined in PCI Express Class Code and Revision ID Register. ++ ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit describing both controller device ID and revision number ++* ++*******************************************************************************/ ++MV_U32 mvCtrlModelRevGet(MV_VOID) ++{ ++ return ((mvCtrlModelGet() << 16) | mvCtrlRevGet()); ++} ++ ++/******************************************************************************* ++* mvCtrlModelRevNameGet - Get Marvell controller name ++* ++* DESCRIPTION: ++* This function returns a string describing the device model and revision. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* pNameBuff - Buffer to contain device name string. Minimum size 30 chars. ++* ++* RETURN: ++* ++* MV_ERROR if informantion can not be read. ++*******************************************************************************/ ++ ++MV_STATUS mvCtrlModelRevNameGet(char *pNameBuff) ++{ ++ ++ switch (mvCtrlModelRevGet()) ++ { ++ case MV_6281_A0_ID: ++ mvOsSPrintf (pNameBuff, "%s",MV_6281_A0_NAME); ++ break; ++ case MV_6192_A0_ID: ++ mvOsSPrintf (pNameBuff, "%s",MV_6192_A0_NAME); ++ break; ++ case MV_6180_A0_ID: ++ mvOsSPrintf (pNameBuff, "%s",MV_6180_A0_NAME); ++ break; ++ case MV_6190_A0_ID: ++ mvOsSPrintf (pNameBuff, "%s",MV_6190_A0_NAME); ++ break; ++ case MV_6281_A1_ID: ++ mvOsSPrintf (pNameBuff, "%s",MV_6281_A1_NAME); ++ break; ++ case MV_6192_A1_ID: ++ mvOsSPrintf (pNameBuff, "%s",MV_6192_A1_NAME); ++ break; ++ case MV_6180_A1_ID: ++ mvOsSPrintf (pNameBuff, "%s",MV_6180_A1_NAME); ++ break; ++ case MV_6190_A1_ID: ++ mvOsSPrintf (pNameBuff, "%s",MV_6190_A1_NAME); ++ break; ++ default: ++ mvCtrlNameGet(pNameBuff); ++ break; ++ } ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* ctrlWinOverlapTest - Test address windows for overlaping. ++* ++* DESCRIPTION: ++* This function checks the given two address windows for overlaping. ++* ++* INPUT: ++* pAddrWin1 - Address window 1. ++* pAddrWin2 - Address window 2. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++* MV_TRUE if address window overlaps, MV_FALSE otherwise. ++*******************************************************************************/ ++MV_STATUS ctrlWinOverlapTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2) ++{ ++ MV_U32 winBase1, winBase2; ++ MV_U32 winTop1, winTop2; ++ ++ /* check if we have overflow than 4G*/ ++ if (((0xffffffff - pAddrWin1->baseLow) < pAddrWin1->size-1)|| ++ ((0xffffffff - pAddrWin2->baseLow) < pAddrWin2->size-1)) ++ { ++ return MV_TRUE; ++ } ++ ++ winBase1 = pAddrWin1->baseLow; ++ winBase2 = pAddrWin2->baseLow; ++ winTop1 = winBase1 + pAddrWin1->size-1; ++ winTop2 = winBase2 + pAddrWin2->size-1; ++ ++ ++ if (((winBase1 <= winTop2 ) && ( winTop2 <= winTop1)) || ++ ((winBase1 <= winBase2) && (winBase2 <= winTop1))) ++ { ++ return MV_TRUE; ++ } ++ else ++ { ++ return MV_FALSE; ++ } ++} ++ ++/******************************************************************************* ++* ctrlWinWithinWinTest - Test address windows for overlaping. ++* ++* DESCRIPTION: ++* This function checks the given win1 boundries is within ++* win2 boundries. ++* ++* INPUT: ++* pAddrWin1 - Address window 1. ++* pAddrWin2 - Address window 2. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++* MV_TRUE if found win1 inside win2, MV_FALSE otherwise. ++*******************************************************************************/ ++MV_STATUS ctrlWinWithinWinTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2) ++{ ++ MV_U32 winBase1, winBase2; ++ MV_U32 winTop1, winTop2; ++ ++ winBase1 = pAddrWin1->baseLow; ++ winBase2 = pAddrWin2->baseLow; ++ winTop1 = winBase1 + pAddrWin1->size -1; ++ winTop2 = winBase2 + pAddrWin2->size -1; ++ ++ if (((winBase1 >= winBase2 ) && ( winBase1 <= winTop2)) || ++ ((winTop1 >= winBase2) && (winTop1 <= winTop2))) ++ { ++ return MV_TRUE; ++ } ++ else ++ { ++ return MV_FALSE; ++ } ++} ++ ++static const char* cntrlName[] = TARGETS_NAME_ARRAY; ++ ++/******************************************************************************* ++* mvCtrlTargetNameGet - Get Marvell controller target name ++* ++* DESCRIPTION: ++* This function convert the trget enumeration to string. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Target name (const MV_8 *) ++*******************************************************************************/ ++const MV_8* mvCtrlTargetNameGet( MV_TARGET target ) ++{ ++ ++ if (target >= MAX_TARGETS) ++ { ++ return "target unknown"; ++ } ++ ++ return cntrlName[target]; ++} ++ ++/******************************************************************************* ++* mvCtrlAddrDecShow - Print the Controller units address decode map. ++* ++* DESCRIPTION: ++* This function the Controller units address decode map. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvCtrlAddrDecShow(MV_VOID) ++{ ++ mvCpuIfAddDecShow(); ++ mvAhbToMbusAddDecShow(); ++#if defined(MV_INCLUDE_PEX) ++ mvPexAddrDecShow(); ++#endif ++#if defined(MV_INCLUDE_USB) ++ mvUsbAddrDecShow(); ++#endif ++#if defined(MV_INCLUDE_GIG_ETH) ++ mvEthAddrDecShow(); ++#endif ++#if defined(MV_INCLUDE_XOR) ++ mvXorAddrDecShow(); ++#endif ++#if defined(MV_INCLUDE_SATA) ++ mvSataAddrDecShow(); ++#endif ++#if defined(MV_INCLUDE_AUDIO) ++ mvAudioAddrDecShow(); ++#endif ++#if defined(MV_INCLUDE_TS) ++ mvTsuAddrDecShow(); ++#endif ++} ++ ++/******************************************************************************* ++* ctrlSizeToReg - Extract size value for register assignment. ++* ++* DESCRIPTION: ++* Address decode size parameter must be programed from LSB to MSB as ++* sequence of 1's followed by sequence of 0's. The number of 1's ++* specifies the size of the window in 64 KB granularity (e.g. a ++* value of 0x00ff specifies 256x64k = 16 MB). ++* This function extract the size value from the size parameter according ++* to given aligment paramter. For example for size 0x1000000 (16MB) and ++* aligment 0x10000 (64KB) the function will return 0x00FF. ++* ++* INPUT: ++* size - Size. ++* alignment - Size alignment. Note that alignment must be power of 2! ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit describing size register value correspond to size parameter. ++* If value is '-1' size parameter or aligment are invalid. ++*******************************************************************************/ ++MV_U32 ctrlSizeToReg(MV_U32 size, MV_U32 alignment) ++{ ++ MV_U32 retVal; ++ ++ /* Check size parameter alignment */ ++ if ((0 == size) || (MV_IS_NOT_ALIGN(size, alignment))) ++ { ++ DB(mvOsPrintf("ctrlSizeToReg: ERR. Size is zero or not aligned.\n")); ++ return -1; ++ } ++ ++ /* Take out the "alignment" portion out of the size parameter */ ++ alignment--; /* Now the alignmet is a sequance of '1' (e.g. 0xffff) */ ++ /* and size is 0x1000000 (16MB) for example */ ++ while(alignment & 1) /* Check that alignmet LSB is set */ ++ { ++ size = (size >> 1); /* If LSB is set, move 'size' one bit to right */ ++ alignment = (alignment >> 1); ++ } ++ ++ /* If after the alignment first '0' was met we still have '1' in */ ++ /* it then aligment is invalid (not power of 2) */ ++ if (alignment) ++ { ++ DB(mvOsPrintf("ctrlSizeToReg: ERR. Alignment parameter 0x%x invalid.\n", ++ (MV_U32)alignment)); ++ return -1; ++ } ++ ++ /* Now the size is shifted right according to aligment: 0x0100 */ ++ size--; /* Now the size is a sequance of '1': 0x00ff */ ++ ++ retVal = size ; ++ ++ /* Check that LSB to MSB is sequence of 1's followed by sequence of 0's */ ++ while(size & 1) /* Check that LSB is set */ ++ { ++ size = (size >> 1); /* If LSB is set, move one bit to the right */ ++ } ++ ++ if (size) /* Sequance of 1's is over. Check that we have no other 1's */ ++ { ++ DB(mvOsPrintf("ctrlSizeToReg: ERR. Size parameter 0x%x invalid.\n", ++ size)); ++ return -1; ++ } ++ ++ return retVal; ++ ++} ++ ++/******************************************************************************* ++* ctrlRegToSize - Extract size value from register value. ++* ++* DESCRIPTION: ++* This function extract a size value from the register size parameter ++* according to given aligment paramter. For example for register size ++* value 0xff and aligment 0x10000 the function will return 0x01000000. ++* ++* INPUT: ++* regSize - Size as in register format. See ctrlSizeToReg. ++* alignment - Size alignment. Note that alignment must be power of 2! ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit describing size. ++* If value is '-1' size parameter or aligment are invalid. ++*******************************************************************************/ ++MV_U32 ctrlRegToSize(MV_U32 regSize, MV_U32 alignment) ++{ ++ MV_U32 temp; ++ ++ /* Check that LSB to MSB is sequence of 1's followed by sequence of 0's */ ++ temp = regSize; /* Now the size is a sequance of '1': 0x00ff */ ++ ++ while(temp & 1) /* Check that LSB is set */ ++ { ++ temp = (temp >> 1); /* If LSB is set, move one bit to the right */ ++ } ++ ++ if (temp) /* Sequance of 1's is over. Check that we have no other 1's */ ++ { ++ DB(mvOsPrintf("ctrlRegToSize: ERR. Size parameter 0x%x invalid.\n", ++ regSize)); ++ return -1; ++ } ++ ++ ++ /* Check that aligment is a power of two */ ++ temp = alignment - 1;/* Now the alignmet is a sequance of '1' (0xffff) */ ++ ++ while(temp & 1) /* Check that alignmet LSB is set */ ++ { ++ temp = (temp >> 1); /* If LSB is set, move 'size' one bit to right */ ++ } ++ ++ /* If after the 'temp' first '0' was met we still have '1' in 'temp' */ ++ /* then 'temp' is invalid (not power of 2) */ ++ if (temp) ++ { ++ DB(mvOsPrintf("ctrlSizeToReg: ERR. Alignment parameter 0x%x invalid.\n", ++ alignment)); ++ return -1; ++ } ++ ++ regSize++; /* Now the size is 0x0100 */ ++ ++ /* Add in the "alignment" portion to the register size parameter */ ++ alignment--; /* Now the alignmet is a sequance of '1' (e.g. 0xffff) */ ++ ++ while(alignment & 1) /* Check that alignmet LSB is set */ ++ { ++ regSize = (regSize << 1); /* LSB is set, move 'size' one bit left */ ++ alignment = (alignment >> 1); ++ } ++ ++ return regSize; ++} ++ ++ ++/******************************************************************************* ++* ctrlSizeRegRoundUp - Round up given size ++* ++* DESCRIPTION: ++* This function round up a given size to a size that fits the ++* restrictions of size format given an aligment parameter. ++* to given aligment paramter. For example for size parameter 0xa1000 and ++* aligment 0x1000 the function will return 0xFF000. ++* ++* INPUT: ++* size - Size. ++* alignment - Size alignment. Note that alignment must be power of 2! ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit describing size value correspond to size in register. ++*******************************************************************************/ ++MV_U32 ctrlSizeRegRoundUp(MV_U32 size, MV_U32 alignment) ++{ ++ MV_U32 msbBit = 0; ++ MV_U32 retSize; ++ ++ /* Check if size parameter is already comply with restriction */ ++ if (!(-1 == ctrlSizeToReg(size, alignment))) ++ { ++ return size; ++ } ++ ++ while(size) ++ { ++ size = (size >> 1); ++ msbBit++; ++ } ++ ++ retSize = (1 << msbBit); ++ ++ if (retSize < alignment) ++ { ++ return alignment; ++ } ++ else ++ { ++ return retSize; ++ } ++} ++/******************************************************************************* ++* mvCtrlSysRstLengthCounterGet - Return number of milliseconds the reset button ++* was pressed and clear counter ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: number of milliseconds the reset button was pressed ++*******************************************************************************/ ++MV_U32 mvCtrlSysRstLengthCounterGet(MV_VOID) ++{ ++ static volatile MV_U32 Count = 0; ++ ++ if(!Count) { ++ Count = (MV_REG_READ(SYSRST_LENGTH_COUNTER_REG) & SLCR_COUNT_MASK); ++ Count = (Count / (MV_BOARD_REFCLK_25MHZ / 1000)); ++ /* clear counter for next boot */ ++ MV_REG_BIT_SET(SYSRST_LENGTH_COUNTER_REG, SLCR_CLR_MASK); ++ } ++ ++ DB(mvOsPrintf("mvCtrlSysRstLengthCounterGet: Reset button was pressed for %u milliseconds\n", Count)); ++ ++ return Count; ++} ++ ++MV_BOOL mvCtrlIsBootFromSPI(MV_VOID) ++{ ++ MV_U32 satr = 0; ++ satr = MV_REG_READ(MPP_SAMPLE_AT_RESET); ++ if(mvCtrlModelGet() == MV_6180_DEV_ID) ++ { ++ if (MSAR_BOOT_MODE_6180(satr) == MSAR_BOOT_SPI_WITH_BOOTROM_6180) ++ return MV_TRUE; ++ else ++ return MV_FALSE; ++ } ++ satr = satr & MSAR_BOOT_MODE_MASK; ++ if (satr == MSAR_BOOT_SPI_WITH_BOOTROM) ++ return MV_TRUE; ++ else ++ return MV_FALSE; ++} ++ ++MV_BOOL mvCtrlIsBootFromSPIUseNAND(MV_VOID) ++{ ++ MV_U32 satr = 0; ++ if(mvCtrlModelGet() == MV_6180_DEV_ID) ++ return MV_FALSE; ++ satr = MV_REG_READ(MPP_SAMPLE_AT_RESET); ++ satr = satr & MSAR_BOOT_MODE_MASK; ++ ++ if (satr == MSAR_BOOT_SPI_USE_NAND_WITH_BOOTROM) ++ return MV_TRUE; ++ else ++ return MV_FALSE; ++} ++ ++MV_BOOL mvCtrlIsBootFromNAND(MV_VOID) ++{ ++ MV_U32 satr = 0; ++ satr = MV_REG_READ(MPP_SAMPLE_AT_RESET); ++ if(mvCtrlModelGet() == MV_6180_DEV_ID) ++ { ++ if (MSAR_BOOT_MODE_6180(satr) == MSAR_BOOT_NAND_WITH_BOOTROM_6180) ++ return MV_TRUE; ++ else ++ return MV_FALSE; ++ } ++ satr = satr & MSAR_BOOT_MODE_MASK; ++ if ((satr == MSAR_BOOT_NAND_WITH_BOOTROM)) ++ return MV_TRUE; ++ else ++ return MV_FALSE; ++} ++ ++#if defined(MV_INCLUDE_CLK_PWR_CNTRL) ++/******************************************************************************* ++* mvCtrlPwrSaveOn - Set Power save mode ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++*******************************************************************************/ ++MV_VOID mvCtrlPwrSaveOn(MV_VOID) ++{ ++ unsigned long old,temp; ++ /* Disable int */ ++ __asm__ __volatile__("mrs %0, cpsr\n" ++ "orr %1, %0, #0xc0\n" ++ "msr cpsr_c, %1" ++ : "=r" (old), "=r" (temp) ++ : ++ : "memory"); ++ ++ /* Set SoC in power save */ ++ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, BIT11); ++ /* Wait for int */ ++ __asm__ __volatile__("mcr p15, 0, r0, c7, c0, 4"); ++ ++ /* Enabled int */ ++ __asm__ __volatile__("msr cpsr_c, %0" ++ : ++ : "r" (old) ++ : "memory"); ++} ++ ++ ++ ++/******************************************************************************* ++* mvCtrlPwrSaveOff - Go out of power save mode ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++*******************************************************************************/ ++MV_VOID mvCtrlPwrSaveOff(MV_VOID) ++{ ++ unsigned long old,temp; ++ /* Disable int */ ++ __asm__ __volatile__("mrs %0, cpsr\n" ++ "orr %1, %0, #0xc0\n" ++ "msr cpsr_c, %1" ++ : "=r" (old), "=r" (temp) ++ : ++ : "memory"); ++ ++ /* Set SoC in power save */ ++ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, BIT11); ++ /* Wait for int */ ++ __asm__ __volatile__("mcr p15, 0, r0, c7, c0, 4"); ++ ++ /* Enabled int */ ++ __asm__ __volatile__("msr cpsr_c, %0" ++ : ++ : "r" (old) ++ : "memory"); ++} ++ ++/******************************************************************************* ++* mvCtrlPwrClckSet - Set Power State for specific Unit ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++*******************************************************************************/ ++MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) ++{ ++ switch (unitId) ++ { ++#if defined(MV_INCLUDE_PEX) ++ case PEX_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_PEXSTOPCLOCK_MASK); ++ } ++ else ++ { ++ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_PEXSTOPCLOCK_MASK); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_GIG_ETH) ++ case ETH_GIG_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_GESTOPCLOCK_MASK(index)); ++ } ++ else ++ { ++ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_GESTOPCLOCK_MASK(index)); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_INTEG_SATA) ++ case SATA_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SATASTOPCLOCK_MASK(index)); ++ } ++ else ++ { ++ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SATASTOPCLOCK_MASK(index)); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_CESA) ++ case CESA_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SESTOPCLOCK_MASK); ++ } ++ else ++ { ++ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SESTOPCLOCK_MASK); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_USB) ++ case USB_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_USBSTOPCLOCK_MASK); ++ } ++ else ++ { ++ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_USBSTOPCLOCK_MASK); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_AUDIO) ++ case AUDIO_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_AUDIOSTOPCLOCK_MASK); ++ } ++ else ++ { ++ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_AUDIOSTOPCLOCK_MASK); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_TS) ++ case TS_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_TSSTOPCLOCK_MASK); ++ } ++ else ++ { ++ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_TSSTOPCLOCK_MASK); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_SDIO) ++ case SDIO_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SDIOSTOPCLOCK_MASK); ++ } ++ else ++ { ++ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SDIOSTOPCLOCK_MASK); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_TDM) ++ case TDM_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_TDMSTOPCLOCK_MASK); ++ } ++ else ++ { ++ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_TDMSTOPCLOCK_MASK); ++ } ++ break; ++#endif ++ ++ default: ++ ++ break; ++ ++ } ++} ++ ++/******************************************************************************* ++* mvCtrlPwrClckGet - Get Power State of specific Unit ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++******************************************************************************/ ++MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index) ++{ ++ MV_U32 reg = MV_REG_READ(POWER_MNG_CTRL_REG); ++ MV_BOOL state = MV_TRUE; ++ ++ switch (unitId) ++ { ++#if defined(MV_INCLUDE_PEX) ++ case PEX_UNIT_ID: ++ if ((reg & PMC_PEXSTOPCLOCK_MASK) == PMC_PEXSTOPCLOCK_STOP) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ ++ break; ++#endif ++#if defined(MV_INCLUDE_GIG_ETH) ++ case ETH_GIG_UNIT_ID: ++ if ((reg & PMC_GESTOPCLOCK_MASK(index)) == PMC_GESTOPCLOCK_STOP(index)) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++#if defined(MV_INCLUDE_SATA) ++ case SATA_UNIT_ID: ++ if ((reg & PMC_SATASTOPCLOCK_MASK(index)) == PMC_SATASTOPCLOCK_STOP(index)) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++#if defined(MV_INCLUDE_CESA) ++ case CESA_UNIT_ID: ++ if ((reg & PMC_SESTOPCLOCK_MASK) == PMC_SESTOPCLOCK_STOP) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++#if defined(MV_INCLUDE_USB) ++ case USB_UNIT_ID: ++ if ((reg & PMC_USBSTOPCLOCK_MASK) == PMC_USBSTOPCLOCK_STOP) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++#if defined(MV_INCLUDE_AUDIO) ++ case AUDIO_UNIT_ID: ++ if ((reg & PMC_AUDIOSTOPCLOCK_MASK) == PMC_AUDIOSTOPCLOCK_STOP) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++#if defined(MV_INCLUDE_TS) ++ case TS_UNIT_ID: ++ if ((reg & PMC_TSSTOPCLOCK_MASK) == PMC_TSSTOPCLOCK_STOP) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++#if defined(MV_INCLUDE_SDIO) ++ case SDIO_UNIT_ID: ++ if ((reg & PMC_SDIOSTOPCLOCK_MASK)== PMC_SDIOSTOPCLOCK_STOP) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++#if defined(MV_INCLUDE_TDM) ++ case TDM_UNIT_ID: ++ if ((reg & PMC_TDMSTOPCLOCK_MASK) == PMC_TDMSTOPCLOCK_STOP) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++ ++ default: ++ state = MV_TRUE; ++ break; ++ } ++ ++ ++ return state; ++} ++/******************************************************************************* ++* mvCtrlPwrMemSet - Set Power State for memory on specific Unit ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++*******************************************************************************/ ++MV_VOID mvCtrlPwrMemSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) ++{ ++ switch (unitId) ++ { ++#if defined(MV_INCLUDE_PEX) ++ case PEX_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_PEXSTOPMEM_MASK); ++ } ++ else ++ { ++ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_PEXSTOPMEM_MASK); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_GIG_ETH) ++ case ETH_GIG_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_GESTOPMEM_MASK(index)); ++ } ++ else ++ { ++ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_GESTOPMEM_MASK(index)); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_INTEG_SATA) ++ case SATA_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_SATASTOPMEM_MASK(index)); ++ } ++ else ++ { ++ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_SATASTOPMEM_MASK(index)); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_CESA) ++ case CESA_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_SESTOPMEM_MASK); ++ } ++ else ++ { ++ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_SESTOPMEM_MASK); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_USB) ++ case USB_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_USBSTOPMEM_MASK); ++ } ++ else ++ { ++ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_USBSTOPMEM_MASK); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_AUDIO) ++ case AUDIO_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_AUDIOSTOPMEM_MASK); ++ } ++ else ++ { ++ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_AUDIOSTOPMEM_MASK); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_XOR) ++ case XOR_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_XORSTOPMEM_MASK(index)); ++ } ++ else ++ { ++ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_XORSTOPMEM_MASK(index)); ++ } ++ break; ++#endif ++ default: ++ ++ break; ++ ++ } ++} ++ ++/******************************************************************************* ++* mvCtrlPwrMemGet - Get Power State of memory on specific Unit ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++******************************************************************************/ ++MV_BOOL mvCtrlPwrMemGet(MV_UNIT_ID unitId, MV_U32 index) ++{ ++ MV_U32 reg = MV_REG_READ(POWER_MNG_MEM_CTRL_REG); ++ MV_BOOL state = MV_TRUE; ++ ++ switch (unitId) ++ { ++#if defined(MV_INCLUDE_PEX) ++ case PEX_UNIT_ID: ++ if ((reg & PMC_PEXSTOPMEM_MASK) == PMC_PEXSTOPMEM_STOP) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ ++ break; ++#endif ++#if defined(MV_INCLUDE_GIG_ETH) ++ case ETH_GIG_UNIT_ID: ++ if ((reg & PMC_GESTOPMEM_MASK(index)) == PMC_GESTOPMEM_STOP(index)) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++#if defined(MV_INCLUDE_SATA) ++ case SATA_UNIT_ID: ++ if ((reg & PMC_SATASTOPMEM_MASK(index)) == PMC_SATASTOPMEM_STOP(index)) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++#if defined(MV_INCLUDE_CESA) ++ case CESA_UNIT_ID: ++ if ((reg & PMC_SESTOPMEM_MASK) == PMC_SESTOPMEM_STOP) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++#if defined(MV_INCLUDE_USB) ++ case USB_UNIT_ID: ++ if ((reg & PMC_USBSTOPMEM_MASK) == PMC_USBSTOPMEM_STOP) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++#if defined(MV_INCLUDE_AUDIO) ++ case AUDIO_UNIT_ID: ++ if ((reg & PMC_AUDIOSTOPMEM_MASK) == PMC_AUDIOSTOPMEM_STOP) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++#if defined(MV_INCLUDE_XOR) ++ case XOR_UNIT_ID: ++ if ((reg & PMC_XORSTOPMEM_MASK(index)) == PMC_XORSTOPMEM_STOP(index)) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++ ++ default: ++ state = MV_TRUE; ++ break; ++ } ++ ++ ++ return state; ++} ++#else ++MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) {return;} ++MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index) {return MV_TRUE;} ++#endif /* #if defined(MV_INCLUDE_CLK_PWR_CNTRL) */ ++ ++ ++/******************************************************************************* ++* mvMPPConfigToSPI - Change MPP[3:0] configuration to SPI mode ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++******************************************************************************/ ++MV_VOID mvMPPConfigToSPI(MV_VOID) ++{ ++ MV_U32 mppVal = 0; ++ MV_U32 bootVal = 0; ++ ++ if(!mvCtrlIsBootFromSPIUseNAND()) ++ return; ++ mppVal = 0x00002220; /* Set MPP [3:1] to SPI mode */ ++ bootVal = MV_REG_READ(mvCtrlMppRegGet(0)); ++ bootVal &= 0xffff000f; ++ mppVal |= bootVal; ++ ++ MV_REG_WRITE(mvCtrlMppRegGet(0), mppVal); ++} ++ ++ ++/******************************************************************************* ++* mvMPPConfigToDefault - Change MPP[7:0] configuration to default configuration ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++******************************************************************************/ ++MV_VOID mvMPPConfigToDefault(MV_VOID) ++{ ++ MV_U32 mppVal = 0; ++ MV_U32 bootVal = 0; ++ ++ if(!mvCtrlIsBootFromSPIUseNAND()) ++ return; ++ mppVal = mvBoardMppGet(0); ++ bootVal = MV_REG_READ(mvCtrlMppRegGet(0)); ++ mppVal &= ~0xffff000f; ++ bootVal &= 0xffff000f; ++ mppVal |= bootVal; ++ ++ MV_REG_WRITE(mvCtrlMppRegGet(0), mppVal); ++} ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,185 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvCtrlEnvLibh ++#define __INCmvCtrlEnvLibh ++ ++/* includes */ ++#include "mvSysHwConfig.h" ++#include "mvCommon.h" ++#include "mvTypes.h" ++#include "mvOs.h" ++#include "boardEnv/mvBoardEnvLib.h" ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++#include "ctrlEnv/mvCtrlEnvRegs.h" ++#include "ctrlEnv/mvCtrlEnvAddrDec.h" ++ ++ ++/* typedefs */ ++ ++/* This enumerator describes the possible HW cache coherency policies the */ ++/* controllers supports. */ ++typedef enum _mvCachePolicy ++{ ++ NO_COHERENCY, /* No HW cache coherency support */ ++ WT_COHERENCY, /* HW cache coherency supported in Write Through policy */ ++ WB_COHERENCY /* HW cache coherency supported in Write Back policy */ ++}MV_CACHE_POLICY; ++ ++ ++/* The swapping is referred to a 64-bit words (as this is the controller */ ++/* internal data path width). This enumerator describes the possible */ ++/* data swap types. Below is an example of the data 0x0011223344556677 */ ++typedef enum _mvSwapType ++{ ++ MV_BYTE_SWAP, /* Byte Swap 77 66 55 44 33 22 11 00 */ ++ MV_NO_SWAP, /* No swapping 00 11 22 33 44 55 66 77 */ ++ MV_BYTE_WORD_SWAP, /* Both byte and word swap 33 22 11 00 77 66 55 44 */ ++ MV_WORD_SWAP, /* Word swap 44 55 66 77 00 11 22 33 */ ++ SWAP_TYPE_MAX /* Delimiter for this enumerator */ ++}MV_SWAP_TYPE; ++ ++/* This structure describes access rights for Access protection windows */ ++/* that can be found in IDMA, XOR, Ethernet and MPSC units. */ ++/* Note that the permission enumerator coresponds to its register format. */ ++/* For example, Read only premission is presented as "1" in register field. */ ++typedef enum _mvAccessRights ++{ ++ NO_ACCESS_ALLOWED = 0, /* No access allowed */ ++ READ_ONLY = 1, /* Read only permission */ ++ ACC_RESERVED = 2, /* Reserved access right */ ++ FULL_ACCESS = 3, /* Read and Write permission */ ++ MAX_ACC_RIGHTS ++}MV_ACCESS_RIGHTS; ++ ++ ++/* mcspLib.h API list */ ++ ++MV_STATUS mvCtrlEnvInit(MV_VOID); ++MV_U32 mvCtrlMppRegGet(MV_U32 mppGroup); ++ ++#if defined(MV_INCLUDE_PEX) ++MV_U32 mvCtrlPexMaxIfGet(MV_VOID); ++#else ++#define mvCtrlPexMaxIfGet() (0) ++#endif ++ ++#define mvCtrlPciIfMaxIfGet() (0) ++ ++#if defined(MV_INCLUDE_GIG_ETH) ++MV_U32 mvCtrlEthMaxPortGet(MV_VOID); ++#endif ++#if defined(MV_INCLUDE_XOR) ++MV_U32 mvCtrlXorMaxChanGet(MV_VOID); ++#endif ++#if defined(MV_INCLUDE_USB) ++MV_U32 mvCtrlUsbMaxGet(MV_VOID); ++#endif ++#if defined(MV_INCLUDE_NAND) ++MV_U32 mvCtrlNandSupport(MV_VOID); ++#endif ++#if defined(MV_INCLUDE_SDIO) ++MV_U32 mvCtrlSdioSupport(MV_VOID); ++#endif ++#if defined(MV_INCLUDE_TS) ++MV_U32 mvCtrlTsSupport(MV_VOID); ++#endif ++#if defined(MV_INCLUDE_AUDIO) ++MV_U32 mvCtrlAudioSupport(MV_VOID); ++#endif ++#if defined(MV_INCLUDE_TDM) ++MV_U32 mvCtrlTdmSupport(MV_VOID); ++#endif ++ ++MV_U16 mvCtrlModelGet(MV_VOID); ++MV_U8 mvCtrlRevGet(MV_VOID); ++MV_STATUS mvCtrlNameGet(char *pNameBuff); ++MV_U32 mvCtrlModelRevGet(MV_VOID); ++MV_STATUS mvCtrlModelRevNameGet(char *pNameBuff); ++MV_VOID mvCtrlAddrDecShow(MV_VOID); ++const MV_8* mvCtrlTargetNameGet(MV_TARGET target); ++MV_U32 ctrlSizeToReg(MV_U32 size, MV_U32 alignment); ++MV_U32 ctrlRegToSize(MV_U32 regSize, MV_U32 alignment); ++MV_U32 ctrlSizeRegRoundUp(MV_U32 size, MV_U32 alignment); ++MV_U32 mvCtrlSysRstLengthCounterGet(MV_VOID); ++MV_STATUS ctrlWinOverlapTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2); ++MV_STATUS ctrlWinWithinWinTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2); ++ ++MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable); ++MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index); ++MV_VOID mvCtrlPwrMemSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable); ++MV_BOOL mvCtrlIsBootFromSPI(MV_VOID); ++MV_BOOL mvCtrlIsBootFromSPIUseNAND(MV_VOID); ++MV_BOOL mvCtrlIsBootFromNAND(MV_VOID); ++#if defined(MV_INCLUDE_CLK_PWR_CNTRL) ++MV_VOID mvCtrlPwrSaveOn(MV_VOID); ++MV_VOID mvCtrlPwrSaveOff(MV_VOID); ++#endif ++MV_BOOL mvCtrlPwrMemGet(MV_UNIT_ID unitId, MV_U32 index); ++MV_VOID mvMPPConfigToSPI(MV_VOID); ++MV_VOID mvMPPConfigToDefault(MV_VOID); ++ ++ ++#endif /* __INCmvCtrlEnvLibh */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,419 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvCtrlEnvRegsh ++#define __INCmvCtrlEnvRegsh ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++/* CV Support */ ++#define PEX0_MEM0 PEX0_MEM ++#define PCI0_MEM0 PEX0_MEM ++ ++/* Controller revision info */ ++#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 ++#define PCCRIR_REVID_OFFS 0 /* Revision ID */ ++#define PCCRIR_REVID_MASK (0xff << PCCRIR_REVID_OFFS) ++ ++/* Controler environment registers offsets */ ++ ++/* Power Managment Control */ ++#define POWER_MNG_MEM_CTRL_REG 0x20118 ++ ++#define PMC_GESTOPMEM_OFFS(port) ((port)? 13 : 0) ++#define PMC_GESTOPMEM_MASK(port) (1 << PMC_GESTOPMEM_OFFS(port)) ++#define PMC_GESTOPMEM_EN(port) (0 << PMC_GESTOPMEM_OFFS(port)) ++#define PMC_GESTOPMEM_STOP(port) (1 << PMC_GESTOPMEM_OFFS(port)) ++ ++#define PMC_PEXSTOPMEM_OFFS 1 ++#define PMC_PEXSTOPMEM_MASK (1 << PMC_PEXSTOPMEM_OFFS) ++#define PMC_PEXSTOPMEM_EN (0 << PMC_PEXSTOPMEM_OFFS) ++#define PMC_PEXSTOPMEM_STOP (1 << PMC_PEXSTOPMEM_OFFS) ++ ++#define PMC_USBSTOPMEM_OFFS 2 ++#define PMC_USBSTOPMEM_MASK (1 << PMC_USBSTOPMEM_OFFS) ++#define PMC_USBSTOPMEM_EN (0 << PMC_USBSTOPMEM_OFFS) ++#define PMC_USBSTOPMEM_STOP (1 << PMC_USBSTOPMEM_OFFS) ++ ++#define PMC_DUNITSTOPMEM_OFFS 3 ++#define PMC_DUNITSTOPMEM_MASK (1 << PMC_DUNITSTOPMEM_OFFS) ++#define PMC_DUNITSTOPMEM_EN (0 << PMC_DUNITSTOPMEM_OFFS) ++#define PMC_DUNITSTOPMEM_STOP (1 << PMC_DUNITSTOPMEM_OFFS) ++ ++#define PMC_RUNITSTOPMEM_OFFS 4 ++#define PMC_RUNITSTOPMEM_MASK (1 << PMC_RUNITSTOPMEM_OFFS) ++#define PMC_RUNITSTOPMEM_EN (0 << PMC_RUNITSTOPMEM_OFFS) ++#define PMC_RUNITSTOPMEM_STOP (1 << PMC_RUNITSTOPMEM_OFFS) ++ ++#define PMC_XORSTOPMEM_OFFS(port) (5+(port*2)) ++#define PMC_XORSTOPMEM_MASK(port) (1 << PMC_XORSTOPMEM_OFFS(port)) ++#define PMC_XORSTOPMEM_EN(port) (0 << PMC_XORSTOPMEM_OFFS(port)) ++#define PMC_XORSTOPMEM_STOP(port) (1 << PMC_XORSTOPMEM_OFFS(port)) ++ ++#define PMC_SATASTOPMEM_OFFS(port) (6+(port*5)) ++#define PMC_SATASTOPMEM_MASK(port) (1 << PMC_SATASTOPMEM_OFFS(port)) ++#define PMC_SATASTOPMEM_EN(port) (0 << PMC_SATASTOPMEM_OFFS(port)) ++#define PMC_SATASTOPMEM_STOP(port) (1 << PMC_SATASTOPMEM_OFFS(port)) ++ ++#define PMC_SESTOPMEM_OFFS 8 ++#define PMC_SESTOPMEM_MASK (1 << PMC_SESTOPMEM_OFFS) ++#define PMC_SESTOPMEM_EN (0 << PMC_SESTOPMEM_OFFS) ++#define PMC_SESTOPMEM_STOP (1 << PMC_SESTOPMEM_OFFS) ++ ++#define PMC_AUDIOSTOPMEM_OFFS 9 ++#define PMC_AUDIOSTOPMEM_MASK (1 << PMC_AUDIOSTOPMEM_OFFS) ++#define PMC_AUDIOSTOPMEM_EN (0 << PMC_AUDIOSTOPMEM_OFFS) ++#define PMC_AUDIOSTOPMEM_STOP (1 << PMC_AUDIOSTOPMEM_OFFS) ++ ++#define POWER_MNG_CTRL_REG 0x2011C ++ ++#define PMC_GESTOPCLOCK_OFFS(port) ((port)? 19 : 0) ++#define PMC_GESTOPCLOCK_MASK(port) (1 << PMC_GESTOPCLOCK_OFFS(port)) ++#define PMC_GESTOPCLOCK_EN(port) (1 << PMC_GESTOPCLOCK_OFFS(port)) ++#define PMC_GESTOPCLOCK_STOP(port) (0 << PMC_GESTOPCLOCK_OFFS(port)) ++ ++#define PMC_PEXPHYSTOPCLOCK_OFFS 1 ++#define PMC_PEXPHYSTOPCLOCK_MASK (1 << PMC_PEXPHYSTOPCLOCK_OFFS) ++#define PMC_PEXPHYSTOPCLOCK_EN (1 << PMC_PEXPHYSTOPCLOCK_OFFS) ++#define PMC_PEXPHYSTOPCLOCK_STOP (0 << PMC_PEXPHYSTOPCLOCK_OFFS) ++ ++#define PMC_PEXSTOPCLOCK_OFFS 2 ++#define PMC_PEXSTOPCLOCK_MASK (1 << PMC_PEXSTOPCLOCK_OFFS) ++#define PMC_PEXSTOPCLOCK_EN (1 << PMC_PEXSTOPCLOCK_OFFS) ++#define PMC_PEXSTOPCLOCK_STOP (0 << PMC_PEXSTOPCLOCK_OFFS) ++ ++#define PMC_USBSTOPCLOCK_OFFS 3 ++#define PMC_USBSTOPCLOCK_MASK (1 << PMC_USBSTOPCLOCK_OFFS) ++#define PMC_USBSTOPCLOCK_EN (1 << PMC_USBSTOPCLOCK_OFFS) ++#define PMC_USBSTOPCLOCK_STOP (0 << PMC_USBSTOPCLOCK_OFFS) ++ ++#define PMC_SDIOSTOPCLOCK_OFFS 4 ++#define PMC_SDIOSTOPCLOCK_MASK (1 << PMC_SDIOSTOPCLOCK_OFFS) ++#define PMC_SDIOSTOPCLOCK_EN (1 << PMC_SDIOSTOPCLOCK_OFFS) ++#define PMC_SDIOSTOPCLOCK_STOP (0 << PMC_SDIOSTOPCLOCK_OFFS) ++ ++#define PMC_TSSTOPCLOCK_OFFS 5 ++#define PMC_TSSTOPCLOCK_MASK (1 << PMC_TSSTOPCLOCK_OFFS) ++#define PMC_TSSTOPCLOCK_EN (1 << PMC_TSSTOPCLOCK_OFFS) ++#define PMC_TSSTOPCLOCK_STOP (0 << PMC_TSSTOPCLOCK_OFFS) ++ ++#define PMC_AUDIOSTOPCLOCK_OFFS 9 ++#define PMC_AUDIOSTOPCLOCK_MASK (1 << PMC_AUDIOSTOPCLOCK_OFFS) ++#define PMC_AUDIOSTOPCLOCK_EN (1 << PMC_AUDIOSTOPCLOCK_OFFS) ++#define PMC_AUDIOSTOPCLOCK_STOP (0 << PMC_AUDIOSTOPCLOCK_OFFS) ++ ++#define PMC_POWERSAVE_OFFS 11 ++#define PMC_POWERSAVE_MASK (1 << PMC_POWERSAVE_OFFS) ++#define PMC_POWERSAVE_EN (1 << PMC_POWERSAVE_OFFS) ++#define PMC_POWERSAVE_STOP (0 << PMC_POWERSAVE_OFFS) ++ ++ ++ ++ ++#define PMC_SATASTOPCLOCK_OFFS(port) (14+(port)) ++#define PMC_SATASTOPCLOCK_MASK(port) (1 << PMC_SATASTOPCLOCK_OFFS(port)) ++#define PMC_SATASTOPCLOCK_EN(port) (1 << PMC_SATASTOPCLOCK_OFFS(port)) ++#define PMC_SATASTOPCLOCK_STOP(port) (0 << PMC_SATASTOPCLOCK_OFFS(port)) ++ ++#define PMC_SESTOPCLOCK_OFFS 17 ++#define PMC_SESTOPCLOCK_MASK (1 << PMC_SESTOPCLOCK_OFFS) ++#define PMC_SESTOPCLOCK_EN (1 << PMC_SESTOPCLOCK_OFFS) ++#define PMC_SESTOPCLOCK_STOP (0 << PMC_SESTOPCLOCK_OFFS) ++ ++#define PMC_TDMSTOPCLOCK_OFFS 20 ++#define PMC_TDMSTOPCLOCK_MASK (1 << PMC_TDMSTOPCLOCK_OFFS) ++#define PMC_TDMSTOPCLOCK_EN (1 << PMC_TDMSTOPCLOCK_OFFS) ++#define PMC_TDMSTOPCLOCK_STOP (0 << PMC_TDMSTOPCLOCK_OFFS) ++ ++ ++/* Controler environment registers offsets */ ++#define MPP_CONTROL_REG0 0x10000 ++#define MPP_CONTROL_REG1 0x10004 ++#define MPP_CONTROL_REG2 0x10008 ++#define MPP_CONTROL_REG3 0x1000C ++#define MPP_CONTROL_REG4 0x10010 ++#define MPP_CONTROL_REG5 0x10014 ++#define MPP_CONTROL_REG6 0x10018 ++#define MPP_SAMPLE_AT_RESET 0x10030 ++#define CHIP_BOND_REG 0x10034 ++#define SYSRST_LENGTH_COUNTER_REG 0x10050 ++#define SLCR_COUNT_OFFS 0 ++#define SLCR_COUNT_MASK (0x1FFFFFFF << SLCR_COUNT_OFFS) ++#define SLCR_CLR_OFFS 31 ++#define SLCR_CLR_MASK (1 << SLCR_CLR_OFFS) ++#define PCKG_OPT_MASK 0x3 ++#define MPP_OUTPUT_DRIVE_REG 0x100E0 ++#define MPP_RGMII0_OUTPUT_DRIVE_OFFS 7 ++#define MPP_3_3_RGMII0_OUTPUT_DRIVE (0x0 << MPP_RGMII0_OUTPUT_DRIVE_OFFS) ++#define MPP_1_8_RGMII0_OUTPUT_DRIVE (0x1 << MPP_RGMII0_OUTPUT_DRIVE_OFFS) ++#define MPP_RGMII1_OUTPUT_DRIVE_OFFS 15 ++#define MPP_3_3_RGMII1_OUTPUT_DRIVE (0x0 << MPP_RGMII1_OUTPUT_DRIVE_OFFS) ++#define MPP_1_8_RGMII1_OUTPUT_DRIVE (0x1 << MPP_RGMII1_OUTPUT_DRIVE_OFFS) ++ ++#define MSAR_BOOT_MODE_OFFS 12 ++#define MSAR_BOOT_MODE_MASK (0x7 << MSAR_BOOT_MODE_OFFS) ++#define MSAR_BOOT_NAND_WITH_BOOTROM (0x5 << MSAR_BOOT_MODE_OFFS) ++#define MSAR_BOOT_SPI_WITH_BOOTROM (0x4 << MSAR_BOOT_MODE_OFFS) ++#define MSAR_BOOT_SPI_USE_NAND_WITH_BOOTROM (0x2 << MSAR_BOOT_MODE_OFFS) ++ ++#define MSAR_BOOT_MODE_6180(X) (((X & 0x3000) >> 12) | \ ++ ((X & 0x2) << 1)) ++#define MSAR_BOOT_SPI_WITH_BOOTROM_6180 0x1 ++#define MSAR_BOOT_NAND_WITH_BOOTROM_6180 0x5 ++ ++#define MSAR_TCLCK_OFFS 21 ++#define MSAR_TCLCK_MASK (0x1 << MSAR_TCLCK_OFFS) ++#define MSAR_TCLCK_166 (0x1 << MSAR_TCLCK_OFFS) ++#define MSAR_TCLCK_200 (0x0 << MSAR_TCLCK_OFFS) ++ ++ ++#define MSAR_CPUCLCK_EXTRACT(X) (((X & 0x2) >> 1) | ((X & 0x400000) >> 21) | \ ++ ((X & 0x18) >> 1)) ++ ++#define MSAR_CPUCLCK_OFFS_6180 2 ++#define MSAR_CPUCLCK_MASK_6180 (0x7 << MSAR_CPUCLCK_OFFS_6180) ++ ++#define MSAR_DDRCLCK_RTIO_OFFS 5 ++#define MSAR_DDRCLCK_RTIO_MASK (0xF << MSAR_DDRCLCK_RTIO_OFFS) ++ ++#define MSAR_L2CLCK_EXTRACT(X) (((X & 0x600) >> 9) | ((X & 0x80000) >> 17)) ++ ++#ifndef MV_ASMLANGUAGE ++/* CPU clock for 6281,6192 0->Resereved */ ++#define MV_CPU_CLCK_TBL { 0, 0, 0, 0, \ ++ 600000000, 0, 800000000, 1000000000, \ ++ 0, 1200000000, 0, 0, \ ++ 1500000000, 0, 0, 0} ++ ++/* DDR clock RATIO for 6281,6192 {0,0}->Reserved */ ++#define MV_DDR_CLCK_RTIO_TBL {\ ++ {0, 0}, {0, 0}, {2, 1}, {0, 0}, \ ++ {3, 1}, {0, 0}, {4, 1}, {9, 2}, \ ++ {5, 1}, {6, 1}, {0, 0}, {0, 0}, \ ++ {0, 0}, {0, 0}, {0, 0}, {0, 0} \ ++} ++ ++/* L2 clock RATIO for 6281,6192 {1,1}->Reserved */ ++#define MV_L2_CLCK_RTIO_TBL {\ ++ {0, 0}, {2, 1}, {0, 0}, {3, 1}, \ ++ {0, 0}, {0, 0}, {0, 0}, {0, 0} \ ++} ++ ++/* 6180 have different clk reset sampling */ ++/* ARM CPU, DDR, L2 clock for 6180 {0,0,0}->Reserved */ ++#define MV_CPU6180_DDR_L2_CLCK_TBL { \ ++ {0, 0, 0 },\ ++ {0, 0, 0 },\ ++ {0, 0, 0 },\ ++ {0, 0, 0 },\ ++ {0, 0, 0 },\ ++ {600000000, 200000000, 300000000 },\ ++ {800000000, 200000000, 400000000 },\ ++ {0, 0, 0 }\ ++} ++ ++ ++ ++/* These macros help units to identify a target Mbus Arbiter group */ ++#define MV_TARGET_IS_DRAM(target) \ ++ ((target >= SDRAM_CS0) && (target <= SDRAM_CS3)) ++ ++#define MV_TARGET_IS_PEX0(target) \ ++ ((target >= PEX0_MEM) && (target <= PEX0_IO)) ++ ++#define MV_TARGET_IS_PEX1(target) 0 ++ ++#define MV_TARGET_IS_PEX(target) (MV_TARGET_IS_PEX0(target) || MV_TARGET_IS_PEX1(target)) ++ ++#define MV_TARGET_IS_DEVICE(target) \ ++ ((target >= DEVICE_CS0) && (target <= DEVICE_CS3)) ++ ++#define MV_PCI_DRAM_BAR_TO_DRAM_TARGET(bar) 0 ++ ++#define MV_TARGET_IS_AS_BOOT(target) ((target) == (sampleAtResetTargetArray[ \ ++ (mvCtrlModelGet() == MV_6180_DEV_ID)? MSAR_BOOT_MODE_6180 \ ++ (MV_REG_READ(MPP_SAMPLE_AT_RESET)):((MV_REG_READ(MPP_SAMPLE_AT_RESET)\ ++ & MSAR_BOOT_MODE_MASK) >> MSAR_BOOT_MODE_OFFS)])) ++ ++ ++#define MV_CHANGE_BOOT_CS(target) (((target) == DEV_BOOCS)?\ ++ sampleAtResetTargetArray[(mvCtrlModelGet() == MV_6180_DEV_ID)? \ ++ MSAR_BOOT_MODE_6180(MV_REG_READ(MPP_SAMPLE_AT_RESET)): \ ++ ((MV_REG_READ(MPP_SAMPLE_AT_RESET) & MSAR_BOOT_MODE_MASK)\ ++ >> MSAR_BOOT_MODE_OFFS)]:(target)) ++ ++#define TCLK_TO_COUNTER_RATIO 1 /* counters running in Tclk */ ++ ++#define BOOT_TARGETS_NAME_ARRAY { \ ++ TBL_TERM, \ ++ TBL_TERM, \ ++ BOOT_ROM_CS, \ ++ TBL_TERM, \ ++ BOOT_ROM_CS, \ ++ BOOT_ROM_CS, \ ++ TBL_TERM, \ ++ TBL_TERM \ ++} ++ ++#define BOOT_TARGETS_NAME_ARRAY_6180 { \ ++ TBL_TERM, \ ++ BOOT_ROM_CS, \ ++ TBL_TERM, \ ++ TBL_TERM, \ ++ TBL_TERM, \ ++ BOOT_ROM_CS, \ ++ TBL_TERM, \ ++ TBL_TERM \ ++} ++ ++ ++/* For old competability */ ++#define DEVICE_CS0 NFLASH_CS ++#define DEVICE_CS1 SPI_CS ++#define DEVICE_CS2 BOOT_ROM_CS ++#define DEVICE_CS3 DEV_BOOCS ++#define MV_BOOTDEVICE_INDEX 0 ++ ++#define START_DEV_CS DEV_CS0 ++#define DEV_TO_TARGET(dev) ((dev) + DEVICE_CS0) ++ ++#define PCI_IF0_MEM0 PEX0_MEM ++#define PCI_IF0_IO PEX0_IO ++ ++ ++/* This enumerator defines the Marvell controller target ID */ ++typedef enum _mvTargetId ++{ ++ DRAM_TARGET_ID = 0 , /* Port 0 -> DRAM interface */ ++ DEV_TARGET_ID = 1, /* Port 1 -> Nand/SPI */ ++ PEX0_TARGET_ID = 4 , /* Port 4 -> PCI Express0 */ ++ CRYPT_TARGET_ID = 3 , /* Port 3 --> Crypto Engine */ ++ SAGE_TARGET_ID = 12 , /* Port 12 -> SAGE Unit */ ++ MAX_TARGETS_ID ++}MV_TARGET_ID; ++ ++ ++/* This enumerator described the possible Controller paripheral targets. */ ++/* Controller peripherals are designated memory/IO address spaces that the */ ++/* controller can access. They are also refered as "targets" */ ++typedef enum _mvTarget ++{ ++ TBL_TERM = -1, /* none valid target, used as targets list terminator*/ ++ SDRAM_CS0, /* SDRAM chip select 0 */ ++ SDRAM_CS1, /* SDRAM chip select 1 */ ++ SDRAM_CS2, /* SDRAM chip select 2 */ ++ SDRAM_CS3, /* SDRAM chip select 3 */ ++ PEX0_MEM, /* PCI Express 0 Memory */ ++ PEX0_IO, /* PCI Express 0 IO */ ++ INTER_REGS, /* Internal registers */ ++ NFLASH_CS, /* NFLASH_CS */ ++ SPI_CS, /* SPI_CS */ ++ BOOT_ROM_CS, /* BOOT_ROM_CS */ ++ DEV_BOOCS, /* DEV_BOOCS */ ++ CRYPT_ENG, /* Crypto Engine */ ++#ifdef MV_INCLUDE_SAGE ++ SAGE_UNIT, /* SAGE Unit */ ++#endif ++ MAX_TARGETS ++ ++}MV_TARGET; ++ ++#define TARGETS_DEF_ARRAY { \ ++ {0x0E, DRAM_TARGET_ID }, /* SDRAM_CS0 */ \ ++ {0x0D, DRAM_TARGET_ID }, /* SDRAM_CS1 */ \ ++ {0x0B, DRAM_TARGET_ID }, /* SDRAM_CS0 */ \ ++ {0x07, DRAM_TARGET_ID }, /* SDRAM_CS1 */ \ ++ {0xE8, PEX0_TARGET_ID }, /* PEX0_MEM */ \ ++ {0xE0, PEX0_TARGET_ID }, /* PEX0_IO */ \ ++ {0xFF, 0xFF }, /* INTER_REGS */ \ ++ {0x2F, DEV_TARGET_ID }, /* NFLASH_CS */ \ ++ {0x1E, DEV_TARGET_ID }, /* SPI_CS */ \ ++ {0x1D, DEV_TARGET_ID }, /* BOOT_ROM_CS */ \ ++ {0x1E, DEV_TARGET_ID }, /* DEV_BOOCS */ \ ++ {0x01, CRYPT_TARGET_ID}, /* CRYPT_ENG */ \ ++ {0x00, SAGE_TARGET_ID } \ ++} ++ ++ ++#define TARGETS_NAME_ARRAY { \ ++ "SDRAM_CS0", /* SDRAM_CS0 */ \ ++ "SDRAM_CS1", /* SDRAM_CS1 */ \ ++ "SDRAM_CS2", /* SDRAM_CS2 */ \ ++ "SDRAM_CS3", /* SDRAM_CS3 */ \ ++ "PEX0_MEM", /* PEX0_MEM */ \ ++ "PEX0_IO", /* PEX0_IO */ \ ++ "INTER_REGS", /* INTER_REGS */ \ ++ "NFLASH_CS", /* NFLASH_CS */ \ ++ "SPI_CS", /* SPI_CS */ \ ++ "BOOT_ROM_CS", /* BOOT_ROM_CS */ \ ++ "DEV_BOOTCS", /* DEV_BOOCS */ \ ++ "CRYPT_ENG", /* CRYPT_ENG */ \ ++ "SAGE_UNIT" /* SAGE_UNIT */ \ ++} ++#endif /* MV_ASMLANGUAGE */ ++ ++ ++#endif +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,257 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvCtrlEnvSpech ++#define __INCmvCtrlEnvSpech ++ ++#include "mvDeviceId.h" ++#include "mvSysHwConfig.h" ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++#define MV_ARM_SOC ++#define SOC_NAME_PREFIX "MV88F" ++ ++ ++/* units base and port numbers */ ++#ifdef MV_ASMLANGUAGE ++#define XOR_UNIT_BASE(unit) 0x60800 ++#else ++#define MV_XOR_REG_BASE 0x60000 ++#define XOR_UNIT_BASE(unit) ((unit)? 0x60900:0x60800) ++#endif ++ ++#define TDM_REG_BASE 0xD0000 ++#define USB_REG_BASE(dev) 0x50000 ++#define AUDIO_REG_BASE 0xA0000 ++#define SATA_REG_BASE 0x80000 ++#define MV_CESA_REG_BASE 0x3D000 ++#define MV_CESA_TDMA_REG_BASE 0x30000 ++#define MV_SDIO_REG_BASE 0x90000 ++#define MV_ETH_REG_BASE(port) (((port) == 0) ? 0x72000 : 0x76000) ++#define MV_UART_CHAN_BASE(chanNum) (0x12000 + (chanNum * 0x100)) ++#define DRAM_BASE 0x0 ++#define CNTMR_BASE 0x20300 ++#define TWSI_SLAVE_BASE(chanNum) 0x11000 ++#define PEX_IF_BASE(pexIf) 0x40000 ++#define MPP_REG_BASE 0x10000 ++#define TSU_GLOBAL_REG_BASE 0xB4000 ++#define MAX_AHB_TO_MBUS_REG_BASE 0x20000 ++ ++#define INTER_REGS_SIZE _1M ++/* This define describes the TWSI interrupt bit and location */ ++#define TWSI_CPU_MAIN_INT_CAUSE_REG 0x20200 ++#define TWSI0_CPU_MAIN_INT_BIT (1<<29) ++#define TWSI_SPEED 100000 ++ ++#define MV_GPP_MAX_GROUP 2 ++#define MV_CNTMR_MAX_COUNTER 2 ++#define MV_UART_MAX_CHAN 2 ++#define MV_XOR_MAX_UNIT 2 ++#define MV_XOR_MAX_CHAN 4 /* total channels for all units together*/ ++#define MV_XOR_MAX_CHAN_PER_UNIT 2 /* channels for units */ ++#define MV_SATA_MAX_CHAN 2 ++ ++#define MV_6281_MPP_MAX_MODULE 2 ++#define MV_6192_MPP_MAX_MODULE 1 ++#define MV_6190_MPP_MAX_MODULE 1 ++#define MV_6180_MPP_MAX_MODULE 2 ++#define MV_6281_MPP_MAX_GROUP 7 ++#define MV_6192_MPP_MAX_GROUP 4 ++#define MV_6190_MPP_MAX_GROUP 4 ++#define MV_6180_MPP_MAX_GROUP 3 ++ ++#define MV_DRAM_MAX_CS 4 ++ ++/* This define describes the maximum number of supported PCI\PCIX Interfaces*/ ++#define MV_PCI_MAX_IF 0 ++#define MV_PCI_START_IF 0 ++ ++/* This define describes the maximum number of supported PEX Interfaces */ ++#define MV_INCLUDE_PEX0 ++#define MV_DISABLE_PEX_DEVICE_BAR ++#define MV_PEX_MAX_IF 1 ++#define MV_PEX_START_IF MV_PCI_MAX_IF ++ ++/* This define describes the maximum number of supported PCI Interfaces */ ++#define MV_PCI_IF_MAX_IF (MV_PEX_MAX_IF+MV_PCI_MAX_IF) ++ ++#define MV_ETH_MAX_PORTS 2 ++#define MV_6281_ETH_MAX_PORTS 2 ++#define MV_6192_ETH_MAX_PORTS 2 ++#define MV_6190_ETH_MAX_PORTS 1 ++#define MV_6180_ETH_MAX_PORTS 1 ++ ++#define MV_IDMA_MAX_CHAN 0 ++ ++#define MV_USB_MAX_PORTS 1 ++ ++#define MV_USB_VERSION 1 ++ ++ ++#define MV_6281_NAND 1 ++#define MV_6192_NAND 1 ++#define MV_6190_NAND 1 ++#define MV_6180_NAND 0 ++ ++#define MV_6281_SDIO 1 ++#define MV_6192_SDIO 1 ++#define MV_6190_SDIO 1 ++#define MV_6180_SDIO 1 ++ ++#define MV_6281_TS 1 ++#define MV_6192_TS 1 ++#define MV_6190_TS 0 ++#define MV_6180_TS 0 ++ ++#define MV_6281_AUDIO 1 ++#define MV_6192_AUDIO 1 ++#define MV_6190_AUDIO 0 ++#define MV_6180_AUDIO 1 ++ ++#define MV_6281_TDM 1 ++#define MV_6192_TDM 1 ++#define MV_6190_TDM 0 ++#define MV_6180_TDM 0 ++ ++#define MV_DEVICE_MAX_CS 4 ++ ++/* Others */ ++#define PEX_HOST_BUS_NUM(pciIf) (pciIf) ++#define PEX_HOST_DEV_NUM(pciIf) 0 ++ ++#define PCI_IO(pciIf) (PEX0_IO) ++#define PCI_MEM(pciIf, memNum) (PEX0_MEM0) ++/* CESA version #2: One channel, 2KB SRAM, TDMA */ ++#if defined(MV_CESA_CHAIN_MODE_SUPPORT) ++ #define MV_CESA_VERSION 3 ++#else ++#define MV_CESA_VERSION 2 ++#endif ++#define MV_CESA_SRAM_SIZE 2*1024 ++/* This define describes the maximum number of supported Ethernet ports */ ++#define MV_ETH_VERSION 4 ++#define MV_ETH_MAX_RXQ 8 ++#define MV_ETH_MAX_TXQ 8 ++#define MV_ETH_PORT_SGMII { MV_FALSE, MV_FALSE } ++/* This define describes the the support of USB */ ++#define MV_USB_VERSION 1 ++ ++#define MV_INCLUDE_SDRAM_CS0 ++#define MV_INCLUDE_SDRAM_CS1 ++#define MV_INCLUDE_SDRAM_CS2 ++#define MV_INCLUDE_SDRAM_CS3 ++ ++#define MV_INCLUDE_DEVICE_CS0 ++#define MV_INCLUDE_DEVICE_CS1 ++#define MV_INCLUDE_DEVICE_CS2 ++#define MV_INCLUDE_DEVICE_CS3 ++ ++#define MPP_GROUP_1_TYPE {\ ++ {0, 0, 0}, /* Reserved for AUTO */ \ ++ {0x22220000, 0x22222222, 0x2222}, /* TDM */ \ ++ {0x44440000, 0x00044444, 0x0000}, /* AUDIO */ \ ++ {0x33330000, 0x33003333, 0x0033}, /* RGMII */ \ ++ {0x33330000, 0x03333333, 0x0033}, /* GMII */ \ ++ {0x11110000, 0x11111111, 0x0001}, /* TS */ \ ++ {0x33330000, 0x33333333, 0x3333} /* MII */ \ ++} ++ ++#define MPP_GROUP_2_TYPE {\ ++ {0, 0, 0}, /* Reserved for AUTO */ \ ++ {0x22220000, 0x22222222, 0x22}, /* TDM */ \ ++ {0x44440000, 0x00044444, 0x0}, /* AUDIO */ \ ++ {0, 0, 0}, /* N_A */ \ ++ {0, 0, 0}, /* N_A */ \ ++ {0x11110000, 0x11111111, 0x01} /* TS */ \ ++} ++ ++#ifndef MV_ASMLANGUAGE ++ ++/* This enumerator defines the Marvell Units ID */ ++typedef enum _mvUnitId ++{ ++ DRAM_UNIT_ID, ++ PEX_UNIT_ID, ++ ETH_GIG_UNIT_ID, ++ USB_UNIT_ID, ++ IDMA_UNIT_ID, ++ XOR_UNIT_ID, ++ SATA_UNIT_ID, ++ TDM_UNIT_ID, ++ UART_UNIT_ID, ++ CESA_UNIT_ID, ++ SPI_UNIT_ID, ++ AUDIO_UNIT_ID, ++ SDIO_UNIT_ID, ++ TS_UNIT_ID, ++ MAX_UNITS_ID ++ ++}MV_UNIT_ID; ++ ++#endif ++ ++#endif /* __INCmvCtrlEnvSpech */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,1048 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++/* includes */ ++#include "ctrlEnv/sys/mvAhbToMbus.h" ++#include "ctrlEnv/mvCtrlEnvAddrDec.h" ++ ++#undef MV_DEBUG ++/* defines */ ++#ifdef MV_DEBUG ++ #define DB(x) x ++#else ++ #define DB(x) ++#endif ++ ++/* typedefs */ ++ ++ ++/* CPU address remap registers offsets are inconsecutive. This struct */ ++/* describes address remap register offsets */ ++typedef struct _ahbToMbusRemapRegOffs ++{ ++ MV_U32 lowRegOffs; /* Low 32-bit remap register offset */ ++ MV_U32 highRegOffs; /* High 32 bit remap register offset */ ++}AHB_TO_MBUS_REMAP_REG_OFFS; ++ ++/* locals */ ++static MV_STATUS ahbToMbusRemapRegOffsGet (MV_U32 winNum, ++ AHB_TO_MBUS_REMAP_REG_OFFS *pRemapRegs); ++ ++/******************************************************************************* ++* mvAhbToMbusInit - Initialize Ahb To Mbus Address Map ! ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_OK laways. ++* ++*******************************************************************************/ ++MV_STATUS mvAhbToMbusInit(void) ++{ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvAhbToMbusWinSet - Set CPU-to-peripheral winNum address window ++* ++* DESCRIPTION: ++* This function sets ++* address window, also known as address decode window. ++* A new address decode window is set for specified winNum address window. ++* If address decode window parameter structure enables the window, ++* the routine will also enable the winNum window, allowing CPU to access ++* the winNum window. ++* ++* INPUT: ++* winNum - Windows number. ++* pAddrDecWin - CPU winNum window data structure. ++* ++* OUTPUT: ++* N/A ++* ++* RETURN: ++* MV_OK if CPU winNum window was set correctly, MV_ERROR in case of ++* address window overlapps with other active CPU winNum window or ++* trying to assign 36bit base address while CPU does not support that. ++* The function returns MV_NOT_SUPPORTED, if the winNum is unsupported. ++* ++*******************************************************************************/ ++MV_STATUS mvAhbToMbusWinSet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin) ++{ ++ MV_TARGET_ATTRIB targetAttribs; ++ MV_DEC_REGS decRegs; ++ ++ /* Parameter checking */ ++ if (winNum >= MAX_AHB_TO_MBUS_WINS) ++ { ++ mvOsPrintf("mvAhbToMbusWinSet: ERR. Invalid winNum %d\n", winNum); ++ return MV_NOT_SUPPORTED; ++ } ++ ++ ++ /* read base register*/ ++ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) ++ { ++ decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum)); ++ } ++ else ++ { ++ decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_INTEREG_REG); ++ } ++ ++ /* check if address is aligned to the size */ ++ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) ++ { ++ mvOsPrintf("mvAhbToMbusWinSet:Error setting AHB to MBUS window %d to "\ ++ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", ++ winNum, ++ mvCtrlTargetNameGet(pAddrDecWin->target), ++ pAddrDecWin->addrWin.baseLow, ++ pAddrDecWin->addrWin.size); ++ return MV_ERROR; ++ } ++ ++ /* read control register*/ ++ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) ++ { ++ decRegs.sizeReg = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum)); ++ } ++ ++ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) ++ { ++ mvOsPrintf("mvAhbToMbusWinSet:mvCtrlAddrDecToReg Failed\n"); ++ return MV_ERROR; ++ } ++ ++ /* enable\Disable */ ++ if (MV_TRUE == pAddrDecWin->enable) ++ { ++ decRegs.sizeReg |= ATMWCR_WIN_ENABLE; ++ } ++ else ++ { ++ decRegs.sizeReg &= ~ATMWCR_WIN_ENABLE; ++ } ++ ++ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); ++ ++ /* set attributes */ ++ decRegs.sizeReg &= ~ATMWCR_WIN_ATTR_MASK; ++ decRegs.sizeReg |= targetAttribs.attrib << ATMWCR_WIN_ATTR_OFFS; ++ /* set target ID */ ++ decRegs.sizeReg &= ~ATMWCR_WIN_TARGET_MASK; ++ decRegs.sizeReg |= targetAttribs.targetId << ATMWCR_WIN_TARGET_OFFS; ++ ++#if !defined(MV_RUN_FROM_FLASH) ++ /* To be on the safe side we disable the window before writing the */ ++ /* new values. */ ++ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) ++ { ++ mvAhbToMbusWinEnable(winNum,MV_FALSE); ++ } ++#endif ++ ++ /* 3) Write to address decode Base Address Register */ ++ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) ++ { ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum), decRegs.baseReg); ++ } ++ else ++ { ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_INTEREG_REG, decRegs.baseReg); ++ } ++ ++ ++ /* Internal register space have no size */ ++ /* register. Do not perform size register assigment for those targets */ ++ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) ++ { ++ /* Write to address decode Size Register */ ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), decRegs.sizeReg); ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvAhbToMbusWinGet - Get CPU-to-peripheral winNum address window ++* ++* DESCRIPTION: ++* Get the CPU peripheral winNum address window. ++* ++* INPUT: ++* winNum - Peripheral winNum enumerator ++* ++* OUTPUT: ++* pAddrDecWin - CPU winNum window information data structure. ++* ++* RETURN: ++* MV_OK if winNum exist, MV_ERROR otherwise. ++* ++*******************************************************************************/ ++MV_STATUS mvAhbToMbusWinGet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin) ++{ ++ MV_DEC_REGS decRegs; ++ MV_TARGET_ATTRIB targetAttrib; ++ ++ ++ /* Parameter checking */ ++ if (winNum >= MAX_AHB_TO_MBUS_WINS) ++ { ++ mvOsPrintf("mvAhbToMbusWinGet: ERR. Invalid winNum %d\n", winNum); ++ return MV_NOT_SUPPORTED; ++ } ++ ++ ++ /* Internal register space size have no size register*/ ++ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) ++ { ++ decRegs.sizeReg = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum)); ++ } ++ else ++ { ++ decRegs.sizeReg = 0; ++ } ++ ++ ++ /* Read base and size */ ++ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) ++ { ++ decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum)); ++ } ++ else ++ { ++ decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_INTEREG_REG); ++ } ++ ++ ++ ++ if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) ++ { ++ mvOsPrintf("mvAhbToMbusWinGet: mvCtrlRegToAddrDec Failed \n"); ++ return MV_ERROR; ++ } ++ ++ if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) ++ { ++ pAddrDecWin->addrWin.size = INTER_REGS_SIZE; ++ pAddrDecWin->target = INTER_REGS; ++ pAddrDecWin->enable = MV_TRUE; ++ ++ return MV_OK; ++ } ++ ++ ++ if (decRegs.sizeReg & ATMWCR_WIN_ENABLE) ++ { ++ pAddrDecWin->enable = MV_TRUE; ++ } ++ else ++ { ++ pAddrDecWin->enable = MV_FALSE; ++ ++ } ++ ++ ++ ++ if (-1 == pAddrDecWin->addrWin.size) ++ { ++ return MV_ERROR; ++ } ++ ++ /* attrib and targetId */ ++ targetAttrib.attrib = (decRegs.sizeReg & ATMWCR_WIN_ATTR_MASK) >> ++ ATMWCR_WIN_ATTR_OFFS; ++ targetAttrib.targetId = (decRegs.sizeReg & ATMWCR_WIN_TARGET_MASK) >> ++ ATMWCR_WIN_TARGET_OFFS; ++ ++ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvAhbToMbusWinTargetGet - Get Window number associated with target ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_U32 mvAhbToMbusWinTargetGet(MV_TARGET target) ++{ ++ MV_AHB_TO_MBUS_DEC_WIN decWin; ++ MV_U32 winNum; ++ ++ /* Check parameters */ ++ if (target >= MAX_TARGETS) ++ { ++ mvOsPrintf("mvAhbToMbusWinTargetGet: target %d is Illigal\n", target); ++ return 0xffffffff; ++ } ++ ++ if (INTER_REGS == target) ++ { ++ return MV_AHB_TO_MBUS_INTREG_WIN; ++ } ++ ++ for (winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS ; winNum++) ++ { ++ if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) ++ continue; ++ ++ if (mvAhbToMbusWinGet(winNum,&decWin) != MV_OK) ++ { ++ mvOsPrintf("mvAhbToMbusWinTargetGet: mvAhbToMbusWinGet fail\n"); ++ return 0xffffffff; ++ ++ } ++ ++ if (decWin.enable == MV_TRUE) ++ { ++ if (decWin.target == target) ++ { ++ return winNum; ++ } ++ ++ } ++ ++ } ++ ++ return 0xFFFFFFFF; ++ ++ ++} ++ ++/******************************************************************************* ++* mvAhbToMbusWinAvailGet - Get First Available window number. ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_U32 mvAhbToMbusWinAvailGet(MV_VOID) ++{ ++ MV_AHB_TO_MBUS_DEC_WIN decWin; ++ MV_U32 winNum; ++ ++ for (winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS ; winNum++) ++ { ++ if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) ++ continue; ++ ++ if (mvAhbToMbusWinGet(winNum,&decWin) != MV_OK) ++ { ++ mvOsPrintf("mvAhbToMbusWinTargetGet: mvAhbToMbusWinGet fail\n"); ++ return 0xffffffff; ++ ++ } ++ ++ if (decWin.enable == MV_FALSE) ++ { ++ return winNum; ++ } ++ ++ } ++ ++ return 0xFFFFFFFF; ++} ++ ++ ++/******************************************************************************* ++* mvAhbToMbusWinEnable - Enable/disable a CPU address decode window ++* ++* DESCRIPTION: ++* This function enable/disable a CPU address decode window. ++* if parameter 'enable' == MV_TRUE the routine will enable the ++* window, thus enabling CPU accesses (before enabling the window it is ++* tested for overlapping). Otherwise, the window will be disabled. ++* ++* INPUT: ++* winNum - Peripheral winNum enumerator. ++* enable - Enable/disable parameter. ++* ++* OUTPUT: ++* N/A ++* ++* RETURN: ++* MV_ERROR if protection window number was wrong, or the window ++* overlapps other winNum window. ++* ++*******************************************************************************/ ++MV_STATUS mvAhbToMbusWinEnable(MV_U32 winNum, MV_BOOL enable) ++{ ++ ++ /* Parameter checking */ ++ if (winNum >= MAX_AHB_TO_MBUS_WINS) ++ { ++ mvOsPrintf("mvAhbToMbusWinEnable: ERR. Invalid winNum %d\n", winNum); ++ return MV_NOT_SUPPORTED; ++ } ++ ++ /* Internal registers bar can't be disable or enabled */ ++ if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) ++ { ++ return (enable ? MV_OK : MV_ERROR); ++ } ++ ++ if (enable == MV_TRUE) ++ { ++ /* enable the window */ ++ MV_REG_BIT_SET(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ATMWCR_WIN_ENABLE); ++ } ++ else ++ { /* Disable address decode winNum window */ ++ MV_REG_BIT_RESET(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ATMWCR_WIN_ENABLE); ++ } ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvAhbToMbusWinRemap - Set CPU remap register for address windows. ++* ++* DESCRIPTION: ++* After a CPU address hits one of PCI address decode windows there is an ++* option to remap the address to a different one. For example, CPU ++* executes a read from PCI winNum window address 0x1200.0000. This ++* can be modified so the address on the PCI bus would be 0x1400.0000 ++* Using the PCI address remap mechanism. ++* ++* INPUT: ++* winNum - Peripheral winNum enumerator. Must be a PCI winNum. ++* pAddrDecWin - CPU winNum window information data structure. ++* Note that caller has to fill in the base field only. The ++* size field is ignored. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_ERROR if winNum is not a PCI one, MV_OK otherwise. ++* ++*******************************************************************************/ ++MV_U32 mvAhbToMbusWinRemap(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) ++{ ++ MV_U32 baseAddr; ++ AHB_TO_MBUS_REMAP_REG_OFFS remapRegOffs; ++ ++ MV_U32 effectiveBaseAddress=0, ++ baseAddrValue=0,windowSizeValue=0; ++ ++ ++ /* Get registers offsets of given winNum */ ++ if (MV_NO_SUCH == ahbToMbusRemapRegOffsGet(winNum, &remapRegOffs)) ++ { ++ return 0xffffffff; ++ } ++ ++ /* 1) Set address remap low */ ++ baseAddr = pAddrWin->baseLow; ++ ++ /* Check base address aligment */ ++ /* ++ if (MV_IS_NOT_ALIGN(baseAddr, ATMWRLR_REMAP_LOW_ALIGNMENT)) ++ { ++ mvOsPrintf("mvAhbToMbusPciRemap: Warning. Target base 0x%x unaligned\n", ++ baseAddr); ++ return MV_ERROR; ++ } ++ */ ++ ++ /* BaseLow[31:16] => base register [31:16] */ ++ baseAddr = baseAddr & ATMWRLR_REMAP_LOW_MASK; ++ ++ MV_REG_WRITE(remapRegOffs.lowRegOffs, baseAddr); ++ ++ MV_REG_WRITE(remapRegOffs.highRegOffs, pAddrWin->baseHigh); ++ ++ ++ baseAddrValue = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum)); ++ windowSizeValue = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum)); ++ ++ baseAddrValue &= ATMWBR_BASE_MASK; ++ windowSizeValue &=ATMWCR_WIN_SIZE_MASK; ++ ++ /* Start calculating the effective Base Address */ ++ effectiveBaseAddress = baseAddrValue ; ++ ++ /* The effective base address will be combined from the chopped (if any) ++ remap value (according to the size value and remap mechanism) and the ++ window's base address */ ++ effectiveBaseAddress |= (((windowSizeValue) | 0xffff) & pAddrWin->baseLow); ++ /* If the effectiveBaseAddress exceed the window boundaries return an ++ invalid value. */ ++ ++ if (effectiveBaseAddress > (baseAddrValue + (windowSizeValue | 0xffff))) ++ { ++ mvOsPrintf("mvAhbToMbusPciRemap: Error\n"); ++ return 0xffffffff; ++ } ++ ++ return effectiveBaseAddress; ++ ++ ++} ++/******************************************************************************* ++* mvAhbToMbusWinTargetSwap - Swap AhbToMbus windows between targets ++* ++* DESCRIPTION: ++* ++* INPUT: ++* target1 - CPU Interface target 1 ++* target2 - CPU Interface target 2 ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_ERROR if targets are illigal, or if one of the targets is not ++* associated to a valid window . ++* MV_OK otherwise. ++* ++*******************************************************************************/ ++ ++ ++MV_STATUS mvAhbToMbusWinTargetSwap(MV_TARGET target1,MV_TARGET target2) ++{ ++ MV_U32 winNum1,winNum2; ++ MV_AHB_TO_MBUS_DEC_WIN winDec1,winDec2,winDecTemp; ++ AHB_TO_MBUS_REMAP_REG_OFFS remapRegs1,remapRegs2; ++ MV_U32 remapBaseLow1=0,remapBaseLow2=0; ++ MV_U32 remapBaseHigh1=0,remapBaseHigh2=0; ++ ++ ++ /* Check parameters */ ++ if (target1 >= MAX_TARGETS) ++ { ++ mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d is Illigal\n", target1); ++ return MV_ERROR; ++ } ++ ++ if (target2 >= MAX_TARGETS) ++ { ++ mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d is Illigal\n", target1); ++ return MV_ERROR; ++ } ++ ++ ++ /* get window associated with this target */ ++ winNum1 = mvAhbToMbusWinTargetGet(target1); ++ ++ if (winNum1 == 0xffffffff) ++ { ++ mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d has illigal win %d\n", ++ target1,winNum1); ++ return MV_ERROR; ++ ++ } ++ ++ /* get window associated with this target */ ++ winNum2 = mvAhbToMbusWinTargetGet(target2); ++ ++ if (winNum2 == 0xffffffff) ++ { ++ mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d has illigal win %d\n", ++ target2,winNum2); ++ return MV_ERROR; ++ ++ } ++ ++ /* now Get original values of both Windows */ ++ if (MV_OK != mvAhbToMbusWinGet(winNum1,&winDec1)) ++ { ++ mvOsPrintf("mvAhbToMbusWinTargetSwap: mvAhbToMbusWinGet failed win %d\n", ++ winNum1); ++ return MV_ERROR; ++ ++ } ++ if (MV_OK != mvAhbToMbusWinGet(winNum2,&winDec2)) ++ { ++ mvOsPrintf("mvAhbToMbusWinTargetSwap: mvAhbToMbusWinGet failed win %d\n", ++ winNum2); ++ return MV_ERROR; ++ ++ } ++ ++ ++ /* disable both windows */ ++ if (MV_OK != mvAhbToMbusWinEnable(winNum1,MV_FALSE)) ++ { ++ mvOsPrintf("mvAhbToMbusWinTargetSwap: failed to enable window %d\n", ++ winNum1); ++ return MV_ERROR; ++ ++ } ++ if (MV_OK != mvAhbToMbusWinEnable(winNum2,MV_FALSE)) ++ { ++ mvOsPrintf("mvAhbToMbusWinTargetSwap: failed to enable windo %d\n", ++ winNum2); ++ return MV_ERROR; ++ ++ } ++ ++ ++ /* now swap targets */ ++ ++ /* first save winDec2 values */ ++ winDecTemp.addrWin.baseHigh = winDec2.addrWin.baseHigh; ++ winDecTemp.addrWin.baseLow = winDec2.addrWin.baseLow; ++ winDecTemp.addrWin.size = winDec2.addrWin.size; ++ winDecTemp.enable = winDec2.enable; ++ winDecTemp.target = winDec2.target; ++ ++ /* winDec2 = winDec1 */ ++ winDec2.addrWin.baseHigh = winDec1.addrWin.baseHigh; ++ winDec2.addrWin.baseLow = winDec1.addrWin.baseLow; ++ winDec2.addrWin.size = winDec1.addrWin.size; ++ winDec2.enable = winDec1.enable; ++ winDec2.target = winDec1.target; ++ ++ ++ /* winDec1 = winDecTemp */ ++ winDec1.addrWin.baseHigh = winDecTemp.addrWin.baseHigh; ++ winDec1.addrWin.baseLow = winDecTemp.addrWin.baseLow; ++ winDec1.addrWin.size = winDecTemp.addrWin.size; ++ winDec1.enable = winDecTemp.enable; ++ winDec1.target = winDecTemp.target; ++ ++ ++ /* now set the new values */ ++ ++ ++ mvAhbToMbusWinSet(winNum1,&winDec1); ++ mvAhbToMbusWinSet(winNum2,&winDec2); ++ ++ ++ ++ ++ ++ /* now we will treat the remap windows if exist */ ++ ++ ++ /* now check if one or both windows has a remap window ++ as well after the swap ! */ ++ ++ /* if a window had a remap value differnt than the base value ++ before the swap , then after the swap the remap value will be ++ equal to the base value unless both windows has a remap windows*/ ++ ++ /* first get old values */ ++ if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum1,&remapRegs1)) ++ { ++ remapBaseLow1 = MV_REG_READ(remapRegs1.lowRegOffs); ++ remapBaseHigh1 = MV_REG_READ(remapRegs1.highRegOffs); ++ ++ } ++ if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2,&remapRegs2)) ++ { ++ remapBaseLow2 = MV_REG_READ(remapRegs2.lowRegOffs); ++ remapBaseHigh2 = MV_REG_READ(remapRegs2.highRegOffs); ++ ++ ++ } ++ ++ /* now do the swap */ ++ if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum1,&remapRegs1)) ++ { ++ if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2,&remapRegs2)) ++ { ++ /* Two windows has a remap !!! so swap */ ++ ++ MV_REG_WRITE(remapRegs2.highRegOffs,remapBaseHigh1); ++ MV_REG_WRITE(remapRegs2.lowRegOffs,remapBaseLow1); ++ ++ MV_REG_WRITE(remapRegs1.highRegOffs,remapBaseHigh2); ++ MV_REG_WRITE(remapRegs1.lowRegOffs,remapBaseLow2); ++ ++ ++ ++ } ++ else ++ { ++ /* remap == base */ ++ MV_REG_WRITE(remapRegs1.highRegOffs,winDec1.addrWin.baseHigh); ++ MV_REG_WRITE(remapRegs1.lowRegOffs,winDec1.addrWin.baseLow); ++ ++ } ++ ++ } ++ else if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2,&remapRegs2)) ++ { ++ /* remap == base */ ++ MV_REG_WRITE(remapRegs2.highRegOffs,winDec2.addrWin.baseHigh); ++ MV_REG_WRITE(remapRegs2.lowRegOffs,winDec2.addrWin.baseLow); ++ ++ } ++ ++ ++ ++ return MV_OK; ++ ++ ++} ++ ++ ++ ++#if defined(MV_88F1181) ++ ++/******************************************************************************* ++* mvAhbToMbusXbarCtrlSet - Set The CPU master Xbar arbitration. ++* ++* DESCRIPTION: ++* This function sets CPU Mbus Arbiter ++* ++* INPUT: ++* pPizzaArbArray - A priority Structure describing 16 "pizza slices". At ++* each clock cycle, the crossbar arbiter samples all ++* requests and gives the bus to the next agent according ++* to the "pizza". ++* ++* OUTPUT: ++* N/A ++* ++* RETURN: ++* MV_ERROR if paramers to function invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvMbusArbSet(MV_MBUS_ARB_TARGET *pPizzaArbArray) ++{ ++ MV_U32 sliceNum; ++ MV_U32 xbarCtrl = 0; ++ MV_MBUS_ARB_TARGET xbarTarget; ++ ++ /* 1) Set crossbar control low register */ ++ for (sliceNum = 0; sliceNum < MRLR_SLICE_NUM; sliceNum++) ++ { ++ xbarTarget = pPizzaArbArray[sliceNum]; ++ ++ /* sliceNum parameter check */ ++ if (xbarTarget > MAX_MBUS_ARB_TARGETS) ++ { ++ mvOsPrintf("mvAhbToMbusXbarCtrlSet: ERR. Can't set Target %d\n", ++ xbarTarget); ++ return MV_ERROR; ++ } ++ xbarCtrl |= (xbarTarget << MRLR_LOW_ARB_OFFS(sliceNum)); ++ } ++ /* Write to crossbar control low register */ ++ MV_REG_WRITE(MBUS_ARBITER_LOW_REG, xbarCtrl); ++ ++ xbarCtrl = 0; ++ ++ /* 2) Set crossbar control high register */ ++ for (sliceNum = MRLR_SLICE_NUM; ++ sliceNum < MRLR_SLICE_NUM+MRHR_SLICE_NUM; ++ sliceNum++) ++ { ++ ++ xbarTarget = pPizzaArbArray[sliceNum]; ++ ++ /* sliceNum parameter check */ ++ if (xbarTarget > MAX_MBUS_ARB_TARGETS) ++ { ++ mvOsPrintf("mvAhbToMbusXbarCtrlSet: ERR. Can't set Target %d\n", ++ xbarTarget); ++ return MV_ERROR; ++ } ++ xbarCtrl |= (xbarTarget << MRHR_HIGH_ARB_OFFS(sliceNum)); ++ } ++ /* Write to crossbar control high register */ ++ MV_REG_WRITE(MBUS_ARBITER_HIGH_REG, xbarCtrl); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvMbusArbCtrlSet - Set MBus Arbiter control register ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ctrl - pointer to MV_MBUS_ARB_CTRL register ++* ++* OUTPUT: ++* N/A ++* ++* RETURN: ++* MV_ERROR if paramers to function invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvMbusArbCtrlSet(MV_MBUS_ARB_CTRL *ctrl) ++{ ++ ++ if (ctrl->highPrio == MV_FALSE) ++ { ++ MV_REG_BIT_RESET(MBUS_ARBITER_CTRL_REG, MACR_ARB_ARM_TOP); ++ } ++ else ++ { ++ MV_REG_BIT_SET(MBUS_ARBITER_CTRL_REG, MACR_ARB_ARM_TOP); ++ } ++ ++ if (ctrl->fixedRoundRobin == MV_FALSE) ++ { ++ MV_REG_BIT_RESET(MBUS_ARBITER_CTRL_REG, MACR_ARB_TARGET_FIXED); ++ } ++ else ++ { ++ MV_REG_BIT_SET(MBUS_ARBITER_CTRL_REG, MACR_ARB_TARGET_FIXED); ++ } ++ ++ if (ctrl->starvEn == MV_FALSE) ++ { ++ MV_REG_BIT_RESET(MBUS_ARBITER_CTRL_REG, MACR_ARB_REQ_CTRL_EN); ++ } ++ else ++ { ++ MV_REG_BIT_SET(MBUS_ARBITER_CTRL_REG, MACR_ARB_REQ_CTRL_EN); ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvMbusArbCtrlGet - Get MBus Arbiter control register ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ctrl - pointer to MV_MBUS_ARB_CTRL register ++* ++* OUTPUT: ++* ctrl - pointer to MV_MBUS_ARB_CTRL register ++* ++* RETURN: ++* MV_ERROR if paramers to function invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvMbusArbCtrlGet(MV_MBUS_ARB_CTRL *ctrl) ++{ ++ ++ MV_U32 ctrlReg = MV_REG_READ(MBUS_ARBITER_CTRL_REG); ++ ++ if (ctrlReg & MACR_ARB_ARM_TOP) ++ { ++ ctrl->highPrio = MV_TRUE; ++ } ++ else ++ { ++ ctrl->highPrio = MV_FALSE; ++ } ++ ++ if (ctrlReg & MACR_ARB_TARGET_FIXED) ++ { ++ ctrl->fixedRoundRobin = MV_TRUE; ++ } ++ else ++ { ++ ctrl->fixedRoundRobin = MV_FALSE; ++ } ++ ++ if (ctrlReg & MACR_ARB_REQ_CTRL_EN) ++ { ++ ctrl->starvEn = MV_TRUE; ++ } ++ else ++ { ++ ctrl->starvEn = MV_FALSE; ++ } ++ ++ ++ return MV_OK; ++} ++ ++#endif /* #if defined(MV_88F1181) */ ++ ++ ++ ++/******************************************************************************* ++* ahbToMbusRemapRegOffsGet - Get CPU address remap register offsets ++* ++* DESCRIPTION: ++* CPU to PCI address remap registers offsets are inconsecutive. ++* This function returns PCI address remap registers offsets. ++* ++* INPUT: ++* winNum - Address decode window number. See MV_U32 enumerator. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_ERROR if winNum is not a PCI one. ++* ++*******************************************************************************/ ++static MV_STATUS ahbToMbusRemapRegOffsGet(MV_U32 winNum, ++ AHB_TO_MBUS_REMAP_REG_OFFS *pRemapRegs) ++{ ++ switch (winNum) ++ { ++ case 0: ++ case 1: ++ pRemapRegs->lowRegOffs = AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum); ++ pRemapRegs->highRegOffs = AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum); ++ break; ++ case 2: ++ case 3: ++ if((mvCtrlModelGet() == MV_5281_DEV_ID) || ++ (mvCtrlModelGet() == MV_1281_DEV_ID) || ++ (mvCtrlModelGet() == MV_6183_DEV_ID) || ++ (mvCtrlModelGet() == MV_6183L_DEV_ID)) ++ { ++ pRemapRegs->lowRegOffs = AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum); ++ pRemapRegs->highRegOffs = AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum); ++ break; ++ } ++ else ++ { ++ pRemapRegs->lowRegOffs = 0; ++ pRemapRegs->highRegOffs = 0; ++ ++ DB(mvOsPrintf("ahbToMbusRemapRegOffsGet: ERR. Invalid winNum %d\n", ++ winNum)); ++ return MV_NO_SUCH; ++ } ++ default: ++ { ++ pRemapRegs->lowRegOffs = 0; ++ pRemapRegs->highRegOffs = 0; ++ ++ DB(mvOsPrintf("ahbToMbusRemapRegOffsGet: ERR. Invalid winNum %d\n", ++ winNum)); ++ return MV_NO_SUCH; ++ } ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvAhbToMbusAddDecShow - Print the AHB to MBus bridge address decode map. ++* ++* DESCRIPTION: ++* This function print the CPU address decode map. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvAhbToMbusAddDecShow(MV_VOID) ++{ ++ MV_AHB_TO_MBUS_DEC_WIN win; ++ MV_U32 winNum; ++ mvOsOutput( "\n" ); ++ mvOsOutput( "AHB To MBUS Bridge:\n" ); ++ mvOsOutput( "-------------------\n" ); ++ ++ for( winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS; winNum++ ) ++ { ++ memset( &win, 0, sizeof(MV_AHB_TO_MBUS_DEC_WIN) ); ++ ++ mvOsOutput( "win%d - ", winNum ); ++ ++ if( mvAhbToMbusWinGet( winNum, &win ) == MV_OK ) ++ { ++ if( win.enable ) ++ { ++ mvOsOutput( "%s base %08x, ", ++ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); ++ mvOsOutput( "...." ); ++ mvSizePrint( win.addrWin.size ); ++ ++ mvOsOutput( "\n" ); ++ ++ } ++ else ++ mvOsOutput( "disable\n" ); ++ } ++ } ++ ++} ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,130 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvAhbToMbush ++#define __INCmvAhbToMbush ++ ++/* includes */ ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "ctrlEnv/sys/mvAhbToMbusRegs.h" ++#include "ctrlEnv/mvCtrlEnvAddrDec.h" ++ ++/* defines */ ++ ++#if defined(MV_88F1181) ++/* This enumerator defines the Marvell controller possible MBUS arbiter */ ++/* target ports. It is used to define crossbar priority scheame (pizza) */ ++typedef enum _mvMBusArbTargetId ++{ ++ DRAM_MBUS_ARB_TARGET = 0, /* Port 0 -> DRAM interface */ ++ TWSI_MBUS_ARB_TARGET = 1, /* Port 1 -> TWSI */ ++ ARM_MBUS_ARB_TARGET = 2, /* Port 2 -> ARM */ ++ PEX1_MBUS_ARB_TARGET = 3, /* Port 3 -> PCI Express 1 */ ++ PEX0_MBUS_ARB_TARGET = 4, /* Port 4 -> PCI Express0 */ ++ MAX_MBUS_ARB_TARGETS ++}MV_MBUS_ARB_TARGET; ++ ++typedef struct _mvMBusArbCtrl ++{ ++ MV_BOOL starvEn; ++ MV_BOOL highPrio; ++ MV_BOOL fixedRoundRobin; ++ ++}MV_MBUS_ARB_CTRL; ++ ++#endif /* #if defined(MV_88F1181) */ ++ ++typedef struct _mvAhbtoMbusDecWin ++{ ++ MV_TARGET target; ++ MV_ADDR_WIN addrWin; /* An address window*/ ++ MV_BOOL enable; /* Address decode window is enabled/disabled */ ++ ++}MV_AHB_TO_MBUS_DEC_WIN; ++ ++/* mvAhbToMbus.h API list */ ++ ++MV_STATUS mvAhbToMbusInit(MV_VOID); ++MV_STATUS mvAhbToMbusWinSet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin); ++MV_STATUS mvAhbToMbusWinGet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin); ++MV_STATUS mvAhbToMbusWinEnable(MV_U32 winNum,MV_BOOL enable); ++MV_U32 mvAhbToMbusWinRemap(MV_U32 winNum, MV_ADDR_WIN *pAddrDecWin); ++MV_U32 mvAhbToMbusWinTargetGet(MV_TARGET target); ++MV_U32 mvAhbToMbusWinAvailGet(MV_VOID); ++MV_STATUS mvAhbToMbusWinTargetSwap(MV_TARGET target1,MV_TARGET target2); ++ ++#if defined(MV_88F1181) ++ ++MV_STATUS mvMbusArbSet(MV_MBUS_ARB_TARGET *pPizzaArbArray); ++MV_STATUS mvMbusArbCtrlSet(MV_MBUS_ARB_CTRL *ctrl); ++MV_STATUS mvMbusArbCtrlGet(MV_MBUS_ARB_CTRL *ctrl); ++ ++#endif /* #if defined(MV_88F1181) */ ++ ++ ++MV_VOID mvAhbToMbusAddDecShow(MV_VOID); ++ ++ ++#endif /* __INCmvAhbToMbush */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,143 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvAhbToMbusRegsh ++#define __INCmvAhbToMbusRegsh ++ ++/******************************/ ++/* ARM Address Map Registers */ ++/******************************/ ++ ++#define MAX_AHB_TO_MBUS_WINS 9 ++#define MV_AHB_TO_MBUS_INTREG_WIN 8 ++ ++ ++#define AHB_TO_MBUS_WIN_CTRL_REG(winNum) (0x20000 + (winNum)*0x10) ++#define AHB_TO_MBUS_WIN_BASE_REG(winNum) (0x20004 + (winNum)*0x10) ++#define AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum) (0x20008 + (winNum)*0x10) ++#define AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum) (0x2000C + (winNum)*0x10) ++#define AHB_TO_MBUS_WIN_INTEREG_REG 0x20080 ++ ++/* Window Control Register */ ++/* AHB_TO_MBUS_WIN_CTRL_REG (ATMWCR)*/ ++#define ATMWCR_WIN_ENABLE BIT0 /* Window Enable */ ++ ++#define ATMWCR_WIN_TARGET_OFFS 4 /* The target interface associated ++ with this window*/ ++#define ATMWCR_WIN_TARGET_MASK (0xf << ATMWCR_WIN_TARGET_OFFS) ++ ++#define ATMWCR_WIN_ATTR_OFFS 8 /* The target interface attributes ++ Associated with this window */ ++#define ATMWCR_WIN_ATTR_MASK (0xff << ATMWCR_WIN_ATTR_OFFS) ++ ++ ++/* ++Used with the Base register to set the address window size and location ++Must be programed from LSB to MSB as sequence of 1’s followed ++by sequence of 0’s. The number of 1’s specifies the size of the window ++in 64 KB granularity (e.g. a value of 0x00FF specifies 256 = 16 MB). ++ ++NOTE: A value of 0x0 specifies 64KB size. ++*/ ++#define ATMWCR_WIN_SIZE_OFFS 16 /* Window Size */ ++#define ATMWCR_WIN_SIZE_MASK (0xffff << ATMWCR_WIN_SIZE_OFFS) ++#define ATMWCR_WIN_SIZE_ALIGNMENT 0x10000 ++ ++/* Window Base Register */ ++/* AHB_TO_MBUS_WIN_BASE_REG (ATMWBR) */ ++ ++/* ++Used with the size field to set the address window size and location. ++Corresponds to transaction address[31:16] ++*/ ++#define ATMWBR_BASE_OFFS 16 /* Base Address */ ++#define ATMWBR_BASE_MASK (0xffff << ATMWBR_BASE_OFFS) ++#define ATMWBR_BASE_ALIGNMENT 0x10000 ++ ++/* Window Remap Low Register */ ++/* AHB_TO_MBUS_WIN_REMAP_LOW_REG (ATMWRLR) */ ++ ++/* ++Used with the size field to specifies address bits[31:0] to be driven to ++the target interface.: ++target_addr[31:16] = (addr[31:16] & size[15:0]) | (remap[31:16] & ~size[15:0]) ++*/ ++#define ATMWRLR_REMAP_LOW_OFFS 16 /* Remap Address */ ++#define ATMWRLR_REMAP_LOW_MASK (0xffff << ATMWRLR_REMAP_LOW_OFFS) ++#define ATMWRLR_REMAP_LOW_ALIGNMENT 0x10000 ++ ++/* Window Remap High Register */ ++/* AHB_TO_MBUS_WIN_REMAP_HIGH_REG (ATMWRHR) */ ++ ++/* ++Specifies address bits[63:32] to be driven to the target interface. ++target_addr[63:32] = (RemapHigh[31:0] ++*/ ++#define ATMWRHR_REMAP_HIGH_OFFS 0 /* Remap Address */ ++#define ATMWRHR_REMAP_HIGH_MASK (0xffffffff << ATMWRHR_REMAP_HIGH_OFFS) ++ ++ ++#endif /* __INCmvAhbToMbusRegsh */ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,1036 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++/* includes */ ++#include "ctrlEnv/sys/mvCpuIf.h" ++#include "ctrlEnv/sys/mvAhbToMbusRegs.h" ++#include "cpu/mvCpu.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "mvSysHwConfig.h" ++#include "mvSysDram.h" ++ ++/*#define MV_DEBUG*/ ++/* defines */ ++ ++#ifdef MV_DEBUG ++ #define DB(x) x ++#else ++ #define DB(x) ++#endif ++ ++/* locals */ ++/* static functions */ ++static MV_BOOL cpuTargetWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin); ++ ++MV_TARGET * sampleAtResetTargetArray; ++MV_TARGET sampleAtResetTargetArrayP[] = BOOT_TARGETS_NAME_ARRAY; ++MV_TARGET sampleAtResetTargetArray6180P[] = BOOT_TARGETS_NAME_ARRAY_6180; ++/******************************************************************************* ++* mvCpuIfInit - Initialize Controller CPU interface ++* ++* DESCRIPTION: ++* This function initialize Controller CPU interface: ++* 1. Set CPU interface configuration registers. ++* 2. Set CPU master Pizza arbiter control according to static ++* configuration described in configuration file. ++* 3. Opens CPU address decode windows. DRAM windows are assumed to be ++* already set (auto detection). ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_STATUS mvCpuIfInit(MV_CPU_DEC_WIN *cpuAddrWinMap) ++{ ++ MV_U32 regVal; ++ MV_TARGET target; ++ MV_ADDR_WIN addrWin; ++ ++ if (cpuAddrWinMap == NULL) ++ { ++ DB(mvOsPrintf("mvCpuIfInit:ERR. cpuAddrWinMap == NULL\n")); ++ return MV_ERROR; ++ } ++ ++ /*Initialize the boot target array according to device type*/ ++ if(mvCtrlModelGet() == MV_6180_DEV_ID) ++ sampleAtResetTargetArray = sampleAtResetTargetArray6180P; ++ else ++ sampleAtResetTargetArray = sampleAtResetTargetArrayP; ++ ++ /* Set ARM Configuration register */ ++ regVal = MV_REG_READ(CPU_CONFIG_REG); ++ regVal &= ~CPU_CONFIG_DEFAULT_MASK; ++ regVal |= CPU_CONFIG_DEFAULT; ++ MV_REG_WRITE(CPU_CONFIG_REG,regVal); ++ ++ /* First disable all CPU target windows */ ++ for (target = 0; cpuAddrWinMap[target].enable != TBL_TERM; target++) ++ { ++ if ((MV_TARGET_IS_DRAM(target))||(target == INTER_REGS)) ++ { ++ continue; ++ } ++ ++#if defined(MV_MEM_OVER_PCI_WA) || defined(MV_UART_OVER_PCI_WA) ++ /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ ++ if (MV_TARGET_IS_PCI(target)) ++ { ++ continue; ++ } ++#endif ++ ++#if defined(MV_MEM_OVER_PEX_WA) || defined(MV_UART_OVER_PEX_WA) ++ /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ ++ if (MV_TARGET_IS_PEX(target)) ++ { ++ continue; ++ } ++#endif ++#if defined(MV_RUN_FROM_FLASH) ++ /* Don't disable the boot device. */ ++ if (target == DEV_BOOCS) ++ { ++ continue; ++ } ++#endif /* MV_RUN_FROM_FLASH */ ++ mvCpuIfTargetWinEnable(MV_CHANGE_BOOT_CS(target),MV_FALSE); ++ } ++ ++#if defined(MV_RUN_FROM_FLASH) ++ /* Resize the bootcs windows before other windows, because this */ ++ /* window is enabled and will cause an overlap if not resized. */ ++ target = DEV_BOOCS; ++ ++ if (MV_OK != mvCpuIfTargetWinSet(target, &cpuAddrWinMap[target])) ++ { ++ DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinSet fail\n")); ++ return MV_ERROR; ++ } ++ ++ addrWin.baseLow = cpuAddrWinMap[target].addrWin.baseLow; ++ addrWin.baseHigh = cpuAddrWinMap[target].addrWin.baseHigh; ++ if (0xffffffff == mvAhbToMbusWinRemap(cpuAddrWinMap[target].winNum ,&addrWin)) ++ { ++ DB(mvOsPrintf("mvCpuIfInit:WARN. mvAhbToMbusWinRemap can't remap winNum=%d\n", ++ cpuAddrWinMap[target].winNum)); ++ } ++ ++#endif /* MV_RUN_FROM_FLASH */ ++ ++ /* Go through all targets in user table until table terminator */ ++ for (target = 0; cpuAddrWinMap[target].enable != TBL_TERM; target++) ++ { ++ ++#if defined(MV_RUN_FROM_FLASH) ++ if (target == DEV_BOOCS) ++ { ++ continue; ++ } ++#endif /* MV_RUN_FROM_FLASH */ ++ ++ /* if DRAM auto sizing is used do not initialized DRAM target windows, */ ++ /* assuming this already has been done earlier. */ ++#ifdef MV_DRAM_AUTO_SIZE ++ if (MV_TARGET_IS_DRAM(target)) ++ { ++ continue; ++ } ++#endif ++ ++#if defined(MV_MEM_OVER_PCI_WA) || defined(MV_UART_OVER_PCI_WA) ++ /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ ++ if (MV_TARGET_IS_PCI(target)) ++ { ++ continue; ++ } ++#endif ++ ++#if defined(MV_MEM_OVER_PEX_WA) || defined(MV_UART_OVER_PEX_WA) ++ /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ ++ if (MV_TARGET_IS_PEX(target)) ++ { ++ continue; ++ } ++#endif ++ /* If the target attribute is the same as the boot device attribute */ ++ /* then it's stays disable */ ++ if (MV_TARGET_IS_AS_BOOT(target)) ++ { ++ continue; ++ } ++ ++ if((0 == cpuAddrWinMap[target].addrWin.size) || ++ (DIS == cpuAddrWinMap[target].enable)) ++ ++ { ++ if (MV_OK != mvCpuIfTargetWinEnable(target, MV_FALSE)) ++ { ++ DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinEnable fail\n")); ++ return MV_ERROR; ++ } ++ ++ } ++ else ++ { ++ if (MV_OK != mvCpuIfTargetWinSet(target, &cpuAddrWinMap[target])) ++ { ++ DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinSet fail\n")); ++ return MV_ERROR; ++ } ++ ++ addrWin.baseLow = cpuAddrWinMap[target].addrWin.baseLow; ++ addrWin.baseHigh = cpuAddrWinMap[target].addrWin.baseHigh; ++ if (0xffffffff == mvAhbToMbusWinRemap(cpuAddrWinMap[target].winNum ,&addrWin)) ++ { ++ DB(mvOsPrintf("mvCpuIfInit:WARN. mvAhbToMbusWinRemap can't remap winNum=%d\n", ++ cpuAddrWinMap[target].winNum)); ++ } ++ ++ ++ } ++ } ++ ++ return MV_OK; ++ ++ ++} ++ ++ ++/******************************************************************************* ++* mvCpuIfTargetWinSet - Set CPU-to-peripheral target address window ++* ++* DESCRIPTION: ++* This function sets a peripheral target (e.g. SDRAM bank0, PCI0_MEM0) ++* address window, also known as address decode window. ++* A new address decode window is set for specified target address window. ++* If address decode window parameter structure enables the window, ++* the routine will also enable the target window, allowing CPU to access ++* the target window. ++* ++* INPUT: ++* target - Peripheral target enumerator. ++* pAddrDecWin - CPU target window data structure. ++* ++* OUTPUT: ++* N/A ++* ++* RETURN: ++* MV_OK if CPU target window was set correctly, MV_ERROR in case of ++* address window overlapps with other active CPU target window or ++* trying to assign 36bit base address while CPU does not support that. ++* The function returns MV_NOT_SUPPORTED, if the target is unsupported. ++* ++*******************************************************************************/ ++MV_STATUS mvCpuIfTargetWinSet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin) ++{ ++ MV_AHB_TO_MBUS_DEC_WIN decWin; ++ MV_U32 existingWinNum; ++ MV_DRAM_DEC_WIN addrDecWin; ++ ++ target = MV_CHANGE_BOOT_CS(target); ++ ++ /* Check parameters */ ++ if (target >= MAX_TARGETS) ++ { ++ mvOsPrintf("mvCpuIfTargetWinSet: target %d is Illigal\n", target); ++ return MV_ERROR; ++ } ++ ++ /* 2) Check if the requested window overlaps with current windows */ ++ if (MV_TRUE == cpuTargetWinOverlap(target, &pAddrDecWin->addrWin)) ++ { ++ mvOsPrintf("mvCpuIfTargetWinSet: ERR. Target %d overlap\n", target); ++ return MV_BAD_PARAM; ++ } ++ ++ if (MV_TARGET_IS_DRAM(target)) ++ { ++ /* copy relevant data to MV_DRAM_DEC_WIN structure */ ++ addrDecWin.addrWin.baseHigh = pAddrDecWin->addrWin.baseHigh; ++ addrDecWin.addrWin.baseLow = pAddrDecWin->addrWin.baseLow; ++ addrDecWin.addrWin.size = pAddrDecWin->addrWin.size; ++ addrDecWin.enable = pAddrDecWin->enable; ++ ++ ++ if (mvDramIfWinSet(target,&addrDecWin) != MV_OK); ++ { ++ mvOsPrintf("mvCpuIfTargetWinSet: mvDramIfWinSet Failed\n"); ++ return MV_ERROR; ++ } ++ ++ } ++ else ++ { ++ /* copy relevant data to MV_AHB_TO_MBUS_DEC_WIN structure */ ++ decWin.addrWin.baseLow = pAddrDecWin->addrWin.baseLow; ++ decWin.addrWin.baseHigh = pAddrDecWin->addrWin.baseHigh; ++ decWin.addrWin.size = pAddrDecWin->addrWin.size; ++ decWin.enable = pAddrDecWin->enable; ++ decWin.target = target; ++ ++ existingWinNum = mvAhbToMbusWinTargetGet(target); ++ ++ /* check if there is already another Window configured ++ for this target */ ++ if ((existingWinNum < MAX_AHB_TO_MBUS_WINS )&& ++ (existingWinNum != pAddrDecWin->winNum)) ++ { ++ /* if we want to enable the new winow number ++ passed by the user , then the old one should ++ be disabled */ ++ if (MV_TRUE == pAddrDecWin->enable) ++ { ++ /* be sure it is disabled */ ++ mvAhbToMbusWinEnable(existingWinNum , MV_FALSE); ++ } ++ } ++ ++ if (mvAhbToMbusWinSet(pAddrDecWin->winNum,&decWin) != MV_OK) ++ { ++ mvOsPrintf("mvCpuIfTargetWinSet: mvAhbToMbusWinSet Failed\n"); ++ return MV_ERROR; ++ } ++ ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCpuIfTargetWinGet - Get CPU-to-peripheral target address window ++* ++* DESCRIPTION: ++* Get the CPU peripheral target address window. ++* ++* INPUT: ++* target - Peripheral target enumerator ++* ++* OUTPUT: ++* pAddrDecWin - CPU target window information data structure. ++* ++* RETURN: ++* MV_OK if target exist, MV_ERROR otherwise. ++* ++*******************************************************************************/ ++MV_STATUS mvCpuIfTargetWinGet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin) ++{ ++ ++ MV_U32 winNum=0xffffffff; ++ MV_AHB_TO_MBUS_DEC_WIN decWin; ++ MV_DRAM_DEC_WIN addrDecWin; ++ ++ target = MV_CHANGE_BOOT_CS(target); ++ ++ /* Check parameters */ ++ if (target >= MAX_TARGETS) ++ { ++ mvOsPrintf("mvCpuIfTargetWinGet: target %d is Illigal\n", target); ++ return MV_ERROR; ++ } ++ ++ if (MV_TARGET_IS_DRAM(target)) ++ { ++ if (mvDramIfWinGet(target,&addrDecWin) != MV_OK) ++ { ++ mvOsPrintf("mvCpuIfTargetWinGet: Failed to get window target %d\n", ++ target); ++ return MV_ERROR; ++ } ++ ++ /* copy relevant data to MV_CPU_DEC_WIN structure */ ++ pAddrDecWin->addrWin.baseLow = addrDecWin.addrWin.baseLow; ++ pAddrDecWin->addrWin.baseHigh = addrDecWin.addrWin.baseHigh; ++ pAddrDecWin->addrWin.size = addrDecWin.addrWin.size; ++ pAddrDecWin->enable = addrDecWin.enable; ++ pAddrDecWin->winNum = 0xffffffff; ++ ++ } ++ else ++ { ++ /* get the Window number associated with this target */ ++ ++ winNum = mvAhbToMbusWinTargetGet(target); ++ if (winNum >= MAX_AHB_TO_MBUS_WINS) ++ { ++ return MV_NO_SUCH; ++ ++ } ++ ++ if (mvAhbToMbusWinGet(winNum , &decWin) != MV_OK) ++ { ++ mvOsPrintf("%s: mvAhbToMbusWinGet Failed at winNum = %d\n", ++ __FUNCTION__, winNum); ++ return MV_ERROR; ++ ++ } ++ ++ /* copy relevant data to MV_CPU_DEC_WIN structure */ ++ pAddrDecWin->addrWin.baseLow = decWin.addrWin.baseLow; ++ pAddrDecWin->addrWin.baseHigh = decWin.addrWin.baseHigh; ++ pAddrDecWin->addrWin.size = decWin.addrWin.size; ++ pAddrDecWin->enable = decWin.enable; ++ pAddrDecWin->winNum = winNum; ++ ++ } ++ ++ ++ ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvCpuIfTargetWinEnable - Enable/disable a CPU address decode window ++* ++* DESCRIPTION: ++* This function enable/disable a CPU address decode window. ++* if parameter 'enable' == MV_TRUE the routine will enable the ++* window, thus enabling CPU accesses (before enabling the window it is ++* tested for overlapping). Otherwise, the window will be disabled. ++* ++* INPUT: ++* target - Peripheral target enumerator. ++* enable - Enable/disable parameter. ++* ++* OUTPUT: ++* N/A ++* ++* RETURN: ++* MV_ERROR if protection window number was wrong, or the window ++* overlapps other target window. ++* ++*******************************************************************************/ ++MV_STATUS mvCpuIfTargetWinEnable(MV_TARGET target,MV_BOOL enable) ++{ ++ MV_U32 winNum, temp; ++ MV_CPU_DEC_WIN addrDecWin; ++ ++ target = MV_CHANGE_BOOT_CS(target); ++ ++ /* Check parameters */ ++ if (target >= MAX_TARGETS) ++ { ++ mvOsPrintf("mvCpuIfTargetWinEnable: target %d is Illigal\n", target); ++ return MV_ERROR; ++ } ++ ++ /* get the window and check if it exist */ ++ temp = mvCpuIfTargetWinGet(target, &addrDecWin); ++ if (MV_NO_SUCH == temp) ++ { ++ return (enable? MV_ERROR: MV_OK); ++ } ++ else if( MV_OK != temp) ++ { ++ mvOsPrintf("%s: ERR. Getting target %d failed.\n",__FUNCTION__, target); ++ return MV_ERROR; ++ } ++ ++ ++ /* check overlap */ ++ ++ if (MV_TRUE == enable) ++ { ++ if (MV_TRUE == cpuTargetWinOverlap(target, &addrDecWin.addrWin)) ++ { ++ DB(mvOsPrintf("%s: ERR. Target %d overlap\n",__FUNCTION__, target)); ++ return MV_ERROR; ++ } ++ ++ } ++ ++ ++ if (MV_TARGET_IS_DRAM(target)) ++ { ++ if (mvDramIfWinEnable(target , enable) != MV_OK) ++ { ++ mvOsPrintf("mvCpuIfTargetWinGet: mvDramIfWinEnable Failed at \n"); ++ return MV_ERROR; ++ ++ } ++ ++ } ++ else ++ { ++ /* get the Window number associated with this target */ ++ ++ winNum = mvAhbToMbusWinTargetGet(target); ++ ++ if (winNum >= MAX_AHB_TO_MBUS_WINS) ++ { ++ return (enable? MV_ERROR: MV_OK); ++ } ++ ++ if (mvAhbToMbusWinEnable(winNum , enable) != MV_OK) ++ { ++ mvOsPrintf("mvCpuIfTargetWinGet: Failed to enable window = %d\n", ++ winNum); ++ return MV_ERROR; ++ ++ } ++ ++ } ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvCpuIfTargetWinSizeGet - Get CPU target address window size ++* ++* DESCRIPTION: ++* Get the size of CPU-to-peripheral target window. ++* ++* INPUT: ++* target - Peripheral target enumerator ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit size. Function also returns '0' if window is closed. ++* Function returns 0xFFFFFFFF in case of an error. ++* ++*******************************************************************************/ ++MV_U32 mvCpuIfTargetWinSizeGet(MV_TARGET target) ++{ ++ MV_CPU_DEC_WIN addrDecWin; ++ ++ target = MV_CHANGE_BOOT_CS(target); ++ ++ /* Check parameters */ ++ if (target >= MAX_TARGETS) ++ { ++ mvOsPrintf("mvCpuIfTargetWinSizeGet: target %d is Illigal\n", target); ++ return 0; ++ } ++ ++ /* Get the winNum window */ ++ if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) ++ { ++ mvOsPrintf("mvCpuIfTargetWinSizeGet:ERR. Getting target %d failed.\n", ++ target); ++ return 0; ++ } ++ ++ /* Check if window is enabled */ ++ if (addrDecWin.enable == MV_TRUE) ++ { ++ return (addrDecWin.addrWin.size); ++ } ++ else ++ { ++ return 0; /* Window disabled. return 0 */ ++ } ++} ++ ++/******************************************************************************* ++* mvCpuIfTargetWinBaseLowGet - Get CPU target address window base low ++* ++* DESCRIPTION: ++* CPU-to-peripheral target address window base is constructed of ++* two parts: Low and high. ++* This function gets the CPU peripheral target low base address. ++* ++* INPUT: ++* target - Peripheral target enumerator ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit low base address. ++* ++*******************************************************************************/ ++MV_U32 mvCpuIfTargetWinBaseLowGet(MV_TARGET target) ++{ ++ MV_CPU_DEC_WIN addrDecWin; ++ ++ target = MV_CHANGE_BOOT_CS(target); ++ ++ /* Check parameters */ ++ if (target >= MAX_TARGETS) ++ { ++ mvOsPrintf("mvCpuIfTargetWinBaseLowGet: target %d is Illigal\n", target); ++ return 0xffffffff; ++ } ++ ++ /* Get the target window */ ++ if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) ++ { ++ mvOsPrintf("mvCpuIfTargetWinBaseLowGet:ERR. Getting target %d failed.\n", ++ target); ++ return 0xffffffff; ++ } ++ ++ if (MV_FALSE == addrDecWin.enable) ++ { ++ return 0xffffffff; ++ } ++ return (addrDecWin.addrWin.baseLow); ++} ++ ++/******************************************************************************* ++* mvCpuIfTargetWinBaseHighGet - Get CPU target address window base high ++* ++* DESCRIPTION: ++* CPU-to-peripheral target address window base is constructed of ++* two parts: Low and high. ++* This function gets the CPU peripheral target high base address. ++* ++* INPUT: ++* target - Peripheral target enumerator ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit high base address. ++* ++*******************************************************************************/ ++MV_U32 mvCpuIfTargetWinBaseHighGet(MV_TARGET target) ++{ ++ MV_CPU_DEC_WIN addrDecWin; ++ ++ target = MV_CHANGE_BOOT_CS(target); ++ ++ /* Check parameters */ ++ if (target >= MAX_TARGETS) ++ { ++ mvOsPrintf("mvCpuIfTargetWinBaseLowGet: target %d is Illigal\n", target); ++ return 0xffffffff; ++ } ++ ++ /* Get the target window */ ++ if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) ++ { ++ mvOsPrintf("mvCpuIfTargetWinBaseHighGet:ERR. Getting target %d failed.\n", ++ target); ++ return 0xffffffff; ++ } ++ ++ if (MV_FALSE == addrDecWin.enable) ++ { ++ return 0; ++ } ++ ++ return (addrDecWin.addrWin.baseHigh); ++} ++ ++#if defined(MV_INCLUDE_PEX) ++/******************************************************************************* ++* mvCpuIfPexRemap - Set CPU remap register for address windows. ++* ++* DESCRIPTION: ++* ++* INPUT: ++* pexTarget - Peripheral target enumerator. Must be a PEX target. ++* pAddrDecWin - CPU target window information data structure. ++* Note that caller has to fill in the base field only. The ++* size field is ignored. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_ERROR if target is not a PEX one, MV_OK otherwise. ++* ++*******************************************************************************/ ++MV_U32 mvCpuIfPexRemap(MV_TARGET pexTarget, MV_ADDR_WIN *pAddrDecWin) ++{ ++ MV_U32 winNum; ++ ++ /* Check parameters */ ++ ++ if (mvCtrlPexMaxIfGet() > 1) ++ { ++ if ((!MV_TARGET_IS_PEX1(pexTarget))&&(!MV_TARGET_IS_PEX0(pexTarget))) ++ { ++ mvOsPrintf("mvCpuIfPexRemap: target %d is Illigal\n",pexTarget); ++ return 0xffffffff; ++ } ++ ++ } ++ else ++ { ++ if (!MV_TARGET_IS_PEX0(pexTarget)) ++ { ++ mvOsPrintf("mvCpuIfPexRemap: target %d is Illigal\n",pexTarget); ++ return 0xffffffff; ++ } ++ ++ } ++ ++ /* get the Window number associated with this target */ ++ winNum = mvAhbToMbusWinTargetGet(pexTarget); ++ ++ if (winNum >= MAX_AHB_TO_MBUS_WINS) ++ { ++ mvOsPrintf("mvCpuIfPexRemap: mvAhbToMbusWinTargetGet Failed\n"); ++ return 0xffffffff; ++ ++ } ++ ++ return mvAhbToMbusWinRemap(winNum , pAddrDecWin); ++} ++ ++#endif ++ ++#if defined(MV_INCLUDE_PCI) ++/******************************************************************************* ++* mvCpuIfPciRemap - Set CPU remap register for address windows. ++* ++* DESCRIPTION: ++* ++* INPUT: ++* pciTarget - Peripheral target enumerator. Must be a PCI target. ++* pAddrDecWin - CPU target window information data structure. ++* Note that caller has to fill in the base field only. The ++* size field is ignored. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_ERROR if target is not a PCI one, MV_OK otherwise. ++* ++*******************************************************************************/ ++MV_U32 mvCpuIfPciRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin) ++{ ++ MV_U32 winNum; ++ ++ /* Check parameters */ ++ if (!MV_TARGET_IS_PCI(pciTarget)) ++ { ++ mvOsPrintf("mvCpuIfPciRemap: target %d is Illigal\n",pciTarget); ++ return 0xffffffff; ++ } ++ ++ /* get the Window number associated with this target */ ++ winNum = mvAhbToMbusWinTargetGet(pciTarget); ++ ++ if (winNum >= MAX_AHB_TO_MBUS_WINS) ++ { ++ mvOsPrintf("mvCpuIfPciRemap: mvAhbToMbusWinTargetGet Failed\n"); ++ return 0xffffffff; ++ ++ } ++ ++ return mvAhbToMbusWinRemap(winNum , pAddrDecWin); ++} ++#endif /* MV_INCLUDE_PCI */ ++ ++ ++/******************************************************************************* ++* mvCpuIfPciIfRemap - Set CPU remap register for address windows. ++* ++* DESCRIPTION: ++* ++* INPUT: ++* pciTarget - Peripheral target enumerator. Must be a PCI target. ++* pAddrDecWin - CPU target window information data structure. ++* Note that caller has to fill in the base field only. The ++* size field is ignored. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_ERROR if target is not a PCI one, MV_OK otherwise. ++* ++*******************************************************************************/ ++MV_U32 mvCpuIfPciIfRemap(MV_TARGET pciIfTarget, MV_ADDR_WIN *pAddrDecWin) ++{ ++#if defined(MV_INCLUDE_PEX) ++ if (MV_TARGET_IS_PEX(pciIfTarget)) ++ { ++ return mvCpuIfPexRemap(pciIfTarget,pAddrDecWin); ++ } ++#endif ++#if defined(MV_INCLUDE_PCI) ++ ++ if (MV_TARGET_IS_PCI(pciIfTarget)) ++ { ++ return mvCpuIfPciRemap(pciIfTarget,pAddrDecWin); ++ } ++#endif ++ return 0; ++} ++ ++ ++ ++/******************************************************************************* ++* mvCpuIfTargetOfBaseAddressGet - Get the target according to base address ++* ++* DESCRIPTION: ++* ++* INPUT: ++* baseAddress - base address to be checked ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* the target number that baseAddress belongs to or MAX_TARGETS is not ++* found ++* ++*******************************************************************************/ ++ ++MV_TARGET mvCpuIfTargetOfBaseAddressGet(MV_U32 baseAddress) ++{ ++ MV_CPU_DEC_WIN win; ++ MV_U32 target; ++ ++ for( target = 0; target < MAX_TARGETS; target++ ) ++ { ++ if( mvCpuIfTargetWinGet( target, &win ) == MV_OK ) ++ { ++ if( win.enable ) ++ { ++ if ((baseAddress >= win.addrWin.baseLow) && ++ (baseAddress < win.addrWin.baseLow + win.addrWin.size)) break; ++ } ++ } ++ else return MAX_TARGETS; ++ ++ } ++ ++ return target; ++} ++/******************************************************************************* ++* cpuTargetWinOverlap - Detect CPU address decode windows overlapping ++* ++* DESCRIPTION: ++* An unpredicted behaviur is expected in case CPU address decode ++* windows overlapps. ++* This function detects CPU address decode windows overlapping of a ++* specified target. The function does not check the target itself for ++* overlapping. The function also skipps disabled address decode windows. ++* ++* INPUT: ++* target - Peripheral target enumerator. ++* pAddrDecWin - An address decode window struct. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the given address window overlaps current address ++* decode map, MV_FALSE otherwise. ++* ++*******************************************************************************/ ++static MV_BOOL cpuTargetWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin) ++{ ++ MV_U32 targetNum; ++ MV_CPU_DEC_WIN addrDecWin; ++ MV_STATUS status; ++ ++ ++ for(targetNum = 0; targetNum < MAX_TARGETS; targetNum++) ++ { ++#if defined(MV_RUN_FROM_FLASH) ++ if(MV_TARGET_IS_AS_BOOT(target)) ++ { ++ if (MV_CHANGE_BOOT_CS(targetNum) == target) ++ continue; ++ } ++#endif /* MV_RUN_FROM_FLASH */ ++ ++ /* don't check our target or illegal targets */ ++ if (targetNum == target) ++ { ++ continue; ++ } ++ ++ /* Get window parameters */ ++ status = mvCpuIfTargetWinGet(targetNum, &addrDecWin); ++ if(MV_NO_SUCH == status) ++ { ++ continue; ++ } ++ if(MV_OK != status) ++ { ++ DB(mvOsPrintf("cpuTargetWinOverlap: ERR. TargetWinGet failed\n")); ++ return MV_TRUE; ++ } ++ ++ /* Do not check disabled windows */ ++ if (MV_FALSE == addrDecWin.enable) ++ { ++ continue; ++ } ++ ++ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) ++ { ++ DB(mvOsPrintf( ++ "cpuTargetWinOverlap: Required target %d overlap current %d\n", ++ target, targetNum)); ++ return MV_TRUE; ++ } ++ } ++ ++ return MV_FALSE; ++ ++} ++ ++/******************************************************************************* ++* mvCpuIfAddDecShow - Print the CPU address decode map. ++* ++* DESCRIPTION: ++* This function print the CPU address decode map. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvCpuIfAddDecShow(MV_VOID) ++{ ++ MV_CPU_DEC_WIN win; ++ MV_U32 target; ++ mvOsOutput( "\n" ); ++ mvOsOutput( "CPU Interface\n" ); ++ mvOsOutput( "-------------\n" ); ++ ++ for( target = 0; target < MAX_TARGETS; target++ ) ++ { ++ ++ memset( &win, 0, sizeof(MV_CPU_DEC_WIN) ); ++ ++ mvOsOutput( "%s ",mvCtrlTargetNameGet(target)); ++ mvOsOutput( "...." ); ++ ++ if( mvCpuIfTargetWinGet( target, &win ) == MV_OK ) ++ { ++ if( win.enable ) ++ { ++ mvOsOutput( "base %08x, ", win.addrWin.baseLow ); ++ mvSizePrint( win.addrWin.size ); ++ mvOsOutput( "\n" ); ++ ++ } ++ else ++ mvOsOutput( "disable\n" ); ++ } ++ else if( mvCpuIfTargetWinGet( target, &win ) == MV_NO_SUCH ) ++ { ++ mvOsOutput( "no such\n" ); ++ } ++ } ++} ++ ++/******************************************************************************* ++* mvCpuIfEnablePex - Enable PCI Express. ++* ++* DESCRIPTION: ++* This function Enable PCI Express. ++* ++* INPUT: ++* pexIf - PEX interface number. ++* pexType - MV_PEX_ROOT_COMPLEX - root complex device ++* MV_PEX_END_POINT - end point device ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++#if defined(MV_INCLUDE_PEX) ++MV_VOID mvCpuIfEnablePex(MV_U32 pexIf, MV_PEX_TYPE pexType) ++{ ++ /* Set pex mode incase S@R not exist */ ++ if( pexType == MV_PEX_END_POINT) ++ { ++ MV_REG_BIT_RESET(PEX_CTRL_REG(pexIf),PXCR_DEV_TYPE_CTRL_MASK); ++ /* Change pex mode in capability reg */ ++ MV_REG_BIT_RESET(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_CAPABILITY_REG), BIT22); ++ MV_REG_BIT_SET(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_CAPABILITY_REG), BIT20); ++ ++ } ++ else ++ { ++ MV_REG_BIT_SET(PEX_CTRL_REG(pexIf),PXCR_DEV_TYPE_CTRL_MASK); ++ } ++ ++ /* CPU config register Pex enable */ ++ MV_REG_BIT_SET(CPU_CTRL_STAT_REG,CCSR_PCI_ACCESS_MASK); ++} ++#endif ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,120 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvCpuIfh ++#define __INCmvCpuIfh ++ ++/* includes */ ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "ctrlEnv/sys/mvCpuIfRegs.h" ++#include "ctrlEnv/sys/mvAhbToMbus.h" ++#include "ddr2/mvDramIf.h" ++#include "ctrlEnv/sys/mvSysDram.h" ++#if defined(MV_INCLUDE_PEX) ++#include "pex/mvPex.h" ++#endif ++ ++/* defines */ ++ ++/* typedefs */ ++/* This structure describes CPU interface address decode window */ ++typedef struct _mvCpuIfDecWin ++{ ++ MV_ADDR_WIN addrWin; /* An address window*/ ++ MV_U32 winNum; /* Window Number in the AHB To Mbus bridge */ ++ MV_BOOL enable; /* Address decode window is enabled/disabled */ ++ ++}MV_CPU_DEC_WIN; ++ ++ ++ ++/* mvCpuIfLib.h API list */ ++ ++/* mvCpuIfLib.h API list */ ++ ++MV_STATUS mvCpuIfInit(MV_CPU_DEC_WIN *cpuAddrWinMap); ++MV_STATUS mvCpuIfTargetWinSet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin); ++MV_STATUS mvCpuIfTargetWinGet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin); ++MV_STATUS mvCpuIfTargetWinEnable(MV_TARGET target,MV_BOOL enable); ++MV_U32 mvCpuIfTargetWinSizeGet(MV_TARGET target); ++MV_U32 mvCpuIfTargetWinBaseLowGet(MV_TARGET target); ++MV_U32 mvCpuIfTargetWinBaseHighGet(MV_TARGET target); ++MV_TARGET mvCpuIfTargetOfBaseAddressGet(MV_U32 baseAddress); ++#if defined(MV_INCLUDE_PEX) ++MV_U32 mvCpuIfPexRemap(MV_TARGET pexTarget, MV_ADDR_WIN *pAddrDecWin); ++MV_VOID mvCpuIfEnablePex(MV_U32 pexIf, MV_PEX_TYPE pexType); ++#endif ++#if defined(MV_INCLUDE_PCI) ++MV_U32 mvCpuIfPciRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin); ++#endif ++MV_U32 mvCpuIfPciIfRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin); ++ ++MV_VOID mvCpuIfAddDecShow(MV_VOID); ++ ++#if defined(MV88F6281) ++MV_STATUS mvCpuIfBridgeReorderWAInit(void); ++#endif ++ ++#endif /* __INCmvCpuIfh */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfInit.S linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfInit.S +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfInit.S 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfInit.S 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,163 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#define MV_ASMLANGUAGE ++#include "mvOsAsm.h" ++#include "mvDeviceId.h" ++#include "mvCtrlEnvRegs.h" ++#include "mvCpuIfRegs.h" ++#include "mvCtrlEnvAsm.h" ++ ++ ++/******************************************************************************* ++* mvCpuIfPreInit - Make early initialization of CPU interface. ++* ++* DESCRIPTION: ++* The function will initialize the CPU interface parameters that must ++* be initialize before any BUS activity towards the DDR interface, ++* which means it must be executed from ROM. Because of that, the function ++* is implemented in assembly code. ++* The function configure the following CPU config register parameters: ++* 1) CPU2MbusLTickDrv ++* 2) CPU2MbusLTickSample. ++* NOTE: This function must be called AFTER the internal register ++* base is modified to INTER_REGS_BASE. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++* r11 holds return function address. ++*******************************************************************************/ ++#define MV88F6281_PCKG_OPT 2 ++#define MV88F6192_PCKG_OPT 1 ++#define MV88F6180_PCKG_OPT 0 ++ ++ .globl _mvCpuIfPreInit ++_mvCpuIfPreInit: ++ ++ mov r11, LR /* Save link register */ ++ ++ /* Read device ID */ ++ MV_CTRL_MODEL_GET_ASM(r4, r5); ++ ++ /* goto calcConfigReg if device is 6281 */ ++ ldr r5, =MV88F6281_PCKG_OPT ++ cmp r4, r5 ++ beq calcConfigReg ++ ++ /* goto calcConfigReg if device is 6192/6190 */ ++ ldr r5, =MV88F6192_PCKG_OPT ++ cmp r4, r5 ++ beq calcConfigReg ++ ++ /* Else 6180 */ ++ /* Get the "sample on reset" register */ ++ MV_REG_READ_ASM (r4, r5, MPP_SAMPLE_AT_RESET) ++ ldr r5, =MSAR_CPUCLCK_MASK_6180 ++ and r5, r4, r5 ++ mov r5, r5, lsr #MSAR_CPUCLCK_OFFS_6180 ++ ++ ldr r4, =CPU_2_MBUSL_DDR_CLK_1x3 ++ cmp r5, #CPU_2_DDR_CLK_1x3_1 ++ beq setConfigReg ++ ++ ldr r4, =CPU_2_MBUSL_DDR_CLK_1x4 ++ cmp r5, #CPU_2_DDR_CLK_1x4_1 ++ beq setConfigReg ++ b setConfigReg ++ ++calcConfigReg: ++ /* Get the "sample on reset" register */ ++ MV_REG_READ_ASM (r4, r5, MPP_SAMPLE_AT_RESET) ++ ldr r5, =MSAR_DDRCLCK_RTIO_MASK ++ and r5, r4, r5 ++ mov r5, r5, lsr #MSAR_DDRCLCK_RTIO_OFFS ++ ++ ldr r4, =CPU_2_MBUSL_DDR_CLK_1x3 ++ cmp r5, #CPU_2_DDR_CLK_1x3 ++ beq setConfigReg ++ ++ ldr r4, =CPU_2_MBUSL_DDR_CLK_1x4 ++ cmp r5, #CPU_2_DDR_CLK_1x4 ++ beq setConfigReg ++ ++ /* Else */ ++ ldr r4, =0 ++ ++setConfigReg: ++ /* Read CPU Config register */ ++ MV_REG_READ_ASM (r7, r5, CPU_CONFIG_REG) ++ ldr r5, =~(CCR_CPU_2_MBUSL_TICK_DRV_MASK | CCR_CPU_2_MBUSL_TICK_SMPL_MASK) ++ and r7, r7, r5 /* Clear register fields */ ++ orr r7, r7, r4 /* Set the values according to the findings */ ++ MV_REG_WRITE_ASM (r7, r5, CPU_CONFIG_REG) ++ ++done: ++ mov PC, r11 /* r11 is saved link register */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,304 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvCpuIfRegsh ++#define __INCmvCpuIfRegsh ++ ++/****************************************/ ++/* ARM Control and Status Registers Map */ ++/****************************************/ ++ ++#define CPU_CONFIG_REG 0x20100 ++#define CPU_CTRL_STAT_REG 0x20104 ++#define CPU_RSTOUTN_MASK_REG 0x20108 ++#define CPU_SYS_SOFT_RST_REG 0x2010C ++#define CPU_AHB_MBUS_CAUSE_INT_REG 0x20110 ++#define CPU_AHB_MBUS_MASK_INT_REG 0x20114 ++#define CPU_FTDLL_CONFIG_REG 0x20120 ++#define CPU_L2_CONFIG_REG 0x20128 ++ ++ ++ ++/* ARM Configuration register */ ++/* CPU_CONFIG_REG (CCR) */ ++ ++ ++/* Reset vector location */ ++#define CCR_VEC_INIT_LOC_OFFS 1 ++#define CCR_VEC_INIT_LOC_MASK BIT1 ++/* reset at 0x00000000 */ ++#define CCR_VEC_INIT_LOC_0000 (0 << CCR_VEC_INIT_LOC_OFFS) ++/* reset at 0xFFFF0000 */ ++#define CCR_VEC_INIT_LOC_FF00 (1 << CCR_VEC_INIT_LOC_OFFS) ++ ++ ++#define CCR_AHB_ERROR_PROP_OFFS 2 ++#define CCR_AHB_ERROR_PROP_MASK BIT2 ++/* Erros are not propogated to AHB */ ++#define CCR_AHB_ERROR_PROP_NO_INDICATE (0 << CCR_AHB_ERROR_PROP_OFFS) ++/* Erros are propogated to AHB */ ++#define CCR_AHB_ERROR_PROP_INDICATE (1 << CCR_AHB_ERROR_PROP_OFFS) ++ ++ ++#define CCR_ENDIAN_INIT_OFFS 3 ++#define CCR_ENDIAN_INIT_MASK BIT3 ++#define CCR_ENDIAN_INIT_LITTLE (0 << CCR_ENDIAN_INIT_OFFS) ++#define CCR_ENDIAN_INIT_BIG (1 << CCR_ENDIAN_INIT_OFFS) ++ ++ ++#define CCR_INCR_EN_OFFS 4 ++#define CCR_INCR_EN_MASK BIT4 ++#define CCR_INCR_EN BIT4 ++ ++ ++#define CCR_NCB_BLOCKING_OFFS 5 ++#define CCR_NCB_BLOCKING_MASK (1 << CCR_NCB_BLOCKING_OFFS) ++#define CCR_NCB_BLOCKING_NON (0 << CCR_NCB_BLOCKING_OFFS) ++#define CCR_NCB_BLOCKING_EN (1 << CCR_NCB_BLOCKING_OFFS) ++ ++#define CCR_CPU_2_MBUSL_TICK_DRV_OFFS 8 ++#define CCR_CPU_2_MBUSL_TICK_DRV_MASK (0xF << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) ++#define CCR_CPU_2_MBUSL_TICK_SMPL_OFFS 12 ++#define CCR_CPU_2_MBUSL_TICK_SMPL_MASK (0xF << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS) ++#define CCR_ICACH_PREF_BUF_ENABLE BIT16 ++#define CCR_DCACH_PREF_BUF_ENABLE BIT17 ++ ++/* Ratio options for CPU to DDR for 6281/6192/6190 */ ++#define CPU_2_DDR_CLK_1x3 4 ++#define CPU_2_DDR_CLK_1x4 6 ++ ++/* Ratio options for CPU to DDR for 6281 only */ ++#define CPU_2_DDR_CLK_2x9 7 ++#define CPU_2_DDR_CLK_1x5 8 ++#define CPU_2_DDR_CLK_1x6 9 ++ ++/* Ratio options for CPU to DDR for 6180 only */ ++#define CPU_2_DDR_CLK_1x3_1 0x5 ++#define CPU_2_DDR_CLK_1x4_1 0x6 ++ ++/* Default values for CPU to Mbus-L DDR Interface Tick Driver and */ ++/* CPU to Mbus-L Tick Sample fields in CPU config register */ ++ ++#define TICK_DRV_1x1 0 ++#define TICK_DRV_1x2 0 ++#define TICK_DRV_1x3 1 ++#define TICK_DRV_1x4 2 ++#define TICK_SMPL_1x1 0 ++#define TICK_SMPL_1x2 1 ++#define TICK_SMPL_1x3 0 ++#define TICK_SMPL_1x4 0 ++ ++#define CPU_2_MBUSL_DDR_CLK_1x2 \ ++ ((TICK_DRV_1x2 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \ ++ (TICK_SMPL_1x2 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS)) ++#define CPU_2_MBUSL_DDR_CLK_1x3 \ ++ ((TICK_DRV_1x3 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \ ++ (TICK_SMPL_1x3 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS)) ++#define CPU_2_MBUSL_DDR_CLK_1x4 \ ++ ((TICK_DRV_1x4 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \ ++ (TICK_SMPL_1x4 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS)) ++ ++/* ARM Control and Status register */ ++/* CPU_CTRL_STAT_REG (CCSR) */ ++ ++ ++/* ++This is used to block PCI express\PCI from access Socrates/Feroceon GP ++while ARM boot is still in progress ++*/ ++ ++#define CCSR_PCI_ACCESS_OFFS 0 ++#define CCSR_PCI_ACCESS_MASK BIT0 ++#define CCSR_PCI_ACCESS_ENABLE (0 << CCSR_PCI_ACCESS_OFFS) ++#define CCSR_PCI_ACCESS_DISBALE (1 << CCSR_PCI_ACCESS_OFFS) ++ ++#define CCSR_ARM_RESET BIT1 ++#define CCSR_SELF_INT BIT2 ++#define CCSR_BIG_ENDIAN BIT15 ++ ++ ++/* RSTOUTn Mask Register */ ++/* CPU_RSTOUTN_MASK_REG (CRMR) */ ++ ++#define CRMR_PEX_RST_OUT_OFFS 0 ++#define CRMR_PEX_RST_OUT_MASK BIT0 ++#define CRMR_PEX_RST_OUT_ENABLE (1 << CRMR_PEX_RST_OUT_OFFS) ++#define CRMR_PEX_RST_OUT_DISABLE (0 << CRMR_PEX_RST_OUT_OFFS) ++ ++#define CRMR_WD_RST_OUT_OFFS 1 ++#define CRMR_WD_RST_OUT_MASK BIT1 ++#define CRMR_WD_RST_OUT_ENABLE (1 << CRMR_WD_RST_OUT_OFFS) ++#define CRMR_WD_RST_OUT_DISBALE (0 << CRMR_WD_RST_OUT_OFFS) ++ ++#define CRMR_SOFT_RST_OUT_OFFS 2 ++#define CRMR_SOFT_RST_OUT_MASK BIT2 ++#define CRMR_SOFT_RST_OUT_ENABLE (1 << CRMR_SOFT_RST_OUT_OFFS) ++#define CRMR_SOFT_RST_OUT_DISBALE (0 << CRMR_SOFT_RST_OUT_OFFS) ++ ++/* System Software Reset Register */ ++/* CPU_SYS_SOFT_RST_REG (CSSRR) */ ++ ++#define CSSRR_SYSTEM_SOFT_RST BIT0 ++ ++/* AHB to Mbus Bridge Interrupt Cause Register*/ ++/* CPU_AHB_MBUS_CAUSE_INT_REG (CAMCIR) */ ++ ++#define CAMCIR_ARM_SELF_INT BIT0 ++#define CAMCIR_ARM_TIMER0_INT_REQ BIT1 ++#define CAMCIR_ARM_TIMER1_INT_REQ BIT2 ++#define CAMCIR_ARM_WD_TIMER_INT_REQ BIT3 ++ ++ ++/* AHB to Mbus Bridge Interrupt Mask Register*/ ++/* CPU_AHB_MBUS_MASK_INT_REG (CAMMIR) */ ++ ++#define CAMCIR_ARM_SELF_INT_OFFS 0 ++#define CAMCIR_ARM_SELF_INT_MASK BIT0 ++#define CAMCIR_ARM_SELF_INT_EN (1 << CAMCIR_ARM_SELF_INT_OFFS) ++#define CAMCIR_ARM_SELF_INT_DIS (0 << CAMCIR_ARM_SELF_INT_OFFS) ++ ++ ++#define CAMCIR_ARM_TIMER0_INT_REQ_OFFS 1 ++#define CAMCIR_ARM_TIMER0_INT_REQ_MASK BIT1 ++#define CAMCIR_ARM_TIMER0_INT_REQ_EN (1 << CAMCIR_ARM_TIMER0_INT_REQ_OFFS) ++#define CAMCIR_ARM_TIMER0_INT_REQ_DIS (0 << CAMCIR_ARM_TIMER0_INT_REQ_OFFS) ++ ++#define CAMCIR_ARM_TIMER1_INT_REQ_OFFS 2 ++#define CAMCIR_ARM_TIMER1_INT_REQ_MASK BIT2 ++#define CAMCIR_ARM_TIMER1_INT_REQ_EN (1 << CAMCIR_ARM_TIMER1_INT_REQ_OFFS) ++#define CAMCIR_ARM_TIMER1_INT_REQ_DIS (0 << CAMCIR_ARM_TIMER1_INT_REQ_OFFS) ++ ++#define CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS 3 ++#define CAMCIR_ARM_WD_TIMER_INT_REQ_MASK BIT3 ++#define CAMCIR_ARM_WD_TIMER_INT_REQ_EN (1 << CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS) ++#define CAMCIR_ARM_WD_TIMER_INT_REQ_DIS (0 << CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS) ++ ++/* CPU FTDLL Config register (CFCR) fields */ ++#define CFCR_FTDLL_ICACHE_TAG_OFFS 0 ++#define CFCR_FTDLL_ICACHE_TAG_MASK (0x7F << CFCR_FTDLL_ICACHE_TAG_OFFS) ++#define CFCR_FTDLL_DCACHE_TAG_OFFS 8 ++#define CFCR_FTDLL_DCACHE_TAG_MASK (0x7F << CFCR_FTDLL_DCACHE_TAG_OFFS) ++#define CFCR_FTDLL_OVERWRITE_ENABLE (1 << 15) ++/* For Orion 2 D2 only */ ++#define CFCR_MRVL_CPU_ID_OFFS 16 ++#define CFCR_MRVL_CPU_ID_MASK (0x1 << CFCR_MRVL_CPU_ID_OFFS) ++#define CFCR_ARM_CPU_ID (0x0 << CFCR_MRVL_CPU_ID_OFFS) ++#define CFCR_MRVL_CPU_ID (0x1 << CFCR_MRVL_CPU_ID_OFFS) ++#define CFCR_VFP_SUB_ARC_NUM_OFFS 7 ++#define CFCR_VFP_SUB_ARC_NUM_MASK (0x1 << CFCR_VFP_SUB_ARC_NUM_OFFS) ++#define CFCR_VFP_SUB_ARC_NUM_1 (0x0 << CFCR_VFP_SUB_ARC_NUM_OFFS) ++#define CFCR_VFP_SUB_ARC_NUM_2 (0x1 << CFCR_VFP_SUB_ARC_NUM_OFFS) ++ ++/* CPU_L2_CONFIG_REG fields */ ++#ifdef MV_CPU_LE ++#define CL2CR_L2_ECC_EN_OFFS 2 ++#define CL2CR_L2_WT_MODE_OFFS 4 ++#else ++#define CL2CR_L2_ECC_EN_OFFS 26 ++#define CL2CR_L2_WT_MODE_OFFS 28 ++#endif ++ ++#define CL2CR_L2_ECC_EN_MASK (1 << CL2CR_L2_ECC_EN_OFFS) ++#define CL2CR_L2_WT_MODE_MASK (1 << CL2CR_L2_WT_MODE_OFFS) ++ ++/*******************************************/ ++/* Main Interrupt Controller Registers Map */ ++/*******************************************/ ++ ++#define CPU_MAIN_INT_CAUSE_REG 0x20200 ++#define CPU_MAIN_IRQ_MASK_REG 0x20204 ++#define CPU_MAIN_FIQ_MASK_REG 0x20208 ++#define CPU_ENPOINT_MASK_REG 0x2020C ++#define CPU_MAIN_INT_CAUSE_HIGH_REG 0x20210 ++#define CPU_MAIN_IRQ_MASK_HIGH_REG 0x20214 ++#define CPU_MAIN_FIQ_MASK_HIGH_REG 0x20218 ++#define CPU_ENPOINT_MASK_HIGH_REG 0x2021C ++ ++ ++/*******************************************/ ++/* ARM Doorbell Registers Map */ ++/*******************************************/ ++ ++#define CPU_HOST_TO_ARM_DRBL_REG 0x20400 ++#define CPU_HOST_TO_ARM_MASK_REG 0x20404 ++#define CPU_ARM_TO_HOST_DRBL_REG 0x20408 ++#define CPU_ARM_TO_HOST_MASK_REG 0x2040C ++ ++ ++ ++/* CPU control register map */ ++/* Set bits means value is about to change according to new value */ ++#define CPU_CONFIG_DEFAULT_MASK (CCR_VEC_INIT_LOC_MASK | CCR_AHB_ERROR_PROP_MASK) ++ ++#define CPU_CONFIG_DEFAULT (CCR_VEC_INIT_LOC_FF00) ++ ++/* CPU Control and status defaults */ ++#define CPU_CTRL_STAT_DEFAULT_MASK (CCSR_PCI_ACCESS_MASK) ++ ++ ++#define CPU_CTRL_STAT_DEFAULT (CCSR_PCI_ACCESS_ENABLE) ++ ++#endif /* __INCmvCpuIfRegsh */ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,324 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++#include "mvSysAudio.h" ++ ++/******************************************************************************* ++* mvAudioWinSet - Set AUDIO target address window ++* ++* DESCRIPTION: ++* This function sets a peripheral target (e.g. SDRAM bank0, PCI_MEM0) ++* address window, also known as address decode window. ++* After setting this target window, the AUDIO will be able to access the ++* target within the address window. ++* ++* INPUT: ++* winNum - AUDIO target address decode window number. ++* pAddrDecWin - AUDIO target window data structure. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_ERROR if address window overlapps with other address decode windows. ++* MV_BAD_PARAM if base address is invalid parameter or target is ++* unknown. ++* ++*******************************************************************************/ ++MV_STATUS mvAudioWinSet(MV_U32 winNum, MV_AUDIO_DEC_WIN *pAddrDecWin) ++{ ++ MV_TARGET_ATTRIB targetAttribs; ++ MV_DEC_REGS decRegs; ++ ++ /* Parameter checking */ ++ if (winNum >= MV_AUDIO_MAX_ADDR_DECODE_WIN) ++ { ++ mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); ++ return MV_BAD_PARAM; ++ } ++ ++ /* check if address is aligned to the size */ ++ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) ++ { ++ mvOsPrintf("mvAudioWinSet:Error setting AUDIO window %d to "\ ++ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", ++ winNum, ++ mvCtrlTargetNameGet(pAddrDecWin->target), ++ pAddrDecWin->addrWin.baseLow, ++ pAddrDecWin->addrWin.size); ++ return MV_ERROR; ++ } ++ ++ decRegs.baseReg = 0; ++ decRegs.sizeReg = 0; ++ ++ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) ++ { ++ mvOsPrintf("%s: mvCtrlAddrDecToReg Failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); ++ ++ /* set attributes */ ++ decRegs.sizeReg &= ~MV_AUDIO_WIN_ATTR_MASK; ++ decRegs.sizeReg |= (targetAttribs.attrib << MV_AUDIO_WIN_ATTR_OFFSET); ++ ++ /* set target ID */ ++ decRegs.sizeReg &= ~MV_AUDIO_WIN_TARGET_MASK; ++ decRegs.sizeReg |= (targetAttribs.targetId << MV_AUDIO_WIN_TARGET_OFFSET); ++ ++ if (pAddrDecWin->enable == MV_TRUE) ++ { ++ decRegs.sizeReg |= MV_AUDIO_WIN_ENABLE_MASK; ++ } ++ else ++ { ++ decRegs.sizeReg &= ~MV_AUDIO_WIN_ENABLE_MASK; ++ } ++ ++ MV_REG_WRITE( MV_AUDIO_WIN_CTRL_REG(winNum), decRegs.sizeReg); ++ MV_REG_WRITE( MV_AUDIO_WIN_BASE_REG(winNum), decRegs.baseReg); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvAudioWinGet - Get AUDIO peripheral target address window. ++* ++* DESCRIPTION: ++* Get AUDIO peripheral target address window. ++* ++* INPUT: ++* winNum - AUDIO target address decode window number. ++* ++* OUTPUT: ++* pAddrDecWin - AUDIO target window data structure. ++* ++* RETURN: ++* MV_ERROR if register parameters are invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvAudioWinGet(MV_U32 winNum, MV_AUDIO_DEC_WIN *pAddrDecWin) ++{ ++ MV_DEC_REGS decRegs; ++ MV_TARGET_ATTRIB targetAttrib; ++ ++ /* Parameter checking */ ++ if (winNum >= MV_AUDIO_MAX_ADDR_DECODE_WIN) ++ { ++ mvOsPrintf("%s : ERR. Invalid winNum %d\n", ++ __FUNCTION__, winNum); ++ return MV_NOT_SUPPORTED; ++ } ++ ++ decRegs.baseReg = MV_REG_READ( MV_AUDIO_WIN_BASE_REG(winNum) ); ++ decRegs.sizeReg = MV_REG_READ( MV_AUDIO_WIN_CTRL_REG(winNum) ); ++ ++ if (MV_OK != mvCtrlRegToAddrDec(&decRegs, &pAddrDecWin->addrWin) ) ++ { ++ mvOsPrintf("%s: mvCtrlRegToAddrDec Failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ /* attrib and targetId */ ++ targetAttrib.attrib = (decRegs.sizeReg & MV_AUDIO_WIN_ATTR_MASK) >> ++ MV_AUDIO_WIN_ATTR_OFFSET; ++ targetAttrib.targetId = (decRegs.sizeReg & MV_AUDIO_WIN_TARGET_MASK) >> ++ MV_AUDIO_WIN_TARGET_OFFSET; ++ ++ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); ++ ++ /* Check if window is enabled */ ++ if(decRegs.sizeReg & MV_AUDIO_WIN_ENABLE_MASK) ++ { ++ pAddrDecWin->enable = MV_TRUE; ++ } ++ else ++ { ++ pAddrDecWin->enable = MV_FALSE; ++ } ++ return MV_OK; ++} ++/******************************************************************************* ++* mvAudioAddrDecShow - Print the AUDIO address decode map. ++* ++* DESCRIPTION: ++* This function print the AUDIO address decode map. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvAudioAddrDecShow(MV_VOID) ++{ ++ ++ MV_AUDIO_DEC_WIN win; ++ int i; ++ ++ if (MV_FALSE == mvCtrlPwrClckGet(AUDIO_UNIT_ID, 0)) ++ return; ++ ++ ++ mvOsOutput( "\n" ); ++ mvOsOutput( "AUDIO:\n" ); ++ mvOsOutput( "----\n" ); ++ ++ for( i = 0; i < MV_AUDIO_MAX_ADDR_DECODE_WIN; i++ ) ++ { ++ memset( &win, 0, sizeof(MV_AUDIO_DEC_WIN) ); ++ ++ mvOsOutput( "win%d - ", i ); ++ ++ if( mvAudioWinGet( i, &win ) == MV_OK ) ++ { ++ if( win.enable ) ++ { ++ mvOsOutput( "%s base %08x, ", ++ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); ++ mvOsOutput( "...." ); ++ ++ mvSizePrint( win.addrWin.size ); ++ ++ mvOsOutput( "\n" ); ++ } ++ else ++ mvOsOutput( "disable\n" ); ++ } ++ } ++} ++ ++ ++/******************************************************************************* ++* mvAudioWinInit - Initialize the integrated AUDIO target address window. ++* ++* DESCRIPTION: ++* Initialize the AUDIO peripheral target address window. ++* ++* INPUT: ++* ++* ++* OUTPUT: ++* ++* ++* RETURN: ++* MV_ERROR if register parameters are invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvAudioInit(MV_VOID) ++{ ++ int winNum; ++ MV_AUDIO_DEC_WIN audioWin; ++ MV_CPU_DEC_WIN cpuAddrDecWin; ++ MV_U32 status; ++ ++ mvAudioHalInit(); ++ ++ /* Initiate Audio address decode */ ++ ++ /* First disable all address decode windows */ ++ for(winNum = 0; winNum < MV_AUDIO_MAX_ADDR_DECODE_WIN; winNum++) ++ { ++ MV_U32 regVal = MV_REG_READ(MV_AUDIO_WIN_CTRL_REG(winNum)); ++ regVal &= ~MV_AUDIO_WIN_ENABLE_MASK; ++ MV_REG_WRITE(MV_AUDIO_WIN_CTRL_REG(winNum), regVal); ++ } ++ ++ for(winNum = 0; winNum < MV_AUDIO_MAX_ADDR_DECODE_WIN; winNum++) ++ { ++ ++ /* We will set the Window to DRAM_CS0 in default */ ++ /* first get attributes from CPU If */ ++ status = mvCpuIfTargetWinGet(SDRAM_CS0, ++ &cpuAddrDecWin); ++ ++ if (MV_OK != status) ++ { ++ mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ if (cpuAddrDecWin.enable == MV_TRUE) ++ { ++ audioWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; ++ audioWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; ++ audioWin.addrWin.size = cpuAddrDecWin.addrWin.size; ++ audioWin.enable = MV_TRUE; ++ audioWin.target = SDRAM_CS0; ++ ++ if(MV_OK != mvAudioWinSet(winNum, &audioWin)) ++ { ++ return MV_ERROR; ++ } ++ } ++ } ++ ++ return MV_OK; ++} ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,123 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++#ifndef __INCMVSysAudioH ++#define __INCMVSysAudioH ++ ++#include "mvCommon.h" ++#include "audio/mvAudio.h" ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++#include "ctrlEnv/sys/mvCpuIf.h" ++ ++/***********************************/ ++/* Audio Address Decoding registers*/ ++/***********************************/ ++ ++#define MV_AUDIO_MAX_ADDR_DECODE_WIN 2 ++#define MV_AUDIO_RECORD_WIN_NUM 0 ++#define MV_AUDIO_PLAYBACK_WIN_NUM 1 ++ ++#define MV_AUDIO_WIN_CTRL_REG(win) (AUDIO_REG_BASE + 0xA04 + ((win)<<3)) ++#define MV_AUDIO_WIN_BASE_REG(win) (AUDIO_REG_BASE + 0xA00 + ((win)<<3)) ++ ++#define MV_AUDIO_RECORD_WIN_CTRL_REG MV_AUDIO_WIN_CTRL_REG(MV_AUDIO_RECORD_WIN_NUM) ++#define MV_AUDIO_RECORD_WIN_BASE_REG MV_AUDIO_WIN_BASE_REG(MV_AUDIO_RECORD_WIN_NUM) ++#define MV_AUDIO_PLAYBACK_WIN_CTRL_REG MV_AUDIO_WIN_CTRL_REG(MV_AUDIO_PLAYBACK_WIN_NUM) ++#define MV_AUDIO_PLAYBACK_WIN_BASE_REG MV_AUDIO_WIN_BASE_REG(MV_AUDIO_PLAYBACK_WIN_NUM) ++ ++ ++/* BITs in Windows 0-3 Control and Base Registers */ ++#define MV_AUDIO_WIN_ENABLE_BIT 0 ++#define MV_AUDIO_WIN_ENABLE_MASK (1<= 2) ++MV_TARGET tdmaAddrDecPrioTable[] = ++{ ++#if defined(MV_INCLUDE_SDRAM_CS0) ++ SDRAM_CS0, ++#endif ++#if defined(MV_INCLUDE_SDRAM_CS1) ++ SDRAM_CS1, ++#endif ++#if defined(MV_INCLUDE_SDRAM_CS2) ++ SDRAM_CS2, ++#endif ++#if defined(MV_INCLUDE_SDRAM_CS3) ++ SDRAM_CS3, ++#endif ++#if defined(MV_INCLUDE_PEX) ++ PEX0_MEM, ++#endif ++ ++ TBL_TERM ++}; ++ ++/******************************************************************************* ++* mvCesaWinGet - Get TDMA target address window. ++* ++* DESCRIPTION: ++* Get TDMA target address window. ++* ++* INPUT: ++* winNum - TDMA target address decode window number. ++* ++* OUTPUT: ++* pDecWin - TDMA target window data structure. ++* ++* RETURN: ++* MV_ERROR if register parameters are invalid. ++* ++*******************************************************************************/ ++static MV_STATUS mvCesaWinGet(MV_U32 winNum, MV_DEC_WIN *pDecWin) ++{ ++ MV_DEC_WIN_PARAMS winParam; ++ MV_U32 sizeReg, baseReg; ++ ++ /* Parameter checking */ ++ if (winNum >= MV_CESA_TDMA_ADDR_DEC_WIN) ++ { ++ mvOsPrintf("%s : ERR. Invalid winNum %d\n", ++ __FUNCTION__, winNum); ++ return MV_NOT_SUPPORTED; ++ } ++ ++ baseReg = MV_REG_READ( MV_CESA_TDMA_BASE_ADDR_REG(winNum) ); ++ sizeReg = MV_REG_READ( MV_CESA_TDMA_WIN_CTRL_REG(winNum) ); ++ ++ /* Check if window is enabled */ ++ if(sizeReg & MV_CESA_TDMA_WIN_ENABLE_MASK) ++ { ++ pDecWin->enable = MV_TRUE; ++ ++ /* Extract window parameters from registers */ ++ winParam.targetId = (sizeReg & MV_CESA_TDMA_WIN_TARGET_MASK) >> MV_CESA_TDMA_WIN_TARGET_OFFSET; ++ winParam.attrib = (sizeReg & MV_CESA_TDMA_WIN_ATTR_MASK) >> MV_CESA_TDMA_WIN_ATTR_OFFSET; ++ winParam.size = (sizeReg & MV_CESA_TDMA_WIN_SIZE_MASK) >> MV_CESA_TDMA_WIN_SIZE_OFFSET; ++ winParam.baseAddr = (baseReg & MV_CESA_TDMA_WIN_BASE_MASK); ++ ++ /* Translate the decode window parameters to address decode struct */ ++ if (MV_OK != mvCtrlParamsToAddrDec(&winParam, pDecWin)) ++ { ++ mvOsPrintf("Failed to translate register parameters to CESA address" \ ++ " decode window structure\n"); ++ return MV_ERROR; ++ } ++ } ++ else ++ { ++ pDecWin->enable = MV_FALSE; ++ } ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* cesaWinOverlapDetect - Detect CESA TDMA address windows overlapping ++* ++* DESCRIPTION: ++* An unpredicted behaviur is expected in case TDMA address decode ++* windows overlapps. ++* This function detects TDMA address decode windows overlapping of a ++* specified window. The function does not check the window itself for ++* overlapping. The function also skipps disabled address decode windows. ++* ++* INPUT: ++* winNum - address decode window number. ++* pAddrDecWin - An address decode window struct. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE - if the given address window overlap current address ++* decode map, ++* MV_FALSE - otherwise, MV_ERROR if reading invalid data ++* from registers. ++* ++*******************************************************************************/ ++static MV_STATUS cesaWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) ++{ ++ MV_U32 winNumIndex; ++ MV_DEC_WIN addrDecWin; ++ ++ for(winNumIndex=0; winNumIndex= MV_CESA_TDMA_ADDR_DEC_WIN) ++ { ++ mvOsPrintf("mvCesaTdmaWinSet: ERR. Invalid win num %d\n",winNum); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check if the requested window overlapps with current windows */ ++ if (MV_TRUE == cesaWinOverlapDetect(winNum, &pDecWin->addrWin)) ++ { ++ mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); ++ return MV_ERROR; ++ } ++ ++ /* check if address is aligned to the size */ ++ if(MV_IS_NOT_ALIGN(pDecWin->addrWin.baseLow, pDecWin->addrWin.size)) ++ { ++ mvOsPrintf("mvCesaTdmaWinSet: Error setting CESA TDMA window %d to "\ ++ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", ++ winNum, ++ mvCtrlTargetNameGet(pDecWin->target), ++ pDecWin->addrWin.baseLow, ++ pDecWin->addrWin.size); ++ return MV_ERROR; ++ } ++ ++ if(MV_OK != mvCtrlAddrDecToParams(pDecWin, &winParams)) ++ { ++ mvOsPrintf("%s: mvCtrlAddrDecToParams Failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ /* set Size, Attributes and TargetID */ ++ sizeReg = (((winParams.targetId << MV_CESA_TDMA_WIN_TARGET_OFFSET) & MV_CESA_TDMA_WIN_TARGET_MASK) | ++ ((winParams.attrib << MV_CESA_TDMA_WIN_ATTR_OFFSET) & MV_CESA_TDMA_WIN_ATTR_MASK) | ++ ((winParams.size << MV_CESA_TDMA_WIN_SIZE_OFFSET) & MV_CESA_TDMA_WIN_SIZE_MASK)); ++ ++ if (pDecWin->enable == MV_TRUE) ++ { ++ sizeReg |= MV_CESA_TDMA_WIN_ENABLE_MASK; ++ } ++ else ++ { ++ sizeReg &= ~MV_CESA_TDMA_WIN_ENABLE_MASK; ++ } ++ ++ /* Update Base value */ ++ baseReg = (winParams.baseAddr & MV_CESA_TDMA_WIN_BASE_MASK); ++ ++ MV_REG_WRITE( MV_CESA_TDMA_WIN_CTRL_REG(winNum), sizeReg); ++ MV_REG_WRITE( MV_CESA_TDMA_BASE_ADDR_REG(winNum), baseReg); ++ ++ return MV_OK; ++} ++ ++ ++static MV_STATUS mvCesaTdmaAddrDecInit (void) ++{ ++ MV_U32 winNum; ++ MV_STATUS status; ++ MV_CPU_DEC_WIN cpuAddrDecWin; ++ MV_DEC_WIN cesaWin; ++ MV_U32 winPrioIndex = 0; ++ ++ /* First disable all address decode windows */ ++ for(winNum=0; winNum= 2 */ ++ ++ ++ ++ ++MV_STATUS mvCesaInit (int numOfSession, int queueDepth, char* pSramBase, void *osHandle) ++{ ++ MV_U32 cesaCryptEngBase; ++ MV_CPU_DEC_WIN addrDecWin; ++ ++ if(sizeof(MV_CESA_SRAM_MAP) > MV_CESA_SRAM_SIZE) ++ { ++ mvOsPrintf("mvCesaInit: Wrong SRAM map - %ld > %d\n", ++ sizeof(MV_CESA_SRAM_MAP), MV_CESA_SRAM_SIZE); ++ return MV_FAIL; ++ } ++#if 0 ++ if (mvCpuIfTargetWinGet(CRYPT_ENG, &addrDecWin) == MV_OK) ++ cesaCryptEngBase = addrDecWin.addrWin.baseLow; ++ else ++ { ++ mvOsPrintf("mvCesaInit: ERR. mvCpuIfTargetWinGet failed\n"); ++ return MV_ERROR; ++ } ++#else ++ cesaCryptEngBase = (MV_U32)pSramBase; ++#endif ++ ++#if 0 /* Already done in the platform init */ ++#if (MV_CESA_VERSION >= 2) ++ mvCesaTdmaAddrDecInit(); ++#endif /* MV_CESA_VERSION >= 2 */ ++#endif ++ return mvCesaHalInit(numOfSession, queueDepth, pSramBase, cesaCryptEngBase, ++ osHandle); ++ ++} +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,100 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __mvSysCesa_h__ ++#define __mvSysCesa_h__ ++ ++ ++#include "mvCommon.h" ++#include "cesa/mvCesa.h" ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++#include "ctrlEnv/sys/mvCpuIf.h" ++ ++/***************************** TDMA Registers *************************************/ ++ ++#define MV_CESA_TDMA_ADDR_DEC_WIN 4 ++ ++#define MV_CESA_TDMA_BASE_ADDR_REG(win) (MV_CESA_TDMA_REG_BASE + 0xa00 + (win<<3)) ++ ++#define MV_CESA_TDMA_WIN_CTRL_REG(win) (MV_CESA_TDMA_REG_BASE + 0xa04 + (win<<3)) ++ ++#define MV_CESA_TDMA_WIN_ENABLE_BIT 0 ++#define MV_CESA_TDMA_WIN_ENABLE_MASK (1 << MV_CESA_TDMA_WIN_ENABLE_BIT) ++ ++#define MV_CESA_TDMA_WIN_TARGET_OFFSET 4 ++#define MV_CESA_TDMA_WIN_TARGET_MASK (0xf << MV_CESA_TDMA_WIN_TARGET_OFFSET) ++ ++#define MV_CESA_TDMA_WIN_ATTR_OFFSET 8 ++#define MV_CESA_TDMA_WIN_ATTR_MASK (0xff << MV_CESA_TDMA_WIN_ATTR_OFFSET) ++ ++#define MV_CESA_TDMA_WIN_SIZE_OFFSET 16 ++#define MV_CESA_TDMA_WIN_SIZE_MASK (0xFFFF << MV_CESA_TDMA_WIN_SIZE_OFFSET) ++ ++#define MV_CESA_TDMA_WIN_BASE_OFFSET 16 ++#define MV_CESA_TDMA_WIN_BASE_MASK (0xFFFF << MV_CESA_TDMA_WIN_BASE_OFFSET) ++ ++ ++MV_STATUS mvCesaInit (int numOfSession, int queueDepth, char* pSramBase, void *osHandle); ++ ++#endif +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,348 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++/* includes */ ++ ++#include "ddr2/mvDramIf.h" ++#include "ctrlEnv/sys/mvCpuIf.h" ++#include "ctrlEnv/sys/mvSysDram.h" ++ ++/* #define MV_DEBUG */ ++#ifdef MV_DEBUG ++#define DB(x) x ++#else ++#define DB(x) ++#endif ++ ++static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin); ++ ++/******************************************************************************* ++* mvDramIfWinSet - Set DRAM interface address decode window ++* ++* DESCRIPTION: ++* This function sets DRAM interface address decode window. ++* ++* INPUT: ++* target - System target. Use only SDRAM targets. ++* pAddrDecWin - SDRAM address window structure. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK ++* otherwise. ++*******************************************************************************/ ++MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) ++{ ++ MV_U32 baseReg=0,sizeReg=0; ++ MV_U32 baseToReg=0 , sizeToReg=0; ++ ++ /* Check parameters */ ++ if (!MV_TARGET_IS_DRAM(target)) ++ { ++ mvOsPrintf("mvDramIfWinSet: target %d is not SDRAM\n", target); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check if the requested window overlaps with current enabled windows */ ++ if (MV_TRUE == sdramIfWinOverlap(target, &pAddrDecWin->addrWin)) ++ { ++ mvOsPrintf("mvDramIfWinSet: ERR. Target %d overlaps\n", target); ++ return MV_BAD_PARAM; ++ } ++ ++ /* check if address is aligned to the size */ ++ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) ++ { ++ mvOsPrintf("mvDramIfWinSet:Error setting DRAM interface window %d."\ ++ "\nAddress 0x%08x is unaligned to size 0x%x.\n", ++ target, ++ pAddrDecWin->addrWin.baseLow, ++ pAddrDecWin->addrWin.size); ++ return MV_ERROR; ++ } ++ ++ /* read base register*/ ++ baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(0,target)); ++ ++ /* read size register */ ++ sizeReg = MV_REG_READ(SDRAM_SIZE_REG(0,target)); ++ ++ /* BaseLow[31:16] => base register [31:16] */ ++ baseToReg = pAddrDecWin->addrWin.baseLow & SCBAR_BASE_MASK; ++ ++ /* Write to address decode Base Address Register */ ++ baseReg &= ~SCBAR_BASE_MASK; ++ baseReg |= baseToReg; ++ ++ /* Translate the given window size to register format */ ++ sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, SCSR_SIZE_ALIGNMENT); ++ ++ /* Size parameter validity check. */ ++ if (-1 == sizeToReg) ++ { ++ mvOsPrintf("mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n",target); ++ return MV_BAD_PARAM; ++ } ++ ++ /* set size */ ++ sizeReg &= ~SCSR_SIZE_MASK; ++ /* Size is located at upper 16 bits */ ++ sizeReg |= (sizeToReg << SCSR_SIZE_OFFS); ++ ++ /* enable/Disable */ ++ if (MV_TRUE == pAddrDecWin->enable) ++ { ++ sizeReg |= SCSR_WIN_EN; ++ } ++ else ++ { ++ sizeReg &= ~SCSR_WIN_EN; ++ } ++ ++ /* 3) Write to address decode Base Address Register */ ++ MV_REG_WRITE(SDRAM_BASE_ADDR_REG(0,target), baseReg); ++ ++ /* Write to address decode Size Register */ ++ MV_REG_WRITE(SDRAM_SIZE_REG(0,target), sizeReg); ++ ++ return MV_OK; ++} ++/******************************************************************************* ++* mvDramIfWinGet - Get DRAM interface address decode window ++* ++* DESCRIPTION: ++* This function gets DRAM interface address decode window. ++* ++* INPUT: ++* target - System target. Use only SDRAM targets. ++* ++* OUTPUT: ++* pAddrDecWin - SDRAM address window structure. ++* ++* RETURN: ++* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK ++* otherwise. ++*******************************************************************************/ ++MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) ++{ ++ MV_U32 baseReg,sizeReg; ++ MV_U32 sizeRegVal; ++ /* Check parameters */ ++ if (!MV_TARGET_IS_DRAM(target)) ++ { ++ mvOsPrintf("mvDramIfWinGet: target %d is Illigal\n", target); ++ return MV_ERROR; ++ } ++ ++ /* Read base and size registers */ ++ sizeReg = MV_REG_READ(SDRAM_SIZE_REG(0,target)); ++ baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(0,target)); ++ ++ sizeRegVal = (sizeReg & SCSR_SIZE_MASK) >> SCSR_SIZE_OFFS; ++ ++ pAddrDecWin->addrWin.size = ctrlRegToSize(sizeRegVal, ++ SCSR_SIZE_ALIGNMENT); ++ ++ /* Check if ctrlRegToSize returned OK */ ++ if (-1 == pAddrDecWin->addrWin.size) ++ { ++ mvOsPrintf("mvDramIfWinGet: size of target %d is Illigal\n", target); ++ return MV_ERROR; ++ } ++ ++ /* Extract base address */ ++ /* Base register [31:16] ==> baseLow[31:16] */ ++ pAddrDecWin->addrWin.baseLow = baseReg & SCBAR_BASE_MASK; ++ ++ pAddrDecWin->addrWin.baseHigh = 0; ++ ++ ++ if (sizeReg & SCSR_WIN_EN) ++ { ++ pAddrDecWin->enable = MV_TRUE; ++ } ++ else ++ { ++ pAddrDecWin->enable = MV_FALSE; ++ } ++ ++ return MV_OK; ++} ++/******************************************************************************* ++* mvDramIfWinEnable - Enable/Disable SDRAM address decode window ++* ++* DESCRIPTION: ++* This function enable/Disable SDRAM address decode window. ++* ++* INPUT: ++* target - System target. Use only SDRAM targets. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_ERROR in case function parameter are invalid, MV_OK otherewise. ++* ++*******************************************************************************/ ++MV_STATUS mvDramIfWinEnable(MV_TARGET target, MV_BOOL enable) ++{ ++ MV_DRAM_DEC_WIN addrDecWin; ++ ++ /* Check parameters */ ++ if (!MV_TARGET_IS_DRAM(target)) ++ { ++ mvOsPrintf("mvDramIfWinEnable: target %d is Illigal\n", target); ++ return MV_ERROR; ++ } ++ ++ if (enable == MV_TRUE) ++ { /* First check for overlap with other enabled windows */ ++ if (MV_OK != mvDramIfWinGet(target, &addrDecWin)) ++ { ++ mvOsPrintf("mvDramIfWinEnable:ERR. Getting target %d failed.\n", ++ target); ++ return MV_ERROR; ++ } ++ /* Check for overlapping */ ++ if (MV_FALSE == sdramIfWinOverlap(target, &(addrDecWin.addrWin))) ++ { ++ /* No Overlap. Enable address decode winNum window */ ++ MV_REG_BIT_SET(SDRAM_SIZE_REG(0,target), SCSR_WIN_EN); ++ } ++ else ++ { /* Overlap detected */ ++ mvOsPrintf("mvDramIfWinEnable: ERR. Target %d overlap detect\n", ++ target); ++ return MV_ERROR; ++ } ++ } ++ else ++ { /* Disable address decode winNum window */ ++ MV_REG_BIT_RESET(SDRAM_SIZE_REG(0, target), SCSR_WIN_EN); ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* sdramIfWinOverlap - Check if an address window overlap an SDRAM address window ++* ++* DESCRIPTION: ++* This function scan each SDRAM address decode window to test if it ++* overlapps the given address windoow ++* ++* INPUT: ++* target - SDRAM target where the function skips checking. ++* pAddrDecWin - The tested address window for overlapping with ++* SDRAM windows. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the given address window overlaps any enabled address ++* decode map, MV_FALSE otherwise. ++* ++*******************************************************************************/ ++static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin) ++{ ++ MV_TARGET targetNum; ++ MV_DRAM_DEC_WIN addrDecWin; ++ ++ for(targetNum = SDRAM_CS0; targetNum < MV_DRAM_MAX_CS ; targetNum++) ++ { ++ /* don't check our winNum or illegal targets */ ++ if (targetNum == target) ++ { ++ continue; ++ } ++ ++ /* Get window parameters */ ++ if (MV_OK != mvDramIfWinGet(targetNum, &addrDecWin)) ++ { ++ mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); ++ return MV_ERROR; ++ } ++ ++ /* Do not check disabled windows */ ++ if (MV_FALSE == addrDecWin.enable) ++ { ++ continue; ++ } ++ ++ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) ++ { ++ mvOsPrintf( ++ "sdramIfWinOverlap: Required target %d overlap winNum %d\n", ++ target, targetNum); ++ return MV_TRUE; ++ } ++ } ++ ++ return MV_FALSE; ++} ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,80 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __sysDram ++#define __sysDram ++ ++/* This structure describes CPU interface address decode window */ ++typedef struct _mvDramIfDecWin ++{ ++ MV_ADDR_WIN addrWin; /* An address window*/ ++ MV_BOOL enable; /* Address decode window is enabled/disabled */ ++}MV_DRAM_DEC_WIN; ++ ++MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); ++MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); ++MV_STATUS mvDramIfWinEnable(MV_TARGET target, MV_BOOL enable); ++ ++#endif +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,658 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#include "ctrlEnv/sys/mvSysGbe.h" ++ ++ ++ ++typedef struct _mvEthDecWin ++{ ++ MV_TARGET target; ++ MV_ADDR_WIN addrWin; /* An address window*/ ++ MV_BOOL enable; /* Address decode window is enabled/disabled */ ++ ++}MV_ETH_DEC_WIN; ++ ++MV_TARGET ethAddrDecPrioTap[] = ++{ ++#if defined(MV_INCLUDE_SDRAM_CS0) ++ SDRAM_CS0, ++#endif ++#if defined(MV_INCLUDE_SDRAM_CS1) ++ SDRAM_CS1, ++#endif ++#if defined(MV_INCLUDE_SDRAM_CS2) ++ SDRAM_CS2, ++#endif ++#if defined(MV_INCLUDE_SDRAM_CS3) ++ SDRAM_CS3, ++#endif ++#if defined(MV_INCLUDE_DEVICE_CS0) ++ DEVICE_CS0, ++#endif ++#if defined(MV_INCLUDE_DEVICE_CS1) ++ DEVICE_CS1, ++#endif ++#if defined(MV_INCLUDE_DEVICE_CS2) ++ DEVICE_CS2, ++#endif ++#if defined(MV_INCLUDE_DEVICE_CS3) ++ DEVICE_CS3, ++#endif ++#if defined(MV_INCLUDE_PEX) ++ PEX0_IO, ++#endif ++ TBL_TERM ++}; ++ ++static MV_STATUS ethWinOverlapDetect(int port, MV_U32 winNum, MV_ADDR_WIN *pAddrWin); ++static MV_STATUS mvEthWinSet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin); ++static MV_STATUS mvEthWinGet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin); ++ ++ ++/******************************************************************************* ++* mvEthWinInit - Initialize ETH address decode windows ++* ++* DESCRIPTION: ++* This function initialize ETH window decode unit. It set the ++* default address decode windows of the unit. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_ERROR if setting fail. ++*******************************************************************************/ ++/* Configure EthDrv memory map registes. */ ++MV_STATUS mvEthWinInit (int port) ++{ ++ MV_U32 winNum, status, winPrioIndex=0, i, regVal=0; ++ MV_ETH_DEC_WIN ethWin; ++ MV_CPU_DEC_WIN cpuAddrDecWin; ++ static MV_U32 accessProtReg = 0; ++ ++#if (MV_ETH_VERSION <= 1) ++ static MV_BOOL isFirst = MV_TRUE; ++ ++ if(isFirst == MV_FALSE) ++ { ++ MV_REG_WRITE(ETH_ACCESS_PROTECT_REG(port), accessProtReg); ++ return MV_OK; ++ } ++ isFirst = MV_FALSE; ++#endif /* MV_GIGA_ETH_VERSION */ ++ ++ /* Initiate Ethernet address decode */ ++ ++ /* First disable all address decode windows */ ++ for(winNum=0; winNum= ETH_MAX_DECODE_WIN) ++ { ++ mvOsPrintf("mvEthWinSet: ERR. Invalid win num %d\n",winNum); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check if the requested window overlapps with current windows */ ++ if (MV_TRUE == ethWinOverlapDetect(port, winNum, &pAddrDecWin->addrWin)) ++ { ++ mvOsPrintf("mvEthWinSet: ERR. Window %d overlap\n", winNum); ++ return MV_ERROR; ++ } ++ ++ /* check if address is aligned to the size */ ++ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) ++ { ++ mvOsPrintf("mvEthWinSet: Error setting Ethernet window %d to "\ ++ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", ++ winNum, ++ mvCtrlTargetNameGet(pAddrDecWin->target), ++ pAddrDecWin->addrWin.baseLow, ++ pAddrDecWin->addrWin.size); ++ return MV_ERROR; ++ } ++ ++ ++ decRegs.baseReg = MV_REG_READ(ETH_WIN_BASE_REG(port, winNum)); ++ decRegs.sizeReg = MV_REG_READ(ETH_WIN_SIZE_REG(port, winNum)); ++ ++ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) ++ { ++ mvOsPrintf("mvEthWinSet:mvCtrlAddrDecToReg Failed\n"); ++ return MV_ERROR; ++ } ++ ++ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); ++ ++ /* set attributes */ ++ decRegs.baseReg &= ~ETH_WIN_ATTR_MASK; ++ decRegs.baseReg |= targetAttribs.attrib << ETH_WIN_ATTR_OFFS; ++ /* set target ID */ ++ decRegs.baseReg &= ~ETH_WIN_TARGET_MASK; ++ decRegs.baseReg |= targetAttribs.targetId << ETH_WIN_TARGET_OFFS; ++ ++ /* for the safe side we disable the window before writing the new ++ values */ ++ mvEthWinEnable(port, winNum, MV_FALSE); ++ MV_REG_WRITE(ETH_WIN_BASE_REG(port, winNum), decRegs.baseReg); ++ ++ /* Write to address decode Size Register */ ++ MV_REG_WRITE(ETH_WIN_SIZE_REG(port, winNum), decRegs.sizeReg); ++ ++ /* Enable address decode target window */ ++ if (pAddrDecWin->enable == MV_TRUE) ++ { ++ mvEthWinEnable(port, winNum, MV_TRUE); ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvETHWinGet - Get dma peripheral target address window. ++* ++* DESCRIPTION: ++* Get ETH peripheral target address window. ++* ++* INPUT: ++* winNum - ETH to target address decode window number. ++* ++* OUTPUT: ++* pAddrDecWin - ETH target window data structure. ++* ++* RETURN: ++* MV_ERROR if register parameters are invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvEthWinGet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin) ++{ ++ MV_DEC_REGS decRegs; ++ MV_TARGET_ATTRIB targetAttrib; ++ ++ /* Parameter checking */ ++ if (winNum >= ETH_MAX_DECODE_WIN) ++ { ++ mvOsPrintf("mvEthWinGet: ERR. Invalid winNum %d\n", winNum); ++ return MV_NOT_SUPPORTED; ++ } ++ ++ decRegs.baseReg = MV_REG_READ(ETH_WIN_BASE_REG(port, winNum)); ++ decRegs.sizeReg = MV_REG_READ(ETH_WIN_SIZE_REG(port, winNum)); ++ ++ if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) ++ { ++ mvOsPrintf("mvAhbToMbusWinGet: mvCtrlRegToAddrDec Failed \n"); ++ return MV_ERROR; ++ } ++ ++ /* attrib and targetId */ ++ targetAttrib.attrib = ++ (decRegs.baseReg & ETH_WIN_ATTR_MASK) >> ETH_WIN_ATTR_OFFS; ++ targetAttrib.targetId = ++ (decRegs.baseReg & ETH_WIN_TARGET_MASK) >> ETH_WIN_TARGET_OFFS; ++ ++ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); ++ ++ /* Check if window is enabled */ ++ if (~(MV_REG_READ(ETH_BASE_ADDR_ENABLE_REG(port))) & (1 << winNum) ) ++ { ++ pAddrDecWin->enable = MV_TRUE; ++ } ++ else ++ { ++ pAddrDecWin->enable = MV_FALSE; ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvEthWinEnable - Enable/disable a ETH to target address window ++* ++* DESCRIPTION: ++* This function enable/disable a ETH to target address window. ++* According to parameter 'enable' the routine will enable the ++* window, thus enabling ETH accesses (before enabling the window it is ++* tested for overlapping). Otherwise, the window will be disabled. ++* ++* INPUT: ++* winNum - ETH to target address decode window number. ++* enable - Enable/disable parameter. ++* ++* OUTPUT: ++* N/A ++* ++* RETURN: ++* MV_ERROR if decode window number was wrong or enabled window overlapps. ++* ++*******************************************************************************/ ++MV_STATUS mvEthWinEnable(int port, MV_U32 winNum,MV_BOOL enable) ++{ ++ MV_ETH_DEC_WIN addrDecWin; ++ ++ /* Parameter checking */ ++ if (winNum >= ETH_MAX_DECODE_WIN) ++ { ++ mvOsPrintf("mvEthTargetWinEnable:ERR. Invalid winNum%d\n",winNum); ++ return MV_ERROR; ++ } ++ ++ if (enable == MV_TRUE) ++ { /* First check for overlap with other enabled windows */ ++ /* Get current window */ ++ if (MV_OK != mvEthWinGet(port, winNum, &addrDecWin)) ++ { ++ mvOsPrintf("mvEthTargetWinEnable:ERR. targetWinGet fail\n"); ++ return MV_ERROR; ++ } ++ /* Check for overlapping */ ++ if (MV_FALSE == ethWinOverlapDetect(port, winNum, &(addrDecWin.addrWin))) ++ { ++ /* No Overlap. Enable address decode target window */ ++ MV_REG_BIT_RESET(ETH_BASE_ADDR_ENABLE_REG(port), (1 << winNum)); ++ } ++ else ++ { /* Overlap detected */ ++ mvOsPrintf("mvEthTargetWinEnable:ERR. Overlap detected\n"); ++ return MV_ERROR; ++ } ++ } ++ else ++ { /* Disable address decode target window */ ++ MV_REG_BIT_SET(ETH_BASE_ADDR_ENABLE_REG(port), (1 << winNum)); ++ } ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvEthWinTargetGet - Get Window number associated with target ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++* window number ++* ++*******************************************************************************/ ++MV_U32 mvEthWinTargetGet(int port, MV_TARGET target) ++{ ++ MV_ETH_DEC_WIN decWin; ++ MV_U32 winNum; ++ ++ /* Check parameters */ ++ if (target >= MAX_TARGETS) ++ { ++ mvOsPrintf("mvAhbToMbusWinTargetGet: target %d is Illigal\n", target); ++ return 0xffffffff; ++ } ++ ++ for (winNum=0; winNum= mvCtrlEthMaxPortGet()) ++ { ++ mvOsPrintf("mvEthProtWinSet:ERR. Invalid port number %d\n", portNo); ++ return MV_ERROR; ++ } ++ ++ if (winNum >= ETH_MAX_DECODE_WIN) ++ { ++ mvOsPrintf("mvEthProtWinSet:ERR. Invalid winNum%d\n",winNum); ++ return MV_ERROR; ++ } ++ ++ if((access == ACC_RESERVED) || (access >= MAX_ACC_RIGHTS)) ++ { ++ mvOsPrintf("mvEthProtWinSet:ERR. Inv access param %d\n", access); ++ return MV_ERROR; ++ } ++ /* Read current protection register */ ++ protReg = MV_REG_READ(ETH_ACCESS_PROTECT_REG(portNo)); ++ ++ /* Clear protection window field */ ++ protReg &= ~(ETH_PROT_WIN_MASK(winNum)); ++ ++ /* Set new protection field value */ ++ protReg |= (access << (ETH_PROT_WIN_OFFS(winNum))); ++ ++ /* Write protection register back */ ++ MV_REG_WRITE(ETH_ACCESS_PROTECT_REG(portNo), protReg); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* ethWinOverlapDetect - Detect ETH address windows overlapping ++* ++* DESCRIPTION: ++* An unpredicted behaviur is expected in case ETH address decode ++* windows overlapps. ++* This function detects ETH address decode windows overlapping of a ++* specified window. The function does not check the window itself for ++* overlapping. The function also skipps disabled address decode windows. ++* ++* INPUT: ++* winNum - address decode window number. ++* pAddrDecWin - An address decode window struct. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the given address window overlap current address ++* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data ++* from registers. ++* ++*******************************************************************************/ ++static MV_STATUS ethWinOverlapDetect(int port, MV_U32 winNum, MV_ADDR_WIN *pAddrWin) ++{ ++ MV_U32 baseAddrEnableReg; ++ MV_U32 winNumIndex; ++ MV_ETH_DEC_WIN addrDecWin; ++ ++ /* Read base address enable register. Do not check disabled windows */ ++ baseAddrEnableReg = MV_REG_READ(ETH_BASE_ADDR_ENABLE_REG(port)); ++ ++ for (winNumIndex=0; winNumIndex= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexInit: ERR. Invalid PEX interface %d\n", pexIf); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Enabled CPU access to PCI-Express */ ++ mvCpuIfEnablePex(pexIf, pexType); ++ ++ /* Start with bars */ ++ /* First disable all PEX bars*/ ++ for (bar = 0; bar < PEX_MAX_BARS; bar++) ++ { ++ if (PEX_INTER_REGS_BAR != bar) ++ { ++ if (MV_OK != mvPexBarEnable(pexIf, bar, MV_FALSE)) ++ { ++ mvOsPrintf("mvPexInit:mvPexBarEnable bar =%d failed \n",bar); ++ return MV_ERROR; ++ } ++ ++ } ++ ++ } ++ ++ /* and disable all PEX target windows */ ++ for (winNum = 0; winNum < PEX_MAX_TARGET_WIN - 2; winNum++) ++ { ++ if (MV_OK != mvPexTargetWinEnable(pexIf, winNum, MV_FALSE)) ++ { ++ mvOsPrintf("mvPexInit:mvPexTargetWinEnable winNum =%d failed \n", ++ winNum); ++ return MV_ERROR; ++ ++ } ++ } ++ ++ /* Now, go through all bars*/ ++ ++ ++ ++/******************************************************************************/ ++/* Internal registers bar */ ++/******************************************************************************/ ++ bar = PEX_INTER_REGS_BAR; ++ ++ /* we only open the bar , no need to open windows for this bar */ ++ ++ /* first get the CS attribute from the CPU Interface */ ++ if (MV_OK !=mvCpuIfTargetWinGet(INTER_REGS,&addrDecWin)) ++ { ++ mvOsPrintf("mvPexInit: ERR. mvCpuIfTargetWinGet failed target =%d\n",INTER_REGS); ++ return MV_ERROR; ++ } ++ ++ pexBar.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; ++ pexBar.addrWin.baseLow = addrDecWin.addrWin.baseLow; ++ pexBar.addrWin.size = addrDecWin.addrWin.size; ++ pexBar.enable = MV_TRUE; ++ ++ if (MV_OK != mvPexBarSet(pexIf, bar, &pexBar)) ++ { ++ mvOsPrintf("mvPexInit: ERR. mvPexBarSet %d failed\n", bar); ++ return MV_ERROR; ++ } ++ ++/******************************************************************************/ ++/* DRAM bar */ ++/******************************************************************************/ ++ ++ bar = PEX_DRAM_BAR; ++ ++ pexBar.addrWin.size = 0; ++ ++ for (target = SDRAM_CS0;target < MV_DRAM_MAX_CS; target++ ) ++ { ++ ++ status = mvCpuIfTargetWinGet(target,&addrDecWin); ++ ++ if((MV_NO_SUCH == status)&&(target != SDRAM_CS0)) ++ { ++ continue; ++ } ++ ++ /* first get attributes from CPU If */ ++ if (MV_OK != status) ++ { ++ mvOsPrintf("mvPexInit: ERR. mvCpuIfTargetWinGet failed target =%d\n",target); ++ return MV_ERROR; ++ } ++ if (addrDecWin.enable == MV_TRUE) ++ { ++ /* the base is the base of DRAM CS0 always */ ++ if (SDRAM_CS0 == target ) ++ { ++ pexBar.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; ++ pexBar.addrWin.baseLow = addrDecWin.addrWin.baseLow; ++ ++ } ++ ++ /* increment the bar size to be the sum of the size of all ++ DRAM chips selecs */ ++ pexBar.addrWin.size += addrDecWin.addrWin.size; ++ ++ /* set a Pex window for this target ! ++ DRAM CS always will have a Pex Window , and is not a ++ part of the priority table */ ++ pexWin.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; ++ pexWin.addrWin.baseLow = addrDecWin.addrWin.baseLow; ++ pexWin.addrWin.size = addrDecWin.addrWin.size; ++ ++ /* we disable the windows at first because we are not ++ sure that it is witihin bar boundries */ ++ pexWin.enable =MV_FALSE; ++ pexWin.target = target; ++ pexWin.targetBar = bar; ++ ++ if (MV_OK != mvPexTargetWinSet(pexIf,pexCurrWin++,&pexWin)) ++ { ++ mvOsPrintf("mvPexInit: ERR. mvPexTargetWinSet failed\n"); ++ return MV_ERROR; ++ } ++ } ++ } ++ ++ /* check if the size of the bar is illeggal */ ++ if (-1 == ctrlSizeToReg(pexBar.addrWin.size, PXBCR_BAR_SIZE_ALIGNMENT)) ++ { ++ /* try to get a good size */ ++ pexBar.addrWin.size = ctrlSizeRegRoundUp(pexBar.addrWin.size, ++ PXBCR_BAR_SIZE_ALIGNMENT); ++ } ++ ++ /* check if the size and base are valid */ ++ if (MV_TRUE == pexBarOverlapDetect(pexIf,bar,&pexBar.addrWin)) ++ { ++ mvOsPrintf("mvPexInit:Warning :Bar %d size is illigal\n",bar); ++ mvOsPrintf("it will be disabled\n"); ++ mvOsPrintf("please check Pex and CPU windows configuration\n"); ++ } ++ else ++ { ++ pexBar.enable = MV_TRUE; ++ ++ /* configure the bar */ ++ if (MV_OK != mvPexBarSet(pexIf, bar, &pexBar)) ++ { ++ mvOsPrintf("mvPexInit: ERR. mvPexBarSet %d failed\n", bar); ++ return MV_ERROR; ++ } ++ ++ /* after the bar was configured then we enable the Pex windows*/ ++ for (winNum = 0;winNum < pexCurrWin ;winNum++) ++ { ++ if (MV_OK != mvPexTargetWinEnable(pexIf, winNum, MV_TRUE)) ++ { ++ mvOsPrintf("mvPexInit: Can't enable window =%d\n",winNum); ++ return MV_ERROR; ++ } ++ ++ } ++ } ++ ++/******************************************************************************/ ++/* DEVICE bar */ ++/******************************************************************************/ ++ ++/* Open the Device BAR for non linux only */ ++#ifndef MV_DISABLE_PEX_DEVICE_BAR ++ ++ /* then device bar*/ ++ bar = PEX_DEVICE_BAR; ++ ++ /* save the starting window */ ++ pexStartWindow = pexCurrWin; ++ pexBar.addrWin.size = 0; ++ pexBar.addrWin.baseLow = 0xffffffff; ++ pexBar.addrWin.baseHigh = 0; ++ maxBase = 0; ++ ++ for (target = DEV_TO_TARGET(START_DEV_CS);target < DEV_TO_TARGET(MV_DEV_MAX_CS); target++ ) ++ { ++ status = mvCpuIfTargetWinGet(target,&addrDecWin); ++ ++ if (MV_NO_SUCH == status) ++ { ++ continue; ++ } ++ ++ if (MV_OK != status) ++ { ++ mvOsPrintf("mvPexInit: ERR. mvCpuIfTargetWinGet failed target =%d\n",target); ++ return MV_ERROR; ++ } ++ ++ if (addrDecWin.enable == MV_TRUE) ++ { ++ /* get the minimum base */ ++ if (addrDecWin.addrWin.baseLow < pexBar.addrWin.baseLow) ++ { ++ pexBar.addrWin.baseLow = addrDecWin.addrWin.baseLow; ++ } ++ ++ /* get the maximum base */ ++ if (addrDecWin.addrWin.baseLow > maxBase) ++ { ++ maxBase = addrDecWin.addrWin.baseLow; ++ sizeOfMaxBase = addrDecWin.addrWin.size; ++ } ++ ++ /* search in the priority table for this target */ ++ for (winIndex = 0; pexDevBarPrioTable[winIndex] != TBL_TERM; ++ winIndex++) ++ { ++ if (pexDevBarPrioTable[winIndex] != target) ++ { ++ continue; ++ } ++ else if (pexDevBarPrioTable[winIndex] == target) ++ { ++ /*found it */ ++ ++ /* if the index of this target in the prio table is valid ++ then we set the Pex window for this target, a valid index is ++ an index that is lower than the number of the windows that ++ was not configured yet */ ++ ++ /* we subtract 2 always because the default and expantion ++ rom windows are always configured */ ++ if ( pexCurrWin < PEX_MAX_TARGET_WIN - 2) ++ { ++ /* set a Pex window for this target ! */ ++ pexWin.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; ++ pexWin.addrWin.baseLow = addrDecWin.addrWin.baseLow; ++ pexWin.addrWin.size = addrDecWin.addrWin.size; ++ ++ /* we disable the windows at first because we are not ++ sure that it is witihin bar boundries */ ++ pexWin.enable = MV_FALSE; ++ pexWin.target = target; ++ pexWin.targetBar = bar; ++ ++ if (MV_OK != mvPexTargetWinSet(pexIf,pexCurrWin++, ++ &pexWin)) ++ { ++ mvOsPrintf("mvPexInit: ERR. Window Set failed\n"); ++ return MV_ERROR; ++ } ++ } ++ } ++ } ++ } ++ } ++ ++ pexBar.addrWin.size = maxBase - pexBar.addrWin.baseLow + sizeOfMaxBase; ++ pexBar.enable = MV_TRUE; ++ ++ /* check if the size of the bar is illegal */ ++ if (-1 == ctrlSizeToReg(pexBar.addrWin.size, PXBCR_BAR_SIZE_ALIGNMENT)) ++ { ++ /* try to get a good size */ ++ pexBar.addrWin.size = ctrlSizeRegRoundUp(pexBar.addrWin.size, ++ PXBCR_BAR_SIZE_ALIGNMENT); ++ } ++ ++ /* check if the size and base are valid */ ++ if (MV_TRUE == pexBarOverlapDetect(pexIf,bar,&pexBar.addrWin)) ++ { ++ mvOsPrintf("mvPexInit:Warning :Bar %d size is illigal\n",bar); ++ mvOsPrintf("it will be disabled\n"); ++ mvOsPrintf("please check Pex and CPU windows configuration\n"); ++ } ++ else ++ { ++ if (MV_OK != mvPexBarSet(pexIf, bar, &pexBar)) ++ { ++ mvOsPrintf("mvPexInit: ERR. mvPexBarSet %d failed\n", bar); ++ return MV_ERROR; ++ } ++ ++ /* now enable the windows */ ++ for (winNum = pexStartWindow; winNum < pexCurrWin ; winNum++) ++ { ++ if (MV_OK != mvPexTargetWinEnable(pexIf, winNum, MV_TRUE)) ++ { ++ mvOsPrintf("mvPexInit:mvPexTargetWinEnable winNum =%d failed \n", ++ winNum); ++ return MV_ERROR; ++ } ++ } ++ } ++ ++#endif ++ ++ return mvPexHalInit(pexIf, pexType); ++ ++} ++ ++/******************************************************************************* ++* mvPexTargetWinSet - Set PEX to peripheral target address window BAR ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* N/A ++* ++* RETURN: ++* MV_OK if PEX BAR target window was set correctly, ++* MV_BAD_PARAM on bad params ++* MV_ERROR otherwise ++* (e.g. address window overlapps with other active PEX target window). ++* ++*******************************************************************************/ ++MV_STATUS mvPexTargetWinSet(MV_U32 pexIf, MV_U32 winNum, ++ MV_PEX_DEC_WIN *pAddrDecWin) ++{ ++ ++ MV_DEC_REGS decRegs; ++ PEX_WIN_REG_INFO winRegInfo; ++ MV_TARGET_ATTRIB targetAttribs; ++ ++ /* Parameter checking */ ++ if(pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexTargetWinSet: ERR. Invalid PEX interface %d\n", pexIf); ++ return MV_BAD_PARAM; ++ } ++ ++ if (winNum >= PEX_MAX_TARGET_WIN) ++ { ++ mvOsPrintf("mvPexTargetWinSet: ERR. Invalid PEX winNum %d\n", winNum); ++ return MV_BAD_PARAM; ++ ++ } ++ ++ /* get the pex Window registers offsets */ ++ pexWinRegInfoGet(pexIf,winNum,&winRegInfo); ++ ++ ++ if (MV_TRUE == pAddrDecWin->enable) ++ { ++ ++ /* 2) Check if the requested window overlaps with current windows */ ++ if (MV_TRUE == pexWinOverlapDetect(pexIf,winNum, &pAddrDecWin->addrWin)) ++ { ++ mvOsPrintf("mvPexTargetWinSet: ERR. Target %d overlap\n", winNum); ++ return MV_BAD_PARAM; ++ } ++ ++ /* 2) Check if the requested window overlaps with current windows */ ++ if (MV_FALSE == pexIsWinWithinBar(pexIf,&pAddrDecWin->addrWin)) ++ { ++ mvOsPrintf("mvPexTargetWinSet: Win %d should be in bar boundries\n", ++ winNum); ++ return MV_BAD_PARAM; ++ } ++ ++ } ++ ++ ++ ++ /* read base register*/ ++ ++ if (winRegInfo.baseLowRegOffs) ++ { ++ decRegs.baseReg = MV_REG_READ(winRegInfo.baseLowRegOffs); ++ } ++ else ++ { ++ decRegs.baseReg = 0; ++ } ++ ++ if (winRegInfo.sizeRegOffs) ++ { ++ decRegs.sizeReg = MV_REG_READ(winRegInfo.sizeRegOffs); ++ } ++ else ++ { ++ decRegs.sizeReg =0; ++ } ++ ++ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) ++ { ++ mvOsPrintf("mvPexTargetWinSet:mvCtrlAddrDecToReg Failed\n"); ++ return MV_ERROR; ++ } ++ ++ /* enable\Disable */ ++ if (MV_TRUE == pAddrDecWin->enable) ++ { ++ decRegs.sizeReg |= PXWCR_WIN_EN; ++ } ++ else ++ { ++ decRegs.sizeReg &= ~PXWCR_WIN_EN; ++ } ++ ++ ++ /* clear bit location */ ++ decRegs.sizeReg &= ~PXWCR_WIN_BAR_MAP_MASK; ++ ++ /* set bar Mapping */ ++ if (pAddrDecWin->targetBar == 1) ++ { ++ decRegs.sizeReg |= PXWCR_WIN_BAR_MAP_BAR1; ++ } ++ else if (pAddrDecWin->targetBar == 2) ++ { ++ decRegs.sizeReg |= PXWCR_WIN_BAR_MAP_BAR2; ++ } ++ ++ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); ++ ++ /* set attributes */ ++ decRegs.sizeReg &= ~PXWCR_ATTRIB_MASK; ++ decRegs.sizeReg |= targetAttribs.attrib << PXWCR_ATTRIB_OFFS; ++ /* set target ID */ ++ decRegs.sizeReg &= ~PXWCR_TARGET_MASK; ++ decRegs.sizeReg |= targetAttribs.targetId << PXWCR_TARGET_OFFS; ++ ++ ++ /* 3) Write to address decode Base Address Register */ ++ ++ if (winRegInfo.baseLowRegOffs) ++ { ++ MV_REG_WRITE(winRegInfo.baseLowRegOffs, decRegs.baseReg); ++ } ++ ++ /* write size reg */ ++ if (winRegInfo.sizeRegOffs) ++ { ++ if ((MV_PEX_WIN_DEFAULT == winNum)|| ++ (MV_PEX_WIN_EXP_ROM == winNum)) ++ { ++ /* clear size because there is no size field*/ ++ decRegs.sizeReg &= ~PXWCR_SIZE_MASK; ++ ++ /* clear enable because there is no enable field*/ ++ decRegs.sizeReg &= ~PXWCR_WIN_EN; ++ ++ } ++ ++ MV_REG_WRITE(winRegInfo.sizeRegOffs, decRegs.sizeReg); ++ } ++ ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvPexTargetWinGet - Get PEX to peripheral target address window ++* ++* DESCRIPTION: ++* Get the PEX to peripheral target address window BAR. ++* ++* INPUT: ++* pexIf - PEX interface number. ++* bar - BAR to be accessed by slave. ++* ++* OUTPUT: ++* pAddrBarWin - PEX target window information data structure. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPexTargetWinGet(MV_U32 pexIf, MV_U32 winNum, ++ MV_PEX_DEC_WIN *pAddrDecWin) ++{ ++ MV_TARGET_ATTRIB targetAttrib; ++ MV_DEC_REGS decRegs; ++ ++ PEX_WIN_REG_INFO winRegInfo; ++ ++ /* Parameter checking */ ++ if(pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexTargetWinGet: ERR. Invalid PEX interface %d\n", pexIf); ++ return MV_BAD_PARAM; ++ } ++ ++ if (winNum >= PEX_MAX_TARGET_WIN) ++ { ++ mvOsPrintf("mvPexTargetWinGet: ERR. Invalid PEX winNum %d\n", winNum); ++ return MV_BAD_PARAM; ++ ++ } ++ ++ /* get the pex Window registers offsets */ ++ pexWinRegInfoGet(pexIf,winNum,&winRegInfo); ++ ++ /* read base register*/ ++ if (winRegInfo.baseLowRegOffs) ++ { ++ decRegs.baseReg = MV_REG_READ(winRegInfo.baseLowRegOffs); ++ } ++ else ++ { ++ decRegs.baseReg = 0; ++ } ++ ++ /* read size reg */ ++ if (winRegInfo.sizeRegOffs) ++ { ++ decRegs.sizeReg = MV_REG_READ(winRegInfo.sizeRegOffs); ++ } ++ else ++ { ++ decRegs.sizeReg =0; ++ } ++ ++ if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) ++ { ++ mvOsPrintf("mvPexTargetWinGet: mvCtrlRegToAddrDec Failed \n"); ++ return MV_ERROR; ++ ++ } ++ ++ if (decRegs.sizeReg & PXWCR_WIN_EN) ++ { ++ pAddrDecWin->enable = MV_TRUE; ++ } ++ else ++ { ++ pAddrDecWin->enable = MV_FALSE; ++ ++ } ++ ++ ++ #if 0 ++ if (-1 == pAddrDecWin->addrWin.size) ++ { ++ return MV_ERROR; ++ } ++ #endif ++ ++ ++ /* get target bar */ ++ if ((decRegs.sizeReg & PXWCR_WIN_BAR_MAP_MASK) == PXWCR_WIN_BAR_MAP_BAR1 ) ++ { ++ pAddrDecWin->targetBar = 1; ++ } ++ else if ((decRegs.sizeReg & PXWCR_WIN_BAR_MAP_MASK) == ++ PXWCR_WIN_BAR_MAP_BAR2 ) ++ { ++ pAddrDecWin->targetBar = 2; ++ } ++ ++ /* attrib and targetId */ ++ pAddrDecWin->attrib = (decRegs.sizeReg & PXWCR_ATTRIB_MASK) >> ++ PXWCR_ATTRIB_OFFS; ++ pAddrDecWin->targetId = (decRegs.sizeReg & PXWCR_TARGET_MASK) >> ++ PXWCR_TARGET_OFFS; ++ ++ targetAttrib.attrib = pAddrDecWin->attrib; ++ targetAttrib.targetId = pAddrDecWin->targetId; ++ ++ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); ++ ++ return MV_OK; ++ ++} ++ ++ ++/******************************************************************************* ++* mvPexTargetWinEnable - Enable/disable a PEX BAR window ++* ++* DESCRIPTION: ++* This function enable/disable a PEX BAR window. ++* if parameter 'enable' == MV_TRUE the routine will enable the ++* window, thus enabling PEX accesses for that BAR (before enabling the ++* window it is tested for overlapping). Otherwise, the window will ++* be disabled. ++* ++* INPUT: ++* pexIf - PEX interface number. ++* bar - BAR to be accessed by slave. ++* enable - Enable/disable parameter. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPexTargetWinEnable(MV_U32 pexIf,MV_U32 winNum, MV_BOOL enable) ++{ ++ PEX_WIN_REG_INFO winRegInfo; ++ MV_PEX_DEC_WIN addrDecWin; ++ ++ /* Parameter checking */ ++ if(pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexTargetWinEnable: ERR. Invalid PEX If %d\n", pexIf); ++ return MV_BAD_PARAM; ++ } ++ ++ if (winNum >= PEX_MAX_TARGET_WIN) ++ { ++ mvOsPrintf("mvPexTargetWinEnable ERR. Invalid PEX winNum %d\n", winNum); ++ return MV_BAD_PARAM; ++ ++ } ++ ++ ++ /* get the pex Window registers offsets */ ++ pexWinRegInfoGet(pexIf,winNum,&winRegInfo); ++ ++ ++ /* if the address windows is disabled , we only disable the appropriare ++ pex window and ignore other settings */ ++ ++ if (MV_FALSE == enable) ++ { ++ ++ /* this is not relevant to default and expantion rom ++ windows */ ++ if (winRegInfo.sizeRegOffs) ++ { ++ if ((MV_PEX_WIN_DEFAULT != winNum)&& ++ (MV_PEX_WIN_EXP_ROM != winNum)) ++ { ++ MV_REG_BIT_RESET(winRegInfo.sizeRegOffs, PXWCR_WIN_EN); ++ } ++ } ++ ++ } ++ else ++ { ++ if (MV_OK != mvPexTargetWinGet(pexIf,winNum, &addrDecWin)) ++ { ++ mvOsPrintf("mvPexTargetWinEnable: mvPexTargetWinGet Failed\n"); ++ return MV_ERROR; ++ } ++ ++ /* Check if the requested window overlaps with current windows */ ++ if (MV_TRUE == pexWinOverlapDetect(pexIf,winNum, &addrDecWin.addrWin)) ++ { ++ mvOsPrintf("mvPexTargetWinEnable: ERR. Target %d overlap\n", winNum); ++ return MV_BAD_PARAM; ++ } ++ ++ if (MV_FALSE == pexIsWinWithinBar(pexIf,&addrDecWin.addrWin)) ++ { ++ mvOsPrintf("mvPexTargetWinEnable: Win %d should be in bar boundries\n", ++ winNum); ++ return MV_BAD_PARAM; ++ } ++ ++ ++ /* this is not relevant to default and expantion rom ++ windows */ ++ if (winRegInfo.sizeRegOffs) ++ { ++ if ((MV_PEX_WIN_DEFAULT != winNum)&& ++ (MV_PEX_WIN_EXP_ROM != winNum)) ++ { ++ MV_REG_BIT_SET(winRegInfo.sizeRegOffs, PXWCR_WIN_EN); ++ } ++ } ++ ++ ++ } ++ ++ return MV_OK; ++ ++} ++ ++ ++ ++/******************************************************************************* ++* mvPexTargetWinRemap - Set PEX to target address window remap. ++* ++* DESCRIPTION: ++* The PEX interface supports remap of the BAR original address window. ++* For each BAR it is possible to define a remap address. For example ++* an address 0x12345678 that hits BAR 0x10 (SDRAM CS[0]) will be modified ++* according to remap register but will also be targeted to the ++* SDRAM CS[0]. ++* ++* INPUT: ++* pexIf - PEX interface number. ++* bar - Peripheral target enumerator accessed by slave. ++* pAddrWin - Address window to be checked. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPexTargetWinRemap(MV_U32 pexIf, MV_U32 winNum, ++ MV_PEX_REMAP_WIN *pAddrWin) ++{ ++ ++ PEX_WIN_REG_INFO winRegInfo; ++ ++ /* Parameter checking */ ++ if (pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX interface num %d\n", ++ pexIf); ++ return MV_BAD_PARAM; ++ } ++ if (MV_PEX_WIN_DEFAULT == winNum) ++ { ++ mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX win num %d\n", ++ winNum); ++ return MV_BAD_PARAM; ++ ++ } ++ ++ if (MV_IS_NOT_ALIGN(pAddrWin->addrWin.baseLow, PXWRR_REMAP_ALIGNMENT)) ++ { ++ mvOsPrintf("mvPexTargetWinRemap: Error remap PEX interface %d win %d."\ ++ "\nAddress 0x%08x is unaligned to size 0x%x.\n", ++ pexIf, ++ winNum, ++ pAddrWin->addrWin.baseLow, ++ pAddrWin->addrWin.size); ++ ++ return MV_ERROR; ++ } ++ ++ pexWinRegInfoGet(pexIf, winNum, &winRegInfo); ++ ++ /* Set remap low register value */ ++ MV_REG_WRITE(winRegInfo.remapLowRegOffs, pAddrWin->addrWin.baseLow); ++ ++ /* Skip base high settings if the BAR has only base low (32-bit) */ ++ if (0 != winRegInfo.remapHighRegOffs) ++ { ++ MV_REG_WRITE(winRegInfo.remapHighRegOffs, pAddrWin->addrWin.baseHigh); ++ } ++ ++ ++ if (pAddrWin->enable == MV_TRUE) ++ { ++ MV_REG_BIT_SET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); ++ } ++ else ++ { ++ MV_REG_BIT_RESET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvPexTargetWinRemapEnable - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++ ++MV_STATUS mvPexTargetWinRemapEnable(MV_U32 pexIf, MV_U32 winNum, ++ MV_BOOL enable) ++{ ++ PEX_WIN_REG_INFO winRegInfo; ++ ++ /* Parameter checking */ ++ if (pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX interface num %d\n", ++ pexIf); ++ return MV_BAD_PARAM; ++ } ++ if (MV_PEX_WIN_DEFAULT == winNum) ++ { ++ mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX win num %d\n", ++ winNum); ++ return MV_BAD_PARAM; ++ ++ } ++ ++ ++ pexWinRegInfoGet(pexIf, winNum, &winRegInfo); ++ ++ if (enable == MV_TRUE) ++ { ++ MV_REG_BIT_SET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); ++ } ++ else ++ { ++ MV_REG_BIT_RESET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); ++ } ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvPexBarSet - Set PEX bar address and size ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPexBarSet(MV_U32 pexIf, ++ MV_U32 barNum, ++ MV_PEX_BAR *pAddrWin) ++{ ++ MV_U32 regBaseLow; ++ MV_U32 regSize,sizeToReg; ++ ++ ++ /* check parameters */ ++ if(pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexBarSet: ERR. Invalid PEX interface %d\n", pexIf); ++ return MV_BAD_PARAM; ++ } ++ ++ if(barNum >= PEX_MAX_BARS) ++ { ++ mvOsPrintf("mvPexBarSet: ERR. Invalid bar number %d\n", barNum); ++ return MV_BAD_PARAM; ++ } ++ ++ ++ if (pAddrWin->addrWin.size == 0) ++ { ++ mvOsPrintf("mvPexBarSet: Size zero is Illigal\n" ); ++ return MV_BAD_PARAM; ++ } ++ ++ ++ /* Check if the window complies with PEX spec */ ++ if (MV_TRUE != pexBarIsValid(pAddrWin->addrWin.baseLow, ++ pAddrWin->addrWin.size)) ++ { ++ mvOsPrintf("mvPexBarSet: ERR. Target %d window invalid\n", barNum); ++ return MV_BAD_PARAM; ++ } ++ ++ /* 2) Check if the requested bar overlaps with current bars */ ++ if (MV_TRUE == pexBarOverlapDetect(pexIf,barNum, &pAddrWin->addrWin)) ++ { ++ mvOsPrintf("mvPexBarSet: ERR. Target %d overlap\n", barNum); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Get size register value according to window size */ ++ sizeToReg = ctrlSizeToReg(pAddrWin->addrWin.size, PXBCR_BAR_SIZE_ALIGNMENT); ++ ++ /* Read bar size */ ++ if (PEX_INTER_REGS_BAR != barNum) /* internal registers have no size */ ++ { ++ regSize = MV_REG_READ(PEX_BAR_CTRL_REG(pexIf,barNum)); ++ ++ /* Size parameter validity check. */ ++ if (-1 == sizeToReg) ++ { ++ mvOsPrintf("mvPexBarSet: ERR. Target BAR %d size invalid.\n",barNum); ++ return MV_BAD_PARAM; ++ } ++ ++ regSize &= ~PXBCR_BAR_SIZE_MASK; ++ regSize |= (sizeToReg << PXBCR_BAR_SIZE_OFFS) ; ++ ++ MV_REG_WRITE(PEX_BAR_CTRL_REG(pexIf,barNum),regSize); ++ ++ } ++ ++ /* set size */ ++ ++ ++ ++ /* Read base address low */ ++ regBaseLow = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, ++ PEX_MV_BAR_BASE(barNum))); ++ ++ /* clear current base */ ++ if (PEX_INTER_REGS_BAR == barNum) ++ { ++ regBaseLow &= ~PXBIR_BASE_MASK; ++ regBaseLow |= (pAddrWin->addrWin.baseLow & PXBIR_BASE_MASK); ++ } ++ else ++ { ++ regBaseLow &= ~PXBR_BASE_MASK; ++ regBaseLow |= (pAddrWin->addrWin.baseLow & PXBR_BASE_MASK); ++ } ++ ++ /* if we had a previous value that contain the bar type (MeM\IO), we want to ++ restore it */ ++ regBaseLow |= PEX_BAR_DEFAULT_ATTRIB; ++ ++ ++ ++ /* write base low */ ++ MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE(barNum)), ++ regBaseLow); ++ ++ if (pAddrWin->addrWin.baseHigh != 0) ++ { ++ /* Read base address high */ ++ MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE_HIGH(barNum)), ++ pAddrWin->addrWin.baseHigh); ++ ++ } ++ ++ /* lastly enable the Bar */ ++ if (pAddrWin->enable == MV_TRUE) ++ { ++ if (PEX_INTER_REGS_BAR != barNum) /* internal registers ++ are enabled always */ ++ { ++ MV_REG_BIT_SET(PEX_BAR_CTRL_REG(pexIf,barNum),PXBCR_BAR_EN); ++ } ++ } ++ else if (MV_FALSE == pAddrWin->enable) ++ { ++ if (PEX_INTER_REGS_BAR != barNum) /* internal registers ++ are enabled always */ ++ { ++ MV_REG_BIT_RESET(PEX_BAR_CTRL_REG(pexIf,barNum),PXBCR_BAR_EN); ++ } ++ ++ } ++ ++ ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvPexBarGet - Get PEX bar address and size ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++ ++MV_STATUS mvPexBarGet(MV_U32 pexIf, ++ MV_U32 barNum, ++ MV_PEX_BAR *pAddrWin) ++{ ++ /* check parameters */ ++ if(pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexBarGet: ERR. Invalid PEX interface %d\n", pexIf); ++ return MV_BAD_PARAM; ++ } ++ ++ if(barNum >= PEX_MAX_BARS) ++ { ++ mvOsPrintf("mvPexBarGet: ERR. Invalid bar number %d\n", barNum); ++ return MV_BAD_PARAM; ++ } ++ ++ /* read base low */ ++ pAddrWin->addrWin.baseLow = ++ MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE(barNum))); ++ ++ ++ if (PEX_INTER_REGS_BAR == barNum) ++ { ++ pAddrWin->addrWin.baseLow &= PXBIR_BASE_MASK; ++ } ++ else ++ { ++ pAddrWin->addrWin.baseLow &= PXBR_BASE_MASK; ++ } ++ ++ ++ /* read base high */ ++ pAddrWin->addrWin.baseHigh = ++ MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE_HIGH(barNum))); ++ ++ ++ /* Read bar size */ ++ if (PEX_INTER_REGS_BAR != barNum) /* internal registers have no size */ ++ { ++ pAddrWin->addrWin.size = MV_REG_READ(PEX_BAR_CTRL_REG(pexIf,barNum)); ++ ++ /* check if enable or not */ ++ if (pAddrWin->addrWin.size & PXBCR_BAR_EN) ++ { ++ pAddrWin->enable = MV_TRUE; ++ } ++ else ++ { ++ pAddrWin->enable = MV_FALSE; ++ } ++ ++ /* now get the size */ ++ pAddrWin->addrWin.size &= PXBCR_BAR_SIZE_MASK; ++ pAddrWin->addrWin.size >>= PXBCR_BAR_SIZE_OFFS; ++ ++ pAddrWin->addrWin.size = ctrlRegToSize(pAddrWin->addrWin.size, ++ PXBCR_BAR_SIZE_ALIGNMENT); ++ ++ } ++ else /* PEX_INTER_REGS_BAR */ ++ { ++ pAddrWin->addrWin.size = INTER_REGS_SIZE; ++ pAddrWin->enable = MV_TRUE; ++ } ++ ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvPexBarEnable - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++ ++ ++MV_STATUS mvPexBarEnable(MV_U32 pexIf, MV_U32 barNum, MV_BOOL enable) ++{ ++ ++ MV_PEX_BAR pexBar; ++ ++ /* check parameters */ ++ if(pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexBarEnable: ERR. Invalid PEX interface %d\n", pexIf); ++ return MV_BAD_PARAM; ++ } ++ ++ ++ if(barNum >= PEX_MAX_BARS) ++ { ++ mvOsPrintf("mvPexBarEnable: ERR. Invalid bar number %d\n", barNum); ++ return MV_BAD_PARAM; ++ } ++ ++ if (PEX_INTER_REGS_BAR == barNum) ++ { ++ if (MV_TRUE == enable) ++ { ++ return MV_OK; ++ } ++ else ++ { ++ return MV_ERROR; ++ } ++ } ++ ++ ++ if (MV_FALSE == enable) ++ { ++ /* disable bar and quit */ ++ MV_REG_BIT_RESET(PEX_BAR_CTRL_REG(pexIf,barNum),PXBCR_BAR_EN); ++ return MV_OK; ++ } ++ ++ /* else */ ++ ++ if (mvPexBarGet(pexIf,barNum,&pexBar) != MV_OK) ++ { ++ mvOsPrintf("mvPexBarEnable: mvPexBarGet Failed\n"); ++ return MV_ERROR; ++ ++ } ++ ++ if (MV_TRUE == pexBar.enable) ++ { ++ /* it is already enabled !!! */ ++ return MV_OK; ++ } ++ ++ /* else enable the bar*/ ++ ++ pexBar.enable = MV_TRUE; ++ ++ if (mvPexBarSet(pexIf,barNum,&pexBar) != MV_OK) ++ { ++ mvOsPrintf("mvPexBarEnable: mvPexBarSet Failed\n"); ++ return MV_ERROR; ++ ++ } ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* pexWinOverlapDetect - Detect address windows overlapping ++* ++* DESCRIPTION: ++* This function detects address window overlapping of a given address ++* window in PEX BARs. ++* ++* INPUT: ++* pAddrWin - Address window to be checked. ++* bar - BAR to be accessed by slave. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the given address window overlap current address ++* decode map, MV_FALSE otherwise. ++* ++*******************************************************************************/ ++static MV_BOOL pexWinOverlapDetect(MV_U32 pexIf, ++ MV_U32 winNum, ++ MV_ADDR_WIN *pAddrWin) ++{ ++ MV_U32 win; ++ MV_PEX_DEC_WIN addrDecWin; ++ ++ ++ for(win = 0; win < PEX_MAX_TARGET_WIN -2 ; win++) ++ { ++ /* don't check our target or illegal targets */ ++ if (winNum == win) ++ { ++ continue; ++ } ++ ++ /* Get window parameters */ ++ if (MV_OK != mvPexTargetWinGet(pexIf, win, &addrDecWin)) ++ { ++ mvOsPrintf("pexWinOverlapDetect: ERR. TargetWinGet failed win=%x\n", ++ win); ++ return MV_ERROR; ++ } ++ ++ /* Do not check disabled windows */ ++ if (MV_FALSE == addrDecWin.enable) ++ { ++ continue; ++ } ++ ++ ++ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) ++ { ++ mvOsPrintf("pexWinOverlapDetect: winNum %d overlap current %d\n", ++ winNum, win); ++ return MV_TRUE; ++ } ++ } ++ ++ return MV_FALSE; ++} ++ ++/******************************************************************************* ++* pexIsWinWithinBar - Detect if address is within PEX bar boundries ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the given address window overlap current address ++* decode map, MV_FALSE otherwise. ++* ++*******************************************************************************/ ++static MV_BOOL pexIsWinWithinBar(MV_U32 pexIf, ++ MV_ADDR_WIN *pAddrWin) ++{ ++ MV_U32 bar; ++ MV_PEX_BAR addrDecWin; ++ ++ for(bar = 0; bar < PEX_MAX_BARS; bar++) ++ { ++ ++ /* Get window parameters */ ++ if (MV_OK != mvPexBarGet(pexIf, bar, &addrDecWin)) ++ { ++ mvOsPrintf("pexIsWinWithinBar: ERR. mvPexBarGet failed\n"); ++ return MV_ERROR; ++ } ++ ++ /* Do not check disabled bars */ ++ if (MV_FALSE == addrDecWin.enable) ++ { ++ continue; ++ } ++ ++ ++ if(MV_TRUE == ctrlWinWithinWinTest(pAddrWin, &addrDecWin.addrWin)) ++ { ++ return MV_TRUE; ++ } ++ } ++ ++ return MV_FALSE; ++ ++} ++ ++/******************************************************************************* ++* pexBarOverlapDetect - Detect address windows overlapping ++* ++* DESCRIPTION: ++* This function detects address window overlapping of a given address ++* window in PEX BARs. ++* ++* INPUT: ++* pAddrWin - Address window to be checked. ++* bar - BAR to be accessed by slave. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the given address window overlap current address ++* decode map, MV_FALSE otherwise. ++* ++*******************************************************************************/ ++static MV_BOOL pexBarOverlapDetect(MV_U32 pexIf, ++ MV_U32 barNum, ++ MV_ADDR_WIN *pAddrWin) ++{ ++ MV_U32 bar; ++ MV_PEX_BAR barDecWin; ++ ++ ++ for(bar = 0; bar < PEX_MAX_BARS; bar++) ++ { ++ /* don't check our target or illegal targets */ ++ if (barNum == bar) ++ { ++ continue; ++ } ++ ++ /* Get window parameters */ ++ if (MV_OK != mvPexBarGet(pexIf, bar, &barDecWin)) ++ { ++ mvOsPrintf("pexBarOverlapDetect: ERR. TargetWinGet failed\n"); ++ return MV_ERROR; ++ } ++ ++ /* don'nt check disabled bars */ ++ if (barDecWin.enable == MV_FALSE) ++ { ++ continue; ++ } ++ ++ ++ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &barDecWin.addrWin)) ++ { ++ mvOsPrintf("pexBarOverlapDetect: winNum %d overlap current %d\n", ++ barNum, bar); ++ return MV_TRUE; ++ } ++ } ++ ++ return MV_FALSE; ++} ++ ++/******************************************************************************* ++* pexBarIsValid - Check if the given address window is valid ++* ++* DESCRIPTION: ++* PEX spec restrict BAR base to be aligned to BAR size. ++* This function checks if the given address window is valid. ++* ++* INPUT: ++* baseLow - 32bit low base address. ++* size - Window size. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the address window is valid, MV_FALSE otherwise. ++* ++*******************************************************************************/ ++static MV_STATUS pexBarIsValid(MV_U32 baseLow, MV_U32 size) ++{ ++ ++ /* PCI spec restrict BAR base to be aligned to BAR size */ ++ if(MV_IS_NOT_ALIGN(baseLow, size)) ++ { ++ return MV_ERROR; ++ } ++ else ++ { ++ return MV_TRUE; ++ } ++ ++ return MV_TRUE; ++} ++ ++/******************************************************************************* ++* pexBarRegInfoGet - Get BAR register information ++* ++* DESCRIPTION: ++* PEX BARs registers offsets are inconsecutive. ++* This function gets a PEX BAR register information like register offsets ++* and function location of the BAR. ++* ++* INPUT: ++* pexIf - PEX interface number. ++* bar - The PEX BAR in question. ++* ++* OUTPUT: ++* pBarRegInfo - BAR register info struct. ++* ++* RETURN: ++* MV_BAD_PARAM when bad parameters ,MV_ERROR on error ,othewise MV_OK ++* ++*******************************************************************************/ ++static MV_STATUS pexWinRegInfoGet(MV_U32 pexIf, ++ MV_U32 winNum, ++ PEX_WIN_REG_INFO *pWinRegInfo) ++{ ++ ++ if ((winNum >= 0)&&(winNum <=3)) ++ { ++ pWinRegInfo->baseLowRegOffs = PEX_WIN0_3_BASE_REG(pexIf,winNum); ++ pWinRegInfo->baseHighRegOffs = 0; ++ pWinRegInfo->sizeRegOffs = PEX_WIN0_3_CTRL_REG(pexIf,winNum); ++ pWinRegInfo->remapLowRegOffs = PEX_WIN0_3_REMAP_REG(pexIf,winNum); ++ pWinRegInfo->remapHighRegOffs = 0; ++ } ++ else if ((winNum >= 4)&&(winNum <=5)) ++ { ++ pWinRegInfo->baseLowRegOffs = PEX_WIN4_5_BASE_REG(pexIf,winNum); ++ pWinRegInfo->baseHighRegOffs = 0; ++ pWinRegInfo->sizeRegOffs = PEX_WIN4_5_CTRL_REG(pexIf,winNum); ++ pWinRegInfo->remapLowRegOffs = PEX_WIN4_5_REMAP_REG(pexIf,winNum); ++ pWinRegInfo->remapHighRegOffs = PEX_WIN4_5_REMAP_HIGH_REG(pexIf,winNum); ++ ++ } ++ else if (MV_PEX_WIN_DEFAULT == winNum) ++ { ++ pWinRegInfo->baseLowRegOffs = 0; ++ pWinRegInfo->baseHighRegOffs = 0; ++ pWinRegInfo->sizeRegOffs = PEX_WIN_DEFAULT_CTRL_REG(pexIf); ++ pWinRegInfo->remapLowRegOffs = 0; ++ pWinRegInfo->remapHighRegOffs = 0; ++ } ++ else if (MV_PEX_WIN_EXP_ROM == winNum) ++ { ++ pWinRegInfo->baseLowRegOffs = 0; ++ pWinRegInfo->baseHighRegOffs = 0; ++ pWinRegInfo->sizeRegOffs = PEX_WIN_EXP_ROM_CTRL_REG(pexIf); ++ pWinRegInfo->remapLowRegOffs = PEX_WIN_EXP_ROM_REMAP_REG(pexIf); ++ pWinRegInfo->remapHighRegOffs = 0; ++ ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* pexBarNameGet - Get the string name of PEX BAR. ++* ++* DESCRIPTION: ++* This function get the string name of PEX BAR. ++* ++* INPUT: ++* bar - PEX bar number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* pointer to the string name of PEX BAR. ++* ++*******************************************************************************/ ++const MV_8* pexBarNameGet( MV_U32 bar ) ++{ ++ switch( bar ) ++ { ++ case PEX_INTER_REGS_BAR: ++ return "Internal Regs Bar0...."; ++ case PEX_DRAM_BAR: ++ return "DRAM Bar1............."; ++ case PEX_DEVICE_BAR: ++ return "Devices Bar2.........."; ++ default: ++ return "Bar unknown"; ++ } ++} ++/******************************************************************************* ++* mvPexAddrDecShow - Print the PEX address decode map (BARs and windows). ++* ++* DESCRIPTION: ++* This function print the PEX address decode map (BARs and windows). ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvPexAddrDecShow(MV_VOID) ++{ ++ MV_PEX_BAR pexBar; ++ MV_PEX_DEC_WIN win; ++ MV_U32 pexIf; ++ MV_U32 bar,winNum; ++ ++ for( pexIf = 0; pexIf < mvCtrlPexMaxIfGet(); pexIf++ ) ++ { ++ if (MV_FALSE == mvCtrlPwrClckGet(PEX_UNIT_ID, pexIf)) continue; ++ mvOsOutput( "\n" ); ++ mvOsOutput( "PEX%d:\n", pexIf ); ++ mvOsOutput( "-----\n" ); ++ ++ mvOsOutput( "\nPex Bars \n\n"); ++ ++ for( bar = 0; bar < PEX_MAX_BARS; bar++ ) ++ { ++ memset( &pexBar, 0, sizeof(MV_PEX_BAR) ); ++ ++ mvOsOutput( "%s ", pexBarNameGet(bar) ); ++ ++ if( mvPexBarGet( pexIf, bar, &pexBar ) == MV_OK ) ++ { ++ if( pexBar.enable ) ++ { ++ mvOsOutput( "base %08x, ", pexBar.addrWin.baseLow ); ++ mvSizePrint( pexBar.addrWin.size ); ++ mvOsOutput( "\n" ); ++ } ++ else ++ mvOsOutput( "disable\n" ); ++ } ++ } ++ mvOsOutput( "\nPex Decode Windows\n\n"); ++ ++ for( winNum = 0; winNum < PEX_MAX_TARGET_WIN - 2; winNum++) ++ { ++ memset( &win, 0,sizeof(MV_PEX_DEC_WIN) ); ++ ++ mvOsOutput( "win%d - ", winNum ); ++ ++ if ( mvPexTargetWinGet(pexIf,winNum,&win) == MV_OK) ++ { ++ if (win.enable) ++ { ++ mvOsOutput( "%s base %08x, ", ++ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); ++ mvOsOutput( "...." ); ++ mvSizePrint( win.addrWin.size ); ++ ++ mvOsOutput( "\n" ); ++ } ++ else ++ mvOsOutput( "disable\n" ); ++ ++ ++ } ++ } ++ ++ memset( &win, 0,sizeof(MV_PEX_DEC_WIN) ); ++ ++ mvOsOutput( "default win - " ); ++ ++ if ( mvPexTargetWinGet(pexIf, MV_PEX_WIN_DEFAULT, &win) == MV_OK) ++ { ++ mvOsOutput( "%s ", ++ mvCtrlTargetNameGet(win.target) ); ++ mvOsOutput( "\n" ); ++ } ++ memset( &win, 0,sizeof(MV_PEX_DEC_WIN) ); ++ ++ mvOsOutput( "Expansion ROM - " ); ++ ++ if ( mvPexTargetWinGet(pexIf, MV_PEX_WIN_EXP_ROM, &win) == MV_OK) ++ { ++ mvOsOutput( "%s ", ++ mvCtrlTargetNameGet(win.target) ); ++ mvOsOutput( "\n" ); ++ } ++ ++ } ++} ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,348 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCSysPEXH ++#define __INCSysPEXH ++ ++#include "mvCommon.h" ++#include "ctrlEnv/sys/mvCpuIf.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "ctrlEnv/mvCtrlEnvAddrDec.h" ++ ++/* 4KB granularity */ ++#define MINIMUM_WINDOW_SIZE 0x1000 ++#define MINIMUM_BAR_SIZE 0x1000 ++#define MINIMUM_BAR_SIZE_MASK 0xFFFFF000 ++#define BAR_SIZE_OFFS 12 ++#define BAR_SIZE_MASK (0xFFFFF << BAR_SIZE_OFFS) ++ ++ ++ ++#define MV_PEX_WIN_DEFAULT 6 ++#define MV_PEX_WIN_EXP_ROM 7 ++#define PEX_MAX_TARGET_WIN 8 ++ ++ ++#define PEX_MAX_BARS 3 ++#define PEX_INTER_REGS_BAR 0 ++#define PEX_DRAM_BAR 1 ++#define PEX_DEVICE_BAR 2 ++ ++/*************************************/ ++/* PCI Express BAR Control Registers */ ++/*************************************/ ++#define PEX_BAR_CTRL_REG(pexIf,bar) (0x41804 + (bar-1)*4- (pexIf)*0x10000) ++#define PEX_EXP_ROM_BAR_CTRL_REG(pexIf) (0x4180C - (pexIf)*0x10000) ++ ++ ++/* PCI Express BAR Control Register */ ++/* PEX_BAR_CTRL_REG (PXBCR) */ ++ ++#define PXBCR_BAR_EN BIT0 ++#define PXBCR_BAR_SIZE_OFFS 16 ++#define PXBCR_BAR_SIZE_MASK (0xffff << PXBCR_BAR_SIZE_OFFS) ++#define PXBCR_BAR_SIZE_ALIGNMENT 0x10000 ++ ++ ++ ++/* PCI Express Expansion ROM BAR Control Register */ ++/* PEX_EXP_ROM_BAR_CTRL_REG (PXERBCR) */ ++ ++#define PXERBCR_EXPROM_EN BIT0 ++#define PXERBCR_EXPROMSZ_OFFS 19 ++#define PXERBCR_EXPROMSZ_MASK (0xf << PXERBCR_EXPROMSZ_OFFS) ++#define PXERBCR_EXPROMSZ_512KB (0x0 << PXERBCR_EXPROMSZ_OFFS) ++#define PXERBCR_EXPROMSZ_1024KB (0x1 << PXERBCR_EXPROMSZ_OFFS) ++#define PXERBCR_EXPROMSZ_2048KB (0x3 << PXERBCR_EXPROMSZ_OFFS) ++#define PXERBCR_EXPROMSZ_4096KB (0x7 << PXERBCR_EXPROMSZ_OFFS) ++ ++/************************************************/ ++/* PCI Express Address Window Control Registers */ ++/************************************************/ ++#define PEX_WIN0_3_CTRL_REG(pexIf,winNum) \ ++ (0x41820 + (winNum) * 0x10 - (pexIf) * 0x10000) ++#define PEX_WIN0_3_BASE_REG(pexIf,winNum) \ ++ (0x41824 + (winNum) * 0x10 - (pexIf) * 0x10000) ++#define PEX_WIN0_3_REMAP_REG(pexIf,winNum) \ ++ (0x4182C + (winNum) * 0x10 - (pexIf) * 0x10000) ++#define PEX_WIN4_5_CTRL_REG(pexIf,winNum) \ ++ (0x41860 + (winNum - 4) * 0x20 - (pexIf) * 0x10000) ++#define PEX_WIN4_5_BASE_REG(pexIf,winNum) \ ++ (0x41864 + (winNum - 4) * 0x20 - (pexIf) * 0x10000) ++#define PEX_WIN4_5_REMAP_REG(pexIf,winNum) \ ++ (0x4186C + (winNum - 4) * 0x20 - (pexIf) * 0x10000) ++#define PEX_WIN4_5_REMAP_HIGH_REG(pexIf,winNum) \ ++ (0x41870 + (winNum - 4) * 0x20 - (pexIf) * 0x10000) ++ ++#define PEX_WIN_DEFAULT_CTRL_REG(pexIf) (0x418B0 - (pexIf) * 0x10000) ++#define PEX_WIN_EXP_ROM_CTRL_REG(pexIf) (0x418C0 - (pexIf) * 0x10000) ++#define PEX_WIN_EXP_ROM_REMAP_REG(pexIf) (0x418C4 - (pexIf) * 0x10000) ++ ++/* PCI Express Window Control Register */ ++/* PEX_WIN_CTRL_REG (PXWCR) */ ++ ++#define PXWCR_WIN_EN BIT0 /* Window Enable.*/ ++ ++#define PXWCR_WIN_BAR_MAP_OFFS 1 /* Mapping to BAR.*/ ++#define PXWCR_WIN_BAR_MAP_MASK BIT1 ++#define PXWCR_WIN_BAR_MAP_BAR1 (0 << PXWCR_WIN_BAR_MAP_OFFS) ++#define PXWCR_WIN_BAR_MAP_BAR2 (1 << PXWCR_WIN_BAR_MAP_OFFS) ++ ++#define PXWCR_TARGET_OFFS 4 /*Unit ID */ ++#define PXWCR_TARGET_MASK (0xf << PXWCR_TARGET_OFFS) ++ ++#define PXWCR_ATTRIB_OFFS 8 /* target attributes */ ++#define PXWCR_ATTRIB_MASK (0xff << PXWCR_ATTRIB_OFFS) ++ ++#define PXWCR_SIZE_OFFS 16 /* size */ ++#define PXWCR_SIZE_MASK (0xffff << PXWCR_SIZE_OFFS) ++#define PXWCR_SIZE_ALIGNMENT 0x10000 ++ ++/* PCI Express Window Base Register */ ++/* PEX_WIN_BASE_REG (PXWBR)*/ ++ ++#define PXWBR_BASE_OFFS 16 /* address[31:16] */ ++#define PXWBR_BASE_MASK (0xffff << PXWBR_BASE_OFFS) ++#define PXWBR_BASE_ALIGNMENT 0x10000 ++ ++/* PCI Express Window Remap Register */ ++/* PEX_WIN_REMAP_REG (PXWRR)*/ ++ ++#define PXWRR_REMAP_EN BIT0 ++#define PXWRR_REMAP_OFFS 16 ++#define PXWRR_REMAP_MASK (0xffff << PXWRR_REMAP_OFFS) ++#define PXWRR_REMAP_ALIGNMENT 0x10000 ++ ++/* PCI Express Window Remap (High) Register */ ++/* PEX_WIN_REMAP_HIGH_REG (PXWRHR)*/ ++ ++#define PXWRHR_REMAP_HIGH_OFFS 0 ++#define PXWRHR_REMAP_HIGH_MASK (0xffffffff << PXWRHR_REMAP_HIGH_OFFS) ++ ++/* PCI Express Default Window Control Register */ ++/* PEX_WIN_DEFAULT_CTRL_REG (PXWDCR) */ ++ ++#define PXWDCR_TARGET_OFFS 4 /*Unit ID */ ++#define PXWDCR_TARGET_MASK (0xf << PXWDCR_TARGET_OFFS) ++#define PXWDCR_ATTRIB_OFFS 8 /* target attributes */ ++#define PXWDCR_ATTRIB_MASK (0xff << PXWDCR_ATTRIB_OFFS) ++ ++/* PCI Express Expansion ROM Window Control Register */ ++/* PEX_WIN_EXP_ROM_CTRL_REG (PXWERCR)*/ ++ ++#define PXWERCR_TARGET_OFFS 4 /*Unit ID */ ++#define PXWERCR_TARGET_MASK (0xf << PXWERCR_TARGET_OFFS) ++#define PXWERCR_ATTRIB_OFFS 8 /* target attributes */ ++#define PXWERCR_ATTRIB_MASK (0xff << PXWERCR_ATTRIB_OFFS) ++ ++/* PCI Express Expansion ROM Window Remap Register */ ++/* PEX_WIN_EXP_ROM_REMAP_REG (PXWERRR)*/ ++ ++#define PXWERRR_REMAP_EN BIT0 ++#define PXWERRR_REMAP_OFFS 16 ++#define PXWERRR_REMAP_MASK (0xffff << PXWERRR_REMAP_OFFS) ++#define PXWERRR_REMAP_ALIGNMENT 0x10000 ++ ++ ++ ++/*PEX_MEMORY_BAR_BASE_ADDR(barNum) (PXMBBA)*/ ++/* PCI Express BAR0 Internal Register*/ ++/*PEX BAR0_INTER_REG (PXBIR)*/ ++ ++#define PXBIR_IOSPACE BIT0 /* Memory Space Indicator */ ++ ++#define PXBIR_TYPE_OFFS 1 /* BAR Type/Init Val. */ ++#define PXBIR_TYPE_MASK (0x3 << PXBIR_TYPE_OFFS) ++#define PXBIR_TYPE_32BIT_ADDR (0x0 << PXBIR_TYPE_OFFS) ++#define PXBIR_TYPE_64BIT_ADDR (0x2 << PXBIR_TYPE_OFFS) ++ ++#define PXBIR_PREFETCH_EN BIT3 /* Prefetch Enable */ ++ ++#define PXBIR_BASE_OFFS 20 /* Base address. Address bits [31:20] */ ++#define PXBIR_BASE_MASK (0xfff << PXBIR_BASE_OFFS) ++#define PXBIR_BASE_ALIGNMET (1 << PXBIR_BASE_OFFS) ++ ++ ++/* PCI Express BAR0 Internal (High) Register*/ ++/*PEX BAR0_INTER_REG_HIGH (PXBIRH)*/ ++ ++#define PXBIRH_BASE_OFFS 0 /* Base address. Bits [63:32] */ ++#define PXBIRH_BASE_MASK (0xffffffff << PBBHR_BASE_OFFS) ++ ++ ++#define PEX_BAR_DEFAULT_ATTRIB 0xc /* Memory - Prefetch - 64 bit address */ ++#define PEX_BAR0_DEFAULT_ATTRIB PEX_BAR_DEFAULT_ATTRIB ++#define PEX_BAR1_DEFAULT_ATTRIB PEX_BAR_DEFAULT_ATTRIB ++#define PEX_BAR2_DEFAULT_ATTRIB PEX_BAR_DEFAULT_ATTRIB ++ ++ ++/* PCI Express BAR1 Register */ ++/* PCI Express BAR2 Register*/ ++/*PEX BAR1_REG (PXBR)*/ ++/*PEX BAR2_REG (PXBR)*/ ++ ++#define PXBR_IOSPACE BIT0 /* Memory Space Indicator */ ++ ++#define PXBR_TYPE_OFFS 1 /* BAR Type/Init Val. */ ++#define PXBR_TYPE_MASK (0x3 << PXBR_TYPE_OFFS) ++#define PXBR_TYPE_32BIT_ADDR (0x0 << PXBR_TYPE_OFFS) ++#define PXBR_TYPE_64BIT_ADDR (0x2 << PXBR_TYPE_OFFS) ++ ++#define PXBR_PREFETCH_EN BIT3 /* Prefetch Enable */ ++ ++#define PXBR_BASE_OFFS 16 /* Base address. Address bits [31:16] */ ++#define PXBR_BASE_MASK (0xffff << PXBR_BASE_OFFS) ++#define PXBR_BASE_ALIGNMET (1 << PXBR_BASE_OFFS) ++ ++ ++/* PCI Express BAR1 (High) Register*/ ++/* PCI Express BAR2 (High) Register*/ ++/*PEX BAR1_REG_HIGH (PXBRH)*/ ++/*PEX BAR2_REG_HIGH (PXBRH)*/ ++ ++#define PXBRH_BASE_OFFS 0 /* Base address. Address bits [63:32] */ ++#define PXBRH_BASE_MASK (0xffffffff << PXBRH_BASE_OFFS) ++ ++/* PCI Express Expansion ROM BAR Register*/ ++/*PEX_EXPANSION_ROM_BASE_ADDR_REG (PXERBAR)*/ ++ ++#define PXERBAR_EXPROMEN BIT0 /* Expansion ROM Enable */ ++ ++#define PXERBAR_BASE_512K_OFFS 19 /* Expansion ROM Base Address */ ++#define PXERBAR_BASE_512K_MASK (0x1fff << PXERBAR_BASE_512K_OFFS) ++ ++#define PXERBAR_BASE_1MB_OFFS 20 /* Expansion ROM Base Address */ ++#define PXERBAR_BASE_1MB_MASK (0xfff << PXERBAR_BASE_1MB_OFFS) ++ ++#define PXERBAR_BASE_2MB_OFFS 21 /* Expansion ROM Base Address */ ++#define PXERBAR_BASE_2MB_MASK (0x7ff << PXERBAR_BASE_2MB_OFFS) ++ ++#define PXERBAR_BASE_4MB_OFFS 22 /* Expansion ROM Base Address */ ++#define PXERBAR_BASE_4MB_MASK (0x3ff << PXERBAR_BASE_4MB_OFFS) ++ ++/* PEX Bar attributes */ ++typedef struct _mvPexBar ++{ ++ MV_ADDR_WIN addrWin; /* An address window*/ ++ MV_BOOL enable; /* Address decode window is enabled/disabled */ ++ ++}MV_PEX_BAR; ++ ++/* PEX Remap Window attributes */ ++typedef struct _mvPexRemapWin ++{ ++ MV_ADDR_WIN addrWin; /* An address window*/ ++ MV_BOOL enable; /* Address decode window is enabled/disabled */ ++ ++}MV_PEX_REMAP_WIN; ++ ++/* PEX Remap Window attributes */ ++typedef struct _mvPexDecWin ++{ ++ MV_TARGET target; ++ MV_ADDR_WIN addrWin; /* An address window*/ ++ MV_U32 targetBar; ++ MV_U8 attrib; /* chip select attributes */ ++ MV_TARGET_ID targetId; /* Target Id of this MV_TARGET */ ++ MV_BOOL enable; /* Address decode window is enabled/disabled */ ++ ++}MV_PEX_DEC_WIN; ++ ++/* Global Functions prototypes */ ++/* mvPexHalInit - Initialize PEX interfaces*/ ++MV_STATUS mvPexInit(MV_U32 pexIf, MV_PEX_TYPE pexType); ++ ++ ++/* mvPexTargetWinSet - Set PEX to peripheral target address window BAR*/ ++MV_STATUS mvPexTargetWinSet(MV_U32 pexIf, MV_U32 winNum, ++ MV_PEX_DEC_WIN *pAddrDecWin); ++ ++/* mvPexTargetWinGet - Get PEX to peripheral target address window*/ ++MV_STATUS mvPexTargetWinGet(MV_U32 pexIf, MV_U32 winNum, ++ MV_PEX_DEC_WIN *pAddrDecWin); ++ ++/* mvPexTargetWinEnable - Enable/disable a PEX BAR window*/ ++MV_STATUS mvPexTargetWinEnable(MV_U32 pexIf,MV_U32 winNum, MV_BOOL enable); ++ ++/* mvPexTargetWinRemap - Set PEX to target address window remap.*/ ++MV_STATUS mvPexTargetWinRemap(MV_U32 pexIf, MV_U32 winNum, ++ MV_PEX_REMAP_WIN *pAddrWin); ++ ++/* mvPexTargetWinRemapEnable -enable\disable a PEX Window remap.*/ ++MV_STATUS mvPexTargetWinRemapEnable(MV_U32 pexIf, MV_U32 winNum, ++ MV_BOOL enable); ++ ++/* mvPexBarSet - Set PEX bar address and size */ ++MV_STATUS mvPexBarSet(MV_U32 pexIf, MV_U32 barNum, MV_PEX_BAR *addrWin); ++ ++/* mvPexBarGet - Get PEX bar address and size */ ++MV_STATUS mvPexBarGet(MV_U32 pexIf, MV_U32 barNum, MV_PEX_BAR *addrWin); ++ ++/* mvPexBarEnable - enable\disable a PEX bar*/ ++MV_STATUS mvPexBarEnable(MV_U32 pexIf, MV_U32 barNum, MV_BOOL enable); ++ ++/* mvPexAddrDecShow - Display address decode windows attributes */ ++MV_VOID mvPexAddrDecShow(MV_VOID); ++ ++#endif +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,430 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#include "mvTypes.h" ++#include "mvCommon.h" ++#include "mvOs.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "cpu/mvCpu.h" ++#include "ctrlEnv/sys/mvCpuIf.h" ++#include "sata/CoreDriver/mvRegs.h" ++#include "ctrlEnv/sys/mvSysSata.h" ++ ++MV_TARGET sataAddrDecPrioTab[] = ++{ ++#if defined(MV_INCLUDE_SDRAM_CS0) ++ SDRAM_CS0, ++#endif ++#if defined(MV_INCLUDE_SDRAM_CS1) ++ SDRAM_CS1, ++#endif ++#if defined(MV_INCLUDE_SDRAM_CS2) ++ SDRAM_CS2, ++#endif ++#if defined(MV_INCLUDE_SDRAM_CS3) ++ SDRAM_CS3, ++#endif ++#if defined(MV_INCLUDE_PEX) ++ PEX0_MEM, ++#endif ++ TBL_TERM ++}; ++ ++ ++/******************************************************************************* ++* sataWinOverlapDetect - Detect SATA address windows overlapping ++* ++* DESCRIPTION: ++* An unpredicted behaviur is expected in case SATA address decode ++* windows overlapps. ++* This function detects SATA address decode windows overlapping of a ++* specified window. The function does not check the window itself for ++* overlapping. The function also skipps disabled address decode windows. ++* ++* INPUT: ++* winNum - address decode window number. ++* pAddrDecWin - An address decode window struct. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the given address window overlap current address ++* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data ++* from registers. ++* ++*******************************************************************************/ ++static MV_STATUS sataWinOverlapDetect(int dev, MV_U32 winNum, ++ MV_ADDR_WIN *pAddrWin) ++{ ++ MV_U32 winNumIndex; ++ MV_SATA_DEC_WIN addrDecWin; ++ ++ for(winNumIndex=0; winNumIndex= MV_SATA_MAX_ADDR_DECODE_WIN) ++ { ++ mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check if the requested window overlapps with current windows */ ++ if (MV_TRUE == sataWinOverlapDetect(dev, winNum, &pAddrDecWin->addrWin)) ++ { ++ mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); ++ return MV_ERROR; ++ } ++ ++ /* check if address is aligned to the size */ ++ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) ++ { ++ mvOsPrintf("mvSataWinSet:Error setting SATA window %d to "\ ++ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", ++ winNum, ++ mvCtrlTargetNameGet(pAddrDecWin->target), ++ pAddrDecWin->addrWin.baseLow, ++ pAddrDecWin->addrWin.size); ++ return MV_ERROR; ++ } ++ ++ decRegs.baseReg = 0; ++ decRegs.sizeReg = 0; ++ ++ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) ++ { ++ mvOsPrintf("%s: mvCtrlAddrDecToReg Failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); ++ ++ /* set attributes */ ++ decRegs.sizeReg &= ~MV_SATA_WIN_ATTR_MASK; ++ decRegs.sizeReg |= (targetAttribs.attrib << MV_SATA_WIN_ATTR_OFFSET); ++ ++ /* set target ID */ ++ decRegs.sizeReg &= ~MV_SATA_WIN_TARGET_MASK; ++ decRegs.sizeReg |= (targetAttribs.targetId << MV_SATA_WIN_TARGET_OFFSET); ++ ++ if (pAddrDecWin->enable == MV_TRUE) ++ { ++ decRegs.sizeReg |= MV_SATA_WIN_ENABLE_MASK; ++ } ++ else ++ { ++ decRegs.sizeReg &= ~MV_SATA_WIN_ENABLE_MASK; ++ } ++ ++ MV_REG_WRITE( MV_SATA_WIN_CTRL_REG(dev, winNum), decRegs.sizeReg); ++ MV_REG_WRITE( MV_SATA_WIN_BASE_REG(dev, winNum), decRegs.baseReg); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvSataWinGet - Get SATA peripheral target address window. ++* ++* DESCRIPTION: ++* Get SATA peripheral target address window. ++* ++* INPUT: ++* winNum - SATA target address decode window number. ++* ++* OUTPUT: ++* pAddrDecWin - SATA target window data structure. ++* ++* RETURN: ++* MV_ERROR if register parameters are invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvSataWinGet(int dev, MV_U32 winNum, MV_SATA_DEC_WIN *pAddrDecWin) ++{ ++ MV_DEC_REGS decRegs; ++ MV_TARGET_ATTRIB targetAttrib; ++ ++ /* Parameter checking */ ++ if (winNum >= MV_SATA_MAX_ADDR_DECODE_WIN) ++ { ++ mvOsPrintf("%s (dev=%d): ERR. Invalid winNum %d\n", ++ __FUNCTION__, dev, winNum); ++ return MV_NOT_SUPPORTED; ++ } ++ ++ decRegs.baseReg = MV_REG_READ( MV_SATA_WIN_BASE_REG(dev, winNum) ); ++ decRegs.sizeReg = MV_REG_READ( MV_SATA_WIN_CTRL_REG(dev, winNum) ); ++ ++ if (MV_OK != mvCtrlRegToAddrDec(&decRegs, &pAddrDecWin->addrWin) ) ++ { ++ mvOsPrintf("%s: mvCtrlRegToAddrDec Failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ /* attrib and targetId */ ++ targetAttrib.attrib = (decRegs.sizeReg & MV_SATA_WIN_ATTR_MASK) >> ++ MV_SATA_WIN_ATTR_OFFSET; ++ targetAttrib.targetId = (decRegs.sizeReg & MV_SATA_WIN_TARGET_MASK) >> ++ MV_SATA_WIN_TARGET_OFFSET; ++ ++ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); ++ ++ /* Check if window is enabled */ ++ if(decRegs.sizeReg & MV_SATA_WIN_ENABLE_MASK) ++ { ++ pAddrDecWin->enable = MV_TRUE; ++ } ++ else ++ { ++ pAddrDecWin->enable = MV_FALSE; ++ } ++ return MV_OK; ++} ++/******************************************************************************* ++* mvSataAddrDecShow - Print the SATA address decode map. ++* ++* DESCRIPTION: ++* This function print the SATA address decode map. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvSataAddrDecShow(MV_VOID) ++{ ++ ++ MV_SATA_DEC_WIN win; ++ int i,j; ++ ++ ++ ++ for( j = 0; j < MV_SATA_MAX_CHAN; j++ ) ++ { ++ if (MV_FALSE == mvCtrlPwrClckGet(SATA_UNIT_ID, j)) ++ return; ++ ++ mvOsOutput( "\n" ); ++ mvOsOutput( "SATA %d:\n", j ); ++ mvOsOutput( "----\n" ); ++ ++ for( i = 0; i < MV_SATA_MAX_ADDR_DECODE_WIN; i++ ) ++ { ++ memset( &win, 0, sizeof(MV_SATA_DEC_WIN) ); ++ ++ mvOsOutput( "win%d - ", i ); ++ ++ if( mvSataWinGet(j, i, &win ) == MV_OK ) ++ { ++ if( win.enable ) ++ { ++ mvOsOutput( "%s base %08x, ", ++ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); ++ mvOsOutput( "...." ); ++ ++ mvSizePrint( win.addrWin.size ); ++ ++ mvOsOutput( "\n" ); ++ } ++ else ++ mvOsOutput( "disable\n" ); ++ } ++ } ++ } ++} ++ ++ ++/******************************************************************************* ++* mvSataWinInit - Initialize the integrated SATA target address window. ++* ++* DESCRIPTION: ++* Initialize the SATA peripheral target address window. ++* ++* INPUT: ++* ++* ++* OUTPUT: ++* ++* ++* RETURN: ++* MV_ERROR if register parameters are invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvSataWinInit(MV_VOID) ++{ ++ int winNum; ++ MV_SATA_DEC_WIN sataWin; ++ MV_CPU_DEC_WIN cpuAddrDecWin; ++ MV_U32 status, winPrioIndex = 0; ++ ++ /* Initiate Sata address decode */ ++ ++ /* First disable all address decode windows */ ++ for(winNum = 0; winNum < MV_SATA_MAX_ADDR_DECODE_WIN; winNum++) ++ { ++ MV_U32 regVal = MV_REG_READ(MV_SATA_WIN_CTRL_REG(0, winNum)); ++ regVal &= ~MV_SATA_WIN_ENABLE_MASK; ++ MV_REG_WRITE(MV_SATA_WIN_CTRL_REG(0, winNum), regVal); ++ } ++ ++ winNum = 0; ++ while( (sataAddrDecPrioTab[winPrioIndex] != TBL_TERM) && ++ (winNum < MV_SATA_MAX_ADDR_DECODE_WIN) ) ++ { ++ /* first get attributes from CPU If */ ++ status = mvCpuIfTargetWinGet(sataAddrDecPrioTab[winPrioIndex], ++ &cpuAddrDecWin); ++ ++ if(MV_NO_SUCH == status) ++ { ++ winPrioIndex++; ++ continue; ++ } ++ if (MV_OK != status) ++ { ++ mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ if (cpuAddrDecWin.enable == MV_TRUE) ++ { ++ sataWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; ++ sataWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; ++ sataWin.addrWin.size = cpuAddrDecWin.addrWin.size; ++ sataWin.enable = MV_TRUE; ++ sataWin.target = sataAddrDecPrioTab[winPrioIndex]; ++ ++ if(MV_OK != mvSataWinSet(0/*dev*/, winNum, &sataWin)) ++ { ++ return MV_ERROR; ++ } ++ winNum++; ++ } ++ winPrioIndex++; ++ } ++ return MV_OK; ++} ++ ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,128 @@ ++ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++#ifndef __INCMVSysSataAddrDech ++#define __INCMVSysSataAddrDech ++ ++#include "mvCommon.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "ctrlEnv/sys/mvCpuIf.h" ++ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++typedef struct _mvSataDecWin ++{ ++ MV_TARGET target; ++ MV_ADDR_WIN addrWin; /* An address window*/ ++ MV_BOOL enable; /* Address decode window is enabled/disabled */ ++ ++} MV_SATA_DEC_WIN; ++ ++ ++#define MV_SATA_MAX_ADDR_DECODE_WIN 4 ++ ++#define MV_SATA_WIN_CTRL_REG(dev, win) (SATA_REG_BASE + 0x30 + ((win)<<4)) ++#define MV_SATA_WIN_BASE_REG(dev, win) (SATA_REG_BASE + 0x34 + ((win)<<4)) ++ ++/* BITs in Bridge Interrupt Cause and Mask registers */ ++#define MV_SATA_ADDR_DECODE_ERROR_BIT 0 ++#define MV_SATA_ADDR_DECODE_ERROR_MASK (1<= MV_SDMMC_MAX_ADDR_DECODE_WIN) ++ { ++ mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check if the requested window overlapps with current windows */ ++ if (MV_TRUE == sdmmcWinOverlapDetect(dev, winNum, &pAddrDecWin->addrWin)) ++ { ++ mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); ++ return MV_ERROR; ++ } ++ ++ /* check if address is aligned to the size */ ++ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) ++ { ++ mvOsPrintf("mvSdmmcWinSet:Error setting SDMMC window %d to "\ ++ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", ++ winNum, ++ mvCtrlTargetNameGet(pAddrDecWin->target), ++ pAddrDecWin->addrWin.baseLow, ++ pAddrDecWin->addrWin.size); ++ return MV_ERROR; ++ } ++ ++ decRegs.baseReg = 0; ++ decRegs.sizeReg = 0; ++ ++ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) ++ { ++ mvOsPrintf("%s: mvCtrlAddrDecToReg Failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); ++ ++ /* set attributes */ ++ decRegs.sizeReg &= ~MV_SDMMC_WIN_ATTR_MASK; ++ decRegs.sizeReg |= (targetAttribs.attrib << MV_SDMMC_WIN_ATTR_OFFSET); ++ ++ /* set target ID */ ++ decRegs.sizeReg &= ~MV_SDMMC_WIN_TARGET_MASK; ++ decRegs.sizeReg |= (targetAttribs.targetId << MV_SDMMC_WIN_TARGET_OFFSET); ++ ++ if (pAddrDecWin->enable == MV_TRUE) ++ { ++ decRegs.sizeReg |= MV_SDMMC_WIN_ENABLE_MASK; ++ } ++ else ++ { ++ decRegs.sizeReg &= ~MV_SDMMC_WIN_ENABLE_MASK; ++ } ++ ++ MV_REG_WRITE( MV_SDMMC_WIN_CTRL_REG(dev, winNum), decRegs.sizeReg); ++ MV_REG_WRITE( MV_SDMMC_WIN_BASE_REG(dev, winNum), decRegs.baseReg); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvSdmmcWinGet - Get SDMMC peripheral target address window. ++* ++* DESCRIPTION: ++* Get SDMMC peripheral target address window. ++* ++* INPUT: ++* winNum - SDMMC target address decode window number. ++*d ++* OUTPUT: ++* pAddrDecWin - SDMMC target window data structure. ++* ++* RETURN: ++* MV_ERROR if register parameters are invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvSdmmcWinGet(int dev, MV_U32 winNum, MV_SDMMC_DEC_WIN *pAddrDecWin) ++{ ++ MV_DEC_REGS decRegs; ++ MV_TARGET_ATTRIB targetAttrib; ++ ++ /* Parameter checking */ ++ if (winNum >= MV_SDMMC_MAX_ADDR_DECODE_WIN) ++ { ++ mvOsPrintf("%s (dev=%d): ERR. Invalid winNum %d\n", ++ __FUNCTION__, dev, winNum); ++ return MV_NOT_SUPPORTED; ++ } ++ ++ decRegs.baseReg = MV_REG_READ( MV_SDMMC_WIN_BASE_REG(dev, winNum) ); ++ decRegs.sizeReg = MV_REG_READ( MV_SDMMC_WIN_CTRL_REG(dev, winNum) ); ++ ++ if (MV_OK != mvCtrlRegToAddrDec(&decRegs, &pAddrDecWin->addrWin) ) ++ { ++ mvOsPrintf("%s: mvCtrlRegToAddrDec Failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ /* attrib and targetId */ ++ targetAttrib.attrib = (decRegs.sizeReg & MV_SDMMC_WIN_ATTR_MASK) >> ++ MV_SDMMC_WIN_ATTR_OFFSET; ++ targetAttrib.targetId = (decRegs.sizeReg & MV_SDMMC_WIN_TARGET_MASK) >> ++ MV_SDMMC_WIN_TARGET_OFFSET; ++ ++ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); ++ ++ /* Check if window is enabled */ ++ if(decRegs.sizeReg & MV_SDMMC_WIN_ENABLE_MASK) ++ { ++ pAddrDecWin->enable = MV_TRUE; ++ } ++ else ++ { ++ pAddrDecWin->enable = MV_FALSE; ++ } ++ return MV_OK; ++} ++/******************************************************************************* ++* mvSdmmcAddrDecShow - Print the SDMMC address decode map. ++* ++* DESCRIPTION: ++* This function print the SDMMC address decode map. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvSdmmcAddrDecShow(MV_VOID) ++{ ++ ++ MV_SDMMC_DEC_WIN win; ++ int i,j=0; ++ ++ ++ ++ if (MV_FALSE == mvCtrlPwrClckGet(SDIO_UNIT_ID, 0)) ++ return; ++ ++ mvOsOutput( "\n" ); ++ mvOsOutput( "SDMMC %d:\n", j ); ++ mvOsOutput( "----\n" ); ++ ++ for( i = 0; i < MV_SDMMC_MAX_ADDR_DECODE_WIN; i++ ) ++ { ++ memset( &win, 0, sizeof(MV_SDMMC_DEC_WIN) ); ++ ++ mvOsOutput( "win%d - ", i ); ++ ++ if( mvSdmmcWinGet(j, i, &win ) == MV_OK ) ++ { ++ if( win.enable ) ++ { ++ mvOsOutput( "%s base %08x, ", ++ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); ++ mvOsOutput( "...." ); ++ ++ mvSizePrint( win.addrWin.size ); ++ ++ mvOsOutput( "\n" ); ++ } ++ else ++ mvOsOutput( "disable\n" ); ++ } ++ } ++} ++ ++ ++/******************************************************************************* ++* mvSdmmcWinInit - Initialize the integrated SDMMC target address window. ++* ++* DESCRIPTION: ++* Initialize the SDMMC peripheral target address window. ++* ++* INPUT: ++* ++* ++* OUTPUT: ++* ++* ++* RETURN: ++* MV_ERROR if register parameters are invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvSdmmcWinInit(MV_VOID) ++{ ++ int winNum; ++ MV_SDMMC_DEC_WIN sdmmcWin; ++ MV_CPU_DEC_WIN cpuAddrDecWin; ++ MV_U32 status, winPrioIndex = 0; ++ ++ /* Initiate Sdmmc address decode */ ++ ++ /* First disable all address decode windows */ ++ for(winNum = 0; winNum < MV_SDMMC_MAX_ADDR_DECODE_WIN; winNum++) ++ { ++ MV_U32 regVal = MV_REG_READ(MV_SDMMC_WIN_CTRL_REG(0, winNum)); ++ regVal &= ~MV_SDMMC_WIN_ENABLE_MASK; ++ MV_REG_WRITE(MV_SDMMC_WIN_CTRL_REG(0, winNum), regVal); ++ } ++ ++ winNum = 0; ++ while( (sdmmcAddrDecPrioTab[winPrioIndex] != TBL_TERM) && ++ (winNum < MV_SDMMC_MAX_ADDR_DECODE_WIN) ) ++ { ++ /* first get attributes from CPU If */ ++ status = mvCpuIfTargetWinGet(sdmmcAddrDecPrioTab[winPrioIndex], ++ &cpuAddrDecWin); ++ ++ if(MV_NO_SUCH == status) ++ { ++ winPrioIndex++; ++ continue; ++ } ++ if (MV_OK != status) ++ { ++ mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ if (cpuAddrDecWin.enable == MV_TRUE) ++ { ++ sdmmcWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; ++ sdmmcWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; ++ sdmmcWin.addrWin.size = cpuAddrDecWin.addrWin.size; ++ sdmmcWin.enable = MV_TRUE; ++ sdmmcWin.target = sdmmcAddrDecPrioTab[winPrioIndex]; ++ ++ if(MV_OK != mvSdmmcWinSet(0/*dev*/, winNum, &sdmmcWin)) ++ { ++ return MV_ERROR; ++ } ++ winNum++; ++ } ++ winPrioIndex++; ++ } ++ return MV_OK; ++} ++ ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,125 @@ ++ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++#ifndef __INCMVSysSdmmcAddrDech ++#define __INCMVSysSdmmcAddrDech ++ ++#include "mvCommon.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "ctrlEnv/sys/mvCpuIf.h" ++ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++typedef struct _mvSdmmcDecWin ++{ ++ MV_TARGET target; ++ MV_ADDR_WIN addrWin; /* An address window*/ ++ MV_BOOL enable; /* Address decode window is enabled/disabled */ ++ ++} MV_SDMMC_DEC_WIN; ++ ++ ++#define MV_SDMMC_MAX_ADDR_DECODE_WIN 4 ++ ++#define MV_SDMMC_WIN_CTRL_REG(dev, win) (MV_SDIO_REG_BASE + 0x108 + ((win)<<3)) ++#define MV_SDMMC_WIN_BASE_REG(dev, win) (MV_SDIO_REG_BASE + 0x10c + ((win)<<3)) ++ ++ ++/* BITs in Windows 0-3 Control and Base Registers */ ++#define MV_SDMMC_WIN_ENABLE_BIT 0 ++#define MV_SDMMC_WIN_ENABLE_MASK (1<= TDM_MBUS_MAX_WIN) ++ { ++ mvOsPrintf("mvTdmWinSet: ERR. Invalid win num %d\n",winNum); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check if the requested window overlapps with current windows */ ++ if (MV_TRUE == tdmWinOverlapDetect(winNum, &pAddrDecWin->addrWin)) ++ { ++ mvOsPrintf("mvTdmWinSet: ERR. Window %d overlap\n", winNum); ++ return MV_ERROR; ++ } ++ ++ /* check if address is aligned to the size */ ++ if (MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) ++ { ++ mvOsPrintf("mvTdmWinSet: Error setting TDM window %d to "\ ++ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", ++ winNum, ++ mvCtrlTargetNameGet(pAddrDecWin->target), ++ pAddrDecWin->addrWin.baseLow, ++ pAddrDecWin->addrWin.size); ++ return MV_ERROR; ++ } ++ ++ decRegs.baseReg = MV_REG_READ(TDM_WIN_BASE_REG(winNum)); ++ decRegs.sizeReg = (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_SIZE_MASK) >> TDM_WIN_SIZE_OFFS; ++ ++ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) ++ { ++ mvOsPrintf("mvTdmWinSet: mvCtrlAddrDecToReg Failed\n"); ++ return MV_ERROR; ++ } ++ ++ mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); ++ ++ /* for the safe side we disable the window before writing the new ++ values */ ++ mvTdmWinEnable(winNum, MV_FALSE); ++ ++ ctrlReg |= (targetAttribs.attrib << TDM_WIN_ATTRIB_OFFS); ++ ctrlReg |= (targetAttribs.targetId << TDM_WIN_TARGET_OFFS); ++ ctrlReg |= (decRegs.sizeReg & TDM_WIN_SIZE_MASK); ++ ++ /* Write to address base and control registers */ ++ MV_REG_WRITE(TDM_WIN_BASE_REG(winNum), decRegs.baseReg); ++ MV_REG_WRITE(TDM_WIN_CTRL_REG(winNum), ctrlReg); ++ /* Enable address decode target window */ ++ if (pAddrDecWin->enable == MV_TRUE) ++ { ++ mvTdmWinEnable(winNum, MV_TRUE); ++ } ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvTdmWinGet - Get peripheral target address window. ++* ++* DESCRIPTION: ++* Get TDM peripheral target address window. ++* ++* INPUT: ++* winNum - TDM to target address decode window number. ++* ++* OUTPUT: ++* pAddrDecWin - TDM target window data structure. ++* ++* RETURN: ++* MV_ERROR if register parameters are invalid. ++* ++*******************************************************************************/ ++ ++MV_STATUS mvTdmWinGet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin) ++{ ++ ++ MV_DEC_REGS decRegs; ++ MV_TARGET_ATTRIB targetAttrib; ++ ++ /* Parameter checking */ ++ if (winNum >= TDM_MBUS_MAX_WIN) ++ { ++ mvOsPrintf("mvTdmWinGet: ERR. Invalid winNum %d\n", winNum); ++ return MV_NOT_SUPPORTED; ++ } ++ ++ decRegs.baseReg = MV_REG_READ(TDM_WIN_BASE_REG(winNum)); ++ decRegs.sizeReg = (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_SIZE_MASK) >> TDM_WIN_SIZE_OFFS; ++ ++ if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) ++ { ++ mvOsPrintf("mvTdmWinGet: mvCtrlRegToAddrDec Failed \n"); ++ return MV_ERROR; ++ } ++ ++ /* attrib and targetId */ ++ targetAttrib.attrib = ++ (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ATTRIB_MASK) >> TDM_WIN_ATTRIB_OFFS; ++ targetAttrib.targetId = ++ (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_TARGET_MASK) >> TDM_WIN_TARGET_OFFS; ++ ++ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); ++ ++ /* Check if window is enabled */ ++ if (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ENABLE_MASK) ++ { ++ pAddrDecWin->enable = MV_TRUE; ++ } ++ else ++ { ++ pAddrDecWin->enable = MV_FALSE; ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvTdmWinEnable - Enable/disable a TDM to target address window ++* ++* DESCRIPTION: ++* This function enable/disable a TDM to target address window. ++* According to parameter 'enable' the routine will enable the ++* window, thus enabling TDM accesses (before enabling the window it is ++* tested for overlapping). Otherwise, the window will be disabled. ++* ++* INPUT: ++* winNum - TDM to target address decode window number. ++* enable - Enable/disable parameter. ++* ++* OUTPUT: ++* N/A ++* ++* RETURN: ++* MV_ERROR if decode window number was wrong or enabled window overlapps. ++* ++*******************************************************************************/ ++MV_STATUS mvTdmWinEnable(int winNum, MV_BOOL enable) ++{ ++ MV_TDM_DEC_WIN addrDecWin; ++ ++ if (MV_TRUE == enable) ++ { ++ if (winNum >= TDM_MBUS_MAX_WIN) ++ { ++ mvOsPrintf("mvTdmWinEnable:ERR. Invalid winNum%d\n",winNum); ++ return MV_ERROR; ++ } ++ ++ /* First check for overlap with other enabled windows */ ++ /* Get current window */ ++ if (MV_OK != mvTdmWinGet(winNum, &addrDecWin)) ++ { ++ mvOsPrintf("mvTdmWinEnable:ERR. targetWinGet fail\n"); ++ return MV_ERROR; ++ } ++ /* Check for overlapping */ ++ if (MV_FALSE == tdmWinOverlapDetect(winNum, &(addrDecWin.addrWin))) ++ { ++ /* No Overlap. Enable address decode target window */ ++ MV_REG_BIT_SET(TDM_WIN_CTRL_REG(winNum), TDM_WIN_ENABLE_MASK); ++ } ++ else ++ { /* Overlap detected */ ++ mvOsPrintf("mvTdmWinEnable:ERR. Overlap detected\n"); ++ return MV_ERROR; ++ } ++ } ++ else ++ { ++ MV_REG_BIT_RESET(TDM_WIN_CTRL_REG(winNum), TDM_WIN_ENABLE_MASK); ++ } ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* tdmWinOverlapDetect - Detect TDM address windows overlapping ++* ++* DESCRIPTION: ++* An unpredicted behaviour is expected in case TDM address decode ++* windows overlapps. ++* This function detects TDM address decode windows overlapping of a ++* specified window. The function does not check the window itself for ++* overlapping. The function also skipps disabled address decode windows. ++* ++* INPUT: ++* winNum - address decode window number. ++* pAddrDecWin - An address decode window struct. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the given address window overlap current address ++* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data ++* from registers. ++* ++*******************************************************************************/ ++static MV_STATUS tdmWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) ++{ ++ MV_U32 winNumIndex; ++ MV_TDM_DEC_WIN addrDecWin; ++ ++ for (winNumIndex = 0; winNumIndex < TDM_MBUS_MAX_WIN; winNumIndex++) ++ { ++ /* Do not check window itself */ ++ if (winNumIndex == winNum) ++ { ++ continue; ++ } ++ /* Do not check disabled windows */ ++ if (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ENABLE_MASK) ++ { ++ /* Get window parameters */ ++ if (MV_OK != mvTdmWinGet(winNumIndex, &addrDecWin)) ++ { ++ DB(mvOsPrintf("dmaWinOverlapDetect: ERR. TargetWinGet failed\n")); ++ return MV_ERROR; ++ } ++ ++ if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin))) ++ { ++ return MV_TRUE; ++ } ++ } ++ } ++ return MV_FALSE; ++} ++ ++/******************************************************************************* ++* mvTdmAddrDecShow - Print the TDM address decode map. ++* ++* DESCRIPTION: ++* This function print the TDM address decode map. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvTdmAddrDecShow(MV_VOID) ++{ ++ MV_TDM_DEC_WIN win; ++ int i; ++ ++ mvOsOutput( "\n" ); ++ mvOsOutput( "TDM:\n" ); ++ mvOsOutput( "----\n" ); ++ ++ for( i = 0; i < TDM_MBUS_MAX_WIN; i++ ) ++ { ++ memset( &win, 0, sizeof(MV_TDM_DEC_WIN) ); ++ ++ mvOsOutput( "win%d - ", i ); ++ ++ if (mvTdmWinGet(i, &win ) == MV_OK ) ++ { ++ if( win.enable ) ++ { ++ mvOsOutput( "%s base %08x, ", ++ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow); ++ mvOsOutput( "...." ); ++ mvSizePrint( win.addrWin.size ); ++ mvOsOutput( "\n" ); ++ } ++ else ++ mvOsOutput( "disable\n" ); ++ } ++ } ++} ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,106 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvSysTdmh ++#define __INCmvSysTdmh ++ ++#include "ctrlEnv/sys/mvCpuIf.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "ctrlEnv/mvCtrlEnvAddrDec.h" ++ ++typedef struct _mvTdmDecWin ++{ ++ MV_TARGET target; ++ MV_ADDR_WIN addrWin; /* An address window*/ ++ MV_BOOL enable; /* Address decode window is enabled/disabled */ ++} MV_TDM_DEC_WIN; ++ ++MV_STATUS mvTdmWinInit(MV_VOID); ++MV_STATUS mvTdmWinSet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin); ++MV_STATUS mvTdmWinGet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin); ++MV_STATUS mvTdmWinEnable(int winNum, MV_BOOL enable); ++MV_VOID mvTdmAddrDecShow(MV_VOID); ++ ++ ++#define TDM_MBUS_MAX_WIN 4 ++#define TDM_WIN_CTRL_REG(win) ((TDM_REG_BASE + 0x4030) + (win<<4)) ++#define TDM_WIN_BASE_REG(win) ((TDM_REG_BASE +0x4034) + (win<<4)) ++ ++/* TDM_WIN_CTRL_REG bits */ ++#define TDM_WIN_ENABLE_OFFS 0 ++#define TDM_WIN_ENABLE_MASK (1<= TSU_MAX_DECODE_WIN) ++ { ++ mvOsPrintf("mvTsuWinSet: ERR. Invalid win num %d\n",winNum); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check if the requested window overlapps with current windows */ ++ if(MV_TRUE == tsuWinOverlapDetect(winNum, &pAddrDecWin->addrWin)) ++ { ++ mvOsPrintf("mvTsuWinSet: ERR. Window %d overlap\n", winNum); ++ return MV_ERROR; ++ } ++ ++ /* check if address is aligned to the size */ ++ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow,pAddrDecWin->addrWin.size)) ++ { ++ mvOsPrintf("mvTsuWinSet: Error setting TSU window %d to target " ++ "%s.\nAddress 0x%08x is unaligned to size 0x%x.\n", ++ winNum, mvCtrlTargetNameGet(pAddrDecWin->target), ++ pAddrDecWin->addrWin.baseLow, ++ pAddrDecWin->addrWin.size); ++ return MV_ERROR; ++ } ++ ++ decRegs.baseReg = MV_REG_READ(MV_TSU_WIN_BASE_REG(winNum)); ++ decRegs.sizeReg = MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNum)); ++ ++ if(MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) ++ { ++ mvOsPrintf("mvTsuWinSet: mvCtrlAddrDecToReg Failed\n"); ++ return MV_ERROR; ++ } ++ ++ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); ++ ++ /* set attributes */ ++ decRegs.sizeReg &= ~TSU_WIN_CTRL_ATTR_MASK; ++ decRegs.sizeReg |= targetAttribs.attrib << TSU_WIN_CTRL_ATTR_OFFS; ++ /* set target ID */ ++ decRegs.sizeReg &= ~TSU_WIN_CTRL_TARGET_MASK; ++ decRegs.sizeReg |= targetAttribs.targetId << TSU_WIN_CTRL_TARGET_OFFS; ++ ++ /* for the safe side we disable the window before writing the new */ ++ /* values */ ++ mvTsuWinEnable(winNum, MV_FALSE); ++ MV_REG_WRITE(MV_TSU_WIN_CTRL_REG(winNum),decRegs.sizeReg); ++ ++ /* Write to address decode Size Register */ ++ MV_REG_WRITE(MV_TSU_WIN_BASE_REG(winNum), decRegs.baseReg); ++ ++ /* Enable address decode target window */ ++ if(pAddrDecWin->enable == MV_TRUE) ++ { ++ mvTsuWinEnable(winNum,MV_TRUE); ++ } ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvTsuWinGet ++* ++* DESCRIPTION: ++* Get TSU peripheral target address window. ++* ++* INPUT: ++* winNum - TSU to target address decode window number. ++* ++* OUTPUT: ++* pAddrDecWin - TSU target window data structure. ++* ++* RETURN: ++* MV_ERROR if register parameters are invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvTsuWinGet(MV_U32 winNum, MV_TSU_DEC_WIN *pAddrDecWin) ++{ ++ MV_DEC_REGS decRegs; ++ MV_TARGET_ATTRIB targetAttrib; ++ ++ /* Parameter checking */ ++ if(winNum >= TSU_MAX_DECODE_WIN) ++ { ++ mvOsPrintf("mvTsuWinGet: ERR. Invalid winNum %d\n", winNum); ++ return MV_NOT_SUPPORTED; ++ } ++ ++ decRegs.baseReg = MV_REG_READ(MV_TSU_WIN_BASE_REG(winNum)); ++ decRegs.sizeReg = MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNum)); ++ ++ if(MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) ++ { ++ mvOsPrintf("mvTsuWinGet: mvCtrlRegToAddrDec Failed \n"); ++ return MV_ERROR; ++ } ++ ++ /* attrib and targetId */ ++ targetAttrib.attrib = ++ (decRegs.sizeReg & TSU_WIN_CTRL_ATTR_MASK) >> TSU_WIN_CTRL_ATTR_OFFS; ++ targetAttrib.targetId = ++ (decRegs.sizeReg & TSU_WIN_CTRL_TARGET_MASK) >> TSU_WIN_CTRL_TARGET_OFFS; ++ ++ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); ++ ++ /* Check if window is enabled */ ++ if((MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNum)) & TSU_WIN_CTRL_EN_MASK)) ++ { ++ pAddrDecWin->enable = MV_TRUE; ++ } ++ else ++ { ++ pAddrDecWin->enable = MV_FALSE; ++ } ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvTsuWinEnable ++* ++* DESCRIPTION: ++* This function enable/disable a TSU to target address window. ++* According to parameter 'enable' the routine will enable the ++* window, thus enabling TSU accesses (before enabling the window it is ++* tested for overlapping). Otherwise, the window will be disabled. ++* ++* INPUT: ++* winNum - TSU to target address decode window number. ++* enable - Enable / disable parameter. ++* ++* OUTPUT: ++* N/A ++* ++* RETURN: ++* MV_ERROR if decode window number was wrong or enabled window overlapps. ++* ++*******************************************************************************/ ++MV_STATUS mvTsuWinEnable(MV_U32 winNum,MV_BOOL enable) ++{ ++ MV_TSU_DEC_WIN addrDecWin; ++ ++ /* Parameter checking */ ++ if(winNum >= TSU_MAX_DECODE_WIN) ++ { ++ mvOsPrintf("mvTsuWinEnable: ERR. Invalid winNum%d\n",winNum); ++ return MV_ERROR; ++ } ++ ++ if(enable == MV_TRUE) ++ { ++ /* First check for overlap with other enabled windows */ ++ /* Get current window. */ ++ if(MV_OK != mvTsuWinGet(winNum,&addrDecWin)) ++ { ++ mvOsPrintf("mvTsuWinEnable: ERR. targetWinGet fail\n"); ++ return MV_ERROR; ++ } ++ /* Check for overlapping. */ ++ if(MV_FALSE == tsuWinOverlapDetect(winNum,&(addrDecWin.addrWin))) ++ { ++ /* No Overlap. Enable address decode target window */ ++ MV_REG_BIT_SET(MV_TSU_WIN_CTRL_REG(winNum), ++ TSU_WIN_CTRL_EN_MASK); ++ } ++ else ++ { ++ /* Overlap detected */ ++ mvOsPrintf("mvTsuWinEnable: ERR. Overlap detected\n"); ++ return MV_ERROR; ++ } ++ } ++ else ++ { ++ /* Disable address decode target window */ ++ MV_REG_BIT_RESET(MV_TSU_WIN_CTRL_REG(winNum), ++ TSU_WIN_CTRL_EN_MASK); ++ } ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvTsuWinTargetGet ++* ++* DESCRIPTION: ++* Get Window number associated with target ++* ++* INPUT: ++* target - Target ID to get the window number for. ++* OUTPUT: ++* ++* RETURN: ++* window number or 0xFFFFFFFF on error. ++* ++*******************************************************************************/ ++MV_U32 mvTsuWinTargetGet(MV_TARGET target) ++{ ++ MV_TSU_DEC_WIN decWin; ++ MV_U32 winNum; ++ ++ /* Check parameters */ ++ if(target >= MAX_TARGETS) ++ { ++ mvOsPrintf("mvTsuWinTargetGet: target %d is Illigal\n", target); ++ return 0xffffffff; ++ } ++ ++ for(winNum = 0; winNum < TSU_MAX_DECODE_WIN; winNum++) ++ { ++ if(mvTsuWinGet(winNum,&decWin) != MV_OK) ++ { ++ mvOsPrintf("mvTsuWinGet: window returned error\n"); ++ return 0xffffffff; ++ } ++ ++ if (decWin.enable == MV_TRUE) ++ { ++ if(decWin.target == target) ++ { ++ return winNum; ++ } ++ } ++ } ++ return 0xFFFFFFFF; ++} ++ ++ ++/******************************************************************************* ++* tsuWinOverlapDetect ++* ++* DESCRIPTION: ++* Detect TSU address windows overlapping ++* An unpredicted behaviur is expected in case TSU address decode ++* windows overlapps. ++* This function detects TSU address decode windows overlapping of a ++* specified window. The function does not check the window itself for ++* overlapping. The function also skipps disabled address decode windows. ++* ++* INPUT: ++* winNum - address decode window number. ++* pAddrDecWin - An address decode window struct. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the given address window overlap current address ++* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data ++* from registers. ++* ++*******************************************************************************/ ++static MV_STATUS tsuWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) ++{ ++ MV_U32 ctrlReg; ++ MV_U32 winNumIndex; ++ MV_TSU_DEC_WIN addrDecWin; ++ ++ for(winNumIndex = 0; winNumIndex < TSU_MAX_DECODE_WIN; winNumIndex++) ++ { ++ /* Do not check window itself */ ++ if(winNumIndex == winNum) ++ { ++ continue; ++ } ++ ++ /* Do not check disabled windows */ ++ ctrlReg = MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNumIndex)); ++ if((ctrlReg & TSU_WIN_CTRL_EN_MASK) == 0) ++ { ++ continue; ++ } ++ ++ /* Get window parameters */ ++ if (MV_OK != mvTsuWinGet(winNumIndex, &addrDecWin)) ++ { ++ mvOsPrintf("tsuWinOverlapDetect: ERR. mvTsuWinGet failed\n"); ++ return MV_ERROR; ++ } ++ ++ if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin))) ++ { ++ return MV_TRUE; ++ } ++ } ++ return MV_FALSE; ++} ++ ++ ++/******************************************************************************* ++* mvTsuAddrDecShow ++* ++* DESCRIPTION: ++* Print the TSU address decode map. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++void mvTsuAddrDecShow(void) ++{ ++ MV_TSU_DEC_WIN win; ++ int i; ++ ++ if (MV_FALSE == mvCtrlPwrClckGet(TS_UNIT_ID, 0)) ++ return; ++ ++ mvOsOutput( "\n" ); ++ mvOsOutput( "TSU:\n"); ++ mvOsOutput( "----\n" ); ++ ++ for(i = 0; i < TSU_MAX_DECODE_WIN; i++) ++ { ++ memset(&win, 0, sizeof(TSU_MAX_DECODE_WIN)); ++ mvOsOutput( "win%d - ", i ); ++ ++ if(mvTsuWinGet(i, &win ) == MV_OK ) ++ { ++ if(win.enable == MV_TRUE) ++ { ++ mvOsOutput("%s base %08x, ", ++ mvCtrlTargetNameGet(win.target), ++ win.addrWin.baseLow); ++ mvOsOutput( "...." ); ++ mvSizePrint(win.addrWin.size ); ++ mvOsOutput( "\n" ); ++ } ++ else ++ { ++ mvOsOutput( "disable\n" ); ++ } ++ } ++ } ++ return; ++} ++ ++ ++/******************************************************************************* ++* mvTsuInit ++* ++* DESCRIPTION: ++* Initialize the TSU unit, and get unit out of reset. ++* ++* INPUT: ++* coreClock - The core clock at which the TSU should operate. ++* mode - The mode on configure the unit into (serial/parallel). ++* memHandle - Memory handle used for memory allocations. ++* OUTPUT: ++* None. ++* RETURN: ++* MV_OK - on success, ++* ++*******************************************************************************/ ++MV_STATUS mvTsuInit(MV_TSU_CORE_CLOCK coreClock, MV_TSU_PORTS_MODE mode, ++ void *osHandle) ++{ ++ MV_STATUS status; ++ ++ status = mvTsuWinInit(); ++ if(status == MV_OK) ++ status = mvTsuHalInit(coreClock,mode,osHandle); ++ ++ return status; ++} +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,110 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvSysTsh ++#define __INCmvSysTsh ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++/* includes */ ++#include "ts/mvTsu.h" ++#include "ctrlEnv/sys/mvCpuIf.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "ctrlEnv/mvCtrlEnvAddrDec.h" ++ ++#define TSU_MAX_DECODE_WIN 4 ++ ++ ++/*******************************************/ ++/* TSU Windows Registers */ ++/*******************************************/ ++#define MV_TSU_WIN_CTRL_REG(win) (TSU_GLOBAL_REG_BASE +0x30 + 0x10 * win) ++#define MV_TSU_WIN_BASE_REG(win) (TSU_GLOBAL_REG_BASE +0x34 + 0x10 * win) ++ ++/* TSU windows control register. */ ++#define TSU_WIN_CTRL_EN_MASK (0x1 << 0) ++#define TSU_WIN_CTRL_TARGET_OFFS 4 ++#define TSU_WIN_CTRL_TARGET_MASK (0xF << TSU_WIN_CTRL_TARGET_OFFS) ++#define TSU_WIN_CTRL_ATTR_OFFS 8 ++#define TSU_WIN_CTRL_ATTR_MASK (0xFF << TSU_WIN_CTRL_ATTR_OFFS) ++#define TSU_WIN_CTRL_SIZE_OFFS 16 ++#define TSU_WIN_CTRL_SIZE_MASK (0xFFFF << TSU_WIN_CTRL_SIZE_OFFS) ++ ++/* TSU windows base register. */ ++#define TSU_WIN_BASE_OFFS 16 ++#define TSU_WIN_BASE_MASK (0xFFFF << TSU_WIN_BASE_OFFS) ++ ++MV_STATUS mvTsuWinInit(void); ++ ++void mvTsuAddrDecShow(void); ++MV_STATUS mvTsuInit(MV_TSU_CORE_CLOCK coreClock, MV_TSU_PORTS_MODE mode, ++ void *osHandle); ++ ++#ifdef __cplusplus ++} ++#endif /* __cplusplus */ ++ ++#endif /* __INCmvTsh */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,497 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#include "ctrlEnv/sys/mvSysUsb.h" ++ ++MV_TARGET usbAddrDecPrioTab[] = ++{ ++#if defined(MV_INCLUDE_SDRAM_CS0) ++ SDRAM_CS0, ++#endif ++#if defined(MV_INCLUDE_SDRAM_CS1) ++ SDRAM_CS1, ++#endif ++#if defined(MV_INCLUDE_SDRAM_CS2) ++ SDRAM_CS2, ++#endif ++#if defined(MV_INCLUDE_SDRAM_CS3) ++ SDRAM_CS3, ++#endif ++#if defined(MV_INCLUDE_CESA) && defined(USB_UNDERRUN_WA) ++ CRYPT_ENG, ++#endif ++#if defined(MV_INCLUDE_PEX) ++ PEX0_MEM, ++#endif ++ TBL_TERM ++}; ++ ++ ++ ++MV_STATUS mvUsbInit(int dev, MV_BOOL isHost) ++{ ++ MV_STATUS status; ++ ++ status = mvUsbWinInit(dev); ++ if(status != MV_OK) ++ return status; ++ ++ return mvUsbHalInit(dev, isHost); ++} ++ ++ ++/******************************************************************************* ++* usbWinOverlapDetect - Detect USB address windows overlapping ++* ++* DESCRIPTION: ++* An unpredicted behaviur is expected in case USB address decode ++* windows overlapps. ++* This function detects USB address decode windows overlapping of a ++* specified window. The function does not check the window itself for ++* overlapping. The function also skipps disabled address decode windows. ++* ++* INPUT: ++* winNum - address decode window number. ++* pAddrDecWin - An address decode window struct. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the given address window overlap current address ++* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data ++* from registers. ++* ++*******************************************************************************/ ++static MV_STATUS usbWinOverlapDetect(int dev, MV_U32 winNum, ++ MV_ADDR_WIN *pAddrWin) ++{ ++ MV_U32 winNumIndex; ++ MV_DEC_WIN addrDecWin; ++ ++ for(winNumIndex=0; winNumIndex= MV_USB_MAX_ADDR_DECODE_WIN) ++ { ++ mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check if the requested window overlapps with current windows */ ++ if (MV_TRUE == usbWinOverlapDetect(dev, winNum, &pDecWin->addrWin)) ++ { ++ mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); ++ return MV_ERROR; ++ } ++ ++ /* check if address is aligned to the size */ ++ if(MV_IS_NOT_ALIGN(pDecWin->addrWin.baseLow, pDecWin->addrWin.size)) ++ { ++ mvOsPrintf("mvUsbWinSet:Error setting USB window %d to "\ ++ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", ++ winNum, ++ mvCtrlTargetNameGet(pDecWin->target), ++ pDecWin->addrWin.baseLow, ++ pDecWin->addrWin.size); ++ return MV_ERROR; ++ } ++ ++ if(MV_OK != mvCtrlAddrDecToParams(pDecWin, &winParams)) ++ { ++ mvOsPrintf("%s: mvCtrlAddrDecToParams Failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ /* set Size, Attributes and TargetID */ ++ sizeReg = (((winParams.targetId << MV_USB_WIN_TARGET_OFFSET) & MV_USB_WIN_TARGET_MASK) | ++ ((winParams.attrib << MV_USB_WIN_ATTR_OFFSET) & MV_USB_WIN_ATTR_MASK) | ++ ((winParams.size << MV_USB_WIN_SIZE_OFFSET) & MV_USB_WIN_SIZE_MASK)); ++ ++#if defined(MV645xx) || defined(MV646xx) ++ /* If window is DRAM with HW cache coherency, make sure bit2 is set */ ++ sizeReg &= ~MV_USB_WIN_BURST_WR_LIMIT_MASK; ++ ++ if((MV_TARGET_IS_DRAM(pDecWin->target)) && ++ (pDecWin->addrWinAttr.cachePolicy != NO_COHERENCY)) ++ { ++ sizeReg |= MV_USB_WIN_BURST_WR_32BIT_LIMIT; ++ } ++ else ++ { ++ sizeReg |= MV_USB_WIN_BURST_WR_NO_LIMIT; ++ } ++#endif /* MV645xx || MV646xx */ ++ ++ if (pDecWin->enable == MV_TRUE) ++ { ++ sizeReg |= MV_USB_WIN_ENABLE_MASK; ++ } ++ else ++ { ++ sizeReg &= ~MV_USB_WIN_ENABLE_MASK; ++ } ++ ++ /* Update Base value */ ++ baseReg = (winParams.baseAddr & MV_USB_WIN_BASE_MASK); ++ ++ MV_REG_WRITE( MV_USB_WIN_CTRL_REG(dev, winNum), sizeReg); ++ MV_REG_WRITE( MV_USB_WIN_BASE_REG(dev, winNum), baseReg); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvUsbWinGet - Get USB peripheral target address window. ++* ++* DESCRIPTION: ++* Get USB peripheral target address window. ++* ++* INPUT: ++* winNum - USB target address decode window number. ++* ++* OUTPUT: ++* pDecWin - USB target window data structure. ++* ++* RETURN: ++* MV_ERROR if register parameters are invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvUsbWinGet(int dev, MV_U32 winNum, MV_DEC_WIN *pDecWin) ++{ ++ MV_DEC_WIN_PARAMS winParam; ++ MV_U32 sizeReg, baseReg; ++ ++ /* Parameter checking */ ++ if (winNum >= MV_USB_MAX_ADDR_DECODE_WIN) ++ { ++ mvOsPrintf("%s (dev=%d): ERR. Invalid winNum %d\n", ++ __FUNCTION__, dev, winNum); ++ return MV_NOT_SUPPORTED; ++ } ++ ++ baseReg = MV_REG_READ( MV_USB_WIN_BASE_REG(dev, winNum) ); ++ sizeReg = MV_REG_READ( MV_USB_WIN_CTRL_REG(dev, winNum) ); ++ ++ /* Check if window is enabled */ ++ if(sizeReg & MV_USB_WIN_ENABLE_MASK) ++ { ++ pDecWin->enable = MV_TRUE; ++ ++ /* Extract window parameters from registers */ ++ winParam.targetId = (sizeReg & MV_USB_WIN_TARGET_MASK) >> MV_USB_WIN_TARGET_OFFSET; ++ winParam.attrib = (sizeReg & MV_USB_WIN_ATTR_MASK) >> MV_USB_WIN_ATTR_OFFSET; ++ winParam.size = (sizeReg & MV_USB_WIN_SIZE_MASK) >> MV_USB_WIN_SIZE_OFFSET; ++ winParam.baseAddr = (baseReg & MV_USB_WIN_BASE_MASK); ++ ++ /* Translate the decode window parameters to address decode struct */ ++ if (MV_OK != mvCtrlParamsToAddrDec(&winParam, pDecWin)) ++ { ++ mvOsPrintf("Failed to translate register parameters to USB address" \ ++ " decode window structure\n"); ++ return MV_ERROR; ++ } ++ } ++ else ++ { ++ pDecWin->enable = MV_FALSE; ++ } ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvUsbWinInit - ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++* MV_ERROR if register parameters are invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvUsbWinInit(int dev) ++{ ++ MV_STATUS status; ++ MV_DEC_WIN usbWin; ++ MV_CPU_DEC_WIN cpuAddrDecWin; ++ int winNum; ++ MV_U32 winPrioIndex = 0; ++ ++ /* First disable all address decode windows */ ++ for(winNum = 0; winNum < MV_USB_MAX_ADDR_DECODE_WIN; winNum++) ++ { ++ MV_REG_BIT_RESET(MV_USB_WIN_CTRL_REG(dev, winNum), MV_USB_WIN_ENABLE_MASK); ++ } ++ ++ /* Go through all windows in user table until table terminator */ ++ winNum = 0; ++ while( (usbAddrDecPrioTab[winPrioIndex] != TBL_TERM) && ++ (winNum < MV_USB_MAX_ADDR_DECODE_WIN) ) ++ { ++ /* first get attributes from CPU If */ ++ status = mvCpuIfTargetWinGet(usbAddrDecPrioTab[winPrioIndex], ++ &cpuAddrDecWin); ++ ++ if(MV_NO_SUCH == status) ++ { ++ winPrioIndex++; ++ continue; ++ } ++ if (MV_OK != status) ++ { ++ mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ if (cpuAddrDecWin.enable == MV_TRUE) ++ { ++ usbWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; ++ usbWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; ++ usbWin.addrWin.size = cpuAddrDecWin.addrWin.size; ++ usbWin.enable = MV_TRUE; ++ usbWin.target = usbAddrDecPrioTab[winPrioIndex]; ++ ++#if defined(MV645xx) || defined(MV646xx) ++ /* Get the default attributes for that target window */ ++ mvCtrlDefAttribGet(usbWin.target, &usbWin.addrWinAttr); ++#endif /* MV645xx || MV646xx */ ++ ++ if(MV_OK != mvUsbWinSet(dev, winNum, &usbWin)) ++ { ++ return MV_ERROR; ++ } ++ winNum++; ++ } ++ winPrioIndex++; ++ } ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvUsbAddrDecShow - Print the USB address decode map. ++* ++* DESCRIPTION: ++* This function print the USB address decode map. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvUsbAddrDecShow(MV_VOID) ++{ ++ MV_DEC_WIN addrDecWin; ++ int i, winNum; ++ ++ mvOsOutput( "\n" ); ++ mvOsOutput( "USB:\n" ); ++ mvOsOutput( "----\n" ); ++ ++ for(i=0; i= XOR_MAX_ADDR_DEC_WIN) ++ { ++ DB(mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum)); ++ return MV_BAD_PARAM; ++ } ++ if (pAddrDecWin == NULL) ++ { ++ DB(mvOsPrintf("%s: ERR. pAddrDecWin is NULL pointer\n", __FUNCTION__ )); ++ return MV_BAD_PTR; ++ } ++ /* Check if the requested window overlaps with current windows */ ++ if (MV_TRUE == xorWinOverlapDetect(unit, winNum, &pAddrDecWin->addrWin)) ++ { ++ DB(mvOsPrintf("%s: ERR. Window %d overlap\n",__FUNCTION__,winNum)); ++ return MV_ERROR; ++ } ++ ++ xorDecRegs.baseReg = MV_REG_READ(XOR_BASE_ADDR_REG(unit,winNum)); ++ xorDecRegs.sizeReg = MV_REG_READ(XOR_SIZE_MASK_REG(unit,winNum)); ++ ++ /* Get Base Address and size registers values */ ++ if(MV_OK != mvCtrlAddrDecToReg(&pAddrDecWin->addrWin, &xorDecRegs)) ++ { ++ DB(mvOsPrintf("%s: ERR. Invalid addr dec window\n",__FUNCTION__)); ++ return MV_BAD_PARAM; ++ } ++ ++ ++ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); ++ ++ /* set attributes */ ++ xorDecRegs.baseReg &= ~XEBARX_ATTR_MASK; ++ xorDecRegs.baseReg |= targetAttribs.attrib << XEBARX_ATTR_OFFS; ++ /* set target ID */ ++ xorDecRegs.baseReg &= ~XEBARX_TARGET_MASK; ++ xorDecRegs.baseReg |= targetAttribs.targetId << XEBARX_TARGET_OFFS; ++ ++ ++ /* Write to address decode Base Address Register */ ++ MV_REG_WRITE(XOR_BASE_ADDR_REG(unit,winNum), xorDecRegs.baseReg); ++ ++ /* Write to Size Register */ ++ MV_REG_WRITE(XOR_SIZE_MASK_REG(unit,winNum), xorDecRegs.sizeReg); ++ ++ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) ++ { ++ if (pAddrDecWin->enable) ++ { ++ MV_REG_BIT_SET(XOR_WINDOW_CTRL_REG(unit,chan), ++ XEXWCR_WIN_EN_MASK(winNum)); ++ } ++ else ++ { ++ MV_REG_BIT_RESET(XOR_WINDOW_CTRL_REG(unit,chan), ++ XEXWCR_WIN_EN_MASK(winNum)); ++ } ++ } ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvXorTargetWinGet - Get xor peripheral target address window. ++* ++* DESCRIPTION: ++* Get xor peripheral target address window. ++* ++* INPUT: ++* winNum - One of the possible XOR memory decode windows. ++* ++* OUTPUT: ++* base - Window base address. ++* size - Window size. ++* enable - window enable/disable. ++* ++* RETURN: ++* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. ++* ++*******************************************************************************/ ++MV_STATUS mvXorTargetWinGet(MV_U32 unit,MV_U32 winNum, MV_XOR_DEC_WIN *pAddrDecWin) ++{ ++ MV_DEC_REGS xorDecRegs; ++ MV_TARGET_ATTRIB targetAttrib; ++ MV_U32 chan=0,chanWinEn; ++ ++ /* Parameter checking */ ++ if (winNum >= XOR_MAX_ADDR_DEC_WIN) ++ { ++ DB(mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__ , winNum)); ++ return MV_ERROR; ++ } ++ ++ if (NULL == pAddrDecWin) ++ { ++ DB(mvOsPrintf("%s: ERR. pAddrDecWin is NULL pointer\n", __FUNCTION__ )); ++ return MV_BAD_PTR; ++ } ++ ++ chanWinEn = MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,0)) & XEXWCR_WIN_EN_MASK(winNum); ++ ++ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) /* we should scan here all channels per unit */ ++ { ++ /* Check if enable bit is equal for all channels */ ++ if ((MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,chan)) & ++ XEXWCR_WIN_EN_MASK(winNum)) != chanWinEn) ++ { ++ mvOsPrintf("%s: ERR. Window enable field must be equal in " ++ "all channels(chan=%d)\n",__FUNCTION__, chan); ++ return MV_ERROR; ++ } ++ } ++ ++ ++ ++ xorDecRegs.baseReg = MV_REG_READ(XOR_BASE_ADDR_REG(unit,winNum)); ++ xorDecRegs.sizeReg = MV_REG_READ(XOR_SIZE_MASK_REG(unit,winNum)); ++ ++ if (MV_OK != mvCtrlRegToAddrDec(&xorDecRegs, &pAddrDecWin->addrWin)) ++ { ++ mvOsPrintf("%s: ERR. mvCtrlRegToAddrDec failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ /* attrib and targetId */ ++ targetAttrib.attrib = ++ (xorDecRegs.baseReg & XEBARX_ATTR_MASK) >> XEBARX_ATTR_OFFS; ++ targetAttrib.targetId = ++ (xorDecRegs.baseReg & XEBARX_TARGET_MASK) >> XEBARX_TARGET_OFFS; ++ ++ ++ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); ++ ++ if(chanWinEn) ++ { ++ pAddrDecWin->enable = MV_TRUE; ++ } ++ else pAddrDecWin->enable = MV_FALSE; ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvXorTargetWinEnable - Enable/disable a Xor address decode window ++* ++* DESCRIPTION: ++* This function enable/disable a XOR address decode window. ++* if parameter 'enable' == MV_TRUE the routine will enable the ++* window, thus enabling XOR accesses (before enabling the window it is ++* tested for overlapping). Otherwise, the window will be disabled. ++* ++* INPUT: ++* winNum - Decode window number. ++* enable - Enable/disable parameter. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. ++* ++*******************************************************************************/ ++MV_STATUS mvXorTargetWinEnable(MV_U32 unit,MV_U32 winNum, MV_BOOL enable) ++{ ++ MV_XOR_DEC_WIN addrDecWin; ++ MV_U32 chan; ++ ++ /* Parameter checking */ ++ if (winNum >= XOR_MAX_ADDR_DEC_WIN) ++ { ++ DB(mvOsPrintf("%s: ERR. Invalid winNum%d\n", __FUNCTION__, winNum)); ++ return MV_ERROR; ++ } ++ ++ if (enable == MV_TRUE) ++ { ++ /* Get current window */ ++ if (MV_OK != mvXorTargetWinGet(unit,winNum, &addrDecWin)) ++ { ++ DB(mvOsPrintf("%s: ERR. targetWinGet fail\n", __FUNCTION__)); ++ return MV_ERROR; ++ } ++ ++ /* Check for overlapping */ ++ if (MV_TRUE == xorWinOverlapDetect(unit,winNum, &(addrDecWin.addrWin))) ++ { ++ /* Overlap detected */ ++ DB(mvOsPrintf("%s: ERR. Overlap detected\n", __FUNCTION__)); ++ return MV_ERROR; ++ } ++ ++ /* No Overlap. Enable address decode target window */ ++ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) ++ { ++ MV_REG_BIT_SET(XOR_WINDOW_CTRL_REG(unit,chan), ++ XEXWCR_WIN_EN_MASK(winNum)); ++ } ++ ++ } ++ else ++ { ++ /* Disable address decode target window */ ++ ++ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) ++ { ++ MV_REG_BIT_RESET(XOR_WINDOW_CTRL_REG(unit,chan), ++ XEXWCR_WIN_EN_MASK(winNum)); ++ } ++ ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvXorSetProtWinSet - Configure access attributes of a XOR engine ++* to one of the XOR memory windows. ++* ++* DESCRIPTION: ++* Each engine can be configured with access attributes for each of the ++* memory spaces. This function sets access attributes ++* to a given window for the given engine ++* ++* INPUTS: ++* chan - One of the possible engines. ++* winNum - One of the possible XOR memory spaces. ++* access - Protection access rights. ++* write - Write rights. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. ++* ++*******************************************************************************/ ++MV_STATUS mvXorProtWinSet (MV_U32 unit,MV_U32 chan, MV_U32 winNum, MV_BOOL access, ++ MV_BOOL write) ++{ ++ MV_U32 temp; ++ ++ /* Parameter checking */ ++ if (chan >= MV_XOR_MAX_CHAN_PER_UNIT) ++ { ++ DB(mvOsPrintf("%s: ERR. Invalid chan num %d\n", __FUNCTION__ , chan)); ++ return MV_BAD_PARAM; ++ } ++ if (winNum >= XOR_MAX_ADDR_DEC_WIN) ++ { ++ DB(mvOsPrintf("%s: ERR. Invalid win num %d\n", __FUNCTION__, winNum)); ++ return MV_BAD_PARAM; ++ } ++ ++ temp = MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,chan)) & ++ (~XEXWCR_WIN_ACC_MASK(winNum)); ++ ++ /* if access is disable */ ++ if (!access) ++ { ++ /* disable access */ ++ temp |= XEXWCR_WIN_ACC_NO_ACC(winNum); ++ } ++ /* if access is enable */ ++ else ++ { ++ /* if write is enable */ ++ if (write) ++ { ++ /* enable write */ ++ temp |= XEXWCR_WIN_ACC_RW(winNum); ++ } ++ /* if write is disable */ ++ else ++ { ++ /* disable write */ ++ temp |= XEXWCR_WIN_ACC_RO(winNum); ++ } ++ } ++ MV_REG_WRITE(XOR_WINDOW_CTRL_REG(unit,chan),temp); ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvXorPciRemap - Set XOR remap register for PCI address windows. ++* ++* DESCRIPTION: ++* only Windows 0-3 can be remapped. ++* ++* INPUT: ++* winNum - window number ++* pAddrDecWin - pointer to address space window structure ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. ++* ++*******************************************************************************/ ++MV_STATUS mvXorPciRemap(MV_U32 unit,MV_U32 winNum, MV_U32 addrHigh) ++{ ++ /* Parameter checking */ ++ if (winNum >= XOR_MAX_REMAP_WIN) ++ { ++ DB(mvOsPrintf("%s: ERR. Invalid win num %d\n", __FUNCTION__, winNum)); ++ return MV_BAD_PARAM; ++ } ++ ++ MV_REG_WRITE(XOR_HIGH_ADDR_REMAP_REG(unit,winNum), addrHigh); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* xorWinOverlapDetect - Detect XOR address windows overlaping ++* ++* DESCRIPTION: ++* An unpredicted behaviour is expected in case XOR address decode ++* windows overlaps. ++* This function detects XOR address decode windows overlaping of a ++* specified window. The function does not check the window itself for ++* overlaping. The function also skipps disabled address decode windows. ++* ++* INPUT: ++* winNum - address decode window number. ++* pAddrDecWin - An address decode window struct. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the given address window overlap current address ++* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data ++* from registers. ++* ++*******************************************************************************/ ++static MV_STATUS xorWinOverlapDetect(MV_U32 unit,MV_U32 winNum, MV_ADDR_WIN *pAddrWin) ++{ ++ MV_U32 baseAddrEnableReg; ++ MV_U32 winNumIndex,chan; ++ MV_XOR_DEC_WIN addrDecWin; ++ ++ if (pAddrWin == NULL) ++ { ++ DB(mvOsPrintf("%s: ERR. pAddrWin is NULL pointer\n", __FUNCTION__ )); ++ return MV_BAD_PTR; ++ } ++ ++ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) ++ { ++ /* Read base address enable register. Do not check disabled windows */ ++ baseAddrEnableReg = MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,chan)); ++ ++ for (winNumIndex = 0; winNumIndex < XOR_MAX_ADDR_DEC_WIN; winNumIndex++) ++ { ++ /* Do not check window itself */ ++ if (winNumIndex == winNum) ++ { ++ continue; ++ } ++ ++ /* Do not check disabled windows */ ++ if ((baseAddrEnableReg & XEXWCR_WIN_EN_MASK(winNumIndex)) == 0) ++ { ++ continue; ++ } ++ ++ /* Get window parameters */ ++ if (MV_OK != mvXorTargetWinGet(unit,winNumIndex, &addrDecWin)) ++ { ++ DB(mvOsPrintf("%s: ERR. TargetWinGet failed\n", __FUNCTION__ )); ++ return MV_ERROR; ++ } ++ ++ if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin))) ++ { ++ return MV_TRUE; ++ } ++ } ++ } ++ ++ return MV_FALSE; ++} ++ ++static MV_VOID mvXorAddrDecShowUnit(MV_U32 unit) ++{ ++ MV_XOR_DEC_WIN win; ++ int i; ++ ++ mvOsOutput( "\n" ); ++ mvOsOutput( "XOR %d:\n", unit ); ++ mvOsOutput( "----\n" ); ++ ++ for( i = 0; i < XOR_MAX_ADDR_DEC_WIN; i++ ) ++ { ++ memset( &win, 0, sizeof(MV_XOR_DEC_WIN) ); ++ ++ mvOsOutput( "win%d - ", i ); ++ ++ if( mvXorTargetWinGet(unit, i, &win ) == MV_OK ) ++ { ++ if( win.enable ) ++ { ++ mvOsOutput( "%s base %x, ", ++ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); ++ ++ mvSizePrint( win.addrWin.size ); ++ ++ mvOsOutput( "\n" ); ++ } ++ else ++ mvOsOutput( "disable\n" ); ++ } ++ } ++} ++ ++/******************************************************************************* ++* mvXorAddrDecShow - Print the XOR address decode map. ++* ++* DESCRIPTION: ++* This function print the XOR address decode map. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvXorAddrDecShow(MV_VOID) ++{ ++ int i; ++ ++ for( i = 0; i < MV_XOR_MAX_UNIT; i++ ) ++ mvXorAddrDecShowUnit(i); ++ ++} +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,140 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCMVSysXorh ++#define __INCMVSysXorh ++ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "ctrlEnv/sys/mvCpuIf.h" ++ ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "ctrlEnv/mvCtrlEnvAddrDec.h" ++ ++#define XOR_MAX_ADDR_DEC_WIN 8 /* Maximum address decode windows */ ++#define XOR_MAX_REMAP_WIN 4 /* Maximum address arbiter windows */ ++ ++/* XOR Engine Address Decoding Register Map */ ++#define XOR_WINDOW_CTRL_REG(unit,chan) (XOR_UNIT_BASE(unit)+(0x240 + ((chan) * 4))) ++#define XOR_BASE_ADDR_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x250 + ((winNum) * 4))) ++#define XOR_SIZE_MASK_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x270 + ((winNum) * 4))) ++#define XOR_HIGH_ADDR_REMAP_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x290 + ((winNum) * 4))) ++ ++/* XOR Engine [0..1] Window Control Registers (XExWCR) */ ++#define XEXWCR_WIN_EN_OFFS(winNum) (winNum) ++#define XEXWCR_WIN_EN_MASK(winNum) (1 << (XEXWCR_WIN_EN_OFFS(winNum))) ++#define XEXWCR_WIN_EN_ENABLE(winNum) (1 << (XEXWCR_WIN_EN_OFFS(winNum))) ++#define XEXWCR_WIN_EN_DISABLE(winNum) (0 << (XEXWCR_WIN_EN_OFFS(winNum))) ++ ++#define XEXWCR_WIN_ACC_OFFS(winNum) ((2 * winNum) + 16) ++#define XEXWCR_WIN_ACC_MASK(winNum) (3 << (XEXWCR_WIN_ACC_OFFS(winNum))) ++#define XEXWCR_WIN_ACC_NO_ACC(winNum) (0 << (XEXWCR_WIN_ACC_OFFS(winNum))) ++#define XEXWCR_WIN_ACC_RO(winNum) (1 << (XEXWCR_WIN_ACC_OFFS(winNum))) ++#define XEXWCR_WIN_ACC_RW(winNum) (3 << (XEXWCR_WIN_ACC_OFFS(winNum))) ++ ++/* XOR Engine Base Address Registers (XEBARx) */ ++#define XEBARX_TARGET_OFFS (0) ++#define XEBARX_TARGET_MASK (0xF << XEBARX_TARGET_OFFS) ++#define XEBARX_ATTR_OFFS (8) ++#define XEBARX_ATTR_MASK (0xFF << XEBARX_ATTR_OFFS) ++#define XEBARX_BASE_OFFS (16) ++#define XEBARX_BASE_MASK (0xFFFF << XEBARX_BASE_OFFS) ++ ++/* XOR Engine Size Mask Registers (XESMRx) */ ++#define XESMRX_SIZE_MASK_OFFS (16) ++#define XESMRX_SIZE_MASK_MASK (0xFFFF << XESMRX_SIZE_MASK_OFFS) ++ ++/* XOR Engine High Address Remap Register (XEHARRx1) */ ++#define XEHARRX_REMAP_OFFS (0) ++#define XEHARRX_REMAP_MASK (0xFFFFFFFF << XEHARRX_REMAP_OFFS) ++ ++typedef struct _mvXorDecWin ++{ ++ MV_TARGET target; ++ MV_ADDR_WIN addrWin; /* An address window*/ ++ MV_BOOL enable; /* Address decode window is enabled/disabled */ ++ ++}MV_XOR_DEC_WIN; ++ ++MV_STATUS mvXorInit (MV_VOID); ++MV_STATUS mvXorTargetWinSet(MV_U32 unit, MV_U32 winNum, ++ MV_XOR_DEC_WIN *pAddrDecWin); ++MV_STATUS mvXorTargetWinGet(MV_U32 unit, MV_U32 winNum, ++ MV_XOR_DEC_WIN *pAddrDecWin); ++MV_STATUS mvXorTargetWinEnable(MV_U32 unit, ++ MV_U32 winNum, MV_BOOL enable); ++MV_STATUS mvXorProtWinSet (MV_U32 unit,MV_U32 chan, MV_U32 winNum, MV_BOOL access, ++ MV_BOOL write); ++MV_STATUS mvXorPciRemap(MV_U32 unit, MV_U32 winNum, MV_U32 addrHigh); ++ ++MV_VOID mvXorAddrDecShow(MV_VOID); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,75 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#include "device/mvDevice.h" ++ ++/* defines */ ++#ifdef MV_DEBUG ++ #define DB(x) x ++#else ++ #define DB(x) ++#endif ++ ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,74 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvDeviceH ++#define __INCmvDeviceH ++ ++#include "mvCommon.h" ++#include "mvOs.h" ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++#include "device/mvDeviceRegs.h" ++ ++ ++#endif /* #ifndef __INCmvDeviceH */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDeviceRegs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDeviceRegs.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDeviceRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDeviceRegs.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,101 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvDeviceRegsH ++#define __INCmvDeviceRegsH ++ ++#ifndef MV_ASMLANGUAGE ++#include "ctrlEnv/mvCtrlEnvLib.h" ++/* This enumerator describes the Marvell controller possible devices that */ ++/* can be connected to its device interface. */ ++typedef enum _mvDevice ++{ ++#if defined(MV_INCLUDE_DEVICE_CS0) ++ DEV_CS0 = 0, /* Device connected to dev CS[0] */ ++#endif ++#if defined(MV_INCLUDE_DEVICE_CS1) ++ DEV_CS1 = 1, /* Device connected to dev CS[1] */ ++#endif ++#if defined(MV_INCLUDE_DEVICE_CS2) ++ DEV_CS2 = 2, /* Device connected to dev CS[2] */ ++#endif ++#if defined(MV_INCLUDE_DEVICE_CS3) ++ DEV_CS3 = 3, /* Device connected to dev CS[2] */ ++#endif ++#if defined(MV_INCLUDE_DEVICE_CS4) ++ DEV_CS4 = 4, /* Device connected to BOOT dev */ ++#endif ++ MV_DEV_MAX_CS = MV_DEVICE_MAX_CS ++}MV_DEVICE; ++ ++ ++#endif /* MV_ASMLANGUAGE */ ++ ++ ++#define NAND_CTRL_REG 0x10470 ++ ++#define NAND_ACTCEBOOT_BIT BIT1 ++ ++ ++#endif /* #ifndef __INCmvDeviceRegsH */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/mvCompVer.txt linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/mvCompVer.txt +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/mvCompVer.txt 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/kw_family/mvCompVer.txt 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,4 @@ ++Global HAL Version: FEROCEON_HAL_3_1_7 ++Unit HAL Version: 3.1.5 ++Description: This component includes an implementation of the unit HAL drivers ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,211 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++*******************************************************************************/ ++/******************************************************************************* ++* mvOsCpuArchLib.c - Marvell CPU architecture library ++* ++* DESCRIPTION: ++* This library introduce Marvell API for OS dependent CPU architecture ++* APIs. This library introduce single CPU architecture services APKI ++* cross OS. ++* ++* DEPENDENCIES: ++* None. ++* ++*******************************************************************************/ ++ ++/* includes */ ++#include ++#include "mvOs.h" ++ ++static MV_U32 read_p15_c0 (void); ++ ++/* defines */ ++#define ARM_ID_REVISION_OFFS 0 ++#define ARM_ID_REVISION_MASK (0xf << ARM_ID_REVISION_OFFS) ++ ++#define ARM_ID_PART_NUM_OFFS 4 ++#define ARM_ID_PART_NUM_MASK (0xfff << ARM_ID_PART_NUM_OFFS) ++ ++#define ARM_ID_ARCH_OFFS 16 ++#define ARM_ID_ARCH_MASK (0xf << ARM_ID_ARCH_OFFS) ++ ++#define ARM_ID_VAR_OFFS 20 ++#define ARM_ID_VAR_MASK (0xf << ARM_ID_VAR_OFFS) ++ ++#define ARM_ID_ASCII_OFFS 24 ++#define ARM_ID_ASCII_MASK (0xff << ARM_ID_ASCII_OFFS) ++ ++ ++ ++void* mvOsIoCachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, ++ MV_U32 *memHandle) ++{ ++ void *p = kmalloc( size, GFP_KERNEL ); ++ *pPhyAddr = pci_map_single( osHandle, p, 0, PCI_DMA_BIDIRECTIONAL ); ++ return p; ++} ++void* mvOsIoUncachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, ++ MV_U32 *memHandle) ++{ ++ return pci_alloc_consistent( osHandle, size, (dma_addr_t *)pPhyAddr ); ++} ++ ++void mvOsIoUncachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, ++ MV_U32 memHandle) ++{ ++ return pci_free_consistent( osHandle, size, pVirtAddr, (dma_addr_t)phyAddr ); ++} ++ ++void mvOsIoCachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, ++ MV_U32 memHandle ) ++{ ++ return kfree( pVirtAddr ); ++} ++ ++int mvOsRand(void) ++{ ++ int rand; ++ get_random_bytes(&rand, sizeof(rand) ); ++ return rand; ++} ++ ++/******************************************************************************* ++* mvOsCpuVerGet() - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit CPU Revision ++* ++*******************************************************************************/ ++MV_U32 mvOsCpuRevGet( MV_VOID ) ++{ ++ return ((read_p15_c0() & ARM_ID_REVISION_MASK ) >> ARM_ID_REVISION_OFFS); ++} ++/******************************************************************************* ++* mvOsCpuPartGet() - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit CPU Part number ++* ++*******************************************************************************/ ++MV_U32 mvOsCpuPartGet( MV_VOID ) ++{ ++ return ((read_p15_c0() & ARM_ID_PART_NUM_MASK ) >> ARM_ID_PART_NUM_OFFS); ++} ++/******************************************************************************* ++* mvOsCpuArchGet() - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit CPU Architicture number ++* ++*******************************************************************************/ ++MV_U32 mvOsCpuArchGet( MV_VOID ) ++{ ++ return ((read_p15_c0() & ARM_ID_ARCH_MASK ) >> ARM_ID_ARCH_OFFS); ++} ++/******************************************************************************* ++* mvOsCpuVarGet() - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit CPU Variant number ++* ++*******************************************************************************/ ++MV_U32 mvOsCpuVarGet( MV_VOID ) ++{ ++ return ((read_p15_c0() & ARM_ID_VAR_MASK ) >> ARM_ID_VAR_OFFS); ++} ++/******************************************************************************* ++* mvOsCpuAsciiGet() - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit CPU Variant number ++* ++*******************************************************************************/ ++MV_U32 mvOsCpuAsciiGet( MV_VOID ) ++{ ++ return ((read_p15_c0() & ARM_ID_ASCII_MASK ) >> ARM_ID_ASCII_OFFS); ++} ++ ++ ++ ++/* ++static unsigned long read_p15_c0 (void) ++*/ ++/* read co-processor 15, register #0 (ID register) */ ++static MV_U32 read_p15_c0 (void) ++{ ++ MV_U32 value; ++ ++ __asm__ __volatile__( ++ "mrc p15, 0, %0, c0, c0, 0 @ read control reg\n" ++ : "=r" (value) ++ : ++ : "memory"); ++ ++ return value; ++} ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,423 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++*******************************************************************************/ ++#ifndef _MV_OS_LNX_H_ ++#define _MV_OS_LNX_H_ ++ ++ ++#ifdef __KERNEL__ ++/* for kernel space */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "dbg-trace.h" ++ ++extern void mv_early_printk(char *fmt,...); ++ ++#define MV_ASM __asm__ __volatile__ ++#define INLINE inline ++#define MV_TRC_REC TRC_REC ++#define mvOsPrintf printk ++#define mvOsEarlyPrintf mv_early_printk ++#define mvOsOutput printk ++#define mvOsSPrintf sprintf ++#define mvOsMalloc(_size_) kmalloc(_size_,GFP_ATOMIC) ++#define mvOsFree kfree ++#define mvOsMemcpy memcpy ++#define mvOsSleep(_mils_) mdelay(_mils_) ++#define mvOsTaskLock() ++#define mvOsTaskUnlock() ++#define strtol simple_strtoul ++#define mvOsDelay(x) mdelay(x) ++#define mvOsUDelay(x) udelay(x) ++#define mvCopyFromOs copy_from_user ++#define mvCopyToOs copy_to_user ++ ++ ++#include "mvTypes.h" ++#include "mvCommon.h" ++ ++#ifdef MV_NDEBUG ++#define mvOsAssert(cond) ++#else ++#define mvOsAssert(cond) { do { if(!(cond)) { BUG(); } }while(0); } ++#endif /* MV_NDEBUG */ ++ ++#else /* __KERNEL__ */ ++ ++/* for user space applications */ ++#include ++#include ++#include ++#include ++ ++#define INLINE inline ++#define mvOsPrintf printf ++#define mvOsOutput printf ++#define mvOsMalloc(_size_) malloc(_size_) ++#define mvOsFree free ++#define mvOsAssert(cond) assert(cond) ++ ++#endif /* __KERNEL__ */ ++#define mvOsIoVirtToPhy(pDev, pVirtAddr) \ ++ pci_map_single( (pDev), (pVirtAddr), 0, PCI_DMA_BIDIRECTIONAL ) ++ ++#define mvOsCacheClear(pDev, p, size ) \ ++ pci_map_single( (pDev), (p), (size), PCI_DMA_BIDIRECTIONAL) ++ ++#define mvOsCacheFlush(pDev, p, size ) \ ++ pci_map_single( (pDev), (p), (size), PCI_DMA_TODEVICE) ++ ++#define mvOsCacheInvalidate(pDev, p, size) \ ++ pci_map_single( (pDev), (p), (size), PCI_DMA_FROMDEVICE ) ++ ++#define mvOsCacheUnmap(pDev, phys, size) \ ++ pci_unmap_single( (pDev), (dma_addr_t)(phys), (size), PCI_DMA_FROMDEVICE ) ++ ++ ++#define CPU_PHY_MEM(x) (MV_U32)x ++#define CPU_MEMIO_CACHED_ADDR(x) (void*)x ++#define CPU_MEMIO_UNCACHED_ADDR(x) (void*)x ++ ++ ++/* CPU architecture dependent 32, 16, 8 bit read/write IO addresses */ ++#define MV_MEMIO32_WRITE(addr, data) \ ++ ((*((volatile unsigned int*)(addr))) = ((unsigned int)(data))) ++ ++#define MV_MEMIO32_READ(addr) \ ++ ((*((volatile unsigned int*)(addr)))) ++ ++#define MV_MEMIO16_WRITE(addr, data) \ ++ ((*((volatile unsigned short*)(addr))) = ((unsigned short)(data))) ++ ++#define MV_MEMIO16_READ(addr) \ ++ ((*((volatile unsigned short*)(addr)))) ++ ++#define MV_MEMIO8_WRITE(addr, data) \ ++ ((*((volatile unsigned char*)(addr))) = ((unsigned char)(data))) ++ ++#define MV_MEMIO8_READ(addr) \ ++ ((*((volatile unsigned char*)(addr)))) ++ ++ ++/* No Fast Swap implementation (in assembler) for ARM */ ++#define MV_32BIT_LE_FAST(val) MV_32BIT_LE(val) ++#define MV_16BIT_LE_FAST(val) MV_16BIT_LE(val) ++#define MV_32BIT_BE_FAST(val) MV_32BIT_BE(val) ++#define MV_16BIT_BE_FAST(val) MV_16BIT_BE(val) ++ ++/* 32 and 16 bit read/write in big/little endian mode */ ++ ++/* 16bit write in little endian mode */ ++#define MV_MEMIO_LE16_WRITE(addr, data) \ ++ MV_MEMIO16_WRITE(addr, MV_16BIT_LE_FAST(data)) ++ ++/* 16bit read in little endian mode */ ++static __inline MV_U16 MV_MEMIO_LE16_READ(MV_U32 addr) ++{ ++ MV_U16 data; ++ ++ data= (MV_U16)MV_MEMIO16_READ(addr); ++ ++ return (MV_U16)MV_16BIT_LE_FAST(data); ++} ++ ++/* 32bit write in little endian mode */ ++#define MV_MEMIO_LE32_WRITE(addr, data) \ ++ MV_MEMIO32_WRITE(addr, MV_32BIT_LE_FAST(data)) ++ ++/* 32bit read in little endian mode */ ++static __inline MV_U32 MV_MEMIO_LE32_READ(MV_U32 addr) ++{ ++ MV_U32 data; ++ ++ data= (MV_U32)MV_MEMIO32_READ(addr); ++ ++ return (MV_U32)MV_32BIT_LE_FAST(data); ++} ++ ++static __inline void mvOsBCopy(char* srcAddr, char* dstAddr, int byteCount) ++{ ++ while(byteCount != 0) ++ { ++ *dstAddr = *srcAddr; ++ dstAddr++; ++ srcAddr++; ++ byteCount--; ++ } ++} ++ ++static INLINE MV_U64 mvOsDivMod64(MV_U64 divided, MV_U64 divisor, MV_U64* modulu) ++{ ++ MV_U64 division = 0; ++ ++ if(divisor == 1) ++ return divided; ++ ++ while(divided >= divisor) ++ { ++ division++; ++ divided -= divisor; ++ } ++ if (modulu != NULL) ++ *modulu = divided; ++ ++ return division; ++} ++ ++#if defined(MV_BRIDGE_SYNC_REORDER) ++extern MV_U32 *mvUncachedParam; ++ ++static __inline void mvOsBridgeReorderWA(void) ++{ ++ volatile MV_U32 val = 0; ++ ++ val = mvUncachedParam[0]; ++} ++#endif ++ ++ ++/* Flash APIs */ ++#define MV_FL_8_READ MV_MEMIO8_READ ++#define MV_FL_16_READ MV_MEMIO_LE16_READ ++#define MV_FL_32_READ MV_MEMIO_LE32_READ ++#define MV_FL_8_DATA_READ MV_MEMIO8_READ ++#define MV_FL_16_DATA_READ MV_MEMIO16_READ ++#define MV_FL_32_DATA_READ MV_MEMIO32_READ ++#define MV_FL_8_WRITE MV_MEMIO8_WRITE ++#define MV_FL_16_WRITE MV_MEMIO_LE16_WRITE ++#define MV_FL_32_WRITE MV_MEMIO_LE32_WRITE ++#define MV_FL_8_DATA_WRITE MV_MEMIO8_WRITE ++#define MV_FL_16_DATA_WRITE MV_MEMIO16_WRITE ++#define MV_FL_32_DATA_WRITE MV_MEMIO32_WRITE ++ ++ ++/* CPU cache information */ ++#define CPU_I_CACHE_LINE_SIZE 32 /* 2do: replace 32 with linux core macro */ ++#define CPU_D_CACHE_LINE_SIZE 32 /* 2do: replace 32 with linux core macro */ ++ ++#ifdef CONFIG_L2_CACHE_ENABLE ++/* Data cache flush one line */ ++#define mvOsCacheLineFlushInv(handle, addr) \ ++{ \ ++ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c14, 1" : : "r" (addr));\ ++ __asm__ __volatile__ ("mcr p15, 1, %0, c15, c10, 1" : : "r" (addr));\ ++ __asm__ __volatile__ ("mcr p15, 0, r0, c7, c10, 4"); \ ++} ++ ++#else ++ ++/* Data cache flush one line */ ++#define mvOsCacheLineFlushInv(handle, addr) \ ++{ \ ++ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c14, 1" : : "r" (addr));\ ++ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" : : "r" (addr)); \ ++} ++#endif ++ ++#ifdef CONFIG_L2_CACHE_ENABLE ++#define mvOsCacheLineInv(handle,addr) \ ++{ \ ++ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c6, 1" : : "r" (addr)); \ ++ __asm__ __volatile__ ("mcr p15, 1, %0, c15, c11, 1" : : "r" (addr)); \ ++} ++#else ++#define mvOsCacheLineInv(handle,addr) \ ++{ \ ++ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c6, 1" : : "r" (addr)); \ ++} ++#endif ++ ++#ifdef CONFIG_L2_CACHE_ENABLE ++/* Data cache flush one line */ ++#define mvOsCacheLineFlush(handle, addr) \ ++{ \ ++ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 1" : : "r" (addr));\ ++ __asm__ __volatile__ ("mcr p15, 1, %0, c15, c9, 1" : : "r" (addr));\ ++ __asm__ __volatile__ ("mcr p15, 0, r0, c7, c10, 4"); \ ++} ++ ++#else ++/* Data cache flush one line */ ++#define mvOsCacheLineFlush(handle, addr) \ ++{ \ ++ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 1" : : "r" (addr));\ ++ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" : : "r" (addr)); \ ++} ++#endif ++ ++static __inline void mvOsPrefetch(const void *ptr) ++{ ++#ifdef CONFIG_USE_DSP ++ __asm__ __volatile__( ++ "pld\t%0" ++ : ++ : "o" (*(char *)ptr) ++ : "cc"); ++#else ++ return; ++#endif ++} ++ ++ ++/* Flush CPU pipe */ ++#define CPU_PIPE_FLUSH ++ ++ ++ ++ ++ ++/* register manipulations */ ++ ++/****************************************************************************** ++* This debug function enable the write of each register that u-boot access to ++* to an array in the DRAM, the function record only MV_REG_WRITE access. ++* The function could not be operate when booting from flash. ++* In order to print the array we use the printreg command. ++******************************************************************************/ ++/* #define REG_DEBUG */ ++#if defined(REG_DEBUG) ++extern int reg_arry[2048][2]; ++extern int reg_arry_index; ++#endif ++ ++/* Marvell controller register read/write macros */ ++#define MV_REG_VALUE(offset) \ ++ (MV_MEMIO32_READ((INTER_REGS_BASE | (offset)))) ++ ++#define MV_REG_READ(offset) \ ++ (MV_MEMIO_LE32_READ(INTER_REGS_BASE | (offset))) ++ ++#if defined(REG_DEBUG) ++#define MV_REG_WRITE(offset, val) \ ++ MV_MEMIO_LE32_WRITE((INTER_REGS_BASE | (offset)), (val)); \ ++ { \ ++ reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\ ++ reg_arry[reg_arry_index][1] = (val);\ ++ reg_arry_index++;\ ++ } ++#else ++#define MV_REG_WRITE(offset, val) \ ++ MV_MEMIO_LE32_WRITE((INTER_REGS_BASE | (offset)), (val)); ++#endif ++ ++#define MV_REG_BYTE_READ(offset) \ ++ (MV_MEMIO8_READ((INTER_REGS_BASE | (offset)))) ++ ++#if defined(REG_DEBUG) ++#define MV_REG_BYTE_WRITE(offset, val) \ ++ MV_MEMIO8_WRITE((INTER_REGS_BASE | (offset)), (val)); \ ++ { \ ++ reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\ ++ reg_arry[reg_arry_index][1] = (val);\ ++ reg_arry_index++;\ ++ } ++#else ++#define MV_REG_BYTE_WRITE(offset, val) \ ++ MV_MEMIO8_WRITE((INTER_REGS_BASE | (offset)), (val)) ++#endif ++ ++#if defined(REG_DEBUG) ++#define MV_REG_BIT_SET(offset, bitMask) \ ++ (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ ++ (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) | \ ++ MV_32BIT_LE_FAST(bitMask)))); \ ++ { \ ++ reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\ ++ reg_arry[reg_arry_index][1] = (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)));\ ++ reg_arry_index++;\ ++ } ++#else ++#define MV_REG_BIT_SET(offset, bitMask) \ ++ (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ ++ (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) | \ ++ MV_32BIT_LE_FAST(bitMask)))) ++#endif ++ ++#if defined(REG_DEBUG) ++#define MV_REG_BIT_RESET(offset,bitMask) \ ++ (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ ++ (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) & \ ++ MV_32BIT_LE_FAST(~bitMask)))); \ ++ { \ ++ reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\ ++ reg_arry[reg_arry_index][1] = (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)));\ ++ reg_arry_index++;\ ++ } ++#else ++#define MV_REG_BIT_RESET(offset,bitMask) \ ++ (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ ++ (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) & \ ++ MV_32BIT_LE_FAST(~bitMask)))) ++#endif ++ ++ ++ ++/* ARM architecture APIs */ ++MV_U32 mvOsCpuRevGet (MV_VOID); ++MV_U32 mvOsCpuPartGet (MV_VOID); ++MV_U32 mvOsCpuArchGet (MV_VOID); ++MV_U32 mvOsCpuVarGet (MV_VOID); ++MV_U32 mvOsCpuAsciiGet (MV_VOID); ++ ++/* Other APIs */ ++void* mvOsIoCachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, MV_U32 *memHandle); ++void* mvOsIoUncachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, MV_U32 *memHandle ); ++void mvOsIoUncachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, MV_U32 memHandle ); ++void mvOsIoCachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, MV_U32 memHandle ); ++int mvOsRand(void); ++ ++#endif /* _MV_OS_LNX_H_ */ ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOsSata.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/linux_oss/mvOsSata.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOsSata.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/linux_oss/mvOsSata.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,158 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++*******************************************************************************/ ++/******************************************************************************* ++* mvOsLinux.h - O.S. interface header file for Linux ++* ++* DESCRIPTION: ++* This header file contains OS dependent definition under Linux ++* ++* DEPENDENCIES: ++* Linux kernel header files. ++* ++* FILE REVISION NUMBER: ++* $Revision: 1.1 $ ++*******************************************************************************/ ++ ++#ifndef __INCmvOsLinuxh ++#define __INCmvOsLinuxh ++ ++/* Includes */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include "mvOs.h" ++ ++ ++/* Definitions */ ++#define MV_DEFAULT_QUEUE_DEPTH 2 ++#define MV_SATA_SUPPORT_EDMA_SINGLE_DATA_REGION ++#define MV_SATA_SUPPORT_GEN2E_128_QUEUE_LEN ++ ++#ifdef CONFIG_MV88F6082 ++ #define MV_SATA_OVERRIDE_SW_QUEUE_SIZE ++ #define MV_SATA_REQUESTED_SW_QUEUE_SIZE 2 ++ #undef MV_SATA_SUPPORT_GEN2E_128_QUEUE_LEN ++#endif ++ ++/* System dependent macro for flushing CPU write cache */ ++#if defined (MV_BRIDGE_SYNC_REORDER) ++#define MV_CPU_WRITE_BUFFER_FLUSH() do { \ ++ wmb(); \ ++ mvOsBridgeReorderWA(); \ ++ } while (0) ++#else ++#define MV_CPU_WRITE_BUFFER_FLUSH() wmb() ++#endif /* CONFIG_MV78XX0 */ ++ ++/* System dependent little endian from / to CPU conversions */ ++#define MV_CPU_TO_LE16(x) cpu_to_le16(x) ++#define MV_CPU_TO_LE32(x) cpu_to_le32(x) ++ ++#define MV_LE16_TO_CPU(x) le16_to_cpu(x) ++#define MV_LE32_TO_CPU(x) le32_to_cpu(x) ++ ++#ifdef __BIG_ENDIAN_BITFIELD ++#define MV_BIG_ENDIAN_BITFIELD ++#endif ++ ++/* System dependent register read / write in byte/word/dword variants */ ++#define MV_REG_WRITE_BYTE(base, offset, val) writeb(val, base + offset) ++#define MV_REG_WRITE_WORD(base, offset, val) writew(val, base + offset) ++#define MV_REG_WRITE_DWORD(base, offset, val) writel(val, base + offset) ++#define MV_REG_READ_BYTE(base, offset) readb(base + offset) ++#define MV_REG_READ_WORD(base, offset) readw(base + offset) ++#define MV_REG_READ_DWORD(base, offset) readl(base + offset) ++ ++ ++/* Typedefs */ ++ ++/* System dependant typedefs */ ++typedef void *MV_VOID_PTR; ++typedef u32 *MV_U32_PTR; ++typedef u16 *MV_U16_PTR; ++typedef u8 *MV_U8_PTR; ++typedef char *MV_CHAR_PTR; ++typedef void *MV_BUS_ADDR_T; ++typedef unsigned long MV_CPU_FLAGS; ++ ++ ++/* Structures */ ++/* System dependent structure */ ++typedef struct mvOsSemaphore ++{ ++ int notUsed; ++} MV_OS_SEMAPHORE; ++ ++ ++/* Functions (User implemented)*/ ++ ++/* Semaphore init, take and release */ ++#define mvOsSemInit(x) MV_TRUE ++#define mvOsSemTake(x) ++#define mvOsSemRelease(x) ++ ++/* Interrupt masking and unmasking functions */ ++MV_CPU_FLAGS mvOsSaveFlagsAndMaskCPUInterrupts(MV_VOID); ++MV_VOID mvOsRestoreFlags(MV_CPU_FLAGS); ++ ++/* Delay function in micro seconds resolution */ ++void mvMicroSecondsDelay(MV_VOID_PTR, MV_U32); ++ ++/* Typedefs */ ++typedef enum mvBoolean ++{ ++ MV_SFALSE, MV_STRUE ++} MV_BOOLEAN; ++ ++/* System logging function */ ++#include "mvLog.h" ++/* Enable READ/WRITE Long SCSI command only when driver is compiled for debugging */ ++#ifdef MV_LOGGER ++#define MV_SATA_SUPPORT_READ_WRITE_LONG ++#endif ++ ++#define MV_IAL_LOG_ID 3 ++ ++#endif /* __INCmvOsLinuxh */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mvSysHwConfig.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mvSysHwConfig.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mvSysHwConfig.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mvSysHwConfig.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,375 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++ ++*******************************************************************************/ ++/******************************************************************************* ++* mvSysHwCfg.h - Marvell system HW configuration file ++* ++* DESCRIPTION: ++* None. ++* ++* DEPENDENCIES: ++* None. ++* ++*******************************************************************************/ ++ ++#ifndef __INCmvSysHwConfigh ++#define __INCmvSysHwConfigh ++ ++#include "../../../../include/linux/autoconf.h" ++ ++#define CONFIG_MARVELL 1 ++ ++/* includes */ ++#define _1K 0x00000400 ++#define _4K 0x00001000 ++#define _8K 0x00002000 ++#define _16K 0x00004000 ++#define _32K 0x00008000 ++#define _64K 0x00010000 ++#define _128K 0x00020000 ++#define _256K 0x00040000 ++#define _512K 0x00080000 ++ ++#define _1M 0x00100000 ++#define _2M 0x00200000 ++#define _4M 0x00400000 ++#define _8M 0x00800000 ++#define _16M 0x01000000 ++#define _32M 0x02000000 ++#define _64M 0x04000000 ++#define _128M 0x08000000 ++#define _256M 0x10000000 ++#define _512M 0x20000000 ++ ++#define _1G 0x40000000 ++#define _2G 0x80000000 ++ ++/****************************************/ ++/* Soc supporeted Units definitions */ ++/****************************************/ ++ ++#ifdef CONFIG_MV_INCLUDE_PEX ++#define MV_INCLUDE_PEX ++#endif ++#ifdef CONFIG_MV_INCLUDE_TWSI ++#define MV_INCLUDE_TWSI ++#endif ++#ifdef CONFIG_MV_INCLUDE_CESA ++#define MV_INCLUDE_CESA ++#endif ++#ifdef CONFIG_MV_INCLUDE_GIG_ETH ++#define MV_INCLUDE_GIG_ETH ++#endif ++#ifdef CONFIG_MV_INCLUDE_INTEG_SATA ++#define MV_INCLUDE_INTEG_SATA ++#define MV_INCLUDE_SATA ++#endif ++#ifdef CONFIG_MV_INCLUDE_USB ++#define MV_INCLUDE_USB ++#define MV_USB_VOLTAGE_FIX ++#endif ++#ifdef CONFIG_MV_INCLUDE_NAND ++#define MV_INCLUDE_NAND ++#endif ++#ifdef CONFIG_MV_INCLUDE_TDM ++#define MV_INCLUDE_TDM ++#endif ++#ifdef CONFIG_MV_INCLUDE_XOR ++#define MV_INCLUDE_XOR ++#endif ++#ifdef CONFIG_MV_INCLUDE_TWSI ++#define MV_INCLUDE_TWSI ++#endif ++#ifdef CONFIG_MV_INCLUDE_UART ++#define MV_INCLUDE_UART ++#endif ++#ifdef CONFIG_MV_INCLUDE_SPI ++#define MV_INCLUDE_SPI ++#endif ++#ifdef CONFIG_MV_INCLUDE_SFLASH_MTD ++#define MV_INCLUDE_SFLASH_MTD ++#endif ++#ifdef CONFIG_MV_INCLUDE_AUDIO ++#define MV_INCLUDE_AUDIO ++#endif ++#ifdef CONFIG_MV_INCLUDE_TS ++#define MV_INCLUDE_TS ++#endif ++#ifdef CONFIG_MV_INCLUDE_SDIO ++#define MV_INCLUDE_SDIO ++#endif ++ ++ ++/* NAND flash stuff */ ++#ifdef CONFIG_MV_NAND_BOOT ++#define MV_NAND_BOOT ++#endif ++#ifdef CONFIG_MV_NAND ++#define MV_NAND ++#endif ++ ++/* SPI flash stuff */ ++#ifdef CONFIG_MV_SPI_BOOT ++#define MV_SPI_BOOT ++#endif ++ ++ ++/****************************************************************/ ++/************* General configuration ********************/ ++/****************************************************************/ ++ ++/* Enable Clock Power Control */ ++#define MV_INCLUDE_CLK_PWR_CNTRL ++ ++/* Disable the DEVICE BAR in the PEX */ ++#define MV_DISABLE_PEX_DEVICE_BAR ++ ++/* Allow the usage of early printings during initialization */ ++#define MV_INCLUDE_EARLY_PRINTK ++ ++/****************************************************************/ ++/************* NFP configuration ********************************/ ++/****************************************************************/ ++#define MV_NFP_SEC_Q_SIZE 64 ++#define MV_NFP_SEC_REQ_Q_SIZE 1000 ++ ++ ++ ++/****************************************************************/ ++/************* CESA configuration ********************/ ++/****************************************************************/ ++ ++#ifdef MV_INCLUDE_CESA ++ ++#define MV_CESA_MAX_CHAN 4 ++ ++/* Use 2K of SRAM */ ++#define MV_CESA_MAX_BUF_SIZE 1600 ++ ++#endif /* MV_INCLUDE_CESA */ ++ ++#if defined(CONFIG_MV_INCLUDE_GIG_ETH) ++ ++#ifdef CONFIG_MV_NFP_STATS ++#define MV_FP_STATISTICS ++#else ++#undef MV_FP_STATISTICS ++#endif ++/* Default configuration for SKB_REUSE: 0 - Disabled, 1 - Enabled */ ++#define MV_ETH_SKB_REUSE_DEFAULT 1 ++/* Default configuration for TX_EN workaround: 0 - Disabled, 1 - Enabled */ ++#define MV_ETH_TX_EN_DEFAULT 0 ++ ++/* un-comment if you want to perform tx_done from within the poll function */ ++/* #define ETH_TX_DONE_ISR */ ++ ++/* put descriptors in uncached memory */ ++/* #define ETH_DESCR_UNCACHED */ ++ ++/* Descriptors location: DRAM/internal-SRAM */ ++#define ETH_DESCR_IN_SDRAM ++#undef ETH_DESCR_IN_SRAM /* No integrated SRAM in 88Fxx81 devices */ ++ ++#if defined(ETH_DESCR_IN_SRAM) ++#if defined(ETH_DESCR_UNCACHED) ++ #define ETH_DESCR_CONFIG_STR "Uncached descriptors in integrated SRAM" ++#else ++ #define ETH_DESCR_CONFIG_STR "Cached descriptors in integrated SRAM" ++#endif ++#elif defined(ETH_DESCR_IN_SDRAM) ++#if defined(ETH_DESCR_UNCACHED) ++ #define ETH_DESCR_CONFIG_STR "Uncached descriptors in DRAM" ++#else ++ #define ETH_DESCR_CONFIG_STR "Cached descriptors in DRAM" ++#endif ++#else ++ #error "Ethernet descriptors location undefined" ++#endif /* ETH_DESCR_IN_SRAM or ETH_DESCR_IN_SDRAM*/ ++ ++/* SW Sync-Barrier: not relevant for 88fxx81*/ ++/* Reasnable to define this macro when descriptors in SRAM and buffers in DRAM */ ++/* In RX the CPU theoretically might see himself as the descriptor owner, */ ++/* although the buffer hadn't been written to DRAM yet. Performance cost. */ ++/* #define INCLUDE_SYNC_BARR */ ++ ++/* Buffers cache coherency method (buffers in DRAM) */ ++#ifndef MV_CACHE_COHER_SW ++/* Taken from mvCommon.h */ ++/* Memory uncached, HW or SW cache coherency is not needed */ ++#define MV_UNCACHED 0 ++/* Memory cached, HW cache coherency supported in WriteThrough mode */ ++#define MV_CACHE_COHER_HW_WT 1 ++/* Memory cached, HW cache coherency supported in WriteBack mode */ ++#define MV_CACHE_COHER_HW_WB 2 ++/* Memory cached, No HW cache coherency, Cache coherency must be in SW */ ++#define MV_CACHE_COHER_SW 3 ++ ++#endif ++ ++/* DRAM cache coherency configuration */ ++#define MV_CACHE_COHERENCY MV_CACHE_COHER_SW ++ ++ ++#define ETHER_DRAM_COHER MV_CACHE_COHER_SW /* No HW coherency in 88Fxx81 devices */ ++ ++#if (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WB) ++ #define ETH_SDRAM_CONFIG_STR "DRAM HW cache coherency (write-back)" ++#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WT) ++ #define ETH_SDRAM_CONFIG_STR "DRAM HW cache coherency (write-through)" ++#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) ++ #define ETH_SDRAM_CONFIG_STR "DRAM SW cache-coherency" ++#elif (ETHER_DRAM_COHER == MV_UNCACHED) ++# define ETH_SDRAM_CONFIG_STR "DRAM uncached" ++#else ++ #error "Ethernet-DRAM undefined" ++#endif /* ETHER_DRAM_COHER */ ++ ++ ++/****************************************************************/ ++/************* Ethernet driver configuration ********************/ ++/****************************************************************/ ++ ++/* port's default queueus */ ++#define ETH_DEF_TXQ 0 ++#define ETH_DEF_RXQ 0 ++ ++#define MV_ETH_RX_Q_NUM CONFIG_MV_ETH_RX_Q_NUM ++#define MV_ETH_TX_Q_NUM CONFIG_MV_ETH_TX_Q_NUM ++ ++/* interrupt coalescing setting */ ++#define ETH_TX_COAL 200 ++#define ETH_RX_COAL 200 ++ ++/* Checksum offloading */ ++#define TX_CSUM_OFFLOAD ++#define RX_CSUM_OFFLOAD ++ ++#endif /* CONFIG_MV_INCLUDE_GIG_ETH */ ++ ++/****************************************************************/ ++/*************** Telephony configuration ************************/ ++/****************************************************************/ ++#if defined(CONFIG_MV_TDM_LINEAR_MODE) ++ #define MV_TDM_LINEAR_MODE ++#elif defined(CONFIG_MV_TDM_ULAW_MODE) ++ #define MV_TDM_ULAW_MODE ++#endif ++ ++#if defined(CONFIG_MV_TDM_5CHANNELS) ++ #define MV_TDM_5CHANNELS ++#endif ++ ++#if defined(CONFIG_MV_TDM_USE_EXTERNAL_PCLK_SOURCE) ++ #define MV_TDM_USE_EXTERNAL_PCLK_SOURCE ++#endif ++ ++/* We use the following registers to store DRAM interface pre configuration */ ++/* auto-detection results */ ++/* IMPORTANT: We are using mask register for that purpose. Before writing */ ++/* to units mask register, make sure main maks register is set to disable */ ++/* all interrupts. */ ++#define DRAM_BUF_REG0 0x30810 /* sdram bank 0 size */ ++#define DRAM_BUF_REG1 0x30820 /* sdram config */ ++#define DRAM_BUF_REG2 0x30830 /* sdram mode */ ++#define DRAM_BUF_REG3 0x308c4 /* dunit control low */ ++#define DRAM_BUF_REG4 0x60a90 /* sdram address control */ ++#define DRAM_BUF_REG5 0x60a94 /* sdram timing control low */ ++#define DRAM_BUF_REG6 0x60a98 /* sdram timing control high */ ++#define DRAM_BUF_REG7 0x60a9c /* sdram ODT control low */ ++#define DRAM_BUF_REG8 0x60b90 /* sdram ODT control high */ ++#define DRAM_BUF_REG9 0x60b94 /* sdram Dunit ODT control */ ++#define DRAM_BUF_REG10 0x60b98 /* sdram Extended Mode */ ++#define DRAM_BUF_REG11 0x60b9c /* sdram Ddr2 Time Low Reg */ ++#define DRAM_BUF_REG12 0x60a00 /* sdram Ddr2 Time High Reg */ ++#define DRAM_BUF_REG13 0x60a04 /* dunit Ctrl High */ ++#define DRAM_BUF_REG14 0x60b00 /* sdram second DIMM exist */ ++ ++/* Following the pre-configuration registers default values restored after */ ++/* auto-detection is done */ ++#define DRAM_BUF_REG_DV 0 ++ ++/* System Mapping */ ++#define SDRAM_CS0_BASE 0x00000000 ++#define SDRAM_CS0_SIZE _256M ++ ++#define SDRAM_CS1_BASE 0x10000000 ++#define SDRAM_CS1_SIZE _256M ++ ++#define SDRAM_CS2_BASE 0x20000000 ++#define SDRAM_CS2_SIZE _256M ++ ++#define SDRAM_CS3_BASE 0x30000000 ++#define SDRAM_CS3_SIZE _256M ++ ++/* PEX */ ++#define PEX0_MEM_BASE 0xe8000000 ++#define PEX0_MEM_SIZE _128M ++ ++#define PEX0_IO_BASE 0xf2000000 ++#define PEX0_IO_SIZE _1M ++ ++/* Device Chip Selects */ ++#define NFLASH_CS_BASE 0xfa000000 ++#define NFLASH_CS_SIZE _2M ++ ++#define SPI_CS_BASE 0xf4000000 ++#define SPI_CS_SIZE _16M ++ ++#define CRYPT_ENG_BASE 0xf0000000 ++#define CRYPT_ENG_SIZE _2M ++ ++#define BOOTDEV_CS_BASE 0xff800000 ++#define BOOTDEV_CS_SIZE _8M ++ ++/* CS2 - BOOTROM */ ++#define DEVICE_CS2_BASE 0xff900000 ++#define DEVICE_CS2_SIZE _1M ++ ++/* PEX Work arround */ ++/* the target we will use for the workarround */ ++#define PEX_CONFIG_RW_WA_TARGET PEX0_MEM ++/*a flag that indicates if we are going to use the ++size and base of the target we using for the workarround ++window */ ++#define PEX_CONFIG_RW_WA_USE_ORIGINAL_WIN_VALUES 1 ++/* if the above flag is 0 then the following values ++will be used for the workarround window base and size, ++otherwise the following defines will be ignored */ ++#define PEX_CONFIG_RW_WA_BASE 0xF3000000 ++#define PEX_CONFIG_RW_WA_SIZE _16M ++ ++/* Internal registers: size is defined in Controllerenvironment */ ++#define INTER_REGS_BASE 0xFEE00000 ++ ++/* DRAM detection stuff */ ++#define MV_DRAM_AUTO_SIZE ++ ++/* Board clock detection */ ++#define TCLK_AUTO_DETECT /* Use Tclk auto detection */ ++#define SYSCLK_AUTO_DETECT /* Use SysClk auto detection */ ++#define PCLCK_AUTO_DETECT /* Use PClk auto detection */ ++#define L2CLK_AUTO_DETECT /* Use L2Clk auto detection */ ++ ++/* PEX-PCI\PCI-PCI Bridge*/ ++#define PCI0_IF_PTP 0 /* Bridge exist on pciIf0*/ ++ ++ ++ ++#endif /* __INCmvSysHwConfigh */ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,376 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#include "mvCntmr.h" ++#include "cpu/mvCpu.h" ++ ++/* defines */ ++#ifdef MV_DEBUG ++ #define DB(x) x ++#else ++ #define DB(x) ++#endif ++ ++extern unsigned int whoAmI(void); ++ ++/******************************************************************************* ++* mvCntmrLoad - ++* ++* DESCRIPTION: ++* Load an init Value to a given counter/timer ++* ++* INPUT: ++* countNum - counter number ++* value - value to be loaded ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess ++*******************************************************************************/ ++MV_STATUS mvCntmrLoad(MV_U32 countNum, MV_U32 value) ++{ ++ if (countNum >= MV_CNTMR_MAX_COUNTER ) ++ { ++ ++ mvOsPrintf(("mvCntmrLoad: Err. Illigal counter number \n")); ++ return MV_BAD_PARAM;; ++ ++ } ++ ++ MV_REG_WRITE(CNTMR_RELOAD_REG(countNum),value); ++ MV_REG_WRITE(CNTMR_VAL_REG(countNum),value); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCntmrRead - ++* ++* DESCRIPTION: ++* Returns the value of the given Counter/Timer ++* ++* INPUT: ++* countNum - counter number ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_U32 counter value ++*******************************************************************************/ ++MV_U32 mvCntmrRead(MV_U32 countNum) ++{ ++ return MV_REG_READ(CNTMR_VAL_REG(countNum)); ++} ++ ++/******************************************************************************* ++* mvCntmrWrite - ++* ++* DESCRIPTION: ++* Returns the value of the given Counter/Timer ++* ++* INPUT: ++* countNum - counter number ++* countVal - value to write ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None ++*******************************************************************************/ ++void mvCntmrWrite(MV_U32 countNum,MV_U32 countVal) ++{ ++ MV_REG_WRITE(CNTMR_VAL_REG(countNum),countVal); ++} ++ ++/******************************************************************************* ++* mvCntmrCtrlSet - ++* ++* DESCRIPTION: ++* Set the Control to a given counter/timer ++* ++* INPUT: ++* countNum - counter number ++* pCtrl - pointer to MV_CNTMR_CTRL structure ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess ++*******************************************************************************/ ++MV_STATUS mvCntmrCtrlSet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl) ++{ ++ MV_U32 cntmrCtrl; ++ ++ if (countNum >= MV_CNTMR_MAX_COUNTER ) ++ { ++ ++ DB(mvOsPrintf(("mvCntmrCtrlSet: Err. Illigal counter number \n"))); ++ return MV_BAD_PARAM;; ++ ++ } ++ ++ /* read control register */ ++ cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG); ++ ++ ++ if (pCtrl->enable) /* enable counter\timer */ ++ { ++ cntmrCtrl |= CTCR_ARM_TIMER_EN(countNum); ++ } ++ else /* disable counter\timer */ ++ { ++ cntmrCtrl &= ~CTCR_ARM_TIMER_EN(countNum); ++ } ++ ++ if ( pCtrl->autoEnable ) /* Auto mode */ ++ { ++ cntmrCtrl |= CTCR_ARM_TIMER_AUTO_EN(countNum); ++ ++ } ++ else /* no auto mode */ ++ { ++ cntmrCtrl &= ~CTCR_ARM_TIMER_AUTO_EN(countNum); ++ } ++ ++ MV_REG_WRITE(CNTMR_CTRL_REG,cntmrCtrl); ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvCntmrCtrlGet - ++* ++* DESCRIPTION: ++* Get the Control value of a given counter/timer ++* ++* INPUT: ++* countNum - counter number ++* pCtrl - pointer to MV_CNTMR_CTRL structure ++* ++* OUTPUT: ++* Counter\Timer control value ++* ++* RETURN: ++* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess ++*******************************************************************************/ ++MV_STATUS mvCntmrCtrlGet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl) ++{ ++ MV_U32 cntmrCtrl; ++ ++ if (countNum >= MV_CNTMR_MAX_COUNTER ) ++ { ++ DB(mvOsPrintf(("mvCntmrCtrlGet: Err. Illigal counter number \n"))); ++ return MV_BAD_PARAM;; ++ } ++ ++ /* read control register */ ++ cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG); ++ ++ /* enable counter\timer */ ++ if (cntmrCtrl & CTCR_ARM_TIMER_EN(countNum)) ++ { ++ pCtrl->enable = MV_TRUE; ++ } ++ else ++ { ++ pCtrl->enable = MV_FALSE; ++ } ++ ++ /* counter mode */ ++ if (cntmrCtrl & CTCR_ARM_TIMER_AUTO_EN(countNum)) ++ { ++ pCtrl->autoEnable = MV_TRUE; ++ } ++ else ++ { ++ pCtrl->autoEnable = MV_FALSE; ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCntmrEnable - ++* ++* DESCRIPTION: ++* Set the Enable-Bit to logic '1' ==> starting the counter ++* ++* INPUT: ++* countNum - counter number ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess ++*******************************************************************************/ ++MV_STATUS mvCntmrEnable(MV_U32 countNum) ++{ ++ MV_U32 cntmrCtrl; ++ ++ if (countNum >= MV_CNTMR_MAX_COUNTER ) ++ { ++ ++ DB(mvOsPrintf(("mvCntmrEnable: Err. Illigal counter number \n"))); ++ return MV_BAD_PARAM;; ++ ++ } ++ ++ /* read control register */ ++ cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG); ++ ++ /* enable counter\timer */ ++ cntmrCtrl |= CTCR_ARM_TIMER_EN(countNum); ++ ++ ++ MV_REG_WRITE(CNTMR_CTRL_REG,cntmrCtrl); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCntmrDisable - ++* ++* DESCRIPTION: ++* Stop the counter/timer running, and returns its Value ++* ++* INPUT: ++* countNum - counter number ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_U32 counter\timer value ++*******************************************************************************/ ++MV_STATUS mvCntmrDisable(MV_U32 countNum) ++{ ++ MV_U32 cntmrCtrl; ++ ++ if (countNum >= MV_CNTMR_MAX_COUNTER ) ++ { ++ ++ DB(mvOsPrintf(("mvCntmrDisable: Err. Illigal counter number \n"))); ++ return MV_BAD_PARAM;; ++ ++ } ++ ++ /* read control register */ ++ cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG); ++ ++ /* disable counter\timer */ ++ cntmrCtrl &= ~CTCR_ARM_TIMER_EN(countNum); ++ ++ MV_REG_WRITE(CNTMR_CTRL_REG,cntmrCtrl); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCntmrStart - ++* ++* DESCRIPTION: ++* Combined all the sub-operations above to one function: Load,setMode,Enable ++* ++* INPUT: ++* countNum - counter number ++* value - value of the counter\timer to be set ++* pCtrl - pointer to MV_CNTMR_CTRL structure ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess ++*******************************************************************************/ ++MV_STATUS mvCntmrStart(MV_U32 countNum, MV_U32 value, ++ MV_CNTMR_CTRL *pCtrl) ++{ ++ ++ if (countNum >= MV_CNTMR_MAX_COUNTER ) ++ { ++ ++ mvOsPrintf(("mvCntmrDisable: Err. Illigal counter number \n")); ++ return MV_BAD_PARAM;; ++ ++ } ++ ++ /* load value onto counter\timer */ ++ mvCntmrLoad(countNum,value); ++ ++ /* set the counter to load in the first time */ ++ mvCntmrWrite(countNum,value); ++ ++ /* set control for timer \ cunter and enable */ ++ mvCntmrCtrlSet(countNum,pCtrl); ++ ++ return MV_OK; ++} ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,121 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvTmrWtdgh ++#define __INCmvTmrWtdgh ++ ++/* includes */ ++#include "mvCommon.h" ++#include "mvOs.h" ++#include "cntmr/mvCntmrRegs.h" ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++ ++ ++/* This enumerator describe counters\watchdog numbers */ ++typedef enum _mvCntmrID ++{ ++ TIMER0 = 0, ++ TIMER1, ++ WATCHDOG, ++ TIMER2, ++ TIMER3, ++}MV_CNTMR_ID; ++ ++ ++/* Counter / Timer control structure */ ++typedef struct _mvCntmrCtrl ++{ ++ MV_BOOL enable; /* enable */ ++ MV_BOOL autoEnable; /* counter/Timer */ ++}MV_CNTMR_CTRL; ++ ++ ++/* Functions */ ++ ++/* Load an init Value to a given counter/timer */ ++MV_STATUS mvCntmrLoad(MV_U32 countNum, MV_U32 value); ++ ++/* Returns the value of the given Counter/Timer */ ++MV_U32 mvCntmrRead(MV_U32 countNum); ++ ++/* Write a value of the given Counter/Timer */ ++void mvCntmrWrite(MV_U32 countNum,MV_U32 countVal); ++ ++/* Set the Control to a given counter/timer */ ++MV_STATUS mvCntmrCtrlSet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl); ++ ++/* Get the value of a given counter/timer */ ++MV_STATUS mvCntmrCtrlGet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl); ++ ++/* Set the Enable-Bit to logic '1' ==> starting the counter. */ ++MV_STATUS mvCntmrEnable(MV_U32 countNum); ++ ++/* Stop the counter/timer running, and returns its Value. */ ++MV_STATUS mvCntmrDisable(MV_U32 countNum); ++ ++/* Combined all the sub-operations above to one function: Load,setMode,Enable */ ++MV_STATUS mvCntmrStart(MV_U32 countNum, MV_U32 value, ++ MV_CNTMR_CTRL *pCtrl); ++ ++#endif /* __INCmvTmrWtdgh */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmrRegs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmrRegs.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmrRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmrRegs.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,121 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvTmrwtdgRegsh ++#define __INCmvTmrwtdgRegsh ++ ++/*******************************************/ ++/* ARM Timers Registers Map */ ++/*******************************************/ ++ ++#define CNTMR_RELOAD_REG(tmrNum) (CNTMR_BASE + 0x10 + (tmrNum)*8 + \ ++ (((tmrNum) <= 3)?0:8)) ++#define CNTMR_VAL_REG(tmrNum) (CNTMR_BASE + 0x14 + (tmrNum)*8 + \ ++ (((tmrNum) <= 3)?0:8)) ++#define CNTMR_CTRL_REG (CNTMR_BASE) ++ ++/*For MV78XX0*/ ++#define CNTMR_CAUSE_REG (CPU_AHB_MBUS_CAUSE_INT_REG(whoAmI())) ++#define CNTMR_MASK_REG (CPU_AHB_MBUS_MASK_INT_REG(whoAmI())) ++ ++/* ARM Timers Registers Map */ ++/*******************************************/ ++ ++ ++/* ARM Timers Control Register */ ++/* CPU_TIMERS_CTRL_REG (CTCR) */ ++ ++#define TIMER0_NUM 0 ++#define TIMER1_NUM 1 ++#define WATCHDOG_NUM 2 ++#define TIMER2_NUM 3 ++#define TIMER3_NUM 4 ++ ++#define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2) ++#define CTCR_ARM_TIMER_EN_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS) ++#define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr)) ++#define CTCR_ARM_TIMER_DIS(cntr) (0 << CTCR_ARM_TIMER_EN_OFFS(cntr)) ++ ++#define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1) ++#define CTCR_ARM_TIMER_AUTO_MASK(cntr) BIT1 ++#define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) ++#define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) ++ ++ ++/* ARM Timer\Watchdog Reload Register */ ++/* CNTMR_RELOAD_REG (TRR) */ ++ ++#define TRG_ARM_TIMER_REL_OFFS 0 ++#define TRG_ARM_TIMER_REL_MASK 0xffffffff ++ ++/* ARM Timer\Watchdog Register */ ++/* CNTMR_VAL_REG (TVRG) */ ++ ++#define TVR_ARM_TIMER_OFFS 0 ++#define TVR_ARM_TIMER_MASK 0xffffffff ++#define TVR_ARM_TIMER_MAX 0xffffffff ++ ++ ++ ++#endif /* __INCmvTmrwtdgRegsh */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCompVer.txt linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCompVer.txt +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCompVer.txt 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCompVer.txt 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,4 @@ ++Global HAL Version: FEROCEON_HAL_3_1_7 ++Unit HAL Version: 3.1.3 ++Description: This component includes an implementation of the unit HAL drivers ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,207 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#include "mvOs.h" ++#include "mvCpuCntrs.h" ++ ++ ++const static MV_CPU_CNTRS_OPS mvCpuCntrsOpsTbl[MV_CPU_CNTRS_NUM][MV_CPU_CNTRS_OPS_NUM] = ++{ ++ /*0*/ ++ { ++ MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_DCACHE_READ_HIT, MV_CPU_CNTRS_DCACHE_READ_MISS, ++ MV_CPU_CNTRS_DCACHE_WRITE_HIT, MV_CPU_CNTRS_DCACHE_WRITE_MISS, MV_CPU_CNTRS_INSTRUCTIONS, ++ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, ++ MV_CPU_CNTRS_MMU_READ_LATENCY, MV_CPU_CNTRS_ICACHE_READ_LATENCY, MV_CPU_CNTRS_WB_WRITE_LATENCY, ++ MV_CPU_CNTRS_LDM_STM_HOLD, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, ++ MV_CPU_CNTRS_DATA_WRITE_ACCESS, MV_CPU_CNTRS_DATA_READ_ACCESS, MV_CPU_CNTRS_INVALID, ++ MV_CPU_CNTRS_BRANCH_PREDICT_COUNT, ++ }, ++ /*1*/ ++ { ++ MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_ICACHE_READ_MISS, MV_CPU_CNTRS_DCACHE_READ_MISS, ++ MV_CPU_CNTRS_DCACHE_WRITE_MISS, MV_CPU_CNTRS_ITLB_MISS, MV_CPU_CNTRS_SINGLE_ISSUE, ++ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BRANCH_RETIRED, MV_CPU_CNTRS_INVALID, ++ MV_CPU_CNTRS_MMU_READ_BEAT, MV_CPU_CNTRS_ICACHE_READ_LATENCY, MV_CPU_CNTRS_WB_WRITE_BEAT, ++ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_IS_HOLD, MV_CPU_CNTRS_DATA_READ_ACCESS, ++ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, ++ MV_CPU_CNTRS_INVALID, ++ }, ++ /*2*/ ++ { ++ MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DCACHE_ACCESS, ++ MV_CPU_CNTRS_DTLB_MISS, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, ++ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BRANCH_PREDICT_MISS, MV_CPU_CNTRS_WB_WRITE_BEAT, ++ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DCACHE_READ_LATENCY, MV_CPU_CNTRS_DCACHE_WRITE_LATENCY, ++ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BIU_SIMULT_ACCESS, ++ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, ++ MV_CPU_CNTRS_INVALID, ++ }, ++ /*3*/ ++ { ++ MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_DCACHE_READ_MISS, MV_CPU_CNTRS_DCACHE_WRITE_MISS, ++ MV_CPU_CNTRS_TLB_MISS, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, ++ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BRANCH_TAKEN, MV_CPU_CNTRS_WB_FULL_CYCLES, ++ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DCACHE_READ_BEAT, MV_CPU_CNTRS_DCACHE_WRITE_BEAT, ++ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BIU_ANY_ACCESS, ++ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DATA_WRITE_ACCESS, ++ MV_CPU_CNTRS_INVALID, ++ } ++}; ++ ++MV_CPU_CNTRS_ENTRY mvCpuCntrsTbl[MV_CPU_CNTRS_NUM]; ++ ++MV_CPU_CNTRS_EVENT* mvCpuCntrsEventTbl[128]; ++ ++void mvCpuCntrsReset(void) ++{ ++ MV_U32 reg = 0; ++ ++ MV_ASM ("mcr p15, 0, %0, c15, c13, 0" : : "r" (reg)); ++ MV_ASM ("mcr p15, 0, %0, c15, c13, 1" : : "r" (reg)); ++ MV_ASM ("mcr p15, 0, %0, c15, c13, 2" : : "r" (reg)); ++ MV_ASM ("mcr p15, 0, %0, c15, c13, 3" : : "r" (reg)); ++ MV_ASM ("mcr p15, 0, %0, c15, c13, 4" : : "r" (reg)); ++ MV_ASM ("mcr p15, 0, %0, c15, c13, 5" : : "r" (reg)); ++ MV_ASM ("mcr p15, 0, %0, c15, c13, 6" : : "r" (reg)); ++ MV_ASM ("mcr p15, 0, %0, c15, c13, 7" : : "r" (reg)); ++} ++ ++void program_counter(int counter, int op) ++{ ++ MV_U32 reg = (1 << op) | 0x1; /*enable*/ ++ ++ switch(counter) ++ { ++ case 0: ++ __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 0" : : "r" (reg)); ++ return; ++ ++ case 1: ++ __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 1" : : "r" (reg)); ++ return; ++ ++ case 2: ++ __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 2" : : "r" (reg)); ++ return; ++ ++ case 3: ++ __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 3" : : "r" (reg)); ++ return; ++ ++ default: ++ mvOsPrintf("error in program_counter: bad counter number (%d)\n", counter); ++ } ++ return; ++} ++ ++void mvCpuCntrsEventClear(MV_CPU_CNTRS_EVENT* pEvent) ++{ ++ int i; ++ ++ for(i=0; icounters_sum[i] = 0; ++ } ++ pEvent->num_of_measurements = 0; ++} ++ ++ ++MV_CPU_CNTRS_EVENT* mvCpuCntrsEventCreate(char* name, MV_U32 print_threshold) ++{ ++ int i; ++ MV_CPU_CNTRS_EVENT* event = mvOsMalloc(sizeof(MV_CPU_CNTRS_EVENT)); ++ ++ if(event) ++ { ++ strncpy(event->name, name, sizeof(event->name)); ++ event->num_of_measurements = 0; ++ event->avg_sample_count = print_threshold; ++ for(i=0; icounters_before[i] = 0; ++ event->counters_after[i] = 0; ++ event->counters_sum[i] = 0; ++ } ++ } ++ return event; ++} ++ ++void mvCpuCntrsEventDelete(MV_CPU_CNTRS_EVENT* event) ++{ ++ if(event != NULL) ++ mvOsFree(event); ++} ++ ++ ++MV_STATUS mvCpuCntrsProgram(int counter, MV_CPU_CNTRS_OPS op, ++ char* name, MV_U32 overhead) ++{ ++ int i; ++ ++ /* Find required operations */ ++ for(i=0; inum_of_measurements < pEvent->avg_sample_count) ++ return; ++ ++ mvOsPrintf("%16s: ", pEvent->name); ++ for(i=0; icounters_sum[i], ++ pEvent->num_of_measurements, NULL); ++ if(counters_avg >= mvCpuCntrsTbl[i].overhead) ++ counters_avg -= mvCpuCntrsTbl[i].overhead; ++ else ++ counters_avg = 0; ++ ++ mvOsPrintf("%s=%5llu, ", mvCpuCntrsTbl[i].name, counters_avg); ++ } ++ mvOsPrintf("\n"); ++ mvCpuCntrsEventClear(pEvent); ++ mvCpuCntrsReset(); ++} ++ ++void mvCpuCntrsStatus(void) ++{ ++ int i; ++ ++ for(i=0; icounters_before[i] = mvCpuCntrsRead(i); ++#else ++ pEvent->counters_before[1] = mvCpuCntrsRead(1); ++ pEvent->counters_before[3] = mvCpuCntrsRead(3); ++ pEvent->counters_before[0] = mvCpuCntrsRead(0); ++ pEvent->counters_before[2] = mvCpuCntrsRead(2); ++#endif ++} ++ ++static INLINE void mvCpuCntrsReadAfter(MV_CPU_CNTRS_EVENT* pEvent) ++{ ++ int i; ++ ++#if 0 ++ /* order is important - we want to measure the cycle count first here! */ ++ for(i=0; icounters_after[i] = mvCpuCntrsRead(i); ++#else ++ pEvent->counters_after[2] = mvCpuCntrsRead(2); ++ pEvent->counters_after[0] = mvCpuCntrsRead(0); ++ pEvent->counters_after[3] = mvCpuCntrsRead(3); ++ pEvent->counters_after[1] = mvCpuCntrsRead(1); ++#endif ++ ++ for(i=0; icounters_sum[i] += (pEvent->counters_after[i] - pEvent->counters_before[i]); ++ } ++ pEvent->num_of_measurements++; ++} ++ ++ ++#ifdef CONFIG_MV_CPU_PERF_CNTRS ++ ++#define MV_CPU_CNTRS_READ(counter) mvCpuCntrsRead(counter) ++ ++#define MV_CPU_CNTRS_START(event) mvCpuCntrsReadBefore(event) ++ ++#define MV_CPU_CNTRS_STOP(event) mvCpuCntrsReadAfter(event) ++ ++#define MV_CPU_CNTRS_SHOW(event) mvCpuCntrsShow(event) ++ ++#else ++ ++#define MV_CPU_CNTRS_READ(counter) ++#define MV_CPU_CNTRS_START(event) ++#define MV_CPU_CNTRS_STOP(event) ++#define MV_CPU_CNTRS_SHOW(event) ++ ++#endif /* CONFIG_MV_CPU_PERF_CNTRS */ ++ ++ ++#endif /* __mvCpuCntrs_h__ */ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,143 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#include "mvOs.h" ++#include "mvCpuL2Cntrs.h" ++ ++ ++ ++MV_CPU_L2_CNTRS_ENTRY mvCpuL2CntrsTbl[MV_CPU_L2_CNTRS_NUM]; ++ ++MV_CPU_L2_CNTRS_EVENT* mvCpuL2CntrsEventTbl[128]; ++ ++void mvCpuL2CntrsReset(void) ++{ ++ MV_U32 reg = 0; ++ ++ MV_ASM ("mcr p15, 6, %0, c15, c13, 0" : : "r" (reg)); ++ MV_ASM ("mcr p15, 6, %0, c15, c13, 1" : : "r" (reg)); ++ MV_ASM ("mcr p15, 6, %0, c15, c13, 2" : : "r" (reg)); ++ MV_ASM ("mcr p15, 6, %0, c15, c13, 3" : : "r" (reg)); ++} ++ ++static void mvCpuL2CntrConfig(int counter, int op) ++{ ++ MV_U32 reg = (1 << op) | 0x1; /*enable*/ ++ ++ switch(counter) ++ { ++ case 0: ++ MV_ASM ("mcr p15, 6, %0, c15, c12, 0" : : "r" (reg)); ++ return; ++ ++ case 1: ++ MV_ASM ("mcr p15, 6, %0, c15, c12, 1" : : "r" (reg)); ++ return; ++ ++ default: ++ mvOsPrintf("mvCpuL2CntrConfig: bad counter number (%d)\n", counter); ++ } ++ return; ++} ++ ++void mvCpuL2CntrsEventClear(MV_CPU_L2_CNTRS_EVENT* pEvent) ++{ ++ int i; ++ ++ for(i=0; icounters_sum[i] = 0; ++ } ++ pEvent->num_of_measurements = 0; ++} ++ ++ ++MV_CPU_L2_CNTRS_EVENT* mvCpuL2CntrsEventCreate(char* name, MV_U32 print_threshold) ++{ ++ int i; ++ MV_CPU_L2_CNTRS_EVENT* event = mvOsMalloc(sizeof(MV_CPU_L2_CNTRS_EVENT)); ++ ++ if(event) ++ { ++ strncpy(event->name, name, sizeof(event->name)); ++ event->num_of_measurements = 0; ++ event->avg_sample_count = print_threshold; ++ for(i=0; icounters_before[i] = 0; ++ event->counters_after[i] = 0; ++ event->counters_sum[i] = 0; ++ } ++ } ++ return event; ++} ++ ++void mvCpuL2CntrsEventDelete(MV_CPU_L2_CNTRS_EVENT* event) ++{ ++ if(event != NULL) ++ mvOsFree(event); ++} ++ ++ ++MV_STATUS mvCpuL2CntrsProgram(int counter, MV_CPU_L2_CNTRS_OPS op, ++ char* name, MV_U32 overhead) ++{ ++ strncpy(mvCpuL2CntrsTbl[counter].name, name, sizeof(mvCpuL2CntrsTbl[counter].name)); ++ mvCpuL2CntrsTbl[counter].operation = op; ++ mvCpuL2CntrsTbl[counter].opIdx = op; ++ mvCpuL2CntrsTbl[counter].overhead = overhead; ++ mvCpuL2CntrConfig(counter, op); ++ mvOsPrintf("CPU L2 Counter %d: operation=%d, overhead=%d\n", ++ counter, op, overhead); ++ return MV_OK; ++} ++ ++void mvCpuL2CntrsShow(MV_CPU_L2_CNTRS_EVENT* pEvent) ++{ ++ int i; ++ MV_U64 counters_avg; ++ ++ if(pEvent->num_of_measurements < pEvent->avg_sample_count) ++ return; ++ ++ mvOsPrintf("%16s: ", pEvent->name); ++ for(i=0; icounters_sum[i], ++ pEvent->num_of_measurements, NULL); ++ ++ if(counters_avg >= mvCpuL2CntrsTbl[i].overhead) ++ counters_avg -= mvCpuL2CntrsTbl[i].overhead; ++ else ++ counters_avg = 0; ++ ++ mvOsPrintf("%s=%5llu, ", mvCpuL2CntrsTbl[i].name, counters_avg); ++ } ++ mvOsPrintf("\n"); ++ mvCpuL2CntrsEventClear(pEvent); ++ mvCpuL2CntrsReset(); ++} ++ ++void mvCpuL2CntrsStatus(void) ++{ ++ int i; ++ ++ for(i=0; icounters_before[i] = mvCpuL2CntrsRead(i); ++} ++ ++static INLINE void mvCpuL2CntrsReadAfter(MV_CPU_L2_CNTRS_EVENT* pEvent) ++{ ++ int i; ++ ++ for(i=0; icounters_after[i] = mvCpuL2CntrsRead(i); ++ pEvent->counters_sum[i] += (pEvent->counters_after[i] - pEvent->counters_before[i]); ++ } ++ pEvent->num_of_measurements++; ++} ++ ++ ++#ifdef CONFIG_MV_CPU_L2_PERF_CNTRS ++ ++#define MV_CPU_L2_CNTRS_READ(counter) mvCpuL2CntrsRead(counter) ++ ++#define MV_CPU_L2_CNTRS_START(event) mvCpuL2CntrsReadBefore(event) ++ ++#define MV_CPU_L2_CNTRS_STOP(event) mvCpuL2CntrsReadAfter(event) ++ ++#define MV_CPU_L2_CNTRS_SHOW(event) mvCpuL2CntrsShow(event) ++ ++#else ++ ++#define MV_CPU_L2_CNTRS_READ(counter) ++#define MV_CPU_L2_CNTRS_START(event) ++#define MV_CPU_L2_CNTRS_STOP(event) ++#define MV_CPU_L2_CNTRS_SHOW(event) ++ ++#endif /* CONFIG_MV_CPU_L2_PERF_CNTRS */ ++ ++ ++#endif /* __mvCpuL2Cntrs_h__ */ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvCompVer.txt linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvCompVer.txt +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvCompVer.txt 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvCompVer.txt 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,4 @@ ++Global HAL Version: FEROCEON_HAL_3_1_7 ++Unit HAL Version: 3.1.3 ++Description: This component includes an implementation of the unit HAL drivers ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,1479 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#include "ddr1_2/mvDram.h" ++#include "boardEnv/mvBoardEnvLib.h" ++ ++#undef MV_DEBUG ++#ifdef MV_DEBUG ++#define DB(x) x ++#else ++#define DB(x) ++#endif ++ ++static MV_VOID cpyDimm2BankInfo(MV_DIMM_INFO *pDimmInfo, ++ MV_DRAM_BANK_INFO *pBankInfo); ++static MV_U32 cas2ps(MV_U8 spd_byte); ++/******************************************************************************* ++* mvDramBankGet - Get the DRAM bank paramters. ++* ++* DESCRIPTION: ++* This function retrieves DRAM bank parameters as described in ++* DRAM_BANK_INFO struct to the controller DRAM unit. In case the board ++* has its DRAM on DIMMs it will use its EEPROM to extract SPD data ++* from it. Otherwise, if the DRAM is soldered on board, the function ++* should insert its bank information into MV_DRAM_BANK_INFO struct. ++* ++* INPUT: ++* bankNum - Board DRAM bank number. ++* ++* OUTPUT: ++* pBankInfo - DRAM bank information struct. ++* ++* RETURN: ++* MV_FAIL - Bank parameters could not be read. ++* ++*******************************************************************************/ ++MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo) ++{ ++ MV_DIMM_INFO dimmInfo; ++ ++ DB(mvOsPrintf("Dram: mvDramBankInfoGet bank %d\n", bankNum)); ++ /* zero pBankInfo structure */ ++ memset(pBankInfo, 0, sizeof(*pBankInfo)); ++ ++ if((NULL == pBankInfo) || (bankNum >= MV_DRAM_MAX_CS )) ++ { ++ DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); ++ return MV_BAD_PARAM; ++ } ++ if( MV_OK != dimmSpdGet((MV_U32)(bankNum/2), &dimmInfo)) ++ { ++ DB(mvOsPrintf("Dram: ERR dimmSpdGet failed to get dimm info \n")); ++ return MV_FAIL; ++ } ++ if((dimmInfo.numOfModuleBanks == 1) && ((bankNum % 2) == 1)) ++ { ++ DB(mvOsPrintf("Dram: ERR dimmSpdGet. Can't find DIMM bank 2 \n")); ++ return MV_FAIL; ++ } ++ ++ /* convert Dimm info to Bank info */ ++ cpyDimm2BankInfo(&dimmInfo, pBankInfo); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* cpyDimm2BankInfo - Convert a Dimm info struct into a bank info struct. ++* ++* DESCRIPTION: ++* Convert a Dimm info struct into a bank info struct. ++* ++* INPUT: ++* pDimmInfo - DIMM information structure. ++* ++* OUTPUT: ++* pBankInfo - DRAM bank information struct. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++static MV_VOID cpyDimm2BankInfo(MV_DIMM_INFO *pDimmInfo, ++ MV_DRAM_BANK_INFO *pBankInfo) ++{ ++ pBankInfo->memoryType = pDimmInfo->memoryType; ++ ++ /* DIMM dimensions */ ++ pBankInfo->numOfRowAddr = pDimmInfo->numOfRowAddr; ++ pBankInfo->numOfColAddr = pDimmInfo->numOfColAddr; ++ pBankInfo->dataWidth = pDimmInfo->dataWidth; ++ pBankInfo->errorCheckType = pDimmInfo->errorCheckType; ++ pBankInfo->sdramWidth = pDimmInfo->sdramWidth; ++ pBankInfo->errorCheckDataWidth = pDimmInfo->errorCheckDataWidth; ++ pBankInfo->numOfBanksOnEachDevice = pDimmInfo->numOfBanksOnEachDevice; ++ pBankInfo->suportedCasLatencies = pDimmInfo->suportedCasLatencies; ++ pBankInfo->refreshInterval = pDimmInfo->refreshInterval; ++ ++ /* DIMM timing parameters */ ++ pBankInfo->minCycleTimeAtMaxCasLatPs = pDimmInfo->minCycleTimeAtMaxCasLatPs; ++ pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps = ++ pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps; ++ pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps = ++ pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps; ++ ++ pBankInfo->minRowPrechargeTime = pDimmInfo->minRowPrechargeTime; ++ pBankInfo->minRowActiveToRowActive = pDimmInfo->minRowActiveToRowActive; ++ pBankInfo->minRasToCasDelay = pDimmInfo->minRasToCasDelay; ++ pBankInfo->minRasPulseWidth = pDimmInfo->minRasPulseWidth; ++ pBankInfo->minWriteRecoveryTime = pDimmInfo->minWriteRecoveryTime; ++ pBankInfo->minWriteToReadCmdDelay = pDimmInfo->minWriteToReadCmdDelay; ++ pBankInfo->minReadToPrechCmdDelay = pDimmInfo->minReadToPrechCmdDelay; ++ pBankInfo->minRefreshToActiveCmd = pDimmInfo->minRefreshToActiveCmd; ++ ++ /* Parameters calculated from the extracted DIMM information */ ++ pBankInfo->size = pDimmInfo->size/pDimmInfo->numOfModuleBanks; ++ pBankInfo->deviceDensity = pDimmInfo->deviceDensity; ++ pBankInfo->numberOfDevices = pDimmInfo->numberOfDevices / ++ pDimmInfo->numOfModuleBanks; ++ ++ /* DIMM attributes (MV_TRUE for yes) */ ++ ++ if ((pDimmInfo->memoryType == MEM_TYPE_SDRAM) || ++ (pDimmInfo->memoryType == MEM_TYPE_DDR1) ) ++ { ++ if (pDimmInfo->dimmAttributes & BIT1) ++ pBankInfo->registeredAddrAndControlInputs = MV_TRUE; ++ else ++ pBankInfo->registeredAddrAndControlInputs = MV_FALSE; ++ } ++ else /* pDimmInfo->memoryType == MEM_TYPE_DDR2 */ ++ { ++ if (pDimmInfo->dimmTypeInfo & (BIT0 | BIT4)) ++ pBankInfo->registeredAddrAndControlInputs = MV_TRUE; ++ else ++ pBankInfo->registeredAddrAndControlInputs = MV_FALSE; ++ } ++ ++ return; ++} ++ ++/******************************************************************************* ++* dimmSpdCpy - Cpy SPD parameters from dimm 0 to dimm 1. ++* ++* DESCRIPTION: ++* Read the DIMM SPD parameters from dimm 0 into dimm 1 SPD. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. ++* ++*******************************************************************************/ ++MV_STATUS dimmSpdCpy(MV_VOID) ++{ ++ MV_U32 i; ++ MV_U32 spdChecksum; ++ ++ MV_TWSI_SLAVE twsiSlave; ++ MV_U8 data[SPD_SIZE]; ++ ++ /* zero dimmInfo structure */ ++ memset(data, 0, SPD_SIZE); ++ ++ /* read the dimm eeprom */ ++ DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); ++ twsiSlave.slaveAddr.address = MV_BOARD_DIMM0_I2C_ADDR; ++ twsiSlave.slaveAddr.type = ADDR7_BIT; ++ twsiSlave.validOffset = MV_TRUE; ++ twsiSlave.offset = 0; ++ twsiSlave.moreThen256 = MV_FALSE; ++ ++ if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, ++ &twsiSlave, data, SPD_SIZE) ) ++ { ++ DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 0\n")); ++ return MV_FAIL; ++ } ++ DB(puts("DRAM: Reading dimm info succeded.\n")); ++ ++ /* calculate SPD checksum */ ++ spdChecksum = 0; ++ ++ for(i = 0 ; i <= 62 ; i++) ++ { ++ spdChecksum += data[i]; ++ } ++ ++ if ((spdChecksum & 0xff) != data[63]) ++ { ++ DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", ++ (MV_U32)(spdChecksum & 0xff), data[63])); ++ } ++ else ++ { ++ DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); ++ } ++ ++ /* copy the SPD content 1:1 into the DIMM 1 SPD */ ++ twsiSlave.slaveAddr.address = MV_BOARD_DIMM1_I2C_ADDR; ++ twsiSlave.slaveAddr.type = ADDR7_BIT; ++ twsiSlave.validOffset = MV_TRUE; ++ twsiSlave.offset = 0; ++ twsiSlave.moreThen256 = MV_FALSE; ++ ++ for(i = 0 ; i < SPD_SIZE ; i++) ++ { ++ twsiSlave.offset = i; ++ if( MV_OK != mvTwsiWrite (MV_BOARD_DIMM_I2C_CHANNEL, ++ &twsiSlave, &data[i], 1) ) ++ { ++ mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 1 byte %d \n",i); ++ return MV_FAIL; ++ } ++ mvOsDelay(5); ++ } ++ ++ DB(puts("DRAM: Reading dimm info succeded.\n")); ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* dimmSpdGet - Get the SPD parameters. ++* ++* DESCRIPTION: ++* Read the DIMM SPD parameters into given struct parameter. ++* ++* INPUT: ++* dimmNum - DIMM number. See MV_BOARD_DIMM_NUM enumerator. ++* ++* OUTPUT: ++* pDimmInfo - DIMM information structure. ++* ++* RETURN: ++* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. ++* ++*******************************************************************************/ ++MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo) ++{ ++ MV_U32 i; ++ MV_U32 density = 1; ++ MV_U32 spdChecksum; ++ ++ MV_TWSI_SLAVE twsiSlave; ++ MV_U8 data[SPD_SIZE]; ++ ++ if((NULL == pDimmInfo)|| (dimmNum >= MAX_DIMM_NUM)) ++ { ++ DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); ++ return MV_BAD_PARAM; ++ } ++ ++ /* zero dimmInfo structure */ ++ memset(data, 0, SPD_SIZE); ++ ++ /* read the dimm eeprom */ ++ DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); ++ twsiSlave.slaveAddr.address = (dimmNum == 0) ? ++ MV_BOARD_DIMM0_I2C_ADDR : MV_BOARD_DIMM1_I2C_ADDR; ++ twsiSlave.slaveAddr.type = ADDR7_BIT; ++ twsiSlave.validOffset = MV_TRUE; ++ twsiSlave.offset = 0; ++ twsiSlave.moreThen256 = MV_FALSE; ++ ++ if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, ++ &twsiSlave, data, SPD_SIZE) ) ++ { ++ DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum %d \n", dimmNum)); ++ return MV_FAIL; ++ } ++ DB(puts("DRAM: Reading dimm info succeded.\n")); ++ ++ /* calculate SPD checksum */ ++ spdChecksum = 0; ++ ++ for(i = 0 ; i <= 62 ; i++) ++ { ++ spdChecksum += data[i]; ++ } ++ ++ if ((spdChecksum & 0xff) != data[63]) ++ { ++ DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", ++ (MV_U32)(spdChecksum & 0xff), data[63])); ++ } ++ else ++ { ++ DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); ++ } ++ ++ /* copy the SPD content 1:1 into the dimmInfo structure*/ ++ for(i = 0 ; i < SPD_SIZE ; i++) ++ { ++ pDimmInfo->spdRawData[i] = data[i]; ++ DB(mvOsPrintf("SPD-EEPROM Byte %3d = %3x (%3d)\n",i, data[i], data[i])); ++ } ++ ++ DB(mvOsPrintf("DRAM SPD Information:\n")); ++ ++ /* Memory type (DDR / SDRAM) */ ++ switch (data[DIMM_MEM_TYPE]) ++ { ++ case (DIMM_MEM_TYPE_SDRAM): ++ pDimmInfo->memoryType = MEM_TYPE_SDRAM; ++ DB(mvOsPrintf("DRAM Memeory type SDRAM\n")); ++ break; ++ case (DIMM_MEM_TYPE_DDR1): ++ pDimmInfo->memoryType = MEM_TYPE_DDR1; ++ DB(mvOsPrintf("DRAM Memeory type DDR1\n")); ++ break; ++ case (DIMM_MEM_TYPE_DDR2): ++ pDimmInfo->memoryType = MEM_TYPE_DDR2; ++ DB(mvOsPrintf("DRAM Memeory type DDR2\n")); ++ break; ++ default: ++ mvOsPrintf("ERROR: Undefined memory type!\n"); ++ return MV_ERROR; ++ } ++ ++ ++ /* Number Of Row Addresses */ ++ pDimmInfo->numOfRowAddr = data[DIMM_ROW_NUM]; ++ DB(mvOsPrintf("DRAM numOfRowAddr[3] %d\n",pDimmInfo->numOfRowAddr)); ++ ++ /* Number Of Column Addresses */ ++ pDimmInfo->numOfColAddr = data[DIMM_COL_NUM]; ++ DB(mvOsPrintf("DRAM numOfColAddr[4] %d\n",pDimmInfo->numOfColAddr)); ++ ++ /* Number Of Module Banks */ ++ pDimmInfo->numOfModuleBanks = data[DIMM_MODULE_BANK_NUM]; ++ DB(mvOsPrintf("DRAM numOfModuleBanks[5] 0x%x\n", ++ pDimmInfo->numOfModuleBanks)); ++ ++ /* Number of module banks encoded differently for DDR2 */ ++ if (pDimmInfo->memoryType == MEM_TYPE_DDR2) ++ pDimmInfo->numOfModuleBanks = (pDimmInfo->numOfModuleBanks & 0x7)+1; ++ ++ /* Data Width */ ++ pDimmInfo->dataWidth = data[DIMM_DATA_WIDTH]; ++ DB(mvOsPrintf("DRAM dataWidth[6] 0x%x\n", pDimmInfo->dataWidth)); ++ ++ /* Minimum Cycle Time At Max CasLatancy */ ++ pDimmInfo->minCycleTimeAtMaxCasLatPs = cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS]); ++ ++ /* Error Check Type */ ++ pDimmInfo->errorCheckType = data[DIMM_ERR_CHECK_TYPE]; ++ DB(mvOsPrintf("DRAM errorCheckType[11] 0x%x\n", ++ pDimmInfo->errorCheckType)); ++ ++ /* Refresh Interval */ ++ pDimmInfo->refreshInterval = data[DIMM_REFRESH_INTERVAL]; ++ DB(mvOsPrintf("DRAM refreshInterval[12] 0x%x\n", ++ pDimmInfo->refreshInterval)); ++ ++ /* Sdram Width */ ++ pDimmInfo->sdramWidth = data[DIMM_SDRAM_WIDTH]; ++ DB(mvOsPrintf("DRAM sdramWidth[13] 0x%x\n",pDimmInfo->sdramWidth)); ++ ++ /* Error Check Data Width */ ++ pDimmInfo->errorCheckDataWidth = data[DIMM_ERR_CHECK_DATA_WIDTH]; ++ DB(mvOsPrintf("DRAM errorCheckDataWidth[14] 0x%x\n", ++ pDimmInfo->errorCheckDataWidth)); ++ ++ /* Burst Length Supported */ ++ /* SDRAM/DDR1: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * ++ *********************************************************/ ++ /* DDR2: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * ++ *********************************************************/ ++ ++ pDimmInfo->burstLengthSupported = data[DIMM_BURST_LEN_SUP]; ++ DB(mvOsPrintf("DRAM burstLengthSupported[16] 0x%x\n", ++ pDimmInfo->burstLengthSupported)); ++ ++ /* Number Of Banks On Each Device */ ++ pDimmInfo->numOfBanksOnEachDevice = data[DIMM_DEV_BANK_NUM]; ++ DB(mvOsPrintf("DRAM numOfBanksOnEachDevice[17] 0x%x\n", ++ pDimmInfo->numOfBanksOnEachDevice)); ++ ++ /* Suported Cas Latencies */ ++ ++ /* SDRAM: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * ++ ********************************************************/ ++ ++ /* DDR 1: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * ++ *********************************************************/ ++ ++ /* DDR 2: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * ++ *********************************************************/ ++ ++ pDimmInfo->suportedCasLatencies = data[DIMM_SUP_CAL]; ++ DB(mvOsPrintf("DRAM suportedCasLatencies[18] 0x%x\n", ++ pDimmInfo->suportedCasLatencies)); ++ ++ /* For DDR2 only, get the DIMM type information */ ++ if (pDimmInfo->memoryType == MEM_TYPE_DDR2) ++ { ++ pDimmInfo->dimmTypeInfo = data[DIMM_DDR2_TYPE_INFORMATION]; ++ DB(mvOsPrintf("DRAM dimmTypeInfo[20] (DDR2) 0x%x\n", ++ pDimmInfo->dimmTypeInfo)); ++ } ++ ++ /* SDRAM Modules Attributes */ ++ pDimmInfo->dimmAttributes = data[DIMM_BUF_ADDR_CONT_IN]; ++ DB(mvOsPrintf("DRAM dimmAttributes[21] 0x%x\n", ++ pDimmInfo->dimmAttributes)); ++ ++ /* Minimum Cycle Time At Max CasLatancy Minus 1*/ ++ pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps = ++ cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS1]); ++ ++ /* Minimum Cycle Time At Max CasLatancy Minus 2*/ ++ pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps = ++ cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS2]); ++ ++ pDimmInfo->minRowPrechargeTime = data[DIMM_MIN_ROW_PRECHARGE_TIME]; ++ DB(mvOsPrintf("DRAM minRowPrechargeTime[27] 0x%x\n", ++ pDimmInfo->minRowPrechargeTime)); ++ pDimmInfo->minRowActiveToRowActive = data[DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE]; ++ DB(mvOsPrintf("DRAM minRowActiveToRowActive[28] 0x%x\n", ++ pDimmInfo->minRowActiveToRowActive)); ++ pDimmInfo->minRasToCasDelay = data[DIMM_MIN_RAS_TO_CAS_DELAY]; ++ DB(mvOsPrintf("DRAM minRasToCasDelay[29] 0x%x\n", ++ pDimmInfo->minRasToCasDelay)); ++ pDimmInfo->minRasPulseWidth = data[DIMM_MIN_RAS_PULSE_WIDTH]; ++ DB(mvOsPrintf("DRAM minRasPulseWidth[30] 0x%x\n", ++ pDimmInfo->minRasPulseWidth)); ++ ++ /* DIMM Bank Density */ ++ pDimmInfo->dimmBankDensity = data[DIMM_BANK_DENSITY]; ++ DB(mvOsPrintf("DRAM dimmBankDensity[31] 0x%x\n", ++ pDimmInfo->dimmBankDensity)); ++ ++ /* Only DDR2 includes Write Recovery Time field. Other SDRAM ignore */ ++ pDimmInfo->minWriteRecoveryTime = data[DIMM_MIN_WRITE_RECOVERY_TIME]; ++ DB(mvOsPrintf("DRAM minWriteRecoveryTime[36] 0x%x\n", ++ pDimmInfo->minWriteRecoveryTime)); ++ ++ /* Only DDR2 includes Internal Write To Read Command Delay field. */ ++ pDimmInfo->minWriteToReadCmdDelay = data[DIMM_MIN_WRITE_TO_READ_CMD_DELAY]; ++ DB(mvOsPrintf("DRAM minWriteToReadCmdDelay[37] 0x%x\n", ++ pDimmInfo->minWriteToReadCmdDelay)); ++ ++ /* Only DDR2 includes Internal Read To Precharge Command Delay field. */ ++ pDimmInfo->minReadToPrechCmdDelay = data[DIMM_MIN_READ_TO_PRECH_CMD_DELAY]; ++ DB(mvOsPrintf("DRAM minReadToPrechCmdDelay[38] 0x%x\n", ++ pDimmInfo->minReadToPrechCmdDelay)); ++ ++ /* Only DDR2 includes Minimum Refresh to Activate/Refresh Command field */ ++ pDimmInfo->minRefreshToActiveCmd = data[DIMM_MIN_REFRESH_TO_ACTIVATE_CMD]; ++ DB(mvOsPrintf("DRAM minRefreshToActiveCmd[42] 0x%x\n", ++ pDimmInfo->minRefreshToActiveCmd)); ++ ++ /* calculating the sdram density. Representing device density from */ ++ /* bit 20 to allow representation of 4GB and above. */ ++ /* For example, if density is 512Mbit 0x20000000, will be represent in */ ++ /* deviceDensity by 0x20000000 >> 16 --> 0x00000200. Another example */ ++ /* is density 8GB 0x200000000 >> 16 --> 0x00002000. */ ++ density = (1 << ((pDimmInfo->numOfRowAddr + pDimmInfo->numOfColAddr) - 20)); ++ pDimmInfo->deviceDensity = density * ++ pDimmInfo->numOfBanksOnEachDevice * ++ pDimmInfo->sdramWidth; ++ DB(mvOsPrintf("DRAM deviceDensity %d\n",pDimmInfo->deviceDensity)); ++ ++ /* Number of devices includeing Error correction */ ++ pDimmInfo->numberOfDevices = (pDimmInfo->dataWidth/pDimmInfo->sdramWidth) * ++ pDimmInfo->numOfModuleBanks; ++ DB(mvOsPrintf("DRAM numberOfDevices %d\n", ++ pDimmInfo->numberOfDevices)); ++ ++ pDimmInfo->size = 0; ++ ++ /* Note that pDimmInfo->size is in MB units */ ++ if (pDimmInfo->memoryType == MEM_TYPE_SDRAM) ++ { ++ if (pDimmInfo->dimmBankDensity & BIT0) ++ pDimmInfo->size += 1024; /* Equal to 1GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT1) ++ pDimmInfo->size += 8; /* Equal to 8MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT2) ++ pDimmInfo->size += 16; /* Equal to 16MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT3) ++ pDimmInfo->size += 32; /* Equal to 32MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT4) ++ pDimmInfo->size += 64; /* Equal to 64MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT5) ++ pDimmInfo->size += 128; /* Equal to 128MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT6) ++ pDimmInfo->size += 256; /* Equal to 256MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT7) ++ pDimmInfo->size += 512; /* Equal to 512MB */ ++ } ++ else if (pDimmInfo->memoryType == MEM_TYPE_DDR1) ++ { ++ if (pDimmInfo->dimmBankDensity & BIT0) ++ pDimmInfo->size += 1024; /* Equal to 1GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT1) ++ pDimmInfo->size += 2048; /* Equal to 2GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT2) ++ pDimmInfo->size += 16; /* Equal to 16MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT3) ++ pDimmInfo->size += 32; /* Equal to 32MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT4) ++ pDimmInfo->size += 64; /* Equal to 64MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT5) ++ pDimmInfo->size += 128; /* Equal to 128MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT6) ++ pDimmInfo->size += 256; /* Equal to 256MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT7) ++ pDimmInfo->size += 512; /* Equal to 512MB */ ++ } ++ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ ++ { ++ if (pDimmInfo->dimmBankDensity & BIT0) ++ pDimmInfo->size += 1024; /* Equal to 1GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT1) ++ pDimmInfo->size += 2048; /* Equal to 2GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT2) ++ pDimmInfo->size += 4096; /* Equal to 4GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT3) ++ pDimmInfo->size += 8192; /* Equal to 8GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT4) ++ pDimmInfo->size += 16384; /* Equal to 16GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT5) ++ pDimmInfo->size += 128; /* Equal to 128MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT6) ++ pDimmInfo->size += 256; /* Equal to 256MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT7) ++ pDimmInfo->size += 512; /* Equal to 512MB */ ++ } ++ ++ pDimmInfo->size *= pDimmInfo->numOfModuleBanks; ++ ++ DB(mvOsPrintf("Dram: dimm size %dMB \n",pDimmInfo->size)); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* dimmSpdPrint - Print the SPD parameters. ++* ++* DESCRIPTION: ++* Print the Dimm SPD parameters. ++* ++* INPUT: ++* pDimmInfo - DIMM information structure. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID dimmSpdPrint(MV_U32 dimmNum) ++{ ++ MV_DIMM_INFO dimmInfo; ++ MV_U32 i, temp = 0; ++ MV_U32 k, maskLeftOfPoint = 0, maskRightOfPoint = 0; ++ MV_U32 rightOfPoint = 0,leftOfPoint = 0, div, time_tmp, shift; ++ MV_U32 busClkPs; ++ MV_U8 trp_clocks=0, trcd_clocks, tras_clocks, trrd_clocks, ++ temp_buf[40], *spdRawData; ++ ++ busClkPs = 1000000000 / (mvBoardSysClkGet() / 100); /* in 10 ps units */ ++ ++ spdRawData = dimmInfo.spdRawData; ++ ++ if(MV_OK != dimmSpdGet(dimmNum, &dimmInfo)) ++ { ++ mvOsOutput("ERROR: Could not read SPD information!\n"); ++ return; ++ } ++ ++ /* find Manufactura of Dimm Module */ ++ mvOsOutput("\nManufacturer's JEDEC ID Code: "); ++ for(i = 0 ; i < DIMM_MODULE_MANU_SIZE ; i++) ++ { ++ mvOsOutput("%x",spdRawData[DIMM_MODULE_MANU_OFFS + i]); ++ } ++ mvOsOutput("\n"); ++ ++ /* Manufacturer's Specific Data */ ++ for(i = 0 ; i < DIMM_MODULE_ID_SIZE ; i++) ++ { ++ temp_buf[i] = spdRawData[DIMM_MODULE_ID_OFFS + i]; ++ } ++ mvOsOutput("Manufacturer's Specific Data: %s\n", temp_buf); ++ ++ /* Module Part Number */ ++ for(i = 0 ; i < DIMM_MODULE_VEN_SIZE ; i++) ++ { ++ temp_buf[i] = spdRawData[DIMM_MODULE_VEN_OFFS + i]; ++ } ++ mvOsOutput("Module Part Number: %s\n", temp_buf); ++ ++ /* Module Serial Number */ ++ for(i = 0; i < sizeof(MV_U32); i++) ++ { ++ temp |= spdRawData[95+i] << 8*i; ++ } ++ mvOsOutput("DIMM Serial No. %ld (%lx)\n", (long)temp, ++ (long)temp); ++ ++ /* find Manufac-Data of Dimm Module */ ++ mvOsOutput("Manufactoring Date: Year 20%d%d/ ww %d%d\n", ++ ((spdRawData[93] & 0xf0) >> 4), (spdRawData[93] & 0xf), ++ ((spdRawData[94] & 0xf0) >> 4), (spdRawData[94] & 0xf)); ++ /* find modul_revision of Dimm Module */ ++ mvOsOutput("Module Revision: %d.%d\n", ++ spdRawData[91], spdRawData[92]); ++ ++ /* find manufac_place of Dimm Module */ ++ mvOsOutput("manufac_place: %d\n", spdRawData[72]); ++ ++ /* go over the first 35 I2C data bytes */ ++ for(i = 2 ; i <= 35 ; i++) ++ switch(i) ++ { ++ case 2: /* Memory type (DDR1/2 / SDRAM) */ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ mvOsOutput("Dram Type is: SDRAM\n"); ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) ++ mvOsOutput("Dram Type is: SDRAM DDR1\n"); ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) ++ mvOsOutput("Dram Type is: SDRAM DDR2\n"); ++ else ++ mvOsOutput("Dram Type unknown\n"); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 3: /* Number Of Row Addresses */ ++ mvOsOutput("Module Number of row addresses: %d\n", ++ dimmInfo.numOfRowAddr); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 4: /* Number Of Column Addresses */ ++ mvOsOutput("Module Number of col addresses: %d\n", ++ dimmInfo.numOfColAddr); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 5: /* Number Of Module Banks */ ++ mvOsOutput("Number of Banks on Mod.: %d\n", ++ dimmInfo.numOfModuleBanks); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 6: /* Data Width */ ++ mvOsOutput("Module Data Width: %d bit\n", ++ dimmInfo.dataWidth); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 8: /* Voltage Interface */ ++ switch(spdRawData[i]) ++ { ++ case 0x0: ++ mvOsOutput("Module is TTL_5V_TOLERANT\n"); ++ break; ++ case 0x1: ++ mvOsOutput("Module is LVTTL\n"); ++ break; ++ case 0x2: ++ mvOsOutput("Module is HSTL_1_5V\n"); ++ break; ++ case 0x3: ++ mvOsOutput("Module is SSTL_3_3V\n"); ++ break; ++ case 0x4: ++ mvOsOutput("Module is SSTL_2_5V\n"); ++ break; ++ case 0x5: ++ if (dimmInfo.memoryType != MEM_TYPE_SDRAM) ++ { ++ mvOsOutput("Module is SSTL_1_8V\n"); ++ break; ++ } ++ default: ++ mvOsOutput("Module is VOLTAGE_UNKNOWN\n"); ++ break; ++ } ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 9: /* Minimum Cycle Time At Max CasLatancy */ ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ rightOfPoint = (spdRawData[i] & 0x0f) * 10; ++ ++ /* DDR2 addition of right of point */ ++ if ((spdRawData[i] & 0x0f) == 0xA) ++ { ++ rightOfPoint = 25; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xB) ++ { ++ rightOfPoint = 33; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xC) ++ { ++ rightOfPoint = 66; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xD) ++ { ++ rightOfPoint = 75; ++ } ++ mvOsOutput("Minimum Cycle Time At Max CL: %d.%d [ns]\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 10: /* Clock To Data Out */ ++ div = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 10:100; ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = time_tmp / div; ++ rightOfPoint = time_tmp % div; ++ mvOsOutput("Clock To Data Out: %d.%d [ns]\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 11: /* Error Check Type */ ++ mvOsOutput("Error Check Type (0=NONE): %d\n", ++ dimmInfo.errorCheckType); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 12: /* Refresh Interval */ ++ mvOsOutput("Refresh Rate: %x\n", ++ dimmInfo.refreshInterval); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 13: /* Sdram Width */ ++ mvOsOutput("Sdram Width: %d bits\n", ++ dimmInfo.sdramWidth); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 14: /* Error Check Data Width */ ++ mvOsOutput("Error Check Data Width: %d bits\n", ++ dimmInfo.errorCheckDataWidth); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 15: /* Minimum Clock Delay is unsupported */ ++ if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || ++ (dimmInfo.memoryType == MEM_TYPE_DDR1)) ++ { ++ mvOsOutput("Minimum Clk Delay back to back: %d\n", ++ spdRawData[i]); ++ } ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 16: /* Burst Length Supported */ ++ /* SDRAM/DDR1: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * ++ *********************************************************/ ++ /* DDR2: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * ++ *********************************************************/ ++ mvOsOutput("Burst Length Supported: "); ++ if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || ++ (dimmInfo.memoryType == MEM_TYPE_DDR1)) ++ { ++ if (dimmInfo.burstLengthSupported & BIT0) ++ mvOsOutput("1, "); ++ if (dimmInfo.burstLengthSupported & BIT1) ++ mvOsOutput("2, "); ++ } ++ if (dimmInfo.burstLengthSupported & BIT2) ++ mvOsOutput("4, "); ++ if (dimmInfo.burstLengthSupported & BIT3) ++ mvOsOutput("8, "); ++ ++ mvOsOutput(" Bit \n"); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 17: /* Number Of Banks On Each Device */ ++ mvOsOutput("Number Of Banks On Each Chip: %d\n", ++ dimmInfo.numOfBanksOnEachDevice); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 18: /* Suported Cas Latencies */ ++ ++ /* SDRAM: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * ++ ********************************************************/ ++ ++ /* DDR 1: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * ++ *********************************************************/ ++ ++ /* DDR 2: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * ++ *********************************************************/ ++ ++ mvOsOutput("Suported Cas Latencies: (CL) "); ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ for (k = 0; k <=7; k++) ++ { ++ if (dimmInfo.suportedCasLatencies & (1 << k)) ++ mvOsOutput("%d, ", k+1); ++ } ++ } ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) ++ { ++ if (dimmInfo.suportedCasLatencies & BIT0) ++ mvOsOutput("1, "); ++ if (dimmInfo.suportedCasLatencies & BIT1) ++ mvOsOutput("1.5, "); ++ if (dimmInfo.suportedCasLatencies & BIT2) ++ mvOsOutput("2, "); ++ if (dimmInfo.suportedCasLatencies & BIT3) ++ mvOsOutput("2.5, "); ++ if (dimmInfo.suportedCasLatencies & BIT4) ++ mvOsOutput("3, "); ++ if (dimmInfo.suportedCasLatencies & BIT5) ++ mvOsOutput("3.5, "); ++ } ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) ++ { ++ if (dimmInfo.suportedCasLatencies & BIT2) ++ mvOsOutput("2, "); ++ if (dimmInfo.suportedCasLatencies & BIT3) ++ mvOsOutput("3, "); ++ if (dimmInfo.suportedCasLatencies & BIT4) ++ mvOsOutput("4, "); ++ if (dimmInfo.suportedCasLatencies & BIT5) ++ mvOsOutput("5, "); ++ } ++ else ++ mvOsOutput("?.?, "); ++ mvOsOutput("\n"); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 20: /* DDR2 DIMM type info */ ++ if (dimmInfo.memoryType == MEM_TYPE_DDR2) ++ { ++ if (dimmInfo.dimmTypeInfo & (BIT0 | BIT4)) ++ mvOsOutput("Registered DIMM (RDIMM)\n"); ++ else if (dimmInfo.dimmTypeInfo & (BIT1 | BIT5)) ++ mvOsOutput("Unbuffered DIMM (UDIMM)\n"); ++ else ++ mvOsOutput("Unknown DIMM type.\n"); ++ } ++ ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 21: /* SDRAM Modules Attributes */ ++ mvOsOutput("\nModule Attributes (SPD Byte 21): \n"); ++ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ if (dimmInfo.dimmAttributes & BIT0) ++ mvOsOutput(" Buffered Addr/Control Input: Yes\n"); ++ else ++ mvOsOutput(" Buffered Addr/Control Input: No\n"); ++ ++ if (dimmInfo.dimmAttributes & BIT1) ++ mvOsOutput(" Registered Addr/Control Input: Yes\n"); ++ else ++ mvOsOutput(" Registered Addr/Control Input: No\n"); ++ ++ if (dimmInfo.dimmAttributes & BIT2) ++ mvOsOutput(" On-Card PLL (clock): Yes \n"); ++ else ++ mvOsOutput(" On-Card PLL (clock): No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT3) ++ mvOsOutput(" Bufferd DQMB Input: Yes \n"); ++ else ++ mvOsOutput(" Bufferd DQMB Inputs: No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT4) ++ mvOsOutput(" Registered DQMB Inputs: Yes \n"); ++ else ++ mvOsOutput(" Registered DQMB Inputs: No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT5) ++ mvOsOutput(" Differential Clock Input: Yes \n"); ++ else ++ mvOsOutput(" Differential Clock Input: No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT6) ++ mvOsOutput(" redundant Row Addressing: Yes \n"); ++ else ++ mvOsOutput(" redundant Row Addressing: No \n"); ++ } ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) ++ { ++ if (dimmInfo.dimmAttributes & BIT0) ++ mvOsOutput(" Buffered Addr/Control Input: Yes\n"); ++ else ++ mvOsOutput(" Buffered Addr/Control Input: No\n"); ++ ++ if (dimmInfo.dimmAttributes & BIT1) ++ mvOsOutput(" Registered Addr/Control Input: Yes\n"); ++ else ++ mvOsOutput(" Registered Addr/Control Input: No\n"); ++ ++ if (dimmInfo.dimmAttributes & BIT2) ++ mvOsOutput(" On-Card PLL (clock): Yes \n"); ++ else ++ mvOsOutput(" On-Card PLL (clock): No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT3) ++ mvOsOutput(" FET Switch On-Card Enabled: Yes \n"); ++ else ++ mvOsOutput(" FET Switch On-Card Enabled: No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT4) ++ mvOsOutput(" FET Switch External Enabled: Yes \n"); ++ else ++ mvOsOutput(" FET Switch External Enabled: No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT5) ++ mvOsOutput(" Differential Clock Input: Yes \n"); ++ else ++ mvOsOutput(" Differential Clock Input: No \n"); ++ } ++ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ ++ { ++ mvOsOutput(" Number of Active Registers on the DIMM: %d\n", ++ (dimmInfo.dimmAttributes & 0x3) + 1); ++ ++ mvOsOutput(" Number of PLLs on the DIMM: %d\n", ++ ((dimmInfo.dimmAttributes) >> 2) & 0x3); ++ ++ if (dimmInfo.dimmAttributes & BIT4) ++ mvOsOutput(" FET Switch External Enabled: Yes \n"); ++ else ++ mvOsOutput(" FET Switch External Enabled: No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT6) ++ mvOsOutput(" Analysis probe installed: Yes \n"); ++ else ++ mvOsOutput(" Analysis probe installed: No \n"); ++ } ++ ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 22: /* Suported AutoPreCharge */ ++ mvOsOutput("\nModul Attributes (SPD Byte 22): \n"); ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ if ( spdRawData[i] & BIT0 ) ++ mvOsOutput(" Early Ras Precharge: Yes \n"); ++ else ++ mvOsOutput(" Early Ras Precharge: No \n"); ++ ++ if ( spdRawData[i] & BIT1 ) ++ mvOsOutput(" AutoPreCharge: Yes \n"); ++ else ++ mvOsOutput(" AutoPreCharge: No \n"); ++ ++ if ( spdRawData[i] & BIT2 ) ++ mvOsOutput(" Precharge All: Yes \n"); ++ else ++ mvOsOutput(" Precharge All: No \n"); ++ ++ if ( spdRawData[i] & BIT3 ) ++ mvOsOutput(" Write 1/ReadBurst: Yes \n"); ++ else ++ mvOsOutput(" Write 1/ReadBurst: No \n"); ++ ++ if ( spdRawData[i] & BIT4 ) ++ mvOsOutput(" lower VCC tolerance: 5%%\n"); ++ else ++ mvOsOutput(" lower VCC tolerance: 10%%\n"); ++ ++ if ( spdRawData[i] & BIT5 ) ++ mvOsOutput(" upper VCC tolerance: 5%%\n"); ++ else ++ mvOsOutput(" upper VCC tolerance: 10%%\n"); ++ } ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) ++ { ++ if ( spdRawData[i] & BIT0 ) ++ mvOsOutput(" Supports Weak Driver: Yes \n"); ++ else ++ mvOsOutput(" Supports Weak Driver: No \n"); ++ ++ if ( !(spdRawData[i] & BIT4) ) ++ mvOsOutput(" lower VCC tolerance: 0.2V\n"); ++ ++ if ( !(spdRawData[i] & BIT5) ) ++ mvOsOutput(" upper VCC tolerance: 0.2V\n"); ++ ++ if ( spdRawData[i] & BIT6 ) ++ mvOsOutput(" Concurrent Auto Preharge: Yes \n"); ++ else ++ mvOsOutput(" Concurrent Auto Preharge: No \n"); ++ ++ if ( spdRawData[i] & BIT7 ) ++ mvOsOutput(" Supports Fast AP: Yes \n"); ++ else ++ mvOsOutput(" Supports Fast AP: No \n"); ++ } ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) ++ { ++ if ( spdRawData[i] & BIT0 ) ++ mvOsOutput(" Supports Weak Driver: Yes \n"); ++ else ++ mvOsOutput(" Supports Weak Driver: No \n"); ++ } ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 23: ++ /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */ ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ rightOfPoint = (spdRawData[i] & 0x0f) * 10; ++ ++ /* DDR2 addition of right of point */ ++ if ((spdRawData[i] & 0x0f) == 0xA) ++ { ++ rightOfPoint = 25; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xB) ++ { ++ rightOfPoint = 33; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xC) ++ { ++ rightOfPoint = 66; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xD) ++ { ++ rightOfPoint = 75; ++ } ++ ++ mvOsOutput("Minimum Cycle Time At 2nd highest CasLatancy" ++ "(0 = Not supported): %d.%d [ns]\n", ++ leftOfPoint, rightOfPoint ); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 24: /* Clock To Data Out 2nd highest Cas Latency Value*/ ++ div = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? 10:100; ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = time_tmp / div; ++ rightOfPoint = time_tmp % div; ++ mvOsOutput("Clock To Data Out (2nd CL value): %d.%d [ns]\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 25: ++ /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ leftOfPoint = (spdRawData[i] & 0xfc) >> 2; ++ rightOfPoint = (spdRawData[i] & 0x3) * 25; ++ } ++ else /* DDR1 or DDR2 */ ++ { ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ rightOfPoint = (spdRawData[i] & 0x0f) * 10; ++ ++ /* DDR2 addition of right of point */ ++ if ((spdRawData[i] & 0x0f) == 0xA) ++ { ++ rightOfPoint = 25; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xB) ++ { ++ rightOfPoint = 33; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xC) ++ { ++ rightOfPoint = 66; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xD) ++ { ++ rightOfPoint = 75; ++ } ++ } ++ mvOsOutput("Minimum Cycle Time At 3rd highest CasLatancy" ++ "(0 = Not supported): %d.%d [ns]\n", ++ leftOfPoint, rightOfPoint ); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 26: /* Clock To Data Out 3rd highest Cas Latency Value*/ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ leftOfPoint = (spdRawData[i] & 0xfc) >> 2; ++ rightOfPoint = (spdRawData[i] & 0x3) * 25; ++ } ++ else /* DDR1 or DDR2 */ ++ { ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = 0; ++ rightOfPoint = time_tmp; ++ } ++ mvOsOutput("Clock To Data Out (3rd CL value): %d.%2d[ns]\n", ++ leftOfPoint, rightOfPoint ); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 27: /* Minimum Row Precharge Time */ ++ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; ++ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? ++ 0xff : 0xfc; ++ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? ++ 0x00 : 0x03; ++ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); ++ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; ++ temp = ((leftOfPoint*100) + rightOfPoint);/* in 10ps Intervals*/ ++ trp_clocks = (temp + (busClkPs-1)) / busClkPs; ++ mvOsOutput("Minimum Row Precharge Time [ns]: %d.%d = " ++ "in Clk cycles %d\n", ++ leftOfPoint, rightOfPoint, trp_clocks); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 28: /* Minimum Row Active to Row Active Time */ ++ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; ++ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? ++ 0xff : 0xfc; ++ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? ++ 0x00 : 0x03; ++ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); ++ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; ++ temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ ++ trrd_clocks = (temp + (busClkPs-1)) / busClkPs; ++ mvOsOutput("Minimum Row Active -To- Row Active Delay [ns]: " ++ "%d.%d = in Clk cycles %d\n", ++ leftOfPoint, rightOfPoint, trp_clocks); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 29: /* Minimum Ras-To-Cas Delay */ ++ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; ++ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? ++ 0xff : 0xfc; ++ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? ++ 0x00 : 0x03; ++ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); ++ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; ++ temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ ++ trcd_clocks = (temp + (busClkPs-1) )/ busClkPs; ++ mvOsOutput("Minimum Ras-To-Cas Delay [ns]: %d.%d = " ++ "in Clk cycles %d\n", ++ leftOfPoint, rightOfPoint, trp_clocks); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 30: /* Minimum Ras Pulse Width */ ++ tras_clocks = (cas2ps(spdRawData[i])+(busClkPs-1)) / busClkPs; ++ mvOsOutput("Minimum Ras Pulse Width [ns]: %d = " ++ "in Clk cycles %d\n", spdRawData[i], tras_clocks); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 31: /* Module Bank Density */ ++ mvOsOutput("Module Bank Density (more than 1= Multisize-Module):"); ++ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ if (dimmInfo.dimmBankDensity & BIT0) ++ mvOsOutput("1GB, "); ++ if (dimmInfo.dimmBankDensity & BIT1) ++ mvOsOutput("8MB, "); ++ if (dimmInfo.dimmBankDensity & BIT2) ++ mvOsOutput("16MB, "); ++ if (dimmInfo.dimmBankDensity & BIT3) ++ mvOsOutput("32MB, "); ++ if (dimmInfo.dimmBankDensity & BIT4) ++ mvOsOutput("64MB, "); ++ if (dimmInfo.dimmBankDensity & BIT5) ++ mvOsOutput("128MB, "); ++ if (dimmInfo.dimmBankDensity & BIT6) ++ mvOsOutput("256MB, "); ++ if (dimmInfo.dimmBankDensity & BIT7) ++ mvOsOutput("512MB, "); ++ } ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) ++ { ++ if (dimmInfo.dimmBankDensity & BIT0) ++ mvOsOutput("1GB, "); ++ if (dimmInfo.dimmBankDensity & BIT1) ++ mvOsOutput("2GB, "); ++ if (dimmInfo.dimmBankDensity & BIT2) ++ mvOsOutput("16MB, "); ++ if (dimmInfo.dimmBankDensity & BIT3) ++ mvOsOutput("32MB, "); ++ if (dimmInfo.dimmBankDensity & BIT4) ++ mvOsOutput("64MB, "); ++ if (dimmInfo.dimmBankDensity & BIT5) ++ mvOsOutput("128MB, "); ++ if (dimmInfo.dimmBankDensity & BIT6) ++ mvOsOutput("256MB, "); ++ if (dimmInfo.dimmBankDensity & BIT7) ++ mvOsOutput("512MB, "); ++ } ++ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ ++ { ++ if (dimmInfo.dimmBankDensity & BIT0) ++ mvOsOutput("1GB, "); ++ if (dimmInfo.dimmBankDensity & BIT1) ++ mvOsOutput("2GB, "); ++ if (dimmInfo.dimmBankDensity & BIT2) ++ mvOsOutput("4GB, "); ++ if (dimmInfo.dimmBankDensity & BIT3) ++ mvOsOutput("8GB, "); ++ if (dimmInfo.dimmBankDensity & BIT4) ++ mvOsOutput("16GB, "); ++ if (dimmInfo.dimmBankDensity & BIT5) ++ mvOsOutput("128MB, "); ++ if (dimmInfo.dimmBankDensity & BIT6) ++ mvOsOutput("256MB, "); ++ if (dimmInfo.dimmBankDensity & BIT7) ++ mvOsOutput("512MB, "); ++ } ++ mvOsOutput("\n"); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 32: /* Address And Command Setup Time (measured in ns/1000) */ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ rightOfPoint = (spdRawData[i] & 0x0f); ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ if(leftOfPoint > 7) ++ { ++ leftOfPoint *= -1; ++ } ++ } ++ else /* DDR1 or DDR2 */ ++ { ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = time_tmp / 100; ++ rightOfPoint = time_tmp % 100; ++ } ++ mvOsOutput("Address And Command Setup Time [ns]: %d.%d\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 33: /* Address And Command Hold Time */ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ rightOfPoint = (spdRawData[i] & 0x0f); ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ if(leftOfPoint > 7) ++ { ++ leftOfPoint *= -1; ++ } ++ } ++ else /* DDR1 or DDR2 */ ++ { ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = time_tmp / 100; ++ rightOfPoint = time_tmp % 100; ++ } ++ mvOsOutput("Address And Command Hold Time [ns]: %d.%d\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 34: /* Data Input Setup Time */ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ rightOfPoint = (spdRawData[i] & 0x0f); ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ if(leftOfPoint > 7) ++ { ++ leftOfPoint *= -1; ++ } ++ } ++ else /* DDR1 or DDR2 */ ++ { ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = time_tmp / 100; ++ rightOfPoint = time_tmp % 100; ++ } ++ mvOsOutput("Data Input Setup Time [ns]: %d.%d\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 35: /* Data Input Hold Time */ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ rightOfPoint = (spdRawData[i] & 0x0f); ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ if(leftOfPoint > 7) ++ { ++ leftOfPoint *= -1; ++ } ++ } ++ else /* DDR1 or DDR2 */ ++ { ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = time_tmp / 100; ++ rightOfPoint = time_tmp % 100; ++ } ++ mvOsOutput("Data Input Hold Time [ns]: %d.%d\n\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 36: /* Relevant for DDR2 only: Write Recovery Time */ ++ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> 2); ++ rightOfPoint = (spdRawData[i] & maskRightOfPoint) * 25; ++ mvOsOutput("Write Recovery Time [ns]: %d.%d\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ } ++ ++} ++ ++ ++/* ++ * translate ns.ns/10 coding of SPD timing values ++ * into ps unit values ++ */ ++/******************************************************************************* ++* cas2ps - Translate x.y ns parameter to pico-seconds values ++* ++* DESCRIPTION: ++* This function translates x.y nano seconds to its value in pico seconds. ++* For example 3.75ns will return 3750. ++* ++* INPUT: ++* spd_byte - DIMM SPD byte. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* value in pico seconds. ++* ++*******************************************************************************/ ++static MV_U32 cas2ps(MV_U8 spd_byte) ++{ ++ MV_U32 ns, ns10; ++ ++ /* isolate upper nibble */ ++ ns = (spd_byte >> 4) & 0x0F; ++ /* isolate lower nibble */ ++ ns10 = (spd_byte & 0x0F); ++ ++ if( ns10 < 10 ) { ++ ns10 *= 10; ++ } ++ else if( ns10 == 10 ) ++ ns10 = 25; ++ else if( ns10 == 11 ) ++ ns10 = 33; ++ else if( ns10 == 12 ) ++ ns10 = 66; ++ else if( ns10 == 13 ) ++ ns10 = 75; ++ else ++ { ++ mvOsOutput("cas2ps Err. unsupported cycle time.\n"); ++ } ++ ++ return (ns*1000 + ns10*10); ++} ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,191 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvDram ++#define __INCmvDram ++ ++#include "ddr1_2/mvDramIf.h" ++#include "twsi/mvTwsi.h" ++ ++#define MAX_DIMM_NUM 2 ++#define SPD_SIZE 128 ++ ++/* Dimm spd offsets */ ++#define DIMM_MEM_TYPE 2 ++#define DIMM_ROW_NUM 3 ++#define DIMM_COL_NUM 4 ++#define DIMM_MODULE_BANK_NUM 5 ++#define DIMM_DATA_WIDTH 6 ++#define DIMM_VOLT_IF 8 ++#define DIMM_MIN_CC_AT_MAX_CAS 9 ++#define DIMM_ERR_CHECK_TYPE 11 ++#define DIMM_REFRESH_INTERVAL 12 ++#define DIMM_SDRAM_WIDTH 13 ++#define DIMM_ERR_CHECK_DATA_WIDTH 14 ++#define DIMM_MIN_CLK_DEL 15 ++#define DIMM_BURST_LEN_SUP 16 ++#define DIMM_DEV_BANK_NUM 17 ++#define DIMM_SUP_CAL 18 ++#define DIMM_DDR2_TYPE_INFORMATION 20 /* DDR2 only */ ++#define DIMM_BUF_ADDR_CONT_IN 21 ++#define DIMM_MIN_CC_AT_MAX_CAS_MINUS1 23 ++#define DIMM_MIN_CC_AT_MAX_CAS_MINUS2 25 ++#define DIMM_MIN_ROW_PRECHARGE_TIME 27 ++#define DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE 28 ++#define DIMM_MIN_RAS_TO_CAS_DELAY 29 ++#define DIMM_MIN_RAS_PULSE_WIDTH 30 ++#define DIMM_BANK_DENSITY 31 ++#define DIMM_MIN_WRITE_RECOVERY_TIME 36 ++#define DIMM_MIN_WRITE_TO_READ_CMD_DELAY 37 ++#define DIMM_MIN_READ_TO_PRECH_CMD_DELAY 38 ++#define DIMM_MIN_REFRESH_TO_ACTIVATE_CMD 42 ++ ++/* Dimm Memory Type values */ ++#define DIMM_MEM_TYPE_SDRAM 0x4 ++#define DIMM_MEM_TYPE_DDR1 0x7 ++#define DIMM_MEM_TYPE_DDR2 0x8 ++ ++#define DIMM_MODULE_MANU_OFFS 64 ++#define DIMM_MODULE_MANU_SIZE 8 ++#define DIMM_MODULE_VEN_OFFS 73 ++#define DIMM_MODULE_VEN_SIZE 25 ++#define DIMM_MODULE_ID_OFFS 99 ++#define DIMM_MODULE_ID_SIZE 18 ++ ++/* enumeration for voltage levels. */ ++typedef enum _mvDimmVoltageIf ++{ ++ TTL_5V_TOLERANT, ++ LVTTL, ++ HSTL_1_5V, ++ SSTL_3_3V, ++ SSTL_2_5V, ++ VOLTAGE_UNKNOWN, ++} MV_DIMM_VOLTAGE_IF; ++ ++ ++/* enumaration for SDRAM CAS Latencies. */ ++typedef enum _mvDimmSdramCas ++{ ++ SD_CL_1 =1, ++ SD_CL_2, ++ SD_CL_3, ++ SD_CL_4, ++ SD_CL_5, ++ SD_CL_6, ++ SD_CL_7, ++ SD_FAULT ++}MV_DIMM_SDRAM_CAS; ++ ++ ++/* DIMM information structure */ ++typedef struct _mvDimmInfo ++{ ++ MV_MEMORY_TYPE memoryType; /* DDR or SDRAM */ ++ ++ MV_U8 spdRawData[SPD_SIZE]; /* Content of SPD-EEPROM copied 1:1 */ ++ ++ /* DIMM dimensions */ ++ MV_U32 numOfRowAddr; ++ MV_U32 numOfColAddr; ++ MV_U32 numOfModuleBanks; ++ MV_U32 dataWidth; ++ MV_U32 errorCheckType; /* ECC , PARITY..*/ ++ MV_U32 sdramWidth; /* 4,8,16 or 32 */ ++ MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ ++ MV_U32 burstLengthSupported; ++ MV_U32 numOfBanksOnEachDevice; ++ MV_U32 suportedCasLatencies; ++ MV_U32 refreshInterval; ++ MV_U32 dimmBankDensity; ++ MV_U32 dimmTypeInfo; /* DDR2 only */ ++ MV_U32 dimmAttributes; ++ ++ /* DIMM timing parameters */ ++ MV_U32 minCycleTimeAtMaxCasLatPs; ++ MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; ++ MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; ++ MV_U32 minRowPrechargeTime; ++ MV_U32 minRowActiveToRowActive; ++ MV_U32 minRasToCasDelay; ++ MV_U32 minRasPulseWidth; ++ MV_U32 minWriteRecoveryTime; /* DDR2 only */ ++ MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ ++ MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ ++ MV_U32 minRefreshToActiveCmd; /* DDR2 only */ ++ ++ /* Parameters calculated from the extracted DIMM information */ ++ MV_U32 size; /* 16,64,128,256 or 512 MByte in MB units */ ++ MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit in MB units */ ++ MV_U32 numberOfDevices; ++ ++} MV_DIMM_INFO; ++ ++ ++MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo); ++MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo); ++MV_VOID dimmSpdPrint(MV_U32 dimmNum); ++MV_STATUS dimmSpdCpy(MV_VOID); ++ ++#endif /* __INCmvDram */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,1599 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++/* includes */ ++#include "ddr1_2/mvDramIf.h" ++#include "ctrlEnv/sys/mvCpuIf.h" ++ ++ ++ ++#ifdef MV_DEBUG ++#define DB(x) x ++#else ++#define DB(x) ++#endif ++ ++/* DRAM bank presence encoding */ ++#define BANK_PRESENT_CS0 0x1 ++#define BANK_PRESENT_CS0_CS1 0x3 ++#define BANK_PRESENT_CS0_CS2 0x5 ++#define BANK_PRESENT_CS0_CS1_CS2 0x7 ++#define BANK_PRESENT_CS0_CS2_CS3 0xd ++#define BANK_PRESENT_CS0_CS2_CS3_CS4 0xf ++ ++/* locals */ ++static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin); ++#if defined(MV_INC_BOARD_DDIM) ++static void sdramDDr2OdtConfig(MV_DRAM_BANK_INFO *pBankInfo); ++static MV_U32 dunitCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas); ++static MV_U32 sdramModeRegCalc(MV_U32 minCas); ++static MV_U32 sdramExtModeRegCalc(MV_DRAM_BANK_INFO *pBankInfo); ++static MV_U32 sdramAddrCtrlRegCalc(MV_DRAM_BANK_INFO *pBankInfo); ++static MV_U32 sdramConfigRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk); ++static MV_U32 minCasCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk, ++ MV_U32 forcedCl); ++static MV_U32 sdramTimeCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, ++ MV_U32 minCas, MV_U32 busClk); ++static MV_U32 sdramTimeCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, ++ MV_U32 busClk); ++ ++/******************************************************************************* ++* mvDramIfDetect - Prepare DRAM interface configuration values. ++* ++* DESCRIPTION: ++* This function implements the full DRAM detection and timing ++* configuration for best system performance. ++* Since this routine runs from a ROM device (Boot Flash), its stack ++* resides on RAM, that might be the system DRAM. Changing DRAM ++* configuration values while keeping vital data in DRAM is risky. That ++* is why the function does not preform the configuration setting but ++* prepare those in predefined 32bit registers (in this case IDMA ++* registers are used) for other routine to perform the settings. ++* The function will call for board DRAM SPD information for each DRAM ++* chip select. The function will then analyze those SPD parameters of ++* all DRAM banks in order to decide on DRAM configuration compatible ++* for all DRAM banks. ++* The function will set the CPU DRAM address decode registers. ++* Note: This routine prepares values that will overide configuration of ++* mvDramBasicAsmInit(). ++* ++* INPUT: ++* forcedCl - Forced CAL Latency. If equal to zero, do not force. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_STATUS mvDramIfDetect(MV_U32 forcedCl) ++{ ++ MV_U32 retVal = MV_OK; /* return value */ ++ MV_DRAM_BANK_INFO bankInfo[MV_DRAM_MAX_CS]; ++ MV_U32 busClk, size, base = 0, i, temp, deviceW, dimmW; ++ MV_U8 minCas; ++ MV_DRAM_DEC_WIN dramDecWin; ++ ++ dramDecWin.addrWin.baseHigh = 0; ++ ++ busClk = mvBoardSysClkGet(); ++ ++ if (0 == busClk) ++ { ++ mvOsPrintf("Dram: ERR. Can't detect system clock! \n"); ++ return MV_ERROR; ++ } ++ ++ /* Close DRAM banks except bank 0 (in case code is excecuting from it...) */ ++#if defined(MV_INCLUDE_SDRAM_CS1) ++ for(i= SDRAM_CS1; i < MV_DRAM_MAX_CS; i++) ++ mvCpuIfTargetWinEnable(i, MV_FALSE); ++#endif ++ ++ /* we will use bank 0 as the representative of the all the DRAM banks, */ ++ /* since bank 0 must exist. */ ++ for(i = 0; i < MV_DRAM_MAX_CS; i++) ++ { ++ /* if Bank exist */ ++ if(MV_OK == mvDramBankInfoGet(i, &bankInfo[i])) ++ { ++ /* check it isn't SDRAM */ ++ if(bankInfo[i].memoryType == MEM_TYPE_SDRAM) ++ { ++ mvOsPrintf("Dram: ERR. SDRAM type not supported !!!\n"); ++ return MV_ERROR; ++ } ++ /* All banks must support registry in order to activate it */ ++ if(bankInfo[i].registeredAddrAndControlInputs != ++ bankInfo[0].registeredAddrAndControlInputs) ++ { ++ mvOsPrintf("Dram: ERR. different Registered settings !!!\n"); ++ return MV_ERROR; ++ } ++ ++ /* Init the CPU window decode */ ++ /* Note that the size in Bank info is in MB units */ ++ /* Note that the Dimm width might be different then the device DRAM width */ ++ temp = MV_REG_READ(SDRAM_CONFIG_REG); ++ ++ deviceW = ((temp & SDRAM_DWIDTH_MASK) == SDRAM_DWIDTH_16BIT )? 16 : 32; ++ dimmW = bankInfo[0].dataWidth - (bankInfo[0].dataWidth % 16); ++ size = ((bankInfo[i].size << 20) / (dimmW/deviceW)); ++ ++ /* We can not change DRAM window settings while excecuting */ ++ /* code from it. That is why we skip the DRAM CS[0], saving */ ++ /* it to the ROM configuration routine */ ++ if(i == SDRAM_CS0) ++ { ++ MV_U32 sizeToReg; ++ ++ /* Translate the given window size to register format */ ++ sizeToReg = ctrlSizeToReg(size, SCSR_SIZE_ALIGNMENT); ++ ++ /* Size parameter validity check. */ ++ if (-1 == sizeToReg) ++ { ++ mvOsPrintf("mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n" ++ ,i); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Size is located at upper 16 bits */ ++ sizeToReg <<= SCSR_SIZE_OFFS; ++ ++ /* enable it */ ++ sizeToReg |= SCSR_WIN_EN; ++ ++ MV_REG_WRITE(DRAM_BUF_REG0, sizeToReg); ++ } ++ else ++ { ++ dramDecWin.addrWin.baseLow = base; ++ dramDecWin.addrWin.size = size; ++ dramDecWin.enable = MV_TRUE; ++ ++ if (MV_OK != mvDramIfWinSet(SDRAM_CS0 + i, &dramDecWin)) ++ { ++ mvOsPrintf("Dram: ERR. Fail to set bank %d!!!\n", ++ SDRAM_CS0 + i); ++ return MV_ERROR; ++ } ++ } ++ ++ base += size; ++ ++ /* update the suportedCasLatencies mask */ ++ bankInfo[0].suportedCasLatencies &= bankInfo[i].suportedCasLatencies; ++ ++ } ++ else ++ { ++ if( i == 0 ) /* bank 0 doesn't exist */ ++ { ++ mvOsPrintf("Dram: ERR. Fail to detect bank 0 !!!\n"); ++ return MV_ERROR; ++ } ++ else ++ { ++ DB(mvOsPrintf("Dram: Could not find bank %d\n", i)); ++ bankInfo[i].size = 0; /* Mark this bank as non exist */ ++ } ++ } ++ } ++ ++ /* calculate minimum CAS */ ++ minCas = minCasCalc(&bankInfo[0], busClk, forcedCl); ++ if (0 == minCas) ++ { ++ mvOsOutput("Dram: Warn: Could not find CAS compatible to SysClk %dMhz\n", ++ (busClk / 1000000)); ++ ++ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) ++ { ++ minCas = DDR2_CL_4; /* Continue with this CAS */ ++ mvOsPrintf("Set default CAS latency 4\n"); ++ } ++ else ++ { ++ minCas = DDR1_CL_3; /* Continue with this CAS */ ++ mvOsPrintf("Set default CAS latency 3\n"); ++ } ++ } ++ ++ /* calc SDRAM_CONFIG_REG and save it to temp register */ ++ temp = sdramConfigRegCalc(&bankInfo[0], busClk); ++ if(-1 == temp) ++ { ++ mvOsPrintf("Dram: ERR. sdramConfigRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ MV_REG_WRITE(DRAM_BUF_REG1, temp); ++ ++ /* calc SDRAM_MODE_REG and save it to temp register */ ++ temp = sdramModeRegCalc(minCas); ++ if(-1 == temp) ++ { ++ mvOsPrintf("Dram: ERR. sdramModeRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ MV_REG_WRITE(DRAM_BUF_REG2, temp); ++ ++ /* calc SDRAM_EXTENDED_MODE_REG and save it to temp register */ ++ temp = sdramExtModeRegCalc(&bankInfo[0]); ++ if(-1 == temp) ++ { ++ mvOsPrintf("Dram: ERR. sdramModeRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ MV_REG_WRITE(DRAM_BUF_REG10, temp); ++ ++ /* calc D_UNIT_CONTROL_LOW and save it to temp register */ ++ temp = dunitCtrlLowRegCalc(&bankInfo[0], minCas); ++ if(-1 == temp) ++ { ++ mvOsPrintf("Dram: ERR. dunitCtrlLowRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ MV_REG_WRITE(DRAM_BUF_REG3, temp); ++ ++ /* calc SDRAM_ADDR_CTRL_REG and save it to temp register */ ++ temp = sdramAddrCtrlRegCalc(&bankInfo[0]); ++ if(-1 == temp) ++ { ++ mvOsPrintf("Dram: ERR. sdramAddrCtrlRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ MV_REG_WRITE(DRAM_BUF_REG4, temp); ++ ++ /* calc SDRAM_TIMING_CTRL_LOW_REG and save it to temp register */ ++ temp = sdramTimeCtrlLowRegCalc(&bankInfo[0], minCas, busClk); ++ if(-1 == temp) ++ { ++ mvOsPrintf("Dram: ERR. sdramTimeCtrlLowRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ MV_REG_WRITE(DRAM_BUF_REG5, temp); ++ ++ /* calc SDRAM_TIMING_CTRL_HIGH_REG and save it to temp register */ ++ temp = sdramTimeCtrlHighRegCalc(&bankInfo[0], busClk); ++ if(-1 == temp) ++ { ++ mvOsPrintf("Dram: ERR. sdramTimeCtrlHighRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ MV_REG_WRITE(DRAM_BUF_REG6, temp); ++ ++ /* Config DDR2 On Die Termination (ODT) registers */ ++ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) ++ { ++ sdramDDr2OdtConfig(bankInfo); ++ } ++ ++ /* Note that DDR SDRAM Address/Control and Data pad calibration */ ++ /* settings is done in mvSdramIfConfig.s */ ++ ++ return retVal; ++} ++ ++/******************************************************************************* ++* minCasCalc - Calculate the Minimum CAS latency which can be used. ++* ++* DESCRIPTION: ++* Calculate the minimum CAS latency that can be used, base on the DRAM ++* parameters and the SDRAM bus Clock freq. ++* ++* INPUT: ++* busClk - the DRAM bus Clock. ++* pBankInfo - bank info parameters. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* The minimum CAS Latency. The function returns 0 if max CAS latency ++* supported by banks is incompatible with system bus clock frequancy. ++* ++*******************************************************************************/ ++static MV_U32 minCasCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk, ++ MV_U32 forcedCl) ++{ ++ MV_U32 count = 1, j; ++ MV_U32 busClkPs = 1000000000 / (busClk / 1000); /* in ps units */ ++ MV_U32 startBit, stopBit; ++ ++ /* DDR 1: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * ++ *********************************************************/ ++ ++ /* DDR 2: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * ++ *********************************************************/ ++ ++ ++ /* If we are asked to use the forced CAL */ ++ if (forcedCl) ++ { ++ mvOsPrintf("DRAM: Using forced CL %d.%d\n", (forcedCl / 10), ++ (forcedCl % 10)); ++ ++ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) ++ { ++ if (forcedCl == 30) ++ pBankInfo->suportedCasLatencies = 0x08; ++ else if (forcedCl == 40) ++ pBankInfo->suportedCasLatencies = 0x10; ++ else ++ { ++ mvOsPrintf("Forced CL %d.%d not supported. Set default CL 4\n", ++ (forcedCl / 10), (forcedCl % 10)); ++ pBankInfo->suportedCasLatencies = 0x10; ++ } ++ } ++ else ++ { ++ if (forcedCl == 15) ++ pBankInfo->suportedCasLatencies = 0x02; ++ else if (forcedCl == 20) ++ pBankInfo->suportedCasLatencies = 0x04; ++ else if (forcedCl == 25) ++ pBankInfo->suportedCasLatencies = 0x08; ++ else if (forcedCl == 30) ++ pBankInfo->suportedCasLatencies = 0x10; ++ else if (forcedCl == 40) ++ pBankInfo->suportedCasLatencies = 0x40; ++ else ++ { ++ mvOsPrintf("Forced CL %d.%d not supported. Set default CL 3\n", ++ (forcedCl / 10), (forcedCl % 10)); ++ pBankInfo->suportedCasLatencies = 0x10; ++ } ++ } ++ ++ return pBankInfo->suportedCasLatencies; ++ } ++ ++ /* go over the supported cas mask from Max Cas down and check if the */ ++ /* SysClk stands in its time requirments. */ ++ ++ ++ DB(mvOsPrintf("Dram: minCasCalc supported mask = %x busClkPs = %x \n", ++ pBankInfo->suportedCasLatencies,busClkPs )); ++ for(j = 7; j > 0; j--) ++ { ++ if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) ++ { ++ /* Reset the bits for CL incompatible for the sysClk */ ++ switch (count) ++ { ++ case 1: ++ if (pBankInfo->minCycleTimeAtMaxCasLatPs > busClkPs) ++ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); ++ count++; ++ break; ++ case 2: ++ if (pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps > busClkPs) ++ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); ++ count++; ++ break; ++ case 3: ++ if (pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps > busClkPs) ++ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); ++ count++; ++ break; ++ default: ++ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); ++ break; ++ } ++ } ++ } ++ ++ DB(mvOsPrintf("Dram: minCasCalc support = %x (after SysCC calc)\n", ++ pBankInfo->suportedCasLatencies )); ++ ++ /* SDRAM DDR1 controller supports CL 1.5 to 3.5 */ ++ /* SDRAM DDR2 controller supports CL 3 to 5 */ ++ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) ++ { ++ startBit = 3; /* DDR2 support CL start with CL3 (bit 3) */ ++ stopBit = 5; /* DDR2 support CL stops with CL5 (bit 5) */ ++ } ++ else ++ { ++ startBit = 1; /* DDR1 support CL start with CL1.5 (bit 3) */ ++ stopBit = 4; /* DDR1 support CL stops with CL3 (bit 4) */ ++ } ++ ++ for(j = startBit; j <= stopBit ; j++) ++ { ++ if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) ++ { ++ DB(mvOsPrintf("Dram: minCasCalc choose CAS %x \n",(BIT0 << j))); ++ return (BIT0 << j); ++ } ++ } ++ ++ return 0; ++} ++ ++/******************************************************************************* ++* sdramConfigRegCalc - Calculate sdram config register ++* ++* DESCRIPTION: Calculate sdram config register optimized value based ++* on the bank info parameters. ++* ++* INPUT: ++* pBankInfo - sdram bank parameters ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram config reg value. ++* ++*******************************************************************************/ ++static MV_U32 sdramConfigRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) ++{ ++ MV_U32 sdramConfig = 0; ++ MV_U32 refreshPeriod; ++ ++ busClk /= 1000000; /* we work with busClk in MHz */ ++ ++ sdramConfig = MV_REG_READ(SDRAM_CONFIG_REG); ++ ++ /* figure out the memory refresh internal */ ++ switch (pBankInfo->refreshInterval & 0xf) ++ { ++ case 0x0: /* refresh period is 15.625 usec */ ++ refreshPeriod = 15625; ++ break; ++ case 0x1: /* refresh period is 3.9 usec */ ++ refreshPeriod = 3900; ++ break; ++ case 0x2: /* refresh period is 7.8 usec */ ++ refreshPeriod = 7800; ++ break; ++ case 0x3: /* refresh period is 31.3 usec */ ++ refreshPeriod = 31300; ++ break; ++ case 0x4: /* refresh period is 62.5 usec */ ++ refreshPeriod = 62500; ++ break; ++ case 0x5: /* refresh period is 125 usec */ ++ refreshPeriod = 125000; ++ break; ++ default: /* refresh period undefined */ ++ mvOsPrintf("Dram: ERR. DRAM refresh period is unknown!\n"); ++ return -1; ++ } ++ ++ /* Now the refreshPeriod is in register format value */ ++ refreshPeriod = (busClk * refreshPeriod) / 1000; ++ ++ DB(mvOsPrintf("Dram: sdramConfigRegCalc calculated refresh interval %0x\n", ++ refreshPeriod)); ++ ++ /* make sure the refresh value is only 14 bits */ ++ if(refreshPeriod > SDRAM_REFRESH_MAX) ++ { ++ refreshPeriod = SDRAM_REFRESH_MAX; ++ DB(mvOsPrintf("Dram: sdramConfigRegCalc adjusted refresh interval %0x\n", ++ refreshPeriod)); ++ } ++ ++ /* Clear the refresh field */ ++ sdramConfig &= ~SDRAM_REFRESH_MASK; ++ ++ /* Set new value to refresh field */ ++ sdramConfig |= (refreshPeriod & SDRAM_REFRESH_MASK); ++ ++ /* registered DRAM ? */ ++ if ( pBankInfo->registeredAddrAndControlInputs ) ++ { ++ /* it's registered DRAM, so set the reg. DRAM bit */ ++ sdramConfig |= SDRAM_REGISTERED; ++ mvOsPrintf("DRAM Attribute: Registered address and control inputs.\n"); ++ } ++ ++ /* set DDR SDRAM devices configuration */ ++ sdramConfig &= ~SDRAM_DCFG_MASK; /* Clear Dcfg field */ ++ ++ switch (pBankInfo->sdramWidth) ++ { ++ case 8: /* memory is x8 */ ++ sdramConfig |= SDRAM_DCFG_X8_DEV; ++ DB(mvOsPrintf("Dram: sdramConfigRegCalc SDRAM device width x8\n")); ++ break; ++ case 16: ++ sdramConfig |= SDRAM_DCFG_X16_DEV; ++ DB(mvOsPrintf("Dram: sdramConfigRegCalc SDRAM device width x16\n")); ++ break; ++ default: /* memory width unsupported */ ++ mvOsPrintf("Dram: ERR. DRAM chip width is unknown!\n"); ++ return -1; ++ } ++ ++ /* Set static default settings */ ++ sdramConfig |= SDRAM_CONFIG_DV; ++ ++ DB(mvOsPrintf("Dram: sdramConfigRegCalc set sdramConfig to 0x%x\n", ++ sdramConfig)); ++ ++ return sdramConfig; ++} ++ ++/******************************************************************************* ++* sdramModeRegCalc - Calculate sdram mode register ++* ++* DESCRIPTION: Calculate sdram mode register optimized value based ++* on the bank info parameters and the minCas. ++* ++* INPUT: ++* minCas - minimum CAS supported. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram mode reg value. ++* ++*******************************************************************************/ ++static MV_U32 sdramModeRegCalc(MV_U32 minCas) ++{ ++ MV_U32 sdramMode; ++ ++ sdramMode = MV_REG_READ(SDRAM_MODE_REG); ++ ++ /* Clear CAS Latency field */ ++ sdramMode &= ~SDRAM_CL_MASK; ++ ++ mvOsPrintf("DRAM CAS Latency "); ++ ++ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) ++ { ++ switch (minCas) ++ { ++ case DDR2_CL_3: ++ sdramMode |= SDRAM_DDR2_CL_3; ++ mvOsPrintf("3.\n"); ++ break; ++ case DDR2_CL_4: ++ sdramMode |= SDRAM_DDR2_CL_4; ++ mvOsPrintf("4.\n"); ++ break; ++ case DDR2_CL_5: ++ sdramMode |= SDRAM_DDR2_CL_5; ++ mvOsPrintf("5.\n"); ++ break; ++ default: ++ mvOsPrintf("\nsdramModeRegCalc ERROR: Max. CL out of range\n"); ++ return -1; ++ } ++ sdramMode |= DDR2_MODE_REG_DV; ++ } ++ else /* DDR1 */ ++ { ++ switch (minCas) ++ { ++ case DDR1_CL_1_5: ++ sdramMode |= SDRAM_DDR1_CL_1_5; ++ mvOsPrintf("1.5\n"); ++ break; ++ case DDR1_CL_2: ++ sdramMode |= SDRAM_DDR1_CL_2; ++ mvOsPrintf("2\n"); ++ break; ++ case DDR1_CL_2_5: ++ sdramMode |= SDRAM_DDR1_CL_2_5; ++ mvOsPrintf("2.5\n"); ++ break; ++ case DDR1_CL_3: ++ sdramMode |= SDRAM_DDR1_CL_3; ++ mvOsPrintf("3\n"); ++ break; ++ case DDR1_CL_4: ++ sdramMode |= SDRAM_DDR1_CL_4; ++ mvOsPrintf("4\n"); ++ break; ++ default: ++ mvOsPrintf("\nsdramModeRegCalc ERROR: Max. CL out of range\n"); ++ return -1; ++ } ++ sdramMode |= DDR1_MODE_REG_DV; ++ } ++ ++ DB(mvOsPrintf("nsdramModeRegCalc register 0x%x\n", sdramMode )); ++ ++ return sdramMode; ++} ++ ++/******************************************************************************* ++* sdramExtModeRegCalc - Calculate sdram Extended mode register ++* ++* DESCRIPTION: ++* Return sdram Extended mode register value based ++* on the bank info parameters and bank presence. ++* ++* INPUT: ++* pBankInfo - sdram bank parameters ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram Extended mode reg value. ++* ++*******************************************************************************/ ++static MV_U32 sdramExtModeRegCalc(MV_DRAM_BANK_INFO *pBankInfo) ++{ ++ MV_U32 populateBanks = 0; ++ int bankNum; ++ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) ++ { ++ /* Represent the populate banks in binary form */ ++ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) ++ { ++ if (0 != pBankInfo[bankNum].size) ++ { ++ populateBanks |= (1 << bankNum); ++ } ++ } ++ ++ switch(populateBanks) ++ { ++ case(BANK_PRESENT_CS0): ++ return DDR_SDRAM_EXT_MODE_CS0_DV; ++ ++ case(BANK_PRESENT_CS0_CS1): ++ return DDR_SDRAM_EXT_MODE_CS0_DV; ++ ++ case(BANK_PRESENT_CS0_CS2): ++ return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; ++ ++ case(BANK_PRESENT_CS0_CS1_CS2): ++ return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; ++ ++ case(BANK_PRESENT_CS0_CS2_CS3): ++ return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; ++ ++ case(BANK_PRESENT_CS0_CS2_CS3_CS4): ++ return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; ++ ++ default: ++ mvOsPrintf("sdramExtModeRegCalc: Invalid DRAM bank presence\n"); ++ return -1; ++ } ++ } ++ return 0; ++} ++ ++/******************************************************************************* ++* dunitCtrlLowRegCalc - Calculate sdram dunit control low register ++* ++* DESCRIPTION: Calculate sdram dunit control low register optimized value based ++* on the bank info parameters and the minCas. ++* ++* INPUT: ++* pBankInfo - sdram bank parameters ++* minCas - minimum CAS supported. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram dunit control low reg value. ++* ++*******************************************************************************/ ++static MV_U32 dunitCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas) ++{ ++ MV_U32 dunitCtrlLow; ++ ++ dunitCtrlLow = MV_REG_READ(SDRAM_DUNIT_CTRL_REG); ++ ++ /* Clear StBurstDel field */ ++ dunitCtrlLow &= ~SDRAM_ST_BURST_DEL_MASK; ++ ++#ifdef MV_88W8660 ++ /* Clear address/control output timing field */ ++ dunitCtrlLow &= ~SDRAM_CTRL_POS_RISE; ++#endif /* MV_88W8660 */ ++ ++ DB(mvOsPrintf("Dram: dunitCtrlLowRegCalc\n")); ++ ++ /* For proper sample of read data set the Dunit Control register's */ ++ /* stBurstDel bits [27:24] */ ++ /********-********-********-********-********-********* ++ * CL=1.5 | CL=2 | CL=2.5 | CL=3 | CL=4 | CL=5 * ++ *********-********-********-********-********-********* ++Not Reg. * 0011 | 0011 | 0100 | 0100 | 0101 | TBD * ++ *********-********-********-********-********-********* ++Registered * 0100 | 0100 | 0101 | 0101 | 0110 | TBD * ++ *********-********-********-********-********-*********/ ++ ++ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) ++ { ++ switch (minCas) ++ { ++ case DDR2_CL_3: ++ /* registerd DDR SDRAM? */ ++ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) ++ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; ++ else ++ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; ++ break; ++ case DDR2_CL_4: ++ /* registerd DDR SDRAM? */ ++ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) ++ dunitCtrlLow |= 0x6 << SDRAM_ST_BURST_DEL_OFFS; ++ else ++ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; ++ break; ++ default: ++ mvOsPrintf("Dram: dunitCtrlLowRegCalc Max. CL out of range %d\n", ++ minCas); ++ return -1; ++ } ++ } ++ else /* DDR1 */ ++ { ++ switch (minCas) ++ { ++ case DDR1_CL_1_5: ++ /* registerd DDR SDRAM? */ ++ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) ++ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; ++ else ++ dunitCtrlLow |= 0x3 << SDRAM_ST_BURST_DEL_OFFS; ++ break; ++ case DDR1_CL_2: ++ /* registerd DDR SDRAM? */ ++ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) ++ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; ++ else ++ dunitCtrlLow |= 0x3 << SDRAM_ST_BURST_DEL_OFFS; ++ break; ++ case DDR1_CL_2_5: ++ /* registerd DDR SDRAM? */ ++ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) ++ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; ++ else ++ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; ++ break; ++ case DDR1_CL_3: ++ /* registerd DDR SDRAM? */ ++ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) ++ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; ++ else ++ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; ++ break; ++ case DDR1_CL_4: ++ /* registerd DDR SDRAM? */ ++ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) ++ dunitCtrlLow |= 0x6 << SDRAM_ST_BURST_DEL_OFFS; ++ else ++ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; ++ break; ++ default: ++ mvOsPrintf("Dram: dunitCtrlLowRegCalc Max. CL out of range %d\n", ++ minCas); ++ return -1; ++ } ++ ++ } ++ DB(mvOsPrintf("Dram: Reg dunit control low = %x\n", dunitCtrlLow )); ++ ++ return dunitCtrlLow; ++} ++ ++/******************************************************************************* ++* sdramAddrCtrlRegCalc - Calculate sdram address control register ++* ++* DESCRIPTION: Calculate sdram address control register optimized value based ++* on the bank info parameters and the minCas. ++* ++* INPUT: ++* pBankInfo - sdram bank parameters ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram address control reg value. ++* ++*******************************************************************************/ ++static MV_U32 sdramAddrCtrlRegCalc(MV_DRAM_BANK_INFO *pBankInfo) ++{ ++ MV_U32 addrCtrl = 0; ++ ++ /* Set Address Control register static configuration bits */ ++ addrCtrl = MV_REG_READ(SDRAM_ADDR_CTRL_REG); ++ ++ /* Set address control default value */ ++ addrCtrl |= SDRAM_ADDR_CTRL_DV; ++ ++ /* Clear DSize field */ ++ addrCtrl &= ~SDRAM_DSIZE_MASK; ++ ++ /* Note that density is in MB units */ ++ switch (pBankInfo->deviceDensity) ++ { ++ case 128: /* 128 Mbit */ ++ DB(mvOsPrintf("DRAM Device Density 128Mbit\n")); ++ addrCtrl |= SDRAM_DSIZE_128Mb; ++ break; ++ case 256: /* 256 Mbit */ ++ DB(mvOsPrintf("DRAM Device Density 256Mbit\n")); ++ addrCtrl |= SDRAM_DSIZE_256Mb; ++ break; ++ case 512: /* 512 Mbit */ ++ DB(mvOsPrintf("DRAM Device Density 512Mbit\n")); ++ addrCtrl |= SDRAM_DSIZE_512Mb; ++ break; ++ default: ++ mvOsPrintf("Dram: sdramAddrCtrl unsupported RAM-Device size %d\n", ++ pBankInfo->deviceDensity); ++ return -1; ++ } ++ ++ /* SDRAM address control */ ++ DB(mvOsPrintf("Dram: setting sdram address control with: %x \n", addrCtrl)); ++ ++ return addrCtrl; ++} ++ ++/******************************************************************************* ++* sdramTimeCtrlLowRegCalc - Calculate sdram timing control low register ++* ++* DESCRIPTION: ++* This function calculates sdram timing control low register ++* optimized value based on the bank info parameters and the minCas. ++* ++* INPUT: ++* pBankInfo - sdram bank parameters ++* busClk - Bus clock ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram timinf control low reg value. ++* ++*******************************************************************************/ ++static MV_U32 sdramTimeCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, ++ MV_U32 minCas, MV_U32 busClk) ++{ ++ MV_U32 tRp = 0; ++ MV_U32 tRrd = 0; ++ MV_U32 tRcd = 0; ++ MV_U32 tRas = 0; ++ MV_U32 tWr = 0; ++ MV_U32 tWtr = 0; ++ MV_U32 tRtp = 0; ++ ++ MV_U32 bankNum; ++ ++ busClk = busClk / 1000000; /* In MHz */ ++ ++ /* Scan all DRAM banks to find maximum timing values */ ++ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) ++ { ++ tRp = MV_MAX(tRp, pBankInfo[bankNum].minRowPrechargeTime); ++ tRrd = MV_MAX(tRrd, pBankInfo[bankNum].minRowActiveToRowActive); ++ tRcd = MV_MAX(tRcd, pBankInfo[bankNum].minRasToCasDelay); ++ tRas = MV_MAX(tRas, pBankInfo[bankNum].minRasPulseWidth); ++ } ++ ++ /* Extract timing (in ns) from SPD value. We ignore the tenth ns part. */ ++ /* by shifting the data two bits right. */ ++ tRp = tRp >> 2; /* For example 0x50 -> 20ns */ ++ tRrd = tRrd >> 2; ++ tRcd = tRcd >> 2; ++ ++ /* Extract clock cycles from time parameter. We need to round up */ ++ tRp = ((busClk * tRp) / 1000) + (((busClk * tRp) % 1000) ? 1 : 0); ++ /* Micron work around for 133MHz */ ++ if (busClk == 133) ++ tRp += 1; ++ DB(mvOsPrintf("Dram Timing Low: tRp = %d ", tRp)); ++ tRrd = ((busClk * tRrd) / 1000) + (((busClk * tRrd) % 1000) ? 1 : 0); ++ /* JEDEC min reqeirments tRrd = 2 */ ++ if (tRrd < 2) ++ tRrd = 2; ++ DB(mvOsPrintf("tRrd = %d ", tRrd)); ++ tRcd = ((busClk * tRcd) / 1000) + (((busClk * tRcd) % 1000) ? 1 : 0); ++ DB(mvOsPrintf("tRcd = %d ", tRcd)); ++ tRas = ((busClk * tRas) / 1000) + (((busClk * tRas) % 1000) ? 1 : 0); ++ DB(mvOsPrintf("tRas = %d ", tRas)); ++ ++ /* tWr and tWtr is different for DDR1 and DDR2. tRtp is only for DDR2 */ ++ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) ++ { ++ /* Scan all DRAM banks to find maximum timing values */ ++ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) ++ { ++ tWr = MV_MAX(tWr, pBankInfo[bankNum].minWriteRecoveryTime); ++ tWtr = MV_MAX(tWtr, pBankInfo[bankNum].minWriteToReadCmdDelay); ++ tRtp = MV_MAX(tRtp, pBankInfo[bankNum].minReadToPrechCmdDelay); ++ } ++ ++ /* Extract timing (in ns) from SPD value. We ignore the tenth ns */ ++ /* part by shifting the data two bits right. */ ++ tWr = tWr >> 2; /* For example 0x50 -> 20ns */ ++ tWtr = tWtr >> 2; ++ tRtp = tRtp >> 2; ++ ++ /* Extract clock cycles from time parameter. We need to round up */ ++ tWr = ((busClk * tWr) / 1000) + (((busClk * tWr) % 1000) ? 1 : 0); ++ DB(mvOsPrintf("tWr = %d ", tWr)); ++ tWtr = ((busClk * tWtr) / 1000) + (((busClk * tWtr) % 1000) ? 1 : 0); ++ /* JEDEC min reqeirments tWtr = 2 */ ++ if (tWtr < 2) ++ tWtr = 2; ++ DB(mvOsPrintf("tWtr = %d ", tWtr)); ++ tRtp = ((busClk * tRtp) / 1000) + (((busClk * tRtp) % 1000) ? 1 : 0); ++ /* JEDEC min reqeirments tRtp = 2 */ ++ if (tRtp < 2) ++ tRtp = 2; ++ DB(mvOsPrintf("tRtp = %d ", tRtp)); ++ } ++ else ++ { ++ tWr = ((busClk*SDRAM_TWR) / 1000) + (((busClk*SDRAM_TWR) % 1000)?1:0); ++ ++ if ((200 == busClk) || ((100 == busClk) && (DDR1_CL_1_5 == minCas))) ++ { ++ tWtr = 2; ++ } ++ else ++ { ++ tWtr = 1; ++ } ++ ++ tRtp = 2; /* Must be set to 0x1 (two cycles) when using DDR1 */ ++ } ++ ++ DB(mvOsPrintf("tWtr = %d\n", tWtr)); ++ ++ /* Note: value of 0 in register means one cycle, 1 means two and so on */ ++ return (((tRp - 1) << SDRAM_TRP_OFFS) | ++ ((tRrd - 1) << SDRAM_TRRD_OFFS) | ++ ((tRcd - 1) << SDRAM_TRCD_OFFS) | ++ ((tRas - 1) << SDRAM_TRAS_OFFS) | ++ ((tWr - 1) << SDRAM_TWR_OFFS) | ++ ((tWtr - 1) << SDRAM_TWTR_OFFS) | ++ ((tRtp - 1) << SDRAM_TRTP_OFFS)); ++} ++ ++/******************************************************************************* ++* sdramTimeCtrlHighRegCalc - Calculate sdram timing control high register ++* ++* DESCRIPTION: ++* This function calculates sdram timing control high register ++* optimized value based on the bank info parameters and the bus clock. ++* ++* INPUT: ++* pBankInfo - sdram bank parameters ++* busClk - Bus clock ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram timinf control high reg value. ++* ++*******************************************************************************/ ++static MV_U32 sdramTimeCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, ++ MV_U32 busClk) ++{ ++ MV_U32 tRfc; ++ MV_U32 timeNs = 0; ++ int bankNum; ++ MV_U32 sdramTw2wCyc = 0; ++ ++ busClk = busClk / 1000000; /* In MHz */ ++ ++ /* tRfc is different for DDR1 and DDR2. */ ++ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) ++ { ++ MV_U32 bankNum; ++ ++ /* Scan all DRAM banks to find maximum timing values */ ++ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) ++ timeNs = MV_MAX(timeNs, pBankInfo[bankNum].minRefreshToActiveCmd); ++ } ++ else ++ { ++ if (pBankInfo[0].deviceDensity == _1G) ++ { ++ timeNs = SDRAM_TRFC_1G; ++ } ++ else ++ { ++ if (200 == busClk) ++ { ++ timeNs = SDRAM_TRFC_64_512M_AT_200MHZ; ++ } ++ else ++ { ++ timeNs = SDRAM_TRFC_64_512M; ++ } ++ } ++ } ++ ++ tRfc = ((busClk * timeNs) / 1000) + (((busClk * timeNs) % 1000) ? 1 : 0); ++ ++ DB(mvOsPrintf("Dram Timing High: tRfc = %d\n", tRfc)); ++ ++ ++ /* Represent the populate banks in binary form */ ++ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) ++ { ++ if (0 != pBankInfo[bankNum].size) ++ sdramTw2wCyc++; ++ } ++ ++ /* If we have more the 1 bank then we need the TW2W in 1 for ODT switch */ ++ if (sdramTw2wCyc > 1) ++ sdramTw2wCyc = 1; ++ else ++ sdramTw2wCyc = 0; ++ ++ /* Note: value of 0 in register means one cycle, 1 means two and so on */ ++ return ((((tRfc - 1) & SDRAM_TRFC_MASK) << SDRAM_TRFC_OFFS) | ++ ((SDRAM_TR2R_CYC - 1) << SDRAM_TR2R_OFFS) | ++ ((SDRAM_TR2WW2R_CYC - 1) << SDRAM_TR2W_W2R_OFFS) | ++ (((tRfc - 1) >> 4) << SDRAM_TRFC_EXT_OFFS) | ++ (sdramTw2wCyc << SDRAM_TW2W_OFFS)); ++ ++} ++ ++/******************************************************************************* ++* sdramDDr2OdtConfig - Set DRAM DDR2 On Die Termination registers. ++* ++* DESCRIPTION: ++* This function config DDR2 On Die Termination (ODT) registers. ++* ODT configuration is done according to DIMM presence: ++* ++* Presence Ctrl Low Ctrl High Dunit Ctrl Ext Mode ++* CS0 0x84210000 0x00000000 0x0000780F 0x00000440 ++* CS0+CS1 0x84210000 0x00000000 0x0000780F 0x00000440 ++* CS0+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 ++* CS0+CS1+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 ++* CS0+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 ++* CS0+CS1+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 ++* ++* INPUT: ++* pBankInfo - bank info parameters. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* None ++*******************************************************************************/ ++static void sdramDDr2OdtConfig(MV_DRAM_BANK_INFO *pBankInfo) ++{ ++ MV_U32 populateBanks = 0; ++ MV_U32 odtCtrlLow, odtCtrlHigh, dunitOdtCtrl; ++ int bankNum; ++ ++ /* Represent the populate banks in binary form */ ++ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) ++ { ++ if (0 != pBankInfo[bankNum].size) ++ { ++ populateBanks |= (1 << bankNum); ++ } ++ } ++ ++ switch(populateBanks) ++ { ++ case(BANK_PRESENT_CS0): ++ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_DV; ++ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_DV; ++ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_DV; ++ break; ++ case(BANK_PRESENT_CS0_CS1): ++ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_DV; ++ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_DV; ++ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_DV; ++ break; ++ case(BANK_PRESENT_CS0_CS2): ++ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; ++ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; ++ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; ++ break; ++ case(BANK_PRESENT_CS0_CS1_CS2): ++ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; ++ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; ++ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; ++ break; ++ case(BANK_PRESENT_CS0_CS2_CS3): ++ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; ++ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; ++ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; ++ break; ++ case(BANK_PRESENT_CS0_CS2_CS3_CS4): ++ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; ++ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; ++ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; ++ break; ++ default: ++ mvOsPrintf("sdramDDr2OdtConfig: Invalid DRAM bank presence\n"); ++ return; ++ } ++ MV_REG_WRITE(DRAM_BUF_REG7, odtCtrlLow); ++ MV_REG_WRITE(DRAM_BUF_REG8, odtCtrlHigh); ++ MV_REG_WRITE(DRAM_BUF_REG9, dunitOdtCtrl); ++ return; ++} ++#endif /* defined(MV_INC_BOARD_DDIM) */ ++ ++/******************************************************************************* ++* mvDramIfWinSet - Set DRAM interface address decode window ++* ++* DESCRIPTION: ++* This function sets DRAM interface address decode window. ++* ++* INPUT: ++* target - System target. Use only SDRAM targets. ++* pAddrDecWin - SDRAM address window structure. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK ++* otherwise. ++*******************************************************************************/ ++MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) ++{ ++ MV_U32 baseReg=0,sizeReg=0; ++ MV_U32 baseToReg=0 , sizeToReg=0; ++ ++ /* Check parameters */ ++ if (!MV_TARGET_IS_DRAM(target)) ++ { ++ mvOsPrintf("mvDramIfWinSet: target %d is not SDRAM\n", target); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check if the requested window overlaps with current enabled windows */ ++ if (MV_TRUE == sdramIfWinOverlap(target, &pAddrDecWin->addrWin)) ++ { ++ mvOsPrintf("mvDramIfWinSet: ERR. Target %d overlaps\n", target); ++ return MV_BAD_PARAM; ++ } ++ ++ /* check if address is aligned to the size */ ++ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) ++ { ++ mvOsPrintf("mvDramIfWinSet:Error setting DRAM interface window %d."\ ++ "\nAddress 0x%08x is unaligned to size 0x%x.\n", ++ target, ++ pAddrDecWin->addrWin.baseLow, ++ pAddrDecWin->addrWin.size); ++ return MV_ERROR; ++ } ++ ++ /* read base register*/ ++ baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(target)); ++ ++ /* read size register */ ++ sizeReg = MV_REG_READ(SDRAM_SIZE_REG(target)); ++ ++ /* BaseLow[31:16] => base register [31:16] */ ++ baseToReg = pAddrDecWin->addrWin.baseLow & SCBAR_BASE_MASK; ++ ++ /* Write to address decode Base Address Register */ ++ baseReg &= ~SCBAR_BASE_MASK; ++ baseReg |= baseToReg; ++ ++ /* Translate the given window size to register format */ ++ sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, SCSR_SIZE_ALIGNMENT); ++ ++ /* Size parameter validity check. */ ++ if (-1 == sizeToReg) ++ { ++ mvOsPrintf("mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n",target); ++ return MV_BAD_PARAM; ++ } ++ ++ /* set size */ ++ sizeReg &= ~SCSR_SIZE_MASK; ++ /* Size is located at upper 16 bits */ ++ sizeReg |= (sizeToReg << SCSR_SIZE_OFFS); ++ ++ /* enable/Disable */ ++ if (MV_TRUE == pAddrDecWin->enable) ++ { ++ sizeReg |= SCSR_WIN_EN; ++ } ++ else ++ { ++ sizeReg &= ~SCSR_WIN_EN; ++ } ++ ++ /* 3) Write to address decode Base Address Register */ ++ MV_REG_WRITE(SDRAM_BASE_ADDR_REG(target), baseReg); ++ ++ /* Write to address decode Size Register */ ++ MV_REG_WRITE(SDRAM_SIZE_REG(target), sizeReg); ++ ++ return MV_OK; ++} ++/******************************************************************************* ++* mvDramIfWinGet - Get DRAM interface address decode window ++* ++* DESCRIPTION: ++* This function gets DRAM interface address decode window. ++* ++* INPUT: ++* target - System target. Use only SDRAM targets. ++* ++* OUTPUT: ++* pAddrDecWin - SDRAM address window structure. ++* ++* RETURN: ++* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK ++* otherwise. ++*******************************************************************************/ ++MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) ++{ ++ MV_U32 baseReg,sizeReg; ++ MV_U32 sizeRegVal; ++ ++ /* Check parameters */ ++ if (!MV_TARGET_IS_DRAM(target)) ++ { ++ mvOsPrintf("mvDramIfWinGet: target %d is Illigal\n", target); ++ return MV_ERROR; ++ } ++ ++ /* Read base and size registers */ ++ sizeReg = MV_REG_READ(SDRAM_SIZE_REG(target)); ++ baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(target)); ++ ++ sizeRegVal = (sizeReg & SCSR_SIZE_MASK) >> SCSR_SIZE_OFFS; ++ ++ pAddrDecWin->addrWin.size = ctrlRegToSize(sizeRegVal, ++ SCSR_SIZE_ALIGNMENT); ++ ++ /* Check if ctrlRegToSize returned OK */ ++ if (-1 == pAddrDecWin->addrWin.size) ++ { ++ mvOsPrintf("mvDramIfWinGet: size of target %d is Illigal\n", target); ++ return MV_ERROR; ++ } ++ ++ /* Extract base address */ ++ /* Base register [31:16] ==> baseLow[31:16] */ ++ pAddrDecWin->addrWin.baseLow = baseReg & SCBAR_BASE_MASK; ++ ++ pAddrDecWin->addrWin.baseHigh = 0; ++ ++ ++ if (sizeReg & SCSR_WIN_EN) ++ { ++ pAddrDecWin->enable = MV_TRUE; ++ } ++ else ++ { ++ pAddrDecWin->enable = MV_FALSE; ++ } ++ ++ return MV_OK; ++} ++/******************************************************************************* ++* mvDramIfWinEnable - Enable/Disable SDRAM address decode window ++* ++* DESCRIPTION: ++* This function enable/Disable SDRAM address decode window. ++* ++* INPUT: ++* target - System target. Use only SDRAM targets. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_ERROR in case function parameter are invalid, MV_OK otherewise. ++* ++*******************************************************************************/ ++MV_STATUS mvDramIfWinEnable(MV_TARGET target,MV_BOOL enable) ++{ ++ MV_DRAM_DEC_WIN addrDecWin; ++ ++ /* Check parameters */ ++ if (!MV_TARGET_IS_DRAM(target)) ++ { ++ mvOsPrintf("mvDramIfWinEnable: target %d is Illigal\n", target); ++ return MV_ERROR; ++ } ++ ++ if (enable == MV_TRUE) ++ { /* First check for overlap with other enabled windows */ ++ if (MV_OK != mvDramIfWinGet(target, &addrDecWin)) ++ { ++ mvOsPrintf("mvDramIfWinEnable:ERR. Getting target %d failed.\n", ++ target); ++ return MV_ERROR; ++ } ++ /* Check for overlapping */ ++ if (MV_FALSE == sdramIfWinOverlap(target, &(addrDecWin.addrWin))) ++ { ++ /* No Overlap. Enable address decode winNum window */ ++ MV_REG_BIT_SET(SDRAM_SIZE_REG(target), SCSR_WIN_EN); ++ } ++ else ++ { /* Overlap detected */ ++ mvOsPrintf("mvDramIfWinEnable: ERR. Target %d overlap detect\n", ++ target); ++ return MV_ERROR; ++ } ++ } ++ else ++ { /* Disable address decode winNum window */ ++ MV_REG_BIT_RESET(SDRAM_SIZE_REG(target), SCSR_WIN_EN); ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* sdramIfWinOverlap - Check if an address window overlap an SDRAM address window ++* ++* DESCRIPTION: ++* This function scan each SDRAM address decode window to test if it ++* overlapps the given address windoow ++* ++* INPUT: ++* target - SDRAM target where the function skips checking. ++* pAddrDecWin - The tested address window for overlapping with ++* SDRAM windows. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the given address window overlaps any enabled address ++* decode map, MV_FALSE otherwise. ++* ++*******************************************************************************/ ++static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin) ++{ ++ MV_TARGET targetNum; ++ MV_DRAM_DEC_WIN addrDecWin; ++ ++ for(targetNum = SDRAM_CS0; targetNum < MV_DRAM_MAX_CS ; targetNum++) ++ { ++ /* don't check our winNum or illegal targets */ ++ if (targetNum == target) ++ { ++ continue; ++ } ++ ++ /* Get window parameters */ ++ if (MV_OK != mvDramIfWinGet(targetNum, &addrDecWin)) ++ { ++ mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); ++ return MV_ERROR; ++ } ++ ++ /* Do not check disabled windows */ ++ if (MV_FALSE == addrDecWin.enable) ++ { ++ continue; ++ } ++ ++ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) ++ { ++ mvOsPrintf( ++ "sdramIfWinOverlap: Required target %d overlap winNum %d\n", ++ target, targetNum); ++ return MV_TRUE; ++ } ++ } ++ ++ return MV_FALSE; ++} ++ ++/******************************************************************************* ++* mvDramIfBankSizeGet - Get DRAM interface bank size. ++* ++* DESCRIPTION: ++* This function returns the size of a given DRAM bank. ++* ++* INPUT: ++* bankNum - Bank number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* DRAM bank size. If bank is disabled the function return '0'. In case ++* or paramter is invalid, the function returns -1. ++* ++*******************************************************************************/ ++MV_32 mvDramIfBankSizeGet(MV_U32 bankNum) ++{ ++ MV_DRAM_DEC_WIN addrDecWin; ++ ++ /* Check parameters */ ++ if (!MV_TARGET_IS_DRAM(bankNum)) ++ { ++ mvOsPrintf("mvDramIfBankBaseGet: bankNum %d is invalid\n", bankNum); ++ return -1; ++ } ++ /* Get window parameters */ ++ if (MV_OK != mvDramIfWinGet(bankNum, &addrDecWin)) ++ { ++ mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); ++ return -1; ++ } ++ ++ if (MV_TRUE == addrDecWin.enable) ++ { ++ return addrDecWin.addrWin.size; ++ } ++ else ++ { ++ return 0; ++ } ++} ++ ++ ++/******************************************************************************* ++* mvDramIfSizeGet - Get DRAM interface total size. ++* ++* DESCRIPTION: ++* This function get the DRAM total size. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* DRAM total size. In case or paramter is invalid, the function ++* returns -1. ++* ++*******************************************************************************/ ++MV_32 mvDramIfSizeGet(MV_VOID) ++{ ++ MV_U32 totalSize = 0, bankSize = 0, bankNum; ++ ++ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) ++ { ++ bankSize = mvDramIfBankSizeGet(bankNum); ++ ++ if (-1 == bankSize) ++ { ++ mvOsPrintf("Dram: mvDramIfSizeGet error with bank %d \n",bankNum); ++ return -1; ++ } ++ else ++ { ++ totalSize += bankSize; ++ } ++ } ++ ++ DB(mvOsPrintf("Dram: Total DRAM size is 0x%x \n",totalSize)); ++ ++ return totalSize; ++} ++ ++/******************************************************************************* ++* mvDramIfBankBaseGet - Get DRAM interface bank base. ++* ++* DESCRIPTION: ++* This function returns the 32 bit base address of a given DRAM bank. ++* ++* INPUT: ++* bankNum - Bank number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* DRAM bank size. If bank is disabled or paramter is invalid, the ++* function returns -1. ++* ++*******************************************************************************/ ++MV_32 mvDramIfBankBaseGet(MV_U32 bankNum) ++{ ++ MV_DRAM_DEC_WIN addrDecWin; ++ ++ /* Check parameters */ ++ if (!MV_TARGET_IS_DRAM(bankNum)) ++ { ++ mvOsPrintf("mvDramIfBankBaseGet: bankNum %d is invalid\n", bankNum); ++ return -1; ++ } ++ /* Get window parameters */ ++ if (MV_OK != mvDramIfWinGet(bankNum, &addrDecWin)) ++ { ++ mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); ++ return -1; ++ } ++ ++ if (MV_TRUE == addrDecWin.enable) ++ { ++ return addrDecWin.addrWin.baseLow; ++ } ++ else ++ { ++ return -1; ++ } ++} ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,179 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvDramIfh ++#define __INCmvDramIfh ++ ++/* includes */ ++#include "ddr1_2/mvDramIfRegs.h" ++#include "ddr1_2/mvDramIfConfig.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++ ++/* defines */ ++/* DRAM Timing parameters */ ++#define SDRAM_TWR 15 /* ns tWr */ ++#define SDRAM_TRFC_64_512M_AT_200MHZ 70 /* ns tRfc for dens 64-512 @ 200MHz */ ++#define SDRAM_TRFC_64_512M 75 /* ns tRfc for dens 64-512 */ ++#define SDRAM_TRFC_1G 120 /* ns tRfc for dens 1GB */ ++#define SDRAM_TR2R_CYC 1 /* cycle for tR2r */ ++#define SDRAM_TR2WW2R_CYC 1 /* cycle for tR2wW2r */ ++ ++/* typedefs */ ++ ++/* enumeration for memory types */ ++typedef enum _mvMemoryType ++{ ++ MEM_TYPE_SDRAM, ++ MEM_TYPE_DDR1, ++ MEM_TYPE_DDR2 ++}MV_MEMORY_TYPE; ++ ++/* enumeration for DDR1 supported CAS Latencies */ ++typedef enum _mvDimmDdr1Cas ++{ ++ DDR1_CL_1_5 = 0x02, ++ DDR1_CL_2 = 0x04, ++ DDR1_CL_2_5 = 0x08, ++ DDR1_CL_3 = 0x10, ++ DDR1_CL_4 = 0x40, ++ DDR1_CL_FAULT ++} MV_DIMM_DDR1_CAS; ++ ++/* enumeration for DDR2 supported CAS Latencies */ ++typedef enum _mvDimmDdr2Cas ++{ ++ DDR2_CL_3 = 0x08, ++ DDR2_CL_4 = 0x10, ++ DDR2_CL_5 = 0x20, ++ DDR2_CL_FAULT ++} MV_DIMM_DDR2_CAS; ++ ++ ++typedef struct _mvDramBankInfo ++{ ++ MV_MEMORY_TYPE memoryType; /* DDR1, DDR2 or SDRAM */ ++ ++ /* DIMM dimensions */ ++ MV_U32 numOfRowAddr; ++ MV_U32 numOfColAddr; ++ MV_U32 dataWidth; ++ MV_U32 errorCheckType; /* ECC , PARITY..*/ ++ MV_U32 sdramWidth; /* 4,8,16 or 32 */ ++ MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ ++ MV_U32 burstLengthSupported; ++ MV_U32 numOfBanksOnEachDevice; ++ MV_U32 suportedCasLatencies; ++ MV_U32 refreshInterval; ++ ++ /* DIMM timing parameters */ ++ MV_U32 minCycleTimeAtMaxCasLatPs; ++ MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; ++ MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; ++ MV_U32 minRowPrechargeTime; ++ MV_U32 minRowActiveToRowActive; ++ MV_U32 minRasToCasDelay; ++ MV_U32 minRasPulseWidth; ++ MV_U32 minWriteRecoveryTime; /* DDR2 only */ ++ MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ ++ MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ ++ MV_U32 minRefreshToActiveCmd; /* DDR2 only */ ++ ++ /* Parameters calculated from the extracted DIMM information */ ++ MV_U32 size; ++ MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit */ ++ MV_U32 numberOfDevices; ++ ++ /* DIMM attributes (MV_TRUE for yes) */ ++ MV_BOOL registeredAddrAndControlInputs; ++ ++}MV_DRAM_BANK_INFO; ++ ++/* This structure describes CPU interface address decode window */ ++typedef struct _mvDramIfDecWin ++{ ++ MV_ADDR_WIN addrWin; /* An address window*/ ++ MV_BOOL enable; /* Address decode window is enabled/disabled */ ++}MV_DRAM_DEC_WIN; ++ ++#include "ddr1_2/mvDram.h" ++ ++/* mvDramIf.h API list */ ++MV_VOID mvDramIfBasicAsmInit(MV_VOID); ++MV_STATUS mvDramIfDetect(MV_U32 forcedCl); ++MV_VOID _mvDramIfConfig(MV_VOID); ++ ++MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); ++MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); ++MV_STATUS mvDramIfWinEnable(MV_TARGET target,MV_BOOL enable); ++MV_32 mvDramIfBankSizeGet(MV_U32 bankNum); ++MV_32 mvDramIfBankBaseGet(MV_U32 bankNum); ++MV_32 mvDramIfSizeGet(MV_VOID); ++ ++#if 0 ++MV_STATUS mvDramIfMbusCtrlSet(MV_XBAR_TARGET *pPizzaArbArray); ++MV_STATUS mvDramIfMbusToutSet(MV_U32 timeout, MV_BOOL enable); ++#endif ++ ++#endif /* __INCmvDramIfh */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfBasicInit.S linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfBasicInit.S +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfBasicInit.S 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfBasicInit.S 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,988 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#define MV_ASMLANGUAGE ++#include "mvSysHwConfig.h" ++#include "mvOsAsm.h" ++#include "mvBoardEnvSpec.h" ++#include "mvCpuIfRegs.h" ++#include "mvDramIfConfig.h" ++#include "mvDramIfRegs.h" ++#include "pex/mvPexRegs.h" ++#include "pci/mvPciRegs.h" ++#include "mvCtrlEnvSpec.h" ++#include "mvCtrlEnvAsm.h" ++#include "cpu/mvCpuArm.h" ++#include "mvCommon.h" ++ ++/* defines */ ++ ++#if !defined(MV_INC_BOARD_DDIM) ++.globl dramBoot1 ++dramBoot1: ++ .word 0 ++ ++/****************************************************************************** ++* ++* ++* ++* ++*******************************************************************************/ ++#if defined(DB_PRPMC) || defined(DB_PEX_PCI) || defined(DB_MNG) ++ ++/* PEX_PCI and PRPMC boards 256 MB*/ ++#define STATIC_SDRAM0_BANK0_SIZE 0x0fff0001 ++#define STATIC_SDRAM_CONFIG 0x03248400 ++#define STATIC_SDRAM_MODE 0x62 ++#define STATIC_DUNIT_CTRL_LOW 0x4041000 ++#define STATIC_SDRAM_ADDR_CTRL 0x00000020 ++#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220 ++#define STATIC_SDRAM_TIME_CTRL_HI 0x0000030F ++#define STATIC_SDRAM_ODT_CTRL_LOW 0x0 ++#define STATIC_SDRAM_ODT_CTRL_HI 0x0 ++#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0 ++#define STATIC_SDRAM_EXT_MODE 0x0 ++ ++#elif defined(DB_FPGA) ++ ++/* FPGA DC boards 256 MB*/ ++#define STATIC_SDRAM0_BANK0_SIZE 0x0fff0001 ++#define STATIC_SDRAM_CONFIG 0x03208400 /* 32bit */ ++#define STATIC_SDRAM_MODE 0x22 ++#define STATIC_DUNIT_CTRL_LOW 0x03041000 ++#define STATIC_SDRAM_ADDR_CTRL 0x00000020 ++#define STATIC_SDRAM_TIME_CTRL_LOW 0x11112220 ++#define STATIC_SDRAM_TIME_CTRL_HI 0x0000000D ++#define STATIC_SDRAM_ODT_CTRL_LOW 0x0 ++#define STATIC_SDRAM_ODT_CTRL_HI 0x0 ++#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0 ++#define STATIC_SDRAM_EXT_MODE 0x1 ++ ++#elif defined(RD_88F6183GP) || defined(DB_CUSTOMER) ++ ++/* Customer 1 DDR2 2 devices 512Mbit by 16 bit */ ++#define STATIC_SDRAM0_BANK0_SIZE 0x07ff0001 ++#define STATIC_SDRAM_CONFIG 0x03158400 ++#define STATIC_SDRAM_MODE 0x452 ++#define STATIC_DUNIT_CTRL_LOW 0x06041000 ++#define STATIC_SDRAM_ADDR_CTRL 0x00000020 ++#define STATIC_SDRAM_TIME_CTRL_LOW 0x11912220 ++#define STATIC_SDRAM_TIME_CTRL_HI 0x00000502 ++#define STATIC_SDRAM_ODT_CTRL_LOW 0x00010000 ++#define STATIC_SDRAM_ODT_CTRL_HI 0x00000002 ++#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x00000601 ++#define STATIC_SDRAM_EXT_MODE 0x00000440 ++ ++ ++#elif defined(RD_88F6183AP) ++ ++/* DDR2 1 devices 512Mbit by 16 bit */ ++#define STATIC_SDRAM0_BANK0_SIZE 0x03ff0001 ++#define STATIC_SDRAM_CONFIG 0x1f154400 ++#define STATIC_SDRAM_MODE 0x432 ++#define STATIC_DUNIT_CTRL_LOW 0x04041000 ++#define STATIC_SDRAM_ADDR_CTRL 0x00000020 ++#define STATIC_SDRAM_TIME_CTRL_LOW 0x11912220 ++#define STATIC_SDRAM_TIME_CTRL_HI 0x00000502 ++#define STATIC_SDRAM_ODT_CTRL_LOW 0x00010000 ++#define STATIC_SDRAM_ODT_CTRL_HI 0x00000002 ++#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x00000601 ++#define STATIC_SDRAM_EXT_MODE 0x00000440 ++ ++/* 6082L MARVELL DIMM */ ++#elif defined(DB_88F6082LBP) ++#define STATIC_SDRAM0_BANK0_SIZE 0x07ff0001 ++#define STATIC_SDRAM_CONFIG 0x7f158400 ++#define STATIC_SDRAM_MODE 0x432 ++#define STATIC_DUNIT_CTRL_LOW 0x04041040 ++#define STATIC_SDRAM_ADDR_CTRL 0x00000020 ++#define STATIC_SDRAM_TIME_CTRL_LOW 0x11612220 ++#define STATIC_SDRAM_TIME_CTRL_HI 0x00000501 ++#define STATIC_SDRAM_ODT_CTRL_LOW 0x00010000 ++#define STATIC_SDRAM_ODT_CTRL_HI 0x00000002 ++#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x00000a01 ++#define STATIC_SDRAM_EXT_MODE 0x00000440 ++ ++#elif defined(RD_88W8660_AP82S) ++ ++/* Shark RD */ ++ ++#if defined(MV_DRAM_32M) ++#define STATIC_SDRAM0_BANK0_SIZE 0x01ff0001 ++#define STATIC_SDRAM_ADDR_CTRL 0x00000010 ++#elif defined(MV_DRAM_16M) ++ ++#define STATIC_SDRAM0_BANK0_SIZE 0x00ff0001 ++#define STATIC_SDRAM_ADDR_CTRL 0x00000000 ++ ++#else ++#error "NO DDR size selected" ++#endif ++ ++#define STATIC_SDRAM_CONFIG 0x03144400 ++#define STATIC_SDRAM_MODE 0x62 ++#define STATIC_DUNIT_CTRL_LOW 0x4041000 ++ ++#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220 ++#define STATIC_SDRAM_TIME_CTRL_HI 0x0000040b ++#define STATIC_SDRAM_ODT_CTRL_LOW 0x0 ++#define STATIC_SDRAM_ODT_CTRL_HI 0x0 ++#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0 ++#define STATIC_SDRAM_EXT_MODE 0x0 ++ ++#elif defined(RD_88W8660) ++ ++/* Shark RD */ ++#define STATIC_SDRAM0_BANK0_SIZE 0x03ff0001 ++#define STATIC_SDRAM_CONFIG 0x03144400 ++#define STATIC_SDRAM_MODE 0x62 ++#define STATIC_DUNIT_CTRL_LOW 0x4041000 ++#define STATIC_SDRAM_ADDR_CTRL 0x00000010 ++#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220 ++#define STATIC_SDRAM_TIME_CTRL_HI 0x0000040b ++#define STATIC_SDRAM_ODT_CTRL_LOW 0x0 ++#define STATIC_SDRAM_ODT_CTRL_HI 0x0 ++#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0 ++#define STATIC_SDRAM_EXT_MODE 0x0 ++ ++#else /* NAS */ ++ ++ ++#if defined(RD_88F5182) ++ ++#if defined(MV_88F5082) ++#define STATIC_SDRAM0_BANK0_SIZE 0x3ff0001 ++#define STATIC_SDRAM_ADDR_CTRL 0x20 ++#else ++#define STATIC_SDRAM0_BANK0_SIZE 0x7ff0001 ++#define STATIC_SDRAM_ADDR_CTRL 0x20 ++#endif ++ ++#elif defined(RD_88F5182_3) ++ ++#if defined(MV_88F5082) ++#define STATIC_SDRAM0_BANK0_SIZE 0x3ff0001 ++#define STATIC_SDRAM_ADDR_CTRL 0x20 ++#else ++#define STATIC_SDRAM0_BANK0_SIZE 0x7ff0001 ++#define STATIC_SDRAM_ADDR_CTRL 0x20 ++#endif ++ ++#else ++ ++#define STATIC_SDRAM0_BANK0_SIZE 0x1ff0001 ++#define STATIC_SDRAM_ADDR_CTRL 0x0 ++ ++#endif ++ ++#if defined(MV_88F5082) ++#define STATIC_SDRAM_CONFIG 0x3144400 ++#else ++#define STATIC_SDRAM_CONFIG 0x3148400 ++#endif ++#define STATIC_SDRAM_MODE 0x62 ++#define STATIC_DUNIT_CTRL_LOW 0x4041000 ++#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220 ++#define STATIC_SDRAM_TIME_CTRL_HI 0x40c ++#define STATIC_SDRAM_ODT_CTRL_LOW 0x0 ++#define STATIC_SDRAM_ODT_CTRL_HI 0x0 ++#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0 ++#define STATIC_SDRAM_EXT_MODE 0x0 ++ ++#endif ++ ++ .globl _mvDramIfStaticInit ++_mvDramIfStaticInit: ++ ++ mov r11, LR /* Save link register */ ++ mov r10, r2 ++ ++ /* If we boot from NAND jump to DRAM sddress */ ++ ++ mov r5, #1 ++ ldr r6, =dramBoot1 ++ str r5, [r6] /* We started executing from DRAM */ ++ ++ ldr r6, dramBoot1 ++ cmp r6, #0 ++ bne 1f ++ ++ ++ /* set all dram windows to 0 */ ++ mov r6, #0 ++ MV_REG_WRITE_ASM(r6, r5, 0x1504) ++ MV_REG_WRITE_ASM(r6, r5, 0x150c) ++ MV_REG_WRITE_ASM(r6, r5, 0x1514) ++ MV_REG_WRITE_ASM(r6, r5, 0x151c) ++ ++ /* set all dram configuration in temp registers */ ++ ldr r6, = STATIC_SDRAM0_BANK0_SIZE ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG0) ++ ldr r6, = STATIC_SDRAM_CONFIG ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG1) ++ ldr r6, = STATIC_SDRAM_MODE ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG2) ++ ldr r6, = STATIC_DUNIT_CTRL_LOW ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG3) ++ ldr r6, = STATIC_SDRAM_ADDR_CTRL ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG4) ++ ldr r6, = STATIC_SDRAM_TIME_CTRL_LOW ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG5) ++ ldr r6, = STATIC_SDRAM_TIME_CTRL_HI ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG6) ++ ldr r6, = STATIC_SDRAM_ODT_CTRL_LOW ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG7) ++ ldr r6, = STATIC_SDRAM_ODT_CTRL_HI ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG8) ++ ldr r6, = STATIC_SDRAM_DUNIT_ODT_CTRL ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG9) ++ ldr r6, = STATIC_SDRAM_EXT_MODE ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG10) ++ ++ mov sp, #0 ++ bl _mvDramIfConfig ++1: ++ mov r2, r10 ++ mov PC, r11 /* r11 is saved link register */ ++ ++#else /* #if !defined(MV_INC_BOARD_DDIM) */ ++ ++.globl dramBoot1 ++dramBoot1: ++ .word 0 ++ ++/******************************************************************************* ++* mvDramIfBasicInit - Basic initialization of DRAM interface ++* ++* DESCRIPTION: ++* The function will initialize the DRAM for basic usage. The function ++* will use the TWSI assembly API to extract DIMM parameters according ++* to which DRAM interface will be initialized. ++* The function referes to the following DRAM parameters: ++* 1) DIMM is registered or not. ++* 2) DIMM width detection. ++* 3) DIMM density. ++* ++* INPUT: ++* r3 - required size for initial DRAM. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++* Note: ++* r4 holds I2C EEPROM address ++* r5 holds SDRAM register base address ++* r7 holds returned values ++* r8 holds SDRAM various configuration registers value. ++* r11 holds return function address. ++*******************************************************************************/ ++/* Setting the offsets of the I2C registers */ ++#define NUM_OF_ROWS_OFFSET 3 ++#define NUM_OF_COLS_OFFSET 4 ++#define NUM_OF_RANKS 5 ++#define SDRAM_WIDTH_OFFSET 13 ++#define NUM_OF_BANKS_OFFSET 17 ++#define SUPPORTED_CL_OFFSET 18 ++#define DIMM_TYPE_INFO_OFFSET 20 /* DDR2 only */ ++#define SDRAM_MODULES_ATTR_OFFSET 21 ++ ++#define DRAM_DEV_DENSITY_128M 0x080 ++#define DRAM_DEV_DENSITY_256M 0x100 ++#define DRAM_DEV_DENSITY_512M 0x200 ++ .globl _mvDramIfBasicInit ++ .extern _i2cInit ++ ++_mvDramIfBasicInit: ++ ++ mov r11, LR /* Save link register */ ++ ++ mov r5, #1 ++ ldr r8, =dramBoot1 ++ str r5, [r8] /* We started executing from DRAM */ ++ ++ /* If we boot from NAND jump to DRAM sddress */ ++ ldr r8, dramBoot1 ++ cmp r8, #0 ++ movne pc, r11 ++ ++ ++ ++ bl _i2cInit /* Initialize TWSI master */ ++ ++ /* Get default SDRAM Config values */ ++ MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG) ++ bic r8, r8, #SDRAM_DCFG_MASK ++ ++ ++ /* Read device ID */ ++ MV_CTRL_MODEL_GET_ASM(r4, r5); ++ ++ /* Return if OrionN */ ++ ldr r5, =MV_5180_DEV_ID ++ cmp r4, r5 ++ beq cat_through_end ++ ++ /* Return if Orion1 */ ++ ldr r5, =MV_5181_DEV_ID ++ cmp r4, r5 ++ beq cat_through_end ++ ++ /* Return if Nas */ ++ ldr r5, =MV_5182_DEV_ID ++ cmp r4, r5 ++ beq cat_through_end ++ ++ /* Return if Shark */ ++ ldr r5, =MV_8660_DEV_ID ++ cmp r4, r5 ++ beq cat_through_end ++ ++ /* goto calcConfigReg if bigger than Orion2*/ ++ ldr r5, =MV_5281_DEV_ID ++ cmp r4, r5 ++ bne cat_through ++ ++cat_through: ++ /* set cat through - for better performance - in orion2 b0 and higher*/ ++ orr r8, r8, #SDRAM_CATTHR_EN ++ ++cat_through_end: ++ ++ ++ /* Get registered/non registered info from DIMM */ ++ bl _is_Registered ++ beq nonRegistered ++ ++setRegistered: ++ orr r8, r8, #SDRAM_REGISTERED /* Set registered bit(17) */ ++ ++nonRegistered: ++ /* Get SDRAM width */ ++ bl _get_width ++ ++ orr r6, r8, #SDRAM_DCFG_X16_DEV /* x16 devices */ ++ cmp r7, #16 ++ beq setConfigReg ++ ++ orr r6, r8, #SDRAM_DCFG_X8_DEV /* x8 devices */ ++ cmp r7, #8 ++ beq setConfigReg ++ ++ /* This is an error. return */ ++ b exit_ddrAutoConfig ++ ++setConfigReg: ++ mov r8, r6 ++ ldr r6, =SDRAM_CONFIG_DV ++ orr r8, r8, r6 /* Add default settings */ ++ mov r6, r8 /* Do not swap r8 content */ ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_CONFIG_REG) ++ ++ /* Set maximum CL supported by DIMM */ ++ bl _get_CAL ++ ++ /* r7 is DIMM supported CAS (e.g: 3 --> 0x1C) */ ++ clz r6, r7 ++ rsb r6, r6, #31 /* r6 = the bit number of MAX CAS supported */ ++ ++ /* Check the DDR version */ ++ tst r8, #SDRAM_DTYPE_DDR2 ++ bne casDdr2 ++ ++casDdr1: ++ ldr r7, =3 /* stBurstDel field value */ ++ ldr r8, =0x52 /* Assuming MAX CL = 1.5 */ ++ cmp r6, #1 /* If CL = 1.5 break */ ++ beq setModeReg ++ ++ ldr r7, =3 /* stBurstDel field value */ ++ ldr r8, =0x22 /* Assuming MAX CL = 2 */ ++ cmp r6, #2 /* If CL = 2 break */ ++ beq setModeReg ++ ++ ldr r7, =4 /* stBurstDel field value */ ++ ldr r8, =0x62 /* Assuming MAX CL = 2.5 */ ++ cmp r6, #3 /* If CL = 2.5 break */ ++ beq setModeReg ++ ++ ldr r7, =4 /* stBurstDel field value */ ++ ldr r8, =0x32 /* Assuming MAX CL = 3 */ ++ cmp r6, #4 /* If CL = 3 break */ ++ beq setModeReg ++ ++ ldr r7, =5 /* stBurstDel field value */ ++ ldr r8, =0x42 /* Assuming MAX CL = 4 */ ++ cmp r6, #6 /* If CL = 4 break */ ++ b setModeReg ++ ++ b exit_ddrAutoConfig /* This is an error !! */ ++ ++casDdr2: ++ ldr r7, =4 /* stBurstDel field value */ ++ ldr r8, =0x32 /* Assuming MAX CL = 3 */ ++ cmp r6, #3 /* If CL = 3 break */ ++ beq casDdr2Cont ++ ++ ldr r7, =5 /* stBurstDel field value */ ++ ldr r8, =0x42 /* Assuming MAX CL = 4 */ ++ cmp r6, #4 /* If CL = 4 break */ ++ beq casDdr2Cont ++ ++ /* CL 5 currently unsupported. We use CL 4 instead */ ++ ldr r7, =5 /* stBurstDel field value */ ++ ldr r8, =0x42 /* Assuming MAX CL = 5 */ ++ cmp r6, #5 /* If CL = 5 break */ ++ beq casDdr2Cont ++ ++ b exit_ddrAutoConfig /* This is an error !! */ ++casDdr2Cont: ++ /* Write recovery for auto-precharge relevant only in DDR2 */ ++ orr r8, r8, #0x400 /* Default value */ ++ ++setModeReg: ++ /* The CPU must not attempt to change the SDRAM Mode register setting */ ++ /* prior to DRAM controller completion of the DRAM initialization */ ++ /* sequence. To guarantee this restriction, it is recommended that */ ++ /* the CPU sets the SDRAM Operation register to NOP command, performs */ ++ /* read polling until the register is back in Normal operation value, */ ++ /* and then sets SDRAM Mode register to it's new value. */ ++ ++ /* write 'nop' to SDRAM operation */ ++ mov r6, #0x5 /* 'NOP' command */ ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG) ++ ++ /* poll SDRAM operation. Make sure its back to normal operation */ ++_sdramOpPoll1: ++ ldr r6, [r5] ++ cmp r6, #0 /* '0' = Normal SDRAM Mode */ ++ bne _sdramOpPoll1 ++ ++ /* Now its safe to write new value to SDRAM Mode register */ ++ MV_REG_WRITE_ASM (r8, r5, SDRAM_MODE_REG) ++ ++ /* Make the Dunit write the DRAM its new mode */ ++ mov r6, #0x3 /* Mode Register Set command */ ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG) ++ ++ /* poll SDRAM operation. Make sure its back to normal operation */ ++_sdramOpPoll2: ++ ldr r6, [r5] ++ cmp r6, #0 /* '0' = Normal SDRAM Mode */ ++ bne _sdramOpPoll2 ++ ++ /* Set Dunit control register according to max CL detected */ ++ /* If we use registered DIMM, add 1 to stBurstDel */ ++ MV_REG_READ_ASM (r6, r5, SDRAM_CONFIG_REG) ++ tst r6, #SDRAM_REGISTERED ++ beq setDunitReg ++ add r7, r7, #1 ++ ++setDunitReg: ++ ldr r6, =SDRAM_DUNIT_CTRL_LOW_DV ++ orr r6, r6, r7, LSL #SDRAM_ST_BURST_DEL_OFFS ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) ++ ++ ++ /* DIMM density configuration*/ ++ /* Density = (1 << (rowNum + colNum)) * dramWidth * dramBankNum */ ++Density: ++ bl _getDensity ++ mov r8, r7 ++ mov r8, r8, LSR #20 /* Move density 20 bits to the right */ ++ /* For example 0x10000000 --> 0x1000 */ ++ ++ mov r6, #0x00 ++ cmp r8, #DRAM_DEV_DENSITY_128M ++ beq densCont ++ ++ mov r6, #0x10 ++ cmp r8, #DRAM_DEV_DENSITY_256M ++ beq densCont ++ ++ mov r6, #0x20 ++ cmp r8, #DRAM_DEV_DENSITY_512M ++ beq densCont ++ ++ /* This is an error. return */ ++ b exit_ddrAutoConfig ++ ++densCont: ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_REG) ++ ++ /* Config DDR2 registers (Extended mode, ODTs and pad calibration) */ ++ MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG) ++ tst r8, #SDRAM_DTYPE_DDR2 ++ beq _extModeODTEnd ++ ++ ++ /* Set DDR Extended Mode register for working with CS[0] */ ++ /* write 'nop' to SDRAM operation */ ++ mov r6, #0x5 /* 'NOP' command */ ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG) ++ ++ /* poll SDRAM operation. Make sure its back to normal operation */ ++_sdramOpPoll3: ++ ldr r6, [r5] ++ cmp r6, #0 /* '0' = Normal SDRAM Mode */ ++ bne _sdramOpPoll3 ++ ++ /* Now its safe to write new value to SDRAM Extended Mode register */ ++ ldr r6, =DDR_SDRAM_EXT_MODE_CS0_DV ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_EXTENDED_MODE_REG) ++ ++ /* Make the Dunit write the DRAM its new extended mode */ ++ mov r6, #0x4 /* Extended Mode Register Set command */ ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG) ++ ++ /* poll SDRAM operation. Make sure its back to normal operation */ ++_sdramOpPoll4: ++ ldr r6, [r5] ++ cmp r6, #0 /* '0' = Normal SDRAM Mode */ ++ bne _sdramOpPoll4 ++ ++ /* ODT configuration is done for single bank CS[0] only */ ++ /* Config DDR2 On Die Termination (ODT) registers */ ++ ldr r6, =DDR2_ODT_CTRL_LOW_CS0_DV ++ MV_REG_WRITE_ASM (r6, r5, DDR2_SDRAM_ODT_CTRL_LOW_REG) ++ ++ ldr r6, =DDR2_ODT_CTRL_HIGH_CS0_DV ++ MV_REG_WRITE_ASM (r6, r5, DDR2_SDRAM_ODT_CTRL_HIGH_REG) ++ ++ ldr r6, =DDR2_DUNIT_ODT_CTRL_CS0_DV ++ MV_REG_WRITE_ASM (r6, r5, DDR2_DUNIT_ODT_CONTROL_REG) ++ ++ ++ /* we will check what device we are running and perform ++ Initialization according to device value */ ++ ++_extModeODTEnd: ++ ++ /* Implement Guideline (GL# MEM-2) P_CAL Automatic Calibration */ ++ /* Does Not Work for Address/Control and Data Pads. */ ++ /* Relevant for: 88F5181-A1/B0 and 88F5281-A0 */ ++ ++ /* Read device ID */ ++ MV_CTRL_MODEL_GET_ASM(r6, r5); ++ /* Read device revision */ ++ MV_CTRL_REV_GET_ASM(r8, r5); ++ ++ /* Continue if OrionN */ ++ ldr r5, =MV_5180_DEV_ID ++ cmp r6, r5 ++ bne 1f ++ b glMem2End ++1: ++ ++ /* Continue if Orion1 and device revision B1 */ ++ ldr r5, =MV_5181_DEV_ID ++ cmp r6, r5 ++ bne 1f ++ ++ cmp r8, #MV_5181_B1_REV ++ bge glMem2End ++ b glMem2Start ++1: ++ ++ /* Orion NAS */ ++ ldr r5, =MV_5182_DEV_ID ++ cmp r6, r5 ++ beq glMem2Start ++ ++ /* Orion Shark */ ++ ldr r5, =MV_8660_DEV_ID ++ cmp r6, r5 ++ beq glMem2Start ++ ++ b glMem2End ++ ++glMem2Start: ++ ++ /* DDR SDRAM Address/Control Pads Calibration */ ++ MV_REG_READ_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) ++ ++ /* Set Bit [31] to make the register writable */ ++ orr r8, r6, #SDRAM_WR_EN ++ ++ MV_REG_WRITE_ASM (r8, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) ++ ++ bic r6, r6, #SDRAM_WR_EN /* Make register read-only */ ++ bic r6, r6, #SDRAM_TUNE_EN /* Disable auto calibration */ ++ bic r6, r6, #SDRAM_DRVN_MASK /* Clear r5[5:0] */ ++ bic r6, r6, #SDRAM_DRVP_MASK /* Clear r5[11:6] */ ++ ++ /* Get the final N locked value of driving strength [22:17] */ ++ mov r5, r6 ++ mov r5, r5, LSL #9 ++ mov r5, r5, LSR #26 /* r5[5:0] = r6[22:17] */ ++ orr r5, r5, r5, LSL #6 /* r5[11:6] = r5[5:0] */ ++ ++ /* Write to both bits [5:0] and bits [11:6] */ ++ orr r6, r6, r5 ++ ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) ++ ++ ++ /* DDR SDRAM Data Pads Calibration */ ++ MV_REG_READ_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG) ++ ++ /* Set Bit [31] to make the register writable */ ++ orr r8, r6, #SDRAM_WR_EN ++ ++ MV_REG_WRITE_ASM (r8, r5, SDRAM_DATA_PADS_CAL_REG) ++ ++ bic r6, r6, #SDRAM_WR_EN /* Make register read-only */ ++ bic r6, r6, #SDRAM_TUNE_EN /* Disable auto calibration */ ++ bic r6, r6, #SDRAM_DRVN_MASK /* Clear r5[5:0] */ ++ bic r6, r6, #SDRAM_DRVP_MASK /* Clear r5[11:6] */ ++ ++ /* Get the final N locked value of driving strength [22:17] */ ++ mov r5, r6 ++ mov r5, r5, LSL #9 ++ mov r5, r5, LSR #26 ++ orr r5, r5, r5, LSL #6 /* r5[5:0] = r6[22:17] */ ++ ++ /* Write to both bits [5:0] and bits [11:6] */ ++ orr r6, r6, r5 ++ ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG) ++ ++glMem2End: ++ /* Implement Guideline (GL# MEM-3) Drive Strength Value */ ++ /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */ ++ ++ /* Get SDRAM Config value */ ++ MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG) ++ ++ /* Get DIMM type */ ++ tst r8, #SDRAM_DTYPE_DDR2 ++ beq ddr1StrengthVal ++ ++ddr2StrengthVal: ++ ldr r4, =DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV ++ ldr r8, =DDR2_DATA_PAD_STRENGTH_TYPICAL_DV ++ b setDrvStrength ++ddr1StrengthVal: ++ ldr r4, =DDR1_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV ++ ldr r8, =DDR1_DATA_PAD_STRENGTH_TYPICAL_DV ++ ++setDrvStrength: ++ /* DDR SDRAM Address/Control Pads Calibration */ ++ MV_REG_READ_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) ++ ++ orr r6, r6, #SDRAM_WR_EN /* Make register writeable */ ++ ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) ++ HTOLL(r6,r5) ++ ++ bic r6, r6, #SDRAM_WR_EN /* Make register read-only */ ++ bic r6, r6, #SDRAM_PRE_DRIVER_STRENGTH_MASK ++ orr r6, r4, r6 /* Set default value for DDR */ ++ ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) ++ ++ ++ /* DDR SDRAM Data Pads Calibration */ ++ MV_REG_READ_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG) ++ ++ orr r6, r6, #SDRAM_WR_EN /* Make register writeable */ ++ ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG) ++ HTOLL(r6,r5) ++ ++ bic r6, r6, #SDRAM_WR_EN /* Make register read-only */ ++ bic r6, r6, #SDRAM_PRE_DRIVER_STRENGTH_MASK ++ orr r6, r8, r6 /* Set default value for DDR */ ++ ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG) ++ ++ ++ /* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */ ++ /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */ ++ /* Get the "sample on reset" register for the DDR frequancy */ ++ ++#if defined(MV_RUN_FROM_FLASH) ++ /* Calc the absolute address of the _cpuARMDDRCLK[] in the boot flash */ ++ ldr r7, = _cpuARMDDRCLK ++ ldr r4, =_start ++ ldr r4, [r4] ++ sub r7, r7, r4 ++ ldr r4, = Lrom_start_of_data ++ ldr r4, [r4] ++ add r7, r4, r7 ++#else ++ /* Calc the absolute address of the _cpuARMDDRCLK[] in the boot flash */ ++ ldr r7, = _cpuARMDDRCLK ++ ldr r4, =_start ++ sub r7, r7, r4 ++ add r7, r7, #CFG_MONITOR_BASE ++#endif ++ /* Get the "sample on reset" register for the DDR frequancy */ ++ MV_REG_READ_ASM (r4, r5, MPP_SAMPLE_AT_RESET) ++ ldr r5, =MSAR_ARMDDRCLCK_MASK ++ and r5, r4, r5 ++#if 0 /* YOTAM TO BE FIX */ ++ mov r5, r5, LSR #MSAR_ARMDDRCLCK_OFFS ++#endif ++ ++ /* Read device ID */ ++ MV_CTRL_MODEL_GET_ASM(r6, r8); ++ ++ /* Continue if TC90 */ ++ ldr r8, =MV_1281_DEV_ID ++ cmp r6, r6 ++ beq armClkMsb ++ ++ /* Continue if Orion2 */ ++ ldr r8, =MV_5281_DEV_ID ++ cmp r6, r8 ++#if 0 /* YOTAM TO BE FIX */ ++ bne 1f ++#endif ++ ++armClkMsb: ++#if 0 /* YOTAM TO BE FIX */ ++ tst r4, #MSAR_ARMDDRCLCK_H_MASK ++ beq 1f ++ orr r5, r5, #BIT4 ++1: ++ ldr r4, =MV_CPU_ARM_CLK_ELM_SIZE ++ mul r5, r4, r5 ++ add r7, r7, r5 ++ add r7, r7, #MV_CPU_ARM_CLK_DDR_OFF ++ ldr r5, [r7] ++#endif ++ ++ /* Get SDRAM Config value */ ++ MV_REG_READ_ASM (r8, r4, SDRAM_CONFIG_REG) ++ ++ /* Get DIMM type */ ++ tst r8, #SDRAM_DTYPE_DDR2 ++ beq ddr1FtdllVal ++ ++ddr2FtdllVal: ++ ldr r4, =FTDLL_DDR2_250MHZ ++ ldr r7, =_250MHz ++ cmp r5, r7 ++ beq setFtdllReg ++ ldr r4, =FTDLL_DDR2_200MHZ ++ ldr r7, =_200MHz ++ cmp r5, r7 ++ beq setFtdllReg ++ ldr r4, =FTDLL_DDR2_166MHZ ++ ldr r7, =_166MHz ++ cmp r5, r7 ++ beq setFtdllReg ++ ldr r4, =FTDLL_DDR2_133MHZ ++ b setFtdllReg ++ ++ddr1FtdllVal: ++ ldr r4, =FTDLL_DDR1_200MHZ ++ ldr r7, =_200MHz ++ cmp r5, r7 ++ beq setFtdllReg ++ ldr r4, =FTDLL_DDR1_166MHZ ++ ldr r7, =_166MHz ++ cmp r5, r7 ++ beq setFtdllReg ++ ldr r4, =FTDLL_DDR1_133MHZ ++ ldr r7, =_133MHz ++ cmp r5, r7 ++ beq setFtdllReg ++ ldr r4, =0 ++ ++setFtdllReg: ++ ++#if !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L) ++ MV_REG_READ_ASM (r8, r5, SDRAM_FTDLL_CONFIG_REG) ++ orr r8, r8, r4 ++ MV_REG_WRITE_ASM (r8, r5, SDRAM_FTDLL_CONFIG_REG) ++ bic r8, r8, #1 ++ MV_REG_WRITE_ASM (r8, r5, SDRAM_FTDLL_CONFIG_REG) ++#endif /* !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L)*/ ++ ++ ++setTimingReg: ++ /* Set default Timing parameters */ ++ MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG) ++ tst r8, #SDRAM_DTYPE_DDR2 ++ bne ddr2TimeParam ++ ++ddr1TimeParam: ++ ldr r6, =DDR1_TIMING_LOW_DV ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_LOW_REG) ++ ldr r6, =DDR1_TIMING_HIGH_DV ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_HIGH_REG) ++ b timeParamDone ++ ++ddr2TimeParam: ++ ldr r6, =DDR2_TIMING_LOW_DV ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_LOW_REG) ++ ldr r6, =DDR2_TIMING_HIGH_DV ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_HIGH_REG) ++ ++timeParamDone: ++ /* Open CS[0] window to requested size and enable it. Disable other */ ++ /* windows */ ++ ldr r6, =SCBAR_BASE_MASK ++ sub r3, r3, #1 ++ and r3, r3, r6 ++ orr r3, r3, #1 /* Enable bank */ ++ MV_REG_WRITE_ASM (r3, r5, SDRAM_SIZE_REG(0)) ++ ldr r6, =0 ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(1)) ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(2)) ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(3)) ++ ++exit_ddrAutoConfig: ++ mov PC, r11 /* r11 is saved link register */ ++ ++ ++/***************************************************************************************/ ++/* r4 holds I2C EEPROM address ++ * r7 holds I2C EEPROM offset parameter for i2cRead and its --> returned value ++ * r8 holds SDRAM various configuration registers value. ++ * r13 holds Link register ++ */ ++/**************************/ ++_getDensity: ++ mov r13, LR /* Save link register */ ++ ++ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ ++ mov r7, #NUM_OF_ROWS_OFFSET /* offset 3 */ ++ bl _i2cRead ++ mov r8, r7 /* r8 save number of rows */ ++ ++ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ ++ mov r7, #NUM_OF_COLS_OFFSET /* offset 4 */ ++ bl _i2cRead ++ add r8, r8, r7 /* r8 = number of rows + number of col */ ++ ++ mov r7, #0x1 ++ mov r8, r7, LSL r8 /* r8 = (1 << r8) */ ++ ++ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ ++ mov r7, #SDRAM_WIDTH_OFFSET /* offset 13 */ ++ bl _i2cRead ++ mul r8, r7, r8 ++ ++ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ ++ mov r7, #NUM_OF_BANKS_OFFSET /* offset 17 */ ++ bl _i2cRead ++ mul r7, r8, r7 ++ ++ mov PC, r13 ++ ++/**************************/ ++_get_width: ++ mov r13, LR /* Save link register */ ++ ++ /* Get SDRAM width (SPD offset 13) */ ++ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ ++ mov r7, #SDRAM_WIDTH_OFFSET ++ bl _i2cRead /* result in r7 */ ++ ++ mov PC, r13 ++ ++/**************************/ ++_get_CAL: ++ mov r13, LR /* Save link register */ ++ ++ /* Set maximum CL supported by DIMM */ ++ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ ++ mov r7, #SUPPORTED_CL_OFFSET /* offset 18 */ ++ bl _i2cRead ++ ++ mov PC, r13 ++ ++/**************************/ ++/* R8 - sdram configuration register. ++ * Return value in flag if no-registered then Z-flag is set ++ */ ++_is_Registered: ++ mov r13, LR /* Save link register */ ++ ++ /* Get registered/non registered info from DIMM */ ++ tst r8, #SDRAM_DTYPE_DDR2 ++ bne regDdr2 ++ ++regDdr1: ++ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ ++ mov r7, #SDRAM_MODULES_ATTR_OFFSET ++ bl _i2cRead /* result in r7 */ ++ tst r7, #0x2 ++ b exit ++regDdr2: ++ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ ++ mov r7, #DIMM_TYPE_INFO_OFFSET ++ bl _i2cRead /* result in r7 */ ++ tst r7, #0x11 /* DIMM type = regular RDIMM (0x01) */ ++ /* or Mini-RDIMM (0x10) */ ++exit: ++ mov PC, r13 ++ ++ ++#endif +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.S linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.S +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.S 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.S 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,668 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++/******************************************************************************* ++* mvDramIfBasicAsm.s ++* ++* DESCRIPTION: ++* Memory full detection and best timing configuration is done in ++* C code. C runtime environment requires a stack. This module API ++* initialize DRAM interface chip select 0 for basic functionality for ++* the use of stack. ++* The module API assumes DRAM information is stored in I2C EEPROM reside ++* in a given I2C address MV_BOARD_DIMM0_I2C_ADDR. The I2C EEPROM ++* internal data structure is assumed to be orgenzied in common DRAM ++* vendor SPD structure. ++* NOTE: DFCDL values are assumed to be already initialized prior to ++* this module API activity. ++* ++* ++* DEPENDENCIES: ++* None. ++* ++*******************************************************************************/ ++ ++/* includes */ ++#define MV_ASMLANGUAGE ++#include "mvOsAsm.h" ++#include "mvSysHwConfig.h" ++#include "mvDramIfRegs.h" ++#include "mvDramIfConfig.h" ++#include "mvCpuIfRegs.h" ++#include "pex/mvPexRegs.h" ++#include "pci/mvPciRegs.h" ++#include "mvCtrlEnvSpec.h" ++#include "mvCtrlEnvAsm.h" ++#include "cpu/mvCpuArm.h" ++#include "mvCommon.h" ++ ++/* defines */ ++ ++/* locals */ ++.data ++.globl _mvDramIfConfig ++ ++.text ++ ++/******************************************************************************* ++* _mvDramIfConfig - Basic DRAM interface initialization. ++* ++* DESCRIPTION: ++* The function will initialize the following DRAM parameters using the ++* values prepared by mvDramIfDetect routine. Values are located ++* in predefined registers. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++ ++_mvDramIfConfig: ++ ++ /* Save register on stack */ ++ cmp sp, #0 ++ beq no_stack_s ++save_on_stack: ++ stmdb sp!, {r1, r2, r3, r4, r7, r11} ++no_stack_s: ++ ++ /* 1) Write to SDRAM coniguration register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG1) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_CONFIG_REG) ++ str r4, [r1] ++ ++ /* 2) Write Dunit control low register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG3) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_DUNIT_CTRL_REG) ++ str r4, [r1] ++ ++ /* 3) Write SDRAM address control register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG4) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_ADDR_CTRL_REG) ++ str r4, [r1] ++ ++ /* 4) Write SDRAM bank 0 size register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG0) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_SIZE_REG(0)) ++ str r4, [r1] ++ ++ /* 5) Write SDRAM open pages control register */ ++ ldr r1, =(INTER_REGS_BASE + SDRAM_OPEN_PAGE_CTRL_REG) ++ ldr r4, =SDRAM_OPEN_PAGES_CTRL_REG_DV ++ str r4, [r1] ++ ++ /* 6) Write SDRAM timing Low register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG5) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_LOW_REG) ++ str r4, [r1] ++ ++ /* 7) Write SDRAM timing High register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG6) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_HIGH_REG) ++ str r4, [r1] ++ ++ /* 8) Write SDRAM mode register */ ++ /* The CPU must not attempt to change the SDRAM Mode register setting */ ++ /* prior to DRAM controller completion of the DRAM initialization */ ++ /* sequence. To guarantee this restriction, it is recommended that */ ++ /* the CPU sets the SDRAM Operation register to NOP command, performs */ ++ /* read polling until the register is back in Normal operation value, */ ++ /* and then sets SDRAM Mode register to it’s new value. */ ++ ++ /* 8.1 write 'nop' to SDRAM operation */ ++ mov r4, #0x5 /* 'NOP' command */ ++ MV_REG_WRITE_ASM(r4, r1, SDRAM_OPERATION_REG) ++ ++ /* 8.2 poll SDRAM operation. Make sure its back to normal operation */ ++_sdramOpPoll1: ++ ldr r4, [r1] ++ cmp r4, #0 /* '0' = Normal SDRAM Mode */ ++ bne _sdramOpPoll1 ++ ++ /* 8.3 Now its safe to write new value to SDRAM Mode register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG2) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_MODE_REG) ++ str r4, [r1] ++ ++ /* 8.4 Make the Dunit write the DRAM its new mode */ ++ mov r4, #0x3 /* Mode Register Set command */ ++ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) ++ ++ /* 8.5 poll SDRAM operation. Make sure its back to normal operation */ ++_sdramOpPoll2: ++ ldr r4, [r1] ++ cmp r4, #0 /* '0' = Normal SDRAM Mode */ ++ bne _sdramOpPoll2 ++ ++#ifndef DB_FPGA ++ /* Config DDR2 registers (Extended mode, ODTs and pad calibration) */ ++ MV_REG_READ_ASM (r4, r1, SDRAM_CONFIG_REG) ++ tst r4, #SDRAM_DTYPE_DDR2 ++ beq _extModeODTEnd ++#endif /* DB_FPGA */ ++ ++ /* 9) Write SDRAM Extended mode register This operation should be */ ++ /* done for each memory bank */ ++ /* write 'nop' to SDRAM operation */ ++ mov r4, #0x5 /* 'NOP' command */ ++ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) ++ ++ /* poll SDRAM operation. Make sure its back to normal operation */ ++_sdramOpPoll3: ++ ldr r4, [r1] ++ cmp r4, #0 /* '0' = Normal SDRAM Mode */ ++ bne _sdramOpPoll3 ++ ++ /* Now its safe to write new value to SDRAM Extended Mode register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG10) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_EXTENDED_MODE_REG) ++ str r4, [r1] ++ ++ /* Go over each of the Banks */ ++ ldr r3, =0 /* r3 = DRAM bank Num */ ++ ++extModeLoop: ++ /* Set the SDRAM Operation Control to each of the DRAM banks */ ++ mov r2, r3 /* Do not swap the bank counter value */ ++ MV_REG_WRITE_ASM (r2, r1, SDRAM_OPERATION_CTRL_REG) ++ ++ /* Make the Dunit write the DRAM its new mode */ ++ mov r4, #0x4 /* Extended Mode Register Set command */ ++ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) ++ ++ /* poll SDRAM operation. Make sure its back to normal operation */ ++_sdramOpPoll4: ++ ldr r4, [r1] ++ cmp r4, #0 /* '0' = Normal SDRAM Mode */ ++ bne _sdramOpPoll4 ++#ifndef DB_FPGA ++ add r3, r3, #1 ++ cmp r3, #4 /* 4 = Number of banks */ ++ bne extModeLoop ++ ++extModeEnd: ++ /* Config DDR2 On Die Termination (ODT) registers */ ++ /* Write SDRAM DDR2 ODT control low register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG7) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_LOW_REG) ++ str r4, [r1] ++ ++ /* Write SDRAM DDR2 ODT control high register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG8) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_HIGH_REG) ++ str r4, [r1] ++ ++ /* Write SDRAM DDR2 Dunit ODT control register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG9) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + DDR2_DUNIT_ODT_CONTROL_REG) ++ str r4, [r1] ++ ++#endif /* DB_FPGA */ ++_extModeODTEnd: ++#ifndef DB_FPGA ++ /* Implement Guideline (GL# MEM-2) P_CAL Automatic Calibration */ ++ /* Does Not Work for Address/Control and Data Pads. */ ++ /* Relevant for: 88F5181-A1/B0 and 88F5281-A0 */ ++ ++ /* Read device ID */ ++ MV_CTRL_MODEL_GET_ASM(r3, r1); ++ /* Read device revision */ ++ MV_CTRL_REV_GET_ASM(r2, r1); ++ ++ /* Continue if OrionN */ ++ ldr r1, =MV_5180_DEV_ID ++ cmp r3, r1 ++ bne 1f ++ b glMem2End ++1: ++ /* Continue if Orion1 and device revision B1 */ ++ ldr r1, =MV_5181_DEV_ID ++ cmp r3, r1 ++ bne 1f ++ ++ cmp r2, #MV_5181_B1_REV ++ bge glMem2End ++ b glMem2Start ++1: ++ ++ /* Orion NAS */ ++ ldr r1, =MV_5182_DEV_ID ++ cmp r3, r1 ++ beq glMem2Start ++ ++ /* Orion NAS */ ++ ldr r1, =MV_5082_DEV_ID ++ cmp r3, r1 ++ beq glMem2Start ++ ++ /* Orion Shark */ ++ ldr r1, =MV_8660_DEV_ID ++ cmp r3, r1 ++ beq glMem2Start ++ ++ b glMem2End ++ ++glMem2Start: ++ ++ /* DDR SDRAM Address/Control Pads Calibration */ ++ MV_REG_READ_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) ++ ++ /* Set Bit [31] to make the register writable */ ++ orr r2, r3, #SDRAM_WR_EN ++ ++ MV_REG_WRITE_ASM (r2, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) ++ ++ bic r3, r3, #SDRAM_WR_EN /* Make register read-only */ ++ bic r3, r3, #SDRAM_TUNE_EN /* Disable auto calibration */ ++ bic r3, r3, #SDRAM_DRVN_MASK /* Clear r1[5:0] */ ++ bic r3, r3, #SDRAM_DRVP_MASK /* Clear r1[11:6] */ ++ ++ /* Get the final N locked value of driving strength [22:17] */ ++ mov r1, r3 ++ mov r1, r1, LSL #9 ++ mov r1, r1, LSR #26 /* r1[5:0] = r3[22:17] */ ++ orr r1, r1, r1, LSL #6 /* r1[11:6] = r1[5:0] */ ++ ++ /* Write to both bits [5:0] and bits [11:6] */ ++ orr r3, r3, r1 ++ ++ MV_REG_WRITE_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) ++ ++ ++ /* DDR SDRAM Data Pads Calibration */ ++ MV_REG_READ_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG) ++ ++ /* Set Bit [31] to make the register writable */ ++ orr r2, r3, #SDRAM_WR_EN ++ ++ MV_REG_WRITE_ASM (r2, r1, SDRAM_DATA_PADS_CAL_REG) ++ ++ bic r3, r3, #SDRAM_WR_EN /* Make register read-only */ ++ bic r3, r3, #SDRAM_TUNE_EN /* Disable auto calibration */ ++ bic r3, r3, #SDRAM_DRVN_MASK /* Clear r1[5:0] */ ++ bic r3, r3, #SDRAM_DRVP_MASK /* Clear r1[11:6] */ ++ ++ /* Get the final N locked value of driving strength [22:17] */ ++ mov r1, r3 ++ mov r1, r1, LSL #9 ++ mov r1, r1, LSR #26 ++ orr r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17] */ ++ ++ /* Write to both bits [5:0] and bits [11:6] */ ++ orr r3, r3, r1 ++ ++ MV_REG_WRITE_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG) ++ ++glMem2End: ++ ++ ++ /* Implement Guideline (GL# MEM-3) Drive Strength Value */ ++ /* Relevant for: 88F5181-A1/B0/B1, 88F5281-A0/B0/C/D, 88F5182, */ ++ /* 88F5082, 88F5181L, 88F6082/L, 88F6183, 88F6183L */ ++ ++ /* Get SDRAM Config value */ ++ MV_REG_READ_ASM (r2, r1, SDRAM_CONFIG_REG) ++ ++ /* Get DIMM type */ ++ tst r2, #SDRAM_DTYPE_DDR2 ++ beq ddr1StrengthVal ++ ++ddr2StrengthVal: ++ ldr r4, =DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV ++ ldr r2, =DDR2_DATA_PAD_STRENGTH_TYPICAL_DV ++ b setDrvStrength ++ddr1StrengthVal: ++ ldr r4, =DDR1_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV ++ ldr r2, =DDR1_DATA_PAD_STRENGTH_TYPICAL_DV ++ ++setDrvStrength: ++ /* DDR SDRAM Address/Control Pads Calibration */ ++ MV_REG_READ_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) ++ ++ orr r3, r3, #SDRAM_WR_EN /* Make register writeable */ ++ ++ MV_REG_WRITE_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) ++ HTOLL(r3,r1) ++ ++ bic r3, r3, #SDRAM_WR_EN /* Make register read-only */ ++ bic r3, r3, #SDRAM_PRE_DRIVER_STRENGTH_MASK ++ orr r3, r4, r3 /* Set default value for DDR */ ++ ++ MV_REG_WRITE_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) ++ ++ ++ /* DDR SDRAM Data Pads Calibration */ ++ MV_REG_READ_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG) ++ ++ orr r3, r3, #SDRAM_WR_EN /* Make register writeable */ ++ ++ MV_REG_WRITE_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG) ++ HTOLL(r3,r1) ++ ++ bic r3, r3, #SDRAM_WR_EN /* Make register read-only */ ++ bic r3, r3, #SDRAM_PRE_DRIVER_STRENGTH_MASK ++ orr r3, r2, r3 /* Set default value for DDR */ ++ ++ MV_REG_WRITE_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG) ++ ++#if !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L) ++ /* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */ ++ /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0/C/D, 88F5182 */ ++ /* 88F5082, 88F5181L, 88F6082/L */ ++ ++ /* Calc the absolute address of the _cpuARMDDRCLK[] in the boot flash */ ++ ldr r7, = _cpuARMDDRCLK ++ ldr r4, =_start ++ sub r7, r7, r4 ++ add r7, r7, #CFG_MONITOR_BASE ++ ++ /* Get the "sample on reset" register for the DDR frequancy */ ++ MV_REG_READ_ASM (r4, r1, MPP_SAMPLE_AT_RESET) ++ ldr r1, =MSAR_ARMDDRCLCK_MASK ++ and r1, r4, r1 ++#if 0 /* YOTAM TO BE FIX */ ++ mov r1, r1, LSR #MSAR_ARMDDRCLCK_OFFS ++#endif ++ ++ /* Read device ID */ ++ MV_CTRL_MODEL_GET_ASM(r3, r2); ++ ++ /* Continue if TC90 */ ++ ldr r2, =MV_1281_DEV_ID ++ cmp r3, r2 ++ beq armClkMsb ++ ++ /* Continue if Orion2 */ ++ ldr r2, =MV_5281_DEV_ID ++ cmp r3, r2 ++#if 0 /* YOTAM TO BE FIX */ ++ bne 1f ++#endif ++ ++armClkMsb: ++#if 0 /* YOTAM TO BE FIX */ ++ tst r4, #MSAR_ARMDDRCLCK_H_MASK ++ beq 1f ++ orr r1, r1, #BIT4 ++1: ++ ldr r4, =MV_CPU_ARM_CLK_ELM_SIZE ++ mul r1, r4, r1 ++ add r7, r7, r1 ++ add r7, r7, #MV_CPU_ARM_CLK_DDR_OFF ++ ldr r1, [r7] ++#endif ++ ++ /* Get SDRAM Config value */ ++ MV_REG_READ_ASM (r2, r4, SDRAM_CONFIG_REG) ++ ++ /* Get DIMM type */ ++ tst r2, #SDRAM_DTYPE_DDR2 ++ beq ddr1FtdllVal ++ ++ddr2FtdllVal: ++ ldr r2, =MV_5281_DEV_ID ++ cmp r3, r2 ++ bne 2f ++ MV_CTRL_REV_GET_ASM(r3, r2) ++ cmp r3, #MV_5281_D0_REV ++ beq orin2_d0_ddr2_ftdll_val ++ cmp r3, #MV_5281_D1_REV ++ beq orin2_d1_ddr2_ftdll_val ++ cmp r3, #MV_5281_D2_REV ++ beq orin2_d1_ddr2_ftdll_val ++ b ddr2_default_val ++ ++/* Set Orion 2 D1 ftdll values for DDR2 */ ++orin2_d1_ddr2_ftdll_val: ++ ldr r4, =FTDLL_DDR2_250MHZ_5281_D1 ++ ldr r7, =_250MHz ++ cmp r1, r7 ++ beq setFtdllReg ++ ldr r4, =FTDLL_DDR2_200MHZ_5281_D1 ++ ldr r7, =_200MHz ++ cmp r1, r7 ++ beq setFtdllReg ++ ldr r4, =FTDLL_DDR2_166MHZ_5281_D0 ++ ldr r7, =_166MHz ++ cmp r1, r7 ++ beq setFtdllReg ++ b ddr2_default_val ++ ++/* Set Orion 2 D0 ftdll values for DDR2 */ ++orin2_d0_ddr2_ftdll_val: ++ ldr r4, =FTDLL_DDR2_250MHZ_5281_D0 ++ ldr r7, =_250MHz ++ cmp r1, r7 ++ beq setFtdllReg ++ ldr r4, =FTDLL_DDR2_200MHZ_5281_D0 ++ ldr r7, =_200MHz ++ cmp r1, r7 ++ beq setFtdllReg ++ ldr r4, =FTDLL_DDR2_166MHZ_5281_D0 ++ ldr r7, =_166MHz ++ cmp r1, r7 ++ beq setFtdllReg ++ b ddr2_default_val ++2: ++ ldr r2, =MV_5182_DEV_ID ++ cmp r3, r2 ++ bne 3f ++ ++/* Set Orion nas ftdll values for DDR2 */ ++orin_nas_ftdll_val: ++ ldr r4, =FTDLL_DDR2_166MHZ_5182 ++ ldr r7, =_166MHz ++ cmp r1, r7 ++ beq setFtdllReg ++ ++/* default values for all other devices */ ++3: ++ddr2_default_val: ++ ldr r4, =FTDLL_DDR2_250MHZ ++ ldr r7, =_250MHz ++ cmp r1, r7 ++ beq setFtdllReg ++ ldr r4, =FTDLL_DDR2_200MHZ ++ ldr r7, =_200MHz ++ cmp r1, r7 ++ beq setFtdllReg ++ ldr r4, =FTDLL_DDR2_166MHZ ++ ldr r7, =_166MHz ++ cmp r1, r7 ++ beq setFtdllReg ++ ldr r4, =FTDLL_DDR2_133MHZ ++ ldr r7, =_133MHz ++ cmp r1, r7 ++ beq setFtdllReg ++ ldr r4, =0 ++ b setFtdllReg ++ ++ddr1FtdllVal: ++ ldr r2, =MV_5281_DEV_ID ++ cmp r3, r2 ++ bne 2f ++ MV_CTRL_REV_GET_ASM(r3, r2) ++ cmp r3, #MV_5281_D0_REV ++ bge orin2_ddr1_ftdll_val ++ b ddr1_default_val ++ ++/* Set Orion 2 D0 and above ftdll values for DDR1 */ ++orin2_ddr1_ftdll_val: ++ ldr r4, =FTDLL_DDR1_200MHZ_5281_D0 ++ ldr r7, =_200MHz ++ cmp r1, r7 ++ beq setFtdllReg ++ ldr r4, =FTDLL_DDR1_166MHZ_5281_D0 ++ ldr r7, =_166MHz ++ cmp r1, r7 ++ beq setFtdllReg ++ b ddr1_default_val ++2: ++ ldr r2, =MV_5181_DEV_ID ++ cmp r3, r2 ++ bne 3f ++ MV_CTRL_REV_GET_ASM(r3, r2) ++ cmp r3, #MV_5181_B1_REV ++ bge orin1_ddr1_ftdll_val ++ b ddr1_default_val ++ ++/* Set Orion 1 ftdll values for DDR1 */ ++orin1_ddr1_ftdll_val: ++ ldr r4, =FTDLL_DDR1_166MHZ_5181_B1 ++ ldr r7, =_166MHz ++ cmp r1, r7 ++ beq setFtdllReg ++3: ++ddr1_default_val: ++ ldr r4, =FTDLL_DDR1_133MHZ ++ ldr r7, =_133MHz ++ cmp r1, r7 ++ beq setFtdllReg ++ ++ ldr r4, =FTDLL_DDR1_166MHZ ++ ldr r7, =_166MHz ++ cmp r1, r7 ++ beq setFtdllReg ++ ++ ldr r4, =FTDLL_DDR1_200MHZ ++ ldr r7, =_200MHz ++ cmp r1, r7 ++ beq setFtdllReg ++ ++ ldr r4, =0 ++ ++setFtdllReg: ++ ++ MV_REG_WRITE_ASM (r4, r1, SDRAM_FTDLL_CONFIG_REG) ++ HTOLL(r4,r1) ++ bic r4, r4, #1 ++ MV_REG_WRITE_ASM (r4, r1, SDRAM_FTDLL_CONFIG_REG) ++ ++#endif /* !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L) */ ++#endif /* DB_FPGA */ ++ ++restoreTmpRegs: ++ /* Restore the registers we used to save the DDR detect values */ ++ ++ ldr r4, =DRAM_BUF_REG0_DV ++ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG0) ++ ++ ldr r4, =DRAM_BUF_REG1_DV ++ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG1) ++ ++ ldr r4, =DRAM_BUF_REG2_DV ++ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG2) ++ ++ ldr r4, =DRAM_BUF_REG3_DV ++ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG3) ++ ++ ldr r4, =DRAM_BUF_REG4_DV ++ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG4) ++ ++ ldr r4, =DRAM_BUF_REG5_DV ++ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG5) ++ ++ ldr r4, =DRAM_BUF_REG6_DV ++ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG6) ++ ++ ldr r4, =DRAM_BUF_REG7_DV ++ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG7) ++ ++ ldr r4, =DRAM_BUF_REG8_DV ++ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG8) ++ ++ ldr r4, =DRAM_BUF_REG9_DV ++ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG9) ++ ++ ldr r4, =DRAM_BUF_REG10_DV ++ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG10) ++ ++ ++ /* Restore registers */ ++ /* Save register on stack */ ++ cmp sp, #0 ++ beq no_stack_l ++load_from_stack: ++ ldmia sp!, {r1, r2, r3, r4, r7, r11} ++no_stack_l: ++ ++ mov pc, lr ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,192 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvDramIfConfigh ++#define __INCmvDramIfConfigh ++ ++/* includes */ ++ ++/* defines */ ++ ++/* registers defaults values */ ++ ++#define SDRAM_CONFIG_DV \ ++ (SDRAM_PERR_WRITE | \ ++ SDRAM_SRMODE | \ ++ SDRAM_SRCLK_GATED) ++ ++#define SDRAM_DUNIT_CTRL_LOW_DV \ ++ (SDRAM_CTRL_POS_RISE | \ ++ SDRAM_CLK1DRV_NORMAL | \ ++ SDRAM_LOCKEN_ENABLE) ++ ++#define SDRAM_ADDR_CTRL_DV 0 ++ ++#define SDRAM_TIMING_CTRL_LOW_REG_DV \ ++ ((0x2 << SDRAM_TRCD_OFFS) | \ ++ (0x2 << SDRAM_TRP_OFFS) | \ ++ (0x1 << SDRAM_TWR_OFFS) | \ ++ (0x0 << SDRAM_TWTR_OFFS) | \ ++ (0x5 << SDRAM_TRAS_OFFS) | \ ++ (0x1 << SDRAM_TRRD_OFFS)) ++/* TRFC 0x27, TW2W 0x1 */ ++#define SDRAM_TIMING_CTRL_HIGH_REG_DV (( 0x7 << SDRAM_TRFC_OFFS ) |\ ++ ( 0x2 << SDRAM_TRFC_EXT_OFFS) |\ ++ ( 0x1 << SDRAM_TW2W_OFFS)) ++ ++#define SDRAM_OPEN_PAGES_CTRL_REG_DV SDRAM_OPEN_PAGE_EN ++ ++/* DDR2 ODT default register values */ ++ ++/* Presence Ctrl Low Ctrl High Dunit Ctrl Ext Mode */ ++/* CS0 0x84210000 0x00000000 0x0000780F 0x00000440 */ ++/* CS0+CS1 0x84210000 0x00000000 0x0000780F 0x00000440 */ ++/* CS0+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ ++/* CS0+CS1+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ ++/* CS0+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ ++/* CS0+CS1+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ ++ ++#define DDR2_ODT_CTRL_LOW_CS0_DV 0x84210000 ++#define DDR2_ODT_CTRL_HIGH_CS0_DV 0x00000000 ++#define DDR2_DUNIT_ODT_CTRL_CS0_DV 0x0000780F ++#define DDR_SDRAM_EXT_MODE_CS0_DV 0x00000440 ++ ++#define DDR2_ODT_CTRL_LOW_CS0_CS2_DV 0x030C030C ++#define DDR2_ODT_CTRL_HIGH_CS0_CS2_DV 0x00000000 ++#define DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV 0x0000740F ++#define DDR_SDRAM_EXT_MODE_CS0_CS2_DV 0x00000404 ++ ++ ++/* DDR SDRAM Adderss/Control and Data Pads Calibration default values */ ++#define DDR1_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \ ++ (1 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) ++#define DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \ ++ (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) ++ ++ ++#define DDR1_DATA_PAD_STRENGTH_TYPICAL_DV \ ++ (1 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) ++#define DDR2_DATA_PAD_STRENGTH_TYPICAL_DV \ ++ (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) ++ ++/* DDR SDRAM Mode Register default value */ ++#define DDR1_MODE_REG_DV 0x00000000 ++#define DDR2_MODE_REG_DV 0x00000400 ++ ++/* DDR SDRAM Timing parameter default values */ ++#define DDR1_TIMING_LOW_DV 0x11602220 ++#define DDR1_TIMING_HIGH_DV 0x0000000d ++ ++#define DDR2_TIMING_LOW_DV 0x11812220 ++#define DDR2_TIMING_HIGH_DV 0x0000030f ++ ++/* For Guideline (GL# MEM-4) DQS Reference Delay Tuning */ ++#define FTDLL_DDR1_166MHZ ((0x1 << 0) | \ ++ (0x7F<< 12) | \ ++ (0x1 << 22)) ++ ++#define FTDLL_DDR1_133MHZ FTDLL_DDR1_166MHZ ++ ++#define FTDLL_DDR1_200MHZ ((0x1 << 0) | \ ++ (0x1 << 12) | \ ++ (0x3 << 14) | \ ++ (0x1 << 18) | \ ++ (0x1 << 22)) ++ ++ ++#define FTDLL_DDR2_166MHZ ((0x1 << 0) | \ ++ (0x1 << 12) | \ ++ (0x1 << 14) | \ ++ (0x1 << 16) | \ ++ (0x1 << 19) | \ ++ (0xF << 20)) ++ ++#define FTDLL_DDR2_133MHZ FTDLL_DDR2_166MHZ ++ ++#define FTDLL_DDR2_200MHZ ((0x1 << 0) | \ ++ (0x1 << 12) | \ ++ (0x1 << 14) | \ ++ (0x1 << 16) | \ ++ (0x1 << 19) | \ ++ (0xF << 20)) ++ ++#define FTDLL_DDR2_250MHZ 0x445001 ++ ++/* Orion 1 B1 and above */ ++#define FTDLL_DDR1_166MHZ_5181_B1 0x45D001 ++ ++/* Orion nas */ ++#define FTDLL_DDR2_166MHZ_5182 0x597001 ++ ++/* Orion 2 D0 and above */ ++#define FTDLL_DDR1_166MHZ_5281_D0 0x8D0001 ++#define FTDLL_DDR1_200MHZ_5281_D0 0x8D0001 ++#define FTDLL_DDR2_166MHZ_5281_D0 0x485001 ++#define FTDLL_DDR2_200MHZ_5281_D0 0x485001 ++#define FTDLL_DDR2_250MHZ_5281_D0 0x445001 ++#define FTDLL_DDR2_200MHZ_5281_D1 0x995001 ++#define FTDLL_DDR2_250MHZ_5281_D1 0x984801 ++ ++#endif /* __INCmvDramIfh */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,306 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvDramIfRegsh ++#define __INCmvDramIfRegsh ++ ++ ++/* DDR SDRAM Controller Address Decode Registers */ ++/* SDRAM CSn Base Address Register (SCBAR) */ ++#define SDRAM_BASE_ADDR_REG(csNum) (0x1500 + (csNum * 8)) ++#define SCBAR_BASE_OFFS 16 ++#define SCBAR_BASE_MASK (0xffff << SCBAR_BASE_OFFS) ++#define SCBAR_BASE_ALIGNMENT 0x10000 ++ ++/* SDRAM CSn Size Register (SCSR) */ ++#define SDRAM_SIZE_REG(csNum) (0x1504 + (csNum * 8)) ++#define SCSR_WIN_EN BIT0 ++#define SCSR_SIZE_OFFS 16 ++#define SCSR_SIZE_MASK (0xffff << SCSR_SIZE_OFFS) ++#define SCSR_SIZE_ALIGNMENT 0x10000 ++ ++/* configuration register */ ++#define SDRAM_CONFIG_REG 0x1400 ++#define SDRAM_REFRESH_OFFS 0 ++#define SDRAM_REFRESH_MAX 0x3000 ++#define SDRAM_REFRESH_MASK (SDRAM_REFRESH_MAX << SDRAM_REFRESH_OFFS) ++#define SDRAM_DWIDTH_OFFS 14 ++#define SDRAM_DWIDTH_MASK (3 << SDRAM_DWIDTH_OFFS) ++#define SDRAM_DWIDTH_16BIT (1 << SDRAM_DWIDTH_OFFS) ++#define SDRAM_DWIDTH_32BIT (2 << SDRAM_DWIDTH_OFFS) ++#define SDRAM_DTYPE_OFFS 16 ++#define SDRAM_DTYPE_MASK (1 << SDRAM_DTYPE_OFFS) ++#define SDRAM_DTYPE_DDR1 (0 << SDRAM_DTYPE_OFFS) ++#define SDRAM_DTYPE_DDR2 (1 << SDRAM_DTYPE_OFFS) ++#define SDRAM_REGISTERED (1 << 17) ++#define SDRAM_PERR_OFFS 18 ++#define SDRAM_PERR_MASK (1 << SDRAM_PERR_OFFS) ++#define SDRAM_PERR_NO_WRITE (0 << SDRAM_PERR_OFFS) ++#define SDRAM_PERR_WRITE (1 << SDRAM_PERR_OFFS) ++#define SDRAM_DCFG_OFFS 20 ++#define SDRAM_DCFG_MASK (0x3 << SDRAM_DCFG_OFFS) ++#define SDRAM_DCFG_X16_DEV (1 << SDRAM_DCFG_OFFS) ++#define SDRAM_DCFG_X8_DEV (2 << SDRAM_DCFG_OFFS) ++#define SDRAM_SRMODE (1 << 24) ++#define SDRAM_SRCLK_OFFS 25 ++#define SDRAM_SRCLK_MASK (1 << SDRAM_SRCLK_OFFS) ++#define SDRAM_SRCLK_KEPT (0 << SDRAM_SRCLK_OFFS) ++#define SDRAM_SRCLK_GATED (1 << SDRAM_SRCLK_OFFS) ++#define SDRAM_CATTH_OFFS 26 ++#define SDRAM_CATTHR_EN (1 << SDRAM_CATTH_OFFS) ++ ++ ++/* dunit control register */ ++#define SDRAM_DUNIT_CTRL_REG 0x1404 ++#define SDRAM_CTRL_POS_OFFS 6 ++#define SDRAM_CTRL_POS_FALL (0 << SDRAM_CTRL_POS_OFFS) ++#define SDRAM_CTRL_POS_RISE (1 << SDRAM_CTRL_POS_OFFS) ++#define SDRAM_CLK1DRV_OFFS 12 ++#define SDRAM_CLK1DRV_MASK (1 << SDRAM_CLK1DRV_OFFS) ++#define SDRAM_CLK1DRV_HIGH_Z (0 << SDRAM_CLK1DRV_OFFS) ++#define SDRAM_CLK1DRV_NORMAL (1 << SDRAM_CLK1DRV_OFFS) ++#define SDRAM_LOCKEN_OFFS 18 ++#define SDRAM_LOCKEN_MASK (1 << SDRAM_LOCKEN_OFFS) ++#define SDRAM_LOCKEN_DISABLE (0 << SDRAM_LOCKEN_OFFS) ++#define SDRAM_LOCKEN_ENABLE (1 << SDRAM_LOCKEN_OFFS) ++#define SDRAM_ST_BURST_DEL_OFFS 24 ++#define SDRAM_ST_BURST_DEL_MAX 0xf ++#define SDRAM_ST_BURST_DEL_MASK (SDRAM_ST_BURST_DEL_MAX< busClkPs) ++ { ++ mvOsOutput("Dram: ERR. Bank %d doesn't support memory clock!!!\n", i); ++ return MV_ERROR; ++ } ++ ++ /* All banks must support registry in order to activate it */ ++ if(bankInfo[i].registeredAddrAndControlInputs != ++ bankInfo[0].registeredAddrAndControlInputs) ++ { ++ mvOsOutput("Dram: ERR. different Registered settings !!!\n"); ++ return MV_ERROR; ++ } ++ ++ /* All banks must support same ECC mode */ ++ if(bankInfo[i].errorCheckType != ++ bankInfo[0].errorCheckType) ++ { ++ mvOsOutput("Dram: ERR. different ECC settings !!!\n"); ++ return MV_ERROR; ++ } ++ ++ } ++ else ++ { ++ if( i == 0 ) /* bank 0 doesn't exist */ ++ { ++ mvOsOutput("Dram: ERR. Fail to detect bank 0 !!!\n"); ++ return MV_ERROR; ++ } ++ else ++ { ++ DB(mvOsPrintf("Dram: Could not find bank %d\n", i)); ++ bankInfo[i].size = 0; /* Mark this bank as non exist */ ++ } ++ } ++ } ++ ++#ifdef MV_INCLUDE_SDRAM_CS2 ++ if (bankInfo[SDRAM_CS0].size < bankInfo[SDRAM_CS2].size) ++ { ++ MV_DRAM_CS_order[0] = SDRAM_CS2; ++ MV_DRAM_CS_order[1] = SDRAM_CS3; ++ MV_DRAM_CS_order[2] = SDRAM_CS0; ++ MV_DRAM_CS_order[3] = SDRAM_CS1; ++ DRAM_CS_Order[0] = SDRAM_CS2; ++ DRAM_CS_Order[1] = SDRAM_CS3; ++ DRAM_CS_Order[2] = SDRAM_CS0; ++ DRAM_CS_Order[3] = SDRAM_CS1; ++ ++ } ++ else ++#endif ++ { ++ MV_DRAM_CS_order[0] = SDRAM_CS0; ++ MV_DRAM_CS_order[1] = SDRAM_CS1; ++ DRAM_CS_Order[0] = SDRAM_CS0; ++ DRAM_CS_Order[1] = SDRAM_CS1; ++#ifdef MV_INCLUDE_SDRAM_CS2 ++ MV_DRAM_CS_order[2] = SDRAM_CS2; ++ MV_DRAM_CS_order[3] = SDRAM_CS3; ++ DRAM_CS_Order[2] = SDRAM_CS2; ++ DRAM_CS_Order[3] = SDRAM_CS3; ++#endif ++ } ++ ++ for(j = 0; j < MV_DRAM_MAX_CS; j++) ++ { ++ i = MV_DRAM_CS_order[j]; ++ ++ if (0 == bankInfo[i].size) ++ continue; ++ ++ /* Init the CPU window decode */ ++ /* Note that the Dimm width might be different then the device DRAM width */ ++#ifdef MV78XX0 ++ temp = MV_REG_READ(SDRAM_CONFIG_REG); ++ deviceW = ((temp & SDRAM_DWIDTH_MASK) == SDRAM_DWIDTH_32BIT )? 32 : 64; ++#else ++ deviceW = 16 /* KW family */; ++#endif ++ dimmW = bankInfo[0].dataWidth - (bankInfo[0].dataWidth % 16); ++ size = ((bankInfo[i].size << 20) / (dimmW/deviceW)); ++ ++ /* We can not change DRAM window settings while excecuting */ ++ /* code from it. That is why we skip the DRAM CS[0], saving */ ++ /* it to the ROM configuration routine */ ++ ++ numOfAllDevices += bankInfo[i].numberOfDevices; ++ if (i == MV_DRAM_CS_order[0]) ++ { ++ MV_U32 sizeToReg; ++ /* Translate the given window size to register format */ ++ sizeToReg = ctrlSizeToReg(size, SCSR_SIZE_ALIGNMENT); ++ /* Size parameter validity check. */ ++ if (-1 == sizeToReg) ++ { ++ mvOsOutput("DRAM: mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n" ++ ,i); ++ return MV_BAD_PARAM; ++ } ++ ++ DB(mvOsPrintf("Dram: Bank 0 Size - %x\n",sizeToReg);) ++ sizeToReg = (sizeToReg << SCSR_SIZE_OFFS); ++ sizeToReg |= SCSR_WIN_EN; ++ MV_REG_WRITE(DRAM_BUF_REG0, sizeToReg); ++ } ++ else ++ { ++ dramDecWin.addrWin.baseLow = base; ++ dramDecWin.addrWin.size = size; ++ dramDecWin.enable = MV_TRUE; ++ DB(mvOsPrintf("Dram: Enable window %d base 0x%x, size=0x%x\n",i, base, size)); ++ ++ /* Check if the DRAM size is more then 3GByte */ ++ if (base < 0xC0000000) ++ { ++ DB(mvOsPrintf("Dram: Enable window %d base 0x%x, size=0x%x\n",i, base, size)); ++ if (MV_OK != mvCpuIfTargetWinSet(i, &dramDecWin)) ++ { ++ mvOsPrintf("Dram: ERR. Fail to set bank %d!!!\n", SDRAM_CS0 + i); ++ return MV_ERROR; ++ } ++ } ++ } ++ ++ base += size; ++ ++ /* update the suportedCasLatencies mask */ ++ bankInfo[0].suportedCasLatencies &= bankInfo[i].suportedCasLatencies; ++ } ++ ++ /* calculate minimum CAS */ ++ minCas = minCasCalc(&bankInfo[0], &bankInfo[2], busClk, forcedCl); ++ if (0 == minCas) ++ { ++ mvOsOutput("Dram: Warn: Could not find CAS compatible to SysClk %dMhz\n", ++ (busClk / 1000000)); ++ ++ minCas = DDR2_CL_4; /* Continue with this CAS */ ++ mvOsOutput("Set default CAS latency 4\n"); ++ } ++ ++ /* calc SDRAM_CONFIG_REG and save it to temp register */ ++ temp = sdramConfigRegCalc(&bankInfo[0],&bankInfo[2], busClk); ++ if(-1 == temp) ++ { ++ mvOsOutput("Dram: ERR. sdramConfigRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ ++ /* check if ECC is enabled by the user */ ++ if(eccDisable) ++ { ++ /* turn off ECC*/ ++ temp &= ~BIT18; ++ } ++ DB(mvOsPrintf("Dram: sdramConfigRegCalc - %x\n",temp);) ++ MV_REG_WRITE(DRAM_BUF_REG1, temp); ++ ++ /* calc SDRAM_MODE_REG and save it to temp register */ ++ temp = sdramModeRegCalc(minCas); ++ if(-1 == temp) ++ { ++ mvOsOutput("Dram: ERR. sdramModeRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Dram: sdramModeRegCalc - %x\n",temp);) ++ MV_REG_WRITE(DRAM_BUF_REG2, temp); ++ ++ /* calc SDRAM_EXTENDED_MODE_REG and save it to temp register */ ++ temp = sdramExtModeRegCalc(&bankInfo[0], busClk); ++ if(-1 == temp) ++ { ++ mvOsOutput("Dram: ERR. sdramExtModeRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Dram: sdramExtModeRegCalc - %x\n",temp);) ++ MV_REG_WRITE(DRAM_BUF_REG10, temp); ++ ++ /* calc D_UNIT_CONTROL_LOW and save it to temp register */ ++ TTMode = MV_FALSE; ++ DB(mvOsPrintf("Dram: numOfAllDevices = %x\n",numOfAllDevices);) ++ if( (numOfAllDevices > 9) && (bankInfo[0].registeredAddrAndControlInputs == MV_FALSE) ) ++ { ++ if ( ( (numOfAllDevices > 9) && (busClk > MV_BOARD_SYSCLK_200MHZ) ) || ++ (numOfAllDevices > 18) ) ++ { ++ mvOsOutput("Enable 2T "); ++ TTMode = MV_TRUE; ++ } ++ } ++ ++ temp = dunitCtrlLowRegCalc(&bankInfo[0], minCas, busClk, TTMode ); ++ if(-1 == temp) ++ { ++ mvOsOutput("Dram: ERR. dunitCtrlLowRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Dram: dunitCtrlLowRegCalc - %x\n",temp);) ++ MV_REG_WRITE(DRAM_BUF_REG3, temp); ++ ++ /* calc D_UNIT_CONTROL_HIGH and save it to temp register */ ++ temp = dunitCtrlHighRegCalc(&bankInfo[0], busClk); ++ if(-1 == temp) ++ { ++ mvOsOutput("Dram: ERR. dunitCtrlHighRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Dram: dunitCtrlHighRegCalc - %x\n",temp);) ++ /* check if ECC is enabled by the user */ ++ if(eccDisable) ++ { ++ /* turn off sample stage if no ecc */ ++ temp &= ~SDRAM__D2P_EN;; ++ } ++ MV_REG_WRITE(DRAM_BUF_REG13, temp); ++ ++ /* calc SDRAM_ADDR_CTRL_REG and save it to temp register */ ++ temp = sdramAddrCtrlRegCalc(&bankInfo[0],&bankInfo[2]); ++ if(-1 == temp) ++ { ++ mvOsOutput("Dram: ERR. sdramAddrCtrlRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Dram: sdramAddrCtrlRegCalc - %x\n",temp);) ++ MV_REG_WRITE(DRAM_BUF_REG4, temp); ++ ++ /* calc SDRAM_TIMING_CTRL_LOW_REG and save it to temp register */ ++ temp = sdramTimeCtrlLowRegCalc(&bankInfo[0], minCas, busClk); ++ if(-1 == temp) ++ { ++ mvOsOutput("Dram: ERR. sdramTimeCtrlLowRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Dram: sdramTimeCtrlLowRegCalc - %x\n",temp);) ++ MV_REG_WRITE(DRAM_BUF_REG5, temp); ++ ++ /* calc SDRAM_TIMING_CTRL_HIGH_REG and save it to temp register */ ++ temp = sdramTimeCtrlHighRegCalc(&bankInfo[0], busClk); ++ if(-1 == temp) ++ { ++ mvOsOutput("Dram: ERR. sdramTimeCtrlHighRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Dram: sdramTimeCtrlHighRegCalc - %x\n",temp);) ++ MV_REG_WRITE(DRAM_BUF_REG6, temp); ++ ++ sdramDDr2OdtConfig(bankInfo); ++ ++ /* calc DDR2_SDRAM_TIMING_LOW_REG and save it to temp register */ ++ temp = sdramDdr2TimeLoRegCalc(minCas); ++ if(-1 == temp) ++ { ++ mvOsOutput("Dram: ERR. sdramDdr2TimeLoRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Dram: sdramDdr2TimeLoRegCalc - %x\n",temp);) ++ MV_REG_WRITE(DRAM_BUF_REG11, temp); ++ ++ /* calc DDR2_SDRAM_TIMING_HIGH_REG and save it to temp register */ ++ temp = sdramDdr2TimeHiRegCalc(minCas); ++ if(-1 == temp) ++ { ++ mvOsOutput("Dram: ERR. sdramDdr2TimeHiRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Dram: sdramDdr2TimeHiRegCalc - %x\n",temp);) ++ MV_REG_WRITE(DRAM_BUF_REG12, temp); ++#endif ++ ++ /* Note that DDR SDRAM Address/Control and Data pad calibration */ ++ /* settings is done in mvSdramIfConfig.s */ ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvDramIfBankBaseGet - Get DRAM interface bank base. ++* ++* DESCRIPTION: ++* This function returns the 32 bit base address of a given DRAM bank. ++* ++* INPUT: ++* bankNum - Bank number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* DRAM bank size. If bank is disabled or paramter is invalid, the ++* function returns -1. ++* ++*******************************************************************************/ ++MV_U32 mvDramIfBankBaseGet(MV_U32 bankNum) ++{ ++ DB(mvOsPrintf("Dram: mvDramIfBankBaseGet Bank %d base addr is %x \n", ++ bankNum, mvCpuIfTargetWinBaseLowGet(SDRAM_CS0 + bankNum))); ++ return mvCpuIfTargetWinBaseLowGet(SDRAM_CS0 + bankNum); ++} ++ ++/******************************************************************************* ++* mvDramIfBankSizeGet - Get DRAM interface bank size. ++* ++* DESCRIPTION: ++* This function returns the size of a given DRAM bank. ++* ++* INPUT: ++* bankNum - Bank number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* DRAM bank size. If bank is disabled the function return '0'. In case ++* or paramter is invalid, the function returns -1. ++* ++*******************************************************************************/ ++MV_U32 mvDramIfBankSizeGet(MV_U32 bankNum) ++{ ++ DB(mvOsPrintf("Dram: mvDramIfBankSizeGet Bank %d size is %x \n", ++ bankNum, mvCpuIfTargetWinSizeGet(SDRAM_CS0 + bankNum))); ++ return mvCpuIfTargetWinSizeGet(SDRAM_CS0 + bankNum); ++} ++ ++ ++/******************************************************************************* ++* mvDramIfSizeGet - Get DRAM interface total size. ++* ++* DESCRIPTION: ++* This function get the DRAM total size. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* DRAM total size. In case or paramter is invalid, the function ++* returns -1. ++* ++*******************************************************************************/ ++MV_U32 mvDramIfSizeGet(MV_VOID) ++{ ++ MV_U32 size = 0, i; ++ ++ for(i = 0; i < MV_DRAM_MAX_CS; i++) ++ size += mvDramIfBankSizeGet(i); ++ ++ DB(mvOsPrintf("Dram: mvDramIfSizeGet size is %x \n",size)); ++ return size; ++} ++ ++/******************************************************************************* ++* mvDramIfSingleBitErrThresholdSet - Set single bit ECC threshold. ++* ++* DESCRIPTION: ++* The ECC single bit error threshold is the number of single bit ++* errors to happen before the Dunit generates an interrupt. ++* This function set single bit ECC threshold. ++* ++* INPUT: ++* threshold - threshold. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM if threshold is to big, MV_OK otherwise. ++* ++*******************************************************************************/ ++MV_STATUS mvDramIfSingleBitErrThresholdSet(MV_U32 threshold) ++{ ++ MV_U32 regVal; ++ ++ if (threshold > SECR_THRECC_MAX) ++ { ++ return MV_BAD_PARAM; ++ } ++ ++ regVal = MV_REG_READ(SDRAM_ECC_CONTROL_REG); ++ regVal &= ~SECR_THRECC_MASK; ++ regVal |= ((SECR_THRECC(threshold) & SECR_THRECC_MASK)); ++ MV_REG_WRITE(SDRAM_ECC_CONTROL_REG, regVal); ++ ++ return MV_OK; ++} ++ ++#ifndef MV_STATIC_DRAM_ON_BOARD ++/******************************************************************************* ++* minCasCalc - Calculate the Minimum CAS latency which can be used. ++* ++* DESCRIPTION: ++* Calculate the minimum CAS latency that can be used, base on the DRAM ++* parameters and the SDRAM bus Clock freq. ++* ++* INPUT: ++* busClk - the DRAM bus Clock. ++* pBankInfo - bank info parameters. ++* forcedCl - Forced CAS Latency multiplied by 10. If equal to zero, do not force. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* The minimum CAS Latency. The function returns 0 if max CAS latency ++* supported by banks is incompatible with system bus clock frequancy. ++* ++*******************************************************************************/ ++ ++static MV_U32 minCasCalc(MV_DRAM_BANK_INFO *pBankInfo,MV_DRAM_BANK_INFO *pBankInfo2, MV_U32 busClk, MV_U32 forcedCl) ++{ ++ MV_U32 count = 1, j; ++ MV_U32 busClkPs = 1000000000 / (busClk / 1000); /* in ps units */ ++ MV_U32 startBit, stopBit; ++ MV_U32 minCas0 = 0, minCas2 = 0; ++ ++ ++ /* DDR 2: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * ++ Disco VI= * TBD | TBD | 5 | 4 | 3 | TBD | TBD | TBD * ++ Disco Duo= * TBD | 6 | 5 | 4 | 3 | TBD | TBD | TBD * ++ *********************************************************/ ++ ++ ++ /* If we are asked to use the forced CAL we change the suported CAL to be forcedCl only */ ++ if (forcedCl) ++ { ++ mvOsOutput("DRAM: Using forced CL %d.%d\n", (forcedCl / 10), (forcedCl % 10)); ++ ++ if (forcedCl == 30) ++ pBankInfo->suportedCasLatencies = 0x08; ++ else if (forcedCl == 40) ++ pBankInfo->suportedCasLatencies = 0x10; ++ else if (forcedCl == 50) ++ pBankInfo->suportedCasLatencies = 0x20; ++ else if (forcedCl == 60) ++ pBankInfo->suportedCasLatencies = 0x40; ++ else ++ { ++ mvOsPrintf("Forced CL %d.%d not supported. Set default CL 4\n", ++ (forcedCl / 10), (forcedCl % 10)); ++ pBankInfo->suportedCasLatencies = 0x10; ++ } ++ ++ return pBankInfo->suportedCasLatencies; ++ } ++ ++ /* go over the supported cas mask from Max Cas down and check if the */ ++ /* SysClk stands in its time requirments. */ ++ ++ DB(mvOsPrintf("Dram: minCasCalc supported mask = %x busClkPs = %x \n", ++ pBankInfo->suportedCasLatencies,busClkPs )); ++ count = 1; ++ for(j = 7; j > 0; j--) ++ { ++ if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) ++ { ++ /* Reset the bits for CL incompatible for the sysClk */ ++ switch (count) ++ { ++ case 1: ++ if (pBankInfo->minCycleTimeAtMaxCasLatPs > busClkPs) ++ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); ++ count++; ++ break; ++ case 2: ++ if (pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps > busClkPs) ++ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); ++ count++; ++ break; ++ case 3: ++ if (pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps > busClkPs) ++ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); ++ count++; ++ break; ++ default: ++ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); ++ break; ++ } ++ } ++ } ++ ++ DB(mvOsPrintf("Dram: minCasCalc support = %x (after SysCC calc)\n", ++ pBankInfo->suportedCasLatencies )); ++ ++ count = 1; ++ DB(mvOsPrintf("Dram2: minCasCalc supported mask = %x busClkPs = %x \n", ++ pBankInfo2->suportedCasLatencies,busClkPs )); ++ for(j = 7; j > 0; j--) ++ { ++ if((pBankInfo2->suportedCasLatencies >> j) & BIT0 ) ++ { ++ /* Reset the bits for CL incompatible for the sysClk */ ++ switch (count) ++ { ++ case 1: ++ if (pBankInfo2->minCycleTimeAtMaxCasLatPs > busClkPs) ++ pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); ++ count++; ++ break; ++ case 2: ++ if (pBankInfo2->minCycleTimeAtMaxCasLatMinus1Ps > busClkPs) ++ pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); ++ count++; ++ break; ++ case 3: ++ if (pBankInfo2->minCycleTimeAtMaxCasLatMinus2Ps > busClkPs) ++ pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); ++ count++; ++ break; ++ default: ++ pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); ++ break; ++ } ++ } ++ } ++ ++ DB(mvOsPrintf("Dram2: minCasCalc support = %x (after SysCC calc)\n", ++ pBankInfo2->suportedCasLatencies )); ++ ++ startBit = 3; /* DDR2 support CL start with CL3 (bit 3) */ ++ stopBit = 6; /* DDR2 support CL stops with CL6 (bit 6) */ ++ ++ for(j = startBit; j <= stopBit ; j++) ++ { ++ if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) ++ { ++ DB(mvOsPrintf("Dram: minCasCalc choose CAS %x \n",(BIT0 << j))); ++ minCas0 = (BIT0 << j); ++ break; ++ } ++ } ++ ++ for(j = startBit; j <= stopBit ; j++) ++ { ++ if((pBankInfo2->suportedCasLatencies >> j) & BIT0 ) ++ { ++ DB(mvOsPrintf("Dram: minCasCalc choose CAS %x \n",(BIT0 << j))); ++ minCas2 = (BIT0 << j); ++ break; ++ } ++ } ++ ++ if (minCas2 > minCas0) ++ return minCas2; ++ else ++ return minCas0; ++ ++ return 0; ++} ++ ++/******************************************************************************* ++* sdramConfigRegCalc - Calculate sdram config register ++* ++* DESCRIPTION: Calculate sdram config register optimized value based ++* on the bank info parameters. ++* ++* INPUT: ++* busClk - the DRAM bus Clock. ++* pBankInfo - sdram bank parameters ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram config reg value. ++* ++*******************************************************************************/ ++static MV_U32 sdramConfigRegCalc(MV_DRAM_BANK_INFO *pBankInfo,MV_DRAM_BANK_INFO *pBankInfo2, MV_U32 busClk) ++{ ++ MV_U32 sdramConfig = 0; ++ MV_U32 refreshPeriod; ++ ++ busClk /= 1000000; /* we work with busClk in MHz */ ++ ++ sdramConfig = MV_REG_READ(SDRAM_CONFIG_REG); ++ ++ /* figure out the memory refresh internal */ ++ switch (pBankInfo->refreshInterval & 0xf) ++ { ++ case 0x0: /* refresh period is 15.625 usec */ ++ refreshPeriod = 15625; ++ break; ++ case 0x1: /* refresh period is 3.9 usec */ ++ refreshPeriod = 3900; ++ break; ++ case 0x2: /* refresh period is 7.8 usec */ ++ refreshPeriod = 7800; ++ break; ++ case 0x3: /* refresh period is 31.3 usec */ ++ refreshPeriod = 31300; ++ break; ++ case 0x4: /* refresh period is 62.5 usec */ ++ refreshPeriod = 62500; ++ break; ++ case 0x5: /* refresh period is 125 usec */ ++ refreshPeriod = 125000; ++ break; ++ default: /* refresh period undefined */ ++ mvOsPrintf("Dram: ERR. DRAM refresh period is unknown!\n"); ++ return -1; ++ } ++ ++ /* Now the refreshPeriod is in register format value */ ++ refreshPeriod = (busClk * refreshPeriod) / 1000; ++ ++ DB(mvOsPrintf("Dram: sdramConfigRegCalc calculated refresh interval %0x\n", ++ refreshPeriod)); ++ ++ /* make sure the refresh value is only 14 bits */ ++ if(refreshPeriod > SDRAM_REFRESH_MAX) ++ { ++ refreshPeriod = SDRAM_REFRESH_MAX; ++ DB(mvOsPrintf("Dram: sdramConfigRegCalc adjusted refresh interval %0x\n", ++ refreshPeriod)); ++ } ++ ++ /* Clear the refresh field */ ++ sdramConfig &= ~SDRAM_REFRESH_MASK; ++ ++ /* Set new value to refresh field */ ++ sdramConfig |= (refreshPeriod & SDRAM_REFRESH_MASK); ++ ++ /* registered DRAM ? */ ++ if ( pBankInfo->registeredAddrAndControlInputs ) ++ { ++ /* it's registered DRAM, so set the reg. DRAM bit */ ++ sdramConfig |= SDRAM_REGISTERED; ++ DB(mvOsPrintf("DRAM Attribute: Registered address and control inputs.\n");) ++ } ++ ++ /* ECC and IERR support */ ++ sdramConfig &= ~SDRAM_ECC_MASK; /* Clear ECC field */ ++ sdramConfig &= ~SDRAM_IERR_MASK; /* Clear IErr field */ ++ ++ if ( pBankInfo->errorCheckType ) ++ { ++ sdramConfig |= SDRAM_ECC_EN; ++ sdramConfig |= SDRAM_IERR_REPORTE; ++ DB(mvOsPrintf("Dram: mvDramIfDetect Enabling ECC\n")); ++ } ++ else ++ { ++ sdramConfig |= SDRAM_ECC_DIS; ++ sdramConfig |= SDRAM_IERR_IGNORE; ++ DB(mvOsPrintf("Dram: mvDramIfDetect Disabling ECC!\n")); ++ } ++ /* Set static default settings */ ++ sdramConfig |= SDRAM_CONFIG_DV; ++ ++ DB(mvOsPrintf("Dram: sdramConfigRegCalc set sdramConfig to 0x%x\n", ++ sdramConfig)); ++ ++ return sdramConfig; ++} ++ ++/******************************************************************************* ++* sdramModeRegCalc - Calculate sdram mode register ++* ++* DESCRIPTION: Calculate sdram mode register optimized value based ++* on the bank info parameters and the minCas. ++* ++* INPUT: ++* minCas - minimum CAS supported. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram mode reg value. ++* ++*******************************************************************************/ ++static MV_U32 sdramModeRegCalc(MV_U32 minCas) ++{ ++ MV_U32 sdramMode; ++ ++ sdramMode = MV_REG_READ(SDRAM_MODE_REG); ++ ++ /* Clear CAS Latency field */ ++ sdramMode &= ~SDRAM_CL_MASK; ++ ++ DB(mvOsPrintf("DRAM CAS Latency ");) ++ ++ switch (minCas) ++ { ++ case DDR2_CL_3: ++ sdramMode |= SDRAM_DDR2_CL_3; ++ DB(mvOsPrintf("3.\n");) ++ break; ++ case DDR2_CL_4: ++ sdramMode |= SDRAM_DDR2_CL_4; ++ DB(mvOsPrintf("4.\n");) ++ break; ++ case DDR2_CL_5: ++ sdramMode |= SDRAM_DDR2_CL_5; ++ DB(mvOsPrintf("5.\n");) ++ break; ++ case DDR2_CL_6: ++ sdramMode |= SDRAM_DDR2_CL_6; ++ DB(mvOsPrintf("6.\n");) ++ break; ++ default: ++ mvOsOutput("\nsdramModeRegCalc ERROR: Max. CL out of range\n"); ++ return -1; ++ } ++ ++ DB(mvOsPrintf("\nsdramModeRegCalc register 0x%x\n", sdramMode )); ++ ++ return sdramMode; ++} ++/******************************************************************************* ++* sdramExtModeRegCalc - Calculate sdram Extended mode register ++* ++* DESCRIPTION: ++* Return sdram Extended mode register value based ++* on the bank info parameters and bank presence. ++* ++* INPUT: ++* pBankInfo - sdram bank parameters ++* busClk - DRAM frequency ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram Extended mode reg value. ++* ++*******************************************************************************/ ++static MV_U32 sdramExtModeRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) ++{ ++ MV_U32 populateBanks = 0; ++ int bankNum; ++ ++ /* Represent the populate banks in binary form */ ++ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) ++ { ++ if (0 != pBankInfo[bankNum].size) ++ { ++ populateBanks |= (1 << bankNum); ++ } ++ } ++ ++ switch(populateBanks) ++ { ++ case(BANK_PRESENT_CS0): ++ case(BANK_PRESENT_CS0_CS1): ++ return DDR_SDRAM_EXT_MODE_CS0_CS1_DV; ++ ++ case(BANK_PRESENT_CS0_CS2): ++ case(BANK_PRESENT_CS0_CS1_CS2): ++ case(BANK_PRESENT_CS0_CS2_CS3): ++ case(BANK_PRESENT_CS0_CS2_CS3_CS4): ++ if (busClk >= MV_BOARD_SYSCLK_267MHZ) ++ return DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV; ++ else ++ return DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV; ++ ++ default: ++ mvOsOutput("sdramExtModeRegCalc: Invalid DRAM bank presence\n"); ++ return -1; ++ } ++ return 0; ++} ++ ++/******************************************************************************* ++* dunitCtrlLowRegCalc - Calculate sdram dunit control low register ++* ++* DESCRIPTION: Calculate sdram dunit control low register optimized value based ++* on the bank info parameters and the minCas. ++* ++* INPUT: ++* pBankInfo - sdram bank parameters ++* minCas - minimum CAS supported. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram dunit control low reg value. ++* ++*******************************************************************************/ ++static MV_U32 dunitCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas, MV_U32 busClk, MV_STATUS TTMode) ++{ ++ MV_U32 dunitCtrlLow, cl; ++ MV_U32 sbOutR[4]={3,5,7,9} ; ++ MV_U32 sbOutU[4]={1,3,5,7} ; ++ ++ dunitCtrlLow = MV_REG_READ(SDRAM_DUNIT_CTRL_REG); ++ ++ DB(mvOsPrintf("Dram: dunitCtrlLowRegCalc\n")); ++ ++ /* Clear StBurstOutDel field */ ++ dunitCtrlLow &= ~SDRAM_SB_OUT_MASK; ++ ++ /* Clear StBurstInDel field */ ++ dunitCtrlLow &= ~SDRAM_SB_IN_MASK; ++ ++ /* Clear CtrlPos field */ ++ dunitCtrlLow &= ~SDRAM_CTRL_POS_MASK; ++ ++ /* Clear 2T field */ ++ dunitCtrlLow &= ~SDRAM_2T_MASK; ++ if (TTMode == MV_TRUE) ++ { ++ dunitCtrlLow |= SDRAM_2T_MODE; ++ } ++ ++ /* For proper sample of read data set the Dunit Control register's */ ++ /* stBurstInDel bits [27:24] */ ++ /* 200MHz - 267MHz None reg = CL + 1 */ ++ /* 200MHz - 267MHz reg = CL + 2 */ ++ /* > 267MHz None reg = CL + 2 */ ++ /* > 267MHz reg = CL + 3 */ ++ ++ /* For proper sample of read data set the Dunit Control register's */ ++ /* stBurstOutDel bits [23:20] */ ++ /********-********-********-********- ++ * CL=3 | CL=4 | CL=5 | CL=6 | ++ *********-********-********-********- ++ Not Reg. * 0001 | 0011 | 0101 | 0111 | ++ *********-********-********-********- ++ Registered * 0011 | 0101 | 0111 | 1001 | ++ *********-********-********-********/ ++ ++ /* Set Dunit Control low default value */ ++ dunitCtrlLow |= SDRAM_DUNIT_CTRL_LOW_DDR2_DV; ++ ++ switch (minCas) ++ { ++ case DDR2_CL_3: cl = 3; break; ++ case DDR2_CL_4: cl = 4; break; ++ case DDR2_CL_5: cl = 5; break; ++ case DDR2_CL_6: cl = 6; break; ++ default: ++ mvOsOutput("Dram: dunitCtrlLowRegCalc Max. CL out of range %d\n", minCas); ++ return -1; ++ } ++ ++ /* registerd DDR SDRAM? */ ++ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) ++ { ++ dunitCtrlLow |= (sbOutR[cl-3]) << SDRAM_SB_OUT_DEL_OFFS; ++ } ++ else ++ { ++ dunitCtrlLow |= (sbOutU[cl-3]) << SDRAM_SB_OUT_DEL_OFFS; ++ } ++ ++ DB(mvOsPrintf("\n\ndunitCtrlLowRegCalc: CL = %d, frequencies=%d\n", cl, busClk)); ++ ++ if (busClk <= MV_BOARD_SYSCLK_267MHZ) ++ { ++ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) ++ cl = cl + 2; ++ else ++ cl = cl + 1; ++ } ++ else ++ { ++ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) ++ cl = cl + 3; ++ else ++ cl = cl + 2; ++ } ++ ++ DB(mvOsPrintf("dunitCtrlLowRegCalc: SDRAM_SB_IN_DEL_OFFS = %d \n", cl)); ++ dunitCtrlLow |= cl << SDRAM_SB_IN_DEL_OFFS; ++ ++ DB(mvOsPrintf("Dram: Reg dunit control low = %x\n", dunitCtrlLow )); ++ ++ return dunitCtrlLow; ++} ++ ++/******************************************************************************* ++* dunitCtrlHighRegCalc - Calculate sdram dunit control high register ++* ++* DESCRIPTION: Calculate sdram dunit control high register optimized value based ++* on the bus clock. ++* ++* INPUT: ++* busClk - DRAM frequency. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram dunit control high reg value. ++* ++*******************************************************************************/ ++static MV_U32 dunitCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) ++{ ++ MV_U32 dunitCtrlHigh; ++ dunitCtrlHigh = MV_REG_READ(SDRAM_DUNIT_CTRL_HI_REG); ++ if(busClk > MV_BOARD_SYSCLK_300MHZ) ++ dunitCtrlHigh |= SDRAM__P2D_EN; ++ else ++ dunitCtrlHigh &= ~SDRAM__P2D_EN; ++ ++ if(busClk > MV_BOARD_SYSCLK_267MHZ) ++ dunitCtrlHigh |= (SDRAM__WR_MESH_DELAY_EN | SDRAM__PUP_ZERO_SKEW_EN | SDRAM__ADD_HALF_FCC_EN); ++ ++ /* If ECC support we turn on D2P sample */ ++ dunitCtrlHigh &= ~SDRAM__D2P_EN; /* Clear D2P bit */ ++ if (( pBankInfo->errorCheckType ) && (busClk > MV_BOARD_SYSCLK_267MHZ)) ++ dunitCtrlHigh |= SDRAM__D2P_EN; ++ ++ return dunitCtrlHigh; ++} ++ ++/******************************************************************************* ++* sdramAddrCtrlRegCalc - Calculate sdram address control register ++* ++* DESCRIPTION: Calculate sdram address control register optimized value based ++* on the bank info parameters and the minCas. ++* ++* INPUT: ++* pBankInfo - sdram bank parameters ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram address control reg value. ++* ++*******************************************************************************/ ++static MV_U32 sdramAddrCtrlRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_DRAM_BANK_INFO *pBankInfoDIMM1) ++{ ++ MV_U32 addrCtrl = 0; ++ ++ if (pBankInfoDIMM1->size) ++ { ++ switch (pBankInfoDIMM1->sdramWidth) ++ { ++ case 4: /* memory is x4 */ ++ mvOsOutput("sdramAddrCtrlRegCalc: Error - x4 not supported!\n"); ++ return -1; ++ break; ++ case 8: /* memory is x8 */ ++ addrCtrl |= SDRAM_ADDRSEL_X8(2) | SDRAM_ADDRSEL_X8(3); ++ DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device DIMM2 width x8\n")); ++ break; ++ case 16: ++ addrCtrl |= SDRAM_ADDRSEL_X16(2) | SDRAM_ADDRSEL_X16(3); ++ DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device DIMM2 width x16\n")); ++ break; ++ default: /* memory width unsupported */ ++ mvOsOutput("sdramAddrCtrlRegCalc: ERR. DRAM chip width is unknown!\n"); ++ return -1; ++ } ++ } ++ ++ switch (pBankInfo->sdramWidth) ++ { ++ case 4: /* memory is x4 */ ++ mvOsOutput("sdramAddrCtrlRegCalc: Error - x4 not supported!\n"); ++ return -1; ++ break; ++ case 8: /* memory is x8 */ ++ addrCtrl |= SDRAM_ADDRSEL_X8(0) | SDRAM_ADDRSEL_X8(1); ++ DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device width x8\n")); ++ break; ++ case 16: ++ addrCtrl |= SDRAM_ADDRSEL_X16(0) | SDRAM_ADDRSEL_X16(1); ++ DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device width x16\n")); ++ break; ++ default: /* memory width unsupported */ ++ mvOsOutput("sdramAddrCtrlRegCalc: ERR. DRAM chip width is unknown!\n"); ++ return -1; ++ } ++ ++ /* Note that density is in MB units */ ++ switch (pBankInfo->deviceDensity) ++ { ++ case 256: /* 256 Mbit */ ++ DB(mvOsPrintf("DRAM Device Density 256Mbit\n")); ++ addrCtrl |= SDRAM_DSIZE_256Mb(0) | SDRAM_DSIZE_256Mb(1); ++ break; ++ case 512: /* 512 Mbit */ ++ DB(mvOsPrintf("DRAM Device Density 512Mbit\n")); ++ addrCtrl |= SDRAM_DSIZE_512Mb(0) | SDRAM_DSIZE_512Mb(1); ++ break; ++ case 1024: /* 1 Gbit */ ++ DB(mvOsPrintf("DRAM Device Density 1Gbit\n")); ++ addrCtrl |= SDRAM_DSIZE_1Gb(0) | SDRAM_DSIZE_1Gb(1); ++ break; ++ case 2048: /* 2 Gbit */ ++ DB(mvOsPrintf("DRAM Device Density 2Gbit\n")); ++ addrCtrl |= SDRAM_DSIZE_2Gb(0) | SDRAM_DSIZE_2Gb(1); ++ break; ++ default: ++ mvOsOutput("Dram: sdramAddrCtrl unsupported RAM-Device size %d\n", ++ pBankInfo->deviceDensity); ++ return -1; ++ } ++ ++ if (pBankInfoDIMM1->size) ++ { ++ switch (pBankInfoDIMM1->deviceDensity) ++ { ++ case 256: /* 256 Mbit */ ++ DB(mvOsPrintf("DIMM2: DRAM Device Density 256Mbit\n")); ++ addrCtrl |= SDRAM_DSIZE_256Mb(2) | SDRAM_DSIZE_256Mb(3); ++ break; ++ case 512: /* 512 Mbit */ ++ DB(mvOsPrintf("DIMM2: DRAM Device Density 512Mbit\n")); ++ addrCtrl |= SDRAM_DSIZE_512Mb(2) | SDRAM_DSIZE_512Mb(3); ++ break; ++ case 1024: /* 1 Gbit */ ++ DB(mvOsPrintf("DIMM2: DRAM Device Density 1Gbit\n")); ++ addrCtrl |= SDRAM_DSIZE_1Gb(2) | SDRAM_DSIZE_1Gb(3); ++ break; ++ case 2048: /* 2 Gbit */ ++ DB(mvOsPrintf("DIMM2: DRAM Device Density 2Gbit\n")); ++ addrCtrl |= SDRAM_DSIZE_2Gb(2) | SDRAM_DSIZE_2Gb(3); ++ break; ++ default: ++ mvOsOutput("DIMM2: Dram: sdramAddrCtrl unsupported RAM-Device size %d\n", ++ pBankInfoDIMM1->deviceDensity); ++ return -1; ++ } ++ } ++ /* SDRAM address control */ ++ DB(mvOsPrintf("Dram: setting sdram address control with: %x \n", addrCtrl)); ++ ++ return addrCtrl; ++} ++ ++/******************************************************************************* ++* sdramTimeCtrlLowRegCalc - Calculate sdram timing control low register ++* ++* DESCRIPTION: ++* This function calculates sdram timing control low register ++* optimized value based on the bank info parameters and the minCas. ++* ++* INPUT: ++* pBankInfo - sdram bank parameters ++* minCas - minimum CAS supported. ++* busClk - Bus clock ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram timing control low reg value. ++* ++*******************************************************************************/ ++static MV_U32 sdramTimeCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas, MV_U32 busClk) ++{ ++ MV_U32 tRp = 0; ++ MV_U32 tRrd = 0; ++ MV_U32 tRcd = 0; ++ MV_U32 tRas = 0; ++ MV_U32 tWr = 0; ++ MV_U32 tWtr = 0; ++ MV_U32 tRtp = 0; ++ MV_U32 timeCtrlLow = 0; ++ ++ MV_U32 bankNum; ++ ++ busClk = busClk / 1000000; /* In MHz */ ++ ++ /* Scan all DRAM banks to find maximum timing values */ ++ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) ++ { ++ tRp = MV_MAX(tRp, pBankInfo[bankNum].minRowPrechargeTime); ++ tRrd = MV_MAX(tRrd, pBankInfo[bankNum].minRowActiveToRowActive); ++ tRcd = MV_MAX(tRcd, pBankInfo[bankNum].minRasToCasDelay); ++ tRas = MV_MAX(tRas, pBankInfo[bankNum].minRasPulseWidth); ++ } ++ ++ /* Extract timing (in ns) from SPD value. We ignore the tenth ns part. */ ++ /* by shifting the data two bits right. */ ++ tRp = tRp >> 2; /* For example 0x50 -> 20ns */ ++ tRrd = tRrd >> 2; ++ tRcd = tRcd >> 2; ++ ++ /* Extract clock cycles from time parameter. We need to round up */ ++ tRp = ((busClk * tRp) / 1000) + (((busClk * tRp) % 1000) ? 1 : 0); ++ DB(mvOsPrintf("Dram Timing Low: tRp = %d ", tRp)); ++ tRrd = ((busClk * tRrd) / 1000) + (((busClk * tRrd) % 1000) ? 1 : 0); ++ /* JEDEC min reqeirments tRrd = 2 */ ++ if (tRrd < 2) ++ tRrd = 2; ++ DB(mvOsPrintf("tRrd = %d ", tRrd)); ++ tRcd = ((busClk * tRcd) / 1000) + (((busClk * tRcd) % 1000) ? 1 : 0); ++ DB(mvOsPrintf("tRcd = %d ", tRcd)); ++ tRas = ((busClk * tRas) / 1000) + (((busClk * tRas) % 1000) ? 1 : 0); ++ DB(mvOsPrintf("tRas = %d ", tRas)); ++ ++ /* tWr and tWtr is different for DDR1 and DDR2. tRtp is only for DDR2 */ ++ /* Scan all DRAM banks to find maximum timing values */ ++ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) ++ { ++ tWr = MV_MAX(tWr, pBankInfo[bankNum].minWriteRecoveryTime); ++ tWtr = MV_MAX(tWtr, pBankInfo[bankNum].minWriteToReadCmdDelay); ++ tRtp = MV_MAX(tRtp, pBankInfo[bankNum].minReadToPrechCmdDelay); ++ } ++ ++ /* Extract timing (in ns) from SPD value. We ignore the tenth ns */ ++ /* part by shifting the data two bits right. */ ++ tWr = tWr >> 2; /* For example 0x50 -> 20ns */ ++ tWtr = tWtr >> 2; ++ tRtp = tRtp >> 2; ++ /* Extract clock cycles from time parameter. We need to round up */ ++ tWr = ((busClk * tWr) / 1000) + (((busClk * tWr) % 1000) ? 1 : 0); ++ DB(mvOsPrintf("tWr = %d ", tWr)); ++ tWtr = ((busClk * tWtr) / 1000) + (((busClk * tWtr) % 1000) ? 1 : 0); ++ /* JEDEC min reqeirments tWtr = 2 */ ++ if (tWtr < 2) ++ tWtr = 2; ++ DB(mvOsPrintf("tWtr = %d ", tWtr)); ++ tRtp = ((busClk * tRtp) / 1000) + (((busClk * tRtp) % 1000) ? 1 : 0); ++ /* JEDEC min reqeirments tRtp = 2 */ ++ if (tRtp < 2) ++ tRtp = 2; ++ DB(mvOsPrintf("tRtp = %d ", tRtp)); ++ ++ /* Note: value of 0 in register means one cycle, 1 means two and so on */ ++ timeCtrlLow = (((tRp - 1) << SDRAM_TRP_OFFS) | ++ ((tRrd - 1) << SDRAM_TRRD_OFFS) | ++ ((tRcd - 1) << SDRAM_TRCD_OFFS) | ++ (((tRas - 1) << SDRAM_TRAS_OFFS) & SDRAM_TRAS_MASK)| ++ ((tWr - 1) << SDRAM_TWR_OFFS) | ++ ((tWtr - 1) << SDRAM_TWTR_OFFS) | ++ ((tRtp - 1) << SDRAM_TRTP_OFFS)); ++ ++ /* Check extended tRas bit */ ++ if ((tRas - 1) & BIT4) ++ timeCtrlLow |= (1 << SDRAM_EXT_TRAS_OFFS); ++ ++ return timeCtrlLow; ++} ++ ++/******************************************************************************* ++* sdramTimeCtrlHighRegCalc - Calculate sdram timing control high register ++* ++* DESCRIPTION: ++* This function calculates sdram timing control high register ++* optimized value based on the bank info parameters and the bus clock. ++* ++* INPUT: ++* pBankInfo - sdram bank parameters ++* busClk - Bus clock ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram timing control high reg value. ++* ++*******************************************************************************/ ++static MV_U32 sdramTimeCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) ++{ ++ MV_U32 tRfc; ++ MV_U32 timingHigh; ++ MV_U32 timeNs = 0; ++ MV_U32 bankNum; ++ ++ busClk = busClk / 1000000; /* In MHz */ ++ ++ /* Set DDR timing high register static configuration bits */ ++ timingHigh = MV_REG_READ(SDRAM_TIMING_CTRL_HIGH_REG); ++ ++ /* Set DDR timing high register default value */ ++ timingHigh |= SDRAM_TIMING_CTRL_HIGH_REG_DV; ++ ++ /* Clear tRfc field */ ++ timingHigh &= ~SDRAM_TRFC_MASK; ++ ++ /* Scan all DRAM banks to find maximum timing values */ ++ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) ++ { ++ timeNs = MV_MAX(timeNs, pBankInfo[bankNum].minRefreshToActiveCmd); ++ DB(mvOsPrintf("Dram: Timing High: minRefreshToActiveCmd = %d\n", ++ pBankInfo[bankNum].minRefreshToActiveCmd)); ++ } ++ if(busClk >= 333 && mvCtrlModelGet() == MV_78XX0_A1_REV) ++ { ++ timingHigh |= 0x1 << SDRAM_TR2W_W2R_OFFS; ++ } ++ ++ tRfc = ((busClk * timeNs) / 1000) + (((busClk * timeNs) % 1000) ? 1 : 0); ++ /* Note: value of 0 in register means one cycle, 1 means two and so on */ ++ DB(mvOsPrintf("Dram: Timing High: tRfc = %d\n", tRfc)); ++ timingHigh |= (((tRfc - 1) & SDRAM_TRFC_MASK) << SDRAM_TRFC_OFFS); ++ DB(mvOsPrintf("Dram: Timing High: tRfc = %d\n", tRfc)); ++ ++ /* SDRAM timing high */ ++ DB(mvOsPrintf("Dram: setting timing high with: %x \n", timingHigh)); ++ ++ return timingHigh; ++} ++/******************************************************************************* ++* sdramDDr2OdtConfig - Set DRAM DDR2 On Die Termination registers. ++* ++* DESCRIPTION: ++* This function config DDR2 On Die Termination (ODT) registers. ++* ++* INPUT: ++* pBankInfo - bank info parameters. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* None ++*******************************************************************************/ ++static void sdramDDr2OdtConfig(MV_DRAM_BANK_INFO *pBankInfo) ++{ ++ MV_U32 populateBanks = 0; ++ MV_U32 odtCtrlLow, odtCtrlHigh, dunitOdtCtrl; ++ int bankNum; ++ ++ /* Represent the populate banks in binary form */ ++ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) ++ { ++ if (0 != pBankInfo[bankNum].size) ++ { ++ populateBanks |= (1 << bankNum); ++ } ++ } ++ ++ switch(populateBanks) ++ { ++ case(BANK_PRESENT_CS0): ++ case(BANK_PRESENT_CS0_CS1): ++ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS1_DV; ++ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS1_DV; ++ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV; ++ break; ++ case(BANK_PRESENT_CS0_CS2): ++ case(BANK_PRESENT_CS0_CS1_CS2): ++ case(BANK_PRESENT_CS0_CS2_CS3): ++ case(BANK_PRESENT_CS0_CS2_CS3_CS4): ++ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV; ++ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS1_CS2_CS3_DV; ++ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV; ++ break; ++ default: ++ DB(mvOsPrintf("sdramDDr2OdtConfig: Invalid DRAM bank presence\n")); ++ return; ++ } ++ /* DDR2 SDRAM ODT ctrl low */ ++ DB(mvOsPrintf("Dram: DDR2 setting ODT ctrl low with: %x \n", odtCtrlLow)); ++ MV_REG_WRITE(DRAM_BUF_REG7, odtCtrlLow); ++ ++ /* DDR2 SDRAM ODT ctrl high */ ++ DB(mvOsPrintf("Dram: DDR2 setting ODT ctrl high with: %x \n", odtCtrlHigh)); ++ MV_REG_WRITE(DRAM_BUF_REG8, odtCtrlHigh); ++ ++ /* DDR2 DUNIT ODT ctrl */ ++ if ( ((mvCtrlModelGet() == MV_78XX0_DEV_ID) && (mvCtrlRevGet() == MV_78XX0_Y0_REV)) || ++ (mvCtrlModelGet() == MV_76100_DEV_ID) || ++ (mvCtrlModelGet() == MV_78100_DEV_ID) || ++ (mvCtrlModelGet() == MV_78200_DEV_ID) ) ++ dunitOdtCtrl &= ~(BIT9|BIT8); /* Clear ODT always on */ ++ ++ DB(mvOsPrintf("DUNIT: DDR2 setting ODT ctrl with: %x \n", dunitOdtCtrl)); ++ MV_REG_WRITE(DRAM_BUF_REG9, dunitOdtCtrl); ++ return; ++} ++/******************************************************************************* ++* sdramDdr2TimeLoRegCalc - Set DDR2 DRAM Timing Low registers. ++* ++* DESCRIPTION: ++* This function config DDR2 DRAM Timing low registers. ++* ++* INPUT: ++* minCas - minimum CAS supported. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* DDR2 sdram timing low reg value. ++*******************************************************************************/ ++static MV_U32 sdramDdr2TimeLoRegCalc(MV_U32 minCas) ++{ ++ MV_U8 cl = -1; ++ MV_U32 ddr2TimeLoReg; ++ ++ /* read and clear the feilds we are going to set */ ++ ddr2TimeLoReg = MV_REG_READ(SDRAM_DDR2_TIMING_LO_REG); ++ ddr2TimeLoReg &= ~(SD2TLR_TODT_ON_RD_MASK | ++ SD2TLR_TODT_OFF_RD_MASK | ++ SD2TLR_TODT_ON_CTRL_RD_MASK | ++ SD2TLR_TODT_OFF_CTRL_RD_MASK); ++ ++ if( minCas == DDR2_CL_3 ) ++ { ++ cl = 3; ++ } ++ else if( minCas == DDR2_CL_4 ) ++ { ++ cl = 4; ++ } ++ else if( minCas == DDR2_CL_5 ) ++ { ++ cl = 5; ++ } ++ else if( minCas == DDR2_CL_6 ) ++ { ++ cl = 6; ++ } ++ else ++ { ++ DB(mvOsPrintf("sdramDdr2TimeLoRegCalc: CAS latency %d unsupported. using CAS latency 4\n", ++ minCas)); ++ cl = 4; ++ } ++ ++ ddr2TimeLoReg |= ((cl-3) << SD2TLR_TODT_ON_RD_OFFS); ++ ddr2TimeLoReg |= ( cl << SD2TLR_TODT_OFF_RD_OFFS); ++ ddr2TimeLoReg |= ( cl << SD2TLR_TODT_ON_CTRL_RD_OFFS); ++ ddr2TimeLoReg |= ((cl+3) << SD2TLR_TODT_OFF_CTRL_RD_OFFS); ++ ++ /* DDR2 SDRAM timing low */ ++ DB(mvOsPrintf("Dram: DDR2 setting timing low with: %x \n", ddr2TimeLoReg)); ++ ++ return ddr2TimeLoReg; ++} ++ ++/******************************************************************************* ++* sdramDdr2TimeHiRegCalc - Set DDR2 DRAM Timing High registers. ++* ++* DESCRIPTION: ++* This function config DDR2 DRAM Timing high registers. ++* ++* INPUT: ++* minCas - minimum CAS supported. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* DDR2 sdram timing high reg value. ++*******************************************************************************/ ++static MV_U32 sdramDdr2TimeHiRegCalc(MV_U32 minCas) ++{ ++ MV_U8 cl = -1; ++ MV_U32 ddr2TimeHiReg; ++ ++ /* read and clear the feilds we are going to set */ ++ ddr2TimeHiReg = MV_REG_READ(SDRAM_DDR2_TIMING_HI_REG); ++ ddr2TimeHiReg &= ~(SD2THR_TODT_ON_WR_MASK | ++ SD2THR_TODT_OFF_WR_MASK | ++ SD2THR_TODT_ON_CTRL_WR_MASK | ++ SD2THR_TODT_OFF_CTRL_WR_MASK); ++ ++ if( minCas == DDR2_CL_3 ) ++ { ++ cl = 3; ++ } ++ else if( minCas == DDR2_CL_4 ) ++ { ++ cl = 4; ++ } ++ else if( minCas == DDR2_CL_5 ) ++ { ++ cl = 5; ++ } ++ else if( minCas == DDR2_CL_6 ) ++ { ++ cl = 6; ++ } ++ else ++ { ++ mvOsOutput("sdramDdr2TimeHiRegCalc: CAS latency %d unsupported. using CAS latency 4\n", ++ minCas); ++ cl = 4; ++ } ++ ++ ddr2TimeHiReg |= ((cl-3) << SD2THR_TODT_ON_WR_OFFS); ++ ddr2TimeHiReg |= ( cl << SD2THR_TODT_OFF_WR_OFFS); ++ ddr2TimeHiReg |= ( cl << SD2THR_TODT_ON_CTRL_WR_OFFS); ++ ddr2TimeHiReg |= ((cl+3) << SD2THR_TODT_OFF_CTRL_WR_OFFS); ++ ++ /* DDR2 SDRAM timin high */ ++ DB(mvOsPrintf("Dram: DDR2 setting timing high with: %x \n", ddr2TimeHiReg)); ++ ++ return ddr2TimeHiReg; ++} ++#endif ++ ++/******************************************************************************* ++* mvDramIfCalGet - Get CAS Latency ++* ++* DESCRIPTION: ++* This function get the CAS Latency. ++* ++* INPUT: ++* None ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* CAS latency times 10 (to avoid using floating point). ++* ++*******************************************************************************/ ++MV_U32 mvDramIfCalGet(void) ++{ ++ MV_U32 sdramCasLat, casLatMask; ++ ++ casLatMask = (MV_REG_READ(SDRAM_MODE_REG) & SDRAM_CL_MASK); ++ ++ switch (casLatMask) ++ { ++ case SDRAM_DDR2_CL_3: ++ sdramCasLat = 30; ++ break; ++ case SDRAM_DDR2_CL_4: ++ sdramCasLat = 40; ++ break; ++ case SDRAM_DDR2_CL_5: ++ sdramCasLat = 50; ++ break; ++ case SDRAM_DDR2_CL_6: ++ sdramCasLat = 60; ++ break; ++ default: ++ mvOsOutput("mvDramIfCalGet: Err, unknown DDR2 CAL\n"); ++ return -1; ++ } ++ ++ return sdramCasLat; ++} ++ ++ ++/******************************************************************************* ++* mvDramIfSelfRefreshSet - Put the dram in self refresh mode - ++* ++* DESCRIPTION: ++* add support in power management. ++* ++* ++* INPUT: ++* None ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* None ++* ++*******************************************************************************/ ++ ++MV_VOID mvDramIfSelfRefreshSet() ++{ ++ MV_U32 operReg; ++ ++ operReg = MV_REG_READ(SDRAM_OPERATION_REG); ++ MV_REG_WRITE(SDRAM_OPERATION_REG ,operReg |SDRAM_CMD_SLF_RFRSH); ++ /* Read until register is reset to 0 */ ++ while(MV_REG_READ(SDRAM_OPERATION_REG)); ++} ++/******************************************************************************* ++* mvDramIfDimGetSPDversion - return DIMM SPD version. ++* ++* DESCRIPTION: ++* This function prints the DRAM controller information. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++static void mvDramIfDimGetSPDversion(MV_U32 *pMajor, MV_U32 *pMinor, MV_U32 bankNum) ++{ ++ MV_DIMM_INFO dimmInfo; ++ if (bankNum >= MV_DRAM_MAX_CS ) ++ { ++ DB(mvOsPrintf("Dram: mvDramIfDimGetSPDversion bad params \n")); ++ return ; ++ } ++ memset(&dimmInfo,0,sizeof(dimmInfo)); ++ if ( MV_OK != dimmSpdGet((MV_U32)(bankNum/2), &dimmInfo)) ++ { ++ DB(mvOsPrintf("Dram: ERR dimmSpdGet failed to get dimm info \n")); ++ return ; ++ } ++ *pMajor = dimmInfo.spdRawData[DIMM_SPD_VERSION]/10; ++ *pMinor = dimmInfo.spdRawData[DIMM_SPD_VERSION]%10; ++} ++/******************************************************************************* ++* mvDramIfShow - Show DRAM controller information. ++* ++* DESCRIPTION: ++* This function prints the DRAM controller information. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++void mvDramIfShow(void) ++{ ++ int i, sdramCasLat, sdramCsSize; ++ MV_U32 Major=0, Minor=0; ++ ++ mvOsOutput("DRAM Controller info:\n"); ++ ++ mvOsOutput("Total DRAM "); ++ mvSizePrint(mvDramIfSizeGet()); ++ mvOsOutput("\n"); ++ ++ for(i = 0; i < MV_DRAM_MAX_CS; i++) ++ { ++ sdramCsSize = mvDramIfBankSizeGet(i); ++ if (sdramCsSize) ++ { ++ if (0 == (i & 1)) ++ { ++ mvDramIfDimGetSPDversion(&Major, &Minor,i); ++ mvOsOutput("DIMM %d version %d.%d\n", i/2, Major, Minor); ++ } ++ mvOsOutput("\tDRAM CS[%d] ", i); ++ mvSizePrint(sdramCsSize); ++ mvOsOutput("\n"); ++ } ++ } ++ sdramCasLat = mvDramIfCalGet(); ++ ++ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_ECC_EN) ++ { ++ mvOsOutput("ECC enabled, "); ++ } ++ else ++ { ++ mvOsOutput("ECC Disabled, "); ++ } ++ ++ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_REGISTERED) ++ { ++ mvOsOutput("Registered DIMM\n"); ++ } ++ else ++ { ++ mvOsOutput("Non registered DIMM\n"); ++ } ++ ++ mvOsOutput("Configured CAS Latency %d.%d\n", sdramCasLat/10, sdramCasLat%10); ++} ++/******************************************************************************* ++* mvDramIfGetFirstCS - find the DRAM bank on the lower address ++* ++* ++* DESCRIPTION: ++* This function return the fisrt CS on address 0 ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* SDRAM_CS0 or SDRAM_CS2 ++* ++*******************************************************************************/ ++MV_U32 mvDramIfGetFirstCS(void) ++{ ++ MV_DRAM_BANK_INFO bankInfo[MV_DRAM_MAX_CS]; ++ ++ if (DRAM_CS_Order[0] == N_A) ++ { ++ mvDramBankInfoGet(SDRAM_CS0, &bankInfo[SDRAM_CS0]); ++#ifdef MV_INCLUDE_SDRAM_CS2 ++ mvDramBankInfoGet(SDRAM_CS2, &bankInfo[SDRAM_CS2]); ++#endif ++ ++#ifdef MV_INCLUDE_SDRAM_CS2 ++ if (bankInfo[SDRAM_CS0].size < bankInfo[SDRAM_CS2].size) ++ { ++ DRAM_CS_Order[0] = SDRAM_CS2; ++ DRAM_CS_Order[1] = SDRAM_CS3; ++ DRAM_CS_Order[2] = SDRAM_CS0; ++ DRAM_CS_Order[3] = SDRAM_CS1; ++ ++ return SDRAM_CS2; ++ } ++#endif ++ DRAM_CS_Order[0] = SDRAM_CS0; ++ DRAM_CS_Order[1] = SDRAM_CS1; ++#ifdef MV_INCLUDE_SDRAM_CS2 ++ DRAM_CS_Order[2] = SDRAM_CS2; ++ DRAM_CS_Order[3] = SDRAM_CS3; ++#endif ++ return SDRAM_CS0; ++ } ++ return DRAM_CS_Order[0]; ++} ++/******************************************************************************* ++* mvDramIfGetCSorder - ++* ++* ++* DESCRIPTION: ++* This function return the fisrt CS on address 0 ++* ++* INPUT: ++* CS number. ++* ++* OUTPUT: ++* CS order. ++* ++* RETURN: ++* SDRAM_CS0 or SDRAM_CS2 ++* ++* NOTE: mvDramIfGetFirstCS must be caled before this subroutine ++*******************************************************************************/ ++MV_U32 mvDramIfGetCSorder(MV_U32 csOrder ) ++{ ++ return DRAM_CS_Order[csOrder]; ++} ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,172 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvDramIfh ++#define __INCmvDramIfh ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++/* includes */ ++#include "ddr2/mvDramIfRegs.h" ++#include "ddr2/mvDramIfConfig.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++ ++/* defines */ ++/* DRAM Timing parameters */ ++#define SDRAM_TWR 15 /* ns tWr */ ++#define SDRAM_TRFC_64_512M_AT_200MHZ 70 /* ns tRfc for dens 64-512 @ 200MHz */ ++#define SDRAM_TRFC_64_512M 75 /* ns tRfc for dens 64-512 */ ++#define SDRAM_TRFC_1G 120 /* ns tRfc for dens 1GB */ ++#define SDRAM_TR2R_CYC 1 /* cycle for tR2r */ ++ ++#define CAL_AUTO_DETECT 0 /* Do not force CAS latancy (mvDramIfDetect) */ ++#define ECC_DISABLE 1 /* Force ECC to Disable */ ++#define ECC_ENABLE 0 /* Force ECC to ENABLE */ ++/* typedefs */ ++ ++/* enumeration for memory types */ ++typedef enum _mvMemoryType ++{ ++ MEM_TYPE_SDRAM, ++ MEM_TYPE_DDR1, ++ MEM_TYPE_DDR2 ++}MV_MEMORY_TYPE; ++ ++/* enumeration for DDR2 supported CAS Latencies */ ++typedef enum _mvDimmDdr2Cas ++{ ++ DDR2_CL_3 = 0x08, ++ DDR2_CL_4 = 0x10, ++ DDR2_CL_5 = 0x20, ++ DDR2_CL_6 = 0x40, ++ DDR2_CL_FAULT ++} MV_DIMM_DDR2_CAS; ++ ++ ++typedef struct _mvDramBankInfo ++{ ++ MV_MEMORY_TYPE memoryType; /* DDR1, DDR2 or SDRAM */ ++ ++ /* DIMM dimensions */ ++ MV_U32 numOfRowAddr; ++ MV_U32 numOfColAddr; ++ MV_U32 dataWidth; ++ MV_U32 errorCheckType; /* ECC , PARITY..*/ ++ MV_U32 sdramWidth; /* 4,8,16 or 32 */ ++ MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ ++ MV_U32 burstLengthSupported; ++ MV_U32 numOfBanksOnEachDevice; ++ MV_U32 suportedCasLatencies; ++ MV_U32 refreshInterval; ++ ++ /* DIMM timing parameters */ ++ MV_U32 minCycleTimeAtMaxCasLatPs; ++ MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; ++ MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; ++ MV_U32 minRowPrechargeTime; ++ MV_U32 minRowActiveToRowActive; ++ MV_U32 minRasToCasDelay; ++ MV_U32 minRasPulseWidth; ++ MV_U32 minWriteRecoveryTime; /* DDR2 only */ ++ MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ ++ MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ ++ MV_U32 minRefreshToActiveCmd; /* DDR2 only */ ++ ++ /* Parameters calculated from the extracted DIMM information */ ++ MV_U32 size; ++ MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit */ ++ MV_U32 numberOfDevices; ++ ++ /* DIMM attributes (MV_TRUE for yes) */ ++ MV_BOOL registeredAddrAndControlInputs; ++ MV_BOOL registeredDQMBinputs; ++ ++}MV_DRAM_BANK_INFO; ++ ++#include "ddr2/spd/mvSpd.h" ++ ++/* mvDramIf.h API list */ ++MV_VOID mvDramIfBasicAsmInit(MV_VOID); ++MV_STATUS mvDramIfDetect(MV_U32 forcedCl, MV_BOOL eccDisable); ++MV_VOID _mvDramIfConfig(int entryNum); ++ ++MV_U32 mvDramIfBankSizeGet(MV_U32 bankNum); ++MV_U32 mvDramIfBankBaseGet(MV_U32 bankNum); ++MV_U32 mvDramIfSizeGet(MV_VOID); ++MV_U32 mvDramIfCalGet(void); ++MV_STATUS mvDramIfSingleBitErrThresholdSet(MV_U32 threshold); ++MV_VOID mvDramIfSelfRefreshSet(void); ++void mvDramIfShow(void); ++MV_U32 mvDramIfGetFirstCS(void); ++MV_U32 mvDramIfGetCSorder(MV_U32 csOrder ); ++MV_U32 mvDramCsSizeGet(MV_U32 csNum); ++ ++#ifdef __cplusplus ++} ++#endif /* __cplusplus */ ++ ++#endif /* __INCmvDramIfh */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfBasicInit.S linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfBasicInit.S +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfBasicInit.S 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfBasicInit.S 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,986 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#define _ASMLANGUAGE ++#define MV_ASMLANGUAGE ++#include "mvSysHwConfig.h" ++#include "mvOsAsm.h" ++#include "boardEnv/mvBoardEnvSpec.h" ++#include "ctrlEnv/sys/mvCpuIfRegs.h" ++#include "mvDramIfConfig.h" ++#include "mvDramIfRegs.h" ++#include "pex/mvPexRegs.h" ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++#include "ctrlEnv/mvCtrlEnvAsm.h" ++#include "mvCommon.h" ++ ++/* defines */ ++ ++#if defined(MV_STATIC_DRAM_ON_BOARD) ++.globl dramBoot1 ++dramBoot1: ++ .word 0 ++ ++/****************************************************************************** ++* ++* ++* ++* ++*******************************************************************************/ ++#if defined(DB_MV78XX0) || defined(DB_MV88F632X) ++/* DDR2 boards 512MB 333MHz */ ++#define STATIC_SDRAM0_BANK0_SIZE 0x1ffffff1 /* 0x1504 */ ++#define STATIC_SDRAM_CONFIG 0x43048C30 /* 0x1400 */ ++#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */ ++#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */ ++#define STATIC_DUNIT_CTRL_HI 0x0000FFFF /* 0x1424 */ ++#define STATIC_SDRAM_ADDR_CTRL 0x00000088 /* 0x1410 */ ++#define STATIC_SDRAM_TIME_CTRL_LOW 0x22125441 /* 0x1408 */ ++#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A29 /* 0x140c */ ++#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */ ++#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ ++#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000E80F /* 0x149c */ ++#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */ ++#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ ++#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ ++ ++#elif defined(RD_MV78XX0_AMC) ++/* On board DDR2 512MB 400MHz CL5 */ ++#define STATIC_SDRAM0_BANK0_SIZE 0x1ffffff1 /* 0x1504 */ ++#define STATIC_SDRAM_CONFIG 0x43008C30 /* 0x1400 */ ++#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */ ++#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */ ++#define STATIC_DUNIT_CTRL_HI 0x0000F07F /* 0x1424 */ ++#define STATIC_SDRAM_ADDR_CTRL 0x000000DD /* 0x1410 */ ++#define STATIC_SDRAM_TIME_CTRL_LOW 0x23135441 /* 0x1408 */ ++#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A32 /* 0x140c */ ++#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */ ++#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ ++#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000EB0F /* 0x149c */ ++#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */ ++#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ ++#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ ++ ++#elif defined(RD_MV78XX0_H3C) ++/* DDR2 boards 512MB 333MHz */ ++#define STATIC_SDRAM0_BANK0_SIZE 0x1ffffff1 /* 0x1504 */ ++#define STATIC_SDRAM_CONFIG 0x43048a25 /* 0x1400 */ ++#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */ ++#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */ ++#define STATIC_DUNIT_CTRL_HI 0x0000F07F /* 0x1424 */ ++#define STATIC_SDRAM_ADDR_CTRL 0x00000088 /* 0x1410 */ ++#define STATIC_SDRAM_TIME_CTRL_LOW 0x2202444e /* 0x1408 */ ++#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A22 /* 0x140c */ ++#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */ ++#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ ++#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000EB0F /* 0x149c */ ++#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */ ++#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ ++#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ ++ ++#elif defined(RD_MV78XX0_PCAC) ++/* DDR2 boards 256MB 200MHz */ ++#define STATIC_SDRAM0_BANK0_SIZE 0x0ffffff1 /* 0x1504 */ ++#define STATIC_SDRAM_CONFIG 0x43000a25 /* 0x1400 */ ++#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */ ++#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */ ++#define STATIC_DUNIT_CTRL_HI 0x0000F07F /* 0x1424 */ ++#define STATIC_SDRAM_ADDR_CTRL 0x000000DD /* 0x1410 */ ++#define STATIC_SDRAM_TIME_CTRL_LOW 0x2202444e /* 0x1408 */ ++#define STATIC_SDRAM_TIME_CTRL_HI 0x00000822 /* 0x140c */ ++#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */ ++#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ ++#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000EB0F /* 0x149c */ ++#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */ ++#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ ++#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ ++ ++#else ++/* DDR2 MV88F6281 boards 256MB 400MHz */ ++#define STATIC_SDRAM0_BANK0_SIZE 0x0FFFFFF1 /* 0x1504 */ ++#define STATIC_SDRAM_CONFIG 0x43000c30 /* 0x1400 */ ++#define STATIC_SDRAM_MODE 0x00000C52 /* 0x141c */ ++#define STATIC_DUNIT_CTRL_LOW 0x39543000 /* 0x1404 */ ++#define STATIC_DUNIT_CTRL_HI 0x0000F1FF /* 0x1424 */ ++#define STATIC_SDRAM_ADDR_CTRL 0x000000cc /* 0x1410 */ ++#define STATIC_SDRAM_TIME_CTRL_LOW 0x22125451 /* 0x1408 */ ++#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A33 /* 0x140c */ ++#define STATIC_SDRAM_ODT_CTRL_LOW 0x003C0000 /* 0x1494 */ ++#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ ++#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000F80F /* 0x149c */ ++#define STATIC_SDRAM_EXT_MODE 0x00000042 /* 0x1420 */ ++#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ ++#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ ++#endif /* MV78XX0 */ ++ ++ .globl _mvDramIfStaticInit ++_mvDramIfStaticInit: ++ ++ mov r11, LR /* Save link register */ ++ mov r10, r2 ++ ++#ifdef MV78XX0 ++ MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) ++ orr r6, r6, #BIT4 /* Enable 2T mode */ ++ bic r6, r6, #BIT6 /* clear ctrlPos */ ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) ++#endif ++ ++ /*DDR SDRAM Initialization Control */ ++ ldr r6, =DSICR_INIT_EN ++ MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) ++2: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) ++ and r6, r6, #DSICR_INIT_EN ++ cmp r6, #0 ++ bne 2b ++ ++ /* If we boot from NAND jump to DRAM address */ ++ mov r5, #1 ++ ldr r6, =dramBoot1 ++ str r5, [r6] /* We started executing from DRAM */ ++ ++ ldr r6, dramBoot1 ++ cmp r6, #0 ++ bne 1f ++ ++ /* set all dram windows to 0 */ ++ mov r6, #0 ++ MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,0)) ++ MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,1)) ++ MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,2)) ++ MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,3)) ++ ldr r6, = STATIC_SDRAM0_BANK0_SIZE ++ MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,0)) ++ ++ ++ /* set all dram configuration in temp registers */ ++ ldr r6, = STATIC_SDRAM0_BANK0_SIZE ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG0) ++ ldr r6, = STATIC_SDRAM_CONFIG ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG1) ++ ldr r6, = STATIC_SDRAM_MODE ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG2) ++ ldr r6, = STATIC_DUNIT_CTRL_LOW ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG3) ++ ldr r6, = STATIC_SDRAM_ADDR_CTRL ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG4) ++ ldr r6, = STATIC_SDRAM_TIME_CTRL_LOW ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG5) ++ ldr r6, = STATIC_SDRAM_TIME_CTRL_HI ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG6) ++ ldr r6, = STATIC_SDRAM_ODT_CTRL_LOW ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG7) ++ ldr r6, = STATIC_SDRAM_ODT_CTRL_HI ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG8) ++ ldr r6, = STATIC_SDRAM_DUNIT_ODT_CTRL ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG9) ++ ldr r6, = STATIC_SDRAM_EXT_MODE ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG10) ++ ldr r6, = STATIC_SDRAM_DDR2_TIMING_LO ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG11) ++ ldr r6, = STATIC_SDRAM_DDR2_TIMING_HI ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG12) ++#ifndef MV_NAND_BOOT ++ ldr r6, = STATIC_DUNIT_CTRL_HI ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG13) ++#endif ++ ++ ldr sp,=0 ++ bl _mvDramIfConfig ++ ldr r0, =0 ++#ifdef MV78XX0 ++ bl _mvDramIfEccMemInit ++#endif ++1: ++ mov r2, r10 ++ mov PC, r11 /* r11 is saved link register */ ++ ++#else /* #if defined(MV_STATIC_DRAM_ON_BOARD) */ ++ ++.globl dramBoot1 ++dramBoot1: ++ .word 0 ++ ++/******************************************************************************* ++* mvDramIfBasicInit - Basic initialization of DRAM interface ++* ++* DESCRIPTION: ++* The function will initialize the DRAM for basic usage. The function ++* will use the TWSI assembly API to extract DIMM parameters according ++* to which DRAM interface will be initialized. ++* The function referes to the following DRAM parameters: ++* 1) DIMM is registered or not. ++* 2) DIMM width detection. ++* 3) DIMM density. ++* ++* INPUT: ++* r3 - required size for initial DRAM. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++* Note: ++* r4 holds I2C EEPROM address ++* r5 holds SDRAM register base address ++* r7 holds returned values ++* r8 holds SDRAM various configuration registers value. ++* r11 holds return function address. ++*******************************************************************************/ ++/* Setting the offsets of the I2C registers */ ++#define DIMM_TYPE_OFFSET 2 ++#define NUM_OF_ROWS_OFFSET 3 ++#define NUM_OF_COLS_OFFSET 4 ++#define NUM_OF_RANKS 5 ++#define DIMM_CONFIG_TYPE 11 ++#define SDRAM_WIDTH_OFFSET 13 ++#define NUM_OF_BANKS_OFFSET 17 ++#define SUPPORTED_CL_OFFSET 18 ++#define DIMM_TYPE_INFO_OFFSET 20 /* DDR2 only */ ++#define SDRAM_MODULES_ATTR_OFFSET 21 ++#define RANK_SIZE_OFFSET 31 ++ ++#define DRAM_DEV_DENSITY_128M 128 ++#define DRAM_DEV_DENSITY_256M 256 ++#define DRAM_DEV_DENSITY_512M 512 ++#define DRAM_DEV_DENSITY_1G 1024 ++#define DRAM_DEV_DENSITY_2G 2048 ++ ++#define DRAM_RANK_DENSITY_128M 0x20 ++#define DRAM_RANK_DENSITY_256M 0x40 ++#define DRAM_RANK_DENSITY_512M 0x80 ++#define DRAM_RANK_DENSITY_1G 0x1 ++#define DRAM_RANK_DENSITY_2G 0x2 ++ ++ .globl _mvDramIfBasicInit ++ .extern _i2cInit ++_mvDramIfBasicInit: ++ ++ mov r11, LR /* Save link register */ ++ ++ /* Set Dunit high control register */ ++ MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_HI_REG) ++ orr r6, r6, #BIT7 /* SDRAM__D2P_EN */ ++ orr r6, r6, #BIT8 /* SDRAM__P2D_EN */ ++#ifdef MV78XX0 ++ orr r6, r6, #BIT9 /* SDRAM__ADD_HALF_FCC_EN */ ++ orr r6, r6, #BIT10 /* SDRAM__PUP_ZERO_SKEW_EN */ ++ orr r6, r6, #BIT11 /* SDRAM__WR_MASH_DELAY_EN */ ++#endif ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_HI_REG) ++ ++#ifdef MV78XX0 ++ MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) ++ orr r6, r6, #BIT4 /* Enable 2T mode */ ++ bic r6, r6, #BIT6 /* clear ctrlPos */ ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) ++#endif ++ ++ /*DDR SDRAM Initialization Control */ ++ ldr r6, =DSICR_INIT_EN ++ MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) ++2: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) ++ and r6, r6, #DSICR_INIT_EN ++ cmp r6, #0 ++ bne 2b ++ ++ mov r5, #1 ++ ldr r8, =dramBoot1 ++ str r5, [r8] /* We started executing from DRAM */ ++ ++ /* If we boot from NAND jump to DRAM address */ ++ ldr r8, dramBoot1 ++ cmp r8, #0 ++ movne pc, r11 ++ ++ bl _i2cInit /* Initialize TWSI master */ ++ ++ /* Check if we have more then 1 dimm */ ++ ldr r6, =0 ++ MV_REG_WRITE_ASM (r6, r1, DRAM_BUF_REG14) ++#ifdef MV78XX0 ++ bl _is_Second_Dimm_Exist ++ beq single_dimm ++ ldr r6, =1 ++ MV_REG_WRITE_ASM (r6, r1, DRAM_BUF_REG14) ++single_dimm: ++ bl _i2cInit /* Initialize TWSI master */ ++#endif ++ ++ /* Get default SDRAM Config values */ ++ MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG) ++ ++ /* Get registered/non registered info from DIMM */ ++ bl _is_Registered ++ beq nonRegistered ++ ++setRegistered: ++ orr r8, r8, #SDRAM_REGISTERED /* Set registered bit(17) */ ++nonRegistered: ++#ifdef MV78XX0 ++ /* Get ECC/non ECC info from DIMM */ ++ bl _is_Ecc ++ beq setConfigReg ++ ++setEcc: ++ orr r8, r8, #SDRAM_ECC_EN /* Set ecc bit(18) */ ++#endif ++setConfigReg: ++ MV_REG_WRITE_ASM (r8, r5, DRAM_BUF_REG1) ++ ++ /* Set maximum CL supported by DIMM */ ++ bl _get_CAL ++ ++ /* r7 is DIMM supported CAS (e.g: 3 --> 0x1C) */ ++ clz r6, r7 ++ rsb r6, r6, #31 /* r6 = the bit number of MAX CAS supported */ ++ ++casDdr2: ++ ldr r7, =0x41 /* stBurstInDel|stBurstOutDel field value */ ++ ldr r3, =0x53 /* stBurstInDel|stBurstOutDel registered value*/ ++ ldr r8, =0x32 /* Assuming MAX CL = 3 */ ++ cmp r6, #3 /* If CL = 3 break */ ++ beq casDdr2Cont ++ ++ ldr r7, =0x53 /* stBurstInDel|stBurstOutDel field value */ ++ ldr r3, =0x65 /* stBurstInDel|stBurstOutDel registered value*/ ++ ldr r8, =0x42 /* Assuming MAX CL = 4 */ ++ cmp r6, #4 /* If CL = 4 break */ ++ beq casDdr2Cont ++ ++ ldr r7, =0x65 /* stBurstInDel|stBurstOutDel field value */ ++ ldr r3, =0x77 /* stBurstInDel|stBurstOutDel registered value*/ ++ ldr r8, =0x52 /* Assuming MAX CL = 5 */ ++ cmp r6, #5 /* If CL = 5 break */ ++ beq casDdr2Cont ++ ++ ldr r7, =0x77 /* stBurstInDel|stBurstOutDel field value */ ++ ldr r3, =0x89 /* stBurstInDel|stBurstOutDel registered value*/ ++ ldr r8, =0x62 /* Assuming MAX CL = 6 */ ++ cmp r6, #6 /* If CL = 5 break */ ++ beq casDdr2Cont ++ ++ /* This is an error. return */ ++ b exit_ddrAutoConfig /* This is an error !! */ ++casDdr2Cont: ++ ++ /* Get default SDRAM Mode values */ ++ MV_REG_READ_ASM (r6, r5, SDRAM_MODE_REG) ++ bic r6, r6, #(BIT6 | BIT5 | BIT4) /* Clear CL filed */ ++ orr r6, r6, r8 ++ MV_REG_WRITE_ASM (r6, r5, DRAM_BUF_REG2) ++ ++ /* Set Dunit control register according to max CL detected */ ++ MV_REG_READ_ASM (r6, r5, DRAM_BUF_REG1) ++ tst r6, #SDRAM_REGISTERED ++ beq setDunitReg ++ mov r7, r3 ++ ++setDunitReg: ++#ifdef MV78XX0 ++ /* Set SDRAM Extended Mode register for double DIMM */ ++ /* Check DRAM frequency for more then 267MHz set ODT Rtt to 50ohm */ ++ ++ MV_REG_READ_ASM (r4, r5, CPU_RESET_SAMPLE_L_REG) ++ ldr r5, =MSAR_SYSCLCK_MASK ++ and r4, r4, r5 ++ ldr r5, =MSAR_SYSCLCK_333 ++ cmp r4, r5 ++ ble Clock333 ++ add r7, r7, #0x10 ++Clock333: ++#endif ++ ++ MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) ++ bic r6, r6, #(0xff << 20) /* Clear SBout and SBin */ ++ orr r6, r6, #BIT4 /* Enable 2T mode */ ++ bic r6, r6, #BIT6 /* clear ctrlPos */ ++ orr r6, r6, r7, LSL #20 ++ MV_REG_WRITE_ASM (r6, r5, DRAM_BUF_REG3) ++ ++ /* Set Dunit high control register */ ++ MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_HI_REG) ++ orr r6, r6, #BIT7 /* SDRAM__D2P_EN */ ++ orr r6, r6, #BIT8 /* SDRAM__P2D_EN */ ++#ifdef MV78XX0 ++ orr r6, r6, #BIT9 /* SDRAM__ADD_HALF_FCC_EN */ ++ orr r6, r6, #BIT10 /* SDRAM__PUP_ZERO_SKEW_EN */ ++ orr r6, r6, #BIT11 /* SDRAM__WR_MASH_DELAY_EN */ ++#endif ++ MV_REG_WRITE_ASM (r6, r5, DRAM_BUF_REG13) ++ ++ /* DIMM density configuration*/ ++ /* Density = (1 << (rowNum + colNum)) * dramWidth * dramBankNum */ ++Density: ++ /* Get bank 0 and 1 density */ ++ ldr r6, =0 ++ bl _getDensity ++ ++ mov r8, r7 ++ mov r8, r8, LSR #20 /* Move density 20 bits to the right */ ++ /* For example 0x10000000 --> 0x1000 */ ++ ++ mov r3, #(SDRAM_DSIZE_256Mb(0) | SDRAM_DSIZE_256Mb(1)) ++ cmp r8, #DRAM_DEV_DENSITY_256M ++ beq get_bank_2_density ++ ++ mov r3, #(SDRAM_DSIZE_512Mb(0) | SDRAM_DSIZE_512Mb(1)) ++ cmp r8, #DRAM_DEV_DENSITY_512M ++ beq get_bank_2_density ++ ++ mov r3, #(SDRAM_DSIZE_1Gb(0) | SDRAM_DSIZE_1Gb(1)) ++ cmp r8, #DRAM_DEV_DENSITY_1G ++ beq get_bank_2_density ++ ++ mov r3, #(SDRAM_DSIZE_2Gb(0) | SDRAM_DSIZE_2Gb(1)) ++ cmp r8, #DRAM_DEV_DENSITY_2G ++ beq get_bank_2_density ++ ++ /* This is an error. return */ ++ b exit_ddrAutoConfig ++ ++get_bank_2_density: ++ /* Check for second dimm */ ++ MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14) ++ cmp r6, #1 ++ bne get_width ++ ++ /* Get bank 2 and 3 density */ ++ ldr r6, =2 ++ bl _getDensity ++ ++ mov r8, r7 ++ mov r8, r8, LSR #20 /* Move density 20 bits to the right */ ++ /* For example 0x10000000 --> 0x1000 */ ++ ++ orr r3, r3, #(SDRAM_DSIZE_256Mb(2) | SDRAM_DSIZE_256Mb(3)) ++ cmp r8, #DRAM_DEV_DENSITY_256M ++ beq get_width ++ ++ and r3, r3, #~(SDRAM_DSIZE_MASK(2) | SDRAM_DSIZE_MASK(3)) ++ orr r3, r3, #(SDRAM_DSIZE_512Mb(2) | SDRAM_DSIZE_512Mb(3)) ++ cmp r8, #DRAM_DEV_DENSITY_512M ++ beq get_width ++ ++ and r3, r3, #~(SDRAM_DSIZE_MASK(2) | SDRAM_DSIZE_MASK(3)) ++ orr r3, r3, #(SDRAM_DSIZE_1Gb(2) | SDRAM_DSIZE_1Gb(3)) ++ cmp r8, #DRAM_DEV_DENSITY_1G ++ beq get_width ++ ++ and r3, r3, #~(SDRAM_DSIZE_MASK(2) | SDRAM_DSIZE_MASK(3)) ++ orr r3, r3, #(SDRAM_DSIZE_2Gb(2) | SDRAM_DSIZE_2Gb(3)) ++ cmp r8, #DRAM_DEV_DENSITY_2G ++ beq get_width ++ ++ /* This is an error. return */ ++ b exit_ddrAutoConfig ++ ++ /* Get SDRAM width */ ++get_width: ++ /* Get bank 0 and 1 width */ ++ ldr r6, =0 ++ bl _get_width ++ ++ cmp r7, #8 /* x8 devices */ ++ beq get_bank_2_width ++ ++ orr r3, r3, #(SDRAM_ADDRSEL_X16(0) | SDRAM_ADDRSEL_X16(1)) /* x16 devices */ ++ cmp r7, #16 ++ beq get_bank_2_width ++ ++ /* This is an error. return */ ++ b exit_ddrAutoConfig ++ ++get_bank_2_width: ++ /* Check for second dimm */ ++ MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14) ++ cmp r6, #1 ++ bne densCont ++ ++ /* Get bank 2 and 3 width */ ++ ldr r6, =2 ++ bl _get_width ++ ++ cmp r7, #8 /* x8 devices */ ++ beq densCont ++ ++ orr r3, r3, #(SDRAM_ADDRSEL_X16(2) | SDRAM_ADDRSEL_X16(3)) /* x16 devices */ ++ cmp r7, #16 ++ beq densCont ++ ++ /* This is an error. return */ ++ b exit_ddrAutoConfig ++ ++densCont: ++ MV_REG_WRITE_ASM (r3, r5, DRAM_BUF_REG4) ++ ++ /* Set SDRAM timing control low register */ ++ ldr r4, =SDRAM_TIMING_CTRL_LOW_REG_DEFAULT ++ /* MV_REG_READ_ASM (r4, r5, SDRAM_TIMING_CTRL_LOW_REG) */ ++ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG5) ++ ++ /* Set SDRAM timing control high register */ ++ ldr r6, =SDRAM_TIMING_CTRL_HIGH_REG_DEFAULT ++ ++ MV_REG_READ_ASM (r4, r5, CPU_RESET_SAMPLE_L_REG) ++ ldr r5, =MSAR_SYSCLCK_MASK ++ and r4, r4, r5 ++ ldr r5, =MSAR_SYSCLCK_333 ++ cmp r4, r5 ++ blt timingHighClock333 ++ orr r6, r6, #BIT9 ++ ++timingHighClock333: ++ /* MV_REG_READ_ASM (r6, r5, SDRAM_TIMING_CTRL_HIGH_REG) */ ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG6) ++ ++ /* Check for second dimm */ ++ MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14) ++ cmp r6, #1 ++ bne single_dimm_odt ++ ++ /* Set SDRAM ODT control low register for double DIMM*/ ++ ldr r4, =DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV ++ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG7) ++ ++ /* Set DUNIT ODT control register for double DIMM */ ++ ldr r4, =DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV ++ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG9) ++ ++#ifdef MV78XX0 ++ /* Set SDRAM Extended Mode register for double DIMM */ ++ /* Check DRAM frequency for more then 267MHz set ODT Rtt to 50ohm */ ++ ++ MV_REG_READ_ASM (r4, r5, CPU_RESET_SAMPLE_L_REG) ++ ldr r5, =MSAR_SYSCLCK_MASK ++ and r4, r4, r5 ++ ldr r5, =MSAR_SYSCLCK_267 ++ cmp r4, r5 ++ beq slow_dram_clock_rtt ++ ldr r5, =MSAR_SYSCLCK_300 ++ cmp r4, r5 ++ beq slow_dram_clock_rtt ++ ldr r5, =MSAR_SYSCLCK_333 ++ cmp r4, r5 ++ beq fast_dram_clock_rtt ++ ldr r5, =MSAR_SYSCLCK_400 ++ cmp r4, r5 ++ beq fast_dram_clock_rtt ++ ++ b slow_dram_clock_rtt ++ ++fast_dram_clock_rtt: ++ ldr r4, =DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV ++ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG10) ++ b odt_config_end ++#endif ++slow_dram_clock_rtt: ++ ldr r4, =DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV ++ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG10) ++ b odt_config_end ++ ++single_dimm_odt: ++ /* Set SDRAM ODT control low register */ ++ ldr r4, =DDR2_ODT_CTRL_LOW_CS0_CS1_DV ++ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG7) ++ ++ /* Set DUNIT ODT control register */ ++ ldr r4, =DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV ++ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG9) ++ ++ /* Set SDRAM Extended Mode register */ ++ ldr r4, =DDR_SDRAM_EXT_MODE_CS0_CS1_DV ++ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG10) ++ ++odt_config_end: ++ /* SDRAM ODT control high register is left as default */ ++ MV_REG_READ_ASM (r4, r5, DDR2_SDRAM_ODT_CTRL_HIGH_REG) ++ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG8) ++ ++ /*Read CL and set the DDR2 registers accordingly */ ++ MV_REG_READ_ASM (r6, r5, DRAM_BUF_REG2) ++ and r6, r6, #SDRAM_CL_MASK ++ mov r4, r6 ++ orr r4, r4, r6, LSL #4 ++ orr r4, r4, r6, LSL #8 ++ orr r4, r4, r6, LSL #12 ++ mov r5, #0x30000 ++ add r4, r4, r5 ++ sub r4, r4, #0x30 ++ /* Set SDRAM Ddr2 Timing Low register */ ++ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG11) ++ ++ /* Set SDRAM Ddr2 Timing High register */ ++ mov r4, r4, LSR #4 ++ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG12) ++ ++timeParamDone: ++ /* Close all windows */ ++ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) ++ and r6, r6,#~SCSR_SIZE_MASK ++ and r6, r6,#~1 ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) ++ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,1)) ++ and r6, r6,#~SCSR_SIZE_MASK ++ and r6, r6,#~1 ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,1)) ++ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) ++ and r6, r6,#~SCSR_SIZE_MASK ++ and r6, r6,#~1 ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) ++ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,3)) ++ and r6, r6,#~SCSR_SIZE_MASK ++ and r6, r6,#~1 ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,3)) ++ ++ /* Set sdram bank 0 size and enable it */ ++ ldr r6, =0 ++ bl _mvDramIfGetDimmSizeFromSpd ++#ifdef MV78XX0 ++ /* Check DRAM width */ ++ MV_REG_READ_ASM (r4, r5, SDRAM_CONFIG_REG) ++ ldr r5, =SDRAM_DWIDTH_MASK ++ and r4, r4, r5 ++ ldr r5, =SDRAM_DWIDTH_64BIT ++ cmp r4, r5 ++ beq dram_64bit_width ++ /* Utilize only 32bit width */ ++ mov r8, r8, LSR #1 ++#else ++ /* Utilize only 16bit width */ ++ mov r8, r8, LSR #2 ++#endif ++dram_64bit_width: ++ /* Update first dimm size return value R8 */ ++ MV_REG_READ_ASM (r5, r6, SDRAM_SIZE_REG(0,0)) ++ ldr r6, =~SCSR_SIZE_MASK ++ and r5, r5, r6 ++ orr r5, r5, r8 ++ MV_REG_WRITE_ASM(r5, r8, SDRAM_SIZE_REG(0,0)) ++ ++ /* Clear bank 2 size */ ++ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) ++ and r6, r6,#~SCSR_SIZE_MASK ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) ++ ++ /* Check for second dimm */ ++ MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14) ++ cmp r6, #1 ++ bne defualt_order ++ ++ /* Set sdram bank 2 size */ ++ ldr r6, =2 ++ bl _mvDramIfGetDimmSizeFromSpd ++#ifdef MV78XX0 ++ /* Check DRAM width */ ++ MV_REG_READ_ASM (r4, r5, SDRAM_CONFIG_REG) ++ ldr r5, =SDRAM_DWIDTH_MASK ++ and r4, r4, r5 ++ ldr r5, =SDRAM_DWIDTH_64BIT ++ cmp r4, r5 ++ beq dram_64bit_width2 ++ /* Utilize only 32bit width */ ++ mov r8, r8, LSR #1 ++#else ++ /* Utilize only 16bit width */ ++ mov r8, r8, LSR #2 ++#endif ++dram_64bit_width2: ++ /* Update first dimm size return value R8 */ ++ MV_REG_READ_ASM (r5, r6, SDRAM_SIZE_REG(0,2)) ++ ldr r6, =~SCSR_SIZE_MASK ++ and r5, r5, r6 ++ orr r5, r5, r8 ++ MV_REG_WRITE_ASM(r5, r8, SDRAM_SIZE_REG(0,2)) ++ ++ /* Close windows 1 and 3 */ ++ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,1)) ++ and r6, r6,#~1 ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,1)) ++ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,3)) ++ and r6, r6,#~1 ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,3)) ++ ++ /* Check dimm size for setting dram bank order */ ++ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) ++ MV_REG_READ_ASM (r4, r5, SDRAM_SIZE_REG(0,2)) ++ and r6, r6,#SCSR_SIZE_MASK ++ and r4, r4,#SCSR_SIZE_MASK ++ cmp r6, r4 ++ bge defualt_order ++ ++ /* Bank 2 is biger then bank 0 */ ++ ldr r6,=0 ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_BASE_ADDR_REG(0,2)) ++ ++ /* Open win 2 */ ++ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) ++ orr r6, r6,#1 ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) ++ ++ ldr sp,=0 ++ bl _mvDramIfConfig ++#ifdef MV78XX0 ++ /* Init ECC on CS 2 */ ++ ldr r0, =2 ++ bl _mvDramIfEccMemInit ++#endif ++ mov PC, r11 /* r11 is saved link register */ ++ ++defualt_order: ++ ++ /* Open win 0 */ ++ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) ++ orr r6, r6,#1 ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) ++ ++ ldr sp,=0 ++ bl _mvDramIfConfig ++#ifdef MV78XX0 ++ /* Init ECC on CS 0 */ ++ ldr r0, =0 ++ bl _mvDramIfEccMemInit ++#endif ++exit_ddrAutoConfig: ++ mov PC, r11 /* r11 is saved link register */ ++ ++ ++/***************************************************************************************/ ++/* r4 holds I2C EEPROM address ++ * r7 holds I2C EEPROM offset parameter for i2cRead and its --> returned value ++ * r8 holds SDRAM various configuration registers value. ++ * r13 holds Link register ++ */ ++/**************************/ ++_getDensity: ++ mov r13, LR /* Save link register */ ++ ++ /* Read SPD rank size from DIMM0 */ ++ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ ++ ++ cmp r6, #0 ++ beq 1f ++ ++ /* Read SPD rank size from DIMM1 */ ++ mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM1 */ ++ ++1: ++ mov r7, #NUM_OF_ROWS_OFFSET /* offset 3 */ ++ bl _i2cRead ++ mov r8, r7 /* r8 save number of rows */ ++ ++ mov r7, #NUM_OF_COLS_OFFSET /* offset 4 */ ++ bl _i2cRead ++ add r8, r8, r7 /* r8 = number of rows + number of col */ ++ ++ mov r7, #0x1 ++ mov r8, r7, LSL r8 /* r8 = (1 << r8) */ ++ ++ mov r7, #SDRAM_WIDTH_OFFSET /* offset 13 */ ++ bl _i2cRead ++ mul r8, r7, r8 ++ ++ mov r7, #NUM_OF_BANKS_OFFSET /* offset 17 */ ++ bl _i2cRead ++ mul r7, r8, r7 ++ ++ mov PC, r13 ++ ++/**************************/ ++_get_width: ++ mov r13, LR /* Save link register */ ++ ++ /* Read SPD rank size from DIMM0 */ ++ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ ++ ++ cmp r6, #0 ++ beq 1f ++ ++ /* Read SPD rank size from DIMM1 */ ++ mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM1 */ ++ ++1: ++ /* Get SDRAM width (SPD offset 13) */ ++ mov r7, #SDRAM_WIDTH_OFFSET ++ bl _i2cRead /* result in r7 */ ++ ++ mov PC, r13 ++ ++/**************************/ ++_get_CAL: ++ mov r13, LR /* Save link register */ ++ ++ /* Set maximum CL supported by DIMM */ ++ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ ++ mov r7, #SUPPORTED_CL_OFFSET /* offset 18 */ ++ bl _i2cRead ++ ++ mov PC, r13 ++ ++/**************************/ ++/* R8 - sdram configuration register. ++ * Return value in flag if no-registered then Z-flag is set ++ */ ++_is_Registered: ++ mov r13, LR /* Save link register */ ++#if defined(MV645xx) ++ /* Get registered/non registered info from DIMM */ ++ tst r8, #SDRAM_DTYPE_DDR2 ++ bne regDdr2 ++ ++regDdr1: ++ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ ++ mov r7, #SDRAM_MODULES_ATTR_OFFSET ++ bl _i2cRead /* result in r7 */ ++ ++ tst r7, #0x2 ++ b exit ++#endif ++regDdr2: ++ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ ++ mov r7, #DIMM_TYPE_INFO_OFFSET ++ bl _i2cRead /* result in r7 */ ++ ++ tst r7, #0x11 /* DIMM type = regular RDIMM (0x01) */ ++ /* or Mini-RDIMM (0x10) */ ++exit: ++ mov PC, r13 ++ ++ ++/**************************/ ++/* Return value in flag if no-Ecc then Z-flag is set */ ++_is_Ecc: ++ mov r13, LR /* Save link register */ ++ ++ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ ++ mov r7, #DIMM_CONFIG_TYPE ++ bl _i2cRead /* result in r7 */ ++ ++ tst r7, #0x2 /* bit 1 -> Data ECC */ ++ mov PC, r13 ++ ++/**************************/ ++/* Return value in flag if no second DIMM then Z-flag is set */ ++_is_Second_Dimm_Exist: ++ mov r13, LR /* Save link register */ ++ ++ mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM0 */ ++ mov r7, #DIMM_TYPE_OFFSET ++ bl _i2cRead /* result in r7 */ ++ ++ tst r7, #0x8 /* bit3 is '1' -> DDR 2 */ ++ mov PC, r13 ++ ++/******************************************************************************* ++* _mvDramIfGetDimmSizeFromSpd - read bank 0 dram's size ++* ++* DESCRIPTION: ++* The function will read the bank 0 dram size(SPD version 1.0 and above ) ++* ++* INPUT: ++* r6 - dram bank number. ++* ++* OUTPUT: ++* none ++*/ ++_mvDramIfGetDimmSizeFromSpd: ++ ++ mov r13, LR /* Save link register */ ++ ++ /* Read SPD rank size from DIMM0 */ ++ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ ++ ++ cmp r6, #0 ++ beq 1f ++ ++ /* Read SPD rank size from DIMM1 */ ++ mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM1 */ ++ ++1: ++ mov r7, #RANK_SIZE_OFFSET /* offset 31 */ ++ bl _i2cRead ++ ++pass_read: ++ ldr r8, =(0x7 << SCSR_SIZE_OFFS) ++ cmp r7, #DRAM_RANK_DENSITY_128M ++ beq endDimmSize ++ ++ ldr r8, =(0xf << SCSR_SIZE_OFFS) ++ cmp r7, #DRAM_RANK_DENSITY_256M ++ beq endDimmSize ++ ++ ldr r8, =(0x1f << SCSR_SIZE_OFFS) ++ cmp r7, #DRAM_RANK_DENSITY_512M ++ beq endDimmSize ++ ++ ldr r8, =(0x3f << SCSR_SIZE_OFFS) ++ cmp r7, #DRAM_RANK_DENSITY_1G ++ beq endDimmSize ++ ++ ldr r8, =(0x7f << SCSR_SIZE_OFFS) /* DRAM_RANK_DENSITY_2G */ ++endDimmSize: ++ mov PC, r13 ++#endif +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.S linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.S +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.S 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.S 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,528 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++/******************************************************************************* ++* mvDramIfBasicAsm.s ++* ++* DESCRIPTION: ++* Memory full detection and best timing configuration is done in ++* C code. C runtime environment requires a stack. This module API ++* initialize DRAM interface chip select 0 for basic functionality for ++* the use of stack. ++* The module API assumes DRAM information is stored in I2C EEPROM reside ++* in a given I2C address MV_BOARD_DIMM0_I2C_ADDR. The I2C EEPROM ++* internal data structure is assumed to be orgenzied in common DRAM ++* vendor SPD structure. ++* NOTE: DFCDL values are assumed to be already initialized prior to ++* this module API activity. ++* ++* ++* DEPENDENCIES: ++* None. ++* ++*******************************************************************************/ ++ ++/* includes */ ++#define _ASMLANGUAGE ++#define MV_ASMLANGUAGE ++#include "mvOsAsm.h" ++#include "mvSysHwConfig.h" ++#include "mvDramIfRegs.h" ++#include "mvDramIfConfig.h" ++#include "ctrlEnv/sys/mvCpuIfRegs.h" ++#include "pex/mvPexRegs.h" ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++#include "mvCommon.h" ++ ++/* defines */ ++ ++/* locals */ ++.data ++.globl _mvDramIfConfig ++.text ++.globl _mvDramIfMemInit ++ ++/******************************************************************************* ++* _mvDramIfConfig - Basic DRAM interface initialization. ++* ++* DESCRIPTION: ++* The function will initialize the following DRAM parameters using the ++* values prepared by mvDramIfDetect routine. Values are located ++* in predefined registers. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++ ++_mvDramIfConfig: ++ ++ /* Save register on stack */ ++ cmp sp, #0 ++ beq no_stack_s ++save_on_stack: ++ stmdb sp!, {r1, r2, r3, r4} ++no_stack_s: ++ ++ /* Dunit FTDLL Configuration Register */ ++ /* 0) Write to SDRAM FTDLL coniguration register */ ++ ldr r4, = SDRAM_FTDLL_REG_DEFAULT_LEFT; ++ ldr r1, =(INTER_REGS_BASE + SDRAM_FTDLL_CONFIG_LEFT_REG) ++ str r4, [r1] ++ ldr r4, = SDRAM_FTDLL_REG_DEFAULT_RIGHT; ++ ldr r1, =(INTER_REGS_BASE + SDRAM_FTDLL_CONFIG_RIGHT_REG) ++ str r4, [r1] ++ ldr r4, = SDRAM_FTDLL_REG_DEFAULT_UP; ++ ldr r1, =(INTER_REGS_BASE + SDRAM_FTDLL_CONFIG_UP_REG) ++ str r4, [r1] ++ ++ /* 1) Write to SDRAM coniguration register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG1) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_CONFIG_REG) ++ str r4, [r1] ++ ++ /* 2) Write Dunit control low register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG3) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_DUNIT_CTRL_REG) ++ str r4, [r1] ++ ++ /* 2) Write Dunit control high register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG13) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_DUNIT_CTRL_HI_REG) ++ str r4, [r1] ++ ++ /* 3) Write SDRAM address control register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG4) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_ADDR_CTRL_REG) ++ str r4, [r1] ++#if defined(MV_STATIC_DRAM_ON_BOARD) ++ /* 4) Write SDRAM bank 0 size register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG0) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_SIZE_REG(0,0)) ++ str r4, [r1] ++#endif ++ ++ /* 5) Write SDRAM open pages control register */ ++ ldr r1, =(INTER_REGS_BASE + SDRAM_OPEN_PAGE_CTRL_REG) ++ ldr r4, =SDRAM_OPEN_PAGES_CTRL_REG_DV ++ str r4, [r1] ++ ++ /* 6) Write SDRAM timing Low register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG5) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_LOW_REG) ++ str r4, [r1] ++ ++ /* 7) Write SDRAM timing High register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG6) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_HIGH_REG) ++ str r4, [r1] ++ ++ /* Config DDR2 On Die Termination (ODT) registers */ ++ /* Write SDRAM DDR2 ODT control low register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG7) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_LOW_REG) ++ str r4, [r1] ++ ++ /* Write SDRAM DDR2 ODT control high register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG8) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_HIGH_REG) ++ str r4, [r1] ++ ++ /* Write SDRAM DDR2 Dunit ODT control register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG9) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + DDR2_DUNIT_ODT_CONTROL_REG) ++ str r4, [r1] ++ ++ /* Write DDR2 SDRAM timing Low register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG11) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_DDR2_TIMING_LO_REG) ++ str r4, [r1] ++ ++ /* Write DDR2 SDRAM timing High register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG12) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_DDR2_TIMING_HI_REG) ++ str r4, [r1] ++ ++ /* 8) Write SDRAM mode register */ ++ /* The CPU must not attempt to change the SDRAM Mode register setting */ ++ /* prior to DRAM controller completion of the DRAM initialization */ ++ /* sequence. To guarantee this restriction, it is recommended that */ ++ /* the CPU sets the SDRAM Operation register to NOP command, performs */ ++ /* read polling until the register is back in Normal operation value, */ ++ /* and then sets SDRAM Mode register to its new value. */ ++ ++ /* 8.1 write 'nop' to SDRAM operation */ ++ mov r4, #0x5 /* 'NOP' command */ ++ MV_REG_WRITE_ASM(r4, r1, SDRAM_OPERATION_REG) ++ ++ /* 8.2 poll SDRAM operation. Make sure its back to normal operation */ ++_sdramOpPoll1: ++ ldr r4, [r1] ++ cmp r4, #0 /* '0' = Normal SDRAM Mode */ ++ bne _sdramOpPoll1 ++ ++ /* 8.3 Now its safe to write new value to SDRAM Mode register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG2) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_MODE_REG) ++ str r4, [r1] ++ ++ /* 8.4 Make the Dunit write the DRAM its new mode */ ++ mov r4, #0x3 /* Mode Register Set command */ ++ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) ++ ++ /* 8.5 poll SDRAM operation. Make sure its back to normal operation */ ++_sdramOpPoll2: ++ ldr r4, [r1] ++ cmp r4, #0 /* '0' = Normal SDRAM Mode */ ++ bne _sdramOpPoll2 ++ ++ /* Now its safe to write new value to SDRAM Extended Mode regist */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG10) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_EXTENDED_MODE_REG) ++ str r4, [r1] ++ ++ /* 9) Write SDRAM Extended mode register This operation should be */ ++ /* done for each memory bank */ ++ /* write 'nop' to SDRAM operation */ ++ mov r4, #0x5 /* 'NOP' command */ ++ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) ++ ++ /* poll SDRAM operation. Make sure its back to normal operation */ ++_sdramOpPoll3: ++ ldr r4, [r1] ++ cmp r4, #0 /* '0' = Normal SDRAM Mode */ ++ bne _sdramOpPoll3 ++ /* Go over each of the Banks */ ++ ldr r3, =0 /* r3 = DRAM bank Num */ ++ ++extModeLoop: ++ /* Set the SDRAM Operation Control to each of the DRAM banks */ ++ mov r4, r3 /* Do not swap the bank counter value */ ++ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_CTRL_REG) ++ ++ /* Make the Dunit write the DRAM its new mode */ ++ mov r4, #0x4 /* Extended Mode Register Set command */ ++ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) ++ ++ /* poll SDRAM operation. Make sure its back to normal operation */ ++_sdramOpPoll4: ++ ldr r4, [r1] ++ cmp r4, #0 /* '0' = Normal SDRAM Mode */ ++ bne _sdramOpPoll4 ++ ++ add r3, r3, #1 ++ cmp r3, #4 /* 4 = Number of banks */ ++ bne extModeLoop ++ ++extModeEnd: ++cmp sp, #0 ++ beq no_stack_l ++ mov r1, LR /* Save link register */ ++#if defined(MV78XX0) ++ bl _mvDramIfMemInit ++#endif ++ mov LR,r1 /* restore link register */ ++load_from_stack: ++ /* Restore registers */ ++ ldmia sp!, {r1, r2, r3, r4} ++no_stack_l: ++ ++ mov pc, lr ++ ++ ++/******************************************************************************* ++* _mvDramIfEccMemInit - Basic DRAM ECC initialization. ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++#define XOR_CHAN0 0 /* XOR channel 0 used for memory initialization */ ++#define XOR_UNIT0 0 /* XOR unit 0 used for memory initialization */ ++#define XOR_ADDR_DEC_WIN0 0 /* Enable DRAM access using XOR decode window 0 */ ++/* XOR engine register offsets macros */ ++#define XOR_CONFIG_REG(chan) (XOR_UNIT_BASE(0) + 0x10 + ((chan) * 4)) ++#define XOR_ACTIVATION_REG(chan) (XOR_UNIT_BASE(0) + 0x20 + ((chan) * 4)) ++#define XOR_CAUSE_REG (XOR_UNIT_BASE(0) + 0x30) ++#define XOR_ERROR_CAUSE_REG (XOR_UNIT_BASE(0) + 0x50) ++#define XOR_ERROR_ADDR_REG (XOR_UNIT_BASE(0) + 0x60) ++#define XOR_INIT_VAL_LOW_REG (XOR_UNIT_BASE(0) + 0x2E0) ++#define XOR_INIT_VAL_HIGH_REG (XOR_UNIT_BASE(0) + 0x2E4) ++#define XOR_DST_PTR_REG(chan) (XOR_UNIT_BASE(0) + 0x2B0 + ((chan) * 4)) ++#define XOR_BLOCK_SIZE_REG(chan) (XOR_UNIT_BASE(0) + 0x2C0 + ((chan) * 4)) ++ ++/* XOR Engine Address Decoding Register Map */ ++#define XOR_WINDOW_CTRL_REG(unit,chan) (XOR_UNIT_BASE(unit)+(0x240 + ((chan) * 4))) ++#define XOR_BASE_ADDR_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x250 + ((winNum) * 4))) ++#define XOR_SIZE_MASK_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x270 + ((winNum) * 4))) ++ ++.globl _mvDramIfEccMemInit ++/******************************************************************************* ++* _mvDramIfEccMemInit - mem init for dram cs ++* ++* DESCRIPTION: ++* This function will clean the cs by ussing the XOR mem init. ++* ++* INPUT: ++* r0 - dram bank number. ++* ++* OUTPUT: ++* none ++*/ ++_mvDramIfEccMemInit: ++ ++ /* Save register on stack */ ++ cmp sp, #0 ++ beq no_stack_s1 ++save_on_stack1: ++ stmdb sp!, {r0,r1, r2, r3, r4, r5, r6} ++no_stack_s1: ++ ++ ldr r1, = 0 ++ ++ /* Disable all XOR address decode windows to avoid possible overlap */ ++ MV_REG_WRITE_ASM (r1, r5, (XOR_WINDOW_CTRL_REG(XOR_UNIT0,XOR_CHAN0))) ++ ++ /* Init r5 to first XOR_SIZE_MASK_REG */ ++ mov r5, r0, LSL #3 ++ add r5, r5,#0x1500 ++ add r5, r5,#0x04 ++ add r5, r5,#(INTER_REGS_BASE) ++ ldr r6, [r5] ++ HTOLL(r6,r5) ++ MV_REG_WRITE_ASM (r6, r5, XOR_SIZE_MASK_REG(XOR_UNIT0,XOR_ADDR_DEC_WIN0)) ++ ++ mov r5, r0, LSL #3 ++ add r5, r5,#0x1500 ++ add r5, r5,#(INTER_REGS_BASE) ++ ldr r6, [r5] ++ /* Update destination & size */ ++ MV_REG_WRITE_ASM(r6, r5, XOR_DST_PTR_REG(XOR_CHAN0)) ++ HTOLL(r6,r5) ++ /* Init r6 to first XOR_BASE_ADDR_REG */ ++ ldr r4, = 0xf ++ ldr r5, = 0x1 ++ mov r5, r5, LSL r0 ++ bic r4, r4, r5 ++ mov r4, r4, LSL #8 ++ ++ orr r6, r6, r4 ++ MV_REG_WRITE_ASM (r6, r5, XOR_BASE_ADDR_REG(XOR_UNIT0,XOR_ADDR_DEC_WIN0)) ++ ++ ldr r6, = 0xff0001 ++ MV_REG_WRITE_ASM (r6, r5, XOR_WINDOW_CTRL_REG(XOR_UNIT0,XOR_CHAN0)) ++ ++ /* Configure XOR engine for memory init function. */ ++ MV_REG_READ_ASM (r6, r5, XOR_CONFIG_REG(XOR_CHAN0)) ++ and r6, r6, #~0x7 /* Clear operation mode field */ ++ orr r6, r6, #0x4 /* Set operation to memory init */ ++ MV_REG_WRITE_ASM(r6, r5, XOR_CONFIG_REG(XOR_CHAN0)) ++ ++ /* Set initVal in the XOR Engine Initial Value Registers */ ++ ldr r6, = 0xfeedfeed ++ MV_REG_WRITE_ASM(r6, r5, XOR_INIT_VAL_LOW_REG) ++ ldr r6, = 0xfeedfeed ++ MV_REG_WRITE_ASM(r6, r5, XOR_INIT_VAL_HIGH_REG) ++ ++ /* Set block size using DRAM bank size */ ++ ++ mov r5, r0, LSL #3 ++ add r5, r5,#0x1500 ++ add r5, r5,#0x04 ++ add r5, r5,#(INTER_REGS_BASE) ++ ++ ldr r6, [r5] ++ HTOLL(r6,r5) ++ and r6, r6, #SCSR_SIZE_MASK ++ mov r5, r6, LSR #SCSR_SIZE_OFFS ++ add r5, r5, #1 ++ mov r6, r5, LSL #SCSR_SIZE_OFFS ++ MV_REG_WRITE_ASM(r6, r5, XOR_BLOCK_SIZE_REG(XOR_CHAN0)) ++ ++ /* Clean interrupt cause*/ ++ MV_REG_WRITE_ASM(r1, r5, XOR_CAUSE_REG) ++ ++ /* Clean error interrupt cause*/ ++ MV_REG_READ_ASM(r6, r5, XOR_ERROR_CAUSE_REG) ++ MV_REG_READ_ASM(r6, r5, XOR_ERROR_ADDR_REG) ++ ++ /* Start transfer */ ++ MV_REG_READ_ASM (r6, r5, XOR_ACTIVATION_REG(XOR_CHAN0)) ++ orr r6, r6, #0x1 /* Preform start command */ ++ MV_REG_WRITE_ASM(r6, r5, XOR_ACTIVATION_REG(XOR_CHAN0)) ++ ++ /* Wait for engine to finish */ ++waitForComplete: ++ MV_REG_READ_ASM(r6, r5, XOR_CAUSE_REG) ++ and r6, r6, #2 ++ cmp r6, #0 ++ beq waitForComplete ++ ++ /* Clear all error report registers */ ++ MV_REG_WRITE_ASM(r1, r5, SDRAM_SINGLE_BIT_ERR_CNTR_REG) ++ MV_REG_WRITE_ASM(r1, r5, SDRAM_DOUBLE_BIT_ERR_CNTR_REG) ++ ++ MV_REG_WRITE_ASM(r1, r5, SDRAM_ERROR_CAUSE_REG) ++ ++ cmp sp, #0 ++ beq no_stack_l1 ++load_from_stack1: ++ ldmia sp!, {r0, r1, r2, r3, r4, r5, r6} ++no_stack_l1: ++ mov pc, lr ++ ++ ++/******************************************************************************* ++* mvDramIfMemInit - Use XOR to clear all memory. ++* ++* DESCRIPTION: ++* Use assembler function _mvDramIfEccMemInit to fill all memory with FEADFEAD pattern. ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++#if defined(MV78XX0) ++ ++_mvDramIfMemInit: ++ stmdb sp!, {r0,r1, r2, r3, r4, r5, r6} ++ mov r6, LR /* Save link register */ ++ /* Check if dram bank 0 has to be init for ECC */ ++ MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,0)) ++ and r3, r0, #SCSR_WIN_EN ++ cmp r3, #0 ++ beq no_bank_0 ++ MV_REG_READ_ASM(r0, r5, SDRAM_BASE_ADDR_REG(0,0)) ++ cmp r0, #0 ++ beq no_bank_0 ++ mov r0,#0 ++ bl _mvDramIfEccMemInit ++ ++no_bank_0: ++ /* Check if dram bank 1 has to be init for ECC */ ++ MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,1)) ++ and r0, r0, #SCSR_WIN_EN ++ cmp r0, #0 ++ beq no_bank_1 ++ mov r0,#1 ++ bl _mvDramIfEccMemInit ++no_bank_1: ++ /* Check if dram bank 2 has to be init for ECC */ ++ MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,2)) ++ and r0, r0, #SCSR_WIN_EN ++ cmp r0, #0 ++ beq no_bank_2 ++ MV_REG_READ_ASM(r0, r5, SDRAM_BASE_ADDR_REG(0,2)) ++ cmp r0, #0 ++ beq no_bank_2 ++ mov r0,#2 ++ bl _mvDramIfEccMemInit ++ ++no_bank_2: ++ /* Check if dram bank 3 has to be init for ECC */ ++ MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,3)) ++ and r0, r0, #SCSR_WIN_EN ++ cmp r0, #0 ++ beq no_bank_3 ++ mov r0,#3 ++ bl _mvDramIfEccMemInit ++no_bank_3: ++ mov LR ,r6 /* restore link register */ ++ ldmia sp!, {r0, r1, r2, r3, r4, r5, r6} ++ mov pc, lr ++#endif ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,157 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvDramIfConfigh ++#define __INCmvDramIfConfigh ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++/* includes */ ++ ++/* defines */ ++ ++/* registers defaults values */ ++ ++#define SDRAM_CONFIG_DV (SDRAM_SRMODE_DRAM | BIT25 | BIT30) ++ ++#define SDRAM_DUNIT_CTRL_LOW_DDR2_DV \ ++ (SDRAM_SRCLK_KEPT | \ ++ SDRAM_CLK1DRV_NORMAL | \ ++ (BIT28 | BIT29)) ++ ++#define SDRAM_ADDR_CTRL_DV 2 ++ ++#define SDRAM_TIMING_CTRL_LOW_REG_DV \ ++ ((0x2 << SDRAM_TRCD_OFFS) | \ ++ (0x2 << SDRAM_TRP_OFFS) | \ ++ (0x1 << SDRAM_TWR_OFFS) | \ ++ (0x0 << SDRAM_TWTR_OFFS) | \ ++ (0x5 << SDRAM_TRAS_OFFS) | \ ++ (0x1 << SDRAM_TRRD_OFFS)) ++ ++/* Note: value of 0 in register means one cycle, 1 means two and so on */ ++#define SDRAM_TIMING_CTRL_HIGH_REG_DV \ ++ ((0x0 << SDRAM_TR2R_OFFS) | \ ++ (0x0 << SDRAM_TR2W_W2R_OFFS) | \ ++ (0x1 << SDRAM_TW2W_OFFS)) ++ ++#define SDRAM_OPEN_PAGES_CTRL_REG_DV SDRAM_OPEN_PAGE_EN ++ ++/* Presence Ctrl Low Ctrl High Dunit Ctrl Ext Mode */ ++/* CS0 0x84210000 0x00000000 0x0000780F 0x00000440 */ ++/* CS0+CS1 0x84210000 0x00000000 0x0000780F 0x00000440 */ ++/* CS0+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ ++/* CS0+CS1+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ ++/* CS0+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ ++/* CS0+CS1+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ ++ ++#define DDR2_ODT_CTRL_LOW_CS0_CS1_DV 0x84210000 ++#define DDR2_ODT_CTRL_HIGH_CS0_CS1_DV 0x00000000 ++#define DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV 0x0000E80F ++#ifdef MV78XX0 ++#define DDR_SDRAM_EXT_MODE_CS0_CS1_DV 0x00000040 ++#else ++#define DDR_SDRAM_EXT_MODE_CS0_CS1_DV 0x00000440 ++#endif ++ ++#define DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV 0x030C030C ++#define DDR2_ODT_CTRL_HIGH_CS0_CS1_CS2_CS3_DV 0x00000000 ++#define DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV 0x0000F40F ++#ifdef MV78XX0 ++#define DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV 0x00000004 ++#define DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV 0x00000044 ++#else ++#define DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV 0x00000404 ++#define DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV 0x00000444 ++#endif ++ ++/* DDR SDRAM Adderss/Control and Data Pads Calibration default values */ ++#define DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \ ++ (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) ++ ++#define DDR2_DATA_PAD_STRENGTH_TYPICAL_DV \ ++ (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) ++ ++/* DDR SDRAM Mode Register default value */ ++#define DDR2_MODE_REG_DV (SDRAM_BURST_LEN_4 | SDRAM_WR_3_CYC) ++/* DDR SDRAM Timing parameter default values */ ++#define SDRAM_TIMING_CTRL_LOW_REG_DEFAULT 0x33136552 ++#define SDRAM_TRFC_DEFAULT_VALUE 0x34 ++#define SDRAM_TRFC_DEFAULT SDRAM_TRFC_DEFAULT_VALUE ++#define SDRAM_TW2W_DEFALT (0x1 << SDRAM_TW2W_OFFS) ++ ++#define SDRAM_TIMING_CTRL_HIGH_REG_DEFAULT (SDRAM_TRFC_DEFAULT | SDRAM_TW2W_DEFALT) ++ ++#define SDRAM_FTDLL_REG_DEFAULT_LEFT 0x88C800 ++#define SDRAM_FTDLL_REG_DEFAULT_RIGHT 0x88C800 ++#define SDRAM_FTDLL_REG_DEFAULT_UP 0x88C800 ++ ++#ifdef __cplusplus ++} ++#endif /* __cplusplus */ ++ ++#endif /* __INCmvDramIfh */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,423 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvDramIfRegsh ++#define __INCmvDramIfRegsh ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++/* DDR SDRAM Controller Address Decode Registers */ ++ /* SDRAM CSn Base Address Register (SCBAR) */ ++#define SDRAM_BASE_ADDR_REG(cpu,csNum) (0x1500 + ((csNum) * 8) + ((cpu) * 0x70)) ++#define SCBAR_BASE_OFFS 16 ++#define SCBAR_BASE_MASK (0xffff << SCBAR_BASE_OFFS) ++#define SCBAR_BASE_ALIGNMENT 0x10000 ++ ++/* SDRAM CSn Size Register (SCSR) */ ++#define SDRAM_SIZE_REG(cpu,csNum) (0x1504 + ((csNum) * 8) + ((cpu) * 0x70)) ++#define SCSR_SIZE_OFFS 24 ++#define SCSR_SIZE_MASK (0xff << SCSR_SIZE_OFFS) ++#define SCSR_SIZE_ALIGNMENT 0x1000000 ++#define SCSR_WIN_EN BIT0 ++ ++/* configuration register */ ++#define SDRAM_CONFIG_REG (DRAM_BASE + 0x1400) ++#define SDRAM_REFRESH_OFFS 0 ++#define SDRAM_REFRESH_MAX 0x3FFF ++#define SDRAM_REFRESH_MASK (SDRAM_REFRESH_MAX << SDRAM_REFRESH_OFFS) ++#define SDRAM_DWIDTH_OFFS 15 ++#define SDRAM_DWIDTH_MASK (1 << SDRAM_DWIDTH_OFFS) ++#define SDRAM_DWIDTH_32BIT (0 << SDRAM_DWIDTH_OFFS) ++#define SDRAM_DWIDTH_64BIT (1 << SDRAM_DWIDTH_OFFS) ++#define SDRAM_REGISTERED (1 << 17) ++#define SDRAM_ECC_OFFS 18 ++#define SDRAM_ECC_MASK (1 << SDRAM_ECC_OFFS) ++#define SDRAM_ECC_DIS (0 << SDRAM_ECC_OFFS) ++#define SDRAM_ECC_EN (1 << SDRAM_ECC_OFFS) ++#define SDRAM_IERR_OFFS 19 ++#define SDRAM_IERR_MASK (1 << SDRAM_IERR_OFFS) ++#define SDRAM_IERR_REPORTE (0 << SDRAM_IERR_OFFS) ++#define SDRAM_IERR_IGNORE (1 << SDRAM_IERR_OFFS) ++#define SDRAM_SRMODE_OFFS 24 ++#define SDRAM_SRMODE_MASK (1 << SDRAM_SRMODE_OFFS) ++#define SDRAM_SRMODE_POWER (0 << SDRAM_SRMODE_OFFS) ++#define SDRAM_SRMODE_DRAM (1 << SDRAM_SRMODE_OFFS) ++ ++/* dunit control low register */ ++#define SDRAM_DUNIT_CTRL_REG (DRAM_BASE + 0x1404) ++#define SDRAM_2T_OFFS 4 ++#define SDRAM_2T_MASK (1 << SDRAM_2T_OFFS) ++#define SDRAM_2T_MODE (1 << SDRAM_2T_OFFS) ++ ++#define SDRAM_SRCLK_OFFS 5 ++#define SDRAM_SRCLK_MASK (1 << SDRAM_SRCLK_OFFS) ++#define SDRAM_SRCLK_KEPT (0 << SDRAM_SRCLK_OFFS) ++#define SDRAM_SRCLK_GATED (1 << SDRAM_SRCLK_OFFS) ++#define SDRAM_CTRL_POS_OFFS 6 ++#define SDRAM_CTRL_POS_MASK (1 << SDRAM_CTRL_POS_OFFS) ++#define SDRAM_CTRL_POS_FALL (0 << SDRAM_CTRL_POS_OFFS) ++#define SDRAM_CTRL_POS_RISE (1 << SDRAM_CTRL_POS_OFFS) ++#define SDRAM_CLK1DRV_OFFS 12 ++#define SDRAM_CLK1DRV_MASK (1 << SDRAM_CLK1DRV_OFFS) ++#define SDRAM_CLK1DRV_HIGH_Z (0 << SDRAM_CLK1DRV_OFFS) ++#define SDRAM_CLK1DRV_NORMAL (1 << SDRAM_CLK1DRV_OFFS) ++#define SDRAM_CLK2DRV_OFFS 13 ++#define SDRAM_CLK2DRV_MASK (1 << SDRAM_CLK2DRV_OFFS) ++#define SDRAM_CLK2DRV_HIGH_Z (0 << SDRAM_CLK2DRV_OFFS) ++#define SDRAM_CLK2DRV_NORMAL (1 << SDRAM_CLK2DRV_OFFS) ++#define SDRAM_SB_OUT_DEL_OFFS 20 ++#define SDRAM_SB_OUT_DEL_MAX 0xf ++#define SDRAM_SB_OUT_MASK (SDRAM_SB_OUT_DEL_MAX<= MV_DRAM_MAX_CS )) ++ { ++ DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); ++ return MV_BAD_PARAM; ++ } ++ memset(pBankInfo, 0, sizeof(*pBankInfo)); ++ ++ if ( MV_OK != dimmSpdGet((MV_U32)(bankNum/2), &dimmInfo)) ++ { ++ DB(mvOsPrintf("Dram: ERR dimmSpdGet failed to get dimm info \n")); ++ return MV_FAIL; ++ } ++ if ((dimmInfo.numOfModuleBanks == 1) && ((bankNum % 2) == 1)) ++ { ++ DB(mvOsPrintf("Dram: ERR dimmSpdGet. Can't find DIMM bank 2 \n")); ++ return MV_FAIL; ++ } ++ /* convert Dimm info to Bank info */ ++ cpyDimm2BankInfo(&dimmInfo, pBankInfo); ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* cpyDimm2BankInfo - Convert a Dimm info struct into a bank info struct. ++* ++* DESCRIPTION: ++* Convert a Dimm info struct into a bank info struct. ++* ++* INPUT: ++* pDimmInfo - DIMM information structure. ++* ++* OUTPUT: ++* pBankInfo - DRAM bank information struct. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++static MV_VOID cpyDimm2BankInfo(MV_DIMM_INFO *pDimmInfo, ++ MV_DRAM_BANK_INFO *pBankInfo) ++{ ++ pBankInfo->memoryType = pDimmInfo->memoryType; ++ ++ /* DIMM dimensions */ ++ pBankInfo->numOfRowAddr = pDimmInfo->numOfRowAddr; ++ pBankInfo->numOfColAddr = pDimmInfo->numOfColAddr; ++ pBankInfo->dataWidth = pDimmInfo->dataWidth; ++ pBankInfo->errorCheckType = pDimmInfo->errorCheckType; ++ pBankInfo->sdramWidth = pDimmInfo->sdramWidth; ++ pBankInfo->errorCheckDataWidth = pDimmInfo->errorCheckDataWidth; ++ pBankInfo->numOfBanksOnEachDevice = pDimmInfo->numOfBanksOnEachDevice; ++ pBankInfo->suportedCasLatencies = pDimmInfo->suportedCasLatencies; ++ pBankInfo->refreshInterval = pDimmInfo->refreshInterval; ++ ++ /* DIMM timing parameters */ ++ pBankInfo->minCycleTimeAtMaxCasLatPs = pDimmInfo->minCycleTimeAtMaxCasLatPs; ++ pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps = ++ pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps; ++ pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps = ++ pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps; ++ ++ pBankInfo->minRowPrechargeTime = pDimmInfo->minRowPrechargeTime; ++ pBankInfo->minRowActiveToRowActive = pDimmInfo->minRowActiveToRowActive; ++ pBankInfo->minRasToCasDelay = pDimmInfo->minRasToCasDelay; ++ pBankInfo->minRasPulseWidth = pDimmInfo->minRasPulseWidth; ++ pBankInfo->minWriteRecoveryTime = pDimmInfo->minWriteRecoveryTime; ++ pBankInfo->minWriteToReadCmdDelay = pDimmInfo->minWriteToReadCmdDelay; ++ pBankInfo->minReadToPrechCmdDelay = pDimmInfo->minReadToPrechCmdDelay; ++ pBankInfo->minRefreshToActiveCmd = pDimmInfo->minRefreshToActiveCmd; ++ ++ /* Parameters calculated from the extracted DIMM information */ ++ pBankInfo->size = pDimmInfo->size/pDimmInfo->numOfModuleBanks; ++ pBankInfo->deviceDensity = pDimmInfo->deviceDensity; ++ pBankInfo->numberOfDevices = pDimmInfo->numberOfDevices / ++ pDimmInfo->numOfModuleBanks; ++ ++ /* DIMM attributes (MV_TRUE for yes) */ ++ ++ if ((pDimmInfo->memoryType == MEM_TYPE_SDRAM) || ++ (pDimmInfo->memoryType == MEM_TYPE_DDR1) ) ++ { ++ if (pDimmInfo->dimmAttributes & BIT1) ++ pBankInfo->registeredAddrAndControlInputs = MV_TRUE; ++ else ++ pBankInfo->registeredAddrAndControlInputs = MV_FALSE; ++ } ++ else /* pDimmInfo->memoryType == MEM_TYPE_DDR2 */ ++ { ++ if (pDimmInfo->dimmTypeInfo & (BIT0 | BIT4)) ++ pBankInfo->registeredAddrAndControlInputs = MV_TRUE; ++ else ++ pBankInfo->registeredAddrAndControlInputs = MV_FALSE; ++ } ++ ++ return; ++} ++/******************************************************************************* ++* dimmSpdCpy - Cpy SPD parameters from dimm 0 to dimm 1. ++* ++* DESCRIPTION: ++* Read the DIMM SPD parameters from dimm 0 into dimm 1 SPD. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. ++* ++*******************************************************************************/ ++MV_STATUS dimmSpdCpy(MV_VOID) ++{ ++ MV_U32 i; ++ MV_U32 spdChecksum; ++ ++ MV_TWSI_SLAVE twsiSlave; ++ MV_U8 data[SPD_SIZE]; ++ ++ /* zero dimmInfo structure */ ++ memset(data, 0, SPD_SIZE); ++ ++ /* read the dimm eeprom */ ++ DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); ++ twsiSlave.slaveAddr.address = MV_BOARD_DIMM0_I2C_ADDR; ++ twsiSlave.slaveAddr.type = ADDR7_BIT; ++ twsiSlave.validOffset = MV_TRUE; ++ twsiSlave.offset = 0; ++ twsiSlave.moreThen256 = MV_FALSE; ++ ++ if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, &twsiSlave, data, SPD_SIZE) ) ++ { ++ DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 0\n")); ++ return MV_FAIL; ++ } ++ DB(puts("DRAM: Reading dimm info succeded.\n")); ++ ++ /* calculate SPD checksum */ ++ spdChecksum = 0; ++ ++ for(i = 0 ; i <= 62 ; i++) ++ { ++ spdChecksum += data[i]; ++ } ++ ++ if ((spdChecksum & 0xff) != data[63]) ++ { ++ DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", ++ (MV_U32)(spdChecksum & 0xff), data[63])); ++ } ++ else ++ { ++ DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); ++ } ++ ++ /* copy the SPD content 1:1 into the DIMM 1 SPD */ ++ twsiSlave.slaveAddr.address = MV_BOARD_DIMM1_I2C_ADDR; ++ twsiSlave.slaveAddr.type = ADDR7_BIT; ++ twsiSlave.validOffset = MV_TRUE; ++ twsiSlave.offset = 0; ++ twsiSlave.moreThen256 = MV_FALSE; ++ ++ for(i = 0 ; i < SPD_SIZE ; i++) ++ { ++ twsiSlave.offset = i; ++ if( MV_OK != mvTwsiWrite (MV_BOARD_DIMM_I2C_CHANNEL, &twsiSlave, &data[i], 1) ) ++ { ++ mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 1 byte %d \n",i); ++ return MV_FAIL; ++ } ++ mvOsDelay(5); ++ } ++ ++ DB(puts("DRAM: Reading dimm info succeded.\n")); ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* dimmSpdGet - Get the SPD parameters. ++* ++* DESCRIPTION: ++* Read the DIMM SPD parameters into given struct parameter. ++* ++* INPUT: ++* dimmNum - DIMM number. See MV_BOARD_DIMM_NUM enumerator. ++* ++* OUTPUT: ++* pDimmInfo - DIMM information structure. ++* ++* RETURN: ++* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. ++* ++*******************************************************************************/ ++MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo) ++{ ++ MV_U32 i; ++ MV_U32 density = 1; ++ MV_U32 spdChecksum; ++ ++ MV_TWSI_SLAVE twsiSlave; ++ MV_U8 data[SPD_SIZE]; ++ ++ if((NULL == pDimmInfo)|| (dimmNum >= MAX_DIMM_NUM)) ++ { ++ DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); ++ return MV_BAD_PARAM; ++ } ++ ++ /* zero dimmInfo structure */ ++ memset(data, 0, SPD_SIZE); ++ ++ /* read the dimm eeprom */ ++ DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); ++ twsiSlave.slaveAddr.address = (dimmNum == 0) ? ++ MV_BOARD_DIMM0_I2C_ADDR : MV_BOARD_DIMM1_I2C_ADDR; ++ twsiSlave.slaveAddr.type = ADDR7_BIT; ++ twsiSlave.validOffset = MV_TRUE; ++ twsiSlave.offset = 0; ++ twsiSlave.moreThen256 = MV_FALSE; ++ ++ if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, &twsiSlave, data, SPD_SIZE) ) ++ { ++ DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum %d \n", dimmNum)); ++ return MV_FAIL; ++ } ++ DB(puts("DRAM: Reading dimm info succeded.\n")); ++ ++ /* calculate SPD checksum */ ++ spdChecksum = 0; ++ ++ for(i = 0 ; i <= 62 ; i++) ++ { ++ spdChecksum += data[i]; ++ } ++ ++ if ((spdChecksum & 0xff) != data[63]) ++ { ++ DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", ++ (MV_U32)(spdChecksum & 0xff), data[63])); ++ } ++ else ++ { ++ DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); ++ } ++ ++ /* copy the SPD content 1:1 into the dimmInfo structure*/ ++ for(i = 0 ; i < SPD_SIZE ; i++) ++ { ++ pDimmInfo->spdRawData[i] = data[i]; ++ DB(mvOsPrintf("SPD-EEPROM Byte %3d = %3x (%3d)\n",i, data[i], data[i])); ++ } ++ ++ DB(mvOsPrintf("DRAM SPD Information:\n")); ++ ++ /* Memory type (DDR / SDRAM) */ ++ switch (data[DIMM_MEM_TYPE]) ++ { ++ case (DIMM_MEM_TYPE_SDRAM): ++ pDimmInfo->memoryType = MEM_TYPE_SDRAM; ++ DB(mvOsPrintf("DRAM Memeory type SDRAM\n")); ++ break; ++ case (DIMM_MEM_TYPE_DDR1): ++ pDimmInfo->memoryType = MEM_TYPE_DDR1; ++ DB(mvOsPrintf("DRAM Memeory type DDR1\n")); ++ break; ++ case (DIMM_MEM_TYPE_DDR2): ++ pDimmInfo->memoryType = MEM_TYPE_DDR2; ++ DB(mvOsPrintf("DRAM Memeory type DDR2\n")); ++ break; ++ default: ++ mvOsPrintf("ERROR: Undefined memory type!\n"); ++ return MV_ERROR; ++ } ++ ++ ++ /* Number Of Row Addresses */ ++ pDimmInfo->numOfRowAddr = data[DIMM_ROW_NUM]; ++ DB(mvOsPrintf("DRAM numOfRowAddr[3] %d\n",pDimmInfo->numOfRowAddr)); ++ ++ /* Number Of Column Addresses */ ++ pDimmInfo->numOfColAddr = data[DIMM_COL_NUM]; ++ DB(mvOsPrintf("DRAM numOfColAddr[4] %d\n",pDimmInfo->numOfColAddr)); ++ ++ /* Number Of Module Banks */ ++ pDimmInfo->numOfModuleBanks = data[DIMM_MODULE_BANK_NUM]; ++ DB(mvOsPrintf("DRAM numOfModuleBanks[5] 0x%x\n", ++ pDimmInfo->numOfModuleBanks)); ++ ++ /* Number of module banks encoded differently for DDR2 */ ++ if (pDimmInfo->memoryType == MEM_TYPE_DDR2) ++ pDimmInfo->numOfModuleBanks = (pDimmInfo->numOfModuleBanks & 0x7)+1; ++ ++ /* Data Width */ ++ pDimmInfo->dataWidth = data[DIMM_DATA_WIDTH]; ++ DB(mvOsPrintf("DRAM dataWidth[6] 0x%x\n", pDimmInfo->dataWidth)); ++ ++ /* Minimum Cycle Time At Max CasLatancy */ ++ pDimmInfo->minCycleTimeAtMaxCasLatPs = cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS]); ++ ++ /* Error Check Type */ ++ pDimmInfo->errorCheckType = data[DIMM_ERR_CHECK_TYPE]; ++ DB(mvOsPrintf("DRAM errorCheckType[11] 0x%x\n", ++ pDimmInfo->errorCheckType)); ++ ++ /* Refresh Interval */ ++ pDimmInfo->refreshInterval = data[DIMM_REFRESH_INTERVAL]; ++ DB(mvOsPrintf("DRAM refreshInterval[12] 0x%x\n", ++ pDimmInfo->refreshInterval)); ++ ++ /* Sdram Width */ ++ pDimmInfo->sdramWidth = data[DIMM_SDRAM_WIDTH]; ++ DB(mvOsPrintf("DRAM sdramWidth[13] 0x%x\n",pDimmInfo->sdramWidth)); ++ ++ /* Error Check Data Width */ ++ pDimmInfo->errorCheckDataWidth = data[DIMM_ERR_CHECK_DATA_WIDTH]; ++ DB(mvOsPrintf("DRAM errorCheckDataWidth[14] 0x%x\n", ++ pDimmInfo->errorCheckDataWidth)); ++ ++ /* Burst Length Supported */ ++ /* SDRAM/DDR1: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * ++ *********************************************************/ ++ /* DDR2: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * ++ *********************************************************/ ++ ++ pDimmInfo->burstLengthSupported = data[DIMM_BURST_LEN_SUP]; ++ DB(mvOsPrintf("DRAM burstLengthSupported[16] 0x%x\n", ++ pDimmInfo->burstLengthSupported)); ++ ++ /* Number Of Banks On Each Device */ ++ pDimmInfo->numOfBanksOnEachDevice = data[DIMM_DEV_BANK_NUM]; ++ DB(mvOsPrintf("DRAM numOfBanksOnEachDevice[17] 0x%x\n", ++ pDimmInfo->numOfBanksOnEachDevice)); ++ ++ /* Suported Cas Latencies */ ++ ++ /* SDRAM: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * ++ ********************************************************/ ++ ++ /* DDR 1: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * ++ *********************************************************/ ++ ++ /* DDR 2: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * ++ *********************************************************/ ++ ++ pDimmInfo->suportedCasLatencies = data[DIMM_SUP_CAL]; ++ DB(mvOsPrintf("DRAM suportedCasLatencies[18] 0x%x\n", ++ pDimmInfo->suportedCasLatencies)); ++ ++ /* For DDR2 only, get the DIMM type information */ ++ if (pDimmInfo->memoryType == MEM_TYPE_DDR2) ++ { ++ pDimmInfo->dimmTypeInfo = data[DIMM_DDR2_TYPE_INFORMATION]; ++ DB(mvOsPrintf("DRAM dimmTypeInfo[20] (DDR2) 0x%x\n", ++ pDimmInfo->dimmTypeInfo)); ++ } ++ ++ /* SDRAM Modules Attributes */ ++ pDimmInfo->dimmAttributes = data[DIMM_BUF_ADDR_CONT_IN]; ++ DB(mvOsPrintf("DRAM dimmAttributes[21] 0x%x\n", ++ pDimmInfo->dimmAttributes)); ++ ++ /* Minimum Cycle Time At Max CasLatancy Minus 1*/ ++ pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps = ++ cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS1]); ++ ++ /* Minimum Cycle Time At Max CasLatancy Minus 2*/ ++ pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps = ++ cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS2]); ++ ++ pDimmInfo->minRowPrechargeTime = data[DIMM_MIN_ROW_PRECHARGE_TIME]; ++ DB(mvOsPrintf("DRAM minRowPrechargeTime[27] 0x%x\n", ++ pDimmInfo->minRowPrechargeTime)); ++ pDimmInfo->minRowActiveToRowActive = data[DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE]; ++ DB(mvOsPrintf("DRAM minRowActiveToRowActive[28] 0x%x\n", ++ pDimmInfo->minRowActiveToRowActive)); ++ pDimmInfo->minRasToCasDelay = data[DIMM_MIN_RAS_TO_CAS_DELAY]; ++ DB(mvOsPrintf("DRAM minRasToCasDelay[29] 0x%x\n", ++ pDimmInfo->minRasToCasDelay)); ++ pDimmInfo->minRasPulseWidth = data[DIMM_MIN_RAS_PULSE_WIDTH]; ++ DB(mvOsPrintf("DRAM minRasPulseWidth[30] 0x%x\n", ++ pDimmInfo->minRasPulseWidth)); ++ ++ /* DIMM Bank Density */ ++ pDimmInfo->dimmBankDensity = data[DIMM_BANK_DENSITY]; ++ DB(mvOsPrintf("DRAM dimmBankDensity[31] 0x%x\n", ++ pDimmInfo->dimmBankDensity)); ++ ++ /* Only DDR2 includes Write Recovery Time field. Other SDRAM ignore */ ++ pDimmInfo->minWriteRecoveryTime = data[DIMM_MIN_WRITE_RECOVERY_TIME]; ++ DB(mvOsPrintf("DRAM minWriteRecoveryTime[36] 0x%x\n", ++ pDimmInfo->minWriteRecoveryTime)); ++ ++ /* Only DDR2 includes Internal Write To Read Command Delay field. */ ++ pDimmInfo->minWriteToReadCmdDelay = data[DIMM_MIN_WRITE_TO_READ_CMD_DELAY]; ++ DB(mvOsPrintf("DRAM minWriteToReadCmdDelay[37] 0x%x\n", ++ pDimmInfo->minWriteToReadCmdDelay)); ++ ++ /* Only DDR2 includes Internal Read To Precharge Command Delay field. */ ++ pDimmInfo->minReadToPrechCmdDelay = data[DIMM_MIN_READ_TO_PRECH_CMD_DELAY]; ++ DB(mvOsPrintf("DRAM minReadToPrechCmdDelay[38] 0x%x\n", ++ pDimmInfo->minReadToPrechCmdDelay)); ++ ++ /* Only DDR2 includes Minimum Refresh to Activate/Refresh Command field */ ++ pDimmInfo->minRefreshToActiveCmd = data[DIMM_MIN_REFRESH_TO_ACTIVATE_CMD]; ++ DB(mvOsPrintf("DRAM minRefreshToActiveCmd[42] 0x%x\n", ++ pDimmInfo->minRefreshToActiveCmd)); ++ ++ /* calculating the sdram density. Representing device density from */ ++ /* bit 20 to allow representation of 4GB and above. */ ++ /* For example, if density is 512Mbit 0x20000000, will be represent in */ ++ /* deviceDensity by 0x20000000 >> 16 --> 0x00000200. Another example */ ++ /* is density 8GB 0x200000000 >> 16 --> 0x00002000. */ ++ density = (1 << ((pDimmInfo->numOfRowAddr + pDimmInfo->numOfColAddr) - 20)); ++ pDimmInfo->deviceDensity = density * ++ pDimmInfo->numOfBanksOnEachDevice * ++ pDimmInfo->sdramWidth; ++ DB(mvOsPrintf("DRAM deviceDensity %d\n",pDimmInfo->deviceDensity)); ++ ++ /* Number of devices includeing Error correction */ ++ pDimmInfo->numberOfDevices = (pDimmInfo->dataWidth/pDimmInfo->sdramWidth) * ++ pDimmInfo->numOfModuleBanks; ++ DB(mvOsPrintf("DRAM numberOfDevices %d\n", ++ pDimmInfo->numberOfDevices)); ++ ++ pDimmInfo->size = 0; ++ ++ /* Note that pDimmInfo->size is in MB units */ ++ if (pDimmInfo->memoryType == MEM_TYPE_SDRAM) ++ { ++ if (pDimmInfo->dimmBankDensity & BIT0) ++ pDimmInfo->size += 1024; /* Equal to 1GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT1) ++ pDimmInfo->size += 8; /* Equal to 8MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT2) ++ pDimmInfo->size += 16; /* Equal to 16MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT3) ++ pDimmInfo->size += 32; /* Equal to 32MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT4) ++ pDimmInfo->size += 64; /* Equal to 64MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT5) ++ pDimmInfo->size += 128; /* Equal to 128MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT6) ++ pDimmInfo->size += 256; /* Equal to 256MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT7) ++ pDimmInfo->size += 512; /* Equal to 512MB */ ++ } ++ else if (pDimmInfo->memoryType == MEM_TYPE_DDR1) ++ { ++ if (pDimmInfo->dimmBankDensity & BIT0) ++ pDimmInfo->size += 1024; /* Equal to 1GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT1) ++ pDimmInfo->size += 2048; /* Equal to 2GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT2) ++ pDimmInfo->size += 16; /* Equal to 16MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT3) ++ pDimmInfo->size += 32; /* Equal to 32MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT4) ++ pDimmInfo->size += 64; /* Equal to 64MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT5) ++ pDimmInfo->size += 128; /* Equal to 128MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT6) ++ pDimmInfo->size += 256; /* Equal to 256MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT7) ++ pDimmInfo->size += 512; /* Equal to 512MB */ ++ } ++ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ ++ { ++ if (pDimmInfo->dimmBankDensity & BIT0) ++ pDimmInfo->size += 1024; /* Equal to 1GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT1) ++ pDimmInfo->size += 2048; /* Equal to 2GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT2) ++ pDimmInfo->size += 4096; /* Equal to 4GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT3) ++ pDimmInfo->size += 8192; /* Equal to 8GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT4) ++ pDimmInfo->size += 16384; /* Equal to 16GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT5) ++ pDimmInfo->size += 128; /* Equal to 128MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT6) ++ pDimmInfo->size += 256; /* Equal to 256MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT7) ++ pDimmInfo->size += 512; /* Equal to 512MB */ ++ } ++ ++ pDimmInfo->size *= pDimmInfo->numOfModuleBanks; ++ ++ DB(mvOsPrintf("Dram: dimm size %dMB \n",pDimmInfo->size)); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* dimmSpdPrint - Print the SPD parameters. ++* ++* DESCRIPTION: ++* Print the Dimm SPD parameters. ++* ++* INPUT: ++* pDimmInfo - DIMM information structure. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID dimmSpdPrint(MV_U32 dimmNum) ++{ ++ MV_DIMM_INFO dimmInfo; ++ MV_U32 i, temp = 0; ++ MV_U32 k, maskLeftOfPoint = 0, maskRightOfPoint = 0; ++ MV_U32 rightOfPoint = 0,leftOfPoint = 0, div, time_tmp, shift; ++ MV_U32 busClkPs; ++ MV_U8 trp_clocks=0, trcd_clocks, tras_clocks, trrd_clocks, ++ temp_buf[40], *spdRawData; ++ ++ busClkPs = 1000000000 / (mvBoardSysClkGet() / 100); /* in 10 ps units */ ++ ++ spdRawData = dimmInfo.spdRawData; ++ ++ if(MV_OK != dimmSpdGet(dimmNum, &dimmInfo)) ++ { ++ mvOsOutput("ERROR: Could not read SPD information!\n"); ++ return; ++ } ++ ++ /* find Manufactura of Dimm Module */ ++ mvOsOutput("\nManufacturer's JEDEC ID Code: "); ++ for(i = 0 ; i < DIMM_MODULE_MANU_SIZE ; i++) ++ { ++ mvOsOutput("%x",spdRawData[DIMM_MODULE_MANU_OFFS + i]); ++ } ++ mvOsOutput("\n"); ++ ++ /* Manufacturer's Specific Data */ ++ for(i = 0 ; i < DIMM_MODULE_ID_SIZE ; i++) ++ { ++ temp_buf[i] = spdRawData[DIMM_MODULE_ID_OFFS + i]; ++ } ++ mvOsOutput("Manufacturer's Specific Data: %s\n", temp_buf); ++ ++ /* Module Part Number */ ++ for(i = 0 ; i < DIMM_MODULE_VEN_SIZE ; i++) ++ { ++ temp_buf[i] = spdRawData[DIMM_MODULE_VEN_OFFS + i]; ++ } ++ mvOsOutput("Module Part Number: %s\n", temp_buf); ++ ++ /* Module Serial Number */ ++ for(i = 0; i < sizeof(MV_U32); i++) ++ { ++ temp |= spdRawData[95+i] << 8*i; ++ } ++ mvOsOutput("DIMM Serial No. %ld (%lx)\n", (long)temp, ++ (long)temp); ++ ++ /* find Manufac-Data of Dimm Module */ ++ mvOsOutput("Manufactoring Date: Year 20%d%d/ ww %d%d\n", ++ ((spdRawData[93] & 0xf0) >> 4), (spdRawData[93] & 0xf), ++ ((spdRawData[94] & 0xf0) >> 4), (spdRawData[94] & 0xf)); ++ /* find modul_revision of Dimm Module */ ++ mvOsOutput("Module Revision: %d.%d\n", ++ spdRawData[62]/10, spdRawData[62]%10); ++ ++ /* find manufac_place of Dimm Module */ ++ mvOsOutput("manufac_place: %d\n", spdRawData[72]); ++ ++ /* go over the first 35 I2C data bytes */ ++ for(i = 2 ; i <= 35 ; i++) ++ switch(i) ++ { ++ case 2: /* Memory type (DDR1/2 / SDRAM) */ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ mvOsOutput("Dram Type is: SDRAM\n"); ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) ++ mvOsOutput("Dram Type is: SDRAM DDR1\n"); ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) ++ mvOsOutput("Dram Type is: SDRAM DDR2\n"); ++ else ++ mvOsOutput("Dram Type unknown\n"); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 3: /* Number Of Row Addresses */ ++ mvOsOutput("Module Number of row addresses: %d\n", ++ dimmInfo.numOfRowAddr); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 4: /* Number Of Column Addresses */ ++ mvOsOutput("Module Number of col addresses: %d\n", ++ dimmInfo.numOfColAddr); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 5: /* Number Of Module Banks */ ++ mvOsOutput("Number of Banks on Mod.: %d\n", ++ dimmInfo.numOfModuleBanks); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 6: /* Data Width */ ++ mvOsOutput("Module Data Width: %d bit\n", ++ dimmInfo.dataWidth); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 8: /* Voltage Interface */ ++ switch(spdRawData[i]) ++ { ++ case 0x0: ++ mvOsOutput("Module is TTL_5V_TOLERANT\n"); ++ break; ++ case 0x1: ++ mvOsOutput("Module is LVTTL\n"); ++ break; ++ case 0x2: ++ mvOsOutput("Module is HSTL_1_5V\n"); ++ break; ++ case 0x3: ++ mvOsOutput("Module is SSTL_3_3V\n"); ++ break; ++ case 0x4: ++ mvOsOutput("Module is SSTL_2_5V\n"); ++ break; ++ case 0x5: ++ if (dimmInfo.memoryType != MEM_TYPE_SDRAM) ++ { ++ mvOsOutput("Module is SSTL_1_8V\n"); ++ break; ++ } ++ default: ++ mvOsOutput("Module is VOLTAGE_UNKNOWN\n"); ++ break; ++ } ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 9: /* Minimum Cycle Time At Max CasLatancy */ ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ rightOfPoint = (spdRawData[i] & 0x0f) * 10; ++ ++ /* DDR2 addition of right of point */ ++ if ((spdRawData[i] & 0x0f) == 0xA) ++ { ++ rightOfPoint = 25; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xB) ++ { ++ rightOfPoint = 33; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xC) ++ { ++ rightOfPoint = 66; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xD) ++ { ++ rightOfPoint = 75; ++ } ++ mvOsOutput("Minimum Cycle Time At Max CL: %d.%d [ns]\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 10: /* Clock To Data Out */ ++ div = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 10:100; ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = time_tmp / div; ++ rightOfPoint = time_tmp % div; ++ mvOsOutput("Clock To Data Out: %d.%d [ns]\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 11: /* Error Check Type */ ++ mvOsOutput("Error Check Type (0=NONE): %d\n", ++ dimmInfo.errorCheckType); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 12: /* Refresh Interval */ ++ mvOsOutput("Refresh Rate: %x\n", ++ dimmInfo.refreshInterval); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 13: /* Sdram Width */ ++ mvOsOutput("Sdram Width: %d bits\n", ++ dimmInfo.sdramWidth); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 14: /* Error Check Data Width */ ++ mvOsOutput("Error Check Data Width: %d bits\n", ++ dimmInfo.errorCheckDataWidth); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 15: /* Minimum Clock Delay is unsupported */ ++ if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || ++ (dimmInfo.memoryType == MEM_TYPE_DDR1)) ++ { ++ mvOsOutput("Minimum Clk Delay back to back: %d\n", ++ spdRawData[i]); ++ } ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 16: /* Burst Length Supported */ ++ /* SDRAM/DDR1: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * ++ *********************************************************/ ++ /* DDR2: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * ++ *********************************************************/ ++ mvOsOutput("Burst Length Supported: "); ++ if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || ++ (dimmInfo.memoryType == MEM_TYPE_DDR1)) ++ { ++ if (dimmInfo.burstLengthSupported & BIT0) ++ mvOsOutput("1, "); ++ if (dimmInfo.burstLengthSupported & BIT1) ++ mvOsOutput("2, "); ++ } ++ if (dimmInfo.burstLengthSupported & BIT2) ++ mvOsOutput("4, "); ++ if (dimmInfo.burstLengthSupported & BIT3) ++ mvOsOutput("8, "); ++ ++ mvOsOutput(" Bit \n"); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 17: /* Number Of Banks On Each Device */ ++ mvOsOutput("Number Of Banks On Each Chip: %d\n", ++ dimmInfo.numOfBanksOnEachDevice); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 18: /* Suported Cas Latencies */ ++ ++ /* SDRAM: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * ++ ********************************************************/ ++ ++ /* DDR 1: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * ++ *********************************************************/ ++ ++ /* DDR 2: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * ++ *********************************************************/ ++ ++ mvOsOutput("Suported Cas Latencies: (CL) "); ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ for (k = 0; k <=7; k++) ++ { ++ if (dimmInfo.suportedCasLatencies & (1 << k)) ++ mvOsOutput("%d, ", k+1); ++ } ++ } ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) ++ { ++ if (dimmInfo.suportedCasLatencies & BIT0) ++ mvOsOutput("1, "); ++ if (dimmInfo.suportedCasLatencies & BIT1) ++ mvOsOutput("1.5, "); ++ if (dimmInfo.suportedCasLatencies & BIT2) ++ mvOsOutput("2, "); ++ if (dimmInfo.suportedCasLatencies & BIT3) ++ mvOsOutput("2.5, "); ++ if (dimmInfo.suportedCasLatencies & BIT4) ++ mvOsOutput("3, "); ++ if (dimmInfo.suportedCasLatencies & BIT5) ++ mvOsOutput("3.5, "); ++ } ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) ++ { ++ if (dimmInfo.suportedCasLatencies & BIT2) ++ mvOsOutput("2, "); ++ if (dimmInfo.suportedCasLatencies & BIT3) ++ mvOsOutput("3, "); ++ if (dimmInfo.suportedCasLatencies & BIT4) ++ mvOsOutput("4, "); ++ if (dimmInfo.suportedCasLatencies & BIT5) ++ mvOsOutput("5, "); ++ } ++ else ++ mvOsOutput("?.?, "); ++ mvOsOutput("\n"); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 20: /* DDR2 DIMM type info */ ++ if (dimmInfo.memoryType == MEM_TYPE_DDR2) ++ { ++ if (dimmInfo.dimmTypeInfo & (BIT0 | BIT4)) ++ mvOsOutput("Registered DIMM (RDIMM)\n"); ++ else if (dimmInfo.dimmTypeInfo & (BIT1 | BIT5)) ++ mvOsOutput("Unbuffered DIMM (UDIMM)\n"); ++ else ++ mvOsOutput("Unknown DIMM type.\n"); ++ } ++ ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 21: /* SDRAM Modules Attributes */ ++ mvOsOutput("\nModule Attributes (SPD Byte 21): \n"); ++ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ if (dimmInfo.dimmAttributes & BIT0) ++ mvOsOutput(" Buffered Addr/Control Input: Yes\n"); ++ else ++ mvOsOutput(" Buffered Addr/Control Input: No\n"); ++ ++ if (dimmInfo.dimmAttributes & BIT1) ++ mvOsOutput(" Registered Addr/Control Input: Yes\n"); ++ else ++ mvOsOutput(" Registered Addr/Control Input: No\n"); ++ ++ if (dimmInfo.dimmAttributes & BIT2) ++ mvOsOutput(" On-Card PLL (clock): Yes \n"); ++ else ++ mvOsOutput(" On-Card PLL (clock): No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT3) ++ mvOsOutput(" Bufferd DQMB Input: Yes \n"); ++ else ++ mvOsOutput(" Bufferd DQMB Inputs: No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT4) ++ mvOsOutput(" Registered DQMB Inputs: Yes \n"); ++ else ++ mvOsOutput(" Registered DQMB Inputs: No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT5) ++ mvOsOutput(" Differential Clock Input: Yes \n"); ++ else ++ mvOsOutput(" Differential Clock Input: No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT6) ++ mvOsOutput(" redundant Row Addressing: Yes \n"); ++ else ++ mvOsOutput(" redundant Row Addressing: No \n"); ++ } ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) ++ { ++ if (dimmInfo.dimmAttributes & BIT0) ++ mvOsOutput(" Buffered Addr/Control Input: Yes\n"); ++ else ++ mvOsOutput(" Buffered Addr/Control Input: No\n"); ++ ++ if (dimmInfo.dimmAttributes & BIT1) ++ mvOsOutput(" Registered Addr/Control Input: Yes\n"); ++ else ++ mvOsOutput(" Registered Addr/Control Input: No\n"); ++ ++ if (dimmInfo.dimmAttributes & BIT2) ++ mvOsOutput(" On-Card PLL (clock): Yes \n"); ++ else ++ mvOsOutput(" On-Card PLL (clock): No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT3) ++ mvOsOutput(" FET Switch On-Card Enabled: Yes \n"); ++ else ++ mvOsOutput(" FET Switch On-Card Enabled: No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT4) ++ mvOsOutput(" FET Switch External Enabled: Yes \n"); ++ else ++ mvOsOutput(" FET Switch External Enabled: No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT5) ++ mvOsOutput(" Differential Clock Input: Yes \n"); ++ else ++ mvOsOutput(" Differential Clock Input: No \n"); ++ } ++ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ ++ { ++ mvOsOutput(" Number of Active Registers on the DIMM: %d\n", ++ (dimmInfo.dimmAttributes & 0x3) + 1); ++ ++ mvOsOutput(" Number of PLLs on the DIMM: %d\n", ++ ((dimmInfo.dimmAttributes) >> 2) & 0x3); ++ ++ if (dimmInfo.dimmAttributes & BIT4) ++ mvOsOutput(" FET Switch External Enabled: Yes \n"); ++ else ++ mvOsOutput(" FET Switch External Enabled: No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT6) ++ mvOsOutput(" Analysis probe installed: Yes \n"); ++ else ++ mvOsOutput(" Analysis probe installed: No \n"); ++ } ++ ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 22: /* Suported AutoPreCharge */ ++ mvOsOutput("\nModul Attributes (SPD Byte 22): \n"); ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ if ( spdRawData[i] & BIT0 ) ++ mvOsOutput(" Early Ras Precharge: Yes \n"); ++ else ++ mvOsOutput(" Early Ras Precharge: No \n"); ++ ++ if ( spdRawData[i] & BIT1 ) ++ mvOsOutput(" AutoPreCharge: Yes \n"); ++ else ++ mvOsOutput(" AutoPreCharge: No \n"); ++ ++ if ( spdRawData[i] & BIT2 ) ++ mvOsOutput(" Precharge All: Yes \n"); ++ else ++ mvOsOutput(" Precharge All: No \n"); ++ ++ if ( spdRawData[i] & BIT3 ) ++ mvOsOutput(" Write 1/ReadBurst: Yes \n"); ++ else ++ mvOsOutput(" Write 1/ReadBurst: No \n"); ++ ++ if ( spdRawData[i] & BIT4 ) ++ mvOsOutput(" lower VCC tolerance: 5%%\n"); ++ else ++ mvOsOutput(" lower VCC tolerance: 10%%\n"); ++ ++ if ( spdRawData[i] & BIT5 ) ++ mvOsOutput(" upper VCC tolerance: 5%%\n"); ++ else ++ mvOsOutput(" upper VCC tolerance: 10%%\n"); ++ } ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) ++ { ++ if ( spdRawData[i] & BIT0 ) ++ mvOsOutput(" Supports Weak Driver: Yes \n"); ++ else ++ mvOsOutput(" Supports Weak Driver: No \n"); ++ ++ if ( !(spdRawData[i] & BIT4) ) ++ mvOsOutput(" lower VCC tolerance: 0.2V\n"); ++ ++ if ( !(spdRawData[i] & BIT5) ) ++ mvOsOutput(" upper VCC tolerance: 0.2V\n"); ++ ++ if ( spdRawData[i] & BIT6 ) ++ mvOsOutput(" Concurrent Auto Preharge: Yes \n"); ++ else ++ mvOsOutput(" Concurrent Auto Preharge: No \n"); ++ ++ if ( spdRawData[i] & BIT7 ) ++ mvOsOutput(" Supports Fast AP: Yes \n"); ++ else ++ mvOsOutput(" Supports Fast AP: No \n"); ++ } ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) ++ { ++ if ( spdRawData[i] & BIT0 ) ++ mvOsOutput(" Supports Weak Driver: Yes \n"); ++ else ++ mvOsOutput(" Supports Weak Driver: No \n"); ++ } ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 23: ++ /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */ ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ rightOfPoint = (spdRawData[i] & 0x0f) * 10; ++ ++ /* DDR2 addition of right of point */ ++ if ((spdRawData[i] & 0x0f) == 0xA) ++ { ++ rightOfPoint = 25; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xB) ++ { ++ rightOfPoint = 33; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xC) ++ { ++ rightOfPoint = 66; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xD) ++ { ++ rightOfPoint = 75; ++ } ++ ++ mvOsOutput("Minimum Cycle Time At 2nd highest CasLatancy" ++ "(0 = Not supported): %d.%d [ns]\n", ++ leftOfPoint, rightOfPoint ); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 24: /* Clock To Data Out 2nd highest Cas Latency Value*/ ++ div = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? 10:100; ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = time_tmp / div; ++ rightOfPoint = time_tmp % div; ++ mvOsOutput("Clock To Data Out (2nd CL value): %d.%d [ns]\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 25: ++ /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ leftOfPoint = (spdRawData[i] & 0xfc) >> 2; ++ rightOfPoint = (spdRawData[i] & 0x3) * 25; ++ } ++ else /* DDR1 or DDR2 */ ++ { ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ rightOfPoint = (spdRawData[i] & 0x0f) * 10; ++ ++ /* DDR2 addition of right of point */ ++ if ((spdRawData[i] & 0x0f) == 0xA) ++ { ++ rightOfPoint = 25; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xB) ++ { ++ rightOfPoint = 33; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xC) ++ { ++ rightOfPoint = 66; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xD) ++ { ++ rightOfPoint = 75; ++ } ++ } ++ mvOsOutput("Minimum Cycle Time At 3rd highest CasLatancy" ++ "(0 = Not supported): %d.%d [ns]\n", ++ leftOfPoint, rightOfPoint ); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 26: /* Clock To Data Out 3rd highest Cas Latency Value*/ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ leftOfPoint = (spdRawData[i] & 0xfc) >> 2; ++ rightOfPoint = (spdRawData[i] & 0x3) * 25; ++ } ++ else /* DDR1 or DDR2 */ ++ { ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = 0; ++ rightOfPoint = time_tmp; ++ } ++ mvOsOutput("Clock To Data Out (3rd CL value): %d.%2d[ns]\n", ++ leftOfPoint, rightOfPoint ); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 27: /* Minimum Row Precharge Time */ ++ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; ++ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? ++ 0xff : 0xfc; ++ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? ++ 0x00 : 0x03; ++ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); ++ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; ++ temp = ((leftOfPoint*100) + rightOfPoint);/* in 10ps Intervals*/ ++ trp_clocks = (temp + (busClkPs-1)) / busClkPs; ++ mvOsOutput("Minimum Row Precharge Time [ns]: %d.%d = " ++ "in Clk cycles %d\n", ++ leftOfPoint, rightOfPoint, trp_clocks); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 28: /* Minimum Row Active to Row Active Time */ ++ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; ++ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? ++ 0xff : 0xfc; ++ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? ++ 0x00 : 0x03; ++ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); ++ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; ++ temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ ++ trrd_clocks = (temp + (busClkPs-1)) / busClkPs; ++ mvOsOutput("Minimum Row Active -To- Row Active Delay [ns]: " ++ "%d.%d = in Clk cycles %d\n", ++ leftOfPoint, rightOfPoint, trp_clocks); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 29: /* Minimum Ras-To-Cas Delay */ ++ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; ++ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? ++ 0xff : 0xfc; ++ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? ++ 0x00 : 0x03; ++ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); ++ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; ++ temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ ++ trcd_clocks = (temp + (busClkPs-1) )/ busClkPs; ++ mvOsOutput("Minimum Ras-To-Cas Delay [ns]: %d.%d = " ++ "in Clk cycles %d\n", ++ leftOfPoint, rightOfPoint, trp_clocks); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 30: /* Minimum Ras Pulse Width */ ++ tras_clocks = (cas2ps(spdRawData[i])+(busClkPs-1)) / busClkPs; ++ mvOsOutput("Minimum Ras Pulse Width [ns]: %d = " ++ "in Clk cycles %d\n", spdRawData[i], tras_clocks); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 31: /* Module Bank Density */ ++ mvOsOutput("Module Bank Density (more than 1= Multisize-Module):"); ++ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ if (dimmInfo.dimmBankDensity & BIT0) ++ mvOsOutput("1GB, "); ++ if (dimmInfo.dimmBankDensity & BIT1) ++ mvOsOutput("8MB, "); ++ if (dimmInfo.dimmBankDensity & BIT2) ++ mvOsOutput("16MB, "); ++ if (dimmInfo.dimmBankDensity & BIT3) ++ mvOsOutput("32MB, "); ++ if (dimmInfo.dimmBankDensity & BIT4) ++ mvOsOutput("64MB, "); ++ if (dimmInfo.dimmBankDensity & BIT5) ++ mvOsOutput("128MB, "); ++ if (dimmInfo.dimmBankDensity & BIT6) ++ mvOsOutput("256MB, "); ++ if (dimmInfo.dimmBankDensity & BIT7) ++ mvOsOutput("512MB, "); ++ } ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) ++ { ++ if (dimmInfo.dimmBankDensity & BIT0) ++ mvOsOutput("1GB, "); ++ if (dimmInfo.dimmBankDensity & BIT1) ++ mvOsOutput("2GB, "); ++ if (dimmInfo.dimmBankDensity & BIT2) ++ mvOsOutput("16MB, "); ++ if (dimmInfo.dimmBankDensity & BIT3) ++ mvOsOutput("32MB, "); ++ if (dimmInfo.dimmBankDensity & BIT4) ++ mvOsOutput("64MB, "); ++ if (dimmInfo.dimmBankDensity & BIT5) ++ mvOsOutput("128MB, "); ++ if (dimmInfo.dimmBankDensity & BIT6) ++ mvOsOutput("256MB, "); ++ if (dimmInfo.dimmBankDensity & BIT7) ++ mvOsOutput("512MB, "); ++ } ++ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ ++ { ++ if (dimmInfo.dimmBankDensity & BIT0) ++ mvOsOutput("1GB, "); ++ if (dimmInfo.dimmBankDensity & BIT1) ++ mvOsOutput("2GB, "); ++ if (dimmInfo.dimmBankDensity & BIT2) ++ mvOsOutput("4GB, "); ++ if (dimmInfo.dimmBankDensity & BIT3) ++ mvOsOutput("8GB, "); ++ if (dimmInfo.dimmBankDensity & BIT4) ++ mvOsOutput("16GB, "); ++ if (dimmInfo.dimmBankDensity & BIT5) ++ mvOsOutput("128MB, "); ++ if (dimmInfo.dimmBankDensity & BIT6) ++ mvOsOutput("256MB, "); ++ if (dimmInfo.dimmBankDensity & BIT7) ++ mvOsOutput("512MB, "); ++ } ++ mvOsOutput("\n"); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 32: /* Address And Command Setup Time (measured in ns/1000) */ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ rightOfPoint = (spdRawData[i] & 0x0f); ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ if(leftOfPoint > 7) ++ { ++ leftOfPoint *= -1; ++ } ++ } ++ else /* DDR1 or DDR2 */ ++ { ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = time_tmp / 100; ++ rightOfPoint = time_tmp % 100; ++ } ++ mvOsOutput("Address And Command Setup Time [ns]: %d.%d\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 33: /* Address And Command Hold Time */ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ rightOfPoint = (spdRawData[i] & 0x0f); ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ if(leftOfPoint > 7) ++ { ++ leftOfPoint *= -1; ++ } ++ } ++ else /* DDR1 or DDR2 */ ++ { ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = time_tmp / 100; ++ rightOfPoint = time_tmp % 100; ++ } ++ mvOsOutput("Address And Command Hold Time [ns]: %d.%d\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 34: /* Data Input Setup Time */ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ rightOfPoint = (spdRawData[i] & 0x0f); ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ if(leftOfPoint > 7) ++ { ++ leftOfPoint *= -1; ++ } ++ } ++ else /* DDR1 or DDR2 */ ++ { ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = time_tmp / 100; ++ rightOfPoint = time_tmp % 100; ++ } ++ mvOsOutput("Data Input Setup Time [ns]: %d.%d\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 35: /* Data Input Hold Time */ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ rightOfPoint = (spdRawData[i] & 0x0f); ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ if(leftOfPoint > 7) ++ { ++ leftOfPoint *= -1; ++ } ++ } ++ else /* DDR1 or DDR2 */ ++ { ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = time_tmp / 100; ++ rightOfPoint = time_tmp % 100; ++ } ++ mvOsOutput("Data Input Hold Time [ns]: %d.%d\n\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 36: /* Relevant for DDR2 only: Write Recovery Time */ ++ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> 2); ++ rightOfPoint = (spdRawData[i] & maskRightOfPoint) * 25; ++ mvOsOutput("Write Recovery Time [ns]: %d.%d\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ } ++ ++} ++ ++ ++/* ++ * translate ns.ns/10 coding of SPD timing values ++ * into ps unit values ++ */ ++/******************************************************************************* ++* cas2ps - Translate x.y ns parameter to pico-seconds values ++* ++* DESCRIPTION: ++* This function translates x.y nano seconds to its value in pico seconds. ++* For example 3.75ns will return 3750. ++* ++* INPUT: ++* spd_byte - DIMM SPD byte. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* value in pico seconds. ++* ++*******************************************************************************/ ++static MV_U32 cas2ps(MV_U8 spd_byte) ++{ ++ MV_U32 ns, ns10; ++ ++ /* isolate upper nibble */ ++ ns = (spd_byte >> 4) & 0x0F; ++ /* isolate lower nibble */ ++ ns10 = (spd_byte & 0x0F); ++ ++ if( ns10 < 10 ) { ++ ns10 *= 10; ++ } ++ else if( ns10 == 10 ) ++ ns10 = 25; ++ else if( ns10 == 11 ) ++ ns10 = 33; ++ else if( ns10 == 12 ) ++ ns10 = 66; ++ else if( ns10 == 13 ) ++ ns10 = 75; ++ else ++ { ++ mvOsOutput("cas2ps Err. unsupported cycle time.\n"); ++ } ++ ++ return (ns*1000 + ns10*10); ++} ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,192 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvDram ++#define __INCmvDram ++ ++#include "ddr2/mvDramIf.h" ++#include "twsi/mvTwsi.h" ++ ++#define MAX_DIMM_NUM 2 ++#define SPD_SIZE 128 ++ ++/* Dimm spd offsets */ ++#define DIMM_MEM_TYPE 2 ++#define DIMM_ROW_NUM 3 ++#define DIMM_COL_NUM 4 ++#define DIMM_MODULE_BANK_NUM 5 ++#define DIMM_DATA_WIDTH 6 ++#define DIMM_VOLT_IF 8 ++#define DIMM_MIN_CC_AT_MAX_CAS 9 ++#define DIMM_ERR_CHECK_TYPE 11 ++#define DIMM_REFRESH_INTERVAL 12 ++#define DIMM_SDRAM_WIDTH 13 ++#define DIMM_ERR_CHECK_DATA_WIDTH 14 ++#define DIMM_MIN_CLK_DEL 15 ++#define DIMM_BURST_LEN_SUP 16 ++#define DIMM_DEV_BANK_NUM 17 ++#define DIMM_SUP_CAL 18 ++#define DIMM_DDR2_TYPE_INFORMATION 20 /* DDR2 only */ ++#define DIMM_BUF_ADDR_CONT_IN 21 ++#define DIMM_MIN_CC_AT_MAX_CAS_MINUS1 23 ++#define DIMM_MIN_CC_AT_MAX_CAS_MINUS2 25 ++#define DIMM_MIN_ROW_PRECHARGE_TIME 27 ++#define DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE 28 ++#define DIMM_MIN_RAS_TO_CAS_DELAY 29 ++#define DIMM_MIN_RAS_PULSE_WIDTH 30 ++#define DIMM_BANK_DENSITY 31 ++#define DIMM_MIN_WRITE_RECOVERY_TIME 36 ++#define DIMM_MIN_WRITE_TO_READ_CMD_DELAY 37 ++#define DIMM_MIN_READ_TO_PRECH_CMD_DELAY 38 ++#define DIMM_MIN_REFRESH_TO_ACTIVATE_CMD 42 ++#define DIMM_SPD_VERSION 62 ++ ++/* Dimm Memory Type values */ ++#define DIMM_MEM_TYPE_SDRAM 0x4 ++#define DIMM_MEM_TYPE_DDR1 0x7 ++#define DIMM_MEM_TYPE_DDR2 0x8 ++ ++#define DIMM_MODULE_MANU_OFFS 64 ++#define DIMM_MODULE_MANU_SIZE 8 ++#define DIMM_MODULE_VEN_OFFS 73 ++#define DIMM_MODULE_VEN_SIZE 25 ++#define DIMM_MODULE_ID_OFFS 99 ++#define DIMM_MODULE_ID_SIZE 18 ++ ++/* enumeration for voltage levels. */ ++typedef enum _mvDimmVoltageIf ++{ ++ TTL_5V_TOLERANT, ++ LVTTL, ++ HSTL_1_5V, ++ SSTL_3_3V, ++ SSTL_2_5V, ++ VOLTAGE_UNKNOWN, ++} MV_DIMM_VOLTAGE_IF; ++ ++ ++/* enumaration for SDRAM CAS Latencies. */ ++typedef enum _mvDimmSdramCas ++{ ++ SD_CL_1 =1, ++ SD_CL_2, ++ SD_CL_3, ++ SD_CL_4, ++ SD_CL_5, ++ SD_CL_6, ++ SD_CL_7, ++ SD_FAULT ++}MV_DIMM_SDRAM_CAS; ++ ++ ++/* DIMM information structure */ ++typedef struct _mvDimmInfo ++{ ++ MV_MEMORY_TYPE memoryType; /* DDR or SDRAM */ ++ ++ MV_U8 spdRawData[SPD_SIZE]; /* Content of SPD-EEPROM copied 1:1 */ ++ ++ /* DIMM dimensions */ ++ MV_U32 numOfRowAddr; ++ MV_U32 numOfColAddr; ++ MV_U32 numOfModuleBanks; ++ MV_U32 dataWidth; ++ MV_U32 errorCheckType; /* ECC , PARITY..*/ ++ MV_U32 sdramWidth; /* 4,8,16 or 32 */ ++ MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ ++ MV_U32 burstLengthSupported; ++ MV_U32 numOfBanksOnEachDevice; ++ MV_U32 suportedCasLatencies; ++ MV_U32 refreshInterval; ++ MV_U32 dimmBankDensity; ++ MV_U32 dimmTypeInfo; /* DDR2 only */ ++ MV_U32 dimmAttributes; ++ ++ /* DIMM timing parameters */ ++ MV_U32 minCycleTimeAtMaxCasLatPs; ++ MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; ++ MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; ++ MV_U32 minRowPrechargeTime; ++ MV_U32 minRowActiveToRowActive; ++ MV_U32 minRasToCasDelay; ++ MV_U32 minRasPulseWidth; ++ MV_U32 minWriteRecoveryTime; /* DDR2 only */ ++ MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ ++ MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ ++ MV_U32 minRefreshToActiveCmd; /* DDR2 only */ ++ ++ /* Parameters calculated from the extracted DIMM information */ ++ MV_U32 size; /* 16,64,128,256 or 512 MByte in MB units */ ++ MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit in MB units */ ++ MV_U32 numberOfDevices; ++ ++} MV_DIMM_INFO; ++ ++ ++MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo); ++MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo); ++MV_VOID dimmSpdPrint(MV_U32 dimmNum); ++MV_STATUS dimmSpdCpy(MV_VOID); ++ ++#endif /* __INCmvDram */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEth.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEth.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEth.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEth.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,2952 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++/******************************************************************************* ++* mvEth.c - Marvell's Gigabit Ethernet controller low level driver ++* ++* DESCRIPTION: ++* This file introduce OS independent APIs to Marvell's Gigabit Ethernet ++* controller. This Gigabit Ethernet Controller driver API controls ++* 1) Operations (i.e. port Init, Finish, Up, Down, PhyReset etc'). ++* 2) Data flow (i.e. port Send, Receive etc'). ++* 3) MAC Filtering functions (ethSetMcastAddr, ethSetRxFilterMode, etc.) ++* 4) MIB counters support (ethReadMibCounter) ++* 5) Debug functions (ethPortRegs, ethPortCounters, ethPortQueues, etc.) ++* Each Gigabit Ethernet port is controlled via ETH_PORT_CTRL struct. ++* This struct includes configuration information as well as driver ++* internal data needed for its operations. ++* ++* Supported Features: ++* - OS independent. All required OS services are implemented via external ++* OS dependent components (like osLayer or ethOsg) ++* - The user is free from Rx/Tx queue managing. ++* - Simple Gigabit Ethernet port operation API. ++* - Simple Gigabit Ethernet port data flow API. ++* - Data flow and operation API support per queue functionality. ++* - Support cached descriptors for better performance. ++* - PHY access and control API. ++* - Port Configuration API. ++* - Full control over Special and Other Multicast MAC tables. ++* ++*******************************************************************************/ ++/* includes */ ++#include "mvTypes.h" ++#include "mv802_3.h" ++#include "mvDebug.h" ++#include "mvCommon.h" ++#include "mvOs.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "eth-phy/mvEthPhy.h" ++#include "eth/mvEth.h" ++#include "eth/gbe/mvEthGbe.h" ++#include "cpu/mvCpu.h" ++ ++#ifdef INCLUDE_SYNC_BARR ++#include "sys/mvCpuIf.h" ++#endif ++ ++#ifdef MV_RT_DEBUG ++# define ETH_DEBUG ++#endif ++ ++ ++/* locals */ ++MV_BOOL ethDescInSram; ++MV_BOOL ethDescSwCoher; ++ ++/* This array holds the control structure of each port */ ++ETH_PORT_CTRL* ethPortCtrl[MV_ETH_MAX_PORTS]; ++ ++/* Ethernet Port Local routines */ ++ ++static void ethInitRxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue); ++ ++static void ethInitTxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue); ++ ++static void ethSetUcastTable(int portNo, int queue); ++ ++static MV_BOOL ethSetUcastAddr (int ethPortNum, MV_U8 lastNibble, int queue); ++static MV_BOOL ethSetSpecialMcastAddr(int ethPortNum, MV_U8 lastByte, int queue); ++static MV_BOOL ethSetOtherMcastAddr(int ethPortNum, MV_U8 crc8, int queue); ++ ++static void ethFreeDescrMemory(ETH_PORT_CTRL* pEthPortCtrl, MV_BUF_INFO* pDescBuf); ++static MV_U8* ethAllocDescrMemory(ETH_PORT_CTRL* pEthPortCtrl, int size, ++ MV_ULONG* pPhysAddr, MV_U32 *memHandle); ++ ++static MV_U32 mvEthMruGet(MV_U32 maxRxPktSize); ++ ++static void mvEthPortSgmiiConfig(int port); ++ ++ ++ ++/******************************************************************************/ ++/* EthDrv Initialization functions */ ++/******************************************************************************/ ++ ++/******************************************************************************* ++* mvEthHalInit - Initialize the Giga Ethernet unit ++* ++* DESCRIPTION: ++* This function initialize the Giga Ethernet unit. ++* 1) Configure Address decode windows of the unit ++* 2) Set registers to HW default values. ++* 3) Clear and Disable interrupts ++* ++* INPUT: NONE ++* ++* RETURN: NONE ++* ++* NOTE: this function is called once in the boot process. ++*******************************************************************************/ ++void mvEthHalInit(void) ++{ ++ int port; ++ ++ /* Init static data structures */ ++ for (port=0; port 0) ++ { ++ isSram = MV_TRUE; ++ #if (INTEG_SRAM_COHER == MV_CACHE_COHER_SW) ++ isSwCoher = MV_TRUE; ++ #else ++ isSwCoher = MV_FALSE; ++ #endif ++ } ++#endif /* ETH_DESCR_IN_SRAM */ ++ ++ if(pIsSram != NULL) ++ *pIsSram = isSram; ++ ++ if(pIsSwCoher != NULL) ++ *pIsSwCoher = isSwCoher; ++} ++ ++ ++ ++/******************************************************************************/ ++/* Port Initialization functions */ ++/******************************************************************************/ ++ ++/******************************************************************************* ++* mvEthPortInit - Initialize the Ethernet port driver ++* ++* DESCRIPTION: ++* This function initialize the ethernet port. ++* 1) Allocate and initialize internal port Control structure. ++* 2) Create RX and TX descriptor rings for default RX and TX queues ++* 3) Disable RX and TX operations, clear cause registers and ++* mask all interrupts. ++* 4) Set all registers to default values and clean all MAC tables. ++* ++* INPUT: ++* int portNo - Ethernet port number ++* ETH_PORT_INIT *pEthPortInit - Ethernet port init structure ++* ++* RETURN: ++* void* - ethernet port handler, that should be passed to the most other ++* functions dealing with this port. ++* ++* NOTE: This function is called once per port when loading the eth module. ++*******************************************************************************/ ++void* mvEthPortInit(int portNo, MV_ETH_PORT_INIT *pEthPortInit) ++{ ++ int queue, descSize; ++ ETH_PORT_CTRL* pPortCtrl; ++ ++ /* Check validity of parameters */ ++ if( (portNo >= (int)mvCtrlEthMaxPortGet()) || ++ (pEthPortInit->rxDefQ >= MV_ETH_RX_Q_NUM) || ++ (pEthPortInit->maxRxPktSize < 1518) ) ++ { ++ mvOsPrintf("EthPort #%d: Bad initialization parameters\n", portNo); ++ return NULL; ++ } ++ if( (pEthPortInit->rxDescrNum[pEthPortInit->rxDefQ]) == 0) ++ { ++ mvOsPrintf("EthPort #%d: rxDefQ (%d) must be created\n", ++ portNo, pEthPortInit->rxDefQ); ++ return NULL; ++ } ++ ++ pPortCtrl = (ETH_PORT_CTRL*)mvOsMalloc( sizeof(ETH_PORT_CTRL) ); ++ if(pPortCtrl == NULL) ++ { ++ mvOsPrintf("EthDrv: Can't allocate %dB for port #%d control structure!\n", ++ (int)sizeof(ETH_PORT_CTRL), portNo); ++ return NULL; ++ } ++ ++ memset(pPortCtrl, 0, sizeof(ETH_PORT_CTRL) ); ++ ethPortCtrl[portNo] = pPortCtrl; ++ ++ pPortCtrl->portState = MV_UNDEFINED_STATE; ++ ++ pPortCtrl->portNo = portNo; ++ ++ pPortCtrl->osHandle = pEthPortInit->osHandle; ++ ++ /* Copy Configuration parameters */ ++ pPortCtrl->portConfig.maxRxPktSize = pEthPortInit->maxRxPktSize; ++ pPortCtrl->portConfig.rxDefQ = pEthPortInit->rxDefQ; ++ pPortCtrl->portConfig.ejpMode = 0; ++ ++ for( queue=0; queuerxQueueConfig[queue].descrNum = pEthPortInit->rxDescrNum[queue]; ++ } ++ for( queue=0; queuetxQueueConfig[queue].descrNum = pEthPortInit->txDescrNum[queue]; ++ } ++ ++ mvEthPortDisable(pPortCtrl); ++ ++ /* Set the board information regarding PHY address */ ++ mvEthPhyAddrSet(pPortCtrl, mvBoardPhyAddrGet(portNo) ); ++ ++ /* Create all requested RX queues */ ++ for(queue=0; queuerxQueueConfig[queue].descrNum == 0) ++ continue; ++ ++ /* Allocate memory for RX descriptors */ ++ descSize = ((pPortCtrl->rxQueueConfig[queue].descrNum * ETH_RX_DESC_ALIGNED_SIZE) + ++ CPU_D_CACHE_LINE_SIZE); ++ ++ pPortCtrl->rxQueue[queue].descBuf.bufVirtPtr = ++ ethAllocDescrMemory(pPortCtrl, descSize, ++ &pPortCtrl->rxQueue[queue].descBuf.bufPhysAddr, ++ &pPortCtrl->rxQueue[queue].descBuf.memHandle); ++ pPortCtrl->rxQueue[queue].descBuf.bufSize = descSize; ++ if(pPortCtrl->rxQueue[queue].descBuf.bufVirtPtr == NULL) ++ { ++ mvOsPrintf("EthPort #%d, rxQ=%d: Can't allocate %d bytes in %s for %d RX descr\n", ++ pPortCtrl->portNo, queue, descSize, ++ ethDescInSram ? "SRAM" : "DRAM", ++ pPortCtrl->rxQueueConfig[queue].descrNum); ++ return NULL; ++ } ++ ++ ethInitRxDescRing(pPortCtrl, queue); ++ } ++ /* Create TX queues */ ++ for(queue=0; queuetxQueueConfig[queue].descrNum == 0) ++ continue; ++ ++ /* Allocate memory for TX descriptors */ ++ descSize = ((pPortCtrl->txQueueConfig[queue].descrNum * ETH_TX_DESC_ALIGNED_SIZE) + ++ CPU_D_CACHE_LINE_SIZE); ++ ++ pPortCtrl->txQueue[queue].descBuf.bufVirtPtr = ++ ethAllocDescrMemory(pPortCtrl, descSize, ++ &pPortCtrl->txQueue[queue].descBuf.bufPhysAddr, ++ &pPortCtrl->txQueue[queue].descBuf.memHandle); ++ pPortCtrl->txQueue[queue].descBuf.bufSize = descSize; ++ if(pPortCtrl->txQueue[queue].descBuf.bufVirtPtr == NULL) ++ { ++ mvOsPrintf("EthPort #%d, txQ=%d: Can't allocate %d bytes in %s for %d TX descr\n", ++ pPortCtrl->portNo, queue, descSize, ethDescInSram ? "SRAM" : "DRAM", ++ pPortCtrl->txQueueConfig[queue].descrNum); ++ return NULL; ++ } ++ ++ ethInitTxDescRing(pPortCtrl, queue); ++ } ++ mvEthDefaultsSet(pPortCtrl); ++ ++ pPortCtrl->portState = MV_IDLE; ++ return pPortCtrl; ++} ++ ++/******************************************************************************* ++* ethPortFinish - Finish the Ethernet port driver ++* ++* DESCRIPTION: ++* This function finish the ethernet port. ++* 1) Down ethernet port if needed. ++* 2) Delete RX and TX descriptor rings for all created RX and TX queues ++* 3) Free internal port Control structure. ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet port handler ++* ++* RETURN: NONE. ++* ++*******************************************************************************/ ++void mvEthPortFinish(void* pPortHndl) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ int queue, portNo = pPortCtrl->portNo; ++ ++ if(pPortCtrl->portState == MV_ACTIVE) ++ { ++ mvOsPrintf("ethPort #%d: Warning !!! Finish port in Active state\n", ++ portNo); ++ mvEthPortDisable(pPortHndl); ++ } ++ ++ /* Free all allocated RX queues */ ++ for(queue=0; queuerxQueue[queue].descBuf); ++ } ++ ++ /* Free all allocated TX queues */ ++ for(queue=0; queuetxQueue[queue].descBuf); ++ } ++ ++ /* Free port control structure */ ++ mvOsFree(pPortCtrl); ++ ++ ethPortCtrl[portNo] = NULL; ++} ++ ++/******************************************************************************* ++* mvEthDefaultsSet - Set defaults to the ethernet port ++* ++* DESCRIPTION: ++* This function set default values to the ethernet port. ++* 1) Clear Cause registers and Mask all interrupts ++* 2) Clear all MAC tables ++* 3) Set defaults to all registers ++* 4) Reset all created RX and TX descriptors ring ++* 5) Reset PHY ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet port handler ++* ++* RETURN: MV_STATUS ++* MV_OK - Success, Others - Failure ++* NOTE: ++* This function update all the port configuration except those set ++* Initialy by the OsGlue by MV_ETH_PORT_INIT. ++* This function can be called after portDown to return the port setting ++* to defaults. ++*******************************************************************************/ ++MV_STATUS mvEthDefaultsSet(void* pPortHndl) ++{ ++ int ethPortNo, queue; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ ETH_QUEUE_CTRL* pQueueCtrl; ++ MV_U32 txPrio; ++ MV_U32 portCfgReg, portCfgExtReg, portSerialCtrlReg, portSerialCtrl1Reg, portSdmaCfgReg; ++ MV_BOARD_MAC_SPEED boardMacCfg; ++ ++ ethPortNo = pPortCtrl->portNo; ++ ++ /* Clear Cause registers */ ++ MV_REG_WRITE(ETH_INTR_CAUSE_REG(ethPortNo),0); ++ MV_REG_WRITE(ETH_INTR_CAUSE_EXT_REG(ethPortNo),0); ++ ++ /* Mask all interrupts */ ++ MV_REG_WRITE(ETH_INTR_MASK_REG(ethPortNo),0); ++ MV_REG_WRITE(ETH_INTR_MASK_EXT_REG(ethPortNo),0); ++ ++ portCfgReg = PORT_CONFIG_VALUE; ++ portCfgExtReg = PORT_CONFIG_EXTEND_VALUE; ++ ++ boardMacCfg = mvBoardMacSpeedGet(ethPortNo); ++ ++ if(boardMacCfg == BOARD_MAC_SPEED_100M) ++ { ++ portSerialCtrlReg = PORT_SERIAL_CONTROL_100MB_FORCE_VALUE; ++ } ++ else if(boardMacCfg == BOARD_MAC_SPEED_1000M) ++ { ++ portSerialCtrlReg = PORT_SERIAL_CONTROL_1000MB_FORCE_VALUE; ++ } ++ else ++ { ++ portSerialCtrlReg = PORT_SERIAL_CONTROL_VALUE; ++ } ++ ++ /* build PORT_SDMA_CONFIG_REG */ ++ portSdmaCfgReg = ETH_TX_INTR_COAL_MASK(0); ++ portSdmaCfgReg |= ETH_TX_BURST_SIZE_MASK(ETH_BURST_SIZE_16_64BIT_VALUE); ++ ++#if ( (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WB) || \ ++ (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WT) ) ++ /* some devices have restricted RX burst size when using HW coherency */ ++ portSdmaCfgReg |= ETH_RX_BURST_SIZE_MASK(ETH_BURST_SIZE_4_64BIT_VALUE); ++#else ++ portSdmaCfgReg |= ETH_RX_BURST_SIZE_MASK(ETH_BURST_SIZE_16_64BIT_VALUE); ++#endif ++ ++#if defined(MV_CPU_BE) ++ /* big endian */ ++# if defined(MV_ARM) ++ portSdmaCfgReg |= (ETH_RX_NO_DATA_SWAP_MASK | ++ ETH_TX_NO_DATA_SWAP_MASK | ++ ETH_DESC_SWAP_MASK); ++# elif defined(MV_PPC) ++ portSdmaCfgReg |= (ETH_RX_DATA_SWAP_MASK | ++ ETH_TX_DATA_SWAP_MASK | ++ ETH_NO_DESC_SWAP_MASK); ++# else ++# error "Giga Ethernet Swap policy is not defined for the CPU_ARCH" ++# endif /* MV_ARM / MV_PPC */ ++ ++#else /* MV_CPU_LE */ ++ /* little endian */ ++ portSdmaCfgReg |= (ETH_RX_NO_DATA_SWAP_MASK | ++ ETH_TX_NO_DATA_SWAP_MASK | ++ ETH_NO_DESC_SWAP_MASK); ++#endif /* MV_CPU_BE / MV_CPU_LE */ ++ ++ pPortCtrl->portRxQueueCmdReg = 0; ++ pPortCtrl->portTxQueueCmdReg = 0; ++ ++#if (MV_ETH_VERSION >= 4) ++ if(pPortCtrl->portConfig.ejpMode == MV_TRUE) ++ { ++ MV_REG_WRITE(ETH_TXQ_CMD_1_REG(ethPortNo), ETH_TX_EJP_ENABLE_MASK); ++ } ++ else ++ { ++ MV_REG_WRITE(ETH_TXQ_CMD_1_REG(ethPortNo), 0) ++ } ++#endif /* (MV_ETH_VERSION >= 4) */ ++ ++ ethSetUcastTable(ethPortNo, -1); ++ mvEthSetSpecialMcastTable(ethPortNo, -1); ++ mvEthSetOtherMcastTable(ethPortNo, -1); ++ ++ portSerialCtrlReg &= ~ETH_MAX_RX_PACKET_SIZE_MASK; ++ ++ portSerialCtrlReg |= mvEthMruGet(pPortCtrl->portConfig.maxRxPktSize); ++ ++ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNo), portSerialCtrlReg); ++ ++ /* Update value of PortConfig register accordingly with all RxQueue types */ ++ pPortCtrl->portConfig.rxArpQ = pPortCtrl->portConfig.rxDefQ; ++ pPortCtrl->portConfig.rxBpduQ = pPortCtrl->portConfig.rxDefQ; ++ pPortCtrl->portConfig.rxTcpQ = pPortCtrl->portConfig.rxDefQ; ++ pPortCtrl->portConfig.rxUdpQ = pPortCtrl->portConfig.rxDefQ; ++ ++ portCfgReg &= ~ETH_DEF_RX_QUEUE_ALL_MASK; ++ portCfgReg |= ETH_DEF_RX_QUEUE_MASK(pPortCtrl->portConfig.rxDefQ); ++ ++ portCfgReg &= ~ETH_DEF_RX_ARP_QUEUE_ALL_MASK; ++ portCfgReg |= ETH_DEF_RX_ARP_QUEUE_MASK(pPortCtrl->portConfig.rxArpQ); ++ ++ portCfgReg &= ~ETH_DEF_RX_BPDU_QUEUE_ALL_MASK; ++ portCfgReg |= ETH_DEF_RX_BPDU_QUEUE_MASK(pPortCtrl->portConfig.rxBpduQ); ++ ++ portCfgReg &= ~ETH_DEF_RX_TCP_QUEUE_ALL_MASK; ++ portCfgReg |= ETH_DEF_RX_TCP_QUEUE_MASK(pPortCtrl->portConfig.rxTcpQ); ++ ++ portCfgReg &= ~ETH_DEF_RX_UDP_QUEUE_ALL_MASK; ++ portCfgReg |= ETH_DEF_RX_UDP_QUEUE_MASK(pPortCtrl->portConfig.rxUdpQ); ++ ++ /* Assignment of Tx CTRP of given queue */ ++ txPrio = 0; ++ ++ for(queue=0; queuetxQueue[queue]; ++ ++ if(pQueueCtrl->pFirstDescr != NULL) ++ { ++ ethResetTxDescRing(pPortCtrl, queue); ++ ++ MV_REG_WRITE(ETH_TXQ_TOKEN_COUNT_REG(ethPortNo, queue), ++ 0x3fffffff); ++ MV_REG_WRITE(ETH_TXQ_TOKEN_CFG_REG(ethPortNo, queue), ++ 0x03ffffff); ++ } ++ else ++ { ++ MV_REG_WRITE(ETH_TXQ_TOKEN_COUNT_REG(ethPortNo, queue), 0x0); ++ MV_REG_WRITE(ETH_TXQ_TOKEN_CFG_REG(ethPortNo, queue), 0x0); ++ } ++ } ++ ++ /* Assignment of Rx CRDP of given queue */ ++ for(queue=0; queueportNo; ++ ++ if( (pPortCtrl->portState != MV_ACTIVE) && ++ (pPortCtrl->portState != MV_PAUSED) ) ++ { ++ mvOsPrintf("ethDrv port%d: Unexpected port state %d\n", ++ ethPortNo, pPortCtrl->portState); ++ return MV_BAD_STATE; ++ } ++ ++ ethPortNo = pPortCtrl->portNo; ++ ++ /* Enable port RX. */ ++ MV_REG_WRITE(ETH_RX_QUEUE_COMMAND_REG(ethPortNo), pPortCtrl->portRxQueueCmdReg); ++ ++ /* Enable port TX. */ ++ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(ethPortNo)) = pPortCtrl->portTxQueueCmdReg; ++ ++ pPortCtrl->portState = MV_ACTIVE; ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* ethPortDown - Stop the Ethernet port activity. ++* ++* DESCRIPTION: ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet port handler ++* ++* RETURN: MV_STATUS ++* MV_OK - Success, Others - Failure. ++* ++* NOTE : used for port link down. ++*******************************************************************************/ ++MV_STATUS mvEthPortDown(void* pEthPortHndl) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; ++ int ethPortNum = pPortCtrl->portNo; ++ unsigned int regData; ++ volatile int uDelay, mDelay; ++ ++ /* Stop Rx port activity. Check port Rx activity. */ ++ regData = (MV_REG_READ(ETH_RX_QUEUE_COMMAND_REG(ethPortNum))) & ETH_RXQ_ENABLE_MASK; ++ if(regData != 0) ++ { ++ /* Issue stop command for active channels only */ ++ MV_REG_WRITE(ETH_RX_QUEUE_COMMAND_REG(ethPortNum), (regData << ETH_RXQ_DISABLE_OFFSET)); ++ } ++ ++ /* Stop Tx port activity. Check port Tx activity. */ ++ regData = (MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(ethPortNum))) & ETH_TXQ_ENABLE_MASK; ++ if(regData != 0) ++ { ++ /* Issue stop command for active channels only */ ++ MV_REG_WRITE(ETH_TX_QUEUE_COMMAND_REG(ethPortNum), ++ (regData << ETH_TXQ_DISABLE_OFFSET) ); ++ } ++ ++ /* Force link down */ ++/* ++ regData = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNum)); ++ regData &= ~(ETH_DO_NOT_FORCE_LINK_FAIL_MASK); ++ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNum), regData); ++*/ ++ /* Wait for all Rx activity to terminate. */ ++ mDelay = 0; ++ do ++ { ++ if(mDelay >= RX_DISABLE_TIMEOUT_MSEC) ++ { ++ mvOsPrintf("ethPort_%d: TIMEOUT for RX stopped !!! rxQueueCmd - 0x08%x\n", ++ ethPortNum, regData); ++ break; ++ } ++ mvOsDelay(1); ++ mDelay++; ++ ++ /* Check port RX Command register that all Rx queues are stopped */ ++ regData = MV_REG_READ(ETH_RX_QUEUE_COMMAND_REG(ethPortNum)); ++ } ++ while(regData & 0xFF); ++ ++ /* Wait for all Tx activity to terminate. */ ++ mDelay = 0; ++ do ++ { ++ if(mDelay >= TX_DISABLE_TIMEOUT_MSEC) ++ { ++ mvOsPrintf("ethPort_%d: TIMEOUT for TX stoped !!! txQueueCmd - 0x08%x\n", ++ ethPortNum, regData); ++ break; ++ } ++ mvOsDelay(1); ++ mDelay++; ++ ++ /* Check port TX Command register that all Tx queues are stopped */ ++ regData = MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(ethPortNum)); ++ } ++ while(regData & 0xFF); ++ ++ /* Double check to Verify that TX FIFO is Empty */ ++ mDelay = 0; ++ while(MV_TRUE) ++ { ++ do ++ { ++ if(mDelay >= TX_FIFO_EMPTY_TIMEOUT_MSEC) ++ { ++ mvOsPrintf("\n ethPort_%d: TIMEOUT for TX FIFO empty !!! portStatus - 0x08%x\n", ++ ethPortNum, regData); ++ break; ++ } ++ mvOsDelay(1); ++ mDelay++; ++ ++ regData = MV_REG_READ(ETH_PORT_STATUS_REG(ethPortNum)); ++ } ++ while( ((regData & ETH_TX_FIFO_EMPTY_MASK) == 0) || ++ ((regData & ETH_TX_IN_PROGRESS_MASK) != 0) ); ++ ++ if(mDelay >= TX_FIFO_EMPTY_TIMEOUT_MSEC) ++ break; ++ ++ /* Double check */ ++ regData = MV_REG_READ(ETH_PORT_STATUS_REG(ethPortNum)); ++ if( ((regData & ETH_TX_FIFO_EMPTY_MASK) != 0) && ++ ((regData & ETH_TX_IN_PROGRESS_MASK) == 0) ) ++ { ++ break; ++ } ++ else ++ mvOsPrintf("ethPort_%d: TX FIFO Empty double check failed. %d msec, portStatus=0x%x\n", ++ ethPortNum, mDelay, regData); ++ } ++ ++ /* Do NOT force link down */ ++/* ++ regData = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNum)); ++ regData |= (ETH_DO_NOT_FORCE_LINK_FAIL_MASK); ++ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNum), regData); ++*/ ++ /* Wait about 2500 tclk cycles */ ++ uDelay = (PORT_DISABLE_WAIT_TCLOCKS/(mvBoardTclkGet()/1000000)); ++ mvOsUDelay(uDelay); ++ ++ pPortCtrl->portState = MV_PAUSED; ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* ethPortEnable - Enable the Ethernet port and Start RX and TX. ++* ++* DESCRIPTION: ++* This routine enable the Ethernet port and Rx and Tx activity: ++* ++* Note: Each Rx and Tx queue descriptor's list must be initialized prior ++* to calling this function (use etherInitTxDescRing for Tx queues and ++* etherInitRxDescRing for Rx queues). ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet port handler ++* ++* RETURN: MV_STATUS ++* MV_OK - Success, Others - Failure. ++* ++* NOTE: main usage is to enable the port after ifconfig up. ++*******************************************************************************/ ++MV_STATUS mvEthPortEnable(void* pEthPortHndl) ++{ ++ int ethPortNo; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; ++ MV_U32 portSerialCtrlReg; ++ ++ ethPortNo = pPortCtrl->portNo; ++ ++ /* Enable port */ ++ portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNo)); ++ portSerialCtrlReg |= (ETH_DO_NOT_FORCE_LINK_FAIL_MASK | ETH_PORT_ENABLE_MASK); ++ ++ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNo), portSerialCtrlReg); ++ ++ mvEthMibCountersClear(pEthPortHndl); ++ ++ pPortCtrl->portState = MV_PAUSED; ++ ++ /* If Link is UP, Start RX and TX traffic */ ++ if( MV_REG_READ( ETH_PORT_STATUS_REG(ethPortNo) ) & ETH_LINK_UP_MASK) ++ return( mvEthPortUp(pEthPortHndl) ); ++ ++ return MV_NOT_READY; ++} ++ ++ ++/******************************************************************************* ++* mvEthPortDisable - Stop RX and TX activities and Disable the Ethernet port. ++* ++* DESCRIPTION: ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet port handler ++* ++* RETURN: MV_STATUS ++* MV_OK - Success, Others - Failure. ++* ++* NOTE: main usage is to disable the port after ifconfig down. ++*******************************************************************************/ ++MV_STATUS mvEthPortDisable(void* pEthPortHndl) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; ++ int ethPortNum = pPortCtrl->portNo; ++ unsigned int regData; ++ volatile int mvDelay; ++ ++ if(pPortCtrl->portState == MV_ACTIVE) ++ { ++ /* Stop RX and TX activities */ ++ mvEthPortDown(pEthPortHndl); ++ } ++ ++ /* Reset the Enable bit in the Serial Control Register */ ++ regData = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNum)); ++ regData &= ~(ETH_PORT_ENABLE_MASK); ++ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNum), regData); ++ ++ /* Wait about 2500 tclk cycles */ ++ mvDelay = (PORT_DISABLE_WAIT_TCLOCKS*(mvCpuPclkGet()/mvBoardTclkGet())); ++ for(mvDelay; mvDelay>0; mvDelay--); ++ ++ pPortCtrl->portState = MV_IDLE; ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvEthPortForceTxDone - Get next buffer from TX queue in spite of buffer ownership. ++* ++* DESCRIPTION: ++* This routine used to free buffers attached to the Tx ring and should ++* be called only when Giga Ethernet port is Down ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet Port handler. ++* int txQueue - Number of TX queue. ++* ++* OUTPUT: ++* MV_PKT_INFO *pPktInfo - Pointer to packet was sent. ++* ++* RETURN: ++* MV_EMPTY - There is no more buffers in this queue. ++* MV_OK - Buffer detached from the queue and pPktInfo structure ++* filled with relevant information. ++* ++*******************************************************************************/ ++MV_PKT_INFO* mvEthPortForceTxDone(void* pEthPortHndl, int txQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; ++ ETH_QUEUE_CTRL* pQueueCtrl; ++ MV_PKT_INFO* pPktInfo; ++ ETH_TX_DESC* pTxDesc; ++ int port = pPortCtrl->portNo; ++ ++ pQueueCtrl = &pPortCtrl->txQueue[txQueue]; ++ ++ while( (pQueueCtrl->pUsedDescr != pQueueCtrl->pCurrentDescr) || ++ (pQueueCtrl->resource == 0) ) ++ { ++ /* Free next descriptor */ ++ pQueueCtrl->resource++; ++ pTxDesc = (ETH_TX_DESC*)pQueueCtrl->pUsedDescr; ++ ++ /* pPktInfo is available only in descriptors which are last descriptors */ ++ pPktInfo = (MV_PKT_INFO*)pTxDesc->returnInfo; ++ if (pPktInfo) ++ pPktInfo->status = pTxDesc->cmdSts; ++ ++ pTxDesc->cmdSts = 0x0; ++ pTxDesc->returnInfo = 0x0; ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxDesc); ++ ++ pQueueCtrl->pUsedDescr = TX_NEXT_DESC_PTR(pTxDesc, pQueueCtrl); ++ ++ if (pPktInfo) ++ if (pPktInfo->status & ETH_TX_LAST_DESC_MASK) ++ return pPktInfo; ++ } ++ MV_REG_WRITE( ETH_TX_CUR_DESC_PTR_REG(port, txQueue), ++ (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); ++ return NULL; ++} ++ ++ ++ ++/******************************************************************************* ++* mvEthPortForceRx - Get next buffer from RX queue in spite of buffer ownership. ++* ++* DESCRIPTION: ++* This routine used to free buffers attached to the Rx ring and should ++* be called only when Giga Ethernet port is Down ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet Port handler. ++* int rxQueue - Number of Rx queue. ++* ++* OUTPUT: ++* MV_PKT_INFO *pPktInfo - Pointer to received packet. ++* ++* RETURN: ++* MV_EMPTY - There is no more buffers in this queue. ++* MV_OK - Buffer detached from the queue and pBufInfo structure ++* filled with relevant information. ++* ++*******************************************************************************/ ++MV_PKT_INFO* mvEthPortForceRx(void* pEthPortHndl, int rxQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; ++ ETH_QUEUE_CTRL* pQueueCtrl; ++ ETH_RX_DESC* pRxDesc; ++ MV_PKT_INFO* pPktInfo; ++ int port = pPortCtrl->portNo; ++ ++ pQueueCtrl = &pPortCtrl->rxQueue[rxQueue]; ++ ++ if(pQueueCtrl->resource == 0) ++ { ++ MV_REG_WRITE( ETH_RX_CUR_DESC_PTR_REG(port, rxQueue), ++ (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); ++ ++ return NULL; ++ } ++ /* Free next descriptor */ ++ pQueueCtrl->resource--; ++ pRxDesc = (ETH_RX_DESC*)pQueueCtrl->pCurrentDescr; ++ pPktInfo = (MV_PKT_INFO*)pRxDesc->returnInfo; ++ ++ pPktInfo->status = pRxDesc->cmdSts; ++ pRxDesc->cmdSts = 0x0; ++ pRxDesc->returnInfo = 0x0; ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxDesc); ++ ++ pQueueCtrl->pCurrentDescr = RX_NEXT_DESC_PTR(pRxDesc, pQueueCtrl); ++ return pPktInfo; ++} ++ ++ ++/******************************************************************************/ ++/* Port Configuration functions */ ++/******************************************************************************/ ++/******************************************************************************* ++* mvEthMruGet - Get MRU configuration for Max Rx packet size. ++* ++* INPUT: ++* MV_U32 maxRxPktSize - max packet size. ++* ++* RETURN: MV_U32 - MRU configuration. ++* ++*******************************************************************************/ ++static MV_U32 mvEthMruGet(MV_U32 maxRxPktSize) ++{ ++ MV_U32 portSerialCtrlReg = 0; ++ ++ if(maxRxPktSize > 9192) ++ portSerialCtrlReg |= ETH_MAX_RX_PACKET_9700BYTE; ++ else if(maxRxPktSize > 9022) ++ portSerialCtrlReg |= ETH_MAX_RX_PACKET_9192BYTE; ++ else if(maxRxPktSize > 1552) ++ portSerialCtrlReg |= ETH_MAX_RX_PACKET_9022BYTE; ++ else if(maxRxPktSize > 1522) ++ portSerialCtrlReg |= ETH_MAX_RX_PACKET_1552BYTE; ++ else if(maxRxPktSize > 1518) ++ portSerialCtrlReg |= ETH_MAX_RX_PACKET_1522BYTE; ++ else ++ portSerialCtrlReg |= ETH_MAX_RX_PACKET_1518BYTE; ++ ++ return portSerialCtrlReg; ++} ++ ++/******************************************************************************* ++* mvEthRxCoalSet - Sets coalescing interrupt mechanism on RX path ++* ++* DESCRIPTION: ++* This routine sets the RX coalescing interrupt mechanism parameter. ++* This parameter is a timeout counter, that counts in 64 tClk ++* chunks, that when timeout event occurs a maskable interrupt occurs. ++* The parameter is calculated using the tCLK frequency of the ++* MV-64xxx chip, and the required number is in micro seconds. ++* ++* INPUT: ++* void* pPortHndl - Ethernet Port handler. ++* MV_U32 uSec - Number of micro seconds between ++* RX interrupts ++* ++* RETURN: ++* None. ++* ++* COMMENT: ++* 1 sec - TCLK_RATE clocks ++* 1 uSec - TCLK_RATE / 1,000,000 clocks ++* ++* Register Value for N micro seconds - ((N * ( (TCLK_RATE / 1,000,000)) / 64) ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_U32 mvEthRxCoalSet (void* pPortHndl, MV_U32 uSec) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ MV_U32 coal = ((uSec * (mvBoardTclkGet() / 1000000)) / 64); ++ MV_U32 portSdmaCfgReg; ++ ++ portSdmaCfgReg = MV_REG_READ(ETH_SDMA_CONFIG_REG(pPortCtrl->portNo)); ++ portSdmaCfgReg &= ~ETH_RX_INTR_COAL_ALL_MASK; ++ ++ portSdmaCfgReg |= ETH_RX_INTR_COAL_MASK(coal); ++ ++#if (MV_ETH_VERSION >= 2) ++ /* Set additional bit if needed ETH_RX_INTR_COAL_MSB_BIT (25) */ ++ if(ETH_RX_INTR_COAL_MASK(coal) > ETH_RX_INTR_COAL_ALL_MASK) ++ portSdmaCfgReg |= ETH_RX_INTR_COAL_MSB_MASK; ++#endif /* MV_ETH_VERSION >= 2 */ ++ ++ MV_REG_WRITE (ETH_SDMA_CONFIG_REG(pPortCtrl->portNo), portSdmaCfgReg); ++ return coal; ++} ++ ++/******************************************************************************* ++* mvEthTxCoalSet - Sets coalescing interrupt mechanism on TX path ++* ++* DESCRIPTION: ++* This routine sets the TX coalescing interrupt mechanism parameter. ++* This parameter is a timeout counter, that counts in 64 tClk ++* chunks, that when timeout event occurs a maskable interrupt ++* occurs. ++* The parameter is calculated using the tCLK frequency of the ++* MV-64xxx chip, and the required number is in micro seconds. ++* ++* INPUT: ++* void* pPortHndl - Ethernet Port handler. ++* MV_U32 uSec - Number of micro seconds between ++* RX interrupts ++* ++* RETURN: ++* None. ++* ++* COMMENT: ++* 1 sec - TCLK_RATE clocks ++* 1 uSec - TCLK_RATE / 1,000,000 clocks ++* ++* Register Value for N micro seconds - ((N * ( (TCLK_RATE / 1,000,000)) / 64) ++* ++*******************************************************************************/ ++MV_U32 mvEthTxCoalSet(void* pPortHndl, MV_U32 uSec) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ MV_U32 coal = ((uSec * (mvBoardTclkGet() / 1000000)) / 64); ++ MV_U32 regVal; ++ ++ regVal = MV_REG_READ(ETH_TX_FIFO_URGENT_THRESH_REG(pPortCtrl->portNo)); ++ regVal &= ~ETH_TX_INTR_COAL_ALL_MASK; ++ regVal |= ETH_TX_INTR_COAL_MASK(coal); ++ ++ /* Set TX Coalescing mechanism */ ++ MV_REG_WRITE (ETH_TX_FIFO_URGENT_THRESH_REG(pPortCtrl->portNo), regVal); ++ return coal; ++} ++ ++/******************************************************************************* ++* mvEthCoalGet - Gets RX and TX coalescing values in micro seconds ++* ++* DESCRIPTION: ++* This routine gets the RX and TX coalescing interrupt values. ++* The parameter is calculated using the tCLK frequency of the ++* MV-64xxx chip, and the returned numbers are in micro seconds. ++* ++* INPUTs: ++* void* pPortHndl - Ethernet Port handler. ++* ++* OUTPUTs: ++* MV_U32* pRxCoal - Number of micro seconds between RX interrupts ++* MV_U32* pTxCoal - Number of micro seconds between TX interrupts ++* ++* RETURN: ++* MV_STATUS MV_OK - success ++* Others - failure. ++* ++* COMMENT: ++* 1 sec - TCLK_RATE clocks ++* 1 uSec - TCLK_RATE / 1,000,000 clocks ++* ++* Register Value for N micro seconds - ((N * ( (TCLK_RATE / 1,000,000)) / 64) ++* ++*******************************************************************************/ ++MV_STATUS mvEthCoalGet(void* pPortHndl, MV_U32* pRxCoal, MV_U32* pTxCoal) ++{ ++ MV_U32 regVal, coal, usec; ++ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ ++ /* get TX Coalescing */ ++ regVal = MV_REG_READ (ETH_TX_FIFO_URGENT_THRESH_REG(pPortCtrl->portNo)); ++ coal = ((regVal & ETH_TX_INTR_COAL_ALL_MASK) >> ETH_TX_INTR_COAL_OFFSET); ++ ++ usec = (coal * 64) / (mvBoardTclkGet() / 1000000); ++ if(pTxCoal != NULL) ++ *pTxCoal = usec; ++ ++ /* Get RX Coalescing */ ++ regVal = MV_REG_READ(ETH_SDMA_CONFIG_REG(pPortCtrl->portNo)); ++ coal = ((regVal & ETH_RX_INTR_COAL_ALL_MASK) >> ETH_RX_INTR_COAL_OFFSET); ++ ++#if (MV_ETH_VERSION >= 2) ++ if(regVal & ETH_RX_INTR_COAL_MSB_MASK) ++ { ++ /* Add MSB */ ++ coal |= (ETH_RX_INTR_COAL_ALL_MASK + 1); ++ } ++#endif /* MV_ETH_VERSION >= 2 */ ++ ++ usec = (coal * 64) / (mvBoardTclkGet() / 1000000); ++ if(pRxCoal != NULL) ++ *pRxCoal = usec; ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvEthMaxRxSizeSet - ++* ++* DESCRIPTION: ++* Change maximum receive size of the port. This configuration will take place ++* after next call of ethPortSetDefaults() function. ++* ++* INPUT: ++* ++* RETURN: ++*******************************************************************************/ ++MV_STATUS mvEthMaxRxSizeSet(void* pPortHndl, int maxRxSize) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ MV_U32 portSerialCtrlReg; ++ ++ if((maxRxSize < 1518) || (maxRxSize & ~ETH_RX_BUFFER_MASK)) ++ return MV_BAD_PARAM; ++ ++ pPortCtrl->portConfig.maxRxPktSize = maxRxSize; ++ ++ portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(pPortCtrl->portNo)); ++ portSerialCtrlReg &= ~ETH_MAX_RX_PACKET_SIZE_MASK; ++ portSerialCtrlReg |= mvEthMruGet(pPortCtrl->portConfig.maxRxPktSize); ++ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(pPortCtrl->portNo), portSerialCtrlReg); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************/ ++/* MAC Filtering functions */ ++/******************************************************************************/ ++ ++/******************************************************************************* ++* mvEthRxFilterModeSet - Configure Fitering mode of Ethernet port ++* ++* DESCRIPTION: ++* This routine used to free buffers attached to the Rx ring and should ++* be called only when Giga Ethernet port is Down ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet Port handler. ++* MV_BOOL isPromisc - Promiscous mode ++* MV_TRUE - accept all Broadcast, Multicast ++* and Unicast packets ++* MV_FALSE - accept all Broadcast, ++* specially added Multicast and ++* single Unicast packets ++* ++* RETURN: MV_STATUS MV_OK - Success, Other - Failure ++* ++*******************************************************************************/ ++MV_STATUS mvEthRxFilterModeSet(void* pEthPortHndl, MV_BOOL isPromisc) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; ++ int queue; ++ MV_U32 portCfgReg; ++ ++ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); ++ /* Set / Clear UPM bit in port configuration register */ ++ if(isPromisc) ++ { ++ /* Accept all multicast packets to RX default queue */ ++ queue = pPortCtrl->portConfig.rxDefQ; ++ portCfgReg |= ETH_UNICAST_PROMISCUOUS_MODE_MASK; ++ memset(pPortCtrl->mcastCount, 1, sizeof(pPortCtrl->mcastCount)); ++ MV_REG_WRITE(ETH_MAC_ADDR_LOW_REG(pPortCtrl->portNo),0xFFFF); ++ MV_REG_WRITE(ETH_MAC_ADDR_HIGH_REG(pPortCtrl->portNo),0xFFFFFFFF); ++ } ++ else ++ { ++ /* Reject all Multicast addresses */ ++ queue = -1; ++ portCfgReg &= ~ETH_UNICAST_PROMISCUOUS_MODE_MASK; ++ /* Clear all mcastCount */ ++ memset(pPortCtrl->mcastCount, 0, sizeof(pPortCtrl->mcastCount)); ++ } ++ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); ++ ++ /* Set Special Multicast and Other Multicast tables */ ++ mvEthSetSpecialMcastTable(pPortCtrl->portNo, queue); ++ mvEthSetOtherMcastTable(pPortCtrl->portNo, queue); ++ ethSetUcastTable(pPortCtrl->portNo, queue); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvEthMacAddrSet - This function Set the port Unicast address. ++* ++* DESCRIPTION: ++* This function Set the port Ethernet MAC address. This address ++* will be used to send Pause frames if enabled. Packets with this ++* address will be accepted and dispatched to default RX queue ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet port handler. ++* char* pAddr - Address to be set ++* ++* RETURN: MV_STATUS ++* MV_OK - Success, Other - Faulure ++* ++*******************************************************************************/ ++MV_STATUS mvEthMacAddrSet(void* pPortHndl, unsigned char *pAddr, int queue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ unsigned int macH; ++ unsigned int macL; ++ ++ if(queue >= MV_ETH_RX_Q_NUM) ++ { ++ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", queue); ++ return MV_BAD_PARAM; ++ } ++ ++ if(queue != -1) ++ { ++ macL = (pAddr[4] << 8) | (pAddr[5]); ++ macH = (pAddr[0] << 24)| (pAddr[1] << 16) | ++ (pAddr[2] << 8) | (pAddr[3] << 0); ++ ++ MV_REG_WRITE(ETH_MAC_ADDR_LOW_REG(pPortCtrl->portNo), macL); ++ MV_REG_WRITE(ETH_MAC_ADDR_HIGH_REG(pPortCtrl->portNo), macH); ++ } ++ ++ /* Accept frames of this address */ ++ ethSetUcastAddr(pPortCtrl->portNo, pAddr[5], queue); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvEthMacAddrGet - This function returns the port Unicast address. ++* ++* DESCRIPTION: ++* This function returns the port Ethernet MAC address. ++* ++* INPUT: ++* int portNo - Ethernet port number. ++* char* pAddr - Pointer where address will be written to ++* ++* RETURN: MV_STATUS ++* MV_OK - Success, Other - Faulure ++* ++*******************************************************************************/ ++MV_STATUS mvEthMacAddrGet(int portNo, unsigned char *pAddr) ++{ ++ unsigned int macH; ++ unsigned int macL; ++ ++ if(pAddr == NULL) ++ { ++ mvOsPrintf("mvEthMacAddrGet: NULL pointer.\n"); ++ return MV_BAD_PARAM; ++ } ++ ++ macH = MV_REG_READ(ETH_MAC_ADDR_HIGH_REG(portNo)); ++ macL = MV_REG_READ(ETH_MAC_ADDR_LOW_REG(portNo)); ++ pAddr[0] = (macH >> 24) & 0xff; ++ pAddr[1] = (macH >> 16) & 0xff; ++ pAddr[2] = (macH >> 8) & 0xff; ++ pAddr[3] = macH & 0xff; ++ pAddr[4] = (macL >> 8) & 0xff; ++ pAddr[5] = macL & 0xff; ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvEthMcastCrc8Get - Calculate CRC8 of MAC address. ++* ++* DESCRIPTION: ++* ++* INPUT: ++* MV_U8* pAddr - Address to calculate CRC-8 ++* ++* RETURN: MV_U8 - CRC-8 of this MAC address ++* ++*******************************************************************************/ ++MV_U8 mvEthMcastCrc8Get(MV_U8* pAddr) ++{ ++ unsigned int macH; ++ unsigned int macL; ++ int macArray[48]; ++ int crc[8]; ++ int i; ++ unsigned char crcResult = 0; ++ ++ /* Calculate CRC-8 out of the given address */ ++ macH = (pAddr[0] << 8) | (pAddr[1]); ++ macL = (pAddr[2] << 24)| (pAddr[3] << 16) | ++ (pAddr[4] << 8) | (pAddr[5] << 0); ++ ++ for(i=0; i<32; i++) ++ macArray[i] = (macL >> i) & 0x1; ++ ++ for(i=32; i<48; i++) ++ macArray[i] = (macH >> (i - 32)) & 0x1; ++ ++ crc[0] = macArray[45] ^ macArray[43] ^ macArray[40] ^ macArray[39] ^ ++ macArray[35] ^ macArray[34] ^ macArray[31] ^ macArray[30] ^ ++ macArray[28] ^ macArray[23] ^ macArray[21] ^ macArray[19] ^ ++ macArray[18] ^ macArray[16] ^ macArray[14] ^ macArray[12] ^ ++ macArray[8] ^ macArray[7] ^ macArray[6] ^ macArray[0]; ++ ++ crc[1] = macArray[46] ^ macArray[45] ^ macArray[44] ^ macArray[43] ^ ++ macArray[41] ^ macArray[39] ^ macArray[36] ^ macArray[34] ^ ++ macArray[32] ^ macArray[30] ^ macArray[29] ^ macArray[28] ^ ++ macArray[24] ^ macArray[23] ^ macArray[22] ^ macArray[21] ^ ++ macArray[20] ^ macArray[18] ^ macArray[17] ^ macArray[16] ^ ++ macArray[15] ^ macArray[14] ^ macArray[13] ^ macArray[12] ^ ++ macArray[9] ^ macArray[6] ^ macArray[1] ^ macArray[0]; ++ ++ crc[2] = macArray[47] ^ macArray[46] ^ macArray[44] ^ macArray[43] ^ ++ macArray[42] ^ macArray[39] ^ macArray[37] ^ macArray[34] ^ ++ macArray[33] ^ macArray[29] ^ macArray[28] ^ macArray[25] ^ ++ macArray[24] ^ macArray[22] ^ macArray[17] ^ macArray[15] ^ ++ macArray[13] ^ macArray[12] ^ macArray[10] ^ macArray[8] ^ ++ macArray[6] ^ macArray[2] ^ macArray[1] ^ macArray[0]; ++ ++ crc[3] = macArray[47] ^ macArray[45] ^ macArray[44] ^ macArray[43] ^ ++ macArray[40] ^ macArray[38] ^ macArray[35] ^ macArray[34] ^ ++ macArray[30] ^ macArray[29] ^ macArray[26] ^ macArray[25] ^ ++ macArray[23] ^ macArray[18] ^ macArray[16] ^ macArray[14] ^ ++ macArray[13] ^ macArray[11] ^ macArray[9] ^ macArray[7] ^ ++ macArray[3] ^ macArray[2] ^ macArray[1]; ++ ++ crc[4] = macArray[46] ^ macArray[45] ^ macArray[44] ^ macArray[41] ^ ++ macArray[39] ^ macArray[36] ^ macArray[35] ^ macArray[31] ^ ++ macArray[30] ^ macArray[27] ^ macArray[26] ^ macArray[24] ^ ++ macArray[19] ^ macArray[17] ^ macArray[15] ^ macArray[14] ^ ++ macArray[12] ^ macArray[10] ^ macArray[8] ^ macArray[4] ^ ++ macArray[3] ^ macArray[2]; ++ ++ crc[5] = macArray[47] ^ macArray[46] ^ macArray[45] ^ macArray[42] ^ ++ macArray[40] ^ macArray[37] ^ macArray[36] ^ macArray[32] ^ ++ macArray[31] ^ macArray[28] ^ macArray[27] ^ macArray[25] ^ ++ macArray[20] ^ macArray[18] ^ macArray[16] ^ macArray[15] ^ ++ macArray[13] ^ macArray[11] ^ macArray[9] ^ macArray[5] ^ ++ macArray[4] ^ macArray[3]; ++ ++ crc[6] = macArray[47] ^ macArray[46] ^ macArray[43] ^ macArray[41] ^ ++ macArray[38] ^ macArray[37] ^ macArray[33] ^ macArray[32] ^ ++ macArray[29] ^ macArray[28] ^ macArray[26] ^ macArray[21] ^ ++ macArray[19] ^ macArray[17] ^ macArray[16] ^ macArray[14] ^ ++ macArray[12] ^ macArray[10] ^ macArray[6] ^ macArray[5] ^ ++ macArray[4]; ++ ++ crc[7] = macArray[47] ^ macArray[44] ^ macArray[42] ^ macArray[39] ^ ++ macArray[38] ^ macArray[34] ^ macArray[33] ^ macArray[30] ^ ++ macArray[29] ^ macArray[27] ^ macArray[22] ^ macArray[20] ^ ++ macArray[18] ^ macArray[17] ^ macArray[15] ^ macArray[13] ^ ++ macArray[11] ^ macArray[7] ^ macArray[6] ^ macArray[5]; ++ ++ for(i=0; i<8; i++) ++ crcResult = crcResult | (crc[i] << i); ++ ++ return crcResult; ++} ++/******************************************************************************* ++* mvEthMcastAddrSet - Multicast address settings. ++* ++* DESCRIPTION: ++* This API controls the MV device MAC multicast support. ++* The MV device supports multicast using two tables: ++* 1) Special Multicast Table for MAC addresses of the form ++* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). ++* The MAC DA[7:0] bits are used as a pointer to the Special Multicast ++* Table entries in the DA-Filter table. ++* In this case, the function calls ethPortSmcAddr() routine to set the ++* Special Multicast Table. ++* 2) Other Multicast Table for multicast of another type. A CRC-8bit ++* is used as an index to the Other Multicast Table entries in the ++* DA-Filter table. ++* In this case, the function calculates the CRC-8bit value and calls ++* ethPortOmcAddr() routine to set the Other Multicast Table. ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet port handler. ++* MV_U8* pAddr - Address to be set ++* int queue - RX queue to capture all packets with this ++* Multicast MAC address. ++* -1 means delete this Multicast address. ++* ++* RETURN: MV_STATUS ++* MV_TRUE - Success, Other - Failure ++* ++*******************************************************************************/ ++MV_STATUS mvEthMcastAddrSet(void* pPortHndl, MV_U8 *pAddr, int queue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ unsigned char crcResult = 0; ++ ++ if(queue >= MV_ETH_RX_Q_NUM) ++ { ++ mvOsPrintf("ethPort %d: RX queue #%d is out of range\n", ++ pPortCtrl->portNo, queue); ++ return MV_BAD_PARAM; ++ } ++ ++ if((pAddr[0] == 0x01) && ++ (pAddr[1] == 0x00) && ++ (pAddr[2] == 0x5E) && ++ (pAddr[3] == 0x00) && ++ (pAddr[4] == 0x00)) ++ { ++ ethSetSpecialMcastAddr(pPortCtrl->portNo, pAddr[5], queue); ++ } ++ else ++ { ++ crcResult = mvEthMcastCrc8Get(pAddr); ++ ++ /* Check Add counter for this CRC value */ ++ if(queue == -1) ++ { ++ if(pPortCtrl->mcastCount[crcResult] == 0) ++ { ++ mvOsPrintf("ethPort #%d: No valid Mcast for crc8=0x%02x\n", ++ pPortCtrl->portNo, (unsigned)crcResult); ++ return MV_NO_SUCH; ++ } ++ ++ pPortCtrl->mcastCount[crcResult]--; ++ if(pPortCtrl->mcastCount[crcResult] != 0) ++ { ++ mvOsPrintf("ethPort #%d: After delete there are %d valid Mcast for crc8=0x%02x\n", ++ pPortCtrl->portNo, pPortCtrl->mcastCount[crcResult], ++ (unsigned)crcResult); ++ return MV_NO_CHANGE; ++ } ++ } ++ else ++ { ++ pPortCtrl->mcastCount[crcResult]++; ++ if(pPortCtrl->mcastCount[crcResult] > 1) ++ { ++ mvOsPrintf("ethPort #%d: Valid Mcast for crc8=0x%02x already exists\n", ++ pPortCtrl->portNo, (unsigned)crcResult); ++ return MV_NO_CHANGE; ++ } ++ } ++ ethSetOtherMcastAddr(pPortCtrl->portNo, crcResult, queue); ++ } ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* ethSetUcastTable - Unicast address settings. ++* ++* DESCRIPTION: ++* Set all entries in the Unicast MAC Table queue==-1 means reject all ++* INPUT: ++* ++* RETURN: ++* ++*******************************************************************************/ ++static void ethSetUcastTable(int portNo, int queue) ++{ ++ int offset; ++ MV_U32 regValue; ++ ++ if(queue == -1) ++ { ++ regValue = 0; ++ } ++ else ++ { ++ regValue = (((0x01 | (queue<<1)) << 0) | ++ ((0x01 | (queue<<1)) << 8) | ++ ((0x01 | (queue<<1)) << 16) | ++ ((0x01 | (queue<<1)) << 24)); ++ } ++ ++ for (offset=0; offset<=0xC; offset+=4) ++ MV_REG_WRITE((ETH_DA_FILTER_UCAST_BASE(portNo) + offset), regValue); ++} ++ ++/******************************************************************************* ++* mvEthSetSpecialMcastTable - Special Multicast address settings. ++* ++* DESCRIPTION: ++* Set all entries to the Special Multicast MAC Table. queue==-1 means reject all ++* INPUT: ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_VOID mvEthSetSpecialMcastTable(int portNo, int queue) ++{ ++ int offset; ++ MV_U32 regValue; ++ ++ if(queue == -1) ++ { ++ regValue = 0; ++ } ++ else ++ { ++ regValue = (((0x01 | (queue<<1)) << 0) | ++ ((0x01 | (queue<<1)) << 8) | ++ ((0x01 | (queue<<1)) << 16) | ++ ((0x01 | (queue<<1)) << 24)); ++ } ++ ++ for (offset=0; offset<=0xFC; offset+=4) ++ { ++ MV_REG_WRITE((ETH_DA_FILTER_SPEC_MCAST_BASE(portNo) + ++ offset), regValue); ++ } ++} ++ ++/******************************************************************************* ++* mvEthSetOtherMcastTable - Other Multicast address settings. ++* ++* DESCRIPTION: ++* Set all entries to the Other Multicast MAC Table. queue==-1 means reject all ++* INPUT: ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_VOID mvEthSetOtherMcastTable(int portNo, int queue) ++{ ++ int offset; ++ MV_U32 regValue; ++ ++ if(queue == -1) ++ { ++ regValue = 0; ++ } ++ else ++ { ++ regValue = (((0x01 | (queue<<1)) << 0) | ++ ((0x01 | (queue<<1)) << 8) | ++ ((0x01 | (queue<<1)) << 16) | ++ ((0x01 | (queue<<1)) << 24)); ++ } ++ ++ for (offset=0; offset<=0xFC; offset+=4) ++ { ++ MV_REG_WRITE((ETH_DA_FILTER_OTH_MCAST_BASE(portNo) + ++ offset), regValue); ++ } ++} ++ ++/******************************************************************************* ++* ethSetUcastAddr - This function Set the port unicast address table ++* ++* DESCRIPTION: ++* This function locates the proper entry in the Unicast table for the ++* specified MAC nibble and sets its properties according to function ++* parameters. ++* ++* INPUT: ++* int ethPortNum - Port number. ++* MV_U8 lastNibble - Unicast MAC Address last nibble. ++* int queue - Rx queue number for this MAC address. ++* value "-1" means remove address ++* ++* OUTPUT: ++* This function add/removes MAC addresses from the port unicast address ++* table. ++* ++* RETURN: ++* MV_TRUE is output succeeded. ++* MV_FALSE if option parameter is invalid. ++* ++*******************************************************************************/ ++static MV_BOOL ethSetUcastAddr(int portNo, MV_U8 lastNibble, int queue) ++{ ++ unsigned int unicastReg; ++ unsigned int tblOffset; ++ unsigned int regOffset; ++ ++ /* Locate the Unicast table entry */ ++ lastNibble = (0xf & lastNibble); ++ tblOffset = (lastNibble / 4) * 4; /* Register offset from unicast table base*/ ++ regOffset = lastNibble % 4; /* Entry offset within the above register */ ++ ++ ++ unicastReg = MV_REG_READ( (ETH_DA_FILTER_UCAST_BASE(portNo) + ++ tblOffset)); ++ ++ ++ if(queue == -1) ++ { ++ /* Clear accepts frame bit at specified unicast DA table entry */ ++ unicastReg &= ~(0xFF << (8*regOffset)); ++ } ++ else ++ { ++ unicastReg &= ~(0xFF << (8*regOffset)); ++ unicastReg |= ((0x01 | (queue<<1)) << (8*regOffset)); ++ } ++ MV_REG_WRITE( (ETH_DA_FILTER_UCAST_BASE(portNo) + tblOffset), ++ unicastReg); ++ ++ return MV_TRUE; ++} ++ ++/******************************************************************************* ++* ethSetSpecialMcastAddr - Special Multicast address settings. ++* ++* DESCRIPTION: ++* This routine controls the MV device special MAC multicast support. ++* The Special Multicast Table for MAC addresses supports MAC of the form ++* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). ++* The MAC DA[7:0] bits are used as a pointer to the Special Multicast ++* Table entries in the DA-Filter table. ++* This function set the Special Multicast Table appropriate entry ++* according to the argument given. ++* ++* INPUT: ++* int ethPortNum Port number. ++* unsigned char mcByte Multicast addr last byte (MAC DA[7:0] bits). ++* int queue Rx queue number for this MAC address. ++* int option 0 = Add, 1 = remove address. ++* ++* OUTPUT: ++* See description. ++* ++* RETURN: ++* MV_TRUE is output succeeded. ++* MV_FALSE if option parameter is invalid. ++* ++*******************************************************************************/ ++static MV_BOOL ethSetSpecialMcastAddr(int ethPortNum, MV_U8 lastByte, int queue) ++{ ++ unsigned int smcTableReg; ++ unsigned int tblOffset; ++ unsigned int regOffset; ++ ++ /* Locate the SMC table entry */ ++ tblOffset = (lastByte / 4); /* Register offset from SMC table base */ ++ regOffset = lastByte % 4; /* Entry offset within the above register */ ++ ++ smcTableReg = MV_REG_READ((ETH_DA_FILTER_SPEC_MCAST_BASE(ethPortNum) + tblOffset*4)); ++ ++ if(queue == -1) ++ { ++ /* Clear accepts frame bit at specified Special DA table entry */ ++ smcTableReg &= ~(0xFF << (8 * regOffset)); ++ } ++ else ++ { ++ smcTableReg &= ~(0xFF << (8 * regOffset)); ++ smcTableReg |= ((0x01 | (queue<<1)) << (8 * regOffset)); ++ } ++ MV_REG_WRITE((ETH_DA_FILTER_SPEC_MCAST_BASE(ethPortNum) + ++ tblOffset*4), smcTableReg); ++ ++ return MV_TRUE; ++} ++ ++/******************************************************************************* ++* ethSetOtherMcastAddr - Multicast address settings. ++* ++* DESCRIPTION: ++* This routine controls the MV device Other MAC multicast support. ++* The Other Multicast Table is used for multicast of another type. ++* A CRC-8bit is used as an index to the Other Multicast Table entries ++* in the DA-Filter table. ++* The function gets the CRC-8bit value from the calling routine and ++* set the Other Multicast Table appropriate entry according to the ++* CRC-8 argument given. ++* ++* INPUT: ++* int ethPortNum Port number. ++* MV_U8 crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1). ++* int queue Rx queue number for this MAC address. ++* ++* OUTPUT: ++* See description. ++* ++* RETURN: ++* MV_TRUE is output succeeded. ++* MV_FALSE if option parameter is invalid. ++* ++*******************************************************************************/ ++static MV_BOOL ethSetOtherMcastAddr(int ethPortNum, MV_U8 crc8, int queue) ++{ ++ unsigned int omcTableReg; ++ unsigned int tblOffset; ++ unsigned int regOffset; ++ ++ /* Locate the OMC table entry */ ++ tblOffset = (crc8 / 4) * 4; /* Register offset from OMC table base */ ++ regOffset = crc8 % 4; /* Entry offset within the above register */ ++ ++ omcTableReg = MV_REG_READ( ++ (ETH_DA_FILTER_OTH_MCAST_BASE(ethPortNum) + tblOffset)); ++ ++ if(queue == -1) ++ { ++ /* Clear accepts frame bit at specified Other DA table entry */ ++ omcTableReg &= ~(0xFF << (8 * regOffset)); ++ } ++ else ++ { ++ omcTableReg &= ~(0xFF << (8 * regOffset)); ++ omcTableReg |= ((0x01 | (queue<<1)) << (8 * regOffset)); ++ } ++ ++ MV_REG_WRITE((ETH_DA_FILTER_OTH_MCAST_BASE(ethPortNum) + tblOffset), ++ omcTableReg); ++ ++ return MV_TRUE; ++} ++ ++ ++/******************************************************************************/ ++/* MIB Counters functions */ ++/******************************************************************************/ ++ ++ ++/******************************************************************************* ++* mvEthMibCounterRead - Read a MIB counter ++* ++* DESCRIPTION: ++* This function reads a MIB counter of a specific ethernet port. ++* NOTE - Read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW or ++* ETH_MIB_GOOD_OCTETS_SENT_LOW counters will return 64 bits value, ++* so pHigh32 pointer should not be NULL in this case. ++* ++* INPUT: ++* int ethPortNum - Ethernet Port number. ++* unsigned int mibOffset - MIB counter offset. ++* ++* OUTPUT: ++* MV_U32* pHigh32 - pointer to place where 32 most significant bits ++* of the counter will be stored. ++* ++* RETURN: ++* 32 low sgnificant bits of MIB counter value. ++* ++*******************************************************************************/ ++MV_U32 mvEthMibCounterRead(void* pPortHandle, unsigned int mibOffset, ++ MV_U32* pHigh32) ++{ ++ int portNo; ++ MV_U32 valLow32, valHigh32; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ ++ portNo = pPortCtrl->portNo; ++ ++ valLow32 = MV_REG_READ(ETH_MIB_COUNTERS_BASE(portNo) + mibOffset); ++ ++ /* Implement FEr ETH. Erroneous Value when Reading the Upper 32-bits */ ++ /* of a 64-bit MIB Counter. */ ++ if( (mibOffset == ETH_MIB_GOOD_OCTETS_RECEIVED_LOW) || ++ (mibOffset == ETH_MIB_GOOD_OCTETS_SENT_LOW) ) ++ { ++ valHigh32 = MV_REG_READ(ETH_MIB_COUNTERS_BASE(portNo) + mibOffset + 4); ++ if(pHigh32 != NULL) ++ *pHigh32 = valHigh32; ++ } ++ return valLow32; ++} ++ ++/******************************************************************************* ++* mvEthMibCountersClear - Clear all MIB counters ++* ++* DESCRIPTION: ++* This function clears all MIB counters ++* ++* INPUT: ++* int ethPortNum - Ethernet Port number. ++* ++* ++* RETURN: void ++* ++*******************************************************************************/ ++void mvEthMibCountersClear(void* pPortHandle) ++{ ++ int i, portNo; ++ unsigned int dummy; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ ++ portNo = pPortCtrl->portNo; ++ ++ /* Perform dummy reads from MIB counters */ ++ for(i=ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i 0xFF) ++ { ++ mvOsPrintf("eth_%d: tos=0x%x is out of range\n", pPortCtrl->portNo, tos); ++ return -1; ++ } ++ regIdx = mvOsDivide(tos>>2, 10); ++ regOffs = mvOsReminder(tos>>2, 10); ++ ++ regValue = MV_REG_READ(ETH_DIFF_SERV_PRIO_REG(pPortCtrl->portNo, regIdx) ); ++ rxq = (regValue >> (regOffs*3)); ++ rxq &= 0x7; ++ ++ return rxq; ++} ++ ++/******************************************************************************* ++* mvEthTosToRxqSet - Map packets with special TOS value to special RX queue ++* ++* DESCRIPTION: ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* int tos - TOS value in the IP header of the packet ++* int rxq - RX Queue for packets with the configured TOS value ++* Negative value (-1) means no special processing for these packets, ++* so they will be processed as regular packets. ++* ++* RETURN: MV_STATUS ++*******************************************************************************/ ++MV_STATUS mvEthTosToRxqSet(void* pPortHandle, int tos, int rxq) ++{ ++ MV_U32 regValue; ++ int regIdx, regOffs; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ ++ if( (rxq < 0) || (rxq >= MV_ETH_RX_Q_NUM) ) ++ { ++ mvOsPrintf("eth_%d: RX queue #%d is out of range\n", pPortCtrl->portNo, rxq); ++ return MV_BAD_PARAM; ++ } ++ if(tos > 0xFF) ++ { ++ mvOsPrintf("eth_%d: tos=0x%x is out of range\n", pPortCtrl->portNo, tos); ++ return MV_BAD_PARAM; ++ } ++ regIdx = mvOsDivide(tos>>2, 10); ++ regOffs = mvOsReminder(tos>>2, 10); ++ ++ regValue = MV_REG_READ(ETH_DIFF_SERV_PRIO_REG(pPortCtrl->portNo, regIdx) ); ++ regValue &= ~(0x7 << (regOffs*3)); ++ regValue |= (rxq << (regOffs*3)); ++ ++ MV_REG_WRITE(ETH_DIFF_SERV_PRIO_REG(pPortCtrl->portNo, regIdx), regValue); ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvEthVlanPrioRxQueue - Configure RX queue to capture VLAN tagged packets with ++* special priority bits [0-2] ++* ++* DESCRIPTION: ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* int bpduQueue - Special queue to capture VLAN tagged packets with special ++* priority. ++* Negative value (-1) means no special processing for these packets, ++* so they will be processed as regular packets. ++* ++* RETURN: MV_STATUS ++* MV_OK - Success ++* MV_FAIL - Failed. ++* ++*******************************************************************************/ ++MV_STATUS mvEthVlanPrioRxQueue(void* pPortHandle, int vlanPrio, int vlanPrioQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ MV_U32 vlanPrioReg; ++ ++ if(vlanPrioQueue >= MV_ETH_RX_Q_NUM) ++ { ++ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", vlanPrioQueue); ++ return MV_BAD_PARAM; ++ } ++ if(vlanPrio >= 8) ++ { ++ mvOsPrintf("ethDrv: vlanPrio=%d is out of range\n", vlanPrio); ++ return MV_BAD_PARAM; ++ } ++ ++ vlanPrioReg = MV_REG_READ(ETH_VLAN_TAG_TO_PRIO_REG(pPortCtrl->portNo)); ++ vlanPrioReg &= ~(0x7 << (vlanPrio*3)); ++ vlanPrioReg |= (vlanPrioQueue << (vlanPrio*3)); ++ MV_REG_WRITE(ETH_VLAN_TAG_TO_PRIO_REG(pPortCtrl->portNo), vlanPrioReg); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvEthBpduRxQueue - Configure RX queue to capture BPDU packets. ++* ++* DESCRIPTION: ++* This function defines processing of BPDU packets. ++* BPDU packets can be accepted and captured to one of RX queues ++* or can be processing as regular Multicast packets. ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* int bpduQueue - Special queue to capture BPDU packets (DA is equal to ++* 01-80-C2-00-00-00 through 01-80-C2-00-00-FF, ++* except for the Flow-Control Pause packets). ++* Negative value (-1) means no special processing for BPDU, ++* packets so they will be processed as regular Multicast packets. ++* ++* RETURN: MV_STATUS ++* MV_OK - Success ++* MV_FAIL - Failed. ++* ++*******************************************************************************/ ++MV_STATUS mvEthBpduRxQueue(void* pPortHandle, int bpduQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ MV_U32 portCfgReg; ++ MV_U32 portCfgExtReg; ++ ++ if(bpduQueue >= MV_ETH_RX_Q_NUM) ++ { ++ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", bpduQueue); ++ return MV_BAD_PARAM; ++ } ++ ++ portCfgExtReg = MV_REG_READ(ETH_PORT_CONFIG_EXTEND_REG(pPortCtrl->portNo)); ++ ++ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); ++ if(bpduQueue >= 0) ++ { ++ pPortCtrl->portConfig.rxBpduQ = bpduQueue; ++ ++ portCfgReg &= ~ETH_DEF_RX_BPDU_QUEUE_ALL_MASK; ++ portCfgReg |= ETH_DEF_RX_BPDU_QUEUE_MASK(pPortCtrl->portConfig.rxBpduQ); ++ ++ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); ++ ++ portCfgExtReg |= ETH_CAPTURE_SPAN_BPDU_ENABLE_MASK; ++ } ++ else ++ { ++ pPortCtrl->portConfig.rxBpduQ = -1; ++ /* no special processing for BPDU packets */ ++ portCfgExtReg &= (~ETH_CAPTURE_SPAN_BPDU_ENABLE_MASK); ++ } ++ ++ MV_REG_WRITE(ETH_PORT_CONFIG_EXTEND_REG(pPortCtrl->portNo), portCfgExtReg); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvEthArpRxQueue - Configure RX queue to capture ARP packets. ++* ++* DESCRIPTION: ++* This function defines processing of ARP (type=0x0806) packets. ++* ARP packets can be accepted and captured to one of RX queues ++* or can be processed as other Broadcast packets. ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* int arpQueue - Special queue to capture ARP packets (type=0x806). ++* Negative value (-1) means discard ARP packets ++* ++* RETURN: MV_STATUS ++* MV_OK - Success ++* MV_FAIL - Failed. ++* ++*******************************************************************************/ ++MV_STATUS mvEthArpRxQueue(void* pPortHandle, int arpQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ MV_U32 portCfgReg; ++ ++ if(arpQueue >= MV_ETH_RX_Q_NUM) ++ { ++ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", arpQueue); ++ return MV_BAD_PARAM; ++ } ++ ++ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); ++ ++ if(arpQueue >= 0) ++ { ++ pPortCtrl->portConfig.rxArpQ = arpQueue; ++ portCfgReg &= ~ETH_DEF_RX_ARP_QUEUE_ALL_MASK; ++ portCfgReg |= ETH_DEF_RX_ARP_QUEUE_MASK(pPortCtrl->portConfig.rxArpQ); ++ ++ portCfgReg &= (~ETH_REJECT_ARP_BCAST_MASK); ++ } ++ else ++ { ++ pPortCtrl->portConfig.rxArpQ = -1; ++ portCfgReg |= ETH_REJECT_ARP_BCAST_MASK; ++ } ++ ++ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvEthTcpRxQueue - Configure RX queue to capture TCP packets. ++* ++* DESCRIPTION: ++* This function defines processing of TCP packets. ++* TCP packets can be accepted and captured to one of RX queues ++* or can be processed as regular Unicast packets. ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* int tcpQueue - Special queue to capture TCP packets. Value "-1" ++* means no special processing for TCP packets, ++* so they will be processed as regular ++* ++* RETURN: MV_STATUS ++* MV_OK - Success ++* MV_FAIL - Failed. ++* ++*******************************************************************************/ ++MV_STATUS mvEthTcpRxQueue(void* pPortHandle, int tcpQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ MV_U32 portCfgReg; ++ ++ if(tcpQueue >= MV_ETH_RX_Q_NUM) ++ { ++ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", tcpQueue); ++ return MV_BAD_PARAM; ++ } ++ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); ++ ++ if(tcpQueue >= 0) ++ { ++ pPortCtrl->portConfig.rxTcpQ = tcpQueue; ++ portCfgReg &= ~ETH_DEF_RX_TCP_QUEUE_ALL_MASK; ++ portCfgReg |= ETH_DEF_RX_TCP_QUEUE_MASK(pPortCtrl->portConfig.rxTcpQ); ++ ++ portCfgReg |= ETH_CAPTURE_TCP_FRAMES_ENABLE_MASK; ++ } ++ else ++ { ++ pPortCtrl->portConfig.rxTcpQ = -1; ++ portCfgReg &= (~ETH_CAPTURE_TCP_FRAMES_ENABLE_MASK); ++ } ++ ++ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvEthUdpRxQueue - Configure RX queue to capture UDP packets. ++* ++* DESCRIPTION: ++* This function defines processing of UDP packets. ++* TCP packets can be accepted and captured to one of RX queues ++* or can be processed as regular Unicast packets. ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* int udpQueue - Special queue to capture UDP packets. Value "-1" ++* means no special processing for UDP packets, ++* so they will be processed as regular ++* ++* RETURN: MV_STATUS ++* MV_OK - Success ++* MV_FAIL - Failed. ++* ++*******************************************************************************/ ++MV_STATUS mvEthUdpRxQueue(void* pPortHandle, int udpQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ MV_U32 portCfgReg; ++ ++ if(udpQueue >= MV_ETH_RX_Q_NUM) ++ { ++ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", udpQueue); ++ return MV_BAD_PARAM; ++ } ++ ++ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); ++ ++ if(udpQueue >= 0) ++ { ++ pPortCtrl->portConfig.rxUdpQ = udpQueue; ++ portCfgReg &= ~ETH_DEF_RX_UDP_QUEUE_ALL_MASK; ++ portCfgReg |= ETH_DEF_RX_UDP_QUEUE_MASK(pPortCtrl->portConfig.rxUdpQ); ++ ++ portCfgReg |= ETH_CAPTURE_UDP_FRAMES_ENABLE_MASK; ++ } ++ else ++ { ++ pPortCtrl->portConfig.rxUdpQ = -1; ++ portCfgReg &= ~ETH_CAPTURE_UDP_FRAMES_ENABLE_MASK; ++ } ++ ++ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************/ ++/* Speed, Duplex, FlowControl routines */ ++/******************************************************************************/ ++ ++/******************************************************************************* ++* mvEthSpeedDuplexSet - Set Speed and Duplex of the port. ++* ++* DESCRIPTION: ++* This function configure the port to work with desirable Duplex and Speed. ++* Changing of these parameters are allowed only when port is disabled. ++* This function disable the port if was enabled, change duplex and speed ++* and, enable the port back if needed. ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* ETH_PORT_SPEED speed - Speed of the port. ++* ETH_PORT_SPEED duplex - Duplex of the port. ++* ++* RETURN: MV_STATUS ++* MV_OK - Success ++* MV_OUT_OF_RANGE - Failed. Port is out of valid range ++* MV_NOT_FOUND - Failed. Port is not initialized. ++* MV_BAD_PARAM - Input parameters (speed/duplex) in conflict. ++* MV_BAD_VALUE - Value of one of input parameters (speed, duplex) ++* is not valid ++* ++*******************************************************************************/ ++MV_STATUS mvEthSpeedDuplexSet(void* pPortHandle, MV_ETH_PORT_SPEED speed, ++ MV_ETH_PORT_DUPLEX duplex) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ int port = pPortCtrl->portNo; ++ MV_U32 portSerialCtrlReg; ++ ++ if( (port < 0) || (port >= (int)mvCtrlEthMaxPortGet()) ) ++ return MV_OUT_OF_RANGE; ++ ++ pPortCtrl = ethPortCtrl[port]; ++ if(pPortCtrl == NULL) ++ return MV_NOT_FOUND; ++ ++ /* Check validity */ ++ if( (speed == MV_ETH_SPEED_1000) && (duplex == MV_ETH_DUPLEX_HALF) ) ++ return MV_BAD_PARAM; ++ ++ portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port)); ++ /* Set Speed */ ++ switch(speed) ++ { ++ case MV_ETH_SPEED_AN: ++ portSerialCtrlReg &= ~ETH_DISABLE_SPEED_AUTO_NEG_MASK; ++ break; ++ ++ case MV_ETH_SPEED_10: ++ portSerialCtrlReg |= ETH_DISABLE_SPEED_AUTO_NEG_MASK; ++ portSerialCtrlReg &= ~ETH_SET_GMII_SPEED_1000_MASK; ++ portSerialCtrlReg &= ~ETH_SET_MII_SPEED_100_MASK; ++ break; ++ ++ case MV_ETH_SPEED_100: ++ portSerialCtrlReg |= ETH_DISABLE_SPEED_AUTO_NEG_MASK; ++ portSerialCtrlReg &= ~ETH_SET_GMII_SPEED_1000_MASK; ++ portSerialCtrlReg |= ETH_SET_MII_SPEED_100_MASK; ++ break; ++ ++ case MV_ETH_SPEED_1000: ++ portSerialCtrlReg |= ETH_DISABLE_SPEED_AUTO_NEG_MASK; ++ portSerialCtrlReg |= ETH_SET_GMII_SPEED_1000_MASK; ++ break; ++ ++ default: ++ mvOsPrintf("ethDrv: Unexpected Speed value %d\n", speed); ++ return MV_BAD_VALUE; ++ } ++ /* Set duplex */ ++ switch(duplex) ++ { ++ case MV_ETH_DUPLEX_AN: ++ portSerialCtrlReg &= ~ETH_DISABLE_DUPLEX_AUTO_NEG_MASK; ++ break; ++ ++ case MV_ETH_DUPLEX_HALF: ++ portSerialCtrlReg |= ETH_DISABLE_DUPLEX_AUTO_NEG_MASK; ++ portSerialCtrlReg &= ~ETH_SET_FULL_DUPLEX_MASK; ++ break; ++ ++ case MV_ETH_DUPLEX_FULL: ++ portSerialCtrlReg |= ETH_DISABLE_DUPLEX_AUTO_NEG_MASK; ++ portSerialCtrlReg |= ETH_SET_FULL_DUPLEX_MASK; ++ break; ++ ++ default: ++ mvOsPrintf("ethDrv: Unexpected Duplex value %d\n", duplex); ++ return MV_BAD_VALUE; ++ } ++ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(port), portSerialCtrlReg); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvEthFlowCtrlSet - Set Flow Control of the port. ++* ++* DESCRIPTION: ++* This function configure the port to work with desirable Duplex and ++* Speed. Changing of these parameters are allowed only when port is ++* disabled. This function disable the port if was enabled, change ++* duplex and speed and, enable the port back if needed. ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* MV_ETH_PORT_FC flowControl - Flow control of the port. ++* ++* RETURN: MV_STATUS ++* MV_OK - Success ++* MV_OUT_OF_RANGE - Failed. Port is out of valid range ++* MV_NOT_FOUND - Failed. Port is not initialized. ++* MV_BAD_VALUE - Value flowControl parameters is not valid ++* ++*******************************************************************************/ ++MV_STATUS mvEthFlowCtrlSet(void* pPortHandle, MV_ETH_PORT_FC flowControl) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ int port = pPortCtrl->portNo; ++ MV_U32 portSerialCtrlReg; ++ ++ if( (port < 0) || (port >= (int)mvCtrlEthMaxPortGet() ) ) ++ return MV_OUT_OF_RANGE; ++ ++ pPortCtrl = ethPortCtrl[port]; ++ if(pPortCtrl == NULL) ++ return MV_NOT_FOUND; ++ ++ portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port)); ++ switch(flowControl) ++ { ++ case MV_ETH_FC_AN_ADV_DIS: ++ portSerialCtrlReg &= ~ETH_DISABLE_FC_AUTO_NEG_MASK; ++ portSerialCtrlReg &= ~ETH_ADVERTISE_SYM_FC_MASK; ++ break; ++ ++ case MV_ETH_FC_AN_ADV_SYM: ++ portSerialCtrlReg &= ~ETH_DISABLE_FC_AUTO_NEG_MASK; ++ portSerialCtrlReg |= ETH_ADVERTISE_SYM_FC_MASK; ++ break; ++ ++ case MV_ETH_FC_DISABLE: ++ portSerialCtrlReg |= ETH_DISABLE_FC_AUTO_NEG_MASK; ++ portSerialCtrlReg &= ~ETH_SET_FLOW_CTRL_MASK; ++ break; ++ ++ case MV_ETH_FC_ENABLE: ++ portSerialCtrlReg |= ETH_DISABLE_FC_AUTO_NEG_MASK; ++ portSerialCtrlReg |= ETH_SET_FLOW_CTRL_MASK; ++ break; ++ ++ default: ++ mvOsPrintf("ethDrv: Unexpected FlowControl value %d\n", flowControl); ++ return MV_BAD_VALUE; ++ } ++ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(port), portSerialCtrlReg); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvEthHeaderModeSet - Set port header mode. ++* ++* DESCRIPTION: ++* This function configures the port to work in Marvell-Header mode. ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* MV_ETH_HEADER_MODE headerMode - The header mode to set the port in. ++* ++* RETURN: MV_STATUS ++* MV_OK - Success ++* MV_NOT_SUPPORTED- Feature not supported. ++* MV_OUT_OF_RANGE - Failed. Port is out of valid range ++* MV_NOT_FOUND - Failed. Port is not initialized. ++* MV_BAD_VALUE - Value of headerMode or numRxQueue parameter is not valid. ++* ++*******************************************************************************/ ++MV_STATUS mvEthHeaderModeSet(void* pPortHandle, MV_ETH_HEADER_MODE headerMode) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ int port = pPortCtrl->portNo; ++ MV_U32 mvHeaderReg; ++ MV_U32 numRxQ = MV_ETH_RX_Q_NUM; ++ ++ if((port < 0) || (port >= mvCtrlEthMaxPortGet())) ++ return MV_OUT_OF_RANGE; ++ ++ pPortCtrl = ethPortCtrl[port]; ++ if(pPortCtrl == NULL) ++ return MV_NOT_FOUND; ++ ++ mvHeaderReg = MV_REG_READ(ETH_PORT_MARVELL_HEADER_REG(port)); ++ /* Disable header mode. */ ++ mvHeaderReg &= ~ETH_MVHDR_EN_MASK; ++ ++ if(headerMode != MV_ETH_DISABLE_HEADER_MODE) ++ { ++ /* Enable Header mode. */ ++ mvHeaderReg |= ETH_MVHDR_EN_MASK; ++ ++ /* Clear DA-Prefix & MHMask fields.*/ ++ mvHeaderReg &= ~(ETH_MVHDR_DAPREFIX_MASK | ETH_MVHDR_MHMASK_MASK); ++ ++ if(numRxQ > 1) ++ { ++ switch (headerMode) ++ { ++ case(MV_ETH_ENABLE_HEADER_MODE_PRI_2_1): ++ mvHeaderReg |= ETH_MVHDR_DAPREFIX_PRI_1_2; ++ break; ++ case(MV_ETH_ENABLE_HEADER_MODE_PRI_DBNUM): ++ mvHeaderReg |= ETH_MVHDR_DAPREFIX_DBNUM_PRI; ++ break; ++ case(MV_ETH_ENABLE_HEADER_MODE_PRI_SPID): ++ mvHeaderReg |= ETH_MVHDR_DAPREFIX_SPID_PRI; ++ break; ++ default: ++ break; ++ } ++ ++ switch (numRxQ) ++ { ++ case (4): ++ mvHeaderReg |= ETH_MVHDR_MHMASK_4_QUEUE; ++ break; ++ case (8): ++ mvHeaderReg |= ETH_MVHDR_MHMASK_8_QUEUE; ++ break; ++ default: ++ break; ++ } ++ } ++ } ++ ++ MV_REG_WRITE(ETH_PORT_MARVELL_HEADER_REG(port), mvHeaderReg); ++ ++ return MV_OK; ++} ++ ++#if (MV_ETH_VERSION >= 4) ++/******************************************************************************* ++* mvEthEjpModeSet - Enable / Disable EJP policy for TX. ++* ++* DESCRIPTION: ++* This function ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* MV_BOOL TRUE - enable EJP mode ++* FALSE - disable EJP mode ++* ++* OUTPUT: MV_STATUS ++* MV_OK - Success ++* Other - Failure ++* ++* RETURN: None. ++* ++*******************************************************************************/ ++MV_STATUS mvEthEjpModeSet(void* pPortHandle, int mode) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ int port = pPortCtrl->portNo; ++ ++ if((port < 0) || (port >= mvCtrlEthMaxPortGet())) ++ return MV_OUT_OF_RANGE; ++ ++ pPortCtrl = ethPortCtrl[port]; ++ if(pPortCtrl == NULL) ++ return MV_NOT_FOUND; ++ ++ pPortCtrl->portConfig.ejpMode = mode; ++ if(mode) ++ { ++ /* EJP enabled */ ++ MV_REG_WRITE(ETH_TXQ_CMD_1_REG(port), ETH_TX_EJP_ENABLE_MASK); ++ } ++ else ++ { ++ /* EJP disabled */ ++ MV_REG_WRITE(ETH_TXQ_CMD_1_REG(port), 0); ++ } ++ mvOsPrintf("eth_%d: EJP %s - ETH_TXQ_CMD_1_REG: 0x%x = 0x%08x\n", ++ port, mode ? "Enabled" : "Disabled", ETH_TXQ_CMD_1_REG(port), ++ MV_REG_READ(ETH_TXQ_CMD_1_REG(port))); ++ ++ return MV_OK; ++} ++#endif /* MV_ETH_VERSION >= 4 */ ++ ++/******************************************************************************* ++* mvEthStatusGet - Get major properties of the port . ++* ++* DESCRIPTION: ++* This function get major properties of the port (link, speed, duplex, ++* flowControl, etc) and return them using the single structure. ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* ++* OUTPUT: ++* MV_ETH_PORT_STATUS* pStatus - Pointer to structure, were port status ++* will be placed. ++* ++* RETURN: None. ++* ++*******************************************************************************/ ++void mvEthStatusGet(void* pPortHandle, MV_ETH_PORT_STATUS* pStatus) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ int port = pPortCtrl->portNo; ++ ++ MV_U32 regValue; ++ ++ regValue = MV_REG_READ( ETH_PORT_STATUS_REG(port) ); ++ ++ if(regValue & ETH_GMII_SPEED_1000_MASK) ++ pStatus->speed = MV_ETH_SPEED_1000; ++ else if(regValue & ETH_MII_SPEED_100_MASK) ++ pStatus->speed = MV_ETH_SPEED_100; ++ else ++ pStatus->speed = MV_ETH_SPEED_10; ++ ++ if(regValue & ETH_LINK_UP_MASK) ++ pStatus->isLinkUp = MV_TRUE; ++ else ++ pStatus->isLinkUp = MV_FALSE; ++ ++ if(regValue & ETH_FULL_DUPLEX_MASK) ++ pStatus->duplex = MV_ETH_DUPLEX_FULL; ++ else ++ pStatus->duplex = MV_ETH_DUPLEX_HALF; ++ ++ ++ if(regValue & ETH_ENABLE_RCV_FLOW_CTRL_MASK) ++ pStatus->flowControl = MV_ETH_FC_ENABLE; ++ else ++ pStatus->flowControl = MV_ETH_FC_DISABLE; ++} ++ ++ ++/******************************************************************************/ ++/* PHY Control Functions */ ++/******************************************************************************/ ++ ++ ++/******************************************************************************* ++* mvEthPhyAddrSet - Set the ethernet port PHY address. ++* ++* DESCRIPTION: ++* This routine set the ethernet port PHY address according to given ++* parameter. ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* int phyAddr - PHY address ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++void mvEthPhyAddrSet(void* pPortHandle, int phyAddr) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ int port = pPortCtrl->portNo; ++ unsigned int regData; ++ ++ regData = MV_REG_READ(ETH_PHY_ADDR_REG(port)); ++ ++ regData &= ~ETH_PHY_ADDR_MASK; ++ regData |= phyAddr; ++ ++ MV_REG_WRITE(ETH_PHY_ADDR_REG(port), regData); ++ ++ return; ++} ++ ++/******************************************************************************* ++* mvEthPhyAddrGet - Get the ethernet port PHY address. ++* ++* DESCRIPTION: ++* This routine returns the given ethernet port PHY address. ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* ++* ++* RETURN: int - PHY address. ++* ++*******************************************************************************/ ++int mvEthPhyAddrGet(void* pPortHandle) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ int port = pPortCtrl->portNo; ++ unsigned int regData; ++ ++ regData = MV_REG_READ(ETH_PHY_ADDR_REG(port)); ++ ++ return ((regData >> (5 * port)) & 0x1f); ++} ++ ++/******************************************************************************/ ++/* Descriptor handling Functions */ ++/******************************************************************************/ ++ ++/******************************************************************************* ++* etherInitRxDescRing - Curve a Rx chain desc list and buffer in memory. ++* ++* DESCRIPTION: ++* This function prepares a Rx chained list of descriptors and packet ++* buffers in a form of a ring. The routine must be called after port ++* initialization routine and before port start routine. ++* The Ethernet SDMA engine uses CPU bus addresses to access the various ++* devices in the system (i.e. DRAM). This function uses the ethernet ++* struct 'virtual to physical' routine (set by the user) to set the ring ++* with physical addresses. ++* ++* INPUT: ++* ETH_QUEUE_CTRL *pEthPortCtrl Ethernet Port Control srtuct. ++* int rxQueue Number of Rx queue. ++* int rxDescNum Number of Rx descriptors ++* MV_U8* rxDescBaseAddr Rx descriptors memory area base addr. ++* ++* OUTPUT: ++* The routine updates the Ethernet port control struct with information ++* regarding the Rx descriptors and buffers. ++* ++* RETURN: None ++* ++*******************************************************************************/ ++static void ethInitRxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue) ++{ ++ ETH_RX_DESC *pRxDescBase, *pRxDesc, *pRxPrevDesc; ++ int ix, rxDescNum = pPortCtrl->rxQueueConfig[queue].descrNum; ++ ETH_QUEUE_CTRL *pQueueCtrl = &pPortCtrl->rxQueue[queue]; ++ ++ /* Make sure descriptor address is cache line size aligned */ ++ pRxDescBase = (ETH_RX_DESC*)MV_ALIGN_UP((MV_ULONG)pQueueCtrl->descBuf.bufVirtPtr, ++ CPU_D_CACHE_LINE_SIZE); ++ ++ pRxDesc = (ETH_RX_DESC*)pRxDescBase; ++ pRxPrevDesc = pRxDesc; ++ ++ /* initialize the Rx descriptors ring */ ++ for (ix=0; ixbufSize = 0x0; ++ pRxDesc->byteCnt = 0x0; ++ pRxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; ++ pRxDesc->bufPtr = 0x0; ++ pRxDesc->returnInfo = 0x0; ++ pRxPrevDesc = pRxDesc; ++ if(ix == (rxDescNum-1)) ++ { ++ /* Closing Rx descriptors ring */ ++ pRxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pRxDescBase); ++ } ++ else ++ { ++ pRxDesc = (ETH_RX_DESC*)((MV_ULONG)pRxDesc + ETH_RX_DESC_ALIGNED_SIZE); ++ pRxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pRxDesc); ++ } ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxPrevDesc); ++ } ++ ++ pQueueCtrl->pCurrentDescr = pRxDescBase; ++ pQueueCtrl->pUsedDescr = pRxDescBase; ++ ++ pQueueCtrl->pFirstDescr = pRxDescBase; ++ pQueueCtrl->pLastDescr = pRxDesc; ++ pQueueCtrl->resource = 0; ++} ++ ++void ethResetRxDescRing(void* pPortHndl, int queue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->rxQueue[queue]; ++ ETH_RX_DESC* pRxDesc = (ETH_RX_DESC*)pQueueCtrl->pFirstDescr; ++ ++ pQueueCtrl->resource = 0; ++ if(pQueueCtrl->pFirstDescr != NULL) ++ { ++ while(MV_TRUE) ++ { ++ pRxDesc->bufSize = 0x0; ++ pRxDesc->byteCnt = 0x0; ++ pRxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; ++ pRxDesc->bufPtr = 0x0; ++ pRxDesc->returnInfo = 0x0; ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxDesc); ++ if( (void*)pRxDesc == pQueueCtrl->pLastDescr) ++ break; ++ pRxDesc = RX_NEXT_DESC_PTR(pRxDesc, pQueueCtrl); ++ } ++ pQueueCtrl->pCurrentDescr = pQueueCtrl->pFirstDescr; ++ pQueueCtrl->pUsedDescr = pQueueCtrl->pFirstDescr; ++ ++ /* Update RX Command register */ ++ pPortCtrl->portRxQueueCmdReg |= (1 << queue); ++ ++ /* update HW */ ++ MV_REG_WRITE( ETH_RX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), ++ (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); ++ } ++ else ++ { ++ /* Update RX Command register */ ++ pPortCtrl->portRxQueueCmdReg &= ~(1 << queue); ++ ++ /* update HW */ ++ MV_REG_WRITE( ETH_RX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), 0); ++ } ++} ++ ++/******************************************************************************* ++* etherInitTxDescRing - Curve a Tx chain desc list and buffer in memory. ++* ++* DESCRIPTION: ++* This function prepares a Tx chained list of descriptors and packet ++* buffers in a form of a ring. The routine must be called after port ++* initialization routine and before port start routine. ++* The Ethernet SDMA engine uses CPU bus addresses to access the various ++* devices in the system (i.e. DRAM). This function uses the ethernet ++* struct 'virtual to physical' routine (set by the user) to set the ring ++* with physical addresses. ++* ++* INPUT: ++* ETH_PORT_CTRL *pEthPortCtrl Ethernet Port Control srtuct. ++* int txQueue Number of Tx queue. ++* int txDescNum Number of Tx descriptors ++* int txBuffSize Size of Tx buffer ++* MV_U8* pTxDescBase Tx descriptors memory area base addr. ++* ++* OUTPUT: ++* The routine updates the Ethernet port control struct with information ++* regarding the Tx descriptors and buffers. ++* ++* RETURN: None. ++* ++*******************************************************************************/ ++static void ethInitTxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue) ++{ ++ ETH_TX_DESC *pTxDescBase, *pTxDesc, *pTxPrevDesc; ++ int ix, txDescNum = pPortCtrl->txQueueConfig[queue].descrNum; ++ ETH_QUEUE_CTRL *pQueueCtrl = &pPortCtrl->txQueue[queue]; ++ ++ /* Make sure descriptor address is cache line size aligned */ ++ pTxDescBase = (ETH_TX_DESC*)MV_ALIGN_UP((MV_ULONG)pQueueCtrl->descBuf.bufVirtPtr, ++ CPU_D_CACHE_LINE_SIZE); ++ ++ pTxDesc = (ETH_TX_DESC*)pTxDescBase; ++ pTxPrevDesc = pTxDesc; ++ ++ /* initialize the Tx descriptors ring */ ++ for (ix=0; ixbyteCnt = 0x0000; ++ pTxDesc->L4iChk = 0x0000; ++ pTxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; ++ pTxDesc->bufPtr = 0x0; ++ pTxDesc->returnInfo = 0x0; ++ ++ pTxPrevDesc = pTxDesc; ++ ++ if(ix == (txDescNum-1)) ++ { ++ /* Closing Tx descriptors ring */ ++ pTxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pTxDescBase); ++ } ++ else ++ { ++ pTxDesc = (ETH_TX_DESC*)((MV_ULONG)pTxDesc + ETH_TX_DESC_ALIGNED_SIZE); ++ pTxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pTxDesc); ++ } ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxPrevDesc); ++ } ++ ++ pQueueCtrl->pCurrentDescr = pTxDescBase; ++ pQueueCtrl->pUsedDescr = pTxDescBase; ++ ++ pQueueCtrl->pFirstDescr = pTxDescBase; ++ pQueueCtrl->pLastDescr = pTxDesc; ++ /* Leave one TX descriptor out of use */ ++ pQueueCtrl->resource = txDescNum - 1; ++} ++ ++void ethResetTxDescRing(void* pPortHndl, int queue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->txQueue[queue]; ++ ETH_TX_DESC* pTxDesc = (ETH_TX_DESC*)pQueueCtrl->pFirstDescr; ++ ++ pQueueCtrl->resource = 0; ++ if(pQueueCtrl->pFirstDescr != NULL) ++ { ++ while(MV_TRUE) ++ { ++ pTxDesc->byteCnt = 0x0000; ++ pTxDesc->L4iChk = 0x0000; ++ pTxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; ++ pTxDesc->bufPtr = 0x0; ++ pTxDesc->returnInfo = 0x0; ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxDesc); ++ pQueueCtrl->resource++; ++ if( (void*)pTxDesc == pQueueCtrl->pLastDescr) ++ break; ++ pTxDesc = TX_NEXT_DESC_PTR(pTxDesc, pQueueCtrl); ++ } ++ /* Leave one TX descriptor out of use */ ++ pQueueCtrl->resource--; ++ pQueueCtrl->pCurrentDescr = pQueueCtrl->pFirstDescr; ++ pQueueCtrl->pUsedDescr = pQueueCtrl->pFirstDescr; ++ ++ /* Update TX Command register */ ++ pPortCtrl->portTxQueueCmdReg |= MV_32BIT_LE_FAST(1 << queue); ++ /* update HW */ ++ MV_REG_WRITE( ETH_TX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), ++ (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); ++ } ++ else ++ { ++ /* Update TX Command register */ ++ pPortCtrl->portTxQueueCmdReg &= MV_32BIT_LE_FAST(~(1 << queue)); ++ /* update HW */ ++ MV_REG_WRITE( ETH_TX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), 0 ); ++ } ++} ++ ++/******************************************************************************* ++* ethAllocDescrMemory - Free memory allocated for RX and TX descriptors. ++* ++* DESCRIPTION: ++* This function allocates memory for RX and TX descriptors. ++* - If ETH_DESCR_IN_SRAM defined, allocate memory from SRAM. ++* - If ETH_DESCR_IN_SDRAM defined, allocate memory in SDRAM. ++* ++* INPUT: ++* int size - size of memory should be allocated. ++* ++* RETURN: None ++* ++*******************************************************************************/ ++static MV_U8* ethAllocDescrMemory(ETH_PORT_CTRL* pPortCtrl, int descSize, ++ MV_ULONG* pPhysAddr, MV_U32 *memHandle) ++{ ++ MV_U8* pVirt; ++ ++#if defined(ETH_DESCR_IN_SRAM) ++ if(ethDescInSram == MV_TRUE) ++ pVirt = (char*)mvSramMalloc(descSize, pPhysAddr); ++ else ++#endif /* ETH_DESCR_IN_SRAM */ ++ { ++#ifdef ETH_DESCR_UNCACHED ++ pVirt = (MV_U8*)mvOsIoUncachedMalloc(pPortCtrl->osHandle, descSize, ++ pPhysAddr,memHandle); ++#else ++ pVirt = (MV_U8*)mvOsIoCachedMalloc(pPortCtrl->osHandle, descSize, ++ pPhysAddr, memHandle); ++#endif /* ETH_DESCR_UNCACHED */ ++ } ++ memset(pVirt, 0, descSize); ++ ++ return pVirt; ++} ++ ++/******************************************************************************* ++* ethFreeDescrMemory - Free memory allocated for RX and TX descriptors. ++* ++* DESCRIPTION: ++* This function frees memory allocated for RX and TX descriptors. ++* - If ETH_DESCR_IN_SRAM defined, free memory using gtSramFree() function. ++* - If ETH_DESCR_IN_SDRAM defined, free memory using mvOsFree() function. ++* ++* INPUT: ++* void* pVirtAddr - virtual pointer to memory allocated for RX and TX ++* desriptors. ++* ++* RETURN: None ++* ++*******************************************************************************/ ++void ethFreeDescrMemory(ETH_PORT_CTRL* pPortCtrl, MV_BUF_INFO* pDescBuf) ++{ ++ if( (pDescBuf == NULL) || (pDescBuf->bufVirtPtr == NULL) ) ++ return; ++ ++#if defined(ETH_DESCR_IN_SRAM) ++ if( ethDescInSram ) ++ { ++ mvSramFree(pDescBuf->bufSize, pDescBuf->bufPhysAddr, pDescBuf->bufVirtPtr); ++ return; ++ } ++#endif /* ETH_DESCR_IN_SRAM */ ++ ++#ifdef ETH_DESCR_UNCACHED ++ mvOsIoUncachedFree(pPortCtrl->osHandle, pDescBuf->bufSize, pDescBuf->bufPhysAddr, ++ pDescBuf->bufVirtPtr,pDescBuf->memHandle); ++#else ++ mvOsIoCachedFree(pPortCtrl->osHandle, pDescBuf->bufSize, pDescBuf->bufPhysAddr, ++ pDescBuf->bufVirtPtr,pDescBuf->memHandle); ++#endif /* ETH_DESCR_UNCACHED */ ++} ++ ++/******************************************************************************/ ++/* Other Functions */ ++/******************************************************************************/ ++ ++void mvEthPortPowerUp(int port) ++{ ++ MV_U32 regVal; ++ ++ /* MAC Cause register should be cleared */ ++ MV_REG_WRITE(ETH_UNIT_INTR_CAUSE_REG(port), 0); ++ ++ if (mvBoardIsPortInSgmii(port)) ++ mvEthPortSgmiiConfig(port); ++ ++ /* Cancel Port Reset */ ++ regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)); ++ regVal &= (~ETH_PORT_RESET_MASK); ++ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal); ++ while( (MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)) & ETH_PORT_RESET_MASK) != 0); ++} ++ ++void mvEthPortPowerDown(int port) ++{ ++ MV_U32 regVal; ++ ++ /* Port must be DISABLED */ ++ regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port)); ++ if( (regVal & ETH_PORT_ENABLE_MASK) != 0) ++ { ++ mvOsPrintf("ethPort #%d: PowerDown - port must be Disabled (PSC=0x%x)\n", ++ port, regVal); ++ return; ++ } ++ ++ /* Port Reset (Read after write the register as a precaution) */ ++ regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)); ++ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal | ETH_PORT_RESET_MASK); ++ while((MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)) & ETH_PORT_RESET_MASK) == 0); ++} ++ ++static void mvEthPortSgmiiConfig(int port) ++{ ++ MV_U32 regVal; ++ ++ regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)); ++ ++ regVal |= (ETH_SGMII_MODE_MASK /*| ETH_INBAND_AUTO_NEG_ENABLE_MASK */); ++ regVal &= (~ETH_INBAND_AUTO_NEG_BYPASS_MASK); ++ ++ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal); ++} ++ ++ ++ ++ ++ ++ ++ ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,748 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++/******************************************************************************* ++* mvEthDebug.c - Source file for user friendly debug functions ++* ++* DESCRIPTION: ++* ++* DEPENDENCIES: ++* None. ++* ++*******************************************************************************/ ++ ++#include "mvOs.h" ++#include "mvCommon.h" ++#include "mvTypes.h" ++#include "mv802_3.h" ++#include "mvDebug.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "eth-phy/mvEthPhy.h" ++#include "eth/mvEth.h" ++#include "eth/gbe/mvEthDebug.h" ++ ++/* #define mvOsPrintf printf */ ++ ++void mvEthPortShow(void* pHndl); ++void mvEthQueuesShow(void* pHndl, int rxQueue, int txQueue, int mode); ++ ++/******************************************************************************/ ++/* Debug functions */ ++/******************************************************************************/ ++void ethRxCoal(int port, int usec) ++{ ++ void* pHndl; ++ ++ pHndl = mvEthPortHndlGet(port); ++ if(pHndl != NULL) ++ { ++ mvEthRxCoalSet(pHndl, usec); ++ } ++} ++ ++void ethTxCoal(int port, int usec) ++{ ++ void* pHndl; ++ ++ pHndl = mvEthPortHndlGet(port); ++ if(pHndl != NULL) ++ { ++ mvEthTxCoalSet(pHndl, usec); ++ } ++} ++ ++#if (MV_ETH_VERSION >= 4) ++void ethEjpModeSet(int port, int mode) ++{ ++ void* pHndl; ++ ++ pHndl = mvEthPortHndlGet(port); ++ if(pHndl != NULL) ++ { ++ mvEthEjpModeSet(pHndl, mode); ++ } ++} ++#endif /* (MV_ETH_VERSION >= 4) */ ++ ++void ethBpduRxQ(int port, int bpduQueue) ++{ ++ void* pHndl; ++ ++ pHndl = mvEthPortHndlGet(port); ++ if(pHndl != NULL) ++ { ++ mvEthBpduRxQueue(pHndl, bpduQueue); ++ } ++} ++ ++void ethArpRxQ(int port, int arpQueue) ++{ ++ void* pHndl; ++ ++ pHndl = mvEthPortHndlGet(port); ++ if(pHndl != NULL) ++ { ++ mvEthArpRxQueue(pHndl, arpQueue); ++ } ++} ++ ++void ethTcpRxQ(int port, int tcpQueue) ++{ ++ void* pHndl; ++ ++ pHndl = mvEthPortHndlGet(port); ++ if(pHndl != NULL) ++ { ++ mvEthTcpRxQueue(pHndl, tcpQueue); ++ } ++} ++ ++void ethUdpRxQ(int port, int udpQueue) ++{ ++ void* pHndl; ++ ++ pHndl = mvEthPortHndlGet(port); ++ if(pHndl != NULL) ++ { ++ mvEthUdpRxQueue(pHndl, udpQueue); ++ } ++} ++ ++void ethTxPolicyRegs(int port) ++{ ++ int queue; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)mvEthPortHndlGet(port); ++ ++ if(pPortCtrl == NULL) ++ { ++ return; ++ } ++ mvOsPrintf("Port #%d TX Policy: EJP=%d, TXQs: ", ++ port, pPortCtrl->portConfig.ejpMode); ++ for(queue=0; queuetxQueueConfig[queue].descrNum > 0) ++ mvOsPrintf("%d, ", queue); ++ } ++ mvOsPrintf("\n"); ++ ++ mvOsPrintf("\n\t TX policy Port #%d configuration registers\n", port); ++ ++ mvOsPrintf("ETH_TX_QUEUE_COMMAND_REG : 0x%X = 0x%08x\n", ++ ETH_TX_QUEUE_COMMAND_REG(port), ++ MV_REG_READ( ETH_TX_QUEUE_COMMAND_REG(port) ) ); ++ ++ mvOsPrintf("ETH_TX_FIXED_PRIO_CFG_REG : 0x%X = 0x%08x\n", ++ ETH_TX_FIXED_PRIO_CFG_REG(port), ++ MV_REG_READ( ETH_TX_FIXED_PRIO_CFG_REG(port) ) ); ++ ++ mvOsPrintf("ETH_TX_TOKEN_RATE_CFG_REG : 0x%X = 0x%08x\n", ++ ETH_TX_TOKEN_RATE_CFG_REG(port), ++ MV_REG_READ( ETH_TX_TOKEN_RATE_CFG_REG(port) ) ); ++ ++ mvOsPrintf("ETH_MAX_TRANSMIT_UNIT_REG : 0x%X = 0x%08x\n", ++ ETH_MAX_TRANSMIT_UNIT_REG(port), ++ MV_REG_READ( ETH_MAX_TRANSMIT_UNIT_REG(port) ) ); ++ ++ mvOsPrintf("ETH_TX_TOKEN_BUCKET_SIZE_REG : 0x%X = 0x%08x\n", ++ ETH_TX_TOKEN_BUCKET_SIZE_REG(port), ++ MV_REG_READ( ETH_TX_TOKEN_BUCKET_SIZE_REG(port) ) ); ++ ++ mvOsPrintf("ETH_TX_TOKEN_BUCKET_COUNT_REG : 0x%X = 0x%08x\n", ++ ETH_TX_TOKEN_BUCKET_COUNT_REG(port), ++ MV_REG_READ( ETH_TX_TOKEN_BUCKET_COUNT_REG(port) ) ); ++ ++ for(queue=0; queue> 24) & 0xff), ((macH >> 16) & 0xff), ++ ((macH >> 8) & 0xff), (macH & 0xff), ++ ((macL >> 8) & 0xff), (macL & 0xff) ); ++ ++ for (i=0; i<4; i++) ++ { ++ unicastReg = MV_REG_READ( (ETH_DA_FILTER_UCAST_BASE(port) + i*4)); ++ for(j=0; j<4; j++) ++ { ++ MV_U8 macEntry = (unicastReg >> (8*j)) & 0xFF; ++ ++ mvOsPrintf("%X: %8s, Q = %d\n", i*4+j, ++ (macEntry & BIT0) ? "Accept" : "Reject", (macEntry >> 1) & 0x7); ++ } ++ } ++} ++ ++void ethMcastAdd(int port, char* macStr, int queue) ++{ ++ void* pHndl; ++ MV_U8 macAddr[MV_MAC_ADDR_SIZE]; ++ ++ pHndl = mvEthPortHndlGet(port); ++ if(pHndl != NULL) ++ { ++ mvMacStrToHex(macStr, macAddr); ++ mvEthMcastAddrSet(pHndl, macAddr, queue); ++ } ++} ++ ++void ethPortMcast(int port) ++{ ++ int tblIdx, regIdx; ++ MV_U32 regVal; ++ ++ mvOsPrintf("\n\t Port #%d Special (IP) Multicast table: 01:00:5E:00:00:XX\n\n", ++ port); ++ ++ for(tblIdx=0; tblIdx<(256/4); tblIdx++) ++ { ++ regVal = MV_REG_READ((ETH_DA_FILTER_SPEC_MCAST_BASE(port) + tblIdx*4)); ++ for(regIdx=0; regIdx<4; regIdx++) ++ { ++ if((regVal & (0x01 << (regIdx*8))) != 0) ++ { ++ mvOsPrintf("0x%02X: Accepted, rxQ = %d\n", ++ tblIdx*4+regIdx, ((regVal >> (regIdx*8+1)) & 0x07)); ++ } ++ } ++ } ++ mvOsPrintf("\n\t Port #%d Other Multicast table\n\n", port); ++ for(tblIdx=0; tblIdx<(256/4); tblIdx++) ++ { ++ regVal = MV_REG_READ((ETH_DA_FILTER_OTH_MCAST_BASE(port) + tblIdx*4)); ++ for(regIdx=0; regIdx<4; regIdx++) ++ { ++ if((regVal & (0x01 << (regIdx*8))) != 0) ++ { ++ mvOsPrintf("Crc8=0x%02X: Accepted, rxQ = %d\n", ++ tblIdx*4+regIdx, ((regVal >> (regIdx*8+1)) & 0x07)); ++ } ++ } ++ } ++} ++ ++ ++/* Print status of Ethernet port */ ++void mvEthPortShow(void* pHndl) ++{ ++ MV_U32 regValue, rxCoal, txCoal; ++ int speed, queue, port; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pHndl; ++ ++ port = pPortCtrl->portNo; ++ ++ regValue = MV_REG_READ( ETH_PORT_STATUS_REG(port) ); ++ ++ mvOsPrintf("\n\t ethGiga #%d port Status: 0x%04x = 0x%08x\n\n", ++ port, ETH_PORT_STATUS_REG(port), regValue); ++ ++ mvOsPrintf("descInSram=%d, descSwCoher=%d\n", ++ ethDescInSram, ethDescSwCoher); ++ ++ if(regValue & ETH_GMII_SPEED_1000_MASK) ++ speed = 1000; ++ else if(regValue & ETH_MII_SPEED_100_MASK) ++ speed = 100; ++ else ++ speed = 10; ++ ++ mvEthCoalGet(pPortCtrl, &rxCoal, &txCoal); ++ ++ /* Link, Speed, Duplex, FlowControl */ ++ mvOsPrintf("Link=%s, Speed=%d, Duplex=%s, RxFlowControl=%s", ++ (regValue & ETH_LINK_UP_MASK) ? "UP" : "DOWN", ++ speed, ++ (regValue & ETH_FULL_DUPLEX_MASK) ? "FULL" : "HALF", ++ (regValue & ETH_ENABLE_RCV_FLOW_CTRL_MASK) ? "ENABLE" : "DISABLE"); ++ ++ mvOsPrintf("\n"); ++ ++ mvOsPrintf("RxCoal = %d usec, TxCoal = %d usec\n", ++ rxCoal, txCoal); ++ ++ mvOsPrintf("rxDefQ=%d, arpQ=%d, bpduQ=%d, tcpQ=%d, udpQ=%d\n\n", ++ pPortCtrl->portConfig.rxDefQ, pPortCtrl->portConfig.rxArpQ, ++ pPortCtrl->portConfig.rxBpduQ, ++ pPortCtrl->portConfig.rxTcpQ, pPortCtrl->portConfig.rxUdpQ); ++ ++ /* Print all RX and TX queues */ ++ for(queue=0; queuerxQueue[queue].pFirstDescr, ++ mvEthRxResourceGet(pPortCtrl, queue) ); ++ } ++ mvOsPrintf("\n"); ++ for(queue=0; queuetxQueue[queue].pFirstDescr, ++ mvEthTxResourceGet(pPortCtrl, queue) ); ++ } ++} ++ ++/* Print RX and TX queue of the Ethernet port */ ++void mvEthQueuesShow(void* pHndl, int rxQueue, int txQueue, int mode) ++{ ++ ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL*)pHndl; ++ ETH_QUEUE_CTRL *pQueueCtrl; ++ MV_U32 regValue; ++ ETH_RX_DESC *pRxDescr; ++ ETH_TX_DESC *pTxDescr; ++ int i, port = pPortCtrl->portNo; ++ ++ if( (rxQueue >=0) && (rxQueue < MV_ETH_RX_Q_NUM) ) ++ { ++ pQueueCtrl = &(pPortCtrl->rxQueue[rxQueue]); ++ mvOsPrintf("Port #%d, RX Queue #%d\n\n", port, rxQueue); ++ ++ mvOsPrintf("CURR_RX_DESC_PTR : 0x%X = 0x%08x\n", ++ ETH_RX_CUR_DESC_PTR_REG(port, rxQueue), ++ MV_REG_READ( ETH_RX_CUR_DESC_PTR_REG(port, rxQueue))); ++ ++ ++ if(pQueueCtrl->pFirstDescr != NULL) ++ { ++ mvOsPrintf("pFirstDescr=0x%lx, pLastDescr=0x%lx, numOfResources=%d\n", ++ (MV_ULONG)pQueueCtrl->pFirstDescr, (MV_ULONG)pQueueCtrl->pLastDescr, ++ pQueueCtrl->resource); ++ mvOsPrintf("pCurrDescr: 0x%lx, pUsedDescr: 0x%lx\n", ++ (MV_ULONG)pQueueCtrl->pCurrentDescr, ++ (MV_ULONG)pQueueCtrl->pUsedDescr); ++ ++ if(mode == 1) ++ { ++ pRxDescr = (ETH_RX_DESC*)pQueueCtrl->pFirstDescr; ++ i = 0; ++ do ++ { ++ mvOsPrintf("%3d. desc=%08x (%08x), cmd=%08x, data=%4d, buf=%4d, buf=%08x, pkt=%lx, os=%lx\n", ++ i, (MV_U32)pRxDescr, (MV_U32)ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pRxDescr), ++ pRxDescr->cmdSts, pRxDescr->byteCnt, (MV_U32)pRxDescr->bufSize, ++ (unsigned int)pRxDescr->bufPtr, (MV_ULONG)pRxDescr->returnInfo, ++ ((MV_PKT_INFO*)pRxDescr->returnInfo)->osInfo); ++ ++ ETH_DESCR_INV(pPortCtrl, pRxDescr); ++ pRxDescr = RX_NEXT_DESC_PTR(pRxDescr, pQueueCtrl); ++ i++; ++ } while (pRxDescr != pQueueCtrl->pFirstDescr); ++ } ++ } ++ else ++ mvOsPrintf("RX Queue #%d is NOT CREATED\n", rxQueue); ++ } ++ ++ if( (txQueue >=0) && (txQueue < MV_ETH_TX_Q_NUM) ) ++ { ++ pQueueCtrl = &(pPortCtrl->txQueue[txQueue]); ++ mvOsPrintf("Port #%d, TX Queue #%d\n\n", port, txQueue); ++ ++ regValue = MV_REG_READ( ETH_TX_CUR_DESC_PTR_REG(port, txQueue)); ++ mvOsPrintf("CURR_TX_DESC_PTR : 0x%X = 0x%08x\n", ++ ETH_TX_CUR_DESC_PTR_REG(port, txQueue), regValue); ++ ++ if(pQueueCtrl->pFirstDescr != NULL) ++ { ++ mvOsPrintf("pFirstDescr=0x%lx, pLastDescr=0x%lx, numOfResources=%d\n", ++ (MV_ULONG)pQueueCtrl->pFirstDescr, ++ (MV_ULONG)pQueueCtrl->pLastDescr, ++ pQueueCtrl->resource); ++ mvOsPrintf("pCurrDescr: 0x%lx, pUsedDescr: 0x%lx\n", ++ (MV_ULONG)pQueueCtrl->pCurrentDescr, ++ (MV_ULONG)pQueueCtrl->pUsedDescr); ++ ++ if(mode == 1) ++ { ++ pTxDescr = (ETH_TX_DESC*)pQueueCtrl->pFirstDescr; ++ i = 0; ++ do ++ { ++ mvOsPrintf("%3d. desc=%08x (%08x), cmd=%08x, data=%4d, buf=%08x, pkt=%lx, os=%lx\n", ++ i, (MV_U32)pTxDescr, (MV_U32)ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pTxDescr), ++ pTxDescr->cmdSts, pTxDescr->byteCnt, ++ (MV_U32)pTxDescr->bufPtr, (MV_ULONG)pTxDescr->returnInfo, ++ pTxDescr->returnInfo ? (((MV_PKT_INFO*)pTxDescr->returnInfo)->osInfo) : 0x0); ++ ++ ETH_DESCR_INV(pPortCtrl, pTxDescr); ++ pTxDescr = TX_NEXT_DESC_PTR(pTxDescr, pQueueCtrl); ++ i++; ++ } while (pTxDescr != pQueueCtrl->pFirstDescr); ++ } ++ } ++ else ++ mvOsPrintf("TX Queue #%d is NOT CREATED\n", txQueue); ++ } ++} +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,146 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++#ifndef __MV_ETH_DEBUG_H__ ++#define __MV_ETH_DEBUG_H__ ++ ++#if 0 ++/* ++ ** Externs ++ */ ++void ethBpduRxQ(int port, int bpduQueue); ++void ethArpRxQ(int port, int bpduQueue); ++void ethTcpRxQ(int port, int bpduQueue); ++void ethUdpRxQ(int port, int bpduQueue); ++void ethMcastAdd(int port, char* macStr, int queue); ++ ++#ifdef INCLUDE_MULTI_QUEUE ++void ethRxPolicy( int port); ++void ethTxPolicy( int port); ++void ethTxPolDA(int port, char* macStr, int txQ, char* headerHexStr); ++void ethRxPolMode(int port, MV_ETH_PRIO_MODE prioMode); ++void ethRxPolQ(int port, int rxQueue, int rxQuota); ++#endif /* INCLUDE_MULTI_QUEUE */ ++ ++void print_egiga_stat(void *sc, unsigned int port); ++void ethPortStatus (int port); ++void ethPortQueues( int port, int rxQueue, int txQueue, int mode); ++void ethPortMcast(int port); ++void ethPortRegs(int port); ++void ethPortCounters(int port); ++void ethPortRmonCounters(int port); ++void ethRxCoal(int port, int usec); ++void ethTxCoal(int port, int usec); ++ ++void ethRegs(int port); ++void ethClearCounters(int port); ++void ethUcastSet(int port, char* macStr, int queue); ++void ethPortUcastShow(int port); ++ ++#ifdef CONFIG_MV_ETH_HEADER ++void run_com_header(const char *buffer); ++#endif ++ ++#ifdef INCLUDE_MULTI_QUEUE ++void ethRxPolMode(int port, MV_ETH_PRIO_MODE prioMode); ++void ethRxPolQ(int port, int queue, int quota); ++void ethRxPolicy(int port); ++void ethTxPolDef(int port, int txQ, char* headerHexStr); ++void ethTxPolDA(int port, char* macStr, int txQ, char* headerHexStr); ++void ethTxPolicy(int port); ++#endif /* INCLUDE_MULTI_QUEUE */ ++ ++#if (MV_ETH_VERSION >= 4) ++void ethEjpModeSet(int port, int mode) ++#endif ++#endif /* 0 */ ++ ++ ++ ++ ++void ethRxCoal(int port, int usec); ++void ethTxCoal(int port, int usec); ++#if (MV_ETH_VERSION >= 4) ++void ethEjpModeSet(int port, int mode); ++#endif /* (MV_ETH_VERSION >= 4) */ ++ ++void ethBpduRxQ(int port, int bpduQueue); ++void ethArpRxQ(int port, int arpQueue); ++void ethTcpRxQ(int port, int tcpQueue); ++void ethUdpRxQ(int port, int udpQueue); ++void ethTxPolicyRegs(int port); ++void ethPortRegs(int port); ++void ethRegs(int port); ++void ethClearCounters(int port); ++void ethPortCounters(int port); ++void ethPortRmonCounters(int port); ++void ethPortStatus(int port); ++void ethPortQueues(int port, int rxQueue, int txQueue, int mode); ++void ethUcastSet(int port, char* macStr, int queue); ++void ethPortUcastShow(int port); ++void ethMcastAdd(int port, char* macStr, int queue); ++void ethPortMcast(int port); ++void mvEthPortShow(void* pHndl); ++void mvEthQueuesShow(void* pHndl, int rxQueue, int txQueue, int mode); ++ ++#endif +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthGbe.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthGbe.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthGbe.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthGbe.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,751 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++/******************************************************************************* ++* mvEth.h - Header File for : Marvell Gigabit Ethernet Controller ++* ++* DESCRIPTION: ++* This header file contains macros typedefs and function declaration specific to ++* the Marvell Gigabit Ethernet Controller. ++* ++* DEPENDENCIES: ++* None. ++* ++*******************************************************************************/ ++ ++#ifndef __mvEthGbe_h__ ++#define __mvEthGbe_h__ ++ ++extern MV_BOOL ethDescInSram; ++extern MV_BOOL ethDescSwCoher; ++extern ETH_PORT_CTRL* ethPortCtrl[]; ++ ++static INLINE MV_ULONG ethDescVirtToPhy(ETH_QUEUE_CTRL* pQueueCtrl, MV_U8* pDesc) ++{ ++#if defined (ETH_DESCR_IN_SRAM) ++ if( ethDescInSram ) ++ return mvSramVirtToPhy(pDesc); ++ else ++#endif /* ETH_DESCR_IN_SRAM */ ++ return (pQueueCtrl->descBuf.bufPhysAddr + (pDesc - pQueueCtrl->descBuf.bufVirtPtr)); ++} ++/* Return port handler */ ++#define mvEthPortHndlGet(port) ethPortCtrl[port] ++ ++/* Used as WA for HW/SW race on TX */ ++static INLINE int mvEthPortTxEnable(void* pPortHndl, int queue, int max_deep) ++{ ++ int deep = 0; ++ MV_U32 txCurrReg, txEnReg; ++ ETH_TX_DESC* pTxLastDesc; ++ ETH_QUEUE_CTRL* pQueueCtrl; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ ++ txEnReg = MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)); ++ if( (txEnReg & MV_32BIT_LE_FAST(ETH_TXQ_ENABLE_MASK)) == 0) ++ { ++ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) = pPortCtrl->portTxQueueCmdReg; ++ return 0; ++ } ++ ++ pQueueCtrl = &pPortCtrl->txQueue[queue]; ++ pTxLastDesc = pQueueCtrl->pCurrentDescr; ++ txCurrReg = MV_REG_READ(ETH_TX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue)); ++ if(ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pTxLastDesc) == txCurrReg) ++ { ++ /* All descriptors are processed, no chance for race */ ++ return 0; ++ } ++ ++ /* Check distance betwee HW and SW location: */ ++ /* If distance between HW and SW pointers is less than max_deep descriptors */ ++ /* Race condition is possible, so wait end of TX and restart TXQ */ ++ while(deep < max_deep) ++ { ++ pTxLastDesc = TX_PREV_DESC_PTR(pTxLastDesc, pQueueCtrl); ++ if(ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pTxLastDesc) == txCurrReg) ++ { ++ int count = 0; ++ ++ while( (txEnReg & MV_32BIT_LE_FAST(ETH_TXQ_ENABLE_MASK)) != 0) ++ { ++ count++; ++ if(count > 10000) ++ { ++ mvOsPrintf("mvEthPortTxEnable: timeout - TXQ_CMD=0x%08x\n", ++ MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) ); ++ break; ++ } ++ txEnReg = MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)); ++ } ++ ++ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) = pPortCtrl->portTxQueueCmdReg; ++ return count; ++ } ++ deep++; ++ } ++ /* Distance between HW and SW pointers is more than max_deep descriptors, */ ++ /* So NO race condition - do nothing */ ++ return -1; ++} ++ ++ ++/* defines */ ++#define ETH_CSUM_MIN_BYTE_COUNT 72 ++ ++/* Tailgate and Kirwood have only 2K TX FIFO */ ++#if (MV_ETH_VERSION == 2) || (MV_ETH_VERSION == 4) ++#define ETH_CSUM_MAX_BYTE_COUNT 1600 ++#else ++#define ETH_CSUM_MAX_BYTE_COUNT 9*1024 ++#endif /* MV_ETH_VERSION */ ++ ++#define ETH_MV_HEADER_SIZE 2 ++#define ETH_MV_TX_EN ++ ++/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */ ++#define MIN_TX_BUFF_LOAD 8 ++#define TX_BUF_OFFSET_IN_DESC (ETH_TX_DESC_ALIGNED_SIZE - MIN_TX_BUFF_LOAD) ++ ++/* Default port configuration value */ ++#define PORT_CONFIG_VALUE \ ++ ETH_DEF_RX_QUEUE_MASK(0) | \ ++ ETH_DEF_RX_ARP_QUEUE_MASK(0) | \ ++ ETH_DEF_RX_TCP_QUEUE_MASK(0) | \ ++ ETH_DEF_RX_UDP_QUEUE_MASK(0) | \ ++ ETH_DEF_RX_BPDU_QUEUE_MASK(0) | \ ++ ETH_RX_CHECKSUM_WITH_PSEUDO_HDR ++ ++/* Default port extend configuration value */ ++#define PORT_CONFIG_EXTEND_VALUE 0 ++ ++#define PORT_SERIAL_CONTROL_VALUE \ ++ ETH_DISABLE_FC_AUTO_NEG_MASK | \ ++ BIT9 | \ ++ ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ ++ ETH_MAX_RX_PACKET_1552BYTE | \ ++ ETH_SET_FULL_DUPLEX_MASK ++ ++#define PORT_SERIAL_CONTROL_100MB_FORCE_VALUE \ ++ ETH_FORCE_LINK_PASS_MASK | \ ++ ETH_DISABLE_DUPLEX_AUTO_NEG_MASK | \ ++ ETH_DISABLE_FC_AUTO_NEG_MASK | \ ++ BIT9 | \ ++ ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ ++ ETH_DISABLE_SPEED_AUTO_NEG_MASK | \ ++ ETH_SET_FULL_DUPLEX_MASK | \ ++ ETH_SET_MII_SPEED_100_MASK | \ ++ ETH_MAX_RX_PACKET_1552BYTE ++ ++ ++#define PORT_SERIAL_CONTROL_1000MB_FORCE_VALUE \ ++ ETH_FORCE_LINK_PASS_MASK | \ ++ ETH_DISABLE_DUPLEX_AUTO_NEG_MASK | \ ++ ETH_DISABLE_FC_AUTO_NEG_MASK | \ ++ BIT9 | \ ++ ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ ++ ETH_DISABLE_SPEED_AUTO_NEG_MASK | \ ++ ETH_SET_FULL_DUPLEX_MASK | \ ++ ETH_SET_GMII_SPEED_1000_MASK | \ ++ ETH_MAX_RX_PACKET_1552BYTE ++ ++#define PORT_SERIAL_CONTROL_SGMII_IBAN_VALUE \ ++ ETH_DISABLE_FC_AUTO_NEG_MASK | \ ++ BIT9 | \ ++ ETH_IN_BAND_AN_EN_MASK | \ ++ ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ ++ ETH_MAX_RX_PACKET_1552BYTE ++ ++/* Function headers: */ ++MV_VOID mvEthSetSpecialMcastTable(int portNo, int queue); ++MV_STATUS mvEthArpRxQueue(void* pPortHandle, int arpQueue); ++MV_STATUS mvEthUdpRxQueue(void* pPortHandle, int udpQueue); ++MV_STATUS mvEthTcpRxQueue(void* pPortHandle, int tcpQueue); ++MV_STATUS mvEthMacAddrGet(int portNo, unsigned char *pAddr); ++MV_VOID mvEthSetOtherMcastTable(int portNo, int queue); ++MV_STATUS mvEthHeaderModeSet(void* pPortHandle, MV_ETH_HEADER_MODE headerMode); ++/* Interrupt Coalesting functions */ ++MV_U32 mvEthRxCoalSet(void* pPortHndl, MV_U32 uSec); ++MV_U32 mvEthTxCoalSet(void* pPortHndl, MV_U32 uSec); ++MV_STATUS mvEthCoalGet(void* pPortHndl, MV_U32* pRxCoal, MV_U32* pTxCoal); ++ ++/******************************************************************************/ ++/* Data Flow functions */ ++/******************************************************************************/ ++static INLINE void mvEthPortTxRestart(void* pPortHndl) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ ++ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) = pPortCtrl->portTxQueueCmdReg; ++} ++ ++/* Get number of Free resources in specific TX queue */ ++static INLINE int mvEthTxResourceGet(void* pPortHndl, int txQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ ++ return (pPortCtrl->txQueue[txQueue].resource); ++} ++ ++/* Get number of Free resources in specific RX queue */ ++static INLINE int mvEthRxResourceGet(void* pPortHndl, int rxQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ ++ return (pPortCtrl->rxQueue[rxQueue].resource); ++} ++ ++static INLINE int mvEthTxQueueIsFull(void* pPortHndl, int txQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ ++ if(pPortCtrl->txQueue[txQueue].resource == 0) ++ return MV_TRUE; ++ ++ return MV_FALSE; ++} ++ ++/* Get number of Free resources in specific RX queue */ ++static INLINE int mvEthRxQueueIsFull(void* pPortHndl, int rxQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->rxQueue[rxQueue]; ++ ++ if( (pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) && ++ (pQueueCtrl->resource != 0) ) ++ return MV_TRUE; ++ ++ return MV_FALSE; ++} ++ ++static INLINE int mvEthTxQueueIsEmpty(void* pPortHndl, int txQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->txQueue[txQueue]; ++ ++ if( (pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) && ++ (pQueueCtrl->resource != 0) ) ++ { ++ return MV_TRUE; ++ } ++ return MV_FALSE; ++} ++ ++/* Get number of Free resources in specific RX queue */ ++static INLINE int mvEthRxQueueIsEmpty(void* pPortHndl, int rxQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ ++ if(pPortCtrl->rxQueue[rxQueue].resource == 0) ++ return MV_TRUE; ++ ++ return MV_FALSE; ++} ++ ++/******************************************************************************* ++* mvEthPortTx - Send an Ethernet packet ++* ++* DESCRIPTION: ++* This routine send a given packet described by pPktInfo parameter. ++* Single buffer only. ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet Port handler. ++* int txQueue - Number of Tx queue. ++* MV_PKT_INFO *pPktInfo - User packet to send. ++* ++* RETURN: ++* MV_NO_RESOURCE - No enough resources to send this packet. ++* MV_ERROR - Unexpected Fatal error. ++* MV_OK - Packet send successfully. ++* ++*******************************************************************************/ ++static INLINE MV_STATUS mvEthPortTx(void* pEthPortHndl, int txQueue, MV_PKT_INFO* pPktInfo) ++{ ++ ETH_TX_DESC* pTxCurrDesc; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; ++ ETH_QUEUE_CTRL* pQueueCtrl; ++ int portNo; ++ MV_BUF_INFO* pBufInfo = pPktInfo->pFrags; ++ ++#ifdef ETH_DEBUG ++ if(pPortCtrl->portState != MV_ACTIVE) ++ return MV_BAD_STATE; ++#endif /* ETH_DEBUG */ ++ ++ portNo = pPortCtrl->portNo; ++ pQueueCtrl = &pPortCtrl->txQueue[txQueue]; ++ ++ /* Get the Tx Desc ring indexes */ ++ pTxCurrDesc = pQueueCtrl->pCurrentDescr; ++ ++ /* Check if there is enough resources to send the packet */ ++ if(pQueueCtrl->resource == 0) ++ return MV_NO_RESOURCE; ++ ++ pTxCurrDesc->byteCnt = pBufInfo->dataSize; ++ ++ /* Flash Buffer */ ++ if(pPktInfo->pktSize != 0) ++ { ++#ifdef MV_NETBSD ++ pTxCurrDesc->bufPtr = pBufInfo->bufPhysAddr; ++ ETH_PACKET_CACHE_FLUSH(pBufInfo->bufVirtPtr, pPktInfo->pktSize); ++#else ++ pTxCurrDesc->bufPtr = ETH_PACKET_CACHE_FLUSH(pBufInfo->bufVirtPtr, pPktInfo->pktSize); ++#endif ++ pPktInfo->pktSize = 0; ++ } ++ else ++ pTxCurrDesc->bufPtr = pBufInfo->bufPhysAddr; ++ ++ pTxCurrDesc->returnInfo = (MV_ULONG)pPktInfo; ++ ++ /* There is only one buffer in the packet */ ++ /* The OSG might set some bits for checksum offload, so add them to first descriptor */ ++ pTxCurrDesc->cmdSts = pPktInfo->status | ++ ETH_BUFFER_OWNED_BY_DMA | ++ ETH_TX_GENERATE_CRC_MASK | ++ ETH_TX_ENABLE_INTERRUPT_MASK | ++ ETH_TX_ZERO_PADDING_MASK | ++ ETH_TX_FIRST_DESC_MASK | ++ ETH_TX_LAST_DESC_MASK; ++ ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); ++ ++ pQueueCtrl->resource--; ++ pQueueCtrl->pCurrentDescr = TX_NEXT_DESC_PTR(pTxCurrDesc, pQueueCtrl); ++ ++ /* Apply send command */ ++ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(portNo)) = pPortCtrl->portTxQueueCmdReg; ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvEthPortSgTx - Send an Ethernet packet ++* ++* DESCRIPTION: ++* This routine send a given packet described by pBufInfo parameter. It ++* supports transmitting of a packet spaned over multiple buffers. ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet Port handler. ++* int txQueue - Number of Tx queue. ++* MV_PKT_INFO *pPktInfo - User packet to send. ++* ++* RETURN: ++* MV_NO_RESOURCE - No enough resources to send this packet. ++* MV_ERROR - Unexpected Fatal error. ++* MV_OK - Packet send successfully. ++* ++*******************************************************************************/ ++static INLINE MV_STATUS mvEthPortSgTx(void* pEthPortHndl, int txQueue, MV_PKT_INFO* pPktInfo) ++{ ++ ETH_TX_DESC* pTxFirstDesc; ++ ETH_TX_DESC* pTxCurrDesc; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; ++ ETH_QUEUE_CTRL* pQueueCtrl; ++ int portNo, bufCount; ++ MV_BUF_INFO* pBufInfo = pPktInfo->pFrags; ++ MV_U8* pTxBuf; ++ ++#ifdef ETH_DEBUG ++ if(pPortCtrl->portState != MV_ACTIVE) ++ return MV_BAD_STATE; ++#endif /* ETH_DEBUG */ ++ ++ portNo = pPortCtrl->portNo; ++ pQueueCtrl = &pPortCtrl->txQueue[txQueue]; ++ ++ /* Get the Tx Desc ring indexes */ ++ pTxCurrDesc = pQueueCtrl->pCurrentDescr; ++ ++ /* Check if there is enough resources to send the packet */ ++ if(pQueueCtrl->resource < pPktInfo->numFrags) ++ return MV_NO_RESOURCE; ++ ++ /* Remember first desc */ ++ pTxFirstDesc = pTxCurrDesc; ++ ++ bufCount = 0; ++ while(MV_TRUE) ++ { ++ if(pBufInfo[bufCount].dataSize <= MIN_TX_BUFF_LOAD) ++ { ++ /* Buffers with a payload smaller than MIN_TX_BUFF_LOAD (8 bytes) must be aligned */ ++ /* to 64-bit boundary. Two options here: */ ++ /* 1) Usually, copy the payload to the reserved 8 bytes inside descriptor. */ ++ /* 2) In the Half duplex workaround, the reserved 8 bytes inside descriptor are used */ ++ /* as a pointer to the aligned buffer, copy the small payload to this buffer. */ ++ pTxBuf = ((MV_U8*)pTxCurrDesc)+TX_BUF_OFFSET_IN_DESC; ++ mvOsBCopy(pBufInfo[bufCount].bufVirtPtr, pTxBuf, pBufInfo[bufCount].dataSize); ++ pTxCurrDesc->bufPtr = ethDescVirtToPhy(pQueueCtrl, pTxBuf); ++ } ++ else ++ { ++ /* Flash Buffer */ ++#ifdef MV_NETBSD ++ pTxCurrDesc->bufPtr = pBufInfo[bufCount].bufPhysAddr; ++ ETH_PACKET_CACHE_FLUSH(pBufInfo[bufCount].bufVirtPtr, pBufInfo[bufCount].dataSize); ++#else ++ pTxCurrDesc->bufPtr = ETH_PACKET_CACHE_FLUSH(pBufInfo[bufCount].bufVirtPtr, pBufInfo[bufCount].dataSize); ++#endif ++ } ++ ++ pTxCurrDesc->byteCnt = pBufInfo[bufCount].dataSize; ++ bufCount++; ++ ++ if(bufCount >= pPktInfo->numFrags) ++ break; ++ ++ if(bufCount > 1) ++ { ++ /* There is middle buffer of the packet Not First and Not Last */ ++ pTxCurrDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA; ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); ++ } ++ /* Go to next descriptor and next buffer */ ++ pTxCurrDesc = TX_NEXT_DESC_PTR(pTxCurrDesc, pQueueCtrl); ++ } ++ /* Set last desc with DMA ownership and interrupt enable. */ ++ pTxCurrDesc->returnInfo = (MV_ULONG)pPktInfo; ++ if(bufCount == 1) ++ { ++ /* There is only one buffer in the packet */ ++ /* The OSG might set some bits for checksum offload, so add them to first descriptor */ ++ pTxCurrDesc->cmdSts = pPktInfo->status | ++ ETH_BUFFER_OWNED_BY_DMA | ++ ETH_TX_GENERATE_CRC_MASK | ++ ETH_TX_ENABLE_INTERRUPT_MASK | ++ ETH_TX_ZERO_PADDING_MASK | ++ ETH_TX_FIRST_DESC_MASK | ++ ETH_TX_LAST_DESC_MASK; ++ ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); ++ } ++ else ++ { ++ /* Last but not First */ ++ pTxCurrDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA | ++ ETH_TX_ENABLE_INTERRUPT_MASK | ++ ETH_TX_ZERO_PADDING_MASK | ++ ETH_TX_LAST_DESC_MASK; ++ ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); ++ ++ /* Update First when more than one buffer in the packet */ ++ /* The OSG might set some bits for checksum offload, so add them to first descriptor */ ++ pTxFirstDesc->cmdSts = pPktInfo->status | ++ ETH_BUFFER_OWNED_BY_DMA | ++ ETH_TX_GENERATE_CRC_MASK | ++ ETH_TX_FIRST_DESC_MASK; ++ ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxFirstDesc); ++ } ++ /* Update txQueue state */ ++ pQueueCtrl->resource -= bufCount; ++ pQueueCtrl->pCurrentDescr = TX_NEXT_DESC_PTR(pTxCurrDesc, pQueueCtrl); ++ ++ /* Apply send command */ ++ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(portNo)) = pPortCtrl->portTxQueueCmdReg; ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvEthPortTxDone - Free all used Tx descriptors and mBlks. ++* ++* DESCRIPTION: ++* This routine returns the transmitted packet information to the caller. ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet Port handler. ++* int txQueue - Number of Tx queue. ++* ++* OUTPUT: ++* MV_PKT_INFO *pPktInfo - Pointer to packet was sent. ++* ++* RETURN: ++* MV_NOT_FOUND - No transmitted packets to return. Transmit in progress. ++* MV_EMPTY - No transmitted packets to return. TX Queue is empty. ++* MV_ERROR - Unexpected Fatal error. ++* MV_OK - There is transmitted packet in the queue, ++* 'pPktInfo' filled with relevant information. ++* ++*******************************************************************************/ ++static INLINE MV_PKT_INFO* mvEthPortTxDone(void* pEthPortHndl, int txQueue) ++{ ++ ETH_TX_DESC* pTxCurrDesc; ++ ETH_TX_DESC* pTxUsedDesc; ++ ETH_QUEUE_CTRL* pQueueCtrl; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; ++ MV_PKT_INFO* pPktInfo; ++ MV_U32 commandStatus; ++ ++ pQueueCtrl = &pPortCtrl->txQueue[txQueue]; ++ ++ pTxUsedDesc = pQueueCtrl->pUsedDescr; ++ pTxCurrDesc = pQueueCtrl->pCurrentDescr; ++ ++ while(MV_TRUE) ++ { ++ /* No more used descriptors */ ++ commandStatus = pTxUsedDesc->cmdSts; ++ if (commandStatus & (ETH_BUFFER_OWNED_BY_DMA)) ++ { ++ ETH_DESCR_INV(pPortCtrl, pTxUsedDesc); ++ return NULL; ++ } ++ if( (pTxUsedDesc == pTxCurrDesc) && ++ (pQueueCtrl->resource != 0) ) ++ { ++ return NULL; ++ } ++ pQueueCtrl->resource++; ++ pQueueCtrl->pUsedDescr = TX_NEXT_DESC_PTR(pTxUsedDesc, pQueueCtrl); ++ if(commandStatus & (ETH_TX_LAST_DESC_MASK)) ++ { ++ pPktInfo = (MV_PKT_INFO*)pTxUsedDesc->returnInfo; ++ pPktInfo->status = commandStatus; ++ return pPktInfo; ++ } ++ pTxUsedDesc = pQueueCtrl->pUsedDescr; ++ } ++} ++ ++/******************************************************************************* ++* mvEthPortRx - Get new received packets from Rx queue. ++* ++* DESCRIPTION: ++* This routine returns the received data to the caller. There is no ++* data copying during routine operation. All information is returned ++* using pointer to packet information struct passed from the caller. ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet Port handler. ++* int rxQueue - Number of Rx queue. ++* ++* OUTPUT: ++* MV_PKT_INFO *pPktInfo - Pointer to received packet. ++* ++* RETURN: ++* MV_NO_RESOURCE - No free resources in RX queue. ++* MV_ERROR - Unexpected Fatal error. ++* MV_OK - New packet received and 'pBufInfo' structure filled ++* with relevant information. ++* ++*******************************************************************************/ ++static INLINE MV_PKT_INFO* mvEthPortRx(void* pEthPortHndl, int rxQueue) ++{ ++ ETH_RX_DESC *pRxCurrDesc; ++ MV_U32 commandStatus; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; ++ ETH_QUEUE_CTRL* pQueueCtrl; ++ MV_PKT_INFO* pPktInfo; ++ ++ pQueueCtrl = &(pPortCtrl->rxQueue[rxQueue]); ++ ++ /* Check resources */ ++ if(pQueueCtrl->resource == 0) ++ { ++ mvOsPrintf("ethPortRx: no more resources\n"); ++ return NULL; ++ } ++ while(MV_TRUE) ++ { ++ /* Get the Rx Desc ring 'curr and 'used' indexes */ ++ pRxCurrDesc = pQueueCtrl->pCurrentDescr; ++ ++ commandStatus = pRxCurrDesc->cmdSts; ++ if (commandStatus & (ETH_BUFFER_OWNED_BY_DMA)) ++ { ++ /* Nothing to receive... */ ++ ETH_DESCR_INV(pPortCtrl, pRxCurrDesc); ++ return NULL; ++ } ++ ++ /* Valid RX only if FIRST and LAST bits are set */ ++ if( (commandStatus & (ETH_RX_LAST_DESC_MASK | ETH_RX_FIRST_DESC_MASK)) == ++ (ETH_RX_LAST_DESC_MASK | ETH_RX_FIRST_DESC_MASK) ) ++ { ++ pPktInfo = (MV_PKT_INFO*)pRxCurrDesc->returnInfo; ++ pPktInfo->pFrags->dataSize = pRxCurrDesc->byteCnt - 4; ++ pPktInfo->status = commandStatus; ++ pPktInfo->fragIP = pRxCurrDesc->bufSize & ETH_RX_IP_FRAGMENTED_FRAME_MASK; ++ ++ pQueueCtrl->resource--; ++ /* Update 'curr' in data structure */ ++ pQueueCtrl->pCurrentDescr = RX_NEXT_DESC_PTR(pRxCurrDesc, pQueueCtrl); ++ ++#ifdef INCLUDE_SYNC_BARR ++ mvCpuIfSyncBarr(DRAM_TARGET); ++#endif ++ return pPktInfo; ++ } ++ else ++ { ++ ETH_RX_DESC* pRxUsedDesc = pQueueCtrl->pUsedDescr; ++ ++#ifdef ETH_DEBUG ++ mvOsPrintf("ethDrv: Unexpected Jumbo frame: " ++ "status=0x%08x, byteCnt=%d, pData=0x%x\n", ++ commandStatus, pRxCurrDesc->byteCnt, pRxCurrDesc->bufPtr); ++#endif /* ETH_DEBUG */ ++ ++ /* move buffer from pCurrentDescr position to pUsedDescr position */ ++ pRxUsedDesc->bufPtr = pRxCurrDesc->bufPtr; ++ pRxUsedDesc->returnInfo = pRxCurrDesc->returnInfo; ++ pRxUsedDesc->bufSize = pRxCurrDesc->bufSize & ETH_RX_BUFFER_MASK; ++ ++ /* Return the descriptor to DMA ownership */ ++ pRxUsedDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA | ++ ETH_RX_ENABLE_INTERRUPT_MASK; ++ ++ /* Flush descriptor and CPU pipe */ ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxUsedDesc); ++ ++ /* Move the used descriptor pointer to the next descriptor */ ++ pQueueCtrl->pUsedDescr = RX_NEXT_DESC_PTR(pRxUsedDesc, pQueueCtrl); ++ pQueueCtrl->pCurrentDescr = RX_NEXT_DESC_PTR(pRxCurrDesc, pQueueCtrl); ++ } ++ } ++} ++ ++/******************************************************************************* ++* mvEthPortRxDone - Returns a Rx buffer back to the Rx ring. ++* ++* DESCRIPTION: ++* This routine returns a Rx buffer back to the Rx ring. ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet Port handler. ++* int rxQueue - Number of Rx queue. ++* MV_PKT_INFO *pPktInfo - Pointer to received packet. ++* ++* RETURN: ++* MV_ERROR - Unexpected Fatal error. ++* MV_OUT_OF_RANGE - RX queue is already FULL, so this buffer can't be ++* returned to this queue. ++* MV_FULL - Buffer returned successfully and RX queue became full. ++* More buffers should not be returned at the time. ++* MV_OK - Buffer returned successfully and there are more free ++* places in the queue. ++* ++*******************************************************************************/ ++static INLINE MV_STATUS mvEthPortRxDone(void* pEthPortHndl, int rxQueue, MV_PKT_INFO *pPktInfo) ++{ ++ ETH_RX_DESC* pRxUsedDesc; ++ ETH_QUEUE_CTRL* pQueueCtrl; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; ++ ++ pQueueCtrl = &pPortCtrl->rxQueue[rxQueue]; ++ ++ /* Get 'used' Rx descriptor */ ++ pRxUsedDesc = pQueueCtrl->pUsedDescr; ++ ++ /* Check that ring is not FULL */ ++ if( (pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) && ++ (pQueueCtrl->resource != 0) ) ++ { ++ mvOsPrintf("%s %d: out of range Error resource=%d, curr=%p, used=%p\n", ++ __FUNCTION__, pPortCtrl->portNo, pQueueCtrl->resource, ++ pQueueCtrl->pCurrentDescr, pQueueCtrl->pUsedDescr); ++ return MV_OUT_OF_RANGE; ++ } ++ ++ pRxUsedDesc->bufPtr = pPktInfo->pFrags->bufPhysAddr; ++ pRxUsedDesc->returnInfo = (MV_ULONG)pPktInfo; ++ pRxUsedDesc->bufSize = pPktInfo->pFrags->bufSize & ETH_RX_BUFFER_MASK; ++ ++ /* Invalidate data buffer accordingly with pktSize */ ++ if(pPktInfo->pktSize != 0) ++ { ++ ETH_PACKET_CACHE_INVALIDATE(pPktInfo->pFrags->bufVirtPtr, pPktInfo->pktSize); ++ pPktInfo->pktSize = 0; ++ } ++ ++ /* Return the descriptor to DMA ownership */ ++ pRxUsedDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT_MASK; ++ ++ /* Flush descriptor and CPU pipe */ ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxUsedDesc); ++ ++ pQueueCtrl->resource++; ++ ++ /* Move the used descriptor pointer to the next descriptor */ ++ pQueueCtrl->pUsedDescr = RX_NEXT_DESC_PTR(pRxUsedDesc, pQueueCtrl); ++ ++ /* If ring became Full return MV_FULL */ ++ if(pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) ++ return MV_FULL; ++ ++ return MV_OK; ++} ++ ++ ++#endif /* __mvEthGbe_h__ */ ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,700 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvEthRegsh ++#define __INCmvEthRegsh ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++ ++/****************************************/ ++/* Ethernet Unit Registers */ ++/****************************************/ ++#define ETH_REG_BASE MV_ETH_REG_BASE ++ ++#define ETH_PHY_ADDR_REG(port) (ETH_REG_BASE(port) + 0x000) ++#define ETH_SMI_REG(port) (ETH_REG_BASE(port) + 0x004) ++#define ETH_UNIT_DEF_ADDR_REG(port) (ETH_REG_BASE(port) + 0x008) ++#define ETH_UNIT_DEF_ID_REG(port) (ETH_REG_BASE(port) + 0x00c) ++#define ETH_UNIT_RESERVED(port) (ETH_REG_BASE(port) + 0x014) ++#define ETH_UNIT_INTR_CAUSE_REG(port) (ETH_REG_BASE(port) + 0x080) ++#define ETH_UNIT_INTR_MASK_REG(port) (ETH_REG_BASE(port) + 0x084) ++ ++ ++#define ETH_UNIT_ERROR_ADDR_REG(port) (ETH_REG_BASE(port) + 0x094) ++#define ETH_UNIT_INT_ADDR_ERROR_REG(port) (ETH_REG_BASE(port) + 0x098) ++#define ETH_UNIT_CONTROL_REG(port) (ETH_REG_BASE(port) + 0x0B0) ++ ++#define ETH_PORT_CONFIG_REG(port) (ETH_REG_BASE(port) + 0x400) ++#define ETH_PORT_CONFIG_EXTEND_REG(port) (ETH_REG_BASE(port) + 0x404) ++#define ETH_MII_SERIAL_PARAM_REG(port) (ETH_REG_BASE(port) + 0x408) ++#define ETH_GMII_SERIAL_PARAM_REG(port) (ETH_REG_BASE(port) + 0x40c) ++#define ETH_VLAN_ETHER_TYPE_REG(port) (ETH_REG_BASE(port) + 0x410) ++#define ETH_MAC_ADDR_LOW_REG(port) (ETH_REG_BASE(port) + 0x414) ++#define ETH_MAC_ADDR_HIGH_REG(port) (ETH_REG_BASE(port) + 0x418) ++#define ETH_SDMA_CONFIG_REG(port) (ETH_REG_BASE(port) + 0x41c) ++#define ETH_DIFF_SERV_PRIO_REG(port, code) (ETH_REG_BASE(port) + 0x420 + ((code)<<2)) ++#define ETH_PORT_SERIAL_CTRL_REG(port) (ETH_REG_BASE(port) + 0x43c) ++#define ETH_VLAN_TAG_TO_PRIO_REG(port) (ETH_REG_BASE(port) + 0x440) ++#define ETH_PORT_STATUS_REG(port) (ETH_REG_BASE(port) + 0x444) ++ ++#define ETH_RX_QUEUE_COMMAND_REG(port) (ETH_REG_BASE(port) + 0x680) ++#define ETH_TX_QUEUE_COMMAND_REG(port) (ETH_REG_BASE(port) + 0x448) ++ ++#define ETH_PORT_SERIAL_CTRL_1_REG(port) (ETH_REG_BASE(port) + 0x44c) ++#define ETH_PORT_STATUS_1_REG(port) (ETH_REG_BASE(port) + 0x450) ++#define ETH_PORT_MARVELL_HEADER_REG(port) (ETH_REG_BASE(port) + 0x454) ++#define ETH_PORT_FIFO_PARAMS_REG(port) (ETH_REG_BASE(port) + 0x458) ++#define ETH_MAX_TOKEN_BUCKET_SIZE_REG(port) (ETH_REG_BASE(port) + 0x45c) ++#define ETH_INTR_CAUSE_REG(port) (ETH_REG_BASE(port) + 0x460) ++#define ETH_INTR_CAUSE_EXT_REG(port) (ETH_REG_BASE(port) + 0x464) ++#define ETH_INTR_MASK_REG(port) (ETH_REG_BASE(port) + 0x468) ++#define ETH_INTR_MASK_EXT_REG(port) (ETH_REG_BASE(port) + 0x46c) ++#define ETH_TX_FIFO_URGENT_THRESH_REG(port) (ETH_REG_BASE(port) + 0x474) ++#define ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (ETH_REG_BASE(port) + 0x47c) ++#define ETH_RX_DISCARD_PKTS_CNTR_REG(port) (ETH_REG_BASE(port) + 0x484) ++#define ETH_RX_OVERRUN_PKTS_CNTR_REG(port) (ETH_REG_BASE(port) + 0x488) ++#define ETH_INTERNAL_ADDR_ERROR_REG(port) (ETH_REG_BASE(port) + 0x494) ++#define ETH_TX_FIXED_PRIO_CFG_REG(port) (ETH_REG_BASE(port) + 0x4dc) ++#define ETH_TX_TOKEN_RATE_CFG_REG(port) (ETH_REG_BASE(port) + 0x4e0) ++#define ETH_TX_QUEUE_COMMAND1_REG(port) (ETH_REG_BASE(port) + 0x4e4) ++#define ETH_MAX_TRANSMIT_UNIT_REG(port) (ETH_REG_BASE(port) + 0x4e8) ++#define ETH_TX_TOKEN_BUCKET_SIZE_REG(port) (ETH_REG_BASE(port) + 0x4ec) ++#define ETH_TX_TOKEN_BUCKET_COUNT_REG(port) (ETH_REG_BASE(port) + 0x780) ++#define ETH_RX_DESCR_STAT_CMD_REG(port, q) (ETH_REG_BASE(port) + 0x600 + ((q)<<4)) ++#define ETH_RX_BYTE_COUNT_REG(port, q) (ETH_REG_BASE(port) + 0x604 + ((q)<<4)) ++#define ETH_RX_BUF_PTR_REG(port, q) (ETH_REG_BASE(port) + 0x608 + ((q)<<4)) ++#define ETH_RX_CUR_DESC_PTR_REG(port, q) (ETH_REG_BASE(port) + 0x60c + ((q)<<4)) ++#define ETH_TX_CUR_DESC_PTR_REG(port, q) (ETH_REG_BASE(port) + 0x6c0 + ((q)<<2)) ++ ++#define ETH_TXQ_TOKEN_COUNT_REG(port, q) (ETH_REG_BASE(port) + 0x700 + ((q)<<4)) ++#define ETH_TXQ_TOKEN_CFG_REG(port, q) (ETH_REG_BASE(port) + 0x704 + ((q)<<4)) ++#define ETH_TXQ_ARBITER_CFG_REG(port, q) (ETH_REG_BASE(port) + 0x708 + ((q)<<4)) ++ ++#if (MV_ETH_VERSION >= 4) ++#define ETH_TXQ_CMD_1_REG(port) (ETH_REG_BASE(port) + 0x4E4) ++#define ETH_EJP_TX_HI_IPG_REG(port) (ETH_REG_BASE(port) + 0x7A8) ++#define ETH_EJP_TX_LO_IPG_REG(port) (ETH_REG_BASE(port) + 0x7B8) ++#define ETH_EJP_HI_TKN_LO_PKT_REG(port) (ETH_REG_BASE(port) + 0x7C0) ++#define ETH_EJP_HI_TKN_ASYNC_PKT_REG(port) (ETH_REG_BASE(port) + 0x7C4) ++#define ETH_EJP_LO_TKN_ASYNC_PKT_REG(port) (ETH_REG_BASE(port) + 0x7C8) ++#define ETH_EJP_TX_SPEED_REG(port) (ETH_REG_BASE(port) + 0x7D0) ++#endif /* MV_ETH_VERSION >= 4 */ ++ ++#define ETH_MIB_COUNTERS_BASE(port) (ETH_REG_BASE(port) + 0x1000) ++#define ETH_DA_FILTER_SPEC_MCAST_BASE(port) (ETH_REG_BASE(port) + 0x1400) ++#define ETH_DA_FILTER_OTH_MCAST_BASE(port) (ETH_REG_BASE(port) + 0x1500) ++#define ETH_DA_FILTER_UCAST_BASE(port) (ETH_REG_BASE(port) + 0x1600) ++ ++/* Phy address register definitions */ ++#define ETH_PHY_ADDR_OFFS 0 ++#define ETH_PHY_ADDR_MASK (0x1f <= 4) ++#define ETH_TX_EJP_RESET_BIT 0 ++#define ETH_TX_EJP_RESET_MASK (1 << ETH_TX_EJP_RESET_BIT) ++ ++#define ETH_TX_EJP_ENABLE_BIT 2 ++#define ETH_TX_EJP_ENABLE_MASK (1 << ETH_TX_EJP_ENABLE_BIT) ++ ++#define ETH_TX_LEGACY_WRR_BIT 3 ++#define ETH_TX_LEGACY_WRR_MASK (1 << ETH_TX_LEGACY_WRR_BIT) ++#endif /* (MV_ETH_VERSION >= 4) */ ++ ++/***** BITs of Ethernet Port Status reg (PSR) *****/ ++#define ETH_LINK_UP_BIT 1 ++#define ETH_LINK_UP_MASK (1<= 4) ++MV_STATUS mvEthEjpModeSet(void* pPortHandle, int mode); ++#endif /* (MV_ETH_VERSION >= 4) */ ++ ++void mvEthStatusGet(void* pPortHandle, MV_ETH_PORT_STATUS* pStatus); ++ ++/* Marvell Header control */ ++MV_STATUS mvEthHeaderModeSet(void* pPortHandle, MV_ETH_HEADER_MODE headerMode); ++ ++/* PHY routines */ ++void mvEthPhyAddrSet(void* pPortHandle, int phyAddr); ++int mvEthPhyAddrGet(void* pPortHandle); ++ ++/* Power management routines */ ++void mvEthPortPowerDown(int port); ++void mvEthPortPowerUp(int port); ++ ++/******************** ETH PRIVATE ************************/ ++ ++/*#define UNCACHED_TX_BUFFERS*/ ++/*#define UNCACHED_RX_BUFFERS*/ ++ ++ ++/* Port attributes */ ++/* Size of a Tx/Rx descriptor used in chain list data structure */ ++#define ETH_RX_DESC_ALIGNED_SIZE 32 ++#define ETH_TX_DESC_ALIGNED_SIZE 32 ++ ++#define TX_DISABLE_TIMEOUT_MSEC 1000 ++#define RX_DISABLE_TIMEOUT_MSEC 1000 ++#define TX_FIFO_EMPTY_TIMEOUT_MSEC 10000 ++#define PORT_DISABLE_WAIT_TCLOCKS 5000 ++ ++/* Macros that save access to desc in order to find next desc pointer */ ++#define RX_NEXT_DESC_PTR(pRxDescr, pQueueCtrl) \ ++ ((pRxDescr) == (pQueueCtrl)->pLastDescr) ? \ ++ (ETH_RX_DESC*)((pQueueCtrl)->pFirstDescr) : \ ++ (ETH_RX_DESC*)(((MV_ULONG)(pRxDescr)) + ETH_RX_DESC_ALIGNED_SIZE) ++ ++#define TX_NEXT_DESC_PTR(pTxDescr, pQueueCtrl) \ ++ ((pTxDescr) == (pQueueCtrl)->pLastDescr) ? \ ++ (ETH_TX_DESC*)((pQueueCtrl)->pFirstDescr) : \ ++ (ETH_TX_DESC*)(((MV_ULONG)(pTxDescr)) + ETH_TX_DESC_ALIGNED_SIZE) ++ ++#define RX_PREV_DESC_PTR(pRxDescr, pQueueCtrl) \ ++ ((pRxDescr) == (pQueueCtrl)->pFirstDescr) ? \ ++ (ETH_RX_DESC*)((pQueueCtrl)->pLastDescr) : \ ++ (ETH_RX_DESC*)(((MV_ULONG)(pRxDescr)) - ETH_RX_DESC_ALIGNED_SIZE) ++ ++#define TX_PREV_DESC_PTR(pTxDescr, pQueueCtrl) \ ++ ((pTxDescr) == (pQueueCtrl)->pFirstDescr) ? \ ++ (ETH_TX_DESC*)((pQueueCtrl)->pLastDescr) : \ ++ (ETH_TX_DESC*)(((MV_ULONG)(pTxDescr)) - ETH_TX_DESC_ALIGNED_SIZE) ++ ++ ++/* Queue specific information */ ++typedef struct ++{ ++ void* pFirstDescr; ++ void* pLastDescr; ++ void* pCurrentDescr; ++ void* pUsedDescr; ++ int resource; ++ MV_BUF_INFO descBuf; ++} ETH_QUEUE_CTRL; ++ ++ ++/* Ethernet port specific infomation */ ++typedef struct _ethPortCtrl ++{ ++ int portNo; ++ ETH_QUEUE_CTRL rxQueue[MV_ETH_RX_Q_NUM]; /* Rx ring resource */ ++ ETH_QUEUE_CTRL txQueue[MV_ETH_TX_Q_NUM]; /* Tx ring resource */ ++ ++ MV_ETH_PORT_CFG portConfig; ++ MV_ETH_RX_Q_CFG rxQueueConfig[MV_ETH_RX_Q_NUM]; ++ MV_ETH_TX_Q_CFG txQueueConfig[MV_ETH_TX_Q_NUM]; ++ ++ /* Register images - For DP */ ++ MV_U32 portTxQueueCmdReg; /* Port active Tx queues summary */ ++ MV_U32 portRxQueueCmdReg; /* Port active Rx queues summary */ ++ ++ MV_STATE portState; ++ ++ MV_U8 mcastCount[256]; ++ MV_U32* hashPtr; ++ void *osHandle; ++} ETH_PORT_CTRL; ++ ++/************** MACROs ****************/ ++ ++/* MACROs to Flush / Invalidate TX / RX Buffers */ ++#if (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) && !defined(UNCACHED_TX_BUFFERS) ++# define ETH_PACKET_CACHE_FLUSH(pAddr, size) \ ++ mvOsCacheClear(NULL, (pAddr), (size)); \ ++ /*CPU_PIPE_FLUSH;*/ ++#else ++# define ETH_PACKET_CACHE_FLUSH(pAddr, size) \ ++ mvOsIoVirtToPhy(NULL, (pAddr)); ++#endif /* ETHER_DRAM_COHER == MV_CACHE_COHER_SW */ ++ ++#if ( (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) && !defined(UNCACHED_RX_BUFFERS) ) ++# define ETH_PACKET_CACHE_INVALIDATE(pAddr, size) \ ++ mvOsCacheInvalidate (NULL, (pAddr), (size)); \ ++ /*CPU_PIPE_FLUSH;*/ ++#else ++# define ETH_PACKET_CACHE_INVALIDATE(pAddr, size) ++#endif /* ETHER_DRAM_COHER == MV_CACHE_COHER_SW && !UNCACHED_RX_BUFFERS */ ++ ++#ifdef ETH_DESCR_UNCACHED ++ ++#define ETH_DESCR_FLUSH_INV(pPortCtrl, pDescr) ++#define ETH_DESCR_INV(pPortCtrl, pDescr) ++ ++#else ++ ++#define ETH_DESCR_FLUSH_INV(pPortCtrl, pDescr) \ ++ mvOsCacheLineFlushInv(pPortCtrl->osHandle, (MV_ULONG)(pDescr)) ++ ++#define ETH_DESCR_INV(pPortCtrl, pDescr) \ ++ mvOsCacheLineInv(pPortCtrl->osHandle, (MV_ULONG)(pDescr)) ++ ++#endif /* ETH_DESCR_UNCACHED */ ++ ++#include "eth/gbe/mvEthGbe.h" ++ ++#endif /* __mvEth_h__ */ ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvCompVer.txt linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvCompVer.txt +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvCompVer.txt 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvCompVer.txt 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,4 @@ ++Global HAL Version: FEROCEON_HAL_3_1_7 ++Unit HAL Version: 3.1.4 ++Description: This component includes an implementation of the unit HAL drivers ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,362 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#include "gpp/mvGpp.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++/* defines */ ++#ifdef MV_DEBUG ++ #define DB(x) x ++#else ++ #define DB(x) ++#endif ++ ++static MV_VOID gppRegSet(MV_U32 group, MV_U32 regOffs,MV_U32 mask,MV_U32 value); ++ ++/******************************************************************************* ++* mvGppTypeSet - Enable a GPP (OUT) pin ++* ++* DESCRIPTION: ++* ++* INPUT: ++* group - GPP group number ++* mask - 32bit mask value. Each set bit in the mask means that the type ++* of corresponding GPP will be set. Other GPPs are ignored. ++* value - 32bit value that describes GPP type per pin. ++* ++* OUTPUT: ++* None. ++* ++* EXAMPLE: ++* Set GPP8 to input and GPP15 to output. ++* mvGppTypeSet(0, (GPP8 | GPP15), ++* ((MV_GPP_IN & GPP8) | (MV_GPP_OUT & GPP15)) ); ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_STATUS mvGppTypeSet(MV_U32 group, MV_U32 mask, MV_U32 value) ++{ ++ if (group >= MV_GPP_MAX_GROUP) ++ { ++ DB(mvOsPrintf("mvGppTypeSet: ERR. invalid group number \n")); ++ return MV_BAD_PARAM; ++ } ++ ++ gppRegSet(group, GPP_DATA_OUT_EN_REG(group), mask, value); ++ ++ /* Workaround for Erratum FE-MISC-70*/ ++ if(mvCtrlRevGet()==MV_88F6XXX_A0_REV && (group == 1)) ++ { ++ mask &= 0x2; ++ gppRegSet(0, GPP_DATA_OUT_EN_REG(0), mask, value); ++ } /*End of WA*/ ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvGppBlinkEn - Set a GPP (IN) Pin list to blink every ~100ms ++* ++* DESCRIPTION: ++* ++* INPUT: ++* group - GPP group number ++* mask - 32bit mask value. Each set bit in the mask means that the type ++* of corresponding GPP will be set. Other GPPs are ignored. ++* value - 32bit value that describes GPP blink per pin. ++* ++* OUTPUT: ++* None. ++* ++* EXAMPLE: ++* Set GPP8 to be static and GPP15 to be blinking. ++* mvGppBlinkEn(0, (GPP8 | GPP15), ++* ((MV_GPP_OUT_STATIC & GPP8) | (MV_GPP_OUT_BLINK & GPP15)) ); ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_STATUS mvGppBlinkEn(MV_U32 group, MV_U32 mask, MV_U32 value) ++{ ++ if (group >= MV_GPP_MAX_GROUP) ++ { ++ DB(mvOsPrintf("mvGppBlinkEn: ERR. invalid group number \n")); ++ return MV_BAD_PARAM; ++ } ++ ++ gppRegSet(group, GPP_BLINK_EN_REG(group), mask, value); ++ ++ return MV_OK; ++ ++} ++/******************************************************************************* ++* mvGppPolaritySet - Set a GPP (IN) Pin list Polarity mode ++* ++* DESCRIPTION: ++* ++* INPUT: ++* group - GPP group number ++* mask - 32bit mask value. Each set bit in the mask means that the type ++* of corresponding GPP will be set. Other GPPs are ignored. ++* value - 32bit value that describes GPP polarity per pin. ++* ++* OUTPUT: ++* None. ++* ++* EXAMPLE: ++* Set GPP8 to the actual pin value and GPP15 to be inverted. ++* mvGppPolaritySet(0, (GPP8 | GPP15), ++* ((MV_GPP_IN_ORIGIN & GPP8) | (MV_GPP_IN_INVERT & GPP15)) ); ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_STATUS mvGppPolaritySet(MV_U32 group, MV_U32 mask, MV_U32 value) ++{ ++ if (group >= MV_GPP_MAX_GROUP) ++ { ++ DB(mvOsPrintf("mvGppPolaritySet: ERR. invalid group number \n")); ++ return MV_BAD_PARAM; ++ } ++ ++ gppRegSet(group, GPP_DATA_IN_POL_REG(group), mask, value); ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvGppPolarityGet - Get a value of relevant bits from GPP Polarity register. ++* ++* DESCRIPTION: ++* ++* INPUT: ++* group - GPP group number ++* mask - 32bit mask value. Each set bit in the mask means that the ++* returned value is valid for it. ++* ++* OUTPUT: ++* None. ++* ++* EXAMPLE: ++* Get GPP8 and GPP15 value. ++* mvGppPolarityGet(0, (GPP8 | GPP15)); ++* ++* RETURN: ++* 32bit value that describes GPP polatity mode per pin. ++* ++*******************************************************************************/ ++MV_U32 mvGppPolarityGet(MV_U32 group, MV_U32 mask) ++{ ++ MV_U32 regVal; ++ ++ if (group >= MV_GPP_MAX_GROUP) ++ { ++ DB(mvOsPrintf("mvGppActiveSet: Error invalid group number \n")); ++ return MV_ERROR; ++ } ++ regVal = MV_REG_READ(GPP_DATA_IN_POL_REG(group)); ++ ++ return (regVal & mask); ++} ++ ++/******************************************************************************* ++* mvGppValueGet - Get a GPP Pin list value. ++* ++* DESCRIPTION: ++* This function get GPP value. ++* ++* INPUT: ++* group - GPP group number ++* mask - 32bit mask value. Each set bit in the mask means that the ++* returned value is valid for it. ++* ++* OUTPUT: ++* None. ++* ++* EXAMPLE: ++* Get GPP8 and GPP15 value. ++* mvGppValueGet(0, (GPP8 | GPP15)); ++* ++* RETURN: ++* 32bit value that describes GPP activity mode per pin. ++* ++*******************************************************************************/ ++MV_U32 mvGppValueGet(MV_U32 group, MV_U32 mask) ++{ ++ MV_U32 gppData; ++ ++ gppData = MV_REG_READ(GPP_DATA_IN_REG(group)); ++ ++ gppData &= mask; ++ ++ return gppData; ++ ++} ++ ++/******************************************************************************* ++* mvGppValueSet - Set a GPP Pin list value. ++* ++* DESCRIPTION: ++* This function set value for given GPP pin list. ++* ++* INPUT: ++* group - GPP group number ++* mask - 32bit mask value. Each set bit in the mask means that the ++* value of corresponding GPP will be set accordingly. Other GPP ++* are not affected. ++* value - 32bit value that describes GPP value per pin. ++* ++* OUTPUT: ++* None. ++* ++* EXAMPLE: ++* Set GPP8 value of '0' and GPP15 value of '1'. ++* mvGppActiveSet(0, (GPP8 | GPP15), ((0 & GPP8) | (GPP15)) ); ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_STATUS mvGppValueSet (MV_U32 group, MV_U32 mask, MV_U32 value) ++{ ++ MV_U32 outEnable, tmp; ++ MV_U32 i; ++ ++ if (group >= MV_GPP_MAX_GROUP) ++ { ++ DB(mvOsPrintf("mvGppValueSet: Error invalid group number \n")); ++ return MV_BAD_PARAM; ++ } ++ ++ /* verify that the gpp pin is configured as output */ ++ /* Note that in the register out enabled -> bit = '0'. */ ++ outEnable = ~MV_REG_READ(GPP_DATA_OUT_EN_REG(group)); ++ ++ /* Workaround for Erratum FE-MISC-70*/ ++ if(mvCtrlRevGet()==MV_88F6XXX_A0_REV && (group == 1)) ++ { ++ tmp = ~MV_REG_READ(GPP_DATA_OUT_EN_REG(0)); ++ outEnable &= 0xfffffffd; ++ outEnable |= (tmp & 0x2); ++ } /*End of WA*/ ++ ++ for (i = 0 ; i < 32 ;i++) ++ { ++ if (((mask & (1 << i)) & (outEnable & (1 << i))) != (mask & (1 << i))) ++ { ++ mvOsPrintf("mvGppValueSet: Err. An attempt to set output "\ ++ "value to GPP %d in input mode.\n", i); ++ return MV_ERROR; ++ } ++ } ++ ++ gppRegSet(group, GPP_DATA_OUT_REG(group), mask, value); ++ ++ return MV_OK; ++ ++} ++/******************************************************************************* ++* gppRegSet - Set a specific GPP pin on a specific GPP register ++* ++* DESCRIPTION: ++* This function set a specific GPP pin on a specific GPP register ++* ++* INPUT: ++* regOffs - GPP Register offset ++* group - GPP group number ++* mask - 32bit mask value. Each set bit in the mask means that the ++* value of corresponding GPP will be set accordingly. Other GPP ++* are not affected. ++* value - 32bit value that describes GPP value per pin. ++* ++* OUTPUT: ++* None. ++* ++* EXAMPLE: ++* Set GPP8 value of '0' and GPP15 value of '1'. ++* mvGppActiveSet(0, (GPP8 | GPP15), ((0 & GPP8) | (1 & GPP15)) ); ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++static MV_VOID gppRegSet (MV_U32 group, MV_U32 regOffs,MV_U32 mask,MV_U32 value) ++{ ++ MV_U32 gppData; ++ ++ gppData = MV_REG_READ(regOffs); ++ ++ gppData &= ~mask; ++ ++ gppData |= (value & mask); ++ ++ MV_REG_WRITE(regOffs, gppData); ++} ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,118 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvGppH ++#define __INCmvGppH ++ ++#include "mvCommon.h" ++#include "mvOs.h" ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++#include "gpp/mvGppRegs.h" ++ ++/* These macros describes the GPP type. Each of the GPPs pins can */ ++/* be assigned to act as a general purpose input or output pin. */ ++#define MV_GPP_IN 0xFFFFFFFF /* GPP input */ ++#define MV_GPP_OUT 0 /* GPP output */ ++ ++ ++/* These macros describes the GPP Out Enable. */ ++#define MV_GPP_OUT_DIS 0xFFFFFFFF /* Out pin disabled*/ ++#define MV_GPP_OUT_EN 0 /* Out pin enabled*/ ++ ++/* These macros describes the GPP Out Blinking. */ ++/* When set and the corresponding bit in GPIO Data Out Enable Control */ ++/* Register is enabled, the GPIO pin blinks every ~100 ms (a period of */ ++/* 2^24 TCLK clocks). */ ++#define MV_GPP_OUT_BLINK 0xFFFFFFFF /* Out pin blinking*/ ++#define MV_GPP_OUT_STATIC 0 /* Out pin static*/ ++ ++ ++/* These macros describes the GPP Polarity. */ ++/* When set to 1 GPIO Data In Register reflects the inverted value of the */ ++/* corresponding pin. */ ++ ++#define MV_GPP_IN_INVERT 0xFFFFFFFF /* Inverted value is got*/ ++#define MV_GPP_IN_ORIGIN 0 /* original value is got*/ ++ ++/* mvGppTypeSet - Set PP pin mode (IN or OUT) */ ++MV_STATUS mvGppTypeSet(MV_U32 group, MV_U32 mask, MV_U32 value); ++ ++/* mvGppBlinkEn - Set a GPP (IN) Pin list to blink every ~100ms */ ++MV_STATUS mvGppBlinkEn(MV_U32 group, MV_U32 mask, MV_U32 value); ++ ++/* mvGppPolaritySet - Set a GPP (IN) Pin list Polarity mode. */ ++MV_STATUS mvGppPolaritySet(MV_U32 group, MV_U32 mask, MV_U32 value); ++ ++/* mvGppPolarityGet - Get the Polarity of a GPP Pin */ ++MV_U32 mvGppPolarityGet(MV_U32 group, MV_U32 mask); ++ ++/* mvGppValueGet - Get a GPP Pin list value.*/ ++MV_U32 mvGppValueGet(MV_U32 group, MV_U32 mask); ++ ++ ++/* mvGppValueSet - Set a GPP Pin list value. */ ++MV_STATUS mvGppValueSet (MV_U32 group, MV_U32 mask, MV_U32 value); ++ ++#endif /* #ifndef __INCmvGppH */ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGppRegs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGppRegs.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGppRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGppRegs.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,116 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvGppRegsH ++#define __INCmvGppRegsH ++ ++#define MV_GPP0 BIT0 ++#define MV_GPP1 BIT1 ++#define MV_GPP2 BIT2 ++#define MV_GPP3 BIT3 ++#define MV_GPP4 BIT4 ++#define MV_GPP5 BIT5 ++#define MV_GPP6 BIT6 ++#define MV_GPP7 BIT7 ++#define MV_GPP8 BIT8 ++#define MV_GPP9 BIT9 ++#define MV_GPP10 BIT10 ++#define MV_GPP11 BIT11 ++#define MV_GPP12 BIT12 ++#define MV_GPP13 BIT13 ++#define MV_GPP14 BIT14 ++#define MV_GPP15 BIT15 ++#define MV_GPP16 BIT16 ++#define MV_GPP17 BIT17 ++#define MV_GPP18 BIT18 ++#define MV_GPP19 BIT19 ++#define MV_GPP20 BIT20 ++#define MV_GPP21 BIT21 ++#define MV_GPP22 BIT22 ++#define MV_GPP23 BIT23 ++#define MV_GPP24 BIT24 ++#define MV_GPP25 BIT25 ++#define MV_GPP26 BIT26 ++#define MV_GPP27 BIT27 ++#define MV_GPP28 BIT28 ++#define MV_GPP29 BIT29 ++#define MV_GPP30 BIT30 ++#define MV_GPP31 BIT31 ++ ++ ++/* registers offsets */ ++ ++#define GPP_DATA_OUT_REG(grp) ((grp == 0) ? 0x10100 : 0x10140) ++#define GPP_DATA_OUT_EN_REG(grp) ((grp == 0) ? 0x10104 : 0x10144) ++#define GPP_BLINK_EN_REG(grp) ((grp == 0) ? 0x10108 : 0x10148) ++#define GPP_DATA_IN_POL_REG(grp) ((grp == 0) ? 0x1010C : 0x1014c) ++#define GPP_DATA_IN_REG(grp) ((grp == 0) ? 0x10110 : 0x10150) ++#define GPP_INT_CAUSE_REG(grp) ((grp == 0) ? 0x10114 : 0x10154) ++#define GPP_INT_MASK_REG(grp) ((grp == 0) ? 0x10118 : 0x10158) ++#define GPP_INT_LVL_REG(grp) ((grp == 0) ? 0x1011c : 0x1015c) ++ ++#define GPP_DATA_OUT_SET_REG 0x10120 ++#define GPP_DATA_OUT_CLEAR_REG 0x10124 ++ ++#endif /* #ifndef __INCmvGppRegsH */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvCompVer.txt linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvCompVer.txt +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvCompVer.txt 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvCompVer.txt 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,4 @@ ++Global HAL Version: FEROCEON_HAL_3_1_7 ++Unit HAL Version: 3.1.2 ++Description: This component includes an implementation of the unit HAL drivers ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,1047 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++#include "pci/mvPci.h" ++ ++#include "ctrlEnv/mvCtrlEnvLib.h" ++ ++/* defines */ ++#ifdef MV_DEBUG ++ #define DB(x) x ++#else ++ #define DB(x) ++#endif ++ ++ ++ ++MV_VOID mvPciHalInit(MV_U32 pciIf, MV_PCI_MOD pciIfmod) ++{ ++ if (MV_PCI_MOD_HOST == pciIfmod) ++ { ++ ++ mvPciLocalBusNumSet(pciIf, PCI_HOST_BUS_NUM(pciIf)); ++ mvPciLocalDevNumSet(pciIf, PCI_HOST_DEV_NUM(pciIf)); ++ ++ /* Local device master Enable */ ++ mvPciMasterEnable(pciIf, MV_TRUE); ++ ++ /* Local device slave Enable */ ++ mvPciSlaveEnable(pciIf, mvPciLocalBusNumGet(pciIf), ++ mvPciLocalDevNumGet(pciIf), MV_TRUE); ++ } ++ /* enable CPU-2-PCI ordering */ ++ MV_REG_BIT_SET(PCI_CMD_REG(0), PCR_CPU_TO_PCI_ORDER_EN); ++} ++ ++/******************************************************************************* ++* mvPciCommandSet - Set PCI comman register value. ++* ++* DESCRIPTION: ++* This function sets a given PCI interface with its command register ++* value. ++* ++* INPUT: ++* pciIf - PCI interface number. ++* command - 32bit value to be written to comamnd register. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM if pciIf is not in range otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPciCommandSet(MV_U32 pciIf, MV_U32 command) ++{ ++ MV_U32 locBusNum, locDevNum, regVal; ++ ++ locBusNum = mvPciLocalBusNumGet(pciIf); ++ locDevNum = mvPciLocalDevNumGet(pciIf); ++ ++ /* Parameter checking */ ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciCommandSet: ERR. Invalid PCI IF num %d\n", pciIf); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Set command register */ ++ MV_REG_WRITE(PCI_CMD_REG(pciIf), command); ++ ++ /* Upodate device max outstanding split tarnsaction */ ++ if ((command & PCR_CPU_TO_PCI_ORDER_EN) && ++ (command & PCR_PCI_TO_CPU_ORDER_EN)) ++ { ++ /* Read PCI-X command register */ ++ regVal = mvPciConfigRead (pciIf, locBusNum, locDevNum, 0, PCIX_COMMAND); ++ ++ /* clear bits 22:20 */ ++ regVal &= 0xff8fffff; ++ ++ /* set reset value */ ++ regVal |= (0x3 << 20); ++ ++ /* Write back the value */ ++ mvPciConfigWrite (pciIf, locBusNum, locDevNum, 0, PCIX_COMMAND, regVal); ++ } ++ ++ return MV_OK; ++ ++ ++} ++ ++ ++/******************************************************************************* ++* mvPciModeGet - Get PCI interface mode. ++* ++* DESCRIPTION: ++* This function returns the given PCI interface mode. ++* ++* INPUT: ++* pciIf - PCI interface number. ++* ++* OUTPUT: ++* pPciMode - Pointer to PCI mode structure. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPciModeGet(MV_U32 pciIf, MV_PCI_MODE *pPciMode) ++{ ++ MV_U32 pciMode; ++ ++ /* Parameter checking */ ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciModeGet: ERR. Invalid PCI interface %d\n", pciIf); ++ return MV_BAD_PARAM; ++ } ++ if (NULL == pPciMode) ++ { ++ mvOsPrintf("mvPciModeGet: ERR. pPciMode = NULL \n"); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Read pci mode register */ ++ pciMode = MV_REG_READ(PCI_MODE_REG(pciIf)); ++ ++ switch (pciMode & PMR_PCI_MODE_MASK) ++ { ++ case PMR_PCI_MODE_CONV: ++ pPciMode->pciType = MV_PCI_CONV; ++ ++ if (MV_REG_READ(PCI_DLL_CTRL_REG(pciIf)) & PDC_DLL_EN) ++ { ++ pPciMode->pciSpeed = 66000000; /* 66MHZ */ ++ } ++ else ++ { ++ pPciMode->pciSpeed = 33000000; /* 33MHZ */ ++ } ++ ++ break; ++ ++ case PMR_PCI_MODE_PCIX_66MHZ: ++ pPciMode->pciType = MV_PCIX; ++ pPciMode->pciSpeed = 66000000; /* 66MHZ */ ++ break; ++ ++ case PMR_PCI_MODE_PCIX_100MHZ: ++ pPciMode->pciType = MV_PCIX; ++ pPciMode->pciSpeed = 100000000; /* 100MHZ */ ++ break; ++ ++ case PMR_PCI_MODE_PCIX_133MHZ: ++ pPciMode->pciType = MV_PCIX; ++ pPciMode->pciSpeed = 133000000; /* 133MHZ */ ++ break; ++ ++ default: ++ { ++ mvOsPrintf("mvPciModeGet: ERR. Non existing mode !!\n"); ++ return MV_ERROR; ++ } ++ } ++ ++ switch (pciMode & PMR_PCI_64_MASK) ++ { ++ case PMR_PCI_64_64BIT: ++ pPciMode->pciWidth = MV_PCI_64; ++ break; ++ ++ case PMR_PCI_64_32BIT: ++ pPciMode->pciWidth = MV_PCI_32; ++ break; ++ ++ default: ++ { ++ mvOsPrintf("mvPciModeGet: ERR. Non existing mode !!\n"); ++ return MV_ERROR; ++ } ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvPciRetrySet - Set PCI retry counters ++* ++* DESCRIPTION: ++* This function specifies the number of times the PCI controller ++* retries a transaction before it quits. ++* Applies to the PCI Master when acting as a requester. ++* Applies to the PCI slave when acting as a completer (PCI-X mode). ++* A 0x00 value means a "retry forever". ++* ++* INPUT: ++* pciIf - PCI interface number. ++* counter - Number of times PCI controller retry. Use counter value ++* up to PRR_RETRY_CNTR_MAX. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPciRetrySet(MV_U32 pciIf, MV_U32 counter) ++{ ++ MV_U32 pciRetry; ++ ++ /* Parameter checking */ ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciRetrySet: ERR. Invalid PCI interface %d\n", pciIf); ++ return MV_BAD_PARAM; ++ } ++ ++ if (counter >= PRR_RETRY_CNTR_MAX) ++ { ++ mvOsPrintf("mvPciRetrySet: ERR. Invalid counter: %d\n", counter); ++ return MV_BAD_PARAM; ++ ++ } ++ ++ /* Reading PCI retry register */ ++ pciRetry = MV_REG_READ(PCI_RETRY_REG(pciIf)); ++ ++ pciRetry &= ~PRR_RETRY_CNTR_MASK; ++ ++ pciRetry |= (counter << PRR_RETRY_CNTR_OFFS); ++ ++ /* write new value */ ++ MV_REG_WRITE(PCI_RETRY_REG(pciIf), pciRetry); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvPciDiscardTimerSet - Set PCI discard timer ++* ++* DESCRIPTION: ++* This function set PCI discard timer. ++* In conventional PCI mode: ++* Specifies the number of PCLK cycles the PCI slave keeps a non-accessed ++* read buffers (non-completed delayed read) before invalidate the buffer. ++* Set to '0' to disable the timer. The PCI slave waits for delayed ++* read completion forever. ++* In PCI-X mode: ++* Specifies the number of PCLK cycles the PCI master waits for split ++* completion transaction, before it invalidates the pre-allocated read ++* buffer. ++* Set to '0' to disable the timer. The PCI master waits for split ++* completion forever. ++* NOTE: Must be set to a number greater than MV_PCI_MAX_DISCARD_CLK, ++* unless using the "wait for ever" setting 0x0. ++* NOTE: Must not be updated while there are pending read requests. ++* ++* INPUT: ++* pciIf - PCI interface number. ++* pClkCycles - Number of PCI clock cycles. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPciDiscardTimerSet(MV_U32 pciIf, MV_U32 pClkCycles) ++{ ++ MV_U32 pciDiscardTimer; ++ ++ /* Parameter checking */ ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciDiscardTimerSet: ERR. Invalid PCI interface %d\n", ++ pciIf); ++ return MV_BAD_PARAM; ++ } ++ ++ if (pClkCycles >= PDTR_TIMER_MIN) ++ { ++ mvOsPrintf("mvPciDiscardTimerSet: ERR. Invalid Clk value: %d\n", ++ pClkCycles); ++ return MV_BAD_PARAM; ++ ++ } ++ ++ /* Read PCI Discard Timer */ ++ pciDiscardTimer = MV_REG_READ(PCI_DISCARD_TIMER_REG(pciIf)); ++ ++ pciDiscardTimer &= ~PDTR_TIMER_MASK; ++ ++ pciDiscardTimer |= (pClkCycles << PDTR_TIMER_OFFS); ++ ++ /* Write new value */ ++ MV_REG_WRITE(PCI_DISCARD_TIMER_REG(pciIf), pciDiscardTimer); ++ ++ return MV_OK; ++ ++} ++ ++/* PCI Arbiter routines */ ++ ++/******************************************************************************* ++* mvPciArbEnable - PCI arbiter enable/disable ++* ++* DESCRIPTION: ++* This fuction enable/disables a given PCI interface arbiter. ++* NOTE: Arbiter setting can not be changed while in work. It should only ++* be set once. ++* INPUT: ++* pciIf - PCI interface number. ++* enable - Enable/disable parameter. If enable = MV_TRUE then enable. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_STATUS mvPciArbEnable(MV_U32 pciIf, MV_BOOL enable) ++{ ++ MV_U32 regVal; ++ ++ /* Parameter checking */ ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciArbEnable: ERR. Invalid PCI interface %d\n", pciIf); ++ return MV_ERROR; ++ } ++ ++ /* Set PCI Arbiter Control register according to default configuration */ ++ regVal = MV_REG_READ(PCI_ARBITER_CTRL_REG(pciIf)); ++ ++ /* Make sure arbiter disabled before changing its values */ ++ MV_REG_BIT_RESET(PCI_ARBITER_CTRL_REG(pciIf), PACR_ARB_ENABLE); ++ ++ regVal &= ~PCI_ARBITER_CTRL_DEFAULT_MASK; ++ ++ regVal |= PCI_ARBITER_CTRL_DEFAULT; /* Set default configuration */ ++ ++ if (MV_TRUE == enable) ++ { ++ regVal |= PACR_ARB_ENABLE; ++ } ++ else ++ { ++ regVal &= ~PACR_ARB_ENABLE; ++ } ++ ++ /* Write to register */ ++ MV_REG_WRITE(PCI_ARBITER_CTRL_REG(pciIf), regVal); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvPciArbParkDis - Disable arbiter parking on agent ++* ++* DESCRIPTION: ++* This function disables the PCI arbiter from parking on the given agent ++* list. ++* ++* INPUT: ++* pciIf - PCI interface number. ++* pciAgentMask - When a bit in the mask is set to '1', parking on ++* the associated PCI master is disabled. Mask bit ++* refers to bit 0 - 6. For example disable parking on PCI ++* agent 3 set pciAgentMask 0x4 (bit 3 is set). ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_STATUS mvPciArbParkDis(MV_U32 pciIf, MV_U32 pciAgentMask) ++{ ++ MV_U32 pciArbiterCtrl; ++ ++ /* Parameter checking */ ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciArbParkDis: ERR. Invalid PCI interface %d\n", pciIf); ++ return MV_ERROR; ++ } ++ ++ /* Reading Arbiter Control register */ ++ pciArbiterCtrl = MV_REG_READ(PCI_ARBITER_CTRL_REG(pciIf)); ++ ++ /* Arbiter must be disabled before changing parking */ ++ MV_REG_BIT_RESET(PCI_ARBITER_CTRL_REG(pciIf), PACR_ARB_ENABLE); ++ ++ /* do the change */ ++ pciArbiterCtrl &= ~PACR_PARK_DIS_MASK; ++ pciArbiterCtrl |= (pciAgentMask << PACR_PARK_DIS_OFFS); ++ ++ /* writing new value ( if th earbiter was enabled before the change */ ++ /* here it will be reenabled */ ++ MV_REG_WRITE(PCI_ARBITER_CTRL_REG(pciIf), pciArbiterCtrl); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvPciArbBrokDetectSet - Set PCI arbiter broken detection ++* ++* DESCRIPTION: ++* This function sets the maximum number of cycles that the arbiter ++* waits for a PCI master to respond to its grant assertion. If a ++* PCI agent fails to respond within this time, the PCI arbiter aborts ++* the transaction and performs a new arbitration cycle. ++* NOTE: Value must be greater than '1' for conventional PCI and ++* greater than '5' for PCI-X. ++* ++* INPUT: ++* pciIf - PCI interface number. ++* pClkCycles - Number of PCI clock cycles. If equal to '0' the broken ++* master detection is disabled. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPciArbBrokDetectSet(MV_U32 pciIf, MV_U32 pClkCycles) ++{ ++ MV_U32 pciArbiterCtrl; ++ MV_U32 pciMode; ++ ++ /* Parameter checking */ ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciArbBrokDetectSet: ERR. Invalid PCI interface %d\n", ++ pciIf); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Checking PCI mode and if pClkCycles is legal value */ ++ pciMode = MV_REG_READ(PCI_MODE_REG(pciIf)); ++ pciMode &= PMR_PCI_MODE_MASK; ++ ++ if (PMR_PCI_MODE_CONV == pciMode) ++ { ++ if (pClkCycles < PACR_BROKEN_VAL_CONV_MIN) ++ return MV_ERROR; ++ } ++ else ++ { ++ if (pClkCycles < PACR_BROKEN_VAL_PCIX_MIN) ++ return MV_ERROR; ++ } ++ ++ pClkCycles <<= PACR_BROKEN_VAL_OFFS; ++ ++ /* Reading Arbiter Control register */ ++ pciArbiterCtrl = MV_REG_READ(PCI_ARBITER_CTRL_REG(pciIf)); ++ pciArbiterCtrl &= ~PACR_BROKEN_VAL_MASK; ++ pciArbiterCtrl |= pClkCycles; ++ ++ /* Arbiter must be disabled before changing broken detection */ ++ MV_REG_BIT_RESET(PCI_ARBITER_CTRL_REG(pciIf), PACR_ARB_ENABLE); ++ ++ /* writing new value ( if th earbiter was enabled before the change */ ++ /* here it will be reenabled */ ++ ++ MV_REG_WRITE(PCI_ARBITER_CTRL_REG(pciIf), pciArbiterCtrl); ++ ++ return MV_OK; ++} ++ ++/* PCI configuration space read write */ ++ ++/******************************************************************************* ++* mvPciConfigRead - Read from configuration space ++* ++* DESCRIPTION: ++* This function performs a 32 bit read from PCI configuration space. ++* It supports both type 0 and type 1 of Configuration Transactions ++* (local and over bridge). In order to read from local bus segment, use ++* bus number retrieved from mvPciLocalBusNumGet(). Other bus numbers ++* will result configuration transaction of type 1 (over bridge). ++* ++* INPUT: ++* pciIf - PCI interface number. ++* bus - PCI segment bus number. ++* dev - PCI device number. ++* func - Function number. ++* regOffs - Register offset. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit register data, 0xffffffff on error ++* ++*******************************************************************************/ ++MV_U32 mvPciConfigRead (MV_U32 pciIf, MV_U32 bus, MV_U32 dev, MV_U32 func, ++ MV_U32 regOff) ++{ ++ MV_U32 pciData = 0; ++ ++ /* Parameter checking */ ++ if (PCI_DEFAULT_IF != pciIf) ++ { ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciConfigRead: ERR. Invalid PCI interface %d\n",pciIf); ++ return 0xFFFFFFFF; ++ } ++ } ++ ++ if (dev >= MAX_PCI_DEVICES) ++ { ++ DB(mvOsPrintf("mvPciConfigRead: ERR. device number illigal %d\n", dev)); ++ return 0xFFFFFFFF; ++ } ++ ++ if (func >= MAX_PCI_FUNCS) ++ { ++ DB(mvOsPrintf("mvPciConfigRead: ERR. function number illigal %d\n", func)); ++ return 0xFFFFFFFF; ++ } ++ ++ if (bus >= MAX_PCI_BUSSES) ++ { ++ DB(mvOsPrintf("mvPciConfigRead: ERR. bus number illigal %d\n", bus)); ++ return MV_ERROR; ++ } ++ ++ ++ /* Creating PCI address to be passed */ ++ pciData |= (bus << PCAR_BUS_NUM_OFFS); ++ pciData |= (dev << PCAR_DEVICE_NUM_OFFS); ++ pciData |= (func << PCAR_FUNC_NUM_OFFS); ++ pciData |= (regOff & PCAR_REG_NUM_MASK); ++ ++ pciData |= PCAR_CONFIG_EN; ++ ++ /* Write the address to the PCI configuration address register */ ++ MV_REG_WRITE(PCI_CONFIG_ADDR_REG(pciIf), pciData); ++ ++ /* In order to let the PCI controller absorbed the address of the read */ ++ /* transaction we perform a validity check that the address was written */ ++ if(pciData != MV_REG_READ(PCI_CONFIG_ADDR_REG(pciIf))) ++ { ++ return MV_ERROR; ++ } ++ /* Read the Data returned in the PCI Data register */ ++ pciData = MV_REG_READ(PCI_CONFIG_DATA_REG(pciIf)); ++ ++ return pciData; ++} ++ ++/******************************************************************************* ++* mvPciConfigWrite - Write to configuration space ++* ++* DESCRIPTION: ++* This function performs a 32 bit write to PCI configuration space. ++* It supports both type 0 and type 1 of Configuration Transactions ++* (local and over bridge). In order to write to local bus segment, use ++* bus number retrieved from mvPciLocalBusNumGet(). Other bus numbers ++* will result configuration transaction of type 1 (over bridge). ++* ++* INPUT: ++* pciIf - PCI interface number. ++* bus - PCI segment bus number. ++* dev - PCI device number. ++* func - Function number. ++* regOffs - Register offset. ++* data - 32bit data. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPciConfigWrite(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func, MV_U32 regOff, MV_U32 data) ++{ ++ MV_U32 pciData = 0; ++ ++ /* Parameter checking */ ++ if (PCI_DEFAULT_IF != pciIf) ++ { ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciConfigWrite: ERR. Invalid PCI interface %d\n", ++ pciIf); ++ return 0xFFFFFFFF; ++ } ++ } ++ ++ if (dev >= MAX_PCI_DEVICES) ++ { ++ mvOsPrintf("mvPciConfigWrite: ERR. device number illigal %d\n",dev); ++ return MV_BAD_PARAM; ++ } ++ ++ if (func >= MAX_PCI_FUNCS) ++ { ++ mvOsPrintf("mvPciConfigWrite: ERR. function number illigal %d\n", func); ++ return MV_ERROR; ++ } ++ ++ if (bus >= MAX_PCI_BUSSES) ++ { ++ mvOsPrintf("mvPciConfigWrite: ERR. bus number illigal %d\n", bus); ++ return MV_ERROR; ++ } ++ ++ /* Creating PCI address to be passed */ ++ pciData |= (bus << PCAR_BUS_NUM_OFFS); ++ pciData |= (dev << PCAR_DEVICE_NUM_OFFS); ++ pciData |= (func << PCAR_FUNC_NUM_OFFS); ++ pciData |= (regOff & PCAR_REG_NUM_MASK); ++ ++ pciData |= PCAR_CONFIG_EN; ++ ++ /* Write the address to the PCI configuration address register */ ++ MV_REG_WRITE(PCI_CONFIG_ADDR_REG(pciIf), pciData); ++ ++ /* In order to let the PCI controller absorbed the address of the read */ ++ /* transaction we perform a validity check that the address was written */ ++ if(pciData != MV_REG_READ(PCI_CONFIG_ADDR_REG(pciIf))) ++ { ++ return MV_ERROR; ++ } ++ ++ /* Write the Data passed to the PCI Data register */ ++ MV_REG_WRITE(PCI_CONFIG_DATA_REG(pciIf), data); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvPciMasterEnable - Enable/disale PCI interface master transactions. ++* ++* DESCRIPTION: ++* This function performs read modified write to PCI command status ++* (offset 0x4) to set/reset bit 2. After this bit is set, the PCI ++* master is allowed to gain ownership on the bus, otherwise it is ++* incapable to do so. ++* ++* INPUT: ++* pciIf - PCI interface number. ++* enable - Enable/disable parameter. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPciMasterEnable(MV_U32 pciIf, MV_BOOL enable) ++{ ++ MV_U32 pciCommandStatus; ++ MV_U32 RegOffs; ++ MV_U32 localBus; ++ MV_U32 localDev; ++ ++ /* Parameter checking */ ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciMasterEnable: ERR. Invalid PCI interface %d\n", pciIf); ++ return MV_ERROR; ++ } ++ ++ localBus = mvPciLocalBusNumGet(pciIf); ++ localDev = mvPciLocalDevNumGet(pciIf); ++ ++ RegOffs = PCI_STATUS_AND_COMMAND; ++ ++ pciCommandStatus = mvPciConfigRead(pciIf, localBus, localDev, 0, RegOffs); ++ ++ if (MV_TRUE == enable) ++ { ++ pciCommandStatus |= PSCR_MASTER_EN; ++ } ++ else ++ { ++ pciCommandStatus &= ~PSCR_MASTER_EN; ++ } ++ ++ mvPciConfigWrite(pciIf, localBus, localDev, 0, RegOffs, pciCommandStatus); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvPciSlaveEnable - Enable/disale PCI interface slave transactions. ++* ++* DESCRIPTION: ++* This function performs read modified write to PCI command status ++* (offset 0x4) to set/reset bit 0 and 1. After those bits are set, ++* the PCI slave is allowed to respond to PCI IO space access (bit 0) ++* and PCI memory space access (bit 1). ++* ++* INPUT: ++* pciIf - PCI interface number. ++* dev - PCI device number. ++* enable - Enable/disable parameter. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPciSlaveEnable(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, MV_BOOL enable) ++{ ++ MV_U32 pciCommandStatus; ++ MV_U32 RegOffs; ++ ++ /* Parameter checking */ ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciSlaveEnable: ERR. Invalid PCI interface %d\n", pciIf); ++ return MV_BAD_PARAM; ++ } ++ if (dev >= MAX_PCI_DEVICES) ++ { ++ mvOsPrintf("mvPciLocalDevNumSet: ERR. device number illigal %d\n", dev); ++ return MV_BAD_PARAM; ++ ++ } ++ ++ RegOffs = PCI_STATUS_AND_COMMAND; ++ ++ pciCommandStatus=mvPciConfigRead(pciIf, bus, dev, 0, RegOffs); ++ ++ if (MV_TRUE == enable) ++ { ++ pciCommandStatus |= (PSCR_IO_EN | PSCR_MEM_EN); ++ } ++ else ++ { ++ pciCommandStatus &= ~(PSCR_IO_EN | PSCR_MEM_EN); ++ } ++ ++ mvPciConfigWrite(pciIf, bus, dev, 0, RegOffs, pciCommandStatus); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvPciLocalBusNumSet - Set PCI interface local bus number. ++* ++* DESCRIPTION: ++* This function sets given PCI interface its local bus number. ++* Note: In case the PCI interface is PCI-X, the information is read-only. ++* ++* INPUT: ++* pciIf - PCI interface number. ++* busNum - Bus number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_NOT_ALLOWED in case PCI interface is PCI-X. ++* MV_BAD_PARAM on bad parameters , ++* otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPciLocalBusNumSet(MV_U32 pciIf, MV_U32 busNum) ++{ ++ MV_U32 pciP2PConfig; ++ MV_PCI_MODE pciMode; ++ MV_U32 localBus; ++ MV_U32 localDev; ++ ++ ++ /* Parameter checking */ ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciLocalBusNumSet: ERR. Invalid PCI interface %d\n",pciIf); ++ return MV_BAD_PARAM; ++ } ++ if (busNum >= MAX_PCI_BUSSES) ++ { ++ mvOsPrintf("mvPciLocalBusNumSet: ERR. bus number illigal %d\n", busNum); ++ return MV_ERROR; ++ ++ } ++ ++ localBus = mvPciLocalBusNumGet(pciIf); ++ localDev = mvPciLocalDevNumGet(pciIf); ++ ++ ++ /* PCI interface mode */ ++ mvPciModeGet(pciIf, &pciMode); ++ ++ /* if PCI type is PCI-X then it is not allowed to change the dev number */ ++ if (MV_PCIX == pciMode.pciType) ++ { ++ pciP2PConfig = mvPciConfigRead(pciIf, localBus, localDev, 0, PCIX_STATUS ); ++ ++ pciP2PConfig &= ~PXS_BN_MASK; ++ ++ pciP2PConfig |= (busNum << PXS_BN_OFFS) & PXS_BN_MASK; ++ ++ mvPciConfigWrite(pciIf, localBus, localDev, 0, PCIX_STATUS,pciP2PConfig ); ++ ++ } ++ else ++ { ++ pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); ++ ++ pciP2PConfig &= ~PPCR_BUS_NUM_MASK; ++ ++ pciP2PConfig |= (busNum << PPCR_BUS_NUM_OFFS) & PPCR_BUS_NUM_MASK; ++ ++ MV_REG_WRITE(PCI_P2P_CONFIG_REG(pciIf), pciP2PConfig); ++ ++ } ++ ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvPciLocalBusNumGet - Get PCI interface local bus number. ++* ++* DESCRIPTION: ++* This function gets the local bus number of a given PCI interface. ++* ++* INPUT: ++* pciIf - PCI interface number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Local bus number.0xffffffff on Error ++* ++*******************************************************************************/ ++MV_U32 mvPciLocalBusNumGet(MV_U32 pciIf) ++{ ++ MV_U32 pciP2PConfig; ++ ++ /* Parameter checking */ ++ if (PCI_DEFAULT_IF != pciIf) ++ { ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciLocalBusNumGet: ERR. Invalid PCI interface %d\n", ++ pciIf); ++ return 0xFFFFFFFF; ++ } ++ } ++ ++ pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); ++ pciP2PConfig &= PPCR_BUS_NUM_MASK; ++ return (pciP2PConfig >> PPCR_BUS_NUM_OFFS); ++} ++ ++ ++/******************************************************************************* ++* mvPciLocalDevNumSet - Set PCI interface local device number. ++* ++* DESCRIPTION: ++* This function sets given PCI interface its local device number. ++* Note: In case the PCI interface is PCI-X, the information is read-only. ++* ++* INPUT: ++* pciIf - PCI interface number. ++* devNum - Device number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_NOT_ALLOWED in case PCI interface is PCI-X. MV_BAD_PARAM on bad parameters , ++* otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPciLocalDevNumSet(MV_U32 pciIf, MV_U32 devNum) ++{ ++ MV_U32 pciP2PConfig; ++ MV_PCI_MODE pciMode; ++ MV_U32 localBus; ++ MV_U32 localDev; ++ ++ /* Parameter checking */ ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciLocalDevNumSet: ERR. Invalid PCI interface %d\n",pciIf); ++ return MV_BAD_PARAM; ++ } ++ if (devNum >= MAX_PCI_DEVICES) ++ { ++ mvOsPrintf("mvPciLocalDevNumSet: ERR. device number illigal %d\n", ++ devNum); ++ return MV_BAD_PARAM; ++ ++ } ++ ++ localBus = mvPciLocalBusNumGet(pciIf); ++ localDev = mvPciLocalDevNumGet(pciIf); ++ ++ /* PCI interface mode */ ++ mvPciModeGet(pciIf, &pciMode); ++ ++ /* if PCI type is PCIX then it is not allowed to change the dev number */ ++ if (MV_PCIX == pciMode.pciType) ++ { ++ pciP2PConfig = mvPciConfigRead(pciIf, localBus, localDev, 0, PCIX_STATUS ); ++ ++ pciP2PConfig &= ~PXS_DN_MASK; ++ ++ pciP2PConfig |= (devNum << PXS_DN_OFFS) & PXS_DN_MASK; ++ ++ mvPciConfigWrite(pciIf,localBus, localDev, 0, PCIX_STATUS,pciP2PConfig ); ++ } ++ else ++ { ++ pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); ++ ++ pciP2PConfig &= ~PPCR_DEV_NUM_MASK; ++ ++ pciP2PConfig |= (devNum << PPCR_DEV_NUM_OFFS) & PPCR_DEV_NUM_MASK; ++ ++ MV_REG_WRITE(PCI_P2P_CONFIG_REG(pciIf), pciP2PConfig); ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvPciLocalDevNumGet - Get PCI interface local device number. ++* ++* DESCRIPTION: ++* This function gets the local device number of a given PCI interface. ++* ++* INPUT: ++* pciIf - PCI interface number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Local device number. 0xffffffff on Error ++* ++*******************************************************************************/ ++MV_U32 mvPciLocalDevNumGet(MV_U32 pciIf) ++{ ++ MV_U32 pciP2PConfig; ++ ++ /* Parameter checking */ ++ ++ if (PCI_DEFAULT_IF != pciIf) ++ { ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciLocalDevNumGet: ERR. Invalid PCI interface %d\n", ++ pciIf); ++ return 0xFFFFFFFF; ++ } ++ } ++ ++ pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); ++ ++ pciP2PConfig &= PPCR_DEV_NUM_MASK; ++ ++ return (pciP2PConfig >> PPCR_DEV_NUM_OFFS); ++} ++ ++ ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,185 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCPCIH ++#define __INCPCIH ++ ++#include "mvCommon.h" ++#include "mvOs.h" ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++#include "pci/mvPciRegs.h" ++ ++ ++/* NOTE not supported in this driver: ++ ++ Built In Self Test (BIST) ++ Vital Product Data (VPD) ++ Message Signaled Interrupt (MSI) ++ Power Management ++ Compact PCI Hot Swap ++ Header retarget ++ ++Registers not supported: ++1) PCI DLL Status and Control (PCI0 0x1D20, PCI1 0x1DA0) ++2) PCI/MPP Pads Calibration (CI0/MPP[31:16] 0x1D1C, PCI1/MPP[15:0] 0X1D9C) ++*/ ++ ++/* defines */ ++/* The number of supported PCI interfaces depend on Marvell controller */ ++/* device number. This device number ID is located on the PCI unit */ ++/* configuration header. This creates a loop where calling PCI */ ++/* configuration read/write routine results a call to get PCI configuration */ ++/* information etc. This macro defines a default PCI interface. This PCI */ ++/* interface is sure to exist. */ ++#define PCI_DEFAULT_IF 0 ++ ++ ++/* typedefs */ ++/* The Marvell controller supports both conventional PCI and PCI-X. */ ++/* This enumeration describes the PCI type. */ ++typedef enum _mvPciType ++{ ++ MV_PCI_CONV, /* Conventional PCI */ ++ MV_PCIX /* PCI-X */ ++}MV_PCI_TYPE; ++ ++typedef enum _mvPciMod ++{ ++ MV_PCI_MOD_HOST, ++ MV_PCI_MOD_DEVICE ++}MV_PCI_MOD; ++ ++ ++/* The Marvell controller supports both PCI width of 32 and 64 bit. */ ++/* This enumerator describes PCI width */ ++typedef enum _mvPciWidth ++{ ++ MV_PCI_32, /* PCI width 32bit */ ++ MV_PCI_64 /* PCI width 64bit */ ++}MV_PCI_WIDTH; ++ ++/* This structure describes the PCI unit configured type, speed and width. */ ++typedef struct _mvPciMode ++{ ++ MV_PCI_TYPE pciType; /* PCI type */ ++ MV_U32 pciSpeed; /* Assuming PCI base clock on board is 33MHz */ ++ MV_PCI_WIDTH pciWidth; /* PCI bus width */ ++}MV_PCI_MODE; ++ ++/* mvPciInit - Initialize PCI interfaces*/ ++MV_VOID mvPciHalInit(MV_U32 pciIf, MV_PCI_MOD pciIfmod); ++ ++/* mvPciCommandSet - Set PCI comman register value.*/ ++MV_STATUS mvPciCommandSet(MV_U32 pciIf, MV_U32 command); ++ ++/* mvPciModeGet - Get PCI interface mode.*/ ++MV_STATUS mvPciModeGet(MV_U32 pciIf, MV_PCI_MODE *pPciMode); ++ ++/* mvPciRetrySet - Set PCI retry counters*/ ++MV_STATUS mvPciRetrySet(MV_U32 pciIf, MV_U32 counter); ++ ++/* mvPciDiscardTimerSet - Set PCI discard timer*/ ++MV_STATUS mvPciDiscardTimerSet(MV_U32 pciIf, MV_U32 pClkCycles); ++ ++/* mvPciArbEnable - PCI arbiter enable/disable*/ ++MV_STATUS mvPciArbEnable(MV_U32 pciIf, MV_BOOL enable); ++ ++/* mvPciArbParkDis - Disable arbiter parking on agent */ ++MV_STATUS mvPciArbParkDis(MV_U32 pciIf, MV_U32 pciAgentMask); ++ ++/* mvPciArbBrokDetectSet - Set PCI arbiter broken detection */ ++MV_STATUS mvPciArbBrokDetectSet(MV_U32 pciIf, MV_U32 pClkCycles); ++ ++/* mvPciConfigRead - Read from configuration space */ ++MV_U32 mvPciConfigRead (MV_U32 pciIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func,MV_U32 regOff); ++ ++/* mvPciConfigWrite - Write to configuration space */ ++MV_STATUS mvPciConfigWrite(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func, MV_U32 regOff, MV_U32 data); ++ ++/* mvPciMasterEnable - Enable/disale PCI interface master transactions.*/ ++MV_STATUS mvPciMasterEnable(MV_U32 pciIf, MV_BOOL enable); ++ ++/* mvPciSlaveEnable - Enable/disale PCI interface slave transactions.*/ ++MV_STATUS mvPciSlaveEnable(MV_U32 pciIf, MV_U32 bus, MV_U32 dev,MV_BOOL enable); ++ ++/* mvPciLocalBusNumSet - Set PCI interface local bus number.*/ ++MV_STATUS mvPciLocalBusNumSet(MV_U32 pciIf, MV_U32 busNum); ++ ++/* mvPciLocalBusNumGet - Get PCI interface local bus number.*/ ++MV_U32 mvPciLocalBusNumGet(MV_U32 pciIf); ++ ++/* mvPciLocalDevNumSet - Set PCI interface local device number.*/ ++MV_STATUS mvPciLocalDevNumSet(MV_U32 pciIf, MV_U32 devNum); ++ ++/* mvPciLocalDevNumGet - Get PCI interface local device number.*/ ++MV_U32 mvPciLocalDevNumGet(MV_U32 pciIf); ++ ++ ++#endif /* #ifndef __INCPCIH */ ++ ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,411 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCPCIREGSH ++#define __INCPCIREGSH ++ ++ ++#include "pci-if/mvPciIfRegs.h" ++/* defines */ ++#define MAX_PCI_DEVICES 32 ++#define MAX_PCI_FUNCS 8 ++#define MAX_PCI_BUSSES 128 ++ ++/* enumerators */ ++ ++/* This enumerator described the possible PCI slave targets. */ ++/* PCI slave targets are designated memory/IO address spaces that the */ ++/* PCI slave targets can access. They are also refered as "targets" */ ++/* this enumeratoe order is determined by the content of : ++ PCI_BASE_ADDR_ENABLE_REG */ ++ ++ ++/* registers offsetes defines */ ++ ++ ++ ++/*************************/ ++/* PCI control registers */ ++/*************************/ ++/* maen : should add new registers */ ++#define PCI_CMD_REG(pciIf) (0x30c00 + ((pciIf) * 0x80)) ++#define PCI_MODE_REG(pciIf) (0x30d00 + ((pciIf) * 0x80)) ++#define PCI_RETRY_REG(pciIf) (0x30c04 + ((pciIf) * 0x80)) ++#define PCI_DISCARD_TIMER_REG(pciIf) (0x30d04 + ((pciIf) * 0x80)) ++#define PCI_ARBITER_CTRL_REG(pciIf) (0x31d00 + ((pciIf) * 0x80)) ++#define PCI_P2P_CONFIG_REG(pciIf) (0x31d14 + ((pciIf) * 0x80)) ++#define PCI_ACCESS_CTRL_BASEL_REG(pciIf, targetWin) \ ++ (0x31e00 + ((pciIf) * 0x80) + ((targetWin) * 0x10)) ++#define PCI_ACCESS_CTRL_BASEH_REG(pciIf, targetWin) \ ++ (0x31e04 + ((pciIf) * 0x80) + ((targetWin) * 0x10)) ++#define PCI_ACCESS_CTRL_SIZE_REG(pciIf, targetWin) \ ++ (0x31e08 + ((pciIf) * 0x80) + ((targetWin) * 0x10)) ++ ++#define PCI_DLL_CTRL_REG(pciIf) (0x31d20 + ((pciIf) * 0x80)) ++ ++/* PCI Dll Control (PDC)*/ ++#define PDC_DLL_EN BIT0 ++ ++ ++/* PCI Command Register (PCR) */ ++#define PCR_MASTER_BYTE_SWAP_EN BIT0 ++#define PCR_MASTER_WR_COMBINE_EN BIT4 ++#define PCR_MASTER_RD_COMBINE_EN BIT5 ++#define PCR_MASTER_WR_TRIG_WHOLE BIT6 ++#define PCR_MASTER_RD_TRIG_WHOLE BIT7 ++#define PCR_MASTER_MEM_RD_LINE_EN BIT8 ++#define PCR_MASTER_MEM_RD_MULT_EN BIT9 ++#define PCR_MASTER_WORD_SWAP_EN BIT10 ++#define PCR_SLAVE_WORD_SWAP_EN BIT11 ++#define PCR_NS_ACCORDING_RCV_TRANS BIT14 ++#define PCR_MASTER_PCIX_REQ64N_EN BIT15 ++#define PCR_SLAVE_BYTE_SWAP_EN BIT16 ++#define PCR_MASTER_DAC_EN BIT17 ++#define PCR_MASTER_M64_ALLIGN BIT18 ++#define PCR_ERRORS_PROPAGATION_EN BIT19 ++#define PCR_SLAVE_SWAP_ENABLE BIT20 ++#define PCR_MASTER_SWAP_ENABLE BIT21 ++#define PCR_MASTER_INT_SWAP_EN BIT22 ++#define PCR_LOOP_BACK_ENABLE BIT23 ++#define PCR_SLAVE_INTREG_SWAP_OFFS 24 ++#define PCR_SLAVE_INTREG_SWAP_MASK 0x3 ++#define PCR_SLAVE_INTREG_BYTE_SWAP \ ++ (MV_BYTE_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) ++#define PCR_SLAVE_INTREG_NO_SWAP \ ++ (MV_NO_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) ++#define PCR_SLAVE_INTREG_BYTE_WORD \ ++ (MV_BYTE_WORD_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) ++#define PCR_SLAVE_INTREG_WORD_SWAP \ ++ (MV_WORD_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) ++#define PCR_RESET_REASSERTION_EN BIT26 ++#define PCR_PCI_TO_CPU_REG_ORDER_EN BIT28 ++#define PCR_CPU_TO_PCI_ORDER_EN BIT29 ++#define PCR_PCI_TO_CPU_ORDER_EN BIT30 ++ ++/* PCI Mode Register (PMR) */ ++#define PMR_PCI_ID_OFFS 0 /* PCI Interface ID */ ++#define PMR_PCI_ID_MASK (0x1 << PMR_PCI_ID_OFFS) ++#define PMR_PCI_ID_PCI(pciNum) ((pciNum) << PCI_MODE_PCIID_OFFS) ++ ++#define PMR_PCI_64_OFFS 2 /* 64-bit PCI Interface */ ++#define PMR_PCI_64_MASK (0x1 << PMR_PCI_64_OFFS) ++#define PMR_PCI_64_64BIT (0x1 << PMR_PCI_64_OFFS) ++#define PMR_PCI_64_32BIT (0x0 << PMR_PCI_64_OFFS) ++ ++#define PMR_PCI_MODE_OFFS 4 /* PCI interface mode of operation */ ++#define PMR_PCI_MODE_MASK (0x3 << PMR_PCI_MODE_OFFS) ++#define PMR_PCI_MODE_CONV (0x0 << PMR_PCI_MODE_OFFS) ++#define PMR_PCI_MODE_PCIX_66MHZ (0x1 << PMR_PCI_MODE_OFFS) ++#define PMR_PCI_MODE_PCIX_100MHZ (0x2 << PMR_PCI_MODE_OFFS) ++#define PMR_PCI_MODE_PCIX_133MHZ (0x3 << PMR_PCI_MODE_OFFS) ++ ++#define PMR_EXP_ROM_SUPPORT BIT8 /* Expansion ROM Active */ ++ ++#define PMR_PCI_RESET_OFFS 31 /* PCI Interface Reset Indication */ ++#define PMR_PCI_RESET_MASK (0x1 << PMR_PCI_RESET_OFFS) ++#define PMR_PCI_RESET_PCIXRST (0x0 << PMR_PCI_RESET_OFFS) ++ ++ ++/* PCI Retry Register (PRR) */ ++#define PRR_RETRY_CNTR_OFFS 16 /* Retry Counter */ ++#define PRR_RETRY_CNTR_MAX 0xff ++#define PRR_RETRY_CNTR_MASK (PRR_RETRY_CNTR_MAX << PRR_RETRY_CNTR_OFFS) ++ ++ ++/* PCI Discard Timer Register (PDTR) */ ++#define PDTR_TIMER_OFFS 0 /* Timer */ ++#define PDTR_TIMER_MAX 0xffff ++#define PDTR_TIMER_MIN 0x7F ++#define PDTR_TIMER_MASK (PDTR_TIMER_MAX << PDTR_TIMER_OFFS) ++ ++ ++/* PCI Arbiter Control Register (PACR) */ ++#define PACR_BROKEN_DETECT_EN BIT1 /* Broken Detection Enable */ ++ ++#define PACR_BROKEN_VAL_OFFS 3 /* Broken Value */ ++#define PACR_BROKEN_VAL_MASK (0xf << PACR_BROKEN_VAL_OFFS) ++#define PACR_BROKEN_VAL_CONV_MIN 0x2 ++#define PACR_BROKEN_VAL_PCIX_MIN 0x6 ++ ++#define PACR_PARK_DIS_OFFS 14 /* Parking Disable */ ++#define PACR_PARK_DIS_MAX_AGENT 0x3f ++#define PACR_PARK_DIS_MASK (PACR_PARK_DIS_MAX_AGENT<= MV_PCI_START_IF)&&(pciIf < MV_PCI_MAX_IF + MV_PCI_START_IF)) ++ { ++ return PCI_IF_TYPE_CONVEN_PCIX; ++ } ++ else if ((pciIf >= MV_PEX_START_IF) && ++ (pciIf < MV_PEX_MAX_IF + MV_PEX_START_IF)) ++ { ++ return PCI_IF_TYPE_PEX; ++ ++ } ++ else ++ { ++ mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf); ++ } ++ ++ return 0xffffffff; ++ ++} ++ ++/******************************************************************************* ++* mvPciIfTypeGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++*******************************************************************************/ ++ ++MV_U32 mvPciRealIfNumGet(MV_U32 pciIf) ++{ ++ ++ PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf); ++ ++ if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType) ++ { ++ return (pciIf - MV_PCI_START_IF); ++ } ++ else if (PCI_IF_TYPE_PEX == pciIfType) ++ { ++ return (pciIf - MV_PEX_START_IF); ++ ++ } ++ else ++ { ++ mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf); ++ } ++ ++ return 0xffffffff; ++ ++} ++ ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,134 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCPCIIFH ++#define __INCPCIIFH ++ ++#include "mvSysHwConfig.h" ++#include "pci-if/mvPciIfRegs.h" ++#if defined(MV_INCLUDE_PEX) ++#include "pex/mvPex.h" ++#endif ++#if defined(MV_INCLUDE_PCI) ++#include "pci/mvPci.h" ++#endif ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "ctrlEnv/mvCtrlEnvAddrDec.h" ++ ++typedef enum _mvPCIIfType ++{ ++ PCI_IF_TYPE_CONVEN_PCIX, ++ PCI_IF_TYPE_PEX ++ ++}PCI_IF_TYPE; ++ ++typedef enum _mvPCIIfMode ++{ ++ PCI_IF_MODE_HOST, ++ PCI_IF_MODE_DEVICE ++}PCI_IF_MODE; ++ ++ ++/* Global Functions prototypes */ ++ ++/* mvPciIfInit - Initialize PCI interfaces*/ ++MV_STATUS mvPciIfInit(MV_U32 pciIf, PCI_IF_MODE pciIfmode); ++ ++/* mvPciIfConfigRead - Read from configuration space */ ++MV_U32 mvPciIfConfigRead (MV_U32 pciIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func,MV_U32 regOff); ++ ++/* mvPciIfConfigWrite - Write to configuration space */ ++MV_STATUS mvPciIfConfigWrite(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func, MV_U32 regOff, MV_U32 data); ++ ++/* mvPciIfMasterEnable - Enable/disale PCI interface master transactions.*/ ++MV_STATUS mvPciIfMasterEnable(MV_U32 pciIf, MV_BOOL enable); ++ ++/* mvPciIfSlaveEnable - Enable/disale PCI interface slave transactions.*/ ++MV_STATUS mvPciIfSlaveEnable(MV_U32 pciIf,MV_U32 bus, MV_U32 dev, ++ MV_BOOL enable); ++ ++/* mvPciIfLocalBusNumSet - Set PCI interface local bus number.*/ ++MV_STATUS mvPciIfLocalBusNumSet(MV_U32 pciIf, MV_U32 busNum); ++ ++/* mvPciIfLocalBusNumGet - Get PCI interface local bus number.*/ ++MV_U32 mvPciIfLocalBusNumGet(MV_U32 pciIf); ++ ++/* mvPciIfLocalDevNumSet - Set PCI interface local device number.*/ ++MV_STATUS mvPciIfLocalDevNumSet(MV_U32 pciIf, MV_U32 devNum); ++ ++/* mvPciIfLocalDevNumGet - Get PCI interface local device number.*/ ++MV_U32 mvPciIfLocalDevNumGet(MV_U32 pciIf); ++ ++/* mvPciIfTypeGet - Get PCI If type*/ ++PCI_IF_TYPE mvPciIfTypeGet(MV_U32 pciIf); ++ ++MV_U32 mvPciRealIfNumGet(MV_U32 pciIf); ++ ++/* mvPciIfAddrDecShow - Display address decode windows attributes */ ++MV_VOID mvPciIfAddrDecShow(MV_VOID); ++ ++#endif /* #ifndef __INCPCIIFH */ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,245 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCPCIIFREGSH ++#define __INCPCIIFREGSH ++ ++ ++/* defines */ ++#define MAX_PCI_DEVICES 32 ++#define MAX_PCI_FUNCS 8 ++#define MAX_PCI_BUSSES 128 ++ ++/***************************************/ ++/* PCI Configuration registers */ ++/***************************************/ ++ ++/*********************************************/ ++/* PCI Configuration, Function 0, Registers */ ++/*********************************************/ ++ ++ ++/* Standard registers */ ++#define PCI_DEVICE_AND_VENDOR_ID 0x000 ++#define PCI_STATUS_AND_COMMAND 0x004 ++#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 ++#define PCI_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE 0x00C ++#define PCI_MEMORY_BAR_BASE_ADDR(barNum) (0x010 + ((barNum) << 2)) ++#define PCI_SUBSYS_ID_AND_SUBSYS_VENDOR_ID 0x02C ++#define PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030 ++#define PCI_CAPABILTY_LIST_POINTER 0x034 ++#define PCI_INTERRUPT_PIN_AND_LINE 0x03C ++ ++ ++/* PCI Device and Vendor ID Register (PDVIR) */ ++#define PDVIR_VEN_ID_OFFS 0 /* Vendor ID */ ++#define PDVIR_VEN_ID_MASK (0xffff << PDVIR_VEN_ID_OFFS) ++ ++#define PDVIR_DEV_ID_OFFS 16 /* Device ID */ ++#define PDVIR_DEV_ID_MASK (0xffff << PDVIR_DEV_ID_OFFS) ++ ++/* PCI Status and Command Register (PSCR) */ ++#define PSCR_IO_EN BIT0 /* IO Enable */ ++#define PSCR_MEM_EN BIT1 /* Memory Enable */ ++#define PSCR_MASTER_EN BIT2 /* Master Enable */ ++#define PSCR_SPECIAL_EN BIT3 /* Special Cycle Enable */ ++#define PSCR_MEM_WRI_INV BIT4 /* Memory Write and Invalidate Enable */ ++#define PSCR_VGA BIT5 /* VGA Palette Snoops */ ++#define PSCR_PERR_EN BIT6 /* Parity Errors Respond Enable */ ++#define PSCR_ADDR_STEP BIT7 /* Address Stepping Enable (Wait Cycle En)*/ ++#define PSCR_SERR_EN BIT8 /* Ability to assert SERR# line */ ++#define PSCR_FAST_BTB_EN BIT9 /* generate fast back-to-back transactions*/ ++#define PSCR_CAP_LIST BIT20 /* Capability List Support */ ++#define PSCR_66MHZ_EN BIT21 /* 66 MHz Capable */ ++#define PSCR_UDF_EN BIT22 /* User definable features */ ++#define PSCR_TAR_FAST_BB BIT23 /* fast back-to-back transactions capable */ ++#define PSCR_DATA_PERR BIT24 /* Data Parity reported */ ++ ++#define PSCR_DEVSEL_TIM_OFFS 25 /* DEVSEL timing */ ++#define PSCR_DEVSEL_TIM_MASK (0x3 << PSCR_DEVSEL_TIM_OFFS) ++#define PSCR_DEVSEL_TIM_FAST (0x0 << PSCR_DEVSEL_TIM_OFFS) ++#define PSCR_DEVSEL_TIM_MED (0x1 << PSCR_DEVSEL_TIM_OFFS) ++#define PSCR_DEVSEL_TIM_SLOW (0x2 << PSCR_DEVSEL_TIM_OFFS) ++ ++#define PSCR_SLAVE_TABORT BIT27 /* Signalled Target Abort */ ++#define PSCR_MASTER_TABORT BIT28 /* Recieved Target Abort */ ++#define PSCR_MABORT BIT29 /* Recieved Master Abort */ ++#define PSCR_SYSERR BIT30 /* Signalled system error */ ++#define PSCR_DET_PARERR BIT31 /* Detect Parity Error */ ++ ++/* PCI configuration register offset=0x08 fields ++ (PCI_CLASS_CODE_AND_REVISION_ID)(PCCRI) */ ++ ++#define PCCRIR_REVID_OFFS 0 /* Revision ID */ ++#define PCCRIR_REVID_MASK (0xff << PCCRIR_REVID_OFFS) ++ ++#define PCCRIR_FULL_CLASS_OFFS 8 /* Full Class Code */ ++#define PCCRIR_FULL_CLASS_MASK (0xffffff << PCCRIR_FULL_CLASS_OFFS) ++ ++#define PCCRIR_PROGIF_OFFS 8 /* Prog .I/F*/ ++#define PCCRIR_PROGIF_MASK (0xff << PCCRIR_PROGIF_OFFS) ++ ++#define PCCRIR_SUB_CLASS_OFFS 16 /* Sub Class*/ ++#define PCCRIR_SUB_CLASS_MASK (0xff << PCCRIR_SUB_CLASS_OFFS) ++ ++#define PCCRIR_BASE_CLASS_OFFS 24 /* Base Class*/ ++#define PCCRIR_BASE_CLASS_MASK (0xff << PCCRIR_BASE_CLASS_OFFS) ++ ++/* PCI configuration register offset=0x0C fields ++ (PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE)(PBHTLTCL) */ ++ ++#define PBHTLTCLR_CACHELINE_OFFS 0 /* Specifies the cache line size */ ++#define PBHTLTCLR_CACHELINE_MASK (0xff << PBHTLTCLR_CACHELINE_OFFS) ++ ++#define PBHTLTCLR_LATTIMER_OFFS 8 /* latency timer */ ++#define PBHTLTCLR_LATTIMER_MASK (0xff << PBHTLTCLR_LATTIMER_OFFS) ++ ++#define PBHTLTCLR_HEADTYPE_FULL_OFFS 16 /* Full Header Type */ ++#define PBHTLTCLR_HEADTYPE_FULL_MASK (0xff << PBHTLTCLR_HEADTYPE_FULL_OFFS) ++ ++#define PBHTLTCLR_MULTI_FUNC BIT23 /* Multi/Single function */ ++ ++#define PBHTLTCLR_HEADER_OFFS 16 /* Header type */ ++#define PBHTLTCLR_HEADER_MASK (0x7f << PBHTLTCLR_HEADER_OFFS) ++#define PBHTLTCLR_HEADER_STANDARD (0x0 << PBHTLTCLR_HEADER_OFFS) ++#define PBHTLTCLR_HEADER_PCI2PCI_BRIDGE (0x1 << PBHTLTCLR_HEADER_OFFS) ++ ++ ++#define PBHTLTCLR_BISTCOMP_OFFS 24 /* BIST Completion Code */ ++#define PBHTLTCLR_BISTCOMP_MASK (0xf << PBHTLTCLR_BISTCOMP_OFFS) ++ ++#define PBHTLTCLR_BISTACT BIT30 /* BIST Activate bit */ ++#define PBHTLTCLR_BISTCAP BIT31 /* BIST Capable Bit */ ++ ++ ++/* PCI Bar Base Low Register (PBBLR) */ ++#define PBBLR_IOSPACE BIT0 /* Memory Space Indicator */ ++ ++#define PBBLR_TYPE_OFFS 1 /* BAR Type/Init Val. */ ++#define PBBLR_TYPE_MASK (0x3 << PBBLR_TYPE_OFFS) ++#define PBBLR_TYPE_32BIT_ADDR (0x0 << PBBLR_TYPE_OFFS) ++#define PBBLR_TYPE_64BIT_ADDR (0x2 << PBBLR_TYPE_OFFS) ++ ++#define PBBLR_PREFETCH_EN BIT3 /* Prefetch Enable */ ++ ++ ++#define PBBLR_MEM_BASE_OFFS 4 /* Memory Bar Base address. Corresponds to ++ address bits [31:4] */ ++#define PBBLR_MEM_BASE_MASK (0xfffffff << PBBLR_MEM_BASE_OFFS) ++ ++#define PBBLR_IO_BASE_OFFS 2 /* IO Bar Base address. Corresponds to ++ address bits [31:2] */ ++#define PBBLR_IO_BASE_MASK (0x3fffffff << PBBLR_IO_BASE_OFFS) ++ ++ ++#define PBBLR_BASE_OFFS 12 /* Base address. Address bits [31:12] */ ++#define PBBLR_BASE_MASK (0xfffff << PBBLR_BASE_OFFS) ++#define PBBLR_BASE_ALIGNMET (1 << PBBLR_BASE_OFFS) ++ ++ ++/* PCI Bar Base High Fegister (PBBHR) */ ++#define PBBHR_BASE_OFFS 0 /* Base address. Address bits [31:12] */ ++#define PBBHR_BASE_MASK (0xffffffff << PBBHR_BASE_OFFS) ++ ++ ++/* PCI configuration register offset=0x2C fields ++ (PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID)(PSISVI) */ ++ ++#define PSISVIR_VENID_OFFS 0 /* Subsystem Manufacturer Vendor ID Number */ ++#define PSISVIR_VENID_MASK (0xffff << PSISVIR_VENID_OFFS) ++ ++#define PSISVIR_DEVID_OFFS 16 /* Subsystem Device ID Number */ ++#define PSISVIR_DEVID_MASK (0xffff << PSISVIR_DEVID_OFFS) ++ ++/* PCI configuration register offset=0x30 fields ++ (PCI_EXPANSION_ROM_BASE_ADDR_REG)(PERBA) */ ++ ++#define PERBAR_EXPROMEN BIT0 /* Expansion ROM Enable */ ++ ++#define PERBAR_BASE_OFFS 12 /* Expansion ROM Base Address */ ++#define PERBAR_BASE_MASK (0xfffff << PERBAR_BASE_OFFS) ++ ++/* PCI configuration register offset=0x34 fields ++ (PCI_CAPABILTY_LIST_POINTER)(PCLP) */ ++ ++#define PCLPR_CAPPTR_OFFS 0 /* Capability List Pointer */ ++#define PCLPR_CAPPTR_MASK (0xff << PCLPR_CAPPTR_OFFS) ++ ++/* PCI configuration register offset=0x3C fields ++ (PCI_INTERRUPT_PIN_AND_LINE)(PIPL) */ ++ ++#define PIPLR_INTLINE_OFFS 0 /* Interrupt line (IRQ) */ ++#define PIPLR_INTLINE_MASK (0xff << PIPLR_INTLINE_OFFS) ++ ++#define PIPLR_INTPIN_OFFS 8 /* interrupt pin (A,B,C,D) */ ++#define PIPLR_INTPIN_MASK (0xff << PIPLR_INTPIN_OFFS) ++ ++#define PIPLR_MINGRANT_OFFS 16 /* Minimum Grant on 250 nano seconds units */ ++#define PIPLR_MINGRANT_MASK (0xff << PIPLR_MINGRANT_OFFS) ++ ++#define PIPLR_MAXLATEN_OFFS 24 /* Maximum latency on 250 nano seconds units */ ++#define PIPLR_MAXLATEN_MASK (0xff << PIPLR_MAXLATEN_OFFS) ++ ++#endif /* #ifndef __INCPCIIFREGSH */ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,1006 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++/* includes */ ++#include "mvPciUtils.h" ++ ++#include "ctrlEnv/mvCtrlEnvLib.h" ++ ++/* #define MV_DEBUG */ ++/* defines */ ++#ifdef MV_DEBUG ++ #define DB(x) x ++ #define mvOsPrintf printf ++#else ++ #define DB(x) ++#endif ++ ++/* ++This module only support scanning of Header type 00h of pci devices ++There is no suppotr for Header type 01h of pci devices ( PCI bridges ) ++*/ ++ ++ ++static MV_STATUS pciDetectDevice(MV_U32 pciIf, ++ MV_U32 bus, ++ MV_U32 dev, ++ MV_U32 func, ++ MV_PCI_DEVICE *pPciAgent); ++ ++static MV_U32 pciDetectDeviceBars(MV_U32 pciIf, ++ MV_U32 bus, ++ MV_U32 dev, ++ MV_U32 func, ++ MV_PCI_DEVICE *pPciAgent); ++ ++ ++ ++ ++ ++ ++/******************************************************************************* ++* mvPciScan - Scan a PCI interface bus ++* ++* DESCRIPTION: ++* Performs a full scan on a PCI interface and returns all possible details ++* on the agents found on the bus. ++* ++* INPUT: ++* pciIf - PCI Interface ++* pPciAgents - Pointer to an Array of the pci agents to be detected ++* pPciAgentsNum - pPciAgents array maximum number of elements ++* ++* OUTPUT: ++* pPciAgents - Array of the pci agents detected on the bus ++* pPciAgentsNum - Number of pci agents detected on the bus ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++ ++MV_STATUS mvPciScan(MV_U32 pciIf, ++ MV_PCI_DEVICE *pPciAgents, ++ MV_U32 *pPciAgentsNum) ++{ ++ ++ MV_U32 devIndex,funcIndex=0,busIndex=0,detectedDevNum=0; ++ MV_U32 localBus=mvPciIfLocalBusNumGet(pciIf); ++ MV_PCI_DEVICE *pPciDevice; ++ MV_PCI_DEVICE *pMainDevice; ++ ++ DB(mvOsPrintf("mvPciScan: PCI interface num %d\n", pciIf)); ++ /* Parameter checking */ ++ if (pciIf >= mvCtrlPexMaxIfGet()) ++ { ++ DB(mvOsPrintf("mvPciScan: ERR. Invalid PCI interface num %d\n", pciIf)); ++ return MV_BAD_PARAM; ++ } ++ if (NULL == pPciAgents) ++ { ++ DB(mvOsPrintf("mvPciScan: ERR. pPciAgents=NULL \n")); ++ return MV_BAD_PARAM; ++ } ++ if (NULL == pPciAgentsNum) ++ { ++ DB(mvOsPrintf("mvPciScan: ERR. pPciAgentsNum=NULL \n")); ++ return MV_BAD_PARAM; ++ } ++ ++ ++ DB(mvOsPrintf("mvPciScan: PCI interface num %d mvPciMasterEnable\n", pciIf)); ++ /* Master enable the MV PCI master */ ++ if (MV_OK != mvPciIfMasterEnable(pciIf,MV_TRUE)) ++ { ++ DB(mvOsPrintf("mvPciScan: ERR. mvPciMasterEnable failed \n")); ++ return MV_ERROR; ++ ++ } ++ ++ DB(mvOsPrintf("mvPciScan: PCI interface num scan%d\n", pciIf)); ++ ++ /* go through all busses */ ++ for (busIndex=localBus ; busIndex < MAX_PCI_BUSSES ; busIndex++) ++ { ++ /* go through all possible devices on the local bus */ ++ for (devIndex=0 ; devIndex < MAX_PCI_DEVICES ; devIndex++) ++ { ++ /* always start with function equal to zero */ ++ funcIndex=0; ++ ++ pPciDevice=&pPciAgents[detectedDevNum]; ++ DB(mvOsPrintf("mvPciScan: PCI interface num scan%d:%d\n", busIndex, devIndex)); ++ ++ if (MV_ERROR == pciDetectDevice(pciIf, ++ busIndex, ++ devIndex, ++ funcIndex, ++ pPciDevice)) ++ { ++ /* no device detected , try the next address */ ++ continue; ++ } ++ ++ /* We are here ! means we have detected a device*/ ++ /* always we start with only one function per device */ ++ pMainDevice = pPciDevice; ++ pPciDevice->funtionsNum = 1; ++ ++ ++ /* move on */ ++ detectedDevNum++; ++ ++ ++ /* check if we have no more room for a new device */ ++ if (detectedDevNum == *pPciAgentsNum) ++ { ++ DB(mvOsPrintf("mvPciScan: ERR. array passed too small \n")); ++ return MV_ERROR; ++ } ++ ++ /* check the detected device if it is a multi functional device then ++ scan all device functions*/ ++ if (pPciDevice->isMultiFunction == MV_TRUE) ++ { ++ /* start with function number 1 because we have already detected ++ function 0 */ ++ for (funcIndex=1; funcIndexfuntionsNum++; ++ detectedDevNum++; ++ ++ /* check if we have no more room for a new device */ ++ if (detectedDevNum == *pPciAgentsNum) ++ { ++ DB(mvOsPrintf("mvPciScan: ERR. Array too small\n")); ++ return MV_ERROR; ++ } ++ ++ ++ } ++ } ++ ++ } ++ ++ } ++ ++ /* return the number of devices actually detected on the bus ! */ ++ *pPciAgentsNum = detectedDevNum; ++ ++ return MV_OK; ++ ++} ++ ++ ++/******************************************************************************* ++* pciDetectDevice - Detect a pci device parameters ++* ++* DESCRIPTION: ++* This function detect if a pci agent exist on certain address ! ++* and if exists then it fills all possible information on the ++* agent ++* ++* INPUT: ++* pciIf - PCI Interface ++* bus - Bus number ++* dev - Device number ++* func - Function number ++* ++* ++* ++* OUTPUT: ++* pPciAgent - pointer to the pci agent filled with its information ++* ++* RETURN: ++* MV_ERROR if no device , MV_OK otherwise ++* ++*******************************************************************************/ ++ ++static MV_STATUS pciDetectDevice(MV_U32 pciIf, ++ MV_U32 bus, ++ MV_U32 dev, ++ MV_U32 func, ++ MV_PCI_DEVICE *pPciAgent) ++{ ++ MV_U32 pciData; ++ ++ /* no Parameters checking ! because it is static function and it is assumed ++ that all parameters were checked in the calling function */ ++ ++ ++ /* Try read the PCI Vendor ID and Device ID */ ++ ++ /* We will scan only ourselves and the PCI slots that exist on the ++ board, because we may have a case that we have one slot that has ++ a Cardbus connector, and because CardBus answers all IDsels we want ++ to scan only this slot and ourseleves. ++ ++ */ ++ #if defined(MV_INCLUDE_PCI) ++ if ((PCI_IF_TYPE_CONVEN_PCIX == mvPciIfTypeGet(pciIf)) && ++ (DB_88F5181_DDR1_PRPMC != mvBoardIdGet()) && ++ (DB_88F5181_DDR1_PEXPCI != mvBoardIdGet()) && ++ (DB_88F5181_DDR1_MNG != mvBoardIdGet())) ++ { ++ ++ if (mvBoardIsOurPciSlot(bus, dev) == MV_FALSE) ++ { ++ return MV_ERROR; ++ } ++ } ++ #endif /* defined(MV_INCLUDE_PCI) */ ++ ++ pciData = mvPciIfConfigRead(pciIf, bus,dev,func, PCI_DEVICE_AND_VENDOR_ID); ++ ++ if (PCI_ERROR_CODE == pciData) ++ { ++ /* no device exist */ ++ return MV_ERROR; ++ } ++ ++ /* we are here ! means a device is detected */ ++ ++ /* fill basic information */ ++ pPciAgent->busNumber=bus; ++ pPciAgent->deviceNum=dev; ++ pPciAgent->function=func; ++ ++ /* Fill the PCI Vendor ID and Device ID */ ++ ++ pPciAgent->venID = (pciData & PDVIR_VEN_ID_MASK) >> PDVIR_VEN_ID_OFFS; ++ pPciAgent->deviceID = (pciData & PDVIR_DEV_ID_MASK) >> PDVIR_DEV_ID_OFFS; ++ ++ /* Read Status and command */ ++ pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ PCI_STATUS_AND_COMMAND); ++ ++ ++ /* Fill related Status and Command information*/ ++ ++ if (pciData & PSCR_TAR_FAST_BB) ++ { ++ pPciAgent->isFastB2BCapable = MV_TRUE; ++ } ++ else ++ { ++ pPciAgent->isFastB2BCapable = MV_FALSE; ++ } ++ ++ if (pciData & PSCR_CAP_LIST) ++ { ++ pPciAgent->isCapListSupport=MV_TRUE; ++ } ++ else ++ { ++ pPciAgent->isCapListSupport=MV_FALSE; ++ } ++ ++ if (pciData & PSCR_66MHZ_EN) ++ { ++ pPciAgent->is66MHZCapable=MV_TRUE; ++ } ++ else ++ { ++ pPciAgent->is66MHZCapable=MV_FALSE; ++ } ++ ++ /* Read Class Code and Revision */ ++ pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ PCI_CLASS_CODE_AND_REVISION_ID); ++ ++ ++ pPciAgent->baseClassCode = ++ (pciData & PCCRIR_BASE_CLASS_MASK) >> PCCRIR_BASE_CLASS_OFFS; ++ ++ pPciAgent->subClassCode = ++ (pciData & PCCRIR_SUB_CLASS_MASK) >> PCCRIR_SUB_CLASS_OFFS; ++ ++ pPciAgent->progIf = ++ (pciData & PCCRIR_PROGIF_MASK) >> PCCRIR_PROGIF_OFFS; ++ ++ pPciAgent->revisionID = ++ (pciData & PCCRIR_REVID_MASK) >> PCCRIR_REVID_OFFS; ++ ++ /* Read PCI_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE */ ++ pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ PCI_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE); ++ ++ ++ ++ pPciAgent->pciCacheLine= ++ (pciData & PBHTLTCLR_CACHELINE_MASK ) >> PBHTLTCLR_CACHELINE_OFFS; ++ pPciAgent->pciLatencyTimer= ++ (pciData & PBHTLTCLR_LATTIMER_MASK) >> PBHTLTCLR_LATTIMER_OFFS; ++ ++ switch (pciData & PBHTLTCLR_HEADER_MASK) ++ { ++ case PBHTLTCLR_HEADER_STANDARD: ++ ++ pPciAgent->pciHeader=MV_PCI_STANDARD; ++ break; ++ case PBHTLTCLR_HEADER_PCI2PCI_BRIDGE: ++ ++ pPciAgent->pciHeader=MV_PCI_PCI2PCI_BRIDGE; ++ break; ++ ++ } ++ ++ if (pciData & PBHTLTCLR_MULTI_FUNC) ++ { ++ pPciAgent->isMultiFunction=MV_TRUE; ++ } ++ else ++ { ++ pPciAgent->isMultiFunction=MV_FALSE; ++ } ++ ++ if (pciData & PBHTLTCLR_BISTCAP) ++ { ++ pPciAgent->isBISTCapable=MV_TRUE; ++ } ++ else ++ { ++ pPciAgent->isBISTCapable=MV_FALSE; ++ } ++ ++ ++ /* read this device pci bars */ ++ ++ pciDetectDeviceBars(pciIf, ++ bus,dev,func, ++ pPciAgent); ++ ++ ++ /* check if we are bridge*/ ++ if ((pPciAgent->baseClassCode == PCI_BRIDGE_CLASS)&& ++ (pPciAgent->subClassCode == P2P_BRIDGE_SUB_CLASS_CODE)) ++ { ++ ++ /* Read P2P_BUSSES_NUM */ ++ pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ P2P_BUSSES_NUM); ++ ++ pPciAgent->p2pPrimBusNum = ++ (pciData & PBM_PRIME_BUS_NUM_MASK) >> PBM_PRIME_BUS_NUM_OFFS; ++ ++ pPciAgent->p2pSecBusNum = ++ (pciData & PBM_SEC_BUS_NUM_MASK) >> PBM_SEC_BUS_NUM_OFFS; ++ ++ pPciAgent->p2pSubBusNum = ++ (pciData & PBM_SUB_BUS_NUM_MASK) >> PBM_SUB_BUS_NUM_OFFS; ++ ++ pPciAgent->p2pSecLatencyTimer = ++ (pciData & PBM_SEC_LAT_TMR_MASK) >> PBM_SEC_LAT_TMR_OFFS; ++ ++ /* Read P2P_IO_BASE_LIMIT_SEC_STATUS */ ++ pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ P2P_IO_BASE_LIMIT_SEC_STATUS); ++ ++ pPciAgent->p2pSecStatus = ++ (pciData & PIBLSS_SEC_STATUS_MASK) >> PIBLSS_SEC_STATUS_OFFS; ++ ++ ++ pPciAgent->p2pIObase = ++ (pciData & PIBLSS_IO_BASE_MASK) << PIBLSS_IO_LIMIT_OFFS; ++ ++ /* clear low address (should be zero)*/ ++ pPciAgent->p2pIObase &= PIBLSS_HIGH_ADDR_MASK; ++ ++ pPciAgent->p2pIOLimit = ++ (pciData & PIBLSS_IO_LIMIT_MASK); ++ ++ /* fill low address with 0xfff */ ++ pPciAgent->p2pIOLimit |= PIBLSS_LOW_ADDR_MASK; ++ ++ ++ switch ((pciData & PIBLSS_ADD_CAP_MASK) >> PIBLSS_ADD_CAP_OFFS) ++ { ++ case PIBLSS_ADD_CAP_16BIT: ++ ++ pPciAgent->bIO32 = MV_FALSE; ++ ++ break; ++ case PIBLSS_ADD_CAP_32BIT: ++ ++ pPciAgent->bIO32 = MV_TRUE; ++ ++ /* Read P2P_IO_BASE_LIMIT_UPPER_16 */ ++ pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ P2P_IO_BASE_LIMIT_UPPER_16); ++ ++ pPciAgent->p2pIObase |= ++ (pciData & PRBU_IO_UPP_BASE_MASK) << PRBU_IO_UPP_LIMIT_OFFS; ++ ++ ++ pPciAgent->p2pIOLimit |= ++ (pciData & PRBU_IO_UPP_LIMIT_MASK); ++ ++ break; ++ ++ } ++ ++ ++ /* Read P2P_MEM_BASE_LIMIT */ ++ pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ P2P_MEM_BASE_LIMIT); ++ ++ pPciAgent->p2pMemBase = ++ (pciData & PMBL_MEM_BASE_MASK) << PMBL_MEM_LIMIT_OFFS; ++ ++ /* clear low address */ ++ pPciAgent->p2pMemBase &= PMBL_HIGH_ADDR_MASK; ++ ++ pPciAgent->p2pMemLimit = ++ (pciData & PMBL_MEM_LIMIT_MASK); ++ ++ /* add 0xfffff */ ++ pPciAgent->p2pMemLimit |= PMBL_LOW_ADDR_MASK; ++ ++ ++ /* Read P2P_PREF_MEM_BASE_LIMIT */ ++ pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ P2P_PREF_MEM_BASE_LIMIT); ++ ++ ++ pPciAgent->p2pPrefMemBase = ++ (pciData & PRMBL_PREF_MEM_BASE_MASK) << PRMBL_PREF_MEM_LIMIT_OFFS; ++ ++ /* get high address only */ ++ pPciAgent->p2pPrefMemBase &= PRMBL_HIGH_ADDR_MASK; ++ ++ ++ ++ pPciAgent->p2pPrefMemLimit = ++ (pciData & PRMBL_PREF_MEM_LIMIT_MASK); ++ ++ /* add 0xfffff */ ++ pPciAgent->p2pPrefMemLimit |= PRMBL_LOW_ADDR_MASK; ++ ++ switch (pciData & PRMBL_ADD_CAP_MASK) ++ { ++ case PRMBL_ADD_CAP_32BIT: ++ ++ pPciAgent->bPrefMem64 = MV_FALSE; ++ ++ /* Read P2P_PREF_BASE_UPPER_32 */ ++ pPciAgent->p2pPrefBaseUpper32Bits = 0; ++ ++ /* Read P2P_PREF_LIMIT_UPPER_32 */ ++ pPciAgent->p2pPrefLimitUpper32Bits = 0; ++ ++ break; ++ case PRMBL_ADD_CAP_64BIT: ++ ++ pPciAgent->bPrefMem64 = MV_TRUE; ++ ++ /* Read P2P_PREF_BASE_UPPER_32 */ ++ pPciAgent->p2pPrefBaseUpper32Bits = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ P2P_PREF_BASE_UPPER_32); ++ ++ /* Read P2P_PREF_LIMIT_UPPER_32 */ ++ pPciAgent->p2pPrefLimitUpper32Bits = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ P2P_PREF_LIMIT_UPPER_32); ++ ++ break; ++ ++ } ++ ++ } ++ else /* no bridge */ ++ { ++ /* Read PCI_SUBSYS_ID_AND_SUBSYS_VENDOR_ID */ ++ pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ PCI_SUBSYS_ID_AND_SUBSYS_VENDOR_ID); ++ ++ ++ pPciAgent->subSysVenID = ++ (pciData & PSISVIR_VENID_MASK) >> PSISVIR_VENID_OFFS; ++ pPciAgent->subSysID = ++ (pciData & PSISVIR_DEVID_MASK) >> PSISVIR_DEVID_OFFS; ++ ++ ++ /* Read PCI_EXPANSION_ROM_BASE_ADDR_REG */ ++ pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ PCI_EXPANSION_ROM_BASE_ADDR_REG); ++ ++ ++ if (pciData & PERBAR_EXPROMEN) ++ { ++ pPciAgent->isExpRom = MV_TRUE; ++ } ++ else ++ { ++ pPciAgent->isExpRom = MV_FALSE; ++ } ++ ++ pPciAgent->expRomAddr = ++ (pciData & PERBAR_BASE_MASK) >> PERBAR_BASE_OFFS; ++ ++ } ++ ++ ++ if (MV_TRUE == pPciAgent->isCapListSupport) ++ { ++ /* Read PCI_CAPABILTY_LIST_POINTER */ ++ pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ PCI_CAPABILTY_LIST_POINTER); ++ ++ pPciAgent->capListPointer = ++ (pciData & PCLPR_CAPPTR_MASK) >> PCLPR_CAPPTR_OFFS; ++ ++ } ++ ++ /* Read PCI_INTERRUPT_PIN_AND_LINE */ ++ pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ PCI_INTERRUPT_PIN_AND_LINE); ++ ++ ++ pPciAgent->irqLine= ++ (pciData & PIPLR_INTLINE_MASK) >> PIPLR_INTLINE_OFFS; ++ ++ pPciAgent->intPin= ++ (MV_PCI_INT_PIN)(pciData & PIPLR_INTPIN_MASK) >> PIPLR_INTPIN_OFFS; ++ ++ pPciAgent->minGrant= ++ (pciData & PIPLR_MINGRANT_MASK) >> PIPLR_MINGRANT_OFFS; ++ pPciAgent->maxLatency= ++ (pciData & PIPLR_MAXLATEN_MASK) >> PIPLR_MAXLATEN_OFFS; ++ ++ mvPciClassNameGet(pPciAgent->baseClassCode, ++ (MV_8 *)pPciAgent->type); ++ ++ return MV_OK; ++ ++ ++} ++ ++/******************************************************************************* ++* pciDetectDeviceBars - Detect a pci device bars ++* ++* DESCRIPTION: ++* This function detects all pci agent bars ++* ++* INPUT: ++* pciIf - PCI Interface ++* bus - Bus number ++* dev - Device number ++* func - Function number ++* ++* ++* ++* OUTPUT: ++* pPciAgent - pointer to the pci agent filled with its information ++* ++* RETURN: ++* detected bars number ++* ++*******************************************************************************/ ++static MV_U32 pciDetectDeviceBars(MV_U32 pciIf, ++ MV_U32 bus, ++ MV_U32 dev, ++ MV_U32 func, ++ MV_PCI_DEVICE *pPciAgent) ++{ ++ MV_U32 pciData,barIndex,detectedBar=0; ++ MV_U32 tmpBaseHigh=0,tmpBaseLow=0; ++ MV_U32 pciMaxBars=0; ++ ++ pPciAgent->barsNum=0; ++ ++ /* check if we are bridge*/ ++ if ((pPciAgent->baseClassCode == PCI_BRIDGE_CLASS)&& ++ (pPciAgent->subClassCode == P2P_BRIDGE_SUB_CLASS_CODE)) ++ { ++ pciMaxBars = 2; ++ } ++ else /* no bridge */ ++ { ++ pciMaxBars = 6; ++ } ++ ++ /* read this device pci bars */ ++ for (barIndex = 0 ; barIndex < pciMaxBars ; barIndex++ ) ++ { ++ /* Read PCI_MEMORY_BAR_BASE_ADDR */ ++ tmpBaseLow = pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ PCI_MEMORY_BAR_BASE_ADDR(barIndex)); ++ ++ pPciAgent->pciBar[detectedBar].barOffset = ++ PCI_MEMORY_BAR_BASE_ADDR(barIndex); ++ ++ /* check if the bar is 32bit or 64bit bar */ ++ switch (pciData & PBBLR_TYPE_MASK) ++ { ++ case PBBLR_TYPE_32BIT_ADDR: ++ pPciAgent->pciBar[detectedBar].barType = PCI_32BIT_BAR; ++ break; ++ case PBBLR_TYPE_64BIT_ADDR: ++ pPciAgent->pciBar[detectedBar].barType = PCI_64BIT_BAR; ++ break; ++ ++ } ++ ++ /* check if it is memory or IO bar */ ++ if (pciData & PBBLR_IOSPACE) ++ { ++ pPciAgent->pciBar[detectedBar].barMapping=PCI_IO_BAR; ++ } ++ else ++ { ++ pPciAgent->pciBar[detectedBar].barMapping=PCI_MEMORY_BAR; ++ } ++ ++ /* if it is memory bar then check if it is prefetchable */ ++ if (PCI_MEMORY_BAR == pPciAgent->pciBar[detectedBar].barMapping) ++ { ++ if (pciData & PBBLR_PREFETCH_EN) ++ { ++ pPciAgent->pciBar[detectedBar].isPrefetchable = MV_TRUE; ++ } ++ else ++ { ++ pPciAgent->pciBar[detectedBar].isPrefetchable = MV_FALSE; ++ } ++ ++ pPciAgent->pciBar[detectedBar].barBaseLow = ++ pciData & PBBLR_MEM_BASE_MASK; ++ ++ ++ } ++ else /* IO Bar */ ++ { ++ pPciAgent->pciBar[detectedBar].barBaseLow = ++ pciData & PBBLR_IO_BASE_MASK; ++ ++ } ++ ++ pPciAgent->pciBar[detectedBar].barBaseHigh=0; ++ ++ if (PCI_64BIT_BAR == pPciAgent->pciBar[detectedBar].barType) ++ { ++ barIndex++; ++ ++ tmpBaseHigh = pPciAgent->pciBar[detectedBar].barBaseHigh = ++ mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ PCI_MEMORY_BAR_BASE_ADDR(barIndex)); ++ ++ ++ } ++ ++ /* calculating full base address (64bit) */ ++ pPciAgent->pciBar[detectedBar].barBaseAddr = ++ (MV_U64)pPciAgent->pciBar[detectedBar].barBaseHigh; ++ ++ pPciAgent->pciBar[detectedBar].barBaseAddr <<= 32; ++ ++ pPciAgent->pciBar[detectedBar].barBaseAddr |= ++ (MV_U64)pPciAgent->pciBar[detectedBar].barBaseLow; ++ ++ ++ ++ /* get the sizes of the the bar */ ++ ++ pPciAgent->pciBar[detectedBar].barSizeHigh=0; ++ ++ if ((PCI_64BIT_BAR == pPciAgent->pciBar[detectedBar].barType) && ++ (PCI_MEMORY_BAR == pPciAgent->pciBar[detectedBar].barMapping)) ++ ++ { ++ /* write oxffffffff to the bar to get the size */ ++ /* start with sizelow ( original value was saved in tmpBaseLow ) */ ++ mvPciIfConfigWrite(pciIf, ++ bus,dev,func, ++ PCI_MEMORY_BAR_BASE_ADDR(barIndex-1), ++ 0xffffffff); ++ ++ /* read size */ ++ pPciAgent->pciBar[detectedBar].barSizeLow = ++ mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ PCI_MEMORY_BAR_BASE_ADDR(barIndex-1)); ++ ++ ++ ++ /* restore original value */ ++ mvPciIfConfigWrite(pciIf, ++ bus,dev,func, ++ PCI_MEMORY_BAR_BASE_ADDR(barIndex-1), ++ tmpBaseLow); ++ ++ ++ /* now do the same for BaseHigh */ ++ ++ /* write oxffffffff to the bar to get the size */ ++ mvPciIfConfigWrite(pciIf, ++ bus,dev,func, ++ PCI_MEMORY_BAR_BASE_ADDR(barIndex), ++ 0xffffffff); ++ ++ /* read size */ ++ pPciAgent->pciBar[detectedBar].barSizeHigh = ++ mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ PCI_MEMORY_BAR_BASE_ADDR(barIndex)); ++ ++ /* restore original value */ ++ mvPciIfConfigWrite(pciIf, ++ bus,dev,func, ++ PCI_MEMORY_BAR_BASE_ADDR(barIndex), ++ tmpBaseHigh); ++ ++ if ((0 == pPciAgent->pciBar[detectedBar].barSizeLow)&& ++ (0 == pPciAgent->pciBar[detectedBar].barSizeHigh)) ++ { ++ /* this bar is not applicable for this device, ++ ignore all previous settings and check the next bar*/ ++ ++ /* we though this was a 64bit bar , and it seems this ++ was wrong ! so decrement barIndex */ ++ barIndex--; ++ continue; ++ } ++ ++ /* calculate the full 64 bit size */ ++ ++ if (0 != pPciAgent->pciBar[detectedBar].barSizeHigh) ++ { ++ pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_MEM_BASE_MASK; ++ ++ pPciAgent->pciBar[detectedBar].barSizeLow = ++ ~pPciAgent->pciBar[detectedBar].barSizeLow + 1; ++ ++ pPciAgent->pciBar[detectedBar].barSizeHigh = 0; ++ ++ } ++ else ++ { ++ ++ pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_MEM_BASE_MASK; ++ ++ pPciAgent->pciBar[detectedBar].barSizeLow = ++ ~pPciAgent->pciBar[detectedBar].barSizeLow + 1; ++ ++ pPciAgent->pciBar[detectedBar].barSizeHigh = 0; ++ ++ } ++ ++ ++ ++ } ++ else /* 32bit bar */ ++ { ++ /* write oxffffffff to the bar to get the size */ ++ mvPciIfConfigWrite(pciIf, ++ bus,dev,func, ++ PCI_MEMORY_BAR_BASE_ADDR(barIndex), ++ 0xffffffff); ++ ++ /* read size */ ++ pPciAgent->pciBar[detectedBar].barSizeLow = ++ mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ PCI_MEMORY_BAR_BASE_ADDR(barIndex)); ++ ++ if (0 == pPciAgent->pciBar[detectedBar].barSizeLow) ++ { ++ /* this bar is not applicable for this device, ++ ignore all previous settings and check the next bar*/ ++ continue; ++ } ++ ++ ++ /* restore original value */ ++ mvPciIfConfigWrite(pciIf, ++ bus,dev,func, ++ PCI_MEMORY_BAR_BASE_ADDR(barIndex), ++ tmpBaseLow); ++ ++ /* calculate size low */ ++ ++ if (PCI_MEMORY_BAR == pPciAgent->pciBar[detectedBar].barMapping) ++ { ++ pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_MEM_BASE_MASK; ++ } ++ else ++ { ++ pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_IO_BASE_MASK; ++ } ++ ++ pPciAgent->pciBar[detectedBar].barSizeLow = ++ ~pPciAgent->pciBar[detectedBar].barSizeLow + 1; ++ ++ pPciAgent->pciBar[detectedBar].barSizeHigh = 0; ++ pPciAgent->pciBar[detectedBar].barSize = ++ (MV_U64)pPciAgent->pciBar[detectedBar].barSizeLow; ++ ++ ++ } ++ ++ /* we are here ! this means we have already detected a bar for ++ this device , now move on */ ++ ++ detectedBar++; ++ pPciAgent->barsNum++; ++ } ++ ++ return detectedBar; ++} ++ ++ ++/******************************************************************************* ++* mvPciClassNameGet - get PCI class name ++* ++* DESCRIPTION: ++* This function returns the PCI class name ++* ++* INPUT: ++* baseClassCode - Base Class Code. ++* ++* OUTPUT: ++* pType - the class name ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPciClassNameGet(MV_U32 baseClassCode, MV_8 *pType) ++{ ++ ++ switch(baseClassCode) ++ { ++ case 0x0: ++ strcpy(pType,"Old generation device"); ++ break; ++ case 0x1: ++ strcpy(pType,"Mass storage controller"); ++ break; ++ case 0x2: ++ strcpy(pType,"Network controller"); ++ break; ++ case 0x3: ++ strcpy(pType,"Display controller"); ++ break; ++ case 0x4: ++ strcpy(pType,"Multimedia device"); ++ break; ++ case 0x5: ++ strcpy(pType,"Memory controller"); ++ break; ++ case 0x6: ++ strcpy(pType,"Bridge Device"); ++ break; ++ case 0x7: ++ strcpy(pType,"Simple Communication controllers"); ++ break; ++ case 0x8: ++ strcpy(pType,"Base system peripherals"); ++ break; ++ case 0x9: ++ strcpy(pType,"Input Devices"); ++ break; ++ case 0xa: ++ strcpy(pType,"Docking stations"); ++ break; ++ case 0xb: ++ strcpy(pType,"Processors"); ++ break; ++ case 0xc: ++ strcpy(pType,"Serial bus controllers"); ++ break; ++ case 0xd: ++ strcpy(pType,"Wireless controllers"); ++ break; ++ case 0xe: ++ strcpy(pType,"Intelligent I/O controllers"); ++ break; ++ case 0xf: ++ strcpy(pType,"Satellite communication controllers"); ++ break; ++ case 0x10: ++ strcpy(pType,"Encryption/Decryption controllers"); ++ break; ++ case 0x11: ++ strcpy(pType,"Data acquisition and signal processing controllers"); ++ break; ++ default: ++ strcpy(pType,"Unknown device"); ++ break; ++ } ++ ++ return MV_OK; ++ ++} ++ ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,323 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvPciUtilsh ++#define __INCmvPciUtilsh ++ ++/* ++This module only support scanning of Header type 00h of pci devices ++There is no suppotr for Header type 01h of pci devices ( PCI bridges ) ++*/ ++ ++/* includes */ ++#include "mvSysHwConfig.h" ++#include "pci-if/mvPciIf.h" ++#include "pci/mvPciRegs.h" ++ ++ ++ ++/* PCI base address low bar mask */ ++#define PCI_ERROR_CODE 0xffffffff ++ ++#define PCI_BRIDGE_CLASS 0x6 ++#define P2P_BRIDGE_SUB_CLASS_CODE 0x4 ++ ++ ++#define P2P_BUSSES_NUM 0x18 ++#define P2P_IO_BASE_LIMIT_SEC_STATUS 0x1C ++#define P2P_MEM_BASE_LIMIT 0x20 ++#define P2P_PREF_MEM_BASE_LIMIT 0x24 ++#define P2P_PREF_BASE_UPPER_32 0x28 ++#define P2P_PREF_LIMIT_UPPER_32 0x2C ++#define P2P_IO_BASE_LIMIT_UPPER_16 0x30 ++#define P2P_EXP_ROM 0x38 ++ ++/* P2P_BUSSES_NUM (PBM) */ ++ ++#define PBM_PRIME_BUS_NUM_OFFS 0 ++#define PBM_PRIME_BUS_NUM_MASK (0xff << PBM_PRIME_BUS_NUM_OFFS) ++ ++#define PBM_SEC_BUS_NUM_OFFS 8 ++#define PBM_SEC_BUS_NUM_MASK (0xff << PBM_SEC_BUS_NUM_OFFS) ++ ++#define PBM_SUB_BUS_NUM_OFFS 16 ++#define PBM_SUB_BUS_NUM_MASK (0xff << PBM_SUB_BUS_NUM_OFFS) ++ ++#define PBM_SEC_LAT_TMR_OFFS 24 ++#define PBM_SEC_LAT_TMR_MASK (0xff << PBM_SEC_LAT_TMR_OFFS) ++ ++/* P2P_IO_BASE_LIMIT_SEC_STATUS (PIBLSS) */ ++ ++#define PIBLSS_IO_BASE_OFFS 0 ++#define PIBLSS_IO_BASE_MASK (0xff << PIBLSS_IO_BASE_OFFS) ++ ++#define PIBLSS_ADD_CAP_OFFS 0 ++#define PIBLSS_ADD_CAP_MASK (0x3 << PIBLSS_ADD_CAP_OFFS) ++#define PIBLSS_ADD_CAP_16BIT (0x0 << PIBLSS_ADD_CAP_OFFS) ++#define PIBLSS_ADD_CAP_32BIT (0x1 << PIBLSS_ADD_CAP_OFFS) ++ ++#define PIBLSS_LOW_ADDR_OFFS 0 ++#define PIBLSS_LOW_ADDR_MASK (0xFFF << PIBLSS_LOW_ADDR_OFFS) ++ ++#define PIBLSS_HIGH_ADDR_OFFS 12 ++#define PIBLSS_HIGH_ADDR_MASK (0xF << PIBLSS_HIGH_ADDR_OFFS) ++ ++#define PIBLSS_IO_LIMIT_OFFS 8 ++#define PIBLSS_IO_LIMIT_MASK (0xff << PIBLSS_IO_LIMIT_OFFS) ++ ++#define PIBLSS_SEC_STATUS_OFFS 16 ++#define PIBLSS_SEC_STATUS_MASK (0xffff << PIBLSS_SEC_STATUS_OFFS) ++ ++ ++/* P2P_MEM_BASE_LIMIT (PMBL)*/ ++ ++#define PMBL_MEM_BASE_OFFS 0 ++#define PMBL_MEM_BASE_MASK (0xffff << PMBL_MEM_BASE_OFFS) ++ ++#define PMBL_MEM_LIMIT_OFFS 16 ++#define PMBL_MEM_LIMIT_MASK (0xffff << PMBL_MEM_LIMIT_OFFS) ++ ++ ++#define PMBL_LOW_ADDR_OFFS 0 ++#define PMBL_LOW_ADDR_MASK (0xFFFFF << PMBL_LOW_ADDR_OFFS) ++ ++#define PMBL_HIGH_ADDR_OFFS 20 ++#define PMBL_HIGH_ADDR_MASK (0xFFF << PMBL_HIGH_ADDR_OFFS) ++ ++ ++/* P2P_PREF_MEM_BASE_LIMIT (PRMBL) */ ++ ++#define PRMBL_PREF_MEM_BASE_OFFS 0 ++#define PRMBL_PREF_MEM_BASE_MASK (0xffff << PRMBL_PREF_MEM_BASE_OFFS) ++ ++#define PRMBL_PREF_MEM_LIMIT_OFFS 16 ++#define PRMBL_PREF_MEM_LIMIT_MASK (0xffff<= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexModeGet: ERR. Invalid PEX interface %d\n",pexIf); ++ return MV_ERROR; ++ } ++ } ++ ++ pexData = MV_REG_READ(PEX_CTRL_REG(pexIf)); ++ ++ switch (pexData & PXCR_DEV_TYPE_CTRL_MASK) ++ { ++ case PXCR_DEV_TYPE_CTRL_CMPLX: ++ pexMode->pexType = MV_PEX_ROOT_COMPLEX; ++ break; ++ case PXCR_DEV_TYPE_CTRL_POINT: ++ pexMode->pexType = MV_PEX_END_POINT; ++ break; ++ ++ } ++ ++ /* Check if we have link */ ++ if (MV_REG_READ(PEX_STATUS_REG(pexIf)) & PXSR_DL_DOWN) ++ { ++ pexMode->pexLinkUp = MV_FALSE; ++ ++ /* If there is no link, the auto negotiation data is worthless */ ++ pexMode->pexWidth = MV_PEX_WITDH_INVALID; ++ } ++ else ++ { ++ pexMode->pexLinkUp = MV_TRUE; ++ ++ /* We have link. The link width is now valid */ ++ pexData = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG)); ++ pexMode->pexWidth = ((pexData & PXLCSR_NEG_LNK_WDTH_MASK) >> ++ PXLCSR_NEG_LNK_WDTH_OFFS); ++ } ++ ++ return MV_OK; ++} ++ ++ ++/* PEX configuration space read write */ ++ ++/******************************************************************************* ++* mvPexConfigRead - Read from configuration space ++* ++* DESCRIPTION: ++* This function performs a 32 bit read from PEX configuration space. ++* It supports both type 0 and type 1 of Configuration Transactions ++* (local and over bridge). In order to read from local bus segment, use ++* bus number retrieved from mvPexLocalBusNumGet(). Other bus numbers ++* will result configuration transaction of type 1 (over bridge). ++* ++* INPUT: ++* pexIf - PEX interface number. ++* bus - PEX segment bus number. ++* dev - PEX device number. ++* func - Function number. ++* regOffs - Register offset. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit register data, 0xffffffff on error ++* ++*******************************************************************************/ ++MV_U32 mvPexConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, ++ MV_U32 regOff) ++{ ++#if defined(PCIE_VIRTUAL_BRIDGE_SUPPORT) ++ return mvPexVrtBrgConfigRead (pexIf, bus, dev, func, regOff); ++} ++ ++MV_U32 mvPexHwConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, ++ MV_U32 regOff) ++{ ++#endif ++ MV_U32 pexData = 0; ++ MV_U32 localDev,localBus; ++ ++ /* Parameter checking */ ++ if (PEX_DEFAULT_IF != pexIf) ++ { ++ if (pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexConfigRead: ERR. Invalid PEX interface %d\n",pexIf); ++ return 0xFFFFFFFF; ++ } ++ } ++ ++ if (dev >= MAX_PEX_DEVICES) ++ { ++ DB(mvOsPrintf("mvPexConfigRead: ERR. device number illigal %d\n", dev)); ++ return 0xFFFFFFFF; ++ } ++ ++ if (func >= MAX_PEX_FUNCS) ++ { ++ DB(mvOsPrintf("mvPexConfigRead: ERR. function num illigal %d\n", func)); ++ return 0xFFFFFFFF; ++ } ++ ++ if (bus >= MAX_PEX_BUSSES) ++ { ++ DB(mvOsPrintf("mvPexConfigRead: ERR. bus number illigal %d\n", bus)); ++ return MV_ERROR; ++ } ++ ++ DB(mvOsPrintf("mvPexConfigRead: pexIf %d, bus %d, dev %d, func %d, regOff 0x%x\n", ++ pexIf, bus, dev, func, regOff)); ++ ++ localDev = mvPexLocalDevNumGet(pexIf); ++ localBus = mvPexLocalBusNumGet(pexIf); ++ ++ /* Speed up the process. In case on no link, return MV_ERROR */ ++ if ((dev != localDev) || (bus != localBus)) ++ { ++ pexData = MV_REG_READ(PEX_STATUS_REG(pexIf)); ++ ++ if ((pexData & PXSR_DL_DOWN)) ++ { ++ return MV_ERROR; ++ } ++ } ++ ++ /* in PCI Express we have only one device number */ ++ /* and this number is the first number we encounter ++ else that the localDev*/ ++ /* spec pex define return on config read/write on any device */ ++ if (bus == localBus) ++ { ++ if (localDev == 0) ++ { ++ /* if local dev is 0 then the first number we encounter ++ after 0 is 1 */ ++ if ((dev != 1)&&(dev != localDev)) ++ { ++ return MV_ERROR; ++ } ++ } ++ else ++ { ++ /* if local dev is not 0 then the first number we encounter ++ is 0 */ ++ ++ if ((dev != 0)&&(dev != localDev)) ++ { ++ return MV_ERROR; ++ } ++ } ++ if(func != 0 ) /* i.e bridge */ ++ { ++ return MV_ERROR; ++ } ++ } ++ ++ ++ /* Creating PEX address to be passed */ ++ pexData = (bus << PXCAR_BUS_NUM_OFFS); ++ pexData |= (dev << PXCAR_DEVICE_NUM_OFFS); ++ pexData |= (func << PXCAR_FUNC_NUM_OFFS); ++ pexData |= (regOff & PXCAR_REG_NUM_MASK); /* lgacy register space */ ++ /* extended register space */ ++ pexData |=(((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >> ++ PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS); ++ ++ pexData |= PXCAR_CONFIG_EN; ++ ++ /* Write the address to the PEX configuration address register */ ++ MV_REG_WRITE(PEX_CFG_ADDR_REG(pexIf), pexData); ++ ++ DB(mvOsPrintf("mvPexConfigRead:address pexData=%x ",pexData)); ++ ++ ++ /* In order to let the PEX controller absorbed the address of the read */ ++ /* transaction we perform a validity check that the address was written */ ++ if(pexData != MV_REG_READ(PEX_CFG_ADDR_REG(pexIf))) ++ { ++ return MV_ERROR; ++ } ++ ++ /* cleaning Master Abort */ ++ MV_REG_BIT_SET(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_STATUS_AND_COMMAND), ++ PXSAC_MABORT); ++#if 0 ++ /* Guideline (GL# PCI Express-1) Erroneous Read Data on Configuration */ ++ /* This guideline is relevant for all devices except of the following devices: ++ 88F5281-BO and above, 88F5181L-A0 and above, 88F1281 A0 and above ++ 88F6183 A0 and above, 88F6183L */ ++ if ( ( (dev != localDev) || (bus != localBus) ) && ++ ( ++ !(MV_5281_DEV_ID == mvCtrlModelGet())&& ++ !((MV_5181_DEV_ID == mvCtrlModelGet())&& (mvCtrlRevGet() >= MV_5181L_A0_REV))&& ++ !(MV_1281_DEV_ID == mvCtrlModelGet())&& ++ !(MV_6183_DEV_ID == mvCtrlModelGet())&& ++ !(MV_6183L_DEV_ID == mvCtrlModelGet())&& ++ !(MV_6281_DEV_ID == mvCtrlModelGet())&& ++ !(MV_6192_DEV_ID == mvCtrlModelGet())&& ++ !(MV_6190_DEV_ID == mvCtrlModelGet())&& ++ !(MV_6180_DEV_ID == mvCtrlModelGet())&& ++ !(MV_78XX0_DEV_ID == mvCtrlModelGet()) ++ )) ++ { ++ ++ /* PCI-Express configuration read work-around */ ++ ++ /* we will use one of the Punit (AHBToMbus) windows to access the xbar ++ and read the data from there */ ++ /* ++ Need to configure the 2 free Punit (AHB to MBus bridge) ++ address decoding windows: ++ Configure the flash Window to handle Configuration space requests ++ for PEX0/1: ++ 1. write 0x7931/0x7941 to the flash window and the size, ++ 79-xbar attr (pci cfg), 3/4-xbar target (pex0/1), 1-WinEn ++ 2. write base to flash window ++ ++ Configuration transactions from the CPU should write/read the data ++ to/from address of the form: ++ addr[31:28] = 0x5 (for PEX0) or 0x6 (for PEX1) ++ addr[27:24] = extended register number ++ addr[23:16] = bus number ++ addr[15:11] = device number ++ addr[10:8] = function number ++ addr[7:0] = register number ++ */ ++ ++ #include "ctrlEnv/sys/mvAhbToMbus.h" ++ { ++ MV_U32 winNum; ++ MV_AHB_TO_MBUS_DEC_WIN originWin; ++ MV_U32 pciAddr=0; ++ MV_U32 remapLow=0,remapHigh=0; ++ ++ /* ++ We will use DEV_CS2\Flash window for this workarround ++ */ ++ ++ winNum = mvAhbToMbusWinTargetGet(PEX_CONFIG_RW_WA_TARGET); ++ ++ /* save remap values if exist */ ++ if ((1 == winNum)||(0 == winNum)) ++ { ++ remapLow = MV_REG_READ(AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum)); ++ remapHigh = MV_REG_READ(AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum)); ++ ++ } ++ ++ ++ /* save the original window values */ ++ mvAhbToMbusWinGet(winNum,&originWin); ++ ++ if (PEX_CONFIG_RW_WA_USE_ORIGINAL_WIN_VALUES) ++ { ++ /* set the window as xbar window */ ++ if (pexIf) ++ { ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ++ (0x7931 | (((originWin.addrWin.size >> 16)-1) ) << 16)); ++ } ++ else ++ { ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ++ (0x7941 | (((originWin.addrWin.size >> 16)-1) ) << 16)); ++ } ++ ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum), ++ originWin.addrWin.baseLow); ++ ++ /*pciAddr = originWin.addrWin.baseLow;*/ ++ pciAddr = (MV_U32)CPU_MEMIO_UNCACHED_ADDR( ++ (MV_U32)originWin.addrWin.baseLow); ++ ++ } ++ else ++ { ++ /* set the window as xbar window */ ++ if (pexIf) ++ { ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ++ (0x7931 | (((PEX_CONFIG_RW_WA_SIZE >> 16)-1) ) << 16)); ++ } ++ else ++ { ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ++ (0x7941 | (((PEX_CONFIG_RW_WA_SIZE >> 16)-1) ) << 16)); ++ } ++ ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum), ++ PEX_CONFIG_RW_WA_BASE); ++ ++ pciAddr = (MV_U32)CPU_MEMIO_UNCACHED_ADDR(PEX_CONFIG_RW_WA_BASE); ++ } ++ ++ ++ /* remap should be as base */ ++ if ((1 == winNum)||(0 == winNum)) ++ { ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum),pciAddr); ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum),0); ++ ++ } ++ ++ /* extended register space */ ++ pciAddr |= (bus << 16); ++ pciAddr |= (dev << 11); ++ pciAddr |= (func << 8); ++ pciAddr |= (regOff & PXCAR_REG_NUM_MASK); /* lgacy register space */ ++ ++ pexData = *(MV_U32*)pciAddr; ++ pexData = MV_32BIT_LE(pexData); /* Data always in LE */ ++ ++ /* restore the original window values */ ++ mvAhbToMbusWinSet(winNum,&originWin); ++ ++ /* restore original remap values*/ ++ if ((1 == winNum)||(0 == winNum)) ++ { ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum),remapLow); ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum),remapHigh); ++ ++ } ++ } ++ } ++ else ++#endif ++ { ++ /* Read the Data returned in the PEX Data register */ ++ pexData = MV_REG_READ(PEX_CFG_DATA_REG(pexIf)); ++ ++ } ++ ++ DB(mvOsPrintf("mvPexConfigRead: got : %x \n",pexData)); ++ ++ return pexData; ++ ++} ++ ++/******************************************************************************* ++* mvPexConfigWrite - Write to configuration space ++* ++* DESCRIPTION: ++* This function performs a 32 bit write to PEX configuration space. ++* It supports both type 0 and type 1 of Configuration Transactions ++* (local and over bridge). In order to write to local bus segment, use ++* bus number retrieved from mvPexLocalBusNumGet(). Other bus numbers ++* will result configuration transaction of type 1 (over bridge). ++* ++* INPUT: ++* pexIf - PEX interface number. ++* bus - PEX segment bus number. ++* dev - PEX device number. ++* func - Function number. ++* regOffs - Register offset. ++* data - 32bit data. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPexConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func, MV_U32 regOff, MV_U32 data) ++{ ++#if defined(PCIE_VIRTUAL_BRIDGE_SUPPORT) ++ return mvPexVrtBrgConfigWrite (pexIf, bus, dev, func, regOff, data); ++} ++ ++MV_STATUS mvPexHwConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func, MV_U32 regOff, MV_U32 data) ++{ ++#endif ++ MV_U32 pexData = 0; ++ MV_U32 localDev,localBus; ++ ++ /* Parameter checking */ ++ if (PEX_DEFAULT_IF != pexIf) ++ { ++ if (pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexConfigWrite: ERR. Invalid PEX interface %d\n", ++ pexIf); ++ return MV_ERROR; ++ } ++ } ++ ++ if (dev >= MAX_PEX_DEVICES) ++ { ++ mvOsPrintf("mvPexConfigWrite: ERR. device number illigal %d\n",dev); ++ return MV_BAD_PARAM; ++ } ++ ++ if (func >= MAX_PEX_FUNCS) ++ { ++ mvOsPrintf("mvPexConfigWrite: ERR. function number illigal %d\n", func); ++ return MV_ERROR; ++ } ++ ++ if (bus >= MAX_PEX_BUSSES) ++ { ++ mvOsPrintf("mvPexConfigWrite: ERR. bus number illigal %d\n", bus); ++ return MV_ERROR; ++ } ++ ++ ++ ++ localDev = mvPexLocalDevNumGet(pexIf); ++ localBus = mvPexLocalBusNumGet(pexIf); ++ ++ ++ /* in PCI Express we have only one device number other than ourselves*/ ++ /* and this number is the first number we encounter ++ else than the localDev that can be any valid dev number*/ ++ /* pex spec define return on config read/write on any device */ ++ if (bus == localBus) ++ { ++ ++ if (localDev == 0) ++ { ++ /* if local dev is 0 then the first number we encounter ++ after 0 is 1 */ ++ if ((dev != 1)&&(dev != localDev)) ++ { ++ return MV_ERROR; ++ } ++ ++ } ++ else ++ { ++ /* if local dev is not 0 then the first number we encounter ++ is 0 */ ++ ++ if ((dev != 0)&&(dev != localDev)) ++ { ++ return MV_ERROR; ++ } ++ } ++ ++ ++ } ++ ++ /* if we are not accessing ourselves , then check the link */ ++ if ((dev != localDev) || (bus != localBus) ) ++ { ++ /* workarround */ ++ /* when no link return MV_ERROR */ ++ ++ pexData = MV_REG_READ(PEX_STATUS_REG(pexIf)); ++ ++ if ((pexData & PXSR_DL_DOWN)) ++ { ++ return MV_ERROR; ++ } ++ ++ } ++ ++ pexData =0; ++ ++ /* Creating PEX address to be passed */ ++ pexData |= (bus << PXCAR_BUS_NUM_OFFS); ++ pexData |= (dev << PXCAR_DEVICE_NUM_OFFS); ++ pexData |= (func << PXCAR_FUNC_NUM_OFFS); ++ pexData |= (regOff & PXCAR_REG_NUM_MASK); /* lgacy register space */ ++ /* extended register space */ ++ pexData |=(((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >> ++ PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS); ++ pexData |= PXCAR_CONFIG_EN; ++ ++ DB(mvOsPrintf("mvPexConfigWrite: If=%x bus=%x func=%x dev=%x regOff=%x data=%x \n", ++ pexIf,bus,func,dev,regOff,data,pexData) ); ++ ++ /* Write the address to the PEX configuration address register */ ++ MV_REG_WRITE(PEX_CFG_ADDR_REG(pexIf), pexData); ++ ++ /* Clear CPU pipe. Important where CPU can perform OOO execution */ ++ CPU_PIPE_FLUSH; ++ ++ /* In order to let the PEX controller absorbed the address of the read */ ++ /* transaction we perform a validity check that the address was written */ ++ if(pexData != MV_REG_READ(PEX_CFG_ADDR_REG(pexIf))) ++ { ++ return MV_ERROR; ++ } ++ ++ /* Write the Data passed to the PEX Data register */ ++ MV_REG_WRITE(PEX_CFG_DATA_REG(pexIf), data); ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvPexMasterEnable - Enable/disale PEX interface master transactions. ++* ++* DESCRIPTION: ++* This function performs read modified write to PEX command status ++* (offset 0x4) to set/reset bit 2. After this bit is set, the PEX ++* master is allowed to gain ownership on the bus, otherwise it is ++* incapable to do so. ++* ++* INPUT: ++* pexIf - PEX interface number. ++* enable - Enable/disable parameter. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPexMasterEnable(MV_U32 pexIf, MV_BOOL enable) ++{ ++ MV_U32 pexCommandStatus; ++ MV_U32 localBus; ++ MV_U32 localDev; ++ ++ /* Parameter checking */ ++ if (pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexMasterEnable: ERR. Invalid PEX interface %d\n", pexIf); ++ return MV_ERROR; ++ } ++ ++ localBus = mvPexLocalBusNumGet(pexIf); ++ localDev = mvPexLocalDevNumGet(pexIf); ++ ++ pexCommandStatus = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, ++ PEX_STATUS_AND_COMMAND)); ++ ++ ++ if (MV_TRUE == enable) ++ { ++ pexCommandStatus |= PXSAC_MASTER_EN; ++ } ++ else ++ { ++ pexCommandStatus &= ~PXSAC_MASTER_EN; ++ } ++ ++ ++ MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_STATUS_AND_COMMAND), ++ pexCommandStatus); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvPexSlaveEnable - Enable/disale PEX interface slave transactions. ++* ++* DESCRIPTION: ++* This function performs read modified write to PEX command status ++* (offset 0x4) to set/reset bit 0 and 1. After those bits are set, ++* the PEX slave is allowed to respond to PEX IO space access (bit 0) ++* and PEX memory space access (bit 1). ++* ++* INPUT: ++* pexIf - PEX interface number. ++* dev - PEX device number. ++* enable - Enable/disable parameter. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPexSlaveEnable(MV_U32 pexIf, MV_U32 bus,MV_U32 dev, MV_BOOL enable) ++{ ++ MV_U32 pexCommandStatus; ++ MV_U32 RegOffs; ++ ++ /* Parameter checking */ ++ if (pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexSlaveEnable: ERR. Invalid PEX interface %d\n", pexIf); ++ return MV_BAD_PARAM; ++ } ++ if (dev >= MAX_PEX_DEVICES) ++ { ++ mvOsPrintf("mvPexLocalDevNumSet: ERR. device number illigal %d\n", dev); ++ return MV_BAD_PARAM; ++ ++ } ++ ++ ++ RegOffs = PEX_STATUS_AND_COMMAND; ++ ++ pexCommandStatus = mvPexConfigRead(pexIf, bus, dev, 0, RegOffs); ++ ++ if (MV_TRUE == enable) ++ { ++ pexCommandStatus |= (PXSAC_IO_EN | PXSAC_MEM_EN); ++ } ++ else ++ { ++ pexCommandStatus &= ~(PXSAC_IO_EN | PXSAC_MEM_EN); ++ } ++ ++ mvPexConfigWrite(pexIf, bus, dev, 0, RegOffs, pexCommandStatus); ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvPexLocalBusNumSet - Set PEX interface local bus number. ++* ++* DESCRIPTION: ++* This function sets given PEX interface its local bus number. ++* Note: In case the PEX interface is PEX-X, the information is read-only. ++* ++* INPUT: ++* pexIf - PEX interface number. ++* busNum - Bus number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_NOT_ALLOWED in case PEX interface is PEX-X. ++* MV_BAD_PARAM on bad parameters , ++* otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPexLocalBusNumSet(MV_U32 pexIf, MV_U32 busNum) ++{ ++ MV_U32 pexStatus; ++ MV_U32 localBus; ++ MV_U32 localDev; ++ ++ ++ /* Parameter checking */ ++ if (pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexLocalBusNumSet: ERR. Invalid PEX interface %d\n",pexIf); ++ return MV_BAD_PARAM; ++ } ++ if (busNum >= MAX_PEX_BUSSES) ++ { ++ mvOsPrintf("mvPexLocalBusNumSet: ERR. bus number illigal %d\n", busNum); ++ return MV_ERROR; ++ ++ } ++ ++ localBus = mvPexLocalBusNumGet(pexIf); ++ localDev = mvPexLocalDevNumGet(pexIf); ++ ++ ++ ++ pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); ++ ++ pexStatus &= ~PXSR_PEX_BUS_NUM_MASK; ++ ++ pexStatus |= (busNum << PXSR_PEX_BUS_NUM_OFFS) & PXSR_PEX_BUS_NUM_MASK; ++ ++ MV_REG_WRITE(PEX_STATUS_REG(pexIf), pexStatus); ++ ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvPexLocalBusNumGet - Get PEX interface local bus number. ++* ++* DESCRIPTION: ++* This function gets the local bus number of a given PEX interface. ++* ++* INPUT: ++* pexIf - PEX interface number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Local bus number.0xffffffff on Error ++* ++*******************************************************************************/ ++MV_U32 mvPexLocalBusNumGet(MV_U32 pexIf) ++{ ++ MV_U32 pexStatus; ++ ++ /* Parameter checking */ ++ if (PEX_DEFAULT_IF != pexIf) ++ { ++ if (pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexLocalBusNumGet: ERR. Invalid PEX interface %d\n",pexIf); ++ return 0xFFFFFFFF; ++ } ++ } ++ ++ ++ pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); ++ ++ pexStatus &= PXSR_PEX_BUS_NUM_MASK; ++ ++ return (pexStatus >> PXSR_PEX_BUS_NUM_OFFS); ++ ++} ++ ++ ++/******************************************************************************* ++* mvPexLocalDevNumSet - Set PEX interface local device number. ++* ++* DESCRIPTION: ++* This function sets given PEX interface its local device number. ++* Note: In case the PEX interface is PEX-X, the information is read-only. ++* ++* INPUT: ++* pexIf - PEX interface number. ++* devNum - Device number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_NOT_ALLOWED in case PEX interface is PEX-X. ++* MV_BAD_PARAM on bad parameters , ++* otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPexLocalDevNumSet(MV_U32 pexIf, MV_U32 devNum) ++{ ++ MV_U32 pexStatus; ++ MV_U32 localBus; ++ MV_U32 localDev; ++ ++ /* Parameter checking */ ++ if (pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexLocalDevNumSet: ERR. Invalid PEX interface %d\n",pexIf); ++ return MV_BAD_PARAM; ++ } ++ if (devNum >= MAX_PEX_DEVICES) ++ { ++ mvOsPrintf("mvPexLocalDevNumSet: ERR. device number illigal %d\n", ++ devNum); ++ return MV_BAD_PARAM; ++ ++ } ++ ++ localBus = mvPexLocalBusNumGet(pexIf); ++ localDev = mvPexLocalDevNumGet(pexIf); ++ ++ ++ pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); ++ ++ pexStatus &= ~PXSR_PEX_DEV_NUM_MASK; ++ ++ pexStatus |= (devNum << PXSR_PEX_DEV_NUM_OFFS) & PXSR_PEX_DEV_NUM_MASK; ++ ++ MV_REG_WRITE(PEX_STATUS_REG(pexIf), pexStatus); ++ ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvPexLocalDevNumGet - Get PEX interface local device number. ++* ++* DESCRIPTION: ++* This function gets the local device number of a given PEX interface. ++* ++* INPUT: ++* pexIf - PEX interface number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Local device number. 0xffffffff on Error ++* ++*******************************************************************************/ ++MV_U32 mvPexLocalDevNumGet(MV_U32 pexIf) ++{ ++ MV_U32 pexStatus; ++ ++ /* Parameter checking */ ++ ++ if (PEX_DEFAULT_IF != pexIf) ++ { ++ if (pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexLocalDevNumGet: ERR. Invalid PEX interface %d\n", ++ pexIf); ++ return 0xFFFFFFFF; ++ } ++ } ++ ++ pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); ++ ++ pexStatus &= PXSR_PEX_DEV_NUM_MASK; ++ ++ return (pexStatus >> PXSR_PEX_DEV_NUM_OFFS); ++} ++ ++MV_VOID mvPexPhyRegRead(MV_U32 pexIf, MV_U32 regOffset, MV_U16 *value) ++{ ++ ++ MV_U32 regAddr; ++ if (pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexPhyRegRead: ERR. Invalid PEX interface %d\n", pexIf); ++ return; ++ } ++ regAddr = (BIT31 | ((regOffset & 0x3fff) << 16)); ++ MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexIf), regAddr); ++ *value = MV_REG_READ(PEX_PHY_ACCESS_REG(pexIf)); ++} ++ ++ ++MV_VOID mvPexPhyRegWrite(MV_U32 pexIf, MV_U32 regOffset, MV_U16 value) ++{ ++ ++ MV_U32 regAddr; ++ if(pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexPhyRegWrite: ERR. Invalid PEX interface %d\n", pexIf); ++ return; ++ } ++ regAddr = (((regOffset & 0x3fff) << 16) | value); ++ MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexIf), regAddr); ++} ++ ++/******************************************************************************* ++* mvPexActiveStateLinkPMEnable ++* ++* DESCRIPTION: ++* Enable Active Link State Power Management ++* ++* INPUT: ++* pexIf - PEX interface number. ++* enable - MV_TRUE to enable ASPM, MV_FALSE to disable. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* MV_OK on success , MV_ERROR otherwise ++* ++*******************************************************************************/ ++MV_STATUS mvPexActiveStateLinkPMEnable(MV_U32 pexIf, MV_BOOL enable) ++{ ++ MV_U32 reg; ++ ++ if(pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexActiveStateLinkPMEnable: ERR. Invalid PEX interface %d\n", pexIf); ++ return MV_ERROR; ++ } ++ ++ reg = MV_REG_READ(PEX_PWR_MNG_EXT_REG(pexIf)) & ~PXPMER_L1_ASPM_EN_MASK; ++ if(enable == MV_TRUE) ++ reg |= PXPMER_L1_ASPM_EN_MASK; ++ MV_REG_WRITE(PEX_PWR_MNG_EXT_REG(pexIf), reg); ++ ++ /* Enable / Disable L0/1 entry */ ++ reg = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG)) ++ & ~PXLCSR_ASPM_CNT_MASK; ++ if(enable == MV_TRUE) ++ reg |= PXLCSR_ASPM_CNT_L0S_L1S_ENT_SUPP; ++ MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG), reg); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvPexForceX1 ++* ++* DESCRIPTION: ++* shut down lanes 1-3 if recognize that attached to an x1 end-point ++* INPUT: ++* pexIf - PEX interface number. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* MV_OK on success , MV_ERROR otherwise ++* ++*******************************************************************************/ ++MV_U32 mvPexForceX1(MV_U32 pexIf) ++{ ++ MV_U32 regData = 0; ++ if(pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexForceX1: ERR. Invalid PEX interface %d\n", pexIf); ++ return MV_BAD_PARAM; ++ } ++ ++ regData = MV_REG_READ(PEX_CTRL_REG(pexIf)) & ~(PXCR_CONF_LINK_MASK) ; ++ regData |= PXCR_CONF_LINK_X1; ++ ++ MV_REG_WRITE(PEX_CTRL_REG(pexIf), regData); ++ return MV_OK; ++} ++ ++MV_BOOL mvPexIsPowerUp(MV_U32 pexIf) ++{ ++ if(pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexIsPowerUp: ERR. Invalid PEX interface %d\n", pexIf); ++ return MV_FALSE; ++ } ++ return mvCtrlPwrClckGet(PEX_UNIT_ID, pexIf); ++} ++ ++ ++MV_VOID mvPexPowerDown(MV_U32 pexIf) ++{ ++ if ( (mvCtrlModelGet() == MV_78XX0_DEV_ID) || ++ (mvCtrlModelGet() == MV_76100_DEV_ID) || ++ (mvCtrlModelGet() == MV_78100_DEV_ID) || ++ (mvCtrlModelGet() == MV_78200_DEV_ID) ) ++ { ++ mvCtrlPwrClckSet(PEX_UNIT_ID, pexIf, MV_FALSE); ++ } ++ else ++ { ++ MV_REG_WRITE((0x41B00 -(pexIf)*0x10000), 0x20800087); ++ } ++} ++ ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,168 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCPEXH ++#define __INCPEXH ++ ++#include "mvCommon.h" ++#include "mvOs.h" ++#include "pex/mvPexRegs.h" ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++ ++ ++ ++/* NOTE not supported in this driver:*/ ++ ++ ++/* defines */ ++/* The number of supported PEX interfaces depend on Marvell controller */ ++/* device number. This device number ID is located on the PEX unit */ ++/* configuration header. This creates a loop where calling PEX */ ++/* configuration read/write routine results a call to get PEX configuration */ ++/* information etc. This macro defines a default PEX interface. This PEX */ ++/* interface is sure to exist. */ ++#define PEX_DEFAULT_IF 0 ++ ++ ++/* typedefs */ ++/* The Marvell controller supports both root complex and end point devices */ ++/* This enumeration describes the PEX type. */ ++typedef enum _mvPexType ++{ ++ MV_PEX_ROOT_COMPLEX, /* root complex device */ ++ MV_PEX_END_POINT /* end point device */ ++}MV_PEX_TYPE; ++ ++typedef enum _mvPexWidth ++{ ++ MV_PEX_WITDH_X1 = 1, ++ MV_PEX_WITDH_X2, ++ MV_PEX_WITDH_X3, ++ MV_PEX_WITDH_X4, ++ MV_PEX_WITDH_INVALID ++}MV_PEX_WIDTH; ++ ++/* PEX Bar attributes */ ++typedef struct _mvPexMode ++{ ++ MV_PEX_TYPE pexType; ++ MV_PEX_WIDTH pexWidth; ++ MV_BOOL pexLinkUp; ++}MV_PEX_MODE; ++ ++ ++ ++/* Global Functions prototypes */ ++/* mvPexInit - Initialize PEX interfaces*/ ++MV_STATUS mvPexHalInit(MV_U32 pexIf, MV_PEX_TYPE pexType); ++ ++/* mvPexModeGet - Get Pex If mode */ ++MV_U32 mvPexModeGet(MV_U32 pexIf,MV_PEX_MODE *pexMode); ++ ++/* mvPexConfigRead - Read from configuration space */ ++MV_U32 mvPexConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func,MV_U32 regOff); ++ ++/* mvPexConfigWrite - Write to configuration space */ ++MV_STATUS mvPexConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func, MV_U32 regOff, MV_U32 data); ++ ++/* mvPexMasterEnable - Enable/disale PEX interface master transactions.*/ ++MV_STATUS mvPexMasterEnable(MV_U32 pexIf, MV_BOOL enable); ++ ++/* mvPexSlaveEnable - Enable/disale PEX interface slave transactions.*/ ++MV_STATUS mvPexSlaveEnable(MV_U32 pexIf, MV_U32 bus,MV_U32 dev, MV_BOOL enable); ++ ++/* mvPexLocalBusNumSet - Set PEX interface local bus number.*/ ++MV_STATUS mvPexLocalBusNumSet(MV_U32 pexIf, MV_U32 busNum); ++ ++/* mvPexLocalBusNumGet - Get PEX interface local bus number.*/ ++MV_U32 mvPexLocalBusNumGet(MV_U32 pexIf); ++ ++/* mvPexLocalDevNumSet - Set PEX interface local device number.*/ ++MV_STATUS mvPexLocalDevNumSet(MV_U32 pexIf, MV_U32 devNum); ++ ++/* mvPexLocalDevNumGet - Get PEX interface local device number.*/ ++MV_U32 mvPexLocalDevNumGet(MV_U32 pexIf); ++/* mvPexForceX1 - Force PEX interface to X1 mode. */ ++MV_U32 mvPexForceX1(MV_U32 pexIf); ++ ++/* mvPexIsPowerUp - Is PEX interface Power up? */ ++MV_BOOL mvPexIsPowerUp(MV_U32 pexIf); ++ ++/* mvPexPowerDown - Power Down */ ++MV_VOID mvPexPowerDown(MV_U32 pexIf); ++ ++/* mvPexPowerUp - Power Up */ ++MV_VOID mvPexPowerUp(MV_U32 pexIf); ++ ++/* mvPexPhyRegRead - Pex phy read */ ++MV_VOID mvPexPhyRegRead(MV_U32 pexIf, MV_U32 regOffset, MV_U16 *value); ++ ++/* mvPexPhyRegWrite - Pex phy write */ ++MV_VOID mvPexPhyRegWrite(MV_U32 pexIf, MV_U32 regOffset, MV_U16 value); ++ ++MV_STATUS mvPexActiveStateLinkPMEnable(MV_U32 pexIf, MV_BOOL enable); ++ ++#endif /* #ifndef __INCPEXH */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,751 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCPEXREGSH ++#define __INCPEXREGSH ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++/* defines */ ++#define MAX_PEX_DEVICES 32 ++#define MAX_PEX_FUNCS 8 ++#define MAX_PEX_BUSSES 256 ++ ++ ++ ++/*********************************************************/ ++/* PCI Express Configuration Cycles Generation Registers */ ++/*********************************************************/ ++ ++#define PEX_CFG_ADDR_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x18F8) ++#define PEX_CFG_DATA_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x18FC) ++#define PEX_PHY_ACCESS_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1B00) ++/* PCI Express Configuration Address Register */ ++/* PEX_CFG_ADDR_REG (PXCAR)*/ ++ ++#define PXCAR_REG_NUM_OFFS 2 ++#define PXCAR_REG_NUM_MAX 0x3F ++#define PXCAR_REG_NUM_MASK (PXCAR_REG_NUM_MAX << PXCAR_REG_NUM_OFFS) ++#define PXCAR_FUNC_NUM_OFFS 8 ++#define PXCAR_FUNC_NUM_MAX 0x7 ++#define PXCAR_FUNC_NUM_MASK (PXCAR_FUNC_NUM_MAX << PXCAR_FUNC_NUM_OFFS) ++#define PXCAR_DEVICE_NUM_OFFS 11 ++#define PXCAR_DEVICE_NUM_MAX 0x1F ++#define PXCAR_DEVICE_NUM_MASK (PXCAR_DEVICE_NUM_MAX << PXCAR_DEVICE_NUM_OFFS) ++#define PXCAR_BUS_NUM_OFFS 16 ++#define PXCAR_BUS_NUM_MAX 0xFF ++#define PXCAR_BUS_NUM_MASK (PXCAR_BUS_NUM_MAX << PXCAR_BUS_NUM_OFFS) ++#define PXCAR_EXT_REG_NUM_OFFS 24 ++#define PXCAR_EXT_REG_NUM_MAX 0xF ++ ++/* in pci express register address is now the legacy register address (8 bits) ++with the new extended register address (more 4 bits) , below is the mask of ++the upper 4 bits of the full register address */ ++ ++#define PXCAR_REAL_EXT_REG_NUM_OFFS 8 ++#define PXCAR_EXT_REG_NUM_MASK (PXCAR_EXT_REG_NUM_MAX << PXCAR_EXT_REG_NUM_OFFS) ++#define PXCAR_CONFIG_EN BIT31 ++ ++#define PXCAR_REAL_EXT_REG_NUM_OFFS 8 ++#define PXCAR_REAL_EXT_REG_NUM_MASK (0xF << PXCAR_REAL_EXT_REG_NUM_OFFS) ++ ++/* The traditional PCI spec defined 6-bit field to describe register offset.*/ ++/* The new PCI Express extend the register offset by an extra 4-bits. */ ++/* The below macro assign 10-bit register offset into the apprpreate */ ++/* fields in the CFG_ADDR_REG */ ++#define PXCAR_REG_OFFS_SET(regOffs) \ ++ ( (regOff & PXCAR_REG_NUM_MASK) | \ ++ ( ((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >> PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS) ) ++ ++/***********************************/ ++/* PCI Express Interrupt registers */ ++/***********************************/ ++#define PEX_CAUSE_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1900) ++#define PEX_MASK_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1910) ++ ++#define PXICR_TX_REQ_IN_DLDOWN_ERR BIT0 /* Transmit request while field */ ++ /* of the PCI Express */ ++/* PCI Express Interrupt Cause */ ++/* PEX_INT_CAUSE_REG (PXICR)*/ ++/* PEX_INT_MASK_REG*/ ++/* ++NOTE:All bits except bits[27:24] are Read/Write Clear only. A cause bit sets ++upon an error event occurrence. A write of 0 clears the bit. A write of 1 has ++no affect. Bits[24:27} are set and cleared upon reception of interrupt ++emulation messages. ++ ++Mask bit per cause bit. If a bit is set to 1, the corresponding event is ++enabled. Mask does not affect setting of the Interrupt Cause register bits; ++it only affects the assertion of the interrupt .*/ ++ ++ ++#define PXICR_MDIS_CAUSE BIT1 /* Attempt to generate PCI transaction ++ while master is disabled */ ++#define PXICR_ERR_WRTO_REG_CAUSE BIT3 /* Erroneous write attempt to ++ PCI Express internal register*/ ++#define PXICR_HIT_DFLT_WIN_ERR BIT4 /* Hit Default Window Error */ ++#define PXICR_RX_RAM_PAR_ERR BIT6 /* Rx RAM Parity Error */ ++#define PXICR_TX_RAM_PAR_ERR BIT7 /* Tx RAM Parity Error */ ++#define PXICR_COR_ERR_DET BIT8 /* Correctable Error Detected*/ ++#define PXICR_NF_ERR_DET BIT9 /* Non-Fatal Error Detected*/ ++#define PXICR_FERR_DET BIT10 /* Fatal Error Detected*/ ++#define PXICR_DSTATE_CHANGE BIT11 /* Dstate Change Indication*/ ++#define PXICR_BIST BIT12 /* PCI-Express BIST activated*/ ++#define PXICR_FLW_CTRL_PROT BIT14 /* Flow Control Protocol Error */ ++ ++#define PXICR_RCV_UR_CA_ERR BIT15 /* Received UR or CA status. */ ++#define PXICR_RCV_ERR_FATAL BIT16 /* Received ERR_FATAL message.*/ ++#define PXICR_RCV_ERR_NON_FATAL BIT17 /* Received ERR_NONFATAL message*/ ++#define PXICR_RCV_ERR_COR BIT18 /* Received ERR_COR message.*/ ++#define PXICR_RCV_CRS BIT19 /* Received CRS completion status*/ ++#define PXICR_SLV_HOT_RESET BIT20 /* Received Hot Reset Indication*/ ++#define PXICR_SLV_DIS_LINK BIT21 /* Slave Disable Link Indication*/ ++#define PXICR_SLV_LB BIT22 /* Slave Loopback Indication*/ ++#define PXICR_LINK_FAIL BIT23 /* Link Failure indication.*/ ++#define PXICR_RCV_INTA BIT24 /* IntA status.*/ ++#define PXICR_RCV_INTB BIT25 /* IntB status.*/ ++#define PXICR_RCV_INTC BIT26 /* IntC status.*/ ++#define PXICR_RCV_INTD BIT27 /* IntD status.*/ ++#define PXICR_RCV_PM_PME BIT28 /* Received PM_PME message. */ ++ ++ ++/********************************************/ ++/* PCI Express Control and Status Registers */ ++/********************************************/ ++#define PEX_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A00) ++#define PEX_STATUS_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A04) ++#define PEX_COMPLT_TMEOUT_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A10) ++#define PEX_PWR_MNG_EXT_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A18) ++#define PEX_FLOW_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A20) ++#define PEX_ACK_TMR_4X_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A30) ++#define PEX_ACK_TMR_1X_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A40) ++#define PEX_TL_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1AB0) ++ ++ ++#define PEX_RAM_PARITY_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A50) ++/* PCI Express Control Register */ ++/* PEX_CTRL_REG (PXCR) */ ++ ++#define PXCR_CONF_LINK_OFFS 0 ++#define PXCR_CONF_LINK_MASK (1 << PXCR_CONF_LINK_OFFS) ++#define PXCR_CONF_LINK_X4 (0 << PXCR_CONF_LINK_OFFS) ++#define PXCR_CONF_LINK_X1 (1 << PXCR_CONF_LINK_OFFS) ++#define PXCR_DEV_TYPE_CTRL_OFFS 1 /*PCI ExpressDevice Type Control*/ ++#define PXCR_DEV_TYPE_CTRL_MASK BIT1 ++#define PXCR_DEV_TYPE_CTRL_CMPLX (1 << PXCR_DEV_TYPE_CTRL_OFFS) ++#define PXCR_DEV_TYPE_CTRL_POINT (0 << PXCR_DEV_TYPE_CTRL_OFFS) ++#define PXCR_CFG_MAP_TO_MEM_EN BIT2 /* Configuration Header Mapping ++ to Memory Space Enable */ ++ ++#define PXCR_CFG_MAP_TO_MEM_EN BIT2 /* Configuration Header Mapping ++ to Memory Space Enable*/ ++ ++#define PXCR_RSRV1_OFFS 5 ++#define PXCR_RSRV1_MASK (0x7 << PXCR_RSRV1_OFFS) ++#define PXCR_RSRV1_VAL (0x0 << PXCR_RSRV1_OFFS) ++ ++#define PXCR_CONF_MAX_OUTSTND_OFFS 8 /*Maximum outstanding NP requests as a master*/ ++#define PXCR_CONF_MAX_OUTSTND_MASK (0x3 << PXCR_CONF_MAX_OUTSTND_OFFS) ++ ++ ++#define PXCR_CONF_NFTS_OFFS 16 /*number of FTS Ordered-Sets*/ ++#define PXCR_CONF_NFTS_MASK (0xff << PXCR_CONF_NFTS_OFFS) ++ ++#define PXCR_CONF_MSTR_HOT_RESET BIT24 /*Master Hot-Reset.*/ ++#define PXCR_CONF_MSTR_LB BIT26 /* Master Loopback */ ++#define PXCR_CONF_MSTR_DIS_SCRMB BIT27 /* Master Disable Scrambling*/ ++#define PXCR_CONF_DIRECT_DIS_SCRMB BIT28 /* Direct Disable Scrambling*/ ++ ++/* PCI Express Status Register */ ++/* PEX_STATUS_REG (PXSR) */ ++ ++#define PXSR_DL_DOWN BIT0 /* DL_Down indication.*/ ++ ++#define PXSR_PEX_BUS_NUM_OFFS 8 /* Bus Number Indication */ ++#define PXSR_PEX_BUS_NUM_MASK (0xff << PXSR_PEX_BUS_NUM_OFFS) ++ ++#define PXSR_PEX_DEV_NUM_OFFS 16 /* Device Number Indication */ ++#define PXSR_PEX_DEV_NUM_MASK (0x1f << PXSR_PEX_DEV_NUM_OFFS) ++ ++#define PXSR_PEX_SLV_HOT_RESET BIT24 /* Slave Hot Reset Indication*/ ++#define PXSR_PEX_SLV_DIS_LINK BIT25 /* Slave Disable Link Indication*/ ++#define PXSR_PEX_SLV_LB BIT26 /* Slave Loopback Indication*/ ++#define PXSR_PEX_SLV_DIS_SCRMB BIT27 /* Slave Disable Scrambling Indication*/ ++ ++ ++/* PCI Express Completion Timeout Register */ ++/* PEX_COMPLT_TMEOUT_REG (PXCTR)*/ ++ ++#define PXCTR_CMP_TO_THRSHLD_OFFS 0 /* Completion Timeout Threshold */ ++#define PXCTR_CMP_TO_THRSHLD_MASK (0xffff << PXCTR_CMP_TO_THRSHLD_OFFS) ++ ++/* PCI Express Power Management Extended Register */ ++/* PEX_PWR_MNG_EXT_REG (PXPMER) */ ++ ++#define PXPMER_L1_ASPM_EN_OFFS 1 ++#define PXPMER_L1_ASPM_EN_MASK (0x1 << PXPMER_L1_ASPM_EN_OFFS) ++ ++/* PCI Express Flow Control Register */ ++/* PEX_FLOW_CTRL_REG (PXFCR)*/ ++ ++#define PXFCR_PH_INIT_FC_OFFS 0 /*Posted Headers Flow Control Credit ++ Initial Value.*/ ++#define PXFCR_PH_INIT_FC_MASK (0xff << PXFCR_PH_INIT_FC_OFFS) ++ ++ ++#define PXFCR_NPH_INIT_FC_OFFS 8 /* Classified Non-Posted Headers ++ Flow Control Credit Initial Value*/ ++#define PXFCR_NPH_INIT_FC_MASK (0xff << PXFCR_NPH_INIT_FC_OFFS) ++ ++#define PXFCR_CH_INIT_FC_OFFS 16 /* Completion Headers Flow Control ++ Credit Initial Value Infinite*/ ++ ++#define PXFCR_CH_INIT_FC_MASK (0xff << PXFCR_CH_INIT_FC_OFFS) ++ ++#define PXFCR_FC_UPDATE_TO_OFFS 24 /* Flow Control Update Timeout */ ++#define PXFCR_FC_UPDATE_TO_MASK (0xff << PXFCR_FC_UPDATE_TO_OFFS) ++ ++/* PCI Express Acknowledge Timers (4X) Register */ ++/* PEX_ACK_TMR_4X_REG (PXAT4R) */ ++#define PXAT1R_ACK_LAT_TOX4_OFFS 0 /* Ack Latency Timer Timeout Value */ ++#define PXAT1R_ACK_LAT_TOX4_MASK (0xffff << PXAT4R_ACK_LAT_TOX1_OFFS) ++#define PXAT1R_ACK_RPLY_TOX4_OFFS 16 /* Ack Replay Timer Timeout Value */ ++#define PXAT1R_ACK_RPLY_TOX4_MASK (0xffff << PXAT1R_ACK_RPLY_TOX1_OFFS) ++ ++/* PCI Express Acknowledge Timers (1X) Register */ ++/* PEX_ACK_TMR_1X_REG (PXAT1R) */ ++ ++#define PXAT1R_ACK_LAT_TOX1_OFFS 0 /* Acknowledge Latency Timer Timeout ++ Value for 1X Link*/ ++#define PXAT1R_ACK_LAT_TOX1_MASK (0xffff << PXAT1R_ACK_LAT_TOX1_OFFS) ++ ++#define PXAT1R_ACK_RPLY_TOX1_OFFS 16 /* Acknowledge Replay Timer Timeout ++ Value for 1X*/ ++#define PXAT1R_ACK_RPLY_TOX1_MASK (0xffff << PXAT1R_ACK_RPLY_TOX1_OFFS) ++ ++ ++/* PCI Express TL Control Register */ ++/* PEX_TL_CTRL_REG (PXTCR) */ ++ ++#define PXTCR_TX_CMP_BUFF_NO_OFFS 8 /*Number of completion buffers in Tx*/ ++#define PXTCR_TX_CMP_BUFF_NO_MASK (0xf << PXTCR_TX_CMP_BUFF_NO_OFFS) ++ ++/* PCI Express Debug MAC Control Register */ ++/* PEX_DEBUG_MAC_CTRL_REG (PXDMCR) */ ++ ++#define PXDMCR_LINKUP BIT4 ++ ++ ++ ++/**********************************************/ ++/* PCI Express Configuration Header Registers */ ++/**********************************************/ ++#define PEX_CFG_DIRECT_ACCESS(pexIf,cfgReg) ((PEX_IF_BASE(pexIf)) + (cfgReg)) ++ ++#define PEX_DEVICE_AND_VENDOR_ID 0x000 ++#define PEX_STATUS_AND_COMMAND 0x004 ++#define PEX_CLASS_CODE_AND_REVISION_ID 0x008 ++#define PEX_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE 0x00C ++#define PEX_MEMORY_BAR_BASE_ADDR(barNum) (0x010 + ((barNum) << 2)) ++#define PEX_MV_BAR_BASE(barNum) (0x010 + (barNum) * 8) ++#define PEX_MV_BAR_BASE_HIGH(barNum) (0x014 + (barNum) * 8) ++#define PEX_BAR0_INTER_REG 0x010 ++#define PEX_BAR0_INTER_REG_HIGH 0x014 ++#define PEX_BAR1_REG 0x018 ++#define PEX_BAR1_REG_HIGH 0x01C ++#define PEX_BAR2_REG 0x020 ++#define PEX_BAR2_REG_HIGH 0x024 ++ ++#define PEX_SUBSYS_ID_AND_SUBSYS_VENDOR_ID 0x02C ++#define PEX_EXPANSION_ROM_BASE_ADDR_REG 0x030 ++#define PEX_CAPABILTY_LIST_POINTER 0x034 ++#define PEX_INTERRUPT_PIN_AND_LINE 0x03C ++ ++/* capability list */ ++#define PEX_POWER_MNG_CAPABILITY 0x040 ++#define PEX_POWER_MNG_STATUS_CONTROL 0x044 ++ ++#define PEX_MSI_MESSAGE_CONTROL 0x050 ++#define PEX_MSI_MESSAGE_ADDR 0x054 ++#define PEX_MSI_MESSAGE_HIGH_ADDR 0x058 ++#define PEX_MSI_MESSAGE_DATA 0x05C ++ ++#define PEX_CAPABILITY_REG 0x60 ++#define PEX_DEV_CAPABILITY_REG 0x64 ++#define PEX_DEV_CTRL_STAT_REG 0x68 ++#define PEX_LINK_CAPABILITY_REG 0x6C ++#define PEX_LINK_CTRL_STAT_REG 0x70 ++ ++#define PEX_ADV_ERR_RPRT_HDR_TRGT_REG 0x100 ++#define PEX_UNCORRECT_ERR_STAT_REG 0x104 ++#define PEX_UNCORRECT_ERR_MASK_REG 0x108 ++#define PEX_UNCORRECT_ERR_SERVITY_REG 0x10C ++#define PEX_CORRECT_ERR_STAT_REG 0x110 ++#define PEX_CORRECT_ERR_MASK_REG 0x114 ++#define PEX_ADV_ERR_CAPABILITY_CTRL_REG 0x118 ++#define PEX_HDR_LOG_FIRST_DWORD_REG 0x11C ++#define PEX_HDR_LOG_SECOND_DWORD_REG 0x120 ++#define PEX_HDR_LOG_THIRD_DWORD_REG 0x124 ++#define PEX_HDR_LOG_FOURTH_DWORD_REG 0x128 ++ ++ ++ ++/* PCI Express Device and Vendor ID Register*/ ++/*PEX_DEVICE_AND_VENDOR_ID (PXDAVI)*/ ++ ++#define PXDAVI_VEN_ID_OFFS 0 /* Vendor ID */ ++#define PXDAVI_VEN_ID_MASK (0xffff << PXDAVI_VEN_ID_OFFS) ++ ++#define PXDAVI_DEV_ID_OFFS 16 /* Device ID */ ++#define PXDAVI_DEV_ID_MASK (0xffff << PXDAVI_DEV_ID_OFFS) ++ ++ ++/* PCI Express Command and Status Register*/ ++/*PEX_STATUS_AND_COMMAND (PXSAC)*/ ++ ++#define PXSAC_IO_EN BIT0 /* IO Enable */ ++#define PXSAC_MEM_EN BIT1 /* Memory Enable */ ++#define PXSAC_MASTER_EN BIT2 /* Master Enable */ ++#define PXSAC_PERR_EN BIT6 /* Parity Errors Respond Enable */ ++#define PXSAC_SERR_EN BIT8 /* Ability to assert SERR# line */ ++#define PXSAC_INT_DIS BIT10 /* Interrupt Disable */ ++#define PXSAC_INT_STAT BIT19 /* Interrupt Status */ ++#define PXSAC_CAP_LIST BIT20 /* Capability List Support */ ++#define PXSAC_MAS_DATA_PERR BIT24 /* Master Data Parity Error */ ++#define PXSAC_SLAVE_TABORT BIT27 /* Signalled Target Abort */ ++#define PXSAC_RT_ABORT BIT28 /* Recieved Target Abort */ ++#define PXSAC_MABORT BIT29 /* Recieved Master Abort */ ++#define PXSAC_SYSERR BIT30 /* Signalled system error */ ++#define PXSAC_DET_PARERR BIT31 /* Detect Parity Error */ ++ ++ ++/* PCI Express Class Code and Revision ID Register*/ ++/*PEX_CLASS_CODE_AND_REVISION_ID (PXCCARI)*/ ++ ++#define PXCCARI_REVID_OFFS 0 /* Revision ID */ ++#define PXCCARI_REVID_MASK (0xff << PXCCARI_REVID_OFFS) ++ ++#define PXCCARI_FULL_CLASS_OFFS 8 /* Full Class Code */ ++#define PXCCARI_FULL_CLASS_MASK (0xffffff << PXCCARI_FULL_CLASS_OFFS) ++ ++#define PXCCARI_PROGIF_OFFS 8 /* Prog .I/F*/ ++#define PXCCARI_PROGIF_MASK (0xff << PXCCARI_PROGIF_OFFS) ++ ++#define PXCCARI_SUB_CLASS_OFFS 16 /* Sub Class*/ ++#define PXCCARI_SUB_CLASS_MASK (0xff << PXCCARI_SUB_CLASS_OFFS) ++ ++#define PXCCARI_BASE_CLASS_OFFS 24 /* Base Class*/ ++#define PXCCARI_BASE_CLASS_MASK (0xff << PXCCARI_BASE_CLASS_OFFS) ++ ++ ++/* PCI Express BIST, Header Type and Cache Line Size Register*/ ++/*PEX_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE (PXBHTLTCL)*/ ++ ++#define PXBHTLTCL_CACHELINE_OFFS 0 /* Specifies the cache line size */ ++#define PXBHTLTCL_CACHELINE_MASK (0xff << PXBHTLTCL_CACHELINE_OFFS) ++ ++#define PXBHTLTCL_HEADTYPE_FULL_OFFS 16 /* Full Header Type */ ++#define PXBHTLTCL_HEADTYPE_FULL_MASK (0xff << PXBHTLTCL_HEADTYPE_FULL_OFFS) ++ ++#define PXBHTLTCL_MULTI_FUNC BIT23 /* Multi/Single function */ ++ ++#define PXBHTLTCL_HEADER_OFFS 16 /* Header type */ ++#define PXBHTLTCL_HEADER_MASK (0x7f << PXBHTLTCL_HEADER_OFFS) ++#define PXBHTLTCL_HEADER_STANDARD (0x0 << PXBHTLTCL_HEADER_OFFS) ++#define PXBHTLTCL_HEADER_PCI2PCI_BRIDGE (0x1 << PXBHTLTCL_HEADER_OFFS) ++ ++ ++#define PXBHTLTCL_BISTCOMP_OFFS 24 /* BIST Completion Code */ ++#define PXBHTLTCL_BISTCOMP_MASK (0xf << PXBHTLTCL_BISTCOMP_OFFS) ++ ++#define PXBHTLTCL_BISTACT BIT30 /* BIST Activate bit */ ++#define PXBHTLTCL_BISTCAP BIT31 /* BIST Capable Bit */ ++#define PXBHTLTCL_BISTCAP_OFFS 31 ++#define PXBHTLTCL_BISTCAP_MASK BIT31 ++#define PXBHTLTCL_BISTCAP_VAL 0 ++ ++ ++/* PCI Express Subsystem Device and Vendor ID */ ++/*PEX_SUBSYS_ID_AND_SUBSYS_VENDOR_ID (PXSIASVI)*/ ++ ++#define PXSIASVI_VENID_OFFS 0 /* Subsystem Manufacturer Vendor ID Number */ ++#define PXSIASVI_VENID_MASK (0xffff << PXSIASVI_VENID_OFFS) ++ ++#define PXSIASVI_DEVID_OFFS 16 /* Subsystem Device ID Number */ ++#define PXSIASVI_DEVID_MASK (0xffff << PXSIASVI_DEVID_OFFS) ++ ++ ++/* PCI Express Capability List Pointer Register*/ ++/*PEX_CAPABILTY_LIST_POINTER (PXCLP)*/ ++ ++#define PXCLP_CAPPTR_OFFS 0 /* Capability List Pointer */ ++#define PXCLP_CAPPTR_MASK (0xff << PXCLP_CAPPTR_OFFS) ++ ++/* PCI Express Interrupt Pin and Line Register */ ++/*PEX_INTERRUPT_PIN_AND_LINE (PXIPAL)*/ ++ ++#define PXIPAL_INTLINE_OFFS 0 /* Interrupt line (IRQ) */ ++#define PXIPAL_INTLINE_MASK (0xff << PXIPAL_INTLINE_OFFS) ++ ++#define PXIPAL_INTPIN_OFFS 8 /* interrupt pin (A,B,C,D) */ ++#define PXIPAL_INTPIN_MASK (0xff << PXIPAL_INTPIN_OFFS) ++ ++ ++/* PCI Express Power Management Capability Header Register*/ ++/*PEX_POWER_MNG_CAPABILITY (PXPMC)*/ ++ ++#define PXPMC_CAP_ID_OFFS 0 /* Capability ID */ ++#define PXPMC_CAP_ID_MASK (0xff << PXPMC_CAP_ID_OFFS) ++ ++#define PXPMC_NEXT_PTR_OFFS 8 /* Next Item Pointer */ ++#define PXPMC_NEXT_PTR_MASK (0xff << PXPMC_NEXT_PTR_OFFS) ++ ++#define PXPMC_PMC_VER_OFFS 16 /* PCI Power Management Capability Version*/ ++#define PXPMC_PMC_VER_MASK (0x7 << PXPMC_PMC_VER_OFFS) ++ ++#define PXPMC_DSI BIT21/* Device Specific Initialization */ ++ ++#define PXPMC_AUX_CUR_OFFS 22 /* Auxiliary Current Requirements */ ++#define PXPMC_AUX_CUR_MASK (0x7 << PXPMC_AUX_CUR_OFFS) ++ ++#define PXPMC_D1_SUP BIT25 /* D1 Power Management support*/ ++ ++#define PXPMC_D2_SUP BIT26 /* D2 Power Management support*/ ++ ++#define PXPMC_PME_SUP_OFFS 27 /* PM Event generation support*/ ++#define PXPMC_PME_SUP_MASK (0x1f << PXPMC_PME_SUP_OFFS) ++ ++/* PCI Express Power Management Control and Status Register*/ ++/*PEX_POWER_MNG_STATUS_CONTROL (PXPMSC)*/ ++ ++#define PXPMSC_PM_STATE_OFFS 0 /* Power State */ ++#define PXPMSC_PM_STATE_MASK (0x3 << PXPMSC_PM_STATE_OFFS) ++#define PXPMSC_PM_STATE_D0 (0x0 << PXPMSC_PM_STATE_OFFS) ++#define PXPMSC_PM_STATE_D1 (0x1 << PXPMSC_PM_STATE_OFFS) ++#define PXPMSC_PM_STATE_D2 (0x2 << PXPMSC_PM_STATE_OFFS) ++#define PXPMSC_PM_STATE_D3 (0x3 << PXPMSC_PM_STATE_OFFS) ++ ++#define PXPMSC_PME_EN BIT8/* PM_PME Message Generation Enable */ ++ ++#define PXPMSC_PM_DATA_SEL_OFFS 9 /* Data Select*/ ++#define PXPMSC_PM_DATA_SEL_MASK (0xf << PXPMSC_PM_DATA_SEL_OFFS) ++ ++#define PXPMSC_PM_DATA_SCALE_OFFS 13 /* Data Scale */ ++#define PXPMSC_PM_DATA_SCALE_MASK (0x3 << PXPMSC_PM_DATA_SCALE_OFFS) ++ ++#define PXPMSC_PME_STAT BIT15/* PME Status */ ++ ++#define PXPMSC_PM_DATA_OFFS 24 /* State Data */ ++#define PXPMSC_PM_DATA_MASK (0xff << PXPMSC_PM_DATA_OFFS) ++ ++ ++/* PCI Express MSI Message Control Register*/ ++/*PEX_MSI_MESSAGE_CONTROL (PXMMC)*/ ++ ++#define PXMMC_CAP_ID_OFFS 0 /* Capability ID */ ++#define PXMMC_CAP_ID_MASK (0xff << PXMMC_CAP_ID_OFFS) ++ ++#define PXMMC_NEXT_PTR_OFFS 8 /* Next Item Pointer */ ++#define PXMMC_NEXT_PTR_MASK (0xff << PXMMC_NEXT_PTR_OFFS) ++ ++#define PXMMC_MSI_EN BIT18 /* MSI Enable */ ++ ++#define PXMMC_MULTI_CAP_OFFS 17 /* Multiple Message Capable */ ++#define PXMMC_MULTI_CAP_MASK (0x7 << PXMMC_MULTI_CAP_OFFS) ++ ++#define PXMMC_MULTI_EN_OFFS 20 /* Multiple Messages Enable */ ++#define PXMMC_MULTI_EN_MASK (0x7 << PXMMC_MULTI_EN_OFFS) ++ ++#define PXMMC_ADDR64 BIT23 /* 64-bit Addressing Capable */ ++ ++ ++/* PCI Express MSI Message Address Register*/ ++/*PEX_MSI_MESSAGE_ADDR (PXMMA)*/ ++ ++#define PXMMA_MSI_ADDR_OFFS 2 /* Message Address corresponds to ++ Address[31:2] of the MSI MWr TLP*/ ++#define PXMMA_MSI_ADDR_MASK (0x3fffffff << PXMMA_MSI_ADDR_OFFS) ++ ++ ++/* PCI Express MSI Message Address (High) Register */ ++/*PEX_MSI_MESSAGE_HIGH_ADDR (PXMMHA)*/ ++ ++#define PXMMA_MSI_ADDR_H_OFFS 0 /* Message Upper Address corresponds to ++ Address[63:32] of the MSI MWr TLP*/ ++#define PXMMA_MSI_ADDR_H_MASK (0xffffffff << PXMMA_MSI_ADDR_H_OFFS ) ++ ++ ++/* PCI Express MSI Message Data Register*/ ++/*PEX_MSI_MESSAGE_DATA (PXMMD)*/ ++ ++#define PXMMD_MSI_DATA_OFFS 0 /* Message Data */ ++#define PXMMD_MSI_DATA_MASK (0xffff << PXMMD_MSI_DATA_OFFS ) ++ ++ ++/* PCI Express Capability Register*/ ++/*PEX_CAPABILITY_REG (PXCR)*/ ++ ++#define PXCR_CAP_ID_OFFS 0 /* Capability ID*/ ++#define PXCR_CAP_ID_MASK (0xff << PXCR_CAP_ID_OFFS) ++ ++#define PXCR_NEXT_PTR_OFFS 8 /* Next Item Pointer*/ ++#define PXCR_NEXT_PTR_MASK (0xff << PXCR_NEXT_PTR_OFFS) ++ ++#define PXCR_CAP_VER_OFFS 16 /* Capability Version*/ ++#define PXCR_CAP_VER_MASK (0xf << PXCR_CAP_VER_OFFS) ++ ++#define PXCR_DEV_TYPE_OFFS 20 /* Device/Port Type*/ ++#define PXCR_DEV_TYPE_MASK (0xf << PXCR_DEV_TYPE_OFFS) ++ ++#define PXCR_SLOT_IMP BIT24 /* Slot Implemented*/ ++ ++#define PXCR_INT_MSG_NUM_OFFS 25 /* Interrupt Message Number*/ ++#define PXCR_INT_MSG_NUM_MASK (0x1f << PXCR_INT_MSG_NUM_OFFS) ++ ++ ++/* PCI Express Device Capabilities Register */ ++/*PEX_DEV_CAPABILITY_REG (PXDCR)*/ ++ ++#define PXDCR_MAX_PLD_SIZE_SUP_OFFS 0 /* Maximum Payload Size Supported*/ ++#define PXDCR_MAX_PLD_SIZE_SUP_MASK (0x7 << PXDCR_MAX_PLD_SIZE_SUP_OFFS) ++ ++#define PXDCR_EP_L0S_ACC_LAT_OFFS 6/* Endpoint L0s Acceptable Latency*/ ++#define PXDCR_EP_L0S_ACC_LAT_MASK (0x7 << PXDCR_EP_L0S_ACC_LAT_OFFS) ++#define PXDCR_EP_L0S_ACC_LAT_64NS_LESS (0x0 << PXDCR_EP_L0S_ACC_LAT_OFFS) ++#define PXDCR_EP_L0S_ACC_LAT_64NS_128NS (0x1 << PXDCR_EP_L0S_ACC_LAT_OFFS) ++#define PXDCR_EP_L0S_ACC_LAT_128NS_256NS (0x2 << PXDCR_EP_L0S_ACC_LAT_OFFS) ++#define PXDCR_EP_L0S_ACC_LAT_256NS_512NS (0x3 << PXDCR_EP_L0S_ACC_LAT_OFFS) ++#define PXDCR_EP_L0S_ACC_LAT_512NS_1US (0x4 << PXDCR_EP_L0S_ACC_LAT_OFFS) ++#define PXDCR_EP_L0S_ACC_LAT_1US_2US (0x5 << PXDCR_EP_L0S_ACC_LAT_OFFS) ++#define PXDCR_EP_L0S_ACC_LAT_2US_4US (0x6 << PXDCR_EP_L0S_ACC_LAT_OFFS) ++#define PXDCR_EP_L0S_ACC_LAT_4US_MORE (0x7 << PXDCR_EP_L0S_ACC_LAT_OFFS) ++ ++#define PXDCR_EP_L1_ACC_LAT_OFFS 9 /* Endpoint L1 Acceptable Latency*/ ++#define PXDCR_EP_L1_ACC_LAT_MASK (0x7 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXDCR_EP_L1_ACC_LAT_64NS_LESS (0x0 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXDCR_EP_L1_ACC_LAT_64NS_128NS (0x1 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXDCR_EP_L1_ACC_LAT_128NS_256NS (0x2 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXDCR_EP_L1_ACC_LAT_256NS_512NS (0x3 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXDCR_EP_L1_ACC_LAT_512NS_1US (0x4 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXDCR_EP_L1_ACC_LAT_1US_2US (0x5 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXDCR_EP_L1_ACC_LAT_2US_4US (0x6 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXDCR_EP_L1_ACC_LAT_4US_MORE (0x7 << PXDCR_EP_L1_ACC_LAT_OFFS) ++ ++ ++#define PXDCR_ATT_BUT_PRS_OFFS 12 /* Attention Button Present*/ ++#define PXDCR_ATT_BUT_PRS_MASK BIT12 ++#define PXDCR_ATT_BUT_PRS_IMPLEMENTED BIT12 ++ ++#define PXDCR_ATT_IND_PRS_OFFS 13 /* Attention Indicator Present*/ ++#define PXDCR_ATT_IND_PRS_MASK BIT13 ++#define PXDCR_ATT_IND_PRS_IMPLEMENTED BIT13 ++ ++#define PXDCR_PWR_IND_PRS_OFFS 14/* Power Indicator Present*/ ++#define PXDCR_PWR_IND_PRS_MASK BIT14 ++#define PXDCR_PWR_IND_PRS_IMPLEMENTED BIT14 ++ ++#define PXDCR_CAP_SPL_VAL_OFFS 18 /*Captured Slot Power Limit ++ Value*/ ++#define PXDCR_CAP_SPL_VAL_MASK (0xff << PXDCR_CAP_SPL_VAL_OFFS) ++ ++#define PXDCR_CAP_SP_LSCL_OFFS 26 /* Captured Slot Power Limit ++ Scale */ ++#define PXDCR_CAP_SP_LSCL_MASK (0x3 << PXDCR_CAP_SP_LSCL_OFFS) ++ ++/* PCI Express Device Control Status Register */ ++/*PEX_DEV_CTRL_STAT_REG (PXDCSR)*/ ++ ++#define PXDCSR_COR_ERR_REP_EN BIT0 /* Correctable Error Reporting Enable*/ ++#define PXDCSR_NF_ERR_REP_EN BIT1 /* Non-Fatal Error Reporting Enable*/ ++#define PXDCSR_F_ERR_REP_EN BIT2 /* Fatal Error Reporting Enable*/ ++#define PXDCSR_UR_REP_EN BIT3 /* Unsupported Request (UR) ++ Reporting Enable*/ ++#define PXDCSR_EN_RO BIT4 /* Enable Relaxed Ordering*/ ++ ++#define PXDCSR_MAX_PLD_SZ_OFFS 5 /* Maximum Payload Size*/ ++#define PXDCSR_MAX_PLD_SZ_MASK (0x7 << PXDCSR_MAX_PLD_SZ_OFFS) ++#define PXDCSR_MAX_PLD_SZ_128B (0x0 << PXDCSR_MAX_PLD_SZ_OFFS) ++#define PXDCSR_EN_NS BIT11 /* Enable No Snoop*/ ++ ++#define PXDCSR_MAX_RD_RQ_SZ_OFFS 12 /* Maximum Read Request Size*/ ++#define PXDCSR_MAX_RD_RQ_SZ_MASK (0x7 << PXDCSR_MAX_RD_RQ_SZ_OFFS) ++#define PXDCSR_MAX_RD_RQ_SZ_128B (0x0 << PXDCSR_MAX_RD_RQ_SZ_OFFS) ++#define PXDCSR_MAX_RD_RQ_SZ_256B (0x1 << PXDCSR_MAX_RD_RQ_SZ_OFFS) ++#define PXDCSR_MAX_RD_RQ_SZ_512B (0x2 << PXDCSR_MAX_RD_RQ_SZ_OFFS) ++#define PXDCSR_MAX_RD_RQ_SZ_1KB (0x3 << PXDCSR_MAX_RD_RQ_SZ_OFFS) ++#define PXDCSR_MAX_RD_RQ_SZ_2KB (0x4 << PXDCSR_MAX_RD_RQ_SZ_OFFS) ++#define PXDCSR_MAX_RD_RQ_SZ_4KB (0x5 << PXDCSR_MAX_RD_RQ_SZ_OFFS) ++ ++#define PXDCSR_COR_ERR_DET BIT16 /* Correctable Error Detected*/ ++#define PXDCSR_NF_ERR_DET BIT17 /* Non-Fatal Error Detected.*/ ++#define PXDCSR_F_ERR_DET BIT18 /* Fatal Error Detected.*/ ++#define PXDCSR_UR_DET BIT19 /* Unsupported Request Detected */ ++#define PXDCSR_AUX_PWR_DET BIT20 /* Reserved*/ ++ ++#define PXDCSR_TRANS_PEND_OFFS 21 /* Transactions Pending*/ ++#define PXDCSR_TRANS_PEND_MASK BIT21 ++#define PXDCSR_TRANS_PEND_NOT_COMPLETED (0x1 << PXDCSR_TRANS_PEND_OFFS) ++ ++ ++/* PCI Express Link Capabilities Register*/ ++/*PEX_LINK_CAPABILITY_REG (PXLCR)*/ ++ ++#define PXLCR_MAX_LINK_SPD_OFFS 0 /* Maximum Link Speed*/ ++#define PXLCR_MAX_LINK_SPD_MASK (0xf << PXLCR_MAX_LINK_SPD_OFFS) ++ ++#define PXLCR_MAX_LNK_WDTH_OFFS 3 /* Maximum Link Width*/ ++#define PXLCR_MAX_LNK_WDTH_MASK (0x3f << PXLCR_MAX_LNK_WDTH_OFFS) ++ ++#define PXLCR_ASPM_SUP_OFFS 10 /* Active State Link PM Support*/ ++#define PXLCR_ASPM_SUP_MASK (0x3 << PXLCR_ASPM_SUP_OFFS) ++ ++#define PXLCR_L0S_EXT_LAT_OFFS 12 /* L0s Exit Latency*/ ++#define PXLCR_L0S_EXT_LAT_MASK (0x7 << PXLCR_L0S_EXT_LAT_OFFS) ++#define PXLCR_L0S_EXT_LAT_64NS_LESS (0x0 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXLCR_L0S_EXT_LAT_64NS_128NS (0x1 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXLCR_L0S_EXT_LAT_128NS_256NS (0x2 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXLCR_L0S_EXT_LAT_256NS_512NS (0x3 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXLCR_L0S_EXT_LAT_512NS_1US (0x4 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXLCR_L0S_EXT_LAT_1US_2US (0x5 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXLCR_L0S_EXT_LAT_2US_4US (0x6 << PXDCR_EP_L1_ACC_LAT_OFFS) ++ ++#define PXLCR_POR_TNUM_OFFS 24 /* Port Number */ ++#define PXLCR_POR_TNUM_MASK (0xff << PXLCR_POR_TNUM_OFFS) ++ ++/* PCI Express Link Control Status Register */ ++/*PEX_LINK_CTRL_STAT_REG (PXLCSR)*/ ++ ++#define PXLCSR_ASPM_CNT_OFFS 0 /* Active State Link PM Control */ ++#define PXLCSR_ASPM_CNT_MASK (0x3 << PXLCSR_ASPM_CNT_OFFS) ++#define PXLCSR_ASPM_CNT_DISABLED (0x0 << PXLCSR_ASPM_CNT_OFFS) ++#define PXLCSR_ASPM_CNT_L0S_ENT_SUPP (0x1 << PXLCSR_ASPM_CNT_OFFS) ++#define PXLCSR_ASPM_CNT_L1S_ENT_SUPP (0x2 << PXLCSR_ASPM_CNT_OFFS) ++#define PXLCSR_ASPM_CNT_L0S_L1S_ENT_SUPP (0x3 << PXLCSR_ASPM_CNT_OFFS) ++ ++#define PXLCSR_RCB_OFFS 3 /* Read Completion Boundary */ ++#define PXLCSR_RCB_MASK BIT3 ++#define PXLCSR_RCB_64B (0 << PXLCSR_RCB_OFFS) ++#define PXLCSR_RCB_128B (1 << PXLCSR_RCB_OFFS) ++ ++#define PXLCSR_LNK_DIS BIT4 /* Link Disable */ ++#define PXLCSR_RETRN_LNK BIT5 /* Retrain Link */ ++#define PXLCSR_CMN_CLK_CFG BIT6 /* Common Clock Configuration */ ++#define PXLCSR_EXTD_SNC BIT7 /* Extended Sync */ ++ ++#define PXLCSR_LNK_SPD_OFFS 16 /* Link Speed */ ++#define PXLCSR_LNK_SPD_MASK (0xf << PXLCSR_LNK_SPD_OFFS) ++ ++#define PXLCSR_NEG_LNK_WDTH_OFFS 20 /* Negotiated Link Width */ ++#define PXLCSR_NEG_LNK_WDTH_MASK (0x3f << PXLCSR_NEG_LNK_WDTH_OFFS) ++#define PXLCSR_NEG_LNK_WDTH_X1 (0x1 << PXLCSR_NEG_LNK_WDTH_OFFS) ++ ++#define PXLCSR_LNK_TRN BIT27 /* Link Training */ ++ ++#define PXLCSR_SLT_CLK_CFG_OFFS 28 /* Slot Clock Configuration */ ++#define PXLCSR_SLT_CLK_CFG_MASK BIT28 ++#define PXLCSR_SLT_CLK_CFG_INDPNT (0x0 << PXLCSR_SLT_CLK_CFG_OFFS) ++#define PXLCSR_SLT_CLK_CFG_REF (0x1 << PXLCSR_SLT_CLK_CFG_OFFS) ++ ++/* PCI Express Advanced Error Report Header Register */ ++/*PEX_ADV_ERR_RPRT_HDR_TRGT_REG (PXAERHTR)*/ ++ ++/* PCI Express Uncorrectable Error Status Register*/ ++/*PEX_UNCORRECT_ERR_STAT_REG (PXUESR)*/ ++ ++/* PCI Express Uncorrectable Error Mask Register */ ++/*PEX_UNCORRECT_ERR_MASK_REG (PXUEMR)*/ ++ ++/* PCI Express Uncorrectable Error Severity Register */ ++/*PEX_UNCORRECT_ERR_SERVITY_REG (PXUESR)*/ ++ ++/* PCI Express Correctable Error Status Register */ ++/*PEX_CORRECT_ERR_STAT_REG (PXCESR)*/ ++ ++/* PCI Express Correctable Error Mask Register */ ++/*PEX_CORRECT_ERR_MASK_REG (PXCEMR)*/ ++ ++/* PCI Express Advanced Error Capability and Control Register*/ ++/*PEX_ADV_ERR_CAPABILITY_CTRL_REG (PXAECCR)*/ ++ ++/* PCI Express Header Log First DWORD Register*/ ++/*PEX_HDR_LOG_FIRST_DWORD_REG (PXHLFDR)*/ ++ ++/* PCI Express Header Log Second DWORD Register*/ ++/*PEX_HDR_LOG_SECOND_DWORD_REG (PXHLSDR)*/ ++ ++/* PCI Express Header Log Third DWORD Register*/ ++/*PEX_HDR_LOG_THIRD_DWORD_REG (PXHLTDR)*/ ++ ++/* PCI Express Header Log Fourth DWORD Register*/ ++/*PEX_HDR_LOG_FOURTH_DWORD_REG (PXHLFDR)*/ ++ ++#ifdef __cplusplus ++} ++#endif /* __cplusplus */ ++ ++#endif /* #ifndef __INCPEXREGSH */ ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,313 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#include "mvPex.h" ++ ++//#define MV_DEBUG ++/* defines */ ++#ifdef MV_DEBUG ++ #define DB(x) x ++#else ++ #define DB(x) ++#endif ++ ++/* locals */ ++typedef struct ++{ ++ MV_U32 data; ++ MV_U32 mask; ++}PEX_HEADER_DATA; ++ ++/* local function forwad decleration */ ++MV_U32 mvPexHwConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, ++ MV_U32 regOff); ++MV_STATUS mvPexHwConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func, MV_U32 regOff, MV_U32 data); ++void resetPexConfig(MV_U32 pexIf, MV_U32 bus, MV_U32 dev); ++ ++ ++PEX_HEADER_DATA configHdr[16] = ++{ ++{0x888811ab, 0x00000000}, /*[device ID, vendor ID] */ ++{0x00100007, 0x0000ffff}, /*[status register, command register] */ ++{0x0604000e, 0x00000000}, /*[programming interface, sub class code, class code, revision ID] */ ++{0x00010008, 0x00000000}, /*[BIST, header type, latency time, cache line] */ ++{0x00000000, 0x00000000}, /*[base address 0] */ ++{0x00000000, 0x00000000}, /*[base address 1] */ ++{0x00000000, 0x00ffffff}, /*[secondary latency timersubordinate bus number, secondary bus number, primary bus number] */ ++{0x0000f101, 0x00000000}, /*[secondary status ,IO limit, IO base] */ ++{0x9ff0a000, 0x00000000}, /*[memory limit, memory base] */ ++{0x0001fff1, 0x00000000}, /*[prefetch memory limit, prefetch memory base] */ ++{0xffffffff, 0x00000000}, /*[prefetch memory base upper] */ ++{0x00000000, 0x00000000}, /*[prefetch memory limit upper] */ ++{0xeffff000, 0x00000000}, /*[IO limit upper 16 bits, IO base upper 16 bits] */ ++{0x00000000, 0x00000000}, /*[reserved, capability pointer] */ ++{0x00000000, 0x00000000}, /*[expansion ROM base address] */ ++{0x00000000, 0x000000FF}, /*[bridge control, interrupt pin, interrupt line] */ ++}; ++ ++ ++#define HEADER_WRITE(data, offset) configHdr[offset/4].data = ((configHdr[offset/4].data & ~configHdr[offset/4].mask) | \ ++ (data & configHdr[offset/4].mask)) ++#define HEADER_READ(offset) configHdr[offset/4].data ++ ++/******************************************************************************* ++* mvVrtBrgPexInit - Initialize PEX interfaces ++* ++* DESCRIPTION: ++* ++* This function is responsible of intialization of the Pex Interface , It ++* configure the Pex Bars and Windows in the following manner: ++* ++* Assumptions : ++* Bar0 is always internal registers bar ++* Bar1 is always the DRAM bar ++* Bar2 is always the Device bar ++* ++* 1) Sets the Internal registers bar base by obtaining the base from ++* the CPU Interface ++* 2) Sets the DRAM bar base and size by getting the base and size from ++* the CPU Interface when the size is the sum of all enabled DRAM ++* chip selects and the base is the base of CS0 . ++* 3) Sets the Device bar base and size by getting these values from the ++* CPU Interface when the base is the base of the lowest base of the ++* Device chip selects, and the ++* ++* ++* INPUT: ++* ++* pexIf - PEX interface number. ++* ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_OK if function success otherwise MV_ERROR or MV_BAD_PARAM ++* ++*******************************************************************************/ ++MV_STATUS mvPexVrtBrgInit(MV_U32 pexIf) ++{ ++ /* reset PEX tree to recover previous U-boot/Boot configurations */ ++ MV_U32 localBus = mvPexLocalBusNumGet(pexIf); ++ ++ ++ resetPexConfig(pexIf, localBus, 1); ++ return MV_OK; ++} ++ ++ ++MV_U32 mvPexVrtBrgConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, ++ MV_U32 regOff) ++{ ++ ++ MV_U32 localBus = mvPexLocalBusNumGet(pexIf); ++ MV_U32 localDev = mvPexLocalDevNumGet(pexIf); ++ MV_U32 val; ++ if(bus == localBus) ++ { ++ if(dev > 1) ++ { ++/* on the local device allow only device #0 & #1 */ ++ return 0xffffffff; ++ } ++ else ++ if (dev == localDev) ++ { ++ /* read the memory controller registers */ ++ return mvPexHwConfigRead (pexIf, bus, dev, func, regOff); ++ } ++ else ++ { ++ /* access the virtual brg header */ ++ return HEADER_READ(regOff); ++ } ++ } ++ else ++ if(bus == (localBus + 1)) ++ { ++ /* access the device behind the virtual bridge */ ++ if((dev == localDev) || (dev > 1)) ++ { ++ return 0xffffffff; ++ } ++ else ++ { ++ /* access the device behind the virtual bridge, in this case ++ * change the bus number to the local bus number in order to ++ * generate type 0 config cycle ++ */ ++ mvPexLocalBusNumSet(pexIf, bus); ++ mvPexLocalDevNumSet(pexIf, 1); ++ val = mvPexHwConfigRead (pexIf, bus, 0, func, regOff); ++ mvPexLocalBusNumSet(pexIf, localBus); ++ mvPexLocalDevNumSet(pexIf, localDev); ++ return val; ++ } ++ } ++ /* for all other devices use the HW function to get the ++ * requested registers ++ */ ++ mvPexLocalDevNumSet(pexIf, 1); ++ val = mvPexHwConfigRead (pexIf, bus, dev, func, regOff); ++ mvPexLocalDevNumSet(pexIf, localDev); ++ return val; ++} ++ ++ ++MV_STATUS mvPexVrtBrgConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func, MV_U32 regOff, MV_U32 data) ++{ ++ MV_U32 localBus = mvPexLocalBusNumGet(pexIf); ++ MV_U32 localDev = mvPexLocalDevNumGet(pexIf); ++ MV_STATUS status; ++ ++ if(bus == localBus) ++ { ++ if(dev > 1) ++ { ++ /* on the local device allow only device #0 & #1 */ ++ return MV_ERROR; ++ } ++ else ++ if (dev == localDev) ++ { ++ /* read the memory controller registers */ ++ return mvPexHwConfigWrite (pexIf, bus, dev, func, regOff, data); ++ } ++ else ++ { ++ /* access the virtual brg header */ ++ HEADER_WRITE(data, regOff); ++ return MV_OK; ++ } ++ } ++ else ++ if(bus == (localBus + 1)) ++ { ++ /* access the device behind the virtual bridge */ ++ if((dev == localDev) || (dev > 1)) ++ { ++ return MV_ERROR; ++ } ++ else ++ { ++ /* access the device behind the virtual bridge, in this case ++ * change the bus number to the local bus number in order to ++ * generate type 0 config cycle ++ */ ++ //return mvPexHwConfigWrite (pexIf, localBus, dev, func, regOff, data); ++ mvPexLocalBusNumSet(pexIf, bus); ++ mvPexLocalDevNumSet(pexIf, 1); ++ status = mvPexHwConfigWrite (pexIf, bus, 0, func, regOff, data); ++ mvPexLocalBusNumSet(pexIf, localBus); ++ mvPexLocalDevNumSet(pexIf, localDev); ++ return status; ++ ++ } ++ } ++ /* for all other devices use the HW function to get the ++ * requested registers ++ */ ++ mvPexLocalDevNumSet(pexIf, 1); ++ status = mvPexHwConfigWrite (pexIf, bus, dev, func, regOff, data); ++ mvPexLocalDevNumSet(pexIf, localDev); ++ return status; ++} ++ ++ ++ ++ ++void resetPexConfig(MV_U32 pexIf, MV_U32 bus, MV_U32 dev) ++{ ++ MV_U32 tData; ++ MV_U32 i; ++ ++ /* restore the PEX configuration to initialization state */ ++ /* in case PEX P2P call recursive and reset config */ ++ tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x0); ++ if(tData != 0xffffffff) ++ { ++ /* agent had been found - check whether P2P */ ++ tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x8); ++ if((tData & 0xffff0000) == 0x06040000) ++ {/* P2P */ ++ /* get the sec bus and the subordinate */ ++ MV_U32 secBus; ++ tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x18); ++ secBus = ((tData >> 8) & 0xff); ++ /* now scan on sec bus */ ++ for(i = 0;i < 0xff;i++) ++ { ++ resetPexConfig(pexIf, secBus, i); ++ } ++ /* now reset this device */ ++ DB(mvOsPrintf("Reset bus %d dev %d\n", bus, dev)); ++ mvPexHwConfigWrite(pexIf, bus, dev, 0x0, 0x18, 0x0); ++ DB(mvOsPrintf("Reset bus %d dev %d\n", bus, dev)); ++ } ++ } ++} ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,82 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCVRTBRGPEXH ++#define __INCVRTBRGPEXH ++ ++ ++/* Global Functions prototypes */ ++/* mvPexInit - Initialize PEX interfaces*/ ++MV_STATUS mvPexVrtBrgInit(MV_U32 pexIf); ++ ++/* mvPexConfigRead - Read from configuration space */ ++MV_U32 mvPexVrtBrgConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func,MV_U32 regOff); ++ ++/* mvPexConfigWrite - Write to configuration space */ ++MV_STATUS mvPexVrtBrgConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func, MV_U32 regOff, MV_U32 data); ++ ++ ++#endif /* #ifndef __INCPEXH */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvCompVer.txt linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvCompVer.txt +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvCompVer.txt 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvCompVer.txt 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,4 @@ ++Global HAL Version: FEROCEON_HAL_3_1_7 ++Unit HAL Version: 3.1.3 ++Description: This component includes an implementation of the unit HAL drivers ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,1522 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++#include "mvOs.h" ++#include "sflash/mvSFlash.h" ++#include "sflash/mvSFlashSpec.h" ++#include "spi/mvSpi.h" ++#include "spi/mvSpiCmnd.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++ ++/*#define MV_DEBUG*/ ++#ifdef MV_DEBUG ++#define DB(x) x ++#else ++#define DB(x) ++#endif ++ ++/* Globals */ ++static MV_SFLASH_DEVICE_PARAMS sflash[] = { ++ /* ST M25P32 SPI flash, 4MB, 64 sectors of 64K each */ ++ { ++ MV_M25P_WREN_CMND_OPCD, ++ MV_M25P_WRDI_CMND_OPCD, ++ MV_M25P_RDID_CMND_OPCD, ++ MV_M25P_RDSR_CMND_OPCD, ++ MV_M25P_WRSR_CMND_OPCD, ++ MV_M25P_READ_CMND_OPCD, ++ MV_M25P_FAST_RD_CMND_OPCD, ++ MV_M25P_PP_CMND_OPCD, ++ MV_M25P_SE_CMND_OPCD, ++ MV_M25P_BE_CMND_OPCD, ++ MV_M25P_RES_CMND_OPCD, ++ MV_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */ ++ MV_M25P32_SECTOR_SIZE, ++ MV_M25P32_SECTOR_NUMBER, ++ MV_M25P_PAGE_SIZE, ++ "ST M25P32", ++ MV_M25PXXX_ST_MANF_ID, ++ MV_M25P32_DEVICE_ID, ++ MV_M25P32_MAX_SPI_FREQ, ++ MV_M25P32_MAX_FAST_SPI_FREQ, ++ MV_M25P32_FAST_READ_DUMMY_BYTES ++ }, ++ /* ST M25P64 SPI flash, 8MB, 128 sectors of 64K each */ ++ { ++ MV_M25P_WREN_CMND_OPCD, ++ MV_M25P_WRDI_CMND_OPCD, ++ MV_M25P_RDID_CMND_OPCD, ++ MV_M25P_RDSR_CMND_OPCD, ++ MV_M25P_WRSR_CMND_OPCD, ++ MV_M25P_READ_CMND_OPCD, ++ MV_M25P_FAST_RD_CMND_OPCD, ++ MV_M25P_PP_CMND_OPCD, ++ MV_M25P_SE_CMND_OPCD, ++ MV_M25P_BE_CMND_OPCD, ++ MV_M25P_RES_CMND_OPCD, ++ MV_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */ ++ MV_M25P64_SECTOR_SIZE, ++ MV_M25P64_SECTOR_NUMBER, ++ MV_M25P_PAGE_SIZE, ++ "ST M25P64", ++ MV_M25PXXX_ST_MANF_ID, ++ MV_M25P64_DEVICE_ID, ++ MV_M25P64_MAX_SPI_FREQ, ++ MV_M25P64_MAX_FAST_SPI_FREQ, ++ MV_M25P64_FAST_READ_DUMMY_BYTES ++ }, ++ /* ST M25P128 SPI flash, 16MB, 64 sectors of 256K each */ ++ { ++ MV_M25P_WREN_CMND_OPCD, ++ MV_M25P_WRDI_CMND_OPCD, ++ MV_M25P_RDID_CMND_OPCD, ++ MV_M25P_RDSR_CMND_OPCD, ++ MV_M25P_WRSR_CMND_OPCD, ++ MV_M25P_READ_CMND_OPCD, ++ MV_M25P_FAST_RD_CMND_OPCD, ++ MV_M25P_PP_CMND_OPCD, ++ MV_M25P_SE_CMND_OPCD, ++ MV_M25P_BE_CMND_OPCD, ++ MV_M25P_RES_CMND_OPCD, ++ MV_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */ ++ MV_M25P128_SECTOR_SIZE, ++ MV_M25P128_SECTOR_NUMBER, ++ MV_M25P_PAGE_SIZE, ++ "ST M25P128", ++ MV_M25PXXX_ST_MANF_ID, ++ MV_M25P128_DEVICE_ID, ++ MV_M25P128_MAX_SPI_FREQ, ++ MV_M25P128_MAX_FAST_SPI_FREQ, ++ MV_M25P128_FAST_READ_DUMMY_BYTES ++ }, ++ /* Macronix MXIC MX25L6405 SPI flash, 8MB, 128 sectors of 64K each */ ++ { ++ MV_MX25L_WREN_CMND_OPCD, ++ MV_MX25L_WRDI_CMND_OPCD, ++ MV_MX25L_RDID_CMND_OPCD, ++ MV_MX25L_RDSR_CMND_OPCD, ++ MV_MX25L_WRSR_CMND_OPCD, ++ MV_MX25L_READ_CMND_OPCD, ++ MV_MX25L_FAST_RD_CMND_OPCD, ++ MV_MX25L_PP_CMND_OPCD, ++ MV_MX25L_SE_CMND_OPCD, ++ MV_MX25L_BE_CMND_OPCD, ++ MV_MX25L_RES_CMND_OPCD, ++ MV_MX25L_DP_CMND_OPCD, ++ MV_MX25L6405_SECTOR_SIZE, ++ MV_MX25L6405_SECTOR_NUMBER, ++ MV_MXIC_PAGE_SIZE, ++ "MXIC MX25L6405", ++ MV_MXIC_MANF_ID, ++ MV_MX25L6405_DEVICE_ID, ++ MV_MX25L6405_MAX_SPI_FREQ, ++ MV_MX25L6405_MAX_FAST_SPI_FREQ, ++ MV_MX25L6405_FAST_READ_DUMMY_BYTES ++ }, ++ /* SPANSION S25FL128P SPI flash, 16MB, 64 sectors of 256K each */ ++ { ++ MV_S25FL_WREN_CMND_OPCD, ++ MV_S25FL_WRDI_CMND_OPCD, ++ MV_S25FL_RDID_CMND_OPCD, ++ MV_S25FL_RDSR_CMND_OPCD, ++ MV_S25FL_WRSR_CMND_OPCD, ++ MV_S25FL_READ_CMND_OPCD, ++ MV_S25FL_FAST_RD_CMND_OPCD, ++ MV_S25FL_PP_CMND_OPCD, ++ MV_S25FL_SE_CMND_OPCD, ++ MV_S25FL_BE_CMND_OPCD, ++ MV_S25FL_RES_CMND_OPCD, ++ MV_S25FL_DP_CMND_OPCD, ++ MV_S25FL128_SECTOR_SIZE, ++ MV_S25FL128_SECTOR_NUMBER, ++ MV_S25FL_PAGE_SIZE, ++ "SPANSION S25FL128", ++ MV_SPANSION_MANF_ID, ++ MV_S25FL128_DEVICE_ID, ++ MV_S25FL128_MAX_SPI_FREQ, ++ MV_M25P128_MAX_FAST_SPI_FREQ, ++ MV_M25P128_FAST_READ_DUMMY_BYTES ++ } ++}; ++ ++/* Static Functions */ ++static MV_STATUS mvWriteEnable (MV_SFLASH_INFO * pFlinfo); ++static MV_STATUS mvStatusRegGet (MV_SFLASH_INFO * pFlinfo, MV_U8 * pStatReg); ++static MV_STATUS mvStatusRegSet (MV_SFLASH_INFO * pFlinfo, MV_U8 sr); ++static MV_STATUS mvWaitOnWipClear(MV_SFLASH_INFO * pFlinfo); ++static MV_STATUS mvSFlashPageWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, \ ++ MV_U8* pPageBuff, MV_U32 buffSize); ++static MV_STATUS mvSFlashWithDefaultsIdGet (MV_SFLASH_INFO * pFlinfo, \ ++ MV_U8* manId, MV_U16* devId); ++ ++/******************************************************************************* ++* mvWriteEnable - serialize the write enable sequence ++* ++* DESCRIPTION: ++* transmit the sequence for write enable ++* ++********************************************************************************/ ++static MV_STATUS mvWriteEnable(MV_SFLASH_INFO * pFlinfo) ++{ ++ MV_U8 cmd[MV_SFLASH_WREN_CMND_LENGTH]; ++ ++ ++ cmd[0] = sflash[pFlinfo->index].opcdWREN; ++ ++ return mvSpiWriteThenRead(cmd, MV_SFLASH_WREN_CMND_LENGTH, NULL, 0, 0); ++} ++ ++/******************************************************************************* ++* mvStatusRegGet - Retrieve the value of the status register ++* ++* DESCRIPTION: ++* perform the RDSR sequence to get the 8bit status register ++* ++********************************************************************************/ ++static MV_STATUS mvStatusRegGet(MV_SFLASH_INFO * pFlinfo, MV_U8 * pStatReg) ++{ ++ MV_STATUS ret; ++ MV_U8 cmd[MV_SFLASH_RDSR_CMND_LENGTH]; ++ MV_U8 sr[MV_SFLASH_RDSR_REPLY_LENGTH]; ++ ++ ++ ++ ++ cmd[0] = sflash[pFlinfo->index].opcdRDSR; ++ ++ if ((ret = mvSpiWriteThenRead(cmd, MV_SFLASH_RDSR_CMND_LENGTH, sr, ++ MV_SFLASH_RDSR_REPLY_LENGTH,0)) != MV_OK) ++ return ret; ++ ++ *pStatReg = sr[0]; ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvWaitOnWipClear - Block waiting for the WIP (write in progress) to be cleared ++* ++* DESCRIPTION: ++* Block waiting for the WIP (write in progress) to be cleared ++* ++********************************************************************************/ ++static MV_STATUS mvWaitOnWipClear(MV_SFLASH_INFO * pFlinfo) ++{ ++ MV_STATUS ret; ++ MV_U32 i; ++ MV_U8 stat; ++ ++ for (i=0; iindex].opcdWRSR; ++ cmd[1] = sr; ++ ++ if ((ret = mvSpiWriteThenRead(cmd, MV_SFLASH_WRSR_CMND_LENGTH, NULL, 0, 0)) != MV_OK) ++ return ret; ++ ++ if ((ret = mvWaitOnWipClear(pFlinfo)) != MV_OK) ++ return ret; ++ ++ mvOsDelay(1); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvSFlashPageWr - Write up to 256 Bytes in the same page ++* ++* DESCRIPTION: ++* Write a buffer up to the page size in length provided that the whole address ++* range is within the same page (alligned to page bounderies) ++* ++*******************************************************************************/ ++static MV_STATUS mvSFlashPageWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, ++ MV_U8* pPageBuff, MV_U32 buffSize) ++{ ++ MV_STATUS ret; ++ MV_U8 cmd[MV_SFLASH_PP_CMND_LENGTH]; ++ ++ ++ /* Protection - check if the model was detected */ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ { ++ DB(mvOsPrintf("%s WARNING: Invalid parameter device index!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ /* check that we do not cross the page bounderies */ ++ if (((offset & (sflash[pFlinfo->index].pageSize - 1)) + buffSize) > ++ sflash[pFlinfo->index].pageSize) ++ { ++ DB(mvOsPrintf("%s WARNING: Page allignment problem!\n", __FUNCTION__);) ++ return MV_OUT_OF_RANGE; ++ } ++ ++ /* Issue the Write enable command prior the page program command */ ++ if ((ret = mvWriteEnable(pFlinfo)) != MV_OK) ++ return ret; ++ ++ cmd[0] = sflash[pFlinfo->index].opcdPP; ++ cmd[1] = ((offset >> 16) & 0xFF); ++ cmd[2] = ((offset >> 8) & 0xFF); ++ cmd[3] = (offset & 0xFF); ++ ++ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_PP_CMND_LENGTH, pPageBuff, buffSize)) != MV_OK) ++ return ret; ++ ++ if ((ret = mvWaitOnWipClear(pFlinfo)) != MV_OK) ++ return ret; ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvSFlashWithDefaultsIdGet - Try to read the manufacturer and Device IDs from ++* the device using the default RDID opcode and the default WREN opcode. ++* ++* DESCRIPTION: ++* This is used to detect a generic device that uses the default opcodes ++* for the WREN and RDID. ++* ++********************************************************************************/ ++static MV_STATUS mvSFlashWithDefaultsIdGet (MV_SFLASH_INFO * pFlinfo, MV_U8* manId, MV_U16* devId) ++{ ++ MV_STATUS ret; ++ MV_U8 cmdRDID[MV_SFLASH_RDID_CMND_LENGTH]; ++ MV_U8 id[MV_SFLASH_RDID_REPLY_LENGTH]; ++ ++ ++ ++ /* Use the default RDID opcode to read the IDs */ ++ cmdRDID[0] = MV_SFLASH_DEFAULT_RDID_OPCD; /* unknown model try default */ ++ if ((ret = mvSpiWriteThenRead(cmdRDID, MV_SFLASH_RDID_CMND_LENGTH, id, MV_SFLASH_RDID_REPLY_LENGTH, 0)) != MV_OK) ++ return ret; ++ ++ *manId = id[0]; ++ *devId = 0; ++ *devId |= (id[1] << 8); ++ *devId |= id[2]; ++ ++ return MV_OK; ++} ++ ++/* ++##################################################################################### ++##################################################################################### ++*/ ++ ++/******************************************************************************* ++* mvSFlashInit - Initialize the serial flash device ++* ++* DESCRIPTION: ++* Perform the neccessary initialization and configuration ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* pFlinfo->baseAddr: base address in fast mode. ++* pFlinfo->index: Index of the flash in the sflash tabel. If the SPI ++* flash device does not support read Id command with ++* the standard opcode, then the user should supply this ++* as an input to skip the autodetection process!!!! ++* ++* OUTPUT: ++* pFlinfo: pointer to the Flash information structure after detection ++* pFlinfo->manufacturerId: Manufacturer ID ++* pFlinfo->deviceId: Device ID ++* pFlinfo->sectorSize: size of the sector (all sectors are the same). ++* pFlinfo->sectorNumber: number of sectors. ++* pFlinfo->pageSize: size of the page. ++* pFlinfo->index: Index of the detected flash in the sflash tabel ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSFlashInit (MV_SFLASH_INFO * pFlinfo) ++{ ++ MV_STATUS ret; ++ MV_U8 manf; ++ MV_U16 dev; ++ MV_U32 indx; ++ MV_BOOL detectFlag = MV_FALSE; ++ ++ /* check for NULL pointer */ ++ if (pFlinfo == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Initialize the SPI interface with low frequency to make sure that the read ID succeeds */ ++ if ((ret = mvSpiInit(MV_SFLASH_BASIC_SPI_FREQ)) != MV_OK) ++ { ++ mvOsPrintf("%s ERROR: Failed to initialize the SPI interface!\n", __FUNCTION__); ++ return ret; ++ } ++ ++ /* First try to read the Manufacturer and Device IDs */ ++ if ((ret = mvSFlashIdGet(pFlinfo, &manf, &dev)) != MV_OK) ++ { ++ mvOsPrintf("%s ERROR: Failed to get the SFlash ID!\n", __FUNCTION__); ++ return ret; ++ } ++ ++ /* loop over the whole table and look for the appropriate SFLASH */ ++ for (indx=0; indxmanufacturerId = manf; ++ pFlinfo->deviceId = dev; ++ pFlinfo->index = indx; ++ detectFlag = MV_TRUE; ++ } ++ } ++ ++ if(!detectFlag) ++ { ++ mvOsPrintf("%s ERROR: Unknown SPI flash device!\n", __FUNCTION__); ++ return MV_FAIL; ++ } ++ ++ /* fill the info based on the model detected */ ++ pFlinfo->sectorSize = sflash[pFlinfo->index].sectorSize; ++ pFlinfo->sectorNumber = sflash[pFlinfo->index].sectorNumber; ++ pFlinfo->pageSize = sflash[pFlinfo->index].pageSize; ++ ++ /* Set the SPI frequency to the MAX allowed for the device for best performance */ ++ if ((ret = mvSpiBaudRateSet(sflash[pFlinfo->index].spiMaxFreq)) != MV_OK) ++ { ++ mvOsPrintf("%s ERROR: Failed to set the SPI frequency!\n", __FUNCTION__); ++ return ret; ++ } ++ ++ /* As default lock the SR */ ++ if ((ret = mvSFlashStatRegLock(pFlinfo, MV_TRUE)) != MV_OK) ++ return ret; ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvSFlashSectorErase - Erasse a single sector of the serial flash ++* ++* DESCRIPTION: ++* Issue the erase sector command and address ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* secNumber: sector Number to erase (0 -> (sectorNumber-1)) ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSFlashSectorErase (MV_SFLASH_INFO * pFlinfo, MV_U32 secNumber) ++{ ++ MV_STATUS ret; ++ MV_U8 cmd[MV_SFLASH_SE_CMND_LENGTH]; ++ ++ MV_U32 secAddr = (secNumber * pFlinfo->sectorSize); ++#if 0 ++ MV_U32 i; ++ MV_U32 * pW = (MV_U32*) (secAddr + pFlinfo->baseAddr); ++ MV_U32 erasedWord = 0xFFFFFFFF; ++ MV_U32 wordsPerSector = (pFlinfo->sectorSize / sizeof(MV_U32)); ++ MV_BOOL eraseNeeded = MV_FALSE; ++#endif ++ /* check for NULL pointer */ ++ if (pFlinfo == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Protection - check if the model was detected */ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ /* check that the sector number is valid */ ++ if (secNumber >= pFlinfo->sectorNumber) ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter sector number!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ /* we don't want to access SPI in direct mode from in-direct API, ++ becasue of timing issue between CS asserts. */ ++#if 0 ++ /* First compare to FF and check if erase is needed */ ++ for (i=0; iindex].opcdSE; ++ cmd[1] = ((secAddr >> 16) & 0xFF); ++ cmd[2] = ((secAddr >> 8) & 0xFF); ++ cmd[3] = (secAddr & 0xFF); ++ ++ /* Issue the Write enable command prior the sector erase command */ ++ if ((ret = mvWriteEnable(pFlinfo)) != MV_OK) ++ return ret; ++ ++ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_SE_CMND_LENGTH, NULL, 0)) != MV_OK) ++ return ret; ++ ++ if ((ret = mvWaitOnWipClear(pFlinfo)) != MV_OK) ++ return ret; ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvSFlashChipErase - Erasse the whole serial flash ++* ++* DESCRIPTION: ++* Issue the bulk (chip) erase command ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSFlashChipErase (MV_SFLASH_INFO * pFlinfo) ++{ ++ MV_STATUS ret; ++ MV_U8 cmd[MV_SFLASH_BE_CMND_LENGTH]; ++ ++ ++ /* check for NULL pointer */ ++ if (pFlinfo == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Protection - check if the model was detected */ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ cmd[0] = sflash[pFlinfo->index].opcdBE; ++ ++ /* Issue the Write enable command prior the Bulk erase command */ ++ if ((ret = mvWriteEnable(pFlinfo)) != MV_OK) ++ return ret; ++ ++ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_BE_CMND_LENGTH, NULL, 0)) != MV_OK) ++ return ret; ++ ++ if ((ret = mvWaitOnChipEraseDone(pFlinfo)) != MV_OK) ++ return ret; ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvSFlashBlockRd - Read from the serial flash ++* ++* DESCRIPTION: ++* Issue the read command and address then perfom the needed read ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* offset: byte offset with the flash to start reading from ++* pReadBuff: pointer to the buffer to read the data in ++* buffSize: size of the buffer to read. ++* ++* OUTPUT: ++* pReadBuff: pointer to the buffer containing the read data ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSFlashBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, ++ MV_U8* pReadBuff, MV_U32 buffSize) ++{ ++ MV_U8 cmd[MV_SFLASH_READ_CMND_LENGTH]; ++ ++ ++ /* check for NULL pointer */ ++ if ((pFlinfo == NULL) || (pReadBuff == NULL)) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Protection - check if the model was detected */ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ cmd[0] = sflash[pFlinfo->index].opcdREAD; ++ cmd[1] = ((offset >> 16) & 0xFF); ++ cmd[2] = ((offset >> 8) & 0xFF); ++ cmd[3] = (offset & 0xFF); ++ ++ return mvSpiWriteThenRead(cmd, MV_SFLASH_READ_CMND_LENGTH, pReadBuff, buffSize, 0); ++} ++ ++/******************************************************************************* ++* mvSFlashFastBlockRd - Fast read from the serial flash ++* ++* DESCRIPTION: ++* Issue the fast read command and address then perfom the needed read ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* offset: byte offset with the flash to start reading from ++* pReadBuff: pointer to the buffer to read the data in ++* buffSize: size of the buffer to read. ++* ++* OUTPUT: ++* pReadBuff: pointer to the buffer containing the read data ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSFlashFastBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, ++ MV_U8* pReadBuff, MV_U32 buffSize) ++{ ++ MV_U8 cmd[MV_SFLASH_READ_CMND_LENGTH]; ++ MV_STATUS ret; ++ ++ /* check for NULL pointer */ ++ if ((pFlinfo == NULL) || (pReadBuff == NULL)) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Protection - check if the model was detected */ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ /* Set the SPI frequency to the MAX allowed for fast-read operations */ ++ mvOsPrintf("Setting freq to %d.\n",sflash[pFlinfo->index].spiMaxFastFreq); ++ if ((ret = mvSpiBaudRateSet(sflash[pFlinfo->index].spiMaxFastFreq)) != MV_OK) ++ { ++ mvOsPrintf("%s ERROR: Failed to set the SPI fast frequency!\n", __FUNCTION__); ++ return ret; ++ } ++ ++ cmd[0] = sflash[pFlinfo->index].opcdFSTRD; ++ cmd[1] = ((offset >> 16) & 0xFF); ++ cmd[2] = ((offset >> 8) & 0xFF); ++ cmd[3] = (offset & 0xFF); ++ ++ ++ ret = mvSpiWriteThenRead(cmd, MV_SFLASH_READ_CMND_LENGTH, pReadBuff, buffSize, ++ sflash[pFlinfo->index].spiFastRdDummyBytes); ++ ++ /* Reset the SPI frequency to the MAX allowed for the device for best performance */ ++ if ((ret = mvSpiBaudRateSet(sflash[pFlinfo->index].spiMaxFreq)) != MV_OK) ++ { ++ mvOsPrintf("%s ERROR: Failed to set the SPI frequency!\n", __FUNCTION__); ++ return ret; ++ } ++ ++ return ret; ++} ++ ++ ++/******************************************************************************* ++* mvSFlashBlockWr - Write a buffer with any size ++* ++* DESCRIPTION: ++* write regardless of the page boundaries and size limit per Page ++* program command ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* offset: byte offset within the flash region ++* pWriteBuff: pointer to the buffer holding the data to program ++* buffSize: size of the buffer to write ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSFlashBlockWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, ++ MV_U8* pWriteBuff, MV_U32 buffSize) ++{ ++ MV_STATUS ret; ++ MV_U32 data2write = buffSize; ++ MV_U32 preAllOffset = (offset & MV_SFLASH_PAGE_ALLIGN_MASK(MV_M25P_PAGE_SIZE)); ++ MV_U32 preAllSz = (preAllOffset ? (MV_M25P_PAGE_SIZE - preAllOffset) : 0); ++ MV_U32 writeOffset = offset; ++ ++ /* check for NULL pointer */ ++#ifndef CONFIG_MARVELL ++ if(NULL == pWriteBuff) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++#endif ++ ++ if (pFlinfo == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Protection - check if the model was detected */ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ /* check that the buffer size does not exceed the flash size */ ++ if ((offset + buffSize) > mvSFlashSizeGet(pFlinfo)) ++ { ++ DB(mvOsPrintf("%s WARNING: Write exceeds flash size!\n", __FUNCTION__);) ++ return MV_OUT_OF_RANGE; ++ } ++ ++ /* check if the total block size is less than the first chunk remainder */ ++ if (data2write < preAllSz) ++ preAllSz = data2write; ++ ++ /* check if programing does not start at a 64byte alligned offset */ ++ if (preAllSz) ++ { ++ if ((ret = mvSFlashPageWr(pFlinfo, writeOffset, pWriteBuff, preAllSz)) != MV_OK) ++ return ret; ++ ++ /* increment pointers and counters */ ++ writeOffset += preAllSz; ++ data2write -= preAllSz; ++ pWriteBuff += preAllSz; ++ } ++ ++ /* program the data that fits in complete page chunks */ ++ while (data2write >= sflash[pFlinfo->index].pageSize) ++ { ++ if ((ret = mvSFlashPageWr(pFlinfo, writeOffset, pWriteBuff, sflash[pFlinfo->index].pageSize)) != MV_OK) ++ return ret; ++ ++ /* increment pointers and counters */ ++ writeOffset += sflash[pFlinfo->index].pageSize; ++ data2write -= sflash[pFlinfo->index].pageSize; ++ pWriteBuff += sflash[pFlinfo->index].pageSize; ++ } ++ ++ /* program the last partial chunk */ ++ if (data2write) ++ { ++ if ((ret = mvSFlashPageWr(pFlinfo, writeOffset, pWriteBuff, data2write)) != MV_OK) ++ return ret; ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvSFlashIdGet - Get the manufacturer and device IDs. ++* ++* DESCRIPTION: ++* Get the Manufacturer and device IDs from the serial flash through ++* writing the RDID command then reading 3 bytes of data. In case that ++* this command was called for the first time in order to detect the ++* manufacturer and device IDs, then the default RDID opcode will be used ++* unless the device index is indicated by the user (in case the SPI flash ++* does not use the default RDID opcode). ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* pManId: pointer to the 8bit variable to hold the manufacturing ID ++* pDevId: pointer to the 16bit variable to hold the device ID ++* ++* OUTPUT: ++* pManId: pointer to the 8bit variable holding the manufacturing ID ++* pDevId: pointer to the 16bit variable holding the device ID ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSFlashIdGet (MV_SFLASH_INFO * pFlinfo, MV_U8* pManId, MV_U16* pDevId) ++{ ++ MV_STATUS ret; ++ MV_U8 cmd[MV_SFLASH_RDID_CMND_LENGTH]; ++ MV_U8 id[MV_SFLASH_RDID_REPLY_LENGTH]; ++ ++ ++ ++ /* check for NULL pointer */ ++ if ((pFlinfo == NULL) || (pManId == NULL) || (pDevId == NULL)) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ return mvSFlashWithDefaultsIdGet(pFlinfo, pManId, pDevId); ++ else ++ cmd[0] = sflash[pFlinfo->index].opcdRDID; ++ ++ if ((ret = mvSpiWriteThenRead(cmd, MV_SFLASH_RDID_CMND_LENGTH, id, MV_SFLASH_RDID_REPLY_LENGTH, 0)) != MV_OK) ++ return ret; ++ ++ *pManId = id[0]; ++ *pDevId = 0; ++ *pDevId |= (id[1] << 8); ++ *pDevId |= id[2]; ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvSFlashWpRegionSet - Set the Write-Protected region ++* ++* DESCRIPTION: ++* Set the Write-Protected region ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* wpRegion: which region will be protected ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSFlashWpRegionSet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION wpRegion) ++{ ++ MV_U8 wpMask; ++ ++ /* check for NULL pointer */ ++ if (pFlinfo == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Protection - check if the model was detected */ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check if the chip is an ST flash; then WP supports only 3 bits */ ++ if (pFlinfo->manufacturerId == MV_M25PXXX_ST_MANF_ID) ++ { ++ switch (wpRegion) ++ { ++ case MV_WP_NONE: ++ wpMask = MV_M25P_STATUS_BP_NONE; ++ break; ++ ++ case MV_WP_UPR_1OF128: ++ DB(mvOsPrintf("%s WARNING: Invaild option for this flash chip!\n", __FUNCTION__);) ++ return MV_NOT_SUPPORTED; ++ ++ case MV_WP_UPR_1OF64: ++ wpMask = MV_M25P_STATUS_BP_1_OF_64; ++ break; ++ ++ case MV_WP_UPR_1OF32: ++ wpMask = MV_M25P_STATUS_BP_1_OF_32; ++ break; ++ ++ case MV_WP_UPR_1OF16: ++ wpMask = MV_M25P_STATUS_BP_1_OF_16; ++ break; ++ ++ case MV_WP_UPR_1OF8: ++ wpMask = MV_M25P_STATUS_BP_1_OF_8; ++ break; ++ ++ case MV_WP_UPR_1OF4: ++ wpMask = MV_M25P_STATUS_BP_1_OF_4; ++ break; ++ ++ case MV_WP_UPR_1OF2: ++ wpMask = MV_M25P_STATUS_BP_1_OF_2; ++ break; ++ ++ case MV_WP_ALL: ++ wpMask = MV_M25P_STATUS_BP_ALL; ++ break; ++ ++ default: ++ DB(mvOsPrintf("%s WARNING: Invaild parameter WP region!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ } ++ /* check if the manufacturer is MXIC then the WP is 4bits */ ++ else if (pFlinfo->manufacturerId == MV_MXIC_MANF_ID) ++ { ++ switch (wpRegion) ++ { ++ case MV_WP_NONE: ++ wpMask = MV_MX25L_STATUS_BP_NONE; ++ break; ++ ++ case MV_WP_UPR_1OF128: ++ wpMask = MV_MX25L_STATUS_BP_1_OF_128; ++ break; ++ ++ case MV_WP_UPR_1OF64: ++ wpMask = MV_MX25L_STATUS_BP_1_OF_64; ++ break; ++ ++ case MV_WP_UPR_1OF32: ++ wpMask = MV_MX25L_STATUS_BP_1_OF_32; ++ break; ++ ++ case MV_WP_UPR_1OF16: ++ wpMask = MV_MX25L_STATUS_BP_1_OF_16; ++ break; ++ ++ case MV_WP_UPR_1OF8: ++ wpMask = MV_MX25L_STATUS_BP_1_OF_8; ++ break; ++ ++ case MV_WP_UPR_1OF4: ++ wpMask = MV_MX25L_STATUS_BP_1_OF_4; ++ break; ++ ++ case MV_WP_UPR_1OF2: ++ wpMask = MV_MX25L_STATUS_BP_1_OF_2; ++ break; ++ ++ case MV_WP_ALL: ++ wpMask = MV_MX25L_STATUS_BP_ALL; ++ break; ++ ++ default: ++ DB(mvOsPrintf("%s WARNING: Invaild parameter WP region!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ } ++ /* check if the manufacturer is SPANSION then the WP is 4bits */ ++ else if (pFlinfo->manufacturerId == MV_SPANSION_MANF_ID) ++ { ++ switch (wpRegion) ++ { ++ case MV_WP_NONE: ++ wpMask = MV_S25FL_STATUS_BP_NONE; ++ break; ++ ++ case MV_WP_UPR_1OF128: ++ DB(mvOsPrintf("%s WARNING: Invaild option for this flash chip!\n", __FUNCTION__);) ++ return MV_NOT_SUPPORTED; ++ ++ case MV_WP_UPR_1OF64: ++ wpMask = MV_S25FL_STATUS_BP_1_OF_64; ++ break; ++ ++ case MV_WP_UPR_1OF32: ++ wpMask = MV_S25FL_STATUS_BP_1_OF_32; ++ break; ++ ++ case MV_WP_UPR_1OF16: ++ wpMask = MV_S25FL_STATUS_BP_1_OF_16; ++ break; ++ ++ case MV_WP_UPR_1OF8: ++ wpMask = MV_S25FL_STATUS_BP_1_OF_8; ++ break; ++ ++ case MV_WP_UPR_1OF4: ++ wpMask = MV_S25FL_STATUS_BP_1_OF_4; ++ break; ++ ++ case MV_WP_UPR_1OF2: ++ wpMask = MV_S25FL_STATUS_BP_1_OF_2; ++ break; ++ ++ case MV_WP_ALL: ++ wpMask = MV_S25FL_STATUS_BP_ALL; ++ break; ++ ++ ++ default: ++ DB(mvOsPrintf("%s WARNING: Invaild parameter WP region!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ } ++ else ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter Manufacturer ID!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ /* Verify that the SRWD bit is always set - register is s/w locked */ ++ wpMask |= MV_SFLASH_STATUS_REG_SRWD_MASK; ++ ++ return mvStatusRegSet(pFlinfo, wpMask); ++} ++ ++/******************************************************************************* ++* mvSFlashWpRegionGet - Get the Write-Protected region configured ++* ++* DESCRIPTION: ++* Get from the chip the Write-Protected region configured ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* pWpRegion: pointer to the variable to return the WP region in ++* ++* OUTPUT: ++* wpRegion: pointer to the variable holding the WP region configured ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSFlashWpRegionGet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION * pWpRegion) ++{ ++ MV_STATUS ret; ++ MV_U8 reg; ++ ++ /* check for NULL pointer */ ++ if ((pFlinfo == NULL) || (pWpRegion == NULL)) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Protection - check if the model was detected */ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ if ((ret = mvStatusRegGet(pFlinfo, ®)) != MV_OK) ++ return ret; ++ ++ /* Check if the chip is an ST flash; then WP supports only 3 bits */ ++ if (pFlinfo->manufacturerId == MV_M25PXXX_ST_MANF_ID) ++ { ++ switch ((reg & MV_M25P_STATUS_REG_WP_MASK)) ++ { ++ case MV_M25P_STATUS_BP_NONE: ++ *pWpRegion = MV_WP_NONE; ++ break; ++ ++ case MV_M25P_STATUS_BP_1_OF_64: ++ *pWpRegion = MV_WP_UPR_1OF64; ++ break; ++ ++ case MV_M25P_STATUS_BP_1_OF_32: ++ *pWpRegion = MV_WP_UPR_1OF32; ++ break; ++ ++ case MV_M25P_STATUS_BP_1_OF_16: ++ *pWpRegion = MV_WP_UPR_1OF16; ++ break; ++ ++ case MV_M25P_STATUS_BP_1_OF_8: ++ *pWpRegion = MV_WP_UPR_1OF8; ++ break; ++ ++ case MV_M25P_STATUS_BP_1_OF_4: ++ *pWpRegion = MV_WP_UPR_1OF4; ++ break; ++ ++ case MV_M25P_STATUS_BP_1_OF_2: ++ *pWpRegion = MV_WP_UPR_1OF2; ++ break; ++ ++ case MV_M25P_STATUS_BP_ALL: ++ *pWpRegion = MV_WP_ALL; ++ break; ++ ++ default: ++ DB(mvOsPrintf("%s WARNING: Unidentified WP region in h/w!\n", __FUNCTION__);) ++ return MV_BAD_VALUE; ++ } ++ } ++ /* check if the manufacturer is MXIC then the WP is 4bits */ ++ else if (pFlinfo->manufacturerId == MV_MXIC_MANF_ID) ++ { ++ switch ((reg & MV_MX25L_STATUS_REG_WP_MASK)) ++ { ++ case MV_MX25L_STATUS_BP_NONE: ++ *pWpRegion = MV_WP_NONE; ++ break; ++ ++ case MV_MX25L_STATUS_BP_1_OF_128: ++ *pWpRegion = MV_WP_UPR_1OF128; ++ break; ++ ++ case MV_MX25L_STATUS_BP_1_OF_64: ++ *pWpRegion = MV_WP_UPR_1OF64; ++ break; ++ ++ case MV_MX25L_STATUS_BP_1_OF_32: ++ *pWpRegion = MV_WP_UPR_1OF32; ++ break; ++ ++ case MV_MX25L_STATUS_BP_1_OF_16: ++ *pWpRegion = MV_WP_UPR_1OF16; ++ break; ++ ++ case MV_MX25L_STATUS_BP_1_OF_8: ++ *pWpRegion = MV_WP_UPR_1OF8; ++ break; ++ ++ case MV_MX25L_STATUS_BP_1_OF_4: ++ *pWpRegion = MV_WP_UPR_1OF4; ++ break; ++ ++ case MV_MX25L_STATUS_BP_1_OF_2: ++ *pWpRegion = MV_WP_UPR_1OF2; ++ break; ++ ++ case MV_MX25L_STATUS_BP_ALL: ++ *pWpRegion = MV_WP_ALL; ++ break; ++ ++ default: ++ DB(mvOsPrintf("%s WARNING: Unidentified WP region in h/w!\n", __FUNCTION__);) ++ return MV_BAD_VALUE; ++ } ++ } ++ /* Check if the chip is an SPANSION flash; then WP supports only 3 bits */ ++ else if (pFlinfo->manufacturerId == MV_SPANSION_MANF_ID) ++ { ++ switch ((reg & MV_S25FL_STATUS_REG_WP_MASK)) ++ { ++ case MV_S25FL_STATUS_BP_NONE: ++ *pWpRegion = MV_WP_NONE; ++ break; ++ ++ case MV_S25FL_STATUS_BP_1_OF_64: ++ *pWpRegion = MV_WP_UPR_1OF64; ++ break; ++ ++ case MV_S25FL_STATUS_BP_1_OF_32: ++ *pWpRegion = MV_WP_UPR_1OF32; ++ break; ++ ++ case MV_S25FL_STATUS_BP_1_OF_16: ++ *pWpRegion = MV_WP_UPR_1OF16; ++ break; ++ ++ case MV_S25FL_STATUS_BP_1_OF_8: ++ *pWpRegion = MV_WP_UPR_1OF8; ++ break; ++ ++ case MV_S25FL_STATUS_BP_1_OF_4: ++ *pWpRegion = MV_WP_UPR_1OF4; ++ break; ++ ++ case MV_S25FL_STATUS_BP_1_OF_2: ++ *pWpRegion = MV_WP_UPR_1OF2; ++ break; ++ ++ case MV_S25FL_STATUS_BP_ALL: ++ *pWpRegion = MV_WP_ALL; ++ break; ++ ++ default: ++ DB(mvOsPrintf("%s WARNING: Unidentified WP region in h/w!\n", __FUNCTION__);) ++ return MV_BAD_VALUE; ++ } ++ } ++ else ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter Manufacturer ID!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvSFlashStatRegLock - Lock the status register for writing - W/Vpp ++* pin should be low to take effect ++* ++* DESCRIPTION: ++* Lock the access to the Status Register for writing. This will ++* cause the flash to enter the hardware protection mode if the W/Vpp ++* is low. If the W/Vpp is hi, the chip will be in soft protection mode, but ++* the register will continue to be writable if WREN sequence was used. ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* srLock: enable/disable (MV_TRUE/MV_FALSE) status registor lock mechanism ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSFlashStatRegLock (MV_SFLASH_INFO * pFlinfo, MV_BOOL srLock) ++{ ++ MV_STATUS ret; ++ MV_U8 reg; ++ ++ /* check for NULL pointer */ ++ if (pFlinfo == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Protection - check if the model was detected */ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ if ((ret = mvStatusRegGet(pFlinfo, ®)) != MV_OK) ++ return ret; ++ ++ if (srLock) ++ reg |= MV_SFLASH_STATUS_REG_SRWD_MASK; ++ else ++ reg &= ~MV_SFLASH_STATUS_REG_SRWD_MASK; ++ ++ return mvStatusRegSet(pFlinfo, reg); ++} ++ ++/******************************************************************************* ++* mvSFlashSizeGet - Get the size of the SPI flash ++* ++* DESCRIPTION: ++* based on the sector number and size of each sector calculate the total ++* size of the flash memory. ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Size of the flash in bytes. ++* ++* ++*******************************************************************************/ ++MV_U32 mvSFlashSizeGet (MV_SFLASH_INFO * pFlinfo) ++{ ++ /* check for NULL pointer */ ++ if (pFlinfo == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return 0; ++ } ++ ++ return (pFlinfo->sectorSize * pFlinfo->sectorNumber); ++} ++ ++/******************************************************************************* ++* mvSFlashPowerSaveEnter - Cause the falsh device to go into power save mode ++* ++* DESCRIPTION: ++* Enter a special power save mode. ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Size of the flash in bytes. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSFlashPowerSaveEnter(MV_SFLASH_INFO * pFlinfo) ++{ ++ MV_STATUS ret; ++ MV_U8 cmd[MV_SFLASH_DP_CMND_LENGTH]; ++ ++ ++ /* check for NULL pointer */ ++ if (pFlinfo == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return 0; ++ } ++ ++ /* Protection - check if the model was detected */ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ /* check that power save mode is supported in the specific device */ ++ if (sflash[pFlinfo->index].opcdPwrSave == MV_SFLASH_NO_SPECIFIC_OPCD) ++ { ++ DB(mvOsPrintf("%s WARNING: Power save not supported for this device!\n", __FUNCTION__);) ++ return MV_NOT_SUPPORTED; ++ } ++ ++ cmd[0] = sflash[pFlinfo->index].opcdPwrSave; ++ ++ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_DP_CMND_LENGTH, NULL, 0)) != MV_OK) ++ return ret; ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvSFlashPowerSaveExit - Cause the falsh device to exit the power save mode ++* ++* DESCRIPTION: ++* Exit the deep power save mode. ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Size of the flash in bytes. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSFlashPowerSaveExit (MV_SFLASH_INFO * pFlinfo) ++{ ++ MV_STATUS ret; ++ MV_U8 cmd[MV_SFLASH_RES_CMND_LENGTH]; ++ ++ ++ /* check for NULL pointer */ ++ if (pFlinfo == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return 0; ++ } ++ ++ /* Protection - check if the model was detected */ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ /* check that power save mode is supported in the specific device */ ++ if (sflash[pFlinfo->index].opcdRES == MV_SFLASH_NO_SPECIFIC_OPCD) ++ { ++ DB(mvOsPrintf("%s WARNING: Read Electronic Signature not supported for this device!\n", __FUNCTION__);) ++ return MV_NOT_SUPPORTED; ++ } ++ ++ cmd[0] = sflash[pFlinfo->index].opcdRES; ++ ++ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_RES_CMND_LENGTH, NULL, 0)) != MV_OK) ++ return ret; ++ ++ /* add the delay needed for the device to wake up */ ++ mvOsDelay(MV_MXIC_DP_EXIT_DELAY); /* 30 ms */ ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvSFlashModelGet - Retreive the string with the device manufacturer and model ++* ++* DESCRIPTION: ++* Retreive the string with the device manufacturer and model ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* pointer to the string indicating the device manufacturer and model ++* ++* ++*******************************************************************************/ ++const MV_8 * mvSFlashModelGet (MV_SFLASH_INFO * pFlinfo) ++{ ++ static const MV_8 * unknModel = (const MV_8 *)"Unknown"; ++ ++ /* check for NULL pointer */ ++ if (pFlinfo == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return 0; ++ } ++ ++ /* Protection - check if the model was detected */ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) ++ return unknModel; ++ } ++ ++ return sflash[pFlinfo->index].deviceModel; ++} ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,166 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvSFlashH ++#define __INCmvSFlashH ++ ++#include "mvTypes.h" ++ ++/* MCAROS */ ++#define MV_SFLASH_PAGE_ALLIGN_MASK(pgSz) (pgSz-1) ++#define MV_ARRAY_SIZE(a) ((sizeof(a)) / (sizeof(a[0]))) ++ ++/* Constants */ ++#define MV_INVALID_DEVICE_NUMBER 0xFFFFFFFF ++/* 10 MHz is the minimum possible SPI frequency when tclk is set 200MHz*/ ++#define MV_SFLASH_BASIC_SPI_FREQ 10000000 ++/* enumerations */ ++typedef enum ++{ ++ MV_WP_NONE, /* Unprotect the whole chip */ ++ MV_WP_UPR_1OF128, /* Write protect the upper 1/128 part */ ++ MV_WP_UPR_1OF64, /* Write protect the upper 1/64 part */ ++ MV_WP_UPR_1OF32, /* Write protect the upper 1/32 part */ ++ MV_WP_UPR_1OF16, /* Write protect the upper 1/16 part */ ++ MV_WP_UPR_1OF8, /* Write protect the upper 1/8 part */ ++ MV_WP_UPR_1OF4, /* Write protect the upper 1/4 part */ ++ MV_WP_UPR_1OF2, /* Write protect the upper 1/2 part */ ++ MV_WP_ALL /* Write protect the whole chip */ ++} MV_SFLASH_WP_REGION; ++ ++/* Type Definitions */ ++typedef struct ++{ ++ MV_U8 opcdWREN; /* Write enable opcode */ ++ MV_U8 opcdWRDI; /* Write disable opcode */ ++ MV_U8 opcdRDID; /* Read ID opcode */ ++ MV_U8 opcdRDSR; /* Read Status Register opcode */ ++ MV_U8 opcdWRSR; /* Write Status register opcode */ ++ MV_U8 opcdREAD; /* Read opcode */ ++ MV_U8 opcdFSTRD; /* Fast Read opcode */ ++ MV_U8 opcdPP; /* Page program opcode */ ++ MV_U8 opcdSE; /* Sector erase opcode */ ++ MV_U8 opcdBE; /* Bulk erase opcode */ ++ MV_U8 opcdRES; /* Read electronic signature */ ++ MV_U8 opcdPwrSave; /* Go into power save mode */ ++ MV_U32 sectorSize; /* Size of each sector */ ++ MV_U32 sectorNumber; /* Number of sectors */ ++ MV_U32 pageSize; /* size of each page */ ++ const char * deviceModel; /* string with the device model */ ++ MV_U32 manufacturerId; /* The manufacturer ID */ ++ MV_U32 deviceId; /* Device ID */ ++ MV_U32 spiMaxFreq; /* The MAX frequency that can be used with the device */ ++ MV_U32 spiMaxFastFreq; /* The MAX frequency that can be used with the device for fast reads */ ++ MV_U32 spiFastRdDummyBytes; /* Number of dumy bytes to read before real data when working in fast read mode. */ ++} MV_SFLASH_DEVICE_PARAMS; ++ ++typedef struct ++{ ++ MV_U32 baseAddr; /* Flash Base Address used in fast mode */ ++ MV_U8 manufacturerId; /* Manufacturer ID */ ++ MV_U16 deviceId; /* Device ID */ ++ MV_U32 sectorSize; /* Size of each sector - all the same */ ++ MV_U32 sectorNumber; /* Number of sectors */ ++ MV_U32 pageSize; /* Page size - affect allignment */ ++ MV_U32 index; /* index of the device in the sflash table (internal parameter) */ ++} MV_SFLASH_INFO; ++ ++/* Function Prototypes */ ++/* Init */ ++MV_STATUS mvSFlashInit (MV_SFLASH_INFO * pFlinfo); ++ ++/* erase */ ++MV_STATUS mvSFlashSectorErase (MV_SFLASH_INFO * pFlinfo, MV_U32 secNumber); ++MV_STATUS mvSFlashChipErase (MV_SFLASH_INFO * pFlinfo); ++ ++/* Read */ ++MV_STATUS mvSFlashBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, ++ MV_U8* pReadBuff, MV_U32 buffSize); ++MV_STATUS mvSFlashFastBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, ++ MV_U8* pReadBuff, MV_U32 buffSize); ++ ++/* write regardless of the page boundaries and size limit per Page program command */ ++MV_STATUS mvSFlashBlockWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, ++ MV_U8* pWriteBuff, MV_U32 buffSize); ++/* Get IDs */ ++MV_STATUS mvSFlashIdGet (MV_SFLASH_INFO * pFlinfo, MV_U8* pManId, MV_U16* pDevId); ++ ++/* Set and Get the Write Protection region - if the Status register is not locked */ ++MV_STATUS mvSFlashWpRegionSet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION wpRegion); ++MV_STATUS mvSFlashWpRegionGet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION * pWpRegion); ++ ++/* Lock the status register for writing - W/Vpp pin should be low to take effect */ ++MV_STATUS mvSFlashStatRegLock (MV_SFLASH_INFO * pFlinfo, MV_BOOL srLock); ++ ++/* Get the regions sizes */ ++MV_U32 mvSFlashSizeGet (MV_SFLASH_INFO * pFlinfo); ++ ++/* Cause the falsh device to go into power save mode */ ++MV_STATUS mvSFlashPowerSaveEnter(MV_SFLASH_INFO * pFlinfo); ++MV_STATUS mvSFlashPowerSaveExit (MV_SFLASH_INFO * pFlinfo); ++ ++/* Retreive the string with the device manufacturer and model */ ++const MV_8 * mvSFlashModelGet (MV_SFLASH_INFO * pFlinfo); ++ ++#endif /* __INCmvSFlashH */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlashSpec.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlashSpec.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlashSpec.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlashSpec.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,233 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvSFlashSpecH ++#define __INCmvSFlashSpecH ++ ++/* Constants */ ++#define MV_SFLASH_READ_CMND_LENGTH 4 /* 1B opcode + 3B address */ ++#define MV_SFLASH_SE_CMND_LENGTH 4 /* 1B opcode + 3B address */ ++#define MV_SFLASH_BE_CMND_LENGTH 1 /* 1B opcode */ ++#define MV_SFLASH_PP_CMND_LENGTH 4 /* 1B opcode + 3B address */ ++#define MV_SFLASH_WREN_CMND_LENGTH 1 /* 1B opcode */ ++#define MV_SFLASH_WRDI_CMND_LENGTH 1 /* 1B opcode */ ++#define MV_SFLASH_RDID_CMND_LENGTH 1 /* 1B opcode */ ++#define MV_SFLASH_RDID_REPLY_LENGTH 3 /* 1B manf ID and 2B device ID */ ++#define MV_SFLASH_RDSR_CMND_LENGTH 1 /* 1B opcode */ ++#define MV_SFLASH_RDSR_REPLY_LENGTH 1 /* 1B status */ ++#define MV_SFLASH_WRSR_CMND_LENGTH 2 /* 1B opcode + 1B status value */ ++#define MV_SFLASH_DP_CMND_LENGTH 1 /* 1B opcode */ ++#define MV_SFLASH_RES_CMND_LENGTH 1 /* 1B opcode */ ++ ++/* Status Register Bit Masks */ ++#define MV_SFLASH_STATUS_REG_WIP_OFFSET 0 /* bit 0; write in progress */ ++#define MV_SFLASH_STATUS_REG_WP_OFFSET 2 /* bit 2-4; write protect option */ ++#define MV_SFLASH_STATUS_REG_SRWD_OFFSET 7 /* bit 7; lock status register write */ ++#define MV_SFLASH_STATUS_REG_WIP_MASK (0x1 << MV_SFLASH_STATUS_REG_WIP_OFFSET) ++#define MV_SFLASH_STATUS_REG_SRWD_MASK (0x1 << MV_SFLASH_STATUS_REG_SRWD_OFFSET) ++ ++#define MV_SFLASH_MAX_WAIT_LOOP 1000000 ++#define MV_SFLASH_CHIP_ERASE_MAX_WAIT_LOOP 0x50000000 ++ ++#define MV_SFLASH_DEFAULT_RDID_OPCD 0x9F /* Default Read ID */ ++#define MV_SFLASH_DEFAULT_WREN_OPCD 0x06 /* Default Write Enable */ ++#define MV_SFLASH_NO_SPECIFIC_OPCD 0x00 ++ ++/********************************/ ++/* ST M25Pxxx Device Specific */ ++/********************************/ ++ ++/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ ++#define MV_M25PXXX_ST_MANF_ID 0x20 ++#define MV_M25P32_DEVICE_ID 0x2016 ++#define MV_M25P32_MAX_SPI_FREQ 20000000 /* 20MHz */ ++#define MV_M25P32_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ ++#define MV_M25P32_FAST_READ_DUMMY_BYTES 1 ++#define MV_M25P64_DEVICE_ID 0x2017 ++#define MV_M25P64_MAX_SPI_FREQ 20000000 /* 20MHz */ ++#define MV_M25P64_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ ++#define MV_M25P64_FAST_READ_DUMMY_BYTES 1 ++#define MV_M25P128_DEVICE_ID 0x2018 ++#define MV_M25P128_MAX_SPI_FREQ 20000000 /* 20MHz */ ++#define MV_M25P128_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ ++#define MV_M25P128_FAST_READ_DUMMY_BYTES 1 ++ ++ ++/* Sector Sizes and population per device model*/ ++#define MV_M25P32_SECTOR_SIZE 0x10000 /* 64K */ ++#define MV_M25P64_SECTOR_SIZE 0x10000 /* 64K */ ++#define MV_M25P128_SECTOR_SIZE 0x40000 /* 256K */ ++#define MV_M25P32_SECTOR_NUMBER 64 ++#define MV_M25P64_SECTOR_NUMBER 128 ++#define MV_M25P128_SECTOR_NUMBER 64 ++#define MV_M25P_PAGE_SIZE 0x100 /* 256 byte */ ++ ++#define MV_M25P_WREN_CMND_OPCD 0x06 /* Write Enable */ ++#define MV_M25P_WRDI_CMND_OPCD 0x04 /* Write Disable */ ++#define MV_M25P_RDID_CMND_OPCD 0x9F /* Read ID */ ++#define MV_M25P_RDSR_CMND_OPCD 0x05 /* Read Status Register */ ++#define MV_M25P_WRSR_CMND_OPCD 0x01 /* Write Status Register */ ++#define MV_M25P_READ_CMND_OPCD 0x03 /* Sequential Read */ ++#define MV_M25P_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ ++#define MV_M25P_PP_CMND_OPCD 0x02 /* Page Program */ ++#define MV_M25P_SE_CMND_OPCD 0xD8 /* Sector Erase */ ++#define MV_M25P_BE_CMND_OPCD 0xC7 /* Bulk Erase */ ++#define MV_M25P_RES_CMND_OPCD 0xAB /* Read Electronic Signature */ ++ ++/* Status Register Write Protect Bit Masks - 3bits */ ++#define MV_M25P_STATUS_REG_WP_MASK (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_M25P_STATUS_BP_NONE (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_M25P_STATUS_BP_1_OF_64 (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_M25P_STATUS_BP_1_OF_32 (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_M25P_STATUS_BP_1_OF_16 (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_M25P_STATUS_BP_1_OF_8 (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_M25P_STATUS_BP_1_OF_4 (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_M25P_STATUS_BP_1_OF_2 (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_M25P_STATUS_BP_ALL (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++ ++/************************************/ ++/* MXIC MX25L6405 Device Specific */ ++/************************************/ ++ ++/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ ++#define MV_MXIC_MANF_ID 0xC2 ++#define MV_MX25L6405_DEVICE_ID 0x2017 ++#define MV_MX25L6405_MAX_SPI_FREQ 20000000 /* 20MHz */ ++#define MV_MX25L6405_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ ++#define MV_MX25L6405_FAST_READ_DUMMY_BYTES 1 ++#define MV_MXIC_DP_EXIT_DELAY 30 /* 30 ms */ ++ ++/* Sector Sizes and population per device model*/ ++#define MV_MX25L6405_SECTOR_SIZE 0x10000 /* 64K */ ++#define MV_MX25L6405_SECTOR_NUMBER 128 ++#define MV_MXIC_PAGE_SIZE 0x100 /* 256 byte */ ++ ++#define MV_MX25L_WREN_CMND_OPCD 0x06 /* Write Enable */ ++#define MV_MX25L_WRDI_CMND_OPCD 0x04 /* Write Disable */ ++#define MV_MX25L_RDID_CMND_OPCD 0x9F /* Read ID */ ++#define MV_MX25L_RDSR_CMND_OPCD 0x05 /* Read Status Register */ ++#define MV_MX25L_WRSR_CMND_OPCD 0x01 /* Write Status Register */ ++#define MV_MX25L_READ_CMND_OPCD 0x03 /* Sequential Read */ ++#define MV_MX25L_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ ++#define MV_MX25L_PP_CMND_OPCD 0x02 /* Page Program */ ++#define MV_MX25L_SE_CMND_OPCD 0xD8 /* Sector Erase */ ++#define MV_MX25L_BE_CMND_OPCD 0xC7 /* Bulk Erase */ ++#define MV_MX25L_DP_CMND_OPCD 0xB9 /* Deep Power Down */ ++#define MV_MX25L_RES_CMND_OPCD 0xAB /* Read Electronic Signature */ ++ ++/* Status Register Write Protect Bit Masks - 4bits */ ++#define MV_MX25L_STATUS_REG_WP_MASK (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_MX25L_STATUS_BP_NONE (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_MX25L_STATUS_BP_1_OF_128 (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_MX25L_STATUS_BP_1_OF_64 (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_MX25L_STATUS_BP_1_OF_32 (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_MX25L_STATUS_BP_1_OF_16 (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_MX25L_STATUS_BP_1_OF_8 (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_MX25L_STATUS_BP_1_OF_4 (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_MX25L_STATUS_BP_1_OF_2 (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_MX25L_STATUS_BP_ALL (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) ++ ++/************************************/ ++/* SPANSION S25FL128P Device Specific */ ++/************************************/ ++ ++/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ ++#define MV_SPANSION_MANF_ID 0x01 ++#define MV_S25FL128_DEVICE_ID 0x2018 ++#define MV_S25FL128_MAX_SPI_FREQ 33000000 /* 33MHz */ ++#define MV_S25FL128_MAX_FAST_SPI_FREQ 104000000 /* 104MHz */ ++#define MV_S25FL128_FAST_READ_DUMMY_BYTES 1 ++ ++/* Sector Sizes and population per device model*/ ++#define MV_S25FL128_SECTOR_SIZE 0x40000 /* 256K */ ++#define MV_S25FL128_SECTOR_NUMBER 64 ++#define MV_S25FL_PAGE_SIZE 0x100 /* 256 byte */ ++ ++#define MV_S25FL_WREN_CMND_OPCD 0x06 /* Write Enable */ ++#define MV_S25FL_WRDI_CMND_OPCD 0x04 /* Write Disable */ ++#define MV_S25FL_RDID_CMND_OPCD 0x9F /* Read ID */ ++#define MV_S25FL_RDSR_CMND_OPCD 0x05 /* Read Status Register */ ++#define MV_S25FL_WRSR_CMND_OPCD 0x01 /* Write Status Register */ ++#define MV_S25FL_READ_CMND_OPCD 0x03 /* Sequential Read */ ++#define MV_S25FL_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ ++#define MV_S25FL_PP_CMND_OPCD 0x02 /* Page Program */ ++#define MV_S25FL_SE_CMND_OPCD 0xD8 /* Sector Erase */ ++#define MV_S25FL_BE_CMND_OPCD 0xC7 /* Bulk Erase */ ++#define MV_S25FL_DP_CMND_OPCD 0xB9 /* Deep Power Down */ ++#define MV_S25FL_RES_CMND_OPCD 0xAB /* Read Electronic Signature */ ++ ++/* Status Register Write Protect Bit Masks - 4bits */ ++#define MV_S25FL_STATUS_REG_WP_MASK (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_S25FL_STATUS_BP_NONE (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_S25FL_STATUS_BP_1_OF_128 (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_S25FL_STATUS_BP_1_OF_64 (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_S25FL_STATUS_BP_1_OF_32 (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_S25FL_STATUS_BP_1_OF_16 (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_S25FL_STATUS_BP_1_OF_8 (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_S25FL_STATUS_BP_1_OF_4 (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_S25FL_STATUS_BP_1_OF_2 (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_S25FL_STATUS_BP_ALL (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) ++ ++#endif /* __INCmvSFlashSpecH */ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvCompVer.txt linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvCompVer.txt +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvCompVer.txt 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvCompVer.txt 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,4 @@ ++Global HAL Version: FEROCEON_HAL_3_1_7 ++Unit HAL Version: 3.1.3 ++Description: This component includes an implementation of the unit HAL drivers ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,576 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#include "spi/mvSpi.h" ++#include "spi/mvSpiSpec.h" ++ ++#include "ctrlEnv/mvCtrlEnvLib.h" ++ ++/* #define MV_DEBUG */ ++#ifdef MV_DEBUG ++#define DB(x) x ++#define mvOsPrintf printf ++#else ++#define DB(x) ++#endif ++ ++ ++/******************************************************************************* ++* mvSpi16bitDataTxRx - Transmt and receive data ++* ++* DESCRIPTION: ++* Tx data and block waiting for data to be transmitted ++* ++********************************************************************************/ ++static MV_STATUS mvSpi16bitDataTxRx (MV_U16 txData, MV_U16 * pRxData) ++{ ++ MV_U32 i; ++ MV_BOOL ready = MV_FALSE; ++ ++ /* First clear the bit in the interrupt cause register */ ++ MV_REG_WRITE(MV_SPI_INT_CAUSE_REG, 0x0); ++ ++ /* Transmit data */ ++ MV_REG_WRITE(MV_SPI_DATA_OUT_REG, MV_16BIT_LE(txData)); ++ ++ /* wait with timeout for memory ready */ ++ for (i=0; i> 8) & 0xFF); ++ ++#elif defined(MV_CPU_BE) ++ ++ /* perform the data write to the buffer in two stages with 8bit each */ ++ MV_U8 * bptr = (MV_U8 *)pRxData; ++ MV_U16 data = MV_16BIT_LE(MV_REG_READ(MV_SPI_DATA_IN_REG)); ++ *bptr = ((data >> 8) & 0xFF); ++ ++bptr; ++ *bptr = (data & 0xFF); ++ ++#else ++ #error "CPU endianess isn't defined!\n" ++#endif ++ ++ } ++ else ++ *pRxData = MV_16BIT_LE(MV_REG_READ(MV_SPI_DATA_IN_REG)); ++ } ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvSpi8bitDataTxRx - Transmt and receive data (8bits) ++* ++* DESCRIPTION: ++* Tx data and block waiting for data to be transmitted ++* ++********************************************************************************/ ++static MV_STATUS mvSpi8bitDataTxRx (MV_U8 txData, MV_U8 * pRxData) ++{ ++ MV_U32 i; ++ MV_BOOL ready = MV_FALSE; ++ ++ /* First clear the bit in the interrupt cause register */ ++ MV_REG_WRITE(MV_SPI_INT_CAUSE_REG, 0x0); ++ ++ /* Transmit data */ ++ MV_REG_WRITE(MV_SPI_DATA_OUT_REG, txData); ++ ++ /* wait with timeout for memory ready */ ++ for (i=0; i serialBaudRate) ++ continue; ++ ++ /* check for exact fit */ ++ if ((cpuClk / preScale[i]) == serialBaudRate) ++ { ++ bestPrescaleIndx = i; ++ break; ++ } ++ ++ /* check if this is better than the previous one */ ++ if ((serialBaudRate - (cpuClk / preScale[i])) < minBaudOffset) ++ { ++ minBaudOffset = (serialBaudRate - (cpuClk / preScale[i])); ++ bestPrescaleIndx = i; ++ } ++ } ++ ++ if (bestPrescaleIndx > 14) ++ { ++ mvOsPrintf("%s ERROR: SPI baud rate prescale error!\n", __FUNCTION__); ++ return MV_OUT_OF_RANGE; ++ } ++ ++ /* configure the Prescale */ ++ tempReg = MV_REG_READ(MV_SPI_IF_CONFIG_REG); ++ tempReg = ((tempReg & ~MV_SPI_CLK_PRESCALE_MASK) | (bestPrescaleIndx + 0x12)); ++ MV_REG_WRITE(MV_SPI_IF_CONFIG_REG, tempReg); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvSpiCsAssert - Assert the Chip Select pin indicating a new transfer ++* ++* DESCRIPTION: ++* Assert The chip select - used to select an external SPI device ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Success or Error code. ++* ++********************************************************************************/ ++MV_VOID mvSpiCsAssert(MV_VOID) ++{ ++ /* For devices in which the SPI is muxed on the MPP with other interfaces*/ ++ mvMPPConfigToSPI(); ++ mvOsUDelay(1); ++ MV_REG_BIT_SET(MV_SPI_IF_CTRL_REG, MV_SPI_CS_ENABLE_MASK); ++} ++ ++/******************************************************************************* ++* mvSpiCsDeassert - DeAssert the Chip Select pin indicating the end of a ++* SPI transfer sequence ++* ++* DESCRIPTION: ++* DeAssert the chip select pin ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Success or Error code. ++* ++********************************************************************************/ ++MV_VOID mvSpiCsDeassert(MV_VOID) ++{ ++ MV_REG_BIT_RESET(MV_SPI_IF_CTRL_REG, MV_SPI_CS_ENABLE_MASK); ++ ++ /* For devices in which the SPI is muxed on the MPP with other interfaces*/ ++ mvMPPConfigToDefault(); ++} ++ ++/******************************************************************************* ++* mvSpiRead - Read a buffer over the SPI interface ++* ++* DESCRIPTION: ++* Receive (read) a buffer over the SPI interface in 16bit chunks. If the ++* buffer size is odd, then the last chunk will be 8bits. Chip select is not ++* handled at this level. ++* ++* INPUT: ++* pRxBuff: Pointer to the buffer to hold the received data ++* buffSize: length of the pRxBuff ++* ++* OUTPUT: ++* pRxBuff: Pointer to the buffer with the received data ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSpiRead (MV_U8* pRxBuff, MV_U32 buffSize) ++{ ++ MV_STATUS ret; ++ MV_U32 bytesLeft = buffSize; ++ MV_U16* rxPtr = (MV_U16*)pRxBuff; ++ ++ /* check for null parameters */ ++ if (pRxBuff == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check that the buffer pointer and the buffer size are 16bit aligned */ ++ if ((((MV_U32)buffSize & 1) == 0) && (((MV_U32)pRxBuff & 1) == 0)) ++ { ++ /* Verify that the SPI mode is in 16bit mode */ ++ MV_REG_BIT_SET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); ++ ++ /* TX/RX as long we have complete 16bit chunks */ ++ while (bytesLeft >= MV_SPI_16_BIT_CHUNK_SIZE) ++ { ++ /* Transmitted and wait for the transfer to be completed */ ++ if ((ret = mvSpi16bitDataTxRx(MV_SPI_DUMMY_WRITE_16BITS, rxPtr)) != MV_OK) ++ return ret; ++ ++ /* increment the pointers */ ++ rxPtr++; ++ bytesLeft -= MV_SPI_16_BIT_CHUNK_SIZE; ++ } ++ ++ } ++ else ++ { ++ /* Verify that the SPI mode is in 8bit mode */ ++ MV_REG_BIT_RESET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); ++ ++ /* TX/RX in 8bit chanks */ ++ while (bytesLeft > 0) ++ { ++ /* Transmitted and wait for the transfer to be completed */ ++ if ((ret = mvSpi8bitDataTxRx(MV_SPI_DUMMY_WRITE_8BITS, pRxBuff)) != MV_OK) ++ return ret; ++ /* increment the pointers */ ++ pRxBuff++; ++ bytesLeft--; ++ } ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvSpiWrite - Transmit a buffer over the SPI interface ++* ++* DESCRIPTION: ++* Transmit a buffer over the SPI interface in 16bit chunks. If the ++* buffer size is odd, then the last chunk will be 8bits. No chip select ++* action is taken. ++* ++* INPUT: ++* pTxBuff: Pointer to the buffer holding the TX data ++* buffSize: length of the pTxBuff ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSpiWrite(MV_U8* pTxBuff, MV_U32 buffSize) ++{ ++ MV_STATUS ret; ++ MV_U32 bytesLeft = buffSize; ++ MV_U16* txPtr = (MV_U16*)pTxBuff; ++ ++ /* check for null parameters */ ++ if (pTxBuff == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check that the buffer pointer and the buffer size are 16bit aligned */ ++ if ((((MV_U32)buffSize & 1) == 0) && (((MV_U32)pTxBuff & 1) == 0)) ++ { ++ /* Verify that the SPI mode is in 16bit mode */ ++ MV_REG_BIT_SET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); ++ ++ /* TX/RX as long we have complete 16bit chunks */ ++ while (bytesLeft >= MV_SPI_16_BIT_CHUNK_SIZE) ++ { ++ /* Transmitted and wait for the transfer to be completed */ ++ if ((ret = mvSpi16bitDataTxRx(*txPtr, NULL)) != MV_OK) ++ return ret; ++ ++ /* increment the pointers */ ++ txPtr++; ++ bytesLeft -= MV_SPI_16_BIT_CHUNK_SIZE; ++ } ++ } ++ else ++ { ++ ++ /* Verify that the SPI mode is in 8bit mode */ ++ MV_REG_BIT_RESET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); ++ ++ /* TX/RX in 8bit chanks */ ++ while (bytesLeft > 0) ++ { ++ /* Transmitted and wait for the transfer to be completed */ ++ if ((ret = mvSpi8bitDataTxRx(*pTxBuff, NULL)) != MV_OK) ++ return ret; ++ ++ /* increment the pointers */ ++ pTxBuff++; ++ bytesLeft--; ++ } ++ } ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvSpiReadWrite - Read and Write a buffer simultanuosely ++* ++* DESCRIPTION: ++* Transmit and receive a buffer over the SPI in 16bit chunks. If the ++* buffer size is odd, then the last chunk will be 8bits. The SPI chip ++* select is not handled implicitely. ++* ++* INPUT: ++* pRxBuff: Pointer to the buffer to write the RX info in ++* pTxBuff: Pointer to the buffer holding the TX info ++* buffSize: length of both the pTxBuff and pRxBuff ++* ++* OUTPUT: ++* pRxBuff: Pointer of the buffer holding the RX data ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSpiReadWrite(MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize) ++{ ++ MV_STATUS ret; ++ MV_U32 bytesLeft = buffSize; ++ MV_U16* txPtr = (MV_U16*)pTxBuff; ++ MV_U16* rxPtr = (MV_U16*)pRxBuff; ++ ++ /* check for null parameters */ ++ if ((pRxBuff == NULL) || (pTxBuff == NULL)) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check that the buffer pointer and the buffer size are 16bit aligned */ ++ if ((((MV_U32)buffSize & 1) == 0) && (((MV_U32)pTxBuff & 1) == 0) && (((MV_U32)pRxBuff & 1) == 0)) ++ { ++ /* Verify that the SPI mode is in 16bit mode */ ++ MV_REG_BIT_SET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); ++ ++ /* TX/RX as long we have complete 16bit chunks */ ++ while (bytesLeft >= MV_SPI_16_BIT_CHUNK_SIZE) ++ { ++ /* Transmitted and wait for the transfer to be completed */ ++ if ((ret = mvSpi16bitDataTxRx(*txPtr, rxPtr)) != MV_OK) ++ return ret; ++ ++ /* increment the pointers */ ++ txPtr++; ++ rxPtr++; ++ bytesLeft -= MV_SPI_16_BIT_CHUNK_SIZE; ++ } ++ } ++ else ++ { ++ /* Verify that the SPI mode is in 8bit mode */ ++ MV_REG_BIT_RESET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); ++ ++ /* TX/RX in 8bit chanks */ ++ while (bytesLeft > 0) ++ { ++ /* Transmitted and wait for the transfer to be completed */ ++ if ( (ret = mvSpi8bitDataTxRx(*pTxBuff, pRxBuff) ) != MV_OK) ++ return ret; ++ pRxBuff++; ++ pTxBuff++; ++ bytesLeft--; ++ } ++ } ++ ++ return MV_OK; ++} ++ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,94 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvSpihH ++#define __INCmvSpihH ++ ++#include "mvCommon.h" ++#include "mvOs.h" ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++ ++/* Function Prototypes */ ++/* Init */ ++MV_STATUS mvSpiInit (MV_U32 serialBaudRate); ++ ++/* Set the Frequency of the Spi clock */ ++MV_STATUS mvSpiBaudRateSet(MV_U32 serialBaudRate); ++ ++/* Assert the SPI chip select */ ++MV_VOID mvSpiCsAssert (MV_VOID); ++ ++/* De-assert the SPI chip select */ ++MV_VOID mvSpiCsDeassert (MV_VOID); ++ ++/* Simultanuous Read and write */ ++MV_STATUS mvSpiReadWrite (MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize); ++ ++/* serialize a buffer on the TX line - Rx is ignored */ ++MV_STATUS mvSpiWrite (MV_U8* pTxBuff, MV_U32 buffSize); ++ ++/* read from the RX line by writing dummy values to the TX line */ ++MV_STATUS mvSpiRead (MV_U8* pRxBuff, MV_U32 buffSize); ++ ++#endif /* __INCmvSpihH */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,249 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#include "spi/mvSpi.h" ++#include "spi/mvSpiSpec.h" ++ ++/*#define MV_DEBUG*/ ++#ifdef MV_DEBUG ++#define DB(x) x ++#else ++#define DB(x) ++#endif ++ ++ ++/******************************************************************************* ++* mvSpiReadAndWrite - Read and Write a buffer simultanuousely ++* ++* DESCRIPTION: ++* Transmit and receive a buffer over the SPI in 16bit chunks. If the ++* buffer size is odd, then the last chunk will be 8bits. ++* ++* INPUT: ++* pRxBuff: Pointer to the buffer to write the RX info in ++* pTxBuff: Pointer to the buffer holding the TX info ++* buffSize: length of both the pTxBuff and pRxBuff ++* ++* OUTPUT: ++* pRxBuff: Pointer of the buffer holding the RX data ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSpiReadAndWrite(MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize) ++{ ++ MV_STATUS ret; ++ ++ /* check for null parameters */ ++ if ((pRxBuff == NULL) || (pTxBuff == NULL) || (buffSize == 0)) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* First assert the chip select */ ++ mvSpiCsAssert(); ++ ++ ret = mvSpiReadWrite(pRxBuff, pTxBuff, buffSize); ++ ++ /* Finally deassert the chip select */ ++ mvSpiCsDeassert(); ++ ++ return ret; ++} ++ ++/******************************************************************************* ++* mvSpiWriteThenWrite - Serialize a command followed by the data over the TX line ++* ++* DESCRIPTION: ++* Assert the chip select line. Transmit the command buffer followed by ++* the data buffer. Then deassert the CS line. ++* ++* INPUT: ++* pCmndBuff: Pointer to the command buffer to transmit ++* cmndSize: length of the command size ++* pTxDataBuff: Pointer to the data buffer to transmit ++* txDataSize: length of the data buffer ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSpiWriteThenWrite (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pTxDataBuff, ++ MV_U32 txDataSize) ++{ ++ MV_STATUS ret = MV_OK, tempRet; ++ ++ /* check for null parameters */ ++#ifndef CONFIG_MARVELL ++ if(NULL == pTxDataBuff) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++#endif ++ ++ if (pCmndBuff == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* First assert the chip select */ ++ mvSpiCsAssert(); ++ ++ /* first write the command */ ++ if ((cmndSize) && (pCmndBuff != NULL)) ++ { ++ if ((tempRet = mvSpiWrite(pCmndBuff, cmndSize)) != MV_OK) ++ ret = tempRet; ++ } ++ ++ /* Then write the data buffer */ ++#ifndef CONFIG_MARVELL ++ if (txDataSize) ++#else ++ if ((txDataSize) && (pTxDataBuff != NULL)) ++#endif ++ { ++ if ((tempRet = mvSpiWrite(pTxDataBuff, txDataSize)) != MV_OK) ++ ret = tempRet; ++ } ++ ++ /* Finally deassert the chip select */ ++ mvSpiCsDeassert(); ++ ++ return ret; ++} ++ ++/******************************************************************************* ++* mvSpiWriteThenRead - Serialize a command then read a data buffer ++* ++* DESCRIPTION: ++* Assert the chip select line. Transmit the command buffer then read ++* the data buffer. Then deassert the CS line. ++* ++* INPUT: ++* pCmndBuff: Pointer to the command buffer to transmit ++* cmndSize: length of the command size ++* pRxDataBuff: Pointer to the buffer to read the data in ++* txDataSize: length of the data buffer ++* ++* OUTPUT: ++* pRxDataBuff: Pointer to the buffer holding the data ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSpiWriteThenRead (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pRxDataBuff, ++ MV_U32 rxDataSize,MV_U32 dummyBytesToRead) ++{ ++ MV_STATUS ret = MV_OK, tempRet; ++ MV_U8 dummyByte; ++ ++ /* check for null parameters */ ++ if ((pCmndBuff == NULL) && (pRxDataBuff == NULL)) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* First assert the chip select */ ++ mvSpiCsAssert(); ++ ++ /* first write the command */ ++ if ((cmndSize) && (pCmndBuff != NULL)) ++ { ++ if ((tempRet = mvSpiWrite(pCmndBuff, cmndSize)) != MV_OK) ++ ret = tempRet; ++ } ++ ++ /* Read dummy bytes before real data. */ ++ while(dummyBytesToRead) ++ { ++ mvSpiRead(&dummyByte,1); ++ dummyBytesToRead--; ++ } ++ ++ /* Then write the data buffer */ ++ if ((rxDataSize) && (pRxDataBuff != NULL)) ++ { ++ if ((tempRet = mvSpiRead(pRxDataBuff, rxDataSize)) != MV_OK) ++ ret = tempRet; ++ } ++ ++ /* Finally deassert the chip select */ ++ mvSpiCsDeassert(); ++ ++ return ret; ++} ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,82 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvSpiCmndhH ++#define __INCmvSpiCmndhH ++ ++#include "mvTypes.h" ++ ++/* Function Prototypes */ ++ ++/* Simultanuous Read and write */ ++MV_STATUS mvSpiReadAndWrite (MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize); ++ ++/* write command - write a command and then write data */ ++MV_STATUS mvSpiWriteThenWrite (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pTxDataBuff, MV_U32 txDataSize); ++ ++/* read command - write a command and then read data by writing dummy data */ ++MV_STATUS mvSpiWriteThenRead (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pRxDataBuff, ++ MV_U32 rxDataSize,MV_U32 dummyBytesToRead); ++ ++#endif /* __INCmvSpiCmndhH */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiSpec.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiSpec.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiSpec.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiSpec.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,98 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvSpiSpecH ++#define __INCmvSpiSpecH ++ ++/* Constants */ ++#define MV_SPI_WAIT_RDY_MAX_LOOP 100000 ++#define MV_SPI_16_BIT_CHUNK_SIZE 2 ++#define MV_SPI_DUMMY_WRITE_16BITS 0xFFFF ++#define MV_SPI_DUMMY_WRITE_8BITS 0xFF ++ ++/* Marvell Flash Device Controller Registers */ ++#define MV_SPI_CTRLR_OFST 0x10600 ++#define MV_SPI_IF_CTRL_REG (MV_SPI_CTRLR_OFST + 0x00) ++#define MV_SPI_IF_CONFIG_REG (MV_SPI_CTRLR_OFST + 0x04) ++#define MV_SPI_DATA_OUT_REG (MV_SPI_CTRLR_OFST + 0x08) ++#define MV_SPI_DATA_IN_REG (MV_SPI_CTRLR_OFST + 0x0c) ++#define MV_SPI_INT_CAUSE_REG (MV_SPI_CTRLR_OFST + 0x10) ++#define MV_SPI_INT_CAUSE_MASK_REG (MV_SPI_CTRLR_OFST + 0x14) ++ ++/* Serial Memory Interface Control Register Masks */ ++#define MV_SPI_CS_ENABLE_OFFSET 0 /* bit 0 */ ++#define MV_SPI_MEMORY_READY_OFFSET 1 /* bit 1 */ ++#define MV_SPI_CS_ENABLE_MASK (0x1 << MV_SPI_CS_ENABLE_OFFSET) ++#define MV_SPI_MEMORY_READY_MASK (0x1 << MV_SPI_MEMORY_READY_OFFSET) ++ ++/* Serial Memory Interface Configuration Register Masks */ ++#define MV_SPI_CLK_PRESCALE_OFFSET 0 /* bit 0-4 */ ++#define MV_SPI_BYTE_LENGTH_OFFSET 5 /* bit 5 */ ++#define MV_SPI_ADDRESS_BURST_LENGTH_OFFSET 8 /* bit 8-9 */ ++#define MV_SPI_CLK_PRESCALE_MASK (0x1F << MV_SPI_CLK_PRESCALE_OFFSET) ++#define MV_SPI_BYTE_LENGTH_MASK (0x1 << MV_SPI_BYTE_LENGTH_OFFSET) ++#define MV_SPI_ADDRESS_BURST_LENGTH_MASK (0x3 << MV_SPI_ADDRESS_BURST_LENGTH_OFFSET) ++ ++#endif /* __INCmvSpiSpecH */ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvCompVer.txt linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvCompVer.txt +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvCompVer.txt 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvCompVer.txt 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,4 @@ ++Global HAL Version: FEROCEON_HAL_3_1_7 ++Unit HAL Version: 3.1.5 ++Description: This component includes an implementation of the unit HAL drivers ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.c linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.c +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,1023 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#include "mvTwsi.h" ++#include "mvTwsiSpec.h" ++#include "cpu/mvCpu.h" ++ ++ ++/*#define MV_DEBUG*/ ++#ifdef MV_DEBUG ++#define DB(x) x ++#else ++#define DB(x) ++#endif ++ ++static MV_VOID twsiIntFlgClr(MV_U8 chanNum); ++static MV_BOOL twsiMainIntGet(MV_U8 chanNum); ++static MV_VOID twsiAckBitSet(MV_U8 chanNum); ++static MV_U32 twsiStsGet(MV_U8 chanNum); ++static MV_VOID twsiReset(MV_U8 chanNum); ++static MV_STATUS twsiAddr7BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command); ++static MV_STATUS twsiAddr10BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command); ++static MV_STATUS twsiDataTransmit(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize); ++static MV_STATUS twsiDataReceive(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize); ++static MV_STATUS twsiTargetOffsSet(MV_U8 chanNum, MV_U32 offset,MV_BOOL moreThen256); ++ ++ ++static MV_BOOL twsiTimeoutChk(MV_U32 timeout, const MV_8 *pString) ++{ ++ if(timeout >= TWSI_TIMEOUT_VALUE) ++ { ++ DB(mvOsPrintf("%s",pString)); ++ return MV_TRUE; ++ } ++ return MV_FALSE; ++ ++} ++/******************************************************************************* ++* mvTwsiStartBitSet - Set start bit on the bus ++* ++* DESCRIPTION: ++* This routine sets the start bit on the TWSI bus. ++* The routine first checks for interrupt flag condition, then it sets ++* the start bit in the TWSI Control register. ++* If the interrupt flag condition check previously was set, the function ++* will clear it. ++* The function then wait for the start bit to be cleared by the HW. ++* Then it waits for the interrupt flag to be set and eventually, the ++* TWSI status is checked to be 0x8 or 0x10(repeated start bit). ++* ++* INPUT: ++* chanNum - TWSI channel. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_OK is start bit was set successfuly on the bus. ++* MV_FAIL if interrupt flag was set before setting start bit. ++* ++*******************************************************************************/ ++MV_STATUS mvTwsiStartBitSet(MV_U8 chanNum) ++{ ++ MV_BOOL isIntFlag = MV_FALSE; ++ MV_U32 timeout, temp; ++ ++ DB(mvOsPrintf("TWSI: mvTwsiStartBitSet \n")); ++ /* check Int flag */ ++ if(twsiMainIntGet(chanNum)) ++ isIntFlag = MV_TRUE; ++ /* set start Bit */ ++ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); ++ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp | TWSI_CONTROL_START_BIT); ++ ++ /* in case that the int flag was set before i.e. repeated start bit */ ++ if(isIntFlag){ ++ DB(mvOsPrintf("TWSI: mvTwsiStartBitSet repeated start Bit\n")); ++ twsiIntFlgClr(chanNum); ++ } ++ ++ /* wait for interrupt */ ++ timeout = 0; ++ while(!twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); ++ ++ /* check for timeout */ ++ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: mvTwsiStartBitSet ERROR - Start Clear bit TimeOut .\n")) ++ return MV_TIMEOUT; ++ ++ ++ /* check that start bit went down */ ++ if((MV_REG_READ(TWSI_CONTROL_REG(chanNum)) & TWSI_CONTROL_START_BIT) != 0) ++ { ++ mvOsPrintf("TWSI: mvTwsiStartBitSet ERROR - start bit didn't went down\n"); ++ return MV_FAIL; ++ } ++ ++ /* check the status */ ++ temp = twsiStsGet(chanNum); ++ if(( temp != TWSI_START_CON_TRA ) && ( temp != TWSI_REPEATED_START_CON_TRA )) ++ { ++ mvOsPrintf("TWSI: mvTwsiStartBitSet ERROR - status %x after Set Start Bit. \n",temp); ++ return MV_FAIL; ++ } ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvTwsiStopBitSet - Set stop bit on the bus ++* ++* DESCRIPTION: ++* This routine set the stop bit on the TWSI bus. ++* The function then wait for the stop bit to be cleared by the HW. ++* Finally the function checks for status of 0xF8. ++* ++* INPUT: ++* chanNum - TWSI channel ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE is stop bit was set successfuly on the bus. ++* ++*******************************************************************************/ ++MV_STATUS mvTwsiStopBitSet(MV_U8 chanNum) ++{ ++ MV_U32 timeout, temp; ++ ++ /* Generate stop bit */ ++ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); ++ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp | TWSI_CONTROL_STOP_BIT); ++ ++ twsiIntFlgClr(chanNum); ++ ++ /* wait for stop bit to come down */ ++ timeout = 0; ++ while( ((MV_REG_READ(TWSI_CONTROL_REG(chanNum)) & TWSI_CONTROL_STOP_BIT) != 0) && (timeout++ < TWSI_TIMEOUT_VALUE)); ++ ++ /* check for timeout */ ++ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: mvTwsiStopBitSet ERROR - Stop bit TimeOut .\n")) ++ return MV_TIMEOUT; ++ ++ /* check that the stop bit went down */ ++ if((MV_REG_READ(TWSI_CONTROL_REG(chanNum)) & TWSI_CONTROL_STOP_BIT) != 0) ++ { ++ mvOsPrintf("TWSI: mvTwsiStopBitSet ERROR - stop bit didn't went down. \n"); ++ return MV_FAIL; ++ } ++ ++ /* check the status */ ++ temp = twsiStsGet(chanNum); ++ if( temp != TWSI_NO_REL_STS_INT_FLAG_IS_KEPT_0){ ++ mvOsPrintf("TWSI: mvTwsiStopBitSet ERROR - status %x after Stop Bit. \n", temp); ++ return MV_FAIL; ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* twsiMainIntGet - Get twsi bit from main Interrupt cause. ++* ++* DESCRIPTION: ++* This routine returns the twsi interrupt flag value. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE is interrupt flag is set, MV_FALSE otherwise. ++* ++*******************************************************************************/ ++static MV_BOOL twsiMainIntGet(MV_U8 chanNum) ++{ ++ MV_U32 temp; ++ ++ /* get the int flag bit */ ++ ++ temp = MV_REG_READ(TWSI_CPU_MAIN_INT_CAUSE_REG); ++ if (temp & (TWSI0_CPU_MAIN_INT_BIT << chanNum)) ++ return MV_TRUE; ++ ++ return MV_FALSE; ++} ++/******************************************************************************* ++* twsiIntFlgClr - Clear Interrupt flag. ++* ++* DESCRIPTION: ++* This routine clears the interrupt flag. It does NOT poll the interrupt ++* to make sure the clear. After clearing the interrupt, it waits for at ++* least 1 miliseconds. ++* ++* INPUT: ++* chanNum - TWSI channel ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++static MV_VOID twsiIntFlgClr(MV_U8 chanNum) ++{ ++ MV_U32 temp; ++ ++ /* wait for 1 mili to prevent TWSI register write after write problems */ ++ mvOsDelay(1); ++ /* clear the int flag bit */ ++ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); ++ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum),temp & ~(TWSI_CONTROL_INT_FLAG_SET)); ++ ++ /* wait for 1 mili sec for the clear to take effect */ ++ mvOsDelay(1); ++ ++ return; ++} ++ ++ ++/******************************************************************************* ++* twsiAckBitSet - Set acknowledge bit on the bus ++* ++* DESCRIPTION: ++* This routine set the acknowledge bit on the TWSI bus. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++static MV_VOID twsiAckBitSet(MV_U8 chanNum) ++{ ++ MV_U32 temp; ++ ++ /*Set the Ack bit */ ++ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); ++ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp | TWSI_CONTROL_ACK); ++ ++ /* Add delay of 1ms */ ++ mvOsDelay(1); ++ return; ++} ++ ++ ++/******************************************************************************* ++* twsiInit - Initialize TWSI interface ++* ++* DESCRIPTION: ++* This routine: ++* -Reset the TWSI. ++* -Initialize the TWSI clock baud rate according to given frequancy ++* parameter based on Tclk frequancy and enables TWSI slave. ++* -Set the ack bit. ++* -Assign the TWSI slave address according to the TWSI address Type. ++* ++* ++* INPUT: ++* chanNum - TWSI channel ++* frequancy - TWSI frequancy in KHz. (up to 100KHZ) ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Actual frequancy. ++* ++*******************************************************************************/ ++MV_U32 mvTwsiInit(MV_U8 chanNum, MV_HZ frequancy, MV_U32 Tclk, MV_TWSI_ADDR *pTwsiAddr, MV_BOOL generalCallEnable) ++{ ++ MV_U32 n,m,freq,margin,minMargin = 0xffffffff; ++ MV_U32 power; ++ MV_U32 actualFreq = 0,actualN = 0,actualM = 0,val; ++ ++ if(frequancy > 100000) ++ { ++ mvOsPrintf("Warning TWSI frequancy is too high, please use up tp 100Khz. \n"); ++ } ++ ++ DB(mvOsPrintf("TWSI: mvTwsiInit - Tclk = %d freq = %d\n",Tclk,frequancy)); ++ /* Calucalte N and M for the TWSI clock baud rate */ ++ for(n = 0 ; n < 8 ; n++) ++ { ++ for(m = 0 ; m < 16 ; m++) ++ { ++ power = 2 << n; /* power = 2^(n+1) */ ++ freq = Tclk/(10*(m+1)*power); ++ margin = MV_ABS(frequancy - freq); ++ if(margin < minMargin) ++ { ++ minMargin = margin; ++ actualFreq = freq; ++ actualN = n; ++ actualM = m; ++ } ++ } ++ } ++ DB(mvOsPrintf("TWSI: mvTwsiInit - actN %d actM %d actFreq %d\n",actualN , actualM, actualFreq)); ++ /* Reset the TWSI logic */ ++ twsiReset(chanNum); ++ ++ /* Set the baud rate */ ++ val = ((actualM<< TWSI_BAUD_RATE_M_OFFS) | actualN << TWSI_BAUD_RATE_N_OFFS); ++ MV_REG_WRITE(TWSI_STATUS_BAUDE_RATE_REG(chanNum),val); ++ ++ /* Enable the TWSI and slave */ ++ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), TWSI_CONTROL_ENA | TWSI_CONTROL_ACK); ++ ++ /* set the TWSI slave address */ ++ if( pTwsiAddr->type == ADDR10_BIT )/* 10 Bit deviceAddress */ ++ { ++ /* writing the 2 most significant bits of the 10 bit address*/ ++ val = ((pTwsiAddr->address & TWSI_SLAVE_ADDR_10BIT_MASK) >> TWSI_SLAVE_ADDR_10BIT_OFFS ); ++ /* bits 7:3 must be 0x11110 */ ++ val |= TWSI_SLAVE_ADDR_10BIT_CONST; ++ /* set GCE bit */ ++ if(generalCallEnable) ++ val |= TWSI_SLAVE_ADDR_GCE_ENA; ++ /* write slave address */ ++ MV_REG_WRITE(TWSI_SLAVE_ADDR_REG(chanNum),val); ++ ++ /* writing the 8 least significant bits of the 10 bit address*/ ++ val = (pTwsiAddr->address << TWSI_EXTENDED_SLAVE_OFFS) & TWSI_EXTENDED_SLAVE_MASK; ++ MV_REG_WRITE(TWSI_EXTENDED_SLAVE_ADDR_REG(chanNum), val); ++ } ++ else /*7 bit address*/ ++ { ++ /* set the 7 Bits address */ ++ MV_REG_WRITE(TWSI_EXTENDED_SLAVE_ADDR_REG(chanNum),0x0); ++ val = (pTwsiAddr->address << TWSI_SLAVE_ADDR_7BIT_OFFS) & TWSI_SLAVE_ADDR_7BIT_MASK; ++ MV_REG_WRITE(TWSI_SLAVE_ADDR_REG(chanNum), val); ++ } ++ ++ /* unmask twsi int */ ++ val = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); ++ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), val | TWSI_CONTROL_INT_ENA); ++ /* Add delay of 1ms */ ++ mvOsDelay(1); ++ ++ return actualFreq; ++} ++ ++ ++/******************************************************************************* ++* twsiStsGet - Get the TWSI status value. ++* ++* DESCRIPTION: ++* This routine returns the TWSI status value. ++* ++* INPUT: ++* chanNum - TWSI channel ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_U32 - the TWSI status. ++* ++*******************************************************************************/ ++static MV_U32 twsiStsGet(MV_U8 chanNum) ++{ ++ return MV_REG_READ(TWSI_STATUS_BAUDE_RATE_REG(chanNum)); ++ ++} ++ ++/******************************************************************************* ++* twsiReset - Reset the TWSI. ++* ++* DESCRIPTION: ++* Resets the TWSI logic and sets all TWSI registers to their reset values. ++* ++* INPUT: ++* chanNum - TWSI channel ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None ++* ++*******************************************************************************/ ++static MV_VOID twsiReset(MV_U8 chanNum) ++{ ++ /* Reset the TWSI logic */ ++ MV_REG_WRITE(TWSI_SOFT_RESET_REG(chanNum),0); ++ ++ /* wait for 2 mili sec */ ++ mvOsDelay(2); ++ ++ return; ++} ++ ++ ++ ++ ++/******************************* POLICY ****************************************/ ++ ++ ++ ++/******************************************************************************* ++* mvTwsiAddrSet - Set address on TWSI bus. ++* ++* DESCRIPTION: ++* This function Set address (7 or 10 Bit address) on the Twsi Bus. ++* ++* INPUT: ++* chanNum - TWSI channel ++* pTwsiAddr - twsi address. ++* command - read / write . ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_OK - if setting the address completed succesfully. ++* MV_FAIL otherwmise. ++* ++*******************************************************************************/ ++MV_STATUS mvTwsiAddrSet(MV_U8 chanNum, MV_TWSI_ADDR *pTwsiAddr, MV_TWSI_CMD command) ++{ ++ DB(mvOsPrintf("TWSI: mvTwsiAddr7BitSet addr %x , type %d, cmd is %s\n",pTwsiAddr->address,\ ++ pTwsiAddr->type, ((command==MV_TWSI_WRITE)?"Write":"Read") )); ++ /* 10 Bit address */ ++ if(pTwsiAddr->type == ADDR10_BIT) ++ { ++ return twsiAddr10BitSet(chanNum, pTwsiAddr->address,command); ++ } ++ /* 7 Bit address */ ++ else ++ { ++ return twsiAddr7BitSet(chanNum, pTwsiAddr->address,command); ++ } ++ ++} ++ ++/******************************************************************************* ++* twsiAddr10BitSet - Set 10 Bit address on TWSI bus. ++* ++* DESCRIPTION: ++* There are two address phases: ++* 1) Write '11110' to data register bits [7:3] and 10-bit address MSB ++* (bits [9:8]) to data register bits [2:1] plus a write(0) or read(1) bit ++* to the Data register. Then it clears interrupt flag which drive ++* the address on the TWSI bus. The function then waits for interrupt ++* flag to be active and status 0x18 (write) or 0x40 (read) to be set. ++* 2) write the rest of 10-bit address to data register and clears ++* interrupt flag which drive the address on the TWSI bus. The ++* function then waits for interrupt flag to be active and status ++* 0xD0 (write) or 0xE0 (read) to be set. ++* ++* INPUT: ++* chanNum - TWSI channel ++* deviceAddress - twsi address. ++* command - read / write . ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_OK - if setting the address completed succesfully. ++* MV_FAIL otherwmise. ++* ++*******************************************************************************/ ++static MV_STATUS twsiAddr10BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command) ++{ ++ MV_U32 val,timeout; ++ ++ /* writing the 2 most significant bits of the 10 bit address*/ ++ val = ((deviceAddress & TWSI_DATA_ADDR_10BIT_MASK) >> TWSI_DATA_ADDR_10BIT_OFFS ); ++ /* bits 7:3 must be 0x11110 */ ++ val |= TWSI_DATA_ADDR_10BIT_CONST; ++ /* set command */ ++ val |= command; ++ MV_REG_WRITE(TWSI_DATA_REG(chanNum), val); ++ /* WA add a delay */ ++ mvOsDelay(1); ++ ++ /* clear Int flag */ ++ twsiIntFlgClr(chanNum); ++ ++ /* wait for Int to be Set */ ++ timeout = 0; ++ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); ++ ++ /* check for timeout */ ++ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiAddr10BitSet ERROR - 1st addr (10Bit) Int TimeOut.\n")) ++ return MV_TIMEOUT; ++ ++ /* check the status */ ++ val = twsiStsGet(chanNum); ++ if(( (val != TWSI_AD_PLS_RD_BIT_TRA_ACK_REC) && (command == MV_TWSI_READ ) ) || ++ ( (val != TWSI_AD_PLS_WR_BIT_TRA_ACK_REC) && (command == MV_TWSI_WRITE) )) ++ { ++ mvOsPrintf("TWSI: twsiAddr10BitSet ERROR - status %x 1st addr (10 Bit) in %s mode.\n"\ ++ ,val, ((command==MV_TWSI_WRITE)?"Write":"Read") ); ++ return MV_FAIL; ++ } ++ ++ /* set 8 LSB of the address */ ++ val = (deviceAddress << TWSI_DATA_ADDR_7BIT_OFFS) & TWSI_DATA_ADDR_7BIT_MASK; ++ MV_REG_WRITE(TWSI_DATA_REG(chanNum), val); ++ ++ /* clear Int flag */ ++ twsiIntFlgClr(chanNum); ++ ++ /* wait for Int to be Set */ ++ timeout = 0; ++ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); ++ ++ /* check for timeout */ ++ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiAddr10BitSet ERROR - 2nd (10 Bit) Int TimOut.\n")) ++ return MV_TIMEOUT; ++ ++ /* check the status */ ++ val = twsiStsGet(chanNum); ++ if(( (val != TWSI_SEC_AD_PLS_RD_BIT_TRA_ACK_REC) && (command == MV_TWSI_READ ) ) || ++ ( (val != TWSI_SEC_AD_PLS_WR_BIT_TRA_ACK_REC) && (command == MV_TWSI_WRITE) )) ++ { ++ mvOsPrintf("TWSI: twsiAddr10BitSet ERROR - status %x 2nd addr(10 Bit) in %s mode.\n"\ ++ ,val, ((command==MV_TWSI_WRITE)?"Write":"Read") ); ++ return MV_FAIL; ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* twsiAddr7BitSet - Set 7 Bit address on TWSI bus. ++* ++* DESCRIPTION: ++* This function writes 7 bit address plus a write or read bit to the ++* Data register. Then it clears interrupt flag which drive the address on ++* the TWSI bus. The function then waits for interrupt flag to be active ++* and status 0x18 (write) or 0x40 (read) to be set. ++* ++* INPUT: ++* chanNum - TWSI channel ++* deviceAddress - twsi address. ++* command - read / write . ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_OK - if setting the address completed succesfully. ++* MV_FAIL otherwmise. ++* ++*******************************************************************************/ ++static MV_STATUS twsiAddr7BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command) ++{ ++ MV_U32 val,timeout; ++ ++ /* set the address */ ++ val = (deviceAddress << TWSI_DATA_ADDR_7BIT_OFFS) & TWSI_DATA_ADDR_7BIT_MASK; ++ /* set command */ ++ val |= command; ++ MV_REG_WRITE(TWSI_DATA_REG(chanNum), val); ++ /* WA add a delay */ ++ mvOsDelay(1); ++ ++ /* clear Int flag */ ++ twsiIntFlgClr(chanNum); ++ ++ /* wait for Int to be Set */ ++ timeout = 0; ++ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); ++ ++ /* check for timeout */ ++ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiAddr7BitSet ERROR - Addr (7 Bit) int TimeOut.\n")) ++ return MV_TIMEOUT; ++ ++ /* check the status */ ++ val = twsiStsGet(chanNum); ++ if(( (val != TWSI_AD_PLS_RD_BIT_TRA_ACK_REC) && (command == MV_TWSI_READ ) ) || ++ ( (val != TWSI_AD_PLS_WR_BIT_TRA_ACK_REC) && (command == MV_TWSI_WRITE) )) ++ { ++ /* only in debug, since in boot we try to read the SPD of both DRAM, and we don't ++ want error messeges in case DIMM doesn't exist. */ ++ DB(mvOsPrintf("TWSI: twsiAddr7BitSet ERROR - status %x addr (7 Bit) in %s mode.\n"\ ++ ,val,((command==MV_TWSI_WRITE)?"Write":"Read") )); ++ return MV_FAIL; ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* twsiDataWrite - Trnasmit a data block over TWSI bus. ++* ++* DESCRIPTION: ++* This function writes a given data block to TWSI bus in 8 bit granularity. ++* first The function waits for interrupt flag to be active then ++* For each 8-bit data: ++* The function writes data to data register. It then clears ++* interrupt flag which drives the data on the TWSI bus. ++* The function then waits for interrupt flag to be active and status ++* 0x28 to be set. ++* ++* ++* INPUT: ++* chanNum - TWSI channel ++* pBlock - Data block. ++* blockSize - number of chars in pBlock. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_OK - if transmiting the block completed succesfully, ++* MV_BAD_PARAM - if pBlock is NULL, ++* MV_FAIL otherwmise. ++* ++*******************************************************************************/ ++static MV_STATUS twsiDataTransmit(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize) ++{ ++ MV_U32 timeout, temp, blockSizeWr = blockSize; ++ ++ if(NULL == pBlock) ++ return MV_BAD_PARAM; ++ ++ /* wait for Int to be Set */ ++ timeout = 0; ++ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); ++ ++ /* check for timeout */ ++ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataTransmit ERROR - Read Data Int TimeOut.\n")) ++ return MV_TIMEOUT; ++ ++ while(blockSizeWr) ++ { ++ /* write the data*/ ++ MV_REG_WRITE(TWSI_DATA_REG(chanNum),(MV_U32)*pBlock); ++ DB(mvOsPrintf("TWSI: twsiDataTransmit place = %d write %x \n",\ ++ blockSize - blockSizeWr, *pBlock)); ++ pBlock++; ++ blockSizeWr--; ++ ++ twsiIntFlgClr(chanNum); ++ ++ /* wait for Int to be Set */ ++ timeout = 0; ++ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); ++ ++ /* check for timeout */ ++ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataTransmit ERROR - Read Data Int TimeOut.\n")) ++ return MV_TIMEOUT; ++ ++ /* check the status */ ++ temp = twsiStsGet(chanNum); ++ if(temp != TWSI_M_TRAN_DATA_BYTE_ACK_REC) ++ { ++ mvOsPrintf("TWSI: twsiDataTransmit ERROR - status %x in write trans\n",temp); ++ return MV_FAIL; ++ } ++ ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* twsiDataReceive - Receive data block from TWSI bus. ++* ++* DESCRIPTION: ++* This function receive data block from TWSI bus in 8bit granularity ++* into pBlock buffer. ++* first The function waits for interrupt flag to be active then ++* For each 8-bit data: ++* It clears the interrupt flag which allows the next data to be ++* received from TWSI bus. ++* The function waits for interrupt flag to be active, ++* and status reg is 0x50. ++* Then the function reads data from data register, and copies it to ++* the given buffer. ++* ++* INPUT: ++* chanNum - TWSI channel ++* blockSize - number of bytes to read. ++* ++* OUTPUT: ++* pBlock - Data block. ++* ++* RETURN: ++* MV_OK - if receive transaction completed succesfully, ++* MV_BAD_PARAM - if pBlock is NULL, ++* MV_FAIL otherwmise. ++* ++*******************************************************************************/ ++static MV_STATUS twsiDataReceive(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize) ++{ ++ MV_U32 timeout, temp, blockSizeRd = blockSize; ++ if(NULL == pBlock) ++ return MV_BAD_PARAM; ++ ++ /* wait for Int to be Set */ ++ timeout = 0; ++ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); ++ ++ /* check for timeout */ ++ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataReceive ERROR - Read Data int Time out .\n")) ++ return MV_TIMEOUT; ++ ++ while(blockSizeRd) ++ { ++ if(blockSizeRd == 1) ++ { ++ /* clear ack and Int flag */ ++ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); ++ temp &= ~(TWSI_CONTROL_ACK); ++ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp); ++ } ++ twsiIntFlgClr(chanNum); ++ /* wait for Int to be Set */ ++ timeout = 0; ++ while( (!twsiMainIntGet(chanNum)) && (timeout++ < TWSI_TIMEOUT_VALUE)); ++ ++ /* check for timeout */ ++ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataReceive ERROR - Read Data Int Time out .\n")) ++ return MV_TIMEOUT; ++ ++ /* check the status */ ++ temp = twsiStsGet(chanNum); ++ if((temp != TWSI_M_REC_RD_DATA_ACK_TRA) && (blockSizeRd !=1)) ++ { ++ mvOsPrintf("TWSI: twsiDataReceive ERROR - status %x in read trans \n",temp); ++ return MV_FAIL; ++ } ++ else if((temp != TWSI_M_REC_RD_DATA_ACK_NOT_TRA) && (blockSizeRd ==1)) ++ { ++ mvOsPrintf("TWSI: twsiDataReceive ERROR - status %x in Rd Terminate\n",temp); ++ return MV_FAIL; ++ } ++ ++ /* read the data*/ ++ *pBlock = (MV_U8)MV_REG_READ(TWSI_DATA_REG(chanNum)); ++ DB(mvOsPrintf("TWSI: twsiDataReceive place %d read %x \n",\ ++ blockSize - blockSizeRd,*pBlock)); ++ pBlock++; ++ blockSizeRd--; ++ } ++ ++ return MV_OK; ++} ++ ++ ++ ++/******************************************************************************* ++* twsiTargetOffsSet - Set TWST target offset on TWSI bus. ++* ++* DESCRIPTION: ++* The function support TWSI targets that have inside address space (for ++* example EEPROMs). The function: ++* 1) Convert the given offset into pBlock and size. ++* in case the offset should be set to a TWSI slave which support ++* more then 256 bytes offset, the offset setting will be done ++* in 2 transactions. ++* 2) Use twsiDataTransmit to place those on the bus. ++* ++* INPUT: ++* chanNum - TWSI channel ++* offset - offset to be set on the EEPROM device. ++* moreThen256 - whether the EEPROM device support more then 256 byte offset. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_OK - if setting the offset completed succesfully. ++* MV_FAIL otherwmise. ++* ++*******************************************************************************/ ++static MV_STATUS twsiTargetOffsSet(MV_U8 chanNum, MV_U32 offset, MV_BOOL moreThen256) ++{ ++ MV_U8 offBlock[2]; ++ MV_U32 offSize; ++ ++ if(moreThen256 == MV_TRUE) ++ { ++ offBlock[0] = (offset >> 8) & 0xff; ++ offBlock[1] = offset & 0xff; ++ offSize = 2; ++ } ++ else ++ { ++ offBlock[0] = offset & 0xff; ++ offSize = 1; ++ } ++ DB(mvOsPrintf("TWSI: twsiTargetOffsSet offSize = %x addr1 = %x addr2 = %x\n",\ ++ offSize,offBlock[0],offBlock[1])); ++ return twsiDataTransmit(chanNum, offBlock, offSize); ++ ++} ++ ++/******************************************************************************* ++* mvTwsiRead - Read data block from a TWSI Slave. ++* ++* DESCRIPTION: ++* The function calls the following functions: ++* -) mvTwsiStartBitSet(); ++* if(EEPROM device) ++* -) mvTwsiAddrSet(w); ++* -) twsiTargetOffsSet(); ++* -) mvTwsiStartBitSet(); ++* -) mvTwsiAddrSet(r); ++* -) twsiDataReceive(); ++* -) mvTwsiStopBitSet(); ++* ++* INPUT: ++* chanNum - TWSI channel ++* pTwsiSlave - Twsi Slave structure. ++* blockSize - number of bytes to read. ++* ++* OUTPUT: ++* pBlock - Data block. ++* ++* RETURN: ++* MV_OK - if EEPROM read transaction completed succesfully, ++* MV_BAD_PARAM - if pBlock is NULL, ++* MV_FAIL otherwmise. ++* ++*******************************************************************************/ ++MV_STATUS mvTwsiRead(MV_U8 chanNum, MV_TWSI_SLAVE *pTwsiSlave, MV_U8 *pBlock, MV_U32 blockSize) ++{ ++ if((NULL == pBlock) || (NULL == pTwsiSlave)) ++ return MV_BAD_PARAM; ++ if(MV_OK != mvTwsiStartBitSet(chanNum)) ++ { ++ mvTwsiStopBitSet(chanNum); ++ return MV_FAIL; ++ } ++ ++ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiStartBitSet\n")); ++ ++ /* in case offset exsist (i.e. eeprom ) */ ++ if(MV_TRUE == pTwsiSlave->validOffset) ++ { ++ if(MV_OK != mvTwsiAddrSet(chanNum, &(pTwsiSlave->slaveAddr), MV_TWSI_WRITE)) ++ { ++ mvTwsiStopBitSet(chanNum); ++ return MV_FAIL; ++ } ++ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiAddrSet\n")); ++ if(MV_OK != twsiTargetOffsSet(chanNum, pTwsiSlave->offset, pTwsiSlave->moreThen256)) ++ { ++ mvTwsiStopBitSet(chanNum); ++ return MV_FAIL; ++ } ++ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after twsiTargetOffsSet\n")); ++ if(MV_OK != mvTwsiStartBitSet(chanNum)) ++ { ++ mvTwsiStopBitSet(chanNum); ++ return MV_FAIL; ++ } ++ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiStartBitSet\n")); ++ } ++ if(MV_OK != mvTwsiAddrSet(chanNum, &(pTwsiSlave->slaveAddr), MV_TWSI_READ)) ++ { ++ mvTwsiStopBitSet(chanNum); ++ return MV_FAIL; ++ } ++ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiAddrSet\n")); ++ if(MV_OK != twsiDataReceive(chanNum, pBlock, blockSize)) ++ { ++ mvTwsiStopBitSet(chanNum); ++ return MV_FAIL; ++ } ++ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after twsiDataReceive\n")); ++ ++ if(MV_OK != mvTwsiStopBitSet(chanNum)) ++ { ++ return MV_FAIL; ++ } ++ ++ twsiAckBitSet(chanNum); ++ ++ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiStopBitSet\n")); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvTwsiWrite - Write data block to a TWSI Slave. ++* ++* DESCRIPTION: ++* The function calls the following functions: ++* -) mvTwsiStartBitSet(); ++* -) mvTwsiAddrSet(); ++* -)if(EEPROM device) ++* -) twsiTargetOffsSet(); ++* -) twsiDataTransmit(); ++* -) mvTwsiStopBitSet(); ++* ++* INPUT: ++* chanNum - TWSI channel ++* eepromAddress - eeprom address. ++* blockSize - number of bytes to write. ++* pBlock - Data block. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* MV_OK - if EEPROM read transaction completed succesfully. ++* MV_BAD_PARAM - if pBlock is NULL, ++* MV_FAIL otherwmise. ++* ++* NOTE: Part of the EEPROM, required that the offset will be aligned to the ++* max write burst supported. ++*******************************************************************************/ ++MV_STATUS mvTwsiWrite(MV_U8 chanNum, MV_TWSI_SLAVE *pTwsiSlave, MV_U8 *pBlock, MV_U32 blockSize) ++{ ++ if((NULL == pBlock) || (NULL == pTwsiSlave)) ++ return MV_BAD_PARAM; ++ ++ if(MV_OK != mvTwsiStartBitSet(chanNum)) ++ { ++ mvTwsiStopBitSet(chanNum); ++ return MV_FAIL; ++ } ++ ++ DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after mvTwsiStartBitSet\n")); ++ if(MV_OK != mvTwsiAddrSet(chanNum, &(pTwsiSlave->slaveAddr), MV_TWSI_WRITE)) ++ { ++ mvTwsiStopBitSet(chanNum); ++ return MV_FAIL; ++ } ++ DB(mvOsPrintf("TWSI :mvTwsiEepromWrite after mvTwsiAddrSet\n")); ++ ++ /* in case offset exsist (i.e. eeprom ) */ ++ if(MV_TRUE == pTwsiSlave->validOffset) ++ { ++ if(MV_OK != twsiTargetOffsSet(chanNum, pTwsiSlave->offset, pTwsiSlave->moreThen256)) ++ { ++ mvTwsiStopBitSet(chanNum); ++ return MV_FAIL; ++ } ++ DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after twsiTargetOffsSet\n")); ++ } ++ if(MV_OK != twsiDataTransmit(chanNum, pBlock, blockSize)) ++ { ++ mvTwsiStopBitSet(chanNum); ++ return MV_FAIL; ++ } ++ DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after twsiDataTransmit\n")); ++ if(MV_OK != mvTwsiStopBitSet(chanNum)) ++ { ++ return MV_FAIL; ++ } ++ DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after mvTwsiStopBitSet\n")); ++ ++ return MV_OK; ++} +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,121 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++#ifndef __INCmvTwsiH ++#define __INCmvTwsiH ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++/* need to update this includes */ ++#include "twsi/mvTwsiSpec.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++ ++ ++/* The TWSI interface supports both 7-bit and 10-bit addressing. */ ++/* This enumerator describes addressing type. */ ++typedef enum _mvTwsiAddrType ++{ ++ ADDR7_BIT, /* 7 bit address */ ++ ADDR10_BIT /* 10 bit address */ ++}MV_TWSI_ADDR_TYPE; ++ ++/* This structure describes TWSI address. */ ++typedef struct _mvTwsiAddr ++{ ++ MV_U32 address; /* address */ ++ MV_TWSI_ADDR_TYPE type; /* Address type */ ++}MV_TWSI_ADDR; ++ ++/* This structure describes a TWSI slave. */ ++typedef struct _mvTwsiSlave ++{ ++ MV_TWSI_ADDR slaveAddr; ++ MV_BOOL validOffset; /* whether the slave has offset (i.e. Eeprom etc.) */ ++ MV_U32 offset; /* offset in the slave. */ ++ MV_BOOL moreThen256; /* whether the ofset is bigger then 256 */ ++}MV_TWSI_SLAVE; ++ ++/* This enumerator describes TWSI protocol commands. */ ++typedef enum _mvTwsiCmd ++{ ++ MV_TWSI_WRITE, /* TWSI write command - 0 according to spec */ ++ MV_TWSI_READ /* TWSI read command - 1 according to spec */ ++}MV_TWSI_CMD; ++ ++MV_STATUS mvTwsiStartBitSet(MV_U8 chanNum); ++MV_STATUS mvTwsiStopBitSet(MV_U8 chanNum); ++MV_STATUS mvTwsiAddrSet(MV_U8 chanNum, MV_TWSI_ADDR *twsiAddr, MV_TWSI_CMD command); ++ ++MV_U32 mvTwsiInit(MV_U8 chanNum, MV_KHZ frequancy, MV_U32 Tclk, MV_TWSI_ADDR *twsiAddr, MV_BOOL generalCallEnable); ++MV_STATUS mvTwsiRead (MV_U8 chanNum, MV_TWSI_SLAVE *twsiSlave, MV_U8 *pBlock, MV_U32 blockSize); ++MV_STATUS mvTwsiWrite(MV_U8 chanNum, MV_TWSI_SLAVE *twsiSlave, MV_U8 *pBlock, MV_U32 blockSize); ++ ++ ++#ifdef __cplusplus ++} ++#endif /* __cplusplus */ ++ ++#endif /* __INCmvTwsiH */ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiEeprom.S linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiEeprom.S +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiEeprom.S 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiEeprom.S 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,457 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++/* includes */ ++#define MV_ASMLANGUAGE ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++#include "boardEnv/mvBoardEnvSpec.h" ++#include "mvOsAsm.h" ++#include "mvTwsiSpec.h" ++#include "mvSysHwConfig.h" ++#include "ctrlEnv/sys/mvCpuIfRegs.h" ++#include "mvCommon.h" ++ ++#define I2C_CH MV_BOARD_DIMM_I2C_CHANNEL ++ ++/* defines */ ++/* defines */ ++ ++ ++ .data ++ .global _i2cInit ++ .global _i2cRead ++ ++ .text ++ ++/******************************************************************************* ++* _i2cInit - Initialize TWSI interface ++* ++* DESCRIPTION: ++* The function performs TWSI interface initialization. It resets the ++* TWSI state machine and initialize its clock to 100KHz assuming Tclock ++* of 133MHz. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++_i2cInit: ++ mov r9, LR /* Save link register */ ++ mov r0, #0 /* Make sure r0 is zero */ ++ ++ /* Reset the i2c Mechanism first */ ++ MV_REG_WRITE_ASM (r0, r1, TWSI_SOFT_RESET_REG(I2C_CH)) ++ ++ bl _twsiDelay ++ bl _twsiDelay ++ ++ /* Initializing the I2C mechanism. Assuming Tclock frequency */ ++ /* of 166MHz. The I2C frequency in that case will be 100KHz. */ ++ /* For this settings, M = 9 and N = 3. Set the baud-rate with the */ ++ /* value of 0x2b (freq of ==> 100KHz */ ++ /* see spec for more details about the calculation of this value) */ ++ mov r6, #(9 << 3 | 3) ++ MV_REG_WRITE_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) ++ ++ /* Enable the I2C master */ ++ /* Enable TWSI interrupt in main mask reg */ ++ mov r6, #0xC4 ++ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ ++ /* Let the slow TWSI machine get used to the idea that it is enabled */ ++ bl _twsiDelay ++ ++ ++ mov PC, r9 /* r9 is saved link register */ ++ ++/******************************************************************************* ++* _twsiDelay - Perform delay. ++* ++* DESCRIPTION: ++* The function performs a delay to enable TWSI logic to stable. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++_twsiDelay: ++ mov r10, #0x100000 /*was 0x400*/ ++ ++_twsiDelayLoop: ++ subs r10, r10, #1 ++ bne _twsiDelayLoop ++ ++ mov PC, LR ++ ++/******************************************************************************* ++* _i2cRead - Read byte from I2C EEPROM device. ++* ++* DESCRIPTION: ++* The function returns a byte from I2C EEPROM device. ++* The EEPROM device is 7-bit address type. ++* ++* INPUT: ++* r4 has the DIMM0 base address with shift 1 bit to the left ++* r7 has the EEPROM offset ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* r4 returns '0' if address can not be read. ++* r7 has byte value in case read is successful. ++* ++*******************************************************************************/ ++_i2cRead: ++ mov r9, LR /* Save link register */ ++ ++ /* Transmit the device address and desired offset within the EEPROM. */ ++ ++ /* Generate Start Bit */ ++ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ orr r6, r6, #TWSI_CONTROL_START_BIT ++ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ ++ /* Wait for the interrupt flag (bit3) to be set */ ++ mov r10, #0x50000 ++loop_1: ++ subs r10, r10, #1 ++ beq loop_1_timeout ++#ifdef MV78XX0 ++ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) ++ tst r6, #BIT2 ++#else ++ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) ++ tst r6, #BIT5 ++#endif ++ beq loop_1 ++ ++loop_1_timeout: ++ ++ /* Wait for the start bit to be reset by HW */ ++ mov r10, #0x50000 ++loop_2: ++ subs r10, r10, #1 ++ beq loop_2_timeout ++ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ tst r6, #TWSI_CONTROL_START_BIT ++ bne loop_2 ++ ++loop_2_timeout: ++ ++ /* Wait for the status TWSI_START_CONDITION_TRA = 0x8 */ ++ mov r10, #0x50000 ++loop_3: ++ subs r10, r10, #1 ++ beq loop_3_timeout ++ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) ++ cmp r6, #0x08 ++ bne loop_3 ++ ++loop_3_timeout: ++ ++ /* writing the address of (DIMM0/1 << 1) with write indication */ ++ mov r6, r4, LSL #1 /* Write operation address bit 0 must be 0 */ ++ MV_REG_WRITE_ASM (r6, r1, TWSI_DATA_REG(I2C_CH)) ++ ++ bl _twsiDelay ++ /* Clear the interrupt flag */ ++ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET ++ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ bl _twsiDelay ++ ++ /* Waiting for the interrupt flag to be set which means that the ++ address has been transmitted */ ++loop_4: ++#ifdef MV78XX0 ++ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) ++ tst r6, #BIT2 ++#else ++ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) ++ tst r6, #BIT5 ++#endif ++ beq loop_4 /* if tst = 0, then the bit is not set yet */ ++ ++ /* Wait for status TWSI_ADDR_PLUS_WRITE_BIT_TRA_ACK_REC = 0x18 */ ++ mov r10, #0x50000 /* Set r10 to 0x50000 =~ 328,000 */ ++ ++loop_5: ++ subs r10, r10, #1 /* timeout count down */ ++ bne testStatus ++ mov r4, #0 /* r4 = 0 -> operation failed */ ++ b exit_i2cRead /* Exit if timeout (No DIMM) */ ++ ++testStatus: ++ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) ++ cmp r6, #0x18 ++ bne loop_5 ++ ++ ++ /* check if the offset is bigger than 256 byte*/ ++ tst r7, #0x80000000 ++ bne great_than_256 ++ ++ /* Write the offset to be read from the DIMM EEPROM */ ++ MV_REG_WRITE_ASM (r7, r1, TWSI_DATA_REG(I2C_CH)) ++ ++ b after_offset ++ ++great_than_256: ++ mov r10, r7, LSR #8 ++ and r10, r10, #0xff ++ /* Write the offset0 to be read from the EEPROM */ ++ MV_REG_WRITE_ASM (r10, r1, TWSI_DATA_REG(I2C_CH)) ++ ++ /* Clear the interrupt flag ==> signaling that the address can now ++ be transmited */ ++ ++ bl _twsiDelay ++ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET ++ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ bl _twsiDelay ++ ++ /* Wait for the interrupt to be set again ==> address has transmited */ ++loop_6_1: ++#ifdef MV78XX0 ++ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) ++ tst r6, #BIT2 ++#else ++ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) ++ tst r6, #BIT5 ++#endif ++ beq loop_6_1 ++ ++ /* Wait for status TWSI_MAS_TRAN_DATA_BYTE_ACK_REC = 0x28 */ ++loop_7_1: ++ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) ++ cmp r6, #0x28 ++ bne loop_7_1 ++ ++ ++ mov r10, r7 ++ and r10, r10, #0xff ++ /* Write the offset1 to be read from the EEPROM */ ++ MV_REG_WRITE_ASM (r10, r1, TWSI_DATA_REG(I2C_CH)) ++ ++ ++ ++after_offset: ++ ++ /* Clear the interrupt flag ==> signaling that the address can now ++ be transmited */ ++ ++ bl _twsiDelay ++ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET ++ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ bl _twsiDelay ++ ++ /* Wait for the interrupt to be set again ==> address has transmited */ ++loop_6: ++#ifdef MV78XX0 ++ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) ++ tst r6, #BIT2 ++#else ++ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) ++ tst r6, #BIT5 ++#endif ++ beq loop_6 ++ ++ /* Wait for status TWSI_MAS_TRAN_DATA_BYTE_ACK_REC = 0x28 */ ++loop_7: ++ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) ++ cmp r6, #0x28 ++ bne loop_7 ++ ++ /* Retransmit the device address with read indication to get the data */ ++ ++ /* generate a repeated start bit */ ++ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ orr r6, r6, #TWSI_CONTROL_START_BIT ++ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ ++ ++ /* Clear the interrupt flag ==> the start bit will be transmitted. */ ++ bl _twsiDelay ++ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET ++ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ bl _twsiDelay ++ ++ /* Wait for the interrupt flag (bit3) to be set */ ++loop_9: ++#ifdef MV78XX0 ++ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) ++ tst r6, #BIT2 ++#else ++ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) ++ tst r6, #BIT5 ++#endif ++ beq loop_9 ++ ++ /* Wait for the start bit to be reset by HW */ ++loop_8: ++ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ tst r6, #TWSI_CONTROL_START_BIT ++ bne loop_8 ++ ++ /* Wait for status TWSI_REPEATED_START_CONDITION_TRA = 0x10 */ ++loop_10: ++ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) ++ cmp r6, #0x10 ++ bne loop_10 ++ ++ /* Writing the address of (DIMM0<<1) with read indication (bit0 is 1) */ ++ mov r6, r4, LSL #1 ++ orr r6, r6, #1 /* Read operation address bit 0 must be 1 */ ++ MV_REG_WRITE_ASM (r6, r1, TWSI_DATA_REG(I2C_CH)) ++ ++ /* Clear the interrupt flag ==> the address will be transmitted */ ++ bl _twsiDelay ++ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET ++ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ bl _twsiDelay ++ ++ /* Wait for the interrupt flag (bit3) to be set as a result of ++ transmitting the address. */ ++loop_11: ++#ifdef MV78XX0 ++ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) ++ tst r6, #BIT2 ++#else ++ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) ++ tst r6, #BIT5 ++#endif ++ beq loop_11 ++ ++ /* Wait for status TWSI_ADDR_PLUS_READ_BIT_TRA_ACK_REC = 0x40 */ ++loop_12: ++ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) ++ cmp r6, #0x40 ++ bne loop_12 ++ ++ /* Clear the interrupt flag and the Acknoledge bit */ ++ bl _twsiDelay ++ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ bic r6, r6, #(TWSI_CONTROL_INT_FLAG_SET | TWSI_CONTROL_ACK) ++ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ bl _twsiDelay ++ ++ /* Wait for the interrupt flag (bit3) to be set */ ++loop_14: ++#ifdef MV78XX0 ++ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) ++ tst r6, #BIT2 ++#else ++ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) ++ tst r6, #BIT5 ++#endif ++ beq loop_14 ++ ++ /* Wait for status TWSI_MAS_REC_READ_DATA_ACK_NOT_TRA = 0x58 */ ++loop_15: ++ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) ++ cmp r6, #0x58 ++ bne loop_15 ++ ++ /* Store the data in r7. */ ++ MV_REG_READ_ASM (r7, r1, TWSI_DATA_REG(I2C_CH)) ++ ++ /* Generate stop bit */ ++ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ orr r6, r6, #TWSI_CONTROL_STOP_BIT ++ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ ++ ++ /* Clear the interrupt flag */ ++ bl _twsiDelay ++ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET ++ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ bl _twsiDelay ++ ++ /* Wait for the stop bit to be reset by HW */ ++loop_16: ++ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ tst r6, #TWSI_CONTROL_INT_FLAG_SET ++ bne loop_16 ++ ++exit_i2cRead: ++ mov PC, r9 /* r9 is saved link register */ +diff -Nur linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiSpec.h linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiSpec.h +--- linux-3.0.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiSpec.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiSpec.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,160 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++/****************************************/ ++/* TWSI Registers */ ++/****************************************/ ++#ifndef __INCmvTwsiSpech ++#define __INCmvTwsiSpech ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++/* defines */ ++#define TWSI_SLAVE_ADDR_REG(chanNum) (TWSI_SLAVE_BASE(chanNum)+ 0x00) ++ ++#define TWSI_SLAVE_ADDR_GCE_ENA BIT0 ++#define TWSI_SLAVE_ADDR_7BIT_OFFS 0x1 ++#define TWSI_SLAVE_ADDR_7BIT_MASK (0xFF << TWSI_SLAVE_ADDR_7BIT_OFFS) ++#define TWSI_SLAVE_ADDR_10BIT_OFFS 0x7 ++#define TWSI_SLAVE_ADDR_10BIT_MASK 0x300 ++#define TWSI_SLAVE_ADDR_10BIT_CONST 0xF0 ++ ++ ++#define TWSI_EXTENDED_SLAVE_ADDR_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x10) ++#define TWSI_EXTENDED_SLAVE_OFFS 0 ++#define TWSI_EXTENDED_SLAVE_MASK (0xFF << TWSI_EXTENDED_SLAVE_OFFS) ++ ++ ++#define TWSI_DATA_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x04) ++#define TWSI_DATA_COMMAND_OFFS 0x0 ++#define TWSI_DATA_COMMAND_MASK (0x1 << TWSI_DATA_COMMAND_OFFS) ++#define TWSI_DATA_COMMAND_WR (0x1 << TWSI_DATA_COMMAND_OFFS) ++#define TWSI_DATA_COMMAND_RD (0x0 << TWSI_DATA_COMMAND_OFFS) ++#define TWSI_DATA_ADDR_7BIT_OFFS 0x1 ++#define TWSI_DATA_ADDR_7BIT_MASK (0xFF << TWSI_DATA_ADDR_7BIT_OFFS) ++#define TWSI_DATA_ADDR_10BIT_OFFS 0x7 ++#define TWSI_DATA_ADDR_10BIT_MASK 0x300 ++#define TWSI_DATA_ADDR_10BIT_CONST 0xF0 ++ ++ ++#define TWSI_CONTROL_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x08) ++#define TWSI_CONTROL_ACK BIT2 ++#define TWSI_CONTROL_INT_FLAG_SET BIT3 ++#define TWSI_CONTROL_STOP_BIT BIT4 ++#define TWSI_CONTROL_START_BIT BIT5 ++#define TWSI_CONTROL_ENA BIT6 ++#define TWSI_CONTROL_INT_ENA BIT7 ++ ++ ++#define TWSI_STATUS_BAUDE_RATE_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x0c) ++#define TWSI_BAUD_RATE_N_OFFS 0 ++#define TWSI_BAUD_RATE_N_MASK (0x7 << TWSI_BAUD_RATE_N_OFFS) ++#define TWSI_BAUD_RATE_M_OFFS 3 ++#define TWSI_BAUD_RATE_M_MASK (0xF << TWSI_BAUD_RATE_M_OFFS) ++ ++#define TWSI_SOFT_RESET_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x1c) ++ ++/* defines */ ++#define TWSI_TIMEOUT_VALUE 0x500 ++ ++/* TWSI status codes */ ++#define TWSI_BUS_ERROR 0x00 ++#define TWSI_START_CON_TRA 0x08 ++#define TWSI_REPEATED_START_CON_TRA 0x10 ++#define TWSI_AD_PLS_WR_BIT_TRA_ACK_REC 0x18 ++#define TWSI_AD_PLS_WR_BIT_TRA_ACK_NOT_REC 0x20 ++#define TWSI_M_TRAN_DATA_BYTE_ACK_REC 0x28 ++#define TWSI_M_TRAN_DATA_BYTE_ACK_NOT_REC 0x30 ++#define TWSI_M_LOST_ARB_DUR_AD_OR_DATA_TRA 0x38 ++#define TWSI_AD_PLS_RD_BIT_TRA_ACK_REC 0x40 ++#define TWSI_AD_PLS_RD_BIT_TRA_ACK_NOT_REC 0x48 ++#define TWSI_M_REC_RD_DATA_ACK_TRA 0x50 ++#define TWSI_M_REC_RD_DATA_ACK_NOT_TRA 0x58 ++#define TWSI_SLA_REC_AD_PLS_WR_BIT_ACK_TRA 0x60 ++#define TWSI_M_LOST_ARB_DUR_AD_TRA_AD_IS_TRGT_TO_SLA_ACK_TRA_W 0x68 ++#define TWSI_GNL_CALL_REC_ACK_TRA 0x70 ++#define TWSI_M_LOST_ARB_DUR_AD_TRA_GNL_CALL_AD_REC_ACK_TRA 0x78 ++#define TWSI_SLA_REC_WR_DATA_AF_REC_SLA_AD_ACK_TRAN 0x80 ++#define TWSI_SLA_REC_WR_DATA_AF_REC_SLA_AD_ACK_NOT_TRAN 0x88 ++#define TWSI_SLA_REC_WR_DATA_AF_REC_GNL_CALL_ACK_TRAN 0x90 ++#define TWSI_SLA_REC_WR_DATA_AF_REC_GNL_CALL_ACK_NOT_TRAN 0x98 ++#define TWSI_SLA_REC_STOP_OR_REPEATED_STRT_CON 0xA0 ++#define TWSI_SLA_REC_AD_PLS_RD_BIT_ACK_TRA 0xA8 ++#define TWSI_M_LOST_ARB_DUR_AD_TRA_AD_IS_TRGT_TO_SLA_ACK_TRA_R 0xB0 ++#define TWSI_SLA_TRA_RD_DATA_ACK_REC 0xB8 ++#define TWSI_SLA_TRA_RD_DATA_ACK_NOT_REC 0xC0 ++#define TWSI_SLA_TRA_LAST_RD_DATA_ACK_REC 0xC8 ++#define TWSI_SEC_AD_PLS_WR_BIT_TRA_ACK_REC 0xD0 ++#define TWSI_SEC_AD_PLS_WR_BIT_TRA_ACK_NOT_REC 0xD8 ++#define TWSI_SEC_AD_PLS_RD_BIT_TRA_ACK_REC 0xE0 ++#define TWSI_SEC_AD_PLS_RD_BIT_TRA_ACK_NOT_REC 0xE8 ++#define TWSI_NO_REL_STS_INT_FLAG_IS_KEPT_0 0xF8 ++ ++ ++#ifdef __cplusplus ++} ++#endif /* __cplusplus */ ++ ++#endif /* __INCmvTwsiSpech */ +diff -Nur linux-3.0.4.orig/crypto/ocf/ocf-bench.c linux-3.0.4/crypto/ocf/ocf-bench.c +--- linux-3.0.4.orig/crypto/ocf/ocf-bench.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/ocf-bench.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,514 @@ ++/* ++ * A loadable module that benchmarks the OCF crypto speed from kernel space. ++ * ++ * Copyright (C) 2004-2010 David McCullough ++ * ++ * LICENSE TERMS ++ * ++ * The free distribution and use of this software in both source and binary ++ * form is allowed (with or without changes) provided that: ++ * ++ * 1. distributions of this source code include the above copyright ++ * notice, this list of conditions and the following disclaimer; ++ * ++ * 2. distributions in binary form include the above copyright ++ * notice, this list of conditions and the following disclaimer ++ * in the documentation and/or other associated materials; ++ * ++ * 3. the copyright holder's name is not used to endorse products ++ * built using this software without specific written permission. ++ * ++ * ALTERNATIVELY, provided that this notice is retained in full, this product ++ * may be distributed under the terms of the GNU General Public License (GPL), ++ * in which case the provisions of the GPL apply INSTEAD OF those given above. ++ * ++ * DISCLAIMER ++ * ++ * This software is provided 'as is' with no explicit or implied warranties ++ * in respect of its properties, including, but not limited to, correctness ++ * and/or fitness for purpose. ++ */ ++ ++ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifdef I_HAVE_AN_XSCALE_WITH_INTEL_SDK ++#define BENCH_IXP_ACCESS_LIB 1 ++#endif ++#ifdef BENCH_IXP_ACCESS_LIB ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#endif ++ ++/* ++ * support for access lib version 1.4 ++ */ ++#ifndef IX_MBUF_PRIV ++#define IX_MBUF_PRIV(x) ((x)->priv) ++#endif ++ ++/* ++ * the number of simultaneously active requests ++ */ ++static int request_q_len = 40; ++module_param(request_q_len, int, 0); ++MODULE_PARM_DESC(request_q_len, "Number of outstanding requests"); ++ ++/* ++ * how many requests we want to have processed ++ */ ++static int request_num = 1024; ++module_param(request_num, int, 0); ++MODULE_PARM_DESC(request_num, "run for at least this many requests"); ++ ++/* ++ * the size of each request ++ */ ++static int request_size = 1488; ++module_param(request_size, int, 0); ++MODULE_PARM_DESC(request_size, "size of each request"); ++ ++/* ++ * OCF batching of requests ++ */ ++static int request_batch = 1; ++module_param(request_batch, int, 0); ++MODULE_PARM_DESC(request_batch, "enable OCF request batching"); ++ ++/* ++ * OCF immediate callback on completion ++ */ ++static int request_cbimm = 1; ++module_param(request_cbimm, int, 0); ++MODULE_PARM_DESC(request_cbimm, "enable OCF immediate callback on completion"); ++ ++/* ++ * a structure for each request ++ */ ++typedef struct { ++ struct work_struct work; ++#ifdef BENCH_IXP_ACCESS_LIB ++ IX_MBUF mbuf; ++#endif ++ unsigned char *buffer; ++} request_t; ++ ++static request_t *requests; ++ ++static spinlock_t ocfbench_counter_lock; ++static int outstanding; ++static int total; ++ ++/*************************************************************************/ ++/* ++ * OCF benchmark routines ++ */ ++ ++static uint64_t ocf_cryptoid; ++static unsigned long jstart, jstop; ++ ++static int ocf_init(void); ++static int ocf_cb(struct cryptop *crp); ++static void ocf_request(void *arg); ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++static void ocf_request_wq(struct work_struct *work); ++#endif ++ ++static int ++ocf_init(void) ++{ ++ int error; ++ struct cryptoini crie, cria; ++ struct cryptodesc crda, crde; ++ ++ memset(&crie, 0, sizeof(crie)); ++ memset(&cria, 0, sizeof(cria)); ++ memset(&crde, 0, sizeof(crde)); ++ memset(&crda, 0, sizeof(crda)); ++ ++ cria.cri_alg = CRYPTO_SHA1_HMAC; ++ cria.cri_klen = 20 * 8; ++ cria.cri_key = "0123456789abcdefghij"; ++ ++ //crie.cri_alg = CRYPTO_3DES_CBC; ++ crie.cri_alg = CRYPTO_AES_CBC; ++ crie.cri_klen = 24 * 8; ++ crie.cri_key = "0123456789abcdefghijklmn"; ++ ++ crie.cri_next = &cria; ++ ++ error = crypto_newsession(&ocf_cryptoid, &crie, ++ CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE); ++ if (error) { ++ printk("crypto_newsession failed %d\n", error); ++ return -1; ++ } ++ return 0; ++} ++ ++static int ++ocf_cb(struct cryptop *crp) ++{ ++ request_t *r = (request_t *) crp->crp_opaque; ++ unsigned long flags; ++ ++ if (crp->crp_etype) ++ printk("Error in OCF processing: %d\n", crp->crp_etype); ++ crypto_freereq(crp); ++ crp = NULL; ++ ++ /* do all requests but take at least 1 second */ ++ spin_lock_irqsave(&ocfbench_counter_lock, flags); ++ total++; ++ if (total > request_num && jstart + HZ < jiffies) { ++ outstanding--; ++ spin_unlock_irqrestore(&ocfbench_counter_lock, flags); ++ return 0; ++ } ++ spin_unlock_irqrestore(&ocfbench_counter_lock, flags); ++ ++ schedule_work(&r->work); ++ return 0; ++} ++ ++ ++static void ++ocf_request(void *arg) ++{ ++ request_t *r = arg; ++ struct cryptop *crp = crypto_getreq(2); ++ struct cryptodesc *crde, *crda; ++ unsigned long flags; ++ ++ if (!crp) { ++ spin_lock_irqsave(&ocfbench_counter_lock, flags); ++ outstanding--; ++ spin_unlock_irqrestore(&ocfbench_counter_lock, flags); ++ return; ++ } ++ ++ crde = crp->crp_desc; ++ crda = crde->crd_next; ++ ++ crda->crd_skip = 0; ++ crda->crd_flags = 0; ++ crda->crd_len = request_size; ++ crda->crd_inject = request_size; ++ crda->crd_alg = CRYPTO_SHA1_HMAC; ++ crda->crd_key = "0123456789abcdefghij"; ++ crda->crd_klen = 20 * 8; ++ ++ crde->crd_skip = 0; ++ crde->crd_flags = CRD_F_IV_EXPLICIT | CRD_F_ENCRYPT; ++ crde->crd_len = request_size; ++ crde->crd_inject = request_size; ++ //crde->crd_alg = CRYPTO_3DES_CBC; ++ crde->crd_alg = CRYPTO_AES_CBC; ++ crde->crd_key = "0123456789abcdefghijklmn"; ++ crde->crd_klen = 24 * 8; ++ ++ crp->crp_ilen = request_size + 64; ++ crp->crp_flags = 0; ++ if (request_batch) ++ crp->crp_flags |= CRYPTO_F_BATCH; ++ if (request_cbimm) ++ crp->crp_flags |= CRYPTO_F_CBIMM; ++ crp->crp_buf = (caddr_t) r->buffer; ++ crp->crp_callback = ocf_cb; ++ crp->crp_sid = ocf_cryptoid; ++ crp->crp_opaque = (caddr_t) r; ++ crypto_dispatch(crp); ++} ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++static void ++ocf_request_wq(struct work_struct *work) ++{ ++ request_t *r = container_of(work, request_t, work); ++ ocf_request(r); ++} ++#endif ++ ++static void ++ocf_done(void) ++{ ++ crypto_freesession(ocf_cryptoid); ++} ++ ++/*************************************************************************/ ++#ifdef BENCH_IXP_ACCESS_LIB ++/*************************************************************************/ ++/* ++ * CryptoAcc benchmark routines ++ */ ++ ++static IxCryptoAccCtx ixp_ctx; ++static UINT32 ixp_ctx_id; ++static IX_MBUF ixp_pri; ++static IX_MBUF ixp_sec; ++static int ixp_registered = 0; ++ ++static void ixp_register_cb(UINT32 ctx_id, IX_MBUF *bufp, ++ IxCryptoAccStatus status); ++static void ixp_perform_cb(UINT32 ctx_id, IX_MBUF *sbufp, IX_MBUF *dbufp, ++ IxCryptoAccStatus status); ++static void ixp_request(void *arg); ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++static void ixp_request_wq(struct work_struct *work); ++#endif ++ ++static int ++ixp_init(void) ++{ ++ IxCryptoAccStatus status; ++ ++ ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_3DES; ++ ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; ++ ixp_ctx.cipherCtx.cipherKeyLen = 24; ++ ixp_ctx.cipherCtx.cipherBlockLen = IX_CRYPTO_ACC_DES_BLOCK_64; ++ ixp_ctx.cipherCtx.cipherInitialVectorLen = IX_CRYPTO_ACC_DES_IV_64; ++ memcpy(ixp_ctx.cipherCtx.key.cipherKey, "0123456789abcdefghijklmn", 24); ++ ++ ixp_ctx.authCtx.authAlgo = IX_CRYPTO_ACC_AUTH_SHA1; ++ ixp_ctx.authCtx.authDigestLen = 12; ++ ixp_ctx.authCtx.aadLen = 0; ++ ixp_ctx.authCtx.authKeyLen = 20; ++ memcpy(ixp_ctx.authCtx.key.authKey, "0123456789abcdefghij", 20); ++ ++ ixp_ctx.useDifferentSrcAndDestMbufs = 0; ++ ixp_ctx.operation = IX_CRYPTO_ACC_OP_ENCRYPT_AUTH ; ++ ++ IX_MBUF_MLEN(&ixp_pri) = IX_MBUF_PKT_LEN(&ixp_pri) = 128; ++ IX_MBUF_MDATA(&ixp_pri) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); ++ IX_MBUF_MLEN(&ixp_sec) = IX_MBUF_PKT_LEN(&ixp_sec) = 128; ++ IX_MBUF_MDATA(&ixp_sec) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); ++ ++ status = ixCryptoAccCtxRegister(&ixp_ctx, &ixp_pri, &ixp_sec, ++ ixp_register_cb, ixp_perform_cb, &ixp_ctx_id); ++ ++ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) { ++ while (!ixp_registered) ++ schedule(); ++ return ixp_registered < 0 ? -1 : 0; ++ } ++ ++ printk("ixp: ixCryptoAccCtxRegister failed %d\n", status); ++ return -1; ++} ++ ++static void ++ixp_register_cb(UINT32 ctx_id, IX_MBUF *bufp, IxCryptoAccStatus status) ++{ ++ if (bufp) { ++ IX_MBUF_MLEN(bufp) = IX_MBUF_PKT_LEN(bufp) = 0; ++ kfree(IX_MBUF_MDATA(bufp)); ++ IX_MBUF_MDATA(bufp) = NULL; ++ } ++ ++ if (IX_CRYPTO_ACC_STATUS_WAIT == status) ++ return; ++ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) ++ ixp_registered = 1; ++ else ++ ixp_registered = -1; ++} ++ ++static void ++ixp_perform_cb( ++ UINT32 ctx_id, ++ IX_MBUF *sbufp, ++ IX_MBUF *dbufp, ++ IxCryptoAccStatus status) ++{ ++ request_t *r = NULL; ++ unsigned long flags; ++ ++ /* do all requests but take at least 1 second */ ++ spin_lock_irqsave(&ocfbench_counter_lock, flags); ++ total++; ++ if (total > request_num && jstart + HZ < jiffies) { ++ outstanding--; ++ spin_unlock_irqrestore(&ocfbench_counter_lock, flags); ++ return; ++ } ++ ++ if (!sbufp || !(r = IX_MBUF_PRIV(sbufp))) { ++ printk("crappo %p %p\n", sbufp, r); ++ outstanding--; ++ spin_unlock_irqrestore(&ocfbench_counter_lock, flags); ++ return; ++ } ++ spin_unlock_irqrestore(&ocfbench_counter_lock, flags); ++ ++ schedule_work(&r->work); ++} ++ ++static void ++ixp_request(void *arg) ++{ ++ request_t *r = arg; ++ IxCryptoAccStatus status; ++ unsigned long flags; ++ ++ memset(&r->mbuf, 0, sizeof(r->mbuf)); ++ IX_MBUF_MLEN(&r->mbuf) = IX_MBUF_PKT_LEN(&r->mbuf) = request_size + 64; ++ IX_MBUF_MDATA(&r->mbuf) = r->buffer; ++ IX_MBUF_PRIV(&r->mbuf) = r; ++ status = ixCryptoAccAuthCryptPerform(ixp_ctx_id, &r->mbuf, NULL, ++ 0, request_size, 0, request_size, request_size, r->buffer); ++ if (IX_CRYPTO_ACC_STATUS_SUCCESS != status) { ++ printk("status1 = %d\n", status); ++ spin_lock_irqsave(&ocfbench_counter_lock, flags); ++ outstanding--; ++ spin_unlock_irqrestore(&ocfbench_counter_lock, flags); ++ return; ++ } ++ return; ++} ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++static void ++ixp_request_wq(struct work_struct *work) ++{ ++ request_t *r = container_of(work, request_t, work); ++ ixp_request(r); ++} ++#endif ++ ++static void ++ixp_done(void) ++{ ++ /* we should free the session here but I am lazy :-) */ ++} ++ ++/*************************************************************************/ ++#endif /* BENCH_IXP_ACCESS_LIB */ ++/*************************************************************************/ ++ ++int ++ocfbench_init(void) ++{ ++ int i; ++ unsigned long mbps; ++ unsigned long flags; ++ ++ printk("Crypto Speed tests\n"); ++ ++ requests = kmalloc(sizeof(request_t) * request_q_len, GFP_KERNEL); ++ if (!requests) { ++ printk("malloc failed\n"); ++ return -EINVAL; ++ } ++ ++ for (i = 0; i < request_q_len; i++) { ++ /* +64 for return data */ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++ INIT_WORK(&requests[i].work, ocf_request_wq); ++#else ++ INIT_WORK(&requests[i].work, ocf_request, &requests[i]); ++#endif ++ requests[i].buffer = kmalloc(request_size + 128, GFP_DMA); ++ if (!requests[i].buffer) { ++ printk("malloc failed\n"); ++ return -EINVAL; ++ } ++ memset(requests[i].buffer, '0' + i, request_size + 128); ++ } ++ ++ /* ++ * OCF benchmark ++ */ ++ printk("OCF: testing ...\n"); ++ if (ocf_init() == -1) ++ return -EINVAL; ++ ++ spin_lock_init(&ocfbench_counter_lock); ++ total = outstanding = 0; ++ jstart = jiffies; ++ for (i = 0; i < request_q_len; i++) { ++ spin_lock_irqsave(&ocfbench_counter_lock, flags); ++ outstanding++; ++ spin_unlock_irqrestore(&ocfbench_counter_lock, flags); ++ ocf_request(&requests[i]); ++ } ++ while (outstanding > 0) ++ schedule(); ++ jstop = jiffies; ++ ++ mbps = 0; ++ if (jstop > jstart) { ++ mbps = (unsigned long) total * (unsigned long) request_size * 8; ++ mbps /= ((jstop - jstart) * 1000) / HZ; ++ } ++ printk("OCF: %d requests of %d bytes in %d jiffies (%d.%03d Mbps)\n", ++ total, request_size, (int)(jstop - jstart), ++ ((int)mbps) / 1000, ((int)mbps) % 1000); ++ ocf_done(); ++ ++#ifdef BENCH_IXP_ACCESS_LIB ++ /* ++ * IXP benchmark ++ */ ++ printk("IXP: testing ...\n"); ++ ixp_init(); ++ total = outstanding = 0; ++ jstart = jiffies; ++ for (i = 0; i < request_q_len; i++) { ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++ INIT_WORK(&requests[i].work, ixp_request_wq); ++#else ++ INIT_WORK(&requests[i].work, ixp_request, &requests[i]); ++#endif ++ spin_lock_irqsave(&ocfbench_counter_lock, flags); ++ outstanding++; ++ spin_unlock_irqrestore(&ocfbench_counter_lock, flags); ++ ixp_request(&requests[i]); ++ } ++ while (outstanding > 0) ++ schedule(); ++ jstop = jiffies; ++ ++ mbps = 0; ++ if (jstop > jstart) { ++ mbps = (unsigned long) total * (unsigned long) request_size * 8; ++ mbps /= ((jstop - jstart) * 1000) / HZ; ++ } ++ printk("IXP: %d requests of %d bytes in %d jiffies (%d.%03d Mbps)\n", ++ total, request_size, jstop - jstart, ++ ((int)mbps) / 1000, ((int)mbps) % 1000); ++ ixp_done(); ++#endif /* BENCH_IXP_ACCESS_LIB */ ++ ++ for (i = 0; i < request_q_len; i++) ++ kfree(requests[i].buffer); ++ kfree(requests); ++ return -EINVAL; /* always fail to load so it can be re-run quickly ;-) */ ++} ++ ++static void __exit ocfbench_exit(void) ++{ ++} ++ ++module_init(ocfbench_init); ++module_exit(ocfbench_exit); ++ ++MODULE_LICENSE("BSD"); ++MODULE_AUTHOR("David McCullough "); ++MODULE_DESCRIPTION("Benchmark various in-kernel crypto speeds"); +diff -Nur linux-3.0.4.orig/crypto/ocf/ocf-compat.h linux-3.0.4/crypto/ocf/ocf-compat.h +--- linux-3.0.4.orig/crypto/ocf/ocf-compat.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/ocf-compat.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,365 @@ ++#ifndef _BSD_COMPAT_H_ ++#define _BSD_COMPAT_H_ 1 ++/****************************************************************************/ ++/* ++ * Provide compat routines for older linux kernels and BSD kernels ++ * ++ * Written by David McCullough ++ * Copyright (C) 2010 David McCullough ++ * ++ * LICENSE TERMS ++ * ++ * The free distribution and use of this software in both source and binary ++ * form is allowed (with or without changes) provided that: ++ * ++ * 1. distributions of this source code include the above copyright ++ * notice, this list of conditions and the following disclaimer; ++ * ++ * 2. distributions in binary form include the above copyright ++ * notice, this list of conditions and the following disclaimer ++ * in the documentation and/or other associated materials; ++ * ++ * 3. the copyright holder's name is not used to endorse products ++ * built using this software without specific written permission. ++ * ++ * ALTERNATIVELY, provided that this notice is retained in full, this file ++ * may be distributed under the terms of the GNU General Public License (GPL), ++ * in which case the provisions of the GPL apply INSTEAD OF those given above. ++ * ++ * DISCLAIMER ++ * ++ * This software is provided 'as is' with no explicit or implied warranties ++ * in respect of its properties, including, but not limited to, correctness ++ * and/or fitness for purpose. ++ */ ++/****************************************************************************/ ++#ifdef __KERNEL__ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++ ++/* ++ * fake some BSD driver interface stuff specifically for OCF use ++ */ ++ ++typedef struct ocf_device *device_t; ++ ++typedef struct { ++ int (*cryptodev_newsession)(device_t dev, u_int32_t *sidp, struct cryptoini *cri); ++ int (*cryptodev_freesession)(device_t dev, u_int64_t tid); ++ int (*cryptodev_process)(device_t dev, struct cryptop *crp, int hint); ++ int (*cryptodev_kprocess)(device_t dev, struct cryptkop *krp, int hint); ++} device_method_t; ++#define DEVMETHOD(id, func) id: func ++ ++struct ocf_device { ++ char name[32]; /* the driver name */ ++ char nameunit[32]; /* the driver name + HW instance */ ++ int unit; ++ device_method_t methods; ++ void *softc; ++}; ++ ++#define CRYPTODEV_NEWSESSION(dev, sid, cri) \ ++ ((*(dev)->methods.cryptodev_newsession)(dev,sid,cri)) ++#define CRYPTODEV_FREESESSION(dev, sid) \ ++ ((*(dev)->methods.cryptodev_freesession)(dev, sid)) ++#define CRYPTODEV_PROCESS(dev, crp, hint) \ ++ ((*(dev)->methods.cryptodev_process)(dev, crp, hint)) ++#define CRYPTODEV_KPROCESS(dev, krp, hint) \ ++ ((*(dev)->methods.cryptodev_kprocess)(dev, krp, hint)) ++ ++#define device_get_name(dev) ((dev)->name) ++#define device_get_nameunit(dev) ((dev)->nameunit) ++#define device_get_unit(dev) ((dev)->unit) ++#define device_get_softc(dev) ((dev)->softc) ++ ++#define softc_device_decl \ ++ struct ocf_device _device; \ ++ device_t ++ ++#define softc_device_init(_sc, _name, _unit, _methods) \ ++ if (1) {\ ++ strncpy((_sc)->_device.name, _name, sizeof((_sc)->_device.name) - 1); \ ++ snprintf((_sc)->_device.nameunit, sizeof((_sc)->_device.name), "%s%d", _name, _unit); \ ++ (_sc)->_device.unit = _unit; \ ++ (_sc)->_device.methods = _methods; \ ++ (_sc)->_device.softc = (void *) _sc; \ ++ *(device_t *)((softc_get_device(_sc))+1) = &(_sc)->_device; \ ++ } else ++ ++#define softc_get_device(_sc) (&(_sc)->_device) ++ ++/* ++ * iomem support for 2.4 and 2.6 kernels ++ */ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++#define ocf_iomem_t unsigned long ++ ++/* ++ * implement simple workqueue like support for older kernels ++ */ ++ ++#include ++ ++#define work_struct tq_struct ++ ++#define INIT_WORK(wp, fp, ap) \ ++ do { \ ++ (wp)->sync = 0; \ ++ (wp)->routine = (fp); \ ++ (wp)->data = (ap); \ ++ } while (0) ++ ++#define schedule_work(wp) \ ++ do { \ ++ queue_task((wp), &tq_immediate); \ ++ mark_bh(IMMEDIATE_BH); \ ++ } while (0) ++ ++#define flush_scheduled_work() run_task_queue(&tq_immediate) ++ ++#else ++#define ocf_iomem_t void __iomem * ++ ++#include ++ ++#endif ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26) ++#include ++#elif LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) ++#define files_fdtable(files) (files) ++#endif ++ ++#ifdef MODULE_PARM ++#undef module_param /* just in case */ ++#define module_param(a,b,c) MODULE_PARM(a,"i") ++#endif ++ ++#define bzero(s,l) memset(s,0,l) ++#define bcopy(s,d,l) memcpy(d,s,l) ++#define bcmp(x, y, l) memcmp(x,y,l) ++ ++#define MIN(x,y) ((x) < (y) ? (x) : (y)) ++ ++#define device_printf(dev, a...) ({ \ ++ printk("%s: ", device_get_nameunit(dev)); printk(a); \ ++ }) ++ ++#undef printf ++#define printf(fmt...) printk(fmt) ++ ++#define KASSERT(c,p) if (!(c)) { printk p ; } else ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++#define ocf_daemonize(str) \ ++ daemonize(); \ ++ spin_lock_irq(¤t->sigmask_lock); \ ++ sigemptyset(¤t->blocked); \ ++ recalc_sigpending(current); \ ++ spin_unlock_irq(¤t->sigmask_lock); \ ++ sprintf(current->comm, str); ++#else ++#define ocf_daemonize(str) daemonize(str); ++#endif ++ ++#define TAILQ_INSERT_TAIL(q,d,m) list_add_tail(&(d)->m, (q)) ++#define TAILQ_EMPTY(q) list_empty(q) ++#define TAILQ_FOREACH(v, q, m) list_for_each_entry(v, q, m) ++ ++#define read_random(p,l) get_random_bytes(p,l) ++ ++#define DELAY(x) ((x) > 2000 ? mdelay((x)/1000) : udelay(x)) ++#define strtoul simple_strtoul ++ ++#define pci_get_vendor(dev) ((dev)->vendor) ++#define pci_get_device(dev) ((dev)->device) ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++#define pci_set_consistent_dma_mask(dev, mask) (0) ++#endif ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10) ++#define pci_dma_sync_single_for_cpu pci_dma_sync_single ++#endif ++ ++#ifndef DMA_32BIT_MASK ++#define DMA_32BIT_MASK 0x00000000ffffffffULL ++#endif ++ ++#ifndef htole32 ++#define htole32(x) cpu_to_le32(x) ++#endif ++#ifndef htobe32 ++#define htobe32(x) cpu_to_be32(x) ++#endif ++#ifndef htole16 ++#define htole16(x) cpu_to_le16(x) ++#endif ++#ifndef htobe16 ++#define htobe16(x) cpu_to_be16(x) ++#endif ++ ++/* older kernels don't have these */ ++ ++#include ++#if !defined(IRQ_NONE) && !defined(IRQ_RETVAL) ++#define IRQ_NONE ++#define IRQ_HANDLED ++#define IRQ_WAKE_THREAD ++#define IRQ_RETVAL ++#define irqreturn_t void ++typedef irqreturn_t (*irq_handler_t)(int irq, void *arg, struct pt_regs *regs); ++#endif ++#ifndef IRQF_SHARED ++#define IRQF_SHARED SA_SHIRQ ++#endif ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) ++# define strlcpy(dest,src,len) \ ++ ({strncpy(dest,src,(len)-1); ((char *)dest)[(len)-1] = '\0'; }) ++#endif ++ ++#ifndef MAX_ERRNO ++#define MAX_ERRNO 4095 ++#endif ++#ifndef IS_ERR_VALUE ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,5) ++#include ++#endif ++#ifndef IS_ERR_VALUE ++#define IS_ERR_VALUE(x) ((unsigned long)(x) >= (unsigned long)-MAX_ERRNO) ++#endif ++#endif ++ ++/* ++ * common debug for all ++ */ ++#if 1 ++#define dprintk(a...) do { if (debug) printk(a); } while(0) ++#else ++#define dprintk(a...) ++#endif ++ ++#ifndef SLAB_ATOMIC ++/* Changed in 2.6.20, must use GFP_ATOMIC now */ ++#define SLAB_ATOMIC GFP_ATOMIC ++#endif ++ ++/* ++ * need some additional support for older kernels */ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,2) ++#define pci_register_driver_compat(driver, rc) \ ++ do { \ ++ if ((rc) > 0) { \ ++ (rc) = 0; \ ++ } else if (rc == 0) { \ ++ (rc) = -ENODEV; \ ++ } else { \ ++ pci_unregister_driver(driver); \ ++ } \ ++ } while (0) ++#elif LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10) ++#define pci_register_driver_compat(driver,rc) ((rc) = (rc) < 0 ? (rc) : 0) ++#else ++#define pci_register_driver_compat(driver,rc) ++#endif ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) ++ ++#include ++#include ++ ++static inline void sg_set_page(struct scatterlist *sg, struct page *page, ++ unsigned int len, unsigned int offset) ++{ ++ sg->page = page; ++ sg->offset = offset; ++ sg->length = len; ++} ++ ++static inline void *sg_virt(struct scatterlist *sg) ++{ ++ return page_address(sg->page) + sg->offset; ++} ++ ++#define sg_init_table(sg, n) ++ ++#endif ++ ++#ifndef late_initcall ++#define late_initcall(init) module_init(init) ++#endif ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,4) || !defined(CONFIG_SMP) ++#define ocf_for_each_cpu(cpu) for ((cpu) = 0; (cpu) == 0; (cpu)++) ++#else ++#define ocf_for_each_cpu(cpu) for_each_present_cpu(cpu) ++#endif ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) ++#include ++#define kill_proc(p,s,v) send_sig(s,find_task_by_vpid(p),0) ++#endif ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,4) ++ ++struct ocf_thread { ++ struct task_struct *task; ++ int (*func)(void *arg); ++ void *arg; ++}; ++ ++/* thread startup helper func */ ++static inline int ocf_run_thread(void *arg) ++{ ++ struct ocf_thread *t = (struct ocf_thread *) arg; ++ if (!t) ++ return -1; /* very bad */ ++ t->task = current; ++ daemonize(); ++ spin_lock_irq(¤t->sigmask_lock); ++ sigemptyset(¤t->blocked); ++ recalc_sigpending(current); ++ spin_unlock_irq(¤t->sigmask_lock); ++ return (*t->func)(t->arg); ++} ++ ++#define kthread_create(f,a,fmt...) \ ++ ({ \ ++ struct ocf_thread t; \ ++ pid_t p; \ ++ t.task = NULL; \ ++ t.func = (f); \ ++ t.arg = (a); \ ++ p = kernel_thread(ocf_run_thread, &t, CLONE_FS|CLONE_FILES); \ ++ while (p != (pid_t) -1 && t.task == NULL) \ ++ schedule(); \ ++ if (t.task) \ ++ snprintf(t.task->comm, sizeof(t.task->comm), fmt); \ ++ (t.task); \ ++ }) ++ ++#define kthread_bind(t,cpu) /**/ ++ ++#define kthread_should_stop() (strcmp(current->comm, "stopping") == 0) ++ ++#define kthread_stop(t) \ ++ ({ \ ++ strcpy((t)->comm, "stopping"); \ ++ kill_proc((t)->pid, SIGTERM, 1); \ ++ do { \ ++ schedule(); \ ++ } while (kill_proc((t)->pid, SIGTERM, 1) == 0); \ ++ }) ++ ++#else ++#include ++#endif ++ ++#endif /* __KERNEL__ */ ++ ++/****************************************************************************/ ++#endif /* _BSD_COMPAT_H_ */ +diff -Nur linux-3.0.4.orig/crypto/ocf/ocfnull/Makefile linux-3.0.4/crypto/ocf/ocfnull/Makefile +--- linux-3.0.4.orig/crypto/ocf/ocfnull/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/ocfnull/Makefile 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,12 @@ ++# for SGlinux builds ++-include $(ROOTDIR)/modules/.config ++ ++obj-$(CONFIG_OCF_OCFNULL) += ocfnull.o ++ ++obj ?= . ++EXTRA_CFLAGS += -I$(obj)/.. ++ ++ifdef TOPDIR ++-include $(TOPDIR)/Rules.make ++endif ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/ocfnull/ocfnull.c linux-3.0.4/crypto/ocf/ocfnull/ocfnull.c +--- linux-3.0.4.orig/crypto/ocf/ocfnull/ocfnull.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/ocfnull/ocfnull.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,204 @@ ++/* ++ * An OCF module for determining the cost of crypto versus the cost of ++ * IPSec processing outside of OCF. This modules gives us the effect of ++ * zero cost encryption, of course you will need to run it at both ends ++ * since it does no crypto at all. ++ * ++ * Written by David McCullough ++ * Copyright (C) 2006-2010 David McCullough ++ * ++ * LICENSE TERMS ++ * ++ * The free distribution and use of this software in both source and binary ++ * form is allowed (with or without changes) provided that: ++ * ++ * 1. distributions of this source code include the above copyright ++ * notice, this list of conditions and the following disclaimer; ++ * ++ * 2. distributions in binary form include the above copyright ++ * notice, this list of conditions and the following disclaimer ++ * in the documentation and/or other associated materials; ++ * ++ * 3. the copyright holder's name is not used to endorse products ++ * built using this software without specific written permission. ++ * ++ * ALTERNATIVELY, provided that this notice is retained in full, this product ++ * may be distributed under the terms of the GNU General Public License (GPL), ++ * in which case the provisions of the GPL apply INSTEAD OF those given above. ++ * ++ * DISCLAIMER ++ * ++ * This software is provided 'as is' with no explicit or implied warranties ++ * in respect of its properties, including, but not limited to, correctness ++ * and/or fitness for purpose. ++ */ ++ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++static int32_t null_id = -1; ++static u_int32_t null_sesnum = 0; ++ ++static int null_process(device_t, struct cryptop *, int); ++static int null_newsession(device_t, u_int32_t *, struct cryptoini *); ++static int null_freesession(device_t, u_int64_t); ++ ++#define debug ocfnull_debug ++int ocfnull_debug = 0; ++module_param(ocfnull_debug, int, 0644); ++MODULE_PARM_DESC(ocfnull_debug, "Enable debug"); ++ ++/* ++ * dummy device structure ++ */ ++ ++static struct { ++ softc_device_decl sc_dev; ++} nulldev; ++ ++static device_method_t null_methods = { ++ /* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, null_newsession), ++ DEVMETHOD(cryptodev_freesession,null_freesession), ++ DEVMETHOD(cryptodev_process, null_process), ++}; ++ ++/* ++ * Generate a new software session. ++ */ ++static int ++null_newsession(device_t arg, u_int32_t *sid, struct cryptoini *cri) ++{ ++ dprintk("%s()\n", __FUNCTION__); ++ if (sid == NULL || cri == NULL) { ++ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ if (null_sesnum == 0) ++ null_sesnum++; ++ *sid = null_sesnum++; ++ return 0; ++} ++ ++ ++/* ++ * Free a session. ++ */ ++static int ++null_freesession(device_t arg, u_int64_t tid) ++{ ++ u_int32_t sid = CRYPTO_SESID2LID(tid); ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (sid > null_sesnum) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ /* Silently accept and return */ ++ if (sid == 0) ++ return 0; ++ return 0; ++} ++ ++ ++/* ++ * Process a request. ++ */ ++static int ++null_process(device_t arg, struct cryptop *crp, int hint) ++{ ++ unsigned int lid; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ /* Sanity check */ ++ if (crp == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ crp->crp_etype = 0; ++ ++ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ crp->crp_etype = EINVAL; ++ goto done; ++ } ++ ++ /* ++ * find the session we are using ++ */ ++ ++ lid = crp->crp_sid & 0xffffffff; ++ if (lid >= null_sesnum || lid == 0) { ++ crp->crp_etype = ENOENT; ++ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); ++ goto done; ++ } ++ ++done: ++ crypto_done(crp); ++ return 0; ++} ++ ++ ++/* ++ * our driver startup and shutdown routines ++ */ ++ ++static int ++null_init(void) ++{ ++ dprintk("%s(%p)\n", __FUNCTION__, null_init); ++ ++ memset(&nulldev, 0, sizeof(nulldev)); ++ softc_device_init(&nulldev, "ocfnull", 0, null_methods); ++ ++ null_id = crypto_get_driverid(softc_get_device(&nulldev), ++ CRYPTOCAP_F_HARDWARE); ++ if (null_id < 0) ++ panic("ocfnull: crypto device cannot initialize!"); ++ ++#define REGISTER(alg) \ ++ crypto_register(null_id,alg,0,0) ++ REGISTER(CRYPTO_DES_CBC); ++ REGISTER(CRYPTO_3DES_CBC); ++ REGISTER(CRYPTO_RIJNDAEL128_CBC); ++ REGISTER(CRYPTO_MD5); ++ REGISTER(CRYPTO_SHA1); ++ REGISTER(CRYPTO_MD5_HMAC); ++ REGISTER(CRYPTO_SHA1_HMAC); ++#undef REGISTER ++ ++ return 0; ++} ++ ++static void ++null_exit(void) ++{ ++ dprintk("%s()\n", __FUNCTION__); ++ crypto_unregister_all(null_id); ++ null_id = -1; ++} ++ ++module_init(null_init); ++module_exit(null_exit); ++ ++MODULE_LICENSE("Dual BSD/GPL"); ++MODULE_AUTHOR("David McCullough "); ++MODULE_DESCRIPTION("ocfnull - claims a lot but does nothing"); +diff -Nur linux-3.0.4.orig/crypto/ocf/pasemi/Makefile linux-3.0.4/crypto/ocf/pasemi/Makefile +--- linux-3.0.4.orig/crypto/ocf/pasemi/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/pasemi/Makefile 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,12 @@ ++# for SGlinux builds ++-include $(ROOTDIR)/modules/.config ++ ++obj-$(CONFIG_OCF_PASEMI) += pasemi.o ++ ++obj ?= . ++EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ ++ ++ifdef TOPDIR ++-include $(TOPDIR)/Rules.make ++endif ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/pasemi/pasemi.c linux-3.0.4/crypto/ocf/pasemi/pasemi.c +--- linux-3.0.4.orig/crypto/ocf/pasemi/pasemi.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/pasemi/pasemi.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,1007 @@ ++/* ++ * Copyright (C) 2007 PA Semi, Inc ++ * ++ * Driver for the PA Semi PWRficient DMA Crypto Engine ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "pasemi_fnu.h" ++ ++#define DRV_NAME "pasemi" ++ ++#define TIMER_INTERVAL 1000 ++ ++static void __devexit pasemi_dma_remove(struct pci_dev *pdev); ++static struct pasdma_status volatile * dma_status; ++ ++static int debug; ++module_param(debug, int, 0644); ++MODULE_PARM_DESC(debug, "Enable debug"); ++ ++static void pasemi_desc_start(struct pasemi_desc *desc, u64 hdr) ++{ ++ desc->postop = 0; ++ desc->quad[0] = hdr; ++ desc->quad_cnt = 1; ++ desc->size = 1; ++} ++ ++static void pasemi_desc_build(struct pasemi_desc *desc, u64 val) ++{ ++ desc->quad[desc->quad_cnt++] = val; ++ desc->size = (desc->quad_cnt + 1) / 2; ++} ++ ++static void pasemi_desc_hdr(struct pasemi_desc *desc, u64 hdr) ++{ ++ desc->quad[0] |= hdr; ++} ++ ++static int pasemi_desc_size(struct pasemi_desc *desc) ++{ ++ return desc->size; ++} ++ ++static void pasemi_ring_add_desc( ++ struct pasemi_fnu_txring *ring, ++ struct pasemi_desc *desc, ++ struct cryptop *crp) { ++ int i; ++ int ring_index = 2 * (ring->next_to_fill & (TX_RING_SIZE-1)); ++ ++ TX_DESC_INFO(ring, ring->next_to_fill).desc_size = desc->size; ++ TX_DESC_INFO(ring, ring->next_to_fill).desc_postop = desc->postop; ++ TX_DESC_INFO(ring, ring->next_to_fill).cf_crp = crp; ++ ++ for (i = 0; i < desc->quad_cnt; i += 2) { ++ ring_index = 2 * (ring->next_to_fill & (TX_RING_SIZE-1)); ++ ring->desc[ring_index] = desc->quad[i]; ++ ring->desc[ring_index + 1] = desc->quad[i + 1]; ++ ring->next_to_fill++; ++ } ++ ++ if (desc->quad_cnt & 1) ++ ring->desc[ring_index + 1] = 0; ++} ++ ++static void pasemi_ring_incr(struct pasemi_softc *sc, int chan_index, int incr) ++{ ++ out_le32(sc->dma_regs + PAS_DMA_TXCHAN_INCR(sc->base_chan + chan_index), ++ incr); ++} ++ ++/* ++ * Generate a new software session. ++ */ ++static int ++pasemi_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) ++{ ++ struct cryptoini *c, *encini = NULL, *macini = NULL; ++ struct pasemi_softc *sc = device_get_softc(dev); ++ struct pasemi_session *ses = NULL, **sespp; ++ int sesn, blksz = 0; ++ u64 ccmd = 0; ++ unsigned long flags; ++ struct pasemi_desc init_desc; ++ struct pasemi_fnu_txring *txring; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ if (sidp == NULL || cri == NULL || sc == NULL) { ++ DPRINTF("%s,%d - EINVAL\n", __FILE__, __LINE__); ++ return -EINVAL; ++ } ++ for (c = cri; c != NULL; c = c->cri_next) { ++ if (ALG_IS_SIG(c->cri_alg)) { ++ if (macini) ++ return -EINVAL; ++ macini = c; ++ } else if (ALG_IS_CIPHER(c->cri_alg)) { ++ if (encini) ++ return -EINVAL; ++ encini = c; ++ } else { ++ DPRINTF("UNKNOWN c->cri_alg %d\n", c->cri_alg); ++ return -EINVAL; ++ } ++ } ++ if (encini == NULL && macini == NULL) ++ return -EINVAL; ++ if (encini) { ++ /* validate key length */ ++ switch (encini->cri_alg) { ++ case CRYPTO_DES_CBC: ++ if (encini->cri_klen != 64) ++ return -EINVAL; ++ ccmd = DMA_CALGO_DES; ++ break; ++ case CRYPTO_3DES_CBC: ++ if (encini->cri_klen != 192) ++ return -EINVAL; ++ ccmd = DMA_CALGO_3DES; ++ break; ++ case CRYPTO_AES_CBC: ++ if (encini->cri_klen != 128 && ++ encini->cri_klen != 192 && ++ encini->cri_klen != 256) ++ return -EINVAL; ++ ccmd = DMA_CALGO_AES; ++ break; ++ case CRYPTO_ARC4: ++ if (encini->cri_klen != 128) ++ return -EINVAL; ++ ccmd = DMA_CALGO_ARC; ++ break; ++ default: ++ DPRINTF("UNKNOWN encini->cri_alg %d\n", ++ encini->cri_alg); ++ return -EINVAL; ++ } ++ } ++ ++ if (macini) { ++ switch (macini->cri_alg) { ++ case CRYPTO_MD5: ++ case CRYPTO_MD5_HMAC: ++ blksz = 16; ++ break; ++ case CRYPTO_SHA1: ++ case CRYPTO_SHA1_HMAC: ++ blksz = 20; ++ break; ++ default: ++ DPRINTF("UNKNOWN macini->cri_alg %d\n", ++ macini->cri_alg); ++ return -EINVAL; ++ } ++ if (((macini->cri_klen + 7) / 8) > blksz) { ++ DPRINTF("key length %d bigger than blksize %d not supported\n", ++ ((macini->cri_klen + 7) / 8), blksz); ++ return -EINVAL; ++ } ++ } ++ ++ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { ++ if (sc->sc_sessions[sesn] == NULL) { ++ sc->sc_sessions[sesn] = (struct pasemi_session *) ++ kzalloc(sizeof(struct pasemi_session), GFP_ATOMIC); ++ ses = sc->sc_sessions[sesn]; ++ break; ++ } else if (sc->sc_sessions[sesn]->used == 0) { ++ ses = sc->sc_sessions[sesn]; ++ break; ++ } ++ } ++ ++ if (ses == NULL) { ++ sespp = (struct pasemi_session **) ++ kzalloc(sc->sc_nsessions * 2 * ++ sizeof(struct pasemi_session *), GFP_ATOMIC); ++ if (sespp == NULL) ++ return -ENOMEM; ++ memcpy(sespp, sc->sc_sessions, ++ sc->sc_nsessions * sizeof(struct pasemi_session *)); ++ kfree(sc->sc_sessions); ++ sc->sc_sessions = sespp; ++ sesn = sc->sc_nsessions; ++ ses = sc->sc_sessions[sesn] = (struct pasemi_session *) ++ kzalloc(sizeof(struct pasemi_session), GFP_ATOMIC); ++ if (ses == NULL) ++ return -ENOMEM; ++ sc->sc_nsessions *= 2; ++ } ++ ++ ses->used = 1; ++ ++ ses->dma_addr = pci_map_single(sc->dma_pdev, (void *) ses->civ, ++ sizeof(struct pasemi_session), DMA_TO_DEVICE); ++ ++ /* enter the channel scheduler */ ++ spin_lock_irqsave(&sc->sc_chnlock, flags); ++ ++ /* ARC4 has to be processed by the even channel */ ++ if (encini && (encini->cri_alg == CRYPTO_ARC4)) ++ ses->chan = sc->sc_lastchn & ~1; ++ else ++ ses->chan = sc->sc_lastchn; ++ sc->sc_lastchn = (sc->sc_lastchn + 1) % sc->sc_num_channels; ++ ++ spin_unlock_irqrestore(&sc->sc_chnlock, flags); ++ ++ txring = &sc->tx[ses->chan]; ++ ++ if (encini) { ++ ses->ccmd = ccmd; ++ ses->keysz = (encini->cri_klen - 63) / 64; ++ memcpy(ses->key, encini->cri_key, (ses->keysz + 1) * 8); ++ ++ pasemi_desc_start(&init_desc, ++ XCT_CTRL_HDR(ses->chan, (encini && macini) ? 0x68 : 0x40, DMA_FN_CIV0)); ++ pasemi_desc_build(&init_desc, ++ XCT_FUN_SRC_PTR((encini && macini) ? 0x68 : 0x40, ses->dma_addr)); ++ } ++ if (macini) { ++ if (macini->cri_alg == CRYPTO_MD5_HMAC || ++ macini->cri_alg == CRYPTO_SHA1_HMAC) ++ memcpy(ses->hkey, macini->cri_key, blksz); ++ else { ++ /* Load initialization constants(RFC 1321, 3174) */ ++ ses->hiv[0] = 0x67452301efcdab89ULL; ++ ses->hiv[1] = 0x98badcfe10325476ULL; ++ ses->hiv[2] = 0xc3d2e1f000000000ULL; ++ } ++ ses->hseq = 0ULL; ++ } ++ ++ spin_lock_irqsave(&txring->fill_lock, flags); ++ ++ if (((txring->next_to_fill + pasemi_desc_size(&init_desc)) - ++ txring->next_to_clean) > TX_RING_SIZE) { ++ spin_unlock_irqrestore(&txring->fill_lock, flags); ++ return ERESTART; ++ } ++ ++ if (encini) { ++ pasemi_ring_add_desc(txring, &init_desc, NULL); ++ pasemi_ring_incr(sc, ses->chan, ++ pasemi_desc_size(&init_desc)); ++ } ++ ++ txring->sesn = sesn; ++ spin_unlock_irqrestore(&txring->fill_lock, flags); ++ ++ *sidp = PASEMI_SID(sesn); ++ return 0; ++} ++ ++/* ++ * Deallocate a session. ++ */ ++static int ++pasemi_freesession(device_t dev, u_int64_t tid) ++{ ++ struct pasemi_softc *sc = device_get_softc(dev); ++ int session; ++ u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ if (sc == NULL) ++ return -EINVAL; ++ session = PASEMI_SESSION(sid); ++ if (session >= sc->sc_nsessions || !sc->sc_sessions[session]) ++ return -EINVAL; ++ ++ pci_unmap_single(sc->dma_pdev, ++ sc->sc_sessions[session]->dma_addr, ++ sizeof(struct pasemi_session), DMA_TO_DEVICE); ++ memset(sc->sc_sessions[session], 0, ++ sizeof(struct pasemi_session)); ++ ++ return 0; ++} ++ ++static int ++pasemi_process(device_t dev, struct cryptop *crp, int hint) ++{ ++ ++ int err = 0, ivsize, srclen = 0, reinit = 0, reinit_size = 0, chsel; ++ struct pasemi_softc *sc = device_get_softc(dev); ++ struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; ++ caddr_t ivp; ++ struct pasemi_desc init_desc, work_desc; ++ struct pasemi_session *ses; ++ struct sk_buff *skb; ++ struct uio *uiop; ++ unsigned long flags; ++ struct pasemi_fnu_txring *txring; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ if (crp == NULL || crp->crp_callback == NULL || sc == NULL) ++ return -EINVAL; ++ ++ crp->crp_etype = 0; ++ if (PASEMI_SESSION(crp->crp_sid) >= sc->sc_nsessions) ++ return -EINVAL; ++ ++ ses = sc->sc_sessions[PASEMI_SESSION(crp->crp_sid)]; ++ ++ crd1 = crp->crp_desc; ++ if (crd1 == NULL) { ++ err = -EINVAL; ++ goto errout; ++ } ++ crd2 = crd1->crd_next; ++ ++ if (ALG_IS_SIG(crd1->crd_alg)) { ++ maccrd = crd1; ++ if (crd2 == NULL) ++ enccrd = NULL; ++ else if (ALG_IS_CIPHER(crd2->crd_alg) && ++ (crd2->crd_flags & CRD_F_ENCRYPT) == 0) ++ enccrd = crd2; ++ else ++ goto erralg; ++ } else if (ALG_IS_CIPHER(crd1->crd_alg)) { ++ enccrd = crd1; ++ if (crd2 == NULL) ++ maccrd = NULL; ++ else if (ALG_IS_SIG(crd2->crd_alg) && ++ (crd1->crd_flags & CRD_F_ENCRYPT)) ++ maccrd = crd2; ++ else ++ goto erralg; ++ } else ++ goto erralg; ++ ++ chsel = ses->chan; ++ ++ txring = &sc->tx[chsel]; ++ ++ if (enccrd && !maccrd) { ++ if (enccrd->crd_alg == CRYPTO_ARC4) ++ reinit = 1; ++ reinit_size = 0x40; ++ srclen = crp->crp_ilen; ++ ++ pasemi_desc_start(&work_desc, XCT_FUN_O | XCT_FUN_I ++ | XCT_FUN_FUN(chsel)); ++ if (enccrd->crd_flags & CRD_F_ENCRYPT) ++ pasemi_desc_hdr(&work_desc, XCT_FUN_CRM_ENC); ++ else ++ pasemi_desc_hdr(&work_desc, XCT_FUN_CRM_DEC); ++ } else if (enccrd && maccrd) { ++ if (enccrd->crd_alg == CRYPTO_ARC4) ++ reinit = 1; ++ reinit_size = 0x68; ++ ++ if (enccrd->crd_flags & CRD_F_ENCRYPT) { ++ /* Encrypt -> Authenticate */ ++ pasemi_desc_start(&work_desc, XCT_FUN_O | XCT_FUN_I | XCT_FUN_CRM_ENC_SIG ++ | XCT_FUN_A | XCT_FUN_FUN(chsel)); ++ srclen = maccrd->crd_skip + maccrd->crd_len; ++ } else { ++ /* Authenticate -> Decrypt */ ++ pasemi_desc_start(&work_desc, XCT_FUN_O | XCT_FUN_I | XCT_FUN_CRM_SIG_DEC ++ | XCT_FUN_24BRES | XCT_FUN_FUN(chsel)); ++ pasemi_desc_build(&work_desc, 0); ++ pasemi_desc_build(&work_desc, 0); ++ pasemi_desc_build(&work_desc, 0); ++ work_desc.postop = PASEMI_CHECK_SIG; ++ srclen = crp->crp_ilen; ++ } ++ ++ pasemi_desc_hdr(&work_desc, XCT_FUN_SHL(maccrd->crd_skip / 4)); ++ pasemi_desc_hdr(&work_desc, XCT_FUN_CHL(enccrd->crd_skip - maccrd->crd_skip)); ++ } else if (!enccrd && maccrd) { ++ srclen = maccrd->crd_len; ++ ++ pasemi_desc_start(&init_desc, ++ XCT_CTRL_HDR(chsel, 0x58, DMA_FN_HKEY0)); ++ pasemi_desc_build(&init_desc, ++ XCT_FUN_SRC_PTR(0x58, ((struct pasemi_session *)ses->dma_addr)->hkey)); ++ ++ pasemi_desc_start(&work_desc, XCT_FUN_O | XCT_FUN_I | XCT_FUN_CRM_SIG ++ | XCT_FUN_A | XCT_FUN_FUN(chsel)); ++ } ++ ++ if (enccrd) { ++ switch (enccrd->crd_alg) { ++ case CRYPTO_3DES_CBC: ++ pasemi_desc_hdr(&work_desc, XCT_FUN_ALG_3DES | ++ XCT_FUN_BCM_CBC); ++ ivsize = sizeof(u64); ++ break; ++ case CRYPTO_DES_CBC: ++ pasemi_desc_hdr(&work_desc, XCT_FUN_ALG_DES | ++ XCT_FUN_BCM_CBC); ++ ivsize = sizeof(u64); ++ break; ++ case CRYPTO_AES_CBC: ++ pasemi_desc_hdr(&work_desc, XCT_FUN_ALG_AES | ++ XCT_FUN_BCM_CBC); ++ ivsize = 2 * sizeof(u64); ++ break; ++ case CRYPTO_ARC4: ++ pasemi_desc_hdr(&work_desc, XCT_FUN_ALG_ARC); ++ ivsize = 0; ++ break; ++ default: ++ printk(DRV_NAME ": unimplemented enccrd->crd_alg %d\n", ++ enccrd->crd_alg); ++ err = -EINVAL; ++ goto errout; ++ } ++ ++ ivp = (ivsize == sizeof(u64)) ? (caddr_t) &ses->civ[1] : (caddr_t) &ses->civ[0]; ++ if (enccrd->crd_flags & CRD_F_ENCRYPT) { ++ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) ++ memcpy(ivp, enccrd->crd_iv, ivsize); ++ else ++ read_random(ivp, ivsize); ++ /* If IV is not present in the buffer already, it has to be copied there */ ++ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ enccrd->crd_inject, ivsize, ivp); ++ } else { ++ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) ++ /* IV is provided expicitly in descriptor */ ++ memcpy(ivp, enccrd->crd_iv, ivsize); ++ else ++ /* IV is provided in the packet */ ++ crypto_copydata(crp->crp_flags, crp->crp_buf, ++ enccrd->crd_inject, ivsize, ++ ivp); ++ } ++ } ++ ++ if (maccrd) { ++ switch (maccrd->crd_alg) { ++ case CRYPTO_MD5: ++ pasemi_desc_hdr(&work_desc, XCT_FUN_SIG_MD5 | ++ XCT_FUN_HSZ((crp->crp_ilen - maccrd->crd_inject) / 4)); ++ break; ++ case CRYPTO_SHA1: ++ pasemi_desc_hdr(&work_desc, XCT_FUN_SIG_SHA1 | ++ XCT_FUN_HSZ((crp->crp_ilen - maccrd->crd_inject) / 4)); ++ break; ++ case CRYPTO_MD5_HMAC: ++ pasemi_desc_hdr(&work_desc, XCT_FUN_SIG_HMAC_MD5 | ++ XCT_FUN_HSZ((crp->crp_ilen - maccrd->crd_inject) / 4)); ++ break; ++ case CRYPTO_SHA1_HMAC: ++ pasemi_desc_hdr(&work_desc, XCT_FUN_SIG_HMAC_SHA1 | ++ XCT_FUN_HSZ((crp->crp_ilen - maccrd->crd_inject) / 4)); ++ break; ++ default: ++ printk(DRV_NAME ": unimplemented maccrd->crd_alg %d\n", ++ maccrd->crd_alg); ++ err = -EINVAL; ++ goto errout; ++ } ++ } ++ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ /* using SKB buffers */ ++ skb = (struct sk_buff *)crp->crp_buf; ++ if (skb_shinfo(skb)->nr_frags) { ++ printk(DRV_NAME ": skb frags unimplemented\n"); ++ err = -EINVAL; ++ goto errout; ++ } ++ pasemi_desc_build( ++ &work_desc, ++ XCT_FUN_DST_PTR(skb->len, pci_map_single( ++ sc->dma_pdev, skb->data, ++ skb->len, DMA_TO_DEVICE))); ++ pasemi_desc_build( ++ &work_desc, ++ XCT_FUN_SRC_PTR( ++ srclen, pci_map_single( ++ sc->dma_pdev, skb->data, ++ srclen, DMA_TO_DEVICE))); ++ pasemi_desc_hdr(&work_desc, XCT_FUN_LLEN(srclen)); ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ /* using IOV buffers */ ++ uiop = (struct uio *)crp->crp_buf; ++ if (uiop->uio_iovcnt > 1) { ++ printk(DRV_NAME ": iov frags unimplemented\n"); ++ err = -EINVAL; ++ goto errout; ++ } ++ ++ /* crp_olen is never set; always use crp_ilen */ ++ pasemi_desc_build( ++ &work_desc, ++ XCT_FUN_DST_PTR(crp->crp_ilen, pci_map_single( ++ sc->dma_pdev, ++ uiop->uio_iov->iov_base, ++ crp->crp_ilen, DMA_TO_DEVICE))); ++ pasemi_desc_hdr(&work_desc, XCT_FUN_LLEN(srclen)); ++ ++ pasemi_desc_build( ++ &work_desc, ++ XCT_FUN_SRC_PTR(srclen, pci_map_single( ++ sc->dma_pdev, ++ uiop->uio_iov->iov_base, ++ srclen, DMA_TO_DEVICE))); ++ } else { ++ /* using contig buffers */ ++ pasemi_desc_build( ++ &work_desc, ++ XCT_FUN_DST_PTR(crp->crp_ilen, pci_map_single( ++ sc->dma_pdev, ++ crp->crp_buf, ++ crp->crp_ilen, DMA_TO_DEVICE))); ++ pasemi_desc_build( ++ &work_desc, ++ XCT_FUN_SRC_PTR(srclen, pci_map_single( ++ sc->dma_pdev, ++ crp->crp_buf, srclen, ++ DMA_TO_DEVICE))); ++ pasemi_desc_hdr(&work_desc, XCT_FUN_LLEN(srclen)); ++ } ++ ++ spin_lock_irqsave(&txring->fill_lock, flags); ++ ++ if (txring->sesn != PASEMI_SESSION(crp->crp_sid)) { ++ txring->sesn = PASEMI_SESSION(crp->crp_sid); ++ reinit = 1; ++ } ++ ++ if (enccrd) { ++ pasemi_desc_start(&init_desc, ++ XCT_CTRL_HDR(chsel, reinit ? reinit_size : 0x10, DMA_FN_CIV0)); ++ pasemi_desc_build(&init_desc, ++ XCT_FUN_SRC_PTR(reinit ? reinit_size : 0x10, ses->dma_addr)); ++ } ++ ++ if (((txring->next_to_fill + pasemi_desc_size(&init_desc) + ++ pasemi_desc_size(&work_desc)) - ++ txring->next_to_clean) > TX_RING_SIZE) { ++ spin_unlock_irqrestore(&txring->fill_lock, flags); ++ err = ERESTART; ++ goto errout; ++ } ++ ++ pasemi_ring_add_desc(txring, &init_desc, NULL); ++ pasemi_ring_add_desc(txring, &work_desc, crp); ++ ++ pasemi_ring_incr(sc, chsel, ++ pasemi_desc_size(&init_desc) + ++ pasemi_desc_size(&work_desc)); ++ ++ spin_unlock_irqrestore(&txring->fill_lock, flags); ++ ++ mod_timer(&txring->crypto_timer, jiffies + TIMER_INTERVAL); ++ ++ return 0; ++ ++erralg: ++ printk(DRV_NAME ": unsupported algorithm or algorithm order alg1 %d alg2 %d\n", ++ crd1->crd_alg, crd2->crd_alg); ++ err = -EINVAL; ++ ++errout: ++ if (err != ERESTART) { ++ crp->crp_etype = err; ++ crypto_done(crp); ++ } ++ return err; ++} ++ ++static int pasemi_clean_tx(struct pasemi_softc *sc, int chan) ++{ ++ int i, j, ring_idx; ++ struct pasemi_fnu_txring *ring = &sc->tx[chan]; ++ u16 delta_cnt; ++ int flags, loops = 10; ++ int desc_size; ++ struct cryptop *crp; ++ ++ spin_lock_irqsave(&ring->clean_lock, flags); ++ ++ while ((delta_cnt = (dma_status->tx_sta[sc->base_chan + chan] ++ & PAS_STATUS_PCNT_M) - ring->total_pktcnt) ++ && loops--) { ++ ++ for (i = 0; i < delta_cnt; i++) { ++ desc_size = TX_DESC_INFO(ring, ring->next_to_clean).desc_size; ++ crp = TX_DESC_INFO(ring, ring->next_to_clean).cf_crp; ++ if (crp) { ++ ring_idx = 2 * (ring->next_to_clean & (TX_RING_SIZE-1)); ++ if (TX_DESC_INFO(ring, ring->next_to_clean).desc_postop & PASEMI_CHECK_SIG) { ++ /* Need to make sure signature matched, ++ * if not - return error */ ++ if (!(ring->desc[ring_idx + 1] & (1ULL << 63))) ++ crp->crp_etype = -EINVAL; ++ } ++ crypto_done(TX_DESC_INFO(ring, ++ ring->next_to_clean).cf_crp); ++ TX_DESC_INFO(ring, ring->next_to_clean).cf_crp = NULL; ++ pci_unmap_single( ++ sc->dma_pdev, ++ XCT_PTR_ADDR_LEN(ring->desc[ring_idx + 1]), ++ PCI_DMA_TODEVICE); ++ ++ ring->desc[ring_idx] = ring->desc[ring_idx + 1] = 0; ++ ++ ring->next_to_clean++; ++ for (j = 1; j < desc_size; j++) { ++ ring_idx = 2 * ++ (ring->next_to_clean & ++ (TX_RING_SIZE-1)); ++ pci_unmap_single( ++ sc->dma_pdev, ++ XCT_PTR_ADDR_LEN(ring->desc[ring_idx]), ++ PCI_DMA_TODEVICE); ++ if (ring->desc[ring_idx + 1]) ++ pci_unmap_single( ++ sc->dma_pdev, ++ XCT_PTR_ADDR_LEN( ++ ring->desc[ ++ ring_idx + 1]), ++ PCI_DMA_TODEVICE); ++ ring->desc[ring_idx] = ++ ring->desc[ring_idx + 1] = 0; ++ ring->next_to_clean++; ++ } ++ } else { ++ for (j = 0; j < desc_size; j++) { ++ ring_idx = 2 * (ring->next_to_clean & (TX_RING_SIZE-1)); ++ ring->desc[ring_idx] = ++ ring->desc[ring_idx + 1] = 0; ++ ring->next_to_clean++; ++ } ++ } ++ } ++ ++ ring->total_pktcnt += delta_cnt; ++ } ++ spin_unlock_irqrestore(&ring->clean_lock, flags); ++ ++ return 0; ++} ++ ++static void sweepup_tx(struct pasemi_softc *sc) ++{ ++ int i; ++ ++ for (i = 0; i < sc->sc_num_channels; i++) ++ pasemi_clean_tx(sc, i); ++} ++ ++static irqreturn_t pasemi_intr(int irq, void *arg, struct pt_regs *regs) ++{ ++ struct pasemi_softc *sc = arg; ++ unsigned int reg; ++ int chan = irq - sc->base_irq; ++ int chan_index = sc->base_chan + chan; ++ u64 stat = dma_status->tx_sta[chan_index]; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ if (!(stat & PAS_STATUS_CAUSE_M)) ++ return IRQ_NONE; ++ ++ pasemi_clean_tx(sc, chan); ++ ++ stat = dma_status->tx_sta[chan_index]; ++ ++ reg = PAS_IOB_DMA_TXCH_RESET_PINTC | ++ PAS_IOB_DMA_TXCH_RESET_PCNT(sc->tx[chan].total_pktcnt); ++ ++ if (stat & PAS_STATUS_SOFT) ++ reg |= PAS_IOB_DMA_RXCH_RESET_SINTC; ++ ++ out_le32(sc->iob_regs + PAS_IOB_DMA_TXCH_RESET(chan_index), reg); ++ ++ ++ return IRQ_HANDLED; ++} ++ ++static int pasemi_dma_setup_tx_resources(struct pasemi_softc *sc, int chan) ++{ ++ u32 val; ++ int chan_index = chan + sc->base_chan; ++ int ret; ++ struct pasemi_fnu_txring *ring; ++ ++ ring = &sc->tx[chan]; ++ ++ spin_lock_init(&ring->fill_lock); ++ spin_lock_init(&ring->clean_lock); ++ ++ ring->desc_info = kzalloc(sizeof(struct pasemi_desc_info) * ++ TX_RING_SIZE, GFP_KERNEL); ++ if (!ring->desc_info) ++ return -ENOMEM; ++ ++ /* Allocate descriptors */ ++ ring->desc = dma_alloc_coherent(&sc->dma_pdev->dev, ++ TX_RING_SIZE * ++ 2 * sizeof(u64), ++ &ring->dma, GFP_KERNEL); ++ if (!ring->desc) ++ return -ENOMEM; ++ ++ memset((void *) ring->desc, 0, TX_RING_SIZE * 2 * sizeof(u64)); ++ ++ out_le32(sc->iob_regs + PAS_IOB_DMA_TXCH_RESET(chan_index), 0x30); ++ ++ ring->total_pktcnt = 0; ++ ++ out_le32(sc->dma_regs + PAS_DMA_TXCHAN_BASEL(chan_index), ++ PAS_DMA_TXCHAN_BASEL_BRBL(ring->dma)); ++ ++ val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->dma >> 32); ++ val |= PAS_DMA_TXCHAN_BASEU_SIZ(TX_RING_SIZE >> 2); ++ ++ out_le32(sc->dma_regs + PAS_DMA_TXCHAN_BASEU(chan_index), val); ++ ++ out_le32(sc->dma_regs + PAS_DMA_TXCHAN_CFG(chan_index), ++ PAS_DMA_TXCHAN_CFG_TY_FUNC | ++ PAS_DMA_TXCHAN_CFG_TATTR(chan) | ++ PAS_DMA_TXCHAN_CFG_WT(2)); ++ ++ /* enable tx channel */ ++ out_le32(sc->dma_regs + ++ PAS_DMA_TXCHAN_TCMDSTA(chan_index), ++ PAS_DMA_TXCHAN_TCMDSTA_EN); ++ ++ out_le32(sc->iob_regs + PAS_IOB_DMA_TXCH_CFG(chan_index), ++ PAS_IOB_DMA_TXCH_CFG_CNTTH(1000)); ++ ++ ring->next_to_fill = 0; ++ ring->next_to_clean = 0; ++ ++ snprintf(ring->irq_name, sizeof(ring->irq_name), ++ "%s%d", "crypto", chan); ++ ++ ring->irq = irq_create_mapping(NULL, sc->base_irq + chan); ++ ret = request_irq(ring->irq, (irq_handler_t) ++ pasemi_intr, IRQF_DISABLED, ring->irq_name, sc); ++ if (ret) { ++ printk(KERN_ERR DRV_NAME ": failed to hook irq %d ret %d\n", ++ ring->irq, ret); ++ ring->irq = -1; ++ return ret; ++ } ++ ++ setup_timer(&ring->crypto_timer, (void *) sweepup_tx, (unsigned long) sc); ++ ++ return 0; ++} ++ ++static device_method_t pasemi_methods = { ++ /* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, pasemi_newsession), ++ DEVMETHOD(cryptodev_freesession, pasemi_freesession), ++ DEVMETHOD(cryptodev_process, pasemi_process), ++}; ++ ++/* Set up the crypto device structure, private data, ++ * and anything else we need before we start */ ++ ++static int __devinit ++pasemi_dma_probe(struct pci_dev *pdev, const struct pci_device_id *ent) ++{ ++ struct pasemi_softc *sc; ++ int ret, i; ++ ++ DPRINTF(KERN_ERR "%s()\n", __FUNCTION__); ++ ++ sc = kzalloc(sizeof(*sc), GFP_KERNEL); ++ if (!sc) ++ return -ENOMEM; ++ ++ softc_device_init(sc, DRV_NAME, 1, pasemi_methods); ++ ++ pci_set_drvdata(pdev, sc); ++ ++ spin_lock_init(&sc->sc_chnlock); ++ ++ sc->sc_sessions = (struct pasemi_session **) ++ kzalloc(PASEMI_INITIAL_SESSIONS * ++ sizeof(struct pasemi_session *), GFP_ATOMIC); ++ if (sc->sc_sessions == NULL) { ++ ret = -ENOMEM; ++ goto out; ++ } ++ ++ sc->sc_nsessions = PASEMI_INITIAL_SESSIONS; ++ sc->sc_lastchn = 0; ++ sc->base_irq = pdev->irq + 6; ++ sc->base_chan = 6; ++ sc->sc_cid = -1; ++ sc->dma_pdev = pdev; ++ ++ sc->iob_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL); ++ if (!sc->iob_pdev) { ++ dev_err(&pdev->dev, "Can't find I/O Bridge\n"); ++ ret = -ENODEV; ++ goto out; ++ } ++ ++ /* This is hardcoded and ugly, but we have some firmware versions ++ * who don't provide the register space in the device tree. Luckily ++ * they are at well-known locations so we can just do the math here. ++ */ ++ sc->dma_regs = ++ ioremap(0xe0000000 + (sc->dma_pdev->devfn << 12), 0x2000); ++ sc->iob_regs = ++ ioremap(0xe0000000 + (sc->iob_pdev->devfn << 12), 0x2000); ++ if (!sc->dma_regs || !sc->iob_regs) { ++ dev_err(&pdev->dev, "Can't map registers\n"); ++ ret = -ENODEV; ++ goto out; ++ } ++ ++ dma_status = __ioremap(0xfd800000, 0x1000, 0); ++ if (!dma_status) { ++ ret = -ENODEV; ++ dev_err(&pdev->dev, "Can't map dmastatus space\n"); ++ goto out; ++ } ++ ++ sc->tx = (struct pasemi_fnu_txring *) ++ kzalloc(sizeof(struct pasemi_fnu_txring) ++ * 8, GFP_KERNEL); ++ if (!sc->tx) { ++ ret = -ENOMEM; ++ goto out; ++ } ++ ++ /* Initialize the h/w */ ++ out_le32(sc->dma_regs + PAS_DMA_COM_CFG, ++ (in_le32(sc->dma_regs + PAS_DMA_COM_CFG) | ++ PAS_DMA_COM_CFG_FWF)); ++ out_le32(sc->dma_regs + PAS_DMA_COM_TXCMD, PAS_DMA_COM_TXCMD_EN); ++ ++ for (i = 0; i < PASEMI_FNU_CHANNELS; i++) { ++ sc->sc_num_channels++; ++ ret = pasemi_dma_setup_tx_resources(sc, i); ++ if (ret) ++ goto out; ++ } ++ ++ sc->sc_cid = crypto_get_driverid(softc_get_device(sc), ++ CRYPTOCAP_F_HARDWARE); ++ if (sc->sc_cid < 0) { ++ printk(KERN_ERR DRV_NAME ": could not get crypto driver id\n"); ++ ret = -ENXIO; ++ goto out; ++ } ++ ++ /* register algorithms with the framework */ ++ printk(DRV_NAME ":"); ++ ++ crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); ++ ++ return 0; ++ ++out: ++ pasemi_dma_remove(pdev); ++ return ret; ++} ++ ++#define MAX_RETRIES 5000 ++ ++static void pasemi_free_tx_resources(struct pasemi_softc *sc, int chan) ++{ ++ struct pasemi_fnu_txring *ring = &sc->tx[chan]; ++ int chan_index = chan + sc->base_chan; ++ int retries; ++ u32 stat; ++ ++ /* Stop the channel */ ++ out_le32(sc->dma_regs + ++ PAS_DMA_TXCHAN_TCMDSTA(chan_index), ++ PAS_DMA_TXCHAN_TCMDSTA_ST); ++ ++ for (retries = 0; retries < MAX_RETRIES; retries++) { ++ stat = in_le32(sc->dma_regs + ++ PAS_DMA_TXCHAN_TCMDSTA(chan_index)); ++ if (!(stat & PAS_DMA_TXCHAN_TCMDSTA_ACT)) ++ break; ++ cond_resched(); ++ } ++ ++ if (stat & PAS_DMA_TXCHAN_TCMDSTA_ACT) ++ dev_err(&sc->dma_pdev->dev, "Failed to stop tx channel %d\n", ++ chan_index); ++ ++ /* Disable the channel */ ++ out_le32(sc->dma_regs + ++ PAS_DMA_TXCHAN_TCMDSTA(chan_index), ++ 0); ++ ++ if (ring->desc_info) ++ kfree((void *) ring->desc_info); ++ if (ring->desc) ++ dma_free_coherent(&sc->dma_pdev->dev, ++ TX_RING_SIZE * ++ 2 * sizeof(u64), ++ (void *) ring->desc, ring->dma); ++ if (ring->irq != -1) ++ free_irq(ring->irq, sc); ++ ++ del_timer(&ring->crypto_timer); ++} ++ ++static void __devexit pasemi_dma_remove(struct pci_dev *pdev) ++{ ++ struct pasemi_softc *sc = pci_get_drvdata(pdev); ++ int i; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ if (sc->sc_cid >= 0) { ++ crypto_unregister_all(sc->sc_cid); ++ } ++ ++ if (sc->tx) { ++ for (i = 0; i < sc->sc_num_channels; i++) ++ pasemi_free_tx_resources(sc, i); ++ ++ kfree(sc->tx); ++ } ++ if (sc->sc_sessions) { ++ for (i = 0; i < sc->sc_nsessions; i++) ++ kfree(sc->sc_sessions[i]); ++ kfree(sc->sc_sessions); ++ } ++ if (sc->iob_pdev) ++ pci_dev_put(sc->iob_pdev); ++ if (sc->dma_regs) ++ iounmap(sc->dma_regs); ++ if (sc->iob_regs) ++ iounmap(sc->iob_regs); ++ kfree(sc); ++} ++ ++static struct pci_device_id pasemi_dma_pci_tbl[] = { ++ { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa007) }, ++}; ++ ++MODULE_DEVICE_TABLE(pci, pasemi_dma_pci_tbl); ++ ++static struct pci_driver pasemi_dma_driver = { ++ .name = "pasemi_dma", ++ .id_table = pasemi_dma_pci_tbl, ++ .probe = pasemi_dma_probe, ++ .remove = __devexit_p(pasemi_dma_remove), ++}; ++ ++static void __exit pasemi_dma_cleanup_module(void) ++{ ++ pci_unregister_driver(&pasemi_dma_driver); ++ __iounmap(dma_status); ++ dma_status = NULL; ++} ++ ++int pasemi_dma_init_module(void) ++{ ++ return pci_register_driver(&pasemi_dma_driver); ++} ++ ++module_init(pasemi_dma_init_module); ++module_exit(pasemi_dma_cleanup_module); ++ ++MODULE_LICENSE("Dual BSD/GPL"); ++MODULE_AUTHOR("Egor Martovetsky egor@pasemi.com"); ++MODULE_DESCRIPTION("OCF driver for PA Semi PWRficient DMA Crypto Engine"); +diff -Nur linux-3.0.4.orig/crypto/ocf/pasemi/pasemi_fnu.h linux-3.0.4/crypto/ocf/pasemi/pasemi_fnu.h +--- linux-3.0.4.orig/crypto/ocf/pasemi/pasemi_fnu.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/pasemi/pasemi_fnu.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,410 @@ ++/* ++ * Copyright (C) 2007 PA Semi, Inc ++ * ++ * Driver for the PA Semi PWRficient DMA Crypto Engine, soft state and ++ * hardware register layouts. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef PASEMI_FNU_H ++#define PASEMI_FNU_H ++ ++#include ++ ++#define PASEMI_SESSION(sid) ((sid) & 0xffffffff) ++#define PASEMI_SID(sesn) ((sesn) & 0xffffffff) ++#define DPRINTF(a...) if (debug) { printk(DRV_NAME ": " a); } ++ ++/* Must be a power of two */ ++#define RX_RING_SIZE 512 ++#define TX_RING_SIZE 512 ++#define TX_DESC(ring, num) ((ring)->desc[2 * (num & (TX_RING_SIZE-1))]) ++#define TX_DESC_INFO(ring, num) ((ring)->desc_info[(num) & (TX_RING_SIZE-1)]) ++#define MAX_DESC_SIZE 8 ++#define PASEMI_INITIAL_SESSIONS 10 ++#define PASEMI_FNU_CHANNELS 8 ++ ++/* DMA descriptor */ ++struct pasemi_desc { ++ u64 quad[2*MAX_DESC_SIZE]; ++ int quad_cnt; ++ int size; ++ int postop; ++}; ++ ++/* ++ * Holds per descriptor data ++ */ ++struct pasemi_desc_info { ++ int desc_size; ++ int desc_postop; ++#define PASEMI_CHECK_SIG 0x1 ++ ++ struct cryptop *cf_crp; ++}; ++ ++/* ++ * Holds per channel data ++ */ ++struct pasemi_fnu_txring { ++ volatile u64 *desc; ++ volatile struct ++ pasemi_desc_info *desc_info; ++ dma_addr_t dma; ++ struct timer_list crypto_timer; ++ spinlock_t fill_lock; ++ spinlock_t clean_lock; ++ unsigned int next_to_fill; ++ unsigned int next_to_clean; ++ u16 total_pktcnt; ++ int irq; ++ int sesn; ++ char irq_name[10]; ++}; ++ ++/* ++ * Holds data specific to a single pasemi device. ++ */ ++struct pasemi_softc { ++ softc_device_decl sc_cdev; ++ struct pci_dev *dma_pdev; /* device backpointer */ ++ struct pci_dev *iob_pdev; /* device backpointer */ ++ void __iomem *dma_regs; ++ void __iomem *iob_regs; ++ int base_irq; ++ int base_chan; ++ int32_t sc_cid; /* crypto tag */ ++ int sc_nsessions; ++ struct pasemi_session **sc_sessions; ++ int sc_num_channels;/* number of crypto channels */ ++ ++ /* pointer to the array of txring datastructures, one txring per channel */ ++ struct pasemi_fnu_txring *tx; ++ ++ /* ++ * mutual exclusion for the channel scheduler ++ */ ++ spinlock_t sc_chnlock; ++ /* last channel used, for now use round-robin to allocate channels */ ++ int sc_lastchn; ++}; ++ ++struct pasemi_session { ++ u64 civ[2]; ++ u64 keysz; ++ u64 key[4]; ++ u64 ccmd; ++ u64 hkey[4]; ++ u64 hseq; ++ u64 giv[2]; ++ u64 hiv[4]; ++ ++ int used; ++ dma_addr_t dma_addr; ++ int chan; ++}; ++ ++/* status register layout in IOB region, at 0xfd800000 */ ++struct pasdma_status { ++ u64 rx_sta[64]; ++ u64 tx_sta[20]; ++}; ++ ++#define ALG_IS_CIPHER(alg) ((alg == CRYPTO_DES_CBC) || \ ++ (alg == CRYPTO_3DES_CBC) || \ ++ (alg == CRYPTO_AES_CBC) || \ ++ (alg == CRYPTO_ARC4) || \ ++ (alg == CRYPTO_NULL_CBC)) ++ ++#define ALG_IS_SIG(alg) ((alg == CRYPTO_MD5) || \ ++ (alg == CRYPTO_MD5_HMAC) || \ ++ (alg == CRYPTO_SHA1) || \ ++ (alg == CRYPTO_SHA1_HMAC) || \ ++ (alg == CRYPTO_NULL_HMAC)) ++ ++enum { ++ PAS_DMA_COM_TXCMD = 0x100, /* Transmit Command Register */ ++ PAS_DMA_COM_TXSTA = 0x104, /* Transmit Status Register */ ++ PAS_DMA_COM_RXCMD = 0x108, /* Receive Command Register */ ++ PAS_DMA_COM_RXSTA = 0x10c, /* Receive Status Register */ ++ PAS_DMA_COM_CFG = 0x114, /* DMA Configuration Register */ ++}; ++ ++/* All these registers live in the PCI configuration space for the DMA PCI ++ * device. Use the normal PCI config access functions for them. ++ */ ++ ++#define PAS_DMA_COM_CFG_FWF 0x18000000 ++ ++#define PAS_DMA_COM_TXCMD_EN 0x00000001 /* enable */ ++#define PAS_DMA_COM_TXSTA_ACT 0x00000001 /* active */ ++#define PAS_DMA_COM_RXCMD_EN 0x00000001 /* enable */ ++#define PAS_DMA_COM_RXSTA_ACT 0x00000001 /* active */ ++ ++#define _PAS_DMA_TXCHAN_STRIDE 0x20 /* Size per channel */ ++#define _PAS_DMA_TXCHAN_TCMDSTA 0x300 /* Command / Status */ ++#define _PAS_DMA_TXCHAN_CFG 0x304 /* Configuration */ ++#define _PAS_DMA_TXCHAN_DSCRBU 0x308 /* Descriptor BU Allocation */ ++#define _PAS_DMA_TXCHAN_INCR 0x310 /* Descriptor increment */ ++#define _PAS_DMA_TXCHAN_CNT 0x314 /* Descriptor count/offset */ ++#define _PAS_DMA_TXCHAN_BASEL 0x318 /* Descriptor ring base (low) */ ++#define _PAS_DMA_TXCHAN_BASEU 0x31c /* (high) */ ++#define PAS_DMA_TXCHAN_TCMDSTA(c) (0x300+(c)*_PAS_DMA_TXCHAN_STRIDE) ++#define PAS_DMA_TXCHAN_TCMDSTA_EN 0x00000001 /* Enabled */ ++#define PAS_DMA_TXCHAN_TCMDSTA_ST 0x00000002 /* Stop interface */ ++#define PAS_DMA_TXCHAN_TCMDSTA_ACT 0x00010000 /* Active */ ++#define PAS_DMA_TXCHAN_CFG(c) (0x304+(c)*_PAS_DMA_TXCHAN_STRIDE) ++#define PAS_DMA_TXCHAN_CFG_TY_FUNC 0x00000002 /* Type = interface */ ++#define PAS_DMA_TXCHAN_CFG_TY_IFACE 0x00000000 /* Type = interface */ ++#define PAS_DMA_TXCHAN_CFG_TATTR_M 0x0000003c ++#define PAS_DMA_TXCHAN_CFG_TATTR_S 2 ++#define PAS_DMA_TXCHAN_CFG_TATTR(x) (((x) << PAS_DMA_TXCHAN_CFG_TATTR_S) & \ ++ PAS_DMA_TXCHAN_CFG_TATTR_M) ++#define PAS_DMA_TXCHAN_CFG_WT_M 0x000001c0 ++#define PAS_DMA_TXCHAN_CFG_WT_S 6 ++#define PAS_DMA_TXCHAN_CFG_WT(x) (((x) << PAS_DMA_TXCHAN_CFG_WT_S) & \ ++ PAS_DMA_TXCHAN_CFG_WT_M) ++#define PAS_DMA_TXCHAN_CFG_LPSQ_FAST 0x00000400 ++#define PAS_DMA_TXCHAN_CFG_LPDQ_FAST 0x00000800 ++#define PAS_DMA_TXCHAN_CFG_CF 0x00001000 /* Clean first line */ ++#define PAS_DMA_TXCHAN_CFG_CL 0x00002000 /* Clean last line */ ++#define PAS_DMA_TXCHAN_CFG_UP 0x00004000 /* update tx descr when sent */ ++#define PAS_DMA_TXCHAN_INCR(c) (0x310+(c)*_PAS_DMA_TXCHAN_STRIDE) ++#define PAS_DMA_TXCHAN_BASEL(c) (0x318+(c)*_PAS_DMA_TXCHAN_STRIDE) ++#define PAS_DMA_TXCHAN_BASEL_BRBL_M 0xffffffc0 ++#define PAS_DMA_TXCHAN_BASEL_BRBL_S 0 ++#define PAS_DMA_TXCHAN_BASEL_BRBL(x) (((x) << PAS_DMA_TXCHAN_BASEL_BRBL_S) & \ ++ PAS_DMA_TXCHAN_BASEL_BRBL_M) ++#define PAS_DMA_TXCHAN_BASEU(c) (0x31c+(c)*_PAS_DMA_TXCHAN_STRIDE) ++#define PAS_DMA_TXCHAN_BASEU_BRBH_M 0x00000fff ++#define PAS_DMA_TXCHAN_BASEU_BRBH_S 0 ++#define PAS_DMA_TXCHAN_BASEU_BRBH(x) (((x) << PAS_DMA_TXCHAN_BASEU_BRBH_S) & \ ++ PAS_DMA_TXCHAN_BASEU_BRBH_M) ++/* # of cache lines worth of buffer ring */ ++#define PAS_DMA_TXCHAN_BASEU_SIZ_M 0x3fff0000 ++#define PAS_DMA_TXCHAN_BASEU_SIZ_S 16 /* 0 = 16K */ ++#define PAS_DMA_TXCHAN_BASEU_SIZ(x) (((x) << PAS_DMA_TXCHAN_BASEU_SIZ_S) & \ ++ PAS_DMA_TXCHAN_BASEU_SIZ_M) ++ ++#define PAS_STATUS_PCNT_M 0x000000000000ffffull ++#define PAS_STATUS_PCNT_S 0 ++#define PAS_STATUS_DCNT_M 0x00000000ffff0000ull ++#define PAS_STATUS_DCNT_S 16 ++#define PAS_STATUS_BPCNT_M 0x0000ffff00000000ull ++#define PAS_STATUS_BPCNT_S 32 ++#define PAS_STATUS_CAUSE_M 0xf000000000000000ull ++#define PAS_STATUS_TIMER 0x1000000000000000ull ++#define PAS_STATUS_ERROR 0x2000000000000000ull ++#define PAS_STATUS_SOFT 0x4000000000000000ull ++#define PAS_STATUS_INT 0x8000000000000000ull ++ ++#define PAS_IOB_DMA_RXCH_CFG(i) (0x1100 + (i)*4) ++#define PAS_IOB_DMA_RXCH_CFG_CNTTH_M 0x00000fff ++#define PAS_IOB_DMA_RXCH_CFG_CNTTH_S 0 ++#define PAS_IOB_DMA_RXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_RXCH_CFG_CNTTH_S) & \ ++ PAS_IOB_DMA_RXCH_CFG_CNTTH_M) ++#define PAS_IOB_DMA_TXCH_CFG(i) (0x1200 + (i)*4) ++#define PAS_IOB_DMA_TXCH_CFG_CNTTH_M 0x00000fff ++#define PAS_IOB_DMA_TXCH_CFG_CNTTH_S 0 ++#define PAS_IOB_DMA_TXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_TXCH_CFG_CNTTH_S) & \ ++ PAS_IOB_DMA_TXCH_CFG_CNTTH_M) ++#define PAS_IOB_DMA_RXCH_STAT(i) (0x1300 + (i)*4) ++#define PAS_IOB_DMA_RXCH_STAT_INTGEN 0x00001000 ++#define PAS_IOB_DMA_RXCH_STAT_CNTDEL_M 0x00000fff ++#define PAS_IOB_DMA_RXCH_STAT_CNTDEL_S 0 ++#define PAS_IOB_DMA_RXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_RXCH_STAT_CNTDEL_S) &\ ++ PAS_IOB_DMA_RXCH_STAT_CNTDEL_M) ++#define PAS_IOB_DMA_TXCH_STAT(i) (0x1400 + (i)*4) ++#define PAS_IOB_DMA_TXCH_STAT_INTGEN 0x00001000 ++#define PAS_IOB_DMA_TXCH_STAT_CNTDEL_M 0x00000fff ++#define PAS_IOB_DMA_TXCH_STAT_CNTDEL_S 0 ++#define PAS_IOB_DMA_TXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_TXCH_STAT_CNTDEL_S) &\ ++ PAS_IOB_DMA_TXCH_STAT_CNTDEL_M) ++#define PAS_IOB_DMA_RXCH_RESET(i) (0x1500 + (i)*4) ++#define PAS_IOB_DMA_RXCH_RESET_PCNT_M 0xffff0000 ++#define PAS_IOB_DMA_RXCH_RESET_PCNT_S 16 ++#define PAS_IOB_DMA_RXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_RXCH_RESET_PCNT_S) & \ ++ PAS_IOB_DMA_RXCH_RESET_PCNT_M) ++#define PAS_IOB_DMA_RXCH_RESET_PCNTRST 0x00000020 ++#define PAS_IOB_DMA_RXCH_RESET_DCNTRST 0x00000010 ++#define PAS_IOB_DMA_RXCH_RESET_TINTC 0x00000008 ++#define PAS_IOB_DMA_RXCH_RESET_DINTC 0x00000004 ++#define PAS_IOB_DMA_RXCH_RESET_SINTC 0x00000002 ++#define PAS_IOB_DMA_RXCH_RESET_PINTC 0x00000001 ++#define PAS_IOB_DMA_TXCH_RESET(i) (0x1600 + (i)*4) ++#define PAS_IOB_DMA_TXCH_RESET_PCNT_M 0xffff0000 ++#define PAS_IOB_DMA_TXCH_RESET_PCNT_S 16 ++#define PAS_IOB_DMA_TXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_TXCH_RESET_PCNT_S) & \ ++ PAS_IOB_DMA_TXCH_RESET_PCNT_M) ++#define PAS_IOB_DMA_TXCH_RESET_PCNTRST 0x00000020 ++#define PAS_IOB_DMA_TXCH_RESET_DCNTRST 0x00000010 ++#define PAS_IOB_DMA_TXCH_RESET_TINTC 0x00000008 ++#define PAS_IOB_DMA_TXCH_RESET_DINTC 0x00000004 ++#define PAS_IOB_DMA_TXCH_RESET_SINTC 0x00000002 ++#define PAS_IOB_DMA_TXCH_RESET_PINTC 0x00000001 ++ ++#define PAS_IOB_DMA_COM_TIMEOUTCFG 0x1700 ++#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M 0x00ffffff ++#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S 0 ++#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(x) (((x) << PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S) & \ ++ PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M) ++ ++/* Transmit descriptor fields */ ++#define XCT_MACTX_T 0x8000000000000000ull ++#define XCT_MACTX_ST 0x4000000000000000ull ++#define XCT_MACTX_NORES 0x0000000000000000ull ++#define XCT_MACTX_8BRES 0x1000000000000000ull ++#define XCT_MACTX_24BRES 0x2000000000000000ull ++#define XCT_MACTX_40BRES 0x3000000000000000ull ++#define XCT_MACTX_I 0x0800000000000000ull ++#define XCT_MACTX_O 0x0400000000000000ull ++#define XCT_MACTX_E 0x0200000000000000ull ++#define XCT_MACTX_VLAN_M 0x0180000000000000ull ++#define XCT_MACTX_VLAN_NOP 0x0000000000000000ull ++#define XCT_MACTX_VLAN_REMOVE 0x0080000000000000ull ++#define XCT_MACTX_VLAN_INSERT 0x0100000000000000ull ++#define XCT_MACTX_VLAN_REPLACE 0x0180000000000000ull ++#define XCT_MACTX_CRC_M 0x0060000000000000ull ++#define XCT_MACTX_CRC_NOP 0x0000000000000000ull ++#define XCT_MACTX_CRC_INSERT 0x0020000000000000ull ++#define XCT_MACTX_CRC_PAD 0x0040000000000000ull ++#define XCT_MACTX_CRC_REPLACE 0x0060000000000000ull ++#define XCT_MACTX_SS 0x0010000000000000ull ++#define XCT_MACTX_LLEN_M 0x00007fff00000000ull ++#define XCT_MACTX_LLEN_S 32ull ++#define XCT_MACTX_LLEN(x) ((((long)(x)) << XCT_MACTX_LLEN_S) & \ ++ XCT_MACTX_LLEN_M) ++#define XCT_MACTX_IPH_M 0x00000000f8000000ull ++#define XCT_MACTX_IPH_S 27ull ++#define XCT_MACTX_IPH(x) ((((long)(x)) << XCT_MACTX_IPH_S) & \ ++ XCT_MACTX_IPH_M) ++#define XCT_MACTX_IPO_M 0x0000000007c00000ull ++#define XCT_MACTX_IPO_S 22ull ++#define XCT_MACTX_IPO(x) ((((long)(x)) << XCT_MACTX_IPO_S) & \ ++ XCT_MACTX_IPO_M) ++#define XCT_MACTX_CSUM_M 0x0000000000000060ull ++#define XCT_MACTX_CSUM_NOP 0x0000000000000000ull ++#define XCT_MACTX_CSUM_TCP 0x0000000000000040ull ++#define XCT_MACTX_CSUM_UDP 0x0000000000000060ull ++#define XCT_MACTX_V6 0x0000000000000010ull ++#define XCT_MACTX_C 0x0000000000000004ull ++#define XCT_MACTX_AL2 0x0000000000000002ull ++ ++#define XCT_PTR_T 0x8000000000000000ull ++#define XCT_PTR_LEN_M 0x7ffff00000000000ull ++#define XCT_PTR_LEN_S 44 ++#define XCT_PTR_LEN(x) ((((long)(x)) << XCT_PTR_LEN_S) & \ ++ XCT_PTR_LEN_M) ++#define XCT_PTR_ADDR_M 0x00000fffffffffffull ++#define XCT_PTR_ADDR_S 0 ++#define XCT_PTR_ADDR(x) ((((long)(x)) << XCT_PTR_ADDR_S) & \ ++ XCT_PTR_ADDR_M) ++ ++/* Function descriptor fields */ ++#define XCT_FUN_T 0x8000000000000000ull ++#define XCT_FUN_ST 0x4000000000000000ull ++#define XCT_FUN_NORES 0x0000000000000000ull ++#define XCT_FUN_8BRES 0x1000000000000000ull ++#define XCT_FUN_24BRES 0x2000000000000000ull ++#define XCT_FUN_40BRES 0x3000000000000000ull ++#define XCT_FUN_I 0x0800000000000000ull ++#define XCT_FUN_O 0x0400000000000000ull ++#define XCT_FUN_E 0x0200000000000000ull ++#define XCT_FUN_FUN_S 54 ++#define XCT_FUN_FUN_M 0x01c0000000000000ull ++#define XCT_FUN_FUN(num) ((((long)(num)) << XCT_FUN_FUN_S) & \ ++ XCT_FUN_FUN_M) ++#define XCT_FUN_CRM_NOP 0x0000000000000000ull ++#define XCT_FUN_CRM_SIG 0x0008000000000000ull ++#define XCT_FUN_CRM_ENC 0x0010000000000000ull ++#define XCT_FUN_CRM_DEC 0x0018000000000000ull ++#define XCT_FUN_CRM_SIG_ENC 0x0020000000000000ull ++#define XCT_FUN_CRM_ENC_SIG 0x0028000000000000ull ++#define XCT_FUN_CRM_SIG_DEC 0x0030000000000000ull ++#define XCT_FUN_CRM_DEC_SIG 0x0038000000000000ull ++#define XCT_FUN_LLEN_M 0x0007ffff00000000ull ++#define XCT_FUN_LLEN_S 32ULL ++#define XCT_FUN_LLEN(x) ((((long)(x)) << XCT_FUN_LLEN_S) & \ ++ XCT_FUN_LLEN_M) ++#define XCT_FUN_SHL_M 0x00000000f8000000ull ++#define XCT_FUN_SHL_S 27ull ++#define XCT_FUN_SHL(x) ((((long)(x)) << XCT_FUN_SHL_S) & \ ++ XCT_FUN_SHL_M) ++#define XCT_FUN_CHL_M 0x0000000007c00000ull ++#define XCT_FUN_CHL_S 22ull ++#define XCT_FUN_CHL(x) ((((long)(x)) << XCT_FUN_CHL_S) & \ ++ XCT_FUN_CHL_M) ++#define XCT_FUN_HSZ_M 0x00000000003c0000ull ++#define XCT_FUN_HSZ_S 18ull ++#define XCT_FUN_HSZ(x) ((((long)(x)) << XCT_FUN_HSZ_S) & \ ++ XCT_FUN_HSZ_M) ++#define XCT_FUN_ALG_DES 0x0000000000000000ull ++#define XCT_FUN_ALG_3DES 0x0000000000008000ull ++#define XCT_FUN_ALG_AES 0x0000000000010000ull ++#define XCT_FUN_ALG_ARC 0x0000000000018000ull ++#define XCT_FUN_ALG_KASUMI 0x0000000000020000ull ++#define XCT_FUN_BCM_ECB 0x0000000000000000ull ++#define XCT_FUN_BCM_CBC 0x0000000000001000ull ++#define XCT_FUN_BCM_CFB 0x0000000000002000ull ++#define XCT_FUN_BCM_OFB 0x0000000000003000ull ++#define XCT_FUN_BCM_CNT 0x0000000000003800ull ++#define XCT_FUN_BCM_KAS_F8 0x0000000000002800ull ++#define XCT_FUN_BCM_KAS_F9 0x0000000000001800ull ++#define XCT_FUN_BCP_NO_PAD 0x0000000000000000ull ++#define XCT_FUN_BCP_ZRO 0x0000000000000200ull ++#define XCT_FUN_BCP_PL 0x0000000000000400ull ++#define XCT_FUN_BCP_INCR 0x0000000000000600ull ++#define XCT_FUN_SIG_MD5 (0ull << 4) ++#define XCT_FUN_SIG_SHA1 (2ull << 4) ++#define XCT_FUN_SIG_HMAC_MD5 (8ull << 4) ++#define XCT_FUN_SIG_HMAC_SHA1 (10ull << 4) ++#define XCT_FUN_A 0x0000000000000008ull ++#define XCT_FUN_C 0x0000000000000004ull ++#define XCT_FUN_AL2 0x0000000000000002ull ++#define XCT_FUN_SE 0x0000000000000001ull ++ ++#define XCT_FUN_SRC_PTR(len, addr) (XCT_PTR_LEN(len) | XCT_PTR_ADDR(addr)) ++#define XCT_FUN_DST_PTR(len, addr) (XCT_FUN_SRC_PTR(len, addr) | \ ++ 0x8000000000000000ull) ++ ++#define XCT_CTRL_HDR_FUN_NUM_M 0x01c0000000000000ull ++#define XCT_CTRL_HDR_FUN_NUM_S 54 ++#define XCT_CTRL_HDR_LEN_M 0x0007ffff00000000ull ++#define XCT_CTRL_HDR_LEN_S 32 ++#define XCT_CTRL_HDR_REG_M 0x00000000000000ffull ++#define XCT_CTRL_HDR_REG_S 0 ++ ++#define XCT_CTRL_HDR(funcN,len,reg) (0x9400000000000000ull | \ ++ ((((long)(funcN)) << XCT_CTRL_HDR_FUN_NUM_S) \ ++ & XCT_CTRL_HDR_FUN_NUM_M) | \ ++ ((((long)(len)) << \ ++ XCT_CTRL_HDR_LEN_S) & XCT_CTRL_HDR_LEN_M) | \ ++ ((((long)(reg)) << \ ++ XCT_CTRL_HDR_REG_S) & XCT_CTRL_HDR_REG_M)) ++ ++/* Function config command options */ ++#define DMA_CALGO_DES 0x00 ++#define DMA_CALGO_3DES 0x01 ++#define DMA_CALGO_AES 0x02 ++#define DMA_CALGO_ARC 0x03 ++ ++#define DMA_FN_CIV0 0x02 ++#define DMA_FN_CIV1 0x03 ++#define DMA_FN_HKEY0 0x0a ++ ++#define XCT_PTR_ADDR_LEN(ptr) ((ptr) & XCT_PTR_ADDR_M), \ ++ (((ptr) & XCT_PTR_LEN_M) >> XCT_PTR_LEN_S) ++ ++#endif /* PASEMI_FNU_H */ +diff -Nur linux-3.0.4.orig/crypto/ocf/random.c linux-3.0.4/crypto/ocf/random.c +--- linux-3.0.4.orig/crypto/ocf/random.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/random.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,317 @@ ++/* ++ * A system independant way of adding entropy to the kernels pool ++ * this way the drivers can focus on the real work and we can take ++ * care of pushing it to the appropriate place in the kernel. ++ * ++ * This should be fast and callable from timers/interrupts ++ * ++ * Written by David McCullough ++ * Copyright (C) 2006-2010 David McCullough ++ * Copyright (C) 2004-2005 Intel Corporation. ++ * ++ * LICENSE TERMS ++ * ++ * The free distribution and use of this software in both source and binary ++ * form is allowed (with or without changes) provided that: ++ * ++ * 1. distributions of this source code include the above copyright ++ * notice, this list of conditions and the following disclaimer; ++ * ++ * 2. distributions in binary form include the above copyright ++ * notice, this list of conditions and the following disclaimer ++ * in the documentation and/or other associated materials; ++ * ++ * 3. the copyright holder's name is not used to endorse products ++ * built using this software without specific written permission. ++ * ++ * ALTERNATIVELY, provided that this notice is retained in full, this product ++ * may be distributed under the terms of the GNU General Public License (GPL), ++ * in which case the provisions of the GPL apply INSTEAD OF those given above. ++ * ++ * DISCLAIMER ++ * ++ * This software is provided 'as is' with no explicit or implied warranties ++ * in respect of its properties, including, but not limited to, correctness ++ * and/or fitness for purpose. ++ */ ++ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifdef CONFIG_OCF_FIPS ++#include "rndtest.h" ++#endif ++ ++#ifndef HAS_RANDOM_INPUT_WAIT ++#error "Please do not enable OCF_RANDOMHARVEST unless you have applied patches" ++#endif ++ ++/* ++ * a hack to access the debug levels from the crypto driver ++ */ ++extern int crypto_debug; ++#define debug crypto_debug ++ ++/* ++ * a list of all registered random providers ++ */ ++static LIST_HEAD(random_ops); ++static int started = 0; ++static int initted = 0; ++ ++struct random_op { ++ struct list_head random_list; ++ u_int32_t driverid; ++ int (*read_random)(void *arg, u_int32_t *buf, int len); ++ void *arg; ++}; ++ ++static int random_proc(void *arg); ++ ++static pid_t randomproc = (pid_t) -1; ++static spinlock_t random_lock; ++ ++/* ++ * just init the spin locks ++ */ ++static int ++crypto_random_init(void) ++{ ++ spin_lock_init(&random_lock); ++ initted = 1; ++ return(0); ++} ++ ++/* ++ * Add the given random reader to our list (if not present) ++ * and start the thread (if not already started) ++ * ++ * we have to assume that driver id is ok for now ++ */ ++int ++crypto_rregister( ++ u_int32_t driverid, ++ int (*read_random)(void *arg, u_int32_t *buf, int len), ++ void *arg) ++{ ++ unsigned long flags; ++ int ret = 0; ++ struct random_op *rops, *tmp; ++ ++ dprintk("%s,%d: %s(0x%x, %p, %p)\n", __FILE__, __LINE__, ++ __FUNCTION__, driverid, read_random, arg); ++ ++ if (!initted) ++ crypto_random_init(); ++ ++#if 0 ++ struct cryptocap *cap; ++ ++ cap = crypto_checkdriver(driverid); ++ if (!cap) ++ return EINVAL; ++#endif ++ ++ list_for_each_entry_safe(rops, tmp, &random_ops, random_list) { ++ if (rops->driverid == driverid && rops->read_random == read_random) ++ return EEXIST; ++ } ++ ++ rops = (struct random_op *) kmalloc(sizeof(*rops), GFP_KERNEL); ++ if (!rops) ++ return ENOMEM; ++ ++ rops->driverid = driverid; ++ rops->read_random = read_random; ++ rops->arg = arg; ++ ++ spin_lock_irqsave(&random_lock, flags); ++ list_add_tail(&rops->random_list, &random_ops); ++ if (!started) { ++ randomproc = kernel_thread(random_proc, NULL, CLONE_FS|CLONE_FILES); ++ if (randomproc < 0) { ++ ret = randomproc; ++ printk("crypto: crypto_rregister cannot start random thread; " ++ "error %d", ret); ++ } else ++ started = 1; ++ } ++ spin_unlock_irqrestore(&random_lock, flags); ++ ++ return ret; ++} ++EXPORT_SYMBOL(crypto_rregister); ++ ++int ++crypto_runregister_all(u_int32_t driverid) ++{ ++ struct random_op *rops, *tmp; ++ unsigned long flags; ++ ++ dprintk("%s,%d: %s(0x%x)\n", __FILE__, __LINE__, __FUNCTION__, driverid); ++ ++ list_for_each_entry_safe(rops, tmp, &random_ops, random_list) { ++ if (rops->driverid == driverid) { ++ list_del(&rops->random_list); ++ kfree(rops); ++ } ++ } ++ ++ spin_lock_irqsave(&random_lock, flags); ++ if (list_empty(&random_ops) && started) ++ kill_proc(randomproc, SIGKILL, 1); ++ spin_unlock_irqrestore(&random_lock, flags); ++ return(0); ++} ++EXPORT_SYMBOL(crypto_runregister_all); ++ ++/* ++ * while we can add entropy to random.c continue to read random data from ++ * the drivers and push it to random. ++ */ ++static int ++random_proc(void *arg) ++{ ++ int n; ++ int wantcnt; ++ int bufcnt = 0; ++ int retval = 0; ++ int *buf = NULL; ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++ daemonize(); ++ spin_lock_irq(¤t->sigmask_lock); ++ sigemptyset(¤t->blocked); ++ recalc_sigpending(current); ++ spin_unlock_irq(¤t->sigmask_lock); ++ sprintf(current->comm, "ocf-random"); ++#else ++ daemonize("ocf-random"); ++ allow_signal(SIGKILL); ++#endif ++ ++ (void) get_fs(); ++ set_fs(get_ds()); ++ ++#ifdef CONFIG_OCF_FIPS ++#define NUM_INT (RNDTEST_NBYTES/sizeof(int)) ++#else ++#define NUM_INT 32 ++#endif ++ ++ /* ++ * some devices can transferr their RNG data direct into memory, ++ * so make sure it is device friendly ++ */ ++ buf = kmalloc(NUM_INT * sizeof(int), GFP_DMA); ++ if (NULL == buf) { ++ printk("crypto: RNG could not allocate memory\n"); ++ retval = -ENOMEM; ++ goto bad_alloc; ++ } ++ ++ wantcnt = NUM_INT; /* start by adding some entropy */ ++ ++ /* ++ * its possible due to errors or driver removal that we no longer ++ * have anything to do, if so exit or we will consume all the CPU ++ * doing nothing ++ */ ++ while (!list_empty(&random_ops)) { ++ struct random_op *rops, *tmp; ++ ++#ifdef CONFIG_OCF_FIPS ++ if (wantcnt) ++ wantcnt = NUM_INT; /* FIPs mode can do 20000 bits or none */ ++#endif ++ ++ /* see if we can get enough entropy to make the world ++ * a better place. ++ */ ++ while (bufcnt < wantcnt && bufcnt < NUM_INT) { ++ list_for_each_entry_safe(rops, tmp, &random_ops, random_list) { ++ ++ n = (*rops->read_random)(rops->arg, &buf[bufcnt], ++ NUM_INT - bufcnt); ++ ++ /* on failure remove the random number generator */ ++ if (n == -1) { ++ list_del(&rops->random_list); ++ printk("crypto: RNG (driverid=0x%x) failed, disabling\n", ++ rops->driverid); ++ kfree(rops); ++ } else if (n > 0) ++ bufcnt += n; ++ } ++ /* give up CPU for a bit, just in case as this is a loop */ ++ schedule(); ++ } ++ ++ ++#ifdef CONFIG_OCF_FIPS ++ if (bufcnt > 0 && rndtest_buf((unsigned char *) &buf[0])) { ++ dprintk("crypto: buffer had fips errors, discarding\n"); ++ bufcnt = 0; ++ } ++#endif ++ ++ /* ++ * if we have a certified buffer, we can send some data ++ * to /dev/random and move along ++ */ ++ if (bufcnt > 0) { ++ /* add what we have */ ++ random_input_words(buf, bufcnt, bufcnt*sizeof(int)*8); ++ bufcnt = 0; ++ } ++ ++ /* give up CPU for a bit so we don't hog while filling */ ++ schedule(); ++ ++ /* wait for needing more */ ++ wantcnt = random_input_wait(); ++ ++ if (wantcnt <= 0) ++ wantcnt = 0; /* try to get some info again */ ++ else ++ /* round up to one word or we can loop forever */ ++ wantcnt = (wantcnt + (sizeof(int)*8)) / (sizeof(int)*8); ++ if (wantcnt > NUM_INT) { ++ wantcnt = NUM_INT; ++ } ++ ++ if (signal_pending(current)) { ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++ spin_lock_irq(¤t->sigmask_lock); ++#endif ++ flush_signals(current); ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++ spin_unlock_irq(¤t->sigmask_lock); ++#endif ++ } ++ } ++ ++ kfree(buf); ++ ++bad_alloc: ++ spin_lock_irq(&random_lock); ++ randomproc = (pid_t) -1; ++ started = 0; ++ spin_unlock_irq(&random_lock); ++ ++ return retval; ++} ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/rndtest.c linux-3.0.4/crypto/ocf/rndtest.c +--- linux-3.0.4.orig/crypto/ocf/rndtest.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/rndtest.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,300 @@ ++/* $OpenBSD$ */ ++ ++/* ++ * OCF/Linux port done by David McCullough ++ * Copyright (C) 2006-2010 David McCullough ++ * Copyright (C) 2004-2005 Intel Corporation. ++ * The license and original author are listed below. ++ * ++ * Copyright (c) 2002 Jason L. Wright (jason@thought.net) ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. All advertising materials mentioning features or use of this software ++ * must display the following acknowledgement: ++ * This product includes software developed by Jason L. Wright ++ * 4. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++ * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, ++ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ++ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "rndtest.h" ++ ++static struct rndtest_stats rndstats; ++ ++static void rndtest_test(struct rndtest_state *); ++ ++/* The tests themselves */ ++static int rndtest_monobit(struct rndtest_state *); ++static int rndtest_runs(struct rndtest_state *); ++static int rndtest_longruns(struct rndtest_state *); ++static int rndtest_chi_4(struct rndtest_state *); ++ ++static int rndtest_runs_check(struct rndtest_state *, int, int *); ++static void rndtest_runs_record(struct rndtest_state *, int, int *); ++ ++static const struct rndtest_testfunc { ++ int (*test)(struct rndtest_state *); ++} rndtest_funcs[] = { ++ { rndtest_monobit }, ++ { rndtest_runs }, ++ { rndtest_chi_4 }, ++ { rndtest_longruns }, ++}; ++ ++#define RNDTEST_NTESTS (sizeof(rndtest_funcs)/sizeof(rndtest_funcs[0])) ++ ++static void ++rndtest_test(struct rndtest_state *rsp) ++{ ++ int i, rv = 0; ++ ++ rndstats.rst_tests++; ++ for (i = 0; i < RNDTEST_NTESTS; i++) ++ rv |= (*rndtest_funcs[i].test)(rsp); ++ rsp->rs_discard = (rv != 0); ++} ++ ++ ++extern int crypto_debug; ++#define rndtest_verbose 2 ++#define rndtest_report(rsp, failure, fmt, a...) \ ++ { if (failure || crypto_debug) { printk("rng_test: " fmt "\n", a); } else; } ++ ++#define RNDTEST_MONOBIT_MINONES 9725 ++#define RNDTEST_MONOBIT_MAXONES 10275 ++ ++static int ++rndtest_monobit(struct rndtest_state *rsp) ++{ ++ int i, ones = 0, j; ++ u_int8_t r; ++ ++ for (i = 0; i < RNDTEST_NBYTES; i++) { ++ r = rsp->rs_buf[i]; ++ for (j = 0; j < 8; j++, r <<= 1) ++ if (r & 0x80) ++ ones++; ++ } ++ if (ones > RNDTEST_MONOBIT_MINONES && ++ ones < RNDTEST_MONOBIT_MAXONES) { ++ if (rndtest_verbose > 1) ++ rndtest_report(rsp, 0, "monobit pass (%d < %d < %d)", ++ RNDTEST_MONOBIT_MINONES, ones, ++ RNDTEST_MONOBIT_MAXONES); ++ return (0); ++ } else { ++ if (rndtest_verbose) ++ rndtest_report(rsp, 1, ++ "monobit failed (%d ones)", ones); ++ rndstats.rst_monobit++; ++ return (-1); ++ } ++} ++ ++#define RNDTEST_RUNS_NINTERVAL 6 ++ ++static const struct rndtest_runs_tabs { ++ u_int16_t min, max; ++} rndtest_runs_tab[] = { ++ { 2343, 2657 }, ++ { 1135, 1365 }, ++ { 542, 708 }, ++ { 251, 373 }, ++ { 111, 201 }, ++ { 111, 201 }, ++}; ++ ++static int ++rndtest_runs(struct rndtest_state *rsp) ++{ ++ int i, j, ones, zeros, rv = 0; ++ int onei[RNDTEST_RUNS_NINTERVAL], zeroi[RNDTEST_RUNS_NINTERVAL]; ++ u_int8_t c; ++ ++ bzero(onei, sizeof(onei)); ++ bzero(zeroi, sizeof(zeroi)); ++ ones = zeros = 0; ++ for (i = 0; i < RNDTEST_NBYTES; i++) { ++ c = rsp->rs_buf[i]; ++ for (j = 0; j < 8; j++, c <<= 1) { ++ if (c & 0x80) { ++ ones++; ++ rndtest_runs_record(rsp, zeros, zeroi); ++ zeros = 0; ++ } else { ++ zeros++; ++ rndtest_runs_record(rsp, ones, onei); ++ ones = 0; ++ } ++ } ++ } ++ rndtest_runs_record(rsp, ones, onei); ++ rndtest_runs_record(rsp, zeros, zeroi); ++ ++ rv |= rndtest_runs_check(rsp, 0, zeroi); ++ rv |= rndtest_runs_check(rsp, 1, onei); ++ ++ if (rv) ++ rndstats.rst_runs++; ++ ++ return (rv); ++} ++ ++static void ++rndtest_runs_record(struct rndtest_state *rsp, int len, int *intrv) ++{ ++ if (len == 0) ++ return; ++ if (len > RNDTEST_RUNS_NINTERVAL) ++ len = RNDTEST_RUNS_NINTERVAL; ++ len -= 1; ++ intrv[len]++; ++} ++ ++static int ++rndtest_runs_check(struct rndtest_state *rsp, int val, int *src) ++{ ++ int i, rv = 0; ++ ++ for (i = 0; i < RNDTEST_RUNS_NINTERVAL; i++) { ++ if (src[i] < rndtest_runs_tab[i].min || ++ src[i] > rndtest_runs_tab[i].max) { ++ rndtest_report(rsp, 1, ++ "%s interval %d failed (%d, %d-%d)", ++ val ? "ones" : "zeros", ++ i + 1, src[i], rndtest_runs_tab[i].min, ++ rndtest_runs_tab[i].max); ++ rv = -1; ++ } else { ++ rndtest_report(rsp, 0, ++ "runs pass %s interval %d (%d < %d < %d)", ++ val ? "ones" : "zeros", ++ i + 1, rndtest_runs_tab[i].min, src[i], ++ rndtest_runs_tab[i].max); ++ } ++ } ++ return (rv); ++} ++ ++static int ++rndtest_longruns(struct rndtest_state *rsp) ++{ ++ int i, j, ones = 0, zeros = 0, maxones = 0, maxzeros = 0; ++ u_int8_t c; ++ ++ for (i = 0; i < RNDTEST_NBYTES; i++) { ++ c = rsp->rs_buf[i]; ++ for (j = 0; j < 8; j++, c <<= 1) { ++ if (c & 0x80) { ++ zeros = 0; ++ ones++; ++ if (ones > maxones) ++ maxones = ones; ++ } else { ++ ones = 0; ++ zeros++; ++ if (zeros > maxzeros) ++ maxzeros = zeros; ++ } ++ } ++ } ++ ++ if (maxones < 26 && maxzeros < 26) { ++ rndtest_report(rsp, 0, "longruns pass (%d ones, %d zeros)", ++ maxones, maxzeros); ++ return (0); ++ } else { ++ rndtest_report(rsp, 1, "longruns fail (%d ones, %d zeros)", ++ maxones, maxzeros); ++ rndstats.rst_longruns++; ++ return (-1); ++ } ++} ++ ++/* ++ * chi^2 test over 4 bits: (this is called the poker test in FIPS 140-2, ++ * but it is really the chi^2 test over 4 bits (the poker test as described ++ * by Knuth vol 2 is something different, and I take him as authoritative ++ * on nomenclature over NIST). ++ */ ++#define RNDTEST_CHI4_K 16 ++#define RNDTEST_CHI4_K_MASK (RNDTEST_CHI4_K - 1) ++ ++/* ++ * The unnormalized values are used so that we don't have to worry about ++ * fractional precision. The "real" value is found by: ++ * (V - 1562500) * (16 / 5000) = Vn (where V is the unnormalized value) ++ */ ++#define RNDTEST_CHI4_VMIN 1563181 /* 2.1792 */ ++#define RNDTEST_CHI4_VMAX 1576929 /* 46.1728 */ ++ ++static int ++rndtest_chi_4(struct rndtest_state *rsp) ++{ ++ unsigned int freq[RNDTEST_CHI4_K], i, sum; ++ ++ for (i = 0; i < RNDTEST_CHI4_K; i++) ++ freq[i] = 0; ++ ++ /* Get number of occurances of each 4 bit pattern */ ++ for (i = 0; i < RNDTEST_NBYTES; i++) { ++ freq[(rsp->rs_buf[i] >> 4) & RNDTEST_CHI4_K_MASK]++; ++ freq[(rsp->rs_buf[i] >> 0) & RNDTEST_CHI4_K_MASK]++; ++ } ++ ++ for (i = 0, sum = 0; i < RNDTEST_CHI4_K; i++) ++ sum += freq[i] * freq[i]; ++ ++ if (sum >= 1563181 && sum <= 1576929) { ++ rndtest_report(rsp, 0, "chi^2(4): pass (sum %u)", sum); ++ return (0); ++ } else { ++ rndtest_report(rsp, 1, "chi^2(4): failed (sum %u)", sum); ++ rndstats.rst_chi++; ++ return (-1); ++ } ++} ++ ++int ++rndtest_buf(unsigned char *buf) ++{ ++ struct rndtest_state rsp; ++ ++ memset(&rsp, 0, sizeof(rsp)); ++ rsp.rs_buf = buf; ++ rndtest_test(&rsp); ++ return(rsp.rs_discard); ++} ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/rndtest.h linux-3.0.4/crypto/ocf/rndtest.h +--- linux-3.0.4.orig/crypto/ocf/rndtest.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/rndtest.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,54 @@ ++/* $FreeBSD: src/sys/dev/rndtest/rndtest.h,v 1.1 2003/03/11 22:54:44 sam Exp $ */ ++/* $OpenBSD$ */ ++ ++/* ++ * Copyright (c) 2002 Jason L. Wright (jason@thought.net) ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. All advertising materials mentioning features or use of this software ++ * must display the following acknowledgement: ++ * This product includes software developed by Jason L. Wright ++ * 4. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++ * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, ++ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ++ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++ ++/* Some of the tests depend on these values */ ++#define RNDTEST_NBYTES 2500 ++#define RNDTEST_NBITS (8 * RNDTEST_NBYTES) ++ ++struct rndtest_state { ++ int rs_discard; /* discard/accept random data */ ++ u_int8_t *rs_buf; ++}; ++ ++struct rndtest_stats { ++ u_int32_t rst_discard; /* number of bytes discarded */ ++ u_int32_t rst_tests; /* number of test runs */ ++ u_int32_t rst_monobit; /* monobit test failures */ ++ u_int32_t rst_runs; /* 0/1 runs failures */ ++ u_int32_t rst_longruns; /* longruns failures */ ++ u_int32_t rst_chi; /* chi^2 failures */ ++}; ++ ++extern int rndtest_buf(unsigned char *buf); +diff -Nur linux-3.0.4.orig/crypto/ocf/safe/Makefile linux-3.0.4/crypto/ocf/safe/Makefile +--- linux-3.0.4.orig/crypto/ocf/safe/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/safe/Makefile 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,12 @@ ++# for SGlinux builds ++-include $(ROOTDIR)/modules/.config ++ ++obj-$(CONFIG_OCF_SAFE) += safe.o ++ ++obj ?= . ++EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ ++ ++ifdef TOPDIR ++-include $(TOPDIR)/Rules.make ++endif ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/safe/hmachack.h linux-3.0.4/crypto/ocf/safe/hmachack.h +--- linux-3.0.4.orig/crypto/ocf/safe/hmachack.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/safe/hmachack.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,37 @@ ++/* ++ * until we find a cleaner way, include the BSD md5/sha1 code ++ * here ++ */ ++#ifdef HMAC_HACK ++#define LITTLE_ENDIAN 1234 ++#define BIG_ENDIAN 4321 ++#ifdef __LITTLE_ENDIAN ++#define BYTE_ORDER LITTLE_ENDIAN ++#endif ++#ifdef __BIG_ENDIAN ++#define BYTE_ORDER BIG_ENDIAN ++#endif ++ ++u_int8_t hmac_ipad_buffer[64] = { ++ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, ++ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, ++ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, ++ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, ++ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, ++ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, ++ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, ++ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36 ++}; ++ ++u_int8_t hmac_opad_buffer[64] = { ++ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, ++ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, ++ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, ++ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, ++ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, ++ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, ++ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, ++ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C ++}; ++#endif /* HMAC_HACK */ ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/safe/md5.c linux-3.0.4/crypto/ocf/safe/md5.c +--- linux-3.0.4.orig/crypto/ocf/safe/md5.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/safe/md5.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,308 @@ ++/* $KAME: md5.c,v 1.5 2000/11/08 06:13:08 itojun Exp $ */ ++/* ++ * Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. Neither the name of the project nor the names of its contributors ++ * may be used to endorse or promote products derived from this software ++ * without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND ++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE ++ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ++ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ++ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF ++ * SUCH DAMAGE. ++ */ ++ ++#if 0 ++#include ++__FBSDID("$FreeBSD: src/sys/crypto/md5.c,v 1.9 2004/01/27 19:49:19 des Exp $"); ++ ++#include ++#include ++#include ++#include ++#include ++#endif ++ ++#define SHIFT(X, s) (((X) << (s)) | ((X) >> (32 - (s)))) ++ ++#define F(X, Y, Z) (((X) & (Y)) | ((~X) & (Z))) ++#define G(X, Y, Z) (((X) & (Z)) | ((Y) & (~Z))) ++#define H(X, Y, Z) ((X) ^ (Y) ^ (Z)) ++#define I(X, Y, Z) ((Y) ^ ((X) | (~Z))) ++ ++#define ROUND1(a, b, c, d, k, s, i) { \ ++ (a) = (a) + F((b), (c), (d)) + X[(k)] + T[(i)]; \ ++ (a) = SHIFT((a), (s)); \ ++ (a) = (b) + (a); \ ++} ++ ++#define ROUND2(a, b, c, d, k, s, i) { \ ++ (a) = (a) + G((b), (c), (d)) + X[(k)] + T[(i)]; \ ++ (a) = SHIFT((a), (s)); \ ++ (a) = (b) + (a); \ ++} ++ ++#define ROUND3(a, b, c, d, k, s, i) { \ ++ (a) = (a) + H((b), (c), (d)) + X[(k)] + T[(i)]; \ ++ (a) = SHIFT((a), (s)); \ ++ (a) = (b) + (a); \ ++} ++ ++#define ROUND4(a, b, c, d, k, s, i) { \ ++ (a) = (a) + I((b), (c), (d)) + X[(k)] + T[(i)]; \ ++ (a) = SHIFT((a), (s)); \ ++ (a) = (b) + (a); \ ++} ++ ++#define Sa 7 ++#define Sb 12 ++#define Sc 17 ++#define Sd 22 ++ ++#define Se 5 ++#define Sf 9 ++#define Sg 14 ++#define Sh 20 ++ ++#define Si 4 ++#define Sj 11 ++#define Sk 16 ++#define Sl 23 ++ ++#define Sm 6 ++#define Sn 10 ++#define So 15 ++#define Sp 21 ++ ++#define MD5_A0 0x67452301 ++#define MD5_B0 0xefcdab89 ++#define MD5_C0 0x98badcfe ++#define MD5_D0 0x10325476 ++ ++/* Integer part of 4294967296 times abs(sin(i)), where i is in radians. */ ++static const u_int32_t T[65] = { ++ 0, ++ 0xd76aa478, 0xe8c7b756, 0x242070db, 0xc1bdceee, ++ 0xf57c0faf, 0x4787c62a, 0xa8304613, 0xfd469501, ++ 0x698098d8, 0x8b44f7af, 0xffff5bb1, 0x895cd7be, ++ 0x6b901122, 0xfd987193, 0xa679438e, 0x49b40821, ++ ++ 0xf61e2562, 0xc040b340, 0x265e5a51, 0xe9b6c7aa, ++ 0xd62f105d, 0x2441453, 0xd8a1e681, 0xe7d3fbc8, ++ 0x21e1cde6, 0xc33707d6, 0xf4d50d87, 0x455a14ed, ++ 0xa9e3e905, 0xfcefa3f8, 0x676f02d9, 0x8d2a4c8a, ++ ++ 0xfffa3942, 0x8771f681, 0x6d9d6122, 0xfde5380c, ++ 0xa4beea44, 0x4bdecfa9, 0xf6bb4b60, 0xbebfbc70, ++ 0x289b7ec6, 0xeaa127fa, 0xd4ef3085, 0x4881d05, ++ 0xd9d4d039, 0xe6db99e5, 0x1fa27cf8, 0xc4ac5665, ++ ++ 0xf4292244, 0x432aff97, 0xab9423a7, 0xfc93a039, ++ 0x655b59c3, 0x8f0ccc92, 0xffeff47d, 0x85845dd1, ++ 0x6fa87e4f, 0xfe2ce6e0, 0xa3014314, 0x4e0811a1, ++ 0xf7537e82, 0xbd3af235, 0x2ad7d2bb, 0xeb86d391, ++}; ++ ++static const u_int8_t md5_paddat[MD5_BUFLEN] = { ++ 0x80, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, ++}; ++ ++static void md5_calc(u_int8_t *, md5_ctxt *); ++ ++void md5_init(ctxt) ++ md5_ctxt *ctxt; ++{ ++ ctxt->md5_n = 0; ++ ctxt->md5_i = 0; ++ ctxt->md5_sta = MD5_A0; ++ ctxt->md5_stb = MD5_B0; ++ ctxt->md5_stc = MD5_C0; ++ ctxt->md5_std = MD5_D0; ++ bzero(ctxt->md5_buf, sizeof(ctxt->md5_buf)); ++} ++ ++void md5_loop(ctxt, input, len) ++ md5_ctxt *ctxt; ++ u_int8_t *input; ++ u_int len; /* number of bytes */ ++{ ++ u_int gap, i; ++ ++ ctxt->md5_n += len * 8; /* byte to bit */ ++ gap = MD5_BUFLEN - ctxt->md5_i; ++ ++ if (len >= gap) { ++ bcopy((void *)input, (void *)(ctxt->md5_buf + ctxt->md5_i), ++ gap); ++ md5_calc(ctxt->md5_buf, ctxt); ++ ++ for (i = gap; i + MD5_BUFLEN <= len; i += MD5_BUFLEN) { ++ md5_calc((u_int8_t *)(input + i), ctxt); ++ } ++ ++ ctxt->md5_i = len - i; ++ bcopy((void *)(input + i), (void *)ctxt->md5_buf, ctxt->md5_i); ++ } else { ++ bcopy((void *)input, (void *)(ctxt->md5_buf + ctxt->md5_i), ++ len); ++ ctxt->md5_i += len; ++ } ++} ++ ++void md5_pad(ctxt) ++ md5_ctxt *ctxt; ++{ ++ u_int gap; ++ ++ /* Don't count up padding. Keep md5_n. */ ++ gap = MD5_BUFLEN - ctxt->md5_i; ++ if (gap > 8) { ++ bcopy(md5_paddat, ++ (void *)(ctxt->md5_buf + ctxt->md5_i), ++ gap - sizeof(ctxt->md5_n)); ++ } else { ++ /* including gap == 8 */ ++ bcopy(md5_paddat, (void *)(ctxt->md5_buf + ctxt->md5_i), ++ gap); ++ md5_calc(ctxt->md5_buf, ctxt); ++ bcopy((md5_paddat + gap), ++ (void *)ctxt->md5_buf, ++ MD5_BUFLEN - sizeof(ctxt->md5_n)); ++ } ++ ++ /* 8 byte word */ ++#if BYTE_ORDER == LITTLE_ENDIAN ++ bcopy(&ctxt->md5_n8[0], &ctxt->md5_buf[56], 8); ++#endif ++#if BYTE_ORDER == BIG_ENDIAN ++ ctxt->md5_buf[56] = ctxt->md5_n8[7]; ++ ctxt->md5_buf[57] = ctxt->md5_n8[6]; ++ ctxt->md5_buf[58] = ctxt->md5_n8[5]; ++ ctxt->md5_buf[59] = ctxt->md5_n8[4]; ++ ctxt->md5_buf[60] = ctxt->md5_n8[3]; ++ ctxt->md5_buf[61] = ctxt->md5_n8[2]; ++ ctxt->md5_buf[62] = ctxt->md5_n8[1]; ++ ctxt->md5_buf[63] = ctxt->md5_n8[0]; ++#endif ++ ++ md5_calc(ctxt->md5_buf, ctxt); ++} ++ ++void md5_result(digest, ctxt) ++ u_int8_t *digest; ++ md5_ctxt *ctxt; ++{ ++ /* 4 byte words */ ++#if BYTE_ORDER == LITTLE_ENDIAN ++ bcopy(&ctxt->md5_st8[0], digest, 16); ++#endif ++#if BYTE_ORDER == BIG_ENDIAN ++ digest[ 0] = ctxt->md5_st8[ 3]; digest[ 1] = ctxt->md5_st8[ 2]; ++ digest[ 2] = ctxt->md5_st8[ 1]; digest[ 3] = ctxt->md5_st8[ 0]; ++ digest[ 4] = ctxt->md5_st8[ 7]; digest[ 5] = ctxt->md5_st8[ 6]; ++ digest[ 6] = ctxt->md5_st8[ 5]; digest[ 7] = ctxt->md5_st8[ 4]; ++ digest[ 8] = ctxt->md5_st8[11]; digest[ 9] = ctxt->md5_st8[10]; ++ digest[10] = ctxt->md5_st8[ 9]; digest[11] = ctxt->md5_st8[ 8]; ++ digest[12] = ctxt->md5_st8[15]; digest[13] = ctxt->md5_st8[14]; ++ digest[14] = ctxt->md5_st8[13]; digest[15] = ctxt->md5_st8[12]; ++#endif ++} ++ ++static void md5_calc(b64, ctxt) ++ u_int8_t *b64; ++ md5_ctxt *ctxt; ++{ ++ u_int32_t A = ctxt->md5_sta; ++ u_int32_t B = ctxt->md5_stb; ++ u_int32_t C = ctxt->md5_stc; ++ u_int32_t D = ctxt->md5_std; ++#if BYTE_ORDER == LITTLE_ENDIAN ++ u_int32_t *X = (u_int32_t *)b64; ++#endif ++#if BYTE_ORDER == BIG_ENDIAN ++ /* 4 byte words */ ++ /* what a brute force but fast! */ ++ u_int32_t X[16]; ++ u_int8_t *y = (u_int8_t *)X; ++ y[ 0] = b64[ 3]; y[ 1] = b64[ 2]; y[ 2] = b64[ 1]; y[ 3] = b64[ 0]; ++ y[ 4] = b64[ 7]; y[ 5] = b64[ 6]; y[ 6] = b64[ 5]; y[ 7] = b64[ 4]; ++ y[ 8] = b64[11]; y[ 9] = b64[10]; y[10] = b64[ 9]; y[11] = b64[ 8]; ++ y[12] = b64[15]; y[13] = b64[14]; y[14] = b64[13]; y[15] = b64[12]; ++ y[16] = b64[19]; y[17] = b64[18]; y[18] = b64[17]; y[19] = b64[16]; ++ y[20] = b64[23]; y[21] = b64[22]; y[22] = b64[21]; y[23] = b64[20]; ++ y[24] = b64[27]; y[25] = b64[26]; y[26] = b64[25]; y[27] = b64[24]; ++ y[28] = b64[31]; y[29] = b64[30]; y[30] = b64[29]; y[31] = b64[28]; ++ y[32] = b64[35]; y[33] = b64[34]; y[34] = b64[33]; y[35] = b64[32]; ++ y[36] = b64[39]; y[37] = b64[38]; y[38] = b64[37]; y[39] = b64[36]; ++ y[40] = b64[43]; y[41] = b64[42]; y[42] = b64[41]; y[43] = b64[40]; ++ y[44] = b64[47]; y[45] = b64[46]; y[46] = b64[45]; y[47] = b64[44]; ++ y[48] = b64[51]; y[49] = b64[50]; y[50] = b64[49]; y[51] = b64[48]; ++ y[52] = b64[55]; y[53] = b64[54]; y[54] = b64[53]; y[55] = b64[52]; ++ y[56] = b64[59]; y[57] = b64[58]; y[58] = b64[57]; y[59] = b64[56]; ++ y[60] = b64[63]; y[61] = b64[62]; y[62] = b64[61]; y[63] = b64[60]; ++#endif ++ ++ ROUND1(A, B, C, D, 0, Sa, 1); ROUND1(D, A, B, C, 1, Sb, 2); ++ ROUND1(C, D, A, B, 2, Sc, 3); ROUND1(B, C, D, A, 3, Sd, 4); ++ ROUND1(A, B, C, D, 4, Sa, 5); ROUND1(D, A, B, C, 5, Sb, 6); ++ ROUND1(C, D, A, B, 6, Sc, 7); ROUND1(B, C, D, A, 7, Sd, 8); ++ ROUND1(A, B, C, D, 8, Sa, 9); ROUND1(D, A, B, C, 9, Sb, 10); ++ ROUND1(C, D, A, B, 10, Sc, 11); ROUND1(B, C, D, A, 11, Sd, 12); ++ ROUND1(A, B, C, D, 12, Sa, 13); ROUND1(D, A, B, C, 13, Sb, 14); ++ ROUND1(C, D, A, B, 14, Sc, 15); ROUND1(B, C, D, A, 15, Sd, 16); ++ ++ ROUND2(A, B, C, D, 1, Se, 17); ROUND2(D, A, B, C, 6, Sf, 18); ++ ROUND2(C, D, A, B, 11, Sg, 19); ROUND2(B, C, D, A, 0, Sh, 20); ++ ROUND2(A, B, C, D, 5, Se, 21); ROUND2(D, A, B, C, 10, Sf, 22); ++ ROUND2(C, D, A, B, 15, Sg, 23); ROUND2(B, C, D, A, 4, Sh, 24); ++ ROUND2(A, B, C, D, 9, Se, 25); ROUND2(D, A, B, C, 14, Sf, 26); ++ ROUND2(C, D, A, B, 3, Sg, 27); ROUND2(B, C, D, A, 8, Sh, 28); ++ ROUND2(A, B, C, D, 13, Se, 29); ROUND2(D, A, B, C, 2, Sf, 30); ++ ROUND2(C, D, A, B, 7, Sg, 31); ROUND2(B, C, D, A, 12, Sh, 32); ++ ++ ROUND3(A, B, C, D, 5, Si, 33); ROUND3(D, A, B, C, 8, Sj, 34); ++ ROUND3(C, D, A, B, 11, Sk, 35); ROUND3(B, C, D, A, 14, Sl, 36); ++ ROUND3(A, B, C, D, 1, Si, 37); ROUND3(D, A, B, C, 4, Sj, 38); ++ ROUND3(C, D, A, B, 7, Sk, 39); ROUND3(B, C, D, A, 10, Sl, 40); ++ ROUND3(A, B, C, D, 13, Si, 41); ROUND3(D, A, B, C, 0, Sj, 42); ++ ROUND3(C, D, A, B, 3, Sk, 43); ROUND3(B, C, D, A, 6, Sl, 44); ++ ROUND3(A, B, C, D, 9, Si, 45); ROUND3(D, A, B, C, 12, Sj, 46); ++ ROUND3(C, D, A, B, 15, Sk, 47); ROUND3(B, C, D, A, 2, Sl, 48); ++ ++ ROUND4(A, B, C, D, 0, Sm, 49); ROUND4(D, A, B, C, 7, Sn, 50); ++ ROUND4(C, D, A, B, 14, So, 51); ROUND4(B, C, D, A, 5, Sp, 52); ++ ROUND4(A, B, C, D, 12, Sm, 53); ROUND4(D, A, B, C, 3, Sn, 54); ++ ROUND4(C, D, A, B, 10, So, 55); ROUND4(B, C, D, A, 1, Sp, 56); ++ ROUND4(A, B, C, D, 8, Sm, 57); ROUND4(D, A, B, C, 15, Sn, 58); ++ ROUND4(C, D, A, B, 6, So, 59); ROUND4(B, C, D, A, 13, Sp, 60); ++ ROUND4(A, B, C, D, 4, Sm, 61); ROUND4(D, A, B, C, 11, Sn, 62); ++ ROUND4(C, D, A, B, 2, So, 63); ROUND4(B, C, D, A, 9, Sp, 64); ++ ++ ctxt->md5_sta += A; ++ ctxt->md5_stb += B; ++ ctxt->md5_stc += C; ++ ctxt->md5_std += D; ++} +diff -Nur linux-3.0.4.orig/crypto/ocf/safe/md5.h linux-3.0.4/crypto/ocf/safe/md5.h +--- linux-3.0.4.orig/crypto/ocf/safe/md5.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/safe/md5.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,76 @@ ++/* $FreeBSD: src/sys/crypto/md5.h,v 1.4 2002/03/20 05:13:50 alfred Exp $ */ ++/* $KAME: md5.h,v 1.4 2000/03/27 04:36:22 sumikawa Exp $ */ ++ ++/* ++ * Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. Neither the name of the project nor the names of its contributors ++ * may be used to endorse or promote products derived from this software ++ * without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND ++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE ++ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ++ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ++ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF ++ * SUCH DAMAGE. ++ */ ++ ++#ifndef _NETINET6_MD5_H_ ++#define _NETINET6_MD5_H_ ++ ++#define MD5_BUFLEN 64 ++ ++typedef struct { ++ union { ++ u_int32_t md5_state32[4]; ++ u_int8_t md5_state8[16]; ++ } md5_st; ++ ++#define md5_sta md5_st.md5_state32[0] ++#define md5_stb md5_st.md5_state32[1] ++#define md5_stc md5_st.md5_state32[2] ++#define md5_std md5_st.md5_state32[3] ++#define md5_st8 md5_st.md5_state8 ++ ++ union { ++ u_int64_t md5_count64; ++ u_int8_t md5_count8[8]; ++ } md5_count; ++#define md5_n md5_count.md5_count64 ++#define md5_n8 md5_count.md5_count8 ++ ++ u_int md5_i; ++ u_int8_t md5_buf[MD5_BUFLEN]; ++} md5_ctxt; ++ ++extern void md5_init(md5_ctxt *); ++extern void md5_loop(md5_ctxt *, u_int8_t *, u_int); ++extern void md5_pad(md5_ctxt *); ++extern void md5_result(u_int8_t *, md5_ctxt *); ++ ++/* compatibility */ ++#define MD5_CTX md5_ctxt ++#define MD5Init(x) md5_init((x)) ++#define MD5Update(x, y, z) md5_loop((x), (y), (z)) ++#define MD5Final(x, y) \ ++do { \ ++ md5_pad((y)); \ ++ md5_result((x), (y)); \ ++} while (0) ++ ++#endif /* ! _NETINET6_MD5_H_*/ +diff -Nur linux-3.0.4.orig/crypto/ocf/safe/safe.c linux-3.0.4/crypto/ocf/safe/safe.c +--- linux-3.0.4.orig/crypto/ocf/safe/safe.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/safe/safe.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,2230 @@ ++/*- ++ * Linux port done by David McCullough ++ * Copyright (C) 2004-2010 David McCullough ++ * The license and original author are listed below. ++ * ++ * Copyright (c) 2003 Sam Leffler, Errno Consulting ++ * Copyright (c) 2003 Global Technology Associates, Inc. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE ++ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ++ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ++ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF ++ * SUCH DAMAGE. ++ * ++__FBSDID("$FreeBSD: src/sys/dev/safe/safe.c,v 1.18 2007/03/21 03:42:50 sam Exp $"); ++ */ ++ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* ++ * SafeNet SafeXcel-1141 hardware crypto accelerator ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#if 1 ++#define DPRINTF(a) do { \ ++ if (debug) { \ ++ printk("%s: ", sc ? \ ++ device_get_nameunit(sc->sc_dev) : "safe"); \ ++ printk a; \ ++ } \ ++ } while (0) ++#else ++#define DPRINTF(a) ++#endif ++ ++/* ++ * until we find a cleaner way, include the BSD md5/sha1 code ++ * here ++ */ ++#define HMAC_HACK 1 ++#ifdef HMAC_HACK ++#include ++#include ++#include ++#include ++#include ++#endif /* HMAC_HACK */ ++ ++/* add proc entry for this */ ++struct safe_stats safestats; ++ ++#define debug safe_debug ++int safe_debug = 0; ++module_param(safe_debug, int, 0644); ++MODULE_PARM_DESC(safe_debug, "Enable debug"); ++ ++static void safe_callback(struct safe_softc *, struct safe_ringentry *); ++static void safe_feed(struct safe_softc *, struct safe_ringentry *); ++#if defined(CONFIG_OCF_RANDOMHARVEST) && !defined(SAFE_NO_RNG) ++static void safe_rng_init(struct safe_softc *); ++int safe_rngbufsize = 8; /* 32 bytes each read */ ++module_param(safe_rngbufsize, int, 0644); ++MODULE_PARM_DESC(safe_rngbufsize, "RNG polling buffer size (32-bit words)"); ++int safe_rngmaxalarm = 8; /* max alarms before reset */ ++module_param(safe_rngmaxalarm, int, 0644); ++MODULE_PARM_DESC(safe_rngmaxalarm, "RNG max alarms before reset"); ++#endif /* SAFE_NO_RNG */ ++ ++static void safe_totalreset(struct safe_softc *sc); ++static int safe_dmamap_aligned(struct safe_softc *sc, const struct safe_operand *op); ++static int safe_dmamap_uniform(struct safe_softc *sc, const struct safe_operand *op); ++static int safe_free_entry(struct safe_softc *sc, struct safe_ringentry *re); ++static int safe_kprocess(device_t dev, struct cryptkop *krp, int hint); ++static int safe_kstart(struct safe_softc *sc); ++static int safe_ksigbits(struct safe_softc *sc, struct crparam *cr); ++static void safe_kfeed(struct safe_softc *sc); ++static void safe_kpoll(unsigned long arg); ++static void safe_kload_reg(struct safe_softc *sc, u_int32_t off, ++ u_int32_t len, struct crparam *n); ++ ++static int safe_newsession(device_t, u_int32_t *, struct cryptoini *); ++static int safe_freesession(device_t, u_int64_t); ++static int safe_process(device_t, struct cryptop *, int); ++ ++static device_method_t safe_methods = { ++ /* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, safe_newsession), ++ DEVMETHOD(cryptodev_freesession,safe_freesession), ++ DEVMETHOD(cryptodev_process, safe_process), ++ DEVMETHOD(cryptodev_kprocess, safe_kprocess), ++}; ++ ++#define READ_REG(sc,r) readl((sc)->sc_base_addr + (r)) ++#define WRITE_REG(sc,r,val) writel((val), (sc)->sc_base_addr + (r)) ++ ++#define SAFE_MAX_CHIPS 8 ++static struct safe_softc *safe_chip_idx[SAFE_MAX_CHIPS]; ++ ++/* ++ * split our buffers up into safe DMAable byte fragments to avoid lockup ++ * bug in 1141 HW on rev 1.0. ++ */ ++ ++static int ++pci_map_linear( ++ struct safe_softc *sc, ++ struct safe_operand *buf, ++ void *addr, ++ int len) ++{ ++ dma_addr_t tmp; ++ int chunk, tlen = len; ++ ++ tmp = pci_map_single(sc->sc_pcidev, addr, len, PCI_DMA_BIDIRECTIONAL); ++ ++ buf->mapsize += len; ++ while (len > 0) { ++ chunk = (len > sc->sc_max_dsize) ? sc->sc_max_dsize : len; ++ buf->segs[buf->nsegs].ds_addr = tmp; ++ buf->segs[buf->nsegs].ds_len = chunk; ++ buf->segs[buf->nsegs].ds_tlen = tlen; ++ buf->nsegs++; ++ tmp += chunk; ++ len -= chunk; ++ tlen = 0; ++ } ++ return 0; ++} ++ ++/* ++ * map in a given uio buffer (great on some arches :-) ++ */ ++ ++static int ++pci_map_uio(struct safe_softc *sc, struct safe_operand *buf, struct uio *uio) ++{ ++ struct iovec *iov = uio->uio_iov; ++ int n; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ buf->mapsize = 0; ++ buf->nsegs = 0; ++ ++ for (n = 0; n < uio->uio_iovcnt; n++) { ++ pci_map_linear(sc, buf, iov->iov_base, iov->iov_len); ++ iov++; ++ } ++ ++ /* identify this buffer by the first segment */ ++ buf->map = (void *) buf->segs[0].ds_addr; ++ return(0); ++} ++ ++/* ++ * map in a given sk_buff ++ */ ++ ++static int ++pci_map_skb(struct safe_softc *sc,struct safe_operand *buf,struct sk_buff *skb) ++{ ++ int i; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ buf->mapsize = 0; ++ buf->nsegs = 0; ++ ++ pci_map_linear(sc, buf, skb->data, skb_headlen(skb)); ++ ++ for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { ++ pci_map_linear(sc, buf, ++ page_address(skb_shinfo(skb)->frags[i].page) + ++ skb_shinfo(skb)->frags[i].page_offset, ++ skb_shinfo(skb)->frags[i].size); ++ } ++ ++ /* identify this buffer by the first segment */ ++ buf->map = (void *) buf->segs[0].ds_addr; ++ return(0); ++} ++ ++ ++#if 0 /* not needed at this time */ ++static void ++pci_sync_operand(struct safe_softc *sc, struct safe_operand *buf) ++{ ++ int i; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ for (i = 0; i < buf->nsegs; i++) ++ pci_dma_sync_single_for_cpu(sc->sc_pcidev, buf->segs[i].ds_addr, ++ buf->segs[i].ds_len, PCI_DMA_BIDIRECTIONAL); ++} ++#endif ++ ++static void ++pci_unmap_operand(struct safe_softc *sc, struct safe_operand *buf) ++{ ++ int i; ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ for (i = 0; i < buf->nsegs; i++) { ++ if (buf->segs[i].ds_tlen) { ++ DPRINTF(("%s - unmap %d 0x%x %d\n", __FUNCTION__, i, buf->segs[i].ds_addr, buf->segs[i].ds_tlen)); ++ pci_unmap_single(sc->sc_pcidev, buf->segs[i].ds_addr, ++ buf->segs[i].ds_tlen, PCI_DMA_BIDIRECTIONAL); ++ DPRINTF(("%s - unmap %d 0x%x %d done\n", __FUNCTION__, i, buf->segs[i].ds_addr, buf->segs[i].ds_tlen)); ++ } ++ buf->segs[i].ds_addr = 0; ++ buf->segs[i].ds_len = 0; ++ buf->segs[i].ds_tlen = 0; ++ } ++ buf->nsegs = 0; ++ buf->mapsize = 0; ++ buf->map = 0; ++} ++ ++ ++/* ++ * SafeXcel Interrupt routine ++ */ ++static irqreturn_t ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) ++safe_intr(int irq, void *arg) ++#else ++safe_intr(int irq, void *arg, struct pt_regs *regs) ++#endif ++{ ++ struct safe_softc *sc = arg; ++ int stat; ++ unsigned long flags; ++ ++ stat = READ_REG(sc, SAFE_HM_STAT); ++ ++ DPRINTF(("%s(stat=0x%x)\n", __FUNCTION__, stat)); ++ ++ if (stat == 0) /* shared irq, not for us */ ++ return IRQ_NONE; ++ ++ WRITE_REG(sc, SAFE_HI_CLR, stat); /* IACK */ ++ ++ if ((stat & SAFE_INT_PE_DDONE)) { ++ /* ++ * Descriptor(s) done; scan the ring and ++ * process completed operations. ++ */ ++ spin_lock_irqsave(&sc->sc_ringmtx, flags); ++ while (sc->sc_back != sc->sc_front) { ++ struct safe_ringentry *re = sc->sc_back; ++ ++#ifdef SAFE_DEBUG ++ if (debug) { ++ safe_dump_ringstate(sc, __func__); ++ safe_dump_request(sc, __func__, re); ++ } ++#endif ++ /* ++ * safe_process marks ring entries that were allocated ++ * but not used with a csr of zero. This insures the ++ * ring front pointer never needs to be set backwards ++ * in the event that an entry is allocated but not used ++ * because of a setup error. ++ */ ++ DPRINTF(("%s re->re_desc.d_csr=0x%x\n", __FUNCTION__, re->re_desc.d_csr)); ++ if (re->re_desc.d_csr != 0) { ++ if (!SAFE_PE_CSR_IS_DONE(re->re_desc.d_csr)) { ++ DPRINTF(("%s !CSR_IS_DONE\n", __FUNCTION__)); ++ break; ++ } ++ if (!SAFE_PE_LEN_IS_DONE(re->re_desc.d_len)) { ++ DPRINTF(("%s !LEN_IS_DONE\n", __FUNCTION__)); ++ break; ++ } ++ sc->sc_nqchip--; ++ safe_callback(sc, re); ++ } ++ if (++(sc->sc_back) == sc->sc_ringtop) ++ sc->sc_back = sc->sc_ring; ++ } ++ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); ++ } ++ ++ /* ++ * Check to see if we got any DMA Error ++ */ ++ if (stat & SAFE_INT_PE_ERROR) { ++ printk("%s: dmaerr dmastat %08x\n", device_get_nameunit(sc->sc_dev), ++ (int)READ_REG(sc, SAFE_PE_DMASTAT)); ++ safestats.st_dmaerr++; ++ safe_totalreset(sc); ++#if 0 ++ safe_feed(sc); ++#endif ++ } ++ ++ if (sc->sc_needwakeup) { /* XXX check high watermark */ ++ int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); ++ DPRINTF(("%s: wakeup crypto %x\n", __func__, ++ sc->sc_needwakeup)); ++ sc->sc_needwakeup &= ~wakeup; ++ crypto_unblock(sc->sc_cid, wakeup); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++/* ++ * safe_feed() - post a request to chip ++ */ ++static void ++safe_feed(struct safe_softc *sc, struct safe_ringentry *re) ++{ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++#ifdef SAFE_DEBUG ++ if (debug) { ++ safe_dump_ringstate(sc, __func__); ++ safe_dump_request(sc, __func__, re); ++ } ++#endif ++ sc->sc_nqchip++; ++ if (sc->sc_nqchip > safestats.st_maxqchip) ++ safestats.st_maxqchip = sc->sc_nqchip; ++ /* poke h/w to check descriptor ring, any value can be written */ ++ WRITE_REG(sc, SAFE_HI_RD_DESCR, 0); ++} ++ ++#define N(a) (sizeof(a) / sizeof (a[0])) ++static void ++safe_setup_enckey(struct safe_session *ses, caddr_t key) ++{ ++ int i; ++ ++ bcopy(key, ses->ses_key, ses->ses_klen / 8); ++ ++ /* PE is little-endian, insure proper byte order */ ++ for (i = 0; i < N(ses->ses_key); i++) ++ ses->ses_key[i] = htole32(ses->ses_key[i]); ++} ++ ++static void ++safe_setup_mackey(struct safe_session *ses, int algo, caddr_t key, int klen) ++{ ++#ifdef HMAC_HACK ++ MD5_CTX md5ctx; ++ SHA1_CTX sha1ctx; ++ int i; ++ ++ ++ for (i = 0; i < klen; i++) ++ key[i] ^= HMAC_IPAD_VAL; ++ ++ if (algo == CRYPTO_MD5_HMAC) { ++ MD5Init(&md5ctx); ++ MD5Update(&md5ctx, key, klen); ++ MD5Update(&md5ctx, hmac_ipad_buffer, MD5_HMAC_BLOCK_LEN - klen); ++ bcopy(md5ctx.md5_st8, ses->ses_hminner, sizeof(md5ctx.md5_st8)); ++ } else { ++ SHA1Init(&sha1ctx); ++ SHA1Update(&sha1ctx, key, klen); ++ SHA1Update(&sha1ctx, hmac_ipad_buffer, ++ SHA1_HMAC_BLOCK_LEN - klen); ++ bcopy(sha1ctx.h.b32, ses->ses_hminner, sizeof(sha1ctx.h.b32)); ++ } ++ ++ for (i = 0; i < klen; i++) ++ key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); ++ ++ if (algo == CRYPTO_MD5_HMAC) { ++ MD5Init(&md5ctx); ++ MD5Update(&md5ctx, key, klen); ++ MD5Update(&md5ctx, hmac_opad_buffer, MD5_HMAC_BLOCK_LEN - klen); ++ bcopy(md5ctx.md5_st8, ses->ses_hmouter, sizeof(md5ctx.md5_st8)); ++ } else { ++ SHA1Init(&sha1ctx); ++ SHA1Update(&sha1ctx, key, klen); ++ SHA1Update(&sha1ctx, hmac_opad_buffer, ++ SHA1_HMAC_BLOCK_LEN - klen); ++ bcopy(sha1ctx.h.b32, ses->ses_hmouter, sizeof(sha1ctx.h.b32)); ++ } ++ ++ for (i = 0; i < klen; i++) ++ key[i] ^= HMAC_OPAD_VAL; ++ ++#if 0 ++ /* ++ * this code prevents SHA working on a BE host, ++ * so it is obviously wrong. I think the byte ++ * swap setup we do with the chip fixes this for us ++ */ ++ ++ /* PE is little-endian, insure proper byte order */ ++ for (i = 0; i < N(ses->ses_hminner); i++) { ++ ses->ses_hminner[i] = htole32(ses->ses_hminner[i]); ++ ses->ses_hmouter[i] = htole32(ses->ses_hmouter[i]); ++ } ++#endif ++#else /* HMAC_HACK */ ++ printk("safe: md5/sha not implemented\n"); ++#endif /* HMAC_HACK */ ++} ++#undef N ++ ++/* ++ * Allocate a new 'session' and return an encoded session id. 'sidp' ++ * contains our registration id, and should contain an encoded session ++ * id on successful allocation. ++ */ ++static int ++safe_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) ++{ ++ struct safe_softc *sc = device_get_softc(dev); ++ struct cryptoini *c, *encini = NULL, *macini = NULL; ++ struct safe_session *ses = NULL; ++ int sesn; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ if (sidp == NULL || cri == NULL || sc == NULL) ++ return (EINVAL); ++ ++ for (c = cri; c != NULL; c = c->cri_next) { ++ if (c->cri_alg == CRYPTO_MD5_HMAC || ++ c->cri_alg == CRYPTO_SHA1_HMAC || ++ c->cri_alg == CRYPTO_NULL_HMAC) { ++ if (macini) ++ return (EINVAL); ++ macini = c; ++ } else if (c->cri_alg == CRYPTO_DES_CBC || ++ c->cri_alg == CRYPTO_3DES_CBC || ++ c->cri_alg == CRYPTO_AES_CBC || ++ c->cri_alg == CRYPTO_NULL_CBC) { ++ if (encini) ++ return (EINVAL); ++ encini = c; ++ } else ++ return (EINVAL); ++ } ++ if (encini == NULL && macini == NULL) ++ return (EINVAL); ++ if (encini) { /* validate key length */ ++ switch (encini->cri_alg) { ++ case CRYPTO_DES_CBC: ++ if (encini->cri_klen != 64) ++ return (EINVAL); ++ break; ++ case CRYPTO_3DES_CBC: ++ if (encini->cri_klen != 192) ++ return (EINVAL); ++ break; ++ case CRYPTO_AES_CBC: ++ if (encini->cri_klen != 128 && ++ encini->cri_klen != 192 && ++ encini->cri_klen != 256) ++ return (EINVAL); ++ break; ++ } ++ } ++ ++ if (sc->sc_sessions == NULL) { ++ ses = sc->sc_sessions = (struct safe_session *) ++ kmalloc(sizeof(struct safe_session), SLAB_ATOMIC); ++ if (ses == NULL) ++ return (ENOMEM); ++ memset(ses, 0, sizeof(struct safe_session)); ++ sesn = 0; ++ sc->sc_nsessions = 1; ++ } else { ++ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { ++ if (sc->sc_sessions[sesn].ses_used == 0) { ++ ses = &sc->sc_sessions[sesn]; ++ break; ++ } ++ } ++ ++ if (ses == NULL) { ++ sesn = sc->sc_nsessions; ++ ses = (struct safe_session *) ++ kmalloc((sesn + 1) * sizeof(struct safe_session), SLAB_ATOMIC); ++ if (ses == NULL) ++ return (ENOMEM); ++ memset(ses, 0, (sesn + 1) * sizeof(struct safe_session)); ++ bcopy(sc->sc_sessions, ses, sesn * ++ sizeof(struct safe_session)); ++ bzero(sc->sc_sessions, sesn * ++ sizeof(struct safe_session)); ++ kfree(sc->sc_sessions); ++ sc->sc_sessions = ses; ++ ses = &sc->sc_sessions[sesn]; ++ sc->sc_nsessions++; ++ } ++ } ++ ++ bzero(ses, sizeof(struct safe_session)); ++ ses->ses_used = 1; ++ ++ if (encini) { ++ ses->ses_klen = encini->cri_klen; ++ if (encini->cri_key != NULL) ++ safe_setup_enckey(ses, encini->cri_key); ++ } ++ ++ if (macini) { ++ ses->ses_mlen = macini->cri_mlen; ++ if (ses->ses_mlen == 0) { ++ if (macini->cri_alg == CRYPTO_MD5_HMAC) ++ ses->ses_mlen = MD5_HASH_LEN; ++ else ++ ses->ses_mlen = SHA1_HASH_LEN; ++ } ++ ++ if (macini->cri_key != NULL) { ++ safe_setup_mackey(ses, macini->cri_alg, macini->cri_key, ++ macini->cri_klen / 8); ++ } ++ } ++ ++ *sidp = SAFE_SID(device_get_unit(sc->sc_dev), sesn); ++ return (0); ++} ++ ++/* ++ * Deallocate a session. ++ */ ++static int ++safe_freesession(device_t dev, u_int64_t tid) ++{ ++ struct safe_softc *sc = device_get_softc(dev); ++ int session, ret; ++ u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ if (sc == NULL) ++ return (EINVAL); ++ ++ session = SAFE_SESSION(sid); ++ if (session < sc->sc_nsessions) { ++ bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session])); ++ ret = 0; ++ } else ++ ret = EINVAL; ++ return (ret); ++} ++ ++ ++static int ++safe_process(device_t dev, struct cryptop *crp, int hint) ++{ ++ struct safe_softc *sc = device_get_softc(dev); ++ int err = 0, i, nicealign, uniform; ++ struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; ++ int bypass, oplen, ivsize; ++ caddr_t iv; ++ int16_t coffset; ++ struct safe_session *ses; ++ struct safe_ringentry *re; ++ struct safe_sarec *sa; ++ struct safe_pdesc *pd; ++ u_int32_t cmd0, cmd1, staterec, rand_iv[4]; ++ unsigned long flags; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { ++ safestats.st_invalid++; ++ return (EINVAL); ++ } ++ if (SAFE_SESSION(crp->crp_sid) >= sc->sc_nsessions) { ++ safestats.st_badsession++; ++ return (EINVAL); ++ } ++ ++ spin_lock_irqsave(&sc->sc_ringmtx, flags); ++ if (sc->sc_front == sc->sc_back && sc->sc_nqchip != 0) { ++ safestats.st_ringfull++; ++ sc->sc_needwakeup |= CRYPTO_SYMQ; ++ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); ++ return (ERESTART); ++ } ++ re = sc->sc_front; ++ ++ staterec = re->re_sa.sa_staterec; /* save */ ++ /* NB: zero everything but the PE descriptor */ ++ bzero(&re->re_sa, sizeof(struct safe_ringentry) - sizeof(re->re_desc)); ++ re->re_sa.sa_staterec = staterec; /* restore */ ++ ++ re->re_crp = crp; ++ re->re_sesn = SAFE_SESSION(crp->crp_sid); ++ ++ re->re_src.nsegs = 0; ++ re->re_dst.nsegs = 0; ++ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ re->re_src_skb = (struct sk_buff *)crp->crp_buf; ++ re->re_dst_skb = (struct sk_buff *)crp->crp_buf; ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ re->re_src_io = (struct uio *)crp->crp_buf; ++ re->re_dst_io = (struct uio *)crp->crp_buf; ++ } else { ++ safestats.st_badflags++; ++ err = EINVAL; ++ goto errout; /* XXX we don't handle contiguous blocks! */ ++ } ++ ++ sa = &re->re_sa; ++ ses = &sc->sc_sessions[re->re_sesn]; ++ ++ crd1 = crp->crp_desc; ++ if (crd1 == NULL) { ++ safestats.st_nodesc++; ++ err = EINVAL; ++ goto errout; ++ } ++ crd2 = crd1->crd_next; ++ ++ cmd0 = SAFE_SA_CMD0_BASIC; /* basic group operation */ ++ cmd1 = 0; ++ if (crd2 == NULL) { ++ if (crd1->crd_alg == CRYPTO_MD5_HMAC || ++ crd1->crd_alg == CRYPTO_SHA1_HMAC || ++ crd1->crd_alg == CRYPTO_NULL_HMAC) { ++ maccrd = crd1; ++ enccrd = NULL; ++ cmd0 |= SAFE_SA_CMD0_OP_HASH; ++ } else if (crd1->crd_alg == CRYPTO_DES_CBC || ++ crd1->crd_alg == CRYPTO_3DES_CBC || ++ crd1->crd_alg == CRYPTO_AES_CBC || ++ crd1->crd_alg == CRYPTO_NULL_CBC) { ++ maccrd = NULL; ++ enccrd = crd1; ++ cmd0 |= SAFE_SA_CMD0_OP_CRYPT; ++ } else { ++ safestats.st_badalg++; ++ err = EINVAL; ++ goto errout; ++ } ++ } else { ++ if ((crd1->crd_alg == CRYPTO_MD5_HMAC || ++ crd1->crd_alg == CRYPTO_SHA1_HMAC || ++ crd1->crd_alg == CRYPTO_NULL_HMAC) && ++ (crd2->crd_alg == CRYPTO_DES_CBC || ++ crd2->crd_alg == CRYPTO_3DES_CBC || ++ crd2->crd_alg == CRYPTO_AES_CBC || ++ crd2->crd_alg == CRYPTO_NULL_CBC) && ++ ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { ++ maccrd = crd1; ++ enccrd = crd2; ++ } else if ((crd1->crd_alg == CRYPTO_DES_CBC || ++ crd1->crd_alg == CRYPTO_3DES_CBC || ++ crd1->crd_alg == CRYPTO_AES_CBC || ++ crd1->crd_alg == CRYPTO_NULL_CBC) && ++ (crd2->crd_alg == CRYPTO_MD5_HMAC || ++ crd2->crd_alg == CRYPTO_SHA1_HMAC || ++ crd2->crd_alg == CRYPTO_NULL_HMAC) && ++ (crd1->crd_flags & CRD_F_ENCRYPT)) { ++ enccrd = crd1; ++ maccrd = crd2; ++ } else { ++ safestats.st_badalg++; ++ err = EINVAL; ++ goto errout; ++ } ++ cmd0 |= SAFE_SA_CMD0_OP_BOTH; ++ } ++ ++ if (enccrd) { ++ if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) ++ safe_setup_enckey(ses, enccrd->crd_key); ++ ++ if (enccrd->crd_alg == CRYPTO_DES_CBC) { ++ cmd0 |= SAFE_SA_CMD0_DES; ++ cmd1 |= SAFE_SA_CMD1_CBC; ++ ivsize = 2*sizeof(u_int32_t); ++ } else if (enccrd->crd_alg == CRYPTO_3DES_CBC) { ++ cmd0 |= SAFE_SA_CMD0_3DES; ++ cmd1 |= SAFE_SA_CMD1_CBC; ++ ivsize = 2*sizeof(u_int32_t); ++ } else if (enccrd->crd_alg == CRYPTO_AES_CBC) { ++ cmd0 |= SAFE_SA_CMD0_AES; ++ cmd1 |= SAFE_SA_CMD1_CBC; ++ if (ses->ses_klen == 128) ++ cmd1 |= SAFE_SA_CMD1_AES128; ++ else if (ses->ses_klen == 192) ++ cmd1 |= SAFE_SA_CMD1_AES192; ++ else ++ cmd1 |= SAFE_SA_CMD1_AES256; ++ ivsize = 4*sizeof(u_int32_t); ++ } else { ++ cmd0 |= SAFE_SA_CMD0_CRYPT_NULL; ++ ivsize = 0; ++ } ++ ++ /* ++ * Setup encrypt/decrypt state. When using basic ops ++ * we can't use an inline IV because hash/crypt offset ++ * must be from the end of the IV to the start of the ++ * crypt data and this leaves out the preceding header ++ * from the hash calculation. Instead we place the IV ++ * in the state record and set the hash/crypt offset to ++ * copy both the header+IV. ++ */ ++ if (enccrd->crd_flags & CRD_F_ENCRYPT) { ++ cmd0 |= SAFE_SA_CMD0_OUTBOUND; ++ ++ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) ++ iv = enccrd->crd_iv; ++ else ++ read_random((iv = (caddr_t) &rand_iv[0]), sizeof(rand_iv)); ++ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ enccrd->crd_inject, ivsize, iv); ++ } ++ bcopy(iv, re->re_sastate.sa_saved_iv, ivsize); ++ /* make iv LE */ ++ for (i = 0; i < ivsize/sizeof(re->re_sastate.sa_saved_iv[0]); i++) ++ re->re_sastate.sa_saved_iv[i] = ++ cpu_to_le32(re->re_sastate.sa_saved_iv[i]); ++ cmd0 |= SAFE_SA_CMD0_IVLD_STATE | SAFE_SA_CMD0_SAVEIV; ++ re->re_flags |= SAFE_QFLAGS_COPYOUTIV; ++ } else { ++ cmd0 |= SAFE_SA_CMD0_INBOUND; ++ ++ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) { ++ bcopy(enccrd->crd_iv, ++ re->re_sastate.sa_saved_iv, ivsize); ++ } else { ++ crypto_copydata(crp->crp_flags, crp->crp_buf, ++ enccrd->crd_inject, ivsize, ++ (caddr_t)re->re_sastate.sa_saved_iv); ++ } ++ /* make iv LE */ ++ for (i = 0; i < ivsize/sizeof(re->re_sastate.sa_saved_iv[0]); i++) ++ re->re_sastate.sa_saved_iv[i] = ++ cpu_to_le32(re->re_sastate.sa_saved_iv[i]); ++ cmd0 |= SAFE_SA_CMD0_IVLD_STATE; ++ } ++ /* ++ * For basic encryption use the zero pad algorithm. ++ * This pads results to an 8-byte boundary and ++ * suppresses padding verification for inbound (i.e. ++ * decrypt) operations. ++ * ++ * NB: Not sure if the 8-byte pad boundary is a problem. ++ */ ++ cmd0 |= SAFE_SA_CMD0_PAD_ZERO; ++ ++ /* XXX assert key bufs have the same size */ ++ bcopy(ses->ses_key, sa->sa_key, sizeof(sa->sa_key)); ++ } ++ ++ if (maccrd) { ++ if (maccrd->crd_flags & CRD_F_KEY_EXPLICIT) { ++ safe_setup_mackey(ses, maccrd->crd_alg, ++ maccrd->crd_key, maccrd->crd_klen / 8); ++ } ++ ++ if (maccrd->crd_alg == CRYPTO_MD5_HMAC) { ++ cmd0 |= SAFE_SA_CMD0_MD5; ++ cmd1 |= SAFE_SA_CMD1_HMAC; /* NB: enable HMAC */ ++ } else if (maccrd->crd_alg == CRYPTO_SHA1_HMAC) { ++ cmd0 |= SAFE_SA_CMD0_SHA1; ++ cmd1 |= SAFE_SA_CMD1_HMAC; /* NB: enable HMAC */ ++ } else { ++ cmd0 |= SAFE_SA_CMD0_HASH_NULL; ++ } ++ /* ++ * Digest data is loaded from the SA and the hash ++ * result is saved to the state block where we ++ * retrieve it for return to the caller. ++ */ ++ /* XXX assert digest bufs have the same size */ ++ bcopy(ses->ses_hminner, sa->sa_indigest, ++ sizeof(sa->sa_indigest)); ++ bcopy(ses->ses_hmouter, sa->sa_outdigest, ++ sizeof(sa->sa_outdigest)); ++ ++ cmd0 |= SAFE_SA_CMD0_HSLD_SA | SAFE_SA_CMD0_SAVEHASH; ++ re->re_flags |= SAFE_QFLAGS_COPYOUTICV; ++ } ++ ++ if (enccrd && maccrd) { ++ /* ++ * The offset from hash data to the start of ++ * crypt data is the difference in the skips. ++ */ ++ bypass = maccrd->crd_skip; ++ coffset = enccrd->crd_skip - maccrd->crd_skip; ++ if (coffset < 0) { ++ DPRINTF(("%s: hash does not precede crypt; " ++ "mac skip %u enc skip %u\n", ++ __func__, maccrd->crd_skip, enccrd->crd_skip)); ++ safestats.st_skipmismatch++; ++ err = EINVAL; ++ goto errout; ++ } ++ oplen = enccrd->crd_skip + enccrd->crd_len; ++ if (maccrd->crd_skip + maccrd->crd_len != oplen) { ++ DPRINTF(("%s: hash amount %u != crypt amount %u\n", ++ __func__, maccrd->crd_skip + maccrd->crd_len, ++ oplen)); ++ safestats.st_lenmismatch++; ++ err = EINVAL; ++ goto errout; ++ } ++#ifdef SAFE_DEBUG ++ if (debug) { ++ printf("mac: skip %d, len %d, inject %d\n", ++ maccrd->crd_skip, maccrd->crd_len, ++ maccrd->crd_inject); ++ printf("enc: skip %d, len %d, inject %d\n", ++ enccrd->crd_skip, enccrd->crd_len, ++ enccrd->crd_inject); ++ printf("bypass %d coffset %d oplen %d\n", ++ bypass, coffset, oplen); ++ } ++#endif ++ if (coffset & 3) { /* offset must be 32-bit aligned */ ++ DPRINTF(("%s: coffset %u misaligned\n", ++ __func__, coffset)); ++ safestats.st_coffmisaligned++; ++ err = EINVAL; ++ goto errout; ++ } ++ coffset >>= 2; ++ if (coffset > 255) { /* offset must be <256 dwords */ ++ DPRINTF(("%s: coffset %u too big\n", ++ __func__, coffset)); ++ safestats.st_cofftoobig++; ++ err = EINVAL; ++ goto errout; ++ } ++ /* ++ * Tell the hardware to copy the header to the output. ++ * The header is defined as the data from the end of ++ * the bypass to the start of data to be encrypted. ++ * Typically this is the inline IV. Note that you need ++ * to do this even if src+dst are the same; it appears ++ * that w/o this bit the crypted data is written ++ * immediately after the bypass data. ++ */ ++ cmd1 |= SAFE_SA_CMD1_HDRCOPY; ++ /* ++ * Disable IP header mutable bit handling. This is ++ * needed to get correct HMAC calculations. ++ */ ++ cmd1 |= SAFE_SA_CMD1_MUTABLE; ++ } else { ++ if (enccrd) { ++ bypass = enccrd->crd_skip; ++ oplen = bypass + enccrd->crd_len; ++ } else { ++ bypass = maccrd->crd_skip; ++ oplen = bypass + maccrd->crd_len; ++ } ++ coffset = 0; ++ } ++ /* XXX verify multiple of 4 when using s/g */ ++ if (bypass > 96) { /* bypass offset must be <= 96 bytes */ ++ DPRINTF(("%s: bypass %u too big\n", __func__, bypass)); ++ safestats.st_bypasstoobig++; ++ err = EINVAL; ++ goto errout; ++ } ++ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ if (pci_map_skb(sc, &re->re_src, re->re_src_skb)) { ++ safestats.st_noload++; ++ err = ENOMEM; ++ goto errout; ++ } ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ if (pci_map_uio(sc, &re->re_src, re->re_src_io)) { ++ safestats.st_noload++; ++ err = ENOMEM; ++ goto errout; ++ } ++ } ++ nicealign = safe_dmamap_aligned(sc, &re->re_src); ++ uniform = safe_dmamap_uniform(sc, &re->re_src); ++ ++ DPRINTF(("src nicealign %u uniform %u nsegs %u\n", ++ nicealign, uniform, re->re_src.nsegs)); ++ if (re->re_src.nsegs > 1) { ++ re->re_desc.d_src = sc->sc_spalloc.dma_paddr + ++ ((caddr_t) sc->sc_spfree - (caddr_t) sc->sc_spring); ++ for (i = 0; i < re->re_src_nsegs; i++) { ++ /* NB: no need to check if there's space */ ++ pd = sc->sc_spfree; ++ if (++(sc->sc_spfree) == sc->sc_springtop) ++ sc->sc_spfree = sc->sc_spring; ++ ++ KASSERT((pd->pd_flags&3) == 0 || ++ (pd->pd_flags&3) == SAFE_PD_DONE, ++ ("bogus source particle descriptor; flags %x", ++ pd->pd_flags)); ++ pd->pd_addr = re->re_src_segs[i].ds_addr; ++ pd->pd_size = re->re_src_segs[i].ds_len; ++ pd->pd_flags = SAFE_PD_READY; ++ } ++ cmd0 |= SAFE_SA_CMD0_IGATHER; ++ } else { ++ /* ++ * No need for gather, reference the operand directly. ++ */ ++ re->re_desc.d_src = re->re_src_segs[0].ds_addr; ++ } ++ ++ if (enccrd == NULL && maccrd != NULL) { ++ /* ++ * Hash op; no destination needed. ++ */ ++ } else { ++ if (crp->crp_flags & (CRYPTO_F_IOV|CRYPTO_F_SKBUF)) { ++ if (!nicealign) { ++ safestats.st_iovmisaligned++; ++ err = EINVAL; ++ goto errout; ++ } ++ if (uniform != 1) { ++ device_printf(sc->sc_dev, "!uniform source\n"); ++ if (!uniform) { ++ /* ++ * There's no way to handle the DMA ++ * requirements with this uio. We ++ * could create a separate DMA area for ++ * the result and then copy it back, ++ * but for now we just bail and return ++ * an error. Note that uio requests ++ * > SAFE_MAX_DSIZE are handled because ++ * the DMA map and segment list for the ++ * destination wil result in a ++ * destination particle list that does ++ * the necessary scatter DMA. ++ */ ++ safestats.st_iovnotuniform++; ++ err = EINVAL; ++ goto errout; ++ } ++ } else ++ re->re_dst = re->re_src; ++ } else { ++ safestats.st_badflags++; ++ err = EINVAL; ++ goto errout; ++ } ++ ++ if (re->re_dst.nsegs > 1) { ++ re->re_desc.d_dst = sc->sc_dpalloc.dma_paddr + ++ ((caddr_t) sc->sc_dpfree - (caddr_t) sc->sc_dpring); ++ for (i = 0; i < re->re_dst_nsegs; i++) { ++ pd = sc->sc_dpfree; ++ KASSERT((pd->pd_flags&3) == 0 || ++ (pd->pd_flags&3) == SAFE_PD_DONE, ++ ("bogus dest particle descriptor; flags %x", ++ pd->pd_flags)); ++ if (++(sc->sc_dpfree) == sc->sc_dpringtop) ++ sc->sc_dpfree = sc->sc_dpring; ++ pd->pd_addr = re->re_dst_segs[i].ds_addr; ++ pd->pd_flags = SAFE_PD_READY; ++ } ++ cmd0 |= SAFE_SA_CMD0_OSCATTER; ++ } else { ++ /* ++ * No need for scatter, reference the operand directly. ++ */ ++ re->re_desc.d_dst = re->re_dst_segs[0].ds_addr; ++ } ++ } ++ ++ /* ++ * All done with setup; fillin the SA command words ++ * and the packet engine descriptor. The operation ++ * is now ready for submission to the hardware. ++ */ ++ sa->sa_cmd0 = cmd0 | SAFE_SA_CMD0_IPCI | SAFE_SA_CMD0_OPCI; ++ sa->sa_cmd1 = cmd1 ++ | (coffset << SAFE_SA_CMD1_OFFSET_S) ++ | SAFE_SA_CMD1_SAREV1 /* Rev 1 SA data structure */ ++ | SAFE_SA_CMD1_SRPCI ++ ; ++ /* ++ * NB: the order of writes is important here. In case the ++ * chip is scanning the ring because of an outstanding request ++ * it might nab this one too. In that case we need to make ++ * sure the setup is complete before we write the length ++ * field of the descriptor as it signals the descriptor is ++ * ready for processing. ++ */ ++ re->re_desc.d_csr = SAFE_PE_CSR_READY | SAFE_PE_CSR_SAPCI; ++ if (maccrd) ++ re->re_desc.d_csr |= SAFE_PE_CSR_LOADSA | SAFE_PE_CSR_HASHFINAL; ++ wmb(); ++ re->re_desc.d_len = oplen ++ | SAFE_PE_LEN_READY ++ | (bypass << SAFE_PE_LEN_BYPASS_S) ++ ; ++ ++ safestats.st_ipackets++; ++ safestats.st_ibytes += oplen; ++ ++ if (++(sc->sc_front) == sc->sc_ringtop) ++ sc->sc_front = sc->sc_ring; ++ ++ /* XXX honor batching */ ++ safe_feed(sc, re); ++ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); ++ return (0); ++ ++errout: ++ if (re->re_src.map != re->re_dst.map) ++ pci_unmap_operand(sc, &re->re_dst); ++ if (re->re_src.map) ++ pci_unmap_operand(sc, &re->re_src); ++ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); ++ if (err != ERESTART) { ++ crp->crp_etype = err; ++ crypto_done(crp); ++ } else { ++ sc->sc_needwakeup |= CRYPTO_SYMQ; ++ } ++ return (err); ++} ++ ++static void ++safe_callback(struct safe_softc *sc, struct safe_ringentry *re) ++{ ++ struct cryptop *crp = (struct cryptop *)re->re_crp; ++ struct cryptodesc *crd; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ safestats.st_opackets++; ++ safestats.st_obytes += re->re_dst.mapsize; ++ ++ if (re->re_desc.d_csr & SAFE_PE_CSR_STATUS) { ++ device_printf(sc->sc_dev, "csr 0x%x cmd0 0x%x cmd1 0x%x\n", ++ re->re_desc.d_csr, ++ re->re_sa.sa_cmd0, re->re_sa.sa_cmd1); ++ safestats.st_peoperr++; ++ crp->crp_etype = EIO; /* something more meaningful? */ ++ } ++ ++ if (re->re_dst.map != NULL && re->re_dst.map != re->re_src.map) ++ pci_unmap_operand(sc, &re->re_dst); ++ pci_unmap_operand(sc, &re->re_src); ++ ++ /* ++ * If result was written to a differet mbuf chain, swap ++ * it in as the return value and reclaim the original. ++ */ ++ if ((crp->crp_flags & CRYPTO_F_SKBUF) && re->re_src_skb != re->re_dst_skb) { ++ device_printf(sc->sc_dev, "no CRYPTO_F_SKBUF swapping support\n"); ++ /* kfree_skb(skb) */ ++ /* crp->crp_buf = (caddr_t)re->re_dst_skb */ ++ return; ++ } ++ ++ if (re->re_flags & SAFE_QFLAGS_COPYOUTICV) { ++ /* copy out ICV result */ ++ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { ++ if (!(crd->crd_alg == CRYPTO_MD5_HMAC || ++ crd->crd_alg == CRYPTO_SHA1_HMAC || ++ crd->crd_alg == CRYPTO_NULL_HMAC)) ++ continue; ++ if (crd->crd_alg == CRYPTO_SHA1_HMAC) { ++ /* ++ * SHA-1 ICV's are byte-swapped; fix 'em up ++ * before copy them to their destination. ++ */ ++ re->re_sastate.sa_saved_indigest[0] = ++ cpu_to_be32(re->re_sastate.sa_saved_indigest[0]); ++ re->re_sastate.sa_saved_indigest[1] = ++ cpu_to_be32(re->re_sastate.sa_saved_indigest[1]); ++ re->re_sastate.sa_saved_indigest[2] = ++ cpu_to_be32(re->re_sastate.sa_saved_indigest[2]); ++ } else { ++ re->re_sastate.sa_saved_indigest[0] = ++ cpu_to_le32(re->re_sastate.sa_saved_indigest[0]); ++ re->re_sastate.sa_saved_indigest[1] = ++ cpu_to_le32(re->re_sastate.sa_saved_indigest[1]); ++ re->re_sastate.sa_saved_indigest[2] = ++ cpu_to_le32(re->re_sastate.sa_saved_indigest[2]); ++ } ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ crd->crd_inject, ++ sc->sc_sessions[re->re_sesn].ses_mlen, ++ (caddr_t)re->re_sastate.sa_saved_indigest); ++ break; ++ } ++ } ++ crypto_done(crp); ++} ++ ++ ++#if defined(CONFIG_OCF_RANDOMHARVEST) && !defined(SAFE_NO_RNG) ++#define SAFE_RNG_MAXWAIT 1000 ++ ++static void ++safe_rng_init(struct safe_softc *sc) ++{ ++ u_int32_t w, v; ++ int i; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ WRITE_REG(sc, SAFE_RNG_CTRL, 0); ++ /* use default value according to the manual */ ++ WRITE_REG(sc, SAFE_RNG_CNFG, 0x834); /* magic from SafeNet */ ++ WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); ++ ++ /* ++ * There is a bug in rev 1.0 of the 1140 that when the RNG ++ * is brought out of reset the ready status flag does not ++ * work until the RNG has finished its internal initialization. ++ * ++ * So in order to determine the device is through its ++ * initialization we must read the data register, using the ++ * status reg in the read in case it is initialized. Then read ++ * the data register until it changes from the first read. ++ * Once it changes read the data register until it changes ++ * again. At this time the RNG is considered initialized. ++ * This could take between 750ms - 1000ms in time. ++ */ ++ i = 0; ++ w = READ_REG(sc, SAFE_RNG_OUT); ++ do { ++ v = READ_REG(sc, SAFE_RNG_OUT); ++ if (v != w) { ++ w = v; ++ break; ++ } ++ DELAY(10); ++ } while (++i < SAFE_RNG_MAXWAIT); ++ ++ /* Wait Until data changes again */ ++ i = 0; ++ do { ++ v = READ_REG(sc, SAFE_RNG_OUT); ++ if (v != w) ++ break; ++ DELAY(10); ++ } while (++i < SAFE_RNG_MAXWAIT); ++} ++ ++static __inline void ++safe_rng_disable_short_cycle(struct safe_softc *sc) ++{ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ WRITE_REG(sc, SAFE_RNG_CTRL, ++ READ_REG(sc, SAFE_RNG_CTRL) &~ SAFE_RNG_CTRL_SHORTEN); ++} ++ ++static __inline void ++safe_rng_enable_short_cycle(struct safe_softc *sc) ++{ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ WRITE_REG(sc, SAFE_RNG_CTRL, ++ READ_REG(sc, SAFE_RNG_CTRL) | SAFE_RNG_CTRL_SHORTEN); ++} ++ ++static __inline u_int32_t ++safe_rng_read(struct safe_softc *sc) ++{ ++ int i; ++ ++ i = 0; ++ while (READ_REG(sc, SAFE_RNG_STAT) != 0 && ++i < SAFE_RNG_MAXWAIT) ++ ; ++ return READ_REG(sc, SAFE_RNG_OUT); ++} ++ ++static int ++safe_read_random(void *arg, u_int32_t *buf, int maxwords) ++{ ++ struct safe_softc *sc = (struct safe_softc *) arg; ++ int i, rc; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ safestats.st_rng++; ++ /* ++ * Fetch the next block of data. ++ */ ++ if (maxwords > safe_rngbufsize) ++ maxwords = safe_rngbufsize; ++ if (maxwords > SAFE_RNG_MAXBUFSIZ) ++ maxwords = SAFE_RNG_MAXBUFSIZ; ++retry: ++ /* read as much as we can */ ++ for (rc = 0; rc < maxwords; rc++) { ++ if (READ_REG(sc, SAFE_RNG_STAT) != 0) ++ break; ++ buf[rc] = READ_REG(sc, SAFE_RNG_OUT); ++ } ++ if (rc == 0) ++ return 0; ++ /* ++ * Check the comparator alarm count and reset the h/w if ++ * it exceeds our threshold. This guards against the ++ * hardware oscillators resonating with external signals. ++ */ ++ if (READ_REG(sc, SAFE_RNG_ALM_CNT) > safe_rngmaxalarm) { ++ u_int32_t freq_inc, w; ++ ++ DPRINTF(("%s: alarm count %u exceeds threshold %u\n", __func__, ++ (unsigned)READ_REG(sc, SAFE_RNG_ALM_CNT), safe_rngmaxalarm)); ++ safestats.st_rngalarm++; ++ safe_rng_enable_short_cycle(sc); ++ freq_inc = 18; ++ for (i = 0; i < 64; i++) { ++ w = READ_REG(sc, SAFE_RNG_CNFG); ++ freq_inc = ((w + freq_inc) & 0x3fL); ++ w = ((w & ~0x3fL) | freq_inc); ++ WRITE_REG(sc, SAFE_RNG_CNFG, w); ++ ++ WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); ++ ++ (void) safe_rng_read(sc); ++ DELAY(25); ++ ++ if (READ_REG(sc, SAFE_RNG_ALM_CNT) == 0) { ++ safe_rng_disable_short_cycle(sc); ++ goto retry; ++ } ++ freq_inc = 1; ++ } ++ safe_rng_disable_short_cycle(sc); ++ } else ++ WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); ++ ++ return(rc); ++} ++#endif /* defined(CONFIG_OCF_RANDOMHARVEST) && !defined(SAFE_NO_RNG) */ ++ ++ ++/* ++ * Resets the board. Values in the regesters are left as is ++ * from the reset (i.e. initial values are assigned elsewhere). ++ */ ++static void ++safe_reset_board(struct safe_softc *sc) ++{ ++ u_int32_t v; ++ /* ++ * Reset the device. The manual says no delay ++ * is needed between marking and clearing reset. ++ */ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ v = READ_REG(sc, SAFE_PE_DMACFG) &~ ++ (SAFE_PE_DMACFG_PERESET | SAFE_PE_DMACFG_PDRRESET | ++ SAFE_PE_DMACFG_SGRESET); ++ WRITE_REG(sc, SAFE_PE_DMACFG, v ++ | SAFE_PE_DMACFG_PERESET ++ | SAFE_PE_DMACFG_PDRRESET ++ | SAFE_PE_DMACFG_SGRESET); ++ WRITE_REG(sc, SAFE_PE_DMACFG, v); ++} ++ ++/* ++ * Initialize registers we need to touch only once. ++ */ ++static void ++safe_init_board(struct safe_softc *sc) ++{ ++ u_int32_t v, dwords; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ v = READ_REG(sc, SAFE_PE_DMACFG); ++ v &=~ ( SAFE_PE_DMACFG_PEMODE ++ | SAFE_PE_DMACFG_FSENA /* failsafe enable */ ++ | SAFE_PE_DMACFG_GPRPCI /* gather ring on PCI */ ++ | SAFE_PE_DMACFG_SPRPCI /* scatter ring on PCI */ ++ | SAFE_PE_DMACFG_ESDESC /* endian-swap descriptors */ ++ | SAFE_PE_DMACFG_ESPDESC /* endian-swap part. desc's */ ++ | SAFE_PE_DMACFG_ESSA /* endian-swap SA's */ ++ | SAFE_PE_DMACFG_ESPACKET /* swap the packet data */ ++ ); ++ v |= SAFE_PE_DMACFG_FSENA /* failsafe enable */ ++ | SAFE_PE_DMACFG_GPRPCI /* gather ring on PCI */ ++ | SAFE_PE_DMACFG_SPRPCI /* scatter ring on PCI */ ++ | SAFE_PE_DMACFG_ESDESC /* endian-swap descriptors */ ++ | SAFE_PE_DMACFG_ESPDESC /* endian-swap part. desc's */ ++ | SAFE_PE_DMACFG_ESSA /* endian-swap SA's */ ++#if 0 ++ | SAFE_PE_DMACFG_ESPACKET /* swap the packet data */ ++#endif ++ ; ++ WRITE_REG(sc, SAFE_PE_DMACFG, v); ++ ++#ifdef __BIG_ENDIAN ++ /* tell the safenet that we are 4321 and not 1234 */ ++ WRITE_REG(sc, SAFE_ENDIAN, 0xe4e41b1b); ++#endif ++ ++ if (sc->sc_chiprev == SAFE_REV(1,0)) { ++ /* ++ * Avoid large PCI DMA transfers. Rev 1.0 has a bug where ++ * "target mode transfers" done while the chip is DMA'ing ++ * >1020 bytes cause the hardware to lockup. To avoid this ++ * we reduce the max PCI transfer size and use small source ++ * particle descriptors (<= 256 bytes). ++ */ ++ WRITE_REG(sc, SAFE_DMA_CFG, 256); ++ device_printf(sc->sc_dev, ++ "Reduce max DMA size to %u words for rev %u.%u WAR\n", ++ (unsigned) ((READ_REG(sc, SAFE_DMA_CFG)>>2) & 0xff), ++ (unsigned) SAFE_REV_MAJ(sc->sc_chiprev), ++ (unsigned) SAFE_REV_MIN(sc->sc_chiprev)); ++ sc->sc_max_dsize = 256; ++ } else { ++ sc->sc_max_dsize = SAFE_MAX_DSIZE; ++ } ++ ++ /* NB: operands+results are overlaid */ ++ WRITE_REG(sc, SAFE_PE_PDRBASE, sc->sc_ringalloc.dma_paddr); ++ WRITE_REG(sc, SAFE_PE_RDRBASE, sc->sc_ringalloc.dma_paddr); ++ /* ++ * Configure ring entry size and number of items in the ring. ++ */ ++ KASSERT((sizeof(struct safe_ringentry) % sizeof(u_int32_t)) == 0, ++ ("PE ring entry not 32-bit aligned!")); ++ dwords = sizeof(struct safe_ringentry) / sizeof(u_int32_t); ++ WRITE_REG(sc, SAFE_PE_RINGCFG, ++ (dwords << SAFE_PE_RINGCFG_OFFSET_S) | SAFE_MAX_NQUEUE); ++ WRITE_REG(sc, SAFE_PE_RINGPOLL, 0); /* disable polling */ ++ ++ WRITE_REG(sc, SAFE_PE_GRNGBASE, sc->sc_spalloc.dma_paddr); ++ WRITE_REG(sc, SAFE_PE_SRNGBASE, sc->sc_dpalloc.dma_paddr); ++ WRITE_REG(sc, SAFE_PE_PARTSIZE, ++ (SAFE_TOTAL_DPART<<16) | SAFE_TOTAL_SPART); ++ /* ++ * NB: destination particles are fixed size. We use ++ * an mbuf cluster and require all results go to ++ * clusters or smaller. ++ */ ++ WRITE_REG(sc, SAFE_PE_PARTCFG, sc->sc_max_dsize); ++ ++ /* it's now safe to enable PE mode, do it */ ++ WRITE_REG(sc, SAFE_PE_DMACFG, v | SAFE_PE_DMACFG_PEMODE); ++ ++ /* ++ * Configure hardware to use level-triggered interrupts and ++ * to interrupt after each descriptor is processed. ++ */ ++ WRITE_REG(sc, SAFE_HI_CFG, SAFE_HI_CFG_LEVEL); ++ WRITE_REG(sc, SAFE_HI_CLR, 0xffffffff); ++ WRITE_REG(sc, SAFE_HI_DESC_CNT, 1); ++ WRITE_REG(sc, SAFE_HI_MASK, SAFE_INT_PE_DDONE | SAFE_INT_PE_ERROR); ++} ++ ++ ++/* ++ * Clean up after a chip crash. ++ * It is assumed that the caller in splimp() ++ */ ++static void ++safe_cleanchip(struct safe_softc *sc) ++{ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ if (sc->sc_nqchip != 0) { ++ struct safe_ringentry *re = sc->sc_back; ++ ++ while (re != sc->sc_front) { ++ if (re->re_desc.d_csr != 0) ++ safe_free_entry(sc, re); ++ if (++re == sc->sc_ringtop) ++ re = sc->sc_ring; ++ } ++ sc->sc_back = re; ++ sc->sc_nqchip = 0; ++ } ++} ++ ++/* ++ * free a safe_q ++ * It is assumed that the caller is within splimp(). ++ */ ++static int ++safe_free_entry(struct safe_softc *sc, struct safe_ringentry *re) ++{ ++ struct cryptop *crp; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ /* ++ * Free header MCR ++ */ ++ if ((re->re_dst_skb != NULL) && (re->re_src_skb != re->re_dst_skb)) ++#ifdef NOTYET ++ m_freem(re->re_dst_m); ++#else ++ printk("%s,%d: SKB not supported\n", __FILE__, __LINE__); ++#endif ++ ++ crp = (struct cryptop *)re->re_crp; ++ ++ re->re_desc.d_csr = 0; ++ ++ crp->crp_etype = EFAULT; ++ crypto_done(crp); ++ return(0); ++} ++ ++/* ++ * Routine to reset the chip and clean up. ++ * It is assumed that the caller is in splimp() ++ */ ++static void ++safe_totalreset(struct safe_softc *sc) ++{ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ safe_reset_board(sc); ++ safe_init_board(sc); ++ safe_cleanchip(sc); ++} ++ ++/* ++ * Is the operand suitable aligned for direct DMA. Each ++ * segment must be aligned on a 32-bit boundary and all ++ * but the last segment must be a multiple of 4 bytes. ++ */ ++static int ++safe_dmamap_aligned(struct safe_softc *sc, const struct safe_operand *op) ++{ ++ int i; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ for (i = 0; i < op->nsegs; i++) { ++ if (op->segs[i].ds_addr & 3) ++ return (0); ++ if (i != (op->nsegs - 1) && (op->segs[i].ds_len & 3)) ++ return (0); ++ } ++ return (1); ++} ++ ++/* ++ * Is the operand suitable for direct DMA as the destination ++ * of an operation. The hardware requires that each ``particle'' ++ * but the last in an operation result have the same size. We ++ * fix that size at SAFE_MAX_DSIZE bytes. This routine returns ++ * 0 if some segment is not a multiple of of this size, 1 if all ++ * segments are exactly this size, or 2 if segments are at worst ++ * a multple of this size. ++ */ ++static int ++safe_dmamap_uniform(struct safe_softc *sc, const struct safe_operand *op) ++{ ++ int result = 1; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ if (op->nsegs > 0) { ++ int i; ++ ++ for (i = 0; i < op->nsegs-1; i++) { ++ if (op->segs[i].ds_len % sc->sc_max_dsize) ++ return (0); ++ if (op->segs[i].ds_len != sc->sc_max_dsize) ++ result = 2; ++ } ++ } ++ return (result); ++} ++ ++static int ++safe_kprocess(device_t dev, struct cryptkop *krp, int hint) ++{ ++ struct safe_softc *sc = device_get_softc(dev); ++ struct safe_pkq *q; ++ unsigned long flags; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ if (sc == NULL) { ++ krp->krp_status = EINVAL; ++ goto err; ++ } ++ ++ if (krp->krp_op != CRK_MOD_EXP) { ++ krp->krp_status = EOPNOTSUPP; ++ goto err; ++ } ++ ++ q = (struct safe_pkq *) kmalloc(sizeof(*q), GFP_KERNEL); ++ if (q == NULL) { ++ krp->krp_status = ENOMEM; ++ goto err; ++ } ++ memset(q, 0, sizeof(*q)); ++ q->pkq_krp = krp; ++ INIT_LIST_HEAD(&q->pkq_list); ++ ++ spin_lock_irqsave(&sc->sc_pkmtx, flags); ++ list_add_tail(&q->pkq_list, &sc->sc_pkq); ++ safe_kfeed(sc); ++ spin_unlock_irqrestore(&sc->sc_pkmtx, flags); ++ return (0); ++ ++err: ++ crypto_kdone(krp); ++ return (0); ++} ++ ++#define SAFE_CRK_PARAM_BASE 0 ++#define SAFE_CRK_PARAM_EXP 1 ++#define SAFE_CRK_PARAM_MOD 2 ++ ++static int ++safe_kstart(struct safe_softc *sc) ++{ ++ struct cryptkop *krp = sc->sc_pkq_cur->pkq_krp; ++ int exp_bits, mod_bits, base_bits; ++ u_int32_t op, a_off, b_off, c_off, d_off; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ if (krp->krp_iparams < 3 || krp->krp_oparams != 1) { ++ krp->krp_status = EINVAL; ++ return (1); ++ } ++ ++ base_bits = safe_ksigbits(sc, &krp->krp_param[SAFE_CRK_PARAM_BASE]); ++ if (base_bits > 2048) ++ goto too_big; ++ if (base_bits <= 0) /* 5. base not zero */ ++ goto too_small; ++ ++ exp_bits = safe_ksigbits(sc, &krp->krp_param[SAFE_CRK_PARAM_EXP]); ++ if (exp_bits > 2048) ++ goto too_big; ++ if (exp_bits <= 0) /* 1. exponent word length > 0 */ ++ goto too_small; /* 4. exponent not zero */ ++ ++ mod_bits = safe_ksigbits(sc, &krp->krp_param[SAFE_CRK_PARAM_MOD]); ++ if (mod_bits > 2048) ++ goto too_big; ++ if (mod_bits <= 32) /* 2. modulus word length > 1 */ ++ goto too_small; /* 8. MSW of modulus != zero */ ++ if (mod_bits < exp_bits) /* 3 modulus len >= exponent len */ ++ goto too_small; ++ if ((krp->krp_param[SAFE_CRK_PARAM_MOD].crp_p[0] & 1) == 0) ++ goto bad_domain; /* 6. modulus is odd */ ++ if (mod_bits > krp->krp_param[krp->krp_iparams].crp_nbits) ++ goto too_small; /* make sure result will fit */ ++ ++ /* 7. modulus > base */ ++ if (mod_bits < base_bits) ++ goto too_small; ++ if (mod_bits == base_bits) { ++ u_int8_t *basep, *modp; ++ int i; ++ ++ basep = krp->krp_param[SAFE_CRK_PARAM_BASE].crp_p + ++ ((base_bits + 7) / 8) - 1; ++ modp = krp->krp_param[SAFE_CRK_PARAM_MOD].crp_p + ++ ((mod_bits + 7) / 8) - 1; ++ ++ for (i = 0; i < (mod_bits + 7) / 8; i++, basep--, modp--) { ++ if (*modp < *basep) ++ goto too_small; ++ if (*modp > *basep) ++ break; ++ } ++ } ++ ++ /* And on the 9th step, he rested. */ ++ ++ WRITE_REG(sc, SAFE_PK_A_LEN, (exp_bits + 31) / 32); ++ WRITE_REG(sc, SAFE_PK_B_LEN, (mod_bits + 31) / 32); ++ if (mod_bits > 1024) { ++ op = SAFE_PK_FUNC_EXP4; ++ a_off = 0x000; ++ b_off = 0x100; ++ c_off = 0x200; ++ d_off = 0x300; ++ } else { ++ op = SAFE_PK_FUNC_EXP16; ++ a_off = 0x000; ++ b_off = 0x080; ++ c_off = 0x100; ++ d_off = 0x180; ++ } ++ sc->sc_pk_reslen = b_off - a_off; ++ sc->sc_pk_resoff = d_off; ++ ++ /* A is exponent, B is modulus, C is base, D is result */ ++ safe_kload_reg(sc, a_off, b_off - a_off, ++ &krp->krp_param[SAFE_CRK_PARAM_EXP]); ++ WRITE_REG(sc, SAFE_PK_A_ADDR, a_off >> 2); ++ safe_kload_reg(sc, b_off, b_off - a_off, ++ &krp->krp_param[SAFE_CRK_PARAM_MOD]); ++ WRITE_REG(sc, SAFE_PK_B_ADDR, b_off >> 2); ++ safe_kload_reg(sc, c_off, b_off - a_off, ++ &krp->krp_param[SAFE_CRK_PARAM_BASE]); ++ WRITE_REG(sc, SAFE_PK_C_ADDR, c_off >> 2); ++ WRITE_REG(sc, SAFE_PK_D_ADDR, d_off >> 2); ++ ++ WRITE_REG(sc, SAFE_PK_FUNC, op | SAFE_PK_FUNC_RUN); ++ ++ return (0); ++ ++too_big: ++ krp->krp_status = E2BIG; ++ return (1); ++too_small: ++ krp->krp_status = ERANGE; ++ return (1); ++bad_domain: ++ krp->krp_status = EDOM; ++ return (1); ++} ++ ++static int ++safe_ksigbits(struct safe_softc *sc, struct crparam *cr) ++{ ++ u_int plen = (cr->crp_nbits + 7) / 8; ++ int i, sig = plen * 8; ++ u_int8_t c, *p = cr->crp_p; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ for (i = plen - 1; i >= 0; i--) { ++ c = p[i]; ++ if (c != 0) { ++ while ((c & 0x80) == 0) { ++ sig--; ++ c <<= 1; ++ } ++ break; ++ } ++ sig -= 8; ++ } ++ return (sig); ++} ++ ++static void ++safe_kfeed(struct safe_softc *sc) ++{ ++ struct safe_pkq *q, *tmp; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ if (list_empty(&sc->sc_pkq) && sc->sc_pkq_cur == NULL) ++ return; ++ if (sc->sc_pkq_cur != NULL) ++ return; ++ list_for_each_entry_safe(q, tmp, &sc->sc_pkq, pkq_list) { ++ sc->sc_pkq_cur = q; ++ list_del(&q->pkq_list); ++ if (safe_kstart(sc) != 0) { ++ crypto_kdone(q->pkq_krp); ++ kfree(q); ++ sc->sc_pkq_cur = NULL; ++ } else { ++ /* op started, start polling */ ++ mod_timer(&sc->sc_pkto, jiffies + 1); ++ break; ++ } ++ } ++} ++ ++static void ++safe_kpoll(unsigned long arg) ++{ ++ struct safe_softc *sc = NULL; ++ struct safe_pkq *q; ++ struct crparam *res; ++ int i; ++ u_int32_t buf[64]; ++ unsigned long flags; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ if (arg >= SAFE_MAX_CHIPS) ++ return; ++ sc = safe_chip_idx[arg]; ++ if (!sc) { ++ DPRINTF(("%s() - bad callback\n", __FUNCTION__)); ++ return; ++ } ++ ++ spin_lock_irqsave(&sc->sc_pkmtx, flags); ++ if (sc->sc_pkq_cur == NULL) ++ goto out; ++ if (READ_REG(sc, SAFE_PK_FUNC) & SAFE_PK_FUNC_RUN) { ++ /* still running, check back later */ ++ mod_timer(&sc->sc_pkto, jiffies + 1); ++ goto out; ++ } ++ ++ q = sc->sc_pkq_cur; ++ res = &q->pkq_krp->krp_param[q->pkq_krp->krp_iparams]; ++ bzero(buf, sizeof(buf)); ++ bzero(res->crp_p, (res->crp_nbits + 7) / 8); ++ for (i = 0; i < sc->sc_pk_reslen >> 2; i++) ++ buf[i] = le32_to_cpu(READ_REG(sc, SAFE_PK_RAM_START + ++ sc->sc_pk_resoff + (i << 2))); ++ bcopy(buf, res->crp_p, (res->crp_nbits + 7) / 8); ++ /* ++ * reduce the bits that need copying if possible ++ */ ++ res->crp_nbits = min(res->crp_nbits,sc->sc_pk_reslen * 8); ++ res->crp_nbits = safe_ksigbits(sc, res); ++ ++ for (i = SAFE_PK_RAM_START; i < SAFE_PK_RAM_END; i += 4) ++ WRITE_REG(sc, i, 0); ++ ++ crypto_kdone(q->pkq_krp); ++ kfree(q); ++ sc->sc_pkq_cur = NULL; ++ ++ safe_kfeed(sc); ++out: ++ spin_unlock_irqrestore(&sc->sc_pkmtx, flags); ++} ++ ++static void ++safe_kload_reg(struct safe_softc *sc, u_int32_t off, u_int32_t len, ++ struct crparam *n) ++{ ++ u_int32_t buf[64], i; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ bzero(buf, sizeof(buf)); ++ bcopy(n->crp_p, buf, (n->crp_nbits + 7) / 8); ++ ++ for (i = 0; i < len >> 2; i++) ++ WRITE_REG(sc, SAFE_PK_RAM_START + off + (i << 2), ++ cpu_to_le32(buf[i])); ++} ++ ++#ifdef SAFE_DEBUG ++static void ++safe_dump_dmastatus(struct safe_softc *sc, const char *tag) ++{ ++ printf("%s: ENDIAN 0x%x SRC 0x%x DST 0x%x STAT 0x%x\n" ++ , tag ++ , READ_REG(sc, SAFE_DMA_ENDIAN) ++ , READ_REG(sc, SAFE_DMA_SRCADDR) ++ , READ_REG(sc, SAFE_DMA_DSTADDR) ++ , READ_REG(sc, SAFE_DMA_STAT) ++ ); ++} ++ ++static void ++safe_dump_intrstate(struct safe_softc *sc, const char *tag) ++{ ++ printf("%s: HI_CFG 0x%x HI_MASK 0x%x HI_DESC_CNT 0x%x HU_STAT 0x%x HM_STAT 0x%x\n" ++ , tag ++ , READ_REG(sc, SAFE_HI_CFG) ++ , READ_REG(sc, SAFE_HI_MASK) ++ , READ_REG(sc, SAFE_HI_DESC_CNT) ++ , READ_REG(sc, SAFE_HU_STAT) ++ , READ_REG(sc, SAFE_HM_STAT) ++ ); ++} ++ ++static void ++safe_dump_ringstate(struct safe_softc *sc, const char *tag) ++{ ++ u_int32_t estat = READ_REG(sc, SAFE_PE_ERNGSTAT); ++ ++ /* NB: assume caller has lock on ring */ ++ printf("%s: ERNGSTAT %x (next %u) back %lu front %lu\n", ++ tag, ++ estat, (estat >> SAFE_PE_ERNGSTAT_NEXT_S), ++ (unsigned long)(sc->sc_back - sc->sc_ring), ++ (unsigned long)(sc->sc_front - sc->sc_ring)); ++} ++ ++static void ++safe_dump_request(struct safe_softc *sc, const char* tag, struct safe_ringentry *re) ++{ ++ int ix, nsegs; ++ ++ ix = re - sc->sc_ring; ++ printf("%s: %p (%u): csr %x src %x dst %x sa %x len %x\n" ++ , tag ++ , re, ix ++ , re->re_desc.d_csr ++ , re->re_desc.d_src ++ , re->re_desc.d_dst ++ , re->re_desc.d_sa ++ , re->re_desc.d_len ++ ); ++ if (re->re_src.nsegs > 1) { ++ ix = (re->re_desc.d_src - sc->sc_spalloc.dma_paddr) / ++ sizeof(struct safe_pdesc); ++ for (nsegs = re->re_src.nsegs; nsegs; nsegs--) { ++ printf(" spd[%u] %p: %p size %u flags %x" ++ , ix, &sc->sc_spring[ix] ++ , (caddr_t)(uintptr_t) sc->sc_spring[ix].pd_addr ++ , sc->sc_spring[ix].pd_size ++ , sc->sc_spring[ix].pd_flags ++ ); ++ if (sc->sc_spring[ix].pd_size == 0) ++ printf(" (zero!)"); ++ printf("\n"); ++ if (++ix == SAFE_TOTAL_SPART) ++ ix = 0; ++ } ++ } ++ if (re->re_dst.nsegs > 1) { ++ ix = (re->re_desc.d_dst - sc->sc_dpalloc.dma_paddr) / ++ sizeof(struct safe_pdesc); ++ for (nsegs = re->re_dst.nsegs; nsegs; nsegs--) { ++ printf(" dpd[%u] %p: %p flags %x\n" ++ , ix, &sc->sc_dpring[ix] ++ , (caddr_t)(uintptr_t) sc->sc_dpring[ix].pd_addr ++ , sc->sc_dpring[ix].pd_flags ++ ); ++ if (++ix == SAFE_TOTAL_DPART) ++ ix = 0; ++ } ++ } ++ printf("sa: cmd0 %08x cmd1 %08x staterec %x\n", ++ re->re_sa.sa_cmd0, re->re_sa.sa_cmd1, re->re_sa.sa_staterec); ++ printf("sa: key %x %x %x %x %x %x %x %x\n" ++ , re->re_sa.sa_key[0] ++ , re->re_sa.sa_key[1] ++ , re->re_sa.sa_key[2] ++ , re->re_sa.sa_key[3] ++ , re->re_sa.sa_key[4] ++ , re->re_sa.sa_key[5] ++ , re->re_sa.sa_key[6] ++ , re->re_sa.sa_key[7] ++ ); ++ printf("sa: indigest %x %x %x %x %x\n" ++ , re->re_sa.sa_indigest[0] ++ , re->re_sa.sa_indigest[1] ++ , re->re_sa.sa_indigest[2] ++ , re->re_sa.sa_indigest[3] ++ , re->re_sa.sa_indigest[4] ++ ); ++ printf("sa: outdigest %x %x %x %x %x\n" ++ , re->re_sa.sa_outdigest[0] ++ , re->re_sa.sa_outdigest[1] ++ , re->re_sa.sa_outdigest[2] ++ , re->re_sa.sa_outdigest[3] ++ , re->re_sa.sa_outdigest[4] ++ ); ++ printf("sr: iv %x %x %x %x\n" ++ , re->re_sastate.sa_saved_iv[0] ++ , re->re_sastate.sa_saved_iv[1] ++ , re->re_sastate.sa_saved_iv[2] ++ , re->re_sastate.sa_saved_iv[3] ++ ); ++ printf("sr: hashbc %u indigest %x %x %x %x %x\n" ++ , re->re_sastate.sa_saved_hashbc ++ , re->re_sastate.sa_saved_indigest[0] ++ , re->re_sastate.sa_saved_indigest[1] ++ , re->re_sastate.sa_saved_indigest[2] ++ , re->re_sastate.sa_saved_indigest[3] ++ , re->re_sastate.sa_saved_indigest[4] ++ ); ++} ++ ++static void ++safe_dump_ring(struct safe_softc *sc, const char *tag) ++{ ++ unsigned long flags; ++ ++ spin_lock_irqsave(&sc->sc_ringmtx, flags); ++ printf("\nSafeNet Ring State:\n"); ++ safe_dump_intrstate(sc, tag); ++ safe_dump_dmastatus(sc, tag); ++ safe_dump_ringstate(sc, tag); ++ if (sc->sc_nqchip) { ++ struct safe_ringentry *re = sc->sc_back; ++ do { ++ safe_dump_request(sc, tag, re); ++ if (++re == sc->sc_ringtop) ++ re = sc->sc_ring; ++ } while (re != sc->sc_front); ++ } ++ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); ++} ++#endif /* SAFE_DEBUG */ ++ ++ ++static int safe_probe(struct pci_dev *dev, const struct pci_device_id *ent) ++{ ++ struct safe_softc *sc = NULL; ++ u32 mem_start, mem_len, cmd; ++ int i, rc, devinfo; ++ dma_addr_t raddr; ++ static int num_chips = 0; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ if (pci_enable_device(dev) < 0) ++ return(-ENODEV); ++ ++ if (!dev->irq) { ++ printk("safe: found device with no IRQ assigned. check BIOS settings!"); ++ pci_disable_device(dev); ++ return(-ENODEV); ++ } ++ ++ if (pci_set_mwi(dev)) { ++ printk("safe: pci_set_mwi failed!"); ++ return(-ENODEV); ++ } ++ ++ sc = (struct safe_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); ++ if (!sc) ++ return(-ENOMEM); ++ memset(sc, 0, sizeof(*sc)); ++ ++ softc_device_init(sc, "safe", num_chips, safe_methods); ++ ++ sc->sc_irq = -1; ++ sc->sc_cid = -1; ++ sc->sc_pcidev = dev; ++ if (num_chips < SAFE_MAX_CHIPS) { ++ safe_chip_idx[device_get_unit(sc->sc_dev)] = sc; ++ num_chips++; ++ } ++ ++ INIT_LIST_HEAD(&sc->sc_pkq); ++ spin_lock_init(&sc->sc_pkmtx); ++ ++ pci_set_drvdata(sc->sc_pcidev, sc); ++ ++ /* we read its hardware registers as memory */ ++ mem_start = pci_resource_start(sc->sc_pcidev, 0); ++ mem_len = pci_resource_len(sc->sc_pcidev, 0); ++ ++ sc->sc_base_addr = (ocf_iomem_t) ioremap(mem_start, mem_len); ++ if (!sc->sc_base_addr) { ++ device_printf(sc->sc_dev, "failed to ioremap 0x%x-0x%x\n", ++ mem_start, mem_start + mem_len - 1); ++ goto out; ++ } ++ ++ /* fix up the bus size */ ++ if (pci_set_dma_mask(sc->sc_pcidev, DMA_32BIT_MASK)) { ++ device_printf(sc->sc_dev, "No usable DMA configuration, aborting.\n"); ++ goto out; ++ } ++ if (pci_set_consistent_dma_mask(sc->sc_pcidev, DMA_32BIT_MASK)) { ++ device_printf(sc->sc_dev, "No usable consistent DMA configuration, aborting.\n"); ++ goto out; ++ } ++ ++ pci_set_master(sc->sc_pcidev); ++ ++ pci_read_config_dword(sc->sc_pcidev, PCI_COMMAND, &cmd); ++ ++ if (!(cmd & PCI_COMMAND_MEMORY)) { ++ device_printf(sc->sc_dev, "failed to enable memory mapping\n"); ++ goto out; ++ } ++ ++ if (!(cmd & PCI_COMMAND_MASTER)) { ++ device_printf(sc->sc_dev, "failed to enable bus mastering\n"); ++ goto out; ++ } ++ ++ rc = request_irq(dev->irq, safe_intr, IRQF_SHARED, "safe", sc); ++ if (rc) { ++ device_printf(sc->sc_dev, "failed to hook irq %d\n", sc->sc_irq); ++ goto out; ++ } ++ sc->sc_irq = dev->irq; ++ ++ sc->sc_chiprev = READ_REG(sc, SAFE_DEVINFO) & ++ (SAFE_DEVINFO_REV_MAJ | SAFE_DEVINFO_REV_MIN); ++ ++ /* ++ * Allocate packet engine descriptors. ++ */ ++ sc->sc_ringalloc.dma_vaddr = pci_alloc_consistent(sc->sc_pcidev, ++ SAFE_MAX_NQUEUE * sizeof (struct safe_ringentry), ++ &sc->sc_ringalloc.dma_paddr); ++ if (!sc->sc_ringalloc.dma_vaddr) { ++ device_printf(sc->sc_dev, "cannot allocate PE descriptor ring\n"); ++ goto out; ++ } ++ ++ /* ++ * Hookup the static portion of all our data structures. ++ */ ++ sc->sc_ring = (struct safe_ringentry *) sc->sc_ringalloc.dma_vaddr; ++ sc->sc_ringtop = sc->sc_ring + SAFE_MAX_NQUEUE; ++ sc->sc_front = sc->sc_ring; ++ sc->sc_back = sc->sc_ring; ++ raddr = sc->sc_ringalloc.dma_paddr; ++ bzero(sc->sc_ring, SAFE_MAX_NQUEUE * sizeof(struct safe_ringentry)); ++ for (i = 0; i < SAFE_MAX_NQUEUE; i++) { ++ struct safe_ringentry *re = &sc->sc_ring[i]; ++ ++ re->re_desc.d_sa = raddr + ++ offsetof(struct safe_ringentry, re_sa); ++ re->re_sa.sa_staterec = raddr + ++ offsetof(struct safe_ringentry, re_sastate); ++ ++ raddr += sizeof (struct safe_ringentry); ++ } ++ spin_lock_init(&sc->sc_ringmtx); ++ ++ /* ++ * Allocate scatter and gather particle descriptors. ++ */ ++ sc->sc_spalloc.dma_vaddr = pci_alloc_consistent(sc->sc_pcidev, ++ SAFE_TOTAL_SPART * sizeof (struct safe_pdesc), ++ &sc->sc_spalloc.dma_paddr); ++ if (!sc->sc_spalloc.dma_vaddr) { ++ device_printf(sc->sc_dev, "cannot allocate source particle descriptor ring\n"); ++ goto out; ++ } ++ sc->sc_spring = (struct safe_pdesc *) sc->sc_spalloc.dma_vaddr; ++ sc->sc_springtop = sc->sc_spring + SAFE_TOTAL_SPART; ++ sc->sc_spfree = sc->sc_spring; ++ bzero(sc->sc_spring, SAFE_TOTAL_SPART * sizeof(struct safe_pdesc)); ++ ++ sc->sc_dpalloc.dma_vaddr = pci_alloc_consistent(sc->sc_pcidev, ++ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), ++ &sc->sc_dpalloc.dma_paddr); ++ if (!sc->sc_dpalloc.dma_vaddr) { ++ device_printf(sc->sc_dev, "cannot allocate destination particle descriptor ring\n"); ++ goto out; ++ } ++ sc->sc_dpring = (struct safe_pdesc *) sc->sc_dpalloc.dma_vaddr; ++ sc->sc_dpringtop = sc->sc_dpring + SAFE_TOTAL_DPART; ++ sc->sc_dpfree = sc->sc_dpring; ++ bzero(sc->sc_dpring, SAFE_TOTAL_DPART * sizeof(struct safe_pdesc)); ++ ++ sc->sc_cid = crypto_get_driverid(softc_get_device(sc), CRYPTOCAP_F_HARDWARE); ++ if (sc->sc_cid < 0) { ++ device_printf(sc->sc_dev, "could not get crypto driver id\n"); ++ goto out; ++ } ++ ++ printf("%s:", device_get_nameunit(sc->sc_dev)); ++ ++ devinfo = READ_REG(sc, SAFE_DEVINFO); ++ if (devinfo & SAFE_DEVINFO_RNG) { ++ sc->sc_flags |= SAFE_FLAGS_RNG; ++ printf(" rng"); ++ } ++ if (devinfo & SAFE_DEVINFO_PKEY) { ++ printf(" key"); ++ sc->sc_flags |= SAFE_FLAGS_KEY; ++ crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0); ++#if 0 ++ crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0); ++#endif ++ init_timer(&sc->sc_pkto); ++ sc->sc_pkto.function = safe_kpoll; ++ sc->sc_pkto.data = (unsigned long) device_get_unit(sc->sc_dev); ++ } ++ if (devinfo & SAFE_DEVINFO_DES) { ++ printf(" des/3des"); ++ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); ++ } ++ if (devinfo & SAFE_DEVINFO_AES) { ++ printf(" aes"); ++ crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); ++ } ++ if (devinfo & SAFE_DEVINFO_MD5) { ++ printf(" md5"); ++ crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); ++ } ++ if (devinfo & SAFE_DEVINFO_SHA1) { ++ printf(" sha1"); ++ crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); ++ } ++ printf(" null"); ++ crypto_register(sc->sc_cid, CRYPTO_NULL_CBC, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_NULL_HMAC, 0, 0); ++ /* XXX other supported algorithms */ ++ printf("\n"); ++ ++ safe_reset_board(sc); /* reset h/w */ ++ safe_init_board(sc); /* init h/w */ ++ ++#if defined(CONFIG_OCF_RANDOMHARVEST) && !defined(SAFE_NO_RNG) ++ if (sc->sc_flags & SAFE_FLAGS_RNG) { ++ safe_rng_init(sc); ++ crypto_rregister(sc->sc_cid, safe_read_random, sc); ++ } ++#endif /* SAFE_NO_RNG */ ++ ++ return (0); ++ ++out: ++ if (sc->sc_cid >= 0) ++ crypto_unregister_all(sc->sc_cid); ++ if (sc->sc_irq != -1) ++ free_irq(sc->sc_irq, sc); ++ if (sc->sc_ringalloc.dma_vaddr) ++ pci_free_consistent(sc->sc_pcidev, ++ SAFE_MAX_NQUEUE * sizeof (struct safe_ringentry), ++ sc->sc_ringalloc.dma_vaddr, sc->sc_ringalloc.dma_paddr); ++ if (sc->sc_spalloc.dma_vaddr) ++ pci_free_consistent(sc->sc_pcidev, ++ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), ++ sc->sc_spalloc.dma_vaddr, sc->sc_spalloc.dma_paddr); ++ if (sc->sc_dpalloc.dma_vaddr) ++ pci_free_consistent(sc->sc_pcidev, ++ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), ++ sc->sc_dpalloc.dma_vaddr, sc->sc_dpalloc.dma_paddr); ++ kfree(sc); ++ return(-ENODEV); ++} ++ ++static void safe_remove(struct pci_dev *dev) ++{ ++ struct safe_softc *sc = pci_get_drvdata(dev); ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ /* XXX wait/abort active ops */ ++ ++ WRITE_REG(sc, SAFE_HI_MASK, 0); /* disable interrupts */ ++ ++ del_timer_sync(&sc->sc_pkto); ++ ++ crypto_unregister_all(sc->sc_cid); ++ ++ safe_cleanchip(sc); ++ ++ if (sc->sc_irq != -1) ++ free_irq(sc->sc_irq, sc); ++ if (sc->sc_ringalloc.dma_vaddr) ++ pci_free_consistent(sc->sc_pcidev, ++ SAFE_MAX_NQUEUE * sizeof (struct safe_ringentry), ++ sc->sc_ringalloc.dma_vaddr, sc->sc_ringalloc.dma_paddr); ++ if (sc->sc_spalloc.dma_vaddr) ++ pci_free_consistent(sc->sc_pcidev, ++ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), ++ sc->sc_spalloc.dma_vaddr, sc->sc_spalloc.dma_paddr); ++ if (sc->sc_dpalloc.dma_vaddr) ++ pci_free_consistent(sc->sc_pcidev, ++ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), ++ sc->sc_dpalloc.dma_vaddr, sc->sc_dpalloc.dma_paddr); ++ sc->sc_irq = -1; ++ sc->sc_ringalloc.dma_vaddr = NULL; ++ sc->sc_spalloc.dma_vaddr = NULL; ++ sc->sc_dpalloc.dma_vaddr = NULL; ++} ++ ++static struct pci_device_id safe_pci_tbl[] = { ++ { PCI_VENDOR_SAFENET, PCI_PRODUCT_SAFEXCEL, ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(pci, safe_pci_tbl); ++ ++static struct pci_driver safe_driver = { ++ .name = "safe", ++ .id_table = safe_pci_tbl, ++ .probe = safe_probe, ++ .remove = safe_remove, ++ /* add PM stuff here one day */ ++}; ++ ++static int __init safe_init (void) ++{ ++ struct safe_softc *sc = NULL; ++ int rc; ++ ++ DPRINTF(("%s(%p)\n", __FUNCTION__, safe_init)); ++ ++ rc = pci_register_driver(&safe_driver); ++ pci_register_driver_compat(&safe_driver, rc); ++ ++ return rc; ++} ++ ++static void __exit safe_exit (void) ++{ ++ pci_unregister_driver(&safe_driver); ++} ++ ++module_init(safe_init); ++module_exit(safe_exit); ++ ++MODULE_LICENSE("BSD"); ++MODULE_AUTHOR("David McCullough "); ++MODULE_DESCRIPTION("OCF driver for safenet PCI crypto devices"); +diff -Nur linux-3.0.4.orig/crypto/ocf/safe/safereg.h linux-3.0.4/crypto/ocf/safe/safereg.h +--- linux-3.0.4.orig/crypto/ocf/safe/safereg.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/safe/safereg.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,421 @@ ++/*- ++ * Copyright (c) 2003 Sam Leffler, Errno Consulting ++ * Copyright (c) 2003 Global Technology Associates, Inc. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE ++ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ++ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ++ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF ++ * SUCH DAMAGE. ++ * ++ * $FreeBSD: src/sys/dev/safe/safereg.h,v 1.1 2003/07/21 21:46:07 sam Exp $ ++ */ ++#ifndef _SAFE_SAFEREG_H_ ++#define _SAFE_SAFEREG_H_ ++ ++/* ++ * Register definitions for SafeNet SafeXcel-1141 crypto device. ++ * Definitions from revision 1.3 (Nov 6 2002) of the User's Manual. ++ */ ++ ++#define BS_BAR 0x10 /* DMA base address register */ ++#define BS_TRDY_TIMEOUT 0x40 /* TRDY timeout */ ++#define BS_RETRY_TIMEOUT 0x41 /* DMA retry timeout */ ++ ++#define PCI_VENDOR_SAFENET 0x16ae /* SafeNet, Inc. */ ++ ++/* SafeNet */ ++#define PCI_PRODUCT_SAFEXCEL 0x1141 /* 1141 */ ++ ++#define SAFE_PE_CSR 0x0000 /* Packet Enginge Ctrl/Status */ ++#define SAFE_PE_SRC 0x0004 /* Packet Engine Source */ ++#define SAFE_PE_DST 0x0008 /* Packet Engine Destination */ ++#define SAFE_PE_SA 0x000c /* Packet Engine SA */ ++#define SAFE_PE_LEN 0x0010 /* Packet Engine Length */ ++#define SAFE_PE_DMACFG 0x0040 /* Packet Engine DMA Configuration */ ++#define SAFE_PE_DMASTAT 0x0044 /* Packet Engine DMA Status */ ++#define SAFE_PE_PDRBASE 0x0048 /* Packet Engine Descriptor Ring Base */ ++#define SAFE_PE_RDRBASE 0x004c /* Packet Engine Result Ring Base */ ++#define SAFE_PE_RINGCFG 0x0050 /* Packet Engine Ring Configuration */ ++#define SAFE_PE_RINGPOLL 0x0054 /* Packet Engine Ring Poll */ ++#define SAFE_PE_IRNGSTAT 0x0058 /* Packet Engine Internal Ring Status */ ++#define SAFE_PE_ERNGSTAT 0x005c /* Packet Engine External Ring Status */ ++#define SAFE_PE_IOTHRESH 0x0060 /* Packet Engine I/O Threshold */ ++#define SAFE_PE_GRNGBASE 0x0064 /* Packet Engine Gather Ring Base */ ++#define SAFE_PE_SRNGBASE 0x0068 /* Packet Engine Scatter Ring Base */ ++#define SAFE_PE_PARTSIZE 0x006c /* Packet Engine Particlar Ring Size */ ++#define SAFE_PE_PARTCFG 0x0070 /* Packet Engine Particle Ring Config */ ++#define SAFE_CRYPTO_CTRL 0x0080 /* Crypto Control */ ++#define SAFE_DEVID 0x0084 /* Device ID */ ++#define SAFE_DEVINFO 0x0088 /* Device Info */ ++#define SAFE_HU_STAT 0x00a0 /* Host Unmasked Status */ ++#define SAFE_HM_STAT 0x00a4 /* Host Masked Status (read-only) */ ++#define SAFE_HI_CLR 0x00a4 /* Host Clear Interrupt (write-only) */ ++#define SAFE_HI_MASK 0x00a8 /* Host Mask Control */ ++#define SAFE_HI_CFG 0x00ac /* Interrupt Configuration */ ++#define SAFE_HI_RD_DESCR 0x00b4 /* Force Descriptor Read */ ++#define SAFE_HI_DESC_CNT 0x00b8 /* Host Descriptor Done Count */ ++#define SAFE_DMA_ENDIAN 0x00c0 /* Master Endian Status */ ++#define SAFE_DMA_SRCADDR 0x00c4 /* DMA Source Address Status */ ++#define SAFE_DMA_DSTADDR 0x00c8 /* DMA Destination Address Status */ ++#define SAFE_DMA_STAT 0x00cc /* DMA Current Status */ ++#define SAFE_DMA_CFG 0x00d4 /* DMA Configuration/Status */ ++#define SAFE_ENDIAN 0x00e0 /* Endian Configuration */ ++#define SAFE_PK_A_ADDR 0x0800 /* Public Key A Address */ ++#define SAFE_PK_B_ADDR 0x0804 /* Public Key B Address */ ++#define SAFE_PK_C_ADDR 0x0808 /* Public Key C Address */ ++#define SAFE_PK_D_ADDR 0x080c /* Public Key D Address */ ++#define SAFE_PK_A_LEN 0x0810 /* Public Key A Length */ ++#define SAFE_PK_B_LEN 0x0814 /* Public Key B Length */ ++#define SAFE_PK_SHIFT 0x0818 /* Public Key Shift */ ++#define SAFE_PK_FUNC 0x081c /* Public Key Function */ ++#define SAFE_PK_RAM_START 0x1000 /* Public Key RAM start address */ ++#define SAFE_PK_RAM_END 0x1fff /* Public Key RAM end address */ ++ ++#define SAFE_RNG_OUT 0x0100 /* RNG Output */ ++#define SAFE_RNG_STAT 0x0104 /* RNG Status */ ++#define SAFE_RNG_CTRL 0x0108 /* RNG Control */ ++#define SAFE_RNG_A 0x010c /* RNG A */ ++#define SAFE_RNG_B 0x0110 /* RNG B */ ++#define SAFE_RNG_X_LO 0x0114 /* RNG X [31:0] */ ++#define SAFE_RNG_X_MID 0x0118 /* RNG X [63:32] */ ++#define SAFE_RNG_X_HI 0x011c /* RNG X [80:64] */ ++#define SAFE_RNG_X_CNTR 0x0120 /* RNG Counter */ ++#define SAFE_RNG_ALM_CNT 0x0124 /* RNG Alarm Count */ ++#define SAFE_RNG_CNFG 0x0128 /* RNG Configuration */ ++#define SAFE_RNG_LFSR1_LO 0x012c /* RNG LFSR1 [31:0] */ ++#define SAFE_RNG_LFSR1_HI 0x0130 /* RNG LFSR1 [47:32] */ ++#define SAFE_RNG_LFSR2_LO 0x0134 /* RNG LFSR1 [31:0] */ ++#define SAFE_RNG_LFSR2_HI 0x0138 /* RNG LFSR1 [47:32] */ ++ ++#define SAFE_PE_CSR_READY 0x00000001 /* ready for processing */ ++#define SAFE_PE_CSR_DONE 0x00000002 /* h/w completed processing */ ++#define SAFE_PE_CSR_LOADSA 0x00000004 /* load SA digests */ ++#define SAFE_PE_CSR_HASHFINAL 0x00000010 /* do hash pad & write result */ ++#define SAFE_PE_CSR_SABUSID 0x000000c0 /* bus id for SA */ ++#define SAFE_PE_CSR_SAPCI 0x00000040 /* PCI bus id for SA */ ++#define SAFE_PE_CSR_NXTHDR 0x0000ff00 /* next hdr value for IPsec */ ++#define SAFE_PE_CSR_FPAD 0x0000ff00 /* fixed pad for basic ops */ ++#define SAFE_PE_CSR_STATUS 0x00ff0000 /* operation result status */ ++#define SAFE_PE_CSR_AUTH_FAIL 0x00010000 /* ICV mismatch (inbound) */ ++#define SAFE_PE_CSR_PAD_FAIL 0x00020000 /* pad verify fail (inbound) */ ++#define SAFE_PE_CSR_SEQ_FAIL 0x00040000 /* sequence number (inbound) */ ++#define SAFE_PE_CSR_XERROR 0x00080000 /* extended error follows */ ++#define SAFE_PE_CSR_XECODE 0x00f00000 /* extended error code */ ++#define SAFE_PE_CSR_XECODE_S 20 ++#define SAFE_PE_CSR_XECODE_BADCMD 0 /* invalid command */ ++#define SAFE_PE_CSR_XECODE_BADALG 1 /* invalid algorithm */ ++#define SAFE_PE_CSR_XECODE_ALGDIS 2 /* algorithm disabled */ ++#define SAFE_PE_CSR_XECODE_ZEROLEN 3 /* zero packet length */ ++#define SAFE_PE_CSR_XECODE_DMAERR 4 /* bus DMA error */ ++#define SAFE_PE_CSR_XECODE_PIPEABORT 5 /* secondary bus DMA error */ ++#define SAFE_PE_CSR_XECODE_BADSPI 6 /* IPsec SPI mismatch */ ++#define SAFE_PE_CSR_XECODE_TIMEOUT 10 /* failsafe timeout */ ++#define SAFE_PE_CSR_PAD 0xff000000 /* ESP padding control/status */ ++#define SAFE_PE_CSR_PAD_MIN 0x00000000 /* minimum IPsec padding */ ++#define SAFE_PE_CSR_PAD_16 0x08000000 /* pad to 16-byte boundary */ ++#define SAFE_PE_CSR_PAD_32 0x10000000 /* pad to 32-byte boundary */ ++#define SAFE_PE_CSR_PAD_64 0x20000000 /* pad to 64-byte boundary */ ++#define SAFE_PE_CSR_PAD_128 0x40000000 /* pad to 128-byte boundary */ ++#define SAFE_PE_CSR_PAD_256 0x80000000 /* pad to 256-byte boundary */ ++ ++/* ++ * Check the CSR to see if the PE has returned ownership to ++ * the host. Note that before processing a descriptor this ++ * must be done followed by a check of the SAFE_PE_LEN register ++ * status bits to avoid premature processing of a descriptor ++ * on its way back to the host. ++ */ ++#define SAFE_PE_CSR_IS_DONE(_csr) \ ++ (((_csr) & (SAFE_PE_CSR_READY | SAFE_PE_CSR_DONE)) == SAFE_PE_CSR_DONE) ++ ++#define SAFE_PE_LEN_LENGTH 0x000fffff /* total length (bytes) */ ++#define SAFE_PE_LEN_READY 0x00400000 /* ready for processing */ ++#define SAFE_PE_LEN_DONE 0x00800000 /* h/w completed processing */ ++#define SAFE_PE_LEN_BYPASS 0xff000000 /* bypass offset (bytes) */ ++#define SAFE_PE_LEN_BYPASS_S 24 ++ ++#define SAFE_PE_LEN_IS_DONE(_len) \ ++ (((_len) & (SAFE_PE_LEN_READY | SAFE_PE_LEN_DONE)) == SAFE_PE_LEN_DONE) ++ ++/* NB: these apply to HU_STAT, HM_STAT, HI_CLR, and HI_MASK */ ++#define SAFE_INT_PE_CDONE 0x00000002 /* PE context done */ ++#define SAFE_INT_PE_DDONE 0x00000008 /* PE descriptor done */ ++#define SAFE_INT_PE_ERROR 0x00000010 /* PE error */ ++#define SAFE_INT_PE_ODONE 0x00000020 /* PE operation done */ ++ ++#define SAFE_HI_CFG_PULSE 0x00000001 /* use pulse interrupt */ ++#define SAFE_HI_CFG_LEVEL 0x00000000 /* use level interrupt */ ++#define SAFE_HI_CFG_AUTOCLR 0x00000002 /* auto-clear pulse interrupt */ ++ ++#define SAFE_ENDIAN_PASS 0x000000e4 /* straight pass-thru */ ++#define SAFE_ENDIAN_SWAB 0x0000001b /* swap bytes in 32-bit word */ ++ ++#define SAFE_PE_DMACFG_PERESET 0x00000001 /* reset packet engine */ ++#define SAFE_PE_DMACFG_PDRRESET 0x00000002 /* reset PDR counters/ptrs */ ++#define SAFE_PE_DMACFG_SGRESET 0x00000004 /* reset scatter/gather cache */ ++#define SAFE_PE_DMACFG_FSENA 0x00000008 /* enable failsafe reset */ ++#define SAFE_PE_DMACFG_PEMODE 0x00000100 /* packet engine mode */ ++#define SAFE_PE_DMACFG_SAPREC 0x00000200 /* SA precedes packet */ ++#define SAFE_PE_DMACFG_PKFOLL 0x00000400 /* packet follows descriptor */ ++#define SAFE_PE_DMACFG_GPRBID 0x00003000 /* gather particle ring busid */ ++#define SAFE_PE_DMACFG_GPRPCI 0x00001000 /* PCI gather particle ring */ ++#define SAFE_PE_DMACFG_SPRBID 0x0000c000 /* scatter part. ring busid */ ++#define SAFE_PE_DMACFG_SPRPCI 0x00004000 /* PCI scatter part. ring */ ++#define SAFE_PE_DMACFG_ESDESC 0x00010000 /* endian swap descriptors */ ++#define SAFE_PE_DMACFG_ESSA 0x00020000 /* endian swap SA data */ ++#define SAFE_PE_DMACFG_ESPACKET 0x00040000 /* endian swap packet data */ ++#define SAFE_PE_DMACFG_ESPDESC 0x00080000 /* endian swap particle desc. */ ++#define SAFE_PE_DMACFG_NOPDRUP 0x00100000 /* supp. PDR ownership update */ ++#define SAFE_PD_EDMACFG_PCIMODE 0x01000000 /* PCI target mode */ ++ ++#define SAFE_PE_DMASTAT_PEIDONE 0x00000001 /* PE core input done */ ++#define SAFE_PE_DMASTAT_PEODONE 0x00000002 /* PE core output done */ ++#define SAFE_PE_DMASTAT_ENCDONE 0x00000004 /* encryption done */ ++#define SAFE_PE_DMASTAT_IHDONE 0x00000008 /* inner hash done */ ++#define SAFE_PE_DMASTAT_OHDONE 0x00000010 /* outer hash (HMAC) done */ ++#define SAFE_PE_DMASTAT_PADFLT 0x00000020 /* crypto pad fault */ ++#define SAFE_PE_DMASTAT_ICVFLT 0x00000040 /* ICV fault */ ++#define SAFE_PE_DMASTAT_SPIMIS 0x00000080 /* SPI mismatch */ ++#define SAFE_PE_DMASTAT_CRYPTO 0x00000100 /* crypto engine timeout */ ++#define SAFE_PE_DMASTAT_CQACT 0x00000200 /* command queue active */ ++#define SAFE_PE_DMASTAT_IRACT 0x00000400 /* input request active */ ++#define SAFE_PE_DMASTAT_ORACT 0x00000800 /* output request active */ ++#define SAFE_PE_DMASTAT_PEISIZE 0x003ff000 /* PE input size:32-bit words */ ++#define SAFE_PE_DMASTAT_PEOSIZE 0xffc00000 /* PE out. size:32-bit words */ ++ ++#define SAFE_PE_RINGCFG_SIZE 0x000003ff /* ring size (descriptors) */ ++#define SAFE_PE_RINGCFG_OFFSET 0xffff0000 /* offset btw desc's (dwords) */ ++#define SAFE_PE_RINGCFG_OFFSET_S 16 ++ ++#define SAFE_PE_RINGPOLL_POLL 0x00000fff /* polling frequency/divisor */ ++#define SAFE_PE_RINGPOLL_RETRY 0x03ff0000 /* polling frequency/divisor */ ++#define SAFE_PE_RINGPOLL_CONT 0x80000000 /* continuously poll */ ++ ++#define SAFE_PE_IRNGSTAT_CQAVAIL 0x00000001 /* command queue available */ ++ ++#define SAFE_PE_ERNGSTAT_NEXT 0x03ff0000 /* index of next packet desc. */ ++#define SAFE_PE_ERNGSTAT_NEXT_S 16 ++ ++#define SAFE_PE_IOTHRESH_INPUT 0x000003ff /* input threshold (dwords) */ ++#define SAFE_PE_IOTHRESH_OUTPUT 0x03ff0000 /* output threshold (dwords) */ ++ ++#define SAFE_PE_PARTCFG_SIZE 0x0000ffff /* scatter particle size */ ++#define SAFE_PE_PARTCFG_GBURST 0x00030000 /* gather particle burst */ ++#define SAFE_PE_PARTCFG_GBURST_2 0x00000000 ++#define SAFE_PE_PARTCFG_GBURST_4 0x00010000 ++#define SAFE_PE_PARTCFG_GBURST_8 0x00020000 ++#define SAFE_PE_PARTCFG_GBURST_16 0x00030000 ++#define SAFE_PE_PARTCFG_SBURST 0x000c0000 /* scatter particle burst */ ++#define SAFE_PE_PARTCFG_SBURST_2 0x00000000 ++#define SAFE_PE_PARTCFG_SBURST_4 0x00040000 ++#define SAFE_PE_PARTCFG_SBURST_8 0x00080000 ++#define SAFE_PE_PARTCFG_SBURST_16 0x000c0000 ++ ++#define SAFE_PE_PARTSIZE_SCAT 0xffff0000 /* scatter particle ring size */ ++#define SAFE_PE_PARTSIZE_GATH 0x0000ffff /* gather particle ring size */ ++ ++#define SAFE_CRYPTO_CTRL_3DES 0x00000001 /* enable 3DES support */ ++#define SAFE_CRYPTO_CTRL_PKEY 0x00010000 /* enable public key support */ ++#define SAFE_CRYPTO_CTRL_RNG 0x00020000 /* enable RNG support */ ++ ++#define SAFE_DEVINFO_REV_MIN 0x0000000f /* minor rev for chip */ ++#define SAFE_DEVINFO_REV_MAJ 0x000000f0 /* major rev for chip */ ++#define SAFE_DEVINFO_REV_MAJ_S 4 ++#define SAFE_DEVINFO_DES 0x00000100 /* DES/3DES support present */ ++#define SAFE_DEVINFO_ARC4 0x00000200 /* ARC4 support present */ ++#define SAFE_DEVINFO_AES 0x00000400 /* AES support present */ ++#define SAFE_DEVINFO_MD5 0x00001000 /* MD5 support present */ ++#define SAFE_DEVINFO_SHA1 0x00002000 /* SHA-1 support present */ ++#define SAFE_DEVINFO_RIPEMD 0x00004000 /* RIPEMD support present */ ++#define SAFE_DEVINFO_DEFLATE 0x00010000 /* Deflate support present */ ++#define SAFE_DEVINFO_SARAM 0x00100000 /* on-chip SA RAM present */ ++#define SAFE_DEVINFO_EMIBUS 0x00200000 /* EMI bus present */ ++#define SAFE_DEVINFO_PKEY 0x00400000 /* public key support present */ ++#define SAFE_DEVINFO_RNG 0x00800000 /* RNG present */ ++ ++#define SAFE_REV(_maj, _min) (((_maj) << SAFE_DEVINFO_REV_MAJ_S) | (_min)) ++#define SAFE_REV_MAJ(_chiprev) \ ++ (((_chiprev) & SAFE_DEVINFO_REV_MAJ) >> SAFE_DEVINFO_REV_MAJ_S) ++#define SAFE_REV_MIN(_chiprev) ((_chiprev) & SAFE_DEVINFO_REV_MIN) ++ ++#define SAFE_PK_FUNC_MULT 0x00000001 /* Multiply function */ ++#define SAFE_PK_FUNC_SQUARE 0x00000004 /* Square function */ ++#define SAFE_PK_FUNC_ADD 0x00000010 /* Add function */ ++#define SAFE_PK_FUNC_SUB 0x00000020 /* Subtract function */ ++#define SAFE_PK_FUNC_LSHIFT 0x00000040 /* Left-shift function */ ++#define SAFE_PK_FUNC_RSHIFT 0x00000080 /* Right-shift function */ ++#define SAFE_PK_FUNC_DIV 0x00000100 /* Divide function */ ++#define SAFE_PK_FUNC_CMP 0x00000400 /* Compare function */ ++#define SAFE_PK_FUNC_COPY 0x00000800 /* Copy function */ ++#define SAFE_PK_FUNC_EXP16 0x00002000 /* Exponentiate (4-bit ACT) */ ++#define SAFE_PK_FUNC_EXP4 0x00004000 /* Exponentiate (2-bit ACT) */ ++#define SAFE_PK_FUNC_RUN 0x00008000 /* start/status */ ++ ++#define SAFE_RNG_STAT_BUSY 0x00000001 /* busy, data not valid */ ++ ++#define SAFE_RNG_CTRL_PRE_LFSR 0x00000001 /* enable output pre-LFSR */ ++#define SAFE_RNG_CTRL_TST_MODE 0x00000002 /* enable test mode */ ++#define SAFE_RNG_CTRL_TST_RUN 0x00000004 /* start test state machine */ ++#define SAFE_RNG_CTRL_ENA_RING1 0x00000008 /* test entropy oscillator #1 */ ++#define SAFE_RNG_CTRL_ENA_RING2 0x00000010 /* test entropy oscillator #2 */ ++#define SAFE_RNG_CTRL_DIS_ALARM 0x00000020 /* disable RNG alarm reports */ ++#define SAFE_RNG_CTRL_TST_CLOCK 0x00000040 /* enable test clock */ ++#define SAFE_RNG_CTRL_SHORTEN 0x00000080 /* shorten state timers */ ++#define SAFE_RNG_CTRL_TST_ALARM 0x00000100 /* simulate alarm state */ ++#define SAFE_RNG_CTRL_RST_LFSR 0x00000200 /* reset LFSR */ ++ ++/* ++ * Packet engine descriptor. Note that d_csr is a copy of the ++ * SAFE_PE_CSR register and all definitions apply, and d_len ++ * is a copy of the SAFE_PE_LEN register and all definitions apply. ++ * d_src and d_len may point directly to contiguous data or to a ++ * list of ``particle descriptors'' when using scatter/gather i/o. ++ */ ++struct safe_desc { ++ u_int32_t d_csr; /* per-packet control/status */ ++ u_int32_t d_src; /* source address */ ++ u_int32_t d_dst; /* destination address */ ++ u_int32_t d_sa; /* SA address */ ++ u_int32_t d_len; /* length, bypass, status */ ++}; ++ ++/* ++ * Scatter/Gather particle descriptor. ++ * ++ * NB: scatter descriptors do not specify a size; this is fixed ++ * by the setting of the SAFE_PE_PARTCFG register. ++ */ ++struct safe_pdesc { ++ u_int32_t pd_addr; /* particle address */ ++#ifdef __BIG_ENDIAN ++ u_int16_t pd_flags; /* control word */ ++ u_int16_t pd_size; /* particle size (bytes) */ ++#else ++ u_int16_t pd_flags; /* control word */ ++ u_int16_t pd_size; /* particle size (bytes) */ ++#endif ++}; ++ ++#define SAFE_PD_READY 0x0001 /* ready for processing */ ++#define SAFE_PD_DONE 0x0002 /* h/w completed processing */ ++ ++/* ++ * Security Association (SA) Record (Rev 1). One of these is ++ * required for each operation processed by the packet engine. ++ */ ++struct safe_sarec { ++ u_int32_t sa_cmd0; ++ u_int32_t sa_cmd1; ++ u_int32_t sa_resv0; ++ u_int32_t sa_resv1; ++ u_int32_t sa_key[8]; /* DES/3DES/AES key */ ++ u_int32_t sa_indigest[5]; /* inner digest */ ++ u_int32_t sa_outdigest[5]; /* outer digest */ ++ u_int32_t sa_spi; /* SPI */ ++ u_int32_t sa_seqnum; /* sequence number */ ++ u_int32_t sa_seqmask[2]; /* sequence number mask */ ++ u_int32_t sa_resv2; ++ u_int32_t sa_staterec; /* address of state record */ ++ u_int32_t sa_resv3[2]; ++ u_int32_t sa_samgmt0; /* SA management field 0 */ ++ u_int32_t sa_samgmt1; /* SA management field 0 */ ++}; ++ ++#define SAFE_SA_CMD0_OP 0x00000007 /* operation code */ ++#define SAFE_SA_CMD0_OP_CRYPT 0x00000000 /* encrypt/decrypt (basic) */ ++#define SAFE_SA_CMD0_OP_BOTH 0x00000001 /* encrypt-hash/hash-decrypto */ ++#define SAFE_SA_CMD0_OP_HASH 0x00000003 /* hash (outbound-only) */ ++#define SAFE_SA_CMD0_OP_ESP 0x00000000 /* ESP in/out (proto) */ ++#define SAFE_SA_CMD0_OP_AH 0x00000001 /* AH in/out (proto) */ ++#define SAFE_SA_CMD0_INBOUND 0x00000008 /* inbound operation */ ++#define SAFE_SA_CMD0_OUTBOUND 0x00000000 /* outbound operation */ ++#define SAFE_SA_CMD0_GROUP 0x00000030 /* operation group */ ++#define SAFE_SA_CMD0_BASIC 0x00000000 /* basic operation */ ++#define SAFE_SA_CMD0_PROTO 0x00000010 /* protocol/packet operation */ ++#define SAFE_SA_CMD0_BUNDLE 0x00000020 /* bundled operation (resvd) */ ++#define SAFE_SA_CMD0_PAD 0x000000c0 /* crypto pad method */ ++#define SAFE_SA_CMD0_PAD_IPSEC 0x00000000 /* IPsec padding */ ++#define SAFE_SA_CMD0_PAD_PKCS7 0x00000040 /* PKCS#7 padding */ ++#define SAFE_SA_CMD0_PAD_CONS 0x00000080 /* constant padding */ ++#define SAFE_SA_CMD0_PAD_ZERO 0x000000c0 /* zero padding */ ++#define SAFE_SA_CMD0_CRYPT_ALG 0x00000f00 /* symmetric crypto algorithm */ ++#define SAFE_SA_CMD0_DES 0x00000000 /* DES crypto algorithm */ ++#define SAFE_SA_CMD0_3DES 0x00000100 /* 3DES crypto algorithm */ ++#define SAFE_SA_CMD0_AES 0x00000300 /* AES crypto algorithm */ ++#define SAFE_SA_CMD0_CRYPT_NULL 0x00000f00 /* null crypto algorithm */ ++#define SAFE_SA_CMD0_HASH_ALG 0x0000f000 /* hash algorithm */ ++#define SAFE_SA_CMD0_MD5 0x00000000 /* MD5 hash algorithm */ ++#define SAFE_SA_CMD0_SHA1 0x00001000 /* SHA-1 hash algorithm */ ++#define SAFE_SA_CMD0_HASH_NULL 0x0000f000 /* null hash algorithm */ ++#define SAFE_SA_CMD0_HDR_PROC 0x00080000 /* header processing */ ++#define SAFE_SA_CMD0_IBUSID 0x00300000 /* input bus id */ ++#define SAFE_SA_CMD0_IPCI 0x00100000 /* PCI input bus id */ ++#define SAFE_SA_CMD0_OBUSID 0x00c00000 /* output bus id */ ++#define SAFE_SA_CMD0_OPCI 0x00400000 /* PCI output bus id */ ++#define SAFE_SA_CMD0_IVLD 0x03000000 /* IV loading */ ++#define SAFE_SA_CMD0_IVLD_NONE 0x00000000 /* IV no load (reuse) */ ++#define SAFE_SA_CMD0_IVLD_IBUF 0x01000000 /* IV load from input buffer */ ++#define SAFE_SA_CMD0_IVLD_STATE 0x02000000 /* IV load from state */ ++#define SAFE_SA_CMD0_HSLD 0x0c000000 /* hash state loading */ ++#define SAFE_SA_CMD0_HSLD_SA 0x00000000 /* hash state load from SA */ ++#define SAFE_SA_CMD0_HSLD_STATE 0x08000000 /* hash state load from state */ ++#define SAFE_SA_CMD0_HSLD_NONE 0x0c000000 /* hash state no load */ ++#define SAFE_SA_CMD0_SAVEIV 0x10000000 /* save IV */ ++#define SAFE_SA_CMD0_SAVEHASH 0x20000000 /* save hash state */ ++#define SAFE_SA_CMD0_IGATHER 0x40000000 /* input gather */ ++#define SAFE_SA_CMD0_OSCATTER 0x80000000 /* output scatter */ ++ ++#define SAFE_SA_CMD1_HDRCOPY 0x00000002 /* copy header to output */ ++#define SAFE_SA_CMD1_PAYCOPY 0x00000004 /* copy payload to output */ ++#define SAFE_SA_CMD1_PADCOPY 0x00000008 /* copy pad to output */ ++#define SAFE_SA_CMD1_IPV4 0x00000000 /* IPv4 protocol */ ++#define SAFE_SA_CMD1_IPV6 0x00000010 /* IPv6 protocol */ ++#define SAFE_SA_CMD1_MUTABLE 0x00000020 /* mutable bit processing */ ++#define SAFE_SA_CMD1_SRBUSID 0x000000c0 /* state record bus id */ ++#define SAFE_SA_CMD1_SRPCI 0x00000040 /* state record from PCI */ ++#define SAFE_SA_CMD1_CRMODE 0x00000300 /* crypto mode */ ++#define SAFE_SA_CMD1_ECB 0x00000000 /* ECB crypto mode */ ++#define SAFE_SA_CMD1_CBC 0x00000100 /* CBC crypto mode */ ++#define SAFE_SA_CMD1_OFB 0x00000200 /* OFB crypto mode */ ++#define SAFE_SA_CMD1_CFB 0x00000300 /* CFB crypto mode */ ++#define SAFE_SA_CMD1_CRFEEDBACK 0x00000c00 /* crypto feedback mode */ ++#define SAFE_SA_CMD1_64BIT 0x00000000 /* 64-bit crypto feedback */ ++#define SAFE_SA_CMD1_8BIT 0x00000400 /* 8-bit crypto feedback */ ++#define SAFE_SA_CMD1_1BIT 0x00000800 /* 1-bit crypto feedback */ ++#define SAFE_SA_CMD1_128BIT 0x00000c00 /* 128-bit crypto feedback */ ++#define SAFE_SA_CMD1_OPTIONS 0x00001000 /* HMAC/options mutable bit */ ++#define SAFE_SA_CMD1_HMAC SAFE_SA_CMD1_OPTIONS ++#define SAFE_SA_CMD1_SAREV1 0x00008000 /* SA Revision 1 */ ++#define SAFE_SA_CMD1_OFFSET 0x00ff0000 /* hash/crypto offset(dwords) */ ++#define SAFE_SA_CMD1_OFFSET_S 16 ++#define SAFE_SA_CMD1_AESKEYLEN 0x0f000000 /* AES key length */ ++#define SAFE_SA_CMD1_AES128 0x02000000 /* 128-bit AES key */ ++#define SAFE_SA_CMD1_AES192 0x03000000 /* 192-bit AES key */ ++#define SAFE_SA_CMD1_AES256 0x04000000 /* 256-bit AES key */ ++ ++/* ++ * Security Associate State Record (Rev 1). ++ */ ++struct safe_sastate { ++ u_int32_t sa_saved_iv[4]; /* saved IV (DES/3DES/AES) */ ++ u_int32_t sa_saved_hashbc; /* saved hash byte count */ ++ u_int32_t sa_saved_indigest[5]; /* saved inner digest */ ++}; ++#endif /* _SAFE_SAFEREG_H_ */ +diff -Nur linux-3.0.4.orig/crypto/ocf/safe/safevar.h linux-3.0.4/crypto/ocf/safe/safevar.h +--- linux-3.0.4.orig/crypto/ocf/safe/safevar.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/safe/safevar.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,229 @@ ++/*- ++ * The linux port of this code done by David McCullough ++ * Copyright (C) 2004-2010 David McCullough ++ * The license and original author are listed below. ++ * ++ * Copyright (c) 2003 Sam Leffler, Errno Consulting ++ * Copyright (c) 2003 Global Technology Associates, Inc. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE ++ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ++ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ++ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF ++ * SUCH DAMAGE. ++ * ++ * $FreeBSD: src/sys/dev/safe/safevar.h,v 1.2 2006/05/17 18:34:26 pjd Exp $ ++ */ ++#ifndef _SAFE_SAFEVAR_H_ ++#define _SAFE_SAFEVAR_H_ ++ ++/* Maximum queue length */ ++#ifndef SAFE_MAX_NQUEUE ++#define SAFE_MAX_NQUEUE 60 ++#endif ++ ++#define SAFE_MAX_PART 64 /* Maximum scatter/gather depth */ ++#define SAFE_DMA_BOUNDARY 0 /* No boundary for source DMA ops */ ++#define SAFE_MAX_DSIZE 2048 /* MCLBYTES Fixed scatter particle size */ ++#define SAFE_MAX_SSIZE 0x0ffff /* Maximum gather particle size */ ++#define SAFE_MAX_DMA 0xfffff /* Maximum PE operand size (20 bits) */ ++/* total src+dst particle descriptors */ ++#define SAFE_TOTAL_DPART (SAFE_MAX_NQUEUE * SAFE_MAX_PART) ++#define SAFE_TOTAL_SPART (SAFE_MAX_NQUEUE * SAFE_MAX_PART) ++ ++#define SAFE_RNG_MAXBUFSIZ 128 /* 32-bit words */ ++ ++#define SAFE_CARD(sid) (((sid) & 0xf0000000) >> 28) ++#define SAFE_SESSION(sid) ( (sid) & 0x0fffffff) ++#define SAFE_SID(crd, sesn) (((crd) << 28) | ((sesn) & 0x0fffffff)) ++ ++#define SAFE_DEF_RTY 0xff /* PCI Retry Timeout */ ++#define SAFE_DEF_TOUT 0xff /* PCI TRDY Timeout */ ++#define SAFE_DEF_CACHELINE 0x01 /* Cache Line setting */ ++ ++#ifdef __KERNEL__ ++/* ++ * State associated with the allocation of each chunk ++ * of memory setup for DMA. ++ */ ++struct safe_dma_alloc { ++ dma_addr_t dma_paddr; ++ void *dma_vaddr; ++}; ++ ++/* ++ * Cryptographic operand state. One of these exists for each ++ * source and destination operand passed in from the crypto ++ * subsystem. When possible source and destination operands ++ * refer to the same memory. More often they are distinct. ++ * We track the virtual address of each operand as well as ++ * where each is mapped for DMA. ++ */ ++struct safe_operand { ++ union { ++ struct sk_buff *skb; ++ struct uio *io; ++ } u; ++ void *map; ++ int mapsize; /* total number of bytes in segs */ ++ struct { ++ dma_addr_t ds_addr; ++ int ds_len; ++ int ds_tlen; ++ } segs[SAFE_MAX_PART]; ++ int nsegs; ++}; ++ ++/* ++ * Packet engine ring entry and cryptographic operation state. ++ * The packet engine requires a ring of descriptors that contain ++ * pointers to various cryptographic state. However the ring ++ * configuration register allows you to specify an arbitrary size ++ * for ring entries. We use this feature to collect most of the ++ * state for each cryptographic request into one spot. Other than ++ * ring entries only the ``particle descriptors'' (scatter/gather ++ * lists) and the actual operand data are kept separate. The ++ * particle descriptors must also be organized in rings. The ++ * operand data can be located aribtrarily (modulo alignment constraints). ++ * ++ * Note that the descriptor ring is mapped onto the PCI bus so ++ * the hardware can DMA data. This means the entire ring must be ++ * contiguous. ++ */ ++struct safe_ringentry { ++ struct safe_desc re_desc; /* command descriptor */ ++ struct safe_sarec re_sa; /* SA record */ ++ struct safe_sastate re_sastate; /* SA state record */ ++ ++ struct cryptop *re_crp; /* crypto operation */ ++ ++ struct safe_operand re_src; /* source operand */ ++ struct safe_operand re_dst; /* destination operand */ ++ ++ int re_sesn; /* crypto session ID */ ++ int re_flags; ++#define SAFE_QFLAGS_COPYOUTIV 0x1 /* copy back on completion */ ++#define SAFE_QFLAGS_COPYOUTICV 0x2 /* copy back on completion */ ++}; ++ ++#define re_src_skb re_src.u.skb ++#define re_src_io re_src.u.io ++#define re_src_map re_src.map ++#define re_src_nsegs re_src.nsegs ++#define re_src_segs re_src.segs ++#define re_src_mapsize re_src.mapsize ++ ++#define re_dst_skb re_dst.u.skb ++#define re_dst_io re_dst.u.io ++#define re_dst_map re_dst.map ++#define re_dst_nsegs re_dst.nsegs ++#define re_dst_segs re_dst.segs ++#define re_dst_mapsize re_dst.mapsize ++ ++struct rndstate_test; ++ ++struct safe_session { ++ u_int32_t ses_used; ++ u_int32_t ses_klen; /* key length in bits */ ++ u_int32_t ses_key[8]; /* DES/3DES/AES key */ ++ u_int32_t ses_mlen; /* hmac length in bytes */ ++ u_int32_t ses_hminner[5]; /* hmac inner state */ ++ u_int32_t ses_hmouter[5]; /* hmac outer state */ ++}; ++ ++struct safe_pkq { ++ struct list_head pkq_list; ++ struct cryptkop *pkq_krp; ++}; ++ ++struct safe_softc { ++ softc_device_decl sc_dev; ++ u32 sc_irq; ++ ++ struct pci_dev *sc_pcidev; ++ ocf_iomem_t sc_base_addr; ++ ++ u_int sc_chiprev; /* major/minor chip revision */ ++ int sc_flags; /* device specific flags */ ++#define SAFE_FLAGS_KEY 0x01 /* has key accelerator */ ++#define SAFE_FLAGS_RNG 0x02 /* hardware rng */ ++ int sc_suspended; ++ int sc_needwakeup; /* notify crypto layer */ ++ int32_t sc_cid; /* crypto tag */ ++ ++ struct safe_dma_alloc sc_ringalloc; /* PE ring allocation state */ ++ struct safe_ringentry *sc_ring; /* PE ring */ ++ struct safe_ringentry *sc_ringtop; /* PE ring top */ ++ struct safe_ringentry *sc_front; /* next free entry */ ++ struct safe_ringentry *sc_back; /* next pending entry */ ++ int sc_nqchip; /* # passed to chip */ ++ spinlock_t sc_ringmtx; /* PE ring lock */ ++ struct safe_pdesc *sc_spring; /* src particle ring */ ++ struct safe_pdesc *sc_springtop; /* src particle ring top */ ++ struct safe_pdesc *sc_spfree; /* next free src particle */ ++ struct safe_dma_alloc sc_spalloc; /* src particle ring state */ ++ struct safe_pdesc *sc_dpring; /* dest particle ring */ ++ struct safe_pdesc *sc_dpringtop; /* dest particle ring top */ ++ struct safe_pdesc *sc_dpfree; /* next free dest particle */ ++ struct safe_dma_alloc sc_dpalloc; /* dst particle ring state */ ++ int sc_nsessions; /* # of sessions */ ++ struct safe_session *sc_sessions; /* sessions */ ++ ++ struct timer_list sc_pkto; /* PK polling */ ++ spinlock_t sc_pkmtx; /* PK lock */ ++ struct list_head sc_pkq; /* queue of PK requests */ ++ struct safe_pkq *sc_pkq_cur; /* current processing request */ ++ u_int32_t sc_pk_reslen, sc_pk_resoff; ++ ++ int sc_max_dsize; /* maximum safe DMA size */ ++}; ++#endif /* __KERNEL__ */ ++ ++struct safe_stats { ++ u_int64_t st_ibytes; ++ u_int64_t st_obytes; ++ u_int32_t st_ipackets; ++ u_int32_t st_opackets; ++ u_int32_t st_invalid; /* invalid argument */ ++ u_int32_t st_badsession; /* invalid session id */ ++ u_int32_t st_badflags; /* flags indicate !(mbuf | uio) */ ++ u_int32_t st_nodesc; /* op submitted w/o descriptors */ ++ u_int32_t st_badalg; /* unsupported algorithm */ ++ u_int32_t st_ringfull; /* PE descriptor ring full */ ++ u_int32_t st_peoperr; /* PE marked error */ ++ u_int32_t st_dmaerr; /* PE DMA error */ ++ u_int32_t st_bypasstoobig; /* bypass > 96 bytes */ ++ u_int32_t st_skipmismatch; /* enc part begins before auth part */ ++ u_int32_t st_lenmismatch; /* enc length different auth length */ ++ u_int32_t st_coffmisaligned; /* crypto offset not 32-bit aligned */ ++ u_int32_t st_cofftoobig; /* crypto offset > 255 words */ ++ u_int32_t st_iovmisaligned; /* iov op not aligned */ ++ u_int32_t st_iovnotuniform; /* iov op not suitable */ ++ u_int32_t st_unaligned; /* unaligned src caused copy */ ++ u_int32_t st_notuniform; /* non-uniform src caused copy */ ++ u_int32_t st_nomap; /* bus_dmamap_create failed */ ++ u_int32_t st_noload; /* bus_dmamap_load_* failed */ ++ u_int32_t st_nombuf; /* MGET* failed */ ++ u_int32_t st_nomcl; /* MCLGET* failed */ ++ u_int32_t st_maxqchip; /* max mcr1 ops out for processing */ ++ u_int32_t st_rng; /* RNG requests */ ++ u_int32_t st_rngalarm; /* RNG alarm requests */ ++ u_int32_t st_noicvcopy; /* ICV data copies suppressed */ ++}; ++#endif /* _SAFE_SAFEVAR_H_ */ +diff -Nur linux-3.0.4.orig/crypto/ocf/safe/sha1.c linux-3.0.4/crypto/ocf/safe/sha1.c +--- linux-3.0.4.orig/crypto/ocf/safe/sha1.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/safe/sha1.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,279 @@ ++/* $KAME: sha1.c,v 1.5 2000/11/08 06:13:08 itojun Exp $ */ ++/* ++ * Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. Neither the name of the project nor the names of its contributors ++ * may be used to endorse or promote products derived from this software ++ * without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND ++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE ++ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ++ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ++ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF ++ * SUCH DAMAGE. ++ */ ++ ++/* ++ * FIPS pub 180-1: Secure Hash Algorithm (SHA-1) ++ * based on: http://csrc.nist.gov/fips/fip180-1.txt ++ * implemented by Jun-ichiro itojun Itoh ++ */ ++ ++#if 0 ++#include ++__FBSDID("$FreeBSD: src/sys/crypto/sha1.c,v 1.9 2003/06/10 21:36:57 obrien Exp $"); ++ ++#include ++#include ++#include ++#include ++ ++#include ++#endif ++ ++/* sanity check */ ++#if BYTE_ORDER != BIG_ENDIAN ++# if BYTE_ORDER != LITTLE_ENDIAN ++# define unsupported 1 ++# endif ++#endif ++ ++#ifndef unsupported ++ ++/* constant table */ ++static u_int32_t _K[] = { 0x5a827999, 0x6ed9eba1, 0x8f1bbcdc, 0xca62c1d6 }; ++#define K(t) _K[(t) / 20] ++ ++#define F0(b, c, d) (((b) & (c)) | ((~(b)) & (d))) ++#define F1(b, c, d) (((b) ^ (c)) ^ (d)) ++#define F2(b, c, d) (((b) & (c)) | ((b) & (d)) | ((c) & (d))) ++#define F3(b, c, d) (((b) ^ (c)) ^ (d)) ++ ++#define S(n, x) (((x) << (n)) | ((x) >> (32 - n))) ++ ++#undef H ++#define H(n) (ctxt->h.b32[(n)]) ++#define COUNT (ctxt->count) ++#define BCOUNT (ctxt->c.b64[0] / 8) ++#define W(n) (ctxt->m.b32[(n)]) ++ ++#define PUTBYTE(x) { \ ++ ctxt->m.b8[(COUNT % 64)] = (x); \ ++ COUNT++; \ ++ COUNT %= 64; \ ++ ctxt->c.b64[0] += 8; \ ++ if (COUNT % 64 == 0) \ ++ sha1_step(ctxt); \ ++ } ++ ++#define PUTPAD(x) { \ ++ ctxt->m.b8[(COUNT % 64)] = (x); \ ++ COUNT++; \ ++ COUNT %= 64; \ ++ if (COUNT % 64 == 0) \ ++ sha1_step(ctxt); \ ++ } ++ ++static void sha1_step(struct sha1_ctxt *); ++ ++static void ++sha1_step(ctxt) ++ struct sha1_ctxt *ctxt; ++{ ++ u_int32_t a, b, c, d, e; ++ size_t t, s; ++ u_int32_t tmp; ++ ++#if BYTE_ORDER == LITTLE_ENDIAN ++ struct sha1_ctxt tctxt; ++ bcopy(&ctxt->m.b8[0], &tctxt.m.b8[0], 64); ++ ctxt->m.b8[0] = tctxt.m.b8[3]; ctxt->m.b8[1] = tctxt.m.b8[2]; ++ ctxt->m.b8[2] = tctxt.m.b8[1]; ctxt->m.b8[3] = tctxt.m.b8[0]; ++ ctxt->m.b8[4] = tctxt.m.b8[7]; ctxt->m.b8[5] = tctxt.m.b8[6]; ++ ctxt->m.b8[6] = tctxt.m.b8[5]; ctxt->m.b8[7] = tctxt.m.b8[4]; ++ ctxt->m.b8[8] = tctxt.m.b8[11]; ctxt->m.b8[9] = tctxt.m.b8[10]; ++ ctxt->m.b8[10] = tctxt.m.b8[9]; ctxt->m.b8[11] = tctxt.m.b8[8]; ++ ctxt->m.b8[12] = tctxt.m.b8[15]; ctxt->m.b8[13] = tctxt.m.b8[14]; ++ ctxt->m.b8[14] = tctxt.m.b8[13]; ctxt->m.b8[15] = tctxt.m.b8[12]; ++ ctxt->m.b8[16] = tctxt.m.b8[19]; ctxt->m.b8[17] = tctxt.m.b8[18]; ++ ctxt->m.b8[18] = tctxt.m.b8[17]; ctxt->m.b8[19] = tctxt.m.b8[16]; ++ ctxt->m.b8[20] = tctxt.m.b8[23]; ctxt->m.b8[21] = tctxt.m.b8[22]; ++ ctxt->m.b8[22] = tctxt.m.b8[21]; ctxt->m.b8[23] = tctxt.m.b8[20]; ++ ctxt->m.b8[24] = tctxt.m.b8[27]; ctxt->m.b8[25] = tctxt.m.b8[26]; ++ ctxt->m.b8[26] = tctxt.m.b8[25]; ctxt->m.b8[27] = tctxt.m.b8[24]; ++ ctxt->m.b8[28] = tctxt.m.b8[31]; ctxt->m.b8[29] = tctxt.m.b8[30]; ++ ctxt->m.b8[30] = tctxt.m.b8[29]; ctxt->m.b8[31] = tctxt.m.b8[28]; ++ ctxt->m.b8[32] = tctxt.m.b8[35]; ctxt->m.b8[33] = tctxt.m.b8[34]; ++ ctxt->m.b8[34] = tctxt.m.b8[33]; ctxt->m.b8[35] = tctxt.m.b8[32]; ++ ctxt->m.b8[36] = tctxt.m.b8[39]; ctxt->m.b8[37] = tctxt.m.b8[38]; ++ ctxt->m.b8[38] = tctxt.m.b8[37]; ctxt->m.b8[39] = tctxt.m.b8[36]; ++ ctxt->m.b8[40] = tctxt.m.b8[43]; ctxt->m.b8[41] = tctxt.m.b8[42]; ++ ctxt->m.b8[42] = tctxt.m.b8[41]; ctxt->m.b8[43] = tctxt.m.b8[40]; ++ ctxt->m.b8[44] = tctxt.m.b8[47]; ctxt->m.b8[45] = tctxt.m.b8[46]; ++ ctxt->m.b8[46] = tctxt.m.b8[45]; ctxt->m.b8[47] = tctxt.m.b8[44]; ++ ctxt->m.b8[48] = tctxt.m.b8[51]; ctxt->m.b8[49] = tctxt.m.b8[50]; ++ ctxt->m.b8[50] = tctxt.m.b8[49]; ctxt->m.b8[51] = tctxt.m.b8[48]; ++ ctxt->m.b8[52] = tctxt.m.b8[55]; ctxt->m.b8[53] = tctxt.m.b8[54]; ++ ctxt->m.b8[54] = tctxt.m.b8[53]; ctxt->m.b8[55] = tctxt.m.b8[52]; ++ ctxt->m.b8[56] = tctxt.m.b8[59]; ctxt->m.b8[57] = tctxt.m.b8[58]; ++ ctxt->m.b8[58] = tctxt.m.b8[57]; ctxt->m.b8[59] = tctxt.m.b8[56]; ++ ctxt->m.b8[60] = tctxt.m.b8[63]; ctxt->m.b8[61] = tctxt.m.b8[62]; ++ ctxt->m.b8[62] = tctxt.m.b8[61]; ctxt->m.b8[63] = tctxt.m.b8[60]; ++#endif ++ ++ a = H(0); b = H(1); c = H(2); d = H(3); e = H(4); ++ ++ for (t = 0; t < 20; t++) { ++ s = t & 0x0f; ++ if (t >= 16) { ++ W(s) = S(1, W((s+13) & 0x0f) ^ W((s+8) & 0x0f) ^ W((s+2) & 0x0f) ^ W(s)); ++ } ++ tmp = S(5, a) + F0(b, c, d) + e + W(s) + K(t); ++ e = d; d = c; c = S(30, b); b = a; a = tmp; ++ } ++ for (t = 20; t < 40; t++) { ++ s = t & 0x0f; ++ W(s) = S(1, W((s+13) & 0x0f) ^ W((s+8) & 0x0f) ^ W((s+2) & 0x0f) ^ W(s)); ++ tmp = S(5, a) + F1(b, c, d) + e + W(s) + K(t); ++ e = d; d = c; c = S(30, b); b = a; a = tmp; ++ } ++ for (t = 40; t < 60; t++) { ++ s = t & 0x0f; ++ W(s) = S(1, W((s+13) & 0x0f) ^ W((s+8) & 0x0f) ^ W((s+2) & 0x0f) ^ W(s)); ++ tmp = S(5, a) + F2(b, c, d) + e + W(s) + K(t); ++ e = d; d = c; c = S(30, b); b = a; a = tmp; ++ } ++ for (t = 60; t < 80; t++) { ++ s = t & 0x0f; ++ W(s) = S(1, W((s+13) & 0x0f) ^ W((s+8) & 0x0f) ^ W((s+2) & 0x0f) ^ W(s)); ++ tmp = S(5, a) + F3(b, c, d) + e + W(s) + K(t); ++ e = d; d = c; c = S(30, b); b = a; a = tmp; ++ } ++ ++ H(0) = H(0) + a; ++ H(1) = H(1) + b; ++ H(2) = H(2) + c; ++ H(3) = H(3) + d; ++ H(4) = H(4) + e; ++ ++ bzero(&ctxt->m.b8[0], 64); ++} ++ ++/*------------------------------------------------------------*/ ++ ++void ++sha1_init(ctxt) ++ struct sha1_ctxt *ctxt; ++{ ++ bzero(ctxt, sizeof(struct sha1_ctxt)); ++ H(0) = 0x67452301; ++ H(1) = 0xefcdab89; ++ H(2) = 0x98badcfe; ++ H(3) = 0x10325476; ++ H(4) = 0xc3d2e1f0; ++} ++ ++void ++sha1_pad(ctxt) ++ struct sha1_ctxt *ctxt; ++{ ++ size_t padlen; /*pad length in bytes*/ ++ size_t padstart; ++ ++ PUTPAD(0x80); ++ ++ padstart = COUNT % 64; ++ padlen = 64 - padstart; ++ if (padlen < 8) { ++ bzero(&ctxt->m.b8[padstart], padlen); ++ COUNT += padlen; ++ COUNT %= 64; ++ sha1_step(ctxt); ++ padstart = COUNT % 64; /* should be 0 */ ++ padlen = 64 - padstart; /* should be 64 */ ++ } ++ bzero(&ctxt->m.b8[padstart], padlen - 8); ++ COUNT += (padlen - 8); ++ COUNT %= 64; ++#if BYTE_ORDER == BIG_ENDIAN ++ PUTPAD(ctxt->c.b8[0]); PUTPAD(ctxt->c.b8[1]); ++ PUTPAD(ctxt->c.b8[2]); PUTPAD(ctxt->c.b8[3]); ++ PUTPAD(ctxt->c.b8[4]); PUTPAD(ctxt->c.b8[5]); ++ PUTPAD(ctxt->c.b8[6]); PUTPAD(ctxt->c.b8[7]); ++#else ++ PUTPAD(ctxt->c.b8[7]); PUTPAD(ctxt->c.b8[6]); ++ PUTPAD(ctxt->c.b8[5]); PUTPAD(ctxt->c.b8[4]); ++ PUTPAD(ctxt->c.b8[3]); PUTPAD(ctxt->c.b8[2]); ++ PUTPAD(ctxt->c.b8[1]); PUTPAD(ctxt->c.b8[0]); ++#endif ++} ++ ++void ++sha1_loop(ctxt, input, len) ++ struct sha1_ctxt *ctxt; ++ const u_int8_t *input; ++ size_t len; ++{ ++ size_t gaplen; ++ size_t gapstart; ++ size_t off; ++ size_t copysiz; ++ ++ off = 0; ++ ++ while (off < len) { ++ gapstart = COUNT % 64; ++ gaplen = 64 - gapstart; ++ ++ copysiz = (gaplen < len - off) ? gaplen : len - off; ++ bcopy(&input[off], &ctxt->m.b8[gapstart], copysiz); ++ COUNT += copysiz; ++ COUNT %= 64; ++ ctxt->c.b64[0] += copysiz * 8; ++ if (COUNT % 64 == 0) ++ sha1_step(ctxt); ++ off += copysiz; ++ } ++} ++ ++void ++sha1_result(ctxt, digest0) ++ struct sha1_ctxt *ctxt; ++ caddr_t digest0; ++{ ++ u_int8_t *digest; ++ ++ digest = (u_int8_t *)digest0; ++ sha1_pad(ctxt); ++#if BYTE_ORDER == BIG_ENDIAN ++ bcopy(&ctxt->h.b8[0], digest, 20); ++#else ++ digest[0] = ctxt->h.b8[3]; digest[1] = ctxt->h.b8[2]; ++ digest[2] = ctxt->h.b8[1]; digest[3] = ctxt->h.b8[0]; ++ digest[4] = ctxt->h.b8[7]; digest[5] = ctxt->h.b8[6]; ++ digest[6] = ctxt->h.b8[5]; digest[7] = ctxt->h.b8[4]; ++ digest[8] = ctxt->h.b8[11]; digest[9] = ctxt->h.b8[10]; ++ digest[10] = ctxt->h.b8[9]; digest[11] = ctxt->h.b8[8]; ++ digest[12] = ctxt->h.b8[15]; digest[13] = ctxt->h.b8[14]; ++ digest[14] = ctxt->h.b8[13]; digest[15] = ctxt->h.b8[12]; ++ digest[16] = ctxt->h.b8[19]; digest[17] = ctxt->h.b8[18]; ++ digest[18] = ctxt->h.b8[17]; digest[19] = ctxt->h.b8[16]; ++#endif ++} ++ ++#endif /*unsupported*/ +diff -Nur linux-3.0.4.orig/crypto/ocf/safe/sha1.h linux-3.0.4/crypto/ocf/safe/sha1.h +--- linux-3.0.4.orig/crypto/ocf/safe/sha1.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/safe/sha1.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,72 @@ ++/* $FreeBSD: src/sys/crypto/sha1.h,v 1.8 2002/03/20 05:13:50 alfred Exp $ */ ++/* $KAME: sha1.h,v 1.5 2000/03/27 04:36:23 sumikawa Exp $ */ ++ ++/* ++ * Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. Neither the name of the project nor the names of its contributors ++ * may be used to endorse or promote products derived from this software ++ * without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND ++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE ++ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ++ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ++ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF ++ * SUCH DAMAGE. ++ */ ++/* ++ * FIPS pub 180-1: Secure Hash Algorithm (SHA-1) ++ * based on: http://csrc.nist.gov/fips/fip180-1.txt ++ * implemented by Jun-ichiro itojun Itoh ++ */ ++ ++#ifndef _NETINET6_SHA1_H_ ++#define _NETINET6_SHA1_H_ ++ ++struct sha1_ctxt { ++ union { ++ u_int8_t b8[20]; ++ u_int32_t b32[5]; ++ } h; ++ union { ++ u_int8_t b8[8]; ++ u_int64_t b64[1]; ++ } c; ++ union { ++ u_int8_t b8[64]; ++ u_int32_t b32[16]; ++ } m; ++ u_int8_t count; ++}; ++ ++#ifdef __KERNEL__ ++extern void sha1_init(struct sha1_ctxt *); ++extern void sha1_pad(struct sha1_ctxt *); ++extern void sha1_loop(struct sha1_ctxt *, const u_int8_t *, size_t); ++extern void sha1_result(struct sha1_ctxt *, caddr_t); ++ ++/* compatibilty with other SHA1 source codes */ ++typedef struct sha1_ctxt SHA1_CTX; ++#define SHA1Init(x) sha1_init((x)) ++#define SHA1Update(x, y, z) sha1_loop((x), (y), (z)) ++#define SHA1Final(x, y) sha1_result((y), (x)) ++#endif /* __KERNEL__ */ ++ ++#define SHA1_RESULTLEN (160/8) ++ ++#endif /*_NETINET6_SHA1_H_*/ +diff -Nur linux-3.0.4.orig/crypto/ocf/talitos/Makefile linux-3.0.4/crypto/ocf/talitos/Makefile +--- linux-3.0.4.orig/crypto/ocf/talitos/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/talitos/Makefile 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,12 @@ ++# for SGlinux builds ++-include $(ROOTDIR)/modules/.config ++ ++obj-$(CONFIG_OCF_TALITOS) += talitos.o ++ ++obj ?= . ++EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ ++ ++ifdef TOPDIR ++-include $(TOPDIR)/Rules.make ++endif ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/talitos/talitos.c linux-3.0.4/crypto/ocf/talitos/talitos.c +--- linux-3.0.4.orig/crypto/ocf/talitos/talitos.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/talitos/talitos.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,1355 @@ ++/* ++ * crypto/ocf/talitos/talitos.c ++ * ++ * An OCF-Linux module that uses Freescale's SEC to do the crypto. ++ * Based on crypto/ocf/hifn and crypto/ocf/safe OCF drivers ++ * ++ * Copyright (c) 2006 Freescale Semiconductor, Inc. ++ * ++ * This code written by Kim A. B. Phillips ++ * some code copied from files with the following: ++ * Copyright (C) 2004-2007 David McCullough ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * --------------------------------------------------------------------------- ++ * ++ * NOTES: ++ * ++ * The Freescale SEC (also known as 'talitos') resides on the ++ * internal bus, and runs asynchronous to the processor core. It has ++ * a wide gamut of cryptographic acceleration features, including single- ++ * pass IPsec (also known as algorithm chaining). To properly utilize ++ * all of the SEC's performance enhancing features, further reworking ++ * of higher level code (framework, applications) will be necessary. ++ * ++ * The following table shows which SEC version is present in which devices: ++ * ++ * Devices SEC version ++ * ++ * 8272, 8248 SEC 1.0 ++ * 885, 875 SEC 1.2 ++ * 8555E, 8541E SEC 2.0 ++ * 8349E SEC 2.01 ++ * 8548E SEC 2.1 ++ * ++ * The following table shows the features offered by each SEC version: ++ * ++ * Max. chan- ++ * version Bus I/F Clock nels DEU AESU AFEU MDEU PKEU RNG KEU ++ * ++ * SEC 1.0 internal 64b 100MHz 4 1 1 1 1 1 1 0 ++ * SEC 1.2 internal 32b 66MHz 1 1 1 0 1 0 0 0 ++ * SEC 2.0 internal 64b 166MHz 4 1 1 1 1 1 1 0 ++ * SEC 2.01 internal 64b 166MHz 4 1 1 1 1 1 1 0 ++ * SEC 2.1 internal 64b 333MHz 4 1 1 1 1 1 1 1 ++ * ++ * Each execution unit in the SEC has two modes of execution; channel and ++ * slave/debug. This driver employs the channel infrastructure in the ++ * device for convenience. Only the RNG is directly accessed due to the ++ * convenience of its random fifo pool. The relationship between the ++ * channels and execution units is depicted in the following diagram: ++ * ++ * ------- ------------ ++ * ---| ch0 |---| | ++ * ------- | | ++ * | |------+-------+-------+-------+------------ ++ * ------- | | | | | | | ++ * ---| ch1 |---| | | | | | | ++ * ------- | | ------ ------ ------ ------ ------ ++ * |controller| |DEU | |AESU| |MDEU| |PKEU| ... |RNG | ++ * ------- | | ------ ------ ------ ------ ------ ++ * ---| ch2 |---| | | | | | | ++ * ------- | | | | | | | ++ * | |------+-------+-------+-------+------------ ++ * ------- | | ++ * ---| ch3 |---| | ++ * ------- ------------ ++ * ++ * Channel ch0 may drive an aes operation to the aes unit (AESU), ++ * and, at the same time, ch1 may drive a message digest operation ++ * to the mdeu. Each channel has an input descriptor FIFO, and the ++ * FIFO can contain, e.g. on the 8541E, up to 24 entries, before a ++ * a buffer overrun error is triggered. The controller is responsible ++ * for fetching the data from descriptor pointers, and passing the ++ * data to the appropriate EUs. The controller also writes the ++ * cryptographic operation's result to memory. The SEC notifies ++ * completion by triggering an interrupt and/or setting the 1st byte ++ * of the hdr field to 0xff. ++ * ++ * TODO: ++ * o support more algorithms ++ * o support more versions of the SEC ++ * o add support for linux 2.4 ++ * o scatter-gather (sg) support ++ * o add support for public key ops (PKEU) ++ * o add statistics ++ */ ++ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include /* dma_map_single() */ ++#include ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,15) ++#include ++#endif ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) ++#include ++#endif ++ ++#include ++#include ++ ++#define DRV_NAME "talitos" ++ ++#include "talitos_dev.h" ++#include "talitos_soft.h" ++ ++#define read_random(p,l) get_random_bytes(p,l) ++ ++const char talitos_driver_name[] = "Talitos OCF"; ++const char talitos_driver_version[] = "0.2"; ++ ++static int talitos_newsession(device_t dev, u_int32_t *sidp, ++ struct cryptoini *cri); ++static int talitos_freesession(device_t dev, u_int64_t tid); ++static int talitos_process(device_t dev, struct cryptop *crp, int hint); ++static void dump_talitos_status(struct talitos_softc *sc); ++static int talitos_submit(struct talitos_softc *sc, struct talitos_desc *td, ++ int chsel); ++static void talitos_doneprocessing(struct talitos_softc *sc); ++static void talitos_init_device(struct talitos_softc *sc); ++static void talitos_reset_device_master(struct talitos_softc *sc); ++static void talitos_reset_device(struct talitos_softc *sc); ++static void talitos_errorprocessing(struct talitos_softc *sc); ++#ifdef CONFIG_PPC_MERGE ++static int talitos_probe(struct of_device *ofdev, const struct of_device_id *match); ++static int talitos_remove(struct of_device *ofdev); ++#else ++static int talitos_probe(struct platform_device *pdev); ++static int talitos_remove(struct platform_device *pdev); ++#endif ++#ifdef CONFIG_OCF_RANDOMHARVEST ++static int talitos_read_random(void *arg, u_int32_t *buf, int maxwords); ++static void talitos_rng_init(struct talitos_softc *sc); ++#endif ++ ++static device_method_t talitos_methods = { ++ /* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, talitos_newsession), ++ DEVMETHOD(cryptodev_freesession,talitos_freesession), ++ DEVMETHOD(cryptodev_process, talitos_process), ++}; ++ ++#define debug talitos_debug ++int talitos_debug = 0; ++module_param(talitos_debug, int, 0644); ++MODULE_PARM_DESC(talitos_debug, "Enable debug"); ++ ++static inline void talitos_write(volatile unsigned *addr, u32 val) ++{ ++ out_be32(addr, val); ++} ++ ++static inline u32 talitos_read(volatile unsigned *addr) ++{ ++ u32 val; ++ val = in_be32(addr); ++ return val; ++} ++ ++static void dump_talitos_status(struct talitos_softc *sc) ++{ ++ unsigned int v, v_hi, i, *ptr; ++ v = talitos_read(sc->sc_base_addr + TALITOS_MCR); ++ v_hi = talitos_read(sc->sc_base_addr + TALITOS_MCR_HI); ++ printk(KERN_INFO "%s: MCR 0x%08x_%08x\n", ++ device_get_nameunit(sc->sc_cdev), v, v_hi); ++ v = talitos_read(sc->sc_base_addr + TALITOS_IMR); ++ v_hi = talitos_read(sc->sc_base_addr + TALITOS_IMR_HI); ++ printk(KERN_INFO "%s: IMR 0x%08x_%08x\n", ++ device_get_nameunit(sc->sc_cdev), v, v_hi); ++ v = talitos_read(sc->sc_base_addr + TALITOS_ISR); ++ v_hi = talitos_read(sc->sc_base_addr + TALITOS_ISR_HI); ++ printk(KERN_INFO "%s: ISR 0x%08x_%08x\n", ++ device_get_nameunit(sc->sc_cdev), v, v_hi); ++ for (i = 0; i < sc->sc_num_channels; i++) { ++ v = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + ++ TALITOS_CH_CDPR); ++ v_hi = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + ++ TALITOS_CH_CDPR_HI); ++ printk(KERN_INFO "%s: CDPR ch%d 0x%08x_%08x\n", ++ device_get_nameunit(sc->sc_cdev), i, v, v_hi); ++ } ++ for (i = 0; i < sc->sc_num_channels; i++) { ++ v = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + ++ TALITOS_CH_CCPSR); ++ v_hi = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + ++ TALITOS_CH_CCPSR_HI); ++ printk(KERN_INFO "%s: CCPSR ch%d 0x%08x_%08x\n", ++ device_get_nameunit(sc->sc_cdev), i, v, v_hi); ++ } ++ ptr = sc->sc_base_addr + TALITOS_CH_DESCBUF; ++ for (i = 0; i < 16; i++) { ++ v = talitos_read(ptr++); v_hi = talitos_read(ptr++); ++ printk(KERN_INFO "%s: DESCBUF ch0 0x%08x_%08x (tdp%02d)\n", ++ device_get_nameunit(sc->sc_cdev), v, v_hi, i); ++ } ++ return; ++} ++ ++ ++#ifdef CONFIG_OCF_RANDOMHARVEST ++/* ++ * pull random numbers off the RNG FIFO, not exceeding amount available ++ */ ++static int ++talitos_read_random(void *arg, u_int32_t *buf, int maxwords) ++{ ++ struct talitos_softc *sc = (struct talitos_softc *) arg; ++ int rc; ++ u_int32_t v; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ /* check for things like FIFO underflow */ ++ v = talitos_read(sc->sc_base_addr + TALITOS_RNGISR_HI); ++ if (unlikely(v)) { ++ printk(KERN_ERR "%s: RNGISR_HI error %08x\n", ++ device_get_nameunit(sc->sc_cdev), v); ++ return 0; ++ } ++ /* ++ * OFL is number of available 64-bit words, ++ * shift and convert to a 32-bit word count ++ */ ++ v = talitos_read(sc->sc_base_addr + TALITOS_RNGSR_HI); ++ v = (v & TALITOS_RNGSR_HI_OFL) >> (16 - 1); ++ if (maxwords > v) ++ maxwords = v; ++ for (rc = 0; rc < maxwords; rc++) { ++ buf[rc] = talitos_read(sc->sc_base_addr + ++ TALITOS_RNG_FIFO + rc*sizeof(u_int32_t)); ++ } ++ if (maxwords & 1) { ++ /* ++ * RNG will complain with an AE in the RNGISR ++ * if we don't complete the pairs of 32-bit reads ++ * to its 64-bit register based FIFO ++ */ ++ v = talitos_read(sc->sc_base_addr + ++ TALITOS_RNG_FIFO + rc*sizeof(u_int32_t)); ++ } ++ ++ return rc; ++} ++ ++static void ++talitos_rng_init(struct talitos_softc *sc) ++{ ++ u_int32_t v; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ /* reset RNG EU */ ++ v = talitos_read(sc->sc_base_addr + TALITOS_RNGRCR_HI); ++ v |= TALITOS_RNGRCR_HI_SR; ++ talitos_write(sc->sc_base_addr + TALITOS_RNGRCR_HI, v); ++ while ((talitos_read(sc->sc_base_addr + TALITOS_RNGSR_HI) ++ & TALITOS_RNGSR_HI_RD) == 0) ++ cpu_relax(); ++ /* ++ * we tell the RNG to start filling the RNG FIFO ++ * by writing the RNGDSR ++ */ ++ v = talitos_read(sc->sc_base_addr + TALITOS_RNGDSR_HI); ++ talitos_write(sc->sc_base_addr + TALITOS_RNGDSR_HI, v); ++ /* ++ * 64 bits of data will be pushed onto the FIFO every ++ * 256 SEC cycles until the FIFO is full. The RNG then ++ * attempts to keep the FIFO full. ++ */ ++ v = talitos_read(sc->sc_base_addr + TALITOS_RNGISR_HI); ++ if (v) { ++ printk(KERN_ERR "%s: RNGISR_HI error %08x\n", ++ device_get_nameunit(sc->sc_cdev), v); ++ return; ++ } ++ /* ++ * n.b. we need to add a FIPS test here - if the RNG is going ++ * to fail, it's going to fail at reset time ++ */ ++ return; ++} ++#endif /* CONFIG_OCF_RANDOMHARVEST */ ++ ++/* ++ * Generate a new software session. ++ */ ++static int ++talitos_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) ++{ ++ struct cryptoini *c, *encini = NULL, *macini = NULL; ++ struct talitos_softc *sc = device_get_softc(dev); ++ struct talitos_session *ses = NULL; ++ int sesn; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ if (sidp == NULL || cri == NULL || sc == NULL) { ++ DPRINTF("%s,%d - EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ for (c = cri; c != NULL; c = c->cri_next) { ++ if (c->cri_alg == CRYPTO_MD5 || ++ c->cri_alg == CRYPTO_MD5_HMAC || ++ c->cri_alg == CRYPTO_SHA1 || ++ c->cri_alg == CRYPTO_SHA1_HMAC || ++ c->cri_alg == CRYPTO_NULL_HMAC) { ++ if (macini) ++ return EINVAL; ++ macini = c; ++ } else if (c->cri_alg == CRYPTO_DES_CBC || ++ c->cri_alg == CRYPTO_3DES_CBC || ++ c->cri_alg == CRYPTO_AES_CBC || ++ c->cri_alg == CRYPTO_NULL_CBC) { ++ if (encini) ++ return EINVAL; ++ encini = c; ++ } else { ++ DPRINTF("UNKNOWN c->cri_alg %d\n", encini->cri_alg); ++ return EINVAL; ++ } ++ } ++ if (encini == NULL && macini == NULL) ++ return EINVAL; ++ if (encini) { ++ /* validate key length */ ++ switch (encini->cri_alg) { ++ case CRYPTO_DES_CBC: ++ if (encini->cri_klen != 64) ++ return EINVAL; ++ break; ++ case CRYPTO_3DES_CBC: ++ if (encini->cri_klen != 192) { ++ return EINVAL; ++ } ++ break; ++ case CRYPTO_AES_CBC: ++ if (encini->cri_klen != 128 && ++ encini->cri_klen != 192 && ++ encini->cri_klen != 256) ++ return EINVAL; ++ break; ++ default: ++ DPRINTF("UNKNOWN encini->cri_alg %d\n", ++ encini->cri_alg); ++ return EINVAL; ++ } ++ } ++ ++ if (sc->sc_sessions == NULL) { ++ ses = sc->sc_sessions = (struct talitos_session *) ++ kmalloc(sizeof(struct talitos_session), SLAB_ATOMIC); ++ if (ses == NULL) ++ return ENOMEM; ++ memset(ses, 0, sizeof(struct talitos_session)); ++ sesn = 0; ++ sc->sc_nsessions = 1; ++ } else { ++ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { ++ if (sc->sc_sessions[sesn].ses_used == 0) { ++ ses = &sc->sc_sessions[sesn]; ++ break; ++ } ++ } ++ ++ if (ses == NULL) { ++ /* allocating session */ ++ sesn = sc->sc_nsessions; ++ ses = (struct talitos_session *) kmalloc( ++ (sesn + 1) * sizeof(struct talitos_session), ++ SLAB_ATOMIC); ++ if (ses == NULL) ++ return ENOMEM; ++ memset(ses, 0, ++ (sesn + 1) * sizeof(struct talitos_session)); ++ memcpy(ses, sc->sc_sessions, ++ sesn * sizeof(struct talitos_session)); ++ memset(sc->sc_sessions, 0, ++ sesn * sizeof(struct talitos_session)); ++ kfree(sc->sc_sessions); ++ sc->sc_sessions = ses; ++ ses = &sc->sc_sessions[sesn]; ++ sc->sc_nsessions++; ++ } ++ } ++ ++ ses->ses_used = 1; ++ ++ if (encini) { ++ ses->ses_klen = (encini->cri_klen + 7) / 8; ++ memcpy(ses->ses_key, encini->cri_key, ses->ses_klen); ++ if (macini) { ++ /* doing hash on top of cipher */ ++ ses->ses_hmac_len = (macini->cri_klen + 7) / 8; ++ memcpy(ses->ses_hmac, macini->cri_key, ++ ses->ses_hmac_len); ++ } ++ } else if (macini) { ++ /* doing hash */ ++ ses->ses_klen = (macini->cri_klen + 7) / 8; ++ memcpy(ses->ses_key, macini->cri_key, ses->ses_klen); ++ } ++ ++ /* back compat way of determining MSC result len */ ++ if (macini) { ++ ses->ses_mlen = macini->cri_mlen; ++ if (ses->ses_mlen == 0) { ++ if (macini->cri_alg == CRYPTO_MD5_HMAC) ++ ses->ses_mlen = MD5_HASH_LEN; ++ else ++ ses->ses_mlen = SHA1_HASH_LEN; ++ } ++ } ++ ++ /* really should make up a template td here, ++ * and only fill things like i/o and direction in process() */ ++ ++ /* assign session ID */ ++ *sidp = TALITOS_SID(sc->sc_num, sesn); ++ return 0; ++} ++ ++/* ++ * Deallocate a session. ++ */ ++static int ++talitos_freesession(device_t dev, u_int64_t tid) ++{ ++ struct talitos_softc *sc = device_get_softc(dev); ++ int session, ret; ++ u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; ++ ++ if (sc == NULL) ++ return EINVAL; ++ session = TALITOS_SESSION(sid); ++ if (session < sc->sc_nsessions) { ++ memset(&sc->sc_sessions[session], 0, ++ sizeof(sc->sc_sessions[session])); ++ ret = 0; ++ } else ++ ret = EINVAL; ++ return ret; ++} ++ ++/* ++ * launch device processing - it will come back with done notification ++ * in the form of an interrupt and/or HDR_DONE_BITS in header ++ */ ++static int ++talitos_submit( ++ struct talitos_softc *sc, ++ struct talitos_desc *td, ++ int chsel) ++{ ++ u_int32_t v; ++ ++ v = dma_map_single(NULL, td, sizeof(*td), DMA_TO_DEVICE); ++ talitos_write(sc->sc_base_addr + ++ chsel*TALITOS_CH_OFFSET + TALITOS_CH_FF, 0); ++ talitos_write(sc->sc_base_addr + ++ chsel*TALITOS_CH_OFFSET + TALITOS_CH_FF_HI, v); ++ return 0; ++} ++ ++static int ++talitos_process(device_t dev, struct cryptop *crp, int hint) ++{ ++ int i, err = 0, ivsize; ++ struct talitos_softc *sc = device_get_softc(dev); ++ struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; ++ caddr_t iv; ++ struct talitos_session *ses; ++ struct talitos_desc *td; ++ unsigned long flags; ++ /* descriptor mappings */ ++ int hmac_key, hmac_data, cipher_iv, cipher_key, ++ in_fifo, out_fifo, cipher_iv_out; ++ static int chsel = -1; ++ u_int32_t rand_iv[4]; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { ++ return EINVAL; ++ } ++ crp->crp_etype = 0; ++ if (TALITOS_SESSION(crp->crp_sid) >= sc->sc_nsessions) { ++ return EINVAL; ++ } ++ ++ ses = &sc->sc_sessions[TALITOS_SESSION(crp->crp_sid)]; ++ ++ /* enter the channel scheduler */ ++ spin_lock_irqsave(&sc->sc_chnfifolock[sc->sc_num_channels], flags); ++ ++ /* reuse channel that already had/has requests for the required EU */ ++ for (i = 0; i < sc->sc_num_channels; i++) { ++ if (sc->sc_chnlastalg[i] == crp->crp_desc->crd_alg) ++ break; ++ } ++ if (i == sc->sc_num_channels) { ++ /* ++ * haven't seen this algo the last sc_num_channels or more ++ * use round robin in this case ++ * nb: sc->sc_num_channels must be power of 2 ++ */ ++ chsel = (chsel + 1) & (sc->sc_num_channels - 1); ++ } else { ++ /* ++ * matches channel with same target execution unit; ++ * use same channel in this case ++ */ ++ chsel = i; ++ } ++ sc->sc_chnlastalg[chsel] = crp->crp_desc->crd_alg; ++ ++ /* release the channel scheduler lock */ ++ spin_unlock_irqrestore(&sc->sc_chnfifolock[sc->sc_num_channels], flags); ++ ++ /* acquire the selected channel fifo lock */ ++ spin_lock_irqsave(&sc->sc_chnfifolock[chsel], flags); ++ ++ /* find and reserve next available descriptor-cryptop pair */ ++ for (i = 0; i < sc->sc_chfifo_len; i++) { ++ if (sc->sc_chnfifo[chsel][i].cf_desc.hdr == 0) { ++ /* ++ * ensure correct descriptor formation by ++ * avoiding inadvertently setting "optional" entries ++ * e.g. not using "optional" dptr2 for MD/HMAC descs ++ */ ++ memset(&sc->sc_chnfifo[chsel][i].cf_desc, ++ 0, sizeof(*td)); ++ /* reserve it with done notification request bit */ ++ sc->sc_chnfifo[chsel][i].cf_desc.hdr |= ++ TALITOS_DONE_NOTIFY; ++ break; ++ } ++ } ++ spin_unlock_irqrestore(&sc->sc_chnfifolock[chsel], flags); ++ ++ if (i == sc->sc_chfifo_len) { ++ /* fifo full */ ++ err = ERESTART; ++ goto errout; ++ } ++ ++ td = &sc->sc_chnfifo[chsel][i].cf_desc; ++ sc->sc_chnfifo[chsel][i].cf_crp = crp; ++ ++ crd1 = crp->crp_desc; ++ if (crd1 == NULL) { ++ err = EINVAL; ++ goto errout; ++ } ++ crd2 = crd1->crd_next; ++ /* prevent compiler warning */ ++ hmac_key = 0; ++ hmac_data = 0; ++ if (crd2 == NULL) { ++ td->hdr |= TD_TYPE_COMMON_NONSNOOP_NO_AFEU; ++ /* assign descriptor dword ptr mappings for this desc. type */ ++ cipher_iv = 1; ++ cipher_key = 2; ++ in_fifo = 3; ++ cipher_iv_out = 5; ++ if (crd1->crd_alg == CRYPTO_MD5_HMAC || ++ crd1->crd_alg == CRYPTO_SHA1_HMAC || ++ crd1->crd_alg == CRYPTO_SHA1 || ++ crd1->crd_alg == CRYPTO_MD5) { ++ out_fifo = 5; ++ maccrd = crd1; ++ enccrd = NULL; ++ } else if (crd1->crd_alg == CRYPTO_DES_CBC || ++ crd1->crd_alg == CRYPTO_3DES_CBC || ++ crd1->crd_alg == CRYPTO_AES_CBC || ++ crd1->crd_alg == CRYPTO_ARC4) { ++ out_fifo = 4; ++ maccrd = NULL; ++ enccrd = crd1; ++ } else { ++ DPRINTF("UNKNOWN crd1->crd_alg %d\n", crd1->crd_alg); ++ err = EINVAL; ++ goto errout; ++ } ++ } else { ++ if (sc->sc_desc_types & TALITOS_HAS_DT_IPSEC_ESP) { ++ td->hdr |= TD_TYPE_IPSEC_ESP; ++ } else { ++ DPRINTF("unimplemented: multiple descriptor ipsec\n"); ++ err = EINVAL; ++ goto errout; ++ } ++ /* assign descriptor dword ptr mappings for this desc. type */ ++ hmac_key = 0; ++ hmac_data = 1; ++ cipher_iv = 2; ++ cipher_key = 3; ++ in_fifo = 4; ++ out_fifo = 5; ++ cipher_iv_out = 6; ++ if ((crd1->crd_alg == CRYPTO_MD5_HMAC || ++ crd1->crd_alg == CRYPTO_SHA1_HMAC || ++ crd1->crd_alg == CRYPTO_MD5 || ++ crd1->crd_alg == CRYPTO_SHA1) && ++ (crd2->crd_alg == CRYPTO_DES_CBC || ++ crd2->crd_alg == CRYPTO_3DES_CBC || ++ crd2->crd_alg == CRYPTO_AES_CBC || ++ crd2->crd_alg == CRYPTO_ARC4) && ++ ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { ++ maccrd = crd1; ++ enccrd = crd2; ++ } else if ((crd1->crd_alg == CRYPTO_DES_CBC || ++ crd1->crd_alg == CRYPTO_ARC4 || ++ crd1->crd_alg == CRYPTO_3DES_CBC || ++ crd1->crd_alg == CRYPTO_AES_CBC) && ++ (crd2->crd_alg == CRYPTO_MD5_HMAC || ++ crd2->crd_alg == CRYPTO_SHA1_HMAC || ++ crd2->crd_alg == CRYPTO_MD5 || ++ crd2->crd_alg == CRYPTO_SHA1) && ++ (crd1->crd_flags & CRD_F_ENCRYPT)) { ++ enccrd = crd1; ++ maccrd = crd2; ++ } else { ++ /* We cannot order the SEC as requested */ ++ printk("%s: cannot do the order\n", ++ device_get_nameunit(sc->sc_cdev)); ++ err = EINVAL; ++ goto errout; ++ } ++ } ++ /* assign in_fifo and out_fifo based on input/output struct type */ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ /* using SKB buffers */ ++ struct sk_buff *skb = (struct sk_buff *)crp->crp_buf; ++ if (skb_shinfo(skb)->nr_frags) { ++ printk("%s: skb frags unimplemented\n", ++ device_get_nameunit(sc->sc_cdev)); ++ err = EINVAL; ++ goto errout; ++ } ++ td->ptr[in_fifo].ptr = dma_map_single(NULL, skb->data, ++ skb->len, DMA_TO_DEVICE); ++ td->ptr[in_fifo].len = skb->len; ++ td->ptr[out_fifo].ptr = dma_map_single(NULL, skb->data, ++ skb->len, DMA_TO_DEVICE); ++ td->ptr[out_fifo].len = skb->len; ++ td->ptr[hmac_data].ptr = dma_map_single(NULL, skb->data, ++ skb->len, DMA_TO_DEVICE); ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ /* using IOV buffers */ ++ struct uio *uiop = (struct uio *)crp->crp_buf; ++ if (uiop->uio_iovcnt > 1) { ++ printk("%s: iov frags unimplemented\n", ++ device_get_nameunit(sc->sc_cdev)); ++ err = EINVAL; ++ goto errout; ++ } ++ td->ptr[in_fifo].ptr = dma_map_single(NULL, ++ uiop->uio_iov->iov_base, crp->crp_ilen, DMA_TO_DEVICE); ++ td->ptr[in_fifo].len = crp->crp_ilen; ++ /* crp_olen is never set; always use crp_ilen */ ++ td->ptr[out_fifo].ptr = dma_map_single(NULL, ++ uiop->uio_iov->iov_base, ++ crp->crp_ilen, DMA_TO_DEVICE); ++ td->ptr[out_fifo].len = crp->crp_ilen; ++ } else { ++ /* using contig buffers */ ++ td->ptr[in_fifo].ptr = dma_map_single(NULL, ++ crp->crp_buf, crp->crp_ilen, DMA_TO_DEVICE); ++ td->ptr[in_fifo].len = crp->crp_ilen; ++ td->ptr[out_fifo].ptr = dma_map_single(NULL, ++ crp->crp_buf, crp->crp_ilen, DMA_TO_DEVICE); ++ td->ptr[out_fifo].len = crp->crp_ilen; ++ } ++ if (enccrd) { ++ switch (enccrd->crd_alg) { ++ case CRYPTO_3DES_CBC: ++ td->hdr |= TALITOS_MODE0_DEU_3DES; ++ /* FALLTHROUGH */ ++ case CRYPTO_DES_CBC: ++ td->hdr |= TALITOS_SEL0_DEU ++ | TALITOS_MODE0_DEU_CBC; ++ if (enccrd->crd_flags & CRD_F_ENCRYPT) ++ td->hdr |= TALITOS_MODE0_DEU_ENC; ++ ivsize = 2*sizeof(u_int32_t); ++ DPRINTF("%cDES ses %d ch %d len %d\n", ++ (td->hdr & TALITOS_MODE0_DEU_3DES)?'3':'1', ++ (u32)TALITOS_SESSION(crp->crp_sid), ++ chsel, td->ptr[in_fifo].len); ++ break; ++ case CRYPTO_AES_CBC: ++ td->hdr |= TALITOS_SEL0_AESU ++ | TALITOS_MODE0_AESU_CBC; ++ if (enccrd->crd_flags & CRD_F_ENCRYPT) ++ td->hdr |= TALITOS_MODE0_AESU_ENC; ++ ivsize = 4*sizeof(u_int32_t); ++ DPRINTF("AES ses %d ch %d len %d\n", ++ (u32)TALITOS_SESSION(crp->crp_sid), ++ chsel, td->ptr[in_fifo].len); ++ break; ++ default: ++ printk("%s: unimplemented enccrd->crd_alg %d\n", ++ device_get_nameunit(sc->sc_cdev), enccrd->crd_alg); ++ err = EINVAL; ++ goto errout; ++ } ++ /* ++ * Setup encrypt/decrypt state. When using basic ops ++ * we can't use an inline IV because hash/crypt offset ++ * must be from the end of the IV to the start of the ++ * crypt data and this leaves out the preceding header ++ * from the hash calculation. Instead we place the IV ++ * in the state record and set the hash/crypt offset to ++ * copy both the header+IV. ++ */ ++ if (enccrd->crd_flags & CRD_F_ENCRYPT) { ++ td->hdr |= TALITOS_DIR_OUTBOUND; ++ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) ++ iv = enccrd->crd_iv; ++ else ++ read_random((iv = (caddr_t) rand_iv), sizeof(rand_iv)); ++ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ enccrd->crd_inject, ivsize, iv); ++ } ++ } else { ++ td->hdr |= TALITOS_DIR_INBOUND; ++ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) { ++ iv = enccrd->crd_iv; ++ } else { ++ iv = (caddr_t) rand_iv; ++ crypto_copydata(crp->crp_flags, crp->crp_buf, ++ enccrd->crd_inject, ivsize, iv); ++ } ++ } ++ td->ptr[cipher_iv].ptr = dma_map_single(NULL, iv, ivsize, ++ DMA_TO_DEVICE); ++ td->ptr[cipher_iv].len = ivsize; ++ /* ++ * we don't need the cipher iv out length/pointer ++ * field to do ESP IPsec. Therefore we set the len field as 0, ++ * which tells the SEC not to do anything with this len/ptr ++ * field. Previously, when length/pointer as pointing to iv, ++ * it gave us corruption of packets. ++ */ ++ td->ptr[cipher_iv_out].len = 0; ++ } ++ if (enccrd && maccrd) { ++ /* this is ipsec only for now */ ++ td->hdr |= TALITOS_SEL1_MDEU ++ | TALITOS_MODE1_MDEU_INIT ++ | TALITOS_MODE1_MDEU_PAD; ++ switch (maccrd->crd_alg) { ++ case CRYPTO_MD5: ++ td->hdr |= TALITOS_MODE1_MDEU_MD5; ++ break; ++ case CRYPTO_MD5_HMAC: ++ td->hdr |= TALITOS_MODE1_MDEU_MD5_HMAC; ++ break; ++ case CRYPTO_SHA1: ++ td->hdr |= TALITOS_MODE1_MDEU_SHA1; ++ break; ++ case CRYPTO_SHA1_HMAC: ++ td->hdr |= TALITOS_MODE1_MDEU_SHA1_HMAC; ++ break; ++ default: ++ /* We cannot order the SEC as requested */ ++ printk("%s: cannot do the order\n", ++ device_get_nameunit(sc->sc_cdev)); ++ err = EINVAL; ++ goto errout; ++ } ++ if ((maccrd->crd_alg == CRYPTO_MD5_HMAC) || ++ (maccrd->crd_alg == CRYPTO_SHA1_HMAC)) { ++ /* ++ * The offset from hash data to the start of ++ * crypt data is the difference in the skips. ++ */ ++ /* ipsec only for now */ ++ td->ptr[hmac_key].ptr = dma_map_single(NULL, ++ ses->ses_hmac, ses->ses_hmac_len, DMA_TO_DEVICE); ++ td->ptr[hmac_key].len = ses->ses_hmac_len; ++ td->ptr[in_fifo].ptr += enccrd->crd_skip; ++ td->ptr[in_fifo].len = enccrd->crd_len; ++ td->ptr[out_fifo].ptr += enccrd->crd_skip; ++ td->ptr[out_fifo].len = enccrd->crd_len; ++ /* bytes of HMAC to postpend to ciphertext */ ++ td->ptr[out_fifo].extent = ses->ses_mlen; ++ td->ptr[hmac_data].ptr += maccrd->crd_skip; ++ td->ptr[hmac_data].len = enccrd->crd_skip - maccrd->crd_skip; ++ } ++ if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) { ++ printk("%s: CRD_F_KEY_EXPLICIT unimplemented\n", ++ device_get_nameunit(sc->sc_cdev)); ++ } ++ } ++ if (!enccrd && maccrd) { ++ /* single MD5 or SHA */ ++ td->hdr |= TALITOS_SEL0_MDEU ++ | TALITOS_MODE0_MDEU_INIT ++ | TALITOS_MODE0_MDEU_PAD; ++ switch (maccrd->crd_alg) { ++ case CRYPTO_MD5: ++ td->hdr |= TALITOS_MODE0_MDEU_MD5; ++ DPRINTF("MD5 ses %d ch %d len %d\n", ++ (u32)TALITOS_SESSION(crp->crp_sid), ++ chsel, td->ptr[in_fifo].len); ++ break; ++ case CRYPTO_MD5_HMAC: ++ td->hdr |= TALITOS_MODE0_MDEU_MD5_HMAC; ++ break; ++ case CRYPTO_SHA1: ++ td->hdr |= TALITOS_MODE0_MDEU_SHA1; ++ DPRINTF("SHA1 ses %d ch %d len %d\n", ++ (u32)TALITOS_SESSION(crp->crp_sid), ++ chsel, td->ptr[in_fifo].len); ++ break; ++ case CRYPTO_SHA1_HMAC: ++ td->hdr |= TALITOS_MODE0_MDEU_SHA1_HMAC; ++ break; ++ default: ++ /* We cannot order the SEC as requested */ ++ DPRINTF("cannot do the order\n"); ++ err = EINVAL; ++ goto errout; ++ } ++ ++ if (crp->crp_flags & CRYPTO_F_IOV) ++ td->ptr[out_fifo].ptr += maccrd->crd_inject; ++ ++ if ((maccrd->crd_alg == CRYPTO_MD5_HMAC) || ++ (maccrd->crd_alg == CRYPTO_SHA1_HMAC)) { ++ td->ptr[hmac_key].ptr = dma_map_single(NULL, ++ ses->ses_hmac, ses->ses_hmac_len, ++ DMA_TO_DEVICE); ++ td->ptr[hmac_key].len = ses->ses_hmac_len; ++ } ++ } ++ else { ++ /* using process key (session data has duplicate) */ ++ td->ptr[cipher_key].ptr = dma_map_single(NULL, ++ enccrd->crd_key, (enccrd->crd_klen + 7) / 8, ++ DMA_TO_DEVICE); ++ td->ptr[cipher_key].len = (enccrd->crd_klen + 7) / 8; ++ } ++ /* descriptor complete - GO! */ ++ return talitos_submit(sc, td, chsel); ++ ++errout: ++ if (err != ERESTART) { ++ crp->crp_etype = err; ++ crypto_done(crp); ++ } ++ return err; ++} ++ ++/* go through all channels descriptors, notifying OCF what has ++ * _and_hasn't_ successfully completed and reset the device ++ * (otherwise it's up to decoding desc hdrs!) ++ */ ++static void talitos_errorprocessing(struct talitos_softc *sc) ++{ ++ unsigned long flags; ++ int i, j; ++ ++ /* disable further scheduling until under control */ ++ spin_lock_irqsave(&sc->sc_chnfifolock[sc->sc_num_channels], flags); ++ ++ if (debug) dump_talitos_status(sc); ++ /* go through descriptors, try and salvage those successfully done, ++ * and EIO those that weren't ++ */ ++ for (i = 0; i < sc->sc_num_channels; i++) { ++ spin_lock_irqsave(&sc->sc_chnfifolock[i], flags); ++ for (j = 0; j < sc->sc_chfifo_len; j++) { ++ if (sc->sc_chnfifo[i][j].cf_desc.hdr) { ++ if ((sc->sc_chnfifo[i][j].cf_desc.hdr ++ & TALITOS_HDR_DONE_BITS) ++ != TALITOS_HDR_DONE_BITS) { ++ /* this one didn't finish */ ++ /* signify in crp->etype */ ++ sc->sc_chnfifo[i][j].cf_crp->crp_etype ++ = EIO; ++ } ++ } else ++ continue; /* free entry */ ++ /* either way, notify ocf */ ++ crypto_done(sc->sc_chnfifo[i][j].cf_crp); ++ /* and tag it available again ++ * ++ * memset to ensure correct descriptor formation by ++ * avoiding inadvertently setting "optional" entries ++ * e.g. not using "optional" dptr2 MD/HMAC processing ++ */ ++ memset(&sc->sc_chnfifo[i][j].cf_desc, ++ 0, sizeof(struct talitos_desc)); ++ } ++ spin_unlock_irqrestore(&sc->sc_chnfifolock[i], flags); ++ } ++ /* reset and initialize the SEC h/w device */ ++ talitos_reset_device(sc); ++ talitos_init_device(sc); ++#ifdef CONFIG_OCF_RANDOMHARVEST ++ if (sc->sc_exec_units & TALITOS_HAS_EU_RNG) ++ talitos_rng_init(sc); ++#endif ++ ++ /* Okay. Stand by. */ ++ spin_unlock_irqrestore(&sc->sc_chnfifolock[sc->sc_num_channels], flags); ++ ++ return; ++} ++ ++/* go through all channels descriptors, notifying OCF what's been done */ ++static void talitos_doneprocessing(struct talitos_softc *sc) ++{ ++ unsigned long flags; ++ int i, j; ++ ++ /* go through descriptors looking for done bits */ ++ for (i = 0; i < sc->sc_num_channels; i++) { ++ spin_lock_irqsave(&sc->sc_chnfifolock[i], flags); ++ for (j = 0; j < sc->sc_chfifo_len; j++) { ++ /* descriptor has done bits set? */ ++ if ((sc->sc_chnfifo[i][j].cf_desc.hdr ++ & TALITOS_HDR_DONE_BITS) ++ == TALITOS_HDR_DONE_BITS) { ++ /* notify ocf */ ++ crypto_done(sc->sc_chnfifo[i][j].cf_crp); ++ /* and tag it available again ++ * ++ * memset to ensure correct descriptor formation by ++ * avoiding inadvertently setting "optional" entries ++ * e.g. not using "optional" dptr2 MD/HMAC processing ++ */ ++ memset(&sc->sc_chnfifo[i][j].cf_desc, ++ 0, sizeof(struct talitos_desc)); ++ } ++ } ++ spin_unlock_irqrestore(&sc->sc_chnfifolock[i], flags); ++ } ++ return; ++} ++ ++static irqreturn_t ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) ++talitos_intr(int irq, void *arg) ++#else ++talitos_intr(int irq, void *arg, struct pt_regs *regs) ++#endif ++{ ++ struct talitos_softc *sc = arg; ++ u_int32_t v, v_hi; ++ ++ /* ack */ ++ v = talitos_read(sc->sc_base_addr + TALITOS_ISR); ++ v_hi = talitos_read(sc->sc_base_addr + TALITOS_ISR_HI); ++ talitos_write(sc->sc_base_addr + TALITOS_ICR, v); ++ talitos_write(sc->sc_base_addr + TALITOS_ICR_HI, v_hi); ++ ++ if (unlikely(v & TALITOS_ISR_ERROR)) { ++ /* Okay, Houston, we've had a problem here. */ ++ printk(KERN_DEBUG "%s: got error interrupt - ISR 0x%08x_%08x\n", ++ device_get_nameunit(sc->sc_cdev), v, v_hi); ++ talitos_errorprocessing(sc); ++ } else ++ if (likely(v & TALITOS_ISR_DONE)) { ++ talitos_doneprocessing(sc); ++ } ++ return IRQ_HANDLED; ++} ++ ++/* ++ * Initialize registers we need to touch only once. ++ */ ++static void ++talitos_init_device(struct talitos_softc *sc) ++{ ++ u_int32_t v; ++ int i; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ /* init all channels */ ++ for (i = 0; i < sc->sc_num_channels; i++) { ++ v = talitos_read(sc->sc_base_addr + ++ i*TALITOS_CH_OFFSET + TALITOS_CH_CCCR_HI); ++ v |= TALITOS_CH_CCCR_HI_CDWE ++ | TALITOS_CH_CCCR_HI_CDIE; /* invoke interrupt if done */ ++ talitos_write(sc->sc_base_addr + ++ i*TALITOS_CH_OFFSET + TALITOS_CH_CCCR_HI, v); ++ } ++ /* enable all interrupts */ ++ v = talitos_read(sc->sc_base_addr + TALITOS_IMR); ++ v |= TALITOS_IMR_ALL; ++ talitos_write(sc->sc_base_addr + TALITOS_IMR, v); ++ v = talitos_read(sc->sc_base_addr + TALITOS_IMR_HI); ++ v |= TALITOS_IMR_HI_ERRONLY; ++ talitos_write(sc->sc_base_addr + TALITOS_IMR_HI, v); ++ return; ++} ++ ++/* ++ * set the master reset bit on the device. ++ */ ++static void ++talitos_reset_device_master(struct talitos_softc *sc) ++{ ++ u_int32_t v; ++ ++ /* Reset the device by writing 1 to MCR:SWR and waiting 'til cleared */ ++ v = talitos_read(sc->sc_base_addr + TALITOS_MCR); ++ talitos_write(sc->sc_base_addr + TALITOS_MCR, v | TALITOS_MCR_SWR); ++ ++ while (talitos_read(sc->sc_base_addr + TALITOS_MCR) & TALITOS_MCR_SWR) ++ cpu_relax(); ++ ++ return; ++} ++ ++/* ++ * Resets the device. Values in the registers are left as is ++ * from the reset (i.e. initial values are assigned elsewhere). ++ */ ++static void ++talitos_reset_device(struct talitos_softc *sc) ++{ ++ u_int32_t v; ++ int i; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ /* ++ * Master reset ++ * errata documentation: warning: certain SEC interrupts ++ * are not fully cleared by writing the MCR:SWR bit, ++ * set bit twice to completely reset ++ */ ++ talitos_reset_device_master(sc); /* once */ ++ talitos_reset_device_master(sc); /* and once again */ ++ ++ /* reset all channels */ ++ for (i = 0; i < sc->sc_num_channels; i++) { ++ v = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + ++ TALITOS_CH_CCCR); ++ talitos_write(sc->sc_base_addr + i*TALITOS_CH_OFFSET + ++ TALITOS_CH_CCCR, v | TALITOS_CH_CCCR_RESET); ++ } ++} ++ ++/* Set up the crypto device structure, private data, ++ * and anything else we need before we start */ ++#ifdef CONFIG_PPC_MERGE ++static int talitos_probe(struct of_device *ofdev, const struct of_device_id *match) ++#else ++static int talitos_probe(struct platform_device *pdev) ++#endif ++{ ++ struct talitos_softc *sc = NULL; ++ struct resource *r; ++#ifdef CONFIG_PPC_MERGE ++ struct device *device = &ofdev->dev; ++ struct device_node *np = ofdev->node; ++ const unsigned int *prop; ++ int err; ++ struct resource res; ++#endif ++ static int num_chips = 0; ++ int rc; ++ int i; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ sc = (struct talitos_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); ++ if (!sc) ++ return -ENOMEM; ++ memset(sc, 0, sizeof(*sc)); ++ ++ softc_device_init(sc, DRV_NAME, num_chips, talitos_methods); ++ ++ sc->sc_irq = -1; ++ sc->sc_cid = -1; ++#ifndef CONFIG_PPC_MERGE ++ sc->sc_dev = pdev; ++#endif ++ sc->sc_num = num_chips++; ++ ++#ifdef CONFIG_PPC_MERGE ++ dev_set_drvdata(device, sc); ++#else ++ platform_set_drvdata(sc->sc_dev, sc); ++#endif ++ ++ /* get the irq line */ ++#ifdef CONFIG_PPC_MERGE ++ err = of_address_to_resource(np, 0, &res); ++ if (err) ++ return -EINVAL; ++ r = &res; ++ ++ sc->sc_irq = irq_of_parse_and_map(np, 0); ++#else ++ /* get a pointer to the register memory */ ++ r = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ ++ sc->sc_irq = platform_get_irq(pdev, 0); ++#endif ++ rc = request_irq(sc->sc_irq, talitos_intr, 0, ++ device_get_nameunit(sc->sc_cdev), sc); ++ if (rc) { ++ printk(KERN_ERR "%s: failed to hook irq %d\n", ++ device_get_nameunit(sc->sc_cdev), sc->sc_irq); ++ sc->sc_irq = -1; ++ goto out; ++ } ++ ++ sc->sc_base_addr = (ocf_iomem_t) ioremap(r->start, (r->end - r->start)); ++ if (!sc->sc_base_addr) { ++ printk(KERN_ERR "%s: failed to ioremap\n", ++ device_get_nameunit(sc->sc_cdev)); ++ goto out; ++ } ++ ++ /* figure out our SEC's properties and capabilities */ ++ sc->sc_chiprev = (u64)talitos_read(sc->sc_base_addr + TALITOS_ID) << 32 ++ | talitos_read(sc->sc_base_addr + TALITOS_ID_HI); ++ DPRINTF("sec id 0x%llx\n", sc->sc_chiprev); ++ ++#ifdef CONFIG_PPC_MERGE ++ /* get SEC properties from device tree, defaulting to SEC 2.0 */ ++ ++ prop = of_get_property(np, "num-channels", NULL); ++ sc->sc_num_channels = prop ? *prop : TALITOS_NCHANNELS_SEC_2_0; ++ ++ prop = of_get_property(np, "channel-fifo-len", NULL); ++ sc->sc_chfifo_len = prop ? *prop : TALITOS_CHFIFOLEN_SEC_2_0; ++ ++ prop = of_get_property(np, "exec-units-mask", NULL); ++ sc->sc_exec_units = prop ? *prop : TALITOS_HAS_EUS_SEC_2_0; ++ ++ prop = of_get_property(np, "descriptor-types-mask", NULL); ++ sc->sc_desc_types = prop ? *prop : TALITOS_HAS_DESCTYPES_SEC_2_0; ++#else ++ /* bulk should go away with openfirmware flat device tree support */ ++ if (sc->sc_chiprev & TALITOS_ID_SEC_2_0) { ++ sc->sc_num_channels = TALITOS_NCHANNELS_SEC_2_0; ++ sc->sc_chfifo_len = TALITOS_CHFIFOLEN_SEC_2_0; ++ sc->sc_exec_units = TALITOS_HAS_EUS_SEC_2_0; ++ sc->sc_desc_types = TALITOS_HAS_DESCTYPES_SEC_2_0; ++ } else { ++ printk(KERN_ERR "%s: failed to id device\n", ++ device_get_nameunit(sc->sc_cdev)); ++ goto out; ++ } ++#endif ++ ++ /* + 1 is for the meta-channel lock used by the channel scheduler */ ++ sc->sc_chnfifolock = (spinlock_t *) kmalloc( ++ (sc->sc_num_channels + 1) * sizeof(spinlock_t), GFP_KERNEL); ++ if (!sc->sc_chnfifolock) ++ goto out; ++ for (i = 0; i < sc->sc_num_channels + 1; i++) { ++ spin_lock_init(&sc->sc_chnfifolock[i]); ++ } ++ ++ sc->sc_chnlastalg = (int *) kmalloc( ++ sc->sc_num_channels * sizeof(int), GFP_KERNEL); ++ if (!sc->sc_chnlastalg) ++ goto out; ++ memset(sc->sc_chnlastalg, 0, sc->sc_num_channels * sizeof(int)); ++ ++ sc->sc_chnfifo = (struct desc_cryptop_pair **) kmalloc( ++ sc->sc_num_channels * sizeof(struct desc_cryptop_pair *), ++ GFP_KERNEL); ++ if (!sc->sc_chnfifo) ++ goto out; ++ for (i = 0; i < sc->sc_num_channels; i++) { ++ sc->sc_chnfifo[i] = (struct desc_cryptop_pair *) kmalloc( ++ sc->sc_chfifo_len * sizeof(struct desc_cryptop_pair), ++ GFP_KERNEL); ++ if (!sc->sc_chnfifo[i]) ++ goto out; ++ memset(sc->sc_chnfifo[i], 0, ++ sc->sc_chfifo_len * sizeof(struct desc_cryptop_pair)); ++ } ++ ++ /* reset and initialize the SEC h/w device */ ++ talitos_reset_device(sc); ++ talitos_init_device(sc); ++ ++ sc->sc_cid = crypto_get_driverid(softc_get_device(sc),CRYPTOCAP_F_HARDWARE); ++ if (sc->sc_cid < 0) { ++ printk(KERN_ERR "%s: could not get crypto driver id\n", ++ device_get_nameunit(sc->sc_cdev)); ++ goto out; ++ } ++ ++ /* register algorithms with the framework */ ++ printk("%s:", device_get_nameunit(sc->sc_cdev)); ++ ++ if (sc->sc_exec_units & TALITOS_HAS_EU_RNG) { ++ printk(" rng"); ++#ifdef CONFIG_OCF_RANDOMHARVEST ++ talitos_rng_init(sc); ++ crypto_rregister(sc->sc_cid, talitos_read_random, sc); ++#endif ++ } ++ if (sc->sc_exec_units & TALITOS_HAS_EU_DEU) { ++ printk(" des/3des"); ++ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); ++ } ++ if (sc->sc_exec_units & TALITOS_HAS_EU_AESU) { ++ printk(" aes"); ++ crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); ++ } ++ if (sc->sc_exec_units & TALITOS_HAS_EU_MDEU) { ++ printk(" md5"); ++ crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0); ++ /* HMAC support only with IPsec for now */ ++ crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); ++ printk(" sha1"); ++ crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0); ++ /* HMAC support only with IPsec for now */ ++ crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); ++ } ++ printk("\n"); ++ return 0; ++ ++out: ++#ifndef CONFIG_PPC_MERGE ++ talitos_remove(pdev); ++#endif ++ return -ENOMEM; ++} ++ ++#ifdef CONFIG_PPC_MERGE ++static int talitos_remove(struct of_device *ofdev) ++#else ++static int talitos_remove(struct platform_device *pdev) ++#endif ++{ ++#ifdef CONFIG_PPC_MERGE ++ struct talitos_softc *sc = dev_get_drvdata(&ofdev->dev); ++#else ++ struct talitos_softc *sc = platform_get_drvdata(pdev); ++#endif ++ int i; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ if (sc->sc_cid >= 0) ++ crypto_unregister_all(sc->sc_cid); ++ if (sc->sc_chnfifo) { ++ for (i = 0; i < sc->sc_num_channels; i++) ++ if (sc->sc_chnfifo[i]) ++ kfree(sc->sc_chnfifo[i]); ++ kfree(sc->sc_chnfifo); ++ } ++ if (sc->sc_chnlastalg) ++ kfree(sc->sc_chnlastalg); ++ if (sc->sc_chnfifolock) ++ kfree(sc->sc_chnfifolock); ++ if (sc->sc_irq != -1) ++ free_irq(sc->sc_irq, sc); ++ if (sc->sc_base_addr) ++ iounmap((void *) sc->sc_base_addr); ++ kfree(sc); ++ return 0; ++} ++ ++#ifdef CONFIG_PPC_MERGE ++static struct of_device_id talitos_match[] = { ++ { ++ .type = "crypto", ++ .compatible = "talitos", ++ }, ++ {}, ++}; ++ ++MODULE_DEVICE_TABLE(of, talitos_match); ++ ++static struct of_platform_driver talitos_driver = { ++ .name = DRV_NAME, ++ .match_table = talitos_match, ++ .probe = talitos_probe, ++ .remove = talitos_remove, ++}; ++ ++static int __init talitos_init(void) ++{ ++ return of_register_platform_driver(&talitos_driver); ++} ++ ++static void __exit talitos_exit(void) ++{ ++ of_unregister_platform_driver(&talitos_driver); ++} ++#else ++/* Structure for a platform device driver */ ++static struct platform_driver talitos_driver = { ++ .probe = talitos_probe, ++ .remove = talitos_remove, ++ .driver = { ++ .name = "fsl-sec2", ++ } ++}; ++ ++static int __init talitos_init(void) ++{ ++ return platform_driver_register(&talitos_driver); ++} ++ ++static void __exit talitos_exit(void) ++{ ++ platform_driver_unregister(&talitos_driver); ++} ++#endif ++ ++module_init(talitos_init); ++module_exit(talitos_exit); ++ ++MODULE_LICENSE("Dual BSD/GPL"); ++MODULE_AUTHOR("kim.phillips@freescale.com"); ++MODULE_DESCRIPTION("OCF driver for Freescale SEC (talitos)"); +diff -Nur linux-3.0.4.orig/crypto/ocf/talitos/talitos_dev.h linux-3.0.4/crypto/ocf/talitos/talitos_dev.h +--- linux-3.0.4.orig/crypto/ocf/talitos/talitos_dev.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/talitos/talitos_dev.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,277 @@ ++/* ++ * Freescale SEC (talitos) device dependent data structures ++ * ++ * Copyright (c) 2006 Freescale Semiconductor, Inc. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ */ ++ ++/* device ID register values */ ++#define TALITOS_ID_SEC_2_0 0x40 ++#define TALITOS_ID_SEC_2_1 0x40 /* cross ref with IP block revision reg */ ++ ++/* ++ * following num_channels, channel-fifo-depth, exec-unit-mask, and ++ * descriptor-types-mask are for forward-compatibility with openfirmware ++ * flat device trees ++ */ ++ ++/* ++ * num_channels : the number of channels available in each SEC version. ++ */ ++ ++/* n.b. this driver requires these values be a power of 2 */ ++#define TALITOS_NCHANNELS_SEC_1_0 4 ++#define TALITOS_NCHANNELS_SEC_1_2 1 ++#define TALITOS_NCHANNELS_SEC_2_0 4 ++#define TALITOS_NCHANNELS_SEC_2_01 4 ++#define TALITOS_NCHANNELS_SEC_2_1 4 ++#define TALITOS_NCHANNELS_SEC_2_4 4 ++ ++/* ++ * channel-fifo-depth : The number of descriptor ++ * pointers a channel fetch fifo can hold. ++ */ ++#define TALITOS_CHFIFOLEN_SEC_1_0 1 ++#define TALITOS_CHFIFOLEN_SEC_1_2 1 ++#define TALITOS_CHFIFOLEN_SEC_2_0 24 ++#define TALITOS_CHFIFOLEN_SEC_2_01 24 ++#define TALITOS_CHFIFOLEN_SEC_2_1 24 ++#define TALITOS_CHFIFOLEN_SEC_2_4 24 ++ ++/* ++ * exec-unit-mask : The bitmask representing what Execution Units (EUs) ++ * are available. EU information should be encoded following the SEC's ++ * EU_SEL0 bitfield documentation, i.e. as follows: ++ * ++ * bit 31 = set if SEC permits no-EU selection (should be always set) ++ * bit 30 = set if SEC has the ARC4 EU (AFEU) ++ * bit 29 = set if SEC has the des/3des EU (DEU) ++ * bit 28 = set if SEC has the message digest EU (MDEU) ++ * bit 27 = set if SEC has the random number generator EU (RNG) ++ * bit 26 = set if SEC has the public key EU (PKEU) ++ * bit 25 = set if SEC has the aes EU (AESU) ++ * bit 24 = set if SEC has the Kasumi EU (KEU) ++ * ++ */ ++#define TALITOS_HAS_EU_NONE (1<<0) ++#define TALITOS_HAS_EU_AFEU (1<<1) ++#define TALITOS_HAS_EU_DEU (1<<2) ++#define TALITOS_HAS_EU_MDEU (1<<3) ++#define TALITOS_HAS_EU_RNG (1<<4) ++#define TALITOS_HAS_EU_PKEU (1<<5) ++#define TALITOS_HAS_EU_AESU (1<<6) ++#define TALITOS_HAS_EU_KEU (1<<7) ++ ++/* the corresponding masks for each SEC version */ ++#define TALITOS_HAS_EUS_SEC_1_0 0x7f ++#define TALITOS_HAS_EUS_SEC_1_2 0x4d ++#define TALITOS_HAS_EUS_SEC_2_0 0x7f ++#define TALITOS_HAS_EUS_SEC_2_01 0x7f ++#define TALITOS_HAS_EUS_SEC_2_1 0xff ++#define TALITOS_HAS_EUS_SEC_2_4 0x7f ++ ++/* ++ * descriptor-types-mask : The bitmask representing what descriptors ++ * are available. Descriptor type information should be encoded ++ * following the SEC's Descriptor Header Dword DESC_TYPE field ++ * documentation, i.e. as follows: ++ * ++ * bit 0 = set if SEC supports the aesu_ctr_nonsnoop desc. type ++ * bit 1 = set if SEC supports the ipsec_esp descriptor type ++ * bit 2 = set if SEC supports the common_nonsnoop desc. type ++ * bit 3 = set if SEC supports the 802.11i AES ccmp desc. type ++ * bit 4 = set if SEC supports the hmac_snoop_no_afeu desc. type ++ * bit 5 = set if SEC supports the srtp descriptor type ++ * bit 6 = set if SEC supports the non_hmac_snoop_no_afeu desc.type ++ * bit 7 = set if SEC supports the pkeu_assemble descriptor type ++ * bit 8 = set if SEC supports the aesu_key_expand_output desc.type ++ * bit 9 = set if SEC supports the pkeu_ptmul descriptor type ++ * bit 10 = set if SEC supports the common_nonsnoop_afeu desc. type ++ * bit 11 = set if SEC supports the pkeu_ptadd_dbl descriptor type ++ * ++ * ..and so on and so forth. ++ */ ++#define TALITOS_HAS_DT_AESU_CTR_NONSNOOP (1<<0) ++#define TALITOS_HAS_DT_IPSEC_ESP (1<<1) ++#define TALITOS_HAS_DT_COMMON_NONSNOOP (1<<2) ++ ++/* the corresponding masks for each SEC version */ ++#define TALITOS_HAS_DESCTYPES_SEC_2_0 0x01010ebf ++#define TALITOS_HAS_DESCTYPES_SEC_2_1 0x012b0ebf ++ ++/* ++ * a TALITOS_xxx_HI address points to the low data bits (32-63) of the register ++ */ ++ ++/* global register offset addresses */ ++#define TALITOS_ID 0x1020 ++#define TALITOS_ID_HI 0x1024 ++#define TALITOS_MCR 0x1030 /* master control register */ ++#define TALITOS_MCR_HI 0x1038 /* master control register */ ++#define TALITOS_MCR_SWR 0x1 ++#define TALITOS_IMR 0x1008 /* interrupt mask register */ ++#define TALITOS_IMR_ALL 0x00010fff /* enable all interrupts mask */ ++#define TALITOS_IMR_ERRONLY 0x00010aaa /* enable error interrupts */ ++#define TALITOS_IMR_HI 0x100C /* interrupt mask register */ ++#define TALITOS_IMR_HI_ALL 0x00323333 /* enable all interrupts mask */ ++#define TALITOS_IMR_HI_ERRONLY 0x00222222 /* enable error interrupts */ ++#define TALITOS_ISR 0x1010 /* interrupt status register */ ++#define TALITOS_ISR_ERROR 0x00010faa /* errors mask */ ++#define TALITOS_ISR_DONE 0x00000055 /* channel(s) done mask */ ++#define TALITOS_ISR_HI 0x1014 /* interrupt status register */ ++#define TALITOS_ICR 0x1018 /* interrupt clear register */ ++#define TALITOS_ICR_HI 0x101C /* interrupt clear register */ ++ ++/* channel register address stride */ ++#define TALITOS_CH_OFFSET 0x100 ++ ++/* channel register offset addresses and bits */ ++#define TALITOS_CH_CCCR 0x1108 /* Crypto-Channel Config Register */ ++#define TALITOS_CH_CCCR_RESET 0x1 /* Channel Reset bit */ ++#define TALITOS_CH_CCCR_HI 0x110c /* Crypto-Channel Config Register */ ++#define TALITOS_CH_CCCR_HI_CDWE 0x10 /* Channel done writeback enable bit */ ++#define TALITOS_CH_CCCR_HI_NT 0x4 /* Notification type bit */ ++#define TALITOS_CH_CCCR_HI_CDIE 0x2 /* Channel Done Interrupt Enable bit */ ++#define TALITOS_CH_CCPSR 0x1110 /* Crypto-Channel Pointer Status Reg */ ++#define TALITOS_CH_CCPSR_HI 0x1114 /* Crypto-Channel Pointer Status Reg */ ++#define TALITOS_CH_FF 0x1148 /* Fetch FIFO */ ++#define TALITOS_CH_FF_HI 0x114c /* Fetch FIFO's FETCH_ADRS */ ++#define TALITOS_CH_CDPR 0x1140 /* Crypto-Channel Pointer Status Reg */ ++#define TALITOS_CH_CDPR_HI 0x1144 /* Crypto-Channel Pointer Status Reg */ ++#define TALITOS_CH_DESCBUF 0x1180 /* (thru 11bf) Crypto-Channel ++ * Descriptor Buffer (debug) */ ++ ++/* execution unit register offset addresses and bits */ ++#define TALITOS_DEUSR 0x2028 /* DEU status register */ ++#define TALITOS_DEUSR_HI 0x202c /* DEU status register */ ++#define TALITOS_DEUISR 0x2030 /* DEU interrupt status register */ ++#define TALITOS_DEUISR_HI 0x2034 /* DEU interrupt status register */ ++#define TALITOS_DEUICR 0x2038 /* DEU interrupt control register */ ++#define TALITOS_DEUICR_HI 0x203c /* DEU interrupt control register */ ++#define TALITOS_AESUISR 0x4030 /* AESU interrupt status register */ ++#define TALITOS_AESUISR_HI 0x4034 /* AESU interrupt status register */ ++#define TALITOS_AESUICR 0x4038 /* AESU interrupt control register */ ++#define TALITOS_AESUICR_HI 0x403c /* AESU interrupt control register */ ++#define TALITOS_MDEUISR 0x6030 /* MDEU interrupt status register */ ++#define TALITOS_MDEUISR_HI 0x6034 /* MDEU interrupt status register */ ++#define TALITOS_RNGSR 0xa028 /* RNG status register */ ++#define TALITOS_RNGSR_HI 0xa02c /* RNG status register */ ++#define TALITOS_RNGSR_HI_RD 0x1 /* RNG Reset done */ ++#define TALITOS_RNGSR_HI_OFL 0xff0000/* number of dwords in RNG output FIFO*/ ++#define TALITOS_RNGDSR 0xa010 /* RNG data size register */ ++#define TALITOS_RNGDSR_HI 0xa014 /* RNG data size register */ ++#define TALITOS_RNG_FIFO 0xa800 /* RNG FIFO - pool of random numbers */ ++#define TALITOS_RNGISR 0xa030 /* RNG Interrupt status register */ ++#define TALITOS_RNGISR_HI 0xa034 /* RNG Interrupt status register */ ++#define TALITOS_RNGRCR 0xa018 /* RNG Reset control register */ ++#define TALITOS_RNGRCR_HI 0xa01c /* RNG Reset control register */ ++#define TALITOS_RNGRCR_HI_SR 0x1 /* RNG RNGRCR:Software Reset */ ++ ++/* descriptor pointer entry */ ++struct talitos_desc_ptr { ++ u16 len; /* length */ ++ u8 extent; /* jump (to s/g link table) and extent */ ++ u8 res; /* reserved */ ++ u32 ptr; /* pointer */ ++}; ++ ++/* descriptor */ ++struct talitos_desc { ++ u32 hdr; /* header */ ++ u32 res; /* reserved */ ++ struct talitos_desc_ptr ptr[7]; /* ptr/len pair array */ ++}; ++ ++/* talitos descriptor header (hdr) bits */ ++ ++/* primary execution unit select */ ++#define TALITOS_SEL0_AFEU 0x10000000 ++#define TALITOS_SEL0_DEU 0x20000000 ++#define TALITOS_SEL0_MDEU 0x30000000 ++#define TALITOS_SEL0_RNG 0x40000000 ++#define TALITOS_SEL0_PKEU 0x50000000 ++#define TALITOS_SEL0_AESU 0x60000000 ++ ++/* primary execution unit mode (MODE0) and derivatives */ ++#define TALITOS_MODE0_AESU_CBC 0x00200000 ++#define TALITOS_MODE0_AESU_ENC 0x00100000 ++#define TALITOS_MODE0_DEU_CBC 0x00400000 ++#define TALITOS_MODE0_DEU_3DES 0x00200000 ++#define TALITOS_MODE0_DEU_ENC 0x00100000 ++#define TALITOS_MODE0_MDEU_INIT 0x01000000 /* init starting regs */ ++#define TALITOS_MODE0_MDEU_HMAC 0x00800000 ++#define TALITOS_MODE0_MDEU_PAD 0x00400000 /* PD */ ++#define TALITOS_MODE0_MDEU_MD5 0x00200000 ++#define TALITOS_MODE0_MDEU_SHA256 0x00100000 ++#define TALITOS_MODE0_MDEU_SHA1 0x00000000 /* SHA-160 */ ++#define TALITOS_MODE0_MDEU_MD5_HMAC \ ++ (TALITOS_MODE0_MDEU_MD5 | TALITOS_MODE0_MDEU_HMAC) ++#define TALITOS_MODE0_MDEU_SHA256_HMAC \ ++ (TALITOS_MODE0_MDEU_SHA256 | TALITOS_MODE0_MDEU_HMAC) ++#define TALITOS_MODE0_MDEU_SHA1_HMAC \ ++ (TALITOS_MODE0_MDEU_SHA1 | TALITOS_MODE0_MDEU_HMAC) ++ ++/* secondary execution unit select (SEL1) */ ++/* it's MDEU or nothing */ ++#define TALITOS_SEL1_MDEU 0x00030000 ++ ++/* secondary execution unit mode (MODE1) and derivatives */ ++#define TALITOS_MODE1_MDEU_INIT 0x00001000 /* init starting regs */ ++#define TALITOS_MODE1_MDEU_HMAC 0x00000800 ++#define TALITOS_MODE1_MDEU_PAD 0x00000400 /* PD */ ++#define TALITOS_MODE1_MDEU_MD5 0x00000200 ++#define TALITOS_MODE1_MDEU_SHA256 0x00000100 ++#define TALITOS_MODE1_MDEU_SHA1 0x00000000 /* SHA-160 */ ++#define TALITOS_MODE1_MDEU_MD5_HMAC \ ++ (TALITOS_MODE1_MDEU_MD5 | TALITOS_MODE1_MDEU_HMAC) ++#define TALITOS_MODE1_MDEU_SHA256_HMAC \ ++ (TALITOS_MODE1_MDEU_SHA256 | TALITOS_MODE1_MDEU_HMAC) ++#define TALITOS_MODE1_MDEU_SHA1_HMAC \ ++ (TALITOS_MODE1_MDEU_SHA1 | TALITOS_MODE1_MDEU_HMAC) ++ ++/* direction of overall data flow (DIR) */ ++#define TALITOS_DIR_OUTBOUND 0x00000000 ++#define TALITOS_DIR_INBOUND 0x00000002 ++ ++/* done notification (DN) */ ++#define TALITOS_DONE_NOTIFY 0x00000001 ++ ++/* descriptor types */ ++/* odd numbers here are valid on SEC2 and greater only (e.g. ipsec_esp) */ ++#define TD_TYPE_AESU_CTR_NONSNOOP (0 << 3) ++#define TD_TYPE_IPSEC_ESP (1 << 3) ++#define TD_TYPE_COMMON_NONSNOOP_NO_AFEU (2 << 3) ++#define TD_TYPE_HMAC_SNOOP_NO_AFEU (4 << 3) ++ ++#define TALITOS_HDR_DONE_BITS 0xff000000 ++ ++#define DPRINTF(a...) do { \ ++ if (debug) { \ ++ printk("%s: ", sc ? \ ++ device_get_nameunit(sc->sc_cdev) : "talitos"); \ ++ printk(a); \ ++ } \ ++ } while (0) +diff -Nur linux-3.0.4.orig/crypto/ocf/talitos/talitos_soft.h linux-3.0.4/crypto/ocf/talitos/talitos_soft.h +--- linux-3.0.4.orig/crypto/ocf/talitos/talitos_soft.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/talitos/talitos_soft.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,76 @@ ++/* ++ * Freescale SEC data structures for integration with ocf-linux ++ * ++ * Copyright (c) 2006 Freescale Semiconductor, Inc. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++/* ++ * paired descriptor and associated crypto operation ++ */ ++struct desc_cryptop_pair { ++ struct talitos_desc cf_desc; /* descriptor ptr */ ++ struct cryptop *cf_crp; /* cryptop ptr */ ++}; ++ ++/* ++ * Holds data specific to a single talitos device. ++ */ ++struct talitos_softc { ++ softc_device_decl sc_cdev; ++ struct platform_device *sc_dev; /* device backpointer */ ++ ocf_iomem_t sc_base_addr; ++ int sc_irq; ++ int sc_num; /* if we have multiple chips */ ++ int32_t sc_cid; /* crypto tag */ ++ u64 sc_chiprev; /* major/minor chip revision */ ++ int sc_nsessions; ++ struct talitos_session *sc_sessions; ++ int sc_num_channels;/* number of crypto channels */ ++ int sc_chfifo_len; /* channel fetch fifo len */ ++ int sc_exec_units; /* execution units mask */ ++ int sc_desc_types; /* descriptor types mask */ ++ /* ++ * mutual exclusion for intra-channel resources, e.g. fetch fifos ++ * the last entry is a meta-channel lock used by the channel scheduler ++ */ ++ spinlock_t *sc_chnfifolock; ++ /* sc_chnlastalgo contains last algorithm for that channel */ ++ int *sc_chnlastalg; ++ /* sc_chnfifo holds pending descriptor--crypto operation pairs */ ++ struct desc_cryptop_pair **sc_chnfifo; ++}; ++ ++struct talitos_session { ++ u_int32_t ses_used; ++ u_int32_t ses_klen; /* key length in bits */ ++ u_int32_t ses_key[8]; /* DES/3DES/AES key */ ++ u_int32_t ses_hmac[5]; /* hmac inner state */ ++ u_int32_t ses_hmac_len; /* hmac length */ ++ u_int32_t ses_mlen; /* desired hash result len (12=ipsec or 16) */ ++}; ++ ++#define TALITOS_SESSION(sid) ((sid) & 0x0fffffff) ++#define TALITOS_SID(crd, sesn) (((crd) << 28) | ((sesn) & 0x0fffffff)) +diff -Nur linux-3.0.4.orig/crypto/ocf/ubsec_ssb/Makefile linux-3.0.4/crypto/ocf/ubsec_ssb/Makefile +--- linux-3.0.4.orig/crypto/ocf/ubsec_ssb/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/ubsec_ssb/Makefile 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,12 @@ ++# for SGlinux builds ++-include $(ROOTDIR)/modules/.config ++ ++obj-$(CONFIG_OCF_UBSEC_SSB) += ubsec_ssb.o ++ ++obj ?= . ++EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ ++ ++ifdef TOPDIR ++-include $(TOPDIR)/Rules.make ++endif ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/ubsec_ssb/bsdqueue.h linux-3.0.4/crypto/ocf/ubsec_ssb/bsdqueue.h +--- linux-3.0.4.orig/crypto/ocf/ubsec_ssb/bsdqueue.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/ubsec_ssb/bsdqueue.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,527 @@ ++/* $OpenBSD: queue.h,v 1.32 2007/04/30 18:42:34 pedro Exp $ */ ++/* $NetBSD: queue.h,v 1.11 1996/05/16 05:17:14 mycroft Exp $ */ ++ ++/* ++ * Copyright (c) 1991, 1993 ++ * The Regents of the University of California. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. Neither the name of the University nor the names of its contributors ++ * may be used to endorse or promote products derived from this software ++ * without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE ++ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ++ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ++ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF ++ * SUCH DAMAGE. ++ * ++ * @(#)queue.h 8.5 (Berkeley) 8/20/94 ++ */ ++ ++#ifndef _BSD_SYS_QUEUE_H_ ++#define _BSD_SYS_QUEUE_H_ ++ ++/* ++ * This file defines five types of data structures: singly-linked lists, ++ * lists, simple queues, tail queues, and circular queues. ++ * ++ * ++ * A singly-linked list is headed by a single forward pointer. The elements ++ * are singly linked for minimum space and pointer manipulation overhead at ++ * the expense of O(n) removal for arbitrary elements. New elements can be ++ * added to the list after an existing element or at the head of the list. ++ * Elements being removed from the head of the list should use the explicit ++ * macro for this purpose for optimum efficiency. A singly-linked list may ++ * only be traversed in the forward direction. Singly-linked lists are ideal ++ * for applications with large datasets and few or no removals or for ++ * implementing a LIFO queue. ++ * ++ * A list is headed by a single forward pointer (or an array of forward ++ * pointers for a hash table header). The elements are doubly linked ++ * so that an arbitrary element can be removed without a need to ++ * traverse the list. New elements can be added to the list before ++ * or after an existing element or at the head of the list. A list ++ * may only be traversed in the forward direction. ++ * ++ * A simple queue is headed by a pair of pointers, one the head of the ++ * list and the other to the tail of the list. The elements are singly ++ * linked to save space, so elements can only be removed from the ++ * head of the list. New elements can be added to the list before or after ++ * an existing element, at the head of the list, or at the end of the ++ * list. A simple queue may only be traversed in the forward direction. ++ * ++ * A tail queue is headed by a pair of pointers, one to the head of the ++ * list and the other to the tail of the list. The elements are doubly ++ * linked so that an arbitrary element can be removed without a need to ++ * traverse the list. New elements can be added to the list before or ++ * after an existing element, at the head of the list, or at the end of ++ * the list. A tail queue may be traversed in either direction. ++ * ++ * A circle queue is headed by a pair of pointers, one to the head of the ++ * list and the other to the tail of the list. The elements are doubly ++ * linked so that an arbitrary element can be removed without a need to ++ * traverse the list. New elements can be added to the list before or after ++ * an existing element, at the head of the list, or at the end of the list. ++ * A circle queue may be traversed in either direction, but has a more ++ * complex end of list detection. ++ * ++ * For details on the use of these macros, see the queue(3) manual page. ++ */ ++ ++#if defined(QUEUE_MACRO_DEBUG) || (defined(_KERNEL) && defined(DIAGNOSTIC)) ++#define _Q_INVALIDATE(a) (a) = ((void *)-1) ++#else ++#define _Q_INVALIDATE(a) ++#endif ++ ++/* ++ * Singly-linked List definitions. ++ */ ++#define BSD_SLIST_HEAD(name, type) \ ++struct name { \ ++ struct type *slh_first; /* first element */ \ ++} ++ ++#define BSD_SLIST_HEAD_INITIALIZER(head) \ ++ { NULL } ++ ++#define BSD_SLIST_ENTRY(type) \ ++struct { \ ++ struct type *sle_next; /* next element */ \ ++} ++ ++/* ++ * Singly-linked List access methods. ++ */ ++#define BSD_SLIST_FIRST(head) ((head)->slh_first) ++#define BSD_SLIST_END(head) NULL ++#define BSD_SLIST_EMPTY(head) (BSD_SLIST_FIRST(head) == BSD_SLIST_END(head)) ++#define BSD_SLIST_NEXT(elm, field) ((elm)->field.sle_next) ++ ++#define BSD_SLIST_FOREACH(var, head, field) \ ++ for((var) = BSD_SLIST_FIRST(head); \ ++ (var) != BSD_SLIST_END(head); \ ++ (var) = BSD_SLIST_NEXT(var, field)) ++ ++#define BSD_SLIST_FOREACH_PREVPTR(var, varp, head, field) \ ++ for ((varp) = &BSD_SLIST_FIRST((head)); \ ++ ((var) = *(varp)) != BSD_SLIST_END(head); \ ++ (varp) = &BSD_SLIST_NEXT((var), field)) ++ ++/* ++ * Singly-linked List functions. ++ */ ++#define BSD_SLIST_INIT(head) { \ ++ BSD_SLIST_FIRST(head) = BSD_SLIST_END(head); \ ++} ++ ++#define BSD_SLIST_INSERT_AFTER(slistelm, elm, field) do { \ ++ (elm)->field.sle_next = (slistelm)->field.sle_next; \ ++ (slistelm)->field.sle_next = (elm); \ ++} while (0) ++ ++#define BSD_SLIST_INSERT_HEAD(head, elm, field) do { \ ++ (elm)->field.sle_next = (head)->slh_first; \ ++ (head)->slh_first = (elm); \ ++} while (0) ++ ++#define BSD_SLIST_REMOVE_NEXT(head, elm, field) do { \ ++ (elm)->field.sle_next = (elm)->field.sle_next->field.sle_next; \ ++} while (0) ++ ++#define BSD_SLIST_REMOVE_HEAD(head, field) do { \ ++ (head)->slh_first = (head)->slh_first->field.sle_next; \ ++} while (0) ++ ++#define BSD_SLIST_REMOVE(head, elm, type, field) do { \ ++ if ((head)->slh_first == (elm)) { \ ++ BSD_SLIST_REMOVE_HEAD((head), field); \ ++ } else { \ ++ struct type *curelm = (head)->slh_first; \ ++ \ ++ while (curelm->field.sle_next != (elm)) \ ++ curelm = curelm->field.sle_next; \ ++ curelm->field.sle_next = \ ++ curelm->field.sle_next->field.sle_next; \ ++ _Q_INVALIDATE((elm)->field.sle_next); \ ++ } \ ++} while (0) ++ ++/* ++ * List definitions. ++ */ ++#define BSD_LIST_HEAD(name, type) \ ++struct name { \ ++ struct type *lh_first; /* first element */ \ ++} ++ ++#define BSD_LIST_HEAD_INITIALIZER(head) \ ++ { NULL } ++ ++#define BSD_LIST_ENTRY(type) \ ++struct { \ ++ struct type *le_next; /* next element */ \ ++ struct type **le_prev; /* address of previous next element */ \ ++} ++ ++/* ++ * List access methods ++ */ ++#define BSD_LIST_FIRST(head) ((head)->lh_first) ++#define BSD_LIST_END(head) NULL ++#define BSD_LIST_EMPTY(head) (BSD_LIST_FIRST(head) == BSD_LIST_END(head)) ++#define BSD_LIST_NEXT(elm, field) ((elm)->field.le_next) ++ ++#define BSD_LIST_FOREACH(var, head, field) \ ++ for((var) = BSD_LIST_FIRST(head); \ ++ (var)!= BSD_LIST_END(head); \ ++ (var) = BSD_LIST_NEXT(var, field)) ++ ++/* ++ * List functions. ++ */ ++#define BSD_LIST_INIT(head) do { \ ++ BSD_LIST_FIRST(head) = BSD_LIST_END(head); \ ++} while (0) ++ ++#define BSD_LIST_INSERT_AFTER(listelm, elm, field) do { \ ++ if (((elm)->field.le_next = (listelm)->field.le_next) != NULL) \ ++ (listelm)->field.le_next->field.le_prev = \ ++ &(elm)->field.le_next; \ ++ (listelm)->field.le_next = (elm); \ ++ (elm)->field.le_prev = &(listelm)->field.le_next; \ ++} while (0) ++ ++#define BSD_LIST_INSERT_BEFORE(listelm, elm, field) do { \ ++ (elm)->field.le_prev = (listelm)->field.le_prev; \ ++ (elm)->field.le_next = (listelm); \ ++ *(listelm)->field.le_prev = (elm); \ ++ (listelm)->field.le_prev = &(elm)->field.le_next; \ ++} while (0) ++ ++#define BSD_LIST_INSERT_HEAD(head, elm, field) do { \ ++ if (((elm)->field.le_next = (head)->lh_first) != NULL) \ ++ (head)->lh_first->field.le_prev = &(elm)->field.le_next;\ ++ (head)->lh_first = (elm); \ ++ (elm)->field.le_prev = &(head)->lh_first; \ ++} while (0) ++ ++#define BSD_LIST_REMOVE(elm, field) do { \ ++ if ((elm)->field.le_next != NULL) \ ++ (elm)->field.le_next->field.le_prev = \ ++ (elm)->field.le_prev; \ ++ *(elm)->field.le_prev = (elm)->field.le_next; \ ++ _Q_INVALIDATE((elm)->field.le_prev); \ ++ _Q_INVALIDATE((elm)->field.le_next); \ ++} while (0) ++ ++#define BSD_LIST_REPLACE(elm, elm2, field) do { \ ++ if (((elm2)->field.le_next = (elm)->field.le_next) != NULL) \ ++ (elm2)->field.le_next->field.le_prev = \ ++ &(elm2)->field.le_next; \ ++ (elm2)->field.le_prev = (elm)->field.le_prev; \ ++ *(elm2)->field.le_prev = (elm2); \ ++ _Q_INVALIDATE((elm)->field.le_prev); \ ++ _Q_INVALIDATE((elm)->field.le_next); \ ++} while (0) ++ ++/* ++ * Simple queue definitions. ++ */ ++#define BSD_SIMPLEQ_HEAD(name, type) \ ++struct name { \ ++ struct type *sqh_first; /* first element */ \ ++ struct type **sqh_last; /* addr of last next element */ \ ++} ++ ++#define BSD_SIMPLEQ_HEAD_INITIALIZER(head) \ ++ { NULL, &(head).sqh_first } ++ ++#define BSD_SIMPLEQ_ENTRY(type) \ ++struct { \ ++ struct type *sqe_next; /* next element */ \ ++} ++ ++/* ++ * Simple queue access methods. ++ */ ++#define BSD_SIMPLEQ_FIRST(head) ((head)->sqh_first) ++#define BSD_SIMPLEQ_END(head) NULL ++#define BSD_SIMPLEQ_EMPTY(head) (BSD_SIMPLEQ_FIRST(head) == BSD_SIMPLEQ_END(head)) ++#define BSD_SIMPLEQ_NEXT(elm, field) ((elm)->field.sqe_next) ++ ++#define BSD_SIMPLEQ_FOREACH(var, head, field) \ ++ for((var) = BSD_SIMPLEQ_FIRST(head); \ ++ (var) != BSD_SIMPLEQ_END(head); \ ++ (var) = BSD_SIMPLEQ_NEXT(var, field)) ++ ++/* ++ * Simple queue functions. ++ */ ++#define BSD_SIMPLEQ_INIT(head) do { \ ++ (head)->sqh_first = NULL; \ ++ (head)->sqh_last = &(head)->sqh_first; \ ++} while (0) ++ ++#define BSD_SIMPLEQ_INSERT_HEAD(head, elm, field) do { \ ++ if (((elm)->field.sqe_next = (head)->sqh_first) == NULL) \ ++ (head)->sqh_last = &(elm)->field.sqe_next; \ ++ (head)->sqh_first = (elm); \ ++} while (0) ++ ++#define BSD_SIMPLEQ_INSERT_TAIL(head, elm, field) do { \ ++ (elm)->field.sqe_next = NULL; \ ++ *(head)->sqh_last = (elm); \ ++ (head)->sqh_last = &(elm)->field.sqe_next; \ ++} while (0) ++ ++#define BSD_SIMPLEQ_INSERT_AFTER(head, listelm, elm, field) do { \ ++ if (((elm)->field.sqe_next = (listelm)->field.sqe_next) == NULL)\ ++ (head)->sqh_last = &(elm)->field.sqe_next; \ ++ (listelm)->field.sqe_next = (elm); \ ++} while (0) ++ ++#define BSD_SIMPLEQ_REMOVE_HEAD(head, field) do { \ ++ if (((head)->sqh_first = (head)->sqh_first->field.sqe_next) == NULL) \ ++ (head)->sqh_last = &(head)->sqh_first; \ ++} while (0) ++ ++/* ++ * Tail queue definitions. ++ */ ++#define BSD_TAILQ_HEAD(name, type) \ ++struct name { \ ++ struct type *tqh_first; /* first element */ \ ++ struct type **tqh_last; /* addr of last next element */ \ ++} ++ ++#define BSD_TAILQ_HEAD_INITIALIZER(head) \ ++ { NULL, &(head).tqh_first } ++ ++#define BSD_TAILQ_ENTRY(type) \ ++struct { \ ++ struct type *tqe_next; /* next element */ \ ++ struct type **tqe_prev; /* address of previous next element */ \ ++} ++ ++/* ++ * tail queue access methods ++ */ ++#define BSD_TAILQ_FIRST(head) ((head)->tqh_first) ++#define BSD_TAILQ_END(head) NULL ++#define BSD_TAILQ_NEXT(elm, field) ((elm)->field.tqe_next) ++#define BSD_TAILQ_LAST(head, headname) \ ++ (*(((struct headname *)((head)->tqh_last))->tqh_last)) ++/* XXX */ ++#define BSD_TAILQ_PREV(elm, headname, field) \ ++ (*(((struct headname *)((elm)->field.tqe_prev))->tqh_last)) ++#define BSD_TAILQ_EMPTY(head) \ ++ (BSD_TAILQ_FIRST(head) == BSD_TAILQ_END(head)) ++ ++#define BSD_TAILQ_FOREACH(var, head, field) \ ++ for((var) = BSD_TAILQ_FIRST(head); \ ++ (var) != BSD_TAILQ_END(head); \ ++ (var) = BSD_TAILQ_NEXT(var, field)) ++ ++#define BSD_TAILQ_FOREACH_REVERSE(var, head, headname, field) \ ++ for((var) = BSD_TAILQ_LAST(head, headname); \ ++ (var) != BSD_TAILQ_END(head); \ ++ (var) = BSD_TAILQ_PREV(var, headname, field)) ++ ++/* ++ * Tail queue functions. ++ */ ++#define BSD_TAILQ_INIT(head) do { \ ++ (head)->tqh_first = NULL; \ ++ (head)->tqh_last = &(head)->tqh_first; \ ++} while (0) ++ ++#define BSD_TAILQ_INSERT_HEAD(head, elm, field) do { \ ++ if (((elm)->field.tqe_next = (head)->tqh_first) != NULL) \ ++ (head)->tqh_first->field.tqe_prev = \ ++ &(elm)->field.tqe_next; \ ++ else \ ++ (head)->tqh_last = &(elm)->field.tqe_next; \ ++ (head)->tqh_first = (elm); \ ++ (elm)->field.tqe_prev = &(head)->tqh_first; \ ++} while (0) ++ ++#define BSD_TAILQ_INSERT_TAIL(head, elm, field) do { \ ++ (elm)->field.tqe_next = NULL; \ ++ (elm)->field.tqe_prev = (head)->tqh_last; \ ++ *(head)->tqh_last = (elm); \ ++ (head)->tqh_last = &(elm)->field.tqe_next; \ ++} while (0) ++ ++#define BSD_TAILQ_INSERT_AFTER(head, listelm, elm, field) do { \ ++ if (((elm)->field.tqe_next = (listelm)->field.tqe_next) != NULL)\ ++ (elm)->field.tqe_next->field.tqe_prev = \ ++ &(elm)->field.tqe_next; \ ++ else \ ++ (head)->tqh_last = &(elm)->field.tqe_next; \ ++ (listelm)->field.tqe_next = (elm); \ ++ (elm)->field.tqe_prev = &(listelm)->field.tqe_next; \ ++} while (0) ++ ++#define BSD_TAILQ_INSERT_BEFORE(listelm, elm, field) do { \ ++ (elm)->field.tqe_prev = (listelm)->field.tqe_prev; \ ++ (elm)->field.tqe_next = (listelm); \ ++ *(listelm)->field.tqe_prev = (elm); \ ++ (listelm)->field.tqe_prev = &(elm)->field.tqe_next; \ ++} while (0) ++ ++#define BSD_TAILQ_REMOVE(head, elm, field) do { \ ++ if (((elm)->field.tqe_next) != NULL) \ ++ (elm)->field.tqe_next->field.tqe_prev = \ ++ (elm)->field.tqe_prev; \ ++ else \ ++ (head)->tqh_last = (elm)->field.tqe_prev; \ ++ *(elm)->field.tqe_prev = (elm)->field.tqe_next; \ ++ _Q_INVALIDATE((elm)->field.tqe_prev); \ ++ _Q_INVALIDATE((elm)->field.tqe_next); \ ++} while (0) ++ ++#define BSD_TAILQ_REPLACE(head, elm, elm2, field) do { \ ++ if (((elm2)->field.tqe_next = (elm)->field.tqe_next) != NULL) \ ++ (elm2)->field.tqe_next->field.tqe_prev = \ ++ &(elm2)->field.tqe_next; \ ++ else \ ++ (head)->tqh_last = &(elm2)->field.tqe_next; \ ++ (elm2)->field.tqe_prev = (elm)->field.tqe_prev; \ ++ *(elm2)->field.tqe_prev = (elm2); \ ++ _Q_INVALIDATE((elm)->field.tqe_prev); \ ++ _Q_INVALIDATE((elm)->field.tqe_next); \ ++} while (0) ++ ++/* ++ * Circular queue definitions. ++ */ ++#define BSD_CIRCLEQ_HEAD(name, type) \ ++struct name { \ ++ struct type *cqh_first; /* first element */ \ ++ struct type *cqh_last; /* last element */ \ ++} ++ ++#define BSD_CIRCLEQ_HEAD_INITIALIZER(head) \ ++ { BSD_CIRCLEQ_END(&head), BSD_CIRCLEQ_END(&head) } ++ ++#define BSD_CIRCLEQ_ENTRY(type) \ ++struct { \ ++ struct type *cqe_next; /* next element */ \ ++ struct type *cqe_prev; /* previous element */ \ ++} ++ ++/* ++ * Circular queue access methods ++ */ ++#define BSD_CIRCLEQ_FIRST(head) ((head)->cqh_first) ++#define BSD_CIRCLEQ_LAST(head) ((head)->cqh_last) ++#define BSD_CIRCLEQ_END(head) ((void *)(head)) ++#define BSD_CIRCLEQ_NEXT(elm, field) ((elm)->field.cqe_next) ++#define BSD_CIRCLEQ_PREV(elm, field) ((elm)->field.cqe_prev) ++#define BSD_CIRCLEQ_EMPTY(head) \ ++ (BSD_CIRCLEQ_FIRST(head) == BSD_CIRCLEQ_END(head)) ++ ++#define BSD_CIRCLEQ_FOREACH(var, head, field) \ ++ for((var) = BSD_CIRCLEQ_FIRST(head); \ ++ (var) != BSD_CIRCLEQ_END(head); \ ++ (var) = BSD_CIRCLEQ_NEXT(var, field)) ++ ++#define BSD_CIRCLEQ_FOREACH_REVERSE(var, head, field) \ ++ for((var) = BSD_CIRCLEQ_LAST(head); \ ++ (var) != BSD_CIRCLEQ_END(head); \ ++ (var) = BSD_CIRCLEQ_PREV(var, field)) ++ ++/* ++ * Circular queue functions. ++ */ ++#define BSD_CIRCLEQ_INIT(head) do { \ ++ (head)->cqh_first = BSD_CIRCLEQ_END(head); \ ++ (head)->cqh_last = BSD_CIRCLEQ_END(head); \ ++} while (0) ++ ++#define BSD_CIRCLEQ_INSERT_AFTER(head, listelm, elm, field) do { \ ++ (elm)->field.cqe_next = (listelm)->field.cqe_next; \ ++ (elm)->field.cqe_prev = (listelm); \ ++ if ((listelm)->field.cqe_next == BSD_CIRCLEQ_END(head)) \ ++ (head)->cqh_last = (elm); \ ++ else \ ++ (listelm)->field.cqe_next->field.cqe_prev = (elm); \ ++ (listelm)->field.cqe_next = (elm); \ ++} while (0) ++ ++#define BSD_CIRCLEQ_INSERT_BEFORE(head, listelm, elm, field) do { \ ++ (elm)->field.cqe_next = (listelm); \ ++ (elm)->field.cqe_prev = (listelm)->field.cqe_prev; \ ++ if ((listelm)->field.cqe_prev == BSD_CIRCLEQ_END(head)) \ ++ (head)->cqh_first = (elm); \ ++ else \ ++ (listelm)->field.cqe_prev->field.cqe_next = (elm); \ ++ (listelm)->field.cqe_prev = (elm); \ ++} while (0) ++ ++#define BSD_CIRCLEQ_INSERT_HEAD(head, elm, field) do { \ ++ (elm)->field.cqe_next = (head)->cqh_first; \ ++ (elm)->field.cqe_prev = BSD_CIRCLEQ_END(head); \ ++ if ((head)->cqh_last == BSD_CIRCLEQ_END(head)) \ ++ (head)->cqh_last = (elm); \ ++ else \ ++ (head)->cqh_first->field.cqe_prev = (elm); \ ++ (head)->cqh_first = (elm); \ ++} while (0) ++ ++#define BSD_CIRCLEQ_INSERT_TAIL(head, elm, field) do { \ ++ (elm)->field.cqe_next = BSD_CIRCLEQ_END(head); \ ++ (elm)->field.cqe_prev = (head)->cqh_last; \ ++ if ((head)->cqh_first == BSD_CIRCLEQ_END(head)) \ ++ (head)->cqh_first = (elm); \ ++ else \ ++ (head)->cqh_last->field.cqe_next = (elm); \ ++ (head)->cqh_last = (elm); \ ++} while (0) ++ ++#define BSD_CIRCLEQ_REMOVE(head, elm, field) do { \ ++ if ((elm)->field.cqe_next == BSD_CIRCLEQ_END(head)) \ ++ (head)->cqh_last = (elm)->field.cqe_prev; \ ++ else \ ++ (elm)->field.cqe_next->field.cqe_prev = \ ++ (elm)->field.cqe_prev; \ ++ if ((elm)->field.cqe_prev == BSD_CIRCLEQ_END(head)) \ ++ (head)->cqh_first = (elm)->field.cqe_next; \ ++ else \ ++ (elm)->field.cqe_prev->field.cqe_next = \ ++ (elm)->field.cqe_next; \ ++ _Q_INVALIDATE((elm)->field.cqe_prev); \ ++ _Q_INVALIDATE((elm)->field.cqe_next); \ ++} while (0) ++ ++#define BSD_CIRCLEQ_REPLACE(head, elm, elm2, field) do { \ ++ if (((elm2)->field.cqe_next = (elm)->field.cqe_next) == \ ++ BSD_CIRCLEQ_END(head)) \ ++ (head).cqh_last = (elm2); \ ++ else \ ++ (elm2)->field.cqe_next->field.cqe_prev = (elm2); \ ++ if (((elm2)->field.cqe_prev = (elm)->field.cqe_prev) == \ ++ BSD_CIRCLEQ_END(head)) \ ++ (head).cqh_first = (elm2); \ ++ else \ ++ (elm2)->field.cqe_prev->field.cqe_next = (elm2); \ ++ _Q_INVALIDATE((elm)->field.cqe_prev); \ ++ _Q_INVALIDATE((elm)->field.cqe_next); \ ++} while (0) ++ ++#endif /* !_BSD_SYS_QUEUE_H_ */ +diff -Nur linux-3.0.4.orig/crypto/ocf/ubsec_ssb/ubsec_ssb.c linux-3.0.4/crypto/ocf/ubsec_ssb/ubsec_ssb.c +--- linux-3.0.4.orig/crypto/ocf/ubsec_ssb/ubsec_ssb.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/ubsec_ssb/ubsec_ssb.c 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,2220 @@ ++ ++/* ++ * Copyright (c) 2008 Daniel Mueller (daniel@danm.de) ++ * Copyright (c) 2007 David McCullough (david_mccullough@securecomputing.com) ++ * Copyright (c) 2000 Jason L. Wright (jason@thought.net) ++ * Copyright (c) 2000 Theo de Raadt (deraadt@openbsd.org) ++ * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com) ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++ * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, ++ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ++ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored in part by the Defense Advanced Research Projects ++ * Agency (DARPA) and Air Force Research Laboratory, Air Force ++ * Materiel Command, USAF, under agreement number F30602-01-2-0537. ++ * ++ */ ++#undef UBSEC_DEBUG ++#undef UBSEC_VERBOSE_DEBUG ++ ++#ifdef UBSEC_VERBOSE_DEBUG ++#define UBSEC_DEBUG ++#endif ++ ++/* ++ * uBsec BCM5365 hardware crypto accelerator ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++/* ++ * BSD queue ++ */ ++//#include "bsdqueue.h" ++ ++/* ++ * OCF ++ */ ++#include ++#include ++ ++#define HMAC_HACK 1 ++ ++#define HMAC_HACK 1 ++#ifdef HMAC_HACK ++#include ++#include ++#include ++#include ++#include ++#endif ++ ++#include "bsdqueue.h" ++#include "ubsecreg.h" ++#include "ubsecvar.h" ++ ++#define DRV_MODULE_NAME "ubsec_ssb" ++#define PFX DRV_MODULE_NAME ": " ++#define DRV_MODULE_VERSION "0.02" ++#define DRV_MODULE_RELDATE "Feb 21, 2009" ++ ++#if 1 ++#define DPRINTF(a...) \ ++ if (debug) \ ++ { \ ++ printk(DRV_MODULE_NAME ": " a); \ ++ } ++#else ++#define DPRINTF(a...) ++#endif ++ ++/* ++ * Prototypes ++ */ ++static irqreturn_t ubsec_ssb_isr(int, void *, struct pt_regs *); ++static int __devinit ubsec_ssb_probe(struct ssb_device *sdev, ++ const struct ssb_device_id *ent); ++static void __devexit ubsec_ssb_remove(struct ssb_device *sdev); ++int ubsec_attach(struct ssb_device *sdev, const struct ssb_device_id *ent, ++ struct device *self); ++static void ubsec_setup_mackey(struct ubsec_session *ses, int algo, ++ caddr_t key, int klen); ++static int dma_map_skb(struct ubsec_softc *sc, ++ struct ubsec_dma_alloc* q_map, struct sk_buff *skb, int *mlen); ++static int dma_map_uio(struct ubsec_softc *sc, ++ struct ubsec_dma_alloc *q_map, struct uio *uio, int *mlen); ++static void dma_unmap(struct ubsec_softc *sc, ++ struct ubsec_dma_alloc *q_map, int mlen); ++static int ubsec_dmamap_aligned(struct ubsec_softc *sc, ++ const struct ubsec_dma_alloc *q_map, int mlen); ++ ++#ifdef UBSEC_DEBUG ++static int proc_read(char *buf, char **start, off_t offset, ++ int size, int *peof, void *data); ++#endif ++ ++void ubsec_reset_board(struct ubsec_softc *); ++void ubsec_init_board(struct ubsec_softc *); ++void ubsec_cleanchip(struct ubsec_softc *); ++void ubsec_totalreset(struct ubsec_softc *); ++int ubsec_free_q(struct ubsec_softc*, struct ubsec_q *); ++ ++static int ubsec_newsession(device_t, u_int32_t *, struct cryptoini *); ++static int ubsec_freesession(device_t, u_int64_t); ++static int ubsec_process(device_t, struct cryptop *, int); ++ ++void ubsec_callback(struct ubsec_softc *, struct ubsec_q *); ++void ubsec_feed(struct ubsec_softc *); ++void ubsec_mcopy(struct sk_buff *, struct sk_buff *, int, int); ++void ubsec_dma_free(struct ubsec_softc *, struct ubsec_dma_alloc *); ++int ubsec_dma_malloc(struct ubsec_softc *, struct ubsec_dma_alloc *, ++ size_t, int); ++ ++/* DEBUG crap... */ ++void ubsec_dump_pb(struct ubsec_pktbuf *); ++void ubsec_dump_mcr(struct ubsec_mcr *); ++ ++#define READ_REG(sc,r) \ ++ ssb_read32((sc)->sdev, (r)); ++#define WRITE_REG(sc,r,val) \ ++ ssb_write32((sc)->sdev, (r), (val)); ++#define READ_REG_SDEV(sdev,r) \ ++ ssb_read32((sdev), (r)); ++#define WRITE_REG_SDEV(sdev,r,val) \ ++ ssb_write32((sdev), (r), (val)); ++ ++#define SWAP32(x) (x) = htole32(ntohl((x))) ++#define HTOLE32(x) (x) = htole32(x) ++ ++#ifdef __LITTLE_ENDIAN ++#define letoh16(x) (x) ++#define letoh32(x) (x) ++#endif ++ ++static int debug; ++module_param(debug, int, 0644); ++MODULE_PARM_DESC(debug, "Enable debug output"); ++ ++#define UBSEC_SSB_MAX_CHIPS 1 ++static struct ubsec_softc *ubsec_chip_idx[UBSEC_SSB_MAX_CHIPS]; ++static struct ubsec_stats ubsecstats; ++ ++#ifdef UBSEC_DEBUG ++static struct proc_dir_entry *procdebug; ++#endif ++ ++static struct ssb_device_id ubsec_ssb_tbl[] = { ++ /* Broadcom BCM5365P IPSec Core */ ++ SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_IPSEC, SSB_ANY_REV), ++ SSB_DEVTABLE_END ++}; ++ ++static struct ssb_driver ubsec_ssb_driver = { ++ .name = DRV_MODULE_NAME, ++ .id_table = ubsec_ssb_tbl, ++ .probe = ubsec_ssb_probe, ++ .remove = __devexit_p(ubsec_ssb_remove), ++ /* ++ .suspend = ubsec_ssb_suspend, ++ .resume = ubsec_ssb_resume ++ */ ++}; ++ ++static device_method_t ubsec_ssb_methods = { ++ /* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, ubsec_newsession), ++ DEVMETHOD(cryptodev_freesession,ubsec_freesession), ++ DEVMETHOD(cryptodev_process, ubsec_process), ++}; ++ ++#ifdef UBSEC_DEBUG ++static int ++proc_read(char *buf, char **start, off_t offset, ++ int size, int *peof, void *data) ++{ ++ int i = 0, byteswritten = 0, ret; ++ unsigned int stat, ctrl; ++#ifdef UBSEC_VERBOSE_DEBUG ++ struct ubsec_q *q; ++ struct ubsec_dma *dmap; ++#endif ++ ++ while ((i < UBSEC_SSB_MAX_CHIPS) && (ubsec_chip_idx[i] != NULL)) ++ { ++ struct ubsec_softc *sc = ubsec_chip_idx[i]; ++ ++ stat = READ_REG(sc, BS_STAT); ++ ctrl = READ_REG(sc, BS_CTRL); ++ ret = snprintf((buf + byteswritten), ++ (size - byteswritten) , ++ "DEV %d, DMASTAT %08x, DMACTRL %08x\n", i, stat, ctrl); ++ ++ byteswritten += ret; ++ ++#ifdef UBSEC_VERBOSE_DEBUG ++ printf("DEV %d, DMASTAT %08x, DMACTRL %08x\n", i, stat, ctrl); ++ ++ /* Dump all queues MCRs */ ++ if (!BSD_SIMPLEQ_EMPTY(&sc->sc_qchip)) { ++ BSD_SIMPLEQ_FOREACH(q, &sc->sc_qchip, q_next) ++ { ++ dmap = q->q_dma; ++ ubsec_dump_mcr(&dmap->d_dma->d_mcr); ++ } ++ } ++#endif ++ ++ i++; ++ } ++ ++ *peof = 1; ++ ++ return byteswritten; ++} ++#endif ++ ++/* ++ * map in a given sk_buff ++ */ ++static int ++dma_map_skb(struct ubsec_softc *sc, struct ubsec_dma_alloc* q_map, struct sk_buff *skb, int *mlen) ++{ ++ int i = 0; ++ dma_addr_t tmp; ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ ++ /* ++ * We support only a limited number of fragments. ++ */ ++ if (unlikely((skb_shinfo(skb)->nr_frags + 1) >= UBS_MAX_SCATTER)) ++ { ++ printk(KERN_ERR "Only %d scatter fragments are supported.\n", UBS_MAX_SCATTER); ++ return (-ENOMEM); ++ } ++ ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("%s - map %d 0x%x %d\n", __FUNCTION__, 0, (unsigned int)skb->data, skb_headlen(skb)); ++#endif ++ ++ /* first data package */ ++ tmp = dma_map_single(sc->sc_dv, ++ skb->data, ++ skb_headlen(skb), ++ DMA_BIDIRECTIONAL); ++ ++ q_map[i].dma_paddr = tmp; ++ q_map[i].dma_vaddr = skb->data; ++ q_map[i].dma_size = skb_headlen(skb); ++ ++ if (unlikely(tmp == 0)) ++ { ++ printk(KERN_ERR "Could not map memory region for dma.\n"); ++ return (-EINVAL); ++ } ++ ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("%s - map %d done physical addr 0x%x\n", __FUNCTION__, 0, (unsigned int)tmp); ++#endif ++ ++ ++ /* all other data packages */ ++ for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { ++ ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("%s - map %d 0x%x %d\n", __FUNCTION__, i + 1, ++ (unsigned int)page_address(skb_shinfo(skb)->frags[i].page) + ++ skb_shinfo(skb)->frags[i].page_offset, skb_shinfo(skb)->frags[i].size); ++#endif ++ ++ tmp = dma_map_single(sc->sc_dv, ++ page_address(skb_shinfo(skb)->frags[i].page) + ++ skb_shinfo(skb)->frags[i].page_offset, ++ skb_shinfo(skb)->frags[i].size, ++ DMA_BIDIRECTIONAL); ++ ++ q_map[i + 1].dma_paddr = tmp; ++ q_map[i + 1].dma_vaddr = (void*)(page_address(skb_shinfo(skb)->frags[i].page) + ++ skb_shinfo(skb)->frags[i].page_offset); ++ q_map[i + 1].dma_size = skb_shinfo(skb)->frags[i].size; ++ ++ if (unlikely(tmp == 0)) ++ { ++ printk(KERN_ERR "Could not map memory region for dma.\n"); ++ return (-EINVAL); ++ } ++ ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("%s - map %d done physical addr 0x%x\n", __FUNCTION__, i + 1, (unsigned int)tmp); ++#endif ++ ++ } ++ *mlen = i + 1; ++ ++ return(0); ++} ++ ++/* ++ * map in a given uio buffer ++ */ ++ ++static int ++dma_map_uio(struct ubsec_softc *sc, struct ubsec_dma_alloc *q_map, struct uio *uio, int *mlen) ++{ ++ struct iovec *iov = uio->uio_iov; ++ int n; ++ dma_addr_t tmp; ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ ++ /* ++ * We support only a limited number of fragments. ++ */ ++ if (unlikely(uio->uio_iovcnt >= UBS_MAX_SCATTER)) ++ { ++ printk(KERN_ERR "Only %d scatter fragments are supported.\n", UBS_MAX_SCATTER); ++ return (-ENOMEM); ++ } ++ ++ for (n = 0; n < uio->uio_iovcnt; n++) { ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("%s - map %d 0x%x %d\n", __FUNCTION__, n, (unsigned int)iov->iov_base, iov->iov_len); ++#endif ++ tmp = dma_map_single(sc->sc_dv, ++ iov->iov_base, ++ iov->iov_len, ++ DMA_BIDIRECTIONAL); ++ ++ q_map[n].dma_paddr = tmp; ++ q_map[n].dma_vaddr = iov->iov_base; ++ q_map[n].dma_size = iov->iov_len; ++ ++ if (unlikely(tmp == 0)) ++ { ++ printk(KERN_ERR "Could not map memory region for dma.\n"); ++ return (-EINVAL); ++ } ++ ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("%s - map %d done physical addr 0x%x\n", __FUNCTION__, n, (unsigned int)tmp); ++#endif ++ ++ iov++; ++ } ++ *mlen = n; ++ ++ return(0); ++} ++ ++static void ++dma_unmap(struct ubsec_softc *sc, struct ubsec_dma_alloc *q_map, int mlen) ++{ ++ int i; ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ ++ for(i = 0; i < mlen; i++) ++ { ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("%s - unmap %d 0x%x %d\n", __FUNCTION__, i, (unsigned int)q_map[i].dma_paddr, q_map[i].dma_size); ++#endif ++ dma_unmap_single(sc->sc_dv, ++ q_map[i].dma_paddr, ++ q_map[i].dma_size, ++ DMA_BIDIRECTIONAL); ++ } ++ return; ++} ++ ++/* ++ * Is the operand suitable aligned for direct DMA. Each ++ * segment must be aligned on a 32-bit boundary and all ++ * but the last segment must be a multiple of 4 bytes. ++ */ ++static int ++ubsec_dmamap_aligned(struct ubsec_softc *sc, const struct ubsec_dma_alloc *q_map, int mlen) ++{ ++ int i; ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ ++ for (i = 0; i < mlen; i++) { ++ if (q_map[i].dma_paddr & 3) ++ return (0); ++ if (i != (mlen - 1) && (q_map[i].dma_size & 3)) ++ return (0); ++ } ++ return (1); ++} ++ ++ ++#define N(a) (sizeof(a) / sizeof (a[0])) ++static void ++ubsec_setup_mackey(struct ubsec_session *ses, int algo, caddr_t key, int klen) ++{ ++#ifdef HMAC_HACK ++ MD5_CTX md5ctx; ++ SHA1_CTX sha1ctx; ++ int i; ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ ++ for (i = 0; i < klen; i++) ++ key[i] ^= HMAC_IPAD_VAL; ++ ++ if (algo == CRYPTO_MD5_HMAC) { ++ MD5Init(&md5ctx); ++ MD5Update(&md5ctx, key, klen); ++ MD5Update(&md5ctx, hmac_ipad_buffer, MD5_HMAC_BLOCK_LEN - klen); ++ bcopy(md5ctx.md5_st8, ses->ses_hminner, sizeof(md5ctx.md5_st8)); ++ } else { ++ SHA1Init(&sha1ctx); ++ SHA1Update(&sha1ctx, key, klen); ++ SHA1Update(&sha1ctx, hmac_ipad_buffer, ++ SHA1_HMAC_BLOCK_LEN - klen); ++ bcopy(sha1ctx.h.b32, ses->ses_hminner, sizeof(sha1ctx.h.b32)); ++ } ++ ++ for (i = 0; i < klen; i++) ++ key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); ++ ++ if (algo == CRYPTO_MD5_HMAC) { ++ MD5Init(&md5ctx); ++ MD5Update(&md5ctx, key, klen); ++ MD5Update(&md5ctx, hmac_opad_buffer, MD5_HMAC_BLOCK_LEN - klen); ++ bcopy(md5ctx.md5_st8, ses->ses_hmouter, sizeof(md5ctx.md5_st8)); ++ } else { ++ SHA1Init(&sha1ctx); ++ SHA1Update(&sha1ctx, key, klen); ++ SHA1Update(&sha1ctx, hmac_opad_buffer, ++ SHA1_HMAC_BLOCK_LEN - klen); ++ bcopy(sha1ctx.h.b32, ses->ses_hmouter, sizeof(sha1ctx.h.b32)); ++ } ++ ++ for (i = 0; i < klen; i++) ++ key[i] ^= HMAC_OPAD_VAL; ++ ++#else /* HMAC_HACK */ ++ DPRINTF("md5/sha not implemented\n"); ++#endif /* HMAC_HACK */ ++} ++#undef N ++ ++static int ++__devinit ubsec_ssb_probe(struct ssb_device *sdev, ++ const struct ssb_device_id *ent) ++{ ++ int err; ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ ++ err = ssb_bus_powerup(sdev->bus, 0); ++ if (err) { ++ dev_err(sdev->dev, "Failed to powerup the bus\n"); ++ goto err_out; ++ } ++ ++ err = request_irq(sdev->irq, (irq_handler_t)ubsec_ssb_isr, ++ IRQF_DISABLED | IRQF_SHARED, DRV_MODULE_NAME, sdev); ++ if (err) { ++ dev_err(sdev->dev, "Could not request irq\n"); ++ goto err_out_powerdown; ++ } ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,36)) ++ err = dma_set_mask(sdev->dma_dev, DMA_BIT_MASK(32)) || ++ dma_set_coherent_mask(sdev->dma_dev, DMA_BIT_MASK(32)); ++#else ++ err = ssb_dma_set_mask(sdev, DMA_32BIT_MASK); ++#endif ++ if (err) { ++ dev_err(sdev->dev, ++ "Required 32BIT DMA mask unsupported by the system.\n"); ++ goto err_out_free_irq; ++ } ++ ++ printk(KERN_INFO "Sentry5(tm) ROBOGateway(tm) IPSec Core at IRQ %u\n", ++ sdev->irq); ++ ++ DPRINTF("Vendor: %x, core id: %x, revision: %x\n", ++ sdev->id.vendor, sdev->id.coreid, sdev->id.revision); ++ ++ ssb_device_enable(sdev, 0); ++ ++ if (ubsec_attach(sdev, ent, sdev->dev) != 0) ++ goto err_out_disable; ++ ++#ifdef UBSEC_DEBUG ++ procdebug = create_proc_entry(DRV_MODULE_NAME, S_IRUSR, NULL); ++ if (procdebug) ++ { ++ procdebug->read_proc = proc_read; ++ procdebug->data = NULL; ++ } else ++ DPRINTF("Unable to create proc file.\n"); ++#endif ++ ++ return 0; ++ ++err_out_disable: ++ ssb_device_disable(sdev, 0); ++ ++err_out_free_irq: ++ free_irq(sdev->irq, sdev); ++ ++err_out_powerdown: ++ ssb_bus_may_powerdown(sdev->bus); ++ ++err_out: ++ return err; ++} ++ ++static void __devexit ubsec_ssb_remove(struct ssb_device *sdev) { ++ ++ struct ubsec_softc *sc; ++ unsigned int ctrlflgs; ++ struct ubsec_dma *dmap; ++ u_int32_t i; ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ ++ ctrlflgs = READ_REG_SDEV(sdev, BS_CTRL); ++ /* disable all IPSec Core interrupts globally */ ++ ctrlflgs ^= (BS_CTRL_MCR1INT | BS_CTRL_MCR2INT | ++ BS_CTRL_DMAERR); ++ WRITE_REG_SDEV(sdev, BS_CTRL, ctrlflgs); ++ ++ free_irq(sdev->irq, sdev); ++ ++ sc = (struct ubsec_softc *)ssb_get_drvdata(sdev); ++ ++ /* unregister all crypto algorithms */ ++ crypto_unregister_all(sc->sc_cid); ++ ++ /* Free queue / dma memory */ ++ for (i = 0; i < UBS_MAX_NQUEUE; i++) { ++ struct ubsec_q *q; ++ ++ q = sc->sc_queuea[i]; ++ if (q != NULL) ++ { ++ dmap = q->q_dma; ++ if (dmap != NULL) ++ { ++ ubsec_dma_free(sc, &dmap->d_alloc); ++ q->q_dma = NULL; ++ } ++ kfree(q); ++ } ++ sc->sc_queuea[i] = NULL; ++ } ++ ++ ssb_device_disable(sdev, 0); ++ ssb_bus_may_powerdown(sdev->bus); ++ ssb_set_drvdata(sdev, NULL); ++ ++#ifdef UBSEC_DEBUG ++ if (procdebug) ++ remove_proc_entry(DRV_MODULE_NAME, NULL); ++#endif ++ ++} ++ ++ ++int ++ubsec_attach(struct ssb_device *sdev, const struct ssb_device_id *ent, ++ struct device *self) ++{ ++ struct ubsec_softc *sc = NULL; ++ struct ubsec_dma *dmap; ++ u_int32_t i; ++ static int num_chips = 0; ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ ++ sc = (struct ubsec_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); ++ if (!sc) ++ return(-ENOMEM); ++ memset(sc, 0, sizeof(*sc)); ++ ++ sc->sc_dv = sdev->dev; ++ sc->sdev = sdev; ++ ++ spin_lock_init(&sc->sc_ringmtx); ++ ++ softc_device_init(sc, "ubsec_ssb", num_chips, ubsec_ssb_methods); ++ ++ /* Maybe someday there are boards with more than one chip available */ ++ if (num_chips < UBSEC_SSB_MAX_CHIPS) { ++ ubsec_chip_idx[device_get_unit(sc->sc_dev)] = sc; ++ num_chips++; ++ } ++ ++ ssb_set_drvdata(sdev, sc); ++ ++ BSD_SIMPLEQ_INIT(&sc->sc_queue); ++ BSD_SIMPLEQ_INIT(&sc->sc_qchip); ++ BSD_SIMPLEQ_INIT(&sc->sc_queue2); ++ BSD_SIMPLEQ_INIT(&sc->sc_qchip2); ++ BSD_SIMPLEQ_INIT(&sc->sc_q2free); ++ ++ sc->sc_statmask = BS_STAT_MCR1_DONE | BS_STAT_DMAERR; ++ ++ sc->sc_cid = crypto_get_driverid(softc_get_device(sc), CRYPTOCAP_F_HARDWARE); ++ if (sc->sc_cid < 0) { ++ device_printf(sc->sc_dev, "could not get crypto driver id\n"); ++ return -1; ++ } ++ ++ BSD_SIMPLEQ_INIT(&sc->sc_freequeue); ++ dmap = sc->sc_dmaa; ++ for (i = 0; i < UBS_MAX_NQUEUE; i++, dmap++) { ++ struct ubsec_q *q; ++ ++ q = (struct ubsec_q *)kmalloc(sizeof(struct ubsec_q), GFP_KERNEL); ++ if (q == NULL) { ++ printf(": can't allocate queue buffers\n"); ++ break; ++ } ++ ++ if (ubsec_dma_malloc(sc, &dmap->d_alloc, sizeof(struct ubsec_dmachunk),0)) { ++ printf(": can't allocate dma buffers\n"); ++ kfree(q); ++ break; ++ } ++ dmap->d_dma = (struct ubsec_dmachunk *)dmap->d_alloc.dma_vaddr; ++ ++ q->q_dma = dmap; ++ sc->sc_queuea[i] = q; ++ ++ BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); ++ } ++ ++ /* ++ * Reset Broadcom chip ++ */ ++ ubsec_reset_board(sc); ++ ++ /* ++ * Init Broadcom chip ++ */ ++ ubsec_init_board(sc); ++ ++ /* supported crypto algorithms */ ++ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); ++ ++ if (sc->sc_flags & UBS_FLAGS_AES) { ++ crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); ++ printf(KERN_INFO DRV_MODULE_NAME ": DES 3DES AES128 AES192 AES256 MD5_HMAC SHA1_HMAC\n"); ++ } ++ else ++ printf(KERN_INFO DRV_MODULE_NAME ": DES 3DES MD5_HMAC SHA1_HMAC\n"); ++ ++ crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); ++ ++ return 0; ++} ++ ++/* ++ * UBSEC Interrupt routine ++ */ ++static irqreturn_t ++ubsec_ssb_isr(int irq, void *arg, struct pt_regs *regs) ++{ ++ struct ubsec_softc *sc = NULL; ++ volatile u_int32_t stat; ++ struct ubsec_q *q; ++ struct ubsec_dma *dmap; ++ int npkts = 0, i; ++ ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ ++ sc = (struct ubsec_softc *)ssb_get_drvdata(arg); ++ ++ stat = READ_REG(sc, BS_STAT); ++ ++ stat &= sc->sc_statmask; ++ if (stat == 0) ++ return IRQ_NONE; ++ ++ WRITE_REG(sc, BS_STAT, stat); /* IACK */ ++ ++ /* ++ * Check to see if we have any packets waiting for us ++ */ ++ if ((stat & BS_STAT_MCR1_DONE)) { ++ while (!BSD_SIMPLEQ_EMPTY(&sc->sc_qchip)) { ++ q = BSD_SIMPLEQ_FIRST(&sc->sc_qchip); ++ dmap = q->q_dma; ++ ++ if ((dmap->d_dma->d_mcr.mcr_flags & htole16(UBS_MCR_DONE)) == 0) ++ { ++ DPRINTF("error while processing MCR. Flags = %x\n", dmap->d_dma->d_mcr.mcr_flags); ++ break; ++ } ++ ++ BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q_next); ++ ++ npkts = q->q_nstacked_mcrs; ++ /* ++ * search for further sc_qchip ubsec_q's that share ++ * the same MCR, and complete them too, they must be ++ * at the top. ++ */ ++ for (i = 0; i < npkts; i++) { ++ if(q->q_stacked_mcr[i]) ++ ubsec_callback(sc, q->q_stacked_mcr[i]); ++ else ++ break; ++ } ++ ubsec_callback(sc, q); ++ } ++ ++ /* ++ * Don't send any more packet to chip if there has been ++ * a DMAERR. ++ */ ++ if (likely(!(stat & BS_STAT_DMAERR))) ++ ubsec_feed(sc); ++ else ++ DPRINTF("DMA error occurred. Stop feeding crypto chip.\n"); ++ } ++ ++ /* ++ * Check to see if we got any DMA Error ++ */ ++ if (stat & BS_STAT_DMAERR) { ++ volatile u_int32_t a = READ_REG(sc, BS_ERR); ++ ++ printf(KERN_ERR "%s: dmaerr %s@%08x\n", DRV_MODULE_NAME, ++ (a & BS_ERR_READ) ? "read" : "write", a & BS_ERR_ADDR); ++ ++ ubsecstats.hst_dmaerr++; ++ ubsec_totalreset(sc); ++ ubsec_feed(sc); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++/* ++ * ubsec_feed() - aggregate and post requests to chip ++ * It is assumed that the caller set splnet() ++ */ ++void ++ubsec_feed(struct ubsec_softc *sc) ++{ ++#ifdef UBSEC_VERBOSE_DEBUG ++ static int max; ++#endif ++ struct ubsec_q *q, *q2; ++ int npkts, i; ++ void *v; ++ u_int32_t stat; ++ ++ npkts = sc->sc_nqueue; ++ if (npkts > UBS_MAX_AGGR) ++ npkts = UBS_MAX_AGGR; ++ if (npkts < 2) ++ goto feed1; ++ ++ stat = READ_REG(sc, BS_STAT); ++ ++ if (stat & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) { ++ if(stat & BS_STAT_DMAERR) { ++ ubsec_totalreset(sc); ++ ubsecstats.hst_dmaerr++; ++ } ++ return; ++ } ++ ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("merging %d records\n", npkts); ++ ++ /* XXX temporary aggregation statistics reporting code */ ++ if (max < npkts) { ++ max = npkts; ++ DPRINTF("%s: new max aggregate %d\n", DRV_MODULE_NAME, max); ++ } ++#endif /* UBSEC_VERBOSE_DEBUG */ ++ ++ q = BSD_SIMPLEQ_FIRST(&sc->sc_queue); ++ BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next); ++ --sc->sc_nqueue; ++ ++#if 0 ++ /* ++ * XXX ++ * We use dma_map_single() - no sync required! ++ */ ++ ++ bus_dmamap_sync(sc->sc_dmat, q->q_src_map, ++ 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE); ++ if (q->q_dst_map != NULL) ++ bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, ++ 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD); ++#endif ++ ++ q->q_nstacked_mcrs = npkts - 1; /* Number of packets stacked */ ++ ++ for (i = 0; i < q->q_nstacked_mcrs; i++) { ++ q2 = BSD_SIMPLEQ_FIRST(&sc->sc_queue); ++ ++#if 0 ++ bus_dmamap_sync(sc->sc_dmat, q2->q_src_map, ++ 0, q2->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE); ++ if (q2->q_dst_map != NULL) ++ bus_dmamap_sync(sc->sc_dmat, q2->q_dst_map, ++ 0, q2->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD); ++#endif ++ BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next); ++ --sc->sc_nqueue; ++ ++ v = ((char *)&q2->q_dma->d_dma->d_mcr) + sizeof(struct ubsec_mcr) - ++ sizeof(struct ubsec_mcr_add); ++ bcopy(v, &q->q_dma->d_dma->d_mcradd[i], sizeof(struct ubsec_mcr_add)); ++ q->q_stacked_mcr[i] = q2; ++ } ++ q->q_dma->d_dma->d_mcr.mcr_pkts = htole16(npkts); ++ BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); ++#if 0 ++ bus_dmamap_sync(sc->sc_dmat, q->q_dma->d_alloc.dma_map, ++ 0, q->q_dma->d_alloc.dma_map->dm_mapsize, ++ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ++#endif ++ WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + ++ offsetof(struct ubsec_dmachunk, d_mcr)); ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("feed (1): q->chip %p %08x %08x\n", q, ++ (u_int32_t)q->q_dma->d_alloc.dma_paddr, ++ (u_int32_t)(q->q_dma->d_alloc.dma_paddr + ++ offsetof(struct ubsec_dmachunk, d_mcr))); ++#endif /* UBSEC_DEBUG */ ++ return; ++ ++feed1: ++ while (!BSD_SIMPLEQ_EMPTY(&sc->sc_queue)) { ++ stat = READ_REG(sc, BS_STAT); ++ ++ if (stat & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) { ++ if(stat & BS_STAT_DMAERR) { ++ ubsec_totalreset(sc); ++ ubsecstats.hst_dmaerr++; ++ } ++ break; ++ } ++ ++ q = BSD_SIMPLEQ_FIRST(&sc->sc_queue); ++ ++#if 0 ++ bus_dmamap_sync(sc->sc_dmat, q->q_src_map, ++ 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE); ++ if (q->q_dst_map != NULL) ++ bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, ++ 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD); ++ bus_dmamap_sync(sc->sc_dmat, q->q_dma->d_alloc.dma_map, ++ 0, q->q_dma->d_alloc.dma_map->dm_mapsize, ++ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ++#endif ++ ++ WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + ++ offsetof(struct ubsec_dmachunk, d_mcr)); ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("feed (2): q->chip %p %08x %08x\n", q, ++ (u_int32_t)q->q_dma->d_alloc.dma_paddr, ++ (u_int32_t)(q->q_dma->d_alloc.dma_paddr + ++ offsetof(struct ubsec_dmachunk, d_mcr))); ++#endif /* UBSEC_DEBUG */ ++ BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next); ++ --sc->sc_nqueue; ++ BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); ++ } ++} ++ ++/* ++ * Allocate a new 'session' and return an encoded session id. 'sidp' ++ * contains our registration id, and should contain an encoded session ++ * id on successful allocation. ++ */ ++static int ++ubsec_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) ++{ ++ struct cryptoini *c, *encini = NULL, *macini = NULL; ++ struct ubsec_softc *sc = NULL; ++ struct ubsec_session *ses = NULL; ++ int sesn, i; ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ ++ if (sidp == NULL || cri == NULL) ++ return (EINVAL); ++ ++ sc = device_get_softc(dev); ++ ++ if (sc == NULL) ++ return (EINVAL); ++ ++ for (c = cri; c != NULL; c = c->cri_next) { ++ if (c->cri_alg == CRYPTO_MD5_HMAC || ++ c->cri_alg == CRYPTO_SHA1_HMAC) { ++ if (macini) ++ return (EINVAL); ++ macini = c; ++ } else if (c->cri_alg == CRYPTO_DES_CBC || ++ c->cri_alg == CRYPTO_3DES_CBC || ++ c->cri_alg == CRYPTO_AES_CBC) { ++ if (encini) ++ return (EINVAL); ++ encini = c; ++ } else ++ return (EINVAL); ++ } ++ if (encini == NULL && macini == NULL) ++ return (EINVAL); ++ ++ if (sc->sc_sessions == NULL) { ++ ses = sc->sc_sessions = (struct ubsec_session *)kmalloc( ++ sizeof(struct ubsec_session), SLAB_ATOMIC); ++ if (ses == NULL) ++ return (ENOMEM); ++ memset(ses, 0, sizeof(struct ubsec_session)); ++ sesn = 0; ++ sc->sc_nsessions = 1; ++ } else { ++ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { ++ if (sc->sc_sessions[sesn].ses_used == 0) { ++ ses = &sc->sc_sessions[sesn]; ++ break; ++ } ++ } ++ ++ if (ses == NULL) { ++ sesn = sc->sc_nsessions; ++ ses = (struct ubsec_session *)kmalloc((sesn + 1) * ++ sizeof(struct ubsec_session), SLAB_ATOMIC); ++ if (ses == NULL) ++ return (ENOMEM); ++ memset(ses, 0, (sesn + 1) * sizeof(struct ubsec_session)); ++ bcopy(sc->sc_sessions, ses, sesn * ++ sizeof(struct ubsec_session)); ++ bzero(sc->sc_sessions, sesn * ++ sizeof(struct ubsec_session)); ++ kfree(sc->sc_sessions); ++ sc->sc_sessions = ses; ++ ses = &sc->sc_sessions[sesn]; ++ sc->sc_nsessions++; ++ } ++ } ++ ++ bzero(ses, sizeof(struct ubsec_session)); ++ ses->ses_used = 1; ++ if (encini) { ++ /* get an IV */ ++ /* XXX may read fewer than requested */ ++ read_random(ses->ses_iv, sizeof(ses->ses_iv)); ++ ++ /* Go ahead and compute key in ubsec's byte order */ ++ if (encini->cri_alg == CRYPTO_DES_CBC) { ++ /* DES uses the same key three times: ++ * 1st encrypt -> 2nd decrypt -> 3nd encrypt */ ++ bcopy(encini->cri_key, &ses->ses_key[0], 8); ++ bcopy(encini->cri_key, &ses->ses_key[2], 8); ++ bcopy(encini->cri_key, &ses->ses_key[4], 8); ++ ses->ses_keysize = 192; /* Fake! Actually its only 64bits .. ++ oh no it is even less: 54bits. */ ++ } else if(encini->cri_alg == CRYPTO_3DES_CBC) { ++ bcopy(encini->cri_key, ses->ses_key, 24); ++ ses->ses_keysize = 192; ++ } else if(encini->cri_alg == CRYPTO_AES_CBC) { ++ ses->ses_keysize = encini->cri_klen; ++ ++ if (ses->ses_keysize != 128 && ++ ses->ses_keysize != 192 && ++ ses->ses_keysize != 256) ++ { ++ DPRINTF("unsupported AES key size: %d\n", ses->ses_keysize); ++ return (EINVAL); ++ } ++ bcopy(encini->cri_key, ses->ses_key, (ses->ses_keysize / 8)); ++ } ++ ++ /* Hardware requires the keys in little endian byte order */ ++ for (i=0; i < (ses->ses_keysize / 32); i++) ++ SWAP32(ses->ses_key[i]); ++ } ++ ++ if (macini) { ++ ses->ses_mlen = macini->cri_mlen; ++ ++ if (ses->ses_mlen == 0 || ++ ses->ses_mlen > SHA1_HASH_LEN) { ++ ++ if (macini->cri_alg == CRYPTO_MD5_HMAC || ++ macini->cri_alg == CRYPTO_SHA1_HMAC) ++ { ++ ses->ses_mlen = DEFAULT_HMAC_LEN; ++ } else ++ { ++ /* ++ * Reserved for future usage. MD5/SHA1 calculations have ++ * different hash sizes. ++ */ ++ printk(KERN_ERR DRV_MODULE_NAME ": unsupported hash operation with mac/hash len: %d\n", ses->ses_mlen); ++ return (EINVAL); ++ } ++ ++ } ++ ++ if (macini->cri_key != NULL) { ++ ubsec_setup_mackey(ses, macini->cri_alg, macini->cri_key, ++ macini->cri_klen / 8); ++ } ++ } ++ ++ *sidp = UBSEC_SID(device_get_unit(sc->sc_dev), sesn); ++ return (0); ++} ++ ++/* ++ * Deallocate a session. ++ */ ++static int ++ubsec_freesession(device_t dev, u_int64_t tid) ++{ ++ struct ubsec_softc *sc = device_get_softc(dev); ++ int session; ++ u_int32_t sid = ((u_int32_t)tid) & 0xffffffff; ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ ++ if (sc == NULL) ++ return (EINVAL); ++ ++ session = UBSEC_SESSION(sid); ++ if (session < sc->sc_nsessions) { ++ bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session])); ++ return (0); ++ } else ++ return (EINVAL); ++} ++ ++static int ++ubsec_process(device_t dev, struct cryptop *crp, int hint) ++{ ++ struct ubsec_q *q = NULL; ++ int err = 0, i, j, nicealign; ++ struct ubsec_softc *sc = device_get_softc(dev); ++ struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; ++ int encoffset = 0, macoffset = 0, cpskip, cpoffset; ++ int sskip, dskip, stheend, dtheend, ivsize = 8; ++ int16_t coffset; ++ struct ubsec_session *ses; ++ struct ubsec_generic_ctx ctx; ++ struct ubsec_dma *dmap = NULL; ++ unsigned long flags; ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ ++ if (unlikely(crp == NULL || crp->crp_callback == NULL)) { ++ ubsecstats.hst_invalid++; ++ return (EINVAL); ++ } ++ ++ if (unlikely(sc == NULL)) ++ return (EINVAL); ++ ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("spin_lock_irqsave\n"); ++#endif ++ spin_lock_irqsave(&sc->sc_ringmtx, flags); ++ //spin_lock_irq(&sc->sc_ringmtx); ++ ++ if (BSD_SIMPLEQ_EMPTY(&sc->sc_freequeue)) { ++ ubsecstats.hst_queuefull++; ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("spin_unlock_irqrestore\n"); ++#endif ++ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); ++ //spin_unlock_irq(&sc->sc_ringmtx); ++ err = ENOMEM; ++ goto errout2; ++ } ++ ++ q = BSD_SIMPLEQ_FIRST(&sc->sc_freequeue); ++ BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q_next); ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("spin_unlock_irqrestore\n"); ++#endif ++ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); ++ //spin_unlock_irq(&sc->sc_ringmtx); ++ ++ dmap = q->q_dma; /* Save dma pointer */ ++ bzero(q, sizeof(struct ubsec_q)); ++ bzero(&ctx, sizeof(ctx)); ++ ++ q->q_sesn = UBSEC_SESSION(crp->crp_sid); ++ q->q_dma = dmap; ++ ses = &sc->sc_sessions[q->q_sesn]; ++ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ q->q_src_m = (struct sk_buff *)crp->crp_buf; ++ q->q_dst_m = (struct sk_buff *)crp->crp_buf; ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ q->q_src_io = (struct uio *)crp->crp_buf; ++ q->q_dst_io = (struct uio *)crp->crp_buf; ++ } else { ++ err = EINVAL; ++ goto errout; /* XXX we don't handle contiguous blocks! */ ++ } ++ ++ bzero(&dmap->d_dma->d_mcr, sizeof(struct ubsec_mcr)); ++ ++ dmap->d_dma->d_mcr.mcr_pkts = htole16(1); ++ dmap->d_dma->d_mcr.mcr_flags = 0; ++ q->q_crp = crp; ++ ++ crd1 = crp->crp_desc; ++ if (crd1 == NULL) { ++ err = EINVAL; ++ goto errout; ++ } ++ crd2 = crd1->crd_next; ++ ++ if (crd2 == NULL) { ++ if (crd1->crd_alg == CRYPTO_MD5_HMAC || ++ crd1->crd_alg == CRYPTO_SHA1_HMAC) { ++ maccrd = crd1; ++ enccrd = NULL; ++ } else if (crd1->crd_alg == CRYPTO_DES_CBC || ++ crd1->crd_alg == CRYPTO_3DES_CBC || ++ crd1->crd_alg == CRYPTO_AES_CBC) { ++ maccrd = NULL; ++ enccrd = crd1; ++ } else { ++ err = EINVAL; ++ goto errout; ++ } ++ } else { ++ if ((crd1->crd_alg == CRYPTO_MD5_HMAC || ++ crd1->crd_alg == CRYPTO_SHA1_HMAC) && ++ (crd2->crd_alg == CRYPTO_DES_CBC || ++ crd2->crd_alg == CRYPTO_3DES_CBC || ++ crd2->crd_alg == CRYPTO_AES_CBC) && ++ ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { ++ maccrd = crd1; ++ enccrd = crd2; ++ } else if ((crd1->crd_alg == CRYPTO_DES_CBC || ++ crd1->crd_alg == CRYPTO_3DES_CBC || ++ crd1->crd_alg == CRYPTO_AES_CBC) && ++ (crd2->crd_alg == CRYPTO_MD5_HMAC || ++ crd2->crd_alg == CRYPTO_SHA1_HMAC) && ++ (crd1->crd_flags & CRD_F_ENCRYPT)) { ++ enccrd = crd1; ++ maccrd = crd2; ++ } else { ++ /* ++ * We cannot order the ubsec as requested ++ */ ++ printk(KERN_ERR DRV_MODULE_NAME ": got wrong algorithm/signature order.\n"); ++ err = EINVAL; ++ goto errout; ++ } ++ } ++ ++ /* Encryption/Decryption requested */ ++ if (enccrd) { ++ encoffset = enccrd->crd_skip; ++ ++ if (enccrd->crd_alg == CRYPTO_DES_CBC || ++ enccrd->crd_alg == CRYPTO_3DES_CBC) ++ { ++ ctx.pc_flags |= htole16(UBS_PKTCTX_ENC_3DES); ++ ctx.pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC_DES); ++ ivsize = 8; /* [3]DES uses 64bit IVs */ ++ } else { ++ ctx.pc_flags |= htole16(UBS_PKTCTX_ENC_AES); ++ ctx.pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC_AES); ++ ivsize = 16; /* AES uses 128bit IVs / [3]DES 64bit IVs */ ++ ++ switch(ses->ses_keysize) ++ { ++ case 128: ++ ctx.pc_flags |= htole16(UBS_PKTCTX_AES128); ++ break; ++ case 192: ++ ctx.pc_flags |= htole16(UBS_PKTCTX_AES192); ++ break; ++ case 256: ++ ctx.pc_flags |= htole16(UBS_PKTCTX_AES256); ++ break; ++ default: ++ DPRINTF("invalid AES key size: %d\n", ses->ses_keysize); ++ err = EINVAL; ++ goto errout; ++ } ++ } ++ ++ if (enccrd->crd_flags & CRD_F_ENCRYPT) { ++ /* Direction: Outbound */ ++ ++ q->q_flags |= UBSEC_QFLAGS_COPYOUTIV; ++ ++ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) { ++ bcopy(enccrd->crd_iv, ctx.pc_iv, ivsize); ++ } else { ++ for(i=0; i < (ivsize / 4); i++) ++ ctx.pc_iv[i] = ses->ses_iv[i]; ++ } ++ ++ /* If there is no IV in the buffer -> copy it here */ ++ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { ++ if (crp->crp_flags & CRYPTO_F_SKBUF) ++ /* ++ m_copyback(q->q_src_m, ++ enccrd->crd_inject, ++ 8, ctx.pc_iv); ++ */ ++ crypto_copyback(crp->crp_flags, (caddr_t)q->q_src_m, ++ enccrd->crd_inject, ivsize, (caddr_t)ctx.pc_iv); ++ else if (crp->crp_flags & CRYPTO_F_IOV) ++ /* ++ cuio_copyback(q->q_src_io, ++ enccrd->crd_inject, ++ 8, ctx.pc_iv); ++ */ ++ crypto_copyback(crp->crp_flags, (caddr_t)q->q_src_io, ++ enccrd->crd_inject, ivsize, (caddr_t)ctx.pc_iv); ++ } ++ } else { ++ /* Direction: Inbound */ ++ ++ ctx.pc_flags |= htole16(UBS_PKTCTX_INBOUND); ++ ++ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) ++ bcopy(enccrd->crd_iv, ctx.pc_iv, ivsize); ++ else if (crp->crp_flags & CRYPTO_F_SKBUF) ++ /* ++ m_copydata(q->q_src_m, enccrd->crd_inject, ++ 8, (caddr_t)ctx.pc_iv); ++ */ ++ crypto_copydata(crp->crp_flags, (caddr_t)q->q_src_m, ++ enccrd->crd_inject, ivsize, ++ (caddr_t)ctx.pc_iv); ++ else if (crp->crp_flags & CRYPTO_F_IOV) ++ /* ++ cuio_copydata(q->q_src_io, ++ enccrd->crd_inject, 8, ++ (caddr_t)ctx.pc_iv); ++ */ ++ crypto_copydata(crp->crp_flags, (caddr_t)q->q_src_io, ++ enccrd->crd_inject, ivsize, ++ (caddr_t)ctx.pc_iv); ++ ++ } ++ ++ /* Even though key & IV sizes differ from cipher to cipher ++ * copy / swap the full array lengths. Let the compiler unroll ++ * the loop to increase the cpu pipeline performance... */ ++ for(i=0; i < 8; i++) ++ ctx.pc_key[i] = ses->ses_key[i]; ++ for(i=0; i < 4; i++) ++ SWAP32(ctx.pc_iv[i]); ++ } ++ ++ /* Authentication requested */ ++ if (maccrd) { ++ macoffset = maccrd->crd_skip; ++ ++ if (maccrd->crd_alg == CRYPTO_MD5_HMAC) ++ ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_MD5); ++ else ++ ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_SHA1); ++ ++ for (i = 0; i < 5; i++) { ++ ctx.pc_hminner[i] = ses->ses_hminner[i]; ++ ctx.pc_hmouter[i] = ses->ses_hmouter[i]; ++ ++ HTOLE32(ctx.pc_hminner[i]); ++ HTOLE32(ctx.pc_hmouter[i]); ++ } ++ } ++ ++ if (enccrd && maccrd) { ++ /* ++ * ubsec cannot handle packets where the end of encryption ++ * and authentication are not the same, or where the ++ * encrypted part begins before the authenticated part. ++ */ ++ if (((encoffset + enccrd->crd_len) != ++ (macoffset + maccrd->crd_len)) || ++ (enccrd->crd_skip < maccrd->crd_skip)) { ++ err = EINVAL; ++ goto errout; ++ } ++ sskip = maccrd->crd_skip; ++ cpskip = dskip = enccrd->crd_skip; ++ stheend = maccrd->crd_len; ++ dtheend = enccrd->crd_len; ++ coffset = enccrd->crd_skip - maccrd->crd_skip; ++ cpoffset = cpskip + dtheend; ++#ifdef UBSEC_DEBUG ++ DPRINTF("mac: skip %d, len %d, inject %d\n", ++ maccrd->crd_skip, maccrd->crd_len, maccrd->crd_inject); ++ DPRINTF("enc: skip %d, len %d, inject %d\n", ++ enccrd->crd_skip, enccrd->crd_len, enccrd->crd_inject); ++ DPRINTF("src: skip %d, len %d\n", sskip, stheend); ++ DPRINTF("dst: skip %d, len %d\n", dskip, dtheend); ++ DPRINTF("ubs: coffset %d, pktlen %d, cpskip %d, cpoffset %d\n", ++ coffset, stheend, cpskip, cpoffset); ++#endif ++ } else { ++ cpskip = dskip = sskip = macoffset + encoffset; ++ dtheend = stheend = (enccrd)?enccrd->crd_len:maccrd->crd_len; ++ cpoffset = cpskip + dtheend; ++ coffset = 0; ++ } ++ ctx.pc_offset = htole16(coffset >> 2); ++ ++#if 0 ++ if (bus_dmamap_create(sc->sc_dmat, 0xfff0, UBS_MAX_SCATTER, ++ 0xfff0, 0, BUS_DMA_NOWAIT, &q->q_src_map) != 0) { ++ err = ENOMEM; ++ goto errout; ++ } ++#endif ++ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++#if 0 ++ if (bus_dmamap_load_mbuf(sc->sc_dmat, q->q_src_map, ++ q->q_src_m, BUS_DMA_NOWAIT) != 0) { ++ bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); ++ q->q_src_map = NULL; ++ err = ENOMEM; ++ goto errout; ++ } ++#endif ++ err = dma_map_skb(sc, q->q_src_map, q->q_src_m, &q->q_src_len); ++ if (unlikely(err != 0)) ++ goto errout; ++ ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++#if 0 ++ if (bus_dmamap_load_uio(sc->sc_dmat, q->q_src_map, ++ q->q_src_io, BUS_DMA_NOWAIT) != 0) { ++ bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); ++ q->q_src_map = NULL; ++ err = ENOMEM; ++ goto errout; ++ } ++#endif ++ err = dma_map_uio(sc, q->q_src_map, q->q_src_io, &q->q_src_len); ++ if (unlikely(err != 0)) ++ goto errout; ++ } ++ ++ /* ++ * Check alignment ++ */ ++ nicealign = ubsec_dmamap_aligned(sc, q->q_src_map, q->q_src_len); ++ ++ dmap->d_dma->d_mcr.mcr_pktlen = htole16(stheend); ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("src skip: %d\n", sskip); ++#endif ++ for (i = j = 0; i < q->q_src_len; i++) { ++ struct ubsec_pktbuf *pb; ++ size_t packl = q->q_src_map[i].dma_size; ++ dma_addr_t packp = q->q_src_map[i].dma_paddr; ++ ++ if (sskip >= packl) { ++ sskip -= packl; ++ continue; ++ } ++ ++ packl -= sskip; ++ packp += sskip; ++ sskip = 0; ++ ++ /* maximum fragment size is 0xfffc */ ++ if (packl > 0xfffc) { ++ DPRINTF("Error: fragment size is bigger than 0xfffc.\n"); ++ err = EIO; ++ goto errout; ++ } ++ ++ if (j == 0) ++ pb = &dmap->d_dma->d_mcr.mcr_ipktbuf; ++ else ++ pb = &dmap->d_dma->d_sbuf[j - 1]; ++ ++ pb->pb_addr = htole32(packp); ++ ++ if (stheend) { ++ if (packl > stheend) { ++ pb->pb_len = htole32(stheend); ++ stheend = 0; ++ } else { ++ pb->pb_len = htole32(packl); ++ stheend -= packl; ++ } ++ } else ++ pb->pb_len = htole32(packl); ++ ++ if ((i + 1) == q->q_src_len) ++ pb->pb_next = 0; ++ else ++ pb->pb_next = htole32(dmap->d_alloc.dma_paddr + ++ offsetof(struct ubsec_dmachunk, d_sbuf[j])); ++ j++; ++ } ++ ++ if (enccrd == NULL && maccrd != NULL) { ++ /* Authentication only */ ++ dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr = 0; ++ dmap->d_dma->d_mcr.mcr_opktbuf.pb_len = 0; ++ dmap->d_dma->d_mcr.mcr_opktbuf.pb_next = ++ htole32(dmap->d_alloc.dma_paddr + ++ offsetof(struct ubsec_dmachunk, d_macbuf[0])); ++#ifdef UBSEC_DEBUG ++ DPRINTF("opkt: %x %x %x\n", ++ dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr, ++ dmap->d_dma->d_mcr.mcr_opktbuf.pb_len, ++ dmap->d_dma->d_mcr.mcr_opktbuf.pb_next); ++#endif ++ } else { ++ if (crp->crp_flags & CRYPTO_F_IOV) { ++ if (!nicealign) { ++ err = EINVAL; ++ goto errout; ++ } ++#if 0 ++ if (bus_dmamap_create(sc->sc_dmat, 0xfff0, ++ UBS_MAX_SCATTER, 0xfff0, 0, BUS_DMA_NOWAIT, ++ &q->q_dst_map) != 0) { ++ err = ENOMEM; ++ goto errout; ++ } ++ if (bus_dmamap_load_uio(sc->sc_dmat, q->q_dst_map, ++ q->q_dst_io, BUS_DMA_NOWAIT) != 0) { ++ bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); ++ q->q_dst_map = NULL; ++ goto errout; ++ } ++#endif ++ ++ /* HW shall copy the result into the source memory */ ++ for(i = 0; i < q->q_src_len; i++) ++ q->q_dst_map[i] = q->q_src_map[i]; ++ ++ q->q_dst_len = q->q_src_len; ++ q->q_has_dst = 0; ++ ++ } else if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ if (nicealign) { ++ ++ /* HW shall copy the result into the source memory */ ++ q->q_dst_m = q->q_src_m; ++ for(i = 0; i < q->q_src_len; i++) ++ q->q_dst_map[i] = q->q_src_map[i]; ++ ++ q->q_dst_len = q->q_src_len; ++ q->q_has_dst = 0; ++ ++ } else { ++#ifdef NOTYET ++ int totlen, len; ++ struct sk_buff *m, *top, **mp; ++ ++ totlen = q->q_src_map->dm_mapsize; ++ if (q->q_src_m->m_flags & M_PKTHDR) { ++ len = MHLEN; ++ MGETHDR(m, M_DONTWAIT, MT_DATA); ++ } else { ++ len = MLEN; ++ MGET(m, M_DONTWAIT, MT_DATA); ++ } ++ if (m == NULL) { ++ err = ENOMEM; ++ goto errout; ++ } ++ if (len == MHLEN) ++ M_DUP_PKTHDR(m, q->q_src_m); ++ if (totlen >= MINCLSIZE) { ++ MCLGET(m, M_DONTWAIT); ++ if (m->m_flags & M_EXT) ++ len = MCLBYTES; ++ } ++ m->m_len = len; ++ top = NULL; ++ mp = ⊤ ++ ++ while (totlen > 0) { ++ if (top) { ++ MGET(m, M_DONTWAIT, MT_DATA); ++ if (m == NULL) { ++ m_freem(top); ++ err = ENOMEM; ++ goto errout; ++ } ++ len = MLEN; ++ } ++ if (top && totlen >= MINCLSIZE) { ++ MCLGET(m, M_DONTWAIT); ++ if (m->m_flags & M_EXT) ++ len = MCLBYTES; ++ } ++ m->m_len = len = min(totlen, len); ++ totlen -= len; ++ *mp = m; ++ mp = &m->m_next; ++ } ++ q->q_dst_m = top; ++ ubsec_mcopy(q->q_src_m, q->q_dst_m, ++ cpskip, cpoffset); ++ if (bus_dmamap_create(sc->sc_dmat, 0xfff0, ++ UBS_MAX_SCATTER, 0xfff0, 0, BUS_DMA_NOWAIT, ++ &q->q_dst_map) != 0) { ++ err = ENOMEM; ++ goto errout; ++ } ++ if (bus_dmamap_load_mbuf(sc->sc_dmat, ++ q->q_dst_map, q->q_dst_m, ++ BUS_DMA_NOWAIT) != 0) { ++ bus_dmamap_destroy(sc->sc_dmat, ++ q->q_dst_map); ++ q->q_dst_map = NULL; ++ err = ENOMEM; ++ goto errout; ++ } ++#else ++ device_printf(sc->sc_dev, ++ "%s,%d: CRYPTO_F_SKBUF unaligned not implemented\n", ++ __FILE__, __LINE__); ++ err = EINVAL; ++ goto errout; ++#endif ++ } ++ } else { ++ err = EINVAL; ++ goto errout; ++ } ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("dst skip: %d\n", dskip); ++#endif ++ for (i = j = 0; i < q->q_dst_len; i++) { ++ struct ubsec_pktbuf *pb; ++ size_t packl = q->q_dst_map[i].dma_size; ++ dma_addr_t packp = q->q_dst_map[i].dma_paddr; ++ ++ if (dskip >= packl) { ++ dskip -= packl; ++ continue; ++ } ++ ++ packl -= dskip; ++ packp += dskip; ++ dskip = 0; ++ ++ if (packl > 0xfffc) { ++ DPRINTF("Error: fragment size is bigger than 0xfffc.\n"); ++ err = EIO; ++ goto errout; ++ } ++ ++ if (j == 0) ++ pb = &dmap->d_dma->d_mcr.mcr_opktbuf; ++ else ++ pb = &dmap->d_dma->d_dbuf[j - 1]; ++ ++ pb->pb_addr = htole32(packp); ++ ++ if (dtheend) { ++ if (packl > dtheend) { ++ pb->pb_len = htole32(dtheend); ++ dtheend = 0; ++ } else { ++ pb->pb_len = htole32(packl); ++ dtheend -= packl; ++ } ++ } else ++ pb->pb_len = htole32(packl); ++ ++ if ((i + 1) == q->q_dst_len) { ++ if (maccrd) ++ /* Authentication: ++ * The last fragment of the output buffer ++ * contains the HMAC. */ ++ pb->pb_next = htole32(dmap->d_alloc.dma_paddr + ++ offsetof(struct ubsec_dmachunk, d_macbuf[0])); ++ else ++ pb->pb_next = 0; ++ } else ++ pb->pb_next = htole32(dmap->d_alloc.dma_paddr + ++ offsetof(struct ubsec_dmachunk, d_dbuf[j])); ++ j++; ++ } ++ } ++ ++ dmap->d_dma->d_mcr.mcr_cmdctxp = htole32(dmap->d_alloc.dma_paddr + ++ offsetof(struct ubsec_dmachunk, d_ctx)); ++ ++ if (sc->sc_flags & UBS_FLAGS_LONGCTX) { ++ /* new Broadcom cards with dynamic long command context structure */ ++ ++ if (enccrd != NULL && ++ enccrd->crd_alg == CRYPTO_AES_CBC) ++ { ++ struct ubsec_pktctx_aes128 *ctxaes128; ++ struct ubsec_pktctx_aes192 *ctxaes192; ++ struct ubsec_pktctx_aes256 *ctxaes256; ++ ++ switch(ses->ses_keysize) ++ { ++ /* AES 128bit */ ++ case 128: ++ ctxaes128 = (struct ubsec_pktctx_aes128 *) ++ (dmap->d_alloc.dma_vaddr + ++ offsetof(struct ubsec_dmachunk, d_ctx)); ++ ++ ctxaes128->pc_len = htole16(sizeof(struct ubsec_pktctx_aes128)); ++ ctxaes128->pc_type = ctx.pc_type; ++ ctxaes128->pc_flags = ctx.pc_flags; ++ ctxaes128->pc_offset = ctx.pc_offset; ++ for (i = 0; i < 4; i++) ++ ctxaes128->pc_aeskey[i] = ctx.pc_key[i]; ++ for (i = 0; i < 5; i++) ++ ctxaes128->pc_hminner[i] = ctx.pc_hminner[i]; ++ for (i = 0; i < 5; i++) ++ ctxaes128->pc_hmouter[i] = ctx.pc_hmouter[i]; ++ for (i = 0; i < 4; i++) ++ ctxaes128->pc_iv[i] = ctx.pc_iv[i]; ++ break; ++ ++ /* AES 192bit */ ++ case 192: ++ ctxaes192 = (struct ubsec_pktctx_aes192 *) ++ (dmap->d_alloc.dma_vaddr + ++ offsetof(struct ubsec_dmachunk, d_ctx)); ++ ++ ctxaes192->pc_len = htole16(sizeof(struct ubsec_pktctx_aes192)); ++ ctxaes192->pc_type = ctx.pc_type; ++ ctxaes192->pc_flags = ctx.pc_flags; ++ ctxaes192->pc_offset = ctx.pc_offset; ++ for (i = 0; i < 6; i++) ++ ctxaes192->pc_aeskey[i] = ctx.pc_key[i]; ++ for (i = 0; i < 5; i++) ++ ctxaes192->pc_hminner[i] = ctx.pc_hminner[i]; ++ for (i = 0; i < 5; i++) ++ ctxaes192->pc_hmouter[i] = ctx.pc_hmouter[i]; ++ for (i = 0; i < 4; i++) ++ ctxaes192->pc_iv[i] = ctx.pc_iv[i]; ++ break; ++ ++ /* AES 256bit */ ++ case 256: ++ ctxaes256 = (struct ubsec_pktctx_aes256 *) ++ (dmap->d_alloc.dma_vaddr + ++ offsetof(struct ubsec_dmachunk, d_ctx)); ++ ++ ctxaes256->pc_len = htole16(sizeof(struct ubsec_pktctx_aes256)); ++ ctxaes256->pc_type = ctx.pc_type; ++ ctxaes256->pc_flags = ctx.pc_flags; ++ ctxaes256->pc_offset = ctx.pc_offset; ++ for (i = 0; i < 8; i++) ++ ctxaes256->pc_aeskey[i] = ctx.pc_key[i]; ++ for (i = 0; i < 5; i++) ++ ctxaes256->pc_hminner[i] = ctx.pc_hminner[i]; ++ for (i = 0; i < 5; i++) ++ ctxaes256->pc_hmouter[i] = ctx.pc_hmouter[i]; ++ for (i = 0; i < 4; i++) ++ ctxaes256->pc_iv[i] = ctx.pc_iv[i]; ++ break; ++ ++ } ++ } else { ++ /* ++ * [3]DES / MD5_HMAC / SHA1_HMAC ++ * ++ * MD5_HMAC / SHA1_HMAC can use the IPSEC 3DES operation without ++ * encryption. ++ */ ++ struct ubsec_pktctx_des *ctxdes; ++ ++ ctxdes = (struct ubsec_pktctx_des *)(dmap->d_alloc.dma_vaddr + ++ offsetof(struct ubsec_dmachunk, d_ctx)); ++ ++ ctxdes->pc_len = htole16(sizeof(struct ubsec_pktctx_des)); ++ ctxdes->pc_type = ctx.pc_type; ++ ctxdes->pc_flags = ctx.pc_flags; ++ ctxdes->pc_offset = ctx.pc_offset; ++ for (i = 0; i < 6; i++) ++ ctxdes->pc_deskey[i] = ctx.pc_key[i]; ++ for (i = 0; i < 5; i++) ++ ctxdes->pc_hminner[i] = ctx.pc_hminner[i]; ++ for (i = 0; i < 5; i++) ++ ctxdes->pc_hmouter[i] = ctx.pc_hmouter[i]; ++ ctxdes->pc_iv[0] = ctx.pc_iv[0]; ++ ctxdes->pc_iv[1] = ctx.pc_iv[1]; ++ } ++ } else ++ { ++ /* old Broadcom card with fixed small command context structure */ ++ ++ /* ++ * [3]DES / MD5_HMAC / SHA1_HMAC ++ */ ++ struct ubsec_pktctx *ctxs; ++ ++ ctxs = (struct ubsec_pktctx *)(dmap->d_alloc.dma_vaddr + ++ offsetof(struct ubsec_dmachunk, d_ctx)); ++ ++ /* transform generic context into small context */ ++ for (i = 0; i < 6; i++) ++ ctxs->pc_deskey[i] = ctx.pc_key[i]; ++ for (i = 0; i < 5; i++) ++ ctxs->pc_hminner[i] = ctx.pc_hminner[i]; ++ for (i = 0; i < 5; i++) ++ ctxs->pc_hmouter[i] = ctx.pc_hmouter[i]; ++ ctxs->pc_iv[0] = ctx.pc_iv[0]; ++ ctxs->pc_iv[1] = ctx.pc_iv[1]; ++ ctxs->pc_flags = ctx.pc_flags; ++ ctxs->pc_offset = ctx.pc_offset; ++ } ++ ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("spin_lock_irqsave\n"); ++#endif ++ spin_lock_irqsave(&sc->sc_ringmtx, flags); ++ //spin_lock_irq(&sc->sc_ringmtx); ++ ++ BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_queue, q, q_next); ++ sc->sc_nqueue++; ++ ubsecstats.hst_ipackets++; ++ ubsecstats.hst_ibytes += stheend; ++ ubsec_feed(sc); ++ ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("spin_unlock_irqrestore\n"); ++#endif ++ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); ++ //spin_unlock_irq(&sc->sc_ringmtx); ++ ++ return (0); ++ ++errout: ++ if (q != NULL) { ++#ifdef NOTYET ++ if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) ++ m_freem(q->q_dst_m); ++#endif ++ ++ if ((q->q_has_dst == 1) && q->q_dst_len > 0) { ++#if 0 ++ bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); ++ bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); ++#endif ++ dma_unmap(sc, q->q_dst_map, q->q_dst_len); ++ } ++ if (q->q_src_len > 0) { ++#if 0 ++ bus_dmamap_unload(sc->sc_dmat, q->q_src_map); ++ bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); ++#endif ++ dma_unmap(sc, q->q_src_map, q->q_src_len); ++ } ++ ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("spin_lock_irqsave\n"); ++#endif ++ spin_lock_irqsave(&sc->sc_ringmtx, flags); ++ //spin_lock_irq(&sc->sc_ringmtx); ++ ++ BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); ++ ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("spin_unlock_irqrestore\n"); ++#endif ++ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); ++ //spin_unlock_irq(&sc->sc_ringmtx); ++ ++ } ++ if (err == EINVAL) ++ ubsecstats.hst_invalid++; ++ else ++ ubsecstats.hst_nomem++; ++errout2: ++ crp->crp_etype = err; ++ crypto_done(crp); ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s() err = %x\n", __FUNCTION__, err); ++#endif ++ ++ return (0); ++} ++ ++void ++ubsec_callback(struct ubsec_softc *sc, struct ubsec_q *q) ++{ ++ struct cryptop *crp = (struct cryptop *)q->q_crp; ++ struct cryptodesc *crd; ++ struct ubsec_dma *dmap = q->q_dma; ++ int ivsize = 8; ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ ++ ubsecstats.hst_opackets++; ++ ubsecstats.hst_obytes += dmap->d_alloc.dma_size; ++ ++#if 0 ++ bus_dmamap_sync(sc->sc_dmat, dmap->d_alloc.dma_map, 0, ++ dmap->d_alloc.dma_map->dm_mapsize, ++ BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); ++ if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { ++ bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, ++ 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_POSTREAD); ++ bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); ++ bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); ++ } ++ bus_dmamap_sync(sc->sc_dmat, q->q_src_map, ++ 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); ++ bus_dmamap_unload(sc->sc_dmat, q->q_src_map); ++ bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); ++#endif ++ ++ if ((q->q_has_dst == 1) && q->q_dst_len > 0) ++ dma_unmap(sc, q->q_dst_map, q->q_dst_len); ++ ++ dma_unmap(sc, q->q_src_map, q->q_src_len); ++ ++#ifdef NOTYET ++ if ((crp->crp_flags & CRYPTO_F_SKBUF) && (q->q_src_m != q->q_dst_m)) { ++ m_freem(q->q_src_m); ++ crp->crp_buf = (caddr_t)q->q_dst_m; ++ } ++#endif ++ ++ /* copy out IV for future use */ ++ if (q->q_flags & UBSEC_QFLAGS_COPYOUTIV) { ++ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { ++ if (crd->crd_alg != CRYPTO_DES_CBC && ++ crd->crd_alg != CRYPTO_3DES_CBC && ++ crd->crd_alg != CRYPTO_AES_CBC) ++ continue; ++ ++ if (crd->crd_alg == CRYPTO_AES_CBC) ++ ivsize = 16; ++ else ++ ivsize = 8; ++ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) ++#if 0 ++ m_copydata((struct sk_buff *)crp->crp_buf, ++ crd->crd_skip + crd->crd_len - 8, 8, ++ (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv); ++#endif ++ crypto_copydata(crp->crp_flags, (caddr_t)crp->crp_buf, ++ crd->crd_skip + crd->crd_len - ivsize, ivsize, ++ (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv); ++ ++ else if (crp->crp_flags & CRYPTO_F_IOV) { ++#if 0 ++ cuio_copydata((struct uio *)crp->crp_buf, ++ crd->crd_skip + crd->crd_len - 8, 8, ++ (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv); ++#endif ++ crypto_copydata(crp->crp_flags, (caddr_t)crp->crp_buf, ++ crd->crd_skip + crd->crd_len - ivsize, ivsize, ++ (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv); ++ ++ } ++ break; ++ } ++ } ++ ++ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { ++ if (crd->crd_alg != CRYPTO_MD5_HMAC && ++ crd->crd_alg != CRYPTO_SHA1_HMAC) ++ continue; ++#if 0 ++ if (crp->crp_flags & CRYPTO_F_SKBUF) ++ m_copyback((struct sk_buff *)crp->crp_buf, ++ crd->crd_inject, 12, ++ dmap->d_dma->d_macbuf); ++#endif ++#if 0 ++ /* BUG? it does not honor the mac len.. */ ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ crd->crd_inject, 12, ++ (caddr_t)dmap->d_dma->d_macbuf); ++#endif ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ crd->crd_inject, ++ sc->sc_sessions[q->q_sesn].ses_mlen, ++ (caddr_t)dmap->d_dma->d_macbuf); ++#if 0 ++ else if (crp->crp_flags & CRYPTO_F_IOV && crp->crp_mac) ++ bcopy((caddr_t)dmap->d_dma->d_macbuf, ++ crp->crp_mac, 12); ++#endif ++ break; ++ } ++ BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); ++ crypto_done(crp); ++} ++ ++void ++ubsec_mcopy(struct sk_buff *srcm, struct sk_buff *dstm, int hoffset, int toffset) ++{ ++ int i, j, dlen, slen; ++ caddr_t dptr, sptr; ++ ++ j = 0; ++ sptr = srcm->data; ++ slen = srcm->len; ++ dptr = dstm->data; ++ dlen = dstm->len; ++ ++ while (1) { ++ for (i = 0; i < min(slen, dlen); i++) { ++ if (j < hoffset || j >= toffset) ++ *dptr++ = *sptr++; ++ slen--; ++ dlen--; ++ j++; ++ } ++ if (slen == 0) { ++ srcm = srcm->next; ++ if (srcm == NULL) ++ return; ++ sptr = srcm->data; ++ slen = srcm->len; ++ } ++ if (dlen == 0) { ++ dstm = dstm->next; ++ if (dstm == NULL) ++ return; ++ dptr = dstm->data; ++ dlen = dstm->len; ++ } ++ } ++} ++ ++int ++ubsec_dma_malloc(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma, ++ size_t size, int mapflags) ++{ ++ dma->dma_vaddr = dma_alloc_coherent(sc->sc_dv, ++ size, &dma->dma_paddr, GFP_KERNEL); ++ ++ if (likely(dma->dma_vaddr)) ++ { ++ dma->dma_size = size; ++ return (0); ++ } ++ ++ DPRINTF("could not allocate %d bytes of coherent memory.\n", size); ++ ++ return (1); ++} ++ ++void ++ubsec_dma_free(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma) ++{ ++ dma_free_coherent(sc->sc_dv, dma->dma_size, dma->dma_vaddr, ++ dma->dma_paddr); ++} ++ ++/* ++ * Resets the board. Values in the regesters are left as is ++ * from the reset (i.e. initial values are assigned elsewhere). ++ */ ++void ++ubsec_reset_board(struct ubsec_softc *sc) ++{ ++ volatile u_int32_t ctrl; ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ DPRINTF("Send reset signal to chip.\n"); ++ ++ ctrl = READ_REG(sc, BS_CTRL); ++ ctrl |= BS_CTRL_RESET; ++ WRITE_REG(sc, BS_CTRL, ctrl); ++ ++ /* ++ * Wait aprox. 30 PCI clocks = 900 ns = 0.9 us ++ */ ++ DELAY(10); ++} ++ ++/* ++ * Init Broadcom registers ++ */ ++void ++ubsec_init_board(struct ubsec_softc *sc) ++{ ++ u_int32_t ctrl; ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ DPRINTF("Initialize chip.\n"); ++ ++ ctrl = READ_REG(sc, BS_CTRL); ++ ctrl &= ~(BS_CTRL_BE32 | BS_CTRL_BE64); ++ ctrl |= BS_CTRL_LITTLE_ENDIAN | BS_CTRL_MCR1INT | BS_CTRL_DMAERR; ++ ++ WRITE_REG(sc, BS_CTRL, ctrl); ++ ++ /* Set chip capabilities (BCM5365P) */ ++ sc->sc_flags |= UBS_FLAGS_LONGCTX | UBS_FLAGS_AES; ++} ++ ++/* ++ * Clean up after a chip crash. ++ * It is assumed that the caller has spin_lock_irq(sc_ringmtx). ++ */ ++void ++ubsec_cleanchip(struct ubsec_softc *sc) ++{ ++ struct ubsec_q *q; ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ DPRINTF("Clean up queues after chip crash.\n"); ++ ++ while (!BSD_SIMPLEQ_EMPTY(&sc->sc_qchip)) { ++ q = BSD_SIMPLEQ_FIRST(&sc->sc_qchip); ++ BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q_next); ++ ubsec_free_q(sc, q); ++ } ++} ++ ++/* ++ * free a ubsec_q ++ * It is assumed that the caller has spin_lock_irq(sc_ringmtx). ++ */ ++int ++ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q) ++{ ++ struct ubsec_q *q2; ++ struct cryptop *crp; ++ int npkts; ++ int i; ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ ++ npkts = q->q_nstacked_mcrs; ++ ++ for (i = 0; i < npkts; i++) { ++ if(q->q_stacked_mcr[i]) { ++ q2 = q->q_stacked_mcr[i]; ++ ++ if ((q2->q_dst_m != NULL) && (q2->q_src_m != q2->q_dst_m)) ++#ifdef NOTYET ++ m_freem(q2->q_dst_m); ++#else ++ printk(KERN_ERR "%s,%d: SKB not supported\n", __FILE__, __LINE__); ++#endif ++ ++ crp = (struct cryptop *)q2->q_crp; ++ ++ BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q2, q_next); ++ ++ crp->crp_etype = EFAULT; ++ crypto_done(crp); ++ } else { ++ break; ++ } ++ } ++ ++ /* ++ * Free header MCR ++ */ ++ if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) ++#ifdef NOTYET ++ m_freem(q->q_dst_m); ++#else ++ printk(KERN_ERR "%s,%d: SKB not supported\n", __FILE__, __LINE__); ++#endif ++ ++ crp = (struct cryptop *)q->q_crp; ++ ++ BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); ++ ++ crp->crp_etype = EFAULT; ++ crypto_done(crp); ++ return(0); ++} ++ ++/* ++ * Routine to reset the chip and clean up. ++ * It is assumed that the caller has spin_lock_irq(sc_ringmtx). ++ */ ++void ++ubsec_totalreset(struct ubsec_softc *sc) ++{ ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ DPRINTF("initiate total chip reset.. \n"); ++ ubsec_reset_board(sc); ++ ubsec_init_board(sc); ++ ubsec_cleanchip(sc); ++} ++ ++void ++ubsec_dump_pb(struct ubsec_pktbuf *pb) ++{ ++ printf("addr 0x%x (0x%x) next 0x%x\n", ++ pb->pb_addr, pb->pb_len, pb->pb_next); ++} ++ ++void ++ubsec_dump_mcr(struct ubsec_mcr *mcr) ++{ ++ struct ubsec_mcr_add *ma; ++ int i; ++ ++ printf("MCR:\n"); ++ printf(" pkts: %u, flags 0x%x\n", ++ letoh16(mcr->mcr_pkts), letoh16(mcr->mcr_flags)); ++ ma = (struct ubsec_mcr_add *)&mcr->mcr_cmdctxp; ++ for (i = 0; i < letoh16(mcr->mcr_pkts); i++) { ++ printf(" %d: ctx 0x%x len 0x%x rsvd 0x%x\n", i, ++ letoh32(ma->mcr_cmdctxp), letoh16(ma->mcr_pktlen), ++ letoh16(ma->mcr_reserved)); ++ printf(" %d: ipkt ", i); ++ ubsec_dump_pb(&ma->mcr_ipktbuf); ++ printf(" %d: opkt ", i); ++ ubsec_dump_pb(&ma->mcr_opktbuf); ++ ma++; ++ } ++ printf("END MCR\n"); ++} ++ ++static int __init mod_init(void) { ++ return ssb_driver_register(&ubsec_ssb_driver); ++} ++ ++static void __exit mod_exit(void) { ++ ssb_driver_unregister(&ubsec_ssb_driver); ++} ++ ++module_init(mod_init); ++module_exit(mod_exit); ++ ++// Meta information ++MODULE_AUTHOR("Daniel Mueller "); ++MODULE_LICENSE("BSD"); ++MODULE_DESCRIPTION("OCF driver for BCM5365P IPSec Core"); ++MODULE_VERSION(DRV_MODULE_VERSION); ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/ubsec_ssb/ubsecreg.h linux-3.0.4/crypto/ocf/ubsec_ssb/ubsecreg.h +--- linux-3.0.4.orig/crypto/ocf/ubsec_ssb/ubsecreg.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/ubsec_ssb/ubsecreg.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,233 @@ ++ ++/* ++ * Copyright (c) 2008 Daniel Mueller (daniel@danm.de) ++ * Copyright (c) 2000 Theo de Raadt ++ * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com) ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored in part by the Defense Advanced Research Projects ++ * Agency (DARPA) and Air Force Research Laboratory, Air Force ++ * Materiel Command, USAF, under agreement number F30602-01-2-0537. ++ * ++ */ ++ ++/* ++ * Register definitions for 5601 BlueSteel Networks Ubiquitous Broadband ++ * Security "uBSec" chip. Definitions from revision 2.8 of the product ++ * datasheet. ++ */ ++ ++#define BS_BAR 0x10 /* DMA base address register */ ++#define BS_TRDY_TIMEOUT 0x40 /* TRDY timeout */ ++#define BS_RETRY_TIMEOUT 0x41 /* DMA retry timeout */ ++ ++#define UBS_PCI_RTY_SHIFT 8 ++#define UBS_PCI_RTY_MASK 0xff ++#define UBS_PCI_RTY(misc) \ ++ (((misc) >> UBS_PCI_RTY_SHIFT) & UBS_PCI_RTY_MASK) ++ ++#define UBS_PCI_TOUT_SHIFT 0 ++#define UBS_PCI_TOUT_MASK 0xff ++#define UBS_PCI_TOUT(misc) \ ++ (((misc) >> PCI_TOUT_SHIFT) & PCI_TOUT_MASK) ++ ++/* ++ * DMA Control & Status Registers (offset from BS_BAR) ++ */ ++#define BS_MCR1 0x20 /* DMA Master Command Record 1 */ ++#define BS_CTRL 0x24 /* DMA Control */ ++#define BS_STAT 0x28 /* DMA Status */ ++#define BS_ERR 0x2c /* DMA Error Address */ ++#define BS_DEV_ID 0x34 /* IPSec Device ID */ ++ ++/* BS_CTRL - DMA Control */ ++#define BS_CTRL_RESET 0x80000000 /* hardware reset, 5805/5820 */ ++#define BS_CTRL_MCR2INT 0x40000000 /* enable intr MCR for MCR2 */ ++#define BS_CTRL_MCR1INT 0x20000000 /* enable intr MCR for MCR1 */ ++#define BS_CTRL_OFM 0x10000000 /* Output fragment mode */ ++#define BS_CTRL_BE32 0x08000000 /* big-endian, 32bit bytes */ ++#define BS_CTRL_BE64 0x04000000 /* big-endian, 64bit bytes */ ++#define BS_CTRL_DMAERR 0x02000000 /* enable intr DMA error */ ++#define BS_CTRL_RNG_M 0x01800000 /* RNG mode */ ++#define BS_CTRL_RNG_1 0x00000000 /* 1bit rn/one slow clock */ ++#define BS_CTRL_RNG_4 0x00800000 /* 1bit rn/four slow clocks */ ++#define BS_CTRL_RNG_8 0x01000000 /* 1bit rn/eight slow clocks */ ++#define BS_CTRL_RNG_16 0x01800000 /* 1bit rn/16 slow clocks */ ++#define BS_CTRL_SWNORM 0x00400000 /* 582[01], sw normalization */ ++#define BS_CTRL_FRAG_M 0x0000ffff /* output fragment size mask */ ++#define BS_CTRL_LITTLE_ENDIAN (BS_CTRL_BE32 | BS_CTRL_BE64) ++ ++/* BS_STAT - DMA Status */ ++#define BS_STAT_MCR1_BUSY 0x80000000 /* MCR1 is busy */ ++#define BS_STAT_MCR1_FULL 0x40000000 /* MCR1 is full */ ++#define BS_STAT_MCR1_DONE 0x20000000 /* MCR1 is done */ ++#define BS_STAT_DMAERR 0x10000000 /* DMA error */ ++#define BS_STAT_MCR2_FULL 0x08000000 /* MCR2 is full */ ++#define BS_STAT_MCR2_DONE 0x04000000 /* MCR2 is done */ ++#define BS_STAT_MCR1_ALLEMPTY 0x02000000 /* 5821, MCR1 is empty */ ++#define BS_STAT_MCR2_ALLEMPTY 0x01000000 /* 5821, MCR2 is empty */ ++ ++/* BS_ERR - DMA Error Address */ ++#define BS_ERR_ADDR 0xfffffffc /* error address mask */ ++#define BS_ERR_READ 0x00000002 /* fault was on read */ ++ ++struct ubsec_pktctx { ++ u_int32_t pc_deskey[6]; /* 3DES key */ ++ u_int32_t pc_hminner[5]; /* hmac inner state */ ++ u_int32_t pc_hmouter[5]; /* hmac outer state */ ++ u_int32_t pc_iv[2]; /* [3]DES iv */ ++ u_int16_t pc_flags; /* flags, below */ ++ u_int16_t pc_offset; /* crypto offset */ ++} __attribute__ ((packed)); ++ ++#define UBS_PKTCTX_ENC_3DES 0x8000 /* use 3des */ ++#define UBS_PKTCTX_ENC_AES 0x8000 /* use aes */ ++#define UBS_PKTCTX_ENC_NONE 0x0000 /* no encryption */ ++#define UBS_PKTCTX_INBOUND 0x4000 /* inbound packet */ ++#define UBS_PKTCTX_AUTH 0x3000 /* authentication mask */ ++#define UBS_PKTCTX_AUTH_NONE 0x0000 /* no authentication */ ++#define UBS_PKTCTX_AUTH_MD5 0x1000 /* use hmac-md5 */ ++#define UBS_PKTCTX_AUTH_SHA1 0x2000 /* use hmac-sha1 */ ++#define UBS_PKTCTX_AES128 0x0 /* AES 128bit keys */ ++#define UBS_PKTCTX_AES192 0x100 /* AES 192bit keys */ ++#define UBS_PKTCTX_AES256 0x200 /* AES 256bit keys */ ++ ++struct ubsec_pktctx_des { ++ volatile u_int16_t pc_len; /* length of ctx struct */ ++ volatile u_int16_t pc_type; /* context type */ ++ volatile u_int16_t pc_flags; /* flags, same as above */ ++ volatile u_int16_t pc_offset; /* crypto/auth offset */ ++ volatile u_int32_t pc_deskey[6]; /* 3DES key */ ++ volatile u_int32_t pc_iv[2]; /* [3]DES iv */ ++ volatile u_int32_t pc_hminner[5]; /* hmac inner state */ ++ volatile u_int32_t pc_hmouter[5]; /* hmac outer state */ ++} __attribute__ ((packed)); ++ ++struct ubsec_pktctx_aes128 { ++ volatile u_int16_t pc_len; /* length of ctx struct */ ++ volatile u_int16_t pc_type; /* context type */ ++ volatile u_int16_t pc_flags; /* flags, same as above */ ++ volatile u_int16_t pc_offset; /* crypto/auth offset */ ++ volatile u_int32_t pc_aeskey[4]; /* AES 128bit key */ ++ volatile u_int32_t pc_iv[4]; /* AES iv */ ++ volatile u_int32_t pc_hminner[5]; /* hmac inner state */ ++ volatile u_int32_t pc_hmouter[5]; /* hmac outer state */ ++} __attribute__ ((packed)); ++ ++struct ubsec_pktctx_aes192 { ++ volatile u_int16_t pc_len; /* length of ctx struct */ ++ volatile u_int16_t pc_type; /* context type */ ++ volatile u_int16_t pc_flags; /* flags, same as above */ ++ volatile u_int16_t pc_offset; /* crypto/auth offset */ ++ volatile u_int32_t pc_aeskey[6]; /* AES 192bit key */ ++ volatile u_int32_t pc_iv[4]; /* AES iv */ ++ volatile u_int32_t pc_hminner[5]; /* hmac inner state */ ++ volatile u_int32_t pc_hmouter[5]; /* hmac outer state */ ++} __attribute__ ((packed)); ++ ++struct ubsec_pktctx_aes256 { ++ volatile u_int16_t pc_len; /* length of ctx struct */ ++ volatile u_int16_t pc_type; /* context type */ ++ volatile u_int16_t pc_flags; /* flags, same as above */ ++ volatile u_int16_t pc_offset; /* crypto/auth offset */ ++ volatile u_int32_t pc_aeskey[8]; /* AES 256bit key */ ++ volatile u_int32_t pc_iv[4]; /* AES iv */ ++ volatile u_int32_t pc_hminner[5]; /* hmac inner state */ ++ volatile u_int32_t pc_hmouter[5]; /* hmac outer state */ ++} __attribute__ ((packed)); ++ ++#define UBS_PKTCTX_TYPE_IPSEC_DES 0x0000 ++#define UBS_PKTCTX_TYPE_IPSEC_AES 0x0040 ++ ++struct ubsec_pktbuf { ++ volatile u_int32_t pb_addr; /* address of buffer start */ ++ volatile u_int32_t pb_next; /* pointer to next pktbuf */ ++ volatile u_int32_t pb_len; /* packet length */ ++} __attribute__ ((packed)); ++#define UBS_PKTBUF_LEN 0x0000ffff /* length mask */ ++ ++struct ubsec_mcr { ++ volatile u_int16_t mcr_pkts; /* #pkts in this mcr */ ++ volatile u_int16_t mcr_flags; /* mcr flags (below) */ ++ volatile u_int32_t mcr_cmdctxp; /* command ctx pointer */ ++ struct ubsec_pktbuf mcr_ipktbuf; /* input chain header */ ++ volatile u_int16_t mcr_reserved; ++ volatile u_int16_t mcr_pktlen; ++ struct ubsec_pktbuf mcr_opktbuf; /* output chain header */ ++} __attribute__ ((packed)); ++ ++struct ubsec_mcr_add { ++ volatile u_int32_t mcr_cmdctxp; /* command ctx pointer */ ++ struct ubsec_pktbuf mcr_ipktbuf; /* input chain header */ ++ volatile u_int16_t mcr_reserved; ++ volatile u_int16_t mcr_pktlen; ++ struct ubsec_pktbuf mcr_opktbuf; /* output chain header */ ++} __attribute__ ((packed)); ++ ++#define UBS_MCR_DONE 0x0001 /* mcr has been processed */ ++#define UBS_MCR_ERROR 0x0002 /* error in processing */ ++#define UBS_MCR_ERRORCODE 0xff00 /* error type */ ++ ++struct ubsec_ctx_keyop { ++ volatile u_int16_t ctx_len; /* command length */ ++ volatile u_int16_t ctx_op; /* operation code */ ++ volatile u_int8_t ctx_pad[60]; /* padding */ ++} __attribute__ ((packed)); ++#define UBS_CTXOP_DHPKGEN 0x01 /* dh public key generation */ ++#define UBS_CTXOP_DHSSGEN 0x02 /* dh shared secret gen. */ ++#define UBS_CTXOP_RSAPUB 0x03 /* rsa public key op */ ++#define UBS_CTXOP_RSAPRIV 0x04 /* rsa private key op */ ++#define UBS_CTXOP_DSASIGN 0x05 /* dsa signing op */ ++#define UBS_CTXOP_DSAVRFY 0x06 /* dsa verification */ ++#define UBS_CTXOP_RNGBYPASS 0x41 /* rng direct test mode */ ++#define UBS_CTXOP_RNGSHA1 0x42 /* rng sha1 test mode */ ++#define UBS_CTXOP_MODADD 0x43 /* modular addition */ ++#define UBS_CTXOP_MODSUB 0x44 /* modular subtraction */ ++#define UBS_CTXOP_MODMUL 0x45 /* modular multiplication */ ++#define UBS_CTXOP_MODRED 0x46 /* modular reduction */ ++#define UBS_CTXOP_MODEXP 0x47 /* modular exponentiation */ ++#define UBS_CTXOP_MODINV 0x48 /* modular inverse */ ++ ++struct ubsec_ctx_rngbypass { ++ volatile u_int16_t rbp_len; /* command length, 64 */ ++ volatile u_int16_t rbp_op; /* rng bypass, 0x41 */ ++ volatile u_int8_t rbp_pad[60]; /* padding */ ++} __attribute__ ((packed)); ++ ++/* modexp: C = (M ^ E) mod N */ ++struct ubsec_ctx_modexp { ++ volatile u_int16_t me_len; /* command length */ ++ volatile u_int16_t me_op; /* modexp, 0x47 */ ++ volatile u_int16_t me_E_len; /* E (bits) */ ++ volatile u_int16_t me_N_len; /* N (bits) */ ++ u_int8_t me_N[2048/8]; /* N */ ++} __attribute__ ((packed)); ++ ++struct ubsec_ctx_rsapriv { ++ volatile u_int16_t rpr_len; /* command length */ ++ volatile u_int16_t rpr_op; /* rsaprivate, 0x04 */ ++ volatile u_int16_t rpr_q_len; /* q (bits) */ ++ volatile u_int16_t rpr_p_len; /* p (bits) */ ++ u_int8_t rpr_buf[5 * 1024 / 8]; /* parameters: */ ++ /* p, q, dp, dq, pinv */ ++} __attribute__ ((packed)); +diff -Nur linux-3.0.4.orig/crypto/ocf/ubsec_ssb/ubsecvar.h linux-3.0.4/crypto/ocf/ubsec_ssb/ubsecvar.h +--- linux-3.0.4.orig/crypto/ocf/ubsec_ssb/ubsecvar.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/ubsec_ssb/ubsecvar.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,228 @@ ++ ++/* ++ * Copyright (c) 2008 Daniel Mueller (daniel@danm.de) ++ * Copyright (c) 2000 Theo de Raadt ++ * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com) ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored in part by the Defense Advanced Research Projects ++ * Agency (DARPA) and Air Force Research Laboratory, Air Force ++ * Materiel Command, USAF, under agreement number F30602-01-2-0537. ++ * ++ */ ++ ++/* Maximum queue length */ ++#ifndef UBS_MAX_NQUEUE ++#define UBS_MAX_NQUEUE 60 ++#endif ++ ++#define UBS_MAX_SCATTER 64 /* Maximum scatter/gather depth */ ++ ++#ifndef UBS_MAX_AGGR ++#define UBS_MAX_AGGR 5 /* Maximum aggregation count */ ++#endif ++ ++#define UBSEC_CARD(sid) (((sid) & 0xf0000000) >> 28) ++#define UBSEC_SESSION(sid) ( (sid) & 0x0fffffff) ++#define UBSEC_SID(crd, sesn) (((crd) << 28) | ((sesn) & 0x0fffffff)) ++ ++#define UBS_DEF_RTY 0xff /* PCI Retry Timeout */ ++#define UBS_DEF_TOUT 0xff /* PCI TRDY Timeout */ ++#define UBS_DEF_CACHELINE 0x01 /* Cache Line setting */ ++ ++#define DEFAULT_HMAC_LEN 12 ++ ++struct ubsec_dma_alloc { ++ dma_addr_t dma_paddr; ++ void *dma_vaddr; ++ /* ++ bus_dmamap_t dma_map; ++ bus_dma_segment_t dma_seg; ++ */ ++ size_t dma_size; ++ /* ++ int dma_nseg; ++ */ ++}; ++ ++struct ubsec_q2 { ++ BSD_SIMPLEQ_ENTRY(ubsec_q2) q_next; ++ struct ubsec_dma_alloc q_mcr; ++ struct ubsec_dma_alloc q_ctx; ++ u_int q_type; ++}; ++ ++struct ubsec_q2_rng { ++ struct ubsec_q2 rng_q; ++ struct ubsec_dma_alloc rng_buf; ++ int rng_used; ++}; ++ ++/* C = (M ^ E) mod N */ ++#define UBS_MODEXP_PAR_M 0 ++#define UBS_MODEXP_PAR_E 1 ++#define UBS_MODEXP_PAR_N 2 ++struct ubsec_q2_modexp { ++ struct ubsec_q2 me_q; ++ struct cryptkop * me_krp; ++ struct ubsec_dma_alloc me_M; ++ struct ubsec_dma_alloc me_E; ++ struct ubsec_dma_alloc me_C; ++ struct ubsec_dma_alloc me_epb; ++ int me_modbits; ++ int me_shiftbits; ++ int me_normbits; ++}; ++ ++#define UBS_RSAPRIV_PAR_P 0 ++#define UBS_RSAPRIV_PAR_Q 1 ++#define UBS_RSAPRIV_PAR_DP 2 ++#define UBS_RSAPRIV_PAR_DQ 3 ++#define UBS_RSAPRIV_PAR_PINV 4 ++#define UBS_RSAPRIV_PAR_MSGIN 5 ++#define UBS_RSAPRIV_PAR_MSGOUT 6 ++struct ubsec_q2_rsapriv { ++ struct ubsec_q2 rpr_q; ++ struct cryptkop * rpr_krp; ++ struct ubsec_dma_alloc rpr_msgin; ++ struct ubsec_dma_alloc rpr_msgout; ++}; ++ ++#define UBSEC_RNG_BUFSIZ 16 /* measured in 32bit words */ ++ ++struct ubsec_dmachunk { ++ struct ubsec_mcr d_mcr; ++ struct ubsec_mcr_add d_mcradd[UBS_MAX_AGGR-1]; ++ struct ubsec_pktbuf d_sbuf[UBS_MAX_SCATTER-1]; ++ struct ubsec_pktbuf d_dbuf[UBS_MAX_SCATTER-1]; ++ u_int32_t d_macbuf[5]; ++ union { ++ struct ubsec_pktctx_aes256 ctxaes256; ++ struct ubsec_pktctx_aes192 ctxaes192; ++ struct ubsec_pktctx_des ctxdes; ++ struct ubsec_pktctx_aes128 ctxaes128; ++ struct ubsec_pktctx ctx; ++ } d_ctx; ++}; ++ ++struct ubsec_dma { ++ BSD_SIMPLEQ_ENTRY(ubsec_dma) d_next; ++ struct ubsec_dmachunk *d_dma; ++ struct ubsec_dma_alloc d_alloc; ++}; ++ ++#define UBS_FLAGS_KEY 0x01 /* has key accelerator */ ++#define UBS_FLAGS_LONGCTX 0x02 /* uses long ipsec ctx */ ++#define UBS_FLAGS_BIGKEY 0x04 /* 2048bit keys */ ++#define UBS_FLAGS_HWNORM 0x08 /* hardware normalization */ ++#define UBS_FLAGS_RNG 0x10 /* hardware rng */ ++#define UBS_FLAGS_AES 0x20 /* hardware AES support */ ++ ++struct ubsec_q { ++ BSD_SIMPLEQ_ENTRY(ubsec_q) q_next; ++ int q_nstacked_mcrs; ++ struct ubsec_q *q_stacked_mcr[UBS_MAX_AGGR-1]; ++ struct cryptop *q_crp; ++ struct ubsec_dma *q_dma; ++ ++ //struct mbuf *q_src_m, *q_dst_m; ++ struct sk_buff *q_src_m, *q_dst_m; ++ struct uio *q_src_io, *q_dst_io; ++ ++ /* ++ bus_dmamap_t q_src_map; ++ bus_dmamap_t q_dst_map; ++ */ ++ ++ /* DMA addresses for In-/Out packages */ ++ int q_src_len; ++ int q_dst_len; ++ struct ubsec_dma_alloc q_src_map[UBS_MAX_SCATTER]; ++ struct ubsec_dma_alloc q_dst_map[UBS_MAX_SCATTER]; ++ int q_has_dst; ++ ++ int q_sesn; ++ int q_flags; ++}; ++ ++struct ubsec_softc { ++ softc_device_decl sc_dev; ++ struct ssb_device *sdev; /* device backpointer */ ++ ++ struct device *sc_dv; /* generic device */ ++ void *sc_ih; /* interrupt handler cookie */ ++ int sc_flags; /* device specific flags */ ++ u_int32_t sc_statmask; /* interrupt status mask */ ++ int32_t sc_cid; /* crypto tag */ ++ BSD_SIMPLEQ_HEAD(,ubsec_q) sc_queue; /* packet queue, mcr1 */ ++ int sc_nqueue; /* count enqueued, mcr1 */ ++ BSD_SIMPLEQ_HEAD(,ubsec_q) sc_qchip; /* on chip, mcr1 */ ++ BSD_SIMPLEQ_HEAD(,ubsec_q) sc_freequeue; /* list of free queue elements */ ++ BSD_SIMPLEQ_HEAD(,ubsec_q2) sc_queue2; /* packet queue, mcr2 */ ++ int sc_nqueue2; /* count enqueued, mcr2 */ ++ BSD_SIMPLEQ_HEAD(,ubsec_q2) sc_qchip2; /* on chip, mcr2 */ ++ int sc_nsessions; /* # of sessions */ ++ struct ubsec_session *sc_sessions; /* sessions */ ++ int sc_rnghz; /* rng poll time */ ++ struct ubsec_q2_rng sc_rng; ++ struct ubsec_dma sc_dmaa[UBS_MAX_NQUEUE]; ++ struct ubsec_q *sc_queuea[UBS_MAX_NQUEUE]; ++ BSD_SIMPLEQ_HEAD(,ubsec_q2) sc_q2free; /* free list */ ++ spinlock_t sc_ringmtx; /* PE ring lock */ ++}; ++ ++#define UBSEC_QFLAGS_COPYOUTIV 0x1 ++ ++struct ubsec_session { ++ u_int32_t ses_used; ++ u_int32_t ses_key[8]; /* 3DES/AES key */ ++ u_int32_t ses_hminner[5]; /* hmac inner state */ ++ u_int32_t ses_hmouter[5]; /* hmac outer state */ ++ u_int32_t ses_iv[4]; /* [3]DES/AES iv */ ++ u_int32_t ses_keysize; /* AES key size */ ++ u_int32_t ses_mlen; /* hmac/hash length */ ++}; ++ ++struct ubsec_stats { ++ u_int64_t hst_ibytes; ++ u_int64_t hst_obytes; ++ u_int32_t hst_ipackets; ++ u_int32_t hst_opackets; ++ u_int32_t hst_invalid; ++ u_int32_t hst_nomem; ++ u_int32_t hst_queuefull; ++ u_int32_t hst_dmaerr; ++ u_int32_t hst_mcrerr; ++ u_int32_t hst_nodmafree; ++}; ++ ++struct ubsec_generic_ctx { ++ u_int32_t pc_key[8]; /* [3]DES/AES key */ ++ u_int32_t pc_hminner[5]; /* hmac inner state */ ++ u_int32_t pc_hmouter[5]; /* hmac outer state */ ++ u_int32_t pc_iv[4]; /* [3]DES/AES iv */ ++ u_int16_t pc_flags; /* flags, below */ ++ u_int16_t pc_offset; /* crypto offset */ ++ u_int16_t pc_type; /* Cryptographic operation */ ++}; ++ +diff -Nur linux-3.0.4.orig/crypto/ocf/uio.h linux-3.0.4/crypto/ocf/uio.h +--- linux-3.0.4.orig/crypto/ocf/uio.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/crypto/ocf/uio.h 2011-07-20 02:01:53.000000000 +0200 +@@ -0,0 +1,54 @@ ++#ifndef _OCF_UIO_H_ ++#define _OCF_UIO_H_ ++ ++#include ++ ++/* ++ * The linux uio.h doesn't have all we need. To be fully api compatible ++ * with the BSD cryptodev, we need to keep this around. Perhaps this can ++ * be moved back into the linux/uio.h ++ * ++ * Linux port done by David McCullough ++ * Copyright (C) 2006-2010 David McCullough ++ * Copyright (C) 2004-2005 Intel Corporation. ++ * ++ * LICENSE TERMS ++ * ++ * The free distribution and use of this software in both source and binary ++ * form is allowed (with or without changes) provided that: ++ * ++ * 1. distributions of this source code include the above copyright ++ * notice, this list of conditions and the following disclaimer; ++ * ++ * 2. distributions in binary form include the above copyright ++ * notice, this list of conditions and the following disclaimer ++ * in the documentation and/or other associated materials; ++ * ++ * 3. the copyright holder's name is not used to endorse products ++ * built using this software without specific written permission. ++ * ++ * ALTERNATIVELY, provided that this notice is retained in full, this product ++ * may be distributed under the terms of the GNU General Public License (GPL), ++ * in which case the provisions of the GPL apply INSTEAD OF those given above. ++ * ++ * DISCLAIMER ++ * ++ * This software is provided 'as is' with no explicit or implied warranties ++ * in respect of its properties, including, but not limited to, correctness ++ * and/or fitness for purpose. ++ * --------------------------------------------------------------------------- ++ */ ++ ++struct uio { ++ struct iovec *uio_iov; ++ int uio_iovcnt; ++ off_t uio_offset; ++ int uio_resid; ++#if 0 ++ enum uio_seg uio_segflg; ++ enum uio_rw uio_rw; ++ struct thread *uio_td; ++#endif ++}; ++ ++#endif +diff -Nur linux-3.0.4.orig/drivers/char/random.c linux-3.0.4/drivers/char/random.c +--- linux-3.0.4.orig/drivers/char/random.c 2011-08-29 22:56:30.000000000 +0200 ++++ linux-3.0.4/drivers/char/random.c 2011-10-17 04:36:27.356574299 +0200 +@@ -130,6 +130,9 @@ + * void add_interrupt_randomness(int irq); + * void add_disk_randomness(struct gendisk *disk); + * ++ * void random_input_words(__u32 *buf, size_t wordcount, int ent_count) ++ * int random_input_wait(void); ++ * + * add_input_randomness() uses the input layer interrupt timing, as well as + * the event type information from the hardware. + * +@@ -147,6 +150,13 @@ + * seek times do not make for good sources of entropy, as their seek + * times are usually fairly consistent. + * ++ * random_input_words() just provides a raw block of entropy to the input ++ * pool, such as from a hardware entropy generator. ++ * ++ * random_input_wait() suspends the caller until such time as the ++ * entropy pool falls below the write threshold, and returns a count of how ++ * much entropy (in bits) is needed to sustain the pool. ++ * + * All of these routines try to estimate how many bits of randomness a + * particular randomness source. They do this by keeping track of the + * first and second order deltas of the event timings. +@@ -722,6 +732,63 @@ + } + #endif + ++/* ++ * random_input_words - add bulk entropy to pool ++ * ++ * @buf: buffer to add ++ * @wordcount: number of __u32 words to add ++ * @ent_count: total amount of entropy (in bits) to credit ++ * ++ * this provides bulk input of entropy to the input pool ++ * ++ */ ++void random_input_words(__u32 *buf, size_t wordcount, int ent_count) ++{ ++ mix_pool_bytes(&input_pool, buf, wordcount*4); ++ ++ credit_entropy_bits(&input_pool, ent_count); ++ ++ DEBUG_ENT("crediting %d bits => %d\n", ++ ent_count, input_pool.entropy_count); ++ /* ++ * Wake up waiting processes if we have enough ++ * entropy. ++ */ ++ if (input_pool.entropy_count >= random_read_wakeup_thresh) ++ wake_up_interruptible(&random_read_wait); ++} ++EXPORT_SYMBOL(random_input_words); ++ ++/* ++ * random_input_wait - wait until random needs entropy ++ * ++ * this function sleeps until the /dev/random subsystem actually ++ * needs more entropy, and then return the amount of entropy ++ * that it would be nice to have added to the system. ++ */ ++int random_input_wait(void) ++{ ++ int count; ++ ++ wait_event_interruptible(random_write_wait, ++ input_pool.entropy_count < random_write_wakeup_thresh); ++ ++ count = random_write_wakeup_thresh - input_pool.entropy_count; ++ ++ /* likely we got woken up due to a signal */ ++ if (count <= 0) count = random_read_wakeup_thresh; ++ ++ DEBUG_ENT("requesting %d bits from input_wait()er %d<%d\n", ++ count, ++ input_pool.entropy_count, random_write_wakeup_thresh); ++ ++ return count; ++} ++EXPORT_SYMBOL(random_input_wait); ++ ++ ++#define EXTRACT_SIZE 10 ++ + /********************************************************************* + * + * Entropy extraction routines +diff -Nur linux-3.0.4.orig/drivers/char/random.c.orig linux-3.0.4/drivers/char/random.c.orig +--- linux-3.0.4.orig/drivers/char/random.c.orig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/drivers/char/random.c.orig 2011-08-29 22:56:30.000000000 +0200 +@@ -0,0 +1,1349 @@ ++/* ++ * random.c -- A strong random number generator ++ * ++ * Copyright Matt Mackall , 2003, 2004, 2005 ++ * ++ * Copyright Theodore Ts'o, 1994, 1995, 1996, 1997, 1998, 1999. All ++ * rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, and the entire permission notice in its entirety, ++ * including the disclaimer of warranties. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote ++ * products derived from this software without specific prior ++ * written permission. ++ * ++ * ALTERNATIVELY, this product may be distributed under the terms of ++ * the GNU General Public License, in which case the provisions of the GPL are ++ * required INSTEAD OF the above restrictions. (This clause is ++ * necessary due to a potential bad interaction between the GPL and ++ * the restrictions contained in a BSD-style copyright.) ++ * ++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED ++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ALL OF ++ * WHICH ARE HEREBY DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ++ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ++ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE ++ * USE OF THIS SOFTWARE, EVEN IF NOT ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ */ ++ ++/* ++ * (now, with legal B.S. out of the way.....) ++ * ++ * This routine gathers environmental noise from device drivers, etc., ++ * and returns good random numbers, suitable for cryptographic use. ++ * Besides the obvious cryptographic uses, these numbers are also good ++ * for seeding TCP sequence numbers, and other places where it is ++ * desirable to have numbers which are not only random, but hard to ++ * predict by an attacker. ++ * ++ * Theory of operation ++ * =================== ++ * ++ * Computers are very predictable devices. Hence it is extremely hard ++ * to produce truly random numbers on a computer --- as opposed to ++ * pseudo-random numbers, which can easily generated by using a ++ * algorithm. Unfortunately, it is very easy for attackers to guess ++ * the sequence of pseudo-random number generators, and for some ++ * applications this is not acceptable. So instead, we must try to ++ * gather "environmental noise" from the computer's environment, which ++ * must be hard for outside attackers to observe, and use that to ++ * generate random numbers. In a Unix environment, this is best done ++ * from inside the kernel. ++ * ++ * Sources of randomness from the environment include inter-keyboard ++ * timings, inter-interrupt timings from some interrupts, and other ++ * events which are both (a) non-deterministic and (b) hard for an ++ * outside observer to measure. Randomness from these sources are ++ * added to an "entropy pool", which is mixed using a CRC-like function. ++ * This is not cryptographically strong, but it is adequate assuming ++ * the randomness is not chosen maliciously, and it is fast enough that ++ * the overhead of doing it on every interrupt is very reasonable. ++ * As random bytes are mixed into the entropy pool, the routines keep ++ * an *estimate* of how many bits of randomness have been stored into ++ * the random number generator's internal state. ++ * ++ * When random bytes are desired, they are obtained by taking the SHA ++ * hash of the contents of the "entropy pool". The SHA hash avoids ++ * exposing the internal state of the entropy pool. It is believed to ++ * be computationally infeasible to derive any useful information ++ * about the input of SHA from its output. Even if it is possible to ++ * analyze SHA in some clever way, as long as the amount of data ++ * returned from the generator is less than the inherent entropy in ++ * the pool, the output data is totally unpredictable. For this ++ * reason, the routine decreases its internal estimate of how many ++ * bits of "true randomness" are contained in the entropy pool as it ++ * outputs random numbers. ++ * ++ * If this estimate goes to zero, the routine can still generate ++ * random numbers; however, an attacker may (at least in theory) be ++ * able to infer the future output of the generator from prior ++ * outputs. This requires successful cryptanalysis of SHA, which is ++ * not believed to be feasible, but there is a remote possibility. ++ * Nonetheless, these numbers should be useful for the vast majority ++ * of purposes. ++ * ++ * Exported interfaces ---- output ++ * =============================== ++ * ++ * There are three exported interfaces; the first is one designed to ++ * be used from within the kernel: ++ * ++ * void get_random_bytes(void *buf, int nbytes); ++ * ++ * This interface will return the requested number of random bytes, ++ * and place it in the requested buffer. ++ * ++ * The two other interfaces are two character devices /dev/random and ++ * /dev/urandom. /dev/random is suitable for use when very high ++ * quality randomness is desired (for example, for key generation or ++ * one-time pads), as it will only return a maximum of the number of ++ * bits of randomness (as estimated by the random number generator) ++ * contained in the entropy pool. ++ * ++ * The /dev/urandom device does not have this limit, and will return ++ * as many bytes as are requested. As more and more random bytes are ++ * requested without giving time for the entropy pool to recharge, ++ * this will result in random numbers that are merely cryptographically ++ * strong. For many applications, however, this is acceptable. ++ * ++ * Exported interfaces ---- input ++ * ============================== ++ * ++ * The current exported interfaces for gathering environmental noise ++ * from the devices are: ++ * ++ * void add_input_randomness(unsigned int type, unsigned int code, ++ * unsigned int value); ++ * void add_interrupt_randomness(int irq); ++ * void add_disk_randomness(struct gendisk *disk); ++ * ++ * add_input_randomness() uses the input layer interrupt timing, as well as ++ * the event type information from the hardware. ++ * ++ * add_interrupt_randomness() uses the inter-interrupt timing as random ++ * inputs to the entropy pool. Note that not all interrupts are good ++ * sources of randomness! For example, the timer interrupts is not a ++ * good choice, because the periodicity of the interrupts is too ++ * regular, and hence predictable to an attacker. Network Interface ++ * Controller interrupts are a better measure, since the timing of the ++ * NIC interrupts are more unpredictable. ++ * ++ * add_disk_randomness() uses what amounts to the seek time of block ++ * layer request events, on a per-disk_devt basis, as input to the ++ * entropy pool. Note that high-speed solid state drives with very low ++ * seek times do not make for good sources of entropy, as their seek ++ * times are usually fairly consistent. ++ * ++ * All of these routines try to estimate how many bits of randomness a ++ * particular randomness source. They do this by keeping track of the ++ * first and second order deltas of the event timings. ++ * ++ * Ensuring unpredictability at system startup ++ * ============================================ ++ * ++ * When any operating system starts up, it will go through a sequence ++ * of actions that are fairly predictable by an adversary, especially ++ * if the start-up does not involve interaction with a human operator. ++ * This reduces the actual number of bits of unpredictability in the ++ * entropy pool below the value in entropy_count. In order to ++ * counteract this effect, it helps to carry information in the ++ * entropy pool across shut-downs and start-ups. To do this, put the ++ * following lines an appropriate script which is run during the boot ++ * sequence: ++ * ++ * echo "Initializing random number generator..." ++ * random_seed=/var/run/random-seed ++ * # Carry a random seed from start-up to start-up ++ * # Load and then save the whole entropy pool ++ * if [ -f $random_seed ]; then ++ * cat $random_seed >/dev/urandom ++ * else ++ * touch $random_seed ++ * fi ++ * chmod 600 $random_seed ++ * dd if=/dev/urandom of=$random_seed count=1 bs=512 ++ * ++ * and the following lines in an appropriate script which is run as ++ * the system is shutdown: ++ * ++ * # Carry a random seed from shut-down to start-up ++ * # Save the whole entropy pool ++ * echo "Saving random seed..." ++ * random_seed=/var/run/random-seed ++ * touch $random_seed ++ * chmod 600 $random_seed ++ * dd if=/dev/urandom of=$random_seed count=1 bs=512 ++ * ++ * For example, on most modern systems using the System V init ++ * scripts, such code fragments would be found in ++ * /etc/rc.d/init.d/random. On older Linux systems, the correct script ++ * location might be in /etc/rcb.d/rc.local or /etc/rc.d/rc.0. ++ * ++ * Effectively, these commands cause the contents of the entropy pool ++ * to be saved at shut-down time and reloaded into the entropy pool at ++ * start-up. (The 'dd' in the addition to the bootup script is to ++ * make sure that /etc/random-seed is different for every start-up, ++ * even if the system crashes without executing rc.0.) Even with ++ * complete knowledge of the start-up activities, predicting the state ++ * of the entropy pool requires knowledge of the previous history of ++ * the system. ++ * ++ * Configuring the /dev/random driver under Linux ++ * ============================================== ++ * ++ * The /dev/random driver under Linux uses minor numbers 8 and 9 of ++ * the /dev/mem major number (#1). So if your system does not have ++ * /dev/random and /dev/urandom created already, they can be created ++ * by using the commands: ++ * ++ * mknod /dev/random c 1 8 ++ * mknod /dev/urandom c 1 9 ++ * ++ * Acknowledgements: ++ * ================= ++ * ++ * Ideas for constructing this random number generator were derived ++ * from Pretty Good Privacy's random number generator, and from private ++ * discussions with Phil Karn. Colin Plumb provided a faster random ++ * number generator, which speed up the mixing function of the entropy ++ * pool, taken from PGPfone. Dale Worley has also contributed many ++ * useful ideas and suggestions to improve this driver. ++ * ++ * Any flaws in the design are solely my responsibility, and should ++ * not be attributed to the Phil, Colin, or any of authors of PGP. ++ * ++ * Further background information on this topic may be obtained from ++ * RFC 1750, "Randomness Recommendations for Security", by Donald ++ * Eastlake, Steve Crocker, and Jeff Schiller. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifdef CONFIG_GENERIC_HARDIRQS ++# include ++#endif ++ ++#include ++#include ++#include ++#include ++ ++/* ++ * Configuration information ++ */ ++#define INPUT_POOL_WORDS 128 ++#define OUTPUT_POOL_WORDS 32 ++#define SEC_XFER_SIZE 512 ++#define EXTRACT_SIZE 10 ++ ++/* ++ * The minimum number of bits of entropy before we wake up a read on ++ * /dev/random. Should be enough to do a significant reseed. ++ */ ++static int random_read_wakeup_thresh = 64; ++ ++/* ++ * If the entropy count falls under this number of bits, then we ++ * should wake up processes which are selecting or polling on write ++ * access to /dev/random. ++ */ ++static int random_write_wakeup_thresh = 128; ++ ++/* ++ * When the input pool goes over trickle_thresh, start dropping most ++ * samples to avoid wasting CPU time and reduce lock contention. ++ */ ++ ++static int trickle_thresh __read_mostly = INPUT_POOL_WORDS * 28; ++ ++static DEFINE_PER_CPU(int, trickle_count); ++ ++/* ++ * A pool of size .poolwords is stirred with a primitive polynomial ++ * of degree .poolwords over GF(2). The taps for various sizes are ++ * defined below. They are chosen to be evenly spaced (minimum RMS ++ * distance from evenly spaced; the numbers in the comments are a ++ * scaled squared error sum) except for the last tap, which is 1 to ++ * get the twisting happening as fast as possible. ++ */ ++static struct poolinfo { ++ int poolwords; ++ int tap1, tap2, tap3, tap4, tap5; ++} poolinfo_table[] = { ++ /* x^128 + x^103 + x^76 + x^51 +x^25 + x + 1 -- 105 */ ++ { 128, 103, 76, 51, 25, 1 }, ++ /* x^32 + x^26 + x^20 + x^14 + x^7 + x + 1 -- 15 */ ++ { 32, 26, 20, 14, 7, 1 }, ++#if 0 ++ /* x^2048 + x^1638 + x^1231 + x^819 + x^411 + x + 1 -- 115 */ ++ { 2048, 1638, 1231, 819, 411, 1 }, ++ ++ /* x^1024 + x^817 + x^615 + x^412 + x^204 + x + 1 -- 290 */ ++ { 1024, 817, 615, 412, 204, 1 }, ++ ++ /* x^1024 + x^819 + x^616 + x^410 + x^207 + x^2 + 1 -- 115 */ ++ { 1024, 819, 616, 410, 207, 2 }, ++ ++ /* x^512 + x^411 + x^308 + x^208 + x^104 + x + 1 -- 225 */ ++ { 512, 411, 308, 208, 104, 1 }, ++ ++ /* x^512 + x^409 + x^307 + x^206 + x^102 + x^2 + 1 -- 95 */ ++ { 512, 409, 307, 206, 102, 2 }, ++ /* x^512 + x^409 + x^309 + x^205 + x^103 + x^2 + 1 -- 95 */ ++ { 512, 409, 309, 205, 103, 2 }, ++ ++ /* x^256 + x^205 + x^155 + x^101 + x^52 + x + 1 -- 125 */ ++ { 256, 205, 155, 101, 52, 1 }, ++ ++ /* x^128 + x^103 + x^78 + x^51 + x^27 + x^2 + 1 -- 70 */ ++ { 128, 103, 78, 51, 27, 2 }, ++ ++ /* x^64 + x^52 + x^39 + x^26 + x^14 + x + 1 -- 15 */ ++ { 64, 52, 39, 26, 14, 1 }, ++#endif ++}; ++ ++#define POOLBITS poolwords*32 ++#define POOLBYTES poolwords*4 ++ ++/* ++ * For the purposes of better mixing, we use the CRC-32 polynomial as ++ * well to make a twisted Generalized Feedback Shift Reigster ++ * ++ * (See M. Matsumoto & Y. Kurita, 1992. Twisted GFSR generators. ACM ++ * Transactions on Modeling and Computer Simulation 2(3):179-194. ++ * Also see M. Matsumoto & Y. Kurita, 1994. Twisted GFSR generators ++ * II. ACM Transactions on Mdeling and Computer Simulation 4:254-266) ++ * ++ * Thanks to Colin Plumb for suggesting this. ++ * ++ * We have not analyzed the resultant polynomial to prove it primitive; ++ * in fact it almost certainly isn't. Nonetheless, the irreducible factors ++ * of a random large-degree polynomial over GF(2) are more than large enough ++ * that periodicity is not a concern. ++ * ++ * The input hash is much less sensitive than the output hash. All ++ * that we want of it is that it be a good non-cryptographic hash; ++ * i.e. it not produce collisions when fed "random" data of the sort ++ * we expect to see. As long as the pool state differs for different ++ * inputs, we have preserved the input entropy and done a good job. ++ * The fact that an intelligent attacker can construct inputs that ++ * will produce controlled alterations to the pool's state is not ++ * important because we don't consider such inputs to contribute any ++ * randomness. The only property we need with respect to them is that ++ * the attacker can't increase his/her knowledge of the pool's state. ++ * Since all additions are reversible (knowing the final state and the ++ * input, you can reconstruct the initial state), if an attacker has ++ * any uncertainty about the initial state, he/she can only shuffle ++ * that uncertainty about, but never cause any collisions (which would ++ * decrease the uncertainty). ++ * ++ * The chosen system lets the state of the pool be (essentially) the input ++ * modulo the generator polymnomial. Now, for random primitive polynomials, ++ * this is a universal class of hash functions, meaning that the chance ++ * of a collision is limited by the attacker's knowledge of the generator ++ * polynomail, so if it is chosen at random, an attacker can never force ++ * a collision. Here, we use a fixed polynomial, but we *can* assume that ++ * ###--> it is unknown to the processes generating the input entropy. <-### ++ * Because of this important property, this is a good, collision-resistant ++ * hash; hash collisions will occur no more often than chance. ++ */ ++ ++/* ++ * Static global variables ++ */ ++static DECLARE_WAIT_QUEUE_HEAD(random_read_wait); ++static DECLARE_WAIT_QUEUE_HEAD(random_write_wait); ++static struct fasync_struct *fasync; ++ ++#if 0 ++static int debug; ++module_param(debug, bool, 0644); ++#define DEBUG_ENT(fmt, arg...) do { \ ++ if (debug) \ ++ printk(KERN_DEBUG "random %04d %04d %04d: " \ ++ fmt,\ ++ input_pool.entropy_count,\ ++ blocking_pool.entropy_count,\ ++ nonblocking_pool.entropy_count,\ ++ ## arg); } while (0) ++#else ++#define DEBUG_ENT(fmt, arg...) do {} while (0) ++#endif ++ ++/********************************************************************** ++ * ++ * OS independent entropy store. Here are the functions which handle ++ * storing entropy in an entropy pool. ++ * ++ **********************************************************************/ ++ ++struct entropy_store; ++struct entropy_store { ++ /* read-only data: */ ++ struct poolinfo *poolinfo; ++ __u32 *pool; ++ const char *name; ++ struct entropy_store *pull; ++ int limit; ++ ++ /* read-write data: */ ++ spinlock_t lock; ++ unsigned add_ptr; ++ int entropy_count; ++ int input_rotate; ++ __u8 last_data[EXTRACT_SIZE]; ++}; ++ ++static __u32 input_pool_data[INPUT_POOL_WORDS]; ++static __u32 blocking_pool_data[OUTPUT_POOL_WORDS]; ++static __u32 nonblocking_pool_data[OUTPUT_POOL_WORDS]; ++ ++static struct entropy_store input_pool = { ++ .poolinfo = &poolinfo_table[0], ++ .name = "input", ++ .limit = 1, ++ .lock = __SPIN_LOCK_UNLOCKED(&input_pool.lock), ++ .pool = input_pool_data ++}; ++ ++static struct entropy_store blocking_pool = { ++ .poolinfo = &poolinfo_table[1], ++ .name = "blocking", ++ .limit = 1, ++ .pull = &input_pool, ++ .lock = __SPIN_LOCK_UNLOCKED(&blocking_pool.lock), ++ .pool = blocking_pool_data ++}; ++ ++static struct entropy_store nonblocking_pool = { ++ .poolinfo = &poolinfo_table[1], ++ .name = "nonblocking", ++ .pull = &input_pool, ++ .lock = __SPIN_LOCK_UNLOCKED(&nonblocking_pool.lock), ++ .pool = nonblocking_pool_data ++}; ++ ++/* ++ * This function adds bytes into the entropy "pool". It does not ++ * update the entropy estimate. The caller should call ++ * credit_entropy_bits if this is appropriate. ++ * ++ * The pool is stirred with a primitive polynomial of the appropriate ++ * degree, and then twisted. We twist by three bits at a time because ++ * it's cheap to do so and helps slightly in the expected case where ++ * the entropy is concentrated in the low-order bits. ++ */ ++static void mix_pool_bytes_extract(struct entropy_store *r, const void *in, ++ int nbytes, __u8 out[64]) ++{ ++ static __u32 const twist_table[8] = { ++ 0x00000000, 0x3b6e20c8, 0x76dc4190, 0x4db26158, ++ 0xedb88320, 0xd6d6a3e8, 0x9b64c2b0, 0xa00ae278 }; ++ unsigned long i, j, tap1, tap2, tap3, tap4, tap5; ++ int input_rotate; ++ int wordmask = r->poolinfo->poolwords - 1; ++ const char *bytes = in; ++ __u32 w; ++ unsigned long flags; ++ ++ /* Taps are constant, so we can load them without holding r->lock. */ ++ tap1 = r->poolinfo->tap1; ++ tap2 = r->poolinfo->tap2; ++ tap3 = r->poolinfo->tap3; ++ tap4 = r->poolinfo->tap4; ++ tap5 = r->poolinfo->tap5; ++ ++ spin_lock_irqsave(&r->lock, flags); ++ input_rotate = r->input_rotate; ++ i = r->add_ptr; ++ ++ /* mix one byte at a time to simplify size handling and churn faster */ ++ while (nbytes--) { ++ w = rol32(*bytes++, input_rotate & 31); ++ i = (i - 1) & wordmask; ++ ++ /* XOR in the various taps */ ++ w ^= r->pool[i]; ++ w ^= r->pool[(i + tap1) & wordmask]; ++ w ^= r->pool[(i + tap2) & wordmask]; ++ w ^= r->pool[(i + tap3) & wordmask]; ++ w ^= r->pool[(i + tap4) & wordmask]; ++ w ^= r->pool[(i + tap5) & wordmask]; ++ ++ /* Mix the result back in with a twist */ ++ r->pool[i] = (w >> 3) ^ twist_table[w & 7]; ++ ++ /* ++ * Normally, we add 7 bits of rotation to the pool. ++ * At the beginning of the pool, add an extra 7 bits ++ * rotation, so that successive passes spread the ++ * input bits across the pool evenly. ++ */ ++ input_rotate += i ? 7 : 14; ++ } ++ ++ r->input_rotate = input_rotate; ++ r->add_ptr = i; ++ ++ if (out) ++ for (j = 0; j < 16; j++) ++ ((__u32 *)out)[j] = r->pool[(i - j) & wordmask]; ++ ++ spin_unlock_irqrestore(&r->lock, flags); ++} ++ ++static void mix_pool_bytes(struct entropy_store *r, const void *in, int bytes) ++{ ++ mix_pool_bytes_extract(r, in, bytes, NULL); ++} ++ ++/* ++ * Credit (or debit) the entropy store with n bits of entropy ++ */ ++static void credit_entropy_bits(struct entropy_store *r, int nbits) ++{ ++ unsigned long flags; ++ int entropy_count; ++ ++ if (!nbits) ++ return; ++ ++ spin_lock_irqsave(&r->lock, flags); ++ ++ DEBUG_ENT("added %d entropy credits to %s\n", nbits, r->name); ++ entropy_count = r->entropy_count; ++ entropy_count += nbits; ++ if (entropy_count < 0) { ++ DEBUG_ENT("negative entropy/overflow\n"); ++ entropy_count = 0; ++ } else if (entropy_count > r->poolinfo->POOLBITS) ++ entropy_count = r->poolinfo->POOLBITS; ++ r->entropy_count = entropy_count; ++ ++ /* should we wake readers? */ ++ if (r == &input_pool && entropy_count >= random_read_wakeup_thresh) { ++ wake_up_interruptible(&random_read_wait); ++ kill_fasync(&fasync, SIGIO, POLL_IN); ++ } ++ spin_unlock_irqrestore(&r->lock, flags); ++} ++ ++/********************************************************************* ++ * ++ * Entropy input management ++ * ++ *********************************************************************/ ++ ++/* There is one of these per entropy source */ ++struct timer_rand_state { ++ cycles_t last_time; ++ long last_delta, last_delta2; ++ unsigned dont_count_entropy:1; ++}; ++ ++#ifndef CONFIG_GENERIC_HARDIRQS ++ ++static struct timer_rand_state *irq_timer_state[NR_IRQS]; ++ ++static struct timer_rand_state *get_timer_rand_state(unsigned int irq) ++{ ++ return irq_timer_state[irq]; ++} ++ ++static void set_timer_rand_state(unsigned int irq, ++ struct timer_rand_state *state) ++{ ++ irq_timer_state[irq] = state; ++} ++ ++#else ++ ++static struct timer_rand_state *get_timer_rand_state(unsigned int irq) ++{ ++ struct irq_desc *desc; ++ ++ desc = irq_to_desc(irq); ++ ++ return desc->timer_rand_state; ++} ++ ++static void set_timer_rand_state(unsigned int irq, ++ struct timer_rand_state *state) ++{ ++ struct irq_desc *desc; ++ ++ desc = irq_to_desc(irq); ++ ++ desc->timer_rand_state = state; ++} ++#endif ++ ++static struct timer_rand_state input_timer_state; ++ ++/* ++ * This function adds entropy to the entropy "pool" by using timing ++ * delays. It uses the timer_rand_state structure to make an estimate ++ * of how many bits of entropy this call has added to the pool. ++ * ++ * The number "num" is also added to the pool - it should somehow describe ++ * the type of event which just happened. This is currently 0-255 for ++ * keyboard scan codes, and 256 upwards for interrupts. ++ * ++ */ ++static void add_timer_randomness(struct timer_rand_state *state, unsigned num) ++{ ++ struct { ++ cycles_t cycles; ++ long jiffies; ++ unsigned num; ++ } sample; ++ long delta, delta2, delta3; ++ ++ preempt_disable(); ++ /* if over the trickle threshold, use only 1 in 4096 samples */ ++ if (input_pool.entropy_count > trickle_thresh && ++ ((__this_cpu_inc_return(trickle_count) - 1) & 0xfff)) ++ goto out; ++ ++ sample.jiffies = jiffies; ++ sample.cycles = get_cycles(); ++ sample.num = num; ++ mix_pool_bytes(&input_pool, &sample, sizeof(sample)); ++ ++ /* ++ * Calculate number of bits of randomness we probably added. ++ * We take into account the first, second and third-order deltas ++ * in order to make our estimate. ++ */ ++ ++ if (!state->dont_count_entropy) { ++ delta = sample.jiffies - state->last_time; ++ state->last_time = sample.jiffies; ++ ++ delta2 = delta - state->last_delta; ++ state->last_delta = delta; ++ ++ delta3 = delta2 - state->last_delta2; ++ state->last_delta2 = delta2; ++ ++ if (delta < 0) ++ delta = -delta; ++ if (delta2 < 0) ++ delta2 = -delta2; ++ if (delta3 < 0) ++ delta3 = -delta3; ++ if (delta > delta2) ++ delta = delta2; ++ if (delta > delta3) ++ delta = delta3; ++ ++ /* ++ * delta is now minimum absolute delta. ++ * Round down by 1 bit on general principles, ++ * and limit entropy entimate to 12 bits. ++ */ ++ credit_entropy_bits(&input_pool, ++ min_t(int, fls(delta>>1), 11)); ++ } ++out: ++ preempt_enable(); ++} ++ ++void add_input_randomness(unsigned int type, unsigned int code, ++ unsigned int value) ++{ ++ static unsigned char last_value; ++ ++ /* ignore autorepeat and the like */ ++ if (value == last_value) ++ return; ++ ++ DEBUG_ENT("input event\n"); ++ last_value = value; ++ add_timer_randomness(&input_timer_state, ++ (type << 4) ^ code ^ (code >> 4) ^ value); ++} ++EXPORT_SYMBOL_GPL(add_input_randomness); ++ ++void add_interrupt_randomness(int irq) ++{ ++ struct timer_rand_state *state; ++ ++ state = get_timer_rand_state(irq); ++ ++ if (state == NULL) ++ return; ++ ++ DEBUG_ENT("irq event %d\n", irq); ++ add_timer_randomness(state, 0x100 + irq); ++} ++ ++#ifdef CONFIG_BLOCK ++void add_disk_randomness(struct gendisk *disk) ++{ ++ if (!disk || !disk->random) ++ return; ++ /* first major is 1, so we get >= 0x200 here */ ++ DEBUG_ENT("disk event %d:%d\n", ++ MAJOR(disk_devt(disk)), MINOR(disk_devt(disk))); ++ ++ add_timer_randomness(disk->random, 0x100 + disk_devt(disk)); ++} ++#endif ++ ++/********************************************************************* ++ * ++ * Entropy extraction routines ++ * ++ *********************************************************************/ ++ ++static ssize_t extract_entropy(struct entropy_store *r, void *buf, ++ size_t nbytes, int min, int rsvd); ++ ++/* ++ * This utility inline function is responsible for transferring entropy ++ * from the primary pool to the secondary extraction pool. We make ++ * sure we pull enough for a 'catastrophic reseed'. ++ */ ++static void xfer_secondary_pool(struct entropy_store *r, size_t nbytes) ++{ ++ __u32 tmp[OUTPUT_POOL_WORDS]; ++ ++ if (r->pull && r->entropy_count < nbytes * 8 && ++ r->entropy_count < r->poolinfo->POOLBITS) { ++ /* If we're limited, always leave two wakeup worth's BITS */ ++ int rsvd = r->limit ? 0 : random_read_wakeup_thresh/4; ++ int bytes = nbytes; ++ ++ /* pull at least as many as BYTES as wakeup BITS */ ++ bytes = max_t(int, bytes, random_read_wakeup_thresh / 8); ++ /* but never more than the buffer size */ ++ bytes = min_t(int, bytes, sizeof(tmp)); ++ ++ DEBUG_ENT("going to reseed %s with %d bits " ++ "(%d of %d requested)\n", ++ r->name, bytes * 8, nbytes * 8, r->entropy_count); ++ ++ bytes = extract_entropy(r->pull, tmp, bytes, ++ random_read_wakeup_thresh / 8, rsvd); ++ mix_pool_bytes(r, tmp, bytes); ++ credit_entropy_bits(r, bytes*8); ++ } ++} ++ ++/* ++ * These functions extracts randomness from the "entropy pool", and ++ * returns it in a buffer. ++ * ++ * The min parameter specifies the minimum amount we can pull before ++ * failing to avoid races that defeat catastrophic reseeding while the ++ * reserved parameter indicates how much entropy we must leave in the ++ * pool after each pull to avoid starving other readers. ++ * ++ * Note: extract_entropy() assumes that .poolwords is a multiple of 16 words. ++ */ ++ ++static size_t account(struct entropy_store *r, size_t nbytes, int min, ++ int reserved) ++{ ++ unsigned long flags; ++ ++ /* Hold lock while accounting */ ++ spin_lock_irqsave(&r->lock, flags); ++ ++ BUG_ON(r->entropy_count > r->poolinfo->POOLBITS); ++ DEBUG_ENT("trying to extract %d bits from %s\n", ++ nbytes * 8, r->name); ++ ++ /* Can we pull enough? */ ++ if (r->entropy_count / 8 < min + reserved) { ++ nbytes = 0; ++ } else { ++ /* If limited, never pull more than available */ ++ if (r->limit && nbytes + reserved >= r->entropy_count / 8) ++ nbytes = r->entropy_count/8 - reserved; ++ ++ if (r->entropy_count / 8 >= nbytes + reserved) ++ r->entropy_count -= nbytes*8; ++ else ++ r->entropy_count = reserved; ++ ++ if (r->entropy_count < random_write_wakeup_thresh) { ++ wake_up_interruptible(&random_write_wait); ++ kill_fasync(&fasync, SIGIO, POLL_OUT); ++ } ++ } ++ ++ DEBUG_ENT("debiting %d entropy credits from %s%s\n", ++ nbytes * 8, r->name, r->limit ? "" : " (unlimited)"); ++ ++ spin_unlock_irqrestore(&r->lock, flags); ++ ++ return nbytes; ++} ++ ++static void extract_buf(struct entropy_store *r, __u8 *out) ++{ ++ int i; ++ __u32 hash[5], workspace[SHA_WORKSPACE_WORDS]; ++ __u8 extract[64]; ++ ++ /* Generate a hash across the pool, 16 words (512 bits) at a time */ ++ sha_init(hash); ++ for (i = 0; i < r->poolinfo->poolwords; i += 16) ++ sha_transform(hash, (__u8 *)(r->pool + i), workspace); ++ ++ /* ++ * We mix the hash back into the pool to prevent backtracking ++ * attacks (where the attacker knows the state of the pool ++ * plus the current outputs, and attempts to find previous ++ * ouputs), unless the hash function can be inverted. By ++ * mixing at least a SHA1 worth of hash data back, we make ++ * brute-forcing the feedback as hard as brute-forcing the ++ * hash. ++ */ ++ mix_pool_bytes_extract(r, hash, sizeof(hash), extract); ++ ++ /* ++ * To avoid duplicates, we atomically extract a portion of the ++ * pool while mixing, and hash one final time. ++ */ ++ sha_transform(hash, extract, workspace); ++ memset(extract, 0, sizeof(extract)); ++ memset(workspace, 0, sizeof(workspace)); ++ ++ /* ++ * In case the hash function has some recognizable output ++ * pattern, we fold it in half. Thus, we always feed back ++ * twice as much data as we output. ++ */ ++ hash[0] ^= hash[3]; ++ hash[1] ^= hash[4]; ++ hash[2] ^= rol32(hash[2], 16); ++ memcpy(out, hash, EXTRACT_SIZE); ++ memset(hash, 0, sizeof(hash)); ++} ++ ++static ssize_t extract_entropy(struct entropy_store *r, void *buf, ++ size_t nbytes, int min, int reserved) ++{ ++ ssize_t ret = 0, i; ++ __u8 tmp[EXTRACT_SIZE]; ++ unsigned long flags; ++ ++ xfer_secondary_pool(r, nbytes); ++ nbytes = account(r, nbytes, min, reserved); ++ ++ while (nbytes) { ++ extract_buf(r, tmp); ++ ++ if (fips_enabled) { ++ spin_lock_irqsave(&r->lock, flags); ++ if (!memcmp(tmp, r->last_data, EXTRACT_SIZE)) ++ panic("Hardware RNG duplicated output!\n"); ++ memcpy(r->last_data, tmp, EXTRACT_SIZE); ++ spin_unlock_irqrestore(&r->lock, flags); ++ } ++ i = min_t(int, nbytes, EXTRACT_SIZE); ++ memcpy(buf, tmp, i); ++ nbytes -= i; ++ buf += i; ++ ret += i; ++ } ++ ++ /* Wipe data just returned from memory */ ++ memset(tmp, 0, sizeof(tmp)); ++ ++ return ret; ++} ++ ++static ssize_t extract_entropy_user(struct entropy_store *r, void __user *buf, ++ size_t nbytes) ++{ ++ ssize_t ret = 0, i; ++ __u8 tmp[EXTRACT_SIZE]; ++ ++ xfer_secondary_pool(r, nbytes); ++ nbytes = account(r, nbytes, 0, 0); ++ ++ while (nbytes) { ++ if (need_resched()) { ++ if (signal_pending(current)) { ++ if (ret == 0) ++ ret = -ERESTARTSYS; ++ break; ++ } ++ schedule(); ++ } ++ ++ extract_buf(r, tmp); ++ i = min_t(int, nbytes, EXTRACT_SIZE); ++ if (copy_to_user(buf, tmp, i)) { ++ ret = -EFAULT; ++ break; ++ } ++ ++ nbytes -= i; ++ buf += i; ++ ret += i; ++ } ++ ++ /* Wipe data just returned from memory */ ++ memset(tmp, 0, sizeof(tmp)); ++ ++ return ret; ++} ++ ++/* ++ * This function is the exported kernel interface. It returns some ++ * number of good random numbers, suitable for seeding TCP sequence ++ * numbers, etc. ++ */ ++void get_random_bytes(void *buf, int nbytes) ++{ ++ extract_entropy(&nonblocking_pool, buf, nbytes, 0, 0); ++} ++EXPORT_SYMBOL(get_random_bytes); ++ ++/* ++ * init_std_data - initialize pool with system data ++ * ++ * @r: pool to initialize ++ * ++ * This function clears the pool's entropy count and mixes some system ++ * data into the pool to prepare it for use. The pool is not cleared ++ * as that can only decrease the entropy in the pool. ++ */ ++static void init_std_data(struct entropy_store *r) ++{ ++ ktime_t now; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&r->lock, flags); ++ r->entropy_count = 0; ++ spin_unlock_irqrestore(&r->lock, flags); ++ ++ now = ktime_get_real(); ++ mix_pool_bytes(r, &now, sizeof(now)); ++ mix_pool_bytes(r, utsname(), sizeof(*(utsname()))); ++} ++ ++static int rand_initialize(void) ++{ ++ init_std_data(&input_pool); ++ init_std_data(&blocking_pool); ++ init_std_data(&nonblocking_pool); ++ return 0; ++} ++module_init(rand_initialize); ++ ++void rand_initialize_irq(int irq) ++{ ++ struct timer_rand_state *state; ++ ++ state = get_timer_rand_state(irq); ++ ++ if (state) ++ return; ++ ++ /* ++ * If kzalloc returns null, we just won't use that entropy ++ * source. ++ */ ++ state = kzalloc(sizeof(struct timer_rand_state), GFP_KERNEL); ++ if (state) ++ set_timer_rand_state(irq, state); ++} ++ ++#ifdef CONFIG_BLOCK ++void rand_initialize_disk(struct gendisk *disk) ++{ ++ struct timer_rand_state *state; ++ ++ /* ++ * If kzalloc returns null, we just won't use that entropy ++ * source. ++ */ ++ state = kzalloc(sizeof(struct timer_rand_state), GFP_KERNEL); ++ if (state) ++ disk->random = state; ++} ++#endif ++ ++static ssize_t ++random_read(struct file *file, char __user *buf, size_t nbytes, loff_t *ppos) ++{ ++ ssize_t n, retval = 0, count = 0; ++ ++ if (nbytes == 0) ++ return 0; ++ ++ while (nbytes > 0) { ++ n = nbytes; ++ if (n > SEC_XFER_SIZE) ++ n = SEC_XFER_SIZE; ++ ++ DEBUG_ENT("reading %d bits\n", n*8); ++ ++ n = extract_entropy_user(&blocking_pool, buf, n); ++ ++ DEBUG_ENT("read got %d bits (%d still needed)\n", ++ n*8, (nbytes-n)*8); ++ ++ if (n == 0) { ++ if (file->f_flags & O_NONBLOCK) { ++ retval = -EAGAIN; ++ break; ++ } ++ ++ DEBUG_ENT("sleeping?\n"); ++ ++ wait_event_interruptible(random_read_wait, ++ input_pool.entropy_count >= ++ random_read_wakeup_thresh); ++ ++ DEBUG_ENT("awake\n"); ++ ++ if (signal_pending(current)) { ++ retval = -ERESTARTSYS; ++ break; ++ } ++ ++ continue; ++ } ++ ++ if (n < 0) { ++ retval = n; ++ break; ++ } ++ count += n; ++ buf += n; ++ nbytes -= n; ++ break; /* This break makes the device work */ ++ /* like a named pipe */ ++ } ++ ++ return (count ? count : retval); ++} ++ ++static ssize_t ++urandom_read(struct file *file, char __user *buf, size_t nbytes, loff_t *ppos) ++{ ++ return extract_entropy_user(&nonblocking_pool, buf, nbytes); ++} ++ ++static unsigned int ++random_poll(struct file *file, poll_table * wait) ++{ ++ unsigned int mask; ++ ++ poll_wait(file, &random_read_wait, wait); ++ poll_wait(file, &random_write_wait, wait); ++ mask = 0; ++ if (input_pool.entropy_count >= random_read_wakeup_thresh) ++ mask |= POLLIN | POLLRDNORM; ++ if (input_pool.entropy_count < random_write_wakeup_thresh) ++ mask |= POLLOUT | POLLWRNORM; ++ return mask; ++} ++ ++static int ++write_pool(struct entropy_store *r, const char __user *buffer, size_t count) ++{ ++ size_t bytes; ++ __u32 buf[16]; ++ const char __user *p = buffer; ++ ++ while (count > 0) { ++ bytes = min(count, sizeof(buf)); ++ if (copy_from_user(&buf, p, bytes)) ++ return -EFAULT; ++ ++ count -= bytes; ++ p += bytes; ++ ++ mix_pool_bytes(r, buf, bytes); ++ cond_resched(); ++ } ++ ++ return 0; ++} ++ ++static ssize_t random_write(struct file *file, const char __user *buffer, ++ size_t count, loff_t *ppos) ++{ ++ size_t ret; ++ ++ ret = write_pool(&blocking_pool, buffer, count); ++ if (ret) ++ return ret; ++ ret = write_pool(&nonblocking_pool, buffer, count); ++ if (ret) ++ return ret; ++ ++ return (ssize_t)count; ++} ++ ++static long random_ioctl(struct file *f, unsigned int cmd, unsigned long arg) ++{ ++ int size, ent_count; ++ int __user *p = (int __user *)arg; ++ int retval; ++ ++ switch (cmd) { ++ case RNDGETENTCNT: ++ /* inherently racy, no point locking */ ++ if (put_user(input_pool.entropy_count, p)) ++ return -EFAULT; ++ return 0; ++ case RNDADDTOENTCNT: ++ if (!capable(CAP_SYS_ADMIN)) ++ return -EPERM; ++ if (get_user(ent_count, p)) ++ return -EFAULT; ++ credit_entropy_bits(&input_pool, ent_count); ++ return 0; ++ case RNDADDENTROPY: ++ if (!capable(CAP_SYS_ADMIN)) ++ return -EPERM; ++ if (get_user(ent_count, p++)) ++ return -EFAULT; ++ if (ent_count < 0) ++ return -EINVAL; ++ if (get_user(size, p++)) ++ return -EFAULT; ++ retval = write_pool(&input_pool, (const char __user *)p, ++ size); ++ if (retval < 0) ++ return retval; ++ credit_entropy_bits(&input_pool, ent_count); ++ return 0; ++ case RNDZAPENTCNT: ++ case RNDCLEARPOOL: ++ /* Clear the entropy pool counters. */ ++ if (!capable(CAP_SYS_ADMIN)) ++ return -EPERM; ++ rand_initialize(); ++ return 0; ++ default: ++ return -EINVAL; ++ } ++} ++ ++static int random_fasync(int fd, struct file *filp, int on) ++{ ++ return fasync_helper(fd, filp, on, &fasync); ++} ++ ++const struct file_operations random_fops = { ++ .read = random_read, ++ .write = random_write, ++ .poll = random_poll, ++ .unlocked_ioctl = random_ioctl, ++ .fasync = random_fasync, ++ .llseek = noop_llseek, ++}; ++ ++const struct file_operations urandom_fops = { ++ .read = urandom_read, ++ .write = random_write, ++ .unlocked_ioctl = random_ioctl, ++ .fasync = random_fasync, ++ .llseek = noop_llseek, ++}; ++ ++/*************************************************************** ++ * Random UUID interface ++ * ++ * Used here for a Boot ID, but can be useful for other kernel ++ * drivers. ++ ***************************************************************/ ++ ++/* ++ * Generate random UUID ++ */ ++void generate_random_uuid(unsigned char uuid_out[16]) ++{ ++ get_random_bytes(uuid_out, 16); ++ /* Set UUID version to 4 --- truly random generation */ ++ uuid_out[6] = (uuid_out[6] & 0x0F) | 0x40; ++ /* Set the UUID variant to DCE */ ++ uuid_out[8] = (uuid_out[8] & 0x3F) | 0x80; ++} ++EXPORT_SYMBOL(generate_random_uuid); ++ ++/******************************************************************** ++ * ++ * Sysctl interface ++ * ++ ********************************************************************/ ++ ++#ifdef CONFIG_SYSCTL ++ ++#include ++ ++static int min_read_thresh = 8, min_write_thresh; ++static int max_read_thresh = INPUT_POOL_WORDS * 32; ++static int max_write_thresh = INPUT_POOL_WORDS * 32; ++static char sysctl_bootid[16]; ++ ++/* ++ * These functions is used to return both the bootid UUID, and random ++ * UUID. The difference is in whether table->data is NULL; if it is, ++ * then a new UUID is generated and returned to the user. ++ * ++ * If the user accesses this via the proc interface, it will be returned ++ * as an ASCII string in the standard UUID format. If accesses via the ++ * sysctl system call, it is returned as 16 bytes of binary data. ++ */ ++static int proc_do_uuid(ctl_table *table, int write, ++ void __user *buffer, size_t *lenp, loff_t *ppos) ++{ ++ ctl_table fake_table; ++ unsigned char buf[64], tmp_uuid[16], *uuid; ++ ++ uuid = table->data; ++ if (!uuid) { ++ uuid = tmp_uuid; ++ uuid[8] = 0; ++ } ++ if (uuid[8] == 0) ++ generate_random_uuid(uuid); ++ ++ sprintf(buf, "%pU", uuid); ++ ++ fake_table.data = buf; ++ fake_table.maxlen = sizeof(buf); ++ ++ return proc_dostring(&fake_table, write, buffer, lenp, ppos); ++} ++ ++static int sysctl_poolsize = INPUT_POOL_WORDS * 32; ++ctl_table random_table[] = { ++ { ++ .procname = "poolsize", ++ .data = &sysctl_poolsize, ++ .maxlen = sizeof(int), ++ .mode = 0444, ++ .proc_handler = proc_dointvec, ++ }, ++ { ++ .procname = "entropy_avail", ++ .maxlen = sizeof(int), ++ .mode = 0444, ++ .proc_handler = proc_dointvec, ++ .data = &input_pool.entropy_count, ++ }, ++ { ++ .procname = "read_wakeup_threshold", ++ .data = &random_read_wakeup_thresh, ++ .maxlen = sizeof(int), ++ .mode = 0644, ++ .proc_handler = proc_dointvec_minmax, ++ .extra1 = &min_read_thresh, ++ .extra2 = &max_read_thresh, ++ }, ++ { ++ .procname = "write_wakeup_threshold", ++ .data = &random_write_wakeup_thresh, ++ .maxlen = sizeof(int), ++ .mode = 0644, ++ .proc_handler = proc_dointvec_minmax, ++ .extra1 = &min_write_thresh, ++ .extra2 = &max_write_thresh, ++ }, ++ { ++ .procname = "boot_id", ++ .data = &sysctl_bootid, ++ .maxlen = 16, ++ .mode = 0444, ++ .proc_handler = proc_do_uuid, ++ }, ++ { ++ .procname = "uuid", ++ .maxlen = 16, ++ .mode = 0444, ++ .proc_handler = proc_do_uuid, ++ }, ++ { } ++}; ++#endif /* CONFIG_SYSCTL */ ++ ++static u32 random_int_secret[MD5_MESSAGE_BYTES / 4] ____cacheline_aligned; ++ ++static int __init random_int_secret_init(void) ++{ ++ get_random_bytes(random_int_secret, sizeof(random_int_secret)); ++ return 0; ++} ++late_initcall(random_int_secret_init); ++ ++/* ++ * Get a random word for internal kernel use only. Similar to urandom but ++ * with the goal of minimal entropy pool depletion. As a result, the random ++ * value is not cryptographically secure but for several uses the cost of ++ * depleting entropy is too high ++ */ ++DEFINE_PER_CPU(__u32 [MD5_DIGEST_WORDS], get_random_int_hash); ++unsigned int get_random_int(void) ++{ ++ __u32 *hash = get_cpu_var(get_random_int_hash); ++ unsigned int ret; ++ ++ hash[0] += current->pid + jiffies + get_cycles(); ++ md5_transform(hash, random_int_secret); ++ ret = hash[0]; ++ put_cpu_var(get_random_int_hash); ++ ++ return ret; ++} ++ ++/* ++ * randomize_range() returns a start address such that ++ * ++ * [...... .....] ++ * start end ++ * ++ * a with size "len" starting at the return value is inside in the ++ * area defined by [start, end], but is otherwise randomized. ++ */ ++unsigned long ++randomize_range(unsigned long start, unsigned long end, unsigned long len) ++{ ++ unsigned long range = end - len - start; ++ ++ if (end <= start + len) ++ return 0; ++ return PAGE_ALIGN(get_random_int() % range + start); ++} +diff -Nur linux-3.0.4.orig/fs/fcntl.c linux-3.0.4/fs/fcntl.c +--- linux-3.0.4.orig/fs/fcntl.c 2011-08-29 22:56:30.000000000 +0200 ++++ linux-3.0.4/fs/fcntl.c 2011-10-17 04:36:27.356574299 +0200 +@@ -142,6 +142,7 @@ + } + return ret; + } ++EXPORT_SYMBOL(sys_dup); + + #define SETFL_MASK (O_APPEND | O_NONBLOCK | O_NDELAY | O_DIRECT | O_NOATIME) + +diff -Nur linux-3.0.4.orig/include/linux/miscdevice.h linux-3.0.4/include/linux/miscdevice.h +--- linux-3.0.4.orig/include/linux/miscdevice.h 2011-08-29 22:56:30.000000000 +0200 ++++ linux-3.0.4/include/linux/miscdevice.h 2011-10-17 04:36:27.356574299 +0200 +@@ -18,6 +18,7 @@ + #define APOLLO_MOUSE_MINOR 7 + #define PC110PAD_MINOR 9 + /*#define ADB_MOUSE_MINOR 10 FIXME OBSOLETE */ ++#define CRYPTODEV_MINOR 70 /* /dev/crypto */ + #define WATCHDOG_MINOR 130 /* Watchdog timer */ + #define TEMP_MINOR 131 /* Temperature Sensor */ + #define RTC_MINOR 135 +diff -Nur linux-3.0.4.orig/include/linux/random.h linux-3.0.4/include/linux/random.h +--- linux-3.0.4.orig/include/linux/random.h 2011-08-29 22:56:30.000000000 +0200 ++++ linux-3.0.4/include/linux/random.h 2011-10-17 04:36:27.356574299 +0200 +@@ -54,6 +54,10 @@ + unsigned int value); + extern void add_interrupt_randomness(int irq); + ++extern void random_input_words(__u32 *buf, size_t wordcount, int ent_count); ++extern int random_input_wait(void); ++#define HAS_RANDOM_INPUT_WAIT 1 ++ + extern void get_random_bytes(void *buf, int nbytes); + void generate_random_uuid(unsigned char uuid_out[16]); + +diff -Nur linux-3.0.4.orig/kernel/pid.c linux-3.0.4/kernel/pid.c +--- linux-3.0.4.orig/kernel/pid.c 2011-08-29 22:56:30.000000000 +0200 ++++ linux-3.0.4/kernel/pid.c 2011-10-17 04:36:27.356574299 +0200 +@@ -427,6 +427,7 @@ + { + return find_task_by_pid_ns(vnr, current->nsproxy->pid_ns); + } ++EXPORT_SYMBOL(find_task_by_vpid); + + struct pid *get_task_pid(struct task_struct *task, enum pid_type type) + { +diff -Nur linux-3.0.4.orig/kernel/pid.c.orig linux-3.0.4/kernel/pid.c.orig +--- linux-3.0.4.orig/kernel/pid.c.orig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.0.4/kernel/pid.c.orig 2011-08-29 22:56:30.000000000 +0200 +@@ -0,0 +1,570 @@ ++/* ++ * Generic pidhash and scalable, time-bounded PID allocator ++ * ++ * (C) 2002-2003 William Irwin, IBM ++ * (C) 2004 William Irwin, Oracle ++ * (C) 2002-2004 Ingo Molnar, Red Hat ++ * ++ * pid-structures are backing objects for tasks sharing a given ID to chain ++ * against. There is very little to them aside from hashing them and ++ * parking tasks using given ID's on a list. ++ * ++ * The hash is always changed with the tasklist_lock write-acquired, ++ * and the hash is only accessed with the tasklist_lock at least ++ * read-acquired, so there's no additional SMP locking needed here. ++ * ++ * We have a list of bitmap pages, which bitmaps represent the PID space. ++ * Allocating and freeing PIDs is completely lockless. The worst-case ++ * allocation scenario when all but one out of 1 million PIDs possible are ++ * allocated already: the scanning of 32 list entries and at most PAGE_SIZE ++ * bytes. The typical fastpath is a single successful setbit. Freeing is O(1). ++ * ++ * Pid namespaces: ++ * (C) 2007 Pavel Emelyanov , OpenVZ, SWsoft Inc. ++ * (C) 2007 Sukadev Bhattiprolu , IBM ++ * Many thanks to Oleg Nesterov for comments and help ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define pid_hashfn(nr, ns) \ ++ hash_long((unsigned long)nr + (unsigned long)ns, pidhash_shift) ++static struct hlist_head *pid_hash; ++static unsigned int pidhash_shift = 4; ++struct pid init_struct_pid = INIT_STRUCT_PID; ++ ++int pid_max = PID_MAX_DEFAULT; ++ ++#define RESERVED_PIDS 300 ++ ++int pid_max_min = RESERVED_PIDS + 1; ++int pid_max_max = PID_MAX_LIMIT; ++ ++#define BITS_PER_PAGE (PAGE_SIZE*8) ++#define BITS_PER_PAGE_MASK (BITS_PER_PAGE-1) ++ ++static inline int mk_pid(struct pid_namespace *pid_ns, ++ struct pidmap *map, int off) ++{ ++ return (map - pid_ns->pidmap)*BITS_PER_PAGE + off; ++} ++ ++#define find_next_offset(map, off) \ ++ find_next_zero_bit((map)->page, BITS_PER_PAGE, off) ++ ++/* ++ * PID-map pages start out as NULL, they get allocated upon ++ * first use and are never deallocated. This way a low pid_max ++ * value does not cause lots of bitmaps to be allocated, but ++ * the scheme scales to up to 4 million PIDs, runtime. ++ */ ++struct pid_namespace init_pid_ns = { ++ .kref = { ++ .refcount = ATOMIC_INIT(2), ++ }, ++ .pidmap = { ++ [ 0 ... PIDMAP_ENTRIES-1] = { ATOMIC_INIT(BITS_PER_PAGE), NULL } ++ }, ++ .last_pid = 0, ++ .level = 0, ++ .child_reaper = &init_task, ++}; ++EXPORT_SYMBOL_GPL(init_pid_ns); ++ ++int is_container_init(struct task_struct *tsk) ++{ ++ int ret = 0; ++ struct pid *pid; ++ ++ rcu_read_lock(); ++ pid = task_pid(tsk); ++ if (pid != NULL && pid->numbers[pid->level].nr == 1) ++ ret = 1; ++ rcu_read_unlock(); ++ ++ return ret; ++} ++EXPORT_SYMBOL(is_container_init); ++ ++/* ++ * Note: disable interrupts while the pidmap_lock is held as an ++ * interrupt might come in and do read_lock(&tasklist_lock). ++ * ++ * If we don't disable interrupts there is a nasty deadlock between ++ * detach_pid()->free_pid() and another cpu that does ++ * spin_lock(&pidmap_lock) followed by an interrupt routine that does ++ * read_lock(&tasklist_lock); ++ * ++ * After we clean up the tasklist_lock and know there are no ++ * irq handlers that take it we can leave the interrupts enabled. ++ * For now it is easier to be safe than to prove it can't happen. ++ */ ++ ++static __cacheline_aligned_in_smp DEFINE_SPINLOCK(pidmap_lock); ++ ++static void free_pidmap(struct upid *upid) ++{ ++ int nr = upid->nr; ++ struct pidmap *map = upid->ns->pidmap + nr / BITS_PER_PAGE; ++ int offset = nr & BITS_PER_PAGE_MASK; ++ ++ clear_bit(offset, map->page); ++ atomic_inc(&map->nr_free); ++} ++ ++/* ++ * If we started walking pids at 'base', is 'a' seen before 'b'? ++ */ ++static int pid_before(int base, int a, int b) ++{ ++ /* ++ * This is the same as saying ++ * ++ * (a - base + MAXUINT) % MAXUINT < (b - base + MAXUINT) % MAXUINT ++ * and that mapping orders 'a' and 'b' with respect to 'base'. ++ */ ++ return (unsigned)(a - base) < (unsigned)(b - base); ++} ++ ++/* ++ * We might be racing with someone else trying to set pid_ns->last_pid. ++ * We want the winner to have the "later" value, because if the ++ * "earlier" value prevails, then a pid may get reused immediately. ++ * ++ * Since pids rollover, it is not sufficient to just pick the bigger ++ * value. We have to consider where we started counting from. ++ * ++ * 'base' is the value of pid_ns->last_pid that we observed when ++ * we started looking for a pid. ++ * ++ * 'pid' is the pid that we eventually found. ++ */ ++static void set_last_pid(struct pid_namespace *pid_ns, int base, int pid) ++{ ++ int prev; ++ int last_write = base; ++ do { ++ prev = last_write; ++ last_write = cmpxchg(&pid_ns->last_pid, prev, pid); ++ } while ((prev != last_write) && (pid_before(base, last_write, pid))); ++} ++ ++static int alloc_pidmap(struct pid_namespace *pid_ns) ++{ ++ int i, offset, max_scan, pid, last = pid_ns->last_pid; ++ struct pidmap *map; ++ ++ pid = last + 1; ++ if (pid >= pid_max) ++ pid = RESERVED_PIDS; ++ offset = pid & BITS_PER_PAGE_MASK; ++ map = &pid_ns->pidmap[pid/BITS_PER_PAGE]; ++ /* ++ * If last_pid points into the middle of the map->page we ++ * want to scan this bitmap block twice, the second time ++ * we start with offset == 0 (or RESERVED_PIDS). ++ */ ++ max_scan = DIV_ROUND_UP(pid_max, BITS_PER_PAGE) - !offset; ++ for (i = 0; i <= max_scan; ++i) { ++ if (unlikely(!map->page)) { ++ void *page = kzalloc(PAGE_SIZE, GFP_KERNEL); ++ /* ++ * Free the page if someone raced with us ++ * installing it: ++ */ ++ spin_lock_irq(&pidmap_lock); ++ if (!map->page) { ++ map->page = page; ++ page = NULL; ++ } ++ spin_unlock_irq(&pidmap_lock); ++ kfree(page); ++ if (unlikely(!map->page)) ++ break; ++ } ++ if (likely(atomic_read(&map->nr_free))) { ++ do { ++ if (!test_and_set_bit(offset, map->page)) { ++ atomic_dec(&map->nr_free); ++ set_last_pid(pid_ns, last, pid); ++ return pid; ++ } ++ offset = find_next_offset(map, offset); ++ pid = mk_pid(pid_ns, map, offset); ++ } while (offset < BITS_PER_PAGE && pid < pid_max); ++ } ++ if (map < &pid_ns->pidmap[(pid_max-1)/BITS_PER_PAGE]) { ++ ++map; ++ offset = 0; ++ } else { ++ map = &pid_ns->pidmap[0]; ++ offset = RESERVED_PIDS; ++ if (unlikely(last == offset)) ++ break; ++ } ++ pid = mk_pid(pid_ns, map, offset); ++ } ++ return -1; ++} ++ ++int next_pidmap(struct pid_namespace *pid_ns, unsigned int last) ++{ ++ int offset; ++ struct pidmap *map, *end; ++ ++ if (last >= PID_MAX_LIMIT) ++ return -1; ++ ++ offset = (last + 1) & BITS_PER_PAGE_MASK; ++ map = &pid_ns->pidmap[(last + 1)/BITS_PER_PAGE]; ++ end = &pid_ns->pidmap[PIDMAP_ENTRIES]; ++ for (; map < end; map++, offset = 0) { ++ if (unlikely(!map->page)) ++ continue; ++ offset = find_next_bit((map)->page, BITS_PER_PAGE, offset); ++ if (offset < BITS_PER_PAGE) ++ return mk_pid(pid_ns, map, offset); ++ } ++ return -1; ++} ++ ++void put_pid(struct pid *pid) ++{ ++ struct pid_namespace *ns; ++ ++ if (!pid) ++ return; ++ ++ ns = pid->numbers[pid->level].ns; ++ if ((atomic_read(&pid->count) == 1) || ++ atomic_dec_and_test(&pid->count)) { ++ kmem_cache_free(ns->pid_cachep, pid); ++ put_pid_ns(ns); ++ } ++} ++EXPORT_SYMBOL_GPL(put_pid); ++ ++static void delayed_put_pid(struct rcu_head *rhp) ++{ ++ struct pid *pid = container_of(rhp, struct pid, rcu); ++ put_pid(pid); ++} ++ ++void free_pid(struct pid *pid) ++{ ++ /* We can be called with write_lock_irq(&tasklist_lock) held */ ++ int i; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&pidmap_lock, flags); ++ for (i = 0; i <= pid->level; i++) ++ hlist_del_rcu(&pid->numbers[i].pid_chain); ++ spin_unlock_irqrestore(&pidmap_lock, flags); ++ ++ for (i = 0; i <= pid->level; i++) ++ free_pidmap(pid->numbers + i); ++ ++ call_rcu(&pid->rcu, delayed_put_pid); ++} ++ ++struct pid *alloc_pid(struct pid_namespace *ns) ++{ ++ struct pid *pid; ++ enum pid_type type; ++ int i, nr; ++ struct pid_namespace *tmp; ++ struct upid *upid; ++ ++ pid = kmem_cache_alloc(ns->pid_cachep, GFP_KERNEL); ++ if (!pid) ++ goto out; ++ ++ tmp = ns; ++ for (i = ns->level; i >= 0; i--) { ++ nr = alloc_pidmap(tmp); ++ if (nr < 0) ++ goto out_free; ++ ++ pid->numbers[i].nr = nr; ++ pid->numbers[i].ns = tmp; ++ tmp = tmp->parent; ++ } ++ ++ get_pid_ns(ns); ++ pid->level = ns->level; ++ atomic_set(&pid->count, 1); ++ for (type = 0; type < PIDTYPE_MAX; ++type) ++ INIT_HLIST_HEAD(&pid->tasks[type]); ++ ++ upid = pid->numbers + ns->level; ++ spin_lock_irq(&pidmap_lock); ++ for ( ; upid >= pid->numbers; --upid) ++ hlist_add_head_rcu(&upid->pid_chain, ++ &pid_hash[pid_hashfn(upid->nr, upid->ns)]); ++ spin_unlock_irq(&pidmap_lock); ++ ++out: ++ return pid; ++ ++out_free: ++ while (++i <= ns->level) ++ free_pidmap(pid->numbers + i); ++ ++ kmem_cache_free(ns->pid_cachep, pid); ++ pid = NULL; ++ goto out; ++} ++ ++struct pid *find_pid_ns(int nr, struct pid_namespace *ns) ++{ ++ struct hlist_node *elem; ++ struct upid *pnr; ++ ++ hlist_for_each_entry_rcu(pnr, elem, ++ &pid_hash[pid_hashfn(nr, ns)], pid_chain) ++ if (pnr->nr == nr && pnr->ns == ns) ++ return container_of(pnr, struct pid, ++ numbers[ns->level]); ++ ++ return NULL; ++} ++EXPORT_SYMBOL_GPL(find_pid_ns); ++ ++struct pid *find_vpid(int nr) ++{ ++ return find_pid_ns(nr, current->nsproxy->pid_ns); ++} ++EXPORT_SYMBOL_GPL(find_vpid); ++ ++/* ++ * attach_pid() must be called with the tasklist_lock write-held. ++ */ ++void attach_pid(struct task_struct *task, enum pid_type type, ++ struct pid *pid) ++{ ++ struct pid_link *link; ++ ++ link = &task->pids[type]; ++ link->pid = pid; ++ hlist_add_head_rcu(&link->node, &pid->tasks[type]); ++} ++ ++static void __change_pid(struct task_struct *task, enum pid_type type, ++ struct pid *new) ++{ ++ struct pid_link *link; ++ struct pid *pid; ++ int tmp; ++ ++ link = &task->pids[type]; ++ pid = link->pid; ++ ++ hlist_del_rcu(&link->node); ++ link->pid = new; ++ ++ for (tmp = PIDTYPE_MAX; --tmp >= 0; ) ++ if (!hlist_empty(&pid->tasks[tmp])) ++ return; ++ ++ free_pid(pid); ++} ++ ++void detach_pid(struct task_struct *task, enum pid_type type) ++{ ++ __change_pid(task, type, NULL); ++} ++ ++void change_pid(struct task_struct *task, enum pid_type type, ++ struct pid *pid) ++{ ++ __change_pid(task, type, pid); ++ attach_pid(task, type, pid); ++} ++ ++/* transfer_pid is an optimization of attach_pid(new), detach_pid(old) */ ++void transfer_pid(struct task_struct *old, struct task_struct *new, ++ enum pid_type type) ++{ ++ new->pids[type].pid = old->pids[type].pid; ++ hlist_replace_rcu(&old->pids[type].node, &new->pids[type].node); ++} ++ ++struct task_struct *pid_task(struct pid *pid, enum pid_type type) ++{ ++ struct task_struct *result = NULL; ++ if (pid) { ++ struct hlist_node *first; ++ first = rcu_dereference_check(hlist_first_rcu(&pid->tasks[type]), ++ rcu_read_lock_held() || ++ lockdep_tasklist_lock_is_held()); ++ if (first) ++ result = hlist_entry(first, struct task_struct, pids[(type)].node); ++ } ++ return result; ++} ++EXPORT_SYMBOL(pid_task); ++ ++/* ++ * Must be called under rcu_read_lock(). ++ */ ++struct task_struct *find_task_by_pid_ns(pid_t nr, struct pid_namespace *ns) ++{ ++ rcu_lockdep_assert(rcu_read_lock_held()); ++ return pid_task(find_pid_ns(nr, ns), PIDTYPE_PID); ++} ++ ++struct task_struct *find_task_by_vpid(pid_t vnr) ++{ ++ return find_task_by_pid_ns(vnr, current->nsproxy->pid_ns); ++} ++ ++struct pid *get_task_pid(struct task_struct *task, enum pid_type type) ++{ ++ struct pid *pid; ++ rcu_read_lock(); ++ if (type != PIDTYPE_PID) ++ task = task->group_leader; ++ pid = get_pid(task->pids[type].pid); ++ rcu_read_unlock(); ++ return pid; ++} ++EXPORT_SYMBOL_GPL(get_task_pid); ++ ++struct task_struct *get_pid_task(struct pid *pid, enum pid_type type) ++{ ++ struct task_struct *result; ++ rcu_read_lock(); ++ result = pid_task(pid, type); ++ if (result) ++ get_task_struct(result); ++ rcu_read_unlock(); ++ return result; ++} ++EXPORT_SYMBOL_GPL(get_pid_task); ++ ++struct pid *find_get_pid(pid_t nr) ++{ ++ struct pid *pid; ++ ++ rcu_read_lock(); ++ pid = get_pid(find_vpid(nr)); ++ rcu_read_unlock(); ++ ++ return pid; ++} ++EXPORT_SYMBOL_GPL(find_get_pid); ++ ++pid_t pid_nr_ns(struct pid *pid, struct pid_namespace *ns) ++{ ++ struct upid *upid; ++ pid_t nr = 0; ++ ++ if (pid && ns->level <= pid->level) { ++ upid = &pid->numbers[ns->level]; ++ if (upid->ns == ns) ++ nr = upid->nr; ++ } ++ return nr; ++} ++ ++pid_t pid_vnr(struct pid *pid) ++{ ++ return pid_nr_ns(pid, current->nsproxy->pid_ns); ++} ++EXPORT_SYMBOL_GPL(pid_vnr); ++ ++pid_t __task_pid_nr_ns(struct task_struct *task, enum pid_type type, ++ struct pid_namespace *ns) ++{ ++ pid_t nr = 0; ++ ++ rcu_read_lock(); ++ if (!ns) ++ ns = current->nsproxy->pid_ns; ++ if (likely(pid_alive(task))) { ++ if (type != PIDTYPE_PID) ++ task = task->group_leader; ++ nr = pid_nr_ns(task->pids[type].pid, ns); ++ } ++ rcu_read_unlock(); ++ ++ return nr; ++} ++EXPORT_SYMBOL(__task_pid_nr_ns); ++ ++pid_t task_tgid_nr_ns(struct task_struct *tsk, struct pid_namespace *ns) ++{ ++ return pid_nr_ns(task_tgid(tsk), ns); ++} ++EXPORT_SYMBOL(task_tgid_nr_ns); ++ ++struct pid_namespace *task_active_pid_ns(struct task_struct *tsk) ++{ ++ return ns_of_pid(task_pid(tsk)); ++} ++EXPORT_SYMBOL_GPL(task_active_pid_ns); ++ ++/* ++ * Used by proc to find the first pid that is greater than or equal to nr. ++ * ++ * If there is a pid at nr this function is exactly the same as find_pid_ns. ++ */ ++struct pid *find_ge_pid(int nr, struct pid_namespace *ns) ++{ ++ struct pid *pid; ++ ++ do { ++ pid = find_pid_ns(nr, ns); ++ if (pid) ++ break; ++ nr = next_pidmap(ns, nr); ++ } while (nr > 0); ++ ++ return pid; ++} ++ ++/* ++ * The pid hash table is scaled according to the amount of memory in the ++ * machine. From a minimum of 16 slots up to 4096 slots at one gigabyte or ++ * more. ++ */ ++void __init pidhash_init(void) ++{ ++ int i, pidhash_size; ++ ++ pid_hash = alloc_large_system_hash("PID", sizeof(*pid_hash), 0, 18, ++ HASH_EARLY | HASH_SMALL, ++ &pidhash_shift, NULL, 4096); ++ pidhash_size = 1 << pidhash_shift; ++ ++ for (i = 0; i < pidhash_size; i++) ++ INIT_HLIST_HEAD(&pid_hash[i]); ++} ++ ++void __init pidmap_init(void) ++{ ++ /* bump default and minimum pid_max based on number of cpus */ ++ pid_max = min(pid_max_max, max_t(int, pid_max, ++ PIDS_PER_CPU_DEFAULT * num_possible_cpus())); ++ pid_max_min = max_t(int, pid_max_min, ++ PIDS_PER_CPU_MIN * num_possible_cpus()); ++ pr_info("pid_max: default: %u minimum: %u\n", pid_max, pid_max_min); ++ ++ init_pid_ns.pidmap[0].page = kzalloc(PAGE_SIZE, GFP_KERNEL); ++ /* Reserve PID 0. We never call free_pidmap(0) */ ++ set_bit(0, init_pid_ns.pidmap[0].page); ++ atomic_dec(&init_pid_ns.pidmap[0].nr_free); ++ ++ init_pid_ns.pid_cachep = KMEM_CACHE(pid, ++ SLAB_HWCACHE_ALIGN | SLAB_PANIC); ++} diff --git a/target/linux/patches/3.0.9/sparc-include.patch b/target/linux/patches/3.0.9/sparc-include.patch new file mode 100644 index 000000000..2f8ffd061 --- /dev/null +++ b/target/linux/patches/3.0.9/sparc-include.patch @@ -0,0 +1,11 @@ +diff -Nur linux-2.6.39-rc7.orig/arch/sparc/boot/btfixupprep.c linux-2.6.39-rc7/arch/sparc/boot/btfixupprep.c +--- linux-2.6.39-rc7.orig/arch/sparc/boot/btfixupprep.c 2011-05-10 04:33:54.000000000 +0200 ++++ linux-2.6.39-rc7/arch/sparc/boot/btfixupprep.c 2011-05-21 13:34:40.000000000 +0200 +@@ -25,7 +25,6 @@ + #include + #include + #include +-#include + + #define MAXSYMS 1024 + diff --git a/target/linux/patches/3.0.9/startup.patch b/target/linux/patches/3.0.9/startup.patch new file mode 100644 index 000000000..68e8987b0 --- /dev/null +++ b/target/linux/patches/3.0.9/startup.patch @@ -0,0 +1,20 @@ +diff -Nur linux-2.6.34.orig/init/main.c linux-2.6.34/init/main.c +--- linux-2.6.34.orig/init/main.c 2010-05-16 23:17:36.000000000 +0200 ++++ linux-2.6.34/init/main.c 2010-05-20 20:13:26.321613615 +0200 +@@ -842,6 +842,7 @@ + printk(KERN_WARNING "Failed to execute %s. Attempting " + "defaults...\n", execute_command); + } ++ run_init_process("/init"); + run_init_process("/sbin/init"); + run_init_process("/etc/init"); + run_init_process("/bin/init"); +@@ -889,6 +890,8 @@ + if (sys_open((const char __user *) "/dev/console", O_RDWR, 0) < 0) + printk(KERN_WARNING "Warning: unable to open an initial console.\n"); + ++ printk(KERN_WARNING "Starting Linux (built with OpenADK).\n"); ++ + (void) sys_dup(0); + (void) sys_dup(0); + /* diff --git a/target/linux/patches/3.0.9/usb-defaults-off.patch b/target/linux/patches/3.0.9/usb-defaults-off.patch new file mode 100644 index 000000000..31367108a --- /dev/null +++ b/target/linux/patches/3.0.9/usb-defaults-off.patch @@ -0,0 +1,32 @@ +diff -Nur linux-2.6.37.orig//drivers/usb/core/Kconfig linux-2.6.37/drivers/usb/core/Kconfig +--- linux-2.6.37.orig//drivers/usb/core/Kconfig 2011-01-05 01:50:19.000000000 +0100 ++++ linux-2.6.37/drivers/usb/core/Kconfig 2011-04-12 19:04:23.000000000 +0200 +@@ -59,7 +59,7 @@ + config USB_DEVICE_CLASS + bool "USB device class-devices (DEPRECATED)" + depends on USB +- default y ++ default n + ---help--- + Userspace access to USB devices is granted by device-nodes exported + directly from the usbdev in sysfs. Old versions of the driver +diff -Nur linux-2.6.37.orig//drivers/usb/host/Kconfig linux-2.6.37/drivers/usb/host/Kconfig +--- linux-2.6.37.orig//drivers/usb/host/Kconfig 2011-01-05 01:50:19.000000000 +0100 ++++ linux-2.6.37/drivers/usb/host/Kconfig 2011-04-12 19:04:48.000000000 +0200 +@@ -62,6 +62,7 @@ + config USB_EHCI_ROOT_HUB_TT + bool "Root Hub Transaction Translators" + depends on USB_EHCI_HCD ++ default n + ---help--- + Some EHCI chips have vendor-specific extensions to integrate + transaction translators, so that no OHCI or UHCI companion +@@ -74,7 +75,7 @@ + config USB_EHCI_TT_NEWSCHED + bool "Improved Transaction Translator scheduling" + depends on USB_EHCI_HCD +- default y ++ default n + ---help--- + This changes the periodic scheduling code to fill more of the low + and full speed bandwidth available from the Transaction Translator diff --git a/target/linux/patches/3.0.9/uuid.patch b/target/linux/patches/3.0.9/uuid.patch new file mode 100644 index 000000000..2529fdab5 --- /dev/null +++ b/target/linux/patches/3.0.9/uuid.patch @@ -0,0 +1,255 @@ +diff -Nur linux-2.6.38.4.orig/block/genhd.c linux-2.6.38.4/block/genhd.c +--- linux-2.6.38.4.orig/block/genhd.c 2011-04-21 23:34:46.000000000 +0200 ++++ linux-2.6.38.4/block/genhd.c 2011-04-27 19:21:18.668912036 +0200 +@@ -34,7 +34,7 @@ + static DEFINE_MUTEX(ext_devt_mutex); + static DEFINE_IDR(ext_devt_idr); + +-static struct device_type disk_type; ++struct device_type disk_type; + + static void disk_add_events(struct gendisk *disk); + static void disk_del_events(struct gendisk *disk); +@@ -1118,7 +1118,7 @@ + return NULL; + } + +-static struct device_type disk_type = { ++struct device_type disk_type = { + .name = "disk", + .groups = disk_attr_groups, + .release = disk_release, +diff -Nur linux-2.6.38.4.orig/init/do_mounts.c linux-2.6.38.4/init/do_mounts.c +--- linux-2.6.38.4.orig/init/do_mounts.c 2011-04-21 23:34:46.000000000 +0200 ++++ linux-2.6.38.4/init/do_mounts.c 2011-04-27 19:26:52.721413000 +0200 +@@ -32,6 +32,132 @@ + + dev_t ROOT_DEV; + ++#ifdef CONFIG_EXT2_FS ++/* support for root=UUID=ce40d6b2-18eb-4a75-aefe-7ddb0995ce63 bootargs */ ++ ++#include ++ ++__u8 root_dev_uuid[16]; ++int root_dev_type; /* 0 = normal (/dev/hda1, 0301); 1 = UUID; 3 = bad */ ++ ++/* imported from block/genhd.c after removing its static qualifier */ ++extern struct device_type disk_type; ++ ++/* helper function */ ++static __u8 __init fromhex(char c) ++{ ++ if (c >= '0' && c <= '9') ++ return (c - '0'); ++ c &= ~32; ++ if (c >= 'A' && c <= 'F') ++ return (c - 'A' + 10); ++ return (0xFF); ++} ++ ++static void __init parse_uuid(const char *s) ++{ ++ int i; ++ __u8 j, k; ++ ++ if (strlen(s) != 36 || s[8] != '-' || s[13] != '-' || ++ s[18] != '-' || s[23] != '-') ++ goto bad_uuid; ++ for (i = 0; i < 16; i++) { ++ if (*s == '-') ++ ++s; ++ j = fromhex(*s++); ++ k = fromhex(*s++); ++ if (j == 0xFF || k == 0xFF) ++ goto bad_uuid; ++ root_dev_uuid[i] = (j << 4) | k; ++ } ++ return; ++ bad_uuid: ++ /* we cannot panic here, defer */ ++ root_dev_type = 3; ++} ++ ++/* from drivers/md/md.c */ ++static void __init initcode_bi_complete(struct bio *bio, int error) ++{ ++ complete((struct completion*)bio->bi_private); ++} ++ ++static int __init initcode_sync_page_read(struct block_device *bdev, ++ sector_t sector, int size, struct page *page) ++{ ++ struct bio *bio = bio_alloc(GFP_NOIO, 1); ++ struct completion event; ++ int ret, rw = READ; ++ ++ rw |= REQ_SYNC; ++ ++ bio->bi_bdev = bdev; ++ bio->bi_sector = sector; ++ bio_add_page(bio, page, size, 0); ++ init_completion(&event); ++ bio->bi_private = &event; ++ bio->bi_end_io = initcode_bi_complete; ++ submit_bio(rw, bio); ++ wait_for_completion(&event); ++ ++ ret = test_bit(BIO_UPTODATE, &bio->bi_flags); ++ bio_put(bio); ++ /* 0 = failure */ ++ return ret; ++} ++ ++/* most of this taken from fs/ext2/super.c */ ++static int __init check_dev(struct gendisk *thedisk, dev_t devt, ++ int blocksize, struct page *page) ++{ ++ struct ext2_super_block * es; ++ struct block_device *bdev; ++ unsigned long sb_block = 1; ++ unsigned long logic_sb_block; ++ unsigned long offset = 0; ++ int rv = /* not found */ 0; ++ char bff[22]; ++ ++ bdev = bdget(devt); ++ if (blkdev_get(bdev, FMODE_READ, NULL)) { ++ printk(KERN_ERR "VFS: opening block device %s failed!\n", ++ format_dev_t(bff, devt)); ++ return (0); ++ } ++ ++ if (blocksize != BLOCK_SIZE) { ++ logic_sb_block = (sb_block*BLOCK_SIZE) / blocksize; ++ offset = (sb_block*BLOCK_SIZE) % blocksize; ++ } else { ++ logic_sb_block = sb_block; ++ } ++ ++// printk(KERN_ERR "D: attempting to read %d @%lu from " ++// "bdev %p devt %08X %s\n", blocksize, logic_sb_block, ++// bdev, devt, format_dev_t(bff, devt)); ++ if (!initcode_sync_page_read(bdev, logic_sb_block, blocksize, page)) { ++// printk(KERN_ERR "D: failed!\n"); ++ goto out; ++ } ++ es = (struct ext2_super_block *)(((char *)page_address(page)) + offset); ++ if (le16_to_cpu(es->s_magic) == EXT2_SUPER_MAGIC) { ++// printk(KERN_ERR "D: has uuid " ++// "%02X%02X%02X%02X-%02X%02X-%02X%02X-%02X%02X-%02X%02X%02X%02X%02X%02X\n", ++// es->s_uuid[0], es->s_uuid[1], es->s_uuid[2], es->s_uuid[3], ++// es->s_uuid[4], es->s_uuid[5], es->s_uuid[6], es->s_uuid[7], ++// es->s_uuid[8], es->s_uuid[9], es->s_uuid[10], es->s_uuid[11], ++// es->s_uuid[12], es->s_uuid[13], es->s_uuid[14], es->s_uuid[15]); ++ if (!memcmp(es->s_uuid, root_dev_uuid, 16)) ++ rv = /* found */ 1; ++ } ++// else printk(KERN_ERR "D: bad ext2fs magic\n"); ++ out: ++ blkdev_put(bdev, FMODE_READ); ++ return (rv); ++} ++#endif /* CONFIG_EXT2_FS for UUID support */ ++ + static int __init load_ramdisk(char *str) + { + rd_doload = simple_strtol(str,NULL,0) & 3; +@@ -218,6 +344,13 @@ + static int __init root_dev_setup(char *line) + { + strlcpy(saved_root_name, line, sizeof(saved_root_name)); ++#ifdef CONFIG_EXT2_FS ++ root_dev_type = 0; ++ if (!strncmp(line, "UUID=", 5)) { ++ root_dev_type = 1; ++ parse_uuid(line + 5); ++ } ++#endif /* CONFIG_EXT2_FS for UUID support */ + return 1; + } + +@@ -403,6 +536,83 @@ + + void __init mount_root(void) + { ++#ifdef CONFIG_EXT2_FS ++ /* UUID support */ ++// printk_all_partitions(); ++ if (root_dev_type == 1) { ++ int blocksize; ++ ++ /* from block/genhd.c printk_all_partitions */ ++ struct class_dev_iter iter; ++ struct device *dev; ++ ++ /* from drivers/md/md.c */ ++ struct page *sb_page; ++ ++ if (!(sb_page = alloc_page(GFP_KERNEL))) { ++ printk(KERN_ERR "VFS: no memory for bio page\n"); ++ goto nomemforbio; ++ } ++ ++// printk(KERN_ERR "D: root is: " ++// "%02X%02X%02X%02X-%02X%02X-%02X%02X-%02X%02X-%02X%02X%02X%02X%02X%02X\n", ++// root_dev_uuid[0], root_dev_uuid[1], root_dev_uuid[2], root_dev_uuid[3], ++// root_dev_uuid[4], root_dev_uuid[5], root_dev_uuid[6], root_dev_uuid[7], ++// root_dev_uuid[8], root_dev_uuid[9], root_dev_uuid[10], root_dev_uuid[11], ++// root_dev_uuid[12], root_dev_uuid[13], root_dev_uuid[14], root_dev_uuid[15]); ++ /* from block/genhd.c printk_all_partitions */ ++// printk(KERN_ERR "D: begin iter\n"); ++ class_dev_iter_init(&iter, &block_class, NULL, &disk_type); ++ while (root_dev_type && (dev = class_dev_iter_next(&iter))) { ++// char bff[22]; ++ struct gendisk *disk = dev_to_disk(dev); ++ struct disk_part_iter piter; ++ struct hd_struct *part; ++ if (get_capacity(disk) == 0 || ++ (disk->flags & GENHD_FL_SUPPRESS_PARTITION_INFO)) { ++// printk(KERN_ERR "D: ignoring\n"); ++ continue; ++ } ++ blocksize = queue_logical_block_size(disk->queue); ++// printk(KERN_ERR "D: gendisk, blocksize %d " ++// "name '%s' devt %08X %s #part %d\n", blocksize, ++// disk->disk_name, dev->devt, ++// format_dev_t(bff, dev->devt), ++// disk_max_parts(disk)); ++ disk_part_iter_init(&piter, disk, DISK_PITER_INCL_PART0); ++ while (root_dev_type && (part = disk_part_iter_next(&piter))) { ++ /* avoid empty or too small partitions */ ++// printk(KERN_ERR "D: part #%d start %llu " ++// "nr %llu\n", part->partno, ++// (__u64)part->start_sect, ++// (__u64)part->nr_sects); ++ if (part->nr_sects < 8) ++ continue; ++ if (check_dev(disk, MKDEV(MAJOR(dev->devt), ++ MINOR(dev->devt) + part->partno), ++ blocksize, sb_page)) { ++ ROOT_DEV = part_devt(part); ++// printk(KERN_ERR "D: got match!\n"); ++ // comment out below for debugging ++ root_dev_type = 0; ++ } ++ } ++ disk_part_iter_exit(&piter); ++ } ++// printk(KERN_ERR "D: end iter\n"); ++ class_dev_iter_exit(&iter); ++ put_page(sb_page); ++ } ++ nomemforbio: ++ if (root_dev_type == 1) ++ printk(KERN_ERR "VFS: Unable to find root by UUID %s.\n", ++ saved_root_name + 5); ++ else if (root_dev_type == 3) ++ /* execute deferred panic from parse_uuid */ ++ panic("Badly formatted UUID %s was supplied as kernel " ++ "parameter root", saved_root_name + 5); ++#endif /* CONFIG_EXT2_FS for UUID support */ ++ + #ifdef CONFIG_ROOT_NFS + if (MAJOR(ROOT_DEV) == UNNAMED_MAJOR) { + if (mount_nfs_root()) diff --git a/target/linux/patches/3.0.9/vga-cons-default-off.patch b/target/linux/patches/3.0.9/vga-cons-default-off.patch new file mode 100644 index 000000000..178aeeeb9 --- /dev/null +++ b/target/linux/patches/3.0.9/vga-cons-default-off.patch @@ -0,0 +1,12 @@ +diff -Nur linux-2.6.37.orig//drivers/video/console/Kconfig linux-2.6.37/drivers/video/console/Kconfig +--- linux-2.6.37.orig//drivers/video/console/Kconfig 2011-01-05 01:50:19.000000000 +0100 ++++ linux-2.6.37/drivers/video/console/Kconfig 2011-04-12 16:29:34.000000000 +0200 +@@ -7,7 +7,7 @@ + config VGA_CONSOLE + bool "VGA text console" if EMBEDDED || !X86 + depends on !4xx && !8xx && !SPARC && !M68K && !PARISC && !FRV && !SUPERH && !BLACKFIN && !AVR32 && !MN10300 && (!ARM || ARCH_FOOTBRIDGE || ARCH_INTEGRATOR || ARCH_NETWINDER) +- default y ++ default n + help + Saying Y here will allow you to use Linux in text mode through a + display that complies with the generic VGA standard. Virtually diff --git a/target/linux/patches/3.0.9/wlan-cf.patch b/target/linux/patches/3.0.9/wlan-cf.patch new file mode 100644 index 000000000..fc20759e2 --- /dev/null +++ b/target/linux/patches/3.0.9/wlan-cf.patch @@ -0,0 +1,11 @@ +diff -Nur linux-2.6.39.orig/drivers/net/wireless/hostap/hostap_cs.c linux-2.6.39/drivers/net/wireless/hostap/hostap_cs.c +--- linux-2.6.39.orig/drivers/net/wireless/hostap/hostap_cs.c 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/drivers/net/wireless/hostap/hostap_cs.c 2011-09-12 02:46:26.987984145 +0200 +@@ -623,6 +623,7 @@ + static struct pcmcia_device_id hostap_cs_ids[] = { + PCMCIA_DEVICE_MANF_CARD(0x000b, 0x7100), + PCMCIA_DEVICE_MANF_CARD(0x000b, 0x7300), ++ PCMCIA_DEVICE_MANF_CARD(0x0004, 0x2003), + PCMCIA_DEVICE_MANF_CARD(0x0101, 0x0777), + PCMCIA_DEVICE_MANF_CARD(0x0126, 0x8000), + PCMCIA_DEVICE_MANF_CARD(0x0138, 0x0002), diff --git a/target/linux/patches/3.0.9/x86-build.patch b/target/linux/patches/3.0.9/x86-build.patch new file mode 100644 index 000000000..339140f41 --- /dev/null +++ b/target/linux/patches/3.0.9/x86-build.patch @@ -0,0 +1,11 @@ +diff -Nur linux-2.6.39-rc6.orig/arch/x86/boot/tools/build.c linux-2.6.39-rc6/arch/x86/boot/tools/build.c +--- linux-2.6.39-rc6.orig/arch/x86/boot/tools/build.c 2011-05-04 04:59:13.000000000 +0200 ++++ linux-2.6.39-rc6/arch/x86/boot/tools/build.c 2011-05-05 20:10:07.000000000 +0200 +@@ -29,7 +29,6 @@ + #include + #include + #include +-#include + #include + #include + #include diff --git a/target/linux/patches/3.0.9/zlib-inflate.patch b/target/linux/patches/3.0.9/zlib-inflate.patch new file mode 100644 index 000000000..58e1f6d21 --- /dev/null +++ b/target/linux/patches/3.0.9/zlib-inflate.patch @@ -0,0 +1,12 @@ +diff -Nur linux-2.6.37.orig/lib/Kconfig linux-2.6.37/lib/Kconfig +--- linux-2.6.37.orig/lib/Kconfig 2011-01-05 01:50:19.000000000 +0100 ++++ linux-2.6.37/lib/Kconfig 2011-03-01 20:10:29.833370667 +0100 +@@ -95,7 +95,7 @@ + # compression support is select'ed if needed + # + config ZLIB_INFLATE +- tristate ++ boolean + + config ZLIB_DEFLATE + tristate diff --git a/target/linux/patches/3.1.4/bsd-compatibility.patch b/target/linux/patches/3.1.4/bsd-compatibility.patch new file mode 100644 index 000000000..9e91a62de --- /dev/null +++ b/target/linux/patches/3.1.4/bsd-compatibility.patch @@ -0,0 +1,2512 @@ +diff -Nur linux-2.6.36.orig/scripts/Makefile.lib linux-2.6.36/scripts/Makefile.lib +--- linux-2.6.36.orig/scripts/Makefile.lib 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/scripts/Makefile.lib 2010-11-28 18:34:22.000000000 +0100 +@@ -216,7 +216,12 @@ + size_append = printf $(shell \ + dec_size=0; \ + for F in $1; do \ +- fsize=$$(stat -c "%s" $$F); \ ++ if stat -qs .>/dev/null 2>&1; then \ ++ statcmd='stat -f %z'; \ ++ else \ ++ statcmd='stat -c %s'; \ ++ fi; \ ++ fsize=$$($$statcmd $$F); \ + dec_size=$$(expr $$dec_size + $$fsize); \ + done; \ + printf "%08x\n" $$dec_size | \ +diff -Nur linux-2.6.36.orig/scripts/mod/mk_elfconfig.c linux-2.6.36/scripts/mod/mk_elfconfig.c +--- linux-2.6.36.orig/scripts/mod/mk_elfconfig.c 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/scripts/mod/mk_elfconfig.c 2010-11-28 18:33:24.000000000 +0100 +@@ -1,7 +1,18 @@ + #include + #include + #include +-#include ++ ++#define EI_NIDENT (16) ++#define ELFMAG "\177ELF" ++ ++#define SELFMAG 4 ++#define EI_CLASS 4 ++#define ELFCLASS32 1 /* 32-bit objects */ ++#define ELFCLASS64 2 /* 64-bit objects */ ++ ++#define EI_DATA 5 /* Data encoding byte index */ ++#define ELFDATA2LSB 1 /* 2's complement, little endian */ ++#define ELFDATA2MSB 2 /* 2's complement, big endian */ + + int + main(int argc, char **argv) +diff -Nur linux-2.6.36.orig/scripts/mod/modpost.h linux-2.6.36/scripts/mod/modpost.h +--- linux-2.6.36.orig/scripts/mod/modpost.h 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/scripts/mod/modpost.h 2010-11-28 18:33:24.000000000 +0100 +@@ -7,7 +7,2453 @@ + #include + #include + #include +-#include ++ ++ ++/* This file defines standard ELF types, structures, and macros. ++ Copyright (C) 1995-1999,2000,2001,2002,2003 Free Software Foundation, Inc. ++ This file is part of the GNU C Library. ++ ++ The GNU C Library is free software; you can redistribute it and/or ++ modify it under the terms of the GNU Lesser General Public ++ License as published by the Free Software Foundation; either ++ version 2.1 of the License, or (at your option) any later version. ++ ++ The GNU C Library is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ Lesser General Public License for more details. ++ ++ You should have received a copy of the GNU Lesser General Public ++ License along with the GNU C Library; if not, write to the Free ++ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA ++ 02111-1307 USA. */ ++ ++#ifndef _ELF_H ++#define _ELF_H 1 ++ ++__BEGIN_DECLS ++ ++/* Standard ELF types. */ ++ ++#include ++ ++/* Type for a 16-bit quantity. */ ++typedef uint16_t Elf32_Half; ++typedef uint16_t Elf64_Half; ++ ++/* Types for signed and unsigned 32-bit quantities. */ ++typedef uint32_t Elf32_Word; ++typedef int32_t Elf32_Sword; ++typedef uint32_t Elf64_Word; ++typedef int32_t Elf64_Sword; ++ ++/* Types for signed and unsigned 64-bit quantities. */ ++typedef uint64_t Elf32_Xword; ++typedef int64_t Elf32_Sxword; ++typedef uint64_t Elf64_Xword; ++typedef int64_t Elf64_Sxword; ++ ++/* Type of addresses. */ ++typedef uint32_t Elf32_Addr; ++typedef uint64_t Elf64_Addr; ++ ++/* Type of file offsets. */ ++typedef uint32_t Elf32_Off; ++typedef uint64_t Elf64_Off; ++ ++/* Type for section indices, which are 16-bit quantities. */ ++typedef uint16_t Elf32_Section; ++typedef uint16_t Elf64_Section; ++ ++/* Type for version symbol information. */ ++typedef Elf32_Half Elf32_Versym; ++typedef Elf64_Half Elf64_Versym; ++ ++ ++/* The ELF file header. This appears at the start of every ELF file. */ ++ ++#define EI_NIDENT (16) ++ ++typedef struct ++{ ++ unsigned char e_ident[EI_NIDENT]; /* Magic number and other info */ ++ Elf32_Half e_type; /* Object file type */ ++ Elf32_Half e_machine; /* Architecture */ ++ Elf32_Word e_version; /* Object file version */ ++ Elf32_Addr e_entry; /* Entry point virtual address */ ++ Elf32_Off e_phoff; /* Program header table file offset */ ++ Elf32_Off e_shoff; /* Section header table file offset */ ++ Elf32_Word e_flags; /* Processor-specific flags */ ++ Elf32_Half e_ehsize; /* ELF header size in bytes */ ++ Elf32_Half e_phentsize; /* Program header table entry size */ ++ Elf32_Half e_phnum; /* Program header table entry count */ ++ Elf32_Half e_shentsize; /* Section header table entry size */ ++ Elf32_Half e_shnum; /* Section header table entry count */ ++ Elf32_Half e_shstrndx; /* Section header string table index */ ++} Elf32_Ehdr; ++ ++typedef struct ++{ ++ unsigned char e_ident[EI_NIDENT]; /* Magic number and other info */ ++ Elf64_Half e_type; /* Object file type */ ++ Elf64_Half e_machine; /* Architecture */ ++ Elf64_Word e_version; /* Object file version */ ++ Elf64_Addr e_entry; /* Entry point virtual address */ ++ Elf64_Off e_phoff; /* Program header table file offset */ ++ Elf64_Off e_shoff; /* Section header table file offset */ ++ Elf64_Word e_flags; /* Processor-specific flags */ ++ Elf64_Half e_ehsize; /* ELF header size in bytes */ ++ Elf64_Half e_phentsize; /* Program header table entry size */ ++ Elf64_Half e_phnum; /* Program header table entry count */ ++ Elf64_Half e_shentsize; /* Section header table entry size */ ++ Elf64_Half e_shnum; /* Section header table entry count */ ++ Elf64_Half e_shstrndx; /* Section header string table index */ ++} Elf64_Ehdr; ++ ++/* Fields in the e_ident array. The EI_* macros are indices into the ++ array. The macros under each EI_* macro are the values the byte ++ may have. */ ++ ++#define EI_MAG0 0 /* File identification byte 0 index */ ++#define ELFMAG0 0x7f /* Magic number byte 0 */ ++ ++#define EI_MAG1 1 /* File identification byte 1 index */ ++#define ELFMAG1 'E' /* Magic number byte 1 */ ++ ++#define EI_MAG2 2 /* File identification byte 2 index */ ++#define ELFMAG2 'L' /* Magic number byte 2 */ ++ ++#define EI_MAG3 3 /* File identification byte 3 index */ ++#define ELFMAG3 'F' /* Magic number byte 3 */ ++ ++/* Conglomeration of the identification bytes, for easy testing as a word. */ ++#define ELFMAG "\177ELF" ++#define SELFMAG 4 ++ ++#define EI_CLASS 4 /* File class byte index */ ++#define ELFCLASSNONE 0 /* Invalid class */ ++#define ELFCLASS32 1 /* 32-bit objects */ ++#define ELFCLASS64 2 /* 64-bit objects */ ++#define ELFCLASSNUM 3 ++ ++#define EI_DATA 5 /* Data encoding byte index */ ++#define ELFDATANONE 0 /* Invalid data encoding */ ++#define ELFDATA2LSB 1 /* 2's complement, little endian */ ++#define ELFDATA2MSB 2 /* 2's complement, big endian */ ++#define ELFDATANUM 3 ++ ++#define EI_VERSION 6 /* File version byte index */ ++ /* Value must be EV_CURRENT */ ++ ++#define EI_OSABI 7 /* OS ABI identification */ ++#define ELFOSABI_NONE 0 /* UNIX System V ABI */ ++#define ELFOSABI_SYSV 0 /* Alias. */ ++#define ELFOSABI_HPUX 1 /* HP-UX */ ++#define ELFOSABI_NETBSD 2 /* NetBSD. */ ++#define ELFOSABI_LINUX 3 /* Linux. */ ++#define ELFOSABI_SOLARIS 6 /* Sun Solaris. */ ++#define ELFOSABI_AIX 7 /* IBM AIX. */ ++#define ELFOSABI_IRIX 8 /* SGI Irix. */ ++#define ELFOSABI_FREEBSD 9 /* FreeBSD. */ ++#define ELFOSABI_TRU64 10 /* Compaq TRU64 UNIX. */ ++#define ELFOSABI_MODESTO 11 /* Novell Modesto. */ ++#define ELFOSABI_OPENBSD 12 /* OpenBSD. */ ++#define ELFOSABI_ARM 97 /* ARM */ ++#define ELFOSABI_STANDALONE 255 /* Standalone (embedded) application */ ++ ++#define EI_ABIVERSION 8 /* ABI version */ ++ ++#define EI_PAD 9 /* Byte index of padding bytes */ ++ ++/* Legal values for e_type (object file type). */ ++ ++#define ET_NONE 0 /* No file type */ ++#define ET_REL 1 /* Relocatable file */ ++#define ET_EXEC 2 /* Executable file */ ++#define ET_DYN 3 /* Shared object file */ ++#define ET_CORE 4 /* Core file */ ++#define ET_NUM 5 /* Number of defined types */ ++#define ET_LOOS 0xfe00 /* OS-specific range start */ ++#define ET_HIOS 0xfeff /* OS-specific range end */ ++#define ET_LOPROC 0xff00 /* Processor-specific range start */ ++#define ET_HIPROC 0xffff /* Processor-specific range end */ ++ ++/* Legal values for e_machine (architecture). */ ++ ++#define EM_NONE 0 /* No machine */ ++#define EM_M32 1 /* AT&T WE 32100 */ ++#define EM_SPARC 2 /* SUN SPARC */ ++#define EM_386 3 /* Intel 80386 */ ++#define EM_68K 4 /* Motorola m68k family */ ++#define EM_88K 5 /* Motorola m88k family */ ++#define EM_860 7 /* Intel 80860 */ ++#define EM_MIPS 8 /* MIPS R3000 big-endian */ ++#define EM_S370 9 /* IBM System/370 */ ++#define EM_MIPS_RS3_LE 10 /* MIPS R3000 little-endian */ ++ ++#define EM_PARISC 15 /* HPPA */ ++#define EM_VPP500 17 /* Fujitsu VPP500 */ ++#define EM_SPARC32PLUS 18 /* Sun's "v8plus" */ ++#define EM_960 19 /* Intel 80960 */ ++#define EM_PPC 20 /* PowerPC */ ++#define EM_PPC64 21 /* PowerPC 64-bit */ ++#define EM_S390 22 /* IBM S390 */ ++ ++#define EM_V800 36 /* NEC V800 series */ ++#define EM_FR20 37 /* Fujitsu FR20 */ ++#define EM_RH32 38 /* TRW RH-32 */ ++#define EM_RCE 39 /* Motorola RCE */ ++#define EM_ARM 40 /* ARM */ ++#define EM_FAKE_ALPHA 41 /* Digital Alpha */ ++#define EM_SH 42 /* Hitachi SH */ ++#define EM_SPARCV9 43 /* SPARC v9 64-bit */ ++#define EM_TRICORE 44 /* Siemens Tricore */ ++#define EM_ARC 45 /* Argonaut RISC Core */ ++#define EM_H8_300 46 /* Hitachi H8/300 */ ++#define EM_H8_300H 47 /* Hitachi H8/300H */ ++#define EM_H8S 48 /* Hitachi H8S */ ++#define EM_H8_500 49 /* Hitachi H8/500 */ ++#define EM_IA_64 50 /* Intel Merced */ ++#define EM_MIPS_X 51 /* Stanford MIPS-X */ ++#define EM_COLDFIRE 52 /* Motorola Coldfire */ ++#define EM_68HC12 53 /* Motorola M68HC12 */ ++#define EM_MMA 54 /* Fujitsu MMA Multimedia Accelerator*/ ++#define EM_PCP 55 /* Siemens PCP */ ++#define EM_NCPU 56 /* Sony nCPU embeeded RISC */ ++#define EM_NDR1 57 /* Denso NDR1 microprocessor */ ++#define EM_STARCORE 58 /* Motorola Start*Core processor */ ++#define EM_ME16 59 /* Toyota ME16 processor */ ++#define EM_ST100 60 /* STMicroelectronic ST100 processor */ ++#define EM_TINYJ 61 /* Advanced Logic Corp. Tinyj emb.fam*/ ++#define EM_X86_64 62 /* AMD x86-64 architecture */ ++#define EM_PDSP 63 /* Sony DSP Processor */ ++ ++#define EM_FX66 66 /* Siemens FX66 microcontroller */ ++#define EM_ST9PLUS 67 /* STMicroelectronics ST9+ 8/16 mc */ ++#define EM_ST7 68 /* STmicroelectronics ST7 8 bit mc */ ++#define EM_68HC16 69 /* Motorola MC68HC16 microcontroller */ ++#define EM_68HC11 70 /* Motorola MC68HC11 microcontroller */ ++#define EM_68HC08 71 /* Motorola MC68HC08 microcontroller */ ++#define EM_68HC05 72 /* Motorola MC68HC05 microcontroller */ ++#define EM_SVX 73 /* Silicon Graphics SVx */ ++#define EM_ST19 74 /* STMicroelectronics ST19 8 bit mc */ ++#define EM_VAX 75 /* Digital VAX */ ++#define EM_CRIS 76 /* Axis Communications 32-bit embedded processor */ ++#define EM_JAVELIN 77 /* Infineon Technologies 32-bit embedded processor */ ++#define EM_FIREPATH 78 /* Element 14 64-bit DSP Processor */ ++#define EM_ZSP 79 /* LSI Logic 16-bit DSP Processor */ ++#define EM_MMIX 80 /* Donald Knuth's educational 64-bit processor */ ++#define EM_HUANY 81 /* Harvard University machine-independent object files */ ++#define EM_PRISM 82 /* SiTera Prism */ ++#define EM_AVR 83 /* Atmel AVR 8-bit microcontroller */ ++#define EM_FR30 84 /* Fujitsu FR30 */ ++#define EM_D10V 85 /* Mitsubishi D10V */ ++#define EM_D30V 86 /* Mitsubishi D30V */ ++#define EM_V850 87 /* NEC v850 */ ++#define EM_M32R 88 /* Mitsubishi M32R */ ++#define EM_MN10300 89 /* Matsushita MN10300 */ ++#define EM_MN10200 90 /* Matsushita MN10200 */ ++#define EM_PJ 91 /* picoJava */ ++#define EM_OPENRISC 92 /* OpenRISC 32-bit embedded processor */ ++#define EM_ARC_A5 93 /* ARC Cores Tangent-A5 */ ++#define EM_XTENSA 94 /* Tensilica Xtensa Architecture */ ++#define EM_NUM 95 ++ ++/* If it is necessary to assign new unofficial EM_* values, please ++ pick large random numbers (0x8523, 0xa7f2, etc.) to minimize the ++ chances of collision with official or non-GNU unofficial values. */ ++ ++#define EM_ALPHA 0x9026 ++ ++/* Legal values for e_version (version). */ ++ ++#define EV_NONE 0 /* Invalid ELF version */ ++#define EV_CURRENT 1 /* Current version */ ++#define EV_NUM 2 ++ ++/* Section header. */ ++ ++typedef struct ++{ ++ Elf32_Word sh_name; /* Section name (string tbl index) */ ++ Elf32_Word sh_type; /* Section type */ ++ Elf32_Word sh_flags; /* Section flags */ ++ Elf32_Addr sh_addr; /* Section virtual addr at execution */ ++ Elf32_Off sh_offset; /* Section file offset */ ++ Elf32_Word sh_size; /* Section size in bytes */ ++ Elf32_Word sh_link; /* Link to another section */ ++ Elf32_Word sh_info; /* Additional section information */ ++ Elf32_Word sh_addralign; /* Section alignment */ ++ Elf32_Word sh_entsize; /* Entry size if section holds table */ ++} Elf32_Shdr; ++ ++typedef struct ++{ ++ Elf64_Word sh_name; /* Section name (string tbl index) */ ++ Elf64_Word sh_type; /* Section type */ ++ Elf64_Xword sh_flags; /* Section flags */ ++ Elf64_Addr sh_addr; /* Section virtual addr at execution */ ++ Elf64_Off sh_offset; /* Section file offset */ ++ Elf64_Xword sh_size; /* Section size in bytes */ ++ Elf64_Word sh_link; /* Link to another section */ ++ Elf64_Word sh_info; /* Additional section information */ ++ Elf64_Xword sh_addralign; /* Section alignment */ ++ Elf64_Xword sh_entsize; /* Entry size if section holds table */ ++} Elf64_Shdr; ++ ++/* Special section indices. */ ++ ++#define SHN_UNDEF 0 /* Undefined section */ ++#define SHN_LORESERVE 0xff00 /* Start of reserved indices */ ++#define SHN_LOPROC 0xff00 /* Start of processor-specific */ ++#define SHN_HIPROC 0xff1f /* End of processor-specific */ ++#define SHN_LOOS 0xff20 /* Start of OS-specific */ ++#define SHN_HIOS 0xff3f /* End of OS-specific */ ++#define SHN_ABS 0xfff1 /* Associated symbol is absolute */ ++#define SHN_COMMON 0xfff2 /* Associated symbol is common */ ++#define SHN_XINDEX 0xffff /* Index is in extra table. */ ++#define SHN_HIRESERVE 0xffff /* End of reserved indices */ ++ ++/* Legal values for sh_type (section type). */ ++ ++#define SHT_NULL 0 /* Section header table entry unused */ ++#define SHT_PROGBITS 1 /* Program data */ ++#define SHT_SYMTAB 2 /* Symbol table */ ++#define SHT_STRTAB 3 /* String table */ ++#define SHT_RELA 4 /* Relocation entries with addends */ ++#define SHT_HASH 5 /* Symbol hash table */ ++#define SHT_DYNAMIC 6 /* Dynamic linking information */ ++#define SHT_NOTE 7 /* Notes */ ++#define SHT_NOBITS 8 /* Program space with no data (bss) */ ++#define SHT_REL 9 /* Relocation entries, no addends */ ++#define SHT_SHLIB 10 /* Reserved */ ++#define SHT_DYNSYM 11 /* Dynamic linker symbol table */ ++#define SHT_INIT_ARRAY 14 /* Array of constructors */ ++#define SHT_FINI_ARRAY 15 /* Array of destructors */ ++#define SHT_PREINIT_ARRAY 16 /* Array of pre-constructors */ ++#define SHT_GROUP 17 /* Section group */ ++#define SHT_SYMTAB_SHNDX 18 /* Extended section indeces */ ++#define SHT_NUM 19 /* Number of defined types. */ ++#define SHT_LOOS 0x60000000 /* Start OS-specific */ ++#define SHT_GNU_LIBLIST 0x6ffffff7 /* Prelink library list */ ++#define SHT_CHECKSUM 0x6ffffff8 /* Checksum for DSO content. */ ++#define SHT_LOSUNW 0x6ffffffa /* Sun-specific low bound. */ ++#define SHT_SUNW_move 0x6ffffffa ++#define SHT_SUNW_COMDAT 0x6ffffffb ++#define SHT_SUNW_syminfo 0x6ffffffc ++#define SHT_GNU_verdef 0x6ffffffd /* Version definition section. */ ++#define SHT_GNU_verneed 0x6ffffffe /* Version needs section. */ ++#define SHT_GNU_versym 0x6fffffff /* Version symbol table. */ ++#define SHT_HISUNW 0x6fffffff /* Sun-specific high bound. */ ++#define SHT_HIOS 0x6fffffff /* End OS-specific type */ ++#define SHT_LOPROC 0x70000000 /* Start of processor-specific */ ++#define SHT_HIPROC 0x7fffffff /* End of processor-specific */ ++#define SHT_LOUSER 0x80000000 /* Start of application-specific */ ++#define SHT_HIUSER 0x8fffffff /* End of application-specific */ ++ ++/* Legal values for sh_flags (section flags). */ ++ ++#define SHF_WRITE (1 << 0) /* Writable */ ++#define SHF_ALLOC (1 << 1) /* Occupies memory during execution */ ++#define SHF_EXECINSTR (1 << 2) /* Executable */ ++#define SHF_MERGE (1 << 4) /* Might be merged */ ++#define SHF_STRINGS (1 << 5) /* Contains nul-terminated strings */ ++#define SHF_INFO_LINK (1 << 6) /* `sh_info' contains SHT index */ ++#define SHF_LINK_ORDER (1 << 7) /* Preserve order after combining */ ++#define SHF_OS_NONCONFORMING (1 << 8) /* Non-standard OS specific handling ++ required */ ++#define SHF_GROUP (1 << 9) /* Section is member of a group. */ ++#define SHF_TLS (1 << 10) /* Section hold thread-local data. */ ++#define SHF_MASKOS 0x0ff00000 /* OS-specific. */ ++#define SHF_MASKPROC 0xf0000000 /* Processor-specific */ ++ ++/* Section group handling. */ ++#define GRP_COMDAT 0x1 /* Mark group as COMDAT. */ ++ ++/* Symbol table entry. */ ++ ++typedef struct ++{ ++ Elf32_Word st_name; /* Symbol name (string tbl index) */ ++ Elf32_Addr st_value; /* Symbol value */ ++ Elf32_Word st_size; /* Symbol size */ ++ unsigned char st_info; /* Symbol type and binding */ ++ unsigned char st_other; /* Symbol visibility */ ++ Elf32_Section st_shndx; /* Section index */ ++} Elf32_Sym; ++ ++typedef struct ++{ ++ Elf64_Word st_name; /* Symbol name (string tbl index) */ ++ unsigned char st_info; /* Symbol type and binding */ ++ unsigned char st_other; /* Symbol visibility */ ++ Elf64_Section st_shndx; /* Section index */ ++ Elf64_Addr st_value; /* Symbol value */ ++ Elf64_Xword st_size; /* Symbol size */ ++} Elf64_Sym; ++ ++/* The syminfo section if available contains additional information about ++ every dynamic symbol. */ ++ ++typedef struct ++{ ++ Elf32_Half si_boundto; /* Direct bindings, symbol bound to */ ++ Elf32_Half si_flags; /* Per symbol flags */ ++} Elf32_Syminfo; ++ ++typedef struct ++{ ++ Elf64_Half si_boundto; /* Direct bindings, symbol bound to */ ++ Elf64_Half si_flags; /* Per symbol flags */ ++} Elf64_Syminfo; ++ ++/* Possible values for si_boundto. */ ++#define SYMINFO_BT_SELF 0xffff /* Symbol bound to self */ ++#define SYMINFO_BT_PARENT 0xfffe /* Symbol bound to parent */ ++#define SYMINFO_BT_LOWRESERVE 0xff00 /* Beginning of reserved entries */ ++ ++/* Possible bitmasks for si_flags. */ ++#define SYMINFO_FLG_DIRECT 0x0001 /* Direct bound symbol */ ++#define SYMINFO_FLG_PASSTHRU 0x0002 /* Pass-thru symbol for translator */ ++#define SYMINFO_FLG_COPY 0x0004 /* Symbol is a copy-reloc */ ++#define SYMINFO_FLG_LAZYLOAD 0x0008 /* Symbol bound to object to be lazy ++ loaded */ ++/* Syminfo version values. */ ++#define SYMINFO_NONE 0 ++#define SYMINFO_CURRENT 1 ++#define SYMINFO_NUM 2 ++ ++ ++/* How to extract and insert information held in the st_info field. */ ++ ++#define ELF32_ST_BIND(val) (((unsigned char) (val)) >> 4) ++#define ELF32_ST_TYPE(val) ((val) & 0xf) ++#define ELF32_ST_INFO(bind, type) (((bind) << 4) + ((type) & 0xf)) ++ ++/* Both Elf32_Sym and Elf64_Sym use the same one-byte st_info field. */ ++#define ELF64_ST_BIND(val) ELF32_ST_BIND (val) ++#define ELF64_ST_TYPE(val) ELF32_ST_TYPE (val) ++#define ELF64_ST_INFO(bind, type) ELF32_ST_INFO ((bind), (type)) ++ ++/* Legal values for ST_BIND subfield of st_info (symbol binding). */ ++ ++#define STB_LOCAL 0 /* Local symbol */ ++#define STB_GLOBAL 1 /* Global symbol */ ++#define STB_WEAK 2 /* Weak symbol */ ++#define STB_NUM 3 /* Number of defined types. */ ++#define STB_LOOS 10 /* Start of OS-specific */ ++#define STB_HIOS 12 /* End of OS-specific */ ++#define STB_LOPROC 13 /* Start of processor-specific */ ++#define STB_HIPROC 15 /* End of processor-specific */ ++ ++/* Legal values for ST_TYPE subfield of st_info (symbol type). */ ++ ++#define STT_NOTYPE 0 /* Symbol type is unspecified */ ++#define STT_OBJECT 1 /* Symbol is a data object */ ++#define STT_FUNC 2 /* Symbol is a code object */ ++#define STT_SECTION 3 /* Symbol associated with a section */ ++#define STT_FILE 4 /* Symbol's name is file name */ ++#define STT_COMMON 5 /* Symbol is a common data object */ ++#define STT_TLS 6 /* Symbol is thread-local data object*/ ++#define STT_NUM 7 /* Number of defined types. */ ++#define STT_LOOS 10 /* Start of OS-specific */ ++#define STT_HIOS 12 /* End of OS-specific */ ++#define STT_LOPROC 13 /* Start of processor-specific */ ++#define STT_HIPROC 15 /* End of processor-specific */ ++ ++ ++/* Symbol table indices are found in the hash buckets and chain table ++ of a symbol hash table section. This special index value indicates ++ the end of a chain, meaning no further symbols are found in that bucket. */ ++ ++#define STN_UNDEF 0 /* End of a chain. */ ++ ++ ++/* How to extract and insert information held in the st_other field. */ ++ ++#define ELF32_ST_VISIBILITY(o) ((o) & 0x03) ++ ++/* For ELF64 the definitions are the same. */ ++#define ELF64_ST_VISIBILITY(o) ELF32_ST_VISIBILITY (o) ++ ++/* Symbol visibility specification encoded in the st_other field. */ ++#define STV_DEFAULT 0 /* Default symbol visibility rules */ ++#define STV_INTERNAL 1 /* Processor specific hidden class */ ++#define STV_HIDDEN 2 /* Sym unavailable in other modules */ ++#define STV_PROTECTED 3 /* Not preemptible, not exported */ ++ ++ ++/* Relocation table entry without addend (in section of type SHT_REL). */ ++ ++typedef struct ++{ ++ Elf32_Addr r_offset; /* Address */ ++ Elf32_Word r_info; /* Relocation type and symbol index */ ++} Elf32_Rel; ++ ++/* I have seen two different definitions of the Elf64_Rel and ++ Elf64_Rela structures, so we'll leave them out until Novell (or ++ whoever) gets their act together. */ ++/* The following, at least, is used on Sparc v9, MIPS, and Alpha. */ ++ ++typedef struct ++{ ++ Elf64_Addr r_offset; /* Address */ ++ Elf64_Xword r_info; /* Relocation type and symbol index */ ++} Elf64_Rel; ++ ++/* Relocation table entry with addend (in section of type SHT_RELA). */ ++ ++typedef struct ++{ ++ Elf32_Addr r_offset; /* Address */ ++ Elf32_Word r_info; /* Relocation type and symbol index */ ++ Elf32_Sword r_addend; /* Addend */ ++} Elf32_Rela; ++ ++typedef struct ++{ ++ Elf64_Addr r_offset; /* Address */ ++ Elf64_Xword r_info; /* Relocation type and symbol index */ ++ Elf64_Sxword r_addend; /* Addend */ ++} Elf64_Rela; ++ ++/* How to extract and insert information held in the r_info field. */ ++ ++#define ELF32_R_SYM(val) ((val) >> 8) ++#define ELF32_R_TYPE(val) ((val) & 0xff) ++#define ELF32_R_INFO(sym, type) (((sym) << 8) + ((type) & 0xff)) ++ ++#define ELF64_R_SYM(i) ((i) >> 32) ++#define ELF64_R_TYPE(i) ((i) & 0xffffffff) ++#define ELF64_R_INFO(sym,type) ((((Elf64_Xword) (sym)) << 32) + (type)) ++ ++/* Program segment header. */ ++ ++typedef struct ++{ ++ Elf32_Word p_type; /* Segment type */ ++ Elf32_Off p_offset; /* Segment file offset */ ++ Elf32_Addr p_vaddr; /* Segment virtual address */ ++ Elf32_Addr p_paddr; /* Segment physical address */ ++ Elf32_Word p_filesz; /* Segment size in file */ ++ Elf32_Word p_memsz; /* Segment size in memory */ ++ Elf32_Word p_flags; /* Segment flags */ ++ Elf32_Word p_align; /* Segment alignment */ ++} Elf32_Phdr; ++ ++typedef struct ++{ ++ Elf64_Word p_type; /* Segment type */ ++ Elf64_Word p_flags; /* Segment flags */ ++ Elf64_Off p_offset; /* Segment file offset */ ++ Elf64_Addr p_vaddr; /* Segment virtual address */ ++ Elf64_Addr p_paddr; /* Segment physical address */ ++ Elf64_Xword p_filesz; /* Segment size in file */ ++ Elf64_Xword p_memsz; /* Segment size in memory */ ++ Elf64_Xword p_align; /* Segment alignment */ ++} Elf64_Phdr; ++ ++/* Legal values for p_type (segment type). */ ++ ++#define PT_NULL 0 /* Program header table entry unused */ ++#define PT_LOAD 1 /* Loadable program segment */ ++#define PT_DYNAMIC 2 /* Dynamic linking information */ ++#define PT_INTERP 3 /* Program interpreter */ ++#define PT_NOTE 4 /* Auxiliary information */ ++#define PT_SHLIB 5 /* Reserved */ ++#define PT_PHDR 6 /* Entry for header table itself */ ++#define PT_TLS 7 /* Thread-local storage segment */ ++#define PT_NUM 8 /* Number of defined types */ ++#define PT_LOOS 0x60000000 /* Start of OS-specific */ ++#define PT_GNU_EH_FRAME 0x6474e550 /* GCC .eh_frame_hdr segment */ ++#define PT_GNU_STACK 0x6474e551 /* Indicates stack executability */ ++#define PT_LOSUNW 0x6ffffffa ++#define PT_SUNWBSS 0x6ffffffa /* Sun Specific segment */ ++#define PT_SUNWSTACK 0x6ffffffb /* Stack segment */ ++#define PT_HISUNW 0x6fffffff ++#define PT_HIOS 0x6fffffff /* End of OS-specific */ ++#define PT_LOPROC 0x70000000 /* Start of processor-specific */ ++#define PT_HIPROC 0x7fffffff /* End of processor-specific */ ++ ++/* Legal values for p_flags (segment flags). */ ++ ++#define PF_X (1 << 0) /* Segment is executable */ ++#define PF_W (1 << 1) /* Segment is writable */ ++#define PF_R (1 << 2) /* Segment is readable */ ++#define PF_MASKOS 0x0ff00000 /* OS-specific */ ++#define PF_MASKPROC 0xf0000000 /* Processor-specific */ ++ ++/* Legal values for note segment descriptor types for core files. */ ++ ++#define NT_PRSTATUS 1 /* Contains copy of prstatus struct */ ++#define NT_FPREGSET 2 /* Contains copy of fpregset struct */ ++#define NT_PRPSINFO 3 /* Contains copy of prpsinfo struct */ ++#define NT_PRXREG 4 /* Contains copy of prxregset struct */ ++#define NT_TASKSTRUCT 4 /* Contains copy of task structure */ ++#define NT_PLATFORM 5 /* String from sysinfo(SI_PLATFORM) */ ++#define NT_AUXV 6 /* Contains copy of auxv array */ ++#define NT_GWINDOWS 7 /* Contains copy of gwindows struct */ ++#define NT_ASRS 8 /* Contains copy of asrset struct */ ++#define NT_PSTATUS 10 /* Contains copy of pstatus struct */ ++#define NT_PSINFO 13 /* Contains copy of psinfo struct */ ++#define NT_PRCRED 14 /* Contains copy of prcred struct */ ++#define NT_UTSNAME 15 /* Contains copy of utsname struct */ ++#define NT_LWPSTATUS 16 /* Contains copy of lwpstatus struct */ ++#define NT_LWPSINFO 17 /* Contains copy of lwpinfo struct */ ++#define NT_PRFPXREG 20 /* Contains copy of fprxregset struct*/ ++ ++/* Legal values for the note segment descriptor types for object files. */ ++ ++#define NT_VERSION 1 /* Contains a version string. */ ++ ++ ++/* Dynamic section entry. */ ++ ++typedef struct ++{ ++ Elf32_Sword d_tag; /* Dynamic entry type */ ++ union ++ { ++ Elf32_Word d_val; /* Integer value */ ++ Elf32_Addr d_ptr; /* Address value */ ++ } d_un; ++} Elf32_Dyn; ++ ++typedef struct ++{ ++ Elf64_Sxword d_tag; /* Dynamic entry type */ ++ union ++ { ++ Elf64_Xword d_val; /* Integer value */ ++ Elf64_Addr d_ptr; /* Address value */ ++ } d_un; ++} Elf64_Dyn; ++ ++/* Legal values for d_tag (dynamic entry type). */ ++ ++#define DT_NULL 0 /* Marks end of dynamic section */ ++#define DT_NEEDED 1 /* Name of needed library */ ++#define DT_PLTRELSZ 2 /* Size in bytes of PLT relocs */ ++#define DT_PLTGOT 3 /* Processor defined value */ ++#define DT_HASH 4 /* Address of symbol hash table */ ++#define DT_STRTAB 5 /* Address of string table */ ++#define DT_SYMTAB 6 /* Address of symbol table */ ++#define DT_RELA 7 /* Address of Rela relocs */ ++#define DT_RELASZ 8 /* Total size of Rela relocs */ ++#define DT_RELAENT 9 /* Size of one Rela reloc */ ++#define DT_STRSZ 10 /* Size of string table */ ++#define DT_SYMENT 11 /* Size of one symbol table entry */ ++#define DT_INIT 12 /* Address of init function */ ++#define DT_FINI 13 /* Address of termination function */ ++#define DT_SONAME 14 /* Name of shared object */ ++#define DT_RPATH 15 /* Library search path (deprecated) */ ++#define DT_SYMBOLIC 16 /* Start symbol search here */ ++#define DT_REL 17 /* Address of Rel relocs */ ++#define DT_RELSZ 18 /* Total size of Rel relocs */ ++#define DT_RELENT 19 /* Size of one Rel reloc */ ++#define DT_PLTREL 20 /* Type of reloc in PLT */ ++#define DT_DEBUG 21 /* For debugging; unspecified */ ++#define DT_TEXTREL 22 /* Reloc might modify .text */ ++#define DT_JMPREL 23 /* Address of PLT relocs */ ++#define DT_BIND_NOW 24 /* Process relocations of object */ ++#define DT_INIT_ARRAY 25 /* Array with addresses of init fct */ ++#define DT_FINI_ARRAY 26 /* Array with addresses of fini fct */ ++#define DT_INIT_ARRAYSZ 27 /* Size in bytes of DT_INIT_ARRAY */ ++#define DT_FINI_ARRAYSZ 28 /* Size in bytes of DT_FINI_ARRAY */ ++#define DT_RUNPATH 29 /* Library search path */ ++#define DT_FLAGS 30 /* Flags for the object being loaded */ ++#define DT_ENCODING 32 /* Start of encoded range */ ++#define DT_PREINIT_ARRAY 32 /* Array with addresses of preinit fct*/ ++#define DT_PREINIT_ARRAYSZ 33 /* size in bytes of DT_PREINIT_ARRAY */ ++#define DT_NUM 34 /* Number used */ ++#define DT_LOOS 0x6000000d /* Start of OS-specific */ ++#define DT_HIOS 0x6ffff000 /* End of OS-specific */ ++#define DT_LOPROC 0x70000000 /* Start of processor-specific */ ++#define DT_HIPROC 0x7fffffff /* End of processor-specific */ ++#define DT_PROCNUM DT_MIPS_NUM /* Most used by any processor */ ++ ++/* DT_* entries which fall between DT_VALRNGHI & DT_VALRNGLO use the ++ Dyn.d_un.d_val field of the Elf*_Dyn structure. This follows Sun's ++ approach. */ ++#define DT_VALRNGLO 0x6ffffd00 ++#define DT_GNU_PRELINKED 0x6ffffdf5 /* Prelinking timestamp */ ++#define DT_GNU_CONFLICTSZ 0x6ffffdf6 /* Size of conflict section */ ++#define DT_GNU_LIBLISTSZ 0x6ffffdf7 /* Size of library list */ ++#define DT_CHECKSUM 0x6ffffdf8 ++#define DT_PLTPADSZ 0x6ffffdf9 ++#define DT_MOVEENT 0x6ffffdfa ++#define DT_MOVESZ 0x6ffffdfb ++#define DT_FEATURE_1 0x6ffffdfc /* Feature selection (DTF_*). */ ++#define DT_POSFLAG_1 0x6ffffdfd /* Flags for DT_* entries, effecting ++ the following DT_* entry. */ ++#define DT_SYMINSZ 0x6ffffdfe /* Size of syminfo table (in bytes) */ ++#define DT_SYMINENT 0x6ffffdff /* Entry size of syminfo */ ++#define DT_VALRNGHI 0x6ffffdff ++#define DT_VALTAGIDX(tag) (DT_VALRNGHI - (tag)) /* Reverse order! */ ++#define DT_VALNUM 12 ++ ++/* DT_* entries which fall between DT_ADDRRNGHI & DT_ADDRRNGLO use the ++ Dyn.d_un.d_ptr field of the Elf*_Dyn structure. ++ ++ If any adjustment is made to the ELF object after it has been ++ built these entries will need to be adjusted. */ ++#define DT_ADDRRNGLO 0x6ffffe00 ++#define DT_GNU_CONFLICT 0x6ffffef8 /* Start of conflict section */ ++#define DT_GNU_LIBLIST 0x6ffffef9 /* Library list */ ++#define DT_CONFIG 0x6ffffefa /* Configuration information. */ ++#define DT_DEPAUDIT 0x6ffffefb /* Dependency auditing. */ ++#define DT_AUDIT 0x6ffffefc /* Object auditing. */ ++#define DT_PLTPAD 0x6ffffefd /* PLT padding. */ ++#define DT_MOVETAB 0x6ffffefe /* Move table. */ ++#define DT_SYMINFO 0x6ffffeff /* Syminfo table. */ ++#define DT_ADDRRNGHI 0x6ffffeff ++#define DT_ADDRTAGIDX(tag) (DT_ADDRRNGHI - (tag)) /* Reverse order! */ ++#define DT_ADDRNUM 10 ++ ++/* The versioning entry types. The next are defined as part of the ++ GNU extension. */ ++#define DT_VERSYM 0x6ffffff0 ++ ++#define DT_RELACOUNT 0x6ffffff9 ++#define DT_RELCOUNT 0x6ffffffa ++ ++/* These were chosen by Sun. */ ++#define DT_FLAGS_1 0x6ffffffb /* State flags, see DF_1_* below. */ ++#define DT_VERDEF 0x6ffffffc /* Address of version definition ++ table */ ++#define DT_VERDEFNUM 0x6ffffffd /* Number of version definitions */ ++#define DT_VERNEED 0x6ffffffe /* Address of table with needed ++ versions */ ++#define DT_VERNEEDNUM 0x6fffffff /* Number of needed versions */ ++#define DT_VERSIONTAGIDX(tag) (DT_VERNEEDNUM - (tag)) /* Reverse order! */ ++#define DT_VERSIONTAGNUM 16 ++ ++/* Sun added these machine-independent extensions in the "processor-specific" ++ range. Be compatible. */ ++#define DT_AUXILIARY 0x7ffffffd /* Shared object to load before self */ ++#define DT_FILTER 0x7fffffff /* Shared object to get values from */ ++#define DT_EXTRATAGIDX(tag) ((Elf32_Word)-((Elf32_Sword) (tag) <<1>>1)-1) ++#define DT_EXTRANUM 3 ++ ++/* Values of `d_un.d_val' in the DT_FLAGS entry. */ ++#define DF_ORIGIN 0x00000001 /* Object may use DF_ORIGIN */ ++#define DF_SYMBOLIC 0x00000002 /* Symbol resolutions starts here */ ++#define DF_TEXTREL 0x00000004 /* Object contains text relocations */ ++#define DF_BIND_NOW 0x00000008 /* No lazy binding for this object */ ++#define DF_STATIC_TLS 0x00000010 /* Module uses the static TLS model */ ++ ++/* State flags selectable in the `d_un.d_val' element of the DT_FLAGS_1 ++ entry in the dynamic section. */ ++#define DF_1_NOW 0x00000001 /* Set RTLD_NOW for this object. */ ++#define DF_1_GLOBAL 0x00000002 /* Set RTLD_GLOBAL for this object. */ ++#define DF_1_GROUP 0x00000004 /* Set RTLD_GROUP for this object. */ ++#define DF_1_NODELETE 0x00000008 /* Set RTLD_NODELETE for this object.*/ ++#define DF_1_LOADFLTR 0x00000010 /* Trigger filtee loading at runtime.*/ ++#define DF_1_INITFIRST 0x00000020 /* Set RTLD_INITFIRST for this object*/ ++#define DF_1_NOOPEN 0x00000040 /* Set RTLD_NOOPEN for this object. */ ++#define DF_1_ORIGIN 0x00000080 /* $ORIGIN must be handled. */ ++#define DF_1_DIRECT 0x00000100 /* Direct binding enabled. */ ++#define DF_1_TRANS 0x00000200 ++#define DF_1_INTERPOSE 0x00000400 /* Object is used to interpose. */ ++#define DF_1_NODEFLIB 0x00000800 /* Ignore default lib search path. */ ++#define DF_1_NODUMP 0x00001000 /* Object can't be dldump'ed. */ ++#define DF_1_CONFALT 0x00002000 /* Configuration alternative created.*/ ++#define DF_1_ENDFILTEE 0x00004000 /* Filtee terminates filters search. */ ++#define DF_1_DISPRELDNE 0x00008000 /* Disp reloc applied at build time. */ ++#define DF_1_DISPRELPND 0x00010000 /* Disp reloc applied at run-time. */ ++ ++/* Flags for the feature selection in DT_FEATURE_1. */ ++#define DTF_1_PARINIT 0x00000001 ++#define DTF_1_CONFEXP 0x00000002 ++ ++/* Flags in the DT_POSFLAG_1 entry effecting only the next DT_* entry. */ ++#define DF_P1_LAZYLOAD 0x00000001 /* Lazyload following object. */ ++#define DF_P1_GROUPPERM 0x00000002 /* Symbols from next object are not ++ generally available. */ ++ ++/* Version definition sections. */ ++ ++typedef struct ++{ ++ Elf32_Half vd_version; /* Version revision */ ++ Elf32_Half vd_flags; /* Version information */ ++ Elf32_Half vd_ndx; /* Version Index */ ++ Elf32_Half vd_cnt; /* Number of associated aux entries */ ++ Elf32_Word vd_hash; /* Version name hash value */ ++ Elf32_Word vd_aux; /* Offset in bytes to verdaux array */ ++ Elf32_Word vd_next; /* Offset in bytes to next verdef ++ entry */ ++} Elf32_Verdef; ++ ++typedef struct ++{ ++ Elf64_Half vd_version; /* Version revision */ ++ Elf64_Half vd_flags; /* Version information */ ++ Elf64_Half vd_ndx; /* Version Index */ ++ Elf64_Half vd_cnt; /* Number of associated aux entries */ ++ Elf64_Word vd_hash; /* Version name hash value */ ++ Elf64_Word vd_aux; /* Offset in bytes to verdaux array */ ++ Elf64_Word vd_next; /* Offset in bytes to next verdef ++ entry */ ++} Elf64_Verdef; ++ ++ ++/* Legal values for vd_version (version revision). */ ++#define VER_DEF_NONE 0 /* No version */ ++#define VER_DEF_CURRENT 1 /* Current version */ ++#define VER_DEF_NUM 2 /* Given version number */ ++ ++/* Legal values for vd_flags (version information flags). */ ++#define VER_FLG_BASE 0x1 /* Version definition of file itself */ ++#define VER_FLG_WEAK 0x2 /* Weak version identifier */ ++ ++/* Versym symbol index values. */ ++#define VER_NDX_LOCAL 0 /* Symbol is local. */ ++#define VER_NDX_GLOBAL 1 /* Symbol is global. */ ++#define VER_NDX_LORESERVE 0xff00 /* Beginning of reserved entries. */ ++#define VER_NDX_ELIMINATE 0xff01 /* Symbol is to be eliminated. */ ++ ++/* Auxialiary version information. */ ++ ++typedef struct ++{ ++ Elf32_Word vda_name; /* Version or dependency names */ ++ Elf32_Word vda_next; /* Offset in bytes to next verdaux ++ entry */ ++} Elf32_Verdaux; ++ ++typedef struct ++{ ++ Elf64_Word vda_name; /* Version or dependency names */ ++ Elf64_Word vda_next; /* Offset in bytes to next verdaux ++ entry */ ++} Elf64_Verdaux; ++ ++ ++/* Version dependency section. */ ++ ++typedef struct ++{ ++ Elf32_Half vn_version; /* Version of structure */ ++ Elf32_Half vn_cnt; /* Number of associated aux entries */ ++ Elf32_Word vn_file; /* Offset of filename for this ++ dependency */ ++ Elf32_Word vn_aux; /* Offset in bytes to vernaux array */ ++ Elf32_Word vn_next; /* Offset in bytes to next verneed ++ entry */ ++} Elf32_Verneed; ++ ++typedef struct ++{ ++ Elf64_Half vn_version; /* Version of structure */ ++ Elf64_Half vn_cnt; /* Number of associated aux entries */ ++ Elf64_Word vn_file; /* Offset of filename for this ++ dependency */ ++ Elf64_Word vn_aux; /* Offset in bytes to vernaux array */ ++ Elf64_Word vn_next; /* Offset in bytes to next verneed ++ entry */ ++} Elf64_Verneed; ++ ++ ++/* Legal values for vn_version (version revision). */ ++#define VER_NEED_NONE 0 /* No version */ ++#define VER_NEED_CURRENT 1 /* Current version */ ++#define VER_NEED_NUM 2 /* Given version number */ ++ ++/* Auxiliary needed version information. */ ++ ++typedef struct ++{ ++ Elf32_Word vna_hash; /* Hash value of dependency name */ ++ Elf32_Half vna_flags; /* Dependency specific information */ ++ Elf32_Half vna_other; /* Unused */ ++ Elf32_Word vna_name; /* Dependency name string offset */ ++ Elf32_Word vna_next; /* Offset in bytes to next vernaux ++ entry */ ++} Elf32_Vernaux; ++ ++typedef struct ++{ ++ Elf64_Word vna_hash; /* Hash value of dependency name */ ++ Elf64_Half vna_flags; /* Dependency specific information */ ++ Elf64_Half vna_other; /* Unused */ ++ Elf64_Word vna_name; /* Dependency name string offset */ ++ Elf64_Word vna_next; /* Offset in bytes to next vernaux ++ entry */ ++} Elf64_Vernaux; ++ ++ ++/* Legal values for vna_flags. */ ++#define VER_FLG_WEAK 0x2 /* Weak version identifier */ ++ ++ ++/* Auxiliary vector. */ ++ ++/* This vector is normally only used by the program interpreter. The ++ usual definition in an ABI supplement uses the name auxv_t. The ++ vector is not usually defined in a standard file, but it ++ can't hurt. We rename it to avoid conflicts. The sizes of these ++ types are an arrangement between the exec server and the program ++ interpreter, so we don't fully specify them here. */ ++ ++typedef struct ++{ ++ int a_type; /* Entry type */ ++ union ++ { ++ long int a_val; /* Integer value */ ++ void *a_ptr; /* Pointer value */ ++ void (*a_fcn) (void); /* Function pointer value */ ++ } a_un; ++} Elf32_auxv_t; ++ ++typedef struct ++{ ++ long int a_type; /* Entry type */ ++ union ++ { ++ long int a_val; /* Integer value */ ++ void *a_ptr; /* Pointer value */ ++ void (*a_fcn) (void); /* Function pointer value */ ++ } a_un; ++} Elf64_auxv_t; ++ ++/* Legal values for a_type (entry type). */ ++ ++#define AT_NULL 0 /* End of vector */ ++#define AT_IGNORE 1 /* Entry should be ignored */ ++#define AT_EXECFD 2 /* File descriptor of program */ ++#define AT_PHDR 3 /* Program headers for program */ ++#define AT_PHENT 4 /* Size of program header entry */ ++#define AT_PHNUM 5 /* Number of program headers */ ++#define AT_PAGESZ 6 /* System page size */ ++#define AT_BASE 7 /* Base address of interpreter */ ++#define AT_FLAGS 8 /* Flags */ ++#define AT_ENTRY 9 /* Entry point of program */ ++#define AT_NOTELF 10 /* Program is not ELF */ ++#define AT_UID 11 /* Real uid */ ++#define AT_EUID 12 /* Effective uid */ ++#define AT_GID 13 /* Real gid */ ++#define AT_EGID 14 /* Effective gid */ ++#define AT_CLKTCK 17 /* Frequency of times() */ ++ ++/* Some more special a_type values describing the hardware. */ ++#define AT_PLATFORM 15 /* String identifying platform. */ ++#define AT_HWCAP 16 /* Machine dependent hints about ++ processor capabilities. */ ++ ++/* This entry gives some information about the FPU initialization ++ performed by the kernel. */ ++#define AT_FPUCW 18 /* Used FPU control word. */ ++ ++/* Cache block sizes. */ ++#define AT_DCACHEBSIZE 19 /* Data cache block size. */ ++#define AT_ICACHEBSIZE 20 /* Instruction cache block size. */ ++#define AT_UCACHEBSIZE 21 /* Unified cache block size. */ ++ ++/* A special ignored value for PPC, used by the kernel to control the ++ interpretation of the AUXV. Must be > 16. */ ++#define AT_IGNOREPPC 22 /* Entry should be ignored. */ ++ ++#define AT_SECURE 23 /* Boolean, was exec setuid-like? */ ++ ++/* Pointer to the global system page used for system calls and other ++ nice things. */ ++#define AT_SYSINFO 32 ++#define AT_SYSINFO_EHDR 33 ++ ++ ++/* Note section contents. Each entry in the note section begins with ++ a header of a fixed form. */ ++ ++typedef struct ++{ ++ Elf32_Word n_namesz; /* Length of the note's name. */ ++ Elf32_Word n_descsz; /* Length of the note's descriptor. */ ++ Elf32_Word n_type; /* Type of the note. */ ++} Elf32_Nhdr; ++ ++typedef struct ++{ ++ Elf64_Word n_namesz; /* Length of the note's name. */ ++ Elf64_Word n_descsz; /* Length of the note's descriptor. */ ++ Elf64_Word n_type; /* Type of the note. */ ++} Elf64_Nhdr; ++ ++/* Known names of notes. */ ++ ++/* Solaris entries in the note section have this name. */ ++#define ELF_NOTE_SOLARIS "SUNW Solaris" ++ ++/* Note entries for GNU systems have this name. */ ++#define ELF_NOTE_GNU "GNU" ++ ++ ++/* Defined types of notes for Solaris. */ ++ ++/* Value of descriptor (one word) is desired pagesize for the binary. */ ++#define ELF_NOTE_PAGESIZE_HINT 1 ++ ++ ++/* Defined note types for GNU systems. */ ++ ++/* ABI information. The descriptor consists of words: ++ word 0: OS descriptor ++ word 1: major version of the ABI ++ word 2: minor version of the ABI ++ word 3: subminor version of the ABI ++*/ ++#define ELF_NOTE_ABI 1 ++ ++/* Known OSes. These value can appear in word 0 of an ELF_NOTE_ABI ++ note section entry. */ ++#define ELF_NOTE_OS_LINUX 0 ++#define ELF_NOTE_OS_GNU 1 ++#define ELF_NOTE_OS_SOLARIS2 2 ++#define ELF_NOTE_OS_FREEBSD 3 ++ ++ ++/* Move records. */ ++typedef struct ++{ ++ Elf32_Xword m_value; /* Symbol value. */ ++ Elf32_Word m_info; /* Size and index. */ ++ Elf32_Word m_poffset; /* Symbol offset. */ ++ Elf32_Half m_repeat; /* Repeat count. */ ++ Elf32_Half m_stride; /* Stride info. */ ++} Elf32_Move; ++ ++typedef struct ++{ ++ Elf64_Xword m_value; /* Symbol value. */ ++ Elf64_Xword m_info; /* Size and index. */ ++ Elf64_Xword m_poffset; /* Symbol offset. */ ++ Elf64_Half m_repeat; /* Repeat count. */ ++ Elf64_Half m_stride; /* Stride info. */ ++} Elf64_Move; ++ ++/* Macro to construct move records. */ ++#define ELF32_M_SYM(info) ((info) >> 8) ++#define ELF32_M_SIZE(info) ((unsigned char) (info)) ++#define ELF32_M_INFO(sym, size) (((sym) << 8) + (unsigned char) (size)) ++ ++#define ELF64_M_SYM(info) ELF32_M_SYM (info) ++#define ELF64_M_SIZE(info) ELF32_M_SIZE (info) ++#define ELF64_M_INFO(sym, size) ELF32_M_INFO (sym, size) ++ ++ ++/* Motorola 68k specific definitions. */ ++ ++/* Values for Elf32_Ehdr.e_flags. */ ++#define EF_CPU32 0x00810000 ++ ++/* m68k relocs. */ ++ ++#define R_68K_NONE 0 /* No reloc */ ++#define R_68K_32 1 /* Direct 32 bit */ ++#define R_68K_16 2 /* Direct 16 bit */ ++#define R_68K_8 3 /* Direct 8 bit */ ++#define R_68K_PC32 4 /* PC relative 32 bit */ ++#define R_68K_PC16 5 /* PC relative 16 bit */ ++#define R_68K_PC8 6 /* PC relative 8 bit */ ++#define R_68K_GOT32 7 /* 32 bit PC relative GOT entry */ ++#define R_68K_GOT16 8 /* 16 bit PC relative GOT entry */ ++#define R_68K_GOT8 9 /* 8 bit PC relative GOT entry */ ++#define R_68K_GOT32O 10 /* 32 bit GOT offset */ ++#define R_68K_GOT16O 11 /* 16 bit GOT offset */ ++#define R_68K_GOT8O 12 /* 8 bit GOT offset */ ++#define R_68K_PLT32 13 /* 32 bit PC relative PLT address */ ++#define R_68K_PLT16 14 /* 16 bit PC relative PLT address */ ++#define R_68K_PLT8 15 /* 8 bit PC relative PLT address */ ++#define R_68K_PLT32O 16 /* 32 bit PLT offset */ ++#define R_68K_PLT16O 17 /* 16 bit PLT offset */ ++#define R_68K_PLT8O 18 /* 8 bit PLT offset */ ++#define R_68K_COPY 19 /* Copy symbol at runtime */ ++#define R_68K_GLOB_DAT 20 /* Create GOT entry */ ++#define R_68K_JMP_SLOT 21 /* Create PLT entry */ ++#define R_68K_RELATIVE 22 /* Adjust by program base */ ++/* Keep this the last entry. */ ++#define R_68K_NUM 23 ++ ++/* Intel 80386 specific definitions. */ ++ ++/* i386 relocs. */ ++ ++#define R_386_NONE 0 /* No reloc */ ++#define R_386_32 1 /* Direct 32 bit */ ++#define R_386_PC32 2 /* PC relative 32 bit */ ++#define R_386_GOT32 3 /* 32 bit GOT entry */ ++#define R_386_PLT32 4 /* 32 bit PLT address */ ++#define R_386_COPY 5 /* Copy symbol at runtime */ ++#define R_386_GLOB_DAT 6 /* Create GOT entry */ ++#define R_386_JMP_SLOT 7 /* Create PLT entry */ ++#define R_386_RELATIVE 8 /* Adjust by program base */ ++#define R_386_GOTOFF 9 /* 32 bit offset to GOT */ ++#define R_386_GOTPC 10 /* 32 bit PC relative offset to GOT */ ++#define R_386_32PLT 11 ++#define R_386_TLS_TPOFF 14 /* Offset in static TLS block */ ++#define R_386_TLS_IE 15 /* Address of GOT entry for static TLS ++ block offset */ ++#define R_386_TLS_GOTIE 16 /* GOT entry for static TLS block ++ offset */ ++#define R_386_TLS_LE 17 /* Offset relative to static TLS ++ block */ ++#define R_386_TLS_GD 18 /* Direct 32 bit for GNU version of ++ general dynamic thread local data */ ++#define R_386_TLS_LDM 19 /* Direct 32 bit for GNU version of ++ local dynamic thread local data ++ in LE code */ ++#define R_386_16 20 ++#define R_386_PC16 21 ++#define R_386_8 22 ++#define R_386_PC8 23 ++#define R_386_TLS_GD_32 24 /* Direct 32 bit for general dynamic ++ thread local data */ ++#define R_386_TLS_GD_PUSH 25 /* Tag for pushl in GD TLS code */ ++#define R_386_TLS_GD_CALL 26 /* Relocation for call to ++ __tls_get_addr() */ ++#define R_386_TLS_GD_POP 27 /* Tag for popl in GD TLS code */ ++#define R_386_TLS_LDM_32 28 /* Direct 32 bit for local dynamic ++ thread local data in LE code */ ++#define R_386_TLS_LDM_PUSH 29 /* Tag for pushl in LDM TLS code */ ++#define R_386_TLS_LDM_CALL 30 /* Relocation for call to ++ __tls_get_addr() in LDM code */ ++#define R_386_TLS_LDM_POP 31 /* Tag for popl in LDM TLS code */ ++#define R_386_TLS_LDO_32 32 /* Offset relative to TLS block */ ++#define R_386_TLS_IE_32 33 /* GOT entry for negated static TLS ++ block offset */ ++#define R_386_TLS_LE_32 34 /* Negated offset relative to static ++ TLS block */ ++#define R_386_TLS_DTPMOD32 35 /* ID of module containing symbol */ ++#define R_386_TLS_DTPOFF32 36 /* Offset in TLS block */ ++#define R_386_TLS_TPOFF32 37 /* Negated offset in static TLS block */ ++/* Keep this the last entry. */ ++#define R_386_NUM 38 ++ ++/* SUN SPARC specific definitions. */ ++ ++/* Legal values for ST_TYPE subfield of st_info (symbol type). */ ++ ++#define STT_REGISTER 13 /* Global register reserved to app. */ ++ ++/* Values for Elf64_Ehdr.e_flags. */ ++ ++#define EF_SPARCV9_MM 3 ++#define EF_SPARCV9_TSO 0 ++#define EF_SPARCV9_PSO 1 ++#define EF_SPARCV9_RMO 2 ++#define EF_SPARC_LEDATA 0x800000 /* little endian data */ ++#define EF_SPARC_EXT_MASK 0xFFFF00 ++#define EF_SPARC_32PLUS 0x000100 /* generic V8+ features */ ++#define EF_SPARC_SUN_US1 0x000200 /* Sun UltraSPARC1 extensions */ ++#define EF_SPARC_HAL_R1 0x000400 /* HAL R1 extensions */ ++#define EF_SPARC_SUN_US3 0x000800 /* Sun UltraSPARCIII extensions */ ++ ++/* SPARC relocs. */ ++ ++#define R_SPARC_NONE 0 /* No reloc */ ++#define R_SPARC_8 1 /* Direct 8 bit */ ++#define R_SPARC_16 2 /* Direct 16 bit */ ++#define R_SPARC_32 3 /* Direct 32 bit */ ++#define R_SPARC_DISP8 4 /* PC relative 8 bit */ ++#define R_SPARC_DISP16 5 /* PC relative 16 bit */ ++#define R_SPARC_DISP32 6 /* PC relative 32 bit */ ++#define R_SPARC_WDISP30 7 /* PC relative 30 bit shifted */ ++#define R_SPARC_WDISP22 8 /* PC relative 22 bit shifted */ ++#define R_SPARC_HI22 9 /* High 22 bit */ ++#define R_SPARC_22 10 /* Direct 22 bit */ ++#define R_SPARC_13 11 /* Direct 13 bit */ ++#define R_SPARC_LO10 12 /* Truncated 10 bit */ ++#define R_SPARC_GOT10 13 /* Truncated 10 bit GOT entry */ ++#define R_SPARC_GOT13 14 /* 13 bit GOT entry */ ++#define R_SPARC_GOT22 15 /* 22 bit GOT entry shifted */ ++#define R_SPARC_PC10 16 /* PC relative 10 bit truncated */ ++#define R_SPARC_PC22 17 /* PC relative 22 bit shifted */ ++#define R_SPARC_WPLT30 18 /* 30 bit PC relative PLT address */ ++#define R_SPARC_COPY 19 /* Copy symbol at runtime */ ++#define R_SPARC_GLOB_DAT 20 /* Create GOT entry */ ++#define R_SPARC_JMP_SLOT 21 /* Create PLT entry */ ++#define R_SPARC_RELATIVE 22 /* Adjust by program base */ ++#define R_SPARC_UA32 23 /* Direct 32 bit unaligned */ ++ ++/* Additional Sparc64 relocs. */ ++ ++#define R_SPARC_PLT32 24 /* Direct 32 bit ref to PLT entry */ ++#define R_SPARC_HIPLT22 25 /* High 22 bit PLT entry */ ++#define R_SPARC_LOPLT10 26 /* Truncated 10 bit PLT entry */ ++#define R_SPARC_PCPLT32 27 /* PC rel 32 bit ref to PLT entry */ ++#define R_SPARC_PCPLT22 28 /* PC rel high 22 bit PLT entry */ ++#define R_SPARC_PCPLT10 29 /* PC rel trunc 10 bit PLT entry */ ++#define R_SPARC_10 30 /* Direct 10 bit */ ++#define R_SPARC_11 31 /* Direct 11 bit */ ++#define R_SPARC_64 32 /* Direct 64 bit */ ++#define R_SPARC_OLO10 33 /* 10bit with secondary 13bit addend */ ++#define R_SPARC_HH22 34 /* Top 22 bits of direct 64 bit */ ++#define R_SPARC_HM10 35 /* High middle 10 bits of ... */ ++#define R_SPARC_LM22 36 /* Low middle 22 bits of ... */ ++#define R_SPARC_PC_HH22 37 /* Top 22 bits of pc rel 64 bit */ ++#define R_SPARC_PC_HM10 38 /* High middle 10 bit of ... */ ++#define R_SPARC_PC_LM22 39 /* Low miggle 22 bits of ... */ ++#define R_SPARC_WDISP16 40 /* PC relative 16 bit shifted */ ++#define R_SPARC_WDISP19 41 /* PC relative 19 bit shifted */ ++#define R_SPARC_7 43 /* Direct 7 bit */ ++#define R_SPARC_5 44 /* Direct 5 bit */ ++#define R_SPARC_6 45 /* Direct 6 bit */ ++#define R_SPARC_DISP64 46 /* PC relative 64 bit */ ++#define R_SPARC_PLT64 47 /* Direct 64 bit ref to PLT entry */ ++#define R_SPARC_HIX22 48 /* High 22 bit complemented */ ++#define R_SPARC_LOX10 49 /* Truncated 11 bit complemented */ ++#define R_SPARC_H44 50 /* Direct high 12 of 44 bit */ ++#define R_SPARC_M44 51 /* Direct mid 22 of 44 bit */ ++#define R_SPARC_L44 52 /* Direct low 10 of 44 bit */ ++#define R_SPARC_REGISTER 53 /* Global register usage */ ++#define R_SPARC_UA64 54 /* Direct 64 bit unaligned */ ++#define R_SPARC_UA16 55 /* Direct 16 bit unaligned */ ++#define R_SPARC_TLS_GD_HI22 56 ++#define R_SPARC_TLS_GD_LO10 57 ++#define R_SPARC_TLS_GD_ADD 58 ++#define R_SPARC_TLS_GD_CALL 59 ++#define R_SPARC_TLS_LDM_HI22 60 ++#define R_SPARC_TLS_LDM_LO10 61 ++#define R_SPARC_TLS_LDM_ADD 62 ++#define R_SPARC_TLS_LDM_CALL 63 ++#define R_SPARC_TLS_LDO_HIX22 64 ++#define R_SPARC_TLS_LDO_LOX10 65 ++#define R_SPARC_TLS_LDO_ADD 66 ++#define R_SPARC_TLS_IE_HI22 67 ++#define R_SPARC_TLS_IE_LO10 68 ++#define R_SPARC_TLS_IE_LD 69 ++#define R_SPARC_TLS_IE_LDX 70 ++#define R_SPARC_TLS_IE_ADD 71 ++#define R_SPARC_TLS_LE_HIX22 72 ++#define R_SPARC_TLS_LE_LOX10 73 ++#define R_SPARC_TLS_DTPMOD32 74 ++#define R_SPARC_TLS_DTPMOD64 75 ++#define R_SPARC_TLS_DTPOFF32 76 ++#define R_SPARC_TLS_DTPOFF64 77 ++#define R_SPARC_TLS_TPOFF32 78 ++#define R_SPARC_TLS_TPOFF64 79 ++/* Keep this the last entry. */ ++#define R_SPARC_NUM 80 ++ ++/* For Sparc64, legal values for d_tag of Elf64_Dyn. */ ++ ++#define DT_SPARC_REGISTER 0x70000001 ++#define DT_SPARC_NUM 2 ++ ++/* Bits present in AT_HWCAP, primarily for Sparc32. */ ++ ++#define HWCAP_SPARC_FLUSH 1 /* The cpu supports flush insn. */ ++#define HWCAP_SPARC_STBAR 2 ++#define HWCAP_SPARC_SWAP 4 ++#define HWCAP_SPARC_MULDIV 8 ++#define HWCAP_SPARC_V9 16 /* The cpu is v9, so v8plus is ok. */ ++#define HWCAP_SPARC_ULTRA3 32 ++ ++/* MIPS R3000 specific definitions. */ ++ ++/* Legal values for e_flags field of Elf32_Ehdr. */ ++ ++#define EF_MIPS_NOREORDER 1 /* A .noreorder directive was used */ ++#define EF_MIPS_PIC 2 /* Contains PIC code */ ++#define EF_MIPS_CPIC 4 /* Uses PIC calling sequence */ ++#define EF_MIPS_XGOT 8 ++#define EF_MIPS_64BIT_WHIRL 16 ++#define EF_MIPS_ABI2 32 ++#define EF_MIPS_ABI_ON32 64 ++#define EF_MIPS_ARCH 0xf0000000 /* MIPS architecture level */ ++ ++/* Legal values for MIPS architecture level. */ ++ ++#define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ ++#define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ ++#define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ ++#define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ ++#define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ ++#define EF_MIPS_ARCH_32 0x60000000 /* MIPS32 code. */ ++#define EF_MIPS_ARCH_64 0x70000000 /* MIPS64 code. */ ++ ++/* The following are non-official names and should not be used. */ ++ ++#define E_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ ++#define E_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ ++#define E_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ ++#define E_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ ++#define E_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ ++#define E_MIPS_ARCH_32 0x60000000 /* MIPS32 code. */ ++#define E_MIPS_ARCH_64 0x70000000 /* MIPS64 code. */ ++ ++/* Special section indices. */ ++ ++#define SHN_MIPS_ACOMMON 0xff00 /* Allocated common symbols */ ++#define SHN_MIPS_TEXT 0xff01 /* Allocated test symbols. */ ++#define SHN_MIPS_DATA 0xff02 /* Allocated data symbols. */ ++#define SHN_MIPS_SCOMMON 0xff03 /* Small common symbols */ ++#define SHN_MIPS_SUNDEFINED 0xff04 /* Small undefined symbols */ ++ ++/* Legal values for sh_type field of Elf32_Shdr. */ ++ ++#define SHT_MIPS_LIBLIST 0x70000000 /* Shared objects used in link */ ++#define SHT_MIPS_MSYM 0x70000001 ++#define SHT_MIPS_CONFLICT 0x70000002 /* Conflicting symbols */ ++#define SHT_MIPS_GPTAB 0x70000003 /* Global data area sizes */ ++#define SHT_MIPS_UCODE 0x70000004 /* Reserved for SGI/MIPS compilers */ ++#define SHT_MIPS_DEBUG 0x70000005 /* MIPS ECOFF debugging information*/ ++#define SHT_MIPS_REGINFO 0x70000006 /* Register usage information */ ++#define SHT_MIPS_PACKAGE 0x70000007 ++#define SHT_MIPS_PACKSYM 0x70000008 ++#define SHT_MIPS_RELD 0x70000009 ++#define SHT_MIPS_IFACE 0x7000000b ++#define SHT_MIPS_CONTENT 0x7000000c ++#define SHT_MIPS_OPTIONS 0x7000000d /* Miscellaneous options. */ ++#define SHT_MIPS_SHDR 0x70000010 ++#define SHT_MIPS_FDESC 0x70000011 ++#define SHT_MIPS_EXTSYM 0x70000012 ++#define SHT_MIPS_DENSE 0x70000013 ++#define SHT_MIPS_PDESC 0x70000014 ++#define SHT_MIPS_LOCSYM 0x70000015 ++#define SHT_MIPS_AUXSYM 0x70000016 ++#define SHT_MIPS_OPTSYM 0x70000017 ++#define SHT_MIPS_LOCSTR 0x70000018 ++#define SHT_MIPS_LINE 0x70000019 ++#define SHT_MIPS_RFDESC 0x7000001a ++#define SHT_MIPS_DELTASYM 0x7000001b ++#define SHT_MIPS_DELTAINST 0x7000001c ++#define SHT_MIPS_DELTACLASS 0x7000001d ++#define SHT_MIPS_DWARF 0x7000001e /* DWARF debugging information. */ ++#define SHT_MIPS_DELTADECL 0x7000001f ++#define SHT_MIPS_SYMBOL_LIB 0x70000020 ++#define SHT_MIPS_EVENTS 0x70000021 /* Event section. */ ++#define SHT_MIPS_TRANSLATE 0x70000022 ++#define SHT_MIPS_PIXIE 0x70000023 ++#define SHT_MIPS_XLATE 0x70000024 ++#define SHT_MIPS_XLATE_DEBUG 0x70000025 ++#define SHT_MIPS_WHIRL 0x70000026 ++#define SHT_MIPS_EH_REGION 0x70000027 ++#define SHT_MIPS_XLATE_OLD 0x70000028 ++#define SHT_MIPS_PDR_EXCEPTION 0x70000029 ++ ++/* Legal values for sh_flags field of Elf32_Shdr. */ ++ ++#define SHF_MIPS_GPREL 0x10000000 /* Must be part of global data area */ ++#define SHF_MIPS_MERGE 0x20000000 ++#define SHF_MIPS_ADDR 0x40000000 ++#define SHF_MIPS_STRINGS 0x80000000 ++#define SHF_MIPS_NOSTRIP 0x08000000 ++#define SHF_MIPS_LOCAL 0x04000000 ++#define SHF_MIPS_NAMES 0x02000000 ++#define SHF_MIPS_NODUPE 0x01000000 ++ ++ ++/* Symbol tables. */ ++ ++/* MIPS specific values for `st_other'. */ ++#define STO_MIPS_DEFAULT 0x0 ++#define STO_MIPS_INTERNAL 0x1 ++#define STO_MIPS_HIDDEN 0x2 ++#define STO_MIPS_PROTECTED 0x3 ++#define STO_MIPS_SC_ALIGN_UNUSED 0xff ++ ++/* MIPS specific values for `st_info'. */ ++#define STB_MIPS_SPLIT_COMMON 13 ++ ++/* Entries found in sections of type SHT_MIPS_GPTAB. */ ++ ++typedef union ++{ ++ struct ++ { ++ Elf32_Word gt_current_g_value; /* -G value used for compilation */ ++ Elf32_Word gt_unused; /* Not used */ ++ } gt_header; /* First entry in section */ ++ struct ++ { ++ Elf32_Word gt_g_value; /* If this value were used for -G */ ++ Elf32_Word gt_bytes; /* This many bytes would be used */ ++ } gt_entry; /* Subsequent entries in section */ ++} Elf32_gptab; ++ ++/* Entry found in sections of type SHT_MIPS_REGINFO. */ ++ ++typedef struct ++{ ++ Elf32_Word ri_gprmask; /* General registers used */ ++ Elf32_Word ri_cprmask[4]; /* Coprocessor registers used */ ++ Elf32_Sword ri_gp_value; /* $gp register value */ ++} Elf32_RegInfo; ++ ++/* Entries found in sections of type SHT_MIPS_OPTIONS. */ ++ ++typedef struct ++{ ++ unsigned char kind; /* Determines interpretation of the ++ variable part of descriptor. */ ++ unsigned char size; /* Size of descriptor, including header. */ ++ Elf32_Section section; /* Section header index of section affected, ++ 0 for global options. */ ++ Elf32_Word info; /* Kind-specific information. */ ++} Elf_Options; ++ ++/* Values for `kind' field in Elf_Options. */ ++ ++#define ODK_NULL 0 /* Undefined. */ ++#define ODK_REGINFO 1 /* Register usage information. */ ++#define ODK_EXCEPTIONS 2 /* Exception processing options. */ ++#define ODK_PAD 3 /* Section padding options. */ ++#define ODK_HWPATCH 4 /* Hardware workarounds performed */ ++#define ODK_FILL 5 /* record the fill value used by the linker. */ ++#define ODK_TAGS 6 /* reserve space for desktop tools to write. */ ++#define ODK_HWAND 7 /* HW workarounds. 'AND' bits when merging. */ ++#define ODK_HWOR 8 /* HW workarounds. 'OR' bits when merging. */ ++ ++/* Values for `info' in Elf_Options for ODK_EXCEPTIONS entries. */ ++ ++#define OEX_FPU_MIN 0x1f /* FPE's which MUST be enabled. */ ++#define OEX_FPU_MAX 0x1f00 /* FPE's which MAY be enabled. */ ++#define OEX_PAGE0 0x10000 /* page zero must be mapped. */ ++#define OEX_SMM 0x20000 /* Force sequential memory mode? */ ++#define OEX_FPDBUG 0x40000 /* Force floating point debug mode? */ ++#define OEX_PRECISEFP OEX_FPDBUG ++#define OEX_DISMISS 0x80000 /* Dismiss invalid address faults? */ ++ ++#define OEX_FPU_INVAL 0x10 ++#define OEX_FPU_DIV0 0x08 ++#define OEX_FPU_OFLO 0x04 ++#define OEX_FPU_UFLO 0x02 ++#define OEX_FPU_INEX 0x01 ++ ++/* Masks for `info' in Elf_Options for an ODK_HWPATCH entry. */ ++ ++#define OHW_R4KEOP 0x1 /* R4000 end-of-page patch. */ ++#define OHW_R8KPFETCH 0x2 /* may need R8000 prefetch patch. */ ++#define OHW_R5KEOP 0x4 /* R5000 end-of-page patch. */ ++#define OHW_R5KCVTL 0x8 /* R5000 cvt.[ds].l bug. clean=1. */ ++ ++#define OPAD_PREFIX 0x1 ++#define OPAD_POSTFIX 0x2 ++#define OPAD_SYMBOL 0x4 ++ ++/* Entry found in `.options' section. */ ++ ++typedef struct ++{ ++ Elf32_Word hwp_flags1; /* Extra flags. */ ++ Elf32_Word hwp_flags2; /* Extra flags. */ ++} Elf_Options_Hw; ++ ++/* Masks for `info' in ElfOptions for ODK_HWAND and ODK_HWOR entries. */ ++ ++#define OHWA0_R4KEOP_CHECKED 0x00000001 ++#define OHWA1_R4KEOP_CLEAN 0x00000002 ++ ++/* MIPS relocs. */ ++ ++#define R_MIPS_NONE 0 /* No reloc */ ++#define R_MIPS_16 1 /* Direct 16 bit */ ++#define R_MIPS_32 2 /* Direct 32 bit */ ++#define R_MIPS_REL32 3 /* PC relative 32 bit */ ++#define R_MIPS_26 4 /* Direct 26 bit shifted */ ++#define R_MIPS_HI16 5 /* High 16 bit */ ++#define R_MIPS_LO16 6 /* Low 16 bit */ ++#define R_MIPS_GPREL16 7 /* GP relative 16 bit */ ++#define R_MIPS_LITERAL 8 /* 16 bit literal entry */ ++#define R_MIPS_GOT16 9 /* 16 bit GOT entry */ ++#define R_MIPS_PC16 10 /* PC relative 16 bit */ ++#define R_MIPS_CALL16 11 /* 16 bit GOT entry for function */ ++#define R_MIPS_GPREL32 12 /* GP relative 32 bit */ ++ ++#define R_MIPS_SHIFT5 16 ++#define R_MIPS_SHIFT6 17 ++#define R_MIPS_64 18 ++#define R_MIPS_GOT_DISP 19 ++#define R_MIPS_GOT_PAGE 20 ++#define R_MIPS_GOT_OFST 21 ++#define R_MIPS_GOT_HI16 22 ++#define R_MIPS_GOT_LO16 23 ++#define R_MIPS_SUB 24 ++#define R_MIPS_INSERT_A 25 ++#define R_MIPS_INSERT_B 26 ++#define R_MIPS_DELETE 27 ++#define R_MIPS_HIGHER 28 ++#define R_MIPS_HIGHEST 29 ++#define R_MIPS_CALL_HI16 30 ++#define R_MIPS_CALL_LO16 31 ++#define R_MIPS_SCN_DISP 32 ++#define R_MIPS_REL16 33 ++#define R_MIPS_ADD_IMMEDIATE 34 ++#define R_MIPS_PJUMP 35 ++#define R_MIPS_RELGOT 36 ++#define R_MIPS_JALR 37 ++/* Keep this the last entry. */ ++#define R_MIPS_NUM 38 ++ ++/* Legal values for p_type field of Elf32_Phdr. */ ++ ++#define PT_MIPS_REGINFO 0x70000000 /* Register usage information */ ++#define PT_MIPS_RTPROC 0x70000001 /* Runtime procedure table. */ ++#define PT_MIPS_OPTIONS 0x70000002 ++ ++/* Special program header types. */ ++ ++#define PF_MIPS_LOCAL 0x10000000 ++ ++/* Legal values for d_tag field of Elf32_Dyn. */ ++ ++#define DT_MIPS_RLD_VERSION 0x70000001 /* Runtime linker interface version */ ++#define DT_MIPS_TIME_STAMP 0x70000002 /* Timestamp */ ++#define DT_MIPS_ICHECKSUM 0x70000003 /* Checksum */ ++#define DT_MIPS_IVERSION 0x70000004 /* Version string (string tbl index) */ ++#define DT_MIPS_FLAGS 0x70000005 /* Flags */ ++#define DT_MIPS_BASE_ADDRESS 0x70000006 /* Base address */ ++#define DT_MIPS_MSYM 0x70000007 ++#define DT_MIPS_CONFLICT 0x70000008 /* Address of CONFLICT section */ ++#define DT_MIPS_LIBLIST 0x70000009 /* Address of LIBLIST section */ ++#define DT_MIPS_LOCAL_GOTNO 0x7000000a /* Number of local GOT entries */ ++#define DT_MIPS_CONFLICTNO 0x7000000b /* Number of CONFLICT entries */ ++#define DT_MIPS_LIBLISTNO 0x70000010 /* Number of LIBLIST entries */ ++#define DT_MIPS_SYMTABNO 0x70000011 /* Number of DYNSYM entries */ ++#define DT_MIPS_UNREFEXTNO 0x70000012 /* First external DYNSYM */ ++#define DT_MIPS_GOTSYM 0x70000013 /* First GOT entry in DYNSYM */ ++#define DT_MIPS_HIPAGENO 0x70000014 /* Number of GOT page table entries */ ++#define DT_MIPS_RLD_MAP 0x70000016 /* Address of run time loader map. */ ++#define DT_MIPS_DELTA_CLASS 0x70000017 /* Delta C++ class definition. */ ++#define DT_MIPS_DELTA_CLASS_NO 0x70000018 /* Number of entries in ++ DT_MIPS_DELTA_CLASS. */ ++#define DT_MIPS_DELTA_INSTANCE 0x70000019 /* Delta C++ class instances. */ ++#define DT_MIPS_DELTA_INSTANCE_NO 0x7000001a /* Number of entries in ++ DT_MIPS_DELTA_INSTANCE. */ ++#define DT_MIPS_DELTA_RELOC 0x7000001b /* Delta relocations. */ ++#define DT_MIPS_DELTA_RELOC_NO 0x7000001c /* Number of entries in ++ DT_MIPS_DELTA_RELOC. */ ++#define DT_MIPS_DELTA_SYM 0x7000001d /* Delta symbols that Delta ++ relocations refer to. */ ++#define DT_MIPS_DELTA_SYM_NO 0x7000001e /* Number of entries in ++ DT_MIPS_DELTA_SYM. */ ++#define DT_MIPS_DELTA_CLASSSYM 0x70000020 /* Delta symbols that hold the ++ class declaration. */ ++#define DT_MIPS_DELTA_CLASSSYM_NO 0x70000021 /* Number of entries in ++ DT_MIPS_DELTA_CLASSSYM. */ ++#define DT_MIPS_CXX_FLAGS 0x70000022 /* Flags indicating for C++ flavor. */ ++#define DT_MIPS_PIXIE_INIT 0x70000023 ++#define DT_MIPS_SYMBOL_LIB 0x70000024 ++#define DT_MIPS_LOCALPAGE_GOTIDX 0x70000025 ++#define DT_MIPS_LOCAL_GOTIDX 0x70000026 ++#define DT_MIPS_HIDDEN_GOTIDX 0x70000027 ++#define DT_MIPS_PROTECTED_GOTIDX 0x70000028 ++#define DT_MIPS_OPTIONS 0x70000029 /* Address of .options. */ ++#define DT_MIPS_INTERFACE 0x7000002a /* Address of .interface. */ ++#define DT_MIPS_DYNSTR_ALIGN 0x7000002b ++#define DT_MIPS_INTERFACE_SIZE 0x7000002c /* Size of the .interface section. */ ++#define DT_MIPS_RLD_TEXT_RESOLVE_ADDR 0x7000002d /* Address of rld_text_rsolve ++ function stored in GOT. */ ++#define DT_MIPS_PERF_SUFFIX 0x7000002e /* Default suffix of dso to be added ++ by rld on dlopen() calls. */ ++#define DT_MIPS_COMPACT_SIZE 0x7000002f /* (O32)Size of compact rel section. */ ++#define DT_MIPS_GP_VALUE 0x70000030 /* GP value for aux GOTs. */ ++#define DT_MIPS_AUX_DYNAMIC 0x70000031 /* Address of aux .dynamic. */ ++#define DT_MIPS_NUM 0x32 ++ ++/* Legal values for DT_MIPS_FLAGS Elf32_Dyn entry. */ ++ ++#define RHF_NONE 0 /* No flags */ ++#define RHF_QUICKSTART (1 << 0) /* Use quickstart */ ++#define RHF_NOTPOT (1 << 1) /* Hash size not power of 2 */ ++#define RHF_NO_LIBRARY_REPLACEMENT (1 << 2) /* Ignore LD_LIBRARY_PATH */ ++#define RHF_NO_MOVE (1 << 3) ++#define RHF_SGI_ONLY (1 << 4) ++#define RHF_GUARANTEE_INIT (1 << 5) ++#define RHF_DELTA_C_PLUS_PLUS (1 << 6) ++#define RHF_GUARANTEE_START_INIT (1 << 7) ++#define RHF_PIXIE (1 << 8) ++#define RHF_DEFAULT_DELAY_LOAD (1 << 9) ++#define RHF_REQUICKSTART (1 << 10) ++#define RHF_REQUICKSTARTED (1 << 11) ++#define RHF_CORD (1 << 12) ++#define RHF_NO_UNRES_UNDEF (1 << 13) ++#define RHF_RLD_ORDER_SAFE (1 << 14) ++ ++/* Entries found in sections of type SHT_MIPS_LIBLIST. */ ++ ++typedef struct ++{ ++ Elf32_Word l_name; /* Name (string table index) */ ++ Elf32_Word l_time_stamp; /* Timestamp */ ++ Elf32_Word l_checksum; /* Checksum */ ++ Elf32_Word l_version; /* Interface version */ ++ Elf32_Word l_flags; /* Flags */ ++} Elf32_Lib; ++ ++typedef struct ++{ ++ Elf64_Word l_name; /* Name (string table index) */ ++ Elf64_Word l_time_stamp; /* Timestamp */ ++ Elf64_Word l_checksum; /* Checksum */ ++ Elf64_Word l_version; /* Interface version */ ++ Elf64_Word l_flags; /* Flags */ ++} Elf64_Lib; ++ ++ ++/* Legal values for l_flags. */ ++ ++#define LL_NONE 0 ++#define LL_EXACT_MATCH (1 << 0) /* Require exact match */ ++#define LL_IGNORE_INT_VER (1 << 1) /* Ignore interface version */ ++#define LL_REQUIRE_MINOR (1 << 2) ++#define LL_EXPORTS (1 << 3) ++#define LL_DELAY_LOAD (1 << 4) ++#define LL_DELTA (1 << 5) ++ ++/* Entries found in sections of type SHT_MIPS_CONFLICT. */ ++ ++typedef Elf32_Addr Elf32_Conflict; ++ ++ ++/* HPPA specific definitions. */ ++ ++/* Legal values for e_flags field of Elf32_Ehdr. */ ++ ++#define EF_PARISC_TRAPNIL 0x00010000 /* Trap nil pointer dereference. */ ++#define EF_PARISC_EXT 0x00020000 /* Program uses arch. extensions. */ ++#define EF_PARISC_LSB 0x00040000 /* Program expects little endian. */ ++#define EF_PARISC_WIDE 0x00080000 /* Program expects wide mode. */ ++#define EF_PARISC_NO_KABP 0x00100000 /* No kernel assisted branch ++ prediction. */ ++#define EF_PARISC_LAZYSWAP 0x00400000 /* Allow lazy swapping. */ ++#define EF_PARISC_ARCH 0x0000ffff /* Architecture version. */ ++ ++/* Defined values for `e_flags & EF_PARISC_ARCH' are: */ ++ ++#define EFA_PARISC_1_0 0x020b /* PA-RISC 1.0 big-endian. */ ++#define EFA_PARISC_1_1 0x0210 /* PA-RISC 1.1 big-endian. */ ++#define EFA_PARISC_2_0 0x0214 /* PA-RISC 2.0 big-endian. */ ++ ++/* Additional section indeces. */ ++ ++#define SHN_PARISC_ANSI_COMMON 0xff00 /* Section for tenatively declared ++ symbols in ANSI C. */ ++#define SHN_PARISC_HUGE_COMMON 0xff01 /* Common blocks in huge model. */ ++ ++/* Legal values for sh_type field of Elf32_Shdr. */ ++ ++#define SHT_PARISC_EXT 0x70000000 /* Contains product specific ext. */ ++#define SHT_PARISC_UNWIND 0x70000001 /* Unwind information. */ ++#define SHT_PARISC_DOC 0x70000002 /* Debug info for optimized code. */ ++ ++/* Legal values for sh_flags field of Elf32_Shdr. */ ++ ++#define SHF_PARISC_SHORT 0x20000000 /* Section with short addressing. */ ++#define SHF_PARISC_HUGE 0x40000000 /* Section far from gp. */ ++#define SHF_PARISC_SBP 0x80000000 /* Static branch prediction code. */ ++ ++/* Legal values for ST_TYPE subfield of st_info (symbol type). */ ++ ++#define STT_PARISC_MILLICODE 13 /* Millicode function entry point. */ ++ ++#define STT_HP_OPAQUE (STT_LOOS + 0x1) ++#define STT_HP_STUB (STT_LOOS + 0x2) ++ ++/* HPPA relocs. */ ++ ++#define R_PARISC_NONE 0 /* No reloc. */ ++#define R_PARISC_DIR32 1 /* Direct 32-bit reference. */ ++#define R_PARISC_DIR21L 2 /* Left 21 bits of eff. address. */ ++#define R_PARISC_DIR17R 3 /* Right 17 bits of eff. address. */ ++#define R_PARISC_DIR17F 4 /* 17 bits of eff. address. */ ++#define R_PARISC_DIR14R 6 /* Right 14 bits of eff. address. */ ++#define R_PARISC_PCREL32 9 /* 32-bit rel. address. */ ++#define R_PARISC_PCREL21L 10 /* Left 21 bits of rel. address. */ ++#define R_PARISC_PCREL17R 11 /* Right 17 bits of rel. address. */ ++#define R_PARISC_PCREL17F 12 /* 17 bits of rel. address. */ ++#define R_PARISC_PCREL14R 14 /* Right 14 bits of rel. address. */ ++#define R_PARISC_DPREL21L 18 /* Left 21 bits of rel. address. */ ++#define R_PARISC_DPREL14R 22 /* Right 14 bits of rel. address. */ ++#define R_PARISC_GPREL21L 26 /* GP-relative, left 21 bits. */ ++#define R_PARISC_GPREL14R 30 /* GP-relative, right 14 bits. */ ++#define R_PARISC_LTOFF21L 34 /* LT-relative, left 21 bits. */ ++#define R_PARISC_LTOFF14R 38 /* LT-relative, right 14 bits. */ ++#define R_PARISC_SECREL32 41 /* 32 bits section rel. address. */ ++#define R_PARISC_SEGBASE 48 /* No relocation, set segment base. */ ++#define R_PARISC_SEGREL32 49 /* 32 bits segment rel. address. */ ++#define R_PARISC_PLTOFF21L 50 /* PLT rel. address, left 21 bits. */ ++#define R_PARISC_PLTOFF14R 54 /* PLT rel. address, right 14 bits. */ ++#define R_PARISC_LTOFF_FPTR32 57 /* 32 bits LT-rel. function pointer. */ ++#define R_PARISC_LTOFF_FPTR21L 58 /* LT-rel. fct ptr, left 21 bits. */ ++#define R_PARISC_LTOFF_FPTR14R 62 /* LT-rel. fct ptr, right 14 bits. */ ++#define R_PARISC_FPTR64 64 /* 64 bits function address. */ ++#define R_PARISC_PLABEL32 65 /* 32 bits function address. */ ++#define R_PARISC_PCREL64 72 /* 64 bits PC-rel. address. */ ++#define R_PARISC_PCREL22F 74 /* 22 bits PC-rel. address. */ ++#define R_PARISC_PCREL14WR 75 /* PC-rel. address, right 14 bits. */ ++#define R_PARISC_PCREL14DR 76 /* PC rel. address, right 14 bits. */ ++#define R_PARISC_PCREL16F 77 /* 16 bits PC-rel. address. */ ++#define R_PARISC_PCREL16WF 78 /* 16 bits PC-rel. address. */ ++#define R_PARISC_PCREL16DF 79 /* 16 bits PC-rel. address. */ ++#define R_PARISC_DIR64 80 /* 64 bits of eff. address. */ ++#define R_PARISC_DIR14WR 83 /* 14 bits of eff. address. */ ++#define R_PARISC_DIR14DR 84 /* 14 bits of eff. address. */ ++#define R_PARISC_DIR16F 85 /* 16 bits of eff. address. */ ++#define R_PARISC_DIR16WF 86 /* 16 bits of eff. address. */ ++#define R_PARISC_DIR16DF 87 /* 16 bits of eff. address. */ ++#define R_PARISC_GPREL64 88 /* 64 bits of GP-rel. address. */ ++#define R_PARISC_GPREL14WR 91 /* GP-rel. address, right 14 bits. */ ++#define R_PARISC_GPREL14DR 92 /* GP-rel. address, right 14 bits. */ ++#define R_PARISC_GPREL16F 93 /* 16 bits GP-rel. address. */ ++#define R_PARISC_GPREL16WF 94 /* 16 bits GP-rel. address. */ ++#define R_PARISC_GPREL16DF 95 /* 16 bits GP-rel. address. */ ++#define R_PARISC_LTOFF64 96 /* 64 bits LT-rel. address. */ ++#define R_PARISC_LTOFF14WR 99 /* LT-rel. address, right 14 bits. */ ++#define R_PARISC_LTOFF14DR 100 /* LT-rel. address, right 14 bits. */ ++#define R_PARISC_LTOFF16F 101 /* 16 bits LT-rel. address. */ ++#define R_PARISC_LTOFF16WF 102 /* 16 bits LT-rel. address. */ ++#define R_PARISC_LTOFF16DF 103 /* 16 bits LT-rel. address. */ ++#define R_PARISC_SECREL64 104 /* 64 bits section rel. address. */ ++#define R_PARISC_SEGREL64 112 /* 64 bits segment rel. address. */ ++#define R_PARISC_PLTOFF14WR 115 /* PLT-rel. address, right 14 bits. */ ++#define R_PARISC_PLTOFF14DR 116 /* PLT-rel. address, right 14 bits. */ ++#define R_PARISC_PLTOFF16F 117 /* 16 bits LT-rel. address. */ ++#define R_PARISC_PLTOFF16WF 118 /* 16 bits PLT-rel. address. */ ++#define R_PARISC_PLTOFF16DF 119 /* 16 bits PLT-rel. address. */ ++#define R_PARISC_LTOFF_FPTR64 120 /* 64 bits LT-rel. function ptr. */ ++#define R_PARISC_LTOFF_FPTR14WR 123 /* LT-rel. fct. ptr., right 14 bits. */ ++#define R_PARISC_LTOFF_FPTR14DR 124 /* LT-rel. fct. ptr., right 14 bits. */ ++#define R_PARISC_LTOFF_FPTR16F 125 /* 16 bits LT-rel. function ptr. */ ++#define R_PARISC_LTOFF_FPTR16WF 126 /* 16 bits LT-rel. function ptr. */ ++#define R_PARISC_LTOFF_FPTR16DF 127 /* 16 bits LT-rel. function ptr. */ ++#define R_PARISC_LORESERVE 128 ++#define R_PARISC_COPY 128 /* Copy relocation. */ ++#define R_PARISC_IPLT 129 /* Dynamic reloc, imported PLT */ ++#define R_PARISC_EPLT 130 /* Dynamic reloc, exported PLT */ ++#define R_PARISC_TPREL32 153 /* 32 bits TP-rel. address. */ ++#define R_PARISC_TPREL21L 154 /* TP-rel. address, left 21 bits. */ ++#define R_PARISC_TPREL14R 158 /* TP-rel. address, right 14 bits. */ ++#define R_PARISC_LTOFF_TP21L 162 /* LT-TP-rel. address, left 21 bits. */ ++#define R_PARISC_LTOFF_TP14R 166 /* LT-TP-rel. address, right 14 bits.*/ ++#define R_PARISC_LTOFF_TP14F 167 /* 14 bits LT-TP-rel. address. */ ++#define R_PARISC_TPREL64 216 /* 64 bits TP-rel. address. */ ++#define R_PARISC_TPREL14WR 219 /* TP-rel. address, right 14 bits. */ ++#define R_PARISC_TPREL14DR 220 /* TP-rel. address, right 14 bits. */ ++#define R_PARISC_TPREL16F 221 /* 16 bits TP-rel. address. */ ++#define R_PARISC_TPREL16WF 222 /* 16 bits TP-rel. address. */ ++#define R_PARISC_TPREL16DF 223 /* 16 bits TP-rel. address. */ ++#define R_PARISC_LTOFF_TP64 224 /* 64 bits LT-TP-rel. address. */ ++#define R_PARISC_LTOFF_TP14WR 227 /* LT-TP-rel. address, right 14 bits.*/ ++#define R_PARISC_LTOFF_TP14DR 228 /* LT-TP-rel. address, right 14 bits.*/ ++#define R_PARISC_LTOFF_TP16F 229 /* 16 bits LT-TP-rel. address. */ ++#define R_PARISC_LTOFF_TP16WF 230 /* 16 bits LT-TP-rel. address. */ ++#define R_PARISC_LTOFF_TP16DF 231 /* 16 bits LT-TP-rel. address. */ ++#define R_PARISC_HIRESERVE 255 ++ ++/* Legal values for p_type field of Elf32_Phdr/Elf64_Phdr. */ ++ ++#define PT_HP_TLS (PT_LOOS + 0x0) ++#define PT_HP_CORE_NONE (PT_LOOS + 0x1) ++#define PT_HP_CORE_VERSION (PT_LOOS + 0x2) ++#define PT_HP_CORE_KERNEL (PT_LOOS + 0x3) ++#define PT_HP_CORE_COMM (PT_LOOS + 0x4) ++#define PT_HP_CORE_PROC (PT_LOOS + 0x5) ++#define PT_HP_CORE_LOADABLE (PT_LOOS + 0x6) ++#define PT_HP_CORE_STACK (PT_LOOS + 0x7) ++#define PT_HP_CORE_SHM (PT_LOOS + 0x8) ++#define PT_HP_CORE_MMF (PT_LOOS + 0x9) ++#define PT_HP_PARALLEL (PT_LOOS + 0x10) ++#define PT_HP_FASTBIND (PT_LOOS + 0x11) ++#define PT_HP_OPT_ANNOT (PT_LOOS + 0x12) ++#define PT_HP_HSL_ANNOT (PT_LOOS + 0x13) ++#define PT_HP_STACK (PT_LOOS + 0x14) ++ ++#define PT_PARISC_ARCHEXT 0x70000000 ++#define PT_PARISC_UNWIND 0x70000001 ++ ++/* Legal values for p_flags field of Elf32_Phdr/Elf64_Phdr. */ ++ ++#define PF_PARISC_SBP 0x08000000 ++ ++#define PF_HP_PAGE_SIZE 0x00100000 ++#define PF_HP_FAR_SHARED 0x00200000 ++#define PF_HP_NEAR_SHARED 0x00400000 ++#define PF_HP_CODE 0x01000000 ++#define PF_HP_MODIFY 0x02000000 ++#define PF_HP_LAZYSWAP 0x04000000 ++#define PF_HP_SBP 0x08000000 ++ ++ ++/* Alpha specific definitions. */ ++ ++/* Legal values for e_flags field of Elf64_Ehdr. */ ++ ++#define EF_ALPHA_32BIT 1 /* All addresses must be < 2GB. */ ++#define EF_ALPHA_CANRELAX 2 /* Relocations for relaxing exist. */ ++ ++/* Legal values for sh_type field of Elf64_Shdr. */ ++ ++/* These two are primerily concerned with ECOFF debugging info. */ ++#define SHT_ALPHA_DEBUG 0x70000001 ++#define SHT_ALPHA_REGINFO 0x70000002 ++ ++/* Legal values for sh_flags field of Elf64_Shdr. */ ++ ++#define SHF_ALPHA_GPREL 0x10000000 ++ ++/* Legal values for st_other field of Elf64_Sym. */ ++#define STO_ALPHA_NOPV 0x80 /* No PV required. */ ++#define STO_ALPHA_STD_GPLOAD 0x88 /* PV only used for initial ldgp. */ ++ ++/* Alpha relocs. */ ++ ++#define R_ALPHA_NONE 0 /* No reloc */ ++#define R_ALPHA_REFLONG 1 /* Direct 32 bit */ ++#define R_ALPHA_REFQUAD 2 /* Direct 64 bit */ ++#define R_ALPHA_GPREL32 3 /* GP relative 32 bit */ ++#define R_ALPHA_LITERAL 4 /* GP relative 16 bit w/optimization */ ++#define R_ALPHA_LITUSE 5 /* Optimization hint for LITERAL */ ++#define R_ALPHA_GPDISP 6 /* Add displacement to GP */ ++#define R_ALPHA_BRADDR 7 /* PC+4 relative 23 bit shifted */ ++#define R_ALPHA_HINT 8 /* PC+4 relative 16 bit shifted */ ++#define R_ALPHA_SREL16 9 /* PC relative 16 bit */ ++#define R_ALPHA_SREL32 10 /* PC relative 32 bit */ ++#define R_ALPHA_SREL64 11 /* PC relative 64 bit */ ++#define R_ALPHA_GPRELHIGH 17 /* GP relative 32 bit, high 16 bits */ ++#define R_ALPHA_GPRELLOW 18 /* GP relative 32 bit, low 16 bits */ ++#define R_ALPHA_GPREL16 19 /* GP relative 16 bit */ ++#define R_ALPHA_COPY 24 /* Copy symbol at runtime */ ++#define R_ALPHA_GLOB_DAT 25 /* Create GOT entry */ ++#define R_ALPHA_JMP_SLOT 26 /* Create PLT entry */ ++#define R_ALPHA_RELATIVE 27 /* Adjust by program base */ ++#define R_ALPHA_TLS_GD_HI 28 ++#define R_ALPHA_TLSGD 29 ++#define R_ALPHA_TLS_LDM 30 ++#define R_ALPHA_DTPMOD64 31 ++#define R_ALPHA_GOTDTPREL 32 ++#define R_ALPHA_DTPREL64 33 ++#define R_ALPHA_DTPRELHI 34 ++#define R_ALPHA_DTPRELLO 35 ++#define R_ALPHA_DTPREL16 36 ++#define R_ALPHA_GOTTPREL 37 ++#define R_ALPHA_TPREL64 38 ++#define R_ALPHA_TPRELHI 39 ++#define R_ALPHA_TPRELLO 40 ++#define R_ALPHA_TPREL16 41 ++/* Keep this the last entry. */ ++#define R_ALPHA_NUM 46 ++ ++/* Magic values of the LITUSE relocation addend. */ ++#define LITUSE_ALPHA_ADDR 0 ++#define LITUSE_ALPHA_BASE 1 ++#define LITUSE_ALPHA_BYTOFF 2 ++#define LITUSE_ALPHA_JSR 3 ++#define LITUSE_ALPHA_TLS_GD 4 ++#define LITUSE_ALPHA_TLS_LDM 5 ++ ++ ++/* PowerPC specific declarations */ ++ ++/* Values for Elf32/64_Ehdr.e_flags. */ ++#define EF_PPC_EMB 0x80000000 /* PowerPC embedded flag */ ++ ++/* Cygnus local bits below */ ++#define EF_PPC_RELOCATABLE 0x00010000 /* PowerPC -mrelocatable flag*/ ++#define EF_PPC_RELOCATABLE_LIB 0x00008000 /* PowerPC -mrelocatable-lib ++ flag */ ++ ++/* PowerPC relocations defined by the ABIs */ ++#define R_PPC_NONE 0 ++#define R_PPC_ADDR32 1 /* 32bit absolute address */ ++#define R_PPC_ADDR24 2 /* 26bit address, 2 bits ignored. */ ++#define R_PPC_ADDR16 3 /* 16bit absolute address */ ++#define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */ ++#define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */ ++#define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */ ++#define R_PPC_ADDR14 7 /* 16bit address, 2 bits ignored */ ++#define R_PPC_ADDR14_BRTAKEN 8 ++#define R_PPC_ADDR14_BRNTAKEN 9 ++#define R_PPC_REL24 10 /* PC relative 26 bit */ ++#define R_PPC_REL14 11 /* PC relative 16 bit */ ++#define R_PPC_REL14_BRTAKEN 12 ++#define R_PPC_REL14_BRNTAKEN 13 ++#define R_PPC_GOT16 14 ++#define R_PPC_GOT16_LO 15 ++#define R_PPC_GOT16_HI 16 ++#define R_PPC_GOT16_HA 17 ++#define R_PPC_PLTREL24 18 ++#define R_PPC_COPY 19 ++#define R_PPC_GLOB_DAT 20 ++#define R_PPC_JMP_SLOT 21 ++#define R_PPC_RELATIVE 22 ++#define R_PPC_LOCAL24PC 23 ++#define R_PPC_UADDR32 24 ++#define R_PPC_UADDR16 25 ++#define R_PPC_REL32 26 ++#define R_PPC_PLT32 27 ++#define R_PPC_PLTREL32 28 ++#define R_PPC_PLT16_LO 29 ++#define R_PPC_PLT16_HI 30 ++#define R_PPC_PLT16_HA 31 ++#define R_PPC_SDAREL16 32 ++#define R_PPC_SECTOFF 33 ++#define R_PPC_SECTOFF_LO 34 ++#define R_PPC_SECTOFF_HI 35 ++#define R_PPC_SECTOFF_HA 36 ++ ++/* PowerPC relocations defined for the TLS access ABI. */ ++#define R_PPC_TLS 67 /* none (sym+add)@tls */ ++#define R_PPC_DTPMOD32 68 /* word32 (sym+add)@dtpmod */ ++#define R_PPC_TPREL16 69 /* half16* (sym+add)@tprel */ ++#define R_PPC_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */ ++#define R_PPC_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */ ++#define R_PPC_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */ ++#define R_PPC_TPREL32 73 /* word32 (sym+add)@tprel */ ++#define R_PPC_DTPREL16 74 /* half16* (sym+add)@dtprel */ ++#define R_PPC_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */ ++#define R_PPC_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */ ++#define R_PPC_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */ ++#define R_PPC_DTPREL32 78 /* word32 (sym+add)@dtprel */ ++#define R_PPC_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */ ++#define R_PPC_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */ ++#define R_PPC_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */ ++#define R_PPC_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */ ++#define R_PPC_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */ ++#define R_PPC_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */ ++#define R_PPC_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */ ++#define R_PPC_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */ ++#define R_PPC_GOT_TPREL16 87 /* half16* (sym+add)@got@tprel */ ++#define R_PPC_GOT_TPREL16_LO 88 /* half16 (sym+add)@got@tprel@l */ ++#define R_PPC_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */ ++#define R_PPC_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */ ++#define R_PPC_GOT_DTPREL16 91 /* half16* (sym+add)@got@dtprel */ ++#define R_PPC_GOT_DTPREL16_LO 92 /* half16* (sym+add)@got@dtprel@l */ ++#define R_PPC_GOT_DTPREL16_HI 93 /* half16* (sym+add)@got@dtprel@h */ ++#define R_PPC_GOT_DTPREL16_HA 94 /* half16* (sym+add)@got@dtprel@ha */ ++ ++/* Keep this the last entry. */ ++#define R_PPC_NUM 95 ++ ++/* The remaining relocs are from the Embedded ELF ABI, and are not ++ in the SVR4 ELF ABI. */ ++#define R_PPC_EMB_NADDR32 101 ++#define R_PPC_EMB_NADDR16 102 ++#define R_PPC_EMB_NADDR16_LO 103 ++#define R_PPC_EMB_NADDR16_HI 104 ++#define R_PPC_EMB_NADDR16_HA 105 ++#define R_PPC_EMB_SDAI16 106 ++#define R_PPC_EMB_SDA2I16 107 ++#define R_PPC_EMB_SDA2REL 108 ++#define R_PPC_EMB_SDA21 109 /* 16 bit offset in SDA */ ++#define R_PPC_EMB_MRKREF 110 ++#define R_PPC_EMB_RELSEC16 111 ++#define R_PPC_EMB_RELST_LO 112 ++#define R_PPC_EMB_RELST_HI 113 ++#define R_PPC_EMB_RELST_HA 114 ++#define R_PPC_EMB_BIT_FLD 115 ++#define R_PPC_EMB_RELSDA 116 /* 16 bit relative offset in SDA */ ++ ++/* Diab tool relocations. */ ++#define R_PPC_DIAB_SDA21_LO 180 /* like EMB_SDA21, but lower 16 bit */ ++#define R_PPC_DIAB_SDA21_HI 181 /* like EMB_SDA21, but high 16 bit */ ++#define R_PPC_DIAB_SDA21_HA 182 /* like EMB_SDA21, adjusted high 16 */ ++#define R_PPC_DIAB_RELSDA_LO 183 /* like EMB_RELSDA, but lower 16 bit */ ++#define R_PPC_DIAB_RELSDA_HI 184 /* like EMB_RELSDA, but high 16 bit */ ++#define R_PPC_DIAB_RELSDA_HA 185 /* like EMB_RELSDA, adjusted high 16 */ ++ ++/* This is a phony reloc to handle any old fashioned TOC16 references ++ that may still be in object files. */ ++#define R_PPC_TOC16 255 ++ ++ ++/* PowerPC64 relocations defined by the ABIs */ ++#define R_PPC64_NONE R_PPC_NONE ++#define R_PPC64_ADDR32 R_PPC_ADDR32 /* 32bit absolute address */ ++#define R_PPC64_ADDR24 R_PPC_ADDR24 /* 26bit address, word aligned */ ++#define R_PPC64_ADDR16 R_PPC_ADDR16 /* 16bit absolute address */ ++#define R_PPC64_ADDR16_LO R_PPC_ADDR16_LO /* lower 16bits of address */ ++#define R_PPC64_ADDR16_HI R_PPC_ADDR16_HI /* high 16bits of address. */ ++#define R_PPC64_ADDR16_HA R_PPC_ADDR16_HA /* adjusted high 16bits. */ ++#define R_PPC64_ADDR14 R_PPC_ADDR14 /* 16bit address, word aligned */ ++#define R_PPC64_ADDR14_BRTAKEN R_PPC_ADDR14_BRTAKEN ++#define R_PPC64_ADDR14_BRNTAKEN R_PPC_ADDR14_BRNTAKEN ++#define R_PPC64_REL24 R_PPC_REL24 /* PC-rel. 26 bit, word aligned */ ++#define R_PPC64_REL14 R_PPC_REL14 /* PC relative 16 bit */ ++#define R_PPC64_REL14_BRTAKEN R_PPC_REL14_BRTAKEN ++#define R_PPC64_REL14_BRNTAKEN R_PPC_REL14_BRNTAKEN ++#define R_PPC64_GOT16 R_PPC_GOT16 ++#define R_PPC64_GOT16_LO R_PPC_GOT16_LO ++#define R_PPC64_GOT16_HI R_PPC_GOT16_HI ++#define R_PPC64_GOT16_HA R_PPC_GOT16_HA ++ ++#define R_PPC64_COPY R_PPC_COPY ++#define R_PPC64_GLOB_DAT R_PPC_GLOB_DAT ++#define R_PPC64_JMP_SLOT R_PPC_JMP_SLOT ++#define R_PPC64_RELATIVE R_PPC_RELATIVE ++ ++#define R_PPC64_UADDR32 R_PPC_UADDR32 ++#define R_PPC64_UADDR16 R_PPC_UADDR16 ++#define R_PPC64_REL32 R_PPC_REL32 ++#define R_PPC64_PLT32 R_PPC_PLT32 ++#define R_PPC64_PLTREL32 R_PPC_PLTREL32 ++#define R_PPC64_PLT16_LO R_PPC_PLT16_LO ++#define R_PPC64_PLT16_HI R_PPC_PLT16_HI ++#define R_PPC64_PLT16_HA R_PPC_PLT16_HA ++ ++#define R_PPC64_SECTOFF R_PPC_SECTOFF ++#define R_PPC64_SECTOFF_LO R_PPC_SECTOFF_LO ++#define R_PPC64_SECTOFF_HI R_PPC_SECTOFF_HI ++#define R_PPC64_SECTOFF_HA R_PPC_SECTOFF_HA ++#define R_PPC64_ADDR30 37 /* word30 (S + A - P) >> 2 */ ++#define R_PPC64_ADDR64 38 /* doubleword64 S + A */ ++#define R_PPC64_ADDR16_HIGHER 39 /* half16 #higher(S + A) */ ++#define R_PPC64_ADDR16_HIGHERA 40 /* half16 #highera(S + A) */ ++#define R_PPC64_ADDR16_HIGHEST 41 /* half16 #highest(S + A) */ ++#define R_PPC64_ADDR16_HIGHESTA 42 /* half16 #highesta(S + A) */ ++#define R_PPC64_UADDR64 43 /* doubleword64 S + A */ ++#define R_PPC64_REL64 44 /* doubleword64 S + A - P */ ++#define R_PPC64_PLT64 45 /* doubleword64 L + A */ ++#define R_PPC64_PLTREL64 46 /* doubleword64 L + A - P */ ++#define R_PPC64_TOC16 47 /* half16* S + A - .TOC */ ++#define R_PPC64_TOC16_LO 48 /* half16 #lo(S + A - .TOC.) */ ++#define R_PPC64_TOC16_HI 49 /* half16 #hi(S + A - .TOC.) */ ++#define R_PPC64_TOC16_HA 50 /* half16 #ha(S + A - .TOC.) */ ++#define R_PPC64_TOC 51 /* doubleword64 .TOC */ ++#define R_PPC64_PLTGOT16 52 /* half16* M + A */ ++#define R_PPC64_PLTGOT16_LO 53 /* half16 #lo(M + A) */ ++#define R_PPC64_PLTGOT16_HI 54 /* half16 #hi(M + A) */ ++#define R_PPC64_PLTGOT16_HA 55 /* half16 #ha(M + A) */ ++ ++#define R_PPC64_ADDR16_DS 56 /* half16ds* (S + A) >> 2 */ ++#define R_PPC64_ADDR16_LO_DS 57 /* half16ds #lo(S + A) >> 2 */ ++#define R_PPC64_GOT16_DS 58 /* half16ds* (G + A) >> 2 */ ++#define R_PPC64_GOT16_LO_DS 59 /* half16ds #lo(G + A) >> 2 */ ++#define R_PPC64_PLT16_LO_DS 60 /* half16ds #lo(L + A) >> 2 */ ++#define R_PPC64_SECTOFF_DS 61 /* half16ds* (R + A) >> 2 */ ++#define R_PPC64_SECTOFF_LO_DS 62 /* half16ds #lo(R + A) >> 2 */ ++#define R_PPC64_TOC16_DS 63 /* half16ds* (S + A - .TOC.) >> 2 */ ++#define R_PPC64_TOC16_LO_DS 64 /* half16ds #lo(S + A - .TOC.) >> 2 */ ++#define R_PPC64_PLTGOT16_DS 65 /* half16ds* (M + A) >> 2 */ ++#define R_PPC64_PLTGOT16_LO_DS 66 /* half16ds #lo(M + A) >> 2 */ ++ ++/* PowerPC64 relocations defined for the TLS access ABI. */ ++#define R_PPC64_TLS 67 /* none (sym+add)@tls */ ++#define R_PPC64_DTPMOD64 68 /* doubleword64 (sym+add)@dtpmod */ ++#define R_PPC64_TPREL16 69 /* half16* (sym+add)@tprel */ ++#define R_PPC64_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */ ++#define R_PPC64_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */ ++#define R_PPC64_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */ ++#define R_PPC64_TPREL64 73 /* doubleword64 (sym+add)@tprel */ ++#define R_PPC64_DTPREL16 74 /* half16* (sym+add)@dtprel */ ++#define R_PPC64_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */ ++#define R_PPC64_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */ ++#define R_PPC64_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */ ++#define R_PPC64_DTPREL64 78 /* doubleword64 (sym+add)@dtprel */ ++#define R_PPC64_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */ ++#define R_PPC64_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */ ++#define R_PPC64_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */ ++#define R_PPC64_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */ ++#define R_PPC64_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */ ++#define R_PPC64_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */ ++#define R_PPC64_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */ ++#define R_PPC64_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */ ++#define R_PPC64_GOT_TPREL16_DS 87 /* half16ds* (sym+add)@got@tprel */ ++#define R_PPC64_GOT_TPREL16_LO_DS 88 /* half16ds (sym+add)@got@tprel@l */ ++#define R_PPC64_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */ ++#define R_PPC64_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */ ++#define R_PPC64_GOT_DTPREL16_DS 91 /* half16ds* (sym+add)@got@dtprel */ ++#define R_PPC64_GOT_DTPREL16_LO_DS 92 /* half16ds (sym+add)@got@dtprel@l */ ++#define R_PPC64_GOT_DTPREL16_HI 93 /* half16 (sym+add)@got@dtprel@h */ ++#define R_PPC64_GOT_DTPREL16_HA 94 /* half16 (sym+add)@got@dtprel@ha */ ++#define R_PPC64_TPREL16_DS 95 /* half16ds* (sym+add)@tprel */ ++#define R_PPC64_TPREL16_LO_DS 96 /* half16ds (sym+add)@tprel@l */ ++#define R_PPC64_TPREL16_HIGHER 97 /* half16 (sym+add)@tprel@higher */ ++#define R_PPC64_TPREL16_HIGHERA 98 /* half16 (sym+add)@tprel@highera */ ++#define R_PPC64_TPREL16_HIGHEST 99 /* half16 (sym+add)@tprel@highest */ ++#define R_PPC64_TPREL16_HIGHESTA 100 /* half16 (sym+add)@tprel@highesta */ ++#define R_PPC64_DTPREL16_DS 101 /* half16ds* (sym+add)@dtprel */ ++#define R_PPC64_DTPREL16_LO_DS 102 /* half16ds (sym+add)@dtprel@l */ ++#define R_PPC64_DTPREL16_HIGHER 103 /* half16 (sym+add)@dtprel@higher */ ++#define R_PPC64_DTPREL16_HIGHERA 104 /* half16 (sym+add)@dtprel@highera */ ++#define R_PPC64_DTPREL16_HIGHEST 105 /* half16 (sym+add)@dtprel@highest */ ++#define R_PPC64_DTPREL16_HIGHESTA 106 /* half16 (sym+add)@dtprel@highesta */ ++ ++/* Keep this the last entry. */ ++#define R_PPC64_NUM 107 ++ ++/* PowerPC64 specific values for the Dyn d_tag field. */ ++#define DT_PPC64_GLINK (DT_LOPROC + 0) ++#define DT_PPC64_NUM 1 ++ ++ ++/* ARM specific declarations */ ++ ++/* Processor specific flags for the ELF header e_flags field. */ ++#define EF_ARM_RELEXEC 0x01 ++#define EF_ARM_HASENTRY 0x02 ++#define EF_ARM_INTERWORK 0x04 ++#define EF_ARM_APCS_26 0x08 ++#define EF_ARM_APCS_FLOAT 0x10 ++#define EF_ARM_PIC 0x20 ++#define EF_ARM_ALIGN8 0x40 /* 8-bit structure alignment is in use */ ++#define EF_ARM_NEW_ABI 0x80 ++#define EF_ARM_OLD_ABI 0x100 ++ ++/* Other constants defined in the ARM ELF spec. version B-01. */ ++/* NB. These conflict with values defined above. */ ++#define EF_ARM_SYMSARESORTED 0x04 ++#define EF_ARM_DYNSYMSUSESEGIDX 0x08 ++#define EF_ARM_MAPSYMSFIRST 0x10 ++#define EF_ARM_EABIMASK 0XFF000000 ++ ++#define EF_ARM_EABI_VERSION(flags) ((flags) & EF_ARM_EABIMASK) ++#define EF_ARM_EABI_UNKNOWN 0x00000000 ++#define EF_ARM_EABI_VER1 0x01000000 ++#define EF_ARM_EABI_VER2 0x02000000 ++ ++/* Additional symbol types for Thumb */ ++#define STT_ARM_TFUNC 0xd ++ ++/* ARM-specific values for sh_flags */ ++#define SHF_ARM_ENTRYSECT 0x10000000 /* Section contains an entry point */ ++#define SHF_ARM_COMDEF 0x80000000 /* Section may be multiply defined ++ in the input to a link step */ ++ ++/* ARM-specific program header flags */ ++#define PF_ARM_SB 0x10000000 /* Segment contains the location ++ addressed by the static base */ ++ ++/* ARM relocs. */ ++#define R_ARM_NONE 0 /* No reloc */ ++#define R_ARM_PC24 1 /* PC relative 26 bit branch */ ++#define R_ARM_ABS32 2 /* Direct 32 bit */ ++#define R_ARM_REL32 3 /* PC relative 32 bit */ ++#define R_ARM_PC13 4 ++#define R_ARM_ABS16 5 /* Direct 16 bit */ ++#define R_ARM_ABS12 6 /* Direct 12 bit */ ++#define R_ARM_THM_ABS5 7 ++#define R_ARM_ABS8 8 /* Direct 8 bit */ ++#define R_ARM_SBREL32 9 ++#define R_ARM_THM_PC22 10 ++#define R_ARM_THM_PC8 11 ++#define R_ARM_AMP_VCALL9 12 ++#define R_ARM_SWI24 13 ++#define R_ARM_THM_SWI8 14 ++#define R_ARM_XPC25 15 ++#define R_ARM_THM_XPC22 16 ++#define R_ARM_COPY 20 /* Copy symbol at runtime */ ++#define R_ARM_GLOB_DAT 21 /* Create GOT entry */ ++#define R_ARM_JUMP_SLOT 22 /* Create PLT entry */ ++#define R_ARM_RELATIVE 23 /* Adjust by program base */ ++#define R_ARM_GOTOFF 24 /* 32 bit offset to GOT */ ++#define R_ARM_GOTPC 25 /* 32 bit PC relative offset to GOT */ ++#define R_ARM_GOT32 26 /* 32 bit GOT entry */ ++#define R_ARM_PLT32 27 /* 32 bit PLT address */ ++#define R_ARM_ALU_PCREL_7_0 32 ++#define R_ARM_ALU_PCREL_15_8 33 ++#define R_ARM_ALU_PCREL_23_15 34 ++#define R_ARM_LDR_SBREL_11_0 35 ++#define R_ARM_ALU_SBREL_19_12 36 ++#define R_ARM_ALU_SBREL_27_20 37 ++#define R_ARM_GNU_VTENTRY 100 ++#define R_ARM_GNU_VTINHERIT 101 ++#define R_ARM_THM_PC11 102 /* thumb unconditional branch */ ++#define R_ARM_THM_PC9 103 /* thumb conditional branch */ ++#define R_ARM_RXPC25 249 ++#define R_ARM_RSBREL32 250 ++#define R_ARM_THM_RPC22 251 ++#define R_ARM_RREL32 252 ++#define R_ARM_RABS22 253 ++#define R_ARM_RPC24 254 ++#define R_ARM_RBASE 255 ++/* Keep this the last entry. */ ++#define R_ARM_NUM 256 ++ ++/* IA-64 specific declarations. */ ++ ++/* Processor specific flags for the Ehdr e_flags field. */ ++#define EF_IA_64_MASKOS 0x0000000f /* os-specific flags */ ++#define EF_IA_64_ABI64 0x00000010 /* 64-bit ABI */ ++#define EF_IA_64_ARCH 0xff000000 /* arch. version mask */ ++ ++/* Processor specific values for the Phdr p_type field. */ ++#define PT_IA_64_ARCHEXT (PT_LOPROC + 0) /* arch extension bits */ ++#define PT_IA_64_UNWIND (PT_LOPROC + 1) /* ia64 unwind bits */ ++ ++/* Processor specific flags for the Phdr p_flags field. */ ++#define PF_IA_64_NORECOV 0x80000000 /* spec insns w/o recovery */ ++ ++/* Processor specific values for the Shdr sh_type field. */ ++#define SHT_IA_64_EXT (SHT_LOPROC + 0) /* extension bits */ ++#define SHT_IA_64_UNWIND (SHT_LOPROC + 1) /* unwind bits */ ++ ++/* Processor specific flags for the Shdr sh_flags field. */ ++#define SHF_IA_64_SHORT 0x10000000 /* section near gp */ ++#define SHF_IA_64_NORECOV 0x20000000 /* spec insns w/o recovery */ ++ ++/* Processor specific values for the Dyn d_tag field. */ ++#define DT_IA_64_PLT_RESERVE (DT_LOPROC + 0) ++#define DT_IA_64_NUM 1 ++ ++/* IA-64 relocations. */ ++#define R_IA64_NONE 0x00 /* none */ ++#define R_IA64_IMM14 0x21 /* symbol + addend, add imm14 */ ++#define R_IA64_IMM22 0x22 /* symbol + addend, add imm22 */ ++#define R_IA64_IMM64 0x23 /* symbol + addend, mov imm64 */ ++#define R_IA64_DIR32MSB 0x24 /* symbol + addend, data4 MSB */ ++#define R_IA64_DIR32LSB 0x25 /* symbol + addend, data4 LSB */ ++#define R_IA64_DIR64MSB 0x26 /* symbol + addend, data8 MSB */ ++#define R_IA64_DIR64LSB 0x27 /* symbol + addend, data8 LSB */ ++#define R_IA64_GPREL22 0x2a /* @gprel(sym + add), add imm22 */ ++#define R_IA64_GPREL64I 0x2b /* @gprel(sym + add), mov imm64 */ ++#define R_IA64_GPREL32MSB 0x2c /* @gprel(sym + add), data4 MSB */ ++#define R_IA64_GPREL32LSB 0x2d /* @gprel(sym + add), data4 LSB */ ++#define R_IA64_GPREL64MSB 0x2e /* @gprel(sym + add), data8 MSB */ ++#define R_IA64_GPREL64LSB 0x2f /* @gprel(sym + add), data8 LSB */ ++#define R_IA64_LTOFF22 0x32 /* @ltoff(sym + add), add imm22 */ ++#define R_IA64_LTOFF64I 0x33 /* @ltoff(sym + add), mov imm64 */ ++#define R_IA64_PLTOFF22 0x3a /* @pltoff(sym + add), add imm22 */ ++#define R_IA64_PLTOFF64I 0x3b /* @pltoff(sym + add), mov imm64 */ ++#define R_IA64_PLTOFF64MSB 0x3e /* @pltoff(sym + add), data8 MSB */ ++#define R_IA64_PLTOFF64LSB 0x3f /* @pltoff(sym + add), data8 LSB */ ++#define R_IA64_FPTR64I 0x43 /* @fptr(sym + add), mov imm64 */ ++#define R_IA64_FPTR32MSB 0x44 /* @fptr(sym + add), data4 MSB */ ++#define R_IA64_FPTR32LSB 0x45 /* @fptr(sym + add), data4 LSB */ ++#define R_IA64_FPTR64MSB 0x46 /* @fptr(sym + add), data8 MSB */ ++#define R_IA64_FPTR64LSB 0x47 /* @fptr(sym + add), data8 LSB */ ++#define R_IA64_PCREL60B 0x48 /* @pcrel(sym + add), brl */ ++#define R_IA64_PCREL21B 0x49 /* @pcrel(sym + add), ptb, call */ ++#define R_IA64_PCREL21M 0x4a /* @pcrel(sym + add), chk.s */ ++#define R_IA64_PCREL21F 0x4b /* @pcrel(sym + add), fchkf */ ++#define R_IA64_PCREL32MSB 0x4c /* @pcrel(sym + add), data4 MSB */ ++#define R_IA64_PCREL32LSB 0x4d /* @pcrel(sym + add), data4 LSB */ ++#define R_IA64_PCREL64MSB 0x4e /* @pcrel(sym + add), data8 MSB */ ++#define R_IA64_PCREL64LSB 0x4f /* @pcrel(sym + add), data8 LSB */ ++#define R_IA64_LTOFF_FPTR22 0x52 /* @ltoff(@fptr(s+a)), imm22 */ ++#define R_IA64_LTOFF_FPTR64I 0x53 /* @ltoff(@fptr(s+a)), imm64 */ ++#define R_IA64_LTOFF_FPTR32MSB 0x54 /* @ltoff(@fptr(s+a)), data4 MSB */ ++#define R_IA64_LTOFF_FPTR32LSB 0x55 /* @ltoff(@fptr(s+a)), data4 LSB */ ++#define R_IA64_LTOFF_FPTR64MSB 0x56 /* @ltoff(@fptr(s+a)), data8 MSB */ ++#define R_IA64_LTOFF_FPTR64LSB 0x57 /* @ltoff(@fptr(s+a)), data8 LSB */ ++#define R_IA64_SEGREL32MSB 0x5c /* @segrel(sym + add), data4 MSB */ ++#define R_IA64_SEGREL32LSB 0x5d /* @segrel(sym + add), data4 LSB */ ++#define R_IA64_SEGREL64MSB 0x5e /* @segrel(sym + add), data8 MSB */ ++#define R_IA64_SEGREL64LSB 0x5f /* @segrel(sym + add), data8 LSB */ ++#define R_IA64_SECREL32MSB 0x64 /* @secrel(sym + add), data4 MSB */ ++#define R_IA64_SECREL32LSB 0x65 /* @secrel(sym + add), data4 LSB */ ++#define R_IA64_SECREL64MSB 0x66 /* @secrel(sym + add), data8 MSB */ ++#define R_IA64_SECREL64LSB 0x67 /* @secrel(sym + add), data8 LSB */ ++#define R_IA64_REL32MSB 0x6c /* data 4 + REL */ ++#define R_IA64_REL32LSB 0x6d /* data 4 + REL */ ++#define R_IA64_REL64MSB 0x6e /* data 8 + REL */ ++#define R_IA64_REL64LSB 0x6f /* data 8 + REL */ ++#define R_IA64_LTV32MSB 0x74 /* symbol + addend, data4 MSB */ ++#define R_IA64_LTV32LSB 0x75 /* symbol + addend, data4 LSB */ ++#define R_IA64_LTV64MSB 0x76 /* symbol + addend, data8 MSB */ ++#define R_IA64_LTV64LSB 0x77 /* symbol + addend, data8 LSB */ ++#define R_IA64_PCREL21BI 0x79 /* @pcrel(sym + add), 21bit inst */ ++#define R_IA64_PCREL22 0x7a /* @pcrel(sym + add), 22bit inst */ ++#define R_IA64_PCREL64I 0x7b /* @pcrel(sym + add), 64bit inst */ ++#define R_IA64_IPLTMSB 0x80 /* dynamic reloc, imported PLT, MSB */ ++#define R_IA64_IPLTLSB 0x81 /* dynamic reloc, imported PLT, LSB */ ++#define R_IA64_COPY 0x84 /* copy relocation */ ++#define R_IA64_SUB 0x85 /* Addend and symbol difference */ ++#define R_IA64_LTOFF22X 0x86 /* LTOFF22, relaxable. */ ++#define R_IA64_LDXMOV 0x87 /* Use of LTOFF22X. */ ++#define R_IA64_TPREL14 0x91 /* @tprel(sym + add), imm14 */ ++#define R_IA64_TPREL22 0x92 /* @tprel(sym + add), imm22 */ ++#define R_IA64_TPREL64I 0x93 /* @tprel(sym + add), imm64 */ ++#define R_IA64_TPREL64MSB 0x96 /* @tprel(sym + add), data8 MSB */ ++#define R_IA64_TPREL64LSB 0x97 /* @tprel(sym + add), data8 LSB */ ++#define R_IA64_LTOFF_TPREL22 0x9a /* @ltoff(@tprel(s+a)), imm2 */ ++#define R_IA64_DTPMOD64MSB 0xa6 /* @dtpmod(sym + add), data8 MSB */ ++#define R_IA64_DTPMOD64LSB 0xa7 /* @dtpmod(sym + add), data8 LSB */ ++#define R_IA64_LTOFF_DTPMOD22 0xaa /* @ltoff(@dtpmod(sym + add)), imm22 */ ++#define R_IA64_DTPREL14 0xb1 /* @dtprel(sym + add), imm14 */ ++#define R_IA64_DTPREL22 0xb2 /* @dtprel(sym + add), imm22 */ ++#define R_IA64_DTPREL64I 0xb3 /* @dtprel(sym + add), imm64 */ ++#define R_IA64_DTPREL32MSB 0xb4 /* @dtprel(sym + add), data4 MSB */ ++#define R_IA64_DTPREL32LSB 0xb5 /* @dtprel(sym + add), data4 LSB */ ++#define R_IA64_DTPREL64MSB 0xb6 /* @dtprel(sym + add), data8 MSB */ ++#define R_IA64_DTPREL64LSB 0xb7 /* @dtprel(sym + add), data8 LSB */ ++#define R_IA64_LTOFF_DTPREL22 0xba /* @ltoff(@dtprel(s+a)), imm22 */ ++ ++/* SH specific declarations */ ++ ++/* SH relocs. */ ++#define R_SH_NONE 0 ++#define R_SH_DIR32 1 ++#define R_SH_REL32 2 ++#define R_SH_DIR8WPN 3 ++#define R_SH_IND12W 4 ++#define R_SH_DIR8WPL 5 ++#define R_SH_DIR8WPZ 6 ++#define R_SH_DIR8BP 7 ++#define R_SH_DIR8W 8 ++#define R_SH_DIR8L 9 ++#define R_SH_SWITCH16 25 ++#define R_SH_SWITCH32 26 ++#define R_SH_USES 27 ++#define R_SH_COUNT 28 ++#define R_SH_ALIGN 29 ++#define R_SH_CODE 30 ++#define R_SH_DATA 31 ++#define R_SH_LABEL 32 ++#define R_SH_SWITCH8 33 ++#define R_SH_GNU_VTINHERIT 34 ++#define R_SH_GNU_VTENTRY 35 ++#define R_SH_TLS_GD_32 144 ++#define R_SH_TLS_LD_32 145 ++#define R_SH_TLS_LDO_32 146 ++#define R_SH_TLS_IE_32 147 ++#define R_SH_TLS_LE_32 148 ++#define R_SH_TLS_DTPMOD32 149 ++#define R_SH_TLS_DTPOFF32 150 ++#define R_SH_TLS_TPOFF32 151 ++#define R_SH_GOT32 160 ++#define R_SH_PLT32 161 ++#define R_SH_COPY 162 ++#define R_SH_GLOB_DAT 163 ++#define R_SH_JMP_SLOT 164 ++#define R_SH_RELATIVE 165 ++#define R_SH_GOTOFF 166 ++#define R_SH_GOTPC 167 ++/* Keep this the last entry. */ ++#define R_SH_NUM 256 ++ ++/* Additional s390 relocs */ ++ ++#define R_390_NONE 0 /* No reloc. */ ++#define R_390_8 1 /* Direct 8 bit. */ ++#define R_390_12 2 /* Direct 12 bit. */ ++#define R_390_16 3 /* Direct 16 bit. */ ++#define R_390_32 4 /* Direct 32 bit. */ ++#define R_390_PC32 5 /* PC relative 32 bit. */ ++#define R_390_GOT12 6 /* 12 bit GOT offset. */ ++#define R_390_GOT32 7 /* 32 bit GOT offset. */ ++#define R_390_PLT32 8 /* 32 bit PC relative PLT address. */ ++#define R_390_COPY 9 /* Copy symbol at runtime. */ ++#define R_390_GLOB_DAT 10 /* Create GOT entry. */ ++#define R_390_JMP_SLOT 11 /* Create PLT entry. */ ++#define R_390_RELATIVE 12 /* Adjust by program base. */ ++#define R_390_GOTOFF32 13 /* 32 bit offset to GOT. */ ++#define R_390_GOTPC 14 /* 32 bit PC relative offset to GOT. */ ++#define R_390_GOT16 15 /* 16 bit GOT offset. */ ++#define R_390_PC16 16 /* PC relative 16 bit. */ ++#define R_390_PC16DBL 17 /* PC relative 16 bit shifted by 1. */ ++#define R_390_PLT16DBL 18 /* 16 bit PC rel. PLT shifted by 1. */ ++#define R_390_PC32DBL 19 /* PC relative 32 bit shifted by 1. */ ++#define R_390_PLT32DBL 20 /* 32 bit PC rel. PLT shifted by 1. */ ++#define R_390_GOTPCDBL 21 /* 32 bit PC rel. GOT shifted by 1. */ ++#define R_390_64 22 /* Direct 64 bit. */ ++#define R_390_PC64 23 /* PC relative 64 bit. */ ++#define R_390_GOT64 24 /* 64 bit GOT offset. */ ++#define R_390_PLT64 25 /* 64 bit PC relative PLT address. */ ++#define R_390_GOTENT 26 /* 32 bit PC rel. to GOT entry >> 1. */ ++#define R_390_GOTOFF16 27 /* 16 bit offset to GOT. */ ++#define R_390_GOTOFF64 28 /* 64 bit offset to GOT. */ ++#define R_390_GOTPLT12 29 /* 12 bit offset to jump slot. */ ++#define R_390_GOTPLT16 30 /* 16 bit offset to jump slot. */ ++#define R_390_GOTPLT32 31 /* 32 bit offset to jump slot. */ ++#define R_390_GOTPLT64 32 /* 64 bit offset to jump slot. */ ++#define R_390_GOTPLTENT 33 /* 32 bit rel. offset to jump slot. */ ++#define R_390_PLTOFF16 34 /* 16 bit offset from GOT to PLT. */ ++#define R_390_PLTOFF32 35 /* 32 bit offset from GOT to PLT. */ ++#define R_390_PLTOFF64 36 /* 16 bit offset from GOT to PLT. */ ++#define R_390_TLS_LOAD 37 /* Tag for load insn in TLS code. */ ++#define R_390_TLS_GDCALL 38 /* Tag for function call in general ++ dynamic TLS code. */ ++#define R_390_TLS_LDCALL 39 /* Tag for function call in local ++ dynamic TLS code. */ ++#define R_390_TLS_GD32 40 /* Direct 32 bit for general dynamic ++ thread local data. */ ++#define R_390_TLS_GD64 41 /* Direct 64 bit for general dynamic ++ thread local data. */ ++#define R_390_TLS_GOTIE12 42 /* 12 bit GOT offset for static TLS ++ block offset. */ ++#define R_390_TLS_GOTIE32 43 /* 32 bit GOT offset for static TLS ++ block offset. */ ++#define R_390_TLS_GOTIE64 44 /* 64 bit GOT offset for static TLS ++ block offset. */ ++#define R_390_TLS_LDM32 45 /* Direct 32 bit for local dynamic ++ thread local data in LE code. */ ++#define R_390_TLS_LDM64 46 /* Direct 64 bit for local dynamic ++ thread local data in LE code. */ ++#define R_390_TLS_IE32 47 /* 32 bit address of GOT entry for ++ negated static TLS block offset. */ ++#define R_390_TLS_IE64 48 /* 64 bit address of GOT entry for ++ negated static TLS block offset. */ ++#define R_390_TLS_IEENT 49 /* 32 bit rel. offset to GOT entry for ++ negated static TLS block offset. */ ++#define R_390_TLS_LE32 50 /* 32 bit negated offset relative to ++ static TLS block. */ ++#define R_390_TLS_LE64 51 /* 64 bit negated offset relative to ++ static TLS block. */ ++#define R_390_TLS_LDO32 52 /* 32 bit offset relative to TLS ++ block. */ ++#define R_390_TLS_LDO64 53 /* 64 bit offset relative to TLS ++ block. */ ++#define R_390_TLS_DTPMOD 54 /* ID of module containing symbol. */ ++#define R_390_TLS_DTPOFF 55 /* Offset in TLS block. */ ++#define R_390_TLS_TPOFF 56 /* Negated offset in static TLS ++ block. */ ++ ++/* Keep this the last entry. */ ++#define R_390_NUM 57 ++ ++/* CRIS relocations. */ ++#define R_CRIS_NONE 0 ++#define R_CRIS_8 1 ++#define R_CRIS_16 2 ++#define R_CRIS_32 3 ++#define R_CRIS_8_PCREL 4 ++#define R_CRIS_16_PCREL 5 ++#define R_CRIS_32_PCREL 6 ++#define R_CRIS_GNU_VTINHERIT 7 ++#define R_CRIS_GNU_VTENTRY 8 ++#define R_CRIS_COPY 9 ++#define R_CRIS_GLOB_DAT 10 ++#define R_CRIS_JUMP_SLOT 11 ++#define R_CRIS_RELATIVE 12 ++#define R_CRIS_16_GOT 13 ++#define R_CRIS_32_GOT 14 ++#define R_CRIS_16_GOTPLT 15 ++#define R_CRIS_32_GOTPLT 16 ++#define R_CRIS_32_GOTREL 17 ++#define R_CRIS_32_PLT_GOTREL 18 ++#define R_CRIS_32_PLT_PCREL 19 ++ ++#define R_CRIS_NUM 20 ++ ++/* AMD x86-64 relocations. */ ++#define R_X86_64_NONE 0 /* No reloc */ ++#define R_X86_64_64 1 /* Direct 64 bit */ ++#define R_X86_64_PC32 2 /* PC relative 32 bit signed */ ++#define R_X86_64_GOT32 3 /* 32 bit GOT entry */ ++#define R_X86_64_PLT32 4 /* 32 bit PLT address */ ++#define R_X86_64_COPY 5 /* Copy symbol at runtime */ ++#define R_X86_64_GLOB_DAT 6 /* Create GOT entry */ ++#define R_X86_64_JUMP_SLOT 7 /* Create PLT entry */ ++#define R_X86_64_RELATIVE 8 /* Adjust by program base */ ++#define R_X86_64_GOTPCREL 9 /* 32 bit signed PC relative ++ offset to GOT */ ++#define R_X86_64_32 10 /* Direct 32 bit zero extended */ ++#define R_X86_64_32S 11 /* Direct 32 bit sign extended */ ++#define R_X86_64_16 12 /* Direct 16 bit zero extended */ ++#define R_X86_64_PC16 13 /* 16 bit sign extended pc relative */ ++#define R_X86_64_8 14 /* Direct 8 bit sign extended */ ++#define R_X86_64_PC8 15 /* 8 bit sign extended pc relative */ ++#define R_X86_64_DTPMOD64 16 /* ID of module containing symbol */ ++#define R_X86_64_DTPOFF64 17 /* Offset in module's TLS block */ ++#define R_X86_64_TPOFF64 18 /* Offset in initial TLS block */ ++#define R_X86_64_TLSGD 19 /* 32 bit signed PC relative offset ++ to two GOT entries for GD symbol */ ++#define R_X86_64_TLSLD 20 /* 32 bit signed PC relative offset ++ to two GOT entries for LD symbol */ ++#define R_X86_64_DTPOFF32 21 /* Offset in TLS block */ ++#define R_X86_64_GOTTPOFF 22 /* 32 bit signed PC relative offset ++ to GOT entry for IE symbol */ ++#define R_X86_64_TPOFF32 23 /* Offset in initial TLS block */ ++ ++#define R_X86_64_NUM 24 ++ ++__END_DECLS ++ ++#endif /* elf.h */ + + #include "elfconfig.h" + +@@ -195,3 +2641,4 @@ + void fatal(const char *fmt, ...); + void warn(const char *fmt, ...); + void merror(const char *fmt, ...); ++ +diff -Nur linux-2.6.36.orig/scripts/mod/sumversion.c linux-2.6.36/scripts/mod/sumversion.c +--- linux-2.6.36.orig/scripts/mod/sumversion.c 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/scripts/mod/sumversion.c 2010-11-28 18:33:24.000000000 +0100 +@@ -1,4 +1,4 @@ +-#include ++/* #include */ + #ifdef __sun__ + #include + #else diff --git a/target/linux/patches/3.1.4/cris-etrax.patch b/target/linux/patches/3.1.4/cris-etrax.patch new file mode 100644 index 000000000..a80d9a8b8 --- /dev/null +++ b/target/linux/patches/3.1.4/cris-etrax.patch @@ -0,0 +1,12 @@ +diff -Nur linux-2.6.39.orig/arch/cris/arch-v32/drivers/i2c.h linux-2.6.39/arch/cris/arch-v32/drivers/i2c.h +--- linux-2.6.39.orig/arch/cris/arch-v32/drivers/i2c.h 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/arch/cris/arch-v32/drivers/i2c.h 2011-08-24 19:15:05.000000000 +0200 +@@ -2,7 +2,7 @@ + #include + + /* High level I2C actions */ +-int __init i2c_init(void); ++static int __init i2c_init(void); + int i2c_write(unsigned char theSlave, void *data, size_t nbytes); + int i2c_read(unsigned char theSlave, void *data, size_t nbytes); + int i2c_writereg(unsigned char theSlave, unsigned char theReg, unsigned char theValue); diff --git a/target/linux/patches/3.1.4/defaults.patch b/target/linux/patches/3.1.4/defaults.patch new file mode 100644 index 000000000..58aae610b --- /dev/null +++ b/target/linux/patches/3.1.4/defaults.patch @@ -0,0 +1,22 @@ +diff -Nur linux-3.0.4.orig/fs/Kconfig linux-3.0.4/fs/Kconfig +--- linux-3.0.4.orig/fs/Kconfig 2011-08-29 22:56:30.000000000 +0200 ++++ linux-3.0.4/fs/Kconfig 2011-10-15 22:08:44.000000000 +0200 +@@ -47,7 +47,7 @@ + def_bool n + + config EXPORTFS +- tristate ++ def_bool y + + config FILE_LOCKING + bool "Enable POSIX file locking API" if EXPERT +diff -Nur linux-3.0.4.orig/fs/notify/Kconfig linux-3.0.4/fs/notify/Kconfig +--- linux-3.0.4.orig/fs/notify/Kconfig 2011-08-29 22:56:30.000000000 +0200 ++++ linux-3.0.4/fs/notify/Kconfig 2011-10-15 22:02:00.000000000 +0200 +@@ -1,5 +1,5 @@ + config FSNOTIFY +- def_bool n ++ def_bool y + + source "fs/notify/dnotify/Kconfig" + source "fs/notify/inotify/Kconfig" diff --git a/target/linux/patches/3.1.4/fon2100.patch b/target/linux/patches/3.1.4/fon2100.patch new file mode 100644 index 000000000..038ff7020 --- /dev/null +++ b/target/linux/patches/3.1.4/fon2100.patch @@ -0,0 +1,6279 @@ +diff -Nur linux-2.6.39-rc7.orig/arch/mips/Kbuild.platforms linux-2.6.39-rc7/arch/mips/Kbuild.platforms +--- linux-2.6.39-rc7.orig/arch/mips/Kbuild.platforms 2011-05-10 04:33:54.000000000 +0200 ++++ linux-2.6.39-rc7/arch/mips/Kbuild.platforms 2011-05-15 21:34:57.000000000 +0200 +@@ -6,6 +6,7 @@ + platforms += bcm47xx + platforms += bcm63xx + platforms += cavium-octeon ++platforms += ar231x + platforms += cobalt + platforms += dec + platforms += emma +diff -Nur linux-2.6.39-rc7.orig/arch/mips/Kconfig linux-2.6.39-rc7/arch/mips/Kconfig +--- linux-2.6.39-rc7.orig/arch/mips/Kconfig 2011-05-10 04:33:54.000000000 +0200 ++++ linux-2.6.39-rc7/arch/mips/Kconfig 2011-05-16 12:11:11.000000000 +0200 +@@ -121,6 +121,21 @@ + help + Support for BCM63XX based boards + ++config ATHEROS_AR231X ++ bool "Atheros 231x/531x SoC support" ++ select CEVT_R4K ++ select CSRC_R4K ++ select DMA_NONCOHERENT ++ select IRQ_CPU ++ select SYS_HAS_CPU_MIPS32_R1 ++ select SYS_SUPPORTS_BIG_ENDIAN ++ select SYS_SUPPORTS_32BIT_KERNEL ++ select GENERIC_GPIO ++ select SYS_HAS_EARLY_PRINTK ++ select SYS_SUPPORTS_ZBOOT ++ help ++ Support for AR231x and AR531x based boards ++ + config MIPS_COBALT + bool "Cobalt Server" + select CEVT_R4K +@@ -738,6 +753,7 @@ + + endchoice + ++source "arch/mips/ar231x/Kconfig" + source "arch/mips/alchemy/Kconfig" + source "arch/mips/ath79/Kconfig" + source "arch/mips/bcm63xx/Kconfig" +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/Kconfig linux-2.6.39-rc7/arch/mips/ar231x/Kconfig +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/Kconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/Kconfig 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,27 @@ ++config ATHEROS_AR5312 ++ bool "Atheros 5312/2312+ support" ++ depends on ATHEROS_AR231X ++ default y ++ ++config ATHEROS_AR2315 ++ bool "Atheros 2315+ support" ++ depends on ATHEROS_AR231X ++ select DMA_NONCOHERENT ++ select CEVT_R4K ++ select CSRC_R4K ++ select IRQ_CPU ++ select SYS_HAS_CPU_MIPS32_R1 ++ select SYS_SUPPORTS_32BIT_KERNEL ++ select SYS_SUPPORTS_BIG_ENDIAN ++ select GENERIC_GPIO ++ default y ++ ++config ATHEROS_AR2315_PCI ++ bool "PCI support" ++ depends on ATHEROS_AR2315 ++ select HW_HAS_PCI ++ select PCI ++ select USB_ARCH_HAS_HCD ++ select USB_ARCH_HAS_OHCI ++ select USB_ARCH_HAS_EHCI ++ default n +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/Makefile linux-2.6.39-rc7/arch/mips/ar231x/Makefile +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/Makefile 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,17 @@ ++# ++# This file is subject to the terms and conditions of the GNU General Public ++# License. See the file "COPYING" in the main directory of this archive ++# for more details. ++# ++# Copyright (C) 2006 FON Technology, SL. ++# Copyright (C) 2006 Imre Kaloz ++# Copyright (C) 2006-2009 Felix Fietkau ++# ++ ++obj-y += board.o prom.o devices.o ++ ++obj-$(CONFIG_EARLY_PRINTK) += early_printk.o ++ ++obj-$(CONFIG_ATHEROS_AR5312) += ar5312.o ++obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o ++obj-$(CONFIG_ATHEROS_AR2315_PCI) += pci.o +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/Platform linux-2.6.39-rc7/arch/mips/ar231x/Platform +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/Platform 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/Platform 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,6 @@ ++# ++# Atheros AR5312/AR2312 WiSoC ++# ++platform-$(CONFIG_ATHEROS_AR231X) += ar231x/ ++cflags-$(CONFIG_ATHEROS_AR231X) += -I$(srctree)/arch/mips/include/asm/mach-ar231x ++load-$(CONFIG_ATHEROS_AR231X) += 0xffffffff80041000 +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/ar2315.c linux-2.6.39-rc7/arch/mips/ar231x/ar2315.c +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/ar2315.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/ar2315.c 2011-05-15 21:47:07.000000000 +0200 +@@ -0,0 +1,654 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. ++ * Copyright (C) 2006 FON Technology, SL. ++ * Copyright (C) 2006 Imre Kaloz ++ * Copyright (C) 2006 Felix Fietkau ++ */ ++ ++/* ++ * Platform devices for Atheros SoCs ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include "devices.h" ++#include "ar2315.h" ++ ++static u32 gpiointmask = 0, gpiointval = 0; ++ ++static inline void ar2315_gpio_irq(void) ++{ ++ u32 pend; ++ int bit = -1; ++ ++ /* only do one gpio interrupt at a time */ ++ pend = (ar231x_read_reg(AR2315_GPIO_DI) ^ gpiointval) & gpiointmask; ++ ++ if (pend) { ++ bit = fls(pend) - 1; ++ pend &= ~(1 << bit); ++ gpiointval ^= (1 << bit); ++ } ++ ++ if (!pend) ++ ar231x_write_reg(AR2315_ISR, AR2315_ISR_GPIO); ++ ++ /* Enable interrupt with edge detection */ ++ if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(bit)) != AR2315_GPIO_CR_I(bit)) ++ return; ++ ++ if (bit >= 0) ++ do_IRQ(AR531X_GPIO_IRQ_BASE + bit); ++} ++ ++#ifdef CONFIG_ATHEROS_AR2315_PCI ++static inline void pci_abort_irq(void) ++{ ++ ar231x_write_reg(AR2315_PCI_INT_STATUS, AR2315_PCI_ABORT_INT); ++} ++ ++static inline void pci_ack_irq(void) ++{ ++ ar231x_write_reg(AR2315_PCI_INT_STATUS, AR2315_PCI_EXT_INT); ++} ++ ++void ar2315_pci_irq(int irq) ++{ ++ if (ar231x_read_reg(AR2315_PCI_INT_STATUS) == AR2315_PCI_ABORT_INT) ++ pci_abort_irq(); ++ else { ++ do_IRQ(irq); ++ pci_ack_irq(); ++ } ++} ++#endif /* CONFIG_ATHEROS_AR2315_PCI */ ++ ++/* ++ * Called when an interrupt is received, this function ++ * determines exactly which interrupt it was, and it ++ * invokes the appropriate handler. ++ * ++ * Implicitly, we also define interrupt priority by ++ * choosing which to dispatch first. ++ */ ++static asmlinkage void ++ar2315_irq_dispatch(void) ++{ ++ int pending = read_c0_status() & read_c0_cause(); ++ ++ if (pending & CAUSEF_IP3) ++ do_IRQ(AR2315_IRQ_WLAN0_INTRS); ++ else if (pending & CAUSEF_IP4) ++ do_IRQ(AR2315_IRQ_ENET0_INTRS); ++#ifdef CONFIG_ATHEROS_AR2315_PCI ++ else if (pending & CAUSEF_IP5) ++ ar2315_pci_irq(AR2315_IRQ_LCBUS_PCI); ++#endif ++ else if (pending & CAUSEF_IP2) { ++ unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) & ar231x_read_reg(AR2315_IMR); ++ ++ if (misc_intr & AR2315_ISR_SPI) ++ do_IRQ(AR531X_MISC_IRQ_SPI); ++ else if (misc_intr & AR2315_ISR_TIMER) ++ do_IRQ(AR531X_MISC_IRQ_TIMER); ++ else if (misc_intr & AR2315_ISR_AHB) ++ do_IRQ(AR531X_MISC_IRQ_AHB_PROC); ++ else if (misc_intr & AR2315_ISR_GPIO) ++ ar2315_gpio_irq(); ++ else if (misc_intr & AR2315_ISR_UART0) ++ do_IRQ(AR531X_MISC_IRQ_UART0); ++ else if (misc_intr & AR2315_ISR_WD) ++ do_IRQ(AR531X_MISC_IRQ_WATCHDOG); ++ else ++ do_IRQ(AR531X_MISC_IRQ_NONE); ++ } else if (pending & CAUSEF_IP7) ++ do_IRQ(AR531X_IRQ_CPU_CLOCK); ++} ++ ++static void ar2315_set_gpiointmask(int gpio, int level) ++{ ++ u32 reg; ++ ++ reg = ar231x_read_reg(AR2315_GPIO_INT); ++ reg &= ~(AR2315_GPIO_INT_M | AR2315_GPIO_INT_LVL_M); ++ reg |= gpio | AR2315_GPIO_INT_LVL(level); ++ ar231x_write_reg(AR2315_GPIO_INT, reg); ++} ++ ++static void ar2315_gpio_intr_enable(struct irq_data *d) ++{ ++ unsigned int gpio = d->irq - AR531X_GPIO_IRQ_BASE; ++ ++ /* Enable interrupt with edge detection */ ++ if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(gpio)) != AR2315_GPIO_CR_I(gpio)) ++ return; ++ ++ gpiointmask |= (1 << gpio); ++ ar2315_set_gpiointmask(gpio, 3); ++} ++ ++static void ar2315_gpio_intr_disable(struct irq_data *d) ++{ ++ unsigned int gpio = d->irq - AR531X_GPIO_IRQ_BASE; ++ ++ /* Disable interrupt */ ++ gpiointmask &= ~(1 << gpio); ++ ar2315_set_gpiointmask(gpio, 0); ++} ++ ++static struct irq_chip ar2315_gpio_intr_controller = { ++ .name = "AR2315-GPIO", ++ .irq_ack = ar2315_gpio_intr_disable, ++ .irq_mask_ack = ar2315_gpio_intr_disable, ++ .irq_mask = ar2315_gpio_intr_disable, ++ .irq_unmask = ar2315_gpio_intr_enable, ++}; ++ ++static void ++ar2315_misc_intr_enable(struct irq_data *d) ++{ ++ unsigned int imr; ++ ++ imr = ar231x_read_reg(AR2315_IMR); ++ switch(d->irq) { ++ case AR531X_MISC_IRQ_SPI: ++ imr |= AR2315_ISR_SPI; ++ break; ++ case AR531X_MISC_IRQ_TIMER: ++ imr |= AR2315_ISR_TIMER; ++ break; ++ case AR531X_MISC_IRQ_AHB_PROC: ++ imr |= AR2315_ISR_AHB; ++ break; ++ case AR531X_MISC_IRQ_GPIO: ++ imr |= AR2315_ISR_GPIO; ++ break; ++ case AR531X_MISC_IRQ_UART0: ++ imr |= AR2315_ISR_UART0; ++ break; ++ case AR531X_MISC_IRQ_WATCHDOG: ++ imr |= AR2315_ISR_WD; ++ break; ++ default: ++ break; ++ } ++ ar231x_write_reg(AR2315_IMR, imr); ++} ++ ++static void ++ar2315_misc_intr_disable(struct irq_data *d) ++{ ++ unsigned int imr; ++ ++ imr = ar231x_read_reg(AR2315_IMR); ++ switch(d->irq) { ++ case AR531X_MISC_IRQ_SPI: ++ imr &= ~AR2315_ISR_SPI; ++ break; ++ case AR531X_MISC_IRQ_TIMER: ++ imr &= ~AR2315_ISR_TIMER; ++ break; ++ case AR531X_MISC_IRQ_AHB_PROC: ++ imr &= ~AR2315_ISR_AHB; ++ break; ++ case AR531X_MISC_IRQ_GPIO: ++ imr &= ~AR2315_ISR_GPIO; ++ break; ++ case AR531X_MISC_IRQ_UART0: ++ imr &= ~AR2315_ISR_UART0; ++ break; ++ case AR531X_MISC_IRQ_WATCHDOG: ++ imr &= ~AR2315_ISR_WD; ++ break; ++ default: ++ break; ++ } ++ ar231x_write_reg(AR2315_IMR, imr); ++} ++ ++ ++static struct irq_chip ar2315_misc_intr_controller = { ++ .name = "AR2315-MISC", ++ .irq_mask = ar2315_misc_intr_disable, ++ .irq_unmask = ar2315_misc_intr_enable, ++}; ++ ++static irqreturn_t ar2315_ahb_proc_handler(int cpl, void *dev_id) ++{ ++ ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET); ++ ar231x_read_reg(AR2315_AHB_ERR1); ++ ++ printk(KERN_ERR "AHB fatal error\n"); ++ machine_restart("AHB error"); /* Catastrophic failure */ ++ ++ return IRQ_HANDLED; ++} ++ ++static struct irqaction ar2315_ahb_proc_interrupt = { ++ .handler = ar2315_ahb_proc_handler, ++ .flags = IRQF_DISABLED, ++ .name = "ar2315_ahb_proc_interrupt", ++}; ++ ++static struct irqaction cascade = { ++ .handler = no_action, ++ .flags = IRQF_DISABLED, ++ .name = "cascade", ++}; ++ ++void ++ar2315_irq_init(void) ++{ ++ int i; ++ ++ if (!is_2315()) ++ return; ++ ++ ar231x_irq_dispatch = ar2315_irq_dispatch; ++ gpiointval = ar231x_read_reg(AR2315_GPIO_DI); ++ for (i = 0; i < AR531X_MISC_IRQ_COUNT; i++) { ++ int irq = AR531X_MISC_IRQ_BASE + i; ++ irq_set_chip_and_handler(irq, &ar2315_misc_intr_controller, ++ handle_level_irq); ++ } ++ for (i = 0; i < AR531X_GPIO_IRQ_COUNT; i++) { ++ int irq = AR531X_GPIO_IRQ_BASE + i; ++ irq_set_chip_and_handler(irq, &ar2315_gpio_intr_controller, ++ handle_level_irq); ++ } ++ setup_irq(AR531X_MISC_IRQ_GPIO, &cascade); ++ setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar2315_ahb_proc_interrupt); ++ setup_irq(AR2315_IRQ_MISC_INTRS, &cascade); ++} ++ ++const struct ar231x_gpiodev ar2315_gpiodev; ++ ++static u32 ++ar2315_gpio_get_output(void) ++{ ++ u32 reg; ++ reg = ar231x_read_reg(AR2315_GPIO_CR); ++ reg &= ar2315_gpiodev.valid_mask; ++ return reg; ++} ++ ++static u32 ++ar2315_gpio_set_output(u32 mask, u32 val) ++{ ++ u32 reg; ++ ++ reg = ar231x_read_reg(AR2315_GPIO_CR); ++ reg &= ~mask; ++ reg |= val; ++ ar231x_write_reg(AR2315_GPIO_CR, reg); ++ return reg; ++} ++ ++static u32 ++ar2315_gpio_get(void) ++{ ++ u32 reg; ++ reg = ar231x_read_reg(AR2315_GPIO_DI); ++ reg &= ar2315_gpiodev.valid_mask; ++ return reg; ++} ++ ++static u32 ++ar2315_gpio_set(u32 mask, u32 value) ++{ ++ u32 reg; ++ reg = ar231x_read_reg(AR2315_GPIO_DO); ++ reg &= ~mask; ++ reg |= value; ++ ar231x_write_reg(AR2315_GPIO_DO, reg); ++ return reg; ++} ++ ++const struct ar231x_gpiodev ar2315_gpiodev = { ++ .valid_mask = (1 << 22) - 1, ++ .get_output = ar2315_gpio_get_output, ++ .set_output = ar2315_gpio_set_output, ++ .get = ar2315_gpio_get, ++ .set = ar2315_gpio_set, ++}; ++ ++static struct ar231x_eth ar2315_eth_data = { ++ .reset_base = AR2315_RESET, ++ .reset_mac = AR2315_RESET_ENET0, ++ .reset_phy = AR2315_RESET_EPHY0, ++ .phy_base = KSEG1ADDR(AR2315_ENET0), ++ .config = &ar231x_board, ++}; ++ ++static struct resource ar2315_spiflash_res[] = { ++ { ++ .name = "flash_base", ++ .flags = IORESOURCE_MEM, ++ .start = KSEG1ADDR(AR2315_SPI_READ), ++ .end = KSEG1ADDR(AR2315_SPI_READ) + 0x1000000 - 1, ++ }, ++ { ++ .name = "flash_regs", ++ .flags = IORESOURCE_MEM, ++ .start = 0x11300000, ++ .end = 0x11300012, ++ }, ++}; ++ ++static struct platform_device ar2315_spiflash = { ++ .id = 0, ++ .name = "spiflash", ++ .resource = ar2315_spiflash_res, ++ .num_resources = ARRAY_SIZE(ar2315_spiflash_res) ++}; ++ ++static struct platform_device ar2315_wdt = { ++ .id = 0, ++ .name = "ar2315_wdt", ++}; ++ ++#define SPI_FLASH_CTL 0x00 ++#define SPI_FLASH_OPCODE 0x04 ++#define SPI_FLASH_DATA 0x08 ++ ++static inline u32 ++spiflash_read_reg(int reg) ++{ ++ return ar231x_read_reg(AR2315_SPI + reg); ++} ++ ++static inline void ++spiflash_write_reg(int reg, u32 data) ++{ ++ ar231x_write_reg(AR2315_SPI + reg, data); ++} ++ ++static u32 ++spiflash_wait_status(void) ++{ ++ u32 reg; ++ ++ do { ++ reg = spiflash_read_reg(SPI_FLASH_CTL); ++ } while (reg & SPI_CTL_BUSY); ++ ++ return reg; ++} ++ ++static u8 ++spiflash_probe(void) ++{ ++ u32 reg; ++ ++ reg = spiflash_wait_status(); ++ reg &= ~SPI_CTL_TX_RX_CNT_MASK; ++ reg |= (1 << 4) | 4 | SPI_CTL_START; ++ ++ spiflash_write_reg(SPI_FLASH_OPCODE, 0xab); ++ spiflash_write_reg(SPI_FLASH_CTL, reg); ++ ++ reg = spiflash_wait_status(); ++ reg = spiflash_read_reg(SPI_FLASH_DATA); ++ reg &= 0xff; ++ ++ return (u8) reg; ++} ++ ++ ++#define STM_8MBIT_SIGNATURE 0x13 ++#define STM_16MBIT_SIGNATURE 0x14 ++#define STM_32MBIT_SIGNATURE 0x15 ++#define STM_64MBIT_SIGNATURE 0x16 ++#define STM_128MBIT_SIGNATURE 0x17 ++ ++static u8 __init * ++ar2315_flash_limit(void) ++{ ++ u32 flash_size = 0; ++ ++ /* probe the flash chip size */ ++ switch(spiflash_probe()) { ++ case STM_8MBIT_SIGNATURE: ++ flash_size = 0x00100000; ++ break; ++ case STM_16MBIT_SIGNATURE: ++ flash_size = 0x00200000; ++ break; ++ case STM_32MBIT_SIGNATURE: ++ flash_size = 0x00400000; ++ break; ++ case STM_64MBIT_SIGNATURE: ++ flash_size = 0x00800000; ++ break; ++ case STM_128MBIT_SIGNATURE: ++ flash_size = 0x01000000; ++ break; ++ } ++ ++ ar2315_spiflash_res[0].end = ar2315_spiflash_res[0].start + ++ flash_size - 1; ++ return (u8 *) ar2315_spiflash_res[0].end + 1; ++} ++ ++#ifdef CONFIG_LEDS_GPIO ++static struct gpio_led ar2315_leds[6]; ++static struct gpio_led_platform_data ar2315_led_data = { ++ .leds = (void *) ar2315_leds, ++}; ++ ++static struct platform_device ar2315_gpio_leds = { ++ .name = "leds-gpio", ++ .id = -1, ++ .dev = { ++ .platform_data = (void *) &ar2315_led_data, ++ } ++}; ++ ++static void __init ++ar2315_init_gpio(void) ++{ ++ static char led_names[6][6]; ++ int i, led = 0; ++ ++ ar2315_led_data.num_leds = 0; ++ for(i = 1; i < 8; i++) ++ { ++ if((i == AR2315_RESET_GPIO) || ++ (i == ar231x_board.config->resetConfigGpio)) ++ continue; ++ ++ if(i == ar231x_board.config->sysLedGpio) ++ strcpy(led_names[led], "wlan"); ++ else ++ sprintf(led_names[led], "gpio%d", i); ++ ++ ar2315_leds[led].name = led_names[led]; ++ ar2315_leds[led].gpio = i; ++ ar2315_leds[led].active_low = 0; ++ led++; ++ } ++ ar2315_led_data.num_leds = led; ++ platform_device_register(&ar2315_gpio_leds); ++} ++#else ++static inline void ar2315_init_gpio(void) ++{ ++} ++#endif ++ ++int __init ++ar2315_init_devices(void) ++{ ++ if (!is_2315()) ++ return 0; ++ ++ /* Find board configuration */ ++ ar231x_find_config(ar2315_flash_limit()); ++ ar2315_eth_data.macaddr = ar231x_board.config->enet0_mac; ++ ++ ar2315_init_gpio(); ++ platform_device_register(&ar2315_wdt); ++ platform_device_register(&ar2315_spiflash); ++ ar231x_add_ethernet(0, KSEG1ADDR(AR2315_ENET0), AR2315_IRQ_ENET0_INTRS, ++ &ar2315_eth_data); ++ ar231x_add_wmac(0, AR2315_WLAN0, AR2315_IRQ_WLAN0_INTRS); ++ ++ return 0; ++} ++ ++static void ++ar2315_restart(char *command) ++{ ++ void (*mips_reset_vec)(void) = (void *) 0xbfc00000; ++ ++ local_irq_disable(); ++ ++ /* try reset the system via reset control */ ++ ar231x_write_reg(AR2315_COLD_RESET,AR2317_RESET_SYSTEM); ++ ++ /* Cold reset does not work on the AR2315/6, use the GPIO reset bits a workaround. ++ * give it some time to attempt a gpio based hardware reset ++ * (atheros reference design workaround) */ ++ gpio_direction_output(AR2315_RESET_GPIO, 0); ++ mdelay(100); ++ ++ /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic ++ * workaround. Attempt to jump to the mips reset location - ++ * the boot loader itself might be able to recover the system */ ++ mips_reset_vec(); ++} ++ ++ ++/* ++ * This table is indexed by bits 5..4 of the CLOCKCTL1 register ++ * to determine the predevisor value. ++ */ ++static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = { 1, 2, 4, 5 }; ++static int __initdata PLLC_DIVIDE_TABLE[5] = { 2, 3, 4, 6, 3 }; ++ ++static unsigned int __init ++ar2315_sys_clk(unsigned int clockCtl) ++{ ++ unsigned int pllcCtrl,cpuDiv; ++ unsigned int pllcOut,refdiv,fdiv,divby2; ++ unsigned int clkDiv; ++ ++ pllcCtrl = ar231x_read_reg(AR2315_PLLC_CTL); ++ refdiv = (pllcCtrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S; ++ refdiv = CLOCKCTL1_PREDIVIDE_TABLE[refdiv]; ++ fdiv = (pllcCtrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S; ++ divby2 = (pllcCtrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S; ++ divby2 += 1; ++ pllcOut = (40000000/refdiv)*(2*divby2)*fdiv; ++ ++ ++ /* clkm input selected */ ++ switch(clockCtl & CPUCLK_CLK_SEL_M) { ++ case 0: ++ case 1: ++ clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKM_DIV_M) >> PLLC_CLKM_DIV_S]; ++ break; ++ case 2: ++ clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKC_DIV_M) >> PLLC_CLKC_DIV_S]; ++ break; ++ default: ++ pllcOut = 40000000; ++ clkDiv = 1; ++ break; ++ } ++ cpuDiv = (clockCtl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S; ++ cpuDiv = cpuDiv * 2 ?: 1; ++ return (pllcOut/(clkDiv * cpuDiv)); ++} ++ ++static inline unsigned int ++ar2315_cpu_frequency(void) ++{ ++ return ar2315_sys_clk(ar231x_read_reg(AR2315_CPUCLK)); ++} ++ ++static inline unsigned int ++ar2315_apb_frequency(void) ++{ ++ return ar2315_sys_clk(ar231x_read_reg(AR2315_AMBACLK)); ++} ++ ++void __init ++ar2315_time_init(void) ++{ ++ if (!is_2315()) ++ return; ++ ++ mips_hpt_frequency = ar2315_cpu_frequency() / 2; ++} ++ ++void __init ++ar2315_prom_init(void) ++{ ++ u32 memsize, memcfg, devid; ++ ++ if (!is_2315()) ++ return; ++ ++ memcfg = ar231x_read_reg(AR2315_MEM_CFG); ++ memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S); ++ memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S); ++ memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S); ++ memsize <<= 3; ++ add_memory_region(0, memsize, BOOT_MEM_RAM); ++ ++ /* Detect the hardware based on the device ID */ ++ devid = ar231x_read_reg(AR2315_SREV) & AR2315_REV_CHIP; ++ switch(devid) { ++ case 0x90: ++ case 0x91: ++ ar231x_devtype = DEV_TYPE_AR2317; ++ break; ++ default: ++ ar231x_devtype = DEV_TYPE_AR2315; ++ break; ++ } ++ ar231x_gpiodev = &ar2315_gpiodev; ++ ar231x_board.devid = devid; ++} ++ ++void __init ++ar2315_plat_setup(void) ++{ ++ u32 config; ++ ++ if (!is_2315()) ++ return; ++ ++ /* Clear any lingering AHB errors */ ++ config = read_c0_config(); ++ write_c0_config(config & ~0x3); ++ ar231x_write_reg(AR2315_AHB_ERR0,AHB_ERROR_DET); ++ ar231x_read_reg(AR2315_AHB_ERR1); ++ ar231x_write_reg(AR2315_WDC, AR2315_WDC_IGNORE_EXPIRATION); ++ ++ _machine_restart = ar2315_restart; ++ ar231x_serial_setup(KSEG1ADDR(AR2315_UART0), ar2315_apb_frequency()); ++} +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/ar2315.h linux-2.6.39-rc7/arch/mips/ar231x/ar2315.h +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/ar2315.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/ar2315.h 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,37 @@ ++#ifndef __AR2315_H ++#define __AR2315_H ++ ++#ifdef CONFIG_ATHEROS_AR2315 ++ ++extern void ar2315_irq_init(void); ++extern int ar2315_init_devices(void); ++extern void ar2315_prom_init(void); ++extern void ar2315_plat_setup(void); ++extern void ar2315_time_init(void); ++ ++#else ++ ++static inline void ar2315_irq_init(void) ++{ ++} ++ ++static inline int ar2315_init_devices(void) ++{ ++ return 0; ++} ++ ++static inline void ar2315_prom_init(void) ++{ ++} ++ ++static inline void ar2315_plat_setup(void) ++{ ++} ++ ++static inline void ar2315_time_init(void) ++{ ++} ++ ++#endif ++ ++#endif +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/ar5312.c linux-2.6.39-rc7/arch/mips/ar231x/ar5312.c +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/ar5312.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/ar5312.c 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,538 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. ++ * Copyright (C) 2006 FON Technology, SL. ++ * Copyright (C) 2006 Imre Kaloz ++ * Copyright (C) 2006-2009 Felix Fietkau ++ */ ++ ++/* ++ * Platform devices for Atheros SoCs ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include "devices.h" ++#include "ar5312.h" ++ ++static void ++ar5312_misc_irq_dispatch(void) ++{ ++ unsigned int ar231x_misc_intrs = ar231x_read_reg(AR531X_ISR) & ar231x_read_reg(AR531X_IMR); ++ ++ if (ar231x_misc_intrs & AR531X_ISR_TIMER) { ++ do_IRQ(AR531X_MISC_IRQ_TIMER); ++ (void)ar231x_read_reg(AR531X_TIMER); ++ } else if (ar231x_misc_intrs & AR531X_ISR_AHBPROC) ++ do_IRQ(AR531X_MISC_IRQ_AHB_PROC); ++ else if ((ar231x_misc_intrs & AR531X_ISR_UART0)) ++ do_IRQ(AR531X_MISC_IRQ_UART0); ++ else if (ar231x_misc_intrs & AR531X_ISR_WD) ++ do_IRQ(AR531X_MISC_IRQ_WATCHDOG); ++ else ++ do_IRQ(AR531X_MISC_IRQ_NONE); ++} ++ ++static asmlinkage void ++ar5312_irq_dispatch(void) ++{ ++ int pending = read_c0_status() & read_c0_cause(); ++ ++ if (pending & CAUSEF_IP2) ++ do_IRQ(AR5312_IRQ_WLAN0_INTRS); ++ else if (pending & CAUSEF_IP3) ++ do_IRQ(AR5312_IRQ_ENET0_INTRS); ++ else if (pending & CAUSEF_IP4) ++ do_IRQ(AR5312_IRQ_ENET1_INTRS); ++ else if (pending & CAUSEF_IP5) ++ do_IRQ(AR5312_IRQ_WLAN1_INTRS); ++ else if (pending & CAUSEF_IP6) ++ ar5312_misc_irq_dispatch(); ++ else if (pending & CAUSEF_IP7) ++ do_IRQ(AR531X_IRQ_CPU_CLOCK); ++} ++ ++ ++/* Enable the specified AR531X_MISC_IRQ interrupt */ ++static void ++ar5312_misc_intr_enable(struct irq_data *d) ++{ ++ unsigned int imr; ++ ++ imr = ar231x_read_reg(AR531X_IMR); ++ imr |= (1 << (d->irq - AR531X_MISC_IRQ_BASE - 1)); ++ ar231x_write_reg(AR531X_IMR, imr); ++} ++ ++/* Disable the specified AR531X_MISC_IRQ interrupt */ ++static void ++ar5312_misc_intr_disable(struct irq_data *d) ++{ ++ unsigned int imr; ++ ++ imr = ar231x_read_reg(AR531X_IMR); ++ imr &= ~(1 << (d->irq - AR531X_MISC_IRQ_BASE - 1)); ++ ar231x_write_reg(AR531X_IMR, imr); ++ ar231x_read_reg(AR531X_IMR); /* flush write buffer */ ++} ++ ++static struct irq_chip ar5312_misc_intr_controller = { ++ .name = "AR5312-MISC", ++ .irq_mask = ar5312_misc_intr_disable, ++ .irq_unmask = ar5312_misc_intr_enable, ++}; ++ ++ ++static irqreturn_t ar5312_ahb_proc_handler(int cpl, void *dev_id) ++{ ++ u32 proc1 = ar231x_read_reg(AR531X_PROC1); ++ u32 procAddr = ar231x_read_reg(AR531X_PROCADDR); /* clears error state */ ++ u32 dma1 = ar231x_read_reg(AR531X_DMA1); ++ u32 dmaAddr = ar231x_read_reg(AR531X_DMAADDR); /* clears error state */ ++ ++ printk("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n", ++ procAddr, proc1, dmaAddr, dma1); ++ ++ machine_restart("AHB error"); /* Catastrophic failure */ ++ return IRQ_HANDLED; ++} ++ ++ ++static struct irqaction ar5312_ahb_proc_interrupt = { ++ .handler = ar5312_ahb_proc_handler, ++ .flags = IRQF_DISABLED, ++ .name = "ar5312_ahb_proc_interrupt", ++}; ++ ++ ++static struct irqaction cascade = { ++ .handler = no_action, ++ .flags = IRQF_DISABLED, ++ .name = "cascade", ++}; ++ ++void __init ar5312_irq_init(void) ++{ ++ int i; ++ ++ if (!is_5312()) ++ return; ++ ++ ar231x_irq_dispatch = ar5312_irq_dispatch; ++ for (i = 0; i < AR531X_MISC_IRQ_COUNT; i++) { ++ int irq = AR531X_MISC_IRQ_BASE + i; ++ irq_set_chip_and_handler(irq, &ar5312_misc_intr_controller, ++ handle_level_irq); ++ } ++ setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt); ++ setup_irq(AR5312_IRQ_MISC_INTRS, &cascade); ++} ++ ++const struct ar231x_gpiodev ar5312_gpiodev; ++ ++static u32 ++ar5312_gpio_get_output(void) ++{ ++ u32 reg; ++ reg = ~(ar231x_read_reg(AR531X_GPIO_CR)); ++ reg &= ar5312_gpiodev.valid_mask; ++ return reg; ++} ++ ++static u32 ++ar5312_gpio_set_output(u32 mask, u32 val) ++{ ++ u32 reg; ++ ++ reg = ar231x_read_reg(AR531X_GPIO_CR); ++ reg |= mask; ++ reg &= ~val; ++ ar231x_write_reg(AR531X_GPIO_CR, reg); ++ return reg; ++} ++ ++static u32 ++ar5312_gpio_get(void) ++{ ++ u32 reg; ++ reg = ar231x_read_reg(AR531X_GPIO_DI); ++ reg &= ar5312_gpiodev.valid_mask; ++ return reg; ++} ++ ++static u32 ++ar5312_gpio_set(u32 mask, u32 value) ++{ ++ u32 reg; ++ reg = ar231x_read_reg(AR531X_GPIO_DO); ++ reg &= ~mask; ++ reg |= value; ++ ar231x_write_reg(AR531X_GPIO_DO, reg); ++ return reg; ++} ++ ++const struct ar231x_gpiodev ar5312_gpiodev = { ++ .valid_mask = (1 << 8) - 1, ++ .get_output = ar5312_gpio_get_output, ++ .set_output = ar5312_gpio_set_output, ++ .get = ar5312_gpio_get, ++ .set = ar5312_gpio_set, ++}; ++ ++static struct physmap_flash_data ar5312_flash_data = { ++ .width = 2, ++}; ++ ++static struct resource ar5312_flash_resource = { ++ .start = AR531X_FLASH, ++ .end = AR531X_FLASH + 0x800000 - 1, ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct ar231x_eth ar5312_eth0_data = { ++ .reset_base = AR531X_RESET, ++ .reset_mac = AR531X_RESET_ENET0, ++ .reset_phy = AR531X_RESET_EPHY0, ++ .phy_base = KSEG1ADDR(AR531X_ENET0), ++ .config = &ar231x_board, ++}; ++ ++static struct ar231x_eth ar5312_eth1_data = { ++ .reset_base = AR531X_RESET, ++ .reset_mac = AR531X_RESET_ENET1, ++ .reset_phy = AR531X_RESET_EPHY1, ++ .phy_base = KSEG1ADDR(AR531X_ENET1), ++ .config = &ar231x_board, ++}; ++ ++static struct platform_device ar5312_physmap_flash = { ++ .name = "physmap-flash", ++ .id = 0, ++ .dev.platform_data = &ar5312_flash_data, ++ .resource = &ar5312_flash_resource, ++ .num_resources = 1, ++}; ++ ++#ifdef CONFIG_LEDS_GPIO ++static struct gpio_led ar5312_leds[] = { ++ { .name = "wlan", .gpio = 0, .active_low = 1, }, ++}; ++ ++static const struct gpio_led_platform_data ar5312_led_data = { ++ .num_leds = ARRAY_SIZE(ar5312_leds), ++ .leds = (void *) ar5312_leds, ++}; ++ ++static struct platform_device ar5312_gpio_leds = { ++ .name = "leds-gpio", ++ .id = -1, ++ .dev.platform_data = (void *) &ar5312_led_data, ++}; ++#endif ++ ++/* ++ * NB: This mapping size is larger than the actual flash size, ++ * but this shouldn't be a problem here, because the flash ++ * will simply be mapped multiple times. ++ */ ++static char __init *ar5312_flash_limit(void) ++{ ++ u32 ctl; ++ /* ++ * Configure flash bank 0. ++ * Assume 8M window size. Flash will be aliased if it's smaller ++ */ ++ ctl = FLASHCTL_E | ++ FLASHCTL_AC_8M | ++ FLASHCTL_RBLE | ++ (0x01 << FLASHCTL_IDCY_S) | ++ (0x07 << FLASHCTL_WST1_S) | ++ (0x07 << FLASHCTL_WST2_S) | ++ (ar231x_read_reg(AR531X_FLASHCTL0) & FLASHCTL_MW); ++ ++ ar231x_write_reg(AR531X_FLASHCTL0, ctl); ++ ++ /* Disable other flash banks */ ++ ar231x_write_reg(AR531X_FLASHCTL1, ++ ar231x_read_reg(AR531X_FLASHCTL1) & ~(FLASHCTL_E | FLASHCTL_AC)); ++ ++ ar231x_write_reg(AR531X_FLASHCTL2, ++ ar231x_read_reg(AR531X_FLASHCTL2) & ~(FLASHCTL_E | FLASHCTL_AC)); ++ ++ return (char *) KSEG1ADDR(AR531X_FLASH + 0x800000); ++} ++ ++int __init ar5312_init_devices(void) ++{ ++ struct ar231x_boarddata *config; ++ u32 fctl = 0; ++ const u8 *radio; ++ u8 *c; ++ ++ if (!is_5312()) ++ return 0; ++ ++ /* Locate board/radio config data */ ++ ar231x_find_config(ar5312_flash_limit()); ++ config = ar231x_board.config; ++ ++ ++ /* ++ * Chip IDs and hardware detection for some Atheros ++ * models are really broken! ++ * ++ * Atheros uses a disabled WMAC0 and Silicon ID of AR5312 ++ * as indication for AR2312, which is otherwise ++ * indistinguishable from the real AR5312. ++ */ ++ if (ar231x_board.radio) { ++ radio = ar231x_board.radio + AR531X_RADIO_MASK_OFF; ++ if ((*((const u32 *) radio) & AR531X_RADIO0_MASK) == 0) ++ config->flags |= BD_ISCASPER; ++ } else ++ radio = NULL; ++ ++ /* AR2313 has CPU minor rev. 10 */ ++ if ((current_cpu_data.processor_id & 0xff) == 0x0a) ++ ar231x_devtype = DEV_TYPE_AR2313; ++ ++ /* AR2312 shares the same Silicon ID as AR5312 */ ++ else if (config->flags & BD_ISCASPER) ++ ar231x_devtype = DEV_TYPE_AR2312; ++ ++ /* Everything else is probably AR5312 or compatible */ ++ else ++ ar231x_devtype = DEV_TYPE_AR5312; ++ ++ /* fixup flash width */ ++ fctl = ar231x_read_reg(AR531X_FLASHCTL) & FLASHCTL_MW; ++ switch (fctl) { ++ case FLASHCTL_MWx16: ++ ar5312_flash_data.width = 2; ++ break; ++ case FLASHCTL_MWx8: ++ default: ++ ar5312_flash_data.width = 1; ++ break; ++ } ++ ++ platform_device_register(&ar5312_physmap_flash); ++ ++#ifdef CONFIG_LEDS_GPIO ++ ar5312_leds[0].gpio = config->sysLedGpio; ++ platform_device_register(&ar5312_gpio_leds); ++#endif ++ ++ /* Fix up MAC addresses if necessary */ ++ if (!memcmp(config->enet0_mac, "\xff\xff\xff\xff\xff\xff", 6)) ++ memcpy(config->enet0_mac, config->enet1_mac, 6); ++ ++ /* If ENET0 and ENET1 have the same mac address, ++ * increment the one from ENET1 */ ++ if (memcmp(config->enet0_mac, config->enet1_mac, 6) == 0) { ++ c = config->enet1_mac + 5; ++ while ((c >= config->enet1_mac) && !(++(*c))) ++ c--; ++ } ++ ++ switch(ar231x_devtype) { ++ case DEV_TYPE_AR5312: ++ ar5312_eth0_data.macaddr = config->enet0_mac; ++ ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET0), ++ AR5312_IRQ_ENET0_INTRS, &ar5312_eth0_data); ++ ++ ar5312_eth1_data.macaddr = config->enet1_mac; ++ ar231x_add_ethernet(1, KSEG1ADDR(AR531X_ENET1), ++ AR5312_IRQ_ENET1_INTRS, &ar5312_eth1_data); ++ ++ if (!ar231x_board.radio) ++ return 0; ++ ++ if ((*((u32 *) radio) & AR531X_RADIO0_MASK) && ++ (config->flags & BD_WLAN0)) ++ ar231x_add_wmac(0, AR531X_WLAN0, ++ AR5312_IRQ_WLAN0_INTRS); ++ ++ break; ++ /* ++ * AR2312/3 ethernet uses the PHY of ENET0, but the MAC ++ * of ENET1. Atheros calls it 'twisted' for a reason :) ++ */ ++ case DEV_TYPE_AR2312: ++ case DEV_TYPE_AR2313: ++ ar5312_eth1_data.phy_base = ar5312_eth0_data.phy_base; ++ ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy; ++ ar5312_eth1_data.macaddr = config->enet0_mac; ++ ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET1), ++ AR5312_IRQ_ENET1_INTRS, &ar5312_eth1_data); ++ ++ if (!ar231x_board.radio) ++ return 0; ++ break; ++ default: ++ break; ++ } ++ ++ if ((*((u32 *) radio) & AR531X_RADIO1_MASK) && ++ (config->flags & BD_WLAN1)) ++ ar231x_add_wmac(1, AR531X_WLAN1, ++ AR5312_IRQ_WLAN1_INTRS); ++ ++ return 0; ++} ++ ++ ++static void ar5312_restart(char *command) ++{ ++ /* reset the system */ ++ local_irq_disable(); ++ while(1) { ++ ar231x_write_reg(AR531X_RESET, AR531X_RESET_SYSTEM); ++ } ++} ++ ++ ++/* ++ * This table is indexed by bits 5..4 of the CLOCKCTL1 register ++ * to determine the predevisor value. ++ */ ++static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = { 1, 2, 4, 5 }; ++ ++ ++static int __init ++ar5312_cpu_frequency(void) ++{ ++ unsigned int result; ++ unsigned int predivide_mask, predivide_shift; ++ unsigned int multiplier_mask, multiplier_shift; ++ unsigned int clockCtl1, preDivideSelect, preDivisor, multiplier; ++ unsigned int doubler_mask; ++ u16 devid; ++ ++ /* Trust the bootrom's idea of cpu frequency. */ ++ if ((result = ar231x_read_reg(AR5312_SCRATCH))) ++ return result; ++ ++ devid = ar231x_read_reg(AR531X_REV); ++ devid &= AR531X_REV_MAJ; ++ devid >>= AR531X_REV_MAJ_S; ++ if (devid == AR531X_REV_MAJ_AR2313) { ++ predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK; ++ predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT; ++ multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK; ++ multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT; ++ doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK; ++ } else { /* AR5312 and AR2312 */ ++ predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK; ++ predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT; ++ multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK; ++ multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT; ++ doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK; ++ } ++ ++ /* ++ * Clocking is derived from a fixed 40MHz input clock. ++ * ++ * cpuFreq = InputClock * MULT (where MULT is PLL multiplier) ++ * sysFreq = cpuFreq / 4 (used for APB clock, serial, ++ * flash, Timer, Watchdog Timer) ++ * ++ * cntFreq = cpuFreq / 2 (use for CPU count/compare) ++ * ++ * So, for example, with a PLL multiplier of 5, we have ++ * ++ * cpuFreq = 200MHz ++ * sysFreq = 50MHz ++ * cntFreq = 100MHz ++ * ++ * We compute the CPU frequency, based on PLL settings. ++ */ ++ ++ clockCtl1 = ar231x_read_reg(AR5312_CLOCKCTL1); ++ preDivideSelect = (clockCtl1 & predivide_mask) >> predivide_shift; ++ preDivisor = CLOCKCTL1_PREDIVIDE_TABLE[preDivideSelect]; ++ multiplier = (clockCtl1 & multiplier_mask) >> multiplier_shift; ++ ++ if (clockCtl1 & doubler_mask) { ++ multiplier = multiplier << 1; ++ } ++ return (40000000 / preDivisor) * multiplier; ++} ++ ++static inline int ++ar5312_sys_frequency(void) ++{ ++ return ar5312_cpu_frequency() / 4; ++} ++ ++void __init ++ar5312_time_init(void) ++{ ++ if (!is_5312()) ++ return; ++ ++ mips_hpt_frequency = ar5312_cpu_frequency() / 2; ++} ++ ++ ++void __init ++ar5312_prom_init(void) ++{ ++ u32 memsize, memcfg, bank0AC, bank1AC; ++ u32 devid; ++ ++ if (!is_5312()) ++ return; ++ ++ /* Detect memory size */ ++ memcfg = ar231x_read_reg(AR531X_MEM_CFG1); ++ bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S; ++ bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S; ++ memsize = (bank0AC ? (1 << (bank0AC+1)) : 0) ++ + (bank1AC ? (1 << (bank1AC+1)) : 0); ++ memsize <<= 20; ++ add_memory_region(0, memsize, BOOT_MEM_RAM); ++ ++ devid = ar231x_read_reg(AR531X_REV); ++ devid >>= AR531X_REV_WMAC_MIN_S; ++ devid &= AR531X_REV_CHIP; ++ ar231x_board.devid = (u16) devid; ++ ar231x_gpiodev = &ar5312_gpiodev; ++} ++ ++void __init ++ar5312_plat_setup(void) ++{ ++ if (!is_5312()) ++ return; ++ ++ /* Clear any lingering AHB errors */ ++ ar231x_read_reg(AR531X_PROCADDR); ++ ar231x_read_reg(AR531X_DMAADDR); ++ ar231x_write_reg(AR531X_WD_CTRL, AR531X_WD_CTRL_IGNORE_EXPIRATION); ++ ++ _machine_restart = ar5312_restart; ++ ar231x_serial_setup(KSEG1ADDR(AR531X_UART0), ar5312_sys_frequency()); ++} ++ +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/ar5312.h linux-2.6.39-rc7/arch/mips/ar231x/ar5312.h +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/ar5312.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/ar5312.h 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,38 @@ ++#ifndef __AR5312_H ++#define __AR5312_H ++ ++#ifdef CONFIG_ATHEROS_AR5312 ++ ++extern void ar5312_irq_init(void); ++extern int ar5312_init_devices(void); ++extern void ar5312_prom_init(void); ++extern void ar5312_plat_setup(void); ++extern void ar5312_time_init(void); ++extern void ar5312_time_init(void); ++ ++#else ++ ++static inline void ar5312_irq_init(void) ++{ ++} ++ ++static inline int ar5312_init_devices(void) ++{ ++ return 0; ++} ++ ++static inline void ar5312_prom_init(void) ++{ ++} ++ ++static inline void ar5312_plat_setup(void) ++{ ++} ++ ++static inline void ar5312_time_init(void) ++{ ++} ++ ++#endif ++ ++#endif +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/board.c linux-2.6.39-rc7/arch/mips/ar231x/board.c +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/board.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/board.c 2011-05-15 22:16:11.000000000 +0200 +@@ -0,0 +1,261 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. ++ * Copyright (C) 2006 FON Technology, SL. ++ * Copyright (C) 2006 Imre Kaloz ++ * Copyright (C) 2006-2009 Felix Fietkau ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include "devices.h" ++#include "ar5312.h" ++#include "ar2315.h" ++ ++void (*ar231x_irq_dispatch)(void); ++ ++static inline bool ++check_radio_magic(u8 *addr) ++{ ++ addr += 0x7a; /* offset for flash magic */ ++ if ((addr[0] == 0x5a) && (addr[1] == 0xa5)) { ++ return 1; ++ } ++ return 0; ++} ++ ++static inline bool ++check_board_data(u8 *flash_limit, u8 *addr, bool broken) ++{ ++ /* config magic found */ ++ if (*((u32 *)addr) == AR531X_BD_MAGIC) ++ return 1; ++ ++ if (!broken) ++ return 0; ++ ++ if (check_radio_magic(addr + 0xf8)) ++ ar231x_board.radio = addr + 0xf8; ++ if ((addr < flash_limit + 0x10000) && ++ check_radio_magic(addr + 0x10000)) ++ ar231x_board.radio = addr + 0x10000; ++ ++ if (ar231x_board.radio) { ++ /* broken board data detected, use radio data to find the offset, ++ * user will fix this */ ++ return 1; ++ } ++ return 0; ++} ++ ++static u8 * ++find_board_config(u8 *flash_limit, bool broken) ++{ ++ u8 *addr; ++ int found = 0; ++ ++ for (addr = flash_limit - 0x1000; ++ addr >= flash_limit - 0x30000; ++ addr -= 0x1000) { ++ ++ if (check_board_data(flash_limit, addr, broken)) { ++ found = 1; ++ break; ++ } ++ } ++ ++ if (!found) ++ addr = NULL; ++ ++ return addr; ++} ++ ++static u8 * ++find_radio_config(u8 *flash_limit, u8 *board_config) ++{ ++ int found; ++ u8 *radio_config; ++ ++ /* ++ * Now find the start of Radio Configuration data, using heuristics: ++ * Search forward from Board Configuration data by 0x1000 bytes ++ * at a time until we find non-0xffffffff. ++ */ ++ found = 0; ++ for (radio_config = board_config + 0x1000; ++ (radio_config < flash_limit); ++ radio_config += 0x1000) { ++ if ((*(u32 *)radio_config != 0xffffffff) && ++ check_radio_magic(radio_config)) { ++ found = 1; ++ break; ++ } ++ } ++ ++ /* AR2316 relocates radio config to new location */ ++ if (!found) { ++ for (radio_config = board_config + 0xf8; ++ (radio_config < flash_limit - 0x1000 + 0xf8); ++ radio_config += 0x1000) { ++ if ((*(u32 *)radio_config != 0xffffffff) && ++ check_radio_magic(radio_config)) { ++ found = 1; ++ break; ++ } ++ } ++ } ++ ++ if (!found) { ++ printk("Could not find Radio Configuration data\n"); ++ radio_config = 0; ++ } ++ ++ return (u8 *) radio_config; ++} ++ ++int __init ++ar231x_find_config(u8 *flash_limit) ++{ ++ struct ar231x_boarddata *config; ++ unsigned int rcfg_size; ++ int broken_boarddata = 0, i, tmp; ++ u8 *bcfg, *rcfg; ++ u8 *board_data; ++ u8 *radio_data; ++ u32 offset; ++ ++ ar231x_board.config = NULL; ++ ar231x_board.radio = NULL; ++ /* Copy the board and radio data to RAM, because accessing the mapped ++ * memory of the flash directly after booting is not safe */ ++ ++ /* Try to find valid board and radio data */ ++ bcfg = find_board_config(flash_limit, false); ++ ++ /* If that fails, try to at least find valid radio data */ ++ if (!bcfg) { ++ bcfg = find_board_config(flash_limit, true); ++ broken_boarddata = 1; ++ } ++ ++ if (!bcfg) { ++ printk(KERN_WARNING "WARNING: No board configuration data found!\n"); ++ return -ENODEV; ++ } ++ ++ board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL); ++ ar231x_board.config = (struct ar231x_boarddata *) board_data; ++ memcpy(board_data, bcfg, 0x100); ++ if (broken_boarddata) { ++ printk(KERN_WARNING "WARNING: broken board data detected\n"); ++ config = ar231x_board.config; ++ if (!memcmp(config->enet0_mac, "\x00\x00\x00\x00\x00\x00", 6)) { ++ printk(KERN_INFO "Fixing up empty mac addresses\n"); ++ config->resetConfigGpio = 0xffff; ++ config->sysLedGpio = 0xffff; ++ random_ether_addr(config->wlan0_mac); ++ config->wlan0_mac[0] &= ~0x06; ++ random_ether_addr(config->enet0_mac); ++ random_ether_addr(config->enet1_mac); ++ } ++ } ++ ++ ++ /* Radio config starts 0x100 bytes after board config, regardless ++ * of what the physical layout on the flash chip looks like */ ++ ++ if (ar231x_board.radio) ++ rcfg = (u8 *) ar231x_board.radio; ++ else ++ rcfg = find_radio_config(flash_limit, bcfg); ++ ++ if (!rcfg) ++ return -ENODEV; ++ ++ radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff); ++ ar231x_board.radio = radio_data; ++ offset = radio_data - board_data; ++ printk(KERN_INFO "Radio config found at offset 0x%x(0x%x)\n", rcfg - bcfg, offset); ++ rcfg_size = BOARD_CONFIG_BUFSZ - offset; ++ memcpy(radio_data, rcfg, rcfg_size); ++ ++ for (tmp = 0xff, i = 0; i < ETH_ALEN; i++) ++ tmp &= radio_data[i + 0x1d * 2]; ++ if (tmp == 0xff) { ++ u16 *eep = (u16 *)radio_data, *bcfgs = (u16 *)bcfg; ++ printk(KERN_INFO "Radio MAC is blank; using board-data\n"); ++ eep[0x1f] = bcfgs[0x30]; ++ eep[0x1e] = bcfgs[0x34]; ++ eep[0x1d] = bcfgs[0x32]; ++ } ++ ++ return 0; ++} ++ ++static void ++ar231x_halt(void) ++{ ++ local_irq_disable(); ++ while (1); ++} ++ ++void __init ++plat_mem_setup(void) ++{ ++ _machine_halt = ar231x_halt; ++ pm_power_off = ar231x_halt; ++ ++ ar5312_plat_setup(); ++ ar2315_plat_setup(); ++ ++ /* Disable data watchpoints */ ++ write_c0_watchlo0(0); ++} ++ ++ ++asmlinkage void ++plat_irq_dispatch(void) ++{ ++ ar231x_irq_dispatch(); ++} ++ ++void __init ++plat_time_init(void) ++{ ++ ar5312_time_init(); ++ ar2315_time_init(); ++} ++ ++unsigned int __cpuinit ++get_c0_compare_int(void) ++{ ++ return CP0_LEGACY_COMPARE_IRQ; ++} ++ ++void __init ++arch_init_irq(void) ++{ ++ clear_c0_status(ST0_IM); ++ mips_cpu_irq_init(); ++ ++ /* Initialize interrupt controllers */ ++ ar5312_irq_init(); ++ ar2315_irq_init(); ++} ++ ++ +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/devices.c linux-2.6.39-rc7/arch/mips/ar231x/devices.c +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/devices.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/devices.c 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,175 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "devices.h" ++#include "ar5312.h" ++#include "ar2315.h" ++ ++struct ar231x_board_config ar231x_board; ++int ar231x_devtype = DEV_TYPE_UNKNOWN; ++const struct ar231x_gpiodev *ar231x_gpiodev; ++EXPORT_SYMBOL(ar231x_gpiodev); ++ ++static struct resource ar231x_eth0_res[] = { ++ { ++ .name = "eth0_membase", ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = "eth0_irq", ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static struct resource ar231x_eth1_res[] = { ++ { ++ .name = "eth1_membase", ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = "eth1_irq", ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static struct platform_device ar231x_eth[] = { ++ { ++ .id = 0, ++ .name = "ar231x-eth", ++ .resource = ar231x_eth0_res, ++ .num_resources = ARRAY_SIZE(ar231x_eth0_res) ++ }, ++ { ++ .id = 1, ++ .name = "ar231x-eth", ++ .resource = ar231x_eth1_res, ++ .num_resources = ARRAY_SIZE(ar231x_eth1_res) ++ } ++}; ++ ++static struct resource ar231x_wmac0_res[] = { ++ { ++ .name = "wmac0_membase", ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = "wmac0_irq", ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static struct resource ar231x_wmac1_res[] = { ++ { ++ .name = "wmac1_membase", ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = "wmac1_irq", ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++ ++static struct platform_device ar231x_wmac[] = { ++ { ++ .id = 0, ++ .name = "ar231x-wmac", ++ .resource = ar231x_wmac0_res, ++ .num_resources = ARRAY_SIZE(ar231x_wmac0_res), ++ .dev.platform_data = &ar231x_board, ++ }, ++ { ++ .id = 1, ++ .name = "ar231x-wmac", ++ .resource = ar231x_wmac1_res, ++ .num_resources = ARRAY_SIZE(ar231x_wmac1_res), ++ .dev.platform_data = &ar231x_board, ++ }, ++}; ++ ++static const char *devtype_strings[] = { ++ [DEV_TYPE_AR5312] = "Atheros AR5312", ++ [DEV_TYPE_AR2312] = "Atheros AR2312", ++ [DEV_TYPE_AR2313] = "Atheros AR2313", ++ [DEV_TYPE_AR2315] = "Atheros AR2315", ++ [DEV_TYPE_AR2316] = "Atheros AR2316", ++ [DEV_TYPE_AR2317] = "Atheros AR2317", ++ [DEV_TYPE_UNKNOWN] = "Atheros (unknown)", ++}; ++ ++const char *get_system_type(void) ++{ ++ if ((ar231x_devtype >= ARRAY_SIZE(devtype_strings)) || ++ !devtype_strings[ar231x_devtype]) ++ return devtype_strings[DEV_TYPE_UNKNOWN]; ++ return devtype_strings[ar231x_devtype]; ++} ++ ++ ++int __init ++ar231x_add_ethernet(int nr, u32 base, int irq, void *pdata) ++{ ++ struct resource *res; ++ ++ ar231x_eth[nr].dev.platform_data = pdata; ++ res = &ar231x_eth[nr].resource[0]; ++ res->start = base; ++ res->end = base + 0x2000 - 1; ++ res++; ++ res->start = irq; ++ res->end = irq; ++ return platform_device_register(&ar231x_eth[nr]); ++} ++ ++void __init ++ar231x_serial_setup(u32 mapbase, unsigned int uartclk) ++{ ++ struct uart_port s; ++ ++ memset(&s, 0, sizeof(s)); ++ ++ s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST; ++ s.iotype = UPIO_MEM; ++ s.irq = AR531X_MISC_IRQ_UART0; ++ s.regshift = 2; ++ s.mapbase = mapbase; ++ s.uartclk = uartclk; ++ s.membase = (void __iomem *)s.mapbase; ++ ++ early_serial_setup(&s); ++} ++ ++int __init ++ar231x_add_wmac(int nr, u32 base, int irq) ++{ ++ struct resource *res; ++ ++ ar231x_wmac[nr].dev.platform_data = &ar231x_board; ++ res = &ar231x_wmac[nr].resource[0]; ++ res->start = base; ++ res->end = base + 0x10000 - 1; ++ res++; ++ res->start = irq; ++ res->end = irq; ++ return platform_device_register(&ar231x_wmac[nr]); ++} ++ ++static int __init ar231x_register_devices(void) ++{ ++ static struct resource res = { ++ .start = 0xFFFFFFFF, ++ }; ++ ++ platform_device_register_simple("GPIODEV", 0, &res, 1); ++ ar5312_init_devices(); ++ ar2315_init_devices(); ++ ++ return 0; ++} ++ ++device_initcall(ar231x_register_devices); +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/devices.h linux-2.6.39-rc7/arch/mips/ar231x/devices.h +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/devices.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/devices.h 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,37 @@ ++#ifndef __AR231X_DEVICES_H ++#define __AR231X_DEVICES_H ++ ++enum { ++ /* handled by ar5312.c */ ++ DEV_TYPE_AR2312, ++ DEV_TYPE_AR2313, ++ DEV_TYPE_AR5312, ++ ++ /* handled by ar2315.c */ ++ DEV_TYPE_AR2315, ++ DEV_TYPE_AR2316, ++ DEV_TYPE_AR2317, ++ ++ DEV_TYPE_UNKNOWN ++}; ++ ++extern int ar231x_devtype; ++extern struct ar231x_board_config ar231x_board; ++extern asmlinkage void (*ar231x_irq_dispatch)(void); ++ ++extern int ar231x_find_config(u8 *flash_limit); ++extern void ar231x_serial_setup(u32 mapbase, unsigned int uartclk); ++extern int ar231x_add_wmac(int nr, u32 base, int irq); ++extern int ar231x_add_ethernet(int nr, u32 base, int irq, void *pdata); ++ ++static inline bool is_2315(void) ++{ ++ return (current_cpu_data.cputype == CPU_4KEC); ++} ++ ++static inline bool is_5312(void) ++{ ++ return !is_2315(); ++} ++ ++#endif +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/early_printk.c linux-2.6.39-rc7/arch/mips/ar231x/early_printk.c +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/early_printk.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/early_printk.c 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,44 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2010 Gabor Juhos ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include "devices.h" ++ ++static inline void prom_uart_wr(void __iomem *base, unsigned reg, ++ unsigned char ch) ++{ ++ __raw_writeb(ch, base + 4 * reg); ++} ++ ++static inline unsigned char prom_uart_rr(void __iomem *base, unsigned reg) ++{ ++ return __raw_readb(base + 4 * reg); ++} ++ ++void prom_putchar(unsigned char ch) ++{ ++ static void __iomem *base; ++ ++ if (unlikely(base == NULL)) { ++ if (is_2315()) ++ base = (void __iomem *)(KSEG1ADDR(AR2315_UART0)); ++ else ++ base = (void __iomem *)(KSEG1ADDR(AR531X_UART0)); ++ } ++ ++ while ((prom_uart_rr(base, UART_LSR) & UART_LSR_THRE) == 0); ++ prom_uart_wr(base, UART_TX, ch); ++ while ((prom_uart_rr(base, UART_LSR) & UART_LSR_THRE) == 0); ++} ++ +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/pci.c linux-2.6.39-rc7/arch/mips/ar231x/pci.c +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/pci.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/pci.c 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,230 @@ ++/* ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "devices.h" ++ ++#define AR531X_MEM_BASE 0x80800000UL ++#define AR531X_MEM_SIZE 0x00ffffffUL ++#define AR531X_IO_SIZE 0x00007fffUL ++ ++static unsigned long configspace; ++ ++static int config_access(int devfn, int where, int size, u32 *ptr, bool write) ++{ ++ unsigned long flags; ++ int func = PCI_FUNC(devfn); ++ int dev = PCI_SLOT(devfn); ++ u32 value = 0; ++ int err = 0; ++ u32 addr; ++ ++ if (((dev != 0) && (dev != 3)) || (func > 2)) ++ return PCIBIOS_DEVICE_NOT_FOUND; ++ ++ /* Select Configuration access */ ++ local_irq_save(flags); ++ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, 0, AR2315_PCIMISC_CFG_SEL); ++ mb(); ++ ++ addr = (u32) configspace + (1 << (13 + dev)) + (func << 8) + where; ++ if (size == 1) ++ addr ^= 0x3; ++ else if (size == 2) ++ addr ^= 0x2; ++ ++ if (write) { ++ value = *ptr; ++ if (size == 1) ++ err = put_dbe(value, (u8 *) addr); ++ else if (size == 2) ++ err = put_dbe(value, (u16 *) addr); ++ else if (size == 4) ++ err = put_dbe(value, (u32 *) addr); ++ } else { ++ if (size == 1) ++ err = get_dbe(value, (u8 *) addr); ++ else if (size == 2) ++ err = get_dbe(value, (u16 *) addr); ++ else if (size == 4) ++ err = get_dbe(value, (u32 *) addr); ++ if (err) ++ *ptr = 0xffffffff; ++ else ++ *ptr = value; ++ } ++ ++ /* Select Memory access */ ++ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_CFG_SEL, 0); ++ local_irq_restore(flags); ++ ++ return (err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL); ++} ++ ++static int ar231x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * value) ++{ ++ return config_access(devfn, where, size, value, 0); ++} ++ ++static int ar231x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value) ++{ ++ return config_access(devfn, where, size, &value, 1); ++} ++ ++struct pci_ops ar231x_pci_ops = { ++ .read = ar231x_pci_read, ++ .write = ar231x_pci_write, ++}; ++ ++static struct resource ar231x_mem_resource = { ++ .name = "AR531x PCI MEM", ++ .start = AR531X_MEM_BASE, ++ .end = AR531X_MEM_BASE + AR531X_MEM_SIZE - AR531X_IO_SIZE - 1 + 0x4000000, ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct resource ar231x_io_resource = { ++ .name = "AR531x PCI I/O", ++ .start = AR531X_MEM_BASE + AR531X_MEM_SIZE - AR531X_IO_SIZE, ++ .end = AR531X_MEM_BASE + AR531X_MEM_SIZE - 1, ++ .flags = IORESOURCE_IO, ++}; ++ ++struct pci_controller ar231x_pci_controller = { ++ .pci_ops = &ar231x_pci_ops, ++ .mem_resource = &ar231x_mem_resource, ++ .io_resource = &ar231x_io_resource, ++ .mem_offset = 0x00000000UL, ++ .io_offset = 0x00000000UL, ++}; ++ ++int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) ++{ ++ return AR2315_IRQ_LCBUS_PCI; ++} ++ ++int pcibios_plat_dev_init(struct pci_dev *dev) ++{ ++ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 5); ++ pci_write_config_word(dev, 0x40, 0); ++ ++ /* Clear any pending Abort or external Interrupts ++ * and enable interrupt processing */ ++ ar231x_mask_reg(AR2315_PCI_INTEN_REG, AR2315_PCI_INT_ENABLE, 0); ++ ar231x_write_reg(AR2315_PCI_INT_STATUS, (AR2315_PCI_ABORT_INT | AR2315_PCI_EXT_INT)); ++ ar231x_write_reg(AR2315_PCI_INT_MASK, (AR2315_PCI_ABORT_INT | AR2315_PCI_EXT_INT)); ++ ar231x_mask_reg(AR2315_PCI_INTEN_REG, 0, AR2315_PCI_INT_ENABLE); ++ ++ return 0; ++} ++ ++static void ++ar2315_pci_fixup(struct pci_dev *dev) ++{ ++ unsigned int devfn = dev->devfn; ++ ++ if (dev->bus->number != 0) ++ return; ++ ++ /* Only fix up the PCI host settings */ ++ if ((PCI_SLOT(devfn) != 3) || (PCI_FUNC(devfn) != 0)) ++ return; ++ ++ /* Fix up MBARs */ ++ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, HOST_PCI_MBAR0); ++ pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, HOST_PCI_MBAR1); ++ pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, HOST_PCI_MBAR2); ++ pci_write_config_dword(dev, PCI_COMMAND, ++ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL | ++ PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | ++ PCI_COMMAND_FAST_BACK); ++} ++DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, ar2315_pci_fixup); ++ ++static int __init ++ar2315_pci_init(void) ++{ ++ u32 reg; ++ ++ if (ar231x_devtype != DEV_TYPE_AR2315) ++ return -ENODEV; ++ ++ configspace = (unsigned long) ioremap_nocache(0x80000000, 1*1024*1024); /* Remap PCI config space */ ++ ar231x_pci_controller.io_map_base = ++ (unsigned long) ioremap_nocache(AR531X_MEM_BASE + AR531X_MEM_SIZE, AR531X_IO_SIZE); ++ set_io_port_base(ar231x_pci_controller.io_map_base); /* PCI I/O space */ ++ ++ reg = ar231x_mask_reg(AR2315_RESET, 0, AR2315_RESET_PCIDMA); ++ msleep(10); ++ ++ reg &= ~AR2315_RESET_PCIDMA; ++ ar231x_write_reg(AR2315_RESET, reg); ++ msleep(10); ++ ++ ar231x_mask_reg(AR2315_ENDIAN_CTL, 0, ++ AR2315_CONFIG_PCIAHB | AR2315_CONFIG_PCIAHB_BRIDGE); ++ ++ ar231x_write_reg(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM | ++ (AR2315_PCICLK_IN_FREQ_DIV_6 << AR2315_PCICLK_DIV_S)); ++ ar231x_mask_reg(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI); ++ ar231x_mask_reg(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK | AR2315_IF_MASK, ++ AR2315_IF_PCI | AR2315_IF_PCI_HOST | AR2315_IF_PCI_INTR | ++ (AR2315_IF_PCI_CLK_OUTPUT_CLK << AR2315_IF_PCI_CLK_SHIFT)); ++ ++ /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */ ++ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE, ++ AR2315_PCIRST_LOW); ++ msleep(100); ++ ++ /* Bring the PCI out of reset */ ++ ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE, ++ AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8); ++ ++ ar231x_write_reg(AR2315_PCI_UNCACHE_CFG, ++ 0x1E | /* 1GB uncached */ ++ (1 << 5) | /* Enable uncached */ ++ (0x2 << 30) /* Base: 0x80000000 */ ++ ); ++ ar231x_read_reg(AR2315_PCI_UNCACHE_CFG); ++ ++ msleep(500); ++ ++ /* dirty hack - anyone with a datasheet that knows the memory map ? */ ++ ioport_resource.start = 0x10000000; ++ ioport_resource.end = 0xffffffff; ++ iomem_resource.start = 0x10000000; ++ iomem_resource.end = 0xffffffff; ++ ++ register_pci_controller(&ar231x_pci_controller); ++ ++ return 0; ++} ++ ++arch_initcall(ar2315_pci_init); +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/prom.c linux-2.6.39-rc7/arch/mips/ar231x/prom.c +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/prom.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/prom.c 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,37 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright MontaVista Software Inc ++ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. ++ * Copyright (C) 2006 FON Technology, SL. ++ * Copyright (C) 2006 Imre Kaloz ++ * Copyright (C) 2006 Felix Fietkau ++ */ ++ ++/* ++ * Prom setup file for ar531x ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include "ar5312.h" ++#include "ar2315.h" ++ ++void __init prom_init(void) ++{ ++ ar5312_prom_init(); ++ ar2315_prom_init(); ++} ++ ++void __init prom_free_prom_memory(void) ++{ ++} +diff -Nur linux-2.6.39-rc7.orig/arch/mips/ar231x/reset.c linux-2.6.39-rc7/arch/mips/ar231x/reset.c +--- linux-2.6.39-rc7.orig/arch/mips/ar231x/reset.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/ar231x/reset.c 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,161 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "devices.h" ++ ++#define AR531X_RESET_GPIO_IRQ (AR531X_GPIO_IRQ(ar231x_board.config->resetConfigGpio)) ++ ++struct event_t { ++ struct work_struct wq; ++ int set; ++ unsigned long jiffies; ++}; ++ ++static struct timer_list rst_button_timer; ++static unsigned long seen; ++ ++struct sock *uevent_sock = NULL; ++EXPORT_SYMBOL_GPL(uevent_sock); ++extern u64 uevent_next_seqnum(void); ++ ++static int no_release_workaround = 1; ++module_param(no_release_workaround, int, 0); ++ ++static inline void ++add_msg(struct sk_buff *skb, char *msg) ++{ ++ char *scratch; ++ scratch = skb_put(skb, strlen(msg) + 1); ++ sprintf(scratch, msg); ++} ++ ++static void ++hotplug_button(struct work_struct *wq) ++{ ++ struct sk_buff *skb; ++ struct event_t *event; ++ size_t len; ++ char *scratch, *s; ++ char buf[128]; ++ ++ event = container_of(wq, struct event_t, wq); ++ if (!uevent_sock) ++ goto done; ++ ++ /* allocate message with the maximum possible size */ ++ s = event->set ? "pressed" : "released"; ++ len = strlen(s) + 2; ++ skb = alloc_skb(NLMSG_GOODSIZE, GFP_KERNEL); ++ if (!skb) ++ goto done; ++ ++ /* add header */ ++ scratch = skb_put(skb, len); ++ sprintf(scratch, "%s@",s); ++ ++ /* copy keys to our continuous event payload buffer */ ++ add_msg(skb, "HOME=/"); ++ add_msg(skb, "PATH=/sbin:/bin:/usr/sbin:/usr/bin"); ++ add_msg(skb, "SUBSYSTEM=button"); ++ add_msg(skb, "BUTTON=reset"); ++ add_msg(skb, (event->set ? "ACTION=pressed" : "ACTION=released")); ++ sprintf(buf, "SEEN=%ld", (event->jiffies - seen)/HZ); ++ add_msg(skb, buf); ++ snprintf(buf, 128, "SEQNUM=%llu", uevent_next_seqnum()); ++ add_msg(skb, buf); ++ ++ NETLINK_CB(skb).dst_group = 1; ++ netlink_broadcast(uevent_sock, skb, 0, 1, GFP_KERNEL); ++ ++done: ++ kfree(event); ++} ++ ++static void ++reset_button_poll(unsigned long unused) ++{ ++ struct event_t *event; ++ int gpio = ~0; ++ ++ if(!no_release_workaround) ++ return; ++ ++ gpio = ar231x_gpiodev->get(); ++ gpio &= (1 << (AR531X_RESET_GPIO_IRQ - AR531X_GPIO_IRQ_BASE)); ++ if(gpio) { ++ rst_button_timer.expires = jiffies + (HZ / 4); ++ add_timer(&rst_button_timer); ++ return; ++ } ++ ++ event = (struct event_t *) kzalloc(sizeof(struct event_t), GFP_ATOMIC); ++ if (!event) ++ return; ++ ++ event->set = 0; ++ event->jiffies = jiffies; ++ INIT_WORK(&event->wq, hotplug_button); ++ schedule_work(&event->wq); ++} ++ ++static irqreturn_t ++button_handler(int irq, void *dev_id) ++{ ++ static int pressed = 0; ++ struct event_t *event; ++ u32 gpio = ~0; ++ ++ event = (struct event_t *) kzalloc(sizeof(struct event_t), GFP_ATOMIC); ++ if (!event) ++ return IRQ_NONE; ++ ++ pressed = !pressed; ++ ++ gpio = ar231x_gpiodev->get() & (1 << (irq - AR531X_GPIO_IRQ_BASE)); ++ ++ event->set = gpio; ++ if(!event->set) ++ no_release_workaround = 0; ++ ++ event->jiffies = jiffies; ++ ++ INIT_WORK(&event->wq, hotplug_button); ++ schedule_work(&event->wq); ++ ++ seen = jiffies; ++ if(event->set && no_release_workaround) ++ mod_timer(&rst_button_timer, jiffies + (HZ / 4)); ++ ++ return IRQ_HANDLED; ++} ++ ++ ++static int __init ++ar231x_init_reset(void) ++{ ++ seen = jiffies; ++ ++ if (ar231x_board.config->resetConfigGpio == 0xffff) ++ return -ENODEV; ++ ++ init_timer(&rst_button_timer); ++ rst_button_timer.function = reset_button_poll; ++ rst_button_timer.expires = jiffies + HZ / 50; ++ add_timer(&rst_button_timer); ++ ++ request_irq(AR531X_RESET_GPIO_IRQ, &button_handler, IRQF_SAMPLE_RANDOM, "ar231x_reset", NULL); ++ ++ return 0; ++} ++ ++module_init(ar231x_init_reset); +diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar2315_regs.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar2315_regs.h +--- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar2315_regs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar2315_regs.h 2011-05-15 21:44:12.000000000 +0200 +@@ -0,0 +1,580 @@ ++/* ++ * Register definitions for AR2315+ ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. ++ * Copyright (C) 2006 FON Technology, SL. ++ * Copyright (C) 2006 Imre Kaloz ++ * Copyright (C) 2006-2008 Felix Fietkau ++ */ ++ ++#ifndef __AR2315_REG_H ++#define __AR2315_REG_H ++ ++/* ++ * IRQs ++ */ ++#define AR2315_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */ ++#define AR2315_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */ ++#define AR2315_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */ ++#define AR2315_IRQ_LCBUS_PCI MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */ ++#define AR2315_IRQ_WLAN0_POLL MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */ ++ ++/* ++ * Address map ++ */ ++#define AR2315_SPI_READ 0x08000000 /* SPI FLASH */ ++#define AR2315_WLAN0 0x10000000 /* Wireless MMR */ ++#define AR2315_PCI 0x10100000 /* PCI MMR */ ++#define AR2315_SDRAMCTL 0x10300000 /* SDRAM MMR */ ++#define AR2315_LOCAL 0x10400000 /* LOCAL BUS MMR */ ++#define AR2315_ENET0 0x10500000 /* ETHERNET MMR */ ++#define AR2315_DSLBASE 0x11000000 /* RESET CONTROL MMR */ ++#define AR2315_UART0 0x11100003 /* UART MMR */ ++#define AR2315_SPI 0x11300000 /* SPI FLASH MMR */ ++#define AR2315_PCIEXT 0x80000000 /* pci external */ ++ ++/* ++ * Reset Register ++ */ ++#define AR2315_COLD_RESET (AR2315_DSLBASE + 0x0000) ++ ++#define AR2315_RESET_COLD_AHB 0x00000001 ++#define AR2315_RESET_COLD_APB 0x00000002 ++#define AR2315_RESET_COLD_CPU 0x00000004 ++#define AR2315_RESET_COLD_CPUWARM 0x00000008 ++#define AR2315_RESET_SYSTEM (RESET_COLD_CPU | RESET_COLD_APB | RESET_COLD_AHB) /* full system */ ++#define AR2317_RESET_SYSTEM 0x00000010 ++ ++ ++#define AR2315_RESET (AR2315_DSLBASE + 0x0004) ++ ++#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001 /* warm reset WLAN0 MAC */ ++#define AR2315_RESET_WARM_WLAN0_BB 0x00000002 /* warm reset WLAN0 BaseBand */ ++#define AR2315_RESET_MPEGTS_RSVD 0x00000004 /* warm reset MPEG-TS */ ++#define AR2315_RESET_PCIDMA 0x00000008 /* warm reset PCI ahb/dma */ ++#define AR2315_RESET_MEMCTL 0x00000010 /* warm reset memory controller */ ++#define AR2315_RESET_LOCAL 0x00000020 /* warm reset local bus */ ++#define AR2315_RESET_I2C_RSVD 0x00000040 /* warm reset I2C bus */ ++#define AR2315_RESET_SPI 0x00000080 /* warm reset SPI interface */ ++#define AR2315_RESET_UART0 0x00000100 /* warm reset UART0 */ ++#define AR2315_RESET_IR_RSVD 0x00000200 /* warm reset IR interface */ ++#define AR2315_RESET_EPHY0 0x00000400 /* cold reset ENET0 phy */ ++#define AR2315_RESET_ENET0 0x00000800 /* cold reset ENET0 mac */ ++ ++/* ++ * AHB master arbitration control ++ */ ++#define AR2315_AHB_ARB_CTL (AR2315_DSLBASE + 0x0008) ++ ++#define AR2315_ARB_CPU 0x00000001 /* CPU, default */ ++#define AR2315_ARB_WLAN 0x00000002 /* WLAN */ ++#define AR2315_ARB_MPEGTS_RSVD 0x00000004 /* MPEG-TS */ ++#define AR2315_ARB_LOCAL 0x00000008 /* LOCAL */ ++#define AR2315_ARB_PCI 0x00000010 /* PCI */ ++#define AR2315_ARB_ETHERNET 0x00000020 /* Ethernet */ ++#define AR2315_ARB_RETRY 0x00000100 /* retry policy, debug only */ ++ ++/* ++ * Config Register ++ */ ++#define AR2315_ENDIAN_CTL (AR2315_DSLBASE + 0x000c) ++ ++#define AR2315_CONFIG_AHB 0x00000001 /* EC - AHB bridge endianess */ ++#define AR2315_CONFIG_WLAN 0x00000002 /* WLAN byteswap */ ++#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004 /* MPEG-TS byteswap */ ++#define AR2315_CONFIG_PCI 0x00000008 /* PCI byteswap */ ++#define AR2315_CONFIG_MEMCTL 0x00000010 /* Memory controller endianess */ ++#define AR2315_CONFIG_LOCAL 0x00000020 /* Local bus byteswap */ ++#define AR2315_CONFIG_ETHERNET 0x00000040 /* Ethernet byteswap */ ++ ++#define AR2315_CONFIG_MERGE 0x00000200 /* CPU write buffer merge */ ++#define AR2315_CONFIG_CPU 0x00000400 /* CPU big endian */ ++#define AR2315_CONFIG_PCIAHB 0x00000800 ++#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000 ++#define AR2315_CONFIG_SPI 0x00008000 /* SPI byteswap */ ++#define AR2315_CONFIG_CPU_DRAM 0x00010000 ++#define AR2315_CONFIG_CPU_PCI 0x00020000 ++#define AR2315_CONFIG_CPU_MMR 0x00040000 ++#define AR2315_CONFIG_BIG 0x00000400 ++ ++ ++/* ++ * NMI control ++ */ ++#define AR2315_NMI_CTL (AR2315_DSLBASE + 0x0010) ++ ++#define AR2315_NMI_EN 1 ++ ++/* ++ * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR531X 1.0). ++ */ ++#define AR2315_SREV (AR2315_DSLBASE + 0x0014) ++ ++#define AR2315_REV_MAJ 0x00f0 ++#define AR2315_REV_MAJ_S 4 ++#define AR2315_REV_MIN 0x000f ++#define AR2315_REV_MIN_S 0 ++#define AR2315_REV_CHIP (AR2315_REV_MAJ|AR2315_REV_MIN) ++ ++/* ++ * Interface Enable ++ */ ++#define AR2315_IF_CTL (AR2315_DSLBASE + 0x0018) ++ ++#define AR2315_IF_MASK 0x00000007 ++#define AR2315_IF_DISABLED 0 ++#define AR2315_IF_PCI 1 ++#define AR2315_IF_TS_LOCAL 2 ++#define AR2315_IF_ALL 3 /* only for emulation with separate pins */ ++#define AR2315_IF_LOCAL_HOST 0x00000008 ++#define AR2315_IF_PCI_HOST 0x00000010 ++#define AR2315_IF_PCI_INTR 0x00000020 ++#define AR2315_IF_PCI_CLK_MASK 0x00030000 ++#define AR2315_IF_PCI_CLK_INPUT 0 ++#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1 ++#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2 ++#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3 ++#define AR2315_IF_PCI_CLK_SHIFT 16 ++ ++/* ++ * APB Interrupt control ++ */ ++ ++#define AR2315_ISR (AR2315_DSLBASE + 0x0020) ++#define AR2315_IMR (AR2315_DSLBASE + 0x0024) ++#define AR2315_GISR (AR2315_DSLBASE + 0x0028) ++ ++#define AR2315_ISR_UART0 0x0001 /* high speed UART */ ++#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */ ++#define AR2315_ISR_SPI 0x0004 /* SPI bus */ ++#define AR2315_ISR_AHB 0x0008 /* AHB error */ ++#define AR2315_ISR_APB 0x0010 /* APB error */ ++#define AR2315_ISR_TIMER 0x0020 /* timer */ ++#define AR2315_ISR_GPIO 0x0040 /* GPIO */ ++#define AR2315_ISR_WD 0x0080 /* watchdog */ ++#define AR2315_ISR_IR_RSVD 0x0100 /* IR */ ++ ++#define AR2315_GISR_MISC 0x0001 ++#define AR2315_GISR_WLAN0 0x0002 ++#define AR2315_GISR_MPEGTS_RSVD 0x0004 ++#define AR2315_GISR_LOCALPCI 0x0008 ++#define AR2315_GISR_WMACPOLL 0x0010 ++#define AR2315_GISR_TIMER 0x0020 ++#define AR2315_GISR_ETHERNET 0x0040 ++ ++/* ++ * Interrupt routing from IO to the processor IP bits ++ * Define our inter mask and level ++ */ ++#define AR2315_INTR_MISCIO SR_IBIT3 ++#define AR2315_INTR_WLAN0 SR_IBIT4 ++#define AR2315_INTR_ENET0 SR_IBIT5 ++#define AR2315_INTR_LOCALPCI SR_IBIT6 ++#define AR2315_INTR_WMACPOLL SR_IBIT7 ++#define AR2315_INTR_COMPARE SR_IBIT8 ++ ++/* ++ * Timers ++ */ ++#define AR2315_TIMER (AR2315_DSLBASE + 0x0030) ++#define AR2315_RELOAD (AR2315_DSLBASE + 0x0034) ++#define AR2315_WD (AR2315_DSLBASE + 0x0038) ++#define AR2315_WDC (AR2315_DSLBASE + 0x003c) ++ ++#define AR2315_WDC_IGNORE_EXPIRATION 0x00000000 ++#define AR2315_WDC_NMI 0x00000001 /* NMI on watchdog */ ++#define AR2315_WDC_RESET 0x00000002 /* reset on watchdog */ ++ ++/* ++ * CPU Performance Counters ++ */ ++#define AR2315_PERFCNT0 (AR2315_DSLBASE + 0x0048) ++#define AR2315_PERFCNT1 (AR2315_DSLBASE + 0x004c) ++ ++#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */ ++#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */ ++#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */ ++#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */ ++#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */ ++#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */ ++#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */ ++ ++#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */ ++#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */ ++#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */ ++#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */ ++#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */ ++#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */ ++#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */ ++ ++/* ++ * AHB Error Reporting. ++ */ ++#define AR2315_AHB_ERR0 (AR2315_DSLBASE + 0x0050) /* error */ ++#define AR2315_AHB_ERR1 (AR2315_DSLBASE + 0x0054) /* haddr */ ++#define AR2315_AHB_ERR2 (AR2315_DSLBASE + 0x0058) /* hwdata */ ++#define AR2315_AHB_ERR3 (AR2315_DSLBASE + 0x005c) /* hrdata */ ++#define AR2315_AHB_ERR4 (AR2315_DSLBASE + 0x0060) /* status */ ++ ++#define AHB_ERROR_DET 1 /* AHB Error has been detected, */ ++ /* write 1 to clear all bits in ERR0 */ ++#define AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */ ++#define AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */ ++ ++#define AR2315_PROCERR_HMAST 0x0000000f ++#define AR2315_PROCERR_HMAST_DFLT 0 ++#define AR2315_PROCERR_HMAST_WMAC 1 ++#define AR2315_PROCERR_HMAST_ENET 2 ++#define AR2315_PROCERR_HMAST_PCIENDPT 3 ++#define AR2315_PROCERR_HMAST_LOCAL 4 ++#define AR2315_PROCERR_HMAST_CPU 5 ++#define AR2315_PROCERR_HMAST_PCITGT 6 ++ ++#define AR2315_PROCERR_HMAST_S 0 ++#define AR2315_PROCERR_HWRITE 0x00000010 ++#define AR2315_PROCERR_HSIZE 0x00000060 ++#define AR2315_PROCERR_HSIZE_S 5 ++#define AR2315_PROCERR_HTRANS 0x00000180 ++#define AR2315_PROCERR_HTRANS_S 7 ++#define AR2315_PROCERR_HBURST 0x00000e00 ++#define AR2315_PROCERR_HBURST_S 9 ++ ++/* ++ * Clock Control ++ */ ++#define AR2315_PLLC_CTL (AR2315_DSLBASE + 0x0064) ++#define AR2315_PLLV_CTL (AR2315_DSLBASE + 0x0068) ++#define AR2315_CPUCLK (AR2315_DSLBASE + 0x006c) ++#define AR2315_AMBACLK (AR2315_DSLBASE + 0x0070) ++#define AR2315_SYNCCLK (AR2315_DSLBASE + 0x0074) ++#define AR2315_DSL_SLEEP_CTL (AR2315_DSLBASE + 0x0080) ++#define AR2315_DSL_SLEEP_DUR (AR2315_DSLBASE + 0x0084) ++ ++/* PLLc Control fields */ ++#define PLLC_REF_DIV_M 0x00000003 ++#define PLLC_REF_DIV_S 0 ++#define PLLC_FDBACK_DIV_M 0x0000007C ++#define PLLC_FDBACK_DIV_S 2 ++#define PLLC_ADD_FDBACK_DIV_M 0x00000080 ++#define PLLC_ADD_FDBACK_DIV_S 7 ++#define PLLC_CLKC_DIV_M 0x0001c000 ++#define PLLC_CLKC_DIV_S 14 ++#define PLLC_CLKM_DIV_M 0x00700000 ++#define PLLC_CLKM_DIV_S 20 ++ ++/* CPU CLK Control fields */ ++#define CPUCLK_CLK_SEL_M 0x00000003 ++#define CPUCLK_CLK_SEL_S 0 ++#define CPUCLK_CLK_DIV_M 0x0000000c ++#define CPUCLK_CLK_DIV_S 2 ++ ++/* AMBA CLK Control fields */ ++#define AMBACLK_CLK_SEL_M 0x00000003 ++#define AMBACLK_CLK_SEL_S 0 ++#define AMBACLK_CLK_DIV_M 0x0000000c ++#define AMBACLK_CLK_DIV_S 2 ++ ++/* ++ * GPIO ++ */ ++#define AR2315_GPIO_DI (AR2315_DSLBASE + 0x0088) ++#define AR2315_GPIO_DO (AR2315_DSLBASE + 0x0090) ++#define AR2315_GPIO_CR (AR2315_DSLBASE + 0x0098) ++#define AR2315_GPIO_INT (AR2315_DSLBASE + 0x00a0) ++ ++#define AR2315_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */ ++#define AR2315_GPIO_CR_O(x) (1 << (x)) /* output */ ++#define AR2315_GPIO_CR_I(x) (0) /* input */ ++ ++#define AR2315_GPIO_INT_S(x) (x) /* interrupt enable */ ++#define AR2315_GPIO_INT_M (0x3F) /* mask for int */ ++#define AR2315_GPIO_INT_LVL(x) ((x) << 6) /* interrupt level */ ++#define AR2315_GPIO_INT_LVL_M ((0x3) << 6) /* mask for int level */ ++ ++#define AR2315_GPIO_INT_MAX_Y 1 /* Maximum value of Y for AR5313_GPIO_INT_* macros */ ++#define AR2315_GPIO_INT_LVL_OFF 0 /* Triggerring off */ ++#define AR2315_GPIO_INT_LVL_LOW 1 /* Low Level Triggered */ ++#define AR2315_GPIO_INT_LVL_HIGH 2 /* High Level Triggered */ ++#define AR2315_GPIO_INT_LVL_EDGE 3 /* Edge Triggered */ ++ ++#define AR2315_RESET_GPIO 5 ++#define AR2315_NUM_GPIO 22 ++ ++/* ++ * PCI Clock Control ++ */ ++#define AR2315_PCICLK (AR2315_DSLBASE + 0x00a4) ++ ++#define AR2315_PCICLK_INPUT_M 0x3 ++#define AR2315_PCICLK_INPUT_S 0 ++ ++#define AR2315_PCICLK_PLLC_CLKM 0 ++#define AR2315_PCICLK_PLLC_CLKM1 1 ++#define AR2315_PCICLK_PLLC_CLKC 2 ++#define AR2315_PCICLK_REF_CLK 3 ++ ++#define AR2315_PCICLK_DIV_M 0xc ++#define AR2315_PCICLK_DIV_S 2 ++ ++#define AR2315_PCICLK_IN_FREQ 0 ++#define AR2315_PCICLK_IN_FREQ_DIV_6 1 ++#define AR2315_PCICLK_IN_FREQ_DIV_8 2 ++#define AR2315_PCICLK_IN_FREQ_DIV_10 3 ++ ++/* ++ * Observation Control Register ++ */ ++#define AR2315_OCR (AR2315_DSLBASE + 0x00b0) ++#define OCR_GPIO0_IRIN 0x0040 ++#define OCR_GPIO1_IROUT 0x0080 ++#define OCR_GPIO3_RXCLR 0x0200 ++ ++/* ++ * General Clock Control ++ */ ++ ++#define AR2315_MISCCLK (AR2315_DSLBASE + 0x00b4) ++#define MISCCLK_PLLBYPASS_EN 0x00000001 ++#define MISCCLK_PROCREFCLK 0x00000002 ++ ++/* ++ * SDRAM Controller ++ * - No read or write buffers are included. ++ */ ++#define AR2315_MEM_CFG (AR2315_SDRAMCTL + 0x00) ++#define AR2315_MEM_CTRL (AR2315_SDRAMCTL + 0x0c) ++#define AR2315_MEM_REF (AR2315_SDRAMCTL + 0x10) ++ ++#define SDRAM_DATA_WIDTH_M 0x00006000 ++#define SDRAM_DATA_WIDTH_S 13 ++ ++#define SDRAM_COL_WIDTH_M 0x00001E00 ++#define SDRAM_COL_WIDTH_S 9 ++ ++#define SDRAM_ROW_WIDTH_M 0x000001E0 ++#define SDRAM_ROW_WIDTH_S 5 ++ ++#define SDRAM_BANKADDR_BITS_M 0x00000018 ++#define SDRAM_BANKADDR_BITS_S 3 ++ ++/* ++ * SPI Flash Interface Registers ++ */ ++ ++#define AR2315_SPI_CTL (AR2315_SPI + 0x00) ++#define AR2315_SPI_OPCODE (AR2315_SPI + 0x04) ++#define AR2315_SPI_DATA (AR2315_SPI + 0x08) ++ ++#define SPI_CTL_START 0x00000100 ++#define SPI_CTL_BUSY 0x00010000 ++#define SPI_CTL_TXCNT_MASK 0x0000000f ++#define SPI_CTL_RXCNT_MASK 0x000000f0 ++#define SPI_CTL_TX_RX_CNT_MASK 0x000000ff ++#define SPI_CTL_SIZE_MASK 0x00060000 ++ ++#define SPI_CTL_CLK_SEL_MASK 0x03000000 ++#define SPI_OPCODE_MASK 0x000000ff ++ ++/* ++ * PCI Bus Interface Registers ++ */ ++#define AR2315_PCI_1MS_REG (AR2315_PCI + 0x0008) ++#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */ ++ ++#define AR2315_PCI_MISC_CONFIG (AR2315_PCI + 0x000c) ++#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */ ++#define AR2315_PCIMISC_CFG_SEL 0x00000002 /* mem or config cycles */ ++#define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */ ++#define AR2315_PCIMISC_RST_MODE 0x00000030 ++#define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */ ++#define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */ ++#define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */ ++#define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */ ++#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */ ++#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */ ++#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */ ++#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache disable */ ++ ++#define AR2315_PCI_OUT_TSTAMP (AR2315_PCI + 0x0010) ++ ++#define AR2315_PCI_UNCACHE_CFG (AR2315_PCI + 0x0014) ++ ++#define AR2315_PCI_IN_EN (AR2315_PCI + 0x0100) ++#define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */ ++#define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */ ++#define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */ ++#define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */ ++ ++#define AR2315_PCI_IN_DIS (AR2315_PCI + 0x0104) ++#define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */ ++#define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */ ++#define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */ ++#define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */ ++ ++#define AR2315_PCI_IN_PTR (AR2315_PCI + 0x0200) ++ ++#define AR2315_PCI_OUT_EN (AR2315_PCI + 0x0400) ++#define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */ ++ ++#define AR2315_PCI_OUT_DIS (AR2315_PCI + 0x0404) ++#define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */ ++ ++#define AR2315_PCI_OUT_PTR (AR2315_PCI + 0x0408) ++ ++#define AR2315_PCI_INT_STATUS (AR2315_PCI + 0x0500) /* write one to clr */ ++#define AR2315_PCI_TXINT 0x00000001 /* Desc In Completed */ ++#define AR2315_PCI_TXOK 0x00000002 /* Desc In OK */ ++#define AR2315_PCI_TXERR 0x00000004 /* Desc In ERR */ ++#define AR2315_PCI_TXEOL 0x00000008 /* Desc In End-of-List */ ++#define AR2315_PCI_RXINT 0x00000010 /* Desc Out Completed */ ++#define AR2315_PCI_RXOK 0x00000020 /* Desc Out OK */ ++#define AR2315_PCI_RXERR 0x00000040 /* Desc Out ERR */ ++#define AR2315_PCI_RXEOL 0x00000080 /* Desc Out EOL */ ++#define AR2315_PCI_TXOOD 0x00000200 /* Desc In Out-of-Desc */ ++#define AR2315_PCI_MASK 0x0000FFFF /* Desc Mask */ ++#define AR2315_PCI_EXT_INT 0x02000000 ++#define AR2315_PCI_ABORT_INT 0x04000000 ++ ++#define AR2315_PCI_INT_MASK (AR2315_PCI + 0x0504) /* same as INT_STATUS */ ++ ++#define AR2315_PCI_INTEN_REG (AR2315_PCI + 0x0508) ++#define AR2315_PCI_INT_DISABLE 0x00 /* disable pci interrupts */ ++#define AR2315_PCI_INT_ENABLE 0x01 /* enable pci interrupts */ ++ ++#define AR2315_PCI_HOST_IN_EN (AR2315_PCI + 0x0800) ++#define AR2315_PCI_HOST_IN_DIS (AR2315_PCI + 0x0804) ++#define AR2315_PCI_HOST_IN_PTR (AR2315_PCI + 0x0810) ++#define AR2315_PCI_HOST_OUT_EN (AR2315_PCI + 0x0900) ++#define AR2315_PCI_HOST_OUT_DIS (AR2315_PCI + 0x0904) ++#define AR2315_PCI_HOST_OUT_PTR (AR2315_PCI + 0x0908) ++ ++ ++/* ++ * Local Bus Interface Registers ++ */ ++#define AR2315_LB_CONFIG (AR2315_LOCAL + 0x0000) ++#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */ ++#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */ ++#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */ ++#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */ ++#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */ ++#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */ ++#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */ ++#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */ ++#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */ ++#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */ ++#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */ ++#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */ ++#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */ ++#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */ ++#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */ ++#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */ ++#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */ ++#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */ ++#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */ ++#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */ ++#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */ ++#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */ ++#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */ ++#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */ ++#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */ ++ ++#define AR2315_LB_CLKSEL (AR2315_LOCAL + 0x0004) ++#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */ ++ ++#define AR2315_LB_1MS (AR2315_LOCAL + 0x0008) ++#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */ ++ ++#define AR2315_LB_MISCCFG (AR2315_LOCAL + 0x000C) ++#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */ ++#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */ ++#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */ ++#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */ ++#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */ ++#define AR2315_LBM_TIMEOUT_MASK 0x00FFFF80 ++#define AR2315_LBM_TIMEOUT_SHFT 7 ++#define AR2315_LBM_PORTMUX 0x07000000 ++ ++ ++#define AR2315_LB_RXTSOFF (AR2315_LOCAL + 0x0010) ++ ++#define AR2315_LB_TX_CHAIN_EN (AR2315_LOCAL + 0x0100) ++#define AR2315_LB_TXEN_0 0x01 ++#define AR2315_LB_TXEN_1 0x02 ++#define AR2315_LB_TXEN_2 0x04 ++#define AR2315_LB_TXEN_3 0x08 ++ ++#define AR2315_LB_TX_CHAIN_DIS (AR2315_LOCAL + 0x0104) ++#define AR2315_LB_TX_DESC_PTR (AR2315_LOCAL + 0x0200) ++ ++#define AR2315_LB_RX_CHAIN_EN (AR2315_LOCAL + 0x0400) ++#define AR2315_LB_RXEN 0x01 ++ ++#define AR2315_LB_RX_CHAIN_DIS (AR2315_LOCAL + 0x0404) ++#define AR2315_LB_RX_DESC_PTR (AR2315_LOCAL + 0x0408) ++ ++#define AR2315_LB_INT_STATUS (AR2315_LOCAL + 0x0500) ++#define AR2315_INT_TX_DESC 0x0001 ++#define AR2315_INT_TX_OK 0x0002 ++#define AR2315_INT_TX_ERR 0x0004 ++#define AR2315_INT_TX_EOF 0x0008 ++#define AR2315_INT_RX_DESC 0x0010 ++#define AR2315_INT_RX_OK 0x0020 ++#define AR2315_INT_RX_ERR 0x0040 ++#define AR2315_INT_RX_EOF 0x0080 ++#define AR2315_INT_TX_TRUNC 0x0100 ++#define AR2315_INT_TX_STARVE 0x0200 ++#define AR2315_INT_LB_TIMEOUT 0x0400 ++#define AR2315_INT_LB_ERR 0x0800 ++#define AR2315_INT_MBOX_WR 0x1000 ++#define AR2315_INT_MBOX_RD 0x2000 ++ ++/* Bit definitions for INT MASK are the same as INT_STATUS */ ++#define AR2315_LB_INT_MASK (AR2315_LOCAL + 0x0504) ++ ++#define AR2315_LB_INT_EN (AR2315_LOCAL + 0x0508) ++#define AR2315_LB_MBOX (AR2315_LOCAL + 0x0600) ++ ++/* ++ * IR Interface Registers ++ */ ++#define AR2315_IR_PKTDATA (AR2315_IR + 0x0000) ++ ++#define AR2315_IR_PKTLEN (AR2315_IR + 0x07fc) /* 0 - 63 */ ++ ++#define AR2315_IR_CONTROL (AR2315_IR + 0x0800) ++#define AR2315_IRCTL_TX 0x00000000 /* use as tranmitter */ ++#define AR2315_IRCTL_RX 0x00000001 /* use as receiver */ ++#define AR2315_IRCTL_SAMPLECLK_MASK 0x00003ffe /* Sample clk divisor mask */ ++#define AR2315_IRCTL_SAMPLECLK_SHFT 1 ++#define AR2315_IRCTL_OUTPUTCLK_MASK 0x03ffc000 /* Output clk divisor mask */ ++#define AR2315_IRCTL_OUTPUTCLK_SHFT 14 ++ ++#define AR2315_IR_STATUS (AR2315_IR + 0x0804) ++#define AR2315_IRSTS_RX 0x00000001 /* receive in progress */ ++#define AR2315_IRSTS_TX 0x00000002 /* transmit in progress */ ++ ++#define AR2315_IR_CONFIG (AR2315_IR + 0x0808) ++#define AR2315_IRCFG_INVIN 0x00000001 /* invert input polarity */ ++#define AR2315_IRCFG_INVOUT 0x00000002 /* invert output polarity */ ++#define AR2315_IRCFG_SEQ_START_WIN_SEL 0x00000004 /* 1 => 28, 0 => 7 */ ++#define AR2315_IRCFG_SEQ_START_THRESH 0x000000f0 /* */ ++#define AR2315_IRCFG_SEQ_END_UNIT_SEL 0x00000100 /* */ ++#define AR2315_IRCFG_SEQ_END_UNIT_THRESH 0x00007e00 /* */ ++#define AR2315_IRCFG_SEQ_END_WIN_SEL 0x00008000 /* */ ++#define AR2315_IRCFG_SEQ_END_WIN_THRESH 0x001f0000 /* */ ++#define AR2315_IRCFG_NUM_BACKOFF_WORDS 0x01e00000 /* */ ++ ++#define HOST_PCI_DEV_ID 3 ++#define HOST_PCI_MBAR0 0x10000000 ++#define HOST_PCI_MBAR1 0x20000000 ++#define HOST_PCI_MBAR2 0x30000000 ++ ++#define HOST_PCI_SDRAM_BASEADDR HOST_PCI_MBAR1 ++#define PCI_DEVICE_MEM_SPACE 0x800000 ++ ++#endif /* __AR2315_REG_H */ +diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar2315_spiflash.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar2315_spiflash.h +--- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar2315_spiflash.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar2315_spiflash.h 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,116 @@ ++/* ++ * SPI Flash Memory support header file. ++ * ++ * Copyright (c) 2005, Atheros Communications Inc. ++ * Copyright (C) 2006 FON Technology, SL. ++ * Copyright (C) 2006 Imre Kaloz ++ * Copyright (C) 2006-2009 Felix Fietkau ++ * ++ * This code is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++#ifndef __AR2315_SPIFLASH_H ++#define __AR2315_SPIFLASH_H ++ ++#define STM_PAGE_SIZE 256 ++ ++#define SFI_WRITE_BUFFER_SIZE 4 ++#define SFI_FLASH_ADDR_MASK 0x00ffffff ++ ++#define STM_8MBIT_SIGNATURE 0x13 ++#define STM_M25P80_BYTE_COUNT 1048576 ++#define STM_M25P80_SECTOR_COUNT 16 ++#define STM_M25P80_SECTOR_SIZE 0x10000 ++ ++#define STM_16MBIT_SIGNATURE 0x14 ++#define STM_M25P16_BYTE_COUNT 2097152 ++#define STM_M25P16_SECTOR_COUNT 32 ++#define STM_M25P16_SECTOR_SIZE 0x10000 ++ ++#define STM_32MBIT_SIGNATURE 0x15 ++#define STM_M25P32_BYTE_COUNT 4194304 ++#define STM_M25P32_SECTOR_COUNT 64 ++#define STM_M25P32_SECTOR_SIZE 0x10000 ++ ++#define STM_64MBIT_SIGNATURE 0x16 ++#define STM_M25P64_BYTE_COUNT 8388608 ++#define STM_M25P64_SECTOR_COUNT 128 ++#define STM_M25P64_SECTOR_SIZE 0x10000 ++ ++#define STM_128MBIT_SIGNATURE 0x17 ++#define STM_M25P128_BYTE_COUNT 16777216 ++#define STM_M25P128_SECTOR_COUNT 256 ++#define STM_M25P128_SECTOR_SIZE 0x10000 ++ ++#define STM_1MB_BYTE_COUNT STM_M25P80_BYTE_COUNT ++#define STM_1MB_SECTOR_COUNT STM_M25P80_SECTOR_COUNT ++#define STM_1MB_SECTOR_SIZE STM_M25P80_SECTOR_SIZE ++#define STM_2MB_BYTE_COUNT STM_M25P16_BYTE_COUNT ++#define STM_2MB_SECTOR_COUNT STM_M25P16_SECTOR_COUNT ++#define STM_2MB_SECTOR_SIZE STM_M25P16_SECTOR_SIZE ++#define STM_4MB_BYTE_COUNT STM_M25P32_BYTE_COUNT ++#define STM_4MB_SECTOR_COUNT STM_M25P32_SECTOR_COUNT ++#define STM_4MB_SECTOR_SIZE STM_M25P32_SECTOR_SIZE ++#define STM_8MB_BYTE_COUNT STM_M25P64_BYTE_COUNT ++#define STM_8MB_SECTOR_COUNT STM_M25P64_SECTOR_COUNT ++#define STM_8MB_SECTOR_SIZE STM_M25P64_SECTOR_SIZE ++#define STM_16MB_BYTE_COUNT STM_M25P128_BYTE_COUNT ++#define STM_16MB_SECTOR_COUNT STM_M25P128_SECTOR_COUNT ++#define STM_16MB_SECTOR_SIZE STM_M25P128_SECTOR_SIZE ++ ++/* ++ * ST Microelectronics Opcodes for Serial Flash ++ */ ++ ++#define STM_OP_WR_ENABLE 0x06 /* Write Enable */ ++#define STM_OP_WR_DISABLE 0x04 /* Write Disable */ ++#define STM_OP_RD_STATUS 0x05 /* Read Status */ ++#define STM_OP_WR_STATUS 0x01 /* Write Status */ ++#define STM_OP_RD_DATA 0x03 /* Read Data */ ++#define STM_OP_FAST_RD_DATA 0x0b /* Fast Read Data */ ++#define STM_OP_PAGE_PGRM 0x02 /* Page Program */ ++#define STM_OP_SECTOR_ERASE 0xd8 /* Sector Erase */ ++#define STM_OP_BULK_ERASE 0xc7 /* Bulk Erase */ ++#define STM_OP_DEEP_PWRDOWN 0xb9 /* Deep Power-Down Mode */ ++#define STM_OP_RD_SIG 0xab /* Read Electronic Signature */ ++ ++#define STM_STATUS_WIP 0x01 /* Write-In-Progress */ ++#define STM_STATUS_WEL 0x02 /* Write Enable Latch */ ++#define STM_STATUS_BP0 0x04 /* Block Protect 0 */ ++#define STM_STATUS_BP1 0x08 /* Block Protect 1 */ ++#define STM_STATUS_BP2 0x10 /* Block Protect 2 */ ++#define STM_STATUS_SRWD 0x80 /* Status Register Write Disable */ ++ ++/* ++ * SPI Flash Interface Registers ++ */ ++#define AR531XPLUS_SPI_READ 0x08000000 ++#define AR531XPLUS_SPI_MMR 0x11300000 ++#define AR531XPLUS_SPI_MMR_SIZE 12 ++ ++#define AR531XPLUS_SPI_CTL 0x00 ++#define AR531XPLUS_SPI_OPCODE 0x04 ++#define AR531XPLUS_SPI_DATA 0x08 ++ ++#define SPI_FLASH_READ AR531XPLUS_SPI_READ ++#define SPI_FLASH_MMR AR531XPLUS_SPI_MMR ++#define SPI_FLASH_MMR_SIZE AR531XPLUS_SPI_MMR_SIZE ++#define SPI_FLASH_CTL AR531XPLUS_SPI_CTL ++#define SPI_FLASH_OPCODE AR531XPLUS_SPI_OPCODE ++#define SPI_FLASH_DATA AR531XPLUS_SPI_DATA ++ ++#define SPI_CTL_START 0x00000100 ++#define SPI_CTL_BUSY 0x00010000 ++#define SPI_CTL_TXCNT_MASK 0x0000000f ++#define SPI_CTL_RXCNT_MASK 0x000000f0 ++#define SPI_CTL_TX_RX_CNT_MASK 0x000000ff ++#define SPI_CTL_SIZE_MASK 0x00060000 ++ ++#define SPI_CTL_CLK_SEL_MASK 0x03000000 ++#define SPI_OPCODE_MASK 0x000000ff ++ ++#define SPI_STATUS_WIP STM_STATUS_WIP ++ ++#endif +diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar231x.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar231x.h +--- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar231x.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar231x.h 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,54 @@ ++#ifndef __AR531X_H ++#define __AR531X_H ++ ++#define AR531X_MISC_IRQ_BASE 0x20 ++#define AR531X_GPIO_IRQ_BASE 0x30 ++ ++/* Software's idea of interrupts handled by "CPU Interrupt Controller" */ ++#define AR531X_IRQ_NONE MIPS_CPU_IRQ_BASE+0 ++#define AR531X_IRQ_CPU_CLOCK MIPS_CPU_IRQ_BASE+7 /* C0_CAUSE: 0x8000 */ ++ ++/* Miscellaneous interrupts, which share IP6 */ ++#define AR531X_MISC_IRQ_NONE AR531X_MISC_IRQ_BASE+0 ++#define AR531X_MISC_IRQ_TIMER AR531X_MISC_IRQ_BASE+1 ++#define AR531X_MISC_IRQ_AHB_PROC AR531X_MISC_IRQ_BASE+2 ++#define AR531X_MISC_IRQ_AHB_DMA AR531X_MISC_IRQ_BASE+3 ++#define AR531X_MISC_IRQ_GPIO AR531X_MISC_IRQ_BASE+4 ++#define AR531X_MISC_IRQ_UART0 AR531X_MISC_IRQ_BASE+5 ++#define AR531X_MISC_IRQ_UART0_DMA AR531X_MISC_IRQ_BASE+6 ++#define AR531X_MISC_IRQ_WATCHDOG AR531X_MISC_IRQ_BASE+7 ++#define AR531X_MISC_IRQ_LOCAL AR531X_MISC_IRQ_BASE+8 ++#define AR531X_MISC_IRQ_SPI AR531X_MISC_IRQ_BASE+9 ++#define AR531X_MISC_IRQ_COUNT 10 ++ ++/* GPIO Interrupts [0..7], share AR531X_MISC_IRQ_GPIO */ ++#define AR531X_GPIO_IRQ_NONE AR531X_GPIO_IRQ_BASE+0 ++#define AR531X_GPIO_IRQ(n) AR531X_GPIO_IRQ_BASE+n ++#define AR531X_GPIO_IRQ_COUNT 22 ++ ++static inline u32 ++ar231x_read_reg(u32 reg) ++{ ++ return __raw_readl((u32 *) KSEG1ADDR(reg)); ++} ++ ++static inline void ++ar231x_write_reg(u32 reg, u32 val) ++{ ++ __raw_writel(val, (u32 *) KSEG1ADDR(reg)); ++} ++ ++static inline u32 ++ar231x_mask_reg(u32 reg, u32 mask, u32 val) ++{ ++ u32 ret; ++ ++ ret = ar231x_read_reg(reg); ++ ret &= ~mask; ++ ret |= val; ++ ar231x_write_reg(reg, ret); ++ ++ return ret; ++} ++ ++#endif +diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar231x_platform.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar231x_platform.h +--- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar231x_platform.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar231x_platform.h 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,83 @@ ++#ifndef __AR531X_PLATFORM_H ++#define __AR531X_PLATFORM_H ++ ++/* ++ * This is board-specific data that is stored in a "fixed" location in flash. ++ * It is shared across operating systems, so it should not be changed lightly. ++ * The main reason we need it is in order to extract the ethernet MAC ++ * address(es). ++ */ ++struct ar231x_boarddata { ++ u32 magic; /* board data is valid */ ++#define AR531X_BD_MAGIC 0x35333131 /* "5311", for all 531x platforms */ ++ u16 cksum; /* checksum (starting with BD_REV 2) */ ++ u16 rev; /* revision of this struct */ ++#define BD_REV 4 ++ char boardName[64]; /* Name of board */ ++ u16 major; /* Board major number */ ++ u16 minor; /* Board minor number */ ++ u32 flags; /* Board configuration */ ++#define BD_ENET0 0x00000001 /* ENET0 is stuffed */ ++#define BD_ENET1 0x00000002 /* ENET1 is stuffed */ ++#define BD_UART1 0x00000004 /* UART1 is stuffed */ ++#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */ ++#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */ ++#define BD_SYSLED 0x00000020 /* System LED stuffed */ ++#define BD_EXTUARTCLK 0x00000040 /* External UART clock */ ++#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */ ++#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */ ++#define BD_WLAN0 0x00000200 /* Enable WLAN0 */ ++#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ memCap for testing */ ++#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */ ++#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */ ++#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */ ++#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */ ++#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */ ++#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */ ++#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */ ++ u16 resetConfigGpio; /* Reset factory GPIO pin */ ++ u16 sysLedGpio; /* System LED GPIO pin */ ++ ++ u32 cpuFreq; /* CPU core frequency in Hz */ ++ u32 sysFreq; /* System frequency in Hz */ ++ u32 cntFreq; /* Calculated C0_COUNT frequency */ ++ ++ u8 wlan0_mac[6]; ++ u8 enet0_mac[6]; ++ u8 enet1_mac[6]; ++ ++ u16 pciId; /* Pseudo PCIID for common code */ ++ u16 memCap; /* cap bank1 in MB */ ++ ++ /* version 3 */ ++ u8 wlan1_mac[6]; /* (ar5212) */ ++}; ++ ++#define BOARD_CONFIG_BUFSZ 0x1000 ++ ++/* ++ * Platform device information for the Wireless MAC ++ */ ++struct ar231x_board_config { ++ u16 devid; ++ ++ /* board config data */ ++ struct ar231x_boarddata *config; ++ ++ /* radio calibration data */ ++ const char *radio; ++}; ++ ++/* ++ * Platform device information for the Ethernet MAC ++ */ ++struct ar231x_eth { ++ u32 reset_base; ++ u32 reset_mac; ++ u32 reset_phy; ++ u32 phy_base; ++ struct ar231x_board_config *config; ++ char *macaddr; ++}; ++ ++#endif /* __AR531X_PLATFORM_H */ +diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar5312_regs.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar5312_regs.h +--- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/ar5312_regs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/ar5312_regs.h 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,236 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved. ++ * Copyright (C) 2006 Imre Kaloz ++ * Copyright (C) 2006 Felix Fietkau ++ */ ++ ++#ifndef AR5312_H ++#define AR5312_H ++ ++#include ++ ++/* ++ * IRQs ++ */ ++ ++#define AR5312_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */ ++#define AR5312_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */ ++#define AR5312_IRQ_ENET1_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */ ++#define AR5312_IRQ_WLAN1_INTRS MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */ ++#define AR5312_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */ ++ ++ ++/* Address Map */ ++#define AR531X_WLAN0 0x18000000 ++#define AR531X_WLAN1 0x18500000 ++#define AR531X_ENET0 0x18100000 ++#define AR531X_ENET1 0x18200000 ++#define AR531X_SDRAMCTL 0x18300000 ++#define AR531X_FLASHCTL 0x18400000 ++#define AR531X_APBBASE 0x1c000000 ++#define AR531X_FLASH 0x1e000000 ++#define AR531X_UART0 0xbc000003 /* UART MMR */ ++ ++/* ++ * AR531X_NUM_ENET_MAC defines the number of ethernet MACs that ++ * should be considered available. The AR5312 supports 2 enet MACS, ++ * even though many reference boards only actually use 1 of them ++ * (i.e. Only MAC 0 is actually connected to an enet PHY or PHY switch. ++ * The AR2312 supports 1 enet MAC. ++ */ ++#define AR531X_NUM_ENET_MAC 2 ++ ++/* ++ * Need these defines to determine true number of ethernet MACs ++ */ ++#define AR5212_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */ ++#define AR5212_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */ ++#define AR5212_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */ ++#define AR531X_RADIO_MASK_OFF 0xc8 ++#define AR531X_RADIO0_MASK 0x0003 ++#define AR531X_RADIO1_MASK 0x000c ++#define AR531X_RADIO1_S 2 ++ ++/* ++ * AR531X_NUM_WMAC defines the number of Wireless MACs that\ ++ * should be considered available. ++ */ ++#define AR531X_NUM_WMAC 2 ++ ++/* Reset/Timer Block Address Map */ ++#define AR531X_RESETTMR (AR531X_APBBASE + 0x3000) ++#define AR531X_TIMER (AR531X_RESETTMR + 0x0000) /* countdown timer */ ++#define AR531X_WD_CTRL (AR531X_RESETTMR + 0x0008) /* watchdog cntrl */ ++#define AR531X_WD_TIMER (AR531X_RESETTMR + 0x000c) /* watchdog timer */ ++#define AR531X_ISR (AR531X_RESETTMR + 0x0010) /* Intr Status Reg */ ++#define AR531X_IMR (AR531X_RESETTMR + 0x0014) /* Intr Mask Reg */ ++#define AR531X_RESET (AR531X_RESETTMR + 0x0020) ++#define AR5312_CLOCKCTL1 (AR531X_RESETTMR + 0x0064) ++#define AR5312_SCRATCH (AR531X_RESETTMR + 0x006c) ++#define AR531X_PROCADDR (AR531X_RESETTMR + 0x0070) ++#define AR531X_PROC1 (AR531X_RESETTMR + 0x0074) ++#define AR531X_DMAADDR (AR531X_RESETTMR + 0x0078) ++#define AR531X_DMA1 (AR531X_RESETTMR + 0x007c) ++#define AR531X_ENABLE (AR531X_RESETTMR + 0x0080) /* interface enb */ ++#define AR531X_REV (AR531X_RESETTMR + 0x0090) /* revision */ ++ ++/* AR531X_WD_CTRL register bit field definitions */ ++#define AR531X_WD_CTRL_IGNORE_EXPIRATION 0x0000 ++#define AR531X_WD_CTRL_NMI 0x0001 ++#define AR531X_WD_CTRL_RESET 0x0002 ++ ++/* AR531X_ISR register bit field definitions */ ++#define AR531X_ISR_NONE 0x0000 ++#define AR531X_ISR_TIMER 0x0001 ++#define AR531X_ISR_AHBPROC 0x0002 ++#define AR531X_ISR_AHBDMA 0x0004 ++#define AR531X_ISR_GPIO 0x0008 ++#define AR531X_ISR_UART0 0x0010 ++#define AR531X_ISR_UART0DMA 0x0020 ++#define AR531X_ISR_WD 0x0040 ++#define AR531X_ISR_LOCAL 0x0080 ++ ++/* AR531X_RESET register bit field definitions */ ++#define AR531X_RESET_SYSTEM 0x00000001 /* cold reset full system */ ++#define AR531X_RESET_PROC 0x00000002 /* cold reset MIPS core */ ++#define AR531X_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */ ++#define AR531X_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */ ++#define AR531X_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */ ++#define AR531X_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */ ++#define AR531X_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */ ++#define AR531X_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */ ++#define AR531X_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */ ++#define AR531X_RESET_APB 0x00000400 /* cold reset APB (ar5312) */ ++#define AR531X_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */ ++#define AR531X_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */ ++#define AR531X_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */ ++#define AR531X_RESET_NMI 0x00010000 /* send an NMI to the processor */ ++#define AR531X_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */ ++#define AR531X_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */ ++#define AR531X_RESET_LOCAL_BUS 0x00080000 /* reset local bus */ ++#define AR531X_RESET_WDOG 0x00100000 /* last reset was a watchdog */ ++ ++#define AR531X_RESET_WMAC0_BITS \ ++ AR531X_RESET_WLAN0 |\ ++ AR531X_RESET_WARM_WLAN0_MAC |\ ++ AR531X_RESET_WARM_WLAN0_BB ++ ++#define AR531X_RESERT_WMAC1_BITS \ ++ AR531X_RESET_WLAN1 |\ ++ AR531X_RESET_WARM_WLAN1_MAC |\ ++ AR531X_RESET_WARM_WLAN1_BB ++ ++/* AR5312_CLOCKCTL1 register bit field definitions */ ++#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030 ++#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4 ++#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00 ++#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8 ++#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000 ++ ++/* Valid for AR5312 and AR2312 */ ++#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030 ++#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4 ++#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00 ++#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8 ++#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000 ++ ++/* Valid for AR2313 */ ++#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000 ++#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12 ++#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000 ++#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16 ++#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000 ++ ++ ++/* AR531X_ENABLE register bit field definitions */ ++#define AR531X_ENABLE_WLAN0 0x0001 ++#define AR531X_ENABLE_ENET0 0x0002 ++#define AR531X_ENABLE_ENET1 0x0004 ++#define AR531X_ENABLE_UART_AND_WLAN1_PIO 0x0008 /* UART, and WLAN1 PIOs */ ++#define AR531X_ENABLE_WLAN1_DMA 0x0010 /* WLAN1 DMAs */ ++#define AR531X_ENABLE_WLAN1 \ ++ (AR531X_ENABLE_UART_AND_WLAN1_PIO | AR531X_ENABLE_WLAN1_DMA) ++ ++/* AR531X_REV register bit field definitions */ ++#define AR531X_REV_WMAC_MAJ 0xf000 ++#define AR531X_REV_WMAC_MAJ_S 12 ++#define AR531X_REV_WMAC_MIN 0x0f00 ++#define AR531X_REV_WMAC_MIN_S 8 ++#define AR531X_REV_MAJ 0x00f0 ++#define AR531X_REV_MAJ_S 4 ++#define AR531X_REV_MIN 0x000f ++#define AR531X_REV_MIN_S 0 ++#define AR531X_REV_CHIP (AR531X_REV_MAJ|AR531X_REV_MIN) ++ ++/* Major revision numbers, bits 7..4 of Revision ID register */ ++#define AR531X_REV_MAJ_AR5312 0x4 ++#define AR531X_REV_MAJ_AR2313 0x5 ++ ++/* Minor revision numbers, bits 3..0 of Revision ID register */ ++#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */ ++#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */ ++ ++/* AR531X_FLASHCTL register bit field definitions */ ++#define FLASHCTL_IDCY 0x0000000f /* Idle cycle turn around time */ ++#define FLASHCTL_IDCY_S 0 ++#define FLASHCTL_WST1 0x000003e0 /* Wait state 1 */ ++#define FLASHCTL_WST1_S 5 ++#define FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */ ++#define FLASHCTL_WST2 0x0000f800 /* Wait state 2 */ ++#define FLASHCTL_WST2_S 11 ++#define FLASHCTL_AC 0x00070000 /* Flash address check (added) */ ++#define FLASHCTL_AC_S 16 ++#define FLASHCTL_AC_128K 0x00000000 ++#define FLASHCTL_AC_256K 0x00010000 ++#define FLASHCTL_AC_512K 0x00020000 ++#define FLASHCTL_AC_1M 0x00030000 ++#define FLASHCTL_AC_2M 0x00040000 ++#define FLASHCTL_AC_4M 0x00050000 ++#define FLASHCTL_AC_8M 0x00060000 ++#define FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */ ++#define FLASHCTL_E 0x00080000 /* Flash bank enable (added) */ ++#define FLASHCTL_BUSERR 0x01000000 /* Bus transfer error status flag */ ++#define FLASHCTL_WPERR 0x02000000 /* Write protect error status flag */ ++#define FLASHCTL_WP 0x04000000 /* Write protect */ ++#define FLASHCTL_BM 0x08000000 /* Burst mode */ ++#define FLASHCTL_MW 0x30000000 /* Memory width */ ++#define FLASHCTL_MWx8 0x00000000 /* Memory width x8 */ ++#define FLASHCTL_MWx16 0x10000000 /* Memory width x16 */ ++#define FLASHCTL_MWx32 0x20000000 /* Memory width x32 (not supported) */ ++#define FLASHCTL_ATNR 0x00000000 /* Access type == no retry */ ++#define FLASHCTL_ATR 0x80000000 /* Access type == retry every */ ++#define FLASHCTL_ATR4 0xc0000000 /* Access type == retry every 4 */ ++ ++/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */ ++#define AR531X_FLASHCTL0 (AR531X_FLASHCTL + 0x00) ++#define AR531X_FLASHCTL1 (AR531X_FLASHCTL + 0x04) ++#define AR531X_FLASHCTL2 (AR531X_FLASHCTL + 0x08) ++ ++/* ARM SDRAM Controller -- just enough to determine memory size */ ++#define AR531X_MEM_CFG1 (AR531X_SDRAMCTL + 0x04) ++#define MEM_CFG1_AC0 0x00000700 /* bank 0: SDRAM addr check (added) */ ++#define MEM_CFG1_AC0_S 8 ++#define MEM_CFG1_AC1 0x00007000 /* bank 1: SDRAM addr check (added) */ ++#define MEM_CFG1_AC1_S 12 ++ ++/* GPIO Address Map */ ++#define AR531X_GPIO (AR531X_APBBASE + 0x2000) ++#define AR531X_GPIO_DO (AR531X_GPIO + 0x00) /* output register */ ++#define AR531X_GPIO_DI (AR531X_GPIO + 0x04) /* intput register */ ++#define AR531X_GPIO_CR (AR531X_GPIO + 0x08) /* control register */ ++ ++/* GPIO Control Register bit field definitions */ ++#define AR531X_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */ ++#define AR531X_GPIO_CR_O(x) (0 << (x)) /* mask for output */ ++#define AR531X_GPIO_CR_I(x) (1 << (x)) /* mask for input */ ++#define AR531X_GPIO_CR_INT(x) (1 << ((x)+8)) /* mask for interrupt */ ++#define AR531X_GPIO_CR_UART(x) (1 << ((x)+16)) /* uart multiplex */ ++#define AR531X_NUM_GPIO 8 ++ ++ ++#endif ++ +diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h +--- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,84 @@ ++/* ++ * Atheros SoC specific CPU feature overrides ++ * ++ * Copyright (C) 2008 Gabor Juhos ++ * ++ * This file was derived from: include/asm-mips/cpu-features.h ++ * Copyright (C) 2003, 2004 Ralf Baechle ++ * Copyright (C) 2004 Maciej W. Rozycki ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ */ ++#ifndef __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H ++#define __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H ++ ++/* ++ * The ATHEROS SoCs have MIPS 4Kc/4KEc core. ++ */ ++#define cpu_has_tlb 1 ++#define cpu_has_4kex 1 ++#define cpu_has_3k_cache 0 ++#define cpu_has_4k_cache 1 ++#define cpu_has_tx39_cache 0 ++#define cpu_has_sb1_cache 0 ++#define cpu_has_fpu 0 ++#define cpu_has_32fpr 0 ++#define cpu_has_counter 1 ++/* #define cpu_has_watch ? */ ++/* #define cpu_has_divec ? */ ++/* #define cpu_has_vce ? */ ++/* #define cpu_has_cache_cdex_p ? */ ++/* #define cpu_has_cache_cdex_s ? */ ++/* #define cpu_has_prefetch ? */ ++/* #define cpu_has_mcheck ? */ ++#define cpu_has_ejtag 1 ++ ++#if !defined(CONFIG_ATHEROS_AR5312) ++# define cpu_has_llsc 1 ++#else ++/* ++ * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the ++ * ll/sc instructions. ++ */ ++# define cpu_has_llsc 0 ++#endif ++ ++#define cpu_has_mips16 0 ++#define cpu_has_mdmx 0 ++#define cpu_has_mips3d 0 ++#define cpu_has_smartmips 0 ++ ++/* #define cpu_has_vtag_icache ? */ ++/* #define cpu_has_dc_aliases ? */ ++/* #define cpu_has_ic_fills_f_dc ? */ ++/* #define cpu_has_pindexed_dcache ? */ ++ ++/* #define cpu_icache_snoops_remote_store ? */ ++ ++#define cpu_has_mips32r1 1 ++ ++#if !defined(CONFIG_ATHEROS_AR5312) ++# define cpu_has_mips32r2 1 ++#endif ++ ++#define cpu_has_mips64r1 0 ++#define cpu_has_mips64r2 0 ++ ++#define cpu_has_dsp 0 ++#define cpu_has_mipsmt 0 ++ ++/* #define cpu_has_nofpuex ? */ ++#define cpu_has_64bits 0 ++#define cpu_has_64bit_zero_reg 0 ++#define cpu_has_64bit_gp_regs 0 ++#define cpu_has_64bit_addresses 0 ++ ++/* #define cpu_has_inclusive_pcaches ? */ ++ ++/* #define cpu_dcache_line_size() ? */ ++/* #define cpu_icache_line_size() ? */ ++ ++#endif /* __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H */ +diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/dma-coherence.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/dma-coherence.h +--- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/dma-coherence.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/dma-coherence.h 2011-05-15 21:41:19.000000000 +0200 +@@ -0,0 +1,76 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2006 Ralf Baechle ++ * Copyright (C) 2007 Felix Fietkau ++ * ++ */ ++#ifndef __ASM_MACH_GENERIC_DMA_COHERENCE_H ++#define __ASM_MACH_GENERIC_DMA_COHERENCE_H ++ ++#define PCI_DMA_OFFSET 0x20000000 ++ ++#include ++ ++static inline dma_addr_t ar231x_dev_offset(struct device *dev) ++{ ++#ifdef CONFIG_PCI ++ extern struct bus_type pci_bus_type; ++ ++ if (dev && dev->bus == &pci_bus_type) ++ return PCI_DMA_OFFSET; ++ else ++#endif ++ return 0; ++} ++ ++static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size) ++{ ++ return virt_to_phys(addr) + ar231x_dev_offset(dev); ++} ++ ++static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page) ++{ ++ return page_to_phys(page) + ar231x_dev_offset(dev); ++} ++ ++static inline unsigned long plat_dma_addr_to_phys(struct device *dev, ++ dma_addr_t dma_addr) ++{ ++ return dma_addr - ar231x_dev_offset(dev); ++} ++ ++static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, ++ size_t size, enum dma_data_direction direction) ++{ ++} ++ ++static inline int plat_dma_supported(struct device *dev, u64 mask) ++{ ++ return 1; ++} ++ ++static inline void plat_extra_sync_for_device(struct device *dev) ++{ ++ return; ++} ++ ++static inline int plat_dma_mapping_error(struct device *dev, ++ dma_addr_t dma_addr) ++{ ++ return 0; ++} ++ ++static inline int plat_device_is_coherent(struct device *dev) ++{ ++#ifdef CONFIG_DMA_COHERENT ++ return 1; ++#endif ++#ifdef CONFIG_DMA_NONCOHERENT ++ return 0; ++#endif ++} ++ ++#endif /* __ASM_MACH_GENERIC_DMA_COHERENCE_H */ +diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/gpio.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/gpio.h +--- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/gpio.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/gpio.h 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,84 @@ ++#ifndef _ATHEROS_GPIO_H_ ++#define _ATHEROS_GPIO_H_ ++ ++#include ++ ++struct ar231x_gpiodev { ++ u32 valid_mask; ++ u32 (*get_output)(void); ++ u32 (*set_output)(u32 mask, u32 val); ++ u32 (*get)(void); ++ u32 (*set)(u32 mask, u32 val); ++}; ++ ++extern const struct ar231x_gpiodev *ar231x_gpiodev; ++ ++/* ++ * Wrappers for the generic GPIO layer ++ */ ++ ++static inline int gpio_direction_input(unsigned gpio) { ++ u32 mask = 1 << gpio; ++ ++ if (!(ar231x_gpiodev->valid_mask & mask)) ++ return -ENXIO; ++ ++ ar231x_gpiodev->set_output(mask, 0); ++ return 0; ++} ++ ++static inline void gpio_set_value(unsigned gpio, int value) { ++ u32 mask = 1 << gpio; ++ ++ if (!(ar231x_gpiodev->valid_mask & mask)) ++ return; ++ ++ ar231x_gpiodev->set(mask, (!!value) * mask); ++} ++ ++static inline int gpio_direction_output(unsigned gpio, int value) { ++ u32 mask = 1 << gpio; ++ ++ if (!(ar231x_gpiodev->valid_mask & mask)) ++ return -ENXIO; ++ ++ ar231x_gpiodev->set_output(mask, mask); ++ ar231x_gpiodev->set(mask, (!!value) * mask); ++ return 0; ++} ++ ++/* Reads the gpio pin. Unchecked function */ ++static inline int gpio_get_value(unsigned gpio) { ++ u32 mask = 1 << gpio; ++ ++ if (!(ar231x_gpiodev->valid_mask & mask)) ++ return 0; ++ ++ return !!(ar231x_gpiodev->get() & mask); ++} ++ ++static inline int gpio_request(unsigned gpio, const char *label) { ++ return 0; ++} ++ ++static inline void gpio_free(unsigned gpio) { ++} ++ ++/* Returns IRQ to attach for gpio. Unchecked function */ ++static inline int gpio_to_irq(unsigned gpio) { ++ return AR531X_GPIO_IRQ(gpio); ++} ++ ++/* Returns gpio for IRQ attached. Unchecked function */ ++static inline int irq_to_gpio(unsigned irq) { ++ return (irq - (AR531X_GPIO_IRQ(0))); ++} ++ ++static inline int gpio_set_debounce(unsigned gpio, unsigned debounce) ++{ ++ return -ENOSYS; ++} ++ ++#include /* cansleep wrappers */ ++ ++#endif +diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/reset.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/reset.h +--- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/reset.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/reset.h 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,6 @@ ++#ifndef __AR531X_RESET_H ++#define __AR531X_RESET_H ++ ++void ar531x_disable_reset_button(void); ++ ++#endif /* __AR531X_RESET_H */ +diff -Nur linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/war.h linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/war.h +--- linux-2.6.39-rc7.orig/arch/mips/include/asm/mach-ar231x/war.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/arch/mips/include/asm/mach-ar231x/war.h 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,25 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2008 Felix Fietkau ++ */ ++#ifndef __ASM_MIPS_MACH_ATHEROS_WAR_H ++#define __ASM_MIPS_MACH_ATHEROS_WAR_H ++ ++#define R4600_V1_INDEX_ICACHEOP_WAR 0 ++#define R4600_V1_HIT_CACHEOP_WAR 0 ++#define R4600_V2_HIT_CACHEOP_WAR 0 ++#define R5432_CP0_INTERRUPT_WAR 0 ++#define BCM1250_M3_WAR 0 ++#define SIBYTE_1956_WAR 0 ++#define MIPS4K_ICACHE_REFILL_WAR 0 ++#define MIPS_CACHE_SYNC_WAR 0 ++#define TX49XX_ICACHE_INDEX_INV_WAR 0 ++#define RM9000_CDEX_SMP_WAR 0 ++#define ICACHE_REFILLS_WORKAROUND_WAR 0 ++#define R10000_LLSC_WAR 0 ++#define MIPS34K_MISSED_ITLB_WAR 0 ++ ++#endif /* __ASM_MIPS_MACH_ATHEROS_WAR_H */ +diff -Nur linux-2.6.39-rc7.orig/arch/mips/kernel/cevt-r4k.c linux-2.6.39-rc7/arch/mips/kernel/cevt-r4k.c +--- linux-2.6.39-rc7.orig/arch/mips/kernel/cevt-r4k.c 2011-05-10 04:33:54.000000000 +0200 ++++ linux-2.6.39-rc7/arch/mips/kernel/cevt-r4k.c 2011-05-15 21:34:57.000000000 +0200 +@@ -168,20 +168,23 @@ + struct clock_event_device *cd; + unsigned int irq; + +- if (!cpu_has_counter || !mips_hpt_frequency) +- return -ENXIO; +- +- if (!c0_compare_int_usable()) +- return -ENXIO; +- + /* + * With vectored interrupts things are getting platform specific. + * get_c0_compare_int is a hook to allow a platform to return the + * interrupt number of it's liking. + */ + irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; +- if (get_c0_compare_int) ++ if (get_c0_compare_int) { + irq = get_c0_compare_int(); ++ if ((irq >= MIPS_CPU_IRQ_BASE) && (irq < MIPS_CPU_IRQ_BASE + 8)) ++ cp0_compare_irq = irq - MIPS_CPU_IRQ_BASE; ++ } ++ ++ if (!cpu_has_counter || !mips_hpt_frequency) ++ return -ENXIO; ++ ++ if (!c0_compare_int_usable()) ++ return -ENXIO; + + cd = &per_cpu(mips_clockevent_device, cpu); + +diff -Nur linux-2.6.39-rc7.orig/drivers/mtd/devices/Kconfig linux-2.6.39-rc7/drivers/mtd/devices/Kconfig +--- linux-2.6.39-rc7.orig/drivers/mtd/devices/Kconfig 2011-05-10 04:33:54.000000000 +0200 ++++ linux-2.6.39-rc7/drivers/mtd/devices/Kconfig 2011-05-15 21:34:57.000000000 +0200 +@@ -112,6 +112,10 @@ + Set up your spi devices with the right board-specific platform data, + if you want to specify device partitioning. + ++config MTD_AR2315 ++ tristate "Atheros AR2315+ SPI Flash support" ++ depends on ATHEROS_AR2315 ++ + config MTD_SLRAM + tristate "Uncached system RAM" + help +diff -Nur linux-2.6.39-rc7.orig/drivers/mtd/devices/Makefile linux-2.6.39-rc7/drivers/mtd/devices/Makefile +--- linux-2.6.39-rc7.orig/drivers/mtd/devices/Makefile 2011-05-10 04:33:54.000000000 +0200 ++++ linux-2.6.39-rc7/drivers/mtd/devices/Makefile 2011-05-15 21:34:57.000000000 +0200 +@@ -17,3 +17,4 @@ + obj-$(CONFIG_MTD_DATAFLASH) += mtd_dataflash.o + obj-$(CONFIG_MTD_M25P80) += m25p80.o + obj-$(CONFIG_MTD_SST25L) += sst25l.o ++obj-$(CONFIG_MTD_AR2315) += ar2315.o +diff -Nur linux-2.6.39-rc7.orig/drivers/mtd/devices/ar2315.c linux-2.6.39-rc7/drivers/mtd/devices/ar2315.c +--- linux-2.6.39-rc7.orig/drivers/mtd/devices/ar2315.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/drivers/mtd/devices/ar2315.c 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,517 @@ ++ ++/* ++ * MTD driver for the SPI Flash Memory support on Atheros AR2315 ++ * ++ * Copyright (c) 2005-2006 Atheros Communications Inc. ++ * Copyright (C) 2006-2007 FON Technology, SL. ++ * Copyright (C) 2006-2007 Imre Kaloz ++ * Copyright (C) 2006-2009 Felix Fietkau ++ * ++ * This code is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++ ++#define SPIFLASH "spiflash: " ++#define busy_wait(_priv, _condition, _wait) do { \ ++ while (_condition) { \ ++ spin_unlock_bh(&_priv->lock); \ ++ if (_wait > 1) \ ++ msleep(_wait); \ ++ else if ((_wait == 1) && need_resched()) \ ++ schedule(); \ ++ else \ ++ udelay(1); \ ++ spin_lock_bh(&_priv->lock); \ ++ } \ ++} while (0) ++ ++enum { ++ FLASH_NONE, ++ FLASH_1MB, ++ FLASH_2MB, ++ FLASH_4MB, ++ FLASH_8MB, ++ FLASH_16MB, ++}; ++ ++/* Flash configuration table */ ++struct flashconfig { ++ u32 byte_cnt; ++ u32 sector_cnt; ++ u32 sector_size; ++}; ++ ++const struct flashconfig flashconfig_tbl[] = { ++ [FLASH_NONE] = { 0, 0, 0}, ++ [FLASH_1MB] = { STM_1MB_BYTE_COUNT, STM_1MB_SECTOR_COUNT, STM_1MB_SECTOR_SIZE}, ++ [FLASH_2MB] = { STM_2MB_BYTE_COUNT, STM_2MB_SECTOR_COUNT, STM_2MB_SECTOR_SIZE}, ++ [FLASH_4MB] = { STM_4MB_BYTE_COUNT, STM_4MB_SECTOR_COUNT, STM_4MB_SECTOR_SIZE}, ++ [FLASH_8MB] = { STM_8MB_BYTE_COUNT, STM_8MB_SECTOR_COUNT, STM_8MB_SECTOR_SIZE}, ++ [FLASH_16MB] = { STM_16MB_BYTE_COUNT, STM_16MB_SECTOR_COUNT, STM_16MB_SECTOR_SIZE} ++}; ++ ++/* Mapping of generic opcodes to STM serial flash opcodes */ ++enum { ++ SPI_WRITE_ENABLE, ++ SPI_WRITE_DISABLE, ++ SPI_RD_STATUS, ++ SPI_WR_STATUS, ++ SPI_RD_DATA, ++ SPI_FAST_RD_DATA, ++ SPI_PAGE_PROGRAM, ++ SPI_SECTOR_ERASE, ++ SPI_BULK_ERASE, ++ SPI_DEEP_PWRDOWN, ++ SPI_RD_SIG, ++}; ++ ++struct opcodes { ++ __u16 code; ++ __s8 tx_cnt; ++ __s8 rx_cnt; ++}; ++const struct opcodes stm_opcodes[] = { ++ [SPI_WRITE_ENABLE] = {STM_OP_WR_ENABLE, 1, 0}, ++ [SPI_WRITE_DISABLE] = {STM_OP_WR_DISABLE, 1, 0}, ++ [SPI_RD_STATUS] = {STM_OP_RD_STATUS, 1, 1}, ++ [SPI_WR_STATUS] = {STM_OP_WR_STATUS, 1, 0}, ++ [SPI_RD_DATA] = {STM_OP_RD_DATA, 4, 4}, ++ [SPI_FAST_RD_DATA] = {STM_OP_FAST_RD_DATA, 5, 0}, ++ [SPI_PAGE_PROGRAM] = {STM_OP_PAGE_PGRM, 8, 0}, ++ [SPI_SECTOR_ERASE] = {STM_OP_SECTOR_ERASE, 4, 0}, ++ [SPI_BULK_ERASE] = {STM_OP_BULK_ERASE, 1, 0}, ++ [SPI_DEEP_PWRDOWN] = {STM_OP_DEEP_PWRDOWN, 1, 0}, ++ [SPI_RD_SIG] = {STM_OP_RD_SIG, 4, 1}, ++}; ++ ++/* Driver private data structure */ ++struct spiflash_priv { ++ struct mtd_info mtd; ++ void *readaddr; /* memory mapped data for read */ ++ void *mmraddr; /* memory mapped register space */ ++ wait_queue_head_t wq; ++ spinlock_t lock; ++ int state; ++}; ++ ++#define to_spiflash(_mtd) container_of(_mtd, struct spiflash_priv, mtd) ++ ++enum { ++ FL_READY, ++ FL_READING, ++ FL_ERASING, ++ FL_WRITING ++}; ++ ++/***************************************************************************************************/ ++ ++static u32 ++spiflash_read_reg(struct spiflash_priv *priv, int reg) ++{ ++ return ar231x_read_reg((u32) priv->mmraddr + reg); ++} ++ ++static void ++spiflash_write_reg(struct spiflash_priv *priv, int reg, u32 data) ++{ ++ ar231x_write_reg((u32) priv->mmraddr + reg, data); ++} ++ ++static u32 ++spiflash_wait_busy(struct spiflash_priv *priv) ++{ ++ u32 reg; ++ ++ busy_wait(priv, (reg = spiflash_read_reg(priv, SPI_FLASH_CTL)) & ++ SPI_CTL_BUSY, 0); ++ return reg; ++} ++ ++static u32 ++spiflash_sendcmd (struct spiflash_priv *priv, int opcode, u32 addr) ++{ ++ const struct opcodes *op; ++ u32 reg, mask; ++ ++ op = &stm_opcodes[opcode]; ++ reg = spiflash_wait_busy(priv); ++ spiflash_write_reg(priv, SPI_FLASH_OPCODE, ++ ((u32) op->code) | (addr << 8)); ++ ++ reg &= ~SPI_CTL_TX_RX_CNT_MASK; ++ reg |= SPI_CTL_START | op->tx_cnt | (op->rx_cnt << 4); ++ ++ spiflash_write_reg(priv, SPI_FLASH_CTL, reg); ++ spiflash_wait_busy(priv); ++ ++ if (!op->rx_cnt) ++ return 0; ++ ++ reg = spiflash_read_reg(priv, SPI_FLASH_DATA); ++ ++ switch (op->rx_cnt) { ++ case 1: ++ mask = 0x000000ff; ++ break; ++ case 2: ++ mask = 0x0000ffff; ++ break; ++ case 3: ++ mask = 0x00ffffff; ++ break; ++ default: ++ mask = 0xffffffff; ++ break; ++ } ++ reg &= mask; ++ ++ return reg; ++} ++ ++ ++/* ++ * Probe SPI flash device ++ * Function returns 0 for failure. ++ * and flashconfig_tbl array index for success. ++ */ ++static int ++spiflash_probe_chip (struct spiflash_priv *priv) ++{ ++ u32 sig; ++ int flash_size; ++ ++ /* Read the signature on the flash device */ ++ spin_lock_bh(&priv->lock); ++ sig = spiflash_sendcmd(priv, SPI_RD_SIG, 0); ++ spin_unlock_bh(&priv->lock); ++ ++ switch (sig) { ++ case STM_8MBIT_SIGNATURE: ++ flash_size = FLASH_1MB; ++ break; ++ case STM_16MBIT_SIGNATURE: ++ flash_size = FLASH_2MB; ++ break; ++ case STM_32MBIT_SIGNATURE: ++ flash_size = FLASH_4MB; ++ break; ++ case STM_64MBIT_SIGNATURE: ++ flash_size = FLASH_8MB; ++ break; ++ case STM_128MBIT_SIGNATURE: ++ flash_size = FLASH_16MB; ++ break; ++ default: ++ printk (KERN_WARNING SPIFLASH "Read of flash device signature failed!\n"); ++ return 0; ++ } ++ ++ return flash_size; ++} ++ ++ ++/* wait until the flash chip is ready and grab a lock */ ++static int spiflash_wait_ready(struct spiflash_priv *priv, int state) ++{ ++ DECLARE_WAITQUEUE(wait, current); ++ ++retry: ++ spin_lock_bh(&priv->lock); ++ if (priv->state != FL_READY) { ++ set_current_state(TASK_UNINTERRUPTIBLE); ++ add_wait_queue(&priv->wq, &wait); ++ spin_unlock_bh(&priv->lock); ++ schedule(); ++ remove_wait_queue(&priv->wq, &wait); ++ ++ if(signal_pending(current)) ++ return 0; ++ ++ goto retry; ++ } ++ priv->state = state; ++ ++ return 1; ++} ++ ++static inline void spiflash_done(struct spiflash_priv *priv) ++{ ++ priv->state = FL_READY; ++ spin_unlock_bh(&priv->lock); ++ wake_up(&priv->wq); ++} ++ ++static void ++spiflash_wait_complete(struct spiflash_priv *priv, unsigned int timeout) ++{ ++ busy_wait(priv, spiflash_sendcmd(priv, SPI_RD_STATUS, 0) & ++ SPI_STATUS_WIP, timeout); ++ spiflash_done(priv); ++} ++ ++ ++ ++static int ++spiflash_erase (struct mtd_info *mtd, struct erase_info *instr) ++{ ++ struct spiflash_priv *priv = to_spiflash(mtd); ++ const struct opcodes *op; ++ u32 temp, reg; ++ ++ if (instr->addr + instr->len > mtd->size) ++ return -EINVAL; ++ ++ if (!spiflash_wait_ready(priv, FL_ERASING)) ++ return -EINTR; ++ ++ spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0); ++ reg = spiflash_wait_busy(priv); ++ ++ op = &stm_opcodes[SPI_SECTOR_ERASE]; ++ temp = ((u32)instr->addr << 8) | (u32)(op->code); ++ spiflash_write_reg(priv, SPI_FLASH_OPCODE, temp); ++ ++ reg &= ~SPI_CTL_TX_RX_CNT_MASK; ++ reg |= op->tx_cnt | SPI_CTL_START; ++ spiflash_write_reg(priv, SPI_FLASH_CTL, reg); ++ ++ spiflash_wait_complete(priv, 20); ++ ++ instr->state = MTD_ERASE_DONE; ++ mtd_erase_callback(instr); ++ ++ return 0; ++} ++ ++static int ++spiflash_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf) ++{ ++ struct spiflash_priv *priv = to_spiflash(mtd); ++ u8 *read_addr; ++ ++ if (!len) ++ return 0; ++ ++ if (from + len > mtd->size) ++ return -EINVAL; ++ ++ *retlen = len; ++ ++ if (!spiflash_wait_ready(priv, FL_READING)) ++ return -EINTR; ++ ++ read_addr = (u8 *)(priv->readaddr + from); ++ memcpy_fromio(buf, read_addr, len); ++ spiflash_done(priv); ++ ++ return 0; ++} ++ ++static int ++spiflash_write (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u8 *buf) ++{ ++ struct spiflash_priv *priv = to_spiflash(mtd); ++ u32 opcode, bytes_left; ++ ++ *retlen = 0; ++ ++ if (!len) ++ return 0; ++ ++ if (to + len > mtd->size) ++ return -EINVAL; ++ ++ bytes_left = len; ++ ++ do { ++ u32 read_len, reg, page_offset, spi_data = 0; ++ ++ read_len = min(bytes_left, sizeof(u32)); ++ ++ /* 32-bit writes cannot span across a page boundary ++ * (256 bytes). This types of writes require two page ++ * program operations to handle it correctly. The STM part ++ * will write the overflow data to the beginning of the ++ * current page as opposed to the subsequent page. ++ */ ++ page_offset = (to & (STM_PAGE_SIZE - 1)) + read_len; ++ ++ if (page_offset > STM_PAGE_SIZE) ++ read_len -= (page_offset - STM_PAGE_SIZE); ++ ++ if (!spiflash_wait_ready(priv, FL_WRITING)) ++ return -EINTR; ++ ++ spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0); ++ spi_data = 0; ++ switch (read_len) { ++ case 4: ++ spi_data |= buf[3] << 24; ++ /* fall through */ ++ case 3: ++ spi_data |= buf[2] << 16; ++ /* fall through */ ++ case 2: ++ spi_data |= buf[1] << 8; ++ /* fall through */ ++ case 1: ++ spi_data |= buf[0] & 0xff; ++ break; ++ default: ++ break; ++ } ++ ++ spiflash_write_reg(priv, SPI_FLASH_DATA, spi_data); ++ opcode = stm_opcodes[SPI_PAGE_PROGRAM].code | ++ (to & 0x00ffffff) << 8; ++ spiflash_write_reg(priv, SPI_FLASH_OPCODE, opcode); ++ ++ reg = spiflash_read_reg(priv, SPI_FLASH_CTL); ++ reg &= ~SPI_CTL_TX_RX_CNT_MASK; ++ reg |= (read_len + 4) | SPI_CTL_START; ++ spiflash_write_reg(priv, SPI_FLASH_CTL, reg); ++ ++ spiflash_wait_complete(priv, 1); ++ ++ bytes_left -= read_len; ++ to += read_len; ++ buf += read_len; ++ ++ *retlen += read_len; ++ } while (bytes_left != 0); ++ ++ return 0; ++} ++ ++ ++#ifdef CONFIG_MTD_PARTITIONS ++static const char *part_probe_types[] = { "cmdlinepart", "RedBoot", "MyLoader", NULL }; ++#endif ++ ++ ++static int ++spiflash_probe(struct platform_device *pdev) ++{ ++ struct spiflash_priv *priv; ++ struct mtd_partition *parts; ++ struct mtd_info *mtd; ++ int index, num_parts; ++ int result = 0; ++ ++ priv = kzalloc(sizeof(struct spiflash_priv), GFP_KERNEL); ++ spin_lock_init(&priv->lock); ++ init_waitqueue_head(&priv->wq); ++ priv->state = FL_READY; ++ mtd = &priv->mtd; ++ ++ priv->mmraddr = ioremap_nocache(SPI_FLASH_MMR, SPI_FLASH_MMR_SIZE); ++ if (!priv->mmraddr) { ++ printk(KERN_WARNING SPIFLASH "Failed to map flash device\n"); ++ goto error; ++ } ++ ++ index = spiflash_probe_chip(priv); ++ if (!index) { ++ printk (KERN_WARNING SPIFLASH "Found no serial flash device\n"); ++ goto error; ++ } ++ ++ priv->readaddr = ioremap_nocache(SPI_FLASH_READ, flashconfig_tbl[index].byte_cnt); ++ if (!priv->readaddr) { ++ printk (KERN_WARNING SPIFLASH "Failed to map flash device\n"); ++ goto error; ++ } ++ ++ platform_set_drvdata(pdev, priv); ++ mtd->name = "spiflash"; ++ mtd->type = MTD_NORFLASH; ++ mtd->flags = (MTD_CAP_NORFLASH|MTD_WRITEABLE); ++ mtd->size = flashconfig_tbl[index].byte_cnt; ++ mtd->erasesize = flashconfig_tbl[index].sector_size; ++ mtd->writesize = 1; ++ mtd->numeraseregions = 0; ++ mtd->eraseregions = NULL; ++ mtd->erase = spiflash_erase; ++ mtd->read = spiflash_read; ++ mtd->write = spiflash_write; ++ mtd->owner = THIS_MODULE; ++ ++#ifdef CONFIG_MTD_PARTITIONS ++ /* parse redboot partitions */ ++ num_parts = parse_mtd_partitions(mtd, part_probe_types, &parts, 0); ++ if (!num_parts) ++ goto error; ++ ++ result = add_mtd_partitions(mtd, parts, num_parts); ++#endif ++ ++ return result; ++ ++error: ++ if (priv->mmraddr) ++ iounmap(priv->mmraddr); ++ kfree(priv); ++ return -ENXIO; ++} ++ ++static int ++spiflash_remove (struct platform_device *pdev) ++{ ++ struct spiflash_priv *priv = platform_get_drvdata(pdev); ++ struct mtd_info *mtd = &priv->mtd; ++ ++ del_mtd_partitions(mtd); ++ iounmap(priv->mmraddr); ++ iounmap(priv->readaddr); ++ kfree(priv); ++ ++ return 0; ++} ++ ++struct platform_driver spiflash_driver = { ++ .driver.name = "spiflash", ++ .probe = spiflash_probe, ++ .remove = spiflash_remove, ++}; ++ ++int __init ++spiflash_init (void) ++{ ++ return platform_driver_register(&spiflash_driver); ++} ++ ++void __exit ++spiflash_exit (void) ++{ ++ return platform_driver_unregister(&spiflash_driver); ++} ++ ++module_init (spiflash_init); ++module_exit (spiflash_exit); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("OpenWrt.org, Atheros Communications Inc"); ++MODULE_DESCRIPTION("MTD driver for SPI Flash on Atheros SOC"); ++ +diff -Nur linux-2.6.39-rc7.orig/drivers/mtd/redboot.c linux-2.6.39-rc7/drivers/mtd/redboot.c +--- linux-2.6.39-rc7.orig/drivers/mtd/redboot.c 2011-05-10 04:33:54.000000000 +0200 ++++ linux-2.6.39-rc7/drivers/mtd/redboot.c 2011-05-15 21:34:57.000000000 +0200 +@@ -55,6 +55,22 @@ + return 1; + } + ++static uint32_t mtd_get_offset_erasesize(struct mtd_info *mtd, uint64_t offset) ++{ ++ struct mtd_erase_region_info *regions = mtd->eraseregions; ++ int i; ++ ++ for (i = 0; i < mtd->numeraseregions; i++) { ++ if (regions[i].offset + ++ regions[i].numblocks * regions[i].erasesize <= offset) ++ continue; ++ ++ return regions[i].erasesize; ++ } ++ ++ return mtd->erasesize; ++} ++ + static int parse_redboot_partitions(struct mtd_info *master, + struct mtd_partition **pparts, + unsigned long fis_origin) +@@ -70,36 +86,38 @@ + int namelen = 0; + int nulllen = 0; + int numslots; ++ int first_slot; + unsigned long offset; + #ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED + static char nullstring[] = "unallocated"; + #endif + ++ buf = vmalloc(master->erasesize); ++ if (!buf) ++ return -ENOMEM; ++ ++ restart: + if ( directory < 0 ) { + offset = master->size + directory * master->erasesize; +- while (master->block_isbad && ++ while (master->block_isbad && + master->block_isbad(master, offset)) { + if (!offset) { + nogood: + printk(KERN_NOTICE "Failed to find a non-bad block to check for RedBoot partition table\n"); ++ vfree(buf); + return -EIO; + } + offset -= master->erasesize; + } + } else { + offset = directory * master->erasesize; +- while (master->block_isbad && ++ while (master->block_isbad && + master->block_isbad(master, offset)) { + offset += master->erasesize; + if (offset == master->size) + goto nogood; + } + } +- buf = vmalloc(master->erasesize); +- +- if (!buf) +- return -ENOMEM; +- + printk(KERN_NOTICE "Searching for RedBoot partition table in %s at offset 0x%lx\n", + master->name, offset); + +@@ -171,13 +189,21 @@ + } + if (i == numslots) { + /* Didn't find it */ ++ if (offset + master->erasesize < master->size) { ++ /* not at the end of the flash yet, maybe next block :) */ ++ directory++; ++ goto restart; ++ } + printk(KERN_NOTICE "No RedBoot partition table detected in %s\n", + master->name); + ret = 0; + goto out; + } + +- for (i = 0; i < numslots; i++) { ++ first_slot = (buf[i].flash_base & (master->erasesize - 1)) / ++ sizeof(struct fis_image_desc); ++ ++ for (i = first_slot; i < first_slot + numslots; i++) { + struct fis_list *new_fl, **prev; + + if (buf[i].name[0] == 0xff) { +diff -Nur linux-2.6.39-rc7.orig/drivers/net/Kconfig linux-2.6.39-rc7/drivers/net/Kconfig +--- linux-2.6.39-rc7.orig/drivers/net/Kconfig 2011-05-10 04:33:54.000000000 +0200 ++++ linux-2.6.39-rc7/drivers/net/Kconfig 2011-05-15 21:34:57.000000000 +0200 +@@ -251,6 +251,12 @@ + help + Select this if your platform comes with an external 93CX6 eeprom. + ++config AR231X_ETHERNET ++ tristate "AR231x Ethernet support" ++ depends on ATHEROS_AR231X ++ help ++ Support for the AR231x/531x ethernet controller ++ + config MACE + tristate "MACE (Power Mac ethernet) support" + depends on PPC_PMAC && PPC32 +diff -Nur linux-2.6.39-rc7.orig/drivers/net/Makefile linux-2.6.39-rc7/drivers/net/Makefile +--- linux-2.6.39-rc7.orig/drivers/net/Makefile 2011-05-10 04:33:54.000000000 +0200 ++++ linux-2.6.39-rc7/drivers/net/Makefile 2011-05-15 21:34:57.000000000 +0200 +@@ -226,6 +226,7 @@ + obj-$(CONFIG_KORINA) += korina.o + obj-$(CONFIG_MIPS_JAZZ_SONIC) += jazzsonic.o + obj-$(CONFIG_MIPS_AU1X00_ENET) += au1000_eth.o ++obj-$(CONFIG_AR231X_ETHERNET) += ar231x.o + obj-$(CONFIG_MIPS_SIM_NET) += mipsnet.o + obj-$(CONFIG_SGI_IOC3_ETH) += ioc3-eth.o + obj-$(CONFIG_DECLANCE) += declance.o +diff -Nur linux-2.6.39-rc7.orig/drivers/net/ar231x.c linux-2.6.39-rc7/drivers/net/ar231x.c +--- linux-2.6.39-rc7.orig/drivers/net/ar231x.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/drivers/net/ar231x.c 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,1293 @@ ++/* ++ * ar231x.c: Linux driver for the Atheros AR231x Ethernet device. ++ * ++ * Copyright (C) 2004 by Sameer Dekate ++ * Copyright (C) 2006 Imre Kaloz ++ * Copyright (C) 2006-2009 Felix Fietkau ++ * ++ * Thanks to Atheros for providing hardware and documentation ++ * enabling me to write this driver. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * Additional credits: ++ * This code is taken from John Taylor's Sibyte driver and then ++ * modified for the AR2313. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define AR2313_MTU 1692 ++#define AR2313_PRIOS 1 ++#define AR2313_QUEUES (2*AR2313_PRIOS) ++#define AR2313_DESCR_ENTRIES 64 ++ ++ ++#ifndef min ++#define min(a,b) (((a)<(b))?(a):(b)) ++#endif ++ ++#ifndef SMP_CACHE_BYTES ++#define SMP_CACHE_BYTES L1_CACHE_BYTES ++#endif ++ ++#define AR2313_MBOX_SET_BIT 0x8 ++ ++#include "ar231x.h" ++ ++/* ++ * New interrupt handler strategy: ++ * ++ * An old interrupt handler worked using the traditional method of ++ * replacing an skbuff with a new one when a packet arrives. However ++ * the rx rings do not need to contain a static number of buffer ++ * descriptors, thus it makes sense to move the memory allocation out ++ * of the main interrupt handler and do it in a bottom half handler ++ * and only allocate new buffers when the number of buffers in the ++ * ring is below a certain threshold. In order to avoid starving the ++ * NIC under heavy load it is however necessary to force allocation ++ * when hitting a minimum threshold. The strategy for alloction is as ++ * follows: ++ * ++ * RX_LOW_BUF_THRES - allocate buffers in the bottom half ++ * RX_PANIC_LOW_THRES - we are very low on buffers, allocate ++ * the buffers in the interrupt handler ++ * RX_RING_THRES - maximum number of buffers in the rx ring ++ * ++ * One advantagous side effect of this allocation approach is that the ++ * entire rx processing can be done without holding any spin lock ++ * since the rx rings and registers are totally independent of the tx ++ * ring and its registers. This of course includes the kmalloc's of ++ * new skb's. Thus start_xmit can run in parallel with rx processing ++ * and the memory allocation on SMP systems. ++ * ++ * Note that running the skb reallocation in a bottom half opens up ++ * another can of races which needs to be handled properly. In ++ * particular it can happen that the interrupt handler tries to run ++ * the reallocation while the bottom half is either running on another ++ * CPU or was interrupted on the same CPU. To get around this the ++ * driver uses bitops to prevent the reallocation routines from being ++ * reentered. ++ * ++ * TX handling can also be done without holding any spin lock, wheee ++ * this is fun! since tx_csm is only written to by the interrupt ++ * handler. ++ */ ++ ++/* ++ * Threshold values for RX buffer allocation - the low water marks for ++ * when to start refilling the rings are set to 75% of the ring ++ * sizes. It seems to make sense to refill the rings entirely from the ++ * intrrupt handler once it gets below the panic threshold, that way ++ * we don't risk that the refilling is moved to another CPU when the ++ * one running the interrupt handler just got the slab code hot in its ++ * cache. ++ */ ++#define RX_RING_SIZE AR2313_DESCR_ENTRIES ++#define RX_PANIC_THRES (RX_RING_SIZE/4) ++#define RX_LOW_THRES ((3*RX_RING_SIZE)/4) ++#define CRC_LEN 4 ++#define RX_OFFSET 2 ++ ++#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) ++#define VLAN_HDR 4 ++#else ++#define VLAN_HDR 0 ++#endif ++ ++#define AR2313_BUFSIZE (AR2313_MTU + VLAN_HDR + ETH_HLEN + CRC_LEN + RX_OFFSET) ++ ++#ifdef MODULE ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Sameer Dekate , Imre Kaloz , Felix Fietkau "); ++MODULE_DESCRIPTION("AR231x Ethernet driver"); ++#endif ++ ++#define virt_to_phys(x) ((u32)(x) & 0x1fffffff) ++ ++// prototypes ++static void ar231x_halt(struct net_device *dev); ++static void rx_tasklet_func(unsigned long data); ++static void rx_tasklet_cleanup(struct net_device *dev); ++static void ar231x_multicast_list(struct net_device *dev); ++static void ar231x_tx_timeout(struct net_device *dev); ++ ++static int ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum); ++static int ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, u16 value); ++static int ar231x_mdiobus_reset(struct mii_bus *bus); ++static int ar231x_mdiobus_probe (struct net_device *dev); ++static void ar231x_adjust_link(struct net_device *dev); ++ ++#ifndef ERR ++#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args) ++#endif ++ ++#ifdef CONFIG_NET_POLL_CONTROLLER ++static void ++ar231x_netpoll(struct net_device *dev) ++{ ++ unsigned long flags; ++ ++ local_irq_save(flags); ++ ar231x_interrupt(dev->irq, dev); ++ local_irq_restore(flags); ++} ++#endif ++ ++static const struct net_device_ops ar231x_ops = { ++ .ndo_open = ar231x_open, ++ .ndo_stop = ar231x_close, ++ .ndo_start_xmit = ar231x_start_xmit, ++ .ndo_set_multicast_list = ar231x_multicast_list, ++ .ndo_do_ioctl = ar231x_ioctl, ++ .ndo_change_mtu = eth_change_mtu, ++ .ndo_validate_addr = eth_validate_addr, ++ .ndo_set_mac_address = eth_mac_addr, ++ .ndo_tx_timeout = ar231x_tx_timeout, ++#ifdef CONFIG_NET_POLL_CONTROLLER ++ .ndo_poll_controller = ar231x_netpoll, ++#endif ++}; ++ ++int __init ar231x_probe(struct platform_device *pdev) ++{ ++ struct net_device *dev; ++ struct ar231x_private *sp; ++ struct resource *res; ++ unsigned long ar_eth_base; ++ char buf[64]; ++ ++ dev = alloc_etherdev(sizeof(struct ar231x_private)); ++ ++ if (dev == NULL) { ++ printk(KERN_ERR ++ "ar231x: Unable to allocate net_device structure!\n"); ++ return -ENOMEM; ++ } ++ ++ platform_set_drvdata(pdev, dev); ++ ++ sp = netdev_priv(dev); ++ sp->dev = dev; ++ sp->cfg = pdev->dev.platform_data; ++ ++ sprintf(buf, "eth%d_membase", pdev->id); ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, buf); ++ if (!res) ++ return -ENODEV; ++ ++ sp->link = 0; ++ ar_eth_base = res->start; ++ ++ sprintf(buf, "eth%d_irq", pdev->id); ++ dev->irq = platform_get_irq_byname(pdev, buf); ++ ++ spin_lock_init(&sp->lock); ++ ++ dev->features |= NETIF_F_HIGHDMA; ++ dev->netdev_ops = &ar231x_ops; ++ ++ tasklet_init(&sp->rx_tasklet, rx_tasklet_func, (unsigned long) dev); ++ tasklet_disable(&sp->rx_tasklet); ++ ++ sp->eth_regs = ++ ioremap_nocache(virt_to_phys(ar_eth_base), sizeof(*sp->eth_regs)); ++ if (!sp->eth_regs) { ++ printk("Can't remap eth registers\n"); ++ return (-ENXIO); ++ } ++ ++ /* ++ * When there's only one MAC, PHY regs are typically on ENET0, ++ * even though the MAC might be on ENET1. ++ * Needto remap PHY regs separately in this case ++ */ ++ if (virt_to_phys(ar_eth_base) == virt_to_phys(sp->phy_regs)) ++ sp->phy_regs = sp->eth_regs; ++ else { ++ sp->phy_regs = ++ ioremap_nocache(virt_to_phys(sp->cfg->phy_base), ++ sizeof(*sp->phy_regs)); ++ if (!sp->phy_regs) { ++ printk("Can't remap phy registers\n"); ++ return (-ENXIO); ++ } ++ } ++ ++ sp->dma_regs = ++ ioremap_nocache(virt_to_phys(ar_eth_base + 0x1000), ++ sizeof(*sp->dma_regs)); ++ dev->base_addr = (unsigned int) sp->dma_regs; ++ if (!sp->dma_regs) { ++ printk("Can't remap DMA registers\n"); ++ return (-ENXIO); ++ } ++ ++ sp->int_regs = ioremap_nocache(virt_to_phys(sp->cfg->reset_base), 4); ++ if (!sp->int_regs) { ++ printk("Can't remap INTERRUPT registers\n"); ++ return (-ENXIO); ++ } ++ ++ strncpy(sp->name, "Atheros AR231x", sizeof(sp->name) - 1); ++ sp->name[sizeof(sp->name) - 1] = '\0'; ++ memcpy(dev->dev_addr, sp->cfg->macaddr, 6); ++ ++ if (ar231x_init(dev)) { ++ /* ++ * ar231x_init() calls ar231x_init_cleanup() on error. ++ */ ++ kfree(dev); ++ return -ENODEV; ++ } ++ ++ if (register_netdev(dev)) { ++ printk("%s: register_netdev failed\n", __func__); ++ return -1; ++ } ++ ++ printk("%s: %s: %02x:%02x:%02x:%02x:%02x:%02x, irq %d\n", ++ dev->name, sp->name, ++ dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], ++ dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5], dev->irq); ++ ++ sp->mii_bus = mdiobus_alloc(); ++ if (sp->mii_bus == NULL) ++ return -1; ++ ++ sp->mii_bus->priv = dev; ++ sp->mii_bus->read = ar231x_mdiobus_read; ++ sp->mii_bus->write = ar231x_mdiobus_write; ++ sp->mii_bus->reset = ar231x_mdiobus_reset; ++ sp->mii_bus->name = "ar231x_eth_mii"; ++ snprintf(sp->mii_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id); ++ sp->mii_bus->irq = kmalloc(sizeof(int), GFP_KERNEL); ++ *sp->mii_bus->irq = PHY_POLL; ++ ++ mdiobus_register(sp->mii_bus); ++ ++ if (ar231x_mdiobus_probe(dev) != 0) { ++ printk(KERN_ERR "%s: mdiobus_probe failed\n", dev->name); ++ rx_tasklet_cleanup(dev); ++ ar231x_init_cleanup(dev); ++ unregister_netdev(dev); ++ kfree(dev); ++ return -ENODEV; ++ } ++ ++ /* start link poll timer */ ++ ar231x_setup_timer(dev); ++ ++ return 0; ++} ++ ++ ++static void ar231x_multicast_list(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ unsigned int filter; ++ ++ filter = sp->eth_regs->mac_control; ++ ++ if (dev->flags & IFF_PROMISC) ++ filter |= MAC_CONTROL_PR; ++ else ++ filter &= ~MAC_CONTROL_PR; ++ if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 0)) ++ filter |= MAC_CONTROL_PM; ++ else ++ filter &= ~MAC_CONTROL_PM; ++ ++ sp->eth_regs->mac_control = filter; ++} ++ ++static void rx_tasklet_cleanup(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ ++ /* ++ * Tasklet may be scheduled. Need to get it removed from the list ++ * since we're about to free the struct. ++ */ ++ ++ sp->unloading = 1; ++ tasklet_enable(&sp->rx_tasklet); ++ tasklet_kill(&sp->rx_tasklet); ++} ++ ++static int __devexit ar231x_remove(struct platform_device *pdev) ++{ ++ struct net_device *dev = platform_get_drvdata(pdev); ++ struct ar231x_private *sp = netdev_priv(dev); ++ rx_tasklet_cleanup(dev); ++ ar231x_init_cleanup(dev); ++ unregister_netdev(dev); ++ mdiobus_unregister(sp->mii_bus); ++ mdiobus_free(sp->mii_bus); ++ kfree(dev); ++ return 0; ++} ++ ++ ++/* ++ * Restart the AR2313 ethernet controller. ++ */ ++static int ar231x_restart(struct net_device *dev) ++{ ++ /* disable interrupts */ ++ disable_irq(dev->irq); ++ ++ /* stop mac */ ++ ar231x_halt(dev); ++ ++ /* initialize */ ++ ar231x_init(dev); ++ ++ /* enable interrupts */ ++ enable_irq(dev->irq); ++ ++ return 0; ++} ++ ++static struct platform_driver ar231x_driver = { ++ .driver.name = "ar231x-eth", ++ .probe = ar231x_probe, ++ .remove = __devexit_p(ar231x_remove), ++}; ++ ++int __init ar231x_module_init(void) ++{ ++ return platform_driver_register(&ar231x_driver); ++} ++ ++void __exit ar231x_module_cleanup(void) ++{ ++ platform_driver_unregister(&ar231x_driver); ++} ++ ++module_init(ar231x_module_init); ++module_exit(ar231x_module_cleanup); ++ ++ ++static void ar231x_free_descriptors(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ if (sp->rx_ring != NULL) { ++ kfree((void *) KSEG0ADDR(sp->rx_ring)); ++ sp->rx_ring = NULL; ++ sp->tx_ring = NULL; ++ } ++} ++ ++ ++static int ar231x_allocate_descriptors(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ int size; ++ int j; ++ ar231x_descr_t *space; ++ ++ if (sp->rx_ring != NULL) { ++ printk("%s: already done.\n", __FUNCTION__); ++ return 0; ++ } ++ ++ size = ++ (sizeof(ar231x_descr_t) * (AR2313_DESCR_ENTRIES * AR2313_QUEUES)); ++ space = kmalloc(size, GFP_KERNEL); ++ if (space == NULL) ++ return 1; ++ ++ /* invalidate caches */ ++ dma_cache_inv((unsigned int) space, size); ++ ++ /* now convert pointer to KSEG1 */ ++ space = (ar231x_descr_t *) KSEG1ADDR(space); ++ ++ memset((void *) space, 0, size); ++ ++ sp->rx_ring = space; ++ space += AR2313_DESCR_ENTRIES; ++ ++ sp->tx_ring = space; ++ space += AR2313_DESCR_ENTRIES; ++ ++ /* Initialize the transmit Descriptors */ ++ for (j = 0; j < AR2313_DESCR_ENTRIES; j++) { ++ ar231x_descr_t *td = &sp->tx_ring[j]; ++ td->status = 0; ++ td->devcs = DMA_TX1_CHAINED; ++ td->addr = 0; ++ td->descr = ++ virt_to_phys(&sp-> ++ tx_ring[(j + 1) & (AR2313_DESCR_ENTRIES - 1)]); ++ } ++ ++ return 0; ++} ++ ++ ++/* ++ * Generic cleanup handling data allocated during init. Used when the ++ * module is unloaded or if an error occurs during initialization ++ */ ++static void ar231x_init_cleanup(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ struct sk_buff *skb; ++ int j; ++ ++ ar231x_free_descriptors(dev); ++ ++ if (sp->eth_regs) ++ iounmap((void *) sp->eth_regs); ++ if (sp->dma_regs) ++ iounmap((void *) sp->dma_regs); ++ ++ if (sp->rx_skb) { ++ for (j = 0; j < AR2313_DESCR_ENTRIES; j++) { ++ skb = sp->rx_skb[j]; ++ if (skb) { ++ sp->rx_skb[j] = NULL; ++ dev_kfree_skb(skb); ++ } ++ } ++ kfree(sp->rx_skb); ++ sp->rx_skb = NULL; ++ } ++ ++ if (sp->tx_skb) { ++ for (j = 0; j < AR2313_DESCR_ENTRIES; j++) { ++ skb = sp->tx_skb[j]; ++ if (skb) { ++ sp->tx_skb[j] = NULL; ++ dev_kfree_skb(skb); ++ } ++ } ++ kfree(sp->tx_skb); ++ sp->tx_skb = NULL; ++ } ++} ++ ++static int ar231x_setup_timer(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ ++ init_timer(&sp->link_timer); ++ ++ sp->link_timer.function = ar231x_link_timer_fn; ++ sp->link_timer.data = (int) dev; ++ sp->link_timer.expires = jiffies + HZ; ++ ++ add_timer(&sp->link_timer); ++ return 0; ++ ++} ++ ++static void ar231x_link_timer_fn(unsigned long data) ++{ ++ struct net_device *dev = (struct net_device *) data; ++ struct ar231x_private *sp = netdev_priv(dev); ++ ++ // see if the link status changed ++ // This was needed to make sure we set the PHY to the ++ // autonegotiated value of half or full duplex. ++ ar231x_check_link(dev); ++ ++ // Loop faster when we don't have link. ++ // This was needed to speed up the AP bootstrap time. ++ if (sp->link == 0) { ++ mod_timer(&sp->link_timer, jiffies + HZ / 2); ++ } else { ++ mod_timer(&sp->link_timer, jiffies + LINK_TIMER); ++ } ++} ++ ++static void ar231x_check_link(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ u16 phyData; ++ ++ phyData = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_BMSR); ++ if (sp->phyData != phyData) { ++ if (phyData & BMSR_LSTATUS) { ++ /* link is present, ready link partner ability to deterine ++ duplexity */ ++ int duplex = 0; ++ u16 reg; ++ ++ sp->link = 1; ++ reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_BMCR); ++ if (reg & BMCR_ANENABLE) { ++ /* auto neg enabled */ ++ reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_LPA); ++ duplex = (reg & (LPA_100FULL | LPA_10FULL)) ? 1 : 0; ++ } else { ++ /* no auto neg, just read duplex config */ ++ duplex = (reg & BMCR_FULLDPLX) ? 1 : 0; ++ } ++ ++ printk(KERN_INFO "%s: Configuring MAC for %s duplex\n", ++ dev->name, (duplex) ? "full" : "half"); ++ ++ if (duplex) { ++ /* full duplex */ ++ sp->eth_regs->mac_control = ++ ((sp->eth_regs-> ++ mac_control | MAC_CONTROL_F) & ~MAC_CONTROL_DRO); ++ } else { ++ /* half duplex */ ++ sp->eth_regs->mac_control = ++ ((sp->eth_regs-> ++ mac_control | MAC_CONTROL_DRO) & ~MAC_CONTROL_F); ++ } ++ } else { ++ /* no link */ ++ sp->link = 0; ++ } ++ sp->phyData = phyData; ++ } ++} ++ ++static int ar231x_reset_reg(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ unsigned int ethsal, ethsah; ++ unsigned int flags; ++ ++ *sp->int_regs |= sp->cfg->reset_mac; ++ mdelay(10); ++ *sp->int_regs &= ~sp->cfg->reset_mac; ++ mdelay(10); ++ *sp->int_regs |= sp->cfg->reset_phy; ++ mdelay(10); ++ *sp->int_regs &= ~sp->cfg->reset_phy; ++ mdelay(10); ++ ++ sp->dma_regs->bus_mode = (DMA_BUS_MODE_SWR); ++ mdelay(10); ++ sp->dma_regs->bus_mode = ++ ((32 << DMA_BUS_MODE_PBL_SHIFT) | DMA_BUS_MODE_BLE); ++ ++ /* enable interrupts */ ++ sp->dma_regs->intr_ena = (DMA_STATUS_AIS | ++ DMA_STATUS_NIS | ++ DMA_STATUS_RI | ++ DMA_STATUS_TI | DMA_STATUS_FBE); ++ sp->dma_regs->xmt_base = virt_to_phys(sp->tx_ring); ++ sp->dma_regs->rcv_base = virt_to_phys(sp->rx_ring); ++ sp->dma_regs->control = ++ (DMA_CONTROL_SR | DMA_CONTROL_ST | DMA_CONTROL_SF); ++ ++ sp->eth_regs->flow_control = (FLOW_CONTROL_FCE); ++ sp->eth_regs->vlan_tag = (0x8100); ++ ++ /* Enable Ethernet Interface */ ++ flags = (MAC_CONTROL_TE | /* transmit enable */ ++ MAC_CONTROL_PM | /* pass mcast */ ++ MAC_CONTROL_F | /* full duplex */ ++ MAC_CONTROL_HBD); /* heart beat disabled */ ++ ++ if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */ ++ flags |= MAC_CONTROL_PR; ++ } ++ sp->eth_regs->mac_control = flags; ++ ++ /* Set all Ethernet station address registers to their initial values */ ++ ethsah = ((((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) | ++ (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF)); ++ ++ ethsal = ((((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) | ++ (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) | ++ (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) | ++ (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF)); ++ ++ sp->eth_regs->mac_addr[0] = ethsah; ++ sp->eth_regs->mac_addr[1] = ethsal; ++ ++ mdelay(10); ++ ++ return (0); ++} ++ ++ ++static int ar231x_init(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ int ecode = 0; ++ ++ /* ++ * Allocate descriptors ++ */ ++ if (ar231x_allocate_descriptors(dev)) { ++ printk("%s: %s: ar231x_allocate_descriptors failed\n", ++ dev->name, __FUNCTION__); ++ ecode = -EAGAIN; ++ goto init_error; ++ } ++ ++ /* ++ * Get the memory for the skb rings. ++ */ ++ if (sp->rx_skb == NULL) { ++ sp->rx_skb = ++ kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES, ++ GFP_KERNEL); ++ if (!(sp->rx_skb)) { ++ printk("%s: %s: rx_skb kmalloc failed\n", ++ dev->name, __FUNCTION__); ++ ecode = -EAGAIN; ++ goto init_error; ++ } ++ } ++ memset(sp->rx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES); ++ ++ if (sp->tx_skb == NULL) { ++ sp->tx_skb = ++ kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES, ++ GFP_KERNEL); ++ if (!(sp->tx_skb)) { ++ printk("%s: %s: tx_skb kmalloc failed\n", ++ dev->name, __FUNCTION__); ++ ecode = -EAGAIN; ++ goto init_error; ++ } ++ } ++ memset(sp->tx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES); ++ ++ /* ++ * Set tx_csm before we start receiving interrupts, otherwise ++ * the interrupt handler might think it is supposed to process ++ * tx ints before we are up and running, which may cause a null ++ * pointer access in the int handler. ++ */ ++ sp->rx_skbprd = 0; ++ sp->cur_rx = 0; ++ sp->tx_prd = 0; ++ sp->tx_csm = 0; ++ ++ /* ++ * Zero the stats before starting the interface ++ */ ++ memset(&dev->stats, 0, sizeof(dev->stats)); ++ ++ /* ++ * We load the ring here as there seem to be no way to tell the ++ * firmware to wipe the ring without re-initializing it. ++ */ ++ ar231x_load_rx_ring(dev, RX_RING_SIZE); ++ ++ /* ++ * Init hardware ++ */ ++ ar231x_reset_reg(dev); ++ ++ /* ++ * Get the IRQ ++ */ ++ ecode = ++ request_irq(dev->irq, &ar231x_interrupt, ++ IRQF_DISABLED | IRQF_SAMPLE_RANDOM, ++ dev->name, dev); ++ if (ecode) { ++ printk(KERN_WARNING "%s: %s: Requested IRQ %d is busy\n", ++ dev->name, __FUNCTION__, dev->irq); ++ goto init_error; ++ } ++ ++ ++ tasklet_enable(&sp->rx_tasklet); ++ ++ return 0; ++ ++ init_error: ++ ar231x_init_cleanup(dev); ++ return ecode; ++} ++ ++/* ++ * Load the rx ring. ++ * ++ * Loading rings is safe without holding the spin lock since this is ++ * done only before the device is enabled, thus no interrupts are ++ * generated and by the interrupt handler/tasklet handler. ++ */ ++static void ar231x_load_rx_ring(struct net_device *dev, int nr_bufs) ++{ ++ ++ struct ar231x_private *sp = netdev_priv(dev); ++ short i, idx; ++ ++ idx = sp->rx_skbprd; ++ ++ for (i = 0; i < nr_bufs; i++) { ++ struct sk_buff *skb; ++ ar231x_descr_t *rd; ++ ++ if (sp->rx_skb[idx]) ++ break; ++ ++ skb = netdev_alloc_skb(dev, AR2313_BUFSIZE); ++ if (!skb) { ++ printk("\n\n\n\n %s: No memory in system\n\n\n\n", ++ __FUNCTION__); ++ break; ++ } ++ ++ /* ++ * Make sure IP header starts on a fresh cache line. ++ */ ++ skb->dev = dev; ++ skb_reserve(skb, RX_OFFSET); ++ sp->rx_skb[idx] = skb; ++ ++ rd = (ar231x_descr_t *) & sp->rx_ring[idx]; ++ ++ /* initialize dma descriptor */ ++ rd->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) | ++ DMA_RX1_CHAINED); ++ rd->addr = virt_to_phys(skb->data); ++ rd->descr = ++ virt_to_phys(&sp-> ++ rx_ring[(idx + 1) & (AR2313_DESCR_ENTRIES - 1)]); ++ rd->status = DMA_RX_OWN; ++ ++ idx = DSC_NEXT(idx); ++ } ++ ++ if (i) ++ sp->rx_skbprd = idx; ++ ++ return; ++} ++ ++#define AR2313_MAX_PKTS_PER_CALL 64 ++ ++static int ar231x_rx_int(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ struct sk_buff *skb, *skb_new; ++ ar231x_descr_t *rxdesc; ++ unsigned int status; ++ u32 idx; ++ int pkts = 0; ++ int rval; ++ ++ idx = sp->cur_rx; ++ ++ /* process at most the entire ring and then wait for another interrupt ++ */ ++ while (1) { ++ ++ rxdesc = &sp->rx_ring[idx]; ++ status = rxdesc->status; ++ if (status & DMA_RX_OWN) { ++ /* SiByte owns descriptor or descr not yet filled in */ ++ rval = 0; ++ break; ++ } ++ ++ if (++pkts > AR2313_MAX_PKTS_PER_CALL) { ++ rval = 1; ++ break; ++ } ++ ++ if ((status & DMA_RX_ERROR) && !(status & DMA_RX_LONG)) { ++ dev->stats.rx_errors++; ++ dev->stats.rx_dropped++; ++ ++ /* add statistics counters */ ++ if (status & DMA_RX_ERR_CRC) ++ dev->stats.rx_crc_errors++; ++ if (status & DMA_RX_ERR_COL) ++ dev->stats.rx_over_errors++; ++ if (status & DMA_RX_ERR_LENGTH) ++ dev->stats.rx_length_errors++; ++ if (status & DMA_RX_ERR_RUNT) ++ dev->stats.rx_over_errors++; ++ if (status & DMA_RX_ERR_DESC) ++ dev->stats.rx_over_errors++; ++ ++ } else { ++ /* alloc new buffer. */ ++ skb_new = netdev_alloc_skb(dev, AR2313_BUFSIZE + RX_OFFSET); ++ if (skb_new != NULL) { ++ ++ skb = sp->rx_skb[idx]; ++ /* set skb */ ++ skb_put(skb, ++ ((status >> DMA_RX_LEN_SHIFT) & 0x3fff) - CRC_LEN); ++ ++ dev->stats.rx_bytes += skb->len; ++ skb->protocol = eth_type_trans(skb, dev); ++ /* pass the packet to upper layers */ ++ netif_rx(skb); ++ ++ skb_new->dev = dev; ++ /* 16 bit align */ ++ skb_reserve(skb_new, RX_OFFSET); ++ /* reset descriptor's curr_addr */ ++ rxdesc->addr = virt_to_phys(skb_new->data); ++ ++ dev->stats.rx_packets++; ++ sp->rx_skb[idx] = skb_new; ++ } else { ++ dev->stats.rx_dropped++; ++ } ++ } ++ ++ rxdesc->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) | ++ DMA_RX1_CHAINED); ++ rxdesc->status = DMA_RX_OWN; ++ ++ idx = DSC_NEXT(idx); ++ } ++ ++ sp->cur_rx = idx; ++ ++ return rval; ++} ++ ++ ++static void ar231x_tx_int(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ u32 idx; ++ struct sk_buff *skb; ++ ar231x_descr_t *txdesc; ++ unsigned int status = 0; ++ ++ idx = sp->tx_csm; ++ ++ while (idx != sp->tx_prd) { ++ txdesc = &sp->tx_ring[idx]; ++ ++ if ((status = txdesc->status) & DMA_TX_OWN) { ++ /* ar231x dma still owns descr */ ++ break; ++ } ++ /* done with this descriptor */ ++ dma_unmap_single(NULL, txdesc->addr, ++ txdesc->devcs & DMA_TX1_BSIZE_MASK, ++ DMA_TO_DEVICE); ++ txdesc->status = 0; ++ ++ if (status & DMA_TX_ERROR) { ++ dev->stats.tx_errors++; ++ dev->stats.tx_dropped++; ++ if (status & DMA_TX_ERR_UNDER) ++ dev->stats.tx_fifo_errors++; ++ if (status & DMA_TX_ERR_HB) ++ dev->stats.tx_heartbeat_errors++; ++ if (status & (DMA_TX_ERR_LOSS | DMA_TX_ERR_LINK)) ++ dev->stats.tx_carrier_errors++; ++ if (status & (DMA_TX_ERR_LATE | ++ DMA_TX_ERR_COL | ++ DMA_TX_ERR_JABBER | DMA_TX_ERR_DEFER)) ++ dev->stats.tx_aborted_errors++; ++ } else { ++ /* transmit OK */ ++ dev->stats.tx_packets++; ++ } ++ ++ skb = sp->tx_skb[idx]; ++ sp->tx_skb[idx] = NULL; ++ idx = DSC_NEXT(idx); ++ dev->stats.tx_bytes += skb->len; ++ dev_kfree_skb_irq(skb); ++ } ++ ++ sp->tx_csm = idx; ++ ++ return; ++} ++ ++ ++static void rx_tasklet_func(unsigned long data) ++{ ++ struct net_device *dev = (struct net_device *) data; ++ struct ar231x_private *sp = netdev_priv(dev); ++ ++ if (sp->unloading) { ++ return; ++ } ++ ++ if (ar231x_rx_int(dev)) { ++ tasklet_hi_schedule(&sp->rx_tasklet); ++ } else { ++ unsigned long flags; ++ spin_lock_irqsave(&sp->lock, flags); ++ sp->dma_regs->intr_ena |= DMA_STATUS_RI; ++ spin_unlock_irqrestore(&sp->lock, flags); ++ } ++} ++ ++static void rx_schedule(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ ++ sp->dma_regs->intr_ena &= ~DMA_STATUS_RI; ++ ++ tasklet_hi_schedule(&sp->rx_tasklet); ++} ++ ++static irqreturn_t ar231x_interrupt(int irq, void *dev_id) ++{ ++ struct net_device *dev = (struct net_device *) dev_id; ++ struct ar231x_private *sp = netdev_priv(dev); ++ unsigned int status, enabled; ++ ++ /* clear interrupt */ ++ /* ++ * Don't clear RI bit if currently disabled. ++ */ ++ status = sp->dma_regs->status; ++ enabled = sp->dma_regs->intr_ena; ++ sp->dma_regs->status = status & enabled; ++ ++ if (status & DMA_STATUS_NIS) { ++ /* normal status */ ++ /* ++ * Don't schedule rx processing if interrupt ++ * is already disabled. ++ */ ++ if (status & enabled & DMA_STATUS_RI) { ++ /* receive interrupt */ ++ rx_schedule(dev); ++ } ++ if (status & DMA_STATUS_TI) { ++ /* transmit interrupt */ ++ ar231x_tx_int(dev); ++ } ++ } ++ ++ /* abnormal status */ ++ if (status & (DMA_STATUS_FBE | DMA_STATUS_TPS)) { ++ ar231x_restart(dev); ++ } ++ return IRQ_HANDLED; ++} ++ ++ ++static int ar231x_open(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ unsigned int ethsal, ethsah; ++ ++ /* reset the hardware, in case the MAC address changed */ ++ ethsah = ((((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) | ++ (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF)); ++ ++ ethsal = ((((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) | ++ (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) | ++ (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) | ++ (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF)); ++ ++ sp->eth_regs->mac_addr[0] = ethsah; ++ sp->eth_regs->mac_addr[1] = ethsal; ++ ++ mdelay(10); ++ ++ dev->mtu = 1500; ++ netif_start_queue(dev); ++ ++ sp->eth_regs->mac_control |= MAC_CONTROL_RE; ++ ++ return 0; ++} ++ ++static void ar231x_tx_timeout(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ unsigned long flags; ++ ++ spin_lock_irqsave(&sp->lock, flags); ++ ar231x_restart(dev); ++ spin_unlock_irqrestore(&sp->lock, flags); ++} ++ ++static void ar231x_halt(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ int j; ++ ++ tasklet_disable(&sp->rx_tasklet); ++ ++ /* kill the MAC */ ++ sp->eth_regs->mac_control &= ~(MAC_CONTROL_RE | /* disable Receives */ ++ MAC_CONTROL_TE); /* disable Transmits */ ++ /* stop dma */ ++ sp->dma_regs->control = 0; ++ sp->dma_regs->bus_mode = DMA_BUS_MODE_SWR; ++ ++ /* place phy and MAC in reset */ ++ *sp->int_regs |= (sp->cfg->reset_mac | sp->cfg->reset_phy); ++ ++ /* free buffers on tx ring */ ++ for (j = 0; j < AR2313_DESCR_ENTRIES; j++) { ++ struct sk_buff *skb; ++ ar231x_descr_t *txdesc; ++ ++ txdesc = &sp->tx_ring[j]; ++ txdesc->descr = 0; ++ ++ skb = sp->tx_skb[j]; ++ if (skb) { ++ dev_kfree_skb(skb); ++ sp->tx_skb[j] = NULL; ++ } ++ } ++} ++ ++/* ++ * close should do nothing. Here's why. It's called when ++ * 'ifconfig bond0 down' is run. If it calls free_irq then ++ * the irq is gone forever ! When bond0 is made 'up' again, ++ * the ar231x_open () does not call request_irq (). Worse, ++ * the call to ar231x_halt() generates a WDOG reset due to ++ * the write to 'sp->int_regs' and the box reboots. ++ * Commenting this out is good since it allows the ++ * system to resume when bond0 is made up again. ++ */ ++static int ar231x_close(struct net_device *dev) ++{ ++#if 0 ++ /* ++ * Disable interrupts ++ */ ++ disable_irq(dev->irq); ++ ++ /* ++ * Without (or before) releasing irq and stopping hardware, this ++ * is an absolute non-sense, by the way. It will be reset instantly ++ * by the first irq. ++ */ ++ netif_stop_queue(dev); ++ ++ /* stop the MAC and DMA engines */ ++ ar231x_halt(dev); ++ ++ /* release the interrupt */ ++ free_irq(dev->irq, dev); ++ ++#endif ++ return 0; ++} ++ ++static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ ar231x_descr_t *td; ++ u32 idx; ++ ++ idx = sp->tx_prd; ++ td = &sp->tx_ring[idx]; ++ ++ if (td->status & DMA_TX_OWN) { ++ /* free skbuf and lie to the caller that we sent it out */ ++ dev->stats.tx_dropped++; ++ dev_kfree_skb(skb); ++ ++ /* restart transmitter in case locked */ ++ sp->dma_regs->xmt_poll = 0; ++ return 0; ++ } ++ ++ /* Setup the transmit descriptor. */ ++ td->devcs = ((skb->len << DMA_TX1_BSIZE_SHIFT) | ++ (DMA_TX1_LS | DMA_TX1_IC | DMA_TX1_CHAINED)); ++ td->addr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE); ++ td->status = DMA_TX_OWN; ++ ++ /* kick transmitter last */ ++ sp->dma_regs->xmt_poll = 0; ++ ++ sp->tx_skb[idx] = skb; ++ idx = DSC_NEXT(idx); ++ sp->tx_prd = idx; ++ ++ return 0; ++} ++ ++static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) ++{ ++ struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_data; ++ struct ar231x_private *sp = netdev_priv(dev); ++ int ret; ++ ++ switch (cmd) { ++ ++ case SIOCETHTOOL: ++ spin_lock_irq(&sp->lock); ++ ret = phy_ethtool_ioctl(sp->phy_dev, (void *) ifr->ifr_data); ++ spin_unlock_irq(&sp->lock); ++ return ret; ++ ++ case SIOCSIFHWADDR: ++ if (copy_from_user ++ (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr))) ++ return -EFAULT; ++ return 0; ++ ++ case SIOCGIFHWADDR: ++ if (copy_to_user ++ (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr))) ++ return -EFAULT; ++ return 0; ++ ++ case SIOCGMIIPHY: ++ case SIOCGMIIREG: ++ case SIOCSMIIREG: ++ return phy_mii_ioctl(sp->phy_dev, data, cmd); ++ ++ default: ++ break; ++ } ++ ++ return -EOPNOTSUPP; ++} ++ ++static void ar231x_adjust_link(struct net_device *dev) ++{ ++ struct ar231x_private *sp = netdev_priv(dev); ++ unsigned int mc; ++ ++ if (!sp->phy_dev->link) ++ return; ++ ++ if (sp->phy_dev->duplex != sp->oldduplex) { ++ mc = readl(&sp->eth_regs->mac_control); ++ mc &= ~(MAC_CONTROL_F | MAC_CONTROL_DRO); ++ if (sp->phy_dev->duplex) ++ mc |= MAC_CONTROL_F; ++ else ++ mc |= MAC_CONTROL_DRO; ++ writel(mc, &sp->eth_regs->mac_control); ++ sp->oldduplex = sp->phy_dev->duplex; ++ } ++} ++ ++#define MII_ADDR(phy, reg) \ ++ ((reg << MII_ADDR_REG_SHIFT) | (phy << MII_ADDR_PHY_SHIFT)) ++ ++static int ++ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum) ++{ ++ struct net_device *const dev = bus->priv; ++ struct ar231x_private *sp = netdev_priv(dev); ++ volatile ETHERNET_STRUCT *ethernet = sp->phy_regs; ++ ++ ethernet->mii_addr = MII_ADDR(phy_addr, regnum); ++ while (ethernet->mii_addr & MII_ADDR_BUSY); ++ return (ethernet->mii_data >> MII_DATA_SHIFT); ++} ++ ++static int ++ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, ++ u16 value) ++{ ++ struct net_device *const dev = bus->priv; ++ struct ar231x_private *sp = netdev_priv(dev); ++ volatile ETHERNET_STRUCT *ethernet = sp->phy_regs; ++ ++ while (ethernet->mii_addr & MII_ADDR_BUSY); ++ ethernet->mii_data = value << MII_DATA_SHIFT; ++ ethernet->mii_addr = MII_ADDR(phy_addr, regnum) | MII_ADDR_WRITE; ++ ++ return 0; ++} ++ ++static int ar231x_mdiobus_reset(struct mii_bus *bus) ++{ ++ struct net_device *const dev = bus->priv; ++ ++ ar231x_reset_reg(dev); ++ ++ return 0; ++} ++ ++static int ar231x_mdiobus_probe (struct net_device *dev) ++{ ++ struct ar231x_private *const sp = netdev_priv(dev); ++ struct phy_device *phydev = NULL; ++ int phy_addr; ++ ++ /* find the first (lowest address) PHY on the current MAC's MII bus */ ++ for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) ++ if (sp->mii_bus->phy_map[phy_addr]) { ++ phydev = sp->mii_bus->phy_map[phy_addr]; ++ sp->phy = phy_addr; ++ break; /* break out with first one found */ ++ } ++ ++ if (!phydev) { ++ printk (KERN_ERR "ar231x: %s: no PHY found\n", dev->name); ++ return -1; ++ } ++ ++ /* now we are supposed to have a proper phydev, to attach to... */ ++ BUG_ON(!phydev); ++ BUG_ON(phydev->attached_dev); ++ ++ phydev = phy_connect(dev, dev_name(&phydev->dev), &ar231x_adjust_link, 0, ++ PHY_INTERFACE_MODE_MII); ++ ++ if (IS_ERR(phydev)) { ++ printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name); ++ return PTR_ERR(phydev); ++ } ++ ++ /* mask with MAC supported features */ ++ phydev->supported &= (SUPPORTED_10baseT_Half ++ | SUPPORTED_10baseT_Full ++ | SUPPORTED_100baseT_Half ++ | SUPPORTED_100baseT_Full ++ | SUPPORTED_Autoneg ++ /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */ ++ | SUPPORTED_MII ++ | SUPPORTED_TP); ++ ++ phydev->advertising = phydev->supported; ++ ++ sp->oldduplex = -1; ++ sp->phy_dev = phydev; ++ ++ printk(KERN_INFO "%s: attached PHY driver [%s] " ++ "(mii_bus:phy_addr=%s)\n", ++ dev->name, phydev->drv->name, dev_name(&phydev->dev)); ++ ++ return 0; ++} ++ +diff -Nur linux-2.6.39-rc7.orig/drivers/net/ar231x.h linux-2.6.39-rc7/drivers/net/ar231x.h +--- linux-2.6.39-rc7.orig/drivers/net/ar231x.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/drivers/net/ar231x.h 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,302 @@ ++/* ++ * ar231x.h: Linux driver for the Atheros AR231x Ethernet device. ++ * ++ * Copyright (C) 2004 by Sameer Dekate ++ * Copyright (C) 2006 Imre Kaloz ++ * Copyright (C) 2006-2009 Felix Fietkau ++ * ++ * Thanks to Atheros for providing hardware and documentation ++ * enabling me to write this driver. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#ifndef _AR2313_H_ ++#define _AR2313_H_ ++ ++#include ++#include ++#include ++#include ++ ++/* ++ * probe link timer - 5 secs ++ */ ++#define LINK_TIMER (5*HZ) ++ ++#define IS_DMA_TX_INT(X) (((X) & (DMA_STATUS_TI)) != 0) ++#define IS_DMA_RX_INT(X) (((X) & (DMA_STATUS_RI)) != 0) ++#define IS_DRIVER_OWNED(X) (((X) & (DMA_TX_OWN)) == 0) ++ ++#define AR2313_TX_TIMEOUT (HZ/4) ++ ++/* ++ * Rings ++ */ ++#define DSC_RING_ENTRIES_SIZE (AR2313_DESCR_ENTRIES * sizeof(struct desc)) ++#define DSC_NEXT(idx) ((idx + 1) & (AR2313_DESCR_ENTRIES - 1)) ++ ++#define AR2313_MBGET 2 ++#define AR2313_MBSET 3 ++#define AR2313_PCI_RECONFIG 4 ++#define AR2313_PCI_DUMP 5 ++#define AR2313_TEST_PANIC 6 ++#define AR2313_TEST_NULLPTR 7 ++#define AR2313_READ_DATA 8 ++#define AR2313_WRITE_DATA 9 ++#define AR2313_GET_VERSION 10 ++#define AR2313_TEST_HANG 11 ++#define AR2313_SYNC 12 ++ ++#define DMA_RX_ERR_CRC BIT(1) ++#define DMA_RX_ERR_DRIB BIT(2) ++#define DMA_RX_ERR_MII BIT(3) ++#define DMA_RX_EV2 BIT(5) ++#define DMA_RX_ERR_COL BIT(6) ++#define DMA_RX_LONG BIT(7) ++#define DMA_RX_LS BIT(8) /* last descriptor */ ++#define DMA_RX_FS BIT(9) /* first descriptor */ ++#define DMA_RX_MF BIT(10) /* multicast frame */ ++#define DMA_RX_ERR_RUNT BIT(11) /* runt frame */ ++#define DMA_RX_ERR_LENGTH BIT(12) /* length error */ ++#define DMA_RX_ERR_DESC BIT(14) /* descriptor error */ ++#define DMA_RX_ERROR BIT(15) /* error summary */ ++#define DMA_RX_LEN_MASK 0x3fff0000 ++#define DMA_RX_LEN_SHIFT 16 ++#define DMA_RX_FILT BIT(30) ++#define DMA_RX_OWN BIT(31) /* desc owned by DMA controller */ ++ ++#define DMA_RX1_BSIZE_MASK 0x000007ff ++#define DMA_RX1_BSIZE_SHIFT 0 ++#define DMA_RX1_CHAINED BIT(24) ++#define DMA_RX1_RER BIT(25) ++ ++#define DMA_TX_ERR_UNDER BIT(1) /* underflow error */ ++#define DMA_TX_ERR_DEFER BIT(2) /* excessive deferral */ ++#define DMA_TX_COL_MASK 0x78 ++#define DMA_TX_COL_SHIFT 3 ++#define DMA_TX_ERR_HB BIT(7) /* hearbeat failure */ ++#define DMA_TX_ERR_COL BIT(8) /* excessive collisions */ ++#define DMA_TX_ERR_LATE BIT(9) /* late collision */ ++#define DMA_TX_ERR_LINK BIT(10) /* no carrier */ ++#define DMA_TX_ERR_LOSS BIT(11) /* loss of carrier */ ++#define DMA_TX_ERR_JABBER BIT(14) /* transmit jabber timeout */ ++#define DMA_TX_ERROR BIT(15) /* frame aborted */ ++#define DMA_TX_OWN BIT(31) /* descr owned by DMA controller */ ++ ++#define DMA_TX1_BSIZE_MASK 0x000007ff ++#define DMA_TX1_BSIZE_SHIFT 0 ++#define DMA_TX1_CHAINED BIT(24) /* chained descriptors */ ++#define DMA_TX1_TER BIT(25) /* transmit end of ring */ ++#define DMA_TX1_FS BIT(29) /* first segment */ ++#define DMA_TX1_LS BIT(30) /* last segment */ ++#define DMA_TX1_IC BIT(31) /* interrupt on completion */ ++ ++#define RCVPKT_LENGTH(X) (X >> 16) /* Received pkt Length */ ++ ++#define MAC_CONTROL_RE BIT(2) /* receive enable */ ++#define MAC_CONTROL_TE BIT(3) /* transmit enable */ ++#define MAC_CONTROL_DC BIT(5) /* Deferral check */ ++#define MAC_CONTROL_ASTP BIT(8) /* Auto pad strip */ ++#define MAC_CONTROL_DRTY BIT(10) /* Disable retry */ ++#define MAC_CONTROL_DBF BIT(11) /* Disable bcast frames */ ++#define MAC_CONTROL_LCC BIT(12) /* late collision ctrl */ ++#define MAC_CONTROL_HP BIT(13) /* Hash Perfect filtering */ ++#define MAC_CONTROL_HASH BIT(14) /* Unicast hash filtering */ ++#define MAC_CONTROL_HO BIT(15) /* Hash only filtering */ ++#define MAC_CONTROL_PB BIT(16) /* Pass Bad frames */ ++#define MAC_CONTROL_IF BIT(17) /* Inverse filtering */ ++#define MAC_CONTROL_PR BIT(18) /* promiscuous mode (valid frames only) */ ++#define MAC_CONTROL_PM BIT(19) /* pass multicast */ ++#define MAC_CONTROL_F BIT(20) /* full-duplex */ ++#define MAC_CONTROL_DRO BIT(23) /* Disable Receive Own */ ++#define MAC_CONTROL_HBD BIT(28) /* heart-beat disabled (MUST BE SET) */ ++#define MAC_CONTROL_BLE BIT(30) /* big endian mode */ ++#define MAC_CONTROL_RA BIT(31) /* receive all (valid and invalid frames) */ ++ ++#define MII_ADDR_BUSY BIT(0) ++#define MII_ADDR_WRITE BIT(1) ++#define MII_ADDR_REG_SHIFT 6 ++#define MII_ADDR_PHY_SHIFT 11 ++#define MII_DATA_SHIFT 0 ++ ++#define FLOW_CONTROL_FCE BIT(1) ++ ++#define DMA_BUS_MODE_SWR BIT(0) /* software reset */ ++#define DMA_BUS_MODE_BLE BIT(7) /* big endian mode */ ++#define DMA_BUS_MODE_PBL_SHIFT 8 /* programmable burst length 32 */ ++#define DMA_BUS_MODE_DBO BIT(20) /* big-endian descriptors */ ++ ++#define DMA_STATUS_TI BIT(0) /* transmit interrupt */ ++#define DMA_STATUS_TPS BIT(1) /* transmit process stopped */ ++#define DMA_STATUS_TU BIT(2) /* transmit buffer unavailable */ ++#define DMA_STATUS_TJT BIT(3) /* transmit buffer timeout */ ++#define DMA_STATUS_UNF BIT(5) /* transmit underflow */ ++#define DMA_STATUS_RI BIT(6) /* receive interrupt */ ++#define DMA_STATUS_RU BIT(7) /* receive buffer unavailable */ ++#define DMA_STATUS_RPS BIT(8) /* receive process stopped */ ++#define DMA_STATUS_ETI BIT(10) /* early transmit interrupt */ ++#define DMA_STATUS_FBE BIT(13) /* fatal bus interrupt */ ++#define DMA_STATUS_ERI BIT(14) /* early receive interrupt */ ++#define DMA_STATUS_AIS BIT(15) /* abnormal interrupt summary */ ++#define DMA_STATUS_NIS BIT(16) /* normal interrupt summary */ ++#define DMA_STATUS_RS_SHIFT 17 /* receive process state */ ++#define DMA_STATUS_TS_SHIFT 20 /* transmit process state */ ++#define DMA_STATUS_EB_SHIFT 23 /* error bits */ ++ ++#define DMA_CONTROL_SR BIT(1) /* start receive */ ++#define DMA_CONTROL_ST BIT(13) /* start transmit */ ++#define DMA_CONTROL_SF BIT(21) /* store and forward */ ++ ++ ++typedef struct { ++ volatile unsigned int status; // OWN, Device control and status. ++ volatile unsigned int devcs; // pkt Control bits + Length ++ volatile unsigned int addr; // Current Address. ++ volatile unsigned int descr; // Next descriptor in chain. ++} ar231x_descr_t; ++ ++ ++ ++// ++// New Combo structure for Both Eth0 AND eth1 ++// ++typedef struct { ++ volatile unsigned int mac_control; /* 0x00 */ ++ volatile unsigned int mac_addr[2]; /* 0x04 - 0x08 */ ++ volatile unsigned int mcast_table[2]; /* 0x0c - 0x10 */ ++ volatile unsigned int mii_addr; /* 0x14 */ ++ volatile unsigned int mii_data; /* 0x18 */ ++ volatile unsigned int flow_control; /* 0x1c */ ++ volatile unsigned int vlan_tag; /* 0x20 */ ++ volatile unsigned int pad[7]; /* 0x24 - 0x3c */ ++ volatile unsigned int ucast_table[8]; /* 0x40-0x5c */ ++ ++} ETHERNET_STRUCT; ++ ++/******************************************************************** ++ * Interrupt controller ++ ********************************************************************/ ++ ++typedef struct { ++ volatile unsigned int wdog_control; /* 0x08 */ ++ volatile unsigned int wdog_timer; /* 0x0c */ ++ volatile unsigned int misc_status; /* 0x10 */ ++ volatile unsigned int misc_mask; /* 0x14 */ ++ volatile unsigned int global_status; /* 0x18 */ ++ volatile unsigned int reserved; /* 0x1c */ ++ volatile unsigned int reset_control; /* 0x20 */ ++} INTERRUPT; ++ ++/******************************************************************** ++ * DMA controller ++ ********************************************************************/ ++typedef struct { ++ volatile unsigned int bus_mode; /* 0x00 (CSR0) */ ++ volatile unsigned int xmt_poll; /* 0x04 (CSR1) */ ++ volatile unsigned int rcv_poll; /* 0x08 (CSR2) */ ++ volatile unsigned int rcv_base; /* 0x0c (CSR3) */ ++ volatile unsigned int xmt_base; /* 0x10 (CSR4) */ ++ volatile unsigned int status; /* 0x14 (CSR5) */ ++ volatile unsigned int control; /* 0x18 (CSR6) */ ++ volatile unsigned int intr_ena; /* 0x1c (CSR7) */ ++ volatile unsigned int rcv_missed; /* 0x20 (CSR8) */ ++ volatile unsigned int reserved[11]; /* 0x24-0x4c (CSR9-19) */ ++ volatile unsigned int cur_tx_buf_addr; /* 0x50 (CSR20) */ ++ volatile unsigned int cur_rx_buf_addr; /* 0x50 (CSR21) */ ++} DMA; ++ ++/* ++ * Struct private for the Sibyte. ++ * ++ * Elements are grouped so variables used by the tx handling goes ++ * together, and will go into the same cache lines etc. in order to ++ * avoid cache line contention between the rx and tx handling on SMP. ++ * ++ * Frequently accessed variables are put at the beginning of the ++ * struct to help the compiler generate better/shorter code. ++ */ ++struct ar231x_private { ++ struct net_device *dev; ++ int version; ++ u32 mb[2]; ++ ++ volatile ETHERNET_STRUCT *phy_regs; ++ volatile ETHERNET_STRUCT *eth_regs; ++ volatile DMA *dma_regs; ++ volatile u32 *int_regs; ++ struct ar231x_eth *cfg; ++ ++ spinlock_t lock; /* Serialise access to device */ ++ ++ /* ++ * RX and TX descriptors, must be adjacent ++ */ ++ ar231x_descr_t *rx_ring; ++ ar231x_descr_t *tx_ring; ++ ++ ++ struct sk_buff **rx_skb; ++ struct sk_buff **tx_skb; ++ ++ /* ++ * RX elements ++ */ ++ u32 rx_skbprd; ++ u32 cur_rx; ++ ++ /* ++ * TX elements ++ */ ++ u32 tx_prd; ++ u32 tx_csm; ++ ++ /* ++ * Misc elements ++ */ ++ char name[48]; ++ struct { ++ u32 address; ++ u32 length; ++ char *mapping; ++ } desc; ++ ++ ++ struct timer_list link_timer; ++ unsigned short phy; /* merlot phy = 1, samsung phy = 0x1f */ ++ unsigned short mac; ++ unsigned short link; /* 0 - link down, 1 - link up */ ++ u16 phyData; ++ ++ struct tasklet_struct rx_tasklet; ++ int unloading; ++ ++ struct phy_device *phy_dev; ++ struct mii_bus *mii_bus; ++ int oldduplex; ++}; ++ ++ ++/* ++ * Prototypes ++ */ ++static int ar231x_init(struct net_device *dev); ++#ifdef TX_TIMEOUT ++static void ar231x_tx_timeout(struct net_device *dev); ++#endif ++static int ar231x_restart(struct net_device *dev); ++static void ar231x_load_rx_ring(struct net_device *dev, int bufs); ++static irqreturn_t ar231x_interrupt(int irq, void *dev_id); ++static int ar231x_open(struct net_device *dev); ++static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev); ++static int ar231x_close(struct net_device *dev); ++static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr, ++ int cmd); ++static void ar231x_init_cleanup(struct net_device *dev); ++static int ar231x_setup_timer(struct net_device *dev); ++static void ar231x_link_timer_fn(unsigned long data); ++static void ar231x_check_link(struct net_device *dev); ++#endif /* _AR2313_H_ */ +diff -Nur linux-2.6.39-rc7.orig/drivers/watchdog/Kconfig linux-2.6.39-rc7/drivers/watchdog/Kconfig +--- linux-2.6.39-rc7.orig/drivers/watchdog/Kconfig 2011-05-10 04:33:54.000000000 +0200 ++++ linux-2.6.39-rc7/drivers/watchdog/Kconfig 2011-05-15 21:34:57.000000000 +0200 +@@ -990,6 +990,12 @@ + To compile this driver as a loadable module, choose M here. + The module will be called bcm63xx_wdt. + ++config ATHEROS_WDT ++ tristate "Atheros wisoc Watchdog Timer" ++ depends on ATHEROS_AR231X ++ help ++ Hardware driver for the Atheros wisoc Watchdog Timer. ++ + # PARISC Architecture + + # POWERPC Architecture +diff -Nur linux-2.6.39-rc7.orig/drivers/watchdog/Makefile linux-2.6.39-rc7/drivers/watchdog/Makefile +--- linux-2.6.39-rc7.orig/drivers/watchdog/Makefile 2011-05-10 04:33:54.000000000 +0200 ++++ linux-2.6.39-rc7/drivers/watchdog/Makefile 2011-05-15 21:34:57.000000000 +0200 +@@ -120,6 +120,7 @@ + obj-$(CONFIG_PNX833X_WDT) += pnx833x_wdt.o + obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o + obj-$(CONFIG_AR7_WDT) += ar7_wdt.o ++obj-$(CONFIG_ATHEROS_WDT) += ar2315-wtd.o + obj-$(CONFIG_TXX9_WDT) += txx9wdt.o + obj-$(CONFIG_OCTEON_WDT) += octeon-wdt.o + octeon-wdt-y := octeon-wdt-main.o octeon-wdt-nmi.o +diff -Nur linux-2.6.39-rc7.orig/drivers/watchdog/ar2315-wtd.c linux-2.6.39-rc7/drivers/watchdog/ar2315-wtd.c +--- linux-2.6.39-rc7.orig/drivers/watchdog/ar2315-wtd.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.39-rc7/drivers/watchdog/ar2315-wtd.c 2011-05-15 21:34:57.000000000 +0200 +@@ -0,0 +1,200 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ * Copyright (C) 2008 John Crispin ++ * Based on EP93xx and ifxmips wdt driver ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define CLOCK_RATE 40000000 ++#define HEARTBEAT(x) (x < 1 || x > 90)?(20):(x) ++ ++static int wdt_timeout = 20; ++static int started = 0; ++static int in_use = 0; ++ ++static void ++ar2315_wdt_enable(void) ++{ ++ ar231x_write_reg(AR2315_WD, wdt_timeout * CLOCK_RATE); ++ ar231x_write_reg(AR2315_ISR, 0x80); ++} ++ ++static ssize_t ++ar2315_wdt_write(struct file *file, const char __user *data, size_t len, loff_t *ppos) ++{ ++ if(len) ++ ar2315_wdt_enable(); ++ return len; ++} ++ ++static int ++ar2315_wdt_open(struct inode *inode, struct file *file) ++{ ++ if(in_use) ++ return -EBUSY; ++ ar2315_wdt_enable(); ++ in_use = started = 1; ++ return nonseekable_open(inode, file); ++} ++ ++static int ++ar2315_wdt_release(struct inode *inode, struct file *file) ++{ ++ in_use = 0; ++ return 0; ++} ++ ++static irqreturn_t ++ar2315_wdt_interrupt(int irq, void *dev_id) ++{ ++ if(started) ++ { ++ printk(KERN_CRIT "watchdog expired, rebooting system\n"); ++ emergency_restart(); ++ } else { ++ ar231x_write_reg(AR2315_WDC, 0); ++ ar231x_write_reg(AR2315_WD, 0); ++ ar231x_write_reg(AR2315_ISR, 0x80); ++ } ++ return IRQ_HANDLED; ++} ++ ++static struct watchdog_info ident = { ++ .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, ++ .identity = "ar2315 Watchdog", ++}; ++ ++static int ++ar2315_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) ++{ ++ int new_wdt_timeout; ++ int ret = -ENOIOCTLCMD; ++ ++ switch(cmd) ++ { ++ case WDIOC_GETSUPPORT: ++ ret = copy_to_user((struct watchdog_info __user *)arg, &ident, sizeof(ident)) ? -EFAULT : 0; ++ break; ++ ++ case WDIOC_KEEPALIVE: ++ ar2315_wdt_enable(); ++ ret = 0; ++ break; ++ ++ case WDIOC_SETTIMEOUT: ++ if((ret = get_user(new_wdt_timeout, (int __user *)arg))) ++ break; ++ wdt_timeout = HEARTBEAT(new_wdt_timeout); ++ ar2315_wdt_enable(); ++ break; ++ ++ case WDIOC_GETTIMEOUT: ++ ret = put_user(wdt_timeout, (int __user *)arg); ++ break; ++ } ++ return ret; ++} ++ ++static struct file_operations ar2315_wdt_fops = { ++ .owner = THIS_MODULE, ++ .llseek = no_llseek, ++ .write = ar2315_wdt_write, ++ .unlocked_ioctl = ar2315_wdt_ioctl, ++ .open = ar2315_wdt_open, ++ .release = ar2315_wdt_release, ++}; ++ ++static struct miscdevice ar2315_wdt_miscdev = { ++ .minor = WATCHDOG_MINOR, ++ .name = "watchdog", ++ .fops = &ar2315_wdt_fops, ++}; ++ ++static int ++ar2315_wdt_probe(struct platform_device *dev) ++{ ++ int ret = 0; ++ ++ ar2315_wdt_enable(); ++ ret = request_irq(AR531X_MISC_IRQ_WATCHDOG, ar2315_wdt_interrupt, IRQF_DISABLED, "ar2315_wdt", NULL); ++ if(ret) ++ { ++ printk(KERN_ERR "ar2315wdt: failed to register inetrrupt\n"); ++ goto out; ++ } ++ ++ ret = misc_register(&ar2315_wdt_miscdev); ++ if(ret) ++ printk(KERN_ERR "ar2315wdt: failed to register miscdev\n"); ++ ++out: ++ return ret; ++} ++ ++static int ++ar2315_wdt_remove(struct platform_device *dev) ++{ ++ misc_deregister(&ar2315_wdt_miscdev); ++ free_irq(AR531X_MISC_IRQ_WATCHDOG, NULL); ++ return 0; ++} ++ ++static struct platform_driver ar2315_wdt_driver = { ++ .probe = ar2315_wdt_probe, ++ .remove = ar2315_wdt_remove, ++ .driver = { ++ .name = "ar2315_wdt", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static int __init ++init_ar2315_wdt(void) ++{ ++ int ret = platform_driver_register(&ar2315_wdt_driver); ++ if(ret) ++ printk(KERN_INFO "ar2315_wdt: error registering platfom driver!"); ++ return ret; ++} ++ ++static void __exit ++exit_ar2315_wdt(void) ++{ ++ platform_driver_unregister(&ar2315_wdt_driver); ++} ++ ++module_init(init_ar2315_wdt); ++module_exit(exit_ar2315_wdt); diff --git a/target/linux/patches/3.1.4/gemalto.patch b/target/linux/patches/3.1.4/gemalto.patch new file mode 100644 index 000000000..f3c223b5e --- /dev/null +++ b/target/linux/patches/3.1.4/gemalto.patch @@ -0,0 +1,11 @@ +diff -Nur linux-2.6.36.orig/drivers/tty/serial/serial_cs.c linux-2.6.36/drivers/serial/serial_cs.c +--- linux-2.6.36.orig/drivers/tty/serial/serial_cs.c 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/drivers/tty/serial/serial_cs.c 2010-12-13 23:03:40.000000000 +0100 +@@ -794,6 +794,7 @@ + PCMCIA_DEVICE_MANF_CARD(0x0137, 0x0025), + PCMCIA_DEVICE_MANF_CARD(0x0137, 0x0045), + PCMCIA_DEVICE_MANF_CARD(0x0137, 0x0052), ++ PCMCIA_DEVICE_MANF_CARD(0x0157, 0x0100), /* Gemalto SCR */ + PCMCIA_DEVICE_MANF_CARD(0x016c, 0x0006), /* Psion 56K+Fax */ + PCMCIA_DEVICE_MANF_CARD(0x0200, 0x0001), /* MultiMobile */ + PCMCIA_DEVICE_PROD_ID134("ADV", "TECH", "COMpad-32/85", 0x67459937, 0x916d02ba, 0x8fbe92ae), diff --git a/target/linux/patches/3.1.4/mmc-host.patch b/target/linux/patches/3.1.4/mmc-host.patch new file mode 100644 index 000000000..3d0e37add --- /dev/null +++ b/target/linux/patches/3.1.4/mmc-host.patch @@ -0,0 +1,36 @@ +diff -Nur linux-2.6.39-rc6.orig/drivers/mmc/host/Kconfig linux-2.6.39-rc6/drivers/mmc/host/Kconfig +--- linux-2.6.39-rc6.orig/drivers/mmc/host/Kconfig 2011-05-04 04:59:13.000000000 +0200 ++++ linux-2.6.39-rc6/drivers/mmc/host/Kconfig 2011-05-10 23:39:01.000000000 +0200 +@@ -253,13 +253,6 @@ + + If unsure, say N. + +-choice +- prompt "Atmel SD/MMC Driver" +- depends on AVR32 || ARCH_AT91 +- default MMC_ATMELMCI if AVR32 +- help +- Choose which driver to use for the Atmel MCI Silicon +- + config MMC_AT91 + tristate "AT91 SD/MMC Card Interface support" + depends on ARCH_AT91 +@@ -268,18 +261,6 @@ + + If unsure, say N. + +-config MMC_ATMELMCI +- tristate "Atmel Multimedia Card Interface support" +- depends on AVR32 || ARCH_AT91 +- help +- This selects the Atmel Multimedia Card Interface driver. If +- you have an AT32 (AVR32) or AT91 platform with a Multimedia +- Card slot, say Y or M here. +- +- If unsure, say N. +- +-endchoice +- + config MMC_ATMELMCI_DMA + bool "Atmel MCI DMA support (EXPERIMENTAL)" + depends on MMC_ATMELMCI && (AVR32 || ARCH_AT91SAM9G45) && DMA_ENGINE && EXPERIMENTAL diff --git a/target/linux/patches/3.1.4/non-static.patch b/target/linux/patches/3.1.4/non-static.patch new file mode 100644 index 000000000..a967703d0 --- /dev/null +++ b/target/linux/patches/3.1.4/non-static.patch @@ -0,0 +1,33 @@ +diff -Nur linux-2.6.39-rc6.orig/fs/namei.c linux-2.6.39-rc6/fs/namei.c +--- linux-2.6.39-rc6.orig/fs/namei.c 2011-05-04 04:59:13.000000000 +0200 ++++ linux-2.6.39-rc6/fs/namei.c 2011-05-05 11:30:14.000000000 +0200 +@@ -1769,7 +1769,7 @@ + * needs parent already locked. Doesn't follow mounts. + * SMP-safe. + */ +-static struct dentry *lookup_hash(struct nameidata *nd) ++struct dentry *lookup_hash(struct nameidata *nd) + { + return __lookup_hash(&nd->last, nd->path.dentry, nd); + } +diff -Nur linux-2.6.39-rc6.orig/fs/splice.c linux-2.6.39-rc6/fs/splice.c +--- linux-2.6.39-rc6.orig/fs/splice.c 2011-05-04 04:59:13.000000000 +0200 ++++ linux-2.6.39-rc6/fs/splice.c 2011-05-05 11:31:04.000000000 +0200 +@@ -1081,7 +1081,7 @@ + /* + * Attempt to initiate a splice from pipe to file. + */ +-static long do_splice_from(struct pipe_inode_info *pipe, struct file *out, ++long do_splice_from(struct pipe_inode_info *pipe, struct file *out, + loff_t *ppos, size_t len, unsigned int flags) + { + ssize_t (*splice_write)(struct pipe_inode_info *, struct file *, +@@ -1109,7 +1109,7 @@ + /* + * Attempt to initiate a splice from a file to a pipe. + */ +-static long do_splice_to(struct file *in, loff_t *ppos, ++long do_splice_to(struct file *in, loff_t *ppos, + struct pipe_inode_info *pipe, size_t len, + unsigned int flags) + { diff --git a/target/linux/patches/3.1.4/ocf-20110720.patch b/target/linux/patches/3.1.4/ocf-20110720.patch new file mode 100644 index 000000000..a162fd5d8 --- /dev/null +++ b/target/linux/patches/3.1.4/ocf-20110720.patch @@ -0,0 +1,96377 @@ +diff -Nur linux-3.1.4.orig/crypto/Kconfig linux-3.1.4/crypto/Kconfig +--- linux-3.1.4.orig/crypto/Kconfig 2011-11-28 23:48:14.000000000 +0100 ++++ linux-3.1.4/crypto/Kconfig 2011-12-01 12:54:17.000000000 +0100 +@@ -860,3 +860,6 @@ + source "drivers/crypto/Kconfig" + + endif # if CRYPTO ++ ++source "crypto/ocf/Kconfig" ++ +diff -Nur linux-3.1.4.orig/crypto/Makefile linux-3.1.4/crypto/Makefile +--- linux-3.1.4.orig/crypto/Makefile 2011-11-28 23:48:14.000000000 +0100 ++++ linux-3.1.4/crypto/Makefile 2011-12-01 12:54:17.000000000 +0100 +@@ -89,6 +89,8 @@ + obj-$(CONFIG_CRYPTO_USER_API_HASH) += algif_hash.o + obj-$(CONFIG_CRYPTO_USER_API_SKCIPHER) += algif_skcipher.o + ++obj-$(CONFIG_OCF_OCF) += ocf/ ++ + # + # generic algorithms and the async_tx api + # +diff -Nur linux-3.1.4.orig/crypto/ocf/Config.in linux-3.1.4/crypto/ocf/Config.in +--- linux-3.1.4.orig/crypto/ocf/Config.in 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/Config.in 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,38 @@ ++############################################################################# ++ ++mainmenu_option next_comment ++comment 'OCF Configuration' ++tristate 'OCF (Open Cryptograhic Framework)' CONFIG_OCF_OCF ++dep_mbool ' enable fips RNG checks (fips check on RNG data before use)' \ ++ CONFIG_OCF_FIPS $CONFIG_OCF_OCF ++dep_mbool ' enable harvesting entropy for /dev/random' \ ++ CONFIG_OCF_RANDOMHARVEST $CONFIG_OCF_OCF ++dep_tristate ' cryptodev (user space support)' \ ++ CONFIG_OCF_CRYPTODEV $CONFIG_OCF_OCF ++dep_tristate ' cryptosoft (software crypto engine)' \ ++ CONFIG_OCF_CRYPTOSOFT $CONFIG_OCF_OCF ++dep_tristate ' safenet (HW crypto engine)' \ ++ CONFIG_OCF_SAFE $CONFIG_OCF_OCF ++dep_tristate ' IXP4xx (HW crypto engine)' \ ++ CONFIG_OCF_IXP4XX $CONFIG_OCF_OCF ++dep_mbool ' Enable IXP4xx HW to perform SHA1 and MD5 hashing (very slow)' \ ++ CONFIG_OCF_IXP4XX_SHA1_MD5 $CONFIG_OCF_IXP4XX ++dep_tristate ' hifn (HW crypto engine)' \ ++ CONFIG_OCF_HIFN $CONFIG_OCF_OCF ++dep_tristate ' talitos (HW crypto engine)' \ ++ CONFIG_OCF_TALITOS $CONFIG_OCF_OCF ++dep_tristate ' pasemi (HW crypto engine)' \ ++ CONFIG_OCF_PASEMI $CONFIG_OCF_OCF ++dep_tristate ' ep80579 (HW crypto engine)' \ ++ CONFIG_OCF_EP80579 $CONFIG_OCF_OCF ++dep_tristate ' Micronas c7108 (HW crypto engine)' \ ++ CONFIG_OCF_C7108 $CONFIG_OCF_OCF ++dep_tristate ' uBsec BCM5365 (HW crypto engine)' ++ CONFIG_OCF_UBSEC_SSB $CONFIG_OCF_OCF ++dep_tristate ' ocfnull (does no crypto)' \ ++ CONFIG_OCF_OCFNULL $CONFIG_OCF_OCF ++dep_tristate ' ocf-bench (HW crypto in-kernel benchmark)' \ ++ CONFIG_OCF_BENCH $CONFIG_OCF_OCF ++endmenu ++ ++############################################################################# +diff -Nur linux-3.1.4.orig/crypto/ocf/Kconfig linux-3.1.4/crypto/ocf/Kconfig +--- linux-3.1.4.orig/crypto/ocf/Kconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/Kconfig 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,125 @@ ++menu "OCF Configuration" ++ ++config OCF_OCF ++ tristate "OCF (Open Cryptograhic Framework)" ++ help ++ A linux port of the OpenBSD/FreeBSD crypto framework. ++ ++config OCF_RANDOMHARVEST ++ bool "crypto random --- harvest entropy for /dev/random" ++ depends on OCF_OCF ++ help ++ Includes code to harvest random numbers from devices that support it. ++ ++config OCF_FIPS ++ bool "enable fips RNG checks" ++ depends on OCF_OCF && OCF_RANDOMHARVEST ++ help ++ Run all RNG provided data through a fips check before ++ adding it /dev/random's entropy pool. ++ ++config OCF_CRYPTODEV ++ tristate "cryptodev (user space support)" ++ depends on OCF_OCF ++ help ++ The user space API to access crypto hardware. ++ ++config OCF_CRYPTOSOFT ++ tristate "cryptosoft (software crypto engine)" ++ depends on OCF_OCF ++ help ++ A software driver for the OCF framework that uses ++ the kernel CryptoAPI. ++ ++config OCF_SAFE ++ tristate "safenet (HW crypto engine)" ++ depends on OCF_OCF ++ help ++ A driver for a number of the safenet Excel crypto accelerators. ++ Currently tested and working on the 1141 and 1741. ++ ++config OCF_IXP4XX ++ tristate "IXP4xx (HW crypto engine)" ++ depends on OCF_OCF ++ help ++ XScale IXP4xx crypto accelerator driver. Requires the ++ Intel Access library. ++ ++config OCF_IXP4XX_SHA1_MD5 ++ bool "IXP4xx SHA1 and MD5 Hashing" ++ depends on OCF_IXP4XX ++ help ++ Allows the IXP4xx crypto accelerator to perform SHA1 and MD5 hashing. ++ Note: this is MUCH slower than using cryptosoft (software crypto engine). ++ ++config OCF_HIFN ++ tristate "hifn (HW crypto engine)" ++ depends on OCF_OCF ++ help ++ OCF driver for various HIFN based crypto accelerators. ++ (7951, 7955, 7956, 7751, 7811) ++ ++config OCF_HIFNHIPP ++ tristate "Hifn HIPP (HW packet crypto engine)" ++ depends on OCF_OCF ++ help ++ OCF driver for various HIFN (HIPP) based crypto accelerators ++ (7855) ++ ++config OCF_TALITOS ++ tristate "talitos (HW crypto engine)" ++ depends on OCF_OCF ++ help ++ OCF driver for Freescale's security engine (SEC/talitos). ++ ++config OCF_PASEMI ++ tristate "pasemi (HW crypto engine)" ++ depends on OCF_OCF && PPC_PASEMI ++ help ++ OCF driver for the PA Semi PWRficient DMA Engine ++ ++config OCF_EP80579 ++ tristate "ep80579 (HW crypto engine)" ++ depends on OCF_OCF ++ help ++ OCF driver for the Intel EP80579 Integrated Processor Product Line. ++ ++config OCF_CRYPTOCTEON ++ tristate "cryptocteon (HW crypto engine)" ++ depends on OCF_OCF ++ help ++ OCF driver for the Cavium OCTEON Processors. ++ ++config OCF_KIRKWOOD ++ tristate "kirkwood (HW crypto engine)" ++ depends on OCF_OCF ++ help ++ OCF driver for the Marvell Kirkwood (88F6xxx) Processors. ++ ++config OCF_C7108 ++ tristate "Micronas 7108 (HW crypto engine)" ++ depends on OCF_OCF ++ help ++ OCF driver for the Microna 7108 Cipher processors. ++ ++config OCF_UBSEC_SSB ++ tristate "uBsec BCM5365 (HW crypto engine)" ++ depends on OCF_OCF ++ help ++ OCF driver for uBsec BCM5365 hardware crypto accelerator. ++ ++config OCF_OCFNULL ++ tristate "ocfnull (fake crypto engine)" ++ depends on OCF_OCF ++ help ++ OCF driver for measuring ipsec overheads (does no crypto) ++ ++config OCF_BENCH ++ tristate "ocf-bench (HW crypto in-kernel benchmark)" ++ depends on OCF_OCF ++ help ++ A very simple encryption test for the in-kernel interface ++ of OCF. Also includes code to benchmark the IXP Access library ++ for comparison. ++ ++endmenu +diff -Nur linux-3.1.4.orig/crypto/ocf/Makefile linux-3.1.4/crypto/ocf/Makefile +--- linux-3.1.4.orig/crypto/ocf/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/Makefile 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,145 @@ ++# for SGlinux builds ++-include $(ROOTDIR)/modules/.config ++ ++OCF_OBJS = crypto.o criov.o ++ ++ifdef CONFIG_OCF_RANDOMHARVEST ++ OCF_OBJS += random.o ++endif ++ ++ifdef CONFIG_OCF_FIPS ++ OCF_OBJS += rndtest.o ++endif ++ ++# Add in autoconf.h to get #defines for CONFIG_xxx ++AUTOCONF_H=$(ROOTDIR)/modules/autoconf.h ++ifeq ($(AUTOCONF_H), $(wildcard $(AUTOCONF_H))) ++ EXTRA_CFLAGS += -include $(AUTOCONF_H) ++ export EXTRA_CFLAGS ++endif ++ ++ifndef obj ++ obj ?= . ++ _obj = subdir ++ mod-subdirs := safe hifn ixp4xx talitos ocfnull ++ export-objs += crypto.o criov.o random.o ++ list-multi += ocf.o ++ _slash := ++else ++ _obj = obj ++ _slash := / ++endif ++ ++EXTRA_CFLAGS += -I$(obj)/. ++ ++obj-$(CONFIG_OCF_OCF) += ocf.o ++obj-$(CONFIG_OCF_CRYPTODEV) += cryptodev.o ++obj-$(CONFIG_OCF_CRYPTOSOFT) += cryptosoft.o ++obj-$(CONFIG_OCF_BENCH) += ocf-bench.o ++ ++$(_obj)-$(CONFIG_OCF_SAFE) += safe$(_slash) ++$(_obj)-$(CONFIG_OCF_HIFN) += hifn$(_slash) ++$(_obj)-$(CONFIG_OCF_IXP4XX) += ixp4xx$(_slash) ++$(_obj)-$(CONFIG_OCF_TALITOS) += talitos$(_slash) ++$(_obj)-$(CONFIG_OCF_PASEMI) += pasemi$(_slash) ++$(_obj)-$(CONFIG_OCF_EP80579) += ep80579$(_slash) ++$(_obj)-$(CONFIG_OCF_CRYPTOCTEON) += cryptocteon$(_slash) ++$(_obj)-$(CONFIG_OCF_KIRKWOOD) += kirkwood$(_slash) ++$(_obj)-$(CONFIG_OCF_OCFNULL) += ocfnull$(_slash) ++$(_obj)-$(CONFIG_OCF_C7108) += c7108$(_slash) ++$(_obj)-$(CONFIG_OCF_UBSEC_SSB) += ubsec_ssb$(_slash) ++ ++ocf-objs := $(OCF_OBJS) ++ ++dummy: ++ @echo "Please consult the README for how to build OCF." ++ @echo "If you can't wait then the following should do it:" ++ @echo "" ++ @echo " make ocf_modules" ++ @echo " sudo make ocf_install" ++ @echo "" ++ @exit 1 ++ ++$(list-multi) dummy1: $(ocf-objs) ++ $(LD) -r -o $@ $(ocf-objs) ++ ++.PHONY: ++clean: ++ rm -f *.o *.ko .*.o.flags .*.ko.cmd .*.o.cmd .*.mod.o.cmd *.mod.c ++ rm -f */*.o */*.ko */.*.o.cmd */.*.ko.cmd */.*.mod.o.cmd */*.mod.c */.*.o.flags ++ rm -f */modules.order */modules.builtin modules.order modules.builtin ++ ++ifdef TOPDIR ++-include $(TOPDIR)/Rules.make ++endif ++ ++# ++# targets to build easily on the current machine ++# ++ ++ocf_make: ++ make -C /lib/modules/$(shell uname -r)/build M=`pwd` $(OCF_TARGET) CONFIG_OCF_OCF=m ++ make -C /lib/modules/$(shell uname -r)/build M=`pwd` $(OCF_TARGET) CONFIG_OCF_OCF=m CONFIG_OCF_CRYPTOSOFT=m ++ -make -C /lib/modules/$(shell uname -r)/build M=`pwd` $(OCF_TARGET) CONFIG_OCF_OCF=m CONFIG_OCF_BENCH=m ++ -make -C /lib/modules/$(shell uname -r)/build M=`pwd` $(OCF_TARGET) CONFIG_OCF_OCF=m CONFIG_OCF_OCFNULL=m ++ -make -C /lib/modules/$(shell uname -r)/build M=`pwd` $(OCF_TARGET) CONFIG_OCF_OCF=m CONFIG_OCF_HIFN=m ++ ++ocf_modules: ++ $(MAKE) ocf_make OCF_TARGET=modules ++ ++ocf_install: ++ $(MAKE) ocf_make OCF_TARGET="modules modules_install" ++ depmod ++ mkdir -p /usr/include/crypto ++ cp cryptodev.h /usr/include/crypto/. ++ ++# ++# generate full kernel patches for 2.4 and 2.6 kernels to make patching ++# your kernel easier ++# ++ ++.PHONY: patch ++patch: ++ patchbase=.; \ ++ [ -d $$patchbase/patches ] || patchbase=..; \ ++ patch=ocf-linux-base.patch; \ ++ patch24=ocf-linux-24.patch; \ ++ patch26=ocf-linux-26.patch; \ ++ ( \ ++ find . -name Makefile; \ ++ find . -name Config.in; \ ++ find . -name Kconfig; \ ++ find . -name README; \ ++ find . -name '*.[ch]' | grep -v '.mod.c'; \ ++ ) | while read t; do \ ++ diff -Nau /dev/null $$t | sed 's?^+++ \./?+++ linux/crypto/ocf/?'; \ ++ done > $$patch; \ ++ cat $$patchbase/patches/linux-2.4.35-ocf.patch $$patch > $$patch24; \ ++ cat $$patchbase/patches/linux-2.6.38-ocf.patch $$patch > $$patch26; \ ++ ++# ++# this target probably does nothing for anyone but me - davidm ++# ++ ++.PHONY: release ++release: ++ REL=`date +%Y%m%d`; RELDIR=/tmp/ocf-linux-$$REL; \ ++ CURDIR=`pwd`; \ ++ rm -rf /tmp/ocf-linux-$$REL*; \ ++ mkdir -p $$RELDIR/ocf; \ ++ mkdir -p $$RELDIR/patches; \ ++ mkdir -p $$RELDIR/crypto-tools; \ ++ cp README* $$RELDIR/.; \ ++ cp patches/[!C]* $$RELDIR/patches/.; \ ++ cp tools/[!C]* $$RELDIR/crypto-tools/.; \ ++ cp -r [!C]* Config.in $$RELDIR/ocf/.; \ ++ rm -rf $$RELDIR/ocf/patches $$RELDIR/ocf/tools; \ ++ rm -f $$RELDIR/ocf/README*; \ ++ cp $$CURDIR/../../user/crypto-tools/[!C]* $$RELDIR/crypto-tools/.; \ ++ make -C $$RELDIR/crypto-tools clean; \ ++ make -C $$RELDIR/ocf clean; \ ++ find $$RELDIR/ocf -name CVS | xargs rm -rf; \ ++ cd $$RELDIR/..; \ ++ tar cvf ocf-linux-$$REL.tar ocf-linux-$$REL; \ ++ gzip -9 ocf-linux-$$REL.tar ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/c7108/Makefile linux-3.1.4/crypto/ocf/c7108/Makefile +--- linux-3.1.4.orig/crypto/ocf/c7108/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/c7108/Makefile 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,12 @@ ++# for SGlinux builds ++-include $(ROOTDIR)/modules/.config ++ ++obj-$(CONFIG_OCF_C7108) += aes-7108.o ++ ++obj ?= . ++EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ ++ ++ifdef TOPDIR ++-include $(TOPDIR)/Rules.make ++endif ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/c7108/aes-7108.c linux-3.1.4/crypto/ocf/c7108/aes-7108.c +--- linux-3.1.4.orig/crypto/ocf/c7108/aes-7108.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/c7108/aes-7108.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,839 @@ ++/* ++ * Copyright (C) 2006 Micronas USA ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored in part by the Defense Advanced Research Projects ++ * Agency (DARPA) and Air Force Research Laboratory, Air Force ++ * Materiel Command, USAF, under agreement number F30602-01-2-0537. ++ * ++ */ ++ ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* Runtime mode */ ++static int c7108_crypto_mode = C7108_AES_CTRL_MODE_CTR; ++//static int c7108_crypto_mode = C7108_AES_CTRL_MODE_CBC; ++ ++static int32_t c7108_id = -1; ++static struct cipher_7108 **c7108_sessions = NULL; ++static u_int32_t c7108_sesnum = 0; ++static unsigned long iobar; ++ ++/* Crypto entry points */ ++static int c7108_process(void *, struct cryptop *, int); ++static int c7108_newsession(void *, u_int32_t *, struct cryptoini *); ++static int c7108_freesession(void *, u_int64_t); ++ ++/* Globals */ ++static int debug = 0; ++static spinlock_t csr_mutex; ++ ++/* Generic controller-based lock */ ++#define AES_LOCK()\ ++ spin_lock(&csr_mutex) ++#define AES_UNLOCK()\ ++ spin_unlock(&csr_mutex) ++ ++/* 7108 AES register access */ ++#define c7108_reg_wr8(a,d) iowrite8(d, (void*)(iobar+(a))) ++#define c7108_reg_wr16(a,d) iowrite16(d, (void*)(iobar+(a))) ++#define c7108_reg_wr32(a,d) iowrite32(d, (void*)(iobar+(a))) ++#define c7108_reg_rd8(a) ioread8((void*)(iobar+(a))) ++#define c7108_reg_rd16(a) ioread16((void*)(iobar+(a))) ++#define c7108_reg_rd32(a) ioread32((void*)(iobar+(a))) ++ ++static int ++c7108_xlate_key(int klen, u8* k8ptr, u32* k32ptr) ++{ ++ int i, nw=0; ++ nw = ((klen >= 256) ? 8 : (klen >= 192) ? 6 : 4); ++ for ( i = 0; i < nw; i++) { ++ k32ptr[i] = (k8ptr[i+3] << 24) | (k8ptr[i+2] << 16) | ++ (k8ptr[i+1] << 8) | k8ptr[i]; ++ ++ } ++ return 0; ++} ++ ++static int ++c7108_cache_key(int klen, u32* k32ptr, u8* k8ptr) ++{ ++ int i, nb=0; ++ u8* ptr = (u8*)k32ptr; ++ nb = ((klen >= 256) ? 32 : (klen >= 192) ? 24 : 16); ++ for ( i = 0; i < nb; i++) ++ k8ptr[i] = ptr[i]; ++ return 0; ++} ++ ++static int ++c7108_aes_setup_dma(u32 src, u32 dst, u32 len) ++{ ++ if (len < 16) { ++ printk("len < 16\n"); ++ return -10; ++ } ++ if (len % 16) { ++ printk("len not multiple of 16\n"); ++ return -11; ++ } ++ c7108_reg_wr16(C7108_AES_DMA_SRC0_LO, (u16) src); ++ c7108_reg_wr16(C7108_AES_DMA_SRC0_HI, (u16)((src & 0xffff0000) >> 16)); ++ c7108_reg_wr16(C7108_AES_DMA_DST0_LO, (u16) dst); ++ c7108_reg_wr16(C7108_AES_DMA_DST0_HI, (u16)((dst & 0xffff0000) >> 16)); ++ c7108_reg_wr16(C7108_AES_DMA_LEN, (u16) ((len / 16) - 1)); ++ ++ return 0; ++} ++ ++static int ++c7108_aes_set_hw_iv(u8 iv[16]) ++{ ++ c7108_reg_wr16(C7108_AES_IV0_LO, (u16) ((iv[1] << 8) | iv[0])); ++ c7108_reg_wr16(C7108_AES_IV0_HI, (u16) ((iv[3] << 8) | iv[2])); ++ c7108_reg_wr16(C7108_AES_IV1_LO, (u16) ((iv[5] << 8) | iv[4])); ++ c7108_reg_wr16(C7108_AES_IV1_HI, (u16) ((iv[7] << 8) | iv[6])); ++ c7108_reg_wr16(C7108_AES_IV2_LO, (u16) ((iv[9] << 8) | iv[8])); ++ c7108_reg_wr16(C7108_AES_IV2_HI, (u16) ((iv[11] << 8) | iv[10])); ++ c7108_reg_wr16(C7108_AES_IV3_LO, (u16) ((iv[13] << 8) | iv[12])); ++ c7108_reg_wr16(C7108_AES_IV3_HI, (u16) ((iv[15] << 8) | iv[14])); ++ ++ return 0; ++} ++ ++static void ++c7108_aes_read_dkey(u32 * dkey) ++{ ++ dkey[0] = (c7108_reg_rd16(C7108_AES_EKEY0_HI) << 16) | ++ c7108_reg_rd16(C7108_AES_EKEY0_LO); ++ dkey[1] = (c7108_reg_rd16(C7108_AES_EKEY1_HI) << 16) | ++ c7108_reg_rd16(C7108_AES_EKEY1_LO); ++ dkey[2] = (c7108_reg_rd16(C7108_AES_EKEY2_HI) << 16) | ++ c7108_reg_rd16(C7108_AES_EKEY2_LO); ++ dkey[3] = (c7108_reg_rd16(C7108_AES_EKEY3_HI) << 16) | ++ c7108_reg_rd16(C7108_AES_EKEY3_LO); ++ dkey[4] = (c7108_reg_rd16(C7108_AES_EKEY4_HI) << 16) | ++ c7108_reg_rd16(C7108_AES_EKEY4_LO); ++ dkey[5] = (c7108_reg_rd16(C7108_AES_EKEY5_HI) << 16) | ++ c7108_reg_rd16(C7108_AES_EKEY5_LO); ++ dkey[6] = (c7108_reg_rd16(C7108_AES_EKEY6_HI) << 16) | ++ c7108_reg_rd16(C7108_AES_EKEY6_LO); ++ dkey[7] = (c7108_reg_rd16(C7108_AES_EKEY7_HI) << 16) | ++ c7108_reg_rd16(C7108_AES_EKEY7_LO); ++} ++ ++static int ++c7108_aes_cipher(int op, ++ u32 dst, ++ u32 src, ++ u32 len, ++ int klen, ++ u16 mode, ++ u32 key[8], ++ u8 iv[16]) ++{ ++ int rv = 0, cnt=0; ++ u16 ctrl = 0, stat = 0; ++ ++ AES_LOCK(); ++ ++ /* Setup key length */ ++ if (klen == 128) { ++ ctrl |= C7108_AES_KEY_LEN_128; ++ } else if (klen == 192) { ++ ctrl |= C7108_AES_KEY_LEN_192; ++ } else if (klen == 256) { ++ ctrl |= C7108_AES_KEY_LEN_256; ++ } else { ++ AES_UNLOCK(); ++ return -3; ++ } ++ ++ /* Check opcode */ ++ if (C7108_AES_ENCRYPT == op) { ++ ctrl |= C7108_AES_ENCRYPT; ++ } else if (C7108_AES_DECRYPT == op) { ++ ctrl |= C7108_AES_DECRYPT; ++ } else { ++ AES_UNLOCK(); ++ return -4; ++ } ++ ++ /* check mode */ ++ if ( (mode != C7108_AES_CTRL_MODE_CBC) && ++ (mode != C7108_AES_CTRL_MODE_CFB) && ++ (mode != C7108_AES_CTRL_MODE_OFB) && ++ (mode != C7108_AES_CTRL_MODE_CTR) && ++ (mode != C7108_AES_CTRL_MODE_ECB) ) { ++ AES_UNLOCK(); ++ return -5; ++ } ++ ++ /* Now set mode */ ++ ctrl |= mode; ++ ++ /* For CFB, OFB, and CTR, neither backward key ++ * expansion nor key inversion is required. ++ */ ++ if ( (C7108_AES_DECRYPT == op) && ++ (C7108_AES_CTRL_MODE_CBC == mode || ++ C7108_AES_CTRL_MODE_ECB == mode ) ){ ++ ++ /* Program Key */ ++ c7108_reg_wr16(C7108_AES_KEY0_LO, (u16) key[4]); ++ c7108_reg_wr16(C7108_AES_KEY0_HI, (u16) (key[4] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY1_LO, (u16) key[5]); ++ c7108_reg_wr16(C7108_AES_KEY1_HI, (u16) (key[5] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY2_LO, (u16) key[6]); ++ c7108_reg_wr16(C7108_AES_KEY2_HI, (u16) (key[6] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY3_LO, (u16) key[7]); ++ c7108_reg_wr16(C7108_AES_KEY3_HI, (u16) (key[7] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY6_LO, (u16) key[2]); ++ c7108_reg_wr16(C7108_AES_KEY6_HI, (u16) (key[2] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY7_LO, (u16) key[3]); ++ c7108_reg_wr16(C7108_AES_KEY7_HI, (u16) (key[3] >> 16)); ++ ++ ++ if (192 == klen) { ++ c7108_reg_wr16(C7108_AES_KEY4_LO, (u16) key[7]); ++ c7108_reg_wr16(C7108_AES_KEY4_HI, (u16) (key[7] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY5_LO, (u16) key[7]); ++ c7108_reg_wr16(C7108_AES_KEY5_HI, (u16) (key[7] >> 16)); ++ ++ } else if (256 == klen) { ++ /* 256 */ ++ c7108_reg_wr16(C7108_AES_KEY4_LO, (u16) key[0]); ++ c7108_reg_wr16(C7108_AES_KEY4_HI, (u16) (key[0] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY5_LO, (u16) key[1]); ++ c7108_reg_wr16(C7108_AES_KEY5_HI, (u16) (key[1] >> 16)); ++ ++ } ++ ++ } else { ++ /* Program Key */ ++ c7108_reg_wr16(C7108_AES_KEY0_LO, (u16) key[0]); ++ c7108_reg_wr16(C7108_AES_KEY0_HI, (u16) (key[0] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY1_LO, (u16) key[1]); ++ c7108_reg_wr16(C7108_AES_KEY1_HI, (u16) (key[1] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY2_LO, (u16) key[2]); ++ c7108_reg_wr16(C7108_AES_KEY2_HI, (u16) (key[2] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY3_LO, (u16) key[3]); ++ c7108_reg_wr16(C7108_AES_KEY3_HI, (u16) (key[3] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY4_LO, (u16) key[4]); ++ c7108_reg_wr16(C7108_AES_KEY4_HI, (u16) (key[4] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY5_LO, (u16) key[5]); ++ c7108_reg_wr16(C7108_AES_KEY5_HI, (u16) (key[5] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY6_LO, (u16) key[6]); ++ c7108_reg_wr16(C7108_AES_KEY6_HI, (u16) (key[6] >> 16)); ++ c7108_reg_wr16(C7108_AES_KEY7_LO, (u16) key[7]); ++ c7108_reg_wr16(C7108_AES_KEY7_HI, (u16) (key[7] >> 16)); ++ ++ } ++ ++ /* Set IV always */ ++ c7108_aes_set_hw_iv(iv); ++ ++ /* Program DMA addresses */ ++ if ((rv = c7108_aes_setup_dma(src, dst, len)) < 0) { ++ AES_UNLOCK(); ++ return rv; ++ } ++ ++ ++ /* Start AES cipher */ ++ c7108_reg_wr16(C7108_AES_CTRL, ctrl | C7108_AES_GO); ++ ++ //printk("Ctrl: 0x%x\n", ctrl | C7108_AES_GO); ++ do { ++ /* TODO: interrupt mode */ ++ // printk("aes_stat=0x%x\n", stat); ++ //udelay(100); ++ } while ((cnt++ < 1000000) && ++ !((stat=c7108_reg_rd16(C7108_AES_CTRL))&C7108_AES_OP_DONE)); ++ ++ ++ if ((mode == C7108_AES_CTRL_MODE_ECB)|| ++ (mode == C7108_AES_CTRL_MODE_CBC)) { ++ /* Save out key when the lock is held ... */ ++ c7108_aes_read_dkey(key); ++ } ++ ++ AES_UNLOCK(); ++ return 0; ++ ++} ++ ++/* ++ * Generate a new crypto device session. ++ */ ++static int ++c7108_newsession(void *arg, u_int32_t *sid, struct cryptoini *cri) ++{ ++ struct cipher_7108 **swd; ++ u_int32_t i; ++ char *algo; ++ int mode, xfm_type; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (sid == NULL || cri == NULL) { ++ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ if (c7108_sessions) { ++ for (i = 1; i < c7108_sesnum; i++) ++ if (c7108_sessions[i] == NULL) ++ break; ++ } else ++ i = 1; /* NB: to silence compiler warning */ ++ ++ if (c7108_sessions == NULL || i == c7108_sesnum) { ++ if (c7108_sessions == NULL) { ++ i = 1; /* We leave c7108_sessions[0] empty */ ++ c7108_sesnum = CRYPTO_SW_SESSIONS; ++ } else ++ c7108_sesnum *= 2; ++ ++ swd = kmalloc(c7108_sesnum * sizeof(struct cipher_7108 *), ++ GFP_ATOMIC); ++ if (swd == NULL) { ++ /* Reset session number */ ++ if (c7108_sesnum == CRYPTO_SW_SESSIONS) ++ c7108_sesnum = 0; ++ else ++ c7108_sesnum /= 2; ++ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ memset(swd, 0, c7108_sesnum * sizeof(struct cipher_7108 *)); ++ ++ /* Copy existing sessions */ ++ if (c7108_sessions) { ++ memcpy(swd, c7108_sessions, ++ (c7108_sesnum / 2) * sizeof(struct cipher_7108 *)); ++ kfree(c7108_sessions); ++ } ++ ++ c7108_sessions = swd; ++ ++ } ++ ++ swd = &c7108_sessions[i]; ++ *sid = i; ++ ++ while (cri) { ++ *swd = (struct cipher_7108 *) ++ kmalloc(sizeof(struct cipher_7108), GFP_ATOMIC); ++ if (*swd == NULL) { ++ c7108_freesession(NULL, i); ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ memset(*swd, 0, sizeof(struct cipher_7108)); ++ ++ algo = NULL; ++ mode = 0; ++ xfm_type = HW_TYPE_CIPHER; ++ ++ switch (cri->cri_alg) { ++ ++ case CRYPTO_AES_CBC: ++ algo = "aes"; ++ mode = CRYPTO_TFM_MODE_CBC; ++ c7108_crypto_mode = C7108_AES_CTRL_MODE_CBC; ++ break; ++#if 0 ++ case CRYPTO_AES_CTR: ++ algo = "aes_ctr"; ++ mode = CRYPTO_TFM_MODE_CBC; ++ c7108_crypto_mode = C7108_AES_CTRL_MODE_CTR; ++ break; ++ case CRYPTO_AES_ECB: ++ algo = "aes_ecb"; ++ mode = CRYPTO_TFM_MODE_CBC; ++ c7108_crypto_mode = C7108_AES_CTRL_MODE_ECB; ++ break; ++ case CRYPTO_AES_OFB: ++ algo = "aes_ofb"; ++ mode = CRYPTO_TFM_MODE_CBC; ++ c7108_crypto_mode = C7108_AES_CTRL_MODE_OFB; ++ break; ++ case CRYPTO_AES_CFB: ++ algo = "aes_cfb"; ++ mode = CRYPTO_TFM_MODE_CBC; ++ c7108_crypto_mode = C7108_AES_CTRL_MODE_CFB; ++ break; ++#endif ++ default: ++ printk("unsupported crypto algorithm: %d\n", ++ cri->cri_alg); ++ return -EINVAL; ++ break; ++ } ++ ++ ++ if (!algo || !*algo) { ++ printk("cypher_7108_crypto: Unknown algo 0x%x\n", ++ cri->cri_alg); ++ c7108_freesession(NULL, i); ++ return EINVAL; ++ } ++ ++ if (xfm_type == HW_TYPE_CIPHER) { ++ if (debug) { ++ dprintk("%s key:", __FUNCTION__); ++ for (i = 0; i < (cri->cri_klen + 7) / 8; i++) ++ dprintk("%s0x%02x", (i % 8) ? " " : "\n ", ++ cri->cri_key[i]); ++ dprintk("\n"); ++ } ++ ++ } else if (xfm_type == SW_TYPE_HMAC || ++ xfm_type == SW_TYPE_HASH) { ++ printk("cypher_7108_crypto: HMAC unsupported!\n"); ++ return -EINVAL; ++ c7108_freesession(NULL, i); ++ } else { ++ printk("cypher_7108_crypto: " ++ "Unhandled xfm_type %d\n", xfm_type); ++ c7108_freesession(NULL, i); ++ return EINVAL; ++ } ++ ++ (*swd)->cri_alg = cri->cri_alg; ++ (*swd)->xfm_type = xfm_type; ++ ++ cri = cri->cri_next; ++ swd = &((*swd)->next); ++ } ++ return 0; ++} ++ ++/* ++ * Free a session. ++ */ ++static int ++c7108_freesession(void *arg, u_int64_t tid) ++{ ++ struct cipher_7108 *swd; ++ u_int32_t sid = CRYPTO_SESID2LID(tid); ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (sid > c7108_sesnum || c7108_sessions == NULL || ++ c7108_sessions[sid] == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return(EINVAL); ++ } ++ ++ /* Silently accept and return */ ++ if (sid == 0) ++ return(0); ++ ++ while ((swd = c7108_sessions[sid]) != NULL) { ++ c7108_sessions[sid] = swd->next; ++ kfree(swd); ++ } ++ return 0; ++} ++ ++/* ++ * Process a hardware request. ++ */ ++static int ++c7108_process(void *arg, struct cryptop *crp, int hint) ++{ ++ struct cryptodesc *crd; ++ struct cipher_7108 *sw; ++ u_int32_t lid; ++ int type; ++ u32 hwkey[8]; ++ ++#define SCATTERLIST_MAX 16 ++ struct scatterlist sg[SCATTERLIST_MAX]; ++ int sg_num, sg_len, skip; ++ struct sk_buff *skb = NULL; ++ struct uio *uiop = NULL; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ /* Sanity check */ ++ if (crp == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ crp->crp_etype = 0; ++ ++ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ crp->crp_etype = EINVAL; ++ goto done; ++ } ++ ++ lid = crp->crp_sid & 0xffffffff; ++ if (lid >= c7108_sesnum || lid == 0 || c7108_sessions == NULL || ++ c7108_sessions[lid] == NULL) { ++ crp->crp_etype = ENOENT; ++ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); ++ goto done; ++ } ++ ++ /* ++ * do some error checking outside of the loop for SKB and IOV ++ * processing this leaves us with valid skb or uiop pointers ++ * for later ++ */ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ skb = (struct sk_buff *) crp->crp_buf; ++ if (skb_shinfo(skb)->nr_frags >= SCATTERLIST_MAX) { ++ printk("%s,%d: %d nr_frags > SCATTERLIST_MAX", ++ __FILE__, __LINE__, ++ skb_shinfo(skb)->nr_frags); ++ goto done; ++ } ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ uiop = (struct uio *) crp->crp_buf; ++ if (uiop->uio_iovcnt > SCATTERLIST_MAX) { ++ printk("%s,%d: %d uio_iovcnt > SCATTERLIST_MAX", ++ __FILE__, __LINE__, ++ uiop->uio_iovcnt); ++ goto done; ++ } ++ } ++ ++ /* Go through crypto descriptors, processing as we go */ ++ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { ++ /* ++ * Find the crypto context. ++ * ++ * XXX Note that the logic here prevents us from having ++ * XXX the same algorithm multiple times in a session ++ * XXX (or rather, we can but it won't give us the right ++ * XXX results). To do that, we'd need some way of differentiating ++ * XXX between the various instances of an algorithm (so we can ++ * XXX locate the correct crypto context). ++ */ ++ for (sw = c7108_sessions[lid]; ++ sw && sw->cri_alg != crd->crd_alg; ++ sw = sw->next) ++ ; ++ ++ /* No such context ? */ ++ if (sw == NULL) { ++ crp->crp_etype = EINVAL; ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ goto done; ++ } ++ ++ skip = crd->crd_skip; ++ ++ /* ++ * setup the SG list skip from the start of the buffer ++ */ ++ memset(sg, 0, sizeof(sg)); ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ int i, len; ++ type = CRYPTO_BUF_SKBUF; ++ ++ sg_num = 0; ++ sg_len = 0; ++ ++ if (skip < skb_headlen(skb)) { ++ //sg[sg_num].page = virt_to_page(skb->data + skip); ++ //sg[sg_num].offset = offset_in_page(skb->data + skip); ++ len = skb_headlen(skb) - skip; ++ if (len + sg_len > crd->crd_len) ++ len = crd->crd_len - sg_len; ++ //sg[sg_num].length = len; ++ sg_set_page(&sg[sg_num], virt_to_page(skb->data + skip), len, offset_in_page(skb->data + skip)); ++ sg_len += sg[sg_num].length; ++ sg_num++; ++ skip = 0; ++ } else ++ skip -= skb_headlen(skb); ++ ++ for (i = 0; sg_len < crd->crd_len && ++ i < skb_shinfo(skb)->nr_frags && ++ sg_num < SCATTERLIST_MAX; i++) { ++ if (skip < skb_shinfo(skb)->frags[i].size) { ++ //sg[sg_num].page = skb_shinfo(skb)->frags[i].page; ++ //sg[sg_num].offset = skb_shinfo(skb)->frags[i].page_offset + skip; ++ len = skb_shinfo(skb)->frags[i].size - skip; ++ if (len + sg_len > crd->crd_len) ++ len = crd->crd_len - sg_len; ++ //sg[sg_num].length = len; ++ sg_set_page(&sg[sg_num], skb_shinfo(skb)->frags[i].page, len, skb_shinfo(skb)->frags[i].page_offset + skip); ++ sg_len += sg[sg_num].length; ++ sg_num++; ++ skip = 0; ++ } else ++ skip -= skb_shinfo(skb)->frags[i].size; ++ } ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ int len; ++ type = CRYPTO_BUF_IOV; ++ sg_len = 0; ++ for (sg_num = 0; sg_len < crd->crd_len && ++ sg_num < uiop->uio_iovcnt && ++ sg_num < SCATTERLIST_MAX; sg_num++) { ++ if (skip < uiop->uio_iov[sg_num].iov_len) { ++ //sg[sg_num].page = virt_to_page(uiop->uio_iov[sg_num].iov_base+skip); ++ //sg[sg_num].offset = offset_in_page(uiop->uio_iov[sg_num].iov_base+skip); ++ len = uiop->uio_iov[sg_num].iov_len - skip; ++ if (len + sg_len > crd->crd_len) ++ len = crd->crd_len - sg_len; ++ //sg[sg_num].length = len; ++ sg_set_page(&sg[sg_num], virt_to_page(uiop->uio_iov[sg_num].iov_base+skip), len, offset_in_page(uiop->uio_iov[sg_num].iov_base+skip)); ++ sg_len += sg[sg_num].length; ++ skip = 0; ++ } else ++ skip -= uiop->uio_iov[sg_num].iov_len; ++ } ++ } else { ++ type = CRYPTO_BUF_CONTIG; ++ //sg[0].page = virt_to_page(crp->crp_buf + skip); ++ //sg[0].offset = offset_in_page(crp->crp_buf + skip); ++ sg_len = (crp->crp_ilen - skip); ++ if (sg_len > crd->crd_len) ++ sg_len = crd->crd_len; ++ //sg[0].length = sg_len; ++ sg_set_page(&sg[0], virt_to_page(crp->crp_buf + skip), sg_len, offset_in_page(crp->crp_buf + skip)); ++ sg_num = 1; ++ } ++ ++ ++ switch (sw->xfm_type) { ++ ++ case HW_TYPE_CIPHER: { ++ ++ unsigned char iv[64]; ++ unsigned char *ivp = iv; ++ int i; ++ int ivsize = 16; /* fixed for AES */ ++ int blocksize = 16; /* fixed for AES */ ++ ++ if (sg_len < blocksize) { ++ crp->crp_etype = EINVAL; ++ dprintk("%s,%d: EINVAL len %d < %d\n", ++ __FILE__, __LINE__, ++ sg_len, ++ blocksize); ++ goto done; ++ } ++ ++ if (ivsize > sizeof(iv)) { ++ crp->crp_etype = EINVAL; ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ goto done; ++ } ++ ++ if (crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ ++ ++ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { ++ ivp = crd->crd_iv; ++ } else { ++ get_random_bytes(ivp, ivsize); ++ } ++ /* ++ * do we have to copy the IV back to the buffer ? ++ */ ++ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { ++ crypto_copyback(crp->crp_buf, ++ crd->crd_inject, ++ ivsize, ++ (caddr_t)ivp); ++ } ++ ++ c7108_xlate_key(crd->crd_klen, ++ (u8*)crd->crd_key, (u32*)hwkey); ++ ++ /* Encrypt SG list */ ++ for (i = 0; i < sg_num; i++) { ++ sg[i].dma_address = ++ dma_map_single(NULL, ++ kmap(sg_page(&sg[i])) + sg[i].offset, sg_len, DMA_BIDIRECTIONAL); ++#if 0 ++ printk("sg[%d]:0x%08x, off 0x%08x " ++ "kmap 0x%08x phys 0x%08x\n", ++ i, sg[i].page, sg[i].offset, ++ kmap(sg[i].page) + sg[i].offset, ++ sg[i].dma_address); ++#endif ++ c7108_aes_cipher(C7108_AES_ENCRYPT, ++ sg[i].dma_address, ++ sg[i].dma_address, ++ sg_len, ++ crd->crd_klen, ++ c7108_crypto_mode, ++ hwkey, ++ ivp); ++ ++ if ((c7108_crypto_mode == C7108_AES_CTRL_MODE_CBC)|| ++ (c7108_crypto_mode == C7108_AES_CTRL_MODE_ECB)) { ++ /* Read back expanded key and cache it in key ++ * context. ++ * NOTE: for ECB/CBC modes only (not CTR, CFB, OFB) ++ * where you set the key once. ++ */ ++ c7108_cache_key(crd->crd_klen, ++ (u32*)hwkey, (u8*)crd->crd_key); ++#if 0 ++ printk("%s expanded key:", __FUNCTION__); ++ for (i = 0; i < (crd->crd_klen + 7) / 8; i++) ++ printk("%s0x%02x", (i % 8) ? " " : "\n ", ++ crd->crd_key[i]); ++ printk("\n"); ++#endif ++ } ++ } ++ } ++ else { /*decrypt */ ++ ++ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { ++ ivp = crd->crd_iv; ++ } else { ++ crypto_copydata(crp->crp_buf, crd->crd_inject, ++ ivsize, (caddr_t)ivp); ++ } ++ ++ c7108_xlate_key(crd->crd_klen, ++ (u8*)crd->crd_key, (u32*)hwkey); ++ ++ /* Decrypt SG list */ ++ for (i = 0; i < sg_num; i++) { ++ sg[i].dma_address = ++ dma_map_single(NULL, ++ kmap(sg_page(&sg[i])) + sg[i].offset, ++ sg_len, DMA_BIDIRECTIONAL); ++ ++#if 0 ++ printk("sg[%d]:0x%08x, off 0x%08x " ++ "kmap 0x%08x phys 0x%08x\n", ++ i, sg[i].page, sg[i].offset, ++ kmap(sg[i].page) + sg[i].offset, ++ sg[i].dma_address); ++#endif ++ c7108_aes_cipher(C7108_AES_DECRYPT, ++ sg[i].dma_address, ++ sg[i].dma_address, ++ sg_len, ++ crd->crd_klen, ++ c7108_crypto_mode, ++ hwkey, ++ ivp); ++ } ++ } ++ } break; ++ case SW_TYPE_HMAC: ++ case SW_TYPE_HASH: ++ crp->crp_etype = EINVAL; ++ goto done; ++ break; ++ ++ case SW_TYPE_COMP: ++ crp->crp_etype = EINVAL; ++ goto done; ++ break; ++ ++ default: ++ /* Unknown/unsupported algorithm */ ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ crp->crp_etype = EINVAL; ++ goto done; ++ } ++ } ++ ++done: ++ crypto_done(crp); ++ return 0; ++} ++ ++static struct { ++ softc_device_decl sc_dev; ++} a7108dev; ++ ++static device_method_t a7108_methods = { ++/* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, c7108_newsession), ++ DEVMETHOD(cryptodev_freesession, c7108_freesession), ++ DEVMETHOD(cryptodev_process, c7108_process), ++ DEVMETHOD(cryptodev_kprocess, NULL) ++}; ++ ++static int ++cypher_7108_crypto_init(void) ++{ ++ dprintk("%s(%p)\n", __FUNCTION__, cypher_7108_crypto_init); ++ ++ iobar = (unsigned long)ioremap(CCU_AES_REG_BASE, 0x4000); ++ printk("7108: AES @ 0x%08x (0x%08x phys) %s mode\n", ++ iobar, CCU_AES_REG_BASE, ++ c7108_crypto_mode & C7108_AES_CTRL_MODE_CBC ? "CBC" : ++ c7108_crypto_mode & C7108_AES_CTRL_MODE_ECB ? "ECB" : ++ c7108_crypto_mode & C7108_AES_CTRL_MODE_CTR ? "CTR" : ++ c7108_crypto_mode & C7108_AES_CTRL_MODE_CFB ? "CFB" : ++ c7108_crypto_mode & C7108_AES_CTRL_MODE_OFB ? "OFB" : "???"); ++ csr_mutex = SPIN_LOCK_UNLOCKED; ++ ++ memset(&a7108dev, 0, sizeof(a7108dev)); ++ softc_device_init(&a7108dev, "aes7108", 0, a7108_methods); ++ ++ c7108_id = crypto_get_driverid(softc_get_device(&a7108dev), CRYPTOCAP_F_HARDWARE); ++ if (c7108_id < 0) ++ panic("7108: crypto device cannot initialize!"); ++ ++// crypto_register(c7108_id, CRYPTO_AES_CBC, 0, 0, c7108_newsession, c7108_freesession, c7108_process, NULL); ++ crypto_register(c7108_id, CRYPTO_AES_CBC, 0, 0); ++ ++ return(0); ++} ++ ++static void ++cypher_7108_crypto_exit(void) ++{ ++ dprintk("%s()\n", __FUNCTION__); ++ crypto_unregister_all(c7108_id); ++ c7108_id = -1; ++} ++ ++module_init(cypher_7108_crypto_init); ++module_exit(cypher_7108_crypto_exit); ++ ++MODULE_LICENSE("Dual BSD/GPL"); ++MODULE_DESCRIPTION("Cypher 7108 Crypto (OCF module for kernel crypto)"); +diff -Nur linux-3.1.4.orig/crypto/ocf/c7108/aes-7108.h linux-3.1.4/crypto/ocf/c7108/aes-7108.h +--- linux-3.1.4.orig/crypto/ocf/c7108/aes-7108.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/c7108/aes-7108.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,134 @@ ++/* ++ * Copyright (C) 2006 Micronas USA ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored in part by the Defense Advanced Research Projects ++ * Agency (DARPA) and Air Force Research Laboratory, Air Force ++ * Materiel Command, USAF, under agreement number F30602-01-2-0537. ++ * ++ */ ++ ++#ifndef __AES_7108_H__ ++#define __AES_7108_H__ ++ ++/* Cypher 7108 AES Controller Hardware */ ++#define CCU_REG_BASE 0x1b500000 ++#define CCU_AES_REG_BASE (CCU_REG_BASE + 0x100) ++#define C7108_AES_KEY0_LO (0x0000) ++#define C7108_AES_KEY0_HI (0x0004) ++#define C7108_AES_KEY1_LO (0x0008) ++#define C7108_AES_KEY1_HI (0x000c) ++#define C7108_AES_KEY2_LO (0x0010) ++#define C7108_AES_KEY2_HI (0x0014) ++#define C7108_AES_KEY3_LO (0x0018) ++#define C7108_AES_KEY3_HI (0x001c) ++#define C7108_AES_KEY4_LO (0x0020) ++#define C7108_AES_KEY4_HI (0x0024) ++#define C7108_AES_KEY5_LO (0x0028) ++#define C7108_AES_KEY5_HI (0x002c) ++#define C7108_AES_KEY6_LO (0x0030) ++#define C7108_AES_KEY6_HI (0x0034) ++#define C7108_AES_KEY7_LO (0x0038) ++#define C7108_AES_KEY7_HI (0x003c) ++#define C7108_AES_IV0_LO (0x0040) ++#define C7108_AES_IV0_HI (0x0044) ++#define C7108_AES_IV1_LO (0x0048) ++#define C7108_AES_IV1_HI (0x004c) ++#define C7108_AES_IV2_LO (0x0050) ++#define C7108_AES_IV2_HI (0x0054) ++#define C7108_AES_IV3_LO (0x0058) ++#define C7108_AES_IV3_HI (0x005c) ++ ++#define C7108_AES_DMA_SRC0_LO (0x0068) /* Bits 0:15 */ ++#define C7108_AES_DMA_SRC0_HI (0x006c) /* Bits 27:16 */ ++#define C7108_AES_DMA_DST0_LO (0x0070) /* Bits 0:15 */ ++#define C7108_AES_DMA_DST0_HI (0x0074) /* Bits 27:16 */ ++#define C7108_AES_DMA_LEN (0x0078) /*Bytes:(Count+1)x16 */ ++ ++/* AES/Copy engine control register */ ++#define C7108_AES_CTRL (0x007c) /* AES control */ ++#define C7108_AES_CTRL_RS (1<<0) /* Which set of src/dst to use */ ++ ++/* AES Cipher mode, controlled by setting Bits 2:0 */ ++#define C7108_AES_CTRL_MODE_CBC 0 ++#define C7108_AES_CTRL_MODE_CFB (1<<0) ++#define C7108_AES_CTRL_MODE_OFB (1<<1) ++#define C7108_AES_CTRL_MODE_CTR ((1<<0)|(1<<1)) ++#define C7108_AES_CTRL_MODE_ECB (1<<2) ++ ++/* AES Key length , Bits 5:4 */ ++#define C7108_AES_KEY_LEN_128 0 /* 00 */ ++#define C7108_AES_KEY_LEN_192 (1<<4) /* 01 */ ++#define C7108_AES_KEY_LEN_256 (1<<5) /* 10 */ ++ ++/* AES Operation (crypt/decrypt), Bit 3 */ ++#define C7108_AES_DECRYPT (1<<3) /* Clear for encrypt */ ++#define C7108_AES_ENCRYPT 0 ++#define C7108_AES_INTR (1<<13) /* Set on done trans from 0->1*/ ++#define C7108_AES_GO (1<<14) /* Run */ ++#define C7108_AES_OP_DONE (1<<15) /* Set when complete */ ++ ++ ++/* Expanded key registers */ ++#define C7108_AES_EKEY0_LO (0x0080) ++#define C7108_AES_EKEY0_HI (0x0084) ++#define C7108_AES_EKEY1_LO (0x0088) ++#define C7108_AES_EKEY1_HI (0x008c) ++#define C7108_AES_EKEY2_LO (0x0090) ++#define C7108_AES_EKEY2_HI (0x0094) ++#define C7108_AES_EKEY3_LO (0x0098) ++#define C7108_AES_EKEY3_HI (0x009c) ++#define C7108_AES_EKEY4_LO (0x00a0) ++#define C7108_AES_EKEY4_HI (0x00a4) ++#define C7108_AES_EKEY5_LO (0x00a8) ++#define C7108_AES_EKEY5_HI (0x00ac) ++#define C7108_AES_EKEY6_LO (0x00b0) ++#define C7108_AES_EKEY6_HI (0x00b4) ++#define C7108_AES_EKEY7_LO (0x00b8) ++#define C7108_AES_EKEY7_HI (0x00bc) ++#define C7108_AES_OK (0x00fc) /* Reset: "OK" */ ++ ++#define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK) ++ ++/* Software session entry */ ++ ++#define HW_TYPE_CIPHER 0 ++#define SW_TYPE_HMAC 1 ++#define SW_TYPE_AUTH2 2 ++#define SW_TYPE_HASH 3 ++#define SW_TYPE_COMP 4 ++ ++struct cipher_7108 { ++ int xfm_type; ++ int cri_alg; ++ union { ++ struct { ++ char sw_key[HMAC_BLOCK_LEN]; ++ int sw_klen; ++ int sw_authlen; ++ } hmac; ++ } u; ++ struct cipher_7108 *next; ++}; ++ ++ ++ ++#endif /* __C7108_AES_7108_H__ */ +diff -Nur linux-3.1.4.orig/crypto/ocf/criov.c linux-3.1.4/crypto/ocf/criov.c +--- linux-3.1.4.orig/crypto/ocf/criov.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/criov.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,216 @@ ++/* $OpenBSD: criov.c,v 1.9 2002/01/29 15:48:29 jason Exp $ */ ++ ++/* ++ * Linux port done by David McCullough ++ * Copyright (C) 2006-2010 David McCullough ++ * Copyright (C) 2004-2005 Intel Corporation. ++ * The license and original author are listed below. ++ * ++ * Copyright (c) 1999 Theo de Raadt ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++__FBSDID("$FreeBSD: src/sys/opencrypto/criov.c,v 1.5 2006/06/04 22:15:13 pjd Exp $"); ++ */ ++ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++/* ++ * This macro is only for avoiding code duplication, as we need to skip ++ * given number of bytes in the same way in three functions below. ++ */ ++#define CUIO_SKIP() do { \ ++ KASSERT(off >= 0, ("%s: off %d < 0", __func__, off)); \ ++ KASSERT(len >= 0, ("%s: len %d < 0", __func__, len)); \ ++ while (off > 0) { \ ++ KASSERT(iol >= 0, ("%s: empty in skip", __func__)); \ ++ if (off < iov->iov_len) \ ++ break; \ ++ off -= iov->iov_len; \ ++ iol--; \ ++ iov++; \ ++ } \ ++} while (0) ++ ++void ++cuio_copydata(struct uio* uio, int off, int len, caddr_t cp) ++{ ++ struct iovec *iov = uio->uio_iov; ++ int iol = uio->uio_iovcnt; ++ unsigned count; ++ ++ CUIO_SKIP(); ++ while (len > 0) { ++ KASSERT(iol >= 0, ("%s: empty", __func__)); ++ count = min((int)(iov->iov_len - off), len); ++ memcpy(cp, ((caddr_t)iov->iov_base) + off, count); ++ len -= count; ++ cp += count; ++ off = 0; ++ iol--; ++ iov++; ++ } ++} ++ ++void ++cuio_copyback(struct uio* uio, int off, int len, caddr_t cp) ++{ ++ struct iovec *iov = uio->uio_iov; ++ int iol = uio->uio_iovcnt; ++ unsigned count; ++ ++ CUIO_SKIP(); ++ while (len > 0) { ++ KASSERT(iol >= 0, ("%s: empty", __func__)); ++ count = min((int)(iov->iov_len - off), len); ++ memcpy(((caddr_t)iov->iov_base) + off, cp, count); ++ len -= count; ++ cp += count; ++ off = 0; ++ iol--; ++ iov++; ++ } ++} ++ ++/* ++ * Return a pointer to iov/offset of location in iovec list. ++ */ ++struct iovec * ++cuio_getptr(struct uio *uio, int loc, int *off) ++{ ++ struct iovec *iov = uio->uio_iov; ++ int iol = uio->uio_iovcnt; ++ ++ while (loc >= 0) { ++ /* Normal end of search */ ++ if (loc < iov->iov_len) { ++ *off = loc; ++ return (iov); ++ } ++ ++ loc -= iov->iov_len; ++ if (iol == 0) { ++ if (loc == 0) { ++ /* Point at the end of valid data */ ++ *off = iov->iov_len; ++ return (iov); ++ } else ++ return (NULL); ++ } else { ++ iov++, iol--; ++ } ++ } ++ ++ return (NULL); ++} ++ ++EXPORT_SYMBOL(cuio_copyback); ++EXPORT_SYMBOL(cuio_copydata); ++EXPORT_SYMBOL(cuio_getptr); ++ ++ ++static void ++skb_copy_bits_back(struct sk_buff *skb, int offset, caddr_t cp, int len) ++{ ++ int i; ++ if (offset < skb_headlen(skb)) { ++ memcpy(skb->data + offset, cp, min_t(int, skb_headlen(skb), len)); ++ len -= skb_headlen(skb); ++ cp += skb_headlen(skb); ++ } ++ offset -= skb_headlen(skb); ++ for (i = 0; len > 0 && i < skb_shinfo(skb)->nr_frags; i++) { ++ if (offset < skb_shinfo(skb)->frags[i].size) { ++ memcpy(page_address(skb_shinfo(skb)->frags[i].page) + ++ skb_shinfo(skb)->frags[i].page_offset, ++ cp, min_t(int, skb_shinfo(skb)->frags[i].size, len)); ++ len -= skb_shinfo(skb)->frags[i].size; ++ cp += skb_shinfo(skb)->frags[i].size; ++ } ++ offset -= skb_shinfo(skb)->frags[i].size; ++ } ++} ++ ++void ++crypto_copyback(int flags, caddr_t buf, int off, int size, caddr_t in) ++{ ++ ++ if ((flags & CRYPTO_F_SKBUF) != 0) ++ skb_copy_bits_back((struct sk_buff *)buf, off, in, size); ++ else if ((flags & CRYPTO_F_IOV) != 0) ++ cuio_copyback((struct uio *)buf, off, size, in); ++ else ++ bcopy(in, buf + off, size); ++} ++ ++void ++crypto_copydata(int flags, caddr_t buf, int off, int size, caddr_t out) ++{ ++ ++ if ((flags & CRYPTO_F_SKBUF) != 0) ++ skb_copy_bits((struct sk_buff *)buf, off, out, size); ++ else if ((flags & CRYPTO_F_IOV) != 0) ++ cuio_copydata((struct uio *)buf, off, size, out); ++ else ++ bcopy(buf + off, out, size); ++} ++ ++int ++crypto_apply(int flags, caddr_t buf, int off, int len, ++ int (*f)(void *, void *, u_int), void *arg) ++{ ++#if 0 ++ int error; ++ ++ if ((flags & CRYPTO_F_SKBUF) != 0) ++ error = XXXXXX((struct mbuf *)buf, off, len, f, arg); ++ else if ((flags & CRYPTO_F_IOV) != 0) ++ error = cuio_apply((struct uio *)buf, off, len, f, arg); ++ else ++ error = (*f)(arg, buf + off, len); ++ return (error); ++#else ++ KASSERT(0, ("crypto_apply not implemented!\n")); ++#endif ++ return 0; ++} ++ ++EXPORT_SYMBOL(crypto_copyback); ++EXPORT_SYMBOL(crypto_copydata); ++EXPORT_SYMBOL(crypto_apply); ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/crypto.c linux-3.1.4/crypto/ocf/crypto.c +--- linux-3.1.4.orig/crypto/ocf/crypto.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/crypto.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,1766 @@ ++/*- ++ * Linux port done by David McCullough ++ * Copyright (C) 2006-2010 David McCullough ++ * Copyright (C) 2004-2005 Intel Corporation. ++ * The license and original author are listed below. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * Copyright (c) 2002-2006 Sam Leffler. All rights reserved. ++ * ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#if 0 ++#include ++__FBSDID("$FreeBSD: src/sys/opencrypto/crypto.c,v 1.27 2007/03/21 03:42:51 sam Exp $"); ++#endif ++ ++/* ++ * Cryptographic Subsystem. ++ * ++ * This code is derived from the Openbsd Cryptographic Framework (OCF) ++ * that has the copyright shown below. Very little of the original ++ * code remains. ++ */ ++/*- ++ * The author of this code is Angelos D. Keromytis (angelos@cis.upenn.edu) ++ * ++ * This code was written by Angelos D. Keromytis in Athens, Greece, in ++ * February 2000. Network Security Technologies Inc. (NSTI) kindly ++ * supported the development of this code. ++ * ++ * Copyright (c) 2000, 2001 Angelos D. Keromytis ++ * ++ * Permission to use, copy, and modify this software with or without fee ++ * is hereby granted, provided that this entire notice is included in ++ * all source code copies of any software which is or includes a copy or ++ * modification of this software. ++ * ++ * THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR ++ * IMPLIED WARRANTY. IN PARTICULAR, NONE OF THE AUTHORS MAKES ANY ++ * REPRESENTATION OR WARRANTY OF ANY KIND CONCERNING THE ++ * MERCHANTABILITY OF THIS SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR ++ * PURPOSE. ++ * ++__FBSDID("$FreeBSD: src/sys/opencrypto/crypto.c,v 1.16 2005/01/07 02:29:16 imp Exp $"); ++ */ ++ ++ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,4) ++#include ++#endif ++#include ++ ++/* ++ * keep track of whether or not we have been initialised, a big ++ * issue if we are linked into the kernel and a driver gets started before ++ * us ++ */ ++static int crypto_initted = 0; ++ ++/* ++ * Crypto drivers register themselves by allocating a slot in the ++ * crypto_drivers table with crypto_get_driverid() and then registering ++ * each algorithm they support with crypto_register() and crypto_kregister(). ++ */ ++ ++/* ++ * lock on driver table ++ * we track its state as spin_is_locked does not do anything on non-SMP boxes ++ */ ++static spinlock_t crypto_drivers_lock; ++static int crypto_drivers_locked; /* for non-SMP boxes */ ++ ++#define CRYPTO_DRIVER_LOCK() \ ++ ({ \ ++ spin_lock_irqsave(&crypto_drivers_lock, d_flags); \ ++ crypto_drivers_locked = 1; \ ++ dprintk("%s,%d: DRIVER_LOCK()\n", __FILE__, __LINE__); \ ++ }) ++#define CRYPTO_DRIVER_UNLOCK() \ ++ ({ \ ++ dprintk("%s,%d: DRIVER_UNLOCK()\n", __FILE__, __LINE__); \ ++ crypto_drivers_locked = 0; \ ++ spin_unlock_irqrestore(&crypto_drivers_lock, d_flags); \ ++ }) ++#define CRYPTO_DRIVER_ASSERT() \ ++ ({ \ ++ if (!crypto_drivers_locked) { \ ++ dprintk("%s,%d: DRIVER_ASSERT!\n", __FILE__, __LINE__); \ ++ } \ ++ }) ++ ++/* ++ * Crypto device/driver capabilities structure. ++ * ++ * Synchronization: ++ * (d) - protected by CRYPTO_DRIVER_LOCK() ++ * (q) - protected by CRYPTO_Q_LOCK() ++ * Not tagged fields are read-only. ++ */ ++struct cryptocap { ++ device_t cc_dev; /* (d) device/driver */ ++ u_int32_t cc_sessions; /* (d) # of sessions */ ++ u_int32_t cc_koperations; /* (d) # os asym operations */ ++ /* ++ * Largest possible operator length (in bits) for each type of ++ * encryption algorithm. XXX not used ++ */ ++ u_int16_t cc_max_op_len[CRYPTO_ALGORITHM_MAX + 1]; ++ u_int8_t cc_alg[CRYPTO_ALGORITHM_MAX + 1]; ++ u_int8_t cc_kalg[CRK_ALGORITHM_MAX + 1]; ++ ++ int cc_flags; /* (d) flags */ ++#define CRYPTOCAP_F_CLEANUP 0x80000000 /* needs resource cleanup */ ++ int cc_qblocked; /* (q) symmetric q blocked */ ++ int cc_kqblocked; /* (q) asymmetric q blocked */ ++ ++ int cc_unqblocked; /* (q) symmetric q blocked */ ++ int cc_unkqblocked; /* (q) asymmetric q blocked */ ++}; ++static struct cryptocap *crypto_drivers = NULL; ++static int crypto_drivers_num = 0; ++ ++/* ++ * There are two queues for crypto requests; one for symmetric (e.g. ++ * cipher) operations and one for asymmetric (e.g. MOD)operations. ++ * A single mutex is used to lock access to both queues. We could ++ * have one per-queue but having one simplifies handling of block/unblock ++ * operations. ++ */ ++static LIST_HEAD(crp_q); /* crypto request queue */ ++static LIST_HEAD(crp_kq); /* asym request queue */ ++ ++static spinlock_t crypto_q_lock; ++ ++int crypto_all_qblocked = 0; /* protect with Q_LOCK */ ++module_param(crypto_all_qblocked, int, 0444); ++MODULE_PARM_DESC(crypto_all_qblocked, "Are all crypto queues blocked"); ++ ++int crypto_all_kqblocked = 0; /* protect with Q_LOCK */ ++module_param(crypto_all_kqblocked, int, 0444); ++MODULE_PARM_DESC(crypto_all_kqblocked, "Are all asym crypto queues blocked"); ++ ++#define CRYPTO_Q_LOCK() \ ++ ({ \ ++ spin_lock_irqsave(&crypto_q_lock, q_flags); \ ++ dprintk("%s,%d: Q_LOCK()\n", __FILE__, __LINE__); \ ++ }) ++#define CRYPTO_Q_UNLOCK() \ ++ ({ \ ++ dprintk("%s,%d: Q_UNLOCK()\n", __FILE__, __LINE__); \ ++ spin_unlock_irqrestore(&crypto_q_lock, q_flags); \ ++ }) ++ ++/* ++ * There are two queues for processing completed crypto requests; one ++ * for the symmetric and one for the asymmetric ops. We only need one ++ * but have two to avoid type futzing (cryptop vs. cryptkop). A single ++ * mutex is used to lock access to both queues. Note that this lock ++ * must be separate from the lock on request queues to insure driver ++ * callbacks don't generate lock order reversals. ++ */ ++static LIST_HEAD(crp_ret_q); /* callback queues */ ++static LIST_HEAD(crp_ret_kq); ++ ++static spinlock_t crypto_ret_q_lock; ++#define CRYPTO_RETQ_LOCK() \ ++ ({ \ ++ spin_lock_irqsave(&crypto_ret_q_lock, r_flags); \ ++ dprintk("%s,%d: RETQ_LOCK\n", __FILE__, __LINE__); \ ++ }) ++#define CRYPTO_RETQ_UNLOCK() \ ++ ({ \ ++ dprintk("%s,%d: RETQ_UNLOCK\n", __FILE__, __LINE__); \ ++ spin_unlock_irqrestore(&crypto_ret_q_lock, r_flags); \ ++ }) ++#define CRYPTO_RETQ_EMPTY() (list_empty(&crp_ret_q) && list_empty(&crp_ret_kq)) ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) ++static kmem_cache_t *cryptop_zone; ++static kmem_cache_t *cryptodesc_zone; ++#else ++static struct kmem_cache *cryptop_zone; ++static struct kmem_cache *cryptodesc_zone; ++#endif ++ ++#define debug crypto_debug ++int crypto_debug = 0; ++module_param(crypto_debug, int, 0644); ++MODULE_PARM_DESC(crypto_debug, "Enable debug"); ++EXPORT_SYMBOL(crypto_debug); ++ ++/* ++ * Maximum number of outstanding crypto requests before we start ++ * failing requests. We need this to prevent DOS when too many ++ * requests are arriving for us to keep up. Otherwise we will ++ * run the system out of memory. Since crypto is slow, we are ++ * usually the bottleneck that needs to say, enough is enough. ++ * ++ * We cannot print errors when this condition occurs, we are already too ++ * slow, printing anything will just kill us ++ */ ++ ++static int crypto_q_cnt = 0; ++module_param(crypto_q_cnt, int, 0444); ++MODULE_PARM_DESC(crypto_q_cnt, ++ "Current number of outstanding crypto requests"); ++ ++static int crypto_q_max = 1000; ++module_param(crypto_q_max, int, 0644); ++MODULE_PARM_DESC(crypto_q_max, ++ "Maximum number of outstanding crypto requests"); ++ ++#define bootverbose crypto_verbose ++static int crypto_verbose = 0; ++module_param(crypto_verbose, int, 0644); ++MODULE_PARM_DESC(crypto_verbose, ++ "Enable verbose crypto startup"); ++ ++int crypto_usercrypto = 1; /* userland may do crypto reqs */ ++module_param(crypto_usercrypto, int, 0644); ++MODULE_PARM_DESC(crypto_usercrypto, ++ "Enable/disable user-mode access to crypto support"); ++ ++int crypto_userasymcrypto = 1; /* userland may do asym crypto reqs */ ++module_param(crypto_userasymcrypto, int, 0644); ++MODULE_PARM_DESC(crypto_userasymcrypto, ++ "Enable/disable user-mode access to asymmetric crypto support"); ++ ++int crypto_devallowsoft = 0; /* only use hardware crypto */ ++module_param(crypto_devallowsoft, int, 0644); ++MODULE_PARM_DESC(crypto_devallowsoft, ++ "Enable/disable use of software crypto support"); ++ ++/* ++ * This parameter controls the maximum number of crypto operations to ++ * do consecutively in the crypto kernel thread before scheduling to allow ++ * other processes to run. Without it, it is possible to get into a ++ * situation where the crypto thread never allows any other processes to run. ++ * Default to 1000 which should be less than one second. ++ */ ++static int crypto_max_loopcount = 1000; ++module_param(crypto_max_loopcount, int, 0644); ++MODULE_PARM_DESC(crypto_max_loopcount, ++ "Maximum number of crypto ops to do before yielding to other processes"); ++ ++#ifndef CONFIG_NR_CPUS ++#define CONFIG_NR_CPUS 1 ++#endif ++ ++static struct task_struct *cryptoproc[CONFIG_NR_CPUS]; ++static struct task_struct *cryptoretproc[CONFIG_NR_CPUS]; ++static DECLARE_WAIT_QUEUE_HEAD(cryptoproc_wait); ++static DECLARE_WAIT_QUEUE_HEAD(cryptoretproc_wait); ++ ++static int crypto_proc(void *arg); ++static int crypto_ret_proc(void *arg); ++static int crypto_invoke(struct cryptocap *cap, struct cryptop *crp, int hint); ++static int crypto_kinvoke(struct cryptkop *krp, int flags); ++static void crypto_exit(void); ++static int crypto_init(void); ++ ++static struct cryptostats cryptostats; ++ ++static struct cryptocap * ++crypto_checkdriver(u_int32_t hid) ++{ ++ if (crypto_drivers == NULL) ++ return NULL; ++ return (hid >= crypto_drivers_num ? NULL : &crypto_drivers[hid]); ++} ++ ++/* ++ * Compare a driver's list of supported algorithms against another ++ * list; return non-zero if all algorithms are supported. ++ */ ++static int ++driver_suitable(const struct cryptocap *cap, const struct cryptoini *cri) ++{ ++ const struct cryptoini *cr; ++ ++ /* See if all the algorithms are supported. */ ++ for (cr = cri; cr; cr = cr->cri_next) ++ if (cap->cc_alg[cr->cri_alg] == 0) ++ return 0; ++ return 1; ++} ++ ++ ++/* ++ * Select a driver for a new session that supports the specified ++ * algorithms and, optionally, is constrained according to the flags. ++ * The algorithm we use here is pretty stupid; just use the ++ * first driver that supports all the algorithms we need. If there ++ * are multiple drivers we choose the driver with the fewest active ++ * sessions. We prefer hardware-backed drivers to software ones. ++ * ++ * XXX We need more smarts here (in real life too, but that's ++ * XXX another story altogether). ++ */ ++static struct cryptocap * ++crypto_select_driver(const struct cryptoini *cri, int flags) ++{ ++ struct cryptocap *cap, *best; ++ int match, hid; ++ ++ CRYPTO_DRIVER_ASSERT(); ++ ++ /* ++ * Look first for hardware crypto devices if permitted. ++ */ ++ if (flags & CRYPTOCAP_F_HARDWARE) ++ match = CRYPTOCAP_F_HARDWARE; ++ else ++ match = CRYPTOCAP_F_SOFTWARE; ++ best = NULL; ++again: ++ for (hid = 0; hid < crypto_drivers_num; hid++) { ++ cap = &crypto_drivers[hid]; ++ /* ++ * If it's not initialized, is in the process of ++ * going away, or is not appropriate (hardware ++ * or software based on match), then skip. ++ */ ++ if (cap->cc_dev == NULL || ++ (cap->cc_flags & CRYPTOCAP_F_CLEANUP) || ++ (cap->cc_flags & match) == 0) ++ continue; ++ ++ /* verify all the algorithms are supported. */ ++ if (driver_suitable(cap, cri)) { ++ if (best == NULL || ++ cap->cc_sessions < best->cc_sessions) ++ best = cap; ++ } ++ } ++ if (best != NULL) ++ return best; ++ if (match == CRYPTOCAP_F_HARDWARE && (flags & CRYPTOCAP_F_SOFTWARE)) { ++ /* sort of an Algol 68-style for loop */ ++ match = CRYPTOCAP_F_SOFTWARE; ++ goto again; ++ } ++ return best; ++} ++ ++/* ++ * Create a new session. The crid argument specifies a crypto ++ * driver to use or constraints on a driver to select (hardware ++ * only, software only, either). Whatever driver is selected ++ * must be capable of the requested crypto algorithms. ++ */ ++int ++crypto_newsession(u_int64_t *sid, struct cryptoini *cri, int crid) ++{ ++ struct cryptocap *cap; ++ u_int32_t hid, lid; ++ int err; ++ unsigned long d_flags; ++ ++ CRYPTO_DRIVER_LOCK(); ++ if ((crid & (CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE)) == 0) { ++ /* ++ * Use specified driver; verify it is capable. ++ */ ++ cap = crypto_checkdriver(crid); ++ if (cap != NULL && !driver_suitable(cap, cri)) ++ cap = NULL; ++ } else { ++ /* ++ * No requested driver; select based on crid flags. ++ */ ++ cap = crypto_select_driver(cri, crid); ++ /* ++ * if NULL then can't do everything in one session. ++ * XXX Fix this. We need to inject a "virtual" session ++ * XXX layer right about here. ++ */ ++ } ++ if (cap != NULL) { ++ /* Call the driver initialization routine. */ ++ hid = cap - crypto_drivers; ++ lid = hid; /* Pass the driver ID. */ ++ cap->cc_sessions++; ++ CRYPTO_DRIVER_UNLOCK(); ++ err = CRYPTODEV_NEWSESSION(cap->cc_dev, &lid, cri); ++ CRYPTO_DRIVER_LOCK(); ++ if (err == 0) { ++ (*sid) = (cap->cc_flags & 0xff000000) ++ | (hid & 0x00ffffff); ++ (*sid) <<= 32; ++ (*sid) |= (lid & 0xffffffff); ++ } else ++ cap->cc_sessions--; ++ } else ++ err = EINVAL; ++ CRYPTO_DRIVER_UNLOCK(); ++ return err; ++} ++ ++static void ++crypto_remove(struct cryptocap *cap) ++{ ++ CRYPTO_DRIVER_ASSERT(); ++ if (cap->cc_sessions == 0 && cap->cc_koperations == 0) ++ bzero(cap, sizeof(*cap)); ++} ++ ++/* ++ * Delete an existing session (or a reserved session on an unregistered ++ * driver). ++ */ ++int ++crypto_freesession(u_int64_t sid) ++{ ++ struct cryptocap *cap; ++ u_int32_t hid; ++ int err = 0; ++ unsigned long d_flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ CRYPTO_DRIVER_LOCK(); ++ ++ if (crypto_drivers == NULL) { ++ err = EINVAL; ++ goto done; ++ } ++ ++ /* Determine two IDs. */ ++ hid = CRYPTO_SESID2HID(sid); ++ ++ if (hid >= crypto_drivers_num) { ++ dprintk("%s - INVALID DRIVER NUM %d\n", __FUNCTION__, hid); ++ err = ENOENT; ++ goto done; ++ } ++ cap = &crypto_drivers[hid]; ++ ++ if (cap->cc_dev) { ++ CRYPTO_DRIVER_UNLOCK(); ++ /* Call the driver cleanup routine, if available, unlocked. */ ++ err = CRYPTODEV_FREESESSION(cap->cc_dev, sid); ++ CRYPTO_DRIVER_LOCK(); ++ } ++ ++ if (cap->cc_sessions) ++ cap->cc_sessions--; ++ ++ if (cap->cc_flags & CRYPTOCAP_F_CLEANUP) ++ crypto_remove(cap); ++ ++done: ++ CRYPTO_DRIVER_UNLOCK(); ++ return err; ++} ++ ++/* ++ * Return an unused driver id. Used by drivers prior to registering ++ * support for the algorithms they handle. ++ */ ++int32_t ++crypto_get_driverid(device_t dev, int flags) ++{ ++ struct cryptocap *newdrv; ++ int i; ++ unsigned long d_flags; ++ ++ if ((flags & (CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE)) == 0) { ++ printf("%s: no flags specified when registering driver\n", ++ device_get_nameunit(dev)); ++ return -1; ++ } ++ ++ CRYPTO_DRIVER_LOCK(); ++ ++ for (i = 0; i < crypto_drivers_num; i++) { ++ if (crypto_drivers[i].cc_dev == NULL && ++ (crypto_drivers[i].cc_flags & CRYPTOCAP_F_CLEANUP) == 0) { ++ break; ++ } ++ } ++ ++ /* Out of entries, allocate some more. */ ++ if (i == crypto_drivers_num) { ++ /* Be careful about wrap-around. */ ++ if (2 * crypto_drivers_num <= crypto_drivers_num) { ++ CRYPTO_DRIVER_UNLOCK(); ++ printk("crypto: driver count wraparound!\n"); ++ return -1; ++ } ++ ++ newdrv = kmalloc(2 * crypto_drivers_num * sizeof(struct cryptocap), ++ GFP_KERNEL); ++ if (newdrv == NULL) { ++ CRYPTO_DRIVER_UNLOCK(); ++ printk("crypto: no space to expand driver table!\n"); ++ return -1; ++ } ++ ++ memcpy(newdrv, crypto_drivers, ++ crypto_drivers_num * sizeof(struct cryptocap)); ++ memset(&newdrv[crypto_drivers_num], 0, ++ crypto_drivers_num * sizeof(struct cryptocap)); ++ ++ crypto_drivers_num *= 2; ++ ++ kfree(crypto_drivers); ++ crypto_drivers = newdrv; ++ } ++ ++ /* NB: state is zero'd on free */ ++ crypto_drivers[i].cc_sessions = 1; /* Mark */ ++ crypto_drivers[i].cc_dev = dev; ++ crypto_drivers[i].cc_flags = flags; ++ if (bootverbose) ++ printf("crypto: assign %s driver id %u, flags %u\n", ++ device_get_nameunit(dev), i, flags); ++ ++ CRYPTO_DRIVER_UNLOCK(); ++ ++ return i; ++} ++ ++/* ++ * Lookup a driver by name. We match against the full device ++ * name and unit, and against just the name. The latter gives ++ * us a simple widlcarding by device name. On success return the ++ * driver/hardware identifier; otherwise return -1. ++ */ ++int ++crypto_find_driver(const char *match) ++{ ++ int i, len = strlen(match); ++ unsigned long d_flags; ++ ++ CRYPTO_DRIVER_LOCK(); ++ for (i = 0; i < crypto_drivers_num; i++) { ++ device_t dev = crypto_drivers[i].cc_dev; ++ if (dev == NULL || ++ (crypto_drivers[i].cc_flags & CRYPTOCAP_F_CLEANUP)) ++ continue; ++ if (strncmp(match, device_get_nameunit(dev), len) == 0 || ++ strncmp(match, device_get_name(dev), len) == 0) ++ break; ++ } ++ CRYPTO_DRIVER_UNLOCK(); ++ return i < crypto_drivers_num ? i : -1; ++} ++ ++/* ++ * Return the device_t for the specified driver or NULL ++ * if the driver identifier is invalid. ++ */ ++device_t ++crypto_find_device_byhid(int hid) ++{ ++ struct cryptocap *cap = crypto_checkdriver(hid); ++ return cap != NULL ? cap->cc_dev : NULL; ++} ++ ++/* ++ * Return the device/driver capabilities. ++ */ ++int ++crypto_getcaps(int hid) ++{ ++ struct cryptocap *cap = crypto_checkdriver(hid); ++ return cap != NULL ? cap->cc_flags : 0; ++} ++ ++/* ++ * Register support for a key-related algorithm. This routine ++ * is called once for each algorithm supported a driver. ++ */ ++int ++crypto_kregister(u_int32_t driverid, int kalg, u_int32_t flags) ++{ ++ struct cryptocap *cap; ++ int err; ++ unsigned long d_flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ CRYPTO_DRIVER_LOCK(); ++ ++ cap = crypto_checkdriver(driverid); ++ if (cap != NULL && ++ (CRK_ALGORITM_MIN <= kalg && kalg <= CRK_ALGORITHM_MAX)) { ++ /* ++ * XXX Do some performance testing to determine placing. ++ * XXX We probably need an auxiliary data structure that ++ * XXX describes relative performances. ++ */ ++ ++ cap->cc_kalg[kalg] = flags | CRYPTO_ALG_FLAG_SUPPORTED; ++ if (bootverbose) ++ printf("crypto: %s registers key alg %u flags %u\n" ++ , device_get_nameunit(cap->cc_dev) ++ , kalg ++ , flags ++ ); ++ err = 0; ++ } else ++ err = EINVAL; ++ ++ CRYPTO_DRIVER_UNLOCK(); ++ return err; ++} ++ ++/* ++ * Register support for a non-key-related algorithm. This routine ++ * is called once for each such algorithm supported by a driver. ++ */ ++int ++crypto_register(u_int32_t driverid, int alg, u_int16_t maxoplen, ++ u_int32_t flags) ++{ ++ struct cryptocap *cap; ++ int err; ++ unsigned long d_flags; ++ ++ dprintk("%s(id=0x%x, alg=%d, maxoplen=%d, flags=0x%x)\n", __FUNCTION__, ++ driverid, alg, maxoplen, flags); ++ ++ CRYPTO_DRIVER_LOCK(); ++ ++ cap = crypto_checkdriver(driverid); ++ /* NB: algorithms are in the range [1..max] */ ++ if (cap != NULL && ++ (CRYPTO_ALGORITHM_MIN <= alg && alg <= CRYPTO_ALGORITHM_MAX)) { ++ /* ++ * XXX Do some performance testing to determine placing. ++ * XXX We probably need an auxiliary data structure that ++ * XXX describes relative performances. ++ */ ++ ++ cap->cc_alg[alg] = flags | CRYPTO_ALG_FLAG_SUPPORTED; ++ cap->cc_max_op_len[alg] = maxoplen; ++ if (bootverbose) ++ printf("crypto: %s registers alg %u flags %u maxoplen %u\n" ++ , device_get_nameunit(cap->cc_dev) ++ , alg ++ , flags ++ , maxoplen ++ ); ++ cap->cc_sessions = 0; /* Unmark */ ++ err = 0; ++ } else ++ err = EINVAL; ++ ++ CRYPTO_DRIVER_UNLOCK(); ++ return err; ++} ++ ++static void ++driver_finis(struct cryptocap *cap) ++{ ++ u_int32_t ses, kops; ++ ++ CRYPTO_DRIVER_ASSERT(); ++ ++ ses = cap->cc_sessions; ++ kops = cap->cc_koperations; ++ bzero(cap, sizeof(*cap)); ++ if (ses != 0 || kops != 0) { ++ /* ++ * If there are pending sessions, ++ * just mark as invalid. ++ */ ++ cap->cc_flags |= CRYPTOCAP_F_CLEANUP; ++ cap->cc_sessions = ses; ++ cap->cc_koperations = kops; ++ } ++} ++ ++/* ++ * Unregister a crypto driver. If there are pending sessions using it, ++ * leave enough information around so that subsequent calls using those ++ * sessions will correctly detect the driver has been unregistered and ++ * reroute requests. ++ */ ++int ++crypto_unregister(u_int32_t driverid, int alg) ++{ ++ struct cryptocap *cap; ++ int i, err; ++ unsigned long d_flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ CRYPTO_DRIVER_LOCK(); ++ ++ cap = crypto_checkdriver(driverid); ++ if (cap != NULL && ++ (CRYPTO_ALGORITHM_MIN <= alg && alg <= CRYPTO_ALGORITHM_MAX) && ++ cap->cc_alg[alg] != 0) { ++ cap->cc_alg[alg] = 0; ++ cap->cc_max_op_len[alg] = 0; ++ ++ /* Was this the last algorithm ? */ ++ for (i = 1; i <= CRYPTO_ALGORITHM_MAX; i++) ++ if (cap->cc_alg[i] != 0) ++ break; ++ ++ if (i == CRYPTO_ALGORITHM_MAX + 1) ++ driver_finis(cap); ++ err = 0; ++ } else ++ err = EINVAL; ++ CRYPTO_DRIVER_UNLOCK(); ++ return err; ++} ++ ++/* ++ * Unregister all algorithms associated with a crypto driver. ++ * If there are pending sessions using it, leave enough information ++ * around so that subsequent calls using those sessions will ++ * correctly detect the driver has been unregistered and reroute ++ * requests. ++ */ ++int ++crypto_unregister_all(u_int32_t driverid) ++{ ++ struct cryptocap *cap; ++ int err; ++ unsigned long d_flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ CRYPTO_DRIVER_LOCK(); ++ cap = crypto_checkdriver(driverid); ++ if (cap != NULL) { ++ driver_finis(cap); ++ err = 0; ++ } else ++ err = EINVAL; ++ CRYPTO_DRIVER_UNLOCK(); ++ ++ return err; ++} ++ ++/* ++ * Clear blockage on a driver. The what parameter indicates whether ++ * the driver is now ready for cryptop's and/or cryptokop's. ++ */ ++int ++crypto_unblock(u_int32_t driverid, int what) ++{ ++ struct cryptocap *cap; ++ int err; ++ unsigned long q_flags; ++ ++ CRYPTO_Q_LOCK(); ++ cap = crypto_checkdriver(driverid); ++ if (cap != NULL) { ++ if (what & CRYPTO_SYMQ) { ++ cap->cc_qblocked = 0; ++ cap->cc_unqblocked = 0; ++ crypto_all_qblocked = 0; ++ } ++ if (what & CRYPTO_ASYMQ) { ++ cap->cc_kqblocked = 0; ++ cap->cc_unkqblocked = 0; ++ crypto_all_kqblocked = 0; ++ } ++ wake_up_interruptible(&cryptoproc_wait); ++ err = 0; ++ } else ++ err = EINVAL; ++ CRYPTO_Q_UNLOCK(); //DAVIDM should this be a driver lock ++ ++ return err; ++} ++ ++/* ++ * Add a crypto request to a queue, to be processed by the kernel thread. ++ */ ++int ++crypto_dispatch(struct cryptop *crp) ++{ ++ struct cryptocap *cap; ++ int result = -1; ++ unsigned long q_flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ cryptostats.cs_ops++; ++ ++ CRYPTO_Q_LOCK(); ++ if (crypto_q_cnt >= crypto_q_max) { ++ cryptostats.cs_drops++; ++ CRYPTO_Q_UNLOCK(); ++ return ENOMEM; ++ } ++ crypto_q_cnt++; ++ ++ /* make sure we are starting a fresh run on this crp. */ ++ crp->crp_flags &= ~CRYPTO_F_DONE; ++ crp->crp_etype = 0; ++ ++ /* ++ * Caller marked the request to be processed immediately; dispatch ++ * it directly to the driver unless the driver is currently blocked. ++ */ ++ if ((crp->crp_flags & CRYPTO_F_BATCH) == 0) { ++ int hid = CRYPTO_SESID2HID(crp->crp_sid); ++ cap = crypto_checkdriver(hid); ++ /* Driver cannot disappear when there is an active session. */ ++ KASSERT(cap != NULL, ("%s: Driver disappeared.", __func__)); ++ if (!cap->cc_qblocked) { ++ crypto_all_qblocked = 0; ++ crypto_drivers[hid].cc_unqblocked = 1; ++ CRYPTO_Q_UNLOCK(); ++ result = crypto_invoke(cap, crp, 0); ++ CRYPTO_Q_LOCK(); ++ if (result == ERESTART) ++ if (crypto_drivers[hid].cc_unqblocked) ++ crypto_drivers[hid].cc_qblocked = 1; ++ crypto_drivers[hid].cc_unqblocked = 0; ++ } ++ } ++ if (result == ERESTART) { ++ /* ++ * The driver ran out of resources, mark the ++ * driver ``blocked'' for cryptop's and put ++ * the request back in the queue. It would ++ * best to put the request back where we got ++ * it but that's hard so for now we put it ++ * at the front. This should be ok; putting ++ * it at the end does not work. ++ */ ++ list_add(&crp->crp_next, &crp_q); ++ cryptostats.cs_blocks++; ++ result = 0; ++ } else if (result == -1) { ++ TAILQ_INSERT_TAIL(&crp_q, crp, crp_next); ++ result = 0; ++ } ++ wake_up_interruptible(&cryptoproc_wait); ++ CRYPTO_Q_UNLOCK(); ++ return result; ++} ++ ++/* ++ * Add an asymetric crypto request to a queue, ++ * to be processed by the kernel thread. ++ */ ++int ++crypto_kdispatch(struct cryptkop *krp) ++{ ++ int error; ++ unsigned long q_flags; ++ ++ cryptostats.cs_kops++; ++ ++ error = crypto_kinvoke(krp, krp->krp_crid); ++ if (error == ERESTART) { ++ CRYPTO_Q_LOCK(); ++ TAILQ_INSERT_TAIL(&crp_kq, krp, krp_next); ++ wake_up_interruptible(&cryptoproc_wait); ++ CRYPTO_Q_UNLOCK(); ++ error = 0; ++ } ++ return error; ++} ++ ++/* ++ * Verify a driver is suitable for the specified operation. ++ */ ++static __inline int ++kdriver_suitable(const struct cryptocap *cap, const struct cryptkop *krp) ++{ ++ return (cap->cc_kalg[krp->krp_op] & CRYPTO_ALG_FLAG_SUPPORTED) != 0; ++} ++ ++/* ++ * Select a driver for an asym operation. The driver must ++ * support the necessary algorithm. The caller can constrain ++ * which device is selected with the flags parameter. The ++ * algorithm we use here is pretty stupid; just use the first ++ * driver that supports the algorithms we need. If there are ++ * multiple suitable drivers we choose the driver with the ++ * fewest active operations. We prefer hardware-backed ++ * drivers to software ones when either may be used. ++ */ ++static struct cryptocap * ++crypto_select_kdriver(const struct cryptkop *krp, int flags) ++{ ++ struct cryptocap *cap, *best, *blocked; ++ int match, hid; ++ ++ CRYPTO_DRIVER_ASSERT(); ++ ++ /* ++ * Look first for hardware crypto devices if permitted. ++ */ ++ if (flags & CRYPTOCAP_F_HARDWARE) ++ match = CRYPTOCAP_F_HARDWARE; ++ else ++ match = CRYPTOCAP_F_SOFTWARE; ++ best = NULL; ++ blocked = NULL; ++again: ++ for (hid = 0; hid < crypto_drivers_num; hid++) { ++ cap = &crypto_drivers[hid]; ++ /* ++ * If it's not initialized, is in the process of ++ * going away, or is not appropriate (hardware ++ * or software based on match), then skip. ++ */ ++ if (cap->cc_dev == NULL || ++ (cap->cc_flags & CRYPTOCAP_F_CLEANUP) || ++ (cap->cc_flags & match) == 0) ++ continue; ++ ++ /* verify all the algorithms are supported. */ ++ if (kdriver_suitable(cap, krp)) { ++ if (best == NULL || ++ cap->cc_koperations < best->cc_koperations) ++ best = cap; ++ } ++ } ++ if (best != NULL) ++ return best; ++ if (match == CRYPTOCAP_F_HARDWARE && (flags & CRYPTOCAP_F_SOFTWARE)) { ++ /* sort of an Algol 68-style for loop */ ++ match = CRYPTOCAP_F_SOFTWARE; ++ goto again; ++ } ++ return best; ++} ++ ++/* ++ * Dispatch an assymetric crypto request. ++ */ ++static int ++crypto_kinvoke(struct cryptkop *krp, int crid) ++{ ++ struct cryptocap *cap = NULL; ++ int error; ++ unsigned long d_flags; ++ ++ KASSERT(krp != NULL, ("%s: krp == NULL", __func__)); ++ KASSERT(krp->krp_callback != NULL, ++ ("%s: krp->crp_callback == NULL", __func__)); ++ ++ CRYPTO_DRIVER_LOCK(); ++ if ((crid & (CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE)) == 0) { ++ cap = crypto_checkdriver(crid); ++ if (cap != NULL) { ++ /* ++ * Driver present, it must support the necessary ++ * algorithm and, if s/w drivers are excluded, ++ * it must be registered as hardware-backed. ++ */ ++ if (!kdriver_suitable(cap, krp) || ++ (!crypto_devallowsoft && ++ (cap->cc_flags & CRYPTOCAP_F_HARDWARE) == 0)) ++ cap = NULL; ++ } ++ } else { ++ /* ++ * No requested driver; select based on crid flags. ++ */ ++ if (!crypto_devallowsoft) /* NB: disallow s/w drivers */ ++ crid &= ~CRYPTOCAP_F_SOFTWARE; ++ cap = crypto_select_kdriver(krp, crid); ++ } ++ if (cap != NULL && !cap->cc_kqblocked) { ++ krp->krp_hid = cap - crypto_drivers; ++ cap->cc_koperations++; ++ CRYPTO_DRIVER_UNLOCK(); ++ error = CRYPTODEV_KPROCESS(cap->cc_dev, krp, 0); ++ CRYPTO_DRIVER_LOCK(); ++ if (error == ERESTART) { ++ cap->cc_koperations--; ++ CRYPTO_DRIVER_UNLOCK(); ++ return (error); ++ } ++ /* return the actual device used */ ++ krp->krp_crid = krp->krp_hid; ++ } else { ++ /* ++ * NB: cap is !NULL if device is blocked; in ++ * that case return ERESTART so the operation ++ * is resubmitted if possible. ++ */ ++ error = (cap == NULL) ? ENODEV : ERESTART; ++ } ++ CRYPTO_DRIVER_UNLOCK(); ++ ++ if (error) { ++ krp->krp_status = error; ++ crypto_kdone(krp); ++ } ++ return 0; ++} ++ ++ ++/* ++ * Dispatch a crypto request to the appropriate crypto devices. ++ */ ++static int ++crypto_invoke(struct cryptocap *cap, struct cryptop *crp, int hint) ++{ ++ KASSERT(crp != NULL, ("%s: crp == NULL", __func__)); ++ KASSERT(crp->crp_callback != NULL, ++ ("%s: crp->crp_callback == NULL", __func__)); ++ KASSERT(crp->crp_desc != NULL, ("%s: crp->crp_desc == NULL", __func__)); ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++#ifdef CRYPTO_TIMING ++ if (crypto_timing) ++ crypto_tstat(&cryptostats.cs_invoke, &crp->crp_tstamp); ++#endif ++ if (cap->cc_flags & CRYPTOCAP_F_CLEANUP) { ++ struct cryptodesc *crd; ++ u_int64_t nid; ++ ++ /* ++ * Driver has unregistered; migrate the session and return ++ * an error to the caller so they'll resubmit the op. ++ * ++ * XXX: What if there are more already queued requests for this ++ * session? ++ */ ++ crypto_freesession(crp->crp_sid); ++ ++ for (crd = crp->crp_desc; crd->crd_next; crd = crd->crd_next) ++ crd->CRD_INI.cri_next = &(crd->crd_next->CRD_INI); ++ ++ /* XXX propagate flags from initial session? */ ++ if (crypto_newsession(&nid, &(crp->crp_desc->CRD_INI), ++ CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE) == 0) ++ crp->crp_sid = nid; ++ ++ crp->crp_etype = EAGAIN; ++ crypto_done(crp); ++ return 0; ++ } else { ++ /* ++ * Invoke the driver to process the request. ++ */ ++ return CRYPTODEV_PROCESS(cap->cc_dev, crp, hint); ++ } ++} ++ ++/* ++ * Release a set of crypto descriptors. ++ */ ++void ++crypto_freereq(struct cryptop *crp) ++{ ++ struct cryptodesc *crd; ++ ++ if (crp == NULL) ++ return; ++ ++#ifdef DIAGNOSTIC ++ { ++ struct cryptop *crp2; ++ unsigned long q_flags; ++ ++ CRYPTO_Q_LOCK(); ++ TAILQ_FOREACH(crp2, &crp_q, crp_next) { ++ KASSERT(crp2 != crp, ++ ("Freeing cryptop from the crypto queue (%p).", ++ crp)); ++ } ++ CRYPTO_Q_UNLOCK(); ++ CRYPTO_RETQ_LOCK(); ++ TAILQ_FOREACH(crp2, &crp_ret_q, crp_next) { ++ KASSERT(crp2 != crp, ++ ("Freeing cryptop from the return queue (%p).", ++ crp)); ++ } ++ CRYPTO_RETQ_UNLOCK(); ++ } ++#endif ++ ++ while ((crd = crp->crp_desc) != NULL) { ++ crp->crp_desc = crd->crd_next; ++ kmem_cache_free(cryptodesc_zone, crd); ++ } ++ kmem_cache_free(cryptop_zone, crp); ++} ++ ++/* ++ * Acquire a set of crypto descriptors. ++ */ ++struct cryptop * ++crypto_getreq(int num) ++{ ++ struct cryptodesc *crd; ++ struct cryptop *crp; ++ ++ crp = kmem_cache_alloc(cryptop_zone, SLAB_ATOMIC); ++ if (crp != NULL) { ++ memset(crp, 0, sizeof(*crp)); ++ INIT_LIST_HEAD(&crp->crp_next); ++ init_waitqueue_head(&crp->crp_waitq); ++ while (num--) { ++ crd = kmem_cache_alloc(cryptodesc_zone, SLAB_ATOMIC); ++ if (crd == NULL) { ++ crypto_freereq(crp); ++ return NULL; ++ } ++ memset(crd, 0, sizeof(*crd)); ++ crd->crd_next = crp->crp_desc; ++ crp->crp_desc = crd; ++ } ++ } ++ return crp; ++} ++ ++/* ++ * Invoke the callback on behalf of the driver. ++ */ ++void ++crypto_done(struct cryptop *crp) ++{ ++ unsigned long q_flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if ((crp->crp_flags & CRYPTO_F_DONE) == 0) { ++ crp->crp_flags |= CRYPTO_F_DONE; ++ CRYPTO_Q_LOCK(); ++ crypto_q_cnt--; ++ CRYPTO_Q_UNLOCK(); ++ } else ++ printk("crypto: crypto_done op already done, flags 0x%x", ++ crp->crp_flags); ++ if (crp->crp_etype != 0) ++ cryptostats.cs_errs++; ++ /* ++ * CBIMM means unconditionally do the callback immediately; ++ * CBIFSYNC means do the callback immediately only if the ++ * operation was done synchronously. Both are used to avoid ++ * doing extraneous context switches; the latter is mostly ++ * used with the software crypto driver. ++ */ ++ if ((crp->crp_flags & CRYPTO_F_CBIMM) || ++ ((crp->crp_flags & CRYPTO_F_CBIFSYNC) && ++ (CRYPTO_SESID2CAPS(crp->crp_sid) & CRYPTOCAP_F_SYNC))) { ++ /* ++ * Do the callback directly. This is ok when the ++ * callback routine does very little (e.g. the ++ * /dev/crypto callback method just does a wakeup). ++ */ ++ crp->crp_callback(crp); ++ } else { ++ unsigned long r_flags; ++ /* ++ * Normal case; queue the callback for the thread. ++ */ ++ CRYPTO_RETQ_LOCK(); ++ wake_up_interruptible(&cryptoretproc_wait);/* shared wait channel */ ++ TAILQ_INSERT_TAIL(&crp_ret_q, crp, crp_next); ++ CRYPTO_RETQ_UNLOCK(); ++ } ++} ++ ++/* ++ * Invoke the callback on behalf of the driver. ++ */ ++void ++crypto_kdone(struct cryptkop *krp) ++{ ++ struct cryptocap *cap; ++ unsigned long d_flags; ++ ++ if ((krp->krp_flags & CRYPTO_KF_DONE) != 0) ++ printk("crypto: crypto_kdone op already done, flags 0x%x", ++ krp->krp_flags); ++ krp->krp_flags |= CRYPTO_KF_DONE; ++ if (krp->krp_status != 0) ++ cryptostats.cs_kerrs++; ++ ++ CRYPTO_DRIVER_LOCK(); ++ /* XXX: What if driver is loaded in the meantime? */ ++ if (krp->krp_hid < crypto_drivers_num) { ++ cap = &crypto_drivers[krp->krp_hid]; ++ cap->cc_koperations--; ++ KASSERT(cap->cc_koperations >= 0, ("cc_koperations < 0")); ++ if (cap->cc_flags & CRYPTOCAP_F_CLEANUP) ++ crypto_remove(cap); ++ } ++ CRYPTO_DRIVER_UNLOCK(); ++ ++ /* ++ * CBIMM means unconditionally do the callback immediately; ++ * This is used to avoid doing extraneous context switches ++ */ ++ if ((krp->krp_flags & CRYPTO_KF_CBIMM)) { ++ /* ++ * Do the callback directly. This is ok when the ++ * callback routine does very little (e.g. the ++ * /dev/crypto callback method just does a wakeup). ++ */ ++ krp->krp_callback(krp); ++ } else { ++ unsigned long r_flags; ++ /* ++ * Normal case; queue the callback for the thread. ++ */ ++ CRYPTO_RETQ_LOCK(); ++ wake_up_interruptible(&cryptoretproc_wait);/* shared wait channel */ ++ TAILQ_INSERT_TAIL(&crp_ret_kq, krp, krp_next); ++ CRYPTO_RETQ_UNLOCK(); ++ } ++} ++ ++int ++crypto_getfeat(int *featp) ++{ ++ int hid, kalg, feat = 0; ++ unsigned long d_flags; ++ ++ CRYPTO_DRIVER_LOCK(); ++ for (hid = 0; hid < crypto_drivers_num; hid++) { ++ const struct cryptocap *cap = &crypto_drivers[hid]; ++ ++ if ((cap->cc_flags & CRYPTOCAP_F_SOFTWARE) && ++ !crypto_devallowsoft) { ++ continue; ++ } ++ for (kalg = 0; kalg < CRK_ALGORITHM_MAX; kalg++) ++ if (cap->cc_kalg[kalg] & CRYPTO_ALG_FLAG_SUPPORTED) ++ feat |= 1 << kalg; ++ } ++ CRYPTO_DRIVER_UNLOCK(); ++ *featp = feat; ++ return (0); ++} ++ ++/* ++ * Crypto thread, dispatches crypto requests. ++ */ ++static int ++crypto_proc(void *arg) ++{ ++ struct cryptop *crp, *submit; ++ struct cryptkop *krp, *krpp; ++ struct cryptocap *cap; ++ u_int32_t hid; ++ int result, hint; ++ unsigned long q_flags; ++ int loopcount = 0; ++ ++ set_current_state(TASK_INTERRUPTIBLE); ++ ++ CRYPTO_Q_LOCK(); ++ for (;;) { ++ /* ++ * we need to make sure we don't get into a busy loop with nothing ++ * to do, the two crypto_all_*blocked vars help us find out when ++ * we are all full and can do nothing on any driver or Q. If so we ++ * wait for an unblock. ++ */ ++ crypto_all_qblocked = !list_empty(&crp_q); ++ ++ /* ++ * Find the first element in the queue that can be ++ * processed and look-ahead to see if multiple ops ++ * are ready for the same driver. ++ */ ++ submit = NULL; ++ hint = 0; ++ list_for_each_entry(crp, &crp_q, crp_next) { ++ hid = CRYPTO_SESID2HID(crp->crp_sid); ++ cap = crypto_checkdriver(hid); ++ /* ++ * Driver cannot disappear when there is an active ++ * session. ++ */ ++ KASSERT(cap != NULL, ("%s:%u Driver disappeared.", ++ __func__, __LINE__)); ++ if (cap == NULL || cap->cc_dev == NULL) { ++ /* Op needs to be migrated, process it. */ ++ if (submit == NULL) ++ submit = crp; ++ break; ++ } ++ if (!cap->cc_qblocked) { ++ if (submit != NULL) { ++ /* ++ * We stop on finding another op, ++ * regardless whether its for the same ++ * driver or not. We could keep ++ * searching the queue but it might be ++ * better to just use a per-driver ++ * queue instead. ++ */ ++ if (CRYPTO_SESID2HID(submit->crp_sid) == hid) ++ hint = CRYPTO_HINT_MORE; ++ break; ++ } else { ++ submit = crp; ++ if ((submit->crp_flags & CRYPTO_F_BATCH) == 0) ++ break; ++ /* keep scanning for more are q'd */ ++ } ++ } ++ } ++ if (submit != NULL) { ++ hid = CRYPTO_SESID2HID(submit->crp_sid); ++ crypto_all_qblocked = 0; ++ list_del(&submit->crp_next); ++ crypto_drivers[hid].cc_unqblocked = 1; ++ cap = crypto_checkdriver(hid); ++ CRYPTO_Q_UNLOCK(); ++ KASSERT(cap != NULL, ("%s:%u Driver disappeared.", ++ __func__, __LINE__)); ++ result = crypto_invoke(cap, submit, hint); ++ CRYPTO_Q_LOCK(); ++ if (result == ERESTART) { ++ /* ++ * The driver ran out of resources, mark the ++ * driver ``blocked'' for cryptop's and put ++ * the request back in the queue. It would ++ * best to put the request back where we got ++ * it but that's hard so for now we put it ++ * at the front. This should be ok; putting ++ * it at the end does not work. ++ */ ++ /* XXX validate sid again? */ ++ list_add(&submit->crp_next, &crp_q); ++ cryptostats.cs_blocks++; ++ if (crypto_drivers[hid].cc_unqblocked) ++ crypto_drivers[hid].cc_qblocked=0; ++ crypto_drivers[hid].cc_unqblocked=0; ++ } ++ crypto_drivers[hid].cc_unqblocked = 0; ++ } ++ ++ crypto_all_kqblocked = !list_empty(&crp_kq); ++ ++ /* As above, but for key ops */ ++ krp = NULL; ++ list_for_each_entry(krpp, &crp_kq, krp_next) { ++ cap = crypto_checkdriver(krpp->krp_hid); ++ if (cap == NULL || cap->cc_dev == NULL) { ++ /* ++ * Operation needs to be migrated, invalidate ++ * the assigned device so it will reselect a ++ * new one below. Propagate the original ++ * crid selection flags if supplied. ++ */ ++ krp->krp_hid = krp->krp_crid & ++ (CRYPTOCAP_F_SOFTWARE|CRYPTOCAP_F_HARDWARE); ++ if (krp->krp_hid == 0) ++ krp->krp_hid = ++ CRYPTOCAP_F_SOFTWARE|CRYPTOCAP_F_HARDWARE; ++ break; ++ } ++ if (!cap->cc_kqblocked) { ++ krp = krpp; ++ break; ++ } ++ } ++ if (krp != NULL) { ++ crypto_all_kqblocked = 0; ++ list_del(&krp->krp_next); ++ crypto_drivers[krp->krp_hid].cc_kqblocked = 1; ++ CRYPTO_Q_UNLOCK(); ++ result = crypto_kinvoke(krp, krp->krp_hid); ++ CRYPTO_Q_LOCK(); ++ if (result == ERESTART) { ++ /* ++ * The driver ran out of resources, mark the ++ * driver ``blocked'' for cryptkop's and put ++ * the request back in the queue. It would ++ * best to put the request back where we got ++ * it but that's hard so for now we put it ++ * at the front. This should be ok; putting ++ * it at the end does not work. ++ */ ++ /* XXX validate sid again? */ ++ list_add(&krp->krp_next, &crp_kq); ++ cryptostats.cs_kblocks++; ++ } else ++ crypto_drivers[krp->krp_hid].cc_kqblocked = 0; ++ } ++ ++ if (submit == NULL && krp == NULL) { ++ /* ++ * Nothing more to be processed. Sleep until we're ++ * woken because there are more ops to process. ++ * This happens either by submission or by a driver ++ * becoming unblocked and notifying us through ++ * crypto_unblock. Note that when we wakeup we ++ * start processing each queue again from the ++ * front. It's not clear that it's important to ++ * preserve this ordering since ops may finish ++ * out of order if dispatched to different devices ++ * and some become blocked while others do not. ++ */ ++ dprintk("%s - sleeping (qe=%d qb=%d kqe=%d kqb=%d)\n", ++ __FUNCTION__, ++ list_empty(&crp_q), crypto_all_qblocked, ++ list_empty(&crp_kq), crypto_all_kqblocked); ++ loopcount = 0; ++ CRYPTO_Q_UNLOCK(); ++ wait_event_interruptible(cryptoproc_wait, ++ !(list_empty(&crp_q) || crypto_all_qblocked) || ++ !(list_empty(&crp_kq) || crypto_all_kqblocked) || ++ kthread_should_stop()); ++ if (signal_pending (current)) { ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++ spin_lock_irq(¤t->sigmask_lock); ++#endif ++ flush_signals(current); ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++ spin_unlock_irq(¤t->sigmask_lock); ++#endif ++ } ++ CRYPTO_Q_LOCK(); ++ dprintk("%s - awake\n", __FUNCTION__); ++ if (kthread_should_stop()) ++ break; ++ cryptostats.cs_intrs++; ++ } else if (loopcount > crypto_max_loopcount) { ++ /* ++ * Give other processes a chance to run if we've ++ * been using the CPU exclusively for a while. ++ */ ++ loopcount = 0; ++ CRYPTO_Q_UNLOCK(); ++ schedule(); ++ CRYPTO_Q_LOCK(); ++ } ++ loopcount++; ++ } ++ CRYPTO_Q_UNLOCK(); ++ return 0; ++} ++ ++/* ++ * Crypto returns thread, does callbacks for processed crypto requests. ++ * Callbacks are done here, rather than in the crypto drivers, because ++ * callbacks typically are expensive and would slow interrupt handling. ++ */ ++static int ++crypto_ret_proc(void *arg) ++{ ++ struct cryptop *crpt; ++ struct cryptkop *krpt; ++ unsigned long r_flags; ++ ++ set_current_state(TASK_INTERRUPTIBLE); ++ ++ CRYPTO_RETQ_LOCK(); ++ for (;;) { ++ /* Harvest return q's for completed ops */ ++ crpt = NULL; ++ if (!list_empty(&crp_ret_q)) ++ crpt = list_entry(crp_ret_q.next, typeof(*crpt), crp_next); ++ if (crpt != NULL) ++ list_del(&crpt->crp_next); ++ ++ krpt = NULL; ++ if (!list_empty(&crp_ret_kq)) ++ krpt = list_entry(crp_ret_kq.next, typeof(*krpt), krp_next); ++ if (krpt != NULL) ++ list_del(&krpt->krp_next); ++ ++ if (crpt != NULL || krpt != NULL) { ++ CRYPTO_RETQ_UNLOCK(); ++ /* ++ * Run callbacks unlocked. ++ */ ++ if (crpt != NULL) ++ crpt->crp_callback(crpt); ++ if (krpt != NULL) ++ krpt->krp_callback(krpt); ++ CRYPTO_RETQ_LOCK(); ++ } else { ++ /* ++ * Nothing more to be processed. Sleep until we're ++ * woken because there are more returns to process. ++ */ ++ dprintk("%s - sleeping\n", __FUNCTION__); ++ CRYPTO_RETQ_UNLOCK(); ++ wait_event_interruptible(cryptoretproc_wait, ++ !list_empty(&crp_ret_q) || ++ !list_empty(&crp_ret_kq) || ++ kthread_should_stop()); ++ if (signal_pending (current)) { ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++ spin_lock_irq(¤t->sigmask_lock); ++#endif ++ flush_signals(current); ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++ spin_unlock_irq(¤t->sigmask_lock); ++#endif ++ } ++ CRYPTO_RETQ_LOCK(); ++ dprintk("%s - awake\n", __FUNCTION__); ++ if (kthread_should_stop()) { ++ dprintk("%s - EXITING!\n", __FUNCTION__); ++ break; ++ } ++ cryptostats.cs_rets++; ++ } ++ } ++ CRYPTO_RETQ_UNLOCK(); ++ return 0; ++} ++ ++ ++#if 0 /* should put this into /proc or something */ ++static void ++db_show_drivers(void) ++{ ++ int hid; ++ ++ db_printf("%12s %4s %4s %8s %2s %2s\n" ++ , "Device" ++ , "Ses" ++ , "Kops" ++ , "Flags" ++ , "QB" ++ , "KB" ++ ); ++ for (hid = 0; hid < crypto_drivers_num; hid++) { ++ const struct cryptocap *cap = &crypto_drivers[hid]; ++ if (cap->cc_dev == NULL) ++ continue; ++ db_printf("%-12s %4u %4u %08x %2u %2u\n" ++ , device_get_nameunit(cap->cc_dev) ++ , cap->cc_sessions ++ , cap->cc_koperations ++ , cap->cc_flags ++ , cap->cc_qblocked ++ , cap->cc_kqblocked ++ ); ++ } ++} ++ ++DB_SHOW_COMMAND(crypto, db_show_crypto) ++{ ++ struct cryptop *crp; ++ ++ db_show_drivers(); ++ db_printf("\n"); ++ ++ db_printf("%4s %8s %4s %4s %4s %4s %8s %8s\n", ++ "HID", "Caps", "Ilen", "Olen", "Etype", "Flags", ++ "Desc", "Callback"); ++ TAILQ_FOREACH(crp, &crp_q, crp_next) { ++ db_printf("%4u %08x %4u %4u %4u %04x %8p %8p\n" ++ , (int) CRYPTO_SESID2HID(crp->crp_sid) ++ , (int) CRYPTO_SESID2CAPS(crp->crp_sid) ++ , crp->crp_ilen, crp->crp_olen ++ , crp->crp_etype ++ , crp->crp_flags ++ , crp->crp_desc ++ , crp->crp_callback ++ ); ++ } ++ if (!TAILQ_EMPTY(&crp_ret_q)) { ++ db_printf("\n%4s %4s %4s %8s\n", ++ "HID", "Etype", "Flags", "Callback"); ++ TAILQ_FOREACH(crp, &crp_ret_q, crp_next) { ++ db_printf("%4u %4u %04x %8p\n" ++ , (int) CRYPTO_SESID2HID(crp->crp_sid) ++ , crp->crp_etype ++ , crp->crp_flags ++ , crp->crp_callback ++ ); ++ } ++ } ++} ++ ++DB_SHOW_COMMAND(kcrypto, db_show_kcrypto) ++{ ++ struct cryptkop *krp; ++ ++ db_show_drivers(); ++ db_printf("\n"); ++ ++ db_printf("%4s %5s %4s %4s %8s %4s %8s\n", ++ "Op", "Status", "#IP", "#OP", "CRID", "HID", "Callback"); ++ TAILQ_FOREACH(krp, &crp_kq, krp_next) { ++ db_printf("%4u %5u %4u %4u %08x %4u %8p\n" ++ , krp->krp_op ++ , krp->krp_status ++ , krp->krp_iparams, krp->krp_oparams ++ , krp->krp_crid, krp->krp_hid ++ , krp->krp_callback ++ ); ++ } ++ if (!TAILQ_EMPTY(&crp_ret_q)) { ++ db_printf("%4s %5s %8s %4s %8s\n", ++ "Op", "Status", "CRID", "HID", "Callback"); ++ TAILQ_FOREACH(krp, &crp_ret_kq, krp_next) { ++ db_printf("%4u %5u %08x %4u %8p\n" ++ , krp->krp_op ++ , krp->krp_status ++ , krp->krp_crid, krp->krp_hid ++ , krp->krp_callback ++ ); ++ } ++ } ++} ++#endif ++ ++ ++static int ++crypto_init(void) ++{ ++ int error; ++ unsigned long cpu; ++ ++ dprintk("%s(%p)\n", __FUNCTION__, (void *) crypto_init); ++ ++ if (crypto_initted) ++ return 0; ++ crypto_initted = 1; ++ ++ spin_lock_init(&crypto_drivers_lock); ++ spin_lock_init(&crypto_q_lock); ++ spin_lock_init(&crypto_ret_q_lock); ++ ++ cryptop_zone = kmem_cache_create("cryptop", sizeof(struct cryptop), ++ 0, SLAB_HWCACHE_ALIGN, NULL ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) ++ , NULL ++#endif ++ ); ++ ++ cryptodesc_zone = kmem_cache_create("cryptodesc", sizeof(struct cryptodesc), ++ 0, SLAB_HWCACHE_ALIGN, NULL ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) ++ , NULL ++#endif ++ ); ++ ++ if (cryptodesc_zone == NULL || cryptop_zone == NULL) { ++ printk("crypto: crypto_init cannot setup crypto zones\n"); ++ error = ENOMEM; ++ goto bad; ++ } ++ ++ crypto_drivers_num = CRYPTO_DRIVERS_INITIAL; ++ crypto_drivers = kmalloc(crypto_drivers_num * sizeof(struct cryptocap), ++ GFP_KERNEL); ++ if (crypto_drivers == NULL) { ++ printk("crypto: crypto_init cannot setup crypto drivers\n"); ++ error = ENOMEM; ++ goto bad; ++ } ++ ++ memset(crypto_drivers, 0, crypto_drivers_num * sizeof(struct cryptocap)); ++ ++ ocf_for_each_cpu(cpu) { ++ cryptoproc[cpu] = kthread_create(crypto_proc, (void *) cpu, ++ "ocf_%d", (int) cpu); ++ if (IS_ERR(cryptoproc[cpu])) { ++ error = PTR_ERR(cryptoproc[cpu]); ++ printk("crypto: crypto_init cannot start crypto thread; error %d", ++ error); ++ goto bad; ++ } ++ kthread_bind(cryptoproc[cpu], cpu); ++ wake_up_process(cryptoproc[cpu]); ++ ++ cryptoretproc[cpu] = kthread_create(crypto_ret_proc, (void *) cpu, ++ "ocf_ret_%d", (int) cpu); ++ if (IS_ERR(cryptoretproc[cpu])) { ++ error = PTR_ERR(cryptoretproc[cpu]); ++ printk("crypto: crypto_init cannot start cryptoret thread; error %d", ++ error); ++ goto bad; ++ } ++ kthread_bind(cryptoretproc[cpu], cpu); ++ wake_up_process(cryptoretproc[cpu]); ++ } ++ ++ return 0; ++bad: ++ crypto_exit(); ++ return error; ++} ++ ++ ++static void ++crypto_exit(void) ++{ ++ int cpu; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ /* ++ * Terminate any crypto threads. ++ */ ++ ocf_for_each_cpu(cpu) { ++ kthread_stop(cryptoproc[cpu]); ++ kthread_stop(cryptoretproc[cpu]); ++ } ++ ++ /* ++ * Reclaim dynamically allocated resources. ++ */ ++ if (crypto_drivers != NULL) ++ kfree(crypto_drivers); ++ ++ if (cryptodesc_zone != NULL) ++ kmem_cache_destroy(cryptodesc_zone); ++ if (cryptop_zone != NULL) ++ kmem_cache_destroy(cryptop_zone); ++} ++ ++ ++EXPORT_SYMBOL(crypto_newsession); ++EXPORT_SYMBOL(crypto_freesession); ++EXPORT_SYMBOL(crypto_get_driverid); ++EXPORT_SYMBOL(crypto_kregister); ++EXPORT_SYMBOL(crypto_register); ++EXPORT_SYMBOL(crypto_unregister); ++EXPORT_SYMBOL(crypto_unregister_all); ++EXPORT_SYMBOL(crypto_unblock); ++EXPORT_SYMBOL(crypto_dispatch); ++EXPORT_SYMBOL(crypto_kdispatch); ++EXPORT_SYMBOL(crypto_freereq); ++EXPORT_SYMBOL(crypto_getreq); ++EXPORT_SYMBOL(crypto_done); ++EXPORT_SYMBOL(crypto_kdone); ++EXPORT_SYMBOL(crypto_getfeat); ++EXPORT_SYMBOL(crypto_userasymcrypto); ++EXPORT_SYMBOL(crypto_getcaps); ++EXPORT_SYMBOL(crypto_find_driver); ++EXPORT_SYMBOL(crypto_find_device_byhid); ++ ++module_init(crypto_init); ++module_exit(crypto_exit); ++ ++MODULE_LICENSE("BSD"); ++MODULE_AUTHOR("David McCullough "); ++MODULE_DESCRIPTION("OCF (OpenBSD Cryptographic Framework)"); +diff -Nur linux-3.1.4.orig/crypto/ocf/cryptocteon/Makefile linux-3.1.4/crypto/ocf/cryptocteon/Makefile +--- linux-3.1.4.orig/crypto/ocf/cryptocteon/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/cryptocteon/Makefile 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,17 @@ ++# for SGlinux builds ++-include $(ROOTDIR)/modules/.config ++ ++obj-$(CONFIG_OCF_CRYPTOCTEON) += cryptocteon.o ++ ++obj ?= . ++EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ ++ ++ifdef CONFIG_OCF_CRYPTOCTEON ++# you need the cavium crypto component installed ++EXTRA_CFLAGS += -I$(ROOTDIR)/prop/include ++endif ++ ++ifdef TOPDIR ++-include $(TOPDIR)/Rules.make ++endif ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/cryptocteon/README.txt linux-3.1.4/crypto/ocf/cryptocteon/README.txt +--- linux-3.1.4.orig/crypto/ocf/cryptocteon/README.txt 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/cryptocteon/README.txt 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,11 @@ ++ ++You will need the CRYPTO package installed to build this driver, and ++potentially the ADK. ++ ++cavium_crypto sourced from: ++ ++ adk/components/source/cavium_ipsec_kame/cavium_ipsec.c ++ ++and significantly modified to suit use with OCF. All original ++copyright/ownership headers retained. ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/cryptocteon/cavium_crypto.c linux-3.1.4/crypto/ocf/cryptocteon/cavium_crypto.c +--- linux-3.1.4.orig/crypto/ocf/cryptocteon/cavium_crypto.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/cryptocteon/cavium_crypto.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,2283 @@ ++/* ++ * Copyright (c) 2009 David McCullough ++ * ++ * Copyright (c) 2003-2007 Cavium Networks (support@cavium.com). All rights ++ * reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * 1. Redistributions of source code must retain the above copyright notice, ++ * this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright notice, ++ * this list of conditions and the following disclaimer in the documentation ++ * and/or other materials provided with the distribution. ++ * 3. All advertising materials mentioning features or use of this software ++ * must display the following acknowledgement: ++ * This product includes software developed by Cavium Networks ++ * 4. Cavium Networks' name may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * This Software, including technical data, may be subject to U.S. export ++ * control laws, including the U.S. Export Administration Act and its ++ * associated regulations, and may be subject to export or import regulations ++ * in other countries. You warrant that You will comply strictly in all ++ * respects with all such regulations and acknowledge that you have the ++ * responsibility to obtain licenses to export, re-export or import the ++ * Software. ++ * ++ * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" AND ++ * WITH ALL FAULTS AND CAVIUM MAKES NO PROMISES, REPRESENTATIONS OR WARRANTIES, ++ * EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO THE ++ * SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR ++ * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM ++ * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, ++ * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF ++ * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR ++ * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR ++ * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. ++*/ ++/****************************************************************************/ ++ ++#include ++#include ++#include "octeon-asm.h" ++ ++/****************************************************************************/ ++ ++extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *); ++extern void octeon_crypto_disable(struct octeon_cop2_state *, unsigned long); ++ ++#define SG_INIT(s, p, i, l) \ ++ { \ ++ (i) = 0; \ ++ (l) = (s)[0].length; \ ++ (p) = (typeof(p)) sg_virt((s)); \ ++ CVMX_PREFETCH0((p)); \ ++ } ++ ++#define SG_CONSUME(s, p, i, l) \ ++ { \ ++ (p)++; \ ++ (l) -= sizeof(*(p)); \ ++ if ((l) < 0) { \ ++ dprintk("%s, %d: l = %d\n", __FILE__, __LINE__, l); \ ++ } else if ((l) == 0) { \ ++ (i)++; \ ++ (l) = (s)[0].length; \ ++ (p) = (typeof(p)) sg_virt(s); \ ++ CVMX_PREFETCH0((p)); \ ++ } \ ++ } ++ ++#define ESP_HEADER_LENGTH 8 ++#define DES_CBC_IV_LENGTH 8 ++#define AES_CBC_IV_LENGTH 16 ++#define ESP_HMAC_LEN 12 ++ ++#define ESP_HEADER_LENGTH 8 ++#define DES_CBC_IV_LENGTH 8 ++ ++/****************************************************************************/ ++ ++#define CVM_LOAD_SHA_UNIT(dat, next) { \ ++ if (next == 0) { \ ++ next = 1; \ ++ CVMX_MT_HSH_DAT (dat, 0); \ ++ } else if (next == 1) { \ ++ next = 2; \ ++ CVMX_MT_HSH_DAT (dat, 1); \ ++ } else if (next == 2) { \ ++ next = 3; \ ++ CVMX_MT_HSH_DAT (dat, 2); \ ++ } else if (next == 3) { \ ++ next = 4; \ ++ CVMX_MT_HSH_DAT (dat, 3); \ ++ } else if (next == 4) { \ ++ next = 5; \ ++ CVMX_MT_HSH_DAT (dat, 4); \ ++ } else if (next == 5) { \ ++ next = 6; \ ++ CVMX_MT_HSH_DAT (dat, 5); \ ++ } else if (next == 6) { \ ++ next = 7; \ ++ CVMX_MT_HSH_DAT (dat, 6); \ ++ } else { \ ++ CVMX_MT_HSH_STARTSHA (dat); \ ++ next = 0; \ ++ } \ ++} ++ ++#define CVM_LOAD2_SHA_UNIT(dat1, dat2, next) { \ ++ if (next == 0) { \ ++ CVMX_MT_HSH_DAT (dat1, 0); \ ++ CVMX_MT_HSH_DAT (dat2, 1); \ ++ next = 2; \ ++ } else if (next == 1) { \ ++ CVMX_MT_HSH_DAT (dat1, 1); \ ++ CVMX_MT_HSH_DAT (dat2, 2); \ ++ next = 3; \ ++ } else if (next == 2) { \ ++ CVMX_MT_HSH_DAT (dat1, 2); \ ++ CVMX_MT_HSH_DAT (dat2, 3); \ ++ next = 4; \ ++ } else if (next == 3) { \ ++ CVMX_MT_HSH_DAT (dat1, 3); \ ++ CVMX_MT_HSH_DAT (dat2, 4); \ ++ next = 5; \ ++ } else if (next == 4) { \ ++ CVMX_MT_HSH_DAT (dat1, 4); \ ++ CVMX_MT_HSH_DAT (dat2, 5); \ ++ next = 6; \ ++ } else if (next == 5) { \ ++ CVMX_MT_HSH_DAT (dat1, 5); \ ++ CVMX_MT_HSH_DAT (dat2, 6); \ ++ next = 7; \ ++ } else if (next == 6) { \ ++ CVMX_MT_HSH_DAT (dat1, 6); \ ++ CVMX_MT_HSH_STARTSHA (dat2); \ ++ next = 0; \ ++ } else { \ ++ CVMX_MT_HSH_STARTSHA (dat1); \ ++ CVMX_MT_HSH_DAT (dat2, 0); \ ++ next = 1; \ ++ } \ ++} ++ ++/****************************************************************************/ ++ ++#define CVM_LOAD_MD5_UNIT(dat, next) { \ ++ if (next == 0) { \ ++ next = 1; \ ++ CVMX_MT_HSH_DAT (dat, 0); \ ++ } else if (next == 1) { \ ++ next = 2; \ ++ CVMX_MT_HSH_DAT (dat, 1); \ ++ } else if (next == 2) { \ ++ next = 3; \ ++ CVMX_MT_HSH_DAT (dat, 2); \ ++ } else if (next == 3) { \ ++ next = 4; \ ++ CVMX_MT_HSH_DAT (dat, 3); \ ++ } else if (next == 4) { \ ++ next = 5; \ ++ CVMX_MT_HSH_DAT (dat, 4); \ ++ } else if (next == 5) { \ ++ next = 6; \ ++ CVMX_MT_HSH_DAT (dat, 5); \ ++ } else if (next == 6) { \ ++ next = 7; \ ++ CVMX_MT_HSH_DAT (dat, 6); \ ++ } else { \ ++ CVMX_MT_HSH_STARTMD5 (dat); \ ++ next = 0; \ ++ } \ ++} ++ ++#define CVM_LOAD2_MD5_UNIT(dat1, dat2, next) { \ ++ if (next == 0) { \ ++ CVMX_MT_HSH_DAT (dat1, 0); \ ++ CVMX_MT_HSH_DAT (dat2, 1); \ ++ next = 2; \ ++ } else if (next == 1) { \ ++ CVMX_MT_HSH_DAT (dat1, 1); \ ++ CVMX_MT_HSH_DAT (dat2, 2); \ ++ next = 3; \ ++ } else if (next == 2) { \ ++ CVMX_MT_HSH_DAT (dat1, 2); \ ++ CVMX_MT_HSH_DAT (dat2, 3); \ ++ next = 4; \ ++ } else if (next == 3) { \ ++ CVMX_MT_HSH_DAT (dat1, 3); \ ++ CVMX_MT_HSH_DAT (dat2, 4); \ ++ next = 5; \ ++ } else if (next == 4) { \ ++ CVMX_MT_HSH_DAT (dat1, 4); \ ++ CVMX_MT_HSH_DAT (dat2, 5); \ ++ next = 6; \ ++ } else if (next == 5) { \ ++ CVMX_MT_HSH_DAT (dat1, 5); \ ++ CVMX_MT_HSH_DAT (dat2, 6); \ ++ next = 7; \ ++ } else if (next == 6) { \ ++ CVMX_MT_HSH_DAT (dat1, 6); \ ++ CVMX_MT_HSH_STARTMD5 (dat2); \ ++ next = 0; \ ++ } else { \ ++ CVMX_MT_HSH_STARTMD5 (dat1); \ ++ CVMX_MT_HSH_DAT (dat2, 0); \ ++ next = 1; \ ++ } \ ++} ++ ++/****************************************************************************/ ++ ++static inline uint64_t ++swap64(uint64_t a) ++{ ++ return ((a >> 56) | ++ (((a >> 48) & 0xfful) << 8) | ++ (((a >> 40) & 0xfful) << 16) | ++ (((a >> 32) & 0xfful) << 24) | ++ (((a >> 24) & 0xfful) << 32) | ++ (((a >> 16) & 0xfful) << 40) | ++ (((a >> 8) & 0xfful) << 48) | (((a >> 0) & 0xfful) << 56)); ++} ++ ++/****************************************************************************/ ++ ++void ++octo_calc_hash(__u8 auth, unsigned char *key, uint64_t *inner, uint64_t *outer) ++{ ++ uint8_t hash_key[64]; ++ uint64_t *key1; ++ register uint64_t xor1 = 0x3636363636363636ULL; ++ register uint64_t xor2 = 0x5c5c5c5c5c5c5c5cULL; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ memset(hash_key, 0, sizeof(hash_key)); ++ memcpy(hash_key, (uint8_t *) key, (auth ? 20 : 16)); ++ key1 = (uint64_t *) hash_key; ++ flags = octeon_crypto_enable(&state); ++ if (auth) { ++ CVMX_MT_HSH_IV(0x67452301EFCDAB89ULL, 0); ++ CVMX_MT_HSH_IV(0x98BADCFE10325476ULL, 1); ++ CVMX_MT_HSH_IV(0xC3D2E1F000000000ULL, 2); ++ } else { ++ CVMX_MT_HSH_IV(0x0123456789ABCDEFULL, 0); ++ CVMX_MT_HSH_IV(0xFEDCBA9876543210ULL, 1); ++ } ++ ++ CVMX_MT_HSH_DAT((*key1 ^ xor1), 0); ++ key1++; ++ CVMX_MT_HSH_DAT((*key1 ^ xor1), 1); ++ key1++; ++ CVMX_MT_HSH_DAT((*key1 ^ xor1), 2); ++ key1++; ++ CVMX_MT_HSH_DAT((*key1 ^ xor1), 3); ++ key1++; ++ CVMX_MT_HSH_DAT((*key1 ^ xor1), 4); ++ key1++; ++ CVMX_MT_HSH_DAT((*key1 ^ xor1), 5); ++ key1++; ++ CVMX_MT_HSH_DAT((*key1 ^ xor1), 6); ++ key1++; ++ if (auth) ++ CVMX_MT_HSH_STARTSHA((*key1 ^ xor1)); ++ else ++ CVMX_MT_HSH_STARTMD5((*key1 ^ xor1)); ++ ++ CVMX_MF_HSH_IV(inner[0], 0); ++ CVMX_MF_HSH_IV(inner[1], 1); ++ if (auth) { ++ inner[2] = 0; ++ CVMX_MF_HSH_IV(((uint64_t *) inner)[2], 2); ++ } ++ ++ memset(hash_key, 0, sizeof(hash_key)); ++ memcpy(hash_key, (uint8_t *) key, (auth ? 20 : 16)); ++ key1 = (uint64_t *) hash_key; ++ if (auth) { ++ CVMX_MT_HSH_IV(0x67452301EFCDAB89ULL, 0); ++ CVMX_MT_HSH_IV(0x98BADCFE10325476ULL, 1); ++ CVMX_MT_HSH_IV(0xC3D2E1F000000000ULL, 2); ++ } else { ++ CVMX_MT_HSH_IV(0x0123456789ABCDEFULL, 0); ++ CVMX_MT_HSH_IV(0xFEDCBA9876543210ULL, 1); ++ } ++ ++ CVMX_MT_HSH_DAT((*key1 ^ xor2), 0); ++ key1++; ++ CVMX_MT_HSH_DAT((*key1 ^ xor2), 1); ++ key1++; ++ CVMX_MT_HSH_DAT((*key1 ^ xor2), 2); ++ key1++; ++ CVMX_MT_HSH_DAT((*key1 ^ xor2), 3); ++ key1++; ++ CVMX_MT_HSH_DAT((*key1 ^ xor2), 4); ++ key1++; ++ CVMX_MT_HSH_DAT((*key1 ^ xor2), 5); ++ key1++; ++ CVMX_MT_HSH_DAT((*key1 ^ xor2), 6); ++ key1++; ++ if (auth) ++ CVMX_MT_HSH_STARTSHA((*key1 ^ xor2)); ++ else ++ CVMX_MT_HSH_STARTMD5((*key1 ^ xor2)); ++ ++ CVMX_MF_HSH_IV(outer[0], 0); ++ CVMX_MF_HSH_IV(outer[1], 1); ++ if (auth) { ++ outer[2] = 0; ++ CVMX_MF_HSH_IV(outer[2], 2); ++ } ++ octeon_crypto_disable(&state, flags); ++ return; ++} ++ ++/****************************************************************************/ ++/* DES functions */ ++ ++int ++octo_des_cbc_encrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ uint64_t *data; ++ int data_i, data_l; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || ++ (crypt_off & 0x7) || (crypt_off + crypt_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data, data_i, data_l); ++ ++ CVMX_PREFETCH0(ivp); ++ CVMX_PREFETCH0(od->octo_enckey); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* load 3DES Key */ ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); ++ if (od->octo_encklen == 24) { ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ } else if (od->octo_encklen == 8) { ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); ++ } else { ++ octeon_crypto_disable(&state, flags); ++ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); ++ return -EINVAL; ++ } ++ ++ CVMX_MT_3DES_IV(* (uint64_t *) ivp); ++ ++ while (crypt_off > 0) { ++ SG_CONSUME(sg, data, data_i, data_l); ++ crypt_off -= 8; ++ } ++ ++ while (crypt_len > 0) { ++ CVMX_MT_3DES_ENC_CBC(*data); ++ CVMX_MF_3DES_RESULT(*data); ++ SG_CONSUME(sg, data, data_i, data_l); ++ crypt_len -= 8; ++ } ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++ ++int ++octo_des_cbc_decrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ uint64_t *data; ++ int data_i, data_l; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || ++ (crypt_off & 0x7) || (crypt_off + crypt_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data, data_i, data_l); ++ ++ CVMX_PREFETCH0(ivp); ++ CVMX_PREFETCH0(od->octo_enckey); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* load 3DES Key */ ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); ++ if (od->octo_encklen == 24) { ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ } else if (od->octo_encklen == 8) { ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); ++ } else { ++ octeon_crypto_disable(&state, flags); ++ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); ++ return -EINVAL; ++ } ++ ++ CVMX_MT_3DES_IV(* (uint64_t *) ivp); ++ ++ while (crypt_off > 0) { ++ SG_CONSUME(sg, data, data_i, data_l); ++ crypt_off -= 8; ++ } ++ ++ while (crypt_len > 0) { ++ CVMX_MT_3DES_DEC_CBC(*data); ++ CVMX_MF_3DES_RESULT(*data); ++ SG_CONSUME(sg, data, data_i, data_l); ++ crypt_len -= 8; ++ } ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++/****************************************************************************/ ++/* AES functions */ ++ ++int ++octo_aes_cbc_encrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ uint64_t *data, *pdata; ++ int data_i, data_l; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || ++ (crypt_off & 0x7) || (crypt_off + crypt_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data, data_i, data_l); ++ ++ CVMX_PREFETCH0(ivp); ++ CVMX_PREFETCH0(od->octo_enckey); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* load AES Key */ ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); ++ ++ if (od->octo_encklen == 16) { ++ CVMX_MT_AES_KEY(0x0, 2); ++ CVMX_MT_AES_KEY(0x0, 3); ++ } else if (od->octo_encklen == 24) { ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ CVMX_MT_AES_KEY(0x0, 3); ++ } else if (od->octo_encklen == 32) { ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); ++ } else { ++ octeon_crypto_disable(&state, flags); ++ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); ++ return -EINVAL; ++ } ++ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); ++ ++ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); ++ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); ++ ++ while (crypt_off > 0) { ++ SG_CONSUME(sg, data, data_i, data_l); ++ crypt_off -= 8; ++ } ++ ++ while (crypt_len > 0) { ++ pdata = data; ++ CVMX_MT_AES_ENC_CBC0(*data); ++ SG_CONSUME(sg, data, data_i, data_l); ++ CVMX_MT_AES_ENC_CBC1(*data); ++ CVMX_MF_AES_RESULT(*pdata, 0); ++ CVMX_MF_AES_RESULT(*data, 1); ++ SG_CONSUME(sg, data, data_i, data_l); ++ crypt_len -= 16; ++ } ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++ ++int ++octo_aes_cbc_decrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ uint64_t *data, *pdata; ++ int data_i, data_l; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || ++ (crypt_off & 0x7) || (crypt_off + crypt_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data, data_i, data_l); ++ ++ CVMX_PREFETCH0(ivp); ++ CVMX_PREFETCH0(od->octo_enckey); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* load AES Key */ ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); ++ ++ if (od->octo_encklen == 16) { ++ CVMX_MT_AES_KEY(0x0, 2); ++ CVMX_MT_AES_KEY(0x0, 3); ++ } else if (od->octo_encklen == 24) { ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ CVMX_MT_AES_KEY(0x0, 3); ++ } else if (od->octo_encklen == 32) { ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); ++ } else { ++ octeon_crypto_disable(&state, flags); ++ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); ++ return -EINVAL; ++ } ++ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); ++ ++ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); ++ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); ++ ++ while (crypt_off > 0) { ++ SG_CONSUME(sg, data, data_i, data_l); ++ crypt_off -= 8; ++ } ++ ++ while (crypt_len > 0) { ++ pdata = data; ++ CVMX_MT_AES_DEC_CBC0(*data); ++ SG_CONSUME(sg, data, data_i, data_l); ++ CVMX_MT_AES_DEC_CBC1(*data); ++ CVMX_MF_AES_RESULT(*pdata, 0); ++ CVMX_MF_AES_RESULT(*data, 1); ++ SG_CONSUME(sg, data, data_i, data_l); ++ crypt_len -= 16; ++ } ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++/****************************************************************************/ ++/* MD5 */ ++ ++int ++octo_null_md5_encrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ register int next = 0; ++ uint64_t *data; ++ uint64_t tmp1, tmp2; ++ int data_i, data_l, alen = auth_len; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ++ (auth_off & 0x7) || (auth_off + auth_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data, data_i, data_l); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* Load MD5 IV */ ++ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); ++ ++ while (auth_off > 0) { ++ SG_CONSUME(sg, data, data_i, data_l); ++ auth_off -= 8; ++ } ++ ++ while (auth_len > 0) { ++ CVM_LOAD_MD5_UNIT(*data, next); ++ auth_len -= 8; ++ SG_CONSUME(sg, data, data_i, data_l); ++ } ++ ++ /* finish the hash */ ++ CVMX_PREFETCH0(od->octo_hmouter); ++#if 0 ++ if (unlikely(inplen)) { ++ uint64_t tmp = 0; ++ uint8_t *p = (uint8_t *) & tmp; ++ p[inplen] = 0x80; ++ do { ++ inplen--; ++ p[inplen] = ((uint8_t *) data)[inplen]; ++ } while (inplen); ++ CVM_LOAD_MD5_UNIT(tmp, next); ++ } else { ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++ } ++#else ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++#endif ++ ++ /* Finish Inner hash */ ++ while (next != 7) { ++ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); ++ } ++ CVMX_ES64(tmp1, ((alen + 64) << 3)); ++ CVM_LOAD_MD5_UNIT(tmp1, next); ++ ++ /* Get the inner hash of HMAC */ ++ CVMX_MF_HSH_IV(tmp1, 0); ++ CVMX_MF_HSH_IV(tmp2, 1); ++ ++ /* Initialize hash unit */ ++ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); ++ ++ CVMX_MT_HSH_DAT(tmp1, 0); ++ CVMX_MT_HSH_DAT(tmp2, 1); ++ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); ++ CVMX_MT_HSH_DATZ(3); ++ CVMX_MT_HSH_DATZ(4); ++ CVMX_MT_HSH_DATZ(5); ++ CVMX_MT_HSH_DATZ(6); ++ CVMX_ES64(tmp1, ((64 + 16) << 3)); ++ CVMX_MT_HSH_STARTMD5(tmp1); ++ ++ /* save the HMAC */ ++ SG_INIT(sg, data, data_i, data_l); ++ while (icv_off > 0) { ++ SG_CONSUME(sg, data, data_i, data_l); ++ icv_off -= 8; ++ } ++ CVMX_MF_HSH_IV(*data, 0); ++ SG_CONSUME(sg, data, data_i, data_l); ++ CVMX_MF_HSH_IV(tmp1, 1); ++ *(uint32_t *)data = (uint32_t) (tmp1 >> 32); ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++/****************************************************************************/ ++/* SHA1 */ ++ ++int ++octo_null_sha1_encrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ register int next = 0; ++ uint64_t *data; ++ uint64_t tmp1, tmp2, tmp3; ++ int data_i, data_l, alen = auth_len; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ++ (auth_off & 0x7) || (auth_off + auth_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data, data_i, data_l); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* Load SHA1 IV */ ++ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); ++ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); ++ ++ while (auth_off > 0) { ++ SG_CONSUME(sg, data, data_i, data_l); ++ auth_off -= 8; ++ } ++ ++ while (auth_len > 0) { ++ CVM_LOAD_SHA_UNIT(*data, next); ++ auth_len -= 8; ++ SG_CONSUME(sg, data, data_i, data_l); ++ } ++ ++ /* finish the hash */ ++ CVMX_PREFETCH0(od->octo_hmouter); ++#if 0 ++ if (unlikely(inplen)) { ++ uint64_t tmp = 0; ++ uint8_t *p = (uint8_t *) & tmp; ++ p[inplen] = 0x80; ++ do { ++ inplen--; ++ p[inplen] = ((uint8_t *) data)[inplen]; ++ } while (inplen); ++ CVM_LOAD_MD5_UNIT(tmp, next); ++ } else { ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++ } ++#else ++ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); ++#endif ++ ++ /* Finish Inner hash */ ++ while (next != 7) { ++ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); ++ } ++ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); ++ ++ /* Get the inner hash of HMAC */ ++ CVMX_MF_HSH_IV(tmp1, 0); ++ CVMX_MF_HSH_IV(tmp2, 1); ++ tmp3 = 0; ++ CVMX_MF_HSH_IV(tmp3, 2); ++ ++ /* Initialize hash unit */ ++ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); ++ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); ++ ++ CVMX_MT_HSH_DAT(tmp1, 0); ++ CVMX_MT_HSH_DAT(tmp2, 1); ++ tmp3 |= 0x0000000080000000; ++ CVMX_MT_HSH_DAT(tmp3, 2); ++ CVMX_MT_HSH_DATZ(3); ++ CVMX_MT_HSH_DATZ(4); ++ CVMX_MT_HSH_DATZ(5); ++ CVMX_MT_HSH_DATZ(6); ++ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); ++ ++ /* save the HMAC */ ++ SG_INIT(sg, data, data_i, data_l); ++ while (icv_off > 0) { ++ SG_CONSUME(sg, data, data_i, data_l); ++ icv_off -= 8; ++ } ++ CVMX_MF_HSH_IV(*data, 0); ++ SG_CONSUME(sg, data, data_i, data_l); ++ CVMX_MF_HSH_IV(tmp1, 1); ++ *(uint32_t *)data = (uint32_t) (tmp1 >> 32); ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++/****************************************************************************/ ++/* DES MD5 */ ++ ++int ++octo_des_cbc_md5_encrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ register int next = 0; ++ union { ++ uint32_t data32[2]; ++ uint64_t data64[1]; ++ } mydata; ++ uint64_t *data = &mydata.data64[0]; ++ uint32_t *data32; ++ uint64_t tmp1, tmp2; ++ int data_i, data_l, alen = auth_len; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || ++ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || ++ (crypt_len & 0x7) || ++ (auth_len & 0x7) || ++ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data32, data_i, data_l); ++ ++ CVMX_PREFETCH0(ivp); ++ CVMX_PREFETCH0(od->octo_enckey); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* load 3DES Key */ ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); ++ if (od->octo_encklen == 24) { ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ } else if (od->octo_encklen == 8) { ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); ++ } else { ++ octeon_crypto_disable(&state, flags); ++ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); ++ return -EINVAL; ++ } ++ ++ CVMX_MT_3DES_IV(* (uint64_t *) ivp); ++ ++ /* Load MD5 IV */ ++ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); ++ ++ while (crypt_off > 0 && auth_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ crypt_off -= 4; ++ auth_off -= 4; ++ } ++ ++ while (crypt_len > 0 || auth_len > 0) { ++ uint32_t *first = data32; ++ mydata.data32[0] = *first; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata.data32[1] = *data32; ++ if (crypt_off <= 0) { ++ if (crypt_len > 0) { ++ CVMX_MT_3DES_ENC_CBC(*data); ++ CVMX_MF_3DES_RESULT(*data); ++ crypt_len -= 8; ++ } ++ } else ++ crypt_off -= 8; ++ if (auth_off <= 0) { ++ if (auth_len > 0) { ++ CVM_LOAD_MD5_UNIT(*data, next); ++ auth_len -= 8; ++ } ++ } else ++ auth_off -= 8; ++ *first = mydata.data32[0]; ++ *data32 = mydata.data32[1]; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ } ++ ++ /* finish the hash */ ++ CVMX_PREFETCH0(od->octo_hmouter); ++#if 0 ++ if (unlikely(inplen)) { ++ uint64_t tmp = 0; ++ uint8_t *p = (uint8_t *) & tmp; ++ p[inplen] = 0x80; ++ do { ++ inplen--; ++ p[inplen] = ((uint8_t *) data)[inplen]; ++ } while (inplen); ++ CVM_LOAD_MD5_UNIT(tmp, next); ++ } else { ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++ } ++#else ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++#endif ++ ++ /* Finish Inner hash */ ++ while (next != 7) { ++ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); ++ } ++ CVMX_ES64(tmp1, ((alen + 64) << 3)); ++ CVM_LOAD_MD5_UNIT(tmp1, next); ++ ++ /* Get the inner hash of HMAC */ ++ CVMX_MF_HSH_IV(tmp1, 0); ++ CVMX_MF_HSH_IV(tmp2, 1); ++ ++ /* Initialize hash unit */ ++ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); ++ ++ CVMX_MT_HSH_DAT(tmp1, 0); ++ CVMX_MT_HSH_DAT(tmp2, 1); ++ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); ++ CVMX_MT_HSH_DATZ(3); ++ CVMX_MT_HSH_DATZ(4); ++ CVMX_MT_HSH_DATZ(5); ++ CVMX_MT_HSH_DATZ(6); ++ CVMX_ES64(tmp1, ((64 + 16) << 3)); ++ CVMX_MT_HSH_STARTMD5(tmp1); ++ ++ /* save the HMAC */ ++ SG_INIT(sg, data32, data_i, data_l); ++ while (icv_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ icv_off -= 4; ++ } ++ CVMX_MF_HSH_IV(tmp1, 0); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ SG_CONSUME(sg, data32, data_i, data_l); ++ *data32 = (uint32_t) tmp1; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVMX_MF_HSH_IV(tmp1, 1); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++int ++octo_des_cbc_md5_decrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ register int next = 0; ++ union { ++ uint32_t data32[2]; ++ uint64_t data64[1]; ++ } mydata; ++ uint64_t *data = &mydata.data64[0]; ++ uint32_t *data32; ++ uint64_t tmp1, tmp2; ++ int data_i, data_l, alen = auth_len; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || ++ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || ++ (crypt_len & 0x7) || ++ (auth_len & 0x7) || ++ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data32, data_i, data_l); ++ ++ CVMX_PREFETCH0(ivp); ++ CVMX_PREFETCH0(od->octo_enckey); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* load 3DES Key */ ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); ++ if (od->octo_encklen == 24) { ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ } else if (od->octo_encklen == 8) { ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); ++ } else { ++ octeon_crypto_disable(&state, flags); ++ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); ++ return -EINVAL; ++ } ++ ++ CVMX_MT_3DES_IV(* (uint64_t *) ivp); ++ ++ /* Load MD5 IV */ ++ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); ++ ++ while (crypt_off > 0 && auth_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ crypt_off -= 4; ++ auth_off -= 4; ++ } ++ ++ while (crypt_len > 0 || auth_len > 0) { ++ uint32_t *first = data32; ++ mydata.data32[0] = *first; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata.data32[1] = *data32; ++ if (auth_off <= 0) { ++ if (auth_len > 0) { ++ CVM_LOAD_MD5_UNIT(*data, next); ++ auth_len -= 8; ++ } ++ } else ++ auth_off -= 8; ++ if (crypt_off <= 0) { ++ if (crypt_len > 0) { ++ CVMX_MT_3DES_DEC_CBC(*data); ++ CVMX_MF_3DES_RESULT(*data); ++ crypt_len -= 8; ++ } ++ } else ++ crypt_off -= 8; ++ *first = mydata.data32[0]; ++ *data32 = mydata.data32[1]; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ } ++ ++ /* finish the hash */ ++ CVMX_PREFETCH0(od->octo_hmouter); ++#if 0 ++ if (unlikely(inplen)) { ++ uint64_t tmp = 0; ++ uint8_t *p = (uint8_t *) & tmp; ++ p[inplen] = 0x80; ++ do { ++ inplen--; ++ p[inplen] = ((uint8_t *) data)[inplen]; ++ } while (inplen); ++ CVM_LOAD_MD5_UNIT(tmp, next); ++ } else { ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++ } ++#else ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++#endif ++ ++ /* Finish Inner hash */ ++ while (next != 7) { ++ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); ++ } ++ CVMX_ES64(tmp1, ((alen + 64) << 3)); ++ CVM_LOAD_MD5_UNIT(tmp1, next); ++ ++ /* Get the inner hash of HMAC */ ++ CVMX_MF_HSH_IV(tmp1, 0); ++ CVMX_MF_HSH_IV(tmp2, 1); ++ ++ /* Initialize hash unit */ ++ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); ++ ++ CVMX_MT_HSH_DAT(tmp1, 0); ++ CVMX_MT_HSH_DAT(tmp2, 1); ++ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); ++ CVMX_MT_HSH_DATZ(3); ++ CVMX_MT_HSH_DATZ(4); ++ CVMX_MT_HSH_DATZ(5); ++ CVMX_MT_HSH_DATZ(6); ++ CVMX_ES64(tmp1, ((64 + 16) << 3)); ++ CVMX_MT_HSH_STARTMD5(tmp1); ++ ++ /* save the HMAC */ ++ SG_INIT(sg, data32, data_i, data_l); ++ while (icv_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ icv_off -= 4; ++ } ++ CVMX_MF_HSH_IV(tmp1, 0); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ SG_CONSUME(sg, data32, data_i, data_l); ++ *data32 = (uint32_t) tmp1; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVMX_MF_HSH_IV(tmp1, 1); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++/****************************************************************************/ ++/* DES SHA */ ++ ++int ++octo_des_cbc_sha1_encrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ register int next = 0; ++ union { ++ uint32_t data32[2]; ++ uint64_t data64[1]; ++ } mydata; ++ uint64_t *data = &mydata.data64[0]; ++ uint32_t *data32; ++ uint64_t tmp1, tmp2, tmp3; ++ int data_i, data_l, alen = auth_len; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || ++ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || ++ (crypt_len & 0x7) || ++ (auth_len & 0x7) || ++ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data32, data_i, data_l); ++ ++ CVMX_PREFETCH0(ivp); ++ CVMX_PREFETCH0(od->octo_enckey); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* load 3DES Key */ ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); ++ if (od->octo_encklen == 24) { ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ } else if (od->octo_encklen == 8) { ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); ++ } else { ++ octeon_crypto_disable(&state, flags); ++ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); ++ return -EINVAL; ++ } ++ ++ CVMX_MT_3DES_IV(* (uint64_t *) ivp); ++ ++ /* Load SHA1 IV */ ++ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); ++ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); ++ ++ while (crypt_off > 0 && auth_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ crypt_off -= 4; ++ auth_off -= 4; ++ } ++ ++ while (crypt_len > 0 || auth_len > 0) { ++ uint32_t *first = data32; ++ mydata.data32[0] = *first; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata.data32[1] = *data32; ++ if (crypt_off <= 0) { ++ if (crypt_len > 0) { ++ CVMX_MT_3DES_ENC_CBC(*data); ++ CVMX_MF_3DES_RESULT(*data); ++ crypt_len -= 8; ++ } ++ } else ++ crypt_off -= 8; ++ if (auth_off <= 0) { ++ if (auth_len > 0) { ++ CVM_LOAD_SHA_UNIT(*data, next); ++ auth_len -= 8; ++ } ++ } else ++ auth_off -= 8; ++ *first = mydata.data32[0]; ++ *data32 = mydata.data32[1]; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ } ++ ++ /* finish the hash */ ++ CVMX_PREFETCH0(od->octo_hmouter); ++#if 0 ++ if (unlikely(inplen)) { ++ uint64_t tmp = 0; ++ uint8_t *p = (uint8_t *) & tmp; ++ p[inplen] = 0x80; ++ do { ++ inplen--; ++ p[inplen] = ((uint8_t *) data)[inplen]; ++ } while (inplen); ++ CVM_LOAD_SHA_UNIT(tmp, next); ++ } else { ++ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); ++ } ++#else ++ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); ++#endif ++ ++ /* Finish Inner hash */ ++ while (next != 7) { ++ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); ++ } ++ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); ++ ++ /* Get the inner hash of HMAC */ ++ CVMX_MF_HSH_IV(tmp1, 0); ++ CVMX_MF_HSH_IV(tmp2, 1); ++ tmp3 = 0; ++ CVMX_MF_HSH_IV(tmp3, 2); ++ ++ /* Initialize hash unit */ ++ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); ++ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); ++ ++ CVMX_MT_HSH_DAT(tmp1, 0); ++ CVMX_MT_HSH_DAT(tmp2, 1); ++ tmp3 |= 0x0000000080000000; ++ CVMX_MT_HSH_DAT(tmp3, 2); ++ CVMX_MT_HSH_DATZ(3); ++ CVMX_MT_HSH_DATZ(4); ++ CVMX_MT_HSH_DATZ(5); ++ CVMX_MT_HSH_DATZ(6); ++ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); ++ ++ /* save the HMAC */ ++ SG_INIT(sg, data32, data_i, data_l); ++ while (icv_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ icv_off -= 4; ++ } ++ CVMX_MF_HSH_IV(tmp1, 0); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ SG_CONSUME(sg, data32, data_i, data_l); ++ *data32 = (uint32_t) tmp1; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVMX_MF_HSH_IV(tmp1, 1); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++int ++octo_des_cbc_sha1_decrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ register int next = 0; ++ union { ++ uint32_t data32[2]; ++ uint64_t data64[1]; ++ } mydata; ++ uint64_t *data = &mydata.data64[0]; ++ uint32_t *data32; ++ uint64_t tmp1, tmp2, tmp3; ++ int data_i, data_l, alen = auth_len; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || ++ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || ++ (crypt_len & 0x7) || ++ (auth_len & 0x7) || ++ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data32, data_i, data_l); ++ ++ CVMX_PREFETCH0(ivp); ++ CVMX_PREFETCH0(od->octo_enckey); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* load 3DES Key */ ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 0); ++ if (od->octo_encklen == 24) { ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[1], 1); ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ } else if (od->octo_encklen == 8) { ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 1); ++ CVMX_MT_3DES_KEY(((uint64_t *) od->octo_enckey)[0], 2); ++ } else { ++ octeon_crypto_disable(&state, flags); ++ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); ++ return -EINVAL; ++ } ++ ++ CVMX_MT_3DES_IV(* (uint64_t *) ivp); ++ ++ /* Load SHA1 IV */ ++ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); ++ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); ++ ++ while (crypt_off > 0 && auth_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ crypt_off -= 4; ++ auth_off -= 4; ++ } ++ ++ while (crypt_len > 0 || auth_len > 0) { ++ uint32_t *first = data32; ++ mydata.data32[0] = *first; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata.data32[1] = *data32; ++ if (auth_off <= 0) { ++ if (auth_len > 0) { ++ CVM_LOAD_SHA_UNIT(*data, next); ++ auth_len -= 8; ++ } ++ } else ++ auth_off -= 8; ++ if (crypt_off <= 0) { ++ if (crypt_len > 0) { ++ CVMX_MT_3DES_DEC_CBC(*data); ++ CVMX_MF_3DES_RESULT(*data); ++ crypt_len -= 8; ++ } ++ } else ++ crypt_off -= 8; ++ *first = mydata.data32[0]; ++ *data32 = mydata.data32[1]; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ } ++ ++ /* finish the hash */ ++ CVMX_PREFETCH0(od->octo_hmouter); ++#if 0 ++ if (unlikely(inplen)) { ++ uint64_t tmp = 0; ++ uint8_t *p = (uint8_t *) & tmp; ++ p[inplen] = 0x80; ++ do { ++ inplen--; ++ p[inplen] = ((uint8_t *) data)[inplen]; ++ } while (inplen); ++ CVM_LOAD_SHA_UNIT(tmp, next); ++ } else { ++ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); ++ } ++#else ++ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); ++#endif ++ ++ /* Finish Inner hash */ ++ while (next != 7) { ++ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); ++ } ++ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); ++ ++ /* Get the inner hash of HMAC */ ++ CVMX_MF_HSH_IV(tmp1, 0); ++ CVMX_MF_HSH_IV(tmp2, 1); ++ tmp3 = 0; ++ CVMX_MF_HSH_IV(tmp3, 2); ++ ++ /* Initialize hash unit */ ++ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); ++ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); ++ ++ CVMX_MT_HSH_DAT(tmp1, 0); ++ CVMX_MT_HSH_DAT(tmp2, 1); ++ tmp3 |= 0x0000000080000000; ++ CVMX_MT_HSH_DAT(tmp3, 2); ++ CVMX_MT_HSH_DATZ(3); ++ CVMX_MT_HSH_DATZ(4); ++ CVMX_MT_HSH_DATZ(5); ++ CVMX_MT_HSH_DATZ(6); ++ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); ++ /* save the HMAC */ ++ SG_INIT(sg, data32, data_i, data_l); ++ while (icv_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ icv_off -= 4; ++ } ++ CVMX_MF_HSH_IV(tmp1, 0); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ SG_CONSUME(sg, data32, data_i, data_l); ++ *data32 = (uint32_t) tmp1; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVMX_MF_HSH_IV(tmp1, 1); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++/****************************************************************************/ ++/* AES MD5 */ ++ ++int ++octo_aes_cbc_md5_encrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ register int next = 0; ++ union { ++ uint32_t data32[2]; ++ uint64_t data64[1]; ++ } mydata[2]; ++ uint64_t *pdata = &mydata[0].data64[0]; ++ uint64_t *data = &mydata[1].data64[0]; ++ uint32_t *data32; ++ uint64_t tmp1, tmp2; ++ int data_i, data_l, alen = auth_len; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || ++ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || ++ (crypt_len & 0x7) || ++ (auth_len & 0x7) || ++ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data32, data_i, data_l); ++ ++ CVMX_PREFETCH0(ivp); ++ CVMX_PREFETCH0(od->octo_enckey); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* load AES Key */ ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); ++ ++ if (od->octo_encklen == 16) { ++ CVMX_MT_AES_KEY(0x0, 2); ++ CVMX_MT_AES_KEY(0x0, 3); ++ } else if (od->octo_encklen == 24) { ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ CVMX_MT_AES_KEY(0x0, 3); ++ } else if (od->octo_encklen == 32) { ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); ++ } else { ++ octeon_crypto_disable(&state, flags); ++ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); ++ return -EINVAL; ++ } ++ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); ++ ++ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); ++ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); ++ ++ /* Load MD5 IV */ ++ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); ++ ++ while (crypt_off > 0 && auth_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ crypt_off -= 4; ++ auth_off -= 4; ++ } ++ ++ /* align auth and crypt */ ++ while (crypt_off > 0 && auth_len > 0) { ++ mydata[0].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata[0].data32[1] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVM_LOAD_MD5_UNIT(*pdata, next); ++ crypt_off -= 8; ++ auth_len -= 8; ++ } ++ ++ while (crypt_len > 0) { ++ uint32_t *pdata32[3]; ++ ++ pdata32[0] = data32; ++ mydata[0].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ ++ pdata32[1] = data32; ++ mydata[0].data32[1] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ ++ pdata32[2] = data32; ++ mydata[1].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ ++ mydata[1].data32[1] = *data32; ++ ++ CVMX_MT_AES_ENC_CBC0(*pdata); ++ CVMX_MT_AES_ENC_CBC1(*data); ++ CVMX_MF_AES_RESULT(*pdata, 0); ++ CVMX_MF_AES_RESULT(*data, 1); ++ crypt_len -= 16; ++ ++ if (auth_len > 0) { ++ CVM_LOAD_MD5_UNIT(*pdata, next); ++ auth_len -= 8; ++ } ++ if (auth_len > 0) { ++ CVM_LOAD_MD5_UNIT(*data, next); ++ auth_len -= 8; ++ } ++ ++ *pdata32[0] = mydata[0].data32[0]; ++ *pdata32[1] = mydata[0].data32[1]; ++ *pdata32[2] = mydata[1].data32[0]; ++ *data32 = mydata[1].data32[1]; ++ ++ SG_CONSUME(sg, data32, data_i, data_l); ++ } ++ ++ /* finish any left over hashing */ ++ while (auth_len > 0) { ++ mydata[0].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata[0].data32[1] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVM_LOAD_MD5_UNIT(*pdata, next); ++ auth_len -= 8; ++ } ++ ++ /* finish the hash */ ++ CVMX_PREFETCH0(od->octo_hmouter); ++#if 0 ++ if (unlikely(inplen)) { ++ uint64_t tmp = 0; ++ uint8_t *p = (uint8_t *) & tmp; ++ p[inplen] = 0x80; ++ do { ++ inplen--; ++ p[inplen] = ((uint8_t *) data)[inplen]; ++ } while (inplen); ++ CVM_LOAD_MD5_UNIT(tmp, next); ++ } else { ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++ } ++#else ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++#endif ++ ++ /* Finish Inner hash */ ++ while (next != 7) { ++ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); ++ } ++ CVMX_ES64(tmp1, ((alen + 64) << 3)); ++ CVM_LOAD_MD5_UNIT(tmp1, next); ++ ++ /* Get the inner hash of HMAC */ ++ CVMX_MF_HSH_IV(tmp1, 0); ++ CVMX_MF_HSH_IV(tmp2, 1); ++ ++ /* Initialize hash unit */ ++ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); ++ ++ CVMX_MT_HSH_DAT(tmp1, 0); ++ CVMX_MT_HSH_DAT(tmp2, 1); ++ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); ++ CVMX_MT_HSH_DATZ(3); ++ CVMX_MT_HSH_DATZ(4); ++ CVMX_MT_HSH_DATZ(5); ++ CVMX_MT_HSH_DATZ(6); ++ CVMX_ES64(tmp1, ((64 + 16) << 3)); ++ CVMX_MT_HSH_STARTMD5(tmp1); ++ ++ /* save the HMAC */ ++ SG_INIT(sg, data32, data_i, data_l); ++ while (icv_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ icv_off -= 4; ++ } ++ CVMX_MF_HSH_IV(tmp1, 0); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ SG_CONSUME(sg, data32, data_i, data_l); ++ *data32 = (uint32_t) tmp1; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVMX_MF_HSH_IV(tmp1, 1); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++int ++octo_aes_cbc_md5_decrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ register int next = 0; ++ union { ++ uint32_t data32[2]; ++ uint64_t data64[1]; ++ } mydata[2]; ++ uint64_t *pdata = &mydata[0].data64[0]; ++ uint64_t *data = &mydata[1].data64[0]; ++ uint32_t *data32; ++ uint64_t tmp1, tmp2; ++ int data_i, data_l, alen = auth_len; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || ++ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || ++ (crypt_len & 0x7) || ++ (auth_len & 0x7) || ++ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data32, data_i, data_l); ++ ++ CVMX_PREFETCH0(ivp); ++ CVMX_PREFETCH0(od->octo_enckey); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* load AES Key */ ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); ++ ++ if (od->octo_encklen == 16) { ++ CVMX_MT_AES_KEY(0x0, 2); ++ CVMX_MT_AES_KEY(0x0, 3); ++ } else if (od->octo_encklen == 24) { ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ CVMX_MT_AES_KEY(0x0, 3); ++ } else if (od->octo_encklen == 32) { ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); ++ } else { ++ octeon_crypto_disable(&state, flags); ++ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); ++ return -EINVAL; ++ } ++ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); ++ ++ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); ++ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); ++ ++ /* Load MD5 IV */ ++ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); ++ ++ while (crypt_off > 0 && auth_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ crypt_off -= 4; ++ auth_off -= 4; ++ } ++ ++ /* align auth and crypt */ ++ while (crypt_off > 0 && auth_len > 0) { ++ mydata[0].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata[0].data32[1] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVM_LOAD_MD5_UNIT(*pdata, next); ++ crypt_off -= 8; ++ auth_len -= 8; ++ } ++ ++ while (crypt_len > 0) { ++ uint32_t *pdata32[3]; ++ ++ pdata32[0] = data32; ++ mydata[0].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ pdata32[1] = data32; ++ mydata[0].data32[1] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ pdata32[2] = data32; ++ mydata[1].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata[1].data32[1] = *data32; ++ ++ if (auth_len > 0) { ++ CVM_LOAD_MD5_UNIT(*pdata, next); ++ auth_len -= 8; ++ } ++ ++ if (auth_len > 0) { ++ CVM_LOAD_MD5_UNIT(*data, next); ++ auth_len -= 8; ++ } ++ ++ CVMX_MT_AES_DEC_CBC0(*pdata); ++ CVMX_MT_AES_DEC_CBC1(*data); ++ CVMX_MF_AES_RESULT(*pdata, 0); ++ CVMX_MF_AES_RESULT(*data, 1); ++ crypt_len -= 16; ++ ++ *pdata32[0] = mydata[0].data32[0]; ++ *pdata32[1] = mydata[0].data32[1]; ++ *pdata32[2] = mydata[1].data32[0]; ++ *data32 = mydata[1].data32[1]; ++ ++ SG_CONSUME(sg, data32, data_i, data_l); ++ } ++ ++ /* finish left over hash if any */ ++ while (auth_len > 0) { ++ mydata[0].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata[0].data32[1] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVM_LOAD_MD5_UNIT(*pdata, next); ++ auth_len -= 8; ++ } ++ ++ ++ /* finish the hash */ ++ CVMX_PREFETCH0(od->octo_hmouter); ++#if 0 ++ if (unlikely(inplen)) { ++ uint64_t tmp = 0; ++ uint8_t *p = (uint8_t *) & tmp; ++ p[inplen] = 0x80; ++ do { ++ inplen--; ++ p[inplen] = ((uint8_t *) data)[inplen]; ++ } while (inplen); ++ CVM_LOAD_MD5_UNIT(tmp, next); ++ } else { ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++ } ++#else ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++#endif ++ ++ /* Finish Inner hash */ ++ while (next != 7) { ++ CVM_LOAD_MD5_UNIT(((uint64_t) 0x0ULL), next); ++ } ++ CVMX_ES64(tmp1, ((alen + 64) << 3)); ++ CVM_LOAD_MD5_UNIT(tmp1, next); ++ ++ /* Get the inner hash of HMAC */ ++ CVMX_MF_HSH_IV(tmp1, 0); ++ CVMX_MF_HSH_IV(tmp2, 1); ++ ++ /* Initialize hash unit */ ++ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); ++ ++ CVMX_MT_HSH_DAT(tmp1, 0); ++ CVMX_MT_HSH_DAT(tmp2, 1); ++ CVMX_MT_HSH_DAT(0x8000000000000000ULL, 2); ++ CVMX_MT_HSH_DATZ(3); ++ CVMX_MT_HSH_DATZ(4); ++ CVMX_MT_HSH_DATZ(5); ++ CVMX_MT_HSH_DATZ(6); ++ CVMX_ES64(tmp1, ((64 + 16) << 3)); ++ CVMX_MT_HSH_STARTMD5(tmp1); ++ ++ /* save the HMAC */ ++ SG_INIT(sg, data32, data_i, data_l); ++ while (icv_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ icv_off -= 4; ++ } ++ CVMX_MF_HSH_IV(tmp1, 0); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ SG_CONSUME(sg, data32, data_i, data_l); ++ *data32 = (uint32_t) tmp1; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVMX_MF_HSH_IV(tmp1, 1); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++/****************************************************************************/ ++/* AES SHA1 */ ++ ++int ++octo_aes_cbc_sha1_encrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ register int next = 0; ++ union { ++ uint32_t data32[2]; ++ uint64_t data64[1]; ++ } mydata[2]; ++ uint64_t *pdata = &mydata[0].data64[0]; ++ uint64_t *data = &mydata[1].data64[0]; ++ uint32_t *data32; ++ uint64_t tmp1, tmp2, tmp3; ++ int data_i, data_l, alen = auth_len; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s(a_off=%d a_len=%d c_off=%d c_len=%d icv_off=%d)\n", ++ __FUNCTION__, auth_off, auth_len, crypt_off, crypt_len, icv_off); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || ++ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || ++ (crypt_len & 0x7) || ++ (auth_len & 0x7) || ++ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data32, data_i, data_l); ++ ++ CVMX_PREFETCH0(ivp); ++ CVMX_PREFETCH0(od->octo_enckey); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* load AES Key */ ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); ++ ++ if (od->octo_encklen == 16) { ++ CVMX_MT_AES_KEY(0x0, 2); ++ CVMX_MT_AES_KEY(0x0, 3); ++ } else if (od->octo_encklen == 24) { ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ CVMX_MT_AES_KEY(0x0, 3); ++ } else if (od->octo_encklen == 32) { ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); ++ } else { ++ octeon_crypto_disable(&state, flags); ++ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); ++ return -EINVAL; ++ } ++ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); ++ ++ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); ++ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); ++ ++ /* Load SHA IV */ ++ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); ++ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); ++ ++ while (crypt_off > 0 && auth_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ crypt_off -= 4; ++ auth_off -= 4; ++ } ++ ++ /* align auth and crypt */ ++ while (crypt_off > 0 && auth_len > 0) { ++ mydata[0].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata[0].data32[1] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVM_LOAD_SHA_UNIT(*pdata, next); ++ crypt_off -= 8; ++ auth_len -= 8; ++ } ++ ++ while (crypt_len > 0) { ++ uint32_t *pdata32[3]; ++ ++ pdata32[0] = data32; ++ mydata[0].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ pdata32[1] = data32; ++ mydata[0].data32[1] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ pdata32[2] = data32; ++ mydata[1].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata[1].data32[1] = *data32; ++ ++ CVMX_MT_AES_ENC_CBC0(*pdata); ++ CVMX_MT_AES_ENC_CBC1(*data); ++ CVMX_MF_AES_RESULT(*pdata, 0); ++ CVMX_MF_AES_RESULT(*data, 1); ++ crypt_len -= 16; ++ ++ if (auth_len > 0) { ++ CVM_LOAD_SHA_UNIT(*pdata, next); ++ auth_len -= 8; ++ } ++ if (auth_len > 0) { ++ CVM_LOAD_SHA_UNIT(*data, next); ++ auth_len -= 8; ++ } ++ ++ *pdata32[0] = mydata[0].data32[0]; ++ *pdata32[1] = mydata[0].data32[1]; ++ *pdata32[2] = mydata[1].data32[0]; ++ *data32 = mydata[1].data32[1]; ++ ++ SG_CONSUME(sg, data32, data_i, data_l); ++ } ++ ++ /* finish and hashing */ ++ while (auth_len > 0) { ++ mydata[0].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata[0].data32[1] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVM_LOAD_SHA_UNIT(*pdata, next); ++ auth_len -= 8; ++ } ++ ++ /* finish the hash */ ++ CVMX_PREFETCH0(od->octo_hmouter); ++#if 0 ++ if (unlikely(inplen)) { ++ uint64_t tmp = 0; ++ uint8_t *p = (uint8_t *) & tmp; ++ p[inplen] = 0x80; ++ do { ++ inplen--; ++ p[inplen] = ((uint8_t *) data)[inplen]; ++ } while (inplen); ++ CVM_LOAD_SHA_UNIT(tmp, next); ++ } else { ++ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); ++ } ++#else ++ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); ++#endif ++ ++ /* Finish Inner hash */ ++ while (next != 7) { ++ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); ++ } ++ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); ++ ++ /* Get the inner hash of HMAC */ ++ CVMX_MF_HSH_IV(tmp1, 0); ++ CVMX_MF_HSH_IV(tmp2, 1); ++ tmp3 = 0; ++ CVMX_MF_HSH_IV(tmp3, 2); ++ ++ /* Initialize hash unit */ ++ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); ++ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); ++ ++ CVMX_MT_HSH_DAT(tmp1, 0); ++ CVMX_MT_HSH_DAT(tmp2, 1); ++ tmp3 |= 0x0000000080000000; ++ CVMX_MT_HSH_DAT(tmp3, 2); ++ CVMX_MT_HSH_DATZ(3); ++ CVMX_MT_HSH_DATZ(4); ++ CVMX_MT_HSH_DATZ(5); ++ CVMX_MT_HSH_DATZ(6); ++ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); ++ ++ /* finish the hash */ ++ CVMX_PREFETCH0(od->octo_hmouter); ++#if 0 ++ if (unlikely(inplen)) { ++ uint64_t tmp = 0; ++ uint8_t *p = (uint8_t *) & tmp; ++ p[inplen] = 0x80; ++ do { ++ inplen--; ++ p[inplen] = ((uint8_t *) data)[inplen]; ++ } while (inplen); ++ CVM_LOAD_MD5_UNIT(tmp, next); ++ } else { ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++ } ++#else ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++#endif ++ ++ /* save the HMAC */ ++ SG_INIT(sg, data32, data_i, data_l); ++ while (icv_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ icv_off -= 4; ++ } ++ CVMX_MF_HSH_IV(tmp1, 0); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ SG_CONSUME(sg, data32, data_i, data_l); ++ *data32 = (uint32_t) tmp1; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVMX_MF_HSH_IV(tmp1, 1); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++int ++octo_aes_cbc_sha1_decrypt( ++ struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp) ++{ ++ register int next = 0; ++ union { ++ uint32_t data32[2]; ++ uint64_t data64[1]; ++ } mydata[2]; ++ uint64_t *pdata = &mydata[0].data64[0]; ++ uint64_t *data = &mydata[1].data64[0]; ++ uint32_t *data32; ++ uint64_t tmp1, tmp2, tmp3; ++ int data_i, data_l, alen = auth_len; ++ struct octeon_cop2_state state; ++ unsigned long flags; ++ ++ dprintk("%s(a_off=%d a_len=%d c_off=%d c_len=%d icv_off=%d)\n", ++ __FUNCTION__, auth_off, auth_len, crypt_off, crypt_len, icv_off); ++ ++ if (unlikely(od == NULL || sg==NULL || sg_len==0 || ivp==NULL || ++ (crypt_off & 0x3) || (crypt_off + crypt_len > sg_len) || ++ (crypt_len & 0x7) || ++ (auth_len & 0x7) || ++ (auth_off & 0x3) || (auth_off + auth_len > sg_len))) { ++ dprintk("%s: Bad parameters od=%p sg=%p sg_len=%d " ++ "auth_off=%d auth_len=%d crypt_off=%d crypt_len=%d " ++ "icv_off=%d ivp=%p\n", __FUNCTION__, od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ return -EINVAL; ++ } ++ ++ SG_INIT(sg, data32, data_i, data_l); ++ ++ CVMX_PREFETCH0(ivp); ++ CVMX_PREFETCH0(od->octo_enckey); ++ ++ flags = octeon_crypto_enable(&state); ++ ++ /* load AES Key */ ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[0], 0); ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[1], 1); ++ ++ if (od->octo_encklen == 16) { ++ CVMX_MT_AES_KEY(0x0, 2); ++ CVMX_MT_AES_KEY(0x0, 3); ++ } else if (od->octo_encklen == 24) { ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ CVMX_MT_AES_KEY(0x0, 3); ++ } else if (od->octo_encklen == 32) { ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[2], 2); ++ CVMX_MT_AES_KEY(((uint64_t *) od->octo_enckey)[3], 3); ++ } else { ++ octeon_crypto_disable(&state, flags); ++ dprintk("%s: Bad key length %d\n", __FUNCTION__, od->octo_encklen); ++ return -EINVAL; ++ } ++ CVMX_MT_AES_KEYLENGTH(od->octo_encklen / 8 - 1); ++ ++ CVMX_MT_AES_IV(((uint64_t *) ivp)[0], 0); ++ CVMX_MT_AES_IV(((uint64_t *) ivp)[1], 1); ++ ++ /* Load SHA1 IV */ ++ CVMX_MT_HSH_IV(od->octo_hminner[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hminner[1], 1); ++ CVMX_MT_HSH_IV(od->octo_hminner[2], 2); ++ ++ while (crypt_off > 0 && auth_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ crypt_off -= 4; ++ auth_off -= 4; ++ } ++ ++ /* align auth and crypt */ ++ while (crypt_off > 0 && auth_len > 0) { ++ mydata[0].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata[0].data32[1] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVM_LOAD_SHA_UNIT(*pdata, next); ++ crypt_off -= 8; ++ auth_len -= 8; ++ } ++ ++ while (crypt_len > 0) { ++ uint32_t *pdata32[3]; ++ ++ pdata32[0] = data32; ++ mydata[0].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ pdata32[1] = data32; ++ mydata[0].data32[1] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ pdata32[2] = data32; ++ mydata[1].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata[1].data32[1] = *data32; ++ ++ if (auth_len > 0) { ++ CVM_LOAD_SHA_UNIT(*pdata, next); ++ auth_len -= 8; ++ } ++ if (auth_len > 0) { ++ CVM_LOAD_SHA_UNIT(*data, next); ++ auth_len -= 8; ++ } ++ ++ CVMX_MT_AES_DEC_CBC0(*pdata); ++ CVMX_MT_AES_DEC_CBC1(*data); ++ CVMX_MF_AES_RESULT(*pdata, 0); ++ CVMX_MF_AES_RESULT(*data, 1); ++ crypt_len -= 16; ++ ++ *pdata32[0] = mydata[0].data32[0]; ++ *pdata32[1] = mydata[0].data32[1]; ++ *pdata32[2] = mydata[1].data32[0]; ++ *data32 = mydata[1].data32[1]; ++ ++ SG_CONSUME(sg, data32, data_i, data_l); ++ } ++ ++ /* finish and leftover hashing */ ++ while (auth_len > 0) { ++ mydata[0].data32[0] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ mydata[0].data32[1] = *data32; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVM_LOAD_SHA_UNIT(*pdata, next); ++ auth_len -= 8; ++ } ++ ++ /* finish the hash */ ++ CVMX_PREFETCH0(od->octo_hmouter); ++#if 0 ++ if (unlikely(inplen)) { ++ uint64_t tmp = 0; ++ uint8_t *p = (uint8_t *) & tmp; ++ p[inplen] = 0x80; ++ do { ++ inplen--; ++ p[inplen] = ((uint8_t *) data)[inplen]; ++ } while (inplen); ++ CVM_LOAD_SHA_UNIT(tmp, next); ++ } else { ++ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); ++ } ++#else ++ CVM_LOAD_SHA_UNIT(0x8000000000000000ULL, next); ++#endif ++ ++ /* Finish Inner hash */ ++ while (next != 7) { ++ CVM_LOAD_SHA_UNIT(((uint64_t) 0x0ULL), next); ++ } ++ CVM_LOAD_SHA_UNIT((uint64_t) ((alen + 64) << 3), next); ++ ++ /* Get the inner hash of HMAC */ ++ CVMX_MF_HSH_IV(tmp1, 0); ++ CVMX_MF_HSH_IV(tmp2, 1); ++ tmp3 = 0; ++ CVMX_MF_HSH_IV(tmp3, 2); ++ ++ /* Initialize hash unit */ ++ CVMX_MT_HSH_IV(od->octo_hmouter[0], 0); ++ CVMX_MT_HSH_IV(od->octo_hmouter[1], 1); ++ CVMX_MT_HSH_IV(od->octo_hmouter[2], 2); ++ ++ CVMX_MT_HSH_DAT(tmp1, 0); ++ CVMX_MT_HSH_DAT(tmp2, 1); ++ tmp3 |= 0x0000000080000000; ++ CVMX_MT_HSH_DAT(tmp3, 2); ++ CVMX_MT_HSH_DATZ(3); ++ CVMX_MT_HSH_DATZ(4); ++ CVMX_MT_HSH_DATZ(5); ++ CVMX_MT_HSH_DATZ(6); ++ CVMX_MT_HSH_STARTSHA((uint64_t) ((64 + 20) << 3)); ++ ++ /* finish the hash */ ++ CVMX_PREFETCH0(od->octo_hmouter); ++#if 0 ++ if (unlikely(inplen)) { ++ uint64_t tmp = 0; ++ uint8_t *p = (uint8_t *) & tmp; ++ p[inplen] = 0x80; ++ do { ++ inplen--; ++ p[inplen] = ((uint8_t *) data)[inplen]; ++ } while (inplen); ++ CVM_LOAD_MD5_UNIT(tmp, next); ++ } else { ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++ } ++#else ++ CVM_LOAD_MD5_UNIT(0x8000000000000000ULL, next); ++#endif ++ ++ /* save the HMAC */ ++ SG_INIT(sg, data32, data_i, data_l); ++ while (icv_off > 0) { ++ SG_CONSUME(sg, data32, data_i, data_l); ++ icv_off -= 4; ++ } ++ CVMX_MF_HSH_IV(tmp1, 0); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ SG_CONSUME(sg, data32, data_i, data_l); ++ *data32 = (uint32_t) tmp1; ++ SG_CONSUME(sg, data32, data_i, data_l); ++ CVMX_MF_HSH_IV(tmp1, 1); ++ *data32 = (uint32_t) (tmp1 >> 32); ++ ++ octeon_crypto_disable(&state, flags); ++ return 0; ++} ++ ++/****************************************************************************/ +diff -Nur linux-3.1.4.orig/crypto/ocf/cryptocteon/cryptocteon.c linux-3.1.4/crypto/ocf/cryptocteon/cryptocteon.c +--- linux-3.1.4.orig/crypto/ocf/cryptocteon/cryptocteon.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/cryptocteon/cryptocteon.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,575 @@ ++/* ++ * Octeon Crypto for OCF ++ * ++ * Written by David McCullough ++ * Copyright (C) 2009-2010 David McCullough ++ * ++ * LICENSE TERMS ++ * ++ * The free distribution and use of this software in both source and binary ++ * form is allowed (with or without changes) provided that: ++ * ++ * 1. distributions of this source code include the above copyright ++ * notice, this list of conditions and the following disclaimer; ++ * ++ * 2. distributions in binary form include the above copyright ++ * notice, this list of conditions and the following disclaimer ++ * in the documentation and/or other associated materials; ++ * ++ * 3. the copyright holder's name is not used to endorse products ++ * built using this software without specific written permission. ++ * ++ * DISCLAIMER ++ * ++ * This software is provided 'as is' with no explicit or implied warranties ++ * in respect of its properties, including, but not limited to, correctness ++ * and/or fitness for purpose. ++ * --------------------------------------------------------------------------- ++ */ ++ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++struct { ++ softc_device_decl sc_dev; ++} octo_softc; ++ ++#define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK) ++ ++struct octo_sess { ++ int octo_encalg; ++ #define MAX_CIPHER_KEYLEN 64 ++ char octo_enckey[MAX_CIPHER_KEYLEN]; ++ int octo_encklen; ++ ++ int octo_macalg; ++ #define MAX_HASH_KEYLEN 64 ++ char octo_mackey[MAX_HASH_KEYLEN]; ++ int octo_macklen; ++ int octo_mackey_set; ++ ++ int octo_mlen; ++ int octo_ivsize; ++ ++ int (*octo_encrypt)(struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp); ++ int (*octo_decrypt)(struct octo_sess *od, ++ struct scatterlist *sg, int sg_len, ++ int auth_off, int auth_len, ++ int crypt_off, int crypt_len, ++ int icv_off, uint8_t *ivp); ++ ++ uint64_t octo_hminner[3]; ++ uint64_t octo_hmouter[3]; ++}; ++ ++int32_t octo_id = -1; ++module_param(octo_id, int, 0444); ++MODULE_PARM_DESC(octo_id, "Read-Only OCF ID for cryptocteon driver"); ++ ++static struct octo_sess **octo_sessions = NULL; ++static u_int32_t octo_sesnum = 0; ++ ++static int octo_process(device_t, struct cryptop *, int); ++static int octo_newsession(device_t, u_int32_t *, struct cryptoini *); ++static int octo_freesession(device_t, u_int64_t); ++ ++static device_method_t octo_methods = { ++ /* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, octo_newsession), ++ DEVMETHOD(cryptodev_freesession,octo_freesession), ++ DEVMETHOD(cryptodev_process, octo_process), ++}; ++ ++#define debug octo_debug ++int octo_debug = 0; ++module_param(octo_debug, int, 0644); ++MODULE_PARM_DESC(octo_debug, "Enable debug"); ++ ++ ++#include "cavium_crypto.c" ++ ++ ++/* ++ * Generate a new octo session. We artifically limit it to a single ++ * hash/cipher or hash-cipher combo just to make it easier, most callers ++ * do not expect more than this anyway. ++ */ ++static int ++octo_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) ++{ ++ struct cryptoini *c, *encini = NULL, *macini = NULL; ++ struct octo_sess **ocd; ++ int i; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (sid == NULL || cri == NULL) { ++ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ /* ++ * To keep it simple, we only handle hash, cipher or hash/cipher in a ++ * session, you cannot currently do multiple ciphers/hashes in one ++ * session even though it would be possibel to code this driver to ++ * handle it. ++ */ ++ for (i = 0, c = cri; c && i < 2; i++) { ++ if (c->cri_alg == CRYPTO_MD5_HMAC || ++ c->cri_alg == CRYPTO_SHA1_HMAC || ++ c->cri_alg == CRYPTO_NULL_HMAC) { ++ if (macini) { ++ break; ++ } ++ macini = c; ++ } ++ if (c->cri_alg == CRYPTO_DES_CBC || ++ c->cri_alg == CRYPTO_3DES_CBC || ++ c->cri_alg == CRYPTO_AES_CBC || ++ c->cri_alg == CRYPTO_NULL_CBC) { ++ if (encini) { ++ break; ++ } ++ encini = c; ++ } ++ c = c->cri_next; ++ } ++ if (!macini && !encini) { ++ dprintk("%s,%d - EINVAL bad cipher/hash or combination\n", ++ __FILE__, __LINE__); ++ return EINVAL; ++ } ++ if (c) { ++ dprintk("%s,%d - EINVAL cannot handle chained cipher/hash combos\n", ++ __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ /* ++ * So we have something we can do, lets setup the session ++ */ ++ ++ if (octo_sessions) { ++ for (i = 1; i < octo_sesnum; i++) ++ if (octo_sessions[i] == NULL) ++ break; ++ } else ++ i = 1; /* NB: to silence compiler warning */ ++ ++ if (octo_sessions == NULL || i == octo_sesnum) { ++ if (octo_sessions == NULL) { ++ i = 1; /* We leave octo_sessions[0] empty */ ++ octo_sesnum = CRYPTO_SW_SESSIONS; ++ } else ++ octo_sesnum *= 2; ++ ++ ocd = kmalloc(octo_sesnum * sizeof(struct octo_sess *), SLAB_ATOMIC); ++ if (ocd == NULL) { ++ /* Reset session number */ ++ if (octo_sesnum == CRYPTO_SW_SESSIONS) ++ octo_sesnum = 0; ++ else ++ octo_sesnum /= 2; ++ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ memset(ocd, 0, octo_sesnum * sizeof(struct octo_sess *)); ++ ++ /* Copy existing sessions */ ++ if (octo_sessions) { ++ memcpy(ocd, octo_sessions, ++ (octo_sesnum / 2) * sizeof(struct octo_sess *)); ++ kfree(octo_sessions); ++ } ++ ++ octo_sessions = ocd; ++ } ++ ++ ocd = &octo_sessions[i]; ++ *sid = i; ++ ++ ++ *ocd = (struct octo_sess *) kmalloc(sizeof(struct octo_sess), SLAB_ATOMIC); ++ if (*ocd == NULL) { ++ octo_freesession(NULL, i); ++ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ memset(*ocd, 0, sizeof(struct octo_sess)); ++ ++ if (encini && encini->cri_key) { ++ (*ocd)->octo_encklen = (encini->cri_klen + 7) / 8; ++ memcpy((*ocd)->octo_enckey, encini->cri_key, (*ocd)->octo_encklen); ++ } ++ ++ if (macini && macini->cri_key) { ++ (*ocd)->octo_macklen = (macini->cri_klen + 7) / 8; ++ memcpy((*ocd)->octo_mackey, macini->cri_key, (*ocd)->octo_macklen); ++ } ++ ++ (*ocd)->octo_mlen = 0; ++ if (encini && encini->cri_mlen) ++ (*ocd)->octo_mlen = encini->cri_mlen; ++ else if (macini && macini->cri_mlen) ++ (*ocd)->octo_mlen = macini->cri_mlen; ++ else ++ (*ocd)->octo_mlen = 12; ++ ++ /* ++ * point c at the enc if it exists, otherwise the mac ++ */ ++ c = encini ? encini : macini; ++ ++ switch (c->cri_alg) { ++ case CRYPTO_DES_CBC: ++ case CRYPTO_3DES_CBC: ++ (*ocd)->octo_ivsize = 8; ++ switch (macini ? macini->cri_alg : -1) { ++ case CRYPTO_MD5_HMAC: ++ (*ocd)->octo_encrypt = octo_des_cbc_md5_encrypt; ++ (*ocd)->octo_decrypt = octo_des_cbc_md5_decrypt; ++ octo_calc_hash(0, macini->cri_key, (*ocd)->octo_hminner, ++ (*ocd)->octo_hmouter); ++ break; ++ case CRYPTO_SHA1_HMAC: ++ (*ocd)->octo_encrypt = octo_des_cbc_sha1_encrypt; ++ (*ocd)->octo_decrypt = octo_des_cbc_sha1_decrypt; ++ octo_calc_hash(1, macini->cri_key, (*ocd)->octo_hminner, ++ (*ocd)->octo_hmouter); ++ break; ++ case -1: ++ (*ocd)->octo_encrypt = octo_des_cbc_encrypt; ++ (*ocd)->octo_decrypt = octo_des_cbc_decrypt; ++ break; ++ default: ++ octo_freesession(NULL, i); ++ dprintk("%s,%d: EINVALn", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ break; ++ case CRYPTO_AES_CBC: ++ (*ocd)->octo_ivsize = 16; ++ switch (macini ? macini->cri_alg : -1) { ++ case CRYPTO_MD5_HMAC: ++ (*ocd)->octo_encrypt = octo_aes_cbc_md5_encrypt; ++ (*ocd)->octo_decrypt = octo_aes_cbc_md5_decrypt; ++ octo_calc_hash(0, macini->cri_key, (*ocd)->octo_hminner, ++ (*ocd)->octo_hmouter); ++ break; ++ case CRYPTO_SHA1_HMAC: ++ (*ocd)->octo_encrypt = octo_aes_cbc_sha1_encrypt; ++ (*ocd)->octo_decrypt = octo_aes_cbc_sha1_decrypt; ++ octo_calc_hash(1, macini->cri_key, (*ocd)->octo_hminner, ++ (*ocd)->octo_hmouter); ++ break; ++ case -1: ++ (*ocd)->octo_encrypt = octo_aes_cbc_encrypt; ++ (*ocd)->octo_decrypt = octo_aes_cbc_decrypt; ++ break; ++ default: ++ octo_freesession(NULL, i); ++ dprintk("%s,%d: EINVALn", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ break; ++ case CRYPTO_MD5_HMAC: ++ (*ocd)->octo_encrypt = octo_null_md5_encrypt; ++ (*ocd)->octo_decrypt = octo_null_md5_encrypt; /* encrypt == decrypt */ ++ octo_calc_hash(0, macini->cri_key, (*ocd)->octo_hminner, ++ (*ocd)->octo_hmouter); ++ break; ++ case CRYPTO_SHA1_HMAC: ++ (*ocd)->octo_encrypt = octo_null_sha1_encrypt; ++ (*ocd)->octo_decrypt = octo_null_sha1_encrypt; /* encrypt == decrypt */ ++ octo_calc_hash(1, macini->cri_key, (*ocd)->octo_hminner, ++ (*ocd)->octo_hmouter); ++ break; ++ default: ++ octo_freesession(NULL, i); ++ dprintk("%s,%d: EINVALn", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ (*ocd)->octo_encalg = encini ? encini->cri_alg : -1; ++ (*ocd)->octo_macalg = macini ? macini->cri_alg : -1; ++ ++ return 0; ++} ++ ++/* ++ * Free a session. ++ */ ++static int ++octo_freesession(device_t dev, u_int64_t tid) ++{ ++ u_int32_t sid = CRYPTO_SESID2LID(tid); ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (sid > octo_sesnum || octo_sessions == NULL || ++ octo_sessions[sid] == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return(EINVAL); ++ } ++ ++ /* Silently accept and return */ ++ if (sid == 0) ++ return(0); ++ ++ if (octo_sessions[sid]) ++ kfree(octo_sessions[sid]); ++ octo_sessions[sid] = NULL; ++ return 0; ++} ++ ++/* ++ * Process a request. ++ */ ++static int ++octo_process(device_t dev, struct cryptop *crp, int hint) ++{ ++ struct cryptodesc *crd; ++ struct octo_sess *od; ++ u_int32_t lid; ++#define SCATTERLIST_MAX 16 ++ struct scatterlist sg[SCATTERLIST_MAX]; ++ int sg_num, sg_len; ++ struct sk_buff *skb = NULL; ++ struct uio *uiop = NULL; ++ struct cryptodesc *enccrd = NULL, *maccrd = NULL; ++ unsigned char *ivp = NULL; ++ unsigned char iv_data[HASH_MAX_LEN]; ++ int auth_off = 0, auth_len = 0, crypt_off = 0, crypt_len = 0, icv_off = 0; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ /* Sanity check */ ++ if (crp == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ crp->crp_etype = 0; ++ ++ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ crp->crp_etype = EINVAL; ++ goto done; ++ } ++ ++ lid = crp->crp_sid & 0xffffffff; ++ if (lid >= octo_sesnum || lid == 0 || octo_sessions == NULL || ++ octo_sessions[lid] == NULL) { ++ crp->crp_etype = ENOENT; ++ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); ++ goto done; ++ } ++ od = octo_sessions[lid]; ++ ++ /* ++ * do some error checking outside of the loop for SKB and IOV processing ++ * this leaves us with valid skb or uiop pointers for later ++ */ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ skb = (struct sk_buff *) crp->crp_buf; ++ if (skb_shinfo(skb)->nr_frags >= SCATTERLIST_MAX) { ++ printk("%s,%d: %d nr_frags > SCATTERLIST_MAX", __FILE__, __LINE__, ++ skb_shinfo(skb)->nr_frags); ++ goto done; ++ } ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ uiop = (struct uio *) crp->crp_buf; ++ if (uiop->uio_iovcnt > SCATTERLIST_MAX) { ++ printk("%s,%d: %d uio_iovcnt > SCATTERLIST_MAX", __FILE__, __LINE__, ++ uiop->uio_iovcnt); ++ goto done; ++ } ++ } ++ ++ /* point our enccrd and maccrd appropriately */ ++ crd = crp->crp_desc; ++ if (crd->crd_alg == od->octo_encalg) enccrd = crd; ++ if (crd->crd_alg == od->octo_macalg) maccrd = crd; ++ crd = crd->crd_next; ++ if (crd) { ++ if (crd->crd_alg == od->octo_encalg) enccrd = crd; ++ if (crd->crd_alg == od->octo_macalg) maccrd = crd; ++ crd = crd->crd_next; ++ } ++ if (crd) { ++ crp->crp_etype = EINVAL; ++ dprintk("%s,%d: ENOENT - descriptors do not match session\n", ++ __FILE__, __LINE__); ++ goto done; ++ } ++ ++ if (enccrd) { ++ if (enccrd->crd_flags & CRD_F_ENCRYPT) { ++ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) ++ ivp = enccrd->crd_iv; ++ else ++ read_random((ivp = iv_data), od->octo_ivsize); ++ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ enccrd->crd_inject, od->octo_ivsize, ivp); ++ } else { ++ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) { ++ ivp = enccrd->crd_iv; ++ } else { ++ ivp = iv_data; ++ crypto_copydata(crp->crp_flags, crp->crp_buf, ++ enccrd->crd_inject, od->octo_ivsize, (caddr_t) ivp); ++ } ++ } ++ ++ if (maccrd) { ++ auth_off = maccrd->crd_skip; ++ auth_len = maccrd->crd_len; ++ icv_off = maccrd->crd_inject; ++ } ++ ++ crypt_off = enccrd->crd_skip; ++ crypt_len = enccrd->crd_len; ++ } else { /* if (maccrd) */ ++ auth_off = maccrd->crd_skip; ++ auth_len = maccrd->crd_len; ++ icv_off = maccrd->crd_inject; ++ } ++ ++ ++ /* ++ * setup the SG list to cover the buffer ++ */ ++ memset(sg, 0, sizeof(sg)); ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ int i, len; ++ ++ sg_num = 0; ++ sg_len = 0; ++ ++ len = skb_headlen(skb); ++ sg_set_page(&sg[sg_num], virt_to_page(skb->data), len, ++ offset_in_page(skb->data)); ++ sg_len += len; ++ sg_num++; ++ ++ for (i = 0; i < skb_shinfo(skb)->nr_frags && sg_num < SCATTERLIST_MAX; ++ i++) { ++ len = skb_shinfo(skb)->frags[i].size; ++ sg_set_page(&sg[sg_num], skb_shinfo(skb)->frags[i].page, ++ len, skb_shinfo(skb)->frags[i].page_offset); ++ sg_len += len; ++ sg_num++; ++ } ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ int len; ++ ++ sg_len = 0; ++ for (sg_num = 0; sg_len < crp->crp_ilen && ++ sg_num < uiop->uio_iovcnt && ++ sg_num < SCATTERLIST_MAX; sg_num++) { ++ len = uiop->uio_iov[sg_num].iov_len; ++ sg_set_page(&sg[sg_num], ++ virt_to_page(uiop->uio_iov[sg_num].iov_base), len, ++ offset_in_page(uiop->uio_iov[sg_num].iov_base)); ++ sg_len += len; ++ } ++ } else { ++ sg_len = crp->crp_ilen; ++ sg_set_page(&sg[0], virt_to_page(crp->crp_buf), sg_len, ++ offset_in_page(crp->crp_buf)); ++ sg_num = 1; ++ } ++ ++ ++ /* ++ * setup a new explicit key ++ */ ++ if (enccrd) { ++ if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) { ++ od->octo_encklen = (enccrd->crd_klen + 7) / 8; ++ memcpy(od->octo_enckey, enccrd->crd_key, od->octo_encklen); ++ } ++ } ++ if (maccrd) { ++ if (maccrd->crd_flags & CRD_F_KEY_EXPLICIT) { ++ od->octo_macklen = (maccrd->crd_klen + 7) / 8; ++ memcpy(od->octo_mackey, maccrd->crd_key, od->octo_macklen); ++ od->octo_mackey_set = 0; ++ } ++ if (!od->octo_mackey_set) { ++ octo_calc_hash(maccrd->crd_alg == CRYPTO_MD5_HMAC ? 0 : 1, ++ maccrd->crd_key, od->octo_hminner, od->octo_hmouter); ++ od->octo_mackey_set = 1; ++ } ++ } ++ ++ ++ if (!enccrd || (enccrd->crd_flags & CRD_F_ENCRYPT)) ++ (*od->octo_encrypt)(od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ else ++ (*od->octo_decrypt)(od, sg, sg_len, ++ auth_off, auth_len, crypt_off, crypt_len, icv_off, ivp); ++ ++done: ++ crypto_done(crp); ++ return 0; ++} ++ ++static int ++cryptocteon_init(void) ++{ ++ dprintk("%s(%p)\n", __FUNCTION__, cryptocteon_init); ++ ++ softc_device_init(&octo_softc, "cryptocteon", 0, octo_methods); ++ ++ octo_id = crypto_get_driverid(softc_get_device(&octo_softc), ++ CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SYNC); ++ if (octo_id < 0) { ++ printk("Cryptocteon device cannot initialize!"); ++ return -ENODEV; ++ } ++ ++ crypto_register(octo_id, CRYPTO_MD5_HMAC, 0,0); ++ crypto_register(octo_id, CRYPTO_SHA1_HMAC, 0,0); ++ //crypto_register(octo_id, CRYPTO_MD5, 0,0); ++ //crypto_register(octo_id, CRYPTO_SHA1, 0,0); ++ crypto_register(octo_id, CRYPTO_DES_CBC, 0,0); ++ crypto_register(octo_id, CRYPTO_3DES_CBC, 0,0); ++ crypto_register(octo_id, CRYPTO_AES_CBC, 0,0); ++ ++ return(0); ++} ++ ++static void ++cryptocteon_exit(void) ++{ ++ dprintk("%s()\n", __FUNCTION__); ++ crypto_unregister_all(octo_id); ++ octo_id = -1; ++} ++ ++module_init(cryptocteon_init); ++module_exit(cryptocteon_exit); ++ ++MODULE_LICENSE("BSD"); ++MODULE_AUTHOR("David McCullough "); ++MODULE_DESCRIPTION("Cryptocteon (OCF module for Cavium OCTEON crypto)"); +diff -Nur linux-3.1.4.orig/crypto/ocf/cryptodev.c linux-3.1.4/crypto/ocf/cryptodev.c +--- linux-3.1.4.orig/crypto/ocf/cryptodev.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/cryptodev.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,1069 @@ ++/* $OpenBSD: cryptodev.c,v 1.52 2002/06/19 07:22:46 deraadt Exp $ */ ++ ++/*- ++ * Linux port done by David McCullough ++ * Copyright (C) 2006-2010 David McCullough ++ * Copyright (C) 2004-2005 Intel Corporation. ++ * The license and original author are listed below. ++ * ++ * Copyright (c) 2001 Theo de Raadt ++ * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored in part by the Defense Advanced Research Projects ++ * Agency (DARPA) and Air Force Research Laboratory, Air Force ++ * Materiel Command, USAF, under agreement number F30602-01-2-0537. ++ * ++__FBSDID("$FreeBSD: src/sys/opencrypto/cryptodev.c,v 1.34 2007/05/09 19:37:02 gnn Exp $"); ++ */ ++ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++extern asmlinkage long sys_dup(unsigned int fildes); ++ ++#define debug cryptodev_debug ++int cryptodev_debug = 0; ++module_param(cryptodev_debug, int, 0644); ++MODULE_PARM_DESC(cryptodev_debug, "Enable cryptodev debug"); ++ ++struct csession_info { ++ u_int16_t blocksize; ++ u_int16_t minkey, maxkey; ++ ++ u_int16_t keysize; ++ /* u_int16_t hashsize; */ ++ u_int16_t authsize; ++ u_int16_t authkey; ++ /* u_int16_t ctxsize; */ ++}; ++ ++struct csession { ++ struct list_head list; ++ u_int64_t sid; ++ u_int32_t ses; ++ ++ wait_queue_head_t waitq; ++ ++ u_int32_t cipher; ++ ++ u_int32_t mac; ++ ++ caddr_t key; ++ int keylen; ++ u_char tmp_iv[EALG_MAX_BLOCK_LEN]; ++ ++ caddr_t mackey; ++ int mackeylen; ++ ++ struct csession_info info; ++ ++ struct iovec iovec; ++ struct uio uio; ++ int error; ++}; ++ ++struct fcrypt { ++ struct list_head csessions; ++ int sesn; ++}; ++ ++static struct csession *csefind(struct fcrypt *, u_int); ++static int csedelete(struct fcrypt *, struct csession *); ++static struct csession *cseadd(struct fcrypt *, struct csession *); ++static struct csession *csecreate(struct fcrypt *, u_int64_t, ++ struct cryptoini *crie, struct cryptoini *cria, struct csession_info *); ++static int csefree(struct csession *); ++ ++static int cryptodev_op(struct csession *, struct crypt_op *); ++static int cryptodev_key(struct crypt_kop *); ++static int cryptodev_find(struct crypt_find_op *); ++ ++static int cryptodev_cb(void *); ++static int cryptodev_open(struct inode *inode, struct file *filp); ++ ++/* ++ * Check a crypto identifier to see if it requested ++ * a valid crid and it's capabilities match. ++ */ ++static int ++checkcrid(int crid) ++{ ++ int hid = crid & ~(CRYPTOCAP_F_SOFTWARE | CRYPTOCAP_F_HARDWARE); ++ int typ = crid & (CRYPTOCAP_F_SOFTWARE | CRYPTOCAP_F_HARDWARE); ++ int caps = 0; ++ ++ /* if the user hasn't selected a driver, then just call newsession */ ++ if (hid == 0 && typ != 0) ++ return 0; ++ ++ caps = crypto_getcaps(hid); ++ ++ /* didn't find anything with capabilities */ ++ if (caps == 0) { ++ dprintk("%s: hid=%x typ=%x not matched\n", __FUNCTION__, hid, typ); ++ return EINVAL; ++ } ++ ++ /* the user didn't specify SW or HW, so the driver is ok */ ++ if (typ == 0) ++ return 0; ++ ++ /* if the type specified didn't match */ ++ if (typ != (caps & (CRYPTOCAP_F_SOFTWARE | CRYPTOCAP_F_HARDWARE))) { ++ dprintk("%s: hid=%x typ=%x caps=%x not matched\n", __FUNCTION__, ++ hid, typ, caps); ++ return EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int ++cryptodev_op(struct csession *cse, struct crypt_op *cop) ++{ ++ struct cryptop *crp = NULL; ++ struct cryptodesc *crde = NULL, *crda = NULL; ++ int error = 0; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (cop->len > CRYPTO_MAX_DATA_LEN) { ++ dprintk("%s: %d > %d\n", __FUNCTION__, cop->len, CRYPTO_MAX_DATA_LEN); ++ return (E2BIG); ++ } ++ ++ if (cse->info.blocksize && (cop->len % cse->info.blocksize) != 0) { ++ dprintk("%s: blocksize=%d len=%d\n", __FUNCTION__, cse->info.blocksize, ++ cop->len); ++ return (EINVAL); ++ } ++ ++ cse->uio.uio_iov = &cse->iovec; ++ cse->uio.uio_iovcnt = 1; ++ cse->uio.uio_offset = 0; ++#if 0 ++ cse->uio.uio_resid = cop->len; ++ cse->uio.uio_segflg = UIO_SYSSPACE; ++ cse->uio.uio_rw = UIO_WRITE; ++ cse->uio.uio_td = td; ++#endif ++ cse->uio.uio_iov[0].iov_len = cop->len; ++ if (cse->info.authsize) ++ cse->uio.uio_iov[0].iov_len += cse->info.authsize; ++ cse->uio.uio_iov[0].iov_base = kmalloc(cse->uio.uio_iov[0].iov_len, ++ GFP_KERNEL); ++ ++ if (cse->uio.uio_iov[0].iov_base == NULL) { ++ dprintk("%s: iov_base kmalloc(%d) failed\n", __FUNCTION__, ++ (int)cse->uio.uio_iov[0].iov_len); ++ return (ENOMEM); ++ } ++ ++ crp = crypto_getreq((cse->info.blocksize != 0) + (cse->info.authsize != 0)); ++ if (crp == NULL) { ++ dprintk("%s: ENOMEM\n", __FUNCTION__); ++ error = ENOMEM; ++ goto bail; ++ } ++ ++ if (cse->info.authsize && cse->info.blocksize) { ++ if (cop->op == COP_ENCRYPT) { ++ crde = crp->crp_desc; ++ crda = crde->crd_next; ++ } else { ++ crda = crp->crp_desc; ++ crde = crda->crd_next; ++ } ++ } else if (cse->info.authsize) { ++ crda = crp->crp_desc; ++ } else if (cse->info.blocksize) { ++ crde = crp->crp_desc; ++ } else { ++ dprintk("%s: bad request\n", __FUNCTION__); ++ error = EINVAL; ++ goto bail; ++ } ++ ++ if ((error = copy_from_user(cse->uio.uio_iov[0].iov_base, cop->src, ++ cop->len))) { ++ dprintk("%s: bad copy\n", __FUNCTION__); ++ goto bail; ++ } ++ ++ if (crda) { ++ crda->crd_skip = 0; ++ crda->crd_len = cop->len; ++ crda->crd_inject = cop->len; ++ ++ crda->crd_alg = cse->mac; ++ crda->crd_key = cse->mackey; ++ crda->crd_klen = cse->mackeylen * 8; ++ } ++ ++ if (crde) { ++ if (cop->op == COP_ENCRYPT) ++ crde->crd_flags |= CRD_F_ENCRYPT; ++ else ++ crde->crd_flags &= ~CRD_F_ENCRYPT; ++ crde->crd_len = cop->len; ++ crde->crd_inject = 0; ++ ++ crde->crd_alg = cse->cipher; ++ crde->crd_key = cse->key; ++ crde->crd_klen = cse->keylen * 8; ++ } ++ ++ crp->crp_ilen = cse->uio.uio_iov[0].iov_len; ++ crp->crp_flags = CRYPTO_F_IOV | CRYPTO_F_CBIMM ++ | (cop->flags & COP_F_BATCH); ++ crp->crp_buf = (caddr_t)&cse->uio; ++ crp->crp_callback = (int (*) (struct cryptop *)) cryptodev_cb; ++ crp->crp_sid = cse->sid; ++ crp->crp_opaque = (void *)cse; ++ ++ if (cop->iv) { ++ if (crde == NULL) { ++ error = EINVAL; ++ dprintk("%s no crde\n", __FUNCTION__); ++ goto bail; ++ } ++ if (cse->cipher == CRYPTO_ARC4) { /* XXX use flag? */ ++ error = EINVAL; ++ dprintk("%s arc4 with IV\n", __FUNCTION__); ++ goto bail; ++ } ++ if ((error = copy_from_user(cse->tmp_iv, cop->iv, ++ cse->info.blocksize))) { ++ dprintk("%s bad iv copy\n", __FUNCTION__); ++ goto bail; ++ } ++ memcpy(crde->crd_iv, cse->tmp_iv, cse->info.blocksize); ++ crde->crd_flags |= CRD_F_IV_EXPLICIT | CRD_F_IV_PRESENT; ++ crde->crd_skip = 0; ++ } else if (cse->cipher == CRYPTO_ARC4) { /* XXX use flag? */ ++ crde->crd_skip = 0; ++ } else if (crde) { ++ crde->crd_flags |= CRD_F_IV_PRESENT; ++ crde->crd_skip = cse->info.blocksize; ++ crde->crd_len -= cse->info.blocksize; ++ } ++ ++ if (cop->mac && crda == NULL) { ++ error = EINVAL; ++ dprintk("%s no crda\n", __FUNCTION__); ++ goto bail; ++ } ++ ++ /* ++ * Let the dispatch run unlocked, then, interlock against the ++ * callback before checking if the operation completed and going ++ * to sleep. This insures drivers don't inherit our lock which ++ * results in a lock order reversal between crypto_dispatch forced ++ * entry and the crypto_done callback into us. ++ */ ++ error = crypto_dispatch(crp); ++ if (error) { ++ dprintk("%s error in crypto_dispatch\n", __FUNCTION__); ++ goto bail; ++ } ++ ++ dprintk("%s about to WAIT\n", __FUNCTION__); ++ /* ++ * we really need to wait for driver to complete to maintain ++ * state, luckily interrupts will be remembered ++ */ ++ do { ++ error = wait_event_interruptible(crp->crp_waitq, ++ ((crp->crp_flags & CRYPTO_F_DONE) != 0)); ++ /* ++ * we can't break out of this loop or we will leave behind ++ * a huge mess, however, staying here means if your driver ++ * is broken user applications can hang and not be killed. ++ * The solution, fix your driver :-) ++ */ ++ if (error) { ++ schedule(); ++ error = 0; ++ } ++ } while ((crp->crp_flags & CRYPTO_F_DONE) == 0); ++ dprintk("%s finished WAITING error=%d\n", __FUNCTION__, error); ++ ++ if (crp->crp_etype != 0) { ++ error = crp->crp_etype; ++ dprintk("%s error in crp processing\n", __FUNCTION__); ++ goto bail; ++ } ++ ++ if (cse->error) { ++ error = cse->error; ++ dprintk("%s error in cse processing\n", __FUNCTION__); ++ goto bail; ++ } ++ ++ if (cop->dst && (error = copy_to_user(cop->dst, ++ cse->uio.uio_iov[0].iov_base, cop->len))) { ++ dprintk("%s bad dst copy\n", __FUNCTION__); ++ goto bail; ++ } ++ ++ if (cop->mac && ++ (error=copy_to_user(cop->mac, ++ (caddr_t)cse->uio.uio_iov[0].iov_base + cop->len, ++ cse->info.authsize))) { ++ dprintk("%s bad mac copy\n", __FUNCTION__); ++ goto bail; ++ } ++ ++bail: ++ if (crp) ++ crypto_freereq(crp); ++ if (cse->uio.uio_iov[0].iov_base) ++ kfree(cse->uio.uio_iov[0].iov_base); ++ ++ return (error); ++} ++ ++static int ++cryptodev_cb(void *op) ++{ ++ struct cryptop *crp = (struct cryptop *) op; ++ struct csession *cse = (struct csession *)crp->crp_opaque; ++ int error; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ error = crp->crp_etype; ++ if (error == EAGAIN) { ++ crp->crp_flags &= ~CRYPTO_F_DONE; ++#ifdef NOTYET ++ /* ++ * DAVIDM I am fairly sure that we should turn this into a batch ++ * request to stop bad karma/lockup, revisit ++ */ ++ crp->crp_flags |= CRYPTO_F_BATCH; ++#endif ++ return crypto_dispatch(crp); ++ } ++ if (error != 0 || (crp->crp_flags & CRYPTO_F_DONE)) { ++ cse->error = error; ++ wake_up_interruptible(&crp->crp_waitq); ++ } ++ return (0); ++} ++ ++static int ++cryptodevkey_cb(void *op) ++{ ++ struct cryptkop *krp = (struct cryptkop *) op; ++ dprintk("%s()\n", __FUNCTION__); ++ wake_up_interruptible(&krp->krp_waitq); ++ return (0); ++} ++ ++static int ++cryptodev_key(struct crypt_kop *kop) ++{ ++ struct cryptkop *krp = NULL; ++ int error = EINVAL; ++ int in, out, size, i; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (kop->crk_iparams + kop->crk_oparams > CRK_MAXPARAM) { ++ dprintk("%s params too big\n", __FUNCTION__); ++ return (EFBIG); ++ } ++ ++ in = kop->crk_iparams; ++ out = kop->crk_oparams; ++ switch (kop->crk_op) { ++ case CRK_MOD_EXP: ++ if (in == 3 && out == 1) ++ break; ++ return (EINVAL); ++ case CRK_MOD_EXP_CRT: ++ if (in == 6 && out == 1) ++ break; ++ return (EINVAL); ++ case CRK_DSA_SIGN: ++ if (in == 5 && out == 2) ++ break; ++ return (EINVAL); ++ case CRK_DSA_VERIFY: ++ if (in == 7 && out == 0) ++ break; ++ return (EINVAL); ++ case CRK_DH_COMPUTE_KEY: ++ if (in == 3 && out == 1) ++ break; ++ return (EINVAL); ++ default: ++ return (EINVAL); ++ } ++ ++ krp = (struct cryptkop *)kmalloc(sizeof *krp, GFP_KERNEL); ++ if (!krp) ++ return (ENOMEM); ++ bzero(krp, sizeof *krp); ++ krp->krp_op = kop->crk_op; ++ krp->krp_status = kop->crk_status; ++ krp->krp_iparams = kop->crk_iparams; ++ krp->krp_oparams = kop->crk_oparams; ++ krp->krp_crid = kop->crk_crid; ++ krp->krp_status = 0; ++ krp->krp_flags = CRYPTO_KF_CBIMM; ++ krp->krp_callback = (int (*) (struct cryptkop *)) cryptodevkey_cb; ++ init_waitqueue_head(&krp->krp_waitq); ++ ++ for (i = 0; i < CRK_MAXPARAM; i++) ++ krp->krp_param[i].crp_nbits = kop->crk_param[i].crp_nbits; ++ for (i = 0; i < krp->krp_iparams + krp->krp_oparams; i++) { ++ size = (krp->krp_param[i].crp_nbits + 7) / 8; ++ if (size == 0) ++ continue; ++ krp->krp_param[i].crp_p = (caddr_t) kmalloc(size, GFP_KERNEL); ++ if (i >= krp->krp_iparams) ++ continue; ++ error = copy_from_user(krp->krp_param[i].crp_p, ++ kop->crk_param[i].crp_p, size); ++ if (error) ++ goto fail; ++ } ++ ++ error = crypto_kdispatch(krp); ++ if (error) ++ goto fail; ++ ++ do { ++ error = wait_event_interruptible(krp->krp_waitq, ++ ((krp->krp_flags & CRYPTO_KF_DONE) != 0)); ++ /* ++ * we can't break out of this loop or we will leave behind ++ * a huge mess, however, staying here means if your driver ++ * is broken user applications can hang and not be killed. ++ * The solution, fix your driver :-) ++ */ ++ if (error) { ++ schedule(); ++ error = 0; ++ } ++ } while ((krp->krp_flags & CRYPTO_KF_DONE) == 0); ++ ++ dprintk("%s finished WAITING error=%d\n", __FUNCTION__, error); ++ ++ kop->crk_crid = krp->krp_crid; /* device that did the work */ ++ if (krp->krp_status != 0) { ++ error = krp->krp_status; ++ goto fail; ++ } ++ ++ for (i = krp->krp_iparams; i < krp->krp_iparams + krp->krp_oparams; i++) { ++ size = (krp->krp_param[i].crp_nbits + 7) / 8; ++ if (size == 0) ++ continue; ++ error = copy_to_user(kop->crk_param[i].crp_p, krp->krp_param[i].crp_p, ++ size); ++ if (error) ++ goto fail; ++ } ++ ++fail: ++ if (krp) { ++ kop->crk_status = krp->krp_status; ++ for (i = 0; i < CRK_MAXPARAM; i++) { ++ if (krp->krp_param[i].crp_p) ++ kfree(krp->krp_param[i].crp_p); ++ } ++ kfree(krp); ++ } ++ return (error); ++} ++ ++static int ++cryptodev_find(struct crypt_find_op *find) ++{ ++ device_t dev; ++ ++ if (find->crid != -1) { ++ dev = crypto_find_device_byhid(find->crid); ++ if (dev == NULL) ++ return (ENOENT); ++ strlcpy(find->name, device_get_nameunit(dev), ++ sizeof(find->name)); ++ } else { ++ find->crid = crypto_find_driver(find->name); ++ if (find->crid == -1) ++ return (ENOENT); ++ } ++ return (0); ++} ++ ++static struct csession * ++csefind(struct fcrypt *fcr, u_int ses) ++{ ++ struct csession *cse; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ list_for_each_entry(cse, &fcr->csessions, list) ++ if (cse->ses == ses) ++ return (cse); ++ return (NULL); ++} ++ ++static int ++csedelete(struct fcrypt *fcr, struct csession *cse_del) ++{ ++ struct csession *cse; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ list_for_each_entry(cse, &fcr->csessions, list) { ++ if (cse == cse_del) { ++ list_del(&cse->list); ++ return (1); ++ } ++ } ++ return (0); ++} ++ ++static struct csession * ++cseadd(struct fcrypt *fcr, struct csession *cse) ++{ ++ dprintk("%s()\n", __FUNCTION__); ++ list_add_tail(&cse->list, &fcr->csessions); ++ cse->ses = fcr->sesn++; ++ return (cse); ++} ++ ++static struct csession * ++csecreate(struct fcrypt *fcr, u_int64_t sid, struct cryptoini *crie, ++ struct cryptoini *cria, struct csession_info *info) ++{ ++ struct csession *cse; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ cse = (struct csession *) kmalloc(sizeof(struct csession), GFP_KERNEL); ++ if (cse == NULL) ++ return NULL; ++ memset(cse, 0, sizeof(struct csession)); ++ ++ INIT_LIST_HEAD(&cse->list); ++ init_waitqueue_head(&cse->waitq); ++ ++ cse->key = crie->cri_key; ++ cse->keylen = crie->cri_klen/8; ++ cse->mackey = cria->cri_key; ++ cse->mackeylen = cria->cri_klen/8; ++ cse->sid = sid; ++ cse->cipher = crie->cri_alg; ++ cse->mac = cria->cri_alg; ++ cse->info = *info; ++ cseadd(fcr, cse); ++ return (cse); ++} ++ ++static int ++csefree(struct csession *cse) ++{ ++ int error; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ error = crypto_freesession(cse->sid); ++ if (cse->key) ++ kfree(cse->key); ++ if (cse->mackey) ++ kfree(cse->mackey); ++ kfree(cse); ++ return(error); ++} ++ ++static int ++cryptodev_ioctl( ++ struct inode *inode, ++ struct file *filp, ++ unsigned int cmd, ++ unsigned long arg) ++{ ++ struct cryptoini cria, crie; ++ struct fcrypt *fcr = filp->private_data; ++ struct csession *cse; ++ struct csession_info info; ++ struct session2_op sop; ++ struct crypt_op cop; ++ struct crypt_kop kop; ++ struct crypt_find_op fop; ++ u_int64_t sid; ++ u_int32_t ses = 0; ++ int feat, fd, error = 0, crid; ++ mm_segment_t fs; ++ ++ dprintk("%s(cmd=%x arg=%lx)\n", __FUNCTION__, cmd, arg); ++ ++ switch (cmd) { ++ ++ case CRIOGET: { ++ dprintk("%s(CRIOGET)\n", __FUNCTION__); ++ fs = get_fs(); ++ set_fs(get_ds()); ++ for (fd = 0; fd < files_fdtable(current->files)->max_fds; fd++) ++ if (files_fdtable(current->files)->fd[fd] == filp) ++ break; ++ fd = sys_dup(fd); ++ set_fs(fs); ++ put_user(fd, (int *) arg); ++ return IS_ERR_VALUE(fd) ? fd : 0; ++ } ++ ++#define CIOCGSESSSTR (cmd == CIOCGSESSION ? "CIOCGSESSION" : "CIOCGSESSION2") ++ case CIOCGSESSION: ++ case CIOCGSESSION2: ++ dprintk("%s(%s)\n", __FUNCTION__, CIOCGSESSSTR); ++ memset(&crie, 0, sizeof(crie)); ++ memset(&cria, 0, sizeof(cria)); ++ memset(&info, 0, sizeof(info)); ++ memset(&sop, 0, sizeof(sop)); ++ ++ if (copy_from_user(&sop, (void*)arg, (cmd == CIOCGSESSION) ? ++ sizeof(struct session_op) : sizeof(sop))) { ++ dprintk("%s(%s) - bad copy\n", __FUNCTION__, CIOCGSESSSTR); ++ error = EFAULT; ++ goto bail; ++ } ++ ++ switch (sop.cipher) { ++ case 0: ++ dprintk("%s(%s) - no cipher\n", __FUNCTION__, CIOCGSESSSTR); ++ break; ++ case CRYPTO_NULL_CBC: ++ info.blocksize = NULL_BLOCK_LEN; ++ info.minkey = NULL_MIN_KEY_LEN; ++ info.maxkey = NULL_MAX_KEY_LEN; ++ break; ++ case CRYPTO_DES_CBC: ++ info.blocksize = DES_BLOCK_LEN; ++ info.minkey = DES_MIN_KEY_LEN; ++ info.maxkey = DES_MAX_KEY_LEN; ++ break; ++ case CRYPTO_3DES_CBC: ++ info.blocksize = DES3_BLOCK_LEN; ++ info.minkey = DES3_MIN_KEY_LEN; ++ info.maxkey = DES3_MAX_KEY_LEN; ++ break; ++ case CRYPTO_BLF_CBC: ++ info.blocksize = BLOWFISH_BLOCK_LEN; ++ info.minkey = BLOWFISH_MIN_KEY_LEN; ++ info.maxkey = BLOWFISH_MAX_KEY_LEN; ++ break; ++ case CRYPTO_CAST_CBC: ++ info.blocksize = CAST128_BLOCK_LEN; ++ info.minkey = CAST128_MIN_KEY_LEN; ++ info.maxkey = CAST128_MAX_KEY_LEN; ++ break; ++ case CRYPTO_SKIPJACK_CBC: ++ info.blocksize = SKIPJACK_BLOCK_LEN; ++ info.minkey = SKIPJACK_MIN_KEY_LEN; ++ info.maxkey = SKIPJACK_MAX_KEY_LEN; ++ break; ++ case CRYPTO_AES_CBC: ++ info.blocksize = AES_BLOCK_LEN; ++ info.minkey = AES_MIN_KEY_LEN; ++ info.maxkey = AES_MAX_KEY_LEN; ++ break; ++ case CRYPTO_ARC4: ++ info.blocksize = ARC4_BLOCK_LEN; ++ info.minkey = ARC4_MIN_KEY_LEN; ++ info.maxkey = ARC4_MAX_KEY_LEN; ++ break; ++ case CRYPTO_CAMELLIA_CBC: ++ info.blocksize = CAMELLIA_BLOCK_LEN; ++ info.minkey = CAMELLIA_MIN_KEY_LEN; ++ info.maxkey = CAMELLIA_MAX_KEY_LEN; ++ break; ++ default: ++ dprintk("%s(%s) - bad cipher\n", __FUNCTION__, CIOCGSESSSTR); ++ error = EINVAL; ++ goto bail; ++ } ++ ++ switch (sop.mac) { ++ case 0: ++ dprintk("%s(%s) - no mac\n", __FUNCTION__, CIOCGSESSSTR); ++ break; ++ case CRYPTO_NULL_HMAC: ++ info.authsize = NULL_HASH_LEN; ++ break; ++ case CRYPTO_MD5: ++ info.authsize = MD5_HASH_LEN; ++ break; ++ case CRYPTO_SHA1: ++ info.authsize = SHA1_HASH_LEN; ++ break; ++ case CRYPTO_SHA2_256: ++ info.authsize = SHA2_256_HASH_LEN; ++ break; ++ case CRYPTO_SHA2_384: ++ info.authsize = SHA2_384_HASH_LEN; ++ break; ++ case CRYPTO_SHA2_512: ++ info.authsize = SHA2_512_HASH_LEN; ++ break; ++ case CRYPTO_RIPEMD160: ++ info.authsize = RIPEMD160_HASH_LEN; ++ break; ++ case CRYPTO_MD5_HMAC: ++ info.authsize = MD5_HASH_LEN; ++ info.authkey = 16; ++ break; ++ case CRYPTO_SHA1_HMAC: ++ info.authsize = SHA1_HASH_LEN; ++ info.authkey = 20; ++ break; ++ case CRYPTO_SHA2_256_HMAC: ++ info.authsize = SHA2_256_HASH_LEN; ++ info.authkey = 32; ++ break; ++ case CRYPTO_SHA2_384_HMAC: ++ info.authsize = SHA2_384_HASH_LEN; ++ info.authkey = 48; ++ break; ++ case CRYPTO_SHA2_512_HMAC: ++ info.authsize = SHA2_512_HASH_LEN; ++ info.authkey = 64; ++ break; ++ case CRYPTO_RIPEMD160_HMAC: ++ info.authsize = RIPEMD160_HASH_LEN; ++ info.authkey = 20; ++ break; ++ default: ++ dprintk("%s(%s) - bad mac\n", __FUNCTION__, CIOCGSESSSTR); ++ error = EINVAL; ++ goto bail; ++ } ++ ++ if (info.blocksize) { ++ crie.cri_alg = sop.cipher; ++ crie.cri_klen = sop.keylen * 8; ++ if ((info.maxkey && sop.keylen > info.maxkey) || ++ sop.keylen < info.minkey) { ++ dprintk("%s(%s) - bad key\n", __FUNCTION__, CIOCGSESSSTR); ++ error = EINVAL; ++ goto bail; ++ } ++ ++ crie.cri_key = (u_int8_t *) kmalloc(crie.cri_klen/8+1, GFP_KERNEL); ++ if (copy_from_user(crie.cri_key, sop.key, ++ crie.cri_klen/8)) { ++ dprintk("%s(%s) - bad copy\n", __FUNCTION__, CIOCGSESSSTR); ++ error = EFAULT; ++ goto bail; ++ } ++ if (info.authsize) ++ crie.cri_next = &cria; ++ } ++ ++ if (info.authsize) { ++ cria.cri_alg = sop.mac; ++ cria.cri_klen = sop.mackeylen * 8; ++ if (info.authkey && sop.mackeylen != info.authkey) { ++ dprintk("%s(%s) - mackeylen %d != %d\n", __FUNCTION__, ++ CIOCGSESSSTR, sop.mackeylen, info.authkey); ++ error = EINVAL; ++ goto bail; ++ } ++ ++ if (cria.cri_klen) { ++ cria.cri_key = (u_int8_t *) kmalloc(cria.cri_klen/8,GFP_KERNEL); ++ if (copy_from_user(cria.cri_key, sop.mackey, ++ cria.cri_klen / 8)) { ++ dprintk("%s(%s) - bad copy\n", __FUNCTION__, CIOCGSESSSTR); ++ error = EFAULT; ++ goto bail; ++ } ++ } ++ } ++ ++ /* NB: CIOGSESSION2 has the crid */ ++ if (cmd == CIOCGSESSION2) { ++ crid = sop.crid; ++ error = checkcrid(crid); ++ if (error) { ++ dprintk("%s(%s) - checkcrid %x\n", __FUNCTION__, ++ CIOCGSESSSTR, error); ++ goto bail; ++ } ++ } else { ++ /* allow either HW or SW to be used */ ++ crid = CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE; ++ } ++ error = crypto_newsession(&sid, (info.blocksize ? &crie : &cria), crid); ++ if (error) { ++ dprintk("%s(%s) - newsession %d\n",__FUNCTION__,CIOCGSESSSTR,error); ++ goto bail; ++ } ++ ++ cse = csecreate(fcr, sid, &crie, &cria, &info); ++ if (cse == NULL) { ++ crypto_freesession(sid); ++ error = EINVAL; ++ dprintk("%s(%s) - csecreate failed\n", __FUNCTION__, CIOCGSESSSTR); ++ goto bail; ++ } ++ sop.ses = cse->ses; ++ ++ if (cmd == CIOCGSESSION2) { ++ /* return hardware/driver id */ ++ sop.crid = CRYPTO_SESID2HID(cse->sid); ++ } ++ ++ if (copy_to_user((void*)arg, &sop, (cmd == CIOCGSESSION) ? ++ sizeof(struct session_op) : sizeof(sop))) { ++ dprintk("%s(%s) - bad copy\n", __FUNCTION__, CIOCGSESSSTR); ++ error = EFAULT; ++ } ++bail: ++ if (error) { ++ dprintk("%s(%s) - bail %d\n", __FUNCTION__, CIOCGSESSSTR, error); ++ if (crie.cri_key) ++ kfree(crie.cri_key); ++ if (cria.cri_key) ++ kfree(cria.cri_key); ++ } ++ break; ++ case CIOCFSESSION: ++ dprintk("%s(CIOCFSESSION)\n", __FUNCTION__); ++ get_user(ses, (uint32_t*)arg); ++ cse = csefind(fcr, ses); ++ if (cse == NULL) { ++ error = EINVAL; ++ dprintk("%s(CIOCFSESSION) - Fail %d\n", __FUNCTION__, error); ++ break; ++ } ++ csedelete(fcr, cse); ++ error = csefree(cse); ++ break; ++ case CIOCCRYPT: ++ dprintk("%s(CIOCCRYPT)\n", __FUNCTION__); ++ if(copy_from_user(&cop, (void*)arg, sizeof(cop))) { ++ dprintk("%s(CIOCCRYPT) - bad copy\n", __FUNCTION__); ++ error = EFAULT; ++ goto bail; ++ } ++ cse = csefind(fcr, cop.ses); ++ if (cse == NULL) { ++ error = EINVAL; ++ dprintk("%s(CIOCCRYPT) - Fail %d\n", __FUNCTION__, error); ++ break; ++ } ++ error = cryptodev_op(cse, &cop); ++ if(copy_to_user((void*)arg, &cop, sizeof(cop))) { ++ dprintk("%s(CIOCCRYPT) - bad return copy\n", __FUNCTION__); ++ error = EFAULT; ++ goto bail; ++ } ++ break; ++ case CIOCKEY: ++ case CIOCKEY2: ++ dprintk("%s(CIOCKEY)\n", __FUNCTION__); ++ if (!crypto_userasymcrypto) ++ return (EPERM); /* XXX compat? */ ++ if(copy_from_user(&kop, (void*)arg, sizeof(kop))) { ++ dprintk("%s(CIOCKEY) - bad copy\n", __FUNCTION__); ++ error = EFAULT; ++ goto bail; ++ } ++ if (cmd == CIOCKEY) { ++ /* NB: crypto core enforces s/w driver use */ ++ kop.crk_crid = ++ CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE; ++ } ++ error = cryptodev_key(&kop); ++ if(copy_to_user((void*)arg, &kop, sizeof(kop))) { ++ dprintk("%s(CIOCGKEY) - bad return copy\n", __FUNCTION__); ++ error = EFAULT; ++ goto bail; ++ } ++ break; ++ case CIOCASYMFEAT: ++ dprintk("%s(CIOCASYMFEAT)\n", __FUNCTION__); ++ if (!crypto_userasymcrypto) { ++ /* ++ * NB: if user asym crypto operations are ++ * not permitted return "no algorithms" ++ * so well-behaved applications will just ++ * fallback to doing them in software. ++ */ ++ feat = 0; ++ } else ++ error = crypto_getfeat(&feat); ++ if (!error) { ++ error = copy_to_user((void*)arg, &feat, sizeof(feat)); ++ } ++ break; ++ case CIOCFINDDEV: ++ if (copy_from_user(&fop, (void*)arg, sizeof(fop))) { ++ dprintk("%s(CIOCFINDDEV) - bad copy\n", __FUNCTION__); ++ error = EFAULT; ++ goto bail; ++ } ++ error = cryptodev_find(&fop); ++ if (copy_to_user((void*)arg, &fop, sizeof(fop))) { ++ dprintk("%s(CIOCFINDDEV) - bad return copy\n", __FUNCTION__); ++ error = EFAULT; ++ goto bail; ++ } ++ break; ++ default: ++ dprintk("%s(unknown ioctl 0x%x)\n", __FUNCTION__, cmd); ++ error = EINVAL; ++ break; ++ } ++ return(-error); ++} ++ ++#ifdef HAVE_UNLOCKED_IOCTL ++static long ++cryptodev_unlocked_ioctl( ++ struct file *filp, ++ unsigned int cmd, ++ unsigned long arg) ++{ ++ return cryptodev_ioctl(NULL, filp, cmd, arg); ++} ++#endif ++ ++static int ++cryptodev_open(struct inode *inode, struct file *filp) ++{ ++ struct fcrypt *fcr; ++ ++ dprintk("%s()\n", __FUNCTION__); ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35) ++ /* ++ * on 2.6.35 private_data points to a miscdevice structure, we override ++ * it, which is currently safe to do. ++ */ ++ if (filp->private_data) { ++ printk("cryptodev: Private data already exists - %p!\n", filp->private_data); ++ return(-ENODEV); ++ } ++#endif ++ ++ fcr = kmalloc(sizeof(*fcr), GFP_KERNEL); ++ if (!fcr) { ++ dprintk("%s() - malloc failed\n", __FUNCTION__); ++ return(-ENOMEM); ++ } ++ memset(fcr, 0, sizeof(*fcr)); ++ ++ INIT_LIST_HEAD(&fcr->csessions); ++ filp->private_data = fcr; ++ return(0); ++} ++ ++static int ++cryptodev_release(struct inode *inode, struct file *filp) ++{ ++ struct fcrypt *fcr = filp->private_data; ++ struct csession *cse, *tmp; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (!filp) { ++ printk("cryptodev: No private data on release\n"); ++ return(0); ++ } ++ ++ list_for_each_entry_safe(cse, tmp, &fcr->csessions, list) { ++ list_del(&cse->list); ++ (void)csefree(cse); ++ } ++ filp->private_data = NULL; ++ kfree(fcr); ++ return(0); ++} ++ ++static struct file_operations cryptodev_fops = { ++ .owner = THIS_MODULE, ++ .open = cryptodev_open, ++ .release = cryptodev_release, ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36) ++ .ioctl = cryptodev_ioctl, ++#endif ++#ifdef HAVE_UNLOCKED_IOCTL ++ .unlocked_ioctl = cryptodev_unlocked_ioctl, ++#endif ++}; ++ ++static struct miscdevice cryptodev = { ++ .minor = CRYPTODEV_MINOR, ++ .name = "crypto", ++ .fops = &cryptodev_fops, ++}; ++ ++static int __init ++cryptodev_init(void) ++{ ++ int rc; ++ ++ dprintk("%s(%p)\n", __FUNCTION__, cryptodev_init); ++ rc = misc_register(&cryptodev); ++ if (rc) { ++ printk(KERN_ERR "cryptodev: registration of /dev/crypto failed\n"); ++ return(rc); ++ } ++ ++ return(0); ++} ++ ++static void __exit ++cryptodev_exit(void) ++{ ++ dprintk("%s()\n", __FUNCTION__); ++ misc_deregister(&cryptodev); ++} ++ ++module_init(cryptodev_init); ++module_exit(cryptodev_exit); ++ ++MODULE_LICENSE("BSD"); ++MODULE_AUTHOR("David McCullough "); ++MODULE_DESCRIPTION("Cryptodev (user interface to OCF)"); +diff -Nur linux-3.1.4.orig/crypto/ocf/cryptodev.h linux-3.1.4/crypto/ocf/cryptodev.h +--- linux-3.1.4.orig/crypto/ocf/cryptodev.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/cryptodev.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,480 @@ ++/* $FreeBSD: src/sys/opencrypto/cryptodev.h,v 1.25 2007/05/09 19:37:02 gnn Exp $ */ ++/* $OpenBSD: cryptodev.h,v 1.31 2002/06/11 11:14:29 beck Exp $ */ ++ ++/*- ++ * Linux port done by David McCullough ++ * Copyright (C) 2006-2010 David McCullough ++ * Copyright (C) 2004-2005 Intel Corporation. ++ * The license and original author are listed below. ++ * ++ * The author of this code is Angelos D. Keromytis (angelos@cis.upenn.edu) ++ * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting ++ * ++ * This code was written by Angelos D. Keromytis in Athens, Greece, in ++ * February 2000. Network Security Technologies Inc. (NSTI) kindly ++ * supported the development of this code. ++ * ++ * Copyright (c) 2000 Angelos D. Keromytis ++ * ++ * Permission to use, copy, and modify this software with or without fee ++ * is hereby granted, provided that this entire notice is included in ++ * all source code copies of any software which is or includes a copy or ++ * modification of this software. ++ * ++ * THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR ++ * IMPLIED WARRANTY. IN PARTICULAR, NONE OF THE AUTHORS MAKES ANY ++ * REPRESENTATION OR WARRANTY OF ANY KIND CONCERNING THE ++ * MERCHANTABILITY OF THIS SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR ++ * PURPOSE. ++ * ++ * Copyright (c) 2001 Theo de Raadt ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored in part by the Defense Advanced Research Projects ++ * Agency (DARPA) and Air Force Research Laboratory, Air Force ++ * Materiel Command, USAF, under agreement number F30602-01-2-0537. ++ * ++ */ ++ ++#ifndef _CRYPTO_CRYPTO_H_ ++#define _CRYPTO_CRYPTO_H_ ++ ++/* Some initial values */ ++#define CRYPTO_DRIVERS_INITIAL 4 ++#define CRYPTO_SW_SESSIONS 32 ++ ++/* Hash values */ ++#define NULL_HASH_LEN 0 ++#define MD5_HASH_LEN 16 ++#define SHA1_HASH_LEN 20 ++#define RIPEMD160_HASH_LEN 20 ++#define SHA2_256_HASH_LEN 32 ++#define SHA2_384_HASH_LEN 48 ++#define SHA2_512_HASH_LEN 64 ++#define MD5_KPDK_HASH_LEN 16 ++#define SHA1_KPDK_HASH_LEN 20 ++/* Maximum hash algorithm result length */ ++#define HASH_MAX_LEN SHA2_512_HASH_LEN /* Keep this updated */ ++ ++/* HMAC values */ ++#define NULL_HMAC_BLOCK_LEN 1 ++#define MD5_HMAC_BLOCK_LEN 64 ++#define SHA1_HMAC_BLOCK_LEN 64 ++#define RIPEMD160_HMAC_BLOCK_LEN 64 ++#define SHA2_256_HMAC_BLOCK_LEN 64 ++#define SHA2_384_HMAC_BLOCK_LEN 128 ++#define SHA2_512_HMAC_BLOCK_LEN 128 ++/* Maximum HMAC block length */ ++#define HMAC_MAX_BLOCK_LEN SHA2_512_HMAC_BLOCK_LEN /* Keep this updated */ ++#define HMAC_IPAD_VAL 0x36 ++#define HMAC_OPAD_VAL 0x5C ++ ++/* Encryption algorithm block sizes */ ++#define NULL_BLOCK_LEN 1 ++#define DES_BLOCK_LEN 8 ++#define DES3_BLOCK_LEN 8 ++#define BLOWFISH_BLOCK_LEN 8 ++#define SKIPJACK_BLOCK_LEN 8 ++#define CAST128_BLOCK_LEN 8 ++#define RIJNDAEL128_BLOCK_LEN 16 ++#define AES_BLOCK_LEN RIJNDAEL128_BLOCK_LEN ++#define CAMELLIA_BLOCK_LEN 16 ++#define ARC4_BLOCK_LEN 1 ++#define EALG_MAX_BLOCK_LEN AES_BLOCK_LEN /* Keep this updated */ ++ ++/* Encryption algorithm min and max key sizes */ ++#define NULL_MIN_KEY_LEN 0 ++#define NULL_MAX_KEY_LEN 0 ++#define DES_MIN_KEY_LEN 8 ++#define DES_MAX_KEY_LEN 8 ++#define DES3_MIN_KEY_LEN 24 ++#define DES3_MAX_KEY_LEN 24 ++#define BLOWFISH_MIN_KEY_LEN 4 ++#define BLOWFISH_MAX_KEY_LEN 56 ++#define SKIPJACK_MIN_KEY_LEN 10 ++#define SKIPJACK_MAX_KEY_LEN 10 ++#define CAST128_MIN_KEY_LEN 5 ++#define CAST128_MAX_KEY_LEN 16 ++#define RIJNDAEL128_MIN_KEY_LEN 16 ++#define RIJNDAEL128_MAX_KEY_LEN 32 ++#define AES_MIN_KEY_LEN RIJNDAEL128_MIN_KEY_LEN ++#define AES_MAX_KEY_LEN RIJNDAEL128_MAX_KEY_LEN ++#define CAMELLIA_MIN_KEY_LEN 16 ++#define CAMELLIA_MAX_KEY_LEN 32 ++#define ARC4_MIN_KEY_LEN 1 ++#define ARC4_MAX_KEY_LEN 256 ++ ++/* Max size of data that can be processed */ ++#define CRYPTO_MAX_DATA_LEN 64*1024 - 1 ++ ++#define CRYPTO_ALGORITHM_MIN 1 ++#define CRYPTO_DES_CBC 1 ++#define CRYPTO_3DES_CBC 2 ++#define CRYPTO_BLF_CBC 3 ++#define CRYPTO_CAST_CBC 4 ++#define CRYPTO_SKIPJACK_CBC 5 ++#define CRYPTO_MD5_HMAC 6 ++#define CRYPTO_SHA1_HMAC 7 ++#define CRYPTO_RIPEMD160_HMAC 8 ++#define CRYPTO_MD5_KPDK 9 ++#define CRYPTO_SHA1_KPDK 10 ++#define CRYPTO_RIJNDAEL128_CBC 11 /* 128 bit blocksize */ ++#define CRYPTO_AES_CBC 11 /* 128 bit blocksize -- the same as above */ ++#define CRYPTO_ARC4 12 ++#define CRYPTO_MD5 13 ++#define CRYPTO_SHA1 14 ++#define CRYPTO_NULL_HMAC 15 ++#define CRYPTO_NULL_CBC 16 ++#define CRYPTO_DEFLATE_COMP 17 /* Deflate compression algorithm */ ++#define CRYPTO_SHA2_256_HMAC 18 ++#define CRYPTO_SHA2_384_HMAC 19 ++#define CRYPTO_SHA2_512_HMAC 20 ++#define CRYPTO_CAMELLIA_CBC 21 ++#define CRYPTO_SHA2_256 22 ++#define CRYPTO_SHA2_384 23 ++#define CRYPTO_SHA2_512 24 ++#define CRYPTO_RIPEMD160 25 ++#define CRYPTO_LZS_COMP 26 ++#define CRYPTO_ALGORITHM_MAX 26 /* Keep updated - see above */ ++ ++/* Algorithm flags */ ++#define CRYPTO_ALG_FLAG_SUPPORTED 0x01 /* Algorithm is supported */ ++#define CRYPTO_ALG_FLAG_RNG_ENABLE 0x02 /* Has HW RNG for DH/DSA */ ++#define CRYPTO_ALG_FLAG_DSA_SHA 0x04 /* Can do SHA on msg */ ++ ++/* ++ * Crypto driver/device flags. They can set in the crid ++ * parameter when creating a session or submitting a key ++ * op to affect the device/driver assigned. If neither ++ * of these are specified then the crid is assumed to hold ++ * the driver id of an existing (and suitable) device that ++ * must be used to satisfy the request. ++ */ ++#define CRYPTO_FLAG_HARDWARE 0x01000000 /* hardware accelerated */ ++#define CRYPTO_FLAG_SOFTWARE 0x02000000 /* software implementation */ ++ ++/* NB: deprecated */ ++struct session_op { ++ u_int32_t cipher; /* ie. CRYPTO_DES_CBC */ ++ u_int32_t mac; /* ie. CRYPTO_MD5_HMAC */ ++ ++ u_int32_t keylen; /* cipher key */ ++ caddr_t key; ++ int mackeylen; /* mac key */ ++ caddr_t mackey; ++ ++ u_int32_t ses; /* returns: session # */ ++}; ++ ++struct session2_op { ++ u_int32_t cipher; /* ie. CRYPTO_DES_CBC */ ++ u_int32_t mac; /* ie. CRYPTO_MD5_HMAC */ ++ ++ u_int32_t keylen; /* cipher key */ ++ caddr_t key; ++ int mackeylen; /* mac key */ ++ caddr_t mackey; ++ ++ u_int32_t ses; /* returns: session # */ ++ int crid; /* driver id + flags (rw) */ ++ int pad[4]; /* for future expansion */ ++}; ++ ++struct crypt_op { ++ u_int32_t ses; ++ u_int16_t op; /* i.e. COP_ENCRYPT */ ++#define COP_NONE 0 ++#define COP_ENCRYPT 1 ++#define COP_DECRYPT 2 ++ u_int16_t flags; ++#define COP_F_BATCH 0x0008 /* Batch op if possible */ ++ u_int len; ++ caddr_t src, dst; /* become iov[] inside kernel */ ++ caddr_t mac; /* must be big enough for chosen MAC */ ++ caddr_t iv; ++}; ++ ++/* ++ * Parameters for looking up a crypto driver/device by ++ * device name or by id. The latter are returned for ++ * created sessions (crid) and completed key operations. ++ */ ++struct crypt_find_op { ++ int crid; /* driver id + flags */ ++ char name[32]; /* device/driver name */ ++}; ++ ++/* bignum parameter, in packed bytes, ... */ ++struct crparam { ++ caddr_t crp_p; ++ u_int crp_nbits; ++}; ++ ++#define CRK_MAXPARAM 8 ++ ++struct crypt_kop { ++ u_int crk_op; /* ie. CRK_MOD_EXP or other */ ++ u_int crk_status; /* return status */ ++ u_short crk_iparams; /* # of input parameters */ ++ u_short crk_oparams; /* # of output parameters */ ++ u_int crk_crid; /* NB: only used by CIOCKEY2 (rw) */ ++ struct crparam crk_param[CRK_MAXPARAM]; ++}; ++#define CRK_ALGORITM_MIN 0 ++#define CRK_MOD_EXP 0 ++#define CRK_MOD_EXP_CRT 1 ++#define CRK_DSA_SIGN 2 ++#define CRK_DSA_VERIFY 3 ++#define CRK_DH_COMPUTE_KEY 4 ++#define CRK_ALGORITHM_MAX 4 /* Keep updated - see below */ ++ ++#define CRF_MOD_EXP (1 << CRK_MOD_EXP) ++#define CRF_MOD_EXP_CRT (1 << CRK_MOD_EXP_CRT) ++#define CRF_DSA_SIGN (1 << CRK_DSA_SIGN) ++#define CRF_DSA_VERIFY (1 << CRK_DSA_VERIFY) ++#define CRF_DH_COMPUTE_KEY (1 << CRK_DH_COMPUTE_KEY) ++ ++/* ++ * done against open of /dev/crypto, to get a cloned descriptor. ++ * Please use F_SETFD against the cloned descriptor. ++ */ ++#define CRIOGET _IOWR('c', 100, u_int32_t) ++#define CRIOASYMFEAT CIOCASYMFEAT ++#define CRIOFINDDEV CIOCFINDDEV ++ ++/* the following are done against the cloned descriptor */ ++#define CIOCGSESSION _IOWR('c', 101, struct session_op) ++#define CIOCFSESSION _IOW('c', 102, u_int32_t) ++#define CIOCCRYPT _IOWR('c', 103, struct crypt_op) ++#define CIOCKEY _IOWR('c', 104, struct crypt_kop) ++#define CIOCASYMFEAT _IOR('c', 105, u_int32_t) ++#define CIOCGSESSION2 _IOWR('c', 106, struct session2_op) ++#define CIOCKEY2 _IOWR('c', 107, struct crypt_kop) ++#define CIOCFINDDEV _IOWR('c', 108, struct crypt_find_op) ++ ++struct cryptotstat { ++ struct timespec acc; /* total accumulated time */ ++ struct timespec min; /* min time */ ++ struct timespec max; /* max time */ ++ u_int32_t count; /* number of observations */ ++}; ++ ++struct cryptostats { ++ u_int32_t cs_ops; /* symmetric crypto ops submitted */ ++ u_int32_t cs_errs; /* symmetric crypto ops that failed */ ++ u_int32_t cs_kops; /* asymetric/key ops submitted */ ++ u_int32_t cs_kerrs; /* asymetric/key ops that failed */ ++ u_int32_t cs_intrs; /* crypto swi thread activations */ ++ u_int32_t cs_rets; /* crypto return thread activations */ ++ u_int32_t cs_blocks; /* symmetric op driver block */ ++ u_int32_t cs_kblocks; /* symmetric op driver block */ ++ /* ++ * When CRYPTO_TIMING is defined at compile time and the ++ * sysctl debug.crypto is set to 1, the crypto system will ++ * accumulate statistics about how long it takes to process ++ * crypto requests at various points during processing. ++ */ ++ struct cryptotstat cs_invoke; /* crypto_dipsatch -> crypto_invoke */ ++ struct cryptotstat cs_done; /* crypto_invoke -> crypto_done */ ++ struct cryptotstat cs_cb; /* crypto_done -> callback */ ++ struct cryptotstat cs_finis; /* callback -> callback return */ ++ ++ u_int32_t cs_drops; /* crypto ops dropped due to congestion */ ++}; ++ ++#ifdef __KERNEL__ ++ ++/* Standard initialization structure beginning */ ++struct cryptoini { ++ int cri_alg; /* Algorithm to use */ ++ int cri_klen; /* Key length, in bits */ ++ int cri_mlen; /* Number of bytes we want from the ++ entire hash. 0 means all. */ ++ caddr_t cri_key; /* key to use */ ++ u_int8_t cri_iv[EALG_MAX_BLOCK_LEN]; /* IV to use */ ++ struct cryptoini *cri_next; ++}; ++ ++/* Describe boundaries of a single crypto operation */ ++struct cryptodesc { ++ int crd_skip; /* How many bytes to ignore from start */ ++ int crd_len; /* How many bytes to process */ ++ int crd_inject; /* Where to inject results, if applicable */ ++ int crd_flags; ++ ++#define CRD_F_ENCRYPT 0x01 /* Set when doing encryption */ ++#define CRD_F_IV_PRESENT 0x02 /* When encrypting, IV is already in ++ place, so don't copy. */ ++#define CRD_F_IV_EXPLICIT 0x04 /* IV explicitly provided */ ++#define CRD_F_DSA_SHA_NEEDED 0x08 /* Compute SHA-1 of buffer for DSA */ ++#define CRD_F_KEY_EXPLICIT 0x10 /* Key explicitly provided */ ++#define CRD_F_COMP 0x0f /* Set when doing compression */ ++ ++ struct cryptoini CRD_INI; /* Initialization/context data */ ++#define crd_iv CRD_INI.cri_iv ++#define crd_key CRD_INI.cri_key ++#define crd_alg CRD_INI.cri_alg ++#define crd_klen CRD_INI.cri_klen ++#define crd_mlen CRD_INI.cri_mlen ++ ++ struct cryptodesc *crd_next; ++}; ++ ++/* Structure describing complete operation */ ++struct cryptop { ++ struct list_head crp_next; ++ wait_queue_head_t crp_waitq; ++ ++ u_int64_t crp_sid; /* Session ID */ ++ int crp_ilen; /* Input data total length */ ++ int crp_olen; /* Result total length */ ++ ++ int crp_etype; /* ++ * Error type (zero means no error). ++ * All error codes except EAGAIN ++ * indicate possible data corruption (as in, ++ * the data have been touched). On all ++ * errors, the crp_sid may have changed ++ * (reset to a new one), so the caller ++ * should always check and use the new ++ * value on future requests. ++ */ ++ int crp_flags; ++ ++#define CRYPTO_F_SKBUF 0x0001 /* Input/output are skbuf chains */ ++#define CRYPTO_F_IOV 0x0002 /* Input/output are uio */ ++#define CRYPTO_F_REL 0x0004 /* Must return data in same place */ ++#define CRYPTO_F_BATCH 0x0008 /* Batch op if possible */ ++#define CRYPTO_F_CBIMM 0x0010 /* Do callback immediately */ ++#define CRYPTO_F_DONE 0x0020 /* Operation completed */ ++#define CRYPTO_F_CBIFSYNC 0x0040 /* Do CBIMM if op is synchronous */ ++ ++ caddr_t crp_buf; /* Data to be processed */ ++ caddr_t crp_opaque; /* Opaque pointer, passed along */ ++ struct cryptodesc *crp_desc; /* Linked list of processing descriptors */ ++ ++ int (*crp_callback)(struct cryptop *); /* Callback function */ ++}; ++ ++#define CRYPTO_BUF_CONTIG 0x0 ++#define CRYPTO_BUF_IOV 0x1 ++#define CRYPTO_BUF_SKBUF 0x2 ++ ++#define CRYPTO_OP_DECRYPT 0x0 ++#define CRYPTO_OP_ENCRYPT 0x1 ++ ++/* ++ * Hints passed to process methods. ++ */ ++#define CRYPTO_HINT_MORE 0x1 /* more ops coming shortly */ ++ ++struct cryptkop { ++ struct list_head krp_next; ++ wait_queue_head_t krp_waitq; ++ ++ int krp_flags; ++#define CRYPTO_KF_DONE 0x0001 /* Operation completed */ ++#define CRYPTO_KF_CBIMM 0x0002 /* Do callback immediately */ ++ ++ u_int krp_op; /* ie. CRK_MOD_EXP or other */ ++ u_int krp_status; /* return status */ ++ u_short krp_iparams; /* # of input parameters */ ++ u_short krp_oparams; /* # of output parameters */ ++ u_int krp_crid; /* desired device, etc. */ ++ u_int32_t krp_hid; ++ struct crparam krp_param[CRK_MAXPARAM]; /* kvm */ ++ int (*krp_callback)(struct cryptkop *); ++}; ++ ++#include ++ ++/* ++ * Session ids are 64 bits. The lower 32 bits contain a "local id" which ++ * is a driver-private session identifier. The upper 32 bits contain a ++ * "hardware id" used by the core crypto code to identify the driver and ++ * a copy of the driver's capabilities that can be used by client code to ++ * optimize operation. ++ */ ++#define CRYPTO_SESID2HID(_sid) (((_sid) >> 32) & 0x00ffffff) ++#define CRYPTO_SESID2CAPS(_sid) (((_sid) >> 32) & 0xff000000) ++#define CRYPTO_SESID2LID(_sid) (((u_int32_t) (_sid)) & 0xffffffff) ++ ++extern int crypto_newsession(u_int64_t *sid, struct cryptoini *cri, int hard); ++extern int crypto_freesession(u_int64_t sid); ++#define CRYPTOCAP_F_HARDWARE CRYPTO_FLAG_HARDWARE ++#define CRYPTOCAP_F_SOFTWARE CRYPTO_FLAG_SOFTWARE ++#define CRYPTOCAP_F_SYNC 0x04000000 /* operates synchronously */ ++extern int32_t crypto_get_driverid(device_t dev, int flags); ++extern int crypto_find_driver(const char *); ++extern device_t crypto_find_device_byhid(int hid); ++extern int crypto_getcaps(int hid); ++extern int crypto_register(u_int32_t driverid, int alg, u_int16_t maxoplen, ++ u_int32_t flags); ++extern int crypto_kregister(u_int32_t, int, u_int32_t); ++extern int crypto_unregister(u_int32_t driverid, int alg); ++extern int crypto_unregister_all(u_int32_t driverid); ++extern int crypto_dispatch(struct cryptop *crp); ++extern int crypto_kdispatch(struct cryptkop *); ++#define CRYPTO_SYMQ 0x1 ++#define CRYPTO_ASYMQ 0x2 ++extern int crypto_unblock(u_int32_t, int); ++extern void crypto_done(struct cryptop *crp); ++extern void crypto_kdone(struct cryptkop *); ++extern int crypto_getfeat(int *); ++ ++extern void crypto_freereq(struct cryptop *crp); ++extern struct cryptop *crypto_getreq(int num); ++ ++extern int crypto_usercrypto; /* userland may do crypto requests */ ++extern int crypto_userasymcrypto; /* userland may do asym crypto reqs */ ++extern int crypto_devallowsoft; /* only use hardware crypto */ ++ ++/* ++ * random number support, crypto_unregister_all will unregister ++ */ ++extern int crypto_rregister(u_int32_t driverid, ++ int (*read_random)(void *arg, u_int32_t *buf, int len), void *arg); ++extern int crypto_runregister_all(u_int32_t driverid); ++ ++/* ++ * Crypto-related utility routines used mainly by drivers. ++ * ++ * XXX these don't really belong here; but for now they're ++ * kept apart from the rest of the system. ++ */ ++struct uio; ++extern void cuio_copydata(struct uio* uio, int off, int len, caddr_t cp); ++extern void cuio_copyback(struct uio* uio, int off, int len, caddr_t cp); ++extern struct iovec *cuio_getptr(struct uio *uio, int loc, int *off); ++ ++extern void crypto_copyback(int flags, caddr_t buf, int off, int size, ++ caddr_t in); ++extern void crypto_copydata(int flags, caddr_t buf, int off, int size, ++ caddr_t out); ++extern int crypto_apply(int flags, caddr_t buf, int off, int len, ++ int (*f)(void *, void *, u_int), void *arg); ++ ++#endif /* __KERNEL__ */ ++#endif /* _CRYPTO_CRYPTO_H_ */ +diff -Nur linux-3.1.4.orig/crypto/ocf/cryptosoft.c linux-3.1.4/crypto/ocf/cryptosoft.c +--- linux-3.1.4.orig/crypto/ocf/cryptosoft.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/cryptosoft.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,1320 @@ ++/* ++ * An OCF module that uses the linux kernel cryptoapi, based on the ++ * original cryptosoft for BSD by Angelos D. Keromytis (angelos@cis.upenn.edu) ++ * but is mostly unrecognisable, ++ * ++ * Written by David McCullough ++ * Copyright (C) 2004-2011 David McCullough ++ * Copyright (C) 2004-2005 Intel Corporation. ++ * ++ * LICENSE TERMS ++ * ++ * The free distribution and use of this software in both source and binary ++ * form is allowed (with or without changes) provided that: ++ * ++ * 1. distributions of this source code include the above copyright ++ * notice, this list of conditions and the following disclaimer; ++ * ++ * 2. distributions in binary form include the above copyright ++ * notice, this list of conditions and the following disclaimer ++ * in the documentation and/or other associated materials; ++ * ++ * 3. the copyright holder's name is not used to endorse products ++ * built using this software without specific written permission. ++ * ++ * ALTERNATIVELY, provided that this notice is retained in full, this product ++ * may be distributed under the terms of the GNU General Public License (GPL), ++ * in which case the provisions of the GPL apply INSTEAD OF those given above. ++ * ++ * DISCLAIMER ++ * ++ * This software is provided 'as is' with no explicit or implied warranties ++ * in respect of its properties, including, but not limited to, correctness ++ * and/or fitness for purpose. ++ * --------------------------------------------------------------------------- ++ */ ++ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,10) ++#include ++#endif ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29) ++#include ++#endif ++ ++#include ++#include ++ ++struct { ++ softc_device_decl sc_dev; ++} swcr_softc; ++ ++#define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK) ++ ++#define SW_TYPE_CIPHER 0x01 ++#define SW_TYPE_HMAC 0x02 ++#define SW_TYPE_HASH 0x04 ++#define SW_TYPE_COMP 0x08 ++#define SW_TYPE_BLKCIPHER 0x10 ++#define SW_TYPE_ALG_MASK 0x1f ++ ++#define SW_TYPE_ASYNC 0x8000 ++ ++#define SW_TYPE_INUSE 0x10000000 ++ ++/* We change some of the above if we have an async interface */ ++ ++#define SW_TYPE_ALG_AMASK (SW_TYPE_ALG_MASK | SW_TYPE_ASYNC) ++ ++#define SW_TYPE_ABLKCIPHER (SW_TYPE_BLKCIPHER | SW_TYPE_ASYNC) ++#define SW_TYPE_AHASH (SW_TYPE_HASH | SW_TYPE_ASYNC) ++#define SW_TYPE_AHMAC (SW_TYPE_HMAC | SW_TYPE_ASYNC) ++ ++#define SCATTERLIST_MAX 16 ++ ++struct swcr_data { ++ struct work_struct workq; ++ int sw_type; ++ int sw_alg; ++ struct crypto_tfm *sw_tfm; ++ spinlock_t sw_tfm_lock; ++ union { ++ struct { ++ char *sw_key; ++ int sw_klen; ++ int sw_mlen; ++ } hmac; ++ void *sw_comp_buf; ++ } u; ++ struct swcr_data *sw_next; ++}; ++ ++struct swcr_req { ++ struct swcr_data *sw_head; ++ struct swcr_data *sw; ++ struct cryptop *crp; ++ struct cryptodesc *crd; ++ struct scatterlist sg[SCATTERLIST_MAX]; ++ unsigned char iv[EALG_MAX_BLOCK_LEN]; ++ char result[HASH_MAX_LEN]; ++ void *crypto_req; ++}; ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) ++static kmem_cache_t *swcr_req_cache; ++#else ++static struct kmem_cache *swcr_req_cache; ++#endif ++ ++#ifndef CRYPTO_TFM_MODE_CBC ++/* ++ * As of linux-2.6.21 this is no longer defined, and presumably no longer ++ * needed to be passed into the crypto core code. ++ */ ++#define CRYPTO_TFM_MODE_CBC 0 ++#define CRYPTO_TFM_MODE_ECB 0 ++#endif ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) ++ /* ++ * Linux 2.6.19 introduced a new Crypto API, setup macro's to convert new ++ * API into old API. ++ */ ++ ++ /* Symmetric/Block Cipher */ ++ struct blkcipher_desc ++ { ++ struct crypto_tfm *tfm; ++ void *info; ++ }; ++ #define ecb(X) #X , CRYPTO_TFM_MODE_ECB ++ #define cbc(X) #X , CRYPTO_TFM_MODE_CBC ++ #define crypto_has_blkcipher(X, Y, Z) crypto_alg_available(X, 0) ++ #define crypto_blkcipher_cast(X) X ++ #define crypto_blkcipher_tfm(X) X ++ #define crypto_alloc_blkcipher(X, Y, Z) crypto_alloc_tfm(X, mode) ++ #define crypto_blkcipher_ivsize(X) crypto_tfm_alg_ivsize(X) ++ #define crypto_blkcipher_blocksize(X) crypto_tfm_alg_blocksize(X) ++ #define crypto_blkcipher_setkey(X, Y, Z) crypto_cipher_setkey(X, Y, Z) ++ #define crypto_blkcipher_encrypt_iv(W, X, Y, Z) \ ++ crypto_cipher_encrypt_iv((W)->tfm, X, Y, Z, (u8 *)((W)->info)) ++ #define crypto_blkcipher_decrypt_iv(W, X, Y, Z) \ ++ crypto_cipher_decrypt_iv((W)->tfm, X, Y, Z, (u8 *)((W)->info)) ++ #define crypto_blkcipher_set_flags(x, y) /* nop */ ++ #define crypto_free_blkcipher(x) crypto_free_tfm(x) ++ #define crypto_free_comp crypto_free_tfm ++ #define crypto_free_hash crypto_free_tfm ++ ++ /* Hash/HMAC/Digest */ ++ struct hash_desc ++ { ++ struct crypto_tfm *tfm; ++ }; ++ #define hmac(X) #X , 0 ++ #define crypto_has_hash(X, Y, Z) crypto_alg_available(X, 0) ++ #define crypto_hash_cast(X) X ++ #define crypto_hash_tfm(X) X ++ #define crypto_alloc_hash(X, Y, Z) crypto_alloc_tfm(X, mode) ++ #define crypto_hash_digestsize(X) crypto_tfm_alg_digestsize(X) ++ #define crypto_hash_digest(W, X, Y, Z) \ ++ crypto_digest_digest((W)->tfm, X, sg_num, Z) ++ ++ /* Asymmetric Cipher */ ++ #define crypto_has_cipher(X, Y, Z) crypto_alg_available(X, 0) ++ ++ /* Compression */ ++ #define crypto_has_comp(X, Y, Z) crypto_alg_available(X, 0) ++ #define crypto_comp_tfm(X) X ++ #define crypto_comp_cast(X) X ++ #define crypto_alloc_comp(X, Y, Z) crypto_alloc_tfm(X, mode) ++ #define plain(X) #X , 0 ++#else ++ #define ecb(X) "ecb(" #X ")" , 0 ++ #define cbc(X) "cbc(" #X ")" , 0 ++ #define hmac(X) "hmac(" #X ")" , 0 ++ #define plain(X) #X , 0 ++#endif /* if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) */ ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22) ++/* no ablkcipher in older kernels */ ++#define crypto_alloc_ablkcipher(a,b,c) (NULL) ++#define crypto_ablkcipher_tfm(x) ((struct crypto_tfm *)(x)) ++#define crypto_ablkcipher_set_flags(a, b) /* nop */ ++#define crypto_ablkcipher_setkey(x, y, z) (-EINVAL) ++#define crypto_has_ablkcipher(a,b,c) (0) ++#else ++#define HAVE_ABLKCIPHER ++#endif ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,32) ++/* no ahash in older kernels */ ++#define crypto_ahash_tfm(x) ((struct crypto_tfm *)(x)) ++#define crypto_alloc_ahash(a,b,c) (NULL) ++#define crypto_ahash_digestsize(x) 0 ++#else ++#define HAVE_AHASH ++#endif ++ ++struct crypto_details { ++ char *alg_name; ++ int mode; ++ int sw_type; ++}; ++ ++static struct crypto_details crypto_details[] = { ++ [CRYPTO_DES_CBC] = { cbc(des), SW_TYPE_BLKCIPHER, }, ++ [CRYPTO_3DES_CBC] = { cbc(des3_ede), SW_TYPE_BLKCIPHER, }, ++ [CRYPTO_BLF_CBC] = { cbc(blowfish), SW_TYPE_BLKCIPHER, }, ++ [CRYPTO_CAST_CBC] = { cbc(cast5), SW_TYPE_BLKCIPHER, }, ++ [CRYPTO_SKIPJACK_CBC] = { cbc(skipjack), SW_TYPE_BLKCIPHER, }, ++ [CRYPTO_MD5_HMAC] = { hmac(md5), SW_TYPE_HMAC, }, ++ [CRYPTO_SHA1_HMAC] = { hmac(sha1), SW_TYPE_HMAC, }, ++ [CRYPTO_RIPEMD160_HMAC] = { hmac(ripemd160), SW_TYPE_HMAC, }, ++ [CRYPTO_MD5_KPDK] = { plain(md5-kpdk), SW_TYPE_HASH, }, ++ [CRYPTO_SHA1_KPDK] = { plain(sha1-kpdk), SW_TYPE_HASH, }, ++ [CRYPTO_AES_CBC] = { cbc(aes), SW_TYPE_BLKCIPHER, }, ++ [CRYPTO_ARC4] = { ecb(arc4), SW_TYPE_BLKCIPHER, }, ++ [CRYPTO_MD5] = { plain(md5), SW_TYPE_HASH, }, ++ [CRYPTO_SHA1] = { plain(sha1), SW_TYPE_HASH, }, ++ [CRYPTO_NULL_HMAC] = { hmac(digest_null), SW_TYPE_HMAC, }, ++ [CRYPTO_NULL_CBC] = { cbc(cipher_null), SW_TYPE_BLKCIPHER, }, ++ [CRYPTO_DEFLATE_COMP] = { plain(deflate), SW_TYPE_COMP, }, ++ [CRYPTO_SHA2_256_HMAC] = { hmac(sha256), SW_TYPE_HMAC, }, ++ [CRYPTO_SHA2_384_HMAC] = { hmac(sha384), SW_TYPE_HMAC, }, ++ [CRYPTO_SHA2_512_HMAC] = { hmac(sha512), SW_TYPE_HMAC, }, ++ [CRYPTO_CAMELLIA_CBC] = { cbc(camellia), SW_TYPE_BLKCIPHER, }, ++ [CRYPTO_SHA2_256] = { plain(sha256), SW_TYPE_HASH, }, ++ [CRYPTO_SHA2_384] = { plain(sha384), SW_TYPE_HASH, }, ++ [CRYPTO_SHA2_512] = { plain(sha512), SW_TYPE_HASH, }, ++ [CRYPTO_RIPEMD160] = { plain(ripemd160), SW_TYPE_HASH, }, ++}; ++ ++int32_t swcr_id = -1; ++module_param(swcr_id, int, 0444); ++MODULE_PARM_DESC(swcr_id, "Read-Only OCF ID for cryptosoft driver"); ++ ++int swcr_fail_if_compression_grows = 1; ++module_param(swcr_fail_if_compression_grows, int, 0644); ++MODULE_PARM_DESC(swcr_fail_if_compression_grows, ++ "Treat compression that results in more data as a failure"); ++ ++int swcr_no_ahash = 0; ++module_param(swcr_no_ahash, int, 0644); ++MODULE_PARM_DESC(swcr_no_ahash, ++ "Do not use async hash/hmac even if available"); ++ ++int swcr_no_ablk = 0; ++module_param(swcr_no_ablk, int, 0644); ++MODULE_PARM_DESC(swcr_no_ablk, ++ "Do not use async blk ciphers even if available"); ++ ++static struct swcr_data **swcr_sessions = NULL; ++static u_int32_t swcr_sesnum = 0; ++ ++static int swcr_process(device_t, struct cryptop *, int); ++static int swcr_newsession(device_t, u_int32_t *, struct cryptoini *); ++static int swcr_freesession(device_t, u_int64_t); ++ ++static device_method_t swcr_methods = { ++ /* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, swcr_newsession), ++ DEVMETHOD(cryptodev_freesession,swcr_freesession), ++ DEVMETHOD(cryptodev_process, swcr_process), ++}; ++ ++#define debug swcr_debug ++int swcr_debug = 0; ++module_param(swcr_debug, int, 0644); ++MODULE_PARM_DESC(swcr_debug, "Enable debug"); ++ ++static void swcr_process_req(struct swcr_req *req); ++ ++/* ++ * somethings just need to be run with user context no matter whether ++ * the kernel compression libs use vmalloc/vfree for example. ++ */ ++ ++typedef struct { ++ struct work_struct wq; ++ void (*func)(void *arg); ++ void *arg; ++} execute_later_t; ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++static void ++doing_it_now(struct work_struct *wq) ++{ ++ execute_later_t *w = container_of(wq, execute_later_t, wq); ++ (w->func)(w->arg); ++ kfree(w); ++} ++#else ++static void ++doing_it_now(void *arg) ++{ ++ execute_later_t *w = (execute_later_t *) arg; ++ (w->func)(w->arg); ++ kfree(w); ++} ++#endif ++ ++static void ++execute_later(void (fn)(void *), void *arg) ++{ ++ execute_later_t *w; ++ ++ w = (execute_later_t *) kmalloc(sizeof(execute_later_t), SLAB_ATOMIC); ++ if (w) { ++ memset(w, '\0', sizeof(w)); ++ w->func = fn; ++ w->arg = arg; ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++ INIT_WORK(&w->wq, doing_it_now); ++#else ++ INIT_WORK(&w->wq, doing_it_now, w); ++#endif ++ schedule_work(&w->wq); ++ } ++} ++ ++/* ++ * Generate a new software session. ++ */ ++static int ++swcr_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) ++{ ++ struct swcr_data **swd; ++ u_int32_t i; ++ int error; ++ char *algo; ++ int mode; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (sid == NULL || cri == NULL) { ++ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ if (swcr_sessions) { ++ for (i = 1; i < swcr_sesnum; i++) ++ if (swcr_sessions[i] == NULL) ++ break; ++ } else ++ i = 1; /* NB: to silence compiler warning */ ++ ++ if (swcr_sessions == NULL || i == swcr_sesnum) { ++ if (swcr_sessions == NULL) { ++ i = 1; /* We leave swcr_sessions[0] empty */ ++ swcr_sesnum = CRYPTO_SW_SESSIONS; ++ } else ++ swcr_sesnum *= 2; ++ ++ swd = kmalloc(swcr_sesnum * sizeof(struct swcr_data *), SLAB_ATOMIC); ++ if (swd == NULL) { ++ /* Reset session number */ ++ if (swcr_sesnum == CRYPTO_SW_SESSIONS) ++ swcr_sesnum = 0; ++ else ++ swcr_sesnum /= 2; ++ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ memset(swd, 0, swcr_sesnum * sizeof(struct swcr_data *)); ++ ++ /* Copy existing sessions */ ++ if (swcr_sessions) { ++ memcpy(swd, swcr_sessions, ++ (swcr_sesnum / 2) * sizeof(struct swcr_data *)); ++ kfree(swcr_sessions); ++ } ++ ++ swcr_sessions = swd; ++ } ++ ++ swd = &swcr_sessions[i]; ++ *sid = i; ++ ++ while (cri) { ++ *swd = (struct swcr_data *) kmalloc(sizeof(struct swcr_data), ++ SLAB_ATOMIC); ++ if (*swd == NULL) { ++ swcr_freesession(NULL, i); ++ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ memset(*swd, 0, sizeof(struct swcr_data)); ++ ++ if (cri->cri_alg < 0 || ++ cri->cri_alg>=sizeof(crypto_details)/sizeof(crypto_details[0])){ ++ printk("cryptosoft: Unknown algorithm 0x%x\n", cri->cri_alg); ++ swcr_freesession(NULL, i); ++ return EINVAL; ++ } ++ ++ algo = crypto_details[cri->cri_alg].alg_name; ++ if (!algo || !*algo) { ++ printk("cryptosoft: Unsupported algorithm 0x%x\n", cri->cri_alg); ++ swcr_freesession(NULL, i); ++ return EINVAL; ++ } ++ ++ mode = crypto_details[cri->cri_alg].mode; ++ (*swd)->sw_type = crypto_details[cri->cri_alg].sw_type; ++ (*swd)->sw_alg = cri->cri_alg; ++ ++ spin_lock_init(&(*swd)->sw_tfm_lock); ++ ++ /* Algorithm specific configuration */ ++ switch (cri->cri_alg) { ++ case CRYPTO_NULL_CBC: ++ cri->cri_klen = 0; /* make it work with crypto API */ ++ break; ++ default: ++ break; ++ } ++ ++ if ((*swd)->sw_type & SW_TYPE_BLKCIPHER) { ++ dprintk("%s crypto_alloc_*blkcipher(%s, 0x%x)\n", __FUNCTION__, ++ algo, mode); ++ ++ /* try async first */ ++ (*swd)->sw_tfm = swcr_no_ablk ? NULL : ++ crypto_ablkcipher_tfm(crypto_alloc_ablkcipher(algo, 0, 0)); ++ if ((*swd)->sw_tfm && !IS_ERR((*swd)->sw_tfm)) { ++ dprintk("%s %s cipher is async\n", __FUNCTION__, algo); ++ (*swd)->sw_type |= SW_TYPE_ASYNC; ++ } else { ++ (*swd)->sw_tfm = crypto_blkcipher_tfm( ++ crypto_alloc_blkcipher(algo, 0, CRYPTO_ALG_ASYNC)); ++ if ((*swd)->sw_tfm && !IS_ERR((*swd)->sw_tfm)) ++ dprintk("%s %s cipher is sync\n", __FUNCTION__, algo); ++ } ++ if (!(*swd)->sw_tfm || IS_ERR((*swd)->sw_tfm)) { ++ int err; ++ dprintk("cryptosoft: crypto_alloc_blkcipher failed(%s, 0x%x)\n", ++ algo,mode); ++ err = IS_ERR((*swd)->sw_tfm) ? -(PTR_ERR((*swd)->sw_tfm)) : EINVAL; ++ (*swd)->sw_tfm = NULL; /* ensure NULL */ ++ swcr_freesession(NULL, i); ++ return err; ++ } ++ ++ if (debug) { ++ dprintk("%s key:cri->cri_klen=%d,(cri->cri_klen + 7)/8=%d", ++ __FUNCTION__, cri->cri_klen, (cri->cri_klen + 7) / 8); ++ for (i = 0; i < (cri->cri_klen + 7) / 8; i++) ++ dprintk("%s0x%x", (i % 8) ? " " : "\n ", ++ cri->cri_key[i] & 0xff); ++ dprintk("\n"); ++ } ++ if ((*swd)->sw_type & SW_TYPE_ASYNC) { ++ /* OCF doesn't enforce keys */ ++ crypto_ablkcipher_set_flags( ++ __crypto_ablkcipher_cast((*swd)->sw_tfm), ++ CRYPTO_TFM_REQ_WEAK_KEY); ++ error = crypto_ablkcipher_setkey( ++ __crypto_ablkcipher_cast((*swd)->sw_tfm), ++ cri->cri_key, (cri->cri_klen + 7) / 8); ++ } else { ++ /* OCF doesn't enforce keys */ ++ crypto_blkcipher_set_flags( ++ crypto_blkcipher_cast((*swd)->sw_tfm), ++ CRYPTO_TFM_REQ_WEAK_KEY); ++ error = crypto_blkcipher_setkey( ++ crypto_blkcipher_cast((*swd)->sw_tfm), ++ cri->cri_key, (cri->cri_klen + 7) / 8); ++ } ++ if (error) { ++ printk("cryptosoft: setkey failed %d (crt_flags=0x%x)\n", error, ++ (*swd)->sw_tfm->crt_flags); ++ swcr_freesession(NULL, i); ++ return error; ++ } ++ } else if ((*swd)->sw_type & (SW_TYPE_HMAC | SW_TYPE_HASH)) { ++ dprintk("%s crypto_alloc_*hash(%s, 0x%x)\n", __FUNCTION__, ++ algo, mode); ++ ++ /* try async first */ ++ (*swd)->sw_tfm = swcr_no_ahash ? NULL : ++ crypto_ahash_tfm(crypto_alloc_ahash(algo, 0, 0)); ++ if ((*swd)->sw_tfm) { ++ dprintk("%s %s hash is async\n", __FUNCTION__, algo); ++ (*swd)->sw_type |= SW_TYPE_ASYNC; ++ } else { ++ dprintk("%s %s hash is sync\n", __FUNCTION__, algo); ++ (*swd)->sw_tfm = crypto_hash_tfm( ++ crypto_alloc_hash(algo, 0, CRYPTO_ALG_ASYNC)); ++ } ++ ++ if (!(*swd)->sw_tfm) { ++ dprintk("cryptosoft: crypto_alloc_hash failed(%s,0x%x)\n", ++ algo, mode); ++ swcr_freesession(NULL, i); ++ return EINVAL; ++ } ++ ++ (*swd)->u.hmac.sw_klen = (cri->cri_klen + 7) / 8; ++ (*swd)->u.hmac.sw_key = (char *)kmalloc((*swd)->u.hmac.sw_klen, ++ SLAB_ATOMIC); ++ if ((*swd)->u.hmac.sw_key == NULL) { ++ swcr_freesession(NULL, i); ++ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ memcpy((*swd)->u.hmac.sw_key, cri->cri_key, (*swd)->u.hmac.sw_klen); ++ if (cri->cri_mlen) { ++ (*swd)->u.hmac.sw_mlen = cri->cri_mlen; ++ } else if ((*swd)->sw_type & SW_TYPE_ASYNC) { ++ (*swd)->u.hmac.sw_mlen = crypto_ahash_digestsize( ++ __crypto_ahash_cast((*swd)->sw_tfm)); ++ } else { ++ (*swd)->u.hmac.sw_mlen = crypto_hash_digestsize( ++ crypto_hash_cast((*swd)->sw_tfm)); ++ } ++ } else if ((*swd)->sw_type & SW_TYPE_COMP) { ++ (*swd)->sw_tfm = crypto_comp_tfm( ++ crypto_alloc_comp(algo, 0, CRYPTO_ALG_ASYNC)); ++ if (!(*swd)->sw_tfm) { ++ dprintk("cryptosoft: crypto_alloc_comp failed(%s,0x%x)\n", ++ algo, mode); ++ swcr_freesession(NULL, i); ++ return EINVAL; ++ } ++ (*swd)->u.sw_comp_buf = kmalloc(CRYPTO_MAX_DATA_LEN, SLAB_ATOMIC); ++ if ((*swd)->u.sw_comp_buf == NULL) { ++ swcr_freesession(NULL, i); ++ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ } else { ++ printk("cryptosoft: Unhandled sw_type %d\n", (*swd)->sw_type); ++ swcr_freesession(NULL, i); ++ return EINVAL; ++ } ++ ++ cri = cri->cri_next; ++ swd = &((*swd)->sw_next); ++ } ++ return 0; ++} ++ ++/* ++ * Free a session. ++ */ ++static int ++swcr_freesession(device_t dev, u_int64_t tid) ++{ ++ struct swcr_data *swd; ++ u_int32_t sid = CRYPTO_SESID2LID(tid); ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (sid > swcr_sesnum || swcr_sessions == NULL || ++ swcr_sessions[sid] == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return(EINVAL); ++ } ++ ++ /* Silently accept and return */ ++ if (sid == 0) ++ return(0); ++ ++ while ((swd = swcr_sessions[sid]) != NULL) { ++ swcr_sessions[sid] = swd->sw_next; ++ if (swd->sw_tfm) { ++ switch (swd->sw_type & SW_TYPE_ALG_AMASK) { ++#ifdef HAVE_AHASH ++ case SW_TYPE_AHMAC: ++ case SW_TYPE_AHASH: ++ crypto_free_ahash(__crypto_ahash_cast(swd->sw_tfm)); ++ break; ++#endif ++#ifdef HAVE_ABLKCIPHER ++ case SW_TYPE_ABLKCIPHER: ++ crypto_free_ablkcipher(__crypto_ablkcipher_cast(swd->sw_tfm)); ++ break; ++#endif ++ case SW_TYPE_BLKCIPHER: ++ crypto_free_blkcipher(crypto_blkcipher_cast(swd->sw_tfm)); ++ break; ++ case SW_TYPE_HMAC: ++ case SW_TYPE_HASH: ++ crypto_free_hash(crypto_hash_cast(swd->sw_tfm)); ++ break; ++ case SW_TYPE_COMP: ++ if (in_interrupt()) ++ execute_later((void (*)(void *))crypto_free_comp, (void *)crypto_comp_cast(swd->sw_tfm)); ++ else ++ crypto_free_comp(crypto_comp_cast(swd->sw_tfm)); ++ break; ++ default: ++ crypto_free_tfm(swd->sw_tfm); ++ break; ++ } ++ swd->sw_tfm = NULL; ++ } ++ if (swd->sw_type & SW_TYPE_COMP) { ++ if (swd->u.sw_comp_buf) ++ kfree(swd->u.sw_comp_buf); ++ } else { ++ if (swd->u.hmac.sw_key) ++ kfree(swd->u.hmac.sw_key); ++ } ++ kfree(swd); ++ } ++ return 0; ++} ++ ++static void swcr_process_req_complete(struct swcr_req *req) ++{ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (req->sw->sw_type & SW_TYPE_INUSE) { ++ unsigned long flags; ++ spin_lock_irqsave(&req->sw->sw_tfm_lock, flags); ++ req->sw->sw_type &= ~SW_TYPE_INUSE; ++ spin_unlock_irqrestore(&req->sw->sw_tfm_lock, flags); ++ } ++ ++ if (req->crp->crp_etype) ++ goto done; ++ ++ switch (req->sw->sw_type & SW_TYPE_ALG_AMASK) { ++#if defined(HAVE_AHASH) ++ case SW_TYPE_AHMAC: ++ case SW_TYPE_AHASH: ++ crypto_copyback(req->crp->crp_flags, req->crp->crp_buf, ++ req->crd->crd_inject, req->sw->u.hmac.sw_mlen, req->result); ++ ahash_request_free(req->crypto_req); ++ break; ++#endif ++#if defined(HAVE_ABLKCIPHER) ++ case SW_TYPE_ABLKCIPHER: ++ ablkcipher_request_free(req->crypto_req); ++ break; ++#endif ++ case SW_TYPE_CIPHER: ++ case SW_TYPE_HMAC: ++ case SW_TYPE_HASH: ++ case SW_TYPE_COMP: ++ case SW_TYPE_BLKCIPHER: ++ break; ++ default: ++ req->crp->crp_etype = EINVAL; ++ goto done; ++ } ++ ++ req->crd = req->crd->crd_next; ++ if (req->crd) { ++ swcr_process_req(req); ++ return; ++ } ++ ++done: ++ dprintk("%s crypto_done %p\n", __FUNCTION__, req); ++ crypto_done(req->crp); ++ kmem_cache_free(swcr_req_cache, req); ++} ++ ++#if defined(HAVE_ABLKCIPHER) || defined(HAVE_AHASH) ++static void swcr_process_callback(struct crypto_async_request *creq, int err) ++{ ++ struct swcr_req *req = creq->data; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (err) { ++ if (err == -EINPROGRESS) ++ return; ++ dprintk("%s() fail %d\n", __FUNCTION__, -err); ++ req->crp->crp_etype = -err; ++ } ++ ++ swcr_process_req_complete(req); ++} ++#endif /* defined(HAVE_ABLKCIPHER) || defined(HAVE_AHASH) */ ++ ++ ++static void swcr_process_req(struct swcr_req *req) ++{ ++ struct swcr_data *sw; ++ struct cryptop *crp = req->crp; ++ struct cryptodesc *crd = req->crd; ++ struct sk_buff *skb = (struct sk_buff *) crp->crp_buf; ++ struct uio *uiop = (struct uio *) crp->crp_buf; ++ int sg_num, sg_len, skip; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ /* ++ * Find the crypto context. ++ * ++ * XXX Note that the logic here prevents us from having ++ * XXX the same algorithm multiple times in a session ++ * XXX (or rather, we can but it won't give us the right ++ * XXX results). To do that, we'd need some way of differentiating ++ * XXX between the various instances of an algorithm (so we can ++ * XXX locate the correct crypto context). ++ */ ++ for (sw = req->sw_head; sw && sw->sw_alg != crd->crd_alg; sw = sw->sw_next) ++ ; ++ ++ /* No such context ? */ ++ if (sw == NULL) { ++ crp->crp_etype = EINVAL; ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ goto done; ++ } ++ ++ /* ++ * for some types we need to ensure only one user as info is stored in ++ * the tfm during an operation that can get corrupted ++ */ ++ switch (sw->sw_type & SW_TYPE_ALG_AMASK) { ++#ifdef HAVE_AHASH ++ case SW_TYPE_AHMAC: ++ case SW_TYPE_AHASH: ++#endif ++ case SW_TYPE_HMAC: ++ case SW_TYPE_HASH: { ++ unsigned long flags; ++ spin_lock_irqsave(&sw->sw_tfm_lock, flags); ++ if (sw->sw_type & SW_TYPE_INUSE) { ++ spin_unlock_irqrestore(&sw->sw_tfm_lock, flags); ++ execute_later((void (*)(void *))swcr_process_req, (void *)req); ++ return; ++ } ++ sw->sw_type |= SW_TYPE_INUSE; ++ spin_unlock_irqrestore(&sw->sw_tfm_lock, flags); ++ } break; ++ } ++ ++ req->sw = sw; ++ skip = crd->crd_skip; ++ ++ /* ++ * setup the SG list skip from the start of the buffer ++ */ ++ memset(req->sg, 0, sizeof(req->sg)); ++ sg_init_table(req->sg, SCATTERLIST_MAX); ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ int i, len; ++ ++ sg_num = 0; ++ sg_len = 0; ++ ++ if (skip < skb_headlen(skb)) { ++ len = skb_headlen(skb) - skip; ++ if (len + sg_len > crd->crd_len) ++ len = crd->crd_len - sg_len; ++ sg_set_page(&req->sg[sg_num], ++ virt_to_page(skb->data + skip), len, ++ offset_in_page(skb->data + skip)); ++ sg_len += len; ++ sg_num++; ++ skip = 0; ++ } else ++ skip -= skb_headlen(skb); ++ ++ for (i = 0; sg_len < crd->crd_len && ++ i < skb_shinfo(skb)->nr_frags && ++ sg_num < SCATTERLIST_MAX; i++) { ++ if (skip < skb_shinfo(skb)->frags[i].size) { ++ len = skb_shinfo(skb)->frags[i].size - skip; ++ if (len + sg_len > crd->crd_len) ++ len = crd->crd_len - sg_len; ++ sg_set_page(&req->sg[sg_num], ++ skb_shinfo(skb)->frags[i].page, ++ len, ++ skb_shinfo(skb)->frags[i].page_offset + skip); ++ sg_len += len; ++ sg_num++; ++ skip = 0; ++ } else ++ skip -= skb_shinfo(skb)->frags[i].size; ++ } ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ int len; ++ ++ sg_len = 0; ++ for (sg_num = 0; sg_len < crd->crd_len && ++ sg_num < uiop->uio_iovcnt && ++ sg_num < SCATTERLIST_MAX; sg_num++) { ++ if (skip <= uiop->uio_iov[sg_num].iov_len) { ++ len = uiop->uio_iov[sg_num].iov_len - skip; ++ if (len + sg_len > crd->crd_len) ++ len = crd->crd_len - sg_len; ++ sg_set_page(&req->sg[sg_num], ++ virt_to_page(uiop->uio_iov[sg_num].iov_base+skip), ++ len, ++ offset_in_page(uiop->uio_iov[sg_num].iov_base+skip)); ++ sg_len += len; ++ skip = 0; ++ } else ++ skip -= uiop->uio_iov[sg_num].iov_len; ++ } ++ } else { ++ sg_len = (crp->crp_ilen - skip); ++ if (sg_len > crd->crd_len) ++ sg_len = crd->crd_len; ++ sg_set_page(&req->sg[0], virt_to_page(crp->crp_buf + skip), ++ sg_len, offset_in_page(crp->crp_buf + skip)); ++ sg_num = 1; ++ } ++ ++ switch (sw->sw_type & SW_TYPE_ALG_AMASK) { ++ ++#ifdef HAVE_AHASH ++ case SW_TYPE_AHMAC: ++ case SW_TYPE_AHASH: ++ { ++ int ret; ++ ++ /* check we have room for the result */ ++ if (crp->crp_ilen - crd->crd_inject < sw->u.hmac.sw_mlen) { ++ dprintk("cryptosoft: EINVAL crp_ilen=%d, len=%d, inject=%d " ++ "digestsize=%d\n", crp->crp_ilen, crd->crd_skip + sg_len, ++ crd->crd_inject, sw->u.hmac.sw_mlen); ++ crp->crp_etype = EINVAL; ++ goto done; ++ } ++ ++ req->crypto_req = ++ ahash_request_alloc(__crypto_ahash_cast(sw->sw_tfm),GFP_ATOMIC); ++ if (!req->crypto_req) { ++ crp->crp_etype = ENOMEM; ++ dprintk("%s,%d: ENOMEM ahash_request_alloc", __FILE__, __LINE__); ++ goto done; ++ } ++ ++ ahash_request_set_callback(req->crypto_req, ++ CRYPTO_TFM_REQ_MAY_BACKLOG, swcr_process_callback, req); ++ ++ memset(req->result, 0, sizeof(req->result)); ++ ++ if (sw->sw_type & SW_TYPE_AHMAC) ++ crypto_ahash_setkey(__crypto_ahash_cast(sw->sw_tfm), ++ sw->u.hmac.sw_key, sw->u.hmac.sw_klen); ++ ahash_request_set_crypt(req->crypto_req, req->sg, req->result, sg_len); ++ ret = crypto_ahash_digest(req->crypto_req); ++ switch (ret) { ++ case -EINPROGRESS: ++ case -EBUSY: ++ return; ++ default: ++ case 0: ++ dprintk("hash OP %s %d\n", ret ? "failed" : "success", ret); ++ crp->crp_etype = ret; ++ goto done; ++ } ++ } break; ++#endif /* HAVE_AHASH */ ++ ++#ifdef HAVE_ABLKCIPHER ++ case SW_TYPE_ABLKCIPHER: { ++ int ret; ++ unsigned char *ivp = req->iv; ++ int ivsize = ++ crypto_ablkcipher_ivsize(__crypto_ablkcipher_cast(sw->sw_tfm)); ++ ++ if (sg_len < crypto_ablkcipher_blocksize( ++ __crypto_ablkcipher_cast(sw->sw_tfm))) { ++ crp->crp_etype = EINVAL; ++ dprintk("%s,%d: EINVAL len %d < %d\n", __FILE__, __LINE__, ++ sg_len, crypto_ablkcipher_blocksize( ++ __crypto_ablkcipher_cast(sw->sw_tfm))); ++ goto done; ++ } ++ ++ if (ivsize > sizeof(req->iv)) { ++ crp->crp_etype = EINVAL; ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ goto done; ++ } ++ ++ req->crypto_req = ablkcipher_request_alloc( ++ __crypto_ablkcipher_cast(sw->sw_tfm), GFP_ATOMIC); ++ if (!req->crypto_req) { ++ crp->crp_etype = ENOMEM; ++ dprintk("%s,%d: ENOMEM ablkcipher_request_alloc", ++ __FILE__, __LINE__); ++ goto done; ++ } ++ ++ ablkcipher_request_set_callback(req->crypto_req, ++ CRYPTO_TFM_REQ_MAY_BACKLOG, swcr_process_callback, req); ++ ++ if (crd->crd_flags & CRD_F_KEY_EXPLICIT) { ++ int i, error; ++ ++ if (debug) { ++ dprintk("%s key:", __FUNCTION__); ++ for (i = 0; i < (crd->crd_klen + 7) / 8; i++) ++ dprintk("%s0x%x", (i % 8) ? " " : "\n ", ++ crd->crd_key[i] & 0xff); ++ dprintk("\n"); ++ } ++ /* OCF doesn't enforce keys */ ++ crypto_ablkcipher_set_flags(__crypto_ablkcipher_cast(sw->sw_tfm), ++ CRYPTO_TFM_REQ_WEAK_KEY); ++ error = crypto_ablkcipher_setkey( ++ __crypto_ablkcipher_cast(sw->sw_tfm), crd->crd_key, ++ (crd->crd_klen + 7) / 8); ++ if (error) { ++ dprintk("cryptosoft: setkey failed %d (crt_flags=0x%x)\n", ++ error, sw->sw_tfm->crt_flags); ++ crp->crp_etype = -error; ++ } ++ } ++ ++ if (crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ ++ ++ if (crd->crd_flags & CRD_F_IV_EXPLICIT) ++ ivp = crd->crd_iv; ++ else ++ get_random_bytes(ivp, ivsize); ++ /* ++ * do we have to copy the IV back to the buffer ? ++ */ ++ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ crd->crd_inject, ivsize, (caddr_t)ivp); ++ } ++ ablkcipher_request_set_crypt(req->crypto_req, req->sg, req->sg, ++ sg_len, ivp); ++ ret = crypto_ablkcipher_encrypt(req->crypto_req); ++ ++ } else { /*decrypt */ ++ ++ if (crd->crd_flags & CRD_F_IV_EXPLICIT) ++ ivp = crd->crd_iv; ++ else ++ crypto_copydata(crp->crp_flags, crp->crp_buf, ++ crd->crd_inject, ivsize, (caddr_t)ivp); ++ ablkcipher_request_set_crypt(req->crypto_req, req->sg, req->sg, ++ sg_len, ivp); ++ ret = crypto_ablkcipher_decrypt(req->crypto_req); ++ } ++ ++ switch (ret) { ++ case -EINPROGRESS: ++ case -EBUSY: ++ return; ++ default: ++ case 0: ++ dprintk("crypto OP %s %d\n", ret ? "failed" : "success", ret); ++ crp->crp_etype = ret; ++ goto done; ++ } ++ } break; ++#endif /* HAVE_ABLKCIPHER */ ++ ++ case SW_TYPE_BLKCIPHER: { ++ unsigned char iv[EALG_MAX_BLOCK_LEN]; ++ unsigned char *ivp = iv; ++ struct blkcipher_desc desc; ++ int ivsize = crypto_blkcipher_ivsize(crypto_blkcipher_cast(sw->sw_tfm)); ++ ++ if (sg_len < crypto_blkcipher_blocksize( ++ crypto_blkcipher_cast(sw->sw_tfm))) { ++ crp->crp_etype = EINVAL; ++ dprintk("%s,%d: EINVAL len %d < %d\n", __FILE__, __LINE__, ++ sg_len, crypto_blkcipher_blocksize( ++ crypto_blkcipher_cast(sw->sw_tfm))); ++ goto done; ++ } ++ ++ if (ivsize > sizeof(iv)) { ++ crp->crp_etype = EINVAL; ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ goto done; ++ } ++ ++ if (crd->crd_flags & CRD_F_KEY_EXPLICIT) { ++ int i, error; ++ ++ if (debug) { ++ dprintk("%s key:", __FUNCTION__); ++ for (i = 0; i < (crd->crd_klen + 7) / 8; i++) ++ dprintk("%s0x%x", (i % 8) ? " " : "\n ", ++ crd->crd_key[i] & 0xff); ++ dprintk("\n"); ++ } ++ /* OCF doesn't enforce keys */ ++ crypto_blkcipher_set_flags(crypto_blkcipher_cast(sw->sw_tfm), ++ CRYPTO_TFM_REQ_WEAK_KEY); ++ error = crypto_blkcipher_setkey( ++ crypto_blkcipher_cast(sw->sw_tfm), crd->crd_key, ++ (crd->crd_klen + 7) / 8); ++ if (error) { ++ dprintk("cryptosoft: setkey failed %d (crt_flags=0x%x)\n", ++ error, sw->sw_tfm->crt_flags); ++ crp->crp_etype = -error; ++ } ++ } ++ ++ memset(&desc, 0, sizeof(desc)); ++ desc.tfm = crypto_blkcipher_cast(sw->sw_tfm); ++ ++ if (crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ ++ ++ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { ++ ivp = crd->crd_iv; ++ } else { ++ get_random_bytes(ivp, ivsize); ++ } ++ /* ++ * do we have to copy the IV back to the buffer ? ++ */ ++ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ crd->crd_inject, ivsize, (caddr_t)ivp); ++ } ++ desc.info = ivp; ++ crypto_blkcipher_encrypt_iv(&desc, req->sg, req->sg, sg_len); ++ ++ } else { /*decrypt */ ++ ++ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { ++ ivp = crd->crd_iv; ++ } else { ++ crypto_copydata(crp->crp_flags, crp->crp_buf, ++ crd->crd_inject, ivsize, (caddr_t)ivp); ++ } ++ desc.info = ivp; ++ crypto_blkcipher_decrypt_iv(&desc, req->sg, req->sg, sg_len); ++ } ++ } break; ++ ++ case SW_TYPE_HMAC: ++ case SW_TYPE_HASH: ++ { ++ char result[HASH_MAX_LEN]; ++ struct hash_desc desc; ++ ++ /* check we have room for the result */ ++ if (crp->crp_ilen - crd->crd_inject < sw->u.hmac.sw_mlen) { ++ dprintk("cryptosoft: EINVAL crp_ilen=%d, len=%d, inject=%d " ++ "digestsize=%d\n", crp->crp_ilen, crd->crd_skip + sg_len, ++ crd->crd_inject, sw->u.hmac.sw_mlen); ++ crp->crp_etype = EINVAL; ++ goto done; ++ } ++ ++ memset(&desc, 0, sizeof(desc)); ++ desc.tfm = crypto_hash_cast(sw->sw_tfm); ++ ++ memset(result, 0, sizeof(result)); ++ ++ if (sw->sw_type & SW_TYPE_HMAC) { ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) ++ crypto_hmac(sw->sw_tfm, sw->u.hmac.sw_key, &sw->u.hmac.sw_klen, ++ req->sg, sg_num, result); ++#else ++ crypto_hash_setkey(desc.tfm, sw->u.hmac.sw_key, ++ sw->u.hmac.sw_klen); ++ crypto_hash_digest(&desc, req->sg, sg_len, result); ++#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) */ ++ ++ } else { /* SW_TYPE_HASH */ ++ crypto_hash_digest(&desc, req->sg, sg_len, result); ++ } ++ ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ crd->crd_inject, sw->u.hmac.sw_mlen, result); ++ } ++ break; ++ ++ case SW_TYPE_COMP: { ++ void *ibuf = NULL; ++ void *obuf = sw->u.sw_comp_buf; ++ int ilen = sg_len, olen = CRYPTO_MAX_DATA_LEN; ++ int ret = 0; ++ ++ /* ++ * we need to use an additional copy if there is more than one ++ * input chunk since the kernel comp routines do not handle ++ * SG yet. Otherwise we just use the input buffer as is. ++ * Rather than allocate another buffer we just split the tmp ++ * buffer we already have. ++ * Perhaps we should just use zlib directly ? ++ */ ++ if (sg_num > 1) { ++ int blk; ++ ++ ibuf = obuf; ++ for (blk = 0; blk < sg_num; blk++) { ++ memcpy(obuf, sg_virt(&req->sg[blk]), ++ req->sg[blk].length); ++ obuf += req->sg[blk].length; ++ } ++ olen -= sg_len; ++ } else ++ ibuf = sg_virt(&req->sg[0]); ++ ++ if (crd->crd_flags & CRD_F_ENCRYPT) { /* compress */ ++ ret = crypto_comp_compress(crypto_comp_cast(sw->sw_tfm), ++ ibuf, ilen, obuf, &olen); ++ if (!ret && olen > crd->crd_len) { ++ dprintk("cryptosoft: ERANGE compress %d into %d\n", ++ crd->crd_len, olen); ++ if (swcr_fail_if_compression_grows) ++ ret = ERANGE; ++ } ++ } else { /* decompress */ ++ ret = crypto_comp_decompress(crypto_comp_cast(sw->sw_tfm), ++ ibuf, ilen, obuf, &olen); ++ if (!ret && (olen + crd->crd_inject) > crp->crp_olen) { ++ dprintk("cryptosoft: ETOOSMALL decompress %d into %d, " ++ "space for %d,at offset %d\n", ++ crd->crd_len, olen, crp->crp_olen, crd->crd_inject); ++ ret = ETOOSMALL; ++ } ++ } ++ if (ret) ++ dprintk("%s,%d: ret = %d\n", __FILE__, __LINE__, ret); ++ ++ /* ++ * on success copy result back, ++ * linux crpyto API returns -errno, we need to fix that ++ */ ++ crp->crp_etype = ret < 0 ? -ret : ret; ++ if (ret == 0) { ++ /* copy back the result and return it's size */ ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ crd->crd_inject, olen, obuf); ++ crp->crp_olen = olen; ++ } ++ } break; ++ ++ default: ++ /* Unknown/unsupported algorithm */ ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ crp->crp_etype = EINVAL; ++ goto done; ++ } ++ ++done: ++ swcr_process_req_complete(req); ++} ++ ++ ++/* ++ * Process a crypto request. ++ */ ++static int ++swcr_process(device_t dev, struct cryptop *crp, int hint) ++{ ++ struct swcr_req *req = NULL; ++ u_int32_t lid; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ /* Sanity check */ ++ if (crp == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ crp->crp_etype = 0; ++ ++ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ crp->crp_etype = EINVAL; ++ goto done; ++ } ++ ++ lid = crp->crp_sid & 0xffffffff; ++ if (lid >= swcr_sesnum || lid == 0 || swcr_sessions == NULL || ++ swcr_sessions[lid] == NULL) { ++ crp->crp_etype = ENOENT; ++ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); ++ goto done; ++ } ++ ++ /* ++ * do some error checking outside of the loop for SKB and IOV processing ++ * this leaves us with valid skb or uiop pointers for later ++ */ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ struct sk_buff *skb = (struct sk_buff *) crp->crp_buf; ++ if (skb_shinfo(skb)->nr_frags >= SCATTERLIST_MAX) { ++ printk("%s,%d: %d nr_frags > SCATTERLIST_MAX", __FILE__, __LINE__, ++ skb_shinfo(skb)->nr_frags); ++ goto done; ++ } ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ struct uio *uiop = (struct uio *) crp->crp_buf; ++ if (uiop->uio_iovcnt > SCATTERLIST_MAX) { ++ printk("%s,%d: %d uio_iovcnt > SCATTERLIST_MAX", __FILE__, __LINE__, ++ uiop->uio_iovcnt); ++ goto done; ++ } ++ } ++ ++ /* ++ * setup a new request ready for queuing ++ */ ++ req = kmem_cache_alloc(swcr_req_cache, SLAB_ATOMIC); ++ if (req == NULL) { ++ dprintk("%s,%d: ENOMEM\n", __FILE__, __LINE__); ++ crp->crp_etype = ENOMEM; ++ goto done; ++ } ++ memset(req, 0, sizeof(*req)); ++ ++ req->sw_head = swcr_sessions[lid]; ++ req->crp = crp; ++ req->crd = crp->crp_desc; ++ ++ swcr_process_req(req); ++ return 0; ++ ++done: ++ crypto_done(crp); ++ if (req) ++ kmem_cache_free(swcr_req_cache, req); ++ return 0; ++} ++ ++ ++static int ++cryptosoft_init(void) ++{ ++ int i, sw_type, mode; ++ char *algo; ++ ++ dprintk("%s(%p)\n", __FUNCTION__, cryptosoft_init); ++ ++ swcr_req_cache = kmem_cache_create("cryptosoft_req", ++ sizeof(struct swcr_req), 0, SLAB_HWCACHE_ALIGN, NULL ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) ++ , NULL ++#endif ++ ); ++ if (!swcr_req_cache) { ++ printk("cryptosoft: failed to create request cache\n"); ++ return -ENOENT; ++ } ++ ++ softc_device_init(&swcr_softc, "cryptosoft", 0, swcr_methods); ++ ++ swcr_id = crypto_get_driverid(softc_get_device(&swcr_softc), ++ CRYPTOCAP_F_SOFTWARE | CRYPTOCAP_F_SYNC); ++ if (swcr_id < 0) { ++ printk("cryptosoft: Software crypto device cannot initialize!"); ++ return -ENODEV; ++ } ++ ++#define REGISTER(alg) \ ++ crypto_register(swcr_id, alg, 0,0) ++ ++ for (i = 0; i < sizeof(crypto_details)/sizeof(crypto_details[0]); i++) { ++ int found; ++ ++ algo = crypto_details[i].alg_name; ++ if (!algo || !*algo) { ++ dprintk("%s:Algorithm %d not supported\n", __FUNCTION__, i); ++ continue; ++ } ++ ++ mode = crypto_details[i].mode; ++ sw_type = crypto_details[i].sw_type; ++ ++ found = 0; ++ switch (sw_type & SW_TYPE_ALG_MASK) { ++ case SW_TYPE_CIPHER: ++ found = crypto_has_cipher(algo, 0, CRYPTO_ALG_ASYNC); ++ break; ++ case SW_TYPE_HMAC: ++ found = crypto_has_hash(algo, 0, swcr_no_ahash?CRYPTO_ALG_ASYNC:0); ++ break; ++ case SW_TYPE_HASH: ++ found = crypto_has_hash(algo, 0, swcr_no_ahash?CRYPTO_ALG_ASYNC:0); ++ break; ++ case SW_TYPE_COMP: ++ found = crypto_has_comp(algo, 0, CRYPTO_ALG_ASYNC); ++ break; ++ case SW_TYPE_BLKCIPHER: ++ found = crypto_has_blkcipher(algo, 0, CRYPTO_ALG_ASYNC); ++ if (!found && !swcr_no_ablk) ++ found = crypto_has_ablkcipher(algo, 0, 0); ++ break; ++ } ++ if (found) { ++ REGISTER(i); ++ } else { ++ dprintk("%s:Algorithm Type %d not supported (algorithm %d:'%s')\n", ++ __FUNCTION__, sw_type, i, algo); ++ } ++ } ++ return 0; ++} ++ ++static void ++cryptosoft_exit(void) ++{ ++ dprintk("%s()\n", __FUNCTION__); ++ crypto_unregister_all(swcr_id); ++ swcr_id = -1; ++ kmem_cache_destroy(swcr_req_cache); ++} ++ ++late_initcall(cryptosoft_init); ++module_exit(cryptosoft_exit); ++ ++MODULE_LICENSE("Dual BSD/GPL"); ++MODULE_AUTHOR("David McCullough "); ++MODULE_DESCRIPTION("Cryptosoft (OCF module for kernel crypto)"); +diff -Nur linux-3.1.4.orig/crypto/ocf/ep80579/Makefile linux-3.1.4/crypto/ocf/ep80579/Makefile +--- linux-3.1.4.orig/crypto/ocf/ep80579/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/ep80579/Makefile 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,119 @@ ++######################################################################### ++# ++# Targets supported ++# all - builds everything and installs ++# install - identical to all ++# depend - build dependencies ++# clean - clears derived objects except the .depend files ++# distclean- clears all derived objects and the .depend file ++# ++# @par ++# This file is provided under a dual BSD/GPLv2 license. When using or ++# redistributing this file, you may do so under either license. ++# ++# GPL LICENSE SUMMARY ++# ++# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. ++# ++# This program is free software; you can redistribute it and/or modify ++# it under the terms of version 2 of the GNU General Public License as ++# published by the Free Software Foundation. ++# ++# This program is distributed in the hope that it will be useful, but ++# WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++# General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++# The full GNU General Public License is included in this distribution ++# in the file called LICENSE.GPL. ++# ++# Contact Information: ++# Intel Corporation ++# ++# BSD LICENSE ++# ++# Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. ++# All rights reserved. ++# ++# Redistribution and use in source and binary forms, with or without ++# modification, are permitted provided that the following conditions ++# are met: ++# ++# * Redistributions of source code must retain the above copyright ++# notice, this list of conditions and the following disclaimer. ++# * Redistributions in binary form must reproduce the above copyright ++# notice, this list of conditions and the following disclaimer in ++# the documentation and/or other materials provided with the ++# distribution. ++# * Neither the name of Intel Corporation nor the names of its ++# contributors may be used to endorse or promote products derived ++# from this software without specific prior written permission. ++# ++# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++# ++# ++# version: Security.L.1.0.2-229 ++############################################################################ ++ ++ ++####################Common variables and definitions######################## ++ ++ifndef ICP_ROOT ++$(warning ICP_ROOT is undefined. Please set the path to EP80579 release package directory \ ++ "-> setenv ICP_ROOT ") ++all fastdep: ++ : ++else ++ ++ifndef KERNEL_SOURCE_ROOT ++$(error KERNEL_SOURCE_ROOT is undefined. Please set the path to the kernel source directory \ ++ "-> setenv KERNEL_SOURCE_ROOT ") ++endif ++ ++# Ensure The ENV_DIR environmental var is defined. ++ifndef ICP_ENV_DIR ++$(error ICP_ENV_DIR is undefined. Please set the path to EP80579 driver environment.mk file \ ++ "-> setenv ICP_ENV_DIR ") ++endif ++ ++#Add your project environment Makefile ++include ${ICP_ENV_DIR}/environment.mk ++ ++#include the makefile with all the default and common Make variable definitions ++include ${ICP_BUILDSYSTEM_PATH}/build_files/common.mk ++ ++#Add the name for the executable, Library or Module output definitions ++OUTPUT_NAME= icp_ocf ++ ++# List of Source Files to be compiled ++SOURCES= icp_common.c icp_sym.c icp_asym.c icp_ocf_linux.c ++ ++#common includes between all supported OSes ++INCLUDES= -I ${ICP_API_DIR} -I${ICP_LAC_API} \ ++-I${ICP_OCF_SRC_DIR} ++ ++# The location of the os level makefile needs to be changed. ++include ${ICP_ENV_DIR}/${ICP_OS}_${ICP_OS_LEVEL}.mk ++ ++# On the line directly below list the outputs you wish to build for, ++# e.g "lib_static lib_shared exe module" as shown below ++install: module ++ ++###################Include rules makefiles######################## ++include ${ICP_BUILDSYSTEM_PATH}/build_files/rules.mk ++###################End of Rules inclusion######################### ++ ++endif +diff -Nur linux-3.1.4.orig/crypto/ocf/ep80579/environment.mk linux-3.1.4/crypto/ocf/ep80579/environment.mk +--- linux-3.1.4.orig/crypto/ocf/ep80579/environment.mk 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/ep80579/environment.mk 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,78 @@ ++ ########################################################################### ++ # ++# This file is provided under a dual BSD/GPLv2 license. When using or ++# redistributing this file, you may do so under either license. ++# ++# GPL LICENSE SUMMARY ++# ++# Copyright(c) 2007,2008 Intel Corporation. All rights reserved. ++# ++# This program is free software; you can redistribute it and/or modify ++# it under the terms of version 2 of the GNU General Public License as ++# published by the Free Software Foundation. ++# ++# This program is distributed in the hope that it will be useful, but ++# WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++# General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++# The full GNU General Public License is included in this distribution ++# in the file called LICENSE.GPL. ++# ++# Contact Information: ++# Intel Corporation ++# ++# BSD LICENSE ++# ++# Copyright(c) 2007,2008 Intel Corporation. All rights reserved. ++# All rights reserved. ++# ++# Redistribution and use in source and binary forms, with or without ++# modification, are permitted provided that the following conditions ++# are met: ++# ++# * Redistributions of source code must retain the above copyright ++# notice, this list of conditions and the following disclaimer. ++# * Redistributions in binary form must reproduce the above copyright ++# notice, this list of conditions and the following disclaimer in ++# the documentation and/or other materials provided with the ++# distribution. ++# * Neither the name of Intel Corporation nor the names of its ++# contributors may be used to endorse or promote products derived ++# from this software without specific prior written permission. ++# ++# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++# ++# ++# version: Security.L.1.0.130 ++ # ++ ########################################################################### ++ ++ ++ICP_LAC_API=$(ICP_ROOT)/Acceleration/include/lac ++ICP_BTR_API=$(ICP_ROOT)/Acceleration/include/btr ++ICP_API_DIR=$(ICP_ROOT)/Acceleration/include ++ICP_OCF_SHIM_DIR?=$(KERNEL_SOURCE_ROOT)/crypto/ocf/ ++ifeq ($(wildcard $(ICP_OCF_SHIM_DIR)),) ++ICP_OCF_SHIM_DIR?=$(ROOTDIR)/modules/ocf/ ++endif ++ ++ICP_OS_LEVEL?=kernel_space ++ ++ICP_OS?=linux_2.6 ++ ++ICP_CORE?=ia ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/ep80579/icp_asym.c linux-3.1.4/crypto/ocf/ep80579/icp_asym.c +--- linux-3.1.4.orig/crypto/ocf/ep80579/icp_asym.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/ep80579/icp_asym.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,1334 @@ ++/*************************************************************************** ++ * ++ * This file is provided under a dual BSD/GPLv2 license. When using or ++ * redistributing this file, you may do so under either license. ++ * ++ * GPL LICENSE SUMMARY ++ * ++ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ * The full GNU General Public License is included in this distribution ++ * in the file called LICENSE.GPL. ++ * ++ * Contact Information: ++ * Intel Corporation ++ * ++ * BSD LICENSE ++ * ++ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * * Neither the name of Intel Corporation nor the names of its ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * ++ * version: Security.L.1.0.2-229 ++ * ++ ***************************************************************************/ ++ ++#include "icp_ocf.h" ++ ++/*The following define values (containing the word 'INDEX') are used to find ++the index of each input buffer of the crypto_kop struct (see OCF cryptodev.h). ++These values were found through analysis of the OCF OpenSSL patch. If the ++calling program uses different input buffer positions, these defines will have ++to be changed.*/ ++ ++/*DIFFIE HELLMAN buffer index values*/ ++#define ICP_DH_KRP_PARAM_PRIME_INDEX (0) ++#define ICP_DH_KRP_PARAM_BASE_INDEX (1) ++#define ICP_DH_KRP_PARAM_PRIVATE_VALUE_INDEX (2) ++#define ICP_DH_KRP_PARAM_RESULT_INDEX (3) ++ ++/*MOD EXP buffer index values*/ ++#define ICP_MOD_EXP_KRP_PARAM_BASE_INDEX (0) ++#define ICP_MOD_EXP_KRP_PARAM_EXPONENT_INDEX (1) ++#define ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX (2) ++#define ICP_MOD_EXP_KRP_PARAM_RESULT_INDEX (3) ++ ++/*MOD EXP CRT buffer index values*/ ++#define ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_P_INDEX (0) ++#define ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_Q_INDEX (1) ++#define ICP_MOD_EXP_CRT_KRP_PARAM_I_INDEX (2) ++#define ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DP_INDEX (3) ++#define ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DQ_INDEX (4) ++#define ICP_MOD_EXP_CRT_KRP_PARAM_COEFF_QINV_INDEX (5) ++#define ICP_MOD_EXP_CRT_KRP_PARAM_RESULT_INDEX (6) ++ ++/*DSA sign buffer index values*/ ++#define ICP_DSA_SIGN_KRP_PARAM_DGST_INDEX (0) ++#define ICP_DSA_SIGN_KRP_PARAM_PRIME_P_INDEX (1) ++#define ICP_DSA_SIGN_KRP_PARAM_PRIME_Q_INDEX (2) ++#define ICP_DSA_SIGN_KRP_PARAM_G_INDEX (3) ++#define ICP_DSA_SIGN_KRP_PARAM_X_INDEX (4) ++#define ICP_DSA_SIGN_KRP_PARAM_R_RESULT_INDEX (5) ++#define ICP_DSA_SIGN_KRP_PARAM_S_RESULT_INDEX (6) ++ ++/*DSA verify buffer index values*/ ++#define ICP_DSA_VERIFY_KRP_PARAM_DGST_INDEX (0) ++#define ICP_DSA_VERIFY_KRP_PARAM_PRIME_P_INDEX (1) ++#define ICP_DSA_VERIFY_KRP_PARAM_PRIME_Q_INDEX (2) ++#define ICP_DSA_VERIFY_KRP_PARAM_G_INDEX (3) ++#define ICP_DSA_VERIFY_KRP_PARAM_PUBKEY_INDEX (4) ++#define ICP_DSA_VERIFY_KRP_PARAM_SIG_R_INDEX (5) ++#define ICP_DSA_VERIFY_KRP_PARAM_SIG_S_INDEX (6) ++ ++/*DSA sign prime Q vs random number K size check values*/ ++#define DONT_RUN_LESS_THAN_CHECK (0) ++#define FAIL_A_IS_GREATER_THAN_B (1) ++#define FAIL_A_IS_EQUAL_TO_B (1) ++#define SUCCESS_A_IS_LESS_THAN_B (0) ++#define DSA_SIGN_RAND_GEN_VAL_CHECK_MAX_ITERATIONS (500) ++ ++/* We need to set a cryptokp success value just in case it is set or allocated ++ and not set to zero outside of this module */ ++#define CRYPTO_OP_SUCCESS (0) ++ ++/*Function to compute Diffie Hellman (DH) phase 1 or phase 2 key values*/ ++static int icp_ocfDrvDHComputeKey(struct cryptkop *krp); ++ ++/*Function to compute a Modular Exponentiation (Mod Exp)*/ ++static int icp_ocfDrvModExp(struct cryptkop *krp); ++ ++/*Function to compute a Mod Exp using the Chinease Remainder Theorem*/ ++static int icp_ocfDrvModExpCRT(struct cryptkop *krp); ++ ++/*Helper function to compute whether the first big number argument is less than ++ the second big number argument */ ++static int ++icp_ocfDrvCheckALessThanB(CpaFlatBuffer * pK, CpaFlatBuffer * pQ, int *doCheck); ++ ++/*Function to sign an input with DSA R and S keys*/ ++static int icp_ocfDrvDsaSign(struct cryptkop *krp); ++ ++/*Function to Verify a DSA buffer signature*/ ++static int icp_ocfDrvDsaVerify(struct cryptkop *krp); ++ ++/*Callback function for DH operation*/ ++static void ++icp_ocfDrvDhP1CallBack(void *callbackTag, ++ CpaStatus status, ++ void *pOpData, CpaFlatBuffer * pLocalOctetStringPV); ++ ++/*Callback function for ME operation*/ ++static void ++icp_ocfDrvModExpCallBack(void *callbackTag, ++ CpaStatus status, ++ void *pOpData, CpaFlatBuffer * pResult); ++ ++/*Callback function for ME CRT operation*/ ++static void ++icp_ocfDrvModExpCRTCallBack(void *callbackTag, ++ CpaStatus status, ++ void *pOpData, CpaFlatBuffer * pOutputData); ++ ++/*Callback function for DSA sign operation*/ ++static void ++icp_ocfDrvDsaRSSignCallBack(void *callbackTag, ++ CpaStatus status, ++ void *pOpData, ++ CpaBoolean protocolStatus, ++ CpaFlatBuffer * pR, CpaFlatBuffer * pS); ++ ++/*Callback function for DSA Verify operation*/ ++static void ++icp_ocfDrvDsaVerifyCallBack(void *callbackTag, ++ CpaStatus status, ++ void *pOpData, CpaBoolean verifyStatus); ++ ++/* Name : icp_ocfDrvPkeProcess ++ * ++ * Description : This function will choose which PKE process to follow ++ * based on the input arguments ++ */ ++int icp_ocfDrvPkeProcess(icp_device_t dev, struct cryptkop *krp, int hint) ++{ ++ CpaStatus lacStatus = CPA_STATUS_SUCCESS; ++ ++ if (NULL == krp) { ++ DPRINTK("%s(): Invalid input parameters, cryptkop = %p\n", ++ __FUNCTION__, krp); ++ return EINVAL; ++ } ++ ++ if (CPA_TRUE == icp_atomic_read(&icp_ocfDrvIsExiting)) { ++ krp->krp_status = ECANCELED; ++ return ECANCELED; ++ } ++ ++ switch (krp->krp_op) { ++ case CRK_DH_COMPUTE_KEY: ++ DPRINTK("%s() doing DH_COMPUTE_KEY\n", __FUNCTION__); ++ lacStatus = icp_ocfDrvDHComputeKey(krp); ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): icp_ocfDrvDHComputeKey failed " ++ "(%d).\n", __FUNCTION__, lacStatus); ++ krp->krp_status = ECANCELED; ++ return ECANCELED; ++ } ++ ++ break; ++ ++ case CRK_MOD_EXP: ++ DPRINTK("%s() doing MOD_EXP \n", __FUNCTION__); ++ lacStatus = icp_ocfDrvModExp(krp); ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): icp_ocfDrvModExp failed (%d).\n", ++ __FUNCTION__, lacStatus); ++ krp->krp_status = ECANCELED; ++ return ECANCELED; ++ } ++ ++ break; ++ ++ case CRK_MOD_EXP_CRT: ++ DPRINTK("%s() doing MOD_EXP_CRT \n", __FUNCTION__); ++ lacStatus = icp_ocfDrvModExpCRT(krp); ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): icp_ocfDrvModExpCRT " ++ "failed (%d).\n", __FUNCTION__, lacStatus); ++ krp->krp_status = ECANCELED; ++ return ECANCELED; ++ } ++ ++ break; ++ ++ case CRK_DSA_SIGN: ++ DPRINTK("%s() doing DSA_SIGN \n", __FUNCTION__); ++ lacStatus = icp_ocfDrvDsaSign(krp); ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): icp_ocfDrvDsaSign " ++ "failed (%d).\n", __FUNCTION__, lacStatus); ++ krp->krp_status = ECANCELED; ++ return ECANCELED; ++ } ++ ++ break; ++ ++ case CRK_DSA_VERIFY: ++ DPRINTK("%s() doing DSA_VERIFY \n", __FUNCTION__); ++ lacStatus = icp_ocfDrvDsaVerify(krp); ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): icp_ocfDrvDsaVerify " ++ "failed (%d).\n", __FUNCTION__, lacStatus); ++ krp->krp_status = ECANCELED; ++ return ECANCELED; ++ } ++ ++ break; ++ ++ default: ++ EPRINTK("%s(): Asymettric function not " ++ "supported (%d).\n", __FUNCTION__, krp->krp_op); ++ krp->krp_status = EOPNOTSUPP; ++ return EOPNOTSUPP; ++ } ++ ++ return ICP_OCF_DRV_STATUS_SUCCESS; ++} ++ ++/* Name : icp_ocfDrvSwapBytes ++ * ++ * Description : This function is used to swap the byte order of a buffer. ++ * It has been seen that in general we are passed little endian byte order ++ * buffers, but LAC only accepts big endian byte order buffers. ++ */ ++static void inline icp_ocfDrvSwapBytes(u_int8_t * num, u_int32_t buff_len_bytes) ++{ ++ ++ int i; ++ u_int8_t *end_ptr; ++ u_int8_t hold_val; ++ ++ end_ptr = num + (buff_len_bytes - 1); ++ buff_len_bytes = buff_len_bytes >> 1; ++ for (i = 0; i < buff_len_bytes; i++) { ++ hold_val = *num; ++ *num = *end_ptr; ++ num++; ++ *end_ptr = hold_val; ++ end_ptr--; ++ } ++} ++ ++/* Name : icp_ocfDrvDHComputeKey ++ * ++ * Description : This function will map Diffie Hellman calls from OCF ++ * to the LAC API. OCF uses this function for Diffie Hellman Phase1 and ++ * Phase2. LAC has a separate Diffie Hellman Phase2 call, however both phases ++ * break down to a modular exponentiation. ++ */ ++static int icp_ocfDrvDHComputeKey(struct cryptkop *krp) ++{ ++ CpaStatus lacStatus = CPA_STATUS_SUCCESS; ++ void *callbackTag = NULL; ++ CpaCyDhPhase1KeyGenOpData *pPhase1OpData = NULL; ++ CpaFlatBuffer *pLocalOctetStringPV = NULL; ++ uint32_t dh_prime_len_bytes = 0, dh_prime_len_bits = 0; ++ ++ /* Input checks - check prime is a multiple of 8 bits to allow for ++ allocation later */ ++ dh_prime_len_bits = ++ (krp->krp_param[ICP_DH_KRP_PARAM_PRIME_INDEX].crp_nbits); ++ ++ /* LAC can reject prime lengths based on prime key sizes, we just ++ need to make sure we can allocate space for the base and ++ exponent buffers correctly */ ++ if ((dh_prime_len_bits % NUM_BITS_IN_BYTE) != 0) { ++ APRINTK("%s(): Warning Prime number buffer size is not a " ++ "multiple of 8 bits\n", __FUNCTION__); ++ } ++ ++ /* Result storage space should be the same size as the prime as this ++ value can take up the same amount of storage space */ ++ if (dh_prime_len_bits != ++ krp->krp_param[ICP_DH_KRP_PARAM_RESULT_INDEX].crp_nbits) { ++ DPRINTK("%s(): Return Buffer must be the same size " ++ "as the Prime buffer\n", __FUNCTION__); ++ krp->krp_status = EINVAL; ++ return EINVAL; ++ } ++ /* Switch to size in bytes */ ++ BITS_TO_BYTES(dh_prime_len_bytes, dh_prime_len_bits); ++ ++ callbackTag = krp; ++ ++/*All allocations are set to ICP_M_NOWAIT due to the possibility of getting ++called in interrupt context*/ ++ pPhase1OpData = icp_kmem_cache_zalloc(drvDH_zone, ICP_M_NOWAIT); ++ if (NULL == pPhase1OpData) { ++ APRINTK("%s():Failed to get memory for key gen data\n", ++ __FUNCTION__); ++ krp->krp_status = ENOMEM; ++ return ENOMEM; ++ } ++ ++ pLocalOctetStringPV = ++ icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); ++ if (NULL == pLocalOctetStringPV) { ++ APRINTK("%s():Failed to get memory for pLocalOctetStringPV\n", ++ __FUNCTION__); ++ ICP_CACHE_FREE(drvDH_zone, pPhase1OpData); ++ krp->krp_status = ENOMEM; ++ return ENOMEM; ++ } ++ ++ /* Link parameters */ ++ pPhase1OpData->primeP.pData = ++ krp->krp_param[ICP_DH_KRP_PARAM_PRIME_INDEX].crp_p; ++ ++ pPhase1OpData->primeP.dataLenInBytes = dh_prime_len_bytes; ++ ++ icp_ocfDrvSwapBytes(pPhase1OpData->primeP.pData, dh_prime_len_bytes); ++ ++ pPhase1OpData->baseG.pData = ++ krp->krp_param[ICP_DH_KRP_PARAM_BASE_INDEX].crp_p; ++ ++ BITS_TO_BYTES(pPhase1OpData->baseG.dataLenInBytes, ++ krp->krp_param[ICP_DH_KRP_PARAM_BASE_INDEX].crp_nbits); ++ ++ icp_ocfDrvSwapBytes(pPhase1OpData->baseG.pData, ++ pPhase1OpData->baseG.dataLenInBytes); ++ ++ pPhase1OpData->privateValueX.pData = ++ krp->krp_param[ICP_DH_KRP_PARAM_PRIVATE_VALUE_INDEX].crp_p; ++ ++ BITS_TO_BYTES(pPhase1OpData->privateValueX.dataLenInBytes, ++ krp->krp_param[ICP_DH_KRP_PARAM_PRIVATE_VALUE_INDEX]. ++ crp_nbits); ++ ++ icp_ocfDrvSwapBytes(pPhase1OpData->privateValueX.pData, ++ pPhase1OpData->privateValueX.dataLenInBytes); ++ ++ /* Output parameters */ ++ pLocalOctetStringPV->pData = ++ krp->krp_param[ICP_DH_KRP_PARAM_RESULT_INDEX].crp_p; ++ ++ BITS_TO_BYTES(pLocalOctetStringPV->dataLenInBytes, ++ krp->krp_param[ICP_DH_KRP_PARAM_RESULT_INDEX].crp_nbits); ++ ++ lacStatus = cpaCyDhKeyGenPhase1(CPA_INSTANCE_HANDLE_SINGLE, ++ icp_ocfDrvDhP1CallBack, ++ callbackTag, pPhase1OpData, ++ pLocalOctetStringPV); ++ ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): DH Phase 1 Key Gen failed (%d).\n", ++ __FUNCTION__, lacStatus); ++ icp_ocfDrvFreeFlatBuffer(pLocalOctetStringPV); ++ ICP_CACHE_FREE(drvDH_zone, pPhase1OpData); ++ } ++ ++ return lacStatus; ++} ++ ++/* Name : icp_ocfDrvModExp ++ * ++ * Description : This function will map ordinary Modular Exponentiation calls ++ * from OCF to the LAC API. ++ * ++ */ ++static int icp_ocfDrvModExp(struct cryptkop *krp) ++{ ++ CpaStatus lacStatus = CPA_STATUS_SUCCESS; ++ void *callbackTag = NULL; ++ CpaCyLnModExpOpData *pModExpOpData = NULL; ++ CpaFlatBuffer *pResult = NULL; ++ ++ if ((krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX].crp_nbits % ++ NUM_BITS_IN_BYTE) != 0) { ++ DPRINTK("%s(): Warning - modulus buffer size (%d) is not a " ++ "multiple of 8 bits\n", __FUNCTION__, ++ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX]. ++ crp_nbits); ++ } ++ ++ /* Result storage space should be the same size as the prime as this ++ value can take up the same amount of storage space */ ++ if (krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX].crp_nbits > ++ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_RESULT_INDEX].crp_nbits) { ++ APRINTK("%s(): Return Buffer size must be the same or" ++ " greater than the Modulus buffer\n", __FUNCTION__); ++ krp->krp_status = EINVAL; ++ return EINVAL; ++ } ++ ++ callbackTag = krp; ++ ++ pModExpOpData = icp_kmem_cache_zalloc(drvLnModExp_zone, ICP_M_NOWAIT); ++ if (NULL == pModExpOpData) { ++ APRINTK("%s():Failed to get memory for key gen data\n", ++ __FUNCTION__); ++ krp->krp_status = ENOMEM; ++ return ENOMEM; ++ } ++ ++ pResult = icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); ++ if (NULL == pResult) { ++ APRINTK("%s():Failed to get memory for ModExp result\n", ++ __FUNCTION__); ++ ICP_CACHE_FREE(drvLnModExp_zone, pModExpOpData); ++ krp->krp_status = ENOMEM; ++ return ENOMEM; ++ } ++ ++ /* Link parameters */ ++ pModExpOpData->modulus.pData = ++ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX].crp_p; ++ BITS_TO_BYTES(pModExpOpData->modulus.dataLenInBytes, ++ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_MODULUS_INDEX]. ++ crp_nbits); ++ ++ icp_ocfDrvSwapBytes(pModExpOpData->modulus.pData, ++ pModExpOpData->modulus.dataLenInBytes); ++ ++ DPRINTK("%s : base (%d)\n", __FUNCTION__, krp-> ++ krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX].crp_nbits); ++ pModExpOpData->base.pData = ++ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX].crp_p; ++ BITS_TO_BYTES(pModExpOpData->base.dataLenInBytes, ++ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX]. ++ crp_nbits); ++ icp_ocfDrvSwapBytes(pModExpOpData->base.pData, ++ pModExpOpData->base.dataLenInBytes); ++ ++ pModExpOpData->exponent.pData = ++ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_EXPONENT_INDEX].crp_p; ++ BITS_TO_BYTES(pModExpOpData->exponent.dataLenInBytes, ++ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_EXPONENT_INDEX]. ++ crp_nbits); ++ ++ icp_ocfDrvSwapBytes(pModExpOpData->exponent.pData, ++ pModExpOpData->exponent.dataLenInBytes); ++ /* Output parameters */ ++ pResult->pData = ++ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_RESULT_INDEX].crp_p, ++ BITS_TO_BYTES(pResult->dataLenInBytes, ++ krp->krp_param[ICP_MOD_EXP_KRP_PARAM_RESULT_INDEX]. ++ crp_nbits); ++ ++ lacStatus = cpaCyLnModExp(CPA_INSTANCE_HANDLE_SINGLE, ++ icp_ocfDrvModExpCallBack, ++ callbackTag, pModExpOpData, pResult); ++ ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): Mod Exp Operation failed (%d).\n", ++ __FUNCTION__, lacStatus); ++ krp->krp_status = ECANCELED; ++ icp_ocfDrvFreeFlatBuffer(pResult); ++ ICP_CACHE_FREE(drvLnModExp_zone, pModExpOpData); ++ } ++ ++ return lacStatus; ++} ++ ++/* Name : icp_ocfDrvModExpCRT ++ * ++ * Description : This function will map ordinary Modular Exponentiation Chinese ++ * Remainder Theorem implementaion calls from OCF to the LAC API. ++ * ++ * Note : Mod Exp CRT for this driver is accelerated through LAC RSA type 2 ++ * decrypt operation. Therefore P and Q input values must always be prime ++ * numbers. Although basic primality checks are done in LAC, it is up to the ++ * user to do any correct prime number checking before passing the inputs. ++ */ ++static int icp_ocfDrvModExpCRT(struct cryptkop *krp) ++{ ++ CpaStatus lacStatus = CPA_STATUS_SUCCESS; ++ CpaCyRsaDecryptOpData *rsaDecryptOpData = NULL; ++ void *callbackTag = NULL; ++ CpaFlatBuffer *pOutputData = NULL; ++ ++ /*Parameter input checks are all done by LAC, no need to repeat ++ them here. */ ++ callbackTag = krp; ++ ++ rsaDecryptOpData = ++ icp_kmem_cache_zalloc(drvRSADecrypt_zone, ICP_M_NOWAIT); ++ if (NULL == rsaDecryptOpData) { ++ APRINTK("%s():Failed to get memory" ++ " for MOD EXP CRT Op data struct\n", __FUNCTION__); ++ krp->krp_status = ENOMEM; ++ return ENOMEM; ++ } ++ ++ rsaDecryptOpData->pRecipientPrivateKey ++ = icp_kmem_cache_zalloc(drvRSAPrivateKey_zone, ICP_M_NOWAIT); ++ if (NULL == rsaDecryptOpData->pRecipientPrivateKey) { ++ APRINTK("%s():Failed to get memory for MOD EXP CRT" ++ " private key values struct\n", __FUNCTION__); ++ ICP_CACHE_FREE(drvRSADecrypt_zone, rsaDecryptOpData); ++ krp->krp_status = ENOMEM; ++ return ENOMEM; ++ } ++ ++ rsaDecryptOpData->pRecipientPrivateKey-> ++ version = CPA_CY_RSA_VERSION_TWO_PRIME; ++ rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRepType = CPA_CY_RSA_PRIVATE_KEY_REP_TYPE_2; ++ ++ pOutputData = icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); ++ if (NULL == pOutputData) { ++ APRINTK("%s():Failed to get memory" ++ " for MOD EXP CRT output data\n", __FUNCTION__); ++ ICP_CACHE_FREE(drvRSAPrivateKey_zone, ++ rsaDecryptOpData->pRecipientPrivateKey); ++ ICP_CACHE_FREE(drvRSADecrypt_zone, rsaDecryptOpData); ++ krp->krp_status = ENOMEM; ++ return ENOMEM; ++ } ++ ++ rsaDecryptOpData->pRecipientPrivateKey-> ++ version = CPA_CY_RSA_VERSION_TWO_PRIME; ++ rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRepType = CPA_CY_RSA_PRIVATE_KEY_REP_TYPE_2; ++ ++ /* Link parameters */ ++ rsaDecryptOpData->inputData.pData = ++ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_I_INDEX].crp_p; ++ BITS_TO_BYTES(rsaDecryptOpData->inputData.dataLenInBytes, ++ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_I_INDEX]. ++ crp_nbits); ++ ++ icp_ocfDrvSwapBytes(rsaDecryptOpData->inputData.pData, ++ rsaDecryptOpData->inputData.dataLenInBytes); ++ ++ rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2.prime1P.pData = ++ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_P_INDEX].crp_p; ++ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2. ++ prime1P.dataLenInBytes, ++ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_P_INDEX]. ++ crp_nbits); ++ ++ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.prime1P.pData, ++ rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.prime1P.dataLenInBytes); ++ ++ rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2.prime2Q.pData = ++ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_Q_INDEX].crp_p; ++ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2. ++ prime2Q.dataLenInBytes, ++ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_PRIME_Q_INDEX]. ++ crp_nbits); ++ ++ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.prime2Q.pData, ++ rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.prime2Q.dataLenInBytes); ++ ++ rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.exponent1Dp.pData = ++ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DP_INDEX].crp_p; ++ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey->privateKeyRep2. ++ exponent1Dp.dataLenInBytes, ++ krp-> ++ krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DP_INDEX]. ++ crp_nbits); ++ ++ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.exponent1Dp.pData, ++ rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.exponent1Dp.dataLenInBytes); ++ ++ rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.exponent2Dq.pData = ++ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DQ_INDEX].crp_p; ++ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.exponent2Dq.dataLenInBytes, ++ krp-> ++ krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_EXPONENT_DQ_INDEX]. ++ crp_nbits); ++ ++ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.exponent2Dq.pData, ++ rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.exponent2Dq.dataLenInBytes); ++ ++ rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.coefficientQInv.pData = ++ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_COEFF_QINV_INDEX].crp_p; ++ BITS_TO_BYTES(rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.coefficientQInv.dataLenInBytes, ++ krp-> ++ krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_COEFF_QINV_INDEX]. ++ crp_nbits); ++ ++ icp_ocfDrvSwapBytes(rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.coefficientQInv.pData, ++ rsaDecryptOpData->pRecipientPrivateKey-> ++ privateKeyRep2.coefficientQInv.dataLenInBytes); ++ ++ /* Output Parameter */ ++ pOutputData->pData = ++ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_RESULT_INDEX].crp_p; ++ BITS_TO_BYTES(pOutputData->dataLenInBytes, ++ krp->krp_param[ICP_MOD_EXP_CRT_KRP_PARAM_RESULT_INDEX]. ++ crp_nbits); ++ ++ lacStatus = cpaCyRsaDecrypt(CPA_INSTANCE_HANDLE_SINGLE, ++ icp_ocfDrvModExpCRTCallBack, ++ callbackTag, rsaDecryptOpData, pOutputData); ++ ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): Mod Exp CRT Operation failed (%d).\n", ++ __FUNCTION__, lacStatus); ++ krp->krp_status = ECANCELED; ++ icp_ocfDrvFreeFlatBuffer(pOutputData); ++ ICP_CACHE_FREE(drvRSAPrivateKey_zone, ++ rsaDecryptOpData->pRecipientPrivateKey); ++ ICP_CACHE_FREE(drvRSADecrypt_zone, rsaDecryptOpData); ++ } ++ ++ return lacStatus; ++} ++ ++/* Name : icp_ocfDrvCheckALessThanB ++ * ++ * Description : This function will check whether the first argument is less ++ * than the second. It is used to check whether the DSA RS sign Random K ++ * value is less than the Prime Q value (as defined in the specification) ++ * ++ */ ++static int ++icp_ocfDrvCheckALessThanB(CpaFlatBuffer * pK, CpaFlatBuffer * pQ, int *doCheck) ++{ ++ ++ uint8_t *MSB_K = pK->pData; ++ uint8_t *MSB_Q = pQ->pData; ++ uint32_t buffer_lengths_in_bytes = pQ->dataLenInBytes; ++ ++ if (DONT_RUN_LESS_THAN_CHECK == *doCheck) { ++ return FAIL_A_IS_GREATER_THAN_B; ++ } ++ ++/*Check MSBs ++if A == B, check next MSB ++if A > B, return A_IS_GREATER_THAN_B ++if A < B, return A_IS_LESS_THAN_B (success) ++*/ ++ while (*MSB_K == *MSB_Q) { ++ MSB_K++; ++ MSB_Q++; ++ ++ buffer_lengths_in_bytes--; ++ if (0 == buffer_lengths_in_bytes) { ++ DPRINTK("%s() Buffers have equal value!!\n", ++ __FUNCTION__); ++ return FAIL_A_IS_EQUAL_TO_B; ++ } ++ ++ } ++ ++ if (*MSB_K < *MSB_Q) { ++ return SUCCESS_A_IS_LESS_THAN_B; ++ } else { ++ return FAIL_A_IS_GREATER_THAN_B; ++ } ++ ++} ++ ++/* Name : icp_ocfDrvDsaSign ++ * ++ * Description : This function will map DSA RS Sign from OCF to the LAC API. ++ * ++ * NOTE: From looking at OCF patch to OpenSSL and even the number of input ++ * parameters, OCF expects us to generate the random seed value. This value ++ * is generated and passed to LAC, however the number is discared in the ++ * callback and not returned to the user. ++ */ ++static int icp_ocfDrvDsaSign(struct cryptkop *krp) ++{ ++ CpaStatus lacStatus = CPA_STATUS_SUCCESS; ++ CpaCyDsaRSSignOpData *dsaRsSignOpData = NULL; ++ void *callbackTag = NULL; ++ CpaCyRandGenOpData randGenOpData; ++ int primeQSizeInBytes = 0; ++ int doCheck = 0; ++ CpaFlatBuffer randData; ++ CpaBoolean protocolStatus = CPA_FALSE; ++ CpaFlatBuffer *pR = NULL; ++ CpaFlatBuffer *pS = NULL; ++ ++ callbackTag = krp; ++ ++ BITS_TO_BYTES(primeQSizeInBytes, ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_Q_INDEX]. ++ crp_nbits); ++ ++ if (DSA_RS_SIGN_PRIMEQ_SIZE_IN_BYTES != primeQSizeInBytes) { ++ APRINTK("%s(): DSA PRIME Q size not equal to the " ++ "FIPS defined 20bytes, = %d\n", ++ __FUNCTION__, primeQSizeInBytes); ++ krp->krp_status = EDOM; ++ return EDOM; ++ } ++ ++ dsaRsSignOpData = ++ icp_kmem_cache_zalloc(drvDSARSSign_zone, ICP_M_NOWAIT); ++ if (NULL == dsaRsSignOpData) { ++ APRINTK("%s():Failed to get memory" ++ " for DSA RS Sign Op data struct\n", __FUNCTION__); ++ krp->krp_status = ENOMEM; ++ return ENOMEM; ++ } ++ ++ dsaRsSignOpData->K.pData = ++ icp_kmem_cache_alloc(drvDSARSSignKValue_zone, ICP_M_NOWAIT); ++ ++ if (NULL == dsaRsSignOpData->K.pData) { ++ APRINTK("%s():Failed to get memory" ++ " for DSA RS Sign Op Random value\n", __FUNCTION__); ++ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); ++ krp->krp_status = ENOMEM; ++ return ENOMEM; ++ } ++ ++ pR = icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); ++ if (NULL == pR) { ++ APRINTK("%s():Failed to get memory" ++ " for DSA signature R\n", __FUNCTION__); ++ ICP_CACHE_FREE(drvDSARSSignKValue_zone, ++ dsaRsSignOpData->K.pData); ++ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); ++ krp->krp_status = ENOMEM; ++ return ENOMEM; ++ } ++ ++ pS = icp_kmem_cache_zalloc(drvFlatBuffer_zone, ICP_M_NOWAIT); ++ if (NULL == pS) { ++ APRINTK("%s():Failed to get memory" ++ " for DSA signature S\n", __FUNCTION__); ++ icp_ocfDrvFreeFlatBuffer(pR); ++ ICP_CACHE_FREE(drvDSARSSignKValue_zone, ++ dsaRsSignOpData->K.pData); ++ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); ++ krp->krp_status = ENOMEM; ++ return ENOMEM; ++ } ++ ++ /*link prime number parameter for ease of processing */ ++ dsaRsSignOpData->P.pData = ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_P_INDEX].crp_p; ++ BITS_TO_BYTES(dsaRsSignOpData->P.dataLenInBytes, ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_P_INDEX]. ++ crp_nbits); ++ ++ icp_ocfDrvSwapBytes(dsaRsSignOpData->P.pData, ++ dsaRsSignOpData->P.dataLenInBytes); ++ ++ dsaRsSignOpData->Q.pData = ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_Q_INDEX].crp_p; ++ BITS_TO_BYTES(dsaRsSignOpData->Q.dataLenInBytes, ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_PRIME_Q_INDEX]. ++ crp_nbits); ++ ++ icp_ocfDrvSwapBytes(dsaRsSignOpData->Q.pData, ++ dsaRsSignOpData->Q.dataLenInBytes); ++ ++ /*generate random number with equal buffer size to Prime value Q, ++ but value less than Q */ ++ dsaRsSignOpData->K.dataLenInBytes = dsaRsSignOpData->Q.dataLenInBytes; ++ ++ randGenOpData.generateBits = CPA_TRUE; ++ randGenOpData.lenInBytes = dsaRsSignOpData->K.dataLenInBytes; ++ ++ icp_ocfDrvPtrAndLenToFlatBuffer(dsaRsSignOpData->K.pData, ++ dsaRsSignOpData->K.dataLenInBytes, ++ &randData); ++ ++ doCheck = 0; ++ while (icp_ocfDrvCheckALessThanB(&(dsaRsSignOpData->K), ++ &(dsaRsSignOpData->Q), &doCheck)) { ++ ++ if (CPA_STATUS_SUCCESS ++ != cpaCyRandGen(CPA_INSTANCE_HANDLE_SINGLE, ++ NULL, NULL, &randGenOpData, &randData)) { ++ APRINTK("%s(): ERROR - Failed to generate DSA RS Sign K" ++ "value\n", __FUNCTION__); ++ icp_ocfDrvFreeFlatBuffer(pS); ++ icp_ocfDrvFreeFlatBuffer(pR); ++ ICP_CACHE_FREE(drvDSARSSignKValue_zone, ++ dsaRsSignOpData->K.pData); ++ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); ++ krp->krp_status = EAGAIN; ++ return EAGAIN; ++ } ++ ++ doCheck++; ++ if (DSA_SIGN_RAND_GEN_VAL_CHECK_MAX_ITERATIONS == doCheck) { ++ APRINTK("%s(): ERROR - Failed to find DSA RS Sign K " ++ "value less than Q value\n", __FUNCTION__); ++ icp_ocfDrvFreeFlatBuffer(pS); ++ icp_ocfDrvFreeFlatBuffer(pR); ++ ICP_CACHE_FREE(drvDSARSSignKValue_zone, ++ dsaRsSignOpData->K.pData); ++ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); ++ krp->krp_status = EAGAIN; ++ return EAGAIN; ++ } ++ ++ } ++ /*Rand Data - no need to swap bytes for pK */ ++ ++ /* Link parameters */ ++ dsaRsSignOpData->G.pData = ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_G_INDEX].crp_p; ++ BITS_TO_BYTES(dsaRsSignOpData->G.dataLenInBytes, ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_G_INDEX].crp_nbits); ++ ++ icp_ocfDrvSwapBytes(dsaRsSignOpData->G.pData, ++ dsaRsSignOpData->G.dataLenInBytes); ++ ++ dsaRsSignOpData->X.pData = ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_X_INDEX].crp_p; ++ BITS_TO_BYTES(dsaRsSignOpData->X.dataLenInBytes, ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_X_INDEX].crp_nbits); ++ icp_ocfDrvSwapBytes(dsaRsSignOpData->X.pData, ++ dsaRsSignOpData->X.dataLenInBytes); ++ ++ /*OpenSSL dgst parameter is left in big endian byte order, ++ therefore no byte swap is required */ ++ dsaRsSignOpData->M.pData = ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_DGST_INDEX].crp_p; ++ BITS_TO_BYTES(dsaRsSignOpData->M.dataLenInBytes, ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_DGST_INDEX]. ++ crp_nbits); ++ ++ /* Output Parameters */ ++ pS->pData = krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_S_RESULT_INDEX].crp_p; ++ BITS_TO_BYTES(pS->dataLenInBytes, ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_S_RESULT_INDEX]. ++ crp_nbits); ++ ++ pR->pData = krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_R_RESULT_INDEX].crp_p; ++ BITS_TO_BYTES(pR->dataLenInBytes, ++ krp->krp_param[ICP_DSA_SIGN_KRP_PARAM_R_RESULT_INDEX]. ++ crp_nbits); ++ ++ lacStatus = cpaCyDsaSignRS(CPA_INSTANCE_HANDLE_SINGLE, ++ icp_ocfDrvDsaRSSignCallBack, ++ callbackTag, dsaRsSignOpData, ++ &protocolStatus, pR, pS); ++ ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): DSA RS Sign Operation failed (%d).\n", ++ __FUNCTION__, lacStatus); ++ krp->krp_status = ECANCELED; ++ icp_ocfDrvFreeFlatBuffer(pS); ++ icp_ocfDrvFreeFlatBuffer(pR); ++ ICP_CACHE_FREE(drvDSARSSignKValue_zone, ++ dsaRsSignOpData->K.pData); ++ ICP_CACHE_FREE(drvDSARSSign_zone, dsaRsSignOpData); ++ } ++ ++ return lacStatus; ++} ++ ++/* Name : icp_ocfDrvDsaVerify ++ * ++ * Description : This function will map DSA RS Verify from OCF to the LAC API. ++ * ++ */ ++static int icp_ocfDrvDsaVerify(struct cryptkop *krp) ++{ ++ CpaStatus lacStatus = CPA_STATUS_SUCCESS; ++ CpaCyDsaVerifyOpData *dsaVerifyOpData = NULL; ++ void *callbackTag = NULL; ++ CpaBoolean verifyStatus = CPA_FALSE; ++ ++ callbackTag = krp; ++ ++ dsaVerifyOpData = ++ icp_kmem_cache_zalloc(drvDSAVerify_zone, ICP_M_NOWAIT); ++ if (NULL == dsaVerifyOpData) { ++ APRINTK("%s():Failed to get memory" ++ " for DSA Verify Op data struct\n", __FUNCTION__); ++ krp->krp_status = ENOMEM; ++ return ENOMEM; ++ } ++ ++ /* Link parameters */ ++ dsaVerifyOpData->P.pData = ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PRIME_P_INDEX].crp_p; ++ BITS_TO_BYTES(dsaVerifyOpData->P.dataLenInBytes, ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PRIME_P_INDEX]. ++ crp_nbits); ++ icp_ocfDrvSwapBytes(dsaVerifyOpData->P.pData, ++ dsaVerifyOpData->P.dataLenInBytes); ++ ++ dsaVerifyOpData->Q.pData = ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PRIME_Q_INDEX].crp_p; ++ BITS_TO_BYTES(dsaVerifyOpData->Q.dataLenInBytes, ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PRIME_Q_INDEX]. ++ crp_nbits); ++ icp_ocfDrvSwapBytes(dsaVerifyOpData->Q.pData, ++ dsaVerifyOpData->Q.dataLenInBytes); ++ ++ dsaVerifyOpData->G.pData = ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_G_INDEX].crp_p; ++ BITS_TO_BYTES(dsaVerifyOpData->G.dataLenInBytes, ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_G_INDEX]. ++ crp_nbits); ++ icp_ocfDrvSwapBytes(dsaVerifyOpData->G.pData, ++ dsaVerifyOpData->G.dataLenInBytes); ++ ++ dsaVerifyOpData->Y.pData = ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PUBKEY_INDEX].crp_p; ++ BITS_TO_BYTES(dsaVerifyOpData->Y.dataLenInBytes, ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_PUBKEY_INDEX]. ++ crp_nbits); ++ icp_ocfDrvSwapBytes(dsaVerifyOpData->Y.pData, ++ dsaVerifyOpData->Y.dataLenInBytes); ++ ++ /*OpenSSL dgst parameter is left in big endian byte order, ++ therefore no byte swap is required */ ++ dsaVerifyOpData->M.pData = ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_DGST_INDEX].crp_p; ++ BITS_TO_BYTES(dsaVerifyOpData->M.dataLenInBytes, ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_DGST_INDEX]. ++ crp_nbits); ++ ++ dsaVerifyOpData->R.pData = ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_SIG_R_INDEX].crp_p; ++ BITS_TO_BYTES(dsaVerifyOpData->R.dataLenInBytes, ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_SIG_R_INDEX]. ++ crp_nbits); ++ icp_ocfDrvSwapBytes(dsaVerifyOpData->R.pData, ++ dsaVerifyOpData->R.dataLenInBytes); ++ ++ dsaVerifyOpData->S.pData = ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_SIG_S_INDEX].crp_p; ++ BITS_TO_BYTES(dsaVerifyOpData->S.dataLenInBytes, ++ krp->krp_param[ICP_DSA_VERIFY_KRP_PARAM_SIG_S_INDEX]. ++ crp_nbits); ++ icp_ocfDrvSwapBytes(dsaVerifyOpData->S.pData, ++ dsaVerifyOpData->S.dataLenInBytes); ++ ++ lacStatus = cpaCyDsaVerify(CPA_INSTANCE_HANDLE_SINGLE, ++ icp_ocfDrvDsaVerifyCallBack, ++ callbackTag, dsaVerifyOpData, &verifyStatus); ++ ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): DSA Verify Operation failed (%d).\n", ++ __FUNCTION__, lacStatus); ++ ICP_CACHE_FREE(drvDSAVerify_zone, dsaVerifyOpData); ++ krp->krp_status = ECANCELED; ++ } ++ ++ return lacStatus; ++} ++ ++/* Name : icp_ocfDrvDhP1Callback ++ * ++ * Description : When this function returns it signifies that the LAC ++ * component has completed the DH operation. ++ */ ++static void ++icp_ocfDrvDhP1CallBack(void *callbackTag, ++ CpaStatus status, ++ void *pOpData, CpaFlatBuffer * pLocalOctetStringPV) ++{ ++ struct cryptkop *krp = NULL; ++ CpaCyDhPhase1KeyGenOpData *pPhase1OpData = NULL; ++ ++ if (NULL == callbackTag) { ++ DPRINTK("%s(): Invalid input parameters - " ++ "callbackTag data is NULL\n", __FUNCTION__); ++ return; ++ } ++ krp = (struct cryptkop *)callbackTag; ++ ++ if (NULL == pOpData) { ++ DPRINTK("%s(): Invalid input parameters - " ++ "Operation Data is NULL\n", __FUNCTION__); ++ krp->krp_status = ECANCELED; ++ crypto_kdone(krp); ++ return; ++ } ++ pPhase1OpData = (CpaCyDhPhase1KeyGenOpData *) pOpData; ++ ++ if (NULL == pLocalOctetStringPV) { ++ DPRINTK("%s(): Invalid input parameters - " ++ "pLocalOctetStringPV Data is NULL\n", __FUNCTION__); ++ memset(pPhase1OpData, 0, sizeof(CpaCyDhPhase1KeyGenOpData)); ++ ICP_CACHE_FREE(drvDH_zone, pPhase1OpData); ++ krp->krp_status = ECANCELED; ++ crypto_kdone(krp); ++ return; ++ } ++ ++ if (CPA_STATUS_SUCCESS == status) { ++ krp->krp_status = CRYPTO_OP_SUCCESS; ++ } else { ++ APRINTK("%s(): Diffie Hellman Phase1 Key Gen failed - " ++ "Operation Status = %d\n", __FUNCTION__, status); ++ krp->krp_status = ECANCELED; ++ } ++ ++ icp_ocfDrvSwapBytes(pLocalOctetStringPV->pData, ++ pLocalOctetStringPV->dataLenInBytes); ++ ++ icp_ocfDrvFreeFlatBuffer(pLocalOctetStringPV); ++ memset(pPhase1OpData, 0, sizeof(CpaCyDhPhase1KeyGenOpData)); ++ ICP_CACHE_FREE(drvDH_zone, pPhase1OpData); ++ ++ crypto_kdone(krp); ++ ++ return; ++} ++ ++/* Name : icp_ocfDrvModExpCallBack ++ * ++ * Description : When this function returns it signifies that the LAC ++ * component has completed the Mod Exp operation. ++ */ ++static void ++icp_ocfDrvModExpCallBack(void *callbackTag, ++ CpaStatus status, ++ void *pOpdata, CpaFlatBuffer * pResult) ++{ ++ struct cryptkop *krp = NULL; ++ CpaCyLnModExpOpData *pLnModExpOpData = NULL; ++ ++ if (NULL == callbackTag) { ++ DPRINTK("%s(): Invalid input parameters - " ++ "callbackTag data is NULL\n", __FUNCTION__); ++ return; ++ } ++ krp = (struct cryptkop *)callbackTag; ++ ++ if (NULL == pOpdata) { ++ DPRINTK("%s(): Invalid Mod Exp input parameters - " ++ "Operation Data is NULL\n", __FUNCTION__); ++ krp->krp_status = ECANCELED; ++ crypto_kdone(krp); ++ return; ++ } ++ pLnModExpOpData = (CpaCyLnModExpOpData *) pOpdata; ++ ++ if (NULL == pResult) { ++ DPRINTK("%s(): Invalid input parameters - " ++ "pResult data is NULL\n", __FUNCTION__); ++ krp->krp_status = ECANCELED; ++ memset(pLnModExpOpData, 0, sizeof(CpaCyLnModExpOpData)); ++ ICP_CACHE_FREE(drvLnModExp_zone, pLnModExpOpData); ++ crypto_kdone(krp); ++ return; ++ } ++ ++ if (CPA_STATUS_SUCCESS == status) { ++ krp->krp_status = CRYPTO_OP_SUCCESS; ++ } else { ++ APRINTK("%s(): LAC Mod Exp Operation failed - " ++ "Operation Status = %d\n", __FUNCTION__, status); ++ krp->krp_status = ECANCELED; ++ } ++ ++ icp_ocfDrvSwapBytes(pResult->pData, pResult->dataLenInBytes); ++ ++ /*switch base size value back to original */ ++ if (pLnModExpOpData->base.pData == ++ (uint8_t *) & (krp-> ++ krp_param[ICP_MOD_EXP_KRP_PARAM_BASE_INDEX]. ++ crp_nbits)) { ++ *((uint32_t *) pLnModExpOpData->base.pData) = ++ ntohl(*((uint32_t *) pLnModExpOpData->base.pData)); ++ } ++ icp_ocfDrvFreeFlatBuffer(pResult); ++ memset(pLnModExpOpData, 0, sizeof(CpaCyLnModExpOpData)); ++ ICP_CACHE_FREE(drvLnModExp_zone, pLnModExpOpData); ++ ++ crypto_kdone(krp); ++ ++ return; ++ ++} ++ ++/* Name : icp_ocfDrvModExpCRTCallBack ++ * ++ * Description : When this function returns it signifies that the LAC ++ * component has completed the Mod Exp CRT operation. ++ */ ++static void ++icp_ocfDrvModExpCRTCallBack(void *callbackTag, ++ CpaStatus status, ++ void *pOpData, CpaFlatBuffer * pOutputData) ++{ ++ struct cryptkop *krp = NULL; ++ CpaCyRsaDecryptOpData *pDecryptData = NULL; ++ ++ if (NULL == callbackTag) { ++ DPRINTK("%s(): Invalid input parameters - " ++ "callbackTag data is NULL\n", __FUNCTION__); ++ return; ++ } ++ ++ krp = (struct cryptkop *)callbackTag; ++ ++ if (NULL == pOpData) { ++ DPRINTK("%s(): Invalid input parameters - " ++ "Operation Data is NULL\n", __FUNCTION__); ++ krp->krp_status = ECANCELED; ++ crypto_kdone(krp); ++ return; ++ } ++ pDecryptData = (CpaCyRsaDecryptOpData *) pOpData; ++ ++ if (NULL == pOutputData) { ++ DPRINTK("%s(): Invalid input parameter - " ++ "pOutputData is NULL\n", __FUNCTION__); ++ memset(pDecryptData->pRecipientPrivateKey, 0, ++ sizeof(CpaCyRsaPrivateKey)); ++ ICP_CACHE_FREE(drvRSAPrivateKey_zone, ++ pDecryptData->pRecipientPrivateKey); ++ memset(pDecryptData, 0, sizeof(CpaCyRsaDecryptOpData)); ++ ICP_CACHE_FREE(drvRSADecrypt_zone, pDecryptData); ++ krp->krp_status = ECANCELED; ++ crypto_kdone(krp); ++ return; ++ } ++ ++ if (CPA_STATUS_SUCCESS == status) { ++ krp->krp_status = CRYPTO_OP_SUCCESS; ++ } else { ++ APRINTK("%s(): LAC Mod Exp CRT operation failed - " ++ "Operation Status = %d\n", __FUNCTION__, status); ++ krp->krp_status = ECANCELED; ++ } ++ ++ icp_ocfDrvSwapBytes(pOutputData->pData, pOutputData->dataLenInBytes); ++ ++ icp_ocfDrvFreeFlatBuffer(pOutputData); ++ memset(pDecryptData->pRecipientPrivateKey, 0, ++ sizeof(CpaCyRsaPrivateKey)); ++ ICP_CACHE_FREE(drvRSAPrivateKey_zone, ++ pDecryptData->pRecipientPrivateKey); ++ memset(pDecryptData, 0, sizeof(CpaCyRsaDecryptOpData)); ++ ICP_CACHE_FREE(drvRSADecrypt_zone, pDecryptData); ++ ++ crypto_kdone(krp); ++ ++ return; ++} ++ ++/* Name : icp_ocfDrvDsaRSSignCallBack ++ * ++ * Description : When this function returns it signifies that the LAC ++ * component has completed the DSA RS sign operation. ++ */ ++static void ++icp_ocfDrvDsaRSSignCallBack(void *callbackTag, ++ CpaStatus status, ++ void *pOpData, ++ CpaBoolean protocolStatus, ++ CpaFlatBuffer * pR, CpaFlatBuffer * pS) ++{ ++ struct cryptkop *krp = NULL; ++ CpaCyDsaRSSignOpData *pSignData = NULL; ++ ++ if (NULL == callbackTag) { ++ DPRINTK("%s(): Invalid input parameters - " ++ "callbackTag data is NULL\n", __FUNCTION__); ++ return; ++ } ++ ++ krp = (struct cryptkop *)callbackTag; ++ ++ if (NULL == pOpData) { ++ DPRINTK("%s(): Invalid input parameters - " ++ "Operation Data is NULL\n", __FUNCTION__); ++ krp->krp_status = ECANCELED; ++ crypto_kdone(krp); ++ return; ++ } ++ pSignData = (CpaCyDsaRSSignOpData *) pOpData; ++ ++ if (NULL == pR) { ++ DPRINTK("%s(): Invalid input parameter - " ++ "pR sign is NULL\n", __FUNCTION__); ++ icp_ocfDrvFreeFlatBuffer(pS); ++ ICP_CACHE_FREE(drvDSARSSign_zone, pSignData); ++ krp->krp_status = ECANCELED; ++ crypto_kdone(krp); ++ return; ++ } ++ ++ if (NULL == pS) { ++ DPRINTK("%s(): Invalid input parameter - " ++ "pS sign is NULL\n", __FUNCTION__); ++ icp_ocfDrvFreeFlatBuffer(pR); ++ ICP_CACHE_FREE(drvDSARSSign_zone, pSignData); ++ krp->krp_status = ECANCELED; ++ crypto_kdone(krp); ++ return; ++ } ++ ++ if (CPA_STATUS_SUCCESS != status) { ++ APRINTK("%s(): LAC DSA RS Sign operation failed - " ++ "Operation Status = %d\n", __FUNCTION__, status); ++ krp->krp_status = ECANCELED; ++ } else { ++ krp->krp_status = CRYPTO_OP_SUCCESS; ++ ++ if (CPA_TRUE != protocolStatus) { ++ DPRINTK("%s(): LAC DSA RS Sign operation failed due " ++ "to protocol error\n", __FUNCTION__); ++ krp->krp_status = EIO; ++ } ++ } ++ ++ /* Swap bytes only when the callback status is successful and ++ protocolStatus is set to true */ ++ if (CPA_STATUS_SUCCESS == status && CPA_TRUE == protocolStatus) { ++ icp_ocfDrvSwapBytes(pR->pData, pR->dataLenInBytes); ++ icp_ocfDrvSwapBytes(pS->pData, pS->dataLenInBytes); ++ } ++ ++ icp_ocfDrvFreeFlatBuffer(pR); ++ icp_ocfDrvFreeFlatBuffer(pS); ++ memset(pSignData->K.pData, 0, pSignData->K.dataLenInBytes); ++ ICP_CACHE_FREE(drvDSARSSignKValue_zone, pSignData->K.pData); ++ memset(pSignData, 0, sizeof(CpaCyDsaRSSignOpData)); ++ ICP_CACHE_FREE(drvDSARSSign_zone, pSignData); ++ crypto_kdone(krp); ++ ++ return; ++} ++ ++/* Name : icp_ocfDrvDsaVerifyCallback ++ * ++ * Description : When this function returns it signifies that the LAC ++ * component has completed the DSA Verify operation. ++ */ ++static void ++icp_ocfDrvDsaVerifyCallBack(void *callbackTag, ++ CpaStatus status, ++ void *pOpData, CpaBoolean verifyStatus) ++{ ++ ++ struct cryptkop *krp = NULL; ++ CpaCyDsaVerifyOpData *pVerData = NULL; ++ ++ if (NULL == callbackTag) { ++ DPRINTK("%s(): Invalid input parameters - " ++ "callbackTag data is NULL\n", __FUNCTION__); ++ return; ++ } ++ ++ krp = (struct cryptkop *)callbackTag; ++ ++ if (NULL == pOpData) { ++ DPRINTK("%s(): Invalid input parameters - " ++ "Operation Data is NULL\n", __FUNCTION__); ++ krp->krp_status = ECANCELED; ++ crypto_kdone(krp); ++ return; ++ } ++ pVerData = (CpaCyDsaVerifyOpData *) pOpData; ++ ++ if (CPA_STATUS_SUCCESS != status) { ++ APRINTK("%s(): LAC DSA Verify operation failed - " ++ "Operation Status = %d\n", __FUNCTION__, status); ++ krp->krp_status = ECANCELED; ++ } else { ++ krp->krp_status = CRYPTO_OP_SUCCESS; ++ ++ if (CPA_TRUE != verifyStatus) { ++ DPRINTK("%s(): DSA signature invalid\n", __FUNCTION__); ++ krp->krp_status = EIO; ++ } ++ } ++ ++ /* Swap bytes only when the callback status is successful and ++ verifyStatus is set to true */ ++ /*Just swapping back the key values for now. Possibly all ++ swapped buffers need to be reverted */ ++ if (CPA_STATUS_SUCCESS == status && CPA_TRUE == verifyStatus) { ++ icp_ocfDrvSwapBytes(pVerData->R.pData, ++ pVerData->R.dataLenInBytes); ++ icp_ocfDrvSwapBytes(pVerData->S.pData, ++ pVerData->S.dataLenInBytes); ++ } ++ ++ memset(pVerData, 0, sizeof(CpaCyDsaVerifyOpData)); ++ ICP_CACHE_FREE(drvDSAVerify_zone, pVerData); ++ crypto_kdone(krp); ++ ++ return; ++} +diff -Nur linux-3.1.4.orig/crypto/ocf/ep80579/icp_common.c linux-3.1.4/crypto/ocf/ep80579/icp_common.c +--- linux-3.1.4.orig/crypto/ocf/ep80579/icp_common.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/ep80579/icp_common.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,773 @@ ++/************************************************************************* ++ * ++ * This file is provided under a dual BSD/GPLv2 license. When using or ++ * redistributing this file, you may do so under either license. ++ * ++ * GPL LICENSE SUMMARY ++ * ++ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ * The full GNU General Public License is included in this distribution ++ * in the file called LICENSE.GPL. ++ * ++ * Contact Information: ++ * Intel Corporation ++ * ++ * BSD LICENSE ++ * ++ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * * Neither the name of Intel Corporation nor the names of its ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * ++ * version: Security.L.1.0.2-229 ++ * ++ ***************************************************************************/ ++ ++/* ++ * An OCF module that uses Intel® QuickAssist Integrated Accelerator to do the ++ * crypto. ++ * ++ * This driver requires the ICP Access Library that is available from Intel in ++ * order to operate. ++ */ ++ ++#include "icp_ocf.h" ++ ++#define ICP_OCF_COMP_NAME "ICP_OCF" ++#define ICP_OCF_VER_MAIN (2) ++#define ICP_OCF_VER_MJR (1) ++#define ICP_OCF_VER_MNR (0) ++ ++#define MAX_DEREG_RETRIES (100) ++#define DEFAULT_DEREG_RETRIES (10) ++#define DEFAULT_DEREG_DELAY_IN_JIFFIES (10) ++ ++/* This defines the maximum number of sessions possible between OCF ++ and the OCF EP80579 Driver. If set to zero, there is no limit. */ ++#define DEFAULT_OCF_TO_DRV_MAX_SESSION_COUNT (0) ++#define NUM_SUPPORTED_CAPABILITIES (21) ++ ++/*Slab zone names*/ ++#define ICP_SESSION_DATA_NAME "icp_ocf.SesDat" ++#define ICP_OP_DATA_NAME "icp_ocf.OpDat" ++#define ICP_DH_NAME "icp_ocf.DH" ++#define ICP_MODEXP_NAME "icp_ocf.ModExp" ++#define ICP_RSA_DECRYPT_NAME "icp_ocf.RSAdec" ++#define ICP_RSA_PKEY_NAME "icp_ocf.RSApk" ++#define ICP_DSA_SIGN_NAME "icp_ocf.DSAsg" ++#define ICP_DSA_VER_NAME "icp_ocf.DSAver" ++#define ICP_RAND_VAL_NAME "icp_ocf.DSArnd" ++#define ICP_FLAT_BUFF_NAME "icp_ocf.FB" ++ ++/*Slabs zones*/ ++icp_kmem_cache drvSessionData_zone = NULL; ++icp_kmem_cache drvOpData_zone = NULL; ++icp_kmem_cache drvDH_zone = NULL; ++icp_kmem_cache drvLnModExp_zone = NULL; ++icp_kmem_cache drvRSADecrypt_zone = NULL; ++icp_kmem_cache drvRSAPrivateKey_zone = NULL; ++icp_kmem_cache drvDSARSSign_zone = NULL; ++icp_kmem_cache drvDSARSSignKValue_zone = NULL; ++icp_kmem_cache drvDSAVerify_zone = NULL; ++ ++/*Slab zones for flatbuffers and bufferlist*/ ++icp_kmem_cache drvFlatBuffer_zone = NULL; ++ ++static inline int icp_cache_null_check(void) ++{ ++ return (drvSessionData_zone && drvOpData_zone ++ && drvDH_zone && drvLnModExp_zone && drvRSADecrypt_zone ++ && drvRSAPrivateKey_zone && drvDSARSSign_zone ++ && drvDSARSSign_zone && drvDSARSSignKValue_zone ++ && drvDSAVerify_zone && drvFlatBuffer_zone); ++} ++ ++/*Function to free all allocated slab caches before exiting the module*/ ++static void icp_ocfDrvFreeCaches(void); ++ ++int32_t icp_ocfDrvDriverId = INVALID_DRIVER_ID; ++ ++/* Module parameter - gives the number of times LAC deregistration shall be ++ re-tried */ ++int num_dereg_retries = DEFAULT_DEREG_RETRIES; ++ ++/* Module parameter - gives the delay time in jiffies before a LAC session ++ shall be attempted to be deregistered again */ ++int dereg_retry_delay_in_jiffies = DEFAULT_DEREG_DELAY_IN_JIFFIES; ++ ++/* Module parameter - gives the maximum number of sessions possible between ++ OCF and the OCF EP80579 Driver. If set to zero, there is no limit.*/ ++int max_sessions = DEFAULT_OCF_TO_DRV_MAX_SESSION_COUNT; ++ ++/* This is set when the module is removed from the system, no further ++ processing can take place if this is set */ ++icp_atomic_t icp_ocfDrvIsExiting = ICP_ATOMIC_INIT(0); ++ ++/* This is used to show how many lac sessions were not deregistered*/ ++icp_atomic_t lac_session_failed_dereg_count = ICP_ATOMIC_INIT(0); ++ ++/* This is used to track the number of registered sessions between OCF and ++ * and the OCF EP80579 driver, when max_session is set to value other than ++ * zero. This ensures that the max_session set for the OCF and the driver ++ * is equal to the LAC registered sessions */ ++icp_atomic_t num_ocf_to_drv_registered_sessions = ICP_ATOMIC_INIT(0); ++ ++/* Head of linked list used to store session data */ ++icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead; ++icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead_FreeMemList; ++ ++icp_spinlock_t icp_ocfDrvSymSessInfoListSpinlock; ++ ++/*Below pointer is only used in linux, FreeBSD uses the name to ++create its own variable name*/ ++icp_workqueue *icp_ocfDrvFreeLacSessionWorkQ = NULL; ++ICP_WORKQUEUE_DEFINE_THREAD(icp_ocfDrvFreeLacSessionWorkQ); ++ ++struct icp_drvBuffListInfo defBuffListInfo; ++ ++/* Name : icp_ocfDrvInit ++ * ++ * Description : This function will register all the symmetric and asymmetric ++ * functionality that will be accelerated by the hardware. It will also ++ * get a unique driver ID from the OCF and initialise all slab caches ++ */ ++ICP_MODULE_INIT_FUNC(icp_ocfDrvInit) ++{ ++ int ocfStatus = 0; ++ ++ IPRINTK("=== %s ver %d.%d.%d ===\n", ICP_OCF_COMP_NAME, ++ ICP_OCF_VER_MAIN, ICP_OCF_VER_MJR, ICP_OCF_VER_MNR); ++ ++ if (MAX_DEREG_RETRIES < num_dereg_retries) { ++ EPRINTK("Session deregistration retry count set to greater " ++ "than %d", MAX_DEREG_RETRIES); ++ icp_module_return_code(EINVAL); ++ } ++ ++ /* Initialize and Start the Cryptographic component */ ++ if (CPA_STATUS_SUCCESS != ++ cpaCyStartInstance(CPA_INSTANCE_HANDLE_SINGLE)) { ++ EPRINTK("Failed to initialize and start the instance " ++ "of the Cryptographic component.\n"); ++ return icp_module_return_code(EINVAL); ++ } ++ ++ icp_spin_lock_init(&icp_ocfDrvSymSessInfoListSpinlock); ++ ++ /* Set the default size of BufferList to allocate */ ++ memset(&defBuffListInfo, 0, sizeof(struct icp_drvBuffListInfo)); ++ if (ICP_OCF_DRV_STATUS_SUCCESS != ++ icp_ocfDrvBufferListMemInfo(ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS, ++ &defBuffListInfo)) { ++ EPRINTK("Failed to get bufferlist memory info.\n"); ++ return icp_module_return_code(ENOMEM); ++ } ++ ++ /*Register OCF EP80579 Driver with OCF */ ++ icp_ocfDrvDriverId = ICP_CRYPTO_GET_DRIVERID(); ++ ++ if (icp_ocfDrvDriverId < 0) { ++ EPRINTK("%s : ICP driver failed to register with OCF!\n", ++ __FUNCTION__); ++ return icp_module_return_code(ENODEV); ++ } ++ ++ /*Create all the slab caches used by the OCF EP80579 Driver */ ++ drvSessionData_zone = ++ ICP_CACHE_CREATE(ICP_SESSION_DATA_NAME, struct icp_drvSessionData); ++ ++ /* ++ * Allocation of the OpData includes the allocation space for meta data. ++ * The memory after the opData structure is reserved for this meta data. ++ */ ++ drvOpData_zone = ++ icp_kmem_cache_create(ICP_OP_DATA_NAME, ++ sizeof(struct icp_drvOpData) + ++ defBuffListInfo.metaSize, ++ ICP_KERNEL_CACHE_ALIGN, ++ ICP_KERNEL_CACHE_NOINIT); ++ ++ drvDH_zone = ICP_CACHE_CREATE(ICP_DH_NAME, CpaCyDhPhase1KeyGenOpData); ++ ++ drvLnModExp_zone = ++ ICP_CACHE_CREATE(ICP_MODEXP_NAME, CpaCyLnModExpOpData); ++ ++ drvRSADecrypt_zone = ++ ICP_CACHE_CREATE(ICP_RSA_DECRYPT_NAME, CpaCyRsaDecryptOpData); ++ ++ drvRSAPrivateKey_zone = ++ ICP_CACHE_CREATE(ICP_RSA_PKEY_NAME, CpaCyRsaPrivateKey); ++ ++ drvDSARSSign_zone = ++ ICP_CACHE_CREATE(ICP_DSA_SIGN_NAME, CpaCyDsaRSSignOpData); ++ ++ /*too awkward to use a macro here */ ++ drvDSARSSignKValue_zone = ++ ICP_CACHE_CREATE(ICP_RAND_VAL_NAME, ++ DSA_RS_SIGN_PRIMEQ_SIZE_IN_BYTES); ++ ++ drvDSAVerify_zone = ++ ICP_CACHE_CREATE(ICP_DSA_VER_NAME, CpaCyDsaVerifyOpData); ++ ++ drvFlatBuffer_zone = ++ ICP_CACHE_CREATE(ICP_FLAT_BUFF_NAME, CpaFlatBuffer); ++ ++ if (0 == icp_cache_null_check()) { ++ icp_ocfDrvFreeCaches(); ++ EPRINTK("%s() line %d: Not enough memory!\n", ++ __FUNCTION__, __LINE__); ++ return ENOMEM; ++ } ++ ++ /* Register the ICP symmetric crypto support. */ ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_NULL_CBC, ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_DES_CBC, ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_3DES_CBC, ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_AES_CBC, ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_ARC4, ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_MD5, ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_MD5_HMAC, ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA1, ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA1_HMAC, ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_256, ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_256_HMAC, ++ ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_384, ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_384_HMAC, ++ ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_512, ocfStatus); ++ ICP_REG_SYM_WITH_OCF(icp_ocfDrvDriverId, CRYPTO_SHA2_512_HMAC, ++ ocfStatus); ++ ++ /* Register the ICP asymmetric algorithm support */ ++ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_DH_COMPUTE_KEY, ++ ocfStatus); ++ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_MOD_EXP, ocfStatus); ++ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_MOD_EXP_CRT, ocfStatus); ++ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_DSA_SIGN, ocfStatus); ++ ICP_REG_ASYM_WITH_OCF(icp_ocfDrvDriverId, CRK_DSA_VERIFY, ocfStatus); ++ ++ /* Register the ICP random number generator support */ ++ ICP_REG_RAND_WITH_OCF(icp_ocfDrvDriverId, ++ icp_ocfDrvReadRandom, NULL, ocfStatus); ++ ++ if (OCF_ZERO_FUNCTIONALITY_REGISTERED == ocfStatus) { ++ DPRINTK("%s: Failed to register any device capabilities\n", ++ __FUNCTION__); ++ icp_ocfDrvFreeCaches(); ++ icp_ocfDrvDriverId = INVALID_DRIVER_ID; ++ return icp_module_return_code(ECANCELED); ++ } ++ ++ DPRINTK("%s: Registered %d of %d device capabilities\n", ++ __FUNCTION__, ocfStatus, NUM_SUPPORTED_CAPABILITIES); ++ ++ /*Session data linked list used during module exit */ ++ ICP_INIT_LIST_HEAD(&icp_ocfDrvGlobalSymListHead); ++ ICP_INIT_LIST_HEAD(&icp_ocfDrvGlobalSymListHead_FreeMemList); ++ ++ ICP_WORKQUEUE_CREATE(icp_ocfDrvFreeLacSessionWorkQ, "icpwq"); ++ if (ICP_WORKQUEUE_NULL_CHECK(icp_ocfDrvFreeLacSessionWorkQ)) { ++ EPRINTK("%s: Failed to create single " ++ "thread workqueue\n", __FUNCTION__); ++ icp_ocfDrvFreeCaches(); ++ icp_ocfDrvDriverId = INVALID_DRIVER_ID; ++ return icp_module_return_code(ENOMEM); ++ } ++ ++ return icp_module_return_code(0); ++} ++ ++/* Name : icp_ocfDrvExit ++ * ++ * Description : This function will deregister all the symmetric sessions ++ * registered with the LAC component. It will also deregister all symmetric ++ * and asymmetric functionality that can be accelerated by the hardware via OCF ++ * and random number generation if it is enabled. ++ */ ++ICP_MODULE_EXIT_FUNC(icp_ocfDrvExit) ++{ ++ CpaStatus lacStatus = CPA_STATUS_SUCCESS; ++ struct icp_drvSessionData *sessionData = NULL; ++ struct icp_drvSessionData *tempSessionData = NULL; ++ int i, remaining_delay_time_in_jiffies = 0; ++ ++ /* For FreeBSD the invariant macro below makes function to return */ ++ /* with EBUSY value in the case of any session which has been regi- */ ++ /* stered with LAC not being deregistered. */ ++ /* The Linux implementation is empty since it is purely to compensate */ ++ /* for a limitation of the FreeBSD 7.1 Opencrypto framework. */ ++ ++ ICP_MODULE_EXIT_INV(); ++ ++ /* There is a possibility of a process or new session command being */ ++ /* sent before this variable is incremented. The aim of this variable */ ++ /* is to stop a loop of calls creating a deadlock situation which */ ++ /* would prevent the driver from exiting. */ ++ icp_atomic_set(&icp_ocfDrvIsExiting, 1); ++ ++ /*Existing sessions will be routed to another driver after these calls */ ++ crypto_unregister_all(icp_ocfDrvDriverId); ++ crypto_runregister_all(icp_ocfDrvDriverId); ++ ++ if (ICP_WORKQUEUE_NULL_CHECK(icp_ocfDrvFreeLacSessionWorkQ)) { ++ DPRINTK("%s: workqueue already " ++ "destroyed, therefore module exit " ++ " function already called. Exiting.\n", __FUNCTION__); ++ return ICP_MODULE_EXIT_FUNC_RETURN_VAL; ++ } ++ /*If any sessions are waiting to be deregistered, do that. This also ++ flushes the work queue */ ++ ICP_WORKQUEUE_DESTROY(icp_ocfDrvFreeLacSessionWorkQ); ++ ++ /*ENTER CRITICAL SECTION */ ++ icp_spin_lockbh_lock(&icp_ocfDrvSymSessInfoListSpinlock); ++ ++ ICP_LIST_FOR_EACH_ENTRY_SAFE(tempSessionData, sessionData, ++ &icp_ocfDrvGlobalSymListHead, listNode) { ++ for (i = 0; i < num_dereg_retries; i++) { ++ /*No harm if bad input - LAC will handle error cases */ ++ if (ICP_SESSION_RUNNING == tempSessionData->inUse) { ++ lacStatus = ++ cpaCySymRemoveSession ++ (CPA_INSTANCE_HANDLE_SINGLE, ++ tempSessionData->sessHandle); ++ if (CPA_STATUS_SUCCESS == lacStatus) { ++ /* Succesfully deregistered */ ++ break; ++ } else if (CPA_STATUS_RETRY != lacStatus) { ++ icp_atomic_inc ++ (&lac_session_failed_dereg_count); ++ break; ++ } ++ ++ /*schedule_timout returns the time left for completion if ++ * this task is set to TASK_INTERRUPTIBLE */ ++ remaining_delay_time_in_jiffies = ++ dereg_retry_delay_in_jiffies; ++ while (0 > remaining_delay_time_in_jiffies) { ++ remaining_delay_time_in_jiffies = ++ icp_schedule_timeout ++ (&icp_ocfDrvSymSessInfoListSpinlock, ++ remaining_delay_time_in_jiffies); ++ } ++ ++ DPRINTK ++ ("%s(): Retry %d to deregistrate the session\n", ++ __FUNCTION__, i); ++ } ++ } ++ ++ /*remove from current list */ ++ ICP_LIST_DEL(tempSessionData, listNode); ++ /*add to free mem linked list */ ++ ICP_LIST_ADD(tempSessionData, ++ &icp_ocfDrvGlobalSymListHead_FreeMemList, ++ listNode); ++ ++ } ++ ++ /*EXIT CRITICAL SECTION */ ++ icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock); ++ ++ /*set back to initial values */ ++ sessionData = NULL; ++ /*still have a reference in our list! */ ++ tempSessionData = NULL; ++ /*free memory */ ++ ++ ICP_LIST_FOR_EACH_ENTRY_SAFE(tempSessionData, sessionData, ++ &icp_ocfDrvGlobalSymListHead_FreeMemList, ++ listNode) { ++ ++ ICP_LIST_DEL(tempSessionData, listNode); ++ /* Free allocated CpaCySymSessionCtx */ ++ if (NULL != tempSessionData->sessHandle) { ++ icp_kfree(tempSessionData->sessHandle); ++ } ++ memset(tempSessionData, 0, sizeof(struct icp_drvSessionData)); ++ ICP_CACHE_FREE(drvSessionData_zone, tempSessionData); ++ } ++ ++ if (0 != icp_atomic_read(&lac_session_failed_dereg_count)) { ++ DPRINTK("%s(): %d LAC sessions were not deregistered " ++ "correctly. This is not a clean exit! \n", ++ __FUNCTION__, ++ icp_atomic_read(&lac_session_failed_dereg_count)); ++ } ++ ++ icp_ocfDrvFreeCaches(); ++ icp_ocfDrvDriverId = INVALID_DRIVER_ID; ++ ++ icp_spin_lock_destroy(&icp_ocfDrvSymSessInfoListSpinlock); ++ ++ /* Shutdown the Cryptographic component */ ++ lacStatus = cpaCyStopInstance(CPA_INSTANCE_HANDLE_SINGLE); ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ DPRINTK("%s(): Failed to stop instance of the " ++ "Cryptographic component.(status == %d)\n", ++ __FUNCTION__, lacStatus); ++ } ++ ++ return ICP_MODULE_EXIT_FUNC_RETURN_VAL; ++} ++ ++/* Name : icp_ocfDrvFreeCaches ++ * ++ * Description : This function deregisters all slab caches ++ */ ++static void icp_ocfDrvFreeCaches(void) ++{ ++ icp_atomic_set(&icp_ocfDrvIsExiting, 1); ++ ++ /*Sym Zones */ ++ ICP_CACHE_DESTROY(drvSessionData_zone); ++ ICP_CACHE_DESTROY(drvOpData_zone); ++ ++ /*Asym zones */ ++ ICP_CACHE_DESTROY(drvDH_zone); ++ ICP_CACHE_DESTROY(drvLnModExp_zone); ++ ICP_CACHE_DESTROY(drvRSADecrypt_zone); ++ ICP_CACHE_DESTROY(drvRSAPrivateKey_zone); ++ ICP_CACHE_DESTROY(drvDSARSSignKValue_zone); ++ ICP_CACHE_DESTROY(drvDSARSSign_zone); ++ ICP_CACHE_DESTROY(drvDSAVerify_zone); ++ ++ /*FlatBuffer and BufferList Zones */ ++ ICP_CACHE_DESTROY(drvFlatBuffer_zone); ++ ++} ++ ++/* Name : icp_ocfDrvDeregRetry ++ * ++ * Description : This function will try to farm the session deregistration ++ * off to a work queue. If it fails, nothing more can be done and it ++ * returns an error ++ */ ++int icp_ocfDrvDeregRetry(CpaCySymSessionCtx sessionToDeregister) ++{ ++ struct icp_ocfDrvFreeLacSession *workstore = NULL; ++ ++ DPRINTK("%s(): Retry - Deregistering session (%p)\n", ++ __FUNCTION__, sessionToDeregister); ++ ++ /*make sure the session is not available to be allocated during this ++ process */ ++ icp_atomic_inc(&lac_session_failed_dereg_count); ++ ++ /*Farm off to work queue */ ++ workstore = ++ icp_kmalloc(sizeof(struct icp_ocfDrvFreeLacSession), ICP_M_NOWAIT); ++ if (NULL == workstore) { ++ DPRINTK("%s(): unable to free session - no memory available " ++ "for work queue\n", __FUNCTION__); ++ return ENOMEM; ++ } ++ ++ workstore->sessionToDeregister = sessionToDeregister; ++ ++ icp_init_work(&(workstore->work), ++ icp_ocfDrvDeferedFreeLacSessionTaskFn, workstore); ++ ++ ICP_WORKQUEUE_ENQUEUE(icp_ocfDrvFreeLacSessionWorkQ, ++ &(workstore->work)); ++ ++ return ICP_OCF_DRV_STATUS_SUCCESS; ++ ++} ++ ++/* Name : icp_ocfDrvDeferedFreeLacSessionProcess ++ * ++ * Description : This function will retry (module input parameter) ++ * 'num_dereg_retries' times to deregister any symmetric session that recieves a ++ * CPA_STATUS_RETRY message from the LAC component. This function is run in ++ * Thread context because it is called from a worker thread ++ */ ++void icp_ocfDrvDeferedFreeLacSessionProcess(void *arg) ++{ ++ struct icp_ocfDrvFreeLacSession *workstore = NULL; ++ CpaCySymSessionCtx sessionToDeregister = NULL; ++ int i = 0; ++ int remaining_delay_time_in_jiffies = 0; ++ CpaStatus lacStatus = CPA_STATUS_SUCCESS; ++ ++ workstore = (struct icp_ocfDrvFreeLacSession *)arg; ++ if (NULL == workstore) { ++ DPRINTK("%s() function called with null parameter \n", ++ __FUNCTION__); ++ return; ++ } ++ ++ sessionToDeregister = workstore->sessionToDeregister; ++ icp_kfree(workstore); ++ ++ /*if exiting, give deregistration one more blast only */ ++ if (icp_atomic_read(&icp_ocfDrvIsExiting) == CPA_TRUE) { ++ lacStatus = cpaCySymRemoveSession(CPA_INSTANCE_HANDLE_SINGLE, ++ sessionToDeregister); ++ ++ if (lacStatus != CPA_STATUS_SUCCESS) { ++ DPRINTK("%s() Failed to Dereg LAC session %p " ++ "during module exit\n", __FUNCTION__, ++ sessionToDeregister); ++ return; ++ } ++ ++ icp_atomic_dec(&lac_session_failed_dereg_count); ++ return; ++ } ++ ++ for (i = 0; i <= num_dereg_retries; i++) { ++ lacStatus = cpaCySymRemoveSession(CPA_INSTANCE_HANDLE_SINGLE, ++ sessionToDeregister); ++ ++ if (lacStatus == CPA_STATUS_SUCCESS) { ++ icp_atomic_dec(&lac_session_failed_dereg_count); ++ return; ++ } ++ if (lacStatus != CPA_STATUS_RETRY) { ++ DPRINTK("%s() Failed to deregister session - lacStatus " ++ " = %d", __FUNCTION__, lacStatus); ++ break; ++ } ++ ++ /*schedule_timout returns the time left for completion if this ++ task is set to TASK_INTERRUPTIBLE */ ++ remaining_delay_time_in_jiffies = dereg_retry_delay_in_jiffies; ++ while (0 < remaining_delay_time_in_jiffies) { ++ remaining_delay_time_in_jiffies = ++ icp_schedule_timeout(NULL, ++ remaining_delay_time_in_jiffies); ++ } ++ ++ } ++ ++ DPRINTK("%s(): Unable to deregister session\n", __FUNCTION__); ++ DPRINTK("%s(): Number of unavailable LAC sessions = %d\n", __FUNCTION__, ++ icp_atomic_read(&lac_session_failed_dereg_count)); ++} ++ ++/* Name : icp_ocfDrvPtrAndLenToFlatBuffer ++ * ++ * Description : This function converts a "pointer and length" buffer ++ * structure to Fredericksburg Flat Buffer (CpaFlatBuffer) format. ++ * ++ * This function assumes that the data passed in are valid. ++ */ ++inline void ++icp_ocfDrvPtrAndLenToFlatBuffer(void *pData, uint32_t len, ++ CpaFlatBuffer * pFlatBuffer) ++{ ++ pFlatBuffer->pData = pData; ++ pFlatBuffer->dataLenInBytes = len; ++} ++ ++/* Name : icp_ocfDrvPtrAndLenToBufferList ++ * ++ * Description : This function converts a "pointer and length" buffer ++ * structure to Fredericksburg Scatter/Gather Buffer (CpaBufferList) format. ++ * ++ * This function assumes that the data passed in are valid. ++ */ ++inline void ++icp_ocfDrvPtrAndLenToBufferList(void *pDataIn, uint32_t length, ++ CpaBufferList * pBufferList) ++{ ++ pBufferList->numBuffers = 1; ++ pBufferList->pBuffers->pData = pDataIn; ++ pBufferList->pBuffers->dataLenInBytes = length; ++} ++ ++/* Name : icp_ocfDrvBufferListToPtrAndLen ++ * ++ * Description : This function converts Fredericksburg Scatter/Gather Buffer ++ * (CpaBufferList) format to a "pointer and length" buffer structure. ++ * ++ * This function assumes that the data passed in are valid. ++ */ ++inline void ++icp_ocfDrvBufferListToPtrAndLen(CpaBufferList * pBufferList, ++ void **ppDataOut, uint32_t * pLength) ++{ ++ *ppDataOut = pBufferList->pBuffers->pData; ++ *pLength = pBufferList->pBuffers->dataLenInBytes; ++} ++ ++/* Name : icp_ocfDrvBufferListMemInfo ++ * ++ * Description : This function will set the number of flat buffers in ++ * bufferlist, the size of memory to allocate for the pPrivateMetaData ++ * member of the CpaBufferList. ++ */ ++int ++icp_ocfDrvBufferListMemInfo(uint16_t numBuffers, ++ struct icp_drvBuffListInfo *buffListInfo) ++{ ++ buffListInfo->numBuffers = numBuffers; ++ ++ if (CPA_STATUS_SUCCESS != ++ cpaCyBufferListGetMetaSize(CPA_INSTANCE_HANDLE_SINGLE, ++ buffListInfo->numBuffers, ++ &(buffListInfo->metaSize))) { ++ EPRINTK("%s() Failed to get buffer list meta size.\n", ++ __FUNCTION__); ++ return ICP_OCF_DRV_STATUS_FAIL; ++ } ++ ++ return ICP_OCF_DRV_STATUS_SUCCESS; ++} ++ ++/* Name : icp_ocfDrvFreeFlatBuffer ++ * ++ * Description : This function will deallocate flat buffer. ++ */ ++inline void icp_ocfDrvFreeFlatBuffer(CpaFlatBuffer * pFlatBuffer) ++{ ++ if (pFlatBuffer != NULL) { ++ memset(pFlatBuffer, 0, sizeof(CpaFlatBuffer)); ++ ICP_CACHE_FREE(drvFlatBuffer_zone, pFlatBuffer); ++ } ++} ++ ++/* Name : icp_ocfDrvAllocMetaData ++ * ++ * Description : This function will allocate memory for the ++ * pPrivateMetaData member of CpaBufferList. ++ */ ++inline int ++icp_ocfDrvAllocMetaData(CpaBufferList * pBufferList, ++ struct icp_drvOpData *pOpData) ++{ ++ Cpa32U metaSize = 0; ++ ++ if (pBufferList->numBuffers <= ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) { ++ uint8_t *pOpDataStartAddr = (uint8_t *) pOpData; ++ ++ if (0 == defBuffListInfo.metaSize) { ++ pBufferList->pPrivateMetaData = NULL; ++ return ICP_OCF_DRV_STATUS_SUCCESS; ++ } ++ /* ++ * The meta data allocation has been included as part of the ++ * op data. It has been pre-allocated in memory just after the ++ * icp_drvOpData structure. ++ */ ++ pBufferList->pPrivateMetaData = (void *)(pOpDataStartAddr + ++ sizeof(struct ++ icp_drvOpData)); ++ } else { ++ if (CPA_STATUS_SUCCESS != ++ cpaCyBufferListGetMetaSize(CPA_INSTANCE_HANDLE_SINGLE, ++ pBufferList->numBuffers, ++ &metaSize)) { ++ EPRINTK("%s() Failed to get buffer list meta size.\n", ++ __FUNCTION__); ++ return ICP_OCF_DRV_STATUS_FAIL; ++ } ++ ++ if (0 == metaSize) { ++ pBufferList->pPrivateMetaData = NULL; ++ return ICP_OCF_DRV_STATUS_SUCCESS; ++ } ++ ++ pBufferList->pPrivateMetaData = ++ icp_kmalloc(metaSize, ICP_M_NOWAIT); ++ } ++ if (NULL == pBufferList->pPrivateMetaData) { ++ EPRINTK("%s() Failed to allocate pPrivateMetaData.\n", ++ __FUNCTION__); ++ return ICP_OCF_DRV_STATUS_FAIL; ++ } ++ ++ return ICP_OCF_DRV_STATUS_SUCCESS; ++} ++ ++/* Name : icp_ocfDrvFreeMetaData ++ * ++ * Description : This function will deallocate pPrivateMetaData memory. ++ */ ++inline void icp_ocfDrvFreeMetaData(CpaBufferList * pBufferList) ++{ ++ if (NULL == pBufferList->pPrivateMetaData) { ++ return; ++ } ++ ++ /* ++ * Only free the meta data if the BufferList has more than ++ * ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS number of buffers. ++ * Otherwise, the meta data shall be freed when the icp_drvOpData is ++ * freed. ++ */ ++ if (ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS < pBufferList->numBuffers) { ++ icp_kfree(pBufferList->pPrivateMetaData); ++ } ++} ++ ++/* Module declaration, init and exit functions */ ++ICP_DECLARE_MODULE(icp_ocf, icp_ocfDrvInit, icp_ocfDrvExit); ++ICP_MODULE_DESCRIPTION("OCF Driver for Intel Quick Assist crypto acceleration"); ++ICP_MODULE_VERSION(icp_ocf, ICP_OCF_VER_MJR); ++ICP_MODULE_LICENSE("Dual BSD/GPL"); ++ICP_MODULE_AUTHOR("Intel"); ++ ++/* Module parameters */ ++ICP_MODULE_PARAM_INT(icp_ocf, num_dereg_retries, ++ "Number of times to retry LAC Sym Session Deregistration. " ++ "Default 10, Max 100"); ++ICP_MODULE_PARAM_INT(icp_ocf, dereg_retry_delay_in_jiffies, "Delay in jiffies " ++ "(added to a schedule() function call) before a LAC Sym " ++ "Session Dereg is retried. Default 10"); ++ICP_MODULE_PARAM_INT(icp_ocf, max_sessions, ++ "This sets the maximum number of sessions " ++ "between OCF and this driver. If this value is set to zero," ++ "max session count checking is disabled. Default is zero(0)"); ++ ++/* Module dependencies */ ++#define MODULE_MIN_VER 1 ++#define CRYPTO_MAX_VER 3 ++#define LAC_MAX_VER 2 ++ ++ICP_MODULE_DEPEND(icp_ocf, crypto, MODULE_MIN_VER, MODULE_MIN_VER, ++ CRYPTO_MAX_VER); ++ICP_MODULE_DEPEND(icp_ocf, cryptodev, MODULE_MIN_VER, MODULE_MIN_VER, ++ CRYPTO_MAX_VER); ++ICP_MODULE_DEPEND(icp_ocf, icp_crypto, MODULE_MIN_VER, MODULE_MIN_VER, ++ LAC_MAX_VER); +diff -Nur linux-3.1.4.orig/crypto/ocf/ep80579/icp_ocf.h linux-3.1.4/crypto/ocf/ep80579/icp_ocf.h +--- linux-3.1.4.orig/crypto/ocf/ep80579/icp_ocf.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/ep80579/icp_ocf.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,376 @@ ++/*************************************************************************** ++ * ++ * This file is provided under a dual BSD/GPLv2 license. When using or ++ * redistributing this file, you may do so under either license. ++ * ++ * GPL LICENSE SUMMARY ++ * ++ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ * The full GNU General Public License is included in this distribution ++ * in the file called LICENSE.GPL. ++ * ++ * Contact Information: ++ * Intel Corporation ++ * ++ * BSD LICENSE ++ * ++ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * * Neither the name of Intel Corporation nor the names of its ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * ++ * version: Security.L.1.0.2-229 ++ * ++ ***************************************************************************/ ++ ++/* ++ * OCF driver header file for the Intel ICP processor. ++ */ ++ ++#ifndef ICP_OCF_H_ ++#define ICP_OCF_H_ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "icp_os.h" ++ ++#define NUM_BITS_IN_BYTE (8) ++#define NUM_BITS_IN_BYTE_MINUS_ONE (NUM_BITS_IN_BYTE -1) ++#define INVALID_DRIVER_ID (-1) ++#define RETURN_RAND_NUM_GEN_FAILED (-1) ++ ++/*This is the max block cipher initialisation vector*/ ++#define MAX_IV_LEN_IN_BYTES (20) ++/*This is used to check whether the OCF to this driver session limit has ++ been disabled*/ ++#define NO_OCF_TO_DRV_MAX_SESSIONS (0) ++ ++/*OCF values mapped here*/ ++#define ICP_SHA1_DIGEST_SIZE_IN_BYTES (SHA1_HASH_LEN) ++#define ICP_SHA256_DIGEST_SIZE_IN_BYTES (SHA2_256_HASH_LEN) ++#define ICP_SHA384_DIGEST_SIZE_IN_BYTES (SHA2_384_HASH_LEN) ++#define ICP_SHA512_DIGEST_SIZE_IN_BYTES (SHA2_512_HASH_LEN) ++#define ICP_MD5_DIGEST_SIZE_IN_BYTES (MD5_HASH_LEN) ++#define ARC4_COUNTER_LEN (ARC4_BLOCK_LEN) ++ ++#define OCF_REGISTRATION_STATUS_SUCCESS (0) ++#define OCF_ZERO_FUNCTIONALITY_REGISTERED (0) ++#define ICP_OCF_DRV_NO_CRYPTO_PROCESS_ERROR (0) ++#define ICP_OCF_DRV_STATUS_SUCCESS (0) ++#define ICP_OCF_DRV_STATUS_FAIL (1) ++ ++/*Turn on/off debug options*/ ++#define ICP_OCF_PRINT_DEBUG_MESSAGES (0) ++#define ICP_OCF_PRINT_KERN_ALERT (1) ++#define ICP_OCF_PRINT_KERN_ERRS (1) ++ ++#if ICP_OCF_PRINT_DEBUG_MESSAGES == 1 ++#define DPRINTK(args...) \ ++{ \ ++ ICP_IPRINTK(args); \ ++} ++ ++#else //ICP_OCF_PRINT_DEBUG_MESSAGES == 1 ++ ++#define DPRINTK(args...) ++ ++#endif //ICP_OCF_PRINT_DEBUG_MESSAGES == 1 ++ ++#if ICP_OCF_PRINT_KERN_ALERT == 1 ++#define APRINTK(args...) \ ++{ \ ++ ICP_APRINTK(args); \ ++} ++ ++#else //ICP_OCF_PRINT_KERN_ALERT == 1 ++ ++#define APRINTK(args...) ++ ++#endif //ICP_OCF_PRINT_KERN_ALERT == 1 ++ ++#if ICP_OCF_PRINT_KERN_ERRS == 1 ++#define EPRINTK(args...) \ ++{ \ ++ ICP_EPRINTK(args); \ ++} ++ ++#else //ICP_OCF_PRINT_KERN_ERRS == 1 ++ ++#define EPRINTK(args...) ++ ++#endif //ICP_OCF_PRINT_KERN_ERRS == 1 ++ ++#define IPRINTK(args...) \ ++{ \ ++ ICP_IPRINTK(args); \ ++} ++ ++/*DSA Prime Q size in bytes (as defined in the standard) */ ++#define DSA_RS_SIGN_PRIMEQ_SIZE_IN_BYTES (20) ++ ++#define BITS_TO_BYTES(bytes, bits) \ ++ bytes = (bits + NUM_BITS_IN_BYTE_MINUS_ONE) / NUM_BITS_IN_BYTE ++ ++typedef enum { ++ ICP_OCF_DRV_ALG_CIPHER = 0, ++ ICP_OCF_DRV_ALG_HASH ++} icp_ocf_drv_alg_type_t; ++ ++typedef ICP_LIST_HEAD(icp_drvSessionListHead_s, ++ icp_drvSessionData) icp_drvSessionListHead_t; ++ ++/*Values used to derisk chances of performs being called against ++deregistered sessions (for which the slab page has been reclaimed) ++This is not a fix - since page frames are reclaimed from a slab, one cannot ++rely on that memory not being re-used by another app.*/ ++typedef enum { ++ ICP_SESSION_INITIALISED = 0x5C5C5C, ++ ICP_SESSION_RUNNING = 0x005C00, ++ ICP_SESSION_DEREGISTERED = 0xC5C5C5 ++} usage_derisk; ++ ++/* This struct is required for deferred session ++ deregistration as a work queue function can ++ only have one argument*/ ++struct icp_ocfDrvFreeLacSession { ++ CpaCySymSessionCtx sessionToDeregister; ++ icp_workstruct work; ++}; ++ ++/* ++This is the OCF<->OCF_DRV session object: ++ ++1.listNode ++ The first member is a listNode. These session objects are added to a linked ++ list in order to make it easier to remove them all at session exit time. ++ ++2.inUse ++ The second member is used to give the session object state and derisk the ++ possibility of OCF batch calls executing against a deregistered session (as ++ described above). ++ ++3.sessHandle ++ The third member is a LAC<->OCF_DRV session handle (initialised with the first ++ perform request for that session). ++ ++4.lacSessCtx ++ The fourth is the LAC session context. All the parameters for this structure ++ are only known when the first perform request for this session occurs. That is ++ why the OCF EP80579 Driver only registers a new LAC session at perform time ++*/ ++struct icp_drvSessionData { ++ ICP_LIST_ENTRY(icp_drvSessionData) listNode; ++ usage_derisk inUse; ++ CpaCySymSessionCtx sessHandle; ++ CpaCySymSessionSetupData lacSessCtx; ++}; ++ ++/* These are all defined in icp_common.c */ ++extern icp_atomic_t lac_session_failed_dereg_count; ++extern icp_atomic_t icp_ocfDrvIsExiting; ++extern icp_atomic_t num_ocf_to_drv_registered_sessions; ++ ++extern int32_t icp_ocfDrvDriverId; ++ ++extern icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead; ++extern icp_drvSessionListHead_t icp_ocfDrvGlobalSymListHead_FreeMemList; ++extern icp_workqueue *icp_ocfDrvFreeLacSessionWorkQ; ++extern icp_spinlock_t icp_ocfDrvSymSessInfoListSpinlock; ++ ++/*Slab zones for symettric functionality, instantiated in icp_common.c*/ ++extern icp_kmem_cache drvSessionData_zone; ++extern icp_kmem_cache drvOpData_zone; ++ ++/*Slabs zones for asymettric functionality, instantiated in icp_common.c*/ ++extern icp_kmem_cache drvDH_zone; ++extern icp_kmem_cache drvLnModExp_zone; ++extern icp_kmem_cache drvRSADecrypt_zone; ++extern icp_kmem_cache drvRSAPrivateKey_zone; ++extern icp_kmem_cache drvDSARSSign_zone; ++extern icp_kmem_cache drvDSARSSignKValue_zone; ++extern icp_kmem_cache drvDSAVerify_zone; ++ ++/* Module parameters defined in icp_cpmmon.c*/ ++ ++/* Module parameters - gives the number of times LAC deregistration shall be ++ re-tried */ ++extern int num_dereg_retries; ++ ++/* Module parameter - gives the delay time in jiffies before a LAC session ++ shall be attempted to be deregistered again */ ++extern int dereg_retry_delay_in_jiffies; ++ ++/* Module parameter - gives the maximum number of sessions possible between ++ OCF and the OCF EP80579 Driver. If set to zero, there is no limit.*/ ++extern int max_sessions; ++ ++/*Slab zones for flatbuffers and bufferlist*/ ++extern icp_kmem_cache drvFlatBuffer_zone; ++ ++#define ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS (16) ++ ++struct icp_drvBuffListInfo { ++ Cpa16U numBuffers; ++ Cpa32U metaSize; ++ Cpa32U metaOffset; ++ Cpa32U buffListSize; ++}; ++ ++extern struct icp_drvBuffListInfo defBuffListInfo; ++ ++/* This struct is used to keep a reference to the relevant node in the list ++ of sessionData structs, to the buffer type required by OCF and to the OCF ++ provided crp struct that needs to be returned. All this info is needed in ++ the callback function.*/ ++struct icp_drvOpData { ++ CpaCySymOpData lacOpData; ++ uint32_t digestSizeInBytes; ++ struct cryptop *crp; ++ uint8_t bufferType; ++ uint8_t ivData[MAX_IV_LEN_IN_BYTES]; ++ uint16_t numBufferListArray; ++ CpaBufferList srcBuffer; ++ CpaFlatBuffer bufferListArray[ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS]; ++ CpaBoolean verifyResult; ++}; ++ ++/* Create a new session between OCF and this driver*/ ++int icp_ocfDrvNewSession(icp_device_t dev, uint32_t * sild, ++ struct cryptoini *cri); ++ ++/* Free a session between this driver and the Quick Assist Framework*/ ++int icp_ocfDrvFreeLACSession(icp_device_t dev, uint64_t sid); ++ ++/* Defer freeing a Quick Assist session*/ ++void icp_ocfDrvDeferedFreeLacSessionProcess(void *arg); ++ ++/* Process OCF cryptographic request for a symmetric algorithm*/ ++int icp_ocfDrvSymProcess(icp_device_t dev, struct cryptop *crp, int hint); ++ ++/* Process OCF cryptographic request for an asymmetric algorithm*/ ++int icp_ocfDrvPkeProcess(icp_device_t dev, struct cryptkop *krp, int hint); ++ ++/* Populate a buffer with random data*/ ++int icp_ocfDrvReadRandom(void *arg, uint32_t * buf, int maxwords); ++ ++/* Retry Quick Assist session deregistration*/ ++int icp_ocfDrvDeregRetry(CpaCySymSessionCtx sessionToDeregister); ++ ++/* Convert an OS scatter gather list to a CPA buffer list*/ ++int icp_ocfDrvPacketBuffToBufferList(icp_packet_buffer_t * pPacketBuffer, ++ CpaBufferList * bufferList); ++ ++/* Convert a CPA buffer list to an OS scatter gather list*/ ++int icp_ocfDrvBufferListToPacketBuff(CpaBufferList * bufferList, ++ icp_packet_buffer_t ** pPacketBuffer); ++ ++/* Get the number of buffers in an OS scatter gather list*/ ++uint16_t icp_ocfDrvGetPacketBuffFrags(icp_packet_buffer_t * pPacketBuffer); ++ ++/* Convert a single OS buffer to a CPA Flat Buffer*/ ++void icp_ocfDrvSinglePacketBuffToFlatBuffer(icp_packet_buffer_t * pPacketBuffer, ++ CpaFlatBuffer * pFlatBuffer); ++ ++/* Add pointer and length to a CPA Flat Buffer structure*/ ++void icp_ocfDrvPtrAndLenToFlatBuffer(void *pData, uint32_t len, ++ CpaFlatBuffer * pFlatBuffer); ++ ++/* Convert pointer and length values to a CPA buffer list*/ ++void icp_ocfDrvPtrAndLenToBufferList(void *pDataIn, uint32_t length, ++ CpaBufferList * pBufferList); ++ ++/* Convert a CPA buffer list to pointer and length values*/ ++void icp_ocfDrvBufferListToPtrAndLen(CpaBufferList * pBufferList, ++ void **ppDataOut, uint32_t * pLength); ++ ++/* Set the number of flat buffers in bufferlist and the size of memory ++ to allocate for the pPrivateMetaData member of the CpaBufferList.*/ ++int icp_ocfDrvBufferListMemInfo(uint16_t numBuffers, ++ struct icp_drvBuffListInfo *buffListInfo); ++ ++/* Find pointer position of the digest within an OS scatter gather list*/ ++uint8_t *icp_ocfDrvPacketBufferDigestPointerFind(struct icp_drvOpData ++ *drvOpData, ++ int offsetInBytes, ++ uint32_t digestSizeInBytes); ++ ++/*This top level function is used to find a pointer to where a digest is ++ stored/needs to be inserted. */ ++uint8_t *icp_ocfDrvDigestPointerFind(struct icp_drvOpData *drvOpData, ++ struct cryptodesc *crp_desc); ++ ++/* Free a CPA flat buffer*/ ++void icp_ocfDrvFreeFlatBuffer(CpaFlatBuffer * pFlatBuffer); ++ ++/* This function will allocate memory for the pPrivateMetaData ++ member of CpaBufferList. */ ++int icp_ocfDrvAllocMetaData(CpaBufferList * pBufferList, ++ struct icp_drvOpData *pOpData); ++ ++/* Free data allocated for the pPrivateMetaData ++ member of CpaBufferList.*/ ++void icp_ocfDrvFreeMetaData(CpaBufferList * pBufferList); ++ ++#define ICP_CACHE_CREATE(cache_ID, cache_name) \ ++ icp_kmem_cache_create(cache_ID, sizeof(cache_name),ICP_KERNEL_CACHE_ALIGN,\ ++ ICP_KERNEL_CACHE_NOINIT) ++ ++#define ICP_CACHE_FREE(args...) \ ++ icp_kmem_cache_free (args) ++ ++#define ICP_CACHE_DESTROY(slab_zone)\ ++{\ ++ if(NULL != slab_zone){\ ++ icp_kmem_cache_destroy(slab_zone);\ ++ slab_zone = NULL;\ ++ }\ ++} ++ ++#endif ++/* ICP_OCF_H_ */ +diff -Nur linux-3.1.4.orig/crypto/ocf/ep80579/icp_sym.c linux-3.1.4/crypto/ocf/ep80579/icp_sym.c +--- linux-3.1.4.orig/crypto/ocf/ep80579/icp_sym.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/ep80579/icp_sym.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,1153 @@ ++/*************************************************************************** ++ * ++ * This file is provided under a dual BSD/GPLv2 license. When using or ++ * redistributing this file, you may do so under either license. ++ * ++ * GPL LICENSE SUMMARY ++ * ++ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++ * The full GNU General Public License is included in this distribution ++ * in the file called LICENSE.GPL. ++ * ++ * Contact Information: ++ * Intel Corporation ++ * ++ * BSD LICENSE ++ * ++ * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * * Neither the name of Intel Corporation nor the names of its ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * ++ * version: Security.L.1.0.2-229 ++ * ++ ***************************************************************************/ ++/* ++ * An OCF module that uses the API for Intel® QuickAssist Technology to do the ++ * cryptography. ++ * ++ * This driver requires the ICP Access Library that is available from Intel in ++ * order to operate. ++ */ ++ ++#include "icp_ocf.h" ++ ++/*This is the call back function for all symmetric cryptographic processes. ++ Its main functionality is to free driver crypto operation structure and to ++ call back to OCF*/ ++static void ++icp_ocfDrvSymCallBack(void *callbackTag, ++ CpaStatus status, ++ const CpaCySymOp operationType, ++ void *pOpData, ++ CpaBufferList * pDstBuffer, CpaBoolean verifyResult); ++ ++/*This function is used to extract crypto processing information from the OCF ++ inputs, so as that it may be passed onto LAC*/ ++static int ++icp_ocfDrvProcessDataSetup(struct icp_drvOpData *drvOpData, ++ struct cryptodesc *crp_desc); ++ ++/*This function checks whether the crp_desc argument pertains to a digest or a ++ cipher operation*/ ++static int icp_ocfDrvAlgCheck(struct cryptodesc *crp_desc); ++ ++/*This function copies all the passed in session context information and stores ++ it in a LAC context structure*/ ++static int ++icp_ocfDrvAlgorithmSetup(struct cryptoini *cri, ++ CpaCySymSessionSetupData * lacSessCtx); ++ ++/*This function is used to free an OCF->OCF_DRV session object*/ ++static void icp_ocfDrvFreeOCFSession(struct icp_drvSessionData *sessionData); ++ ++/*max IOV buffs supported in a UIO structure*/ ++#define NUM_IOV_SUPPORTED (1) ++ ++/* Name : icp_ocfDrvSymCallBack ++ * ++ * Description : When this function returns it signifies that the LAC ++ * component has completed the relevant symmetric operation. ++ * ++ * Notes : The callbackTag is a pointer to an icp_drvOpData. This memory ++ * object was passed to LAC for the cryptographic processing and contains all ++ * the relevant information for cleaning up buffer handles etc. so that the ++ * OCF EP80579 Driver portion of this crypto operation can be fully completed. ++ */ ++static void ++icp_ocfDrvSymCallBack(void *callbackTag, ++ CpaStatus status, ++ const CpaCySymOp operationType, ++ void *pOpData, ++ CpaBufferList * pDstBuffer, CpaBoolean verifyResult) ++{ ++ struct cryptop *crp = NULL; ++ struct icp_drvOpData *temp_drvOpData = ++ (struct icp_drvOpData *)callbackTag; ++ uint64_t *tempBasePtr = NULL; ++ uint32_t tempLen = 0; ++ ++ if (NULL == temp_drvOpData) { ++ DPRINTK("%s(): The callback from the LAC component" ++ " has failed due to Null userOpaque data" ++ "(status == %d).\n", __FUNCTION__, status); ++ DPRINTK("%s(): Unable to call OCF back! \n", __FUNCTION__); ++ return; ++ } ++ ++ crp = temp_drvOpData->crp; ++ crp->crp_etype = ICP_OCF_DRV_NO_CRYPTO_PROCESS_ERROR; ++ ++ if (NULL == pOpData) { ++ DPRINTK("%s(): The callback from the LAC component" ++ " has failed due to Null Symmetric Op data" ++ "(status == %d).\n", __FUNCTION__, status); ++ crp->crp_etype = ECANCELED; ++ crypto_done(crp); ++ return; ++ } ++ ++ if (NULL == pDstBuffer) { ++ DPRINTK("%s(): The callback from the LAC component" ++ " has failed due to Null Dst Bufferlist data" ++ "(status == %d).\n", __FUNCTION__, status); ++ crp->crp_etype = ECANCELED; ++ crypto_done(crp); ++ return; ++ } ++ ++ if (CPA_STATUS_SUCCESS == status) { ++ ++ if (temp_drvOpData->bufferType == ICP_CRYPTO_F_PACKET_BUF) { ++ if (ICP_OCF_DRV_STATUS_SUCCESS != ++ icp_ocfDrvBufferListToPacketBuff(pDstBuffer, ++ (icp_packet_buffer_t ++ **) ++ & (crp->crp_buf))) { ++ EPRINTK("%s(): BufferList to SkBuff " ++ "conversion error.\n", __FUNCTION__); ++ crp->crp_etype = EPERM; ++ } ++ } else { ++ icp_ocfDrvBufferListToPtrAndLen(pDstBuffer, ++ (void **)&tempBasePtr, ++ &tempLen); ++ crp->crp_olen = (int)tempLen; ++ } ++ ++ } else { ++ DPRINTK("%s(): The callback from the LAC component has failed" ++ "(status == %d).\n", __FUNCTION__, status); ++ ++ crp->crp_etype = ECANCELED; ++ } ++ ++ if (temp_drvOpData->numBufferListArray > ++ ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) { ++ icp_kfree(pDstBuffer->pBuffers); ++ } ++ icp_ocfDrvFreeMetaData(pDstBuffer); ++ ICP_CACHE_FREE(drvOpData_zone, temp_drvOpData); ++ ++ /* Invoke the OCF callback function */ ++ crypto_done(crp); ++ ++ return; ++} ++ ++/* Name : icp_ocfDrvNewSession ++ * ++ * Description : This function will create a new Driver<->OCF session ++ * ++ * Notes : LAC session registration happens during the first perform call. ++ * That is the first time we know all information about a given session. ++ */ ++int icp_ocfDrvNewSession(icp_device_t dev, uint32_t * sid, ++ struct cryptoini *cri) ++{ ++ struct icp_drvSessionData *sessionData = NULL; ++ uint32_t delete_session = 0; ++ ++ /* The SID passed in should be our driver ID. We can return the */ ++ /* local ID (LID) which is a unique identifier which we can use */ ++ /* to differentiate between the encrypt/decrypt LAC session handles */ ++ if (NULL == sid) { ++ EPRINTK("%s(): Invalid input parameters - NULL sid.\n", ++ __FUNCTION__); ++ return EINVAL; ++ } ++ ++ if (NULL == cri) { ++ EPRINTK("%s(): Invalid input parameters - NULL cryptoini.\n", ++ __FUNCTION__); ++ return EINVAL; ++ } ++ ++ if (icp_ocfDrvDriverId != *sid) { ++ EPRINTK("%s(): Invalid input parameters - bad driver ID\n", ++ __FUNCTION__); ++ EPRINTK("\t sid = 0x08%p \n \t cri = 0x08%p \n", sid, cri); ++ return EINVAL; ++ } ++ ++ sessionData = icp_kmem_cache_zalloc(drvSessionData_zone, ICP_M_NOWAIT); ++ if (NULL == sessionData) { ++ DPRINTK("%s():No memory for Session Data\n", __FUNCTION__); ++ return ENOMEM; ++ } ++ ++ /*ENTER CRITICAL SECTION */ ++ icp_spin_lockbh_lock(&icp_ocfDrvSymSessInfoListSpinlock); ++ /*put this check in the spinlock so no new sessions can be added to the ++ linked list when we are exiting */ ++ if (CPA_TRUE == icp_atomic_read(&icp_ocfDrvIsExiting)) { ++ delete_session++; ++ ++ } else if (NO_OCF_TO_DRV_MAX_SESSIONS != max_sessions) { ++ if (icp_atomic_read(&num_ocf_to_drv_registered_sessions) >= ++ (max_sessions - ++ icp_atomic_read(&lac_session_failed_dereg_count))) { ++ delete_session++; ++ } else { ++ icp_atomic_inc(&num_ocf_to_drv_registered_sessions); ++ /* Add to session data linked list */ ++ ICP_LIST_ADD(sessionData, &icp_ocfDrvGlobalSymListHead, ++ listNode); ++ } ++ ++ } else if (NO_OCF_TO_DRV_MAX_SESSIONS == max_sessions) { ++ ICP_LIST_ADD(sessionData, &icp_ocfDrvGlobalSymListHead, ++ listNode); ++ } ++ ++ sessionData->inUse = ICP_SESSION_INITIALISED; ++ ++ /*EXIT CRITICAL SECTION */ ++ icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock); ++ ++ if (delete_session) { ++ DPRINTK("%s():No Session handles available\n", __FUNCTION__); ++ ICP_CACHE_FREE(drvSessionData_zone, sessionData); ++ return EPERM; ++ } ++ ++ if (ICP_OCF_DRV_STATUS_SUCCESS != ++ icp_ocfDrvAlgorithmSetup(cri, &(sessionData->lacSessCtx))) { ++ DPRINTK("%s():algorithm not supported\n", __FUNCTION__); ++ icp_ocfDrvFreeOCFSession(sessionData); ++ return EINVAL; ++ } ++ ++ if (cri->cri_next) { ++ if (cri->cri_next->cri_next != NULL) { ++ DPRINTK("%s():only two chained algorithms supported\n", ++ __FUNCTION__); ++ icp_ocfDrvFreeOCFSession(sessionData); ++ return EPERM; ++ } ++ ++ if (ICP_OCF_DRV_STATUS_SUCCESS != ++ icp_ocfDrvAlgorithmSetup(cri->cri_next, ++ &(sessionData->lacSessCtx))) { ++ DPRINTK("%s():second algorithm not supported\n", ++ __FUNCTION__); ++ icp_ocfDrvFreeOCFSession(sessionData); ++ return EINVAL; ++ } ++ ++ sessionData->lacSessCtx.symOperation = ++ CPA_CY_SYM_OP_ALGORITHM_CHAINING; ++ } ++ ++ *sid = (uint32_t) sessionData; ++ ++ return ICP_OCF_DRV_STATUS_SUCCESS; ++} ++ ++/* Name : icp_ocfDrvAlgorithmSetup ++ * ++ * Description : This function builds the session context data from the ++ * information supplied through OCF. Algorithm chain order and whether the ++ * session is Encrypt/Decrypt can only be found out at perform time however, so ++ * the session is registered with LAC at that time. ++ */ ++static int ++icp_ocfDrvAlgorithmSetup(struct cryptoini *cri, ++ CpaCySymSessionSetupData * lacSessCtx) ++{ ++ ++ lacSessCtx->sessionPriority = CPA_CY_PRIORITY_NORMAL; ++ ++ switch (cri->cri_alg) { ++ ++ case CRYPTO_NULL_CBC: ++ DPRINTK("%s(): NULL CBC\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; ++ lacSessCtx->cipherSetupData.cipherAlgorithm = ++ CPA_CY_SYM_CIPHER_NULL; ++ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = ++ cri->cri_klen / NUM_BITS_IN_BYTE; ++ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; ++ break; ++ ++ case CRYPTO_DES_CBC: ++ DPRINTK("%s(): DES CBC\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; ++ lacSessCtx->cipherSetupData.cipherAlgorithm = ++ CPA_CY_SYM_CIPHER_DES_CBC; ++ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = ++ cri->cri_klen / NUM_BITS_IN_BYTE; ++ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; ++ break; ++ ++ case CRYPTO_3DES_CBC: ++ DPRINTK("%s(): 3DES CBC\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; ++ lacSessCtx->cipherSetupData.cipherAlgorithm = ++ CPA_CY_SYM_CIPHER_3DES_CBC; ++ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = ++ cri->cri_klen / NUM_BITS_IN_BYTE; ++ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; ++ break; ++ ++ case CRYPTO_AES_CBC: ++ DPRINTK("%s(): AES CBC\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; ++ lacSessCtx->cipherSetupData.cipherAlgorithm = ++ CPA_CY_SYM_CIPHER_AES_CBC; ++ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = ++ cri->cri_klen / NUM_BITS_IN_BYTE; ++ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; ++ break; ++ ++ case CRYPTO_ARC4: ++ DPRINTK("%s(): ARC4\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_CIPHER; ++ lacSessCtx->cipherSetupData.cipherAlgorithm = ++ CPA_CY_SYM_CIPHER_ARC4; ++ lacSessCtx->cipherSetupData.cipherKeyLenInBytes = ++ cri->cri_klen / NUM_BITS_IN_BYTE; ++ lacSessCtx->cipherSetupData.pCipherKey = cri->cri_key; ++ break; ++ ++ case CRYPTO_SHA1: ++ DPRINTK("%s(): SHA1\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; ++ lacSessCtx->hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_SHA1; ++ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; ++ lacSessCtx->hashSetupData.digestResultLenInBytes = ++ (cri->cri_mlen ? ++ cri->cri_mlen : ICP_SHA1_DIGEST_SIZE_IN_BYTES); ++ ++ break; ++ ++ case CRYPTO_SHA1_HMAC: ++ DPRINTK("%s(): SHA1_HMAC\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; ++ lacSessCtx->hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_SHA1; ++ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; ++ lacSessCtx->hashSetupData.digestResultLenInBytes = ++ (cri->cri_mlen ? ++ cri->cri_mlen : ICP_SHA1_DIGEST_SIZE_IN_BYTES); ++ lacSessCtx->hashSetupData.authModeSetupData.authKey = ++ cri->cri_key; ++ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = ++ cri->cri_klen / NUM_BITS_IN_BYTE; ++ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; ++ ++ break; ++ ++ case CRYPTO_SHA2_256: ++ DPRINTK("%s(): SHA256\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; ++ lacSessCtx->hashSetupData.hashAlgorithm = ++ CPA_CY_SYM_HASH_SHA256; ++ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; ++ lacSessCtx->hashSetupData.digestResultLenInBytes = ++ (cri->cri_mlen ? ++ cri->cri_mlen : ICP_SHA256_DIGEST_SIZE_IN_BYTES); ++ ++ break; ++ ++ case CRYPTO_SHA2_256_HMAC: ++ DPRINTK("%s(): SHA256_HMAC\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; ++ lacSessCtx->hashSetupData.hashAlgorithm = ++ CPA_CY_SYM_HASH_SHA256; ++ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; ++ lacSessCtx->hashSetupData.digestResultLenInBytes = ++ (cri->cri_mlen ? ++ cri->cri_mlen : ICP_SHA256_DIGEST_SIZE_IN_BYTES); ++ lacSessCtx->hashSetupData.authModeSetupData.authKey = ++ cri->cri_key; ++ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = ++ cri->cri_klen / NUM_BITS_IN_BYTE; ++ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; ++ ++ break; ++ ++ case CRYPTO_SHA2_384: ++ DPRINTK("%s(): SHA384\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; ++ lacSessCtx->hashSetupData.hashAlgorithm = ++ CPA_CY_SYM_HASH_SHA384; ++ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; ++ lacSessCtx->hashSetupData.digestResultLenInBytes = ++ (cri->cri_mlen ? ++ cri->cri_mlen : ICP_SHA384_DIGEST_SIZE_IN_BYTES); ++ ++ break; ++ ++ case CRYPTO_SHA2_384_HMAC: ++ DPRINTK("%s(): SHA384_HMAC\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; ++ lacSessCtx->hashSetupData.hashAlgorithm = ++ CPA_CY_SYM_HASH_SHA384; ++ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; ++ lacSessCtx->hashSetupData.digestResultLenInBytes = ++ (cri->cri_mlen ? ++ cri->cri_mlen : ICP_SHA384_DIGEST_SIZE_IN_BYTES); ++ lacSessCtx->hashSetupData.authModeSetupData.authKey = ++ cri->cri_key; ++ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = ++ cri->cri_klen / NUM_BITS_IN_BYTE; ++ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; ++ ++ break; ++ ++ case CRYPTO_SHA2_512: ++ DPRINTK("%s(): SHA512\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; ++ lacSessCtx->hashSetupData.hashAlgorithm = ++ CPA_CY_SYM_HASH_SHA512; ++ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; ++ lacSessCtx->hashSetupData.digestResultLenInBytes = ++ (cri->cri_mlen ? ++ cri->cri_mlen : ICP_SHA512_DIGEST_SIZE_IN_BYTES); ++ ++ break; ++ ++ case CRYPTO_SHA2_512_HMAC: ++ DPRINTK("%s(): SHA512_HMAC\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; ++ lacSessCtx->hashSetupData.hashAlgorithm = ++ CPA_CY_SYM_HASH_SHA512; ++ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; ++ lacSessCtx->hashSetupData.digestResultLenInBytes = ++ (cri->cri_mlen ? ++ cri->cri_mlen : ICP_SHA512_DIGEST_SIZE_IN_BYTES); ++ lacSessCtx->hashSetupData.authModeSetupData.authKey = ++ cri->cri_key; ++ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = ++ cri->cri_klen / NUM_BITS_IN_BYTE; ++ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; ++ ++ break; ++ ++ case CRYPTO_MD5: ++ DPRINTK("%s(): MD5\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; ++ lacSessCtx->hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_MD5; ++ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_PLAIN; ++ lacSessCtx->hashSetupData.digestResultLenInBytes = ++ (cri->cri_mlen ? ++ cri->cri_mlen : ICP_MD5_DIGEST_SIZE_IN_BYTES); ++ ++ break; ++ ++ case CRYPTO_MD5_HMAC: ++ DPRINTK("%s(): MD5_HMAC\n", __FUNCTION__); ++ lacSessCtx->symOperation = CPA_CY_SYM_OP_HASH; ++ lacSessCtx->hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_MD5; ++ lacSessCtx->hashSetupData.hashMode = CPA_CY_SYM_HASH_MODE_AUTH; ++ lacSessCtx->hashSetupData.digestResultLenInBytes = ++ (cri->cri_mlen ? ++ cri->cri_mlen : ICP_MD5_DIGEST_SIZE_IN_BYTES); ++ lacSessCtx->hashSetupData.authModeSetupData.authKey = ++ cri->cri_key; ++ lacSessCtx->hashSetupData.authModeSetupData.authKeyLenInBytes = ++ cri->cri_klen / NUM_BITS_IN_BYTE; ++ lacSessCtx->hashSetupData.authModeSetupData.aadLenInBytes = 0; ++ ++ break; ++ ++ default: ++ DPRINTK("%s(): ALG Setup FAIL\n", __FUNCTION__); ++ return ICP_OCF_DRV_STATUS_FAIL; ++ } ++ ++ return ICP_OCF_DRV_STATUS_SUCCESS; ++} ++ ++/* Name : icp_ocfDrvFreeOCFSession ++ * ++ * Description : This function deletes all existing Session data representing ++ * the Cryptographic session established between OCF and this driver. This ++ * also includes freeing the memory allocated for the session context. The ++ * session object is also removed from the session linked list. ++ */ ++static void icp_ocfDrvFreeOCFSession(struct icp_drvSessionData *sessionData) ++{ ++ ++ sessionData->inUse = ICP_SESSION_DEREGISTERED; ++ ++ /*ENTER CRITICAL SECTION */ ++ icp_spin_lockbh_lock(&icp_ocfDrvSymSessInfoListSpinlock); ++ ++ if (CPA_TRUE == icp_atomic_read(&icp_ocfDrvIsExiting)) { ++ /*If the Driver is exiting, allow that process to ++ handle any deletions */ ++ /*EXIT CRITICAL SECTION */ ++ icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock); ++ return; ++ } ++ ++ icp_atomic_dec(&num_ocf_to_drv_registered_sessions); ++ ++ ICP_LIST_DEL(sessionData, listNode); ++ ++ /*EXIT CRITICAL SECTION */ ++ icp_spin_lockbh_unlock(&icp_ocfDrvSymSessInfoListSpinlock); ++ ++ if (NULL != sessionData->sessHandle) { ++ icp_kfree(sessionData->sessHandle); ++ } ++ ICP_CACHE_FREE(drvSessionData_zone, sessionData); ++} ++ ++/* Name : icp_ocfDrvFreeLACSession ++ * ++ * Description : This attempts to deregister a LAC session. If it fails, the ++ * deregistation retry function is called. ++ */ ++int icp_ocfDrvFreeLACSession(icp_device_t dev, uint64_t sid) ++{ ++ CpaCySymSessionCtx sessionToDeregister = NULL; ++ struct icp_drvSessionData *sessionData = NULL; ++ CpaStatus lacStatus = CPA_STATUS_SUCCESS; ++ int retval = 0; ++ ++ sessionData = (struct icp_drvSessionData *)CRYPTO_SESID2LID(sid); ++ if (NULL == sessionData) { ++ EPRINTK("%s(): OCF Free session called with Null Session ID.\n", ++ __FUNCTION__); ++ return EINVAL; ++ } ++ ++ sessionToDeregister = sessionData->sessHandle; ++ ++ if ((ICP_SESSION_INITIALISED != sessionData->inUse) && ++ (ICP_SESSION_RUNNING != sessionData->inUse) && ++ (ICP_SESSION_DEREGISTERED != sessionData->inUse)) { ++ DPRINTK("%s() Session not initialised.\n", __FUNCTION__); ++ return EINVAL; ++ } ++ ++ if (ICP_SESSION_RUNNING == sessionData->inUse) { ++ lacStatus = cpaCySymRemoveSession(CPA_INSTANCE_HANDLE_SINGLE, ++ sessionToDeregister); ++ if (CPA_STATUS_RETRY == lacStatus) { ++ if (ICP_OCF_DRV_STATUS_SUCCESS != ++ icp_ocfDrvDeregRetry(&sessionToDeregister)) { ++ /* the retry function increments the ++ dereg failed count */ ++ DPRINTK("%s(): LAC failed to deregister the " ++ "session. (localSessionId= %p)\n", ++ __FUNCTION__, sessionToDeregister); ++ retval = EPERM; ++ } ++ ++ } else if (CPA_STATUS_SUCCESS != lacStatus) { ++ DPRINTK("%s(): LAC failed to deregister the session. " ++ "localSessionId= %p, lacStatus = %d\n", ++ __FUNCTION__, sessionToDeregister, lacStatus); ++ icp_atomic_inc(&lac_session_failed_dereg_count); ++ retval = EPERM; ++ } ++ } else { ++ DPRINTK("%s() Session not registered with LAC.\n", ++ __FUNCTION__); ++ } ++ ++ icp_ocfDrvFreeOCFSession(sessionData); ++ return retval; ++ ++} ++ ++/* Name : icp_ocfDrvAlgCheck ++ * ++ * Description : This function checks whether the cryptodesc argument pertains ++ * to a sym or hash function ++ */ ++static int icp_ocfDrvAlgCheck(struct cryptodesc *crp_desc) ++{ ++ ++ if (crp_desc->crd_alg == CRYPTO_3DES_CBC || ++ crp_desc->crd_alg == CRYPTO_AES_CBC || ++ crp_desc->crd_alg == CRYPTO_DES_CBC || ++ crp_desc->crd_alg == CRYPTO_NULL_CBC || ++ crp_desc->crd_alg == CRYPTO_ARC4) { ++ return ICP_OCF_DRV_ALG_CIPHER; ++ } ++ ++ return ICP_OCF_DRV_ALG_HASH; ++} ++ ++/* Name : icp_ocfDrvSymProcess ++ * ++ * Description : This function will map symmetric functionality calls from OCF ++ * to the LAC API. It will also allocate memory to store the session context. ++ * ++ * Notes: If it is the first perform call for a given session, then a LAC ++ * session is registered. After the session is registered, no checks as ++ * to whether session paramaters have changed (e.g. alg chain order) are ++ * done. ++ */ ++int icp_ocfDrvSymProcess(icp_device_t dev, struct cryptop *crp, int hint) ++{ ++ struct icp_drvSessionData *sessionData = NULL; ++ struct icp_drvOpData *drvOpData = NULL; ++ CpaStatus lacStatus = CPA_STATUS_SUCCESS; ++ Cpa32U sessionCtxSizeInBytes = 0; ++ ++ if (NULL == crp) { ++ DPRINTK("%s(): Invalid input parameters, cryptop is NULL\n", ++ __FUNCTION__); ++ return EINVAL; ++ } ++ ++ if (NULL == crp->crp_desc) { ++ DPRINTK("%s(): Invalid input parameters, no crp_desc attached " ++ "to crp\n", __FUNCTION__); ++ crp->crp_etype = EINVAL; ++ return EINVAL; ++ } ++ ++ if (NULL == crp->crp_buf) { ++ DPRINTK("%s(): Invalid input parameters, no buffer attached " ++ "to crp\n", __FUNCTION__); ++ crp->crp_etype = EINVAL; ++ return EINVAL; ++ } ++ ++ if (CPA_TRUE == icp_atomic_read(&icp_ocfDrvIsExiting)) { ++ crp->crp_etype = EFAULT; ++ return EFAULT; ++ } ++ ++ sessionData = (struct icp_drvSessionData *) ++ (CRYPTO_SESID2LID(crp->crp_sid)); ++ if (NULL == sessionData) { ++ DPRINTK("%s(): Invalid input parameters, Null Session ID \n", ++ __FUNCTION__); ++ crp->crp_etype = EINVAL; ++ return EINVAL; ++ } ++ ++/*If we get a request against a deregisted session, cancel operation*/ ++ if (ICP_SESSION_DEREGISTERED == sessionData->inUse) { ++ DPRINTK("%s(): Session ID %d was deregistered \n", ++ __FUNCTION__, (int)(CRYPTO_SESID2LID(crp->crp_sid))); ++ crp->crp_etype = EFAULT; ++ return EFAULT; ++ } ++ ++/*If none of the session states are set, then the session structure was either ++ not initialised properly or we are reading from a freed memory area (possible ++ due to OCF batch mode not removing queued requests against deregistered ++ sessions*/ ++ if (ICP_SESSION_INITIALISED != sessionData->inUse && ++ ICP_SESSION_RUNNING != sessionData->inUse) { ++ DPRINTK("%s(): Session - ID %d - not properly initialised or " ++ "memory freed back to the kernel \n", ++ __FUNCTION__, (int)(CRYPTO_SESID2LID(crp->crp_sid))); ++ crp->crp_etype = EINVAL; ++ return EINVAL; ++ } ++ ++ /*For the below checks, remember error checking is already done in LAC. ++ We're not validating inputs subsequent to registration */ ++ if (sessionData->inUse == ICP_SESSION_INITIALISED) { ++ DPRINTK("%s(): Initialising session\n", __FUNCTION__); ++ ++ if (NULL != crp->crp_desc->crd_next) { ++ if (ICP_OCF_DRV_ALG_CIPHER == ++ icp_ocfDrvAlgCheck(crp->crp_desc)) { ++ ++ sessionData->lacSessCtx.algChainOrder = ++ CPA_CY_SYM_ALG_CHAIN_ORDER_CIPHER_THEN_HASH; ++ ++ if (crp->crp_desc->crd_flags & CRD_F_ENCRYPT) { ++ sessionData->lacSessCtx.cipherSetupData. ++ cipherDirection = ++ CPA_CY_SYM_CIPHER_DIRECTION_ENCRYPT; ++ } else { ++ sessionData->lacSessCtx.cipherSetupData. ++ cipherDirection = ++ CPA_CY_SYM_CIPHER_DIRECTION_DECRYPT; ++ } ++ } else { ++ sessionData->lacSessCtx.algChainOrder = ++ CPA_CY_SYM_ALG_CHAIN_ORDER_HASH_THEN_CIPHER; ++ ++ if (crp->crp_desc->crd_next->crd_flags & ++ CRD_F_ENCRYPT) { ++ sessionData->lacSessCtx.cipherSetupData. ++ cipherDirection = ++ CPA_CY_SYM_CIPHER_DIRECTION_ENCRYPT; ++ } else { ++ sessionData->lacSessCtx.cipherSetupData. ++ cipherDirection = ++ CPA_CY_SYM_CIPHER_DIRECTION_DECRYPT; ++ } ++ ++ } ++ ++ } else if (ICP_OCF_DRV_ALG_CIPHER == ++ icp_ocfDrvAlgCheck(crp->crp_desc)) { ++ if (crp->crp_desc->crd_flags & CRD_F_ENCRYPT) { ++ sessionData->lacSessCtx.cipherSetupData. ++ cipherDirection = ++ CPA_CY_SYM_CIPHER_DIRECTION_ENCRYPT; ++ } else { ++ sessionData->lacSessCtx.cipherSetupData. ++ cipherDirection = ++ CPA_CY_SYM_CIPHER_DIRECTION_DECRYPT; ++ } ++ ++ } ++ ++ /*No action required for standalone Auth here */ ++ ++ /* Allocate memory for SymSessionCtx before the Session Registration */ ++ lacStatus = ++ cpaCySymSessionCtxGetSize(CPA_INSTANCE_HANDLE_SINGLE, ++ &(sessionData->lacSessCtx), ++ &sessionCtxSizeInBytes); ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): cpaCySymSessionCtxGetSize failed - %d\n", ++ __FUNCTION__, lacStatus); ++ crp->crp_etype = EINVAL; ++ return EINVAL; ++ } ++ sessionData->sessHandle = ++ icp_kmalloc(sessionCtxSizeInBytes, ICP_M_NOWAIT); ++ if (NULL == sessionData->sessHandle) { ++ EPRINTK ++ ("%s(): Failed to get memory for SymSessionCtx\n", ++ __FUNCTION__); ++ crp->crp_etype = ENOMEM; ++ return ENOMEM; ++ } ++ ++ lacStatus = cpaCySymInitSession(CPA_INSTANCE_HANDLE_SINGLE, ++ icp_ocfDrvSymCallBack, ++ &(sessionData->lacSessCtx), ++ sessionData->sessHandle); ++ ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): cpaCySymInitSession failed -%d \n", ++ __FUNCTION__, lacStatus); ++ crp->crp_etype = EFAULT; ++ return EFAULT; ++ } ++ ++ sessionData->inUse = ICP_SESSION_RUNNING; ++ } ++ ++ drvOpData = icp_kmem_cache_zalloc(drvOpData_zone, ICP_M_NOWAIT); ++ if (NULL == drvOpData) { ++ EPRINTK("%s():Failed to get memory for drvOpData\n", ++ __FUNCTION__); ++ crp->crp_etype = ENOMEM; ++ return ENOMEM; ++ } ++ ++ drvOpData->lacOpData.pSessionCtx = sessionData->sessHandle; ++ drvOpData->digestSizeInBytes = sessionData->lacSessCtx.hashSetupData. ++ digestResultLenInBytes; ++ drvOpData->crp = crp; ++ ++ /* Set the default buffer list array memory allocation */ ++ drvOpData->srcBuffer.pBuffers = drvOpData->bufferListArray; ++ drvOpData->numBufferListArray = ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS; ++ ++ if (ICP_OCF_DRV_STATUS_SUCCESS != ++ icp_ocfDrvProcessDataSetup(drvOpData, drvOpData->crp->crp_desc)) { ++ crp->crp_etype = EINVAL; ++ goto err; ++ } ++ ++ if (drvOpData->crp->crp_desc->crd_next != NULL) { ++ if (icp_ocfDrvProcessDataSetup(drvOpData, drvOpData->crp-> ++ crp_desc->crd_next)) { ++ crp->crp_etype = EINVAL; ++ goto err; ++ } ++ ++ } ++ ++ /* ++ * Allocate buffer list array memory if the data fragment is more than ++ * the default number (ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) and not ++ * calculated already ++ */ ++ if (crp->crp_flags & ICP_CRYPTO_F_PACKET_BUF) { ++ if (NULL == drvOpData->lacOpData.pDigestResult) { ++ drvOpData->numBufferListArray = ++ icp_ocfDrvGetPacketBuffFrags((icp_packet_buffer_t *) ++ crp->crp_buf); ++ } ++ ++ if (ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS < ++ drvOpData->numBufferListArray) { ++ DPRINTK("%s() numBufferListArray more than default\n", ++ __FUNCTION__); ++ drvOpData->srcBuffer.pBuffers = NULL; ++ drvOpData->srcBuffer.pBuffers = ++ icp_kmalloc(drvOpData->numBufferListArray * ++ sizeof(CpaFlatBuffer), ICP_M_NOWAIT); ++ if (NULL == drvOpData->srcBuffer.pBuffers) { ++ EPRINTK("%s() Failed to get memory for " ++ "pBuffers\n", __FUNCTION__); ++ ICP_CACHE_FREE(drvOpData_zone, drvOpData); ++ crp->crp_etype = ENOMEM; ++ return ENOMEM; ++ } ++ } ++ } ++ ++ /* ++ * Check the type of buffer structure we got and convert it into ++ * CpaBufferList format. ++ */ ++ if (crp->crp_flags & ICP_CRYPTO_F_PACKET_BUF) { ++ if (ICP_OCF_DRV_STATUS_SUCCESS != ++ icp_ocfDrvPacketBuffToBufferList((icp_packet_buffer_t *) ++ crp->crp_buf, ++ &(drvOpData->srcBuffer))) { ++ EPRINTK("%s():Failed to translate from packet buffer " ++ "to bufferlist\n", __FUNCTION__); ++ crp->crp_etype = EINVAL; ++ goto err; ++ } ++ ++ drvOpData->bufferType = ICP_CRYPTO_F_PACKET_BUF; ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ /* OCF only supports IOV of one entry. */ ++ if (NUM_IOV_SUPPORTED == ++ ((struct uio *)(crp->crp_buf))->uio_iovcnt) { ++ ++ icp_ocfDrvPtrAndLenToBufferList(((struct uio *)(crp-> ++ crp_buf))-> ++ uio_iov[0].iov_base, ++ ((struct uio *)(crp-> ++ crp_buf))-> ++ uio_iov[0].iov_len, ++ &(drvOpData-> ++ srcBuffer)); ++ ++ drvOpData->bufferType = CRYPTO_F_IOV; ++ ++ } else { ++ DPRINTK("%s():Unable to handle IOVs with lengths of " ++ "greater than one!\n", __FUNCTION__); ++ crp->crp_etype = EINVAL; ++ goto err; ++ } ++ ++ } else { ++ icp_ocfDrvPtrAndLenToBufferList(crp->crp_buf, ++ crp->crp_ilen, ++ &(drvOpData->srcBuffer)); ++ ++ drvOpData->bufferType = CRYPTO_BUF_CONTIG; ++ } ++ ++ /* Allocate srcBuffer's private meta data */ ++ if (ICP_OCF_DRV_STATUS_SUCCESS != ++ icp_ocfDrvAllocMetaData(&(drvOpData->srcBuffer), drvOpData)) { ++ EPRINTK("%s() icp_ocfDrvAllocMetaData failed\n", __FUNCTION__); ++ memset(&(drvOpData->lacOpData), 0, sizeof(CpaCySymOpData)); ++ crp->crp_etype = EINVAL; ++ goto err; ++ } ++ ++ /* Perform "in-place" crypto operation */ ++ lacStatus = cpaCySymPerformOp(CPA_INSTANCE_HANDLE_SINGLE, ++ (void *)drvOpData, ++ &(drvOpData->lacOpData), ++ &(drvOpData->srcBuffer), ++ &(drvOpData->srcBuffer), ++ &(drvOpData->verifyResult)); ++ if (CPA_STATUS_RETRY == lacStatus) { ++ DPRINTK("%s(): cpaCySymPerformOp retry, lacStatus = %d\n", ++ __FUNCTION__, lacStatus); ++ memset(&(drvOpData->lacOpData), 0, sizeof(CpaCySymOpData)); ++ crp->crp_etype = ERESTART; ++ goto err; ++ } ++ if (CPA_STATUS_SUCCESS != lacStatus) { ++ EPRINTK("%s(): cpaCySymPerformOp failed, lacStatus = %d\n", ++ __FUNCTION__, lacStatus); ++ memset(&(drvOpData->lacOpData), 0, sizeof(CpaCySymOpData)); ++ crp->crp_etype = EINVAL; ++ goto err; ++ } ++ ++ return 0; //OCF success status value ++ ++ err: ++ if (drvOpData->numBufferListArray > ICP_OCF_DRV_DEFAULT_BUFFLIST_ARRAYS) { ++ icp_kfree(drvOpData->srcBuffer.pBuffers); ++ } ++ icp_ocfDrvFreeMetaData(&(drvOpData->srcBuffer)); ++ ICP_CACHE_FREE(drvOpData_zone, drvOpData); ++ ++ return crp->crp_etype; ++} ++ ++/* Name : icp_ocfDrvProcessDataSetup ++ * ++ * Description : This function will setup all the cryptographic operation data ++ * that is required by LAC to execute the operation. ++ */ ++static int icp_ocfDrvProcessDataSetup(struct icp_drvOpData *drvOpData, ++ struct cryptodesc *crp_desc) ++{ ++ CpaCyRandGenOpData randGenOpData; ++ CpaFlatBuffer randData; ++ ++ drvOpData->lacOpData.packetType = CPA_CY_SYM_PACKET_TYPE_FULL; ++ ++ /* Convert from the cryptop to the ICP LAC crypto parameters */ ++ switch (crp_desc->crd_alg) { ++ case CRYPTO_NULL_CBC: ++ drvOpData->lacOpData. ++ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; ++ drvOpData->lacOpData. ++ messageLenToCipherInBytes = crp_desc->crd_len; ++ drvOpData->verifyResult = CPA_FALSE; ++ drvOpData->lacOpData.ivLenInBytes = NULL_BLOCK_LEN; ++ break; ++ case CRYPTO_DES_CBC: ++ drvOpData->lacOpData. ++ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; ++ drvOpData->lacOpData. ++ messageLenToCipherInBytes = crp_desc->crd_len; ++ drvOpData->verifyResult = CPA_FALSE; ++ drvOpData->lacOpData.ivLenInBytes = DES_BLOCK_LEN; ++ break; ++ case CRYPTO_3DES_CBC: ++ drvOpData->lacOpData. ++ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; ++ drvOpData->lacOpData. ++ messageLenToCipherInBytes = crp_desc->crd_len; ++ drvOpData->verifyResult = CPA_FALSE; ++ drvOpData->lacOpData.ivLenInBytes = DES3_BLOCK_LEN; ++ break; ++ case CRYPTO_ARC4: ++ drvOpData->lacOpData. ++ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; ++ drvOpData->lacOpData. ++ messageLenToCipherInBytes = crp_desc->crd_len; ++ drvOpData->verifyResult = CPA_FALSE; ++ drvOpData->lacOpData.ivLenInBytes = ARC4_COUNTER_LEN; ++ break; ++ case CRYPTO_AES_CBC: ++ drvOpData->lacOpData. ++ cryptoStartSrcOffsetInBytes = crp_desc->crd_skip; ++ drvOpData->lacOpData. ++ messageLenToCipherInBytes = crp_desc->crd_len; ++ drvOpData->verifyResult = CPA_FALSE; ++ drvOpData->lacOpData.ivLenInBytes = RIJNDAEL128_BLOCK_LEN; ++ break; ++ case CRYPTO_SHA1: ++ case CRYPTO_SHA1_HMAC: ++ case CRYPTO_SHA2_256: ++ case CRYPTO_SHA2_256_HMAC: ++ case CRYPTO_SHA2_384: ++ case CRYPTO_SHA2_384_HMAC: ++ case CRYPTO_SHA2_512: ++ case CRYPTO_SHA2_512_HMAC: ++ case CRYPTO_MD5: ++ case CRYPTO_MD5_HMAC: ++ drvOpData->lacOpData. ++ hashStartSrcOffsetInBytes = crp_desc->crd_skip; ++ drvOpData->lacOpData. ++ messageLenToHashInBytes = crp_desc->crd_len; ++ drvOpData->lacOpData. ++ pDigestResult = ++ icp_ocfDrvDigestPointerFind(drvOpData, crp_desc); ++ ++ if (NULL == drvOpData->lacOpData.pDigestResult) { ++ DPRINTK("%s(): ERROR - could not calculate " ++ "Digest Result memory address\n", __FUNCTION__); ++ return ICP_OCF_DRV_STATUS_FAIL; ++ } ++ ++ drvOpData->lacOpData.digestVerify = CPA_FALSE; ++ break; ++ default: ++ DPRINTK("%s(): Crypto process error - algorithm not " ++ "found \n", __FUNCTION__); ++ return ICP_OCF_DRV_STATUS_FAIL; ++ } ++ ++ /* Figure out what the IV is supposed to be */ ++ if ((crp_desc->crd_alg == CRYPTO_DES_CBC) || ++ (crp_desc->crd_alg == CRYPTO_3DES_CBC) || ++ (crp_desc->crd_alg == CRYPTO_AES_CBC)) { ++ /*ARC4 doesn't use an IV */ ++ if (crp_desc->crd_flags & CRD_F_IV_EXPLICIT) { ++ /* Explicit IV provided to OCF */ ++ drvOpData->lacOpData.pIv = crp_desc->crd_iv; ++ } else { ++ /* IV is not explicitly provided to OCF */ ++ ++ /* Point the LAC OP Data IV pointer to our allocated ++ storage location for this session. */ ++ drvOpData->lacOpData.pIv = drvOpData->ivData; ++ ++ if ((crp_desc->crd_flags & CRD_F_ENCRYPT) && ++ ((crp_desc->crd_flags & CRD_F_IV_PRESENT) == 0)) { ++ ++ /* Encrypting - need to create IV */ ++ randGenOpData.generateBits = CPA_TRUE; ++ randGenOpData.lenInBytes = MAX_IV_LEN_IN_BYTES; ++ ++ icp_ocfDrvPtrAndLenToFlatBuffer((Cpa8U *) ++ drvOpData-> ++ ivData, ++ MAX_IV_LEN_IN_BYTES, ++ &randData); ++ ++ if (CPA_STATUS_SUCCESS != ++ cpaCyRandGen(CPA_INSTANCE_HANDLE_SINGLE, ++ NULL, NULL, ++ &randGenOpData, &randData)) { ++ DPRINTK("%s(): ERROR - Failed to" ++ " generate" ++ " Initialisation Vector\n", ++ __FUNCTION__); ++ return ICP_OCF_DRV_STATUS_FAIL; ++ } ++ ++ crypto_copyback(drvOpData->crp-> ++ crp_flags, ++ drvOpData->crp->crp_buf, ++ crp_desc->crd_inject, ++ drvOpData->lacOpData. ++ ivLenInBytes, ++ (caddr_t) (drvOpData->lacOpData. ++ pIv)); ++ } else { ++ /* Reading IV from buffer */ ++ crypto_copydata(drvOpData->crp-> ++ crp_flags, ++ drvOpData->crp->crp_buf, ++ crp_desc->crd_inject, ++ drvOpData->lacOpData. ++ ivLenInBytes, ++ (caddr_t) (drvOpData->lacOpData. ++ pIv)); ++ } ++ ++ } ++ ++ } ++ ++ return ICP_OCF_DRV_STATUS_SUCCESS; ++} ++ ++/* Name : icp_ocfDrvDigestPointerFind ++ * ++ * Description : This function is used to find the memory address of where the ++ * digest information shall be stored in. Input buffer types are an skbuff, iov ++ * or flat buffer. The address is found using the buffer data start address and ++ * an offset. ++ * ++ * Note: In the case of a linux skbuff, the digest address may exist within ++ * a memory space linked to from the start buffer. These linked memory spaces ++ * must be traversed by the data length offset in order to find the digest start ++ * address. Whether there is enough space for the digest must also be checked. ++ */ ++uint8_t *icp_ocfDrvDigestPointerFind(struct icp_drvOpData * drvOpData, ++ struct cryptodesc * crp_desc) ++{ ++ ++ int offsetInBytes = crp_desc->crd_inject; ++ uint32_t digestSizeInBytes = drvOpData->digestSizeInBytes; ++ uint8_t *flat_buffer_base = NULL; ++ int flat_buffer_length = 0; ++ ++ if (drvOpData->crp->crp_flags & ICP_CRYPTO_F_PACKET_BUF) { ++ ++ return icp_ocfDrvPacketBufferDigestPointerFind(drvOpData, ++ offsetInBytes, ++ digestSizeInBytes); ++ ++ } else { ++ /* IOV or flat buffer */ ++ if (drvOpData->crp->crp_flags & CRYPTO_F_IOV) { ++ /*single IOV check has already been done */ ++ flat_buffer_base = ((struct uio *) ++ (drvOpData->crp->crp_buf))-> ++ uio_iov[0].iov_base; ++ flat_buffer_length = ((struct uio *) ++ (drvOpData->crp->crp_buf))-> ++ uio_iov[0].iov_len; ++ } else { ++ flat_buffer_base = (uint8_t *) drvOpData->crp->crp_buf; ++ flat_buffer_length = drvOpData->crp->crp_ilen; ++ } ++ ++ if (flat_buffer_length < (offsetInBytes + digestSizeInBytes)) { ++ DPRINTK("%s() Not enough space for Digest " ++ "(IOV/Flat Buffer) \n", __FUNCTION__); ++ return NULL; ++ } else { ++ return (uint8_t *) (flat_buffer_base + offsetInBytes); ++ } ++ } ++ DPRINTK("%s() Should not reach this point\n", __FUNCTION__); ++ return NULL; ++} +diff -Nur linux-3.1.4.orig/crypto/ocf/ep80579/linux_2.6_kernel_space.mk linux-3.1.4/crypto/ocf/ep80579/linux_2.6_kernel_space.mk +--- linux-3.1.4.orig/crypto/ocf/ep80579/linux_2.6_kernel_space.mk 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/ep80579/linux_2.6_kernel_space.mk 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,69 @@ ++################### ++# @par ++# This file is provided under a dual BSD/GPLv2 license. When using or ++# redistributing this file, you may do so under either license. ++# ++# GPL LICENSE SUMMARY ++# ++# Copyright(c) 2007,2008 Intel Corporation. All rights reserved. ++# ++# This program is free software; you can redistribute it and/or modify ++# it under the terms of version 2 of the GNU General Public License as ++# published by the Free Software Foundation. ++# ++# This program is distributed in the hope that it will be useful, but ++# WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++# General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. ++# The full GNU General Public License is included in this distribution ++# in the file called LICENSE.GPL. ++# ++# Contact Information: ++# Intel Corporation ++# ++# BSD LICENSE ++# ++# Copyright(c) 2007,2008 Intel Corporation. All rights reserved. ++# All rights reserved. ++# ++# Redistribution and use in source and binary forms, with or without ++# modification, are permitted provided that the following conditions ++# are met: ++# ++# * Redistributions of source code must retain the above copyright ++# notice, this list of conditions and the following disclaimer. ++# * Redistributions in binary form must reproduce the above copyright ++# notice, this list of conditions and the following disclaimer in ++# the documentation and/or other materials provided with the ++# distribution. ++# * Neither the name of Intel Corporation nor the names of its ++# contributors may be used to endorse or promote products derived ++# from this software without specific prior written permission. ++# ++# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++# ++# ++# version: Security.L.1.0.130 ++################### ++ ++#specific include directories in kernel space ++INCLUDES+=#e.g. -I$(OSAL_DIR)/include \ ++ ++#Extra Flags Specific in kernel space e.g. include path or debug flags etc. e.g to add an include path EXTRA_CFLAGS += -I$(src)/../include ++EXTRA_CFLAGS += $(INCLUDES) -O2 -Wall ++EXTRA_LDFLAGS +=-whole-archive ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/hifn/Makefile linux-3.1.4/crypto/ocf/hifn/Makefile +--- linux-3.1.4.orig/crypto/ocf/hifn/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/hifn/Makefile 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,13 @@ ++# for SGlinux builds ++-include $(ROOTDIR)/modules/.config ++ ++obj-$(CONFIG_OCF_HIFN) += hifn7751.o ++obj-$(CONFIG_OCF_HIFNHIPP) += hifnHIPP.o ++ ++obj ?= . ++EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ ++ ++ifdef TOPDIR ++-include $(TOPDIR)/Rules.make ++endif ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/hifn/hifn7751.c linux-3.1.4/crypto/ocf/hifn/hifn7751.c +--- linux-3.1.4.orig/crypto/ocf/hifn/hifn7751.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/hifn/hifn7751.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,2954 @@ ++/* $OpenBSD: hifn7751.c,v 1.120 2002/05/17 00:33:34 deraadt Exp $ */ ++ ++/*- ++ * Invertex AEON / Hifn 7751 driver ++ * Copyright (c) 1999 Invertex Inc. All rights reserved. ++ * Copyright (c) 1999 Theo de Raadt ++ * Copyright (c) 2000-2001 Network Security Technologies, Inc. ++ * http://www.netsec.net ++ * Copyright (c) 2003 Hifn Inc. ++ * ++ * This driver is based on a previous driver by Invertex, for which they ++ * requested: Please send any comments, feedback, bug-fixes, or feature ++ * requests to software@invertex.com. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored in part by the Defense Advanced Research Projects ++ * Agency (DARPA) and Air Force Research Laboratory, Air Force ++ * Materiel Command, USAF, under agreement number F30602-01-2-0537. ++ * ++ * ++__FBSDID("$FreeBSD: src/sys/dev/hifn/hifn7751.c,v 1.40 2007/03/21 03:42:49 sam Exp $"); ++ */ ++ ++/* ++ * Driver for various Hifn encryption processors. ++ */ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#if 1 ++#define DPRINTF(a...) if (hifn_debug) { \ ++ printk("%s: ", sc ? \ ++ device_get_nameunit(sc->sc_dev) : "hifn"); \ ++ printk(a); \ ++ } else ++#else ++#define DPRINTF(a...) ++#endif ++ ++static inline int ++pci_get_revid(struct pci_dev *dev) ++{ ++ u8 rid = 0; ++ pci_read_config_byte(dev, PCI_REVISION_ID, &rid); ++ return rid; ++} ++ ++static struct hifn_stats hifnstats; ++ ++#define debug hifn_debug ++int hifn_debug = 0; ++module_param(hifn_debug, int, 0644); ++MODULE_PARM_DESC(hifn_debug, "Enable debug"); ++ ++int hifn_maxbatch = 1; ++module_param(hifn_maxbatch, int, 0644); ++MODULE_PARM_DESC(hifn_maxbatch, "max ops to batch w/o interrupt"); ++ ++int hifn_cache_linesize = 0x10; ++module_param(hifn_cache_linesize, int, 0444); ++MODULE_PARM_DESC(hifn_cache_linesize, "PCI config cache line size"); ++ ++#ifdef MODULE_PARM ++char *hifn_pllconfig = NULL; ++MODULE_PARM(hifn_pllconfig, "s"); ++#else ++char hifn_pllconfig[32]; /* This setting is RO after loading */ ++module_param_string(hifn_pllconfig, hifn_pllconfig, 32, 0444); ++#endif ++MODULE_PARM_DESC(hifn_pllconfig, "PLL config, ie., pci66, ext33, ..."); ++ ++#ifdef HIFN_VULCANDEV ++#include ++#include ++ ++static struct cdevsw vulcanpk_cdevsw; /* forward declaration */ ++#endif ++ ++/* ++ * Prototypes and count for the pci_device structure ++ */ ++static int hifn_probe(struct pci_dev *dev, const struct pci_device_id *ent); ++static void hifn_remove(struct pci_dev *dev); ++ ++static int hifn_newsession(device_t, u_int32_t *, struct cryptoini *); ++static int hifn_freesession(device_t, u_int64_t); ++static int hifn_process(device_t, struct cryptop *, int); ++ ++static device_method_t hifn_methods = { ++ /* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, hifn_newsession), ++ DEVMETHOD(cryptodev_freesession,hifn_freesession), ++ DEVMETHOD(cryptodev_process, hifn_process), ++}; ++ ++static void hifn_reset_board(struct hifn_softc *, int); ++static void hifn_reset_puc(struct hifn_softc *); ++static void hifn_puc_wait(struct hifn_softc *); ++static int hifn_enable_crypto(struct hifn_softc *); ++static void hifn_set_retry(struct hifn_softc *sc); ++static void hifn_init_dma(struct hifn_softc *); ++static void hifn_init_pci_registers(struct hifn_softc *); ++static int hifn_sramsize(struct hifn_softc *); ++static int hifn_dramsize(struct hifn_softc *); ++static int hifn_ramtype(struct hifn_softc *); ++static void hifn_sessions(struct hifn_softc *); ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) ++static irqreturn_t hifn_intr(int irq, void *arg); ++#else ++static irqreturn_t hifn_intr(int irq, void *arg, struct pt_regs *regs); ++#endif ++static u_int hifn_write_command(struct hifn_command *, u_int8_t *); ++static u_int32_t hifn_next_signature(u_int32_t a, u_int cnt); ++static void hifn_callback(struct hifn_softc *, struct hifn_command *, u_int8_t *); ++static int hifn_crypto(struct hifn_softc *, struct hifn_command *, struct cryptop *, int); ++static int hifn_readramaddr(struct hifn_softc *, int, u_int8_t *); ++static int hifn_writeramaddr(struct hifn_softc *, int, u_int8_t *); ++static int hifn_dmamap_load_src(struct hifn_softc *, struct hifn_command *); ++static int hifn_dmamap_load_dst(struct hifn_softc *, struct hifn_command *); ++static int hifn_init_pubrng(struct hifn_softc *); ++static void hifn_tick(unsigned long arg); ++static void hifn_abort(struct hifn_softc *); ++static void hifn_alloc_slot(struct hifn_softc *, int *, int *, int *, int *); ++ ++static void hifn_write_reg_0(struct hifn_softc *, bus_size_t, u_int32_t); ++static void hifn_write_reg_1(struct hifn_softc *, bus_size_t, u_int32_t); ++ ++#ifdef CONFIG_OCF_RANDOMHARVEST ++static int hifn_read_random(void *arg, u_int32_t *buf, int len); ++#endif ++ ++#define HIFN_MAX_CHIPS 8 ++static struct hifn_softc *hifn_chip_idx[HIFN_MAX_CHIPS]; ++ ++static __inline u_int32_t ++READ_REG_0(struct hifn_softc *sc, bus_size_t reg) ++{ ++ u_int32_t v = readl(sc->sc_bar0 + reg); ++ sc->sc_bar0_lastreg = (bus_size_t) -1; ++ return (v); ++} ++#define WRITE_REG_0(sc, reg, val) hifn_write_reg_0(sc, reg, val) ++ ++static __inline u_int32_t ++READ_REG_1(struct hifn_softc *sc, bus_size_t reg) ++{ ++ u_int32_t v = readl(sc->sc_bar1 + reg); ++ sc->sc_bar1_lastreg = (bus_size_t) -1; ++ return (v); ++} ++#define WRITE_REG_1(sc, reg, val) hifn_write_reg_1(sc, reg, val) ++ ++/* ++ * map in a given buffer (great on some arches :-) ++ */ ++ ++static int ++pci_map_uio(struct hifn_softc *sc, struct hifn_operand *buf, struct uio *uio) ++{ ++ struct iovec *iov = uio->uio_iov; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ buf->mapsize = 0; ++ for (buf->nsegs = 0; buf->nsegs < uio->uio_iovcnt; ) { ++ buf->segs[buf->nsegs].ds_addr = pci_map_single(sc->sc_pcidev, ++ iov->iov_base, iov->iov_len, ++ PCI_DMA_BIDIRECTIONAL); ++ buf->segs[buf->nsegs].ds_len = iov->iov_len; ++ buf->mapsize += iov->iov_len; ++ iov++; ++ buf->nsegs++; ++ } ++ /* identify this buffer by the first segment */ ++ buf->map = (void *) buf->segs[0].ds_addr; ++ return(0); ++} ++ ++/* ++ * map in a given sk_buff ++ */ ++ ++static int ++pci_map_skb(struct hifn_softc *sc,struct hifn_operand *buf,struct sk_buff *skb) ++{ ++ int i; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ buf->mapsize = 0; ++ ++ buf->segs[0].ds_addr = pci_map_single(sc->sc_pcidev, ++ skb->data, skb_headlen(skb), PCI_DMA_BIDIRECTIONAL); ++ buf->segs[0].ds_len = skb_headlen(skb); ++ buf->mapsize += buf->segs[0].ds_len; ++ ++ buf->nsegs = 1; ++ ++ for (i = 0; i < skb_shinfo(skb)->nr_frags; ) { ++ buf->segs[buf->nsegs].ds_len = skb_shinfo(skb)->frags[i].size; ++ buf->segs[buf->nsegs].ds_addr = pci_map_single(sc->sc_pcidev, ++ page_address(skb_shinfo(skb)->frags[i].page) + ++ skb_shinfo(skb)->frags[i].page_offset, ++ buf->segs[buf->nsegs].ds_len, PCI_DMA_BIDIRECTIONAL); ++ buf->mapsize += buf->segs[buf->nsegs].ds_len; ++ buf->nsegs++; ++ } ++ ++ /* identify this buffer by the first segment */ ++ buf->map = (void *) buf->segs[0].ds_addr; ++ return(0); ++} ++ ++/* ++ * map in a given contiguous buffer ++ */ ++ ++static int ++pci_map_buf(struct hifn_softc *sc,struct hifn_operand *buf, void *b, int len) ++{ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ buf->mapsize = 0; ++ buf->segs[0].ds_addr = pci_map_single(sc->sc_pcidev, ++ b, len, PCI_DMA_BIDIRECTIONAL); ++ buf->segs[0].ds_len = len; ++ buf->mapsize += buf->segs[0].ds_len; ++ buf->nsegs = 1; ++ ++ /* identify this buffer by the first segment */ ++ buf->map = (void *) buf->segs[0].ds_addr; ++ return(0); ++} ++ ++#if 0 /* not needed at this time */ ++static void ++pci_sync_iov(struct hifn_softc *sc, struct hifn_operand *buf) ++{ ++ int i; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ for (i = 0; i < buf->nsegs; i++) ++ pci_dma_sync_single_for_cpu(sc->sc_pcidev, buf->segs[i].ds_addr, ++ buf->segs[i].ds_len, PCI_DMA_BIDIRECTIONAL); ++} ++#endif ++ ++static void ++pci_unmap_buf(struct hifn_softc *sc, struct hifn_operand *buf) ++{ ++ int i; ++ DPRINTF("%s()\n", __FUNCTION__); ++ for (i = 0; i < buf->nsegs; i++) { ++ pci_unmap_single(sc->sc_pcidev, buf->segs[i].ds_addr, ++ buf->segs[i].ds_len, PCI_DMA_BIDIRECTIONAL); ++ buf->segs[i].ds_addr = 0; ++ buf->segs[i].ds_len = 0; ++ } ++ buf->nsegs = 0; ++ buf->mapsize = 0; ++ buf->map = 0; ++} ++ ++static const char* ++hifn_partname(struct hifn_softc *sc) ++{ ++ /* XXX sprintf numbers when not decoded */ ++ switch (pci_get_vendor(sc->sc_pcidev)) { ++ case PCI_VENDOR_HIFN: ++ switch (pci_get_device(sc->sc_pcidev)) { ++ case PCI_PRODUCT_HIFN_6500: return "Hifn 6500"; ++ case PCI_PRODUCT_HIFN_7751: return "Hifn 7751"; ++ case PCI_PRODUCT_HIFN_7811: return "Hifn 7811"; ++ case PCI_PRODUCT_HIFN_7951: return "Hifn 7951"; ++ case PCI_PRODUCT_HIFN_7955: return "Hifn 7955"; ++ case PCI_PRODUCT_HIFN_7956: return "Hifn 7956"; ++ } ++ return "Hifn unknown-part"; ++ case PCI_VENDOR_INVERTEX: ++ switch (pci_get_device(sc->sc_pcidev)) { ++ case PCI_PRODUCT_INVERTEX_AEON: return "Invertex AEON"; ++ } ++ return "Invertex unknown-part"; ++ case PCI_VENDOR_NETSEC: ++ switch (pci_get_device(sc->sc_pcidev)) { ++ case PCI_PRODUCT_NETSEC_7751: return "NetSec 7751"; ++ } ++ return "NetSec unknown-part"; ++ } ++ return "Unknown-vendor unknown-part"; ++} ++ ++static u_int ++checkmaxmin(struct pci_dev *dev, const char *what, u_int v, u_int min, u_int max) ++{ ++ struct hifn_softc *sc = pci_get_drvdata(dev); ++ if (v > max) { ++ device_printf(sc->sc_dev, "Warning, %s %u out of range, " ++ "using max %u\n", what, v, max); ++ v = max; ++ } else if (v < min) { ++ device_printf(sc->sc_dev, "Warning, %s %u out of range, " ++ "using min %u\n", what, v, min); ++ v = min; ++ } ++ return v; ++} ++ ++/* ++ * Select PLL configuration for 795x parts. This is complicated in ++ * that we cannot determine the optimal parameters without user input. ++ * The reference clock is derived from an external clock through a ++ * multiplier. The external clock is either the host bus (i.e. PCI) ++ * or an external clock generator. When using the PCI bus we assume ++ * the clock is either 33 or 66 MHz; for an external source we cannot ++ * tell the speed. ++ * ++ * PLL configuration is done with a string: "pci" for PCI bus, or "ext" ++ * for an external source, followed by the frequency. We calculate ++ * the appropriate multiplier and PLL register contents accordingly. ++ * When no configuration is given we default to "pci66" since that ++ * always will allow the card to work. If a card is using the PCI ++ * bus clock and in a 33MHz slot then it will be operating at half ++ * speed until the correct information is provided. ++ * ++ * We use a default setting of "ext66" because according to Mike Ham ++ * of HiFn, almost every board in existence has an external crystal ++ * populated at 66Mhz. Using PCI can be a problem on modern motherboards, ++ * because PCI33 can have clocks from 0 to 33Mhz, and some have ++ * non-PCI-compliant spread-spectrum clocks, which can confuse the pll. ++ */ ++static void ++hifn_getpllconfig(struct pci_dev *dev, u_int *pll) ++{ ++ const char *pllspec = hifn_pllconfig; ++ u_int freq, mul, fl, fh; ++ u_int32_t pllconfig; ++ char *nxt; ++ ++ if (pllspec == NULL) ++ pllspec = "ext66"; ++ fl = 33, fh = 66; ++ pllconfig = 0; ++ if (strncmp(pllspec, "ext", 3) == 0) { ++ pllspec += 3; ++ pllconfig |= HIFN_PLL_REF_SEL; ++ switch (pci_get_device(dev)) { ++ case PCI_PRODUCT_HIFN_7955: ++ case PCI_PRODUCT_HIFN_7956: ++ fl = 20, fh = 100; ++ break; ++#ifdef notyet ++ case PCI_PRODUCT_HIFN_7954: ++ fl = 20, fh = 66; ++ break; ++#endif ++ } ++ } else if (strncmp(pllspec, "pci", 3) == 0) ++ pllspec += 3; ++ freq = strtoul(pllspec, &nxt, 10); ++ if (nxt == pllspec) ++ freq = 66; ++ else ++ freq = checkmaxmin(dev, "frequency", freq, fl, fh); ++ /* ++ * Calculate multiplier. We target a Fck of 266 MHz, ++ * allowing only even values, possibly rounded down. ++ * Multipliers > 8 must set the charge pump current. ++ */ ++ mul = checkmaxmin(dev, "PLL divisor", (266 / freq) &~ 1, 2, 12); ++ pllconfig |= (mul / 2 - 1) << HIFN_PLL_ND_SHIFT; ++ if (mul > 8) ++ pllconfig |= HIFN_PLL_IS; ++ *pll = pllconfig; ++} ++ ++/* ++ * Attach an interface that successfully probed. ++ */ ++static int ++hifn_probe(struct pci_dev *dev, const struct pci_device_id *ent) ++{ ++ struct hifn_softc *sc = NULL; ++ char rbase; ++ u_int16_t ena, rev; ++ int rseg, rc; ++ unsigned long mem_start, mem_len; ++ static int num_chips = 0; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ if (pci_enable_device(dev) < 0) ++ return(-ENODEV); ++ ++ if (pci_set_mwi(dev)) ++ return(-ENODEV); ++ ++ if (!dev->irq) { ++ printk("hifn: found device with no IRQ assigned. check BIOS settings!"); ++ pci_disable_device(dev); ++ return(-ENODEV); ++ } ++ ++ sc = (struct hifn_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); ++ if (!sc) ++ return(-ENOMEM); ++ memset(sc, 0, sizeof(*sc)); ++ ++ softc_device_init(sc, "hifn", num_chips, hifn_methods); ++ ++ sc->sc_pcidev = dev; ++ sc->sc_irq = -1; ++ sc->sc_cid = -1; ++ sc->sc_num = num_chips++; ++ if (sc->sc_num < HIFN_MAX_CHIPS) ++ hifn_chip_idx[sc->sc_num] = sc; ++ ++ pci_set_drvdata(sc->sc_pcidev, sc); ++ ++ spin_lock_init(&sc->sc_mtx); ++ ++ /* XXX handle power management */ ++ ++ /* ++ * The 7951 and 795x have a random number generator and ++ * public key support; note this. ++ */ ++ if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && ++ (pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 || ++ pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 || ++ pci_get_device(dev) == PCI_PRODUCT_HIFN_7956)) ++ sc->sc_flags = HIFN_HAS_RNG | HIFN_HAS_PUBLIC; ++ /* ++ * The 7811 has a random number generator and ++ * we also note it's identity 'cuz of some quirks. ++ */ ++ if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && ++ pci_get_device(dev) == PCI_PRODUCT_HIFN_7811) ++ sc->sc_flags |= HIFN_IS_7811 | HIFN_HAS_RNG; ++ ++ /* ++ * The 795x parts support AES. ++ */ ++ if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && ++ (pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 || ++ pci_get_device(dev) == PCI_PRODUCT_HIFN_7956)) { ++ sc->sc_flags |= HIFN_IS_7956 | HIFN_HAS_AES; ++ /* ++ * Select PLL configuration. This depends on the ++ * bus and board design and must be manually configured ++ * if the default setting is unacceptable. ++ */ ++ hifn_getpllconfig(dev, &sc->sc_pllconfig); ++ } ++ ++ /* ++ * Setup PCI resources. Note that we record the bus ++ * tag and handle for each register mapping, this is ++ * used by the READ_REG_0, WRITE_REG_0, READ_REG_1, ++ * and WRITE_REG_1 macros throughout the driver. ++ */ ++ mem_start = pci_resource_start(sc->sc_pcidev, 0); ++ mem_len = pci_resource_len(sc->sc_pcidev, 0); ++ sc->sc_bar0 = (ocf_iomem_t) ioremap(mem_start, mem_len); ++ if (!sc->sc_bar0) { ++ device_printf(sc->sc_dev, "cannot map bar%d register space\n", 0); ++ goto fail; ++ } ++ sc->sc_bar0_lastreg = (bus_size_t) -1; ++ ++ mem_start = pci_resource_start(sc->sc_pcidev, 1); ++ mem_len = pci_resource_len(sc->sc_pcidev, 1); ++ sc->sc_bar1 = (ocf_iomem_t) ioremap(mem_start, mem_len); ++ if (!sc->sc_bar1) { ++ device_printf(sc->sc_dev, "cannot map bar%d register space\n", 1); ++ goto fail; ++ } ++ sc->sc_bar1_lastreg = (bus_size_t) -1; ++ ++ /* fix up the bus size */ ++ if (pci_set_dma_mask(dev, DMA_32BIT_MASK)) { ++ device_printf(sc->sc_dev, "No usable DMA configuration, aborting.\n"); ++ goto fail; ++ } ++ if (pci_set_consistent_dma_mask(dev, DMA_32BIT_MASK)) { ++ device_printf(sc->sc_dev, ++ "No usable consistent DMA configuration, aborting.\n"); ++ goto fail; ++ } ++ ++ hifn_set_retry(sc); ++ ++ /* ++ * Setup the area where the Hifn DMA's descriptors ++ * and associated data structures. ++ */ ++ sc->sc_dma = (struct hifn_dma *) pci_alloc_consistent(dev, ++ sizeof(*sc->sc_dma), ++ &sc->sc_dma_physaddr); ++ if (!sc->sc_dma) { ++ device_printf(sc->sc_dev, "cannot alloc sc_dma\n"); ++ goto fail; ++ } ++ bzero(sc->sc_dma, sizeof(*sc->sc_dma)); ++ ++ /* ++ * Reset the board and do the ``secret handshake'' ++ * to enable the crypto support. Then complete the ++ * initialization procedure by setting up the interrupt ++ * and hooking in to the system crypto support so we'll ++ * get used for system services like the crypto device, ++ * IPsec, RNG device, etc. ++ */ ++ hifn_reset_board(sc, 0); ++ ++ if (hifn_enable_crypto(sc) != 0) { ++ device_printf(sc->sc_dev, "crypto enabling failed\n"); ++ goto fail; ++ } ++ hifn_reset_puc(sc); ++ ++ hifn_init_dma(sc); ++ hifn_init_pci_registers(sc); ++ ++ pci_set_master(sc->sc_pcidev); ++ ++ /* XXX can't dynamically determine ram type for 795x; force dram */ ++ if (sc->sc_flags & HIFN_IS_7956) ++ sc->sc_drammodel = 1; ++ else if (hifn_ramtype(sc)) ++ goto fail; ++ ++ if (sc->sc_drammodel == 0) ++ hifn_sramsize(sc); ++ else ++ hifn_dramsize(sc); ++ ++ /* ++ * Workaround for NetSec 7751 rev A: half ram size because two ++ * of the address lines were left floating ++ */ ++ if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC && ++ pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751 && ++ pci_get_revid(dev) == 0x61) /*XXX???*/ ++ sc->sc_ramsize >>= 1; ++ ++ /* ++ * Arrange the interrupt line. ++ */ ++ rc = request_irq(dev->irq, hifn_intr, IRQF_SHARED, "hifn", sc); ++ if (rc) { ++ device_printf(sc->sc_dev, "could not map interrupt: %d\n", rc); ++ goto fail; ++ } ++ sc->sc_irq = dev->irq; ++ ++ hifn_sessions(sc); ++ ++ /* ++ * NB: Keep only the low 16 bits; this masks the chip id ++ * from the 7951. ++ */ ++ rev = READ_REG_1(sc, HIFN_1_REVID) & 0xffff; ++ ++ rseg = sc->sc_ramsize / 1024; ++ rbase = 'K'; ++ if (sc->sc_ramsize >= (1024 * 1024)) { ++ rbase = 'M'; ++ rseg /= 1024; ++ } ++ device_printf(sc->sc_dev, "%s, rev %u, %d%cB %cram", ++ hifn_partname(sc), rev, ++ rseg, rbase, sc->sc_drammodel ? 'd' : 's'); ++ if (sc->sc_flags & HIFN_IS_7956) ++ printf(", pll=0x%x<%s clk, %ux mult>", ++ sc->sc_pllconfig, ++ sc->sc_pllconfig & HIFN_PLL_REF_SEL ? "ext" : "pci", ++ 2 + 2*((sc->sc_pllconfig & HIFN_PLL_ND) >> 11)); ++ printf("\n"); ++ ++ sc->sc_cid = crypto_get_driverid(softc_get_device(sc),CRYPTOCAP_F_HARDWARE); ++ if (sc->sc_cid < 0) { ++ device_printf(sc->sc_dev, "could not get crypto driver id\n"); ++ goto fail; ++ } ++ ++ WRITE_REG_0(sc, HIFN_0_PUCNFG, ++ READ_REG_0(sc, HIFN_0_PUCNFG) | HIFN_PUCNFG_CHIPID); ++ ena = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; ++ ++ switch (ena) { ++ case HIFN_PUSTAT_ENA_2: ++ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0); ++ if (sc->sc_flags & HIFN_HAS_AES) ++ crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); ++ /*FALLTHROUGH*/ ++ case HIFN_PUSTAT_ENA_1: ++ crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); ++ break; ++ } ++ ++ if (sc->sc_flags & (HIFN_HAS_PUBLIC | HIFN_HAS_RNG)) ++ hifn_init_pubrng(sc); ++ ++ init_timer(&sc->sc_tickto); ++ sc->sc_tickto.function = hifn_tick; ++ sc->sc_tickto.data = (unsigned long) sc->sc_num; ++ mod_timer(&sc->sc_tickto, jiffies + HZ); ++ ++ return (0); ++ ++fail: ++ if (sc->sc_cid >= 0) ++ crypto_unregister_all(sc->sc_cid); ++ if (sc->sc_irq != -1) ++ free_irq(sc->sc_irq, sc); ++ if (sc->sc_dma) { ++ /* Turn off DMA polling */ ++ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | ++ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); ++ ++ pci_free_consistent(sc->sc_pcidev, ++ sizeof(*sc->sc_dma), ++ sc->sc_dma, sc->sc_dma_physaddr); ++ } ++ kfree(sc); ++ return (-ENXIO); ++} ++ ++/* ++ * Detach an interface that successfully probed. ++ */ ++static void ++hifn_remove(struct pci_dev *dev) ++{ ++ struct hifn_softc *sc = pci_get_drvdata(dev); ++ unsigned long l_flags; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ KASSERT(sc != NULL, ("hifn_detach: null software carrier!")); ++ ++ /* disable interrupts */ ++ HIFN_LOCK(sc); ++ WRITE_REG_1(sc, HIFN_1_DMA_IER, 0); ++ HIFN_UNLOCK(sc); ++ ++ /*XXX other resources */ ++ del_timer_sync(&sc->sc_tickto); ++ ++ /* Turn off DMA polling */ ++ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | ++ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); ++ ++ crypto_unregister_all(sc->sc_cid); ++ ++ free_irq(sc->sc_irq, sc); ++ ++ pci_free_consistent(sc->sc_pcidev, sizeof(*sc->sc_dma), ++ sc->sc_dma, sc->sc_dma_physaddr); ++} ++ ++ ++static int ++hifn_init_pubrng(struct hifn_softc *sc) ++{ ++ int i; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ if ((sc->sc_flags & HIFN_IS_7811) == 0) { ++ /* Reset 7951 public key/rng engine */ ++ WRITE_REG_1(sc, HIFN_1_PUB_RESET, ++ READ_REG_1(sc, HIFN_1_PUB_RESET) | HIFN_PUBRST_RESET); ++ ++ for (i = 0; i < 100; i++) { ++ DELAY(1000); ++ if ((READ_REG_1(sc, HIFN_1_PUB_RESET) & ++ HIFN_PUBRST_RESET) == 0) ++ break; ++ } ++ ++ if (i == 100) { ++ device_printf(sc->sc_dev, "public key init failed\n"); ++ return (1); ++ } ++ } ++ ++ /* Enable the rng, if available */ ++#ifdef CONFIG_OCF_RANDOMHARVEST ++ if (sc->sc_flags & HIFN_HAS_RNG) { ++ if (sc->sc_flags & HIFN_IS_7811) { ++ u_int32_t r; ++ r = READ_REG_1(sc, HIFN_1_7811_RNGENA); ++ if (r & HIFN_7811_RNGENA_ENA) { ++ r &= ~HIFN_7811_RNGENA_ENA; ++ WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); ++ } ++ WRITE_REG_1(sc, HIFN_1_7811_RNGCFG, ++ HIFN_7811_RNGCFG_DEFL); ++ r |= HIFN_7811_RNGENA_ENA; ++ WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); ++ } else ++ WRITE_REG_1(sc, HIFN_1_RNG_CONFIG, ++ READ_REG_1(sc, HIFN_1_RNG_CONFIG) | ++ HIFN_RNGCFG_ENA); ++ ++ sc->sc_rngfirst = 1; ++ crypto_rregister(sc->sc_cid, hifn_read_random, sc); ++ } ++#endif ++ ++ /* Enable public key engine, if available */ ++ if (sc->sc_flags & HIFN_HAS_PUBLIC) { ++ WRITE_REG_1(sc, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE); ++ sc->sc_dmaier |= HIFN_DMAIER_PUBDONE; ++ WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); ++#ifdef HIFN_VULCANDEV ++ sc->sc_pkdev = make_dev(&vulcanpk_cdevsw, 0, ++ UID_ROOT, GID_WHEEL, 0666, ++ "vulcanpk"); ++ sc->sc_pkdev->si_drv1 = sc; ++#endif ++ } ++ ++ return (0); ++} ++ ++#ifdef CONFIG_OCF_RANDOMHARVEST ++static int ++hifn_read_random(void *arg, u_int32_t *buf, int len) ++{ ++ struct hifn_softc *sc = (struct hifn_softc *) arg; ++ u_int32_t sts; ++ int i, rc = 0; ++ ++ if (len <= 0) ++ return rc; ++ ++ if (sc->sc_flags & HIFN_IS_7811) { ++ /* ONLY VALID ON 7811!!!! */ ++ for (i = 0; i < 5; i++) { ++ sts = READ_REG_1(sc, HIFN_1_7811_RNGSTS); ++ if (sts & HIFN_7811_RNGSTS_UFL) { ++ device_printf(sc->sc_dev, ++ "RNG underflow: disabling\n"); ++ /* DAVIDM perhaps return -1 */ ++ break; ++ } ++ if ((sts & HIFN_7811_RNGSTS_RDY) == 0) ++ break; ++ ++ /* ++ * There are at least two words in the RNG FIFO ++ * at this point. ++ */ ++ if (rc < len) ++ buf[rc++] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); ++ if (rc < len) ++ buf[rc++] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); ++ } ++ } else ++ buf[rc++] = READ_REG_1(sc, HIFN_1_RNG_DATA); ++ ++ /* NB: discard first data read */ ++ if (sc->sc_rngfirst) { ++ sc->sc_rngfirst = 0; ++ rc = 0; ++ } ++ ++ return(rc); ++} ++#endif /* CONFIG_OCF_RANDOMHARVEST */ ++ ++static void ++hifn_puc_wait(struct hifn_softc *sc) ++{ ++ int i; ++ int reg = HIFN_0_PUCTRL; ++ ++ if (sc->sc_flags & HIFN_IS_7956) { ++ reg = HIFN_0_PUCTRL2; ++ } ++ ++ for (i = 5000; i > 0; i--) { ++ DELAY(1); ++ if (!(READ_REG_0(sc, reg) & HIFN_PUCTRL_RESET)) ++ break; ++ } ++ if (!i) ++ device_printf(sc->sc_dev, "proc unit did not reset(0x%x)\n", ++ READ_REG_0(sc, HIFN_0_PUCTRL)); ++} ++ ++/* ++ * Reset the processing unit. ++ */ ++static void ++hifn_reset_puc(struct hifn_softc *sc) ++{ ++ /* Reset processing unit */ ++ int reg = HIFN_0_PUCTRL; ++ ++ if (sc->sc_flags & HIFN_IS_7956) { ++ reg = HIFN_0_PUCTRL2; ++ } ++ WRITE_REG_0(sc, reg, HIFN_PUCTRL_DMAENA); ++ ++ hifn_puc_wait(sc); ++} ++ ++/* ++ * Set the Retry and TRDY registers; note that we set them to ++ * zero because the 7811 locks up when forced to retry (section ++ * 3.6 of "Specification Update SU-0014-04". Not clear if we ++ * should do this for all Hifn parts, but it doesn't seem to hurt. ++ */ ++static void ++hifn_set_retry(struct hifn_softc *sc) ++{ ++ DPRINTF("%s()\n", __FUNCTION__); ++ /* NB: RETRY only responds to 8-bit reads/writes */ ++ pci_write_config_byte(sc->sc_pcidev, HIFN_RETRY_TIMEOUT, 0); ++ pci_write_config_byte(sc->sc_pcidev, HIFN_TRDY_TIMEOUT, 0); ++ /* piggy back the cache line setting here */ ++ pci_write_config_byte(sc->sc_pcidev, PCI_CACHE_LINE_SIZE, hifn_cache_linesize); ++} ++ ++/* ++ * Resets the board. Values in the regesters are left as is ++ * from the reset (i.e. initial values are assigned elsewhere). ++ */ ++static void ++hifn_reset_board(struct hifn_softc *sc, int full) ++{ ++ u_int32_t reg; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ /* ++ * Set polling in the DMA configuration register to zero. 0x7 avoids ++ * resetting the board and zeros out the other fields. ++ */ ++ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | ++ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); ++ ++ /* ++ * Now that polling has been disabled, we have to wait 1 ms ++ * before resetting the board. ++ */ ++ DELAY(1000); ++ ++ /* Reset the DMA unit */ ++ if (full) { ++ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE); ++ DELAY(1000); ++ } else { ++ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, ++ HIFN_DMACNFG_MODE | HIFN_DMACNFG_MSTRESET); ++ hifn_reset_puc(sc); ++ } ++ ++ KASSERT(sc->sc_dma != NULL, ("hifn_reset_board: null DMA tag!")); ++ bzero(sc->sc_dma, sizeof(*sc->sc_dma)); ++ ++ /* Bring dma unit out of reset */ ++ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | ++ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); ++ ++ hifn_puc_wait(sc); ++ hifn_set_retry(sc); ++ ++ if (sc->sc_flags & HIFN_IS_7811) { ++ for (reg = 0; reg < 1000; reg++) { ++ if (READ_REG_1(sc, HIFN_1_7811_MIPSRST) & ++ HIFN_MIPSRST_CRAMINIT) ++ break; ++ DELAY(1000); ++ } ++ if (reg == 1000) ++ device_printf(sc->sc_dev, ": cram init timeout\n"); ++ } else { ++ /* set up DMA configuration register #2 */ ++ /* turn off all PK and BAR0 swaps */ ++ WRITE_REG_1(sc, HIFN_1_DMA_CNFG2, ++ (3 << HIFN_DMACNFG2_INIT_WRITE_BURST_SHIFT)| ++ (3 << HIFN_DMACNFG2_INIT_READ_BURST_SHIFT)| ++ (2 << HIFN_DMACNFG2_TGT_WRITE_BURST_SHIFT)| ++ (2 << HIFN_DMACNFG2_TGT_READ_BURST_SHIFT)); ++ } ++} ++ ++static u_int32_t ++hifn_next_signature(u_int32_t a, u_int cnt) ++{ ++ int i; ++ u_int32_t v; ++ ++ for (i = 0; i < cnt; i++) { ++ ++ /* get the parity */ ++ v = a & 0x80080125; ++ v ^= v >> 16; ++ v ^= v >> 8; ++ v ^= v >> 4; ++ v ^= v >> 2; ++ v ^= v >> 1; ++ ++ a = (v & 1) ^ (a << 1); ++ } ++ ++ return a; ++} ++ ++ ++/* ++ * Checks to see if crypto is already enabled. If crypto isn't enable, ++ * "hifn_enable_crypto" is called to enable it. The check is important, ++ * as enabling crypto twice will lock the board. ++ */ ++static int ++hifn_enable_crypto(struct hifn_softc *sc) ++{ ++ u_int32_t dmacfg, ramcfg, encl, addr, i; ++ char offtbl[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00 }; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ ramcfg = READ_REG_0(sc, HIFN_0_PUCNFG); ++ dmacfg = READ_REG_1(sc, HIFN_1_DMA_CNFG); ++ ++ /* ++ * The RAM config register's encrypt level bit needs to be set before ++ * every read performed on the encryption level register. ++ */ ++ WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); ++ ++ encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; ++ ++ /* ++ * Make sure we don't re-unlock. Two unlocks kills chip until the ++ * next reboot. ++ */ ++ if (encl == HIFN_PUSTAT_ENA_1 || encl == HIFN_PUSTAT_ENA_2) { ++#ifdef HIFN_DEBUG ++ if (hifn_debug) ++ device_printf(sc->sc_dev, ++ "Strong crypto already enabled!\n"); ++#endif ++ goto report; ++ } ++ ++ if (encl != 0 && encl != HIFN_PUSTAT_ENA_0) { ++#ifdef HIFN_DEBUG ++ if (hifn_debug) ++ device_printf(sc->sc_dev, ++ "Unknown encryption level 0x%x\n", encl); ++#endif ++ return 1; ++ } ++ ++ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_UNLOCK | ++ HIFN_DMACNFG_MSTRESET | HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); ++ DELAY(1000); ++ addr = READ_REG_1(sc, HIFN_UNLOCK_SECRET1); ++ DELAY(1000); ++ WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, 0); ++ DELAY(1000); ++ ++ for (i = 0; i <= 12; i++) { ++ addr = hifn_next_signature(addr, offtbl[i] + 0x101); ++ WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, addr); ++ ++ DELAY(1000); ++ } ++ ++ WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); ++ encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; ++ ++#ifdef HIFN_DEBUG ++ if (hifn_debug) { ++ if (encl != HIFN_PUSTAT_ENA_1 && encl != HIFN_PUSTAT_ENA_2) ++ device_printf(sc->sc_dev, "Engine is permanently " ++ "locked until next system reset!\n"); ++ else ++ device_printf(sc->sc_dev, "Engine enabled " ++ "successfully!\n"); ++ } ++#endif ++ ++report: ++ WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg); ++ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, dmacfg); ++ ++ switch (encl) { ++ case HIFN_PUSTAT_ENA_1: ++ case HIFN_PUSTAT_ENA_2: ++ break; ++ case HIFN_PUSTAT_ENA_0: ++ default: ++ device_printf(sc->sc_dev, "disabled\n"); ++ break; ++ } ++ ++ return 0; ++} ++ ++/* ++ * Give initial values to the registers listed in the "Register Space" ++ * section of the HIFN Software Development reference manual. ++ */ ++static void ++hifn_init_pci_registers(struct hifn_softc *sc) ++{ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ /* write fixed values needed by the Initialization registers */ ++ WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA); ++ WRITE_REG_0(sc, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD); ++ WRITE_REG_0(sc, HIFN_0_PUIER, HIFN_PUIER_DSTOVER); ++ ++ /* write all 4 ring address registers */ ++ WRITE_REG_1(sc, HIFN_1_DMA_CRAR, sc->sc_dma_physaddr + ++ offsetof(struct hifn_dma, cmdr[0])); ++ WRITE_REG_1(sc, HIFN_1_DMA_SRAR, sc->sc_dma_physaddr + ++ offsetof(struct hifn_dma, srcr[0])); ++ WRITE_REG_1(sc, HIFN_1_DMA_DRAR, sc->sc_dma_physaddr + ++ offsetof(struct hifn_dma, dstr[0])); ++ WRITE_REG_1(sc, HIFN_1_DMA_RRAR, sc->sc_dma_physaddr + ++ offsetof(struct hifn_dma, resr[0])); ++ ++ DELAY(2000); ++ ++ /* write status register */ ++ WRITE_REG_1(sc, HIFN_1_DMA_CSR, ++ HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS | ++ HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS | ++ HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST | ++ HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER | ++ HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST | ++ HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER | ++ HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST | ++ HIFN_DMACSR_S_WAIT | ++ HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST | ++ HIFN_DMACSR_C_WAIT | ++ HIFN_DMACSR_ENGINE | ++ ((sc->sc_flags & HIFN_HAS_PUBLIC) ? ++ HIFN_DMACSR_PUBDONE : 0) | ++ ((sc->sc_flags & HIFN_IS_7811) ? ++ HIFN_DMACSR_ILLW | HIFN_DMACSR_ILLR : 0)); ++ ++ sc->sc_d_busy = sc->sc_r_busy = sc->sc_s_busy = sc->sc_c_busy = 0; ++ sc->sc_dmaier |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT | ++ HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER | ++ HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT | ++ ((sc->sc_flags & HIFN_IS_7811) ? ++ HIFN_DMAIER_ILLW | HIFN_DMAIER_ILLR : 0); ++ sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; ++ WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); ++ ++ ++ if (sc->sc_flags & HIFN_IS_7956) { ++ u_int32_t pll; ++ ++ WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING | ++ HIFN_PUCNFG_TCALLPHASES | ++ HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32); ++ ++ /* turn off the clocks and insure bypass is set */ ++ pll = READ_REG_1(sc, HIFN_1_PLL); ++ pll = (pll &~ (HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL)) ++ | HIFN_PLL_BP | HIFN_PLL_MBSET; ++ WRITE_REG_1(sc, HIFN_1_PLL, pll); ++ DELAY(10*1000); /* 10ms */ ++ ++ /* change configuration */ ++ pll = (pll &~ HIFN_PLL_CONFIG) | sc->sc_pllconfig; ++ WRITE_REG_1(sc, HIFN_1_PLL, pll); ++ DELAY(10*1000); /* 10ms */ ++ ++ /* disable bypass */ ++ pll &= ~HIFN_PLL_BP; ++ WRITE_REG_1(sc, HIFN_1_PLL, pll); ++ /* enable clocks with new configuration */ ++ pll |= HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL; ++ WRITE_REG_1(sc, HIFN_1_PLL, pll); ++ } else { ++ WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING | ++ HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES | ++ HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 | ++ (sc->sc_drammodel ? HIFN_PUCNFG_DRAM : HIFN_PUCNFG_SRAM)); ++ } ++ ++ WRITE_REG_0(sc, HIFN_0_PUISR, HIFN_PUISR_DSTOVER); ++ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | ++ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST | ++ ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) | ++ ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL)); ++} ++ ++/* ++ * The maximum number of sessions supported by the card ++ * is dependent on the amount of context ram, which ++ * encryption algorithms are enabled, and how compression ++ * is configured. This should be configured before this ++ * routine is called. ++ */ ++static void ++hifn_sessions(struct hifn_softc *sc) ++{ ++ u_int32_t pucnfg; ++ int ctxsize; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ pucnfg = READ_REG_0(sc, HIFN_0_PUCNFG); ++ ++ if (pucnfg & HIFN_PUCNFG_COMPSING) { ++ if (pucnfg & HIFN_PUCNFG_ENCCNFG) ++ ctxsize = 128; ++ else ++ ctxsize = 512; ++ /* ++ * 7955/7956 has internal context memory of 32K ++ */ ++ if (sc->sc_flags & HIFN_IS_7956) ++ sc->sc_maxses = 32768 / ctxsize; ++ else ++ sc->sc_maxses = 1 + ++ ((sc->sc_ramsize - 32768) / ctxsize); ++ } else ++ sc->sc_maxses = sc->sc_ramsize / 16384; ++ ++ if (sc->sc_maxses > 2048) ++ sc->sc_maxses = 2048; ++} ++ ++/* ++ * Determine ram type (sram or dram). Board should be just out of a reset ++ * state when this is called. ++ */ ++static int ++hifn_ramtype(struct hifn_softc *sc) ++{ ++ u_int8_t data[8], dataexpect[8]; ++ int i; ++ ++ for (i = 0; i < sizeof(data); i++) ++ data[i] = dataexpect[i] = 0x55; ++ if (hifn_writeramaddr(sc, 0, data)) ++ return (-1); ++ if (hifn_readramaddr(sc, 0, data)) ++ return (-1); ++ if (bcmp(data, dataexpect, sizeof(data)) != 0) { ++ sc->sc_drammodel = 1; ++ return (0); ++ } ++ ++ for (i = 0; i < sizeof(data); i++) ++ data[i] = dataexpect[i] = 0xaa; ++ if (hifn_writeramaddr(sc, 0, data)) ++ return (-1); ++ if (hifn_readramaddr(sc, 0, data)) ++ return (-1); ++ if (bcmp(data, dataexpect, sizeof(data)) != 0) { ++ sc->sc_drammodel = 1; ++ return (0); ++ } ++ ++ return (0); ++} ++ ++#define HIFN_SRAM_MAX (32 << 20) ++#define HIFN_SRAM_STEP_SIZE 16384 ++#define HIFN_SRAM_GRANULARITY (HIFN_SRAM_MAX / HIFN_SRAM_STEP_SIZE) ++ ++static int ++hifn_sramsize(struct hifn_softc *sc) ++{ ++ u_int32_t a; ++ u_int8_t data[8]; ++ u_int8_t dataexpect[sizeof(data)]; ++ int32_t i; ++ ++ for (i = 0; i < sizeof(data); i++) ++ data[i] = dataexpect[i] = i ^ 0x5a; ++ ++ for (i = HIFN_SRAM_GRANULARITY - 1; i >= 0; i--) { ++ a = i * HIFN_SRAM_STEP_SIZE; ++ bcopy(&i, data, sizeof(i)); ++ hifn_writeramaddr(sc, a, data); ++ } ++ ++ for (i = 0; i < HIFN_SRAM_GRANULARITY; i++) { ++ a = i * HIFN_SRAM_STEP_SIZE; ++ bcopy(&i, dataexpect, sizeof(i)); ++ if (hifn_readramaddr(sc, a, data) < 0) ++ return (0); ++ if (bcmp(data, dataexpect, sizeof(data)) != 0) ++ return (0); ++ sc->sc_ramsize = a + HIFN_SRAM_STEP_SIZE; ++ } ++ ++ return (0); ++} ++ ++/* ++ * XXX For dram boards, one should really try all of the ++ * HIFN_PUCNFG_DSZ_*'s. This just assumes that PUCNFG ++ * is already set up correctly. ++ */ ++static int ++hifn_dramsize(struct hifn_softc *sc) ++{ ++ u_int32_t cnfg; ++ ++ if (sc->sc_flags & HIFN_IS_7956) { ++ /* ++ * 7955/7956 have a fixed internal ram of only 32K. ++ */ ++ sc->sc_ramsize = 32768; ++ } else { ++ cnfg = READ_REG_0(sc, HIFN_0_PUCNFG) & ++ HIFN_PUCNFG_DRAMMASK; ++ sc->sc_ramsize = 1 << ((cnfg >> 13) + 18); ++ } ++ return (0); ++} ++ ++static void ++hifn_alloc_slot(struct hifn_softc *sc, int *cmdp, int *srcp, int *dstp, int *resp) ++{ ++ struct hifn_dma *dma = sc->sc_dma; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ if (dma->cmdi == HIFN_D_CMD_RSIZE) { ++ dma->cmdi = 0; ++ dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); ++ wmb(); ++ dma->cmdr[HIFN_D_CMD_RSIZE].l |= htole32(HIFN_D_VALID); ++ HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, ++ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); ++ } ++ *cmdp = dma->cmdi++; ++ dma->cmdk = dma->cmdi; ++ ++ if (dma->srci == HIFN_D_SRC_RSIZE) { ++ dma->srci = 0; ++ dma->srcr[HIFN_D_SRC_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); ++ wmb(); ++ dma->srcr[HIFN_D_SRC_RSIZE].l |= htole32(HIFN_D_VALID); ++ HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, ++ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); ++ } ++ *srcp = dma->srci++; ++ dma->srck = dma->srci; ++ ++ if (dma->dsti == HIFN_D_DST_RSIZE) { ++ dma->dsti = 0; ++ dma->dstr[HIFN_D_DST_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); ++ wmb(); ++ dma->dstr[HIFN_D_DST_RSIZE].l |= htole32(HIFN_D_VALID); ++ HIFN_DSTR_SYNC(sc, HIFN_D_DST_RSIZE, ++ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); ++ } ++ *dstp = dma->dsti++; ++ dma->dstk = dma->dsti; ++ ++ if (dma->resi == HIFN_D_RES_RSIZE) { ++ dma->resi = 0; ++ dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); ++ wmb(); ++ dma->resr[HIFN_D_RES_RSIZE].l |= htole32(HIFN_D_VALID); ++ HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, ++ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); ++ } ++ *resp = dma->resi++; ++ dma->resk = dma->resi; ++} ++ ++static int ++hifn_writeramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) ++{ ++ struct hifn_dma *dma = sc->sc_dma; ++ hifn_base_command_t wc; ++ const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; ++ int r, cmdi, resi, srci, dsti; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ wc.masks = htole16(3 << 13); ++ wc.session_num = htole16(addr >> 14); ++ wc.total_source_count = htole16(8); ++ wc.total_dest_count = htole16(addr & 0x3fff); ++ ++ hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); ++ ++ WRITE_REG_1(sc, HIFN_1_DMA_CSR, ++ HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | ++ HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); ++ ++ /* build write command */ ++ bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); ++ *(hifn_base_command_t *)dma->command_bufs[cmdi] = wc; ++ bcopy(data, &dma->test_src, sizeof(dma->test_src)); ++ ++ dma->srcr[srci].p = htole32(sc->sc_dma_physaddr ++ + offsetof(struct hifn_dma, test_src)); ++ dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr ++ + offsetof(struct hifn_dma, test_dst)); ++ ++ dma->cmdr[cmdi].l = htole32(16 | masks); ++ dma->srcr[srci].l = htole32(8 | masks); ++ dma->dstr[dsti].l = htole32(4 | masks); ++ dma->resr[resi].l = htole32(4 | masks); ++ ++ for (r = 10000; r >= 0; r--) { ++ DELAY(10); ++ if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) ++ break; ++ } ++ if (r == 0) { ++ device_printf(sc->sc_dev, "writeramaddr -- " ++ "result[%d](addr %d) still valid\n", resi, addr); ++ r = -1; ++ return (-1); ++ } else ++ r = 0; ++ ++ WRITE_REG_1(sc, HIFN_1_DMA_CSR, ++ HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | ++ HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); ++ ++ return (r); ++} ++ ++static int ++hifn_readramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) ++{ ++ struct hifn_dma *dma = sc->sc_dma; ++ hifn_base_command_t rc; ++ const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; ++ int r, cmdi, srci, dsti, resi; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ rc.masks = htole16(2 << 13); ++ rc.session_num = htole16(addr >> 14); ++ rc.total_source_count = htole16(addr & 0x3fff); ++ rc.total_dest_count = htole16(8); ++ ++ hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); ++ ++ WRITE_REG_1(sc, HIFN_1_DMA_CSR, ++ HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | ++ HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); ++ ++ bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); ++ *(hifn_base_command_t *)dma->command_bufs[cmdi] = rc; ++ ++ dma->srcr[srci].p = htole32(sc->sc_dma_physaddr + ++ offsetof(struct hifn_dma, test_src)); ++ dma->test_src = 0; ++ dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr + ++ offsetof(struct hifn_dma, test_dst)); ++ dma->test_dst = 0; ++ dma->cmdr[cmdi].l = htole32(8 | masks); ++ dma->srcr[srci].l = htole32(8 | masks); ++ dma->dstr[dsti].l = htole32(8 | masks); ++ dma->resr[resi].l = htole32(HIFN_MAX_RESULT | masks); ++ ++ for (r = 10000; r >= 0; r--) { ++ DELAY(10); ++ if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) ++ break; ++ } ++ if (r == 0) { ++ device_printf(sc->sc_dev, "readramaddr -- " ++ "result[%d](addr %d) still valid\n", resi, addr); ++ r = -1; ++ } else { ++ r = 0; ++ bcopy(&dma->test_dst, data, sizeof(dma->test_dst)); ++ } ++ ++ WRITE_REG_1(sc, HIFN_1_DMA_CSR, ++ HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | ++ HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); ++ ++ return (r); ++} ++ ++/* ++ * Initialize the descriptor rings. ++ */ ++static void ++hifn_init_dma(struct hifn_softc *sc) ++{ ++ struct hifn_dma *dma = sc->sc_dma; ++ int i; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ hifn_set_retry(sc); ++ ++ /* initialize static pointer values */ ++ for (i = 0; i < HIFN_D_CMD_RSIZE; i++) ++ dma->cmdr[i].p = htole32(sc->sc_dma_physaddr + ++ offsetof(struct hifn_dma, command_bufs[i][0])); ++ for (i = 0; i < HIFN_D_RES_RSIZE; i++) ++ dma->resr[i].p = htole32(sc->sc_dma_physaddr + ++ offsetof(struct hifn_dma, result_bufs[i][0])); ++ ++ dma->cmdr[HIFN_D_CMD_RSIZE].p = ++ htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, cmdr[0])); ++ dma->srcr[HIFN_D_SRC_RSIZE].p = ++ htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, srcr[0])); ++ dma->dstr[HIFN_D_DST_RSIZE].p = ++ htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, dstr[0])); ++ dma->resr[HIFN_D_RES_RSIZE].p = ++ htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, resr[0])); ++ ++ dma->cmdu = dma->srcu = dma->dstu = dma->resu = 0; ++ dma->cmdi = dma->srci = dma->dsti = dma->resi = 0; ++ dma->cmdk = dma->srck = dma->dstk = dma->resk = 0; ++} ++ ++/* ++ * Writes out the raw command buffer space. Returns the ++ * command buffer size. ++ */ ++static u_int ++hifn_write_command(struct hifn_command *cmd, u_int8_t *buf) ++{ ++ struct hifn_softc *sc = NULL; ++ u_int8_t *buf_pos; ++ hifn_base_command_t *base_cmd; ++ hifn_mac_command_t *mac_cmd; ++ hifn_crypt_command_t *cry_cmd; ++ int using_mac, using_crypt, len, ivlen; ++ u_int32_t dlen, slen; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ buf_pos = buf; ++ using_mac = cmd->base_masks & HIFN_BASE_CMD_MAC; ++ using_crypt = cmd->base_masks & HIFN_BASE_CMD_CRYPT; ++ ++ base_cmd = (hifn_base_command_t *)buf_pos; ++ base_cmd->masks = htole16(cmd->base_masks); ++ slen = cmd->src_mapsize; ++ if (cmd->sloplen) ++ dlen = cmd->dst_mapsize - cmd->sloplen + sizeof(u_int32_t); ++ else ++ dlen = cmd->dst_mapsize; ++ base_cmd->total_source_count = htole16(slen & HIFN_BASE_CMD_LENMASK_LO); ++ base_cmd->total_dest_count = htole16(dlen & HIFN_BASE_CMD_LENMASK_LO); ++ dlen >>= 16; ++ slen >>= 16; ++ base_cmd->session_num = htole16( ++ ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) | ++ ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M)); ++ buf_pos += sizeof(hifn_base_command_t); ++ ++ if (using_mac) { ++ mac_cmd = (hifn_mac_command_t *)buf_pos; ++ dlen = cmd->maccrd->crd_len; ++ mac_cmd->source_count = htole16(dlen & 0xffff); ++ dlen >>= 16; ++ mac_cmd->masks = htole16(cmd->mac_masks | ++ ((dlen << HIFN_MAC_CMD_SRCLEN_S) & HIFN_MAC_CMD_SRCLEN_M)); ++ mac_cmd->header_skip = htole16(cmd->maccrd->crd_skip); ++ mac_cmd->reserved = 0; ++ buf_pos += sizeof(hifn_mac_command_t); ++ } ++ ++ if (using_crypt) { ++ cry_cmd = (hifn_crypt_command_t *)buf_pos; ++ dlen = cmd->enccrd->crd_len; ++ cry_cmd->source_count = htole16(dlen & 0xffff); ++ dlen >>= 16; ++ cry_cmd->masks = htole16(cmd->cry_masks | ++ ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) & HIFN_CRYPT_CMD_SRCLEN_M)); ++ cry_cmd->header_skip = htole16(cmd->enccrd->crd_skip); ++ cry_cmd->reserved = 0; ++ buf_pos += sizeof(hifn_crypt_command_t); ++ } ++ ++ if (using_mac && cmd->mac_masks & HIFN_MAC_CMD_NEW_KEY) { ++ bcopy(cmd->mac, buf_pos, HIFN_MAC_KEY_LENGTH); ++ buf_pos += HIFN_MAC_KEY_LENGTH; ++ } ++ ++ if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_KEY) { ++ switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) { ++ case HIFN_CRYPT_CMD_ALG_3DES: ++ bcopy(cmd->ck, buf_pos, HIFN_3DES_KEY_LENGTH); ++ buf_pos += HIFN_3DES_KEY_LENGTH; ++ break; ++ case HIFN_CRYPT_CMD_ALG_DES: ++ bcopy(cmd->ck, buf_pos, HIFN_DES_KEY_LENGTH); ++ buf_pos += HIFN_DES_KEY_LENGTH; ++ break; ++ case HIFN_CRYPT_CMD_ALG_RC4: ++ len = 256; ++ do { ++ int clen; ++ ++ clen = MIN(cmd->cklen, len); ++ bcopy(cmd->ck, buf_pos, clen); ++ len -= clen; ++ buf_pos += clen; ++ } while (len > 0); ++ bzero(buf_pos, 4); ++ buf_pos += 4; ++ break; ++ case HIFN_CRYPT_CMD_ALG_AES: ++ /* ++ * AES keys are variable 128, 192 and ++ * 256 bits (16, 24 and 32 bytes). ++ */ ++ bcopy(cmd->ck, buf_pos, cmd->cklen); ++ buf_pos += cmd->cklen; ++ break; ++ } ++ } ++ ++ if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_IV) { ++ switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) { ++ case HIFN_CRYPT_CMD_ALG_AES: ++ ivlen = HIFN_AES_IV_LENGTH; ++ break; ++ default: ++ ivlen = HIFN_IV_LENGTH; ++ break; ++ } ++ bcopy(cmd->iv, buf_pos, ivlen); ++ buf_pos += ivlen; ++ } ++ ++ if ((cmd->base_masks & (HIFN_BASE_CMD_MAC|HIFN_BASE_CMD_CRYPT)) == 0) { ++ bzero(buf_pos, 8); ++ buf_pos += 8; ++ } ++ ++ return (buf_pos - buf); ++} ++ ++static int ++hifn_dmamap_aligned(struct hifn_operand *op) ++{ ++ struct hifn_softc *sc = NULL; ++ int i; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ for (i = 0; i < op->nsegs; i++) { ++ if (op->segs[i].ds_addr & 3) ++ return (0); ++ if ((i != (op->nsegs - 1)) && (op->segs[i].ds_len & 3)) ++ return (0); ++ } ++ return (1); ++} ++ ++static __inline int ++hifn_dmamap_dstwrap(struct hifn_softc *sc, int idx) ++{ ++ struct hifn_dma *dma = sc->sc_dma; ++ ++ if (++idx == HIFN_D_DST_RSIZE) { ++ dma->dstr[idx].l = htole32(HIFN_D_VALID | HIFN_D_JUMP | ++ HIFN_D_MASKDONEIRQ); ++ HIFN_DSTR_SYNC(sc, idx, ++ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ++ idx = 0; ++ } ++ return (idx); ++} ++ ++static int ++hifn_dmamap_load_dst(struct hifn_softc *sc, struct hifn_command *cmd) ++{ ++ struct hifn_dma *dma = sc->sc_dma; ++ struct hifn_operand *dst = &cmd->dst; ++ u_int32_t p, l; ++ int idx, used = 0, i; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ idx = dma->dsti; ++ for (i = 0; i < dst->nsegs - 1; i++) { ++ dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); ++ dma->dstr[idx].l = htole32(HIFN_D_MASKDONEIRQ | dst->segs[i].ds_len); ++ wmb(); ++ dma->dstr[idx].l |= htole32(HIFN_D_VALID); ++ HIFN_DSTR_SYNC(sc, idx, ++ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ++ used++; ++ ++ idx = hifn_dmamap_dstwrap(sc, idx); ++ } ++ ++ if (cmd->sloplen == 0) { ++ p = dst->segs[i].ds_addr; ++ l = HIFN_D_MASKDONEIRQ | HIFN_D_LAST | ++ dst->segs[i].ds_len; ++ } else { ++ p = sc->sc_dma_physaddr + ++ offsetof(struct hifn_dma, slop[cmd->slopidx]); ++ l = HIFN_D_MASKDONEIRQ | HIFN_D_LAST | ++ sizeof(u_int32_t); ++ ++ if ((dst->segs[i].ds_len - cmd->sloplen) != 0) { ++ dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); ++ dma->dstr[idx].l = htole32(HIFN_D_MASKDONEIRQ | ++ (dst->segs[i].ds_len - cmd->sloplen)); ++ wmb(); ++ dma->dstr[idx].l |= htole32(HIFN_D_VALID); ++ HIFN_DSTR_SYNC(sc, idx, ++ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ++ used++; ++ ++ idx = hifn_dmamap_dstwrap(sc, idx); ++ } ++ } ++ dma->dstr[idx].p = htole32(p); ++ dma->dstr[idx].l = htole32(l); ++ wmb(); ++ dma->dstr[idx].l |= htole32(HIFN_D_VALID); ++ HIFN_DSTR_SYNC(sc, idx, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ++ used++; ++ ++ idx = hifn_dmamap_dstwrap(sc, idx); ++ ++ dma->dsti = idx; ++ dma->dstu += used; ++ return (idx); ++} ++ ++static __inline int ++hifn_dmamap_srcwrap(struct hifn_softc *sc, int idx) ++{ ++ struct hifn_dma *dma = sc->sc_dma; ++ ++ if (++idx == HIFN_D_SRC_RSIZE) { ++ dma->srcr[idx].l = htole32(HIFN_D_VALID | ++ HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); ++ HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, ++ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); ++ idx = 0; ++ } ++ return (idx); ++} ++ ++static int ++hifn_dmamap_load_src(struct hifn_softc *sc, struct hifn_command *cmd) ++{ ++ struct hifn_dma *dma = sc->sc_dma; ++ struct hifn_operand *src = &cmd->src; ++ int idx, i; ++ u_int32_t last = 0; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ idx = dma->srci; ++ for (i = 0; i < src->nsegs; i++) { ++ if (i == src->nsegs - 1) ++ last = HIFN_D_LAST; ++ ++ dma->srcr[idx].p = htole32(src->segs[i].ds_addr); ++ dma->srcr[idx].l = htole32(src->segs[i].ds_len | ++ HIFN_D_MASKDONEIRQ | last); ++ wmb(); ++ dma->srcr[idx].l |= htole32(HIFN_D_VALID); ++ HIFN_SRCR_SYNC(sc, idx, ++ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); ++ ++ idx = hifn_dmamap_srcwrap(sc, idx); ++ } ++ dma->srci = idx; ++ dma->srcu += src->nsegs; ++ return (idx); ++} ++ ++ ++static int ++hifn_crypto( ++ struct hifn_softc *sc, ++ struct hifn_command *cmd, ++ struct cryptop *crp, ++ int hint) ++{ ++ struct hifn_dma *dma = sc->sc_dma; ++ u_int32_t cmdlen, csr; ++ int cmdi, resi, err = 0; ++ unsigned long l_flags; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ /* ++ * need 1 cmd, and 1 res ++ * ++ * NB: check this first since it's easy. ++ */ ++ HIFN_LOCK(sc); ++ if ((dma->cmdu + 1) > HIFN_D_CMD_RSIZE || ++ (dma->resu + 1) > HIFN_D_RES_RSIZE) { ++#ifdef HIFN_DEBUG ++ if (hifn_debug) { ++ device_printf(sc->sc_dev, ++ "cmd/result exhaustion, cmdu %u resu %u\n", ++ dma->cmdu, dma->resu); ++ } ++#endif ++ hifnstats.hst_nomem_cr++; ++ sc->sc_needwakeup |= CRYPTO_SYMQ; ++ HIFN_UNLOCK(sc); ++ return (ERESTART); ++ } ++ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ if (pci_map_skb(sc, &cmd->src, cmd->src_skb)) { ++ hifnstats.hst_nomem_load++; ++ err = ENOMEM; ++ goto err_srcmap1; ++ } ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ if (pci_map_uio(sc, &cmd->src, cmd->src_io)) { ++ hifnstats.hst_nomem_load++; ++ err = ENOMEM; ++ goto err_srcmap1; ++ } ++ } else { ++ if (pci_map_buf(sc, &cmd->src, cmd->src_buf, crp->crp_ilen)) { ++ hifnstats.hst_nomem_load++; ++ err = ENOMEM; ++ goto err_srcmap1; ++ } ++ } ++ ++ if (hifn_dmamap_aligned(&cmd->src)) { ++ cmd->sloplen = cmd->src_mapsize & 3; ++ cmd->dst = cmd->src; ++ } else { ++ if (crp->crp_flags & CRYPTO_F_IOV) { ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ err = EINVAL; ++ goto err_srcmap; ++ } else if (crp->crp_flags & CRYPTO_F_SKBUF) { ++#ifdef NOTYET ++ int totlen, len; ++ struct mbuf *m, *m0, *mlast; ++ ++ KASSERT(cmd->dst_m == cmd->src_m, ++ ("hifn_crypto: dst_m initialized improperly")); ++ hifnstats.hst_unaligned++; ++ /* ++ * Source is not aligned on a longword boundary. ++ * Copy the data to insure alignment. If we fail ++ * to allocate mbufs or clusters while doing this ++ * we return ERESTART so the operation is requeued ++ * at the crypto later, but only if there are ++ * ops already posted to the hardware; otherwise we ++ * have no guarantee that we'll be re-entered. ++ */ ++ totlen = cmd->src_mapsize; ++ if (cmd->src_m->m_flags & M_PKTHDR) { ++ len = MHLEN; ++ MGETHDR(m0, M_DONTWAIT, MT_DATA); ++ if (m0 && !m_dup_pkthdr(m0, cmd->src_m, M_DONTWAIT)) { ++ m_free(m0); ++ m0 = NULL; ++ } ++ } else { ++ len = MLEN; ++ MGET(m0, M_DONTWAIT, MT_DATA); ++ } ++ if (m0 == NULL) { ++ hifnstats.hst_nomem_mbuf++; ++ err = dma->cmdu ? ERESTART : ENOMEM; ++ goto err_srcmap; ++ } ++ if (totlen >= MINCLSIZE) { ++ MCLGET(m0, M_DONTWAIT); ++ if ((m0->m_flags & M_EXT) == 0) { ++ hifnstats.hst_nomem_mcl++; ++ err = dma->cmdu ? ERESTART : ENOMEM; ++ m_freem(m0); ++ goto err_srcmap; ++ } ++ len = MCLBYTES; ++ } ++ totlen -= len; ++ m0->m_pkthdr.len = m0->m_len = len; ++ mlast = m0; ++ ++ while (totlen > 0) { ++ MGET(m, M_DONTWAIT, MT_DATA); ++ if (m == NULL) { ++ hifnstats.hst_nomem_mbuf++; ++ err = dma->cmdu ? ERESTART : ENOMEM; ++ m_freem(m0); ++ goto err_srcmap; ++ } ++ len = MLEN; ++ if (totlen >= MINCLSIZE) { ++ MCLGET(m, M_DONTWAIT); ++ if ((m->m_flags & M_EXT) == 0) { ++ hifnstats.hst_nomem_mcl++; ++ err = dma->cmdu ? ERESTART : ENOMEM; ++ mlast->m_next = m; ++ m_freem(m0); ++ goto err_srcmap; ++ } ++ len = MCLBYTES; ++ } ++ ++ m->m_len = len; ++ m0->m_pkthdr.len += len; ++ totlen -= len; ++ ++ mlast->m_next = m; ++ mlast = m; ++ } ++ cmd->dst_m = m0; ++#else ++ device_printf(sc->sc_dev, ++ "%s,%d: CRYPTO_F_SKBUF unaligned not implemented\n", ++ __FILE__, __LINE__); ++ err = EINVAL; ++ goto err_srcmap; ++#endif ++ } else { ++ device_printf(sc->sc_dev, ++ "%s,%d: unaligned contig buffers not implemented\n", ++ __FILE__, __LINE__); ++ err = EINVAL; ++ goto err_srcmap; ++ } ++ } ++ ++ if (cmd->dst_map == NULL) { ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ if (pci_map_skb(sc, &cmd->dst, cmd->dst_skb)) { ++ hifnstats.hst_nomem_map++; ++ err = ENOMEM; ++ goto err_dstmap1; ++ } ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ if (pci_map_uio(sc, &cmd->dst, cmd->dst_io)) { ++ hifnstats.hst_nomem_load++; ++ err = ENOMEM; ++ goto err_dstmap1; ++ } ++ } else { ++ if (pci_map_buf(sc, &cmd->dst, cmd->dst_buf, crp->crp_ilen)) { ++ hifnstats.hst_nomem_load++; ++ err = ENOMEM; ++ goto err_dstmap1; ++ } ++ } ++ } ++ ++#ifdef HIFN_DEBUG ++ if (hifn_debug) { ++ device_printf(sc->sc_dev, ++ "Entering cmd: stat %8x ien %8x u %d/%d/%d/%d n %d/%d\n", ++ READ_REG_1(sc, HIFN_1_DMA_CSR), ++ READ_REG_1(sc, HIFN_1_DMA_IER), ++ dma->cmdu, dma->srcu, dma->dstu, dma->resu, ++ cmd->src_nsegs, cmd->dst_nsegs); ++ } ++#endif ++ ++#if 0 ++ if (cmd->src_map == cmd->dst_map) { ++ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, ++ BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); ++ } else { ++ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, ++ BUS_DMASYNC_PREWRITE); ++ bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, ++ BUS_DMASYNC_PREREAD); ++ } ++#endif ++ ++ /* ++ * need N src, and N dst ++ */ ++ if ((dma->srcu + cmd->src_nsegs) > HIFN_D_SRC_RSIZE || ++ (dma->dstu + cmd->dst_nsegs + 1) > HIFN_D_DST_RSIZE) { ++#ifdef HIFN_DEBUG ++ if (hifn_debug) { ++ device_printf(sc->sc_dev, ++ "src/dst exhaustion, srcu %u+%u dstu %u+%u\n", ++ dma->srcu, cmd->src_nsegs, ++ dma->dstu, cmd->dst_nsegs); ++ } ++#endif ++ hifnstats.hst_nomem_sd++; ++ err = ERESTART; ++ goto err_dstmap; ++ } ++ ++ if (dma->cmdi == HIFN_D_CMD_RSIZE) { ++ dma->cmdi = 0; ++ dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); ++ wmb(); ++ dma->cmdr[HIFN_D_CMD_RSIZE].l |= htole32(HIFN_D_VALID); ++ HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, ++ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); ++ } ++ cmdi = dma->cmdi++; ++ cmdlen = hifn_write_command(cmd, dma->command_bufs[cmdi]); ++ HIFN_CMD_SYNC(sc, cmdi, BUS_DMASYNC_PREWRITE); ++ ++ /* .p for command/result already set */ ++ dma->cmdr[cmdi].l = htole32(cmdlen | HIFN_D_LAST | ++ HIFN_D_MASKDONEIRQ); ++ wmb(); ++ dma->cmdr[cmdi].l |= htole32(HIFN_D_VALID); ++ HIFN_CMDR_SYNC(sc, cmdi, ++ BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); ++ dma->cmdu++; ++ ++ /* ++ * We don't worry about missing an interrupt (which a "command wait" ++ * interrupt salvages us from), unless there is more than one command ++ * in the queue. ++ */ ++ if (dma->cmdu > 1) { ++ sc->sc_dmaier |= HIFN_DMAIER_C_WAIT; ++ WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); ++ } ++ ++ hifnstats.hst_ipackets++; ++ hifnstats.hst_ibytes += cmd->src_mapsize; ++ ++ hifn_dmamap_load_src(sc, cmd); ++ ++ /* ++ * Unlike other descriptors, we don't mask done interrupt from ++ * result descriptor. ++ */ ++#ifdef HIFN_DEBUG ++ if (hifn_debug) ++ device_printf(sc->sc_dev, "load res\n"); ++#endif ++ if (dma->resi == HIFN_D_RES_RSIZE) { ++ dma->resi = 0; ++ dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_JUMP|HIFN_D_MASKDONEIRQ); ++ wmb(); ++ dma->resr[HIFN_D_RES_RSIZE].l |= htole32(HIFN_D_VALID); ++ HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, ++ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ++ } ++ resi = dma->resi++; ++ KASSERT(dma->hifn_commands[resi] == NULL, ++ ("hifn_crypto: command slot %u busy", resi)); ++ dma->hifn_commands[resi] = cmd; ++ HIFN_RES_SYNC(sc, resi, BUS_DMASYNC_PREREAD); ++ if ((hint & CRYPTO_HINT_MORE) && sc->sc_curbatch < hifn_maxbatch) { ++ dma->resr[resi].l = htole32(HIFN_MAX_RESULT | ++ HIFN_D_LAST | HIFN_D_MASKDONEIRQ); ++ wmb(); ++ dma->resr[resi].l |= htole32(HIFN_D_VALID); ++ sc->sc_curbatch++; ++ if (sc->sc_curbatch > hifnstats.hst_maxbatch) ++ hifnstats.hst_maxbatch = sc->sc_curbatch; ++ hifnstats.hst_totbatch++; ++ } else { ++ dma->resr[resi].l = htole32(HIFN_MAX_RESULT | HIFN_D_LAST); ++ wmb(); ++ dma->resr[resi].l |= htole32(HIFN_D_VALID); ++ sc->sc_curbatch = 0; ++ } ++ HIFN_RESR_SYNC(sc, resi, ++ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ++ dma->resu++; ++ ++ if (cmd->sloplen) ++ cmd->slopidx = resi; ++ ++ hifn_dmamap_load_dst(sc, cmd); ++ ++ csr = 0; ++ if (sc->sc_c_busy == 0) { ++ csr |= HIFN_DMACSR_C_CTRL_ENA; ++ sc->sc_c_busy = 1; ++ } ++ if (sc->sc_s_busy == 0) { ++ csr |= HIFN_DMACSR_S_CTRL_ENA; ++ sc->sc_s_busy = 1; ++ } ++ if (sc->sc_r_busy == 0) { ++ csr |= HIFN_DMACSR_R_CTRL_ENA; ++ sc->sc_r_busy = 1; ++ } ++ if (sc->sc_d_busy == 0) { ++ csr |= HIFN_DMACSR_D_CTRL_ENA; ++ sc->sc_d_busy = 1; ++ } ++ if (csr) ++ WRITE_REG_1(sc, HIFN_1_DMA_CSR, csr); ++ ++#ifdef HIFN_DEBUG ++ if (hifn_debug) { ++ device_printf(sc->sc_dev, "command: stat %8x ier %8x\n", ++ READ_REG_1(sc, HIFN_1_DMA_CSR), ++ READ_REG_1(sc, HIFN_1_DMA_IER)); ++ } ++#endif ++ ++ sc->sc_active = 5; ++ HIFN_UNLOCK(sc); ++ KASSERT(err == 0, ("hifn_crypto: success with error %u", err)); ++ return (err); /* success */ ++ ++err_dstmap: ++ if (cmd->src_map != cmd->dst_map) ++ pci_unmap_buf(sc, &cmd->dst); ++err_dstmap1: ++err_srcmap: ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ if (cmd->src_skb != cmd->dst_skb) ++#ifdef NOTYET ++ m_freem(cmd->dst_m); ++#else ++ device_printf(sc->sc_dev, ++ "%s,%d: CRYPTO_F_SKBUF src != dst not implemented\n", ++ __FILE__, __LINE__); ++#endif ++ } ++ pci_unmap_buf(sc, &cmd->src); ++err_srcmap1: ++ HIFN_UNLOCK(sc); ++ return (err); ++} ++ ++static void ++hifn_tick(unsigned long arg) ++{ ++ struct hifn_softc *sc; ++ unsigned long l_flags; ++ ++ if (arg >= HIFN_MAX_CHIPS) ++ return; ++ sc = hifn_chip_idx[arg]; ++ if (!sc) ++ return; ++ ++ HIFN_LOCK(sc); ++ if (sc->sc_active == 0) { ++ struct hifn_dma *dma = sc->sc_dma; ++ u_int32_t r = 0; ++ ++ if (dma->cmdu == 0 && sc->sc_c_busy) { ++ sc->sc_c_busy = 0; ++ r |= HIFN_DMACSR_C_CTRL_DIS; ++ } ++ if (dma->srcu == 0 && sc->sc_s_busy) { ++ sc->sc_s_busy = 0; ++ r |= HIFN_DMACSR_S_CTRL_DIS; ++ } ++ if (dma->dstu == 0 && sc->sc_d_busy) { ++ sc->sc_d_busy = 0; ++ r |= HIFN_DMACSR_D_CTRL_DIS; ++ } ++ if (dma->resu == 0 && sc->sc_r_busy) { ++ sc->sc_r_busy = 0; ++ r |= HIFN_DMACSR_R_CTRL_DIS; ++ } ++ if (r) ++ WRITE_REG_1(sc, HIFN_1_DMA_CSR, r); ++ } else ++ sc->sc_active--; ++ HIFN_UNLOCK(sc); ++ mod_timer(&sc->sc_tickto, jiffies + HZ); ++} ++ ++static irqreturn_t ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) ++hifn_intr(int irq, void *arg) ++#else ++hifn_intr(int irq, void *arg, struct pt_regs *regs) ++#endif ++{ ++ struct hifn_softc *sc = arg; ++ struct hifn_dma *dma; ++ u_int32_t dmacsr, restart; ++ int i, u; ++ unsigned long l_flags; ++ ++ dmacsr = READ_REG_1(sc, HIFN_1_DMA_CSR); ++ ++ /* Nothing in the DMA unit interrupted */ ++ if ((dmacsr & sc->sc_dmaier) == 0) ++ return IRQ_NONE; ++ ++ HIFN_LOCK(sc); ++ ++ dma = sc->sc_dma; ++ ++#ifdef HIFN_DEBUG ++ if (hifn_debug) { ++ device_printf(sc->sc_dev, ++ "irq: stat %08x ien %08x damier %08x i %d/%d/%d/%d k %d/%d/%d/%d u %d/%d/%d/%d\n", ++ dmacsr, READ_REG_1(sc, HIFN_1_DMA_IER), sc->sc_dmaier, ++ dma->cmdi, dma->srci, dma->dsti, dma->resi, ++ dma->cmdk, dma->srck, dma->dstk, dma->resk, ++ dma->cmdu, dma->srcu, dma->dstu, dma->resu); ++ } ++#endif ++ ++ WRITE_REG_1(sc, HIFN_1_DMA_CSR, dmacsr & sc->sc_dmaier); ++ ++ if ((sc->sc_flags & HIFN_HAS_PUBLIC) && ++ (dmacsr & HIFN_DMACSR_PUBDONE)) ++ WRITE_REG_1(sc, HIFN_1_PUB_STATUS, ++ READ_REG_1(sc, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE); ++ ++ restart = dmacsr & (HIFN_DMACSR_D_OVER | HIFN_DMACSR_R_OVER); ++ if (restart) ++ device_printf(sc->sc_dev, "overrun %x\n", dmacsr); ++ ++ if (sc->sc_flags & HIFN_IS_7811) { ++ if (dmacsr & HIFN_DMACSR_ILLR) ++ device_printf(sc->sc_dev, "illegal read\n"); ++ if (dmacsr & HIFN_DMACSR_ILLW) ++ device_printf(sc->sc_dev, "illegal write\n"); ++ } ++ ++ restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT | ++ HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT); ++ if (restart) { ++ device_printf(sc->sc_dev, "abort, resetting.\n"); ++ hifnstats.hst_abort++; ++ hifn_abort(sc); ++ HIFN_UNLOCK(sc); ++ return IRQ_HANDLED; ++ } ++ ++ if ((dmacsr & HIFN_DMACSR_C_WAIT) && (dma->cmdu == 0)) { ++ /* ++ * If no slots to process and we receive a "waiting on ++ * command" interrupt, we disable the "waiting on command" ++ * (by clearing it). ++ */ ++ sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; ++ WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); ++ } ++ ++ /* clear the rings */ ++ i = dma->resk; u = dma->resu; ++ while (u != 0) { ++ HIFN_RESR_SYNC(sc, i, ++ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); ++ if (dma->resr[i].l & htole32(HIFN_D_VALID)) { ++ HIFN_RESR_SYNC(sc, i, ++ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ++ break; ++ } ++ ++ if (i != HIFN_D_RES_RSIZE) { ++ struct hifn_command *cmd; ++ u_int8_t *macbuf = NULL; ++ ++ HIFN_RES_SYNC(sc, i, BUS_DMASYNC_POSTREAD); ++ cmd = dma->hifn_commands[i]; ++ KASSERT(cmd != NULL, ++ ("hifn_intr: null command slot %u", i)); ++ dma->hifn_commands[i] = NULL; ++ ++ if (cmd->base_masks & HIFN_BASE_CMD_MAC) { ++ macbuf = dma->result_bufs[i]; ++ macbuf += 12; ++ } ++ ++ hifn_callback(sc, cmd, macbuf); ++ hifnstats.hst_opackets++; ++ u--; ++ } ++ ++ if (++i == (HIFN_D_RES_RSIZE + 1)) ++ i = 0; ++ } ++ dma->resk = i; dma->resu = u; ++ ++ i = dma->srck; u = dma->srcu; ++ while (u != 0) { ++ if (i == HIFN_D_SRC_RSIZE) ++ i = 0; ++ HIFN_SRCR_SYNC(sc, i, ++ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); ++ if (dma->srcr[i].l & htole32(HIFN_D_VALID)) { ++ HIFN_SRCR_SYNC(sc, i, ++ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ++ break; ++ } ++ i++, u--; ++ } ++ dma->srck = i; dma->srcu = u; ++ ++ i = dma->cmdk; u = dma->cmdu; ++ while (u != 0) { ++ HIFN_CMDR_SYNC(sc, i, ++ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); ++ if (dma->cmdr[i].l & htole32(HIFN_D_VALID)) { ++ HIFN_CMDR_SYNC(sc, i, ++ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ++ break; ++ } ++ if (i != HIFN_D_CMD_RSIZE) { ++ u--; ++ HIFN_CMD_SYNC(sc, i, BUS_DMASYNC_POSTWRITE); ++ } ++ if (++i == (HIFN_D_CMD_RSIZE + 1)) ++ i = 0; ++ } ++ dma->cmdk = i; dma->cmdu = u; ++ ++ HIFN_UNLOCK(sc); ++ ++ if (sc->sc_needwakeup) { /* XXX check high watermark */ ++ int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); ++#ifdef HIFN_DEBUG ++ if (hifn_debug) ++ device_printf(sc->sc_dev, ++ "wakeup crypto (%x) u %d/%d/%d/%d\n", ++ sc->sc_needwakeup, ++ dma->cmdu, dma->srcu, dma->dstu, dma->resu); ++#endif ++ sc->sc_needwakeup &= ~wakeup; ++ crypto_unblock(sc->sc_cid, wakeup); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++/* ++ * Allocate a new 'session' and return an encoded session id. 'sidp' ++ * contains our registration id, and should contain an encoded session ++ * id on successful allocation. ++ */ ++static int ++hifn_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) ++{ ++ struct hifn_softc *sc = device_get_softc(dev); ++ struct cryptoini *c; ++ int mac = 0, cry = 0, sesn; ++ struct hifn_session *ses = NULL; ++ unsigned long l_flags; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ KASSERT(sc != NULL, ("hifn_newsession: null softc")); ++ if (sidp == NULL || cri == NULL || sc == NULL) { ++ DPRINTF("%s,%d: %s - EINVAL\n", __FILE__, __LINE__, __FUNCTION__); ++ return (EINVAL); ++ } ++ ++ HIFN_LOCK(sc); ++ if (sc->sc_sessions == NULL) { ++ ses = sc->sc_sessions = (struct hifn_session *)kmalloc(sizeof(*ses), ++ SLAB_ATOMIC); ++ if (ses == NULL) { ++ HIFN_UNLOCK(sc); ++ return (ENOMEM); ++ } ++ sesn = 0; ++ sc->sc_nsessions = 1; ++ } else { ++ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { ++ if (!sc->sc_sessions[sesn].hs_used) { ++ ses = &sc->sc_sessions[sesn]; ++ break; ++ } ++ } ++ ++ if (ses == NULL) { ++ sesn = sc->sc_nsessions; ++ ses = (struct hifn_session *)kmalloc((sesn + 1) * sizeof(*ses), ++ SLAB_ATOMIC); ++ if (ses == NULL) { ++ HIFN_UNLOCK(sc); ++ return (ENOMEM); ++ } ++ bcopy(sc->sc_sessions, ses, sesn * sizeof(*ses)); ++ bzero(sc->sc_sessions, sesn * sizeof(*ses)); ++ kfree(sc->sc_sessions); ++ sc->sc_sessions = ses; ++ ses = &sc->sc_sessions[sesn]; ++ sc->sc_nsessions++; ++ } ++ } ++ HIFN_UNLOCK(sc); ++ ++ bzero(ses, sizeof(*ses)); ++ ses->hs_used = 1; ++ ++ for (c = cri; c != NULL; c = c->cri_next) { ++ switch (c->cri_alg) { ++ case CRYPTO_MD5: ++ case CRYPTO_SHA1: ++ case CRYPTO_MD5_HMAC: ++ case CRYPTO_SHA1_HMAC: ++ if (mac) { ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ return (EINVAL); ++ } ++ mac = 1; ++ ses->hs_mlen = c->cri_mlen; ++ if (ses->hs_mlen == 0) { ++ switch (c->cri_alg) { ++ case CRYPTO_MD5: ++ case CRYPTO_MD5_HMAC: ++ ses->hs_mlen = 16; ++ break; ++ case CRYPTO_SHA1: ++ case CRYPTO_SHA1_HMAC: ++ ses->hs_mlen = 20; ++ break; ++ } ++ } ++ break; ++ case CRYPTO_DES_CBC: ++ case CRYPTO_3DES_CBC: ++ case CRYPTO_AES_CBC: ++ case CRYPTO_ARC4: ++ if (cry) { ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ return (EINVAL); ++ } ++ cry = 1; ++ break; ++ default: ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ return (EINVAL); ++ } ++ } ++ if (mac == 0 && cry == 0) { ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ return (EINVAL); ++ } ++ ++ *sidp = HIFN_SID(device_get_unit(sc->sc_dev), sesn); ++ ++ return (0); ++} ++ ++/* ++ * Deallocate a session. ++ * XXX this routine should run a zero'd mac/encrypt key into context ram. ++ * XXX to blow away any keys already stored there. ++ */ ++static int ++hifn_freesession(device_t dev, u_int64_t tid) ++{ ++ struct hifn_softc *sc = device_get_softc(dev); ++ int session, error; ++ u_int32_t sid = CRYPTO_SESID2LID(tid); ++ unsigned long l_flags; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ KASSERT(sc != NULL, ("hifn_freesession: null softc")); ++ if (sc == NULL) { ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ return (EINVAL); ++ } ++ ++ HIFN_LOCK(sc); ++ session = HIFN_SESSION(sid); ++ if (session < sc->sc_nsessions) { ++ bzero(&sc->sc_sessions[session], sizeof(struct hifn_session)); ++ error = 0; ++ } else { ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ error = EINVAL; ++ } ++ HIFN_UNLOCK(sc); ++ ++ return (error); ++} ++ ++static int ++hifn_process(device_t dev, struct cryptop *crp, int hint) ++{ ++ struct hifn_softc *sc = device_get_softc(dev); ++ struct hifn_command *cmd = NULL; ++ int session, err, ivlen; ++ struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ if (crp == NULL || crp->crp_callback == NULL) { ++ hifnstats.hst_invalid++; ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ return (EINVAL); ++ } ++ session = HIFN_SESSION(crp->crp_sid); ++ ++ if (sc == NULL || session >= sc->sc_nsessions) { ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ err = EINVAL; ++ goto errout; ++ } ++ ++ cmd = kmalloc(sizeof(struct hifn_command), SLAB_ATOMIC); ++ if (cmd == NULL) { ++ hifnstats.hst_nomem++; ++ err = ENOMEM; ++ goto errout; ++ } ++ memset(cmd, 0, sizeof(*cmd)); ++ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ cmd->src_skb = (struct sk_buff *)crp->crp_buf; ++ cmd->dst_skb = (struct sk_buff *)crp->crp_buf; ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ cmd->src_io = (struct uio *)crp->crp_buf; ++ cmd->dst_io = (struct uio *)crp->crp_buf; ++ } else { ++ cmd->src_buf = crp->crp_buf; ++ cmd->dst_buf = crp->crp_buf; ++ } ++ ++ crd1 = crp->crp_desc; ++ if (crd1 == NULL) { ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ err = EINVAL; ++ goto errout; ++ } ++ crd2 = crd1->crd_next; ++ ++ if (crd2 == NULL) { ++ if (crd1->crd_alg == CRYPTO_MD5_HMAC || ++ crd1->crd_alg == CRYPTO_SHA1_HMAC || ++ crd1->crd_alg == CRYPTO_SHA1 || ++ crd1->crd_alg == CRYPTO_MD5) { ++ maccrd = crd1; ++ enccrd = NULL; ++ } else if (crd1->crd_alg == CRYPTO_DES_CBC || ++ crd1->crd_alg == CRYPTO_3DES_CBC || ++ crd1->crd_alg == CRYPTO_AES_CBC || ++ crd1->crd_alg == CRYPTO_ARC4) { ++ if ((crd1->crd_flags & CRD_F_ENCRYPT) == 0) ++ cmd->base_masks |= HIFN_BASE_CMD_DECODE; ++ maccrd = NULL; ++ enccrd = crd1; ++ } else { ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ err = EINVAL; ++ goto errout; ++ } ++ } else { ++ if ((crd1->crd_alg == CRYPTO_MD5_HMAC || ++ crd1->crd_alg == CRYPTO_SHA1_HMAC || ++ crd1->crd_alg == CRYPTO_MD5 || ++ crd1->crd_alg == CRYPTO_SHA1) && ++ (crd2->crd_alg == CRYPTO_DES_CBC || ++ crd2->crd_alg == CRYPTO_3DES_CBC || ++ crd2->crd_alg == CRYPTO_AES_CBC || ++ crd2->crd_alg == CRYPTO_ARC4) && ++ ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { ++ cmd->base_masks = HIFN_BASE_CMD_DECODE; ++ maccrd = crd1; ++ enccrd = crd2; ++ } else if ((crd1->crd_alg == CRYPTO_DES_CBC || ++ crd1->crd_alg == CRYPTO_ARC4 || ++ crd1->crd_alg == CRYPTO_3DES_CBC || ++ crd1->crd_alg == CRYPTO_AES_CBC) && ++ (crd2->crd_alg == CRYPTO_MD5_HMAC || ++ crd2->crd_alg == CRYPTO_SHA1_HMAC || ++ crd2->crd_alg == CRYPTO_MD5 || ++ crd2->crd_alg == CRYPTO_SHA1) && ++ (crd1->crd_flags & CRD_F_ENCRYPT)) { ++ enccrd = crd1; ++ maccrd = crd2; ++ } else { ++ /* ++ * We cannot order the 7751 as requested ++ */ ++ DPRINTF("%s,%d: %s %d,%d,%d - EINVAL\n",__FILE__,__LINE__,__FUNCTION__, crd1->crd_alg, crd2->crd_alg, crd1->crd_flags & CRD_F_ENCRYPT); ++ err = EINVAL; ++ goto errout; ++ } ++ } ++ ++ if (enccrd) { ++ cmd->enccrd = enccrd; ++ cmd->base_masks |= HIFN_BASE_CMD_CRYPT; ++ switch (enccrd->crd_alg) { ++ case CRYPTO_ARC4: ++ cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_RC4; ++ break; ++ case CRYPTO_DES_CBC: ++ cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_DES | ++ HIFN_CRYPT_CMD_MODE_CBC | ++ HIFN_CRYPT_CMD_NEW_IV; ++ break; ++ case CRYPTO_3DES_CBC: ++ cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_3DES | ++ HIFN_CRYPT_CMD_MODE_CBC | ++ HIFN_CRYPT_CMD_NEW_IV; ++ break; ++ case CRYPTO_AES_CBC: ++ cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_AES | ++ HIFN_CRYPT_CMD_MODE_CBC | ++ HIFN_CRYPT_CMD_NEW_IV; ++ break; ++ default: ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ err = EINVAL; ++ goto errout; ++ } ++ if (enccrd->crd_alg != CRYPTO_ARC4) { ++ ivlen = ((enccrd->crd_alg == CRYPTO_AES_CBC) ? ++ HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH); ++ if (enccrd->crd_flags & CRD_F_ENCRYPT) { ++ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) ++ bcopy(enccrd->crd_iv, cmd->iv, ivlen); ++ else ++ read_random(cmd->iv, ivlen); ++ ++ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) ++ == 0) { ++ crypto_copyback(crp->crp_flags, ++ crp->crp_buf, enccrd->crd_inject, ++ ivlen, cmd->iv); ++ } ++ } else { ++ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) ++ bcopy(enccrd->crd_iv, cmd->iv, ivlen); ++ else { ++ crypto_copydata(crp->crp_flags, ++ crp->crp_buf, enccrd->crd_inject, ++ ivlen, cmd->iv); ++ } ++ } ++ } ++ ++ if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) ++ cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY; ++ cmd->ck = enccrd->crd_key; ++ cmd->cklen = enccrd->crd_klen >> 3; ++ cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY; ++ ++ /* ++ * Need to specify the size for the AES key in the masks. ++ */ ++ if ((cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) == ++ HIFN_CRYPT_CMD_ALG_AES) { ++ switch (cmd->cklen) { ++ case 16: ++ cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_128; ++ break; ++ case 24: ++ cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_192; ++ break; ++ case 32: ++ cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_256; ++ break; ++ default: ++ DPRINTF("%s,%d: %s - EINVAL\n",__FILE__,__LINE__,__FUNCTION__); ++ err = EINVAL; ++ goto errout; ++ } ++ } ++ } ++ ++ if (maccrd) { ++ cmd->maccrd = maccrd; ++ cmd->base_masks |= HIFN_BASE_CMD_MAC; ++ ++ switch (maccrd->crd_alg) { ++ case CRYPTO_MD5: ++ cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | ++ HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | ++ HIFN_MAC_CMD_POS_IPSEC; ++ break; ++ case CRYPTO_MD5_HMAC: ++ cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | ++ HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | ++ HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; ++ break; ++ case CRYPTO_SHA1: ++ cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | ++ HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | ++ HIFN_MAC_CMD_POS_IPSEC; ++ break; ++ case CRYPTO_SHA1_HMAC: ++ cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | ++ HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | ++ HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; ++ break; ++ } ++ ++ if (maccrd->crd_alg == CRYPTO_SHA1_HMAC || ++ maccrd->crd_alg == CRYPTO_MD5_HMAC) { ++ cmd->mac_masks |= HIFN_MAC_CMD_NEW_KEY; ++ bcopy(maccrd->crd_key, cmd->mac, maccrd->crd_klen >> 3); ++ bzero(cmd->mac + (maccrd->crd_klen >> 3), ++ HIFN_MAC_KEY_LENGTH - (maccrd->crd_klen >> 3)); ++ } ++ } ++ ++ cmd->crp = crp; ++ cmd->session_num = session; ++ cmd->softc = sc; ++ ++ err = hifn_crypto(sc, cmd, crp, hint); ++ if (!err) { ++ return 0; ++ } else if (err == ERESTART) { ++ /* ++ * There weren't enough resources to dispatch the request ++ * to the part. Notify the caller so they'll requeue this ++ * request and resubmit it again soon. ++ */ ++#ifdef HIFN_DEBUG ++ if (hifn_debug) ++ device_printf(sc->sc_dev, "requeue request\n"); ++#endif ++ kfree(cmd); ++ sc->sc_needwakeup |= CRYPTO_SYMQ; ++ return (err); ++ } ++ ++errout: ++ if (cmd != NULL) ++ kfree(cmd); ++ if (err == EINVAL) ++ hifnstats.hst_invalid++; ++ else ++ hifnstats.hst_nomem++; ++ crp->crp_etype = err; ++ crypto_done(crp); ++ return (err); ++} ++ ++static void ++hifn_abort(struct hifn_softc *sc) ++{ ++ struct hifn_dma *dma = sc->sc_dma; ++ struct hifn_command *cmd; ++ struct cryptop *crp; ++ int i, u; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ i = dma->resk; u = dma->resu; ++ while (u != 0) { ++ cmd = dma->hifn_commands[i]; ++ KASSERT(cmd != NULL, ("hifn_abort: null command slot %u", i)); ++ dma->hifn_commands[i] = NULL; ++ crp = cmd->crp; ++ ++ if ((dma->resr[i].l & htole32(HIFN_D_VALID)) == 0) { ++ /* Salvage what we can. */ ++ u_int8_t *macbuf; ++ ++ if (cmd->base_masks & HIFN_BASE_CMD_MAC) { ++ macbuf = dma->result_bufs[i]; ++ macbuf += 12; ++ } else ++ macbuf = NULL; ++ hifnstats.hst_opackets++; ++ hifn_callback(sc, cmd, macbuf); ++ } else { ++#if 0 ++ if (cmd->src_map == cmd->dst_map) { ++ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, ++ BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); ++ } else { ++ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, ++ BUS_DMASYNC_POSTWRITE); ++ bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, ++ BUS_DMASYNC_POSTREAD); ++ } ++#endif ++ ++ if (cmd->src_skb != cmd->dst_skb) { ++#ifdef NOTYET ++ m_freem(cmd->src_m); ++ crp->crp_buf = (caddr_t)cmd->dst_m; ++#else ++ device_printf(sc->sc_dev, ++ "%s,%d: CRYPTO_F_SKBUF src != dst not implemented\n", ++ __FILE__, __LINE__); ++#endif ++ } ++ ++ /* non-shared buffers cannot be restarted */ ++ if (cmd->src_map != cmd->dst_map) { ++ /* ++ * XXX should be EAGAIN, delayed until ++ * after the reset. ++ */ ++ crp->crp_etype = ENOMEM; ++ pci_unmap_buf(sc, &cmd->dst); ++ } else ++ crp->crp_etype = ENOMEM; ++ ++ pci_unmap_buf(sc, &cmd->src); ++ ++ kfree(cmd); ++ if (crp->crp_etype != EAGAIN) ++ crypto_done(crp); ++ } ++ ++ if (++i == HIFN_D_RES_RSIZE) ++ i = 0; ++ u--; ++ } ++ dma->resk = i; dma->resu = u; ++ ++ hifn_reset_board(sc, 1); ++ hifn_init_dma(sc); ++ hifn_init_pci_registers(sc); ++} ++ ++static void ++hifn_callback(struct hifn_softc *sc, struct hifn_command *cmd, u_int8_t *macbuf) ++{ ++ struct hifn_dma *dma = sc->sc_dma; ++ struct cryptop *crp = cmd->crp; ++ struct cryptodesc *crd; ++ int i, u; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++#if 0 ++ if (cmd->src_map == cmd->dst_map) { ++ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, ++ BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); ++ } else { ++ bus_dmamap_sync(sc->sc_dmat, cmd->src_map, ++ BUS_DMASYNC_POSTWRITE); ++ bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, ++ BUS_DMASYNC_POSTREAD); ++ } ++#endif ++ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ if (cmd->src_skb != cmd->dst_skb) { ++#ifdef NOTYET ++ crp->crp_buf = (caddr_t)cmd->dst_m; ++ totlen = cmd->src_mapsize; ++ for (m = cmd->dst_m; m != NULL; m = m->m_next) { ++ if (totlen < m->m_len) { ++ m->m_len = totlen; ++ totlen = 0; ++ } else ++ totlen -= m->m_len; ++ } ++ cmd->dst_m->m_pkthdr.len = cmd->src_m->m_pkthdr.len; ++ m_freem(cmd->src_m); ++#else ++ device_printf(sc->sc_dev, ++ "%s,%d: CRYPTO_F_SKBUF src != dst not implemented\n", ++ __FILE__, __LINE__); ++#endif ++ } ++ } ++ ++ if (cmd->sloplen != 0) { ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ cmd->src_mapsize - cmd->sloplen, cmd->sloplen, ++ (caddr_t)&dma->slop[cmd->slopidx]); ++ } ++ ++ i = dma->dstk; u = dma->dstu; ++ while (u != 0) { ++ if (i == HIFN_D_DST_RSIZE) ++ i = 0; ++#if 0 ++ bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, ++ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); ++#endif ++ if (dma->dstr[i].l & htole32(HIFN_D_VALID)) { ++#if 0 ++ bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, ++ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ++#endif ++ break; ++ } ++ i++, u--; ++ } ++ dma->dstk = i; dma->dstu = u; ++ ++ hifnstats.hst_obytes += cmd->dst_mapsize; ++ ++ if (macbuf != NULL) { ++ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { ++ int len; ++ ++ if (crd->crd_alg != CRYPTO_MD5 && ++ crd->crd_alg != CRYPTO_SHA1 && ++ crd->crd_alg != CRYPTO_MD5_HMAC && ++ crd->crd_alg != CRYPTO_SHA1_HMAC) { ++ continue; ++ } ++ len = cmd->softc->sc_sessions[cmd->session_num].hs_mlen; ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ crd->crd_inject, len, macbuf); ++ break; ++ } ++ } ++ ++ if (cmd->src_map != cmd->dst_map) ++ pci_unmap_buf(sc, &cmd->dst); ++ pci_unmap_buf(sc, &cmd->src); ++ kfree(cmd); ++ crypto_done(crp); ++} ++ ++/* ++ * 7811 PB3 rev/2 parts lock-up on burst writes to Group 0 ++ * and Group 1 registers; avoid conditions that could create ++ * burst writes by doing a read in between the writes. ++ * ++ * NB: The read we interpose is always to the same register; ++ * we do this because reading from an arbitrary (e.g. last) ++ * register may not always work. ++ */ ++static void ++hifn_write_reg_0(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) ++{ ++ if (sc->sc_flags & HIFN_IS_7811) { ++ if (sc->sc_bar0_lastreg == reg - 4) ++ readl(sc->sc_bar0 + HIFN_0_PUCNFG); ++ sc->sc_bar0_lastreg = reg; ++ } ++ writel(val, sc->sc_bar0 + reg); ++} ++ ++static void ++hifn_write_reg_1(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) ++{ ++ if (sc->sc_flags & HIFN_IS_7811) { ++ if (sc->sc_bar1_lastreg == reg - 4) ++ readl(sc->sc_bar1 + HIFN_1_REVID); ++ sc->sc_bar1_lastreg = reg; ++ } ++ writel(val, sc->sc_bar1 + reg); ++} ++ ++ ++static struct pci_device_id hifn_pci_tbl[] = { ++ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7951, ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, ++ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7955, ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, ++ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7956, ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, ++ { PCI_VENDOR_NETSEC, PCI_PRODUCT_NETSEC_7751, ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, ++ { PCI_VENDOR_INVERTEX, PCI_PRODUCT_INVERTEX_AEON, ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, ++ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7811, ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, ++ /* ++ * Other vendors share this PCI ID as well, such as ++ * http://www.powercrypt.com, and obviously they also ++ * use the same key. ++ */ ++ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7751, ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, ++ { 0, 0, 0, 0, 0, 0, } ++}; ++MODULE_DEVICE_TABLE(pci, hifn_pci_tbl); ++ ++static struct pci_driver hifn_driver = { ++ .name = "hifn", ++ .id_table = hifn_pci_tbl, ++ .probe = hifn_probe, ++ .remove = hifn_remove, ++ /* add PM stuff here one day */ ++}; ++ ++static int __init hifn_init (void) ++{ ++ struct hifn_softc *sc = NULL; ++ int rc; ++ ++ DPRINTF("%s(%p)\n", __FUNCTION__, hifn_init); ++ ++ rc = pci_register_driver(&hifn_driver); ++ pci_register_driver_compat(&hifn_driver, rc); ++ ++ return rc; ++} ++ ++static void __exit hifn_exit (void) ++{ ++ pci_unregister_driver(&hifn_driver); ++} ++ ++module_init(hifn_init); ++module_exit(hifn_exit); ++ ++MODULE_LICENSE("BSD"); ++MODULE_AUTHOR("David McCullough "); ++MODULE_DESCRIPTION("OCF driver for hifn PCI crypto devices"); +diff -Nur linux-3.1.4.orig/crypto/ocf/hifn/hifn7751reg.h linux-3.1.4/crypto/ocf/hifn/hifn7751reg.h +--- linux-3.1.4.orig/crypto/ocf/hifn/hifn7751reg.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/hifn/hifn7751reg.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,540 @@ ++/* $FreeBSD: src/sys/dev/hifn/hifn7751reg.h,v 1.7 2007/03/21 03:42:49 sam Exp $ */ ++/* $OpenBSD: hifn7751reg.h,v 1.35 2002/04/08 17:49:42 jason Exp $ */ ++ ++/*- ++ * Invertex AEON / Hifn 7751 driver ++ * Copyright (c) 1999 Invertex Inc. All rights reserved. ++ * Copyright (c) 1999 Theo de Raadt ++ * Copyright (c) 2000-2001 Network Security Technologies, Inc. ++ * http://www.netsec.net ++ * ++ * Please send any comments, feedback, bug-fixes, or feature requests to ++ * software@invertex.com. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored in part by the Defense Advanced Research Projects ++ * Agency (DARPA) and Air Force Research Laboratory, Air Force ++ * Materiel Command, USAF, under agreement number F30602-01-2-0537. ++ * ++ */ ++#ifndef __HIFN_H__ ++#define __HIFN_H__ ++ ++/* ++ * Some PCI configuration space offset defines. The names were made ++ * identical to the names used by the Linux kernel. ++ */ ++#define HIFN_BAR0 PCIR_BAR(0) /* PUC register map */ ++#define HIFN_BAR1 PCIR_BAR(1) /* DMA register map */ ++#define HIFN_TRDY_TIMEOUT 0x40 ++#define HIFN_RETRY_TIMEOUT 0x41 ++ ++/* ++ * PCI vendor and device identifiers ++ * (the names are preserved from their OpenBSD source). ++ */ ++#define PCI_VENDOR_HIFN 0x13a3 /* Hifn */ ++#define PCI_PRODUCT_HIFN_7751 0x0005 /* 7751 */ ++#define PCI_PRODUCT_HIFN_6500 0x0006 /* 6500 */ ++#define PCI_PRODUCT_HIFN_7811 0x0007 /* 7811 */ ++#define PCI_PRODUCT_HIFN_7855 0x001f /* 7855 */ ++#define PCI_PRODUCT_HIFN_7951 0x0012 /* 7951 */ ++#define PCI_PRODUCT_HIFN_7955 0x0020 /* 7954/7955 */ ++#define PCI_PRODUCT_HIFN_7956 0x001d /* 7956 */ ++ ++#define PCI_VENDOR_INVERTEX 0x14e1 /* Invertex */ ++#define PCI_PRODUCT_INVERTEX_AEON 0x0005 /* AEON */ ++ ++#define PCI_VENDOR_NETSEC 0x1660 /* NetSec */ ++#define PCI_PRODUCT_NETSEC_7751 0x7751 /* 7751 */ ++ ++/* ++ * The values below should multiple of 4 -- and be large enough to handle ++ * any command the driver implements. ++ * ++ * MAX_COMMAND = base command + mac command + encrypt command + ++ * mac-key + rc4-key ++ * MAX_RESULT = base result + mac result + mac + encrypt result ++ * ++ * ++ */ ++#define HIFN_MAX_COMMAND (8 + 8 + 8 + 64 + 260) ++#define HIFN_MAX_RESULT (8 + 4 + 20 + 4) ++ ++/* ++ * hifn_desc_t ++ * ++ * Holds an individual descriptor for any of the rings. ++ */ ++typedef struct hifn_desc { ++ volatile u_int32_t l; /* length and status bits */ ++ volatile u_int32_t p; ++} hifn_desc_t; ++ ++/* ++ * Masks for the "length" field of struct hifn_desc. ++ */ ++#define HIFN_D_LENGTH 0x0000ffff /* length bit mask */ ++#define HIFN_D_MASKDONEIRQ 0x02000000 /* mask the done interrupt */ ++#define HIFN_D_DESTOVER 0x04000000 /* destination overflow */ ++#define HIFN_D_OVER 0x08000000 /* overflow */ ++#define HIFN_D_LAST 0x20000000 /* last descriptor in chain */ ++#define HIFN_D_JUMP 0x40000000 /* jump descriptor */ ++#define HIFN_D_VALID 0x80000000 /* valid bit */ ++ ++ ++/* ++ * Processing Unit Registers (offset from BASEREG0) ++ */ ++#define HIFN_0_PUDATA 0x00 /* Processing Unit Data */ ++#define HIFN_0_PUCTRL 0x04 /* Processing Unit Control */ ++#define HIFN_0_PUISR 0x08 /* Processing Unit Interrupt Status */ ++#define HIFN_0_PUCNFG 0x0c /* Processing Unit Configuration */ ++#define HIFN_0_PUIER 0x10 /* Processing Unit Interrupt Enable */ ++#define HIFN_0_PUSTAT 0x14 /* Processing Unit Status/Chip ID */ ++#define HIFN_0_FIFOSTAT 0x18 /* FIFO Status */ ++#define HIFN_0_FIFOCNFG 0x1c /* FIFO Configuration */ ++#define HIFN_0_PUCTRL2 0x28 /* Processing Unit Control (2nd map) */ ++#define HIFN_0_MUTE1 0x80 ++#define HIFN_0_MUTE2 0x90 ++#define HIFN_0_SPACESIZE 0x100 /* Register space size */ ++ ++/* Processing Unit Control Register (HIFN_0_PUCTRL) */ ++#define HIFN_PUCTRL_CLRSRCFIFO 0x0010 /* clear source fifo */ ++#define HIFN_PUCTRL_STOP 0x0008 /* stop pu */ ++#define HIFN_PUCTRL_LOCKRAM 0x0004 /* lock ram */ ++#define HIFN_PUCTRL_DMAENA 0x0002 /* enable dma */ ++#define HIFN_PUCTRL_RESET 0x0001 /* Reset processing unit */ ++ ++/* Processing Unit Interrupt Status Register (HIFN_0_PUISR) */ ++#define HIFN_PUISR_CMDINVAL 0x8000 /* Invalid command interrupt */ ++#define HIFN_PUISR_DATAERR 0x4000 /* Data error interrupt */ ++#define HIFN_PUISR_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ ++#define HIFN_PUISR_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ ++#define HIFN_PUISR_DSTOVER 0x0200 /* Destination overrun interrupt */ ++#define HIFN_PUISR_SRCCMD 0x0080 /* Source command interrupt */ ++#define HIFN_PUISR_SRCCTX 0x0040 /* Source context interrupt */ ++#define HIFN_PUISR_SRCDATA 0x0020 /* Source data interrupt */ ++#define HIFN_PUISR_DSTDATA 0x0010 /* Destination data interrupt */ ++#define HIFN_PUISR_DSTRESULT 0x0004 /* Destination result interrupt */ ++ ++/* Processing Unit Configuration Register (HIFN_0_PUCNFG) */ ++#define HIFN_PUCNFG_DRAMMASK 0xe000 /* DRAM size mask */ ++#define HIFN_PUCNFG_DSZ_256K 0x0000 /* 256k dram */ ++#define HIFN_PUCNFG_DSZ_512K 0x2000 /* 512k dram */ ++#define HIFN_PUCNFG_DSZ_1M 0x4000 /* 1m dram */ ++#define HIFN_PUCNFG_DSZ_2M 0x6000 /* 2m dram */ ++#define HIFN_PUCNFG_DSZ_4M 0x8000 /* 4m dram */ ++#define HIFN_PUCNFG_DSZ_8M 0xa000 /* 8m dram */ ++#define HIFN_PUNCFG_DSZ_16M 0xc000 /* 16m dram */ ++#define HIFN_PUCNFG_DSZ_32M 0xe000 /* 32m dram */ ++#define HIFN_PUCNFG_DRAMREFRESH 0x1800 /* DRAM refresh rate mask */ ++#define HIFN_PUCNFG_DRFR_512 0x0000 /* 512 divisor of ECLK */ ++#define HIFN_PUCNFG_DRFR_256 0x0800 /* 256 divisor of ECLK */ ++#define HIFN_PUCNFG_DRFR_128 0x1000 /* 128 divisor of ECLK */ ++#define HIFN_PUCNFG_TCALLPHASES 0x0200 /* your guess is as good as mine... */ ++#define HIFN_PUCNFG_TCDRVTOTEM 0x0100 /* your guess is as good as mine... */ ++#define HIFN_PUCNFG_BIGENDIAN 0x0080 /* DMA big endian mode */ ++#define HIFN_PUCNFG_BUS32 0x0040 /* Bus width 32bits */ ++#define HIFN_PUCNFG_BUS16 0x0000 /* Bus width 16 bits */ ++#define HIFN_PUCNFG_CHIPID 0x0020 /* Allow chipid from PUSTAT */ ++#define HIFN_PUCNFG_DRAM 0x0010 /* Context RAM is DRAM */ ++#define HIFN_PUCNFG_SRAM 0x0000 /* Context RAM is SRAM */ ++#define HIFN_PUCNFG_COMPSING 0x0004 /* Enable single compression context */ ++#define HIFN_PUCNFG_ENCCNFG 0x0002 /* Encryption configuration */ ++ ++/* Processing Unit Interrupt Enable Register (HIFN_0_PUIER) */ ++#define HIFN_PUIER_CMDINVAL 0x8000 /* Invalid command interrupt */ ++#define HIFN_PUIER_DATAERR 0x4000 /* Data error interrupt */ ++#define HIFN_PUIER_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ ++#define HIFN_PUIER_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ ++#define HIFN_PUIER_DSTOVER 0x0200 /* Destination overrun interrupt */ ++#define HIFN_PUIER_SRCCMD 0x0080 /* Source command interrupt */ ++#define HIFN_PUIER_SRCCTX 0x0040 /* Source context interrupt */ ++#define HIFN_PUIER_SRCDATA 0x0020 /* Source data interrupt */ ++#define HIFN_PUIER_DSTDATA 0x0010 /* Destination data interrupt */ ++#define HIFN_PUIER_DSTRESULT 0x0004 /* Destination result interrupt */ ++ ++/* Processing Unit Status Register/Chip ID (HIFN_0_PUSTAT) */ ++#define HIFN_PUSTAT_CMDINVAL 0x8000 /* Invalid command interrupt */ ++#define HIFN_PUSTAT_DATAERR 0x4000 /* Data error interrupt */ ++#define HIFN_PUSTAT_SRCFIFO 0x2000 /* Source FIFO ready interrupt */ ++#define HIFN_PUSTAT_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */ ++#define HIFN_PUSTAT_DSTOVER 0x0200 /* Destination overrun interrupt */ ++#define HIFN_PUSTAT_SRCCMD 0x0080 /* Source command interrupt */ ++#define HIFN_PUSTAT_SRCCTX 0x0040 /* Source context interrupt */ ++#define HIFN_PUSTAT_SRCDATA 0x0020 /* Source data interrupt */ ++#define HIFN_PUSTAT_DSTDATA 0x0010 /* Destination data interrupt */ ++#define HIFN_PUSTAT_DSTRESULT 0x0004 /* Destination result interrupt */ ++#define HIFN_PUSTAT_CHIPREV 0x00ff /* Chip revision mask */ ++#define HIFN_PUSTAT_CHIPENA 0xff00 /* Chip enabled mask */ ++#define HIFN_PUSTAT_ENA_2 0x1100 /* Level 2 enabled */ ++#define HIFN_PUSTAT_ENA_1 0x1000 /* Level 1 enabled */ ++#define HIFN_PUSTAT_ENA_0 0x3000 /* Level 0 enabled */ ++#define HIFN_PUSTAT_REV_2 0x0020 /* 7751 PT6/2 */ ++#define HIFN_PUSTAT_REV_3 0x0030 /* 7751 PT6/3 */ ++ ++/* FIFO Status Register (HIFN_0_FIFOSTAT) */ ++#define HIFN_FIFOSTAT_SRC 0x7f00 /* Source FIFO available */ ++#define HIFN_FIFOSTAT_DST 0x007f /* Destination FIFO available */ ++ ++/* FIFO Configuration Register (HIFN_0_FIFOCNFG) */ ++#define HIFN_FIFOCNFG_THRESHOLD 0x0400 /* must be written as this value */ ++ ++/* ++ * DMA Interface Registers (offset from BASEREG1) ++ */ ++#define HIFN_1_DMA_CRAR 0x0c /* DMA Command Ring Address */ ++#define HIFN_1_DMA_SRAR 0x1c /* DMA Source Ring Address */ ++#define HIFN_1_DMA_RRAR 0x2c /* DMA Result Ring Address */ ++#define HIFN_1_DMA_DRAR 0x3c /* DMA Destination Ring Address */ ++#define HIFN_1_DMA_CSR 0x40 /* DMA Status and Control */ ++#define HIFN_1_DMA_IER 0x44 /* DMA Interrupt Enable */ ++#define HIFN_1_DMA_CNFG 0x48 /* DMA Configuration */ ++#define HIFN_1_PLL 0x4c /* 7955/7956: PLL config */ ++#define HIFN_1_7811_RNGENA 0x60 /* 7811: rng enable */ ++#define HIFN_1_7811_RNGCFG 0x64 /* 7811: rng config */ ++#define HIFN_1_7811_RNGDAT 0x68 /* 7811: rng data */ ++#define HIFN_1_7811_RNGSTS 0x6c /* 7811: rng status */ ++#define HIFN_1_DMA_CNFG2 0x6c /* 7955/7956: dma config #2 */ ++#define HIFN_1_7811_MIPSRST 0x94 /* 7811: MIPS reset */ ++#define HIFN_1_REVID 0x98 /* Revision ID */ ++ ++#define HIFN_1_PUB_RESET 0x204 /* Public/RNG Reset */ ++#define HIFN_1_PUB_BASE 0x300 /* Public Base Address */ ++#define HIFN_1_PUB_OPLEN 0x304 /* 7951-compat Public Operand Length */ ++#define HIFN_1_PUB_OP 0x308 /* 7951-compat Public Operand */ ++#define HIFN_1_PUB_STATUS 0x30c /* 7951-compat Public Status */ ++#define HIFN_1_PUB_IEN 0x310 /* Public Interrupt enable */ ++#define HIFN_1_RNG_CONFIG 0x314 /* RNG config */ ++#define HIFN_1_RNG_DATA 0x318 /* RNG data */ ++#define HIFN_1_PUB_MODE 0x320 /* PK mode */ ++#define HIFN_1_PUB_FIFO_OPLEN 0x380 /* first element of oplen fifo */ ++#define HIFN_1_PUB_FIFO_OP 0x384 /* first element of op fifo */ ++#define HIFN_1_PUB_MEM 0x400 /* start of Public key memory */ ++#define HIFN_1_PUB_MEMEND 0xbff /* end of Public key memory */ ++ ++/* DMA Status and Control Register (HIFN_1_DMA_CSR) */ ++#define HIFN_DMACSR_D_CTRLMASK 0xc0000000 /* Destinition Ring Control */ ++#define HIFN_DMACSR_D_CTRL_NOP 0x00000000 /* Dest. Control: no-op */ ++#define HIFN_DMACSR_D_CTRL_DIS 0x40000000 /* Dest. Control: disable */ ++#define HIFN_DMACSR_D_CTRL_ENA 0x80000000 /* Dest. Control: enable */ ++#define HIFN_DMACSR_D_ABORT 0x20000000 /* Destinition Ring PCIAbort */ ++#define HIFN_DMACSR_D_DONE 0x10000000 /* Destinition Ring Done */ ++#define HIFN_DMACSR_D_LAST 0x08000000 /* Destinition Ring Last */ ++#define HIFN_DMACSR_D_WAIT 0x04000000 /* Destinition Ring Waiting */ ++#define HIFN_DMACSR_D_OVER 0x02000000 /* Destinition Ring Overflow */ ++#define HIFN_DMACSR_R_CTRL 0x00c00000 /* Result Ring Control */ ++#define HIFN_DMACSR_R_CTRL_NOP 0x00000000 /* Result Control: no-op */ ++#define HIFN_DMACSR_R_CTRL_DIS 0x00400000 /* Result Control: disable */ ++#define HIFN_DMACSR_R_CTRL_ENA 0x00800000 /* Result Control: enable */ ++#define HIFN_DMACSR_R_ABORT 0x00200000 /* Result Ring PCI Abort */ ++#define HIFN_DMACSR_R_DONE 0x00100000 /* Result Ring Done */ ++#define HIFN_DMACSR_R_LAST 0x00080000 /* Result Ring Last */ ++#define HIFN_DMACSR_R_WAIT 0x00040000 /* Result Ring Waiting */ ++#define HIFN_DMACSR_R_OVER 0x00020000 /* Result Ring Overflow */ ++#define HIFN_DMACSR_S_CTRL 0x0000c000 /* Source Ring Control */ ++#define HIFN_DMACSR_S_CTRL_NOP 0x00000000 /* Source Control: no-op */ ++#define HIFN_DMACSR_S_CTRL_DIS 0x00004000 /* Source Control: disable */ ++#define HIFN_DMACSR_S_CTRL_ENA 0x00008000 /* Source Control: enable */ ++#define HIFN_DMACSR_S_ABORT 0x00002000 /* Source Ring PCI Abort */ ++#define HIFN_DMACSR_S_DONE 0x00001000 /* Source Ring Done */ ++#define HIFN_DMACSR_S_LAST 0x00000800 /* Source Ring Last */ ++#define HIFN_DMACSR_S_WAIT 0x00000400 /* Source Ring Waiting */ ++#define HIFN_DMACSR_ILLW 0x00000200 /* Illegal write (7811 only) */ ++#define HIFN_DMACSR_ILLR 0x00000100 /* Illegal read (7811 only) */ ++#define HIFN_DMACSR_C_CTRL 0x000000c0 /* Command Ring Control */ ++#define HIFN_DMACSR_C_CTRL_NOP 0x00000000 /* Command Control: no-op */ ++#define HIFN_DMACSR_C_CTRL_DIS 0x00000040 /* Command Control: disable */ ++#define HIFN_DMACSR_C_CTRL_ENA 0x00000080 /* Command Control: enable */ ++#define HIFN_DMACSR_C_ABORT 0x00000020 /* Command Ring PCI Abort */ ++#define HIFN_DMACSR_C_DONE 0x00000010 /* Command Ring Done */ ++#define HIFN_DMACSR_C_LAST 0x00000008 /* Command Ring Last */ ++#define HIFN_DMACSR_C_WAIT 0x00000004 /* Command Ring Waiting */ ++#define HIFN_DMACSR_PUBDONE 0x00000002 /* Public op done (7951 only) */ ++#define HIFN_DMACSR_ENGINE 0x00000001 /* Command Ring Engine IRQ */ ++ ++/* DMA Interrupt Enable Register (HIFN_1_DMA_IER) */ ++#define HIFN_DMAIER_D_ABORT 0x20000000 /* Destination Ring PCIAbort */ ++#define HIFN_DMAIER_D_DONE 0x10000000 /* Destination Ring Done */ ++#define HIFN_DMAIER_D_LAST 0x08000000 /* Destination Ring Last */ ++#define HIFN_DMAIER_D_WAIT 0x04000000 /* Destination Ring Waiting */ ++#define HIFN_DMAIER_D_OVER 0x02000000 /* Destination Ring Overflow */ ++#define HIFN_DMAIER_R_ABORT 0x00200000 /* Result Ring PCI Abort */ ++#define HIFN_DMAIER_R_DONE 0x00100000 /* Result Ring Done */ ++#define HIFN_DMAIER_R_LAST 0x00080000 /* Result Ring Last */ ++#define HIFN_DMAIER_R_WAIT 0x00040000 /* Result Ring Waiting */ ++#define HIFN_DMAIER_R_OVER 0x00020000 /* Result Ring Overflow */ ++#define HIFN_DMAIER_S_ABORT 0x00002000 /* Source Ring PCI Abort */ ++#define HIFN_DMAIER_S_DONE 0x00001000 /* Source Ring Done */ ++#define HIFN_DMAIER_S_LAST 0x00000800 /* Source Ring Last */ ++#define HIFN_DMAIER_S_WAIT 0x00000400 /* Source Ring Waiting */ ++#define HIFN_DMAIER_ILLW 0x00000200 /* Illegal write (7811 only) */ ++#define HIFN_DMAIER_ILLR 0x00000100 /* Illegal read (7811 only) */ ++#define HIFN_DMAIER_C_ABORT 0x00000020 /* Command Ring PCI Abort */ ++#define HIFN_DMAIER_C_DONE 0x00000010 /* Command Ring Done */ ++#define HIFN_DMAIER_C_LAST 0x00000008 /* Command Ring Last */ ++#define HIFN_DMAIER_C_WAIT 0x00000004 /* Command Ring Waiting */ ++#define HIFN_DMAIER_PUBDONE 0x00000002 /* public op done (7951 only) */ ++#define HIFN_DMAIER_ENGINE 0x00000001 /* Engine IRQ */ ++ ++/* DMA Configuration Register (HIFN_1_DMA_CNFG) */ ++#define HIFN_DMACNFG_BIGENDIAN 0x10000000 /* big endian mode */ ++#define HIFN_DMACNFG_POLLFREQ 0x00ff0000 /* Poll frequency mask */ ++#define HIFN_DMACNFG_UNLOCK 0x00000800 ++#define HIFN_DMACNFG_POLLINVAL 0x00000700 /* Invalid Poll Scalar */ ++#define HIFN_DMACNFG_LAST 0x00000010 /* Host control LAST bit */ ++#define HIFN_DMACNFG_MODE 0x00000004 /* DMA mode */ ++#define HIFN_DMACNFG_DMARESET 0x00000002 /* DMA Reset # */ ++#define HIFN_DMACNFG_MSTRESET 0x00000001 /* Master Reset # */ ++ ++/* DMA Configuration Register (HIFN_1_DMA_CNFG2) */ ++#define HIFN_DMACNFG2_PKSWAP32 (1 << 19) /* swap the OPLEN/OP reg */ ++#define HIFN_DMACNFG2_PKSWAP8 (1 << 18) /* swap the bits of OPLEN/OP */ ++#define HIFN_DMACNFG2_BAR0_SWAP32 (1<<17) /* swap the bytes of BAR0 */ ++#define HIFN_DMACNFG2_BAR1_SWAP8 (1<<16) /* swap the bits of BAR0 */ ++#define HIFN_DMACNFG2_INIT_WRITE_BURST_SHIFT 12 ++#define HIFN_DMACNFG2_INIT_READ_BURST_SHIFT 8 ++#define HIFN_DMACNFG2_TGT_WRITE_BURST_SHIFT 4 ++#define HIFN_DMACNFG2_TGT_READ_BURST_SHIFT 0 ++ ++/* 7811 RNG Enable Register (HIFN_1_7811_RNGENA) */ ++#define HIFN_7811_RNGENA_ENA 0x00000001 /* enable RNG */ ++ ++/* 7811 RNG Config Register (HIFN_1_7811_RNGCFG) */ ++#define HIFN_7811_RNGCFG_PRE1 0x00000f00 /* first prescalar */ ++#define HIFN_7811_RNGCFG_OPRE 0x00000080 /* output prescalar */ ++#define HIFN_7811_RNGCFG_DEFL 0x00000f80 /* 2 words/ 1/100 sec */ ++ ++/* 7811 RNG Status Register (HIFN_1_7811_RNGSTS) */ ++#define HIFN_7811_RNGSTS_RDY 0x00004000 /* two numbers in FIFO */ ++#define HIFN_7811_RNGSTS_UFL 0x00001000 /* rng underflow */ ++ ++/* 7811 MIPS Reset Register (HIFN_1_7811_MIPSRST) */ ++#define HIFN_MIPSRST_BAR2SIZE 0xffff0000 /* sdram size */ ++#define HIFN_MIPSRST_GPRAMINIT 0x00008000 /* gpram can be accessed */ ++#define HIFN_MIPSRST_CRAMINIT 0x00004000 /* ctxram can be accessed */ ++#define HIFN_MIPSRST_LED2 0x00000400 /* external LED2 */ ++#define HIFN_MIPSRST_LED1 0x00000200 /* external LED1 */ ++#define HIFN_MIPSRST_LED0 0x00000100 /* external LED0 */ ++#define HIFN_MIPSRST_MIPSDIS 0x00000004 /* disable MIPS */ ++#define HIFN_MIPSRST_MIPSRST 0x00000002 /* warm reset MIPS */ ++#define HIFN_MIPSRST_MIPSCOLD 0x00000001 /* cold reset MIPS */ ++ ++/* Public key reset register (HIFN_1_PUB_RESET) */ ++#define HIFN_PUBRST_RESET 0x00000001 /* reset public/rng unit */ ++ ++/* Public operation register (HIFN_1_PUB_OP) */ ++#define HIFN_PUBOP_AOFFSET 0x0000003e /* A offset */ ++#define HIFN_PUBOP_BOFFSET 0x00000fc0 /* B offset */ ++#define HIFN_PUBOP_MOFFSET 0x0003f000 /* M offset */ ++#define HIFN_PUBOP_OP_MASK 0x003c0000 /* Opcode: */ ++#define HIFN_PUBOP_OP_NOP 0x00000000 /* NOP */ ++#define HIFN_PUBOP_OP_ADD 0x00040000 /* ADD */ ++#define HIFN_PUBOP_OP_ADDC 0x00080000 /* ADD w/carry */ ++#define HIFN_PUBOP_OP_SUB 0x000c0000 /* SUB */ ++#define HIFN_PUBOP_OP_SUBC 0x00100000 /* SUB w/carry */ ++#define HIFN_PUBOP_OP_MODADD 0x00140000 /* Modular ADD */ ++#define HIFN_PUBOP_OP_MODSUB 0x00180000 /* Modular SUB */ ++#define HIFN_PUBOP_OP_INCA 0x001c0000 /* INC A */ ++#define HIFN_PUBOP_OP_DECA 0x00200000 /* DEC A */ ++#define HIFN_PUBOP_OP_MULT 0x00240000 /* MULT */ ++#define HIFN_PUBOP_OP_MODMULT 0x00280000 /* Modular MULT */ ++#define HIFN_PUBOP_OP_MODRED 0x002c0000 /* Modular Red */ ++#define HIFN_PUBOP_OP_MODEXP 0x00300000 /* Modular Exp */ ++ ++/* Public operand length register (HIFN_1_PUB_OPLEN) */ ++#define HIFN_PUBOPLEN_MODLEN 0x0000007f ++#define HIFN_PUBOPLEN_EXPLEN 0x0003ff80 ++#define HIFN_PUBOPLEN_REDLEN 0x003c0000 ++ ++/* Public status register (HIFN_1_PUB_STATUS) */ ++#define HIFN_PUBSTS_DONE 0x00000001 /* operation done */ ++#define HIFN_PUBSTS_CARRY 0x00000002 /* carry */ ++#define HIFN_PUBSTS_FIFO_EMPTY 0x00000100 /* fifo empty */ ++#define HIFN_PUBSTS_FIFO_FULL 0x00000200 /* fifo full */ ++#define HIFN_PUBSTS_FIFO_OVFL 0x00000400 /* fifo overflow */ ++#define HIFN_PUBSTS_FIFO_WRITE 0x000f0000 /* fifo write */ ++#define HIFN_PUBSTS_FIFO_READ 0x0f000000 /* fifo read */ ++ ++/* Public interrupt enable register (HIFN_1_PUB_IEN) */ ++#define HIFN_PUBIEN_DONE 0x00000001 /* operation done interrupt */ ++ ++/* Random number generator config register (HIFN_1_RNG_CONFIG) */ ++#define HIFN_RNGCFG_ENA 0x00000001 /* enable rng */ ++ ++/* ++ * Register offsets in register set 1 ++ */ ++ ++#define HIFN_UNLOCK_SECRET1 0xf4 ++#define HIFN_UNLOCK_SECRET2 0xfc ++ ++/* ++ * PLL config register ++ * ++ * This register is present only on 7954/7955/7956 parts. It must be ++ * programmed according to the bus interface method used by the h/w. ++ * Note that the parts require a stable clock. Since the PCI clock ++ * may vary the reference clock must usually be used. To avoid ++ * overclocking the core logic, setup must be done carefully, refer ++ * to the driver for details. The exact multiplier required varies ++ * by part and system configuration; refer to the Hifn documentation. ++ */ ++#define HIFN_PLL_REF_SEL 0x00000001 /* REF/HBI clk selection */ ++#define HIFN_PLL_BP 0x00000002 /* bypass (used during setup) */ ++/* bit 2 reserved */ ++#define HIFN_PLL_PK_CLK_SEL 0x00000008 /* public key clk select */ ++#define HIFN_PLL_PE_CLK_SEL 0x00000010 /* packet engine clk select */ ++/* bits 5-9 reserved */ ++#define HIFN_PLL_MBSET 0x00000400 /* must be set to 1 */ ++#define HIFN_PLL_ND 0x00003800 /* Fpll_ref multiplier select */ ++#define HIFN_PLL_ND_SHIFT 11 ++#define HIFN_PLL_ND_2 0x00000000 /* 2x */ ++#define HIFN_PLL_ND_4 0x00000800 /* 4x */ ++#define HIFN_PLL_ND_6 0x00001000 /* 6x */ ++#define HIFN_PLL_ND_8 0x00001800 /* 8x */ ++#define HIFN_PLL_ND_10 0x00002000 /* 10x */ ++#define HIFN_PLL_ND_12 0x00002800 /* 12x */ ++/* bits 14-15 reserved */ ++#define HIFN_PLL_IS 0x00010000 /* charge pump current select */ ++/* bits 17-31 reserved */ ++ ++/* ++ * Board configuration specifies only these bits. ++ */ ++#define HIFN_PLL_CONFIG (HIFN_PLL_IS|HIFN_PLL_ND|HIFN_PLL_REF_SEL) ++ ++/* ++ * Public Key Engine Mode Register ++ */ ++#define HIFN_PKMODE_HOSTINVERT (1 << 0) /* HOST INVERT */ ++#define HIFN_PKMODE_ENHANCED (1 << 1) /* Enable enhanced mode */ ++ ++ ++/********************************************************************* ++ * Structs for board commands ++ * ++ *********************************************************************/ ++ ++/* ++ * Structure to help build up the command data structure. ++ */ ++typedef struct hifn_base_command { ++ volatile u_int16_t masks; ++ volatile u_int16_t session_num; ++ volatile u_int16_t total_source_count; ++ volatile u_int16_t total_dest_count; ++} hifn_base_command_t; ++ ++#define HIFN_BASE_CMD_MAC 0x0400 ++#define HIFN_BASE_CMD_CRYPT 0x0800 ++#define HIFN_BASE_CMD_DECODE 0x2000 ++#define HIFN_BASE_CMD_SRCLEN_M 0xc000 ++#define HIFN_BASE_CMD_SRCLEN_S 14 ++#define HIFN_BASE_CMD_DSTLEN_M 0x3000 ++#define HIFN_BASE_CMD_DSTLEN_S 12 ++#define HIFN_BASE_CMD_LENMASK_HI 0x30000 ++#define HIFN_BASE_CMD_LENMASK_LO 0x0ffff ++ ++/* ++ * Structure to help build up the command data structure. ++ */ ++typedef struct hifn_crypt_command { ++ volatile u_int16_t masks; ++ volatile u_int16_t header_skip; ++ volatile u_int16_t source_count; ++ volatile u_int16_t reserved; ++} hifn_crypt_command_t; ++ ++#define HIFN_CRYPT_CMD_ALG_MASK 0x0003 /* algorithm: */ ++#define HIFN_CRYPT_CMD_ALG_DES 0x0000 /* DES */ ++#define HIFN_CRYPT_CMD_ALG_3DES 0x0001 /* 3DES */ ++#define HIFN_CRYPT_CMD_ALG_RC4 0x0002 /* RC4 */ ++#define HIFN_CRYPT_CMD_ALG_AES 0x0003 /* AES */ ++#define HIFN_CRYPT_CMD_MODE_MASK 0x0018 /* Encrypt mode: */ ++#define HIFN_CRYPT_CMD_MODE_ECB 0x0000 /* ECB */ ++#define HIFN_CRYPT_CMD_MODE_CBC 0x0008 /* CBC */ ++#define HIFN_CRYPT_CMD_MODE_CFB 0x0010 /* CFB */ ++#define HIFN_CRYPT_CMD_MODE_OFB 0x0018 /* OFB */ ++#define HIFN_CRYPT_CMD_CLR_CTX 0x0040 /* clear context */ ++#define HIFN_CRYPT_CMD_NEW_KEY 0x0800 /* expect new key */ ++#define HIFN_CRYPT_CMD_NEW_IV 0x1000 /* expect new iv */ ++ ++#define HIFN_CRYPT_CMD_SRCLEN_M 0xc000 ++#define HIFN_CRYPT_CMD_SRCLEN_S 14 ++ ++#define HIFN_CRYPT_CMD_KSZ_MASK 0x0600 /* AES key size: */ ++#define HIFN_CRYPT_CMD_KSZ_128 0x0000 /* 128 bit */ ++#define HIFN_CRYPT_CMD_KSZ_192 0x0200 /* 192 bit */ ++#define HIFN_CRYPT_CMD_KSZ_256 0x0400 /* 256 bit */ ++ ++/* ++ * Structure to help build up the command data structure. ++ */ ++typedef struct hifn_mac_command { ++ volatile u_int16_t masks; ++ volatile u_int16_t header_skip; ++ volatile u_int16_t source_count; ++ volatile u_int16_t reserved; ++} hifn_mac_command_t; ++ ++#define HIFN_MAC_CMD_ALG_MASK 0x0001 ++#define HIFN_MAC_CMD_ALG_SHA1 0x0000 ++#define HIFN_MAC_CMD_ALG_MD5 0x0001 ++#define HIFN_MAC_CMD_MODE_MASK 0x000c ++#define HIFN_MAC_CMD_MODE_HMAC 0x0000 ++#define HIFN_MAC_CMD_MODE_SSL_MAC 0x0004 ++#define HIFN_MAC_CMD_MODE_HASH 0x0008 ++#define HIFN_MAC_CMD_MODE_FULL 0x0004 ++#define HIFN_MAC_CMD_TRUNC 0x0010 ++#define HIFN_MAC_CMD_RESULT 0x0020 ++#define HIFN_MAC_CMD_APPEND 0x0040 ++#define HIFN_MAC_CMD_SRCLEN_M 0xc000 ++#define HIFN_MAC_CMD_SRCLEN_S 14 ++ ++/* ++ * MAC POS IPsec initiates authentication after encryption on encodes ++ * and before decryption on decodes. ++ */ ++#define HIFN_MAC_CMD_POS_IPSEC 0x0200 ++#define HIFN_MAC_CMD_NEW_KEY 0x0800 ++ ++/* ++ * The poll frequency and poll scalar defines are unshifted values used ++ * to set fields in the DMA Configuration Register. ++ */ ++#ifndef HIFN_POLL_FREQUENCY ++#define HIFN_POLL_FREQUENCY 0x1 ++#endif ++ ++#ifndef HIFN_POLL_SCALAR ++#define HIFN_POLL_SCALAR 0x0 ++#endif ++ ++#define HIFN_MAX_SEGLEN 0xffff /* maximum dma segment len */ ++#define HIFN_MAX_DMALEN 0x3ffff /* maximum dma length */ ++#endif /* __HIFN_H__ */ +diff -Nur linux-3.1.4.orig/crypto/ocf/hifn/hifn7751var.h linux-3.1.4/crypto/ocf/hifn/hifn7751var.h +--- linux-3.1.4.orig/crypto/ocf/hifn/hifn7751var.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/hifn/hifn7751var.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,368 @@ ++/* $FreeBSD: src/sys/dev/hifn/hifn7751var.h,v 1.9 2007/03/21 03:42:49 sam Exp $ */ ++/* $OpenBSD: hifn7751var.h,v 1.42 2002/04/08 17:49:42 jason Exp $ */ ++ ++/*- ++ * Invertex AEON / Hifn 7751 driver ++ * Copyright (c) 1999 Invertex Inc. All rights reserved. ++ * Copyright (c) 1999 Theo de Raadt ++ * Copyright (c) 2000-2001 Network Security Technologies, Inc. ++ * http://www.netsec.net ++ * ++ * Please send any comments, feedback, bug-fixes, or feature requests to ++ * software@invertex.com. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored in part by the Defense Advanced Research Projects ++ * Agency (DARPA) and Air Force Research Laboratory, Air Force ++ * Materiel Command, USAF, under agreement number F30602-01-2-0537. ++ * ++ */ ++ ++#ifndef __HIFN7751VAR_H__ ++#define __HIFN7751VAR_H__ ++ ++#ifdef __KERNEL__ ++ ++/* ++ * Some configurable values for the driver. By default command+result ++ * descriptor rings are the same size. The src+dst descriptor rings ++ * are sized at 3.5x the number of potential commands. Slower parts ++ * (e.g. 7951) tend to run out of src descriptors; faster parts (7811) ++ * src+cmd/result descriptors. It's not clear that increasing the size ++ * of the descriptor rings helps performance significantly as other ++ * factors tend to come into play (e.g. copying misaligned packets). ++ */ ++#define HIFN_D_CMD_RSIZE 24 /* command descriptors */ ++#define HIFN_D_SRC_RSIZE ((HIFN_D_CMD_RSIZE * 7) / 2) /* source descriptors */ ++#define HIFN_D_RES_RSIZE HIFN_D_CMD_RSIZE /* result descriptors */ ++#define HIFN_D_DST_RSIZE HIFN_D_SRC_RSIZE /* destination descriptors */ ++ ++/* ++ * Length values for cryptography ++ */ ++#define HIFN_DES_KEY_LENGTH 8 ++#define HIFN_3DES_KEY_LENGTH 24 ++#define HIFN_MAX_CRYPT_KEY_LENGTH HIFN_3DES_KEY_LENGTH ++#define HIFN_IV_LENGTH 8 ++#define HIFN_AES_IV_LENGTH 16 ++#define HIFN_MAX_IV_LENGTH HIFN_AES_IV_LENGTH ++ ++/* ++ * Length values for authentication ++ */ ++#define HIFN_MAC_KEY_LENGTH 64 ++#define HIFN_MD5_LENGTH 16 ++#define HIFN_SHA1_LENGTH 20 ++#define HIFN_MAC_TRUNC_LENGTH 12 ++ ++#define MAX_SCATTER 64 ++ ++/* ++ * Data structure to hold all 4 rings and any other ring related data. ++ */ ++struct hifn_dma { ++ /* ++ * Descriptor rings. We add +1 to the size to accomidate the ++ * jump descriptor. ++ */ ++ struct hifn_desc cmdr[HIFN_D_CMD_RSIZE+1]; ++ struct hifn_desc srcr[HIFN_D_SRC_RSIZE+1]; ++ struct hifn_desc dstr[HIFN_D_DST_RSIZE+1]; ++ struct hifn_desc resr[HIFN_D_RES_RSIZE+1]; ++ ++ struct hifn_command *hifn_commands[HIFN_D_RES_RSIZE]; ++ ++ u_char command_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_COMMAND]; ++ u_char result_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_RESULT]; ++ u_int32_t slop[HIFN_D_CMD_RSIZE]; ++ ++ u_int64_t test_src, test_dst; ++ ++ /* ++ * Our current positions for insertion and removal from the desriptor ++ * rings. ++ */ ++ int cmdi, srci, dsti, resi; ++ volatile int cmdu, srcu, dstu, resu; ++ int cmdk, srck, dstk, resk; ++}; ++ ++struct hifn_session { ++ int hs_used; ++ int hs_mlen; ++}; ++ ++#define HIFN_RING_SYNC(sc, r, i, f) \ ++ /* DAVIDM bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, (f)) */ ++ ++#define HIFN_CMDR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), cmdr, (i), (f)) ++#define HIFN_RESR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), resr, (i), (f)) ++#define HIFN_SRCR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), srcr, (i), (f)) ++#define HIFN_DSTR_SYNC(sc, i, f) HIFN_RING_SYNC((sc), dstr, (i), (f)) ++ ++#define HIFN_CMD_SYNC(sc, i, f) \ ++ /* DAVIDM bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, (f)) */ ++ ++#define HIFN_RES_SYNC(sc, i, f) \ ++ /* DAVIDM bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, (f)) */ ++ ++typedef int bus_size_t; ++ ++/* ++ * Holds data specific to a single HIFN board. ++ */ ++struct hifn_softc { ++ softc_device_decl sc_dev; ++ ++ struct pci_dev *sc_pcidev; /* PCI device pointer */ ++ spinlock_t sc_mtx; /* per-instance lock */ ++ ++ int sc_num; /* for multiple devs */ ++ ++ ocf_iomem_t sc_bar0; ++ bus_size_t sc_bar0_lastreg;/* bar0 last reg written */ ++ ocf_iomem_t sc_bar1; ++ bus_size_t sc_bar1_lastreg;/* bar1 last reg written */ ++ ++ int sc_irq; ++ ++ u_int32_t sc_dmaier; ++ u_int32_t sc_drammodel; /* 1=dram, 0=sram */ ++ u_int32_t sc_pllconfig; /* 7954/7955/7956 PLL config */ ++ ++ struct hifn_dma *sc_dma; ++ dma_addr_t sc_dma_physaddr;/* physical address of sc_dma */ ++ ++ int sc_dmansegs; ++ int32_t sc_cid; ++ int sc_maxses; ++ int sc_nsessions; ++ struct hifn_session *sc_sessions; ++ int sc_ramsize; ++ int sc_flags; ++#define HIFN_HAS_RNG 0x1 /* includes random number generator */ ++#define HIFN_HAS_PUBLIC 0x2 /* includes public key support */ ++#define HIFN_HAS_AES 0x4 /* includes AES support */ ++#define HIFN_IS_7811 0x8 /* Hifn 7811 part */ ++#define HIFN_IS_7956 0x10 /* Hifn 7956/7955 don't have SDRAM */ ++ ++ struct timer_list sc_tickto; /* for managing DMA */ ++ ++ int sc_rngfirst; ++ int sc_rnghz; /* RNG polling frequency */ ++ ++ int sc_c_busy; /* command ring busy */ ++ int sc_s_busy; /* source data ring busy */ ++ int sc_d_busy; /* destination data ring busy */ ++ int sc_r_busy; /* result ring busy */ ++ int sc_active; /* for initial countdown */ ++ int sc_needwakeup; /* ops q'd wating on resources */ ++ int sc_curbatch; /* # ops submitted w/o int */ ++ int sc_suspended; ++#ifdef HIFN_VULCANDEV ++ struct cdev *sc_pkdev; ++#endif ++}; ++ ++#define HIFN_LOCK(_sc) spin_lock_irqsave(&(_sc)->sc_mtx, l_flags) ++#define HIFN_UNLOCK(_sc) spin_unlock_irqrestore(&(_sc)->sc_mtx, l_flags) ++ ++/* ++ * hifn_command_t ++ * ++ * This is the control structure used to pass commands to hifn_encrypt(). ++ * ++ * flags ++ * ----- ++ * Flags is the bitwise "or" values for command configuration. A single ++ * encrypt direction needs to be set: ++ * ++ * HIFN_ENCODE or HIFN_DECODE ++ * ++ * To use cryptography, a single crypto algorithm must be included: ++ * ++ * HIFN_CRYPT_3DES or HIFN_CRYPT_DES ++ * ++ * To use authentication is used, a single MAC algorithm must be included: ++ * ++ * HIFN_MAC_MD5 or HIFN_MAC_SHA1 ++ * ++ * By default MD5 uses a 16 byte hash and SHA-1 uses a 20 byte hash. ++ * If the value below is set, hash values are truncated or assumed ++ * truncated to 12 bytes: ++ * ++ * HIFN_MAC_TRUNC ++ * ++ * Keys for encryption and authentication can be sent as part of a command, ++ * or the last key value used with a particular session can be retrieved ++ * and used again if either of these flags are not specified. ++ * ++ * HIFN_CRYPT_NEW_KEY, HIFN_MAC_NEW_KEY ++ * ++ * session_num ++ * ----------- ++ * A number between 0 and 2048 (for DRAM models) or a number between ++ * 0 and 768 (for SRAM models). Those who don't want to use session ++ * numbers should leave value at zero and send a new crypt key and/or ++ * new MAC key on every command. If you use session numbers and ++ * don't send a key with a command, the last key sent for that same ++ * session number will be used. ++ * ++ * Warning: Using session numbers and multiboard at the same time ++ * is currently broken. ++ * ++ * mbuf ++ * ---- ++ * Either fill in the mbuf pointer and npa=0 or ++ * fill packp[] and packl[] and set npa to > 0 ++ * ++ * mac_header_skip ++ * --------------- ++ * The number of bytes of the source_buf that are skipped over before ++ * authentication begins. This must be a number between 0 and 2^16-1 ++ * and can be used by IPsec implementers to skip over IP headers. ++ * *** Value ignored if authentication not used *** ++ * ++ * crypt_header_skip ++ * ----------------- ++ * The number of bytes of the source_buf that are skipped over before ++ * the cryptographic operation begins. This must be a number between 0 ++ * and 2^16-1. For IPsec, this number will always be 8 bytes larger ++ * than the auth_header_skip (to skip over the ESP header). ++ * *** Value ignored if cryptography not used *** ++ * ++ */ ++struct hifn_operand { ++ union { ++ struct sk_buff *skb; ++ struct uio *io; ++ unsigned char *buf; ++ } u; ++ void *map; ++ bus_size_t mapsize; ++ int nsegs; ++ struct { ++ dma_addr_t ds_addr; ++ int ds_len; ++ } segs[MAX_SCATTER]; ++}; ++ ++struct hifn_command { ++ u_int16_t session_num; ++ u_int16_t base_masks, cry_masks, mac_masks; ++ u_int8_t iv[HIFN_MAX_IV_LENGTH], *ck, mac[HIFN_MAC_KEY_LENGTH]; ++ int cklen; ++ int sloplen, slopidx; ++ ++ struct hifn_operand src; ++ struct hifn_operand dst; ++ ++ struct hifn_softc *softc; ++ struct cryptop *crp; ++ struct cryptodesc *enccrd, *maccrd; ++}; ++ ++#define src_skb src.u.skb ++#define src_io src.u.io ++#define src_map src.map ++#define src_mapsize src.mapsize ++#define src_segs src.segs ++#define src_nsegs src.nsegs ++#define src_buf src.u.buf ++ ++#define dst_skb dst.u.skb ++#define dst_io dst.u.io ++#define dst_map dst.map ++#define dst_mapsize dst.mapsize ++#define dst_segs dst.segs ++#define dst_nsegs dst.nsegs ++#define dst_buf dst.u.buf ++ ++/* ++ * Return values for hifn_crypto() ++ */ ++#define HIFN_CRYPTO_SUCCESS 0 ++#define HIFN_CRYPTO_BAD_INPUT (-1) ++#define HIFN_CRYPTO_RINGS_FULL (-2) ++ ++/************************************************************************** ++ * ++ * Function: hifn_crypto ++ * ++ * Purpose: Called by external drivers to begin an encryption on the ++ * HIFN board. ++ * ++ * Blocking/Non-blocking Issues ++ * ============================ ++ * The driver cannot block in hifn_crypto (no calls to tsleep) currently. ++ * hifn_crypto() returns HIFN_CRYPTO_RINGS_FULL if there is not enough ++ * room in any of the rings for the request to proceed. ++ * ++ * Return Values ++ * ============= ++ * 0 for success, negative values on error ++ * ++ * Defines for negative error codes are: ++ * ++ * HIFN_CRYPTO_BAD_INPUT : The passed in command had invalid settings. ++ * HIFN_CRYPTO_RINGS_FULL : All DMA rings were full and non-blocking ++ * behaviour was requested. ++ * ++ *************************************************************************/ ++ ++/* ++ * Convert back and forth from 'sid' to 'card' and 'session' ++ */ ++#define HIFN_CARD(sid) (((sid) & 0xf0000000) >> 28) ++#define HIFN_SESSION(sid) ((sid) & 0x000007ff) ++#define HIFN_SID(crd,ses) (((crd) << 28) | ((ses) & 0x7ff)) ++ ++#endif /* _KERNEL */ ++ ++struct hifn_stats { ++ u_int64_t hst_ibytes; ++ u_int64_t hst_obytes; ++ u_int32_t hst_ipackets; ++ u_int32_t hst_opackets; ++ u_int32_t hst_invalid; ++ u_int32_t hst_nomem; /* malloc or one of hst_nomem_* */ ++ u_int32_t hst_abort; ++ u_int32_t hst_noirq; /* IRQ for no reason */ ++ u_int32_t hst_totbatch; /* ops submitted w/o interrupt */ ++ u_int32_t hst_maxbatch; /* max ops submitted together */ ++ u_int32_t hst_unaligned; /* unaligned src caused copy */ ++ /* ++ * The following divides hst_nomem into more specific buckets. ++ */ ++ u_int32_t hst_nomem_map; /* bus_dmamap_create failed */ ++ u_int32_t hst_nomem_load; /* bus_dmamap_load_* failed */ ++ u_int32_t hst_nomem_mbuf; /* MGET* failed */ ++ u_int32_t hst_nomem_mcl; /* MCLGET* failed */ ++ u_int32_t hst_nomem_cr; /* out of command/result descriptor */ ++ u_int32_t hst_nomem_sd; /* out of src/dst descriptors */ ++}; ++ ++#endif /* __HIFN7751VAR_H__ */ +diff -Nur linux-3.1.4.orig/crypto/ocf/hifn/hifnHIPP.c linux-3.1.4/crypto/ocf/hifn/hifnHIPP.c +--- linux-3.1.4.orig/crypto/ocf/hifn/hifnHIPP.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/hifn/hifnHIPP.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,420 @@ ++/*- ++ * Driver for Hifn HIPP-I/II chipset ++ * Copyright (c) 2006 Michael Richardson ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored by Hifn Inc. ++ * ++ */ ++ ++/* ++ * Driver for various Hifn encryption processors. ++ */ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "hifnHIPPreg.h" ++#include "hifnHIPPvar.h" ++ ++#if 1 ++#define DPRINTF(a...) if (hipp_debug) { \ ++ printk("%s: ", sc ? \ ++ device_get_nameunit(sc->sc_dev) : "hifn"); \ ++ printk(a); \ ++ } else ++#else ++#define DPRINTF(a...) ++#endif ++ ++typedef int bus_size_t; ++ ++static inline int ++pci_get_revid(struct pci_dev *dev) ++{ ++ u8 rid = 0; ++ pci_read_config_byte(dev, PCI_REVISION_ID, &rid); ++ return rid; ++} ++ ++#define debug hipp_debug ++int hipp_debug = 0; ++module_param(hipp_debug, int, 0644); ++MODULE_PARM_DESC(hipp_debug, "Enable debug"); ++ ++int hipp_maxbatch = 1; ++module_param(hipp_maxbatch, int, 0644); ++MODULE_PARM_DESC(hipp_maxbatch, "max ops to batch w/o interrupt"); ++ ++static int hipp_probe(struct pci_dev *dev, const struct pci_device_id *ent); ++static void hipp_remove(struct pci_dev *dev); ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) ++static irqreturn_t hipp_intr(int irq, void *arg); ++#else ++static irqreturn_t hipp_intr(int irq, void *arg, struct pt_regs *regs); ++#endif ++ ++static int hipp_num_chips = 0; ++static struct hipp_softc *hipp_chip_idx[HIPP_MAX_CHIPS]; ++ ++static int hipp_newsession(device_t, u_int32_t *, struct cryptoini *); ++static int hipp_freesession(device_t, u_int64_t); ++static int hipp_process(device_t, struct cryptop *, int); ++ ++static device_method_t hipp_methods = { ++ /* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, hipp_newsession), ++ DEVMETHOD(cryptodev_freesession,hipp_freesession), ++ DEVMETHOD(cryptodev_process, hipp_process), ++}; ++ ++static __inline u_int32_t ++READ_REG(struct hipp_softc *sc, unsigned int barno, bus_size_t reg) ++{ ++ u_int32_t v = readl(sc->sc_bar[barno] + reg); ++ //sc->sc_bar0_lastreg = (bus_size_t) -1; ++ return (v); ++} ++static __inline void ++WRITE_REG(struct hipp_softc *sc, unsigned int barno, bus_size_t reg, u_int32_t val) ++{ ++ writel(val, sc->sc_bar[barno] + reg); ++} ++ ++#define READ_REG_0(sc, reg) READ_REG(sc, 0, reg) ++#define WRITE_REG_0(sc, reg, val) WRITE_REG(sc,0, reg, val) ++#define READ_REG_1(sc, reg) READ_REG(sc, 1, reg) ++#define WRITE_REG_1(sc, reg, val) WRITE_REG(sc,1, reg, val) ++ ++static int ++hipp_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) ++{ ++ return EINVAL; ++} ++ ++static int ++hipp_freesession(device_t dev, u_int64_t tid) ++{ ++ return EINVAL; ++} ++ ++static int ++hipp_process(device_t dev, struct cryptop *crp, int hint) ++{ ++ return EINVAL; ++} ++ ++static const char* ++hipp_partname(struct hipp_softc *sc, char buf[128], size_t blen) ++{ ++ char *n = NULL; ++ ++ switch (pci_get_vendor(sc->sc_pcidev)) { ++ case PCI_VENDOR_HIFN: ++ switch (pci_get_device(sc->sc_pcidev)) { ++ case PCI_PRODUCT_HIFN_7855: n = "Hifn 7855"; ++ case PCI_PRODUCT_HIFN_8155: n = "Hifn 8155"; ++ case PCI_PRODUCT_HIFN_6500: n = "Hifn 6500"; ++ } ++ } ++ ++ if(n==NULL) { ++ snprintf(buf, blen, "VID=%02x,PID=%02x", ++ pci_get_vendor(sc->sc_pcidev), ++ pci_get_device(sc->sc_pcidev)); ++ } else { ++ buf[0]='\0'; ++ strncat(buf, n, blen); ++ } ++ return buf; ++} ++ ++struct hipp_fs_entry { ++ struct attribute attr; ++ /* other stuff */ ++}; ++ ++ ++static ssize_t ++cryptoid_show(struct device *dev, ++ struct device_attribute *attr, ++ char *buf) ++{ ++ struct hipp_softc *sc; ++ ++ sc = pci_get_drvdata(to_pci_dev (dev)); ++ return sprintf (buf, "%d\n", sc->sc_cid); ++} ++ ++struct device_attribute hipp_dev_cryptoid = __ATTR_RO(cryptoid); ++ ++/* ++ * Attach an interface that successfully probed. ++ */ ++static int ++hipp_probe(struct pci_dev *dev, const struct pci_device_id *ent) ++{ ++ struct hipp_softc *sc = NULL; ++ int i; ++ //char rbase; ++ //u_int16_t ena; ++ int rev; ++ //int rseg; ++ int rc; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ if (pci_enable_device(dev) < 0) ++ return(-ENODEV); ++ ++ if (pci_set_mwi(dev)) ++ return(-ENODEV); ++ ++ if (!dev->irq) { ++ printk("hifn: found device with no IRQ assigned. check BIOS settings!"); ++ pci_disable_device(dev); ++ return(-ENODEV); ++ } ++ ++ sc = (struct hipp_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); ++ if (!sc) ++ return(-ENOMEM); ++ memset(sc, 0, sizeof(*sc)); ++ ++ softc_device_init(sc, "hifn-hipp", hipp_num_chips, hipp_methods); ++ ++ sc->sc_pcidev = dev; ++ sc->sc_irq = -1; ++ sc->sc_cid = -1; ++ sc->sc_num = hipp_num_chips++; ++ ++ if (sc->sc_num < HIPP_MAX_CHIPS) ++ hipp_chip_idx[sc->sc_num] = sc; ++ ++ pci_set_drvdata(sc->sc_pcidev, sc); ++ ++ spin_lock_init(&sc->sc_mtx); ++ ++ /* ++ * Setup PCI resources. ++ * The READ_REG_0, WRITE_REG_0, READ_REG_1, ++ * and WRITE_REG_1 macros throughout the driver are used ++ * to permit better debugging. ++ */ ++ for(i=0; i<4; i++) { ++ unsigned long mem_start, mem_len; ++ mem_start = pci_resource_start(sc->sc_pcidev, i); ++ mem_len = pci_resource_len(sc->sc_pcidev, i); ++ sc->sc_barphy[i] = (caddr_t)mem_start; ++ sc->sc_bar[i] = (ocf_iomem_t) ioremap(mem_start, mem_len); ++ if (!sc->sc_bar[i]) { ++ device_printf(sc->sc_dev, "cannot map bar%d register space\n", i); ++ goto fail; ++ } ++ } ++ ++ //hipp_reset_board(sc, 0); ++ pci_set_master(sc->sc_pcidev); ++ ++ /* ++ * Arrange the interrupt line. ++ */ ++ rc = request_irq(dev->irq, hipp_intr, IRQF_SHARED, "hifn", sc); ++ if (rc) { ++ device_printf(sc->sc_dev, "could not map interrupt: %d\n", rc); ++ goto fail; ++ } ++ sc->sc_irq = dev->irq; ++ ++ rev = READ_REG_1(sc, HIPP_1_REVID) & 0xffff; ++ ++ { ++ char b[32]; ++ device_printf(sc->sc_dev, "%s, rev %u", ++ hipp_partname(sc, b, sizeof(b)), rev); ++ } ++ ++#if 0 ++ if (sc->sc_flags & HIFN_IS_7956) ++ printf(", pll=0x%x<%s clk, %ux mult>", ++ sc->sc_pllconfig, ++ sc->sc_pllconfig & HIFN_PLL_REF_SEL ? "ext" : "pci", ++ 2 + 2*((sc->sc_pllconfig & HIFN_PLL_ND) >> 11)); ++#endif ++ printf("\n"); ++ ++ sc->sc_cid = crypto_get_driverid(softc_get_device(sc),CRYPTOCAP_F_HARDWARE); ++ if (sc->sc_cid < 0) { ++ device_printf(sc->sc_dev, "could not get crypto driver id\n"); ++ goto fail; ++ } ++ ++#if 0 /* cannot work with a non-GPL module */ ++ /* make a sysfs entry to let the world know what entry we got */ ++ sysfs_create_file(&sc->sc_pcidev->dev.kobj, &hipp_dev_cryptoid.attr); ++#endif ++ ++#if 0 ++ init_timer(&sc->sc_tickto); ++ sc->sc_tickto.function = hifn_tick; ++ sc->sc_tickto.data = (unsigned long) sc->sc_num; ++ mod_timer(&sc->sc_tickto, jiffies + HZ); ++#endif ++ ++#if 0 /* no code here yet ?? */ ++ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); ++#endif ++ ++ return (0); ++ ++fail: ++ if (sc->sc_cid >= 0) ++ crypto_unregister_all(sc->sc_cid); ++ if (sc->sc_irq != -1) ++ free_irq(sc->sc_irq, sc); ++ ++#if 0 ++ if (sc->sc_dma) { ++ /* Turn off DMA polling */ ++ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | ++ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); ++ ++ pci_free_consistent(sc->sc_pcidev, ++ sizeof(*sc->sc_dma), ++ sc->sc_dma, sc->sc_dma_physaddr); ++ } ++#endif ++ kfree(sc); ++ return (-ENXIO); ++} ++ ++/* ++ * Detach an interface that successfully probed. ++ */ ++static void ++hipp_remove(struct pci_dev *dev) ++{ ++ struct hipp_softc *sc = pci_get_drvdata(dev); ++ unsigned long l_flags; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ /* disable interrupts */ ++ HIPP_LOCK(sc); ++ ++#if 0 ++ WRITE_REG_1(sc, HIFN_1_DMA_IER, 0); ++ HIFN_UNLOCK(sc); ++ ++ /*XXX other resources */ ++ del_timer_sync(&sc->sc_tickto); ++ ++ /* Turn off DMA polling */ ++ WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | ++ HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); ++#endif ++ ++ crypto_unregister_all(sc->sc_cid); ++ ++ free_irq(sc->sc_irq, sc); ++ ++#if 0 ++ pci_free_consistent(sc->sc_pcidev, sizeof(*sc->sc_dma), ++ sc->sc_dma, sc->sc_dma_physaddr); ++#endif ++} ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) ++static irqreturn_t hipp_intr(int irq, void *arg) ++#else ++static irqreturn_t hipp_intr(int irq, void *arg, struct pt_regs *regs) ++#endif ++{ ++ struct hipp_softc *sc = arg; ++ ++ sc = sc; /* shut up compiler */ ++ ++ return IRQ_HANDLED; ++} ++ ++static struct pci_device_id hipp_pci_tbl[] = { ++ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_7855, ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, ++ { PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_8155, ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, ++}; ++MODULE_DEVICE_TABLE(pci, hipp_pci_tbl); ++ ++static struct pci_driver hipp_driver = { ++ .name = "hipp", ++ .id_table = hipp_pci_tbl, ++ .probe = hipp_probe, ++ .remove = hipp_remove, ++ /* add PM stuff here one day */ ++}; ++ ++static int __init hipp_init (void) ++{ ++ struct hipp_softc *sc = NULL; ++ int rc; ++ ++ DPRINTF("%s(%p)\n", __FUNCTION__, hipp_init); ++ ++ rc = pci_register_driver(&hipp_driver); ++ pci_register_driver_compat(&hipp_driver, rc); ++ ++ return rc; ++} ++ ++static void __exit hipp_exit (void) ++{ ++ pci_unregister_driver(&hipp_driver); ++} ++ ++module_init(hipp_init); ++module_exit(hipp_exit); ++ ++MODULE_LICENSE("BSD"); ++MODULE_AUTHOR("Michael Richardson "); ++MODULE_DESCRIPTION("OCF driver for hifn HIPP-I/II PCI crypto devices"); +diff -Nur linux-3.1.4.orig/crypto/ocf/hifn/hifnHIPPreg.h linux-3.1.4/crypto/ocf/hifn/hifnHIPPreg.h +--- linux-3.1.4.orig/crypto/ocf/hifn/hifnHIPPreg.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/hifn/hifnHIPPreg.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,46 @@ ++/*- ++ * Hifn HIPP-I/HIPP-II (7855/8155) driver. ++ * Copyright (c) 2006 Michael Richardson ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored by Hifn inc. ++ * ++ */ ++ ++#ifndef __HIFNHIPP_H__ ++#define __HIFNHIPP_H__ ++ ++/* ++ * PCI vendor and device identifiers ++ */ ++#define PCI_VENDOR_HIFN 0x13a3 /* Hifn */ ++#define PCI_PRODUCT_HIFN_6500 0x0006 /* 6500 */ ++#define PCI_PRODUCT_HIFN_7855 0x001f /* 7855 */ ++#define PCI_PRODUCT_HIFN_8155 0x999 /* XXX 8155 */ ++ ++#define HIPP_1_REVID 0x01 /* BOGUS */ ++ ++#endif /* __HIPP_H__ */ +diff -Nur linux-3.1.4.orig/crypto/ocf/hifn/hifnHIPPvar.h linux-3.1.4/crypto/ocf/hifn/hifnHIPPvar.h +--- linux-3.1.4.orig/crypto/ocf/hifn/hifnHIPPvar.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/hifn/hifnHIPPvar.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,93 @@ ++/* ++ * Hifn HIPP-I/HIPP-II (7855/8155) driver. ++ * Copyright (c) 2006 Michael Richardson * ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored by Hifn inc. ++ * ++ */ ++ ++#ifndef __HIFNHIPPVAR_H__ ++#define __HIFNHIPPVAR_H__ ++ ++#define HIPP_MAX_CHIPS 8 ++ ++/* ++ * Holds data specific to a single Hifn HIPP-I board. ++ */ ++struct hipp_softc { ++ softc_device_decl sc_dev; ++ ++ struct pci_dev *sc_pcidev; /* device backpointer */ ++ ocf_iomem_t sc_bar[5]; ++ caddr_t sc_barphy[5]; /* physical address */ ++ int sc_num; /* for multiple devs */ ++ spinlock_t sc_mtx; /* per-instance lock */ ++ int32_t sc_cid; ++ int sc_irq; ++ ++#if 0 ++ ++ u_int32_t sc_dmaier; ++ u_int32_t sc_drammodel; /* 1=dram, 0=sram */ ++ u_int32_t sc_pllconfig; /* 7954/7955/7956 PLL config */ ++ ++ struct hifn_dma *sc_dma; ++ dma_addr_t sc_dma_physaddr;/* physical address of sc_dma */ ++ ++ int sc_dmansegs; ++ int sc_maxses; ++ int sc_nsessions; ++ struct hifn_session *sc_sessions; ++ int sc_ramsize; ++ int sc_flags; ++#define HIFN_HAS_RNG 0x1 /* includes random number generator */ ++#define HIFN_HAS_PUBLIC 0x2 /* includes public key support */ ++#define HIFN_HAS_AES 0x4 /* includes AES support */ ++#define HIFN_IS_7811 0x8 /* Hifn 7811 part */ ++#define HIFN_IS_7956 0x10 /* Hifn 7956/7955 don't have SDRAM */ ++ ++ struct timer_list sc_tickto; /* for managing DMA */ ++ ++ int sc_rngfirst; ++ int sc_rnghz; /* RNG polling frequency */ ++ ++ int sc_c_busy; /* command ring busy */ ++ int sc_s_busy; /* source data ring busy */ ++ int sc_d_busy; /* destination data ring busy */ ++ int sc_r_busy; /* result ring busy */ ++ int sc_active; /* for initial countdown */ ++ int sc_needwakeup; /* ops q'd wating on resources */ ++ int sc_curbatch; /* # ops submitted w/o int */ ++ int sc_suspended; ++ struct miscdevice sc_miscdev; ++#endif ++}; ++ ++#define HIPP_LOCK(_sc) spin_lock_irqsave(&(_sc)->sc_mtx, l_flags) ++#define HIPP_UNLOCK(_sc) spin_unlock_irqrestore(&(_sc)->sc_mtx, l_flags) ++ ++#endif /* __HIFNHIPPVAR_H__ */ +diff -Nur linux-3.1.4.orig/crypto/ocf/ixp4xx/.#ixp4xx.c.1.46 linux-3.1.4/crypto/ocf/ixp4xx/.#ixp4xx.c.1.46 +--- linux-3.1.4.orig/crypto/ocf/ixp4xx/.#ixp4xx.c.1.46 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/ixp4xx/.#ixp4xx.c.1.46 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,1323 @@ ++/* ++ * An OCF module that uses Intels IXP CryptACC API to do the crypto. ++ * This driver requires the IXP400 Access Library that is available ++ * from Intel in order to operate (or compile). ++ * ++ * Written by David McCullough ++ * Copyright (C) 2006-2007 David McCullough ++ * Copyright (C) 2004-2005 Intel Corporation. ++ * ++ * LICENSE TERMS ++ * ++ * The free distribution and use of this software in both source and binary ++ * form is allowed (with or without changes) provided that: ++ * ++ * 1. distributions of this source code include the above copyright ++ * notice, this list of conditions and the following disclaimer; ++ * ++ * 2. distributions in binary form include the above copyright ++ * notice, this list of conditions and the following disclaimer ++ * in the documentation and/or other associated materials; ++ * ++ * 3. the copyright holder's name is not used to endorse products ++ * built using this software without specific written permission. ++ * ++ * ALTERNATIVELY, provided that this notice is retained in full, this product ++ * may be distributed under the terms of the GNU General Public License (GPL), ++ * in which case the provisions of the GPL apply INSTEAD OF those given above. ++ * ++ * DISCLAIMER ++ * ++ * This software is provided 'as is' with no explicit or implied warranties ++ * in respect of its properties, including, but not limited to, correctness ++ * and/or fitness for purpose. ++ */ ++ ++#ifndef AUTOCONF_INCLUDED ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#ifndef IX_MBUF_PRIV ++#define IX_MBUF_PRIV(x) ((x)->priv) ++#endif ++ ++struct ixp_data; ++ ++struct ixp_q { ++ struct list_head ixp_q_list; ++ struct ixp_data *ixp_q_data; ++ struct cryptop *ixp_q_crp; ++ struct cryptodesc *ixp_q_ccrd; ++ struct cryptodesc *ixp_q_acrd; ++ IX_MBUF ixp_q_mbuf; ++ UINT8 *ixp_hash_dest; /* Location for hash in client buffer */ ++ UINT8 *ixp_hash_src; /* Location of hash in internal buffer */ ++ unsigned char ixp_q_iv_data[IX_CRYPTO_ACC_MAX_CIPHER_IV_LENGTH]; ++ unsigned char *ixp_q_iv; ++}; ++ ++struct ixp_data { ++ int ixp_registered; /* is the context registered */ ++ int ixp_crd_flags; /* detect direction changes */ ++ ++ int ixp_cipher_alg; ++ int ixp_auth_alg; ++ ++ UINT32 ixp_ctx_id; ++ UINT32 ixp_hash_key_id; /* used when hashing */ ++ IxCryptoAccCtx ixp_ctx; ++ IX_MBUF ixp_pri_mbuf; ++ IX_MBUF ixp_sec_mbuf; ++ ++ struct work_struct ixp_pending_work; ++ struct work_struct ixp_registration_work; ++ struct list_head ixp_q; /* unprocessed requests */ ++}; ++ ++#ifdef __ixp46X ++ ++#define MAX_IOP_SIZE 64 /* words */ ++#define MAX_OOP_SIZE 128 ++ ++#define MAX_PARAMS 3 ++ ++struct ixp_pkq { ++ struct list_head pkq_list; ++ struct cryptkop *pkq_krp; ++ ++ IxCryptoAccPkeEauInOperands pkq_op; ++ IxCryptoAccPkeEauOpResult pkq_result; ++ ++ UINT32 pkq_ibuf0[MAX_IOP_SIZE]; ++ UINT32 pkq_ibuf1[MAX_IOP_SIZE]; ++ UINT32 pkq_ibuf2[MAX_IOP_SIZE]; ++ UINT32 pkq_obuf[MAX_OOP_SIZE]; ++}; ++ ++static LIST_HEAD(ixp_pkq); /* current PK wait list */ ++static struct ixp_pkq *ixp_pk_cur; ++static spinlock_t ixp_pkq_lock; ++ ++#endif /* __ixp46X */ ++ ++static int ixp_blocked = 0; ++ ++static int32_t ixp_id = -1; ++static struct ixp_data **ixp_sessions = NULL; ++static u_int32_t ixp_sesnum = 0; ++ ++static int ixp_process(device_t, struct cryptop *, int); ++static int ixp_newsession(device_t, u_int32_t *, struct cryptoini *); ++static int ixp_freesession(device_t, u_int64_t); ++#ifdef __ixp46X ++static int ixp_kprocess(device_t, struct cryptkop *krp, int hint); ++#endif ++ ++static struct kmem_cache *qcache; ++ ++#define debug ixp_debug ++static int ixp_debug = 0; ++module_param(ixp_debug, int, 0644); ++MODULE_PARM_DESC(ixp_debug, "Enable debug"); ++ ++static int ixp_init_crypto = 1; ++module_param(ixp_init_crypto, int, 0444); /* RO after load/boot */ ++MODULE_PARM_DESC(ixp_init_crypto, "Call ixCryptoAccInit (default is 1)"); ++ ++static void ixp_process_pending(void *arg); ++static void ixp_registration(void *arg); ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++static void ixp_process_pending_wq(struct work_struct *work); ++static void ixp_registration_wq(struct work_struct *work); ++#endif ++ ++/* ++ * dummy device structure ++ */ ++ ++static struct { ++ softc_device_decl sc_dev; ++} ixpdev; ++ ++static device_method_t ixp_methods = { ++ /* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, ixp_newsession), ++ DEVMETHOD(cryptodev_freesession,ixp_freesession), ++ DEVMETHOD(cryptodev_process, ixp_process), ++#ifdef __ixp46X ++ DEVMETHOD(cryptodev_kprocess, ixp_kprocess), ++#endif ++}; ++ ++/* ++ * Generate a new software session. ++ */ ++static int ++ixp_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) ++{ ++ struct ixp_data *ixp; ++ u_int32_t i; ++#define AUTH_LEN(cri, def) \ ++ (cri->cri_mlen ? cri->cri_mlen : (def)) ++ ++ dprintk("%s():alg %d\n", __FUNCTION__,cri->cri_alg); ++ if (sid == NULL || cri == NULL) { ++ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ if (ixp_sessions) { ++ for (i = 1; i < ixp_sesnum; i++) ++ if (ixp_sessions[i] == NULL) ++ break; ++ } else ++ i = 1; /* NB: to silence compiler warning */ ++ ++ if (ixp_sessions == NULL || i == ixp_sesnum) { ++ struct ixp_data **ixpd; ++ ++ if (ixp_sessions == NULL) { ++ i = 1; /* We leave ixp_sessions[0] empty */ ++ ixp_sesnum = CRYPTO_SW_SESSIONS; ++ } else ++ ixp_sesnum *= 2; ++ ++ ixpd = kmalloc(ixp_sesnum * sizeof(struct ixp_data *), SLAB_ATOMIC); ++ if (ixpd == NULL) { ++ /* Reset session number */ ++ if (ixp_sesnum == CRYPTO_SW_SESSIONS) ++ ixp_sesnum = 0; ++ else ++ ixp_sesnum /= 2; ++ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ memset(ixpd, 0, ixp_sesnum * sizeof(struct ixp_data *)); ++ ++ /* Copy existing sessions */ ++ if (ixp_sessions) { ++ memcpy(ixpd, ixp_sessions, ++ (ixp_sesnum / 2) * sizeof(struct ixp_data *)); ++ kfree(ixp_sessions); ++ } ++ ++ ixp_sessions = ixpd; ++ } ++ ++ ixp_sessions[i] = (struct ixp_data *) kmalloc(sizeof(struct ixp_data), ++ SLAB_ATOMIC); ++ if (ixp_sessions[i] == NULL) { ++ ixp_freesession(NULL, i); ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ ++ *sid = i; ++ ++ ixp = ixp_sessions[i]; ++ memset(ixp, 0, sizeof(*ixp)); ++ ++ ixp->ixp_cipher_alg = -1; ++ ixp->ixp_auth_alg = -1; ++ ixp->ixp_ctx_id = -1; ++ INIT_LIST_HEAD(&ixp->ixp_q); ++ ++ ixp->ixp_ctx.useDifferentSrcAndDestMbufs = 0; ++ ++ while (cri) { ++ switch (cri->cri_alg) { ++ case CRYPTO_DES_CBC: ++ ixp->ixp_cipher_alg = cri->cri_alg; ++ ixp->ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_DES; ++ ixp->ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; ++ ixp->ixp_ctx.cipherCtx.cipherKeyLen = (cri->cri_klen + 7) / 8; ++ ixp->ixp_ctx.cipherCtx.cipherBlockLen = IX_CRYPTO_ACC_DES_BLOCK_64; ++ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen = ++ IX_CRYPTO_ACC_DES_IV_64; ++ memcpy(ixp->ixp_ctx.cipherCtx.key.cipherKey, ++ cri->cri_key, (cri->cri_klen + 7) / 8); ++ break; ++ ++ case CRYPTO_3DES_CBC: ++ ixp->ixp_cipher_alg = cri->cri_alg; ++ ixp->ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_3DES; ++ ixp->ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; ++ ixp->ixp_ctx.cipherCtx.cipherKeyLen = (cri->cri_klen + 7) / 8; ++ ixp->ixp_ctx.cipherCtx.cipherBlockLen = IX_CRYPTO_ACC_DES_BLOCK_64; ++ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen = ++ IX_CRYPTO_ACC_DES_IV_64; ++ memcpy(ixp->ixp_ctx.cipherCtx.key.cipherKey, ++ cri->cri_key, (cri->cri_klen + 7) / 8); ++ break; ++ ++ case CRYPTO_RIJNDAEL128_CBC: ++ ixp->ixp_cipher_alg = cri->cri_alg; ++ ixp->ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_AES; ++ ixp->ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; ++ ixp->ixp_ctx.cipherCtx.cipherKeyLen = (cri->cri_klen + 7) / 8; ++ ixp->ixp_ctx.cipherCtx.cipherBlockLen = 16; ++ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen = 16; ++ memcpy(ixp->ixp_ctx.cipherCtx.key.cipherKey, ++ cri->cri_key, (cri->cri_klen + 7) / 8); ++ break; ++ ++ case CRYPTO_MD5: ++ case CRYPTO_MD5_HMAC: ++ ixp->ixp_auth_alg = cri->cri_alg; ++ ixp->ixp_ctx.authCtx.authAlgo = IX_CRYPTO_ACC_AUTH_MD5; ++ ixp->ixp_ctx.authCtx.authDigestLen = AUTH_LEN(cri, MD5_HASH_LEN); ++ ixp->ixp_ctx.authCtx.aadLen = 0; ++ /* Only MD5_HMAC needs a key */ ++ if (cri->cri_alg == CRYPTO_MD5_HMAC) { ++ ixp->ixp_ctx.authCtx.authKeyLen = (cri->cri_klen + 7) / 8; ++ if (ixp->ixp_ctx.authCtx.authKeyLen > ++ sizeof(ixp->ixp_ctx.authCtx.key.authKey)) { ++ printk( ++ "ixp4xx: Invalid key length for MD5_HMAC - %d bits\n", ++ cri->cri_klen); ++ ixp_freesession(NULL, i); ++ return EINVAL; ++ } ++ memcpy(ixp->ixp_ctx.authCtx.key.authKey, ++ cri->cri_key, (cri->cri_klen + 7) / 8); ++ } ++ break; ++ ++ case CRYPTO_SHA1: ++ case CRYPTO_SHA1_HMAC: ++ ixp->ixp_auth_alg = cri->cri_alg; ++ ixp->ixp_ctx.authCtx.authAlgo = IX_CRYPTO_ACC_AUTH_SHA1; ++ ixp->ixp_ctx.authCtx.authDigestLen = AUTH_LEN(cri, SHA1_HASH_LEN); ++ ixp->ixp_ctx.authCtx.aadLen = 0; ++ /* Only SHA1_HMAC needs a key */ ++ if (cri->cri_alg == CRYPTO_SHA1_HMAC) { ++ ixp->ixp_ctx.authCtx.authKeyLen = (cri->cri_klen + 7) / 8; ++ if (ixp->ixp_ctx.authCtx.authKeyLen > ++ sizeof(ixp->ixp_ctx.authCtx.key.authKey)) { ++ printk( ++ "ixp4xx: Invalid key length for SHA1_HMAC - %d bits\n", ++ cri->cri_klen); ++ ixp_freesession(NULL, i); ++ return EINVAL; ++ } ++ memcpy(ixp->ixp_ctx.authCtx.key.authKey, ++ cri->cri_key, (cri->cri_klen + 7) / 8); ++ } ++ break; ++ ++ default: ++ printk("ixp: unknown algo 0x%x\n", cri->cri_alg); ++ ixp_freesession(NULL, i); ++ return EINVAL; ++ } ++ cri = cri->cri_next; ++ } ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++ INIT_WORK(&ixp->ixp_pending_work, ixp_process_pending_wq); ++ INIT_WORK(&ixp->ixp_registration_work, ixp_registration_wq); ++#else ++ INIT_WORK(&ixp->ixp_pending_work, ixp_process_pending, ixp); ++ INIT_WORK(&ixp->ixp_registration_work, ixp_registration, ixp); ++#endif ++ ++ return 0; ++} ++ ++ ++/* ++ * Free a session. ++ */ ++static int ++ixp_freesession(device_t dev, u_int64_t tid) ++{ ++ u_int32_t sid = CRYPTO_SESID2LID(tid); ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (sid > ixp_sesnum || ixp_sessions == NULL || ++ ixp_sessions[sid] == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ /* Silently accept and return */ ++ if (sid == 0) ++ return 0; ++ ++ if (ixp_sessions[sid]) { ++ if (ixp_sessions[sid]->ixp_ctx_id != -1) { ++ ixCryptoAccCtxUnregister(ixp_sessions[sid]->ixp_ctx_id); ++ ixp_sessions[sid]->ixp_ctx_id = -1; ++ } ++ ++ flush_scheduled_work(); ++ ++ kfree(ixp_sessions[sid]); ++ } ++ ixp_sessions[sid] = NULL; ++ if (ixp_blocked) { ++ ixp_blocked = 0; ++ crypto_unblock(ixp_id, CRYPTO_SYMQ); ++ } ++ return 0; ++} ++ ++ ++/* ++ * callback for when hash processing is complete ++ */ ++ ++static void ++ixp_hash_perform_cb( ++ UINT32 hash_key_id, ++ IX_MBUF *bufp, ++ IxCryptoAccStatus status) ++{ ++ struct ixp_q *q; ++ ++ dprintk("%s(%u, %p, 0x%x)\n", __FUNCTION__, hash_key_id, bufp, status); ++ ++ if (bufp == NULL) { ++ printk("ixp: NULL buf in %s\n", __FUNCTION__); ++ return; ++ } ++ ++ q = IX_MBUF_PRIV(bufp); ++ if (q == NULL) { ++ printk("ixp: NULL priv in %s\n", __FUNCTION__); ++ return; ++ } ++ ++ if (status == IX_CRYPTO_ACC_STATUS_SUCCESS) { ++ /* On success, need to copy hash back into original client buffer */ ++ memcpy(q->ixp_hash_dest, q->ixp_hash_src, ++ (q->ixp_q_data->ixp_auth_alg == CRYPTO_SHA1) ? ++ SHA1_HASH_LEN : MD5_HASH_LEN); ++ } ++ else { ++ printk("ixp: hash perform failed status=%d\n", status); ++ q->ixp_q_crp->crp_etype = EINVAL; ++ } ++ ++ /* Free internal buffer used for hashing */ ++ kfree(IX_MBUF_MDATA(&q->ixp_q_mbuf)); ++ ++ crypto_done(q->ixp_q_crp); ++ kmem_cache_free(qcache, q); ++} ++ ++/* ++ * setup a request and perform it ++ */ ++static void ++ixp_q_process(struct ixp_q *q) ++{ ++ IxCryptoAccStatus status; ++ struct ixp_data *ixp = q->ixp_q_data; ++ int auth_off = 0; ++ int auth_len = 0; ++ int crypt_off = 0; ++ int crypt_len = 0; ++ int icv_off = 0; ++ char *crypt_func; ++ ++ dprintk("%s(%p)\n", __FUNCTION__, q); ++ ++ if (q->ixp_q_ccrd) { ++ if (q->ixp_q_ccrd->crd_flags & CRD_F_IV_EXPLICIT) { ++ q->ixp_q_iv = q->ixp_q_ccrd->crd_iv; ++ } else { ++ q->ixp_q_iv = q->ixp_q_iv_data; ++ crypto_copydata(q->ixp_q_crp->crp_flags, q->ixp_q_crp->crp_buf, ++ q->ixp_q_ccrd->crd_inject, ++ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen, ++ (caddr_t) q->ixp_q_iv); ++ } ++ ++ if (q->ixp_q_acrd) { ++ auth_off = q->ixp_q_acrd->crd_skip; ++ auth_len = q->ixp_q_acrd->crd_len; ++ icv_off = q->ixp_q_acrd->crd_inject; ++ } ++ ++ crypt_off = q->ixp_q_ccrd->crd_skip; ++ crypt_len = q->ixp_q_ccrd->crd_len; ++ } else { /* if (q->ixp_q_acrd) */ ++ auth_off = q->ixp_q_acrd->crd_skip; ++ auth_len = q->ixp_q_acrd->crd_len; ++ icv_off = q->ixp_q_acrd->crd_inject; ++ } ++ ++ if (q->ixp_q_crp->crp_flags & CRYPTO_F_SKBUF) { ++ struct sk_buff *skb = (struct sk_buff *) q->ixp_q_crp->crp_buf; ++ if (skb_shinfo(skb)->nr_frags) { ++ /* ++ * DAVIDM fix this limitation one day by using ++ * a buffer pool and chaining, it is not currently ++ * needed for current user/kernel space acceleration ++ */ ++ printk("ixp: Cannot handle fragmented skb's yet !\n"); ++ q->ixp_q_crp->crp_etype = ENOENT; ++ goto done; ++ } ++ IX_MBUF_MLEN(&q->ixp_q_mbuf) = ++ IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = skb->len; ++ IX_MBUF_MDATA(&q->ixp_q_mbuf) = skb->data; ++ } else if (q->ixp_q_crp->crp_flags & CRYPTO_F_IOV) { ++ struct uio *uiop = (struct uio *) q->ixp_q_crp->crp_buf; ++ if (uiop->uio_iovcnt != 1) { ++ /* ++ * DAVIDM fix this limitation one day by using ++ * a buffer pool and chaining, it is not currently ++ * needed for current user/kernel space acceleration ++ */ ++ printk("ixp: Cannot handle more than 1 iovec yet !\n"); ++ q->ixp_q_crp->crp_etype = ENOENT; ++ goto done; ++ } ++ IX_MBUF_MLEN(&q->ixp_q_mbuf) = ++ IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = uiop->uio_iov[0].iov_len; ++ IX_MBUF_MDATA(&q->ixp_q_mbuf) = uiop->uio_iov[0].iov_base; ++ } else /* contig buffer */ { ++ IX_MBUF_MLEN(&q->ixp_q_mbuf) = ++ IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = q->ixp_q_crp->crp_ilen; ++ IX_MBUF_MDATA(&q->ixp_q_mbuf) = q->ixp_q_crp->crp_buf; ++ } ++ ++ IX_MBUF_PRIV(&q->ixp_q_mbuf) = q; ++ ++ if (ixp->ixp_auth_alg == CRYPTO_SHA1 || ixp->ixp_auth_alg == CRYPTO_MD5) { ++ /* ++ * For SHA1 and MD5 hash, need to create an internal buffer that is big ++ * enough to hold the original data + the appropriate padding for the ++ * hash algorithm. ++ */ ++ UINT8 *tbuf = NULL; ++ ++ IX_MBUF_MLEN(&q->ixp_q_mbuf) = IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = ++ ((IX_MBUF_MLEN(&q->ixp_q_mbuf) * 8) + 72 + 511) / 8; ++ tbuf = kmalloc(IX_MBUF_MLEN(&q->ixp_q_mbuf), SLAB_ATOMIC); ++ ++ if (IX_MBUF_MDATA(&q->ixp_q_mbuf) == NULL) { ++ printk("ixp: kmalloc(%u, SLAB_ATOMIC) failed\n", ++ IX_MBUF_MLEN(&q->ixp_q_mbuf)); ++ q->ixp_q_crp->crp_etype = ENOMEM; ++ goto done; ++ } ++ memcpy(tbuf, &(IX_MBUF_MDATA(&q->ixp_q_mbuf))[auth_off], auth_len); ++ ++ /* Set location in client buffer to copy hash into */ ++ q->ixp_hash_dest = ++ &(IX_MBUF_MDATA(&q->ixp_q_mbuf))[auth_off + auth_len]; ++ ++ IX_MBUF_MDATA(&q->ixp_q_mbuf) = tbuf; ++ ++ /* Set location in internal buffer for where hash starts */ ++ q->ixp_hash_src = &(IX_MBUF_MDATA(&q->ixp_q_mbuf))[auth_len]; ++ ++ crypt_func = "ixCryptoAccHashPerform"; ++ status = ixCryptoAccHashPerform(ixp->ixp_ctx.authCtx.authAlgo, ++ &q->ixp_q_mbuf, ixp_hash_perform_cb, 0, auth_len, auth_len, ++ &ixp->ixp_hash_key_id); ++ } ++ else { ++ crypt_func = "ixCryptoAccAuthCryptPerform"; ++ status = ixCryptoAccAuthCryptPerform(ixp->ixp_ctx_id, &q->ixp_q_mbuf, ++ NULL, auth_off, auth_len, crypt_off, crypt_len, icv_off, ++ q->ixp_q_iv); ++ } ++ ++ if (IX_CRYPTO_ACC_STATUS_QUEUE_FULL == status) { ++ q->ixp_q_crp->crp_etype = ENOMEM; ++ goto done; ++ } ++ ++ if (IX_CRYPTO_ACC_STATUS_SUCCESS != status) { ++ printk("ixp: %s failed %u\n", crypt_func, status); ++ q->ixp_q_crp->crp_etype = EINVAL; ++ } ++ ++done: ++ crypto_done(q->ixp_q_crp); ++ kmem_cache_free(qcache, q); ++} ++ ++ ++/* ++ * because we cannot process the Q from the Register callback ++ * we do it here on a task Q. ++ */ ++ ++static void ++ixp_process_pending(void *arg) ++{ ++ struct ixp_data *ixp = arg; ++ struct ixp_q *q = NULL; ++ ++ dprintk("%s(%p)\n", __FUNCTION__, arg); ++ ++ if (!ixp) ++ return; ++ ++ while (!list_empty(&ixp->ixp_q)) { ++ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); ++ list_del(&q->ixp_q_list); ++ ixp_q_process(q); ++ } ++} ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++static void ++ixp_process_pending_wq(struct work_struct *work) ++{ ++ struct ixp_data *ixp = container_of(work, struct ixp_data, ++ ixp_pending_work); ++ ixp_process_pending(ixp); ++} ++#endif ++ ++/* ++ * callback for when context registration is complete ++ */ ++ ++static void ++ixp_register_cb(UINT32 ctx_id, IX_MBUF *bufp, IxCryptoAccStatus status) ++{ ++ int i; ++ struct ixp_data *ixp; ++ struct ixp_q *q; ++ ++ dprintk("%s(%d, %p, %d)\n", __FUNCTION__, ctx_id, bufp, status); ++ ++ /* ++ * free any buffer passed in to this routine ++ */ ++ if (bufp) { ++ IX_MBUF_MLEN(bufp) = IX_MBUF_PKT_LEN(bufp) = 0; ++ kfree(IX_MBUF_MDATA(bufp)); ++ IX_MBUF_MDATA(bufp) = NULL; ++ } ++ ++ for (i = 0; i < ixp_sesnum; i++) { ++ ixp = ixp_sessions[i]; ++ if (ixp && ixp->ixp_ctx_id == ctx_id) ++ break; ++ } ++ if (i >= ixp_sesnum) { ++ printk("ixp: invalid context id %d\n", ctx_id); ++ return; ++ } ++ ++ if (IX_CRYPTO_ACC_STATUS_WAIT == status) { ++ /* this is normal to free the first of two buffers */ ++ dprintk("ixp: register not finished yet.\n"); ++ return; ++ } ++ ++ if (IX_CRYPTO_ACC_STATUS_SUCCESS != status) { ++ printk("ixp: register failed 0x%x\n", status); ++ while (!list_empty(&ixp->ixp_q)) { ++ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); ++ list_del(&q->ixp_q_list); ++ q->ixp_q_crp->crp_etype = EINVAL; ++ crypto_done(q->ixp_q_crp); ++ kmem_cache_free(qcache, q); ++ } ++ return; ++ } ++ ++ /* ++ * we are now registered, we cannot start processing the Q here ++ * or we get strange errors with AES (DES/3DES seem to be ok). ++ */ ++ ixp->ixp_registered = 1; ++ schedule_work(&ixp->ixp_pending_work); ++} ++ ++ ++/* ++ * callback for when data processing is complete ++ */ ++ ++static void ++ixp_perform_cb( ++ UINT32 ctx_id, ++ IX_MBUF *sbufp, ++ IX_MBUF *dbufp, ++ IxCryptoAccStatus status) ++{ ++ struct ixp_q *q; ++ ++ dprintk("%s(%d, %p, %p, 0x%x)\n", __FUNCTION__, ctx_id, sbufp, ++ dbufp, status); ++ ++ if (sbufp == NULL) { ++ printk("ixp: NULL sbuf in ixp_perform_cb\n"); ++ return; ++ } ++ ++ q = IX_MBUF_PRIV(sbufp); ++ if (q == NULL) { ++ printk("ixp: NULL priv in ixp_perform_cb\n"); ++ return; ++ } ++ ++ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { ++ printk("ixp: perform failed status=%d\n", status); ++ q->ixp_q_crp->crp_etype = EINVAL; ++ } ++ ++ crypto_done(q->ixp_q_crp); ++ kmem_cache_free(qcache, q); ++} ++ ++ ++/* ++ * registration is not callable at IRQ time, so we defer ++ * to a task queue, this routines completes the registration for us ++ * when the task queue runs ++ * ++ * Unfortunately this means we cannot tell OCF that the driver is blocked, ++ * we do that on the next request. ++ */ ++ ++static void ++ixp_registration(void *arg) ++{ ++ struct ixp_data *ixp = arg; ++ struct ixp_q *q = NULL; ++ IX_MBUF *pri = NULL, *sec = NULL; ++ int status = IX_CRYPTO_ACC_STATUS_SUCCESS; ++ ++ if (!ixp) { ++ printk("ixp: ixp_registration with no arg\n"); ++ return; ++ } ++ ++ if (ixp->ixp_ctx_id != -1) { ++ ixCryptoAccCtxUnregister(ixp->ixp_ctx_id); ++ ixp->ixp_ctx_id = -1; ++ } ++ ++ if (list_empty(&ixp->ixp_q)) { ++ printk("ixp: ixp_registration with no Q\n"); ++ return; ++ } ++ ++ /* ++ * setup the primary and secondary buffers ++ */ ++ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); ++ if (q->ixp_q_acrd) { ++ pri = &ixp->ixp_pri_mbuf; ++ sec = &ixp->ixp_sec_mbuf; ++ IX_MBUF_MLEN(pri) = IX_MBUF_PKT_LEN(pri) = 128; ++ IX_MBUF_MDATA(pri) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); ++ IX_MBUF_MLEN(sec) = IX_MBUF_PKT_LEN(sec) = 128; ++ IX_MBUF_MDATA(sec) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); ++ } ++ ++ /* Only need to register if a crypt op or HMAC op */ ++ if (!(ixp->ixp_auth_alg == CRYPTO_SHA1 || ++ ixp->ixp_auth_alg == CRYPTO_MD5)) { ++ status = ixCryptoAccCtxRegister( ++ &ixp->ixp_ctx, ++ pri, sec, ++ ixp_register_cb, ++ ixp_perform_cb, ++ &ixp->ixp_ctx_id); ++ } ++ else { ++ /* Otherwise we start processing pending q */ ++ schedule_work(&ixp->ixp_pending_work); ++ } ++ ++ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) ++ return; ++ ++ if (IX_CRYPTO_ACC_STATUS_EXCEED_MAX_TUNNELS == status) { ++ printk("ixp: ixCryptoAccCtxRegister failed (out of tunnels)\n"); ++ ixp_blocked = 1; ++ /* perhaps we should return EGAIN on queued ops ? */ ++ return; ++ } ++ ++ printk("ixp: ixCryptoAccCtxRegister failed %d\n", status); ++ ixp->ixp_ctx_id = -1; ++ ++ /* ++ * everything waiting is toasted ++ */ ++ while (!list_empty(&ixp->ixp_q)) { ++ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); ++ list_del(&q->ixp_q_list); ++ q->ixp_q_crp->crp_etype = ENOENT; ++ crypto_done(q->ixp_q_crp); ++ kmem_cache_free(qcache, q); ++ } ++} ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++static void ++ixp_registration_wq(struct work_struct *work) ++{ ++ struct ixp_data *ixp = container_of(work, struct ixp_data, ++ ixp_registration_work); ++ ixp_registration(ixp); ++} ++#endif ++ ++/* ++ * Process a request. ++ */ ++static int ++ixp_process(device_t dev, struct cryptop *crp, int hint) ++{ ++ struct ixp_data *ixp; ++ unsigned int lid; ++ struct ixp_q *q = NULL; ++ int status; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ /* Sanity check */ ++ if (crp == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ crp->crp_etype = 0; ++ ++ if (ixp_blocked) ++ return ERESTART; ++ ++ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ crp->crp_etype = EINVAL; ++ goto done; ++ } ++ ++ /* ++ * find the session we are using ++ */ ++ ++ lid = crp->crp_sid & 0xffffffff; ++ if (lid >= ixp_sesnum || lid == 0 || ixp_sessions == NULL || ++ ixp_sessions[lid] == NULL) { ++ crp->crp_etype = ENOENT; ++ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); ++ goto done; ++ } ++ ixp = ixp_sessions[lid]; ++ ++ /* ++ * setup a new request ready for queuing ++ */ ++ q = kmem_cache_alloc(qcache, SLAB_ATOMIC); ++ if (q == NULL) { ++ dprintk("%s,%d: ENOMEM\n", __FILE__, __LINE__); ++ crp->crp_etype = ENOMEM; ++ goto done; ++ } ++ /* ++ * save some cycles by only zeroing the important bits ++ */ ++ memset(&q->ixp_q_mbuf, 0, sizeof(q->ixp_q_mbuf)); ++ q->ixp_q_ccrd = NULL; ++ q->ixp_q_acrd = NULL; ++ q->ixp_q_crp = crp; ++ q->ixp_q_data = ixp; ++ ++ /* ++ * point the cipher and auth descriptors appropriately ++ * check that we have something to do ++ */ ++ if (crp->crp_desc->crd_alg == ixp->ixp_cipher_alg) ++ q->ixp_q_ccrd = crp->crp_desc; ++ else if (crp->crp_desc->crd_alg == ixp->ixp_auth_alg) ++ q->ixp_q_acrd = crp->crp_desc; ++ else { ++ crp->crp_etype = ENOENT; ++ dprintk("%s,%d: bad desc match: ENOENT\n", __FILE__, __LINE__); ++ goto done; ++ } ++ if (crp->crp_desc->crd_next) { ++ if (crp->crp_desc->crd_next->crd_alg == ixp->ixp_cipher_alg) ++ q->ixp_q_ccrd = crp->crp_desc->crd_next; ++ else if (crp->crp_desc->crd_next->crd_alg == ixp->ixp_auth_alg) ++ q->ixp_q_acrd = crp->crp_desc->crd_next; ++ else { ++ crp->crp_etype = ENOENT; ++ dprintk("%s,%d: bad desc match: ENOENT\n", __FILE__, __LINE__); ++ goto done; ++ } ++ } ++ ++ /* ++ * If there is a direction change for this context then we mark it as ++ * unregistered and re-register is for the new direction. This is not ++ * a very expensive operation and currently only tends to happen when ++ * user-space application are doing benchmarks ++ * ++ * DM - we should be checking for pending requests before unregistering. ++ */ ++ if (q->ixp_q_ccrd && ixp->ixp_registered && ++ ixp->ixp_crd_flags != (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT)) { ++ dprintk("%s - detected direction change on session\n", __FUNCTION__); ++ ixp->ixp_registered = 0; ++ } ++ ++ /* ++ * if we are registered, call straight into the perform code ++ */ ++ if (ixp->ixp_registered) { ++ ixp_q_process(q); ++ return 0; ++ } ++ ++ /* ++ * the only part of the context not set in newsession is the direction ++ * dependent parts ++ */ ++ if (q->ixp_q_ccrd) { ++ ixp->ixp_crd_flags = (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT); ++ if (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT) { ++ ixp->ixp_ctx.operation = q->ixp_q_acrd ? ++ IX_CRYPTO_ACC_OP_ENCRYPT_AUTH : IX_CRYPTO_ACC_OP_ENCRYPT; ++ } else { ++ ixp->ixp_ctx.operation = q->ixp_q_acrd ? ++ IX_CRYPTO_ACC_OP_AUTH_DECRYPT : IX_CRYPTO_ACC_OP_DECRYPT; ++ } ++ } else { ++ /* q->ixp_q_acrd must be set if we are here */ ++ ixp->ixp_ctx.operation = IX_CRYPTO_ACC_OP_AUTH_CALC; ++ } ++ ++ status = list_empty(&ixp->ixp_q); ++ list_add_tail(&q->ixp_q_list, &ixp->ixp_q); ++ if (status) ++ schedule_work(&ixp->ixp_registration_work); ++ return 0; ++ ++done: ++ if (q) ++ kmem_cache_free(qcache, q); ++ crypto_done(crp); ++ return 0; ++} ++ ++ ++#ifdef __ixp46X ++/* ++ * key processing support for the ixp465 ++ */ ++ ++ ++/* ++ * copy a BN (LE) into a buffer (BE) an fill out the op appropriately ++ * assume zeroed and only copy bits that are significant ++ */ ++ ++static int ++ixp_copy_ibuf(struct crparam *p, IxCryptoAccPkeEauOperand *op, UINT32 *buf) ++{ ++ unsigned char *src = (unsigned char *) p->crp_p; ++ unsigned char *dst; ++ int len, bits = p->crp_nbits; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (bits > MAX_IOP_SIZE * sizeof(UINT32) * 8) { ++ dprintk("%s - ibuf too big (%d > %d)\n", __FUNCTION__, ++ bits, MAX_IOP_SIZE * sizeof(UINT32) * 8); ++ return -1; ++ } ++ ++ len = (bits + 31) / 32; /* the number UINT32's needed */ ++ ++ dst = (unsigned char *) &buf[len]; ++ dst--; ++ ++ while (bits > 0) { ++ *dst-- = *src++; ++ bits -= 8; ++ } ++ ++#if 0 /* no need to zero remaining bits as it is done during request alloc */ ++ while (dst > (unsigned char *) buf) ++ *dst-- = '\0'; ++#endif ++ ++ op->pData = buf; ++ op->dataLen = len; ++ return 0; ++} ++ ++/* ++ * copy out the result, be as forgiving as we can about small output buffers ++ */ ++ ++static int ++ixp_copy_obuf(struct crparam *p, IxCryptoAccPkeEauOpResult *op, UINT32 *buf) ++{ ++ unsigned char *dst = (unsigned char *) p->crp_p; ++ unsigned char *src = (unsigned char *) buf; ++ int len, z, bits = p->crp_nbits; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ len = op->dataLen * sizeof(UINT32); ++ ++ /* skip leading zeroes to be small buffer friendly */ ++ z = 0; ++ while (z < len && src[z] == '\0') ++ z++; ++ ++ src += len; ++ src--; ++ len -= z; ++ ++ while (len > 0 && bits > 0) { ++ *dst++ = *src--; ++ len--; ++ bits -= 8; ++ } ++ ++ while (bits > 0) { ++ *dst++ = '\0'; ++ bits -= 8; ++ } ++ ++ if (len > 0) { ++ dprintk("%s - obuf is %d (z=%d, ob=%d) bytes too small\n", ++ __FUNCTION__, len, z, p->crp_nbits / 8); ++ return -1; ++ } ++ ++ return 0; ++} ++ ++ ++/* ++ * the parameter offsets for exp_mod ++ */ ++ ++#define IXP_PARAM_BASE 0 ++#define IXP_PARAM_EXP 1 ++#define IXP_PARAM_MOD 2 ++#define IXP_PARAM_RES 3 ++ ++/* ++ * key processing complete callback, is also used to start processing ++ * by passing a NULL for pResult ++ */ ++ ++static void ++ixp_kperform_cb( ++ IxCryptoAccPkeEauOperation operation, ++ IxCryptoAccPkeEauOpResult *pResult, ++ BOOL carryOrBorrow, ++ IxCryptoAccStatus status) ++{ ++ struct ixp_pkq *q, *tmp; ++ unsigned long flags; ++ ++ dprintk("%s(0x%x, %p, %d, 0x%x)\n", __FUNCTION__, operation, pResult, ++ carryOrBorrow, status); ++ ++ /* handle a completed request */ ++ if (pResult) { ++ if (ixp_pk_cur && &ixp_pk_cur->pkq_result == pResult) { ++ q = ixp_pk_cur; ++ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { ++ dprintk("%s() - op failed 0x%x\n", __FUNCTION__, status); ++ q->pkq_krp->krp_status = ERANGE; /* could do better */ ++ } else { ++ /* copy out the result */ ++ if (ixp_copy_obuf(&q->pkq_krp->krp_param[IXP_PARAM_RES], ++ &q->pkq_result, q->pkq_obuf)) ++ q->pkq_krp->krp_status = ERANGE; ++ } ++ crypto_kdone(q->pkq_krp); ++ kfree(q); ++ ixp_pk_cur = NULL; ++ } else ++ printk("%s - callback with invalid result pointer\n", __FUNCTION__); ++ } ++ ++ spin_lock_irqsave(&ixp_pkq_lock, flags); ++ if (ixp_pk_cur || list_empty(&ixp_pkq)) { ++ spin_unlock_irqrestore(&ixp_pkq_lock, flags); ++ return; ++ } ++ ++ list_for_each_entry_safe(q, tmp, &ixp_pkq, pkq_list) { ++ ++ list_del(&q->pkq_list); ++ ixp_pk_cur = q; ++ ++ spin_unlock_irqrestore(&ixp_pkq_lock, flags); ++ ++ status = ixCryptoAccPkeEauPerform( ++ IX_CRYPTO_ACC_OP_EAU_MOD_EXP, ++ &q->pkq_op, ++ ixp_kperform_cb, ++ &q->pkq_result); ++ ++ if (status == IX_CRYPTO_ACC_STATUS_SUCCESS) { ++ dprintk("%s() - ixCryptoAccPkeEauPerform SUCCESS\n", __FUNCTION__); ++ return; /* callback will return here for callback */ ++ } else if (status == IX_CRYPTO_ACC_STATUS_RETRY) { ++ printk("%s() - ixCryptoAccPkeEauPerform RETRY\n", __FUNCTION__); ++ } else { ++ printk("%s() - ixCryptoAccPkeEauPerform failed %d\n", ++ __FUNCTION__, status); ++ } ++ q->pkq_krp->krp_status = ERANGE; /* could do better */ ++ crypto_kdone(q->pkq_krp); ++ kfree(q); ++ spin_lock_irqsave(&ixp_pkq_lock, flags); ++ } ++ spin_unlock_irqrestore(&ixp_pkq_lock, flags); ++} ++ ++ ++static int ++ixp_kprocess(device_t dev, struct cryptkop *krp, int hint) ++{ ++ struct ixp_pkq *q; ++ int rc = 0; ++ unsigned long flags; ++ ++ dprintk("%s l1=%d l2=%d l3=%d l4=%d\n", __FUNCTION__, ++ krp->krp_param[IXP_PARAM_BASE].crp_nbits, ++ krp->krp_param[IXP_PARAM_EXP].crp_nbits, ++ krp->krp_param[IXP_PARAM_MOD].crp_nbits, ++ krp->krp_param[IXP_PARAM_RES].crp_nbits); ++ ++ ++ if (krp->krp_op != CRK_MOD_EXP) { ++ krp->krp_status = EOPNOTSUPP; ++ goto err; ++ } ++ ++ q = (struct ixp_pkq *) kmalloc(sizeof(*q), GFP_KERNEL); ++ if (q == NULL) { ++ krp->krp_status = ENOMEM; ++ goto err; ++ } ++ ++ /* ++ * The PKE engine does not appear to zero the output buffer ++ * appropriately, so we need to do it all here. ++ */ ++ memset(q, 0, sizeof(*q)); ++ ++ q->pkq_krp = krp; ++ INIT_LIST_HEAD(&q->pkq_list); ++ ++ if (ixp_copy_ibuf(&krp->krp_param[IXP_PARAM_BASE], &q->pkq_op.modExpOpr.M, ++ q->pkq_ibuf0)) ++ rc = 1; ++ if (!rc && ixp_copy_ibuf(&krp->krp_param[IXP_PARAM_EXP], ++ &q->pkq_op.modExpOpr.e, q->pkq_ibuf1)) ++ rc = 2; ++ if (!rc && ixp_copy_ibuf(&krp->krp_param[IXP_PARAM_MOD], ++ &q->pkq_op.modExpOpr.N, q->pkq_ibuf2)) ++ rc = 3; ++ ++ if (rc) { ++ kfree(q); ++ krp->krp_status = ERANGE; ++ goto err; ++ } ++ ++ q->pkq_result.pData = q->pkq_obuf; ++ q->pkq_result.dataLen = ++ (krp->krp_param[IXP_PARAM_RES].crp_nbits + 31) / 32; ++ ++ spin_lock_irqsave(&ixp_pkq_lock, flags); ++ list_add_tail(&q->pkq_list, &ixp_pkq); ++ spin_unlock_irqrestore(&ixp_pkq_lock, flags); ++ ++ if (!ixp_pk_cur) ++ ixp_kperform_cb(0, NULL, 0, 0); ++ return (0); ++ ++err: ++ crypto_kdone(krp); ++ return (0); ++} ++ ++ ++ ++#ifdef CONFIG_OCF_RANDOMHARVEST ++/* ++ * We run the random number generator output through SHA so that it ++ * is FIPS compliant. ++ */ ++ ++static volatile int sha_done = 0; ++static unsigned char sha_digest[20]; ++ ++static void ++ixp_hash_cb(UINT8 *digest, IxCryptoAccStatus status) ++{ ++ dprintk("%s(%p, %d)\n", __FUNCTION__, digest, status); ++ if (sha_digest != digest) ++ printk("digest error\n"); ++ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) ++ sha_done = 1; ++ else ++ sha_done = -status; ++} ++ ++static int ++ixp_read_random(void *arg, u_int32_t *buf, int maxwords) ++{ ++ IxCryptoAccStatus status; ++ int i, n, rc; ++ ++ dprintk("%s(%p, %d)\n", __FUNCTION__, buf, maxwords); ++ memset(buf, 0, maxwords * sizeof(*buf)); ++ status = ixCryptoAccPkePseudoRandomNumberGet(maxwords, buf); ++ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { ++ dprintk("%s: ixCryptoAccPkePseudoRandomNumberGet failed %d\n", ++ __FUNCTION__, status); ++ return 0; ++ } ++ ++ /* ++ * run the random data through SHA to make it look more random ++ */ ++ ++ n = sizeof(sha_digest); /* process digest bytes at a time */ ++ ++ rc = 0; ++ for (i = 0; i < maxwords; i += n / sizeof(*buf)) { ++ if ((maxwords - i) * sizeof(*buf) < n) ++ n = (maxwords - i) * sizeof(*buf); ++ sha_done = 0; ++ status = ixCryptoAccPkeHashPerform(IX_CRYPTO_ACC_AUTH_SHA1, ++ (UINT8 *) &buf[i], n, ixp_hash_cb, sha_digest); ++ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { ++ dprintk("ixCryptoAccPkeHashPerform failed %d\n", status); ++ return -EIO; ++ } ++ while (!sha_done) ++ schedule(); ++ if (sha_done < 0) { ++ dprintk("ixCryptoAccPkeHashPerform failed CB %d\n", -sha_done); ++ return 0; ++ } ++ memcpy(&buf[i], sha_digest, n); ++ rc += n / sizeof(*buf);; ++ } ++ ++ return rc; ++} ++#endif /* CONFIG_OCF_RANDOMHARVEST */ ++ ++#endif /* __ixp46X */ ++ ++ ++ ++/* ++ * our driver startup and shutdown routines ++ */ ++ ++static int ++ixp_init(void) ++{ ++ dprintk("%s(%p)\n", __FUNCTION__, ixp_init); ++ ++ if (ixp_init_crypto && ixCryptoAccInit() != IX_CRYPTO_ACC_STATUS_SUCCESS) ++ printk("ixCryptoAccInit failed, assuming already initialised!\n"); ++ ++ qcache = kmem_cache_create("ixp4xx_q", sizeof(struct ixp_q), 0, ++ SLAB_HWCACHE_ALIGN, NULL ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) ++ , NULL ++#endif ++ ); ++ if (!qcache) { ++ printk("failed to create Qcache\n"); ++ return -ENOENT; ++ } ++ ++ memset(&ixpdev, 0, sizeof(ixpdev)); ++ softc_device_init(&ixpdev, "ixp4xx", 0, ixp_methods); ++ ++ ixp_id = crypto_get_driverid(softc_get_device(&ixpdev), ++ CRYPTOCAP_F_HARDWARE); ++ if (ixp_id < 0) ++ panic("IXP/OCF crypto device cannot initialize!"); ++ ++#define REGISTER(alg) \ ++ crypto_register(ixp_id,alg,0,0) ++ ++ REGISTER(CRYPTO_DES_CBC); ++ REGISTER(CRYPTO_3DES_CBC); ++ REGISTER(CRYPTO_RIJNDAEL128_CBC); ++#ifdef CONFIG_OCF_IXP4XX_SHA1_MD5 ++ REGISTER(CRYPTO_MD5); ++ REGISTER(CRYPTO_SHA1); ++#endif ++ REGISTER(CRYPTO_MD5_HMAC); ++ REGISTER(CRYPTO_SHA1_HMAC); ++#undef REGISTER ++ ++#ifdef __ixp46X ++ spin_lock_init(&ixp_pkq_lock); ++ /* ++ * we do not enable the go fast options here as they can potentially ++ * allow timing based attacks ++ * ++ * http://www.openssl.org/news/secadv_20030219.txt ++ */ ++ ixCryptoAccPkeEauExpConfig(0, 0); ++ crypto_kregister(ixp_id, CRK_MOD_EXP, 0); ++#ifdef CONFIG_OCF_RANDOMHARVEST ++ crypto_rregister(ixp_id, ixp_read_random, NULL); ++#endif ++#endif ++ ++ return 0; ++} ++ ++static void ++ixp_exit(void) ++{ ++ dprintk("%s()\n", __FUNCTION__); ++ crypto_unregister_all(ixp_id); ++ ixp_id = -1; ++ kmem_cache_destroy(qcache); ++ qcache = NULL; ++} ++ ++module_init(ixp_init); ++module_exit(ixp_exit); ++ ++MODULE_LICENSE("Dual BSD/GPL"); ++MODULE_AUTHOR("David McCullough "); ++MODULE_DESCRIPTION("ixp (OCF module for IXP4xx crypto)"); +diff -Nur linux-3.1.4.orig/crypto/ocf/ixp4xx/Makefile linux-3.1.4/crypto/ocf/ixp4xx/Makefile +--- linux-3.1.4.orig/crypto/ocf/ixp4xx/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/ixp4xx/Makefile 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,104 @@ ++# for SGlinux builds ++-include $(ROOTDIR)/modules/.config ++ ++# ++# You will need to point this at your Intel ixp425 includes, this portion ++# of the Makefile only really works under SGLinux with the appropriate libs ++# installed. They can be downloaded from http://www.snapgear.org/ ++# ++ifeq ($(CONFIG_CPU_IXP46X),y) ++IXPLATFORM = ixp46X ++else ++ifeq ($(CONFIG_CPU_IXP43X),y) ++IXPLATFORM = ixp43X ++else ++IXPLATFORM = ixp42X ++endif ++endif ++ ++ifdef CONFIG_IXP400_LIB_2_4 ++IX_XSCALE_SW = $(ROOTDIR)/modules/ixp425/ixp400-2.4/ixp400_xscale_sw ++OSAL_DIR = $(ROOTDIR)/modules/ixp425/ixp400-2.4/ixp_osal ++endif ++ifdef CONFIG_IXP400_LIB_2_1 ++IX_XSCALE_SW = $(ROOTDIR)/modules/ixp425/ixp400-2.1/ixp400_xscale_sw ++OSAL_DIR = $(ROOTDIR)/modules/ixp425/ixp400-2.1/ixp_osal ++endif ++ifdef CONFIG_IXP400_LIB_2_0 ++IX_XSCALE_SW = $(ROOTDIR)/modules/ixp425/ixp400-2.0/ixp400_xscale_sw ++OSAL_DIR = $(ROOTDIR)/modules/ixp425/ixp400-2.0/ixp_osal ++endif ++ifdef IX_XSCALE_SW ++ifdef CONFIG_IXP400_LIB_2_4 ++IXP_CFLAGS = \ ++ -I$(ROOTDIR)/. \ ++ -I$(IX_XSCALE_SW)/src/include \ ++ -I$(OSAL_DIR)/common/include/ \ ++ -I$(OSAL_DIR)/common/include/modules/ \ ++ -I$(OSAL_DIR)/common/include/modules/ddk/ \ ++ -I$(OSAL_DIR)/common/include/modules/bufferMgt/ \ ++ -I$(OSAL_DIR)/common/include/modules/ioMem/ \ ++ -I$(OSAL_DIR)/common/os/linux/include/ \ ++ -I$(OSAL_DIR)/common/os/linux/include/core/ \ ++ -I$(OSAL_DIR)/common/os/linux/include/modules/ \ ++ -I$(OSAL_DIR)/common/os/linux/include/modules/ddk/ \ ++ -I$(OSAL_DIR)/common/os/linux/include/modules/bufferMgt/ \ ++ -I$(OSAL_DIR)/common/os/linux/include/modules/ioMem/ \ ++ -I$(OSAL_DIR)/platforms/$(IXPLATFORM)/include/ \ ++ -I$(OSAL_DIR)/platforms/$(IXPLATFORM)/os/linux/include/ \ ++ -DENABLE_IOMEM -DENABLE_BUFFERMGT -DENABLE_DDK \ ++ -DUSE_IXP4XX_CRYPTO ++else ++IXP_CFLAGS = \ ++ -I$(ROOTDIR)/. \ ++ -I$(IX_XSCALE_SW)/src/include \ ++ -I$(OSAL_DIR)/ \ ++ -I$(OSAL_DIR)/os/linux/include/ \ ++ -I$(OSAL_DIR)/os/linux/include/modules/ \ ++ -I$(OSAL_DIR)/os/linux/include/modules/ioMem/ \ ++ -I$(OSAL_DIR)/os/linux/include/modules/bufferMgt/ \ ++ -I$(OSAL_DIR)/os/linux/include/core/ \ ++ -I$(OSAL_DIR)/os/linux/include/platforms/ \ ++ -I$(OSAL_DIR)/os/linux/include/platforms/ixp400/ \ ++ -I$(OSAL_DIR)/os/linux/include/platforms/ixp400/ixp425 \ ++ -I$(OSAL_DIR)/os/linux/include/platforms/ixp400/ixp465 \ ++ -I$(OSAL_DIR)/os/linux/include/core/ \ ++ -I$(OSAL_DIR)/include/ \ ++ -I$(OSAL_DIR)/include/modules/ \ ++ -I$(OSAL_DIR)/include/modules/bufferMgt/ \ ++ -I$(OSAL_DIR)/include/modules/ioMem/ \ ++ -I$(OSAL_DIR)/include/platforms/ \ ++ -I$(OSAL_DIR)/include/platforms/ixp400/ \ ++ -DUSE_IXP4XX_CRYPTO ++endif ++endif ++ifdef CONFIG_IXP400_LIB_1_4 ++IXP_CFLAGS = \ ++ -I$(ROOTDIR)/. \ ++ -I$(ROOTDIR)/modules/ixp425/ixp400-1.4/ixp400_xscale_sw/src/include \ ++ -I$(ROOTDIR)/modules/ixp425/ixp400-1.4/ixp400_xscale_sw/src/linux \ ++ -DUSE_IXP4XX_CRYPTO ++endif ++ifndef IXPDIR ++IXPDIR = ixp-version-is-not-supported ++endif ++ ++ifeq ($(CONFIG_CPU_IXP46X),y) ++IXP_CFLAGS += -D__ixp46X ++else ++ifeq ($(CONFIG_CPU_IXP43X),y) ++IXP_CFLAGS += -D__ixp43X ++else ++IXP_CFLAGS += -D__ixp42X ++endif ++endif ++ ++obj-$(CONFIG_OCF_IXP4XX) += ixp4xx.o ++ ++obj ?= . ++EXTRA_CFLAGS += $(IXP_CFLAGS) -I$(obj)/.. -I$(obj)/. ++ ++ifdef TOPDIR ++-include $(TOPDIR)/Rules.make ++endif ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/ixp4xx/ixp4xx.c linux-3.1.4/crypto/ocf/ixp4xx/ixp4xx.c +--- linux-3.1.4.orig/crypto/ocf/ixp4xx/ixp4xx.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/ixp4xx/ixp4xx.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,1339 @@ ++/* ++ * An OCF module that uses Intels IXP CryptACC API to do the crypto. ++ * This driver requires the IXP400 Access Library that is available ++ * from Intel in order to operate (or compile). ++ * ++ * Written by David McCullough ++ * Copyright (C) 2006-2011 David McCullough ++ * Copyright (C) 2004-2005 Intel Corporation. ++ * ++ * LICENSE TERMS ++ * ++ * The free distribution and use of this software in both source and binary ++ * form is allowed (with or without changes) provided that: ++ * ++ * 1. distributions of this source code include the above copyright ++ * notice, this list of conditions and the following disclaimer; ++ * ++ * 2. distributions in binary form include the above copyright ++ * notice, this list of conditions and the following disclaimer ++ * in the documentation and/or other associated materials; ++ * ++ * 3. the copyright holder's name is not used to endorse products ++ * built using this software without specific written permission. ++ * ++ * ALTERNATIVELY, provided that this notice is retained in full, this product ++ * may be distributed under the terms of the GNU General Public License (GPL), ++ * in which case the provisions of the GPL apply INSTEAD OF those given above. ++ * ++ * DISCLAIMER ++ * ++ * This software is provided 'as is' with no explicit or implied warranties ++ * in respect of its properties, including, but not limited to, correctness ++ * and/or fitness for purpose. ++ */ ++ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#ifndef IX_MBUF_PRIV ++#define IX_MBUF_PRIV(x) ((x)->priv) ++#endif ++ ++struct ixp_data; ++ ++struct ixp_q { ++ struct list_head ixp_q_list; ++ struct ixp_data *ixp_q_data; ++ struct cryptop *ixp_q_crp; ++ struct cryptodesc *ixp_q_ccrd; ++ struct cryptodesc *ixp_q_acrd; ++ IX_MBUF ixp_q_mbuf; ++ UINT8 *ixp_hash_dest; /* Location for hash in client buffer */ ++ UINT8 *ixp_hash_src; /* Location of hash in internal buffer */ ++ unsigned char ixp_q_iv_data[IX_CRYPTO_ACC_MAX_CIPHER_IV_LENGTH]; ++ unsigned char *ixp_q_iv; ++}; ++ ++struct ixp_data { ++ int ixp_registered; /* is the context registered */ ++ int ixp_crd_flags; /* detect direction changes */ ++ ++ int ixp_cipher_alg; ++ int ixp_auth_alg; ++ ++ UINT32 ixp_ctx_id; ++ UINT32 ixp_hash_key_id; /* used when hashing */ ++ IxCryptoAccCtx ixp_ctx; ++ IX_MBUF ixp_pri_mbuf; ++ IX_MBUF ixp_sec_mbuf; ++ ++ struct work_struct ixp_pending_work; ++ struct work_struct ixp_registration_work; ++ struct list_head ixp_q; /* unprocessed requests */ ++}; ++ ++#ifdef __ixp46X ++ ++#define MAX_IOP_SIZE 64 /* words */ ++#define MAX_OOP_SIZE 128 ++ ++#define MAX_PARAMS 3 ++ ++struct ixp_pkq { ++ struct list_head pkq_list; ++ struct cryptkop *pkq_krp; ++ ++ IxCryptoAccPkeEauInOperands pkq_op; ++ IxCryptoAccPkeEauOpResult pkq_result; ++ ++ UINT32 pkq_ibuf0[MAX_IOP_SIZE]; ++ UINT32 pkq_ibuf1[MAX_IOP_SIZE]; ++ UINT32 pkq_ibuf2[MAX_IOP_SIZE]; ++ UINT32 pkq_obuf[MAX_OOP_SIZE]; ++}; ++ ++static LIST_HEAD(ixp_pkq); /* current PK wait list */ ++static struct ixp_pkq *ixp_pk_cur; ++static spinlock_t ixp_pkq_lock; ++ ++#endif /* __ixp46X */ ++ ++static int ixp_blocked = 0; ++ ++static int32_t ixp_id = -1; ++static struct ixp_data **ixp_sessions = NULL; ++static u_int32_t ixp_sesnum = 0; ++ ++static int ixp_process(device_t, struct cryptop *, int); ++static int ixp_newsession(device_t, u_int32_t *, struct cryptoini *); ++static int ixp_freesession(device_t, u_int64_t); ++#ifdef __ixp46X ++static int ixp_kprocess(device_t, struct cryptkop *krp, int hint); ++#endif ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) ++static kmem_cache_t *qcache; ++#else ++static struct kmem_cache *qcache; ++#endif ++ ++#define debug ixp_debug ++static int ixp_debug = 0; ++module_param(ixp_debug, int, 0644); ++MODULE_PARM_DESC(ixp_debug, "Enable debug"); ++ ++static int ixp_init_crypto = 1; ++module_param(ixp_init_crypto, int, 0444); /* RO after load/boot */ ++MODULE_PARM_DESC(ixp_init_crypto, "Call ixCryptoAccInit (default is 1)"); ++ ++static void ixp_process_pending(void *arg); ++static void ixp_registration(void *arg); ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++static void ixp_process_pending_wq(struct work_struct *work); ++static void ixp_registration_wq(struct work_struct *work); ++#endif ++ ++/* ++ * dummy device structure ++ */ ++ ++static struct { ++ softc_device_decl sc_dev; ++} ixpdev; ++ ++static device_method_t ixp_methods = { ++ /* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, ixp_newsession), ++ DEVMETHOD(cryptodev_freesession,ixp_freesession), ++ DEVMETHOD(cryptodev_process, ixp_process), ++#ifdef __ixp46X ++ DEVMETHOD(cryptodev_kprocess, ixp_kprocess), ++#endif ++}; ++ ++/* ++ * Generate a new software session. ++ */ ++static int ++ixp_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) ++{ ++ struct ixp_data *ixp; ++ u_int32_t i; ++#define AUTH_LEN(cri, def) \ ++ (cri->cri_mlen ? cri->cri_mlen : (def)) ++ ++ dprintk("%s():alg %d\n", __FUNCTION__,cri->cri_alg); ++ if (sid == NULL || cri == NULL) { ++ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ if (ixp_sessions) { ++ for (i = 1; i < ixp_sesnum; i++) ++ if (ixp_sessions[i] == NULL) ++ break; ++ } else ++ i = 1; /* NB: to silence compiler warning */ ++ ++ if (ixp_sessions == NULL || i == ixp_sesnum) { ++ struct ixp_data **ixpd; ++ ++ if (ixp_sessions == NULL) { ++ i = 1; /* We leave ixp_sessions[0] empty */ ++ ixp_sesnum = CRYPTO_SW_SESSIONS; ++ } else ++ ixp_sesnum *= 2; ++ ++ ixpd = kmalloc(ixp_sesnum * sizeof(struct ixp_data *), SLAB_ATOMIC); ++ if (ixpd == NULL) { ++ /* Reset session number */ ++ if (ixp_sesnum == CRYPTO_SW_SESSIONS) ++ ixp_sesnum = 0; ++ else ++ ixp_sesnum /= 2; ++ dprintk("%s,%d: ENOBUFS\n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ memset(ixpd, 0, ixp_sesnum * sizeof(struct ixp_data *)); ++ ++ /* Copy existing sessions */ ++ if (ixp_sessions) { ++ memcpy(ixpd, ixp_sessions, ++ (ixp_sesnum / 2) * sizeof(struct ixp_data *)); ++ kfree(ixp_sessions); ++ } ++ ++ ixp_sessions = ixpd; ++ } ++ ++ ixp_sessions[i] = (struct ixp_data *) kmalloc(sizeof(struct ixp_data), ++ SLAB_ATOMIC); ++ if (ixp_sessions[i] == NULL) { ++ ixp_freesession(NULL, i); ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ ++ *sid = i; ++ ++ ixp = ixp_sessions[i]; ++ memset(ixp, 0, sizeof(*ixp)); ++ ++ ixp->ixp_cipher_alg = -1; ++ ixp->ixp_auth_alg = -1; ++ ixp->ixp_ctx_id = -1; ++ INIT_LIST_HEAD(&ixp->ixp_q); ++ ++ ixp->ixp_ctx.useDifferentSrcAndDestMbufs = 0; ++ ++ while (cri) { ++ switch (cri->cri_alg) { ++ case CRYPTO_DES_CBC: ++ ixp->ixp_cipher_alg = cri->cri_alg; ++ ixp->ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_DES; ++ ixp->ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; ++ ixp->ixp_ctx.cipherCtx.cipherKeyLen = (cri->cri_klen + 7) / 8; ++ ixp->ixp_ctx.cipherCtx.cipherBlockLen = IX_CRYPTO_ACC_DES_BLOCK_64; ++ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen = ++ IX_CRYPTO_ACC_DES_IV_64; ++ memcpy(ixp->ixp_ctx.cipherCtx.key.cipherKey, ++ cri->cri_key, (cri->cri_klen + 7) / 8); ++ break; ++ ++ case CRYPTO_3DES_CBC: ++ ixp->ixp_cipher_alg = cri->cri_alg; ++ ixp->ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_3DES; ++ ixp->ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; ++ ixp->ixp_ctx.cipherCtx.cipherKeyLen = (cri->cri_klen + 7) / 8; ++ ixp->ixp_ctx.cipherCtx.cipherBlockLen = IX_CRYPTO_ACC_DES_BLOCK_64; ++ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen = ++ IX_CRYPTO_ACC_DES_IV_64; ++ memcpy(ixp->ixp_ctx.cipherCtx.key.cipherKey, ++ cri->cri_key, (cri->cri_klen + 7) / 8); ++ break; ++ ++ case CRYPTO_RIJNDAEL128_CBC: ++ ixp->ixp_cipher_alg = cri->cri_alg; ++ ixp->ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_AES; ++ ixp->ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; ++ ixp->ixp_ctx.cipherCtx.cipherKeyLen = (cri->cri_klen + 7) / 8; ++ ixp->ixp_ctx.cipherCtx.cipherBlockLen = 16; ++ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen = 16; ++ memcpy(ixp->ixp_ctx.cipherCtx.key.cipherKey, ++ cri->cri_key, (cri->cri_klen + 7) / 8); ++ break; ++ ++ case CRYPTO_MD5: ++ case CRYPTO_MD5_HMAC: ++ ixp->ixp_auth_alg = cri->cri_alg; ++ ixp->ixp_ctx.authCtx.authAlgo = IX_CRYPTO_ACC_AUTH_MD5; ++ ixp->ixp_ctx.authCtx.authDigestLen = AUTH_LEN(cri, MD5_HASH_LEN); ++ ixp->ixp_ctx.authCtx.aadLen = 0; ++ /* Only MD5_HMAC needs a key */ ++ if (cri->cri_alg == CRYPTO_MD5_HMAC) { ++ ixp->ixp_ctx.authCtx.authKeyLen = (cri->cri_klen + 7) / 8; ++ if (ixp->ixp_ctx.authCtx.authKeyLen > ++ sizeof(ixp->ixp_ctx.authCtx.key.authKey)) { ++ printk( ++ "ixp4xx: Invalid key length for MD5_HMAC - %d bits\n", ++ cri->cri_klen); ++ ixp_freesession(NULL, i); ++ return EINVAL; ++ } ++ memcpy(ixp->ixp_ctx.authCtx.key.authKey, ++ cri->cri_key, (cri->cri_klen + 7) / 8); ++ } ++ break; ++ ++ case CRYPTO_SHA1: ++ case CRYPTO_SHA1_HMAC: ++ ixp->ixp_auth_alg = cri->cri_alg; ++ ixp->ixp_ctx.authCtx.authAlgo = IX_CRYPTO_ACC_AUTH_SHA1; ++ ixp->ixp_ctx.authCtx.authDigestLen = AUTH_LEN(cri, SHA1_HASH_LEN); ++ ixp->ixp_ctx.authCtx.aadLen = 0; ++ /* Only SHA1_HMAC needs a key */ ++ if (cri->cri_alg == CRYPTO_SHA1_HMAC) { ++ ixp->ixp_ctx.authCtx.authKeyLen = (cri->cri_klen + 7) / 8; ++ if (ixp->ixp_ctx.authCtx.authKeyLen > ++ sizeof(ixp->ixp_ctx.authCtx.key.authKey)) { ++ printk( ++ "ixp4xx: Invalid key length for SHA1_HMAC - %d bits\n", ++ cri->cri_klen); ++ ixp_freesession(NULL, i); ++ return EINVAL; ++ } ++ memcpy(ixp->ixp_ctx.authCtx.key.authKey, ++ cri->cri_key, (cri->cri_klen + 7) / 8); ++ } ++ break; ++ ++ default: ++ printk("ixp: unknown algo 0x%x\n", cri->cri_alg); ++ ixp_freesession(NULL, i); ++ return EINVAL; ++ } ++ cri = cri->cri_next; ++ } ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++ INIT_WORK(&ixp->ixp_pending_work, ixp_process_pending_wq); ++ INIT_WORK(&ixp->ixp_registration_work, ixp_registration_wq); ++#else ++ INIT_WORK(&ixp->ixp_pending_work, ixp_process_pending, ixp); ++ INIT_WORK(&ixp->ixp_registration_work, ixp_registration, ixp); ++#endif ++ ++ return 0; ++} ++ ++ ++/* ++ * Free a session. ++ */ ++static int ++ixp_freesession(device_t dev, u_int64_t tid) ++{ ++ u_int32_t sid = CRYPTO_SESID2LID(tid); ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (sid > ixp_sesnum || ixp_sessions == NULL || ++ ixp_sessions[sid] == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ /* Silently accept and return */ ++ if (sid == 0) ++ return 0; ++ ++ if (ixp_sessions[sid]) { ++ if (ixp_sessions[sid]->ixp_ctx_id != -1) { ++ ixCryptoAccCtxUnregister(ixp_sessions[sid]->ixp_ctx_id); ++ ixp_sessions[sid]->ixp_ctx_id = -1; ++ } ++ kfree(ixp_sessions[sid]); ++ } ++ ixp_sessions[sid] = NULL; ++ if (ixp_blocked) { ++ ixp_blocked = 0; ++ crypto_unblock(ixp_id, CRYPTO_SYMQ); ++ } ++ return 0; ++} ++ ++ ++/* ++ * callback for when hash processing is complete ++ */ ++ ++static void ++ixp_hash_perform_cb( ++ UINT32 hash_key_id, ++ IX_MBUF *bufp, ++ IxCryptoAccStatus status) ++{ ++ struct ixp_q *q; ++ ++ dprintk("%s(%u, %p, 0x%x)\n", __FUNCTION__, hash_key_id, bufp, status); ++ ++ if (bufp == NULL) { ++ printk("ixp: NULL buf in %s\n", __FUNCTION__); ++ return; ++ } ++ ++ q = IX_MBUF_PRIV(bufp); ++ if (q == NULL) { ++ printk("ixp: NULL priv in %s\n", __FUNCTION__); ++ return; ++ } ++ ++ if (status == IX_CRYPTO_ACC_STATUS_SUCCESS) { ++ /* On success, need to copy hash back into original client buffer */ ++ memcpy(q->ixp_hash_dest, q->ixp_hash_src, ++ (q->ixp_q_data->ixp_auth_alg == CRYPTO_SHA1) ? ++ SHA1_HASH_LEN : MD5_HASH_LEN); ++ } ++ else { ++ printk("ixp: hash perform failed status=%d\n", status); ++ q->ixp_q_crp->crp_etype = EINVAL; ++ } ++ ++ /* Free internal buffer used for hashing */ ++ kfree(IX_MBUF_MDATA(&q->ixp_q_mbuf)); ++ ++ crypto_done(q->ixp_q_crp); ++ kmem_cache_free(qcache, q); ++} ++ ++/* ++ * setup a request and perform it ++ */ ++static void ++ixp_q_process(struct ixp_q *q) ++{ ++ IxCryptoAccStatus status; ++ struct ixp_data *ixp = q->ixp_q_data; ++ int auth_off = 0; ++ int auth_len = 0; ++ int crypt_off = 0; ++ int crypt_len = 0; ++ int icv_off = 0; ++ char *crypt_func; ++ ++ dprintk("%s(%p)\n", __FUNCTION__, q); ++ ++ if (q->ixp_q_ccrd) { ++ if (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT) { ++ if (q->ixp_q_ccrd->crd_flags & CRD_F_IV_EXPLICIT) { ++ q->ixp_q_iv = q->ixp_q_ccrd->crd_iv; ++ } else { ++ q->ixp_q_iv = q->ixp_q_iv_data; ++ read_random(q->ixp_q_iv, ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen); ++ } ++ if ((q->ixp_q_ccrd->crd_flags & CRD_F_IV_PRESENT) == 0) ++ crypto_copyback(q->ixp_q_crp->crp_flags, q->ixp_q_crp->crp_buf, ++ q->ixp_q_ccrd->crd_inject, ++ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen, ++ (caddr_t) q->ixp_q_iv); ++ } else { ++ if (q->ixp_q_ccrd->crd_flags & CRD_F_IV_EXPLICIT) ++ q->ixp_q_iv = q->ixp_q_ccrd->crd_iv; ++ else { ++ q->ixp_q_iv = q->ixp_q_iv_data; ++ crypto_copydata(q->ixp_q_crp->crp_flags, q->ixp_q_crp->crp_buf, ++ q->ixp_q_ccrd->crd_inject, ++ ixp->ixp_ctx.cipherCtx.cipherInitialVectorLen, ++ (caddr_t) q->ixp_q_iv); ++ } ++ } ++ ++ if (q->ixp_q_acrd) { ++ auth_off = q->ixp_q_acrd->crd_skip; ++ auth_len = q->ixp_q_acrd->crd_len; ++ icv_off = q->ixp_q_acrd->crd_inject; ++ } ++ ++ crypt_off = q->ixp_q_ccrd->crd_skip; ++ crypt_len = q->ixp_q_ccrd->crd_len; ++ } else { /* if (q->ixp_q_acrd) */ ++ auth_off = q->ixp_q_acrd->crd_skip; ++ auth_len = q->ixp_q_acrd->crd_len; ++ icv_off = q->ixp_q_acrd->crd_inject; ++ } ++ ++ if (q->ixp_q_crp->crp_flags & CRYPTO_F_SKBUF) { ++ struct sk_buff *skb = (struct sk_buff *) q->ixp_q_crp->crp_buf; ++ if (skb_shinfo(skb)->nr_frags) { ++ /* ++ * DAVIDM fix this limitation one day by using ++ * a buffer pool and chaining, it is not currently ++ * needed for current user/kernel space acceleration ++ */ ++ printk("ixp: Cannot handle fragmented skb's yet !\n"); ++ q->ixp_q_crp->crp_etype = ENOENT; ++ goto done; ++ } ++ IX_MBUF_MLEN(&q->ixp_q_mbuf) = ++ IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = skb->len; ++ IX_MBUF_MDATA(&q->ixp_q_mbuf) = skb->data; ++ } else if (q->ixp_q_crp->crp_flags & CRYPTO_F_IOV) { ++ struct uio *uiop = (struct uio *) q->ixp_q_crp->crp_buf; ++ if (uiop->uio_iovcnt != 1) { ++ /* ++ * DAVIDM fix this limitation one day by using ++ * a buffer pool and chaining, it is not currently ++ * needed for current user/kernel space acceleration ++ */ ++ printk("ixp: Cannot handle more than 1 iovec yet !\n"); ++ q->ixp_q_crp->crp_etype = ENOENT; ++ goto done; ++ } ++ IX_MBUF_MLEN(&q->ixp_q_mbuf) = ++ IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = uiop->uio_iov[0].iov_len; ++ IX_MBUF_MDATA(&q->ixp_q_mbuf) = uiop->uio_iov[0].iov_base; ++ } else /* contig buffer */ { ++ IX_MBUF_MLEN(&q->ixp_q_mbuf) = ++ IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = q->ixp_q_crp->crp_ilen; ++ IX_MBUF_MDATA(&q->ixp_q_mbuf) = q->ixp_q_crp->crp_buf; ++ } ++ ++ IX_MBUF_PRIV(&q->ixp_q_mbuf) = q; ++ ++ if (ixp->ixp_auth_alg == CRYPTO_SHA1 || ixp->ixp_auth_alg == CRYPTO_MD5) { ++ /* ++ * For SHA1 and MD5 hash, need to create an internal buffer that is big ++ * enough to hold the original data + the appropriate padding for the ++ * hash algorithm. ++ */ ++ UINT8 *tbuf = NULL; ++ ++ IX_MBUF_MLEN(&q->ixp_q_mbuf) = IX_MBUF_PKT_LEN(&q->ixp_q_mbuf) = ++ ((IX_MBUF_MLEN(&q->ixp_q_mbuf) * 8) + 72 + 511) / 8; ++ tbuf = kmalloc(IX_MBUF_MLEN(&q->ixp_q_mbuf), SLAB_ATOMIC); ++ ++ if (IX_MBUF_MDATA(&q->ixp_q_mbuf) == NULL) { ++ printk("ixp: kmalloc(%u, SLAB_ATOMIC) failed\n", ++ IX_MBUF_MLEN(&q->ixp_q_mbuf)); ++ q->ixp_q_crp->crp_etype = ENOMEM; ++ goto done; ++ } ++ memcpy(tbuf, &(IX_MBUF_MDATA(&q->ixp_q_mbuf))[auth_off], auth_len); ++ ++ /* Set location in client buffer to copy hash into */ ++ q->ixp_hash_dest = ++ &(IX_MBUF_MDATA(&q->ixp_q_mbuf))[auth_off + auth_len]; ++ ++ IX_MBUF_MDATA(&q->ixp_q_mbuf) = tbuf; ++ ++ /* Set location in internal buffer for where hash starts */ ++ q->ixp_hash_src = &(IX_MBUF_MDATA(&q->ixp_q_mbuf))[auth_len]; ++ ++ crypt_func = "ixCryptoAccHashPerform"; ++ status = ixCryptoAccHashPerform(ixp->ixp_ctx.authCtx.authAlgo, ++ &q->ixp_q_mbuf, ixp_hash_perform_cb, 0, auth_len, auth_len, ++ &ixp->ixp_hash_key_id); ++ } ++ else { ++ crypt_func = "ixCryptoAccAuthCryptPerform"; ++ status = ixCryptoAccAuthCryptPerform(ixp->ixp_ctx_id, &q->ixp_q_mbuf, ++ NULL, auth_off, auth_len, crypt_off, crypt_len, icv_off, ++ q->ixp_q_iv); ++ } ++ ++ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) ++ return; ++ ++ if (IX_CRYPTO_ACC_STATUS_QUEUE_FULL == status) { ++ q->ixp_q_crp->crp_etype = ENOMEM; ++ goto done; ++ } ++ ++ printk("ixp: %s failed %u\n", crypt_func, status); ++ q->ixp_q_crp->crp_etype = EINVAL; ++ ++done: ++ crypto_done(q->ixp_q_crp); ++ kmem_cache_free(qcache, q); ++} ++ ++ ++/* ++ * because we cannot process the Q from the Register callback ++ * we do it here on a task Q. ++ */ ++ ++static void ++ixp_process_pending(void *arg) ++{ ++ struct ixp_data *ixp = arg; ++ struct ixp_q *q = NULL; ++ ++ dprintk("%s(%p)\n", __FUNCTION__, arg); ++ ++ if (!ixp) ++ return; ++ ++ while (!list_empty(&ixp->ixp_q)) { ++ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); ++ list_del(&q->ixp_q_list); ++ ixp_q_process(q); ++ } ++} ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++static void ++ixp_process_pending_wq(struct work_struct *work) ++{ ++ struct ixp_data *ixp = container_of(work, struct ixp_data, ixp_pending_work); ++ ixp_process_pending(ixp); ++} ++#endif ++ ++/* ++ * callback for when context registration is complete ++ */ ++ ++static void ++ixp_register_cb(UINT32 ctx_id, IX_MBUF *bufp, IxCryptoAccStatus status) ++{ ++ int i; ++ struct ixp_data *ixp; ++ struct ixp_q *q; ++ ++ dprintk("%s(%d, %p, %d)\n", __FUNCTION__, ctx_id, bufp, status); ++ ++ /* ++ * free any buffer passed in to this routine ++ */ ++ if (bufp) { ++ IX_MBUF_MLEN(bufp) = IX_MBUF_PKT_LEN(bufp) = 0; ++ kfree(IX_MBUF_MDATA(bufp)); ++ IX_MBUF_MDATA(bufp) = NULL; ++ } ++ ++ for (i = 0; i < ixp_sesnum; i++) { ++ ixp = ixp_sessions[i]; ++ if (ixp && ixp->ixp_ctx_id == ctx_id) ++ break; ++ } ++ if (i >= ixp_sesnum) { ++ printk("ixp: invalid context id %d\n", ctx_id); ++ return; ++ } ++ ++ if (IX_CRYPTO_ACC_STATUS_WAIT == status) { ++ /* this is normal to free the first of two buffers */ ++ dprintk("ixp: register not finished yet.\n"); ++ return; ++ } ++ ++ if (IX_CRYPTO_ACC_STATUS_SUCCESS != status) { ++ printk("ixp: register failed 0x%x\n", status); ++ while (!list_empty(&ixp->ixp_q)) { ++ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); ++ list_del(&q->ixp_q_list); ++ q->ixp_q_crp->crp_etype = EINVAL; ++ crypto_done(q->ixp_q_crp); ++ kmem_cache_free(qcache, q); ++ } ++ return; ++ } ++ ++ /* ++ * we are now registered, we cannot start processing the Q here ++ * or we get strange errors with AES (DES/3DES seem to be ok). ++ */ ++ ixp->ixp_registered = 1; ++ schedule_work(&ixp->ixp_pending_work); ++} ++ ++ ++/* ++ * callback for when data processing is complete ++ */ ++ ++static void ++ixp_perform_cb( ++ UINT32 ctx_id, ++ IX_MBUF *sbufp, ++ IX_MBUF *dbufp, ++ IxCryptoAccStatus status) ++{ ++ struct ixp_q *q; ++ ++ dprintk("%s(%d, %p, %p, 0x%x)\n", __FUNCTION__, ctx_id, sbufp, ++ dbufp, status); ++ ++ if (sbufp == NULL) { ++ printk("ixp: NULL sbuf in ixp_perform_cb\n"); ++ return; ++ } ++ ++ q = IX_MBUF_PRIV(sbufp); ++ if (q == NULL) { ++ printk("ixp: NULL priv in ixp_perform_cb\n"); ++ return; ++ } ++ ++ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { ++ printk("ixp: perform failed status=%d\n", status); ++ q->ixp_q_crp->crp_etype = EINVAL; ++ } ++ ++ crypto_done(q->ixp_q_crp); ++ kmem_cache_free(qcache, q); ++} ++ ++ ++/* ++ * registration is not callable at IRQ time, so we defer ++ * to a task queue, this routines completes the registration for us ++ * when the task queue runs ++ * ++ * Unfortunately this means we cannot tell OCF that the driver is blocked, ++ * we do that on the next request. ++ */ ++ ++static void ++ixp_registration(void *arg) ++{ ++ struct ixp_data *ixp = arg; ++ struct ixp_q *q = NULL; ++ IX_MBUF *pri = NULL, *sec = NULL; ++ int status = IX_CRYPTO_ACC_STATUS_SUCCESS; ++ ++ if (!ixp) { ++ printk("ixp: ixp_registration with no arg\n"); ++ return; ++ } ++ ++ if (ixp->ixp_ctx_id != -1) { ++ ixCryptoAccCtxUnregister(ixp->ixp_ctx_id); ++ ixp->ixp_ctx_id = -1; ++ } ++ ++ if (list_empty(&ixp->ixp_q)) { ++ printk("ixp: ixp_registration with no Q\n"); ++ return; ++ } ++ ++ /* ++ * setup the primary and secondary buffers ++ */ ++ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); ++ if (q->ixp_q_acrd) { ++ pri = &ixp->ixp_pri_mbuf; ++ sec = &ixp->ixp_sec_mbuf; ++ IX_MBUF_MLEN(pri) = IX_MBUF_PKT_LEN(pri) = 128; ++ IX_MBUF_MDATA(pri) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); ++ IX_MBUF_MLEN(sec) = IX_MBUF_PKT_LEN(sec) = 128; ++ IX_MBUF_MDATA(sec) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); ++ } ++ ++ /* Only need to register if a crypt op or HMAC op */ ++ if (!(ixp->ixp_auth_alg == CRYPTO_SHA1 || ++ ixp->ixp_auth_alg == CRYPTO_MD5)) { ++ status = ixCryptoAccCtxRegister( ++ &ixp->ixp_ctx, ++ pri, sec, ++ ixp_register_cb, ++ ixp_perform_cb, ++ &ixp->ixp_ctx_id); ++ } ++ else { ++ /* Otherwise we start processing pending q */ ++ schedule_work(&ixp->ixp_pending_work); ++ } ++ ++ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) ++ return; ++ ++ if (IX_CRYPTO_ACC_STATUS_EXCEED_MAX_TUNNELS == status) { ++ printk("ixp: ixCryptoAccCtxRegister failed (out of tunnels)\n"); ++ ixp_blocked = 1; ++ /* perhaps we should return EGAIN on queued ops ? */ ++ return; ++ } ++ ++ printk("ixp: ixCryptoAccCtxRegister failed %d\n", status); ++ ixp->ixp_ctx_id = -1; ++ ++ /* ++ * everything waiting is toasted ++ */ ++ while (!list_empty(&ixp->ixp_q)) { ++ q = list_entry(ixp->ixp_q.next, struct ixp_q, ixp_q_list); ++ list_del(&q->ixp_q_list); ++ q->ixp_q_crp->crp_etype = ENOENT; ++ crypto_done(q->ixp_q_crp); ++ kmem_cache_free(qcache, q); ++ } ++} ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++static void ++ixp_registration_wq(struct work_struct *work) ++{ ++ struct ixp_data *ixp = container_of(work, struct ixp_data, ++ ixp_registration_work); ++ ixp_registration(ixp); ++} ++#endif ++ ++/* ++ * Process a request. ++ */ ++static int ++ixp_process(device_t dev, struct cryptop *crp, int hint) ++{ ++ struct ixp_data *ixp; ++ unsigned int lid; ++ struct ixp_q *q = NULL; ++ int status; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ /* Sanity check */ ++ if (crp == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ crp->crp_etype = 0; ++ ++ if (ixp_blocked) ++ return ERESTART; ++ ++ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ crp->crp_etype = EINVAL; ++ goto done; ++ } ++ ++ /* ++ * find the session we are using ++ */ ++ ++ lid = crp->crp_sid & 0xffffffff; ++ if (lid >= ixp_sesnum || lid == 0 || ixp_sessions == NULL || ++ ixp_sessions[lid] == NULL) { ++ crp->crp_etype = ENOENT; ++ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); ++ goto done; ++ } ++ ixp = ixp_sessions[lid]; ++ ++ /* ++ * setup a new request ready for queuing ++ */ ++ q = kmem_cache_alloc(qcache, SLAB_ATOMIC); ++ if (q == NULL) { ++ dprintk("%s,%d: ENOMEM\n", __FILE__, __LINE__); ++ crp->crp_etype = ENOMEM; ++ goto done; ++ } ++ /* ++ * save some cycles by only zeroing the important bits ++ */ ++ memset(&q->ixp_q_mbuf, 0, sizeof(q->ixp_q_mbuf)); ++ q->ixp_q_ccrd = NULL; ++ q->ixp_q_acrd = NULL; ++ q->ixp_q_crp = crp; ++ q->ixp_q_data = ixp; ++ ++ /* ++ * point the cipher and auth descriptors appropriately ++ * check that we have something to do ++ */ ++ if (crp->crp_desc->crd_alg == ixp->ixp_cipher_alg) ++ q->ixp_q_ccrd = crp->crp_desc; ++ else if (crp->crp_desc->crd_alg == ixp->ixp_auth_alg) ++ q->ixp_q_acrd = crp->crp_desc; ++ else { ++ crp->crp_etype = ENOENT; ++ dprintk("%s,%d: bad desc match: ENOENT\n", __FILE__, __LINE__); ++ goto done; ++ } ++ if (crp->crp_desc->crd_next) { ++ if (crp->crp_desc->crd_next->crd_alg == ixp->ixp_cipher_alg) ++ q->ixp_q_ccrd = crp->crp_desc->crd_next; ++ else if (crp->crp_desc->crd_next->crd_alg == ixp->ixp_auth_alg) ++ q->ixp_q_acrd = crp->crp_desc->crd_next; ++ else { ++ crp->crp_etype = ENOENT; ++ dprintk("%s,%d: bad desc match: ENOENT\n", __FILE__, __LINE__); ++ goto done; ++ } ++ } ++ ++ /* ++ * If there is a direction change for this context then we mark it as ++ * unregistered and re-register is for the new direction. This is not ++ * a very expensive operation and currently only tends to happen when ++ * user-space application are doing benchmarks ++ * ++ * DM - we should be checking for pending requests before unregistering. ++ */ ++ if (q->ixp_q_ccrd && ixp->ixp_registered && ++ ixp->ixp_crd_flags != (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT)) { ++ dprintk("%s - detected direction change on session\n", __FUNCTION__); ++ ixp->ixp_registered = 0; ++ } ++ ++ /* ++ * if we are registered, call straight into the perform code ++ */ ++ if (ixp->ixp_registered) { ++ ixp_q_process(q); ++ return 0; ++ } ++ ++ /* ++ * the only part of the context not set in newsession is the direction ++ * dependent parts ++ */ ++ if (q->ixp_q_ccrd) { ++ ixp->ixp_crd_flags = (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT); ++ if (q->ixp_q_ccrd->crd_flags & CRD_F_ENCRYPT) { ++ ixp->ixp_ctx.operation = q->ixp_q_acrd ? ++ IX_CRYPTO_ACC_OP_ENCRYPT_AUTH : IX_CRYPTO_ACC_OP_ENCRYPT; ++ } else { ++ ixp->ixp_ctx.operation = q->ixp_q_acrd ? ++ IX_CRYPTO_ACC_OP_AUTH_DECRYPT : IX_CRYPTO_ACC_OP_DECRYPT; ++ } ++ } else { ++ /* q->ixp_q_acrd must be set if we are here */ ++ ixp->ixp_ctx.operation = IX_CRYPTO_ACC_OP_AUTH_CALC; ++ } ++ ++ status = list_empty(&ixp->ixp_q); ++ list_add_tail(&q->ixp_q_list, &ixp->ixp_q); ++ if (status) ++ schedule_work(&ixp->ixp_registration_work); ++ return 0; ++ ++done: ++ if (q) ++ kmem_cache_free(qcache, q); ++ crypto_done(crp); ++ return 0; ++} ++ ++ ++#ifdef __ixp46X ++/* ++ * key processing support for the ixp465 ++ */ ++ ++ ++/* ++ * copy a BN (LE) into a buffer (BE) an fill out the op appropriately ++ * assume zeroed and only copy bits that are significant ++ */ ++ ++static int ++ixp_copy_ibuf(struct crparam *p, IxCryptoAccPkeEauOperand *op, UINT32 *buf) ++{ ++ unsigned char *src = (unsigned char *) p->crp_p; ++ unsigned char *dst; ++ int len, bits = p->crp_nbits; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if (bits > MAX_IOP_SIZE * sizeof(UINT32) * 8) { ++ dprintk("%s - ibuf too big (%d > %d)\n", __FUNCTION__, ++ bits, MAX_IOP_SIZE * sizeof(UINT32) * 8); ++ return -1; ++ } ++ ++ len = (bits + 31) / 32; /* the number UINT32's needed */ ++ ++ dst = (unsigned char *) &buf[len]; ++ dst--; ++ ++ while (bits > 0) { ++ *dst-- = *src++; ++ bits -= 8; ++ } ++ ++#if 0 /* no need to zero remaining bits as it is done during request alloc */ ++ while (dst > (unsigned char *) buf) ++ *dst-- = '\0'; ++#endif ++ ++ op->pData = buf; ++ op->dataLen = len; ++ return 0; ++} ++ ++/* ++ * copy out the result, be as forgiving as we can about small output buffers ++ */ ++ ++static int ++ixp_copy_obuf(struct crparam *p, IxCryptoAccPkeEauOpResult *op, UINT32 *buf) ++{ ++ unsigned char *dst = (unsigned char *) p->crp_p; ++ unsigned char *src = (unsigned char *) buf; ++ int len, z, bits = p->crp_nbits; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ len = op->dataLen * sizeof(UINT32); ++ ++ /* skip leading zeroes to be small buffer friendly */ ++ z = 0; ++ while (z < len && src[z] == '\0') ++ z++; ++ ++ src += len; ++ src--; ++ len -= z; ++ ++ while (len > 0 && bits > 0) { ++ *dst++ = *src--; ++ len--; ++ bits -= 8; ++ } ++ ++ while (bits > 0) { ++ *dst++ = '\0'; ++ bits -= 8; ++ } ++ ++ if (len > 0) { ++ dprintk("%s - obuf is %d (z=%d, ob=%d) bytes too small\n", ++ __FUNCTION__, len, z, p->crp_nbits / 8); ++ return -1; ++ } ++ ++ return 0; ++} ++ ++ ++/* ++ * the parameter offsets for exp_mod ++ */ ++ ++#define IXP_PARAM_BASE 0 ++#define IXP_PARAM_EXP 1 ++#define IXP_PARAM_MOD 2 ++#define IXP_PARAM_RES 3 ++ ++/* ++ * key processing complete callback, is also used to start processing ++ * by passing a NULL for pResult ++ */ ++ ++static void ++ixp_kperform_cb( ++ IxCryptoAccPkeEauOperation operation, ++ IxCryptoAccPkeEauOpResult *pResult, ++ BOOL carryOrBorrow, ++ IxCryptoAccStatus status) ++{ ++ struct ixp_pkq *q, *tmp; ++ unsigned long flags; ++ ++ dprintk("%s(0x%x, %p, %d, 0x%x)\n", __FUNCTION__, operation, pResult, ++ carryOrBorrow, status); ++ ++ /* handle a completed request */ ++ if (pResult) { ++ if (ixp_pk_cur && &ixp_pk_cur->pkq_result == pResult) { ++ q = ixp_pk_cur; ++ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { ++ dprintk("%s() - op failed 0x%x\n", __FUNCTION__, status); ++ q->pkq_krp->krp_status = ERANGE; /* could do better */ ++ } else { ++ /* copy out the result */ ++ if (ixp_copy_obuf(&q->pkq_krp->krp_param[IXP_PARAM_RES], ++ &q->pkq_result, q->pkq_obuf)) ++ q->pkq_krp->krp_status = ERANGE; ++ } ++ crypto_kdone(q->pkq_krp); ++ kfree(q); ++ ixp_pk_cur = NULL; ++ } else ++ printk("%s - callback with invalid result pointer\n", __FUNCTION__); ++ } ++ ++ spin_lock_irqsave(&ixp_pkq_lock, flags); ++ if (ixp_pk_cur || list_empty(&ixp_pkq)) { ++ spin_unlock_irqrestore(&ixp_pkq_lock, flags); ++ return; ++ } ++ ++ list_for_each_entry_safe(q, tmp, &ixp_pkq, pkq_list) { ++ ++ list_del(&q->pkq_list); ++ ixp_pk_cur = q; ++ ++ spin_unlock_irqrestore(&ixp_pkq_lock, flags); ++ ++ status = ixCryptoAccPkeEauPerform( ++ IX_CRYPTO_ACC_OP_EAU_MOD_EXP, ++ &q->pkq_op, ++ ixp_kperform_cb, ++ &q->pkq_result); ++ ++ if (status == IX_CRYPTO_ACC_STATUS_SUCCESS) { ++ dprintk("%s() - ixCryptoAccPkeEauPerform SUCCESS\n", __FUNCTION__); ++ return; /* callback will return here for callback */ ++ } else if (status == IX_CRYPTO_ACC_STATUS_RETRY) { ++ printk("%s() - ixCryptoAccPkeEauPerform RETRY\n", __FUNCTION__); ++ } else { ++ printk("%s() - ixCryptoAccPkeEauPerform failed %d\n", ++ __FUNCTION__, status); ++ } ++ q->pkq_krp->krp_status = ERANGE; /* could do better */ ++ crypto_kdone(q->pkq_krp); ++ kfree(q); ++ spin_lock_irqsave(&ixp_pkq_lock, flags); ++ } ++ spin_unlock_irqrestore(&ixp_pkq_lock, flags); ++} ++ ++ ++static int ++ixp_kprocess(device_t dev, struct cryptkop *krp, int hint) ++{ ++ struct ixp_pkq *q; ++ int rc = 0; ++ unsigned long flags; ++ ++ dprintk("%s l1=%d l2=%d l3=%d l4=%d\n", __FUNCTION__, ++ krp->krp_param[IXP_PARAM_BASE].crp_nbits, ++ krp->krp_param[IXP_PARAM_EXP].crp_nbits, ++ krp->krp_param[IXP_PARAM_MOD].crp_nbits, ++ krp->krp_param[IXP_PARAM_RES].crp_nbits); ++ ++ ++ if (krp->krp_op != CRK_MOD_EXP) { ++ krp->krp_status = EOPNOTSUPP; ++ goto err; ++ } ++ ++ q = (struct ixp_pkq *) kmalloc(sizeof(*q), GFP_KERNEL); ++ if (q == NULL) { ++ krp->krp_status = ENOMEM; ++ goto err; ++ } ++ ++ /* ++ * The PKE engine does not appear to zero the output buffer ++ * appropriately, so we need to do it all here. ++ */ ++ memset(q, 0, sizeof(*q)); ++ ++ q->pkq_krp = krp; ++ INIT_LIST_HEAD(&q->pkq_list); ++ ++ if (ixp_copy_ibuf(&krp->krp_param[IXP_PARAM_BASE], &q->pkq_op.modExpOpr.M, ++ q->pkq_ibuf0)) ++ rc = 1; ++ if (!rc && ixp_copy_ibuf(&krp->krp_param[IXP_PARAM_EXP], ++ &q->pkq_op.modExpOpr.e, q->pkq_ibuf1)) ++ rc = 2; ++ if (!rc && ixp_copy_ibuf(&krp->krp_param[IXP_PARAM_MOD], ++ &q->pkq_op.modExpOpr.N, q->pkq_ibuf2)) ++ rc = 3; ++ ++ if (rc) { ++ kfree(q); ++ krp->krp_status = ERANGE; ++ goto err; ++ } ++ ++ q->pkq_result.pData = q->pkq_obuf; ++ q->pkq_result.dataLen = ++ (krp->krp_param[IXP_PARAM_RES].crp_nbits + 31) / 32; ++ ++ spin_lock_irqsave(&ixp_pkq_lock, flags); ++ list_add_tail(&q->pkq_list, &ixp_pkq); ++ spin_unlock_irqrestore(&ixp_pkq_lock, flags); ++ ++ if (!ixp_pk_cur) ++ ixp_kperform_cb(0, NULL, 0, 0); ++ return (0); ++ ++err: ++ crypto_kdone(krp); ++ return (0); ++} ++ ++ ++ ++#ifdef CONFIG_OCF_RANDOMHARVEST ++/* ++ * We run the random number generator output through SHA so that it ++ * is FIPS compliant. ++ */ ++ ++static volatile int sha_done = 0; ++static unsigned char sha_digest[20]; ++ ++static void ++ixp_hash_cb(UINT8 *digest, IxCryptoAccStatus status) ++{ ++ dprintk("%s(%p, %d)\n", __FUNCTION__, digest, status); ++ if (sha_digest != digest) ++ printk("digest error\n"); ++ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) ++ sha_done = 1; ++ else ++ sha_done = -status; ++} ++ ++static int ++ixp_read_random(void *arg, u_int32_t *buf, int maxwords) ++{ ++ IxCryptoAccStatus status; ++ int i, n, rc; ++ ++ dprintk("%s(%p, %d)\n", __FUNCTION__, buf, maxwords); ++ memset(buf, 0, maxwords * sizeof(*buf)); ++ status = ixCryptoAccPkePseudoRandomNumberGet(maxwords, buf); ++ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { ++ dprintk("%s: ixCryptoAccPkePseudoRandomNumberGet failed %d\n", ++ __FUNCTION__, status); ++ return 0; ++ } ++ ++ /* ++ * run the random data through SHA to make it look more random ++ */ ++ ++ n = sizeof(sha_digest); /* process digest bytes at a time */ ++ ++ rc = 0; ++ for (i = 0; i < maxwords; i += n / sizeof(*buf)) { ++ if ((maxwords - i) * sizeof(*buf) < n) ++ n = (maxwords - i) * sizeof(*buf); ++ sha_done = 0; ++ status = ixCryptoAccPkeHashPerform(IX_CRYPTO_ACC_AUTH_SHA1, ++ (UINT8 *) &buf[i], n, ixp_hash_cb, sha_digest); ++ if (status != IX_CRYPTO_ACC_STATUS_SUCCESS) { ++ dprintk("ixCryptoAccPkeHashPerform failed %d\n", status); ++ return -EIO; ++ } ++ while (!sha_done) ++ schedule(); ++ if (sha_done < 0) { ++ dprintk("ixCryptoAccPkeHashPerform failed CB %d\n", -sha_done); ++ return 0; ++ } ++ memcpy(&buf[i], sha_digest, n); ++ rc += n / sizeof(*buf);; ++ } ++ ++ return rc; ++} ++#endif /* CONFIG_OCF_RANDOMHARVEST */ ++ ++#endif /* __ixp46X */ ++ ++ ++ ++/* ++ * our driver startup and shutdown routines ++ */ ++ ++static int ++ixp_init(void) ++{ ++ dprintk("%s(%p)\n", __FUNCTION__, ixp_init); ++ ++ if (ixp_init_crypto && ixCryptoAccInit() != IX_CRYPTO_ACC_STATUS_SUCCESS) ++ printk("ixCryptoAccInit failed, assuming already initialised!\n"); ++ ++ qcache = kmem_cache_create("ixp4xx_q", sizeof(struct ixp_q), 0, ++ SLAB_HWCACHE_ALIGN, NULL ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) ++ , NULL ++#endif ++ ); ++ if (!qcache) { ++ printk("failed to create Qcache\n"); ++ return -ENOENT; ++ } ++ ++ memset(&ixpdev, 0, sizeof(ixpdev)); ++ softc_device_init(&ixpdev, "ixp4xx", 0, ixp_methods); ++ ++ ixp_id = crypto_get_driverid(softc_get_device(&ixpdev), ++ CRYPTOCAP_F_HARDWARE); ++ if (ixp_id < 0) ++ panic("IXP/OCF crypto device cannot initialize!"); ++ ++#define REGISTER(alg) \ ++ crypto_register(ixp_id,alg,0,0) ++ ++ REGISTER(CRYPTO_DES_CBC); ++ REGISTER(CRYPTO_3DES_CBC); ++ REGISTER(CRYPTO_RIJNDAEL128_CBC); ++#ifdef CONFIG_OCF_IXP4XX_SHA1_MD5 ++ REGISTER(CRYPTO_MD5); ++ REGISTER(CRYPTO_SHA1); ++#endif ++ REGISTER(CRYPTO_MD5_HMAC); ++ REGISTER(CRYPTO_SHA1_HMAC); ++#undef REGISTER ++ ++#ifdef __ixp46X ++ spin_lock_init(&ixp_pkq_lock); ++ /* ++ * we do not enable the go fast options here as they can potentially ++ * allow timing based attacks ++ * ++ * http://www.openssl.org/news/secadv_20030219.txt ++ */ ++ ixCryptoAccPkeEauExpConfig(0, 0); ++ crypto_kregister(ixp_id, CRK_MOD_EXP, 0); ++#ifdef CONFIG_OCF_RANDOMHARVEST ++ crypto_rregister(ixp_id, ixp_read_random, NULL); ++#endif ++#endif ++ ++ return 0; ++} ++ ++static void ++ixp_exit(void) ++{ ++ dprintk("%s()\n", __FUNCTION__); ++ crypto_unregister_all(ixp_id); ++ ixp_id = -1; ++ kmem_cache_destroy(qcache); ++ qcache = NULL; ++} ++ ++module_init(ixp_init); ++module_exit(ixp_exit); ++ ++MODULE_LICENSE("Dual BSD/GPL"); ++MODULE_AUTHOR("David McCullough "); ++MODULE_DESCRIPTION("ixp (OCF module for IXP4xx crypto)"); +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/Makefile linux-3.1.4/crypto/ocf/kirkwood/Makefile +--- linux-3.1.4.orig/crypto/ocf/kirkwood/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/Makefile 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,19 @@ ++# for SGlinux builds ++-include $(ROOTDIR)/modules/.config ++ ++obj-$(CONFIG_OCF_KIRKWOOD) += mv_cesa.o ++ ++mv_cesa-y := cesa/mvCesa.o cesa/mvLru.o cesa/mvMD5.o cesa/mvSHA1.o cesa/AES/mvAesAlg.o cesa/AES/mvAesApi.o cesa/mvCesaDebug.o cesa_ocf_drv.o ++ ++# Extra objects required by the CESA driver ++mv_cesa-y += mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.o mvHal/kw_family/boardEnv/mvBoardEnvLib.o mvHal/mv_hal/twsi/mvTwsi.o mvHal/kw_family/ctrlEnv/sys/mvCpuIf.o mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.o mvHal/kw_family/ctrlEnv/sys/mvSysDram.o mvHal/linux_oss/mvOs.o mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.o mvHal/mv_hal/gpp/mvGpp.o mvHal/kw_family/ctrlEnv/sys/mvSysPex.o mvHal/mv_hal/pex/mvPex.o mvHal/kw_family/boardEnv/mvBoardEnvSpec.o mvHal/common/mvCommon.o mvHal/common/mvDebug.o mvHal/kw_family/ctrlEnv/sys/mvSysCesa.o ++ ++ifdef src ++EXTRA_CFLAGS += -I$(src)/.. -I$(src)/cesa -I$(src)/mvHal -I$(src)/mvHal/common -I$(src)/mvHal/kw_family -I$(src)/mvHal/mv_hal -I$(src)/mvHal/linux_oss -I$(src) ++endif ++ ++EXTRA_CFLAGS += -DMV_LINUX -DMV_CPU_LE -DMV_ARM -DMV_INCLUDE_CESA -DMV_INCLUDE_PEX -DMV_CACHE_COHERENCY=3 ++ifdef TOPDIR ++-include $(TOPDIR)/Rules.make ++endif ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/cesa/AES/mvAes.h linux-3.1.4/crypto/ocf/kirkwood/cesa/AES/mvAes.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/cesa/AES/mvAes.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/cesa/AES/mvAes.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,62 @@ ++/* mvAes.h v2.0 August '99 ++ * Reference ANSI C code ++ */ ++ ++/* AES Cipher header file for ANSI C Submissions ++ Lawrence E. Bassham III ++ Computer Security Division ++ National Institute of Standards and Technology ++ ++ April 15, 1998 ++ ++ This sample is to assist implementers developing to the Cryptographic ++API Profile for AES Candidate Algorithm Submissions. Please consult this ++document as a cross-reference. ++ ++ ANY CHANGES, WHERE APPROPRIATE, TO INFORMATION PROVIDED IN THIS FILE ++MUST BE DOCUMENTED. CHANGES ARE ONLY APPROPRIATE WHERE SPECIFIED WITH ++THE STRING "CHANGE POSSIBLE". FUNCTION CALLS AND THEIR PARAMETERS CANNOT ++BE CHANGED. STRUCTURES CAN BE ALTERED TO ALLOW IMPLEMENTERS TO INCLUDE ++IMPLEMENTATION SPECIFIC INFORMATION. ++*/ ++ ++/* Includes: ++ Standard include files ++*/ ++ ++#include "mvOs.h" ++ ++ ++/* Error Codes - CHANGE POSSIBLE: inclusion of additional error codes */ ++ ++/* Key direction is invalid, e.g., unknown value */ ++#define AES_BAD_KEY_DIR -1 ++ ++/* Key material not of correct length */ ++#define AES_BAD_KEY_MAT -2 ++ ++/* Key passed is not valid */ ++#define AES_BAD_KEY_INSTANCE -3 ++ ++/* Params struct passed to cipherInit invalid */ ++#define AES_BAD_CIPHER_MODE -4 ++ ++/* Cipher in wrong state (e.g., not initialized) */ ++#define AES_BAD_CIPHER_STATE -5 ++ ++#define AES_BAD_CIPHER_INSTANCE -7 ++ ++ ++/* Function protoypes */ ++/* CHANGED: makeKey(): parameter blockLen added ++ this parameter is absolutely necessary if you want to ++ setup the round keys in a variable block length setting ++ cipherInit(): parameter blockLen added (for obvious reasons) ++ */ ++int aesMakeKey(MV_U8 *expandedKey, MV_U8 *keyMaterial, int keyLen, int blockLen); ++int aesBlockEncrypt128(MV_U8 mode, MV_U8 *IV, MV_U8 *expandedKey, int keyLen, ++ MV_U32 *plain, int numBlocks, MV_U32 *cipher); ++int aesBlockDecrypt128(MV_U8 mode, MV_U8 *IV, MV_U8 *expandedKey, int keyLen, ++ MV_U32 *plain, int numBlocks, MV_U32 *cipher); ++ ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.c linux-3.1.4/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.c +--- linux-3.1.4.orig/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,317 @@ ++/* rijndael-alg-ref.c v2.0 August '99 ++ * Reference ANSI C code ++ * authors: Paulo Barreto ++ * Vincent Rijmen, K.U.Leuven ++ * ++ * This code is placed in the public domain. ++ */ ++ ++#include "mvOs.h" ++ ++#include "mvAesAlg.h" ++ ++#include "mvAesBoxes.dat" ++ ++ ++MV_U8 mul1(MV_U8 aa, MV_U8 bb); ++void KeyAddition(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC], MV_U8 BC); ++void ShiftRow128Enc(MV_U8 a[4][MAXBC]); ++void ShiftRow128Dec(MV_U8 a[4][MAXBC]); ++void Substitution(MV_U8 a[4][MAXBC], MV_U8 box[256]); ++void MixColumn(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC]); ++void InvMixColumn(MV_U8 a[4][MAXBC]); ++ ++ ++#define mul(aa, bb) (mask[bb] & Alogtable[aa + Logtable[bb]]) ++ ++MV_U8 mul1(MV_U8 aa, MV_U8 bb) ++{ ++ return mask[bb] & Alogtable[aa + Logtable[bb]]; ++} ++ ++ ++void KeyAddition(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC], MV_U8 BC) ++{ ++ /* Exor corresponding text input and round key input bytes ++ */ ++ ((MV_U32*)(&(a[0][0])))[0] ^= ((MV_U32*)(&(rk[0][0])))[0]; ++ ((MV_U32*)(&(a[1][0])))[0] ^= ((MV_U32*)(&(rk[1][0])))[0]; ++ ((MV_U32*)(&(a[2][0])))[0] ^= ((MV_U32*)(&(rk[2][0])))[0]; ++ ((MV_U32*)(&(a[3][0])))[0] ^= ((MV_U32*)(&(rk[3][0])))[0]; ++ ++} ++ ++void ShiftRow128Enc(MV_U8 a[4][MAXBC]) { ++ /* Row 0 remains unchanged ++ * The other three rows are shifted a variable amount ++ */ ++ MV_U8 tmp[MAXBC]; ++ ++ tmp[0] = a[1][1]; ++ tmp[1] = a[1][2]; ++ tmp[2] = a[1][3]; ++ tmp[3] = a[1][0]; ++ ++ ((MV_U32*)(&(a[1][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; ++ /* ++ a[1][0] = tmp[0]; ++ a[1][1] = tmp[1]; ++ a[1][2] = tmp[2]; ++ a[1][3] = tmp[3]; ++ */ ++ tmp[0] = a[2][2]; ++ tmp[1] = a[2][3]; ++ tmp[2] = a[2][0]; ++ tmp[3] = a[2][1]; ++ ++ ((MV_U32*)(&(a[2][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; ++ /* ++ a[2][0] = tmp[0]; ++ a[2][1] = tmp[1]; ++ a[2][2] = tmp[2]; ++ a[2][3] = tmp[3]; ++ */ ++ tmp[0] = a[3][3]; ++ tmp[1] = a[3][0]; ++ tmp[2] = a[3][1]; ++ tmp[3] = a[3][2]; ++ ++ ((MV_U32*)(&(a[3][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; ++ /* ++ a[3][0] = tmp[0]; ++ a[3][1] = tmp[1]; ++ a[3][2] = tmp[2]; ++ a[3][3] = tmp[3]; ++ */ ++} ++ ++void ShiftRow128Dec(MV_U8 a[4][MAXBC]) { ++ /* Row 0 remains unchanged ++ * The other three rows are shifted a variable amount ++ */ ++ MV_U8 tmp[MAXBC]; ++ ++ tmp[0] = a[1][3]; ++ tmp[1] = a[1][0]; ++ tmp[2] = a[1][1]; ++ tmp[3] = a[1][2]; ++ ++ ((MV_U32*)(&(a[1][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; ++ /* ++ a[1][0] = tmp[0]; ++ a[1][1] = tmp[1]; ++ a[1][2] = tmp[2]; ++ a[1][3] = tmp[3]; ++ */ ++ ++ tmp[0] = a[2][2]; ++ tmp[1] = a[2][3]; ++ tmp[2] = a[2][0]; ++ tmp[3] = a[2][1]; ++ ++ ((MV_U32*)(&(a[2][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; ++ /* ++ a[2][0] = tmp[0]; ++ a[2][1] = tmp[1]; ++ a[2][2] = tmp[2]; ++ a[2][3] = tmp[3]; ++ */ ++ ++ tmp[0] = a[3][1]; ++ tmp[1] = a[3][2]; ++ tmp[2] = a[3][3]; ++ tmp[3] = a[3][0]; ++ ++ ((MV_U32*)(&(a[3][0])))[0] = ((MV_U32*)(&(tmp[0])))[0]; ++ /* ++ a[3][0] = tmp[0]; ++ a[3][1] = tmp[1]; ++ a[3][2] = tmp[2]; ++ a[3][3] = tmp[3]; ++ */ ++} ++ ++void Substitution(MV_U8 a[4][MAXBC], MV_U8 box[256]) { ++ /* Replace every byte of the input by the byte at that place ++ * in the nonlinear S-box ++ */ ++ int i, j; ++ ++ for(i = 0; i < 4; i++) ++ for(j = 0; j < 4; j++) a[i][j] = box[a[i][j]] ; ++} ++ ++void MixColumn(MV_U8 a[4][MAXBC], MV_U8 rk[4][MAXBC]) { ++ /* Mix the four bytes of every column in a linear way ++ */ ++ MV_U8 b[4][MAXBC]; ++ int i, j; ++ ++ for(j = 0; j < 4; j++){ ++ b[0][j] = mul(25,a[0][j]) ^ mul(1,a[1][j]) ^ a[2][j] ^ a[3][j]; ++ b[1][j] = mul(25,a[1][j]) ^ mul(1,a[2][j]) ^ a[3][j] ^ a[0][j]; ++ b[2][j] = mul(25,a[2][j]) ^ mul(1,a[3][j]) ^ a[0][j] ^ a[1][j]; ++ b[3][j] = mul(25,a[3][j]) ^ mul(1,a[0][j]) ^ a[1][j] ^ a[2][j]; ++ } ++ for(i = 0; i < 4; i++) ++ /*for(j = 0; j < BC; j++) a[i][j] = b[i][j];*/ ++ ((MV_U32*)(&(a[i][0])))[0] = ((MV_U32*)(&(b[i][0])))[0] ^ ((MV_U32*)(&(rk[i][0])))[0];; ++} ++ ++void InvMixColumn(MV_U8 a[4][MAXBC]) { ++ /* Mix the four bytes of every column in a linear way ++ * This is the opposite operation of Mixcolumn ++ */ ++ MV_U8 b[4][MAXBC]; ++ int i, j; ++ ++ for(j = 0; j < 4; j++){ ++ b[0][j] = mul(223,a[0][j]) ^ mul(104,a[1][j]) ^ mul(238,a[2][j]) ^ mul(199,a[3][j]); ++ b[1][j] = mul(223,a[1][j]) ^ mul(104,a[2][j]) ^ mul(238,a[3][j]) ^ mul(199,a[0][j]); ++ b[2][j] = mul(223,a[2][j]) ^ mul(104,a[3][j]) ^ mul(238,a[0][j]) ^ mul(199,a[1][j]); ++ b[3][j] = mul(223,a[3][j]) ^ mul(104,a[0][j]) ^ mul(238,a[1][j]) ^ mul(199,a[2][j]); ++ } ++ for(i = 0; i < 4; i++) ++ /*for(j = 0; j < BC; j++) a[i][j] = b[i][j];*/ ++ ((MV_U32*)(&(a[i][0])))[0] = ((MV_U32*)(&(b[i][0])))[0]; ++} ++ ++int rijndaelKeySched (MV_U8 k[4][MAXKC], int keyBits, int blockBits, MV_U8 W[MAXROUNDS+1][4][MAXBC]) ++{ ++ /* Calculate the necessary round keys ++ * The number of calculations depends on keyBits and blockBits ++ */ ++ int KC, BC, ROUNDS; ++ int i, j, t, rconpointer = 0; ++ MV_U8 tk[4][MAXKC]; ++ ++ switch (keyBits) { ++ case 128: KC = 4; break; ++ case 192: KC = 6; break; ++ case 256: KC = 8; break; ++ default : return (-1); ++ } ++ ++ switch (blockBits) { ++ case 128: BC = 4; break; ++ case 192: BC = 6; break; ++ case 256: BC = 8; break; ++ default : return (-2); ++ } ++ ++ switch (keyBits >= blockBits ? keyBits : blockBits) { ++ case 128: ROUNDS = 10; break; ++ case 192: ROUNDS = 12; break; ++ case 256: ROUNDS = 14; break; ++ default : return (-3); /* this cannot happen */ ++ } ++ ++ ++ for(j = 0; j < KC; j++) ++ for(i = 0; i < 4; i++) ++ tk[i][j] = k[i][j]; ++ t = 0; ++ /* copy values into round key array */ ++ for(j = 0; (j < KC) && (t < (ROUNDS+1)*BC); j++, t++) ++ for(i = 0; i < 4; i++) W[t / BC][i][t % BC] = tk[i][j]; ++ ++ while (t < (ROUNDS+1)*BC) { /* while not enough round key material calculated */ ++ /* calculate new values */ ++ for(i = 0; i < 4; i++) ++ tk[i][0] ^= S[tk[(i+1)%4][KC-1]]; ++ tk[0][0] ^= rcon[rconpointer++]; ++ ++ if (KC != 8) ++ for(j = 1; j < KC; j++) ++ for(i = 0; i < 4; i++) tk[i][j] ^= tk[i][j-1]; ++ else { ++ for(j = 1; j < KC/2; j++) ++ for(i = 0; i < 4; i++) tk[i][j] ^= tk[i][j-1]; ++ for(i = 0; i < 4; i++) tk[i][KC/2] ^= S[tk[i][KC/2 - 1]]; ++ for(j = KC/2 + 1; j < KC; j++) ++ for(i = 0; i < 4; i++) tk[i][j] ^= tk[i][j-1]; ++ } ++ /* copy values into round key array */ ++ for(j = 0; (j < KC) && (t < (ROUNDS+1)*BC); j++, t++) ++ for(i = 0; i < 4; i++) W[t / BC][i][t % BC] = tk[i][j]; ++ } ++ ++ return 0; ++} ++ ++ ++ ++int rijndaelEncrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds) ++{ ++ /* Encryption of one block. ++ */ ++ int r, BC, ROUNDS; ++ ++ BC = 4; ++ ROUNDS = rounds; ++ ++ /* begin with a key addition ++ */ ++ ++ KeyAddition(a,rk[0],BC); ++ ++ /* ROUNDS-1 ordinary rounds ++ */ ++ for(r = 1; r < ROUNDS; r++) { ++ Substitution(a,S); ++ ShiftRow128Enc(a); ++ MixColumn(a, rk[r]); ++ /*KeyAddition(a,rk[r],BC);*/ ++ } ++ ++ /* Last round is special: there is no MixColumn ++ */ ++ Substitution(a,S); ++ ShiftRow128Enc(a); ++ KeyAddition(a,rk[ROUNDS],BC); ++ ++ return 0; ++} ++ ++ ++int rijndaelDecrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds) ++{ ++ int r, BC, ROUNDS; ++ ++ BC = 4; ++ ROUNDS = rounds; ++ ++ /* To decrypt: apply the inverse operations of the encrypt routine, ++ * in opposite order ++ * ++ * (KeyAddition is an involution: it 's equal to its inverse) ++ * (the inverse of Substitution with table S is Substitution with the inverse table of S) ++ * (the inverse of Shiftrow is Shiftrow over a suitable distance) ++ */ ++ ++ /* First the special round: ++ * without InvMixColumn ++ * with extra KeyAddition ++ */ ++ KeyAddition(a,rk[ROUNDS],BC); ++ ShiftRow128Dec(a); ++ Substitution(a,Si); ++ ++ /* ROUNDS-1 ordinary rounds ++ */ ++ for(r = ROUNDS-1; r > 0; r--) { ++ KeyAddition(a,rk[r],BC); ++ InvMixColumn(a); ++ ShiftRow128Dec(a); ++ Substitution(a,Si); ++ ++ } ++ ++ /* End with the extra key addition ++ */ ++ ++ KeyAddition(a,rk[0],BC); ++ ++ return 0; ++} ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.h linux-3.1.4/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/cesa/AES/mvAesAlg.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,19 @@ ++/* rijndael-alg-ref.h v2.0 August '99 ++ * Reference ANSI C code ++ * authors: Paulo Barreto ++ * Vincent Rijmen, K.U.Leuven ++ */ ++#ifndef __RIJNDAEL_ALG_H ++#define __RIJNDAEL_ALG_H ++ ++#define MAXBC (128/32) ++#define MAXKC (256/32) ++#define MAXROUNDS 14 ++ ++ ++int rijndaelKeySched (MV_U8 k[4][MAXKC], int keyBits, int blockBits, MV_U8 rk[MAXROUNDS+1][4][MAXBC]); ++ ++int rijndaelEncrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds); ++int rijndaelDecrypt128(MV_U8 a[4][MAXBC], MV_U8 rk[MAXROUNDS+1][4][MAXBC], int rounds); ++ ++#endif /* __RIJNDAEL_ALG_H */ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/cesa/AES/mvAesApi.c linux-3.1.4/crypto/ocf/kirkwood/cesa/AES/mvAesApi.c +--- linux-3.1.4.orig/crypto/ocf/kirkwood/cesa/AES/mvAesApi.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/cesa/AES/mvAesApi.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,312 @@ ++/* rijndael-api-ref.c v2.1 April 2000 ++ * Reference ANSI C code ++ * authors: v2.0 Paulo Barreto ++ * Vincent Rijmen, K.U.Leuven ++ * v2.1 Vincent Rijmen, K.U.Leuven ++ * ++ * This code is placed in the public domain. ++ */ ++#include "mvOs.h" ++ ++#include "mvAes.h" ++#include "mvAesAlg.h" ++ ++ ++/* Defines: ++ Add any additional defines you need ++*/ ++ ++#define MODE_ECB 1 /* Are we ciphering in ECB mode? */ ++#define MODE_CBC 2 /* Are we ciphering in CBC mode? */ ++#define MODE_CFB1 3 /* Are we ciphering in 1-bit CFB mode? */ ++ ++ ++int aesMakeKey(MV_U8 *expandedKey, MV_U8 *keyMaterial, int keyLen, int blockLen) ++{ ++ MV_U8 W[MAXROUNDS+1][4][MAXBC]; ++ MV_U8 k[4][MAXKC]; ++ MV_U8 j; ++ int i, rounds, KC; ++ ++ if (expandedKey == NULL) ++ { ++ return AES_BAD_KEY_INSTANCE; ++ } ++ ++ if (!((keyLen == 128) || (keyLen == 192) || (keyLen == 256))) ++ { ++ return AES_BAD_KEY_MAT; ++ } ++ ++ if (keyMaterial == NULL) ++ { ++ return AES_BAD_KEY_MAT; ++ } ++ ++ /* initialize key schedule: */ ++ for(i=0; i= 3) ++MV_U32 cesaChainLength = 0; ++int chainReqNum = 0; ++MV_U32 chainIndex = 0; ++MV_CESA_REQ* pNextActiveChain = 0; ++MV_CESA_REQ* pEndCurrChain = 0; ++MV_BOOL isFirstReq = MV_TRUE; ++#endif ++ ++static INLINE MV_U8* mvCesaSramAddrGet(void) ++{ ++#ifdef MV_CESA_NO_SRAM ++ return (MV_U8*)cesaSramVirtPtr; ++#else ++ return (MV_U8*)cesaCryptEngBase; ++#endif /* MV_CESA_NO_SRAM */ ++} ++ ++static INLINE MV_ULONG mvCesaSramVirtToPhys(void* pDev, MV_U8* pSramVirt) ++{ ++#ifdef MV_CESA_NO_SRAM ++ return (MV_ULONG)mvOsIoVirtToPhy(NULL, pSramVirt); ++#else ++ return (MV_ULONG)pSramVirt; ++#endif /* MV_CESA_NO_SRAM */ ++} ++ ++/* Internal Function prototypes */ ++ ++static INLINE void mvCesaSramDescrBuild(MV_U32 config, int frag, ++ int cryptoOffset, int ivOffset, int cryptoLength, ++ int macOffset, int digestOffset, int macLength, int macTotalLen, ++ MV_CESA_REQ *pCesaReq, MV_DMA_DESC* pDmaDesc); ++ ++static INLINE void mvCesaSramSaUpdate(short sid, MV_DMA_DESC *pDmaDesc); ++ ++static INLINE int mvCesaDmaCopyPrepare(MV_CESA_MBUF* pMbuf, MV_U8* pSramBuf, ++ MV_DMA_DESC* pDmaDesc, MV_BOOL isToMbuf, ++ int offset, int copySize, MV_BOOL skipFlush); ++ ++static void mvCesaHmacIvGet(MV_CESA_MAC_MODE macMode, unsigned char key[], int keyLength, ++ unsigned char innerIV[], unsigned char outerIV[]); ++ ++static MV_STATUS mvCesaFragAuthComplete(MV_CESA_REQ* pReq, MV_CESA_SA* pSA, ++ int macDataSize); ++ ++static MV_CESA_COMMAND* mvCesaCtrModeInit(void); ++ ++static MV_STATUS mvCesaCtrModePrepare(MV_CESA_COMMAND *pCtrModeCmd, MV_CESA_COMMAND *pCmd); ++static MV_STATUS mvCesaCtrModeComplete(MV_CESA_COMMAND *pOrgCmd, MV_CESA_COMMAND *pCmd); ++static void mvCesaCtrModeFinish(MV_CESA_COMMAND *pCmd); ++ ++static INLINE MV_STATUS mvCesaReqProcess(MV_CESA_REQ* pReq); ++static MV_STATUS mvCesaFragReqProcess(MV_CESA_REQ* pReq, MV_U8 frag); ++ ++static INLINE MV_STATUS mvCesaParamCheck(MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, MV_U8* pFixOffset); ++static INLINE MV_STATUS mvCesaFragParamCheck(MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd); ++ ++static INLINE void mvCesaFragSizeFind(MV_CESA_SA* pSA, MV_CESA_REQ* pReq, ++ int cryptoOffset, int macOffset, ++ int* pCopySize, int* pCryptoDataSize, int* pMacDataSize); ++static MV_STATUS mvCesaMbufCacheUnmap(MV_CESA_MBUF* pMbuf, int offset, int size); ++ ++ ++/* Go to the next request in the request queue */ ++static INLINE MV_CESA_REQ* MV_CESA_REQ_NEXT_PTR(MV_CESA_REQ* pReq) ++{ ++ if(pReq == pCesaReqLast) ++ return pCesaReqFirst; ++ ++ return pReq+1; ++} ++ ++#if (MV_CESA_VERSION >= 3) ++/* Go to the previous request in the request queue */ ++static INLINE MV_CESA_REQ* MV_CESA_REQ_PREV_PTR(MV_CESA_REQ* pReq) ++{ ++ if(pReq == pCesaReqFirst) ++ return pCesaReqLast; ++ ++ return pReq-1; ++} ++ ++#endif ++ ++ ++static INLINE void mvCesaReqProcessStart(MV_CESA_REQ* pReq) ++{ ++ int frag; ++ ++#if (MV_CESA_VERSION >= 3) ++ pReq->state = MV_CESA_CHAIN; ++#else ++ pReq->state = MV_CESA_PROCESS; ++#endif ++ cesaStats.startCount++; ++ ++ if(pReq->fragMode == MV_CESA_FRAG_NONE) ++ { ++ frag = 0; ++ } ++ else ++ { ++ frag = pReq->frags.nextFrag; ++ pReq->frags.nextFrag++; ++ } ++#if (MV_CESA_VERSION >= 2) ++ /* Enable TDMA engine */ ++ MV_REG_WRITE(MV_CESA_TDMA_CURR_DESC_PTR_REG, 0); ++ MV_REG_WRITE(MV_CESA_TDMA_NEXT_DESC_PTR_REG, ++ (MV_U32)mvCesaVirtToPhys(&pReq->dmaDescBuf, pReq->dma[frag].pDmaFirst)); ++#else ++ /* Enable IDMA engine */ ++ MV_REG_WRITE(IDMA_CURR_DESC_PTR_REG(0), 0); ++ MV_REG_WRITE(IDMA_NEXT_DESC_PTR_REG(0), ++ (MV_U32)mvCesaVirtToPhys(&pReq->dmaDescBuf, pReq->dma[frag].pDmaFirst)); ++#endif /* MV_CESA_VERSION >= 2 */ ++ ++#if defined(MV_BRIDGE_SYNC_REORDER) ++ mvOsBridgeReorderWA(); ++#endif ++ ++ /* Start Accelerator */ ++ MV_REG_WRITE(MV_CESA_CMD_REG, MV_CESA_CMD_CHAN_ENABLE_MASK); ++} ++ ++ ++/******************************************************************************* ++* mvCesaHalInit - Initialize the CESA driver ++* ++* DESCRIPTION: ++* This function initialize the CESA driver. ++* 1) Session database ++* 2) Request queue ++* 4) DMA descriptor lists - one list per request. Each list ++* has MV_CESA_MAX_DMA_DESC descriptors. ++* ++* INPUT: ++* numOfSession - maximum number of supported sessions ++* queueDepth - number of elements in the request queue. ++* pSramBase - virtual address of Sram ++* osHandle - A handle used by the OS to allocate memory for the ++* module (Passed to the OS Services layer) ++* ++* RETURN: ++* MV_OK - Success ++* MV_NO_RESOURCE - Fail, can't allocate resources: ++* Session database, request queue, ++* DMA descriptors list, LRU cache database. ++* MV_NOT_ALIGNED - Sram base address is not 8 byte aligned. ++* ++*******************************************************************************/ ++MV_STATUS mvCesaHalInit (int numOfSession, int queueDepth, char* pSramBase, MV_U32 cryptEngBase, ++ void *osHandle) ++{ ++ int i, req; ++ MV_U32 descOffsetReg, configReg; ++ MV_CESA_SRAM_SA *pSramSA; ++ ++ ++ mvOsPrintf("mvCesaInit: sessions=%d, queue=%d, pSram=%p\n", ++ numOfSession, queueDepth, pSramBase); ++ ++ cesaOsHandle = osHandle; ++ /* Create Session database */ ++ pCesaSAD = mvOsMalloc(sizeof(MV_CESA_SA)*numOfSession); ++ if(pCesaSAD == NULL) ++ { ++ mvOsPrintf("mvCesaInit: Can't allocate %u bytes for %d SAs\n", ++ sizeof(MV_CESA_SA)*numOfSession, numOfSession); ++ mvCesaFinish(); ++ return MV_NO_RESOURCE; ++ } ++ memset(pCesaSAD, 0, sizeof(MV_CESA_SA)*numOfSession); ++ cesaMaxSA = numOfSession; ++ ++ /* Allocate imag of sramSA in the DRAM */ ++ cesaSramSaBuf.bufSize = sizeof(MV_CESA_SRAM_SA)*numOfSession + ++ CPU_D_CACHE_LINE_SIZE; ++ ++ cesaSramSaBuf.bufVirtPtr = mvOsIoCachedMalloc(osHandle,cesaSramSaBuf.bufSize, ++ &cesaSramSaBuf.bufPhysAddr, ++ &cesaSramSaBuf.memHandle); ++ ++ if(cesaSramSaBuf.bufVirtPtr == NULL) ++ { ++ mvOsPrintf("mvCesaInit: Can't allocate %d bytes for sramSA structures\n", ++ cesaSramSaBuf.bufSize); ++ mvCesaFinish(); ++ return MV_NO_RESOURCE; ++ } ++ memset(cesaSramSaBuf.bufVirtPtr, 0, cesaSramSaBuf.bufSize); ++ pSramSA = (MV_CESA_SRAM_SA*)MV_ALIGN_UP((MV_ULONG)cesaSramSaBuf.bufVirtPtr, ++ CPU_D_CACHE_LINE_SIZE); ++ for(i=0; i= 3) ++ cesaChainLength = MAX_CESA_CHAIN_LENGTH; ++#endif ++ /* pSramBase must be 8 byte aligned */ ++ if( MV_IS_NOT_ALIGN((MV_ULONG)pSramBase, 8) ) ++ { ++ mvOsPrintf("mvCesaInit: pSramBase (%p) must be 8 byte aligned\n", ++ pSramBase); ++ mvCesaFinish(); ++ return MV_NOT_ALIGNED; ++ } ++ cesaSramVirtPtr = (MV_CESA_SRAM_MAP*)pSramBase; ++ ++ cesaCryptEngBase = cryptEngBase; ++ ++ /*memset(cesaSramVirtPtr, 0, sizeof(MV_CESA_SRAM_MAP));*/ ++ ++ /* Clear registers */ ++ MV_REG_WRITE( MV_CESA_CFG_REG, 0); ++ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); ++ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, 0); ++ ++ /* Initialize DMA descriptor lists for all requests in Request queue */ ++ descOffsetReg = configReg = 0; ++ for(req=0; reqcesaDescBuf.bufSize = sizeof(MV_CESA_DESC)*MV_CESA_MAX_REQ_FRAGS + ++ CPU_D_CACHE_LINE_SIZE; ++ ++ pReq->cesaDescBuf.bufVirtPtr = ++ mvOsIoCachedMalloc(osHandle,pReq->cesaDescBuf.bufSize, ++ &pReq->cesaDescBuf.bufPhysAddr, ++ &pReq->cesaDescBuf.memHandle); ++ ++ if(pReq->cesaDescBuf.bufVirtPtr == NULL) ++ { ++ mvOsPrintf("mvCesaInit: req=%d, Can't allocate %d bytes for CESA descriptors\n", ++ req, pReq->cesaDescBuf.bufSize); ++ mvCesaFinish(); ++ return MV_NO_RESOURCE; ++ } ++ memset(pReq->cesaDescBuf.bufVirtPtr, 0, pReq->cesaDescBuf.bufSize); ++ pReq->pCesaDesc = (MV_CESA_DESC*)MV_ALIGN_UP((MV_ULONG)pReq->cesaDescBuf.bufVirtPtr, ++ CPU_D_CACHE_LINE_SIZE); ++ ++ pReq->dmaDescBuf.bufSize = sizeof(MV_DMA_DESC)*MV_CESA_MAX_DMA_DESC*MV_CESA_MAX_REQ_FRAGS + ++ CPU_D_CACHE_LINE_SIZE; ++ ++ pReq->dmaDescBuf.bufVirtPtr = ++ mvOsIoCachedMalloc(osHandle,pReq->dmaDescBuf.bufSize, ++ &pReq->dmaDescBuf.bufPhysAddr, ++ &pReq->dmaDescBuf.memHandle); ++ ++ if(pReq->dmaDescBuf.bufVirtPtr == NULL) ++ { ++ mvOsPrintf("mvCesaInit: req=%d, Can't allocate %d bytes for DMA descriptor list\n", ++ req, pReq->dmaDescBuf.bufSize); ++ mvCesaFinish(); ++ return MV_NO_RESOURCE; ++ } ++ memset(pReq->dmaDescBuf.bufVirtPtr, 0, pReq->dmaDescBuf.bufSize); ++ pDmaDesc = (MV_DMA_DESC*)MV_ALIGN_UP((MV_ULONG)pReq->dmaDescBuf.bufVirtPtr, ++ CPU_D_CACHE_LINE_SIZE); ++ ++ for(frag=0; fragdma[frag]; ++ ++ pDma->pDmaFirst = pDmaDesc; ++ pDma->pDmaLast = NULL; ++ ++ for(i=0; ipDmaFirst[i].phyNextDescPtr = ++ MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, &pDmaDesc[i+1])); ++ } ++ pDma->pDmaFirst[i].phyNextDescPtr = 0; ++ mvOsCacheFlush(NULL, &pDma->pDmaFirst[0], MV_CESA_MAX_DMA_DESC*sizeof(MV_DMA_DESC)); ++ ++ pDmaDesc += MV_CESA_MAX_DMA_DESC; ++ } ++ } ++ /*mvCesaCryptoIvSet(NULL, MV_CESA_MAX_IV_LENGTH);*/ ++ descOffsetReg = (MV_U16)((MV_U8*)&cesaSramVirtPtr->desc - mvCesaSramAddrGet()); ++ MV_REG_WRITE(MV_CESA_CHAN_DESC_OFFSET_REG, descOffsetReg); ++ ++ configReg |= (MV_CESA_CFG_WAIT_DMA_MASK | MV_CESA_CFG_ACT_DMA_MASK); ++#if (MV_CESA_VERSION >= 3) ++ configReg |= MV_CESA_CFG_CHAIN_MODE_MASK; ++#endif ++ ++#if (MV_CESA_VERSION >= 2) ++ /* Initialize TDMA engine */ ++ MV_REG_WRITE(MV_CESA_TDMA_CTRL_REG, MV_CESA_TDMA_CTRL_VALUE); ++ MV_REG_WRITE(MV_CESA_TDMA_BYTE_COUNT_REG, 0); ++ MV_REG_WRITE(MV_CESA_TDMA_CURR_DESC_PTR_REG, 0); ++#else ++ /* Initialize IDMA #0 engine */ ++ MV_REG_WRITE(IDMA_CTRL_LOW_REG(0), 0); ++ MV_REG_WRITE(IDMA_BYTE_COUNT_REG(0), 0); ++ MV_REG_WRITE(IDMA_CURR_DESC_PTR_REG(0), 0); ++ MV_REG_WRITE(IDMA_CTRL_HIGH_REG(0), ICCHR_ENDIAN_LITTLE ++#ifdef MV_CPU_LE ++ | ICCHR_DESC_BYTE_SWAP_EN ++#endif ++ ); ++ /* Clear Cause Byte of IDMA channel to be used */ ++ MV_REG_WRITE( IDMA_CAUSE_REG, ~ICICR_CAUSE_MASK_ALL(0)); ++ MV_REG_WRITE(IDMA_CTRL_LOW_REG(0), MV_CESA_IDMA_CTRL_LOW_VALUE); ++#endif /* (MV_CESA_VERSION >= 2) */ ++ ++ /* Set CESA configuration registers */ ++ MV_REG_WRITE( MV_CESA_CFG_REG, configReg); ++ mvCesaDebugStatsClear(); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCesaFinish - Shutdown the CESA driver ++* ++* DESCRIPTION: ++* This function shutdown the CESA driver and free all allocted resources. ++* ++* INPUT: None ++* ++* RETURN: ++* MV_OK - Success ++* Other - Fail ++* ++*******************************************************************************/ ++MV_STATUS mvCesaFinish (void) ++{ ++ int req; ++ MV_CESA_REQ* pReq; ++ ++ mvOsPrintf("mvCesaFinish: \n"); ++ ++ cesaSramVirtPtr = NULL; ++ ++ /* Free all resources: DMA list, etc. */ ++ for(req=0; reqdmaDescBuf.bufVirtPtr != NULL) ++ { ++ mvOsIoCachedFree(cesaOsHandle,pReq->dmaDescBuf.bufSize, ++ pReq->dmaDescBuf.bufPhysAddr, ++ pReq->dmaDescBuf.bufVirtPtr, ++ pReq->dmaDescBuf.memHandle); ++ } ++ if(pReq->cesaDescBuf.bufVirtPtr != NULL) ++ { ++ mvOsIoCachedFree(cesaOsHandle,pReq->cesaDescBuf.bufSize, ++ pReq->cesaDescBuf.bufPhysAddr, ++ pReq->cesaDescBuf.bufVirtPtr, ++ pReq->cesaDescBuf.memHandle); ++ } ++ } ++#if (MV_CESA_VERSION < 2) ++ MV_REG_WRITE(IDMA_CTRL_LOW_REG(0), 0); ++#endif /* (MV_CESA_VERSION < 2) */ ++ ++ /* Free request queue */ ++ if(pCesaReqFirst != NULL) ++ { ++ mvOsFree(pCesaReqFirst); ++ pCesaReqFirst = pCesaReqLast = NULL; ++ pCesaReqEmpty = pCesaReqProcess = NULL; ++ cesaQueueDepth = cesaReqResources = 0; ++ } ++ /* Free SA database */ ++ if(pCesaSAD != NULL) ++ { ++ mvOsFree(pCesaSAD); ++ pCesaSAD = NULL; ++ cesaMaxSA = 0; ++ } ++ MV_REG_WRITE( MV_CESA_CFG_REG, 0); ++ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); ++ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, 0); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCesaCryptoIvSet - Set IV value for Crypto algorithm working in CBC mode ++* ++* DESCRIPTION: ++* This function set IV value using by Crypto algorithms in CBC mode. ++* Each channel has its own IV value. ++* This function gets IV value from the caller. If no IV value passed from ++* the caller or only part of IV passed, the function will init the rest part ++* of IV value (or the whole IV) by random value. ++* ++* INPUT: ++* MV_U8* pIV - Pointer to IV value supplied by user. If pIV==NULL ++* the function will generate random IV value. ++* int ivSize - size (in bytes) of IV provided by user. If ivSize is ++* smaller than maximum IV size, the function will complete ++* IV by random value. ++* ++* RETURN: ++* MV_OK - Success ++* Other - Fail ++* ++*******************************************************************************/ ++MV_STATUS mvCesaCryptoIvSet(MV_U8* pIV, int ivSize) ++{ ++ MV_U8* pSramIV; ++#if defined(MV646xx) ++ mvOsPrintf("mvCesaCryptoIvSet: ERR. shouldn't use this call on MV64660\n"); ++#endif ++ pSramIV = cesaSramVirtPtr->cryptoIV; ++ if(ivSize > MV_CESA_MAX_IV_LENGTH) ++ { ++ mvOsPrintf("mvCesaCryptoIvSet: ivSize (%d) is too large\n", ivSize); ++ ivSize = MV_CESA_MAX_IV_LENGTH; ++ } ++ if(pIV != NULL) ++ { ++ memcpy(pSramIV, pIV, ivSize); ++ ivSize = MV_CESA_MAX_IV_LENGTH - ivSize; ++ pSramIV += ivSize; ++ } ++ ++ while(ivSize > 0) ++ { ++ int size, mv_random = mvOsRand(); ++ ++ size = MV_MIN(ivSize, sizeof(mv_random)); ++ memcpy(pSramIV, (void*)&mv_random, size); ++ ++ pSramIV += size; ++ ivSize -= size; ++ } ++/* ++ mvOsCacheFlush(NULL, cesaSramVirtPtr->cryptoIV, ++ MV_CESA_MAX_IV_LENGTH); ++ mvOsCacheInvalidate(NULL, cesaSramVirtPtr->cryptoIV, ++ MV_CESA_MAX_IV_LENGTH); ++*/ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCesaSessionOpen - Open new uni-directional crypto session ++* ++* DESCRIPTION: ++* This function open new session. ++* ++* INPUT: ++* MV_CESA_OPEN_SESSION *pSession - pointer to new session input parameters ++* ++* OUTPUT: ++* short *pSid - session ID, should be used for all future ++* requests over this session. ++* ++* RETURN: ++* MV_OK - Session opend successfully. ++* MV_FULL - All sessions are in use, no free place in ++* SA database. ++* MV_BAD_PARAM - One of session input parameters is invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvCesaSessionOpen(MV_CESA_OPEN_SESSION *pSession, short* pSid) ++{ ++ short sid; ++ MV_U32 config = 0; ++ int digestSize; ++ ++ cesaStats.openedCount++; ++ ++ /* Find free entry in SAD */ ++ for(sid=0; sidoperation >= MV_CESA_MAX_OPERATION) ++ { ++ mvOsPrintf("mvCesaSessionOpen: Unexpected operation %d\n", ++ pSession->operation); ++ return MV_BAD_PARAM; ++ } ++ config |= (pSession->operation << MV_CESA_OPERATION_OFFSET); ++ ++ if( (pSession->direction != MV_CESA_DIR_ENCODE) && ++ (pSession->direction != MV_CESA_DIR_DECODE) ) ++ { ++ mvOsPrintf("mvCesaSessionOpen: Unexpected direction %d\n", ++ pSession->direction); ++ return MV_BAD_PARAM; ++ } ++ config |= (pSession->direction << MV_CESA_DIRECTION_BIT); ++ /* Clear SA entry */ ++ /* memset(&pCesaSAD[sid], 0, sizeof(pCesaSAD[sid])); */ ++ ++ /* Check AUTH parameters and update SA entry */ ++ if(pSession->operation != MV_CESA_CRYPTO_ONLY) ++ { ++ /* For HMAC (MD5 and SHA1) - Maximum Key size is 64 bytes */ ++ if( (pSession->macMode == MV_CESA_MAC_HMAC_MD5) || ++ (pSession->macMode == MV_CESA_MAC_HMAC_SHA1) ) ++ { ++ if(pSession->macKeyLength > MV_CESA_MAX_MAC_KEY_LENGTH) ++ { ++ mvOsPrintf("mvCesaSessionOpen: macKeyLength %d is too large\n", ++ pSession->macKeyLength); ++ return MV_BAD_PARAM; ++ } ++ mvCesaHmacIvGet(pSession->macMode, pSession->macKey, pSession->macKeyLength, ++ pCesaSAD[sid].pSramSA->macInnerIV, ++ pCesaSAD[sid].pSramSA->macOuterIV); ++ pCesaSAD[sid].macKeyLength = pSession->macKeyLength; ++ } ++ switch(pSession->macMode) ++ { ++ case MV_CESA_MAC_MD5: ++ case MV_CESA_MAC_HMAC_MD5: ++ digestSize = MV_CESA_MD5_DIGEST_SIZE; ++ break; ++ ++ case MV_CESA_MAC_SHA1: ++ case MV_CESA_MAC_HMAC_SHA1: ++ digestSize = MV_CESA_SHA1_DIGEST_SIZE; ++ break; ++ ++ default: ++ mvOsPrintf("mvCesaSessionOpen: Unexpected macMode %d\n", ++ pSession->macMode); ++ return MV_BAD_PARAM; ++ } ++ config |= (pSession->macMode << MV_CESA_MAC_MODE_OFFSET); ++ ++ /* Supported digest sizes: MD5 - 16 bytes (128 bits), */ ++ /* SHA1 - 20 bytes (160 bits) or 12 bytes (96 bits) for both */ ++ if( (pSession->digestSize != digestSize) && (pSession->digestSize != 12)) ++ { ++ mvOsPrintf("mvCesaSessionOpen: Unexpected digest size %d\n", ++ pSession->digestSize); ++ mvOsPrintf("\t Valid values [bytes]: MD5-16, SHA1-20, Both-12\n"); ++ return MV_BAD_PARAM; ++ } ++ pCesaSAD[sid].digestSize = pSession->digestSize; ++ ++ if(pCesaSAD[sid].digestSize == 12) ++ { ++ /* Set MV_CESA_MAC_DIGEST_SIZE_BIT if digest size is 96 bits */ ++ config |= (MV_CESA_MAC_DIGEST_96B << MV_CESA_MAC_DIGEST_SIZE_BIT); ++ } ++ } ++ ++ /* Check CRYPTO parameters and update SA entry */ ++ if(pSession->operation != MV_CESA_MAC_ONLY) ++ { ++ switch(pSession->cryptoAlgorithm) ++ { ++ case MV_CESA_CRYPTO_DES: ++ pCesaSAD[sid].cryptoKeyLength = MV_CESA_DES_KEY_LENGTH; ++ pCesaSAD[sid].cryptoBlockSize = MV_CESA_DES_BLOCK_SIZE; ++ break; ++ ++ case MV_CESA_CRYPTO_3DES: ++ pCesaSAD[sid].cryptoKeyLength = MV_CESA_3DES_KEY_LENGTH; ++ pCesaSAD[sid].cryptoBlockSize = MV_CESA_DES_BLOCK_SIZE; ++ /* Only EDE mode is supported */ ++ config |= (MV_CESA_CRYPTO_3DES_EDE << ++ MV_CESA_CRYPTO_3DES_MODE_BIT); ++ break; ++ ++ case MV_CESA_CRYPTO_AES: ++ switch(pSession->cryptoKeyLength) ++ { ++ case 16: ++ pCesaSAD[sid].cryptoKeyLength = MV_CESA_AES_128_KEY_LENGTH; ++ config |= (MV_CESA_CRYPTO_AES_KEY_128 << ++ MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET); ++ break; ++ ++ case 24: ++ pCesaSAD[sid].cryptoKeyLength = MV_CESA_AES_192_KEY_LENGTH; ++ config |= (MV_CESA_CRYPTO_AES_KEY_192 << ++ MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET); ++ break; ++ ++ case 32: ++ default: ++ pCesaSAD[sid].cryptoKeyLength = MV_CESA_AES_256_KEY_LENGTH; ++ config |= (MV_CESA_CRYPTO_AES_KEY_256 << ++ MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET); ++ break; ++ } ++ pCesaSAD[sid].cryptoBlockSize = MV_CESA_AES_BLOCK_SIZE; ++ break; ++ ++ default: ++ mvOsPrintf("mvCesaSessionOpen: Unexpected cryptoAlgorithm %d\n", ++ pSession->cryptoAlgorithm); ++ return MV_BAD_PARAM; ++ } ++ config |= (pSession->cryptoAlgorithm << MV_CESA_CRYPTO_ALG_OFFSET); ++ ++ if(pSession->cryptoKeyLength != pCesaSAD[sid].cryptoKeyLength) ++ { ++ mvOsPrintf("cesaSessionOpen: Wrong CryptoKeySize %d != %d\n", ++ pSession->cryptoKeyLength, pCesaSAD[sid].cryptoKeyLength); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Copy Crypto key */ ++ if( (pSession->cryptoAlgorithm == MV_CESA_CRYPTO_AES) && ++ (pSession->direction == MV_CESA_DIR_DECODE)) ++ { ++ /* Crypto Key for AES decode is computed from original key material */ ++ /* and depend on cryptoKeyLength (128/192/256 bits) */ ++ aesMakeKey(pCesaSAD[sid].pSramSA->cryptoKey, pSession->cryptoKey, ++ pSession->cryptoKeyLength*8, MV_CESA_AES_BLOCK_SIZE*8); ++ } ++ else ++ { ++ /*panic("mvCesaSessionOpen2");*/ ++ memcpy(pCesaSAD[sid].pSramSA->cryptoKey, pSession->cryptoKey, ++ pCesaSAD[sid].cryptoKeyLength); ++ ++ } ++ ++ switch(pSession->cryptoMode) ++ { ++ case MV_CESA_CRYPTO_ECB: ++ pCesaSAD[sid].cryptoIvSize = 0; ++ break; ++ ++ case MV_CESA_CRYPTO_CBC: ++ pCesaSAD[sid].cryptoIvSize = pCesaSAD[sid].cryptoBlockSize; ++ break; ++ ++ case MV_CESA_CRYPTO_CTR: ++ /* Supported only for AES algorithm */ ++ if(pSession->cryptoAlgorithm != MV_CESA_CRYPTO_AES) ++ { ++ mvOsPrintf("mvCesaSessionOpen: CRYPTO CTR mode supported for AES only\n"); ++ return MV_BAD_PARAM; ++ } ++ pCesaSAD[sid].cryptoIvSize = 0; ++ pCesaSAD[sid].ctrMode = 1; ++ /* Replace to ECB mode for HW */ ++ pSession->cryptoMode = MV_CESA_CRYPTO_ECB; ++ break; ++ ++ default: ++ mvOsPrintf("mvCesaSessionOpen: Unexpected cryptoMode %d\n", ++ pSession->cryptoMode); ++ return MV_BAD_PARAM; ++ } ++ ++ config |= (pSession->cryptoMode << MV_CESA_CRYPTO_MODE_BIT); ++ } ++ pCesaSAD[sid].config = config; ++ ++ mvOsCacheFlush(NULL, pCesaSAD[sid].pSramSA, sizeof(MV_CESA_SRAM_SA)); ++ if(pSid != NULL) ++ *pSid = sid; ++ ++ pCesaSAD[sid].valid = 1; ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCesaSessionClose - Close active crypto session ++* ++* DESCRIPTION: ++* This function closes existing session ++* ++* INPUT: ++* short sid - Unique identifier of the session to be closed ++* ++* RETURN: ++* MV_OK - Session closed successfully. ++* MV_BAD_PARAM - Session identifier is out of valid range. ++* MV_NOT_FOUND - There is no active session with such ID. ++* ++*******************************************************************************/ ++MV_STATUS mvCesaSessionClose(short sid) ++{ ++ cesaStats.closedCount++; ++ ++ if(sid >= cesaMaxSA) ++ { ++ mvOsPrintf("CESA Error: sid (%d) is too big\n", sid); ++ return MV_BAD_PARAM; ++ } ++ if(pCesaSAD[sid].valid == 0) ++ { ++ mvOsPrintf("CESA Warning: Session (sid=%d) is invalid\n", sid); ++ return MV_NOT_FOUND; ++ } ++ if(cesaLastSid == sid) ++ cesaLastSid = -1; ++ ++ pCesaSAD[sid].valid = 0; ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCesaAction - Perform crypto operation ++* ++* DESCRIPTION: ++* This function set new CESA request FIFO queue for further HW processing. ++* The function checks request parameters before set new request to the queue. ++* If one of the CESA channels is ready for processing the request will be ++* passed to HW. When request processing is finished the CESA interrupt will ++* be generated by HW. The caller should call mvCesaReadyGet() function to ++* complete request processing and get result. ++* ++* INPUT: ++* MV_CESA_COMMAND *pCmd - pointer to new CESA request. ++* It includes pointers to Source and Destination ++* buffers, session identifier get from ++* mvCesaSessionOpen() function, pointer to caller ++* private data and all needed crypto parameters. ++* ++* RETURN: ++* MV_OK - request successfully added to request queue ++* and will be processed. ++* MV_NO_MORE - request successfully added to request queue and will ++* be processed, but request queue became Full and next ++* request will not be accepted. ++* MV_NO_RESOURCE - request queue is FULL and the request can not ++* be processed. ++* MV_OUT_OF_CPU_MEM - memory allocation needed for request processing is ++* failed. Request can not be processed. ++* MV_NOT_ALLOWED - This mixed request (CRYPTO+MAC) can not be processed ++* as one request and should be splitted for two requests: ++* CRYPTO_ONLY and MAC_ONLY. ++* MV_BAD_PARAM - One of the request parameters is out of valid range. ++* The request can not be processed. ++* ++*******************************************************************************/ ++MV_STATUS mvCesaAction (MV_CESA_COMMAND *pCmd) ++{ ++ MV_STATUS status; ++ MV_CESA_REQ* pReq = pCesaReqEmpty; ++ int sid = pCmd->sessionId; ++ MV_CESA_SA* pSA = &pCesaSAD[sid]; ++#if (MV_CESA_VERSION >= 3) ++ MV_CESA_REQ* pFromReq; ++ MV_CESA_REQ* pToReq; ++#endif ++ cesaStats.reqCount++; ++ ++ /* Check that the request queue is not FULL */ ++ if(cesaReqResources == 0) ++ return MV_NO_RESOURCE; ++ ++ if( (sid >= cesaMaxSA) || (!pSA->valid) ) ++ { ++ mvOsPrintf("CESA Action Error: Session sid=%d is INVALID\n", sid); ++ return MV_BAD_PARAM; ++ } ++ pSA->count++; ++ ++ if(pSA->ctrMode) ++ { ++ /* AES in CTR mode can't be mixed with Authentication */ ++ if( (pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) ++ { ++ mvOsPrintf("mvCesaAction : CRYPTO CTR mode can't be mixed with AUTH\n"); ++ return MV_NOT_ALLOWED; ++ } ++ /* All other request parameters should not be checked because key stream */ ++ /* (not user data) processed by AES HW engine */ ++ pReq->pOrgCmd = pCmd; ++ /* Allocate temporary pCmd structure for Key stream */ ++ pCmd = mvCesaCtrModeInit(); ++ if(pCmd == NULL) ++ return MV_OUT_OF_CPU_MEM; ++ ++ /* Prepare Key stream */ ++ mvCesaCtrModePrepare(pCmd, pReq->pOrgCmd); ++ pReq->fixOffset = 0; ++ } ++ else ++ { ++ /* Check request parameters and calculae fixOffset */ ++ status = mvCesaParamCheck(pSA, pCmd, &pReq->fixOffset); ++ if(status != MV_OK) ++ { ++ return status; ++ } ++ } ++ pReq->pCmd = pCmd; ++ ++ /* Check if the packet need fragmentation */ ++ if(pCmd->pSrc->mbufSize <= sizeof(cesaSramVirtPtr->buf) ) ++ { ++ /* request size is smaller than single buffer size */ ++ pReq->fragMode = MV_CESA_FRAG_NONE; ++ ++ /* Prepare NOT fragmented packets */ ++ status = mvCesaReqProcess(pReq); ++ if(status != MV_OK) ++ { ++ mvOsPrintf("CesaReady: ReqProcess error: pReq=%p, status=0x%x\n", ++ pReq, status); ++ } ++#if (MV_CESA_VERSION >= 3) ++ pReq->frags.numFrag = 1; ++#endif ++ } ++ else ++ { ++ MV_U8 frag = 0; ++ ++ /* request size is larger than buffer size - needs fragmentation */ ++ ++ /* Check restrictions for processing fragmented packets */ ++ status = mvCesaFragParamCheck(pSA, pCmd); ++ if(status != MV_OK) ++ return status; ++ ++ pReq->fragMode = MV_CESA_FRAG_FIRST; ++ pReq->frags.nextFrag = 0; ++ ++ /* Prepare Process Fragmented packets */ ++ while(pReq->fragMode != MV_CESA_FRAG_LAST) ++ { ++ if(frag >= MV_CESA_MAX_REQ_FRAGS) ++ { ++ mvOsPrintf("mvCesaAction Error: Too large request frag=%d\n", frag); ++ return MV_OUT_OF_CPU_MEM; ++ } ++ status = mvCesaFragReqProcess(pReq, frag); ++ if(status == MV_OK) { ++#if (MV_CESA_VERSION >= 3) ++ if(frag) { ++ pReq->dma[frag-1].pDmaLast->phyNextDescPtr = ++ MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, pReq->dma[frag].pDmaFirst)); ++ mvOsCacheFlush(NULL, pReq->dma[frag-1].pDmaLast, sizeof(MV_DMA_DESC)); ++ } ++#endif ++ frag++; ++ } ++ } ++ pReq->frags.numFrag = frag; ++#if (MV_CESA_VERSION >= 3) ++ if(chainReqNum) { ++ chainReqNum += pReq->frags.numFrag; ++ if(chainReqNum >= MAX_CESA_CHAIN_LENGTH) ++ chainReqNum = MAX_CESA_CHAIN_LENGTH; ++ } ++#endif ++ } ++ ++ pReq->state = MV_CESA_PENDING; ++ ++ pCesaReqEmpty = MV_CESA_REQ_NEXT_PTR(pReq); ++ cesaReqResources -= 1; ++ ++/* #ifdef CESA_DEBUG */ ++ if( (cesaQueueDepth - cesaReqResources) > cesaStats.maxReqCount) ++ cesaStats.maxReqCount = (cesaQueueDepth - cesaReqResources); ++/* #endif CESA_DEBUG */ ++ ++ cesaLastSid = sid; ++ ++#if (MV_CESA_VERSION >= 3) ++ /* Are we within chain bounderies and follows the first request ? */ ++ if((chainReqNum > 0) && (chainReqNum < MAX_CESA_CHAIN_LENGTH)) { ++ if(chainIndex) { ++ pFromReq = MV_CESA_REQ_PREV_PTR(pReq); ++ pToReq = pReq; ++ pReq->state = MV_CESA_CHAIN; ++ /* assume concatenating is possible */ ++ pFromReq->dma[pFromReq->frags.numFrag-1].pDmaLast->phyNextDescPtr = ++ MV_32BIT_LE(mvCesaVirtToPhys(&pToReq->dmaDescBuf, pToReq->dma[0].pDmaFirst)); ++ mvOsCacheFlush(NULL, pFromReq->dma[pFromReq->frags.numFrag-1].pDmaLast, sizeof(MV_DMA_DESC)); ++ ++ /* align active & next pointers */ ++ if(pNextActiveChain->state != MV_CESA_PENDING) ++ pEndCurrChain = pNextActiveChain = MV_CESA_REQ_NEXT_PTR(pReq); ++ } ++ else { /* we have only one chain, start new one */ ++ chainReqNum = 0; ++ chainIndex++; ++ /* align active & next pointers */ ++ if(pNextActiveChain->state != MV_CESA_PENDING) ++ pEndCurrChain = pNextActiveChain = pReq; ++ } ++ } ++ else { ++ /* In case we concatenate full chain */ ++ if(chainReqNum == MAX_CESA_CHAIN_LENGTH) { ++ chainIndex++; ++ if(pNextActiveChain->state != MV_CESA_PENDING) ++ pEndCurrChain = pNextActiveChain = pReq; ++ chainReqNum = 0; ++ } ++ ++ pReq = pCesaReqProcess; ++ if(pReq->state == MV_CESA_PENDING) { ++ pNextActiveChain = pReq; ++ pEndCurrChain = MV_CESA_REQ_NEXT_PTR(pReq); ++ /* Start Process new request */ ++ mvCesaReqProcessStart(pReq); ++ } ++ } ++ ++ chainReqNum++; ++ ++ if((chainIndex < MAX_CESA_CHAIN_LENGTH) && (chainReqNum > cesaStats.maxChainUsage)) ++ cesaStats.maxChainUsage = chainReqNum; ++ ++#else ++ ++ /* Check status of CESA channels and process requests if possible */ ++ pReq = pCesaReqProcess; ++ if(pReq->state == MV_CESA_PENDING) ++ { ++ /* Start Process new request */ ++ mvCesaReqProcessStart(pReq); ++ } ++#endif ++ /* If request queue became FULL - return MV_NO_MORE */ ++ if(cesaReqResources == 0) ++ return MV_NO_MORE; ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvCesaReadyGet - Get crypto request that processing is finished ++* ++* DESCRIPTION: ++* This function complete request processing and return ready request to ++* caller. To don't miss interrupts the caller must call this function ++* while MV_OK or MV_TERMINATE values returned. ++* ++* INPUT: ++* MV_U32 chanMap - map of CESA channels finished thier job ++* accordingly with CESA Cause register. ++* MV_CESA_RESULT* pResult - pointer to structure contains information ++* about ready request. It includes pointer to ++* user private structure "pReqPrv", session identifier ++* for this request "sessionId" and return code. ++* Return code set to MV_FAIL if calculated digest value ++* on decode direction is different than digest value ++* in the packet. ++* ++* RETURN: ++* MV_OK - Success, ready request is returned. ++* MV_NOT_READY - Next request is not ready yet. New interrupt will ++* be generated for futher request processing. ++* MV_EMPTY - There is no more request for processing. ++* MV_BUSY - Fragmented request is not ready yet. ++* MV_TERMINATE - Call this function once more to complete processing ++* of fragmented request. ++* ++*******************************************************************************/ ++MV_STATUS mvCesaReadyGet(MV_CESA_RESULT* pResult) ++{ ++ MV_STATUS status, readyStatus = MV_NOT_READY; ++ MV_U32 statusReg; ++ MV_CESA_REQ* pReq; ++ MV_CESA_SA* pSA; ++ ++#if (MV_CESA_VERSION >= 3) ++ if(isFirstReq == MV_TRUE) { ++ if(chainIndex == 0) ++ chainReqNum = 0; ++ ++ isFirstReq = MV_FALSE; ++ ++ if(pNextActiveChain->state == MV_CESA_PENDING) { ++ /* Start request Process */ ++ mvCesaReqProcessStart(pNextActiveChain); ++ pEndCurrChain = pNextActiveChain; ++ if(chainIndex > 0) ++ chainIndex--; ++ /* Update pNextActiveChain to next chain head */ ++ while(pNextActiveChain->state == MV_CESA_CHAIN) ++ pNextActiveChain = MV_CESA_REQ_NEXT_PTR(pNextActiveChain); ++ } ++ } ++ ++ /* Check if there are more processed requests - can we remove pEndCurrChain ??? */ ++ if(pCesaReqProcess == pEndCurrChain) { ++ isFirstReq = MV_TRUE; ++ pEndCurrChain = pNextActiveChain; ++#else ++ if(pCesaReqProcess->state != MV_CESA_PROCESS) { ++#endif ++ return MV_EMPTY; ++ } ++ ++#ifdef CESA_DEBUG ++ statusReg = MV_REG_READ(MV_CESA_STATUS_REG); ++ if( statusReg & MV_CESA_STATUS_ACTIVE_MASK ) ++ { ++ mvOsPrintf("mvCesaReadyGet: Not Ready, Status = 0x%x\n", statusReg); ++ cesaStats.notReadyCount++; ++ return MV_NOT_READY; ++ } ++#endif /* CESA_DEBUG */ ++ ++ cesaStats.readyCount++; ++ ++ pReq = pCesaReqProcess; ++ pSA = &pCesaSAD[pReq->pCmd->sessionId]; ++ ++ pResult->retCode = MV_OK; ++ if(pReq->fragMode != MV_CESA_FRAG_NONE) ++ { ++ MV_U8* pNewDigest; ++ int frag; ++#if (MV_CESA_VERSION >= 3) ++ pReq->frags.nextFrag = 1; ++ while(pReq->frags.nextFrag <= pReq->frags.numFrag) { ++#endif ++ frag = (pReq->frags.nextFrag - 1); ++ ++ /* Restore DMA descriptor list */ ++ pReq->dma[frag].pDmaLast->phyNextDescPtr = ++ MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, &pReq->dma[frag].pDmaLast[1])); ++ pReq->dma[frag].pDmaLast = NULL; ++ ++ /* Special processing for finished fragmented request */ ++ if(pReq->frags.nextFrag >= pReq->frags.numFrag) ++ { ++ mvCesaMbufCacheUnmap(pReq->pCmd->pDst, 0, pReq->pCmd->pDst->mbufSize); ++ ++ /* Fragmented packet is ready */ ++ if( (pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) ++ { ++ int macDataSize = pReq->pCmd->macLength - pReq->frags.macSize; ++ ++ if(macDataSize != 0) ++ { ++ /* Calculate all other blocks by SW */ ++ mvCesaFragAuthComplete(pReq, pSA, macDataSize); ++ } ++ ++ /* Copy new digest from SRAM to the Destination buffer */ ++ pNewDigest = cesaSramVirtPtr->buf + pReq->frags.newDigestOffset; ++ status = mvCesaCopyToMbuf(pNewDigest, pReq->pCmd->pDst, ++ pReq->pCmd->digestOffset, pSA->digestSize); ++ ++ /* For decryption: Compare new digest value with original one */ ++ if((pSA->config & MV_CESA_DIRECTION_MASK) == ++ (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) ++ { ++ if( memcmp(pNewDigest, pReq->frags.orgDigest, pSA->digestSize) != 0) ++ { ++/* ++ mvOsPrintf("Digest error: chan=%d, newDigest=%p, orgDigest=%p, status = 0x%x\n", ++ chan, pNewDigest, pReq->frags.orgDigest, MV_REG_READ(MV_CESA_STATUS_REG)); ++*/ ++ /* Signiture verification is failed */ ++ pResult->retCode = MV_FAIL; ++ } ++ } ++ } ++ readyStatus = MV_OK; ++ } ++#if (MV_CESA_VERSION >= 3) ++ pReq->frags.nextFrag++; ++ } ++#endif ++ } ++ else ++ { ++ mvCesaMbufCacheUnmap(pReq->pCmd->pDst, 0, pReq->pCmd->pDst->mbufSize); ++ ++ /* Restore DMA descriptor list */ ++ pReq->dma[0].pDmaLast->phyNextDescPtr = ++ MV_32BIT_LE(mvCesaVirtToPhys(&pReq->dmaDescBuf, &pReq->dma[0].pDmaLast[1])); ++ pReq->dma[0].pDmaLast = NULL; ++ if( ((pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) && ++ ((pSA->config & MV_CESA_DIRECTION_MASK) == ++ (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) ) ++ { ++ /* For AUTH on decode : Check Digest result in Status register */ ++ statusReg = MV_REG_READ(MV_CESA_STATUS_REG); ++ if(statusReg & MV_CESA_STATUS_DIGEST_ERR_MASK) ++ { ++/* ++ mvOsPrintf("Digest error: chan=%d, status = 0x%x\n", ++ chan, statusReg); ++*/ ++ /* Signiture verification is failed */ ++ pResult->retCode = MV_FAIL; ++ } ++ } ++ readyStatus = MV_OK; ++ } ++ ++ if(readyStatus == MV_OK) ++ { ++ /* If Request is ready - Prepare pResult structure */ ++ pResult->pReqPrv = pReq->pCmd->pReqPrv; ++ pResult->sessionId = pReq->pCmd->sessionId; ++ ++ pReq->state = MV_CESA_IDLE; ++ pCesaReqProcess = MV_CESA_REQ_NEXT_PTR(pReq); ++ cesaReqResources++; ++ ++ if(pSA->ctrMode) ++ { ++ /* For AES CTR mode - complete processing and free allocated resources */ ++ mvCesaCtrModeComplete(pReq->pOrgCmd, pReq->pCmd); ++ mvCesaCtrModeFinish(pReq->pCmd); ++ pReq->pOrgCmd = NULL; ++ } ++ } ++ ++#if (MV_CESA_VERSION < 3) ++ if(pCesaReqProcess->state == MV_CESA_PROCESS) ++ { ++ /* Start request Process */ ++ mvCesaReqProcessStart(pCesaReqProcess); ++ if(readyStatus == MV_NOT_READY) ++ readyStatus = MV_BUSY; ++ } ++ else if(pCesaReqProcess != pCesaReqEmpty) ++ { ++ /* Start process new request from the queue */ ++ mvCesaReqProcessStart(pCesaReqProcess); ++ } ++#endif ++ return readyStatus; ++} ++ ++/***************** Functions to work with CESA_MBUF structure ******************/ ++ ++/******************************************************************************* ++* mvCesaMbufOffset - Locate offset in the Mbuf structure ++* ++* DESCRIPTION: ++* This function locates offset inside Multi-Bufeer structure. ++* It get fragment number and place in the fragment where the offset ++* is located. ++* ++* ++* INPUT: ++* MV_CESA_MBUF* pMbuf - Pointer to multi-buffer structure ++* int offset - Offset from the beginning of the data presented by ++* the Mbuf structure. ++* ++* OUTPUT: ++* int* pBufOffset - Offset from the beginning of the fragment where ++* the offset is located. ++* ++* RETURN: ++* int - Number of fragment, where the offset is located\ ++* ++*******************************************************************************/ ++int mvCesaMbufOffset(MV_CESA_MBUF* pMbuf, int offset, int* pBufOffset) ++{ ++ int frag = 0; ++ ++ while(offset > 0) ++ { ++ if(frag >= pMbuf->numFrags) ++ { ++ mvOsPrintf("mvCesaMbufOffset: Error: frag (%d) > numFrags (%d)\n", ++ frag, pMbuf->numFrags); ++ return MV_INVALID; ++ } ++ if(offset < pMbuf->pFrags[frag].bufSize) ++ { ++ break; ++ } ++ offset -= pMbuf->pFrags[frag].bufSize; ++ frag++; ++ } ++ if(pBufOffset != NULL) ++ *pBufOffset = offset; ++ ++ return frag; ++} ++ ++/******************************************************************************* ++* mvCesaCopyFromMbuf - Copy data from the Mbuf structure to continuous buffer ++* ++* DESCRIPTION: ++* ++* ++* INPUT: ++* MV_U8* pDstBuf - Pointer to continuous buffer, where data is ++* copied to. ++* MV_CESA_MBUF* pSrcMbuf - Pointer to multi-buffer structure where data is ++* copied from. ++* int offset - Offset in the Mbuf structure where located first ++* byte of data should be copied. ++* int size - Size of data should be copied ++* ++* RETURN: ++* MV_OK - Success, all data is copied successfully. ++* MV_OUT_OF_RANGE - Failed, offset is out of Multi-buffer data range. ++* No data is copied. ++* MV_EMPTY - Multi-buffer structure has not enough data to copy ++* Data from the offset to end of Mbuf data is copied. ++* ++*******************************************************************************/ ++MV_STATUS mvCesaCopyFromMbuf(MV_U8* pDstBuf, MV_CESA_MBUF* pSrcMbuf, ++ int offset, int size) ++{ ++ int frag, fragOffset, bufSize; ++ MV_U8* pBuf; ++ ++ if(size == 0) ++ return MV_OK; ++ ++ frag = mvCesaMbufOffset(pSrcMbuf, offset, &fragOffset); ++ if(frag == MV_INVALID) ++ { ++ mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); ++ return MV_OUT_OF_RANGE; ++ } ++ ++ bufSize = pSrcMbuf->pFrags[frag].bufSize - fragOffset; ++ pBuf = pSrcMbuf->pFrags[frag].bufVirtPtr + fragOffset; ++ while(MV_TRUE) ++ { ++ if(size <= bufSize) ++ { ++ memcpy(pDstBuf, pBuf, size); ++ return MV_OK; ++ } ++ memcpy(pDstBuf, pBuf, bufSize); ++ size -= bufSize; ++ frag++; ++ pDstBuf += bufSize; ++ if(frag >= pSrcMbuf->numFrags) ++ break; ++ ++ bufSize = pSrcMbuf->pFrags[frag].bufSize; ++ pBuf = pSrcMbuf->pFrags[frag].bufVirtPtr; ++ } ++ mvOsPrintf("mvCesaCopyFromMbuf: Mbuf is EMPTY - %d bytes isn't copied\n", ++ size); ++ return MV_EMPTY; ++} ++ ++/******************************************************************************* ++* mvCesaCopyToMbuf - Copy data from continuous buffer to the Mbuf structure ++* ++* DESCRIPTION: ++* ++* ++* INPUT: ++* MV_U8* pSrcBuf - Pointer to continuous buffer, where data is ++* copied from. ++* MV_CESA_MBUF* pDstMbuf - Pointer to multi-buffer structure where data is ++* copied to. ++* int offset - Offset in the Mbuf structure where located first ++* byte of data should be copied. ++* int size - Size of data should be copied ++* ++* RETURN: ++* MV_OK - Success, all data is copied successfully. ++* MV_OUT_OF_RANGE - Failed, offset is out of Multi-buffer data range. ++* No data is copied. ++* MV_FULL - Multi-buffer structure has not enough place to copy ++* all data. Data from the offset to end of Mbuf data ++* is copied. ++* ++*******************************************************************************/ ++MV_STATUS mvCesaCopyToMbuf(MV_U8* pSrcBuf, MV_CESA_MBUF* pDstMbuf, ++ int offset, int size) ++{ ++ int frag, fragOffset, bufSize; ++ MV_U8* pBuf; ++ ++ if(size == 0) ++ return MV_OK; ++ ++ frag = mvCesaMbufOffset(pDstMbuf, offset, &fragOffset); ++ if(frag == MV_INVALID) ++ { ++ mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); ++ return MV_OUT_OF_RANGE; ++ } ++ ++ bufSize = pDstMbuf->pFrags[frag].bufSize - fragOffset; ++ pBuf = pDstMbuf->pFrags[frag].bufVirtPtr + fragOffset; ++ while(MV_TRUE) ++ { ++ if(size <= bufSize) ++ { ++ memcpy(pBuf, pSrcBuf, size); ++ return MV_OK; ++ } ++ memcpy(pBuf, pSrcBuf, bufSize); ++ size -= bufSize; ++ frag++; ++ pSrcBuf += bufSize; ++ if(frag >= pDstMbuf->numFrags) ++ break; ++ ++ bufSize = pDstMbuf->pFrags[frag].bufSize; ++ pBuf = pDstMbuf->pFrags[frag].bufVirtPtr; ++ } ++ mvOsPrintf("mvCesaCopyToMbuf: Mbuf is FULL - %d bytes isn't copied\n", ++ size); ++ return MV_FULL; ++} ++ ++/******************************************************************************* ++* mvCesaMbufCopy - Copy data from one Mbuf structure to the other Mbuf structure ++* ++* DESCRIPTION: ++* ++* ++* INPUT: ++* ++* MV_CESA_MBUF* pDstMbuf - Pointer to multi-buffer structure where data is ++* copied to. ++* int dstMbufOffset - Offset in the dstMbuf structure where first byte ++* of data should be copied to. ++* MV_CESA_MBUF* pSrcMbuf - Pointer to multi-buffer structure where data is ++* copied from. ++* int srcMbufOffset - Offset in the srcMbuf structure where first byte ++* of data should be copied from. ++* int size - Size of data should be copied ++* ++* RETURN: ++* MV_OK - Success, all data is copied successfully. ++* MV_OUT_OF_RANGE - Failed, srcMbufOffset or dstMbufOffset is out of ++* srcMbuf or dstMbuf structure correspondently. ++* No data is copied. ++* MV_BAD_SIZE - srcMbuf or dstMbuf structure is too small to copy ++* all data. Partial data is copied ++* ++*******************************************************************************/ ++MV_STATUS mvCesaMbufCopy(MV_CESA_MBUF* pMbufDst, int dstMbufOffset, ++ MV_CESA_MBUF* pMbufSrc, int srcMbufOffset, int size) ++{ ++ int srcFrag, dstFrag, srcSize, dstSize, srcOffset, dstOffset; ++ int copySize; ++ MV_U8 *pSrc, *pDst; ++ ++ if(size == 0) ++ return MV_OK; ++ ++ srcFrag = mvCesaMbufOffset(pMbufSrc, srcMbufOffset, &srcOffset); ++ if(srcFrag == MV_INVALID) ++ { ++ mvOsPrintf("CESA srcMbuf Error: offset (%d) out of range\n", srcMbufOffset); ++ return MV_OUT_OF_RANGE; ++ } ++ pSrc = pMbufSrc->pFrags[srcFrag].bufVirtPtr + srcOffset; ++ srcSize = pMbufSrc->pFrags[srcFrag].bufSize - srcOffset; ++ ++ dstFrag = mvCesaMbufOffset(pMbufDst, dstMbufOffset, &dstOffset); ++ if(dstFrag == MV_INVALID) ++ { ++ mvOsPrintf("CESA dstMbuf Error: offset (%d) out of range\n", dstMbufOffset); ++ return MV_OUT_OF_RANGE; ++ } ++ pDst = pMbufDst->pFrags[dstFrag].bufVirtPtr + dstOffset; ++ dstSize = pMbufDst->pFrags[dstFrag].bufSize - dstOffset; ++ ++ while(size > 0) ++ { ++ copySize = MV_MIN(srcSize, dstSize); ++ if(size <= copySize) ++ { ++ memcpy(pDst, pSrc, size); ++ return MV_OK; ++ } ++ memcpy(pDst, pSrc, copySize); ++ size -= copySize; ++ srcSize -= copySize; ++ dstSize -= copySize; ++ ++ if(srcSize == 0) ++ { ++ srcFrag++; ++ if(srcFrag >= pMbufSrc->numFrags) ++ break; ++ ++ pSrc = pMbufSrc->pFrags[srcFrag].bufVirtPtr; ++ srcSize = pMbufSrc->pFrags[srcFrag].bufSize; ++ } ++ ++ if(dstSize == 0) ++ { ++ dstFrag++; ++ if(dstFrag >= pMbufDst->numFrags) ++ break; ++ ++ pDst = pMbufDst->pFrags[dstFrag].bufVirtPtr; ++ dstSize = pMbufDst->pFrags[dstFrag].bufSize; ++ } ++ } ++ mvOsPrintf("mvCesaMbufCopy: BAD size - %d bytes isn't copied\n", ++ size); ++ ++ return MV_BAD_SIZE; ++} ++ ++static MV_STATUS mvCesaMbufCacheUnmap(MV_CESA_MBUF* pMbuf, int offset, int size) ++{ ++ int frag, fragOffset, bufSize; ++ MV_U8* pBuf; ++ ++ if(size == 0) ++ return MV_OK; ++ ++ frag = mvCesaMbufOffset(pMbuf, offset, &fragOffset); ++ if(frag == MV_INVALID) ++ { ++ mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); ++ return MV_OUT_OF_RANGE; ++ } ++ ++ bufSize = pMbuf->pFrags[frag].bufSize - fragOffset; ++ pBuf = pMbuf->pFrags[frag].bufVirtPtr + fragOffset; ++ while(MV_TRUE) ++ { ++ if(size <= bufSize) ++ { ++ mvOsCacheUnmap(NULL, mvOsIoVirtToPhy(NULL, pBuf), size); ++ return MV_OK; ++ } ++ ++ mvOsCacheUnmap(NULL, mvOsIoVirtToPhy(NULL, pBuf), bufSize); ++ size -= bufSize; ++ frag++; ++ if(frag >= pMbuf->numFrags) ++ break; ++ ++ bufSize = pMbuf->pFrags[frag].bufSize; ++ pBuf = pMbuf->pFrags[frag].bufVirtPtr; ++ } ++ mvOsPrintf("%s: Mbuf is FULL - %d bytes isn't Unmapped\n", ++ __FUNCTION__, size); ++ return MV_FULL; ++} ++ ++ ++/*************************************** Local Functions ******************************/ ++ ++/******************************************************************************* ++* mvCesaFragReqProcess - Process fragmented request ++* ++* DESCRIPTION: ++* This function processes a fragment of fragmented request (First, Middle or Last) ++* ++* ++* INPUT: ++* MV_CESA_REQ* pReq - Pointer to the request in the request queue. ++* ++* RETURN: ++* MV_OK - The fragment is successfully passed to HW for processing. ++* MV_TERMINATE - Means, that HW finished its work on this packet and no more ++* interrupts will be generated for this request. ++* Function mvCesaReadyGet() must be called to complete request ++* processing and get request result. ++* ++*******************************************************************************/ ++static MV_STATUS mvCesaFragReqProcess(MV_CESA_REQ* pReq, MV_U8 frag) ++{ ++ int i, copySize, cryptoDataSize, macDataSize, sid; ++ int cryptoIvOffset, digestOffset; ++ MV_U32 config; ++ MV_CESA_COMMAND* pCmd = pReq->pCmd; ++ MV_CESA_SA* pSA; ++ MV_CESA_MBUF* pMbuf; ++ MV_DMA_DESC* pDmaDesc = pReq->dma[frag].pDmaFirst; ++ MV_U8* pSramBuf = cesaSramVirtPtr->buf; ++ int macTotalLen = 0; ++ int fixOffset, cryptoOffset, macOffset; ++ ++ cesaStats.fragCount++; ++ ++ sid = pReq->pCmd->sessionId; ++ ++ pSA = &pCesaSAD[sid]; ++ ++ cryptoIvOffset = digestOffset = 0; ++ i = macDataSize = 0; ++ cryptoDataSize = 0; ++ ++ /* First fragment processing */ ++ if(pReq->fragMode == MV_CESA_FRAG_FIRST) ++ { ++ /* pReq->frags monitors processing of fragmented request between fragments */ ++ pReq->frags.bufOffset = 0; ++ pReq->frags.cryptoSize = 0; ++ pReq->frags.macSize = 0; ++ ++ config = pSA->config | (MV_CESA_FRAG_FIRST << MV_CESA_FRAG_MODE_OFFSET); ++ ++ /* fixOffset can be not equal to zero only for FIRST fragment */ ++ fixOffset = pReq->fixOffset; ++ /* For FIRST fragment crypto and mac offsets are taken from pCmd */ ++ cryptoOffset = pCmd->cryptoOffset; ++ macOffset = pCmd->macOffset; ++ ++ copySize = sizeof(cesaSramVirtPtr->buf) - pReq->fixOffset; ++ ++ /* Find fragment size: Must meet all requirements for CRYPTO and MAC ++ * cryptoDataSize - size of data will be encrypted/decrypted in this fragment ++ * macDataSize - size of data will be signed/verified in this fragment ++ * copySize - size of data will be copied from srcMbuf to SRAM and ++ * back to dstMbuf for this fragment ++ */ ++ mvCesaFragSizeFind(pSA, pReq, cryptoOffset, macOffset, ++ ©Size, &cryptoDataSize, &macDataSize); ++ ++ if( (pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) ++ { ++ /* CryptoIV special processing */ ++ if( (pSA->config & MV_CESA_CRYPTO_MODE_MASK) == ++ (MV_CESA_CRYPTO_CBC << MV_CESA_CRYPTO_MODE_BIT) ) ++ { ++ /* In CBC mode for encode direction when IV from user */ ++ if( (pCmd->ivFromUser) && ++ ((pSA->config & MV_CESA_DIRECTION_MASK) == ++ (MV_CESA_DIR_ENCODE << MV_CESA_DIRECTION_BIT)) ) ++ { ++ ++ /* For Crypto Encode in CBC mode HW always takes IV from SRAM IVPointer, ++ * (not from IVBufPointer). So when ivFromUser==1, we should copy IV from user place ++ * in the buffer to SRAM IVPointer ++ */ ++ i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->cryptoIV, &pDmaDesc[i], ++ MV_FALSE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); ++ } ++ ++ /* Special processing when IV is not located in the first fragment */ ++ if(pCmd->ivOffset > (copySize - pSA->cryptoIvSize)) ++ { ++ /* Prepare dummy place for cryptoIV in SRAM */ ++ cryptoIvOffset = cesaSramVirtPtr->tempCryptoIV - mvCesaSramAddrGet(); ++ ++ /* For Decryption: Copy IV value from pCmd->ivOffset to Special SRAM place */ ++ if((pSA->config & MV_CESA_DIRECTION_MASK) == ++ (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) ++ { ++ i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->tempCryptoIV, &pDmaDesc[i], ++ MV_FALSE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); ++ } ++ else ++ { ++ /* For Encryption when IV is NOT from User: */ ++ /* Copy IV from SRAM to buffer (pCmd->ivOffset) */ ++ if(pCmd->ivFromUser == 0) ++ { ++ /* copy IV value from cryptoIV to Buffer (pCmd->ivOffset) */ ++ i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->cryptoIV, &pDmaDesc[i], ++ MV_TRUE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); ++ } ++ } ++ } ++ else ++ { ++ cryptoIvOffset = pCmd->ivOffset; ++ } ++ } ++ } ++ ++ if( (pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) ++ { ++ /* MAC digest special processing on Decode direction */ ++ if((pSA->config & MV_CESA_DIRECTION_MASK) == ++ (MV_CESA_DIR_DECODE << MV_CESA_DIRECTION_BIT)) ++ { ++ /* Save digest from pCmd->digestOffset */ ++ mvCesaCopyFromMbuf(pReq->frags.orgDigest, ++ pCmd->pSrc, pCmd->digestOffset, pSA->digestSize); ++ ++ /* If pCmd->digestOffset is not located on the first */ ++ if(pCmd->digestOffset > (copySize - pSA->digestSize)) ++ { ++ MV_U8 digestZero[MV_CESA_MAX_DIGEST_SIZE]; ++ ++ /* Set zeros to pCmd->digestOffset (DRAM) */ ++ memset(digestZero, 0, MV_CESA_MAX_DIGEST_SIZE); ++ mvCesaCopyToMbuf(digestZero, pCmd->pSrc, pCmd->digestOffset, pSA->digestSize); ++ ++ /* Prepare dummy place for digest in SRAM */ ++ digestOffset = cesaSramVirtPtr->tempDigest - mvCesaSramAddrGet(); ++ } ++ else ++ { ++ digestOffset = pCmd->digestOffset; ++ } ++ } ++ } ++ /* Update SA in SRAM */ ++ if(cesaLastSid != sid) ++ { ++ mvCesaSramSaUpdate(sid, &pDmaDesc[i]); ++ i++; ++ } ++ ++ pReq->fragMode = MV_CESA_FRAG_MIDDLE; ++ } ++ else ++ { ++ /* Continue fragment */ ++ fixOffset = 0; ++ cryptoOffset = 0; ++ macOffset = 0; ++ if( (pCmd->pSrc->mbufSize - pReq->frags.bufOffset) <= sizeof(cesaSramVirtPtr->buf)) ++ { ++ /* Last fragment */ ++ config = pSA->config | (MV_CESA_FRAG_LAST << MV_CESA_FRAG_MODE_OFFSET); ++ pReq->fragMode = MV_CESA_FRAG_LAST; ++ copySize = pCmd->pSrc->mbufSize - pReq->frags.bufOffset; ++ ++ if( (pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) ++ { ++ macDataSize = pCmd->macLength - pReq->frags.macSize; ++ ++ /* If pCmd->digestOffset is not located on last fragment */ ++ if(pCmd->digestOffset < pReq->frags.bufOffset) ++ { ++ /* Prepare dummy place for digest in SRAM */ ++ digestOffset = cesaSramVirtPtr->tempDigest - mvCesaSramAddrGet(); ++ } ++ else ++ { ++ digestOffset = pCmd->digestOffset - pReq->frags.bufOffset; ++ } ++ pReq->frags.newDigestOffset = digestOffset; ++ macTotalLen = pCmd->macLength; ++ ++ /* HW can't calculate the Digest correctly for fragmented packets ++ * in the following cases: ++ * - MV88F5182 || ++ * - MV88F5181L when total macLength more that 16 Kbytes || ++ * - total macLength more that 64 Kbytes ++ */ ++ if( (mvCtrlModelGet() == MV_5182_DEV_ID) || ++ ( (mvCtrlModelGet() == MV_5181_DEV_ID) && ++ (mvCtrlRevGet() >= MV_5181L_A0_REV) && ++ (pCmd->macLength >= (1 << 14)) ) ) ++ { ++ return MV_TERMINATE; ++ } ++ } ++ if( (pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET) ) ++ { ++ cryptoDataSize = pCmd->cryptoLength - pReq->frags.cryptoSize; ++ } ++ ++ /* cryptoIvOffset - don't care */ ++ } ++ else ++ { ++ /* WA for MV88F5182 SHA1 and MD5 fragmentation mode */ ++ if( (mvCtrlModelGet() == MV_5182_DEV_ID) && ++ (((pSA->config & MV_CESA_MAC_MODE_MASK) == ++ (MV_CESA_MAC_MD5 << MV_CESA_MAC_MODE_OFFSET)) || ++ ((pSA->config & MV_CESA_MAC_MODE_MASK) == ++ (MV_CESA_MAC_SHA1 << MV_CESA_MAC_MODE_OFFSET))) ) ++ { ++ pReq->frags.newDigestOffset = cesaSramVirtPtr->tempDigest - mvCesaSramAddrGet(); ++ pReq->fragMode = MV_CESA_FRAG_LAST; ++ ++ return MV_TERMINATE; ++ } ++ /* Middle fragment */ ++ config = pSA->config | (MV_CESA_FRAG_MIDDLE << MV_CESA_FRAG_MODE_OFFSET); ++ copySize = sizeof(cesaSramVirtPtr->buf); ++ /* digestOffset and cryptoIvOffset - don't care */ ++ ++ /* Find fragment size */ ++ mvCesaFragSizeFind(pSA, pReq, cryptoOffset, macOffset, ++ ©Size, &cryptoDataSize, &macDataSize); ++ } ++ } ++ /********* Prepare DMA descriptors to copy from pSrc to SRAM *********/ ++ pMbuf = pCmd->pSrc; ++ i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], ++ MV_FALSE, pReq->frags.bufOffset, copySize, pCmd->skipFlush); ++ ++ /* Prepare CESA descriptor to copy from DRAM to SRAM by DMA */ ++ mvCesaSramDescrBuild(config, frag, ++ cryptoOffset + fixOffset, cryptoIvOffset + fixOffset, ++ cryptoDataSize, macOffset + fixOffset, ++ digestOffset + fixOffset, macDataSize, macTotalLen, ++ pReq, &pDmaDesc[i]); ++ i++; ++ ++ /* Add special descriptor Ownership for CPU */ ++ pDmaDesc[i].byteCnt = 0; ++ pDmaDesc[i].phySrcAdd = 0; ++ pDmaDesc[i].phyDestAdd = 0; ++ i++; ++ ++ /********* Prepare DMA descriptors to copy from SRAM to pDst *********/ ++ pMbuf = pCmd->pDst; ++ i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], ++ MV_TRUE, pReq->frags.bufOffset, copySize, pCmd->skipFlush); ++ ++ /* Next field of Last DMA descriptor must be NULL */ ++ pDmaDesc[i-1].phyNextDescPtr = 0; ++ pReq->dma[frag].pDmaLast = &pDmaDesc[i-1]; ++ mvOsCacheFlush(NULL, pReq->dma[frag].pDmaFirst, ++ i*sizeof(MV_DMA_DESC)); ++ ++ /*mvCesaDebugDescriptor(&cesaSramVirtPtr->desc[frag]);*/ ++ ++ pReq->frags.bufOffset += copySize; ++ pReq->frags.cryptoSize += cryptoDataSize; ++ pReq->frags.macSize += macDataSize; ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvCesaReqProcess - Process regular (Non-fragmented) request ++* ++* DESCRIPTION: ++* This function processes the whole (not fragmented) request ++* ++* INPUT: ++* MV_CESA_REQ* pReq - Pointer to the request in the request queue. ++* ++* RETURN: ++* MV_OK - The request is successfully passed to HW for processing. ++* Other - Failure. The request will not be processed ++* ++*******************************************************************************/ ++static MV_STATUS mvCesaReqProcess(MV_CESA_REQ* pReq) ++{ ++ MV_CESA_MBUF *pMbuf; ++ MV_DMA_DESC *pDmaDesc; ++ MV_U8 *pSramBuf; ++ int sid, i, fixOffset; ++ MV_CESA_SA *pSA; ++ MV_CESA_COMMAND *pCmd = pReq->pCmd; ++ ++ cesaStats.procCount++; ++ ++ sid = pCmd->sessionId; ++ pSA = &pCesaSAD[sid]; ++ pDmaDesc = pReq->dma[0].pDmaFirst; ++ pSramBuf = cesaSramVirtPtr->buf; ++ fixOffset = pReq->fixOffset; ++ ++/* ++ mvOsPrintf("mvCesaReqProcess: sid=%d, pSA=%p, pDmaDesc=%p, pSramBuf=%p\n", ++ sid, pSA, pDmaDesc, pSramBuf); ++*/ ++ i = 0; ++ ++ /* Crypto IV Special processing in CBC mode for Encryption direction */ ++ if( ((pSA->config & MV_CESA_OPERATION_MASK) != (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) && ++ ((pSA->config & MV_CESA_CRYPTO_MODE_MASK) == (MV_CESA_CRYPTO_CBC << MV_CESA_CRYPTO_MODE_BIT)) && ++ ((pSA->config & MV_CESA_DIRECTION_MASK) == (MV_CESA_DIR_ENCODE << MV_CESA_DIRECTION_BIT)) && ++ (pCmd->ivFromUser) ) ++ { ++ /* For Crypto Encode in CBC mode HW always takes IV from SRAM IVPointer, ++ * (not from IVBufPointer). So when ivFromUser==1, we should copy IV from user place ++ * in the buffer to SRAM IVPointer ++ */ ++ i += mvCesaDmaCopyPrepare(pCmd->pSrc, cesaSramVirtPtr->cryptoIV, &pDmaDesc[i], ++ MV_FALSE, pCmd->ivOffset, pSA->cryptoIvSize, pCmd->skipFlush); ++ } ++ ++ /* Update SA in SRAM */ ++ if(cesaLastSid != sid) ++ { ++ mvCesaSramSaUpdate(sid, &pDmaDesc[i]); ++ i++; ++ } ++ ++ /********* Prepare DMA descriptors to copy from pSrc to SRAM *********/ ++ pMbuf = pCmd->pSrc; ++ i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], ++ MV_FALSE, 0, pMbuf->mbufSize, pCmd->skipFlush); ++ ++ /* Prepare Security Accelerator descriptor to SRAM words 0 - 7 */ ++ mvCesaSramDescrBuild(pSA->config, 0, pCmd->cryptoOffset + fixOffset, ++ pCmd->ivOffset + fixOffset, pCmd->cryptoLength, ++ pCmd->macOffset + fixOffset, pCmd->digestOffset + fixOffset, ++ pCmd->macLength, pCmd->macLength, pReq, &pDmaDesc[i]); ++ i++; ++ ++ /* Add special descriptor Ownership for CPU */ ++ pDmaDesc[i].byteCnt = 0; ++ pDmaDesc[i].phySrcAdd = 0; ++ pDmaDesc[i].phyDestAdd = 0; ++ i++; ++ ++ /********* Prepare DMA descriptors to copy from SRAM to pDst *********/ ++ pMbuf = pCmd->pDst; ++ i += mvCesaDmaCopyPrepare(pMbuf, pSramBuf + fixOffset, &pDmaDesc[i], ++ MV_TRUE, 0, pMbuf->mbufSize, pCmd->skipFlush); ++ ++ /* Next field of Last DMA descriptor must be NULL */ ++ pDmaDesc[i-1].phyNextDescPtr = 0; ++ pReq->dma[0].pDmaLast = &pDmaDesc[i-1]; ++ mvOsCacheFlush(NULL, pReq->dma[0].pDmaFirst, i*sizeof(MV_DMA_DESC)); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvCesaSramDescrBuild - Set CESA descriptor in SRAM ++* ++* DESCRIPTION: ++* This function builds CESA descriptor in SRAM from all Command parameters ++* ++* ++* INPUT: ++* int chan - CESA channel uses the descriptor ++* MV_U32 config - 32 bits of WORD_0 in CESA descriptor structure ++* int cryptoOffset - Offset from the beginning of SRAM buffer where ++* data for encryption/decription is started. ++* int ivOffset - Offset of crypto IV from the SRAM base. Valid only ++* for first fragment. ++* int cryptoLength - Size (in bytes) of data for encryption/descryption ++* operation on this fragment. ++* int macOffset - Offset from the beginning of SRAM buffer where ++* data for Authentication is started ++* int digestOffset - Offset from the beginning of SRAM buffer where ++* digest is located. Valid for first and last fragments. ++* int macLength - Size (in bytes) of data for Authentication ++* operation on this fragment. ++* int macTotalLen - Toatl size (in bytes) of data for Authentication ++* operation on the whole request (packet). Valid for ++* last fragment only. ++* ++* RETURN: None ++* ++*******************************************************************************/ ++static void mvCesaSramDescrBuild(MV_U32 config, int frag, ++ int cryptoOffset, int ivOffset, int cryptoLength, ++ int macOffset, int digestOffset, int macLength, ++ int macTotalLen, MV_CESA_REQ* pReq, MV_DMA_DESC* pDmaDesc) ++{ ++ MV_CESA_DESC* pCesaDesc = &pReq->pCesaDesc[frag]; ++ MV_CESA_DESC* pSramDesc = pSramDesc = &cesaSramVirtPtr->desc; ++ MV_U16 sramBufOffset = (MV_U16)((MV_U8*)cesaSramVirtPtr->buf - mvCesaSramAddrGet()); ++ ++ pCesaDesc->config = MV_32BIT_LE(config); ++ ++ if( (config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET) ) ++ { ++ /* word 1 */ ++ pCesaDesc->cryptoSrcOffset = MV_16BIT_LE(sramBufOffset + cryptoOffset); ++ pCesaDesc->cryptoDstOffset = MV_16BIT_LE(sramBufOffset + cryptoOffset); ++ /* word 2 */ ++ pCesaDesc->cryptoDataLen = MV_16BIT_LE(cryptoLength); ++ /* word 3 */ ++ pCesaDesc->cryptoKeyOffset = MV_16BIT_LE((MV_U16)(cesaSramVirtPtr->sramSA.cryptoKey - ++ mvCesaSramAddrGet())); ++ /* word 4 */ ++ pCesaDesc->cryptoIvOffset = MV_16BIT_LE((MV_U16)(cesaSramVirtPtr->cryptoIV - ++ mvCesaSramAddrGet())); ++ pCesaDesc->cryptoIvBufOffset = MV_16BIT_LE(sramBufOffset + ivOffset); ++ } ++ ++ if( (config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) ++ { ++ /* word 5 */ ++ pCesaDesc->macSrcOffset = MV_16BIT_LE(sramBufOffset + macOffset); ++ pCesaDesc->macTotalLen = MV_16BIT_LE(macTotalLen); ++ ++ /* word 6 */ ++ pCesaDesc->macDigestOffset = MV_16BIT_LE(sramBufOffset + digestOffset); ++ pCesaDesc->macDataLen = MV_16BIT_LE(macLength); ++ ++ /* word 7 */ ++ pCesaDesc->macInnerIvOffset = MV_16BIT_LE((MV_U16)(cesaSramVirtPtr->sramSA.macInnerIV - ++ mvCesaSramAddrGet())); ++ pCesaDesc->macOuterIvOffset = MV_16BIT_LE((MV_U16)(cesaSramVirtPtr->sramSA.macOuterIV - ++ mvCesaSramAddrGet())); ++ } ++ /* Prepare DMA descriptor to CESA descriptor from DRAM to SRAM */ ++ pDmaDesc->phySrcAdd = MV_32BIT_LE(mvCesaVirtToPhys(&pReq->cesaDescBuf, pCesaDesc)); ++ pDmaDesc->phyDestAdd = MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (MV_U8*)pSramDesc)); ++ pDmaDesc->byteCnt = MV_32BIT_LE(sizeof(MV_CESA_DESC) | BIT31); ++ ++ /* flush Source buffer */ ++ mvOsCacheFlush(NULL, pCesaDesc, sizeof(MV_CESA_DESC)); ++} ++ ++/******************************************************************************* ++* mvCesaSramSaUpdate - Move required SA information to SRAM if needed. ++* ++* DESCRIPTION: ++* Copy to SRAM values of the required SA. ++* ++* ++* INPUT: ++* short sid - Session ID needs SRAM Cache update ++* MV_DMA_DESC *pDmaDesc - Pointer to DMA descriptor used to ++* copy SA values from DRAM to SRAM. ++* ++* RETURN: ++* MV_OK - Cache entry for this SA copied to SRAM. ++* MV_NO_CHANGE - Cache entry for this SA already exist in SRAM ++* ++*******************************************************************************/ ++static INLINE void mvCesaSramSaUpdate(short sid, MV_DMA_DESC *pDmaDesc) ++{ ++ MV_CESA_SA *pSA = &pCesaSAD[sid]; ++ ++ /* Prepare DMA descriptor to Copy CACHE_SA from SA database in DRAM to SRAM */ ++ pDmaDesc->byteCnt = MV_32BIT_LE(sizeof(MV_CESA_SRAM_SA) | BIT31); ++ pDmaDesc->phySrcAdd = MV_32BIT_LE(mvCesaVirtToPhys(&cesaSramSaBuf, pSA->pSramSA)); ++ pDmaDesc->phyDestAdd = ++ MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (MV_U8*)&cesaSramVirtPtr->sramSA)); ++ ++ /* Source buffer is already flushed during OpenSession*/ ++ /*mvOsCacheFlush(NULL, &pSA->sramSA, sizeof(MV_CESA_SRAM_SA));*/ ++} ++ ++/******************************************************************************* ++* mvCesaDmaCopyPrepare - prepare DMA descriptor list to copy data presented by ++* Mbuf structure from DRAM to SRAM ++* ++* DESCRIPTION: ++* ++* ++* INPUT: ++* MV_CESA_MBUF* pMbuf - pointer to Mbuf structure contains request ++* data in DRAM ++* MV_U8* pSramBuf - pointer to buffer in SRAM where data should ++* be copied to. ++* MV_DMA_DESC* pDmaDesc - pointer to first DMA descriptor for this copy. ++* The function set number of DMA descriptors needed ++* to copy the copySize bytes from Mbuf. ++* MV_BOOL isToMbuf - Copy direction. ++* MV_TRUE means copy from SRAM buffer to Mbuf in DRAM. ++* MV_FALSE means copy from Mbuf in DRAM to SRAM buffer. ++* int offset - Offset in the Mbuf structure that copy should be ++* started from. ++* int copySize - Size of data should be copied. ++* ++* RETURN: ++* int - number of DMA descriptors used for the copy. ++* ++*******************************************************************************/ ++#ifndef MV_NETBSD ++static INLINE int mvCesaDmaCopyPrepare(MV_CESA_MBUF* pMbuf, MV_U8* pSramBuf, ++ MV_DMA_DESC* pDmaDesc, MV_BOOL isToMbuf, ++ int offset, int copySize, MV_BOOL skipFlush) ++{ ++ int bufOffset, bufSize, size, frag, i; ++ MV_U8* pBuf; ++ ++ i = 0; ++ ++ /* Calculate start place for copy: fragment number and offset in the fragment */ ++ frag = mvCesaMbufOffset(pMbuf, offset, &bufOffset); ++ bufSize = pMbuf->pFrags[frag].bufSize - bufOffset; ++ pBuf = pMbuf->pFrags[frag].bufVirtPtr + bufOffset; ++ ++ /* Size accumulate total copy size */ ++ size = 0; ++ ++ /* Create DMA lists to copy mBuf from pSrc to SRAM */ ++ while(size < copySize) ++ { ++ /* Find copy size for each DMA descriptor */ ++ bufSize = MV_MIN(bufSize, (copySize - size)); ++ pDmaDesc[i].byteCnt = MV_32BIT_LE(bufSize | BIT31); ++ if(isToMbuf) ++ { ++ pDmaDesc[i].phyDestAdd = MV_32BIT_LE(mvOsIoVirtToPhy(NULL, pBuf)); ++ pDmaDesc[i].phySrcAdd = ++ MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (pSramBuf + size))); ++ /* invalidate the buffer */ ++ if(skipFlush == MV_FALSE) ++ mvOsCacheInvalidate(NULL, pBuf, bufSize); ++ } ++ else ++ { ++ pDmaDesc[i].phySrcAdd = MV_32BIT_LE(mvOsIoVirtToPhy(NULL, pBuf)); ++ pDmaDesc[i].phyDestAdd = ++ MV_32BIT_LE(mvCesaSramVirtToPhys(NULL, (pSramBuf + size))); ++ /* flush the buffer */ ++ if(skipFlush == MV_FALSE) ++ mvOsCacheFlush(NULL, pBuf, bufSize); ++ } ++ ++ /* Count number of used DMA descriptors */ ++ i++; ++ size += bufSize; ++ ++ /* go to next fragment in the Mbuf */ ++ frag++; ++ pBuf = pMbuf->pFrags[frag].bufVirtPtr; ++ bufSize = pMbuf->pFrags[frag].bufSize; ++ } ++ return i; ++} ++#else /* MV_NETBSD */ ++static int mvCesaDmaCopyPrepare(MV_CESA_MBUF* pMbuf, MV_U8* pSramBuf, ++ MV_DMA_DESC* pDmaDesc, MV_BOOL isToMbuf, ++ int offset, int copySize, MV_BOOL skipFlush) ++{ ++ int bufOffset, bufSize, thisSize, size, frag, i; ++ MV_ULONG bufPhys, sramPhys; ++ MV_U8* pBuf; ++ ++ /* ++ * Calculate start place for copy: fragment number and offset in ++ * the fragment ++ */ ++ frag = mvCesaMbufOffset(pMbuf, offset, &bufOffset); ++ ++ /* ++ * Get SRAM physical address only once. We can update it in-place ++ * as we build the descriptor chain. ++ */ ++ sramPhys = mvCesaSramVirtToPhys(NULL, pSramBuf); ++ ++ /* ++ * 'size' accumulates total copy size, 'i' counts desccriptors. ++ */ ++ size = i = 0; ++ ++ /* Create DMA lists to copy mBuf from pSrc to SRAM */ ++ while (size < copySize) { ++ /* ++ * Calculate # of bytes to copy from the current fragment, ++ * and the pointer to the start of data ++ */ ++ bufSize = pMbuf->pFrags[frag].bufSize - bufOffset; ++ pBuf = pMbuf->pFrags[frag].bufVirtPtr + bufOffset; ++ bufOffset = 0; /* First frag may be non-zero */ ++ frag++; ++ ++ /* ++ * As long as there is data in the current fragment... ++ */ ++ while (bufSize > 0) { ++ /* ++ * Ensure we don't cross an MMU page boundary. ++ * XXX: This is NetBSD-specific, but it is a ++ * quick and dirty way to fix the problem. ++ * A true HAL would rely on the OS-specific ++ * driver to do this... ++ */ ++ thisSize = PAGE_SIZE - ++ (((MV_ULONG)pBuf) & (PAGE_SIZE - 1)); ++ thisSize = MV_MIN(bufSize, thisSize); ++ /* ++ * Make sure we don't copy more than requested ++ */ ++ if (thisSize > (copySize - size)) { ++ thisSize = copySize - size; ++ bufSize = 0; ++ } ++ ++ /* ++ * Physicall address of this fragment ++ */ ++ bufPhys = MV_32BIT_LE(mvOsIoVirtToPhy(NULL, pBuf)); ++ ++ /* ++ * Set up the descriptor ++ */ ++ pDmaDesc[i].byteCnt = MV_32BIT_LE(thisSize | BIT31); ++ if(isToMbuf) { ++ pDmaDesc[i].phyDestAdd = bufPhys; ++ pDmaDesc[i].phySrcAdd = MV_32BIT_LE(sramPhys); ++ /* invalidate the buffer */ ++ if(skipFlush == MV_FALSE) ++ mvOsCacheInvalidate(NULL, pBuf, thisSize); ++ } else { ++ pDmaDesc[i].phySrcAdd = bufPhys; ++ pDmaDesc[i].phyDestAdd = MV_32BIT_LE(sramPhys); ++ /* flush the buffer */ ++ if(skipFlush == MV_FALSE) ++ mvOsCacheFlush(NULL, pBuf, thisSize); ++ } ++ ++ pDmaDesc[i].phyNextDescPtr = ++ MV_32BIT_LE(mvOsIoVirtToPhy(NULL,(&pDmaDesc[i+1]))); ++ ++ /* flush the DMA desc */ ++ mvOsCacheFlush(NULL, &pDmaDesc[i], sizeof(MV_DMA_DESC)); ++ ++ /* Update state */ ++ bufSize -= thisSize; ++ sramPhys += thisSize; ++ pBuf += thisSize; ++ size += thisSize; ++ i++; ++ } ++ } ++ ++ return i; ++} ++#endif /* MV_NETBSD */ ++/******************************************************************************* ++* mvCesaHmacIvGet - Calculate Inner and Outter values from HMAC key ++* ++* DESCRIPTION: ++* This function calculate Inner and Outer values used for HMAC algorithm. ++* This operation allows improve performance fro the whole HMAC processing. ++* ++* INPUT: ++* MV_CESA_MAC_MODE macMode - Authentication mode: HMAC_MD5 or HMAC_SHA1. ++* unsigned char key[] - Pointer to HMAC key. ++* int keyLength - Size of HMAC key (maximum 64 bytes) ++* ++* OUTPUT: ++* unsigned char innerIV[] - HASH(key^inner) ++* unsigned char outerIV[] - HASH(key^outter) ++* ++* RETURN: None ++* ++*******************************************************************************/ ++static void mvCesaHmacIvGet(MV_CESA_MAC_MODE macMode, unsigned char key[], int keyLength, ++ unsigned char innerIV[], unsigned char outerIV[]) ++{ ++ unsigned char inner[MV_CESA_MAX_MAC_KEY_LENGTH]; ++ unsigned char outer[MV_CESA_MAX_MAC_KEY_LENGTH]; ++ int i, digestSize = 0; ++#if defined(MV_CPU_LE) || defined(MV_PPC) ++ MV_U32 swapped32, val32, *pVal32; ++#endif ++ for(i=0; ipFrags[frag].bufVirtPtr + fragOffset; ++ size = pMbuf->pFrags[frag].bufSize - fragOffset; ++ ++ /* Complete Inner part */ ++ while(macLeftSize > 0) ++ { ++ if(macLeftSize <= size) ++ { ++ mvSHA1Update(&ctx, pData, macLeftSize); ++ break; ++ } ++ mvSHA1Update(&ctx, pData, size); ++ macLeftSize -= size; ++ frag++; ++ pData = pMbuf->pFrags[frag].bufVirtPtr; ++ size = pMbuf->pFrags[frag].bufSize; ++ } ++ mvSHA1Final(pDigest, &ctx); ++/* ++ mvOsPrintf("mvCesaFragSha1Complete: pOuterIV=%p, macLeftSize=%d, macTotalSize=%d\n", ++ pOuterIV, macLeftSize, macTotalSize); ++ mvDebugMemDump(pDigest, MV_CESA_SHA1_DIGEST_SIZE, 1); ++*/ ++ ++ if(pOuterIV != NULL) ++ { ++ /* If HMAC - Complete Outer part */ ++ for(i=0; ipFrags[frag].bufVirtPtr + fragOffset; ++ size = pMbuf->pFrags[frag].bufSize - fragOffset; ++ ++ /* Complete Inner part */ ++ while(macLeftSize > 0) ++ { ++ if(macLeftSize <= size) ++ { ++ mvMD5Update(&ctx, pData, macLeftSize); ++ break; ++ } ++ mvMD5Update(&ctx, pData, size); ++ macLeftSize -= size; ++ frag++; ++ pData = pMbuf->pFrags[frag].bufVirtPtr; ++ size = pMbuf->pFrags[frag].bufSize; ++ } ++ mvMD5Final(pDigest, &ctx); ++ ++/* ++ mvOsPrintf("mvCesaFragMd5Complete: pOuterIV=%p, macLeftSize=%d, macTotalSize=%d\n", ++ pOuterIV, macLeftSize, macTotalSize); ++ mvDebugMemDump(pDigest, MV_CESA_MD5_DIGEST_SIZE, 1); ++*/ ++ if(pOuterIV != NULL) ++ { ++ /* Complete Outer part */ ++ for(i=0; ipCmd; ++ MV_U8* pDigest; ++ MV_CESA_MAC_MODE macMode; ++ MV_U8* pOuterIV = NULL; ++ ++ /* Copy data from Source fragment to Destination */ ++ if(pCmd->pSrc != pCmd->pDst) ++ { ++ mvCesaMbufCopy(pCmd->pDst, pReq->frags.bufOffset, ++ pCmd->pSrc, pReq->frags.bufOffset, macDataSize); ++ } ++ ++/* ++ mvCesaCopyFromMbuf(cesaSramVirtPtr->buf[0], pCmd->pSrc, pReq->frags.bufOffset, macDataSize); ++ mvCesaCopyToMbuf(cesaSramVirtPtr->buf[0], pCmd->pDst, pReq->frags.bufOffset, macDataSize); ++*/ ++ pDigest = (mvCesaSramAddrGet() + pReq->frags.newDigestOffset); ++ ++ macMode = (pSA->config & MV_CESA_MAC_MODE_MASK) >> MV_CESA_MAC_MODE_OFFSET; ++/* ++ mvOsPrintf("macDataSize=%d, macLength=%d, digestOffset=%d, macMode=%d\n", ++ macDataSize, pCmd->macLength, pCmd->digestOffset, macMode); ++*/ ++ switch(macMode) ++ { ++ case MV_CESA_MAC_HMAC_MD5: ++ pOuterIV = pSA->pSramSA->macOuterIV; ++ ++ case MV_CESA_MAC_MD5: ++ mvCesaFragMd5Complete(pCmd->pDst, pReq->frags.bufOffset, pOuterIV, ++ macDataSize, pCmd->macLength, pDigest); ++ break; ++ ++ case MV_CESA_MAC_HMAC_SHA1: ++ pOuterIV = pSA->pSramSA->macOuterIV; ++ ++ case MV_CESA_MAC_SHA1: ++ mvCesaFragSha1Complete(pCmd->pDst, pReq->frags.bufOffset, pOuterIV, ++ macDataSize, pCmd->macLength, pDigest); ++ break; ++ ++ default: ++ mvOsPrintf("mvCesaFragAuthComplete: Unexpected macMode %d\n", macMode); ++ return MV_BAD_PARAM; ++ } ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCesaCtrModeInit - ++* ++* DESCRIPTION: ++* ++* ++* INPUT: NONE ++* ++* ++* RETURN: ++* MV_CESA_COMMAND* ++* ++*******************************************************************************/ ++static MV_CESA_COMMAND* mvCesaCtrModeInit(void) ++{ ++ MV_CESA_MBUF *pMbuf; ++ MV_U8 *pBuf; ++ MV_CESA_COMMAND *pCmd; ++ ++ pBuf = mvOsMalloc(sizeof(MV_CESA_COMMAND) + ++ sizeof(MV_CESA_MBUF) + sizeof(MV_BUF_INFO) + 100); ++ if(pBuf == NULL) ++ { ++ mvOsPrintf("mvCesaSessionOpen: Can't allocate %u bytes for CTR Mode\n", ++ sizeof(MV_CESA_COMMAND) + sizeof(MV_CESA_MBUF) + sizeof(MV_BUF_INFO) ); ++ return NULL; ++ } ++ pCmd = (MV_CESA_COMMAND*)pBuf; ++ pBuf += sizeof(MV_CESA_COMMAND); ++ ++ pMbuf = (MV_CESA_MBUF*)pBuf; ++ pBuf += sizeof(MV_CESA_MBUF); ++ ++ pMbuf->pFrags = (MV_BUF_INFO*)pBuf; ++ ++ pMbuf->numFrags = 1; ++ pCmd->pSrc = pMbuf; ++ pCmd->pDst = pMbuf; ++/* ++ mvOsPrintf("CtrModeInit: pCmd=%p, pSrc=%p, pDst=%p, pFrags=%p\n", ++ pCmd, pCmd->pSrc, pCmd->pDst, ++ pMbuf->pFrags); ++*/ ++ return pCmd; ++} ++ ++/******************************************************************************* ++* mvCesaCtrModePrepare - ++* ++* DESCRIPTION: ++* ++* ++* INPUT: ++* MV_CESA_COMMAND *pCtrModeCmd, MV_CESA_COMMAND *pCmd ++* ++* RETURN: ++* MV_STATUS ++* ++*******************************************************************************/ ++static MV_STATUS mvCesaCtrModePrepare(MV_CESA_COMMAND *pCtrModeCmd, MV_CESA_COMMAND *pCmd) ++{ ++ MV_CESA_MBUF *pMbuf; ++ MV_U8 *pBuf, *pIV; ++ MV_U32 counter, *pCounter; ++ int cryptoSize = MV_ALIGN_UP(pCmd->cryptoLength, MV_CESA_AES_BLOCK_SIZE); ++/* ++ mvOsPrintf("CtrModePrepare: pCmd=%p, pCtrSrc=%p, pCtrDst=%p, pOrgCmd=%p, pOrgSrc=%p, pOrgDst=%p\n", ++ pCmd, pCmd->pSrc, pCmd->pDst, ++ pCtrModeCmd, pCtrModeCmd->pSrc, pCtrModeCmd->pDst); ++*/ ++ pMbuf = pCtrModeCmd->pSrc; ++ ++ /* Allocate buffer for Key stream */ ++ pBuf = mvOsIoCachedMalloc(cesaOsHandle,cryptoSize, ++ &pMbuf->pFrags[0].bufPhysAddr, ++ &pMbuf->pFrags[0].memHandle); ++ if(pBuf == NULL) ++ { ++ mvOsPrintf("mvCesaCtrModePrepare: Can't allocate %d bytes\n", cryptoSize); ++ return MV_OUT_OF_CPU_MEM; ++ } ++ memset(pBuf, 0, cryptoSize); ++ mvOsCacheFlush(NULL, pBuf, cryptoSize); ++ ++ pMbuf->pFrags[0].bufVirtPtr = pBuf; ++ pMbuf->mbufSize = cryptoSize; ++ pMbuf->pFrags[0].bufSize = cryptoSize; ++ ++ pCtrModeCmd->pReqPrv = pCmd->pReqPrv; ++ pCtrModeCmd->sessionId = pCmd->sessionId; ++ ++ /* ivFromUser and ivOffset are don't care */ ++ pCtrModeCmd->cryptoOffset = 0; ++ pCtrModeCmd->cryptoLength = cryptoSize; ++ ++ /* digestOffset, macOffset and macLength are don't care */ ++ ++ mvCesaCopyFromMbuf(pBuf, pCmd->pSrc, pCmd->ivOffset, MV_CESA_AES_BLOCK_SIZE); ++ pCounter = (MV_U32*)(pBuf + (MV_CESA_AES_BLOCK_SIZE - sizeof(counter))); ++ counter = *pCounter; ++ counter = MV_32BIT_BE(counter); ++ pIV = pBuf; ++ cryptoSize -= MV_CESA_AES_BLOCK_SIZE; ++ ++ /* fill key stream */ ++ while(cryptoSize > 0) ++ { ++ pBuf += MV_CESA_AES_BLOCK_SIZE; ++ memcpy(pBuf, pIV, MV_CESA_AES_BLOCK_SIZE - sizeof(counter)); ++ pCounter = (MV_U32*)(pBuf + (MV_CESA_AES_BLOCK_SIZE - sizeof(counter))); ++ counter++; ++ *pCounter = MV_32BIT_BE(counter); ++ cryptoSize -= MV_CESA_AES_BLOCK_SIZE; ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCesaCtrModeComplete - ++* ++* DESCRIPTION: ++* ++* ++* INPUT: ++* MV_CESA_COMMAND *pOrgCmd, MV_CESA_COMMAND *pCmd ++* ++* RETURN: ++* MV_STATUS ++* ++*******************************************************************************/ ++static MV_STATUS mvCesaCtrModeComplete(MV_CESA_COMMAND *pOrgCmd, MV_CESA_COMMAND *pCmd) ++{ ++ int srcFrag, dstFrag, srcOffset, dstOffset, keyOffset, srcSize, dstSize; ++ int cryptoSize = pCmd->cryptoLength; ++ MV_U8 *pSrc, *pDst, *pKey; ++ MV_STATUS status = MV_OK; ++/* ++ mvOsPrintf("CtrModeComplete: pCmd=%p, pCtrSrc=%p, pCtrDst=%p, pOrgCmd=%p, pOrgSrc=%p, pOrgDst=%p\n", ++ pCmd, pCmd->pSrc, pCmd->pDst, ++ pOrgCmd, pOrgCmd->pSrc, pOrgCmd->pDst); ++*/ ++ /* XOR source data with key stream to destination data */ ++ pKey = pCmd->pDst->pFrags[0].bufVirtPtr; ++ keyOffset = 0; ++ ++ if( (pOrgCmd->pSrc != pOrgCmd->pDst) && ++ (pOrgCmd->cryptoOffset > 0) ) ++ { ++ /* Copy Prefix from source buffer to destination buffer */ ++ ++ status = mvCesaMbufCopy(pOrgCmd->pDst, 0, ++ pOrgCmd->pSrc, 0, pOrgCmd->cryptoOffset); ++/* ++ status = mvCesaCopyFromMbuf(tempBuf, pOrgCmd->pSrc, ++ 0, pOrgCmd->cryptoOffset); ++ status = mvCesaCopyToMbuf(tempBuf, pOrgCmd->pDst, ++ 0, pOrgCmd->cryptoOffset); ++*/ ++ } ++ ++ srcFrag = mvCesaMbufOffset(pOrgCmd->pSrc, pOrgCmd->cryptoOffset, &srcOffset); ++ pSrc = pOrgCmd->pSrc->pFrags[srcFrag].bufVirtPtr; ++ srcSize = pOrgCmd->pSrc->pFrags[srcFrag].bufSize; ++ ++ dstFrag = mvCesaMbufOffset(pOrgCmd->pDst, pOrgCmd->cryptoOffset, &dstOffset); ++ pDst = pOrgCmd->pDst->pFrags[dstFrag].bufVirtPtr; ++ dstSize = pOrgCmd->pDst->pFrags[dstFrag].bufSize; ++ ++ while(cryptoSize > 0) ++ { ++ pDst[dstOffset] = (pSrc[srcOffset] ^ pKey[keyOffset]); ++ ++ cryptoSize--; ++ dstOffset++; ++ srcOffset++; ++ keyOffset++; ++ ++ if(srcOffset >= srcSize) ++ { ++ srcFrag++; ++ srcOffset = 0; ++ pSrc = pOrgCmd->pSrc->pFrags[srcFrag].bufVirtPtr; ++ srcSize = pOrgCmd->pSrc->pFrags[srcFrag].bufSize; ++ } ++ ++ if(dstOffset >= dstSize) ++ { ++ dstFrag++; ++ dstOffset = 0; ++ pDst = pOrgCmd->pDst->pFrags[dstFrag].bufVirtPtr; ++ dstSize = pOrgCmd->pDst->pFrags[dstFrag].bufSize; ++ } ++ } ++ ++ if(pOrgCmd->pSrc != pOrgCmd->pDst) ++ { ++ /* Copy Suffix from source buffer to destination buffer */ ++ srcOffset = pOrgCmd->cryptoOffset + pOrgCmd->cryptoLength; ++ ++ if( (pOrgCmd->pDst->mbufSize - srcOffset) > 0) ++ { ++ status = mvCesaMbufCopy(pOrgCmd->pDst, srcOffset, ++ pOrgCmd->pSrc, srcOffset, ++ pOrgCmd->pDst->mbufSize - srcOffset); ++ } ++ ++/* ++ status = mvCesaCopyFromMbuf(tempBuf, pOrgCmd->pSrc, ++ srcOffset, pOrgCmd->pSrc->mbufSize - srcOffset); ++ status = mvCesaCopyToMbuf(tempBuf, pOrgCmd->pDst, ++ srcOffset, pOrgCmd->pDst->mbufSize - srcOffset); ++*/ ++ } ++ ++ /* Free buffer used for Key stream */ ++ mvOsIoCachedFree(cesaOsHandle,pCmd->pDst->pFrags[0].bufSize, ++ pCmd->pDst->pFrags[0].bufPhysAddr, ++ pCmd->pDst->pFrags[0].bufVirtPtr, ++ pCmd->pDst->pFrags[0].memHandle); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCesaCtrModeFinish - ++* ++* DESCRIPTION: ++* ++* ++* INPUT: ++* MV_CESA_COMMAND* pCmd ++* ++* RETURN: ++* MV_STATUS ++* ++*******************************************************************************/ ++static void mvCesaCtrModeFinish(MV_CESA_COMMAND* pCmd) ++{ ++ mvOsFree(pCmd); ++} ++ ++/******************************************************************************* ++* mvCesaParamCheck - ++* ++* DESCRIPTION: ++* ++* ++* INPUT: ++* MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, MV_U8* pFixOffset ++* ++* RETURN: ++* MV_STATUS ++* ++*******************************************************************************/ ++static MV_STATUS mvCesaParamCheck(MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, ++ MV_U8* pFixOffset) ++{ ++ MV_U8 fixOffset = 0xFF; ++ ++ /* Check AUTH operation parameters */ ++ if( ((pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET)) ) ++ { ++ /* MAC offset should be at least 4 byte aligned */ ++ if( MV_IS_NOT_ALIGN(pCmd->macOffset, 4) ) ++ { ++ mvOsPrintf("mvCesaAction: macOffset %d must be 4 byte aligned\n", ++ pCmd->macOffset); ++ return MV_BAD_PARAM; ++ } ++ /* Digest offset must be 4 byte aligned */ ++ if( MV_IS_NOT_ALIGN(pCmd->digestOffset, 4) ) ++ { ++ mvOsPrintf("mvCesaAction: digestOffset %d must be 4 byte aligned\n", ++ pCmd->digestOffset); ++ return MV_BAD_PARAM; ++ } ++ /* In addition all offsets should be the same alignment: 8 or 4 */ ++ if(fixOffset == 0xFF) ++ { ++ fixOffset = (pCmd->macOffset % 8); ++ } ++ else ++ { ++ if( (pCmd->macOffset % 8) != fixOffset) ++ { ++ mvOsPrintf("mvCesaAction: macOffset %d mod 8 must be equal %d\n", ++ pCmd->macOffset, fixOffset); ++ return MV_BAD_PARAM; ++ } ++ } ++ if( (pCmd->digestOffset % 8) != fixOffset) ++ { ++ mvOsPrintf("mvCesaAction: digestOffset %d mod 8 must be equal %d\n", ++ pCmd->digestOffset, fixOffset); ++ return MV_BAD_PARAM; ++ } ++ } ++ /* Check CRYPTO operation parameters */ ++ if( ((pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) ) ++ { ++ /* CryptoOffset should be at least 4 byte aligned */ ++ if( MV_IS_NOT_ALIGN(pCmd->cryptoOffset, 4) ) ++ { ++ mvOsPrintf("CesaAction: cryptoOffset=%d must be 4 byte aligned\n", ++ pCmd->cryptoOffset); ++ return MV_BAD_PARAM; ++ } ++ /* cryptoLength should be the whole number of blocks */ ++ if( MV_IS_NOT_ALIGN(pCmd->cryptoLength, pSA->cryptoBlockSize) ) ++ { ++ mvOsPrintf("mvCesaAction: cryptoLength=%d must be %d byte aligned\n", ++ pCmd->cryptoLength, pSA->cryptoBlockSize); ++ return MV_BAD_PARAM; ++ } ++ if(fixOffset == 0xFF) ++ { ++ fixOffset = (pCmd->cryptoOffset % 8); ++ } ++ else ++ { ++ /* In addition all offsets should be the same alignment: 8 or 4 */ ++ if( (pCmd->cryptoOffset % 8) != fixOffset) ++ { ++ mvOsPrintf("mvCesaAction: cryptoOffset %d mod 8 must be equal %d \n", ++ pCmd->cryptoOffset, fixOffset); ++ return MV_BAD_PARAM; ++ } ++ } ++ ++ /* check for CBC mode */ ++ if(pSA->cryptoIvSize > 0) ++ { ++ /* cryptoIV must not be part of CryptoLength */ ++ if( ((pCmd->ivOffset + pSA->cryptoIvSize) > pCmd->cryptoOffset) && ++ (pCmd->ivOffset < (pCmd->cryptoOffset + pCmd->cryptoLength)) ) ++ { ++ mvOsPrintf("mvCesaFragParamCheck: cryptoIvOffset (%d) is part of cryptoLength (%d+%d)\n", ++ pCmd->ivOffset, pCmd->macOffset, pCmd->macLength); ++ return MV_BAD_PARAM; ++ } ++ ++ /* ivOffset must be 4 byte aligned */ ++ if( MV_IS_NOT_ALIGN(pCmd->ivOffset, 4) ) ++ { ++ mvOsPrintf("CesaAction: ivOffset=%d must be 4 byte aligned\n", ++ pCmd->ivOffset); ++ return MV_BAD_PARAM; ++ } ++ /* In addition all offsets should be the same alignment: 8 or 4 */ ++ if( (pCmd->ivOffset % 8) != fixOffset) ++ { ++ mvOsPrintf("mvCesaAction: ivOffset %d mod 8 must be %d\n", ++ pCmd->ivOffset, fixOffset); ++ return MV_BAD_PARAM; ++ } ++ } ++ } ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCesaFragParamCheck - ++* ++* DESCRIPTION: ++* ++* ++* INPUT: ++* MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd ++* ++* RETURN: ++* MV_STATUS ++* ++*******************************************************************************/ ++static MV_STATUS mvCesaFragParamCheck(MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd) ++{ ++ int offset; ++ ++ if( ((pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET)) ) ++ { ++ /* macOffset must be less that SRAM buffer size */ ++ if(pCmd->macOffset > (sizeof(cesaSramVirtPtr->buf) - MV_CESA_AUTH_BLOCK_SIZE)) ++ { ++ mvOsPrintf("mvCesaFragParamCheck: macOffset is too large (%d)\n", ++ pCmd->macOffset); ++ return MV_BAD_PARAM; ++ } ++ /* macOffset+macSize must be more than mbufSize - SRAM buffer size */ ++ if( ((pCmd->macOffset + pCmd->macLength) > pCmd->pSrc->mbufSize) || ++ ((pCmd->pSrc->mbufSize - (pCmd->macOffset + pCmd->macLength)) >= ++ sizeof(cesaSramVirtPtr->buf)) ) ++ { ++ mvOsPrintf("mvCesaFragParamCheck: macLength is too large (%d), mbufSize=%d\n", ++ pCmd->macLength, pCmd->pSrc->mbufSize); ++ return MV_BAD_PARAM; ++ } ++ } ++ ++ if( ((pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET)) ) ++ { ++ /* cryptoOffset must be less that SRAM buffer size */ ++ /* 4 for possible fixOffset */ ++ if( (pCmd->cryptoOffset + 4) > (sizeof(cesaSramVirtPtr->buf) - pSA->cryptoBlockSize)) ++ { ++ mvOsPrintf("mvCesaFragParamCheck: cryptoOffset is too large (%d)\n", ++ pCmd->cryptoOffset); ++ return MV_BAD_PARAM; ++ } ++ ++ /* cryptoOffset+cryptoSize must be more than mbufSize - SRAM buffer size */ ++ if( ((pCmd->cryptoOffset + pCmd->cryptoLength) > pCmd->pSrc->mbufSize) || ++ ((pCmd->pSrc->mbufSize - (pCmd->cryptoOffset + pCmd->cryptoLength)) >= ++ (sizeof(cesaSramVirtPtr->buf) - pSA->cryptoBlockSize)) ) ++ { ++ mvOsPrintf("mvCesaFragParamCheck: cryptoLength is too large (%d), mbufSize=%d\n", ++ pCmd->cryptoLength, pCmd->pSrc->mbufSize); ++ return MV_BAD_PARAM; ++ } ++ } ++ ++ /* When MAC_THEN_CRYPTO or CRYPTO_THEN_MAC */ ++ if( ((pSA->config & MV_CESA_OPERATION_MASK) == ++ (MV_CESA_MAC_THEN_CRYPTO << MV_CESA_OPERATION_OFFSET)) || ++ ((pSA->config & MV_CESA_OPERATION_MASK) == ++ (MV_CESA_CRYPTO_THEN_MAC << MV_CESA_OPERATION_OFFSET)) ) ++ { ++ if( (mvCtrlModelGet() == MV_5182_DEV_ID) || ++ ( (mvCtrlModelGet() == MV_5181_DEV_ID) && ++ (mvCtrlRevGet() >= MV_5181L_A0_REV) && ++ (pCmd->macLength >= (1 << 14)) ) ) ++ { ++ return MV_NOT_ALLOWED; ++ } ++ ++ /* abs(cryptoOffset-macOffset) must be aligned cryptoBlockSize */ ++ if(pCmd->cryptoOffset > pCmd->macOffset) ++ { ++ offset = pCmd->cryptoOffset - pCmd->macOffset; ++ } ++ else ++ { ++ offset = pCmd->macOffset - pCmd->cryptoOffset; ++ } ++ ++ if( MV_IS_NOT_ALIGN(offset, pSA->cryptoBlockSize) ) ++ { ++/* ++ mvOsPrintf("mvCesaFragParamCheck: (cryptoOffset - macOffset) must be %d byte aligned\n", ++ pSA->cryptoBlockSize); ++*/ ++ return MV_NOT_ALLOWED; ++ } ++ /* Digest must not be part of CryptoLength */ ++ if( ((pCmd->digestOffset + pSA->digestSize) > pCmd->cryptoOffset) && ++ (pCmd->digestOffset < (pCmd->cryptoOffset + pCmd->cryptoLength)) ) ++ { ++/* ++ mvOsPrintf("mvCesaFragParamCheck: digestOffset (%d) is part of cryptoLength (%d+%d)\n", ++ pCmd->digestOffset, pCmd->cryptoOffset, pCmd->cryptoLength); ++*/ ++ return MV_NOT_ALLOWED; ++ } ++ } ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCesaFragSizeFind - ++* ++* DESCRIPTION: ++* ++* ++* INPUT: ++* MV_CESA_SA* pSA, MV_CESA_COMMAND *pCmd, ++* int cryptoOffset, int macOffset, ++* ++* OUTPUT: ++* int* pCopySize, int* pCryptoDataSize, int* pMacDataSize ++* ++* RETURN: ++* MV_STATUS ++* ++*******************************************************************************/ ++static void mvCesaFragSizeFind(MV_CESA_SA* pSA, MV_CESA_REQ* pReq, ++ int cryptoOffset, int macOffset, ++ int* pCopySize, int* pCryptoDataSize, int* pMacDataSize) ++{ ++ MV_CESA_COMMAND *pCmd = pReq->pCmd; ++ int cryptoDataSize, macDataSize, copySize; ++ ++ cryptoDataSize = macDataSize = 0; ++ copySize = *pCopySize; ++ ++ if( (pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_MAC_ONLY << MV_CESA_OPERATION_OFFSET) ) ++ { ++ cryptoDataSize = MV_MIN( (copySize - cryptoOffset), ++ (pCmd->cryptoLength - (pReq->frags.cryptoSize + 1)) ); ++ ++ /* cryptoSize for each fragment must be the whole number of blocksSize */ ++ if( MV_IS_NOT_ALIGN(cryptoDataSize, pSA->cryptoBlockSize) ) ++ { ++ cryptoDataSize = MV_ALIGN_DOWN(cryptoDataSize, pSA->cryptoBlockSize); ++ copySize = cryptoOffset + cryptoDataSize; ++ } ++ } ++ if( (pSA->config & MV_CESA_OPERATION_MASK) != ++ (MV_CESA_CRYPTO_ONLY << MV_CESA_OPERATION_OFFSET) ) ++ { ++ macDataSize = MV_MIN( (copySize - macOffset), ++ (pCmd->macLength - (pReq->frags.macSize + 1))); ++ ++ /* macSize for each fragment (except last) must be the whole number of blocksSize */ ++ if( MV_IS_NOT_ALIGN(macDataSize, MV_CESA_AUTH_BLOCK_SIZE) ) ++ { ++ macDataSize = MV_ALIGN_DOWN(macDataSize, MV_CESA_AUTH_BLOCK_SIZE); ++ copySize = macOffset + macDataSize; ++ } ++ cryptoDataSize = copySize - cryptoOffset; ++ } ++ *pCopySize = copySize; ++ ++ if(pCryptoDataSize != NULL) ++ *pCryptoDataSize = cryptoDataSize; ++ ++ if(pMacDataSize != NULL) ++ *pMacDataSize = macDataSize; ++} +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/cesa/mvCesa.h linux-3.1.4/crypto/ocf/kirkwood/cesa/mvCesa.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/cesa/mvCesa.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/cesa/mvCesa.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,412 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++/******************************************************************************* ++* mvCesa.h - Header File for Cryptographic Engines and Security Accelerator ++* ++* DESCRIPTION: ++* This header file contains macros typedefs and function declaration for ++* the Marvell Cryptographic Engines and Security Accelerator. ++* ++*******************************************************************************/ ++ ++#ifndef __mvCesa_h__ ++#define __mvCesa_h__ ++ ++#include "mvOs.h" ++#include "mvCommon.h" ++#include "mvDebug.h" ++ ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++ ++#include "cesa/mvMD5.h" ++#include "cesa/mvSHA1.h" ++ ++#include "cesa/mvCesa.h" ++#include "cesa/AES/mvAes.h" ++#include "mvSysHwConfig.h" ++ ++#ifdef MV_INCLUDE_IDMA ++#include "idma/mvIdma.h" ++#include "idma/mvIdmaRegs.h" ++#else ++/* Redefine MV_DMA_DESC structure */ ++typedef struct _mvDmaDesc ++{ ++ MV_U32 byteCnt; /* The total number of bytes to transfer */ ++ MV_U32 phySrcAdd; /* The physical source address */ ++ MV_U32 phyDestAdd; /* The physical destination address */ ++ MV_U32 phyNextDescPtr; /* If we are using chain mode DMA transfer, */ ++ /* then this pointer should point to the */ ++ /* physical address of the next descriptor, */ ++ /* otherwise it should be NULL. */ ++}MV_DMA_DESC; ++#endif /* MV_INCLUDE_IDMA */ ++ ++#include "cesa/mvCesaRegs.h" ++ ++#define MV_CESA_AUTH_BLOCK_SIZE 64 /* bytes */ ++ ++#define MV_CESA_MD5_DIGEST_SIZE 16 /* bytes */ ++#define MV_CESA_SHA1_DIGEST_SIZE 20 /* bytes */ ++ ++#define MV_CESA_MAX_DIGEST_SIZE MV_CESA_SHA1_DIGEST_SIZE ++ ++#define MV_CESA_DES_KEY_LENGTH 8 /* bytes = 64 bits */ ++#define MV_CESA_3DES_KEY_LENGTH 24 /* bytes = 192 bits */ ++#define MV_CESA_AES_128_KEY_LENGTH 16 /* bytes = 128 bits */ ++#define MV_CESA_AES_192_KEY_LENGTH 24 /* bytes = 192 bits */ ++#define MV_CESA_AES_256_KEY_LENGTH 32 /* bytes = 256 bits */ ++ ++#define MV_CESA_MAX_CRYPTO_KEY_LENGTH MV_CESA_AES_256_KEY_LENGTH ++ ++#define MV_CESA_DES_BLOCK_SIZE 8 /* bytes = 64 bits */ ++#define MV_CESA_3DES_BLOCK_SIZE 8 /* bytes = 64 bits */ ++ ++#define MV_CESA_AES_BLOCK_SIZE 16 /* bytes = 128 bits */ ++ ++#define MV_CESA_MAX_IV_LENGTH MV_CESA_AES_BLOCK_SIZE ++ ++#define MV_CESA_MAX_MAC_KEY_LENGTH 64 /* bytes */ ++ ++typedef struct ++{ ++ MV_U8 cryptoKey[MV_CESA_MAX_CRYPTO_KEY_LENGTH]; ++ MV_U8 macKey[MV_CESA_MAX_MAC_KEY_LENGTH]; ++ MV_CESA_OPERATION operation; ++ MV_CESA_DIRECTION direction; ++ MV_CESA_CRYPTO_ALG cryptoAlgorithm; ++ MV_CESA_CRYPTO_MODE cryptoMode; ++ MV_U8 cryptoKeyLength; ++ MV_CESA_MAC_MODE macMode; ++ MV_U8 macKeyLength; ++ MV_U8 digestSize; ++ ++} MV_CESA_OPEN_SESSION; ++ ++typedef struct ++{ ++ MV_BUF_INFO *pFrags; ++ MV_U16 numFrags; ++ MV_U16 mbufSize; ++ ++} MV_CESA_MBUF; ++ ++typedef struct ++{ ++ void* pReqPrv; /* instead of reqId */ ++ MV_U32 retCode; ++ MV_16 sessionId; ++ ++} MV_CESA_RESULT; ++ ++typedef void (*MV_CESA_CALLBACK) (MV_CESA_RESULT* pResult); ++ ++ ++typedef struct ++{ ++ void* pReqPrv; /* instead of reqId */ ++ MV_CESA_MBUF* pSrc; ++ MV_CESA_MBUF* pDst; ++ MV_CESA_CALLBACK* pFuncCB; ++ MV_16 sessionId; ++ MV_U16 ivFromUser; ++ MV_U16 ivOffset; ++ MV_U16 cryptoOffset; ++ MV_U16 cryptoLength; ++ MV_U16 digestOffset; ++ MV_U16 macOffset; ++ MV_U16 macLength; ++ MV_BOOL skipFlush; ++} MV_CESA_COMMAND; ++ ++ ++ ++MV_STATUS mvCesaHalInit (int numOfSession, int queueDepth, char* pSramBase, MV_U32 cryptEngBase, void *osHandle); ++MV_STATUS mvCesaFinish (void); ++MV_STATUS mvCesaSessionOpen(MV_CESA_OPEN_SESSION *pSession, short* pSid); ++MV_STATUS mvCesaSessionClose(short sid); ++MV_STATUS mvCesaCryptoIvSet(MV_U8* pIV, int ivSize); ++ ++MV_STATUS mvCesaAction (MV_CESA_COMMAND* pCmd); ++ ++MV_U32 mvCesaInProcessGet(void); ++MV_STATUS mvCesaReadyDispatch(void); ++MV_STATUS mvCesaReadyGet(MV_CESA_RESULT* pResult); ++MV_BOOL mvCesaIsReady(void); ++ ++int mvCesaMbufOffset(MV_CESA_MBUF* pMbuf, int offset, int* pBufOffset); ++MV_STATUS mvCesaCopyFromMbuf(MV_U8* pDst, MV_CESA_MBUF* pSrcMbuf, ++ int offset, int size); ++MV_STATUS mvCesaCopyToMbuf(MV_U8* pSrc, MV_CESA_MBUF* pDstMbuf, ++ int offset, int size); ++MV_STATUS mvCesaMbufCopy(MV_CESA_MBUF* pMbufDst, int dstMbufOffset, ++ MV_CESA_MBUF* pMbufSrc, int srcMbufOffset, int size); ++ ++/********** Debug functions ********/ ++ ++void mvCesaDebugMbuf(const char* str, MV_CESA_MBUF *pMbuf, int offset, int size); ++void mvCesaDebugSA(short sid, int mode); ++void mvCesaDebugStats(void); ++void mvCesaDebugStatsClear(void); ++void mvCesaDebugRegs(void); ++void mvCesaDebugStatus(void); ++void mvCesaDebugQueue(int mode); ++void mvCesaDebugSram(int mode); ++void mvCesaDebugSAD(int mode); ++ ++ ++/******** CESA Private definitions ********/ ++#if (MV_CESA_VERSION >= 2) ++#if (MV_CACHE_COHERENCY == MV_CACHE_COHER_SW) ++#define MV_CESA_TDMA_CTRL_VALUE MV_CESA_TDMA_DST_BURST_MASK(MV_CESA_TDMA_BURST_128B) \ ++ | MV_CESA_TDMA_SRC_BURST_MASK(MV_CESA_TDMA_BURST_128B) \ ++ | MV_CESA_TDMA_OUTSTAND_READ_EN_MASK \ ++ | MV_CESA_TDMA_NO_BYTE_SWAP_MASK \ ++ | MV_CESA_TDMA_ENABLE_MASK ++#else ++#define MV_CESA_TDMA_CTRL_VALUE MV_CESA_TDMA_DST_BURST_MASK(MV_CESA_TDMA_BURST_32B) \ ++ | MV_CESA_TDMA_SRC_BURST_MASK(MV_CESA_TDMA_BURST_128B) \ ++ /*| MV_CESA_TDMA_OUTSTAND_READ_EN_MASK */\ ++ | MV_CESA_TDMA_ENABLE_MASK ++ ++#endif ++#else ++#define MV_CESA_IDMA_CTRL_LOW_VALUE ICCLR_DST_BURST_LIM_128BYTE \ ++ | ICCLR_SRC_BURST_LIM_128BYTE \ ++ | ICCLR_INT_MODE_MASK \ ++ | ICCLR_BLOCK_MODE \ ++ | ICCLR_CHAN_ENABLE \ ++ | ICCLR_DESC_MODE_16M ++#endif /* MV_CESA_VERSION >= 2 */ ++ ++#define MV_CESA_MAX_PKT_SIZE (64 * 1024) ++#define MV_CESA_MAX_MBUF_FRAGS 20 ++ ++#define MV_CESA_MAX_REQ_FRAGS ( (MV_CESA_MAX_PKT_SIZE / MV_CESA_MAX_BUF_SIZE) + 1) ++ ++#define MV_CESA_MAX_DMA_DESC (MV_CESA_MAX_MBUF_FRAGS*2 + 5) ++ ++#define MAX_CESA_CHAIN_LENGTH 20 ++ ++typedef enum ++{ ++ MV_CESA_IDLE = 0, ++ MV_CESA_PENDING, ++ MV_CESA_PROCESS, ++ MV_CESA_READY, ++#if (MV_CESA_VERSION >= 3) ++ MV_CESA_CHAIN, ++#endif ++} MV_CESA_STATE; ++ ++ ++/* Session database */ ++ ++/* Map of Key materials of the session in SRAM. ++ * Each field must be 8 byte aligned ++ * Total size: 32 + 24 + 24 = 80 bytes ++ */ ++typedef struct ++{ ++ MV_U8 cryptoKey[MV_CESA_MAX_CRYPTO_KEY_LENGTH]; ++ MV_U8 macInnerIV[MV_CESA_MAX_DIGEST_SIZE]; ++ MV_U8 reservedInner[4]; ++ MV_U8 macOuterIV[MV_CESA_MAX_DIGEST_SIZE]; ++ MV_U8 reservedOuter[4]; ++ ++} MV_CESA_SRAM_SA; ++ ++typedef struct ++{ ++ MV_CESA_SRAM_SA* pSramSA; ++ MV_U32 config; ++ MV_U8 cryptoKeyLength; ++ MV_U8 cryptoIvSize; ++ MV_U8 cryptoBlockSize; ++ MV_U8 digestSize; ++ MV_U8 macKeyLength; ++ MV_U8 valid; ++ MV_U8 ctrMode; ++ MV_U32 count; ++ ++} MV_CESA_SA; ++ ++/* DMA list management */ ++typedef struct ++{ ++ MV_DMA_DESC* pDmaFirst; ++ MV_DMA_DESC* pDmaLast; ++ ++} MV_CESA_DMA; ++ ++ ++typedef struct ++{ ++ MV_U8 numFrag; ++ MV_U8 nextFrag; ++ int bufOffset; ++ int cryptoSize; ++ int macSize; ++ int newDigestOffset; ++ MV_U8 orgDigest[MV_CESA_MAX_DIGEST_SIZE]; ++ ++} MV_CESA_FRAGS; ++ ++/* Request queue */ ++typedef struct ++{ ++ MV_U8 state; ++ MV_U8 fragMode; ++ MV_U8 fixOffset; ++ MV_CESA_COMMAND* pCmd; ++ MV_CESA_COMMAND* pOrgCmd; ++ MV_BUF_INFO dmaDescBuf; ++ MV_CESA_DMA dma[MV_CESA_MAX_REQ_FRAGS]; ++ MV_BUF_INFO cesaDescBuf; ++ MV_CESA_DESC* pCesaDesc; ++ MV_CESA_FRAGS frags; ++ ++ ++} MV_CESA_REQ; ++ ++ ++/* SRAM map */ ++/* Total SRAM size calculation */ ++/* SRAM size = ++ * MV_CESA_MAX_BUF_SIZE + ++ * sizeof(MV_CESA_DESC) + ++ * MV_CESA_MAX_IV_LENGTH + ++ * MV_CESA_MAX_IV_LENGTH + ++ * MV_CESA_MAX_DIGEST_SIZE + ++ * sizeof(MV_CESA_SRAM_SA) ++ * = 1600 + 32 + 16 + 16 + 24 + 80 + 280 (reserved) = 2048 bytes ++ * = 3200 + 32 + 16 + 16 + 24 + 80 + 728 (reserved) = 4096 bytes ++ */ ++typedef struct ++{ ++ MV_U8 buf[MV_CESA_MAX_BUF_SIZE]; ++ MV_CESA_DESC desc; ++ MV_U8 cryptoIV[MV_CESA_MAX_IV_LENGTH]; ++ MV_U8 tempCryptoIV[MV_CESA_MAX_IV_LENGTH]; ++ MV_U8 tempDigest[MV_CESA_MAX_DIGEST_SIZE+4]; ++ MV_CESA_SRAM_SA sramSA; ++ ++} MV_CESA_SRAM_MAP; ++ ++ ++typedef struct ++{ ++ MV_U32 openedCount; ++ MV_U32 closedCount; ++ MV_U32 fragCount; ++ MV_U32 reqCount; ++ MV_U32 maxReqCount; ++ MV_U32 procCount; ++ MV_U32 readyCount; ++ MV_U32 notReadyCount; ++ MV_U32 startCount; ++#if (MV_CESA_VERSION >= 3) ++ MV_U32 maxChainUsage; ++#endif ++ ++} MV_CESA_STATS; ++ ++ ++/* External variables */ ++ ++extern MV_CESA_STATS cesaStats; ++extern MV_CESA_FRAGS cesaFrags; ++ ++extern MV_BUF_INFO cesaSramSaBuf; ++ ++extern MV_CESA_SA* pCesaSAD; ++extern MV_U16 cesaMaxSA; ++ ++extern MV_CESA_REQ* pCesaReqFirst; ++extern MV_CESA_REQ* pCesaReqLast; ++extern MV_CESA_REQ* pCesaReqEmpty; ++extern MV_CESA_REQ* pCesaReqProcess; ++extern int cesaQueueDepth; ++extern int cesaReqResources; ++#if (MV_CESA_VERSION>= 3) ++extern MV_U32 cesaChainLength; ++#endif ++ ++extern MV_CESA_SRAM_MAP* cesaSramVirtPtr; ++extern MV_U32 cesaSramPhysAddr; ++ ++static INLINE MV_ULONG mvCesaVirtToPhys(MV_BUF_INFO* pBufInfo, void* pVirt) ++{ ++ return (pBufInfo->bufPhysAddr + ((MV_U8*)pVirt - pBufInfo->bufVirtPtr)); ++} ++ ++/* Additional DEBUG functions */ ++void mvCesaDebugSramSA(MV_CESA_SRAM_SA* pSramSA, int mode); ++void mvCesaDebugCmd(MV_CESA_COMMAND* pCmd, int mode); ++void mvCesaDebugDescriptor(MV_CESA_DESC* pDesc); ++ ++ ++ ++#endif /* __mvCesa_h__ */ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/cesa/mvCesaDebug.c linux-3.1.4/crypto/ocf/kirkwood/cesa/mvCesaDebug.c +--- linux-3.1.4.orig/crypto/ocf/kirkwood/cesa/mvCesaDebug.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/cesa/mvCesaDebug.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,484 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#include "mvOs.h" ++#include "mvDebug.h" ++ ++#include "cesa/mvMD5.h" ++#include "cesa/mvSHA1.h" ++ ++#include "cesa/mvCesa.h" ++#include "cesa/mvCesaRegs.h" ++#include "cesa/AES/mvAes.h" ++ ++static const char* mvCesaDebugStateStr(MV_CESA_STATE state) ++{ ++ switch(state) ++ { ++ case MV_CESA_IDLE: ++ return "Idle"; ++ ++ case MV_CESA_PENDING: ++ return "Pend"; ++ ++ case MV_CESA_PROCESS: ++ return "Proc"; ++ ++ case MV_CESA_READY: ++ return "Ready"; ++ ++ default: ++ break; ++ } ++ return "Unknown"; ++} ++ ++static const char* mvCesaDebugOperStr(MV_CESA_OPERATION oper) ++{ ++ switch(oper) ++ { ++ case MV_CESA_MAC_ONLY: ++ return "MacOnly"; ++ ++ case MV_CESA_CRYPTO_ONLY: ++ return "CryptoOnly"; ++ ++ case MV_CESA_MAC_THEN_CRYPTO: ++ return "MacCrypto"; ++ ++ case MV_CESA_CRYPTO_THEN_MAC: ++ return "CryptoMac"; ++ ++ default: ++ break; ++ } ++ return "Null"; ++} ++ ++static const char* mvCesaDebugCryptoAlgStr(MV_CESA_CRYPTO_ALG cryptoAlg) ++{ ++ switch(cryptoAlg) ++ { ++ case MV_CESA_CRYPTO_DES: ++ return "DES"; ++ ++ case MV_CESA_CRYPTO_3DES: ++ return "3DES"; ++ ++ case MV_CESA_CRYPTO_AES: ++ return "AES"; ++ ++ default: ++ break; ++ } ++ return "Null"; ++} ++ ++static const char* mvCesaDebugMacModeStr(MV_CESA_MAC_MODE macMode) ++{ ++ switch(macMode) ++ { ++ case MV_CESA_MAC_MD5: ++ return "MD5"; ++ ++ case MV_CESA_MAC_SHA1: ++ return "SHA1"; ++ ++ case MV_CESA_MAC_HMAC_MD5: ++ return "HMAC-MD5"; ++ ++ case MV_CESA_MAC_HMAC_SHA1: ++ return "HMAC_SHA1"; ++ ++ default: ++ break; ++ } ++ return "Null"; ++} ++ ++void mvCesaDebugCmd(MV_CESA_COMMAND* pCmd, int mode) ++{ ++ mvOsPrintf("pCmd=%p, pReqPrv=%p, pSrc=%p, pDst=%p, pCB=%p, sid=%d\n", ++ pCmd, pCmd->pReqPrv, pCmd->pSrc, pCmd->pDst, ++ pCmd->pFuncCB, pCmd->sessionId); ++ mvOsPrintf("isUser=%d, ivOffs=%d, crOffs=%d, crLen=%d, digest=%d, macOffs=%d, macLen=%d\n", ++ pCmd->ivFromUser, pCmd->ivOffset, pCmd->cryptoOffset, pCmd->cryptoLength, ++ pCmd->digestOffset, pCmd->macOffset, pCmd->macLength); ++} ++ ++/* no need to use in tool */ ++void mvCesaDebugMbuf(const char* str, MV_CESA_MBUF *pMbuf, int offset, int size) ++{ ++ int frag, len, fragOffset; ++ ++ if(str != NULL) ++ mvOsPrintf("%s: pMbuf=%p, numFrags=%d, mbufSize=%d\n", ++ str, pMbuf, pMbuf->numFrags, pMbuf->mbufSize); ++ ++ frag = mvCesaMbufOffset(pMbuf, offset, &fragOffset); ++ if(frag == MV_INVALID) ++ { ++ mvOsPrintf("CESA Mbuf Error: offset (%d) out of range\n", offset); ++ return; ++ } ++ ++ for(; fragnumFrags; frag++) ++ { ++ mvOsPrintf("#%2d. bufVirt=%p, bufSize=%d\n", ++ frag, pMbuf->pFrags[frag].bufVirtPtr, ++ pMbuf->pFrags[frag].bufSize); ++ if(size > 0) ++ { ++ len = MV_MIN(pMbuf->pFrags[frag].bufSize, size); ++ mvDebugMemDump(pMbuf->pFrags[frag].bufVirtPtr+fragOffset, len, 1); ++ size -= len; ++ fragOffset = 0; ++ } ++ } ++} ++ ++void mvCesaDebugRegs(void) ++{ ++ mvOsPrintf("\t CESA Registers:\n"); ++ ++ mvOsPrintf("MV_CESA_CMD_REG : 0x%X = 0x%08x\n", ++ MV_CESA_CMD_REG, ++ MV_REG_READ( MV_CESA_CMD_REG ) ); ++ ++ mvOsPrintf("MV_CESA_CHAN_DESC_OFFSET_REG : 0x%X = 0x%08x\n", ++ MV_CESA_CHAN_DESC_OFFSET_REG, ++ MV_REG_READ(MV_CESA_CHAN_DESC_OFFSET_REG) ); ++ ++ mvOsPrintf("MV_CESA_CFG_REG : 0x%X = 0x%08x\n", ++ MV_CESA_CFG_REG, ++ MV_REG_READ( MV_CESA_CFG_REG ) ); ++ ++ mvOsPrintf("MV_CESA_STATUS_REG : 0x%X = 0x%08x\n", ++ MV_CESA_STATUS_REG, ++ MV_REG_READ( MV_CESA_STATUS_REG ) ); ++ ++ mvOsPrintf("MV_CESA_ISR_CAUSE_REG : 0x%X = 0x%08x\n", ++ MV_CESA_ISR_CAUSE_REG, ++ MV_REG_READ( MV_CESA_ISR_CAUSE_REG ) ); ++ ++ mvOsPrintf("MV_CESA_ISR_MASK_REG : 0x%X = 0x%08x\n", ++ MV_CESA_ISR_MASK_REG, ++ MV_REG_READ( MV_CESA_ISR_MASK_REG ) ); ++#if (MV_CESA_VERSION >= 2) ++ mvOsPrintf("MV_CESA_TDMA_CTRL_REG : 0x%X = 0x%08x\n", ++ MV_CESA_TDMA_CTRL_REG, ++ MV_REG_READ( MV_CESA_TDMA_CTRL_REG ) ); ++ ++ mvOsPrintf("MV_CESA_TDMA_BYTE_COUNT_REG : 0x%X = 0x%08x\n", ++ MV_CESA_TDMA_BYTE_COUNT_REG, ++ MV_REG_READ( MV_CESA_TDMA_BYTE_COUNT_REG ) ); ++ ++ mvOsPrintf("MV_CESA_TDMA_SRC_ADDR_REG : 0x%X = 0x%08x\n", ++ MV_CESA_TDMA_SRC_ADDR_REG, ++ MV_REG_READ( MV_CESA_TDMA_SRC_ADDR_REG ) ); ++ ++ mvOsPrintf("MV_CESA_TDMA_DST_ADDR_REG : 0x%X = 0x%08x\n", ++ MV_CESA_TDMA_DST_ADDR_REG, ++ MV_REG_READ( MV_CESA_TDMA_DST_ADDR_REG ) ); ++ ++ mvOsPrintf("MV_CESA_TDMA_NEXT_DESC_PTR_REG : 0x%X = 0x%08x\n", ++ MV_CESA_TDMA_NEXT_DESC_PTR_REG, ++ MV_REG_READ( MV_CESA_TDMA_NEXT_DESC_PTR_REG ) ); ++ ++ mvOsPrintf("MV_CESA_TDMA_CURR_DESC_PTR_REG : 0x%X = 0x%08x\n", ++ MV_CESA_TDMA_CURR_DESC_PTR_REG, ++ MV_REG_READ( MV_CESA_TDMA_CURR_DESC_PTR_REG ) ); ++ ++ mvOsPrintf("MV_CESA_TDMA_ERROR_CAUSE_REG : 0x%X = 0x%08x\n", ++ MV_CESA_TDMA_ERROR_CAUSE_REG, ++ MV_REG_READ( MV_CESA_TDMA_ERROR_CAUSE_REG ) ); ++ ++ mvOsPrintf("MV_CESA_TDMA_ERROR_MASK_REG : 0x%X = 0x%08x\n", ++ MV_CESA_TDMA_ERROR_MASK_REG, ++ MV_REG_READ( MV_CESA_TDMA_ERROR_CAUSE_REG ) ); ++ ++#endif ++} ++ ++void mvCesaDebugStatus(void) ++{ ++ mvOsPrintf("\n\t CESA Status\n\n"); ++ ++ mvOsPrintf("pReqQ=%p, qDepth=%d, reqSize=%ld bytes, qRes=%d, ", ++ pCesaReqFirst, cesaQueueDepth, sizeof(MV_CESA_REQ), ++ cesaReqResources); ++#if (MV_CESA_VERSION >= 3) ++ mvOsPrintf("chainLength=%u\n",cesaChainLength); ++#else ++ mvOsPrintf("\n"); ++#endif ++ ++ mvOsPrintf("pSAD=%p, maxSA=%d, sizeSA=%ld bytes\n", ++ pCesaSAD, cesaMaxSA, sizeof(MV_CESA_SA)); ++ ++ mvOsPrintf("\n"); ++ ++ mvCesaDebugRegs(); ++ mvCesaDebugStats(); ++ mvCesaDebugStatsClear(); ++} ++ ++void mvCesaDebugDescriptor(MV_CESA_DESC* pDesc) ++{ ++ mvOsPrintf("config=0x%08x, crSrcOffs=0x%04x, crDstOffs=0x%04x\n", ++ pDesc->config, pDesc->cryptoSrcOffset, pDesc->cryptoDstOffset); ++ ++ mvOsPrintf("crLen=0x%04x, crKeyOffs=0x%04x, ivOffs=0x%04x, ivBufOffs=0x%04x\n", ++ pDesc->cryptoDataLen, pDesc->cryptoKeyOffset, ++ pDesc->cryptoIvOffset, pDesc->cryptoIvBufOffset); ++ ++ mvOsPrintf("macSrc=0x%04x, digest=0x%04x, macLen=0x%04x, inIv=0x%04x, outIv=0x%04x\n", ++ pDesc->macSrcOffset, pDesc->macDigestOffset, pDesc->macDataLen, ++ pDesc->macInnerIvOffset, pDesc->macOuterIvOffset); ++} ++ ++void mvCesaDebugQueue(int mode) ++{ ++ mvOsPrintf("\n\t CESA Request Queue:\n\n"); ++ ++ mvOsPrintf("pFirstReq=%p, pLastReq=%p, qDepth=%d, reqSize=%ld bytes\n", ++ pCesaReqFirst, pCesaReqLast, cesaQueueDepth, sizeof(MV_CESA_REQ)); ++ ++ mvOsPrintf("pEmpty=%p, pProcess=%p, qResources=%d\n", ++ pCesaReqEmpty, pCesaReqProcess, ++ cesaReqResources); ++ ++ if(mode != 0) ++ { ++ int count = 0; ++ MV_CESA_REQ* pReq = pCesaReqFirst; ++ ++ for(count=0; countstate), ++ pReq->fragMode, pReq->pCmd, pReq->dma[0].pDmaFirst, &pReq->pCesaDesc[0]); ++ if(pReq->fragMode != MV_CESA_FRAG_NONE) ++ { ++ int frag; ++ ++ mvOsPrintf("pFrags=%p, num=%d, next=%d, bufOffset=%d, cryptoSize=%d, macSize=%d\n", ++ &pReq->frags, pReq->frags.numFrag, pReq->frags.nextFrag, ++ pReq->frags.bufOffset, pReq->frags.cryptoSize, pReq->frags.macSize); ++ for(frag=0; fragfrags.numFrag; frag++) ++ { ++ mvOsPrintf("#%d: pDmaFirst=%p, pDesc=%p\n", frag, ++ pReq->dma[frag].pDmaFirst, &pReq->pCesaDesc[frag]); ++ } ++ } ++ if(mode > 1) ++ { ++ /* Print out Command */ ++ mvCesaDebugCmd(pReq->pCmd, mode); ++ ++ /* Print out Descriptor */ ++ mvCesaDebugDescriptor(&pReq->pCesaDesc[0]); ++ } ++ pReq++; ++ } ++ } ++} ++ ++ ++void mvCesaDebugSramSA(MV_CESA_SRAM_SA* pSramSA, int mode) ++{ ++ if(pSramSA == NULL) ++ { ++ mvOsPrintf("cesaSramSA: Unexpected pSramSA=%p\n", pSramSA); ++ return; ++ } ++ mvOsPrintf("pSramSA=%p, sizeSramSA=%ld bytes\n", ++ pSramSA, sizeof(MV_CESA_SRAM_SA)); ++ ++ if(mode != 0) ++ { ++ mvOsPrintf("cryptoKey=%p, maxCryptoKey=%d bytes\n", ++ pSramSA->cryptoKey, MV_CESA_MAX_CRYPTO_KEY_LENGTH); ++ mvDebugMemDump(pSramSA->cryptoKey, MV_CESA_MAX_CRYPTO_KEY_LENGTH, 1); ++ ++ mvOsPrintf("macInnerIV=%p, maxInnerIV=%d bytes\n", ++ pSramSA->macInnerIV, MV_CESA_MAX_DIGEST_SIZE); ++ mvDebugMemDump(pSramSA->macInnerIV, MV_CESA_MAX_DIGEST_SIZE, 1); ++ ++ mvOsPrintf("macOuterIV=%p, maxOuterIV=%d bytes\n", ++ pSramSA->macOuterIV, MV_CESA_MAX_DIGEST_SIZE); ++ mvDebugMemDump(pSramSA->macOuterIV, MV_CESA_MAX_DIGEST_SIZE, 1); ++ } ++} ++ ++void mvCesaDebugSA(short sid, int mode) ++{ ++ MV_CESA_OPERATION oper; ++ MV_CESA_DIRECTION dir; ++ MV_CESA_CRYPTO_ALG cryptoAlg; ++ MV_CESA_CRYPTO_MODE cryptoMode; ++ MV_CESA_MAC_MODE macMode; ++ MV_CESA_SA* pSA = &pCesaSAD[sid]; ++ ++ if( (pSA->valid) || ((pSA->count != 0) && (mode > 0)) || (mode >= 2) ) ++ { ++ mvOsPrintf("\n\nCESA SA Entry #%d (%p) - %s (count=%d)\n", ++ sid, pSA, ++ pSA->valid ? "Valid" : "Invalid", pSA->count); ++ ++ oper = (pSA->config & MV_CESA_OPERATION_MASK) >> MV_CESA_OPERATION_OFFSET; ++ dir = (pSA->config & MV_CESA_DIRECTION_MASK) >> MV_CESA_DIRECTION_BIT; ++ mvOsPrintf("%s - %s ", mvCesaDebugOperStr(oper), ++ (dir == MV_CESA_DIR_ENCODE) ? "Encode" : "Decode"); ++ if(oper != MV_CESA_MAC_ONLY) ++ { ++ cryptoAlg = (pSA->config & MV_CESA_CRYPTO_ALG_MASK) >> MV_CESA_CRYPTO_ALG_OFFSET; ++ cryptoMode = (pSA->config & MV_CESA_CRYPTO_MODE_MASK) >> MV_CESA_CRYPTO_MODE_BIT; ++ mvOsPrintf("- %s - %s ", mvCesaDebugCryptoAlgStr(cryptoAlg), ++ (cryptoMode == MV_CESA_CRYPTO_ECB) ? "ECB" : "CBC"); ++ } ++ if(oper != MV_CESA_CRYPTO_ONLY) ++ { ++ macMode = (pSA->config & MV_CESA_MAC_MODE_MASK) >> MV_CESA_MAC_MODE_OFFSET; ++ mvOsPrintf("- %s ", mvCesaDebugMacModeStr(macMode)); ++ } ++ mvOsPrintf("\n"); ++ ++ if(mode > 0) ++ { ++ mvOsPrintf("config=0x%08x, cryptoKeySize=%d, digestSize=%d\n", ++ pCesaSAD[sid].config, pCesaSAD[sid].cryptoKeyLength, ++ pCesaSAD[sid].digestSize); ++ ++ mvCesaDebugSramSA(pCesaSAD[sid].pSramSA, mode); ++ } ++ } ++} ++ ++ ++/**/ ++void mvCesaDebugSram(int mode) ++{ ++ mvOsPrintf("\n\t SRAM contents: size=%ld, pVirt=%p\n\n", ++ sizeof(MV_CESA_SRAM_MAP), cesaSramVirtPtr); ++ ++ mvOsPrintf("\n\t Sram buffer: size=%d, pVirt=%p\n", ++ MV_CESA_MAX_BUF_SIZE, cesaSramVirtPtr->buf); ++ if(mode != 0) ++ mvDebugMemDump(cesaSramVirtPtr->buf, 64, 1); ++ ++ mvOsPrintf("\n"); ++ mvOsPrintf("\n\t Sram descriptor: size=%ld, pVirt=%p\n", ++ sizeof(MV_CESA_DESC), &cesaSramVirtPtr->desc); ++ if(mode != 0) ++ { ++ mvOsPrintf("\n"); ++ mvCesaDebugDescriptor(&cesaSramVirtPtr->desc); ++ } ++ mvOsPrintf("\n\t Sram IV: size=%d, pVirt=%p\n", ++ MV_CESA_MAX_IV_LENGTH, &cesaSramVirtPtr->cryptoIV); ++ if(mode != 0) ++ { ++ mvOsPrintf("\n"); ++ mvDebugMemDump(cesaSramVirtPtr->cryptoIV, MV_CESA_MAX_IV_LENGTH, 1); ++ } ++ mvOsPrintf("\n"); ++ mvCesaDebugSramSA(&cesaSramVirtPtr->sramSA, 0); ++} ++ ++void mvCesaDebugSAD(int mode) ++{ ++ int sid; ++ ++ mvOsPrintf("\n\t Cesa SAD status: pSAD=%p, maxSA=%d\n", ++ pCesaSAD, cesaMaxSA); ++ ++ for(sid=0; sid= 3) ++ mvOsPrintf("maxChainUsage=%u\n",cesaStats.maxChainUsage); ++#endif ++ mvOsPrintf("\n"); ++ mvOsPrintf("proc=%u, ready=%u, notReady=%u\n", ++ cesaStats.procCount, cesaStats.readyCount, cesaStats.notReadyCount); ++} ++ ++void mvCesaDebugStatsClear(void) ++{ ++ memset(&cesaStats, 0, sizeof(cesaStats)); ++} +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/cesa/mvCesaRegs.h linux-3.1.4/crypto/ocf/kirkwood/cesa/mvCesaRegs.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/cesa/mvCesaRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/cesa/mvCesaRegs.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,357 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __mvCesaRegs_h__ ++#define __mvCesaRegs_h__ ++ ++#include "mvTypes.h" ++ ++typedef struct ++{ ++ /* word 0 */ ++ MV_U32 config; ++ /* word 1 */ ++ MV_U16 cryptoSrcOffset; ++ MV_U16 cryptoDstOffset; ++ /* word 2 */ ++ MV_U16 cryptoDataLen; ++ MV_U16 reserved1; ++ /* word 3 */ ++ MV_U16 cryptoKeyOffset; ++ MV_U16 reserved2; ++ /* word 4 */ ++ MV_U16 cryptoIvOffset; ++ MV_U16 cryptoIvBufOffset; ++ /* word 5 */ ++ MV_U16 macSrcOffset; ++ MV_U16 macTotalLen; ++ /* word 6 */ ++ MV_U16 macDigestOffset; ++ MV_U16 macDataLen; ++ /* word 7 */ ++ MV_U16 macInnerIvOffset; ++ MV_U16 macOuterIvOffset; ++ ++} MV_CESA_DESC; ++ ++/* operation */ ++typedef enum ++{ ++ MV_CESA_MAC_ONLY = 0, ++ MV_CESA_CRYPTO_ONLY = 1, ++ MV_CESA_MAC_THEN_CRYPTO = 2, ++ MV_CESA_CRYPTO_THEN_MAC = 3, ++ ++ MV_CESA_MAX_OPERATION ++ ++} MV_CESA_OPERATION; ++ ++#define MV_CESA_OPERATION_OFFSET 0 ++#define MV_CESA_OPERATION_MASK (0x3 << MV_CESA_OPERATION_OFFSET) ++ ++/* mac algorithm */ ++typedef enum ++{ ++ MV_CESA_MAC_NULL = 0, ++ MV_CESA_MAC_MD5 = 4, ++ MV_CESA_MAC_SHA1 = 5, ++ MV_CESA_MAC_HMAC_MD5 = 6, ++ MV_CESA_MAC_HMAC_SHA1 = 7, ++ ++} MV_CESA_MAC_MODE; ++ ++#define MV_CESA_MAC_MODE_OFFSET 4 ++#define MV_CESA_MAC_MODE_MASK (0x7 << MV_CESA_MAC_MODE_OFFSET) ++ ++typedef enum ++{ ++ MV_CESA_MAC_DIGEST_FULL = 0, ++ MV_CESA_MAC_DIGEST_96B = 1, ++ ++} MV_CESA_MAC_DIGEST_SIZE; ++ ++#define MV_CESA_MAC_DIGEST_SIZE_BIT 7 ++#define MV_CESA_MAC_DIGEST_SIZE_MASK (1 << MV_CESA_MAC_DIGEST_SIZE_BIT) ++ ++ ++typedef enum ++{ ++ MV_CESA_CRYPTO_NULL = 0, ++ MV_CESA_CRYPTO_DES = 1, ++ MV_CESA_CRYPTO_3DES = 2, ++ MV_CESA_CRYPTO_AES = 3, ++ ++} MV_CESA_CRYPTO_ALG; ++ ++#define MV_CESA_CRYPTO_ALG_OFFSET 8 ++#define MV_CESA_CRYPTO_ALG_MASK (0x3 << MV_CESA_CRYPTO_ALG_OFFSET) ++ ++ ++/* direction */ ++typedef enum ++{ ++ MV_CESA_DIR_ENCODE = 0, ++ MV_CESA_DIR_DECODE = 1, ++ ++} MV_CESA_DIRECTION; ++ ++#define MV_CESA_DIRECTION_BIT 12 ++#define MV_CESA_DIRECTION_MASK (1 << MV_CESA_DIRECTION_BIT) ++ ++/* crypto IV mode */ ++typedef enum ++{ ++ MV_CESA_CRYPTO_ECB = 0, ++ MV_CESA_CRYPTO_CBC = 1, ++ ++ /* NO HW Support */ ++ MV_CESA_CRYPTO_CTR = 10, ++ ++} MV_CESA_CRYPTO_MODE; ++ ++#define MV_CESA_CRYPTO_MODE_BIT 16 ++#define MV_CESA_CRYPTO_MODE_MASK (1 << MV_CESA_CRYPTO_MODE_BIT) ++ ++/* 3DES mode */ ++typedef enum ++{ ++ MV_CESA_CRYPTO_3DES_EEE = 0, ++ MV_CESA_CRYPTO_3DES_EDE = 1, ++ ++} MV_CESA_CRYPTO_3DES_MODE; ++ ++#define MV_CESA_CRYPTO_3DES_MODE_BIT 20 ++#define MV_CESA_CRYPTO_3DES_MODE_MASK (1 << MV_CESA_CRYPTO_3DES_MODE_BIT) ++ ++ ++/* AES Key Length */ ++typedef enum ++{ ++ MV_CESA_CRYPTO_AES_KEY_128 = 0, ++ MV_CESA_CRYPTO_AES_KEY_192 = 1, ++ MV_CESA_CRYPTO_AES_KEY_256 = 2, ++ ++} MV_CESA_CRYPTO_AES_KEY_LEN; ++ ++#define MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET 24 ++#define MV_CESA_CRYPTO_AES_KEY_LEN_MASK (0x3 << MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET) ++ ++/* Fragmentation mode */ ++typedef enum ++{ ++ MV_CESA_FRAG_NONE = 0, ++ MV_CESA_FRAG_FIRST = 1, ++ MV_CESA_FRAG_LAST = 2, ++ MV_CESA_FRAG_MIDDLE = 3, ++ ++} MV_CESA_FRAG_MODE; ++ ++#define MV_CESA_FRAG_MODE_OFFSET 30 ++#define MV_CESA_FRAG_MODE_MASK (0x3 << MV_CESA_FRAG_MODE_OFFSET) ++/*---------------------------------------------------------------------------*/ ++ ++/********** Security Accelerator Command Register **************/ ++#define MV_CESA_CMD_REG (MV_CESA_REG_BASE + 0xE00) ++ ++#define MV_CESA_CMD_CHAN_ENABLE_BIT 0 ++#define MV_CESA_CMD_CHAN_ENABLE_MASK (1 << MV_CESA_CMD_CHAN_ENABLE_BIT) ++ ++#define MV_CESA_CMD_CHAN_DISABLE_BIT 2 ++#define MV_CESA_CMD_CHAN_DISABLE_MASK (1 << MV_CESA_CMD_CHAN_DISABLE_BIT) ++ ++/********** Security Accelerator Descriptor Pointers Register **********/ ++#define MV_CESA_CHAN_DESC_OFFSET_REG (MV_CESA_REG_BASE + 0xE04) ++ ++/********** Security Accelerator Configuration Register **********/ ++#define MV_CESA_CFG_REG (MV_CESA_REG_BASE + 0xE08) ++ ++#define MV_CESA_CFG_STOP_DIGEST_ERR_BIT 0 ++#define MV_CESA_CFG_STOP_DIGEST_ERR_MASK (1 << MV_CESA_CFG_STOP_DIGEST_ERR_BIT) ++ ++#define MV_CESA_CFG_WAIT_DMA_BIT 7 ++#define MV_CESA_CFG_WAIT_DMA_MASK (1 << MV_CESA_CFG_WAIT_DMA_BIT) ++ ++#define MV_CESA_CFG_ACT_DMA_BIT 9 ++#define MV_CESA_CFG_ACT_DMA_MASK (1 << MV_CESA_CFG_ACT_DMA_BIT) ++ ++#define MV_CESA_CFG_CHAIN_MODE_BIT 11 ++#define MV_CESA_CFG_CHAIN_MODE_MASK (1 << MV_CESA_CFG_CHAIN_MODE_BIT) ++ ++/********** Security Accelerator Status Register ***********/ ++#define MV_CESA_STATUS_REG (MV_CESA_REG_BASE + 0xE0C) ++ ++#define MV_CESA_STATUS_ACTIVE_BIT 0 ++#define MV_CESA_STATUS_ACTIVE_MASK (1 << MV_CESA_STATUS_ACTIVE_BIT) ++ ++#define MV_CESA_STATUS_DIGEST_ERR_BIT 8 ++#define MV_CESA_STATUS_DIGEST_ERR_MASK (1 << MV_CESA_STATUS_DIGEST_ERR_BIT) ++ ++ ++/* Cryptographic Engines and Security Accelerator Interrupt Cause Register */ ++#define MV_CESA_ISR_CAUSE_REG (MV_CESA_REG_BASE + 0xE20) ++ ++/* Cryptographic Engines and Security Accelerator Interrupt Mask Register */ ++#define MV_CESA_ISR_MASK_REG (MV_CESA_REG_BASE + 0xE24) ++ ++#define MV_CESA_CAUSE_AUTH_MASK (1 << 0) ++#define MV_CESA_CAUSE_DES_MASK (1 << 1) ++#define MV_CESA_CAUSE_AES_ENCR_MASK (1 << 2) ++#define MV_CESA_CAUSE_AES_DECR_MASK (1 << 3) ++#define MV_CESA_CAUSE_DES_ALL_MASK (1 << 4) ++ ++#define MV_CESA_CAUSE_ACC_BIT 5 ++#define MV_CESA_CAUSE_ACC_MASK (1 << MV_CESA_CAUSE_ACC_BIT) ++ ++#define MV_CESA_CAUSE_ACC_DMA_BIT 7 ++#define MV_CESA_CAUSE_ACC_DMA_MASK (1 << MV_CESA_CAUSE_ACC_DMA_BIT) ++#define MV_CESA_CAUSE_ACC_DMA_ALL_MASK (3 << MV_CESA_CAUSE_ACC_DMA_BIT) ++ ++#define MV_CESA_CAUSE_DMA_COMPL_BIT 9 ++#define MV_CESA_CAUSE_DMA_COMPL_MASK (1 << MV_CESA_CAUSE_DMA_COMPL_BIT) ++ ++#define MV_CESA_CAUSE_DMA_OWN_ERR_BIT 10 ++#define MV_CESA_CAUSE_DMA_OWN_ERR_MASK (1 < MV_CESA_CAUSE_DMA_OWN_ERR_BIT) ++ ++#define MV_CESA_CAUSE_DMA_CHAIN_PKT_BIT 11 ++#define MV_CESA_CAUSE_DMA_CHAIN_PKT_MASK (1 < MV_CESA_CAUSE_DMA_CHAIN_PKT_BIT) ++ ++ ++#define MV_CESA_AUTH_DATA_IN_REG (MV_CESA_REG_BASE + 0xd38) ++#define MV_CESA_AUTH_BIT_COUNT_LOW_REG (MV_CESA_REG_BASE + 0xd20) ++#define MV_CESA_AUTH_BIT_COUNT_HIGH_REG (MV_CESA_REG_BASE + 0xd24) ++ ++#define MV_CESA_AUTH_INIT_VAL_DIGEST_REG(i) (MV_CESA_REG_BASE + 0xd00 + (i<<2)) ++ ++#define MV_CESA_AUTH_INIT_VAL_DIGEST_A_REG (MV_CESA_REG_BASE + 0xd00) ++#define MV_CESA_AUTH_INIT_VAL_DIGEST_B_REG (MV_CESA_REG_BASE + 0xd04) ++#define MV_CESA_AUTH_INIT_VAL_DIGEST_C_REG (MV_CESA_REG_BASE + 0xd08) ++#define MV_CESA_AUTH_INIT_VAL_DIGEST_D_REG (MV_CESA_REG_BASE + 0xd0c) ++#define MV_CESA_AUTH_INIT_VAL_DIGEST_E_REG (MV_CESA_REG_BASE + 0xd10) ++#define MV_CESA_AUTH_COMMAND_REG (MV_CESA_REG_BASE + 0xd18) ++ ++#define MV_CESA_AUTH_ALGORITHM_BIT 0 ++#define MV_CESA_AUTH_ALGORITHM_MD5 (0< ++wait_queue_head_t cesaTest_waitq; ++spinlock_t cesaLock; ++ ++#define CESA_TEST_LOCK(flags) spin_lock_irqsave( &cesaLock, flags) ++#define CESA_TEST_UNLOCK(flags) spin_unlock_irqrestore( &cesaLock, flags); ++ ++#define CESA_TEST_WAIT_INIT() init_waitqueue_head(&cesaTest_waitq) ++#define CESA_TEST_WAKE_UP() wake_up(&cesaTest_waitq) ++#define CESA_TEST_WAIT(cond, ms) wait_event_timeout(cesaTest_waitq, (cond), msecs_to_jiffies(ms)) ++ ++#define CESA_TEST_TICK_GET() jiffies ++#define CESA_TEST_TICK_TO_MS(tick) jiffies_to_msecs(tick) ++ ++#elif defined(MV_NETBSD) ++ ++#include ++#include ++static int cesaLock; ++ ++#define CESA_TEST_LOCK(flags) flags = splnet() ++#define CESA_TEST_UNLOCK(flags) splx(flags) ++ ++#define CESA_TEST_WAIT_INIT() /* nothing */ ++#define CESA_TEST_WAKE_UP() wakeup(&cesaLock) ++#define CESA_TEST_WAIT(cond, ms) \ ++do { \ ++ while (!(cond)) \ ++ tsleep(&cesaLock, PWAIT, "cesatest",mstohz(ms)); \ ++} while (/*CONSTCOND*/0) ++ ++#define CESA_TEST_TICK_GET() hardclock_ticks ++#define CESA_TEST_TICK_TO_MS(tick) ((1000/hz)*(tick)) ++ ++#define request_irq(i,h,t,n,a) \ ++ !mv_intr_establish((i),IPL_NET,(int(*)(void *))(h),(a)) ++ ++#else ++#error "Only Linux, VxWorks, or NetBSD OS are supported" ++#endif ++ ++#include "mvDebug.h" ++ ++#include "mvSysHwConfig.h" ++#include "boardEnv/mvBoardEnvLib.h" ++#include "ctrlEnv/sys/mvCpuIf.h" ++#include "cntmr/mvCntmr.h" ++#include "cesa/mvCesa.h" ++#include "cesa/mvCesaRegs.h" ++#include "cesa/mvMD5.h" ++#include "cesa/mvSHA1.h" ++ ++#if defined(CONFIG_MV646xx) ++#include "marvell_pic.h" ++#endif ++ ++#define MV_CESA_USE_TIMER_ID 0 ++#define CESA_DEF_BUF_SIZE 1500 ++#define CESA_DEF_BUF_NUM 1 ++#define CESA_DEF_SESSION_NUM 32 ++ ++#define CESA_DEF_ITER_NUM 100 ++ ++#define CESA_DEF_REQ_SIZE 256 ++ ++ ++/* CESA Tests Debug */ ++#undef CESA_TEST_DEBUG ++ ++#ifdef CESA_TEST_DEBUG ++ ++# define CESA_TEST_DEBUG_PRINT(msg) mvOsPrintf msg ++# define CESA_TEST_DEBUG_CODE(code) code ++ ++typedef struct ++{ ++ int type; /* 0 - isrEmpty, 1 - cesaReadyGet, 2 - cesaAction */ ++ MV_U32 timeStamp; ++ MV_U32 cause; ++ MV_U32 realCause; ++ MV_U32 dmaCause; ++ int resources; ++ MV_CESA_REQ* pReqReady; ++ MV_CESA_REQ* pReqEmpty; ++ MV_CESA_REQ* pReqProcess; ++} MV_CESA_TEST_TRACE; ++ ++#define MV_CESA_TEST_TRACE_SIZE 25 ++ ++static int cesaTestTraceIdx = 0; ++static MV_CESA_TEST_TRACE cesaTestTrace[MV_CESA_TEST_TRACE_SIZE]; ++ ++static void cesaTestTraceAdd(int type, MV_U32 cause) ++{ ++ cesaTestTrace[cesaTestTraceIdx].type = type; ++ cesaTestTrace[cesaTestTraceIdx].cause = cause; ++ cesaTestTrace[cesaTestTraceIdx].realCause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); ++ cesaTestTrace[cesaTestTraceIdx].dmaCause = MV_REG_READ(IDMA_CAUSE_REG); ++ cesaTestTrace[cesaTestTraceIdx].resources = cesaReqResources; ++ cesaTestTrace[cesaTestTraceIdx].pReqReady = pCesaReqReady; ++ cesaTestTrace[cesaTestTraceIdx].pReqEmpty = pCesaReqEmpty; ++ cesaTestTrace[cesaTestTraceIdx].pReqProcess = pCesaReqProcess; ++ cesaTestTrace[cesaTestTraceIdx].timeStamp = mvCntmrRead(MV_CESA_USE_TIMER_ID); ++ cesaTestTraceIdx++; ++ if(cesaTestTraceIdx == MV_CESA_TEST_TRACE_SIZE) ++ cesaTestTraceIdx = 0; ++} ++ ++#else ++ ++# define CESA_TEST_DEBUG_PRINT(msg) ++# define CESA_TEST_DEBUG_CODE(code) ++ ++#endif /* CESA_TEST_DEBUG */ ++ ++int cesaExpReqId=0; ++int cesaCbIter=0; ++ ++int cesaIdx; ++int cesaIteration; ++int cesaRateSize; ++int cesaReqSize; ++unsigned long cesaTaskId; ++int cesaBufNum; ++int cesaBufSize; ++int cesaCheckOffset; ++int cesaCheckSize; ++int cesaCheckMode; ++int cesaTestIdx; ++int cesaCaseIdx; ++ ++ ++MV_U32 cesaTestIsrCount = 0; ++MV_U32 cesaTestIsrMissCount = 0; ++ ++MV_U32 cesaCryptoError = 0; ++MV_U32 cesaReqIdError = 0; ++MV_U32 cesaError = 0; ++ ++char* cesaHexBuffer = NULL; ++ ++char* cesaBinBuffer = NULL; ++char* cesaExpBinBuffer = NULL; ++ ++char* cesaInputHexStr = NULL; ++char* cesaOutputHexStr = NULL; ++ ++MV_BUF_INFO cesaReqBufs[CESA_DEF_REQ_SIZE]; ++ ++MV_CESA_COMMAND* cesaCmdRing; ++MV_CESA_RESULT cesaResult; ++ ++int cesaTestFull = 0; ++ ++MV_BOOL cesaIsReady = MV_FALSE; ++MV_U32 cesaCycles = 0; ++MV_U32 cesaBeginTicks = 0; ++MV_U32 cesaEndTicks = 0; ++MV_U32 cesaRate = 0; ++MV_U32 cesaRateAfterDot = 0; ++ ++void *cesaTestOSHandle = NULL; ++ ++enum ++{ ++ CESA_FAST_CHECK_MODE = 0, ++ CESA_FULL_CHECK_MODE, ++ CESA_NULL_CHECK_MODE, ++ CESA_SHOW_CHECK_MODE, ++ CESA_SW_SHOW_CHECK_MODE, ++ CESA_SW_NULL_CHECK_MODE, ++ ++ CESA_MAX_CHECK_MODE ++}; ++ ++enum ++{ ++ DES_TEST_TYPE = 0, ++ TRIPLE_DES_TEST_TYPE = 1, ++ AES_TEST_TYPE = 2, ++ MD5_TEST_TYPE = 3, ++ SHA_TEST_TYPE = 4, ++ COMBINED_TEST_TYPE = 5, ++ ++ MAX_TEST_TYPE ++}; ++ ++/* Tests data base */ ++typedef struct ++{ ++ short sid; ++ char cryptoAlgorithm; /* DES/3DES/AES */ ++ char cryptoMode; /* ECB or CBC */ ++ char macAlgorithm; /* MD5 / SHA1 */ ++ char operation; /* CRYPTO/HMAC/CRYPTO+HMAC/HMAC+CRYPTO */ ++ char direction; /* ENCODE(SIGN)/DECODE(VERIFY) */ ++ unsigned char* pCryptoKey; ++ int cryptoKeySize; ++ unsigned char* pMacKey; ++ int macKeySize; ++ const char* name; ++ ++} MV_CESA_TEST_SESSION; ++ ++typedef struct ++{ ++ MV_CESA_TEST_SESSION* pSessions; ++ int numSessions; ++ ++} MV_CESA_TEST_DB_ENTRY; ++ ++typedef struct ++{ ++ char* plainHexStr; ++ char* cipherHexStr; ++ unsigned char* pCryptoIV; ++ int cryptoLength; ++ int macLength; ++ int digestOffset; ++ ++} MV_CESA_TEST_CASE; ++ ++typedef struct ++{ ++ int size; ++ const char* outputHexStr; ++ ++} MV_CESA_SIZE_TEST; ++ ++static unsigned char cryptoKey1[] = {0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, ++ 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, ++ 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef}; ++ ++static unsigned char cryptoKey7[] = {0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef}; ++static unsigned char iv1[] = {0x12, 0x34, 0x56, 0x78, 0x90, 0xab, 0xcd, 0xef}; ++ ++ ++static unsigned char cryptoKey2[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, ++ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F}; ++ ++static unsigned char cryptoKey3[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, ++ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, ++ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17}; ++ ++static unsigned char cryptoKey4[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, ++ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, ++ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, ++ 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f}; ++ ++static unsigned char cryptoKey5[] = {0x56, 0xe4, 0x7a, 0x38, 0xc5, 0x59, 0x89, 0x74, ++ 0xbc, 0x46, 0x90, 0x3d, 0xba, 0x29, 0x03, 0x49}; ++ ++ ++static unsigned char key3des1[] = {0x01, 0x23, 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF, ++ 0x23, 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF, 0x01, ++ 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF, 0x01, 0x23}; ++ ++/* Input ASCII string: The quick brown fox jump */ ++static char plain3des1[] = "54686520717566636B2062726F776E20666F78206A756D70"; ++static char cipher3des1[] = "A826FD8CE53B855FCCE21C8112256FE668D5C05DD9B6B900"; ++ ++static unsigned char key3des2[] = {0x62, 0x7f, 0x46, 0x0e, 0x08, 0x10, 0x4a, 0x10, ++ 0x43, 0xcd, 0x26, 0x5d, 0x58, 0x40, 0xea, 0xf1, ++ 0x31, 0x3e, 0xdf, 0x97, 0xdf, 0x2a, 0x8a, 0x8c}; ++ ++static unsigned char iv3des2[] = {0x8e, 0x29, 0xf7, 0x5e, 0xa7, 0x7e, 0x54, 0x75}; ++ ++static char plain3des2[] = "326a494cd33fe756"; ++ ++static char cipher3desCbc2[] = "8e29f75ea77e5475" ++ "b22b8d66de970692"; ++ ++static unsigned char key3des3[] = {0x37, 0xae, 0x5e, 0xbf, 0x46, 0xdf, 0xf2, 0xdc, ++ 0x07, 0x54, 0xb9, 0x4f, 0x31, 0xcb, 0xb3, 0x85, ++ 0x5e, 0x7f, 0xd3, 0x6d, 0xc8, 0x70, 0xbf, 0xae}; ++ ++static unsigned char iv3des3[] = {0x3d, 0x1d, 0xe3, 0xcc, 0x13, 0x2e, 0x3b, 0x65}; ++ ++static char plain3des3[] = "84401f78fe6c10876d8ea23094ea5309"; ++ ++static char cipher3desCbc3[] = "3d1de3cc132e3b65" ++ "7b1f7c7e3b1c948ebd04a75ffba7d2f5"; ++ ++static unsigned char iv5[] = {0x8c, 0xe8, 0x2e, 0xef, 0xbe, 0xa0, 0xda, 0x3c, ++ 0x44, 0x69, 0x9e, 0xd7, 0xdb, 0x51, 0xb7, 0xd9}; ++ ++static unsigned char aesCtrKey[] = {0x76, 0x91, 0xBE, 0x03, 0x5E, 0x50, 0x20, 0xA8, ++ 0xAC, 0x6E, 0x61, 0x85, 0x29, 0xF9, 0xA0, 0xDC}; ++ ++static unsigned char mdKey1[] = {0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, ++ 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b}; ++ ++static unsigned char mdKey2[] = {0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, ++ 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa}; ++ ++static unsigned char shaKey1[] = {0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, ++ 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, ++ 0x0b, 0x0b, 0x0b, 0x0b}; ++ ++static unsigned char shaKey2[] = {0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, ++ 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, ++ 0xaa, 0xaa, 0xaa, 0xaa}; ++ ++static unsigned char mdKey4[] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, ++ 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10}; ++ ++static unsigned char shaKey4[] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, ++ 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10, ++ 0x11, 0x12, 0x13, 0x14}; ++ ++ ++static MV_CESA_TEST_SESSION desTestSessions[] = ++{ ++/*000*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey7, sizeof(cryptoKey7)/sizeof(cryptoKey7[0]), ++ NULL, 0, ++ "DES ECB encode", ++ }, ++/*001*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_DECODE, ++ cryptoKey7, sizeof(cryptoKey7)/sizeof(cryptoKey7[0]), ++ NULL, 0, ++ "DES ECB decode", ++ }, ++/*002*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_CBC, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey7, sizeof(cryptoKey7)/sizeof(cryptoKey7[0]), ++ NULL, 0, ++ "DES CBC encode" ++ }, ++/*003*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_CBC, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_DECODE, ++ cryptoKey7, sizeof(cryptoKey7)/sizeof(cryptoKey7[0]), ++ NULL, 0, ++ "DES CBC decode" ++ }, ++/*004*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ NULL, 0, NULL, 0, ++ "NULL Crypto Algorithm encode" ++ }, ++}; ++ ++ ++static MV_CESA_TEST_SESSION tripleDesTestSessions[] = ++{ ++/*100*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), ++ NULL, 0, ++ "3DES ECB encode", ++ }, ++/*101*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_DECODE, ++ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), ++ NULL, 0, ++ "3DES ECB decode", ++ }, ++/*102*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), ++ NULL, 0, ++ "3DES CBC encode" ++ }, ++/*103*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_DECODE, ++ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), ++ NULL, 0, ++ "3DES CBC decode" ++ }, ++/*104*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ key3des1, sizeof(key3des1), ++ NULL, 0, ++ "3DES ECB encode" ++ }, ++/*105*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ key3des2, sizeof(key3des2), ++ NULL, 0, ++ "3DES ECB encode" ++ }, ++/*106*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ key3des3, sizeof(key3des3), ++ NULL, 0, ++ "3DES ECB encode" ++ }, ++}; ++ ++ ++static MV_CESA_TEST_SESSION aesTestSessions[] = ++{ ++/*200*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey2, sizeof(cryptoKey2)/sizeof(cryptoKey2[0]), ++ NULL, 0, ++ "AES-128 ECB encode" ++ }, ++/*201*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_DECODE, ++ cryptoKey2, sizeof(cryptoKey2)/sizeof(cryptoKey2[0]), ++ NULL, 0, ++ "AES-128 ECB decode" ++ }, ++/*202*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey5, sizeof(cryptoKey5)/sizeof(cryptoKey5[0]), ++ NULL, 0, ++ "AES-128 CBC encode" ++ }, ++/*203*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_DECODE, ++ cryptoKey5, sizeof(cryptoKey5)/sizeof(cryptoKey5[0]), ++ NULL, 0, ++ "AES-128 CBC decode" ++ }, ++/*204*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey3, sizeof(cryptoKey3)/sizeof(cryptoKey3[0]), ++ NULL, 0, ++ "AES-192 ECB encode" ++ }, ++/*205*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_DECODE, ++ cryptoKey3, sizeof(cryptoKey3)/sizeof(cryptoKey3[0]), ++ NULL, 0, ++ "AES-192 ECB decode" ++ }, ++/*206*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey4, sizeof(cryptoKey4)/sizeof(cryptoKey4[0]), ++ NULL, 0, ++ "AES-256 ECB encode" ++ }, ++/*207*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_DECODE, ++ cryptoKey4, sizeof(cryptoKey4)/sizeof(cryptoKey4[0]), ++ NULL, 0, ++ "AES-256 ECB decode" ++ }, ++/*208*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CTR, ++ MV_CESA_MAC_NULL, MV_CESA_CRYPTO_ONLY, ++ MV_CESA_DIR_ENCODE, ++ aesCtrKey, sizeof(aesCtrKey)/sizeof(aesCtrKey[0]), ++ NULL, 0, ++ "AES-128 CTR encode" ++ }, ++}; ++ ++ ++static MV_CESA_TEST_SESSION md5TestSessions[] = ++{ ++/*300*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, ++ MV_CESA_DIR_ENCODE, ++ NULL, 0, ++ mdKey1, sizeof(mdKey1), ++ "HMAC-MD5 Generate Signature" ++ }, ++/*301*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, ++ MV_CESA_DIR_DECODE, ++ NULL, 0, ++ mdKey1, sizeof(mdKey1), ++ "HMAC-MD5 Verify Signature" ++ }, ++/*302*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, ++ MV_CESA_DIR_ENCODE, ++ NULL, 0, ++ mdKey2, sizeof(mdKey2), ++ "HMAC-MD5 Generate Signature" ++ }, ++/*303*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, ++ MV_CESA_DIR_DECODE, ++ NULL, 0, ++ mdKey2, sizeof(mdKey2), ++ "HMAC-MD5 Verify Signature" ++ }, ++/*304*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_ONLY, ++ MV_CESA_DIR_ENCODE, ++ NULL, 0, ++ mdKey4, sizeof(mdKey4), ++ "HMAC-MD5 Generate Signature" ++ }, ++/*305*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_MD5, MV_CESA_MAC_ONLY, ++ MV_CESA_DIR_ENCODE, ++ NULL, 0, ++ NULL, 0, ++ "HASH-MD5 Generate Signature" ++ }, ++}; ++ ++ ++static MV_CESA_TEST_SESSION shaTestSessions[] = ++{ ++/*400*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, ++ MV_CESA_DIR_ENCODE, ++ NULL, 0, ++ shaKey1, sizeof(shaKey1), ++ "HMAC-SHA1 Generate Signature" ++ }, ++/*401*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, ++ MV_CESA_DIR_DECODE, ++ NULL, 0, ++ shaKey1, sizeof(shaKey1), ++ "HMAC-SHA1 Verify Signature" ++ }, ++/*402*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, ++ MV_CESA_DIR_ENCODE, ++ NULL, 0, ++ shaKey2, sizeof(shaKey2), ++ "HMAC-SHA1 Generate Signature" ++ }, ++/*403*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, ++ MV_CESA_DIR_DECODE, ++ NULL, 0, ++ shaKey2, sizeof(shaKey2), ++ "HMAC-SHA1 Verify Signature" ++ }, ++/*404*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_SHA1, MV_CESA_MAC_ONLY, ++ MV_CESA_DIR_ENCODE, ++ NULL, 0, ++ shaKey4, sizeof(shaKey4), ++ "HMAC-SHA1 Generate Signature" ++ }, ++/*405*/ {-1, MV_CESA_CRYPTO_NULL, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_SHA1, MV_CESA_MAC_ONLY, ++ MV_CESA_DIR_ENCODE, ++ NULL, 0, ++ NULL, 0, ++ "HASH-SHA1 Generate Signature" ++ }, ++}; ++ ++static MV_CESA_TEST_SESSION combinedTestSessions[] = ++{ ++/*500*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey1, MV_CESA_DES_KEY_LENGTH, ++ mdKey4, sizeof(mdKey4), ++ "DES + MD5 encode" ++ }, ++/*501*/ {-1, MV_CESA_CRYPTO_DES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey1, MV_CESA_DES_KEY_LENGTH, ++ shaKey4, sizeof(shaKey4), ++ "DES + SHA1 encode" ++ }, ++/*502*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), ++ mdKey4, sizeof(mdKey4), ++ "3DES + MD5 encode" ++ }, ++/*503*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), ++ shaKey4, sizeof(shaKey4), ++ "3DES + SHA1 encode" ++ }, ++/*504*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, ++ MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), ++ mdKey4, sizeof(mdKey4), ++ "3DES CBC + MD5 encode" ++ }, ++/*505*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_CBC, ++ MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), ++ shaKey4, sizeof(shaKey4), ++ "3DES CBC + SHA1 encode" ++ }, ++/*506*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, ++ MV_CESA_MAC_HMAC_MD5, MV_CESA_CRYPTO_THEN_MAC, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey5, sizeof(cryptoKey5)/sizeof(cryptoKey5[0]), ++ mdKey4, sizeof(mdKey4), ++ "AES-128 CBC + MD5 encode" ++ }, ++/*507*/ {-1, MV_CESA_CRYPTO_AES, MV_CESA_CRYPTO_CBC, ++ MV_CESA_MAC_HMAC_SHA1, MV_CESA_CRYPTO_THEN_MAC, ++ MV_CESA_DIR_ENCODE, ++ cryptoKey5, sizeof(cryptoKey5)/sizeof(cryptoKey5[0]), ++ shaKey4, sizeof(shaKey4), ++ "AES-128 CBC + SHA1 encode" ++ }, ++/*508*/ {-1, MV_CESA_CRYPTO_3DES, MV_CESA_CRYPTO_ECB, ++ MV_CESA_MAC_HMAC_MD5, MV_CESA_MAC_THEN_CRYPTO, ++ MV_CESA_DIR_DECODE, ++ cryptoKey1, sizeof(cryptoKey1)/sizeof(cryptoKey1[0]), ++ mdKey4, sizeof(mdKey4), ++ "HMAC-MD5 + 3DES decode" ++ }, ++}; ++ ++ ++static MV_CESA_TEST_DB_ENTRY cesaTestsDB[MAX_TEST_TYPE+1] = ++{ ++ { desTestSessions, sizeof(desTestSessions)/sizeof(desTestSessions[0]) }, ++ { tripleDesTestSessions, sizeof(tripleDesTestSessions)/sizeof(tripleDesTestSessions[0]) }, ++ { aesTestSessions, sizeof(aesTestSessions)/sizeof(aesTestSessions[0]) }, ++ { md5TestSessions, sizeof(md5TestSessions)/sizeof(md5TestSessions[0]) }, ++ { shaTestSessions, sizeof(shaTestSessions)/sizeof(shaTestSessions[0]) }, ++ { combinedTestSessions, sizeof(combinedTestSessions)/sizeof(combinedTestSessions[0]) }, ++ { NULL, 0 } ++}; ++ ++ ++char cesaNullPlainHexText[] = "000000000000000000000000000000000000000000000000"; ++ ++char cesaPlainAsciiText[] = "Now is the time for all "; ++char cesaPlainHexEbc[] = "4e6f77206973207468652074696d6520666f7220616c6c20"; ++char cesaCipherHexEcb[] = "3fa40e8a984d48156a271787ab8883f9893d51ec4b563b53"; ++char cesaPlainHexCbc[] = "1234567890abcdef4e6f77206973207468652074696d6520666f7220616c6c20"; ++char cesaCipherHexCbc[] = "1234567890abcdefe5c7cdde872bf27c43e934008c389c0f683788499a7c05f6"; ++ ++char cesaAesPlainHexEcb[] = "000102030405060708090a0b0c0d0e0f"; ++char cesaAes128cipherHexEcb[] = "0a940bb5416ef045f1c39458c653ea5a"; ++char cesaAes192cipherHexEcb[] = "0060bffe46834bb8da5cf9a61ff220ae"; ++char cesaAes256cipherHexEcb[] = "5a6e045708fb7196f02e553d02c3a692"; ++ ++char cesaAsciiStr1[] = "Hi There"; ++char cesaDataHexStr1[] = "4869205468657265"; ++char cesaHmacMd5digestHex1[] = "9294727a3638bb1c13f48ef8158bfc9d"; ++char cesaHmacSha1digestHex1[] = "b617318655057264e28bc0b6fb378c8ef146be00"; ++char cesaDataAndMd5digest1[] = "48692054686572659294727a3638bb1c13f48ef8158bfc9d"; ++char cesaDataAndSha1digest1[] = "4869205468657265b617318655057264e28bc0b6fb378c8ef146be00"; ++ ++char cesaAesPlainText[] = "a0a1a2a3a4a5a6a7a8a9aaabacadaeaf" ++ "b0b1b2b3b4b5b6b7b8b9babbbcbdbebf" ++ "c0c1c2c3c4c5c6c7c8c9cacbcccdcecf" ++ "d0d1d2d3d4d5d6d7d8d9dadbdcdddedf"; ++ ++char cesaAes128CipherCbc[] = "c30e32ffedc0774e6aff6af0869f71aa" ++ "0f3af07a9a31a9c684db207eb0ef8e4e" ++ "35907aa632c3ffdf868bb7b29d3d46ad" ++ "83ce9f9a102ee99d49a53e87f4c3da55"; ++ ++char cesaAesIvPlainText[] = "8ce82eefbea0da3c44699ed7db51b7d9" ++ "a0a1a2a3a4a5a6a7a8a9aaabacadaeaf" ++ "b0b1b2b3b4b5b6b7b8b9babbbcbdbebf" ++ "c0c1c2c3c4c5c6c7c8c9cacbcccdcecf" ++ "d0d1d2d3d4d5d6d7d8d9dadbdcdddedf"; ++ ++char cesaAes128IvCipherCbc[] = "8ce82eefbea0da3c44699ed7db51b7d9" ++ "c30e32ffedc0774e6aff6af0869f71aa" ++ "0f3af07a9a31a9c684db207eb0ef8e4e" ++ "35907aa632c3ffdf868bb7b29d3d46ad" ++ "83ce9f9a102ee99d49a53e87f4c3da55"; ++ ++char cesaAesCtrPlain[] = "00E0017B27777F3F4A1786F000000001" ++ "000102030405060708090A0B0C0D0E0F" ++ "101112131415161718191A1B1C1D1E1F" ++ "20212223"; ++ ++char cesaAesCtrCipher[] = "00E0017B27777F3F4A1786F000000001" ++ "C1CF48A89F2FFDD9CF4652E9EFDB72D7" ++ "4540A42BDE6D7836D59A5CEAAEF31053" ++ "25B2072F"; ++ ++ ++ ++/* Input cesaHmacHex3 is '0xdd' repeated 50 times */ ++char cesaHmacMd5digestHex3[] = "56be34521d144c88dbb8c733f0e8b3f6"; ++char cesaHmacSha1digestHex3[] = "125d7342b9ac11cd91a39af48aa17b4f63f175d3"; ++char cesaDataHexStr3[50*2+1] = ""; ++char cesaDataAndMd5digest3[sizeof(cesaDataHexStr3)+sizeof(cesaHmacMd5digestHex3)+8*2+1] = ""; ++char cesaDataAndSha1digest3[sizeof(cesaDataHexStr3)+sizeof(cesaHmacSha1digestHex3)+8*2+1] = ""; ++ ++/* Ascii string is "abc" */ ++char hashHexStr3[] = "616263"; ++char hashMd5digest3[] = "900150983cd24fb0d6963f7d28e17f72"; ++char hashSha1digest3[] = "a9993e364706816aba3e25717850c26c9cd0d89d"; ++ ++char hashHexStr80[] = "31323334353637383930" ++ "31323334353637383930" ++ "31323334353637383930" ++ "31323334353637383930" ++ "31323334353637383930" ++ "31323334353637383930" ++ "31323334353637383930" ++ "31323334353637383930"; ++ ++char hashMd5digest80[] = "57edf4a22be3c955ac49da2e2107b67a"; ++ ++char tripleDesThenMd5digest80[] = "b7726a03aad490bd6c5a452a89a1b271"; ++char tripleDesThenSha1digest80[] = "b2ddeaca91030eab5b95a234ef2c0f6e738ff883"; ++ ++char cbc3desThenMd5digest80[] = "6f463057e1a90e0e91ae505b527bcec0"; ++char cbc3desThenSha1digest80[] = "1b002ed050be743aa98860cf35659646bb8efcc0"; ++ ++char cbcAes128ThenMd5digest80[] = "6b6e863ac5a71d15e3e9b1c86c9ba05f"; ++char cbcAes128ThenSha1digest80[] = "13558472d1fc1c90dffec6e5136c7203452d509b"; ++ ++ ++static MV_CESA_TEST_CASE cesaTestCases[] = ++{ ++ /* plainHexStr cipherHexStr IV crypto mac digest */ ++ /* Length Length Offset */ ++ /*0*/ { NULL, NULL, NULL, 0, 0, -1 }, ++ /*1*/ { cesaPlainHexEbc, cesaCipherHexEcb, NULL, 24, 0, -1 }, ++ /*2*/ { cesaPlainHexCbc, cesaCipherHexCbc, NULL, 24, 0, -1 }, ++ /*3*/ { cesaAesPlainHexEcb, cesaAes128cipherHexEcb, NULL, 16, 0, -1 }, ++ /*4*/ { cesaAesPlainHexEcb, cesaAes192cipherHexEcb, NULL, 16, 0, -1 }, ++ /*5*/ { cesaAesPlainHexEcb, cesaAes256cipherHexEcb, NULL, 16, 0, -1 }, ++ /*6*/ { cesaDataHexStr1, cesaHmacMd5digestHex1, NULL, 0, 8, -1 }, ++ /*7*/ { NULL, cesaDataAndMd5digest1, NULL, 0, 8, -1 }, ++ /*8*/ { cesaDataHexStr3, cesaHmacMd5digestHex3, NULL, 0, 50, -1 }, ++ /*9*/ { NULL, cesaDataAndMd5digest3, NULL, 0, 50, -1 }, ++/*10*/ { cesaAesPlainText, cesaAes128IvCipherCbc, iv5, 64, 0, -1 }, ++/*11*/ { cesaDataHexStr1, cesaHmacSha1digestHex1, NULL, 0, 8, -1 }, ++/*12*/ { NULL, cesaDataAndSha1digest1, NULL, 0, 8, -1 }, ++/*13*/ { cesaDataHexStr3, cesaHmacSha1digestHex3, NULL, 0, 50, -1 }, ++/*14*/ { NULL, cesaDataAndSha1digest3, NULL, 0, 50, -1 }, ++/*15*/ { hashHexStr3, hashMd5digest3, NULL, 0, 3, -1 }, ++/*16*/ { hashHexStr3, hashSha1digest3, NULL, 0, 3, -1 }, ++/*17*/ { hashHexStr80, tripleDesThenMd5digest80, NULL, 80, 80, -1 }, ++/*18*/ { hashHexStr80, tripleDesThenSha1digest80, NULL, 80, 80, -1 }, ++/*19*/ { hashHexStr80, cbc3desThenMd5digest80, iv1, 80, 80, -1 }, ++/*20*/ { hashHexStr80, cbc3desThenSha1digest80, iv1, 80, 80, -1 }, ++/*21*/ { hashHexStr80, cbcAes128ThenMd5digest80, iv5, 80, 80, -1 }, ++/*22*/ { hashHexStr80, cbcAes128ThenSha1digest80, iv5, 80, 80, -1 }, ++/*23*/ { cesaAesCtrPlain, cesaAesCtrCipher, NULL, 36, 0, -1 }, ++/*24*/ { cesaAesIvPlainText, cesaAes128IvCipherCbc, NULL, 64, 0, -1 }, ++/*25*/ { plain3des1, cipher3des1, NULL, 0, 0, -1 }, ++/*26*/ { plain3des2, cipher3desCbc2, iv3des2,0, 0, -1 }, ++/*27*/ { plain3des3, cipher3desCbc3, iv3des3,0, 0, -1 }, ++}; ++ ++ ++/* Key = 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, ++ * 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa ++ * Input 0xdd repeated "size" times ++ */ ++static MV_CESA_SIZE_TEST mdMultiSizeTest302[] = ++{ ++ { 80, "7a031a640c14a4872814930b1ef3a5b2" }, ++ { 512, "5488e6c5a14dc72a79f28312ca5b939b" }, ++ { 1000, "d00814f586a8b78a05724239d2531821" }, ++ { 1001, "bf07df7b7f49d3f5b5ecacd4e9e63281" }, ++ { 1002, "1ed4a1a802e87817a819d4e37bb4d0f7" }, ++ { 1003, "5972ab64a4f265ee371dac2f2f137f90" }, ++ { 1004, "71f95e7ec3aa7df2548e90898abdb28e" }, ++ { 1005, "e082790b4857fcfc266e92e59e608814" }, ++ { 1006, "9500f02fd8ac7fde8b10e4fece9a920d" }, ++ { 1336, "e42edcce57d0b75b01aa09d71427948b" }, ++ { 1344, "bb5454ada0deb49ba0a97ffd60f57071" }, ++ { 1399, "0f44d793e744b24d53f44f295082ee8c" }, ++ { 1400, "359de8a03a9b707928c6c60e0e8d79f1" }, ++ { 1401, "e913858b484cbe2b384099ea88d8855b" }, ++ { 1402, "d9848a164af53620e0540c1d7d87629e" }, ++ { 1403, "0c9ee1c2c9ef45e9b625c26cbaf3e822" }, ++ { 1404, "12edd4f609416e3c936170360561b064" }, ++ { 1405, "7fc912718a05446395345009132bf562" }, ++ { 1406, "882f17425e579ff0d85a91a59f308aa0" }, ++ { 1407, "005cae408630a2fb5db82ad9db7e59da" }, ++ { 1408, "64655f8b404b3fea7a3e3e609bc5088f" }, ++ { 1409, "4a145284a7f74e01b6bb1a0ec6a0dd80" }, ++ { 2048, "67caf64475650732def374ebb8bde3fd" }, ++ { 2049, "6c84f11f472825f7e6cd125c2981884b" }, ++ { 2050, "8999586754a73a99efbe4dbad2816d41" }, ++ { 2051, "ba6946b610e098d286bc81091659dfff" }, ++ { 2052, "d0afa01c92d4d13def2b024f36faed83" }, ++ { 3072, "61d8beac61806afa2585d74a9a0e6974" }, ++ { 3074, "f6501a28dcc24d1e4770505c51a87ed3" }, ++ { 3075, "ea4a6929be67e33e61ff475369248b73" }, ++ { 4048, "aa8c4d68f282a07e7385acdfa69f4bed" }, ++ { 4052, "afb5ed2c0e1d430ea59e59ed5ed6b18a" }, ++ { 4058, "9e8553f9bdd43aebe0bd729f0e600c99" }, ++ { 6144, "f628f3e5d183fe5cdd3a5abee39cf872" }, ++ { 6150, "89a3efcea9a2f25f919168ad4a1fd292" }, ++ { 6400, "cdd176b7fb747873efa4da5e32bdf88f" }, ++ { 6528, "b1d707b027354aca152c45ee559ccd3f" }, ++ { 8192, "c600ea4429ac47f9941f09182166e51a" }, ++ {16384, "16e8754bfbeb4c649218422792267a37" }, ++ {18432, "0fd0607521b0aa8b52219cfbe215f63e" }, ++ { 0, NULL }, ++}; ++ ++/* Key = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, ++ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 ++ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") ++ */ ++static MV_CESA_SIZE_TEST mdMultiSizeTest304[] = ++{ ++ { 80, "a456c4723fee6068530af5a2afa71627" }, ++ { 512, "f85c2a2344f5de68b432208ad13e5794" }, ++ { 1000, "35464d6821fd4a293a41eb84e274c8c5" }, ++ { 1001, "c08eedbdce60cceb54bc2d732bb32c8b" }, ++ { 1002, "5664f71800c011cc311cb6943339c1b8" }, ++ { 1003, "779c723b044c585dc7802b13e8501bdc" }, ++ { 1004, "55e500766a2c307bc5c5fdd15e4cacd4" }, ++ { 1005, "d5f978954f5c38529d1679d2b714f068" }, ++ { 1006, "cd3efc827ce628b7281b72172693abf9" }, ++ { 1336, "6f04479910785878ae6335b8d1e87edf" }, ++ { 1344, "b6d27b50c2bce1ba2a8e1b5cc4324368" }, ++ { 1399, "65f70a1d4c86e5eaeb0704c8a7816795" }, ++ { 1400, "3394b5adc4cb3ff98843ca260a44a88a" }, ++ { 1401, "3a06f3582033a66a4e57e0603ce94e74" }, ++ { 1402, "e4d97f5ed51edc48abfa46eeb5c31752" }, ++ { 1403, "3d05e40b080ee3bedf293cb87b7140e7" }, ++ { 1404, "8cf294fc3cd153ab18dccb2a52cbf244" }, ++ { 1405, "d1487bd42f6edd9b4dab316631159221" }, ++ { 1406, "0527123b6bf6936cf5d369dc18c6c70f" }, ++ { 1407, "3224a06639db70212a0cd1ae1fcc570a" }, ++ { 1408, "a9e13335612c0356f5e2c27086e86c43" }, ++ { 1409, "a86d1f37d1ed8a3552e9a4f04dceea98" }, ++ { 2048, "396905c9b961cd0f6152abfb69c4449c" }, ++ { 2049, "49f39bff85d9dcf059fadb89efc4a70f" }, ++ { 2050, "3a2b4823bc4d0415656550226a63e34a" }, ++ { 2051, "dec60580d406c782540f398ad0bcc7e0" }, ++ { 2052, "32f76610a14310309eb748fe025081bf" }, ++ { 3072, "45edc1a42bf9d708a621076b63b774da" }, ++ { 3074, "9be1b333fe7c0c9f835fb369dc45f778" }, ++ { 3075, "8c06fcac7bd0e7b7a17fd6508c09a549" }, ++ { 4048, "0ddaef848184bf0ad98507a10f1e90e4" }, ++ { 4052, "81976bcaeb274223983996c137875cb8" }, ++ { 4058, "0b0a7a1c82bc7cbc64d8b7cd2dc2bb22" }, ++ { 6144, "1c24056f52725ede2dff0d7f9fc9855f" }, ++ { 6150, "b7f4b65681c4e43ee68ca466ca9ca4ec" }, ++ { 6400, "443bbaab9f7331ddd4bf11b659cd43c8" }, ++ { 6528, "216f44f23047cfee03a7a64f88f9a995" }, ++ { 8192, "ac7a993b2cad54879dba1bde63e39097" }, ++ { 8320, "55ed7be9682d6c0025b3221a62088d08" }, ++ {16384, "c6c722087653b62007aea668277175e5" }, ++ {18432, "f1faca8e907872c809e14ffbd85792d6" }, ++ { 0, NULL }, ++}; ++ ++/* HASH-MD5 ++ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") ++ * repeated "size" times ++ */ ++static MV_CESA_SIZE_TEST mdMultiSizeTest305[] = ++{ ++ { 80, "57edf4a22be3c955ac49da2e2107b67a" }, ++ { 512, "c729ae8f0736cc377a9767a660eaa04e" }, ++ { 1000, "f1257a8659eb92d36fe14c6bf3852a6a" }, ++ { 1001, "f8a46fe8ea04fdc8c7de0e84042d3878" }, ++ { 1002, "da188dd67bff87d58aa3c02af2d0cc0f" }, ++ { 1003, "961753017feee04c9b93a8e51658a829" }, ++ { 1004, "dd68c4338608dcc87807a711636bf2af" }, ++ { 1005, "e338d567d3ce66bf69ada29658a8759b" }, ++ { 1006, "443c9811e8b92599b0b149e8d7ec700a" }, ++ { 1336, "89a98511706008ba4cbd0b4a24fa5646" }, ++ { 1344, "335a919805f370b9e402a62c6fe01739" }, ++ { 1399, "5d18d0eddcd84212fe28d812b5e80e3b" }, ++ { 1400, "6b695c240d2dffd0dffc99459ca76db6" }, ++ { 1401, "49590f61298a76719bc93a57a30136f5" }, ++ { 1402, "94c2999fa3ef1910a683d69b2b8476f2" }, ++ { 1403, "37073a02ab00ecba2645c57c228860db" }, ++ { 1404, "1bcd06994fce28b624f0c5fdc2dcdd2b" }, ++ { 1405, "11b93671a64c95079e8cf9e7cddc8b3d" }, ++ { 1406, "4b6695772a4c66313fa4871017d05f36" }, ++ { 1407, "d1539b97fbfda1c075624e958de19c5b" }, ++ { 1408, "b801b9b69920907cd018e8063092ede9" }, ++ { 1409, "b765f1406cfe78e238273ed01bbcaf7e" }, ++ { 2048, "1d7e2c64ac29e2b3fb4c272844ed31f5" }, ++ { 2049, "71d38fac49c6b1f4478d8d88447bcdd0" }, ++ { 2050, "141c34a5592b1bebfa731e0b23d0cdba" }, ++ { 2051, "c5e1853f21c59f5d6039bd13d4b380d8" }, ++ { 2052, "dd44a0d128b63d4b5cccd967906472d7" }, ++ { 3072, "37d158e33b21390822739d13db7b87fe" }, ++ { 3074, "aef3b209d01d39d0597fe03634bbf441" }, ++ { 3075, "335ffb428eabf210bada96d74d5a4012" }, ++ { 4048, "2434c2b43d798d2819487a886261fc64" }, ++ { 4052, "ac2fa84a8a33065b2e92e36432e861f8" }, ++ { 4058, "856781f85616c341c3533d090c1e1e84" }, ++ { 6144, "e5d134c652c18bf19833e115f7a82e9b" }, ++ { 6150, "a09a353be7795fac2401dac5601872e6" }, ++ { 6400, "08b9033ac6a1821398f50af75a2dbc83" }, ++ { 6528, "3d47aa193a8540c091e7e02f779e6751" }, ++ { 8192, "d3164e710c0626f6f395b38f20141cb7" }, ++ { 8320, "b727589d9183ff4e8491dd24466974a3" }, ++ {16384, "3f54d970793d2274d5b20d10a69938ac" }, ++ {18432, "f558511dcf81985b7a1bb57fad970531" }, ++ { 0, NULL }, ++}; ++ ++ ++/* Key = 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, ++ * 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa ++ * 0xaa, 0xaa, 0xaa, 0xaa ++ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") ++ */ ++static MV_CESA_SIZE_TEST shaMultiSizeTest402[] = ++{ ++ { 80, "e812f370e659705a1649940d1f78cd7af18affd3" }, ++ { 512, "e547f886b2c15d995ed76a8a924cb408c8080f66" }, ++ { 1000, "239443194409f1a5342ecde1a092c8f3a3ed790a" }, ++ { 1001, "f278ab9a102850a9f48dc4e9e6822afe2d0c52b5" }, ++ { 1002, "8bcc667df5ab6ece988b3af361d09747c77f4e72" }, ++ { 1003, "0fae6046c7dc1d3e356b25af836f6077a363f338" }, ++ { 1004, "0ea48401cc92ae6bc92ae76685269cb0167fbe1a" }, ++ { 1005, "ecbcd7c879b295bafcd8766cbeac58cc371e31d1" }, ++ { 1006, "eb4a4a3d07d1e9a15e6f1ab8a9c47f243e27324c" }, ++ { 1336, "f5950ee1d77c10e9011d2149699c9366fe52529c" }, ++ { 1344, "b04263604a63c351b0b3b9cf1785b4bdba6c8838" }, ++ { 1399, "8cb1cff61d5b784045974a2fc69386e3b8d24218" }, ++ { 1400, "9bb2f3fcbeddb2b90f0be797cd647334a2816d51" }, ++ { 1401, "23ae462a7a0cb440f7445791079a5d75a535dd33" }, ++ { 1402, "832974b524a4d3f9cc2f45a3cabf5ccef65cd2aa" }, ++ { 1403, "d1c683742fe404c3c20d5704a5430e7832a7ec95" }, ++ { 1404, "867c79042e64f310628e219d8b85594cd0c7adc3" }, ++ { 1405, "c9d81d49d13d94358f56ccfd61af02b36c69f7c3" }, ++ { 1406, "0df43daab2786172f9b8d07d61f14a070cf1287a" }, ++ { 1407, "0fd8f3ad7f169534b274d4c66bbddd89f759e391" }, ++ { 1408, "3987511182b18473a564436003139b808fa46343" }, ++ { 1409, "ef667e063c9e9f539a8987a8d0bd3066ee85d901" }, ++ { 2048, "921109c99f3fedaca21727156d5f2b4460175327" }, ++ { 2049, "47188600dd165eb45f27c27196d3c46f4f042c1b" }, ++ { 2050, "8831939904009338de10e7fa670847041387807d" }, ++ { 2051, "2f8ebb5db2997d614e767be1050366f3641e7520" }, ++ { 2052, "669e51cd730dae158d3bef8adba075bd95a0d011" }, ++ { 3072, "cfee66cfd83abc8451af3c96c6b35a41cc6c55f5" }, ++ { 3074, "216ea26f02976a261b7d21a4dd3085157bedfabd" }, ++ { 3075, "bd612ebba021fd8e012b14c3bd60c8c5161fabc0" }, ++ { 4048, "c2564c1fdf2d5e9d7dde7aace2643428e90662e8" }, ++ { 4052, "91ce61fe924b445dfe7b5a1dcd10a27caec16df6" }, ++ { 4058, "db2a9be5ee8124f091c7ebd699266c5de223c164" }, ++ { 6144, "855109903feae2ba3a7a05a326b8a171116eb368" }, ++ { 6150, "37520bb3a668294d9c7b073e7e3daf8fee248a78" }, ++ { 6400, "60a353c841b6d2b1a05890349dad2fa33c7536b7" }, ++ { 6528, "9e53a43a69bb42d7c8522ca8bd632e421d5edb36" }, ++ { 8192, "a918cb0da862eaea0a33ee0efea50243e6b4927c" }, ++ { 8320, "29a5dcf55d1db29cd113fcf0572ae414f1c71329" }, ++ {16384, "6fb27966138e0c8d5a0d65ace817ebd53633cee1" }, ++ {18432, "ca09900d891c7c9ae2a559b10f63a217003341c1" }, ++ { 0, NULL }, ++}; ++ ++/* Key = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, ++ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 ++ * 0x11, 0x12, 0x13, 0x14 ++ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") ++ */ ++static MV_CESA_SIZE_TEST shaMultiSizeTest404[] = ++{ ++ { 80, "beaf20a34b06a87558d156c0949bc3957d40222e" }, ++ { 512, "3353955358d886bc2940a3c7f337ff7dafb59c7b" }, ++ { 1000, "8737a542c5e9b2b6244b757ebb69d5bd602a829f" }, ++ { 1001, "fd9e7582d8a5d3c9fe3b923e4e6a41b07a1eb4d4" }, ++ { 1002, "a146d14a6fc3c274ff600568f4d75b977989e00d" }, ++ { 1003, "be22601bbc027ddef2dec97d30b3dc424fd803c5" }, ++ { 1004, "3e71fe99b2fe2b7bfdf4dbf0c7f3da25d7ea35e7" }, ++ { 1005, "2c422735d7295408fddd76f5e8a83a2a8da13df3" }, ++ { 1006, "6d875319049314b61855101a647b9ba3313428e6" }, ++ { 1336, "c1631ea80bad9dc43a180712461b65a0598c711c" }, ++ { 1344, "816069bf91d34581005746e2e0283d0f9c7b7605" }, ++ { 1399, "4e139866dc61cfcb8b67ca2ebd637b3a538593af" }, ++ { 1400, "ff2a0f8dd2b02c5417910f6f55d33a78e081a723" }, ++ { 1401, "ab00c12be62336964cbce31ae97fe2a0002984d5" }, ++ { 1402, "61349e7f999f3a1acc56c3e9a5060a9c4a7b05b6" }, ++ { 1403, "3edbc0f61e435bc1317fa27d840076093fb79353" }, ++ { 1404, "d052c6dfdbe63d45dab23ef9893e2aa4636aca1e" }, ++ { 1405, "0cc16b7388d67bf0add15a31e6e6c753cfae4987" }, ++ { 1406, "c96ba7eaad74253c38c22101b558d2850b1d1b90" }, ++ { 1407, "3445428a40d2c6556e7c55797ad8d323b61a48d9" }, ++ { 1408, "8d6444f937a09317c89834187b8ea9b8d3a8c56b" }, ++ { 1409, "c700acd3ecd19014ea2bdb4d42510c467e088475" }, ++ { 2048, "ee27d2a0cb77470c2f496212dfd68b5bb7b04e4b" }, ++ { 2049, "683762d7a02983b26a6d046e6451d9cd82c25932" }, ++ { 2050, "0fd20f1d55a9ee18363c2a6fd54aa13aee69992f" }, ++ { 2051, "86c267d8cc4bc8d59090e4f8b303da960fd228b7" }, ++ { 2052, "452395ae05b3ec503eea34f86fc0832485ad97c1" }, ++ { 3072, "75198e3cfd0b9bcff2dabdf8e38e6fdaa33ca49a" }, ++ { 3074, "4e24785ef080141ce4aab4675986d9acea624d7c" }, ++ { 3075, "3a20c5978dd637ec0e809bf84f0d9ccf30bc65bf" }, ++ { 4048, "3c32da256be7a7554922bf5fed51b0d2d09e59ad" }, ++ { 4052, "fff898426ea16e54325ae391a32c6c9bce4c23c0" }, ++ { 4058, "c800b9e562e1c91e1310116341a3c91d37f848ec" }, ++ { 6144, "d91d509d0cc4376c2d05bf9a5097717a373530e6" }, ++ { 6150, "d957030e0f13c5df07d9eec298542d8f94a07f12" }, ++ { 6400, "bb745313c3d7dc17b3f955e5534ad500a1082613" }, ++ { 6528, "77905f80d9ca82080bbb3e5654896dabfcfd1bdb" }, ++ { 8192, "5237fd9a81830c974396f99f32047586612ff3c0" }, ++ { 8320, "57668e28d5f2dba0839518a11db0f6af3d7e08bf" }, ++ {16384, "62e093fde467f0748087beea32e9af97d5c61241" }, ++ {18432, "845fb33130c7d6ea554fd5aacb9c50cf7ccb5929" }, ++ { 0, NULL }, ++}; ++ ++/* HASH-SHA1 ++ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") ++ * repeated "size" times ++ */ ++static MV_CESA_SIZE_TEST shaMultiSizeTest405[] = ++{ ++ { 80, "50abf5706a150990a08b2c5ea40fa0e585554732" }, ++ { 512, "f14516a08948fa27917a974d219741a697ba0087" }, ++ { 1000, "0bd18c378d5788817eb4f1e5dc07d867efa5cbf4" }, ++ { 1001, "ca29b85c35db1b8aef83c977893a11159d1b7aa2" }, ++ { 1002, "d83bc973eaaedb8a31437994dabbb3304b0be086" }, ++ { 1003, "2cf7bbef0acd6c00536b5c58ca470df9a3a90b6c" }, ++ { 1004, "e4375d09b1223385a8a393066f8209acfd936a80" }, ++ { 1005, "1029b38043e027745d019ce1d2d68e3d8b9d8f99" }, ++ { 1006, "deea16dcebbd8ac137e2b984deb639b9fb5e9680" }, ++ { 1336, "ea031b065fff63dcfb6a41956e4777520cdbc55d" }, ++ { 1344, "b52096c6445e6c0a8355995c70dc36ae186c863c" }, ++ { 1399, "cde2f6f8379870db4b32cf17471dc828a8dbff2b" }, ++ { 1400, "e53ff664064bc09fe5054c650806bd42d8179518" }, ++ { 1401, "d1156db5ddafcace64cdb510ff0d4af9b9a8ad64" }, ++ { 1402, "34ede0e9a909dd84a2ae291539105c0507b958e1" }, ++ { 1403, "a772ca3536da77e6ad3251e4f9e1234a4d7b87c0" }, ++ { 1404, "29740fd2b04e7a8bfd32242db6233156ad699948" }, ++ { 1405, "65b17397495b70ce4865dad93bf991b74c97cce1" }, ++ { 1406, "a7ee89cd0754061fdb91af7ea6abad2c69d542e3" }, ++ { 1407, "3eebf82f7420188e23d328b7ce93580b279a5715" }, ++ { 1408, "e08d3363a8b9a490dfb3a4c453452b8f114deeec" }, ++ { 1409, "95d74df739181a4ff30b8c39e28793a36598e924" }, ++ { 2048, "aa40262509c2abf84aab0197f83187fc90056d91" }, ++ { 2049, "7dec28ef105bc313bade8d9a7cdeac58b99de5ea" }, ++ { 2050, "d2e30f77ec81197de20f56588a156094ecb88450" }, ++ { 2051, "6b22ccc874833e96551a39da0c0edcaa0d969d92" }, ++ { 2052, "f843141e57875cd669af58744bc60aa9ea59549c" }, ++ { 3072, "09c5fedeaa62c132e673cc3c608a00142273d086" }, ++ { 3074, "b09e95eea9c7b1b007a58accec488301901a7f3d" }, ++ { 3075, "e6226b77b4ada287a8c9bbcf4ed71eec5ce632dc" }, ++ { 4048, "e99394894f855821951ddddf5bfc628547435f5c" }, ++ { 4052, "32d2f1af38be9cfba6cd03d55a254d0b3e1eb382" }, ++ { 4058, "d906552a4f2aca3a22e1fecccbcd183d7289d0ef" }, ++ { 6144, "2e7f62d35a860988e1224dc0543204af19316041" }, ++ { 6150, "d6b89698ee133df46fec9d552fadc328aa5a1b51" }, ++ { 6400, "dff50e90c46853988fa3a4b4ce5dda6945aae976" }, ++ { 6528, "9e63ec0430b96db02d38bc78357a2f63de2ab7f8" }, ++ { 8192, "971eb71ed60394d5ab5abb12e88420bdd41b5992" }, ++ { 8320, "91606a31b46afeaac965cecf87297e791b211013" }, ++ {16384, "547f830a5ec1f5f170ce818f156b1002cabc7569" }, ++ {18432, "f16f272787f3b8d539652e4dc315af6ab4fda0ef" }, ++ { 0, NULL }, ++}; ++ ++/* CryptoKey = 0x01234567, 0x89abcdef, ++ * 0x01234567, 0x89abcdef, ++ * 0x01234567, 0x89abcdef; ++ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, ++ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 ++ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") ++ * Note: only sizes aligned to 3DES block size (8 bytes) allowed ++ */ ++static MV_CESA_SIZE_TEST tripleDesMdMultiSizeTest502[] = ++{ ++ { 64, "9586962a2aaaef28803dec2e17807a7f" }, ++ { 80, "b7726a03aad490bd6c5a452a89a1b271" }, ++ { 352, "f1ed9563aecc3c0d2766eb2bed3b4e4c" }, ++ { 512, "0f9decb11ab40fe86f4d4d9397bc020e" }, ++ { 1000, "3ba69deac12cab8ff9dff7dbd9669927" }, ++ { 1336, "6cf47bf1e80e03e2c1d0945bc50d37d2" }, ++ { 1344, "4be388dab21ceb3fa1b8d302e9b821f7" }, ++ { 1400, "a58b79fb21dd9bfc6ec93e3b99fb0ef1" }, ++ { 1408, "8bc97379fc2ac3237effcdd4f7a86528" }, ++ { 2048, "1339f03ab3076f25a20bc4cba16eb5bf" }, ++ { 3072, "731204d2d90c4b36ae41f5e1fb874288" }, ++ { 4048, "c028d998cfda5642547b7e1ed5ea16e4" }, ++ { 6144, "b1b19cd910cc51bd22992f1e59f1e068" }, ++ { 6400, "44e4613496ba622deb0e7cb768135a2f" }, ++ { 6528, "3b06b0a86f8db9cd67f9448dfcf10549" }, ++ { 8192, "d581780b7163138a0f412be681457d82" }, ++ {16384, "03b8ac05527faaf1bed03df149c65ccf" }, ++ {18432, "677c8a86a41dab6c5d81b85b8fb10ff6" }, ++ { 0, NULL }, ++}; ++ ++ ++/* CryptoKey = 0x01234567, 0x89abcdef, ++ * 0x01234567, 0x89abcdef, ++ * 0x01234567, 0x89abcdef; ++ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, ++ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 ++ * 0x11, 0x12, 0x13, 0x14 ++ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") ++ * Note: only sizes aligned to 3DES block size (8 bytes) allowed ++ */ ++static MV_CESA_SIZE_TEST tripleDesShaMultiSizeTest503[] = ++{ ++ { 64, "44a1e9bcbfc1429630d9ea68b7a48b0427a684f2" }, ++ { 80, "b2ddeaca91030eab5b95a234ef2c0f6e738ff883" }, ++ { 352, "4b91864c7ff629bdff75d9726421f76705452aaf" }, ++ { 512, "6dd37faceeb2aa98ba74f4242ed6734a4d546af5" }, ++ { 1000, "463661c30300be512a9df40904f0757cde5f1141" }, ++ { 1336, "b931f831d9034fe59c65176400b039fe9c1f44a5" }, ++ { 1344, "af8866b1cd4a4887d6185bfe72470ffdfb3648e1" }, ++ { 1400, "49c6caf07296d5e31d2504d088bc5b20c3ee7cdb" }, ++ { 1408, "fcae8deedbc6ebf0763575dc7e9de075b448a0f4" }, ++ { 2048, "edece5012146c1faa0dd10f50b183ba5d2af58ac" }, ++ { 3072, "5b83625adb43a488b8d64fecf39bb766818547b7" }, ++ { 4048, "d2c533678d26c970293af60f14c8279dc708bfc9" }, ++ { 6144, "b8f67af4f991b08b725f969b049ebf813bfacc5c" }, ++ { 6400, "d9a6c7f746ac7a60ef2edbed2841cf851c25cfb0" }, ++ { 6528, "376792b8c8d18161d15579fb7829e6e3a27e9946" }, ++ { 8192, "d890eabdca195b34ef8724b28360cffa92ae5655" }, ++ {16384, "a167ee52639ec7bf19aee9c6e8f76667c14134b9" }, ++ {18432, "e4396ab56f67296b220985a12078f4a0e365d2cc" }, ++ { 0, NULL }, ++}; ++ ++/* CryptoKey = 0x01234567, 0x89abcdef, ++ * 0x01234567, 0x89abcdef, ++ * 0x01234567, 0x89abcdef ++ * IV = 0x12345678, 0x90abcdef ++ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, ++ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 ++ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") ++ * Note: only sizes aligned to 3DES block size (8 bytes) allowed ++ */ ++static MV_CESA_SIZE_TEST cbc3desMdMultiSizeTest504[] = ++{ ++ { 64, "8d10e00802460ede0058c139ba48bd2d" }, ++ { 80, "6f463057e1a90e0e91ae505b527bcec0" }, ++ { 352, "4938d48bdf86aece2c6851e7c6079788" }, ++ { 512, "516705d59f3cf810ebf2a13a23a7d42e" }, ++ { 1000, "a5a000ee5c830e67ddc6a2d2e5644b31" }, ++ { 1336, "44af60087b74ed07950088efbe3b126a" }, ++ { 1344, "1f5b39e0577920af731dabbfcf6dfc2a" }, ++ { 1400, "6804ea640e29b9cd39e08bc37dbce734" }, ++ { 1408, "4fb436624b02516fc9d1535466574bf9" }, ++ { 2048, "c909b0985c423d8d86719f701e9e83db" }, ++ { 3072, "cfe0bc34ef97213ee3d3f8b10122db21" }, ++ { 4048, "03ea10b5ae4ddeb20aed6af373082ed1" }, ++ { 6144, "b9a0ff4f87fc14b3c2dc6f0ed0998fdf" }, ++ { 6400, "6995f85d9d4985dd99e974ec7dda9dd6" }, ++ { 6528, "bbbb548ce2fa3d58467f6a6a5168a0e6" }, ++ { 8192, "afe101fbe745bb449ae4f50d10801456" }, ++ {16384, "9741706d0b1c923340c4660ff97cacdf" }, ++ {18432, "b0217becb73cb8f61fd79c7ce9d023fb" }, ++ { 0, NULL }, ++}; ++ ++ ++/* CryptoKey = 0x01234567, 0x89abcdef, ++ * 0x01234567, 0x89abcdef, ++ * 0x01234567, 0x89abcdef; ++ * IV = 0x12345678, 0x90abcdef ++ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, ++ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 ++ * 0x11, 0x12, 0x13, 0x14 ++ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") ++ * Note: only sizes aligned to 3DES block size (8 bytes) allowed ++ */ ++static MV_CESA_SIZE_TEST cbc3desShaMultiSizeTest505[] = ++{ ++ { 64, "409187e5bdb0be4a7754ca3747f7433dc4f01b98" }, ++ { 80, "1b002ed050be743aa98860cf35659646bb8efcc0" }, ++ { 352, "6cbf7ebe50fa4fa6eecc19eca23f9eae553ccfff" }, ++ { 512, "cfb5253fb4bf72b743320c30c7e48c54965853b0" }, ++ { 1000, "95e04e1ca2937e7c5a9aba9e42d2bcdb8a7af21f" }, ++ { 1336, "3b5c1f5eee5837ebf67b83ae01405542d77a6627" }, ++ { 1344, "2b3d42ab25615437f98a1ee310b81d07a02badc2" }, ++ { 1400, "7f8687df7c1af44e4baf3c934b6cca5ab6bc993e" }, ++ { 1408, "473a581c5f04f7527d50793c845471ac87e86430" }, ++ { 2048, "e41d20cae7ebe34e6e828ed62b1e5734019037bb" }, ++ { 3072, "275664afd7a561d804e6b0d204e53939cde653ae" }, ++ { 4048, "0d220cc5b34aeeb46bbbd637dde6290b5a8285a3" }, ++ { 6144, "cb393ddcc8b1c206060625b7d822ef9839e67bc5" }, ++ { 6400, "dd3317e2a627fc04800f74a4b05bfda00fab0347" }, ++ { 6528, "8a74c3b2441ab3f5a7e08895cc432566219a7c41" }, ++ { 8192, "b8e6ef3a549ed0e005bd5b8b1a5fe6689e9711a7" }, ++ {16384, "55f59404008276cdac0e2ba0d193af2d40eac5ce" }, ++ {18432, "86ae6c4fc72369a54cce39938e2d0296cd9c6ec5" }, ++ { 0, NULL }, ++}; ++ ++ ++/* CryptoKey = 0x01234567, 0x89abcdef, ++ * 0x01234567, 0x89abcdef, ++ * 0x01234567, 0x89abcdef ++ * IV = 0x12345678, 0x90abcdef ++ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, ++ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 ++ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") ++ * Note: only sizes aligned to AES block size (16 bytes) allowed ++ */ ++static MV_CESA_SIZE_TEST cbcAes128md5multiSizeTest506[] = ++{ ++ { 16, "7ca4c2ba866751598720c5c4aa0d6786" }, ++ { 64, "7dba7fb988e80da609b1fea7254bced8" }, ++ { 80, "6b6e863ac5a71d15e3e9b1c86c9ba05f" }, ++ { 352, "a1ceb9c2e3021002400d525187a9f38c" }, ++ { 512, "596c055c1c55db748379223164075641" }, ++ { 1008, "f920989c02f3b3603f53c99d89492377" }, ++ { 1344, "2e496b73759d77ed32ea222dbd2e7b41" }, ++ { 1408, "7178c046b3a8d772efdb6a71c4991ea4" }, ++ { 2048, "a917f0099c69eb94079a8421714b6aad" }, ++ { 3072, "693cd5033d7f5391d3c958519fa9e934" }, ++ { 4048, "139dca91bcff65b3c40771749052906b" }, ++ { 6144, "428d9cef6df4fb70a6e9b6bbe4819e55" }, ++ { 6400, "9c0b909e76daa811e12b1fc17000a0c4" }, ++ { 6528, "ad876f6297186a7be1f1b907ed860eda" }, ++ { 8192, "479cbbaca37dd3191ea1f3e8134a0ef4" }, ++ {16384, "60fda559c74f91df538100c9842f2f15" }, ++ {18432, "4a3eb1cba1fa45f3981270953f720c42" }, ++ { 0, NULL }, ++}; ++ ++ ++/* CryptoKey = 0x01234567, 0x89abcdef, ++ * 0x01234567, 0x89abcdef, ++ * 0x01234567, 0x89abcdef; ++ * IV = 0x12345678, 0x90abcdef ++ * MacKey = 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, ++ * 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10 ++ * 0x11, 0x12, 0x13, 0x14 ++ * InputHexStr = "31323334353637383930" (ASCII = "1234567890") ++ * Note: only sizes aligned to AES block size (16 bytes) allowed ++ */ ++static MV_CESA_SIZE_TEST cbcAes128sha1multiSizeTest507[] = ++{ ++ { 16, "9aa8dc1c45f0946daf78057fa978759c625c1fee" }, ++ { 64, "9f588fc1ede851e5f8b20256abc9979465ae2189" }, ++ { 80, "13558472d1fc1c90dffec6e5136c7203452d509b" }, ++ { 352, "6b93518e006cfaa1f7adb24615e7291fb0a27e06" }, ++ { 512, "096874951a77fbbf333e49d80c096ee2016e09bd" }, ++ { 1008, "696fc203c2e4b5ae0ec5d1db3f623c490bc6dbac" }, ++ { 1344, "79bf77509935ccd3528caaac6a5eb6481f74029b" }, ++ { 1408, "627f9462b95fc188e8cfa7eec15119bdc5d4fcf1" }, ++ { 2048, "3d50d0c005feba92fe41502d609fced9c882b4d1" }, ++ { 3072, "758807e5b983e3a91c06fb218fe0f73f77111e94" }, ++ { 4048, "ca90e85242e33f005da3504416a52098d0d31fb2" }, ++ { 6144, "8044c1d4fd06642dfc46990b4f18b61ef1e972cf" }, ++ { 6400, "166f1f4ea57409f04feba9fb1e39af0e00bd6f43" }, ++ { 6528, "0389016a39485d6e330f8b4215ddf718b404f7e9" }, ++ { 8192, "6df7ee2a8b61d6f7f860ce8dbf778f0c2a5b508b" }, ++ {16384, "a70a6d8dfa1f91ded621c3dbaed34162bc48783f" }, ++ {18432, "8dfad627922ce15df1eed10bdbed49244efa57db" }, ++ { 0, NULL }, ++}; ++ ++ ++void cesaTestPrintStatus(void); ++ ++ ++/*------------------------- LOCAL FUNCTIONs ---------------------------------*/ ++MV_STATUS testCmd(int sid, int iter, MV_CESA_COMMAND* pCmd, ++ MV_CESA_TEST_SESSION* pTestSession, MV_U8* pIV, int ivSize); ++MV_STATUS testClose(int idx); ++MV_STATUS testOpen(int idx); ++void close_session(int sid); ++void cesaTestCheckReady(const MV_CESA_RESULT *r); ++void cesaCheckReady(MV_CESA_RESULT* r); ++void printTestResults(int idx, MV_STATUS status, int checkMode); ++void cesaLastResult(void); ++void cesaTestPrintReq(int req, int offset, int size); ++ ++void cesaTestPrintStatus(void); ++void cesaTestPrintSession(int idx); ++void sizeTest(int testIdx, int iter, int checkMode); ++void multiTest(int iter, int reqSize, int checkMode); ++void oneTest(int testIdx, int caseIdx,int iter, int reqSize, int checkMode); ++void multiSizeTest(int idx, int iter, int checkMode, char* inputData); ++void cesaTest(int iter, int reqSize, int checkMode); ++void cesaOneTest(int testIdx, int caseIdx,int iter, int reqSize, int checkMode); ++void combiTest(int iter, int reqSize, int checkMode); ++void shaTest(int iter, int reqSize, int checkMode); ++void mdTest(int iter, int reqSize, int checkMode); ++void aesTest(int iter, int reqSize, int checkMode); ++void tripleDesTest(int iter, int reqSize, int checkMode); ++void desTest(int iter, int reqSize, int checkMode); ++void cesaTestStop(void); ++MV_STATUS testRun(int idx, int caseIdx, int iter,int reqSize, int checkMode); ++void cesaTestStart(int bufNum, int bufSize); ++ ++ ++static MV_U32 getRate(MV_U32* remainder) ++{ ++ MV_U32 kBits, milliSec, rate; ++ ++ milliSec = 0; ++ if( (cesaEndTicks - cesaBeginTicks) > 0) ++ { ++ milliSec = CESA_TEST_TICK_TO_MS(cesaEndTicks - cesaBeginTicks); ++ } ++ if(milliSec == 0) ++ { ++ if(remainder != NULL) ++ *remainder = 0; ++ return 0; ++ } ++ ++ kBits = (cesaIteration*cesaRateSize*8)/1000; ++ rate = kBits/milliSec; ++ if(remainder != NULL) ++ *remainder = ((kBits % milliSec)*10)/milliSec; ++ ++ return rate; ++} ++ ++static char* extractMbuf(MV_CESA_MBUF *pMbuf, ++ int offset, int size, char* hexStr) ++{ ++ mvCesaCopyFromMbuf((MV_U8*)cesaBinBuffer, pMbuf, offset, size); ++ mvBinToHex((const MV_U8*)cesaBinBuffer, hexStr, size); ++ ++ return hexStr; ++} ++ ++static MV_BOOL cesaCheckMbuf(MV_CESA_MBUF *pMbuf, ++ const char* hexString, int offset, ++ int checkSize) ++{ ++ MV_BOOL isFailed = MV_FALSE; ++ MV_STATUS status; ++ int size = strlen(hexString)/2; ++ int checkedSize = 0; ++/* ++ mvOsPrintf("cesaCheckMbuf: pMbuf=%p, offset=%d, checkSize=%d, mBufSize=%d\n", ++ pMbuf, offset, checkSize, pMbuf->mbufSize); ++*/ ++ if(pMbuf->mbufSize < (checkSize + offset)) ++ { ++ mvOsPrintf("checkSize (%d) is too large: offset=%d, mbufSize=%d\n", ++ checkSize, offset, pMbuf->mbufSize); ++ return MV_TRUE; ++ } ++ status = mvCesaCopyFromMbuf((MV_U8*)cesaBinBuffer, pMbuf, offset, checkSize); ++ if(status != MV_OK) ++ { ++ mvOsPrintf("CesaTest: Can't copy %d bytes from Mbuf=%p to checkBuf=%p\n", ++ checkSize, pMbuf, cesaBinBuffer); ++ return MV_TRUE; ++ } ++/* ++ mvDebugMemDump(cesaBinBuffer, size, 1); ++*/ ++ mvHexToBin(hexString, (MV_U8*)cesaExpBinBuffer, size); ++ ++ /* Compare buffers */ ++ while(checkSize > checkedSize) ++ { ++ size = MV_MIN(size, (checkSize - checkedSize)); ++ if(memcmp(cesaExpBinBuffer, &cesaBinBuffer[checkedSize], size) != 0) ++ { ++ mvOsPrintf("CheckMbuf failed: checkSize=%d, size=%d, checkedSize=%d\n", ++ checkSize, size, checkedSize); ++ mvDebugMemDump(&cesaBinBuffer[checkedSize], size, 1); ++ mvDebugMemDump(cesaExpBinBuffer, size, 1); ++ ++ isFailed = MV_TRUE; ++ break; ++ } ++ checkedSize += size; ++ } ++ ++ return isFailed; ++} ++ ++static MV_STATUS cesaSetMbuf(MV_CESA_MBUF *pMbuf, ++ const char* hexString, ++ int offset, int reqSize) ++{ ++ MV_STATUS status = MV_OK; ++ int copySize, size = strlen(hexString)/2; ++ ++ mvHexToBin(hexString, (MV_U8*)cesaBinBuffer, size); ++ ++ copySize = 0; ++ while(reqSize > copySize) ++ { ++ size = MV_MIN(size, (reqSize - copySize)); ++ ++ status = mvCesaCopyToMbuf((MV_U8*)cesaBinBuffer, pMbuf, offset+copySize, size); ++ if(status != MV_OK) ++ { ++ mvOsPrintf("cesaSetMbuf Error: Copy %d of %d bytes to MBuf\n", ++ copySize, reqSize); ++ break; ++ } ++ copySize += size; ++ } ++ pMbuf->mbufSize = offset+copySize; ++ return status; ++} ++ ++static MV_CESA_TEST_SESSION* getTestSessionDb(int idx, int* pTestIdx) ++{ ++ int testIdx, dbIdx = idx/100; ++ ++ if(dbIdx > MAX_TEST_TYPE) ++ { ++ mvOsPrintf("Wrong index %d - No such test type\n", idx); ++ return NULL; ++ } ++ testIdx = idx % 100; ++ ++ if(testIdx >= cesaTestsDB[dbIdx].numSessions) ++ { ++ mvOsPrintf("Wrong index %d - No such test\n", idx); ++ return NULL; ++ } ++ if(pTestIdx != NULL) ++ *pTestIdx = testIdx; ++ ++ return cesaTestsDB[dbIdx].pSessions; ++} ++ ++/* Debug */ ++void cesaTestPrintReq(int req, int offset, int size) ++{ ++ MV_CESA_MBUF* pMbuf; ++ ++ mvOsPrintf("cesaTestPrintReq: req=%d, offset=%d, size=%d\n", ++ req, offset, size); ++ mvDebugMemDump(cesaCmdRing, 128, 4); ++ ++ pMbuf = cesaCmdRing[req].pSrc; ++ mvCesaDebugMbuf("src", pMbuf, offset,size); ++ pMbuf = cesaCmdRing[req].pDst; ++ mvCesaDebugMbuf("dst", pMbuf, offset, size); ++ ++ cesaTestPrintStatus(); ++} ++ ++void cesaLastResult(void) ++{ ++ mvOsPrintf("Last Result: ReqId = %d, SessionId = %d, rc = (%d)\n", ++ (MV_U32)cesaResult.pReqPrv, cesaResult.sessionId, ++ cesaResult.retCode); ++} ++ ++void printTestResults(int idx, MV_STATUS status, int checkMode) ++{ ++ int testIdx; ++ MV_CESA_TEST_SESSION* pTestSessions = getTestSessionDb(idx, &testIdx); ++ ++ if(pTestSessions == NULL) ++ return; ++ ++ mvOsPrintf("%-35s %4dx%-4d : ", pTestSessions[testIdx].name, ++ cesaIteration, cesaReqSize); ++ if( (status == MV_OK) && ++ (cesaCryptoError == 0) && ++ (cesaError == 0) && ++ (cesaReqIdError == 0) ) ++ { ++ mvOsPrintf("Passed, Rate=%3u.%u Mbps (%5u cpp)\n", ++ cesaRate, cesaRateAfterDot, cesaEndTicks - cesaBeginTicks); ++ } ++ else ++ { ++ mvOsPrintf("Failed, Status = 0x%x\n", status); ++ if(cesaCryptoError > 0) ++ mvOsPrintf("cryptoError : %d\n", cesaCryptoError); ++ if(cesaReqIdError > 0) ++ mvOsPrintf("reqIdError : %d\n", cesaReqIdError); ++ if(cesaError > 0) ++ mvOsPrintf("cesaError : %d\n", cesaError); ++ } ++ if(cesaTestIsrMissCount > 0) ++ mvOsPrintf("cesaIsrMissed : %d\n", cesaTestIsrMissCount); ++} ++ ++void cesaCheckReady(MV_CESA_RESULT* r) ++{ ++ int reqId; ++ MV_CESA_MBUF *pMbuf; ++ MV_BOOL isFailed; ++ ++ cesaResult = *r; ++ reqId = (int)cesaResult.pReqPrv; ++ pMbuf = cesaCmdRing[reqId].pDst; ++ ++/* ++ mvOsPrintf("cesaCheckReady: reqId=%d, checkOffset=%d, checkSize=%d\n", ++ reqId, cesaCheckOffset, cesaCheckSize); ++*/ ++ /* Check expected reqId */ ++ if(reqId != cesaExpReqId) ++ { ++ cesaReqIdError++; ++/* ++ mvOsPrintf("CESA reqId Error: cbIter=%d (%d), reqId=%d, expReqId=%d\n", ++ cesaCbIter, cesaIteration, reqId, cesaExpReqId); ++*/ ++ } ++ else ++ { ++ if( (cesaCheckMode == CESA_FULL_CHECK_MODE) || ++ (cesaCheckMode == CESA_FAST_CHECK_MODE) ) ++ { ++ if(cesaResult.retCode != MV_OK) ++ { ++ cesaError++; ++ ++ mvOsPrintf("CESA Error: cbIter=%d (%d), reqId=%d, rc=%d\n", ++ cesaCbIter, cesaIteration, reqId, cesaResult.retCode); ++ } ++ else ++ { ++ if( (cesaCheckSize > 0) && (cesaOutputHexStr != NULL) ) ++ { ++ /* Check expected output */ ++ ++ isFailed = cesaCheckMbuf(pMbuf, cesaOutputHexStr, cesaCheckOffset, cesaCheckSize); ++ if(isFailed) ++ { ++ mvOsPrintf("CESA Crypto Error: cbIter=%d (%d), reqId=%d\n", ++ cesaCbIter, cesaIteration, reqId); ++ ++ CESA_TEST_DEBUG_PRINT(("Error: reqId=%d, reqSize=%d, checkOffset=%d, checkSize=%d\n", ++ reqId, cesaReqSize, cesaCheckOffset, cesaCheckSize)); ++ ++ CESA_TEST_DEBUG_PRINT(("Output str: %s\n", cesaOutputHexStr)); ++ ++ CESA_TEST_DEBUG_CODE( mvCesaDebugMbuf("error", pMbuf, 0, cesaCheckOffset+cesaCheckSize) ); ++ ++ cesaCryptoError++; ++ } ++ } ++ } ++ } ++ } ++ if(cesaCheckMode == CESA_SHOW_CHECK_MODE) ++ { ++ extractMbuf(pMbuf, cesaCheckOffset, cesaCheckSize, cesaHexBuffer); ++ mvOsPrintf("%4d, %s\n", cesaCheckOffset, cesaHexBuffer); ++ } ++ ++ cesaCbIter++; ++ if(cesaCbIter >= cesaIteration) ++ { ++ cesaCbIter = 0; ++ cesaExpReqId = 0; ++ cesaIsReady = MV_TRUE; ++ ++ cesaEndTicks = CESA_TEST_TICK_GET(); ++ cesaRate = getRate(&cesaRateAfterDot); ++ } ++ else ++ { ++ cesaExpReqId = reqId + 1; ++ if(cesaExpReqId == CESA_DEF_REQ_SIZE) ++ cesaExpReqId = 0; ++ } ++} ++ ++ ++#ifdef MV_NETBSD ++static int cesaTestReadyIsr(void *arg) ++#else ++#ifdef __KERNEL__ ++static irqreturn_t cesaTestReadyIsr( int irq , void *dev_id) ++#endif ++#ifdef MV_VXWORKS ++void cesaTestReadyIsr(void) ++#endif ++#endif ++{ ++ MV_U32 cause; ++ MV_STATUS status; ++ MV_CESA_RESULT result; ++ ++ cesaTestIsrCount++; ++ /* Clear cause register */ ++ cause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); ++ if( (cause & MV_CESA_CAUSE_ACC_DMA_ALL_MASK) == 0) ++ { ++ mvOsPrintf("cesaTestReadyIsr: cause=0x%x\n", cause); ++#ifdef MV_NETBSD ++ return 0; ++#else ++#ifdef __KERNEL__ ++ return 1; ++#else ++ return; ++#endif ++#endif ++ } ++ ++ MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); ++ ++ while(MV_TRUE) ++ { ++ /* Get Ready requests */ ++ status = mvCesaReadyGet(&result); ++ if(status == MV_OK) ++ cesaCheckReady(&result); ++ ++ break; ++ } ++ if( (cesaTestFull == 1) && (status != MV_BUSY) ) ++ { ++ cesaTestFull = 0; ++ CESA_TEST_WAKE_UP(); ++ } ++ ++#ifdef __KERNEL__ ++ return 1; ++#endif ++} ++ ++void ++cesaTestCheckReady(const MV_CESA_RESULT *r) ++{ ++ MV_CESA_RESULT result = *r; ++ ++ cesaCheckReady(&result); ++ ++ if (cesaTestFull == 1) { ++ cesaTestFull = 0; ++ CESA_TEST_WAKE_UP(); ++ } ++} ++ ++static INLINE int open_session(MV_CESA_OPEN_SESSION* pOs) ++{ ++ MV_U16 sid; ++ MV_STATUS status; ++ ++ status = mvCesaSessionOpen(pOs, (short*)&sid); ++ if(status != MV_OK) ++ { ++ mvOsPrintf("CesaTest: Can't open new session - status = 0x%x\n", ++ status); ++ return -1; ++ } ++ ++ return (int)sid; ++} ++ ++void close_session(int sid) ++{ ++ MV_STATUS status; ++ ++ status = mvCesaSessionClose(sid); ++ if(status != MV_OK) ++ { ++ mvOsPrintf("CesaTest: Can't close session %d - status = 0x%x\n", ++ sid, status); ++ } ++} ++ ++MV_STATUS testOpen(int idx) ++{ ++ MV_CESA_OPEN_SESSION os; ++ int sid, i, testIdx; ++ MV_CESA_TEST_SESSION* pTestSession; ++ MV_U16 digestSize = 0; ++ ++ pTestSession = getTestSessionDb(idx, &testIdx); ++ if(pTestSession == NULL) ++ { ++ mvOsPrintf("Test %d is not exist\n", idx); ++ return MV_BAD_PARAM; ++ } ++ pTestSession = &pTestSession[testIdx]; ++ ++ if(pTestSession->sid != -1) ++ { ++ mvOsPrintf("Session for test %d already created: sid=%d\n", ++ idx, pTestSession->sid); ++ return MV_OK; ++ } ++ ++ os.cryptoAlgorithm = pTestSession->cryptoAlgorithm; ++ os.macMode = pTestSession->macAlgorithm; ++ switch(os.macMode) ++ { ++ case MV_CESA_MAC_MD5: ++ case MV_CESA_MAC_HMAC_MD5: ++ digestSize = MV_CESA_MD5_DIGEST_SIZE; ++ break; ++ ++ case MV_CESA_MAC_SHA1: ++ case MV_CESA_MAC_HMAC_SHA1: ++ digestSize = MV_CESA_SHA1_DIGEST_SIZE; ++ break; ++ ++ case MV_CESA_MAC_NULL: ++ digestSize = 0; ++ } ++ os.cryptoMode = pTestSession->cryptoMode; ++ os.direction = pTestSession->direction; ++ os.operation = pTestSession->operation; ++ ++ for(i=0; icryptoKeySize; i++) ++ os.cryptoKey[i] = pTestSession->pCryptoKey[i]; ++ ++ os.cryptoKeyLength = pTestSession->cryptoKeySize; ++ ++ for(i=0; imacKeySize; i++) ++ os.macKey[i] = pTestSession->pMacKey[i]; ++ ++ os.macKeyLength = pTestSession->macKeySize; ++ os.digestSize = digestSize; ++ ++ sid = open_session(&os); ++ if(sid == -1) ++ { ++ mvOsPrintf("Can't open session for test %d: rc=0x%x\n", ++ idx, cesaResult.retCode); ++ return cesaResult.retCode; ++ } ++ CESA_TEST_DEBUG_PRINT(("Opened session: sid = %d\n", sid)); ++ pTestSession->sid = sid; ++ return MV_OK; ++} ++ ++MV_STATUS testClose(int idx) ++{ ++ int testIdx; ++ MV_CESA_TEST_SESSION* pTestSession; ++ ++ pTestSession = getTestSessionDb(idx, &testIdx); ++ if(pTestSession == NULL) ++ { ++ mvOsPrintf("Test %d is not exist\n", idx); ++ return MV_BAD_PARAM; ++ } ++ pTestSession = &pTestSession[testIdx]; ++ ++ if(pTestSession->sid == -1) ++ { ++ mvOsPrintf("Test session %d is not opened\n", idx); ++ return MV_NO_SUCH; ++ } ++ ++ close_session(pTestSession->sid); ++ pTestSession->sid = -1; ++ ++ return MV_OK; ++} ++ ++MV_STATUS testCmd(int sid, int iter, MV_CESA_COMMAND* pCmd, ++ MV_CESA_TEST_SESSION* pTestSession, MV_U8* pIV, int ivSize) ++{ ++ int cmdReqId = 0; ++ int i; ++ MV_STATUS rc = MV_OK; ++ char ivZeroHex[] = "0000"; ++ ++ if(iter == 0) ++ iter = CESA_DEF_ITER_NUM; ++ ++ if(pCmd == NULL) ++ { ++ mvOsPrintf("testCmd failed: pCmd=NULL\n"); ++ return MV_BAD_PARAM; ++ } ++ pCmd->sessionId = sid; ++ ++ cesaCryptoError = 0; ++ cesaReqIdError = 0; ++ cesaError = 0; ++ cesaTestIsrMissCount = 0; ++ cesaIsReady = MV_FALSE; ++ cesaIteration = iter; ++ ++ if(cesaInputHexStr == NULL) ++ cesaInputHexStr = cesaPlainHexEbc; ++ ++ for(i=0; ipSrc = (MV_CESA_MBUF*)(cesaCmdRing[i].pSrc); ++ if(pIV != NULL) ++ { ++ /* If IV from SA - set IV in Source buffer to zeros */ ++ cesaSetMbuf(pCmd->pSrc, ivZeroHex, 0, pCmd->cryptoOffset); ++ cesaSetMbuf(pCmd->pSrc, cesaInputHexStr, pCmd->cryptoOffset, ++ (cesaReqSize - pCmd->cryptoOffset)); ++ } ++ else ++ { ++ cesaSetMbuf(pCmd->pSrc, cesaInputHexStr, 0, cesaReqSize); ++ } ++ pCmd->pDst = (MV_CESA_MBUF*)(cesaCmdRing[i].pDst); ++ cesaSetMbuf(pCmd->pDst, cesaNullPlainHexText, 0, cesaReqSize); ++ ++ memcpy(&cesaCmdRing[i], pCmd, sizeof(*pCmd)); ++ } ++ ++ if(cesaCheckMode == CESA_SW_SHOW_CHECK_MODE) ++ { ++ MV_U8 pDigest[MV_CESA_MAX_DIGEST_SIZE]; ++ ++ if(pTestSession->macAlgorithm == MV_CESA_MAC_MD5) ++ { ++ mvMD5(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, pDigest); ++ mvOsPrintf("SW HASH_MD5: reqSize=%d, macLength=%d\n", ++ cesaReqSize, pCmd->macLength); ++ mvDebugMemDump(pDigest, MV_CESA_MD5_DIGEST_SIZE, 1); ++ return MV_OK; ++ } ++ if(pTestSession->macAlgorithm == MV_CESA_MAC_SHA1) ++ { ++ mvSHA1(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, pDigest); ++ mvOsPrintf("SW HASH_SHA1: reqSize=%d, macLength=%d\n", ++ cesaReqSize, pCmd->macLength); ++ mvDebugMemDump(pDigest, MV_CESA_SHA1_DIGEST_SIZE, 1); ++ return MV_OK; ++ } ++ } ++ ++ cesaBeginTicks = CESA_TEST_TICK_GET(); ++ CESA_TEST_DEBUG_CODE( memset(cesaTestTrace, 0, sizeof(cesaTestTrace)); ++ cesaTestTraceIdx = 0; ++ ); ++ ++ if(cesaCheckMode == CESA_SW_NULL_CHECK_MODE) ++ { ++ volatile MV_U8 pDigest[MV_CESA_MAX_DIGEST_SIZE]; ++ ++ for(i=0; imacAlgorithm == MV_CESA_MAC_MD5) ++ { ++ mvMD5(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, (unsigned char*)pDigest); ++ } ++ if(pTestSession->macAlgorithm == MV_CESA_MAC_SHA1) ++ { ++ mvSHA1(pCmd->pSrc->pFrags[0].bufVirtPtr, pCmd->macLength, (MV_U8 *)pDigest); ++ } ++ } ++ cesaEndTicks = CESA_TEST_TICK_GET(); ++ cesaRate = getRate(&cesaRateAfterDot); ++ cesaIsReady = MV_TRUE; ++ ++ return MV_OK; ++ } ++ ++ /*cesaTestIsrCount = 0;*/ ++ /*mvCesaDebugStatsClear();*/ ++ ++#ifndef MV_NETBSD ++ MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); ++#endif ++ ++ for(i=0; ipReqPrv = (void*)cmdReqId; ++ ++ CESA_TEST_LOCK(flags); ++ ++ rc = mvCesaAction(pCmd); ++ if(rc == MV_NO_RESOURCE) ++ cesaTestFull = 1; ++ ++ CESA_TEST_UNLOCK(flags); ++ ++ if(rc == MV_NO_RESOURCE) ++ { ++ CESA_TEST_LOCK(flags); ++ CESA_TEST_WAIT( (cesaTestFull == 0), 100); ++ CESA_TEST_UNLOCK(flags); ++ if(cesaTestFull == 1) ++ { ++ mvOsPrintf("CESA Test timeout: i=%d, iter=%d, cesaTestFull=%d\n", ++ i, iter, cesaTestFull); ++ cesaTestFull = 0; ++ return MV_TIMEOUT; ++ } ++ ++ CESA_TEST_LOCK(flags); ++ ++ rc = mvCesaAction(pCmd); ++ ++ CESA_TEST_UNLOCK(flags); ++ } ++ if( (rc != MV_OK) && (rc != MV_NO_MORE) ) ++ { ++ mvOsPrintf("mvCesaAction failed: rc=%d\n", rc); ++ return rc; ++ } ++ ++ cmdReqId++; ++ if(cmdReqId >= CESA_DEF_REQ_SIZE) ++ cmdReqId = 0; ++ ++#ifdef MV_LINUX ++ /* Reschedule each 16 requests */ ++ if( (i & 0xF) == 0) ++ schedule(); ++#endif ++ } ++ return MV_OK; ++} ++ ++void cesaTestStart(int bufNum, int bufSize) ++{ ++ int i, j, idx; ++ MV_CESA_MBUF *pMbufSrc, *pMbufDst; ++ MV_BUF_INFO *pFragsSrc, *pFragsDst; ++ char *pBuf; ++#ifndef MV_NETBSD ++ int numOfSessions, queueDepth; ++ char *pSram; ++ MV_STATUS status; ++ MV_CPU_DEC_WIN addrDecWin; ++#endif ++ ++ cesaCmdRing = mvOsMalloc(sizeof(MV_CESA_COMMAND) * CESA_DEF_REQ_SIZE); ++ if(cesaCmdRing == NULL) ++ { ++ mvOsPrintf("testStart: Can't allocate %ld bytes of memory\n", ++ sizeof(MV_CESA_COMMAND) * CESA_DEF_REQ_SIZE); ++ return; ++ } ++ memset(cesaCmdRing, 0, sizeof(MV_CESA_COMMAND) * CESA_DEF_REQ_SIZE); ++ ++ if(bufNum == 0) ++ bufNum = CESA_DEF_BUF_NUM; ++ ++ if(bufSize == 0) ++ bufSize = CESA_DEF_BUF_SIZE; ++ ++ cesaBufNum = bufNum; ++ cesaBufSize = bufSize; ++ mvOsPrintf("CESA test started: bufNum = %d, bufSize = %d\n", ++ bufNum, bufSize); ++ ++ cesaHexBuffer = mvOsMalloc(2*bufNum*bufSize); ++ if(cesaHexBuffer == NULL) ++ { ++ mvOsPrintf("testStart: Can't malloc %d bytes for cesaHexBuffer.\n", ++ 2*bufNum*bufSize); ++ return; ++ } ++ memset(cesaHexBuffer, 0, (2*bufNum*bufSize)); ++ ++ cesaBinBuffer = mvOsMalloc(bufNum*bufSize); ++ if(cesaBinBuffer == NULL) ++ { ++ mvOsPrintf("testStart: Can't malloc %d bytes for cesaBinBuffer\n", ++ bufNum*bufSize); ++ return; ++ } ++ memset(cesaBinBuffer, 0, (bufNum*bufSize)); ++ ++ cesaExpBinBuffer = mvOsMalloc(bufNum*bufSize); ++ if(cesaExpBinBuffer == NULL) ++ { ++ mvOsPrintf("testStart: Can't malloc %d bytes for cesaExpBinBuffer\n", ++ bufNum*bufSize); ++ return; ++ } ++ memset(cesaExpBinBuffer, 0, (bufNum*bufSize)); ++ ++ CESA_TEST_WAIT_INIT(); ++ ++ pMbufSrc = mvOsMalloc(sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); ++ pFragsSrc = mvOsMalloc(sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); ++ ++ pMbufDst = mvOsMalloc(sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); ++ pFragsDst = mvOsMalloc(sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); ++ ++ if( (pMbufSrc == NULL) || (pFragsSrc == NULL) || ++ (pMbufDst == NULL) || (pFragsDst == NULL) ) ++ { ++ mvOsPrintf("testStart: Can't malloc Src and Dst pMbuf and pFrags structures.\n"); ++ /* !!!! Dima cesaTestCleanup();*/ ++ return; ++ } ++ ++ memset(pMbufSrc, 0, sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); ++ memset(pFragsSrc, 0, sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); ++ ++ memset(pMbufDst, 0, sizeof(MV_CESA_MBUF) * CESA_DEF_REQ_SIZE); ++ memset(pFragsDst, 0, sizeof(MV_BUF_INFO) * bufNum * CESA_DEF_REQ_SIZE); ++ ++ mvOsPrintf("Cesa Test Start: pMbufSrc=%p, pFragsSrc=%p, pMbufDst=%p, pFragsDst=%p\n", ++ pMbufSrc, pFragsSrc, pMbufDst, pFragsDst); ++ ++ idx = 0; ++ for(i=0; ipFrags = &pFragsSrc[idx]; ++ cesaCmdRing[i].pSrc->numFrags = bufNum; ++ cesaCmdRing[i].pSrc->mbufSize = 0; ++ ++ cesaCmdRing[i].pDst = &pMbufDst[i]; ++ cesaCmdRing[i].pDst->pFrags = &pFragsDst[idx]; ++ cesaCmdRing[i].pDst->numFrags = bufNum; ++ cesaCmdRing[i].pDst->mbufSize = 0; ++ ++ for(j=0; jpFrags[j].bufVirtPtr = (MV_U8*)pBuf; ++ cesaCmdRing[i].pSrc->pFrags[j].bufSize = bufSize; ++ pBuf += bufSize; ++ cesaCmdRing[i].pDst->pFrags[j].bufVirtPtr = (MV_U8*)pBuf; ++ cesaCmdRing[i].pDst->pFrags[j].bufSize = bufSize; ++ pBuf += bufSize; ++ } ++ idx += bufNum; ++ } ++ ++#ifndef MV_NETBSD ++ if (mvCpuIfTargetWinGet(CRYPT_ENG, &addrDecWin) == MV_OK) ++ pSram = (char*)addrDecWin.addrWin.baseLow; ++ else ++ { ++ mvOsPrintf("mvCesaInit: ERR. mvCpuIfTargetWinGet failed\n"); ++ return; ++ } ++ ++#ifdef MV_CESA_NO_SRAM ++ pSram = mvOsMalloc(4*1024+8); ++ if(pSram == NULL) ++ { ++ mvOsPrintf("CesaTest: can't allocate %d bytes for SRAM simulation\n", ++ 4*1024+8); ++ /* !!!! Dima cesaTestCleanup();*/ ++ return; ++ } ++ pSram = (MV_U8*)MV_ALIGN_UP((MV_U32)pSram, 8); ++#endif /* MV_CESA_NO_SRAM */ ++ ++ numOfSessions = CESA_DEF_SESSION_NUM; ++ queueDepth = CESA_DEF_REQ_SIZE - MV_CESA_MAX_CHAN; ++ ++ status = mvCesaInit(numOfSessions, queueDepth, pSram, NULL); ++ if(status != MV_OK) ++ { ++ mvOsPrintf("mvCesaInit is Failed: status = 0x%x\n", status); ++ /* !!!! Dima cesaTestCleanup();*/ ++ return; ++ } ++#endif /* !MV_NETBSD */ ++ ++ /* Prepare data for tests */ ++ for(i=0; i<50; i++) ++ strcat((char*)cesaDataHexStr3, "dd"); ++ ++ strcpy((char*)cesaDataAndMd5digest3, cesaDataHexStr3); ++ strcpy((char*)cesaDataAndSha1digest3, cesaDataHexStr3); ++ ++ /* Digest must be 8 byte aligned */ ++ for(; i<56; i++) ++ { ++ strcat((char*)cesaDataAndMd5digest3, "00"); ++ strcat((char*)cesaDataAndSha1digest3, "00"); ++ } ++ strcat((char*)cesaDataAndMd5digest3, cesaHmacMd5digestHex3); ++ strcat((char*)cesaDataAndSha1digest3, cesaHmacSha1digestHex3); ++ ++#ifndef MV_NETBSD ++ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); ++ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, MV_CESA_CAUSE_ACC_DMA_MASK); ++#endif ++ ++#ifdef MV_VXWORKS ++ { ++ MV_STATUS status; ++ ++ status = intConnect((VOIDFUNCPTR *)INT_LVL_CESA, cesaTestReadyIsr, (int)NULL); ++ if (status != OK) ++ { ++ mvOsPrintf("CESA: Can't connect CESA (%d) interrupt, status=0x%x \n", ++ INT_LVL_CESA, status); ++ /* !!!! Dima cesaTestCleanup();*/ ++ return; ++ } ++ cesaSemId = semMCreate(SEM_Q_PRIORITY | SEM_INVERSION_SAFE | SEM_DELETE_SAFE); ++ if(cesaSemId == NULL) ++ { ++ mvOsPrintf("cesaTestStart: Can't create semaphore\n"); ++ return; ++ } ++ intEnable(INT_LVL_CESA); ++ } ++#endif /* MV_VXWORKS */ ++ ++#if !defined(MV_NETBSD) && defined(__KERNEL__) ++ if( request_irq(CESA_IRQ, cesaTestReadyIsr, (SA_INTERRUPT) , "cesa_test", NULL ) ) ++ { ++ mvOsPrintf( "cannot assign irq\n" ); ++ /* !!!! Dima cesaTestCleanup();*/ ++ return; ++ } ++ spin_lock_init( &cesaLock ); ++#endif ++} ++ ++MV_STATUS testRun(int idx, int caseIdx, int iter, ++ int reqSize, int checkMode) ++{ ++ int testIdx, count, sid, digestSize; ++ int blockSize; ++ MV_CESA_TEST_SESSION* pTestSession; ++ MV_CESA_COMMAND cmd; ++ MV_STATUS status; ++ ++ memset(&cmd, 0, sizeof(cmd)); ++ ++ pTestSession = getTestSessionDb(idx, &testIdx); ++ if(pTestSession == NULL) ++ { ++ mvOsPrintf("Test %d is not exist\n", idx); ++ return MV_BAD_PARAM; ++ } ++ pTestSession = &pTestSession[testIdx]; ++ ++ sid = pTestSession->sid; ++ if(sid == -1) ++ { ++ mvOsPrintf("Test %d is not opened\n", idx); ++ return MV_BAD_STATE; ++ } ++ switch(pTestSession->cryptoAlgorithm) ++ { ++ case MV_CESA_CRYPTO_DES: ++ case MV_CESA_CRYPTO_3DES: ++ blockSize = MV_CESA_DES_BLOCK_SIZE; ++ break; ++ ++ case MV_CESA_CRYPTO_AES: ++ blockSize = MV_CESA_AES_BLOCK_SIZE; ++ break; ++ ++ case MV_CESA_CRYPTO_NULL: ++ blockSize = 0; ++ break; ++ ++ default: ++ mvOsPrintf("cesaTestRun: Bad CryptoAlgorithm=%d\n", ++ pTestSession->cryptoAlgorithm); ++ return MV_BAD_PARAM; ++ } ++ switch(pTestSession->macAlgorithm) ++ { ++ case MV_CESA_MAC_MD5: ++ case MV_CESA_MAC_HMAC_MD5: ++ digestSize = MV_CESA_MD5_DIGEST_SIZE; ++ break; ++ ++ case MV_CESA_MAC_SHA1: ++ case MV_CESA_MAC_HMAC_SHA1: ++ digestSize = MV_CESA_SHA1_DIGEST_SIZE; ++ break; ++ default: ++ digestSize = 0; ++ } ++ ++ if(iter == 0) ++ iter = CESA_DEF_ITER_NUM; ++ ++ if(pTestSession->direction == MV_CESA_DIR_ENCODE) ++ { ++ cesaOutputHexStr = cesaTestCases[caseIdx].cipherHexStr; ++ cesaInputHexStr = cesaTestCases[caseIdx].plainHexStr; ++ } ++ else ++ { ++ cesaOutputHexStr = cesaTestCases[caseIdx].plainHexStr; ++ cesaInputHexStr = cesaTestCases[caseIdx].cipherHexStr; ++ } ++ ++ cmd.sessionId = sid; ++ if(checkMode == CESA_FAST_CHECK_MODE) ++ { ++ cmd.cryptoLength = cesaTestCases[caseIdx].cryptoLength; ++ cmd.macLength = cesaTestCases[caseIdx].macLength; ++ } ++ else ++ { ++ cmd.cryptoLength = reqSize; ++ cmd.macLength = reqSize; ++ } ++ cesaRateSize = cmd.cryptoLength; ++ cesaReqSize = cmd.cryptoLength; ++ cmd.cryptoOffset = 0; ++ if(pTestSession->operation != MV_CESA_MAC_ONLY) ++ { ++ if( (pTestSession->cryptoMode == MV_CESA_CRYPTO_CBC) || ++ (pTestSession->cryptoMode == MV_CESA_CRYPTO_CTR) ) ++ { ++ cmd.ivOffset = 0; ++ cmd.cryptoOffset = blockSize; ++ if(cesaTestCases[caseIdx].pCryptoIV == NULL) ++ { ++ cmd.ivFromUser = 1; ++ } ++ else ++ { ++ cmd.ivFromUser = 0; ++ mvCesaCryptoIvSet(cesaTestCases[caseIdx].pCryptoIV, blockSize); ++ } ++ cesaReqSize = cmd.cryptoOffset + cmd.cryptoLength; ++ } ++ } ++ ++/* ++ mvOsPrintf("ivFromUser=%d, cryptoLength=%d, cesaReqSize=%d, cryptoOffset=%d\n", ++ cmd.ivFromUser, cmd.cryptoLength, cesaReqSize, cmd.cryptoOffset); ++*/ ++ if(pTestSession->operation != MV_CESA_CRYPTO_ONLY) ++ { ++ cmd.macOffset = cmd.cryptoOffset; ++ ++ if(cesaTestCases[caseIdx].digestOffset == -1) ++ { ++ cmd.digestOffset = cmd.macOffset + cmd.macLength; ++ cmd.digestOffset = MV_ALIGN_UP(cmd.digestOffset, 8); ++ } ++ else ++ { ++ cmd.digestOffset = cesaTestCases[caseIdx].digestOffset; ++ } ++ if( (cmd.digestOffset + digestSize) > cesaReqSize) ++ cesaReqSize = cmd.digestOffset + digestSize; ++ } ++ ++ cesaCheckMode = checkMode; ++ ++ if(checkMode == CESA_NULL_CHECK_MODE) ++ { ++ cesaCheckSize = 0; ++ cesaCheckOffset = 0; ++ } ++ else ++ { ++ if(pTestSession->operation == MV_CESA_CRYPTO_ONLY) ++ { ++ cesaCheckOffset = 0; ++ cesaCheckSize = cmd.cryptoLength; ++ } ++ else ++ { ++ cesaCheckSize = digestSize; ++ cesaCheckOffset = cmd.digestOffset; ++ } ++ } ++/* ++ mvOsPrintf("reqSize=%d, checkSize=%d, checkOffset=%d, checkMode=%d\n", ++ cesaReqSize, cesaCheckSize, cesaCheckOffset, cesaCheckMode); ++ ++ mvOsPrintf("blockSize=%d, ivOffset=%d, ivFromUser=%d, crOffset=%d, crLength=%d\n", ++ blockSize, cmd.ivOffset, cmd.ivFromUser, ++ cmd.cryptoOffset, cmd.cryptoLength); ++ ++ mvOsPrintf("macOffset=%d, digestOffset=%d, macLength=%d\n", ++ cmd.macOffset, cmd.digestOffset, cmd.macLength); ++*/ ++ status = testCmd(sid, iter, &cmd, pTestSession, ++ cesaTestCases[caseIdx].pCryptoIV, blockSize); ++ ++ if(status != MV_OK) ++ return status; ++ ++ /* Wait when all callbacks is received */ ++ count = 0; ++ while(cesaIsReady == MV_FALSE) ++ { ++ mvOsSleep(10); ++ count++; ++ if(count > 100) ++ { ++ mvOsPrintf("testRun: Timeout occured\n"); ++ return MV_TIMEOUT; ++ } ++ } ++ ++ return MV_OK; ++} ++ ++ ++void cesaTestStop(void) ++{ ++ MV_CESA_MBUF *pMbufSrc, *pMbufDst; ++ MV_BUF_INFO *pFragsSrc, *pFragsDst; ++ int i; ++ ++ /* Release all allocated memories */ ++ pMbufSrc = (MV_CESA_MBUF*)(cesaCmdRing[0].pSrc); ++ pFragsSrc = cesaCmdRing[0].pSrc->pFrags; ++ ++ pMbufDst = (MV_CESA_MBUF*)(cesaCmdRing[0].pDst); ++ pFragsDst = cesaCmdRing[0].pDst->pFrags; ++ ++ mvOsFree(pMbufSrc); ++ mvOsFree(pMbufDst); ++ mvOsFree(pFragsSrc); ++ mvOsFree(pFragsDst); ++ ++ for(i=0; i 0) ++ cryptoError++; ++ if(cesaReqIdError > 0) ++ reqIdError++; ++ ++ testClose(idx); ++ } ++ } ++ if(cryptoError > 0) ++ mvOsPrintf("cryptoError : %d\n", cryptoError); ++ if(reqIdError > 0) ++ mvOsPrintf("reqIdError : %d\n", reqIdError); ++ ++ if(openErrors > 0) ++ { ++ mvOsPrintf("Open Errors = %d\n", openErrors); ++ for(i=0; i<100; i++) ++ { ++ if(openErrDisp[i] != 0) ++ mvOsPrintf("Error %d - occurs %d times\n", i, openErrDisp[i]); ++ } ++ } ++} ++ ++ ++void loopback_test(int idx, int iter, int size, char* pPlainData) ++{ ++} ++ ++ ++#if defined(MV_VXWORKS) ++int testMode = 0; ++unsigned __TASKCONV cesaTask(void* args) ++{ ++ int reqSize = cesaReqSize; ++ ++ if(testMode == 0) ++ { ++ cesaOneTest(cesaTestIdx, cesaCaseIdx, cesaIteration, ++ reqSize, cesaCheckMode); ++ } ++ else ++ { ++ if(testMode == 1) ++ { ++ cesaTest(cesaIteration, reqSize, cesaCheckMode); ++ combiTest(cesaIteration, reqSize, cesaCheckMode); ++ } ++ else ++ { ++ multiSizeTest(cesaIdx, cesaIteration, cesaCheckMode, NULL); ++ } ++ } ++ return 0; ++} ++ ++void oneTest(int testIdx, int caseIdx, ++ int iter, int reqSize, int checkMode) ++{ ++ long rc; ++ ++ cesaIteration = iter; ++ cesaReqSize = cesaRateSize = reqSize; ++ cesaCheckMode = checkMode; ++ testMode = 0; ++ cesaTestIdx = testIdx; ++ cesaCaseIdx = caseIdx; ++ rc = mvOsTaskCreate("CESA_T", 100, 4*1024, cesaTask, NULL, &cesaTaskId); ++ if (rc != MV_OK) ++ { ++ mvOsPrintf("hMW: Can't create CESA multiCmd test task, rc = %ld\n", rc); ++ } ++} ++ ++void multiTest(int iter, int reqSize, int checkMode) ++{ ++ long rc; ++ ++ cesaIteration = iter; ++ cesaCheckMode = checkMode; ++ cesaReqSize = reqSize; ++ testMode = 1; ++ rc = mvOsTaskCreate("CESA_T", 100, 4*1024, cesaTask, NULL, &cesaTaskId); ++ if (rc != MV_OK) ++ { ++ mvOsPrintf("hMW: Can't create CESA multiCmd test task, rc = %ld\n", rc); ++ } ++} ++ ++void sizeTest(int testIdx, int iter, int checkMode) ++{ ++ long rc; ++ ++ cesaIteration = iter; ++ cesaCheckMode = checkMode; ++ testMode = 2; ++ cesaIdx = testIdx; ++ rc = mvOsTaskCreate("CESA_T", 100, 4*1024, cesaTask, NULL, &cesaTaskId); ++ if (rc != MV_OK) ++ { ++ mvOsPrintf("hMW: Can't create CESA test task, rc = %ld\n", rc); ++ } ++} ++ ++#endif /* MV_VXWORKS */ ++ ++extern void mvCesaDebugSA(short sid, int mode); ++void cesaTestPrintSession(int idx) ++{ ++ int testIdx; ++ MV_CESA_TEST_SESSION* pTestSession; ++ ++ pTestSession = getTestSessionDb(idx, &testIdx); ++ if(pTestSession == NULL) ++ { ++ mvOsPrintf("Test %d is not exist\n", idx); ++ return; ++ } ++ pTestSession = &pTestSession[testIdx]; ++ ++ if(pTestSession->sid == -1) ++ { ++ mvOsPrintf("Test session %d is not opened\n", idx); ++ return; ++ } ++ ++ mvCesaDebugSA(pTestSession->sid, 1); ++} ++ ++void cesaTestPrintStatus(void) ++{ ++ mvOsPrintf("\n\t Cesa Test Status\n\n"); ++ ++ mvOsPrintf("isrCount=%d\n", ++ cesaTestIsrCount); ++ ++#ifdef CESA_TEST_DEBUG ++ { ++ int i, j; ++ j = cesaTestTraceIdx; ++ mvOsPrintf("No Type Cause rCause iCause Res Time pReady pProc pEmpty\n"); ++ for(i=0; itable = mvOsMalloc(numOfEntries*sizeof(MV_LRU_ENTRY)); ++ if(pLruCache->table == NULL) ++ { ++ mvOsFree(pLruCache); ++ return NULL; ++ } ++ memset(pLruCache->table, 0, numOfEntries*sizeof(MV_LRU_ENTRY)); ++ pLruCache->tableSize = numOfEntries; ++ ++ for(i=0; itable[i].next = i+1; ++ pLruCache->table[i].prev = i-1; ++ } ++ pLruCache->least = 0; ++ pLruCache->most = numOfEntries-1; ++ ++ return pLruCache; ++} ++ ++void mvLruCacheFinish(MV_LRU_CACHE* pLruCache) ++{ ++ mvOsFree(pLruCache->table); ++ mvOsFree(pLruCache); ++} ++ ++/* Update LRU cache database after using cache Index */ ++void mvLruCacheIdxUpdate(MV_LRU_CACHE* pLruHndl, int cacheIdx) ++{ ++ int prev, next; ++ ++ if(cacheIdx == pLruHndl->most) ++ return; ++ ++ next = pLruHndl->table[cacheIdx].next; ++ if(cacheIdx == pLruHndl->least) ++ { ++ pLruHndl->least = next; ++ } ++ else ++ { ++ prev = pLruHndl->table[cacheIdx].prev; ++ ++ pLruHndl->table[next].prev = prev; ++ pLruHndl->table[prev].next = next; ++ } ++ ++ pLruHndl->table[pLruHndl->most].next = cacheIdx; ++ pLruHndl->table[cacheIdx].prev = pLruHndl->most; ++ pLruHndl->most = cacheIdx; ++} ++ ++/* Delete LRU cache entry */ ++void mvLruCacheIdxDelete(MV_LRU_CACHE* pLruHndl, int cacheIdx) ++{ ++ int prev, next; ++ ++ if(cacheIdx == pLruHndl->least) ++ return; ++ ++ prev = pLruHndl->table[cacheIdx].prev; ++ if(cacheIdx == pLruHndl->most) ++ { ++ pLruHndl->most = prev; ++ } ++ else ++ { ++ next = pLruHndl->table[cacheIdx].next; ++ ++ pLruHndl->table[next].prev = prev; ++ pLruHndl->table[prev].next = next; ++ } ++ pLruHndl->table[pLruHndl->least].prev = cacheIdx; ++ pLruHndl->table[cacheIdx].next = pLruHndl->least; ++ pLruHndl->least = cacheIdx; ++} +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/cesa/mvLru.h linux-3.1.4/crypto/ocf/kirkwood/cesa/mvLru.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/cesa/mvLru.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/cesa/mvLru.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,112 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++/******************************************************************************* ++* mvLru.h - Header File for Least Recently Used Cache algorithm ++* ++* DESCRIPTION: ++* This header file contains macros typedefs and function declaration for ++* the Least Recently Used Cache algorithm. ++* ++*******************************************************************************/ ++ ++#ifndef __mvLru_h__ ++#define __mvLru_h__ ++ ++ ++typedef struct ++{ ++ int next; ++ int prev; ++} MV_LRU_ENTRY; ++ ++typedef struct ++{ ++ int least; ++ int most; ++ MV_LRU_ENTRY* table; ++ int tableSize; ++ ++}MV_LRU_CACHE; ++ ++ ++/* Find Cache index for replacement LRU */ ++static INLINE int mvLruCacheIdxFind(MV_LRU_CACHE* pLruHndl) ++{ ++ return pLruHndl->least; ++} ++ ++/* Init LRU cache module */ ++MV_LRU_CACHE* mvLruCacheInit(int numOfEntries); ++ ++/* Finish LRU cache module */ ++void mvLruCacheFinish(MV_LRU_CACHE* pLruHndl); ++ ++/* Update LRU cache database after using cache Index */ ++void mvLruCacheIdxUpdate(MV_LRU_CACHE* pLruHndl, int cacheIdx); ++ ++/* Delete LRU cache entry */ ++void mvLruCacheIdxDelete(MV_LRU_CACHE* pLruHndl, int cacheIdx); ++ ++ ++#endif /* __mvLru_h__ */ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/cesa/mvMD5.c linux-3.1.4/crypto/ocf/kirkwood/cesa/mvMD5.c +--- linux-3.1.4.orig/crypto/ocf/kirkwood/cesa/mvMD5.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/cesa/mvMD5.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,349 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#include "mvOs.h" ++#include "mvMD5.h" ++ ++static void mvMD5Transform(MV_U32 buf[4], MV_U32 const in[MV_MD5_MAC_LEN]); ++ ++#ifdef MV_CPU_LE ++#define mvByteReverse(buf, len) /* Nothing */ ++#else ++static void mvByteReverse(unsigned char *buf, unsigned longs); ++ ++/* ++ * Note: this code is harmless on little-endian machines. ++ */ ++static void mvByteReverse(unsigned char *buf, unsigned longs) ++{ ++ MV_U32 t; ++ ++ do ++ { ++ t = (MV_U32) ((unsigned) buf[3] << 8 | buf[2]) << 16 | ++ ((unsigned) buf[1] << 8 | buf[0]); ++ *(MV_U32 *) buf = t; ++ buf += 4; ++ } while (--longs); ++} ++#endif ++ ++/* ++ * Start MD5 accumulation. Set bit count to 0 and buffer to mysterious ++ * initialization constants. ++ */ ++void mvMD5Init(MV_MD5_CONTEXT *ctx) ++{ ++ ctx->buf[0] = 0x67452301; ++ ctx->buf[1] = 0xefcdab89; ++ ctx->buf[2] = 0x98badcfe; ++ ctx->buf[3] = 0x10325476; ++ ++ ctx->bits[0] = 0; ++ ctx->bits[1] = 0; ++} ++ ++/* ++ * Update context to reflect the concatenation of another buffer full ++ * of bytes. ++ */ ++void mvMD5Update(MV_MD5_CONTEXT *ctx, unsigned char const *buf, unsigned len) ++{ ++ MV_U32 t; ++ ++ /* Update bitcount */ ++ ++ t = ctx->bits[0]; ++ if ((ctx->bits[0] = t + ((MV_U32) len << 3)) < t) ++ ctx->bits[1]++; /* Carry from low to high */ ++ ctx->bits[1] += len >> 29; ++ ++ t = (t >> 3) & 0x3f; /* Bytes already in shsInfo->data */ ++ ++ /* Handle any leading odd-sized chunks */ ++ ++ if (t) ++ { ++ unsigned char *p = (unsigned char *) ctx->in + t; ++ ++ t = 64 - t; ++ if (len < t) ++ { ++ memcpy(p, buf, len); ++ return; ++ } ++ memcpy(p, buf, t); ++ mvByteReverse(ctx->in, MV_MD5_MAC_LEN); ++ mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in); ++ buf += t; ++ len -= t; ++ } ++ /* Process data in 64-byte chunks */ ++ ++ while (len >= 64) ++ { ++ memcpy(ctx->in, buf, 64); ++ mvByteReverse(ctx->in, MV_MD5_MAC_LEN); ++ mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in); ++ buf += 64; ++ len -= 64; ++ } ++ ++ /* Handle any remaining bytes of data. */ ++ ++ memcpy(ctx->in, buf, len); ++} ++ ++/* ++ * Final wrapup - pad to 64-byte boundary with the bit pattern ++ * 1 0* (64-bit count of bits processed, MSB-first) ++ */ ++void mvMD5Final(unsigned char digest[MV_MD5_MAC_LEN], MV_MD5_CONTEXT *ctx) ++{ ++ unsigned count; ++ unsigned char *p; ++ ++ /* Compute number of bytes mod 64 */ ++ count = (ctx->bits[0] >> 3) & 0x3F; ++ ++ /* Set the first char of padding to 0x80. This is safe since there is ++ always at least one byte free */ ++ p = ctx->in + count; ++ *p++ = 0x80; ++ ++ /* Bytes of padding needed to make 64 bytes */ ++ count = 64 - 1 - count; ++ ++ /* Pad out to 56 mod 64 */ ++ if (count < 8) ++ { ++ /* Two lots of padding: Pad the first block to 64 bytes */ ++ memset(p, 0, count); ++ mvByteReverse(ctx->in, MV_MD5_MAC_LEN); ++ mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in); ++ ++ /* Now fill the next block with 56 bytes */ ++ memset(ctx->in, 0, 56); ++ } ++ else ++ { ++ /* Pad block to 56 bytes */ ++ memset(p, 0, count - 8); ++ } ++ mvByteReverse(ctx->in, 14); ++ ++ /* Append length in bits and transform */ ++ ((MV_U32 *) ctx->in)[14] = ctx->bits[0]; ++ ((MV_U32 *) ctx->in)[15] = ctx->bits[1]; ++ ++ mvMD5Transform(ctx->buf, (MV_U32 *) ctx->in); ++ mvByteReverse((unsigned char *) ctx->buf, 4); ++ memcpy(digest, ctx->buf, MV_MD5_MAC_LEN); ++ memset(ctx, 0, sizeof(ctx)); /* In case it's sensitive */ ++} ++ ++/* The four core functions - F1 is optimized somewhat */ ++ ++/* #define F1(x, y, z) (x & y | ~x & z) */ ++#define F1(x, y, z) (z ^ (x & (y ^ z))) ++#define F2(x, y, z) F1(z, x, y) ++#define F3(x, y, z) (x ^ y ^ z) ++#define F4(x, y, z) (y ^ (x | ~z)) ++ ++/* This is the central step in the MD5 algorithm. */ ++#define MD5STEP(f, w, x, y, z, data, s) \ ++ ( w += f(x, y, z) + data, w = w<>(32-s), w += x ) ++ ++/* ++ * The core of the MD5 algorithm, this alters an existing MD5 hash to ++ * reflect the addition of 16 longwords of new data. MD5Update blocks ++ * the data and converts bytes into longwords for this routine. ++ */ ++static void mvMD5Transform(MV_U32 buf[4], MV_U32 const in[MV_MD5_MAC_LEN]) ++{ ++ register MV_U32 a, b, c, d; ++ ++ a = buf[0]; ++ b = buf[1]; ++ c = buf[2]; ++ d = buf[3]; ++ ++ MD5STEP(F1, a, b, c, d, in[0] + 0xd76aa478, 7); ++ MD5STEP(F1, d, a, b, c, in[1] + 0xe8c7b756, 12); ++ MD5STEP(F1, c, d, a, b, in[2] + 0x242070db, 17); ++ MD5STEP(F1, b, c, d, a, in[3] + 0xc1bdceee, 22); ++ MD5STEP(F1, a, b, c, d, in[4] + 0xf57c0faf, 7); ++ MD5STEP(F1, d, a, b, c, in[5] + 0x4787c62a, 12); ++ MD5STEP(F1, c, d, a, b, in[6] + 0xa8304613, 17); ++ MD5STEP(F1, b, c, d, a, in[7] + 0xfd469501, 22); ++ MD5STEP(F1, a, b, c, d, in[8] + 0x698098d8, 7); ++ MD5STEP(F1, d, a, b, c, in[9] + 0x8b44f7af, 12); ++ MD5STEP(F1, c, d, a, b, in[10] + 0xffff5bb1, 17); ++ MD5STEP(F1, b, c, d, a, in[11] + 0x895cd7be, 22); ++ MD5STEP(F1, a, b, c, d, in[12] + 0x6b901122, 7); ++ MD5STEP(F1, d, a, b, c, in[13] + 0xfd987193, 12); ++ MD5STEP(F1, c, d, a, b, in[14] + 0xa679438e, 17); ++ MD5STEP(F1, b, c, d, a, in[15] + 0x49b40821, 22); ++ ++ MD5STEP(F2, a, b, c, d, in[1] + 0xf61e2562, 5); ++ MD5STEP(F2, d, a, b, c, in[6] + 0xc040b340, 9); ++ MD5STEP(F2, c, d, a, b, in[11] + 0x265e5a51, 14); ++ MD5STEP(F2, b, c, d, a, in[0] + 0xe9b6c7aa, 20); ++ MD5STEP(F2, a, b, c, d, in[5] + 0xd62f105d, 5); ++ MD5STEP(F2, d, a, b, c, in[10] + 0x02441453, 9); ++ MD5STEP(F2, c, d, a, b, in[15] + 0xd8a1e681, 14); ++ MD5STEP(F2, b, c, d, a, in[4] + 0xe7d3fbc8, 20); ++ MD5STEP(F2, a, b, c, d, in[9] + 0x21e1cde6, 5); ++ MD5STEP(F2, d, a, b, c, in[14] + 0xc33707d6, 9); ++ MD5STEP(F2, c, d, a, b, in[3] + 0xf4d50d87, 14); ++ MD5STEP(F2, b, c, d, a, in[8] + 0x455a14ed, 20); ++ MD5STEP(F2, a, b, c, d, in[13] + 0xa9e3e905, 5); ++ MD5STEP(F2, d, a, b, c, in[2] + 0xfcefa3f8, 9); ++ MD5STEP(F2, c, d, a, b, in[7] + 0x676f02d9, 14); ++ MD5STEP(F2, b, c, d, a, in[12] + 0x8d2a4c8a, 20); ++ ++ MD5STEP(F3, a, b, c, d, in[5] + 0xfffa3942, 4); ++ MD5STEP(F3, d, a, b, c, in[8] + 0x8771f681, 11); ++ MD5STEP(F3, c, d, a, b, in[11] + 0x6d9d6122, 16); ++ MD5STEP(F3, b, c, d, a, in[14] + 0xfde5380c, 23); ++ MD5STEP(F3, a, b, c, d, in[1] + 0xa4beea44, 4); ++ MD5STEP(F3, d, a, b, c, in[4] + 0x4bdecfa9, 11); ++ MD5STEP(F3, c, d, a, b, in[7] + 0xf6bb4b60, 16); ++ MD5STEP(F3, b, c, d, a, in[10] + 0xbebfbc70, 23); ++ MD5STEP(F3, a, b, c, d, in[13] + 0x289b7ec6, 4); ++ MD5STEP(F3, d, a, b, c, in[0] + 0xeaa127fa, 11); ++ MD5STEP(F3, c, d, a, b, in[3] + 0xd4ef3085, 16); ++ MD5STEP(F3, b, c, d, a, in[6] + 0x04881d05, 23); ++ MD5STEP(F3, a, b, c, d, in[9] + 0xd9d4d039, 4); ++ MD5STEP(F3, d, a, b, c, in[12] + 0xe6db99e5, 11); ++ MD5STEP(F3, c, d, a, b, in[15] + 0x1fa27cf8, 16); ++ MD5STEP(F3, b, c, d, a, in[2] + 0xc4ac5665, 23); ++ ++ MD5STEP(F4, a, b, c, d, in[0] + 0xf4292244, 6); ++ MD5STEP(F4, d, a, b, c, in[7] + 0x432aff97, 10); ++ MD5STEP(F4, c, d, a, b, in[14] + 0xab9423a7, 15); ++ MD5STEP(F4, b, c, d, a, in[5] + 0xfc93a039, 21); ++ MD5STEP(F4, a, b, c, d, in[12] + 0x655b59c3, 6); ++ MD5STEP(F4, d, a, b, c, in[3] + 0x8f0ccc92, 10); ++ MD5STEP(F4, c, d, a, b, in[10] + 0xffeff47d, 15); ++ MD5STEP(F4, b, c, d, a, in[1] + 0x85845dd1, 21); ++ MD5STEP(F4, a, b, c, d, in[8] + 0x6fa87e4f, 6); ++ MD5STEP(F4, d, a, b, c, in[15] + 0xfe2ce6e0, 10); ++ MD5STEP(F4, c, d, a, b, in[6] + 0xa3014314, 15); ++ MD5STEP(F4, b, c, d, a, in[13] + 0x4e0811a1, 21); ++ MD5STEP(F4, a, b, c, d, in[4] + 0xf7537e82, 6); ++ MD5STEP(F4, d, a, b, c, in[11] + 0xbd3af235, 10); ++ MD5STEP(F4, c, d, a, b, in[2] + 0x2ad7d2bb, 15); ++ MD5STEP(F4, b, c, d, a, in[9] + 0xeb86d391, 21); ++ ++ buf[0] += a; ++ buf[1] += b; ++ buf[2] += c; ++ buf[3] += d; ++} ++ ++void mvMD5(unsigned char const *buf, unsigned len, unsigned char* digest) ++{ ++ MV_MD5_CONTEXT ctx; ++ ++ mvMD5Init(&ctx); ++ mvMD5Update(&ctx, buf, len); ++ mvMD5Final(digest, &ctx); ++} ++ ++ ++void mvHmacMd5(unsigned char const* text, int text_len, ++ unsigned char const* key, int key_len, ++ unsigned char* digest) ++{ ++ int i; ++ MV_MD5_CONTEXT ctx; ++ unsigned char k_ipad[64+1]; /* inner padding - key XORd with ipad */ ++ unsigned char k_opad[64+1]; /* outer padding - key XORd with opad */ ++ ++ /* start out by storing key in pads */ ++ memset(k_ipad, 0, 64); ++ memcpy(k_ipad, key, key_len); ++ memset(k_opad, 0, 64); ++ memcpy(k_opad, key, key_len); ++ ++ /* XOR key with ipad and opad values */ ++ for (i=0; i<64; i++) ++ { ++ k_ipad[i] ^= 0x36; ++ k_opad[i] ^= 0x5c; ++ } ++ ++ /* perform inner MD5 */ ++ mvMD5Init(&ctx); /* init ctx for 1st pass */ ++ mvMD5Update(&ctx, k_ipad, 64); /* start with inner pad */ ++ mvMD5Update(&ctx, text, text_len); /* then text of datagram */ ++ mvMD5Final(digest, &ctx); /* finish up 1st pass */ ++ ++ /* perform outer MD5 */ ++ mvMD5Init(&ctx); /* init ctx for 2nd pass */ ++ mvMD5Update(&ctx, k_opad, 64); /* start with outer pad */ ++ mvMD5Update(&ctx, digest, 16); /* then results of 1st hash */ ++ mvMD5Final(digest, &ctx); /* finish up 2nd pass */ ++} +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/cesa/mvMD5.h linux-3.1.4/crypto/ocf/kirkwood/cesa/mvMD5.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/cesa/mvMD5.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/cesa/mvMD5.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,93 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __mvMD5_h__ ++#define __mvMD5_h__ ++ ++#include "mvMD5.h" ++ ++#define MV_MD5_MAC_LEN 16 ++ ++ ++typedef struct ++{ ++ MV_U32 buf[4]; ++ MV_U32 bits[2]; ++ MV_U8 in[64]; ++ ++} MV_MD5_CONTEXT; ++ ++void mvMD5Init(MV_MD5_CONTEXT *context); ++void mvMD5Update(MV_MD5_CONTEXT *context, unsigned char const *buf, ++ unsigned len); ++void mvMD5Final(unsigned char digest[16], MV_MD5_CONTEXT *context); ++ ++void mvMD5(unsigned char const *buf, unsigned len, unsigned char* digest); ++ ++void mvHmacMd5(unsigned char const* text, int text_len, ++ unsigned char const* key, int key_len, ++ unsigned char* digest); ++ ++ ++#endif /* __mvMD5_h__ */ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/cesa/mvSHA1.c linux-3.1.4/crypto/ocf/kirkwood/cesa/mvSHA1.c +--- linux-3.1.4.orig/crypto/ocf/kirkwood/cesa/mvSHA1.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/cesa/mvSHA1.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,239 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#include "mvOs.h" ++#include "mvSHA1.h" ++ ++#define SHA1HANDSOFF ++ ++typedef union ++{ ++ MV_U8 c[64]; ++ MV_U32 l[16]; ++ ++} CHAR64LONG16; ++ ++static void mvSHA1Transform(MV_U32 state[5], const MV_U8 *buffer); ++ ++#define rol(value, bits) (((value) << (bits)) | ((value) >> (32 - (bits)))) ++ ++ ++#ifdef MV_CPU_LE ++#define blk0(i) (block->l[i] = (rol(block->l[i], 24) & 0xFF00FF00) | \ ++ (rol(block->l[i], 8) & 0x00FF00FF)) ++#else ++#define blk0(i) block->l[i] ++#endif ++#define blk(i) (block->l[i & 15] = rol(block->l[(i + 13) & 15] ^ \ ++ block->l[(i + 8) & 15] ^ block->l[(i + 2) & 15] ^ block->l[i & 15], 1)) ++ ++/* (R0+R1), R2, R3, R4 are the different operations used in SHA1 */ ++#define R0(v,w,x,y,z,i) \ ++ z += ((w & (x ^ y)) ^ y) + blk0(i) + 0x5A827999 + rol(v, 5); \ ++ w = rol(w, 30); ++#define R1(v,w,x,y,z,i) \ ++ z += ((w & (x ^ y)) ^ y) + blk(i) + 0x5A827999 + rol(v, 5); \ ++ w = rol(w, 30); ++#define R2(v,w,x,y,z,i) \ ++ z += (w ^ x ^ y) + blk(i) + 0x6ED9EBA1 + rol(v, 5); w = rol(w, 30); ++#define R3(v,w,x,y,z,i) \ ++ z += (((w | x) & y) | (w & x)) + blk(i) + 0x8F1BBCDC + rol(v, 5); \ ++ w = rol(w, 30); ++#define R4(v,w,x,y,z,i) \ ++ z += (w ^ x ^ y) + blk(i) + 0xCA62C1D6 + rol(v, 5); \ ++ w=rol(w, 30); ++ ++/* Hash a single 512-bit block. This is the core of the algorithm. */ ++static void mvSHA1Transform(MV_U32 state[5], const MV_U8 *buffer) ++{ ++ MV_U32 a, b, c, d, e; ++ CHAR64LONG16* block; ++ ++#ifdef SHA1HANDSOFF ++ static MV_U32 workspace[16]; ++ ++ block = (CHAR64LONG16 *) workspace; ++ memcpy(block, buffer, 64); ++#else ++ block = (CHAR64LONG16 *) buffer; ++#endif ++ /* Copy context->state[] to working vars */ ++ a = state[0]; ++ b = state[1]; ++ c = state[2]; ++ d = state[3]; ++ e = state[4]; ++ /* 4 rounds of 20 operations each. Loop unrolled. */ ++ R0(a,b,c,d,e, 0); R0(e,a,b,c,d, 1); R0(d,e,a,b,c, 2); R0(c,d,e,a,b, 3); ++ R0(b,c,d,e,a, 4); R0(a,b,c,d,e, 5); R0(e,a,b,c,d, 6); R0(d,e,a,b,c, 7); ++ R0(c,d,e,a,b, 8); R0(b,c,d,e,a, 9); R0(a,b,c,d,e,10); R0(e,a,b,c,d,11); ++ R0(d,e,a,b,c,12); R0(c,d,e,a,b,13); R0(b,c,d,e,a,14); R0(a,b,c,d,e,15); ++ R1(e,a,b,c,d,16); R1(d,e,a,b,c,17); R1(c,d,e,a,b,18); R1(b,c,d,e,a,19); ++ R2(a,b,c,d,e,20); R2(e,a,b,c,d,21); R2(d,e,a,b,c,22); R2(c,d,e,a,b,23); ++ R2(b,c,d,e,a,24); R2(a,b,c,d,e,25); R2(e,a,b,c,d,26); R2(d,e,a,b,c,27); ++ R2(c,d,e,a,b,28); R2(b,c,d,e,a,29); R2(a,b,c,d,e,30); R2(e,a,b,c,d,31); ++ R2(d,e,a,b,c,32); R2(c,d,e,a,b,33); R2(b,c,d,e,a,34); R2(a,b,c,d,e,35); ++ R2(e,a,b,c,d,36); R2(d,e,a,b,c,37); R2(c,d,e,a,b,38); R2(b,c,d,e,a,39); ++ R3(a,b,c,d,e,40); R3(e,a,b,c,d,41); R3(d,e,a,b,c,42); R3(c,d,e,a,b,43); ++ R3(b,c,d,e,a,44); R3(a,b,c,d,e,45); R3(e,a,b,c,d,46); R3(d,e,a,b,c,47); ++ R3(c,d,e,a,b,48); R3(b,c,d,e,a,49); R3(a,b,c,d,e,50); R3(e,a,b,c,d,51); ++ R3(d,e,a,b,c,52); R3(c,d,e,a,b,53); R3(b,c,d,e,a,54); R3(a,b,c,d,e,55); ++ R3(e,a,b,c,d,56); R3(d,e,a,b,c,57); R3(c,d,e,a,b,58); R3(b,c,d,e,a,59); ++ R4(a,b,c,d,e,60); R4(e,a,b,c,d,61); R4(d,e,a,b,c,62); R4(c,d,e,a,b,63); ++ R4(b,c,d,e,a,64); R4(a,b,c,d,e,65); R4(e,a,b,c,d,66); R4(d,e,a,b,c,67); ++ R4(c,d,e,a,b,68); R4(b,c,d,e,a,69); R4(a,b,c,d,e,70); R4(e,a,b,c,d,71); ++ R4(d,e,a,b,c,72); R4(c,d,e,a,b,73); R4(b,c,d,e,a,74); R4(a,b,c,d,e,75); ++ R4(e,a,b,c,d,76); R4(d,e,a,b,c,77); R4(c,d,e,a,b,78); R4(b,c,d,e,a,79); ++ /* Add the working vars back into context.state[] */ ++ state[0] += a; ++ state[1] += b; ++ state[2] += c; ++ state[3] += d; ++ state[4] += e; ++ /* Wipe variables */ ++ a = b = c = d = e = 0; ++} ++ ++void mvSHA1Init(MV_SHA1_CTX* context) ++{ ++ /* SHA1 initialization constants */ ++ context->state[0] = 0x67452301; ++ context->state[1] = 0xEFCDAB89; ++ context->state[2] = 0x98BADCFE; ++ context->state[3] = 0x10325476; ++ context->state[4] = 0xC3D2E1F0; ++ context->count[0] = context->count[1] = 0; ++} ++ ++ ++/* Run your data through this. */ ++void mvSHA1Update(MV_SHA1_CTX *context, MV_U8 const *data, ++ unsigned int len) ++{ ++ MV_U32 i, j; ++ ++ j = (context->count[0] >> 3) & 63; ++ if ((context->count[0] += len << 3) < (len << 3)) ++ context->count[1]++; ++ context->count[1] += (len >> 29); ++ if ((j + len) > 63) ++ { ++ memcpy(&context->buffer[j], data, (i = 64-j)); ++ mvSHA1Transform(context->state, context->buffer); ++ for ( ; i + 63 < len; i += 64) ++ { ++ mvSHA1Transform(context->state, &data[i]); ++ } ++ j = 0; ++ } ++ else ++ { ++ i = 0; ++ } ++ memcpy(&context->buffer[j], &data[i], len - i); ++} ++ ++void mvSHA1Final(MV_U8* digest, MV_SHA1_CTX* context) ++{ ++ MV_U32 i; ++ MV_U8 finalcount[8]; ++ ++ for (i = 0; i < 8; i++) ++ { ++ finalcount[i] = (unsigned char)((context->count[(i >= 4 ? 0 : 1)] >> ++ ((3-(i & 3)) * 8) ) & 255); /* Endian independent */ ++ } ++ mvSHA1Update(context, (const unsigned char *) "\200", 1); ++ while ((context->count[0] & 504) != 448) ++ { ++ mvSHA1Update(context, (const unsigned char *) "\0", 1); ++ } ++ mvSHA1Update(context, finalcount, 8); /* Should cause a mvSHA1Transform() ++ */ ++ for (i = 0; i < 20; i++) ++ { ++ digest[i] = (unsigned char) ++ ((context->state[i >> 2] >> ((3 - (i & 3)) * 8)) & 255); ++ } ++ /* Wipe variables */ ++ i = 0; ++ memset(context->buffer, 0, 64); ++ memset(context->state, 0, 20); ++ memset(context->count, 0, 8); ++ memset(finalcount, 0, 8); ++ ++#ifdef SHA1HANDSOFF /* make SHA1Transform overwrite it's own static vars */ ++ mvSHA1Transform(context->state, context->buffer); ++#endif ++} ++ ++ ++void mvSHA1(MV_U8 const *buf, unsigned int len, MV_U8* digest) ++{ ++ MV_SHA1_CTX ctx; ++ ++ mvSHA1Init(&ctx); ++ mvSHA1Update(&ctx, buf, len); ++ mvSHA1Final(digest, &ctx); ++} +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/cesa/mvSHA1.h linux-3.1.4/crypto/ocf/kirkwood/cesa/mvSHA1.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/cesa/mvSHA1.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/cesa/mvSHA1.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,88 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __mvSHA1_h__ ++#define __mvSHA1_h__ ++ ++#include "mvSHA1.h" ++ ++#define MV_SHA1_MAC_LEN 20 ++ ++ ++typedef struct ++{ ++ MV_U32 state[5]; ++ MV_U32 count[2]; ++ MV_U8 buffer[64]; ++ ++} MV_SHA1_CTX; ++ ++void mvSHA1Init(MV_SHA1_CTX *context); ++void mvSHA1Update(MV_SHA1_CTX *context, MV_U8 const *buf, unsigned int len); ++void mvSHA1Final(MV_U8* digest, MV_SHA1_CTX *context); ++ ++void mvSHA1(MV_U8 const *buf, unsigned int len, MV_U8* digest); ++ ++ ++#endif /* __mvSHA1_h__ */ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/cesa_ocf_drv.c linux-3.1.4/crypto/ocf/kirkwood/cesa_ocf_drv.c +--- linux-3.1.4.orig/crypto/ocf/kirkwood/cesa_ocf_drv.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/cesa_ocf_drv.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,1297 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++*******************************************************************************/ ++ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "ctrlEnv/sys/mvSysCesa.h" ++#include "cesa/mvCesa.h" /* moved here before cryptodev.h due to include dependencies */ ++#include ++#include ++#include ++#include ++#include "mvDebug.h" ++ ++#include "cesa/mvMD5.h" ++#include "cesa/mvSHA1.h" ++ ++#include "cesa/mvCesaRegs.h" ++#include "cesa/AES/mvAes.h" ++#include "cesa/mvLru.h" ++ ++#undef RT_DEBUG ++#ifdef RT_DEBUG ++static int debug = 1; ++module_param(debug, int, 1); ++MODULE_PARM_DESC(debug, "Enable debug"); ++#undef dprintk ++#define dprintk(a...) if (debug) { printk(a); } else ++#else ++static int debug = 0; ++#undef dprintk ++#define dprintk(a...) ++#endif ++ ++ ++/* TDMA Regs */ ++#define WINDOW_BASE(i) 0xA00 + (i << 3) ++#define WINDOW_CTRL(i) 0xA04 + (i << 3) ++ ++/* interrupt handling */ ++#undef CESA_OCF_POLLING ++#undef CESA_OCF_TASKLET ++ ++#if defined(CESA_OCF_POLLING) && defined(CESA_OCF_TASKLET) ++#error "don't use both tasklet and polling mode" ++#endif ++ ++extern int cesaReqResources; ++/* support for spliting action into 2 actions */ ++#define CESA_OCF_SPLIT ++ ++/* general defines */ ++#define CESA_OCF_MAX_SES 128 ++#define CESA_Q_SIZE 64 ++ ++ ++/* data structures */ ++struct cesa_ocf_data { ++ int cipher_alg; ++ int auth_alg; ++ int encrypt_tn_auth; ++#define auth_tn_decrypt encrypt_tn_auth ++ int ivlen; ++ int digestlen; ++ short sid_encrypt; ++ short sid_decrypt; ++ /* fragment workaround sessions */ ++ short frag_wa_encrypt; ++ short frag_wa_decrypt; ++ short frag_wa_auth; ++}; ++ ++/* CESA device data */ ++struct cesa_dev { ++ void __iomem *sram; ++ void __iomem *reg; ++ struct mv_cesa_platform_data *plat_data; ++ int irq; ++}; ++ ++#define DIGEST_BUF_SIZE 32 ++struct cesa_ocf_process { ++ MV_CESA_COMMAND cesa_cmd; ++ MV_CESA_MBUF cesa_mbuf; ++ MV_BUF_INFO cesa_bufs[MV_CESA_MAX_MBUF_FRAGS]; ++ char digest[DIGEST_BUF_SIZE]; ++ int digest_len; ++ struct cryptop *crp; ++ int need_cb; ++}; ++ ++/* global variables */ ++static int32_t cesa_ocf_id = -1; ++static struct cesa_ocf_data *cesa_ocf_sessions[CESA_OCF_MAX_SES]; ++static spinlock_t cesa_lock; ++static struct cesa_dev cesa_device; ++ ++/* static APIs */ ++static int cesa_ocf_process (device_t, struct cryptop *, int); ++static int cesa_ocf_newsession (device_t, u_int32_t *, struct cryptoini *); ++static int cesa_ocf_freesession (device_t, u_int64_t); ++static void cesa_callback (unsigned long); ++static irqreturn_t cesa_interrupt_handler (int, void *); ++#ifdef CESA_OCF_POLLING ++static void cesa_interrupt_polling(void); ++#endif ++#ifdef CESA_OCF_TASKLET ++static struct tasklet_struct cesa_ocf_tasklet; ++#endif ++ ++static struct timeval tt_start; ++static struct timeval tt_end; ++ ++/* ++ * dummy device structure ++ */ ++ ++static struct { ++ softc_device_decl sc_dev; ++} mv_cesa_dev; ++ ++static device_method_t mv_cesa_methods = { ++ /* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, cesa_ocf_newsession), ++ DEVMETHOD(cryptodev_freesession,cesa_ocf_freesession), ++ DEVMETHOD(cryptodev_process, cesa_ocf_process), ++ DEVMETHOD(cryptodev_kprocess, NULL), ++}; ++ ++ ++ ++/* Add debug Trace */ ++#undef CESA_OCF_TRACE_DEBUG ++#ifdef CESA_OCF_TRACE_DEBUG ++ ++#define MV_CESA_USE_TIMER_ID 0 ++ ++typedef struct ++{ ++ int type; /* 0 - isrEmpty, 1 - cesaReadyGet, 2 - cesaAction */ ++ MV_U32 timeStamp; ++ MV_U32 cause; ++ MV_U32 realCause; ++ MV_U32 dmaCause; ++ int resources; ++ MV_CESA_REQ* pReqReady; ++ MV_CESA_REQ* pReqEmpty; ++ MV_CESA_REQ* pReqProcess; ++} MV_CESA_TEST_TRACE; ++ ++#define MV_CESA_TEST_TRACE_SIZE 50 ++ ++static int cesaTestTraceIdx = 0; ++static MV_CESA_TEST_TRACE cesaTestTrace[MV_CESA_TEST_TRACE_SIZE]; ++ ++static void cesaTestTraceAdd(int type) ++{ ++ cesaTestTrace[cesaTestTraceIdx].type = type; ++ cesaTestTrace[cesaTestTraceIdx].realCause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); ++ //cesaTestTrace[cesaTestTraceIdx].idmaCause = MV_REG_READ(IDMA_CAUSE_REG); ++ cesaTestTrace[cesaTestTraceIdx].resources = cesaReqResources; ++ cesaTestTrace[cesaTestTraceIdx].pReqReady = pCesaReqReady; ++ cesaTestTrace[cesaTestTraceIdx].pReqEmpty = pCesaReqEmpty; ++ cesaTestTrace[cesaTestTraceIdx].pReqProcess = pCesaReqProcess; ++ cesaTestTrace[cesaTestTraceIdx].timeStamp = mvCntmrRead(MV_CESA_USE_TIMER_ID); ++ cesaTestTraceIdx++; ++ if(cesaTestTraceIdx == MV_CESA_TEST_TRACE_SIZE) ++ cesaTestTraceIdx = 0; ++} ++ ++#else /* CESA_OCF_TRACE_DEBUG */ ++ ++#define cesaTestTraceAdd(x) ++ ++#endif /* CESA_OCF_TRACE_DEBUG */ ++ ++unsigned int ++get_usec(unsigned int start) ++{ ++ if(start) { ++ do_gettimeofday (&tt_start); ++ return 0; ++ } ++ else { ++ do_gettimeofday (&tt_end); ++ tt_end.tv_sec -= tt_start.tv_sec; ++ tt_end.tv_usec -= tt_start.tv_usec; ++ if (tt_end.tv_usec < 0) { ++ tt_end.tv_usec += 1000 * 1000; ++ tt_end.tv_sec -= 1; ++ } ++ } ++ printk("time taken is %d\n", (unsigned int)(tt_end.tv_usec + tt_end.tv_sec * 1000000)); ++ return (tt_end.tv_usec + tt_end.tv_sec * 1000000); ++} ++ ++#ifdef RT_DEBUG ++/* ++ * check that the crp action match the current session ++ */ ++static int ++ocf_check_action(struct cryptop *crp, struct cesa_ocf_data *cesa_ocf_cur_ses) { ++ int count = 0; ++ int encrypt = 0, decrypt = 0, auth = 0; ++ struct cryptodesc *crd; ++ ++ /* Go through crypto descriptors, processing as we go */ ++ for (crd = crp->crp_desc; crd; crd = crd->crd_next, count++) { ++ if(count > 2) { ++ printk("%s,%d: session mode is not supported.\n", __FILE__, __LINE__); ++ return 1; ++ } ++ ++ /* Encryption /Decryption */ ++ if(crd->crd_alg == cesa_ocf_cur_ses->cipher_alg) { ++ /* check that the action is compatible with session */ ++ if(encrypt || decrypt) { ++ printk("%s,%d: session mode is not supported.\n", __FILE__, __LINE__); ++ return 1; ++ } ++ ++ if(crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ ++ if( (count == 2) && (cesa_ocf_cur_ses->encrypt_tn_auth) ) { ++ printk("%s,%d: sequence isn't supported by this session.\n", __FILE__, __LINE__); ++ return 1; ++ } ++ encrypt++; ++ } ++ else { /* decrypt */ ++ if( (count == 2) && !(cesa_ocf_cur_ses->auth_tn_decrypt) ) { ++ printk("%s,%d: sequence isn't supported by this session.\n", __FILE__, __LINE__); ++ return 1; ++ } ++ decrypt++; ++ } ++ ++ } ++ /* Authentication */ ++ else if(crd->crd_alg == cesa_ocf_cur_ses->auth_alg) { ++ /* check that the action is compatible with session */ ++ if(auth) { ++ printk("%s,%d: session mode is not supported.\n", __FILE__, __LINE__); ++ return 1; ++ } ++ if( (count == 2) && (decrypt) && (cesa_ocf_cur_ses->auth_tn_decrypt)) { ++ printk("%s,%d: sequence isn't supported by this session.\n", __FILE__, __LINE__); ++ return 1; ++ } ++ if( (count == 2) && (encrypt) && !(cesa_ocf_cur_ses->encrypt_tn_auth)) { ++ printk("%s,%d: sequence isn't supported by this session.\n", __FILE__, __LINE__); ++ return 1; ++ } ++ auth++; ++ } ++ else { ++ printk("%s,%d: Alg isn't supported by this session.\n", __FILE__, __LINE__); ++ return 1; ++ } ++ } ++ return 0; ++ ++} ++#endif ++ ++/* ++ * Process a request. ++ */ ++static int ++cesa_ocf_process(device_t dev, struct cryptop *crp, int hint) ++{ ++ struct cesa_ocf_process *cesa_ocf_cmd = NULL; ++ struct cesa_ocf_process *cesa_ocf_cmd_wa = NULL; ++ MV_CESA_COMMAND *cesa_cmd; ++ struct cryptodesc *crd; ++ struct cesa_ocf_data *cesa_ocf_cur_ses; ++ int sid = 0, temp_len = 0, i; ++ int encrypt = 0, decrypt = 0, auth = 0; ++ int status; ++ struct sk_buff *skb = NULL; ++ struct uio *uiop = NULL; ++ unsigned char *ivp; ++ MV_BUF_INFO *p_buf_info; ++ MV_CESA_MBUF *p_mbuf_info; ++ unsigned long flags; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ if( cesaReqResources <= 1 ) { ++ dprintk("%s,%d: ERESTART\n", __FILE__, __LINE__); ++ return ERESTART; ++ } ++ ++#ifdef RT_DEBUG ++ /* Sanity check */ ++ if (crp == NULL) { ++ printk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ if (crp->crp_desc == NULL || crp->crp_buf == NULL ) { ++ printk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ crp->crp_etype = EINVAL; ++ return EINVAL; ++ } ++ ++ sid = crp->crp_sid & 0xffffffff; ++ if ((sid >= CESA_OCF_MAX_SES) || (cesa_ocf_sessions[sid] == NULL)) { ++ crp->crp_etype = ENOENT; ++ printk("%s,%d: ENOENT session %d \n", __FILE__, __LINE__, sid); ++ return EINVAL; ++ } ++#endif ++ ++ sid = crp->crp_sid & 0xffffffff; ++ crp->crp_etype = 0; ++ cesa_ocf_cur_ses = cesa_ocf_sessions[sid]; ++ ++#ifdef RT_DEBUG ++ if(ocf_check_action(crp, cesa_ocf_cur_ses)){ ++ goto p_error; ++ } ++#endif ++ ++ /* malloc a new cesa process */ ++ cesa_ocf_cmd = kmalloc(sizeof(struct cesa_ocf_process), GFP_ATOMIC); ++ ++ if (cesa_ocf_cmd == NULL) { ++ printk("%s,%d: ENOBUFS \n", __FILE__, __LINE__); ++ goto p_error; ++ } ++ memset(cesa_ocf_cmd, 0, sizeof(struct cesa_ocf_process)); ++ ++ /* init cesa_process */ ++ cesa_ocf_cmd->crp = crp; ++ /* always call callback */ ++ cesa_ocf_cmd->need_cb = 1; ++ ++ /* init cesa_cmd for usage of the HALs */ ++ cesa_cmd = &cesa_ocf_cmd->cesa_cmd; ++ cesa_cmd->pReqPrv = (void *)cesa_ocf_cmd; ++ cesa_cmd->sessionId = cesa_ocf_cur_ses->sid_encrypt; /* defualt use encrypt */ ++ ++ /* prepare src buffer */ ++ /* we send the entire buffer to the HAL, even if only part of it should be encrypt/auth. */ ++ /* if not using seesions for both encrypt and auth, then it will be wiser to to copy only */ ++ /* from skip to crd_len. */ ++ p_buf_info = cesa_ocf_cmd->cesa_bufs; ++ p_mbuf_info = &cesa_ocf_cmd->cesa_mbuf; ++ ++ p_buf_info += 2; /* save 2 first buffers for IV and digest - ++ we won't append them to the end since, they ++ might be places in an unaligned addresses. */ ++ ++ p_mbuf_info->pFrags = p_buf_info; ++ temp_len = 0; ++ ++ /* handle SKB */ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ ++ dprintk("%s,%d: handle SKB.\n", __FILE__, __LINE__); ++ skb = (struct sk_buff *) crp->crp_buf; ++ ++ if (skb_shinfo(skb)->nr_frags >= (MV_CESA_MAX_MBUF_FRAGS - 1)) { ++ printk("%s,%d: %d nr_frags > MV_CESA_MAX_MBUF_FRAGS", __FILE__, __LINE__, skb_shinfo(skb)->nr_frags); ++ goto p_error; ++ } ++ ++ p_mbuf_info->mbufSize = skb->len; ++ temp_len = skb->len; ++ /* first skb fragment */ ++ p_buf_info->bufSize = skb_headlen(skb); ++ p_buf_info->bufVirtPtr = skb->data; ++ p_buf_info++; ++ ++ /* now handle all other skb fragments */ ++ for ( i = 0; i < skb_shinfo(skb)->nr_frags; i++ ) { ++ skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; ++ p_buf_info->bufSize = frag->size; ++ p_buf_info->bufVirtPtr = page_address(frag->page) + frag->page_offset; ++ p_buf_info++; ++ } ++ p_mbuf_info->numFrags = skb_shinfo(skb)->nr_frags + 1; ++ } ++ /* handle UIO */ ++ else if(crp->crp_flags & CRYPTO_F_IOV) { ++ ++ dprintk("%s,%d: handle UIO.\n", __FILE__, __LINE__); ++ uiop = (struct uio *) crp->crp_buf; ++ ++ if (uiop->uio_iovcnt > (MV_CESA_MAX_MBUF_FRAGS - 1)) { ++ printk("%s,%d: %d uio_iovcnt > MV_CESA_MAX_MBUF_FRAGS \n", __FILE__, __LINE__, uiop->uio_iovcnt); ++ goto p_error; ++ } ++ ++ p_mbuf_info->mbufSize = crp->crp_ilen; ++ p_mbuf_info->numFrags = uiop->uio_iovcnt; ++ for(i = 0; i < uiop->uio_iovcnt; i++) { ++ p_buf_info->bufVirtPtr = uiop->uio_iov[i].iov_base; ++ p_buf_info->bufSize = uiop->uio_iov[i].iov_len; ++ temp_len += p_buf_info->bufSize; ++ dprintk("%s,%d: buf %x-> addr %x, size %x \n" ++ , __FILE__, __LINE__, i, (unsigned int)p_buf_info->bufVirtPtr, p_buf_info->bufSize); ++ p_buf_info++; ++ } ++ ++ } ++ /* handle CONTIG */ ++ else { ++ dprintk("%s,%d: handle CONTIG.\n", __FILE__, __LINE__); ++ p_mbuf_info->numFrags = 1; ++ p_mbuf_info->mbufSize = crp->crp_ilen; ++ p_buf_info->bufVirtPtr = crp->crp_buf; ++ p_buf_info->bufSize = crp->crp_ilen; ++ temp_len = crp->crp_ilen; ++ p_buf_info++; ++ } ++ ++ /* Support up to 64K why? cause! */ ++ if(crp->crp_ilen > 64*1024) { ++ printk("%s,%d: buf too big %x \n", __FILE__, __LINE__, crp->crp_ilen); ++ goto p_error; ++ } ++ ++ if( temp_len != crp->crp_ilen ) { ++ printk("%s,%d: warning size don't match.(%x %x) \n", __FILE__, __LINE__, temp_len, crp->crp_ilen); ++ } ++ ++ cesa_cmd->pSrc = p_mbuf_info; ++ cesa_cmd->pDst = p_mbuf_info; ++ ++ /* restore p_buf_info to point to first available buf */ ++ p_buf_info = cesa_ocf_cmd->cesa_bufs; ++ p_buf_info += 1; ++ ++ ++ /* Go through crypto descriptors, processing as we go */ ++ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { ++ ++ /* Encryption /Decryption */ ++ if(crd->crd_alg == cesa_ocf_cur_ses->cipher_alg) { ++ ++ dprintk("%s,%d: cipher", __FILE__, __LINE__); ++ ++ cesa_cmd->cryptoOffset = crd->crd_skip; ++ cesa_cmd->cryptoLength = crd->crd_len; ++ ++ if(crd->crd_flags & CRD_F_ENCRYPT) { /* encrypt */ ++ dprintk(" encrypt \n"); ++ encrypt++; ++ ++ /* handle IV */ ++ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { /* IV from USER */ ++ dprintk("%s,%d: IV from USER (offset %x) \n", __FILE__, __LINE__, crd->crd_inject); ++ cesa_cmd->ivFromUser = 1; ++ ivp = crd->crd_iv; ++ ++ /* ++ * do we have to copy the IV back to the buffer ? ++ */ ++ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { ++ dprintk("%s,%d: copy the IV back to the buffer\n", __FILE__, __LINE__); ++ cesa_cmd->ivOffset = crd->crd_inject; ++ crypto_copyback(crp->crp_flags, crp->crp_buf, crd->crd_inject, cesa_ocf_cur_ses->ivlen, ivp); ++ } ++ else { ++ dprintk("%s,%d: don't copy the IV back to the buffer \n", __FILE__, __LINE__); ++ p_mbuf_info->numFrags++; ++ p_mbuf_info->mbufSize += cesa_ocf_cur_ses->ivlen; ++ p_mbuf_info->pFrags = p_buf_info; ++ ++ p_buf_info->bufVirtPtr = ivp; ++ p_buf_info->bufSize = cesa_ocf_cur_ses->ivlen; ++ p_buf_info--; ++ ++ /* offsets */ ++ cesa_cmd->ivOffset = 0; ++ cesa_cmd->cryptoOffset += cesa_ocf_cur_ses->ivlen; ++ if(auth) { ++ cesa_cmd->macOffset += cesa_ocf_cur_ses->ivlen; ++ cesa_cmd->digestOffset += cesa_ocf_cur_ses->ivlen; ++ } ++ } ++ } ++ else { /* random IV */ ++ dprintk("%s,%d: random IV \n", __FILE__, __LINE__); ++ cesa_cmd->ivFromUser = 0; ++ ++ /* ++ * do we have to copy the IV back to the buffer ? ++ */ ++ /* in this mode the HAL will always copy the IV */ ++ /* given by the session to the ivOffset */ ++ if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) { ++ cesa_cmd->ivOffset = crd->crd_inject; ++ } ++ else { ++ /* if IV isn't copy, then how will the user know which IV did we use??? */ ++ printk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ goto p_error; ++ } ++ } ++ } ++ else { /* decrypt */ ++ dprintk(" decrypt \n"); ++ decrypt++; ++ cesa_cmd->sessionId = cesa_ocf_cur_ses->sid_decrypt; ++ ++ /* handle IV */ ++ if (crd->crd_flags & CRD_F_IV_EXPLICIT) { ++ dprintk("%s,%d: IV from USER \n", __FILE__, __LINE__); ++ /* append the IV buf to the mbuf */ ++ cesa_cmd->ivFromUser = 1; ++ p_mbuf_info->numFrags++; ++ p_mbuf_info->mbufSize += cesa_ocf_cur_ses->ivlen; ++ p_mbuf_info->pFrags = p_buf_info; ++ ++ p_buf_info->bufVirtPtr = crd->crd_iv; ++ p_buf_info->bufSize = cesa_ocf_cur_ses->ivlen; ++ p_buf_info--; ++ ++ /* offsets */ ++ cesa_cmd->ivOffset = 0; ++ cesa_cmd->cryptoOffset += cesa_ocf_cur_ses->ivlen; ++ if(auth) { ++ cesa_cmd->macOffset += cesa_ocf_cur_ses->ivlen; ++ cesa_cmd->digestOffset += cesa_ocf_cur_ses->ivlen; ++ } ++ } ++ else { ++ dprintk("%s,%d: IV inside the buffer \n", __FILE__, __LINE__); ++ cesa_cmd->ivFromUser = 0; ++ cesa_cmd->ivOffset = crd->crd_inject; ++ } ++ } ++ ++ } ++ /* Authentication */ ++ else if(crd->crd_alg == cesa_ocf_cur_ses->auth_alg) { ++ dprintk("%s,%d: Authentication \n", __FILE__, __LINE__); ++ auth++; ++ cesa_cmd->macOffset = crd->crd_skip; ++ cesa_cmd->macLength = crd->crd_len; ++ ++ /* digest + mac */ ++ cesa_cmd->digestOffset = crd->crd_inject; ++ } ++ else { ++ printk("%s,%d: Alg isn't supported by this session.\n", __FILE__, __LINE__); ++ goto p_error; ++ } ++ } ++ ++ dprintk("\n"); ++ dprintk("%s,%d: Sending Action: \n", __FILE__, __LINE__); ++ dprintk("%s,%d: IV from user: %d. IV offset %x \n", __FILE__, __LINE__, cesa_cmd->ivFromUser, cesa_cmd->ivOffset); ++ dprintk("%s,%d: crypt offset %x len %x \n", __FILE__, __LINE__, cesa_cmd->cryptoOffset, cesa_cmd->cryptoLength); ++ dprintk("%s,%d: Auth offset %x len %x \n", __FILE__, __LINE__, cesa_cmd->macOffset, cesa_cmd->macLength); ++ dprintk("%s,%d: set digest in offset %x . \n", __FILE__, __LINE__, cesa_cmd->digestOffset); ++ if(debug) { ++ mvCesaDebugMbuf("SRC BUFFER", cesa_cmd->pSrc, 0, cesa_cmd->pSrc->mbufSize); ++ } ++ ++ ++ /* send action to HAL */ ++ spin_lock_irqsave(&cesa_lock, flags); ++ status = mvCesaAction(cesa_cmd); ++ spin_unlock_irqrestore(&cesa_lock, flags); ++ ++ /* action not allowed */ ++ if(status == MV_NOT_ALLOWED) { ++#ifdef CESA_OCF_SPLIT ++ /* if both encrypt and auth try to split */ ++ if(auth && (encrypt || decrypt)) { ++ MV_CESA_COMMAND *cesa_cmd_wa; ++ ++ /* malloc a new cesa process and init it */ ++ cesa_ocf_cmd_wa = kmalloc(sizeof(struct cesa_ocf_process), GFP_ATOMIC); ++ ++ if (cesa_ocf_cmd_wa == NULL) { ++ printk("%s,%d: ENOBUFS \n", __FILE__, __LINE__); ++ goto p_error; ++ } ++ memcpy(cesa_ocf_cmd_wa, cesa_ocf_cmd, sizeof(struct cesa_ocf_process)); ++ cesa_cmd_wa = &cesa_ocf_cmd_wa->cesa_cmd; ++ cesa_cmd_wa->pReqPrv = (void *)cesa_ocf_cmd_wa; ++ cesa_ocf_cmd_wa->need_cb = 0; ++ ++ /* break requests to two operation, first operation completion won't call callback */ ++ if((decrypt) && (cesa_ocf_cur_ses->auth_tn_decrypt)) { ++ cesa_cmd_wa->sessionId = cesa_ocf_cur_ses->frag_wa_auth; ++ cesa_cmd->sessionId = cesa_ocf_cur_ses->frag_wa_decrypt; ++ } ++ else if((decrypt) && !(cesa_ocf_cur_ses->auth_tn_decrypt)) { ++ cesa_cmd_wa->sessionId = cesa_ocf_cur_ses->frag_wa_decrypt; ++ cesa_cmd->sessionId = cesa_ocf_cur_ses->frag_wa_auth; ++ } ++ else if((encrypt) && (cesa_ocf_cur_ses->encrypt_tn_auth)) { ++ cesa_cmd_wa->sessionId = cesa_ocf_cur_ses->frag_wa_encrypt; ++ cesa_cmd->sessionId = cesa_ocf_cur_ses->frag_wa_auth; ++ } ++ else if((encrypt) && !(cesa_ocf_cur_ses->encrypt_tn_auth)){ ++ cesa_cmd_wa->sessionId = cesa_ocf_cur_ses->frag_wa_auth; ++ cesa_cmd->sessionId = cesa_ocf_cur_ses->frag_wa_encrypt; ++ } ++ else { ++ printk("%s,%d: Unsupporterd fragment wa mode \n", __FILE__, __LINE__); ++ goto p_error; ++ } ++ ++ /* send the 2 actions to the HAL */ ++ spin_lock_irqsave(&cesa_lock, flags); ++ status = mvCesaAction(cesa_cmd_wa); ++ spin_unlock_irqrestore(&cesa_lock, flags); ++ ++ if((status != MV_NO_MORE) && (status != MV_OK)) { ++ printk("%s,%d: cesa action failed, status = 0x%x\n", __FILE__, __LINE__, status); ++ goto p_error; ++ } ++ spin_lock_irqsave(&cesa_lock, flags); ++ status = mvCesaAction(cesa_cmd); ++ spin_unlock_irqrestore(&cesa_lock, flags); ++ ++ } ++ /* action not allowed and can't split */ ++ else ++#endif ++ { ++ goto p_error; ++ } ++ } ++ ++ /* Hal Q is full, send again. This should never happen */ ++ if(status == MV_NO_RESOURCE) { ++ printk("%s,%d: cesa no more resources \n", __FILE__, __LINE__); ++ if(cesa_ocf_cmd) ++ kfree(cesa_ocf_cmd); ++ if(cesa_ocf_cmd_wa) ++ kfree(cesa_ocf_cmd_wa); ++ return ERESTART; ++ } ++ else if((status != MV_NO_MORE) && (status != MV_OK)) { ++ printk("%s,%d: cesa action failed, status = 0x%x\n", __FILE__, __LINE__, status); ++ goto p_error; ++ } ++ ++ ++#ifdef CESA_OCF_POLLING ++ cesa_interrupt_polling(); ++#endif ++ cesaTestTraceAdd(5); ++ ++ return 0; ++p_error: ++ crp->crp_etype = EINVAL; ++ if(cesa_ocf_cmd) ++ kfree(cesa_ocf_cmd); ++ if(cesa_ocf_cmd_wa) ++ kfree(cesa_ocf_cmd_wa); ++ return EINVAL; ++} ++ ++/* ++ * cesa callback. ++ */ ++static void ++cesa_callback(unsigned long dummy) ++{ ++ struct cesa_ocf_process *cesa_ocf_cmd = NULL; ++ struct cryptop *crp = NULL; ++ MV_CESA_RESULT result[MV_CESA_MAX_CHAN]; ++ int res_idx = 0,i; ++ MV_STATUS status; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++#ifdef CESA_OCF_TASKLET ++ disable_irq(cesa_device.irq); ++#endif ++ while(MV_TRUE) { ++ ++ /* Get Ready requests */ ++ spin_lock(&cesa_lock); ++ status = mvCesaReadyGet(&result[res_idx]); ++ spin_unlock(&cesa_lock); ++ ++ cesaTestTraceAdd(2); ++ ++ if(status != MV_OK) { ++#ifdef CESA_OCF_POLLING ++ if(status == MV_BUSY) { /* Fragment */ ++ cesa_interrupt_polling(); ++ return; ++ } ++#endif ++ break; ++ } ++ res_idx++; ++ break; ++ } ++ ++ for(i = 0; i < res_idx; i++) { ++ ++ if(!result[i].pReqPrv) { ++ printk("%s,%d: warning private is NULL\n", __FILE__, __LINE__); ++ break; ++ } ++ ++ cesa_ocf_cmd = result[i].pReqPrv; ++ crp = cesa_ocf_cmd->crp; ++ ++ // ignore HMAC error. ++ //if(result->retCode) ++ // crp->crp_etype = EIO; ++ ++#if defined(CESA_OCF_POLLING) ++ if(!cesa_ocf_cmd->need_cb){ ++ cesa_interrupt_polling(); ++ } ++#endif ++ if(cesa_ocf_cmd->need_cb) { ++ if(debug) { ++ mvCesaDebugMbuf("DST BUFFER", cesa_ocf_cmd->cesa_cmd.pDst, 0, cesa_ocf_cmd->cesa_cmd.pDst->mbufSize); ++ } ++ crypto_done(crp); ++ } ++ kfree(cesa_ocf_cmd); ++ } ++#ifdef CESA_OCF_TASKLET ++ enable_irq(cesa_device.irq); ++#endif ++ ++ cesaTestTraceAdd(3); ++ ++ return; ++} ++ ++#ifdef CESA_OCF_POLLING ++static void ++cesa_interrupt_polling(void) ++{ ++ u32 cause; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ /* Read cause register */ ++ do { ++ cause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); ++ cause &= MV_CESA_CAUSE_ACC_DMA_ALL_MASK; ++ ++ } while (cause == 0); ++ ++ /* clear interrupts */ ++ MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); ++ ++ cesa_callback(0); ++ ++ return; ++} ++ ++#endif ++ ++/* ++ * cesa Interrupt polling routine. ++ */ ++static irqreturn_t ++cesa_interrupt_handler(int irq, void *arg) ++{ ++ u32 cause; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ cesaTestTraceAdd(0); ++ ++ /* Read cause register */ ++ cause = MV_REG_READ(MV_CESA_ISR_CAUSE_REG); ++ ++ if( (cause & MV_CESA_CAUSE_ACC_DMA_ALL_MASK) == 0) ++ { ++ /* Empty interrupt */ ++ dprintk("%s,%d: cesaTestReadyIsr: cause=0x%x\n", __FILE__, __LINE__, cause); ++ return IRQ_HANDLED; ++ } ++ ++ /* clear interrupts */ ++ MV_REG_WRITE(MV_CESA_ISR_CAUSE_REG, 0); ++ ++ cesaTestTraceAdd(1); ++#ifdef CESA_OCF_TASKLET ++ tasklet_hi_schedule(&cesa_ocf_tasklet); ++#else ++ cesa_callback(0); ++#endif ++ return IRQ_HANDLED; ++} ++ ++/* ++ * Open a session. ++ */ ++static int ++/*cesa_ocf_newsession(void *arg, u_int32_t *sid, struct cryptoini *cri)*/ ++cesa_ocf_newsession(device_t dev, u_int32_t *sid, struct cryptoini *cri) ++{ ++ u32 status = 0, i; ++ u32 count = 0, auth = 0, encrypt =0; ++ struct cesa_ocf_data *cesa_ocf_cur_ses; ++ MV_CESA_OPEN_SESSION cesa_session; ++ MV_CESA_OPEN_SESSION *cesa_ses = &cesa_session; ++ ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (sid == NULL || cri == NULL) { ++ printk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ /* leave first empty like in other implementations */ ++ for (i = 1; i < CESA_OCF_MAX_SES; i++) { ++ if (cesa_ocf_sessions[i] == NULL) ++ break; ++ } ++ ++ if(i >= CESA_OCF_MAX_SES) { ++ printk("%s,%d: no more sessions \n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ cesa_ocf_sessions[i] = (struct cesa_ocf_data *) kmalloc(sizeof(struct cesa_ocf_data), GFP_ATOMIC); ++ if (cesa_ocf_sessions[i] == NULL) { ++ cesa_ocf_freesession(NULL, i); ++ printk("%s,%d: ENOBUFS \n", __FILE__, __LINE__); ++ return ENOBUFS; ++ } ++ dprintk("%s,%d: new session %d \n", __FILE__, __LINE__, i); ++ ++ *sid = i; ++ cesa_ocf_cur_ses = cesa_ocf_sessions[i]; ++ memset(cesa_ocf_cur_ses, 0, sizeof(struct cesa_ocf_data)); ++ cesa_ocf_cur_ses->sid_encrypt = -1; ++ cesa_ocf_cur_ses->sid_decrypt = -1; ++ cesa_ocf_cur_ses->frag_wa_encrypt = -1; ++ cesa_ocf_cur_ses->frag_wa_decrypt = -1; ++ cesa_ocf_cur_ses->frag_wa_auth = -1; ++ ++ /* init the session */ ++ memset(cesa_ses, 0, sizeof(MV_CESA_OPEN_SESSION)); ++ count = 1; ++ while (cri) { ++ if(count > 2) { ++ printk("%s,%d: don't support more then 2 operations\n", __FILE__, __LINE__); ++ goto error; ++ } ++ switch (cri->cri_alg) { ++ case CRYPTO_AES_CBC: ++ dprintk("%s,%d: (%d) AES CBC \n", __FILE__, __LINE__, count); ++ cesa_ocf_cur_ses->cipher_alg = cri->cri_alg; ++ cesa_ocf_cur_ses->ivlen = MV_CESA_AES_BLOCK_SIZE; ++ cesa_ses->cryptoAlgorithm = MV_CESA_CRYPTO_AES; ++ cesa_ses->cryptoMode = MV_CESA_CRYPTO_CBC; ++ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { ++ printk("%s,%d: CRYPTO key too long.\n", __FILE__, __LINE__); ++ goto error; ++ } ++ memcpy(cesa_ses->cryptoKey, cri->cri_key, cri->cri_klen/8); ++ dprintk("%s,%d: key length %d \n", __FILE__, __LINE__, cri->cri_klen/8); ++ cesa_ses->cryptoKeyLength = cri->cri_klen/8; ++ encrypt += count; ++ break; ++ case CRYPTO_3DES_CBC: ++ dprintk("%s,%d: (%d) 3DES CBC \n", __FILE__, __LINE__, count); ++ cesa_ocf_cur_ses->cipher_alg = cri->cri_alg; ++ cesa_ocf_cur_ses->ivlen = MV_CESA_3DES_BLOCK_SIZE; ++ cesa_ses->cryptoAlgorithm = MV_CESA_CRYPTO_3DES; ++ cesa_ses->cryptoMode = MV_CESA_CRYPTO_CBC; ++ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { ++ printk("%s,%d: CRYPTO key too long.\n", __FILE__, __LINE__); ++ goto error; ++ } ++ memcpy(cesa_ses->cryptoKey, cri->cri_key, cri->cri_klen/8); ++ cesa_ses->cryptoKeyLength = cri->cri_klen/8; ++ encrypt += count; ++ break; ++ case CRYPTO_DES_CBC: ++ dprintk("%s,%d: (%d) DES CBC \n", __FILE__, __LINE__, count); ++ cesa_ocf_cur_ses->cipher_alg = cri->cri_alg; ++ cesa_ocf_cur_ses->ivlen = MV_CESA_DES_BLOCK_SIZE; ++ cesa_ses->cryptoAlgorithm = MV_CESA_CRYPTO_DES; ++ cesa_ses->cryptoMode = MV_CESA_CRYPTO_CBC; ++ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { ++ printk("%s,%d: CRYPTO key too long.\n", __FILE__, __LINE__); ++ goto error; ++ } ++ memcpy(cesa_ses->cryptoKey, cri->cri_key, cri->cri_klen/8); ++ cesa_ses->cryptoKeyLength = cri->cri_klen/8; ++ encrypt += count; ++ break; ++ case CRYPTO_MD5: ++ case CRYPTO_MD5_HMAC: ++ dprintk("%s,%d: (%d) %sMD5 CBC \n", __FILE__, __LINE__, count, (cri->cri_alg != CRYPTO_MD5)? "H-":" "); ++ cesa_ocf_cur_ses->auth_alg = cri->cri_alg; ++ cesa_ocf_cur_ses->digestlen = (cri->cri_alg == CRYPTO_MD5)? MV_CESA_MD5_DIGEST_SIZE : 12; ++ cesa_ses->macMode = (cri->cri_alg == CRYPTO_MD5)? MV_CESA_MAC_MD5 : MV_CESA_MAC_HMAC_MD5; ++ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { ++ printk("%s,%d: MAC key too long. \n", __FILE__, __LINE__); ++ goto error; ++ } ++ cesa_ses->macKeyLength = cri->cri_klen/8; ++ memcpy(cesa_ses->macKey, cri->cri_key, cri->cri_klen/8); ++ cesa_ses->digestSize = cesa_ocf_cur_ses->digestlen; ++ auth += count; ++ break; ++ case CRYPTO_SHA1: ++ case CRYPTO_SHA1_HMAC: ++ dprintk("%s,%d: (%d) %sSHA1 CBC \n", __FILE__, __LINE__, count, (cri->cri_alg != CRYPTO_SHA1)? "H-":" "); ++ cesa_ocf_cur_ses->auth_alg = cri->cri_alg; ++ cesa_ocf_cur_ses->digestlen = (cri->cri_alg == CRYPTO_SHA1)? MV_CESA_SHA1_DIGEST_SIZE : 12; ++ cesa_ses->macMode = (cri->cri_alg == CRYPTO_SHA1)? MV_CESA_MAC_SHA1 : MV_CESA_MAC_HMAC_SHA1; ++ if(cri->cri_klen/8 > MV_CESA_MAX_CRYPTO_KEY_LENGTH) { ++ printk("%s,%d: MAC key too long. \n", __FILE__, __LINE__); ++ goto error; ++ } ++ cesa_ses->macKeyLength = cri->cri_klen/8; ++ memcpy(cesa_ses->macKey, cri->cri_key, cri->cri_klen/8); ++ cesa_ses->digestSize = cesa_ocf_cur_ses->digestlen; ++ auth += count; ++ break; ++ default: ++ printk("%s,%d: unknown algo 0x%x\n", __FILE__, __LINE__, cri->cri_alg); ++ goto error; ++ } ++ cri = cri->cri_next; ++ count++; ++ } ++ ++ if((encrypt > 2) || (auth > 2)) { ++ printk("%s,%d: session mode is not supported.\n", __FILE__, __LINE__); ++ goto error; ++ } ++ /* create new sessions in HAL */ ++ if(encrypt) { ++ cesa_ses->operation = MV_CESA_CRYPTO_ONLY; ++ /* encrypt session */ ++ if(auth == 1) { ++ cesa_ses->operation = MV_CESA_MAC_THEN_CRYPTO; ++ } ++ else if(auth == 2) { ++ cesa_ses->operation = MV_CESA_CRYPTO_THEN_MAC; ++ cesa_ocf_cur_ses->encrypt_tn_auth = 1; ++ } ++ else { ++ cesa_ses->operation = MV_CESA_CRYPTO_ONLY; ++ } ++ cesa_ses->direction = MV_CESA_DIR_ENCODE; ++ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->sid_encrypt); ++ if(status != MV_OK) { ++ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); ++ goto error; ++ } ++ /* decrypt session */ ++ if( cesa_ses->operation == MV_CESA_MAC_THEN_CRYPTO ) { ++ cesa_ses->operation = MV_CESA_CRYPTO_THEN_MAC; ++ } ++ else if( cesa_ses->operation == MV_CESA_CRYPTO_THEN_MAC ) { ++ cesa_ses->operation = MV_CESA_MAC_THEN_CRYPTO; ++ } ++ cesa_ses->direction = MV_CESA_DIR_DECODE; ++ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->sid_decrypt); ++ if(status != MV_OK) { ++ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); ++ goto error; ++ } ++ ++ /* preapre one action sessions for case we will need to split an action */ ++#ifdef CESA_OCF_SPLIT ++ if(( cesa_ses->operation == MV_CESA_MAC_THEN_CRYPTO ) || ++ ( cesa_ses->operation == MV_CESA_CRYPTO_THEN_MAC )) { ++ /* open one session for encode and one for decode */ ++ cesa_ses->operation = MV_CESA_CRYPTO_ONLY; ++ cesa_ses->direction = MV_CESA_DIR_ENCODE; ++ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->frag_wa_encrypt); ++ if(status != MV_OK) { ++ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); ++ goto error; ++ } ++ ++ cesa_ses->direction = MV_CESA_DIR_DECODE; ++ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->frag_wa_decrypt); ++ if(status != MV_OK) { ++ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); ++ goto error; ++ } ++ /* open one session for auth */ ++ cesa_ses->operation = MV_CESA_MAC_ONLY; ++ cesa_ses->direction = MV_CESA_DIR_ENCODE; ++ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->frag_wa_auth); ++ if(status != MV_OK) { ++ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); ++ goto error; ++ } ++ } ++#endif ++ } ++ else { /* only auth */ ++ cesa_ses->operation = MV_CESA_MAC_ONLY; ++ cesa_ses->direction = MV_CESA_DIR_ENCODE; ++ status = mvCesaSessionOpen(cesa_ses, &cesa_ocf_cur_ses->sid_encrypt); ++ if(status != MV_OK) { ++ printk("%s,%d: Can't open new session - status = 0x%x\n", __FILE__, __LINE__, status); ++ goto error; ++ } ++ } ++ ++ return 0; ++error: ++ cesa_ocf_freesession(NULL, *sid); ++ return EINVAL; ++ ++} ++ ++ ++/* ++ * Free a session. ++ */ ++static int ++cesa_ocf_freesession(device_t dev, u_int64_t tid) ++{ ++ struct cesa_ocf_data *cesa_ocf_cur_ses; ++ u_int32_t sid = CRYPTO_SESID2LID(tid); ++ //unsigned long flags; ++ ++ dprintk("%s() %d \n", __FUNCTION__, sid); ++ if ( (sid >= CESA_OCF_MAX_SES) || (cesa_ocf_sessions[sid] == NULL) ) { ++ printk("%s,%d: EINVAL can't free session %d \n", __FILE__, __LINE__, sid); ++ return(EINVAL); ++ } ++ ++ /* Silently accept and return */ ++ if (sid == 0) ++ return(0); ++ ++ /* release session from HAL */ ++ cesa_ocf_cur_ses = cesa_ocf_sessions[sid]; ++ if (cesa_ocf_cur_ses->sid_encrypt != -1) { ++ mvCesaSessionClose(cesa_ocf_cur_ses->sid_encrypt); ++ } ++ if (cesa_ocf_cur_ses->sid_decrypt != -1) { ++ mvCesaSessionClose(cesa_ocf_cur_ses->sid_decrypt); ++ } ++ if (cesa_ocf_cur_ses->frag_wa_encrypt != -1) { ++ mvCesaSessionClose(cesa_ocf_cur_ses->frag_wa_encrypt); ++ } ++ if (cesa_ocf_cur_ses->frag_wa_decrypt != -1) { ++ mvCesaSessionClose(cesa_ocf_cur_ses->frag_wa_decrypt); ++ } ++ if (cesa_ocf_cur_ses->frag_wa_auth != -1) { ++ mvCesaSessionClose(cesa_ocf_cur_ses->frag_wa_auth); ++ } ++ ++ kfree(cesa_ocf_cur_ses); ++ cesa_ocf_sessions[sid] = NULL; ++ ++ return 0; ++} ++ ++ ++/* TDMA Window setup */ ++ ++static void __init ++setup_tdma_mbus_windows(struct cesa_dev *dev) ++{ ++ int i; ++ ++ for (i = 0; i < 4; i++) { ++ writel(0, dev->reg + WINDOW_BASE(i)); ++ writel(0, dev->reg + WINDOW_CTRL(i)); ++ } ++ ++ for (i = 0; i < dev->plat_data->dram->num_cs; i++) { ++ struct mbus_dram_window *cs = dev->plat_data->dram->cs + i; ++ writel( ++ ((cs->size - 1) & 0xffff0000) | ++ (cs->mbus_attr << 8) | ++ (dev->plat_data->dram->mbus_dram_target_id << 4) | 1, ++ dev->reg + WINDOW_CTRL(i) ++ ); ++ writel(cs->base, dev->reg + WINDOW_BASE(i)); ++ } ++} ++ ++/* ++ * our driver startup and shutdown routines ++ */ ++static int ++mv_cesa_ocf_init(struct platform_device *pdev) ++{ ++#if defined(CONFIG_MV78200) || defined(CONFIG_MV632X) ++ if (MV_FALSE == mvSocUnitIsMappedToThisCpu(CESA)) ++ { ++ dprintk("CESA is not mapped to this CPU\n"); ++ return -ENODEV; ++ } ++#endif ++ ++ dprintk("%s\n", __FUNCTION__); ++ memset(&mv_cesa_dev, 0, sizeof(mv_cesa_dev)); ++ softc_device_init(&mv_cesa_dev, "MV CESA", 0, mv_cesa_methods); ++ cesa_ocf_id = crypto_get_driverid(softc_get_device(&mv_cesa_dev),CRYPTOCAP_F_HARDWARE); ++ ++ if (cesa_ocf_id < 0) ++ panic("MV CESA crypto device cannot initialize!"); ++ ++ dprintk("%s,%d: cesa ocf device id is %d \n", __FILE__, __LINE__, cesa_ocf_id); ++ ++ /* CESA unit is auto power on off */ ++#if 0 ++ if (MV_FALSE == mvCtrlPwrClckGet(CESA_UNIT_ID,0)) ++ { ++ printk("\nWarning CESA %d is Powered Off\n",0); ++ return EINVAL; ++ } ++#endif ++ ++ memset(&cesa_device, 0, sizeof(struct cesa_dev)); ++ /* Get the IRQ, and crypto memory regions */ ++ { ++ struct resource *res; ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram"); ++ ++ if (!res) ++ return -ENXIO; ++ ++ cesa_device.sram = ioremap(res->start, res->end - res->start + 1); ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); ++ ++ if (!res) { ++ iounmap(cesa_device.sram); ++ return -ENXIO; ++ } ++ cesa_device.reg = ioremap(res->start, res->end - res->start + 1); ++ cesa_device.irq = platform_get_irq(pdev, 0); ++ cesa_device.plat_data = pdev->dev.platform_data; ++ setup_tdma_mbus_windows(&cesa_device); ++ ++ } ++ ++ ++ if( MV_OK != mvCesaInit(CESA_OCF_MAX_SES*5, CESA_Q_SIZE, cesa_device.reg, ++ NULL) ) { ++ printk("%s,%d: mvCesaInit Failed. \n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ /* clear and unmask Int */ ++ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); ++#ifndef CESA_OCF_POLLING ++ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, MV_CESA_CAUSE_ACC_DMA_MASK); ++#endif ++#ifdef CESA_OCF_TASKLET ++ tasklet_init(&cesa_ocf_tasklet, cesa_callback, (unsigned int) 0); ++#endif ++ /* register interrupt */ ++ if( request_irq( cesa_device.irq, cesa_interrupt_handler, ++ (IRQF_DISABLED) , "cesa", &cesa_ocf_id) < 0) { ++ printk("%s,%d: cannot assign irq %x\n", __FILE__, __LINE__, cesa_device.reg); ++ return EINVAL; ++ } ++ ++ ++ memset(cesa_ocf_sessions, 0, sizeof(struct cesa_ocf_data *) * CESA_OCF_MAX_SES); ++ ++#define REGISTER(alg) \ ++ crypto_register(cesa_ocf_id, alg, 0,0) ++ REGISTER(CRYPTO_AES_CBC); ++ REGISTER(CRYPTO_DES_CBC); ++ REGISTER(CRYPTO_3DES_CBC); ++ REGISTER(CRYPTO_MD5); ++ REGISTER(CRYPTO_MD5_HMAC); ++ REGISTER(CRYPTO_SHA1); ++ REGISTER(CRYPTO_SHA1_HMAC); ++#undef REGISTER ++ ++ return 0; ++} ++ ++static void ++mv_cesa_ocf_exit(struct platform_device *pdev) ++{ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ crypto_unregister_all(cesa_ocf_id); ++ cesa_ocf_id = -1; ++ iounmap(cesa_device.reg); ++ iounmap(cesa_device.sram); ++ free_irq(cesa_device.irq, NULL); ++ ++ /* mask and clear Int */ ++ MV_REG_WRITE( MV_CESA_ISR_MASK_REG, 0); ++ MV_REG_WRITE( MV_CESA_ISR_CAUSE_REG, 0); ++ ++ ++ if( MV_OK != mvCesaFinish() ) { ++ printk("%s,%d: mvCesaFinish Failed. \n", __FILE__, __LINE__); ++ return; ++ } ++} ++ ++ ++void cesa_ocf_debug(void) ++{ ++ ++#ifdef CESA_OCF_TRACE_DEBUG ++ { ++ int i, j; ++ j = cesaTestTraceIdx; ++ mvOsPrintf("No Type rCause iCause Proc Isr Res Time pReady pProc pEmpty\n"); ++ for(i=0; i= _1G) ++ { ++ mvOsOutput("%3dGB ", size / _1G); ++ size %= _1G; ++ if(size) ++ mvOsOutput("+"); ++ } ++ if(size >= _1M ) ++ { ++ mvOsOutput("%3dMB ", size / _1M); ++ size %= _1M; ++ if(size) ++ mvOsOutput("+"); ++ } ++ if(size >= _1K) ++ { ++ mvOsOutput("%3dKB ", size / _1K); ++ size %= _1K; ++ if(size) ++ mvOsOutput("+"); ++ } ++ if(size > 0) ++ { ++ mvOsOutput("%3dB ", size); ++ } ++} ++ ++/******************************************************************************* ++* mvHexToBin - Convert hex to binary ++* ++* DESCRIPTION: ++* This function Convert hex to binary. ++* ++* INPUT: ++* pHexStr - hex buffer pointer. ++* size - Size to convert. ++* ++* OUTPUT: ++* pBin - Binary buffer pointer. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvHexToBin(const char* pHexStr, MV_U8* pBin, int size) ++{ ++ int j, i; ++ char tmp[3]; ++ MV_U8 byte; ++ ++ for(j=0, i=0; j> 1; ++ result++; ++ } ++ return result; ++} ++ ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/common/mvCommon.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/common/mvCommon.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/common/mvCommon.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/common/mvCommon.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,308 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++ ++#ifndef __INCmvCommonh ++#define __INCmvCommonh ++ ++#include "mvTypes.h" ++ ++/* Swap tool */ ++ ++/* 16bit nibble swap. For example 0x1234 -> 0x2143 */ ++#define MV_NIBBLE_SWAP_16BIT(X) (((X&0xf) << 4) | \ ++ ((X&0xf0) >> 4) | \ ++ ((X&0xf00) << 4) | \ ++ ((X&0xf000) >> 4)) ++ ++/* 32bit nibble swap. For example 0x12345678 -> 0x21436587 */ ++#define MV_NIBBLE_SWAP_32BIT(X) (((X&0xf) << 4) | \ ++ ((X&0xf0) >> 4) | \ ++ ((X&0xf00) << 4) | \ ++ ((X&0xf000) >> 4) | \ ++ ((X&0xf0000) << 4) | \ ++ ((X&0xf00000) >> 4) | \ ++ ((X&0xf000000) << 4) | \ ++ ((X&0xf0000000) >> 4)) ++ ++/* 16bit byte swap. For example 0x1122 -> 0x2211 */ ++#define MV_BYTE_SWAP_16BIT(X) ((((X)&0xff)<<8) | (((X)&0xff00)>>8)) ++ ++/* 32bit byte swap. For example 0x11223344 -> 0x44332211 */ ++#define MV_BYTE_SWAP_32BIT(X) ((((X)&0xff)<<24) | \ ++ (((X)&0xff00)<<8) | \ ++ (((X)&0xff0000)>>8) | \ ++ (((X)&0xff000000)>>24)) ++ ++/* 64bit byte swap. For example 0x11223344.55667788 -> 0x88776655.44332211 */ ++#define MV_BYTE_SWAP_64BIT(X) ((l64) ((((X)&0xffULL)<<56) | \ ++ (((X)&0xff00ULL)<<40) | \ ++ (((X)&0xff0000ULL)<<24) | \ ++ (((X)&0xff000000ULL)<<8) | \ ++ (((X)&0xff00000000ULL)>>8) | \ ++ (((X)&0xff0000000000ULL)>>24) | \ ++ (((X)&0xff000000000000ULL)>>40) | \ ++ (((X)&0xff00000000000000ULL)>>56))) ++ ++/* Endianess macros. */ ++#if defined(MV_CPU_LE) ++ #define MV_16BIT_LE(X) (X) ++ #define MV_32BIT_LE(X) (X) ++ #define MV_64BIT_LE(X) (X) ++ #define MV_16BIT_BE(X) MV_BYTE_SWAP_16BIT(X) ++ #define MV_32BIT_BE(X) MV_BYTE_SWAP_32BIT(X) ++ #define MV_64BIT_BE(X) MV_BYTE_SWAP_64BIT(X) ++#elif defined(MV_CPU_BE) ++ #define MV_16BIT_LE(X) MV_BYTE_SWAP_16BIT(X) ++ #define MV_32BIT_LE(X) MV_BYTE_SWAP_32BIT(X) ++ #define MV_64BIT_LE(X) MV_BYTE_SWAP_64BIT(X) ++ #define MV_16BIT_BE(X) (X) ++ #define MV_32BIT_BE(X) (X) ++ #define MV_64BIT_BE(X) (X) ++#else ++ #error "CPU endianess isn't defined!\n" ++#endif ++ ++ ++/* Bit field definitions */ ++#define NO_BIT 0x00000000 ++#define BIT0 0x00000001 ++#define BIT1 0x00000002 ++#define BIT2 0x00000004 ++#define BIT3 0x00000008 ++#define BIT4 0x00000010 ++#define BIT5 0x00000020 ++#define BIT6 0x00000040 ++#define BIT7 0x00000080 ++#define BIT8 0x00000100 ++#define BIT9 0x00000200 ++#define BIT10 0x00000400 ++#define BIT11 0x00000800 ++#define BIT12 0x00001000 ++#define BIT13 0x00002000 ++#define BIT14 0x00004000 ++#define BIT15 0x00008000 ++#define BIT16 0x00010000 ++#define BIT17 0x00020000 ++#define BIT18 0x00040000 ++#define BIT19 0x00080000 ++#define BIT20 0x00100000 ++#define BIT21 0x00200000 ++#define BIT22 0x00400000 ++#define BIT23 0x00800000 ++#define BIT24 0x01000000 ++#define BIT25 0x02000000 ++#define BIT26 0x04000000 ++#define BIT27 0x08000000 ++#define BIT28 0x10000000 ++#define BIT29 0x20000000 ++#define BIT30 0x40000000 ++#define BIT31 0x80000000 ++ ++/* Handy sizes */ ++#define _1K 0x00000400 ++#define _2K 0x00000800 ++#define _4K 0x00001000 ++#define _8K 0x00002000 ++#define _16K 0x00004000 ++#define _32K 0x00008000 ++#define _64K 0x00010000 ++#define _128K 0x00020000 ++#define _256K 0x00040000 ++#define _512K 0x00080000 ++ ++#define _1M 0x00100000 ++#define _2M 0x00200000 ++#define _4M 0x00400000 ++#define _8M 0x00800000 ++#define _16M 0x01000000 ++#define _32M 0x02000000 ++#define _64M 0x04000000 ++#define _128M 0x08000000 ++#define _256M 0x10000000 ++#define _512M 0x20000000 ++ ++#define _1G 0x40000000 ++#define _2G 0x80000000 ++ ++/* Tclock and Sys clock define */ ++#define _100MHz 100000000 ++#define _125MHz 125000000 ++#define _133MHz 133333334 ++#define _150MHz 150000000 ++#define _160MHz 160000000 ++#define _166MHz 166666667 ++#define _175MHz 175000000 ++#define _178MHz 178000000 ++#define _183MHz 183333334 ++#define _187MHz 187000000 ++#define _192MHz 192000000 ++#define _194MHz 194000000 ++#define _200MHz 200000000 ++#define _233MHz 233333334 ++#define _250MHz 250000000 ++#define _266MHz 266666667 ++#define _300MHz 300000000 ++ ++/* For better address window table readability */ ++#define EN MV_TRUE ++#define DIS MV_FALSE ++#define N_A -1 /* Not applicable */ ++ ++/* Cache configuration options for memory (DRAM, SRAM, ... ) */ ++ ++/* Memory uncached, HW or SW cache coherency is not needed */ ++#define MV_UNCACHED 0 ++/* Memory cached, HW cache coherency supported in WriteThrough mode */ ++#define MV_CACHE_COHER_HW_WT 1 ++/* Memory cached, HW cache coherency supported in WriteBack mode */ ++#define MV_CACHE_COHER_HW_WB 2 ++/* Memory cached, No HW cache coherency, Cache coherency must be in SW */ ++#define MV_CACHE_COHER_SW 3 ++ ++ ++/* Macro for testing aligment. Positive if number is NOT aligned */ ++#define MV_IS_NOT_ALIGN(number, align) ((number) & ((align) - 1)) ++ ++/* Macro for alignment up. For example, MV_ALIGN_UP(0x0330, 0x20) = 0x0340 */ ++#define MV_ALIGN_UP(number, align) \ ++(((number) & ((align) - 1)) ? (((number) + (align)) & ~((align)-1)) : (number)) ++ ++/* Macro for alignment down. For example, MV_ALIGN_UP(0x0330, 0x20) = 0x0320 */ ++#define MV_ALIGN_DOWN(number, align) ((number) & ~((align)-1)) ++ ++/* This macro returns absolute value */ ++#define MV_ABS(number) (((int)(number) < 0) ? -(int)(number) : (int)(number)) ++ ++ ++/* Bit fields manipulation macros */ ++ ++/* An integer word which its 'x' bit is set */ ++#define MV_BIT_MASK(bitNum) (1 << (bitNum) ) ++ ++/* Checks wheter bit 'x' in integer word is set */ ++#define MV_BIT_CHECK(word, bitNum) ( (word) & MV_BIT_MASK(bitNum) ) ++ ++/* Clear (reset) bit 'x' in integer word (RMW - Read-Modify-Write) */ ++#define MV_BIT_CLEAR(word, bitNum) ( (word) &= ~(MV_BIT_MASK(bitNum)) ) ++ ++/* Set bit 'x' in integer word (RMW) */ ++#define MV_BIT_SET(word, bitNum) ( (word) |= MV_BIT_MASK(bitNum) ) ++ ++/* Invert bit 'x' in integer word (RMW) */ ++#define MV_BIT_INV(word, bitNum) ( (word) ^= MV_BIT_MASK(bitNum) ) ++ ++/* Get the min between 'a' or 'b' */ ++#define MV_MIN(a,b) (((a) < (b)) ? (a) : (b)) ++ ++/* Get the max between 'a' or 'b' */ ++#define MV_MAX(a,b) (((a) < (b)) ? (b) : (a)) ++ ++/* Temporary */ ++#define mvOsDivide(num, div) \ ++({ \ ++ int i=0, rem=(num); \ ++ \ ++ while(rem >= (div)) \ ++ { \ ++ rem -= (div); \ ++ i++; \ ++ } \ ++ (i); \ ++}) ++ ++/* Temporary */ ++#define mvOsReminder(num, div) \ ++({ \ ++ int rem = (num); \ ++ \ ++ while(rem >= (div)) \ ++ rem -= (div); \ ++ (rem); \ ++}) ++ ++#define MV_IP_QUAD(ipAddr) ((ipAddr >> 24) & 0xFF), ((ipAddr >> 16) & 0xFF), \ ++ ((ipAddr >> 8) & 0xFF), ((ipAddr >> 0) & 0xFF) ++ ++#define MV_IS_POWER_OF_2(num) ((num != 0) && ((num & (num - 1)) == 0)) ++ ++#ifndef MV_ASMLANGUAGE ++/* mvCommon API list */ ++ ++MV_VOID mvHexToBin(const char* pHexStr, MV_U8* pBin, int size); ++void mvAsciiToHex(const char* asciiStr, char* hexStr); ++void mvBinToHex(const MV_U8* bin, char* hexStr, int size); ++void mvBinToAscii(const MV_U8* bin, char* asciiStr, int size); ++ ++MV_STATUS mvMacStrToHex(const char* macStr, MV_U8* macHex); ++MV_STATUS mvMacHexToStr(MV_U8* macHex, char* macStr); ++void mvSizePrint(MV_U32); ++ ++MV_U32 mvLog2(MV_U32 num); ++ ++#endif /* MV_ASMLANGUAGE */ ++ ++ ++#endif /* __INCmvCommonh */ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/common/mvCompVer.txt linux-3.1.4/crypto/ocf/kirkwood/mvHal/common/mvCompVer.txt +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/common/mvCompVer.txt 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/common/mvCompVer.txt 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,4 @@ ++Global HAL Version: FEROCEON_HAL_3_1_7 ++Unit HAL Version: 3.1.4 ++Description: This component includes an implementation of the unit HAL drivers ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/common/mvDebug.c linux-3.1.4/crypto/ocf/kirkwood/mvHal/common/mvDebug.c +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/common/mvDebug.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/common/mvDebug.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,326 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++ ++/* includes */ ++#include "mvOs.h" ++#include "mv802_3.h" ++#include "mvCommon.h" ++#include "mvDebug.h" ++ ++/* Global variables effect on behave MV_DEBUG_PRINT and MV_DEBUG_CODE macros ++ * mvDebug - map of bits (one for each module) bit=1 means enable ++ * debug code and messages for this module ++ * mvModuleDebug - array of 32 bits varables one for each module ++ */ ++MV_U32 mvDebug = 0; ++MV_U32 mvDebugModules[MV_MODULE_MAX]; ++ ++/* Init mvModuleDebug array to default values */ ++void mvDebugInit(void) ++{ ++ int bit; ++ ++ mvDebug = 0; ++ for(bit=0; bit 0) ++ { ++ mvOsPrintf("%08x: ", memAddr); ++ i = 0; ++ /* 32 bytes in the line */ ++ while(i < 32) ++ { ++ if(memAddr >= (MV_U32)addr) ++ { ++ switch(access) ++ { ++ case 1: ++ if( memAddr == CPU_PHY_MEM(memAddr) ) ++ { ++ mvOsPrintf("%02x ", MV_MEMIO8_READ(memAddr)); ++ } ++ else ++ { ++ mvOsPrintf("%02x ", *((MV_U8*)memAddr)); ++ } ++ break; ++ ++ case 2: ++ if( memAddr == CPU_PHY_MEM(memAddr) ) ++ { ++ mvOsPrintf("%04x ", MV_MEMIO16_READ(memAddr)); ++ } ++ else ++ { ++ mvOsPrintf("%04x ", *((MV_U16*)memAddr)); ++ } ++ break; ++ ++ case 4: ++ if( memAddr == CPU_PHY_MEM(memAddr) ) ++ { ++ mvOsPrintf("%08x ", MV_MEMIO32_READ(memAddr)); ++ } ++ else ++ { ++ mvOsPrintf("%08x ", *((MV_U32*)memAddr)); ++ } ++ break; ++ } ++ } ++ else ++ { ++ for(j=0; j<(access*2+1); j++) ++ mvOsPrintf(" "); ++ } ++ i += access; ++ memAddr += access; ++ size -= access; ++ if(size <= 0) ++ break; ++ } ++ mvOsPrintf("\n"); ++ } ++} ++ ++void mvDebugPrintBufInfo(BUF_INFO* pBufInfo, int size, int access) ++{ ++ if(pBufInfo == NULL) ++ { ++ mvOsPrintf("\n!!! pBufInfo = NULL\n"); ++ return; ++ } ++ mvOsPrintf("\n*** pBufInfo=0x%x, cmdSts=0x%08x, pBuf=0x%x, bufSize=%d\n", ++ (unsigned int)pBufInfo, ++ (unsigned int)pBufInfo->cmdSts, ++ (unsigned int)pBufInfo->pBuff, ++ (unsigned int)pBufInfo->bufSize); ++ mvOsPrintf("pData=0x%x, byteCnt=%d, pNext=0x%x, uInfo1=0x%x, uInfo2=0x%x\n", ++ (unsigned int)pBufInfo->pData, ++ (unsigned int)pBufInfo->byteCnt, ++ (unsigned int)pBufInfo->pNextBufInfo, ++ (unsigned int)pBufInfo->userInfo1, ++ (unsigned int)pBufInfo->userInfo2); ++ if(pBufInfo->pData != NULL) ++ { ++ if(size > pBufInfo->byteCnt) ++ size = pBufInfo->byteCnt; ++ mvDebugMemDump(pBufInfo->pData, size, access); ++ } ++} ++ ++void mvDebugPrintPktInfo(MV_PKT_INFO* pPktInfo, int size, int access) ++{ ++ int frag, len; ++ ++ if(pPktInfo == NULL) ++ { ++ mvOsPrintf("\n!!! pPktInfo = NULL\n"); ++ return; ++ } ++ mvOsPrintf("\npPkt=%p, stat=0x%08x, numFr=%d, size=%d, pFr=%p, osInfo=0x%lx\n", ++ pPktInfo, pPktInfo->status, pPktInfo->numFrags, pPktInfo->pktSize, ++ pPktInfo->pFrags, pPktInfo->osInfo); ++ ++ for(frag=0; fragnumFrags; frag++) ++ { ++ mvOsPrintf("#%2d. bufVirt=%p, bufSize=%d\n", ++ frag, pPktInfo->pFrags[frag].bufVirtPtr, ++ pPktInfo->pFrags[frag].bufSize); ++ if(size > 0) ++ { ++ len = MV_MIN((int)pPktInfo->pFrags[frag].bufSize, size); ++ mvDebugMemDump(pPktInfo->pFrags[frag].bufVirtPtr, len, access); ++ size -= len; ++ } ++ } ++ ++} ++ ++void mvDebugPrintIpAddr(MV_U32 ipAddr) ++{ ++ mvOsPrintf("%d.%d.%d.%d", ((ipAddr >> 24) & 0xFF), ((ipAddr >> 16) & 0xFF), ++ ((ipAddr >> 8) & 0xFF), ((ipAddr >> 0) & 0xFF)); ++} ++ ++void mvDebugPrintMacAddr(const MV_U8* pMacAddr) ++{ ++ int i; ++ ++ mvOsPrintf("%02x", (unsigned int)pMacAddr[0]); ++ for(i=1; ibegin = 0; ++ pTimeEntry->count = count; ++ pTimeEntry->end = 0; ++ pTimeEntry->left = pTimeEntry->count; ++ pTimeEntry->total = 0; ++ pTimeEntry->min = 0xFFFFFFFF; ++ pTimeEntry->max = 0x0; ++ strncpy(pTimeEntry->name, pName, sizeof(pTimeEntry->name)-1); ++ pTimeEntry->name[sizeof(pTimeEntry->name)-1] = '\0'; ++} ++ ++/* Print out MV_DEBUG_TIMES entry */ ++void mvDebugPrintTimeEntry(MV_DEBUG_TIMES* pTimeEntry, MV_BOOL isTitle) ++{ ++ int num; ++ ++ if(isTitle == MV_TRUE) ++ mvOsPrintf("Event NumOfEvents TotalTime Average Min Max\n"); ++ ++ num = pTimeEntry->count-pTimeEntry->left; ++ if(num > 0) ++ { ++ mvOsPrintf("%-11s %6u 0x%08lx %6lu %6lu %6lu\n", ++ pTimeEntry->name, num, pTimeEntry->total, pTimeEntry->total/num, ++ pTimeEntry->min, pTimeEntry->max); ++ } ++} ++ ++/* Update MV_DEBUG_TIMES entry */ ++void mvDebugUpdateTimeEntry(MV_DEBUG_TIMES* pTimeEntry) ++{ ++ MV_U32 delta; ++ ++ if(pTimeEntry->left > 0) ++ { ++ if(pTimeEntry->end <= pTimeEntry->begin) ++ { ++ delta = pTimeEntry->begin - pTimeEntry->end; ++ } ++ else ++ { ++ delta = ((MV_U32)0x10000 - pTimeEntry->end) + pTimeEntry->begin; ++ } ++ pTimeEntry->total += delta; ++ ++ if(delta < pTimeEntry->min) ++ pTimeEntry->min = delta; ++ ++ if(delta > pTimeEntry->max) ++ pTimeEntry->max = delta; ++ ++ pTimeEntry->left--; ++ } ++} ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/common/mvDebug.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/common/mvDebug.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/common/mvDebug.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/common/mvDebug.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,178 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++ ++#ifndef __INCmvDebugh ++#define __INCmvDebugh ++ ++/* includes */ ++#include "mvTypes.h" ++ ++typedef enum ++{ ++ MV_MODULE_INVALID = -1, ++ MV_MODULE_ETH = 0, ++ MV_MODULE_IDMA, ++ MV_MODULE_XOR, ++ MV_MODULE_TWASI, ++ MV_MODULE_MGI, ++ MV_MODULE_USB, ++ MV_MODULE_CESA, ++ ++ MV_MODULE_MAX ++}MV_MODULE_ID; ++ ++/* Define generic flags useful for most of modules */ ++#define MV_DEBUG_FLAG_ALL (0) ++#define MV_DEBUG_FLAG_INIT (1 << 0) ++#define MV_DEBUG_FLAG_RX (1 << 1) ++#define MV_DEBUG_FLAG_TX (1 << 2) ++#define MV_DEBUG_FLAG_ERR (1 << 3) ++#define MV_DEBUG_FLAG_TRACE (1 << 4) ++#define MV_DEBUG_FLAG_DUMP (1 << 5) ++#define MV_DEBUG_FLAG_CACHE (1 << 6) ++#define MV_DEBUG_FLAG_IOCTL (1 << 7) ++#define MV_DEBUG_FLAG_STATS (1 << 8) ++ ++extern MV_U32 mvDebug; ++extern MV_U32 mvDebugModules[MV_MODULE_MAX]; ++ ++#ifdef MV_DEBUG ++# define MV_DEBUG_PRINT(module, flags, msg) mvOsPrintf msg ++# define MV_DEBUG_CODE(module, flags, code) code ++#elif defined(MV_RT_DEBUG) ++# define MV_DEBUG_PRINT(module, flags, msg) \ ++ if( (mvDebug & (1<<(module))) && \ ++ ((mvDebugModules[(module)] & (flags)) == (flags)) ) \ ++ mvOsPrintf msg ++# define MV_DEBUG_CODE(module, flags, code) \ ++ if( (mvDebug & (1<<(module))) && \ ++ ((mvDebugModules[(module)] & (flags)) == (flags)) ) \ ++ code ++#else ++# define MV_DEBUG_PRINT(module, flags, msg) ++# define MV_DEBUG_CODE(module, flags, code) ++#endif ++ ++ ++ ++/* typedefs */ ++ ++/* time measurement structure used to check how much time pass between ++ * two points ++ */ ++typedef struct { ++ char name[20]; /* name of the entry */ ++ unsigned long begin; /* time measured on begin point */ ++ unsigned long end; /* time measured on end point */ ++ unsigned long total; /* Accumulated time */ ++ unsigned long left; /* The rest measurement actions */ ++ unsigned long count; /* Maximum measurement actions */ ++ unsigned long min; /* Minimum time from begin to end */ ++ unsigned long max; /* Maximum time from begin to end */ ++} MV_DEBUG_TIMES; ++ ++ ++/* mvDebug.h API list */ ++ ++/****** Error Recording ******/ ++ ++/* Dump memory in specific format: ++ * address: X1X1X1X1 X2X2X2X2 ... X8X8X8X8 ++ */ ++void mvDebugMemDump(void* addr, int size, int access); ++ ++void mvDebugPrintBufInfo(BUF_INFO* pBufInfo, int size, int access); ++ ++void mvDebugPrintPktInfo(MV_PKT_INFO* pPktInfo, int size, int access); ++ ++void mvDebugPrintIpAddr(MV_U32 ipAddr); ++ ++void mvDebugPrintMacAddr(const MV_U8* pMacAddr); ++ ++/**** There are three functions deals with MV_DEBUG_TIMES structure ****/ ++ ++/* Reset MV_DEBUG_TIMES entry */ ++void mvDebugResetTimeEntry(MV_DEBUG_TIMES* pTimeEntry, int count, char* name); ++ ++/* Update MV_DEBUG_TIMES entry */ ++void mvDebugUpdateTimeEntry(MV_DEBUG_TIMES* pTimeEntry); ++ ++/* Print out MV_DEBUG_TIMES entry */ ++void mvDebugPrintTimeEntry(MV_DEBUG_TIMES* pTimeEntry, MV_BOOL isTitle); ++ ++ ++/******** General ***********/ ++ ++/* Change value of mvDebugPrint global variable */ ++ ++void mvDebugInit(void); ++void mvDebugModuleEnable(MV_MODULE_ID module, MV_BOOL isEnable); ++void mvDebugModuleSetFlags(MV_MODULE_ID module, MV_U32 flags); ++void mvDebugModuleClearFlags(MV_MODULE_ID module, MV_U32 flags); ++ ++ ++#endif /* __INCmvDebug.h */ ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/common/mvDeviceId.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,225 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvDeviceIdh ++#define __INCmvDeviceIdh ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++/* defines */ ++#define MARVELL_VEN_ID 0x11ab ++ ++/* Disco-3 */ ++#define MV64460_DEV_ID 0x6480 ++#define MV64460B_DEV_ID 0x6485 ++#define MV64430_DEV_ID 0x6420 ++ ++/* Disco-5 */ ++#define MV64560_DEV_ID 0x6450 ++ ++/* Disco-6 */ ++#define MV64660_DEV_ID 0x6460 ++ ++/* Orion */ ++#define MV_1181_DEV_ID 0x1181 ++#define MV_5181_DEV_ID 0x5181 ++#define MV_5281_DEV_ID 0x5281 ++#define MV_5182_DEV_ID 0x5182 ++#define MV_8660_DEV_ID 0x8660 ++#define MV_5180_DEV_ID 0x5180 ++#define MV_5082_DEV_ID 0x5082 ++#define MV_1281_DEV_ID 0x1281 ++#define MV_6082_DEV_ID 0x6082 ++#define MV_6183_DEV_ID 0x6183 ++#define MV_6183L_DEV_ID 0x6083 ++ ++#define MV_5281_D0_REV 0x4 ++#define MV_5281_D0_ID ((MV_5281_DEV_ID << 16) | MV_5281_D0_REV) ++#define MV_5281_D0_NAME "88F5281 D0" ++ ++#define MV_5281_D1_REV 0x5 ++#define MV_5281_D1_ID ((MV_5281_DEV_ID << 16) | MV_5281_D1_REV) ++#define MV_5281_D1_NAME "88F5281 D1" ++ ++#define MV_5281_D2_REV 0x6 ++#define MV_5281_D2_ID ((MV_5281_DEV_ID << 16) | MV_5281_D2_REV) ++#define MV_5281_D2_NAME "88F5281 D2" ++ ++ ++#define MV_5181L_A0_REV 0x8 /* need for PCIE Er */ ++#define MV_5181_A1_REV 0x1 /* for USB Er ..*/ ++#define MV_5181_B0_REV 0x2 ++#define MV_5181_B1_REV 0x3 ++#define MV_5182_A1_REV 0x1 ++#define MV_5180N_B1_REV 0x3 ++#define MV_5181L_A0_ID ((MV_5181_DEV_ID << 16) | MV_5181L_A0_REV) ++ ++ ++ ++/* kw */ ++#define MV_6281_DEV_ID 0x6281 ++#define MV_6192_DEV_ID 0x6192 ++#define MV_6190_DEV_ID 0x6190 ++#define MV_6180_DEV_ID 0x6180 ++ ++#define MV_6281_A0_REV 0x2 ++#define MV_6281_A0_ID ((MV_6281_DEV_ID << 16) | MV_6281_A0_REV) ++#define MV_6281_A0_NAME "88F6281 A0" ++ ++#define MV_6192_A0_REV 0x2 ++#define MV_6192_A0_ID ((MV_6192_DEV_ID << 16) | MV_6192_A0_REV) ++#define MV_6192_A0_NAME "88F6192 A0" ++ ++#define MV_6190_A0_REV 0x2 ++#define MV_6190_A0_ID ((MV_6190_DEV_ID << 16) | MV_6190_A0_REV) ++#define MV_6190_A0_NAME "88F6190 A0" ++ ++#define MV_6180_A0_REV 0x2 ++#define MV_6180_A0_ID ((MV_6180_DEV_ID << 16) | MV_6180_A0_REV) ++#define MV_6180_A0_NAME "88F6180 A0" ++ ++#define MV_6281_A1_REV 0x3 ++#define MV_6281_A1_ID ((MV_6281_DEV_ID << 16) | MV_6281_A1_REV) ++#define MV_6281_A1_NAME "88F6281 A1" ++ ++#define MV_6192_A1_REV 0x3 ++#define MV_6192_A1_ID ((MV_6192_DEV_ID << 16) | MV_6192_A1_REV) ++#define MV_6192_A1_NAME "88F6192 A1" ++ ++#define MV_6190_A1_REV 0x3 ++#define MV_6190_A1_ID ((MV_6190_DEV_ID << 16) | MV_6190_A1_REV) ++#define MV_6190_A1_NAME "88F6190 A1" ++ ++#define MV_6180_A1_REV 0x3 ++#define MV_6180_A1_ID ((MV_6180_DEV_ID << 16) | MV_6180_A1_REV) ++#define MV_6180_A1_NAME "88F6180 A1" ++ ++#define MV_88F6XXX_A0_REV 0x2 ++#define MV_88F6XXX_A1_REV 0x3 ++/* Disco-Duo */ ++#define MV_78XX0_ZY_DEV_ID 0x6381 ++#define MV_78XX0_ZY_NAME "MV78X00" ++ ++#define MV_78XX0_Z0_REV 0x1 ++#define MV_78XX0_Z0_ID ((MV_78XX0_ZY_DEV_ID << 16) | MV_78XX0_Z0_REV) ++#define MV_78XX0_Z0_NAME "78X00 Z0" ++ ++#define MV_78XX0_Y0_REV 0x2 ++#define MV_78XX0_Y0_ID ((MV_78XX0_ZY_DEV_ID << 16) | MV_78XX0_Y0_REV) ++#define MV_78XX0_Y0_NAME "78X00 Y0" ++ ++#define MV_78XX0_DEV_ID 0x7800 ++#define MV_78XX0_NAME "MV78X00" ++ ++#define MV_76100_DEV_ID 0x7610 ++#define MV_78200_DEV_ID 0x7820 ++#define MV_78100_DEV_ID 0x7810 ++#define MV_78XX0_A0_REV 0x1 ++#define MV_78XX0_A1_REV 0x2 ++ ++#define MV_76100_NAME "MV76100" ++#define MV_78100_NAME "MV78100" ++#define MV_78200_NAME "MV78200" ++ ++#define MV_76100_A0_ID ((MV_76100_DEV_ID << 16) | MV_78XX0_A0_REV) ++#define MV_78100_A0_ID ((MV_78100_DEV_ID << 16) | MV_78XX0_A0_REV) ++#define MV_78200_A0_ID ((MV_78200_DEV_ID << 16) | MV_78XX0_A0_REV) ++ ++#define MV_76100_A1_ID ((MV_76100_DEV_ID << 16) | MV_78XX0_A1_REV) ++#define MV_78100_A1_ID ((MV_78100_DEV_ID << 16) | MV_78XX0_A1_REV) ++#define MV_78200_A1_ID ((MV_78200_DEV_ID << 16) | MV_78XX0_A1_REV) ++ ++#define MV_76100_A0_NAME "MV76100 A0" ++#define MV_78100_A0_NAME "MV78100 A0" ++#define MV_78200_A0_NAME "MV78200 A0" ++#define MV_78XX0_A0_NAME "MV78XX0 A0" ++ ++#define MV_76100_A1_NAME "MV76100 A1" ++#define MV_78100_A1_NAME "MV78100 A1" ++#define MV_78200_A1_NAME "MV78200 A1" ++#define MV_78XX0_A1_NAME "MV78XX0 A1" ++ ++/*MV88F632X family*/ ++#define MV_6321_DEV_ID 0x6321 ++#define MV_6322_DEV_ID 0x6322 ++#define MV_6323_DEV_ID 0x6323 ++ ++#define MV_6321_NAME "88F6321" ++#define MV_6322_NAME "88F6322" ++#define MV_6323_NAME "88F6323" ++ ++#define MV_632X_A1_REV 0x2 ++ ++#define MV_6321_A1_ID ((MV_6321_DEV_ID << 16) | MV_632X_A1_REV) ++#define MV_6322_A1_ID ((MV_6322_DEV_ID << 16) | MV_632X_A1_REV) ++#define MV_6323_A1_ID ((MV_6323_DEV_ID << 16) | MV_632X_A1_REV) ++ ++#define MV_6321_A1_NAME "88F6321 A1" ++#define MV_6322_A1_NAME "88F6322 A1" ++#define MV_6323_A1_NAME "88F6323 A1" ++ ++ ++#endif /* __INCmvDeviceIdh */ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/common/mvHalVer.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/common/mvHalVer.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/common/mvHalVer.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/common/mvHalVer.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,73 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvHalVerh ++#define __INCmvHalVerh ++ ++/* Defines */ ++#define MV_HAL_VERSION "FEROCEON_HAL_3_1_7" ++#define MV_RELEASE_BASELINE "SoCandControllers_FEROCEON_RELEASE_7_9_2009_KW_4_3_4_DD_2_1_4_6183_1_1_4" ++ ++#endif /* __INCmvHalVerh */ +\ No newline at end of file +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/common/mvStack.c linux-3.1.4/crypto/ocf/kirkwood/mvHal/common/mvStack.c +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/common/mvStack.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/common/mvStack.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,100 @@ ++/******************************************************************************* ++* Copyright 2003, Marvell Semiconductor Israel LTD. * ++* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL. * ++* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT * ++* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE * ++* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL. * ++* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED, * ++* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE. * ++* * ++* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, * ++* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL * ++* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K. * ++* (MJKK), MARVELL SEMICONDUCTOR ISRAEL LTD (MSIL). * ++******************************************************************************** ++* mvQueue.c ++* ++* FILENAME: $Workfile: mvStack.c $ ++* REVISION: $Revision: 1.1 $ ++* LAST UPDATE: $Modtime: $ ++* ++* DESCRIPTION: ++* This file implements simple Stack LIFO functionality. ++*******************************************************************************/ ++ ++/* includes */ ++#include "mvOs.h" ++#include "mvTypes.h" ++#include "mvDebug.h" ++#include "mvStack.h" ++ ++/* defines */ ++ ++ ++/* Public functions */ ++ ++ ++/* Purpose: Create new stack ++ * Inputs: ++ * - MV_U32 noOfElements - maximum number of elements in the stack. ++ * Each element 4 bytes size ++ * Return: void* - pointer to created stack. ++ */ ++void* mvStackCreate(int numOfElements) ++{ ++ MV_STACK* pStack; ++ MV_U32* pStackElements; ++ ++ pStack = (MV_STACK*)mvOsMalloc(sizeof(MV_STACK)); ++ pStackElements = (MV_U32*)mvOsMalloc(numOfElements*sizeof(MV_U32)); ++ if( (pStack == NULL) || (pStackElements == NULL) ) ++ { ++ mvOsPrintf("mvStack: Can't create new stack\n"); ++ return NULL; ++ } ++ memset(pStackElements, 0, numOfElements*sizeof(MV_U32)); ++ pStack->numOfElements = numOfElements; ++ pStack->stackIdx = 0; ++ pStack->stackElements = pStackElements; ++ ++ return pStack; ++} ++ ++/* Purpose: Delete existing stack ++ * Inputs: ++ * - void* stackHndl - Stack handle as returned by "mvStackCreate()" function ++ * ++ * Return: MV_STATUS MV_NOT_FOUND - Failure. StackHandle is not valid. ++ * MV_OK - Success. ++ */ ++MV_STATUS mvStackDelete(void* stackHndl) ++{ ++ MV_STACK* pStack = (MV_STACK*)stackHndl; ++ ++ if( (pStack == NULL) || (pStack->stackElements == NULL) ) ++ return MV_NOT_FOUND; ++ ++ mvOsFree(pStack->stackElements); ++ mvOsFree(pStack); ++ ++ return MV_OK; ++} ++ ++ ++/* PrintOut status of the stack */ ++void mvStackStatus(void* stackHndl, MV_BOOL isPrintElements) ++{ ++ int i; ++ MV_STACK* pStack = (MV_STACK*)stackHndl; ++ ++ mvOsPrintf("StackHandle=%p, pElements=%p, numElements=%d, stackIdx=%d\n", ++ stackHndl, pStack->stackElements, pStack->numOfElements, ++ pStack->stackIdx); ++ if(isPrintElements == MV_TRUE) ++ { ++ for(i=0; istackIdx; i++) ++ { ++ mvOsPrintf("%3d. Value=0x%x\n", i, pStack->stackElements[i]); ++ } ++ } ++} +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/common/mvStack.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/common/mvStack.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/common/mvStack.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/common/mvStack.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,140 @@ ++/******************************************************************************* ++* Copyright 2003, Marvell Semiconductor Israel LTD. * ++* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL. * ++* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT * ++* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE * ++* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL. * ++* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED, * ++* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE. * ++* * ++* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, * ++* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL * ++* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K. * ++* (MJKK), MARVELL SEMICONDUCTOR ISRAEL LTD (MSIL). * ++******************************************************************************** ++* mvStack.h - Header File for : ++* ++* FILENAME: $Workfile: mvStack.h $ ++* REVISION: $Revision: 1.1 $ ++* LAST UPDATE: $Modtime: $ ++* ++* DESCRIPTION: ++* This file defines simple Stack (LIFO) functionality. ++* ++*******************************************************************************/ ++ ++#ifndef __mvStack_h__ ++#define __mvStack_h__ ++ ++ ++/* includes */ ++#include "mvTypes.h" ++ ++ ++/* defines */ ++ ++ ++/* typedefs */ ++/* Data structure describes general purpose Stack */ ++typedef struct ++{ ++ int stackIdx; ++ int numOfElements; ++ MV_U32* stackElements; ++} MV_STACK; ++ ++static INLINE MV_BOOL mvStackIsFull(void* stackHndl) ++{ ++ MV_STACK* pStack = (MV_STACK*)stackHndl; ++ ++ if(pStack->stackIdx == pStack->numOfElements) ++ return MV_TRUE; ++ ++ return MV_FALSE; ++} ++ ++static INLINE MV_BOOL mvStackIsEmpty(void* stackHndl) ++{ ++ MV_STACK* pStack = (MV_STACK*)stackHndl; ++ ++ if(pStack->stackIdx == 0) ++ return MV_TRUE; ++ ++ return MV_FALSE; ++} ++/* Purpose: Push new element to stack ++ * Inputs: ++ * - void* stackHndl - Stack handle as returned by "mvStackCreate()" function. ++ * - MV_U32 value - New element. ++ * ++ * Return: MV_STATUS MV_FULL - Failure. Stack is full. ++ * MV_OK - Success. Element is put to stack. ++ */ ++static INLINE void mvStackPush(void* stackHndl, MV_U32 value) ++{ ++ MV_STACK* pStack = (MV_STACK*)stackHndl; ++ ++#ifdef MV_RT_DEBUG ++ if(pStack->stackIdx == pStack->numOfElements) ++ { ++ mvOsPrintf("mvStackPush: Stack is FULL\n"); ++ return; ++ } ++#endif /* MV_RT_DEBUG */ ++ ++ pStack->stackElements[pStack->stackIdx] = value; ++ pStack->stackIdx++; ++} ++ ++/* Purpose: Pop element from the top of stack and copy it to "pValue" ++ * Inputs: ++ * - void* stackHndl - Stack handle as returned by "mvStackCreate()" function. ++ * - MV_U32 value - Element in the top of stack. ++ * ++ * Return: MV_STATUS MV_EMPTY - Failure. Stack is empty. ++ * MV_OK - Success. Element is removed from the stack and ++ * copied to pValue argument ++ */ ++static INLINE MV_U32 mvStackPop(void* stackHndl) ++{ ++ MV_STACK* pStack = (MV_STACK*)stackHndl; ++ ++#ifdef MV_RT_DEBUG ++ if(pStack->stackIdx == 0) ++ { ++ mvOsPrintf("mvStackPop: Stack is EMPTY\n"); ++ return 0; ++ } ++#endif /* MV_RT_DEBUG */ ++ ++ pStack->stackIdx--; ++ return pStack->stackElements[pStack->stackIdx]; ++} ++ ++static INLINE int mvStackIndex(void* stackHndl) ++{ ++ MV_STACK* pStack = (MV_STACK*)stackHndl; ++ ++ return pStack->stackIdx; ++} ++ ++static INLINE int mvStackFreeElements(void* stackHndl) ++{ ++ MV_STACK* pStack = (MV_STACK*)stackHndl; ++ ++ return (pStack->numOfElements - pStack->stackIdx); ++} ++ ++/* mvStack.h API list */ ++ ++/* Create new Stack */ ++void* mvStackCreate(int numOfElements); ++ ++/* Delete existing stack */ ++MV_STATUS mvStackDelete(void* stackHndl); ++ ++/* Print status of the stack */ ++void mvStackStatus(void* stackHndl, MV_BOOL isPrintElements); ++ ++#endif /* __mvStack_h__ */ ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/common/mvTypes.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/common/mvTypes.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/common/mvTypes.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/common/mvTypes.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,245 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvTypesh ++#define __INCmvTypesh ++ ++/* Defines */ ++ ++/* The following is a list of Marvell status */ ++#define MV_ERROR (-1) ++#define MV_OK (0x00) /* Operation succeeded */ ++#define MV_FAIL (0x01) /* Operation failed */ ++#define MV_BAD_VALUE (0x02) /* Illegal value (general) */ ++#define MV_OUT_OF_RANGE (0x03) /* The value is out of range */ ++#define MV_BAD_PARAM (0x04) /* Illegal parameter in function called */ ++#define MV_BAD_PTR (0x05) /* Illegal pointer value */ ++#define MV_BAD_SIZE (0x06) /* Illegal size */ ++#define MV_BAD_STATE (0x07) /* Illegal state of state machine */ ++#define MV_SET_ERROR (0x08) /* Set operation failed */ ++#define MV_GET_ERROR (0x09) /* Get operation failed */ ++#define MV_CREATE_ERROR (0x0A) /* Fail while creating an item */ ++#define MV_NOT_FOUND (0x0B) /* Item not found */ ++#define MV_NO_MORE (0x0C) /* No more items found */ ++#define MV_NO_SUCH (0x0D) /* No such item */ ++#define MV_TIMEOUT (0x0E) /* Time Out */ ++#define MV_NO_CHANGE (0x0F) /* Parameter(s) is already in this value */ ++#define MV_NOT_SUPPORTED (0x10) /* This request is not support */ ++#define MV_NOT_IMPLEMENTED (0x11) /* Request supported but not implemented */ ++#define MV_NOT_INITIALIZED (0x12) /* The item is not initialized */ ++#define MV_NO_RESOURCE (0x13) /* Resource not available (memory ...) */ ++#define MV_FULL (0x14) /* Item is full (Queue or table etc...) */ ++#define MV_EMPTY (0x15) /* Item is empty (Queue or table etc...) */ ++#define MV_INIT_ERROR (0x16) /* Error occured while INIT process */ ++#define MV_HW_ERROR (0x17) /* Hardware error */ ++#define MV_TX_ERROR (0x18) /* Transmit operation not succeeded */ ++#define MV_RX_ERROR (0x19) /* Recieve operation not succeeded */ ++#define MV_NOT_READY (0x1A) /* The other side is not ready yet */ ++#define MV_ALREADY_EXIST (0x1B) /* Tried to create existing item */ ++#define MV_OUT_OF_CPU_MEM (0x1C) /* Cpu memory allocation failed. */ ++#define MV_NOT_STARTED (0x1D) /* Not started yet */ ++#define MV_BUSY (0x1E) /* Item is busy. */ ++#define MV_TERMINATE (0x1F) /* Item terminates it's work. */ ++#define MV_NOT_ALIGNED (0x20) /* Wrong alignment */ ++#define MV_NOT_ALLOWED (0x21) /* Operation NOT allowed */ ++#define MV_WRITE_PROTECT (0x22) /* Write protected */ ++ ++ ++#define MV_INVALID (int)(-1) ++ ++#define MV_FALSE 0 ++#define MV_TRUE (!(MV_FALSE)) ++ ++ ++#ifndef NULL ++#define NULL ((void*)0) ++#endif ++ ++ ++#ifndef MV_ASMLANGUAGE ++/* typedefs */ ++ ++typedef char MV_8; ++typedef unsigned char MV_U8; ++ ++typedef int MV_32; ++typedef unsigned int MV_U32; ++ ++typedef short MV_16; ++typedef unsigned short MV_U16; ++ ++#ifdef MV_PPC64 ++typedef long MV_64; ++typedef unsigned long MV_U64; ++#else ++typedef long long MV_64; ++typedef unsigned long long MV_U64; ++#endif ++ ++typedef long MV_LONG; /* 32/64 */ ++typedef unsigned long MV_ULONG; /* 32/64 */ ++ ++typedef int MV_STATUS; ++typedef int MV_BOOL; ++typedef void MV_VOID; ++typedef float MV_FLOAT; ++ ++typedef int (*MV_FUNCPTR) (void); /* ptr to function returning int */ ++typedef void (*MV_VOIDFUNCPTR) (void); /* ptr to function returning void */ ++typedef double (*MV_DBLFUNCPTR) (void); /* ptr to function returning double*/ ++typedef float (*MV_FLTFUNCPTR) (void); /* ptr to function returning float */ ++ ++typedef MV_U32 MV_KHZ; ++typedef MV_U32 MV_MHZ; ++typedef MV_U32 MV_HZ; ++ ++ ++/* This enumerator describes the set of commands that can be applied on */ ++/* an engine (e.g. IDMA, XOR). Appling a comman depends on the current */ ++/* status (see MV_STATE enumerator) */ ++/* Start can be applied only when status is IDLE */ ++/* Stop can be applied only when status is IDLE, ACTIVE or PAUSED */ ++/* Pause can be applied only when status is ACTIVE */ ++/* Restart can be applied only when status is PAUSED */ ++typedef enum _mvCommand ++{ ++ MV_START, /* Start */ ++ MV_STOP, /* Stop */ ++ MV_PAUSE, /* Pause */ ++ MV_RESTART /* Restart */ ++} MV_COMMAND; ++ ++/* This enumerator describes the set of state conditions. */ ++/* Moving from one state to other is stricted. */ ++typedef enum _mvState ++{ ++ MV_IDLE, ++ MV_ACTIVE, ++ MV_PAUSED, ++ MV_UNDEFINED_STATE ++} MV_STATE; ++ ++ ++/* This structure describes address space window. Window base can be */ ++/* 64 bit, window size up to 4GB */ ++typedef struct _mvAddrWin ++{ ++ MV_U32 baseLow; /* 32bit base low */ ++ MV_U32 baseHigh; /* 32bit base high */ ++ MV_U32 size; /* 32bit size */ ++}MV_ADDR_WIN; ++ ++/* This binary enumerator describes protection attribute status */ ++typedef enum _mvProtRight ++{ ++ ALLOWED, /* Protection attribute allowed */ ++ FORBIDDEN /* Protection attribute forbidden */ ++}MV_PROT_RIGHT; ++ ++/* Unified struct for Rx and Tx packet operations. The user is required to */ ++/* be familier only with Tx/Rx descriptor command status. */ ++typedef struct _bufInfo ++{ ++ MV_U32 cmdSts; /* Tx/Rx command status */ ++ MV_U16 byteCnt; /* Size of valid data in the buffer */ ++ MV_U16 bufSize; /* Total size of the buffer */ ++ MV_U8 *pBuff; /* Pointer to Buffer */ ++ MV_U8 *pData; /* Pointer to data in the Buffer */ ++ MV_U32 userInfo1; /* Tx/Rx attached user information 1 */ ++ MV_U32 userInfo2; /* Tx/Rx attached user information 2 */ ++ struct _bufInfo *pNextBufInfo; /* Next buffer in packet */ ++} BUF_INFO; ++ ++/* This structure contains information describing one of buffers ++ * (fragments) they are built Ethernet packet. ++ */ ++typedef struct ++{ ++ MV_U8* bufVirtPtr; ++ MV_ULONG bufPhysAddr; ++ MV_U32 bufSize; ++ MV_U32 dataSize; ++ MV_U32 memHandle; ++ MV_32 bufAddrShift; ++} MV_BUF_INFO; ++ ++/* This structure contains information describing Ethernet packet. ++ * The packet can be divided for few buffers (fragments) ++ */ ++typedef struct ++{ ++ MV_ULONG osInfo; ++ MV_BUF_INFO *pFrags; ++ MV_U32 status; ++ MV_U16 pktSize; ++ MV_U16 numFrags; ++ MV_U32 ownerId; ++ MV_U32 fragIP; ++} MV_PKT_INFO; ++ ++#endif /* MV_ASMLANGUAGE */ ++ ++#endif /* __INCmvTypesh */ ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/dbg-trace.c linux-3.1.4/crypto/ocf/kirkwood/mvHal/dbg-trace.c +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/dbg-trace.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/dbg-trace.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,110 @@ ++#include ++#include ++#include ++#include "dbg-trace.h" ++ ++#define TRACE_ARR_LEN 800 ++#define STR_LEN 128 ++struct trace { ++ struct timeval tv; ++ char str[STR_LEN]; ++ unsigned int callback_val1; ++ unsigned int callback_val2; ++ char valid; ++}; ++static unsigned int (*trc_callback1) (unsigned char) = NULL; ++static unsigned int (*trc_callback2) (unsigned char) = NULL; ++static unsigned char trc_param1 = 0; ++static unsigned char trc_param2 = 0; ++struct trace *trc_arr; ++static int trc_index; ++static int trc_active = 0; ++ ++void TRC_START() ++{ ++ trc_active = 1; ++} ++ ++void TRC_STOP() ++{ ++ trc_active = 0; ++} ++ ++void TRC_INIT(void *callback1, void *callback2, unsigned char callback1_param, unsigned char callback2_param) ++{ ++ printk("Marvell debug tracing is on\n"); ++ trc_arr = (struct trace *)kmalloc(TRACE_ARR_LEN*sizeof(struct trace),GFP_KERNEL); ++ if(trc_arr == NULL) ++ { ++ printk("Can't allocate Debug Trace buffer\n"); ++ return; ++ } ++ memset(trc_arr,0,TRACE_ARR_LEN*sizeof(struct trace)); ++ trc_index = 0; ++ trc_callback1 = callback1; ++ trc_callback2 = callback2; ++ trc_param1 = callback1_param; ++ trc_param2 = callback2_param; ++} ++void TRC_REC(char *fmt,...) ++{ ++ va_list args; ++ struct trace *trc = &trc_arr[trc_index]; ++ ++ if(trc_active == 0) ++ return; ++ ++ do_gettimeofday(&trc->tv); ++ if(trc_callback1) ++ trc->callback_val1 = trc_callback1(trc_param1); ++ if(trc_callback2) ++ trc->callback_val2 = trc_callback2(trc_param2); ++ va_start(args, fmt); ++ vsprintf(trc->str,fmt,args); ++ va_end(args); ++ trc->valid = 1; ++ if((++trc_index) == TRACE_ARR_LEN) { ++ trc_index = 0; ++ } ++} ++void TRC_OUTPUT(void) ++{ ++ int i,j; ++ struct trace *p; ++ printk("\n\nTrace %d items\n",TRACE_ARR_LEN); ++ for(i=0,j=trc_index; ivalid) { ++ unsigned long uoffs; ++ struct trace *plast; ++ if(p == &trc_arr[0]) ++ plast = &trc_arr[TRACE_ARR_LEN-1]; ++ else ++ plast = p-1; ++ if(p->tv.tv_sec == ((plast)->tv.tv_sec)) ++ uoffs = (p->tv.tv_usec - ((plast)->tv.tv_usec)); ++ else ++ uoffs = (1000000 - ((plast)->tv.tv_usec)) + ++ ((p->tv.tv_sec - ((plast)->tv.tv_sec) - 1) * 1000000) + ++ p->tv.tv_usec; ++ printk("%03d: [+%ld usec]", j, (unsigned long)uoffs); ++ if(trc_callback1) ++ printk("[%u]",p->callback_val1); ++ if(trc_callback2) ++ printk("[%u]",p->callback_val2); ++ printk(": %s",p->str); ++ } ++ p->valid = 0; ++ } ++ memset(trc_arr,0,TRACE_ARR_LEN*sizeof(struct trace)); ++ trc_index = 0; ++} ++void TRC_RELEASE(void) ++{ ++ kfree(trc_arr); ++ trc_index = 0; ++} ++ ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/dbg-trace.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/dbg-trace.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/dbg-trace.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/dbg-trace.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,24 @@ ++ ++#ifndef _MV_DBG_TRCE_H_ ++#define _MV_DBG_TRCE_H_ ++ ++#ifdef CONFIG_MV_DBG_TRACE ++void TRC_INIT(void *callback1, void *callback2, ++ unsigned char callback1_param, unsigned char callback2_param); ++void TRC_REC(char *fmt,...); ++void TRC_OUTPUT(void); ++void TRC_RELEASE(void); ++void TRC_START(void); ++void TRC_STOP(void); ++ ++#else ++#define TRC_INIT(x1,x2,x3,x4) ++#define TRC_REC(X...) ++#define TRC_OUTPUT() ++#define TRC_RELEASE() ++#define TRC_START() ++#define TRC_STOP() ++#endif ++ ++ ++#endif +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,2513 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#include "boardEnv/mvBoardEnvLib.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "ctrlEnv/sys/mvCpuIf.h" ++#include "cpu/mvCpu.h" ++#include "cntmr/mvCntmr.h" ++#include "gpp/mvGpp.h" ++#include "twsi/mvTwsi.h" ++#include "pex/mvPex.h" ++#include "device/mvDevice.h" ++#include "eth/gbe/mvEthRegs.h" ++ ++/* defines */ ++/* #define MV_DEBUG */ ++#ifdef MV_DEBUG ++ #define DB(x) x ++#else ++ #define DB(x) ++#endif ++ ++extern MV_CPU_ARM_CLK _cpuARMDDRCLK[]; ++ ++#define CODE_IN_ROM MV_FALSE ++#define CODE_IN_RAM MV_TRUE ++ ++extern MV_BOARD_INFO* boardInfoTbl[]; ++#define BOARD_INFO(boardId) boardInfoTbl[boardId - BOARD_ID_BASE] ++ ++/* Locals */ ++static MV_DEV_CS_INFO* boardGetDevEntry(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); ++ ++MV_U32 tClkRate = -1; ++ ++ ++/******************************************************************************* ++* mvBoardEnvInit - Init board ++* ++* DESCRIPTION: ++* In this function the board environment take care of device bank ++* initialization. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvBoardEnvInit(MV_VOID) ++{ ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardEnvInit:Board unknown.\n"); ++ return; ++ ++ } ++ ++ /* Set GPP Out value */ ++ MV_REG_WRITE(GPP_DATA_OUT_REG(0), BOARD_INFO(boardId)->gppOutValLow); ++ MV_REG_WRITE(GPP_DATA_OUT_REG(1), BOARD_INFO(boardId)->gppOutValHigh); ++ ++ /* set GPP polarity */ ++ mvGppPolaritySet(0, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValLow); ++ mvGppPolaritySet(1, 0xFFFFFFFF, BOARD_INFO(boardId)->gppPolarityValHigh); ++ ++ /* Workaround for Erratum FE-MISC-70*/ ++ if(mvCtrlRevGet()==MV_88F6XXX_A0_REV) ++ { ++ BOARD_INFO(boardId)->gppOutEnValLow &= 0xfffffffd; ++ BOARD_INFO(boardId)->gppOutEnValLow |= (BOARD_INFO(boardId)->gppOutEnValHigh) & 0x00000002; ++ } /*End of WA*/ ++ ++ /* Set GPP Out Enable*/ ++ mvGppTypeSet(0, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValLow); ++ mvGppTypeSet(1, 0xFFFFFFFF, BOARD_INFO(boardId)->gppOutEnValHigh); ++ ++ /* Nand CE */ ++ MV_REG_BIT_SET(NAND_CTRL_REG, NAND_ACTCEBOOT_BIT); ++} ++ ++/******************************************************************************* ++* mvBoardModelGet - Get Board model ++* ++* DESCRIPTION: ++* This function returns 16bit describing board model. ++* Board model is constructed of one byte major and minor numbers in the ++* following manner: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* String describing board model. ++* ++*******************************************************************************/ ++MV_U16 mvBoardModelGet(MV_VOID) ++{ ++ return (mvBoardIdGet() >> 16); ++} ++ ++/******************************************************************************* ++* mbBoardRevlGet - Get Board revision ++* ++* DESCRIPTION: ++* This function returns a 32bit describing the board revision. ++* Board revision is constructed of 4bytes. 2bytes describes major number ++* and the other 2bytes describes minor munber. ++* For example for board revision 3.4 the function will return ++* 0x00030004. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* String describing board model. ++* ++*******************************************************************************/ ++MV_U16 mvBoardRevGet(MV_VOID) ++{ ++ return (mvBoardIdGet() & 0xFFFF); ++} ++ ++/******************************************************************************* ++* mvBoardNameGet - Get Board name ++* ++* DESCRIPTION: ++* This function returns a string describing the board model and revision. ++* String is extracted from board I2C EEPROM. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* pNameBuff - Buffer to contain board name string. Minimum size 32 chars. ++* ++* RETURN: ++* ++* MV_ERROR if informantion can not be read. ++*******************************************************************************/ ++MV_STATUS mvBoardNameGet(char *pNameBuff) ++{ ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsSPrintf (pNameBuff, "Board unknown.\n"); ++ return MV_ERROR; ++ ++ } ++ ++ mvOsSPrintf (pNameBuff, "%s",BOARD_INFO(boardId)->boardName); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvBoardIsPortInSgmii - ++* ++* DESCRIPTION: ++* This routine returns MV_TRUE for port number works in SGMII or MV_FALSE ++* For all other options. ++* ++* INPUT: ++* ethPortNum - Ethernet port number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE - port in SGMII. ++* MV_FALSE - other. ++* ++*******************************************************************************/ ++MV_BOOL mvBoardIsPortInSgmii(MV_U32 ethPortNum) ++{ ++ MV_BOOL ethPortSgmiiSupport[BOARD_ETH_PORT_NUM] = MV_ETH_PORT_SGMII; ++ ++ if(ethPortNum >= BOARD_ETH_PORT_NUM) ++ { ++ mvOsPrintf ("Invalid portNo=%d\n", ethPortNum); ++ return MV_FALSE; ++ } ++ return ethPortSgmiiSupport[ethPortNum]; ++} ++ ++/******************************************************************************* ++* mvBoardIsPortInGmii - ++* ++* DESCRIPTION: ++* This routine returns MV_TRUE for port number works in GMII or MV_FALSE ++* For all other options. ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE - port in GMII. ++* MV_FALSE - other. ++* ++*******************************************************************************/ ++MV_BOOL mvBoardIsPortInGmii(MV_VOID) ++{ ++ MV_U32 devClassId, devClass = 0; ++ if (mvBoardMppGroupTypeGet(devClass) == MV_BOARD_AUTO) ++ { ++ /* Get MPP module ID */ ++ devClassId = mvBoarModuleTypeGet(devClass); ++ if (MV_BOARD_MODULE_GMII_ID == devClassId) ++ return MV_TRUE; ++ } ++ else if (mvBoardMppGroupTypeGet(devClass) == MV_BOARD_GMII) ++ return MV_TRUE; ++ ++ return MV_FALSE; ++} ++/******************************************************************************* ++* mvBoardPhyAddrGet - Get the phy address ++* ++* DESCRIPTION: ++* This routine returns the Phy address of a given ethernet port. ++* ++* INPUT: ++* ethPortNum - Ethernet port number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit describing Phy address, -1 if the port number is wrong. ++* ++*******************************************************************************/ ++MV_32 mvBoardPhyAddrGet(MV_U32 ethPortNum) ++{ ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardPhyAddrGet: Board unknown.\n"); ++ return MV_ERROR; ++ } ++ ++ return BOARD_INFO(boardId)->pBoardMacInfo[ethPortNum].boardEthSmiAddr; ++} ++ ++/******************************************************************************* ++* mvBoardMacSpeedGet - Get the Mac speed ++* ++* DESCRIPTION: ++* This routine returns the Mac speed if pre define of a given ethernet port. ++* ++* INPUT: ++* ethPortNum - Ethernet port number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BOARD_MAC_SPEED, -1 if the port number is wrong. ++* ++*******************************************************************************/ ++MV_BOARD_MAC_SPEED mvBoardMacSpeedGet(MV_U32 ethPortNum) ++{ ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardMacSpeedGet: Board unknown.\n"); ++ return MV_ERROR; ++ } ++ ++ return BOARD_INFO(boardId)->pBoardMacInfo[ethPortNum].boardMacSpeed; ++} ++ ++/******************************************************************************* ++* mvBoardLinkStatusIrqGet - Get the IRQ number for the link status indication ++* ++* DESCRIPTION: ++* This routine returns the IRQ number for the link status indication. ++* ++* INPUT: ++* ethPortNum - Ethernet port number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* the number of the IRQ for the link status indication, -1 if the port ++* number is wrong or if not relevant. ++* ++*******************************************************************************/ ++MV_32 mvBoardLinkStatusIrqGet(MV_U32 ethPortNum) ++{ ++ MV_U32 boardId = mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardLinkStatusIrqGet: Board unknown.\n"); ++ return MV_ERROR; ++ } ++ ++ return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].linkStatusIrq; ++} ++ ++/******************************************************************************* ++* mvBoardSwitchPortGet - Get the mapping between the board connector and the ++* Ethernet Switch port ++* ++* DESCRIPTION: ++* This routine returns the matching Switch port. ++* ++* INPUT: ++* ethPortNum - Ethernet port number. ++* boardPortNum - logical number of the connector on the board ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* the matching Switch port, -1 if the port number is wrong or if not relevant. ++* ++*******************************************************************************/ ++MV_32 mvBoardSwitchPortGet(MV_U32 ethPortNum, MV_U8 boardPortNum) ++{ ++ MV_U32 boardId = mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardSwitchPortGet: Board unknown.\n"); ++ return MV_ERROR; ++ } ++ if (boardPortNum >= BOARD_ETH_SWITCH_PORT_NUM) ++ { ++ mvOsPrintf("mvBoardSwitchPortGet: Illegal board port number.\n"); ++ return MV_ERROR; ++ } ++ ++ return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].qdPort[boardPortNum]; ++} ++ ++/******************************************************************************* ++* mvBoardSwitchCpuPortGet - Get the the Ethernet Switch CPU port ++* ++* DESCRIPTION: ++* This routine returns the Switch CPU port. ++* ++* INPUT: ++* ethPortNum - Ethernet port number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* the Switch CPU port, -1 if the port number is wrong or if not relevant. ++* ++*******************************************************************************/ ++MV_32 mvBoardSwitchCpuPortGet(MV_U32 ethPortNum) ++{ ++ MV_U32 boardId = mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardSwitchCpuPortGet: Board unknown.\n"); ++ return MV_ERROR; ++ } ++ ++ return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].qdCpuPort; ++} ++ ++/******************************************************************************* ++* mvBoardIsSwitchConnected - Get switch connection status ++* DESCRIPTION: ++* This routine returns port's connection status ++* ++* INPUT: ++* ethPortNum - Ethernet port number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 1 - if ethPortNum is connected to switch, 0 otherwise ++* ++*******************************************************************************/ ++MV_32 mvBoardIsSwitchConnected(MV_U32 ethPortNum) ++{ ++ MV_U32 boardId = mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardIsSwitchConnected: Board unknown.\n"); ++ return MV_ERROR; ++ } ++ ++ if(ethPortNum >= BOARD_INFO(boardId)->numBoardMacInfo) ++ { ++ mvOsPrintf("mvBoardIsSwitchConnected: Illegal port number(%u)\n", ethPortNum); ++ return MV_ERROR; ++ } ++ ++ if((MV_32)(BOARD_INFO(boardId)->pSwitchInfo)) ++ return (MV_32)(BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].switchOnPort == ethPortNum); ++ else ++ return 0; ++} ++/******************************************************************************* ++* mvBoardSmiScanModeGet - Get Switch SMI scan mode ++* ++* DESCRIPTION: ++* This routine returns Switch SMI scan mode. ++* ++* INPUT: ++* ethPortNum - Ethernet port number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 1 for SMI_MANUAL_MODE, -1 if the port number is wrong or if not relevant. ++* ++*******************************************************************************/ ++MV_32 mvBoardSmiScanModeGet(MV_U32 ethPortNum) ++{ ++ MV_U32 boardId = mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardSmiScanModeGet: Board unknown.\n"); ++ return MV_ERROR; ++ } ++ ++ return BOARD_INFO(boardId)->pSwitchInfo[ethPortNum].smiScanMode; ++} ++/******************************************************************************* ++* mvBoardSpecInitGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: Return MV_TRUE and parameters in case board need spesific phy init, ++* otherwise return MV_FALSE. ++* ++* ++*******************************************************************************/ ++ ++MV_BOOL mvBoardSpecInitGet(MV_U32* regOff, MV_U32* data) ++{ ++ return MV_FALSE; ++} ++ ++/******************************************************************************* ++* mvBoardTclkGet - Get the board Tclk (Controller clock) ++* ++* DESCRIPTION: ++* This routine extract the controller core clock. ++* This function uses the controller counters to make identification. ++* Note: In order to avoid interference, make sure task context switch ++* and interrupts will not occure during this function operation ++* ++* INPUT: ++* countNum - Counter number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit clock cycles in Hertz. ++* ++*******************************************************************************/ ++MV_U32 mvBoardTclkGet(MV_VOID) ++{ ++ if(mvCtrlModelGet()==MV_6281_DEV_ID) ++ { ++#if defined(TCLK_AUTO_DETECT) ++ MV_U32 tmpTClkRate = MV_BOARD_TCLK_166MHZ; ++ ++ tmpTClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); ++ tmpTClkRate &= MSAR_TCLCK_MASK; ++ ++ switch (tmpTClkRate) ++ { ++ case MSAR_TCLCK_166: ++ return MV_BOARD_TCLK_166MHZ; ++ break; ++ case MSAR_TCLCK_200: ++ return MV_BOARD_TCLK_200MHZ; ++ break; ++ } ++#else ++ return MV_BOARD_TCLK_200MHZ; ++#endif ++ } ++ ++ return MV_BOARD_TCLK_166MHZ; ++ ++} ++/******************************************************************************* ++* mvBoardSysClkGet - Get the board SysClk (CPU bus clock) ++* ++* DESCRIPTION: ++* This routine extract the CPU bus clock. ++* ++* INPUT: ++* countNum - Counter number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit clock cycles in Hertz. ++* ++*******************************************************************************/ ++static MV_U32 mvBoard6180SysClkGet(MV_VOID) ++{ ++ MV_U32 sysClkRate=0; ++ MV_CPU_ARM_CLK _cpu6180_ddr_l2_CLK[] = MV_CPU6180_DDR_L2_CLCK_TBL; ++ ++ sysClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); ++ sysClkRate = sysClkRate & MSAR_CPUCLCK_MASK_6180; ++ sysClkRate = sysClkRate >> MSAR_CPUCLCK_OFFS_6180; ++ ++ sysClkRate = _cpu6180_ddr_l2_CLK[sysClkRate].ddrClk; ++ ++ return sysClkRate; ++ ++} ++ ++MV_U32 mvBoardSysClkGet(MV_VOID) ++{ ++#ifdef SYSCLK_AUTO_DETECT ++ MV_U32 sysClkRate, tmp, pClkRate, indexDdrRtio; ++ MV_U32 cpuCLK[] = MV_CPU_CLCK_TBL; ++ MV_U32 ddrRtio[][2] = MV_DDR_CLCK_RTIO_TBL; ++ ++ if(mvCtrlModelGet() == MV_6180_DEV_ID) ++ return mvBoard6180SysClkGet(); ++ ++ tmp = MV_REG_READ(MPP_SAMPLE_AT_RESET); ++ pClkRate = MSAR_CPUCLCK_EXTRACT(tmp); ++ pClkRate = cpuCLK[pClkRate]; ++ ++ indexDdrRtio = tmp & MSAR_DDRCLCK_RTIO_MASK; ++ indexDdrRtio = indexDdrRtio >> MSAR_DDRCLCK_RTIO_OFFS; ++ if(ddrRtio[indexDdrRtio][0] != 0) ++ sysClkRate = ((pClkRate * ddrRtio[indexDdrRtio][1]) / ddrRtio[indexDdrRtio][0]); ++ else ++ sysClkRate = 0; ++ return sysClkRate; ++#else ++ return MV_BOARD_DEFAULT_SYSCLK; ++#endif ++} ++ ++ ++/******************************************************************************* ++* mvBoardPexBridgeIntPinGet - Get PEX to PCI bridge interrupt pin number ++* ++* DESCRIPTION: ++* Multi-ported PCI Express bridges that is implemented on the board ++* collapse interrupts across multiple conventional PCI/PCI-X buses. ++* A dual-headed PCI Express bridge would map (or "swizzle") the ++* interrupts per the following table (in accordance with the respective ++* logical PCI/PCI-X bridge's Device Number), collapse the INTA#-INTD# ++* signals from its two logical PCI/PCI-X bridges, collapse the ++* INTA#-INTD# signals from any internal sources, and convert the ++* signals to in-band PCI Express messages. 10 ++* This function returns the upstream interrupt as it was converted by ++* the bridge, according to board configuration and the following table: ++* PCI dev num ++* Interrupt pin 7, 8, 9 ++* A -> A D C ++* B -> B A D ++* C -> C B A ++* D -> D C B ++* ++* ++* INPUT: ++* devNum - PCI/PCIX device number. ++* intPin - PCI Int pin ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Int pin connected to the Interrupt controller ++* ++*******************************************************************************/ ++MV_U32 mvBoardPexBridgeIntPinGet(MV_U32 devNum, MV_U32 intPin) ++{ ++ MV_U32 realIntPin = ((intPin + (3 - (devNum % 4))) %4 ); ++ ++ if (realIntPin == 0) return 4; ++ else return realIntPin; ++ ++} ++ ++/******************************************************************************* ++* mvBoardDebugLedNumGet - Get number of debug Leds ++* ++* DESCRIPTION: ++* INPUT: ++* boardId ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_U32 mvBoardDebugLedNumGet(MV_U32 boardId) ++{ ++ return BOARD_INFO(boardId)->activeLedsNumber; ++} ++ ++/******************************************************************************* ++* mvBoardDebugLeg - Set the board debug Leds ++* ++* DESCRIPTION: turn on/off status leds. ++* Note: assume MPP leds are part of group 0 only. ++* ++* INPUT: ++* hexNum - Number to be displied in hex by Leds. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvBoardDebugLed(MV_U32 hexNum) ++{ ++ MV_U32 val = 0,totalMask, currentBitMask = 1,i; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ if (BOARD_INFO(boardId)->pLedGppPin == NULL) ++ return; ++ ++ totalMask = (1 << BOARD_INFO(boardId)->activeLedsNumber) -1; ++ hexNum &= totalMask; ++ totalMask = 0; ++ ++ for (i = 0 ; i < BOARD_INFO(boardId)->activeLedsNumber ; i++) ++ { ++ if (hexNum & currentBitMask) ++ { ++ val |= (1 << BOARD_INFO(boardId)->pLedGppPin[i]); ++ } ++ ++ totalMask |= (1 << BOARD_INFO(boardId)->pLedGppPin[i]); ++ ++ currentBitMask = (currentBitMask << 1); ++ } ++ ++ if (BOARD_INFO(boardId)->ledsPolarity) ++ { ++ mvGppValueSet(0, totalMask, val); ++ } ++ else ++ { ++ mvGppValueSet(0, totalMask, ~val); ++ } ++} ++ ++ ++/******************************************************************************* ++* mvBoarGpioPinGet - mvBoarGpioPinGet ++* ++* DESCRIPTION: ++* ++* INPUT: ++* class - MV_BOARD_GPP_CLASS enum. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* GPIO pin number. The function return -1 for bad parameters. ++* ++*******************************************************************************/ ++MV_32 mvBoarGpioPinNumGet(MV_BOARD_GPP_CLASS class, MV_U32 index) ++{ ++ MV_U32 boardId, i; ++ MV_U32 indexFound = 0; ++ ++ boardId = mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardRTCGpioPinGet:Board unknown.\n"); ++ return MV_ERROR; ++ ++ } ++ ++ for (i = 0; i < BOARD_INFO(boardId)->numBoardGppInfo; i++) ++ if (BOARD_INFO(boardId)->pBoardGppInfo[i].devClass == class) { ++ if (indexFound == index) ++ return (MV_U32)BOARD_INFO(boardId)->pBoardGppInfo[i].gppPinNum; ++ else ++ indexFound++; ++ ++ } ++ ++ return MV_ERROR; ++} ++ ++ ++/******************************************************************************* ++* mvBoardRTCGpioPinGet - mvBoardRTCGpioPinGet ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* GPIO pin number. The function return -1 for bad parameters. ++* ++*******************************************************************************/ ++MV_32 mvBoardRTCGpioPinGet(MV_VOID) ++{ ++ return mvBoarGpioPinNumGet(BOARD_GPP_RTC, 0); ++} ++ ++ ++/******************************************************************************* ++* mvBoardReset - mvBoardReset ++* ++* DESCRIPTION: ++* Reset the board ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None ++* ++*******************************************************************************/ ++MV_VOID mvBoardReset(MV_VOID) ++{ ++ MV_32 resetPin; ++ ++ /* Get gpp reset pin if define */ ++ resetPin = mvBoardResetGpioPinGet(); ++ if (resetPin != MV_ERROR) ++ { ++ MV_REG_BIT_RESET( GPP_DATA_OUT_REG(0) ,(1 << resetPin)); ++ MV_REG_BIT_RESET( GPP_DATA_OUT_EN_REG(0) ,(1 << resetPin)); ++ ++ } ++ else ++ { ++ /* No gpp reset pin was found, try to reset ussing ++ system reset out */ ++ MV_REG_BIT_SET( CPU_RSTOUTN_MASK_REG , BIT2); ++ MV_REG_BIT_SET( CPU_SYS_SOFT_RST_REG , BIT0); ++ } ++} ++ ++/******************************************************************************* ++* mvBoardResetGpioPinGet - mvBoardResetGpioPinGet ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* GPIO pin number. The function return -1 for bad parameters. ++* ++*******************************************************************************/ ++MV_32 mvBoardResetGpioPinGet(MV_VOID) ++{ ++ return mvBoarGpioPinNumGet(BOARD_GPP_RESET, 0); ++} ++/******************************************************************************* ++* mvBoardSDIOGpioPinGet - mvBoardSDIOGpioPinGet ++* ++* DESCRIPTION: ++* used for hotswap detection ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* GPIO pin number. The function return -1 for bad parameters. ++* ++*******************************************************************************/ ++MV_32 mvBoardSDIOGpioPinGet(MV_VOID) ++{ ++ return mvBoarGpioPinNumGet(BOARD_GPP_SDIO_DETECT, 0); ++} ++ ++/******************************************************************************* ++* mvBoardUSBVbusGpioPinGet - return Vbus input GPP ++* ++* DESCRIPTION: ++* ++* INPUT: ++* int devNo. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* GPIO pin number. The function return -1 for bad parameters. ++* ++*******************************************************************************/ ++MV_32 mvBoardUSBVbusGpioPinGet(MV_32 devId) ++{ ++ return mvBoarGpioPinNumGet(BOARD_GPP_USB_VBUS, devId); ++} ++ ++/******************************************************************************* ++* mvBoardUSBVbusEnGpioPinGet - return Vbus Enable output GPP ++* ++* DESCRIPTION: ++* ++* INPUT: ++* int devNo. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* GPIO pin number. The function return -1 for bad parameters. ++* ++*******************************************************************************/ ++MV_32 mvBoardUSBVbusEnGpioPinGet(MV_32 devId) ++{ ++ return mvBoarGpioPinNumGet(BOARD_GPP_USB_VBUS_EN, devId); ++} ++ ++ ++/******************************************************************************* ++* mvBoardGpioIntMaskGet - Get GPIO mask for interrupt pins ++* ++* DESCRIPTION: ++* This function returns a 32-bit mask of GPP pins that connected to ++* interrupt generating sources on board. ++* For example if UART channel A is hardwired to GPP pin 8 and ++* UART channel B is hardwired to GPP pin 4 the fuinction will return ++* the value 0x000000110 ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* See description. The function return -1 if board is not identified. ++* ++*******************************************************************************/ ++MV_32 mvBoardGpioIntMaskLowGet(MV_VOID) ++{ ++ MV_U32 boardId; ++ ++ boardId = mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardGpioIntMaskGet:Board unknown.\n"); ++ return MV_ERROR; ++ ++ } ++ ++ return BOARD_INFO(boardId)->intsGppMaskLow; ++} ++MV_32 mvBoardGpioIntMaskHighGet(MV_VOID) ++{ ++ MV_U32 boardId; ++ ++ boardId = mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardGpioIntMaskGet:Board unknown.\n"); ++ return MV_ERROR; ++ ++ } ++ ++ return BOARD_INFO(boardId)->intsGppMaskHigh; ++} ++ ++ ++/******************************************************************************* ++* mvBoardMppGet - Get board dependent MPP register value ++* ++* DESCRIPTION: ++* MPP settings are derived from board design. ++* MPP group consist of 8 MPPs. An MPP group represent MPP ++* control register. ++* This function retrieves board dependend MPP register value. ++* ++* INPUT: ++* mppGroupNum - MPP group number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit value describing MPP control register value. ++* ++*******************************************************************************/ ++MV_32 mvBoardMppGet(MV_U32 mppGroupNum) ++{ ++ MV_U32 boardId; ++ ++ boardId = mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardMppGet:Board unknown.\n"); ++ return MV_ERROR; ++ ++ } ++ ++ return BOARD_INFO(boardId)->pBoardMppConfigValue[0].mppGroup[mppGroupNum]; ++} ++ ++ ++/******************************************************************************* ++* mvBoardMppGroupId - If MPP group type is AUTO then identify it using twsi ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_VOID mvBoardMppGroupIdUpdate(MV_VOID) ++{ ++ ++ MV_BOARD_MPP_GROUP_CLASS devClass; ++ MV_BOARD_MODULE_ID_CLASS devClassId; ++ MV_BOARD_MPP_TYPE_CLASS mppGroupType; ++ MV_U32 devId; ++ MV_U32 maxMppGrp = 1; ++ ++ devId = mvCtrlModelGet(); ++ ++ switch(devId){ ++ case MV_6281_DEV_ID: ++ maxMppGrp = MV_6281_MPP_MAX_MODULE; ++ break; ++ case MV_6192_DEV_ID: ++ maxMppGrp = MV_6192_MPP_MAX_MODULE; ++ break; ++ case MV_6190_DEV_ID: ++ maxMppGrp = MV_6190_MPP_MAX_MODULE; ++ break; ++ case MV_6180_DEV_ID: ++ maxMppGrp = MV_6180_MPP_MAX_MODULE; ++ break; ++ } ++ ++ for (devClass = 0; devClass < maxMppGrp; devClass++) ++ { ++ /* If MPP group can be defined by the module connected to it */ ++ if (mvBoardMppGroupTypeGet(devClass) == MV_BOARD_AUTO) ++ { ++ /* Get MPP module ID */ ++ devClassId = mvBoarModuleTypeGet(devClass); ++ if (MV_ERROR != devClassId) ++ { ++ switch(devClassId) ++ { ++ case MV_BOARD_MODULE_TDM_ID: ++ case MV_BOARD_MODULE_TDM_5CHAN_ID: ++ mppGroupType = MV_BOARD_TDM; ++ break; ++ case MV_BOARD_MODULE_AUDIO_ID: ++ mppGroupType = MV_BOARD_AUDIO; ++ break; ++ case MV_BOARD_MODULE_RGMII_ID: ++ mppGroupType = MV_BOARD_RGMII; ++ break; ++ case MV_BOARD_MODULE_GMII_ID: ++ mppGroupType = MV_BOARD_GMII; ++ break; ++ case MV_BOARD_MODULE_TS_ID: ++ mppGroupType = MV_BOARD_TS; ++ break; ++ case MV_BOARD_MODULE_MII_ID: ++ mppGroupType = MV_BOARD_MII; ++ break; ++ default: ++ mppGroupType = MV_BOARD_OTHER; ++ break; ++ } ++ } ++ else ++ /* The module bay is empty */ ++ mppGroupType = MV_BOARD_OTHER; ++ ++ /* Update MPP group type */ ++ mvBoardMppGroupTypeSet(devClass, mppGroupType); ++ } ++ ++ /* Update MPP output voltage for RGMII 1.8V. Set port to GMII for GMII module */ ++ if ((mvBoardMppGroupTypeGet(devClass) == MV_BOARD_RGMII)) ++ MV_REG_BIT_SET(MPP_OUTPUT_DRIVE_REG,MPP_1_8_RGMII1_OUTPUT_DRIVE | MPP_1_8_RGMII0_OUTPUT_DRIVE); ++ else ++ { ++ if ((mvBoardMppGroupTypeGet(devClass) == MV_BOARD_GMII)) ++ { ++ MV_REG_BIT_RESET(MPP_OUTPUT_DRIVE_REG, BIT7 | BIT15); ++ MV_REG_BIT_RESET(ETH_PORT_SERIAL_CTRL_1_REG(0),BIT3); ++ MV_REG_BIT_RESET(ETH_PORT_SERIAL_CTRL_1_REG(1),BIT3); ++ } ++ else if ((mvBoardMppGroupTypeGet(devClass) == MV_BOARD_MII)) ++ { ++ /* Assumption that the MDC & MDIO should be 3.3V */ ++ MV_REG_BIT_RESET(MPP_OUTPUT_DRIVE_REG, BIT7 | BIT15); ++ /* Assumption that only ETH1 can be MII when using modules on DB */ ++ MV_REG_BIT_RESET(ETH_PORT_SERIAL_CTRL_1_REG(1),BIT3); ++ } ++ } ++ } ++} ++ ++/******************************************************************************* ++* mvBoardMppGroupTypeGet ++* ++* DESCRIPTION: ++* ++* INPUT: ++* mppGroupClass - MPP group number 0 for MPP[35:20] or 1 for MPP[49:36]. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_BOARD_MPP_TYPE_CLASS mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass) ++{ ++ MV_U32 boardId; ++ ++ boardId = mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardMppGet:Board unknown.\n"); ++ return MV_ERROR; ++ ++ } ++ ++ if (mppGroupClass == MV_BOARD_MPP_GROUP_1) ++ return BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup1; ++ else ++ return BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup2; ++} ++ ++/******************************************************************************* ++* mvBoardMppGroupTypeSet ++* ++* DESCRIPTION: ++* ++* INPUT: ++* mppGroupClass - MPP group number 0 for MPP[35:20] or 1 for MPP[49:36]. ++* mppGroupType - MPP group type for MPP[35:20] or for MPP[49:36]. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_VOID mvBoardMppGroupTypeSet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass, ++ MV_BOARD_MPP_TYPE_CLASS mppGroupType) ++{ ++ MV_U32 boardId; ++ ++ boardId = mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardMppGet:Board unknown.\n"); ++ } ++ ++ if (mppGroupClass == MV_BOARD_MPP_GROUP_1) ++ BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup1 = mppGroupType; ++ else ++ BOARD_INFO(boardId)->pBoardMppTypeValue[0].boardMppGroup2 = mppGroupType; ++ ++} ++ ++/******************************************************************************* ++* mvBoardMppMuxSet - Update MPP mux ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_VOID mvBoardMppMuxSet(MV_VOID) ++{ ++ ++ MV_BOARD_MPP_GROUP_CLASS devClass; ++ MV_BOARD_MPP_TYPE_CLASS mppGroupType; ++ MV_U32 devId; ++ MV_U8 muxVal = 0xf; ++ MV_U32 maxMppGrp = 1; ++ MV_TWSI_SLAVE twsiSlave; ++ MV_TWSI_ADDR slave; ++ ++ devId = mvCtrlModelGet(); ++ ++ switch(devId){ ++ case MV_6281_DEV_ID: ++ maxMppGrp = MV_6281_MPP_MAX_MODULE; ++ break; ++ case MV_6192_DEV_ID: ++ maxMppGrp = MV_6192_MPP_MAX_MODULE; ++ break; ++ case MV_6190_DEV_ID: ++ maxMppGrp = MV_6190_MPP_MAX_MODULE; ++ break; ++ case MV_6180_DEV_ID: ++ maxMppGrp = MV_6180_MPP_MAX_MODULE; ++ break; ++ } ++ ++ for (devClass = 0; devClass < maxMppGrp; devClass++) ++ { ++ mppGroupType = mvBoardMppGroupTypeGet(devClass); ++ ++ switch(mppGroupType) ++ { ++ case MV_BOARD_TDM: ++ muxVal &= ~(devClass ? (0x2 << (devClass * 2)):0x0); ++ break; ++ case MV_BOARD_AUDIO: ++ muxVal &= ~(devClass ? 0x7 : 0x0); /*old Z0 value 0xd:0x0*/ ++ break; ++ case MV_BOARD_TS: ++ muxVal &= ~(devClass ? (0x2 << (devClass * 2)):0x0); ++ break; ++ default: ++ muxVal |= (devClass ? 0xf : 0); ++ break; ++ } ++ } ++ ++ /* TWSI init */ ++ slave.type = ADDR7_BIT; ++ slave.address = 0; ++ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); ++ ++ /* Read MPP module ID */ ++ DB(mvOsPrintf("Board: twsi exp set\n")); ++ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(MV_BOARD_MUX_I2C_ADDR_ENTRY); ++ twsiSlave.slaveAddr.type = mvBoardTwsiExpAddrTypeGet(MV_BOARD_MUX_I2C_ADDR_ENTRY); ++ twsiSlave.validOffset = MV_TRUE; ++ /* Offset is the first command after the address which indicate the register number to be read ++ in next operation */ ++ twsiSlave.offset = 2; ++ twsiSlave.moreThen256 = MV_FALSE; ++ ++ ++ ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) ++ { ++ DB(mvOsPrintf("Board: twsi exp out val fail\n")); ++ return; ++ } ++ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); ++ ++ /* Change twsi exp to output */ ++ twsiSlave.offset = 6; ++ muxVal = 0; ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) ++ { ++ DB(mvOsPrintf("Board: twsi exp change to out fail\n")); ++ return; ++ } ++ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); ++ ++} ++ ++/******************************************************************************* ++* mvBoardTdmMppSet - set MPPs in TDM module ++* ++* DESCRIPTION: ++* ++* INPUT: type of second telephony device ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_VOID mvBoardTdmMppSet(MV_32 chType) ++{ ++ ++ MV_BOARD_MPP_GROUP_CLASS devClass; ++ MV_BOARD_MPP_TYPE_CLASS mppGroupType; ++ MV_U32 devId; ++ MV_U8 muxVal = 1; ++ MV_U8 muxValMask = 1; ++ MV_U8 twsiVal; ++ MV_U32 maxMppGrp = 1; ++ MV_TWSI_SLAVE twsiSlave; ++ MV_TWSI_ADDR slave; ++ ++ devId = mvCtrlModelGet(); ++ ++ switch(devId){ ++ case MV_6281_DEV_ID: ++ maxMppGrp = MV_6281_MPP_MAX_MODULE; ++ break; ++ case MV_6192_DEV_ID: ++ maxMppGrp = MV_6192_MPP_MAX_MODULE; ++ break; ++ case MV_6190_DEV_ID: ++ maxMppGrp = MV_6190_MPP_MAX_MODULE; ++ break; ++ case MV_6180_DEV_ID: ++ maxMppGrp = MV_6180_MPP_MAX_MODULE; ++ break; ++ } ++ ++ for (devClass = 0; devClass < maxMppGrp; devClass++) ++ { ++ mppGroupType = mvBoardMppGroupTypeGet(devClass); ++ if(mppGroupType == MV_BOARD_TDM) ++ break; ++ } ++ ++ if(devClass == maxMppGrp) ++ return; /* TDM module not found */ ++ ++ /* TWSI init */ ++ slave.type = ADDR7_BIT; ++ slave.address = 0; ++ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); ++ ++ /* Read MPP module ID */ ++ DB(mvOsPrintf("Board: twsi exp set\n")); ++ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(devClass); ++ twsiSlave.slaveAddr.type = ADDR7_BIT; ++ twsiSlave.validOffset = MV_TRUE; ++ /* Offset is the first command after the address which indicate the register number to be read ++ in next operation */ ++ twsiSlave.offset = 3; ++ twsiSlave.moreThen256 = MV_FALSE; ++ ++ if(mvBoardIdGet() == RD_88F6281A_ID) ++ { ++ muxVal = 0xc; ++ muxValMask = 0xf3; ++ } ++ ++ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); ++ muxVal = (twsiVal & muxValMask) | muxVal; ++ ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) ++ { ++ mvOsPrintf("Board: twsi exp out val fail\n"); ++ return; ++ } ++ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); ++ ++ /* Change twsi exp to output */ ++ twsiSlave.offset = 7; ++ muxVal = 0xfe; ++ if(mvBoardIdGet() == RD_88F6281A_ID) ++ muxVal = 0xf3; ++ ++ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); ++ muxVal = (twsiVal & muxVal); ++ ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) ++ { ++ mvOsPrintf("Board: twsi exp change to out fail\n"); ++ return; ++ } ++ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); ++ /* reset the line to 0 */ ++ twsiSlave.offset = 3; ++ muxVal = 0; ++ muxValMask = 1; ++ ++ if(mvBoardIdGet() == RD_88F6281A_ID) { ++ muxVal = 0x0; ++ muxValMask = 0xf3; ++ } ++ ++ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); ++ muxVal = (twsiVal & muxValMask) | muxVal; ++ ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) ++ { ++ mvOsPrintf("Board: twsi exp out val fail\n"); ++ return; ++ } ++ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); ++ ++ mvOsDelay(20); ++ ++ /* set the line to 1 */ ++ twsiSlave.offset = 3; ++ muxVal = 1; ++ muxValMask = 1; ++ ++ if(mvBoardIdGet() == RD_88F6281A_ID) ++ { ++ muxVal = 0xc; ++ muxValMask = 0xf3; ++ if(chType) /* FXS - issue reset properly */ ++ { ++ MV_REG_BIT_SET(GPP_DATA_OUT_REG(1), MV_GPP12); ++ mvOsDelay(50); ++ MV_REG_BIT_RESET(GPP_DATA_OUT_REG(1), MV_GPP12); ++ } ++ else /* FXO - issue reset via TDM_CODEC_RST*/ ++ { ++ /* change MPP44 type to TDM_CODEC_RST(0x2) */ ++ MV_REG_WRITE(MPP_CONTROL_REG5, ((MV_REG_READ(MPP_CONTROL_REG5) & 0xFFF0FFFF) | BIT17)); ++ } ++ } ++ ++ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); ++ muxVal = (twsiVal & muxValMask) | muxVal; ++ ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) ++ { ++ mvOsPrintf("Board: twsi exp out val fail\n"); ++ return; ++ } ++ ++ /* TBD - 5 channels */ ++#if defined(MV_TDM_5CHANNELS) ++ /* change MPP38 type to GPIO(0x0) & polarity for TDM_STROBE */ ++ MV_REG_WRITE(MPP_CONTROL_REG4, (MV_REG_READ(MPP_CONTROL_REG4) & 0xF0FFFFFF)); ++ mvGppPolaritySet(1, MV_GPP6, 0); ++ ++ twsiSlave.offset = 6; ++ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(2); ++ ++ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); ++ muxVal = (twsiVal & ~BIT2); ++ ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) ++ { ++ mvOsPrintf("Board: twsi exp change to out fail\n"); ++ return; ++ } ++ ++ ++ twsiSlave.offset = 2; ++ ++ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); ++ muxVal = (twsiVal & ~BIT2); ++ ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &muxVal, 1) ) ++ { ++ mvOsPrintf("Board: twsi exp change to out fail\n"); ++ return; ++ } ++#endif ++ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); ++ ++ ++} ++/******************************************************************************* ++* mvBoardVoiceConnModeGet - return SLIC/DAA connection & interrupt modes ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++*******************************************************************************/ ++ ++MV_VOID mvBoardVoiceConnModeGet(MV_32* connMode, MV_32* irqMode) ++{ ++ switch(mvBoardIdGet()) ++ { ++ case RD_88F6281A_ID: ++ *connMode = DAISY_CHAIN_MODE; ++ *irqMode = INTERRUPT_TO_TDM; ++ break; ++ case DB_88F6281A_BP_ID: ++ *connMode = DUAL_CHIP_SELECT_MODE; ++ *irqMode = INTERRUPT_TO_TDM; ++ break; ++ case RD_88F6192A_ID: ++ *connMode = DUAL_CHIP_SELECT_MODE; ++ *irqMode = INTERRUPT_TO_TDM; ++ break; ++ case DB_88F6192A_BP_ID: ++ *connMode = DUAL_CHIP_SELECT_MODE; ++ *irqMode = INTERRUPT_TO_TDM; ++ break; ++ default: ++ *connMode = *irqMode = -1; ++ mvOsPrintf("mvBoardVoiceAssembleModeGet: TDM not supported(boardId=0x%x)\n",mvBoardIdGet()); ++ } ++ return; ++ ++} ++ ++/******************************************************************************* ++* mvBoardMppModuleTypePrint - print module detect ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_VOID mvBoardMppModuleTypePrint(MV_VOID) ++{ ++ ++ MV_BOARD_MPP_GROUP_CLASS devClass; ++ MV_BOARD_MPP_TYPE_CLASS mppGroupType; ++ MV_U32 devId; ++ MV_U32 maxMppGrp = 1; ++ ++ devId = mvCtrlModelGet(); ++ ++ switch(devId){ ++ case MV_6281_DEV_ID: ++ maxMppGrp = MV_6281_MPP_MAX_MODULE; ++ break; ++ case MV_6192_DEV_ID: ++ maxMppGrp = MV_6192_MPP_MAX_MODULE; ++ break; ++ case MV_6190_DEV_ID: ++ maxMppGrp = MV_6190_MPP_MAX_MODULE; ++ break; ++ case MV_6180_DEV_ID: ++ maxMppGrp = MV_6180_MPP_MAX_MODULE; ++ break; ++ } ++ ++ for (devClass = 0; devClass < maxMppGrp; devClass++) ++ { ++ mppGroupType = mvBoardMppGroupTypeGet(devClass); ++ ++ switch(mppGroupType) ++ { ++ case MV_BOARD_TDM: ++ if(devId != MV_6190_DEV_ID) ++ mvOsPrintf("Module %d is TDM\n", devClass); ++ break; ++ case MV_BOARD_AUDIO: ++ if(devId != MV_6190_DEV_ID) ++ mvOsPrintf("Module %d is AUDIO\n", devClass); ++ break; ++ case MV_BOARD_RGMII: ++ if(devId != MV_6190_DEV_ID) ++ mvOsPrintf("Module %d is RGMII\n", devClass); ++ break; ++ case MV_BOARD_GMII: ++ if(devId != MV_6190_DEV_ID) ++ mvOsPrintf("Module %d is GMII\n", devClass); ++ break; ++ case MV_BOARD_TS: ++ if(devId != MV_6190_DEV_ID) ++ mvOsPrintf("Module %d is TS\n", devClass); ++ break; ++ default: ++ break; ++ } ++ } ++} ++ ++/* Board devices API managments */ ++ ++/******************************************************************************* ++* mvBoardGetDeviceNumber - Get number of device of some type on the board ++* ++* DESCRIPTION: ++* ++* INPUT: ++* devType - The device type ( Flash,RTC , etc .. ) ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* If the device is found on the board the then the functions returns the ++* number of those devices else the function returns 0 ++* ++* ++*******************************************************************************/ ++MV_32 mvBoardGetDevicesNumber(MV_BOARD_DEV_CLASS devClass) ++{ ++ MV_U32 foundIndex=0,devNum; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("mvBoardGetDeviceNumber:Board unknown.\n"); ++ return 0xFFFFFFFF; ++ ++ } ++ ++ for (devNum = START_DEV_CS; devNum < BOARD_INFO(boardId)->numBoardDeviceIf; devNum++) ++ { ++ if (BOARD_INFO(boardId)->pDevCsInfo[devNum].devClass == devClass) ++ { ++ foundIndex++; ++ } ++ } ++ ++ return foundIndex; ++ ++} ++ ++/******************************************************************************* ++* mvBoardGetDeviceBaseAddr - Get base address of a device existing on the board ++* ++* DESCRIPTION: ++* ++* INPUT: ++* devIndex - The device sequential number on the board ++* devType - The device type ( Flash,RTC , etc .. ) ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* If the device is found on the board the then the functions returns the ++* Base address else the function returns 0xffffffff ++* ++* ++*******************************************************************************/ ++MV_32 mvBoardGetDeviceBaseAddr(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) ++{ ++ MV_DEV_CS_INFO* devEntry; ++ devEntry = boardGetDevEntry(devNum,devClass); ++ if (devEntry != NULL) ++ { ++ return mvCpuIfTargetWinBaseLowGet(DEV_TO_TARGET(devEntry->deviceCS)); ++ ++ } ++ ++ return 0xFFFFFFFF; ++} ++ ++/******************************************************************************* ++* mvBoardGetDeviceBusWidth - Get Bus width of a device existing on the board ++* ++* DESCRIPTION: ++* ++* INPUT: ++* devIndex - The device sequential number on the board ++* devType - The device type ( Flash,RTC , etc .. ) ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* If the device is found on the board the then the functions returns the ++* Bus width else the function returns 0xffffffff ++* ++* ++*******************************************************************************/ ++MV_32 mvBoardGetDeviceBusWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) ++{ ++ MV_DEV_CS_INFO* devEntry; ++ ++ devEntry = boardGetDevEntry(devNum,devClass); ++ if (devEntry != NULL) ++ { ++ return 8; ++ } ++ ++ return 0xFFFFFFFF; ++ ++} ++ ++/******************************************************************************* ++* mvBoardGetDeviceWidth - Get dev width of a device existing on the board ++* ++* DESCRIPTION: ++* ++* INPUT: ++* devIndex - The device sequential number on the board ++* devType - The device type ( Flash,RTC , etc .. ) ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* If the device is found on the board the then the functions returns the ++* dev width else the function returns 0xffffffff ++* ++* ++*******************************************************************************/ ++MV_32 mvBoardGetDeviceWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) ++{ ++ MV_DEV_CS_INFO* devEntry; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("Board unknown.\n"); ++ return 0xFFFFFFFF; ++ } ++ ++ devEntry = boardGetDevEntry(devNum,devClass); ++ if (devEntry != NULL) ++ return devEntry->devWidth; ++ ++ return MV_ERROR; ++ ++} ++ ++/******************************************************************************* ++* mvBoardGetDeviceWinSize - Get the window size of a device existing on the board ++* ++* DESCRIPTION: ++* ++* INPUT: ++* devIndex - The device sequential number on the board ++* devType - The device type ( Flash,RTC , etc .. ) ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* If the device is found on the board the then the functions returns the ++* window size else the function returns 0xffffffff ++* ++* ++*******************************************************************************/ ++MV_32 mvBoardGetDeviceWinSize(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) ++{ ++ MV_DEV_CS_INFO* devEntry; ++ MV_U32 boardId = mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("Board unknown.\n"); ++ return 0xFFFFFFFF; ++ } ++ ++ devEntry = boardGetDevEntry(devNum,devClass); ++ if (devEntry != NULL) ++ { ++ return mvCpuIfTargetWinSizeGet(DEV_TO_TARGET(devEntry->deviceCS)); ++ } ++ ++ return 0xFFFFFFFF; ++} ++ ++ ++/******************************************************************************* ++* boardGetDevEntry - returns the entry pointer of a device on the board ++* ++* DESCRIPTION: ++* ++* INPUT: ++* devIndex - The device sequential number on the board ++* devType - The device type ( Flash,RTC , etc .. ) ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* If the device is found on the board the then the functions returns the ++* dev number else the function returns 0x0 ++* ++* ++*******************************************************************************/ ++static MV_DEV_CS_INFO* boardGetDevEntry(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) ++{ ++ MV_U32 foundIndex=0,devIndex; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("boardGetDevEntry: Board unknown.\n"); ++ return NULL; ++ ++ } ++ ++ for (devIndex = START_DEV_CS; devIndex < BOARD_INFO(boardId)->numBoardDeviceIf; devIndex++) ++ { ++ /* TBR */ ++ /*if (BOARD_INFO(boardId)->pDevCsInfo[devIndex].deviceCS == MV_BOOTDEVICE_INDEX) ++ continue;*/ ++ ++ if (BOARD_INFO(boardId)->pDevCsInfo[devIndex].devClass == devClass) ++ { ++ if (foundIndex == devNum) ++ { ++ return &(BOARD_INFO(boardId)->pDevCsInfo[devIndex]); ++ } ++ foundIndex++; ++ } ++ } ++ ++ /* device not found */ ++ return NULL; ++} ++ ++/* Get device CS number */ ++ ++MV_U32 boardGetDevCSNum(MV_32 devNum, MV_BOARD_DEV_CLASS devClass) ++{ ++ MV_DEV_CS_INFO* devEntry; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ if (!((boardId >= BOARD_ID_BASE)&&(boardId < MV_MAX_BOARD_ID))) ++ { ++ mvOsPrintf("Board unknown.\n"); ++ return 0xFFFFFFFF; ++ ++ } ++ ++ ++ devEntry = boardGetDevEntry(devNum,devClass); ++ if (devEntry != NULL) ++ return devEntry->deviceCS; ++ ++ return 0xFFFFFFFF; ++ ++} ++ ++/******************************************************************************* ++* mvBoardRtcTwsiAddrTypeGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++* ++*******************************************************************************/ ++MV_U8 mvBoardRtcTwsiAddrTypeGet() ++{ ++ int i; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) ++ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_RTC) ++ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; ++ return (MV_ERROR); ++} ++ ++/******************************************************************************* ++* mvBoardRtcTwsiAddrGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++* ++*******************************************************************************/ ++MV_U8 mvBoardRtcTwsiAddrGet() ++{ ++ int i; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) ++ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_RTC) ++ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; ++ return (0xFF); ++} ++ ++/******************************************************************************* ++* mvBoardA2DTwsiAddrTypeGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++* ++*******************************************************************************/ ++MV_U8 mvBoardA2DTwsiAddrTypeGet() ++{ ++ int i; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) ++ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_AUDIO_DEC) ++ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; ++ return (MV_ERROR); ++} ++ ++/******************************************************************************* ++* mvBoardA2DTwsiAddrGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++* ++*******************************************************************************/ ++MV_U8 mvBoardA2DTwsiAddrGet() ++{ ++ int i; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) ++ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_TWSI_AUDIO_DEC) ++ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; ++ return (0xFF); ++} ++ ++/******************************************************************************* ++* mvBoardTwsiExpAddrTypeGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++* ++*******************************************************************************/ ++MV_U8 mvBoardTwsiExpAddrTypeGet(MV_U32 index) ++{ ++ int i; ++ MV_U32 indexFound = 0; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) ++ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_EXP) ++ { ++ if (indexFound == index) ++ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; ++ else ++ indexFound++; ++ } ++ ++ return (MV_ERROR); ++} ++ ++/******************************************************************************* ++* mvBoardTwsiExpAddrGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++* ++*******************************************************************************/ ++MV_U8 mvBoardTwsiExpAddrGet(MV_U32 index) ++{ ++ int i; ++ MV_U32 indexFound = 0; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) ++ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_EXP) ++ { ++ if (indexFound == index) ++ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; ++ else ++ indexFound++; ++ } ++ ++ return (0xFF); ++} ++ ++ ++/******************************************************************************* ++* mvBoardTwsiSatRAddrTypeGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++* ++*******************************************************************************/ ++MV_U8 mvBoardTwsiSatRAddrTypeGet(MV_U32 index) ++{ ++ int i; ++ MV_U32 indexFound = 0; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) ++ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_SATR) ++ { ++ if (indexFound == index) ++ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddrType; ++ else ++ indexFound++; ++ } ++ ++ return (MV_ERROR); ++} ++ ++/******************************************************************************* ++* mvBoardTwsiSatRAddrGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++* ++*******************************************************************************/ ++MV_U8 mvBoardTwsiSatRAddrGet(MV_U32 index) ++{ ++ int i; ++ MV_U32 indexFound = 0; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ for (i = 0; i < BOARD_INFO(boardId)->numBoardTwsiDev; i++) ++ if (BOARD_INFO(boardId)->pBoardTwsiDev[i].devClass == BOARD_DEV_TWSI_SATR) ++ { ++ if (indexFound == index) ++ return BOARD_INFO(boardId)->pBoardTwsiDev[i].twsiDevAddr; ++ else ++ indexFound++; ++ } ++ ++ return (0xFF); ++} ++ ++/******************************************************************************* ++* mvBoardNandWidthGet - ++* ++* DESCRIPTION: Get the width of the first NAND device in byte. ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: 1, 2, 4 or MV_ERROR ++* ++* ++*******************************************************************************/ ++/* */ ++MV_32 mvBoardNandWidthGet(void) ++{ ++ MV_U32 devNum; ++ MV_U32 devWidth; ++ MV_U32 boardId= mvBoardIdGet(); ++ ++ for (devNum = START_DEV_CS; devNum < BOARD_INFO(boardId)->numBoardDeviceIf; devNum++) ++ { ++ devWidth = mvBoardGetDeviceWidth(devNum, BOARD_DEV_NAND_FLASH); ++ if (devWidth != MV_ERROR) ++ return (devWidth / 8); ++ } ++ ++ /* NAND wasn't found */ ++ return MV_ERROR; ++} ++ ++MV_U32 gBoardId = -1; ++ ++/******************************************************************************* ++* mvBoardIdGet - Get Board model ++* ++* DESCRIPTION: ++* This function returns board ID. ++* Board ID is 32bit word constructed of board model (16bit) and ++* board revision (16bit) in the following way: 0xMMMMRRRR. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit board ID number, '-1' if board is undefined. ++* ++*******************************************************************************/ ++MV_U32 mvBoardIdGet(MV_VOID) ++{ ++ MV_U32 tmpBoardId = -1; ++ ++ if(gBoardId == -1) ++ { ++ #if defined(DB_88F6281A) ++ tmpBoardId = DB_88F6281A_BP_ID; ++ #elif defined(RD_88F6281A) ++ tmpBoardId = RD_88F6281A_ID; ++ #elif defined(DB_88F6192A) ++ tmpBoardId = DB_88F6192A_BP_ID; ++ #elif defined(DB_88F6190A) ++ tmpBoardId = DB_88F6190A_BP_ID; ++ #elif defined(RD_88F6192A) ++ tmpBoardId = RD_88F6192A_ID; ++ #elif defined(RD_88F6190A) ++ tmpBoardId = RD_88F6190A_ID; ++ #elif defined(DB_88F6180A) ++ tmpBoardId = DB_88F6180A_BP_ID; ++ #elif defined(RD_88F6281A_PCAC) ++ tmpBoardId = RD_88F6281A_PCAC_ID; ++ #elif defined(RD_88F6281A_SHEEVA_PLUG) ++ tmpBoardId = SHEEVA_PLUG_ID; ++ #elif defined(DB_CUSTOMER) ++ tmpBoardId = DB_CUSTOMER_ID; ++ #endif ++ gBoardId = tmpBoardId; ++ } ++ ++ return gBoardId; ++} ++ ++ ++/******************************************************************************* ++* mvBoarModuleTypeGet - mvBoarModuleTypeGet ++* ++* DESCRIPTION: ++* ++* INPUT: ++* group num - MV_BOARD_MPP_GROUP_CLASS enum ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* module num - MV_BOARD_MODULE_CLASS enum ++* ++*******************************************************************************/ ++MV_BOARD_MODULE_ID_CLASS mvBoarModuleTypeGet(MV_BOARD_MPP_GROUP_CLASS devClass) ++{ ++ MV_TWSI_SLAVE twsiSlave; ++ MV_TWSI_ADDR slave; ++ MV_U8 data; ++ ++ /* TWSI init */ ++ slave.type = ADDR7_BIT; ++ slave.address = 0; ++ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); ++ ++ /* Read MPP module ID */ ++ DB(mvOsPrintf("Board: Read MPP module ID\n")); ++ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(devClass); ++ twsiSlave.slaveAddr.type = mvBoardTwsiExpAddrTypeGet(devClass); ++ twsiSlave.validOffset = MV_TRUE; ++ /* Offset is the first command after the address which indicate the register number to be read ++ in next operation */ ++ twsiSlave.offset = 0; ++ twsiSlave.moreThen256 = MV_FALSE; ++ ++ ++ ++ if( MV_OK != mvTwsiRead (0, &twsiSlave, &data, 1) ) ++ { ++ DB(mvOsPrintf("Board: Read MPP module ID fail\n")); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Board: Read MPP module ID succeded\n")); ++ ++ return data; ++} ++ ++/******************************************************************************* ++* mvBoarTwsiSatRGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* device num - one of three devices ++* reg num - 0 or 1 ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* reg value ++* ++*******************************************************************************/ ++MV_U8 mvBoarTwsiSatRGet(MV_U8 devNum, MV_U8 regNum) ++{ ++ MV_TWSI_SLAVE twsiSlave; ++ MV_TWSI_ADDR slave; ++ MV_U8 data; ++ ++ /* TWSI init */ ++ slave.type = ADDR7_BIT; ++ slave.address = 0; ++ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); ++ ++ /* Read MPP module ID */ ++ DB(mvOsPrintf("Board: Read S@R device read\n")); ++ twsiSlave.slaveAddr.address = mvBoardTwsiSatRAddrGet(devNum); ++ twsiSlave.slaveAddr.type = mvBoardTwsiSatRAddrTypeGet(devNum); ++ twsiSlave.validOffset = MV_TRUE; ++ /* Use offset as command */ ++ twsiSlave.offset = regNum; ++ twsiSlave.moreThen256 = MV_FALSE; ++ ++ if( MV_OK != mvTwsiRead (0, &twsiSlave, &data, 1) ) ++ { ++ DB(mvOsPrintf("Board: Read S@R fail\n")); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Board: Read S@R succeded\n")); ++ ++ return data; ++} ++ ++/******************************************************************************* ++* mvBoarTwsiSatRSet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* devNum - one of three devices ++* regNum - 0 or 1 ++* regVal - value ++* ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* reg value ++* ++*******************************************************************************/ ++MV_STATUS mvBoarTwsiSatRSet(MV_U8 devNum, MV_U8 regNum, MV_U8 regVal) ++{ ++ MV_TWSI_SLAVE twsiSlave; ++ MV_TWSI_ADDR slave; ++ ++ /* TWSI init */ ++ slave.type = ADDR7_BIT; ++ slave.address = 0; ++ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); ++ ++ /* Read MPP module ID */ ++ twsiSlave.slaveAddr.address = mvBoardTwsiSatRAddrGet(devNum); ++ twsiSlave.slaveAddr.type = mvBoardTwsiSatRAddrTypeGet(devNum); ++ twsiSlave.validOffset = MV_TRUE; ++ DB(mvOsPrintf("Board: Write S@R device addr %x, type %x, data %x\n", twsiSlave.slaveAddr.address,\ ++ twsiSlave.slaveAddr.type, regVal)); ++ /* Use offset as command */ ++ twsiSlave.offset = regNum; ++ twsiSlave.moreThen256 = MV_FALSE; ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, ®Val, 1) ) ++ { ++ DB(mvOsPrintf("Board: Write S@R fail\n")); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Board: Write S@R succeded\n")); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvBoardSlicGpioPinGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++* ++*******************************************************************************/ ++MV_32 mvBoardSlicGpioPinGet(MV_U32 slicNum) ++{ ++ MV_U32 boardId; ++ boardId = mvBoardIdGet(); ++ ++ switch (boardId) ++ { ++ case DB_88F6281A_BP_ID: ++ case RD_88F6281A_ID: ++ default: ++ return MV_ERROR; ++ break; ++ ++ } ++} ++ ++/******************************************************************************* ++* mvBoardFanPowerControl - Turn on/off the fan power control on the RD-6281A ++* ++* DESCRIPTION: ++* ++* INPUT: ++* mode - MV_TRUE = on ; MV_FALSE = off ++* ++* OUTPUT: ++* MV_STATUS - MV_OK , MV_ERROR. ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_STATUS mvBoardFanPowerControl(MV_BOOL mode) ++{ ++ ++ MV_U8 val = 1, twsiVal; ++ MV_TWSI_SLAVE twsiSlave; ++ MV_TWSI_ADDR slave; ++ ++ if(mvBoardIdGet() != RD_88F6281A_ID) ++ return MV_ERROR; ++ ++ /* TWSI init */ ++ slave.type = ADDR7_BIT; ++ slave.address = 0; ++ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); ++ ++ /* Read MPP module ID */ ++ DB(mvOsPrintf("Board: twsi exp set\n")); ++ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(1); ++ twsiSlave.slaveAddr.type = ADDR7_BIT; ++ twsiSlave.validOffset = MV_TRUE; ++ /* Offset is the first command after the address which indicate the register number to be read ++ in next operation */ ++ twsiSlave.offset = 3; ++ twsiSlave.moreThen256 = MV_FALSE; ++ if(mode == MV_TRUE) ++ val = 0x1; ++ else ++ val = 0; ++ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); ++ val = (twsiVal & 0xfe) | val; ++ ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) ++ { ++ DB(mvOsPrintf("Board: twsi exp out val fail\n")); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); ++ ++ /* Change twsi exp to output */ ++ twsiSlave.offset = 7; ++ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); ++ val = (twsiVal & 0xfe); ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) ++ { ++ DB(mvOsPrintf("Board: twsi exp change to out fail\n")); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvBoardHDDPowerControl - Turn on/off the HDD power control on the RD-6281A ++* ++* DESCRIPTION: ++* ++* INPUT: ++* mode - MV_TRUE = on ; MV_FALSE = off ++* ++* OUTPUT: ++* MV_STATUS - MV_OK , MV_ERROR. ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_STATUS mvBoardHDDPowerControl(MV_BOOL mode) ++{ ++ ++ MV_U8 val = 1, twsiVal; ++ MV_TWSI_SLAVE twsiSlave; ++ MV_TWSI_ADDR slave; ++ ++ if(mvBoardIdGet() != RD_88F6281A_ID) ++ return MV_ERROR; ++ ++ /* TWSI init */ ++ slave.type = ADDR7_BIT; ++ slave.address = 0; ++ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); ++ ++ /* Read MPP module ID */ ++ DB(mvOsPrintf("Board: twsi exp set\n")); ++ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(1); ++ twsiSlave.slaveAddr.type = ADDR7_BIT; ++ twsiSlave.validOffset = MV_TRUE; ++ /* Offset is the first command after the address which indicate the register number to be read ++ in next operation */ ++ twsiSlave.offset = 3; ++ twsiSlave.moreThen256 = MV_FALSE; ++ if(mode == MV_TRUE) ++ val = 0x2; ++ else ++ val = 0; ++ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); ++ val = (twsiVal & 0xfd) | val; ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) ++ { ++ DB(mvOsPrintf("Board: twsi exp out val fail\n")); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); ++ ++ /* Change twsi exp to output */ ++ twsiSlave.offset = 7; ++ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); ++ val = (twsiVal & 0xfd); ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) ++ { ++ DB(mvOsPrintf("Board: twsi exp change to out fail\n")); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvBoardSDioWPControl - Turn on/off the SDIO WP on the RD-6281A ++* ++* DESCRIPTION: ++* ++* INPUT: ++* mode - MV_TRUE = on ; MV_FALSE = off ++* ++* OUTPUT: ++* MV_STATUS - MV_OK , MV_ERROR. ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_STATUS mvBoardSDioWPControl(MV_BOOL mode) ++{ ++ ++ MV_U8 val = 1, twsiVal; ++ MV_TWSI_SLAVE twsiSlave; ++ MV_TWSI_ADDR slave; ++ ++ if(mvBoardIdGet() != RD_88F6281A_ID) ++ return MV_ERROR; ++ ++ /* TWSI init */ ++ slave.type = ADDR7_BIT; ++ slave.address = 0; ++ mvTwsiInit(0, TWSI_SPEED, mvBoardTclkGet(), &slave, 0); ++ ++ /* Read MPP module ID */ ++ DB(mvOsPrintf("Board: twsi exp set\n")); ++ twsiSlave.slaveAddr.address = mvBoardTwsiExpAddrGet(0); ++ twsiSlave.slaveAddr.type = ADDR7_BIT; ++ twsiSlave.validOffset = MV_TRUE; ++ /* Offset is the first command after the address which indicate the register number to be read ++ in next operation */ ++ twsiSlave.offset = 3; ++ twsiSlave.moreThen256 = MV_FALSE; ++ if(mode == MV_TRUE) ++ val = 0x10; ++ else ++ val = 0; ++ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); ++ val = (twsiVal & 0xef) | val; ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) ++ { ++ DB(mvOsPrintf("Board: twsi exp out val fail\n")); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Board: twsi exp out val succeded\n")); ++ ++ /* Change twsi exp to output */ ++ twsiSlave.offset = 7; ++ mvTwsiRead(0, &twsiSlave, &twsiVal, 1); ++ val = (twsiVal & 0xef); ++ if( MV_OK != mvTwsiWrite (0, &twsiSlave, &val, 1) ) ++ { ++ DB(mvOsPrintf("Board: twsi exp change to out fail\n")); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Board: twsi exp change to out succeded\n")); ++ return MV_OK; ++} ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvLib.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,376 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++#ifndef __INCmvBoardEnvLibh ++#define __INCmvBoardEnvLibh ++ ++/* defines */ ++/* The below constant macros defines the board I2C EEPROM data offsets */ ++ ++ ++ ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "mvSysHwConfig.h" ++#include "boardEnv/mvBoardEnvSpec.h" ++ ++ ++/* DUART stuff for Tclk detection only */ ++#define DUART_BAUD_RATE 115200 ++#define MAX_CLOCK_MARGINE 5000000 /* Maximum detected clock margine */ ++ ++/* Voice devices assembly modes */ ++#define DAISY_CHAIN_MODE 1 ++#define DUAL_CHIP_SELECT_MODE 0 ++#define INTERRUPT_TO_MPP 1 ++#define INTERRUPT_TO_TDM 0 ++ ++ ++#define BOARD_ETH_PORT_NUM MV_ETH_MAX_PORTS ++#define BOARD_ETH_SWITCH_PORT_NUM 5 ++ ++#define MV_BOARD_MAX_USB_IF 1 ++#define MV_BOARD_MAX_MPP 7 ++#define MV_BOARD_NAME_LEN 0x20 ++ ++typedef struct _boardData ++{ ++ MV_U32 magic; ++ MV_U16 boardId; ++ MV_U8 boardVer; ++ MV_U8 boardRev; ++ MV_U32 reserved1; ++ MV_U32 reserved2; ++ ++}BOARD_DATA; ++ ++typedef enum _devBoardMppGroupClass ++{ ++ MV_BOARD_MPP_GROUP_1, ++ MV_BOARD_MPP_GROUP_2, ++ MV_BOARD_MAX_MPP_GROUP ++}MV_BOARD_MPP_GROUP_CLASS; ++ ++typedef enum _devBoardMppTypeClass ++{ ++ MV_BOARD_AUTO, ++ MV_BOARD_TDM, ++ MV_BOARD_AUDIO, ++ MV_BOARD_RGMII, ++ MV_BOARD_GMII, ++ MV_BOARD_TS, ++ MV_BOARD_MII, ++ MV_BOARD_OTHER ++}MV_BOARD_MPP_TYPE_CLASS; ++ ++typedef enum _devBoardModuleIdClass ++{ ++ MV_BOARD_MODULE_TDM_ID = 1, ++ MV_BOARD_MODULE_AUDIO_ID, ++ MV_BOARD_MODULE_RGMII_ID, ++ MV_BOARD_MODULE_GMII_ID, ++ MV_BOARD_MODULE_TS_ID, ++ MV_BOARD_MODULE_MII_ID, ++ MV_BOARD_MODULE_TDM_5CHAN_ID, ++ MV_BOARD_MODULE_OTHER_ID ++}MV_BOARD_MODULE_ID_CLASS; ++ ++typedef struct _boardMppTypeInfo ++{ ++ MV_BOARD_MPP_TYPE_CLASS boardMppGroup1; ++ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2; ++ ++}MV_BOARD_MPP_TYPE_INFO; ++ ++ ++typedef enum _devBoardClass ++{ ++ BOARD_DEV_NOR_FLASH, ++ BOARD_DEV_NAND_FLASH, ++ BOARD_DEV_SEVEN_SEG, ++ BOARD_DEV_FPGA, ++ BOARD_DEV_SRAM, ++ BOARD_DEV_SPI_FLASH, ++ BOARD_DEV_OTHER, ++}MV_BOARD_DEV_CLASS; ++ ++typedef enum _devTwsiBoardClass ++{ ++ BOARD_TWSI_RTC, ++ BOARD_DEV_TWSI_EXP, ++ BOARD_DEV_TWSI_SATR, ++ BOARD_TWSI_AUDIO_DEC, ++ BOARD_TWSI_OTHER ++}MV_BOARD_TWSI_CLASS; ++ ++typedef enum _devGppBoardClass ++{ ++ BOARD_GPP_RTC, ++ BOARD_GPP_MV_SWITCH, ++ BOARD_GPP_USB_VBUS, ++ BOARD_GPP_USB_VBUS_EN, ++ BOARD_GPP_USB_OC, ++ BOARD_GPP_USB_HOST_DEVICE, ++ BOARD_GPP_REF_CLCK, ++ BOARD_GPP_VOIP_SLIC, ++ BOARD_GPP_LIFELINE, ++ BOARD_GPP_BUTTON, ++ BOARD_GPP_TS_BUTTON_C, ++ BOARD_GPP_TS_BUTTON_U, ++ BOARD_GPP_TS_BUTTON_D, ++ BOARD_GPP_TS_BUTTON_L, ++ BOARD_GPP_TS_BUTTON_R, ++ BOARD_GPP_POWER_BUTTON, ++ BOARD_GPP_RESTOR_BUTTON, ++ BOARD_GPP_WPS_BUTTON, ++ BOARD_GPP_HDD0_POWER, ++ BOARD_GPP_HDD1_POWER, ++ BOARD_GPP_FAN_POWER, ++ BOARD_GPP_RESET, ++ BOARD_GPP_POWER_ON_LED, ++ BOARD_GPP_HDD_POWER, ++ BOARD_GPP_SDIO_POWER, ++ BOARD_GPP_SDIO_DETECT, ++ BOARD_GPP_SDIO_WP, ++ BOARD_GPP_SWITCH_PHY_INT, ++ BOARD_GPP_TSU_DIRCTION, ++ BOARD_GPP_OTHER ++}MV_BOARD_GPP_CLASS; ++ ++ ++typedef struct _devCsInfo ++{ ++ MV_U8 deviceCS; ++ MV_U32 params; ++ MV_U32 devClass; /* MV_BOARD_DEV_CLASS */ ++ MV_U8 devWidth; ++ ++}MV_DEV_CS_INFO; ++ ++ ++#define MV_BOARD_PHY_FORCE_10MB 0x0 ++#define MV_BOARD_PHY_FORCE_100MB 0x1 ++#define MV_BOARD_PHY_FORCE_1000MB 0x2 ++#define MV_BOARD_PHY_SPEED_AUTO 0x3 ++ ++typedef struct _boardSwitchInfo ++{ ++ MV_32 linkStatusIrq; ++ MV_32 qdPort[BOARD_ETH_SWITCH_PORT_NUM]; ++ MV_32 qdCpuPort; ++ MV_32 smiScanMode; /* 1 for SMI_MANUAL_MODE, 0 otherwise */ ++ MV_32 switchOnPort; ++ ++}MV_BOARD_SWITCH_INFO; ++ ++typedef struct _boardLedInfo ++{ ++ MV_U8 activeLedsNumber; ++ MV_U8 ledsPolarity; /* '0' or '1' to turn on led */ ++ MV_U8* gppPinNum; /* Pointer to GPP values */ ++ ++}MV_BOARD_LED_INFO; ++ ++typedef struct _boardGppInfo ++{ ++ MV_BOARD_GPP_CLASS devClass; ++ MV_U8 gppPinNum; ++ ++}MV_BOARD_GPP_INFO; ++ ++ ++typedef struct _boardTwsiInfo ++{ ++ MV_BOARD_TWSI_CLASS devClass; ++ MV_U8 twsiDevAddr; ++ MV_U8 twsiDevAddrType; ++ ++}MV_BOARD_TWSI_INFO; ++ ++ ++typedef enum _boardMacSpeed ++{ ++ BOARD_MAC_SPEED_10M, ++ BOARD_MAC_SPEED_100M, ++ BOARD_MAC_SPEED_1000M, ++ BOARD_MAC_SPEED_AUTO, ++ ++}MV_BOARD_MAC_SPEED; ++ ++typedef struct _boardMacInfo ++{ ++ MV_BOARD_MAC_SPEED boardMacSpeed; ++ MV_U8 boardEthSmiAddr; ++ ++}MV_BOARD_MAC_INFO; ++ ++typedef struct _boardMppInfo ++{ ++ MV_U32 mppGroup[MV_BOARD_MAX_MPP]; ++ ++}MV_BOARD_MPP_INFO; ++ ++typedef struct _boardInfo ++{ ++ char boardName[MV_BOARD_NAME_LEN]; ++ MV_U8 numBoardMppTypeValue; ++ MV_BOARD_MPP_TYPE_INFO* pBoardMppTypeValue; ++ MV_U8 numBoardMppConfigValue; ++ MV_BOARD_MPP_INFO* pBoardMppConfigValue; ++ MV_U32 intsGppMaskLow; ++ MV_U32 intsGppMaskHigh; ++ MV_U8 numBoardDeviceIf; ++ MV_DEV_CS_INFO* pDevCsInfo; ++ MV_U8 numBoardTwsiDev; ++ MV_BOARD_TWSI_INFO* pBoardTwsiDev; ++ MV_U8 numBoardMacInfo; ++ MV_BOARD_MAC_INFO* pBoardMacInfo; ++ MV_U8 numBoardGppInfo; ++ MV_BOARD_GPP_INFO* pBoardGppInfo; ++ MV_U8 activeLedsNumber; ++ MV_U8* pLedGppPin; ++ MV_U8 ledsPolarity; /* '0' or '1' to turn on led */ ++ /* GPP values */ ++ MV_U32 gppOutEnValLow; ++ MV_U32 gppOutEnValHigh; ++ MV_U32 gppOutValLow; ++ MV_U32 gppOutValHigh; ++ MV_U32 gppPolarityValLow; ++ MV_U32 gppPolarityValHigh; ++ ++ /* Switch Configuration */ ++ MV_BOARD_SWITCH_INFO* pSwitchInfo; ++}MV_BOARD_INFO; ++ ++ ++ ++MV_VOID mvBoardEnvInit(MV_VOID); ++MV_U32 mvBoardIdGet(MV_VOID); ++MV_U16 mvBoardModelGet(MV_VOID); ++MV_U16 mvBoardRevGet(MV_VOID); ++MV_STATUS mvBoardNameGet(char *pNameBuff); ++MV_32 mvBoardPhyAddrGet(MV_U32 ethPortNum); ++MV_BOARD_MAC_SPEED mvBoardMacSpeedGet(MV_U32 ethPortNum); ++MV_32 mvBoardLinkStatusIrqGet(MV_U32 ethPortNum); ++MV_32 mvBoardSwitchPortGet(MV_U32 ethPortNum, MV_U8 boardPortNum); ++MV_32 mvBoardSwitchCpuPortGet(MV_U32 ethPortNum); ++MV_32 mvBoardIsSwitchConnected(MV_U32 ethPortNum); ++MV_32 mvBoardSmiScanModeGet(MV_U32 ethPortNum); ++MV_BOOL mvBoardIsPortInSgmii(MV_U32 ethPortNum); ++MV_BOOL mvBoardIsPortInGmii(MV_VOID); ++MV_U32 mvBoardTclkGet(MV_VOID); ++MV_U32 mvBoardSysClkGet(MV_VOID); ++MV_U32 mvBoardDebugLedNumGet(MV_U32 boardId); ++MV_VOID mvBoardDebugLed(MV_U32 hexNum); ++MV_32 mvBoardMppGet(MV_U32 mppGroupNum); ++ ++MV_U8 mvBoardRtcTwsiAddrTypeGet(MV_VOID); ++MV_U8 mvBoardRtcTwsiAddrGet(MV_VOID); ++ ++MV_U8 mvBoardA2DTwsiAddrTypeGet(MV_VOID); ++MV_U8 mvBoardA2DTwsiAddrGet(MV_VOID); ++ ++MV_U8 mvBoardTwsiExpAddrGet(MV_U32 index); ++MV_U8 mvBoardTwsiSatRAddrTypeGet(MV_U32 index); ++MV_U8 mvBoardTwsiSatRAddrGet(MV_U32 index); ++MV_U8 mvBoardTwsiExpAddrTypeGet(MV_U32 index); ++MV_BOARD_MODULE_ID_CLASS mvBoarModuleTypeGet(MV_BOARD_MPP_GROUP_CLASS devClass); ++MV_BOARD_MPP_TYPE_CLASS mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass); ++MV_VOID mvBoardMppGroupTypeSet(MV_BOARD_MPP_GROUP_CLASS mppGroupClass, ++ MV_BOARD_MPP_TYPE_CLASS mppGroupType); ++MV_VOID mvBoardMppGroupIdUpdate(MV_VOID); ++MV_VOID mvBoardMppMuxSet(MV_VOID); ++MV_VOID mvBoardTdmMppSet(MV_32 chType); ++MV_VOID mvBoardVoiceConnModeGet(MV_32* connMode, MV_32* irqMode); ++ ++MV_VOID mvBoardMppModuleTypePrint(MV_VOID); ++MV_VOID mvBoardReset(MV_VOID); ++MV_U8 mvBoarTwsiSatRGet(MV_U8 devNum, MV_U8 regNum); ++MV_STATUS mvBoarTwsiSatRSet(MV_U8 devNum, MV_U8 regNum, MV_U8 regVal); ++MV_BOOL mvBoardSpecInitGet(MV_U32* regOff, MV_U32* data); ++/* Board devices API managments */ ++MV_32 mvBoardGetDevicesNumber(MV_BOARD_DEV_CLASS devClass); ++MV_32 mvBoardGetDeviceBaseAddr(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); ++MV_32 mvBoardGetDeviceBusWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); ++MV_32 mvBoardGetDeviceWidth(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); ++MV_32 mvBoardGetDeviceWinSize(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); ++MV_U32 boardGetDevCSNum(MV_32 devNum, MV_BOARD_DEV_CLASS devClass); ++ ++/* Gpio Pin Connections API */ ++MV_32 mvBoardUSBVbusGpioPinGet(int devId); ++MV_32 mvBoardUSBVbusEnGpioPinGet(int devId); ++MV_U32 mvBoardPexBridgeIntPinGet(MV_U32 devNum, MV_U32 intPin); ++ ++MV_32 mvBoardResetGpioPinGet(MV_VOID); ++MV_32 mvBoardRTCGpioPinGet(MV_VOID); ++MV_32 mvBoardGpioIntMaskLowGet(MV_VOID); ++MV_32 mvBoardGpioIntMaskHighGet(MV_VOID); ++MV_32 mvBoardSlicGpioPinGet(MV_U32 slicNum); ++ ++MV_32 mvBoardSDIOGpioPinGet(MV_VOID); ++MV_STATUS mvBoardSDioWPControl(MV_BOOL mode); ++MV_32 mvBoarGpioPinNumGet(MV_BOARD_GPP_CLASS class, MV_U32 index); ++ ++MV_32 mvBoardNandWidthGet(void); ++MV_STATUS mvBoardFanPowerControl(MV_BOOL mode); ++MV_STATUS mvBoardHDDPowerControl(MV_BOOL mode); ++#endif /* __INCmvBoardEnvLibh */ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,848 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++#include "mvCommon.h" ++#include "mvBoardEnvLib.h" ++#include "mvBoardEnvSpec.h" ++#include "twsi/mvTwsi.h" ++ ++#define DB_88F6281A_BOARD_PCI_IF_NUM 0x0 ++#define DB_88F6281A_BOARD_TWSI_DEF_NUM 0x7 ++#define DB_88F6281A_BOARD_MAC_INFO_NUM 0x2 ++#define DB_88F6281A_BOARD_GPP_INFO_NUM 0x3 ++#define DB_88F6281A_BOARD_MPP_CONFIG_NUM 0x1 ++#define DB_88F6281A_BOARD_MPP_GROUP_TYPE_NUM 0x1 ++#if defined(MV_NAND) && defined(MV_NAND_BOOT) ++ #define DB_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1 ++#elif defined(MV_NAND) && defined(MV_SPI_BOOT) ++ #define DB_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x2 ++#else ++ #define DB_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1 ++#endif ++#define DB_88F6281A_BOARD_DEBUG_LED_NUM 0x0 ++ ++ ++MV_BOARD_TWSI_INFO db88f6281AInfoBoardTwsiDev[] = ++ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ ++ { ++ {BOARD_DEV_TWSI_EXP, 0x20, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_EXP, 0x21, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_SATR, 0x4D, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_SATR, 0x4E, ADDR7_BIT}, ++ {BOARD_TWSI_AUDIO_DEC, 0x4A, ADDR7_BIT} ++ }; ++ ++MV_BOARD_MAC_INFO db88f6281AInfoBoardMacInfo[] = ++ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ ++ { ++ {BOARD_MAC_SPEED_AUTO, 0x8}, ++ {BOARD_MAC_SPEED_AUTO, 0x9} ++ }; ++ ++MV_BOARD_MPP_TYPE_INFO db88f6281AInfoBoardMppTypeInfo[] = ++ /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, ++ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ ++ {{MV_BOARD_AUTO, MV_BOARD_AUTO} ++ }; ++ ++MV_BOARD_GPP_INFO db88f6281AInfoBoardGppInfo[] = ++ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ ++ { ++ {BOARD_GPP_TSU_DIRCTION, 33} ++ /*muxed with TDM/Audio module via IOexpender ++ {BOARD_GPP_SDIO_DETECT, 38}, ++ {BOARD_GPP_USB_VBUS, 49}*/ ++ }; ++ ++MV_DEV_CS_INFO db88f6281AInfoBoardDeCsInfo[] = ++ /*{deviceCS, params, devType, devWidth}*/ ++#if defined(MV_NAND) && defined(MV_NAND_BOOT) ++ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ ++#elif defined(MV_NAND) && defined(MV_SPI_BOOT) ++ { ++ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ ++ {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ ++ }; ++#else ++ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ ++#endif ++ ++MV_BOARD_MPP_INFO db88f6281AInfoBoardMppConfigValue[] = ++ {{{ ++ DB_88F6281A_MPP0_7, ++ DB_88F6281A_MPP8_15, ++ DB_88F6281A_MPP16_23, ++ DB_88F6281A_MPP24_31, ++ DB_88F6281A_MPP32_39, ++ DB_88F6281A_MPP40_47, ++ DB_88F6281A_MPP48_55 ++ }}}; ++ ++ ++MV_BOARD_INFO db88f6281AInfo = { ++ "DB-88F6281A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ ++ DB_88F6281A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ ++ db88f6281AInfoBoardMppTypeInfo, ++ DB_88F6281A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ ++ db88f6281AInfoBoardMppConfigValue, ++ 0, /* intsGppMaskLow */ ++ 0, /* intsGppMaskHigh */ ++ DB_88F6281A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ ++ db88f6281AInfoBoardDeCsInfo, ++ DB_88F6281A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ ++ db88f6281AInfoBoardTwsiDev, ++ DB_88F6281A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ ++ db88f6281AInfoBoardMacInfo, ++ DB_88F6281A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ ++ db88f6281AInfoBoardGppInfo, ++ DB_88F6281A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ ++ NULL, ++ 0, /* ledsPolarity */ ++ DB_88F6281A_OE_LOW, /* gppOutEnLow */ ++ DB_88F6281A_OE_HIGH, /* gppOutEnHigh */ ++ DB_88F6281A_OE_VAL_LOW, /* gppOutValLow */ ++ DB_88F6281A_OE_VAL_HIGH, /* gppOutValHigh */ ++ 0, /* gppPolarityValLow */ ++ BIT6, /* gppPolarityValHigh */ ++ NULL /* pSwitchInfo */ ++}; ++ ++ ++#define RD_88F6281A_BOARD_PCI_IF_NUM 0x0 ++#define RD_88F6281A_BOARD_TWSI_DEF_NUM 0x2 ++#define RD_88F6281A_BOARD_MAC_INFO_NUM 0x2 ++#define RD_88F6281A_BOARD_GPP_INFO_NUM 0x5 ++#define RD_88F6281A_BOARD_MPP_GROUP_TYPE_NUM 0x1 ++#define RD_88F6281A_BOARD_MPP_CONFIG_NUM 0x1 ++#if defined(MV_NAND) && defined(MV_NAND_BOOT) ++ #define RD_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1 ++#elif defined(MV_NAND) && defined(MV_SPI_BOOT) ++ #define RD_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x2 ++#else ++ #define RD_88F6281A_BOARD_DEVICE_CONFIG_NUM 0x1 ++#endif ++#define RD_88F6281A_BOARD_DEBUG_LED_NUM 0x0 ++ ++MV_BOARD_MAC_INFO rd88f6281AInfoBoardMacInfo[] = ++ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ ++ {{BOARD_MAC_SPEED_1000M, 0xa}, ++ {BOARD_MAC_SPEED_AUTO, 0xb} ++ }; ++ ++MV_BOARD_SWITCH_INFO rd88f6281AInfoBoardSwitchInfo[] = ++ /* MV_32 linkStatusIrq, {MV_32 qdPort0, MV_32 qdPort1, MV_32 qdPort2, MV_32 qdPort3, MV_32 qdPort4}, ++ MV_32 qdCpuPort, MV_32 smiScanMode, MV_32 switchOnPort} */ ++ {{38, {0, 1, 2, 3, -1}, 5, 2, 0}, ++ {-1, {-1}, -1, -1, -1}}; ++ ++MV_BOARD_TWSI_INFO rd88f6281AInfoBoardTwsiDev[] = ++ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ ++ { ++ {BOARD_DEV_TWSI_EXP, 0xFF, ADDR7_BIT}, /* dummy entry to align with modules indexes */ ++ {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT} ++ }; ++ ++MV_BOARD_MPP_TYPE_INFO rd88f6281AInfoBoardMppTypeInfo[] = ++ {{MV_BOARD_RGMII, MV_BOARD_TDM} ++ }; ++ ++MV_DEV_CS_INFO rd88f6281AInfoBoardDeCsInfo[] = ++ /*{deviceCS, params, devType, devWidth}*/ ++#if defined(MV_NAND) && defined(MV_NAND_BOOT) ++ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ ++#elif defined(MV_NAND) && defined(MV_SPI_BOOT) ++ { ++ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ ++ {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ ++ }; ++#else ++ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ ++#endif ++ ++MV_BOARD_GPP_INFO rd88f6281AInfoBoardGppInfo[] = ++ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ ++ {{BOARD_GPP_SDIO_DETECT, 28}, ++ {BOARD_GPP_USB_OC, 29}, ++ {BOARD_GPP_WPS_BUTTON, 35}, ++ {BOARD_GPP_MV_SWITCH, 38}, ++ {BOARD_GPP_USB_VBUS, 49} ++ }; ++ ++MV_BOARD_MPP_INFO rd88f6281AInfoBoardMppConfigValue[] = ++ {{{ ++ RD_88F6281A_MPP0_7, ++ RD_88F6281A_MPP8_15, ++ RD_88F6281A_MPP16_23, ++ RD_88F6281A_MPP24_31, ++ RD_88F6281A_MPP32_39, ++ RD_88F6281A_MPP40_47, ++ RD_88F6281A_MPP48_55 ++ }}}; ++ ++MV_BOARD_INFO rd88f6281AInfo = { ++ "RD-88F6281A", /* boardName[MAX_BOARD_NAME_LEN] */ ++ RD_88F6281A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ ++ rd88f6281AInfoBoardMppTypeInfo, ++ RD_88F6281A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ ++ rd88f6281AInfoBoardMppConfigValue, ++ 0, /* intsGppMaskLow */ ++ (1 << 3), /* intsGppMaskHigh */ ++ RD_88F6281A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ ++ rd88f6281AInfoBoardDeCsInfo, ++ RD_88F6281A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ ++ rd88f6281AInfoBoardTwsiDev, ++ RD_88F6281A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ ++ rd88f6281AInfoBoardMacInfo, ++ RD_88F6281A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ ++ rd88f6281AInfoBoardGppInfo, ++ RD_88F6281A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ ++ NULL, ++ 0, /* ledsPolarity */ ++ RD_88F6281A_OE_LOW, /* gppOutEnLow */ ++ RD_88F6281A_OE_HIGH, /* gppOutEnHigh */ ++ RD_88F6281A_OE_VAL_LOW, /* gppOutValLow */ ++ RD_88F6281A_OE_VAL_HIGH, /* gppOutValHigh */ ++ 0, /* gppPolarityValLow */ ++ BIT6, /* gppPolarityValHigh */ ++ rd88f6281AInfoBoardSwitchInfo /* pSwitchInfo */ ++}; ++ ++ ++#define DB_88F6192A_BOARD_PCI_IF_NUM 0x0 ++#define DB_88F6192A_BOARD_TWSI_DEF_NUM 0x7 ++#define DB_88F6192A_BOARD_MAC_INFO_NUM 0x2 ++#define DB_88F6192A_BOARD_GPP_INFO_NUM 0x3 ++#define DB_88F6192A_BOARD_MPP_GROUP_TYPE_NUM 0x1 ++#define DB_88F6192A_BOARD_MPP_CONFIG_NUM 0x1 ++#if defined(MV_NAND) && defined(MV_NAND_BOOT) ++ #define DB_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x1 ++#elif defined(MV_NAND) && defined(MV_SPI_BOOT) ++ #define DB_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x2 ++#else ++ #define DB_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x1 ++#endif ++#define DB_88F6192A_BOARD_DEBUG_LED_NUM 0x0 ++ ++MV_BOARD_TWSI_INFO db88f6192AInfoBoardTwsiDev[] = ++ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ ++ { ++ {BOARD_DEV_TWSI_EXP, 0x20, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_EXP, 0x21, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_SATR, 0x4D, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_SATR, 0x4E, ADDR7_BIT}, ++ {BOARD_TWSI_AUDIO_DEC, 0x4A, ADDR7_BIT} ++ }; ++ ++MV_BOARD_MAC_INFO db88f6192AInfoBoardMacInfo[] = ++ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ ++ { ++ {BOARD_MAC_SPEED_AUTO, 0x8}, ++ {BOARD_MAC_SPEED_AUTO, 0x9} ++ }; ++ ++MV_BOARD_MPP_TYPE_INFO db88f6192AInfoBoardMppTypeInfo[] = ++ /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, ++ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ ++ {{MV_BOARD_AUTO, MV_BOARD_OTHER} ++ }; ++ ++MV_DEV_CS_INFO db88f6192AInfoBoardDeCsInfo[] = ++ /*{deviceCS, params, devType, devWidth}*/ ++#if defined(MV_NAND) && defined(MV_NAND_BOOT) ++ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ ++#elif defined(MV_NAND) && defined(MV_SPI_BOOT) ++ { ++ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ ++ {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ ++ }; ++#else ++ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ ++#endif ++ ++MV_BOARD_GPP_INFO db88f6192AInfoBoardGppInfo[] = ++ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ ++ { ++ {BOARD_GPP_SDIO_WP, 20}, ++ {BOARD_GPP_USB_VBUS, 22}, ++ {BOARD_GPP_SDIO_DETECT, 23}, ++ }; ++ ++MV_BOARD_MPP_INFO db88f6192AInfoBoardMppConfigValue[] = ++ {{{ ++ DB_88F6192A_MPP0_7, ++ DB_88F6192A_MPP8_15, ++ DB_88F6192A_MPP16_23, ++ DB_88F6192A_MPP24_31, ++ DB_88F6192A_MPP32_35 ++ }}}; ++ ++MV_BOARD_INFO db88f6192AInfo = { ++ "DB-88F6192A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ ++ DB_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ ++ db88f6192AInfoBoardMppTypeInfo, ++ DB_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ ++ db88f6192AInfoBoardMppConfigValue, ++ 0, /* intsGppMaskLow */ ++ (1 << 3), /* intsGppMaskHigh */ ++ DB_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ ++ db88f6192AInfoBoardDeCsInfo, ++ DB_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ ++ db88f6192AInfoBoardTwsiDev, ++ DB_88F6192A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ ++ db88f6192AInfoBoardMacInfo, ++ DB_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ ++ db88f6192AInfoBoardGppInfo, ++ DB_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ ++ NULL, ++ 0, /* ledsPolarity */ ++ DB_88F6192A_OE_LOW, /* gppOutEnLow */ ++ DB_88F6192A_OE_HIGH, /* gppOutEnHigh */ ++ DB_88F6192A_OE_VAL_LOW, /* gppOutValLow */ ++ DB_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */ ++ 0, /* gppPolarityValLow */ ++ 0, /* gppPolarityValHigh */ ++ NULL /* pSwitchInfo */ ++}; ++ ++#define DB_88F6190A_BOARD_MAC_INFO_NUM 0x1 ++ ++MV_BOARD_INFO db88f6190AInfo = { ++ "DB-88F6190A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ ++ DB_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ ++ db88f6192AInfoBoardMppTypeInfo, ++ DB_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ ++ db88f6192AInfoBoardMppConfigValue, ++ 0, /* intsGppMaskLow */ ++ (1 << 3), /* intsGppMaskHigh */ ++ DB_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ ++ db88f6192AInfoBoardDeCsInfo, ++ DB_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ ++ db88f6192AInfoBoardTwsiDev, ++ DB_88F6190A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ ++ db88f6192AInfoBoardMacInfo, ++ DB_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ ++ db88f6192AInfoBoardGppInfo, ++ DB_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ ++ NULL, ++ 0, /* ledsPolarity */ ++ DB_88F6192A_OE_LOW, /* gppOutEnLow */ ++ DB_88F6192A_OE_HIGH, /* gppOutEnHigh */ ++ DB_88F6192A_OE_VAL_LOW, /* gppOutValLow */ ++ DB_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */ ++ 0, /* gppPolarityValLow */ ++ 0, /* gppPolarityValHigh */ ++ NULL /* pSwitchInfo */ ++}; ++ ++#define RD_88F6192A_BOARD_PCI_IF_NUM 0x0 ++#define RD_88F6192A_BOARD_TWSI_DEF_NUM 0x0 ++#define RD_88F6192A_BOARD_MAC_INFO_NUM 0x1 ++#define RD_88F6192A_BOARD_GPP_INFO_NUM 0xE ++#define RD_88F6192A_BOARD_MPP_GROUP_TYPE_NUM 0x1 ++#define RD_88F6192A_BOARD_MPP_CONFIG_NUM 0x1 ++#define RD_88F6192A_BOARD_DEVICE_CONFIG_NUM 0x1 ++#define RD_88F6192A_BOARD_DEBUG_LED_NUM 0x3 ++ ++MV_U8 rd88f6192AInfoBoardDebugLedIf[] = ++ {17, 28, 29}; ++ ++MV_BOARD_MAC_INFO rd88f6192AInfoBoardMacInfo[] = ++ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ ++ {{BOARD_MAC_SPEED_AUTO, 0x8} ++ }; ++ ++MV_BOARD_MPP_TYPE_INFO rd88f6192AInfoBoardMppTypeInfo[] = ++ /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, ++ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ ++ {{MV_BOARD_OTHER, MV_BOARD_OTHER} ++ }; ++ ++MV_DEV_CS_INFO rd88f6192AInfoBoardDeCsInfo[] = ++ /*{deviceCS, params, devType, devWidth}*/ ++ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ ++ ++MV_BOARD_GPP_INFO rd88f6192AInfoBoardGppInfo[] = ++ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ ++ { ++ {BOARD_GPP_USB_VBUS_EN, 10}, ++ {BOARD_GPP_USB_HOST_DEVICE, 11}, ++ {BOARD_GPP_RESET, 14}, ++ {BOARD_GPP_POWER_ON_LED, 15}, ++ {BOARD_GPP_HDD_POWER, 16}, ++ {BOARD_GPP_WPS_BUTTON, 24}, ++ {BOARD_GPP_TS_BUTTON_C, 25}, ++ {BOARD_GPP_USB_VBUS, 26}, ++ {BOARD_GPP_USB_OC, 27}, ++ {BOARD_GPP_TS_BUTTON_U, 30}, ++ {BOARD_GPP_TS_BUTTON_R, 31}, ++ {BOARD_GPP_TS_BUTTON_L, 32}, ++ {BOARD_GPP_TS_BUTTON_D, 34}, ++ {BOARD_GPP_FAN_POWER, 35} ++ }; ++ ++MV_BOARD_MPP_INFO rd88f6192AInfoBoardMppConfigValue[] = ++ {{{ ++ RD_88F6192A_MPP0_7, ++ RD_88F6192A_MPP8_15, ++ RD_88F6192A_MPP16_23, ++ RD_88F6192A_MPP24_31, ++ RD_88F6192A_MPP32_35 ++ }}}; ++ ++MV_BOARD_INFO rd88f6192AInfo = { ++ "RD-88F6192A-NAS", /* boardName[MAX_BOARD_NAME_LEN] */ ++ RD_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ ++ rd88f6192AInfoBoardMppTypeInfo, ++ RD_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ ++ rd88f6192AInfoBoardMppConfigValue, ++ 0, /* intsGppMaskLow */ ++ (1 << 3), /* intsGppMaskHigh */ ++ RD_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ ++ rd88f6192AInfoBoardDeCsInfo, ++ RD_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ ++ NULL, ++ RD_88F6192A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ ++ rd88f6192AInfoBoardMacInfo, ++ RD_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ ++ rd88f6192AInfoBoardGppInfo, ++ RD_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ ++ rd88f6192AInfoBoardDebugLedIf, ++ 0, /* ledsPolarity */ ++ RD_88F6192A_OE_LOW, /* gppOutEnLow */ ++ RD_88F6192A_OE_HIGH, /* gppOutEnHigh */ ++ RD_88F6192A_OE_VAL_LOW, /* gppOutValLow */ ++ RD_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */ ++ 0, /* gppPolarityValLow */ ++ 0, /* gppPolarityValHigh */ ++ NULL /* pSwitchInfo */ ++}; ++ ++MV_BOARD_INFO rd88f6190AInfo = { ++ "RD-88F6190A-NAS", /* boardName[MAX_BOARD_NAME_LEN] */ ++ RD_88F6192A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ ++ rd88f6192AInfoBoardMppTypeInfo, ++ RD_88F6192A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ ++ rd88f6192AInfoBoardMppConfigValue, ++ 0, /* intsGppMaskLow */ ++ (1 << 3), /* intsGppMaskHigh */ ++ RD_88F6192A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ ++ rd88f6192AInfoBoardDeCsInfo, ++ RD_88F6192A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ ++ NULL, ++ RD_88F6192A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ ++ rd88f6192AInfoBoardMacInfo, ++ RD_88F6192A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ ++ rd88f6192AInfoBoardGppInfo, ++ RD_88F6192A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ ++ rd88f6192AInfoBoardDebugLedIf, ++ 0, /* ledsPolarity */ ++ RD_88F6192A_OE_LOW, /* gppOutEnLow */ ++ RD_88F6192A_OE_HIGH, /* gppOutEnHigh */ ++ RD_88F6192A_OE_VAL_LOW, /* gppOutValLow */ ++ RD_88F6192A_OE_VAL_HIGH, /* gppOutValHigh */ ++ 0, /* gppPolarityValLow */ ++ 0, /* gppPolarityValHigh */ ++ NULL /* pSwitchInfo */ ++}; ++ ++#define DB_88F6180A_BOARD_PCI_IF_NUM 0x0 ++#define DB_88F6180A_BOARD_TWSI_DEF_NUM 0x5 ++#define DB_88F6180A_BOARD_MAC_INFO_NUM 0x1 ++#define DB_88F6180A_BOARD_GPP_INFO_NUM 0x0 ++#define DB_88F6180A_BOARD_MPP_GROUP_TYPE_NUM 0x2 ++#define DB_88F6180A_BOARD_MPP_CONFIG_NUM 0x1 ++#define DB_88F6180A_BOARD_DEVICE_CONFIG_NUM 0x1 ++#define DB_88F6180A_BOARD_DEBUG_LED_NUM 0x0 ++ ++MV_BOARD_TWSI_INFO db88f6180AInfoBoardTwsiDev[] = ++ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ ++ { ++ {BOARD_DEV_TWSI_EXP, 0x20, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_EXP, 0x21, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_EXP, 0x27, ADDR7_BIT}, ++ {BOARD_DEV_TWSI_SATR, 0x4C, ADDR7_BIT}, ++ {BOARD_TWSI_AUDIO_DEC, 0x4A, ADDR7_BIT} ++ }; ++ ++MV_BOARD_MAC_INFO db88f6180AInfoBoardMacInfo[] = ++ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ ++ {{BOARD_MAC_SPEED_AUTO, 0x8} ++ }; ++ ++MV_BOARD_GPP_INFO db88f6180AInfoBoardGppInfo[] = ++ /* {{MV_BOARD_GPP_CLASS devClass, MV_U8 gppPinNum}} */ ++ { ++ /* Muxed with TDM/Audio module via IOexpender ++ {BOARD_GPP_USB_VBUS, 6} */ ++ }; ++ ++MV_BOARD_MPP_TYPE_INFO db88f6180AInfoBoardMppTypeInfo[] = ++ /* {{MV_BOARD_MPP_TYPE_CLASS boardMppGroup1, ++ MV_BOARD_MPP_TYPE_CLASS boardMppGroup2}} */ ++ {{MV_BOARD_OTHER, MV_BOARD_AUTO} ++ }; ++ ++MV_DEV_CS_INFO db88f6180AInfoBoardDeCsInfo[] = ++ /*{deviceCS, params, devType, devWidth}*/ ++#if defined(MV_NAND_BOOT) ++ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ ++#else ++ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ ++#endif ++ ++MV_BOARD_MPP_INFO db88f6180AInfoBoardMppConfigValue[] = ++ {{{ ++ DB_88F6180A_MPP0_7, ++ DB_88F6180A_MPP8_15, ++ DB_88F6180A_MPP16_23, ++ DB_88F6180A_MPP24_31, ++ DB_88F6180A_MPP32_39, ++ DB_88F6180A_MPP40_44 ++ }}}; ++ ++MV_BOARD_INFO db88f6180AInfo = { ++ "DB-88F6180A-BP", /* boardName[MAX_BOARD_NAME_LEN] */ ++ DB_88F6180A_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ ++ db88f6180AInfoBoardMppTypeInfo, ++ DB_88F6180A_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ ++ db88f6180AInfoBoardMppConfigValue, ++ 0, /* intsGppMaskLow */ ++ 0, /* intsGppMaskHigh */ ++ DB_88F6180A_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ ++ db88f6180AInfoBoardDeCsInfo, ++ DB_88F6180A_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ ++ db88f6180AInfoBoardTwsiDev, ++ DB_88F6180A_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ ++ db88f6180AInfoBoardMacInfo, ++ DB_88F6180A_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ ++ NULL, ++ DB_88F6180A_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ ++ NULL, ++ 0, /* ledsPolarity */ ++ DB_88F6180A_OE_LOW, /* gppOutEnLow */ ++ DB_88F6180A_OE_HIGH, /* gppOutEnHigh */ ++ DB_88F6180A_OE_VAL_LOW, /* gppOutValLow */ ++ DB_88F6180A_OE_VAL_HIGH, /* gppOutValHigh */ ++ 0, /* gppPolarityValLow */ ++ 0, /* gppPolarityValHigh */ ++ NULL /* pSwitchInfo */ ++}; ++ ++ ++#define RD_88F6281A_PCAC_BOARD_PCI_IF_NUM 0x0 ++#define RD_88F6281A_PCAC_BOARD_TWSI_DEF_NUM 0x1 ++#define RD_88F6281A_PCAC_BOARD_MAC_INFO_NUM 0x1 ++#define RD_88F6281A_PCAC_BOARD_GPP_INFO_NUM 0x0 ++#define RD_88F6281A_PCAC_BOARD_MPP_GROUP_TYPE_NUM 0x1 ++#define RD_88F6281A_PCAC_BOARD_MPP_CONFIG_NUM 0x1 ++#if defined(MV_NAND) && defined(MV_NAND_BOOT) ++ #define RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM 0x1 ++#elif defined(MV_NAND) && defined(MV_SPI_BOOT) ++ #define RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM 0x2 ++#else ++ #define RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM 0x1 ++#endif ++#define RD_88F6281A_PCAC_BOARD_DEBUG_LED_NUM 0x4 ++ ++MV_U8 rd88f6281APcacInfoBoardDebugLedIf[] = ++ {38, 39, 40, 41}; ++ ++MV_BOARD_MAC_INFO rd88f6281APcacInfoBoardMacInfo[] = ++ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ ++ {{BOARD_MAC_SPEED_AUTO, 0x8} ++ }; ++ ++MV_BOARD_TWSI_INFO rd88f6281APcacInfoBoardTwsiDev[] = ++ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ ++ { ++ {BOARD_TWSI_OTHER, 0xa7, ADDR7_BIT} ++ }; ++ ++MV_BOARD_MPP_TYPE_INFO rd88f6281APcacInfoBoardMppTypeInfo[] = ++ {{MV_BOARD_OTHER, MV_BOARD_OTHER} ++ }; ++ ++MV_DEV_CS_INFO rd88f6281APcacInfoBoardDeCsInfo[] = ++ /*{deviceCS, params, devType, devWidth}*/ ++#if defined(MV_NAND) && defined(MV_NAND_BOOT) ++ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ ++#elif defined(MV_NAND) && defined(MV_SPI_BOOT) ++ { ++ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ ++ {1, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ ++ }; ++#else ++ {{1, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ ++#endif ++ ++MV_BOARD_MPP_INFO rd88f6281APcacInfoBoardMppConfigValue[] = ++ {{{ ++ RD_88F6281A_PCAC_MPP0_7, ++ RD_88F6281A_PCAC_MPP8_15, ++ RD_88F6281A_PCAC_MPP16_23, ++ RD_88F6281A_PCAC_MPP24_31, ++ RD_88F6281A_PCAC_MPP32_39, ++ RD_88F6281A_PCAC_MPP40_47, ++ RD_88F6281A_PCAC_MPP48_55 ++ }}}; ++ ++MV_BOARD_INFO rd88f6281APcacInfo = { ++ "RD-88F6281A-PCAC", /* boardName[MAX_BOARD_NAME_LEN] */ ++ RD_88F6281A_PCAC_BOARD_MPP_GROUP_TYPE_NUM, /* numBoardMppGroupType */ ++ rd88f6281APcacInfoBoardMppTypeInfo, ++ RD_88F6281A_PCAC_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ ++ rd88f6281APcacInfoBoardMppConfigValue, ++ 0, /* intsGppMaskLow */ ++ (1 << 3), /* intsGppMaskHigh */ ++ RD_88F6281A_PCAC_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ ++ rd88f6281APcacInfoBoardDeCsInfo, ++ RD_88F6281A_PCAC_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ ++ rd88f6281APcacInfoBoardTwsiDev, ++ RD_88F6281A_PCAC_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ ++ rd88f6281APcacInfoBoardMacInfo, ++ RD_88F6281A_PCAC_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ ++ 0, ++ RD_88F6281A_PCAC_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ ++ NULL, ++ 0, /* ledsPolarity */ ++ RD_88F6281A_PCAC_OE_LOW, /* gppOutEnLow */ ++ RD_88F6281A_PCAC_OE_HIGH, /* gppOutEnHigh */ ++ RD_88F6281A_PCAC_OE_VAL_LOW, /* gppOutValLow */ ++ RD_88F6281A_PCAC_OE_VAL_HIGH, /* gppOutValHigh */ ++ 0, /* gppPolarityValLow */ ++ 0, /* gppPolarityValHigh */ ++ NULL /* pSwitchInfo */ ++}; ++ ++ ++/* 6281 Sheeva Plug*/ ++ ++#define SHEEVA_PLUG_BOARD_PCI_IF_NUM 0x0 ++#define SHEEVA_PLUG_BOARD_TWSI_DEF_NUM 0x0 ++#define SHEEVA_PLUG_BOARD_MAC_INFO_NUM 0x1 ++#define SHEEVA_PLUG_BOARD_GPP_INFO_NUM 0x0 ++#define SHEEVA_PLUG_BOARD_MPP_GROUP_TYPE_NUN 0x1 ++#define SHEEVA_PLUG_BOARD_MPP_CONFIG_NUM 0x1 ++#define SHEEVA_PLUG_BOARD_DEVICE_CONFIG_NUM 0x1 ++#define SHEEVA_PLUG_BOARD_DEBUG_LED_NUM 0x1 ++ ++MV_U8 sheevaPlugInfoBoardDebugLedIf[] = ++ {49}; ++ ++MV_BOARD_MAC_INFO sheevaPlugInfoBoardMacInfo[] = ++ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ ++ {{BOARD_MAC_SPEED_AUTO, 0x0}}; ++ ++MV_BOARD_TWSI_INFO sheevaPlugInfoBoardTwsiDev[] = ++ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ ++ {{BOARD_TWSI_OTHER, 0x0, ADDR7_BIT}}; ++ ++MV_BOARD_MPP_TYPE_INFO sheevaPlugInfoBoardMppTypeInfo[] = ++ {{MV_BOARD_OTHER, MV_BOARD_OTHER} ++ }; ++ ++MV_DEV_CS_INFO sheevaPlugInfoBoardDeCsInfo[] = ++ /*{deviceCS, params, devType, devWidth}*/ ++ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ ++ ++MV_BOARD_MPP_INFO sheevaPlugInfoBoardMppConfigValue[] = ++ {{{ ++ RD_SHEEVA_PLUG_MPP0_7, ++ RD_SHEEVA_PLUG_MPP8_15, ++ RD_SHEEVA_PLUG_MPP16_23, ++ RD_SHEEVA_PLUG_MPP24_31, ++ RD_SHEEVA_PLUG_MPP32_39, ++ RD_SHEEVA_PLUG_MPP40_47, ++ RD_SHEEVA_PLUG_MPP48_55 ++ }}}; ++ ++MV_BOARD_INFO sheevaPlugInfo = { ++ "SHEEVA PLUG", /* boardName[MAX_BOARD_NAME_LEN] */ ++ SHEEVA_PLUG_BOARD_MPP_GROUP_TYPE_NUN, /* numBoardMppGroupType */ ++ sheevaPlugInfoBoardMppTypeInfo, ++ SHEEVA_PLUG_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ ++ sheevaPlugInfoBoardMppConfigValue, ++ 0, /* intsGppMaskLow */ ++ 0, /* intsGppMaskHigh */ ++ SHEEVA_PLUG_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ ++ sheevaPlugInfoBoardDeCsInfo, ++ SHEEVA_PLUG_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ ++ sheevaPlugInfoBoardTwsiDev, ++ SHEEVA_PLUG_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ ++ sheevaPlugInfoBoardMacInfo, ++ SHEEVA_PLUG_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ ++ 0, ++ SHEEVA_PLUG_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ ++ sheevaPlugInfoBoardDebugLedIf, ++ 0, /* ledsPolarity */ ++ RD_SHEEVA_PLUG_OE_LOW, /* gppOutEnLow */ ++ RD_SHEEVA_PLUG_OE_HIGH, /* gppOutEnHigh */ ++ RD_SHEEVA_PLUG_OE_VAL_LOW, /* gppOutValLow */ ++ RD_SHEEVA_PLUG_OE_VAL_HIGH, /* gppOutValHigh */ ++ 0, /* gppPolarityValLow */ ++ 0, /* gppPolarityValHigh */ ++ NULL /* pSwitchInfo */ ++}; ++ ++/* Customer specific board place holder*/ ++ ++#define DB_CUSTOMER_BOARD_PCI_IF_NUM 0x0 ++#define DB_CUSTOMER_BOARD_TWSI_DEF_NUM 0x0 ++#define DB_CUSTOMER_BOARD_MAC_INFO_NUM 0x0 ++#define DB_CUSTOMER_BOARD_GPP_INFO_NUM 0x0 ++#define DB_CUSTOMER_BOARD_MPP_GROUP_TYPE_NUN 0x0 ++#define DB_CUSTOMER_BOARD_MPP_CONFIG_NUM 0x0 ++#if defined(MV_NAND) && defined(MV_NAND_BOOT) ++ #define DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM 0x0 ++#elif defined(MV_NAND) && defined(MV_SPI_BOOT) ++ #define DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM 0x0 ++#else ++ #define DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM 0x0 ++#endif ++#define DB_CUSTOMER_BOARD_DEBUG_LED_NUM 0x0 ++ ++MV_U8 dbCustomerInfoBoardDebugLedIf[] = ++ {0}; ++ ++MV_BOARD_MAC_INFO dbCustomerInfoBoardMacInfo[] = ++ /* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_U8 boardEthSmiAddr}} */ ++ {{BOARD_MAC_SPEED_AUTO, 0x0}}; ++ ++MV_BOARD_TWSI_INFO dbCustomerInfoBoardTwsiDev[] = ++ /* {{MV_BOARD_DEV_CLASS devClass, MV_U8 twsiDevAddr, MV_U8 twsiDevAddrType}} */ ++ {{BOARD_TWSI_OTHER, 0x0, ADDR7_BIT}}; ++ ++MV_BOARD_MPP_TYPE_INFO dbCustomerInfoBoardMppTypeInfo[] = ++ {{MV_BOARD_OTHER, MV_BOARD_OTHER} ++ }; ++ ++MV_DEV_CS_INFO dbCustomerInfoBoardDeCsInfo[] = ++ /*{deviceCS, params, devType, devWidth}*/ ++#if defined(MV_NAND) && defined(MV_NAND_BOOT) ++ {{0, N_A, BOARD_DEV_NAND_FLASH, 8}}; /* NAND DEV */ ++#elif defined(MV_NAND) && defined(MV_SPI_BOOT) ++ { ++ {0, N_A, BOARD_DEV_NAND_FLASH, 8}, /* NAND DEV */ ++ {2, N_A, BOARD_DEV_SPI_FLASH, 8}, /* SPI DEV */ ++ }; ++#else ++ {{2, N_A, BOARD_DEV_SPI_FLASH, 8}}; /* SPI DEV */ ++#endif ++ ++MV_BOARD_MPP_INFO dbCustomerInfoBoardMppConfigValue[] = ++ {{{ ++ DB_CUSTOMER_MPP0_7, ++ DB_CUSTOMER_MPP8_15, ++ DB_CUSTOMER_MPP16_23, ++ DB_CUSTOMER_MPP24_31, ++ DB_CUSTOMER_MPP32_39, ++ DB_CUSTOMER_MPP40_47, ++ DB_CUSTOMER_MPP48_55 ++ }}}; ++ ++MV_BOARD_INFO dbCustomerInfo = { ++ "DB-CUSTOMER", /* boardName[MAX_BOARD_NAME_LEN] */ ++ DB_CUSTOMER_BOARD_MPP_GROUP_TYPE_NUN, /* numBoardMppGroupType */ ++ dbCustomerInfoBoardMppTypeInfo, ++ DB_CUSTOMER_BOARD_MPP_CONFIG_NUM, /* numBoardMppConfig */ ++ dbCustomerInfoBoardMppConfigValue, ++ 0, /* intsGppMaskLow */ ++ 0, /* intsGppMaskHigh */ ++ DB_CUSTOMER_BOARD_DEVICE_CONFIG_NUM, /* numBoardDevIf */ ++ dbCustomerInfoBoardDeCsInfo, ++ DB_CUSTOMER_BOARD_TWSI_DEF_NUM, /* numBoardTwsiDev */ ++ dbCustomerInfoBoardTwsiDev, ++ DB_CUSTOMER_BOARD_MAC_INFO_NUM, /* numBoardMacInfo */ ++ dbCustomerInfoBoardMacInfo, ++ DB_CUSTOMER_BOARD_GPP_INFO_NUM, /* numBoardGppInfo */ ++ 0, ++ DB_CUSTOMER_BOARD_DEBUG_LED_NUM, /* activeLedsNumber */ ++ NULL, ++ 0, /* ledsPolarity */ ++ DB_CUSTOMER_OE_LOW, /* gppOutEnLow */ ++ DB_CUSTOMER_OE_HIGH, /* gppOutEnHigh */ ++ DB_CUSTOMER_OE_VAL_LOW, /* gppOutValLow */ ++ DB_CUSTOMER_OE_VAL_HIGH, /* gppOutValHigh */ ++ 0, /* gppPolarityValLow */ ++ 0, /* gppPolarityValHigh */ ++ NULL /* pSwitchInfo */ ++}; ++ ++MV_BOARD_INFO* boardInfoTbl[] = { ++ &db88f6281AInfo, ++ &rd88f6281AInfo, ++ &db88f6192AInfo, ++ &rd88f6192AInfo, ++ &db88f6180AInfo, ++ &db88f6190AInfo, ++ &rd88f6190AInfo, ++ &rd88f6281APcacInfo, ++ &dbCustomerInfo, ++ &sheevaPlugInfo ++ }; ++ ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/mvBoardEnvSpec.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,262 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvBoardEnvSpech ++#define __INCmvBoardEnvSpech ++ ++#include "mvSysHwConfig.h" ++ ++ ++/* For future use */ ++#define BD_ID_DATA_START_OFFS 0x0 ++#define BD_DETECT_SEQ_OFFS 0x0 ++#define BD_SYS_NUM_OFFS 0x4 ++#define BD_NAME_OFFS 0x8 ++ ++/* I2C bus addresses */ ++#define MV_BOARD_CTRL_I2C_ADDR 0x0 /* Controller slave addr */ ++#define MV_BOARD_CTRL_I2C_ADDR_TYPE ADDR7_BIT ++#define MV_BOARD_DIMM0_I2C_ADDR 0x56 ++#define MV_BOARD_DIMM0_I2C_ADDR_TYPE ADDR7_BIT ++#define MV_BOARD_DIMM1_I2C_ADDR 0x54 ++#define MV_BOARD_DIMM1_I2C_ADDR_TYPE ADDR7_BIT ++#define MV_BOARD_EEPROM_I2C_ADDR 0x51 ++#define MV_BOARD_EEPROM_I2C_ADDR_TYPE ADDR7_BIT ++#define MV_BOARD_MAIN_EEPROM_I2C_ADDR 0x50 ++#define MV_BOARD_MAIN_EEPROM_I2C_ADDR_TYPE ADDR7_BIT ++#define MV_BOARD_MUX_I2C_ADDR_ENTRY 0x2 ++#define MV_BOARD_DIMM_I2C_CHANNEL 0x0 ++ ++#define BOOT_FLASH_INDEX 0 ++#define MAIN_FLASH_INDEX 1 ++ ++#define BOARD_ETH_START_PORT_NUM 0 ++ ++/* Supported clocks */ ++#define MV_BOARD_TCLK_100MHZ 100000000 ++#define MV_BOARD_TCLK_125MHZ 125000000 ++#define MV_BOARD_TCLK_133MHZ 133333333 ++#define MV_BOARD_TCLK_150MHZ 150000000 ++#define MV_BOARD_TCLK_166MHZ 166666667 ++#define MV_BOARD_TCLK_200MHZ 200000000 ++ ++#define MV_BOARD_SYSCLK_100MHZ 100000000 ++#define MV_BOARD_SYSCLK_125MHZ 125000000 ++#define MV_BOARD_SYSCLK_133MHZ 133333333 ++#define MV_BOARD_SYSCLK_150MHZ 150000000 ++#define MV_BOARD_SYSCLK_166MHZ 166666667 ++#define MV_BOARD_SYSCLK_200MHZ 200000000 ++#define MV_BOARD_SYSCLK_233MHZ 233333333 ++#define MV_BOARD_SYSCLK_250MHZ 250000000 ++#define MV_BOARD_SYSCLK_267MHZ 266666667 ++#define MV_BOARD_SYSCLK_300MHZ 300000000 ++#define MV_BOARD_SYSCLK_333MHZ 333333334 ++#define MV_BOARD_SYSCLK_400MHZ 400000000 ++ ++#define MV_BOARD_REFCLK_25MHZ 25000000 ++ ++/* Board specific */ ++/* =============================== */ ++ ++/* boards ID numbers */ ++ ++#define BOARD_ID_BASE 0x0 ++ ++/* New board ID numbers */ ++#define DB_88F6281A_BP_ID (BOARD_ID_BASE) ++#define DB_88F6281_BP_MLL_ID 1680 ++#define RD_88F6281A_ID (BOARD_ID_BASE+0x1) ++#define RD_88F6281_MLL_ID 1682 ++#define DB_88F6192A_BP_ID (BOARD_ID_BASE+0x2) ++#define RD_88F6192A_ID (BOARD_ID_BASE+0x3) ++#define RD_88F6192_MLL_ID 1681 ++#define DB_88F6180A_BP_ID (BOARD_ID_BASE+0x4) ++#define DB_88F6190A_BP_ID (BOARD_ID_BASE+0x5) ++#define RD_88F6190A_ID (BOARD_ID_BASE+0x6) ++#define RD_88F6281A_PCAC_ID (BOARD_ID_BASE+0x7) ++#define DB_CUSTOMER_ID (BOARD_ID_BASE+0x8) ++#define SHEEVA_PLUG_ID (BOARD_ID_BASE+0x9) ++#define MV_MAX_BOARD_ID (SHEEVA_PLUG_ID + 1) ++ ++/* DB-88F6281A-BP */ ++#if defined(MV_NAND) ++ #define DB_88F6281A_MPP0_7 0x21111111 ++#else ++ #define DB_88F6281A_MPP0_7 0x21112220 ++#endif ++#define DB_88F6281A_MPP8_15 0x11113311 ++#define DB_88F6281A_MPP16_23 0x00551111 ++#define DB_88F6281A_MPP24_31 0x00000000 ++#define DB_88F6281A_MPP32_39 0x00000000 ++#define DB_88F6281A_MPP40_47 0x00000000 ++#define DB_88F6281A_MPP48_55 0x00000000 ++#define DB_88F6281A_OE_LOW 0x0 ++#if defined(MV_TDM_5CHANNELS) ++ #define DB_88F6281A_OE_HIGH (BIT6) ++#else ++#define DB_88F6281A_OE_HIGH 0x0 ++#endif ++#define DB_88F6281A_OE_VAL_LOW 0x0 ++#define DB_88F6281A_OE_VAL_HIGH 0x0 ++ ++/* RD-88F6281A */ ++#if defined(MV_NAND) ++ #define RD_88F6281A_MPP0_7 0x21111111 ++#else ++ #define RD_88F6281A_MPP0_7 0x21112220 ++#endif ++#define RD_88F6281A_MPP8_15 0x11113311 ++#define RD_88F6281A_MPP16_23 0x33331111 ++#define RD_88F6281A_MPP24_31 0x33003333 ++#define RD_88F6281A_MPP32_39 0x20440533 ++#define RD_88F6281A_MPP40_47 0x22202222 ++#define RD_88F6281A_MPP48_55 0x00000002 ++#define RD_88F6281A_OE_LOW (BIT28 | BIT29) ++#define RD_88F6281A_OE_HIGH (BIT3 | BIT6 | BIT17) ++#define RD_88F6281A_OE_VAL_LOW 0x0 ++#define RD_88F6281A_OE_VAL_HIGH 0x0 ++ ++/* DB-88F6192A-BP */ ++#if defined(MV_NAND) ++ #define DB_88F6192A_MPP0_7 0x21111111 ++#else ++ #define DB_88F6192A_MPP0_7 0x21112220 ++#endif ++#define DB_88F6192A_MPP8_15 0x11113311 ++#define DB_88F6192A_MPP16_23 0x00501111 ++#define DB_88F6192A_MPP24_31 0x00000000 ++#define DB_88F6192A_MPP32_35 0x00000000 ++#define DB_88F6192A_OE_LOW (BIT22 | BIT23) ++#define DB_88F6192A_OE_HIGH 0x0 ++#define DB_88F6192A_OE_VAL_LOW 0x0 ++#define DB_88F6192A_OE_VAL_HIGH 0x0 ++ ++/* RD-88F6192A */ ++#define RD_88F6192A_MPP0_7 0x01222222 ++#define RD_88F6192A_MPP8_15 0x00000011 ++#define RD_88F6192A_MPP16_23 0x05550000 ++#define RD_88F6192A_MPP24_31 0x0 ++#define RD_88F6192A_MPP32_35 0x0 ++#define RD_88F6192A_OE_LOW (BIT11 | BIT14 | BIT24 | BIT25 | BIT26 | BIT27 | BIT30 | BIT31) ++#define RD_88F6192A_OE_HIGH (BIT0 | BIT2) ++#define RD_88F6192A_OE_VAL_LOW 0x18400 ++#define RD_88F6192A_OE_VAL_HIGH 0x8 ++ ++/* DB-88F6180A-BP */ ++#if defined(MV_NAND) ++ #define DB_88F6180A_MPP0_7 0x21111111 ++#else ++ #define DB_88F6180A_MPP0_7 0x01112222 ++#endif ++#define DB_88F6180A_MPP8_15 0x11113311 ++#define DB_88F6180A_MPP16_23 0x00001111 ++#define DB_88F6180A_MPP24_31 0x0 ++#define DB_88F6180A_MPP32_39 0x4444c000 ++#define DB_88F6180A_MPP40_44 0x00044444 ++#define DB_88F6180A_OE_LOW 0x0 ++#define DB_88F6180A_OE_HIGH 0x0 ++#define DB_88F6180A_OE_VAL_LOW 0x0 ++#define DB_88F6180A_OE_VAL_HIGH 0x0 ++ ++/* RD-88F6281A_PCAC */ ++#define RD_88F6281A_PCAC_MPP0_7 0x21111111 ++#define RD_88F6281A_PCAC_MPP8_15 0x00003311 ++#define RD_88F6281A_PCAC_MPP16_23 0x00001100 ++#define RD_88F6281A_PCAC_MPP24_31 0x00000000 ++#define RD_88F6281A_PCAC_MPP32_39 0x00000000 ++#define RD_88F6281A_PCAC_MPP40_47 0x00000000 ++#define RD_88F6281A_PCAC_MPP48_55 0x00000000 ++#define RD_88F6281A_PCAC_OE_LOW 0x0 ++#define RD_88F6281A_PCAC_OE_HIGH 0x0 ++#define RD_88F6281A_PCAC_OE_VAL_LOW 0x0 ++#define RD_88F6281A_PCAC_OE_VAL_HIGH 0x0 ++ ++/* SHEEVA PLUG */ ++#define RD_SHEEVA_PLUG_MPP0_7 0x01111111 ++#define RD_SHEEVA_PLUG_MPP8_15 0x11113322 ++#define RD_SHEEVA_PLUG_MPP16_23 0x00001111 ++#define RD_SHEEVA_PLUG_MPP24_31 0x00100000 ++#define RD_SHEEVA_PLUG_MPP32_39 0x00000000 ++#define RD_SHEEVA_PLUG_MPP40_47 0x00000000 ++#define RD_SHEEVA_PLUG_MPP48_55 0x00000000 ++#define RD_SHEEVA_PLUG_OE_LOW 0x0 ++#define RD_SHEEVA_PLUG_OE_HIGH 0x0 ++#define RD_SHEEVA_PLUG_OE_VAL_LOW (BIT29) ++#define RD_SHEEVA_PLUG_OE_VAL_HIGH ((~(BIT17 | BIT16 | BIT15)) | BIT14) ++ ++/* DB-CUSTOMER */ ++#define DB_CUSTOMER_MPP0_7 0x21111111 ++#define DB_CUSTOMER_MPP8_15 0x00003311 ++#define DB_CUSTOMER_MPP16_23 0x00001100 ++#define DB_CUSTOMER_MPP24_31 0x00000000 ++#define DB_CUSTOMER_MPP32_39 0x00000000 ++#define DB_CUSTOMER_MPP40_47 0x00000000 ++#define DB_CUSTOMER_MPP48_55 0x00000000 ++#define DB_CUSTOMER_OE_LOW 0x0 ++#define DB_CUSTOMER_OE_HIGH (~((BIT6) | (BIT7) | (BIT8) | (BIT9))) ++#define DB_CUSTOMER_OE_VAL_LOW 0x0 ++#define DB_CUSTOMER_OE_VAL_HIGH 0x0 ++ ++#endif /* __INCmvBoardEnvSpech */ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,320 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#include "cpu/mvCpu.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "ctrlEnv/mvCtrlEnvRegs.h" ++#include "ctrlEnv/sys/mvCpuIfRegs.h" ++ ++/* defines */ ++#ifdef MV_DEBUG ++ #define DB(x) x ++#else ++ #define DB(x) ++#endif ++ ++/* locals */ ++ ++/******************************************************************************* ++* mvCpuPclkGet - Get the CPU pClk (pipe clock) ++* ++* DESCRIPTION: ++* This routine extract the CPU core clock. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit clock cycles in MHertz. ++* ++*******************************************************************************/ ++/* 6180 have different clk reset sampling */ ++ ++static MV_U32 mvCpu6180PclkGet(MV_VOID) ++{ ++ MV_U32 tmpPClkRate=0; ++ MV_CPU_ARM_CLK cpu6180_ddr_l2_CLK[] = MV_CPU6180_DDR_L2_CLCK_TBL; ++ ++ tmpPClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); ++ tmpPClkRate = tmpPClkRate & MSAR_CPUCLCK_MASK_6180; ++ tmpPClkRate = tmpPClkRate >> MSAR_CPUCLCK_OFFS_6180; ++ ++ tmpPClkRate = cpu6180_ddr_l2_CLK[tmpPClkRate].cpuClk; ++ ++ return tmpPClkRate; ++} ++ ++ ++MV_U32 mvCpuPclkGet(MV_VOID) ++{ ++#if defined(PCLCK_AUTO_DETECT) ++ MV_U32 tmpPClkRate=0; ++ MV_U32 cpuCLK[] = MV_CPU_CLCK_TBL; ++ ++ if(mvCtrlModelGet() == MV_6180_DEV_ID) ++ return mvCpu6180PclkGet(); ++ ++ tmpPClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); ++ tmpPClkRate = MSAR_CPUCLCK_EXTRACT(tmpPClkRate); ++ tmpPClkRate = cpuCLK[tmpPClkRate]; ++ ++ return tmpPClkRate; ++#else ++ return MV_DEFAULT_PCLK ++#endif ++} ++ ++/******************************************************************************* ++* mvCpuL2ClkGet - Get the CPU L2 (CPU bus clock) ++* ++* DESCRIPTION: ++* This routine extract the CPU L2 clock. ++* ++* RETURN: ++* 32bit clock cycles in Hertz. ++* ++*******************************************************************************/ ++static MV_U32 mvCpu6180L2ClkGet(MV_VOID) ++{ ++ MV_U32 L2ClkRate=0; ++ MV_CPU_ARM_CLK _cpu6180_ddr_l2_CLK[] = MV_CPU6180_DDR_L2_CLCK_TBL; ++ ++ L2ClkRate = MV_REG_READ(MPP_SAMPLE_AT_RESET); ++ L2ClkRate = L2ClkRate & MSAR_CPUCLCK_MASK_6180; ++ L2ClkRate = L2ClkRate >> MSAR_CPUCLCK_OFFS_6180; ++ ++ L2ClkRate = _cpu6180_ddr_l2_CLK[L2ClkRate].l2Clk; ++ ++ return L2ClkRate; ++ ++} ++ ++MV_U32 mvCpuL2ClkGet(MV_VOID) ++{ ++#ifdef L2CLK_AUTO_DETECT ++ MV_U32 L2ClkRate, tmp, pClkRate, indexL2Rtio; ++ MV_U32 L2Rtio[][2] = MV_L2_CLCK_RTIO_TBL; ++ ++ if(mvCtrlModelGet() == MV_6180_DEV_ID) ++ return mvCpu6180L2ClkGet(); ++ ++ pClkRate = mvCpuPclkGet(); ++ ++ tmp = MV_REG_READ(MPP_SAMPLE_AT_RESET); ++ indexL2Rtio = MSAR_L2CLCK_EXTRACT(tmp); ++ ++ L2ClkRate = ((pClkRate * L2Rtio[indexL2Rtio][1]) / L2Rtio[indexL2Rtio][0]); ++ ++ return L2ClkRate; ++#else ++ return MV_BOARD_DEFAULT_L2CLK; ++#endif ++} ++ ++ ++/******************************************************************************* ++* mvCpuNameGet - Get CPU name ++* ++* DESCRIPTION: ++* This function returns a string describing the CPU model and revision. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* pNameBuff - Buffer to contain board name string. Minimum size 32 chars. ++* ++* RETURN: ++* None. ++*******************************************************************************/ ++MV_VOID mvCpuNameGet(char *pNameBuff) ++{ ++ MV_U32 cpuModel; ++ ++ cpuModel = mvOsCpuPartGet(); ++ ++ /* The CPU module is indicated in the Processor Version Register (PVR) */ ++ switch(cpuModel) ++ { ++ case CPU_PART_MRVL131: ++ mvOsSPrintf(pNameBuff, "%s (Rev %d)", "Marvell Feroceon",mvOsCpuRevGet()); ++ break; ++ case CPU_PART_ARM926: ++ mvOsSPrintf(pNameBuff, "%s (Rev %d)", "ARM926",mvOsCpuRevGet()); ++ break; ++ case CPU_PART_ARM946: ++ mvOsSPrintf(pNameBuff, "%s (Rev %d)", "ARM946",mvOsCpuRevGet()); ++ break; ++ default: ++ mvOsSPrintf(pNameBuff,"??? (0x%04x) (Rev %d)",cpuModel,mvOsCpuRevGet()); ++ break; ++ } /* switch */ ++ ++ return; ++} ++ ++ ++#define MV_PROC_STR_SIZE 50 ++ ++static void mvCpuIfGetL2EccMode(MV_8 *buf) ++{ ++ MV_U32 regVal = MV_REG_READ(CPU_L2_CONFIG_REG); ++ if (regVal & BIT2) ++ mvOsSPrintf(buf, "L2 ECC Enabled"); ++ else ++ mvOsSPrintf(buf, "L2 ECC Disabled"); ++} ++ ++static void mvCpuIfGetL2Mode(MV_8 *buf) ++{ ++ MV_U32 regVal = 0; ++ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ ++ if (regVal & BIT22) ++ mvOsSPrintf(buf, "L2 Enabled"); ++ else ++ mvOsSPrintf(buf, "L2 Disabled"); ++} ++ ++static void mvCpuIfGetL2PrefetchMode(MV_8 *buf) ++{ ++ MV_U32 regVal = 0; ++ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ ++ if (regVal & BIT24) ++ mvOsSPrintf(buf, "L2 Prefetch Disabled"); ++ else ++ mvOsSPrintf(buf, "L2 Prefetch Enabled"); ++} ++ ++static void mvCpuIfGetWriteAllocMode(MV_8 *buf) ++{ ++ MV_U32 regVal = 0; ++ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ ++ if (regVal & BIT28) ++ mvOsSPrintf(buf, "Write Allocate Enabled"); ++ else ++ mvOsSPrintf(buf, "Write Allocate Disabled"); ++} ++ ++static void mvCpuIfGetCpuStreamMode(MV_8 *buf) ++{ ++ MV_U32 regVal = 0; ++ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ ++ if (regVal & BIT29) ++ mvOsSPrintf(buf, "CPU Streaming Enabled"); ++ else ++ mvOsSPrintf(buf, "CPU Streaming Disabled"); ++} ++ ++static void mvCpuIfPrintCpuRegs(void) ++{ ++ MV_U32 regVal = 0; ++ ++ __asm volatile ("mrc p15, 1, %0, c15, c1, 0" : "=r" (regVal)); /* Read Marvell extra features register */ ++ mvOsPrintf("Extra Feature Reg = 0x%x\n",regVal); ++ ++ __asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (regVal)); /* Read Control register */ ++ mvOsPrintf("Control Reg = 0x%x\n",regVal); ++ ++ __asm volatile ("mrc p15, 0, %0, c0, c0, 0" : "=r" (regVal)); /* Read ID Code register */ ++ mvOsPrintf("ID Code Reg = 0x%x\n",regVal); ++ ++ __asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=r" (regVal)); /* Read Cache Type register */ ++ mvOsPrintf("Cache Type Reg = 0x%x\n",regVal); ++ ++} ++ ++MV_U32 mvCpuIfPrintSystemConfig(MV_8 *buffer, MV_U32 index) ++{ ++ MV_U32 count = 0; ++ ++ MV_8 L2_ECC_str[MV_PROC_STR_SIZE]; ++ MV_8 L2_En_str[MV_PROC_STR_SIZE]; ++ MV_8 L2_Prefetch_str[MV_PROC_STR_SIZE]; ++ MV_8 Write_Alloc_str[MV_PROC_STR_SIZE]; ++ MV_8 Cpu_Stream_str[MV_PROC_STR_SIZE]; ++ ++ mvCpuIfGetL2Mode(L2_En_str); ++ mvCpuIfGetL2EccMode(L2_ECC_str); ++ mvCpuIfGetL2PrefetchMode(L2_Prefetch_str); ++ mvCpuIfGetWriteAllocMode(Write_Alloc_str); ++ mvCpuIfGetCpuStreamMode(Cpu_Stream_str); ++ mvCpuIfPrintCpuRegs(); ++ ++ count += mvOsSPrintf(buffer + count + index, "%s\n", L2_En_str); ++ count += mvOsSPrintf(buffer + count + index, "%s\n", L2_ECC_str); ++ count += mvOsSPrintf(buffer + count + index, "%s\n", L2_Prefetch_str); ++ count += mvOsSPrintf(buffer + count + index, "%s\n", Write_Alloc_str); ++ count += mvOsSPrintf(buffer + count + index, "%s\n", Cpu_Stream_str); ++ return count; ++} ++ ++MV_U32 whoAmI(MV_VOID) ++{ ++ return 0; ++} ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/cpu/mvCpu.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,99 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvCpuh ++#define __INCmvCpuh ++ ++#include "mvCommon.h" ++#include "mvOs.h" ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++ ++/* defines */ ++#define CPU_PART_MRVL131 0x131 ++#define CPU_PART_ARM926 0x926 ++#define CPU_PART_ARM946 0x946 ++#define MV_CPU_ARM_CLK_ELM_SIZE 12 ++#define MV_CPU_ARM_CLK_RATIO_OFF 8 ++#define MV_CPU_ARM_CLK_DDR_OFF 4 ++ ++#ifndef MV_ASMLANGUAGE ++typedef struct _mvCpuArmClk ++{ ++ MV_U32 cpuClk; /* CPU clock in MHz */ ++ MV_U32 ddrClk; /* DDR clock in MHz */ ++ MV_U32 l2Clk; /* CPU DDR clock ratio */ ++ ++}MV_CPU_ARM_CLK; ++ ++MV_U32 mvCpuPclkGet(MV_VOID); ++MV_VOID mvCpuNameGet(char *pNameBuff); ++MV_U32 mvCpuL2ClkGet(MV_VOID); ++MV_U32 mvCpuIfPrintSystemConfig(MV_8 *buffer, MV_U32 index); ++MV_U32 whoAmI(MV_VOID); ++ ++#endif /* MV_ASMLANGUAGE */ ++ ++ ++#endif /* __INCmvCpuh */ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,296 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++/******************************************************************************* ++* mvCtrlEnvAddrDec.h - Marvell controller address decode library ++* ++* DESCRIPTION: ++* ++* DEPENDENCIES: ++* None. ++* ++*******************************************************************************/ ++ ++/* includes */ ++#include "ctrlEnv/mvCtrlEnvAddrDec.h" ++#include "ctrlEnv/sys/mvAhbToMbusRegs.h" ++#include "ddr2/mvDramIfRegs.h" ++#include "pex/mvPexRegs.h" ++ ++#define MV_DEBUG ++ ++/* defines */ ++#ifdef MV_DEBUG ++ #define DB(x) x ++#else ++ #define DB(x) ++#endif ++ ++/* Default Attributes array */ ++MV_TARGET_ATTRIB mvTargetDefaultsArray[] = TARGETS_DEF_ARRAY; ++extern MV_TARGET *sampleAtResetTargetArray; ++/* Dram\AHBToMbus\PEX share regsiter */ ++ ++#define CTRL_DEC_BASE_OFFS 16 ++#define CTRL_DEC_BASE_MASK (0xffff << CTRL_DEC_BASE_OFFS) ++#define CTRL_DEC_BASE_ALIGNMENT 0x10000 ++ ++#define CTRL_DEC_SIZE_OFFS 16 ++#define CTRL_DEC_SIZE_MASK (0xffff << CTRL_DEC_SIZE_OFFS) ++#define CTRL_DEC_SIZE_ALIGNMENT 0x10000 ++ ++#define CTRL_DEC_WIN_EN BIT0 ++ ++ ++ ++/******************************************************************************* ++* mvCtrlAddrDecToReg - Get address decode register format values ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_STATUS mvCtrlAddrDecToReg(MV_ADDR_WIN *pAddrDecWin, MV_DEC_REGS *pAddrDecRegs) ++{ ++ ++ MV_U32 baseToReg=0 , sizeToReg=0; ++ ++ /* BaseLow[31:16] => base register [31:16] */ ++ baseToReg = pAddrDecWin->baseLow & CTRL_DEC_BASE_MASK; ++ ++ /* Write to address decode Base Address Register */ ++ pAddrDecRegs->baseReg &= ~CTRL_DEC_BASE_MASK; ++ pAddrDecRegs->baseReg |= baseToReg; ++ ++ /* Get size register value according to window size */ ++ sizeToReg = ctrlSizeToReg(pAddrDecWin->size, CTRL_DEC_SIZE_ALIGNMENT); ++ ++ /* Size parameter validity check. */ ++ if (-1 == sizeToReg) ++ { ++ return MV_BAD_PARAM; ++ } ++ ++ /* set size */ ++ pAddrDecRegs->sizeReg &= ~CTRL_DEC_SIZE_MASK; ++ pAddrDecRegs->sizeReg |= (sizeToReg << CTRL_DEC_SIZE_OFFS); ++ ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvCtrlRegToAddrDec - Extract address decode struct from registers. ++* ++* DESCRIPTION: ++* This function extract address decode struct from address decode ++* registers given as parameters. ++* ++* INPUT: ++* pAddrDecRegs - Address decode register struct. ++* ++* OUTPUT: ++* pAddrDecWin - Target window data structure. ++* ++* RETURN: ++* MV_BAD_PARAM if address decode registers data is invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvCtrlRegToAddrDec(MV_DEC_REGS *pAddrDecRegs, MV_ADDR_WIN *pAddrDecWin) ++{ ++ MV_U32 sizeRegVal; ++ ++ sizeRegVal = (pAddrDecRegs->sizeReg & CTRL_DEC_SIZE_MASK) >> ++ CTRL_DEC_SIZE_OFFS; ++ ++ pAddrDecWin->size = ctrlRegToSize(sizeRegVal, CTRL_DEC_SIZE_ALIGNMENT); ++ ++ ++ /* Extract base address */ ++ /* Base register [31:16] ==> baseLow[31:16] */ ++ pAddrDecWin->baseLow = pAddrDecRegs->baseReg & CTRL_DEC_BASE_MASK; ++ ++ pAddrDecWin->baseHigh = 0; ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvCtrlAttribGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++* ++*******************************************************************************/ ++ ++MV_STATUS mvCtrlAttribGet(MV_TARGET target, ++ MV_TARGET_ATTRIB *targetAttrib) ++{ ++ ++ targetAttrib->attrib = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].attrib; ++ targetAttrib->targetId = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId; ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvCtrlGetAttrib - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_TARGET mvCtrlTargetGet(MV_TARGET_ATTRIB *targetAttrib) ++{ ++ MV_TARGET target; ++ MV_TARGET x; ++ for (target = SDRAM_CS0; target < MAX_TARGETS ; target ++) ++ { ++ x = MV_CHANGE_BOOT_CS(target); ++ if ((mvTargetDefaultsArray[x].attrib == targetAttrib->attrib) && ++ (mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(target)].targetId == targetAttrib->targetId)) ++ { ++ /* found it */ ++ break; ++ } ++ } ++ ++ return target; ++} ++ ++MV_STATUS mvCtrlAddrDecToParams(MV_DEC_WIN *pAddrDecWin, ++ MV_DEC_WIN_PARAMS *pWinParam) ++{ ++ MV_U32 baseToReg=0, sizeToReg=0; ++ ++ /* BaseLow[31:16] => base register [31:16] */ ++ baseToReg = pAddrDecWin->addrWin.baseLow & CTRL_DEC_BASE_MASK; ++ ++ /* Write to address decode Base Address Register */ ++ pWinParam->baseAddr &= ~CTRL_DEC_BASE_MASK; ++ pWinParam->baseAddr |= baseToReg; ++ ++ /* Get size register value according to window size */ ++ sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, CTRL_DEC_SIZE_ALIGNMENT); ++ ++ /* Size parameter validity check. */ ++ if (-1 == sizeToReg) ++ { ++ mvOsPrintf("mvCtrlAddrDecToParams: ERR. ctrlSizeToReg failed.\n"); ++ return MV_BAD_PARAM; ++ } ++ pWinParam->size = sizeToReg; ++ ++ pWinParam->attrib = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(pAddrDecWin->target)].attrib; ++ pWinParam->targetId = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(pAddrDecWin->target)].targetId; ++ ++ return MV_OK; ++} ++ ++MV_STATUS mvCtrlParamsToAddrDec(MV_DEC_WIN_PARAMS *pWinParam, ++ MV_DEC_WIN *pAddrDecWin) ++{ ++ MV_TARGET_ATTRIB targetAttrib; ++ ++ pAddrDecWin->addrWin.baseLow = pWinParam->baseAddr; ++ ++ /* Upper 32bit address base is supported under PCI High Address remap */ ++ pAddrDecWin->addrWin.baseHigh = 0; ++ ++ /* Prepare sizeReg to ctrlRegToSize function */ ++ pAddrDecWin->addrWin.size = ctrlRegToSize(pWinParam->size, CTRL_DEC_SIZE_ALIGNMENT); ++ ++ if (-1 == pAddrDecWin->addrWin.size) ++ { ++ DB(mvOsPrintf("mvCtrlParamsToAddrDec: ERR. ctrlRegToSize failed.\n")); ++ return MV_BAD_PARAM; ++ } ++ targetAttrib.targetId = pWinParam->targetId; ++ targetAttrib.attrib = pWinParam->attrib; ++ ++ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); ++ ++ return MV_OK; ++} ++ ++ ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAddrDec.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,203 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvCtrlEnvAddrDech ++#define __INCmvCtrlEnvAddrDech ++ ++/* includes */ ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "ctrlEnv/mvCtrlEnvRegs.h" ++ ++ ++/* defines */ ++/* DUnit attributes */ ++#define ATMWCR_WIN_DUNIT_CS0_OFFS 0 ++#define ATMWCR_WIN_DUNIT_CS0_MASK BIT0 ++#define ATMWCR_WIN_DUNIT_CS0_REQ (0 << ATMWCR_WIN_DUNIT_CS0_OFFS) ++ ++#define ATMWCR_WIN_DUNIT_CS1_OFFS 1 ++#define ATMWCR_WIN_DUNIT_CS1_MASK BIT1 ++#define ATMWCR_WIN_DUNIT_CS1_REQ (0 << ATMWCR_WIN_DUNIT_CS1_OFFS) ++ ++#define ATMWCR_WIN_DUNIT_CS2_OFFS 2 ++#define ATMWCR_WIN_DUNIT_CS2_MASK BIT2 ++#define ATMWCR_WIN_DUNIT_CS2_REQ (0 << ATMWCR_WIN_DUNIT_CS2_OFFS) ++ ++#define ATMWCR_WIN_DUNIT_CS3_OFFS 3 ++#define ATMWCR_WIN_DUNIT_CS3_MASK BIT3 ++#define ATMWCR_WIN_DUNIT_CS3_REQ (0 << ATMWCR_WIN_DUNIT_CS3_OFFS) ++ ++/* RUnit (Device) attributes */ ++#define ATMWCR_WIN_RUNIT_DEVCS0_OFFS 0 ++#define ATMWCR_WIN_RUNIT_DEVCS0_MASK BIT0 ++#define ATMWCR_WIN_RUNIT_DEVCS0_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS0_OFFS) ++ ++#define ATMWCR_WIN_RUNIT_DEVCS1_OFFS 1 ++#define ATMWCR_WIN_RUNIT_DEVCS1_MASK BIT1 ++#define ATMWCR_WIN_RUNIT_DEVCS1_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS1_OFFS) ++ ++#define ATMWCR_WIN_RUNIT_DEVCS2_OFFS 2 ++#define ATMWCR_WIN_RUNIT_DEVCS2_MASK BIT2 ++#define ATMWCR_WIN_RUNIT_DEVCS2_REQ (0 << ATMWCR_WIN_RUNIT_DEVCS2_OFFS) ++ ++#define ATMWCR_WIN_RUNIT_BOOTCS_OFFS 4 ++#define ATMWCR_WIN_RUNIT_BOOTCS_MASK BIT4 ++#define ATMWCR_WIN_RUNIT_BOOTCS_REQ (0 << ATMWCR_WIN_RUNIT_BOOTCS_OFFS) ++ ++/* LMaster (PCI) attributes */ ++#define ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS 0 ++#define ATMWCR_WIN_LUNIT_BYTE_SWP_MASK BIT0 ++#define ATMWCR_WIN_LUNIT_BYTE_SWP (0 << ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS) ++#define ATMWCR_WIN_LUNIT_BYTE_NO_SWP (1 << ATMWCR_WIN_LUNIT_BYTE_SWP_OFFS) ++ ++ ++#define ATMWCR_WIN_LUNIT_WORD_SWP_OFFS 1 ++#define ATMWCR_WIN_LUNIT_WORD_SWP_MASK BIT1 ++#define ATMWCR_WIN_LUNIT_WORD_SWP (0 << ATMWCR_WIN_LUNIT_WORD_SWP_OFFS) ++#define ATMWCR_WIN_LUNIT_WORD_NO_SWP (1 << ATMWCR_WIN_LUNIT_WORD_SWP_OFFS) ++ ++#define ATMWCR_WIN_LUNIT_NO_SNOOP BIT2 ++ ++#define ATMWCR_WIN_LUNIT_TYPE_OFFS 3 ++#define ATMWCR_WIN_LUNIT_TYPE_MASK BIT3 ++#define ATMWCR_WIN_LUNIT_TYPE_IO (0 << ATMWCR_WIN_LUNIT_TYPE_OFFS) ++#define ATMWCR_WIN_LUNIT_TYPE_MEM (1 << ATMWCR_WIN_LUNIT_TYPE_OFFS) ++ ++#define ATMWCR_WIN_LUNIT_FORCE64_OFFS 4 ++#define ATMWCR_WIN_LUNIT_FORCE64_MASK BIT4 ++#define ATMWCR_WIN_LUNIT_FORCE64 (0 << ATMWCR_WIN_LUNIT_FORCE64_OFFS) ++ ++#define ATMWCR_WIN_LUNIT_ORDERING_OFFS 6 ++#define ATMWCR_WIN_LUNIT_ORDERING_MASK BIT6 ++#define ATMWCR_WIN_LUNIT_ORDERING (1 << ATMWCR_WIN_LUNIT_FORCE64_OFFS) ++ ++/* PEX Attributes */ ++#define ATMWCR_WIN_PEX_TYPE_OFFS 3 ++#define ATMWCR_WIN_PEX_TYPE_MASK BIT3 ++#define ATMWCR_WIN_PEX_TYPE_IO (0 << ATMWCR_WIN_PEX_TYPE_OFFS) ++#define ATMWCR_WIN_PEX_TYPE_MEM (1 << ATMWCR_WIN_PEX_TYPE_OFFS) ++ ++/* typedefs */ ++ ++/* Unsupported attributes for address decode: */ ++/* 2) PCI0/1_REQ64n control */ ++ ++typedef struct _mvDecRegs ++{ ++ MV_U32 baseReg; ++ MV_U32 baseRegHigh; ++ MV_U32 sizeReg; ++ ++}MV_DEC_REGS; ++ ++typedef struct _mvTargetAttrib ++{ ++ MV_U8 attrib; /* chip select attributes */ ++ MV_TARGET_ID targetId; /* Target Id of this MV_TARGET */ ++ ++}MV_TARGET_ATTRIB; ++ ++ ++/* This structure describes address decode window */ ++typedef struct _mvDecWin ++{ ++ MV_TARGET target; /* Target for addr decode window */ ++ MV_ADDR_WIN addrWin; /* Address window of target */ ++ MV_BOOL enable; /* Window enable/disable */ ++}MV_DEC_WIN; ++ ++typedef struct _mvDecWinParams ++{ ++ MV_TARGET_ID targetId; /* Target ID field */ ++ MV_U8 attrib; /* Attribute field */ ++ MV_U32 baseAddr; /* Base address in register format */ ++ MV_U32 size; /* Size in register format */ ++}MV_DEC_WIN_PARAMS; ++ ++ ++/* mvCtrlEnvAddrDec API list */ ++ ++MV_STATUS mvCtrlAddrDecToReg(MV_ADDR_WIN *pAddrDecWin, ++ MV_DEC_REGS *pAddrDecRegs); ++ ++MV_STATUS mvCtrlRegToAddrDec(MV_DEC_REGS *pAddrDecRegs, ++ MV_ADDR_WIN *pAddrDecWin); ++ ++MV_STATUS mvCtrlAttribGet(MV_TARGET target, ++ MV_TARGET_ATTRIB *targetAttrib); ++ ++MV_TARGET mvCtrlTargetGet(MV_TARGET_ATTRIB *targetAttrib); ++ ++ ++MV_STATUS mvCtrlAddrDecToParams(MV_DEC_WIN *pAddrDecWin, ++ MV_DEC_WIN_PARAMS *pWinParam); ++ ++MV_STATUS mvCtrlParamsToAddrDec(MV_DEC_WIN_PARAMS *pWinParam, ++ MV_DEC_WIN *pAddrDecWin); ++ ++ ++ ++ ++#endif /* __INCmvCtrlEnvAddrDech */ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvAsm.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,98 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvCtrlEnvAsmh ++#define __INCmvCtrlEnvAsmh ++#include "pex/mvPexRegs.h" ++ ++#define CHIP_BOND_REG 0x10034 ++#define PCKG_OPT_MASK_AS #3 ++#define PXCCARI_REVID_MASK_AS #PXCCARI_REVID_MASK ++ ++/* Read device ID into toReg bits 15:0 from 0xd0000000 */ ++/* defines */ ++#define MV_DV_CTRL_MODEL_GET_ASM(toReg, tmpReg) \ ++ MV_DV_REG_READ_ASM(toReg, tmpReg, CHIP_BOND_REG);\ ++ and toReg, toReg, PCKG_OPT_MASK_AS /* Mask for package ID */ ++ ++/* Read device ID into toReg bits 15:0 from 0xf1000000*/ ++#define MV_CTRL_MODEL_GET_ASM(toReg, tmpReg) \ ++ MV_REG_READ_ASM(toReg, tmpReg, CHIP_BOND_REG);\ ++ and toReg, toReg, PCKG_OPT_MASK_AS /* Mask for package ID */ ++ ++/* Read Revision into toReg bits 7:0 0xd0000000*/ ++#define MV_DV_CTRL_REV_GET_ASM(toReg, tmpReg) \ ++ /* Read device revision */ \ ++ MV_DV_REG_READ_ASM(toReg, tmpReg, PEX_CFG_DIRECT_ACCESS(0,PEX_CLASS_CODE_AND_REVISION_ID));\ ++ and toReg, toReg, PXCCARI_REVID_MASK_AS /* Mask for calss ID */ ++ ++/* Read Revision into toReg bits 7:0 0xf1000000*/ ++#define MV_CTRL_REV_GET_ASM(toReg, tmpReg) \ ++ /* Read device revision */ \ ++ MV_REG_READ_ASM(toReg, tmpReg, PEX_CFG_DIRECT_ACCESS(0,PEX_CLASS_CODE_AND_REVISION_ID));\ ++ and toReg, toReg, PXCCARI_REVID_MASK_AS /* Mask for calss ID */ ++ ++ ++#endif /* __INCmvCtrlEnvAsmh */ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,1825 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++/* includes */ ++#include "mvCommon.h" ++#include "mvCtrlEnvLib.h" ++#include "ctrlEnv/sys/mvCpuIf.h" ++ ++#if defined(MV_INCLUDE_PEX) ++#include "pex/mvPex.h" ++#include "ctrlEnv/sys/mvSysPex.h" ++#endif ++ ++#if defined(MV_INCLUDE_GIG_ETH) ++#include "ctrlEnv/sys/mvSysGbe.h" ++#endif ++ ++#if defined(MV_INCLUDE_XOR) ++#include "ctrlEnv/sys/mvSysXor.h" ++#endif ++ ++#if defined(MV_INCLUDE_SATA) ++#include "ctrlEnv/sys/mvSysSata.h" ++#endif ++ ++#if defined(MV_INCLUDE_USB) ++#include "ctrlEnv/sys/mvSysUsb.h" ++#endif ++ ++#if defined(MV_INCLUDE_AUDIO) ++#include "ctrlEnv/sys/mvSysAudio.h" ++#endif ++ ++#if defined(MV_INCLUDE_CESA) ++#include "ctrlEnv/sys/mvSysCesa.h" ++#endif ++ ++#if defined(MV_INCLUDE_TS) ++#include "ctrlEnv/sys/mvSysTs.h" ++#endif ++ ++/* defines */ ++#ifdef MV_DEBUG ++ #define DB(x) x ++#else ++ #define DB(x) ++#endif ++ ++/******************************************************************************* ++* mvCtrlEnvInit - Initialize Marvell controller environment. ++* ++* DESCRIPTION: ++* This function get environment information and initialize controller ++* internal/external environment. For example ++* 1) MPP settings according to board MPP macros. ++* NOTE: It is the user responsibility to shut down all DMA channels ++* in device and disable controller sub units interrupts during ++* boot process. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_STATUS mvCtrlEnvInit(MV_VOID) ++{ ++ MV_U32 mppGroup; ++ MV_U32 devId; ++ MV_U32 boardId; ++ MV_U32 i; ++ MV_U32 maxMppGrp = 1; ++ MV_U32 mppVal = 0; ++ MV_U32 bootVal = 0; ++ MV_U32 mppGroupType = 0; ++ MV_U32 mppGroup1[][3] = MPP_GROUP_1_TYPE; ++ MV_U32 mppGroup2[][3] = MPP_GROUP_2_TYPE; ++ ++ devId = mvCtrlModelGet(); ++ boardId= mvBoardIdGet(); ++ ++ switch(devId){ ++ case MV_6281_DEV_ID: ++ maxMppGrp = MV_6281_MPP_MAX_GROUP; ++ break; ++ case MV_6192_DEV_ID: ++ maxMppGrp = MV_6192_MPP_MAX_GROUP; ++ break; ++ case MV_6190_DEV_ID: ++ maxMppGrp = MV_6190_MPP_MAX_GROUP; ++ break; ++ case MV_6180_DEV_ID: ++ maxMppGrp = MV_6180_MPP_MAX_GROUP; ++ break; ++ } ++ ++ /* MPP Init */ ++ /* We split mpp init to 3 phases: ++ * 1. We init mpp[19:0] from the board info. mpp[23:20] will be over write ++ * in phase 2. ++ * 2. We detect the mpp group type and according the mpp values [35:20]. ++ * 3. We detect the mpp group type and according the mpp values [49:36]. ++ */ ++ /* Mpp phase 1 mpp[19:0] */ ++ /* Read MPP group from board level and assign to MPP register */ ++ for (mppGroup = 0; mppGroup < 3; mppGroup++) ++ { ++ mppVal = mvBoardMppGet(mppGroup); ++ if (mppGroup == 0) ++ { ++ bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); ++ if (mvCtrlIsBootFromSPI()) ++ { ++ mppVal &= ~0xffff; ++ bootVal &= 0xffff; ++ mppVal |= bootVal; ++ } ++ else if (mvCtrlIsBootFromSPIUseNAND()) ++ { ++ mppVal &= ~0xf0000000; ++ bootVal &= 0xf0000000; ++ mppVal |= bootVal; ++ } ++ else if (mvCtrlIsBootFromNAND()) ++ { ++ mppVal &= ~0xffffff; ++ bootVal &= 0xffffff; ++ mppVal |= bootVal; ++ } ++ } ++ ++ if (mppGroup == 2) ++ { ++ bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); ++ if (mvCtrlIsBootFromNAND()) ++ { ++ mppVal &= ~0xff00; ++ bootVal &= 0xff00; ++ mppVal |= bootVal; ++ } ++ } ++ ++ MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal); ++ } ++ ++ /* Identify MPPs group */ ++ mvBoardMppGroupIdUpdate(); ++ ++ /* Update MPPs mux relevent only on Marvell DB */ ++ if ((boardId == DB_88F6281A_BP_ID) || ++ (boardId == DB_88F6180A_BP_ID)) ++ mvBoardMppMuxSet(); ++ ++ mppGroupType = mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_1); ++ ++ /* Mpp phase 2 */ ++ /* Read MPP group from board level and assign to MPP register */ ++ if (devId != MV_6180_DEV_ID) ++ { ++ i = 0; ++ for (mppGroup = 2; mppGroup < 5; mppGroup++) ++ { ++ if ((mppGroupType == MV_BOARD_OTHER) || ++ (boardId == RD_88F6281A_ID) || ++ (boardId == RD_88F6192A_ID) || ++ (boardId == RD_88F6190A_ID) || ++ (boardId == RD_88F6281A_PCAC_ID) || ++ (boardId == SHEEVA_PLUG_ID)) ++ mppVal = mvBoardMppGet(mppGroup); ++ else ++ { ++ mppVal = mppGroup1[mppGroupType][i]; ++ i++; ++ } ++ ++ /* Group 2 is shared mpp[23:16] */ ++ if (mppGroup == 2) ++ { ++ bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); ++ mppVal &= ~0xffff; ++ bootVal &= 0xffff; ++ mppVal |= bootVal; ++ } ++ ++ MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal); ++ } ++ } ++ ++ if ((devId == MV_6192_DEV_ID) || (devId == MV_6190_DEV_ID)) ++ return MV_OK; ++ ++ /* Mpp phase 3 */ ++ mppGroupType = mvBoardMppGroupTypeGet(MV_BOARD_MPP_GROUP_2); ++ /* Read MPP group from board level and assign to MPP register */ ++ i = 0; ++ for (mppGroup = 4; mppGroup < 7; mppGroup++) ++ { ++ if ((mppGroupType == MV_BOARD_OTHER) || ++ (boardId == RD_88F6281A_ID) || ++ (boardId == RD_88F6281A_PCAC_ID) || ++ (boardId == SHEEVA_PLUG_ID)) ++ mppVal = mvBoardMppGet(mppGroup); ++ else ++ { ++ mppVal = mppGroup2[mppGroupType][i]; ++ i++; ++ } ++ ++ /* Group 4 is shared mpp[35:32] */ ++ if (mppGroup == 4) ++ { ++ bootVal = MV_REG_READ(mvCtrlMppRegGet(mppGroup)); ++ mppVal &= ~0xffff; ++ bootVal &= 0xffff; ++ mppVal |= bootVal; ++ } ++ ++ MV_REG_WRITE(mvCtrlMppRegGet(mppGroup), mppVal); ++ } ++ /* Update SSCG configuration register*/ ++ if(mvBoardIdGet() == DB_88F6281A_BP_ID || mvBoardIdGet() == DB_88F6192A_BP_ID || ++ mvBoardIdGet() == DB_88F6190A_BP_ID || mvBoardIdGet() == DB_88F6180A_BP_ID) ++ MV_REG_WRITE(0x100d8, 0x53); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCtrlMppRegGet - return reg address of mpp group ++* ++* DESCRIPTION: ++* ++* INPUT: ++* mppGroup - MPP group. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_U32 - Register address. ++* ++*******************************************************************************/ ++MV_U32 mvCtrlMppRegGet(MV_U32 mppGroup) ++{ ++ MV_U32 ret; ++ ++ switch(mppGroup){ ++ case (0): ret = MPP_CONTROL_REG0; ++ break; ++ case (1): ret = MPP_CONTROL_REG1; ++ break; ++ case (2): ret = MPP_CONTROL_REG2; ++ break; ++ case (3): ret = MPP_CONTROL_REG3; ++ break; ++ case (4): ret = MPP_CONTROL_REG4; ++ break; ++ case (5): ret = MPP_CONTROL_REG5; ++ break; ++ case (6): ret = MPP_CONTROL_REG6; ++ break; ++ default: ret = MPP_CONTROL_REG0; ++ break; ++ } ++ return ret; ++} ++#if defined(MV_INCLUDE_PEX) ++/******************************************************************************* ++* mvCtrlPexMaxIfGet - Get Marvell controller number of PEX interfaces. ++* ++* DESCRIPTION: ++* This function returns Marvell controller number of PEX interfaces. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Marvell controller number of PEX interfaces. If controller ++* ID is undefined the function returns '0'. ++* ++*******************************************************************************/ ++MV_U32 mvCtrlPexMaxIfGet(MV_VOID) ++{ ++ ++ return MV_PEX_MAX_IF; ++} ++#endif ++ ++#if defined(MV_INCLUDE_GIG_ETH) ++/******************************************************************************* ++* mvCtrlEthMaxPortGet - Get Marvell controller number of etherent ports. ++* ++* DESCRIPTION: ++* This function returns Marvell controller number of etherent port. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Marvell controller number of etherent port. ++* ++*******************************************************************************/ ++MV_U32 mvCtrlEthMaxPortGet(MV_VOID) ++{ ++ MV_U32 devId; ++ ++ devId = mvCtrlModelGet(); ++ ++ switch(devId){ ++ case MV_6281_DEV_ID: ++ return MV_6281_ETH_MAX_PORTS; ++ break; ++ case MV_6192_DEV_ID: ++ return MV_6192_ETH_MAX_PORTS; ++ break; ++ case MV_6190_DEV_ID: ++ return MV_6190_ETH_MAX_PORTS; ++ break; ++ case MV_6180_DEV_ID: ++ return MV_6180_ETH_MAX_PORTS; ++ break; ++ } ++ return 0; ++ ++} ++#endif ++ ++#if defined(MV_INCLUDE_XOR) ++/******************************************************************************* ++* mvCtrlXorMaxChanGet - Get Marvell controller number of XOR channels. ++* ++* DESCRIPTION: ++* This function returns Marvell controller number of XOR channels. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Marvell controller number of XOR channels. ++* ++*******************************************************************************/ ++MV_U32 mvCtrlXorMaxChanGet(MV_VOID) ++{ ++ return MV_XOR_MAX_CHAN; ++} ++#endif ++ ++#if defined(MV_INCLUDE_USB) ++/******************************************************************************* ++* mvCtrlUsbHostMaxGet - Get number of Marvell Usb controllers ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* returns number of Marvell USB controllers. ++* ++*******************************************************************************/ ++MV_U32 mvCtrlUsbMaxGet(void) ++{ ++ return MV_USB_MAX_PORTS; ++} ++#endif ++ ++ ++#if defined(MV_INCLUDE_NAND) ++/******************************************************************************* ++* mvCtrlNandSupport - Return if this controller has integrated NAND flash support ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if NAND is supported and MV_FALSE otherwise ++* ++*******************************************************************************/ ++MV_U32 mvCtrlNandSupport(MV_VOID) ++{ ++ MV_U32 devId; ++ ++ devId = mvCtrlModelGet(); ++ ++ switch(devId){ ++ case MV_6281_DEV_ID: ++ return MV_6281_NAND; ++ break; ++ case MV_6192_DEV_ID: ++ return MV_6192_NAND; ++ break; ++ case MV_6190_DEV_ID: ++ return MV_6190_NAND; ++ break; ++ case MV_6180_DEV_ID: ++ return MV_6180_NAND; ++ break; ++ } ++ return 0; ++ ++} ++#endif ++ ++#if defined(MV_INCLUDE_SDIO) ++/******************************************************************************* ++* mvCtrlSdioSupport - Return if this controller has integrated SDIO flash support ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if SDIO is supported and MV_FALSE otherwise ++* ++*******************************************************************************/ ++MV_U32 mvCtrlSdioSupport(MV_VOID) ++{ ++ MV_U32 devId; ++ ++ devId = mvCtrlModelGet(); ++ ++ switch(devId){ ++ case MV_6281_DEV_ID: ++ return MV_6281_SDIO; ++ break; ++ case MV_6192_DEV_ID: ++ return MV_6192_SDIO; ++ break; ++ case MV_6190_DEV_ID: ++ return MV_6190_SDIO; ++ break; ++ case MV_6180_DEV_ID: ++ return MV_6180_SDIO; ++ break; ++ } ++ return 0; ++ ++} ++#endif ++ ++#if defined(MV_INCLUDE_TS) ++/******************************************************************************* ++* mvCtrlTsSupport - Return if this controller has integrated TS flash support ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if TS is supported and MV_FALSE otherwise ++* ++*******************************************************************************/ ++MV_U32 mvCtrlTsSupport(MV_VOID) ++{ ++ MV_U32 devId; ++ ++ devId = mvCtrlModelGet(); ++ ++ switch(devId){ ++ case MV_6281_DEV_ID: ++ return MV_6281_TS; ++ break; ++ case MV_6192_DEV_ID: ++ return MV_6192_TS; ++ break; ++ case MV_6190_DEV_ID: ++ return MV_6190_TS; ++ break; ++ case MV_6180_DEV_ID: ++ return MV_6180_TS; ++ break; ++ } ++ return 0; ++} ++#endif ++ ++#if defined(MV_INCLUDE_AUDIO) ++/******************************************************************************* ++* mvCtrlAudioSupport - Return if this controller has integrated AUDIO flash support ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if AUDIO is supported and MV_FALSE otherwise ++* ++*******************************************************************************/ ++MV_U32 mvCtrlAudioSupport(MV_VOID) ++{ ++ MV_U32 devId; ++ ++ devId = mvCtrlModelGet(); ++ ++ switch(devId){ ++ case MV_6281_DEV_ID: ++ return MV_6281_AUDIO; ++ break; ++ case MV_6192_DEV_ID: ++ return MV_6192_AUDIO; ++ break; ++ case MV_6190_DEV_ID: ++ return MV_6190_AUDIO; ++ break; ++ case MV_6180_DEV_ID: ++ return MV_6180_AUDIO; ++ break; ++ } ++ return 0; ++ ++} ++#endif ++ ++#if defined(MV_INCLUDE_TDM) ++/******************************************************************************* ++* mvCtrlTdmSupport - Return if this controller has integrated TDM flash support ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if TDM is supported and MV_FALSE otherwise ++* ++*******************************************************************************/ ++MV_U32 mvCtrlTdmSupport(MV_VOID) ++{ ++ MV_U32 devId; ++ ++ devId = mvCtrlModelGet(); ++ ++ switch(devId){ ++ case MV_6281_DEV_ID: ++ return MV_6281_TDM; ++ break; ++ case MV_6192_DEV_ID: ++ return MV_6192_TDM; ++ break; ++ case MV_6190_DEV_ID: ++ return MV_6190_TDM; ++ break; ++ case MV_6180_DEV_ID: ++ return MV_6180_TDM; ++ break; ++ } ++ return 0; ++ ++} ++#endif ++ ++/******************************************************************************* ++* mvCtrlModelGet - Get Marvell controller device model (Id) ++* ++* DESCRIPTION: ++* This function returns 16bit describing the device model (ID) as defined ++* in PCI Device and Vendor ID configuration register offset 0x0. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 16bit desscribing Marvell controller ID ++* ++*******************************************************************************/ ++MV_U16 mvCtrlModelGet(MV_VOID) ++{ ++ MV_U32 devId; ++ ++ devId = MV_REG_READ(CHIP_BOND_REG); ++ devId &= PCKG_OPT_MASK; ++ ++ switch(devId){ ++ case 2: ++ return MV_6281_DEV_ID; ++ break; ++ case 1: ++ if (((MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0,PEX_DEVICE_AND_VENDOR_ID))& 0xffff0000) >> 16) ++ == MV_6190_DEV_ID) ++ return MV_6190_DEV_ID; ++ else ++ return MV_6192_DEV_ID; ++ break; ++ case 0: ++ return MV_6180_DEV_ID; ++ break; ++ } ++ ++ return 0; ++} ++/******************************************************************************* ++* mvCtrlRevGet - Get Marvell controller device revision number ++* ++* DESCRIPTION: ++* This function returns 8bit describing the device revision as defined ++* in PCI Express Class Code and Revision ID Register. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 8bit desscribing Marvell controller revision number ++* ++*******************************************************************************/ ++MV_U8 mvCtrlRevGet(MV_VOID) ++{ ++ MV_U8 revNum; ++#if defined(MV_INCLUDE_CLK_PWR_CNTRL) ++ /* Check pex power state */ ++ MV_U32 pexPower; ++ pexPower = mvCtrlPwrClckGet(PEX_UNIT_ID,0); ++ if (pexPower == MV_FALSE) ++ mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_TRUE); ++#endif ++ revNum = (MV_U8)MV_REG_READ(PEX_CFG_DIRECT_ACCESS(0,PCI_CLASS_CODE_AND_REVISION_ID)); ++#if defined(MV_INCLUDE_CLK_PWR_CNTRL) ++ /* Return to power off state */ ++ if (pexPower == MV_FALSE) ++ mvCtrlPwrClckSet(PEX_UNIT_ID, 0, MV_FALSE); ++#endif ++ return ((revNum & PCCRIR_REVID_MASK) >> PCCRIR_REVID_OFFS); ++} ++ ++/******************************************************************************* ++* mvCtrlNameGet - Get Marvell controller name ++* ++* DESCRIPTION: ++* This function returns a string describing the device model and revision. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* pNameBuff - Buffer to contain device name string. Minimum size 30 chars. ++* ++* RETURN: ++* ++* MV_ERROR if informantion can not be read. ++*******************************************************************************/ ++MV_STATUS mvCtrlNameGet(char *pNameBuff) ++{ ++ mvOsSPrintf (pNameBuff, "%s%x Rev %d", SOC_NAME_PREFIX, ++ mvCtrlModelGet(), mvCtrlRevGet()); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCtrlModelRevGet - Get Controller Model (Device ID) and Revision ++* ++* DESCRIPTION: ++* This function returns 32bit value describing both Device ID and Revision ++* as defined in PCI Express Device and Vendor ID Register and device revision ++* as defined in PCI Express Class Code and Revision ID Register. ++ ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit describing both controller device ID and revision number ++* ++*******************************************************************************/ ++MV_U32 mvCtrlModelRevGet(MV_VOID) ++{ ++ return ((mvCtrlModelGet() << 16) | mvCtrlRevGet()); ++} ++ ++/******************************************************************************* ++* mvCtrlModelRevNameGet - Get Marvell controller name ++* ++* DESCRIPTION: ++* This function returns a string describing the device model and revision. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* pNameBuff - Buffer to contain device name string. Minimum size 30 chars. ++* ++* RETURN: ++* ++* MV_ERROR if informantion can not be read. ++*******************************************************************************/ ++ ++MV_STATUS mvCtrlModelRevNameGet(char *pNameBuff) ++{ ++ ++ switch (mvCtrlModelRevGet()) ++ { ++ case MV_6281_A0_ID: ++ mvOsSPrintf (pNameBuff, "%s",MV_6281_A0_NAME); ++ break; ++ case MV_6192_A0_ID: ++ mvOsSPrintf (pNameBuff, "%s",MV_6192_A0_NAME); ++ break; ++ case MV_6180_A0_ID: ++ mvOsSPrintf (pNameBuff, "%s",MV_6180_A0_NAME); ++ break; ++ case MV_6190_A0_ID: ++ mvOsSPrintf (pNameBuff, "%s",MV_6190_A0_NAME); ++ break; ++ case MV_6281_A1_ID: ++ mvOsSPrintf (pNameBuff, "%s",MV_6281_A1_NAME); ++ break; ++ case MV_6192_A1_ID: ++ mvOsSPrintf (pNameBuff, "%s",MV_6192_A1_NAME); ++ break; ++ case MV_6180_A1_ID: ++ mvOsSPrintf (pNameBuff, "%s",MV_6180_A1_NAME); ++ break; ++ case MV_6190_A1_ID: ++ mvOsSPrintf (pNameBuff, "%s",MV_6190_A1_NAME); ++ break; ++ default: ++ mvCtrlNameGet(pNameBuff); ++ break; ++ } ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* ctrlWinOverlapTest - Test address windows for overlaping. ++* ++* DESCRIPTION: ++* This function checks the given two address windows for overlaping. ++* ++* INPUT: ++* pAddrWin1 - Address window 1. ++* pAddrWin2 - Address window 2. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++* MV_TRUE if address window overlaps, MV_FALSE otherwise. ++*******************************************************************************/ ++MV_STATUS ctrlWinOverlapTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2) ++{ ++ MV_U32 winBase1, winBase2; ++ MV_U32 winTop1, winTop2; ++ ++ /* check if we have overflow than 4G*/ ++ if (((0xffffffff - pAddrWin1->baseLow) < pAddrWin1->size-1)|| ++ ((0xffffffff - pAddrWin2->baseLow) < pAddrWin2->size-1)) ++ { ++ return MV_TRUE; ++ } ++ ++ winBase1 = pAddrWin1->baseLow; ++ winBase2 = pAddrWin2->baseLow; ++ winTop1 = winBase1 + pAddrWin1->size-1; ++ winTop2 = winBase2 + pAddrWin2->size-1; ++ ++ ++ if (((winBase1 <= winTop2 ) && ( winTop2 <= winTop1)) || ++ ((winBase1 <= winBase2) && (winBase2 <= winTop1))) ++ { ++ return MV_TRUE; ++ } ++ else ++ { ++ return MV_FALSE; ++ } ++} ++ ++/******************************************************************************* ++* ctrlWinWithinWinTest - Test address windows for overlaping. ++* ++* DESCRIPTION: ++* This function checks the given win1 boundries is within ++* win2 boundries. ++* ++* INPUT: ++* pAddrWin1 - Address window 1. ++* pAddrWin2 - Address window 2. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++* MV_TRUE if found win1 inside win2, MV_FALSE otherwise. ++*******************************************************************************/ ++MV_STATUS ctrlWinWithinWinTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2) ++{ ++ MV_U32 winBase1, winBase2; ++ MV_U32 winTop1, winTop2; ++ ++ winBase1 = pAddrWin1->baseLow; ++ winBase2 = pAddrWin2->baseLow; ++ winTop1 = winBase1 + pAddrWin1->size -1; ++ winTop2 = winBase2 + pAddrWin2->size -1; ++ ++ if (((winBase1 >= winBase2 ) && ( winBase1 <= winTop2)) || ++ ((winTop1 >= winBase2) && (winTop1 <= winTop2))) ++ { ++ return MV_TRUE; ++ } ++ else ++ { ++ return MV_FALSE; ++ } ++} ++ ++static const char* cntrlName[] = TARGETS_NAME_ARRAY; ++ ++/******************************************************************************* ++* mvCtrlTargetNameGet - Get Marvell controller target name ++* ++* DESCRIPTION: ++* This function convert the trget enumeration to string. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Target name (const MV_8 *) ++*******************************************************************************/ ++const MV_8* mvCtrlTargetNameGet( MV_TARGET target ) ++{ ++ ++ if (target >= MAX_TARGETS) ++ { ++ return "target unknown"; ++ } ++ ++ return cntrlName[target]; ++} ++ ++/******************************************************************************* ++* mvCtrlAddrDecShow - Print the Controller units address decode map. ++* ++* DESCRIPTION: ++* This function the Controller units address decode map. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvCtrlAddrDecShow(MV_VOID) ++{ ++ mvCpuIfAddDecShow(); ++ mvAhbToMbusAddDecShow(); ++#if defined(MV_INCLUDE_PEX) ++ mvPexAddrDecShow(); ++#endif ++#if defined(MV_INCLUDE_USB) ++ mvUsbAddrDecShow(); ++#endif ++#if defined(MV_INCLUDE_GIG_ETH) ++ mvEthAddrDecShow(); ++#endif ++#if defined(MV_INCLUDE_XOR) ++ mvXorAddrDecShow(); ++#endif ++#if defined(MV_INCLUDE_SATA) ++ mvSataAddrDecShow(); ++#endif ++#if defined(MV_INCLUDE_AUDIO) ++ mvAudioAddrDecShow(); ++#endif ++#if defined(MV_INCLUDE_TS) ++ mvTsuAddrDecShow(); ++#endif ++} ++ ++/******************************************************************************* ++* ctrlSizeToReg - Extract size value for register assignment. ++* ++* DESCRIPTION: ++* Address decode size parameter must be programed from LSB to MSB as ++* sequence of 1's followed by sequence of 0's. The number of 1's ++* specifies the size of the window in 64 KB granularity (e.g. a ++* value of 0x00ff specifies 256x64k = 16 MB). ++* This function extract the size value from the size parameter according ++* to given aligment paramter. For example for size 0x1000000 (16MB) and ++* aligment 0x10000 (64KB) the function will return 0x00FF. ++* ++* INPUT: ++* size - Size. ++* alignment - Size alignment. Note that alignment must be power of 2! ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit describing size register value correspond to size parameter. ++* If value is '-1' size parameter or aligment are invalid. ++*******************************************************************************/ ++MV_U32 ctrlSizeToReg(MV_U32 size, MV_U32 alignment) ++{ ++ MV_U32 retVal; ++ ++ /* Check size parameter alignment */ ++ if ((0 == size) || (MV_IS_NOT_ALIGN(size, alignment))) ++ { ++ DB(mvOsPrintf("ctrlSizeToReg: ERR. Size is zero or not aligned.\n")); ++ return -1; ++ } ++ ++ /* Take out the "alignment" portion out of the size parameter */ ++ alignment--; /* Now the alignmet is a sequance of '1' (e.g. 0xffff) */ ++ /* and size is 0x1000000 (16MB) for example */ ++ while(alignment & 1) /* Check that alignmet LSB is set */ ++ { ++ size = (size >> 1); /* If LSB is set, move 'size' one bit to right */ ++ alignment = (alignment >> 1); ++ } ++ ++ /* If after the alignment first '0' was met we still have '1' in */ ++ /* it then aligment is invalid (not power of 2) */ ++ if (alignment) ++ { ++ DB(mvOsPrintf("ctrlSizeToReg: ERR. Alignment parameter 0x%x invalid.\n", ++ (MV_U32)alignment)); ++ return -1; ++ } ++ ++ /* Now the size is shifted right according to aligment: 0x0100 */ ++ size--; /* Now the size is a sequance of '1': 0x00ff */ ++ ++ retVal = size ; ++ ++ /* Check that LSB to MSB is sequence of 1's followed by sequence of 0's */ ++ while(size & 1) /* Check that LSB is set */ ++ { ++ size = (size >> 1); /* If LSB is set, move one bit to the right */ ++ } ++ ++ if (size) /* Sequance of 1's is over. Check that we have no other 1's */ ++ { ++ DB(mvOsPrintf("ctrlSizeToReg: ERR. Size parameter 0x%x invalid.\n", ++ size)); ++ return -1; ++ } ++ ++ return retVal; ++ ++} ++ ++/******************************************************************************* ++* ctrlRegToSize - Extract size value from register value. ++* ++* DESCRIPTION: ++* This function extract a size value from the register size parameter ++* according to given aligment paramter. For example for register size ++* value 0xff and aligment 0x10000 the function will return 0x01000000. ++* ++* INPUT: ++* regSize - Size as in register format. See ctrlSizeToReg. ++* alignment - Size alignment. Note that alignment must be power of 2! ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit describing size. ++* If value is '-1' size parameter or aligment are invalid. ++*******************************************************************************/ ++MV_U32 ctrlRegToSize(MV_U32 regSize, MV_U32 alignment) ++{ ++ MV_U32 temp; ++ ++ /* Check that LSB to MSB is sequence of 1's followed by sequence of 0's */ ++ temp = regSize; /* Now the size is a sequance of '1': 0x00ff */ ++ ++ while(temp & 1) /* Check that LSB is set */ ++ { ++ temp = (temp >> 1); /* If LSB is set, move one bit to the right */ ++ } ++ ++ if (temp) /* Sequance of 1's is over. Check that we have no other 1's */ ++ { ++ DB(mvOsPrintf("ctrlRegToSize: ERR. Size parameter 0x%x invalid.\n", ++ regSize)); ++ return -1; ++ } ++ ++ ++ /* Check that aligment is a power of two */ ++ temp = alignment - 1;/* Now the alignmet is a sequance of '1' (0xffff) */ ++ ++ while(temp & 1) /* Check that alignmet LSB is set */ ++ { ++ temp = (temp >> 1); /* If LSB is set, move 'size' one bit to right */ ++ } ++ ++ /* If after the 'temp' first '0' was met we still have '1' in 'temp' */ ++ /* then 'temp' is invalid (not power of 2) */ ++ if (temp) ++ { ++ DB(mvOsPrintf("ctrlSizeToReg: ERR. Alignment parameter 0x%x invalid.\n", ++ alignment)); ++ return -1; ++ } ++ ++ regSize++; /* Now the size is 0x0100 */ ++ ++ /* Add in the "alignment" portion to the register size parameter */ ++ alignment--; /* Now the alignmet is a sequance of '1' (e.g. 0xffff) */ ++ ++ while(alignment & 1) /* Check that alignmet LSB is set */ ++ { ++ regSize = (regSize << 1); /* LSB is set, move 'size' one bit left */ ++ alignment = (alignment >> 1); ++ } ++ ++ return regSize; ++} ++ ++ ++/******************************************************************************* ++* ctrlSizeRegRoundUp - Round up given size ++* ++* DESCRIPTION: ++* This function round up a given size to a size that fits the ++* restrictions of size format given an aligment parameter. ++* to given aligment paramter. For example for size parameter 0xa1000 and ++* aligment 0x1000 the function will return 0xFF000. ++* ++* INPUT: ++* size - Size. ++* alignment - Size alignment. Note that alignment must be power of 2! ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit describing size value correspond to size in register. ++*******************************************************************************/ ++MV_U32 ctrlSizeRegRoundUp(MV_U32 size, MV_U32 alignment) ++{ ++ MV_U32 msbBit = 0; ++ MV_U32 retSize; ++ ++ /* Check if size parameter is already comply with restriction */ ++ if (!(-1 == ctrlSizeToReg(size, alignment))) ++ { ++ return size; ++ } ++ ++ while(size) ++ { ++ size = (size >> 1); ++ msbBit++; ++ } ++ ++ retSize = (1 << msbBit); ++ ++ if (retSize < alignment) ++ { ++ return alignment; ++ } ++ else ++ { ++ return retSize; ++ } ++} ++/******************************************************************************* ++* mvCtrlSysRstLengthCounterGet - Return number of milliseconds the reset button ++* was pressed and clear counter ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: number of milliseconds the reset button was pressed ++*******************************************************************************/ ++MV_U32 mvCtrlSysRstLengthCounterGet(MV_VOID) ++{ ++ static volatile MV_U32 Count = 0; ++ ++ if(!Count) { ++ Count = (MV_REG_READ(SYSRST_LENGTH_COUNTER_REG) & SLCR_COUNT_MASK); ++ Count = (Count / (MV_BOARD_REFCLK_25MHZ / 1000)); ++ /* clear counter for next boot */ ++ MV_REG_BIT_SET(SYSRST_LENGTH_COUNTER_REG, SLCR_CLR_MASK); ++ } ++ ++ DB(mvOsPrintf("mvCtrlSysRstLengthCounterGet: Reset button was pressed for %u milliseconds\n", Count)); ++ ++ return Count; ++} ++ ++MV_BOOL mvCtrlIsBootFromSPI(MV_VOID) ++{ ++ MV_U32 satr = 0; ++ satr = MV_REG_READ(MPP_SAMPLE_AT_RESET); ++ if(mvCtrlModelGet() == MV_6180_DEV_ID) ++ { ++ if (MSAR_BOOT_MODE_6180(satr) == MSAR_BOOT_SPI_WITH_BOOTROM_6180) ++ return MV_TRUE; ++ else ++ return MV_FALSE; ++ } ++ satr = satr & MSAR_BOOT_MODE_MASK; ++ if (satr == MSAR_BOOT_SPI_WITH_BOOTROM) ++ return MV_TRUE; ++ else ++ return MV_FALSE; ++} ++ ++MV_BOOL mvCtrlIsBootFromSPIUseNAND(MV_VOID) ++{ ++ MV_U32 satr = 0; ++ if(mvCtrlModelGet() == MV_6180_DEV_ID) ++ return MV_FALSE; ++ satr = MV_REG_READ(MPP_SAMPLE_AT_RESET); ++ satr = satr & MSAR_BOOT_MODE_MASK; ++ ++ if (satr == MSAR_BOOT_SPI_USE_NAND_WITH_BOOTROM) ++ return MV_TRUE; ++ else ++ return MV_FALSE; ++} ++ ++MV_BOOL mvCtrlIsBootFromNAND(MV_VOID) ++{ ++ MV_U32 satr = 0; ++ satr = MV_REG_READ(MPP_SAMPLE_AT_RESET); ++ if(mvCtrlModelGet() == MV_6180_DEV_ID) ++ { ++ if (MSAR_BOOT_MODE_6180(satr) == MSAR_BOOT_NAND_WITH_BOOTROM_6180) ++ return MV_TRUE; ++ else ++ return MV_FALSE; ++ } ++ satr = satr & MSAR_BOOT_MODE_MASK; ++ if ((satr == MSAR_BOOT_NAND_WITH_BOOTROM)) ++ return MV_TRUE; ++ else ++ return MV_FALSE; ++} ++ ++#if defined(MV_INCLUDE_CLK_PWR_CNTRL) ++/******************************************************************************* ++* mvCtrlPwrSaveOn - Set Power save mode ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++*******************************************************************************/ ++MV_VOID mvCtrlPwrSaveOn(MV_VOID) ++{ ++ unsigned long old,temp; ++ /* Disable int */ ++ __asm__ __volatile__("mrs %0, cpsr\n" ++ "orr %1, %0, #0xc0\n" ++ "msr cpsr_c, %1" ++ : "=r" (old), "=r" (temp) ++ : ++ : "memory"); ++ ++ /* Set SoC in power save */ ++ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, BIT11); ++ /* Wait for int */ ++ __asm__ __volatile__("mcr p15, 0, r0, c7, c0, 4"); ++ ++ /* Enabled int */ ++ __asm__ __volatile__("msr cpsr_c, %0" ++ : ++ : "r" (old) ++ : "memory"); ++} ++ ++ ++ ++/******************************************************************************* ++* mvCtrlPwrSaveOff - Go out of power save mode ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++*******************************************************************************/ ++MV_VOID mvCtrlPwrSaveOff(MV_VOID) ++{ ++ unsigned long old,temp; ++ /* Disable int */ ++ __asm__ __volatile__("mrs %0, cpsr\n" ++ "orr %1, %0, #0xc0\n" ++ "msr cpsr_c, %1" ++ : "=r" (old), "=r" (temp) ++ : ++ : "memory"); ++ ++ /* Set SoC in power save */ ++ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, BIT11); ++ /* Wait for int */ ++ __asm__ __volatile__("mcr p15, 0, r0, c7, c0, 4"); ++ ++ /* Enabled int */ ++ __asm__ __volatile__("msr cpsr_c, %0" ++ : ++ : "r" (old) ++ : "memory"); ++} ++ ++/******************************************************************************* ++* mvCtrlPwrClckSet - Set Power State for specific Unit ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++*******************************************************************************/ ++MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) ++{ ++ switch (unitId) ++ { ++#if defined(MV_INCLUDE_PEX) ++ case PEX_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_PEXSTOPCLOCK_MASK); ++ } ++ else ++ { ++ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_PEXSTOPCLOCK_MASK); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_GIG_ETH) ++ case ETH_GIG_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_GESTOPCLOCK_MASK(index)); ++ } ++ else ++ { ++ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_GESTOPCLOCK_MASK(index)); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_INTEG_SATA) ++ case SATA_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SATASTOPCLOCK_MASK(index)); ++ } ++ else ++ { ++ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SATASTOPCLOCK_MASK(index)); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_CESA) ++ case CESA_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SESTOPCLOCK_MASK); ++ } ++ else ++ { ++ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SESTOPCLOCK_MASK); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_USB) ++ case USB_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_USBSTOPCLOCK_MASK); ++ } ++ else ++ { ++ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_USBSTOPCLOCK_MASK); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_AUDIO) ++ case AUDIO_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_AUDIOSTOPCLOCK_MASK); ++ } ++ else ++ { ++ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_AUDIOSTOPCLOCK_MASK); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_TS) ++ case TS_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_TSSTOPCLOCK_MASK); ++ } ++ else ++ { ++ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_TSSTOPCLOCK_MASK); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_SDIO) ++ case SDIO_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_SDIOSTOPCLOCK_MASK); ++ } ++ else ++ { ++ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_SDIOSTOPCLOCK_MASK); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_TDM) ++ case TDM_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_RESET(POWER_MNG_CTRL_REG, PMC_TDMSTOPCLOCK_MASK); ++ } ++ else ++ { ++ MV_REG_BIT_SET(POWER_MNG_CTRL_REG, PMC_TDMSTOPCLOCK_MASK); ++ } ++ break; ++#endif ++ ++ default: ++ ++ break; ++ ++ } ++} ++ ++/******************************************************************************* ++* mvCtrlPwrClckGet - Get Power State of specific Unit ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++******************************************************************************/ ++MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index) ++{ ++ MV_U32 reg = MV_REG_READ(POWER_MNG_CTRL_REG); ++ MV_BOOL state = MV_TRUE; ++ ++ switch (unitId) ++ { ++#if defined(MV_INCLUDE_PEX) ++ case PEX_UNIT_ID: ++ if ((reg & PMC_PEXSTOPCLOCK_MASK) == PMC_PEXSTOPCLOCK_STOP) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ ++ break; ++#endif ++#if defined(MV_INCLUDE_GIG_ETH) ++ case ETH_GIG_UNIT_ID: ++ if ((reg & PMC_GESTOPCLOCK_MASK(index)) == PMC_GESTOPCLOCK_STOP(index)) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++#if defined(MV_INCLUDE_SATA) ++ case SATA_UNIT_ID: ++ if ((reg & PMC_SATASTOPCLOCK_MASK(index)) == PMC_SATASTOPCLOCK_STOP(index)) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++#if defined(MV_INCLUDE_CESA) ++ case CESA_UNIT_ID: ++ if ((reg & PMC_SESTOPCLOCK_MASK) == PMC_SESTOPCLOCK_STOP) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++#if defined(MV_INCLUDE_USB) ++ case USB_UNIT_ID: ++ if ((reg & PMC_USBSTOPCLOCK_MASK) == PMC_USBSTOPCLOCK_STOP) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++#if defined(MV_INCLUDE_AUDIO) ++ case AUDIO_UNIT_ID: ++ if ((reg & PMC_AUDIOSTOPCLOCK_MASK) == PMC_AUDIOSTOPCLOCK_STOP) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++#if defined(MV_INCLUDE_TS) ++ case TS_UNIT_ID: ++ if ((reg & PMC_TSSTOPCLOCK_MASK) == PMC_TSSTOPCLOCK_STOP) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++#if defined(MV_INCLUDE_SDIO) ++ case SDIO_UNIT_ID: ++ if ((reg & PMC_SDIOSTOPCLOCK_MASK)== PMC_SDIOSTOPCLOCK_STOP) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++#if defined(MV_INCLUDE_TDM) ++ case TDM_UNIT_ID: ++ if ((reg & PMC_TDMSTOPCLOCK_MASK) == PMC_TDMSTOPCLOCK_STOP) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++ ++ default: ++ state = MV_TRUE; ++ break; ++ } ++ ++ ++ return state; ++} ++/******************************************************************************* ++* mvCtrlPwrMemSet - Set Power State for memory on specific Unit ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++*******************************************************************************/ ++MV_VOID mvCtrlPwrMemSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) ++{ ++ switch (unitId) ++ { ++#if defined(MV_INCLUDE_PEX) ++ case PEX_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_PEXSTOPMEM_MASK); ++ } ++ else ++ { ++ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_PEXSTOPMEM_MASK); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_GIG_ETH) ++ case ETH_GIG_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_GESTOPMEM_MASK(index)); ++ } ++ else ++ { ++ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_GESTOPMEM_MASK(index)); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_INTEG_SATA) ++ case SATA_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_SATASTOPMEM_MASK(index)); ++ } ++ else ++ { ++ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_SATASTOPMEM_MASK(index)); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_CESA) ++ case CESA_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_SESTOPMEM_MASK); ++ } ++ else ++ { ++ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_SESTOPMEM_MASK); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_USB) ++ case USB_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_USBSTOPMEM_MASK); ++ } ++ else ++ { ++ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_USBSTOPMEM_MASK); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_AUDIO) ++ case AUDIO_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_AUDIOSTOPMEM_MASK); ++ } ++ else ++ { ++ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_AUDIOSTOPMEM_MASK); ++ } ++ break; ++#endif ++#if defined(MV_INCLUDE_XOR) ++ case XOR_UNIT_ID: ++ if (enable == MV_FALSE) ++ { ++ MV_REG_BIT_SET(POWER_MNG_MEM_CTRL_REG, PMC_XORSTOPMEM_MASK(index)); ++ } ++ else ++ { ++ MV_REG_BIT_RESET(POWER_MNG_MEM_CTRL_REG, PMC_XORSTOPMEM_MASK(index)); ++ } ++ break; ++#endif ++ default: ++ ++ break; ++ ++ } ++} ++ ++/******************************************************************************* ++* mvCtrlPwrMemGet - Get Power State of memory on specific Unit ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++******************************************************************************/ ++MV_BOOL mvCtrlPwrMemGet(MV_UNIT_ID unitId, MV_U32 index) ++{ ++ MV_U32 reg = MV_REG_READ(POWER_MNG_MEM_CTRL_REG); ++ MV_BOOL state = MV_TRUE; ++ ++ switch (unitId) ++ { ++#if defined(MV_INCLUDE_PEX) ++ case PEX_UNIT_ID: ++ if ((reg & PMC_PEXSTOPMEM_MASK) == PMC_PEXSTOPMEM_STOP) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ ++ break; ++#endif ++#if defined(MV_INCLUDE_GIG_ETH) ++ case ETH_GIG_UNIT_ID: ++ if ((reg & PMC_GESTOPMEM_MASK(index)) == PMC_GESTOPMEM_STOP(index)) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++#if defined(MV_INCLUDE_SATA) ++ case SATA_UNIT_ID: ++ if ((reg & PMC_SATASTOPMEM_MASK(index)) == PMC_SATASTOPMEM_STOP(index)) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++#if defined(MV_INCLUDE_CESA) ++ case CESA_UNIT_ID: ++ if ((reg & PMC_SESTOPMEM_MASK) == PMC_SESTOPMEM_STOP) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++#if defined(MV_INCLUDE_USB) ++ case USB_UNIT_ID: ++ if ((reg & PMC_USBSTOPMEM_MASK) == PMC_USBSTOPMEM_STOP) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++#if defined(MV_INCLUDE_AUDIO) ++ case AUDIO_UNIT_ID: ++ if ((reg & PMC_AUDIOSTOPMEM_MASK) == PMC_AUDIOSTOPMEM_STOP) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++#if defined(MV_INCLUDE_XOR) ++ case XOR_UNIT_ID: ++ if ((reg & PMC_XORSTOPMEM_MASK(index)) == PMC_XORSTOPMEM_STOP(index)) ++ { ++ state = MV_FALSE; ++ } ++ else state = MV_TRUE; ++ break; ++#endif ++ ++ default: ++ state = MV_TRUE; ++ break; ++ } ++ ++ ++ return state; ++} ++#else ++MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable) {return;} ++MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index) {return MV_TRUE;} ++#endif /* #if defined(MV_INCLUDE_CLK_PWR_CNTRL) */ ++ ++ ++/******************************************************************************* ++* mvMPPConfigToSPI - Change MPP[3:0] configuration to SPI mode ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++******************************************************************************/ ++MV_VOID mvMPPConfigToSPI(MV_VOID) ++{ ++ MV_U32 mppVal = 0; ++ MV_U32 bootVal = 0; ++ ++ if(!mvCtrlIsBootFromSPIUseNAND()) ++ return; ++ mppVal = 0x00002220; /* Set MPP [3:1] to SPI mode */ ++ bootVal = MV_REG_READ(mvCtrlMppRegGet(0)); ++ bootVal &= 0xffff000f; ++ mppVal |= bootVal; ++ ++ MV_REG_WRITE(mvCtrlMppRegGet(0), mppVal); ++} ++ ++ ++/******************************************************************************* ++* mvMPPConfigToDefault - Change MPP[7:0] configuration to default configuration ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++******************************************************************************/ ++MV_VOID mvMPPConfigToDefault(MV_VOID) ++{ ++ MV_U32 mppVal = 0; ++ MV_U32 bootVal = 0; ++ ++ if(!mvCtrlIsBootFromSPIUseNAND()) ++ return; ++ mppVal = mvBoardMppGet(0); ++ bootVal = MV_REG_READ(mvCtrlMppRegGet(0)); ++ mppVal &= ~0xffff000f; ++ bootVal &= 0xffff000f; ++ mppVal |= bootVal; ++ ++ MV_REG_WRITE(mvCtrlMppRegGet(0), mppVal); ++} ++ ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvLib.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,185 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvCtrlEnvLibh ++#define __INCmvCtrlEnvLibh ++ ++/* includes */ ++#include "mvSysHwConfig.h" ++#include "mvCommon.h" ++#include "mvTypes.h" ++#include "mvOs.h" ++#include "boardEnv/mvBoardEnvLib.h" ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++#include "ctrlEnv/mvCtrlEnvRegs.h" ++#include "ctrlEnv/mvCtrlEnvAddrDec.h" ++ ++ ++/* typedefs */ ++ ++/* This enumerator describes the possible HW cache coherency policies the */ ++/* controllers supports. */ ++typedef enum _mvCachePolicy ++{ ++ NO_COHERENCY, /* No HW cache coherency support */ ++ WT_COHERENCY, /* HW cache coherency supported in Write Through policy */ ++ WB_COHERENCY /* HW cache coherency supported in Write Back policy */ ++}MV_CACHE_POLICY; ++ ++ ++/* The swapping is referred to a 64-bit words (as this is the controller */ ++/* internal data path width). This enumerator describes the possible */ ++/* data swap types. Below is an example of the data 0x0011223344556677 */ ++typedef enum _mvSwapType ++{ ++ MV_BYTE_SWAP, /* Byte Swap 77 66 55 44 33 22 11 00 */ ++ MV_NO_SWAP, /* No swapping 00 11 22 33 44 55 66 77 */ ++ MV_BYTE_WORD_SWAP, /* Both byte and word swap 33 22 11 00 77 66 55 44 */ ++ MV_WORD_SWAP, /* Word swap 44 55 66 77 00 11 22 33 */ ++ SWAP_TYPE_MAX /* Delimiter for this enumerator */ ++}MV_SWAP_TYPE; ++ ++/* This structure describes access rights for Access protection windows */ ++/* that can be found in IDMA, XOR, Ethernet and MPSC units. */ ++/* Note that the permission enumerator coresponds to its register format. */ ++/* For example, Read only premission is presented as "1" in register field. */ ++typedef enum _mvAccessRights ++{ ++ NO_ACCESS_ALLOWED = 0, /* No access allowed */ ++ READ_ONLY = 1, /* Read only permission */ ++ ACC_RESERVED = 2, /* Reserved access right */ ++ FULL_ACCESS = 3, /* Read and Write permission */ ++ MAX_ACC_RIGHTS ++}MV_ACCESS_RIGHTS; ++ ++ ++/* mcspLib.h API list */ ++ ++MV_STATUS mvCtrlEnvInit(MV_VOID); ++MV_U32 mvCtrlMppRegGet(MV_U32 mppGroup); ++ ++#if defined(MV_INCLUDE_PEX) ++MV_U32 mvCtrlPexMaxIfGet(MV_VOID); ++#else ++#define mvCtrlPexMaxIfGet() (0) ++#endif ++ ++#define mvCtrlPciIfMaxIfGet() (0) ++ ++#if defined(MV_INCLUDE_GIG_ETH) ++MV_U32 mvCtrlEthMaxPortGet(MV_VOID); ++#endif ++#if defined(MV_INCLUDE_XOR) ++MV_U32 mvCtrlXorMaxChanGet(MV_VOID); ++#endif ++#if defined(MV_INCLUDE_USB) ++MV_U32 mvCtrlUsbMaxGet(MV_VOID); ++#endif ++#if defined(MV_INCLUDE_NAND) ++MV_U32 mvCtrlNandSupport(MV_VOID); ++#endif ++#if defined(MV_INCLUDE_SDIO) ++MV_U32 mvCtrlSdioSupport(MV_VOID); ++#endif ++#if defined(MV_INCLUDE_TS) ++MV_U32 mvCtrlTsSupport(MV_VOID); ++#endif ++#if defined(MV_INCLUDE_AUDIO) ++MV_U32 mvCtrlAudioSupport(MV_VOID); ++#endif ++#if defined(MV_INCLUDE_TDM) ++MV_U32 mvCtrlTdmSupport(MV_VOID); ++#endif ++ ++MV_U16 mvCtrlModelGet(MV_VOID); ++MV_U8 mvCtrlRevGet(MV_VOID); ++MV_STATUS mvCtrlNameGet(char *pNameBuff); ++MV_U32 mvCtrlModelRevGet(MV_VOID); ++MV_STATUS mvCtrlModelRevNameGet(char *pNameBuff); ++MV_VOID mvCtrlAddrDecShow(MV_VOID); ++const MV_8* mvCtrlTargetNameGet(MV_TARGET target); ++MV_U32 ctrlSizeToReg(MV_U32 size, MV_U32 alignment); ++MV_U32 ctrlRegToSize(MV_U32 regSize, MV_U32 alignment); ++MV_U32 ctrlSizeRegRoundUp(MV_U32 size, MV_U32 alignment); ++MV_U32 mvCtrlSysRstLengthCounterGet(MV_VOID); ++MV_STATUS ctrlWinOverlapTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2); ++MV_STATUS ctrlWinWithinWinTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2); ++ ++MV_VOID mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable); ++MV_BOOL mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index); ++MV_VOID mvCtrlPwrMemSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable); ++MV_BOOL mvCtrlIsBootFromSPI(MV_VOID); ++MV_BOOL mvCtrlIsBootFromSPIUseNAND(MV_VOID); ++MV_BOOL mvCtrlIsBootFromNAND(MV_VOID); ++#if defined(MV_INCLUDE_CLK_PWR_CNTRL) ++MV_VOID mvCtrlPwrSaveOn(MV_VOID); ++MV_VOID mvCtrlPwrSaveOff(MV_VOID); ++#endif ++MV_BOOL mvCtrlPwrMemGet(MV_UNIT_ID unitId, MV_U32 index); ++MV_VOID mvMPPConfigToSPI(MV_VOID); ++MV_VOID mvMPPConfigToDefault(MV_VOID); ++ ++ ++#endif /* __INCmvCtrlEnvLibh */ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvRegs.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,419 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvCtrlEnvRegsh ++#define __INCmvCtrlEnvRegsh ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++/* CV Support */ ++#define PEX0_MEM0 PEX0_MEM ++#define PCI0_MEM0 PEX0_MEM ++ ++/* Controller revision info */ ++#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 ++#define PCCRIR_REVID_OFFS 0 /* Revision ID */ ++#define PCCRIR_REVID_MASK (0xff << PCCRIR_REVID_OFFS) ++ ++/* Controler environment registers offsets */ ++ ++/* Power Managment Control */ ++#define POWER_MNG_MEM_CTRL_REG 0x20118 ++ ++#define PMC_GESTOPMEM_OFFS(port) ((port)? 13 : 0) ++#define PMC_GESTOPMEM_MASK(port) (1 << PMC_GESTOPMEM_OFFS(port)) ++#define PMC_GESTOPMEM_EN(port) (0 << PMC_GESTOPMEM_OFFS(port)) ++#define PMC_GESTOPMEM_STOP(port) (1 << PMC_GESTOPMEM_OFFS(port)) ++ ++#define PMC_PEXSTOPMEM_OFFS 1 ++#define PMC_PEXSTOPMEM_MASK (1 << PMC_PEXSTOPMEM_OFFS) ++#define PMC_PEXSTOPMEM_EN (0 << PMC_PEXSTOPMEM_OFFS) ++#define PMC_PEXSTOPMEM_STOP (1 << PMC_PEXSTOPMEM_OFFS) ++ ++#define PMC_USBSTOPMEM_OFFS 2 ++#define PMC_USBSTOPMEM_MASK (1 << PMC_USBSTOPMEM_OFFS) ++#define PMC_USBSTOPMEM_EN (0 << PMC_USBSTOPMEM_OFFS) ++#define PMC_USBSTOPMEM_STOP (1 << PMC_USBSTOPMEM_OFFS) ++ ++#define PMC_DUNITSTOPMEM_OFFS 3 ++#define PMC_DUNITSTOPMEM_MASK (1 << PMC_DUNITSTOPMEM_OFFS) ++#define PMC_DUNITSTOPMEM_EN (0 << PMC_DUNITSTOPMEM_OFFS) ++#define PMC_DUNITSTOPMEM_STOP (1 << PMC_DUNITSTOPMEM_OFFS) ++ ++#define PMC_RUNITSTOPMEM_OFFS 4 ++#define PMC_RUNITSTOPMEM_MASK (1 << PMC_RUNITSTOPMEM_OFFS) ++#define PMC_RUNITSTOPMEM_EN (0 << PMC_RUNITSTOPMEM_OFFS) ++#define PMC_RUNITSTOPMEM_STOP (1 << PMC_RUNITSTOPMEM_OFFS) ++ ++#define PMC_XORSTOPMEM_OFFS(port) (5+(port*2)) ++#define PMC_XORSTOPMEM_MASK(port) (1 << PMC_XORSTOPMEM_OFFS(port)) ++#define PMC_XORSTOPMEM_EN(port) (0 << PMC_XORSTOPMEM_OFFS(port)) ++#define PMC_XORSTOPMEM_STOP(port) (1 << PMC_XORSTOPMEM_OFFS(port)) ++ ++#define PMC_SATASTOPMEM_OFFS(port) (6+(port*5)) ++#define PMC_SATASTOPMEM_MASK(port) (1 << PMC_SATASTOPMEM_OFFS(port)) ++#define PMC_SATASTOPMEM_EN(port) (0 << PMC_SATASTOPMEM_OFFS(port)) ++#define PMC_SATASTOPMEM_STOP(port) (1 << PMC_SATASTOPMEM_OFFS(port)) ++ ++#define PMC_SESTOPMEM_OFFS 8 ++#define PMC_SESTOPMEM_MASK (1 << PMC_SESTOPMEM_OFFS) ++#define PMC_SESTOPMEM_EN (0 << PMC_SESTOPMEM_OFFS) ++#define PMC_SESTOPMEM_STOP (1 << PMC_SESTOPMEM_OFFS) ++ ++#define PMC_AUDIOSTOPMEM_OFFS 9 ++#define PMC_AUDIOSTOPMEM_MASK (1 << PMC_AUDIOSTOPMEM_OFFS) ++#define PMC_AUDIOSTOPMEM_EN (0 << PMC_AUDIOSTOPMEM_OFFS) ++#define PMC_AUDIOSTOPMEM_STOP (1 << PMC_AUDIOSTOPMEM_OFFS) ++ ++#define POWER_MNG_CTRL_REG 0x2011C ++ ++#define PMC_GESTOPCLOCK_OFFS(port) ((port)? 19 : 0) ++#define PMC_GESTOPCLOCK_MASK(port) (1 << PMC_GESTOPCLOCK_OFFS(port)) ++#define PMC_GESTOPCLOCK_EN(port) (1 << PMC_GESTOPCLOCK_OFFS(port)) ++#define PMC_GESTOPCLOCK_STOP(port) (0 << PMC_GESTOPCLOCK_OFFS(port)) ++ ++#define PMC_PEXPHYSTOPCLOCK_OFFS 1 ++#define PMC_PEXPHYSTOPCLOCK_MASK (1 << PMC_PEXPHYSTOPCLOCK_OFFS) ++#define PMC_PEXPHYSTOPCLOCK_EN (1 << PMC_PEXPHYSTOPCLOCK_OFFS) ++#define PMC_PEXPHYSTOPCLOCK_STOP (0 << PMC_PEXPHYSTOPCLOCK_OFFS) ++ ++#define PMC_PEXSTOPCLOCK_OFFS 2 ++#define PMC_PEXSTOPCLOCK_MASK (1 << PMC_PEXSTOPCLOCK_OFFS) ++#define PMC_PEXSTOPCLOCK_EN (1 << PMC_PEXSTOPCLOCK_OFFS) ++#define PMC_PEXSTOPCLOCK_STOP (0 << PMC_PEXSTOPCLOCK_OFFS) ++ ++#define PMC_USBSTOPCLOCK_OFFS 3 ++#define PMC_USBSTOPCLOCK_MASK (1 << PMC_USBSTOPCLOCK_OFFS) ++#define PMC_USBSTOPCLOCK_EN (1 << PMC_USBSTOPCLOCK_OFFS) ++#define PMC_USBSTOPCLOCK_STOP (0 << PMC_USBSTOPCLOCK_OFFS) ++ ++#define PMC_SDIOSTOPCLOCK_OFFS 4 ++#define PMC_SDIOSTOPCLOCK_MASK (1 << PMC_SDIOSTOPCLOCK_OFFS) ++#define PMC_SDIOSTOPCLOCK_EN (1 << PMC_SDIOSTOPCLOCK_OFFS) ++#define PMC_SDIOSTOPCLOCK_STOP (0 << PMC_SDIOSTOPCLOCK_OFFS) ++ ++#define PMC_TSSTOPCLOCK_OFFS 5 ++#define PMC_TSSTOPCLOCK_MASK (1 << PMC_TSSTOPCLOCK_OFFS) ++#define PMC_TSSTOPCLOCK_EN (1 << PMC_TSSTOPCLOCK_OFFS) ++#define PMC_TSSTOPCLOCK_STOP (0 << PMC_TSSTOPCLOCK_OFFS) ++ ++#define PMC_AUDIOSTOPCLOCK_OFFS 9 ++#define PMC_AUDIOSTOPCLOCK_MASK (1 << PMC_AUDIOSTOPCLOCK_OFFS) ++#define PMC_AUDIOSTOPCLOCK_EN (1 << PMC_AUDIOSTOPCLOCK_OFFS) ++#define PMC_AUDIOSTOPCLOCK_STOP (0 << PMC_AUDIOSTOPCLOCK_OFFS) ++ ++#define PMC_POWERSAVE_OFFS 11 ++#define PMC_POWERSAVE_MASK (1 << PMC_POWERSAVE_OFFS) ++#define PMC_POWERSAVE_EN (1 << PMC_POWERSAVE_OFFS) ++#define PMC_POWERSAVE_STOP (0 << PMC_POWERSAVE_OFFS) ++ ++ ++ ++ ++#define PMC_SATASTOPCLOCK_OFFS(port) (14+(port)) ++#define PMC_SATASTOPCLOCK_MASK(port) (1 << PMC_SATASTOPCLOCK_OFFS(port)) ++#define PMC_SATASTOPCLOCK_EN(port) (1 << PMC_SATASTOPCLOCK_OFFS(port)) ++#define PMC_SATASTOPCLOCK_STOP(port) (0 << PMC_SATASTOPCLOCK_OFFS(port)) ++ ++#define PMC_SESTOPCLOCK_OFFS 17 ++#define PMC_SESTOPCLOCK_MASK (1 << PMC_SESTOPCLOCK_OFFS) ++#define PMC_SESTOPCLOCK_EN (1 << PMC_SESTOPCLOCK_OFFS) ++#define PMC_SESTOPCLOCK_STOP (0 << PMC_SESTOPCLOCK_OFFS) ++ ++#define PMC_TDMSTOPCLOCK_OFFS 20 ++#define PMC_TDMSTOPCLOCK_MASK (1 << PMC_TDMSTOPCLOCK_OFFS) ++#define PMC_TDMSTOPCLOCK_EN (1 << PMC_TDMSTOPCLOCK_OFFS) ++#define PMC_TDMSTOPCLOCK_STOP (0 << PMC_TDMSTOPCLOCK_OFFS) ++ ++ ++/* Controler environment registers offsets */ ++#define MPP_CONTROL_REG0 0x10000 ++#define MPP_CONTROL_REG1 0x10004 ++#define MPP_CONTROL_REG2 0x10008 ++#define MPP_CONTROL_REG3 0x1000C ++#define MPP_CONTROL_REG4 0x10010 ++#define MPP_CONTROL_REG5 0x10014 ++#define MPP_CONTROL_REG6 0x10018 ++#define MPP_SAMPLE_AT_RESET 0x10030 ++#define CHIP_BOND_REG 0x10034 ++#define SYSRST_LENGTH_COUNTER_REG 0x10050 ++#define SLCR_COUNT_OFFS 0 ++#define SLCR_COUNT_MASK (0x1FFFFFFF << SLCR_COUNT_OFFS) ++#define SLCR_CLR_OFFS 31 ++#define SLCR_CLR_MASK (1 << SLCR_CLR_OFFS) ++#define PCKG_OPT_MASK 0x3 ++#define MPP_OUTPUT_DRIVE_REG 0x100E0 ++#define MPP_RGMII0_OUTPUT_DRIVE_OFFS 7 ++#define MPP_3_3_RGMII0_OUTPUT_DRIVE (0x0 << MPP_RGMII0_OUTPUT_DRIVE_OFFS) ++#define MPP_1_8_RGMII0_OUTPUT_DRIVE (0x1 << MPP_RGMII0_OUTPUT_DRIVE_OFFS) ++#define MPP_RGMII1_OUTPUT_DRIVE_OFFS 15 ++#define MPP_3_3_RGMII1_OUTPUT_DRIVE (0x0 << MPP_RGMII1_OUTPUT_DRIVE_OFFS) ++#define MPP_1_8_RGMII1_OUTPUT_DRIVE (0x1 << MPP_RGMII1_OUTPUT_DRIVE_OFFS) ++ ++#define MSAR_BOOT_MODE_OFFS 12 ++#define MSAR_BOOT_MODE_MASK (0x7 << MSAR_BOOT_MODE_OFFS) ++#define MSAR_BOOT_NAND_WITH_BOOTROM (0x5 << MSAR_BOOT_MODE_OFFS) ++#define MSAR_BOOT_SPI_WITH_BOOTROM (0x4 << MSAR_BOOT_MODE_OFFS) ++#define MSAR_BOOT_SPI_USE_NAND_WITH_BOOTROM (0x2 << MSAR_BOOT_MODE_OFFS) ++ ++#define MSAR_BOOT_MODE_6180(X) (((X & 0x3000) >> 12) | \ ++ ((X & 0x2) << 1)) ++#define MSAR_BOOT_SPI_WITH_BOOTROM_6180 0x1 ++#define MSAR_BOOT_NAND_WITH_BOOTROM_6180 0x5 ++ ++#define MSAR_TCLCK_OFFS 21 ++#define MSAR_TCLCK_MASK (0x1 << MSAR_TCLCK_OFFS) ++#define MSAR_TCLCK_166 (0x1 << MSAR_TCLCK_OFFS) ++#define MSAR_TCLCK_200 (0x0 << MSAR_TCLCK_OFFS) ++ ++ ++#define MSAR_CPUCLCK_EXTRACT(X) (((X & 0x2) >> 1) | ((X & 0x400000) >> 21) | \ ++ ((X & 0x18) >> 1)) ++ ++#define MSAR_CPUCLCK_OFFS_6180 2 ++#define MSAR_CPUCLCK_MASK_6180 (0x7 << MSAR_CPUCLCK_OFFS_6180) ++ ++#define MSAR_DDRCLCK_RTIO_OFFS 5 ++#define MSAR_DDRCLCK_RTIO_MASK (0xF << MSAR_DDRCLCK_RTIO_OFFS) ++ ++#define MSAR_L2CLCK_EXTRACT(X) (((X & 0x600) >> 9) | ((X & 0x80000) >> 17)) ++ ++#ifndef MV_ASMLANGUAGE ++/* CPU clock for 6281,6192 0->Resereved */ ++#define MV_CPU_CLCK_TBL { 0, 0, 0, 0, \ ++ 600000000, 0, 800000000, 1000000000, \ ++ 0, 1200000000, 0, 0, \ ++ 1500000000, 0, 0, 0} ++ ++/* DDR clock RATIO for 6281,6192 {0,0}->Reserved */ ++#define MV_DDR_CLCK_RTIO_TBL {\ ++ {0, 0}, {0, 0}, {2, 1}, {0, 0}, \ ++ {3, 1}, {0, 0}, {4, 1}, {9, 2}, \ ++ {5, 1}, {6, 1}, {0, 0}, {0, 0}, \ ++ {0, 0}, {0, 0}, {0, 0}, {0, 0} \ ++} ++ ++/* L2 clock RATIO for 6281,6192 {1,1}->Reserved */ ++#define MV_L2_CLCK_RTIO_TBL {\ ++ {0, 0}, {2, 1}, {0, 0}, {3, 1}, \ ++ {0, 0}, {0, 0}, {0, 0}, {0, 0} \ ++} ++ ++/* 6180 have different clk reset sampling */ ++/* ARM CPU, DDR, L2 clock for 6180 {0,0,0}->Reserved */ ++#define MV_CPU6180_DDR_L2_CLCK_TBL { \ ++ {0, 0, 0 },\ ++ {0, 0, 0 },\ ++ {0, 0, 0 },\ ++ {0, 0, 0 },\ ++ {0, 0, 0 },\ ++ {600000000, 200000000, 300000000 },\ ++ {800000000, 200000000, 400000000 },\ ++ {0, 0, 0 }\ ++} ++ ++ ++ ++/* These macros help units to identify a target Mbus Arbiter group */ ++#define MV_TARGET_IS_DRAM(target) \ ++ ((target >= SDRAM_CS0) && (target <= SDRAM_CS3)) ++ ++#define MV_TARGET_IS_PEX0(target) \ ++ ((target >= PEX0_MEM) && (target <= PEX0_IO)) ++ ++#define MV_TARGET_IS_PEX1(target) 0 ++ ++#define MV_TARGET_IS_PEX(target) (MV_TARGET_IS_PEX0(target) || MV_TARGET_IS_PEX1(target)) ++ ++#define MV_TARGET_IS_DEVICE(target) \ ++ ((target >= DEVICE_CS0) && (target <= DEVICE_CS3)) ++ ++#define MV_PCI_DRAM_BAR_TO_DRAM_TARGET(bar) 0 ++ ++#define MV_TARGET_IS_AS_BOOT(target) ((target) == (sampleAtResetTargetArray[ \ ++ (mvCtrlModelGet() == MV_6180_DEV_ID)? MSAR_BOOT_MODE_6180 \ ++ (MV_REG_READ(MPP_SAMPLE_AT_RESET)):((MV_REG_READ(MPP_SAMPLE_AT_RESET)\ ++ & MSAR_BOOT_MODE_MASK) >> MSAR_BOOT_MODE_OFFS)])) ++ ++ ++#define MV_CHANGE_BOOT_CS(target) (((target) == DEV_BOOCS)?\ ++ sampleAtResetTargetArray[(mvCtrlModelGet() == MV_6180_DEV_ID)? \ ++ MSAR_BOOT_MODE_6180(MV_REG_READ(MPP_SAMPLE_AT_RESET)): \ ++ ((MV_REG_READ(MPP_SAMPLE_AT_RESET) & MSAR_BOOT_MODE_MASK)\ ++ >> MSAR_BOOT_MODE_OFFS)]:(target)) ++ ++#define TCLK_TO_COUNTER_RATIO 1 /* counters running in Tclk */ ++ ++#define BOOT_TARGETS_NAME_ARRAY { \ ++ TBL_TERM, \ ++ TBL_TERM, \ ++ BOOT_ROM_CS, \ ++ TBL_TERM, \ ++ BOOT_ROM_CS, \ ++ BOOT_ROM_CS, \ ++ TBL_TERM, \ ++ TBL_TERM \ ++} ++ ++#define BOOT_TARGETS_NAME_ARRAY_6180 { \ ++ TBL_TERM, \ ++ BOOT_ROM_CS, \ ++ TBL_TERM, \ ++ TBL_TERM, \ ++ TBL_TERM, \ ++ BOOT_ROM_CS, \ ++ TBL_TERM, \ ++ TBL_TERM \ ++} ++ ++ ++/* For old competability */ ++#define DEVICE_CS0 NFLASH_CS ++#define DEVICE_CS1 SPI_CS ++#define DEVICE_CS2 BOOT_ROM_CS ++#define DEVICE_CS3 DEV_BOOCS ++#define MV_BOOTDEVICE_INDEX 0 ++ ++#define START_DEV_CS DEV_CS0 ++#define DEV_TO_TARGET(dev) ((dev) + DEVICE_CS0) ++ ++#define PCI_IF0_MEM0 PEX0_MEM ++#define PCI_IF0_IO PEX0_IO ++ ++ ++/* This enumerator defines the Marvell controller target ID */ ++typedef enum _mvTargetId ++{ ++ DRAM_TARGET_ID = 0 , /* Port 0 -> DRAM interface */ ++ DEV_TARGET_ID = 1, /* Port 1 -> Nand/SPI */ ++ PEX0_TARGET_ID = 4 , /* Port 4 -> PCI Express0 */ ++ CRYPT_TARGET_ID = 3 , /* Port 3 --> Crypto Engine */ ++ SAGE_TARGET_ID = 12 , /* Port 12 -> SAGE Unit */ ++ MAX_TARGETS_ID ++}MV_TARGET_ID; ++ ++ ++/* This enumerator described the possible Controller paripheral targets. */ ++/* Controller peripherals are designated memory/IO address spaces that the */ ++/* controller can access. They are also refered as "targets" */ ++typedef enum _mvTarget ++{ ++ TBL_TERM = -1, /* none valid target, used as targets list terminator*/ ++ SDRAM_CS0, /* SDRAM chip select 0 */ ++ SDRAM_CS1, /* SDRAM chip select 1 */ ++ SDRAM_CS2, /* SDRAM chip select 2 */ ++ SDRAM_CS3, /* SDRAM chip select 3 */ ++ PEX0_MEM, /* PCI Express 0 Memory */ ++ PEX0_IO, /* PCI Express 0 IO */ ++ INTER_REGS, /* Internal registers */ ++ NFLASH_CS, /* NFLASH_CS */ ++ SPI_CS, /* SPI_CS */ ++ BOOT_ROM_CS, /* BOOT_ROM_CS */ ++ DEV_BOOCS, /* DEV_BOOCS */ ++ CRYPT_ENG, /* Crypto Engine */ ++#ifdef MV_INCLUDE_SAGE ++ SAGE_UNIT, /* SAGE Unit */ ++#endif ++ MAX_TARGETS ++ ++}MV_TARGET; ++ ++#define TARGETS_DEF_ARRAY { \ ++ {0x0E, DRAM_TARGET_ID }, /* SDRAM_CS0 */ \ ++ {0x0D, DRAM_TARGET_ID }, /* SDRAM_CS1 */ \ ++ {0x0B, DRAM_TARGET_ID }, /* SDRAM_CS0 */ \ ++ {0x07, DRAM_TARGET_ID }, /* SDRAM_CS1 */ \ ++ {0xE8, PEX0_TARGET_ID }, /* PEX0_MEM */ \ ++ {0xE0, PEX0_TARGET_ID }, /* PEX0_IO */ \ ++ {0xFF, 0xFF }, /* INTER_REGS */ \ ++ {0x2F, DEV_TARGET_ID }, /* NFLASH_CS */ \ ++ {0x1E, DEV_TARGET_ID }, /* SPI_CS */ \ ++ {0x1D, DEV_TARGET_ID }, /* BOOT_ROM_CS */ \ ++ {0x1E, DEV_TARGET_ID }, /* DEV_BOOCS */ \ ++ {0x01, CRYPT_TARGET_ID}, /* CRYPT_ENG */ \ ++ {0x00, SAGE_TARGET_ID } \ ++} ++ ++ ++#define TARGETS_NAME_ARRAY { \ ++ "SDRAM_CS0", /* SDRAM_CS0 */ \ ++ "SDRAM_CS1", /* SDRAM_CS1 */ \ ++ "SDRAM_CS2", /* SDRAM_CS2 */ \ ++ "SDRAM_CS3", /* SDRAM_CS3 */ \ ++ "PEX0_MEM", /* PEX0_MEM */ \ ++ "PEX0_IO", /* PEX0_IO */ \ ++ "INTER_REGS", /* INTER_REGS */ \ ++ "NFLASH_CS", /* NFLASH_CS */ \ ++ "SPI_CS", /* SPI_CS */ \ ++ "BOOT_ROM_CS", /* BOOT_ROM_CS */ \ ++ "DEV_BOOTCS", /* DEV_BOOCS */ \ ++ "CRYPT_ENG", /* CRYPT_ENG */ \ ++ "SAGE_UNIT" /* SAGE_UNIT */ \ ++} ++#endif /* MV_ASMLANGUAGE */ ++ ++ ++#endif +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/mvCtrlEnvSpec.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,257 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvCtrlEnvSpech ++#define __INCmvCtrlEnvSpech ++ ++#include "mvDeviceId.h" ++#include "mvSysHwConfig.h" ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++#define MV_ARM_SOC ++#define SOC_NAME_PREFIX "MV88F" ++ ++ ++/* units base and port numbers */ ++#ifdef MV_ASMLANGUAGE ++#define XOR_UNIT_BASE(unit) 0x60800 ++#else ++#define MV_XOR_REG_BASE 0x60000 ++#define XOR_UNIT_BASE(unit) ((unit)? 0x60900:0x60800) ++#endif ++ ++#define TDM_REG_BASE 0xD0000 ++#define USB_REG_BASE(dev) 0x50000 ++#define AUDIO_REG_BASE 0xA0000 ++#define SATA_REG_BASE 0x80000 ++#define MV_CESA_REG_BASE 0x3D000 ++#define MV_CESA_TDMA_REG_BASE 0x30000 ++#define MV_SDIO_REG_BASE 0x90000 ++#define MV_ETH_REG_BASE(port) (((port) == 0) ? 0x72000 : 0x76000) ++#define MV_UART_CHAN_BASE(chanNum) (0x12000 + (chanNum * 0x100)) ++#define DRAM_BASE 0x0 ++#define CNTMR_BASE 0x20300 ++#define TWSI_SLAVE_BASE(chanNum) 0x11000 ++#define PEX_IF_BASE(pexIf) 0x40000 ++#define MPP_REG_BASE 0x10000 ++#define TSU_GLOBAL_REG_BASE 0xB4000 ++#define MAX_AHB_TO_MBUS_REG_BASE 0x20000 ++ ++#define INTER_REGS_SIZE _1M ++/* This define describes the TWSI interrupt bit and location */ ++#define TWSI_CPU_MAIN_INT_CAUSE_REG 0x20200 ++#define TWSI0_CPU_MAIN_INT_BIT (1<<29) ++#define TWSI_SPEED 100000 ++ ++#define MV_GPP_MAX_GROUP 2 ++#define MV_CNTMR_MAX_COUNTER 2 ++#define MV_UART_MAX_CHAN 2 ++#define MV_XOR_MAX_UNIT 2 ++#define MV_XOR_MAX_CHAN 4 /* total channels for all units together*/ ++#define MV_XOR_MAX_CHAN_PER_UNIT 2 /* channels for units */ ++#define MV_SATA_MAX_CHAN 2 ++ ++#define MV_6281_MPP_MAX_MODULE 2 ++#define MV_6192_MPP_MAX_MODULE 1 ++#define MV_6190_MPP_MAX_MODULE 1 ++#define MV_6180_MPP_MAX_MODULE 2 ++#define MV_6281_MPP_MAX_GROUP 7 ++#define MV_6192_MPP_MAX_GROUP 4 ++#define MV_6190_MPP_MAX_GROUP 4 ++#define MV_6180_MPP_MAX_GROUP 3 ++ ++#define MV_DRAM_MAX_CS 4 ++ ++/* This define describes the maximum number of supported PCI\PCIX Interfaces*/ ++#define MV_PCI_MAX_IF 0 ++#define MV_PCI_START_IF 0 ++ ++/* This define describes the maximum number of supported PEX Interfaces */ ++#define MV_INCLUDE_PEX0 ++#define MV_DISABLE_PEX_DEVICE_BAR ++#define MV_PEX_MAX_IF 1 ++#define MV_PEX_START_IF MV_PCI_MAX_IF ++ ++/* This define describes the maximum number of supported PCI Interfaces */ ++#define MV_PCI_IF_MAX_IF (MV_PEX_MAX_IF+MV_PCI_MAX_IF) ++ ++#define MV_ETH_MAX_PORTS 2 ++#define MV_6281_ETH_MAX_PORTS 2 ++#define MV_6192_ETH_MAX_PORTS 2 ++#define MV_6190_ETH_MAX_PORTS 1 ++#define MV_6180_ETH_MAX_PORTS 1 ++ ++#define MV_IDMA_MAX_CHAN 0 ++ ++#define MV_USB_MAX_PORTS 1 ++ ++#define MV_USB_VERSION 1 ++ ++ ++#define MV_6281_NAND 1 ++#define MV_6192_NAND 1 ++#define MV_6190_NAND 1 ++#define MV_6180_NAND 0 ++ ++#define MV_6281_SDIO 1 ++#define MV_6192_SDIO 1 ++#define MV_6190_SDIO 1 ++#define MV_6180_SDIO 1 ++ ++#define MV_6281_TS 1 ++#define MV_6192_TS 1 ++#define MV_6190_TS 0 ++#define MV_6180_TS 0 ++ ++#define MV_6281_AUDIO 1 ++#define MV_6192_AUDIO 1 ++#define MV_6190_AUDIO 0 ++#define MV_6180_AUDIO 1 ++ ++#define MV_6281_TDM 1 ++#define MV_6192_TDM 1 ++#define MV_6190_TDM 0 ++#define MV_6180_TDM 0 ++ ++#define MV_DEVICE_MAX_CS 4 ++ ++/* Others */ ++#define PEX_HOST_BUS_NUM(pciIf) (pciIf) ++#define PEX_HOST_DEV_NUM(pciIf) 0 ++ ++#define PCI_IO(pciIf) (PEX0_IO) ++#define PCI_MEM(pciIf, memNum) (PEX0_MEM0) ++/* CESA version #2: One channel, 2KB SRAM, TDMA */ ++#if defined(MV_CESA_CHAIN_MODE_SUPPORT) ++ #define MV_CESA_VERSION 3 ++#else ++#define MV_CESA_VERSION 2 ++#endif ++#define MV_CESA_SRAM_SIZE 2*1024 ++/* This define describes the maximum number of supported Ethernet ports */ ++#define MV_ETH_VERSION 4 ++#define MV_ETH_MAX_RXQ 8 ++#define MV_ETH_MAX_TXQ 8 ++#define MV_ETH_PORT_SGMII { MV_FALSE, MV_FALSE } ++/* This define describes the the support of USB */ ++#define MV_USB_VERSION 1 ++ ++#define MV_INCLUDE_SDRAM_CS0 ++#define MV_INCLUDE_SDRAM_CS1 ++#define MV_INCLUDE_SDRAM_CS2 ++#define MV_INCLUDE_SDRAM_CS3 ++ ++#define MV_INCLUDE_DEVICE_CS0 ++#define MV_INCLUDE_DEVICE_CS1 ++#define MV_INCLUDE_DEVICE_CS2 ++#define MV_INCLUDE_DEVICE_CS3 ++ ++#define MPP_GROUP_1_TYPE {\ ++ {0, 0, 0}, /* Reserved for AUTO */ \ ++ {0x22220000, 0x22222222, 0x2222}, /* TDM */ \ ++ {0x44440000, 0x00044444, 0x0000}, /* AUDIO */ \ ++ {0x33330000, 0x33003333, 0x0033}, /* RGMII */ \ ++ {0x33330000, 0x03333333, 0x0033}, /* GMII */ \ ++ {0x11110000, 0x11111111, 0x0001}, /* TS */ \ ++ {0x33330000, 0x33333333, 0x3333} /* MII */ \ ++} ++ ++#define MPP_GROUP_2_TYPE {\ ++ {0, 0, 0}, /* Reserved for AUTO */ \ ++ {0x22220000, 0x22222222, 0x22}, /* TDM */ \ ++ {0x44440000, 0x00044444, 0x0}, /* AUDIO */ \ ++ {0, 0, 0}, /* N_A */ \ ++ {0, 0, 0}, /* N_A */ \ ++ {0x11110000, 0x11111111, 0x01} /* TS */ \ ++} ++ ++#ifndef MV_ASMLANGUAGE ++ ++/* This enumerator defines the Marvell Units ID */ ++typedef enum _mvUnitId ++{ ++ DRAM_UNIT_ID, ++ PEX_UNIT_ID, ++ ETH_GIG_UNIT_ID, ++ USB_UNIT_ID, ++ IDMA_UNIT_ID, ++ XOR_UNIT_ID, ++ SATA_UNIT_ID, ++ TDM_UNIT_ID, ++ UART_UNIT_ID, ++ CESA_UNIT_ID, ++ SPI_UNIT_ID, ++ AUDIO_UNIT_ID, ++ SDIO_UNIT_ID, ++ TS_UNIT_ID, ++ MAX_UNITS_ID ++ ++}MV_UNIT_ID; ++ ++#endif ++ ++#endif /* __INCmvCtrlEnvSpech */ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,1048 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++/* includes */ ++#include "ctrlEnv/sys/mvAhbToMbus.h" ++#include "ctrlEnv/mvCtrlEnvAddrDec.h" ++ ++#undef MV_DEBUG ++/* defines */ ++#ifdef MV_DEBUG ++ #define DB(x) x ++#else ++ #define DB(x) ++#endif ++ ++/* typedefs */ ++ ++ ++/* CPU address remap registers offsets are inconsecutive. This struct */ ++/* describes address remap register offsets */ ++typedef struct _ahbToMbusRemapRegOffs ++{ ++ MV_U32 lowRegOffs; /* Low 32-bit remap register offset */ ++ MV_U32 highRegOffs; /* High 32 bit remap register offset */ ++}AHB_TO_MBUS_REMAP_REG_OFFS; ++ ++/* locals */ ++static MV_STATUS ahbToMbusRemapRegOffsGet (MV_U32 winNum, ++ AHB_TO_MBUS_REMAP_REG_OFFS *pRemapRegs); ++ ++/******************************************************************************* ++* mvAhbToMbusInit - Initialize Ahb To Mbus Address Map ! ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_OK laways. ++* ++*******************************************************************************/ ++MV_STATUS mvAhbToMbusInit(void) ++{ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvAhbToMbusWinSet - Set CPU-to-peripheral winNum address window ++* ++* DESCRIPTION: ++* This function sets ++* address window, also known as address decode window. ++* A new address decode window is set for specified winNum address window. ++* If address decode window parameter structure enables the window, ++* the routine will also enable the winNum window, allowing CPU to access ++* the winNum window. ++* ++* INPUT: ++* winNum - Windows number. ++* pAddrDecWin - CPU winNum window data structure. ++* ++* OUTPUT: ++* N/A ++* ++* RETURN: ++* MV_OK if CPU winNum window was set correctly, MV_ERROR in case of ++* address window overlapps with other active CPU winNum window or ++* trying to assign 36bit base address while CPU does not support that. ++* The function returns MV_NOT_SUPPORTED, if the winNum is unsupported. ++* ++*******************************************************************************/ ++MV_STATUS mvAhbToMbusWinSet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin) ++{ ++ MV_TARGET_ATTRIB targetAttribs; ++ MV_DEC_REGS decRegs; ++ ++ /* Parameter checking */ ++ if (winNum >= MAX_AHB_TO_MBUS_WINS) ++ { ++ mvOsPrintf("mvAhbToMbusWinSet: ERR. Invalid winNum %d\n", winNum); ++ return MV_NOT_SUPPORTED; ++ } ++ ++ ++ /* read base register*/ ++ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) ++ { ++ decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum)); ++ } ++ else ++ { ++ decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_INTEREG_REG); ++ } ++ ++ /* check if address is aligned to the size */ ++ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) ++ { ++ mvOsPrintf("mvAhbToMbusWinSet:Error setting AHB to MBUS window %d to "\ ++ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", ++ winNum, ++ mvCtrlTargetNameGet(pAddrDecWin->target), ++ pAddrDecWin->addrWin.baseLow, ++ pAddrDecWin->addrWin.size); ++ return MV_ERROR; ++ } ++ ++ /* read control register*/ ++ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) ++ { ++ decRegs.sizeReg = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum)); ++ } ++ ++ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) ++ { ++ mvOsPrintf("mvAhbToMbusWinSet:mvCtrlAddrDecToReg Failed\n"); ++ return MV_ERROR; ++ } ++ ++ /* enable\Disable */ ++ if (MV_TRUE == pAddrDecWin->enable) ++ { ++ decRegs.sizeReg |= ATMWCR_WIN_ENABLE; ++ } ++ else ++ { ++ decRegs.sizeReg &= ~ATMWCR_WIN_ENABLE; ++ } ++ ++ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); ++ ++ /* set attributes */ ++ decRegs.sizeReg &= ~ATMWCR_WIN_ATTR_MASK; ++ decRegs.sizeReg |= targetAttribs.attrib << ATMWCR_WIN_ATTR_OFFS; ++ /* set target ID */ ++ decRegs.sizeReg &= ~ATMWCR_WIN_TARGET_MASK; ++ decRegs.sizeReg |= targetAttribs.targetId << ATMWCR_WIN_TARGET_OFFS; ++ ++#if !defined(MV_RUN_FROM_FLASH) ++ /* To be on the safe side we disable the window before writing the */ ++ /* new values. */ ++ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) ++ { ++ mvAhbToMbusWinEnable(winNum,MV_FALSE); ++ } ++#endif ++ ++ /* 3) Write to address decode Base Address Register */ ++ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) ++ { ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum), decRegs.baseReg); ++ } ++ else ++ { ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_INTEREG_REG, decRegs.baseReg); ++ } ++ ++ ++ /* Internal register space have no size */ ++ /* register. Do not perform size register assigment for those targets */ ++ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) ++ { ++ /* Write to address decode Size Register */ ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), decRegs.sizeReg); ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvAhbToMbusWinGet - Get CPU-to-peripheral winNum address window ++* ++* DESCRIPTION: ++* Get the CPU peripheral winNum address window. ++* ++* INPUT: ++* winNum - Peripheral winNum enumerator ++* ++* OUTPUT: ++* pAddrDecWin - CPU winNum window information data structure. ++* ++* RETURN: ++* MV_OK if winNum exist, MV_ERROR otherwise. ++* ++*******************************************************************************/ ++MV_STATUS mvAhbToMbusWinGet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin) ++{ ++ MV_DEC_REGS decRegs; ++ MV_TARGET_ATTRIB targetAttrib; ++ ++ ++ /* Parameter checking */ ++ if (winNum >= MAX_AHB_TO_MBUS_WINS) ++ { ++ mvOsPrintf("mvAhbToMbusWinGet: ERR. Invalid winNum %d\n", winNum); ++ return MV_NOT_SUPPORTED; ++ } ++ ++ ++ /* Internal register space size have no size register*/ ++ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) ++ { ++ decRegs.sizeReg = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum)); ++ } ++ else ++ { ++ decRegs.sizeReg = 0; ++ } ++ ++ ++ /* Read base and size */ ++ if (winNum != MV_AHB_TO_MBUS_INTREG_WIN) ++ { ++ decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum)); ++ } ++ else ++ { ++ decRegs.baseReg = MV_REG_READ(AHB_TO_MBUS_WIN_INTEREG_REG); ++ } ++ ++ ++ ++ if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) ++ { ++ mvOsPrintf("mvAhbToMbusWinGet: mvCtrlRegToAddrDec Failed \n"); ++ return MV_ERROR; ++ } ++ ++ if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) ++ { ++ pAddrDecWin->addrWin.size = INTER_REGS_SIZE; ++ pAddrDecWin->target = INTER_REGS; ++ pAddrDecWin->enable = MV_TRUE; ++ ++ return MV_OK; ++ } ++ ++ ++ if (decRegs.sizeReg & ATMWCR_WIN_ENABLE) ++ { ++ pAddrDecWin->enable = MV_TRUE; ++ } ++ else ++ { ++ pAddrDecWin->enable = MV_FALSE; ++ ++ } ++ ++ ++ ++ if (-1 == pAddrDecWin->addrWin.size) ++ { ++ return MV_ERROR; ++ } ++ ++ /* attrib and targetId */ ++ targetAttrib.attrib = (decRegs.sizeReg & ATMWCR_WIN_ATTR_MASK) >> ++ ATMWCR_WIN_ATTR_OFFS; ++ targetAttrib.targetId = (decRegs.sizeReg & ATMWCR_WIN_TARGET_MASK) >> ++ ATMWCR_WIN_TARGET_OFFS; ++ ++ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvAhbToMbusWinTargetGet - Get Window number associated with target ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_U32 mvAhbToMbusWinTargetGet(MV_TARGET target) ++{ ++ MV_AHB_TO_MBUS_DEC_WIN decWin; ++ MV_U32 winNum; ++ ++ /* Check parameters */ ++ if (target >= MAX_TARGETS) ++ { ++ mvOsPrintf("mvAhbToMbusWinTargetGet: target %d is Illigal\n", target); ++ return 0xffffffff; ++ } ++ ++ if (INTER_REGS == target) ++ { ++ return MV_AHB_TO_MBUS_INTREG_WIN; ++ } ++ ++ for (winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS ; winNum++) ++ { ++ if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) ++ continue; ++ ++ if (mvAhbToMbusWinGet(winNum,&decWin) != MV_OK) ++ { ++ mvOsPrintf("mvAhbToMbusWinTargetGet: mvAhbToMbusWinGet fail\n"); ++ return 0xffffffff; ++ ++ } ++ ++ if (decWin.enable == MV_TRUE) ++ { ++ if (decWin.target == target) ++ { ++ return winNum; ++ } ++ ++ } ++ ++ } ++ ++ return 0xFFFFFFFF; ++ ++ ++} ++ ++/******************************************************************************* ++* mvAhbToMbusWinAvailGet - Get First Available window number. ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_U32 mvAhbToMbusWinAvailGet(MV_VOID) ++{ ++ MV_AHB_TO_MBUS_DEC_WIN decWin; ++ MV_U32 winNum; ++ ++ for (winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS ; winNum++) ++ { ++ if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) ++ continue; ++ ++ if (mvAhbToMbusWinGet(winNum,&decWin) != MV_OK) ++ { ++ mvOsPrintf("mvAhbToMbusWinTargetGet: mvAhbToMbusWinGet fail\n"); ++ return 0xffffffff; ++ ++ } ++ ++ if (decWin.enable == MV_FALSE) ++ { ++ return winNum; ++ } ++ ++ } ++ ++ return 0xFFFFFFFF; ++} ++ ++ ++/******************************************************************************* ++* mvAhbToMbusWinEnable - Enable/disable a CPU address decode window ++* ++* DESCRIPTION: ++* This function enable/disable a CPU address decode window. ++* if parameter 'enable' == MV_TRUE the routine will enable the ++* window, thus enabling CPU accesses (before enabling the window it is ++* tested for overlapping). Otherwise, the window will be disabled. ++* ++* INPUT: ++* winNum - Peripheral winNum enumerator. ++* enable - Enable/disable parameter. ++* ++* OUTPUT: ++* N/A ++* ++* RETURN: ++* MV_ERROR if protection window number was wrong, or the window ++* overlapps other winNum window. ++* ++*******************************************************************************/ ++MV_STATUS mvAhbToMbusWinEnable(MV_U32 winNum, MV_BOOL enable) ++{ ++ ++ /* Parameter checking */ ++ if (winNum >= MAX_AHB_TO_MBUS_WINS) ++ { ++ mvOsPrintf("mvAhbToMbusWinEnable: ERR. Invalid winNum %d\n", winNum); ++ return MV_NOT_SUPPORTED; ++ } ++ ++ /* Internal registers bar can't be disable or enabled */ ++ if (winNum == MV_AHB_TO_MBUS_INTREG_WIN) ++ { ++ return (enable ? MV_OK : MV_ERROR); ++ } ++ ++ if (enable == MV_TRUE) ++ { ++ /* enable the window */ ++ MV_REG_BIT_SET(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ATMWCR_WIN_ENABLE); ++ } ++ else ++ { /* Disable address decode winNum window */ ++ MV_REG_BIT_RESET(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ATMWCR_WIN_ENABLE); ++ } ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvAhbToMbusWinRemap - Set CPU remap register for address windows. ++* ++* DESCRIPTION: ++* After a CPU address hits one of PCI address decode windows there is an ++* option to remap the address to a different one. For example, CPU ++* executes a read from PCI winNum window address 0x1200.0000. This ++* can be modified so the address on the PCI bus would be 0x1400.0000 ++* Using the PCI address remap mechanism. ++* ++* INPUT: ++* winNum - Peripheral winNum enumerator. Must be a PCI winNum. ++* pAddrDecWin - CPU winNum window information data structure. ++* Note that caller has to fill in the base field only. The ++* size field is ignored. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_ERROR if winNum is not a PCI one, MV_OK otherwise. ++* ++*******************************************************************************/ ++MV_U32 mvAhbToMbusWinRemap(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) ++{ ++ MV_U32 baseAddr; ++ AHB_TO_MBUS_REMAP_REG_OFFS remapRegOffs; ++ ++ MV_U32 effectiveBaseAddress=0, ++ baseAddrValue=0,windowSizeValue=0; ++ ++ ++ /* Get registers offsets of given winNum */ ++ if (MV_NO_SUCH == ahbToMbusRemapRegOffsGet(winNum, &remapRegOffs)) ++ { ++ return 0xffffffff; ++ } ++ ++ /* 1) Set address remap low */ ++ baseAddr = pAddrWin->baseLow; ++ ++ /* Check base address aligment */ ++ /* ++ if (MV_IS_NOT_ALIGN(baseAddr, ATMWRLR_REMAP_LOW_ALIGNMENT)) ++ { ++ mvOsPrintf("mvAhbToMbusPciRemap: Warning. Target base 0x%x unaligned\n", ++ baseAddr); ++ return MV_ERROR; ++ } ++ */ ++ ++ /* BaseLow[31:16] => base register [31:16] */ ++ baseAddr = baseAddr & ATMWRLR_REMAP_LOW_MASK; ++ ++ MV_REG_WRITE(remapRegOffs.lowRegOffs, baseAddr); ++ ++ MV_REG_WRITE(remapRegOffs.highRegOffs, pAddrWin->baseHigh); ++ ++ ++ baseAddrValue = MV_REG_READ(AHB_TO_MBUS_WIN_BASE_REG(winNum)); ++ windowSizeValue = MV_REG_READ(AHB_TO_MBUS_WIN_CTRL_REG(winNum)); ++ ++ baseAddrValue &= ATMWBR_BASE_MASK; ++ windowSizeValue &=ATMWCR_WIN_SIZE_MASK; ++ ++ /* Start calculating the effective Base Address */ ++ effectiveBaseAddress = baseAddrValue ; ++ ++ /* The effective base address will be combined from the chopped (if any) ++ remap value (according to the size value and remap mechanism) and the ++ window's base address */ ++ effectiveBaseAddress |= (((windowSizeValue) | 0xffff) & pAddrWin->baseLow); ++ /* If the effectiveBaseAddress exceed the window boundaries return an ++ invalid value. */ ++ ++ if (effectiveBaseAddress > (baseAddrValue + (windowSizeValue | 0xffff))) ++ { ++ mvOsPrintf("mvAhbToMbusPciRemap: Error\n"); ++ return 0xffffffff; ++ } ++ ++ return effectiveBaseAddress; ++ ++ ++} ++/******************************************************************************* ++* mvAhbToMbusWinTargetSwap - Swap AhbToMbus windows between targets ++* ++* DESCRIPTION: ++* ++* INPUT: ++* target1 - CPU Interface target 1 ++* target2 - CPU Interface target 2 ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_ERROR if targets are illigal, or if one of the targets is not ++* associated to a valid window . ++* MV_OK otherwise. ++* ++*******************************************************************************/ ++ ++ ++MV_STATUS mvAhbToMbusWinTargetSwap(MV_TARGET target1,MV_TARGET target2) ++{ ++ MV_U32 winNum1,winNum2; ++ MV_AHB_TO_MBUS_DEC_WIN winDec1,winDec2,winDecTemp; ++ AHB_TO_MBUS_REMAP_REG_OFFS remapRegs1,remapRegs2; ++ MV_U32 remapBaseLow1=0,remapBaseLow2=0; ++ MV_U32 remapBaseHigh1=0,remapBaseHigh2=0; ++ ++ ++ /* Check parameters */ ++ if (target1 >= MAX_TARGETS) ++ { ++ mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d is Illigal\n", target1); ++ return MV_ERROR; ++ } ++ ++ if (target2 >= MAX_TARGETS) ++ { ++ mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d is Illigal\n", target1); ++ return MV_ERROR; ++ } ++ ++ ++ /* get window associated with this target */ ++ winNum1 = mvAhbToMbusWinTargetGet(target1); ++ ++ if (winNum1 == 0xffffffff) ++ { ++ mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d has illigal win %d\n", ++ target1,winNum1); ++ return MV_ERROR; ++ ++ } ++ ++ /* get window associated with this target */ ++ winNum2 = mvAhbToMbusWinTargetGet(target2); ++ ++ if (winNum2 == 0xffffffff) ++ { ++ mvOsPrintf("mvAhbToMbusWinTargetSwap: target %d has illigal win %d\n", ++ target2,winNum2); ++ return MV_ERROR; ++ ++ } ++ ++ /* now Get original values of both Windows */ ++ if (MV_OK != mvAhbToMbusWinGet(winNum1,&winDec1)) ++ { ++ mvOsPrintf("mvAhbToMbusWinTargetSwap: mvAhbToMbusWinGet failed win %d\n", ++ winNum1); ++ return MV_ERROR; ++ ++ } ++ if (MV_OK != mvAhbToMbusWinGet(winNum2,&winDec2)) ++ { ++ mvOsPrintf("mvAhbToMbusWinTargetSwap: mvAhbToMbusWinGet failed win %d\n", ++ winNum2); ++ return MV_ERROR; ++ ++ } ++ ++ ++ /* disable both windows */ ++ if (MV_OK != mvAhbToMbusWinEnable(winNum1,MV_FALSE)) ++ { ++ mvOsPrintf("mvAhbToMbusWinTargetSwap: failed to enable window %d\n", ++ winNum1); ++ return MV_ERROR; ++ ++ } ++ if (MV_OK != mvAhbToMbusWinEnable(winNum2,MV_FALSE)) ++ { ++ mvOsPrintf("mvAhbToMbusWinTargetSwap: failed to enable windo %d\n", ++ winNum2); ++ return MV_ERROR; ++ ++ } ++ ++ ++ /* now swap targets */ ++ ++ /* first save winDec2 values */ ++ winDecTemp.addrWin.baseHigh = winDec2.addrWin.baseHigh; ++ winDecTemp.addrWin.baseLow = winDec2.addrWin.baseLow; ++ winDecTemp.addrWin.size = winDec2.addrWin.size; ++ winDecTemp.enable = winDec2.enable; ++ winDecTemp.target = winDec2.target; ++ ++ /* winDec2 = winDec1 */ ++ winDec2.addrWin.baseHigh = winDec1.addrWin.baseHigh; ++ winDec2.addrWin.baseLow = winDec1.addrWin.baseLow; ++ winDec2.addrWin.size = winDec1.addrWin.size; ++ winDec2.enable = winDec1.enable; ++ winDec2.target = winDec1.target; ++ ++ ++ /* winDec1 = winDecTemp */ ++ winDec1.addrWin.baseHigh = winDecTemp.addrWin.baseHigh; ++ winDec1.addrWin.baseLow = winDecTemp.addrWin.baseLow; ++ winDec1.addrWin.size = winDecTemp.addrWin.size; ++ winDec1.enable = winDecTemp.enable; ++ winDec1.target = winDecTemp.target; ++ ++ ++ /* now set the new values */ ++ ++ ++ mvAhbToMbusWinSet(winNum1,&winDec1); ++ mvAhbToMbusWinSet(winNum2,&winDec2); ++ ++ ++ ++ ++ ++ /* now we will treat the remap windows if exist */ ++ ++ ++ /* now check if one or both windows has a remap window ++ as well after the swap ! */ ++ ++ /* if a window had a remap value differnt than the base value ++ before the swap , then after the swap the remap value will be ++ equal to the base value unless both windows has a remap windows*/ ++ ++ /* first get old values */ ++ if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum1,&remapRegs1)) ++ { ++ remapBaseLow1 = MV_REG_READ(remapRegs1.lowRegOffs); ++ remapBaseHigh1 = MV_REG_READ(remapRegs1.highRegOffs); ++ ++ } ++ if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2,&remapRegs2)) ++ { ++ remapBaseLow2 = MV_REG_READ(remapRegs2.lowRegOffs); ++ remapBaseHigh2 = MV_REG_READ(remapRegs2.highRegOffs); ++ ++ ++ } ++ ++ /* now do the swap */ ++ if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum1,&remapRegs1)) ++ { ++ if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2,&remapRegs2)) ++ { ++ /* Two windows has a remap !!! so swap */ ++ ++ MV_REG_WRITE(remapRegs2.highRegOffs,remapBaseHigh1); ++ MV_REG_WRITE(remapRegs2.lowRegOffs,remapBaseLow1); ++ ++ MV_REG_WRITE(remapRegs1.highRegOffs,remapBaseHigh2); ++ MV_REG_WRITE(remapRegs1.lowRegOffs,remapBaseLow2); ++ ++ ++ ++ } ++ else ++ { ++ /* remap == base */ ++ MV_REG_WRITE(remapRegs1.highRegOffs,winDec1.addrWin.baseHigh); ++ MV_REG_WRITE(remapRegs1.lowRegOffs,winDec1.addrWin.baseLow); ++ ++ } ++ ++ } ++ else if (MV_NO_SUCH != ahbToMbusRemapRegOffsGet(winNum2,&remapRegs2)) ++ { ++ /* remap == base */ ++ MV_REG_WRITE(remapRegs2.highRegOffs,winDec2.addrWin.baseHigh); ++ MV_REG_WRITE(remapRegs2.lowRegOffs,winDec2.addrWin.baseLow); ++ ++ } ++ ++ ++ ++ return MV_OK; ++ ++ ++} ++ ++ ++ ++#if defined(MV_88F1181) ++ ++/******************************************************************************* ++* mvAhbToMbusXbarCtrlSet - Set The CPU master Xbar arbitration. ++* ++* DESCRIPTION: ++* This function sets CPU Mbus Arbiter ++* ++* INPUT: ++* pPizzaArbArray - A priority Structure describing 16 "pizza slices". At ++* each clock cycle, the crossbar arbiter samples all ++* requests and gives the bus to the next agent according ++* to the "pizza". ++* ++* OUTPUT: ++* N/A ++* ++* RETURN: ++* MV_ERROR if paramers to function invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvMbusArbSet(MV_MBUS_ARB_TARGET *pPizzaArbArray) ++{ ++ MV_U32 sliceNum; ++ MV_U32 xbarCtrl = 0; ++ MV_MBUS_ARB_TARGET xbarTarget; ++ ++ /* 1) Set crossbar control low register */ ++ for (sliceNum = 0; sliceNum < MRLR_SLICE_NUM; sliceNum++) ++ { ++ xbarTarget = pPizzaArbArray[sliceNum]; ++ ++ /* sliceNum parameter check */ ++ if (xbarTarget > MAX_MBUS_ARB_TARGETS) ++ { ++ mvOsPrintf("mvAhbToMbusXbarCtrlSet: ERR. Can't set Target %d\n", ++ xbarTarget); ++ return MV_ERROR; ++ } ++ xbarCtrl |= (xbarTarget << MRLR_LOW_ARB_OFFS(sliceNum)); ++ } ++ /* Write to crossbar control low register */ ++ MV_REG_WRITE(MBUS_ARBITER_LOW_REG, xbarCtrl); ++ ++ xbarCtrl = 0; ++ ++ /* 2) Set crossbar control high register */ ++ for (sliceNum = MRLR_SLICE_NUM; ++ sliceNum < MRLR_SLICE_NUM+MRHR_SLICE_NUM; ++ sliceNum++) ++ { ++ ++ xbarTarget = pPizzaArbArray[sliceNum]; ++ ++ /* sliceNum parameter check */ ++ if (xbarTarget > MAX_MBUS_ARB_TARGETS) ++ { ++ mvOsPrintf("mvAhbToMbusXbarCtrlSet: ERR. Can't set Target %d\n", ++ xbarTarget); ++ return MV_ERROR; ++ } ++ xbarCtrl |= (xbarTarget << MRHR_HIGH_ARB_OFFS(sliceNum)); ++ } ++ /* Write to crossbar control high register */ ++ MV_REG_WRITE(MBUS_ARBITER_HIGH_REG, xbarCtrl); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvMbusArbCtrlSet - Set MBus Arbiter control register ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ctrl - pointer to MV_MBUS_ARB_CTRL register ++* ++* OUTPUT: ++* N/A ++* ++* RETURN: ++* MV_ERROR if paramers to function invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvMbusArbCtrlSet(MV_MBUS_ARB_CTRL *ctrl) ++{ ++ ++ if (ctrl->highPrio == MV_FALSE) ++ { ++ MV_REG_BIT_RESET(MBUS_ARBITER_CTRL_REG, MACR_ARB_ARM_TOP); ++ } ++ else ++ { ++ MV_REG_BIT_SET(MBUS_ARBITER_CTRL_REG, MACR_ARB_ARM_TOP); ++ } ++ ++ if (ctrl->fixedRoundRobin == MV_FALSE) ++ { ++ MV_REG_BIT_RESET(MBUS_ARBITER_CTRL_REG, MACR_ARB_TARGET_FIXED); ++ } ++ else ++ { ++ MV_REG_BIT_SET(MBUS_ARBITER_CTRL_REG, MACR_ARB_TARGET_FIXED); ++ } ++ ++ if (ctrl->starvEn == MV_FALSE) ++ { ++ MV_REG_BIT_RESET(MBUS_ARBITER_CTRL_REG, MACR_ARB_REQ_CTRL_EN); ++ } ++ else ++ { ++ MV_REG_BIT_SET(MBUS_ARBITER_CTRL_REG, MACR_ARB_REQ_CTRL_EN); ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvMbusArbCtrlGet - Get MBus Arbiter control register ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ctrl - pointer to MV_MBUS_ARB_CTRL register ++* ++* OUTPUT: ++* ctrl - pointer to MV_MBUS_ARB_CTRL register ++* ++* RETURN: ++* MV_ERROR if paramers to function invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvMbusArbCtrlGet(MV_MBUS_ARB_CTRL *ctrl) ++{ ++ ++ MV_U32 ctrlReg = MV_REG_READ(MBUS_ARBITER_CTRL_REG); ++ ++ if (ctrlReg & MACR_ARB_ARM_TOP) ++ { ++ ctrl->highPrio = MV_TRUE; ++ } ++ else ++ { ++ ctrl->highPrio = MV_FALSE; ++ } ++ ++ if (ctrlReg & MACR_ARB_TARGET_FIXED) ++ { ++ ctrl->fixedRoundRobin = MV_TRUE; ++ } ++ else ++ { ++ ctrl->fixedRoundRobin = MV_FALSE; ++ } ++ ++ if (ctrlReg & MACR_ARB_REQ_CTRL_EN) ++ { ++ ctrl->starvEn = MV_TRUE; ++ } ++ else ++ { ++ ctrl->starvEn = MV_FALSE; ++ } ++ ++ ++ return MV_OK; ++} ++ ++#endif /* #if defined(MV_88F1181) */ ++ ++ ++ ++/******************************************************************************* ++* ahbToMbusRemapRegOffsGet - Get CPU address remap register offsets ++* ++* DESCRIPTION: ++* CPU to PCI address remap registers offsets are inconsecutive. ++* This function returns PCI address remap registers offsets. ++* ++* INPUT: ++* winNum - Address decode window number. See MV_U32 enumerator. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_ERROR if winNum is not a PCI one. ++* ++*******************************************************************************/ ++static MV_STATUS ahbToMbusRemapRegOffsGet(MV_U32 winNum, ++ AHB_TO_MBUS_REMAP_REG_OFFS *pRemapRegs) ++{ ++ switch (winNum) ++ { ++ case 0: ++ case 1: ++ pRemapRegs->lowRegOffs = AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum); ++ pRemapRegs->highRegOffs = AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum); ++ break; ++ case 2: ++ case 3: ++ if((mvCtrlModelGet() == MV_5281_DEV_ID) || ++ (mvCtrlModelGet() == MV_1281_DEV_ID) || ++ (mvCtrlModelGet() == MV_6183_DEV_ID) || ++ (mvCtrlModelGet() == MV_6183L_DEV_ID)) ++ { ++ pRemapRegs->lowRegOffs = AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum); ++ pRemapRegs->highRegOffs = AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum); ++ break; ++ } ++ else ++ { ++ pRemapRegs->lowRegOffs = 0; ++ pRemapRegs->highRegOffs = 0; ++ ++ DB(mvOsPrintf("ahbToMbusRemapRegOffsGet: ERR. Invalid winNum %d\n", ++ winNum)); ++ return MV_NO_SUCH; ++ } ++ default: ++ { ++ pRemapRegs->lowRegOffs = 0; ++ pRemapRegs->highRegOffs = 0; ++ ++ DB(mvOsPrintf("ahbToMbusRemapRegOffsGet: ERR. Invalid winNum %d\n", ++ winNum)); ++ return MV_NO_SUCH; ++ } ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvAhbToMbusAddDecShow - Print the AHB to MBus bridge address decode map. ++* ++* DESCRIPTION: ++* This function print the CPU address decode map. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvAhbToMbusAddDecShow(MV_VOID) ++{ ++ MV_AHB_TO_MBUS_DEC_WIN win; ++ MV_U32 winNum; ++ mvOsOutput( "\n" ); ++ mvOsOutput( "AHB To MBUS Bridge:\n" ); ++ mvOsOutput( "-------------------\n" ); ++ ++ for( winNum = 0; winNum < MAX_AHB_TO_MBUS_WINS; winNum++ ) ++ { ++ memset( &win, 0, sizeof(MV_AHB_TO_MBUS_DEC_WIN) ); ++ ++ mvOsOutput( "win%d - ", winNum ); ++ ++ if( mvAhbToMbusWinGet( winNum, &win ) == MV_OK ) ++ { ++ if( win.enable ) ++ { ++ mvOsOutput( "%s base %08x, ", ++ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); ++ mvOsOutput( "...." ); ++ mvSizePrint( win.addrWin.size ); ++ ++ mvOsOutput( "\n" ); ++ ++ } ++ else ++ mvOsOutput( "disable\n" ); ++ } ++ } ++ ++} ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbus.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,130 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvAhbToMbush ++#define __INCmvAhbToMbush ++ ++/* includes */ ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "ctrlEnv/sys/mvAhbToMbusRegs.h" ++#include "ctrlEnv/mvCtrlEnvAddrDec.h" ++ ++/* defines */ ++ ++#if defined(MV_88F1181) ++/* This enumerator defines the Marvell controller possible MBUS arbiter */ ++/* target ports. It is used to define crossbar priority scheame (pizza) */ ++typedef enum _mvMBusArbTargetId ++{ ++ DRAM_MBUS_ARB_TARGET = 0, /* Port 0 -> DRAM interface */ ++ TWSI_MBUS_ARB_TARGET = 1, /* Port 1 -> TWSI */ ++ ARM_MBUS_ARB_TARGET = 2, /* Port 2 -> ARM */ ++ PEX1_MBUS_ARB_TARGET = 3, /* Port 3 -> PCI Express 1 */ ++ PEX0_MBUS_ARB_TARGET = 4, /* Port 4 -> PCI Express0 */ ++ MAX_MBUS_ARB_TARGETS ++}MV_MBUS_ARB_TARGET; ++ ++typedef struct _mvMBusArbCtrl ++{ ++ MV_BOOL starvEn; ++ MV_BOOL highPrio; ++ MV_BOOL fixedRoundRobin; ++ ++}MV_MBUS_ARB_CTRL; ++ ++#endif /* #if defined(MV_88F1181) */ ++ ++typedef struct _mvAhbtoMbusDecWin ++{ ++ MV_TARGET target; ++ MV_ADDR_WIN addrWin; /* An address window*/ ++ MV_BOOL enable; /* Address decode window is enabled/disabled */ ++ ++}MV_AHB_TO_MBUS_DEC_WIN; ++ ++/* mvAhbToMbus.h API list */ ++ ++MV_STATUS mvAhbToMbusInit(MV_VOID); ++MV_STATUS mvAhbToMbusWinSet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin); ++MV_STATUS mvAhbToMbusWinGet(MV_U32 winNum, MV_AHB_TO_MBUS_DEC_WIN *pAddrDecWin); ++MV_STATUS mvAhbToMbusWinEnable(MV_U32 winNum,MV_BOOL enable); ++MV_U32 mvAhbToMbusWinRemap(MV_U32 winNum, MV_ADDR_WIN *pAddrDecWin); ++MV_U32 mvAhbToMbusWinTargetGet(MV_TARGET target); ++MV_U32 mvAhbToMbusWinAvailGet(MV_VOID); ++MV_STATUS mvAhbToMbusWinTargetSwap(MV_TARGET target1,MV_TARGET target2); ++ ++#if defined(MV_88F1181) ++ ++MV_STATUS mvMbusArbSet(MV_MBUS_ARB_TARGET *pPizzaArbArray); ++MV_STATUS mvMbusArbCtrlSet(MV_MBUS_ARB_CTRL *ctrl); ++MV_STATUS mvMbusArbCtrlGet(MV_MBUS_ARB_CTRL *ctrl); ++ ++#endif /* #if defined(MV_88F1181) */ ++ ++ ++MV_VOID mvAhbToMbusAddDecShow(MV_VOID); ++ ++ ++#endif /* __INCmvAhbToMbush */ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvAhbToMbusRegs.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,143 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvAhbToMbusRegsh ++#define __INCmvAhbToMbusRegsh ++ ++/******************************/ ++/* ARM Address Map Registers */ ++/******************************/ ++ ++#define MAX_AHB_TO_MBUS_WINS 9 ++#define MV_AHB_TO_MBUS_INTREG_WIN 8 ++ ++ ++#define AHB_TO_MBUS_WIN_CTRL_REG(winNum) (0x20000 + (winNum)*0x10) ++#define AHB_TO_MBUS_WIN_BASE_REG(winNum) (0x20004 + (winNum)*0x10) ++#define AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum) (0x20008 + (winNum)*0x10) ++#define AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum) (0x2000C + (winNum)*0x10) ++#define AHB_TO_MBUS_WIN_INTEREG_REG 0x20080 ++ ++/* Window Control Register */ ++/* AHB_TO_MBUS_WIN_CTRL_REG (ATMWCR)*/ ++#define ATMWCR_WIN_ENABLE BIT0 /* Window Enable */ ++ ++#define ATMWCR_WIN_TARGET_OFFS 4 /* The target interface associated ++ with this window*/ ++#define ATMWCR_WIN_TARGET_MASK (0xf << ATMWCR_WIN_TARGET_OFFS) ++ ++#define ATMWCR_WIN_ATTR_OFFS 8 /* The target interface attributes ++ Associated with this window */ ++#define ATMWCR_WIN_ATTR_MASK (0xff << ATMWCR_WIN_ATTR_OFFS) ++ ++ ++/* ++Used with the Base register to set the address window size and location ++Must be programed from LSB to MSB as sequence of 1’s followed ++by sequence of 0’s. The number of 1’s specifies the size of the window ++in 64 KB granularity (e.g. a value of 0x00FF specifies 256 = 16 MB). ++ ++NOTE: A value of 0x0 specifies 64KB size. ++*/ ++#define ATMWCR_WIN_SIZE_OFFS 16 /* Window Size */ ++#define ATMWCR_WIN_SIZE_MASK (0xffff << ATMWCR_WIN_SIZE_OFFS) ++#define ATMWCR_WIN_SIZE_ALIGNMENT 0x10000 ++ ++/* Window Base Register */ ++/* AHB_TO_MBUS_WIN_BASE_REG (ATMWBR) */ ++ ++/* ++Used with the size field to set the address window size and location. ++Corresponds to transaction address[31:16] ++*/ ++#define ATMWBR_BASE_OFFS 16 /* Base Address */ ++#define ATMWBR_BASE_MASK (0xffff << ATMWBR_BASE_OFFS) ++#define ATMWBR_BASE_ALIGNMENT 0x10000 ++ ++/* Window Remap Low Register */ ++/* AHB_TO_MBUS_WIN_REMAP_LOW_REG (ATMWRLR) */ ++ ++/* ++Used with the size field to specifies address bits[31:0] to be driven to ++the target interface.: ++target_addr[31:16] = (addr[31:16] & size[15:0]) | (remap[31:16] & ~size[15:0]) ++*/ ++#define ATMWRLR_REMAP_LOW_OFFS 16 /* Remap Address */ ++#define ATMWRLR_REMAP_LOW_MASK (0xffff << ATMWRLR_REMAP_LOW_OFFS) ++#define ATMWRLR_REMAP_LOW_ALIGNMENT 0x10000 ++ ++/* Window Remap High Register */ ++/* AHB_TO_MBUS_WIN_REMAP_HIGH_REG (ATMWRHR) */ ++ ++/* ++Specifies address bits[63:32] to be driven to the target interface. ++target_addr[63:32] = (RemapHigh[31:0] ++*/ ++#define ATMWRHR_REMAP_HIGH_OFFS 0 /* Remap Address */ ++#define ATMWRHR_REMAP_HIGH_MASK (0xffffffff << ATMWRHR_REMAP_HIGH_OFFS) ++ ++ ++#endif /* __INCmvAhbToMbusRegsh */ ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,1036 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++/* includes */ ++#include "ctrlEnv/sys/mvCpuIf.h" ++#include "ctrlEnv/sys/mvAhbToMbusRegs.h" ++#include "cpu/mvCpu.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "mvSysHwConfig.h" ++#include "mvSysDram.h" ++ ++/*#define MV_DEBUG*/ ++/* defines */ ++ ++#ifdef MV_DEBUG ++ #define DB(x) x ++#else ++ #define DB(x) ++#endif ++ ++/* locals */ ++/* static functions */ ++static MV_BOOL cpuTargetWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin); ++ ++MV_TARGET * sampleAtResetTargetArray; ++MV_TARGET sampleAtResetTargetArrayP[] = BOOT_TARGETS_NAME_ARRAY; ++MV_TARGET sampleAtResetTargetArray6180P[] = BOOT_TARGETS_NAME_ARRAY_6180; ++/******************************************************************************* ++* mvCpuIfInit - Initialize Controller CPU interface ++* ++* DESCRIPTION: ++* This function initialize Controller CPU interface: ++* 1. Set CPU interface configuration registers. ++* 2. Set CPU master Pizza arbiter control according to static ++* configuration described in configuration file. ++* 3. Opens CPU address decode windows. DRAM windows are assumed to be ++* already set (auto detection). ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_STATUS mvCpuIfInit(MV_CPU_DEC_WIN *cpuAddrWinMap) ++{ ++ MV_U32 regVal; ++ MV_TARGET target; ++ MV_ADDR_WIN addrWin; ++ ++ if (cpuAddrWinMap == NULL) ++ { ++ DB(mvOsPrintf("mvCpuIfInit:ERR. cpuAddrWinMap == NULL\n")); ++ return MV_ERROR; ++ } ++ ++ /*Initialize the boot target array according to device type*/ ++ if(mvCtrlModelGet() == MV_6180_DEV_ID) ++ sampleAtResetTargetArray = sampleAtResetTargetArray6180P; ++ else ++ sampleAtResetTargetArray = sampleAtResetTargetArrayP; ++ ++ /* Set ARM Configuration register */ ++ regVal = MV_REG_READ(CPU_CONFIG_REG); ++ regVal &= ~CPU_CONFIG_DEFAULT_MASK; ++ regVal |= CPU_CONFIG_DEFAULT; ++ MV_REG_WRITE(CPU_CONFIG_REG,regVal); ++ ++ /* First disable all CPU target windows */ ++ for (target = 0; cpuAddrWinMap[target].enable != TBL_TERM; target++) ++ { ++ if ((MV_TARGET_IS_DRAM(target))||(target == INTER_REGS)) ++ { ++ continue; ++ } ++ ++#if defined(MV_MEM_OVER_PCI_WA) || defined(MV_UART_OVER_PCI_WA) ++ /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ ++ if (MV_TARGET_IS_PCI(target)) ++ { ++ continue; ++ } ++#endif ++ ++#if defined(MV_MEM_OVER_PEX_WA) || defined(MV_UART_OVER_PEX_WA) ++ /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ ++ if (MV_TARGET_IS_PEX(target)) ++ { ++ continue; ++ } ++#endif ++#if defined(MV_RUN_FROM_FLASH) ++ /* Don't disable the boot device. */ ++ if (target == DEV_BOOCS) ++ { ++ continue; ++ } ++#endif /* MV_RUN_FROM_FLASH */ ++ mvCpuIfTargetWinEnable(MV_CHANGE_BOOT_CS(target),MV_FALSE); ++ } ++ ++#if defined(MV_RUN_FROM_FLASH) ++ /* Resize the bootcs windows before other windows, because this */ ++ /* window is enabled and will cause an overlap if not resized. */ ++ target = DEV_BOOCS; ++ ++ if (MV_OK != mvCpuIfTargetWinSet(target, &cpuAddrWinMap[target])) ++ { ++ DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinSet fail\n")); ++ return MV_ERROR; ++ } ++ ++ addrWin.baseLow = cpuAddrWinMap[target].addrWin.baseLow; ++ addrWin.baseHigh = cpuAddrWinMap[target].addrWin.baseHigh; ++ if (0xffffffff == mvAhbToMbusWinRemap(cpuAddrWinMap[target].winNum ,&addrWin)) ++ { ++ DB(mvOsPrintf("mvCpuIfInit:WARN. mvAhbToMbusWinRemap can't remap winNum=%d\n", ++ cpuAddrWinMap[target].winNum)); ++ } ++ ++#endif /* MV_RUN_FROM_FLASH */ ++ ++ /* Go through all targets in user table until table terminator */ ++ for (target = 0; cpuAddrWinMap[target].enable != TBL_TERM; target++) ++ { ++ ++#if defined(MV_RUN_FROM_FLASH) ++ if (target == DEV_BOOCS) ++ { ++ continue; ++ } ++#endif /* MV_RUN_FROM_FLASH */ ++ ++ /* if DRAM auto sizing is used do not initialized DRAM target windows, */ ++ /* assuming this already has been done earlier. */ ++#ifdef MV_DRAM_AUTO_SIZE ++ if (MV_TARGET_IS_DRAM(target)) ++ { ++ continue; ++ } ++#endif ++ ++#if defined(MV_MEM_OVER_PCI_WA) || defined(MV_UART_OVER_PCI_WA) ++ /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ ++ if (MV_TARGET_IS_PCI(target)) ++ { ++ continue; ++ } ++#endif ++ ++#if defined(MV_MEM_OVER_PEX_WA) || defined(MV_UART_OVER_PEX_WA) ++ /* If the target PEX or PCI and memory is over PEX or PCI we don't touch this CPU windows */ ++ if (MV_TARGET_IS_PEX(target)) ++ { ++ continue; ++ } ++#endif ++ /* If the target attribute is the same as the boot device attribute */ ++ /* then it's stays disable */ ++ if (MV_TARGET_IS_AS_BOOT(target)) ++ { ++ continue; ++ } ++ ++ if((0 == cpuAddrWinMap[target].addrWin.size) || ++ (DIS == cpuAddrWinMap[target].enable)) ++ ++ { ++ if (MV_OK != mvCpuIfTargetWinEnable(target, MV_FALSE)) ++ { ++ DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinEnable fail\n")); ++ return MV_ERROR; ++ } ++ ++ } ++ else ++ { ++ if (MV_OK != mvCpuIfTargetWinSet(target, &cpuAddrWinMap[target])) ++ { ++ DB(mvOsPrintf("mvCpuIfInit:ERR. mvCpuIfTargetWinSet fail\n")); ++ return MV_ERROR; ++ } ++ ++ addrWin.baseLow = cpuAddrWinMap[target].addrWin.baseLow; ++ addrWin.baseHigh = cpuAddrWinMap[target].addrWin.baseHigh; ++ if (0xffffffff == mvAhbToMbusWinRemap(cpuAddrWinMap[target].winNum ,&addrWin)) ++ { ++ DB(mvOsPrintf("mvCpuIfInit:WARN. mvAhbToMbusWinRemap can't remap winNum=%d\n", ++ cpuAddrWinMap[target].winNum)); ++ } ++ ++ ++ } ++ } ++ ++ return MV_OK; ++ ++ ++} ++ ++ ++/******************************************************************************* ++* mvCpuIfTargetWinSet - Set CPU-to-peripheral target address window ++* ++* DESCRIPTION: ++* This function sets a peripheral target (e.g. SDRAM bank0, PCI0_MEM0) ++* address window, also known as address decode window. ++* A new address decode window is set for specified target address window. ++* If address decode window parameter structure enables the window, ++* the routine will also enable the target window, allowing CPU to access ++* the target window. ++* ++* INPUT: ++* target - Peripheral target enumerator. ++* pAddrDecWin - CPU target window data structure. ++* ++* OUTPUT: ++* N/A ++* ++* RETURN: ++* MV_OK if CPU target window was set correctly, MV_ERROR in case of ++* address window overlapps with other active CPU target window or ++* trying to assign 36bit base address while CPU does not support that. ++* The function returns MV_NOT_SUPPORTED, if the target is unsupported. ++* ++*******************************************************************************/ ++MV_STATUS mvCpuIfTargetWinSet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin) ++{ ++ MV_AHB_TO_MBUS_DEC_WIN decWin; ++ MV_U32 existingWinNum; ++ MV_DRAM_DEC_WIN addrDecWin; ++ ++ target = MV_CHANGE_BOOT_CS(target); ++ ++ /* Check parameters */ ++ if (target >= MAX_TARGETS) ++ { ++ mvOsPrintf("mvCpuIfTargetWinSet: target %d is Illigal\n", target); ++ return MV_ERROR; ++ } ++ ++ /* 2) Check if the requested window overlaps with current windows */ ++ if (MV_TRUE == cpuTargetWinOverlap(target, &pAddrDecWin->addrWin)) ++ { ++ mvOsPrintf("mvCpuIfTargetWinSet: ERR. Target %d overlap\n", target); ++ return MV_BAD_PARAM; ++ } ++ ++ if (MV_TARGET_IS_DRAM(target)) ++ { ++ /* copy relevant data to MV_DRAM_DEC_WIN structure */ ++ addrDecWin.addrWin.baseHigh = pAddrDecWin->addrWin.baseHigh; ++ addrDecWin.addrWin.baseLow = pAddrDecWin->addrWin.baseLow; ++ addrDecWin.addrWin.size = pAddrDecWin->addrWin.size; ++ addrDecWin.enable = pAddrDecWin->enable; ++ ++ ++ if (mvDramIfWinSet(target,&addrDecWin) != MV_OK); ++ { ++ mvOsPrintf("mvCpuIfTargetWinSet: mvDramIfWinSet Failed\n"); ++ return MV_ERROR; ++ } ++ ++ } ++ else ++ { ++ /* copy relevant data to MV_AHB_TO_MBUS_DEC_WIN structure */ ++ decWin.addrWin.baseLow = pAddrDecWin->addrWin.baseLow; ++ decWin.addrWin.baseHigh = pAddrDecWin->addrWin.baseHigh; ++ decWin.addrWin.size = pAddrDecWin->addrWin.size; ++ decWin.enable = pAddrDecWin->enable; ++ decWin.target = target; ++ ++ existingWinNum = mvAhbToMbusWinTargetGet(target); ++ ++ /* check if there is already another Window configured ++ for this target */ ++ if ((existingWinNum < MAX_AHB_TO_MBUS_WINS )&& ++ (existingWinNum != pAddrDecWin->winNum)) ++ { ++ /* if we want to enable the new winow number ++ passed by the user , then the old one should ++ be disabled */ ++ if (MV_TRUE == pAddrDecWin->enable) ++ { ++ /* be sure it is disabled */ ++ mvAhbToMbusWinEnable(existingWinNum , MV_FALSE); ++ } ++ } ++ ++ if (mvAhbToMbusWinSet(pAddrDecWin->winNum,&decWin) != MV_OK) ++ { ++ mvOsPrintf("mvCpuIfTargetWinSet: mvAhbToMbusWinSet Failed\n"); ++ return MV_ERROR; ++ } ++ ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCpuIfTargetWinGet - Get CPU-to-peripheral target address window ++* ++* DESCRIPTION: ++* Get the CPU peripheral target address window. ++* ++* INPUT: ++* target - Peripheral target enumerator ++* ++* OUTPUT: ++* pAddrDecWin - CPU target window information data structure. ++* ++* RETURN: ++* MV_OK if target exist, MV_ERROR otherwise. ++* ++*******************************************************************************/ ++MV_STATUS mvCpuIfTargetWinGet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin) ++{ ++ ++ MV_U32 winNum=0xffffffff; ++ MV_AHB_TO_MBUS_DEC_WIN decWin; ++ MV_DRAM_DEC_WIN addrDecWin; ++ ++ target = MV_CHANGE_BOOT_CS(target); ++ ++ /* Check parameters */ ++ if (target >= MAX_TARGETS) ++ { ++ mvOsPrintf("mvCpuIfTargetWinGet: target %d is Illigal\n", target); ++ return MV_ERROR; ++ } ++ ++ if (MV_TARGET_IS_DRAM(target)) ++ { ++ if (mvDramIfWinGet(target,&addrDecWin) != MV_OK) ++ { ++ mvOsPrintf("mvCpuIfTargetWinGet: Failed to get window target %d\n", ++ target); ++ return MV_ERROR; ++ } ++ ++ /* copy relevant data to MV_CPU_DEC_WIN structure */ ++ pAddrDecWin->addrWin.baseLow = addrDecWin.addrWin.baseLow; ++ pAddrDecWin->addrWin.baseHigh = addrDecWin.addrWin.baseHigh; ++ pAddrDecWin->addrWin.size = addrDecWin.addrWin.size; ++ pAddrDecWin->enable = addrDecWin.enable; ++ pAddrDecWin->winNum = 0xffffffff; ++ ++ } ++ else ++ { ++ /* get the Window number associated with this target */ ++ ++ winNum = mvAhbToMbusWinTargetGet(target); ++ if (winNum >= MAX_AHB_TO_MBUS_WINS) ++ { ++ return MV_NO_SUCH; ++ ++ } ++ ++ if (mvAhbToMbusWinGet(winNum , &decWin) != MV_OK) ++ { ++ mvOsPrintf("%s: mvAhbToMbusWinGet Failed at winNum = %d\n", ++ __FUNCTION__, winNum); ++ return MV_ERROR; ++ ++ } ++ ++ /* copy relevant data to MV_CPU_DEC_WIN structure */ ++ pAddrDecWin->addrWin.baseLow = decWin.addrWin.baseLow; ++ pAddrDecWin->addrWin.baseHigh = decWin.addrWin.baseHigh; ++ pAddrDecWin->addrWin.size = decWin.addrWin.size; ++ pAddrDecWin->enable = decWin.enable; ++ pAddrDecWin->winNum = winNum; ++ ++ } ++ ++ ++ ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvCpuIfTargetWinEnable - Enable/disable a CPU address decode window ++* ++* DESCRIPTION: ++* This function enable/disable a CPU address decode window. ++* if parameter 'enable' == MV_TRUE the routine will enable the ++* window, thus enabling CPU accesses (before enabling the window it is ++* tested for overlapping). Otherwise, the window will be disabled. ++* ++* INPUT: ++* target - Peripheral target enumerator. ++* enable - Enable/disable parameter. ++* ++* OUTPUT: ++* N/A ++* ++* RETURN: ++* MV_ERROR if protection window number was wrong, or the window ++* overlapps other target window. ++* ++*******************************************************************************/ ++MV_STATUS mvCpuIfTargetWinEnable(MV_TARGET target,MV_BOOL enable) ++{ ++ MV_U32 winNum, temp; ++ MV_CPU_DEC_WIN addrDecWin; ++ ++ target = MV_CHANGE_BOOT_CS(target); ++ ++ /* Check parameters */ ++ if (target >= MAX_TARGETS) ++ { ++ mvOsPrintf("mvCpuIfTargetWinEnable: target %d is Illigal\n", target); ++ return MV_ERROR; ++ } ++ ++ /* get the window and check if it exist */ ++ temp = mvCpuIfTargetWinGet(target, &addrDecWin); ++ if (MV_NO_SUCH == temp) ++ { ++ return (enable? MV_ERROR: MV_OK); ++ } ++ else if( MV_OK != temp) ++ { ++ mvOsPrintf("%s: ERR. Getting target %d failed.\n",__FUNCTION__, target); ++ return MV_ERROR; ++ } ++ ++ ++ /* check overlap */ ++ ++ if (MV_TRUE == enable) ++ { ++ if (MV_TRUE == cpuTargetWinOverlap(target, &addrDecWin.addrWin)) ++ { ++ DB(mvOsPrintf("%s: ERR. Target %d overlap\n",__FUNCTION__, target)); ++ return MV_ERROR; ++ } ++ ++ } ++ ++ ++ if (MV_TARGET_IS_DRAM(target)) ++ { ++ if (mvDramIfWinEnable(target , enable) != MV_OK) ++ { ++ mvOsPrintf("mvCpuIfTargetWinGet: mvDramIfWinEnable Failed at \n"); ++ return MV_ERROR; ++ ++ } ++ ++ } ++ else ++ { ++ /* get the Window number associated with this target */ ++ ++ winNum = mvAhbToMbusWinTargetGet(target); ++ ++ if (winNum >= MAX_AHB_TO_MBUS_WINS) ++ { ++ return (enable? MV_ERROR: MV_OK); ++ } ++ ++ if (mvAhbToMbusWinEnable(winNum , enable) != MV_OK) ++ { ++ mvOsPrintf("mvCpuIfTargetWinGet: Failed to enable window = %d\n", ++ winNum); ++ return MV_ERROR; ++ ++ } ++ ++ } ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvCpuIfTargetWinSizeGet - Get CPU target address window size ++* ++* DESCRIPTION: ++* Get the size of CPU-to-peripheral target window. ++* ++* INPUT: ++* target - Peripheral target enumerator ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit size. Function also returns '0' if window is closed. ++* Function returns 0xFFFFFFFF in case of an error. ++* ++*******************************************************************************/ ++MV_U32 mvCpuIfTargetWinSizeGet(MV_TARGET target) ++{ ++ MV_CPU_DEC_WIN addrDecWin; ++ ++ target = MV_CHANGE_BOOT_CS(target); ++ ++ /* Check parameters */ ++ if (target >= MAX_TARGETS) ++ { ++ mvOsPrintf("mvCpuIfTargetWinSizeGet: target %d is Illigal\n", target); ++ return 0; ++ } ++ ++ /* Get the winNum window */ ++ if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) ++ { ++ mvOsPrintf("mvCpuIfTargetWinSizeGet:ERR. Getting target %d failed.\n", ++ target); ++ return 0; ++ } ++ ++ /* Check if window is enabled */ ++ if (addrDecWin.enable == MV_TRUE) ++ { ++ return (addrDecWin.addrWin.size); ++ } ++ else ++ { ++ return 0; /* Window disabled. return 0 */ ++ } ++} ++ ++/******************************************************************************* ++* mvCpuIfTargetWinBaseLowGet - Get CPU target address window base low ++* ++* DESCRIPTION: ++* CPU-to-peripheral target address window base is constructed of ++* two parts: Low and high. ++* This function gets the CPU peripheral target low base address. ++* ++* INPUT: ++* target - Peripheral target enumerator ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit low base address. ++* ++*******************************************************************************/ ++MV_U32 mvCpuIfTargetWinBaseLowGet(MV_TARGET target) ++{ ++ MV_CPU_DEC_WIN addrDecWin; ++ ++ target = MV_CHANGE_BOOT_CS(target); ++ ++ /* Check parameters */ ++ if (target >= MAX_TARGETS) ++ { ++ mvOsPrintf("mvCpuIfTargetWinBaseLowGet: target %d is Illigal\n", target); ++ return 0xffffffff; ++ } ++ ++ /* Get the target window */ ++ if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) ++ { ++ mvOsPrintf("mvCpuIfTargetWinBaseLowGet:ERR. Getting target %d failed.\n", ++ target); ++ return 0xffffffff; ++ } ++ ++ if (MV_FALSE == addrDecWin.enable) ++ { ++ return 0xffffffff; ++ } ++ return (addrDecWin.addrWin.baseLow); ++} ++ ++/******************************************************************************* ++* mvCpuIfTargetWinBaseHighGet - Get CPU target address window base high ++* ++* DESCRIPTION: ++* CPU-to-peripheral target address window base is constructed of ++* two parts: Low and high. ++* This function gets the CPU peripheral target high base address. ++* ++* INPUT: ++* target - Peripheral target enumerator ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit high base address. ++* ++*******************************************************************************/ ++MV_U32 mvCpuIfTargetWinBaseHighGet(MV_TARGET target) ++{ ++ MV_CPU_DEC_WIN addrDecWin; ++ ++ target = MV_CHANGE_BOOT_CS(target); ++ ++ /* Check parameters */ ++ if (target >= MAX_TARGETS) ++ { ++ mvOsPrintf("mvCpuIfTargetWinBaseLowGet: target %d is Illigal\n", target); ++ return 0xffffffff; ++ } ++ ++ /* Get the target window */ ++ if (MV_OK != mvCpuIfTargetWinGet(target, &addrDecWin)) ++ { ++ mvOsPrintf("mvCpuIfTargetWinBaseHighGet:ERR. Getting target %d failed.\n", ++ target); ++ return 0xffffffff; ++ } ++ ++ if (MV_FALSE == addrDecWin.enable) ++ { ++ return 0; ++ } ++ ++ return (addrDecWin.addrWin.baseHigh); ++} ++ ++#if defined(MV_INCLUDE_PEX) ++/******************************************************************************* ++* mvCpuIfPexRemap - Set CPU remap register for address windows. ++* ++* DESCRIPTION: ++* ++* INPUT: ++* pexTarget - Peripheral target enumerator. Must be a PEX target. ++* pAddrDecWin - CPU target window information data structure. ++* Note that caller has to fill in the base field only. The ++* size field is ignored. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_ERROR if target is not a PEX one, MV_OK otherwise. ++* ++*******************************************************************************/ ++MV_U32 mvCpuIfPexRemap(MV_TARGET pexTarget, MV_ADDR_WIN *pAddrDecWin) ++{ ++ MV_U32 winNum; ++ ++ /* Check parameters */ ++ ++ if (mvCtrlPexMaxIfGet() > 1) ++ { ++ if ((!MV_TARGET_IS_PEX1(pexTarget))&&(!MV_TARGET_IS_PEX0(pexTarget))) ++ { ++ mvOsPrintf("mvCpuIfPexRemap: target %d is Illigal\n",pexTarget); ++ return 0xffffffff; ++ } ++ ++ } ++ else ++ { ++ if (!MV_TARGET_IS_PEX0(pexTarget)) ++ { ++ mvOsPrintf("mvCpuIfPexRemap: target %d is Illigal\n",pexTarget); ++ return 0xffffffff; ++ } ++ ++ } ++ ++ /* get the Window number associated with this target */ ++ winNum = mvAhbToMbusWinTargetGet(pexTarget); ++ ++ if (winNum >= MAX_AHB_TO_MBUS_WINS) ++ { ++ mvOsPrintf("mvCpuIfPexRemap: mvAhbToMbusWinTargetGet Failed\n"); ++ return 0xffffffff; ++ ++ } ++ ++ return mvAhbToMbusWinRemap(winNum , pAddrDecWin); ++} ++ ++#endif ++ ++#if defined(MV_INCLUDE_PCI) ++/******************************************************************************* ++* mvCpuIfPciRemap - Set CPU remap register for address windows. ++* ++* DESCRIPTION: ++* ++* INPUT: ++* pciTarget - Peripheral target enumerator. Must be a PCI target. ++* pAddrDecWin - CPU target window information data structure. ++* Note that caller has to fill in the base field only. The ++* size field is ignored. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_ERROR if target is not a PCI one, MV_OK otherwise. ++* ++*******************************************************************************/ ++MV_U32 mvCpuIfPciRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin) ++{ ++ MV_U32 winNum; ++ ++ /* Check parameters */ ++ if (!MV_TARGET_IS_PCI(pciTarget)) ++ { ++ mvOsPrintf("mvCpuIfPciRemap: target %d is Illigal\n",pciTarget); ++ return 0xffffffff; ++ } ++ ++ /* get the Window number associated with this target */ ++ winNum = mvAhbToMbusWinTargetGet(pciTarget); ++ ++ if (winNum >= MAX_AHB_TO_MBUS_WINS) ++ { ++ mvOsPrintf("mvCpuIfPciRemap: mvAhbToMbusWinTargetGet Failed\n"); ++ return 0xffffffff; ++ ++ } ++ ++ return mvAhbToMbusWinRemap(winNum , pAddrDecWin); ++} ++#endif /* MV_INCLUDE_PCI */ ++ ++ ++/******************************************************************************* ++* mvCpuIfPciIfRemap - Set CPU remap register for address windows. ++* ++* DESCRIPTION: ++* ++* INPUT: ++* pciTarget - Peripheral target enumerator. Must be a PCI target. ++* pAddrDecWin - CPU target window information data structure. ++* Note that caller has to fill in the base field only. The ++* size field is ignored. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_ERROR if target is not a PCI one, MV_OK otherwise. ++* ++*******************************************************************************/ ++MV_U32 mvCpuIfPciIfRemap(MV_TARGET pciIfTarget, MV_ADDR_WIN *pAddrDecWin) ++{ ++#if defined(MV_INCLUDE_PEX) ++ if (MV_TARGET_IS_PEX(pciIfTarget)) ++ { ++ return mvCpuIfPexRemap(pciIfTarget,pAddrDecWin); ++ } ++#endif ++#if defined(MV_INCLUDE_PCI) ++ ++ if (MV_TARGET_IS_PCI(pciIfTarget)) ++ { ++ return mvCpuIfPciRemap(pciIfTarget,pAddrDecWin); ++ } ++#endif ++ return 0; ++} ++ ++ ++ ++/******************************************************************************* ++* mvCpuIfTargetOfBaseAddressGet - Get the target according to base address ++* ++* DESCRIPTION: ++* ++* INPUT: ++* baseAddress - base address to be checked ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* the target number that baseAddress belongs to or MAX_TARGETS is not ++* found ++* ++*******************************************************************************/ ++ ++MV_TARGET mvCpuIfTargetOfBaseAddressGet(MV_U32 baseAddress) ++{ ++ MV_CPU_DEC_WIN win; ++ MV_U32 target; ++ ++ for( target = 0; target < MAX_TARGETS; target++ ) ++ { ++ if( mvCpuIfTargetWinGet( target, &win ) == MV_OK ) ++ { ++ if( win.enable ) ++ { ++ if ((baseAddress >= win.addrWin.baseLow) && ++ (baseAddress < win.addrWin.baseLow + win.addrWin.size)) break; ++ } ++ } ++ else return MAX_TARGETS; ++ ++ } ++ ++ return target; ++} ++/******************************************************************************* ++* cpuTargetWinOverlap - Detect CPU address decode windows overlapping ++* ++* DESCRIPTION: ++* An unpredicted behaviur is expected in case CPU address decode ++* windows overlapps. ++* This function detects CPU address decode windows overlapping of a ++* specified target. The function does not check the target itself for ++* overlapping. The function also skipps disabled address decode windows. ++* ++* INPUT: ++* target - Peripheral target enumerator. ++* pAddrDecWin - An address decode window struct. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the given address window overlaps current address ++* decode map, MV_FALSE otherwise. ++* ++*******************************************************************************/ ++static MV_BOOL cpuTargetWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin) ++{ ++ MV_U32 targetNum; ++ MV_CPU_DEC_WIN addrDecWin; ++ MV_STATUS status; ++ ++ ++ for(targetNum = 0; targetNum < MAX_TARGETS; targetNum++) ++ { ++#if defined(MV_RUN_FROM_FLASH) ++ if(MV_TARGET_IS_AS_BOOT(target)) ++ { ++ if (MV_CHANGE_BOOT_CS(targetNum) == target) ++ continue; ++ } ++#endif /* MV_RUN_FROM_FLASH */ ++ ++ /* don't check our target or illegal targets */ ++ if (targetNum == target) ++ { ++ continue; ++ } ++ ++ /* Get window parameters */ ++ status = mvCpuIfTargetWinGet(targetNum, &addrDecWin); ++ if(MV_NO_SUCH == status) ++ { ++ continue; ++ } ++ if(MV_OK != status) ++ { ++ DB(mvOsPrintf("cpuTargetWinOverlap: ERR. TargetWinGet failed\n")); ++ return MV_TRUE; ++ } ++ ++ /* Do not check disabled windows */ ++ if (MV_FALSE == addrDecWin.enable) ++ { ++ continue; ++ } ++ ++ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) ++ { ++ DB(mvOsPrintf( ++ "cpuTargetWinOverlap: Required target %d overlap current %d\n", ++ target, targetNum)); ++ return MV_TRUE; ++ } ++ } ++ ++ return MV_FALSE; ++ ++} ++ ++/******************************************************************************* ++* mvCpuIfAddDecShow - Print the CPU address decode map. ++* ++* DESCRIPTION: ++* This function print the CPU address decode map. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvCpuIfAddDecShow(MV_VOID) ++{ ++ MV_CPU_DEC_WIN win; ++ MV_U32 target; ++ mvOsOutput( "\n" ); ++ mvOsOutput( "CPU Interface\n" ); ++ mvOsOutput( "-------------\n" ); ++ ++ for( target = 0; target < MAX_TARGETS; target++ ) ++ { ++ ++ memset( &win, 0, sizeof(MV_CPU_DEC_WIN) ); ++ ++ mvOsOutput( "%s ",mvCtrlTargetNameGet(target)); ++ mvOsOutput( "...." ); ++ ++ if( mvCpuIfTargetWinGet( target, &win ) == MV_OK ) ++ { ++ if( win.enable ) ++ { ++ mvOsOutput( "base %08x, ", win.addrWin.baseLow ); ++ mvSizePrint( win.addrWin.size ); ++ mvOsOutput( "\n" ); ++ ++ } ++ else ++ mvOsOutput( "disable\n" ); ++ } ++ else if( mvCpuIfTargetWinGet( target, &win ) == MV_NO_SUCH ) ++ { ++ mvOsOutput( "no such\n" ); ++ } ++ } ++} ++ ++/******************************************************************************* ++* mvCpuIfEnablePex - Enable PCI Express. ++* ++* DESCRIPTION: ++* This function Enable PCI Express. ++* ++* INPUT: ++* pexIf - PEX interface number. ++* pexType - MV_PEX_ROOT_COMPLEX - root complex device ++* MV_PEX_END_POINT - end point device ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++#if defined(MV_INCLUDE_PEX) ++MV_VOID mvCpuIfEnablePex(MV_U32 pexIf, MV_PEX_TYPE pexType) ++{ ++ /* Set pex mode incase S@R not exist */ ++ if( pexType == MV_PEX_END_POINT) ++ { ++ MV_REG_BIT_RESET(PEX_CTRL_REG(pexIf),PXCR_DEV_TYPE_CTRL_MASK); ++ /* Change pex mode in capability reg */ ++ MV_REG_BIT_RESET(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_CAPABILITY_REG), BIT22); ++ MV_REG_BIT_SET(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_CAPABILITY_REG), BIT20); ++ ++ } ++ else ++ { ++ MV_REG_BIT_SET(PEX_CTRL_REG(pexIf),PXCR_DEV_TYPE_CTRL_MASK); ++ } ++ ++ /* CPU config register Pex enable */ ++ MV_REG_BIT_SET(CPU_CTRL_STAT_REG,CCSR_PCI_ACCESS_MASK); ++} ++#endif ++ ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIf.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,120 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvCpuIfh ++#define __INCmvCpuIfh ++ ++/* includes */ ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "ctrlEnv/sys/mvCpuIfRegs.h" ++#include "ctrlEnv/sys/mvAhbToMbus.h" ++#include "ddr2/mvDramIf.h" ++#include "ctrlEnv/sys/mvSysDram.h" ++#if defined(MV_INCLUDE_PEX) ++#include "pex/mvPex.h" ++#endif ++ ++/* defines */ ++ ++/* typedefs */ ++/* This structure describes CPU interface address decode window */ ++typedef struct _mvCpuIfDecWin ++{ ++ MV_ADDR_WIN addrWin; /* An address window*/ ++ MV_U32 winNum; /* Window Number in the AHB To Mbus bridge */ ++ MV_BOOL enable; /* Address decode window is enabled/disabled */ ++ ++}MV_CPU_DEC_WIN; ++ ++ ++ ++/* mvCpuIfLib.h API list */ ++ ++/* mvCpuIfLib.h API list */ ++ ++MV_STATUS mvCpuIfInit(MV_CPU_DEC_WIN *cpuAddrWinMap); ++MV_STATUS mvCpuIfTargetWinSet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin); ++MV_STATUS mvCpuIfTargetWinGet(MV_TARGET target, MV_CPU_DEC_WIN *pAddrDecWin); ++MV_STATUS mvCpuIfTargetWinEnable(MV_TARGET target,MV_BOOL enable); ++MV_U32 mvCpuIfTargetWinSizeGet(MV_TARGET target); ++MV_U32 mvCpuIfTargetWinBaseLowGet(MV_TARGET target); ++MV_U32 mvCpuIfTargetWinBaseHighGet(MV_TARGET target); ++MV_TARGET mvCpuIfTargetOfBaseAddressGet(MV_U32 baseAddress); ++#if defined(MV_INCLUDE_PEX) ++MV_U32 mvCpuIfPexRemap(MV_TARGET pexTarget, MV_ADDR_WIN *pAddrDecWin); ++MV_VOID mvCpuIfEnablePex(MV_U32 pexIf, MV_PEX_TYPE pexType); ++#endif ++#if defined(MV_INCLUDE_PCI) ++MV_U32 mvCpuIfPciRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin); ++#endif ++MV_U32 mvCpuIfPciIfRemap(MV_TARGET pciTarget, MV_ADDR_WIN *pAddrDecWin); ++ ++MV_VOID mvCpuIfAddDecShow(MV_VOID); ++ ++#if defined(MV88F6281) ++MV_STATUS mvCpuIfBridgeReorderWAInit(void); ++#endif ++ ++#endif /* __INCmvCpuIfh */ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfInit.S linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfInit.S +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfInit.S 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfInit.S 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,163 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#define MV_ASMLANGUAGE ++#include "mvOsAsm.h" ++#include "mvDeviceId.h" ++#include "mvCtrlEnvRegs.h" ++#include "mvCpuIfRegs.h" ++#include "mvCtrlEnvAsm.h" ++ ++ ++/******************************************************************************* ++* mvCpuIfPreInit - Make early initialization of CPU interface. ++* ++* DESCRIPTION: ++* The function will initialize the CPU interface parameters that must ++* be initialize before any BUS activity towards the DDR interface, ++* which means it must be executed from ROM. Because of that, the function ++* is implemented in assembly code. ++* The function configure the following CPU config register parameters: ++* 1) CPU2MbusLTickDrv ++* 2) CPU2MbusLTickSample. ++* NOTE: This function must be called AFTER the internal register ++* base is modified to INTER_REGS_BASE. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++* r11 holds return function address. ++*******************************************************************************/ ++#define MV88F6281_PCKG_OPT 2 ++#define MV88F6192_PCKG_OPT 1 ++#define MV88F6180_PCKG_OPT 0 ++ ++ .globl _mvCpuIfPreInit ++_mvCpuIfPreInit: ++ ++ mov r11, LR /* Save link register */ ++ ++ /* Read device ID */ ++ MV_CTRL_MODEL_GET_ASM(r4, r5); ++ ++ /* goto calcConfigReg if device is 6281 */ ++ ldr r5, =MV88F6281_PCKG_OPT ++ cmp r4, r5 ++ beq calcConfigReg ++ ++ /* goto calcConfigReg if device is 6192/6190 */ ++ ldr r5, =MV88F6192_PCKG_OPT ++ cmp r4, r5 ++ beq calcConfigReg ++ ++ /* Else 6180 */ ++ /* Get the "sample on reset" register */ ++ MV_REG_READ_ASM (r4, r5, MPP_SAMPLE_AT_RESET) ++ ldr r5, =MSAR_CPUCLCK_MASK_6180 ++ and r5, r4, r5 ++ mov r5, r5, lsr #MSAR_CPUCLCK_OFFS_6180 ++ ++ ldr r4, =CPU_2_MBUSL_DDR_CLK_1x3 ++ cmp r5, #CPU_2_DDR_CLK_1x3_1 ++ beq setConfigReg ++ ++ ldr r4, =CPU_2_MBUSL_DDR_CLK_1x4 ++ cmp r5, #CPU_2_DDR_CLK_1x4_1 ++ beq setConfigReg ++ b setConfigReg ++ ++calcConfigReg: ++ /* Get the "sample on reset" register */ ++ MV_REG_READ_ASM (r4, r5, MPP_SAMPLE_AT_RESET) ++ ldr r5, =MSAR_DDRCLCK_RTIO_MASK ++ and r5, r4, r5 ++ mov r5, r5, lsr #MSAR_DDRCLCK_RTIO_OFFS ++ ++ ldr r4, =CPU_2_MBUSL_DDR_CLK_1x3 ++ cmp r5, #CPU_2_DDR_CLK_1x3 ++ beq setConfigReg ++ ++ ldr r4, =CPU_2_MBUSL_DDR_CLK_1x4 ++ cmp r5, #CPU_2_DDR_CLK_1x4 ++ beq setConfigReg ++ ++ /* Else */ ++ ldr r4, =0 ++ ++setConfigReg: ++ /* Read CPU Config register */ ++ MV_REG_READ_ASM (r7, r5, CPU_CONFIG_REG) ++ ldr r5, =~(CCR_CPU_2_MBUSL_TICK_DRV_MASK | CCR_CPU_2_MBUSL_TICK_SMPL_MASK) ++ and r7, r7, r5 /* Clear register fields */ ++ orr r7, r7, r4 /* Set the values according to the findings */ ++ MV_REG_WRITE_ASM (r7, r5, CPU_CONFIG_REG) ++ ++done: ++ mov PC, r11 /* r11 is saved link register */ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvCpuIfRegs.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,304 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvCpuIfRegsh ++#define __INCmvCpuIfRegsh ++ ++/****************************************/ ++/* ARM Control and Status Registers Map */ ++/****************************************/ ++ ++#define CPU_CONFIG_REG 0x20100 ++#define CPU_CTRL_STAT_REG 0x20104 ++#define CPU_RSTOUTN_MASK_REG 0x20108 ++#define CPU_SYS_SOFT_RST_REG 0x2010C ++#define CPU_AHB_MBUS_CAUSE_INT_REG 0x20110 ++#define CPU_AHB_MBUS_MASK_INT_REG 0x20114 ++#define CPU_FTDLL_CONFIG_REG 0x20120 ++#define CPU_L2_CONFIG_REG 0x20128 ++ ++ ++ ++/* ARM Configuration register */ ++/* CPU_CONFIG_REG (CCR) */ ++ ++ ++/* Reset vector location */ ++#define CCR_VEC_INIT_LOC_OFFS 1 ++#define CCR_VEC_INIT_LOC_MASK BIT1 ++/* reset at 0x00000000 */ ++#define CCR_VEC_INIT_LOC_0000 (0 << CCR_VEC_INIT_LOC_OFFS) ++/* reset at 0xFFFF0000 */ ++#define CCR_VEC_INIT_LOC_FF00 (1 << CCR_VEC_INIT_LOC_OFFS) ++ ++ ++#define CCR_AHB_ERROR_PROP_OFFS 2 ++#define CCR_AHB_ERROR_PROP_MASK BIT2 ++/* Erros are not propogated to AHB */ ++#define CCR_AHB_ERROR_PROP_NO_INDICATE (0 << CCR_AHB_ERROR_PROP_OFFS) ++/* Erros are propogated to AHB */ ++#define CCR_AHB_ERROR_PROP_INDICATE (1 << CCR_AHB_ERROR_PROP_OFFS) ++ ++ ++#define CCR_ENDIAN_INIT_OFFS 3 ++#define CCR_ENDIAN_INIT_MASK BIT3 ++#define CCR_ENDIAN_INIT_LITTLE (0 << CCR_ENDIAN_INIT_OFFS) ++#define CCR_ENDIAN_INIT_BIG (1 << CCR_ENDIAN_INIT_OFFS) ++ ++ ++#define CCR_INCR_EN_OFFS 4 ++#define CCR_INCR_EN_MASK BIT4 ++#define CCR_INCR_EN BIT4 ++ ++ ++#define CCR_NCB_BLOCKING_OFFS 5 ++#define CCR_NCB_BLOCKING_MASK (1 << CCR_NCB_BLOCKING_OFFS) ++#define CCR_NCB_BLOCKING_NON (0 << CCR_NCB_BLOCKING_OFFS) ++#define CCR_NCB_BLOCKING_EN (1 << CCR_NCB_BLOCKING_OFFS) ++ ++#define CCR_CPU_2_MBUSL_TICK_DRV_OFFS 8 ++#define CCR_CPU_2_MBUSL_TICK_DRV_MASK (0xF << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) ++#define CCR_CPU_2_MBUSL_TICK_SMPL_OFFS 12 ++#define CCR_CPU_2_MBUSL_TICK_SMPL_MASK (0xF << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS) ++#define CCR_ICACH_PREF_BUF_ENABLE BIT16 ++#define CCR_DCACH_PREF_BUF_ENABLE BIT17 ++ ++/* Ratio options for CPU to DDR for 6281/6192/6190 */ ++#define CPU_2_DDR_CLK_1x3 4 ++#define CPU_2_DDR_CLK_1x4 6 ++ ++/* Ratio options for CPU to DDR for 6281 only */ ++#define CPU_2_DDR_CLK_2x9 7 ++#define CPU_2_DDR_CLK_1x5 8 ++#define CPU_2_DDR_CLK_1x6 9 ++ ++/* Ratio options for CPU to DDR for 6180 only */ ++#define CPU_2_DDR_CLK_1x3_1 0x5 ++#define CPU_2_DDR_CLK_1x4_1 0x6 ++ ++/* Default values for CPU to Mbus-L DDR Interface Tick Driver and */ ++/* CPU to Mbus-L Tick Sample fields in CPU config register */ ++ ++#define TICK_DRV_1x1 0 ++#define TICK_DRV_1x2 0 ++#define TICK_DRV_1x3 1 ++#define TICK_DRV_1x4 2 ++#define TICK_SMPL_1x1 0 ++#define TICK_SMPL_1x2 1 ++#define TICK_SMPL_1x3 0 ++#define TICK_SMPL_1x4 0 ++ ++#define CPU_2_MBUSL_DDR_CLK_1x2 \ ++ ((TICK_DRV_1x2 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \ ++ (TICK_SMPL_1x2 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS)) ++#define CPU_2_MBUSL_DDR_CLK_1x3 \ ++ ((TICK_DRV_1x3 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \ ++ (TICK_SMPL_1x3 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS)) ++#define CPU_2_MBUSL_DDR_CLK_1x4 \ ++ ((TICK_DRV_1x4 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \ ++ (TICK_SMPL_1x4 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS)) ++ ++/* ARM Control and Status register */ ++/* CPU_CTRL_STAT_REG (CCSR) */ ++ ++ ++/* ++This is used to block PCI express\PCI from access Socrates/Feroceon GP ++while ARM boot is still in progress ++*/ ++ ++#define CCSR_PCI_ACCESS_OFFS 0 ++#define CCSR_PCI_ACCESS_MASK BIT0 ++#define CCSR_PCI_ACCESS_ENABLE (0 << CCSR_PCI_ACCESS_OFFS) ++#define CCSR_PCI_ACCESS_DISBALE (1 << CCSR_PCI_ACCESS_OFFS) ++ ++#define CCSR_ARM_RESET BIT1 ++#define CCSR_SELF_INT BIT2 ++#define CCSR_BIG_ENDIAN BIT15 ++ ++ ++/* RSTOUTn Mask Register */ ++/* CPU_RSTOUTN_MASK_REG (CRMR) */ ++ ++#define CRMR_PEX_RST_OUT_OFFS 0 ++#define CRMR_PEX_RST_OUT_MASK BIT0 ++#define CRMR_PEX_RST_OUT_ENABLE (1 << CRMR_PEX_RST_OUT_OFFS) ++#define CRMR_PEX_RST_OUT_DISABLE (0 << CRMR_PEX_RST_OUT_OFFS) ++ ++#define CRMR_WD_RST_OUT_OFFS 1 ++#define CRMR_WD_RST_OUT_MASK BIT1 ++#define CRMR_WD_RST_OUT_ENABLE (1 << CRMR_WD_RST_OUT_OFFS) ++#define CRMR_WD_RST_OUT_DISBALE (0 << CRMR_WD_RST_OUT_OFFS) ++ ++#define CRMR_SOFT_RST_OUT_OFFS 2 ++#define CRMR_SOFT_RST_OUT_MASK BIT2 ++#define CRMR_SOFT_RST_OUT_ENABLE (1 << CRMR_SOFT_RST_OUT_OFFS) ++#define CRMR_SOFT_RST_OUT_DISBALE (0 << CRMR_SOFT_RST_OUT_OFFS) ++ ++/* System Software Reset Register */ ++/* CPU_SYS_SOFT_RST_REG (CSSRR) */ ++ ++#define CSSRR_SYSTEM_SOFT_RST BIT0 ++ ++/* AHB to Mbus Bridge Interrupt Cause Register*/ ++/* CPU_AHB_MBUS_CAUSE_INT_REG (CAMCIR) */ ++ ++#define CAMCIR_ARM_SELF_INT BIT0 ++#define CAMCIR_ARM_TIMER0_INT_REQ BIT1 ++#define CAMCIR_ARM_TIMER1_INT_REQ BIT2 ++#define CAMCIR_ARM_WD_TIMER_INT_REQ BIT3 ++ ++ ++/* AHB to Mbus Bridge Interrupt Mask Register*/ ++/* CPU_AHB_MBUS_MASK_INT_REG (CAMMIR) */ ++ ++#define CAMCIR_ARM_SELF_INT_OFFS 0 ++#define CAMCIR_ARM_SELF_INT_MASK BIT0 ++#define CAMCIR_ARM_SELF_INT_EN (1 << CAMCIR_ARM_SELF_INT_OFFS) ++#define CAMCIR_ARM_SELF_INT_DIS (0 << CAMCIR_ARM_SELF_INT_OFFS) ++ ++ ++#define CAMCIR_ARM_TIMER0_INT_REQ_OFFS 1 ++#define CAMCIR_ARM_TIMER0_INT_REQ_MASK BIT1 ++#define CAMCIR_ARM_TIMER0_INT_REQ_EN (1 << CAMCIR_ARM_TIMER0_INT_REQ_OFFS) ++#define CAMCIR_ARM_TIMER0_INT_REQ_DIS (0 << CAMCIR_ARM_TIMER0_INT_REQ_OFFS) ++ ++#define CAMCIR_ARM_TIMER1_INT_REQ_OFFS 2 ++#define CAMCIR_ARM_TIMER1_INT_REQ_MASK BIT2 ++#define CAMCIR_ARM_TIMER1_INT_REQ_EN (1 << CAMCIR_ARM_TIMER1_INT_REQ_OFFS) ++#define CAMCIR_ARM_TIMER1_INT_REQ_DIS (0 << CAMCIR_ARM_TIMER1_INT_REQ_OFFS) ++ ++#define CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS 3 ++#define CAMCIR_ARM_WD_TIMER_INT_REQ_MASK BIT3 ++#define CAMCIR_ARM_WD_TIMER_INT_REQ_EN (1 << CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS) ++#define CAMCIR_ARM_WD_TIMER_INT_REQ_DIS (0 << CAMCIR_ARM_WD_TIMER_INT_REQ_OFFS) ++ ++/* CPU FTDLL Config register (CFCR) fields */ ++#define CFCR_FTDLL_ICACHE_TAG_OFFS 0 ++#define CFCR_FTDLL_ICACHE_TAG_MASK (0x7F << CFCR_FTDLL_ICACHE_TAG_OFFS) ++#define CFCR_FTDLL_DCACHE_TAG_OFFS 8 ++#define CFCR_FTDLL_DCACHE_TAG_MASK (0x7F << CFCR_FTDLL_DCACHE_TAG_OFFS) ++#define CFCR_FTDLL_OVERWRITE_ENABLE (1 << 15) ++/* For Orion 2 D2 only */ ++#define CFCR_MRVL_CPU_ID_OFFS 16 ++#define CFCR_MRVL_CPU_ID_MASK (0x1 << CFCR_MRVL_CPU_ID_OFFS) ++#define CFCR_ARM_CPU_ID (0x0 << CFCR_MRVL_CPU_ID_OFFS) ++#define CFCR_MRVL_CPU_ID (0x1 << CFCR_MRVL_CPU_ID_OFFS) ++#define CFCR_VFP_SUB_ARC_NUM_OFFS 7 ++#define CFCR_VFP_SUB_ARC_NUM_MASK (0x1 << CFCR_VFP_SUB_ARC_NUM_OFFS) ++#define CFCR_VFP_SUB_ARC_NUM_1 (0x0 << CFCR_VFP_SUB_ARC_NUM_OFFS) ++#define CFCR_VFP_SUB_ARC_NUM_2 (0x1 << CFCR_VFP_SUB_ARC_NUM_OFFS) ++ ++/* CPU_L2_CONFIG_REG fields */ ++#ifdef MV_CPU_LE ++#define CL2CR_L2_ECC_EN_OFFS 2 ++#define CL2CR_L2_WT_MODE_OFFS 4 ++#else ++#define CL2CR_L2_ECC_EN_OFFS 26 ++#define CL2CR_L2_WT_MODE_OFFS 28 ++#endif ++ ++#define CL2CR_L2_ECC_EN_MASK (1 << CL2CR_L2_ECC_EN_OFFS) ++#define CL2CR_L2_WT_MODE_MASK (1 << CL2CR_L2_WT_MODE_OFFS) ++ ++/*******************************************/ ++/* Main Interrupt Controller Registers Map */ ++/*******************************************/ ++ ++#define CPU_MAIN_INT_CAUSE_REG 0x20200 ++#define CPU_MAIN_IRQ_MASK_REG 0x20204 ++#define CPU_MAIN_FIQ_MASK_REG 0x20208 ++#define CPU_ENPOINT_MASK_REG 0x2020C ++#define CPU_MAIN_INT_CAUSE_HIGH_REG 0x20210 ++#define CPU_MAIN_IRQ_MASK_HIGH_REG 0x20214 ++#define CPU_MAIN_FIQ_MASK_HIGH_REG 0x20218 ++#define CPU_ENPOINT_MASK_HIGH_REG 0x2021C ++ ++ ++/*******************************************/ ++/* ARM Doorbell Registers Map */ ++/*******************************************/ ++ ++#define CPU_HOST_TO_ARM_DRBL_REG 0x20400 ++#define CPU_HOST_TO_ARM_MASK_REG 0x20404 ++#define CPU_ARM_TO_HOST_DRBL_REG 0x20408 ++#define CPU_ARM_TO_HOST_MASK_REG 0x2040C ++ ++ ++ ++/* CPU control register map */ ++/* Set bits means value is about to change according to new value */ ++#define CPU_CONFIG_DEFAULT_MASK (CCR_VEC_INIT_LOC_MASK | CCR_AHB_ERROR_PROP_MASK) ++ ++#define CPU_CONFIG_DEFAULT (CCR_VEC_INIT_LOC_FF00) ++ ++/* CPU Control and status defaults */ ++#define CPU_CTRL_STAT_DEFAULT_MASK (CCSR_PCI_ACCESS_MASK) ++ ++ ++#define CPU_CTRL_STAT_DEFAULT (CCSR_PCI_ACCESS_ENABLE) ++ ++#endif /* __INCmvCpuIfRegsh */ ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,324 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++#include "mvSysAudio.h" ++ ++/******************************************************************************* ++* mvAudioWinSet - Set AUDIO target address window ++* ++* DESCRIPTION: ++* This function sets a peripheral target (e.g. SDRAM bank0, PCI_MEM0) ++* address window, also known as address decode window. ++* After setting this target window, the AUDIO will be able to access the ++* target within the address window. ++* ++* INPUT: ++* winNum - AUDIO target address decode window number. ++* pAddrDecWin - AUDIO target window data structure. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_ERROR if address window overlapps with other address decode windows. ++* MV_BAD_PARAM if base address is invalid parameter or target is ++* unknown. ++* ++*******************************************************************************/ ++MV_STATUS mvAudioWinSet(MV_U32 winNum, MV_AUDIO_DEC_WIN *pAddrDecWin) ++{ ++ MV_TARGET_ATTRIB targetAttribs; ++ MV_DEC_REGS decRegs; ++ ++ /* Parameter checking */ ++ if (winNum >= MV_AUDIO_MAX_ADDR_DECODE_WIN) ++ { ++ mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); ++ return MV_BAD_PARAM; ++ } ++ ++ /* check if address is aligned to the size */ ++ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) ++ { ++ mvOsPrintf("mvAudioWinSet:Error setting AUDIO window %d to "\ ++ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", ++ winNum, ++ mvCtrlTargetNameGet(pAddrDecWin->target), ++ pAddrDecWin->addrWin.baseLow, ++ pAddrDecWin->addrWin.size); ++ return MV_ERROR; ++ } ++ ++ decRegs.baseReg = 0; ++ decRegs.sizeReg = 0; ++ ++ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) ++ { ++ mvOsPrintf("%s: mvCtrlAddrDecToReg Failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); ++ ++ /* set attributes */ ++ decRegs.sizeReg &= ~MV_AUDIO_WIN_ATTR_MASK; ++ decRegs.sizeReg |= (targetAttribs.attrib << MV_AUDIO_WIN_ATTR_OFFSET); ++ ++ /* set target ID */ ++ decRegs.sizeReg &= ~MV_AUDIO_WIN_TARGET_MASK; ++ decRegs.sizeReg |= (targetAttribs.targetId << MV_AUDIO_WIN_TARGET_OFFSET); ++ ++ if (pAddrDecWin->enable == MV_TRUE) ++ { ++ decRegs.sizeReg |= MV_AUDIO_WIN_ENABLE_MASK; ++ } ++ else ++ { ++ decRegs.sizeReg &= ~MV_AUDIO_WIN_ENABLE_MASK; ++ } ++ ++ MV_REG_WRITE( MV_AUDIO_WIN_CTRL_REG(winNum), decRegs.sizeReg); ++ MV_REG_WRITE( MV_AUDIO_WIN_BASE_REG(winNum), decRegs.baseReg); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvAudioWinGet - Get AUDIO peripheral target address window. ++* ++* DESCRIPTION: ++* Get AUDIO peripheral target address window. ++* ++* INPUT: ++* winNum - AUDIO target address decode window number. ++* ++* OUTPUT: ++* pAddrDecWin - AUDIO target window data structure. ++* ++* RETURN: ++* MV_ERROR if register parameters are invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvAudioWinGet(MV_U32 winNum, MV_AUDIO_DEC_WIN *pAddrDecWin) ++{ ++ MV_DEC_REGS decRegs; ++ MV_TARGET_ATTRIB targetAttrib; ++ ++ /* Parameter checking */ ++ if (winNum >= MV_AUDIO_MAX_ADDR_DECODE_WIN) ++ { ++ mvOsPrintf("%s : ERR. Invalid winNum %d\n", ++ __FUNCTION__, winNum); ++ return MV_NOT_SUPPORTED; ++ } ++ ++ decRegs.baseReg = MV_REG_READ( MV_AUDIO_WIN_BASE_REG(winNum) ); ++ decRegs.sizeReg = MV_REG_READ( MV_AUDIO_WIN_CTRL_REG(winNum) ); ++ ++ if (MV_OK != mvCtrlRegToAddrDec(&decRegs, &pAddrDecWin->addrWin) ) ++ { ++ mvOsPrintf("%s: mvCtrlRegToAddrDec Failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ /* attrib and targetId */ ++ targetAttrib.attrib = (decRegs.sizeReg & MV_AUDIO_WIN_ATTR_MASK) >> ++ MV_AUDIO_WIN_ATTR_OFFSET; ++ targetAttrib.targetId = (decRegs.sizeReg & MV_AUDIO_WIN_TARGET_MASK) >> ++ MV_AUDIO_WIN_TARGET_OFFSET; ++ ++ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); ++ ++ /* Check if window is enabled */ ++ if(decRegs.sizeReg & MV_AUDIO_WIN_ENABLE_MASK) ++ { ++ pAddrDecWin->enable = MV_TRUE; ++ } ++ else ++ { ++ pAddrDecWin->enable = MV_FALSE; ++ } ++ return MV_OK; ++} ++/******************************************************************************* ++* mvAudioAddrDecShow - Print the AUDIO address decode map. ++* ++* DESCRIPTION: ++* This function print the AUDIO address decode map. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvAudioAddrDecShow(MV_VOID) ++{ ++ ++ MV_AUDIO_DEC_WIN win; ++ int i; ++ ++ if (MV_FALSE == mvCtrlPwrClckGet(AUDIO_UNIT_ID, 0)) ++ return; ++ ++ ++ mvOsOutput( "\n" ); ++ mvOsOutput( "AUDIO:\n" ); ++ mvOsOutput( "----\n" ); ++ ++ for( i = 0; i < MV_AUDIO_MAX_ADDR_DECODE_WIN; i++ ) ++ { ++ memset( &win, 0, sizeof(MV_AUDIO_DEC_WIN) ); ++ ++ mvOsOutput( "win%d - ", i ); ++ ++ if( mvAudioWinGet( i, &win ) == MV_OK ) ++ { ++ if( win.enable ) ++ { ++ mvOsOutput( "%s base %08x, ", ++ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); ++ mvOsOutput( "...." ); ++ ++ mvSizePrint( win.addrWin.size ); ++ ++ mvOsOutput( "\n" ); ++ } ++ else ++ mvOsOutput( "disable\n" ); ++ } ++ } ++} ++ ++ ++/******************************************************************************* ++* mvAudioWinInit - Initialize the integrated AUDIO target address window. ++* ++* DESCRIPTION: ++* Initialize the AUDIO peripheral target address window. ++* ++* INPUT: ++* ++* ++* OUTPUT: ++* ++* ++* RETURN: ++* MV_ERROR if register parameters are invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvAudioInit(MV_VOID) ++{ ++ int winNum; ++ MV_AUDIO_DEC_WIN audioWin; ++ MV_CPU_DEC_WIN cpuAddrDecWin; ++ MV_U32 status; ++ ++ mvAudioHalInit(); ++ ++ /* Initiate Audio address decode */ ++ ++ /* First disable all address decode windows */ ++ for(winNum = 0; winNum < MV_AUDIO_MAX_ADDR_DECODE_WIN; winNum++) ++ { ++ MV_U32 regVal = MV_REG_READ(MV_AUDIO_WIN_CTRL_REG(winNum)); ++ regVal &= ~MV_AUDIO_WIN_ENABLE_MASK; ++ MV_REG_WRITE(MV_AUDIO_WIN_CTRL_REG(winNum), regVal); ++ } ++ ++ for(winNum = 0; winNum < MV_AUDIO_MAX_ADDR_DECODE_WIN; winNum++) ++ { ++ ++ /* We will set the Window to DRAM_CS0 in default */ ++ /* first get attributes from CPU If */ ++ status = mvCpuIfTargetWinGet(SDRAM_CS0, ++ &cpuAddrDecWin); ++ ++ if (MV_OK != status) ++ { ++ mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ if (cpuAddrDecWin.enable == MV_TRUE) ++ { ++ audioWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; ++ audioWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; ++ audioWin.addrWin.size = cpuAddrDecWin.addrWin.size; ++ audioWin.enable = MV_TRUE; ++ audioWin.target = SDRAM_CS0; ++ ++ if(MV_OK != mvAudioWinSet(winNum, &audioWin)) ++ { ++ return MV_ERROR; ++ } ++ } ++ } ++ ++ return MV_OK; ++} ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysAudio.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,123 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++#ifndef __INCMVSysAudioH ++#define __INCMVSysAudioH ++ ++#include "mvCommon.h" ++#include "audio/mvAudio.h" ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++#include "ctrlEnv/sys/mvCpuIf.h" ++ ++/***********************************/ ++/* Audio Address Decoding registers*/ ++/***********************************/ ++ ++#define MV_AUDIO_MAX_ADDR_DECODE_WIN 2 ++#define MV_AUDIO_RECORD_WIN_NUM 0 ++#define MV_AUDIO_PLAYBACK_WIN_NUM 1 ++ ++#define MV_AUDIO_WIN_CTRL_REG(win) (AUDIO_REG_BASE + 0xA04 + ((win)<<3)) ++#define MV_AUDIO_WIN_BASE_REG(win) (AUDIO_REG_BASE + 0xA00 + ((win)<<3)) ++ ++#define MV_AUDIO_RECORD_WIN_CTRL_REG MV_AUDIO_WIN_CTRL_REG(MV_AUDIO_RECORD_WIN_NUM) ++#define MV_AUDIO_RECORD_WIN_BASE_REG MV_AUDIO_WIN_BASE_REG(MV_AUDIO_RECORD_WIN_NUM) ++#define MV_AUDIO_PLAYBACK_WIN_CTRL_REG MV_AUDIO_WIN_CTRL_REG(MV_AUDIO_PLAYBACK_WIN_NUM) ++#define MV_AUDIO_PLAYBACK_WIN_BASE_REG MV_AUDIO_WIN_BASE_REG(MV_AUDIO_PLAYBACK_WIN_NUM) ++ ++ ++/* BITs in Windows 0-3 Control and Base Registers */ ++#define MV_AUDIO_WIN_ENABLE_BIT 0 ++#define MV_AUDIO_WIN_ENABLE_MASK (1<= 2) ++MV_TARGET tdmaAddrDecPrioTable[] = ++{ ++#if defined(MV_INCLUDE_SDRAM_CS0) ++ SDRAM_CS0, ++#endif ++#if defined(MV_INCLUDE_SDRAM_CS1) ++ SDRAM_CS1, ++#endif ++#if defined(MV_INCLUDE_SDRAM_CS2) ++ SDRAM_CS2, ++#endif ++#if defined(MV_INCLUDE_SDRAM_CS3) ++ SDRAM_CS3, ++#endif ++#if defined(MV_INCLUDE_PEX) ++ PEX0_MEM, ++#endif ++ ++ TBL_TERM ++}; ++ ++/******************************************************************************* ++* mvCesaWinGet - Get TDMA target address window. ++* ++* DESCRIPTION: ++* Get TDMA target address window. ++* ++* INPUT: ++* winNum - TDMA target address decode window number. ++* ++* OUTPUT: ++* pDecWin - TDMA target window data structure. ++* ++* RETURN: ++* MV_ERROR if register parameters are invalid. ++* ++*******************************************************************************/ ++static MV_STATUS mvCesaWinGet(MV_U32 winNum, MV_DEC_WIN *pDecWin) ++{ ++ MV_DEC_WIN_PARAMS winParam; ++ MV_U32 sizeReg, baseReg; ++ ++ /* Parameter checking */ ++ if (winNum >= MV_CESA_TDMA_ADDR_DEC_WIN) ++ { ++ mvOsPrintf("%s : ERR. Invalid winNum %d\n", ++ __FUNCTION__, winNum); ++ return MV_NOT_SUPPORTED; ++ } ++ ++ baseReg = MV_REG_READ( MV_CESA_TDMA_BASE_ADDR_REG(winNum) ); ++ sizeReg = MV_REG_READ( MV_CESA_TDMA_WIN_CTRL_REG(winNum) ); ++ ++ /* Check if window is enabled */ ++ if(sizeReg & MV_CESA_TDMA_WIN_ENABLE_MASK) ++ { ++ pDecWin->enable = MV_TRUE; ++ ++ /* Extract window parameters from registers */ ++ winParam.targetId = (sizeReg & MV_CESA_TDMA_WIN_TARGET_MASK) >> MV_CESA_TDMA_WIN_TARGET_OFFSET; ++ winParam.attrib = (sizeReg & MV_CESA_TDMA_WIN_ATTR_MASK) >> MV_CESA_TDMA_WIN_ATTR_OFFSET; ++ winParam.size = (sizeReg & MV_CESA_TDMA_WIN_SIZE_MASK) >> MV_CESA_TDMA_WIN_SIZE_OFFSET; ++ winParam.baseAddr = (baseReg & MV_CESA_TDMA_WIN_BASE_MASK); ++ ++ /* Translate the decode window parameters to address decode struct */ ++ if (MV_OK != mvCtrlParamsToAddrDec(&winParam, pDecWin)) ++ { ++ mvOsPrintf("Failed to translate register parameters to CESA address" \ ++ " decode window structure\n"); ++ return MV_ERROR; ++ } ++ } ++ else ++ { ++ pDecWin->enable = MV_FALSE; ++ } ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* cesaWinOverlapDetect - Detect CESA TDMA address windows overlapping ++* ++* DESCRIPTION: ++* An unpredicted behaviur is expected in case TDMA address decode ++* windows overlapps. ++* This function detects TDMA address decode windows overlapping of a ++* specified window. The function does not check the window itself for ++* overlapping. The function also skipps disabled address decode windows. ++* ++* INPUT: ++* winNum - address decode window number. ++* pAddrDecWin - An address decode window struct. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE - if the given address window overlap current address ++* decode map, ++* MV_FALSE - otherwise, MV_ERROR if reading invalid data ++* from registers. ++* ++*******************************************************************************/ ++static MV_STATUS cesaWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) ++{ ++ MV_U32 winNumIndex; ++ MV_DEC_WIN addrDecWin; ++ ++ for(winNumIndex=0; winNumIndex= MV_CESA_TDMA_ADDR_DEC_WIN) ++ { ++ mvOsPrintf("mvCesaTdmaWinSet: ERR. Invalid win num %d\n",winNum); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check if the requested window overlapps with current windows */ ++ if (MV_TRUE == cesaWinOverlapDetect(winNum, &pDecWin->addrWin)) ++ { ++ mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); ++ return MV_ERROR; ++ } ++ ++ /* check if address is aligned to the size */ ++ if(MV_IS_NOT_ALIGN(pDecWin->addrWin.baseLow, pDecWin->addrWin.size)) ++ { ++ mvOsPrintf("mvCesaTdmaWinSet: Error setting CESA TDMA window %d to "\ ++ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", ++ winNum, ++ mvCtrlTargetNameGet(pDecWin->target), ++ pDecWin->addrWin.baseLow, ++ pDecWin->addrWin.size); ++ return MV_ERROR; ++ } ++ ++ if(MV_OK != mvCtrlAddrDecToParams(pDecWin, &winParams)) ++ { ++ mvOsPrintf("%s: mvCtrlAddrDecToParams Failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ /* set Size, Attributes and TargetID */ ++ sizeReg = (((winParams.targetId << MV_CESA_TDMA_WIN_TARGET_OFFSET) & MV_CESA_TDMA_WIN_TARGET_MASK) | ++ ((winParams.attrib << MV_CESA_TDMA_WIN_ATTR_OFFSET) & MV_CESA_TDMA_WIN_ATTR_MASK) | ++ ((winParams.size << MV_CESA_TDMA_WIN_SIZE_OFFSET) & MV_CESA_TDMA_WIN_SIZE_MASK)); ++ ++ if (pDecWin->enable == MV_TRUE) ++ { ++ sizeReg |= MV_CESA_TDMA_WIN_ENABLE_MASK; ++ } ++ else ++ { ++ sizeReg &= ~MV_CESA_TDMA_WIN_ENABLE_MASK; ++ } ++ ++ /* Update Base value */ ++ baseReg = (winParams.baseAddr & MV_CESA_TDMA_WIN_BASE_MASK); ++ ++ MV_REG_WRITE( MV_CESA_TDMA_WIN_CTRL_REG(winNum), sizeReg); ++ MV_REG_WRITE( MV_CESA_TDMA_BASE_ADDR_REG(winNum), baseReg); ++ ++ return MV_OK; ++} ++ ++ ++static MV_STATUS mvCesaTdmaAddrDecInit (void) ++{ ++ MV_U32 winNum; ++ MV_STATUS status; ++ MV_CPU_DEC_WIN cpuAddrDecWin; ++ MV_DEC_WIN cesaWin; ++ MV_U32 winPrioIndex = 0; ++ ++ /* First disable all address decode windows */ ++ for(winNum=0; winNum= 2 */ ++ ++ ++ ++ ++MV_STATUS mvCesaInit (int numOfSession, int queueDepth, char* pSramBase, void *osHandle) ++{ ++ MV_U32 cesaCryptEngBase; ++ MV_CPU_DEC_WIN addrDecWin; ++ ++ if(sizeof(MV_CESA_SRAM_MAP) > MV_CESA_SRAM_SIZE) ++ { ++ mvOsPrintf("mvCesaInit: Wrong SRAM map - %ld > %d\n", ++ sizeof(MV_CESA_SRAM_MAP), MV_CESA_SRAM_SIZE); ++ return MV_FAIL; ++ } ++#if 0 ++ if (mvCpuIfTargetWinGet(CRYPT_ENG, &addrDecWin) == MV_OK) ++ cesaCryptEngBase = addrDecWin.addrWin.baseLow; ++ else ++ { ++ mvOsPrintf("mvCesaInit: ERR. mvCpuIfTargetWinGet failed\n"); ++ return MV_ERROR; ++ } ++#else ++ cesaCryptEngBase = (MV_U32)pSramBase; ++#endif ++ ++#if 0 /* Already done in the platform init */ ++#if (MV_CESA_VERSION >= 2) ++ mvCesaTdmaAddrDecInit(); ++#endif /* MV_CESA_VERSION >= 2 */ ++#endif ++ return mvCesaHalInit(numOfSession, queueDepth, pSramBase, cesaCryptEngBase, ++ osHandle); ++ ++} +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysCesa.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,100 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __mvSysCesa_h__ ++#define __mvSysCesa_h__ ++ ++ ++#include "mvCommon.h" ++#include "cesa/mvCesa.h" ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++#include "ctrlEnv/sys/mvCpuIf.h" ++ ++/***************************** TDMA Registers *************************************/ ++ ++#define MV_CESA_TDMA_ADDR_DEC_WIN 4 ++ ++#define MV_CESA_TDMA_BASE_ADDR_REG(win) (MV_CESA_TDMA_REG_BASE + 0xa00 + (win<<3)) ++ ++#define MV_CESA_TDMA_WIN_CTRL_REG(win) (MV_CESA_TDMA_REG_BASE + 0xa04 + (win<<3)) ++ ++#define MV_CESA_TDMA_WIN_ENABLE_BIT 0 ++#define MV_CESA_TDMA_WIN_ENABLE_MASK (1 << MV_CESA_TDMA_WIN_ENABLE_BIT) ++ ++#define MV_CESA_TDMA_WIN_TARGET_OFFSET 4 ++#define MV_CESA_TDMA_WIN_TARGET_MASK (0xf << MV_CESA_TDMA_WIN_TARGET_OFFSET) ++ ++#define MV_CESA_TDMA_WIN_ATTR_OFFSET 8 ++#define MV_CESA_TDMA_WIN_ATTR_MASK (0xff << MV_CESA_TDMA_WIN_ATTR_OFFSET) ++ ++#define MV_CESA_TDMA_WIN_SIZE_OFFSET 16 ++#define MV_CESA_TDMA_WIN_SIZE_MASK (0xFFFF << MV_CESA_TDMA_WIN_SIZE_OFFSET) ++ ++#define MV_CESA_TDMA_WIN_BASE_OFFSET 16 ++#define MV_CESA_TDMA_WIN_BASE_MASK (0xFFFF << MV_CESA_TDMA_WIN_BASE_OFFSET) ++ ++ ++MV_STATUS mvCesaInit (int numOfSession, int queueDepth, char* pSramBase, void *osHandle); ++ ++#endif +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.c linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.c +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,348 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++/* includes */ ++ ++#include "ddr2/mvDramIf.h" ++#include "ctrlEnv/sys/mvCpuIf.h" ++#include "ctrlEnv/sys/mvSysDram.h" ++ ++/* #define MV_DEBUG */ ++#ifdef MV_DEBUG ++#define DB(x) x ++#else ++#define DB(x) ++#endif ++ ++static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin); ++ ++/******************************************************************************* ++* mvDramIfWinSet - Set DRAM interface address decode window ++* ++* DESCRIPTION: ++* This function sets DRAM interface address decode window. ++* ++* INPUT: ++* target - System target. Use only SDRAM targets. ++* pAddrDecWin - SDRAM address window structure. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK ++* otherwise. ++*******************************************************************************/ ++MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) ++{ ++ MV_U32 baseReg=0,sizeReg=0; ++ MV_U32 baseToReg=0 , sizeToReg=0; ++ ++ /* Check parameters */ ++ if (!MV_TARGET_IS_DRAM(target)) ++ { ++ mvOsPrintf("mvDramIfWinSet: target %d is not SDRAM\n", target); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check if the requested window overlaps with current enabled windows */ ++ if (MV_TRUE == sdramIfWinOverlap(target, &pAddrDecWin->addrWin)) ++ { ++ mvOsPrintf("mvDramIfWinSet: ERR. Target %d overlaps\n", target); ++ return MV_BAD_PARAM; ++ } ++ ++ /* check if address is aligned to the size */ ++ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) ++ { ++ mvOsPrintf("mvDramIfWinSet:Error setting DRAM interface window %d."\ ++ "\nAddress 0x%08x is unaligned to size 0x%x.\n", ++ target, ++ pAddrDecWin->addrWin.baseLow, ++ pAddrDecWin->addrWin.size); ++ return MV_ERROR; ++ } ++ ++ /* read base register*/ ++ baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(0,target)); ++ ++ /* read size register */ ++ sizeReg = MV_REG_READ(SDRAM_SIZE_REG(0,target)); ++ ++ /* BaseLow[31:16] => base register [31:16] */ ++ baseToReg = pAddrDecWin->addrWin.baseLow & SCBAR_BASE_MASK; ++ ++ /* Write to address decode Base Address Register */ ++ baseReg &= ~SCBAR_BASE_MASK; ++ baseReg |= baseToReg; ++ ++ /* Translate the given window size to register format */ ++ sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, SCSR_SIZE_ALIGNMENT); ++ ++ /* Size parameter validity check. */ ++ if (-1 == sizeToReg) ++ { ++ mvOsPrintf("mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n",target); ++ return MV_BAD_PARAM; ++ } ++ ++ /* set size */ ++ sizeReg &= ~SCSR_SIZE_MASK; ++ /* Size is located at upper 16 bits */ ++ sizeReg |= (sizeToReg << SCSR_SIZE_OFFS); ++ ++ /* enable/Disable */ ++ if (MV_TRUE == pAddrDecWin->enable) ++ { ++ sizeReg |= SCSR_WIN_EN; ++ } ++ else ++ { ++ sizeReg &= ~SCSR_WIN_EN; ++ } ++ ++ /* 3) Write to address decode Base Address Register */ ++ MV_REG_WRITE(SDRAM_BASE_ADDR_REG(0,target), baseReg); ++ ++ /* Write to address decode Size Register */ ++ MV_REG_WRITE(SDRAM_SIZE_REG(0,target), sizeReg); ++ ++ return MV_OK; ++} ++/******************************************************************************* ++* mvDramIfWinGet - Get DRAM interface address decode window ++* ++* DESCRIPTION: ++* This function gets DRAM interface address decode window. ++* ++* INPUT: ++* target - System target. Use only SDRAM targets. ++* ++* OUTPUT: ++* pAddrDecWin - SDRAM address window structure. ++* ++* RETURN: ++* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK ++* otherwise. ++*******************************************************************************/ ++MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) ++{ ++ MV_U32 baseReg,sizeReg; ++ MV_U32 sizeRegVal; ++ /* Check parameters */ ++ if (!MV_TARGET_IS_DRAM(target)) ++ { ++ mvOsPrintf("mvDramIfWinGet: target %d is Illigal\n", target); ++ return MV_ERROR; ++ } ++ ++ /* Read base and size registers */ ++ sizeReg = MV_REG_READ(SDRAM_SIZE_REG(0,target)); ++ baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(0,target)); ++ ++ sizeRegVal = (sizeReg & SCSR_SIZE_MASK) >> SCSR_SIZE_OFFS; ++ ++ pAddrDecWin->addrWin.size = ctrlRegToSize(sizeRegVal, ++ SCSR_SIZE_ALIGNMENT); ++ ++ /* Check if ctrlRegToSize returned OK */ ++ if (-1 == pAddrDecWin->addrWin.size) ++ { ++ mvOsPrintf("mvDramIfWinGet: size of target %d is Illigal\n", target); ++ return MV_ERROR; ++ } ++ ++ /* Extract base address */ ++ /* Base register [31:16] ==> baseLow[31:16] */ ++ pAddrDecWin->addrWin.baseLow = baseReg & SCBAR_BASE_MASK; ++ ++ pAddrDecWin->addrWin.baseHigh = 0; ++ ++ ++ if (sizeReg & SCSR_WIN_EN) ++ { ++ pAddrDecWin->enable = MV_TRUE; ++ } ++ else ++ { ++ pAddrDecWin->enable = MV_FALSE; ++ } ++ ++ return MV_OK; ++} ++/******************************************************************************* ++* mvDramIfWinEnable - Enable/Disable SDRAM address decode window ++* ++* DESCRIPTION: ++* This function enable/Disable SDRAM address decode window. ++* ++* INPUT: ++* target - System target. Use only SDRAM targets. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_ERROR in case function parameter are invalid, MV_OK otherewise. ++* ++*******************************************************************************/ ++MV_STATUS mvDramIfWinEnable(MV_TARGET target, MV_BOOL enable) ++{ ++ MV_DRAM_DEC_WIN addrDecWin; ++ ++ /* Check parameters */ ++ if (!MV_TARGET_IS_DRAM(target)) ++ { ++ mvOsPrintf("mvDramIfWinEnable: target %d is Illigal\n", target); ++ return MV_ERROR; ++ } ++ ++ if (enable == MV_TRUE) ++ { /* First check for overlap with other enabled windows */ ++ if (MV_OK != mvDramIfWinGet(target, &addrDecWin)) ++ { ++ mvOsPrintf("mvDramIfWinEnable:ERR. Getting target %d failed.\n", ++ target); ++ return MV_ERROR; ++ } ++ /* Check for overlapping */ ++ if (MV_FALSE == sdramIfWinOverlap(target, &(addrDecWin.addrWin))) ++ { ++ /* No Overlap. Enable address decode winNum window */ ++ MV_REG_BIT_SET(SDRAM_SIZE_REG(0,target), SCSR_WIN_EN); ++ } ++ else ++ { /* Overlap detected */ ++ mvOsPrintf("mvDramIfWinEnable: ERR. Target %d overlap detect\n", ++ target); ++ return MV_ERROR; ++ } ++ } ++ else ++ { /* Disable address decode winNum window */ ++ MV_REG_BIT_RESET(SDRAM_SIZE_REG(0, target), SCSR_WIN_EN); ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* sdramIfWinOverlap - Check if an address window overlap an SDRAM address window ++* ++* DESCRIPTION: ++* This function scan each SDRAM address decode window to test if it ++* overlapps the given address windoow ++* ++* INPUT: ++* target - SDRAM target where the function skips checking. ++* pAddrDecWin - The tested address window for overlapping with ++* SDRAM windows. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the given address window overlaps any enabled address ++* decode map, MV_FALSE otherwise. ++* ++*******************************************************************************/ ++static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin) ++{ ++ MV_TARGET targetNum; ++ MV_DRAM_DEC_WIN addrDecWin; ++ ++ for(targetNum = SDRAM_CS0; targetNum < MV_DRAM_MAX_CS ; targetNum++) ++ { ++ /* don't check our winNum or illegal targets */ ++ if (targetNum == target) ++ { ++ continue; ++ } ++ ++ /* Get window parameters */ ++ if (MV_OK != mvDramIfWinGet(targetNum, &addrDecWin)) ++ { ++ mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); ++ return MV_ERROR; ++ } ++ ++ /* Do not check disabled windows */ ++ if (MV_FALSE == addrDecWin.enable) ++ { ++ continue; ++ } ++ ++ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) ++ { ++ mvOsPrintf( ++ "sdramIfWinOverlap: Required target %d overlap winNum %d\n", ++ target, targetNum); ++ return MV_TRUE; ++ } ++ } ++ ++ return MV_FALSE; ++} ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysDram.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,80 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __sysDram ++#define __sysDram ++ ++/* This structure describes CPU interface address decode window */ ++typedef struct _mvDramIfDecWin ++{ ++ MV_ADDR_WIN addrWin; /* An address window*/ ++ MV_BOOL enable; /* Address decode window is enabled/disabled */ ++}MV_DRAM_DEC_WIN; ++ ++MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); ++MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); ++MV_STATUS mvDramIfWinEnable(MV_TARGET target, MV_BOOL enable); ++ ++#endif +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysGbe.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,658 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#include "ctrlEnv/sys/mvSysGbe.h" ++ ++ ++ ++typedef struct _mvEthDecWin ++{ ++ MV_TARGET target; ++ MV_ADDR_WIN addrWin; /* An address window*/ ++ MV_BOOL enable; /* Address decode window is enabled/disabled */ ++ ++}MV_ETH_DEC_WIN; ++ ++MV_TARGET ethAddrDecPrioTap[] = ++{ ++#if defined(MV_INCLUDE_SDRAM_CS0) ++ SDRAM_CS0, ++#endif ++#if defined(MV_INCLUDE_SDRAM_CS1) ++ SDRAM_CS1, ++#endif ++#if defined(MV_INCLUDE_SDRAM_CS2) ++ SDRAM_CS2, ++#endif ++#if defined(MV_INCLUDE_SDRAM_CS3) ++ SDRAM_CS3, ++#endif ++#if defined(MV_INCLUDE_DEVICE_CS0) ++ DEVICE_CS0, ++#endif ++#if defined(MV_INCLUDE_DEVICE_CS1) ++ DEVICE_CS1, ++#endif ++#if defined(MV_INCLUDE_DEVICE_CS2) ++ DEVICE_CS2, ++#endif ++#if defined(MV_INCLUDE_DEVICE_CS3) ++ DEVICE_CS3, ++#endif ++#if defined(MV_INCLUDE_PEX) ++ PEX0_IO, ++#endif ++ TBL_TERM ++}; ++ ++static MV_STATUS ethWinOverlapDetect(int port, MV_U32 winNum, MV_ADDR_WIN *pAddrWin); ++static MV_STATUS mvEthWinSet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin); ++static MV_STATUS mvEthWinGet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin); ++ ++ ++/******************************************************************************* ++* mvEthWinInit - Initialize ETH address decode windows ++* ++* DESCRIPTION: ++* This function initialize ETH window decode unit. It set the ++* default address decode windows of the unit. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_ERROR if setting fail. ++*******************************************************************************/ ++/* Configure EthDrv memory map registes. */ ++MV_STATUS mvEthWinInit (int port) ++{ ++ MV_U32 winNum, status, winPrioIndex=0, i, regVal=0; ++ MV_ETH_DEC_WIN ethWin; ++ MV_CPU_DEC_WIN cpuAddrDecWin; ++ static MV_U32 accessProtReg = 0; ++ ++#if (MV_ETH_VERSION <= 1) ++ static MV_BOOL isFirst = MV_TRUE; ++ ++ if(isFirst == MV_FALSE) ++ { ++ MV_REG_WRITE(ETH_ACCESS_PROTECT_REG(port), accessProtReg); ++ return MV_OK; ++ } ++ isFirst = MV_FALSE; ++#endif /* MV_GIGA_ETH_VERSION */ ++ ++ /* Initiate Ethernet address decode */ ++ ++ /* First disable all address decode windows */ ++ for(winNum=0; winNum= ETH_MAX_DECODE_WIN) ++ { ++ mvOsPrintf("mvEthWinSet: ERR. Invalid win num %d\n",winNum); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check if the requested window overlapps with current windows */ ++ if (MV_TRUE == ethWinOverlapDetect(port, winNum, &pAddrDecWin->addrWin)) ++ { ++ mvOsPrintf("mvEthWinSet: ERR. Window %d overlap\n", winNum); ++ return MV_ERROR; ++ } ++ ++ /* check if address is aligned to the size */ ++ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) ++ { ++ mvOsPrintf("mvEthWinSet: Error setting Ethernet window %d to "\ ++ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", ++ winNum, ++ mvCtrlTargetNameGet(pAddrDecWin->target), ++ pAddrDecWin->addrWin.baseLow, ++ pAddrDecWin->addrWin.size); ++ return MV_ERROR; ++ } ++ ++ ++ decRegs.baseReg = MV_REG_READ(ETH_WIN_BASE_REG(port, winNum)); ++ decRegs.sizeReg = MV_REG_READ(ETH_WIN_SIZE_REG(port, winNum)); ++ ++ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) ++ { ++ mvOsPrintf("mvEthWinSet:mvCtrlAddrDecToReg Failed\n"); ++ return MV_ERROR; ++ } ++ ++ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); ++ ++ /* set attributes */ ++ decRegs.baseReg &= ~ETH_WIN_ATTR_MASK; ++ decRegs.baseReg |= targetAttribs.attrib << ETH_WIN_ATTR_OFFS; ++ /* set target ID */ ++ decRegs.baseReg &= ~ETH_WIN_TARGET_MASK; ++ decRegs.baseReg |= targetAttribs.targetId << ETH_WIN_TARGET_OFFS; ++ ++ /* for the safe side we disable the window before writing the new ++ values */ ++ mvEthWinEnable(port, winNum, MV_FALSE); ++ MV_REG_WRITE(ETH_WIN_BASE_REG(port, winNum), decRegs.baseReg); ++ ++ /* Write to address decode Size Register */ ++ MV_REG_WRITE(ETH_WIN_SIZE_REG(port, winNum), decRegs.sizeReg); ++ ++ /* Enable address decode target window */ ++ if (pAddrDecWin->enable == MV_TRUE) ++ { ++ mvEthWinEnable(port, winNum, MV_TRUE); ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvETHWinGet - Get dma peripheral target address window. ++* ++* DESCRIPTION: ++* Get ETH peripheral target address window. ++* ++* INPUT: ++* winNum - ETH to target address decode window number. ++* ++* OUTPUT: ++* pAddrDecWin - ETH target window data structure. ++* ++* RETURN: ++* MV_ERROR if register parameters are invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvEthWinGet(int port, MV_U32 winNum, MV_ETH_DEC_WIN *pAddrDecWin) ++{ ++ MV_DEC_REGS decRegs; ++ MV_TARGET_ATTRIB targetAttrib; ++ ++ /* Parameter checking */ ++ if (winNum >= ETH_MAX_DECODE_WIN) ++ { ++ mvOsPrintf("mvEthWinGet: ERR. Invalid winNum %d\n", winNum); ++ return MV_NOT_SUPPORTED; ++ } ++ ++ decRegs.baseReg = MV_REG_READ(ETH_WIN_BASE_REG(port, winNum)); ++ decRegs.sizeReg = MV_REG_READ(ETH_WIN_SIZE_REG(port, winNum)); ++ ++ if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) ++ { ++ mvOsPrintf("mvAhbToMbusWinGet: mvCtrlRegToAddrDec Failed \n"); ++ return MV_ERROR; ++ } ++ ++ /* attrib and targetId */ ++ targetAttrib.attrib = ++ (decRegs.baseReg & ETH_WIN_ATTR_MASK) >> ETH_WIN_ATTR_OFFS; ++ targetAttrib.targetId = ++ (decRegs.baseReg & ETH_WIN_TARGET_MASK) >> ETH_WIN_TARGET_OFFS; ++ ++ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); ++ ++ /* Check if window is enabled */ ++ if (~(MV_REG_READ(ETH_BASE_ADDR_ENABLE_REG(port))) & (1 << winNum) ) ++ { ++ pAddrDecWin->enable = MV_TRUE; ++ } ++ else ++ { ++ pAddrDecWin->enable = MV_FALSE; ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvEthWinEnable - Enable/disable a ETH to target address window ++* ++* DESCRIPTION: ++* This function enable/disable a ETH to target address window. ++* According to parameter 'enable' the routine will enable the ++* window, thus enabling ETH accesses (before enabling the window it is ++* tested for overlapping). Otherwise, the window will be disabled. ++* ++* INPUT: ++* winNum - ETH to target address decode window number. ++* enable - Enable/disable parameter. ++* ++* OUTPUT: ++* N/A ++* ++* RETURN: ++* MV_ERROR if decode window number was wrong or enabled window overlapps. ++* ++*******************************************************************************/ ++MV_STATUS mvEthWinEnable(int port, MV_U32 winNum,MV_BOOL enable) ++{ ++ MV_ETH_DEC_WIN addrDecWin; ++ ++ /* Parameter checking */ ++ if (winNum >= ETH_MAX_DECODE_WIN) ++ { ++ mvOsPrintf("mvEthTargetWinEnable:ERR. Invalid winNum%d\n",winNum); ++ return MV_ERROR; ++ } ++ ++ if (enable == MV_TRUE) ++ { /* First check for overlap with other enabled windows */ ++ /* Get current window */ ++ if (MV_OK != mvEthWinGet(port, winNum, &addrDecWin)) ++ { ++ mvOsPrintf("mvEthTargetWinEnable:ERR. targetWinGet fail\n"); ++ return MV_ERROR; ++ } ++ /* Check for overlapping */ ++ if (MV_FALSE == ethWinOverlapDetect(port, winNum, &(addrDecWin.addrWin))) ++ { ++ /* No Overlap. Enable address decode target window */ ++ MV_REG_BIT_RESET(ETH_BASE_ADDR_ENABLE_REG(port), (1 << winNum)); ++ } ++ else ++ { /* Overlap detected */ ++ mvOsPrintf("mvEthTargetWinEnable:ERR. Overlap detected\n"); ++ return MV_ERROR; ++ } ++ } ++ else ++ { /* Disable address decode target window */ ++ MV_REG_BIT_SET(ETH_BASE_ADDR_ENABLE_REG(port), (1 << winNum)); ++ } ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvEthWinTargetGet - Get Window number associated with target ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++* window number ++* ++*******************************************************************************/ ++MV_U32 mvEthWinTargetGet(int port, MV_TARGET target) ++{ ++ MV_ETH_DEC_WIN decWin; ++ MV_U32 winNum; ++ ++ /* Check parameters */ ++ if (target >= MAX_TARGETS) ++ { ++ mvOsPrintf("mvAhbToMbusWinTargetGet: target %d is Illigal\n", target); ++ return 0xffffffff; ++ } ++ ++ for (winNum=0; winNum= mvCtrlEthMaxPortGet()) ++ { ++ mvOsPrintf("mvEthProtWinSet:ERR. Invalid port number %d\n", portNo); ++ return MV_ERROR; ++ } ++ ++ if (winNum >= ETH_MAX_DECODE_WIN) ++ { ++ mvOsPrintf("mvEthProtWinSet:ERR. Invalid winNum%d\n",winNum); ++ return MV_ERROR; ++ } ++ ++ if((access == ACC_RESERVED) || (access >= MAX_ACC_RIGHTS)) ++ { ++ mvOsPrintf("mvEthProtWinSet:ERR. Inv access param %d\n", access); ++ return MV_ERROR; ++ } ++ /* Read current protection register */ ++ protReg = MV_REG_READ(ETH_ACCESS_PROTECT_REG(portNo)); ++ ++ /* Clear protection window field */ ++ protReg &= ~(ETH_PROT_WIN_MASK(winNum)); ++ ++ /* Set new protection field value */ ++ protReg |= (access << (ETH_PROT_WIN_OFFS(winNum))); ++ ++ /* Write protection register back */ ++ MV_REG_WRITE(ETH_ACCESS_PROTECT_REG(portNo), protReg); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* ethWinOverlapDetect - Detect ETH address windows overlapping ++* ++* DESCRIPTION: ++* An unpredicted behaviur is expected in case ETH address decode ++* windows overlapps. ++* This function detects ETH address decode windows overlapping of a ++* specified window. The function does not check the window itself for ++* overlapping. The function also skipps disabled address decode windows. ++* ++* INPUT: ++* winNum - address decode window number. ++* pAddrDecWin - An address decode window struct. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the given address window overlap current address ++* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data ++* from registers. ++* ++*******************************************************************************/ ++static MV_STATUS ethWinOverlapDetect(int port, MV_U32 winNum, MV_ADDR_WIN *pAddrWin) ++{ ++ MV_U32 baseAddrEnableReg; ++ MV_U32 winNumIndex; ++ MV_ETH_DEC_WIN addrDecWin; ++ ++ /* Read base address enable register. Do not check disabled windows */ ++ baseAddrEnableReg = MV_REG_READ(ETH_BASE_ADDR_ENABLE_REG(port)); ++ ++ for (winNumIndex=0; winNumIndex= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexInit: ERR. Invalid PEX interface %d\n", pexIf); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Enabled CPU access to PCI-Express */ ++ mvCpuIfEnablePex(pexIf, pexType); ++ ++ /* Start with bars */ ++ /* First disable all PEX bars*/ ++ for (bar = 0; bar < PEX_MAX_BARS; bar++) ++ { ++ if (PEX_INTER_REGS_BAR != bar) ++ { ++ if (MV_OK != mvPexBarEnable(pexIf, bar, MV_FALSE)) ++ { ++ mvOsPrintf("mvPexInit:mvPexBarEnable bar =%d failed \n",bar); ++ return MV_ERROR; ++ } ++ ++ } ++ ++ } ++ ++ /* and disable all PEX target windows */ ++ for (winNum = 0; winNum < PEX_MAX_TARGET_WIN - 2; winNum++) ++ { ++ if (MV_OK != mvPexTargetWinEnable(pexIf, winNum, MV_FALSE)) ++ { ++ mvOsPrintf("mvPexInit:mvPexTargetWinEnable winNum =%d failed \n", ++ winNum); ++ return MV_ERROR; ++ ++ } ++ } ++ ++ /* Now, go through all bars*/ ++ ++ ++ ++/******************************************************************************/ ++/* Internal registers bar */ ++/******************************************************************************/ ++ bar = PEX_INTER_REGS_BAR; ++ ++ /* we only open the bar , no need to open windows for this bar */ ++ ++ /* first get the CS attribute from the CPU Interface */ ++ if (MV_OK !=mvCpuIfTargetWinGet(INTER_REGS,&addrDecWin)) ++ { ++ mvOsPrintf("mvPexInit: ERR. mvCpuIfTargetWinGet failed target =%d\n",INTER_REGS); ++ return MV_ERROR; ++ } ++ ++ pexBar.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; ++ pexBar.addrWin.baseLow = addrDecWin.addrWin.baseLow; ++ pexBar.addrWin.size = addrDecWin.addrWin.size; ++ pexBar.enable = MV_TRUE; ++ ++ if (MV_OK != mvPexBarSet(pexIf, bar, &pexBar)) ++ { ++ mvOsPrintf("mvPexInit: ERR. mvPexBarSet %d failed\n", bar); ++ return MV_ERROR; ++ } ++ ++/******************************************************************************/ ++/* DRAM bar */ ++/******************************************************************************/ ++ ++ bar = PEX_DRAM_BAR; ++ ++ pexBar.addrWin.size = 0; ++ ++ for (target = SDRAM_CS0;target < MV_DRAM_MAX_CS; target++ ) ++ { ++ ++ status = mvCpuIfTargetWinGet(target,&addrDecWin); ++ ++ if((MV_NO_SUCH == status)&&(target != SDRAM_CS0)) ++ { ++ continue; ++ } ++ ++ /* first get attributes from CPU If */ ++ if (MV_OK != status) ++ { ++ mvOsPrintf("mvPexInit: ERR. mvCpuIfTargetWinGet failed target =%d\n",target); ++ return MV_ERROR; ++ } ++ if (addrDecWin.enable == MV_TRUE) ++ { ++ /* the base is the base of DRAM CS0 always */ ++ if (SDRAM_CS0 == target ) ++ { ++ pexBar.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; ++ pexBar.addrWin.baseLow = addrDecWin.addrWin.baseLow; ++ ++ } ++ ++ /* increment the bar size to be the sum of the size of all ++ DRAM chips selecs */ ++ pexBar.addrWin.size += addrDecWin.addrWin.size; ++ ++ /* set a Pex window for this target ! ++ DRAM CS always will have a Pex Window , and is not a ++ part of the priority table */ ++ pexWin.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; ++ pexWin.addrWin.baseLow = addrDecWin.addrWin.baseLow; ++ pexWin.addrWin.size = addrDecWin.addrWin.size; ++ ++ /* we disable the windows at first because we are not ++ sure that it is witihin bar boundries */ ++ pexWin.enable =MV_FALSE; ++ pexWin.target = target; ++ pexWin.targetBar = bar; ++ ++ if (MV_OK != mvPexTargetWinSet(pexIf,pexCurrWin++,&pexWin)) ++ { ++ mvOsPrintf("mvPexInit: ERR. mvPexTargetWinSet failed\n"); ++ return MV_ERROR; ++ } ++ } ++ } ++ ++ /* check if the size of the bar is illeggal */ ++ if (-1 == ctrlSizeToReg(pexBar.addrWin.size, PXBCR_BAR_SIZE_ALIGNMENT)) ++ { ++ /* try to get a good size */ ++ pexBar.addrWin.size = ctrlSizeRegRoundUp(pexBar.addrWin.size, ++ PXBCR_BAR_SIZE_ALIGNMENT); ++ } ++ ++ /* check if the size and base are valid */ ++ if (MV_TRUE == pexBarOverlapDetect(pexIf,bar,&pexBar.addrWin)) ++ { ++ mvOsPrintf("mvPexInit:Warning :Bar %d size is illigal\n",bar); ++ mvOsPrintf("it will be disabled\n"); ++ mvOsPrintf("please check Pex and CPU windows configuration\n"); ++ } ++ else ++ { ++ pexBar.enable = MV_TRUE; ++ ++ /* configure the bar */ ++ if (MV_OK != mvPexBarSet(pexIf, bar, &pexBar)) ++ { ++ mvOsPrintf("mvPexInit: ERR. mvPexBarSet %d failed\n", bar); ++ return MV_ERROR; ++ } ++ ++ /* after the bar was configured then we enable the Pex windows*/ ++ for (winNum = 0;winNum < pexCurrWin ;winNum++) ++ { ++ if (MV_OK != mvPexTargetWinEnable(pexIf, winNum, MV_TRUE)) ++ { ++ mvOsPrintf("mvPexInit: Can't enable window =%d\n",winNum); ++ return MV_ERROR; ++ } ++ ++ } ++ } ++ ++/******************************************************************************/ ++/* DEVICE bar */ ++/******************************************************************************/ ++ ++/* Open the Device BAR for non linux only */ ++#ifndef MV_DISABLE_PEX_DEVICE_BAR ++ ++ /* then device bar*/ ++ bar = PEX_DEVICE_BAR; ++ ++ /* save the starting window */ ++ pexStartWindow = pexCurrWin; ++ pexBar.addrWin.size = 0; ++ pexBar.addrWin.baseLow = 0xffffffff; ++ pexBar.addrWin.baseHigh = 0; ++ maxBase = 0; ++ ++ for (target = DEV_TO_TARGET(START_DEV_CS);target < DEV_TO_TARGET(MV_DEV_MAX_CS); target++ ) ++ { ++ status = mvCpuIfTargetWinGet(target,&addrDecWin); ++ ++ if (MV_NO_SUCH == status) ++ { ++ continue; ++ } ++ ++ if (MV_OK != status) ++ { ++ mvOsPrintf("mvPexInit: ERR. mvCpuIfTargetWinGet failed target =%d\n",target); ++ return MV_ERROR; ++ } ++ ++ if (addrDecWin.enable == MV_TRUE) ++ { ++ /* get the minimum base */ ++ if (addrDecWin.addrWin.baseLow < pexBar.addrWin.baseLow) ++ { ++ pexBar.addrWin.baseLow = addrDecWin.addrWin.baseLow; ++ } ++ ++ /* get the maximum base */ ++ if (addrDecWin.addrWin.baseLow > maxBase) ++ { ++ maxBase = addrDecWin.addrWin.baseLow; ++ sizeOfMaxBase = addrDecWin.addrWin.size; ++ } ++ ++ /* search in the priority table for this target */ ++ for (winIndex = 0; pexDevBarPrioTable[winIndex] != TBL_TERM; ++ winIndex++) ++ { ++ if (pexDevBarPrioTable[winIndex] != target) ++ { ++ continue; ++ } ++ else if (pexDevBarPrioTable[winIndex] == target) ++ { ++ /*found it */ ++ ++ /* if the index of this target in the prio table is valid ++ then we set the Pex window for this target, a valid index is ++ an index that is lower than the number of the windows that ++ was not configured yet */ ++ ++ /* we subtract 2 always because the default and expantion ++ rom windows are always configured */ ++ if ( pexCurrWin < PEX_MAX_TARGET_WIN - 2) ++ { ++ /* set a Pex window for this target ! */ ++ pexWin.addrWin.baseHigh = addrDecWin.addrWin.baseHigh; ++ pexWin.addrWin.baseLow = addrDecWin.addrWin.baseLow; ++ pexWin.addrWin.size = addrDecWin.addrWin.size; ++ ++ /* we disable the windows at first because we are not ++ sure that it is witihin bar boundries */ ++ pexWin.enable = MV_FALSE; ++ pexWin.target = target; ++ pexWin.targetBar = bar; ++ ++ if (MV_OK != mvPexTargetWinSet(pexIf,pexCurrWin++, ++ &pexWin)) ++ { ++ mvOsPrintf("mvPexInit: ERR. Window Set failed\n"); ++ return MV_ERROR; ++ } ++ } ++ } ++ } ++ } ++ } ++ ++ pexBar.addrWin.size = maxBase - pexBar.addrWin.baseLow + sizeOfMaxBase; ++ pexBar.enable = MV_TRUE; ++ ++ /* check if the size of the bar is illegal */ ++ if (-1 == ctrlSizeToReg(pexBar.addrWin.size, PXBCR_BAR_SIZE_ALIGNMENT)) ++ { ++ /* try to get a good size */ ++ pexBar.addrWin.size = ctrlSizeRegRoundUp(pexBar.addrWin.size, ++ PXBCR_BAR_SIZE_ALIGNMENT); ++ } ++ ++ /* check if the size and base are valid */ ++ if (MV_TRUE == pexBarOverlapDetect(pexIf,bar,&pexBar.addrWin)) ++ { ++ mvOsPrintf("mvPexInit:Warning :Bar %d size is illigal\n",bar); ++ mvOsPrintf("it will be disabled\n"); ++ mvOsPrintf("please check Pex and CPU windows configuration\n"); ++ } ++ else ++ { ++ if (MV_OK != mvPexBarSet(pexIf, bar, &pexBar)) ++ { ++ mvOsPrintf("mvPexInit: ERR. mvPexBarSet %d failed\n", bar); ++ return MV_ERROR; ++ } ++ ++ /* now enable the windows */ ++ for (winNum = pexStartWindow; winNum < pexCurrWin ; winNum++) ++ { ++ if (MV_OK != mvPexTargetWinEnable(pexIf, winNum, MV_TRUE)) ++ { ++ mvOsPrintf("mvPexInit:mvPexTargetWinEnable winNum =%d failed \n", ++ winNum); ++ return MV_ERROR; ++ } ++ } ++ } ++ ++#endif ++ ++ return mvPexHalInit(pexIf, pexType); ++ ++} ++ ++/******************************************************************************* ++* mvPexTargetWinSet - Set PEX to peripheral target address window BAR ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* N/A ++* ++* RETURN: ++* MV_OK if PEX BAR target window was set correctly, ++* MV_BAD_PARAM on bad params ++* MV_ERROR otherwise ++* (e.g. address window overlapps with other active PEX target window). ++* ++*******************************************************************************/ ++MV_STATUS mvPexTargetWinSet(MV_U32 pexIf, MV_U32 winNum, ++ MV_PEX_DEC_WIN *pAddrDecWin) ++{ ++ ++ MV_DEC_REGS decRegs; ++ PEX_WIN_REG_INFO winRegInfo; ++ MV_TARGET_ATTRIB targetAttribs; ++ ++ /* Parameter checking */ ++ if(pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexTargetWinSet: ERR. Invalid PEX interface %d\n", pexIf); ++ return MV_BAD_PARAM; ++ } ++ ++ if (winNum >= PEX_MAX_TARGET_WIN) ++ { ++ mvOsPrintf("mvPexTargetWinSet: ERR. Invalid PEX winNum %d\n", winNum); ++ return MV_BAD_PARAM; ++ ++ } ++ ++ /* get the pex Window registers offsets */ ++ pexWinRegInfoGet(pexIf,winNum,&winRegInfo); ++ ++ ++ if (MV_TRUE == pAddrDecWin->enable) ++ { ++ ++ /* 2) Check if the requested window overlaps with current windows */ ++ if (MV_TRUE == pexWinOverlapDetect(pexIf,winNum, &pAddrDecWin->addrWin)) ++ { ++ mvOsPrintf("mvPexTargetWinSet: ERR. Target %d overlap\n", winNum); ++ return MV_BAD_PARAM; ++ } ++ ++ /* 2) Check if the requested window overlaps with current windows */ ++ if (MV_FALSE == pexIsWinWithinBar(pexIf,&pAddrDecWin->addrWin)) ++ { ++ mvOsPrintf("mvPexTargetWinSet: Win %d should be in bar boundries\n", ++ winNum); ++ return MV_BAD_PARAM; ++ } ++ ++ } ++ ++ ++ ++ /* read base register*/ ++ ++ if (winRegInfo.baseLowRegOffs) ++ { ++ decRegs.baseReg = MV_REG_READ(winRegInfo.baseLowRegOffs); ++ } ++ else ++ { ++ decRegs.baseReg = 0; ++ } ++ ++ if (winRegInfo.sizeRegOffs) ++ { ++ decRegs.sizeReg = MV_REG_READ(winRegInfo.sizeRegOffs); ++ } ++ else ++ { ++ decRegs.sizeReg =0; ++ } ++ ++ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) ++ { ++ mvOsPrintf("mvPexTargetWinSet:mvCtrlAddrDecToReg Failed\n"); ++ return MV_ERROR; ++ } ++ ++ /* enable\Disable */ ++ if (MV_TRUE == pAddrDecWin->enable) ++ { ++ decRegs.sizeReg |= PXWCR_WIN_EN; ++ } ++ else ++ { ++ decRegs.sizeReg &= ~PXWCR_WIN_EN; ++ } ++ ++ ++ /* clear bit location */ ++ decRegs.sizeReg &= ~PXWCR_WIN_BAR_MAP_MASK; ++ ++ /* set bar Mapping */ ++ if (pAddrDecWin->targetBar == 1) ++ { ++ decRegs.sizeReg |= PXWCR_WIN_BAR_MAP_BAR1; ++ } ++ else if (pAddrDecWin->targetBar == 2) ++ { ++ decRegs.sizeReg |= PXWCR_WIN_BAR_MAP_BAR2; ++ } ++ ++ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); ++ ++ /* set attributes */ ++ decRegs.sizeReg &= ~PXWCR_ATTRIB_MASK; ++ decRegs.sizeReg |= targetAttribs.attrib << PXWCR_ATTRIB_OFFS; ++ /* set target ID */ ++ decRegs.sizeReg &= ~PXWCR_TARGET_MASK; ++ decRegs.sizeReg |= targetAttribs.targetId << PXWCR_TARGET_OFFS; ++ ++ ++ /* 3) Write to address decode Base Address Register */ ++ ++ if (winRegInfo.baseLowRegOffs) ++ { ++ MV_REG_WRITE(winRegInfo.baseLowRegOffs, decRegs.baseReg); ++ } ++ ++ /* write size reg */ ++ if (winRegInfo.sizeRegOffs) ++ { ++ if ((MV_PEX_WIN_DEFAULT == winNum)|| ++ (MV_PEX_WIN_EXP_ROM == winNum)) ++ { ++ /* clear size because there is no size field*/ ++ decRegs.sizeReg &= ~PXWCR_SIZE_MASK; ++ ++ /* clear enable because there is no enable field*/ ++ decRegs.sizeReg &= ~PXWCR_WIN_EN; ++ ++ } ++ ++ MV_REG_WRITE(winRegInfo.sizeRegOffs, decRegs.sizeReg); ++ } ++ ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvPexTargetWinGet - Get PEX to peripheral target address window ++* ++* DESCRIPTION: ++* Get the PEX to peripheral target address window BAR. ++* ++* INPUT: ++* pexIf - PEX interface number. ++* bar - BAR to be accessed by slave. ++* ++* OUTPUT: ++* pAddrBarWin - PEX target window information data structure. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPexTargetWinGet(MV_U32 pexIf, MV_U32 winNum, ++ MV_PEX_DEC_WIN *pAddrDecWin) ++{ ++ MV_TARGET_ATTRIB targetAttrib; ++ MV_DEC_REGS decRegs; ++ ++ PEX_WIN_REG_INFO winRegInfo; ++ ++ /* Parameter checking */ ++ if(pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexTargetWinGet: ERR. Invalid PEX interface %d\n", pexIf); ++ return MV_BAD_PARAM; ++ } ++ ++ if (winNum >= PEX_MAX_TARGET_WIN) ++ { ++ mvOsPrintf("mvPexTargetWinGet: ERR. Invalid PEX winNum %d\n", winNum); ++ return MV_BAD_PARAM; ++ ++ } ++ ++ /* get the pex Window registers offsets */ ++ pexWinRegInfoGet(pexIf,winNum,&winRegInfo); ++ ++ /* read base register*/ ++ if (winRegInfo.baseLowRegOffs) ++ { ++ decRegs.baseReg = MV_REG_READ(winRegInfo.baseLowRegOffs); ++ } ++ else ++ { ++ decRegs.baseReg = 0; ++ } ++ ++ /* read size reg */ ++ if (winRegInfo.sizeRegOffs) ++ { ++ decRegs.sizeReg = MV_REG_READ(winRegInfo.sizeRegOffs); ++ } ++ else ++ { ++ decRegs.sizeReg =0; ++ } ++ ++ if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) ++ { ++ mvOsPrintf("mvPexTargetWinGet: mvCtrlRegToAddrDec Failed \n"); ++ return MV_ERROR; ++ ++ } ++ ++ if (decRegs.sizeReg & PXWCR_WIN_EN) ++ { ++ pAddrDecWin->enable = MV_TRUE; ++ } ++ else ++ { ++ pAddrDecWin->enable = MV_FALSE; ++ ++ } ++ ++ ++ #if 0 ++ if (-1 == pAddrDecWin->addrWin.size) ++ { ++ return MV_ERROR; ++ } ++ #endif ++ ++ ++ /* get target bar */ ++ if ((decRegs.sizeReg & PXWCR_WIN_BAR_MAP_MASK) == PXWCR_WIN_BAR_MAP_BAR1 ) ++ { ++ pAddrDecWin->targetBar = 1; ++ } ++ else if ((decRegs.sizeReg & PXWCR_WIN_BAR_MAP_MASK) == ++ PXWCR_WIN_BAR_MAP_BAR2 ) ++ { ++ pAddrDecWin->targetBar = 2; ++ } ++ ++ /* attrib and targetId */ ++ pAddrDecWin->attrib = (decRegs.sizeReg & PXWCR_ATTRIB_MASK) >> ++ PXWCR_ATTRIB_OFFS; ++ pAddrDecWin->targetId = (decRegs.sizeReg & PXWCR_TARGET_MASK) >> ++ PXWCR_TARGET_OFFS; ++ ++ targetAttrib.attrib = pAddrDecWin->attrib; ++ targetAttrib.targetId = pAddrDecWin->targetId; ++ ++ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); ++ ++ return MV_OK; ++ ++} ++ ++ ++/******************************************************************************* ++* mvPexTargetWinEnable - Enable/disable a PEX BAR window ++* ++* DESCRIPTION: ++* This function enable/disable a PEX BAR window. ++* if parameter 'enable' == MV_TRUE the routine will enable the ++* window, thus enabling PEX accesses for that BAR (before enabling the ++* window it is tested for overlapping). Otherwise, the window will ++* be disabled. ++* ++* INPUT: ++* pexIf - PEX interface number. ++* bar - BAR to be accessed by slave. ++* enable - Enable/disable parameter. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPexTargetWinEnable(MV_U32 pexIf,MV_U32 winNum, MV_BOOL enable) ++{ ++ PEX_WIN_REG_INFO winRegInfo; ++ MV_PEX_DEC_WIN addrDecWin; ++ ++ /* Parameter checking */ ++ if(pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexTargetWinEnable: ERR. Invalid PEX If %d\n", pexIf); ++ return MV_BAD_PARAM; ++ } ++ ++ if (winNum >= PEX_MAX_TARGET_WIN) ++ { ++ mvOsPrintf("mvPexTargetWinEnable ERR. Invalid PEX winNum %d\n", winNum); ++ return MV_BAD_PARAM; ++ ++ } ++ ++ ++ /* get the pex Window registers offsets */ ++ pexWinRegInfoGet(pexIf,winNum,&winRegInfo); ++ ++ ++ /* if the address windows is disabled , we only disable the appropriare ++ pex window and ignore other settings */ ++ ++ if (MV_FALSE == enable) ++ { ++ ++ /* this is not relevant to default and expantion rom ++ windows */ ++ if (winRegInfo.sizeRegOffs) ++ { ++ if ((MV_PEX_WIN_DEFAULT != winNum)&& ++ (MV_PEX_WIN_EXP_ROM != winNum)) ++ { ++ MV_REG_BIT_RESET(winRegInfo.sizeRegOffs, PXWCR_WIN_EN); ++ } ++ } ++ ++ } ++ else ++ { ++ if (MV_OK != mvPexTargetWinGet(pexIf,winNum, &addrDecWin)) ++ { ++ mvOsPrintf("mvPexTargetWinEnable: mvPexTargetWinGet Failed\n"); ++ return MV_ERROR; ++ } ++ ++ /* Check if the requested window overlaps with current windows */ ++ if (MV_TRUE == pexWinOverlapDetect(pexIf,winNum, &addrDecWin.addrWin)) ++ { ++ mvOsPrintf("mvPexTargetWinEnable: ERR. Target %d overlap\n", winNum); ++ return MV_BAD_PARAM; ++ } ++ ++ if (MV_FALSE == pexIsWinWithinBar(pexIf,&addrDecWin.addrWin)) ++ { ++ mvOsPrintf("mvPexTargetWinEnable: Win %d should be in bar boundries\n", ++ winNum); ++ return MV_BAD_PARAM; ++ } ++ ++ ++ /* this is not relevant to default and expantion rom ++ windows */ ++ if (winRegInfo.sizeRegOffs) ++ { ++ if ((MV_PEX_WIN_DEFAULT != winNum)&& ++ (MV_PEX_WIN_EXP_ROM != winNum)) ++ { ++ MV_REG_BIT_SET(winRegInfo.sizeRegOffs, PXWCR_WIN_EN); ++ } ++ } ++ ++ ++ } ++ ++ return MV_OK; ++ ++} ++ ++ ++ ++/******************************************************************************* ++* mvPexTargetWinRemap - Set PEX to target address window remap. ++* ++* DESCRIPTION: ++* The PEX interface supports remap of the BAR original address window. ++* For each BAR it is possible to define a remap address. For example ++* an address 0x12345678 that hits BAR 0x10 (SDRAM CS[0]) will be modified ++* according to remap register but will also be targeted to the ++* SDRAM CS[0]. ++* ++* INPUT: ++* pexIf - PEX interface number. ++* bar - Peripheral target enumerator accessed by slave. ++* pAddrWin - Address window to be checked. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPexTargetWinRemap(MV_U32 pexIf, MV_U32 winNum, ++ MV_PEX_REMAP_WIN *pAddrWin) ++{ ++ ++ PEX_WIN_REG_INFO winRegInfo; ++ ++ /* Parameter checking */ ++ if (pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX interface num %d\n", ++ pexIf); ++ return MV_BAD_PARAM; ++ } ++ if (MV_PEX_WIN_DEFAULT == winNum) ++ { ++ mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX win num %d\n", ++ winNum); ++ return MV_BAD_PARAM; ++ ++ } ++ ++ if (MV_IS_NOT_ALIGN(pAddrWin->addrWin.baseLow, PXWRR_REMAP_ALIGNMENT)) ++ { ++ mvOsPrintf("mvPexTargetWinRemap: Error remap PEX interface %d win %d."\ ++ "\nAddress 0x%08x is unaligned to size 0x%x.\n", ++ pexIf, ++ winNum, ++ pAddrWin->addrWin.baseLow, ++ pAddrWin->addrWin.size); ++ ++ return MV_ERROR; ++ } ++ ++ pexWinRegInfoGet(pexIf, winNum, &winRegInfo); ++ ++ /* Set remap low register value */ ++ MV_REG_WRITE(winRegInfo.remapLowRegOffs, pAddrWin->addrWin.baseLow); ++ ++ /* Skip base high settings if the BAR has only base low (32-bit) */ ++ if (0 != winRegInfo.remapHighRegOffs) ++ { ++ MV_REG_WRITE(winRegInfo.remapHighRegOffs, pAddrWin->addrWin.baseHigh); ++ } ++ ++ ++ if (pAddrWin->enable == MV_TRUE) ++ { ++ MV_REG_BIT_SET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); ++ } ++ else ++ { ++ MV_REG_BIT_RESET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvPexTargetWinRemapEnable - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++ ++MV_STATUS mvPexTargetWinRemapEnable(MV_U32 pexIf, MV_U32 winNum, ++ MV_BOOL enable) ++{ ++ PEX_WIN_REG_INFO winRegInfo; ++ ++ /* Parameter checking */ ++ if (pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX interface num %d\n", ++ pexIf); ++ return MV_BAD_PARAM; ++ } ++ if (MV_PEX_WIN_DEFAULT == winNum) ++ { ++ mvOsPrintf("mvPexTargetWinRemap: ERR. Invalid PEX win num %d\n", ++ winNum); ++ return MV_BAD_PARAM; ++ ++ } ++ ++ ++ pexWinRegInfoGet(pexIf, winNum, &winRegInfo); ++ ++ if (enable == MV_TRUE) ++ { ++ MV_REG_BIT_SET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); ++ } ++ else ++ { ++ MV_REG_BIT_RESET(winRegInfo.remapLowRegOffs,PXWRR_REMAP_EN); ++ } ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvPexBarSet - Set PEX bar address and size ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPexBarSet(MV_U32 pexIf, ++ MV_U32 barNum, ++ MV_PEX_BAR *pAddrWin) ++{ ++ MV_U32 regBaseLow; ++ MV_U32 regSize,sizeToReg; ++ ++ ++ /* check parameters */ ++ if(pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexBarSet: ERR. Invalid PEX interface %d\n", pexIf); ++ return MV_BAD_PARAM; ++ } ++ ++ if(barNum >= PEX_MAX_BARS) ++ { ++ mvOsPrintf("mvPexBarSet: ERR. Invalid bar number %d\n", barNum); ++ return MV_BAD_PARAM; ++ } ++ ++ ++ if (pAddrWin->addrWin.size == 0) ++ { ++ mvOsPrintf("mvPexBarSet: Size zero is Illigal\n" ); ++ return MV_BAD_PARAM; ++ } ++ ++ ++ /* Check if the window complies with PEX spec */ ++ if (MV_TRUE != pexBarIsValid(pAddrWin->addrWin.baseLow, ++ pAddrWin->addrWin.size)) ++ { ++ mvOsPrintf("mvPexBarSet: ERR. Target %d window invalid\n", barNum); ++ return MV_BAD_PARAM; ++ } ++ ++ /* 2) Check if the requested bar overlaps with current bars */ ++ if (MV_TRUE == pexBarOverlapDetect(pexIf,barNum, &pAddrWin->addrWin)) ++ { ++ mvOsPrintf("mvPexBarSet: ERR. Target %d overlap\n", barNum); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Get size register value according to window size */ ++ sizeToReg = ctrlSizeToReg(pAddrWin->addrWin.size, PXBCR_BAR_SIZE_ALIGNMENT); ++ ++ /* Read bar size */ ++ if (PEX_INTER_REGS_BAR != barNum) /* internal registers have no size */ ++ { ++ regSize = MV_REG_READ(PEX_BAR_CTRL_REG(pexIf,barNum)); ++ ++ /* Size parameter validity check. */ ++ if (-1 == sizeToReg) ++ { ++ mvOsPrintf("mvPexBarSet: ERR. Target BAR %d size invalid.\n",barNum); ++ return MV_BAD_PARAM; ++ } ++ ++ regSize &= ~PXBCR_BAR_SIZE_MASK; ++ regSize |= (sizeToReg << PXBCR_BAR_SIZE_OFFS) ; ++ ++ MV_REG_WRITE(PEX_BAR_CTRL_REG(pexIf,barNum),regSize); ++ ++ } ++ ++ /* set size */ ++ ++ ++ ++ /* Read base address low */ ++ regBaseLow = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, ++ PEX_MV_BAR_BASE(barNum))); ++ ++ /* clear current base */ ++ if (PEX_INTER_REGS_BAR == barNum) ++ { ++ regBaseLow &= ~PXBIR_BASE_MASK; ++ regBaseLow |= (pAddrWin->addrWin.baseLow & PXBIR_BASE_MASK); ++ } ++ else ++ { ++ regBaseLow &= ~PXBR_BASE_MASK; ++ regBaseLow |= (pAddrWin->addrWin.baseLow & PXBR_BASE_MASK); ++ } ++ ++ /* if we had a previous value that contain the bar type (MeM\IO), we want to ++ restore it */ ++ regBaseLow |= PEX_BAR_DEFAULT_ATTRIB; ++ ++ ++ ++ /* write base low */ ++ MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE(barNum)), ++ regBaseLow); ++ ++ if (pAddrWin->addrWin.baseHigh != 0) ++ { ++ /* Read base address high */ ++ MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE_HIGH(barNum)), ++ pAddrWin->addrWin.baseHigh); ++ ++ } ++ ++ /* lastly enable the Bar */ ++ if (pAddrWin->enable == MV_TRUE) ++ { ++ if (PEX_INTER_REGS_BAR != barNum) /* internal registers ++ are enabled always */ ++ { ++ MV_REG_BIT_SET(PEX_BAR_CTRL_REG(pexIf,barNum),PXBCR_BAR_EN); ++ } ++ } ++ else if (MV_FALSE == pAddrWin->enable) ++ { ++ if (PEX_INTER_REGS_BAR != barNum) /* internal registers ++ are enabled always */ ++ { ++ MV_REG_BIT_RESET(PEX_BAR_CTRL_REG(pexIf,barNum),PXBCR_BAR_EN); ++ } ++ ++ } ++ ++ ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvPexBarGet - Get PEX bar address and size ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++ ++MV_STATUS mvPexBarGet(MV_U32 pexIf, ++ MV_U32 barNum, ++ MV_PEX_BAR *pAddrWin) ++{ ++ /* check parameters */ ++ if(pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexBarGet: ERR. Invalid PEX interface %d\n", pexIf); ++ return MV_BAD_PARAM; ++ } ++ ++ if(barNum >= PEX_MAX_BARS) ++ { ++ mvOsPrintf("mvPexBarGet: ERR. Invalid bar number %d\n", barNum); ++ return MV_BAD_PARAM; ++ } ++ ++ /* read base low */ ++ pAddrWin->addrWin.baseLow = ++ MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE(barNum))); ++ ++ ++ if (PEX_INTER_REGS_BAR == barNum) ++ { ++ pAddrWin->addrWin.baseLow &= PXBIR_BASE_MASK; ++ } ++ else ++ { ++ pAddrWin->addrWin.baseLow &= PXBR_BASE_MASK; ++ } ++ ++ ++ /* read base high */ ++ pAddrWin->addrWin.baseHigh = ++ MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_MV_BAR_BASE_HIGH(barNum))); ++ ++ ++ /* Read bar size */ ++ if (PEX_INTER_REGS_BAR != barNum) /* internal registers have no size */ ++ { ++ pAddrWin->addrWin.size = MV_REG_READ(PEX_BAR_CTRL_REG(pexIf,barNum)); ++ ++ /* check if enable or not */ ++ if (pAddrWin->addrWin.size & PXBCR_BAR_EN) ++ { ++ pAddrWin->enable = MV_TRUE; ++ } ++ else ++ { ++ pAddrWin->enable = MV_FALSE; ++ } ++ ++ /* now get the size */ ++ pAddrWin->addrWin.size &= PXBCR_BAR_SIZE_MASK; ++ pAddrWin->addrWin.size >>= PXBCR_BAR_SIZE_OFFS; ++ ++ pAddrWin->addrWin.size = ctrlRegToSize(pAddrWin->addrWin.size, ++ PXBCR_BAR_SIZE_ALIGNMENT); ++ ++ } ++ else /* PEX_INTER_REGS_BAR */ ++ { ++ pAddrWin->addrWin.size = INTER_REGS_SIZE; ++ pAddrWin->enable = MV_TRUE; ++ } ++ ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvPexBarEnable - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++ ++ ++MV_STATUS mvPexBarEnable(MV_U32 pexIf, MV_U32 barNum, MV_BOOL enable) ++{ ++ ++ MV_PEX_BAR pexBar; ++ ++ /* check parameters */ ++ if(pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexBarEnable: ERR. Invalid PEX interface %d\n", pexIf); ++ return MV_BAD_PARAM; ++ } ++ ++ ++ if(barNum >= PEX_MAX_BARS) ++ { ++ mvOsPrintf("mvPexBarEnable: ERR. Invalid bar number %d\n", barNum); ++ return MV_BAD_PARAM; ++ } ++ ++ if (PEX_INTER_REGS_BAR == barNum) ++ { ++ if (MV_TRUE == enable) ++ { ++ return MV_OK; ++ } ++ else ++ { ++ return MV_ERROR; ++ } ++ } ++ ++ ++ if (MV_FALSE == enable) ++ { ++ /* disable bar and quit */ ++ MV_REG_BIT_RESET(PEX_BAR_CTRL_REG(pexIf,barNum),PXBCR_BAR_EN); ++ return MV_OK; ++ } ++ ++ /* else */ ++ ++ if (mvPexBarGet(pexIf,barNum,&pexBar) != MV_OK) ++ { ++ mvOsPrintf("mvPexBarEnable: mvPexBarGet Failed\n"); ++ return MV_ERROR; ++ ++ } ++ ++ if (MV_TRUE == pexBar.enable) ++ { ++ /* it is already enabled !!! */ ++ return MV_OK; ++ } ++ ++ /* else enable the bar*/ ++ ++ pexBar.enable = MV_TRUE; ++ ++ if (mvPexBarSet(pexIf,barNum,&pexBar) != MV_OK) ++ { ++ mvOsPrintf("mvPexBarEnable: mvPexBarSet Failed\n"); ++ return MV_ERROR; ++ ++ } ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* pexWinOverlapDetect - Detect address windows overlapping ++* ++* DESCRIPTION: ++* This function detects address window overlapping of a given address ++* window in PEX BARs. ++* ++* INPUT: ++* pAddrWin - Address window to be checked. ++* bar - BAR to be accessed by slave. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the given address window overlap current address ++* decode map, MV_FALSE otherwise. ++* ++*******************************************************************************/ ++static MV_BOOL pexWinOverlapDetect(MV_U32 pexIf, ++ MV_U32 winNum, ++ MV_ADDR_WIN *pAddrWin) ++{ ++ MV_U32 win; ++ MV_PEX_DEC_WIN addrDecWin; ++ ++ ++ for(win = 0; win < PEX_MAX_TARGET_WIN -2 ; win++) ++ { ++ /* don't check our target or illegal targets */ ++ if (winNum == win) ++ { ++ continue; ++ } ++ ++ /* Get window parameters */ ++ if (MV_OK != mvPexTargetWinGet(pexIf, win, &addrDecWin)) ++ { ++ mvOsPrintf("pexWinOverlapDetect: ERR. TargetWinGet failed win=%x\n", ++ win); ++ return MV_ERROR; ++ } ++ ++ /* Do not check disabled windows */ ++ if (MV_FALSE == addrDecWin.enable) ++ { ++ continue; ++ } ++ ++ ++ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) ++ { ++ mvOsPrintf("pexWinOverlapDetect: winNum %d overlap current %d\n", ++ winNum, win); ++ return MV_TRUE; ++ } ++ } ++ ++ return MV_FALSE; ++} ++ ++/******************************************************************************* ++* pexIsWinWithinBar - Detect if address is within PEX bar boundries ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the given address window overlap current address ++* decode map, MV_FALSE otherwise. ++* ++*******************************************************************************/ ++static MV_BOOL pexIsWinWithinBar(MV_U32 pexIf, ++ MV_ADDR_WIN *pAddrWin) ++{ ++ MV_U32 bar; ++ MV_PEX_BAR addrDecWin; ++ ++ for(bar = 0; bar < PEX_MAX_BARS; bar++) ++ { ++ ++ /* Get window parameters */ ++ if (MV_OK != mvPexBarGet(pexIf, bar, &addrDecWin)) ++ { ++ mvOsPrintf("pexIsWinWithinBar: ERR. mvPexBarGet failed\n"); ++ return MV_ERROR; ++ } ++ ++ /* Do not check disabled bars */ ++ if (MV_FALSE == addrDecWin.enable) ++ { ++ continue; ++ } ++ ++ ++ if(MV_TRUE == ctrlWinWithinWinTest(pAddrWin, &addrDecWin.addrWin)) ++ { ++ return MV_TRUE; ++ } ++ } ++ ++ return MV_FALSE; ++ ++} ++ ++/******************************************************************************* ++* pexBarOverlapDetect - Detect address windows overlapping ++* ++* DESCRIPTION: ++* This function detects address window overlapping of a given address ++* window in PEX BARs. ++* ++* INPUT: ++* pAddrWin - Address window to be checked. ++* bar - BAR to be accessed by slave. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the given address window overlap current address ++* decode map, MV_FALSE otherwise. ++* ++*******************************************************************************/ ++static MV_BOOL pexBarOverlapDetect(MV_U32 pexIf, ++ MV_U32 barNum, ++ MV_ADDR_WIN *pAddrWin) ++{ ++ MV_U32 bar; ++ MV_PEX_BAR barDecWin; ++ ++ ++ for(bar = 0; bar < PEX_MAX_BARS; bar++) ++ { ++ /* don't check our target or illegal targets */ ++ if (barNum == bar) ++ { ++ continue; ++ } ++ ++ /* Get window parameters */ ++ if (MV_OK != mvPexBarGet(pexIf, bar, &barDecWin)) ++ { ++ mvOsPrintf("pexBarOverlapDetect: ERR. TargetWinGet failed\n"); ++ return MV_ERROR; ++ } ++ ++ /* don'nt check disabled bars */ ++ if (barDecWin.enable == MV_FALSE) ++ { ++ continue; ++ } ++ ++ ++ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &barDecWin.addrWin)) ++ { ++ mvOsPrintf("pexBarOverlapDetect: winNum %d overlap current %d\n", ++ barNum, bar); ++ return MV_TRUE; ++ } ++ } ++ ++ return MV_FALSE; ++} ++ ++/******************************************************************************* ++* pexBarIsValid - Check if the given address window is valid ++* ++* DESCRIPTION: ++* PEX spec restrict BAR base to be aligned to BAR size. ++* This function checks if the given address window is valid. ++* ++* INPUT: ++* baseLow - 32bit low base address. ++* size - Window size. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the address window is valid, MV_FALSE otherwise. ++* ++*******************************************************************************/ ++static MV_STATUS pexBarIsValid(MV_U32 baseLow, MV_U32 size) ++{ ++ ++ /* PCI spec restrict BAR base to be aligned to BAR size */ ++ if(MV_IS_NOT_ALIGN(baseLow, size)) ++ { ++ return MV_ERROR; ++ } ++ else ++ { ++ return MV_TRUE; ++ } ++ ++ return MV_TRUE; ++} ++ ++/******************************************************************************* ++* pexBarRegInfoGet - Get BAR register information ++* ++* DESCRIPTION: ++* PEX BARs registers offsets are inconsecutive. ++* This function gets a PEX BAR register information like register offsets ++* and function location of the BAR. ++* ++* INPUT: ++* pexIf - PEX interface number. ++* bar - The PEX BAR in question. ++* ++* OUTPUT: ++* pBarRegInfo - BAR register info struct. ++* ++* RETURN: ++* MV_BAD_PARAM when bad parameters ,MV_ERROR on error ,othewise MV_OK ++* ++*******************************************************************************/ ++static MV_STATUS pexWinRegInfoGet(MV_U32 pexIf, ++ MV_U32 winNum, ++ PEX_WIN_REG_INFO *pWinRegInfo) ++{ ++ ++ if ((winNum >= 0)&&(winNum <=3)) ++ { ++ pWinRegInfo->baseLowRegOffs = PEX_WIN0_3_BASE_REG(pexIf,winNum); ++ pWinRegInfo->baseHighRegOffs = 0; ++ pWinRegInfo->sizeRegOffs = PEX_WIN0_3_CTRL_REG(pexIf,winNum); ++ pWinRegInfo->remapLowRegOffs = PEX_WIN0_3_REMAP_REG(pexIf,winNum); ++ pWinRegInfo->remapHighRegOffs = 0; ++ } ++ else if ((winNum >= 4)&&(winNum <=5)) ++ { ++ pWinRegInfo->baseLowRegOffs = PEX_WIN4_5_BASE_REG(pexIf,winNum); ++ pWinRegInfo->baseHighRegOffs = 0; ++ pWinRegInfo->sizeRegOffs = PEX_WIN4_5_CTRL_REG(pexIf,winNum); ++ pWinRegInfo->remapLowRegOffs = PEX_WIN4_5_REMAP_REG(pexIf,winNum); ++ pWinRegInfo->remapHighRegOffs = PEX_WIN4_5_REMAP_HIGH_REG(pexIf,winNum); ++ ++ } ++ else if (MV_PEX_WIN_DEFAULT == winNum) ++ { ++ pWinRegInfo->baseLowRegOffs = 0; ++ pWinRegInfo->baseHighRegOffs = 0; ++ pWinRegInfo->sizeRegOffs = PEX_WIN_DEFAULT_CTRL_REG(pexIf); ++ pWinRegInfo->remapLowRegOffs = 0; ++ pWinRegInfo->remapHighRegOffs = 0; ++ } ++ else if (MV_PEX_WIN_EXP_ROM == winNum) ++ { ++ pWinRegInfo->baseLowRegOffs = 0; ++ pWinRegInfo->baseHighRegOffs = 0; ++ pWinRegInfo->sizeRegOffs = PEX_WIN_EXP_ROM_CTRL_REG(pexIf); ++ pWinRegInfo->remapLowRegOffs = PEX_WIN_EXP_ROM_REMAP_REG(pexIf); ++ pWinRegInfo->remapHighRegOffs = 0; ++ ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* pexBarNameGet - Get the string name of PEX BAR. ++* ++* DESCRIPTION: ++* This function get the string name of PEX BAR. ++* ++* INPUT: ++* bar - PEX bar number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* pointer to the string name of PEX BAR. ++* ++*******************************************************************************/ ++const MV_8* pexBarNameGet( MV_U32 bar ) ++{ ++ switch( bar ) ++ { ++ case PEX_INTER_REGS_BAR: ++ return "Internal Regs Bar0...."; ++ case PEX_DRAM_BAR: ++ return "DRAM Bar1............."; ++ case PEX_DEVICE_BAR: ++ return "Devices Bar2.........."; ++ default: ++ return "Bar unknown"; ++ } ++} ++/******************************************************************************* ++* mvPexAddrDecShow - Print the PEX address decode map (BARs and windows). ++* ++* DESCRIPTION: ++* This function print the PEX address decode map (BARs and windows). ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvPexAddrDecShow(MV_VOID) ++{ ++ MV_PEX_BAR pexBar; ++ MV_PEX_DEC_WIN win; ++ MV_U32 pexIf; ++ MV_U32 bar,winNum; ++ ++ for( pexIf = 0; pexIf < mvCtrlPexMaxIfGet(); pexIf++ ) ++ { ++ if (MV_FALSE == mvCtrlPwrClckGet(PEX_UNIT_ID, pexIf)) continue; ++ mvOsOutput( "\n" ); ++ mvOsOutput( "PEX%d:\n", pexIf ); ++ mvOsOutput( "-----\n" ); ++ ++ mvOsOutput( "\nPex Bars \n\n"); ++ ++ for( bar = 0; bar < PEX_MAX_BARS; bar++ ) ++ { ++ memset( &pexBar, 0, sizeof(MV_PEX_BAR) ); ++ ++ mvOsOutput( "%s ", pexBarNameGet(bar) ); ++ ++ if( mvPexBarGet( pexIf, bar, &pexBar ) == MV_OK ) ++ { ++ if( pexBar.enable ) ++ { ++ mvOsOutput( "base %08x, ", pexBar.addrWin.baseLow ); ++ mvSizePrint( pexBar.addrWin.size ); ++ mvOsOutput( "\n" ); ++ } ++ else ++ mvOsOutput( "disable\n" ); ++ } ++ } ++ mvOsOutput( "\nPex Decode Windows\n\n"); ++ ++ for( winNum = 0; winNum < PEX_MAX_TARGET_WIN - 2; winNum++) ++ { ++ memset( &win, 0,sizeof(MV_PEX_DEC_WIN) ); ++ ++ mvOsOutput( "win%d - ", winNum ); ++ ++ if ( mvPexTargetWinGet(pexIf,winNum,&win) == MV_OK) ++ { ++ if (win.enable) ++ { ++ mvOsOutput( "%s base %08x, ", ++ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); ++ mvOsOutput( "...." ); ++ mvSizePrint( win.addrWin.size ); ++ ++ mvOsOutput( "\n" ); ++ } ++ else ++ mvOsOutput( "disable\n" ); ++ ++ ++ } ++ } ++ ++ memset( &win, 0,sizeof(MV_PEX_DEC_WIN) ); ++ ++ mvOsOutput( "default win - " ); ++ ++ if ( mvPexTargetWinGet(pexIf, MV_PEX_WIN_DEFAULT, &win) == MV_OK) ++ { ++ mvOsOutput( "%s ", ++ mvCtrlTargetNameGet(win.target) ); ++ mvOsOutput( "\n" ); ++ } ++ memset( &win, 0,sizeof(MV_PEX_DEC_WIN) ); ++ ++ mvOsOutput( "Expansion ROM - " ); ++ ++ if ( mvPexTargetWinGet(pexIf, MV_PEX_WIN_EXP_ROM, &win) == MV_OK) ++ { ++ mvOsOutput( "%s ", ++ mvCtrlTargetNameGet(win.target) ); ++ mvOsOutput( "\n" ); ++ } ++ ++ } ++} ++ ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysPex.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,348 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCSysPEXH ++#define __INCSysPEXH ++ ++#include "mvCommon.h" ++#include "ctrlEnv/sys/mvCpuIf.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "ctrlEnv/mvCtrlEnvAddrDec.h" ++ ++/* 4KB granularity */ ++#define MINIMUM_WINDOW_SIZE 0x1000 ++#define MINIMUM_BAR_SIZE 0x1000 ++#define MINIMUM_BAR_SIZE_MASK 0xFFFFF000 ++#define BAR_SIZE_OFFS 12 ++#define BAR_SIZE_MASK (0xFFFFF << BAR_SIZE_OFFS) ++ ++ ++ ++#define MV_PEX_WIN_DEFAULT 6 ++#define MV_PEX_WIN_EXP_ROM 7 ++#define PEX_MAX_TARGET_WIN 8 ++ ++ ++#define PEX_MAX_BARS 3 ++#define PEX_INTER_REGS_BAR 0 ++#define PEX_DRAM_BAR 1 ++#define PEX_DEVICE_BAR 2 ++ ++/*************************************/ ++/* PCI Express BAR Control Registers */ ++/*************************************/ ++#define PEX_BAR_CTRL_REG(pexIf,bar) (0x41804 + (bar-1)*4- (pexIf)*0x10000) ++#define PEX_EXP_ROM_BAR_CTRL_REG(pexIf) (0x4180C - (pexIf)*0x10000) ++ ++ ++/* PCI Express BAR Control Register */ ++/* PEX_BAR_CTRL_REG (PXBCR) */ ++ ++#define PXBCR_BAR_EN BIT0 ++#define PXBCR_BAR_SIZE_OFFS 16 ++#define PXBCR_BAR_SIZE_MASK (0xffff << PXBCR_BAR_SIZE_OFFS) ++#define PXBCR_BAR_SIZE_ALIGNMENT 0x10000 ++ ++ ++ ++/* PCI Express Expansion ROM BAR Control Register */ ++/* PEX_EXP_ROM_BAR_CTRL_REG (PXERBCR) */ ++ ++#define PXERBCR_EXPROM_EN BIT0 ++#define PXERBCR_EXPROMSZ_OFFS 19 ++#define PXERBCR_EXPROMSZ_MASK (0xf << PXERBCR_EXPROMSZ_OFFS) ++#define PXERBCR_EXPROMSZ_512KB (0x0 << PXERBCR_EXPROMSZ_OFFS) ++#define PXERBCR_EXPROMSZ_1024KB (0x1 << PXERBCR_EXPROMSZ_OFFS) ++#define PXERBCR_EXPROMSZ_2048KB (0x3 << PXERBCR_EXPROMSZ_OFFS) ++#define PXERBCR_EXPROMSZ_4096KB (0x7 << PXERBCR_EXPROMSZ_OFFS) ++ ++/************************************************/ ++/* PCI Express Address Window Control Registers */ ++/************************************************/ ++#define PEX_WIN0_3_CTRL_REG(pexIf,winNum) \ ++ (0x41820 + (winNum) * 0x10 - (pexIf) * 0x10000) ++#define PEX_WIN0_3_BASE_REG(pexIf,winNum) \ ++ (0x41824 + (winNum) * 0x10 - (pexIf) * 0x10000) ++#define PEX_WIN0_3_REMAP_REG(pexIf,winNum) \ ++ (0x4182C + (winNum) * 0x10 - (pexIf) * 0x10000) ++#define PEX_WIN4_5_CTRL_REG(pexIf,winNum) \ ++ (0x41860 + (winNum - 4) * 0x20 - (pexIf) * 0x10000) ++#define PEX_WIN4_5_BASE_REG(pexIf,winNum) \ ++ (0x41864 + (winNum - 4) * 0x20 - (pexIf) * 0x10000) ++#define PEX_WIN4_5_REMAP_REG(pexIf,winNum) \ ++ (0x4186C + (winNum - 4) * 0x20 - (pexIf) * 0x10000) ++#define PEX_WIN4_5_REMAP_HIGH_REG(pexIf,winNum) \ ++ (0x41870 + (winNum - 4) * 0x20 - (pexIf) * 0x10000) ++ ++#define PEX_WIN_DEFAULT_CTRL_REG(pexIf) (0x418B0 - (pexIf) * 0x10000) ++#define PEX_WIN_EXP_ROM_CTRL_REG(pexIf) (0x418C0 - (pexIf) * 0x10000) ++#define PEX_WIN_EXP_ROM_REMAP_REG(pexIf) (0x418C4 - (pexIf) * 0x10000) ++ ++/* PCI Express Window Control Register */ ++/* PEX_WIN_CTRL_REG (PXWCR) */ ++ ++#define PXWCR_WIN_EN BIT0 /* Window Enable.*/ ++ ++#define PXWCR_WIN_BAR_MAP_OFFS 1 /* Mapping to BAR.*/ ++#define PXWCR_WIN_BAR_MAP_MASK BIT1 ++#define PXWCR_WIN_BAR_MAP_BAR1 (0 << PXWCR_WIN_BAR_MAP_OFFS) ++#define PXWCR_WIN_BAR_MAP_BAR2 (1 << PXWCR_WIN_BAR_MAP_OFFS) ++ ++#define PXWCR_TARGET_OFFS 4 /*Unit ID */ ++#define PXWCR_TARGET_MASK (0xf << PXWCR_TARGET_OFFS) ++ ++#define PXWCR_ATTRIB_OFFS 8 /* target attributes */ ++#define PXWCR_ATTRIB_MASK (0xff << PXWCR_ATTRIB_OFFS) ++ ++#define PXWCR_SIZE_OFFS 16 /* size */ ++#define PXWCR_SIZE_MASK (0xffff << PXWCR_SIZE_OFFS) ++#define PXWCR_SIZE_ALIGNMENT 0x10000 ++ ++/* PCI Express Window Base Register */ ++/* PEX_WIN_BASE_REG (PXWBR)*/ ++ ++#define PXWBR_BASE_OFFS 16 /* address[31:16] */ ++#define PXWBR_BASE_MASK (0xffff << PXWBR_BASE_OFFS) ++#define PXWBR_BASE_ALIGNMENT 0x10000 ++ ++/* PCI Express Window Remap Register */ ++/* PEX_WIN_REMAP_REG (PXWRR)*/ ++ ++#define PXWRR_REMAP_EN BIT0 ++#define PXWRR_REMAP_OFFS 16 ++#define PXWRR_REMAP_MASK (0xffff << PXWRR_REMAP_OFFS) ++#define PXWRR_REMAP_ALIGNMENT 0x10000 ++ ++/* PCI Express Window Remap (High) Register */ ++/* PEX_WIN_REMAP_HIGH_REG (PXWRHR)*/ ++ ++#define PXWRHR_REMAP_HIGH_OFFS 0 ++#define PXWRHR_REMAP_HIGH_MASK (0xffffffff << PXWRHR_REMAP_HIGH_OFFS) ++ ++/* PCI Express Default Window Control Register */ ++/* PEX_WIN_DEFAULT_CTRL_REG (PXWDCR) */ ++ ++#define PXWDCR_TARGET_OFFS 4 /*Unit ID */ ++#define PXWDCR_TARGET_MASK (0xf << PXWDCR_TARGET_OFFS) ++#define PXWDCR_ATTRIB_OFFS 8 /* target attributes */ ++#define PXWDCR_ATTRIB_MASK (0xff << PXWDCR_ATTRIB_OFFS) ++ ++/* PCI Express Expansion ROM Window Control Register */ ++/* PEX_WIN_EXP_ROM_CTRL_REG (PXWERCR)*/ ++ ++#define PXWERCR_TARGET_OFFS 4 /*Unit ID */ ++#define PXWERCR_TARGET_MASK (0xf << PXWERCR_TARGET_OFFS) ++#define PXWERCR_ATTRIB_OFFS 8 /* target attributes */ ++#define PXWERCR_ATTRIB_MASK (0xff << PXWERCR_ATTRIB_OFFS) ++ ++/* PCI Express Expansion ROM Window Remap Register */ ++/* PEX_WIN_EXP_ROM_REMAP_REG (PXWERRR)*/ ++ ++#define PXWERRR_REMAP_EN BIT0 ++#define PXWERRR_REMAP_OFFS 16 ++#define PXWERRR_REMAP_MASK (0xffff << PXWERRR_REMAP_OFFS) ++#define PXWERRR_REMAP_ALIGNMENT 0x10000 ++ ++ ++ ++/*PEX_MEMORY_BAR_BASE_ADDR(barNum) (PXMBBA)*/ ++/* PCI Express BAR0 Internal Register*/ ++/*PEX BAR0_INTER_REG (PXBIR)*/ ++ ++#define PXBIR_IOSPACE BIT0 /* Memory Space Indicator */ ++ ++#define PXBIR_TYPE_OFFS 1 /* BAR Type/Init Val. */ ++#define PXBIR_TYPE_MASK (0x3 << PXBIR_TYPE_OFFS) ++#define PXBIR_TYPE_32BIT_ADDR (0x0 << PXBIR_TYPE_OFFS) ++#define PXBIR_TYPE_64BIT_ADDR (0x2 << PXBIR_TYPE_OFFS) ++ ++#define PXBIR_PREFETCH_EN BIT3 /* Prefetch Enable */ ++ ++#define PXBIR_BASE_OFFS 20 /* Base address. Address bits [31:20] */ ++#define PXBIR_BASE_MASK (0xfff << PXBIR_BASE_OFFS) ++#define PXBIR_BASE_ALIGNMET (1 << PXBIR_BASE_OFFS) ++ ++ ++/* PCI Express BAR0 Internal (High) Register*/ ++/*PEX BAR0_INTER_REG_HIGH (PXBIRH)*/ ++ ++#define PXBIRH_BASE_OFFS 0 /* Base address. Bits [63:32] */ ++#define PXBIRH_BASE_MASK (0xffffffff << PBBHR_BASE_OFFS) ++ ++ ++#define PEX_BAR_DEFAULT_ATTRIB 0xc /* Memory - Prefetch - 64 bit address */ ++#define PEX_BAR0_DEFAULT_ATTRIB PEX_BAR_DEFAULT_ATTRIB ++#define PEX_BAR1_DEFAULT_ATTRIB PEX_BAR_DEFAULT_ATTRIB ++#define PEX_BAR2_DEFAULT_ATTRIB PEX_BAR_DEFAULT_ATTRIB ++ ++ ++/* PCI Express BAR1 Register */ ++/* PCI Express BAR2 Register*/ ++/*PEX BAR1_REG (PXBR)*/ ++/*PEX BAR2_REG (PXBR)*/ ++ ++#define PXBR_IOSPACE BIT0 /* Memory Space Indicator */ ++ ++#define PXBR_TYPE_OFFS 1 /* BAR Type/Init Val. */ ++#define PXBR_TYPE_MASK (0x3 << PXBR_TYPE_OFFS) ++#define PXBR_TYPE_32BIT_ADDR (0x0 << PXBR_TYPE_OFFS) ++#define PXBR_TYPE_64BIT_ADDR (0x2 << PXBR_TYPE_OFFS) ++ ++#define PXBR_PREFETCH_EN BIT3 /* Prefetch Enable */ ++ ++#define PXBR_BASE_OFFS 16 /* Base address. Address bits [31:16] */ ++#define PXBR_BASE_MASK (0xffff << PXBR_BASE_OFFS) ++#define PXBR_BASE_ALIGNMET (1 << PXBR_BASE_OFFS) ++ ++ ++/* PCI Express BAR1 (High) Register*/ ++/* PCI Express BAR2 (High) Register*/ ++/*PEX BAR1_REG_HIGH (PXBRH)*/ ++/*PEX BAR2_REG_HIGH (PXBRH)*/ ++ ++#define PXBRH_BASE_OFFS 0 /* Base address. Address bits [63:32] */ ++#define PXBRH_BASE_MASK (0xffffffff << PXBRH_BASE_OFFS) ++ ++/* PCI Express Expansion ROM BAR Register*/ ++/*PEX_EXPANSION_ROM_BASE_ADDR_REG (PXERBAR)*/ ++ ++#define PXERBAR_EXPROMEN BIT0 /* Expansion ROM Enable */ ++ ++#define PXERBAR_BASE_512K_OFFS 19 /* Expansion ROM Base Address */ ++#define PXERBAR_BASE_512K_MASK (0x1fff << PXERBAR_BASE_512K_OFFS) ++ ++#define PXERBAR_BASE_1MB_OFFS 20 /* Expansion ROM Base Address */ ++#define PXERBAR_BASE_1MB_MASK (0xfff << PXERBAR_BASE_1MB_OFFS) ++ ++#define PXERBAR_BASE_2MB_OFFS 21 /* Expansion ROM Base Address */ ++#define PXERBAR_BASE_2MB_MASK (0x7ff << PXERBAR_BASE_2MB_OFFS) ++ ++#define PXERBAR_BASE_4MB_OFFS 22 /* Expansion ROM Base Address */ ++#define PXERBAR_BASE_4MB_MASK (0x3ff << PXERBAR_BASE_4MB_OFFS) ++ ++/* PEX Bar attributes */ ++typedef struct _mvPexBar ++{ ++ MV_ADDR_WIN addrWin; /* An address window*/ ++ MV_BOOL enable; /* Address decode window is enabled/disabled */ ++ ++}MV_PEX_BAR; ++ ++/* PEX Remap Window attributes */ ++typedef struct _mvPexRemapWin ++{ ++ MV_ADDR_WIN addrWin; /* An address window*/ ++ MV_BOOL enable; /* Address decode window is enabled/disabled */ ++ ++}MV_PEX_REMAP_WIN; ++ ++/* PEX Remap Window attributes */ ++typedef struct _mvPexDecWin ++{ ++ MV_TARGET target; ++ MV_ADDR_WIN addrWin; /* An address window*/ ++ MV_U32 targetBar; ++ MV_U8 attrib; /* chip select attributes */ ++ MV_TARGET_ID targetId; /* Target Id of this MV_TARGET */ ++ MV_BOOL enable; /* Address decode window is enabled/disabled */ ++ ++}MV_PEX_DEC_WIN; ++ ++/* Global Functions prototypes */ ++/* mvPexHalInit - Initialize PEX interfaces*/ ++MV_STATUS mvPexInit(MV_U32 pexIf, MV_PEX_TYPE pexType); ++ ++ ++/* mvPexTargetWinSet - Set PEX to peripheral target address window BAR*/ ++MV_STATUS mvPexTargetWinSet(MV_U32 pexIf, MV_U32 winNum, ++ MV_PEX_DEC_WIN *pAddrDecWin); ++ ++/* mvPexTargetWinGet - Get PEX to peripheral target address window*/ ++MV_STATUS mvPexTargetWinGet(MV_U32 pexIf, MV_U32 winNum, ++ MV_PEX_DEC_WIN *pAddrDecWin); ++ ++/* mvPexTargetWinEnable - Enable/disable a PEX BAR window*/ ++MV_STATUS mvPexTargetWinEnable(MV_U32 pexIf,MV_U32 winNum, MV_BOOL enable); ++ ++/* mvPexTargetWinRemap - Set PEX to target address window remap.*/ ++MV_STATUS mvPexTargetWinRemap(MV_U32 pexIf, MV_U32 winNum, ++ MV_PEX_REMAP_WIN *pAddrWin); ++ ++/* mvPexTargetWinRemapEnable -enable\disable a PEX Window remap.*/ ++MV_STATUS mvPexTargetWinRemapEnable(MV_U32 pexIf, MV_U32 winNum, ++ MV_BOOL enable); ++ ++/* mvPexBarSet - Set PEX bar address and size */ ++MV_STATUS mvPexBarSet(MV_U32 pexIf, MV_U32 barNum, MV_PEX_BAR *addrWin); ++ ++/* mvPexBarGet - Get PEX bar address and size */ ++MV_STATUS mvPexBarGet(MV_U32 pexIf, MV_U32 barNum, MV_PEX_BAR *addrWin); ++ ++/* mvPexBarEnable - enable\disable a PEX bar*/ ++MV_STATUS mvPexBarEnable(MV_U32 pexIf, MV_U32 barNum, MV_BOOL enable); ++ ++/* mvPexAddrDecShow - Display address decode windows attributes */ ++MV_VOID mvPexAddrDecShow(MV_VOID); ++ ++#endif +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.c linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.c +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,430 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#include "mvTypes.h" ++#include "mvCommon.h" ++#include "mvOs.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "cpu/mvCpu.h" ++#include "ctrlEnv/sys/mvCpuIf.h" ++#include "sata/CoreDriver/mvRegs.h" ++#include "ctrlEnv/sys/mvSysSata.h" ++ ++MV_TARGET sataAddrDecPrioTab[] = ++{ ++#if defined(MV_INCLUDE_SDRAM_CS0) ++ SDRAM_CS0, ++#endif ++#if defined(MV_INCLUDE_SDRAM_CS1) ++ SDRAM_CS1, ++#endif ++#if defined(MV_INCLUDE_SDRAM_CS2) ++ SDRAM_CS2, ++#endif ++#if defined(MV_INCLUDE_SDRAM_CS3) ++ SDRAM_CS3, ++#endif ++#if defined(MV_INCLUDE_PEX) ++ PEX0_MEM, ++#endif ++ TBL_TERM ++}; ++ ++ ++/******************************************************************************* ++* sataWinOverlapDetect - Detect SATA address windows overlapping ++* ++* DESCRIPTION: ++* An unpredicted behaviur is expected in case SATA address decode ++* windows overlapps. ++* This function detects SATA address decode windows overlapping of a ++* specified window. The function does not check the window itself for ++* overlapping. The function also skipps disabled address decode windows. ++* ++* INPUT: ++* winNum - address decode window number. ++* pAddrDecWin - An address decode window struct. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the given address window overlap current address ++* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data ++* from registers. ++* ++*******************************************************************************/ ++static MV_STATUS sataWinOverlapDetect(int dev, MV_U32 winNum, ++ MV_ADDR_WIN *pAddrWin) ++{ ++ MV_U32 winNumIndex; ++ MV_SATA_DEC_WIN addrDecWin; ++ ++ for(winNumIndex=0; winNumIndex= MV_SATA_MAX_ADDR_DECODE_WIN) ++ { ++ mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check if the requested window overlapps with current windows */ ++ if (MV_TRUE == sataWinOverlapDetect(dev, winNum, &pAddrDecWin->addrWin)) ++ { ++ mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); ++ return MV_ERROR; ++ } ++ ++ /* check if address is aligned to the size */ ++ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) ++ { ++ mvOsPrintf("mvSataWinSet:Error setting SATA window %d to "\ ++ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", ++ winNum, ++ mvCtrlTargetNameGet(pAddrDecWin->target), ++ pAddrDecWin->addrWin.baseLow, ++ pAddrDecWin->addrWin.size); ++ return MV_ERROR; ++ } ++ ++ decRegs.baseReg = 0; ++ decRegs.sizeReg = 0; ++ ++ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) ++ { ++ mvOsPrintf("%s: mvCtrlAddrDecToReg Failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); ++ ++ /* set attributes */ ++ decRegs.sizeReg &= ~MV_SATA_WIN_ATTR_MASK; ++ decRegs.sizeReg |= (targetAttribs.attrib << MV_SATA_WIN_ATTR_OFFSET); ++ ++ /* set target ID */ ++ decRegs.sizeReg &= ~MV_SATA_WIN_TARGET_MASK; ++ decRegs.sizeReg |= (targetAttribs.targetId << MV_SATA_WIN_TARGET_OFFSET); ++ ++ if (pAddrDecWin->enable == MV_TRUE) ++ { ++ decRegs.sizeReg |= MV_SATA_WIN_ENABLE_MASK; ++ } ++ else ++ { ++ decRegs.sizeReg &= ~MV_SATA_WIN_ENABLE_MASK; ++ } ++ ++ MV_REG_WRITE( MV_SATA_WIN_CTRL_REG(dev, winNum), decRegs.sizeReg); ++ MV_REG_WRITE( MV_SATA_WIN_BASE_REG(dev, winNum), decRegs.baseReg); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvSataWinGet - Get SATA peripheral target address window. ++* ++* DESCRIPTION: ++* Get SATA peripheral target address window. ++* ++* INPUT: ++* winNum - SATA target address decode window number. ++* ++* OUTPUT: ++* pAddrDecWin - SATA target window data structure. ++* ++* RETURN: ++* MV_ERROR if register parameters are invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvSataWinGet(int dev, MV_U32 winNum, MV_SATA_DEC_WIN *pAddrDecWin) ++{ ++ MV_DEC_REGS decRegs; ++ MV_TARGET_ATTRIB targetAttrib; ++ ++ /* Parameter checking */ ++ if (winNum >= MV_SATA_MAX_ADDR_DECODE_WIN) ++ { ++ mvOsPrintf("%s (dev=%d): ERR. Invalid winNum %d\n", ++ __FUNCTION__, dev, winNum); ++ return MV_NOT_SUPPORTED; ++ } ++ ++ decRegs.baseReg = MV_REG_READ( MV_SATA_WIN_BASE_REG(dev, winNum) ); ++ decRegs.sizeReg = MV_REG_READ( MV_SATA_WIN_CTRL_REG(dev, winNum) ); ++ ++ if (MV_OK != mvCtrlRegToAddrDec(&decRegs, &pAddrDecWin->addrWin) ) ++ { ++ mvOsPrintf("%s: mvCtrlRegToAddrDec Failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ /* attrib and targetId */ ++ targetAttrib.attrib = (decRegs.sizeReg & MV_SATA_WIN_ATTR_MASK) >> ++ MV_SATA_WIN_ATTR_OFFSET; ++ targetAttrib.targetId = (decRegs.sizeReg & MV_SATA_WIN_TARGET_MASK) >> ++ MV_SATA_WIN_TARGET_OFFSET; ++ ++ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); ++ ++ /* Check if window is enabled */ ++ if(decRegs.sizeReg & MV_SATA_WIN_ENABLE_MASK) ++ { ++ pAddrDecWin->enable = MV_TRUE; ++ } ++ else ++ { ++ pAddrDecWin->enable = MV_FALSE; ++ } ++ return MV_OK; ++} ++/******************************************************************************* ++* mvSataAddrDecShow - Print the SATA address decode map. ++* ++* DESCRIPTION: ++* This function print the SATA address decode map. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvSataAddrDecShow(MV_VOID) ++{ ++ ++ MV_SATA_DEC_WIN win; ++ int i,j; ++ ++ ++ ++ for( j = 0; j < MV_SATA_MAX_CHAN; j++ ) ++ { ++ if (MV_FALSE == mvCtrlPwrClckGet(SATA_UNIT_ID, j)) ++ return; ++ ++ mvOsOutput( "\n" ); ++ mvOsOutput( "SATA %d:\n", j ); ++ mvOsOutput( "----\n" ); ++ ++ for( i = 0; i < MV_SATA_MAX_ADDR_DECODE_WIN; i++ ) ++ { ++ memset( &win, 0, sizeof(MV_SATA_DEC_WIN) ); ++ ++ mvOsOutput( "win%d - ", i ); ++ ++ if( mvSataWinGet(j, i, &win ) == MV_OK ) ++ { ++ if( win.enable ) ++ { ++ mvOsOutput( "%s base %08x, ", ++ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); ++ mvOsOutput( "...." ); ++ ++ mvSizePrint( win.addrWin.size ); ++ ++ mvOsOutput( "\n" ); ++ } ++ else ++ mvOsOutput( "disable\n" ); ++ } ++ } ++ } ++} ++ ++ ++/******************************************************************************* ++* mvSataWinInit - Initialize the integrated SATA target address window. ++* ++* DESCRIPTION: ++* Initialize the SATA peripheral target address window. ++* ++* INPUT: ++* ++* ++* OUTPUT: ++* ++* ++* RETURN: ++* MV_ERROR if register parameters are invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvSataWinInit(MV_VOID) ++{ ++ int winNum; ++ MV_SATA_DEC_WIN sataWin; ++ MV_CPU_DEC_WIN cpuAddrDecWin; ++ MV_U32 status, winPrioIndex = 0; ++ ++ /* Initiate Sata address decode */ ++ ++ /* First disable all address decode windows */ ++ for(winNum = 0; winNum < MV_SATA_MAX_ADDR_DECODE_WIN; winNum++) ++ { ++ MV_U32 regVal = MV_REG_READ(MV_SATA_WIN_CTRL_REG(0, winNum)); ++ regVal &= ~MV_SATA_WIN_ENABLE_MASK; ++ MV_REG_WRITE(MV_SATA_WIN_CTRL_REG(0, winNum), regVal); ++ } ++ ++ winNum = 0; ++ while( (sataAddrDecPrioTab[winPrioIndex] != TBL_TERM) && ++ (winNum < MV_SATA_MAX_ADDR_DECODE_WIN) ) ++ { ++ /* first get attributes from CPU If */ ++ status = mvCpuIfTargetWinGet(sataAddrDecPrioTab[winPrioIndex], ++ &cpuAddrDecWin); ++ ++ if(MV_NO_SUCH == status) ++ { ++ winPrioIndex++; ++ continue; ++ } ++ if (MV_OK != status) ++ { ++ mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ if (cpuAddrDecWin.enable == MV_TRUE) ++ { ++ sataWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; ++ sataWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; ++ sataWin.addrWin.size = cpuAddrDecWin.addrWin.size; ++ sataWin.enable = MV_TRUE; ++ sataWin.target = sataAddrDecPrioTab[winPrioIndex]; ++ ++ if(MV_OK != mvSataWinSet(0/*dev*/, winNum, &sataWin)) ++ { ++ return MV_ERROR; ++ } ++ winNum++; ++ } ++ winPrioIndex++; ++ } ++ return MV_OK; ++} ++ ++ ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSata.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,128 @@ ++ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++#ifndef __INCMVSysSataAddrDech ++#define __INCMVSysSataAddrDech ++ ++#include "mvCommon.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "ctrlEnv/sys/mvCpuIf.h" ++ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++typedef struct _mvSataDecWin ++{ ++ MV_TARGET target; ++ MV_ADDR_WIN addrWin; /* An address window*/ ++ MV_BOOL enable; /* Address decode window is enabled/disabled */ ++ ++} MV_SATA_DEC_WIN; ++ ++ ++#define MV_SATA_MAX_ADDR_DECODE_WIN 4 ++ ++#define MV_SATA_WIN_CTRL_REG(dev, win) (SATA_REG_BASE + 0x30 + ((win)<<4)) ++#define MV_SATA_WIN_BASE_REG(dev, win) (SATA_REG_BASE + 0x34 + ((win)<<4)) ++ ++/* BITs in Bridge Interrupt Cause and Mask registers */ ++#define MV_SATA_ADDR_DECODE_ERROR_BIT 0 ++#define MV_SATA_ADDR_DECODE_ERROR_MASK (1<= MV_SDMMC_MAX_ADDR_DECODE_WIN) ++ { ++ mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check if the requested window overlapps with current windows */ ++ if (MV_TRUE == sdmmcWinOverlapDetect(dev, winNum, &pAddrDecWin->addrWin)) ++ { ++ mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); ++ return MV_ERROR; ++ } ++ ++ /* check if address is aligned to the size */ ++ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) ++ { ++ mvOsPrintf("mvSdmmcWinSet:Error setting SDMMC window %d to "\ ++ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", ++ winNum, ++ mvCtrlTargetNameGet(pAddrDecWin->target), ++ pAddrDecWin->addrWin.baseLow, ++ pAddrDecWin->addrWin.size); ++ return MV_ERROR; ++ } ++ ++ decRegs.baseReg = 0; ++ decRegs.sizeReg = 0; ++ ++ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) ++ { ++ mvOsPrintf("%s: mvCtrlAddrDecToReg Failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); ++ ++ /* set attributes */ ++ decRegs.sizeReg &= ~MV_SDMMC_WIN_ATTR_MASK; ++ decRegs.sizeReg |= (targetAttribs.attrib << MV_SDMMC_WIN_ATTR_OFFSET); ++ ++ /* set target ID */ ++ decRegs.sizeReg &= ~MV_SDMMC_WIN_TARGET_MASK; ++ decRegs.sizeReg |= (targetAttribs.targetId << MV_SDMMC_WIN_TARGET_OFFSET); ++ ++ if (pAddrDecWin->enable == MV_TRUE) ++ { ++ decRegs.sizeReg |= MV_SDMMC_WIN_ENABLE_MASK; ++ } ++ else ++ { ++ decRegs.sizeReg &= ~MV_SDMMC_WIN_ENABLE_MASK; ++ } ++ ++ MV_REG_WRITE( MV_SDMMC_WIN_CTRL_REG(dev, winNum), decRegs.sizeReg); ++ MV_REG_WRITE( MV_SDMMC_WIN_BASE_REG(dev, winNum), decRegs.baseReg); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvSdmmcWinGet - Get SDMMC peripheral target address window. ++* ++* DESCRIPTION: ++* Get SDMMC peripheral target address window. ++* ++* INPUT: ++* winNum - SDMMC target address decode window number. ++*d ++* OUTPUT: ++* pAddrDecWin - SDMMC target window data structure. ++* ++* RETURN: ++* MV_ERROR if register parameters are invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvSdmmcWinGet(int dev, MV_U32 winNum, MV_SDMMC_DEC_WIN *pAddrDecWin) ++{ ++ MV_DEC_REGS decRegs; ++ MV_TARGET_ATTRIB targetAttrib; ++ ++ /* Parameter checking */ ++ if (winNum >= MV_SDMMC_MAX_ADDR_DECODE_WIN) ++ { ++ mvOsPrintf("%s (dev=%d): ERR. Invalid winNum %d\n", ++ __FUNCTION__, dev, winNum); ++ return MV_NOT_SUPPORTED; ++ } ++ ++ decRegs.baseReg = MV_REG_READ( MV_SDMMC_WIN_BASE_REG(dev, winNum) ); ++ decRegs.sizeReg = MV_REG_READ( MV_SDMMC_WIN_CTRL_REG(dev, winNum) ); ++ ++ if (MV_OK != mvCtrlRegToAddrDec(&decRegs, &pAddrDecWin->addrWin) ) ++ { ++ mvOsPrintf("%s: mvCtrlRegToAddrDec Failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ /* attrib and targetId */ ++ targetAttrib.attrib = (decRegs.sizeReg & MV_SDMMC_WIN_ATTR_MASK) >> ++ MV_SDMMC_WIN_ATTR_OFFSET; ++ targetAttrib.targetId = (decRegs.sizeReg & MV_SDMMC_WIN_TARGET_MASK) >> ++ MV_SDMMC_WIN_TARGET_OFFSET; ++ ++ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); ++ ++ /* Check if window is enabled */ ++ if(decRegs.sizeReg & MV_SDMMC_WIN_ENABLE_MASK) ++ { ++ pAddrDecWin->enable = MV_TRUE; ++ } ++ else ++ { ++ pAddrDecWin->enable = MV_FALSE; ++ } ++ return MV_OK; ++} ++/******************************************************************************* ++* mvSdmmcAddrDecShow - Print the SDMMC address decode map. ++* ++* DESCRIPTION: ++* This function print the SDMMC address decode map. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvSdmmcAddrDecShow(MV_VOID) ++{ ++ ++ MV_SDMMC_DEC_WIN win; ++ int i,j=0; ++ ++ ++ ++ if (MV_FALSE == mvCtrlPwrClckGet(SDIO_UNIT_ID, 0)) ++ return; ++ ++ mvOsOutput( "\n" ); ++ mvOsOutput( "SDMMC %d:\n", j ); ++ mvOsOutput( "----\n" ); ++ ++ for( i = 0; i < MV_SDMMC_MAX_ADDR_DECODE_WIN; i++ ) ++ { ++ memset( &win, 0, sizeof(MV_SDMMC_DEC_WIN) ); ++ ++ mvOsOutput( "win%d - ", i ); ++ ++ if( mvSdmmcWinGet(j, i, &win ) == MV_OK ) ++ { ++ if( win.enable ) ++ { ++ mvOsOutput( "%s base %08x, ", ++ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); ++ mvOsOutput( "...." ); ++ ++ mvSizePrint( win.addrWin.size ); ++ ++ mvOsOutput( "\n" ); ++ } ++ else ++ mvOsOutput( "disable\n" ); ++ } ++ } ++} ++ ++ ++/******************************************************************************* ++* mvSdmmcWinInit - Initialize the integrated SDMMC target address window. ++* ++* DESCRIPTION: ++* Initialize the SDMMC peripheral target address window. ++* ++* INPUT: ++* ++* ++* OUTPUT: ++* ++* ++* RETURN: ++* MV_ERROR if register parameters are invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvSdmmcWinInit(MV_VOID) ++{ ++ int winNum; ++ MV_SDMMC_DEC_WIN sdmmcWin; ++ MV_CPU_DEC_WIN cpuAddrDecWin; ++ MV_U32 status, winPrioIndex = 0; ++ ++ /* Initiate Sdmmc address decode */ ++ ++ /* First disable all address decode windows */ ++ for(winNum = 0; winNum < MV_SDMMC_MAX_ADDR_DECODE_WIN; winNum++) ++ { ++ MV_U32 regVal = MV_REG_READ(MV_SDMMC_WIN_CTRL_REG(0, winNum)); ++ regVal &= ~MV_SDMMC_WIN_ENABLE_MASK; ++ MV_REG_WRITE(MV_SDMMC_WIN_CTRL_REG(0, winNum), regVal); ++ } ++ ++ winNum = 0; ++ while( (sdmmcAddrDecPrioTab[winPrioIndex] != TBL_TERM) && ++ (winNum < MV_SDMMC_MAX_ADDR_DECODE_WIN) ) ++ { ++ /* first get attributes from CPU If */ ++ status = mvCpuIfTargetWinGet(sdmmcAddrDecPrioTab[winPrioIndex], ++ &cpuAddrDecWin); ++ ++ if(MV_NO_SUCH == status) ++ { ++ winPrioIndex++; ++ continue; ++ } ++ if (MV_OK != status) ++ { ++ mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ if (cpuAddrDecWin.enable == MV_TRUE) ++ { ++ sdmmcWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; ++ sdmmcWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; ++ sdmmcWin.addrWin.size = cpuAddrDecWin.addrWin.size; ++ sdmmcWin.enable = MV_TRUE; ++ sdmmcWin.target = sdmmcAddrDecPrioTab[winPrioIndex]; ++ ++ if(MV_OK != mvSdmmcWinSet(0/*dev*/, winNum, &sdmmcWin)) ++ { ++ return MV_ERROR; ++ } ++ winNum++; ++ } ++ winPrioIndex++; ++ } ++ return MV_OK; ++} ++ ++ ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysSdmmc.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,125 @@ ++ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++#ifndef __INCMVSysSdmmcAddrDech ++#define __INCMVSysSdmmcAddrDech ++ ++#include "mvCommon.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "ctrlEnv/sys/mvCpuIf.h" ++ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++typedef struct _mvSdmmcDecWin ++{ ++ MV_TARGET target; ++ MV_ADDR_WIN addrWin; /* An address window*/ ++ MV_BOOL enable; /* Address decode window is enabled/disabled */ ++ ++} MV_SDMMC_DEC_WIN; ++ ++ ++#define MV_SDMMC_MAX_ADDR_DECODE_WIN 4 ++ ++#define MV_SDMMC_WIN_CTRL_REG(dev, win) (MV_SDIO_REG_BASE + 0x108 + ((win)<<3)) ++#define MV_SDMMC_WIN_BASE_REG(dev, win) (MV_SDIO_REG_BASE + 0x10c + ((win)<<3)) ++ ++ ++/* BITs in Windows 0-3 Control and Base Registers */ ++#define MV_SDMMC_WIN_ENABLE_BIT 0 ++#define MV_SDMMC_WIN_ENABLE_MASK (1<= TDM_MBUS_MAX_WIN) ++ { ++ mvOsPrintf("mvTdmWinSet: ERR. Invalid win num %d\n",winNum); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check if the requested window overlapps with current windows */ ++ if (MV_TRUE == tdmWinOverlapDetect(winNum, &pAddrDecWin->addrWin)) ++ { ++ mvOsPrintf("mvTdmWinSet: ERR. Window %d overlap\n", winNum); ++ return MV_ERROR; ++ } ++ ++ /* check if address is aligned to the size */ ++ if (MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) ++ { ++ mvOsPrintf("mvTdmWinSet: Error setting TDM window %d to "\ ++ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", ++ winNum, ++ mvCtrlTargetNameGet(pAddrDecWin->target), ++ pAddrDecWin->addrWin.baseLow, ++ pAddrDecWin->addrWin.size); ++ return MV_ERROR; ++ } ++ ++ decRegs.baseReg = MV_REG_READ(TDM_WIN_BASE_REG(winNum)); ++ decRegs.sizeReg = (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_SIZE_MASK) >> TDM_WIN_SIZE_OFFS; ++ ++ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) ++ { ++ mvOsPrintf("mvTdmWinSet: mvCtrlAddrDecToReg Failed\n"); ++ return MV_ERROR; ++ } ++ ++ mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs); ++ ++ /* for the safe side we disable the window before writing the new ++ values */ ++ mvTdmWinEnable(winNum, MV_FALSE); ++ ++ ctrlReg |= (targetAttribs.attrib << TDM_WIN_ATTRIB_OFFS); ++ ctrlReg |= (targetAttribs.targetId << TDM_WIN_TARGET_OFFS); ++ ctrlReg |= (decRegs.sizeReg & TDM_WIN_SIZE_MASK); ++ ++ /* Write to address base and control registers */ ++ MV_REG_WRITE(TDM_WIN_BASE_REG(winNum), decRegs.baseReg); ++ MV_REG_WRITE(TDM_WIN_CTRL_REG(winNum), ctrlReg); ++ /* Enable address decode target window */ ++ if (pAddrDecWin->enable == MV_TRUE) ++ { ++ mvTdmWinEnable(winNum, MV_TRUE); ++ } ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvTdmWinGet - Get peripheral target address window. ++* ++* DESCRIPTION: ++* Get TDM peripheral target address window. ++* ++* INPUT: ++* winNum - TDM to target address decode window number. ++* ++* OUTPUT: ++* pAddrDecWin - TDM target window data structure. ++* ++* RETURN: ++* MV_ERROR if register parameters are invalid. ++* ++*******************************************************************************/ ++ ++MV_STATUS mvTdmWinGet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin) ++{ ++ ++ MV_DEC_REGS decRegs; ++ MV_TARGET_ATTRIB targetAttrib; ++ ++ /* Parameter checking */ ++ if (winNum >= TDM_MBUS_MAX_WIN) ++ { ++ mvOsPrintf("mvTdmWinGet: ERR. Invalid winNum %d\n", winNum); ++ return MV_NOT_SUPPORTED; ++ } ++ ++ decRegs.baseReg = MV_REG_READ(TDM_WIN_BASE_REG(winNum)); ++ decRegs.sizeReg = (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_SIZE_MASK) >> TDM_WIN_SIZE_OFFS; ++ ++ if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) ++ { ++ mvOsPrintf("mvTdmWinGet: mvCtrlRegToAddrDec Failed \n"); ++ return MV_ERROR; ++ } ++ ++ /* attrib and targetId */ ++ targetAttrib.attrib = ++ (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ATTRIB_MASK) >> TDM_WIN_ATTRIB_OFFS; ++ targetAttrib.targetId = ++ (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_TARGET_MASK) >> TDM_WIN_TARGET_OFFS; ++ ++ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); ++ ++ /* Check if window is enabled */ ++ if (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ENABLE_MASK) ++ { ++ pAddrDecWin->enable = MV_TRUE; ++ } ++ else ++ { ++ pAddrDecWin->enable = MV_FALSE; ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvTdmWinEnable - Enable/disable a TDM to target address window ++* ++* DESCRIPTION: ++* This function enable/disable a TDM to target address window. ++* According to parameter 'enable' the routine will enable the ++* window, thus enabling TDM accesses (before enabling the window it is ++* tested for overlapping). Otherwise, the window will be disabled. ++* ++* INPUT: ++* winNum - TDM to target address decode window number. ++* enable - Enable/disable parameter. ++* ++* OUTPUT: ++* N/A ++* ++* RETURN: ++* MV_ERROR if decode window number was wrong or enabled window overlapps. ++* ++*******************************************************************************/ ++MV_STATUS mvTdmWinEnable(int winNum, MV_BOOL enable) ++{ ++ MV_TDM_DEC_WIN addrDecWin; ++ ++ if (MV_TRUE == enable) ++ { ++ if (winNum >= TDM_MBUS_MAX_WIN) ++ { ++ mvOsPrintf("mvTdmWinEnable:ERR. Invalid winNum%d\n",winNum); ++ return MV_ERROR; ++ } ++ ++ /* First check for overlap with other enabled windows */ ++ /* Get current window */ ++ if (MV_OK != mvTdmWinGet(winNum, &addrDecWin)) ++ { ++ mvOsPrintf("mvTdmWinEnable:ERR. targetWinGet fail\n"); ++ return MV_ERROR; ++ } ++ /* Check for overlapping */ ++ if (MV_FALSE == tdmWinOverlapDetect(winNum, &(addrDecWin.addrWin))) ++ { ++ /* No Overlap. Enable address decode target window */ ++ MV_REG_BIT_SET(TDM_WIN_CTRL_REG(winNum), TDM_WIN_ENABLE_MASK); ++ } ++ else ++ { /* Overlap detected */ ++ mvOsPrintf("mvTdmWinEnable:ERR. Overlap detected\n"); ++ return MV_ERROR; ++ } ++ } ++ else ++ { ++ MV_REG_BIT_RESET(TDM_WIN_CTRL_REG(winNum), TDM_WIN_ENABLE_MASK); ++ } ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* tdmWinOverlapDetect - Detect TDM address windows overlapping ++* ++* DESCRIPTION: ++* An unpredicted behaviour is expected in case TDM address decode ++* windows overlapps. ++* This function detects TDM address decode windows overlapping of a ++* specified window. The function does not check the window itself for ++* overlapping. The function also skipps disabled address decode windows. ++* ++* INPUT: ++* winNum - address decode window number. ++* pAddrDecWin - An address decode window struct. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the given address window overlap current address ++* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data ++* from registers. ++* ++*******************************************************************************/ ++static MV_STATUS tdmWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) ++{ ++ MV_U32 winNumIndex; ++ MV_TDM_DEC_WIN addrDecWin; ++ ++ for (winNumIndex = 0; winNumIndex < TDM_MBUS_MAX_WIN; winNumIndex++) ++ { ++ /* Do not check window itself */ ++ if (winNumIndex == winNum) ++ { ++ continue; ++ } ++ /* Do not check disabled windows */ ++ if (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ENABLE_MASK) ++ { ++ /* Get window parameters */ ++ if (MV_OK != mvTdmWinGet(winNumIndex, &addrDecWin)) ++ { ++ DB(mvOsPrintf("dmaWinOverlapDetect: ERR. TargetWinGet failed\n")); ++ return MV_ERROR; ++ } ++ ++ if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin))) ++ { ++ return MV_TRUE; ++ } ++ } ++ } ++ return MV_FALSE; ++} ++ ++/******************************************************************************* ++* mvTdmAddrDecShow - Print the TDM address decode map. ++* ++* DESCRIPTION: ++* This function print the TDM address decode map. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvTdmAddrDecShow(MV_VOID) ++{ ++ MV_TDM_DEC_WIN win; ++ int i; ++ ++ mvOsOutput( "\n" ); ++ mvOsOutput( "TDM:\n" ); ++ mvOsOutput( "----\n" ); ++ ++ for( i = 0; i < TDM_MBUS_MAX_WIN; i++ ) ++ { ++ memset( &win, 0, sizeof(MV_TDM_DEC_WIN) ); ++ ++ mvOsOutput( "win%d - ", i ); ++ ++ if (mvTdmWinGet(i, &win ) == MV_OK ) ++ { ++ if( win.enable ) ++ { ++ mvOsOutput( "%s base %08x, ", ++ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow); ++ mvOsOutput( "...." ); ++ mvSizePrint( win.addrWin.size ); ++ mvOsOutput( "\n" ); ++ } ++ else ++ mvOsOutput( "disable\n" ); ++ } ++ } ++} ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTdm.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,106 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvSysTdmh ++#define __INCmvSysTdmh ++ ++#include "ctrlEnv/sys/mvCpuIf.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "ctrlEnv/mvCtrlEnvAddrDec.h" ++ ++typedef struct _mvTdmDecWin ++{ ++ MV_TARGET target; ++ MV_ADDR_WIN addrWin; /* An address window*/ ++ MV_BOOL enable; /* Address decode window is enabled/disabled */ ++} MV_TDM_DEC_WIN; ++ ++MV_STATUS mvTdmWinInit(MV_VOID); ++MV_STATUS mvTdmWinSet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin); ++MV_STATUS mvTdmWinGet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin); ++MV_STATUS mvTdmWinEnable(int winNum, MV_BOOL enable); ++MV_VOID mvTdmAddrDecShow(MV_VOID); ++ ++ ++#define TDM_MBUS_MAX_WIN 4 ++#define TDM_WIN_CTRL_REG(win) ((TDM_REG_BASE + 0x4030) + (win<<4)) ++#define TDM_WIN_BASE_REG(win) ((TDM_REG_BASE +0x4034) + (win<<4)) ++ ++/* TDM_WIN_CTRL_REG bits */ ++#define TDM_WIN_ENABLE_OFFS 0 ++#define TDM_WIN_ENABLE_MASK (1<= TSU_MAX_DECODE_WIN) ++ { ++ mvOsPrintf("mvTsuWinSet: ERR. Invalid win num %d\n",winNum); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check if the requested window overlapps with current windows */ ++ if(MV_TRUE == tsuWinOverlapDetect(winNum, &pAddrDecWin->addrWin)) ++ { ++ mvOsPrintf("mvTsuWinSet: ERR. Window %d overlap\n", winNum); ++ return MV_ERROR; ++ } ++ ++ /* check if address is aligned to the size */ ++ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow,pAddrDecWin->addrWin.size)) ++ { ++ mvOsPrintf("mvTsuWinSet: Error setting TSU window %d to target " ++ "%s.\nAddress 0x%08x is unaligned to size 0x%x.\n", ++ winNum, mvCtrlTargetNameGet(pAddrDecWin->target), ++ pAddrDecWin->addrWin.baseLow, ++ pAddrDecWin->addrWin.size); ++ return MV_ERROR; ++ } ++ ++ decRegs.baseReg = MV_REG_READ(MV_TSU_WIN_BASE_REG(winNum)); ++ decRegs.sizeReg = MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNum)); ++ ++ if(MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs)) ++ { ++ mvOsPrintf("mvTsuWinSet: mvCtrlAddrDecToReg Failed\n"); ++ return MV_ERROR; ++ } ++ ++ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); ++ ++ /* set attributes */ ++ decRegs.sizeReg &= ~TSU_WIN_CTRL_ATTR_MASK; ++ decRegs.sizeReg |= targetAttribs.attrib << TSU_WIN_CTRL_ATTR_OFFS; ++ /* set target ID */ ++ decRegs.sizeReg &= ~TSU_WIN_CTRL_TARGET_MASK; ++ decRegs.sizeReg |= targetAttribs.targetId << TSU_WIN_CTRL_TARGET_OFFS; ++ ++ /* for the safe side we disable the window before writing the new */ ++ /* values */ ++ mvTsuWinEnable(winNum, MV_FALSE); ++ MV_REG_WRITE(MV_TSU_WIN_CTRL_REG(winNum),decRegs.sizeReg); ++ ++ /* Write to address decode Size Register */ ++ MV_REG_WRITE(MV_TSU_WIN_BASE_REG(winNum), decRegs.baseReg); ++ ++ /* Enable address decode target window */ ++ if(pAddrDecWin->enable == MV_TRUE) ++ { ++ mvTsuWinEnable(winNum,MV_TRUE); ++ } ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvTsuWinGet ++* ++* DESCRIPTION: ++* Get TSU peripheral target address window. ++* ++* INPUT: ++* winNum - TSU to target address decode window number. ++* ++* OUTPUT: ++* pAddrDecWin - TSU target window data structure. ++* ++* RETURN: ++* MV_ERROR if register parameters are invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvTsuWinGet(MV_U32 winNum, MV_TSU_DEC_WIN *pAddrDecWin) ++{ ++ MV_DEC_REGS decRegs; ++ MV_TARGET_ATTRIB targetAttrib; ++ ++ /* Parameter checking */ ++ if(winNum >= TSU_MAX_DECODE_WIN) ++ { ++ mvOsPrintf("mvTsuWinGet: ERR. Invalid winNum %d\n", winNum); ++ return MV_NOT_SUPPORTED; ++ } ++ ++ decRegs.baseReg = MV_REG_READ(MV_TSU_WIN_BASE_REG(winNum)); ++ decRegs.sizeReg = MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNum)); ++ ++ if(MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin))) ++ { ++ mvOsPrintf("mvTsuWinGet: mvCtrlRegToAddrDec Failed \n"); ++ return MV_ERROR; ++ } ++ ++ /* attrib and targetId */ ++ targetAttrib.attrib = ++ (decRegs.sizeReg & TSU_WIN_CTRL_ATTR_MASK) >> TSU_WIN_CTRL_ATTR_OFFS; ++ targetAttrib.targetId = ++ (decRegs.sizeReg & TSU_WIN_CTRL_TARGET_MASK) >> TSU_WIN_CTRL_TARGET_OFFS; ++ ++ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); ++ ++ /* Check if window is enabled */ ++ if((MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNum)) & TSU_WIN_CTRL_EN_MASK)) ++ { ++ pAddrDecWin->enable = MV_TRUE; ++ } ++ else ++ { ++ pAddrDecWin->enable = MV_FALSE; ++ } ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvTsuWinEnable ++* ++* DESCRIPTION: ++* This function enable/disable a TSU to target address window. ++* According to parameter 'enable' the routine will enable the ++* window, thus enabling TSU accesses (before enabling the window it is ++* tested for overlapping). Otherwise, the window will be disabled. ++* ++* INPUT: ++* winNum - TSU to target address decode window number. ++* enable - Enable / disable parameter. ++* ++* OUTPUT: ++* N/A ++* ++* RETURN: ++* MV_ERROR if decode window number was wrong or enabled window overlapps. ++* ++*******************************************************************************/ ++MV_STATUS mvTsuWinEnable(MV_U32 winNum,MV_BOOL enable) ++{ ++ MV_TSU_DEC_WIN addrDecWin; ++ ++ /* Parameter checking */ ++ if(winNum >= TSU_MAX_DECODE_WIN) ++ { ++ mvOsPrintf("mvTsuWinEnable: ERR. Invalid winNum%d\n",winNum); ++ return MV_ERROR; ++ } ++ ++ if(enable == MV_TRUE) ++ { ++ /* First check for overlap with other enabled windows */ ++ /* Get current window. */ ++ if(MV_OK != mvTsuWinGet(winNum,&addrDecWin)) ++ { ++ mvOsPrintf("mvTsuWinEnable: ERR. targetWinGet fail\n"); ++ return MV_ERROR; ++ } ++ /* Check for overlapping. */ ++ if(MV_FALSE == tsuWinOverlapDetect(winNum,&(addrDecWin.addrWin))) ++ { ++ /* No Overlap. Enable address decode target window */ ++ MV_REG_BIT_SET(MV_TSU_WIN_CTRL_REG(winNum), ++ TSU_WIN_CTRL_EN_MASK); ++ } ++ else ++ { ++ /* Overlap detected */ ++ mvOsPrintf("mvTsuWinEnable: ERR. Overlap detected\n"); ++ return MV_ERROR; ++ } ++ } ++ else ++ { ++ /* Disable address decode target window */ ++ MV_REG_BIT_RESET(MV_TSU_WIN_CTRL_REG(winNum), ++ TSU_WIN_CTRL_EN_MASK); ++ } ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvTsuWinTargetGet ++* ++* DESCRIPTION: ++* Get Window number associated with target ++* ++* INPUT: ++* target - Target ID to get the window number for. ++* OUTPUT: ++* ++* RETURN: ++* window number or 0xFFFFFFFF on error. ++* ++*******************************************************************************/ ++MV_U32 mvTsuWinTargetGet(MV_TARGET target) ++{ ++ MV_TSU_DEC_WIN decWin; ++ MV_U32 winNum; ++ ++ /* Check parameters */ ++ if(target >= MAX_TARGETS) ++ { ++ mvOsPrintf("mvTsuWinTargetGet: target %d is Illigal\n", target); ++ return 0xffffffff; ++ } ++ ++ for(winNum = 0; winNum < TSU_MAX_DECODE_WIN; winNum++) ++ { ++ if(mvTsuWinGet(winNum,&decWin) != MV_OK) ++ { ++ mvOsPrintf("mvTsuWinGet: window returned error\n"); ++ return 0xffffffff; ++ } ++ ++ if (decWin.enable == MV_TRUE) ++ { ++ if(decWin.target == target) ++ { ++ return winNum; ++ } ++ } ++ } ++ return 0xFFFFFFFF; ++} ++ ++ ++/******************************************************************************* ++* tsuWinOverlapDetect ++* ++* DESCRIPTION: ++* Detect TSU address windows overlapping ++* An unpredicted behaviur is expected in case TSU address decode ++* windows overlapps. ++* This function detects TSU address decode windows overlapping of a ++* specified window. The function does not check the window itself for ++* overlapping. The function also skipps disabled address decode windows. ++* ++* INPUT: ++* winNum - address decode window number. ++* pAddrDecWin - An address decode window struct. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the given address window overlap current address ++* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data ++* from registers. ++* ++*******************************************************************************/ ++static MV_STATUS tsuWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin) ++{ ++ MV_U32 ctrlReg; ++ MV_U32 winNumIndex; ++ MV_TSU_DEC_WIN addrDecWin; ++ ++ for(winNumIndex = 0; winNumIndex < TSU_MAX_DECODE_WIN; winNumIndex++) ++ { ++ /* Do not check window itself */ ++ if(winNumIndex == winNum) ++ { ++ continue; ++ } ++ ++ /* Do not check disabled windows */ ++ ctrlReg = MV_REG_READ(MV_TSU_WIN_CTRL_REG(winNumIndex)); ++ if((ctrlReg & TSU_WIN_CTRL_EN_MASK) == 0) ++ { ++ continue; ++ } ++ ++ /* Get window parameters */ ++ if (MV_OK != mvTsuWinGet(winNumIndex, &addrDecWin)) ++ { ++ mvOsPrintf("tsuWinOverlapDetect: ERR. mvTsuWinGet failed\n"); ++ return MV_ERROR; ++ } ++ ++ if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin))) ++ { ++ return MV_TRUE; ++ } ++ } ++ return MV_FALSE; ++} ++ ++ ++/******************************************************************************* ++* mvTsuAddrDecShow ++* ++* DESCRIPTION: ++* Print the TSU address decode map. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++void mvTsuAddrDecShow(void) ++{ ++ MV_TSU_DEC_WIN win; ++ int i; ++ ++ if (MV_FALSE == mvCtrlPwrClckGet(TS_UNIT_ID, 0)) ++ return; ++ ++ mvOsOutput( "\n" ); ++ mvOsOutput( "TSU:\n"); ++ mvOsOutput( "----\n" ); ++ ++ for(i = 0; i < TSU_MAX_DECODE_WIN; i++) ++ { ++ memset(&win, 0, sizeof(TSU_MAX_DECODE_WIN)); ++ mvOsOutput( "win%d - ", i ); ++ ++ if(mvTsuWinGet(i, &win ) == MV_OK ) ++ { ++ if(win.enable == MV_TRUE) ++ { ++ mvOsOutput("%s base %08x, ", ++ mvCtrlTargetNameGet(win.target), ++ win.addrWin.baseLow); ++ mvOsOutput( "...." ); ++ mvSizePrint(win.addrWin.size ); ++ mvOsOutput( "\n" ); ++ } ++ else ++ { ++ mvOsOutput( "disable\n" ); ++ } ++ } ++ } ++ return; ++} ++ ++ ++/******************************************************************************* ++* mvTsuInit ++* ++* DESCRIPTION: ++* Initialize the TSU unit, and get unit out of reset. ++* ++* INPUT: ++* coreClock - The core clock at which the TSU should operate. ++* mode - The mode on configure the unit into (serial/parallel). ++* memHandle - Memory handle used for memory allocations. ++* OUTPUT: ++* None. ++* RETURN: ++* MV_OK - on success, ++* ++*******************************************************************************/ ++MV_STATUS mvTsuInit(MV_TSU_CORE_CLOCK coreClock, MV_TSU_PORTS_MODE mode, ++ void *osHandle) ++{ ++ MV_STATUS status; ++ ++ status = mvTsuWinInit(); ++ if(status == MV_OK) ++ status = mvTsuHalInit(coreClock,mode,osHandle); ++ ++ return status; ++} +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysTs.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,110 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvSysTsh ++#define __INCmvSysTsh ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++/* includes */ ++#include "ts/mvTsu.h" ++#include "ctrlEnv/sys/mvCpuIf.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "ctrlEnv/mvCtrlEnvAddrDec.h" ++ ++#define TSU_MAX_DECODE_WIN 4 ++ ++ ++/*******************************************/ ++/* TSU Windows Registers */ ++/*******************************************/ ++#define MV_TSU_WIN_CTRL_REG(win) (TSU_GLOBAL_REG_BASE +0x30 + 0x10 * win) ++#define MV_TSU_WIN_BASE_REG(win) (TSU_GLOBAL_REG_BASE +0x34 + 0x10 * win) ++ ++/* TSU windows control register. */ ++#define TSU_WIN_CTRL_EN_MASK (0x1 << 0) ++#define TSU_WIN_CTRL_TARGET_OFFS 4 ++#define TSU_WIN_CTRL_TARGET_MASK (0xF << TSU_WIN_CTRL_TARGET_OFFS) ++#define TSU_WIN_CTRL_ATTR_OFFS 8 ++#define TSU_WIN_CTRL_ATTR_MASK (0xFF << TSU_WIN_CTRL_ATTR_OFFS) ++#define TSU_WIN_CTRL_SIZE_OFFS 16 ++#define TSU_WIN_CTRL_SIZE_MASK (0xFFFF << TSU_WIN_CTRL_SIZE_OFFS) ++ ++/* TSU windows base register. */ ++#define TSU_WIN_BASE_OFFS 16 ++#define TSU_WIN_BASE_MASK (0xFFFF << TSU_WIN_BASE_OFFS) ++ ++MV_STATUS mvTsuWinInit(void); ++ ++void mvTsuAddrDecShow(void); ++MV_STATUS mvTsuInit(MV_TSU_CORE_CLOCK coreClock, MV_TSU_PORTS_MODE mode, ++ void *osHandle); ++ ++#ifdef __cplusplus ++} ++#endif /* __cplusplus */ ++ ++#endif /* __INCmvTsh */ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.c linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.c +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysUsb.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,497 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#include "ctrlEnv/sys/mvSysUsb.h" ++ ++MV_TARGET usbAddrDecPrioTab[] = ++{ ++#if defined(MV_INCLUDE_SDRAM_CS0) ++ SDRAM_CS0, ++#endif ++#if defined(MV_INCLUDE_SDRAM_CS1) ++ SDRAM_CS1, ++#endif ++#if defined(MV_INCLUDE_SDRAM_CS2) ++ SDRAM_CS2, ++#endif ++#if defined(MV_INCLUDE_SDRAM_CS3) ++ SDRAM_CS3, ++#endif ++#if defined(MV_INCLUDE_CESA) && defined(USB_UNDERRUN_WA) ++ CRYPT_ENG, ++#endif ++#if defined(MV_INCLUDE_PEX) ++ PEX0_MEM, ++#endif ++ TBL_TERM ++}; ++ ++ ++ ++MV_STATUS mvUsbInit(int dev, MV_BOOL isHost) ++{ ++ MV_STATUS status; ++ ++ status = mvUsbWinInit(dev); ++ if(status != MV_OK) ++ return status; ++ ++ return mvUsbHalInit(dev, isHost); ++} ++ ++ ++/******************************************************************************* ++* usbWinOverlapDetect - Detect USB address windows overlapping ++* ++* DESCRIPTION: ++* An unpredicted behaviur is expected in case USB address decode ++* windows overlapps. ++* This function detects USB address decode windows overlapping of a ++* specified window. The function does not check the window itself for ++* overlapping. The function also skipps disabled address decode windows. ++* ++* INPUT: ++* winNum - address decode window number. ++* pAddrDecWin - An address decode window struct. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the given address window overlap current address ++* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data ++* from registers. ++* ++*******************************************************************************/ ++static MV_STATUS usbWinOverlapDetect(int dev, MV_U32 winNum, ++ MV_ADDR_WIN *pAddrWin) ++{ ++ MV_U32 winNumIndex; ++ MV_DEC_WIN addrDecWin; ++ ++ for(winNumIndex=0; winNumIndex= MV_USB_MAX_ADDR_DECODE_WIN) ++ { ++ mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check if the requested window overlapps with current windows */ ++ if (MV_TRUE == usbWinOverlapDetect(dev, winNum, &pDecWin->addrWin)) ++ { ++ mvOsPrintf("%s: ERR. Window %d overlap\n", __FUNCTION__, winNum); ++ return MV_ERROR; ++ } ++ ++ /* check if address is aligned to the size */ ++ if(MV_IS_NOT_ALIGN(pDecWin->addrWin.baseLow, pDecWin->addrWin.size)) ++ { ++ mvOsPrintf("mvUsbWinSet:Error setting USB window %d to "\ ++ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n", ++ winNum, ++ mvCtrlTargetNameGet(pDecWin->target), ++ pDecWin->addrWin.baseLow, ++ pDecWin->addrWin.size); ++ return MV_ERROR; ++ } ++ ++ if(MV_OK != mvCtrlAddrDecToParams(pDecWin, &winParams)) ++ { ++ mvOsPrintf("%s: mvCtrlAddrDecToParams Failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ /* set Size, Attributes and TargetID */ ++ sizeReg = (((winParams.targetId << MV_USB_WIN_TARGET_OFFSET) & MV_USB_WIN_TARGET_MASK) | ++ ((winParams.attrib << MV_USB_WIN_ATTR_OFFSET) & MV_USB_WIN_ATTR_MASK) | ++ ((winParams.size << MV_USB_WIN_SIZE_OFFSET) & MV_USB_WIN_SIZE_MASK)); ++ ++#if defined(MV645xx) || defined(MV646xx) ++ /* If window is DRAM with HW cache coherency, make sure bit2 is set */ ++ sizeReg &= ~MV_USB_WIN_BURST_WR_LIMIT_MASK; ++ ++ if((MV_TARGET_IS_DRAM(pDecWin->target)) && ++ (pDecWin->addrWinAttr.cachePolicy != NO_COHERENCY)) ++ { ++ sizeReg |= MV_USB_WIN_BURST_WR_32BIT_LIMIT; ++ } ++ else ++ { ++ sizeReg |= MV_USB_WIN_BURST_WR_NO_LIMIT; ++ } ++#endif /* MV645xx || MV646xx */ ++ ++ if (pDecWin->enable == MV_TRUE) ++ { ++ sizeReg |= MV_USB_WIN_ENABLE_MASK; ++ } ++ else ++ { ++ sizeReg &= ~MV_USB_WIN_ENABLE_MASK; ++ } ++ ++ /* Update Base value */ ++ baseReg = (winParams.baseAddr & MV_USB_WIN_BASE_MASK); ++ ++ MV_REG_WRITE( MV_USB_WIN_CTRL_REG(dev, winNum), sizeReg); ++ MV_REG_WRITE( MV_USB_WIN_BASE_REG(dev, winNum), baseReg); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvUsbWinGet - Get USB peripheral target address window. ++* ++* DESCRIPTION: ++* Get USB peripheral target address window. ++* ++* INPUT: ++* winNum - USB target address decode window number. ++* ++* OUTPUT: ++* pDecWin - USB target window data structure. ++* ++* RETURN: ++* MV_ERROR if register parameters are invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvUsbWinGet(int dev, MV_U32 winNum, MV_DEC_WIN *pDecWin) ++{ ++ MV_DEC_WIN_PARAMS winParam; ++ MV_U32 sizeReg, baseReg; ++ ++ /* Parameter checking */ ++ if (winNum >= MV_USB_MAX_ADDR_DECODE_WIN) ++ { ++ mvOsPrintf("%s (dev=%d): ERR. Invalid winNum %d\n", ++ __FUNCTION__, dev, winNum); ++ return MV_NOT_SUPPORTED; ++ } ++ ++ baseReg = MV_REG_READ( MV_USB_WIN_BASE_REG(dev, winNum) ); ++ sizeReg = MV_REG_READ( MV_USB_WIN_CTRL_REG(dev, winNum) ); ++ ++ /* Check if window is enabled */ ++ if(sizeReg & MV_USB_WIN_ENABLE_MASK) ++ { ++ pDecWin->enable = MV_TRUE; ++ ++ /* Extract window parameters from registers */ ++ winParam.targetId = (sizeReg & MV_USB_WIN_TARGET_MASK) >> MV_USB_WIN_TARGET_OFFSET; ++ winParam.attrib = (sizeReg & MV_USB_WIN_ATTR_MASK) >> MV_USB_WIN_ATTR_OFFSET; ++ winParam.size = (sizeReg & MV_USB_WIN_SIZE_MASK) >> MV_USB_WIN_SIZE_OFFSET; ++ winParam.baseAddr = (baseReg & MV_USB_WIN_BASE_MASK); ++ ++ /* Translate the decode window parameters to address decode struct */ ++ if (MV_OK != mvCtrlParamsToAddrDec(&winParam, pDecWin)) ++ { ++ mvOsPrintf("Failed to translate register parameters to USB address" \ ++ " decode window structure\n"); ++ return MV_ERROR; ++ } ++ } ++ else ++ { ++ pDecWin->enable = MV_FALSE; ++ } ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvUsbWinInit - ++* ++* INPUT: ++* ++* OUTPUT: ++* ++* RETURN: ++* MV_ERROR if register parameters are invalid. ++* ++*******************************************************************************/ ++MV_STATUS mvUsbWinInit(int dev) ++{ ++ MV_STATUS status; ++ MV_DEC_WIN usbWin; ++ MV_CPU_DEC_WIN cpuAddrDecWin; ++ int winNum; ++ MV_U32 winPrioIndex = 0; ++ ++ /* First disable all address decode windows */ ++ for(winNum = 0; winNum < MV_USB_MAX_ADDR_DECODE_WIN; winNum++) ++ { ++ MV_REG_BIT_RESET(MV_USB_WIN_CTRL_REG(dev, winNum), MV_USB_WIN_ENABLE_MASK); ++ } ++ ++ /* Go through all windows in user table until table terminator */ ++ winNum = 0; ++ while( (usbAddrDecPrioTab[winPrioIndex] != TBL_TERM) && ++ (winNum < MV_USB_MAX_ADDR_DECODE_WIN) ) ++ { ++ /* first get attributes from CPU If */ ++ status = mvCpuIfTargetWinGet(usbAddrDecPrioTab[winPrioIndex], ++ &cpuAddrDecWin); ++ ++ if(MV_NO_SUCH == status) ++ { ++ winPrioIndex++; ++ continue; ++ } ++ if (MV_OK != status) ++ { ++ mvOsPrintf("%s: ERR. mvCpuIfTargetWinGet failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ if (cpuAddrDecWin.enable == MV_TRUE) ++ { ++ usbWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh; ++ usbWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow; ++ usbWin.addrWin.size = cpuAddrDecWin.addrWin.size; ++ usbWin.enable = MV_TRUE; ++ usbWin.target = usbAddrDecPrioTab[winPrioIndex]; ++ ++#if defined(MV645xx) || defined(MV646xx) ++ /* Get the default attributes for that target window */ ++ mvCtrlDefAttribGet(usbWin.target, &usbWin.addrWinAttr); ++#endif /* MV645xx || MV646xx */ ++ ++ if(MV_OK != mvUsbWinSet(dev, winNum, &usbWin)) ++ { ++ return MV_ERROR; ++ } ++ winNum++; ++ } ++ winPrioIndex++; ++ } ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvUsbAddrDecShow - Print the USB address decode map. ++* ++* DESCRIPTION: ++* This function print the USB address decode map. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvUsbAddrDecShow(MV_VOID) ++{ ++ MV_DEC_WIN addrDecWin; ++ int i, winNum; ++ ++ mvOsOutput( "\n" ); ++ mvOsOutput( "USB:\n" ); ++ mvOsOutput( "----\n" ); ++ ++ for(i=0; i= XOR_MAX_ADDR_DEC_WIN) ++ { ++ DB(mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__, winNum)); ++ return MV_BAD_PARAM; ++ } ++ if (pAddrDecWin == NULL) ++ { ++ DB(mvOsPrintf("%s: ERR. pAddrDecWin is NULL pointer\n", __FUNCTION__ )); ++ return MV_BAD_PTR; ++ } ++ /* Check if the requested window overlaps with current windows */ ++ if (MV_TRUE == xorWinOverlapDetect(unit, winNum, &pAddrDecWin->addrWin)) ++ { ++ DB(mvOsPrintf("%s: ERR. Window %d overlap\n",__FUNCTION__,winNum)); ++ return MV_ERROR; ++ } ++ ++ xorDecRegs.baseReg = MV_REG_READ(XOR_BASE_ADDR_REG(unit,winNum)); ++ xorDecRegs.sizeReg = MV_REG_READ(XOR_SIZE_MASK_REG(unit,winNum)); ++ ++ /* Get Base Address and size registers values */ ++ if(MV_OK != mvCtrlAddrDecToReg(&pAddrDecWin->addrWin, &xorDecRegs)) ++ { ++ DB(mvOsPrintf("%s: ERR. Invalid addr dec window\n",__FUNCTION__)); ++ return MV_BAD_PARAM; ++ } ++ ++ ++ mvCtrlAttribGet(pAddrDecWin->target,&targetAttribs); ++ ++ /* set attributes */ ++ xorDecRegs.baseReg &= ~XEBARX_ATTR_MASK; ++ xorDecRegs.baseReg |= targetAttribs.attrib << XEBARX_ATTR_OFFS; ++ /* set target ID */ ++ xorDecRegs.baseReg &= ~XEBARX_TARGET_MASK; ++ xorDecRegs.baseReg |= targetAttribs.targetId << XEBARX_TARGET_OFFS; ++ ++ ++ /* Write to address decode Base Address Register */ ++ MV_REG_WRITE(XOR_BASE_ADDR_REG(unit,winNum), xorDecRegs.baseReg); ++ ++ /* Write to Size Register */ ++ MV_REG_WRITE(XOR_SIZE_MASK_REG(unit,winNum), xorDecRegs.sizeReg); ++ ++ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) ++ { ++ if (pAddrDecWin->enable) ++ { ++ MV_REG_BIT_SET(XOR_WINDOW_CTRL_REG(unit,chan), ++ XEXWCR_WIN_EN_MASK(winNum)); ++ } ++ else ++ { ++ MV_REG_BIT_RESET(XOR_WINDOW_CTRL_REG(unit,chan), ++ XEXWCR_WIN_EN_MASK(winNum)); ++ } ++ } ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvXorTargetWinGet - Get xor peripheral target address window. ++* ++* DESCRIPTION: ++* Get xor peripheral target address window. ++* ++* INPUT: ++* winNum - One of the possible XOR memory decode windows. ++* ++* OUTPUT: ++* base - Window base address. ++* size - Window size. ++* enable - window enable/disable. ++* ++* RETURN: ++* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. ++* ++*******************************************************************************/ ++MV_STATUS mvXorTargetWinGet(MV_U32 unit,MV_U32 winNum, MV_XOR_DEC_WIN *pAddrDecWin) ++{ ++ MV_DEC_REGS xorDecRegs; ++ MV_TARGET_ATTRIB targetAttrib; ++ MV_U32 chan=0,chanWinEn; ++ ++ /* Parameter checking */ ++ if (winNum >= XOR_MAX_ADDR_DEC_WIN) ++ { ++ DB(mvOsPrintf("%s: ERR. Invalid win num %d\n",__FUNCTION__ , winNum)); ++ return MV_ERROR; ++ } ++ ++ if (NULL == pAddrDecWin) ++ { ++ DB(mvOsPrintf("%s: ERR. pAddrDecWin is NULL pointer\n", __FUNCTION__ )); ++ return MV_BAD_PTR; ++ } ++ ++ chanWinEn = MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,0)) & XEXWCR_WIN_EN_MASK(winNum); ++ ++ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) /* we should scan here all channels per unit */ ++ { ++ /* Check if enable bit is equal for all channels */ ++ if ((MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,chan)) & ++ XEXWCR_WIN_EN_MASK(winNum)) != chanWinEn) ++ { ++ mvOsPrintf("%s: ERR. Window enable field must be equal in " ++ "all channels(chan=%d)\n",__FUNCTION__, chan); ++ return MV_ERROR; ++ } ++ } ++ ++ ++ ++ xorDecRegs.baseReg = MV_REG_READ(XOR_BASE_ADDR_REG(unit,winNum)); ++ xorDecRegs.sizeReg = MV_REG_READ(XOR_SIZE_MASK_REG(unit,winNum)); ++ ++ if (MV_OK != mvCtrlRegToAddrDec(&xorDecRegs, &pAddrDecWin->addrWin)) ++ { ++ mvOsPrintf("%s: ERR. mvCtrlRegToAddrDec failed\n", __FUNCTION__); ++ return MV_ERROR; ++ } ++ ++ /* attrib and targetId */ ++ targetAttrib.attrib = ++ (xorDecRegs.baseReg & XEBARX_ATTR_MASK) >> XEBARX_ATTR_OFFS; ++ targetAttrib.targetId = ++ (xorDecRegs.baseReg & XEBARX_TARGET_MASK) >> XEBARX_TARGET_OFFS; ++ ++ ++ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib); ++ ++ if(chanWinEn) ++ { ++ pAddrDecWin->enable = MV_TRUE; ++ } ++ else pAddrDecWin->enable = MV_FALSE; ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvXorTargetWinEnable - Enable/disable a Xor address decode window ++* ++* DESCRIPTION: ++* This function enable/disable a XOR address decode window. ++* if parameter 'enable' == MV_TRUE the routine will enable the ++* window, thus enabling XOR accesses (before enabling the window it is ++* tested for overlapping). Otherwise, the window will be disabled. ++* ++* INPUT: ++* winNum - Decode window number. ++* enable - Enable/disable parameter. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. ++* ++*******************************************************************************/ ++MV_STATUS mvXorTargetWinEnable(MV_U32 unit,MV_U32 winNum, MV_BOOL enable) ++{ ++ MV_XOR_DEC_WIN addrDecWin; ++ MV_U32 chan; ++ ++ /* Parameter checking */ ++ if (winNum >= XOR_MAX_ADDR_DEC_WIN) ++ { ++ DB(mvOsPrintf("%s: ERR. Invalid winNum%d\n", __FUNCTION__, winNum)); ++ return MV_ERROR; ++ } ++ ++ if (enable == MV_TRUE) ++ { ++ /* Get current window */ ++ if (MV_OK != mvXorTargetWinGet(unit,winNum, &addrDecWin)) ++ { ++ DB(mvOsPrintf("%s: ERR. targetWinGet fail\n", __FUNCTION__)); ++ return MV_ERROR; ++ } ++ ++ /* Check for overlapping */ ++ if (MV_TRUE == xorWinOverlapDetect(unit,winNum, &(addrDecWin.addrWin))) ++ { ++ /* Overlap detected */ ++ DB(mvOsPrintf("%s: ERR. Overlap detected\n", __FUNCTION__)); ++ return MV_ERROR; ++ } ++ ++ /* No Overlap. Enable address decode target window */ ++ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) ++ { ++ MV_REG_BIT_SET(XOR_WINDOW_CTRL_REG(unit,chan), ++ XEXWCR_WIN_EN_MASK(winNum)); ++ } ++ ++ } ++ else ++ { ++ /* Disable address decode target window */ ++ ++ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) ++ { ++ MV_REG_BIT_RESET(XOR_WINDOW_CTRL_REG(unit,chan), ++ XEXWCR_WIN_EN_MASK(winNum)); ++ } ++ ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvXorSetProtWinSet - Configure access attributes of a XOR engine ++* to one of the XOR memory windows. ++* ++* DESCRIPTION: ++* Each engine can be configured with access attributes for each of the ++* memory spaces. This function sets access attributes ++* to a given window for the given engine ++* ++* INPUTS: ++* chan - One of the possible engines. ++* winNum - One of the possible XOR memory spaces. ++* access - Protection access rights. ++* write - Write rights. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. ++* ++*******************************************************************************/ ++MV_STATUS mvXorProtWinSet (MV_U32 unit,MV_U32 chan, MV_U32 winNum, MV_BOOL access, ++ MV_BOOL write) ++{ ++ MV_U32 temp; ++ ++ /* Parameter checking */ ++ if (chan >= MV_XOR_MAX_CHAN_PER_UNIT) ++ { ++ DB(mvOsPrintf("%s: ERR. Invalid chan num %d\n", __FUNCTION__ , chan)); ++ return MV_BAD_PARAM; ++ } ++ if (winNum >= XOR_MAX_ADDR_DEC_WIN) ++ { ++ DB(mvOsPrintf("%s: ERR. Invalid win num %d\n", __FUNCTION__, winNum)); ++ return MV_BAD_PARAM; ++ } ++ ++ temp = MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,chan)) & ++ (~XEXWCR_WIN_ACC_MASK(winNum)); ++ ++ /* if access is disable */ ++ if (!access) ++ { ++ /* disable access */ ++ temp |= XEXWCR_WIN_ACC_NO_ACC(winNum); ++ } ++ /* if access is enable */ ++ else ++ { ++ /* if write is enable */ ++ if (write) ++ { ++ /* enable write */ ++ temp |= XEXWCR_WIN_ACC_RW(winNum); ++ } ++ /* if write is disable */ ++ else ++ { ++ /* disable write */ ++ temp |= XEXWCR_WIN_ACC_RO(winNum); ++ } ++ } ++ MV_REG_WRITE(XOR_WINDOW_CTRL_REG(unit,chan),temp); ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvXorPciRemap - Set XOR remap register for PCI address windows. ++* ++* DESCRIPTION: ++* only Windows 0-3 can be remapped. ++* ++* INPUT: ++* winNum - window number ++* pAddrDecWin - pointer to address space window structure ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise. ++* ++*******************************************************************************/ ++MV_STATUS mvXorPciRemap(MV_U32 unit,MV_U32 winNum, MV_U32 addrHigh) ++{ ++ /* Parameter checking */ ++ if (winNum >= XOR_MAX_REMAP_WIN) ++ { ++ DB(mvOsPrintf("%s: ERR. Invalid win num %d\n", __FUNCTION__, winNum)); ++ return MV_BAD_PARAM; ++ } ++ ++ MV_REG_WRITE(XOR_HIGH_ADDR_REMAP_REG(unit,winNum), addrHigh); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* xorWinOverlapDetect - Detect XOR address windows overlaping ++* ++* DESCRIPTION: ++* An unpredicted behaviour is expected in case XOR address decode ++* windows overlaps. ++* This function detects XOR address decode windows overlaping of a ++* specified window. The function does not check the window itself for ++* overlaping. The function also skipps disabled address decode windows. ++* ++* INPUT: ++* winNum - address decode window number. ++* pAddrDecWin - An address decode window struct. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the given address window overlap current address ++* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data ++* from registers. ++* ++*******************************************************************************/ ++static MV_STATUS xorWinOverlapDetect(MV_U32 unit,MV_U32 winNum, MV_ADDR_WIN *pAddrWin) ++{ ++ MV_U32 baseAddrEnableReg; ++ MV_U32 winNumIndex,chan; ++ MV_XOR_DEC_WIN addrDecWin; ++ ++ if (pAddrWin == NULL) ++ { ++ DB(mvOsPrintf("%s: ERR. pAddrWin is NULL pointer\n", __FUNCTION__ )); ++ return MV_BAD_PTR; ++ } ++ ++ for (chan = 0; chan < MV_XOR_MAX_CHAN_PER_UNIT; chan++) ++ { ++ /* Read base address enable register. Do not check disabled windows */ ++ baseAddrEnableReg = MV_REG_READ(XOR_WINDOW_CTRL_REG(unit,chan)); ++ ++ for (winNumIndex = 0; winNumIndex < XOR_MAX_ADDR_DEC_WIN; winNumIndex++) ++ { ++ /* Do not check window itself */ ++ if (winNumIndex == winNum) ++ { ++ continue; ++ } ++ ++ /* Do not check disabled windows */ ++ if ((baseAddrEnableReg & XEXWCR_WIN_EN_MASK(winNumIndex)) == 0) ++ { ++ continue; ++ } ++ ++ /* Get window parameters */ ++ if (MV_OK != mvXorTargetWinGet(unit,winNumIndex, &addrDecWin)) ++ { ++ DB(mvOsPrintf("%s: ERR. TargetWinGet failed\n", __FUNCTION__ )); ++ return MV_ERROR; ++ } ++ ++ if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin))) ++ { ++ return MV_TRUE; ++ } ++ } ++ } ++ ++ return MV_FALSE; ++} ++ ++static MV_VOID mvXorAddrDecShowUnit(MV_U32 unit) ++{ ++ MV_XOR_DEC_WIN win; ++ int i; ++ ++ mvOsOutput( "\n" ); ++ mvOsOutput( "XOR %d:\n", unit ); ++ mvOsOutput( "----\n" ); ++ ++ for( i = 0; i < XOR_MAX_ADDR_DEC_WIN; i++ ) ++ { ++ memset( &win, 0, sizeof(MV_XOR_DEC_WIN) ); ++ ++ mvOsOutput( "win%d - ", i ); ++ ++ if( mvXorTargetWinGet(unit, i, &win ) == MV_OK ) ++ { ++ if( win.enable ) ++ { ++ mvOsOutput( "%s base %x, ", ++ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow ); ++ ++ mvSizePrint( win.addrWin.size ); ++ ++ mvOsOutput( "\n" ); ++ } ++ else ++ mvOsOutput( "disable\n" ); ++ } ++ } ++} ++ ++/******************************************************************************* ++* mvXorAddrDecShow - Print the XOR address decode map. ++* ++* DESCRIPTION: ++* This function print the XOR address decode map. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID mvXorAddrDecShow(MV_VOID) ++{ ++ int i; ++ ++ for( i = 0; i < MV_XOR_MAX_UNIT; i++ ) ++ mvXorAddrDecShowUnit(i); ++ ++} +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/mvSysXor.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,140 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCMVSysXorh ++#define __INCMVSysXorh ++ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "ctrlEnv/sys/mvCpuIf.h" ++ ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "ctrlEnv/mvCtrlEnvAddrDec.h" ++ ++#define XOR_MAX_ADDR_DEC_WIN 8 /* Maximum address decode windows */ ++#define XOR_MAX_REMAP_WIN 4 /* Maximum address arbiter windows */ ++ ++/* XOR Engine Address Decoding Register Map */ ++#define XOR_WINDOW_CTRL_REG(unit,chan) (XOR_UNIT_BASE(unit)+(0x240 + ((chan) * 4))) ++#define XOR_BASE_ADDR_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x250 + ((winNum) * 4))) ++#define XOR_SIZE_MASK_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x270 + ((winNum) * 4))) ++#define XOR_HIGH_ADDR_REMAP_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x290 + ((winNum) * 4))) ++ ++/* XOR Engine [0..1] Window Control Registers (XExWCR) */ ++#define XEXWCR_WIN_EN_OFFS(winNum) (winNum) ++#define XEXWCR_WIN_EN_MASK(winNum) (1 << (XEXWCR_WIN_EN_OFFS(winNum))) ++#define XEXWCR_WIN_EN_ENABLE(winNum) (1 << (XEXWCR_WIN_EN_OFFS(winNum))) ++#define XEXWCR_WIN_EN_DISABLE(winNum) (0 << (XEXWCR_WIN_EN_OFFS(winNum))) ++ ++#define XEXWCR_WIN_ACC_OFFS(winNum) ((2 * winNum) + 16) ++#define XEXWCR_WIN_ACC_MASK(winNum) (3 << (XEXWCR_WIN_ACC_OFFS(winNum))) ++#define XEXWCR_WIN_ACC_NO_ACC(winNum) (0 << (XEXWCR_WIN_ACC_OFFS(winNum))) ++#define XEXWCR_WIN_ACC_RO(winNum) (1 << (XEXWCR_WIN_ACC_OFFS(winNum))) ++#define XEXWCR_WIN_ACC_RW(winNum) (3 << (XEXWCR_WIN_ACC_OFFS(winNum))) ++ ++/* XOR Engine Base Address Registers (XEBARx) */ ++#define XEBARX_TARGET_OFFS (0) ++#define XEBARX_TARGET_MASK (0xF << XEBARX_TARGET_OFFS) ++#define XEBARX_ATTR_OFFS (8) ++#define XEBARX_ATTR_MASK (0xFF << XEBARX_ATTR_OFFS) ++#define XEBARX_BASE_OFFS (16) ++#define XEBARX_BASE_MASK (0xFFFF << XEBARX_BASE_OFFS) ++ ++/* XOR Engine Size Mask Registers (XESMRx) */ ++#define XESMRX_SIZE_MASK_OFFS (16) ++#define XESMRX_SIZE_MASK_MASK (0xFFFF << XESMRX_SIZE_MASK_OFFS) ++ ++/* XOR Engine High Address Remap Register (XEHARRx1) */ ++#define XEHARRX_REMAP_OFFS (0) ++#define XEHARRX_REMAP_MASK (0xFFFFFFFF << XEHARRX_REMAP_OFFS) ++ ++typedef struct _mvXorDecWin ++{ ++ MV_TARGET target; ++ MV_ADDR_WIN addrWin; /* An address window*/ ++ MV_BOOL enable; /* Address decode window is enabled/disabled */ ++ ++}MV_XOR_DEC_WIN; ++ ++MV_STATUS mvXorInit (MV_VOID); ++MV_STATUS mvXorTargetWinSet(MV_U32 unit, MV_U32 winNum, ++ MV_XOR_DEC_WIN *pAddrDecWin); ++MV_STATUS mvXorTargetWinGet(MV_U32 unit, MV_U32 winNum, ++ MV_XOR_DEC_WIN *pAddrDecWin); ++MV_STATUS mvXorTargetWinEnable(MV_U32 unit, ++ MV_U32 winNum, MV_BOOL enable); ++MV_STATUS mvXorProtWinSet (MV_U32 unit,MV_U32 chan, MV_U32 winNum, MV_BOOL access, ++ MV_BOOL write); ++MV_STATUS mvXorPciRemap(MV_U32 unit, MV_U32 winNum, MV_U32 addrHigh); ++ ++MV_VOID mvXorAddrDecShow(MV_VOID); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.c linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.c +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,75 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#include "device/mvDevice.h" ++ ++/* defines */ ++#ifdef MV_DEBUG ++ #define DB(x) x ++#else ++ #define DB(x) ++#endif ++ ++ ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDevice.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,74 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvDeviceH ++#define __INCmvDeviceH ++ ++#include "mvCommon.h" ++#include "mvOs.h" ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++#include "device/mvDeviceRegs.h" ++ ++ ++#endif /* #ifndef __INCmvDeviceH */ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDeviceRegs.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDeviceRegs.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDeviceRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/device/mvDeviceRegs.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,101 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvDeviceRegsH ++#define __INCmvDeviceRegsH ++ ++#ifndef MV_ASMLANGUAGE ++#include "ctrlEnv/mvCtrlEnvLib.h" ++/* This enumerator describes the Marvell controller possible devices that */ ++/* can be connected to its device interface. */ ++typedef enum _mvDevice ++{ ++#if defined(MV_INCLUDE_DEVICE_CS0) ++ DEV_CS0 = 0, /* Device connected to dev CS[0] */ ++#endif ++#if defined(MV_INCLUDE_DEVICE_CS1) ++ DEV_CS1 = 1, /* Device connected to dev CS[1] */ ++#endif ++#if defined(MV_INCLUDE_DEVICE_CS2) ++ DEV_CS2 = 2, /* Device connected to dev CS[2] */ ++#endif ++#if defined(MV_INCLUDE_DEVICE_CS3) ++ DEV_CS3 = 3, /* Device connected to dev CS[2] */ ++#endif ++#if defined(MV_INCLUDE_DEVICE_CS4) ++ DEV_CS4 = 4, /* Device connected to BOOT dev */ ++#endif ++ MV_DEV_MAX_CS = MV_DEVICE_MAX_CS ++}MV_DEVICE; ++ ++ ++#endif /* MV_ASMLANGUAGE */ ++ ++ ++#define NAND_CTRL_REG 0x10470 ++ ++#define NAND_ACTCEBOOT_BIT BIT1 ++ ++ ++#endif /* #ifndef __INCmvDeviceRegsH */ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/mvCompVer.txt linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/mvCompVer.txt +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/kw_family/mvCompVer.txt 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/kw_family/mvCompVer.txt 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,4 @@ ++Global HAL Version: FEROCEON_HAL_3_1_7 ++Unit HAL Version: 3.1.5 ++Description: This component includes an implementation of the unit HAL drivers ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.c linux-3.1.4/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.c +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,211 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++*******************************************************************************/ ++/******************************************************************************* ++* mvOsCpuArchLib.c - Marvell CPU architecture library ++* ++* DESCRIPTION: ++* This library introduce Marvell API for OS dependent CPU architecture ++* APIs. This library introduce single CPU architecture services APKI ++* cross OS. ++* ++* DEPENDENCIES: ++* None. ++* ++*******************************************************************************/ ++ ++/* includes */ ++#include ++#include "mvOs.h" ++ ++static MV_U32 read_p15_c0 (void); ++ ++/* defines */ ++#define ARM_ID_REVISION_OFFS 0 ++#define ARM_ID_REVISION_MASK (0xf << ARM_ID_REVISION_OFFS) ++ ++#define ARM_ID_PART_NUM_OFFS 4 ++#define ARM_ID_PART_NUM_MASK (0xfff << ARM_ID_PART_NUM_OFFS) ++ ++#define ARM_ID_ARCH_OFFS 16 ++#define ARM_ID_ARCH_MASK (0xf << ARM_ID_ARCH_OFFS) ++ ++#define ARM_ID_VAR_OFFS 20 ++#define ARM_ID_VAR_MASK (0xf << ARM_ID_VAR_OFFS) ++ ++#define ARM_ID_ASCII_OFFS 24 ++#define ARM_ID_ASCII_MASK (0xff << ARM_ID_ASCII_OFFS) ++ ++ ++ ++void* mvOsIoCachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, ++ MV_U32 *memHandle) ++{ ++ void *p = kmalloc( size, GFP_KERNEL ); ++ *pPhyAddr = pci_map_single( osHandle, p, 0, PCI_DMA_BIDIRECTIONAL ); ++ return p; ++} ++void* mvOsIoUncachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, ++ MV_U32 *memHandle) ++{ ++ return pci_alloc_consistent( osHandle, size, (dma_addr_t *)pPhyAddr ); ++} ++ ++void mvOsIoUncachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, ++ MV_U32 memHandle) ++{ ++ return pci_free_consistent( osHandle, size, pVirtAddr, (dma_addr_t)phyAddr ); ++} ++ ++void mvOsIoCachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, ++ MV_U32 memHandle ) ++{ ++ return kfree( pVirtAddr ); ++} ++ ++int mvOsRand(void) ++{ ++ int rand; ++ get_random_bytes(&rand, sizeof(rand) ); ++ return rand; ++} ++ ++/******************************************************************************* ++* mvOsCpuVerGet() - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit CPU Revision ++* ++*******************************************************************************/ ++MV_U32 mvOsCpuRevGet( MV_VOID ) ++{ ++ return ((read_p15_c0() & ARM_ID_REVISION_MASK ) >> ARM_ID_REVISION_OFFS); ++} ++/******************************************************************************* ++* mvOsCpuPartGet() - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit CPU Part number ++* ++*******************************************************************************/ ++MV_U32 mvOsCpuPartGet( MV_VOID ) ++{ ++ return ((read_p15_c0() & ARM_ID_PART_NUM_MASK ) >> ARM_ID_PART_NUM_OFFS); ++} ++/******************************************************************************* ++* mvOsCpuArchGet() - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit CPU Architicture number ++* ++*******************************************************************************/ ++MV_U32 mvOsCpuArchGet( MV_VOID ) ++{ ++ return ((read_p15_c0() & ARM_ID_ARCH_MASK ) >> ARM_ID_ARCH_OFFS); ++} ++/******************************************************************************* ++* mvOsCpuVarGet() - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit CPU Variant number ++* ++*******************************************************************************/ ++MV_U32 mvOsCpuVarGet( MV_VOID ) ++{ ++ return ((read_p15_c0() & ARM_ID_VAR_MASK ) >> ARM_ID_VAR_OFFS); ++} ++/******************************************************************************* ++* mvOsCpuAsciiGet() - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit CPU Variant number ++* ++*******************************************************************************/ ++MV_U32 mvOsCpuAsciiGet( MV_VOID ) ++{ ++ return ((read_p15_c0() & ARM_ID_ASCII_MASK ) >> ARM_ID_ASCII_OFFS); ++} ++ ++ ++ ++/* ++static unsigned long read_p15_c0 (void) ++*/ ++/* read co-processor 15, register #0 (ID register) */ ++static MV_U32 read_p15_c0 (void) ++{ ++ MV_U32 value; ++ ++ __asm__ __volatile__( ++ "mrc p15, 0, %0, c0, c0, 0 @ read control reg\n" ++ : "=r" (value) ++ : ++ : "memory"); ++ ++ return value; ++} ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,423 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++*******************************************************************************/ ++#ifndef _MV_OS_LNX_H_ ++#define _MV_OS_LNX_H_ ++ ++ ++#ifdef __KERNEL__ ++/* for kernel space */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "dbg-trace.h" ++ ++extern void mv_early_printk(char *fmt,...); ++ ++#define MV_ASM __asm__ __volatile__ ++#define INLINE inline ++#define MV_TRC_REC TRC_REC ++#define mvOsPrintf printk ++#define mvOsEarlyPrintf mv_early_printk ++#define mvOsOutput printk ++#define mvOsSPrintf sprintf ++#define mvOsMalloc(_size_) kmalloc(_size_,GFP_ATOMIC) ++#define mvOsFree kfree ++#define mvOsMemcpy memcpy ++#define mvOsSleep(_mils_) mdelay(_mils_) ++#define mvOsTaskLock() ++#define mvOsTaskUnlock() ++#define strtol simple_strtoul ++#define mvOsDelay(x) mdelay(x) ++#define mvOsUDelay(x) udelay(x) ++#define mvCopyFromOs copy_from_user ++#define mvCopyToOs copy_to_user ++ ++ ++#include "mvTypes.h" ++#include "mvCommon.h" ++ ++#ifdef MV_NDEBUG ++#define mvOsAssert(cond) ++#else ++#define mvOsAssert(cond) { do { if(!(cond)) { BUG(); } }while(0); } ++#endif /* MV_NDEBUG */ ++ ++#else /* __KERNEL__ */ ++ ++/* for user space applications */ ++#include ++#include ++#include ++#include ++ ++#define INLINE inline ++#define mvOsPrintf printf ++#define mvOsOutput printf ++#define mvOsMalloc(_size_) malloc(_size_) ++#define mvOsFree free ++#define mvOsAssert(cond) assert(cond) ++ ++#endif /* __KERNEL__ */ ++#define mvOsIoVirtToPhy(pDev, pVirtAddr) \ ++ pci_map_single( (pDev), (pVirtAddr), 0, PCI_DMA_BIDIRECTIONAL ) ++ ++#define mvOsCacheClear(pDev, p, size ) \ ++ pci_map_single( (pDev), (p), (size), PCI_DMA_BIDIRECTIONAL) ++ ++#define mvOsCacheFlush(pDev, p, size ) \ ++ pci_map_single( (pDev), (p), (size), PCI_DMA_TODEVICE) ++ ++#define mvOsCacheInvalidate(pDev, p, size) \ ++ pci_map_single( (pDev), (p), (size), PCI_DMA_FROMDEVICE ) ++ ++#define mvOsCacheUnmap(pDev, phys, size) \ ++ pci_unmap_single( (pDev), (dma_addr_t)(phys), (size), PCI_DMA_FROMDEVICE ) ++ ++ ++#define CPU_PHY_MEM(x) (MV_U32)x ++#define CPU_MEMIO_CACHED_ADDR(x) (void*)x ++#define CPU_MEMIO_UNCACHED_ADDR(x) (void*)x ++ ++ ++/* CPU architecture dependent 32, 16, 8 bit read/write IO addresses */ ++#define MV_MEMIO32_WRITE(addr, data) \ ++ ((*((volatile unsigned int*)(addr))) = ((unsigned int)(data))) ++ ++#define MV_MEMIO32_READ(addr) \ ++ ((*((volatile unsigned int*)(addr)))) ++ ++#define MV_MEMIO16_WRITE(addr, data) \ ++ ((*((volatile unsigned short*)(addr))) = ((unsigned short)(data))) ++ ++#define MV_MEMIO16_READ(addr) \ ++ ((*((volatile unsigned short*)(addr)))) ++ ++#define MV_MEMIO8_WRITE(addr, data) \ ++ ((*((volatile unsigned char*)(addr))) = ((unsigned char)(data))) ++ ++#define MV_MEMIO8_READ(addr) \ ++ ((*((volatile unsigned char*)(addr)))) ++ ++ ++/* No Fast Swap implementation (in assembler) for ARM */ ++#define MV_32BIT_LE_FAST(val) MV_32BIT_LE(val) ++#define MV_16BIT_LE_FAST(val) MV_16BIT_LE(val) ++#define MV_32BIT_BE_FAST(val) MV_32BIT_BE(val) ++#define MV_16BIT_BE_FAST(val) MV_16BIT_BE(val) ++ ++/* 32 and 16 bit read/write in big/little endian mode */ ++ ++/* 16bit write in little endian mode */ ++#define MV_MEMIO_LE16_WRITE(addr, data) \ ++ MV_MEMIO16_WRITE(addr, MV_16BIT_LE_FAST(data)) ++ ++/* 16bit read in little endian mode */ ++static __inline MV_U16 MV_MEMIO_LE16_READ(MV_U32 addr) ++{ ++ MV_U16 data; ++ ++ data= (MV_U16)MV_MEMIO16_READ(addr); ++ ++ return (MV_U16)MV_16BIT_LE_FAST(data); ++} ++ ++/* 32bit write in little endian mode */ ++#define MV_MEMIO_LE32_WRITE(addr, data) \ ++ MV_MEMIO32_WRITE(addr, MV_32BIT_LE_FAST(data)) ++ ++/* 32bit read in little endian mode */ ++static __inline MV_U32 MV_MEMIO_LE32_READ(MV_U32 addr) ++{ ++ MV_U32 data; ++ ++ data= (MV_U32)MV_MEMIO32_READ(addr); ++ ++ return (MV_U32)MV_32BIT_LE_FAST(data); ++} ++ ++static __inline void mvOsBCopy(char* srcAddr, char* dstAddr, int byteCount) ++{ ++ while(byteCount != 0) ++ { ++ *dstAddr = *srcAddr; ++ dstAddr++; ++ srcAddr++; ++ byteCount--; ++ } ++} ++ ++static INLINE MV_U64 mvOsDivMod64(MV_U64 divided, MV_U64 divisor, MV_U64* modulu) ++{ ++ MV_U64 division = 0; ++ ++ if(divisor == 1) ++ return divided; ++ ++ while(divided >= divisor) ++ { ++ division++; ++ divided -= divisor; ++ } ++ if (modulu != NULL) ++ *modulu = divided; ++ ++ return division; ++} ++ ++#if defined(MV_BRIDGE_SYNC_REORDER) ++extern MV_U32 *mvUncachedParam; ++ ++static __inline void mvOsBridgeReorderWA(void) ++{ ++ volatile MV_U32 val = 0; ++ ++ val = mvUncachedParam[0]; ++} ++#endif ++ ++ ++/* Flash APIs */ ++#define MV_FL_8_READ MV_MEMIO8_READ ++#define MV_FL_16_READ MV_MEMIO_LE16_READ ++#define MV_FL_32_READ MV_MEMIO_LE32_READ ++#define MV_FL_8_DATA_READ MV_MEMIO8_READ ++#define MV_FL_16_DATA_READ MV_MEMIO16_READ ++#define MV_FL_32_DATA_READ MV_MEMIO32_READ ++#define MV_FL_8_WRITE MV_MEMIO8_WRITE ++#define MV_FL_16_WRITE MV_MEMIO_LE16_WRITE ++#define MV_FL_32_WRITE MV_MEMIO_LE32_WRITE ++#define MV_FL_8_DATA_WRITE MV_MEMIO8_WRITE ++#define MV_FL_16_DATA_WRITE MV_MEMIO16_WRITE ++#define MV_FL_32_DATA_WRITE MV_MEMIO32_WRITE ++ ++ ++/* CPU cache information */ ++#define CPU_I_CACHE_LINE_SIZE 32 /* 2do: replace 32 with linux core macro */ ++#define CPU_D_CACHE_LINE_SIZE 32 /* 2do: replace 32 with linux core macro */ ++ ++#ifdef CONFIG_L2_CACHE_ENABLE ++/* Data cache flush one line */ ++#define mvOsCacheLineFlushInv(handle, addr) \ ++{ \ ++ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c14, 1" : : "r" (addr));\ ++ __asm__ __volatile__ ("mcr p15, 1, %0, c15, c10, 1" : : "r" (addr));\ ++ __asm__ __volatile__ ("mcr p15, 0, r0, c7, c10, 4"); \ ++} ++ ++#else ++ ++/* Data cache flush one line */ ++#define mvOsCacheLineFlushInv(handle, addr) \ ++{ \ ++ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c14, 1" : : "r" (addr));\ ++ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" : : "r" (addr)); \ ++} ++#endif ++ ++#ifdef CONFIG_L2_CACHE_ENABLE ++#define mvOsCacheLineInv(handle,addr) \ ++{ \ ++ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c6, 1" : : "r" (addr)); \ ++ __asm__ __volatile__ ("mcr p15, 1, %0, c15, c11, 1" : : "r" (addr)); \ ++} ++#else ++#define mvOsCacheLineInv(handle,addr) \ ++{ \ ++ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c6, 1" : : "r" (addr)); \ ++} ++#endif ++ ++#ifdef CONFIG_L2_CACHE_ENABLE ++/* Data cache flush one line */ ++#define mvOsCacheLineFlush(handle, addr) \ ++{ \ ++ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 1" : : "r" (addr));\ ++ __asm__ __volatile__ ("mcr p15, 1, %0, c15, c9, 1" : : "r" (addr));\ ++ __asm__ __volatile__ ("mcr p15, 0, r0, c7, c10, 4"); \ ++} ++ ++#else ++/* Data cache flush one line */ ++#define mvOsCacheLineFlush(handle, addr) \ ++{ \ ++ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 1" : : "r" (addr));\ ++ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" : : "r" (addr)); \ ++} ++#endif ++ ++static __inline void mvOsPrefetch(const void *ptr) ++{ ++#ifdef CONFIG_USE_DSP ++ __asm__ __volatile__( ++ "pld\t%0" ++ : ++ : "o" (*(char *)ptr) ++ : "cc"); ++#else ++ return; ++#endif ++} ++ ++ ++/* Flush CPU pipe */ ++#define CPU_PIPE_FLUSH ++ ++ ++ ++ ++ ++/* register manipulations */ ++ ++/****************************************************************************** ++* This debug function enable the write of each register that u-boot access to ++* to an array in the DRAM, the function record only MV_REG_WRITE access. ++* The function could not be operate when booting from flash. ++* In order to print the array we use the printreg command. ++******************************************************************************/ ++/* #define REG_DEBUG */ ++#if defined(REG_DEBUG) ++extern int reg_arry[2048][2]; ++extern int reg_arry_index; ++#endif ++ ++/* Marvell controller register read/write macros */ ++#define MV_REG_VALUE(offset) \ ++ (MV_MEMIO32_READ((INTER_REGS_BASE | (offset)))) ++ ++#define MV_REG_READ(offset) \ ++ (MV_MEMIO_LE32_READ(INTER_REGS_BASE | (offset))) ++ ++#if defined(REG_DEBUG) ++#define MV_REG_WRITE(offset, val) \ ++ MV_MEMIO_LE32_WRITE((INTER_REGS_BASE | (offset)), (val)); \ ++ { \ ++ reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\ ++ reg_arry[reg_arry_index][1] = (val);\ ++ reg_arry_index++;\ ++ } ++#else ++#define MV_REG_WRITE(offset, val) \ ++ MV_MEMIO_LE32_WRITE((INTER_REGS_BASE | (offset)), (val)); ++#endif ++ ++#define MV_REG_BYTE_READ(offset) \ ++ (MV_MEMIO8_READ((INTER_REGS_BASE | (offset)))) ++ ++#if defined(REG_DEBUG) ++#define MV_REG_BYTE_WRITE(offset, val) \ ++ MV_MEMIO8_WRITE((INTER_REGS_BASE | (offset)), (val)); \ ++ { \ ++ reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\ ++ reg_arry[reg_arry_index][1] = (val);\ ++ reg_arry_index++;\ ++ } ++#else ++#define MV_REG_BYTE_WRITE(offset, val) \ ++ MV_MEMIO8_WRITE((INTER_REGS_BASE | (offset)), (val)) ++#endif ++ ++#if defined(REG_DEBUG) ++#define MV_REG_BIT_SET(offset, bitMask) \ ++ (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ ++ (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) | \ ++ MV_32BIT_LE_FAST(bitMask)))); \ ++ { \ ++ reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\ ++ reg_arry[reg_arry_index][1] = (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)));\ ++ reg_arry_index++;\ ++ } ++#else ++#define MV_REG_BIT_SET(offset, bitMask) \ ++ (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ ++ (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) | \ ++ MV_32BIT_LE_FAST(bitMask)))) ++#endif ++ ++#if defined(REG_DEBUG) ++#define MV_REG_BIT_RESET(offset,bitMask) \ ++ (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ ++ (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) & \ ++ MV_32BIT_LE_FAST(~bitMask)))); \ ++ { \ ++ reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\ ++ reg_arry[reg_arry_index][1] = (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)));\ ++ reg_arry_index++;\ ++ } ++#else ++#define MV_REG_BIT_RESET(offset,bitMask) \ ++ (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \ ++ (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) & \ ++ MV_32BIT_LE_FAST(~bitMask)))) ++#endif ++ ++ ++ ++/* ARM architecture APIs */ ++MV_U32 mvOsCpuRevGet (MV_VOID); ++MV_U32 mvOsCpuPartGet (MV_VOID); ++MV_U32 mvOsCpuArchGet (MV_VOID); ++MV_U32 mvOsCpuVarGet (MV_VOID); ++MV_U32 mvOsCpuAsciiGet (MV_VOID); ++ ++/* Other APIs */ ++void* mvOsIoCachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, MV_U32 *memHandle); ++void* mvOsIoUncachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, MV_U32 *memHandle ); ++void mvOsIoUncachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, MV_U32 memHandle ); ++void mvOsIoCachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, MV_U32 memHandle ); ++int mvOsRand(void); ++ ++#endif /* _MV_OS_LNX_H_ */ ++ ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOsSata.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/linux_oss/mvOsSata.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/linux_oss/mvOsSata.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/linux_oss/mvOsSata.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,158 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++*******************************************************************************/ ++/******************************************************************************* ++* mvOsLinux.h - O.S. interface header file for Linux ++* ++* DESCRIPTION: ++* This header file contains OS dependent definition under Linux ++* ++* DEPENDENCIES: ++* Linux kernel header files. ++* ++* FILE REVISION NUMBER: ++* $Revision: 1.1 $ ++*******************************************************************************/ ++ ++#ifndef __INCmvOsLinuxh ++#define __INCmvOsLinuxh ++ ++/* Includes */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include "mvOs.h" ++ ++ ++/* Definitions */ ++#define MV_DEFAULT_QUEUE_DEPTH 2 ++#define MV_SATA_SUPPORT_EDMA_SINGLE_DATA_REGION ++#define MV_SATA_SUPPORT_GEN2E_128_QUEUE_LEN ++ ++#ifdef CONFIG_MV88F6082 ++ #define MV_SATA_OVERRIDE_SW_QUEUE_SIZE ++ #define MV_SATA_REQUESTED_SW_QUEUE_SIZE 2 ++ #undef MV_SATA_SUPPORT_GEN2E_128_QUEUE_LEN ++#endif ++ ++/* System dependent macro for flushing CPU write cache */ ++#if defined (MV_BRIDGE_SYNC_REORDER) ++#define MV_CPU_WRITE_BUFFER_FLUSH() do { \ ++ wmb(); \ ++ mvOsBridgeReorderWA(); \ ++ } while (0) ++#else ++#define MV_CPU_WRITE_BUFFER_FLUSH() wmb() ++#endif /* CONFIG_MV78XX0 */ ++ ++/* System dependent little endian from / to CPU conversions */ ++#define MV_CPU_TO_LE16(x) cpu_to_le16(x) ++#define MV_CPU_TO_LE32(x) cpu_to_le32(x) ++ ++#define MV_LE16_TO_CPU(x) le16_to_cpu(x) ++#define MV_LE32_TO_CPU(x) le32_to_cpu(x) ++ ++#ifdef __BIG_ENDIAN_BITFIELD ++#define MV_BIG_ENDIAN_BITFIELD ++#endif ++ ++/* System dependent register read / write in byte/word/dword variants */ ++#define MV_REG_WRITE_BYTE(base, offset, val) writeb(val, base + offset) ++#define MV_REG_WRITE_WORD(base, offset, val) writew(val, base + offset) ++#define MV_REG_WRITE_DWORD(base, offset, val) writel(val, base + offset) ++#define MV_REG_READ_BYTE(base, offset) readb(base + offset) ++#define MV_REG_READ_WORD(base, offset) readw(base + offset) ++#define MV_REG_READ_DWORD(base, offset) readl(base + offset) ++ ++ ++/* Typedefs */ ++ ++/* System dependant typedefs */ ++typedef void *MV_VOID_PTR; ++typedef u32 *MV_U32_PTR; ++typedef u16 *MV_U16_PTR; ++typedef u8 *MV_U8_PTR; ++typedef char *MV_CHAR_PTR; ++typedef void *MV_BUS_ADDR_T; ++typedef unsigned long MV_CPU_FLAGS; ++ ++ ++/* Structures */ ++/* System dependent structure */ ++typedef struct mvOsSemaphore ++{ ++ int notUsed; ++} MV_OS_SEMAPHORE; ++ ++ ++/* Functions (User implemented)*/ ++ ++/* Semaphore init, take and release */ ++#define mvOsSemInit(x) MV_TRUE ++#define mvOsSemTake(x) ++#define mvOsSemRelease(x) ++ ++/* Interrupt masking and unmasking functions */ ++MV_CPU_FLAGS mvOsSaveFlagsAndMaskCPUInterrupts(MV_VOID); ++MV_VOID mvOsRestoreFlags(MV_CPU_FLAGS); ++ ++/* Delay function in micro seconds resolution */ ++void mvMicroSecondsDelay(MV_VOID_PTR, MV_U32); ++ ++/* Typedefs */ ++typedef enum mvBoolean ++{ ++ MV_SFALSE, MV_STRUE ++} MV_BOOLEAN; ++ ++/* System logging function */ ++#include "mvLog.h" ++/* Enable READ/WRITE Long SCSI command only when driver is compiled for debugging */ ++#ifdef MV_LOGGER ++#define MV_SATA_SUPPORT_READ_WRITE_LONG ++#endif ++ ++#define MV_IAL_LOG_ID 3 ++ ++#endif /* __INCmvOsLinuxh */ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mvSysHwConfig.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/mvSysHwConfig.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mvSysHwConfig.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mvSysHwConfig.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,375 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++ ++*******************************************************************************/ ++/******************************************************************************* ++* mvSysHwCfg.h - Marvell system HW configuration file ++* ++* DESCRIPTION: ++* None. ++* ++* DEPENDENCIES: ++* None. ++* ++*******************************************************************************/ ++ ++#ifndef __INCmvSysHwConfigh ++#define __INCmvSysHwConfigh ++ ++#include "../../../../include/linux/autoconf.h" ++ ++#define CONFIG_MARVELL 1 ++ ++/* includes */ ++#define _1K 0x00000400 ++#define _4K 0x00001000 ++#define _8K 0x00002000 ++#define _16K 0x00004000 ++#define _32K 0x00008000 ++#define _64K 0x00010000 ++#define _128K 0x00020000 ++#define _256K 0x00040000 ++#define _512K 0x00080000 ++ ++#define _1M 0x00100000 ++#define _2M 0x00200000 ++#define _4M 0x00400000 ++#define _8M 0x00800000 ++#define _16M 0x01000000 ++#define _32M 0x02000000 ++#define _64M 0x04000000 ++#define _128M 0x08000000 ++#define _256M 0x10000000 ++#define _512M 0x20000000 ++ ++#define _1G 0x40000000 ++#define _2G 0x80000000 ++ ++/****************************************/ ++/* Soc supporeted Units definitions */ ++/****************************************/ ++ ++#ifdef CONFIG_MV_INCLUDE_PEX ++#define MV_INCLUDE_PEX ++#endif ++#ifdef CONFIG_MV_INCLUDE_TWSI ++#define MV_INCLUDE_TWSI ++#endif ++#ifdef CONFIG_MV_INCLUDE_CESA ++#define MV_INCLUDE_CESA ++#endif ++#ifdef CONFIG_MV_INCLUDE_GIG_ETH ++#define MV_INCLUDE_GIG_ETH ++#endif ++#ifdef CONFIG_MV_INCLUDE_INTEG_SATA ++#define MV_INCLUDE_INTEG_SATA ++#define MV_INCLUDE_SATA ++#endif ++#ifdef CONFIG_MV_INCLUDE_USB ++#define MV_INCLUDE_USB ++#define MV_USB_VOLTAGE_FIX ++#endif ++#ifdef CONFIG_MV_INCLUDE_NAND ++#define MV_INCLUDE_NAND ++#endif ++#ifdef CONFIG_MV_INCLUDE_TDM ++#define MV_INCLUDE_TDM ++#endif ++#ifdef CONFIG_MV_INCLUDE_XOR ++#define MV_INCLUDE_XOR ++#endif ++#ifdef CONFIG_MV_INCLUDE_TWSI ++#define MV_INCLUDE_TWSI ++#endif ++#ifdef CONFIG_MV_INCLUDE_UART ++#define MV_INCLUDE_UART ++#endif ++#ifdef CONFIG_MV_INCLUDE_SPI ++#define MV_INCLUDE_SPI ++#endif ++#ifdef CONFIG_MV_INCLUDE_SFLASH_MTD ++#define MV_INCLUDE_SFLASH_MTD ++#endif ++#ifdef CONFIG_MV_INCLUDE_AUDIO ++#define MV_INCLUDE_AUDIO ++#endif ++#ifdef CONFIG_MV_INCLUDE_TS ++#define MV_INCLUDE_TS ++#endif ++#ifdef CONFIG_MV_INCLUDE_SDIO ++#define MV_INCLUDE_SDIO ++#endif ++ ++ ++/* NAND flash stuff */ ++#ifdef CONFIG_MV_NAND_BOOT ++#define MV_NAND_BOOT ++#endif ++#ifdef CONFIG_MV_NAND ++#define MV_NAND ++#endif ++ ++/* SPI flash stuff */ ++#ifdef CONFIG_MV_SPI_BOOT ++#define MV_SPI_BOOT ++#endif ++ ++ ++/****************************************************************/ ++/************* General configuration ********************/ ++/****************************************************************/ ++ ++/* Enable Clock Power Control */ ++#define MV_INCLUDE_CLK_PWR_CNTRL ++ ++/* Disable the DEVICE BAR in the PEX */ ++#define MV_DISABLE_PEX_DEVICE_BAR ++ ++/* Allow the usage of early printings during initialization */ ++#define MV_INCLUDE_EARLY_PRINTK ++ ++/****************************************************************/ ++/************* NFP configuration ********************************/ ++/****************************************************************/ ++#define MV_NFP_SEC_Q_SIZE 64 ++#define MV_NFP_SEC_REQ_Q_SIZE 1000 ++ ++ ++ ++/****************************************************************/ ++/************* CESA configuration ********************/ ++/****************************************************************/ ++ ++#ifdef MV_INCLUDE_CESA ++ ++#define MV_CESA_MAX_CHAN 4 ++ ++/* Use 2K of SRAM */ ++#define MV_CESA_MAX_BUF_SIZE 1600 ++ ++#endif /* MV_INCLUDE_CESA */ ++ ++#if defined(CONFIG_MV_INCLUDE_GIG_ETH) ++ ++#ifdef CONFIG_MV_NFP_STATS ++#define MV_FP_STATISTICS ++#else ++#undef MV_FP_STATISTICS ++#endif ++/* Default configuration for SKB_REUSE: 0 - Disabled, 1 - Enabled */ ++#define MV_ETH_SKB_REUSE_DEFAULT 1 ++/* Default configuration for TX_EN workaround: 0 - Disabled, 1 - Enabled */ ++#define MV_ETH_TX_EN_DEFAULT 0 ++ ++/* un-comment if you want to perform tx_done from within the poll function */ ++/* #define ETH_TX_DONE_ISR */ ++ ++/* put descriptors in uncached memory */ ++/* #define ETH_DESCR_UNCACHED */ ++ ++/* Descriptors location: DRAM/internal-SRAM */ ++#define ETH_DESCR_IN_SDRAM ++#undef ETH_DESCR_IN_SRAM /* No integrated SRAM in 88Fxx81 devices */ ++ ++#if defined(ETH_DESCR_IN_SRAM) ++#if defined(ETH_DESCR_UNCACHED) ++ #define ETH_DESCR_CONFIG_STR "Uncached descriptors in integrated SRAM" ++#else ++ #define ETH_DESCR_CONFIG_STR "Cached descriptors in integrated SRAM" ++#endif ++#elif defined(ETH_DESCR_IN_SDRAM) ++#if defined(ETH_DESCR_UNCACHED) ++ #define ETH_DESCR_CONFIG_STR "Uncached descriptors in DRAM" ++#else ++ #define ETH_DESCR_CONFIG_STR "Cached descriptors in DRAM" ++#endif ++#else ++ #error "Ethernet descriptors location undefined" ++#endif /* ETH_DESCR_IN_SRAM or ETH_DESCR_IN_SDRAM*/ ++ ++/* SW Sync-Barrier: not relevant for 88fxx81*/ ++/* Reasnable to define this macro when descriptors in SRAM and buffers in DRAM */ ++/* In RX the CPU theoretically might see himself as the descriptor owner, */ ++/* although the buffer hadn't been written to DRAM yet. Performance cost. */ ++/* #define INCLUDE_SYNC_BARR */ ++ ++/* Buffers cache coherency method (buffers in DRAM) */ ++#ifndef MV_CACHE_COHER_SW ++/* Taken from mvCommon.h */ ++/* Memory uncached, HW or SW cache coherency is not needed */ ++#define MV_UNCACHED 0 ++/* Memory cached, HW cache coherency supported in WriteThrough mode */ ++#define MV_CACHE_COHER_HW_WT 1 ++/* Memory cached, HW cache coherency supported in WriteBack mode */ ++#define MV_CACHE_COHER_HW_WB 2 ++/* Memory cached, No HW cache coherency, Cache coherency must be in SW */ ++#define MV_CACHE_COHER_SW 3 ++ ++#endif ++ ++/* DRAM cache coherency configuration */ ++#define MV_CACHE_COHERENCY MV_CACHE_COHER_SW ++ ++ ++#define ETHER_DRAM_COHER MV_CACHE_COHER_SW /* No HW coherency in 88Fxx81 devices */ ++ ++#if (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WB) ++ #define ETH_SDRAM_CONFIG_STR "DRAM HW cache coherency (write-back)" ++#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WT) ++ #define ETH_SDRAM_CONFIG_STR "DRAM HW cache coherency (write-through)" ++#elif (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) ++ #define ETH_SDRAM_CONFIG_STR "DRAM SW cache-coherency" ++#elif (ETHER_DRAM_COHER == MV_UNCACHED) ++# define ETH_SDRAM_CONFIG_STR "DRAM uncached" ++#else ++ #error "Ethernet-DRAM undefined" ++#endif /* ETHER_DRAM_COHER */ ++ ++ ++/****************************************************************/ ++/************* Ethernet driver configuration ********************/ ++/****************************************************************/ ++ ++/* port's default queueus */ ++#define ETH_DEF_TXQ 0 ++#define ETH_DEF_RXQ 0 ++ ++#define MV_ETH_RX_Q_NUM CONFIG_MV_ETH_RX_Q_NUM ++#define MV_ETH_TX_Q_NUM CONFIG_MV_ETH_TX_Q_NUM ++ ++/* interrupt coalescing setting */ ++#define ETH_TX_COAL 200 ++#define ETH_RX_COAL 200 ++ ++/* Checksum offloading */ ++#define TX_CSUM_OFFLOAD ++#define RX_CSUM_OFFLOAD ++ ++#endif /* CONFIG_MV_INCLUDE_GIG_ETH */ ++ ++/****************************************************************/ ++/*************** Telephony configuration ************************/ ++/****************************************************************/ ++#if defined(CONFIG_MV_TDM_LINEAR_MODE) ++ #define MV_TDM_LINEAR_MODE ++#elif defined(CONFIG_MV_TDM_ULAW_MODE) ++ #define MV_TDM_ULAW_MODE ++#endif ++ ++#if defined(CONFIG_MV_TDM_5CHANNELS) ++ #define MV_TDM_5CHANNELS ++#endif ++ ++#if defined(CONFIG_MV_TDM_USE_EXTERNAL_PCLK_SOURCE) ++ #define MV_TDM_USE_EXTERNAL_PCLK_SOURCE ++#endif ++ ++/* We use the following registers to store DRAM interface pre configuration */ ++/* auto-detection results */ ++/* IMPORTANT: We are using mask register for that purpose. Before writing */ ++/* to units mask register, make sure main maks register is set to disable */ ++/* all interrupts. */ ++#define DRAM_BUF_REG0 0x30810 /* sdram bank 0 size */ ++#define DRAM_BUF_REG1 0x30820 /* sdram config */ ++#define DRAM_BUF_REG2 0x30830 /* sdram mode */ ++#define DRAM_BUF_REG3 0x308c4 /* dunit control low */ ++#define DRAM_BUF_REG4 0x60a90 /* sdram address control */ ++#define DRAM_BUF_REG5 0x60a94 /* sdram timing control low */ ++#define DRAM_BUF_REG6 0x60a98 /* sdram timing control high */ ++#define DRAM_BUF_REG7 0x60a9c /* sdram ODT control low */ ++#define DRAM_BUF_REG8 0x60b90 /* sdram ODT control high */ ++#define DRAM_BUF_REG9 0x60b94 /* sdram Dunit ODT control */ ++#define DRAM_BUF_REG10 0x60b98 /* sdram Extended Mode */ ++#define DRAM_BUF_REG11 0x60b9c /* sdram Ddr2 Time Low Reg */ ++#define DRAM_BUF_REG12 0x60a00 /* sdram Ddr2 Time High Reg */ ++#define DRAM_BUF_REG13 0x60a04 /* dunit Ctrl High */ ++#define DRAM_BUF_REG14 0x60b00 /* sdram second DIMM exist */ ++ ++/* Following the pre-configuration registers default values restored after */ ++/* auto-detection is done */ ++#define DRAM_BUF_REG_DV 0 ++ ++/* System Mapping */ ++#define SDRAM_CS0_BASE 0x00000000 ++#define SDRAM_CS0_SIZE _256M ++ ++#define SDRAM_CS1_BASE 0x10000000 ++#define SDRAM_CS1_SIZE _256M ++ ++#define SDRAM_CS2_BASE 0x20000000 ++#define SDRAM_CS2_SIZE _256M ++ ++#define SDRAM_CS3_BASE 0x30000000 ++#define SDRAM_CS3_SIZE _256M ++ ++/* PEX */ ++#define PEX0_MEM_BASE 0xe8000000 ++#define PEX0_MEM_SIZE _128M ++ ++#define PEX0_IO_BASE 0xf2000000 ++#define PEX0_IO_SIZE _1M ++ ++/* Device Chip Selects */ ++#define NFLASH_CS_BASE 0xfa000000 ++#define NFLASH_CS_SIZE _2M ++ ++#define SPI_CS_BASE 0xf4000000 ++#define SPI_CS_SIZE _16M ++ ++#define CRYPT_ENG_BASE 0xf0000000 ++#define CRYPT_ENG_SIZE _2M ++ ++#define BOOTDEV_CS_BASE 0xff800000 ++#define BOOTDEV_CS_SIZE _8M ++ ++/* CS2 - BOOTROM */ ++#define DEVICE_CS2_BASE 0xff900000 ++#define DEVICE_CS2_SIZE _1M ++ ++/* PEX Work arround */ ++/* the target we will use for the workarround */ ++#define PEX_CONFIG_RW_WA_TARGET PEX0_MEM ++/*a flag that indicates if we are going to use the ++size and base of the target we using for the workarround ++window */ ++#define PEX_CONFIG_RW_WA_USE_ORIGINAL_WIN_VALUES 1 ++/* if the above flag is 0 then the following values ++will be used for the workarround window base and size, ++otherwise the following defines will be ignored */ ++#define PEX_CONFIG_RW_WA_BASE 0xF3000000 ++#define PEX_CONFIG_RW_WA_SIZE _16M ++ ++/* Internal registers: size is defined in Controllerenvironment */ ++#define INTER_REGS_BASE 0xFEE00000 ++ ++/* DRAM detection stuff */ ++#define MV_DRAM_AUTO_SIZE ++ ++/* Board clock detection */ ++#define TCLK_AUTO_DETECT /* Use Tclk auto detection */ ++#define SYSCLK_AUTO_DETECT /* Use SysClk auto detection */ ++#define PCLCK_AUTO_DETECT /* Use PClk auto detection */ ++#define L2CLK_AUTO_DETECT /* Use L2Clk auto detection */ ++ ++/* PEX-PCI\PCI-PCI Bridge*/ ++#define PCI0_IF_PTP 0 /* Bridge exist on pciIf0*/ ++ ++ ++ ++#endif /* __INCmvSysHwConfigh */ ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.c linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.c +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,376 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#include "mvCntmr.h" ++#include "cpu/mvCpu.h" ++ ++/* defines */ ++#ifdef MV_DEBUG ++ #define DB(x) x ++#else ++ #define DB(x) ++#endif ++ ++extern unsigned int whoAmI(void); ++ ++/******************************************************************************* ++* mvCntmrLoad - ++* ++* DESCRIPTION: ++* Load an init Value to a given counter/timer ++* ++* INPUT: ++* countNum - counter number ++* value - value to be loaded ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess ++*******************************************************************************/ ++MV_STATUS mvCntmrLoad(MV_U32 countNum, MV_U32 value) ++{ ++ if (countNum >= MV_CNTMR_MAX_COUNTER ) ++ { ++ ++ mvOsPrintf(("mvCntmrLoad: Err. Illigal counter number \n")); ++ return MV_BAD_PARAM;; ++ ++ } ++ ++ MV_REG_WRITE(CNTMR_RELOAD_REG(countNum),value); ++ MV_REG_WRITE(CNTMR_VAL_REG(countNum),value); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCntmrRead - ++* ++* DESCRIPTION: ++* Returns the value of the given Counter/Timer ++* ++* INPUT: ++* countNum - counter number ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_U32 counter value ++*******************************************************************************/ ++MV_U32 mvCntmrRead(MV_U32 countNum) ++{ ++ return MV_REG_READ(CNTMR_VAL_REG(countNum)); ++} ++ ++/******************************************************************************* ++* mvCntmrWrite - ++* ++* DESCRIPTION: ++* Returns the value of the given Counter/Timer ++* ++* INPUT: ++* countNum - counter number ++* countVal - value to write ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None ++*******************************************************************************/ ++void mvCntmrWrite(MV_U32 countNum,MV_U32 countVal) ++{ ++ MV_REG_WRITE(CNTMR_VAL_REG(countNum),countVal); ++} ++ ++/******************************************************************************* ++* mvCntmrCtrlSet - ++* ++* DESCRIPTION: ++* Set the Control to a given counter/timer ++* ++* INPUT: ++* countNum - counter number ++* pCtrl - pointer to MV_CNTMR_CTRL structure ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess ++*******************************************************************************/ ++MV_STATUS mvCntmrCtrlSet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl) ++{ ++ MV_U32 cntmrCtrl; ++ ++ if (countNum >= MV_CNTMR_MAX_COUNTER ) ++ { ++ ++ DB(mvOsPrintf(("mvCntmrCtrlSet: Err. Illigal counter number \n"))); ++ return MV_BAD_PARAM;; ++ ++ } ++ ++ /* read control register */ ++ cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG); ++ ++ ++ if (pCtrl->enable) /* enable counter\timer */ ++ { ++ cntmrCtrl |= CTCR_ARM_TIMER_EN(countNum); ++ } ++ else /* disable counter\timer */ ++ { ++ cntmrCtrl &= ~CTCR_ARM_TIMER_EN(countNum); ++ } ++ ++ if ( pCtrl->autoEnable ) /* Auto mode */ ++ { ++ cntmrCtrl |= CTCR_ARM_TIMER_AUTO_EN(countNum); ++ ++ } ++ else /* no auto mode */ ++ { ++ cntmrCtrl &= ~CTCR_ARM_TIMER_AUTO_EN(countNum); ++ } ++ ++ MV_REG_WRITE(CNTMR_CTRL_REG,cntmrCtrl); ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvCntmrCtrlGet - ++* ++* DESCRIPTION: ++* Get the Control value of a given counter/timer ++* ++* INPUT: ++* countNum - counter number ++* pCtrl - pointer to MV_CNTMR_CTRL structure ++* ++* OUTPUT: ++* Counter\Timer control value ++* ++* RETURN: ++* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess ++*******************************************************************************/ ++MV_STATUS mvCntmrCtrlGet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl) ++{ ++ MV_U32 cntmrCtrl; ++ ++ if (countNum >= MV_CNTMR_MAX_COUNTER ) ++ { ++ DB(mvOsPrintf(("mvCntmrCtrlGet: Err. Illigal counter number \n"))); ++ return MV_BAD_PARAM;; ++ } ++ ++ /* read control register */ ++ cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG); ++ ++ /* enable counter\timer */ ++ if (cntmrCtrl & CTCR_ARM_TIMER_EN(countNum)) ++ { ++ pCtrl->enable = MV_TRUE; ++ } ++ else ++ { ++ pCtrl->enable = MV_FALSE; ++ } ++ ++ /* counter mode */ ++ if (cntmrCtrl & CTCR_ARM_TIMER_AUTO_EN(countNum)) ++ { ++ pCtrl->autoEnable = MV_TRUE; ++ } ++ else ++ { ++ pCtrl->autoEnable = MV_FALSE; ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCntmrEnable - ++* ++* DESCRIPTION: ++* Set the Enable-Bit to logic '1' ==> starting the counter ++* ++* INPUT: ++* countNum - counter number ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess ++*******************************************************************************/ ++MV_STATUS mvCntmrEnable(MV_U32 countNum) ++{ ++ MV_U32 cntmrCtrl; ++ ++ if (countNum >= MV_CNTMR_MAX_COUNTER ) ++ { ++ ++ DB(mvOsPrintf(("mvCntmrEnable: Err. Illigal counter number \n"))); ++ return MV_BAD_PARAM;; ++ ++ } ++ ++ /* read control register */ ++ cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG); ++ ++ /* enable counter\timer */ ++ cntmrCtrl |= CTCR_ARM_TIMER_EN(countNum); ++ ++ ++ MV_REG_WRITE(CNTMR_CTRL_REG,cntmrCtrl); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCntmrDisable - ++* ++* DESCRIPTION: ++* Stop the counter/timer running, and returns its Value ++* ++* INPUT: ++* countNum - counter number ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_U32 counter\timer value ++*******************************************************************************/ ++MV_STATUS mvCntmrDisable(MV_U32 countNum) ++{ ++ MV_U32 cntmrCtrl; ++ ++ if (countNum >= MV_CNTMR_MAX_COUNTER ) ++ { ++ ++ DB(mvOsPrintf(("mvCntmrDisable: Err. Illigal counter number \n"))); ++ return MV_BAD_PARAM;; ++ ++ } ++ ++ /* read control register */ ++ cntmrCtrl = MV_REG_READ(CNTMR_CTRL_REG); ++ ++ /* disable counter\timer */ ++ cntmrCtrl &= ~CTCR_ARM_TIMER_EN(countNum); ++ ++ MV_REG_WRITE(CNTMR_CTRL_REG,cntmrCtrl); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvCntmrStart - ++* ++* DESCRIPTION: ++* Combined all the sub-operations above to one function: Load,setMode,Enable ++* ++* INPUT: ++* countNum - counter number ++* value - value of the counter\timer to be set ++* pCtrl - pointer to MV_CNTMR_CTRL structure ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM on bad parameters , MV_ERROR on error ,MV_OK on sucess ++*******************************************************************************/ ++MV_STATUS mvCntmrStart(MV_U32 countNum, MV_U32 value, ++ MV_CNTMR_CTRL *pCtrl) ++{ ++ ++ if (countNum >= MV_CNTMR_MAX_COUNTER ) ++ { ++ ++ mvOsPrintf(("mvCntmrDisable: Err. Illigal counter number \n")); ++ return MV_BAD_PARAM;; ++ ++ } ++ ++ /* load value onto counter\timer */ ++ mvCntmrLoad(countNum,value); ++ ++ /* set the counter to load in the first time */ ++ mvCntmrWrite(countNum,value); ++ ++ /* set control for timer \ cunter and enable */ ++ mvCntmrCtrlSet(countNum,pCtrl); ++ ++ return MV_OK; ++} ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmr.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,121 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvTmrWtdgh ++#define __INCmvTmrWtdgh ++ ++/* includes */ ++#include "mvCommon.h" ++#include "mvOs.h" ++#include "cntmr/mvCntmrRegs.h" ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++ ++ ++/* This enumerator describe counters\watchdog numbers */ ++typedef enum _mvCntmrID ++{ ++ TIMER0 = 0, ++ TIMER1, ++ WATCHDOG, ++ TIMER2, ++ TIMER3, ++}MV_CNTMR_ID; ++ ++ ++/* Counter / Timer control structure */ ++typedef struct _mvCntmrCtrl ++{ ++ MV_BOOL enable; /* enable */ ++ MV_BOOL autoEnable; /* counter/Timer */ ++}MV_CNTMR_CTRL; ++ ++ ++/* Functions */ ++ ++/* Load an init Value to a given counter/timer */ ++MV_STATUS mvCntmrLoad(MV_U32 countNum, MV_U32 value); ++ ++/* Returns the value of the given Counter/Timer */ ++MV_U32 mvCntmrRead(MV_U32 countNum); ++ ++/* Write a value of the given Counter/Timer */ ++void mvCntmrWrite(MV_U32 countNum,MV_U32 countVal); ++ ++/* Set the Control to a given counter/timer */ ++MV_STATUS mvCntmrCtrlSet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl); ++ ++/* Get the value of a given counter/timer */ ++MV_STATUS mvCntmrCtrlGet(MV_U32 countNum, MV_CNTMR_CTRL *pCtrl); ++ ++/* Set the Enable-Bit to logic '1' ==> starting the counter. */ ++MV_STATUS mvCntmrEnable(MV_U32 countNum); ++ ++/* Stop the counter/timer running, and returns its Value. */ ++MV_STATUS mvCntmrDisable(MV_U32 countNum); ++ ++/* Combined all the sub-operations above to one function: Load,setMode,Enable */ ++MV_STATUS mvCntmrStart(MV_U32 countNum, MV_U32 value, ++ MV_CNTMR_CTRL *pCtrl); ++ ++#endif /* __INCmvTmrWtdgh */ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmrRegs.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmrRegs.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmrRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCntmrRegs.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,121 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvTmrwtdgRegsh ++#define __INCmvTmrwtdgRegsh ++ ++/*******************************************/ ++/* ARM Timers Registers Map */ ++/*******************************************/ ++ ++#define CNTMR_RELOAD_REG(tmrNum) (CNTMR_BASE + 0x10 + (tmrNum)*8 + \ ++ (((tmrNum) <= 3)?0:8)) ++#define CNTMR_VAL_REG(tmrNum) (CNTMR_BASE + 0x14 + (tmrNum)*8 + \ ++ (((tmrNum) <= 3)?0:8)) ++#define CNTMR_CTRL_REG (CNTMR_BASE) ++ ++/*For MV78XX0*/ ++#define CNTMR_CAUSE_REG (CPU_AHB_MBUS_CAUSE_INT_REG(whoAmI())) ++#define CNTMR_MASK_REG (CPU_AHB_MBUS_MASK_INT_REG(whoAmI())) ++ ++/* ARM Timers Registers Map */ ++/*******************************************/ ++ ++ ++/* ARM Timers Control Register */ ++/* CPU_TIMERS_CTRL_REG (CTCR) */ ++ ++#define TIMER0_NUM 0 ++#define TIMER1_NUM 1 ++#define WATCHDOG_NUM 2 ++#define TIMER2_NUM 3 ++#define TIMER3_NUM 4 ++ ++#define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2) ++#define CTCR_ARM_TIMER_EN_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS) ++#define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr)) ++#define CTCR_ARM_TIMER_DIS(cntr) (0 << CTCR_ARM_TIMER_EN_OFFS(cntr)) ++ ++#define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1) ++#define CTCR_ARM_TIMER_AUTO_MASK(cntr) BIT1 ++#define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) ++#define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) ++ ++ ++/* ARM Timer\Watchdog Reload Register */ ++/* CNTMR_RELOAD_REG (TRR) */ ++ ++#define TRG_ARM_TIMER_REL_OFFS 0 ++#define TRG_ARM_TIMER_REL_MASK 0xffffffff ++ ++/* ARM Timer\Watchdog Register */ ++/* CNTMR_VAL_REG (TVRG) */ ++ ++#define TVR_ARM_TIMER_OFFS 0 ++#define TVR_ARM_TIMER_MASK 0xffffffff ++#define TVR_ARM_TIMER_MAX 0xffffffff ++ ++ ++ ++#endif /* __INCmvTmrwtdgRegsh */ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCompVer.txt linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCompVer.txt +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCompVer.txt 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/cntmr/mvCompVer.txt 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,4 @@ ++Global HAL Version: FEROCEON_HAL_3_1_7 ++Unit HAL Version: 3.1.3 ++Description: This component includes an implementation of the unit HAL drivers ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuCntrs.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,207 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#include "mvOs.h" ++#include "mvCpuCntrs.h" ++ ++ ++const static MV_CPU_CNTRS_OPS mvCpuCntrsOpsTbl[MV_CPU_CNTRS_NUM][MV_CPU_CNTRS_OPS_NUM] = ++{ ++ /*0*/ ++ { ++ MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_DCACHE_READ_HIT, MV_CPU_CNTRS_DCACHE_READ_MISS, ++ MV_CPU_CNTRS_DCACHE_WRITE_HIT, MV_CPU_CNTRS_DCACHE_WRITE_MISS, MV_CPU_CNTRS_INSTRUCTIONS, ++ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, ++ MV_CPU_CNTRS_MMU_READ_LATENCY, MV_CPU_CNTRS_ICACHE_READ_LATENCY, MV_CPU_CNTRS_WB_WRITE_LATENCY, ++ MV_CPU_CNTRS_LDM_STM_HOLD, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, ++ MV_CPU_CNTRS_DATA_WRITE_ACCESS, MV_CPU_CNTRS_DATA_READ_ACCESS, MV_CPU_CNTRS_INVALID, ++ MV_CPU_CNTRS_BRANCH_PREDICT_COUNT, ++ }, ++ /*1*/ ++ { ++ MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_ICACHE_READ_MISS, MV_CPU_CNTRS_DCACHE_READ_MISS, ++ MV_CPU_CNTRS_DCACHE_WRITE_MISS, MV_CPU_CNTRS_ITLB_MISS, MV_CPU_CNTRS_SINGLE_ISSUE, ++ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BRANCH_RETIRED, MV_CPU_CNTRS_INVALID, ++ MV_CPU_CNTRS_MMU_READ_BEAT, MV_CPU_CNTRS_ICACHE_READ_LATENCY, MV_CPU_CNTRS_WB_WRITE_BEAT, ++ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_IS_HOLD, MV_CPU_CNTRS_DATA_READ_ACCESS, ++ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, ++ MV_CPU_CNTRS_INVALID, ++ }, ++ /*2*/ ++ { ++ MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DCACHE_ACCESS, ++ MV_CPU_CNTRS_DTLB_MISS, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, ++ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BRANCH_PREDICT_MISS, MV_CPU_CNTRS_WB_WRITE_BEAT, ++ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DCACHE_READ_LATENCY, MV_CPU_CNTRS_DCACHE_WRITE_LATENCY, ++ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BIU_SIMULT_ACCESS, ++ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, ++ MV_CPU_CNTRS_INVALID, ++ }, ++ /*3*/ ++ { ++ MV_CPU_CNTRS_CYCLES, MV_CPU_CNTRS_DCACHE_READ_MISS, MV_CPU_CNTRS_DCACHE_WRITE_MISS, ++ MV_CPU_CNTRS_TLB_MISS, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, ++ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BRANCH_TAKEN, MV_CPU_CNTRS_WB_FULL_CYCLES, ++ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DCACHE_READ_BEAT, MV_CPU_CNTRS_DCACHE_WRITE_BEAT, ++ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_BIU_ANY_ACCESS, ++ MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_INVALID, MV_CPU_CNTRS_DATA_WRITE_ACCESS, ++ MV_CPU_CNTRS_INVALID, ++ } ++}; ++ ++MV_CPU_CNTRS_ENTRY mvCpuCntrsTbl[MV_CPU_CNTRS_NUM]; ++ ++MV_CPU_CNTRS_EVENT* mvCpuCntrsEventTbl[128]; ++ ++void mvCpuCntrsReset(void) ++{ ++ MV_U32 reg = 0; ++ ++ MV_ASM ("mcr p15, 0, %0, c15, c13, 0" : : "r" (reg)); ++ MV_ASM ("mcr p15, 0, %0, c15, c13, 1" : : "r" (reg)); ++ MV_ASM ("mcr p15, 0, %0, c15, c13, 2" : : "r" (reg)); ++ MV_ASM ("mcr p15, 0, %0, c15, c13, 3" : : "r" (reg)); ++ MV_ASM ("mcr p15, 0, %0, c15, c13, 4" : : "r" (reg)); ++ MV_ASM ("mcr p15, 0, %0, c15, c13, 5" : : "r" (reg)); ++ MV_ASM ("mcr p15, 0, %0, c15, c13, 6" : : "r" (reg)); ++ MV_ASM ("mcr p15, 0, %0, c15, c13, 7" : : "r" (reg)); ++} ++ ++void program_counter(int counter, int op) ++{ ++ MV_U32 reg = (1 << op) | 0x1; /*enable*/ ++ ++ switch(counter) ++ { ++ case 0: ++ __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 0" : : "r" (reg)); ++ return; ++ ++ case 1: ++ __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 1" : : "r" (reg)); ++ return; ++ ++ case 2: ++ __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 2" : : "r" (reg)); ++ return; ++ ++ case 3: ++ __asm__ __volatile__ ("mcr p15, 0, %0, c15, c12, 3" : : "r" (reg)); ++ return; ++ ++ default: ++ mvOsPrintf("error in program_counter: bad counter number (%d)\n", counter); ++ } ++ return; ++} ++ ++void mvCpuCntrsEventClear(MV_CPU_CNTRS_EVENT* pEvent) ++{ ++ int i; ++ ++ for(i=0; icounters_sum[i] = 0; ++ } ++ pEvent->num_of_measurements = 0; ++} ++ ++ ++MV_CPU_CNTRS_EVENT* mvCpuCntrsEventCreate(char* name, MV_U32 print_threshold) ++{ ++ int i; ++ MV_CPU_CNTRS_EVENT* event = mvOsMalloc(sizeof(MV_CPU_CNTRS_EVENT)); ++ ++ if(event) ++ { ++ strncpy(event->name, name, sizeof(event->name)); ++ event->num_of_measurements = 0; ++ event->avg_sample_count = print_threshold; ++ for(i=0; icounters_before[i] = 0; ++ event->counters_after[i] = 0; ++ event->counters_sum[i] = 0; ++ } ++ } ++ return event; ++} ++ ++void mvCpuCntrsEventDelete(MV_CPU_CNTRS_EVENT* event) ++{ ++ if(event != NULL) ++ mvOsFree(event); ++} ++ ++ ++MV_STATUS mvCpuCntrsProgram(int counter, MV_CPU_CNTRS_OPS op, ++ char* name, MV_U32 overhead) ++{ ++ int i; ++ ++ /* Find required operations */ ++ for(i=0; inum_of_measurements < pEvent->avg_sample_count) ++ return; ++ ++ mvOsPrintf("%16s: ", pEvent->name); ++ for(i=0; icounters_sum[i], ++ pEvent->num_of_measurements, NULL); ++ if(counters_avg >= mvCpuCntrsTbl[i].overhead) ++ counters_avg -= mvCpuCntrsTbl[i].overhead; ++ else ++ counters_avg = 0; ++ ++ mvOsPrintf("%s=%5llu, ", mvCpuCntrsTbl[i].name, counters_avg); ++ } ++ mvOsPrintf("\n"); ++ mvCpuCntrsEventClear(pEvent); ++ mvCpuCntrsReset(); ++} ++ ++void mvCpuCntrsStatus(void) ++{ ++ int i; ++ ++ for(i=0; icounters_before[i] = mvCpuCntrsRead(i); ++#else ++ pEvent->counters_before[1] = mvCpuCntrsRead(1); ++ pEvent->counters_before[3] = mvCpuCntrsRead(3); ++ pEvent->counters_before[0] = mvCpuCntrsRead(0); ++ pEvent->counters_before[2] = mvCpuCntrsRead(2); ++#endif ++} ++ ++static INLINE void mvCpuCntrsReadAfter(MV_CPU_CNTRS_EVENT* pEvent) ++{ ++ int i; ++ ++#if 0 ++ /* order is important - we want to measure the cycle count first here! */ ++ for(i=0; icounters_after[i] = mvCpuCntrsRead(i); ++#else ++ pEvent->counters_after[2] = mvCpuCntrsRead(2); ++ pEvent->counters_after[0] = mvCpuCntrsRead(0); ++ pEvent->counters_after[3] = mvCpuCntrsRead(3); ++ pEvent->counters_after[1] = mvCpuCntrsRead(1); ++#endif ++ ++ for(i=0; icounters_sum[i] += (pEvent->counters_after[i] - pEvent->counters_before[i]); ++ } ++ pEvent->num_of_measurements++; ++} ++ ++ ++#ifdef CONFIG_MV_CPU_PERF_CNTRS ++ ++#define MV_CPU_CNTRS_READ(counter) mvCpuCntrsRead(counter) ++ ++#define MV_CPU_CNTRS_START(event) mvCpuCntrsReadBefore(event) ++ ++#define MV_CPU_CNTRS_STOP(event) mvCpuCntrsReadAfter(event) ++ ++#define MV_CPU_CNTRS_SHOW(event) mvCpuCntrsShow(event) ++ ++#else ++ ++#define MV_CPU_CNTRS_READ(counter) ++#define MV_CPU_CNTRS_START(event) ++#define MV_CPU_CNTRS_STOP(event) ++#define MV_CPU_CNTRS_SHOW(event) ++ ++#endif /* CONFIG_MV_CPU_PERF_CNTRS */ ++ ++ ++#endif /* __mvCpuCntrs_h__ */ ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/cpu/mvCpuL2Cntrs.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,143 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#include "mvOs.h" ++#include "mvCpuL2Cntrs.h" ++ ++ ++ ++MV_CPU_L2_CNTRS_ENTRY mvCpuL2CntrsTbl[MV_CPU_L2_CNTRS_NUM]; ++ ++MV_CPU_L2_CNTRS_EVENT* mvCpuL2CntrsEventTbl[128]; ++ ++void mvCpuL2CntrsReset(void) ++{ ++ MV_U32 reg = 0; ++ ++ MV_ASM ("mcr p15, 6, %0, c15, c13, 0" : : "r" (reg)); ++ MV_ASM ("mcr p15, 6, %0, c15, c13, 1" : : "r" (reg)); ++ MV_ASM ("mcr p15, 6, %0, c15, c13, 2" : : "r" (reg)); ++ MV_ASM ("mcr p15, 6, %0, c15, c13, 3" : : "r" (reg)); ++} ++ ++static void mvCpuL2CntrConfig(int counter, int op) ++{ ++ MV_U32 reg = (1 << op) | 0x1; /*enable*/ ++ ++ switch(counter) ++ { ++ case 0: ++ MV_ASM ("mcr p15, 6, %0, c15, c12, 0" : : "r" (reg)); ++ return; ++ ++ case 1: ++ MV_ASM ("mcr p15, 6, %0, c15, c12, 1" : : "r" (reg)); ++ return; ++ ++ default: ++ mvOsPrintf("mvCpuL2CntrConfig: bad counter number (%d)\n", counter); ++ } ++ return; ++} ++ ++void mvCpuL2CntrsEventClear(MV_CPU_L2_CNTRS_EVENT* pEvent) ++{ ++ int i; ++ ++ for(i=0; icounters_sum[i] = 0; ++ } ++ pEvent->num_of_measurements = 0; ++} ++ ++ ++MV_CPU_L2_CNTRS_EVENT* mvCpuL2CntrsEventCreate(char* name, MV_U32 print_threshold) ++{ ++ int i; ++ MV_CPU_L2_CNTRS_EVENT* event = mvOsMalloc(sizeof(MV_CPU_L2_CNTRS_EVENT)); ++ ++ if(event) ++ { ++ strncpy(event->name, name, sizeof(event->name)); ++ event->num_of_measurements = 0; ++ event->avg_sample_count = print_threshold; ++ for(i=0; icounters_before[i] = 0; ++ event->counters_after[i] = 0; ++ event->counters_sum[i] = 0; ++ } ++ } ++ return event; ++} ++ ++void mvCpuL2CntrsEventDelete(MV_CPU_L2_CNTRS_EVENT* event) ++{ ++ if(event != NULL) ++ mvOsFree(event); ++} ++ ++ ++MV_STATUS mvCpuL2CntrsProgram(int counter, MV_CPU_L2_CNTRS_OPS op, ++ char* name, MV_U32 overhead) ++{ ++ strncpy(mvCpuL2CntrsTbl[counter].name, name, sizeof(mvCpuL2CntrsTbl[counter].name)); ++ mvCpuL2CntrsTbl[counter].operation = op; ++ mvCpuL2CntrsTbl[counter].opIdx = op; ++ mvCpuL2CntrsTbl[counter].overhead = overhead; ++ mvCpuL2CntrConfig(counter, op); ++ mvOsPrintf("CPU L2 Counter %d: operation=%d, overhead=%d\n", ++ counter, op, overhead); ++ return MV_OK; ++} ++ ++void mvCpuL2CntrsShow(MV_CPU_L2_CNTRS_EVENT* pEvent) ++{ ++ int i; ++ MV_U64 counters_avg; ++ ++ if(pEvent->num_of_measurements < pEvent->avg_sample_count) ++ return; ++ ++ mvOsPrintf("%16s: ", pEvent->name); ++ for(i=0; icounters_sum[i], ++ pEvent->num_of_measurements, NULL); ++ ++ if(counters_avg >= mvCpuL2CntrsTbl[i].overhead) ++ counters_avg -= mvCpuL2CntrsTbl[i].overhead; ++ else ++ counters_avg = 0; ++ ++ mvOsPrintf("%s=%5llu, ", mvCpuL2CntrsTbl[i].name, counters_avg); ++ } ++ mvOsPrintf("\n"); ++ mvCpuL2CntrsEventClear(pEvent); ++ mvCpuL2CntrsReset(); ++} ++ ++void mvCpuL2CntrsStatus(void) ++{ ++ int i; ++ ++ for(i=0; icounters_before[i] = mvCpuL2CntrsRead(i); ++} ++ ++static INLINE void mvCpuL2CntrsReadAfter(MV_CPU_L2_CNTRS_EVENT* pEvent) ++{ ++ int i; ++ ++ for(i=0; icounters_after[i] = mvCpuL2CntrsRead(i); ++ pEvent->counters_sum[i] += (pEvent->counters_after[i] - pEvent->counters_before[i]); ++ } ++ pEvent->num_of_measurements++; ++} ++ ++ ++#ifdef CONFIG_MV_CPU_L2_PERF_CNTRS ++ ++#define MV_CPU_L2_CNTRS_READ(counter) mvCpuL2CntrsRead(counter) ++ ++#define MV_CPU_L2_CNTRS_START(event) mvCpuL2CntrsReadBefore(event) ++ ++#define MV_CPU_L2_CNTRS_STOP(event) mvCpuL2CntrsReadAfter(event) ++ ++#define MV_CPU_L2_CNTRS_SHOW(event) mvCpuL2CntrsShow(event) ++ ++#else ++ ++#define MV_CPU_L2_CNTRS_READ(counter) ++#define MV_CPU_L2_CNTRS_START(event) ++#define MV_CPU_L2_CNTRS_STOP(event) ++#define MV_CPU_L2_CNTRS_SHOW(event) ++ ++#endif /* CONFIG_MV_CPU_L2_PERF_CNTRS */ ++ ++ ++#endif /* __mvCpuL2Cntrs_h__ */ ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvCompVer.txt linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvCompVer.txt +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvCompVer.txt 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvCompVer.txt 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,4 @@ ++Global HAL Version: FEROCEON_HAL_3_1_7 ++Unit HAL Version: 3.1.3 ++Description: This component includes an implementation of the unit HAL drivers ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,1479 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#include "ddr1_2/mvDram.h" ++#include "boardEnv/mvBoardEnvLib.h" ++ ++#undef MV_DEBUG ++#ifdef MV_DEBUG ++#define DB(x) x ++#else ++#define DB(x) ++#endif ++ ++static MV_VOID cpyDimm2BankInfo(MV_DIMM_INFO *pDimmInfo, ++ MV_DRAM_BANK_INFO *pBankInfo); ++static MV_U32 cas2ps(MV_U8 spd_byte); ++/******************************************************************************* ++* mvDramBankGet - Get the DRAM bank paramters. ++* ++* DESCRIPTION: ++* This function retrieves DRAM bank parameters as described in ++* DRAM_BANK_INFO struct to the controller DRAM unit. In case the board ++* has its DRAM on DIMMs it will use its EEPROM to extract SPD data ++* from it. Otherwise, if the DRAM is soldered on board, the function ++* should insert its bank information into MV_DRAM_BANK_INFO struct. ++* ++* INPUT: ++* bankNum - Board DRAM bank number. ++* ++* OUTPUT: ++* pBankInfo - DRAM bank information struct. ++* ++* RETURN: ++* MV_FAIL - Bank parameters could not be read. ++* ++*******************************************************************************/ ++MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo) ++{ ++ MV_DIMM_INFO dimmInfo; ++ ++ DB(mvOsPrintf("Dram: mvDramBankInfoGet bank %d\n", bankNum)); ++ /* zero pBankInfo structure */ ++ memset(pBankInfo, 0, sizeof(*pBankInfo)); ++ ++ if((NULL == pBankInfo) || (bankNum >= MV_DRAM_MAX_CS )) ++ { ++ DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); ++ return MV_BAD_PARAM; ++ } ++ if( MV_OK != dimmSpdGet((MV_U32)(bankNum/2), &dimmInfo)) ++ { ++ DB(mvOsPrintf("Dram: ERR dimmSpdGet failed to get dimm info \n")); ++ return MV_FAIL; ++ } ++ if((dimmInfo.numOfModuleBanks == 1) && ((bankNum % 2) == 1)) ++ { ++ DB(mvOsPrintf("Dram: ERR dimmSpdGet. Can't find DIMM bank 2 \n")); ++ return MV_FAIL; ++ } ++ ++ /* convert Dimm info to Bank info */ ++ cpyDimm2BankInfo(&dimmInfo, pBankInfo); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* cpyDimm2BankInfo - Convert a Dimm info struct into a bank info struct. ++* ++* DESCRIPTION: ++* Convert a Dimm info struct into a bank info struct. ++* ++* INPUT: ++* pDimmInfo - DIMM information structure. ++* ++* OUTPUT: ++* pBankInfo - DRAM bank information struct. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++static MV_VOID cpyDimm2BankInfo(MV_DIMM_INFO *pDimmInfo, ++ MV_DRAM_BANK_INFO *pBankInfo) ++{ ++ pBankInfo->memoryType = pDimmInfo->memoryType; ++ ++ /* DIMM dimensions */ ++ pBankInfo->numOfRowAddr = pDimmInfo->numOfRowAddr; ++ pBankInfo->numOfColAddr = pDimmInfo->numOfColAddr; ++ pBankInfo->dataWidth = pDimmInfo->dataWidth; ++ pBankInfo->errorCheckType = pDimmInfo->errorCheckType; ++ pBankInfo->sdramWidth = pDimmInfo->sdramWidth; ++ pBankInfo->errorCheckDataWidth = pDimmInfo->errorCheckDataWidth; ++ pBankInfo->numOfBanksOnEachDevice = pDimmInfo->numOfBanksOnEachDevice; ++ pBankInfo->suportedCasLatencies = pDimmInfo->suportedCasLatencies; ++ pBankInfo->refreshInterval = pDimmInfo->refreshInterval; ++ ++ /* DIMM timing parameters */ ++ pBankInfo->minCycleTimeAtMaxCasLatPs = pDimmInfo->minCycleTimeAtMaxCasLatPs; ++ pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps = ++ pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps; ++ pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps = ++ pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps; ++ ++ pBankInfo->minRowPrechargeTime = pDimmInfo->minRowPrechargeTime; ++ pBankInfo->minRowActiveToRowActive = pDimmInfo->minRowActiveToRowActive; ++ pBankInfo->minRasToCasDelay = pDimmInfo->minRasToCasDelay; ++ pBankInfo->minRasPulseWidth = pDimmInfo->minRasPulseWidth; ++ pBankInfo->minWriteRecoveryTime = pDimmInfo->minWriteRecoveryTime; ++ pBankInfo->minWriteToReadCmdDelay = pDimmInfo->minWriteToReadCmdDelay; ++ pBankInfo->minReadToPrechCmdDelay = pDimmInfo->minReadToPrechCmdDelay; ++ pBankInfo->minRefreshToActiveCmd = pDimmInfo->minRefreshToActiveCmd; ++ ++ /* Parameters calculated from the extracted DIMM information */ ++ pBankInfo->size = pDimmInfo->size/pDimmInfo->numOfModuleBanks; ++ pBankInfo->deviceDensity = pDimmInfo->deviceDensity; ++ pBankInfo->numberOfDevices = pDimmInfo->numberOfDevices / ++ pDimmInfo->numOfModuleBanks; ++ ++ /* DIMM attributes (MV_TRUE for yes) */ ++ ++ if ((pDimmInfo->memoryType == MEM_TYPE_SDRAM) || ++ (pDimmInfo->memoryType == MEM_TYPE_DDR1) ) ++ { ++ if (pDimmInfo->dimmAttributes & BIT1) ++ pBankInfo->registeredAddrAndControlInputs = MV_TRUE; ++ else ++ pBankInfo->registeredAddrAndControlInputs = MV_FALSE; ++ } ++ else /* pDimmInfo->memoryType == MEM_TYPE_DDR2 */ ++ { ++ if (pDimmInfo->dimmTypeInfo & (BIT0 | BIT4)) ++ pBankInfo->registeredAddrAndControlInputs = MV_TRUE; ++ else ++ pBankInfo->registeredAddrAndControlInputs = MV_FALSE; ++ } ++ ++ return; ++} ++ ++/******************************************************************************* ++* dimmSpdCpy - Cpy SPD parameters from dimm 0 to dimm 1. ++* ++* DESCRIPTION: ++* Read the DIMM SPD parameters from dimm 0 into dimm 1 SPD. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. ++* ++*******************************************************************************/ ++MV_STATUS dimmSpdCpy(MV_VOID) ++{ ++ MV_U32 i; ++ MV_U32 spdChecksum; ++ ++ MV_TWSI_SLAVE twsiSlave; ++ MV_U8 data[SPD_SIZE]; ++ ++ /* zero dimmInfo structure */ ++ memset(data, 0, SPD_SIZE); ++ ++ /* read the dimm eeprom */ ++ DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); ++ twsiSlave.slaveAddr.address = MV_BOARD_DIMM0_I2C_ADDR; ++ twsiSlave.slaveAddr.type = ADDR7_BIT; ++ twsiSlave.validOffset = MV_TRUE; ++ twsiSlave.offset = 0; ++ twsiSlave.moreThen256 = MV_FALSE; ++ ++ if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, ++ &twsiSlave, data, SPD_SIZE) ) ++ { ++ DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 0\n")); ++ return MV_FAIL; ++ } ++ DB(puts("DRAM: Reading dimm info succeded.\n")); ++ ++ /* calculate SPD checksum */ ++ spdChecksum = 0; ++ ++ for(i = 0 ; i <= 62 ; i++) ++ { ++ spdChecksum += data[i]; ++ } ++ ++ if ((spdChecksum & 0xff) != data[63]) ++ { ++ DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", ++ (MV_U32)(spdChecksum & 0xff), data[63])); ++ } ++ else ++ { ++ DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); ++ } ++ ++ /* copy the SPD content 1:1 into the DIMM 1 SPD */ ++ twsiSlave.slaveAddr.address = MV_BOARD_DIMM1_I2C_ADDR; ++ twsiSlave.slaveAddr.type = ADDR7_BIT; ++ twsiSlave.validOffset = MV_TRUE; ++ twsiSlave.offset = 0; ++ twsiSlave.moreThen256 = MV_FALSE; ++ ++ for(i = 0 ; i < SPD_SIZE ; i++) ++ { ++ twsiSlave.offset = i; ++ if( MV_OK != mvTwsiWrite (MV_BOARD_DIMM_I2C_CHANNEL, ++ &twsiSlave, &data[i], 1) ) ++ { ++ mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 1 byte %d \n",i); ++ return MV_FAIL; ++ } ++ mvOsDelay(5); ++ } ++ ++ DB(puts("DRAM: Reading dimm info succeded.\n")); ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* dimmSpdGet - Get the SPD parameters. ++* ++* DESCRIPTION: ++* Read the DIMM SPD parameters into given struct parameter. ++* ++* INPUT: ++* dimmNum - DIMM number. See MV_BOARD_DIMM_NUM enumerator. ++* ++* OUTPUT: ++* pDimmInfo - DIMM information structure. ++* ++* RETURN: ++* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. ++* ++*******************************************************************************/ ++MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo) ++{ ++ MV_U32 i; ++ MV_U32 density = 1; ++ MV_U32 spdChecksum; ++ ++ MV_TWSI_SLAVE twsiSlave; ++ MV_U8 data[SPD_SIZE]; ++ ++ if((NULL == pDimmInfo)|| (dimmNum >= MAX_DIMM_NUM)) ++ { ++ DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); ++ return MV_BAD_PARAM; ++ } ++ ++ /* zero dimmInfo structure */ ++ memset(data, 0, SPD_SIZE); ++ ++ /* read the dimm eeprom */ ++ DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); ++ twsiSlave.slaveAddr.address = (dimmNum == 0) ? ++ MV_BOARD_DIMM0_I2C_ADDR : MV_BOARD_DIMM1_I2C_ADDR; ++ twsiSlave.slaveAddr.type = ADDR7_BIT; ++ twsiSlave.validOffset = MV_TRUE; ++ twsiSlave.offset = 0; ++ twsiSlave.moreThen256 = MV_FALSE; ++ ++ if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, ++ &twsiSlave, data, SPD_SIZE) ) ++ { ++ DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum %d \n", dimmNum)); ++ return MV_FAIL; ++ } ++ DB(puts("DRAM: Reading dimm info succeded.\n")); ++ ++ /* calculate SPD checksum */ ++ spdChecksum = 0; ++ ++ for(i = 0 ; i <= 62 ; i++) ++ { ++ spdChecksum += data[i]; ++ } ++ ++ if ((spdChecksum & 0xff) != data[63]) ++ { ++ DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", ++ (MV_U32)(spdChecksum & 0xff), data[63])); ++ } ++ else ++ { ++ DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); ++ } ++ ++ /* copy the SPD content 1:1 into the dimmInfo structure*/ ++ for(i = 0 ; i < SPD_SIZE ; i++) ++ { ++ pDimmInfo->spdRawData[i] = data[i]; ++ DB(mvOsPrintf("SPD-EEPROM Byte %3d = %3x (%3d)\n",i, data[i], data[i])); ++ } ++ ++ DB(mvOsPrintf("DRAM SPD Information:\n")); ++ ++ /* Memory type (DDR / SDRAM) */ ++ switch (data[DIMM_MEM_TYPE]) ++ { ++ case (DIMM_MEM_TYPE_SDRAM): ++ pDimmInfo->memoryType = MEM_TYPE_SDRAM; ++ DB(mvOsPrintf("DRAM Memeory type SDRAM\n")); ++ break; ++ case (DIMM_MEM_TYPE_DDR1): ++ pDimmInfo->memoryType = MEM_TYPE_DDR1; ++ DB(mvOsPrintf("DRAM Memeory type DDR1\n")); ++ break; ++ case (DIMM_MEM_TYPE_DDR2): ++ pDimmInfo->memoryType = MEM_TYPE_DDR2; ++ DB(mvOsPrintf("DRAM Memeory type DDR2\n")); ++ break; ++ default: ++ mvOsPrintf("ERROR: Undefined memory type!\n"); ++ return MV_ERROR; ++ } ++ ++ ++ /* Number Of Row Addresses */ ++ pDimmInfo->numOfRowAddr = data[DIMM_ROW_NUM]; ++ DB(mvOsPrintf("DRAM numOfRowAddr[3] %d\n",pDimmInfo->numOfRowAddr)); ++ ++ /* Number Of Column Addresses */ ++ pDimmInfo->numOfColAddr = data[DIMM_COL_NUM]; ++ DB(mvOsPrintf("DRAM numOfColAddr[4] %d\n",pDimmInfo->numOfColAddr)); ++ ++ /* Number Of Module Banks */ ++ pDimmInfo->numOfModuleBanks = data[DIMM_MODULE_BANK_NUM]; ++ DB(mvOsPrintf("DRAM numOfModuleBanks[5] 0x%x\n", ++ pDimmInfo->numOfModuleBanks)); ++ ++ /* Number of module banks encoded differently for DDR2 */ ++ if (pDimmInfo->memoryType == MEM_TYPE_DDR2) ++ pDimmInfo->numOfModuleBanks = (pDimmInfo->numOfModuleBanks & 0x7)+1; ++ ++ /* Data Width */ ++ pDimmInfo->dataWidth = data[DIMM_DATA_WIDTH]; ++ DB(mvOsPrintf("DRAM dataWidth[6] 0x%x\n", pDimmInfo->dataWidth)); ++ ++ /* Minimum Cycle Time At Max CasLatancy */ ++ pDimmInfo->minCycleTimeAtMaxCasLatPs = cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS]); ++ ++ /* Error Check Type */ ++ pDimmInfo->errorCheckType = data[DIMM_ERR_CHECK_TYPE]; ++ DB(mvOsPrintf("DRAM errorCheckType[11] 0x%x\n", ++ pDimmInfo->errorCheckType)); ++ ++ /* Refresh Interval */ ++ pDimmInfo->refreshInterval = data[DIMM_REFRESH_INTERVAL]; ++ DB(mvOsPrintf("DRAM refreshInterval[12] 0x%x\n", ++ pDimmInfo->refreshInterval)); ++ ++ /* Sdram Width */ ++ pDimmInfo->sdramWidth = data[DIMM_SDRAM_WIDTH]; ++ DB(mvOsPrintf("DRAM sdramWidth[13] 0x%x\n",pDimmInfo->sdramWidth)); ++ ++ /* Error Check Data Width */ ++ pDimmInfo->errorCheckDataWidth = data[DIMM_ERR_CHECK_DATA_WIDTH]; ++ DB(mvOsPrintf("DRAM errorCheckDataWidth[14] 0x%x\n", ++ pDimmInfo->errorCheckDataWidth)); ++ ++ /* Burst Length Supported */ ++ /* SDRAM/DDR1: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * ++ *********************************************************/ ++ /* DDR2: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * ++ *********************************************************/ ++ ++ pDimmInfo->burstLengthSupported = data[DIMM_BURST_LEN_SUP]; ++ DB(mvOsPrintf("DRAM burstLengthSupported[16] 0x%x\n", ++ pDimmInfo->burstLengthSupported)); ++ ++ /* Number Of Banks On Each Device */ ++ pDimmInfo->numOfBanksOnEachDevice = data[DIMM_DEV_BANK_NUM]; ++ DB(mvOsPrintf("DRAM numOfBanksOnEachDevice[17] 0x%x\n", ++ pDimmInfo->numOfBanksOnEachDevice)); ++ ++ /* Suported Cas Latencies */ ++ ++ /* SDRAM: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * ++ ********************************************************/ ++ ++ /* DDR 1: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * ++ *********************************************************/ ++ ++ /* DDR 2: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * ++ *********************************************************/ ++ ++ pDimmInfo->suportedCasLatencies = data[DIMM_SUP_CAL]; ++ DB(mvOsPrintf("DRAM suportedCasLatencies[18] 0x%x\n", ++ pDimmInfo->suportedCasLatencies)); ++ ++ /* For DDR2 only, get the DIMM type information */ ++ if (pDimmInfo->memoryType == MEM_TYPE_DDR2) ++ { ++ pDimmInfo->dimmTypeInfo = data[DIMM_DDR2_TYPE_INFORMATION]; ++ DB(mvOsPrintf("DRAM dimmTypeInfo[20] (DDR2) 0x%x\n", ++ pDimmInfo->dimmTypeInfo)); ++ } ++ ++ /* SDRAM Modules Attributes */ ++ pDimmInfo->dimmAttributes = data[DIMM_BUF_ADDR_CONT_IN]; ++ DB(mvOsPrintf("DRAM dimmAttributes[21] 0x%x\n", ++ pDimmInfo->dimmAttributes)); ++ ++ /* Minimum Cycle Time At Max CasLatancy Minus 1*/ ++ pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps = ++ cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS1]); ++ ++ /* Minimum Cycle Time At Max CasLatancy Minus 2*/ ++ pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps = ++ cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS2]); ++ ++ pDimmInfo->minRowPrechargeTime = data[DIMM_MIN_ROW_PRECHARGE_TIME]; ++ DB(mvOsPrintf("DRAM minRowPrechargeTime[27] 0x%x\n", ++ pDimmInfo->minRowPrechargeTime)); ++ pDimmInfo->minRowActiveToRowActive = data[DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE]; ++ DB(mvOsPrintf("DRAM minRowActiveToRowActive[28] 0x%x\n", ++ pDimmInfo->minRowActiveToRowActive)); ++ pDimmInfo->minRasToCasDelay = data[DIMM_MIN_RAS_TO_CAS_DELAY]; ++ DB(mvOsPrintf("DRAM minRasToCasDelay[29] 0x%x\n", ++ pDimmInfo->minRasToCasDelay)); ++ pDimmInfo->minRasPulseWidth = data[DIMM_MIN_RAS_PULSE_WIDTH]; ++ DB(mvOsPrintf("DRAM minRasPulseWidth[30] 0x%x\n", ++ pDimmInfo->minRasPulseWidth)); ++ ++ /* DIMM Bank Density */ ++ pDimmInfo->dimmBankDensity = data[DIMM_BANK_DENSITY]; ++ DB(mvOsPrintf("DRAM dimmBankDensity[31] 0x%x\n", ++ pDimmInfo->dimmBankDensity)); ++ ++ /* Only DDR2 includes Write Recovery Time field. Other SDRAM ignore */ ++ pDimmInfo->minWriteRecoveryTime = data[DIMM_MIN_WRITE_RECOVERY_TIME]; ++ DB(mvOsPrintf("DRAM minWriteRecoveryTime[36] 0x%x\n", ++ pDimmInfo->minWriteRecoveryTime)); ++ ++ /* Only DDR2 includes Internal Write To Read Command Delay field. */ ++ pDimmInfo->minWriteToReadCmdDelay = data[DIMM_MIN_WRITE_TO_READ_CMD_DELAY]; ++ DB(mvOsPrintf("DRAM minWriteToReadCmdDelay[37] 0x%x\n", ++ pDimmInfo->minWriteToReadCmdDelay)); ++ ++ /* Only DDR2 includes Internal Read To Precharge Command Delay field. */ ++ pDimmInfo->minReadToPrechCmdDelay = data[DIMM_MIN_READ_TO_PRECH_CMD_DELAY]; ++ DB(mvOsPrintf("DRAM minReadToPrechCmdDelay[38] 0x%x\n", ++ pDimmInfo->minReadToPrechCmdDelay)); ++ ++ /* Only DDR2 includes Minimum Refresh to Activate/Refresh Command field */ ++ pDimmInfo->minRefreshToActiveCmd = data[DIMM_MIN_REFRESH_TO_ACTIVATE_CMD]; ++ DB(mvOsPrintf("DRAM minRefreshToActiveCmd[42] 0x%x\n", ++ pDimmInfo->minRefreshToActiveCmd)); ++ ++ /* calculating the sdram density. Representing device density from */ ++ /* bit 20 to allow representation of 4GB and above. */ ++ /* For example, if density is 512Mbit 0x20000000, will be represent in */ ++ /* deviceDensity by 0x20000000 >> 16 --> 0x00000200. Another example */ ++ /* is density 8GB 0x200000000 >> 16 --> 0x00002000. */ ++ density = (1 << ((pDimmInfo->numOfRowAddr + pDimmInfo->numOfColAddr) - 20)); ++ pDimmInfo->deviceDensity = density * ++ pDimmInfo->numOfBanksOnEachDevice * ++ pDimmInfo->sdramWidth; ++ DB(mvOsPrintf("DRAM deviceDensity %d\n",pDimmInfo->deviceDensity)); ++ ++ /* Number of devices includeing Error correction */ ++ pDimmInfo->numberOfDevices = (pDimmInfo->dataWidth/pDimmInfo->sdramWidth) * ++ pDimmInfo->numOfModuleBanks; ++ DB(mvOsPrintf("DRAM numberOfDevices %d\n", ++ pDimmInfo->numberOfDevices)); ++ ++ pDimmInfo->size = 0; ++ ++ /* Note that pDimmInfo->size is in MB units */ ++ if (pDimmInfo->memoryType == MEM_TYPE_SDRAM) ++ { ++ if (pDimmInfo->dimmBankDensity & BIT0) ++ pDimmInfo->size += 1024; /* Equal to 1GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT1) ++ pDimmInfo->size += 8; /* Equal to 8MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT2) ++ pDimmInfo->size += 16; /* Equal to 16MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT3) ++ pDimmInfo->size += 32; /* Equal to 32MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT4) ++ pDimmInfo->size += 64; /* Equal to 64MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT5) ++ pDimmInfo->size += 128; /* Equal to 128MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT6) ++ pDimmInfo->size += 256; /* Equal to 256MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT7) ++ pDimmInfo->size += 512; /* Equal to 512MB */ ++ } ++ else if (pDimmInfo->memoryType == MEM_TYPE_DDR1) ++ { ++ if (pDimmInfo->dimmBankDensity & BIT0) ++ pDimmInfo->size += 1024; /* Equal to 1GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT1) ++ pDimmInfo->size += 2048; /* Equal to 2GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT2) ++ pDimmInfo->size += 16; /* Equal to 16MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT3) ++ pDimmInfo->size += 32; /* Equal to 32MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT4) ++ pDimmInfo->size += 64; /* Equal to 64MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT5) ++ pDimmInfo->size += 128; /* Equal to 128MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT6) ++ pDimmInfo->size += 256; /* Equal to 256MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT7) ++ pDimmInfo->size += 512; /* Equal to 512MB */ ++ } ++ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ ++ { ++ if (pDimmInfo->dimmBankDensity & BIT0) ++ pDimmInfo->size += 1024; /* Equal to 1GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT1) ++ pDimmInfo->size += 2048; /* Equal to 2GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT2) ++ pDimmInfo->size += 4096; /* Equal to 4GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT3) ++ pDimmInfo->size += 8192; /* Equal to 8GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT4) ++ pDimmInfo->size += 16384; /* Equal to 16GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT5) ++ pDimmInfo->size += 128; /* Equal to 128MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT6) ++ pDimmInfo->size += 256; /* Equal to 256MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT7) ++ pDimmInfo->size += 512; /* Equal to 512MB */ ++ } ++ ++ pDimmInfo->size *= pDimmInfo->numOfModuleBanks; ++ ++ DB(mvOsPrintf("Dram: dimm size %dMB \n",pDimmInfo->size)); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* dimmSpdPrint - Print the SPD parameters. ++* ++* DESCRIPTION: ++* Print the Dimm SPD parameters. ++* ++* INPUT: ++* pDimmInfo - DIMM information structure. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID dimmSpdPrint(MV_U32 dimmNum) ++{ ++ MV_DIMM_INFO dimmInfo; ++ MV_U32 i, temp = 0; ++ MV_U32 k, maskLeftOfPoint = 0, maskRightOfPoint = 0; ++ MV_U32 rightOfPoint = 0,leftOfPoint = 0, div, time_tmp, shift; ++ MV_U32 busClkPs; ++ MV_U8 trp_clocks=0, trcd_clocks, tras_clocks, trrd_clocks, ++ temp_buf[40], *spdRawData; ++ ++ busClkPs = 1000000000 / (mvBoardSysClkGet() / 100); /* in 10 ps units */ ++ ++ spdRawData = dimmInfo.spdRawData; ++ ++ if(MV_OK != dimmSpdGet(dimmNum, &dimmInfo)) ++ { ++ mvOsOutput("ERROR: Could not read SPD information!\n"); ++ return; ++ } ++ ++ /* find Manufactura of Dimm Module */ ++ mvOsOutput("\nManufacturer's JEDEC ID Code: "); ++ for(i = 0 ; i < DIMM_MODULE_MANU_SIZE ; i++) ++ { ++ mvOsOutput("%x",spdRawData[DIMM_MODULE_MANU_OFFS + i]); ++ } ++ mvOsOutput("\n"); ++ ++ /* Manufacturer's Specific Data */ ++ for(i = 0 ; i < DIMM_MODULE_ID_SIZE ; i++) ++ { ++ temp_buf[i] = spdRawData[DIMM_MODULE_ID_OFFS + i]; ++ } ++ mvOsOutput("Manufacturer's Specific Data: %s\n", temp_buf); ++ ++ /* Module Part Number */ ++ for(i = 0 ; i < DIMM_MODULE_VEN_SIZE ; i++) ++ { ++ temp_buf[i] = spdRawData[DIMM_MODULE_VEN_OFFS + i]; ++ } ++ mvOsOutput("Module Part Number: %s\n", temp_buf); ++ ++ /* Module Serial Number */ ++ for(i = 0; i < sizeof(MV_U32); i++) ++ { ++ temp |= spdRawData[95+i] << 8*i; ++ } ++ mvOsOutput("DIMM Serial No. %ld (%lx)\n", (long)temp, ++ (long)temp); ++ ++ /* find Manufac-Data of Dimm Module */ ++ mvOsOutput("Manufactoring Date: Year 20%d%d/ ww %d%d\n", ++ ((spdRawData[93] & 0xf0) >> 4), (spdRawData[93] & 0xf), ++ ((spdRawData[94] & 0xf0) >> 4), (spdRawData[94] & 0xf)); ++ /* find modul_revision of Dimm Module */ ++ mvOsOutput("Module Revision: %d.%d\n", ++ spdRawData[91], spdRawData[92]); ++ ++ /* find manufac_place of Dimm Module */ ++ mvOsOutput("manufac_place: %d\n", spdRawData[72]); ++ ++ /* go over the first 35 I2C data bytes */ ++ for(i = 2 ; i <= 35 ; i++) ++ switch(i) ++ { ++ case 2: /* Memory type (DDR1/2 / SDRAM) */ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ mvOsOutput("Dram Type is: SDRAM\n"); ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) ++ mvOsOutput("Dram Type is: SDRAM DDR1\n"); ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) ++ mvOsOutput("Dram Type is: SDRAM DDR2\n"); ++ else ++ mvOsOutput("Dram Type unknown\n"); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 3: /* Number Of Row Addresses */ ++ mvOsOutput("Module Number of row addresses: %d\n", ++ dimmInfo.numOfRowAddr); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 4: /* Number Of Column Addresses */ ++ mvOsOutput("Module Number of col addresses: %d\n", ++ dimmInfo.numOfColAddr); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 5: /* Number Of Module Banks */ ++ mvOsOutput("Number of Banks on Mod.: %d\n", ++ dimmInfo.numOfModuleBanks); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 6: /* Data Width */ ++ mvOsOutput("Module Data Width: %d bit\n", ++ dimmInfo.dataWidth); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 8: /* Voltage Interface */ ++ switch(spdRawData[i]) ++ { ++ case 0x0: ++ mvOsOutput("Module is TTL_5V_TOLERANT\n"); ++ break; ++ case 0x1: ++ mvOsOutput("Module is LVTTL\n"); ++ break; ++ case 0x2: ++ mvOsOutput("Module is HSTL_1_5V\n"); ++ break; ++ case 0x3: ++ mvOsOutput("Module is SSTL_3_3V\n"); ++ break; ++ case 0x4: ++ mvOsOutput("Module is SSTL_2_5V\n"); ++ break; ++ case 0x5: ++ if (dimmInfo.memoryType != MEM_TYPE_SDRAM) ++ { ++ mvOsOutput("Module is SSTL_1_8V\n"); ++ break; ++ } ++ default: ++ mvOsOutput("Module is VOLTAGE_UNKNOWN\n"); ++ break; ++ } ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 9: /* Minimum Cycle Time At Max CasLatancy */ ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ rightOfPoint = (spdRawData[i] & 0x0f) * 10; ++ ++ /* DDR2 addition of right of point */ ++ if ((spdRawData[i] & 0x0f) == 0xA) ++ { ++ rightOfPoint = 25; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xB) ++ { ++ rightOfPoint = 33; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xC) ++ { ++ rightOfPoint = 66; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xD) ++ { ++ rightOfPoint = 75; ++ } ++ mvOsOutput("Minimum Cycle Time At Max CL: %d.%d [ns]\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 10: /* Clock To Data Out */ ++ div = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 10:100; ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = time_tmp / div; ++ rightOfPoint = time_tmp % div; ++ mvOsOutput("Clock To Data Out: %d.%d [ns]\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 11: /* Error Check Type */ ++ mvOsOutput("Error Check Type (0=NONE): %d\n", ++ dimmInfo.errorCheckType); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 12: /* Refresh Interval */ ++ mvOsOutput("Refresh Rate: %x\n", ++ dimmInfo.refreshInterval); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 13: /* Sdram Width */ ++ mvOsOutput("Sdram Width: %d bits\n", ++ dimmInfo.sdramWidth); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 14: /* Error Check Data Width */ ++ mvOsOutput("Error Check Data Width: %d bits\n", ++ dimmInfo.errorCheckDataWidth); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 15: /* Minimum Clock Delay is unsupported */ ++ if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || ++ (dimmInfo.memoryType == MEM_TYPE_DDR1)) ++ { ++ mvOsOutput("Minimum Clk Delay back to back: %d\n", ++ spdRawData[i]); ++ } ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 16: /* Burst Length Supported */ ++ /* SDRAM/DDR1: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * ++ *********************************************************/ ++ /* DDR2: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * ++ *********************************************************/ ++ mvOsOutput("Burst Length Supported: "); ++ if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || ++ (dimmInfo.memoryType == MEM_TYPE_DDR1)) ++ { ++ if (dimmInfo.burstLengthSupported & BIT0) ++ mvOsOutput("1, "); ++ if (dimmInfo.burstLengthSupported & BIT1) ++ mvOsOutput("2, "); ++ } ++ if (dimmInfo.burstLengthSupported & BIT2) ++ mvOsOutput("4, "); ++ if (dimmInfo.burstLengthSupported & BIT3) ++ mvOsOutput("8, "); ++ ++ mvOsOutput(" Bit \n"); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 17: /* Number Of Banks On Each Device */ ++ mvOsOutput("Number Of Banks On Each Chip: %d\n", ++ dimmInfo.numOfBanksOnEachDevice); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 18: /* Suported Cas Latencies */ ++ ++ /* SDRAM: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * ++ ********************************************************/ ++ ++ /* DDR 1: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * ++ *********************************************************/ ++ ++ /* DDR 2: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * ++ *********************************************************/ ++ ++ mvOsOutput("Suported Cas Latencies: (CL) "); ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ for (k = 0; k <=7; k++) ++ { ++ if (dimmInfo.suportedCasLatencies & (1 << k)) ++ mvOsOutput("%d, ", k+1); ++ } ++ } ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) ++ { ++ if (dimmInfo.suportedCasLatencies & BIT0) ++ mvOsOutput("1, "); ++ if (dimmInfo.suportedCasLatencies & BIT1) ++ mvOsOutput("1.5, "); ++ if (dimmInfo.suportedCasLatencies & BIT2) ++ mvOsOutput("2, "); ++ if (dimmInfo.suportedCasLatencies & BIT3) ++ mvOsOutput("2.5, "); ++ if (dimmInfo.suportedCasLatencies & BIT4) ++ mvOsOutput("3, "); ++ if (dimmInfo.suportedCasLatencies & BIT5) ++ mvOsOutput("3.5, "); ++ } ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) ++ { ++ if (dimmInfo.suportedCasLatencies & BIT2) ++ mvOsOutput("2, "); ++ if (dimmInfo.suportedCasLatencies & BIT3) ++ mvOsOutput("3, "); ++ if (dimmInfo.suportedCasLatencies & BIT4) ++ mvOsOutput("4, "); ++ if (dimmInfo.suportedCasLatencies & BIT5) ++ mvOsOutput("5, "); ++ } ++ else ++ mvOsOutput("?.?, "); ++ mvOsOutput("\n"); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 20: /* DDR2 DIMM type info */ ++ if (dimmInfo.memoryType == MEM_TYPE_DDR2) ++ { ++ if (dimmInfo.dimmTypeInfo & (BIT0 | BIT4)) ++ mvOsOutput("Registered DIMM (RDIMM)\n"); ++ else if (dimmInfo.dimmTypeInfo & (BIT1 | BIT5)) ++ mvOsOutput("Unbuffered DIMM (UDIMM)\n"); ++ else ++ mvOsOutput("Unknown DIMM type.\n"); ++ } ++ ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 21: /* SDRAM Modules Attributes */ ++ mvOsOutput("\nModule Attributes (SPD Byte 21): \n"); ++ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ if (dimmInfo.dimmAttributes & BIT0) ++ mvOsOutput(" Buffered Addr/Control Input: Yes\n"); ++ else ++ mvOsOutput(" Buffered Addr/Control Input: No\n"); ++ ++ if (dimmInfo.dimmAttributes & BIT1) ++ mvOsOutput(" Registered Addr/Control Input: Yes\n"); ++ else ++ mvOsOutput(" Registered Addr/Control Input: No\n"); ++ ++ if (dimmInfo.dimmAttributes & BIT2) ++ mvOsOutput(" On-Card PLL (clock): Yes \n"); ++ else ++ mvOsOutput(" On-Card PLL (clock): No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT3) ++ mvOsOutput(" Bufferd DQMB Input: Yes \n"); ++ else ++ mvOsOutput(" Bufferd DQMB Inputs: No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT4) ++ mvOsOutput(" Registered DQMB Inputs: Yes \n"); ++ else ++ mvOsOutput(" Registered DQMB Inputs: No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT5) ++ mvOsOutput(" Differential Clock Input: Yes \n"); ++ else ++ mvOsOutput(" Differential Clock Input: No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT6) ++ mvOsOutput(" redundant Row Addressing: Yes \n"); ++ else ++ mvOsOutput(" redundant Row Addressing: No \n"); ++ } ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) ++ { ++ if (dimmInfo.dimmAttributes & BIT0) ++ mvOsOutput(" Buffered Addr/Control Input: Yes\n"); ++ else ++ mvOsOutput(" Buffered Addr/Control Input: No\n"); ++ ++ if (dimmInfo.dimmAttributes & BIT1) ++ mvOsOutput(" Registered Addr/Control Input: Yes\n"); ++ else ++ mvOsOutput(" Registered Addr/Control Input: No\n"); ++ ++ if (dimmInfo.dimmAttributes & BIT2) ++ mvOsOutput(" On-Card PLL (clock): Yes \n"); ++ else ++ mvOsOutput(" On-Card PLL (clock): No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT3) ++ mvOsOutput(" FET Switch On-Card Enabled: Yes \n"); ++ else ++ mvOsOutput(" FET Switch On-Card Enabled: No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT4) ++ mvOsOutput(" FET Switch External Enabled: Yes \n"); ++ else ++ mvOsOutput(" FET Switch External Enabled: No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT5) ++ mvOsOutput(" Differential Clock Input: Yes \n"); ++ else ++ mvOsOutput(" Differential Clock Input: No \n"); ++ } ++ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ ++ { ++ mvOsOutput(" Number of Active Registers on the DIMM: %d\n", ++ (dimmInfo.dimmAttributes & 0x3) + 1); ++ ++ mvOsOutput(" Number of PLLs on the DIMM: %d\n", ++ ((dimmInfo.dimmAttributes) >> 2) & 0x3); ++ ++ if (dimmInfo.dimmAttributes & BIT4) ++ mvOsOutput(" FET Switch External Enabled: Yes \n"); ++ else ++ mvOsOutput(" FET Switch External Enabled: No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT6) ++ mvOsOutput(" Analysis probe installed: Yes \n"); ++ else ++ mvOsOutput(" Analysis probe installed: No \n"); ++ } ++ ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 22: /* Suported AutoPreCharge */ ++ mvOsOutput("\nModul Attributes (SPD Byte 22): \n"); ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ if ( spdRawData[i] & BIT0 ) ++ mvOsOutput(" Early Ras Precharge: Yes \n"); ++ else ++ mvOsOutput(" Early Ras Precharge: No \n"); ++ ++ if ( spdRawData[i] & BIT1 ) ++ mvOsOutput(" AutoPreCharge: Yes \n"); ++ else ++ mvOsOutput(" AutoPreCharge: No \n"); ++ ++ if ( spdRawData[i] & BIT2 ) ++ mvOsOutput(" Precharge All: Yes \n"); ++ else ++ mvOsOutput(" Precharge All: No \n"); ++ ++ if ( spdRawData[i] & BIT3 ) ++ mvOsOutput(" Write 1/ReadBurst: Yes \n"); ++ else ++ mvOsOutput(" Write 1/ReadBurst: No \n"); ++ ++ if ( spdRawData[i] & BIT4 ) ++ mvOsOutput(" lower VCC tolerance: 5%%\n"); ++ else ++ mvOsOutput(" lower VCC tolerance: 10%%\n"); ++ ++ if ( spdRawData[i] & BIT5 ) ++ mvOsOutput(" upper VCC tolerance: 5%%\n"); ++ else ++ mvOsOutput(" upper VCC tolerance: 10%%\n"); ++ } ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) ++ { ++ if ( spdRawData[i] & BIT0 ) ++ mvOsOutput(" Supports Weak Driver: Yes \n"); ++ else ++ mvOsOutput(" Supports Weak Driver: No \n"); ++ ++ if ( !(spdRawData[i] & BIT4) ) ++ mvOsOutput(" lower VCC tolerance: 0.2V\n"); ++ ++ if ( !(spdRawData[i] & BIT5) ) ++ mvOsOutput(" upper VCC tolerance: 0.2V\n"); ++ ++ if ( spdRawData[i] & BIT6 ) ++ mvOsOutput(" Concurrent Auto Preharge: Yes \n"); ++ else ++ mvOsOutput(" Concurrent Auto Preharge: No \n"); ++ ++ if ( spdRawData[i] & BIT7 ) ++ mvOsOutput(" Supports Fast AP: Yes \n"); ++ else ++ mvOsOutput(" Supports Fast AP: No \n"); ++ } ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) ++ { ++ if ( spdRawData[i] & BIT0 ) ++ mvOsOutput(" Supports Weak Driver: Yes \n"); ++ else ++ mvOsOutput(" Supports Weak Driver: No \n"); ++ } ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 23: ++ /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */ ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ rightOfPoint = (spdRawData[i] & 0x0f) * 10; ++ ++ /* DDR2 addition of right of point */ ++ if ((spdRawData[i] & 0x0f) == 0xA) ++ { ++ rightOfPoint = 25; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xB) ++ { ++ rightOfPoint = 33; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xC) ++ { ++ rightOfPoint = 66; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xD) ++ { ++ rightOfPoint = 75; ++ } ++ ++ mvOsOutput("Minimum Cycle Time At 2nd highest CasLatancy" ++ "(0 = Not supported): %d.%d [ns]\n", ++ leftOfPoint, rightOfPoint ); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 24: /* Clock To Data Out 2nd highest Cas Latency Value*/ ++ div = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? 10:100; ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = time_tmp / div; ++ rightOfPoint = time_tmp % div; ++ mvOsOutput("Clock To Data Out (2nd CL value): %d.%d [ns]\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 25: ++ /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ leftOfPoint = (spdRawData[i] & 0xfc) >> 2; ++ rightOfPoint = (spdRawData[i] & 0x3) * 25; ++ } ++ else /* DDR1 or DDR2 */ ++ { ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ rightOfPoint = (spdRawData[i] & 0x0f) * 10; ++ ++ /* DDR2 addition of right of point */ ++ if ((spdRawData[i] & 0x0f) == 0xA) ++ { ++ rightOfPoint = 25; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xB) ++ { ++ rightOfPoint = 33; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xC) ++ { ++ rightOfPoint = 66; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xD) ++ { ++ rightOfPoint = 75; ++ } ++ } ++ mvOsOutput("Minimum Cycle Time At 3rd highest CasLatancy" ++ "(0 = Not supported): %d.%d [ns]\n", ++ leftOfPoint, rightOfPoint ); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 26: /* Clock To Data Out 3rd highest Cas Latency Value*/ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ leftOfPoint = (spdRawData[i] & 0xfc) >> 2; ++ rightOfPoint = (spdRawData[i] & 0x3) * 25; ++ } ++ else /* DDR1 or DDR2 */ ++ { ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = 0; ++ rightOfPoint = time_tmp; ++ } ++ mvOsOutput("Clock To Data Out (3rd CL value): %d.%2d[ns]\n", ++ leftOfPoint, rightOfPoint ); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 27: /* Minimum Row Precharge Time */ ++ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; ++ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? ++ 0xff : 0xfc; ++ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? ++ 0x00 : 0x03; ++ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); ++ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; ++ temp = ((leftOfPoint*100) + rightOfPoint);/* in 10ps Intervals*/ ++ trp_clocks = (temp + (busClkPs-1)) / busClkPs; ++ mvOsOutput("Minimum Row Precharge Time [ns]: %d.%d = " ++ "in Clk cycles %d\n", ++ leftOfPoint, rightOfPoint, trp_clocks); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 28: /* Minimum Row Active to Row Active Time */ ++ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; ++ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? ++ 0xff : 0xfc; ++ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? ++ 0x00 : 0x03; ++ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); ++ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; ++ temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ ++ trrd_clocks = (temp + (busClkPs-1)) / busClkPs; ++ mvOsOutput("Minimum Row Active -To- Row Active Delay [ns]: " ++ "%d.%d = in Clk cycles %d\n", ++ leftOfPoint, rightOfPoint, trp_clocks); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 29: /* Minimum Ras-To-Cas Delay */ ++ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; ++ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? ++ 0xff : 0xfc; ++ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? ++ 0x00 : 0x03; ++ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); ++ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; ++ temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ ++ trcd_clocks = (temp + (busClkPs-1) )/ busClkPs; ++ mvOsOutput("Minimum Ras-To-Cas Delay [ns]: %d.%d = " ++ "in Clk cycles %d\n", ++ leftOfPoint, rightOfPoint, trp_clocks); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 30: /* Minimum Ras Pulse Width */ ++ tras_clocks = (cas2ps(spdRawData[i])+(busClkPs-1)) / busClkPs; ++ mvOsOutput("Minimum Ras Pulse Width [ns]: %d = " ++ "in Clk cycles %d\n", spdRawData[i], tras_clocks); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 31: /* Module Bank Density */ ++ mvOsOutput("Module Bank Density (more than 1= Multisize-Module):"); ++ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ if (dimmInfo.dimmBankDensity & BIT0) ++ mvOsOutput("1GB, "); ++ if (dimmInfo.dimmBankDensity & BIT1) ++ mvOsOutput("8MB, "); ++ if (dimmInfo.dimmBankDensity & BIT2) ++ mvOsOutput("16MB, "); ++ if (dimmInfo.dimmBankDensity & BIT3) ++ mvOsOutput("32MB, "); ++ if (dimmInfo.dimmBankDensity & BIT4) ++ mvOsOutput("64MB, "); ++ if (dimmInfo.dimmBankDensity & BIT5) ++ mvOsOutput("128MB, "); ++ if (dimmInfo.dimmBankDensity & BIT6) ++ mvOsOutput("256MB, "); ++ if (dimmInfo.dimmBankDensity & BIT7) ++ mvOsOutput("512MB, "); ++ } ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) ++ { ++ if (dimmInfo.dimmBankDensity & BIT0) ++ mvOsOutput("1GB, "); ++ if (dimmInfo.dimmBankDensity & BIT1) ++ mvOsOutput("2GB, "); ++ if (dimmInfo.dimmBankDensity & BIT2) ++ mvOsOutput("16MB, "); ++ if (dimmInfo.dimmBankDensity & BIT3) ++ mvOsOutput("32MB, "); ++ if (dimmInfo.dimmBankDensity & BIT4) ++ mvOsOutput("64MB, "); ++ if (dimmInfo.dimmBankDensity & BIT5) ++ mvOsOutput("128MB, "); ++ if (dimmInfo.dimmBankDensity & BIT6) ++ mvOsOutput("256MB, "); ++ if (dimmInfo.dimmBankDensity & BIT7) ++ mvOsOutput("512MB, "); ++ } ++ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ ++ { ++ if (dimmInfo.dimmBankDensity & BIT0) ++ mvOsOutput("1GB, "); ++ if (dimmInfo.dimmBankDensity & BIT1) ++ mvOsOutput("2GB, "); ++ if (dimmInfo.dimmBankDensity & BIT2) ++ mvOsOutput("4GB, "); ++ if (dimmInfo.dimmBankDensity & BIT3) ++ mvOsOutput("8GB, "); ++ if (dimmInfo.dimmBankDensity & BIT4) ++ mvOsOutput("16GB, "); ++ if (dimmInfo.dimmBankDensity & BIT5) ++ mvOsOutput("128MB, "); ++ if (dimmInfo.dimmBankDensity & BIT6) ++ mvOsOutput("256MB, "); ++ if (dimmInfo.dimmBankDensity & BIT7) ++ mvOsOutput("512MB, "); ++ } ++ mvOsOutput("\n"); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 32: /* Address And Command Setup Time (measured in ns/1000) */ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ rightOfPoint = (spdRawData[i] & 0x0f); ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ if(leftOfPoint > 7) ++ { ++ leftOfPoint *= -1; ++ } ++ } ++ else /* DDR1 or DDR2 */ ++ { ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = time_tmp / 100; ++ rightOfPoint = time_tmp % 100; ++ } ++ mvOsOutput("Address And Command Setup Time [ns]: %d.%d\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 33: /* Address And Command Hold Time */ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ rightOfPoint = (spdRawData[i] & 0x0f); ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ if(leftOfPoint > 7) ++ { ++ leftOfPoint *= -1; ++ } ++ } ++ else /* DDR1 or DDR2 */ ++ { ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = time_tmp / 100; ++ rightOfPoint = time_tmp % 100; ++ } ++ mvOsOutput("Address And Command Hold Time [ns]: %d.%d\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 34: /* Data Input Setup Time */ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ rightOfPoint = (spdRawData[i] & 0x0f); ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ if(leftOfPoint > 7) ++ { ++ leftOfPoint *= -1; ++ } ++ } ++ else /* DDR1 or DDR2 */ ++ { ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = time_tmp / 100; ++ rightOfPoint = time_tmp % 100; ++ } ++ mvOsOutput("Data Input Setup Time [ns]: %d.%d\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 35: /* Data Input Hold Time */ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ rightOfPoint = (spdRawData[i] & 0x0f); ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ if(leftOfPoint > 7) ++ { ++ leftOfPoint *= -1; ++ } ++ } ++ else /* DDR1 or DDR2 */ ++ { ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = time_tmp / 100; ++ rightOfPoint = time_tmp % 100; ++ } ++ mvOsOutput("Data Input Hold Time [ns]: %d.%d\n\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 36: /* Relevant for DDR2 only: Write Recovery Time */ ++ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> 2); ++ rightOfPoint = (spdRawData[i] & maskRightOfPoint) * 25; ++ mvOsOutput("Write Recovery Time [ns]: %d.%d\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ } ++ ++} ++ ++ ++/* ++ * translate ns.ns/10 coding of SPD timing values ++ * into ps unit values ++ */ ++/******************************************************************************* ++* cas2ps - Translate x.y ns parameter to pico-seconds values ++* ++* DESCRIPTION: ++* This function translates x.y nano seconds to its value in pico seconds. ++* For example 3.75ns will return 3750. ++* ++* INPUT: ++* spd_byte - DIMM SPD byte. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* value in pico seconds. ++* ++*******************************************************************************/ ++static MV_U32 cas2ps(MV_U8 spd_byte) ++{ ++ MV_U32 ns, ns10; ++ ++ /* isolate upper nibble */ ++ ns = (spd_byte >> 4) & 0x0F; ++ /* isolate lower nibble */ ++ ns10 = (spd_byte & 0x0F); ++ ++ if( ns10 < 10 ) { ++ ns10 *= 10; ++ } ++ else if( ns10 == 10 ) ++ ns10 = 25; ++ else if( ns10 == 11 ) ++ ns10 = 33; ++ else if( ns10 == 12 ) ++ ns10 = 66; ++ else if( ns10 == 13 ) ++ ns10 = 75; ++ else ++ { ++ mvOsOutput("cas2ps Err. unsupported cycle time.\n"); ++ } ++ ++ return (ns*1000 + ns10*10); ++} ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDram.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,191 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvDram ++#define __INCmvDram ++ ++#include "ddr1_2/mvDramIf.h" ++#include "twsi/mvTwsi.h" ++ ++#define MAX_DIMM_NUM 2 ++#define SPD_SIZE 128 ++ ++/* Dimm spd offsets */ ++#define DIMM_MEM_TYPE 2 ++#define DIMM_ROW_NUM 3 ++#define DIMM_COL_NUM 4 ++#define DIMM_MODULE_BANK_NUM 5 ++#define DIMM_DATA_WIDTH 6 ++#define DIMM_VOLT_IF 8 ++#define DIMM_MIN_CC_AT_MAX_CAS 9 ++#define DIMM_ERR_CHECK_TYPE 11 ++#define DIMM_REFRESH_INTERVAL 12 ++#define DIMM_SDRAM_WIDTH 13 ++#define DIMM_ERR_CHECK_DATA_WIDTH 14 ++#define DIMM_MIN_CLK_DEL 15 ++#define DIMM_BURST_LEN_SUP 16 ++#define DIMM_DEV_BANK_NUM 17 ++#define DIMM_SUP_CAL 18 ++#define DIMM_DDR2_TYPE_INFORMATION 20 /* DDR2 only */ ++#define DIMM_BUF_ADDR_CONT_IN 21 ++#define DIMM_MIN_CC_AT_MAX_CAS_MINUS1 23 ++#define DIMM_MIN_CC_AT_MAX_CAS_MINUS2 25 ++#define DIMM_MIN_ROW_PRECHARGE_TIME 27 ++#define DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE 28 ++#define DIMM_MIN_RAS_TO_CAS_DELAY 29 ++#define DIMM_MIN_RAS_PULSE_WIDTH 30 ++#define DIMM_BANK_DENSITY 31 ++#define DIMM_MIN_WRITE_RECOVERY_TIME 36 ++#define DIMM_MIN_WRITE_TO_READ_CMD_DELAY 37 ++#define DIMM_MIN_READ_TO_PRECH_CMD_DELAY 38 ++#define DIMM_MIN_REFRESH_TO_ACTIVATE_CMD 42 ++ ++/* Dimm Memory Type values */ ++#define DIMM_MEM_TYPE_SDRAM 0x4 ++#define DIMM_MEM_TYPE_DDR1 0x7 ++#define DIMM_MEM_TYPE_DDR2 0x8 ++ ++#define DIMM_MODULE_MANU_OFFS 64 ++#define DIMM_MODULE_MANU_SIZE 8 ++#define DIMM_MODULE_VEN_OFFS 73 ++#define DIMM_MODULE_VEN_SIZE 25 ++#define DIMM_MODULE_ID_OFFS 99 ++#define DIMM_MODULE_ID_SIZE 18 ++ ++/* enumeration for voltage levels. */ ++typedef enum _mvDimmVoltageIf ++{ ++ TTL_5V_TOLERANT, ++ LVTTL, ++ HSTL_1_5V, ++ SSTL_3_3V, ++ SSTL_2_5V, ++ VOLTAGE_UNKNOWN, ++} MV_DIMM_VOLTAGE_IF; ++ ++ ++/* enumaration for SDRAM CAS Latencies. */ ++typedef enum _mvDimmSdramCas ++{ ++ SD_CL_1 =1, ++ SD_CL_2, ++ SD_CL_3, ++ SD_CL_4, ++ SD_CL_5, ++ SD_CL_6, ++ SD_CL_7, ++ SD_FAULT ++}MV_DIMM_SDRAM_CAS; ++ ++ ++/* DIMM information structure */ ++typedef struct _mvDimmInfo ++{ ++ MV_MEMORY_TYPE memoryType; /* DDR or SDRAM */ ++ ++ MV_U8 spdRawData[SPD_SIZE]; /* Content of SPD-EEPROM copied 1:1 */ ++ ++ /* DIMM dimensions */ ++ MV_U32 numOfRowAddr; ++ MV_U32 numOfColAddr; ++ MV_U32 numOfModuleBanks; ++ MV_U32 dataWidth; ++ MV_U32 errorCheckType; /* ECC , PARITY..*/ ++ MV_U32 sdramWidth; /* 4,8,16 or 32 */ ++ MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ ++ MV_U32 burstLengthSupported; ++ MV_U32 numOfBanksOnEachDevice; ++ MV_U32 suportedCasLatencies; ++ MV_U32 refreshInterval; ++ MV_U32 dimmBankDensity; ++ MV_U32 dimmTypeInfo; /* DDR2 only */ ++ MV_U32 dimmAttributes; ++ ++ /* DIMM timing parameters */ ++ MV_U32 minCycleTimeAtMaxCasLatPs; ++ MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; ++ MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; ++ MV_U32 minRowPrechargeTime; ++ MV_U32 minRowActiveToRowActive; ++ MV_U32 minRasToCasDelay; ++ MV_U32 minRasPulseWidth; ++ MV_U32 minWriteRecoveryTime; /* DDR2 only */ ++ MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ ++ MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ ++ MV_U32 minRefreshToActiveCmd; /* DDR2 only */ ++ ++ /* Parameters calculated from the extracted DIMM information */ ++ MV_U32 size; /* 16,64,128,256 or 512 MByte in MB units */ ++ MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit in MB units */ ++ MV_U32 numberOfDevices; ++ ++} MV_DIMM_INFO; ++ ++ ++MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo); ++MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo); ++MV_VOID dimmSpdPrint(MV_U32 dimmNum); ++MV_STATUS dimmSpdCpy(MV_VOID); ++ ++#endif /* __INCmvDram */ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,1599 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++/* includes */ ++#include "ddr1_2/mvDramIf.h" ++#include "ctrlEnv/sys/mvCpuIf.h" ++ ++ ++ ++#ifdef MV_DEBUG ++#define DB(x) x ++#else ++#define DB(x) ++#endif ++ ++/* DRAM bank presence encoding */ ++#define BANK_PRESENT_CS0 0x1 ++#define BANK_PRESENT_CS0_CS1 0x3 ++#define BANK_PRESENT_CS0_CS2 0x5 ++#define BANK_PRESENT_CS0_CS1_CS2 0x7 ++#define BANK_PRESENT_CS0_CS2_CS3 0xd ++#define BANK_PRESENT_CS0_CS2_CS3_CS4 0xf ++ ++/* locals */ ++static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin); ++#if defined(MV_INC_BOARD_DDIM) ++static void sdramDDr2OdtConfig(MV_DRAM_BANK_INFO *pBankInfo); ++static MV_U32 dunitCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas); ++static MV_U32 sdramModeRegCalc(MV_U32 minCas); ++static MV_U32 sdramExtModeRegCalc(MV_DRAM_BANK_INFO *pBankInfo); ++static MV_U32 sdramAddrCtrlRegCalc(MV_DRAM_BANK_INFO *pBankInfo); ++static MV_U32 sdramConfigRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk); ++static MV_U32 minCasCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk, ++ MV_U32 forcedCl); ++static MV_U32 sdramTimeCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, ++ MV_U32 minCas, MV_U32 busClk); ++static MV_U32 sdramTimeCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, ++ MV_U32 busClk); ++ ++/******************************************************************************* ++* mvDramIfDetect - Prepare DRAM interface configuration values. ++* ++* DESCRIPTION: ++* This function implements the full DRAM detection and timing ++* configuration for best system performance. ++* Since this routine runs from a ROM device (Boot Flash), its stack ++* resides on RAM, that might be the system DRAM. Changing DRAM ++* configuration values while keeping vital data in DRAM is risky. That ++* is why the function does not preform the configuration setting but ++* prepare those in predefined 32bit registers (in this case IDMA ++* registers are used) for other routine to perform the settings. ++* The function will call for board DRAM SPD information for each DRAM ++* chip select. The function will then analyze those SPD parameters of ++* all DRAM banks in order to decide on DRAM configuration compatible ++* for all DRAM banks. ++* The function will set the CPU DRAM address decode registers. ++* Note: This routine prepares values that will overide configuration of ++* mvDramBasicAsmInit(). ++* ++* INPUT: ++* forcedCl - Forced CAL Latency. If equal to zero, do not force. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_STATUS mvDramIfDetect(MV_U32 forcedCl) ++{ ++ MV_U32 retVal = MV_OK; /* return value */ ++ MV_DRAM_BANK_INFO bankInfo[MV_DRAM_MAX_CS]; ++ MV_U32 busClk, size, base = 0, i, temp, deviceW, dimmW; ++ MV_U8 minCas; ++ MV_DRAM_DEC_WIN dramDecWin; ++ ++ dramDecWin.addrWin.baseHigh = 0; ++ ++ busClk = mvBoardSysClkGet(); ++ ++ if (0 == busClk) ++ { ++ mvOsPrintf("Dram: ERR. Can't detect system clock! \n"); ++ return MV_ERROR; ++ } ++ ++ /* Close DRAM banks except bank 0 (in case code is excecuting from it...) */ ++#if defined(MV_INCLUDE_SDRAM_CS1) ++ for(i= SDRAM_CS1; i < MV_DRAM_MAX_CS; i++) ++ mvCpuIfTargetWinEnable(i, MV_FALSE); ++#endif ++ ++ /* we will use bank 0 as the representative of the all the DRAM banks, */ ++ /* since bank 0 must exist. */ ++ for(i = 0; i < MV_DRAM_MAX_CS; i++) ++ { ++ /* if Bank exist */ ++ if(MV_OK == mvDramBankInfoGet(i, &bankInfo[i])) ++ { ++ /* check it isn't SDRAM */ ++ if(bankInfo[i].memoryType == MEM_TYPE_SDRAM) ++ { ++ mvOsPrintf("Dram: ERR. SDRAM type not supported !!!\n"); ++ return MV_ERROR; ++ } ++ /* All banks must support registry in order to activate it */ ++ if(bankInfo[i].registeredAddrAndControlInputs != ++ bankInfo[0].registeredAddrAndControlInputs) ++ { ++ mvOsPrintf("Dram: ERR. different Registered settings !!!\n"); ++ return MV_ERROR; ++ } ++ ++ /* Init the CPU window decode */ ++ /* Note that the size in Bank info is in MB units */ ++ /* Note that the Dimm width might be different then the device DRAM width */ ++ temp = MV_REG_READ(SDRAM_CONFIG_REG); ++ ++ deviceW = ((temp & SDRAM_DWIDTH_MASK) == SDRAM_DWIDTH_16BIT )? 16 : 32; ++ dimmW = bankInfo[0].dataWidth - (bankInfo[0].dataWidth % 16); ++ size = ((bankInfo[i].size << 20) / (dimmW/deviceW)); ++ ++ /* We can not change DRAM window settings while excecuting */ ++ /* code from it. That is why we skip the DRAM CS[0], saving */ ++ /* it to the ROM configuration routine */ ++ if(i == SDRAM_CS0) ++ { ++ MV_U32 sizeToReg; ++ ++ /* Translate the given window size to register format */ ++ sizeToReg = ctrlSizeToReg(size, SCSR_SIZE_ALIGNMENT); ++ ++ /* Size parameter validity check. */ ++ if (-1 == sizeToReg) ++ { ++ mvOsPrintf("mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n" ++ ,i); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Size is located at upper 16 bits */ ++ sizeToReg <<= SCSR_SIZE_OFFS; ++ ++ /* enable it */ ++ sizeToReg |= SCSR_WIN_EN; ++ ++ MV_REG_WRITE(DRAM_BUF_REG0, sizeToReg); ++ } ++ else ++ { ++ dramDecWin.addrWin.baseLow = base; ++ dramDecWin.addrWin.size = size; ++ dramDecWin.enable = MV_TRUE; ++ ++ if (MV_OK != mvDramIfWinSet(SDRAM_CS0 + i, &dramDecWin)) ++ { ++ mvOsPrintf("Dram: ERR. Fail to set bank %d!!!\n", ++ SDRAM_CS0 + i); ++ return MV_ERROR; ++ } ++ } ++ ++ base += size; ++ ++ /* update the suportedCasLatencies mask */ ++ bankInfo[0].suportedCasLatencies &= bankInfo[i].suportedCasLatencies; ++ ++ } ++ else ++ { ++ if( i == 0 ) /* bank 0 doesn't exist */ ++ { ++ mvOsPrintf("Dram: ERR. Fail to detect bank 0 !!!\n"); ++ return MV_ERROR; ++ } ++ else ++ { ++ DB(mvOsPrintf("Dram: Could not find bank %d\n", i)); ++ bankInfo[i].size = 0; /* Mark this bank as non exist */ ++ } ++ } ++ } ++ ++ /* calculate minimum CAS */ ++ minCas = minCasCalc(&bankInfo[0], busClk, forcedCl); ++ if (0 == minCas) ++ { ++ mvOsOutput("Dram: Warn: Could not find CAS compatible to SysClk %dMhz\n", ++ (busClk / 1000000)); ++ ++ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) ++ { ++ minCas = DDR2_CL_4; /* Continue with this CAS */ ++ mvOsPrintf("Set default CAS latency 4\n"); ++ } ++ else ++ { ++ minCas = DDR1_CL_3; /* Continue with this CAS */ ++ mvOsPrintf("Set default CAS latency 3\n"); ++ } ++ } ++ ++ /* calc SDRAM_CONFIG_REG and save it to temp register */ ++ temp = sdramConfigRegCalc(&bankInfo[0], busClk); ++ if(-1 == temp) ++ { ++ mvOsPrintf("Dram: ERR. sdramConfigRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ MV_REG_WRITE(DRAM_BUF_REG1, temp); ++ ++ /* calc SDRAM_MODE_REG and save it to temp register */ ++ temp = sdramModeRegCalc(minCas); ++ if(-1 == temp) ++ { ++ mvOsPrintf("Dram: ERR. sdramModeRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ MV_REG_WRITE(DRAM_BUF_REG2, temp); ++ ++ /* calc SDRAM_EXTENDED_MODE_REG and save it to temp register */ ++ temp = sdramExtModeRegCalc(&bankInfo[0]); ++ if(-1 == temp) ++ { ++ mvOsPrintf("Dram: ERR. sdramModeRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ MV_REG_WRITE(DRAM_BUF_REG10, temp); ++ ++ /* calc D_UNIT_CONTROL_LOW and save it to temp register */ ++ temp = dunitCtrlLowRegCalc(&bankInfo[0], minCas); ++ if(-1 == temp) ++ { ++ mvOsPrintf("Dram: ERR. dunitCtrlLowRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ MV_REG_WRITE(DRAM_BUF_REG3, temp); ++ ++ /* calc SDRAM_ADDR_CTRL_REG and save it to temp register */ ++ temp = sdramAddrCtrlRegCalc(&bankInfo[0]); ++ if(-1 == temp) ++ { ++ mvOsPrintf("Dram: ERR. sdramAddrCtrlRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ MV_REG_WRITE(DRAM_BUF_REG4, temp); ++ ++ /* calc SDRAM_TIMING_CTRL_LOW_REG and save it to temp register */ ++ temp = sdramTimeCtrlLowRegCalc(&bankInfo[0], minCas, busClk); ++ if(-1 == temp) ++ { ++ mvOsPrintf("Dram: ERR. sdramTimeCtrlLowRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ MV_REG_WRITE(DRAM_BUF_REG5, temp); ++ ++ /* calc SDRAM_TIMING_CTRL_HIGH_REG and save it to temp register */ ++ temp = sdramTimeCtrlHighRegCalc(&bankInfo[0], busClk); ++ if(-1 == temp) ++ { ++ mvOsPrintf("Dram: ERR. sdramTimeCtrlHighRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ MV_REG_WRITE(DRAM_BUF_REG6, temp); ++ ++ /* Config DDR2 On Die Termination (ODT) registers */ ++ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) ++ { ++ sdramDDr2OdtConfig(bankInfo); ++ } ++ ++ /* Note that DDR SDRAM Address/Control and Data pad calibration */ ++ /* settings is done in mvSdramIfConfig.s */ ++ ++ return retVal; ++} ++ ++/******************************************************************************* ++* minCasCalc - Calculate the Minimum CAS latency which can be used. ++* ++* DESCRIPTION: ++* Calculate the minimum CAS latency that can be used, base on the DRAM ++* parameters and the SDRAM bus Clock freq. ++* ++* INPUT: ++* busClk - the DRAM bus Clock. ++* pBankInfo - bank info parameters. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* The minimum CAS Latency. The function returns 0 if max CAS latency ++* supported by banks is incompatible with system bus clock frequancy. ++* ++*******************************************************************************/ ++static MV_U32 minCasCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk, ++ MV_U32 forcedCl) ++{ ++ MV_U32 count = 1, j; ++ MV_U32 busClkPs = 1000000000 / (busClk / 1000); /* in ps units */ ++ MV_U32 startBit, stopBit; ++ ++ /* DDR 1: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * ++ *********************************************************/ ++ ++ /* DDR 2: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * ++ *********************************************************/ ++ ++ ++ /* If we are asked to use the forced CAL */ ++ if (forcedCl) ++ { ++ mvOsPrintf("DRAM: Using forced CL %d.%d\n", (forcedCl / 10), ++ (forcedCl % 10)); ++ ++ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) ++ { ++ if (forcedCl == 30) ++ pBankInfo->suportedCasLatencies = 0x08; ++ else if (forcedCl == 40) ++ pBankInfo->suportedCasLatencies = 0x10; ++ else ++ { ++ mvOsPrintf("Forced CL %d.%d not supported. Set default CL 4\n", ++ (forcedCl / 10), (forcedCl % 10)); ++ pBankInfo->suportedCasLatencies = 0x10; ++ } ++ } ++ else ++ { ++ if (forcedCl == 15) ++ pBankInfo->suportedCasLatencies = 0x02; ++ else if (forcedCl == 20) ++ pBankInfo->suportedCasLatencies = 0x04; ++ else if (forcedCl == 25) ++ pBankInfo->suportedCasLatencies = 0x08; ++ else if (forcedCl == 30) ++ pBankInfo->suportedCasLatencies = 0x10; ++ else if (forcedCl == 40) ++ pBankInfo->suportedCasLatencies = 0x40; ++ else ++ { ++ mvOsPrintf("Forced CL %d.%d not supported. Set default CL 3\n", ++ (forcedCl / 10), (forcedCl % 10)); ++ pBankInfo->suportedCasLatencies = 0x10; ++ } ++ } ++ ++ return pBankInfo->suportedCasLatencies; ++ } ++ ++ /* go over the supported cas mask from Max Cas down and check if the */ ++ /* SysClk stands in its time requirments. */ ++ ++ ++ DB(mvOsPrintf("Dram: minCasCalc supported mask = %x busClkPs = %x \n", ++ pBankInfo->suportedCasLatencies,busClkPs )); ++ for(j = 7; j > 0; j--) ++ { ++ if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) ++ { ++ /* Reset the bits for CL incompatible for the sysClk */ ++ switch (count) ++ { ++ case 1: ++ if (pBankInfo->minCycleTimeAtMaxCasLatPs > busClkPs) ++ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); ++ count++; ++ break; ++ case 2: ++ if (pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps > busClkPs) ++ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); ++ count++; ++ break; ++ case 3: ++ if (pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps > busClkPs) ++ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); ++ count++; ++ break; ++ default: ++ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); ++ break; ++ } ++ } ++ } ++ ++ DB(mvOsPrintf("Dram: minCasCalc support = %x (after SysCC calc)\n", ++ pBankInfo->suportedCasLatencies )); ++ ++ /* SDRAM DDR1 controller supports CL 1.5 to 3.5 */ ++ /* SDRAM DDR2 controller supports CL 3 to 5 */ ++ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) ++ { ++ startBit = 3; /* DDR2 support CL start with CL3 (bit 3) */ ++ stopBit = 5; /* DDR2 support CL stops with CL5 (bit 5) */ ++ } ++ else ++ { ++ startBit = 1; /* DDR1 support CL start with CL1.5 (bit 3) */ ++ stopBit = 4; /* DDR1 support CL stops with CL3 (bit 4) */ ++ } ++ ++ for(j = startBit; j <= stopBit ; j++) ++ { ++ if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) ++ { ++ DB(mvOsPrintf("Dram: minCasCalc choose CAS %x \n",(BIT0 << j))); ++ return (BIT0 << j); ++ } ++ } ++ ++ return 0; ++} ++ ++/******************************************************************************* ++* sdramConfigRegCalc - Calculate sdram config register ++* ++* DESCRIPTION: Calculate sdram config register optimized value based ++* on the bank info parameters. ++* ++* INPUT: ++* pBankInfo - sdram bank parameters ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram config reg value. ++* ++*******************************************************************************/ ++static MV_U32 sdramConfigRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) ++{ ++ MV_U32 sdramConfig = 0; ++ MV_U32 refreshPeriod; ++ ++ busClk /= 1000000; /* we work with busClk in MHz */ ++ ++ sdramConfig = MV_REG_READ(SDRAM_CONFIG_REG); ++ ++ /* figure out the memory refresh internal */ ++ switch (pBankInfo->refreshInterval & 0xf) ++ { ++ case 0x0: /* refresh period is 15.625 usec */ ++ refreshPeriod = 15625; ++ break; ++ case 0x1: /* refresh period is 3.9 usec */ ++ refreshPeriod = 3900; ++ break; ++ case 0x2: /* refresh period is 7.8 usec */ ++ refreshPeriod = 7800; ++ break; ++ case 0x3: /* refresh period is 31.3 usec */ ++ refreshPeriod = 31300; ++ break; ++ case 0x4: /* refresh period is 62.5 usec */ ++ refreshPeriod = 62500; ++ break; ++ case 0x5: /* refresh period is 125 usec */ ++ refreshPeriod = 125000; ++ break; ++ default: /* refresh period undefined */ ++ mvOsPrintf("Dram: ERR. DRAM refresh period is unknown!\n"); ++ return -1; ++ } ++ ++ /* Now the refreshPeriod is in register format value */ ++ refreshPeriod = (busClk * refreshPeriod) / 1000; ++ ++ DB(mvOsPrintf("Dram: sdramConfigRegCalc calculated refresh interval %0x\n", ++ refreshPeriod)); ++ ++ /* make sure the refresh value is only 14 bits */ ++ if(refreshPeriod > SDRAM_REFRESH_MAX) ++ { ++ refreshPeriod = SDRAM_REFRESH_MAX; ++ DB(mvOsPrintf("Dram: sdramConfigRegCalc adjusted refresh interval %0x\n", ++ refreshPeriod)); ++ } ++ ++ /* Clear the refresh field */ ++ sdramConfig &= ~SDRAM_REFRESH_MASK; ++ ++ /* Set new value to refresh field */ ++ sdramConfig |= (refreshPeriod & SDRAM_REFRESH_MASK); ++ ++ /* registered DRAM ? */ ++ if ( pBankInfo->registeredAddrAndControlInputs ) ++ { ++ /* it's registered DRAM, so set the reg. DRAM bit */ ++ sdramConfig |= SDRAM_REGISTERED; ++ mvOsPrintf("DRAM Attribute: Registered address and control inputs.\n"); ++ } ++ ++ /* set DDR SDRAM devices configuration */ ++ sdramConfig &= ~SDRAM_DCFG_MASK; /* Clear Dcfg field */ ++ ++ switch (pBankInfo->sdramWidth) ++ { ++ case 8: /* memory is x8 */ ++ sdramConfig |= SDRAM_DCFG_X8_DEV; ++ DB(mvOsPrintf("Dram: sdramConfigRegCalc SDRAM device width x8\n")); ++ break; ++ case 16: ++ sdramConfig |= SDRAM_DCFG_X16_DEV; ++ DB(mvOsPrintf("Dram: sdramConfigRegCalc SDRAM device width x16\n")); ++ break; ++ default: /* memory width unsupported */ ++ mvOsPrintf("Dram: ERR. DRAM chip width is unknown!\n"); ++ return -1; ++ } ++ ++ /* Set static default settings */ ++ sdramConfig |= SDRAM_CONFIG_DV; ++ ++ DB(mvOsPrintf("Dram: sdramConfigRegCalc set sdramConfig to 0x%x\n", ++ sdramConfig)); ++ ++ return sdramConfig; ++} ++ ++/******************************************************************************* ++* sdramModeRegCalc - Calculate sdram mode register ++* ++* DESCRIPTION: Calculate sdram mode register optimized value based ++* on the bank info parameters and the minCas. ++* ++* INPUT: ++* minCas - minimum CAS supported. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram mode reg value. ++* ++*******************************************************************************/ ++static MV_U32 sdramModeRegCalc(MV_U32 minCas) ++{ ++ MV_U32 sdramMode; ++ ++ sdramMode = MV_REG_READ(SDRAM_MODE_REG); ++ ++ /* Clear CAS Latency field */ ++ sdramMode &= ~SDRAM_CL_MASK; ++ ++ mvOsPrintf("DRAM CAS Latency "); ++ ++ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) ++ { ++ switch (minCas) ++ { ++ case DDR2_CL_3: ++ sdramMode |= SDRAM_DDR2_CL_3; ++ mvOsPrintf("3.\n"); ++ break; ++ case DDR2_CL_4: ++ sdramMode |= SDRAM_DDR2_CL_4; ++ mvOsPrintf("4.\n"); ++ break; ++ case DDR2_CL_5: ++ sdramMode |= SDRAM_DDR2_CL_5; ++ mvOsPrintf("5.\n"); ++ break; ++ default: ++ mvOsPrintf("\nsdramModeRegCalc ERROR: Max. CL out of range\n"); ++ return -1; ++ } ++ sdramMode |= DDR2_MODE_REG_DV; ++ } ++ else /* DDR1 */ ++ { ++ switch (minCas) ++ { ++ case DDR1_CL_1_5: ++ sdramMode |= SDRAM_DDR1_CL_1_5; ++ mvOsPrintf("1.5\n"); ++ break; ++ case DDR1_CL_2: ++ sdramMode |= SDRAM_DDR1_CL_2; ++ mvOsPrintf("2\n"); ++ break; ++ case DDR1_CL_2_5: ++ sdramMode |= SDRAM_DDR1_CL_2_5; ++ mvOsPrintf("2.5\n"); ++ break; ++ case DDR1_CL_3: ++ sdramMode |= SDRAM_DDR1_CL_3; ++ mvOsPrintf("3\n"); ++ break; ++ case DDR1_CL_4: ++ sdramMode |= SDRAM_DDR1_CL_4; ++ mvOsPrintf("4\n"); ++ break; ++ default: ++ mvOsPrintf("\nsdramModeRegCalc ERROR: Max. CL out of range\n"); ++ return -1; ++ } ++ sdramMode |= DDR1_MODE_REG_DV; ++ } ++ ++ DB(mvOsPrintf("nsdramModeRegCalc register 0x%x\n", sdramMode )); ++ ++ return sdramMode; ++} ++ ++/******************************************************************************* ++* sdramExtModeRegCalc - Calculate sdram Extended mode register ++* ++* DESCRIPTION: ++* Return sdram Extended mode register value based ++* on the bank info parameters and bank presence. ++* ++* INPUT: ++* pBankInfo - sdram bank parameters ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram Extended mode reg value. ++* ++*******************************************************************************/ ++static MV_U32 sdramExtModeRegCalc(MV_DRAM_BANK_INFO *pBankInfo) ++{ ++ MV_U32 populateBanks = 0; ++ int bankNum; ++ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) ++ { ++ /* Represent the populate banks in binary form */ ++ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) ++ { ++ if (0 != pBankInfo[bankNum].size) ++ { ++ populateBanks |= (1 << bankNum); ++ } ++ } ++ ++ switch(populateBanks) ++ { ++ case(BANK_PRESENT_CS0): ++ return DDR_SDRAM_EXT_MODE_CS0_DV; ++ ++ case(BANK_PRESENT_CS0_CS1): ++ return DDR_SDRAM_EXT_MODE_CS0_DV; ++ ++ case(BANK_PRESENT_CS0_CS2): ++ return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; ++ ++ case(BANK_PRESENT_CS0_CS1_CS2): ++ return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; ++ ++ case(BANK_PRESENT_CS0_CS2_CS3): ++ return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; ++ ++ case(BANK_PRESENT_CS0_CS2_CS3_CS4): ++ return DDR_SDRAM_EXT_MODE_CS0_CS2_DV; ++ ++ default: ++ mvOsPrintf("sdramExtModeRegCalc: Invalid DRAM bank presence\n"); ++ return -1; ++ } ++ } ++ return 0; ++} ++ ++/******************************************************************************* ++* dunitCtrlLowRegCalc - Calculate sdram dunit control low register ++* ++* DESCRIPTION: Calculate sdram dunit control low register optimized value based ++* on the bank info parameters and the minCas. ++* ++* INPUT: ++* pBankInfo - sdram bank parameters ++* minCas - minimum CAS supported. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram dunit control low reg value. ++* ++*******************************************************************************/ ++static MV_U32 dunitCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas) ++{ ++ MV_U32 dunitCtrlLow; ++ ++ dunitCtrlLow = MV_REG_READ(SDRAM_DUNIT_CTRL_REG); ++ ++ /* Clear StBurstDel field */ ++ dunitCtrlLow &= ~SDRAM_ST_BURST_DEL_MASK; ++ ++#ifdef MV_88W8660 ++ /* Clear address/control output timing field */ ++ dunitCtrlLow &= ~SDRAM_CTRL_POS_RISE; ++#endif /* MV_88W8660 */ ++ ++ DB(mvOsPrintf("Dram: dunitCtrlLowRegCalc\n")); ++ ++ /* For proper sample of read data set the Dunit Control register's */ ++ /* stBurstDel bits [27:24] */ ++ /********-********-********-********-********-********* ++ * CL=1.5 | CL=2 | CL=2.5 | CL=3 | CL=4 | CL=5 * ++ *********-********-********-********-********-********* ++Not Reg. * 0011 | 0011 | 0100 | 0100 | 0101 | TBD * ++ *********-********-********-********-********-********* ++Registered * 0100 | 0100 | 0101 | 0101 | 0110 | TBD * ++ *********-********-********-********-********-*********/ ++ ++ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) ++ { ++ switch (minCas) ++ { ++ case DDR2_CL_3: ++ /* registerd DDR SDRAM? */ ++ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) ++ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; ++ else ++ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; ++ break; ++ case DDR2_CL_4: ++ /* registerd DDR SDRAM? */ ++ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) ++ dunitCtrlLow |= 0x6 << SDRAM_ST_BURST_DEL_OFFS; ++ else ++ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; ++ break; ++ default: ++ mvOsPrintf("Dram: dunitCtrlLowRegCalc Max. CL out of range %d\n", ++ minCas); ++ return -1; ++ } ++ } ++ else /* DDR1 */ ++ { ++ switch (minCas) ++ { ++ case DDR1_CL_1_5: ++ /* registerd DDR SDRAM? */ ++ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) ++ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; ++ else ++ dunitCtrlLow |= 0x3 << SDRAM_ST_BURST_DEL_OFFS; ++ break; ++ case DDR1_CL_2: ++ /* registerd DDR SDRAM? */ ++ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) ++ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; ++ else ++ dunitCtrlLow |= 0x3 << SDRAM_ST_BURST_DEL_OFFS; ++ break; ++ case DDR1_CL_2_5: ++ /* registerd DDR SDRAM? */ ++ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) ++ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; ++ else ++ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; ++ break; ++ case DDR1_CL_3: ++ /* registerd DDR SDRAM? */ ++ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) ++ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; ++ else ++ dunitCtrlLow |= 0x4 << SDRAM_ST_BURST_DEL_OFFS; ++ break; ++ case DDR1_CL_4: ++ /* registerd DDR SDRAM? */ ++ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) ++ dunitCtrlLow |= 0x6 << SDRAM_ST_BURST_DEL_OFFS; ++ else ++ dunitCtrlLow |= 0x5 << SDRAM_ST_BURST_DEL_OFFS; ++ break; ++ default: ++ mvOsPrintf("Dram: dunitCtrlLowRegCalc Max. CL out of range %d\n", ++ minCas); ++ return -1; ++ } ++ ++ } ++ DB(mvOsPrintf("Dram: Reg dunit control low = %x\n", dunitCtrlLow )); ++ ++ return dunitCtrlLow; ++} ++ ++/******************************************************************************* ++* sdramAddrCtrlRegCalc - Calculate sdram address control register ++* ++* DESCRIPTION: Calculate sdram address control register optimized value based ++* on the bank info parameters and the minCas. ++* ++* INPUT: ++* pBankInfo - sdram bank parameters ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram address control reg value. ++* ++*******************************************************************************/ ++static MV_U32 sdramAddrCtrlRegCalc(MV_DRAM_BANK_INFO *pBankInfo) ++{ ++ MV_U32 addrCtrl = 0; ++ ++ /* Set Address Control register static configuration bits */ ++ addrCtrl = MV_REG_READ(SDRAM_ADDR_CTRL_REG); ++ ++ /* Set address control default value */ ++ addrCtrl |= SDRAM_ADDR_CTRL_DV; ++ ++ /* Clear DSize field */ ++ addrCtrl &= ~SDRAM_DSIZE_MASK; ++ ++ /* Note that density is in MB units */ ++ switch (pBankInfo->deviceDensity) ++ { ++ case 128: /* 128 Mbit */ ++ DB(mvOsPrintf("DRAM Device Density 128Mbit\n")); ++ addrCtrl |= SDRAM_DSIZE_128Mb; ++ break; ++ case 256: /* 256 Mbit */ ++ DB(mvOsPrintf("DRAM Device Density 256Mbit\n")); ++ addrCtrl |= SDRAM_DSIZE_256Mb; ++ break; ++ case 512: /* 512 Mbit */ ++ DB(mvOsPrintf("DRAM Device Density 512Mbit\n")); ++ addrCtrl |= SDRAM_DSIZE_512Mb; ++ break; ++ default: ++ mvOsPrintf("Dram: sdramAddrCtrl unsupported RAM-Device size %d\n", ++ pBankInfo->deviceDensity); ++ return -1; ++ } ++ ++ /* SDRAM address control */ ++ DB(mvOsPrintf("Dram: setting sdram address control with: %x \n", addrCtrl)); ++ ++ return addrCtrl; ++} ++ ++/******************************************************************************* ++* sdramTimeCtrlLowRegCalc - Calculate sdram timing control low register ++* ++* DESCRIPTION: ++* This function calculates sdram timing control low register ++* optimized value based on the bank info parameters and the minCas. ++* ++* INPUT: ++* pBankInfo - sdram bank parameters ++* busClk - Bus clock ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram timinf control low reg value. ++* ++*******************************************************************************/ ++static MV_U32 sdramTimeCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, ++ MV_U32 minCas, MV_U32 busClk) ++{ ++ MV_U32 tRp = 0; ++ MV_U32 tRrd = 0; ++ MV_U32 tRcd = 0; ++ MV_U32 tRas = 0; ++ MV_U32 tWr = 0; ++ MV_U32 tWtr = 0; ++ MV_U32 tRtp = 0; ++ ++ MV_U32 bankNum; ++ ++ busClk = busClk / 1000000; /* In MHz */ ++ ++ /* Scan all DRAM banks to find maximum timing values */ ++ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) ++ { ++ tRp = MV_MAX(tRp, pBankInfo[bankNum].minRowPrechargeTime); ++ tRrd = MV_MAX(tRrd, pBankInfo[bankNum].minRowActiveToRowActive); ++ tRcd = MV_MAX(tRcd, pBankInfo[bankNum].minRasToCasDelay); ++ tRas = MV_MAX(tRas, pBankInfo[bankNum].minRasPulseWidth); ++ } ++ ++ /* Extract timing (in ns) from SPD value. We ignore the tenth ns part. */ ++ /* by shifting the data two bits right. */ ++ tRp = tRp >> 2; /* For example 0x50 -> 20ns */ ++ tRrd = tRrd >> 2; ++ tRcd = tRcd >> 2; ++ ++ /* Extract clock cycles from time parameter. We need to round up */ ++ tRp = ((busClk * tRp) / 1000) + (((busClk * tRp) % 1000) ? 1 : 0); ++ /* Micron work around for 133MHz */ ++ if (busClk == 133) ++ tRp += 1; ++ DB(mvOsPrintf("Dram Timing Low: tRp = %d ", tRp)); ++ tRrd = ((busClk * tRrd) / 1000) + (((busClk * tRrd) % 1000) ? 1 : 0); ++ /* JEDEC min reqeirments tRrd = 2 */ ++ if (tRrd < 2) ++ tRrd = 2; ++ DB(mvOsPrintf("tRrd = %d ", tRrd)); ++ tRcd = ((busClk * tRcd) / 1000) + (((busClk * tRcd) % 1000) ? 1 : 0); ++ DB(mvOsPrintf("tRcd = %d ", tRcd)); ++ tRas = ((busClk * tRas) / 1000) + (((busClk * tRas) % 1000) ? 1 : 0); ++ DB(mvOsPrintf("tRas = %d ", tRas)); ++ ++ /* tWr and tWtr is different for DDR1 and DDR2. tRtp is only for DDR2 */ ++ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) ++ { ++ /* Scan all DRAM banks to find maximum timing values */ ++ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) ++ { ++ tWr = MV_MAX(tWr, pBankInfo[bankNum].minWriteRecoveryTime); ++ tWtr = MV_MAX(tWtr, pBankInfo[bankNum].minWriteToReadCmdDelay); ++ tRtp = MV_MAX(tRtp, pBankInfo[bankNum].minReadToPrechCmdDelay); ++ } ++ ++ /* Extract timing (in ns) from SPD value. We ignore the tenth ns */ ++ /* part by shifting the data two bits right. */ ++ tWr = tWr >> 2; /* For example 0x50 -> 20ns */ ++ tWtr = tWtr >> 2; ++ tRtp = tRtp >> 2; ++ ++ /* Extract clock cycles from time parameter. We need to round up */ ++ tWr = ((busClk * tWr) / 1000) + (((busClk * tWr) % 1000) ? 1 : 0); ++ DB(mvOsPrintf("tWr = %d ", tWr)); ++ tWtr = ((busClk * tWtr) / 1000) + (((busClk * tWtr) % 1000) ? 1 : 0); ++ /* JEDEC min reqeirments tWtr = 2 */ ++ if (tWtr < 2) ++ tWtr = 2; ++ DB(mvOsPrintf("tWtr = %d ", tWtr)); ++ tRtp = ((busClk * tRtp) / 1000) + (((busClk * tRtp) % 1000) ? 1 : 0); ++ /* JEDEC min reqeirments tRtp = 2 */ ++ if (tRtp < 2) ++ tRtp = 2; ++ DB(mvOsPrintf("tRtp = %d ", tRtp)); ++ } ++ else ++ { ++ tWr = ((busClk*SDRAM_TWR) / 1000) + (((busClk*SDRAM_TWR) % 1000)?1:0); ++ ++ if ((200 == busClk) || ((100 == busClk) && (DDR1_CL_1_5 == minCas))) ++ { ++ tWtr = 2; ++ } ++ else ++ { ++ tWtr = 1; ++ } ++ ++ tRtp = 2; /* Must be set to 0x1 (two cycles) when using DDR1 */ ++ } ++ ++ DB(mvOsPrintf("tWtr = %d\n", tWtr)); ++ ++ /* Note: value of 0 in register means one cycle, 1 means two and so on */ ++ return (((tRp - 1) << SDRAM_TRP_OFFS) | ++ ((tRrd - 1) << SDRAM_TRRD_OFFS) | ++ ((tRcd - 1) << SDRAM_TRCD_OFFS) | ++ ((tRas - 1) << SDRAM_TRAS_OFFS) | ++ ((tWr - 1) << SDRAM_TWR_OFFS) | ++ ((tWtr - 1) << SDRAM_TWTR_OFFS) | ++ ((tRtp - 1) << SDRAM_TRTP_OFFS)); ++} ++ ++/******************************************************************************* ++* sdramTimeCtrlHighRegCalc - Calculate sdram timing control high register ++* ++* DESCRIPTION: ++* This function calculates sdram timing control high register ++* optimized value based on the bank info parameters and the bus clock. ++* ++* INPUT: ++* pBankInfo - sdram bank parameters ++* busClk - Bus clock ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram timinf control high reg value. ++* ++*******************************************************************************/ ++static MV_U32 sdramTimeCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, ++ MV_U32 busClk) ++{ ++ MV_U32 tRfc; ++ MV_U32 timeNs = 0; ++ int bankNum; ++ MV_U32 sdramTw2wCyc = 0; ++ ++ busClk = busClk / 1000000; /* In MHz */ ++ ++ /* tRfc is different for DDR1 and DDR2. */ ++ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_DTYPE_DDR2) ++ { ++ MV_U32 bankNum; ++ ++ /* Scan all DRAM banks to find maximum timing values */ ++ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) ++ timeNs = MV_MAX(timeNs, pBankInfo[bankNum].minRefreshToActiveCmd); ++ } ++ else ++ { ++ if (pBankInfo[0].deviceDensity == _1G) ++ { ++ timeNs = SDRAM_TRFC_1G; ++ } ++ else ++ { ++ if (200 == busClk) ++ { ++ timeNs = SDRAM_TRFC_64_512M_AT_200MHZ; ++ } ++ else ++ { ++ timeNs = SDRAM_TRFC_64_512M; ++ } ++ } ++ } ++ ++ tRfc = ((busClk * timeNs) / 1000) + (((busClk * timeNs) % 1000) ? 1 : 0); ++ ++ DB(mvOsPrintf("Dram Timing High: tRfc = %d\n", tRfc)); ++ ++ ++ /* Represent the populate banks in binary form */ ++ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) ++ { ++ if (0 != pBankInfo[bankNum].size) ++ sdramTw2wCyc++; ++ } ++ ++ /* If we have more the 1 bank then we need the TW2W in 1 for ODT switch */ ++ if (sdramTw2wCyc > 1) ++ sdramTw2wCyc = 1; ++ else ++ sdramTw2wCyc = 0; ++ ++ /* Note: value of 0 in register means one cycle, 1 means two and so on */ ++ return ((((tRfc - 1) & SDRAM_TRFC_MASK) << SDRAM_TRFC_OFFS) | ++ ((SDRAM_TR2R_CYC - 1) << SDRAM_TR2R_OFFS) | ++ ((SDRAM_TR2WW2R_CYC - 1) << SDRAM_TR2W_W2R_OFFS) | ++ (((tRfc - 1) >> 4) << SDRAM_TRFC_EXT_OFFS) | ++ (sdramTw2wCyc << SDRAM_TW2W_OFFS)); ++ ++} ++ ++/******************************************************************************* ++* sdramDDr2OdtConfig - Set DRAM DDR2 On Die Termination registers. ++* ++* DESCRIPTION: ++* This function config DDR2 On Die Termination (ODT) registers. ++* ODT configuration is done according to DIMM presence: ++* ++* Presence Ctrl Low Ctrl High Dunit Ctrl Ext Mode ++* CS0 0x84210000 0x00000000 0x0000780F 0x00000440 ++* CS0+CS1 0x84210000 0x00000000 0x0000780F 0x00000440 ++* CS0+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 ++* CS0+CS1+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 ++* CS0+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 ++* CS0+CS1+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 ++* ++* INPUT: ++* pBankInfo - bank info parameters. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* None ++*******************************************************************************/ ++static void sdramDDr2OdtConfig(MV_DRAM_BANK_INFO *pBankInfo) ++{ ++ MV_U32 populateBanks = 0; ++ MV_U32 odtCtrlLow, odtCtrlHigh, dunitOdtCtrl; ++ int bankNum; ++ ++ /* Represent the populate banks in binary form */ ++ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) ++ { ++ if (0 != pBankInfo[bankNum].size) ++ { ++ populateBanks |= (1 << bankNum); ++ } ++ } ++ ++ switch(populateBanks) ++ { ++ case(BANK_PRESENT_CS0): ++ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_DV; ++ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_DV; ++ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_DV; ++ break; ++ case(BANK_PRESENT_CS0_CS1): ++ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_DV; ++ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_DV; ++ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_DV; ++ break; ++ case(BANK_PRESENT_CS0_CS2): ++ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; ++ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; ++ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; ++ break; ++ case(BANK_PRESENT_CS0_CS1_CS2): ++ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; ++ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; ++ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; ++ break; ++ case(BANK_PRESENT_CS0_CS2_CS3): ++ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; ++ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; ++ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; ++ break; ++ case(BANK_PRESENT_CS0_CS2_CS3_CS4): ++ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS2_DV; ++ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS2_DV; ++ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV; ++ break; ++ default: ++ mvOsPrintf("sdramDDr2OdtConfig: Invalid DRAM bank presence\n"); ++ return; ++ } ++ MV_REG_WRITE(DRAM_BUF_REG7, odtCtrlLow); ++ MV_REG_WRITE(DRAM_BUF_REG8, odtCtrlHigh); ++ MV_REG_WRITE(DRAM_BUF_REG9, dunitOdtCtrl); ++ return; ++} ++#endif /* defined(MV_INC_BOARD_DDIM) */ ++ ++/******************************************************************************* ++* mvDramIfWinSet - Set DRAM interface address decode window ++* ++* DESCRIPTION: ++* This function sets DRAM interface address decode window. ++* ++* INPUT: ++* target - System target. Use only SDRAM targets. ++* pAddrDecWin - SDRAM address window structure. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK ++* otherwise. ++*******************************************************************************/ ++MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) ++{ ++ MV_U32 baseReg=0,sizeReg=0; ++ MV_U32 baseToReg=0 , sizeToReg=0; ++ ++ /* Check parameters */ ++ if (!MV_TARGET_IS_DRAM(target)) ++ { ++ mvOsPrintf("mvDramIfWinSet: target %d is not SDRAM\n", target); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check if the requested window overlaps with current enabled windows */ ++ if (MV_TRUE == sdramIfWinOverlap(target, &pAddrDecWin->addrWin)) ++ { ++ mvOsPrintf("mvDramIfWinSet: ERR. Target %d overlaps\n", target); ++ return MV_BAD_PARAM; ++ } ++ ++ /* check if address is aligned to the size */ ++ if(MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size)) ++ { ++ mvOsPrintf("mvDramIfWinSet:Error setting DRAM interface window %d."\ ++ "\nAddress 0x%08x is unaligned to size 0x%x.\n", ++ target, ++ pAddrDecWin->addrWin.baseLow, ++ pAddrDecWin->addrWin.size); ++ return MV_ERROR; ++ } ++ ++ /* read base register*/ ++ baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(target)); ++ ++ /* read size register */ ++ sizeReg = MV_REG_READ(SDRAM_SIZE_REG(target)); ++ ++ /* BaseLow[31:16] => base register [31:16] */ ++ baseToReg = pAddrDecWin->addrWin.baseLow & SCBAR_BASE_MASK; ++ ++ /* Write to address decode Base Address Register */ ++ baseReg &= ~SCBAR_BASE_MASK; ++ baseReg |= baseToReg; ++ ++ /* Translate the given window size to register format */ ++ sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, SCSR_SIZE_ALIGNMENT); ++ ++ /* Size parameter validity check. */ ++ if (-1 == sizeToReg) ++ { ++ mvOsPrintf("mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n",target); ++ return MV_BAD_PARAM; ++ } ++ ++ /* set size */ ++ sizeReg &= ~SCSR_SIZE_MASK; ++ /* Size is located at upper 16 bits */ ++ sizeReg |= (sizeToReg << SCSR_SIZE_OFFS); ++ ++ /* enable/Disable */ ++ if (MV_TRUE == pAddrDecWin->enable) ++ { ++ sizeReg |= SCSR_WIN_EN; ++ } ++ else ++ { ++ sizeReg &= ~SCSR_WIN_EN; ++ } ++ ++ /* 3) Write to address decode Base Address Register */ ++ MV_REG_WRITE(SDRAM_BASE_ADDR_REG(target), baseReg); ++ ++ /* Write to address decode Size Register */ ++ MV_REG_WRITE(SDRAM_SIZE_REG(target), sizeReg); ++ ++ return MV_OK; ++} ++/******************************************************************************* ++* mvDramIfWinGet - Get DRAM interface address decode window ++* ++* DESCRIPTION: ++* This function gets DRAM interface address decode window. ++* ++* INPUT: ++* target - System target. Use only SDRAM targets. ++* ++* OUTPUT: ++* pAddrDecWin - SDRAM address window structure. ++* ++* RETURN: ++* MV_BAD_PARAM if parameters are invalid or window is invalid, MV_OK ++* otherwise. ++*******************************************************************************/ ++MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin) ++{ ++ MV_U32 baseReg,sizeReg; ++ MV_U32 sizeRegVal; ++ ++ /* Check parameters */ ++ if (!MV_TARGET_IS_DRAM(target)) ++ { ++ mvOsPrintf("mvDramIfWinGet: target %d is Illigal\n", target); ++ return MV_ERROR; ++ } ++ ++ /* Read base and size registers */ ++ sizeReg = MV_REG_READ(SDRAM_SIZE_REG(target)); ++ baseReg = MV_REG_READ(SDRAM_BASE_ADDR_REG(target)); ++ ++ sizeRegVal = (sizeReg & SCSR_SIZE_MASK) >> SCSR_SIZE_OFFS; ++ ++ pAddrDecWin->addrWin.size = ctrlRegToSize(sizeRegVal, ++ SCSR_SIZE_ALIGNMENT); ++ ++ /* Check if ctrlRegToSize returned OK */ ++ if (-1 == pAddrDecWin->addrWin.size) ++ { ++ mvOsPrintf("mvDramIfWinGet: size of target %d is Illigal\n", target); ++ return MV_ERROR; ++ } ++ ++ /* Extract base address */ ++ /* Base register [31:16] ==> baseLow[31:16] */ ++ pAddrDecWin->addrWin.baseLow = baseReg & SCBAR_BASE_MASK; ++ ++ pAddrDecWin->addrWin.baseHigh = 0; ++ ++ ++ if (sizeReg & SCSR_WIN_EN) ++ { ++ pAddrDecWin->enable = MV_TRUE; ++ } ++ else ++ { ++ pAddrDecWin->enable = MV_FALSE; ++ } ++ ++ return MV_OK; ++} ++/******************************************************************************* ++* mvDramIfWinEnable - Enable/Disable SDRAM address decode window ++* ++* DESCRIPTION: ++* This function enable/Disable SDRAM address decode window. ++* ++* INPUT: ++* target - System target. Use only SDRAM targets. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_ERROR in case function parameter are invalid, MV_OK otherewise. ++* ++*******************************************************************************/ ++MV_STATUS mvDramIfWinEnable(MV_TARGET target,MV_BOOL enable) ++{ ++ MV_DRAM_DEC_WIN addrDecWin; ++ ++ /* Check parameters */ ++ if (!MV_TARGET_IS_DRAM(target)) ++ { ++ mvOsPrintf("mvDramIfWinEnable: target %d is Illigal\n", target); ++ return MV_ERROR; ++ } ++ ++ if (enable == MV_TRUE) ++ { /* First check for overlap with other enabled windows */ ++ if (MV_OK != mvDramIfWinGet(target, &addrDecWin)) ++ { ++ mvOsPrintf("mvDramIfWinEnable:ERR. Getting target %d failed.\n", ++ target); ++ return MV_ERROR; ++ } ++ /* Check for overlapping */ ++ if (MV_FALSE == sdramIfWinOverlap(target, &(addrDecWin.addrWin))) ++ { ++ /* No Overlap. Enable address decode winNum window */ ++ MV_REG_BIT_SET(SDRAM_SIZE_REG(target), SCSR_WIN_EN); ++ } ++ else ++ { /* Overlap detected */ ++ mvOsPrintf("mvDramIfWinEnable: ERR. Target %d overlap detect\n", ++ target); ++ return MV_ERROR; ++ } ++ } ++ else ++ { /* Disable address decode winNum window */ ++ MV_REG_BIT_RESET(SDRAM_SIZE_REG(target), SCSR_WIN_EN); ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* sdramIfWinOverlap - Check if an address window overlap an SDRAM address window ++* ++* DESCRIPTION: ++* This function scan each SDRAM address decode window to test if it ++* overlapps the given address windoow ++* ++* INPUT: ++* target - SDRAM target where the function skips checking. ++* pAddrDecWin - The tested address window for overlapping with ++* SDRAM windows. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if the given address window overlaps any enabled address ++* decode map, MV_FALSE otherwise. ++* ++*******************************************************************************/ ++static MV_BOOL sdramIfWinOverlap(MV_TARGET target, MV_ADDR_WIN *pAddrWin) ++{ ++ MV_TARGET targetNum; ++ MV_DRAM_DEC_WIN addrDecWin; ++ ++ for(targetNum = SDRAM_CS0; targetNum < MV_DRAM_MAX_CS ; targetNum++) ++ { ++ /* don't check our winNum or illegal targets */ ++ if (targetNum == target) ++ { ++ continue; ++ } ++ ++ /* Get window parameters */ ++ if (MV_OK != mvDramIfWinGet(targetNum, &addrDecWin)) ++ { ++ mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); ++ return MV_ERROR; ++ } ++ ++ /* Do not check disabled windows */ ++ if (MV_FALSE == addrDecWin.enable) ++ { ++ continue; ++ } ++ ++ if(MV_TRUE == ctrlWinOverlapTest(pAddrWin, &addrDecWin.addrWin)) ++ { ++ mvOsPrintf( ++ "sdramIfWinOverlap: Required target %d overlap winNum %d\n", ++ target, targetNum); ++ return MV_TRUE; ++ } ++ } ++ ++ return MV_FALSE; ++} ++ ++/******************************************************************************* ++* mvDramIfBankSizeGet - Get DRAM interface bank size. ++* ++* DESCRIPTION: ++* This function returns the size of a given DRAM bank. ++* ++* INPUT: ++* bankNum - Bank number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* DRAM bank size. If bank is disabled the function return '0'. In case ++* or paramter is invalid, the function returns -1. ++* ++*******************************************************************************/ ++MV_32 mvDramIfBankSizeGet(MV_U32 bankNum) ++{ ++ MV_DRAM_DEC_WIN addrDecWin; ++ ++ /* Check parameters */ ++ if (!MV_TARGET_IS_DRAM(bankNum)) ++ { ++ mvOsPrintf("mvDramIfBankBaseGet: bankNum %d is invalid\n", bankNum); ++ return -1; ++ } ++ /* Get window parameters */ ++ if (MV_OK != mvDramIfWinGet(bankNum, &addrDecWin)) ++ { ++ mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); ++ return -1; ++ } ++ ++ if (MV_TRUE == addrDecWin.enable) ++ { ++ return addrDecWin.addrWin.size; ++ } ++ else ++ { ++ return 0; ++ } ++} ++ ++ ++/******************************************************************************* ++* mvDramIfSizeGet - Get DRAM interface total size. ++* ++* DESCRIPTION: ++* This function get the DRAM total size. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* DRAM total size. In case or paramter is invalid, the function ++* returns -1. ++* ++*******************************************************************************/ ++MV_32 mvDramIfSizeGet(MV_VOID) ++{ ++ MV_U32 totalSize = 0, bankSize = 0, bankNum; ++ ++ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) ++ { ++ bankSize = mvDramIfBankSizeGet(bankNum); ++ ++ if (-1 == bankSize) ++ { ++ mvOsPrintf("Dram: mvDramIfSizeGet error with bank %d \n",bankNum); ++ return -1; ++ } ++ else ++ { ++ totalSize += bankSize; ++ } ++ } ++ ++ DB(mvOsPrintf("Dram: Total DRAM size is 0x%x \n",totalSize)); ++ ++ return totalSize; ++} ++ ++/******************************************************************************* ++* mvDramIfBankBaseGet - Get DRAM interface bank base. ++* ++* DESCRIPTION: ++* This function returns the 32 bit base address of a given DRAM bank. ++* ++* INPUT: ++* bankNum - Bank number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* DRAM bank size. If bank is disabled or paramter is invalid, the ++* function returns -1. ++* ++*******************************************************************************/ ++MV_32 mvDramIfBankBaseGet(MV_U32 bankNum) ++{ ++ MV_DRAM_DEC_WIN addrDecWin; ++ ++ /* Check parameters */ ++ if (!MV_TARGET_IS_DRAM(bankNum)) ++ { ++ mvOsPrintf("mvDramIfBankBaseGet: bankNum %d is invalid\n", bankNum); ++ return -1; ++ } ++ /* Get window parameters */ ++ if (MV_OK != mvDramIfWinGet(bankNum, &addrDecWin)) ++ { ++ mvOsPrintf("sdramIfWinOverlap: ERR. TargetWinGet failed\n"); ++ return -1; ++ } ++ ++ if (MV_TRUE == addrDecWin.enable) ++ { ++ return addrDecWin.addrWin.baseLow; ++ } ++ else ++ { ++ return -1; ++ } ++} ++ ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIf.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,179 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvDramIfh ++#define __INCmvDramIfh ++ ++/* includes */ ++#include "ddr1_2/mvDramIfRegs.h" ++#include "ddr1_2/mvDramIfConfig.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++ ++/* defines */ ++/* DRAM Timing parameters */ ++#define SDRAM_TWR 15 /* ns tWr */ ++#define SDRAM_TRFC_64_512M_AT_200MHZ 70 /* ns tRfc for dens 64-512 @ 200MHz */ ++#define SDRAM_TRFC_64_512M 75 /* ns tRfc for dens 64-512 */ ++#define SDRAM_TRFC_1G 120 /* ns tRfc for dens 1GB */ ++#define SDRAM_TR2R_CYC 1 /* cycle for tR2r */ ++#define SDRAM_TR2WW2R_CYC 1 /* cycle for tR2wW2r */ ++ ++/* typedefs */ ++ ++/* enumeration for memory types */ ++typedef enum _mvMemoryType ++{ ++ MEM_TYPE_SDRAM, ++ MEM_TYPE_DDR1, ++ MEM_TYPE_DDR2 ++}MV_MEMORY_TYPE; ++ ++/* enumeration for DDR1 supported CAS Latencies */ ++typedef enum _mvDimmDdr1Cas ++{ ++ DDR1_CL_1_5 = 0x02, ++ DDR1_CL_2 = 0x04, ++ DDR1_CL_2_5 = 0x08, ++ DDR1_CL_3 = 0x10, ++ DDR1_CL_4 = 0x40, ++ DDR1_CL_FAULT ++} MV_DIMM_DDR1_CAS; ++ ++/* enumeration for DDR2 supported CAS Latencies */ ++typedef enum _mvDimmDdr2Cas ++{ ++ DDR2_CL_3 = 0x08, ++ DDR2_CL_4 = 0x10, ++ DDR2_CL_5 = 0x20, ++ DDR2_CL_FAULT ++} MV_DIMM_DDR2_CAS; ++ ++ ++typedef struct _mvDramBankInfo ++{ ++ MV_MEMORY_TYPE memoryType; /* DDR1, DDR2 or SDRAM */ ++ ++ /* DIMM dimensions */ ++ MV_U32 numOfRowAddr; ++ MV_U32 numOfColAddr; ++ MV_U32 dataWidth; ++ MV_U32 errorCheckType; /* ECC , PARITY..*/ ++ MV_U32 sdramWidth; /* 4,8,16 or 32 */ ++ MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ ++ MV_U32 burstLengthSupported; ++ MV_U32 numOfBanksOnEachDevice; ++ MV_U32 suportedCasLatencies; ++ MV_U32 refreshInterval; ++ ++ /* DIMM timing parameters */ ++ MV_U32 minCycleTimeAtMaxCasLatPs; ++ MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; ++ MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; ++ MV_U32 minRowPrechargeTime; ++ MV_U32 minRowActiveToRowActive; ++ MV_U32 minRasToCasDelay; ++ MV_U32 minRasPulseWidth; ++ MV_U32 minWriteRecoveryTime; /* DDR2 only */ ++ MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ ++ MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ ++ MV_U32 minRefreshToActiveCmd; /* DDR2 only */ ++ ++ /* Parameters calculated from the extracted DIMM information */ ++ MV_U32 size; ++ MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit */ ++ MV_U32 numberOfDevices; ++ ++ /* DIMM attributes (MV_TRUE for yes) */ ++ MV_BOOL registeredAddrAndControlInputs; ++ ++}MV_DRAM_BANK_INFO; ++ ++/* This structure describes CPU interface address decode window */ ++typedef struct _mvDramIfDecWin ++{ ++ MV_ADDR_WIN addrWin; /* An address window*/ ++ MV_BOOL enable; /* Address decode window is enabled/disabled */ ++}MV_DRAM_DEC_WIN; ++ ++#include "ddr1_2/mvDram.h" ++ ++/* mvDramIf.h API list */ ++MV_VOID mvDramIfBasicAsmInit(MV_VOID); ++MV_STATUS mvDramIfDetect(MV_U32 forcedCl); ++MV_VOID _mvDramIfConfig(MV_VOID); ++ ++MV_STATUS mvDramIfWinSet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); ++MV_STATUS mvDramIfWinGet(MV_TARGET target, MV_DRAM_DEC_WIN *pAddrDecWin); ++MV_STATUS mvDramIfWinEnable(MV_TARGET target,MV_BOOL enable); ++MV_32 mvDramIfBankSizeGet(MV_U32 bankNum); ++MV_32 mvDramIfBankBaseGet(MV_U32 bankNum); ++MV_32 mvDramIfSizeGet(MV_VOID); ++ ++#if 0 ++MV_STATUS mvDramIfMbusCtrlSet(MV_XBAR_TARGET *pPizzaArbArray); ++MV_STATUS mvDramIfMbusToutSet(MV_U32 timeout, MV_BOOL enable); ++#endif ++ ++#endif /* __INCmvDramIfh */ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfBasicInit.S linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfBasicInit.S +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfBasicInit.S 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfBasicInit.S 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,988 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#define MV_ASMLANGUAGE ++#include "mvSysHwConfig.h" ++#include "mvOsAsm.h" ++#include "mvBoardEnvSpec.h" ++#include "mvCpuIfRegs.h" ++#include "mvDramIfConfig.h" ++#include "mvDramIfRegs.h" ++#include "pex/mvPexRegs.h" ++#include "pci/mvPciRegs.h" ++#include "mvCtrlEnvSpec.h" ++#include "mvCtrlEnvAsm.h" ++#include "cpu/mvCpuArm.h" ++#include "mvCommon.h" ++ ++/* defines */ ++ ++#if !defined(MV_INC_BOARD_DDIM) ++.globl dramBoot1 ++dramBoot1: ++ .word 0 ++ ++/****************************************************************************** ++* ++* ++* ++* ++*******************************************************************************/ ++#if defined(DB_PRPMC) || defined(DB_PEX_PCI) || defined(DB_MNG) ++ ++/* PEX_PCI and PRPMC boards 256 MB*/ ++#define STATIC_SDRAM0_BANK0_SIZE 0x0fff0001 ++#define STATIC_SDRAM_CONFIG 0x03248400 ++#define STATIC_SDRAM_MODE 0x62 ++#define STATIC_DUNIT_CTRL_LOW 0x4041000 ++#define STATIC_SDRAM_ADDR_CTRL 0x00000020 ++#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220 ++#define STATIC_SDRAM_TIME_CTRL_HI 0x0000030F ++#define STATIC_SDRAM_ODT_CTRL_LOW 0x0 ++#define STATIC_SDRAM_ODT_CTRL_HI 0x0 ++#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0 ++#define STATIC_SDRAM_EXT_MODE 0x0 ++ ++#elif defined(DB_FPGA) ++ ++/* FPGA DC boards 256 MB*/ ++#define STATIC_SDRAM0_BANK0_SIZE 0x0fff0001 ++#define STATIC_SDRAM_CONFIG 0x03208400 /* 32bit */ ++#define STATIC_SDRAM_MODE 0x22 ++#define STATIC_DUNIT_CTRL_LOW 0x03041000 ++#define STATIC_SDRAM_ADDR_CTRL 0x00000020 ++#define STATIC_SDRAM_TIME_CTRL_LOW 0x11112220 ++#define STATIC_SDRAM_TIME_CTRL_HI 0x0000000D ++#define STATIC_SDRAM_ODT_CTRL_LOW 0x0 ++#define STATIC_SDRAM_ODT_CTRL_HI 0x0 ++#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0 ++#define STATIC_SDRAM_EXT_MODE 0x1 ++ ++#elif defined(RD_88F6183GP) || defined(DB_CUSTOMER) ++ ++/* Customer 1 DDR2 2 devices 512Mbit by 16 bit */ ++#define STATIC_SDRAM0_BANK0_SIZE 0x07ff0001 ++#define STATIC_SDRAM_CONFIG 0x03158400 ++#define STATIC_SDRAM_MODE 0x452 ++#define STATIC_DUNIT_CTRL_LOW 0x06041000 ++#define STATIC_SDRAM_ADDR_CTRL 0x00000020 ++#define STATIC_SDRAM_TIME_CTRL_LOW 0x11912220 ++#define STATIC_SDRAM_TIME_CTRL_HI 0x00000502 ++#define STATIC_SDRAM_ODT_CTRL_LOW 0x00010000 ++#define STATIC_SDRAM_ODT_CTRL_HI 0x00000002 ++#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x00000601 ++#define STATIC_SDRAM_EXT_MODE 0x00000440 ++ ++ ++#elif defined(RD_88F6183AP) ++ ++/* DDR2 1 devices 512Mbit by 16 bit */ ++#define STATIC_SDRAM0_BANK0_SIZE 0x03ff0001 ++#define STATIC_SDRAM_CONFIG 0x1f154400 ++#define STATIC_SDRAM_MODE 0x432 ++#define STATIC_DUNIT_CTRL_LOW 0x04041000 ++#define STATIC_SDRAM_ADDR_CTRL 0x00000020 ++#define STATIC_SDRAM_TIME_CTRL_LOW 0x11912220 ++#define STATIC_SDRAM_TIME_CTRL_HI 0x00000502 ++#define STATIC_SDRAM_ODT_CTRL_LOW 0x00010000 ++#define STATIC_SDRAM_ODT_CTRL_HI 0x00000002 ++#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x00000601 ++#define STATIC_SDRAM_EXT_MODE 0x00000440 ++ ++/* 6082L MARVELL DIMM */ ++#elif defined(DB_88F6082LBP) ++#define STATIC_SDRAM0_BANK0_SIZE 0x07ff0001 ++#define STATIC_SDRAM_CONFIG 0x7f158400 ++#define STATIC_SDRAM_MODE 0x432 ++#define STATIC_DUNIT_CTRL_LOW 0x04041040 ++#define STATIC_SDRAM_ADDR_CTRL 0x00000020 ++#define STATIC_SDRAM_TIME_CTRL_LOW 0x11612220 ++#define STATIC_SDRAM_TIME_CTRL_HI 0x00000501 ++#define STATIC_SDRAM_ODT_CTRL_LOW 0x00010000 ++#define STATIC_SDRAM_ODT_CTRL_HI 0x00000002 ++#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x00000a01 ++#define STATIC_SDRAM_EXT_MODE 0x00000440 ++ ++#elif defined(RD_88W8660_AP82S) ++ ++/* Shark RD */ ++ ++#if defined(MV_DRAM_32M) ++#define STATIC_SDRAM0_BANK0_SIZE 0x01ff0001 ++#define STATIC_SDRAM_ADDR_CTRL 0x00000010 ++#elif defined(MV_DRAM_16M) ++ ++#define STATIC_SDRAM0_BANK0_SIZE 0x00ff0001 ++#define STATIC_SDRAM_ADDR_CTRL 0x00000000 ++ ++#else ++#error "NO DDR size selected" ++#endif ++ ++#define STATIC_SDRAM_CONFIG 0x03144400 ++#define STATIC_SDRAM_MODE 0x62 ++#define STATIC_DUNIT_CTRL_LOW 0x4041000 ++ ++#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220 ++#define STATIC_SDRAM_TIME_CTRL_HI 0x0000040b ++#define STATIC_SDRAM_ODT_CTRL_LOW 0x0 ++#define STATIC_SDRAM_ODT_CTRL_HI 0x0 ++#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0 ++#define STATIC_SDRAM_EXT_MODE 0x0 ++ ++#elif defined(RD_88W8660) ++ ++/* Shark RD */ ++#define STATIC_SDRAM0_BANK0_SIZE 0x03ff0001 ++#define STATIC_SDRAM_CONFIG 0x03144400 ++#define STATIC_SDRAM_MODE 0x62 ++#define STATIC_DUNIT_CTRL_LOW 0x4041000 ++#define STATIC_SDRAM_ADDR_CTRL 0x00000010 ++#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220 ++#define STATIC_SDRAM_TIME_CTRL_HI 0x0000040b ++#define STATIC_SDRAM_ODT_CTRL_LOW 0x0 ++#define STATIC_SDRAM_ODT_CTRL_HI 0x0 ++#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0 ++#define STATIC_SDRAM_EXT_MODE 0x0 ++ ++#else /* NAS */ ++ ++ ++#if defined(RD_88F5182) ++ ++#if defined(MV_88F5082) ++#define STATIC_SDRAM0_BANK0_SIZE 0x3ff0001 ++#define STATIC_SDRAM_ADDR_CTRL 0x20 ++#else ++#define STATIC_SDRAM0_BANK0_SIZE 0x7ff0001 ++#define STATIC_SDRAM_ADDR_CTRL 0x20 ++#endif ++ ++#elif defined(RD_88F5182_3) ++ ++#if defined(MV_88F5082) ++#define STATIC_SDRAM0_BANK0_SIZE 0x3ff0001 ++#define STATIC_SDRAM_ADDR_CTRL 0x20 ++#else ++#define STATIC_SDRAM0_BANK0_SIZE 0x7ff0001 ++#define STATIC_SDRAM_ADDR_CTRL 0x20 ++#endif ++ ++#else ++ ++#define STATIC_SDRAM0_BANK0_SIZE 0x1ff0001 ++#define STATIC_SDRAM_ADDR_CTRL 0x0 ++ ++#endif ++ ++#if defined(MV_88F5082) ++#define STATIC_SDRAM_CONFIG 0x3144400 ++#else ++#define STATIC_SDRAM_CONFIG 0x3148400 ++#endif ++#define STATIC_SDRAM_MODE 0x62 ++#define STATIC_DUNIT_CTRL_LOW 0x4041000 ++#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220 ++#define STATIC_SDRAM_TIME_CTRL_HI 0x40c ++#define STATIC_SDRAM_ODT_CTRL_LOW 0x0 ++#define STATIC_SDRAM_ODT_CTRL_HI 0x0 ++#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0 ++#define STATIC_SDRAM_EXT_MODE 0x0 ++ ++#endif ++ ++ .globl _mvDramIfStaticInit ++_mvDramIfStaticInit: ++ ++ mov r11, LR /* Save link register */ ++ mov r10, r2 ++ ++ /* If we boot from NAND jump to DRAM sddress */ ++ ++ mov r5, #1 ++ ldr r6, =dramBoot1 ++ str r5, [r6] /* We started executing from DRAM */ ++ ++ ldr r6, dramBoot1 ++ cmp r6, #0 ++ bne 1f ++ ++ ++ /* set all dram windows to 0 */ ++ mov r6, #0 ++ MV_REG_WRITE_ASM(r6, r5, 0x1504) ++ MV_REG_WRITE_ASM(r6, r5, 0x150c) ++ MV_REG_WRITE_ASM(r6, r5, 0x1514) ++ MV_REG_WRITE_ASM(r6, r5, 0x151c) ++ ++ /* set all dram configuration in temp registers */ ++ ldr r6, = STATIC_SDRAM0_BANK0_SIZE ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG0) ++ ldr r6, = STATIC_SDRAM_CONFIG ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG1) ++ ldr r6, = STATIC_SDRAM_MODE ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG2) ++ ldr r6, = STATIC_DUNIT_CTRL_LOW ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG3) ++ ldr r6, = STATIC_SDRAM_ADDR_CTRL ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG4) ++ ldr r6, = STATIC_SDRAM_TIME_CTRL_LOW ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG5) ++ ldr r6, = STATIC_SDRAM_TIME_CTRL_HI ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG6) ++ ldr r6, = STATIC_SDRAM_ODT_CTRL_LOW ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG7) ++ ldr r6, = STATIC_SDRAM_ODT_CTRL_HI ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG8) ++ ldr r6, = STATIC_SDRAM_DUNIT_ODT_CTRL ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG9) ++ ldr r6, = STATIC_SDRAM_EXT_MODE ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG10) ++ ++ mov sp, #0 ++ bl _mvDramIfConfig ++1: ++ mov r2, r10 ++ mov PC, r11 /* r11 is saved link register */ ++ ++#else /* #if !defined(MV_INC_BOARD_DDIM) */ ++ ++.globl dramBoot1 ++dramBoot1: ++ .word 0 ++ ++/******************************************************************************* ++* mvDramIfBasicInit - Basic initialization of DRAM interface ++* ++* DESCRIPTION: ++* The function will initialize the DRAM for basic usage. The function ++* will use the TWSI assembly API to extract DIMM parameters according ++* to which DRAM interface will be initialized. ++* The function referes to the following DRAM parameters: ++* 1) DIMM is registered or not. ++* 2) DIMM width detection. ++* 3) DIMM density. ++* ++* INPUT: ++* r3 - required size for initial DRAM. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++* Note: ++* r4 holds I2C EEPROM address ++* r5 holds SDRAM register base address ++* r7 holds returned values ++* r8 holds SDRAM various configuration registers value. ++* r11 holds return function address. ++*******************************************************************************/ ++/* Setting the offsets of the I2C registers */ ++#define NUM_OF_ROWS_OFFSET 3 ++#define NUM_OF_COLS_OFFSET 4 ++#define NUM_OF_RANKS 5 ++#define SDRAM_WIDTH_OFFSET 13 ++#define NUM_OF_BANKS_OFFSET 17 ++#define SUPPORTED_CL_OFFSET 18 ++#define DIMM_TYPE_INFO_OFFSET 20 /* DDR2 only */ ++#define SDRAM_MODULES_ATTR_OFFSET 21 ++ ++#define DRAM_DEV_DENSITY_128M 0x080 ++#define DRAM_DEV_DENSITY_256M 0x100 ++#define DRAM_DEV_DENSITY_512M 0x200 ++ .globl _mvDramIfBasicInit ++ .extern _i2cInit ++ ++_mvDramIfBasicInit: ++ ++ mov r11, LR /* Save link register */ ++ ++ mov r5, #1 ++ ldr r8, =dramBoot1 ++ str r5, [r8] /* We started executing from DRAM */ ++ ++ /* If we boot from NAND jump to DRAM sddress */ ++ ldr r8, dramBoot1 ++ cmp r8, #0 ++ movne pc, r11 ++ ++ ++ ++ bl _i2cInit /* Initialize TWSI master */ ++ ++ /* Get default SDRAM Config values */ ++ MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG) ++ bic r8, r8, #SDRAM_DCFG_MASK ++ ++ ++ /* Read device ID */ ++ MV_CTRL_MODEL_GET_ASM(r4, r5); ++ ++ /* Return if OrionN */ ++ ldr r5, =MV_5180_DEV_ID ++ cmp r4, r5 ++ beq cat_through_end ++ ++ /* Return if Orion1 */ ++ ldr r5, =MV_5181_DEV_ID ++ cmp r4, r5 ++ beq cat_through_end ++ ++ /* Return if Nas */ ++ ldr r5, =MV_5182_DEV_ID ++ cmp r4, r5 ++ beq cat_through_end ++ ++ /* Return if Shark */ ++ ldr r5, =MV_8660_DEV_ID ++ cmp r4, r5 ++ beq cat_through_end ++ ++ /* goto calcConfigReg if bigger than Orion2*/ ++ ldr r5, =MV_5281_DEV_ID ++ cmp r4, r5 ++ bne cat_through ++ ++cat_through: ++ /* set cat through - for better performance - in orion2 b0 and higher*/ ++ orr r8, r8, #SDRAM_CATTHR_EN ++ ++cat_through_end: ++ ++ ++ /* Get registered/non registered info from DIMM */ ++ bl _is_Registered ++ beq nonRegistered ++ ++setRegistered: ++ orr r8, r8, #SDRAM_REGISTERED /* Set registered bit(17) */ ++ ++nonRegistered: ++ /* Get SDRAM width */ ++ bl _get_width ++ ++ orr r6, r8, #SDRAM_DCFG_X16_DEV /* x16 devices */ ++ cmp r7, #16 ++ beq setConfigReg ++ ++ orr r6, r8, #SDRAM_DCFG_X8_DEV /* x8 devices */ ++ cmp r7, #8 ++ beq setConfigReg ++ ++ /* This is an error. return */ ++ b exit_ddrAutoConfig ++ ++setConfigReg: ++ mov r8, r6 ++ ldr r6, =SDRAM_CONFIG_DV ++ orr r8, r8, r6 /* Add default settings */ ++ mov r6, r8 /* Do not swap r8 content */ ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_CONFIG_REG) ++ ++ /* Set maximum CL supported by DIMM */ ++ bl _get_CAL ++ ++ /* r7 is DIMM supported CAS (e.g: 3 --> 0x1C) */ ++ clz r6, r7 ++ rsb r6, r6, #31 /* r6 = the bit number of MAX CAS supported */ ++ ++ /* Check the DDR version */ ++ tst r8, #SDRAM_DTYPE_DDR2 ++ bne casDdr2 ++ ++casDdr1: ++ ldr r7, =3 /* stBurstDel field value */ ++ ldr r8, =0x52 /* Assuming MAX CL = 1.5 */ ++ cmp r6, #1 /* If CL = 1.5 break */ ++ beq setModeReg ++ ++ ldr r7, =3 /* stBurstDel field value */ ++ ldr r8, =0x22 /* Assuming MAX CL = 2 */ ++ cmp r6, #2 /* If CL = 2 break */ ++ beq setModeReg ++ ++ ldr r7, =4 /* stBurstDel field value */ ++ ldr r8, =0x62 /* Assuming MAX CL = 2.5 */ ++ cmp r6, #3 /* If CL = 2.5 break */ ++ beq setModeReg ++ ++ ldr r7, =4 /* stBurstDel field value */ ++ ldr r8, =0x32 /* Assuming MAX CL = 3 */ ++ cmp r6, #4 /* If CL = 3 break */ ++ beq setModeReg ++ ++ ldr r7, =5 /* stBurstDel field value */ ++ ldr r8, =0x42 /* Assuming MAX CL = 4 */ ++ cmp r6, #6 /* If CL = 4 break */ ++ b setModeReg ++ ++ b exit_ddrAutoConfig /* This is an error !! */ ++ ++casDdr2: ++ ldr r7, =4 /* stBurstDel field value */ ++ ldr r8, =0x32 /* Assuming MAX CL = 3 */ ++ cmp r6, #3 /* If CL = 3 break */ ++ beq casDdr2Cont ++ ++ ldr r7, =5 /* stBurstDel field value */ ++ ldr r8, =0x42 /* Assuming MAX CL = 4 */ ++ cmp r6, #4 /* If CL = 4 break */ ++ beq casDdr2Cont ++ ++ /* CL 5 currently unsupported. We use CL 4 instead */ ++ ldr r7, =5 /* stBurstDel field value */ ++ ldr r8, =0x42 /* Assuming MAX CL = 5 */ ++ cmp r6, #5 /* If CL = 5 break */ ++ beq casDdr2Cont ++ ++ b exit_ddrAutoConfig /* This is an error !! */ ++casDdr2Cont: ++ /* Write recovery for auto-precharge relevant only in DDR2 */ ++ orr r8, r8, #0x400 /* Default value */ ++ ++setModeReg: ++ /* The CPU must not attempt to change the SDRAM Mode register setting */ ++ /* prior to DRAM controller completion of the DRAM initialization */ ++ /* sequence. To guarantee this restriction, it is recommended that */ ++ /* the CPU sets the SDRAM Operation register to NOP command, performs */ ++ /* read polling until the register is back in Normal operation value, */ ++ /* and then sets SDRAM Mode register to it's new value. */ ++ ++ /* write 'nop' to SDRAM operation */ ++ mov r6, #0x5 /* 'NOP' command */ ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG) ++ ++ /* poll SDRAM operation. Make sure its back to normal operation */ ++_sdramOpPoll1: ++ ldr r6, [r5] ++ cmp r6, #0 /* '0' = Normal SDRAM Mode */ ++ bne _sdramOpPoll1 ++ ++ /* Now its safe to write new value to SDRAM Mode register */ ++ MV_REG_WRITE_ASM (r8, r5, SDRAM_MODE_REG) ++ ++ /* Make the Dunit write the DRAM its new mode */ ++ mov r6, #0x3 /* Mode Register Set command */ ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG) ++ ++ /* poll SDRAM operation. Make sure its back to normal operation */ ++_sdramOpPoll2: ++ ldr r6, [r5] ++ cmp r6, #0 /* '0' = Normal SDRAM Mode */ ++ bne _sdramOpPoll2 ++ ++ /* Set Dunit control register according to max CL detected */ ++ /* If we use registered DIMM, add 1 to stBurstDel */ ++ MV_REG_READ_ASM (r6, r5, SDRAM_CONFIG_REG) ++ tst r6, #SDRAM_REGISTERED ++ beq setDunitReg ++ add r7, r7, #1 ++ ++setDunitReg: ++ ldr r6, =SDRAM_DUNIT_CTRL_LOW_DV ++ orr r6, r6, r7, LSL #SDRAM_ST_BURST_DEL_OFFS ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) ++ ++ ++ /* DIMM density configuration*/ ++ /* Density = (1 << (rowNum + colNum)) * dramWidth * dramBankNum */ ++Density: ++ bl _getDensity ++ mov r8, r7 ++ mov r8, r8, LSR #20 /* Move density 20 bits to the right */ ++ /* For example 0x10000000 --> 0x1000 */ ++ ++ mov r6, #0x00 ++ cmp r8, #DRAM_DEV_DENSITY_128M ++ beq densCont ++ ++ mov r6, #0x10 ++ cmp r8, #DRAM_DEV_DENSITY_256M ++ beq densCont ++ ++ mov r6, #0x20 ++ cmp r8, #DRAM_DEV_DENSITY_512M ++ beq densCont ++ ++ /* This is an error. return */ ++ b exit_ddrAutoConfig ++ ++densCont: ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_REG) ++ ++ /* Config DDR2 registers (Extended mode, ODTs and pad calibration) */ ++ MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG) ++ tst r8, #SDRAM_DTYPE_DDR2 ++ beq _extModeODTEnd ++ ++ ++ /* Set DDR Extended Mode register for working with CS[0] */ ++ /* write 'nop' to SDRAM operation */ ++ mov r6, #0x5 /* 'NOP' command */ ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG) ++ ++ /* poll SDRAM operation. Make sure its back to normal operation */ ++_sdramOpPoll3: ++ ldr r6, [r5] ++ cmp r6, #0 /* '0' = Normal SDRAM Mode */ ++ bne _sdramOpPoll3 ++ ++ /* Now its safe to write new value to SDRAM Extended Mode register */ ++ ldr r6, =DDR_SDRAM_EXT_MODE_CS0_DV ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_EXTENDED_MODE_REG) ++ ++ /* Make the Dunit write the DRAM its new extended mode */ ++ mov r6, #0x4 /* Extended Mode Register Set command */ ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG) ++ ++ /* poll SDRAM operation. Make sure its back to normal operation */ ++_sdramOpPoll4: ++ ldr r6, [r5] ++ cmp r6, #0 /* '0' = Normal SDRAM Mode */ ++ bne _sdramOpPoll4 ++ ++ /* ODT configuration is done for single bank CS[0] only */ ++ /* Config DDR2 On Die Termination (ODT) registers */ ++ ldr r6, =DDR2_ODT_CTRL_LOW_CS0_DV ++ MV_REG_WRITE_ASM (r6, r5, DDR2_SDRAM_ODT_CTRL_LOW_REG) ++ ++ ldr r6, =DDR2_ODT_CTRL_HIGH_CS0_DV ++ MV_REG_WRITE_ASM (r6, r5, DDR2_SDRAM_ODT_CTRL_HIGH_REG) ++ ++ ldr r6, =DDR2_DUNIT_ODT_CTRL_CS0_DV ++ MV_REG_WRITE_ASM (r6, r5, DDR2_DUNIT_ODT_CONTROL_REG) ++ ++ ++ /* we will check what device we are running and perform ++ Initialization according to device value */ ++ ++_extModeODTEnd: ++ ++ /* Implement Guideline (GL# MEM-2) P_CAL Automatic Calibration */ ++ /* Does Not Work for Address/Control and Data Pads. */ ++ /* Relevant for: 88F5181-A1/B0 and 88F5281-A0 */ ++ ++ /* Read device ID */ ++ MV_CTRL_MODEL_GET_ASM(r6, r5); ++ /* Read device revision */ ++ MV_CTRL_REV_GET_ASM(r8, r5); ++ ++ /* Continue if OrionN */ ++ ldr r5, =MV_5180_DEV_ID ++ cmp r6, r5 ++ bne 1f ++ b glMem2End ++1: ++ ++ /* Continue if Orion1 and device revision B1 */ ++ ldr r5, =MV_5181_DEV_ID ++ cmp r6, r5 ++ bne 1f ++ ++ cmp r8, #MV_5181_B1_REV ++ bge glMem2End ++ b glMem2Start ++1: ++ ++ /* Orion NAS */ ++ ldr r5, =MV_5182_DEV_ID ++ cmp r6, r5 ++ beq glMem2Start ++ ++ /* Orion Shark */ ++ ldr r5, =MV_8660_DEV_ID ++ cmp r6, r5 ++ beq glMem2Start ++ ++ b glMem2End ++ ++glMem2Start: ++ ++ /* DDR SDRAM Address/Control Pads Calibration */ ++ MV_REG_READ_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) ++ ++ /* Set Bit [31] to make the register writable */ ++ orr r8, r6, #SDRAM_WR_EN ++ ++ MV_REG_WRITE_ASM (r8, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) ++ ++ bic r6, r6, #SDRAM_WR_EN /* Make register read-only */ ++ bic r6, r6, #SDRAM_TUNE_EN /* Disable auto calibration */ ++ bic r6, r6, #SDRAM_DRVN_MASK /* Clear r5[5:0] */ ++ bic r6, r6, #SDRAM_DRVP_MASK /* Clear r5[11:6] */ ++ ++ /* Get the final N locked value of driving strength [22:17] */ ++ mov r5, r6 ++ mov r5, r5, LSL #9 ++ mov r5, r5, LSR #26 /* r5[5:0] = r6[22:17] */ ++ orr r5, r5, r5, LSL #6 /* r5[11:6] = r5[5:0] */ ++ ++ /* Write to both bits [5:0] and bits [11:6] */ ++ orr r6, r6, r5 ++ ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) ++ ++ ++ /* DDR SDRAM Data Pads Calibration */ ++ MV_REG_READ_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG) ++ ++ /* Set Bit [31] to make the register writable */ ++ orr r8, r6, #SDRAM_WR_EN ++ ++ MV_REG_WRITE_ASM (r8, r5, SDRAM_DATA_PADS_CAL_REG) ++ ++ bic r6, r6, #SDRAM_WR_EN /* Make register read-only */ ++ bic r6, r6, #SDRAM_TUNE_EN /* Disable auto calibration */ ++ bic r6, r6, #SDRAM_DRVN_MASK /* Clear r5[5:0] */ ++ bic r6, r6, #SDRAM_DRVP_MASK /* Clear r5[11:6] */ ++ ++ /* Get the final N locked value of driving strength [22:17] */ ++ mov r5, r6 ++ mov r5, r5, LSL #9 ++ mov r5, r5, LSR #26 ++ orr r5, r5, r5, LSL #6 /* r5[5:0] = r6[22:17] */ ++ ++ /* Write to both bits [5:0] and bits [11:6] */ ++ orr r6, r6, r5 ++ ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG) ++ ++glMem2End: ++ /* Implement Guideline (GL# MEM-3) Drive Strength Value */ ++ /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */ ++ ++ /* Get SDRAM Config value */ ++ MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG) ++ ++ /* Get DIMM type */ ++ tst r8, #SDRAM_DTYPE_DDR2 ++ beq ddr1StrengthVal ++ ++ddr2StrengthVal: ++ ldr r4, =DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV ++ ldr r8, =DDR2_DATA_PAD_STRENGTH_TYPICAL_DV ++ b setDrvStrength ++ddr1StrengthVal: ++ ldr r4, =DDR1_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV ++ ldr r8, =DDR1_DATA_PAD_STRENGTH_TYPICAL_DV ++ ++setDrvStrength: ++ /* DDR SDRAM Address/Control Pads Calibration */ ++ MV_REG_READ_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) ++ ++ orr r6, r6, #SDRAM_WR_EN /* Make register writeable */ ++ ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) ++ HTOLL(r6,r5) ++ ++ bic r6, r6, #SDRAM_WR_EN /* Make register read-only */ ++ bic r6, r6, #SDRAM_PRE_DRIVER_STRENGTH_MASK ++ orr r6, r4, r6 /* Set default value for DDR */ ++ ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG) ++ ++ ++ /* DDR SDRAM Data Pads Calibration */ ++ MV_REG_READ_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG) ++ ++ orr r6, r6, #SDRAM_WR_EN /* Make register writeable */ ++ ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG) ++ HTOLL(r6,r5) ++ ++ bic r6, r6, #SDRAM_WR_EN /* Make register read-only */ ++ bic r6, r6, #SDRAM_PRE_DRIVER_STRENGTH_MASK ++ orr r6, r8, r6 /* Set default value for DDR */ ++ ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG) ++ ++ ++ /* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */ ++ /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */ ++ /* Get the "sample on reset" register for the DDR frequancy */ ++ ++#if defined(MV_RUN_FROM_FLASH) ++ /* Calc the absolute address of the _cpuARMDDRCLK[] in the boot flash */ ++ ldr r7, = _cpuARMDDRCLK ++ ldr r4, =_start ++ ldr r4, [r4] ++ sub r7, r7, r4 ++ ldr r4, = Lrom_start_of_data ++ ldr r4, [r4] ++ add r7, r4, r7 ++#else ++ /* Calc the absolute address of the _cpuARMDDRCLK[] in the boot flash */ ++ ldr r7, = _cpuARMDDRCLK ++ ldr r4, =_start ++ sub r7, r7, r4 ++ add r7, r7, #CFG_MONITOR_BASE ++#endif ++ /* Get the "sample on reset" register for the DDR frequancy */ ++ MV_REG_READ_ASM (r4, r5, MPP_SAMPLE_AT_RESET) ++ ldr r5, =MSAR_ARMDDRCLCK_MASK ++ and r5, r4, r5 ++#if 0 /* YOTAM TO BE FIX */ ++ mov r5, r5, LSR #MSAR_ARMDDRCLCK_OFFS ++#endif ++ ++ /* Read device ID */ ++ MV_CTRL_MODEL_GET_ASM(r6, r8); ++ ++ /* Continue if TC90 */ ++ ldr r8, =MV_1281_DEV_ID ++ cmp r6, r6 ++ beq armClkMsb ++ ++ /* Continue if Orion2 */ ++ ldr r8, =MV_5281_DEV_ID ++ cmp r6, r8 ++#if 0 /* YOTAM TO BE FIX */ ++ bne 1f ++#endif ++ ++armClkMsb: ++#if 0 /* YOTAM TO BE FIX */ ++ tst r4, #MSAR_ARMDDRCLCK_H_MASK ++ beq 1f ++ orr r5, r5, #BIT4 ++1: ++ ldr r4, =MV_CPU_ARM_CLK_ELM_SIZE ++ mul r5, r4, r5 ++ add r7, r7, r5 ++ add r7, r7, #MV_CPU_ARM_CLK_DDR_OFF ++ ldr r5, [r7] ++#endif ++ ++ /* Get SDRAM Config value */ ++ MV_REG_READ_ASM (r8, r4, SDRAM_CONFIG_REG) ++ ++ /* Get DIMM type */ ++ tst r8, #SDRAM_DTYPE_DDR2 ++ beq ddr1FtdllVal ++ ++ddr2FtdllVal: ++ ldr r4, =FTDLL_DDR2_250MHZ ++ ldr r7, =_250MHz ++ cmp r5, r7 ++ beq setFtdllReg ++ ldr r4, =FTDLL_DDR2_200MHZ ++ ldr r7, =_200MHz ++ cmp r5, r7 ++ beq setFtdllReg ++ ldr r4, =FTDLL_DDR2_166MHZ ++ ldr r7, =_166MHz ++ cmp r5, r7 ++ beq setFtdllReg ++ ldr r4, =FTDLL_DDR2_133MHZ ++ b setFtdllReg ++ ++ddr1FtdllVal: ++ ldr r4, =FTDLL_DDR1_200MHZ ++ ldr r7, =_200MHz ++ cmp r5, r7 ++ beq setFtdllReg ++ ldr r4, =FTDLL_DDR1_166MHZ ++ ldr r7, =_166MHz ++ cmp r5, r7 ++ beq setFtdllReg ++ ldr r4, =FTDLL_DDR1_133MHZ ++ ldr r7, =_133MHz ++ cmp r5, r7 ++ beq setFtdllReg ++ ldr r4, =0 ++ ++setFtdllReg: ++ ++#if !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L) ++ MV_REG_READ_ASM (r8, r5, SDRAM_FTDLL_CONFIG_REG) ++ orr r8, r8, r4 ++ MV_REG_WRITE_ASM (r8, r5, SDRAM_FTDLL_CONFIG_REG) ++ bic r8, r8, #1 ++ MV_REG_WRITE_ASM (r8, r5, SDRAM_FTDLL_CONFIG_REG) ++#endif /* !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L)*/ ++ ++ ++setTimingReg: ++ /* Set default Timing parameters */ ++ MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG) ++ tst r8, #SDRAM_DTYPE_DDR2 ++ bne ddr2TimeParam ++ ++ddr1TimeParam: ++ ldr r6, =DDR1_TIMING_LOW_DV ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_LOW_REG) ++ ldr r6, =DDR1_TIMING_HIGH_DV ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_HIGH_REG) ++ b timeParamDone ++ ++ddr2TimeParam: ++ ldr r6, =DDR2_TIMING_LOW_DV ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_LOW_REG) ++ ldr r6, =DDR2_TIMING_HIGH_DV ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_HIGH_REG) ++ ++timeParamDone: ++ /* Open CS[0] window to requested size and enable it. Disable other */ ++ /* windows */ ++ ldr r6, =SCBAR_BASE_MASK ++ sub r3, r3, #1 ++ and r3, r3, r6 ++ orr r3, r3, #1 /* Enable bank */ ++ MV_REG_WRITE_ASM (r3, r5, SDRAM_SIZE_REG(0)) ++ ldr r6, =0 ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(1)) ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(2)) ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(3)) ++ ++exit_ddrAutoConfig: ++ mov PC, r11 /* r11 is saved link register */ ++ ++ ++/***************************************************************************************/ ++/* r4 holds I2C EEPROM address ++ * r7 holds I2C EEPROM offset parameter for i2cRead and its --> returned value ++ * r8 holds SDRAM various configuration registers value. ++ * r13 holds Link register ++ */ ++/**************************/ ++_getDensity: ++ mov r13, LR /* Save link register */ ++ ++ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ ++ mov r7, #NUM_OF_ROWS_OFFSET /* offset 3 */ ++ bl _i2cRead ++ mov r8, r7 /* r8 save number of rows */ ++ ++ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ ++ mov r7, #NUM_OF_COLS_OFFSET /* offset 4 */ ++ bl _i2cRead ++ add r8, r8, r7 /* r8 = number of rows + number of col */ ++ ++ mov r7, #0x1 ++ mov r8, r7, LSL r8 /* r8 = (1 << r8) */ ++ ++ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ ++ mov r7, #SDRAM_WIDTH_OFFSET /* offset 13 */ ++ bl _i2cRead ++ mul r8, r7, r8 ++ ++ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ ++ mov r7, #NUM_OF_BANKS_OFFSET /* offset 17 */ ++ bl _i2cRead ++ mul r7, r8, r7 ++ ++ mov PC, r13 ++ ++/**************************/ ++_get_width: ++ mov r13, LR /* Save link register */ ++ ++ /* Get SDRAM width (SPD offset 13) */ ++ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ ++ mov r7, #SDRAM_WIDTH_OFFSET ++ bl _i2cRead /* result in r7 */ ++ ++ mov PC, r13 ++ ++/**************************/ ++_get_CAL: ++ mov r13, LR /* Save link register */ ++ ++ /* Set maximum CL supported by DIMM */ ++ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ ++ mov r7, #SUPPORTED_CL_OFFSET /* offset 18 */ ++ bl _i2cRead ++ ++ mov PC, r13 ++ ++/**************************/ ++/* R8 - sdram configuration register. ++ * Return value in flag if no-registered then Z-flag is set ++ */ ++_is_Registered: ++ mov r13, LR /* Save link register */ ++ ++ /* Get registered/non registered info from DIMM */ ++ tst r8, #SDRAM_DTYPE_DDR2 ++ bne regDdr2 ++ ++regDdr1: ++ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ ++ mov r7, #SDRAM_MODULES_ATTR_OFFSET ++ bl _i2cRead /* result in r7 */ ++ tst r7, #0x2 ++ b exit ++regDdr2: ++ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ ++ mov r7, #DIMM_TYPE_INFO_OFFSET ++ bl _i2cRead /* result in r7 */ ++ tst r7, #0x11 /* DIMM type = regular RDIMM (0x01) */ ++ /* or Mini-RDIMM (0x10) */ ++exit: ++ mov PC, r13 ++ ++ ++#endif +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.S linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.S +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.S 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.S 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,668 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++/******************************************************************************* ++* mvDramIfBasicAsm.s ++* ++* DESCRIPTION: ++* Memory full detection and best timing configuration is done in ++* C code. C runtime environment requires a stack. This module API ++* initialize DRAM interface chip select 0 for basic functionality for ++* the use of stack. ++* The module API assumes DRAM information is stored in I2C EEPROM reside ++* in a given I2C address MV_BOARD_DIMM0_I2C_ADDR. The I2C EEPROM ++* internal data structure is assumed to be orgenzied in common DRAM ++* vendor SPD structure. ++* NOTE: DFCDL values are assumed to be already initialized prior to ++* this module API activity. ++* ++* ++* DEPENDENCIES: ++* None. ++* ++*******************************************************************************/ ++ ++/* includes */ ++#define MV_ASMLANGUAGE ++#include "mvOsAsm.h" ++#include "mvSysHwConfig.h" ++#include "mvDramIfRegs.h" ++#include "mvDramIfConfig.h" ++#include "mvCpuIfRegs.h" ++#include "pex/mvPexRegs.h" ++#include "pci/mvPciRegs.h" ++#include "mvCtrlEnvSpec.h" ++#include "mvCtrlEnvAsm.h" ++#include "cpu/mvCpuArm.h" ++#include "mvCommon.h" ++ ++/* defines */ ++ ++/* locals */ ++.data ++.globl _mvDramIfConfig ++ ++.text ++ ++/******************************************************************************* ++* _mvDramIfConfig - Basic DRAM interface initialization. ++* ++* DESCRIPTION: ++* The function will initialize the following DRAM parameters using the ++* values prepared by mvDramIfDetect routine. Values are located ++* in predefined registers. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++ ++_mvDramIfConfig: ++ ++ /* Save register on stack */ ++ cmp sp, #0 ++ beq no_stack_s ++save_on_stack: ++ stmdb sp!, {r1, r2, r3, r4, r7, r11} ++no_stack_s: ++ ++ /* 1) Write to SDRAM coniguration register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG1) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_CONFIG_REG) ++ str r4, [r1] ++ ++ /* 2) Write Dunit control low register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG3) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_DUNIT_CTRL_REG) ++ str r4, [r1] ++ ++ /* 3) Write SDRAM address control register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG4) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_ADDR_CTRL_REG) ++ str r4, [r1] ++ ++ /* 4) Write SDRAM bank 0 size register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG0) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_SIZE_REG(0)) ++ str r4, [r1] ++ ++ /* 5) Write SDRAM open pages control register */ ++ ldr r1, =(INTER_REGS_BASE + SDRAM_OPEN_PAGE_CTRL_REG) ++ ldr r4, =SDRAM_OPEN_PAGES_CTRL_REG_DV ++ str r4, [r1] ++ ++ /* 6) Write SDRAM timing Low register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG5) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_LOW_REG) ++ str r4, [r1] ++ ++ /* 7) Write SDRAM timing High register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG6) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_HIGH_REG) ++ str r4, [r1] ++ ++ /* 8) Write SDRAM mode register */ ++ /* The CPU must not attempt to change the SDRAM Mode register setting */ ++ /* prior to DRAM controller completion of the DRAM initialization */ ++ /* sequence. To guarantee this restriction, it is recommended that */ ++ /* the CPU sets the SDRAM Operation register to NOP command, performs */ ++ /* read polling until the register is back in Normal operation value, */ ++ /* and then sets SDRAM Mode register to it’s new value. */ ++ ++ /* 8.1 write 'nop' to SDRAM operation */ ++ mov r4, #0x5 /* 'NOP' command */ ++ MV_REG_WRITE_ASM(r4, r1, SDRAM_OPERATION_REG) ++ ++ /* 8.2 poll SDRAM operation. Make sure its back to normal operation */ ++_sdramOpPoll1: ++ ldr r4, [r1] ++ cmp r4, #0 /* '0' = Normal SDRAM Mode */ ++ bne _sdramOpPoll1 ++ ++ /* 8.3 Now its safe to write new value to SDRAM Mode register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG2) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_MODE_REG) ++ str r4, [r1] ++ ++ /* 8.4 Make the Dunit write the DRAM its new mode */ ++ mov r4, #0x3 /* Mode Register Set command */ ++ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) ++ ++ /* 8.5 poll SDRAM operation. Make sure its back to normal operation */ ++_sdramOpPoll2: ++ ldr r4, [r1] ++ cmp r4, #0 /* '0' = Normal SDRAM Mode */ ++ bne _sdramOpPoll2 ++ ++#ifndef DB_FPGA ++ /* Config DDR2 registers (Extended mode, ODTs and pad calibration) */ ++ MV_REG_READ_ASM (r4, r1, SDRAM_CONFIG_REG) ++ tst r4, #SDRAM_DTYPE_DDR2 ++ beq _extModeODTEnd ++#endif /* DB_FPGA */ ++ ++ /* 9) Write SDRAM Extended mode register This operation should be */ ++ /* done for each memory bank */ ++ /* write 'nop' to SDRAM operation */ ++ mov r4, #0x5 /* 'NOP' command */ ++ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) ++ ++ /* poll SDRAM operation. Make sure its back to normal operation */ ++_sdramOpPoll3: ++ ldr r4, [r1] ++ cmp r4, #0 /* '0' = Normal SDRAM Mode */ ++ bne _sdramOpPoll3 ++ ++ /* Now its safe to write new value to SDRAM Extended Mode register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG10) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_EXTENDED_MODE_REG) ++ str r4, [r1] ++ ++ /* Go over each of the Banks */ ++ ldr r3, =0 /* r3 = DRAM bank Num */ ++ ++extModeLoop: ++ /* Set the SDRAM Operation Control to each of the DRAM banks */ ++ mov r2, r3 /* Do not swap the bank counter value */ ++ MV_REG_WRITE_ASM (r2, r1, SDRAM_OPERATION_CTRL_REG) ++ ++ /* Make the Dunit write the DRAM its new mode */ ++ mov r4, #0x4 /* Extended Mode Register Set command */ ++ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) ++ ++ /* poll SDRAM operation. Make sure its back to normal operation */ ++_sdramOpPoll4: ++ ldr r4, [r1] ++ cmp r4, #0 /* '0' = Normal SDRAM Mode */ ++ bne _sdramOpPoll4 ++#ifndef DB_FPGA ++ add r3, r3, #1 ++ cmp r3, #4 /* 4 = Number of banks */ ++ bne extModeLoop ++ ++extModeEnd: ++ /* Config DDR2 On Die Termination (ODT) registers */ ++ /* Write SDRAM DDR2 ODT control low register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG7) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_LOW_REG) ++ str r4, [r1] ++ ++ /* Write SDRAM DDR2 ODT control high register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG8) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_HIGH_REG) ++ str r4, [r1] ++ ++ /* Write SDRAM DDR2 Dunit ODT control register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG9) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + DDR2_DUNIT_ODT_CONTROL_REG) ++ str r4, [r1] ++ ++#endif /* DB_FPGA */ ++_extModeODTEnd: ++#ifndef DB_FPGA ++ /* Implement Guideline (GL# MEM-2) P_CAL Automatic Calibration */ ++ /* Does Not Work for Address/Control and Data Pads. */ ++ /* Relevant for: 88F5181-A1/B0 and 88F5281-A0 */ ++ ++ /* Read device ID */ ++ MV_CTRL_MODEL_GET_ASM(r3, r1); ++ /* Read device revision */ ++ MV_CTRL_REV_GET_ASM(r2, r1); ++ ++ /* Continue if OrionN */ ++ ldr r1, =MV_5180_DEV_ID ++ cmp r3, r1 ++ bne 1f ++ b glMem2End ++1: ++ /* Continue if Orion1 and device revision B1 */ ++ ldr r1, =MV_5181_DEV_ID ++ cmp r3, r1 ++ bne 1f ++ ++ cmp r2, #MV_5181_B1_REV ++ bge glMem2End ++ b glMem2Start ++1: ++ ++ /* Orion NAS */ ++ ldr r1, =MV_5182_DEV_ID ++ cmp r3, r1 ++ beq glMem2Start ++ ++ /* Orion NAS */ ++ ldr r1, =MV_5082_DEV_ID ++ cmp r3, r1 ++ beq glMem2Start ++ ++ /* Orion Shark */ ++ ldr r1, =MV_8660_DEV_ID ++ cmp r3, r1 ++ beq glMem2Start ++ ++ b glMem2End ++ ++glMem2Start: ++ ++ /* DDR SDRAM Address/Control Pads Calibration */ ++ MV_REG_READ_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) ++ ++ /* Set Bit [31] to make the register writable */ ++ orr r2, r3, #SDRAM_WR_EN ++ ++ MV_REG_WRITE_ASM (r2, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) ++ ++ bic r3, r3, #SDRAM_WR_EN /* Make register read-only */ ++ bic r3, r3, #SDRAM_TUNE_EN /* Disable auto calibration */ ++ bic r3, r3, #SDRAM_DRVN_MASK /* Clear r1[5:0] */ ++ bic r3, r3, #SDRAM_DRVP_MASK /* Clear r1[11:6] */ ++ ++ /* Get the final N locked value of driving strength [22:17] */ ++ mov r1, r3 ++ mov r1, r1, LSL #9 ++ mov r1, r1, LSR #26 /* r1[5:0] = r3[22:17] */ ++ orr r1, r1, r1, LSL #6 /* r1[11:6] = r1[5:0] */ ++ ++ /* Write to both bits [5:0] and bits [11:6] */ ++ orr r3, r3, r1 ++ ++ MV_REG_WRITE_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) ++ ++ ++ /* DDR SDRAM Data Pads Calibration */ ++ MV_REG_READ_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG) ++ ++ /* Set Bit [31] to make the register writable */ ++ orr r2, r3, #SDRAM_WR_EN ++ ++ MV_REG_WRITE_ASM (r2, r1, SDRAM_DATA_PADS_CAL_REG) ++ ++ bic r3, r3, #SDRAM_WR_EN /* Make register read-only */ ++ bic r3, r3, #SDRAM_TUNE_EN /* Disable auto calibration */ ++ bic r3, r3, #SDRAM_DRVN_MASK /* Clear r1[5:0] */ ++ bic r3, r3, #SDRAM_DRVP_MASK /* Clear r1[11:6] */ ++ ++ /* Get the final N locked value of driving strength [22:17] */ ++ mov r1, r3 ++ mov r1, r1, LSL #9 ++ mov r1, r1, LSR #26 ++ orr r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17] */ ++ ++ /* Write to both bits [5:0] and bits [11:6] */ ++ orr r3, r3, r1 ++ ++ MV_REG_WRITE_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG) ++ ++glMem2End: ++ ++ ++ /* Implement Guideline (GL# MEM-3) Drive Strength Value */ ++ /* Relevant for: 88F5181-A1/B0/B1, 88F5281-A0/B0/C/D, 88F5182, */ ++ /* 88F5082, 88F5181L, 88F6082/L, 88F6183, 88F6183L */ ++ ++ /* Get SDRAM Config value */ ++ MV_REG_READ_ASM (r2, r1, SDRAM_CONFIG_REG) ++ ++ /* Get DIMM type */ ++ tst r2, #SDRAM_DTYPE_DDR2 ++ beq ddr1StrengthVal ++ ++ddr2StrengthVal: ++ ldr r4, =DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV ++ ldr r2, =DDR2_DATA_PAD_STRENGTH_TYPICAL_DV ++ b setDrvStrength ++ddr1StrengthVal: ++ ldr r4, =DDR1_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV ++ ldr r2, =DDR1_DATA_PAD_STRENGTH_TYPICAL_DV ++ ++setDrvStrength: ++ /* DDR SDRAM Address/Control Pads Calibration */ ++ MV_REG_READ_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) ++ ++ orr r3, r3, #SDRAM_WR_EN /* Make register writeable */ ++ ++ MV_REG_WRITE_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) ++ HTOLL(r3,r1) ++ ++ bic r3, r3, #SDRAM_WR_EN /* Make register read-only */ ++ bic r3, r3, #SDRAM_PRE_DRIVER_STRENGTH_MASK ++ orr r3, r4, r3 /* Set default value for DDR */ ++ ++ MV_REG_WRITE_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG) ++ ++ ++ /* DDR SDRAM Data Pads Calibration */ ++ MV_REG_READ_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG) ++ ++ orr r3, r3, #SDRAM_WR_EN /* Make register writeable */ ++ ++ MV_REG_WRITE_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG) ++ HTOLL(r3,r1) ++ ++ bic r3, r3, #SDRAM_WR_EN /* Make register read-only */ ++ bic r3, r3, #SDRAM_PRE_DRIVER_STRENGTH_MASK ++ orr r3, r2, r3 /* Set default value for DDR */ ++ ++ MV_REG_WRITE_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG) ++ ++#if !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L) ++ /* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */ ++ /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0/C/D, 88F5182 */ ++ /* 88F5082, 88F5181L, 88F6082/L */ ++ ++ /* Calc the absolute address of the _cpuARMDDRCLK[] in the boot flash */ ++ ldr r7, = _cpuARMDDRCLK ++ ldr r4, =_start ++ sub r7, r7, r4 ++ add r7, r7, #CFG_MONITOR_BASE ++ ++ /* Get the "sample on reset" register for the DDR frequancy */ ++ MV_REG_READ_ASM (r4, r1, MPP_SAMPLE_AT_RESET) ++ ldr r1, =MSAR_ARMDDRCLCK_MASK ++ and r1, r4, r1 ++#if 0 /* YOTAM TO BE FIX */ ++ mov r1, r1, LSR #MSAR_ARMDDRCLCK_OFFS ++#endif ++ ++ /* Read device ID */ ++ MV_CTRL_MODEL_GET_ASM(r3, r2); ++ ++ /* Continue if TC90 */ ++ ldr r2, =MV_1281_DEV_ID ++ cmp r3, r2 ++ beq armClkMsb ++ ++ /* Continue if Orion2 */ ++ ldr r2, =MV_5281_DEV_ID ++ cmp r3, r2 ++#if 0 /* YOTAM TO BE FIX */ ++ bne 1f ++#endif ++ ++armClkMsb: ++#if 0 /* YOTAM TO BE FIX */ ++ tst r4, #MSAR_ARMDDRCLCK_H_MASK ++ beq 1f ++ orr r1, r1, #BIT4 ++1: ++ ldr r4, =MV_CPU_ARM_CLK_ELM_SIZE ++ mul r1, r4, r1 ++ add r7, r7, r1 ++ add r7, r7, #MV_CPU_ARM_CLK_DDR_OFF ++ ldr r1, [r7] ++#endif ++ ++ /* Get SDRAM Config value */ ++ MV_REG_READ_ASM (r2, r4, SDRAM_CONFIG_REG) ++ ++ /* Get DIMM type */ ++ tst r2, #SDRAM_DTYPE_DDR2 ++ beq ddr1FtdllVal ++ ++ddr2FtdllVal: ++ ldr r2, =MV_5281_DEV_ID ++ cmp r3, r2 ++ bne 2f ++ MV_CTRL_REV_GET_ASM(r3, r2) ++ cmp r3, #MV_5281_D0_REV ++ beq orin2_d0_ddr2_ftdll_val ++ cmp r3, #MV_5281_D1_REV ++ beq orin2_d1_ddr2_ftdll_val ++ cmp r3, #MV_5281_D2_REV ++ beq orin2_d1_ddr2_ftdll_val ++ b ddr2_default_val ++ ++/* Set Orion 2 D1 ftdll values for DDR2 */ ++orin2_d1_ddr2_ftdll_val: ++ ldr r4, =FTDLL_DDR2_250MHZ_5281_D1 ++ ldr r7, =_250MHz ++ cmp r1, r7 ++ beq setFtdllReg ++ ldr r4, =FTDLL_DDR2_200MHZ_5281_D1 ++ ldr r7, =_200MHz ++ cmp r1, r7 ++ beq setFtdllReg ++ ldr r4, =FTDLL_DDR2_166MHZ_5281_D0 ++ ldr r7, =_166MHz ++ cmp r1, r7 ++ beq setFtdllReg ++ b ddr2_default_val ++ ++/* Set Orion 2 D0 ftdll values for DDR2 */ ++orin2_d0_ddr2_ftdll_val: ++ ldr r4, =FTDLL_DDR2_250MHZ_5281_D0 ++ ldr r7, =_250MHz ++ cmp r1, r7 ++ beq setFtdllReg ++ ldr r4, =FTDLL_DDR2_200MHZ_5281_D0 ++ ldr r7, =_200MHz ++ cmp r1, r7 ++ beq setFtdllReg ++ ldr r4, =FTDLL_DDR2_166MHZ_5281_D0 ++ ldr r7, =_166MHz ++ cmp r1, r7 ++ beq setFtdllReg ++ b ddr2_default_val ++2: ++ ldr r2, =MV_5182_DEV_ID ++ cmp r3, r2 ++ bne 3f ++ ++/* Set Orion nas ftdll values for DDR2 */ ++orin_nas_ftdll_val: ++ ldr r4, =FTDLL_DDR2_166MHZ_5182 ++ ldr r7, =_166MHz ++ cmp r1, r7 ++ beq setFtdllReg ++ ++/* default values for all other devices */ ++3: ++ddr2_default_val: ++ ldr r4, =FTDLL_DDR2_250MHZ ++ ldr r7, =_250MHz ++ cmp r1, r7 ++ beq setFtdllReg ++ ldr r4, =FTDLL_DDR2_200MHZ ++ ldr r7, =_200MHz ++ cmp r1, r7 ++ beq setFtdllReg ++ ldr r4, =FTDLL_DDR2_166MHZ ++ ldr r7, =_166MHz ++ cmp r1, r7 ++ beq setFtdllReg ++ ldr r4, =FTDLL_DDR2_133MHZ ++ ldr r7, =_133MHz ++ cmp r1, r7 ++ beq setFtdllReg ++ ldr r4, =0 ++ b setFtdllReg ++ ++ddr1FtdllVal: ++ ldr r2, =MV_5281_DEV_ID ++ cmp r3, r2 ++ bne 2f ++ MV_CTRL_REV_GET_ASM(r3, r2) ++ cmp r3, #MV_5281_D0_REV ++ bge orin2_ddr1_ftdll_val ++ b ddr1_default_val ++ ++/* Set Orion 2 D0 and above ftdll values for DDR1 */ ++orin2_ddr1_ftdll_val: ++ ldr r4, =FTDLL_DDR1_200MHZ_5281_D0 ++ ldr r7, =_200MHz ++ cmp r1, r7 ++ beq setFtdllReg ++ ldr r4, =FTDLL_DDR1_166MHZ_5281_D0 ++ ldr r7, =_166MHz ++ cmp r1, r7 ++ beq setFtdllReg ++ b ddr1_default_val ++2: ++ ldr r2, =MV_5181_DEV_ID ++ cmp r3, r2 ++ bne 3f ++ MV_CTRL_REV_GET_ASM(r3, r2) ++ cmp r3, #MV_5181_B1_REV ++ bge orin1_ddr1_ftdll_val ++ b ddr1_default_val ++ ++/* Set Orion 1 ftdll values for DDR1 */ ++orin1_ddr1_ftdll_val: ++ ldr r4, =FTDLL_DDR1_166MHZ_5181_B1 ++ ldr r7, =_166MHz ++ cmp r1, r7 ++ beq setFtdllReg ++3: ++ddr1_default_val: ++ ldr r4, =FTDLL_DDR1_133MHZ ++ ldr r7, =_133MHz ++ cmp r1, r7 ++ beq setFtdllReg ++ ++ ldr r4, =FTDLL_DDR1_166MHZ ++ ldr r7, =_166MHz ++ cmp r1, r7 ++ beq setFtdllReg ++ ++ ldr r4, =FTDLL_DDR1_200MHZ ++ ldr r7, =_200MHz ++ cmp r1, r7 ++ beq setFtdllReg ++ ++ ldr r4, =0 ++ ++setFtdllReg: ++ ++ MV_REG_WRITE_ASM (r4, r1, SDRAM_FTDLL_CONFIG_REG) ++ HTOLL(r4,r1) ++ bic r4, r4, #1 ++ MV_REG_WRITE_ASM (r4, r1, SDRAM_FTDLL_CONFIG_REG) ++ ++#endif /* !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L) */ ++#endif /* DB_FPGA */ ++ ++restoreTmpRegs: ++ /* Restore the registers we used to save the DDR detect values */ ++ ++ ldr r4, =DRAM_BUF_REG0_DV ++ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG0) ++ ++ ldr r4, =DRAM_BUF_REG1_DV ++ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG1) ++ ++ ldr r4, =DRAM_BUF_REG2_DV ++ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG2) ++ ++ ldr r4, =DRAM_BUF_REG3_DV ++ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG3) ++ ++ ldr r4, =DRAM_BUF_REG4_DV ++ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG4) ++ ++ ldr r4, =DRAM_BUF_REG5_DV ++ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG5) ++ ++ ldr r4, =DRAM_BUF_REG6_DV ++ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG6) ++ ++ ldr r4, =DRAM_BUF_REG7_DV ++ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG7) ++ ++ ldr r4, =DRAM_BUF_REG8_DV ++ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG8) ++ ++ ldr r4, =DRAM_BUF_REG9_DV ++ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG9) ++ ++ ldr r4, =DRAM_BUF_REG10_DV ++ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG10) ++ ++ ++ /* Restore registers */ ++ /* Save register on stack */ ++ cmp sp, #0 ++ beq no_stack_l ++load_from_stack: ++ ldmia sp!, {r1, r2, r3, r4, r7, r11} ++no_stack_l: ++ ++ mov pc, lr ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfConfig.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,192 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvDramIfConfigh ++#define __INCmvDramIfConfigh ++ ++/* includes */ ++ ++/* defines */ ++ ++/* registers defaults values */ ++ ++#define SDRAM_CONFIG_DV \ ++ (SDRAM_PERR_WRITE | \ ++ SDRAM_SRMODE | \ ++ SDRAM_SRCLK_GATED) ++ ++#define SDRAM_DUNIT_CTRL_LOW_DV \ ++ (SDRAM_CTRL_POS_RISE | \ ++ SDRAM_CLK1DRV_NORMAL | \ ++ SDRAM_LOCKEN_ENABLE) ++ ++#define SDRAM_ADDR_CTRL_DV 0 ++ ++#define SDRAM_TIMING_CTRL_LOW_REG_DV \ ++ ((0x2 << SDRAM_TRCD_OFFS) | \ ++ (0x2 << SDRAM_TRP_OFFS) | \ ++ (0x1 << SDRAM_TWR_OFFS) | \ ++ (0x0 << SDRAM_TWTR_OFFS) | \ ++ (0x5 << SDRAM_TRAS_OFFS) | \ ++ (0x1 << SDRAM_TRRD_OFFS)) ++/* TRFC 0x27, TW2W 0x1 */ ++#define SDRAM_TIMING_CTRL_HIGH_REG_DV (( 0x7 << SDRAM_TRFC_OFFS ) |\ ++ ( 0x2 << SDRAM_TRFC_EXT_OFFS) |\ ++ ( 0x1 << SDRAM_TW2W_OFFS)) ++ ++#define SDRAM_OPEN_PAGES_CTRL_REG_DV SDRAM_OPEN_PAGE_EN ++ ++/* DDR2 ODT default register values */ ++ ++/* Presence Ctrl Low Ctrl High Dunit Ctrl Ext Mode */ ++/* CS0 0x84210000 0x00000000 0x0000780F 0x00000440 */ ++/* CS0+CS1 0x84210000 0x00000000 0x0000780F 0x00000440 */ ++/* CS0+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ ++/* CS0+CS1+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ ++/* CS0+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ ++/* CS0+CS1+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ ++ ++#define DDR2_ODT_CTRL_LOW_CS0_DV 0x84210000 ++#define DDR2_ODT_CTRL_HIGH_CS0_DV 0x00000000 ++#define DDR2_DUNIT_ODT_CTRL_CS0_DV 0x0000780F ++#define DDR_SDRAM_EXT_MODE_CS0_DV 0x00000440 ++ ++#define DDR2_ODT_CTRL_LOW_CS0_CS2_DV 0x030C030C ++#define DDR2_ODT_CTRL_HIGH_CS0_CS2_DV 0x00000000 ++#define DDR2_DUNIT_ODT_CTRL_CS0_CS2_DV 0x0000740F ++#define DDR_SDRAM_EXT_MODE_CS0_CS2_DV 0x00000404 ++ ++ ++/* DDR SDRAM Adderss/Control and Data Pads Calibration default values */ ++#define DDR1_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \ ++ (1 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) ++#define DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \ ++ (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) ++ ++ ++#define DDR1_DATA_PAD_STRENGTH_TYPICAL_DV \ ++ (1 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) ++#define DDR2_DATA_PAD_STRENGTH_TYPICAL_DV \ ++ (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) ++ ++/* DDR SDRAM Mode Register default value */ ++#define DDR1_MODE_REG_DV 0x00000000 ++#define DDR2_MODE_REG_DV 0x00000400 ++ ++/* DDR SDRAM Timing parameter default values */ ++#define DDR1_TIMING_LOW_DV 0x11602220 ++#define DDR1_TIMING_HIGH_DV 0x0000000d ++ ++#define DDR2_TIMING_LOW_DV 0x11812220 ++#define DDR2_TIMING_HIGH_DV 0x0000030f ++ ++/* For Guideline (GL# MEM-4) DQS Reference Delay Tuning */ ++#define FTDLL_DDR1_166MHZ ((0x1 << 0) | \ ++ (0x7F<< 12) | \ ++ (0x1 << 22)) ++ ++#define FTDLL_DDR1_133MHZ FTDLL_DDR1_166MHZ ++ ++#define FTDLL_DDR1_200MHZ ((0x1 << 0) | \ ++ (0x1 << 12) | \ ++ (0x3 << 14) | \ ++ (0x1 << 18) | \ ++ (0x1 << 22)) ++ ++ ++#define FTDLL_DDR2_166MHZ ((0x1 << 0) | \ ++ (0x1 << 12) | \ ++ (0x1 << 14) | \ ++ (0x1 << 16) | \ ++ (0x1 << 19) | \ ++ (0xF << 20)) ++ ++#define FTDLL_DDR2_133MHZ FTDLL_DDR2_166MHZ ++ ++#define FTDLL_DDR2_200MHZ ((0x1 << 0) | \ ++ (0x1 << 12) | \ ++ (0x1 << 14) | \ ++ (0x1 << 16) | \ ++ (0x1 << 19) | \ ++ (0xF << 20)) ++ ++#define FTDLL_DDR2_250MHZ 0x445001 ++ ++/* Orion 1 B1 and above */ ++#define FTDLL_DDR1_166MHZ_5181_B1 0x45D001 ++ ++/* Orion nas */ ++#define FTDLL_DDR2_166MHZ_5182 0x597001 ++ ++/* Orion 2 D0 and above */ ++#define FTDLL_DDR1_166MHZ_5281_D0 0x8D0001 ++#define FTDLL_DDR1_200MHZ_5281_D0 0x8D0001 ++#define FTDLL_DDR2_166MHZ_5281_D0 0x485001 ++#define FTDLL_DDR2_200MHZ_5281_D0 0x485001 ++#define FTDLL_DDR2_250MHZ_5281_D0 0x445001 ++#define FTDLL_DDR2_200MHZ_5281_D1 0x995001 ++#define FTDLL_DDR2_250MHZ_5281_D1 0x984801 ++ ++#endif /* __INCmvDramIfh */ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/mvDramIfRegs.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,306 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvDramIfRegsh ++#define __INCmvDramIfRegsh ++ ++ ++/* DDR SDRAM Controller Address Decode Registers */ ++/* SDRAM CSn Base Address Register (SCBAR) */ ++#define SDRAM_BASE_ADDR_REG(csNum) (0x1500 + (csNum * 8)) ++#define SCBAR_BASE_OFFS 16 ++#define SCBAR_BASE_MASK (0xffff << SCBAR_BASE_OFFS) ++#define SCBAR_BASE_ALIGNMENT 0x10000 ++ ++/* SDRAM CSn Size Register (SCSR) */ ++#define SDRAM_SIZE_REG(csNum) (0x1504 + (csNum * 8)) ++#define SCSR_WIN_EN BIT0 ++#define SCSR_SIZE_OFFS 16 ++#define SCSR_SIZE_MASK (0xffff << SCSR_SIZE_OFFS) ++#define SCSR_SIZE_ALIGNMENT 0x10000 ++ ++/* configuration register */ ++#define SDRAM_CONFIG_REG 0x1400 ++#define SDRAM_REFRESH_OFFS 0 ++#define SDRAM_REFRESH_MAX 0x3000 ++#define SDRAM_REFRESH_MASK (SDRAM_REFRESH_MAX << SDRAM_REFRESH_OFFS) ++#define SDRAM_DWIDTH_OFFS 14 ++#define SDRAM_DWIDTH_MASK (3 << SDRAM_DWIDTH_OFFS) ++#define SDRAM_DWIDTH_16BIT (1 << SDRAM_DWIDTH_OFFS) ++#define SDRAM_DWIDTH_32BIT (2 << SDRAM_DWIDTH_OFFS) ++#define SDRAM_DTYPE_OFFS 16 ++#define SDRAM_DTYPE_MASK (1 << SDRAM_DTYPE_OFFS) ++#define SDRAM_DTYPE_DDR1 (0 << SDRAM_DTYPE_OFFS) ++#define SDRAM_DTYPE_DDR2 (1 << SDRAM_DTYPE_OFFS) ++#define SDRAM_REGISTERED (1 << 17) ++#define SDRAM_PERR_OFFS 18 ++#define SDRAM_PERR_MASK (1 << SDRAM_PERR_OFFS) ++#define SDRAM_PERR_NO_WRITE (0 << SDRAM_PERR_OFFS) ++#define SDRAM_PERR_WRITE (1 << SDRAM_PERR_OFFS) ++#define SDRAM_DCFG_OFFS 20 ++#define SDRAM_DCFG_MASK (0x3 << SDRAM_DCFG_OFFS) ++#define SDRAM_DCFG_X16_DEV (1 << SDRAM_DCFG_OFFS) ++#define SDRAM_DCFG_X8_DEV (2 << SDRAM_DCFG_OFFS) ++#define SDRAM_SRMODE (1 << 24) ++#define SDRAM_SRCLK_OFFS 25 ++#define SDRAM_SRCLK_MASK (1 << SDRAM_SRCLK_OFFS) ++#define SDRAM_SRCLK_KEPT (0 << SDRAM_SRCLK_OFFS) ++#define SDRAM_SRCLK_GATED (1 << SDRAM_SRCLK_OFFS) ++#define SDRAM_CATTH_OFFS 26 ++#define SDRAM_CATTHR_EN (1 << SDRAM_CATTH_OFFS) ++ ++ ++/* dunit control register */ ++#define SDRAM_DUNIT_CTRL_REG 0x1404 ++#define SDRAM_CTRL_POS_OFFS 6 ++#define SDRAM_CTRL_POS_FALL (0 << SDRAM_CTRL_POS_OFFS) ++#define SDRAM_CTRL_POS_RISE (1 << SDRAM_CTRL_POS_OFFS) ++#define SDRAM_CLK1DRV_OFFS 12 ++#define SDRAM_CLK1DRV_MASK (1 << SDRAM_CLK1DRV_OFFS) ++#define SDRAM_CLK1DRV_HIGH_Z (0 << SDRAM_CLK1DRV_OFFS) ++#define SDRAM_CLK1DRV_NORMAL (1 << SDRAM_CLK1DRV_OFFS) ++#define SDRAM_LOCKEN_OFFS 18 ++#define SDRAM_LOCKEN_MASK (1 << SDRAM_LOCKEN_OFFS) ++#define SDRAM_LOCKEN_DISABLE (0 << SDRAM_LOCKEN_OFFS) ++#define SDRAM_LOCKEN_ENABLE (1 << SDRAM_LOCKEN_OFFS) ++#define SDRAM_ST_BURST_DEL_OFFS 24 ++#define SDRAM_ST_BURST_DEL_MAX 0xf ++#define SDRAM_ST_BURST_DEL_MASK (SDRAM_ST_BURST_DEL_MAX< busClkPs) ++ { ++ mvOsOutput("Dram: ERR. Bank %d doesn't support memory clock!!!\n", i); ++ return MV_ERROR; ++ } ++ ++ /* All banks must support registry in order to activate it */ ++ if(bankInfo[i].registeredAddrAndControlInputs != ++ bankInfo[0].registeredAddrAndControlInputs) ++ { ++ mvOsOutput("Dram: ERR. different Registered settings !!!\n"); ++ return MV_ERROR; ++ } ++ ++ /* All banks must support same ECC mode */ ++ if(bankInfo[i].errorCheckType != ++ bankInfo[0].errorCheckType) ++ { ++ mvOsOutput("Dram: ERR. different ECC settings !!!\n"); ++ return MV_ERROR; ++ } ++ ++ } ++ else ++ { ++ if( i == 0 ) /* bank 0 doesn't exist */ ++ { ++ mvOsOutput("Dram: ERR. Fail to detect bank 0 !!!\n"); ++ return MV_ERROR; ++ } ++ else ++ { ++ DB(mvOsPrintf("Dram: Could not find bank %d\n", i)); ++ bankInfo[i].size = 0; /* Mark this bank as non exist */ ++ } ++ } ++ } ++ ++#ifdef MV_INCLUDE_SDRAM_CS2 ++ if (bankInfo[SDRAM_CS0].size < bankInfo[SDRAM_CS2].size) ++ { ++ MV_DRAM_CS_order[0] = SDRAM_CS2; ++ MV_DRAM_CS_order[1] = SDRAM_CS3; ++ MV_DRAM_CS_order[2] = SDRAM_CS0; ++ MV_DRAM_CS_order[3] = SDRAM_CS1; ++ DRAM_CS_Order[0] = SDRAM_CS2; ++ DRAM_CS_Order[1] = SDRAM_CS3; ++ DRAM_CS_Order[2] = SDRAM_CS0; ++ DRAM_CS_Order[3] = SDRAM_CS1; ++ ++ } ++ else ++#endif ++ { ++ MV_DRAM_CS_order[0] = SDRAM_CS0; ++ MV_DRAM_CS_order[1] = SDRAM_CS1; ++ DRAM_CS_Order[0] = SDRAM_CS0; ++ DRAM_CS_Order[1] = SDRAM_CS1; ++#ifdef MV_INCLUDE_SDRAM_CS2 ++ MV_DRAM_CS_order[2] = SDRAM_CS2; ++ MV_DRAM_CS_order[3] = SDRAM_CS3; ++ DRAM_CS_Order[2] = SDRAM_CS2; ++ DRAM_CS_Order[3] = SDRAM_CS3; ++#endif ++ } ++ ++ for(j = 0; j < MV_DRAM_MAX_CS; j++) ++ { ++ i = MV_DRAM_CS_order[j]; ++ ++ if (0 == bankInfo[i].size) ++ continue; ++ ++ /* Init the CPU window decode */ ++ /* Note that the Dimm width might be different then the device DRAM width */ ++#ifdef MV78XX0 ++ temp = MV_REG_READ(SDRAM_CONFIG_REG); ++ deviceW = ((temp & SDRAM_DWIDTH_MASK) == SDRAM_DWIDTH_32BIT )? 32 : 64; ++#else ++ deviceW = 16 /* KW family */; ++#endif ++ dimmW = bankInfo[0].dataWidth - (bankInfo[0].dataWidth % 16); ++ size = ((bankInfo[i].size << 20) / (dimmW/deviceW)); ++ ++ /* We can not change DRAM window settings while excecuting */ ++ /* code from it. That is why we skip the DRAM CS[0], saving */ ++ /* it to the ROM configuration routine */ ++ ++ numOfAllDevices += bankInfo[i].numberOfDevices; ++ if (i == MV_DRAM_CS_order[0]) ++ { ++ MV_U32 sizeToReg; ++ /* Translate the given window size to register format */ ++ sizeToReg = ctrlSizeToReg(size, SCSR_SIZE_ALIGNMENT); ++ /* Size parameter validity check. */ ++ if (-1 == sizeToReg) ++ { ++ mvOsOutput("DRAM: mvCtrlAddrDecToReg: ERR. Win %d size invalid.\n" ++ ,i); ++ return MV_BAD_PARAM; ++ } ++ ++ DB(mvOsPrintf("Dram: Bank 0 Size - %x\n",sizeToReg);) ++ sizeToReg = (sizeToReg << SCSR_SIZE_OFFS); ++ sizeToReg |= SCSR_WIN_EN; ++ MV_REG_WRITE(DRAM_BUF_REG0, sizeToReg); ++ } ++ else ++ { ++ dramDecWin.addrWin.baseLow = base; ++ dramDecWin.addrWin.size = size; ++ dramDecWin.enable = MV_TRUE; ++ DB(mvOsPrintf("Dram: Enable window %d base 0x%x, size=0x%x\n",i, base, size)); ++ ++ /* Check if the DRAM size is more then 3GByte */ ++ if (base < 0xC0000000) ++ { ++ DB(mvOsPrintf("Dram: Enable window %d base 0x%x, size=0x%x\n",i, base, size)); ++ if (MV_OK != mvCpuIfTargetWinSet(i, &dramDecWin)) ++ { ++ mvOsPrintf("Dram: ERR. Fail to set bank %d!!!\n", SDRAM_CS0 + i); ++ return MV_ERROR; ++ } ++ } ++ } ++ ++ base += size; ++ ++ /* update the suportedCasLatencies mask */ ++ bankInfo[0].suportedCasLatencies &= bankInfo[i].suportedCasLatencies; ++ } ++ ++ /* calculate minimum CAS */ ++ minCas = minCasCalc(&bankInfo[0], &bankInfo[2], busClk, forcedCl); ++ if (0 == minCas) ++ { ++ mvOsOutput("Dram: Warn: Could not find CAS compatible to SysClk %dMhz\n", ++ (busClk / 1000000)); ++ ++ minCas = DDR2_CL_4; /* Continue with this CAS */ ++ mvOsOutput("Set default CAS latency 4\n"); ++ } ++ ++ /* calc SDRAM_CONFIG_REG and save it to temp register */ ++ temp = sdramConfigRegCalc(&bankInfo[0],&bankInfo[2], busClk); ++ if(-1 == temp) ++ { ++ mvOsOutput("Dram: ERR. sdramConfigRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ ++ /* check if ECC is enabled by the user */ ++ if(eccDisable) ++ { ++ /* turn off ECC*/ ++ temp &= ~BIT18; ++ } ++ DB(mvOsPrintf("Dram: sdramConfigRegCalc - %x\n",temp);) ++ MV_REG_WRITE(DRAM_BUF_REG1, temp); ++ ++ /* calc SDRAM_MODE_REG and save it to temp register */ ++ temp = sdramModeRegCalc(minCas); ++ if(-1 == temp) ++ { ++ mvOsOutput("Dram: ERR. sdramModeRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Dram: sdramModeRegCalc - %x\n",temp);) ++ MV_REG_WRITE(DRAM_BUF_REG2, temp); ++ ++ /* calc SDRAM_EXTENDED_MODE_REG and save it to temp register */ ++ temp = sdramExtModeRegCalc(&bankInfo[0], busClk); ++ if(-1 == temp) ++ { ++ mvOsOutput("Dram: ERR. sdramExtModeRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Dram: sdramExtModeRegCalc - %x\n",temp);) ++ MV_REG_WRITE(DRAM_BUF_REG10, temp); ++ ++ /* calc D_UNIT_CONTROL_LOW and save it to temp register */ ++ TTMode = MV_FALSE; ++ DB(mvOsPrintf("Dram: numOfAllDevices = %x\n",numOfAllDevices);) ++ if( (numOfAllDevices > 9) && (bankInfo[0].registeredAddrAndControlInputs == MV_FALSE) ) ++ { ++ if ( ( (numOfAllDevices > 9) && (busClk > MV_BOARD_SYSCLK_200MHZ) ) || ++ (numOfAllDevices > 18) ) ++ { ++ mvOsOutput("Enable 2T "); ++ TTMode = MV_TRUE; ++ } ++ } ++ ++ temp = dunitCtrlLowRegCalc(&bankInfo[0], minCas, busClk, TTMode ); ++ if(-1 == temp) ++ { ++ mvOsOutput("Dram: ERR. dunitCtrlLowRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Dram: dunitCtrlLowRegCalc - %x\n",temp);) ++ MV_REG_WRITE(DRAM_BUF_REG3, temp); ++ ++ /* calc D_UNIT_CONTROL_HIGH and save it to temp register */ ++ temp = dunitCtrlHighRegCalc(&bankInfo[0], busClk); ++ if(-1 == temp) ++ { ++ mvOsOutput("Dram: ERR. dunitCtrlHighRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Dram: dunitCtrlHighRegCalc - %x\n",temp);) ++ /* check if ECC is enabled by the user */ ++ if(eccDisable) ++ { ++ /* turn off sample stage if no ecc */ ++ temp &= ~SDRAM__D2P_EN;; ++ } ++ MV_REG_WRITE(DRAM_BUF_REG13, temp); ++ ++ /* calc SDRAM_ADDR_CTRL_REG and save it to temp register */ ++ temp = sdramAddrCtrlRegCalc(&bankInfo[0],&bankInfo[2]); ++ if(-1 == temp) ++ { ++ mvOsOutput("Dram: ERR. sdramAddrCtrlRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Dram: sdramAddrCtrlRegCalc - %x\n",temp);) ++ MV_REG_WRITE(DRAM_BUF_REG4, temp); ++ ++ /* calc SDRAM_TIMING_CTRL_LOW_REG and save it to temp register */ ++ temp = sdramTimeCtrlLowRegCalc(&bankInfo[0], minCas, busClk); ++ if(-1 == temp) ++ { ++ mvOsOutput("Dram: ERR. sdramTimeCtrlLowRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Dram: sdramTimeCtrlLowRegCalc - %x\n",temp);) ++ MV_REG_WRITE(DRAM_BUF_REG5, temp); ++ ++ /* calc SDRAM_TIMING_CTRL_HIGH_REG and save it to temp register */ ++ temp = sdramTimeCtrlHighRegCalc(&bankInfo[0], busClk); ++ if(-1 == temp) ++ { ++ mvOsOutput("Dram: ERR. sdramTimeCtrlHighRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Dram: sdramTimeCtrlHighRegCalc - %x\n",temp);) ++ MV_REG_WRITE(DRAM_BUF_REG6, temp); ++ ++ sdramDDr2OdtConfig(bankInfo); ++ ++ /* calc DDR2_SDRAM_TIMING_LOW_REG and save it to temp register */ ++ temp = sdramDdr2TimeLoRegCalc(minCas); ++ if(-1 == temp) ++ { ++ mvOsOutput("Dram: ERR. sdramDdr2TimeLoRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Dram: sdramDdr2TimeLoRegCalc - %x\n",temp);) ++ MV_REG_WRITE(DRAM_BUF_REG11, temp); ++ ++ /* calc DDR2_SDRAM_TIMING_HIGH_REG and save it to temp register */ ++ temp = sdramDdr2TimeHiRegCalc(minCas); ++ if(-1 == temp) ++ { ++ mvOsOutput("Dram: ERR. sdramDdr2TimeHiRegCalc failed !!!\n"); ++ return MV_ERROR; ++ } ++ DB(mvOsPrintf("Dram: sdramDdr2TimeHiRegCalc - %x\n",temp);) ++ MV_REG_WRITE(DRAM_BUF_REG12, temp); ++#endif ++ ++ /* Note that DDR SDRAM Address/Control and Data pad calibration */ ++ /* settings is done in mvSdramIfConfig.s */ ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvDramIfBankBaseGet - Get DRAM interface bank base. ++* ++* DESCRIPTION: ++* This function returns the 32 bit base address of a given DRAM bank. ++* ++* INPUT: ++* bankNum - Bank number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* DRAM bank size. If bank is disabled or paramter is invalid, the ++* function returns -1. ++* ++*******************************************************************************/ ++MV_U32 mvDramIfBankBaseGet(MV_U32 bankNum) ++{ ++ DB(mvOsPrintf("Dram: mvDramIfBankBaseGet Bank %d base addr is %x \n", ++ bankNum, mvCpuIfTargetWinBaseLowGet(SDRAM_CS0 + bankNum))); ++ return mvCpuIfTargetWinBaseLowGet(SDRAM_CS0 + bankNum); ++} ++ ++/******************************************************************************* ++* mvDramIfBankSizeGet - Get DRAM interface bank size. ++* ++* DESCRIPTION: ++* This function returns the size of a given DRAM bank. ++* ++* INPUT: ++* bankNum - Bank number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* DRAM bank size. If bank is disabled the function return '0'. In case ++* or paramter is invalid, the function returns -1. ++* ++*******************************************************************************/ ++MV_U32 mvDramIfBankSizeGet(MV_U32 bankNum) ++{ ++ DB(mvOsPrintf("Dram: mvDramIfBankSizeGet Bank %d size is %x \n", ++ bankNum, mvCpuIfTargetWinSizeGet(SDRAM_CS0 + bankNum))); ++ return mvCpuIfTargetWinSizeGet(SDRAM_CS0 + bankNum); ++} ++ ++ ++/******************************************************************************* ++* mvDramIfSizeGet - Get DRAM interface total size. ++* ++* DESCRIPTION: ++* This function get the DRAM total size. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* DRAM total size. In case or paramter is invalid, the function ++* returns -1. ++* ++*******************************************************************************/ ++MV_U32 mvDramIfSizeGet(MV_VOID) ++{ ++ MV_U32 size = 0, i; ++ ++ for(i = 0; i < MV_DRAM_MAX_CS; i++) ++ size += mvDramIfBankSizeGet(i); ++ ++ DB(mvOsPrintf("Dram: mvDramIfSizeGet size is %x \n",size)); ++ return size; ++} ++ ++/******************************************************************************* ++* mvDramIfSingleBitErrThresholdSet - Set single bit ECC threshold. ++* ++* DESCRIPTION: ++* The ECC single bit error threshold is the number of single bit ++* errors to happen before the Dunit generates an interrupt. ++* This function set single bit ECC threshold. ++* ++* INPUT: ++* threshold - threshold. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM if threshold is to big, MV_OK otherwise. ++* ++*******************************************************************************/ ++MV_STATUS mvDramIfSingleBitErrThresholdSet(MV_U32 threshold) ++{ ++ MV_U32 regVal; ++ ++ if (threshold > SECR_THRECC_MAX) ++ { ++ return MV_BAD_PARAM; ++ } ++ ++ regVal = MV_REG_READ(SDRAM_ECC_CONTROL_REG); ++ regVal &= ~SECR_THRECC_MASK; ++ regVal |= ((SECR_THRECC(threshold) & SECR_THRECC_MASK)); ++ MV_REG_WRITE(SDRAM_ECC_CONTROL_REG, regVal); ++ ++ return MV_OK; ++} ++ ++#ifndef MV_STATIC_DRAM_ON_BOARD ++/******************************************************************************* ++* minCasCalc - Calculate the Minimum CAS latency which can be used. ++* ++* DESCRIPTION: ++* Calculate the minimum CAS latency that can be used, base on the DRAM ++* parameters and the SDRAM bus Clock freq. ++* ++* INPUT: ++* busClk - the DRAM bus Clock. ++* pBankInfo - bank info parameters. ++* forcedCl - Forced CAS Latency multiplied by 10. If equal to zero, do not force. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* The minimum CAS Latency. The function returns 0 if max CAS latency ++* supported by banks is incompatible with system bus clock frequancy. ++* ++*******************************************************************************/ ++ ++static MV_U32 minCasCalc(MV_DRAM_BANK_INFO *pBankInfo,MV_DRAM_BANK_INFO *pBankInfo2, MV_U32 busClk, MV_U32 forcedCl) ++{ ++ MV_U32 count = 1, j; ++ MV_U32 busClkPs = 1000000000 / (busClk / 1000); /* in ps units */ ++ MV_U32 startBit, stopBit; ++ MV_U32 minCas0 = 0, minCas2 = 0; ++ ++ ++ /* DDR 2: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * ++ Disco VI= * TBD | TBD | 5 | 4 | 3 | TBD | TBD | TBD * ++ Disco Duo= * TBD | 6 | 5 | 4 | 3 | TBD | TBD | TBD * ++ *********************************************************/ ++ ++ ++ /* If we are asked to use the forced CAL we change the suported CAL to be forcedCl only */ ++ if (forcedCl) ++ { ++ mvOsOutput("DRAM: Using forced CL %d.%d\n", (forcedCl / 10), (forcedCl % 10)); ++ ++ if (forcedCl == 30) ++ pBankInfo->suportedCasLatencies = 0x08; ++ else if (forcedCl == 40) ++ pBankInfo->suportedCasLatencies = 0x10; ++ else if (forcedCl == 50) ++ pBankInfo->suportedCasLatencies = 0x20; ++ else if (forcedCl == 60) ++ pBankInfo->suportedCasLatencies = 0x40; ++ else ++ { ++ mvOsPrintf("Forced CL %d.%d not supported. Set default CL 4\n", ++ (forcedCl / 10), (forcedCl % 10)); ++ pBankInfo->suportedCasLatencies = 0x10; ++ } ++ ++ return pBankInfo->suportedCasLatencies; ++ } ++ ++ /* go over the supported cas mask from Max Cas down and check if the */ ++ /* SysClk stands in its time requirments. */ ++ ++ DB(mvOsPrintf("Dram: minCasCalc supported mask = %x busClkPs = %x \n", ++ pBankInfo->suportedCasLatencies,busClkPs )); ++ count = 1; ++ for(j = 7; j > 0; j--) ++ { ++ if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) ++ { ++ /* Reset the bits for CL incompatible for the sysClk */ ++ switch (count) ++ { ++ case 1: ++ if (pBankInfo->minCycleTimeAtMaxCasLatPs > busClkPs) ++ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); ++ count++; ++ break; ++ case 2: ++ if (pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps > busClkPs) ++ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); ++ count++; ++ break; ++ case 3: ++ if (pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps > busClkPs) ++ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); ++ count++; ++ break; ++ default: ++ pBankInfo->suportedCasLatencies &= ~(BIT0 << j); ++ break; ++ } ++ } ++ } ++ ++ DB(mvOsPrintf("Dram: minCasCalc support = %x (after SysCC calc)\n", ++ pBankInfo->suportedCasLatencies )); ++ ++ count = 1; ++ DB(mvOsPrintf("Dram2: minCasCalc supported mask = %x busClkPs = %x \n", ++ pBankInfo2->suportedCasLatencies,busClkPs )); ++ for(j = 7; j > 0; j--) ++ { ++ if((pBankInfo2->suportedCasLatencies >> j) & BIT0 ) ++ { ++ /* Reset the bits for CL incompatible for the sysClk */ ++ switch (count) ++ { ++ case 1: ++ if (pBankInfo2->minCycleTimeAtMaxCasLatPs > busClkPs) ++ pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); ++ count++; ++ break; ++ case 2: ++ if (pBankInfo2->minCycleTimeAtMaxCasLatMinus1Ps > busClkPs) ++ pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); ++ count++; ++ break; ++ case 3: ++ if (pBankInfo2->minCycleTimeAtMaxCasLatMinus2Ps > busClkPs) ++ pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); ++ count++; ++ break; ++ default: ++ pBankInfo2->suportedCasLatencies &= ~(BIT0 << j); ++ break; ++ } ++ } ++ } ++ ++ DB(mvOsPrintf("Dram2: minCasCalc support = %x (after SysCC calc)\n", ++ pBankInfo2->suportedCasLatencies )); ++ ++ startBit = 3; /* DDR2 support CL start with CL3 (bit 3) */ ++ stopBit = 6; /* DDR2 support CL stops with CL6 (bit 6) */ ++ ++ for(j = startBit; j <= stopBit ; j++) ++ { ++ if((pBankInfo->suportedCasLatencies >> j) & BIT0 ) ++ { ++ DB(mvOsPrintf("Dram: minCasCalc choose CAS %x \n",(BIT0 << j))); ++ minCas0 = (BIT0 << j); ++ break; ++ } ++ } ++ ++ for(j = startBit; j <= stopBit ; j++) ++ { ++ if((pBankInfo2->suportedCasLatencies >> j) & BIT0 ) ++ { ++ DB(mvOsPrintf("Dram: minCasCalc choose CAS %x \n",(BIT0 << j))); ++ minCas2 = (BIT0 << j); ++ break; ++ } ++ } ++ ++ if (minCas2 > minCas0) ++ return minCas2; ++ else ++ return minCas0; ++ ++ return 0; ++} ++ ++/******************************************************************************* ++* sdramConfigRegCalc - Calculate sdram config register ++* ++* DESCRIPTION: Calculate sdram config register optimized value based ++* on the bank info parameters. ++* ++* INPUT: ++* busClk - the DRAM bus Clock. ++* pBankInfo - sdram bank parameters ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram config reg value. ++* ++*******************************************************************************/ ++static MV_U32 sdramConfigRegCalc(MV_DRAM_BANK_INFO *pBankInfo,MV_DRAM_BANK_INFO *pBankInfo2, MV_U32 busClk) ++{ ++ MV_U32 sdramConfig = 0; ++ MV_U32 refreshPeriod; ++ ++ busClk /= 1000000; /* we work with busClk in MHz */ ++ ++ sdramConfig = MV_REG_READ(SDRAM_CONFIG_REG); ++ ++ /* figure out the memory refresh internal */ ++ switch (pBankInfo->refreshInterval & 0xf) ++ { ++ case 0x0: /* refresh period is 15.625 usec */ ++ refreshPeriod = 15625; ++ break; ++ case 0x1: /* refresh period is 3.9 usec */ ++ refreshPeriod = 3900; ++ break; ++ case 0x2: /* refresh period is 7.8 usec */ ++ refreshPeriod = 7800; ++ break; ++ case 0x3: /* refresh period is 31.3 usec */ ++ refreshPeriod = 31300; ++ break; ++ case 0x4: /* refresh period is 62.5 usec */ ++ refreshPeriod = 62500; ++ break; ++ case 0x5: /* refresh period is 125 usec */ ++ refreshPeriod = 125000; ++ break; ++ default: /* refresh period undefined */ ++ mvOsPrintf("Dram: ERR. DRAM refresh period is unknown!\n"); ++ return -1; ++ } ++ ++ /* Now the refreshPeriod is in register format value */ ++ refreshPeriod = (busClk * refreshPeriod) / 1000; ++ ++ DB(mvOsPrintf("Dram: sdramConfigRegCalc calculated refresh interval %0x\n", ++ refreshPeriod)); ++ ++ /* make sure the refresh value is only 14 bits */ ++ if(refreshPeriod > SDRAM_REFRESH_MAX) ++ { ++ refreshPeriod = SDRAM_REFRESH_MAX; ++ DB(mvOsPrintf("Dram: sdramConfigRegCalc adjusted refresh interval %0x\n", ++ refreshPeriod)); ++ } ++ ++ /* Clear the refresh field */ ++ sdramConfig &= ~SDRAM_REFRESH_MASK; ++ ++ /* Set new value to refresh field */ ++ sdramConfig |= (refreshPeriod & SDRAM_REFRESH_MASK); ++ ++ /* registered DRAM ? */ ++ if ( pBankInfo->registeredAddrAndControlInputs ) ++ { ++ /* it's registered DRAM, so set the reg. DRAM bit */ ++ sdramConfig |= SDRAM_REGISTERED; ++ DB(mvOsPrintf("DRAM Attribute: Registered address and control inputs.\n");) ++ } ++ ++ /* ECC and IERR support */ ++ sdramConfig &= ~SDRAM_ECC_MASK; /* Clear ECC field */ ++ sdramConfig &= ~SDRAM_IERR_MASK; /* Clear IErr field */ ++ ++ if ( pBankInfo->errorCheckType ) ++ { ++ sdramConfig |= SDRAM_ECC_EN; ++ sdramConfig |= SDRAM_IERR_REPORTE; ++ DB(mvOsPrintf("Dram: mvDramIfDetect Enabling ECC\n")); ++ } ++ else ++ { ++ sdramConfig |= SDRAM_ECC_DIS; ++ sdramConfig |= SDRAM_IERR_IGNORE; ++ DB(mvOsPrintf("Dram: mvDramIfDetect Disabling ECC!\n")); ++ } ++ /* Set static default settings */ ++ sdramConfig |= SDRAM_CONFIG_DV; ++ ++ DB(mvOsPrintf("Dram: sdramConfigRegCalc set sdramConfig to 0x%x\n", ++ sdramConfig)); ++ ++ return sdramConfig; ++} ++ ++/******************************************************************************* ++* sdramModeRegCalc - Calculate sdram mode register ++* ++* DESCRIPTION: Calculate sdram mode register optimized value based ++* on the bank info parameters and the minCas. ++* ++* INPUT: ++* minCas - minimum CAS supported. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram mode reg value. ++* ++*******************************************************************************/ ++static MV_U32 sdramModeRegCalc(MV_U32 minCas) ++{ ++ MV_U32 sdramMode; ++ ++ sdramMode = MV_REG_READ(SDRAM_MODE_REG); ++ ++ /* Clear CAS Latency field */ ++ sdramMode &= ~SDRAM_CL_MASK; ++ ++ DB(mvOsPrintf("DRAM CAS Latency ");) ++ ++ switch (minCas) ++ { ++ case DDR2_CL_3: ++ sdramMode |= SDRAM_DDR2_CL_3; ++ DB(mvOsPrintf("3.\n");) ++ break; ++ case DDR2_CL_4: ++ sdramMode |= SDRAM_DDR2_CL_4; ++ DB(mvOsPrintf("4.\n");) ++ break; ++ case DDR2_CL_5: ++ sdramMode |= SDRAM_DDR2_CL_5; ++ DB(mvOsPrintf("5.\n");) ++ break; ++ case DDR2_CL_6: ++ sdramMode |= SDRAM_DDR2_CL_6; ++ DB(mvOsPrintf("6.\n");) ++ break; ++ default: ++ mvOsOutput("\nsdramModeRegCalc ERROR: Max. CL out of range\n"); ++ return -1; ++ } ++ ++ DB(mvOsPrintf("\nsdramModeRegCalc register 0x%x\n", sdramMode )); ++ ++ return sdramMode; ++} ++/******************************************************************************* ++* sdramExtModeRegCalc - Calculate sdram Extended mode register ++* ++* DESCRIPTION: ++* Return sdram Extended mode register value based ++* on the bank info parameters and bank presence. ++* ++* INPUT: ++* pBankInfo - sdram bank parameters ++* busClk - DRAM frequency ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram Extended mode reg value. ++* ++*******************************************************************************/ ++static MV_U32 sdramExtModeRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) ++{ ++ MV_U32 populateBanks = 0; ++ int bankNum; ++ ++ /* Represent the populate banks in binary form */ ++ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) ++ { ++ if (0 != pBankInfo[bankNum].size) ++ { ++ populateBanks |= (1 << bankNum); ++ } ++ } ++ ++ switch(populateBanks) ++ { ++ case(BANK_PRESENT_CS0): ++ case(BANK_PRESENT_CS0_CS1): ++ return DDR_SDRAM_EXT_MODE_CS0_CS1_DV; ++ ++ case(BANK_PRESENT_CS0_CS2): ++ case(BANK_PRESENT_CS0_CS1_CS2): ++ case(BANK_PRESENT_CS0_CS2_CS3): ++ case(BANK_PRESENT_CS0_CS2_CS3_CS4): ++ if (busClk >= MV_BOARD_SYSCLK_267MHZ) ++ return DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV; ++ else ++ return DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV; ++ ++ default: ++ mvOsOutput("sdramExtModeRegCalc: Invalid DRAM bank presence\n"); ++ return -1; ++ } ++ return 0; ++} ++ ++/******************************************************************************* ++* dunitCtrlLowRegCalc - Calculate sdram dunit control low register ++* ++* DESCRIPTION: Calculate sdram dunit control low register optimized value based ++* on the bank info parameters and the minCas. ++* ++* INPUT: ++* pBankInfo - sdram bank parameters ++* minCas - minimum CAS supported. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram dunit control low reg value. ++* ++*******************************************************************************/ ++static MV_U32 dunitCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas, MV_U32 busClk, MV_STATUS TTMode) ++{ ++ MV_U32 dunitCtrlLow, cl; ++ MV_U32 sbOutR[4]={3,5,7,9} ; ++ MV_U32 sbOutU[4]={1,3,5,7} ; ++ ++ dunitCtrlLow = MV_REG_READ(SDRAM_DUNIT_CTRL_REG); ++ ++ DB(mvOsPrintf("Dram: dunitCtrlLowRegCalc\n")); ++ ++ /* Clear StBurstOutDel field */ ++ dunitCtrlLow &= ~SDRAM_SB_OUT_MASK; ++ ++ /* Clear StBurstInDel field */ ++ dunitCtrlLow &= ~SDRAM_SB_IN_MASK; ++ ++ /* Clear CtrlPos field */ ++ dunitCtrlLow &= ~SDRAM_CTRL_POS_MASK; ++ ++ /* Clear 2T field */ ++ dunitCtrlLow &= ~SDRAM_2T_MASK; ++ if (TTMode == MV_TRUE) ++ { ++ dunitCtrlLow |= SDRAM_2T_MODE; ++ } ++ ++ /* For proper sample of read data set the Dunit Control register's */ ++ /* stBurstInDel bits [27:24] */ ++ /* 200MHz - 267MHz None reg = CL + 1 */ ++ /* 200MHz - 267MHz reg = CL + 2 */ ++ /* > 267MHz None reg = CL + 2 */ ++ /* > 267MHz reg = CL + 3 */ ++ ++ /* For proper sample of read data set the Dunit Control register's */ ++ /* stBurstOutDel bits [23:20] */ ++ /********-********-********-********- ++ * CL=3 | CL=4 | CL=5 | CL=6 | ++ *********-********-********-********- ++ Not Reg. * 0001 | 0011 | 0101 | 0111 | ++ *********-********-********-********- ++ Registered * 0011 | 0101 | 0111 | 1001 | ++ *********-********-********-********/ ++ ++ /* Set Dunit Control low default value */ ++ dunitCtrlLow |= SDRAM_DUNIT_CTRL_LOW_DDR2_DV; ++ ++ switch (minCas) ++ { ++ case DDR2_CL_3: cl = 3; break; ++ case DDR2_CL_4: cl = 4; break; ++ case DDR2_CL_5: cl = 5; break; ++ case DDR2_CL_6: cl = 6; break; ++ default: ++ mvOsOutput("Dram: dunitCtrlLowRegCalc Max. CL out of range %d\n", minCas); ++ return -1; ++ } ++ ++ /* registerd DDR SDRAM? */ ++ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) ++ { ++ dunitCtrlLow |= (sbOutR[cl-3]) << SDRAM_SB_OUT_DEL_OFFS; ++ } ++ else ++ { ++ dunitCtrlLow |= (sbOutU[cl-3]) << SDRAM_SB_OUT_DEL_OFFS; ++ } ++ ++ DB(mvOsPrintf("\n\ndunitCtrlLowRegCalc: CL = %d, frequencies=%d\n", cl, busClk)); ++ ++ if (busClk <= MV_BOARD_SYSCLK_267MHZ) ++ { ++ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) ++ cl = cl + 2; ++ else ++ cl = cl + 1; ++ } ++ else ++ { ++ if (pBankInfo->registeredAddrAndControlInputs == MV_TRUE) ++ cl = cl + 3; ++ else ++ cl = cl + 2; ++ } ++ ++ DB(mvOsPrintf("dunitCtrlLowRegCalc: SDRAM_SB_IN_DEL_OFFS = %d \n", cl)); ++ dunitCtrlLow |= cl << SDRAM_SB_IN_DEL_OFFS; ++ ++ DB(mvOsPrintf("Dram: Reg dunit control low = %x\n", dunitCtrlLow )); ++ ++ return dunitCtrlLow; ++} ++ ++/******************************************************************************* ++* dunitCtrlHighRegCalc - Calculate sdram dunit control high register ++* ++* DESCRIPTION: Calculate sdram dunit control high register optimized value based ++* on the bus clock. ++* ++* INPUT: ++* busClk - DRAM frequency. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram dunit control high reg value. ++* ++*******************************************************************************/ ++static MV_U32 dunitCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) ++{ ++ MV_U32 dunitCtrlHigh; ++ dunitCtrlHigh = MV_REG_READ(SDRAM_DUNIT_CTRL_HI_REG); ++ if(busClk > MV_BOARD_SYSCLK_300MHZ) ++ dunitCtrlHigh |= SDRAM__P2D_EN; ++ else ++ dunitCtrlHigh &= ~SDRAM__P2D_EN; ++ ++ if(busClk > MV_BOARD_SYSCLK_267MHZ) ++ dunitCtrlHigh |= (SDRAM__WR_MESH_DELAY_EN | SDRAM__PUP_ZERO_SKEW_EN | SDRAM__ADD_HALF_FCC_EN); ++ ++ /* If ECC support we turn on D2P sample */ ++ dunitCtrlHigh &= ~SDRAM__D2P_EN; /* Clear D2P bit */ ++ if (( pBankInfo->errorCheckType ) && (busClk > MV_BOARD_SYSCLK_267MHZ)) ++ dunitCtrlHigh |= SDRAM__D2P_EN; ++ ++ return dunitCtrlHigh; ++} ++ ++/******************************************************************************* ++* sdramAddrCtrlRegCalc - Calculate sdram address control register ++* ++* DESCRIPTION: Calculate sdram address control register optimized value based ++* on the bank info parameters and the minCas. ++* ++* INPUT: ++* pBankInfo - sdram bank parameters ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram address control reg value. ++* ++*******************************************************************************/ ++static MV_U32 sdramAddrCtrlRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_DRAM_BANK_INFO *pBankInfoDIMM1) ++{ ++ MV_U32 addrCtrl = 0; ++ ++ if (pBankInfoDIMM1->size) ++ { ++ switch (pBankInfoDIMM1->sdramWidth) ++ { ++ case 4: /* memory is x4 */ ++ mvOsOutput("sdramAddrCtrlRegCalc: Error - x4 not supported!\n"); ++ return -1; ++ break; ++ case 8: /* memory is x8 */ ++ addrCtrl |= SDRAM_ADDRSEL_X8(2) | SDRAM_ADDRSEL_X8(3); ++ DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device DIMM2 width x8\n")); ++ break; ++ case 16: ++ addrCtrl |= SDRAM_ADDRSEL_X16(2) | SDRAM_ADDRSEL_X16(3); ++ DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device DIMM2 width x16\n")); ++ break; ++ default: /* memory width unsupported */ ++ mvOsOutput("sdramAddrCtrlRegCalc: ERR. DRAM chip width is unknown!\n"); ++ return -1; ++ } ++ } ++ ++ switch (pBankInfo->sdramWidth) ++ { ++ case 4: /* memory is x4 */ ++ mvOsOutput("sdramAddrCtrlRegCalc: Error - x4 not supported!\n"); ++ return -1; ++ break; ++ case 8: /* memory is x8 */ ++ addrCtrl |= SDRAM_ADDRSEL_X8(0) | SDRAM_ADDRSEL_X8(1); ++ DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device width x8\n")); ++ break; ++ case 16: ++ addrCtrl |= SDRAM_ADDRSEL_X16(0) | SDRAM_ADDRSEL_X16(1); ++ DB(mvOsPrintf("sdramAddrCtrlRegCalc: sdramAddrCtrlRegCalc SDRAM device width x16\n")); ++ break; ++ default: /* memory width unsupported */ ++ mvOsOutput("sdramAddrCtrlRegCalc: ERR. DRAM chip width is unknown!\n"); ++ return -1; ++ } ++ ++ /* Note that density is in MB units */ ++ switch (pBankInfo->deviceDensity) ++ { ++ case 256: /* 256 Mbit */ ++ DB(mvOsPrintf("DRAM Device Density 256Mbit\n")); ++ addrCtrl |= SDRAM_DSIZE_256Mb(0) | SDRAM_DSIZE_256Mb(1); ++ break; ++ case 512: /* 512 Mbit */ ++ DB(mvOsPrintf("DRAM Device Density 512Mbit\n")); ++ addrCtrl |= SDRAM_DSIZE_512Mb(0) | SDRAM_DSIZE_512Mb(1); ++ break; ++ case 1024: /* 1 Gbit */ ++ DB(mvOsPrintf("DRAM Device Density 1Gbit\n")); ++ addrCtrl |= SDRAM_DSIZE_1Gb(0) | SDRAM_DSIZE_1Gb(1); ++ break; ++ case 2048: /* 2 Gbit */ ++ DB(mvOsPrintf("DRAM Device Density 2Gbit\n")); ++ addrCtrl |= SDRAM_DSIZE_2Gb(0) | SDRAM_DSIZE_2Gb(1); ++ break; ++ default: ++ mvOsOutput("Dram: sdramAddrCtrl unsupported RAM-Device size %d\n", ++ pBankInfo->deviceDensity); ++ return -1; ++ } ++ ++ if (pBankInfoDIMM1->size) ++ { ++ switch (pBankInfoDIMM1->deviceDensity) ++ { ++ case 256: /* 256 Mbit */ ++ DB(mvOsPrintf("DIMM2: DRAM Device Density 256Mbit\n")); ++ addrCtrl |= SDRAM_DSIZE_256Mb(2) | SDRAM_DSIZE_256Mb(3); ++ break; ++ case 512: /* 512 Mbit */ ++ DB(mvOsPrintf("DIMM2: DRAM Device Density 512Mbit\n")); ++ addrCtrl |= SDRAM_DSIZE_512Mb(2) | SDRAM_DSIZE_512Mb(3); ++ break; ++ case 1024: /* 1 Gbit */ ++ DB(mvOsPrintf("DIMM2: DRAM Device Density 1Gbit\n")); ++ addrCtrl |= SDRAM_DSIZE_1Gb(2) | SDRAM_DSIZE_1Gb(3); ++ break; ++ case 2048: /* 2 Gbit */ ++ DB(mvOsPrintf("DIMM2: DRAM Device Density 2Gbit\n")); ++ addrCtrl |= SDRAM_DSIZE_2Gb(2) | SDRAM_DSIZE_2Gb(3); ++ break; ++ default: ++ mvOsOutput("DIMM2: Dram: sdramAddrCtrl unsupported RAM-Device size %d\n", ++ pBankInfoDIMM1->deviceDensity); ++ return -1; ++ } ++ } ++ /* SDRAM address control */ ++ DB(mvOsPrintf("Dram: setting sdram address control with: %x \n", addrCtrl)); ++ ++ return addrCtrl; ++} ++ ++/******************************************************************************* ++* sdramTimeCtrlLowRegCalc - Calculate sdram timing control low register ++* ++* DESCRIPTION: ++* This function calculates sdram timing control low register ++* optimized value based on the bank info parameters and the minCas. ++* ++* INPUT: ++* pBankInfo - sdram bank parameters ++* minCas - minimum CAS supported. ++* busClk - Bus clock ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram timing control low reg value. ++* ++*******************************************************************************/ ++static MV_U32 sdramTimeCtrlLowRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 minCas, MV_U32 busClk) ++{ ++ MV_U32 tRp = 0; ++ MV_U32 tRrd = 0; ++ MV_U32 tRcd = 0; ++ MV_U32 tRas = 0; ++ MV_U32 tWr = 0; ++ MV_U32 tWtr = 0; ++ MV_U32 tRtp = 0; ++ MV_U32 timeCtrlLow = 0; ++ ++ MV_U32 bankNum; ++ ++ busClk = busClk / 1000000; /* In MHz */ ++ ++ /* Scan all DRAM banks to find maximum timing values */ ++ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) ++ { ++ tRp = MV_MAX(tRp, pBankInfo[bankNum].minRowPrechargeTime); ++ tRrd = MV_MAX(tRrd, pBankInfo[bankNum].minRowActiveToRowActive); ++ tRcd = MV_MAX(tRcd, pBankInfo[bankNum].minRasToCasDelay); ++ tRas = MV_MAX(tRas, pBankInfo[bankNum].minRasPulseWidth); ++ } ++ ++ /* Extract timing (in ns) from SPD value. We ignore the tenth ns part. */ ++ /* by shifting the data two bits right. */ ++ tRp = tRp >> 2; /* For example 0x50 -> 20ns */ ++ tRrd = tRrd >> 2; ++ tRcd = tRcd >> 2; ++ ++ /* Extract clock cycles from time parameter. We need to round up */ ++ tRp = ((busClk * tRp) / 1000) + (((busClk * tRp) % 1000) ? 1 : 0); ++ DB(mvOsPrintf("Dram Timing Low: tRp = %d ", tRp)); ++ tRrd = ((busClk * tRrd) / 1000) + (((busClk * tRrd) % 1000) ? 1 : 0); ++ /* JEDEC min reqeirments tRrd = 2 */ ++ if (tRrd < 2) ++ tRrd = 2; ++ DB(mvOsPrintf("tRrd = %d ", tRrd)); ++ tRcd = ((busClk * tRcd) / 1000) + (((busClk * tRcd) % 1000) ? 1 : 0); ++ DB(mvOsPrintf("tRcd = %d ", tRcd)); ++ tRas = ((busClk * tRas) / 1000) + (((busClk * tRas) % 1000) ? 1 : 0); ++ DB(mvOsPrintf("tRas = %d ", tRas)); ++ ++ /* tWr and tWtr is different for DDR1 and DDR2. tRtp is only for DDR2 */ ++ /* Scan all DRAM banks to find maximum timing values */ ++ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) ++ { ++ tWr = MV_MAX(tWr, pBankInfo[bankNum].minWriteRecoveryTime); ++ tWtr = MV_MAX(tWtr, pBankInfo[bankNum].minWriteToReadCmdDelay); ++ tRtp = MV_MAX(tRtp, pBankInfo[bankNum].minReadToPrechCmdDelay); ++ } ++ ++ /* Extract timing (in ns) from SPD value. We ignore the tenth ns */ ++ /* part by shifting the data two bits right. */ ++ tWr = tWr >> 2; /* For example 0x50 -> 20ns */ ++ tWtr = tWtr >> 2; ++ tRtp = tRtp >> 2; ++ /* Extract clock cycles from time parameter. We need to round up */ ++ tWr = ((busClk * tWr) / 1000) + (((busClk * tWr) % 1000) ? 1 : 0); ++ DB(mvOsPrintf("tWr = %d ", tWr)); ++ tWtr = ((busClk * tWtr) / 1000) + (((busClk * tWtr) % 1000) ? 1 : 0); ++ /* JEDEC min reqeirments tWtr = 2 */ ++ if (tWtr < 2) ++ tWtr = 2; ++ DB(mvOsPrintf("tWtr = %d ", tWtr)); ++ tRtp = ((busClk * tRtp) / 1000) + (((busClk * tRtp) % 1000) ? 1 : 0); ++ /* JEDEC min reqeirments tRtp = 2 */ ++ if (tRtp < 2) ++ tRtp = 2; ++ DB(mvOsPrintf("tRtp = %d ", tRtp)); ++ ++ /* Note: value of 0 in register means one cycle, 1 means two and so on */ ++ timeCtrlLow = (((tRp - 1) << SDRAM_TRP_OFFS) | ++ ((tRrd - 1) << SDRAM_TRRD_OFFS) | ++ ((tRcd - 1) << SDRAM_TRCD_OFFS) | ++ (((tRas - 1) << SDRAM_TRAS_OFFS) & SDRAM_TRAS_MASK)| ++ ((tWr - 1) << SDRAM_TWR_OFFS) | ++ ((tWtr - 1) << SDRAM_TWTR_OFFS) | ++ ((tRtp - 1) << SDRAM_TRTP_OFFS)); ++ ++ /* Check extended tRas bit */ ++ if ((tRas - 1) & BIT4) ++ timeCtrlLow |= (1 << SDRAM_EXT_TRAS_OFFS); ++ ++ return timeCtrlLow; ++} ++ ++/******************************************************************************* ++* sdramTimeCtrlHighRegCalc - Calculate sdram timing control high register ++* ++* DESCRIPTION: ++* This function calculates sdram timing control high register ++* optimized value based on the bank info parameters and the bus clock. ++* ++* INPUT: ++* pBankInfo - sdram bank parameters ++* busClk - Bus clock ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* sdram timing control high reg value. ++* ++*******************************************************************************/ ++static MV_U32 sdramTimeCtrlHighRegCalc(MV_DRAM_BANK_INFO *pBankInfo, MV_U32 busClk) ++{ ++ MV_U32 tRfc; ++ MV_U32 timingHigh; ++ MV_U32 timeNs = 0; ++ MV_U32 bankNum; ++ ++ busClk = busClk / 1000000; /* In MHz */ ++ ++ /* Set DDR timing high register static configuration bits */ ++ timingHigh = MV_REG_READ(SDRAM_TIMING_CTRL_HIGH_REG); ++ ++ /* Set DDR timing high register default value */ ++ timingHigh |= SDRAM_TIMING_CTRL_HIGH_REG_DV; ++ ++ /* Clear tRfc field */ ++ timingHigh &= ~SDRAM_TRFC_MASK; ++ ++ /* Scan all DRAM banks to find maximum timing values */ ++ for (bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) ++ { ++ timeNs = MV_MAX(timeNs, pBankInfo[bankNum].minRefreshToActiveCmd); ++ DB(mvOsPrintf("Dram: Timing High: minRefreshToActiveCmd = %d\n", ++ pBankInfo[bankNum].minRefreshToActiveCmd)); ++ } ++ if(busClk >= 333 && mvCtrlModelGet() == MV_78XX0_A1_REV) ++ { ++ timingHigh |= 0x1 << SDRAM_TR2W_W2R_OFFS; ++ } ++ ++ tRfc = ((busClk * timeNs) / 1000) + (((busClk * timeNs) % 1000) ? 1 : 0); ++ /* Note: value of 0 in register means one cycle, 1 means two and so on */ ++ DB(mvOsPrintf("Dram: Timing High: tRfc = %d\n", tRfc)); ++ timingHigh |= (((tRfc - 1) & SDRAM_TRFC_MASK) << SDRAM_TRFC_OFFS); ++ DB(mvOsPrintf("Dram: Timing High: tRfc = %d\n", tRfc)); ++ ++ /* SDRAM timing high */ ++ DB(mvOsPrintf("Dram: setting timing high with: %x \n", timingHigh)); ++ ++ return timingHigh; ++} ++/******************************************************************************* ++* sdramDDr2OdtConfig - Set DRAM DDR2 On Die Termination registers. ++* ++* DESCRIPTION: ++* This function config DDR2 On Die Termination (ODT) registers. ++* ++* INPUT: ++* pBankInfo - bank info parameters. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* None ++*******************************************************************************/ ++static void sdramDDr2OdtConfig(MV_DRAM_BANK_INFO *pBankInfo) ++{ ++ MV_U32 populateBanks = 0; ++ MV_U32 odtCtrlLow, odtCtrlHigh, dunitOdtCtrl; ++ int bankNum; ++ ++ /* Represent the populate banks in binary form */ ++ for(bankNum = 0; bankNum < MV_DRAM_MAX_CS; bankNum++) ++ { ++ if (0 != pBankInfo[bankNum].size) ++ { ++ populateBanks |= (1 << bankNum); ++ } ++ } ++ ++ switch(populateBanks) ++ { ++ case(BANK_PRESENT_CS0): ++ case(BANK_PRESENT_CS0_CS1): ++ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS1_DV; ++ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS1_DV; ++ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV; ++ break; ++ case(BANK_PRESENT_CS0_CS2): ++ case(BANK_PRESENT_CS0_CS1_CS2): ++ case(BANK_PRESENT_CS0_CS2_CS3): ++ case(BANK_PRESENT_CS0_CS2_CS3_CS4): ++ odtCtrlLow = DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV; ++ odtCtrlHigh = DDR2_ODT_CTRL_HIGH_CS0_CS1_CS2_CS3_DV; ++ dunitOdtCtrl = DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV; ++ break; ++ default: ++ DB(mvOsPrintf("sdramDDr2OdtConfig: Invalid DRAM bank presence\n")); ++ return; ++ } ++ /* DDR2 SDRAM ODT ctrl low */ ++ DB(mvOsPrintf("Dram: DDR2 setting ODT ctrl low with: %x \n", odtCtrlLow)); ++ MV_REG_WRITE(DRAM_BUF_REG7, odtCtrlLow); ++ ++ /* DDR2 SDRAM ODT ctrl high */ ++ DB(mvOsPrintf("Dram: DDR2 setting ODT ctrl high with: %x \n", odtCtrlHigh)); ++ MV_REG_WRITE(DRAM_BUF_REG8, odtCtrlHigh); ++ ++ /* DDR2 DUNIT ODT ctrl */ ++ if ( ((mvCtrlModelGet() == MV_78XX0_DEV_ID) && (mvCtrlRevGet() == MV_78XX0_Y0_REV)) || ++ (mvCtrlModelGet() == MV_76100_DEV_ID) || ++ (mvCtrlModelGet() == MV_78100_DEV_ID) || ++ (mvCtrlModelGet() == MV_78200_DEV_ID) ) ++ dunitOdtCtrl &= ~(BIT9|BIT8); /* Clear ODT always on */ ++ ++ DB(mvOsPrintf("DUNIT: DDR2 setting ODT ctrl with: %x \n", dunitOdtCtrl)); ++ MV_REG_WRITE(DRAM_BUF_REG9, dunitOdtCtrl); ++ return; ++} ++/******************************************************************************* ++* sdramDdr2TimeLoRegCalc - Set DDR2 DRAM Timing Low registers. ++* ++* DESCRIPTION: ++* This function config DDR2 DRAM Timing low registers. ++* ++* INPUT: ++* minCas - minimum CAS supported. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* DDR2 sdram timing low reg value. ++*******************************************************************************/ ++static MV_U32 sdramDdr2TimeLoRegCalc(MV_U32 minCas) ++{ ++ MV_U8 cl = -1; ++ MV_U32 ddr2TimeLoReg; ++ ++ /* read and clear the feilds we are going to set */ ++ ddr2TimeLoReg = MV_REG_READ(SDRAM_DDR2_TIMING_LO_REG); ++ ddr2TimeLoReg &= ~(SD2TLR_TODT_ON_RD_MASK | ++ SD2TLR_TODT_OFF_RD_MASK | ++ SD2TLR_TODT_ON_CTRL_RD_MASK | ++ SD2TLR_TODT_OFF_CTRL_RD_MASK); ++ ++ if( minCas == DDR2_CL_3 ) ++ { ++ cl = 3; ++ } ++ else if( minCas == DDR2_CL_4 ) ++ { ++ cl = 4; ++ } ++ else if( minCas == DDR2_CL_5 ) ++ { ++ cl = 5; ++ } ++ else if( minCas == DDR2_CL_6 ) ++ { ++ cl = 6; ++ } ++ else ++ { ++ DB(mvOsPrintf("sdramDdr2TimeLoRegCalc: CAS latency %d unsupported. using CAS latency 4\n", ++ minCas)); ++ cl = 4; ++ } ++ ++ ddr2TimeLoReg |= ((cl-3) << SD2TLR_TODT_ON_RD_OFFS); ++ ddr2TimeLoReg |= ( cl << SD2TLR_TODT_OFF_RD_OFFS); ++ ddr2TimeLoReg |= ( cl << SD2TLR_TODT_ON_CTRL_RD_OFFS); ++ ddr2TimeLoReg |= ((cl+3) << SD2TLR_TODT_OFF_CTRL_RD_OFFS); ++ ++ /* DDR2 SDRAM timing low */ ++ DB(mvOsPrintf("Dram: DDR2 setting timing low with: %x \n", ddr2TimeLoReg)); ++ ++ return ddr2TimeLoReg; ++} ++ ++/******************************************************************************* ++* sdramDdr2TimeHiRegCalc - Set DDR2 DRAM Timing High registers. ++* ++* DESCRIPTION: ++* This function config DDR2 DRAM Timing high registers. ++* ++* INPUT: ++* minCas - minimum CAS supported. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* DDR2 sdram timing high reg value. ++*******************************************************************************/ ++static MV_U32 sdramDdr2TimeHiRegCalc(MV_U32 minCas) ++{ ++ MV_U8 cl = -1; ++ MV_U32 ddr2TimeHiReg; ++ ++ /* read and clear the feilds we are going to set */ ++ ddr2TimeHiReg = MV_REG_READ(SDRAM_DDR2_TIMING_HI_REG); ++ ddr2TimeHiReg &= ~(SD2THR_TODT_ON_WR_MASK | ++ SD2THR_TODT_OFF_WR_MASK | ++ SD2THR_TODT_ON_CTRL_WR_MASK | ++ SD2THR_TODT_OFF_CTRL_WR_MASK); ++ ++ if( minCas == DDR2_CL_3 ) ++ { ++ cl = 3; ++ } ++ else if( minCas == DDR2_CL_4 ) ++ { ++ cl = 4; ++ } ++ else if( minCas == DDR2_CL_5 ) ++ { ++ cl = 5; ++ } ++ else if( minCas == DDR2_CL_6 ) ++ { ++ cl = 6; ++ } ++ else ++ { ++ mvOsOutput("sdramDdr2TimeHiRegCalc: CAS latency %d unsupported. using CAS latency 4\n", ++ minCas); ++ cl = 4; ++ } ++ ++ ddr2TimeHiReg |= ((cl-3) << SD2THR_TODT_ON_WR_OFFS); ++ ddr2TimeHiReg |= ( cl << SD2THR_TODT_OFF_WR_OFFS); ++ ddr2TimeHiReg |= ( cl << SD2THR_TODT_ON_CTRL_WR_OFFS); ++ ddr2TimeHiReg |= ((cl+3) << SD2THR_TODT_OFF_CTRL_WR_OFFS); ++ ++ /* DDR2 SDRAM timin high */ ++ DB(mvOsPrintf("Dram: DDR2 setting timing high with: %x \n", ddr2TimeHiReg)); ++ ++ return ddr2TimeHiReg; ++} ++#endif ++ ++/******************************************************************************* ++* mvDramIfCalGet - Get CAS Latency ++* ++* DESCRIPTION: ++* This function get the CAS Latency. ++* ++* INPUT: ++* None ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* CAS latency times 10 (to avoid using floating point). ++* ++*******************************************************************************/ ++MV_U32 mvDramIfCalGet(void) ++{ ++ MV_U32 sdramCasLat, casLatMask; ++ ++ casLatMask = (MV_REG_READ(SDRAM_MODE_REG) & SDRAM_CL_MASK); ++ ++ switch (casLatMask) ++ { ++ case SDRAM_DDR2_CL_3: ++ sdramCasLat = 30; ++ break; ++ case SDRAM_DDR2_CL_4: ++ sdramCasLat = 40; ++ break; ++ case SDRAM_DDR2_CL_5: ++ sdramCasLat = 50; ++ break; ++ case SDRAM_DDR2_CL_6: ++ sdramCasLat = 60; ++ break; ++ default: ++ mvOsOutput("mvDramIfCalGet: Err, unknown DDR2 CAL\n"); ++ return -1; ++ } ++ ++ return sdramCasLat; ++} ++ ++ ++/******************************************************************************* ++* mvDramIfSelfRefreshSet - Put the dram in self refresh mode - ++* ++* DESCRIPTION: ++* add support in power management. ++* ++* ++* INPUT: ++* None ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* None ++* ++*******************************************************************************/ ++ ++MV_VOID mvDramIfSelfRefreshSet() ++{ ++ MV_U32 operReg; ++ ++ operReg = MV_REG_READ(SDRAM_OPERATION_REG); ++ MV_REG_WRITE(SDRAM_OPERATION_REG ,operReg |SDRAM_CMD_SLF_RFRSH); ++ /* Read until register is reset to 0 */ ++ while(MV_REG_READ(SDRAM_OPERATION_REG)); ++} ++/******************************************************************************* ++* mvDramIfDimGetSPDversion - return DIMM SPD version. ++* ++* DESCRIPTION: ++* This function prints the DRAM controller information. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++static void mvDramIfDimGetSPDversion(MV_U32 *pMajor, MV_U32 *pMinor, MV_U32 bankNum) ++{ ++ MV_DIMM_INFO dimmInfo; ++ if (bankNum >= MV_DRAM_MAX_CS ) ++ { ++ DB(mvOsPrintf("Dram: mvDramIfDimGetSPDversion bad params \n")); ++ return ; ++ } ++ memset(&dimmInfo,0,sizeof(dimmInfo)); ++ if ( MV_OK != dimmSpdGet((MV_U32)(bankNum/2), &dimmInfo)) ++ { ++ DB(mvOsPrintf("Dram: ERR dimmSpdGet failed to get dimm info \n")); ++ return ; ++ } ++ *pMajor = dimmInfo.spdRawData[DIMM_SPD_VERSION]/10; ++ *pMinor = dimmInfo.spdRawData[DIMM_SPD_VERSION]%10; ++} ++/******************************************************************************* ++* mvDramIfShow - Show DRAM controller information. ++* ++* DESCRIPTION: ++* This function prints the DRAM controller information. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++void mvDramIfShow(void) ++{ ++ int i, sdramCasLat, sdramCsSize; ++ MV_U32 Major=0, Minor=0; ++ ++ mvOsOutput("DRAM Controller info:\n"); ++ ++ mvOsOutput("Total DRAM "); ++ mvSizePrint(mvDramIfSizeGet()); ++ mvOsOutput("\n"); ++ ++ for(i = 0; i < MV_DRAM_MAX_CS; i++) ++ { ++ sdramCsSize = mvDramIfBankSizeGet(i); ++ if (sdramCsSize) ++ { ++ if (0 == (i & 1)) ++ { ++ mvDramIfDimGetSPDversion(&Major, &Minor,i); ++ mvOsOutput("DIMM %d version %d.%d\n", i/2, Major, Minor); ++ } ++ mvOsOutput("\tDRAM CS[%d] ", i); ++ mvSizePrint(sdramCsSize); ++ mvOsOutput("\n"); ++ } ++ } ++ sdramCasLat = mvDramIfCalGet(); ++ ++ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_ECC_EN) ++ { ++ mvOsOutput("ECC enabled, "); ++ } ++ else ++ { ++ mvOsOutput("ECC Disabled, "); ++ } ++ ++ if (MV_REG_READ(SDRAM_CONFIG_REG) & SDRAM_REGISTERED) ++ { ++ mvOsOutput("Registered DIMM\n"); ++ } ++ else ++ { ++ mvOsOutput("Non registered DIMM\n"); ++ } ++ ++ mvOsOutput("Configured CAS Latency %d.%d\n", sdramCasLat/10, sdramCasLat%10); ++} ++/******************************************************************************* ++* mvDramIfGetFirstCS - find the DRAM bank on the lower address ++* ++* ++* DESCRIPTION: ++* This function return the fisrt CS on address 0 ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* SDRAM_CS0 or SDRAM_CS2 ++* ++*******************************************************************************/ ++MV_U32 mvDramIfGetFirstCS(void) ++{ ++ MV_DRAM_BANK_INFO bankInfo[MV_DRAM_MAX_CS]; ++ ++ if (DRAM_CS_Order[0] == N_A) ++ { ++ mvDramBankInfoGet(SDRAM_CS0, &bankInfo[SDRAM_CS0]); ++#ifdef MV_INCLUDE_SDRAM_CS2 ++ mvDramBankInfoGet(SDRAM_CS2, &bankInfo[SDRAM_CS2]); ++#endif ++ ++#ifdef MV_INCLUDE_SDRAM_CS2 ++ if (bankInfo[SDRAM_CS0].size < bankInfo[SDRAM_CS2].size) ++ { ++ DRAM_CS_Order[0] = SDRAM_CS2; ++ DRAM_CS_Order[1] = SDRAM_CS3; ++ DRAM_CS_Order[2] = SDRAM_CS0; ++ DRAM_CS_Order[3] = SDRAM_CS1; ++ ++ return SDRAM_CS2; ++ } ++#endif ++ DRAM_CS_Order[0] = SDRAM_CS0; ++ DRAM_CS_Order[1] = SDRAM_CS1; ++#ifdef MV_INCLUDE_SDRAM_CS2 ++ DRAM_CS_Order[2] = SDRAM_CS2; ++ DRAM_CS_Order[3] = SDRAM_CS3; ++#endif ++ return SDRAM_CS0; ++ } ++ return DRAM_CS_Order[0]; ++} ++/******************************************************************************* ++* mvDramIfGetCSorder - ++* ++* ++* DESCRIPTION: ++* This function return the fisrt CS on address 0 ++* ++* INPUT: ++* CS number. ++* ++* OUTPUT: ++* CS order. ++* ++* RETURN: ++* SDRAM_CS0 or SDRAM_CS2 ++* ++* NOTE: mvDramIfGetFirstCS must be caled before this subroutine ++*******************************************************************************/ ++MV_U32 mvDramIfGetCSorder(MV_U32 csOrder ) ++{ ++ return DRAM_CS_Order[csOrder]; ++} ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIf.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,172 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvDramIfh ++#define __INCmvDramIfh ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++/* includes */ ++#include "ddr2/mvDramIfRegs.h" ++#include "ddr2/mvDramIfConfig.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++ ++/* defines */ ++/* DRAM Timing parameters */ ++#define SDRAM_TWR 15 /* ns tWr */ ++#define SDRAM_TRFC_64_512M_AT_200MHZ 70 /* ns tRfc for dens 64-512 @ 200MHz */ ++#define SDRAM_TRFC_64_512M 75 /* ns tRfc for dens 64-512 */ ++#define SDRAM_TRFC_1G 120 /* ns tRfc for dens 1GB */ ++#define SDRAM_TR2R_CYC 1 /* cycle for tR2r */ ++ ++#define CAL_AUTO_DETECT 0 /* Do not force CAS latancy (mvDramIfDetect) */ ++#define ECC_DISABLE 1 /* Force ECC to Disable */ ++#define ECC_ENABLE 0 /* Force ECC to ENABLE */ ++/* typedefs */ ++ ++/* enumeration for memory types */ ++typedef enum _mvMemoryType ++{ ++ MEM_TYPE_SDRAM, ++ MEM_TYPE_DDR1, ++ MEM_TYPE_DDR2 ++}MV_MEMORY_TYPE; ++ ++/* enumeration for DDR2 supported CAS Latencies */ ++typedef enum _mvDimmDdr2Cas ++{ ++ DDR2_CL_3 = 0x08, ++ DDR2_CL_4 = 0x10, ++ DDR2_CL_5 = 0x20, ++ DDR2_CL_6 = 0x40, ++ DDR2_CL_FAULT ++} MV_DIMM_DDR2_CAS; ++ ++ ++typedef struct _mvDramBankInfo ++{ ++ MV_MEMORY_TYPE memoryType; /* DDR1, DDR2 or SDRAM */ ++ ++ /* DIMM dimensions */ ++ MV_U32 numOfRowAddr; ++ MV_U32 numOfColAddr; ++ MV_U32 dataWidth; ++ MV_U32 errorCheckType; /* ECC , PARITY..*/ ++ MV_U32 sdramWidth; /* 4,8,16 or 32 */ ++ MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ ++ MV_U32 burstLengthSupported; ++ MV_U32 numOfBanksOnEachDevice; ++ MV_U32 suportedCasLatencies; ++ MV_U32 refreshInterval; ++ ++ /* DIMM timing parameters */ ++ MV_U32 minCycleTimeAtMaxCasLatPs; ++ MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; ++ MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; ++ MV_U32 minRowPrechargeTime; ++ MV_U32 minRowActiveToRowActive; ++ MV_U32 minRasToCasDelay; ++ MV_U32 minRasPulseWidth; ++ MV_U32 minWriteRecoveryTime; /* DDR2 only */ ++ MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ ++ MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ ++ MV_U32 minRefreshToActiveCmd; /* DDR2 only */ ++ ++ /* Parameters calculated from the extracted DIMM information */ ++ MV_U32 size; ++ MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit */ ++ MV_U32 numberOfDevices; ++ ++ /* DIMM attributes (MV_TRUE for yes) */ ++ MV_BOOL registeredAddrAndControlInputs; ++ MV_BOOL registeredDQMBinputs; ++ ++}MV_DRAM_BANK_INFO; ++ ++#include "ddr2/spd/mvSpd.h" ++ ++/* mvDramIf.h API list */ ++MV_VOID mvDramIfBasicAsmInit(MV_VOID); ++MV_STATUS mvDramIfDetect(MV_U32 forcedCl, MV_BOOL eccDisable); ++MV_VOID _mvDramIfConfig(int entryNum); ++ ++MV_U32 mvDramIfBankSizeGet(MV_U32 bankNum); ++MV_U32 mvDramIfBankBaseGet(MV_U32 bankNum); ++MV_U32 mvDramIfSizeGet(MV_VOID); ++MV_U32 mvDramIfCalGet(void); ++MV_STATUS mvDramIfSingleBitErrThresholdSet(MV_U32 threshold); ++MV_VOID mvDramIfSelfRefreshSet(void); ++void mvDramIfShow(void); ++MV_U32 mvDramIfGetFirstCS(void); ++MV_U32 mvDramIfGetCSorder(MV_U32 csOrder ); ++MV_U32 mvDramCsSizeGet(MV_U32 csNum); ++ ++#ifdef __cplusplus ++} ++#endif /* __cplusplus */ ++ ++#endif /* __INCmvDramIfh */ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfBasicInit.S linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfBasicInit.S +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfBasicInit.S 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfBasicInit.S 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,986 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#define _ASMLANGUAGE ++#define MV_ASMLANGUAGE ++#include "mvSysHwConfig.h" ++#include "mvOsAsm.h" ++#include "boardEnv/mvBoardEnvSpec.h" ++#include "ctrlEnv/sys/mvCpuIfRegs.h" ++#include "mvDramIfConfig.h" ++#include "mvDramIfRegs.h" ++#include "pex/mvPexRegs.h" ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++#include "ctrlEnv/mvCtrlEnvAsm.h" ++#include "mvCommon.h" ++ ++/* defines */ ++ ++#if defined(MV_STATIC_DRAM_ON_BOARD) ++.globl dramBoot1 ++dramBoot1: ++ .word 0 ++ ++/****************************************************************************** ++* ++* ++* ++* ++*******************************************************************************/ ++#if defined(DB_MV78XX0) || defined(DB_MV88F632X) ++/* DDR2 boards 512MB 333MHz */ ++#define STATIC_SDRAM0_BANK0_SIZE 0x1ffffff1 /* 0x1504 */ ++#define STATIC_SDRAM_CONFIG 0x43048C30 /* 0x1400 */ ++#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */ ++#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */ ++#define STATIC_DUNIT_CTRL_HI 0x0000FFFF /* 0x1424 */ ++#define STATIC_SDRAM_ADDR_CTRL 0x00000088 /* 0x1410 */ ++#define STATIC_SDRAM_TIME_CTRL_LOW 0x22125441 /* 0x1408 */ ++#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A29 /* 0x140c */ ++#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */ ++#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ ++#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000E80F /* 0x149c */ ++#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */ ++#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ ++#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ ++ ++#elif defined(RD_MV78XX0_AMC) ++/* On board DDR2 512MB 400MHz CL5 */ ++#define STATIC_SDRAM0_BANK0_SIZE 0x1ffffff1 /* 0x1504 */ ++#define STATIC_SDRAM_CONFIG 0x43008C30 /* 0x1400 */ ++#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */ ++#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */ ++#define STATIC_DUNIT_CTRL_HI 0x0000F07F /* 0x1424 */ ++#define STATIC_SDRAM_ADDR_CTRL 0x000000DD /* 0x1410 */ ++#define STATIC_SDRAM_TIME_CTRL_LOW 0x23135441 /* 0x1408 */ ++#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A32 /* 0x140c */ ++#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */ ++#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ ++#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000EB0F /* 0x149c */ ++#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */ ++#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ ++#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ ++ ++#elif defined(RD_MV78XX0_H3C) ++/* DDR2 boards 512MB 333MHz */ ++#define STATIC_SDRAM0_BANK0_SIZE 0x1ffffff1 /* 0x1504 */ ++#define STATIC_SDRAM_CONFIG 0x43048a25 /* 0x1400 */ ++#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */ ++#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */ ++#define STATIC_DUNIT_CTRL_HI 0x0000F07F /* 0x1424 */ ++#define STATIC_SDRAM_ADDR_CTRL 0x00000088 /* 0x1410 */ ++#define STATIC_SDRAM_TIME_CTRL_LOW 0x2202444e /* 0x1408 */ ++#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A22 /* 0x140c */ ++#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */ ++#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ ++#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000EB0F /* 0x149c */ ++#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */ ++#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ ++#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ ++ ++#elif defined(RD_MV78XX0_PCAC) ++/* DDR2 boards 256MB 200MHz */ ++#define STATIC_SDRAM0_BANK0_SIZE 0x0ffffff1 /* 0x1504 */ ++#define STATIC_SDRAM_CONFIG 0x43000a25 /* 0x1400 */ ++#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */ ++#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */ ++#define STATIC_DUNIT_CTRL_HI 0x0000F07F /* 0x1424 */ ++#define STATIC_SDRAM_ADDR_CTRL 0x000000DD /* 0x1410 */ ++#define STATIC_SDRAM_TIME_CTRL_LOW 0x2202444e /* 0x1408 */ ++#define STATIC_SDRAM_TIME_CTRL_HI 0x00000822 /* 0x140c */ ++#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */ ++#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ ++#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000EB0F /* 0x149c */ ++#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */ ++#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ ++#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ ++ ++#else ++/* DDR2 MV88F6281 boards 256MB 400MHz */ ++#define STATIC_SDRAM0_BANK0_SIZE 0x0FFFFFF1 /* 0x1504 */ ++#define STATIC_SDRAM_CONFIG 0x43000c30 /* 0x1400 */ ++#define STATIC_SDRAM_MODE 0x00000C52 /* 0x141c */ ++#define STATIC_DUNIT_CTRL_LOW 0x39543000 /* 0x1404 */ ++#define STATIC_DUNIT_CTRL_HI 0x0000F1FF /* 0x1424 */ ++#define STATIC_SDRAM_ADDR_CTRL 0x000000cc /* 0x1410 */ ++#define STATIC_SDRAM_TIME_CTRL_LOW 0x22125451 /* 0x1408 */ ++#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A33 /* 0x140c */ ++#define STATIC_SDRAM_ODT_CTRL_LOW 0x003C0000 /* 0x1494 */ ++#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */ ++#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000F80F /* 0x149c */ ++#define STATIC_SDRAM_EXT_MODE 0x00000042 /* 0x1420 */ ++#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */ ++#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */ ++#endif /* MV78XX0 */ ++ ++ .globl _mvDramIfStaticInit ++_mvDramIfStaticInit: ++ ++ mov r11, LR /* Save link register */ ++ mov r10, r2 ++ ++#ifdef MV78XX0 ++ MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) ++ orr r6, r6, #BIT4 /* Enable 2T mode */ ++ bic r6, r6, #BIT6 /* clear ctrlPos */ ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) ++#endif ++ ++ /*DDR SDRAM Initialization Control */ ++ ldr r6, =DSICR_INIT_EN ++ MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) ++2: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) ++ and r6, r6, #DSICR_INIT_EN ++ cmp r6, #0 ++ bne 2b ++ ++ /* If we boot from NAND jump to DRAM address */ ++ mov r5, #1 ++ ldr r6, =dramBoot1 ++ str r5, [r6] /* We started executing from DRAM */ ++ ++ ldr r6, dramBoot1 ++ cmp r6, #0 ++ bne 1f ++ ++ /* set all dram windows to 0 */ ++ mov r6, #0 ++ MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,0)) ++ MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,1)) ++ MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,2)) ++ MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,3)) ++ ldr r6, = STATIC_SDRAM0_BANK0_SIZE ++ MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,0)) ++ ++ ++ /* set all dram configuration in temp registers */ ++ ldr r6, = STATIC_SDRAM0_BANK0_SIZE ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG0) ++ ldr r6, = STATIC_SDRAM_CONFIG ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG1) ++ ldr r6, = STATIC_SDRAM_MODE ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG2) ++ ldr r6, = STATIC_DUNIT_CTRL_LOW ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG3) ++ ldr r6, = STATIC_SDRAM_ADDR_CTRL ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG4) ++ ldr r6, = STATIC_SDRAM_TIME_CTRL_LOW ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG5) ++ ldr r6, = STATIC_SDRAM_TIME_CTRL_HI ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG6) ++ ldr r6, = STATIC_SDRAM_ODT_CTRL_LOW ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG7) ++ ldr r6, = STATIC_SDRAM_ODT_CTRL_HI ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG8) ++ ldr r6, = STATIC_SDRAM_DUNIT_ODT_CTRL ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG9) ++ ldr r6, = STATIC_SDRAM_EXT_MODE ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG10) ++ ldr r6, = STATIC_SDRAM_DDR2_TIMING_LO ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG11) ++ ldr r6, = STATIC_SDRAM_DDR2_TIMING_HI ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG12) ++#ifndef MV_NAND_BOOT ++ ldr r6, = STATIC_DUNIT_CTRL_HI ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG13) ++#endif ++ ++ ldr sp,=0 ++ bl _mvDramIfConfig ++ ldr r0, =0 ++#ifdef MV78XX0 ++ bl _mvDramIfEccMemInit ++#endif ++1: ++ mov r2, r10 ++ mov PC, r11 /* r11 is saved link register */ ++ ++#else /* #if defined(MV_STATIC_DRAM_ON_BOARD) */ ++ ++.globl dramBoot1 ++dramBoot1: ++ .word 0 ++ ++/******************************************************************************* ++* mvDramIfBasicInit - Basic initialization of DRAM interface ++* ++* DESCRIPTION: ++* The function will initialize the DRAM for basic usage. The function ++* will use the TWSI assembly API to extract DIMM parameters according ++* to which DRAM interface will be initialized. ++* The function referes to the following DRAM parameters: ++* 1) DIMM is registered or not. ++* 2) DIMM width detection. ++* 3) DIMM density. ++* ++* INPUT: ++* r3 - required size for initial DRAM. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++* Note: ++* r4 holds I2C EEPROM address ++* r5 holds SDRAM register base address ++* r7 holds returned values ++* r8 holds SDRAM various configuration registers value. ++* r11 holds return function address. ++*******************************************************************************/ ++/* Setting the offsets of the I2C registers */ ++#define DIMM_TYPE_OFFSET 2 ++#define NUM_OF_ROWS_OFFSET 3 ++#define NUM_OF_COLS_OFFSET 4 ++#define NUM_OF_RANKS 5 ++#define DIMM_CONFIG_TYPE 11 ++#define SDRAM_WIDTH_OFFSET 13 ++#define NUM_OF_BANKS_OFFSET 17 ++#define SUPPORTED_CL_OFFSET 18 ++#define DIMM_TYPE_INFO_OFFSET 20 /* DDR2 only */ ++#define SDRAM_MODULES_ATTR_OFFSET 21 ++#define RANK_SIZE_OFFSET 31 ++ ++#define DRAM_DEV_DENSITY_128M 128 ++#define DRAM_DEV_DENSITY_256M 256 ++#define DRAM_DEV_DENSITY_512M 512 ++#define DRAM_DEV_DENSITY_1G 1024 ++#define DRAM_DEV_DENSITY_2G 2048 ++ ++#define DRAM_RANK_DENSITY_128M 0x20 ++#define DRAM_RANK_DENSITY_256M 0x40 ++#define DRAM_RANK_DENSITY_512M 0x80 ++#define DRAM_RANK_DENSITY_1G 0x1 ++#define DRAM_RANK_DENSITY_2G 0x2 ++ ++ .globl _mvDramIfBasicInit ++ .extern _i2cInit ++_mvDramIfBasicInit: ++ ++ mov r11, LR /* Save link register */ ++ ++ /* Set Dunit high control register */ ++ MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_HI_REG) ++ orr r6, r6, #BIT7 /* SDRAM__D2P_EN */ ++ orr r6, r6, #BIT8 /* SDRAM__P2D_EN */ ++#ifdef MV78XX0 ++ orr r6, r6, #BIT9 /* SDRAM__ADD_HALF_FCC_EN */ ++ orr r6, r6, #BIT10 /* SDRAM__PUP_ZERO_SKEW_EN */ ++ orr r6, r6, #BIT11 /* SDRAM__WR_MASH_DELAY_EN */ ++#endif ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_HI_REG) ++ ++#ifdef MV78XX0 ++ MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) ++ orr r6, r6, #BIT4 /* Enable 2T mode */ ++ bic r6, r6, #BIT6 /* clear ctrlPos */ ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) ++#endif ++ ++ /*DDR SDRAM Initialization Control */ ++ ldr r6, =DSICR_INIT_EN ++ MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) ++2: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG) ++ and r6, r6, #DSICR_INIT_EN ++ cmp r6, #0 ++ bne 2b ++ ++ mov r5, #1 ++ ldr r8, =dramBoot1 ++ str r5, [r8] /* We started executing from DRAM */ ++ ++ /* If we boot from NAND jump to DRAM address */ ++ ldr r8, dramBoot1 ++ cmp r8, #0 ++ movne pc, r11 ++ ++ bl _i2cInit /* Initialize TWSI master */ ++ ++ /* Check if we have more then 1 dimm */ ++ ldr r6, =0 ++ MV_REG_WRITE_ASM (r6, r1, DRAM_BUF_REG14) ++#ifdef MV78XX0 ++ bl _is_Second_Dimm_Exist ++ beq single_dimm ++ ldr r6, =1 ++ MV_REG_WRITE_ASM (r6, r1, DRAM_BUF_REG14) ++single_dimm: ++ bl _i2cInit /* Initialize TWSI master */ ++#endif ++ ++ /* Get default SDRAM Config values */ ++ MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG) ++ ++ /* Get registered/non registered info from DIMM */ ++ bl _is_Registered ++ beq nonRegistered ++ ++setRegistered: ++ orr r8, r8, #SDRAM_REGISTERED /* Set registered bit(17) */ ++nonRegistered: ++#ifdef MV78XX0 ++ /* Get ECC/non ECC info from DIMM */ ++ bl _is_Ecc ++ beq setConfigReg ++ ++setEcc: ++ orr r8, r8, #SDRAM_ECC_EN /* Set ecc bit(18) */ ++#endif ++setConfigReg: ++ MV_REG_WRITE_ASM (r8, r5, DRAM_BUF_REG1) ++ ++ /* Set maximum CL supported by DIMM */ ++ bl _get_CAL ++ ++ /* r7 is DIMM supported CAS (e.g: 3 --> 0x1C) */ ++ clz r6, r7 ++ rsb r6, r6, #31 /* r6 = the bit number of MAX CAS supported */ ++ ++casDdr2: ++ ldr r7, =0x41 /* stBurstInDel|stBurstOutDel field value */ ++ ldr r3, =0x53 /* stBurstInDel|stBurstOutDel registered value*/ ++ ldr r8, =0x32 /* Assuming MAX CL = 3 */ ++ cmp r6, #3 /* If CL = 3 break */ ++ beq casDdr2Cont ++ ++ ldr r7, =0x53 /* stBurstInDel|stBurstOutDel field value */ ++ ldr r3, =0x65 /* stBurstInDel|stBurstOutDel registered value*/ ++ ldr r8, =0x42 /* Assuming MAX CL = 4 */ ++ cmp r6, #4 /* If CL = 4 break */ ++ beq casDdr2Cont ++ ++ ldr r7, =0x65 /* stBurstInDel|stBurstOutDel field value */ ++ ldr r3, =0x77 /* stBurstInDel|stBurstOutDel registered value*/ ++ ldr r8, =0x52 /* Assuming MAX CL = 5 */ ++ cmp r6, #5 /* If CL = 5 break */ ++ beq casDdr2Cont ++ ++ ldr r7, =0x77 /* stBurstInDel|stBurstOutDel field value */ ++ ldr r3, =0x89 /* stBurstInDel|stBurstOutDel registered value*/ ++ ldr r8, =0x62 /* Assuming MAX CL = 6 */ ++ cmp r6, #6 /* If CL = 5 break */ ++ beq casDdr2Cont ++ ++ /* This is an error. return */ ++ b exit_ddrAutoConfig /* This is an error !! */ ++casDdr2Cont: ++ ++ /* Get default SDRAM Mode values */ ++ MV_REG_READ_ASM (r6, r5, SDRAM_MODE_REG) ++ bic r6, r6, #(BIT6 | BIT5 | BIT4) /* Clear CL filed */ ++ orr r6, r6, r8 ++ MV_REG_WRITE_ASM (r6, r5, DRAM_BUF_REG2) ++ ++ /* Set Dunit control register according to max CL detected */ ++ MV_REG_READ_ASM (r6, r5, DRAM_BUF_REG1) ++ tst r6, #SDRAM_REGISTERED ++ beq setDunitReg ++ mov r7, r3 ++ ++setDunitReg: ++#ifdef MV78XX0 ++ /* Set SDRAM Extended Mode register for double DIMM */ ++ /* Check DRAM frequency for more then 267MHz set ODT Rtt to 50ohm */ ++ ++ MV_REG_READ_ASM (r4, r5, CPU_RESET_SAMPLE_L_REG) ++ ldr r5, =MSAR_SYSCLCK_MASK ++ and r4, r4, r5 ++ ldr r5, =MSAR_SYSCLCK_333 ++ cmp r4, r5 ++ ble Clock333 ++ add r7, r7, #0x10 ++Clock333: ++#endif ++ ++ MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG) ++ bic r6, r6, #(0xff << 20) /* Clear SBout and SBin */ ++ orr r6, r6, #BIT4 /* Enable 2T mode */ ++ bic r6, r6, #BIT6 /* clear ctrlPos */ ++ orr r6, r6, r7, LSL #20 ++ MV_REG_WRITE_ASM (r6, r5, DRAM_BUF_REG3) ++ ++ /* Set Dunit high control register */ ++ MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_HI_REG) ++ orr r6, r6, #BIT7 /* SDRAM__D2P_EN */ ++ orr r6, r6, #BIT8 /* SDRAM__P2D_EN */ ++#ifdef MV78XX0 ++ orr r6, r6, #BIT9 /* SDRAM__ADD_HALF_FCC_EN */ ++ orr r6, r6, #BIT10 /* SDRAM__PUP_ZERO_SKEW_EN */ ++ orr r6, r6, #BIT11 /* SDRAM__WR_MASH_DELAY_EN */ ++#endif ++ MV_REG_WRITE_ASM (r6, r5, DRAM_BUF_REG13) ++ ++ /* DIMM density configuration*/ ++ /* Density = (1 << (rowNum + colNum)) * dramWidth * dramBankNum */ ++Density: ++ /* Get bank 0 and 1 density */ ++ ldr r6, =0 ++ bl _getDensity ++ ++ mov r8, r7 ++ mov r8, r8, LSR #20 /* Move density 20 bits to the right */ ++ /* For example 0x10000000 --> 0x1000 */ ++ ++ mov r3, #(SDRAM_DSIZE_256Mb(0) | SDRAM_DSIZE_256Mb(1)) ++ cmp r8, #DRAM_DEV_DENSITY_256M ++ beq get_bank_2_density ++ ++ mov r3, #(SDRAM_DSIZE_512Mb(0) | SDRAM_DSIZE_512Mb(1)) ++ cmp r8, #DRAM_DEV_DENSITY_512M ++ beq get_bank_2_density ++ ++ mov r3, #(SDRAM_DSIZE_1Gb(0) | SDRAM_DSIZE_1Gb(1)) ++ cmp r8, #DRAM_DEV_DENSITY_1G ++ beq get_bank_2_density ++ ++ mov r3, #(SDRAM_DSIZE_2Gb(0) | SDRAM_DSIZE_2Gb(1)) ++ cmp r8, #DRAM_DEV_DENSITY_2G ++ beq get_bank_2_density ++ ++ /* This is an error. return */ ++ b exit_ddrAutoConfig ++ ++get_bank_2_density: ++ /* Check for second dimm */ ++ MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14) ++ cmp r6, #1 ++ bne get_width ++ ++ /* Get bank 2 and 3 density */ ++ ldr r6, =2 ++ bl _getDensity ++ ++ mov r8, r7 ++ mov r8, r8, LSR #20 /* Move density 20 bits to the right */ ++ /* For example 0x10000000 --> 0x1000 */ ++ ++ orr r3, r3, #(SDRAM_DSIZE_256Mb(2) | SDRAM_DSIZE_256Mb(3)) ++ cmp r8, #DRAM_DEV_DENSITY_256M ++ beq get_width ++ ++ and r3, r3, #~(SDRAM_DSIZE_MASK(2) | SDRAM_DSIZE_MASK(3)) ++ orr r3, r3, #(SDRAM_DSIZE_512Mb(2) | SDRAM_DSIZE_512Mb(3)) ++ cmp r8, #DRAM_DEV_DENSITY_512M ++ beq get_width ++ ++ and r3, r3, #~(SDRAM_DSIZE_MASK(2) | SDRAM_DSIZE_MASK(3)) ++ orr r3, r3, #(SDRAM_DSIZE_1Gb(2) | SDRAM_DSIZE_1Gb(3)) ++ cmp r8, #DRAM_DEV_DENSITY_1G ++ beq get_width ++ ++ and r3, r3, #~(SDRAM_DSIZE_MASK(2) | SDRAM_DSIZE_MASK(3)) ++ orr r3, r3, #(SDRAM_DSIZE_2Gb(2) | SDRAM_DSIZE_2Gb(3)) ++ cmp r8, #DRAM_DEV_DENSITY_2G ++ beq get_width ++ ++ /* This is an error. return */ ++ b exit_ddrAutoConfig ++ ++ /* Get SDRAM width */ ++get_width: ++ /* Get bank 0 and 1 width */ ++ ldr r6, =0 ++ bl _get_width ++ ++ cmp r7, #8 /* x8 devices */ ++ beq get_bank_2_width ++ ++ orr r3, r3, #(SDRAM_ADDRSEL_X16(0) | SDRAM_ADDRSEL_X16(1)) /* x16 devices */ ++ cmp r7, #16 ++ beq get_bank_2_width ++ ++ /* This is an error. return */ ++ b exit_ddrAutoConfig ++ ++get_bank_2_width: ++ /* Check for second dimm */ ++ MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14) ++ cmp r6, #1 ++ bne densCont ++ ++ /* Get bank 2 and 3 width */ ++ ldr r6, =2 ++ bl _get_width ++ ++ cmp r7, #8 /* x8 devices */ ++ beq densCont ++ ++ orr r3, r3, #(SDRAM_ADDRSEL_X16(2) | SDRAM_ADDRSEL_X16(3)) /* x16 devices */ ++ cmp r7, #16 ++ beq densCont ++ ++ /* This is an error. return */ ++ b exit_ddrAutoConfig ++ ++densCont: ++ MV_REG_WRITE_ASM (r3, r5, DRAM_BUF_REG4) ++ ++ /* Set SDRAM timing control low register */ ++ ldr r4, =SDRAM_TIMING_CTRL_LOW_REG_DEFAULT ++ /* MV_REG_READ_ASM (r4, r5, SDRAM_TIMING_CTRL_LOW_REG) */ ++ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG5) ++ ++ /* Set SDRAM timing control high register */ ++ ldr r6, =SDRAM_TIMING_CTRL_HIGH_REG_DEFAULT ++ ++ MV_REG_READ_ASM (r4, r5, CPU_RESET_SAMPLE_L_REG) ++ ldr r5, =MSAR_SYSCLCK_MASK ++ and r4, r4, r5 ++ ldr r5, =MSAR_SYSCLCK_333 ++ cmp r4, r5 ++ blt timingHighClock333 ++ orr r6, r6, #BIT9 ++ ++timingHighClock333: ++ /* MV_REG_READ_ASM (r6, r5, SDRAM_TIMING_CTRL_HIGH_REG) */ ++ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG6) ++ ++ /* Check for second dimm */ ++ MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14) ++ cmp r6, #1 ++ bne single_dimm_odt ++ ++ /* Set SDRAM ODT control low register for double DIMM*/ ++ ldr r4, =DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV ++ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG7) ++ ++ /* Set DUNIT ODT control register for double DIMM */ ++ ldr r4, =DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV ++ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG9) ++ ++#ifdef MV78XX0 ++ /* Set SDRAM Extended Mode register for double DIMM */ ++ /* Check DRAM frequency for more then 267MHz set ODT Rtt to 50ohm */ ++ ++ MV_REG_READ_ASM (r4, r5, CPU_RESET_SAMPLE_L_REG) ++ ldr r5, =MSAR_SYSCLCK_MASK ++ and r4, r4, r5 ++ ldr r5, =MSAR_SYSCLCK_267 ++ cmp r4, r5 ++ beq slow_dram_clock_rtt ++ ldr r5, =MSAR_SYSCLCK_300 ++ cmp r4, r5 ++ beq slow_dram_clock_rtt ++ ldr r5, =MSAR_SYSCLCK_333 ++ cmp r4, r5 ++ beq fast_dram_clock_rtt ++ ldr r5, =MSAR_SYSCLCK_400 ++ cmp r4, r5 ++ beq fast_dram_clock_rtt ++ ++ b slow_dram_clock_rtt ++ ++fast_dram_clock_rtt: ++ ldr r4, =DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV ++ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG10) ++ b odt_config_end ++#endif ++slow_dram_clock_rtt: ++ ldr r4, =DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV ++ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG10) ++ b odt_config_end ++ ++single_dimm_odt: ++ /* Set SDRAM ODT control low register */ ++ ldr r4, =DDR2_ODT_CTRL_LOW_CS0_CS1_DV ++ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG7) ++ ++ /* Set DUNIT ODT control register */ ++ ldr r4, =DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV ++ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG9) ++ ++ /* Set SDRAM Extended Mode register */ ++ ldr r4, =DDR_SDRAM_EXT_MODE_CS0_CS1_DV ++ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG10) ++ ++odt_config_end: ++ /* SDRAM ODT control high register is left as default */ ++ MV_REG_READ_ASM (r4, r5, DDR2_SDRAM_ODT_CTRL_HIGH_REG) ++ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG8) ++ ++ /*Read CL and set the DDR2 registers accordingly */ ++ MV_REG_READ_ASM (r6, r5, DRAM_BUF_REG2) ++ and r6, r6, #SDRAM_CL_MASK ++ mov r4, r6 ++ orr r4, r4, r6, LSL #4 ++ orr r4, r4, r6, LSL #8 ++ orr r4, r4, r6, LSL #12 ++ mov r5, #0x30000 ++ add r4, r4, r5 ++ sub r4, r4, #0x30 ++ /* Set SDRAM Ddr2 Timing Low register */ ++ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG11) ++ ++ /* Set SDRAM Ddr2 Timing High register */ ++ mov r4, r4, LSR #4 ++ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG12) ++ ++timeParamDone: ++ /* Close all windows */ ++ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) ++ and r6, r6,#~SCSR_SIZE_MASK ++ and r6, r6,#~1 ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) ++ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,1)) ++ and r6, r6,#~SCSR_SIZE_MASK ++ and r6, r6,#~1 ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,1)) ++ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) ++ and r6, r6,#~SCSR_SIZE_MASK ++ and r6, r6,#~1 ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) ++ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,3)) ++ and r6, r6,#~SCSR_SIZE_MASK ++ and r6, r6,#~1 ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,3)) ++ ++ /* Set sdram bank 0 size and enable it */ ++ ldr r6, =0 ++ bl _mvDramIfGetDimmSizeFromSpd ++#ifdef MV78XX0 ++ /* Check DRAM width */ ++ MV_REG_READ_ASM (r4, r5, SDRAM_CONFIG_REG) ++ ldr r5, =SDRAM_DWIDTH_MASK ++ and r4, r4, r5 ++ ldr r5, =SDRAM_DWIDTH_64BIT ++ cmp r4, r5 ++ beq dram_64bit_width ++ /* Utilize only 32bit width */ ++ mov r8, r8, LSR #1 ++#else ++ /* Utilize only 16bit width */ ++ mov r8, r8, LSR #2 ++#endif ++dram_64bit_width: ++ /* Update first dimm size return value R8 */ ++ MV_REG_READ_ASM (r5, r6, SDRAM_SIZE_REG(0,0)) ++ ldr r6, =~SCSR_SIZE_MASK ++ and r5, r5, r6 ++ orr r5, r5, r8 ++ MV_REG_WRITE_ASM(r5, r8, SDRAM_SIZE_REG(0,0)) ++ ++ /* Clear bank 2 size */ ++ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) ++ and r6, r6,#~SCSR_SIZE_MASK ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) ++ ++ /* Check for second dimm */ ++ MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14) ++ cmp r6, #1 ++ bne defualt_order ++ ++ /* Set sdram bank 2 size */ ++ ldr r6, =2 ++ bl _mvDramIfGetDimmSizeFromSpd ++#ifdef MV78XX0 ++ /* Check DRAM width */ ++ MV_REG_READ_ASM (r4, r5, SDRAM_CONFIG_REG) ++ ldr r5, =SDRAM_DWIDTH_MASK ++ and r4, r4, r5 ++ ldr r5, =SDRAM_DWIDTH_64BIT ++ cmp r4, r5 ++ beq dram_64bit_width2 ++ /* Utilize only 32bit width */ ++ mov r8, r8, LSR #1 ++#else ++ /* Utilize only 16bit width */ ++ mov r8, r8, LSR #2 ++#endif ++dram_64bit_width2: ++ /* Update first dimm size return value R8 */ ++ MV_REG_READ_ASM (r5, r6, SDRAM_SIZE_REG(0,2)) ++ ldr r6, =~SCSR_SIZE_MASK ++ and r5, r5, r6 ++ orr r5, r5, r8 ++ MV_REG_WRITE_ASM(r5, r8, SDRAM_SIZE_REG(0,2)) ++ ++ /* Close windows 1 and 3 */ ++ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,1)) ++ and r6, r6,#~1 ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,1)) ++ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,3)) ++ and r6, r6,#~1 ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,3)) ++ ++ /* Check dimm size for setting dram bank order */ ++ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) ++ MV_REG_READ_ASM (r4, r5, SDRAM_SIZE_REG(0,2)) ++ and r6, r6,#SCSR_SIZE_MASK ++ and r4, r4,#SCSR_SIZE_MASK ++ cmp r6, r4 ++ bge defualt_order ++ ++ /* Bank 2 is biger then bank 0 */ ++ ldr r6,=0 ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_BASE_ADDR_REG(0,2)) ++ ++ /* Open win 2 */ ++ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) ++ orr r6, r6,#1 ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,2)) ++ ++ ldr sp,=0 ++ bl _mvDramIfConfig ++#ifdef MV78XX0 ++ /* Init ECC on CS 2 */ ++ ldr r0, =2 ++ bl _mvDramIfEccMemInit ++#endif ++ mov PC, r11 /* r11 is saved link register */ ++ ++defualt_order: ++ ++ /* Open win 0 */ ++ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) ++ orr r6, r6,#1 ++ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,0)) ++ ++ ldr sp,=0 ++ bl _mvDramIfConfig ++#ifdef MV78XX0 ++ /* Init ECC on CS 0 */ ++ ldr r0, =0 ++ bl _mvDramIfEccMemInit ++#endif ++exit_ddrAutoConfig: ++ mov PC, r11 /* r11 is saved link register */ ++ ++ ++/***************************************************************************************/ ++/* r4 holds I2C EEPROM address ++ * r7 holds I2C EEPROM offset parameter for i2cRead and its --> returned value ++ * r8 holds SDRAM various configuration registers value. ++ * r13 holds Link register ++ */ ++/**************************/ ++_getDensity: ++ mov r13, LR /* Save link register */ ++ ++ /* Read SPD rank size from DIMM0 */ ++ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ ++ ++ cmp r6, #0 ++ beq 1f ++ ++ /* Read SPD rank size from DIMM1 */ ++ mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM1 */ ++ ++1: ++ mov r7, #NUM_OF_ROWS_OFFSET /* offset 3 */ ++ bl _i2cRead ++ mov r8, r7 /* r8 save number of rows */ ++ ++ mov r7, #NUM_OF_COLS_OFFSET /* offset 4 */ ++ bl _i2cRead ++ add r8, r8, r7 /* r8 = number of rows + number of col */ ++ ++ mov r7, #0x1 ++ mov r8, r7, LSL r8 /* r8 = (1 << r8) */ ++ ++ mov r7, #SDRAM_WIDTH_OFFSET /* offset 13 */ ++ bl _i2cRead ++ mul r8, r7, r8 ++ ++ mov r7, #NUM_OF_BANKS_OFFSET /* offset 17 */ ++ bl _i2cRead ++ mul r7, r8, r7 ++ ++ mov PC, r13 ++ ++/**************************/ ++_get_width: ++ mov r13, LR /* Save link register */ ++ ++ /* Read SPD rank size from DIMM0 */ ++ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ ++ ++ cmp r6, #0 ++ beq 1f ++ ++ /* Read SPD rank size from DIMM1 */ ++ mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM1 */ ++ ++1: ++ /* Get SDRAM width (SPD offset 13) */ ++ mov r7, #SDRAM_WIDTH_OFFSET ++ bl _i2cRead /* result in r7 */ ++ ++ mov PC, r13 ++ ++/**************************/ ++_get_CAL: ++ mov r13, LR /* Save link register */ ++ ++ /* Set maximum CL supported by DIMM */ ++ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ ++ mov r7, #SUPPORTED_CL_OFFSET /* offset 18 */ ++ bl _i2cRead ++ ++ mov PC, r13 ++ ++/**************************/ ++/* R8 - sdram configuration register. ++ * Return value in flag if no-registered then Z-flag is set ++ */ ++_is_Registered: ++ mov r13, LR /* Save link register */ ++#if defined(MV645xx) ++ /* Get registered/non registered info from DIMM */ ++ tst r8, #SDRAM_DTYPE_DDR2 ++ bne regDdr2 ++ ++regDdr1: ++ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ ++ mov r7, #SDRAM_MODULES_ATTR_OFFSET ++ bl _i2cRead /* result in r7 */ ++ ++ tst r7, #0x2 ++ b exit ++#endif ++regDdr2: ++ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ ++ mov r7, #DIMM_TYPE_INFO_OFFSET ++ bl _i2cRead /* result in r7 */ ++ ++ tst r7, #0x11 /* DIMM type = regular RDIMM (0x01) */ ++ /* or Mini-RDIMM (0x10) */ ++exit: ++ mov PC, r13 ++ ++ ++/**************************/ ++/* Return value in flag if no-Ecc then Z-flag is set */ ++_is_Ecc: ++ mov r13, LR /* Save link register */ ++ ++ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ ++ mov r7, #DIMM_CONFIG_TYPE ++ bl _i2cRead /* result in r7 */ ++ ++ tst r7, #0x2 /* bit 1 -> Data ECC */ ++ mov PC, r13 ++ ++/**************************/ ++/* Return value in flag if no second DIMM then Z-flag is set */ ++_is_Second_Dimm_Exist: ++ mov r13, LR /* Save link register */ ++ ++ mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM0 */ ++ mov r7, #DIMM_TYPE_OFFSET ++ bl _i2cRead /* result in r7 */ ++ ++ tst r7, #0x8 /* bit3 is '1' -> DDR 2 */ ++ mov PC, r13 ++ ++/******************************************************************************* ++* _mvDramIfGetDimmSizeFromSpd - read bank 0 dram's size ++* ++* DESCRIPTION: ++* The function will read the bank 0 dram size(SPD version 1.0 and above ) ++* ++* INPUT: ++* r6 - dram bank number. ++* ++* OUTPUT: ++* none ++*/ ++_mvDramIfGetDimmSizeFromSpd: ++ ++ mov r13, LR /* Save link register */ ++ ++ /* Read SPD rank size from DIMM0 */ ++ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */ ++ ++ cmp r6, #0 ++ beq 1f ++ ++ /* Read SPD rank size from DIMM1 */ ++ mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM1 */ ++ ++1: ++ mov r7, #RANK_SIZE_OFFSET /* offset 31 */ ++ bl _i2cRead ++ ++pass_read: ++ ldr r8, =(0x7 << SCSR_SIZE_OFFS) ++ cmp r7, #DRAM_RANK_DENSITY_128M ++ beq endDimmSize ++ ++ ldr r8, =(0xf << SCSR_SIZE_OFFS) ++ cmp r7, #DRAM_RANK_DENSITY_256M ++ beq endDimmSize ++ ++ ldr r8, =(0x1f << SCSR_SIZE_OFFS) ++ cmp r7, #DRAM_RANK_DENSITY_512M ++ beq endDimmSize ++ ++ ldr r8, =(0x3f << SCSR_SIZE_OFFS) ++ cmp r7, #DRAM_RANK_DENSITY_1G ++ beq endDimmSize ++ ++ ldr r8, =(0x7f << SCSR_SIZE_OFFS) /* DRAM_RANK_DENSITY_2G */ ++endDimmSize: ++ mov PC, r13 ++#endif +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.S linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.S +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.S 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.S 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,528 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++/******************************************************************************* ++* mvDramIfBasicAsm.s ++* ++* DESCRIPTION: ++* Memory full detection and best timing configuration is done in ++* C code. C runtime environment requires a stack. This module API ++* initialize DRAM interface chip select 0 for basic functionality for ++* the use of stack. ++* The module API assumes DRAM information is stored in I2C EEPROM reside ++* in a given I2C address MV_BOARD_DIMM0_I2C_ADDR. The I2C EEPROM ++* internal data structure is assumed to be orgenzied in common DRAM ++* vendor SPD structure. ++* NOTE: DFCDL values are assumed to be already initialized prior to ++* this module API activity. ++* ++* ++* DEPENDENCIES: ++* None. ++* ++*******************************************************************************/ ++ ++/* includes */ ++#define _ASMLANGUAGE ++#define MV_ASMLANGUAGE ++#include "mvOsAsm.h" ++#include "mvSysHwConfig.h" ++#include "mvDramIfRegs.h" ++#include "mvDramIfConfig.h" ++#include "ctrlEnv/sys/mvCpuIfRegs.h" ++#include "pex/mvPexRegs.h" ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++#include "mvCommon.h" ++ ++/* defines */ ++ ++/* locals */ ++.data ++.globl _mvDramIfConfig ++.text ++.globl _mvDramIfMemInit ++ ++/******************************************************************************* ++* _mvDramIfConfig - Basic DRAM interface initialization. ++* ++* DESCRIPTION: ++* The function will initialize the following DRAM parameters using the ++* values prepared by mvDramIfDetect routine. Values are located ++* in predefined registers. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++ ++_mvDramIfConfig: ++ ++ /* Save register on stack */ ++ cmp sp, #0 ++ beq no_stack_s ++save_on_stack: ++ stmdb sp!, {r1, r2, r3, r4} ++no_stack_s: ++ ++ /* Dunit FTDLL Configuration Register */ ++ /* 0) Write to SDRAM FTDLL coniguration register */ ++ ldr r4, = SDRAM_FTDLL_REG_DEFAULT_LEFT; ++ ldr r1, =(INTER_REGS_BASE + SDRAM_FTDLL_CONFIG_LEFT_REG) ++ str r4, [r1] ++ ldr r4, = SDRAM_FTDLL_REG_DEFAULT_RIGHT; ++ ldr r1, =(INTER_REGS_BASE + SDRAM_FTDLL_CONFIG_RIGHT_REG) ++ str r4, [r1] ++ ldr r4, = SDRAM_FTDLL_REG_DEFAULT_UP; ++ ldr r1, =(INTER_REGS_BASE + SDRAM_FTDLL_CONFIG_UP_REG) ++ str r4, [r1] ++ ++ /* 1) Write to SDRAM coniguration register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG1) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_CONFIG_REG) ++ str r4, [r1] ++ ++ /* 2) Write Dunit control low register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG3) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_DUNIT_CTRL_REG) ++ str r4, [r1] ++ ++ /* 2) Write Dunit control high register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG13) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_DUNIT_CTRL_HI_REG) ++ str r4, [r1] ++ ++ /* 3) Write SDRAM address control register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG4) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_ADDR_CTRL_REG) ++ str r4, [r1] ++#if defined(MV_STATIC_DRAM_ON_BOARD) ++ /* 4) Write SDRAM bank 0 size register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG0) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_SIZE_REG(0,0)) ++ str r4, [r1] ++#endif ++ ++ /* 5) Write SDRAM open pages control register */ ++ ldr r1, =(INTER_REGS_BASE + SDRAM_OPEN_PAGE_CTRL_REG) ++ ldr r4, =SDRAM_OPEN_PAGES_CTRL_REG_DV ++ str r4, [r1] ++ ++ /* 6) Write SDRAM timing Low register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG5) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_LOW_REG) ++ str r4, [r1] ++ ++ /* 7) Write SDRAM timing High register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG6) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_HIGH_REG) ++ str r4, [r1] ++ ++ /* Config DDR2 On Die Termination (ODT) registers */ ++ /* Write SDRAM DDR2 ODT control low register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG7) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_LOW_REG) ++ str r4, [r1] ++ ++ /* Write SDRAM DDR2 ODT control high register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG8) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_HIGH_REG) ++ str r4, [r1] ++ ++ /* Write SDRAM DDR2 Dunit ODT control register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG9) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + DDR2_DUNIT_ODT_CONTROL_REG) ++ str r4, [r1] ++ ++ /* Write DDR2 SDRAM timing Low register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG11) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_DDR2_TIMING_LO_REG) ++ str r4, [r1] ++ ++ /* Write DDR2 SDRAM timing High register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG12) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_DDR2_TIMING_HI_REG) ++ str r4, [r1] ++ ++ /* 8) Write SDRAM mode register */ ++ /* The CPU must not attempt to change the SDRAM Mode register setting */ ++ /* prior to DRAM controller completion of the DRAM initialization */ ++ /* sequence. To guarantee this restriction, it is recommended that */ ++ /* the CPU sets the SDRAM Operation register to NOP command, performs */ ++ /* read polling until the register is back in Normal operation value, */ ++ /* and then sets SDRAM Mode register to its new value. */ ++ ++ /* 8.1 write 'nop' to SDRAM operation */ ++ mov r4, #0x5 /* 'NOP' command */ ++ MV_REG_WRITE_ASM(r4, r1, SDRAM_OPERATION_REG) ++ ++ /* 8.2 poll SDRAM operation. Make sure its back to normal operation */ ++_sdramOpPoll1: ++ ldr r4, [r1] ++ cmp r4, #0 /* '0' = Normal SDRAM Mode */ ++ bne _sdramOpPoll1 ++ ++ /* 8.3 Now its safe to write new value to SDRAM Mode register */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG2) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_MODE_REG) ++ str r4, [r1] ++ ++ /* 8.4 Make the Dunit write the DRAM its new mode */ ++ mov r4, #0x3 /* Mode Register Set command */ ++ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) ++ ++ /* 8.5 poll SDRAM operation. Make sure its back to normal operation */ ++_sdramOpPoll2: ++ ldr r4, [r1] ++ cmp r4, #0 /* '0' = Normal SDRAM Mode */ ++ bne _sdramOpPoll2 ++ ++ /* Now its safe to write new value to SDRAM Extended Mode regist */ ++ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG10) ++ ldr r4, [r1] ++ ldr r1, =(INTER_REGS_BASE + SDRAM_EXTENDED_MODE_REG) ++ str r4, [r1] ++ ++ /* 9) Write SDRAM Extended mode register This operation should be */ ++ /* done for each memory bank */ ++ /* write 'nop' to SDRAM operation */ ++ mov r4, #0x5 /* 'NOP' command */ ++ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) ++ ++ /* poll SDRAM operation. Make sure its back to normal operation */ ++_sdramOpPoll3: ++ ldr r4, [r1] ++ cmp r4, #0 /* '0' = Normal SDRAM Mode */ ++ bne _sdramOpPoll3 ++ /* Go over each of the Banks */ ++ ldr r3, =0 /* r3 = DRAM bank Num */ ++ ++extModeLoop: ++ /* Set the SDRAM Operation Control to each of the DRAM banks */ ++ mov r4, r3 /* Do not swap the bank counter value */ ++ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_CTRL_REG) ++ ++ /* Make the Dunit write the DRAM its new mode */ ++ mov r4, #0x4 /* Extended Mode Register Set command */ ++ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG) ++ ++ /* poll SDRAM operation. Make sure its back to normal operation */ ++_sdramOpPoll4: ++ ldr r4, [r1] ++ cmp r4, #0 /* '0' = Normal SDRAM Mode */ ++ bne _sdramOpPoll4 ++ ++ add r3, r3, #1 ++ cmp r3, #4 /* 4 = Number of banks */ ++ bne extModeLoop ++ ++extModeEnd: ++cmp sp, #0 ++ beq no_stack_l ++ mov r1, LR /* Save link register */ ++#if defined(MV78XX0) ++ bl _mvDramIfMemInit ++#endif ++ mov LR,r1 /* restore link register */ ++load_from_stack: ++ /* Restore registers */ ++ ldmia sp!, {r1, r2, r3, r4} ++no_stack_l: ++ ++ mov pc, lr ++ ++ ++/******************************************************************************* ++* _mvDramIfEccMemInit - Basic DRAM ECC initialization. ++* ++* DESCRIPTION: ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++#define XOR_CHAN0 0 /* XOR channel 0 used for memory initialization */ ++#define XOR_UNIT0 0 /* XOR unit 0 used for memory initialization */ ++#define XOR_ADDR_DEC_WIN0 0 /* Enable DRAM access using XOR decode window 0 */ ++/* XOR engine register offsets macros */ ++#define XOR_CONFIG_REG(chan) (XOR_UNIT_BASE(0) + 0x10 + ((chan) * 4)) ++#define XOR_ACTIVATION_REG(chan) (XOR_UNIT_BASE(0) + 0x20 + ((chan) * 4)) ++#define XOR_CAUSE_REG (XOR_UNIT_BASE(0) + 0x30) ++#define XOR_ERROR_CAUSE_REG (XOR_UNIT_BASE(0) + 0x50) ++#define XOR_ERROR_ADDR_REG (XOR_UNIT_BASE(0) + 0x60) ++#define XOR_INIT_VAL_LOW_REG (XOR_UNIT_BASE(0) + 0x2E0) ++#define XOR_INIT_VAL_HIGH_REG (XOR_UNIT_BASE(0) + 0x2E4) ++#define XOR_DST_PTR_REG(chan) (XOR_UNIT_BASE(0) + 0x2B0 + ((chan) * 4)) ++#define XOR_BLOCK_SIZE_REG(chan) (XOR_UNIT_BASE(0) + 0x2C0 + ((chan) * 4)) ++ ++/* XOR Engine Address Decoding Register Map */ ++#define XOR_WINDOW_CTRL_REG(unit,chan) (XOR_UNIT_BASE(unit)+(0x240 + ((chan) * 4))) ++#define XOR_BASE_ADDR_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x250 + ((winNum) * 4))) ++#define XOR_SIZE_MASK_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x270 + ((winNum) * 4))) ++ ++.globl _mvDramIfEccMemInit ++/******************************************************************************* ++* _mvDramIfEccMemInit - mem init for dram cs ++* ++* DESCRIPTION: ++* This function will clean the cs by ussing the XOR mem init. ++* ++* INPUT: ++* r0 - dram bank number. ++* ++* OUTPUT: ++* none ++*/ ++_mvDramIfEccMemInit: ++ ++ /* Save register on stack */ ++ cmp sp, #0 ++ beq no_stack_s1 ++save_on_stack1: ++ stmdb sp!, {r0,r1, r2, r3, r4, r5, r6} ++no_stack_s1: ++ ++ ldr r1, = 0 ++ ++ /* Disable all XOR address decode windows to avoid possible overlap */ ++ MV_REG_WRITE_ASM (r1, r5, (XOR_WINDOW_CTRL_REG(XOR_UNIT0,XOR_CHAN0))) ++ ++ /* Init r5 to first XOR_SIZE_MASK_REG */ ++ mov r5, r0, LSL #3 ++ add r5, r5,#0x1500 ++ add r5, r5,#0x04 ++ add r5, r5,#(INTER_REGS_BASE) ++ ldr r6, [r5] ++ HTOLL(r6,r5) ++ MV_REG_WRITE_ASM (r6, r5, XOR_SIZE_MASK_REG(XOR_UNIT0,XOR_ADDR_DEC_WIN0)) ++ ++ mov r5, r0, LSL #3 ++ add r5, r5,#0x1500 ++ add r5, r5,#(INTER_REGS_BASE) ++ ldr r6, [r5] ++ /* Update destination & size */ ++ MV_REG_WRITE_ASM(r6, r5, XOR_DST_PTR_REG(XOR_CHAN0)) ++ HTOLL(r6,r5) ++ /* Init r6 to first XOR_BASE_ADDR_REG */ ++ ldr r4, = 0xf ++ ldr r5, = 0x1 ++ mov r5, r5, LSL r0 ++ bic r4, r4, r5 ++ mov r4, r4, LSL #8 ++ ++ orr r6, r6, r4 ++ MV_REG_WRITE_ASM (r6, r5, XOR_BASE_ADDR_REG(XOR_UNIT0,XOR_ADDR_DEC_WIN0)) ++ ++ ldr r6, = 0xff0001 ++ MV_REG_WRITE_ASM (r6, r5, XOR_WINDOW_CTRL_REG(XOR_UNIT0,XOR_CHAN0)) ++ ++ /* Configure XOR engine for memory init function. */ ++ MV_REG_READ_ASM (r6, r5, XOR_CONFIG_REG(XOR_CHAN0)) ++ and r6, r6, #~0x7 /* Clear operation mode field */ ++ orr r6, r6, #0x4 /* Set operation to memory init */ ++ MV_REG_WRITE_ASM(r6, r5, XOR_CONFIG_REG(XOR_CHAN0)) ++ ++ /* Set initVal in the XOR Engine Initial Value Registers */ ++ ldr r6, = 0xfeedfeed ++ MV_REG_WRITE_ASM(r6, r5, XOR_INIT_VAL_LOW_REG) ++ ldr r6, = 0xfeedfeed ++ MV_REG_WRITE_ASM(r6, r5, XOR_INIT_VAL_HIGH_REG) ++ ++ /* Set block size using DRAM bank size */ ++ ++ mov r5, r0, LSL #3 ++ add r5, r5,#0x1500 ++ add r5, r5,#0x04 ++ add r5, r5,#(INTER_REGS_BASE) ++ ++ ldr r6, [r5] ++ HTOLL(r6,r5) ++ and r6, r6, #SCSR_SIZE_MASK ++ mov r5, r6, LSR #SCSR_SIZE_OFFS ++ add r5, r5, #1 ++ mov r6, r5, LSL #SCSR_SIZE_OFFS ++ MV_REG_WRITE_ASM(r6, r5, XOR_BLOCK_SIZE_REG(XOR_CHAN0)) ++ ++ /* Clean interrupt cause*/ ++ MV_REG_WRITE_ASM(r1, r5, XOR_CAUSE_REG) ++ ++ /* Clean error interrupt cause*/ ++ MV_REG_READ_ASM(r6, r5, XOR_ERROR_CAUSE_REG) ++ MV_REG_READ_ASM(r6, r5, XOR_ERROR_ADDR_REG) ++ ++ /* Start transfer */ ++ MV_REG_READ_ASM (r6, r5, XOR_ACTIVATION_REG(XOR_CHAN0)) ++ orr r6, r6, #0x1 /* Preform start command */ ++ MV_REG_WRITE_ASM(r6, r5, XOR_ACTIVATION_REG(XOR_CHAN0)) ++ ++ /* Wait for engine to finish */ ++waitForComplete: ++ MV_REG_READ_ASM(r6, r5, XOR_CAUSE_REG) ++ and r6, r6, #2 ++ cmp r6, #0 ++ beq waitForComplete ++ ++ /* Clear all error report registers */ ++ MV_REG_WRITE_ASM(r1, r5, SDRAM_SINGLE_BIT_ERR_CNTR_REG) ++ MV_REG_WRITE_ASM(r1, r5, SDRAM_DOUBLE_BIT_ERR_CNTR_REG) ++ ++ MV_REG_WRITE_ASM(r1, r5, SDRAM_ERROR_CAUSE_REG) ++ ++ cmp sp, #0 ++ beq no_stack_l1 ++load_from_stack1: ++ ldmia sp!, {r0, r1, r2, r3, r4, r5, r6} ++no_stack_l1: ++ mov pc, lr ++ ++ ++/******************************************************************************* ++* mvDramIfMemInit - Use XOR to clear all memory. ++* ++* DESCRIPTION: ++* Use assembler function _mvDramIfEccMemInit to fill all memory with FEADFEAD pattern. ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++#if defined(MV78XX0) ++ ++_mvDramIfMemInit: ++ stmdb sp!, {r0,r1, r2, r3, r4, r5, r6} ++ mov r6, LR /* Save link register */ ++ /* Check if dram bank 0 has to be init for ECC */ ++ MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,0)) ++ and r3, r0, #SCSR_WIN_EN ++ cmp r3, #0 ++ beq no_bank_0 ++ MV_REG_READ_ASM(r0, r5, SDRAM_BASE_ADDR_REG(0,0)) ++ cmp r0, #0 ++ beq no_bank_0 ++ mov r0,#0 ++ bl _mvDramIfEccMemInit ++ ++no_bank_0: ++ /* Check if dram bank 1 has to be init for ECC */ ++ MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,1)) ++ and r0, r0, #SCSR_WIN_EN ++ cmp r0, #0 ++ beq no_bank_1 ++ mov r0,#1 ++ bl _mvDramIfEccMemInit ++no_bank_1: ++ /* Check if dram bank 2 has to be init for ECC */ ++ MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,2)) ++ and r0, r0, #SCSR_WIN_EN ++ cmp r0, #0 ++ beq no_bank_2 ++ MV_REG_READ_ASM(r0, r5, SDRAM_BASE_ADDR_REG(0,2)) ++ cmp r0, #0 ++ beq no_bank_2 ++ mov r0,#2 ++ bl _mvDramIfEccMemInit ++ ++no_bank_2: ++ /* Check if dram bank 3 has to be init for ECC */ ++ MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,3)) ++ and r0, r0, #SCSR_WIN_EN ++ cmp r0, #0 ++ beq no_bank_3 ++ mov r0,#3 ++ bl _mvDramIfEccMemInit ++no_bank_3: ++ mov LR ,r6 /* restore link register */ ++ ldmia sp!, {r0, r1, r2, r3, r4, r5, r6} ++ mov pc, lr ++#endif ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfConfig.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,157 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvDramIfConfigh ++#define __INCmvDramIfConfigh ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++/* includes */ ++ ++/* defines */ ++ ++/* registers defaults values */ ++ ++#define SDRAM_CONFIG_DV (SDRAM_SRMODE_DRAM | BIT25 | BIT30) ++ ++#define SDRAM_DUNIT_CTRL_LOW_DDR2_DV \ ++ (SDRAM_SRCLK_KEPT | \ ++ SDRAM_CLK1DRV_NORMAL | \ ++ (BIT28 | BIT29)) ++ ++#define SDRAM_ADDR_CTRL_DV 2 ++ ++#define SDRAM_TIMING_CTRL_LOW_REG_DV \ ++ ((0x2 << SDRAM_TRCD_OFFS) | \ ++ (0x2 << SDRAM_TRP_OFFS) | \ ++ (0x1 << SDRAM_TWR_OFFS) | \ ++ (0x0 << SDRAM_TWTR_OFFS) | \ ++ (0x5 << SDRAM_TRAS_OFFS) | \ ++ (0x1 << SDRAM_TRRD_OFFS)) ++ ++/* Note: value of 0 in register means one cycle, 1 means two and so on */ ++#define SDRAM_TIMING_CTRL_HIGH_REG_DV \ ++ ((0x0 << SDRAM_TR2R_OFFS) | \ ++ (0x0 << SDRAM_TR2W_W2R_OFFS) | \ ++ (0x1 << SDRAM_TW2W_OFFS)) ++ ++#define SDRAM_OPEN_PAGES_CTRL_REG_DV SDRAM_OPEN_PAGE_EN ++ ++/* Presence Ctrl Low Ctrl High Dunit Ctrl Ext Mode */ ++/* CS0 0x84210000 0x00000000 0x0000780F 0x00000440 */ ++/* CS0+CS1 0x84210000 0x00000000 0x0000780F 0x00000440 */ ++/* CS0+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ ++/* CS0+CS1+CS2 0x030C030C 0x00000000 0x0000740F 0x00000404 */ ++/* CS0+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ ++/* CS0+CS1+CS2+CS3 0x030C030C 0x00000000 0x0000740F 0x00000404 */ ++ ++#define DDR2_ODT_CTRL_LOW_CS0_CS1_DV 0x84210000 ++#define DDR2_ODT_CTRL_HIGH_CS0_CS1_DV 0x00000000 ++#define DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV 0x0000E80F ++#ifdef MV78XX0 ++#define DDR_SDRAM_EXT_MODE_CS0_CS1_DV 0x00000040 ++#else ++#define DDR_SDRAM_EXT_MODE_CS0_CS1_DV 0x00000440 ++#endif ++ ++#define DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV 0x030C030C ++#define DDR2_ODT_CTRL_HIGH_CS0_CS1_CS2_CS3_DV 0x00000000 ++#define DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV 0x0000F40F ++#ifdef MV78XX0 ++#define DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV 0x00000004 ++#define DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV 0x00000044 ++#else ++#define DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV 0x00000404 ++#define DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV 0x00000444 ++#endif ++ ++/* DDR SDRAM Adderss/Control and Data Pads Calibration default values */ ++#define DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV \ ++ (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) ++ ++#define DDR2_DATA_PAD_STRENGTH_TYPICAL_DV \ ++ (3 << SDRAM_PRE_DRIVER_STRENGTH_OFFS) ++ ++/* DDR SDRAM Mode Register default value */ ++#define DDR2_MODE_REG_DV (SDRAM_BURST_LEN_4 | SDRAM_WR_3_CYC) ++/* DDR SDRAM Timing parameter default values */ ++#define SDRAM_TIMING_CTRL_LOW_REG_DEFAULT 0x33136552 ++#define SDRAM_TRFC_DEFAULT_VALUE 0x34 ++#define SDRAM_TRFC_DEFAULT SDRAM_TRFC_DEFAULT_VALUE ++#define SDRAM_TW2W_DEFALT (0x1 << SDRAM_TW2W_OFFS) ++ ++#define SDRAM_TIMING_CTRL_HIGH_REG_DEFAULT (SDRAM_TRFC_DEFAULT | SDRAM_TW2W_DEFALT) ++ ++#define SDRAM_FTDLL_REG_DEFAULT_LEFT 0x88C800 ++#define SDRAM_FTDLL_REG_DEFAULT_RIGHT 0x88C800 ++#define SDRAM_FTDLL_REG_DEFAULT_UP 0x88C800 ++ ++#ifdef __cplusplus ++} ++#endif /* __cplusplus */ ++ ++#endif /* __INCmvDramIfh */ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/mvDramIfRegs.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,423 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvDramIfRegsh ++#define __INCmvDramIfRegsh ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++/* DDR SDRAM Controller Address Decode Registers */ ++ /* SDRAM CSn Base Address Register (SCBAR) */ ++#define SDRAM_BASE_ADDR_REG(cpu,csNum) (0x1500 + ((csNum) * 8) + ((cpu) * 0x70)) ++#define SCBAR_BASE_OFFS 16 ++#define SCBAR_BASE_MASK (0xffff << SCBAR_BASE_OFFS) ++#define SCBAR_BASE_ALIGNMENT 0x10000 ++ ++/* SDRAM CSn Size Register (SCSR) */ ++#define SDRAM_SIZE_REG(cpu,csNum) (0x1504 + ((csNum) * 8) + ((cpu) * 0x70)) ++#define SCSR_SIZE_OFFS 24 ++#define SCSR_SIZE_MASK (0xff << SCSR_SIZE_OFFS) ++#define SCSR_SIZE_ALIGNMENT 0x1000000 ++#define SCSR_WIN_EN BIT0 ++ ++/* configuration register */ ++#define SDRAM_CONFIG_REG (DRAM_BASE + 0x1400) ++#define SDRAM_REFRESH_OFFS 0 ++#define SDRAM_REFRESH_MAX 0x3FFF ++#define SDRAM_REFRESH_MASK (SDRAM_REFRESH_MAX << SDRAM_REFRESH_OFFS) ++#define SDRAM_DWIDTH_OFFS 15 ++#define SDRAM_DWIDTH_MASK (1 << SDRAM_DWIDTH_OFFS) ++#define SDRAM_DWIDTH_32BIT (0 << SDRAM_DWIDTH_OFFS) ++#define SDRAM_DWIDTH_64BIT (1 << SDRAM_DWIDTH_OFFS) ++#define SDRAM_REGISTERED (1 << 17) ++#define SDRAM_ECC_OFFS 18 ++#define SDRAM_ECC_MASK (1 << SDRAM_ECC_OFFS) ++#define SDRAM_ECC_DIS (0 << SDRAM_ECC_OFFS) ++#define SDRAM_ECC_EN (1 << SDRAM_ECC_OFFS) ++#define SDRAM_IERR_OFFS 19 ++#define SDRAM_IERR_MASK (1 << SDRAM_IERR_OFFS) ++#define SDRAM_IERR_REPORTE (0 << SDRAM_IERR_OFFS) ++#define SDRAM_IERR_IGNORE (1 << SDRAM_IERR_OFFS) ++#define SDRAM_SRMODE_OFFS 24 ++#define SDRAM_SRMODE_MASK (1 << SDRAM_SRMODE_OFFS) ++#define SDRAM_SRMODE_POWER (0 << SDRAM_SRMODE_OFFS) ++#define SDRAM_SRMODE_DRAM (1 << SDRAM_SRMODE_OFFS) ++ ++/* dunit control low register */ ++#define SDRAM_DUNIT_CTRL_REG (DRAM_BASE + 0x1404) ++#define SDRAM_2T_OFFS 4 ++#define SDRAM_2T_MASK (1 << SDRAM_2T_OFFS) ++#define SDRAM_2T_MODE (1 << SDRAM_2T_OFFS) ++ ++#define SDRAM_SRCLK_OFFS 5 ++#define SDRAM_SRCLK_MASK (1 << SDRAM_SRCLK_OFFS) ++#define SDRAM_SRCLK_KEPT (0 << SDRAM_SRCLK_OFFS) ++#define SDRAM_SRCLK_GATED (1 << SDRAM_SRCLK_OFFS) ++#define SDRAM_CTRL_POS_OFFS 6 ++#define SDRAM_CTRL_POS_MASK (1 << SDRAM_CTRL_POS_OFFS) ++#define SDRAM_CTRL_POS_FALL (0 << SDRAM_CTRL_POS_OFFS) ++#define SDRAM_CTRL_POS_RISE (1 << SDRAM_CTRL_POS_OFFS) ++#define SDRAM_CLK1DRV_OFFS 12 ++#define SDRAM_CLK1DRV_MASK (1 << SDRAM_CLK1DRV_OFFS) ++#define SDRAM_CLK1DRV_HIGH_Z (0 << SDRAM_CLK1DRV_OFFS) ++#define SDRAM_CLK1DRV_NORMAL (1 << SDRAM_CLK1DRV_OFFS) ++#define SDRAM_CLK2DRV_OFFS 13 ++#define SDRAM_CLK2DRV_MASK (1 << SDRAM_CLK2DRV_OFFS) ++#define SDRAM_CLK2DRV_HIGH_Z (0 << SDRAM_CLK2DRV_OFFS) ++#define SDRAM_CLK2DRV_NORMAL (1 << SDRAM_CLK2DRV_OFFS) ++#define SDRAM_SB_OUT_DEL_OFFS 20 ++#define SDRAM_SB_OUT_DEL_MAX 0xf ++#define SDRAM_SB_OUT_MASK (SDRAM_SB_OUT_DEL_MAX<= MV_DRAM_MAX_CS )) ++ { ++ DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); ++ return MV_BAD_PARAM; ++ } ++ memset(pBankInfo, 0, sizeof(*pBankInfo)); ++ ++ if ( MV_OK != dimmSpdGet((MV_U32)(bankNum/2), &dimmInfo)) ++ { ++ DB(mvOsPrintf("Dram: ERR dimmSpdGet failed to get dimm info \n")); ++ return MV_FAIL; ++ } ++ if ((dimmInfo.numOfModuleBanks == 1) && ((bankNum % 2) == 1)) ++ { ++ DB(mvOsPrintf("Dram: ERR dimmSpdGet. Can't find DIMM bank 2 \n")); ++ return MV_FAIL; ++ } ++ /* convert Dimm info to Bank info */ ++ cpyDimm2BankInfo(&dimmInfo, pBankInfo); ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* cpyDimm2BankInfo - Convert a Dimm info struct into a bank info struct. ++* ++* DESCRIPTION: ++* Convert a Dimm info struct into a bank info struct. ++* ++* INPUT: ++* pDimmInfo - DIMM information structure. ++* ++* OUTPUT: ++* pBankInfo - DRAM bank information struct. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++static MV_VOID cpyDimm2BankInfo(MV_DIMM_INFO *pDimmInfo, ++ MV_DRAM_BANK_INFO *pBankInfo) ++{ ++ pBankInfo->memoryType = pDimmInfo->memoryType; ++ ++ /* DIMM dimensions */ ++ pBankInfo->numOfRowAddr = pDimmInfo->numOfRowAddr; ++ pBankInfo->numOfColAddr = pDimmInfo->numOfColAddr; ++ pBankInfo->dataWidth = pDimmInfo->dataWidth; ++ pBankInfo->errorCheckType = pDimmInfo->errorCheckType; ++ pBankInfo->sdramWidth = pDimmInfo->sdramWidth; ++ pBankInfo->errorCheckDataWidth = pDimmInfo->errorCheckDataWidth; ++ pBankInfo->numOfBanksOnEachDevice = pDimmInfo->numOfBanksOnEachDevice; ++ pBankInfo->suportedCasLatencies = pDimmInfo->suportedCasLatencies; ++ pBankInfo->refreshInterval = pDimmInfo->refreshInterval; ++ ++ /* DIMM timing parameters */ ++ pBankInfo->minCycleTimeAtMaxCasLatPs = pDimmInfo->minCycleTimeAtMaxCasLatPs; ++ pBankInfo->minCycleTimeAtMaxCasLatMinus1Ps = ++ pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps; ++ pBankInfo->minCycleTimeAtMaxCasLatMinus2Ps = ++ pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps; ++ ++ pBankInfo->minRowPrechargeTime = pDimmInfo->minRowPrechargeTime; ++ pBankInfo->minRowActiveToRowActive = pDimmInfo->minRowActiveToRowActive; ++ pBankInfo->minRasToCasDelay = pDimmInfo->minRasToCasDelay; ++ pBankInfo->minRasPulseWidth = pDimmInfo->minRasPulseWidth; ++ pBankInfo->minWriteRecoveryTime = pDimmInfo->minWriteRecoveryTime; ++ pBankInfo->minWriteToReadCmdDelay = pDimmInfo->minWriteToReadCmdDelay; ++ pBankInfo->minReadToPrechCmdDelay = pDimmInfo->minReadToPrechCmdDelay; ++ pBankInfo->minRefreshToActiveCmd = pDimmInfo->minRefreshToActiveCmd; ++ ++ /* Parameters calculated from the extracted DIMM information */ ++ pBankInfo->size = pDimmInfo->size/pDimmInfo->numOfModuleBanks; ++ pBankInfo->deviceDensity = pDimmInfo->deviceDensity; ++ pBankInfo->numberOfDevices = pDimmInfo->numberOfDevices / ++ pDimmInfo->numOfModuleBanks; ++ ++ /* DIMM attributes (MV_TRUE for yes) */ ++ ++ if ((pDimmInfo->memoryType == MEM_TYPE_SDRAM) || ++ (pDimmInfo->memoryType == MEM_TYPE_DDR1) ) ++ { ++ if (pDimmInfo->dimmAttributes & BIT1) ++ pBankInfo->registeredAddrAndControlInputs = MV_TRUE; ++ else ++ pBankInfo->registeredAddrAndControlInputs = MV_FALSE; ++ } ++ else /* pDimmInfo->memoryType == MEM_TYPE_DDR2 */ ++ { ++ if (pDimmInfo->dimmTypeInfo & (BIT0 | BIT4)) ++ pBankInfo->registeredAddrAndControlInputs = MV_TRUE; ++ else ++ pBankInfo->registeredAddrAndControlInputs = MV_FALSE; ++ } ++ ++ return; ++} ++/******************************************************************************* ++* dimmSpdCpy - Cpy SPD parameters from dimm 0 to dimm 1. ++* ++* DESCRIPTION: ++* Read the DIMM SPD parameters from dimm 0 into dimm 1 SPD. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. ++* ++*******************************************************************************/ ++MV_STATUS dimmSpdCpy(MV_VOID) ++{ ++ MV_U32 i; ++ MV_U32 spdChecksum; ++ ++ MV_TWSI_SLAVE twsiSlave; ++ MV_U8 data[SPD_SIZE]; ++ ++ /* zero dimmInfo structure */ ++ memset(data, 0, SPD_SIZE); ++ ++ /* read the dimm eeprom */ ++ DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); ++ twsiSlave.slaveAddr.address = MV_BOARD_DIMM0_I2C_ADDR; ++ twsiSlave.slaveAddr.type = ADDR7_BIT; ++ twsiSlave.validOffset = MV_TRUE; ++ twsiSlave.offset = 0; ++ twsiSlave.moreThen256 = MV_FALSE; ++ ++ if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, &twsiSlave, data, SPD_SIZE) ) ++ { ++ DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 0\n")); ++ return MV_FAIL; ++ } ++ DB(puts("DRAM: Reading dimm info succeded.\n")); ++ ++ /* calculate SPD checksum */ ++ spdChecksum = 0; ++ ++ for(i = 0 ; i <= 62 ; i++) ++ { ++ spdChecksum += data[i]; ++ } ++ ++ if ((spdChecksum & 0xff) != data[63]) ++ { ++ DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", ++ (MV_U32)(spdChecksum & 0xff), data[63])); ++ } ++ else ++ { ++ DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); ++ } ++ ++ /* copy the SPD content 1:1 into the DIMM 1 SPD */ ++ twsiSlave.slaveAddr.address = MV_BOARD_DIMM1_I2C_ADDR; ++ twsiSlave.slaveAddr.type = ADDR7_BIT; ++ twsiSlave.validOffset = MV_TRUE; ++ twsiSlave.offset = 0; ++ twsiSlave.moreThen256 = MV_FALSE; ++ ++ for(i = 0 ; i < SPD_SIZE ; i++) ++ { ++ twsiSlave.offset = i; ++ if( MV_OK != mvTwsiWrite (MV_BOARD_DIMM_I2C_CHANNEL, &twsiSlave, &data[i], 1) ) ++ { ++ mvOsPrintf("DRAM: ERR. no DIMM in dimmNum 1 byte %d \n",i); ++ return MV_FAIL; ++ } ++ mvOsDelay(5); ++ } ++ ++ DB(puts("DRAM: Reading dimm info succeded.\n")); ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* dimmSpdGet - Get the SPD parameters. ++* ++* DESCRIPTION: ++* Read the DIMM SPD parameters into given struct parameter. ++* ++* INPUT: ++* dimmNum - DIMM number. See MV_BOARD_DIMM_NUM enumerator. ++* ++* OUTPUT: ++* pDimmInfo - DIMM information structure. ++* ++* RETURN: ++* MV_TRUE if function could read DIMM parameters, MV_FALSE otherwise. ++* ++*******************************************************************************/ ++MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo) ++{ ++ MV_U32 i; ++ MV_U32 density = 1; ++ MV_U32 spdChecksum; ++ ++ MV_TWSI_SLAVE twsiSlave; ++ MV_U8 data[SPD_SIZE]; ++ ++ if((NULL == pDimmInfo)|| (dimmNum >= MAX_DIMM_NUM)) ++ { ++ DB(mvOsPrintf("Dram: mvDramBankInfoGet bad params \n")); ++ return MV_BAD_PARAM; ++ } ++ ++ /* zero dimmInfo structure */ ++ memset(data, 0, SPD_SIZE); ++ ++ /* read the dimm eeprom */ ++ DB(mvOsPrintf("DRAM: Read Dimm eeprom\n")); ++ twsiSlave.slaveAddr.address = (dimmNum == 0) ? ++ MV_BOARD_DIMM0_I2C_ADDR : MV_BOARD_DIMM1_I2C_ADDR; ++ twsiSlave.slaveAddr.type = ADDR7_BIT; ++ twsiSlave.validOffset = MV_TRUE; ++ twsiSlave.offset = 0; ++ twsiSlave.moreThen256 = MV_FALSE; ++ ++ if( MV_OK != mvTwsiRead (MV_BOARD_DIMM_I2C_CHANNEL, &twsiSlave, data, SPD_SIZE) ) ++ { ++ DB(mvOsPrintf("DRAM: ERR. no DIMM in dimmNum %d \n", dimmNum)); ++ return MV_FAIL; ++ } ++ DB(puts("DRAM: Reading dimm info succeded.\n")); ++ ++ /* calculate SPD checksum */ ++ spdChecksum = 0; ++ ++ for(i = 0 ; i <= 62 ; i++) ++ { ++ spdChecksum += data[i]; ++ } ++ ++ if ((spdChecksum & 0xff) != data[63]) ++ { ++ DB(mvOsPrintf("DRAM: Warning. Wrong SPD Checksum %2x, expValue=%2x\n", ++ (MV_U32)(spdChecksum & 0xff), data[63])); ++ } ++ else ++ { ++ DB(mvOsPrintf("DRAM: SPD Checksum ok!\n")); ++ } ++ ++ /* copy the SPD content 1:1 into the dimmInfo structure*/ ++ for(i = 0 ; i < SPD_SIZE ; i++) ++ { ++ pDimmInfo->spdRawData[i] = data[i]; ++ DB(mvOsPrintf("SPD-EEPROM Byte %3d = %3x (%3d)\n",i, data[i], data[i])); ++ } ++ ++ DB(mvOsPrintf("DRAM SPD Information:\n")); ++ ++ /* Memory type (DDR / SDRAM) */ ++ switch (data[DIMM_MEM_TYPE]) ++ { ++ case (DIMM_MEM_TYPE_SDRAM): ++ pDimmInfo->memoryType = MEM_TYPE_SDRAM; ++ DB(mvOsPrintf("DRAM Memeory type SDRAM\n")); ++ break; ++ case (DIMM_MEM_TYPE_DDR1): ++ pDimmInfo->memoryType = MEM_TYPE_DDR1; ++ DB(mvOsPrintf("DRAM Memeory type DDR1\n")); ++ break; ++ case (DIMM_MEM_TYPE_DDR2): ++ pDimmInfo->memoryType = MEM_TYPE_DDR2; ++ DB(mvOsPrintf("DRAM Memeory type DDR2\n")); ++ break; ++ default: ++ mvOsPrintf("ERROR: Undefined memory type!\n"); ++ return MV_ERROR; ++ } ++ ++ ++ /* Number Of Row Addresses */ ++ pDimmInfo->numOfRowAddr = data[DIMM_ROW_NUM]; ++ DB(mvOsPrintf("DRAM numOfRowAddr[3] %d\n",pDimmInfo->numOfRowAddr)); ++ ++ /* Number Of Column Addresses */ ++ pDimmInfo->numOfColAddr = data[DIMM_COL_NUM]; ++ DB(mvOsPrintf("DRAM numOfColAddr[4] %d\n",pDimmInfo->numOfColAddr)); ++ ++ /* Number Of Module Banks */ ++ pDimmInfo->numOfModuleBanks = data[DIMM_MODULE_BANK_NUM]; ++ DB(mvOsPrintf("DRAM numOfModuleBanks[5] 0x%x\n", ++ pDimmInfo->numOfModuleBanks)); ++ ++ /* Number of module banks encoded differently for DDR2 */ ++ if (pDimmInfo->memoryType == MEM_TYPE_DDR2) ++ pDimmInfo->numOfModuleBanks = (pDimmInfo->numOfModuleBanks & 0x7)+1; ++ ++ /* Data Width */ ++ pDimmInfo->dataWidth = data[DIMM_DATA_WIDTH]; ++ DB(mvOsPrintf("DRAM dataWidth[6] 0x%x\n", pDimmInfo->dataWidth)); ++ ++ /* Minimum Cycle Time At Max CasLatancy */ ++ pDimmInfo->minCycleTimeAtMaxCasLatPs = cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS]); ++ ++ /* Error Check Type */ ++ pDimmInfo->errorCheckType = data[DIMM_ERR_CHECK_TYPE]; ++ DB(mvOsPrintf("DRAM errorCheckType[11] 0x%x\n", ++ pDimmInfo->errorCheckType)); ++ ++ /* Refresh Interval */ ++ pDimmInfo->refreshInterval = data[DIMM_REFRESH_INTERVAL]; ++ DB(mvOsPrintf("DRAM refreshInterval[12] 0x%x\n", ++ pDimmInfo->refreshInterval)); ++ ++ /* Sdram Width */ ++ pDimmInfo->sdramWidth = data[DIMM_SDRAM_WIDTH]; ++ DB(mvOsPrintf("DRAM sdramWidth[13] 0x%x\n",pDimmInfo->sdramWidth)); ++ ++ /* Error Check Data Width */ ++ pDimmInfo->errorCheckDataWidth = data[DIMM_ERR_CHECK_DATA_WIDTH]; ++ DB(mvOsPrintf("DRAM errorCheckDataWidth[14] 0x%x\n", ++ pDimmInfo->errorCheckDataWidth)); ++ ++ /* Burst Length Supported */ ++ /* SDRAM/DDR1: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * ++ *********************************************************/ ++ /* DDR2: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * ++ *********************************************************/ ++ ++ pDimmInfo->burstLengthSupported = data[DIMM_BURST_LEN_SUP]; ++ DB(mvOsPrintf("DRAM burstLengthSupported[16] 0x%x\n", ++ pDimmInfo->burstLengthSupported)); ++ ++ /* Number Of Banks On Each Device */ ++ pDimmInfo->numOfBanksOnEachDevice = data[DIMM_DEV_BANK_NUM]; ++ DB(mvOsPrintf("DRAM numOfBanksOnEachDevice[17] 0x%x\n", ++ pDimmInfo->numOfBanksOnEachDevice)); ++ ++ /* Suported Cas Latencies */ ++ ++ /* SDRAM: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * ++ ********************************************************/ ++ ++ /* DDR 1: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * ++ *********************************************************/ ++ ++ /* DDR 2: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * ++ *********************************************************/ ++ ++ pDimmInfo->suportedCasLatencies = data[DIMM_SUP_CAL]; ++ DB(mvOsPrintf("DRAM suportedCasLatencies[18] 0x%x\n", ++ pDimmInfo->suportedCasLatencies)); ++ ++ /* For DDR2 only, get the DIMM type information */ ++ if (pDimmInfo->memoryType == MEM_TYPE_DDR2) ++ { ++ pDimmInfo->dimmTypeInfo = data[DIMM_DDR2_TYPE_INFORMATION]; ++ DB(mvOsPrintf("DRAM dimmTypeInfo[20] (DDR2) 0x%x\n", ++ pDimmInfo->dimmTypeInfo)); ++ } ++ ++ /* SDRAM Modules Attributes */ ++ pDimmInfo->dimmAttributes = data[DIMM_BUF_ADDR_CONT_IN]; ++ DB(mvOsPrintf("DRAM dimmAttributes[21] 0x%x\n", ++ pDimmInfo->dimmAttributes)); ++ ++ /* Minimum Cycle Time At Max CasLatancy Minus 1*/ ++ pDimmInfo->minCycleTimeAtMaxCasLatMinus1Ps = ++ cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS1]); ++ ++ /* Minimum Cycle Time At Max CasLatancy Minus 2*/ ++ pDimmInfo->minCycleTimeAtMaxCasLatMinus2Ps = ++ cas2ps(data[DIMM_MIN_CC_AT_MAX_CAS_MINUS2]); ++ ++ pDimmInfo->minRowPrechargeTime = data[DIMM_MIN_ROW_PRECHARGE_TIME]; ++ DB(mvOsPrintf("DRAM minRowPrechargeTime[27] 0x%x\n", ++ pDimmInfo->minRowPrechargeTime)); ++ pDimmInfo->minRowActiveToRowActive = data[DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE]; ++ DB(mvOsPrintf("DRAM minRowActiveToRowActive[28] 0x%x\n", ++ pDimmInfo->minRowActiveToRowActive)); ++ pDimmInfo->minRasToCasDelay = data[DIMM_MIN_RAS_TO_CAS_DELAY]; ++ DB(mvOsPrintf("DRAM minRasToCasDelay[29] 0x%x\n", ++ pDimmInfo->minRasToCasDelay)); ++ pDimmInfo->minRasPulseWidth = data[DIMM_MIN_RAS_PULSE_WIDTH]; ++ DB(mvOsPrintf("DRAM minRasPulseWidth[30] 0x%x\n", ++ pDimmInfo->minRasPulseWidth)); ++ ++ /* DIMM Bank Density */ ++ pDimmInfo->dimmBankDensity = data[DIMM_BANK_DENSITY]; ++ DB(mvOsPrintf("DRAM dimmBankDensity[31] 0x%x\n", ++ pDimmInfo->dimmBankDensity)); ++ ++ /* Only DDR2 includes Write Recovery Time field. Other SDRAM ignore */ ++ pDimmInfo->minWriteRecoveryTime = data[DIMM_MIN_WRITE_RECOVERY_TIME]; ++ DB(mvOsPrintf("DRAM minWriteRecoveryTime[36] 0x%x\n", ++ pDimmInfo->minWriteRecoveryTime)); ++ ++ /* Only DDR2 includes Internal Write To Read Command Delay field. */ ++ pDimmInfo->minWriteToReadCmdDelay = data[DIMM_MIN_WRITE_TO_READ_CMD_DELAY]; ++ DB(mvOsPrintf("DRAM minWriteToReadCmdDelay[37] 0x%x\n", ++ pDimmInfo->minWriteToReadCmdDelay)); ++ ++ /* Only DDR2 includes Internal Read To Precharge Command Delay field. */ ++ pDimmInfo->minReadToPrechCmdDelay = data[DIMM_MIN_READ_TO_PRECH_CMD_DELAY]; ++ DB(mvOsPrintf("DRAM minReadToPrechCmdDelay[38] 0x%x\n", ++ pDimmInfo->minReadToPrechCmdDelay)); ++ ++ /* Only DDR2 includes Minimum Refresh to Activate/Refresh Command field */ ++ pDimmInfo->minRefreshToActiveCmd = data[DIMM_MIN_REFRESH_TO_ACTIVATE_CMD]; ++ DB(mvOsPrintf("DRAM minRefreshToActiveCmd[42] 0x%x\n", ++ pDimmInfo->minRefreshToActiveCmd)); ++ ++ /* calculating the sdram density. Representing device density from */ ++ /* bit 20 to allow representation of 4GB and above. */ ++ /* For example, if density is 512Mbit 0x20000000, will be represent in */ ++ /* deviceDensity by 0x20000000 >> 16 --> 0x00000200. Another example */ ++ /* is density 8GB 0x200000000 >> 16 --> 0x00002000. */ ++ density = (1 << ((pDimmInfo->numOfRowAddr + pDimmInfo->numOfColAddr) - 20)); ++ pDimmInfo->deviceDensity = density * ++ pDimmInfo->numOfBanksOnEachDevice * ++ pDimmInfo->sdramWidth; ++ DB(mvOsPrintf("DRAM deviceDensity %d\n",pDimmInfo->deviceDensity)); ++ ++ /* Number of devices includeing Error correction */ ++ pDimmInfo->numberOfDevices = (pDimmInfo->dataWidth/pDimmInfo->sdramWidth) * ++ pDimmInfo->numOfModuleBanks; ++ DB(mvOsPrintf("DRAM numberOfDevices %d\n", ++ pDimmInfo->numberOfDevices)); ++ ++ pDimmInfo->size = 0; ++ ++ /* Note that pDimmInfo->size is in MB units */ ++ if (pDimmInfo->memoryType == MEM_TYPE_SDRAM) ++ { ++ if (pDimmInfo->dimmBankDensity & BIT0) ++ pDimmInfo->size += 1024; /* Equal to 1GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT1) ++ pDimmInfo->size += 8; /* Equal to 8MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT2) ++ pDimmInfo->size += 16; /* Equal to 16MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT3) ++ pDimmInfo->size += 32; /* Equal to 32MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT4) ++ pDimmInfo->size += 64; /* Equal to 64MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT5) ++ pDimmInfo->size += 128; /* Equal to 128MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT6) ++ pDimmInfo->size += 256; /* Equal to 256MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT7) ++ pDimmInfo->size += 512; /* Equal to 512MB */ ++ } ++ else if (pDimmInfo->memoryType == MEM_TYPE_DDR1) ++ { ++ if (pDimmInfo->dimmBankDensity & BIT0) ++ pDimmInfo->size += 1024; /* Equal to 1GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT1) ++ pDimmInfo->size += 2048; /* Equal to 2GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT2) ++ pDimmInfo->size += 16; /* Equal to 16MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT3) ++ pDimmInfo->size += 32; /* Equal to 32MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT4) ++ pDimmInfo->size += 64; /* Equal to 64MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT5) ++ pDimmInfo->size += 128; /* Equal to 128MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT6) ++ pDimmInfo->size += 256; /* Equal to 256MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT7) ++ pDimmInfo->size += 512; /* Equal to 512MB */ ++ } ++ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ ++ { ++ if (pDimmInfo->dimmBankDensity & BIT0) ++ pDimmInfo->size += 1024; /* Equal to 1GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT1) ++ pDimmInfo->size += 2048; /* Equal to 2GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT2) ++ pDimmInfo->size += 4096; /* Equal to 4GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT3) ++ pDimmInfo->size += 8192; /* Equal to 8GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT4) ++ pDimmInfo->size += 16384; /* Equal to 16GB */ ++ else if (pDimmInfo->dimmBankDensity & BIT5) ++ pDimmInfo->size += 128; /* Equal to 128MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT6) ++ pDimmInfo->size += 256; /* Equal to 256MB */ ++ else if (pDimmInfo->dimmBankDensity & BIT7) ++ pDimmInfo->size += 512; /* Equal to 512MB */ ++ } ++ ++ pDimmInfo->size *= pDimmInfo->numOfModuleBanks; ++ ++ DB(mvOsPrintf("Dram: dimm size %dMB \n",pDimmInfo->size)); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* dimmSpdPrint - Print the SPD parameters. ++* ++* DESCRIPTION: ++* Print the Dimm SPD parameters. ++* ++* INPUT: ++* pDimmInfo - DIMM information structure. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_VOID dimmSpdPrint(MV_U32 dimmNum) ++{ ++ MV_DIMM_INFO dimmInfo; ++ MV_U32 i, temp = 0; ++ MV_U32 k, maskLeftOfPoint = 0, maskRightOfPoint = 0; ++ MV_U32 rightOfPoint = 0,leftOfPoint = 0, div, time_tmp, shift; ++ MV_U32 busClkPs; ++ MV_U8 trp_clocks=0, trcd_clocks, tras_clocks, trrd_clocks, ++ temp_buf[40], *spdRawData; ++ ++ busClkPs = 1000000000 / (mvBoardSysClkGet() / 100); /* in 10 ps units */ ++ ++ spdRawData = dimmInfo.spdRawData; ++ ++ if(MV_OK != dimmSpdGet(dimmNum, &dimmInfo)) ++ { ++ mvOsOutput("ERROR: Could not read SPD information!\n"); ++ return; ++ } ++ ++ /* find Manufactura of Dimm Module */ ++ mvOsOutput("\nManufacturer's JEDEC ID Code: "); ++ for(i = 0 ; i < DIMM_MODULE_MANU_SIZE ; i++) ++ { ++ mvOsOutput("%x",spdRawData[DIMM_MODULE_MANU_OFFS + i]); ++ } ++ mvOsOutput("\n"); ++ ++ /* Manufacturer's Specific Data */ ++ for(i = 0 ; i < DIMM_MODULE_ID_SIZE ; i++) ++ { ++ temp_buf[i] = spdRawData[DIMM_MODULE_ID_OFFS + i]; ++ } ++ mvOsOutput("Manufacturer's Specific Data: %s\n", temp_buf); ++ ++ /* Module Part Number */ ++ for(i = 0 ; i < DIMM_MODULE_VEN_SIZE ; i++) ++ { ++ temp_buf[i] = spdRawData[DIMM_MODULE_VEN_OFFS + i]; ++ } ++ mvOsOutput("Module Part Number: %s\n", temp_buf); ++ ++ /* Module Serial Number */ ++ for(i = 0; i < sizeof(MV_U32); i++) ++ { ++ temp |= spdRawData[95+i] << 8*i; ++ } ++ mvOsOutput("DIMM Serial No. %ld (%lx)\n", (long)temp, ++ (long)temp); ++ ++ /* find Manufac-Data of Dimm Module */ ++ mvOsOutput("Manufactoring Date: Year 20%d%d/ ww %d%d\n", ++ ((spdRawData[93] & 0xf0) >> 4), (spdRawData[93] & 0xf), ++ ((spdRawData[94] & 0xf0) >> 4), (spdRawData[94] & 0xf)); ++ /* find modul_revision of Dimm Module */ ++ mvOsOutput("Module Revision: %d.%d\n", ++ spdRawData[62]/10, spdRawData[62]%10); ++ ++ /* find manufac_place of Dimm Module */ ++ mvOsOutput("manufac_place: %d\n", spdRawData[72]); ++ ++ /* go over the first 35 I2C data bytes */ ++ for(i = 2 ; i <= 35 ; i++) ++ switch(i) ++ { ++ case 2: /* Memory type (DDR1/2 / SDRAM) */ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ mvOsOutput("Dram Type is: SDRAM\n"); ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) ++ mvOsOutput("Dram Type is: SDRAM DDR1\n"); ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) ++ mvOsOutput("Dram Type is: SDRAM DDR2\n"); ++ else ++ mvOsOutput("Dram Type unknown\n"); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 3: /* Number Of Row Addresses */ ++ mvOsOutput("Module Number of row addresses: %d\n", ++ dimmInfo.numOfRowAddr); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 4: /* Number Of Column Addresses */ ++ mvOsOutput("Module Number of col addresses: %d\n", ++ dimmInfo.numOfColAddr); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 5: /* Number Of Module Banks */ ++ mvOsOutput("Number of Banks on Mod.: %d\n", ++ dimmInfo.numOfModuleBanks); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 6: /* Data Width */ ++ mvOsOutput("Module Data Width: %d bit\n", ++ dimmInfo.dataWidth); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 8: /* Voltage Interface */ ++ switch(spdRawData[i]) ++ { ++ case 0x0: ++ mvOsOutput("Module is TTL_5V_TOLERANT\n"); ++ break; ++ case 0x1: ++ mvOsOutput("Module is LVTTL\n"); ++ break; ++ case 0x2: ++ mvOsOutput("Module is HSTL_1_5V\n"); ++ break; ++ case 0x3: ++ mvOsOutput("Module is SSTL_3_3V\n"); ++ break; ++ case 0x4: ++ mvOsOutput("Module is SSTL_2_5V\n"); ++ break; ++ case 0x5: ++ if (dimmInfo.memoryType != MEM_TYPE_SDRAM) ++ { ++ mvOsOutput("Module is SSTL_1_8V\n"); ++ break; ++ } ++ default: ++ mvOsOutput("Module is VOLTAGE_UNKNOWN\n"); ++ break; ++ } ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 9: /* Minimum Cycle Time At Max CasLatancy */ ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ rightOfPoint = (spdRawData[i] & 0x0f) * 10; ++ ++ /* DDR2 addition of right of point */ ++ if ((spdRawData[i] & 0x0f) == 0xA) ++ { ++ rightOfPoint = 25; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xB) ++ { ++ rightOfPoint = 33; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xC) ++ { ++ rightOfPoint = 66; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xD) ++ { ++ rightOfPoint = 75; ++ } ++ mvOsOutput("Minimum Cycle Time At Max CL: %d.%d [ns]\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 10: /* Clock To Data Out */ ++ div = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 10:100; ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = time_tmp / div; ++ rightOfPoint = time_tmp % div; ++ mvOsOutput("Clock To Data Out: %d.%d [ns]\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 11: /* Error Check Type */ ++ mvOsOutput("Error Check Type (0=NONE): %d\n", ++ dimmInfo.errorCheckType); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 12: /* Refresh Interval */ ++ mvOsOutput("Refresh Rate: %x\n", ++ dimmInfo.refreshInterval); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 13: /* Sdram Width */ ++ mvOsOutput("Sdram Width: %d bits\n", ++ dimmInfo.sdramWidth); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 14: /* Error Check Data Width */ ++ mvOsOutput("Error Check Data Width: %d bits\n", ++ dimmInfo.errorCheckDataWidth); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 15: /* Minimum Clock Delay is unsupported */ ++ if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || ++ (dimmInfo.memoryType == MEM_TYPE_DDR1)) ++ { ++ mvOsOutput("Minimum Clk Delay back to back: %d\n", ++ spdRawData[i]); ++ } ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 16: /* Burst Length Supported */ ++ /* SDRAM/DDR1: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ burst length = * Page | TBD | TBD | TBD | 8 | 4 | 2 | 1 * ++ *********************************************************/ ++ /* DDR2: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ burst length = * Page | TBD | TBD | TBD | 8 | 4 | TBD | TBD * ++ *********************************************************/ ++ mvOsOutput("Burst Length Supported: "); ++ if ((dimmInfo.memoryType == MEM_TYPE_SDRAM) || ++ (dimmInfo.memoryType == MEM_TYPE_DDR1)) ++ { ++ if (dimmInfo.burstLengthSupported & BIT0) ++ mvOsOutput("1, "); ++ if (dimmInfo.burstLengthSupported & BIT1) ++ mvOsOutput("2, "); ++ } ++ if (dimmInfo.burstLengthSupported & BIT2) ++ mvOsOutput("4, "); ++ if (dimmInfo.burstLengthSupported & BIT3) ++ mvOsOutput("8, "); ++ ++ mvOsOutput(" Bit \n"); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 17: /* Number Of Banks On Each Device */ ++ mvOsOutput("Number Of Banks On Each Chip: %d\n", ++ dimmInfo.numOfBanksOnEachDevice); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 18: /* Suported Cas Latencies */ ++ ++ /* SDRAM: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * ++ ********************************************************/ ++ ++ /* DDR 1: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * ++ *********************************************************/ ++ ++ /* DDR 2: ++ *******-******-******-******-******-******-******-******* ++ * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * ++ *******-******-******-******-******-******-******-******* ++ CAS = * TBD | TBD | 5 | 4 | 3 | 2 | TBD | TBD * ++ *********************************************************/ ++ ++ mvOsOutput("Suported Cas Latencies: (CL) "); ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ for (k = 0; k <=7; k++) ++ { ++ if (dimmInfo.suportedCasLatencies & (1 << k)) ++ mvOsOutput("%d, ", k+1); ++ } ++ } ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) ++ { ++ if (dimmInfo.suportedCasLatencies & BIT0) ++ mvOsOutput("1, "); ++ if (dimmInfo.suportedCasLatencies & BIT1) ++ mvOsOutput("1.5, "); ++ if (dimmInfo.suportedCasLatencies & BIT2) ++ mvOsOutput("2, "); ++ if (dimmInfo.suportedCasLatencies & BIT3) ++ mvOsOutput("2.5, "); ++ if (dimmInfo.suportedCasLatencies & BIT4) ++ mvOsOutput("3, "); ++ if (dimmInfo.suportedCasLatencies & BIT5) ++ mvOsOutput("3.5, "); ++ } ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) ++ { ++ if (dimmInfo.suportedCasLatencies & BIT2) ++ mvOsOutput("2, "); ++ if (dimmInfo.suportedCasLatencies & BIT3) ++ mvOsOutput("3, "); ++ if (dimmInfo.suportedCasLatencies & BIT4) ++ mvOsOutput("4, "); ++ if (dimmInfo.suportedCasLatencies & BIT5) ++ mvOsOutput("5, "); ++ } ++ else ++ mvOsOutput("?.?, "); ++ mvOsOutput("\n"); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 20: /* DDR2 DIMM type info */ ++ if (dimmInfo.memoryType == MEM_TYPE_DDR2) ++ { ++ if (dimmInfo.dimmTypeInfo & (BIT0 | BIT4)) ++ mvOsOutput("Registered DIMM (RDIMM)\n"); ++ else if (dimmInfo.dimmTypeInfo & (BIT1 | BIT5)) ++ mvOsOutput("Unbuffered DIMM (UDIMM)\n"); ++ else ++ mvOsOutput("Unknown DIMM type.\n"); ++ } ++ ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 21: /* SDRAM Modules Attributes */ ++ mvOsOutput("\nModule Attributes (SPD Byte 21): \n"); ++ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ if (dimmInfo.dimmAttributes & BIT0) ++ mvOsOutput(" Buffered Addr/Control Input: Yes\n"); ++ else ++ mvOsOutput(" Buffered Addr/Control Input: No\n"); ++ ++ if (dimmInfo.dimmAttributes & BIT1) ++ mvOsOutput(" Registered Addr/Control Input: Yes\n"); ++ else ++ mvOsOutput(" Registered Addr/Control Input: No\n"); ++ ++ if (dimmInfo.dimmAttributes & BIT2) ++ mvOsOutput(" On-Card PLL (clock): Yes \n"); ++ else ++ mvOsOutput(" On-Card PLL (clock): No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT3) ++ mvOsOutput(" Bufferd DQMB Input: Yes \n"); ++ else ++ mvOsOutput(" Bufferd DQMB Inputs: No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT4) ++ mvOsOutput(" Registered DQMB Inputs: Yes \n"); ++ else ++ mvOsOutput(" Registered DQMB Inputs: No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT5) ++ mvOsOutput(" Differential Clock Input: Yes \n"); ++ else ++ mvOsOutput(" Differential Clock Input: No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT6) ++ mvOsOutput(" redundant Row Addressing: Yes \n"); ++ else ++ mvOsOutput(" redundant Row Addressing: No \n"); ++ } ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) ++ { ++ if (dimmInfo.dimmAttributes & BIT0) ++ mvOsOutput(" Buffered Addr/Control Input: Yes\n"); ++ else ++ mvOsOutput(" Buffered Addr/Control Input: No\n"); ++ ++ if (dimmInfo.dimmAttributes & BIT1) ++ mvOsOutput(" Registered Addr/Control Input: Yes\n"); ++ else ++ mvOsOutput(" Registered Addr/Control Input: No\n"); ++ ++ if (dimmInfo.dimmAttributes & BIT2) ++ mvOsOutput(" On-Card PLL (clock): Yes \n"); ++ else ++ mvOsOutput(" On-Card PLL (clock): No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT3) ++ mvOsOutput(" FET Switch On-Card Enabled: Yes \n"); ++ else ++ mvOsOutput(" FET Switch On-Card Enabled: No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT4) ++ mvOsOutput(" FET Switch External Enabled: Yes \n"); ++ else ++ mvOsOutput(" FET Switch External Enabled: No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT5) ++ mvOsOutput(" Differential Clock Input: Yes \n"); ++ else ++ mvOsOutput(" Differential Clock Input: No \n"); ++ } ++ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ ++ { ++ mvOsOutput(" Number of Active Registers on the DIMM: %d\n", ++ (dimmInfo.dimmAttributes & 0x3) + 1); ++ ++ mvOsOutput(" Number of PLLs on the DIMM: %d\n", ++ ((dimmInfo.dimmAttributes) >> 2) & 0x3); ++ ++ if (dimmInfo.dimmAttributes & BIT4) ++ mvOsOutput(" FET Switch External Enabled: Yes \n"); ++ else ++ mvOsOutput(" FET Switch External Enabled: No \n"); ++ ++ if (dimmInfo.dimmAttributes & BIT6) ++ mvOsOutput(" Analysis probe installed: Yes \n"); ++ else ++ mvOsOutput(" Analysis probe installed: No \n"); ++ } ++ ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 22: /* Suported AutoPreCharge */ ++ mvOsOutput("\nModul Attributes (SPD Byte 22): \n"); ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ if ( spdRawData[i] & BIT0 ) ++ mvOsOutput(" Early Ras Precharge: Yes \n"); ++ else ++ mvOsOutput(" Early Ras Precharge: No \n"); ++ ++ if ( spdRawData[i] & BIT1 ) ++ mvOsOutput(" AutoPreCharge: Yes \n"); ++ else ++ mvOsOutput(" AutoPreCharge: No \n"); ++ ++ if ( spdRawData[i] & BIT2 ) ++ mvOsOutput(" Precharge All: Yes \n"); ++ else ++ mvOsOutput(" Precharge All: No \n"); ++ ++ if ( spdRawData[i] & BIT3 ) ++ mvOsOutput(" Write 1/ReadBurst: Yes \n"); ++ else ++ mvOsOutput(" Write 1/ReadBurst: No \n"); ++ ++ if ( spdRawData[i] & BIT4 ) ++ mvOsOutput(" lower VCC tolerance: 5%%\n"); ++ else ++ mvOsOutput(" lower VCC tolerance: 10%%\n"); ++ ++ if ( spdRawData[i] & BIT5 ) ++ mvOsOutput(" upper VCC tolerance: 5%%\n"); ++ else ++ mvOsOutput(" upper VCC tolerance: 10%%\n"); ++ } ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) ++ { ++ if ( spdRawData[i] & BIT0 ) ++ mvOsOutput(" Supports Weak Driver: Yes \n"); ++ else ++ mvOsOutput(" Supports Weak Driver: No \n"); ++ ++ if ( !(spdRawData[i] & BIT4) ) ++ mvOsOutput(" lower VCC tolerance: 0.2V\n"); ++ ++ if ( !(spdRawData[i] & BIT5) ) ++ mvOsOutput(" upper VCC tolerance: 0.2V\n"); ++ ++ if ( spdRawData[i] & BIT6 ) ++ mvOsOutput(" Concurrent Auto Preharge: Yes \n"); ++ else ++ mvOsOutput(" Concurrent Auto Preharge: No \n"); ++ ++ if ( spdRawData[i] & BIT7 ) ++ mvOsOutput(" Supports Fast AP: Yes \n"); ++ else ++ mvOsOutput(" Supports Fast AP: No \n"); ++ } ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR2) ++ { ++ if ( spdRawData[i] & BIT0 ) ++ mvOsOutput(" Supports Weak Driver: Yes \n"); ++ else ++ mvOsOutput(" Supports Weak Driver: No \n"); ++ } ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 23: ++ /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */ ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ rightOfPoint = (spdRawData[i] & 0x0f) * 10; ++ ++ /* DDR2 addition of right of point */ ++ if ((spdRawData[i] & 0x0f) == 0xA) ++ { ++ rightOfPoint = 25; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xB) ++ { ++ rightOfPoint = 33; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xC) ++ { ++ rightOfPoint = 66; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xD) ++ { ++ rightOfPoint = 75; ++ } ++ ++ mvOsOutput("Minimum Cycle Time At 2nd highest CasLatancy" ++ "(0 = Not supported): %d.%d [ns]\n", ++ leftOfPoint, rightOfPoint ); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 24: /* Clock To Data Out 2nd highest Cas Latency Value*/ ++ div = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? 10:100; ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = time_tmp / div; ++ rightOfPoint = time_tmp % div; ++ mvOsOutput("Clock To Data Out (2nd CL value): %d.%d [ns]\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 25: ++ /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ leftOfPoint = (spdRawData[i] & 0xfc) >> 2; ++ rightOfPoint = (spdRawData[i] & 0x3) * 25; ++ } ++ else /* DDR1 or DDR2 */ ++ { ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ rightOfPoint = (spdRawData[i] & 0x0f) * 10; ++ ++ /* DDR2 addition of right of point */ ++ if ((spdRawData[i] & 0x0f) == 0xA) ++ { ++ rightOfPoint = 25; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xB) ++ { ++ rightOfPoint = 33; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xC) ++ { ++ rightOfPoint = 66; ++ } ++ if ((spdRawData[i] & 0x0f) == 0xD) ++ { ++ rightOfPoint = 75; ++ } ++ } ++ mvOsOutput("Minimum Cycle Time At 3rd highest CasLatancy" ++ "(0 = Not supported): %d.%d [ns]\n", ++ leftOfPoint, rightOfPoint ); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 26: /* Clock To Data Out 3rd highest Cas Latency Value*/ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ leftOfPoint = (spdRawData[i] & 0xfc) >> 2; ++ rightOfPoint = (spdRawData[i] & 0x3) * 25; ++ } ++ else /* DDR1 or DDR2 */ ++ { ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = 0; ++ rightOfPoint = time_tmp; ++ } ++ mvOsOutput("Clock To Data Out (3rd CL value): %d.%2d[ns]\n", ++ leftOfPoint, rightOfPoint ); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 27: /* Minimum Row Precharge Time */ ++ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; ++ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? ++ 0xff : 0xfc; ++ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? ++ 0x00 : 0x03; ++ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); ++ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; ++ temp = ((leftOfPoint*100) + rightOfPoint);/* in 10ps Intervals*/ ++ trp_clocks = (temp + (busClkPs-1)) / busClkPs; ++ mvOsOutput("Minimum Row Precharge Time [ns]: %d.%d = " ++ "in Clk cycles %d\n", ++ leftOfPoint, rightOfPoint, trp_clocks); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 28: /* Minimum Row Active to Row Active Time */ ++ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; ++ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? ++ 0xff : 0xfc; ++ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? ++ 0x00 : 0x03; ++ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); ++ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; ++ temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ ++ trrd_clocks = (temp + (busClkPs-1)) / busClkPs; ++ mvOsOutput("Minimum Row Active -To- Row Active Delay [ns]: " ++ "%d.%d = in Clk cycles %d\n", ++ leftOfPoint, rightOfPoint, trp_clocks); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 29: /* Minimum Ras-To-Cas Delay */ ++ shift = (dimmInfo.memoryType == MEM_TYPE_SDRAM)? 0:2; ++ maskLeftOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? ++ 0xff : 0xfc; ++ maskRightOfPoint = (dimmInfo.memoryType == MEM_TYPE_SDRAM) ? ++ 0x00 : 0x03; ++ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> shift); ++ rightOfPoint = (spdRawData[i] & maskRightOfPoint)*25; ++ temp = ((leftOfPoint*100) + rightOfPoint);/* in 100ns Interval*/ ++ trcd_clocks = (temp + (busClkPs-1) )/ busClkPs; ++ mvOsOutput("Minimum Ras-To-Cas Delay [ns]: %d.%d = " ++ "in Clk cycles %d\n", ++ leftOfPoint, rightOfPoint, trp_clocks); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 30: /* Minimum Ras Pulse Width */ ++ tras_clocks = (cas2ps(spdRawData[i])+(busClkPs-1)) / busClkPs; ++ mvOsOutput("Minimum Ras Pulse Width [ns]: %d = " ++ "in Clk cycles %d\n", spdRawData[i], tras_clocks); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 31: /* Module Bank Density */ ++ mvOsOutput("Module Bank Density (more than 1= Multisize-Module):"); ++ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ if (dimmInfo.dimmBankDensity & BIT0) ++ mvOsOutput("1GB, "); ++ if (dimmInfo.dimmBankDensity & BIT1) ++ mvOsOutput("8MB, "); ++ if (dimmInfo.dimmBankDensity & BIT2) ++ mvOsOutput("16MB, "); ++ if (dimmInfo.dimmBankDensity & BIT3) ++ mvOsOutput("32MB, "); ++ if (dimmInfo.dimmBankDensity & BIT4) ++ mvOsOutput("64MB, "); ++ if (dimmInfo.dimmBankDensity & BIT5) ++ mvOsOutput("128MB, "); ++ if (dimmInfo.dimmBankDensity & BIT6) ++ mvOsOutput("256MB, "); ++ if (dimmInfo.dimmBankDensity & BIT7) ++ mvOsOutput("512MB, "); ++ } ++ else if (dimmInfo.memoryType == MEM_TYPE_DDR1) ++ { ++ if (dimmInfo.dimmBankDensity & BIT0) ++ mvOsOutput("1GB, "); ++ if (dimmInfo.dimmBankDensity & BIT1) ++ mvOsOutput("2GB, "); ++ if (dimmInfo.dimmBankDensity & BIT2) ++ mvOsOutput("16MB, "); ++ if (dimmInfo.dimmBankDensity & BIT3) ++ mvOsOutput("32MB, "); ++ if (dimmInfo.dimmBankDensity & BIT4) ++ mvOsOutput("64MB, "); ++ if (dimmInfo.dimmBankDensity & BIT5) ++ mvOsOutput("128MB, "); ++ if (dimmInfo.dimmBankDensity & BIT6) ++ mvOsOutput("256MB, "); ++ if (dimmInfo.dimmBankDensity & BIT7) ++ mvOsOutput("512MB, "); ++ } ++ else /* if (dimmInfo.memoryType == MEM_TYPE_DDR2) */ ++ { ++ if (dimmInfo.dimmBankDensity & BIT0) ++ mvOsOutput("1GB, "); ++ if (dimmInfo.dimmBankDensity & BIT1) ++ mvOsOutput("2GB, "); ++ if (dimmInfo.dimmBankDensity & BIT2) ++ mvOsOutput("4GB, "); ++ if (dimmInfo.dimmBankDensity & BIT3) ++ mvOsOutput("8GB, "); ++ if (dimmInfo.dimmBankDensity & BIT4) ++ mvOsOutput("16GB, "); ++ if (dimmInfo.dimmBankDensity & BIT5) ++ mvOsOutput("128MB, "); ++ if (dimmInfo.dimmBankDensity & BIT6) ++ mvOsOutput("256MB, "); ++ if (dimmInfo.dimmBankDensity & BIT7) ++ mvOsOutput("512MB, "); ++ } ++ mvOsOutput("\n"); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 32: /* Address And Command Setup Time (measured in ns/1000) */ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ rightOfPoint = (spdRawData[i] & 0x0f); ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ if(leftOfPoint > 7) ++ { ++ leftOfPoint *= -1; ++ } ++ } ++ else /* DDR1 or DDR2 */ ++ { ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = time_tmp / 100; ++ rightOfPoint = time_tmp % 100; ++ } ++ mvOsOutput("Address And Command Setup Time [ns]: %d.%d\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 33: /* Address And Command Hold Time */ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ rightOfPoint = (spdRawData[i] & 0x0f); ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ if(leftOfPoint > 7) ++ { ++ leftOfPoint *= -1; ++ } ++ } ++ else /* DDR1 or DDR2 */ ++ { ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = time_tmp / 100; ++ rightOfPoint = time_tmp % 100; ++ } ++ mvOsOutput("Address And Command Hold Time [ns]: %d.%d\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 34: /* Data Input Setup Time */ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ rightOfPoint = (spdRawData[i] & 0x0f); ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ if(leftOfPoint > 7) ++ { ++ leftOfPoint *= -1; ++ } ++ } ++ else /* DDR1 or DDR2 */ ++ { ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = time_tmp / 100; ++ rightOfPoint = time_tmp % 100; ++ } ++ mvOsOutput("Data Input Setup Time [ns]: %d.%d\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 35: /* Data Input Hold Time */ ++ if (dimmInfo.memoryType == MEM_TYPE_SDRAM) ++ { ++ rightOfPoint = (spdRawData[i] & 0x0f); ++ leftOfPoint = (spdRawData[i] & 0xf0) >> 4; ++ if(leftOfPoint > 7) ++ { ++ leftOfPoint *= -1; ++ } ++ } ++ else /* DDR1 or DDR2 */ ++ { ++ time_tmp = (((spdRawData[i] & 0xf0) >> 4)*10) + ++ ((spdRawData[i] & 0x0f)); ++ leftOfPoint = time_tmp / 100; ++ rightOfPoint = time_tmp % 100; ++ } ++ mvOsOutput("Data Input Hold Time [ns]: %d.%d\n\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ ++ case 36: /* Relevant for DDR2 only: Write Recovery Time */ ++ leftOfPoint = ((spdRawData[i] & maskLeftOfPoint) >> 2); ++ rightOfPoint = (spdRawData[i] & maskRightOfPoint) * 25; ++ mvOsOutput("Write Recovery Time [ns]: %d.%d\n", ++ leftOfPoint, rightOfPoint); ++ break; ++/*----------------------------------------------------------------------------*/ ++ } ++ ++} ++ ++ ++/* ++ * translate ns.ns/10 coding of SPD timing values ++ * into ps unit values ++ */ ++/******************************************************************************* ++* cas2ps - Translate x.y ns parameter to pico-seconds values ++* ++* DESCRIPTION: ++* This function translates x.y nano seconds to its value in pico seconds. ++* For example 3.75ns will return 3750. ++* ++* INPUT: ++* spd_byte - DIMM SPD byte. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* value in pico seconds. ++* ++*******************************************************************************/ ++static MV_U32 cas2ps(MV_U8 spd_byte) ++{ ++ MV_U32 ns, ns10; ++ ++ /* isolate upper nibble */ ++ ns = (spd_byte >> 4) & 0x0F; ++ /* isolate lower nibble */ ++ ns10 = (spd_byte & 0x0F); ++ ++ if( ns10 < 10 ) { ++ ns10 *= 10; ++ } ++ else if( ns10 == 10 ) ++ ns10 = 25; ++ else if( ns10 == 11 ) ++ ns10 = 33; ++ else if( ns10 == 12 ) ++ ns10 = 66; ++ else if( ns10 == 13 ) ++ ns10 = 75; ++ else ++ { ++ mvOsOutput("cas2ps Err. unsupported cycle time.\n"); ++ } ++ ++ return (ns*1000 + ns10*10); ++} ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/mvSpd.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,192 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvDram ++#define __INCmvDram ++ ++#include "ddr2/mvDramIf.h" ++#include "twsi/mvTwsi.h" ++ ++#define MAX_DIMM_NUM 2 ++#define SPD_SIZE 128 ++ ++/* Dimm spd offsets */ ++#define DIMM_MEM_TYPE 2 ++#define DIMM_ROW_NUM 3 ++#define DIMM_COL_NUM 4 ++#define DIMM_MODULE_BANK_NUM 5 ++#define DIMM_DATA_WIDTH 6 ++#define DIMM_VOLT_IF 8 ++#define DIMM_MIN_CC_AT_MAX_CAS 9 ++#define DIMM_ERR_CHECK_TYPE 11 ++#define DIMM_REFRESH_INTERVAL 12 ++#define DIMM_SDRAM_WIDTH 13 ++#define DIMM_ERR_CHECK_DATA_WIDTH 14 ++#define DIMM_MIN_CLK_DEL 15 ++#define DIMM_BURST_LEN_SUP 16 ++#define DIMM_DEV_BANK_NUM 17 ++#define DIMM_SUP_CAL 18 ++#define DIMM_DDR2_TYPE_INFORMATION 20 /* DDR2 only */ ++#define DIMM_BUF_ADDR_CONT_IN 21 ++#define DIMM_MIN_CC_AT_MAX_CAS_MINUS1 23 ++#define DIMM_MIN_CC_AT_MAX_CAS_MINUS2 25 ++#define DIMM_MIN_ROW_PRECHARGE_TIME 27 ++#define DIMM_MIN_ROW_ACTIVE_TO_ROW_ACTIVE 28 ++#define DIMM_MIN_RAS_TO_CAS_DELAY 29 ++#define DIMM_MIN_RAS_PULSE_WIDTH 30 ++#define DIMM_BANK_DENSITY 31 ++#define DIMM_MIN_WRITE_RECOVERY_TIME 36 ++#define DIMM_MIN_WRITE_TO_READ_CMD_DELAY 37 ++#define DIMM_MIN_READ_TO_PRECH_CMD_DELAY 38 ++#define DIMM_MIN_REFRESH_TO_ACTIVATE_CMD 42 ++#define DIMM_SPD_VERSION 62 ++ ++/* Dimm Memory Type values */ ++#define DIMM_MEM_TYPE_SDRAM 0x4 ++#define DIMM_MEM_TYPE_DDR1 0x7 ++#define DIMM_MEM_TYPE_DDR2 0x8 ++ ++#define DIMM_MODULE_MANU_OFFS 64 ++#define DIMM_MODULE_MANU_SIZE 8 ++#define DIMM_MODULE_VEN_OFFS 73 ++#define DIMM_MODULE_VEN_SIZE 25 ++#define DIMM_MODULE_ID_OFFS 99 ++#define DIMM_MODULE_ID_SIZE 18 ++ ++/* enumeration for voltage levels. */ ++typedef enum _mvDimmVoltageIf ++{ ++ TTL_5V_TOLERANT, ++ LVTTL, ++ HSTL_1_5V, ++ SSTL_3_3V, ++ SSTL_2_5V, ++ VOLTAGE_UNKNOWN, ++} MV_DIMM_VOLTAGE_IF; ++ ++ ++/* enumaration for SDRAM CAS Latencies. */ ++typedef enum _mvDimmSdramCas ++{ ++ SD_CL_1 =1, ++ SD_CL_2, ++ SD_CL_3, ++ SD_CL_4, ++ SD_CL_5, ++ SD_CL_6, ++ SD_CL_7, ++ SD_FAULT ++}MV_DIMM_SDRAM_CAS; ++ ++ ++/* DIMM information structure */ ++typedef struct _mvDimmInfo ++{ ++ MV_MEMORY_TYPE memoryType; /* DDR or SDRAM */ ++ ++ MV_U8 spdRawData[SPD_SIZE]; /* Content of SPD-EEPROM copied 1:1 */ ++ ++ /* DIMM dimensions */ ++ MV_U32 numOfRowAddr; ++ MV_U32 numOfColAddr; ++ MV_U32 numOfModuleBanks; ++ MV_U32 dataWidth; ++ MV_U32 errorCheckType; /* ECC , PARITY..*/ ++ MV_U32 sdramWidth; /* 4,8,16 or 32 */ ++ MV_U32 errorCheckDataWidth; /* 0 - no, 1 - Yes */ ++ MV_U32 burstLengthSupported; ++ MV_U32 numOfBanksOnEachDevice; ++ MV_U32 suportedCasLatencies; ++ MV_U32 refreshInterval; ++ MV_U32 dimmBankDensity; ++ MV_U32 dimmTypeInfo; /* DDR2 only */ ++ MV_U32 dimmAttributes; ++ ++ /* DIMM timing parameters */ ++ MV_U32 minCycleTimeAtMaxCasLatPs; ++ MV_U32 minCycleTimeAtMaxCasLatMinus1Ps; ++ MV_U32 minCycleTimeAtMaxCasLatMinus2Ps; ++ MV_U32 minRowPrechargeTime; ++ MV_U32 minRowActiveToRowActive; ++ MV_U32 minRasToCasDelay; ++ MV_U32 minRasPulseWidth; ++ MV_U32 minWriteRecoveryTime; /* DDR2 only */ ++ MV_U32 minWriteToReadCmdDelay; /* DDR2 only */ ++ MV_U32 minReadToPrechCmdDelay; /* DDR2 only */ ++ MV_U32 minRefreshToActiveCmd; /* DDR2 only */ ++ ++ /* Parameters calculated from the extracted DIMM information */ ++ MV_U32 size; /* 16,64,128,256 or 512 MByte in MB units */ ++ MV_U32 deviceDensity; /* 16,64,128,256 or 512 Mbit in MB units */ ++ MV_U32 numberOfDevices; ++ ++} MV_DIMM_INFO; ++ ++ ++MV_STATUS mvDramBankInfoGet(MV_U32 bankNum, MV_DRAM_BANK_INFO *pBankInfo); ++MV_STATUS dimmSpdGet(MV_U32 dimmNum, MV_DIMM_INFO *pDimmInfo); ++MV_VOID dimmSpdPrint(MV_U32 dimmNum); ++MV_STATUS dimmSpdCpy(MV_VOID); ++ ++#endif /* __INCmvDram */ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEth.c linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEth.c +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEth.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEth.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,2952 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++/******************************************************************************* ++* mvEth.c - Marvell's Gigabit Ethernet controller low level driver ++* ++* DESCRIPTION: ++* This file introduce OS independent APIs to Marvell's Gigabit Ethernet ++* controller. This Gigabit Ethernet Controller driver API controls ++* 1) Operations (i.e. port Init, Finish, Up, Down, PhyReset etc'). ++* 2) Data flow (i.e. port Send, Receive etc'). ++* 3) MAC Filtering functions (ethSetMcastAddr, ethSetRxFilterMode, etc.) ++* 4) MIB counters support (ethReadMibCounter) ++* 5) Debug functions (ethPortRegs, ethPortCounters, ethPortQueues, etc.) ++* Each Gigabit Ethernet port is controlled via ETH_PORT_CTRL struct. ++* This struct includes configuration information as well as driver ++* internal data needed for its operations. ++* ++* Supported Features: ++* - OS independent. All required OS services are implemented via external ++* OS dependent components (like osLayer or ethOsg) ++* - The user is free from Rx/Tx queue managing. ++* - Simple Gigabit Ethernet port operation API. ++* - Simple Gigabit Ethernet port data flow API. ++* - Data flow and operation API support per queue functionality. ++* - Support cached descriptors for better performance. ++* - PHY access and control API. ++* - Port Configuration API. ++* - Full control over Special and Other Multicast MAC tables. ++* ++*******************************************************************************/ ++/* includes */ ++#include "mvTypes.h" ++#include "mv802_3.h" ++#include "mvDebug.h" ++#include "mvCommon.h" ++#include "mvOs.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "eth-phy/mvEthPhy.h" ++#include "eth/mvEth.h" ++#include "eth/gbe/mvEthGbe.h" ++#include "cpu/mvCpu.h" ++ ++#ifdef INCLUDE_SYNC_BARR ++#include "sys/mvCpuIf.h" ++#endif ++ ++#ifdef MV_RT_DEBUG ++# define ETH_DEBUG ++#endif ++ ++ ++/* locals */ ++MV_BOOL ethDescInSram; ++MV_BOOL ethDescSwCoher; ++ ++/* This array holds the control structure of each port */ ++ETH_PORT_CTRL* ethPortCtrl[MV_ETH_MAX_PORTS]; ++ ++/* Ethernet Port Local routines */ ++ ++static void ethInitRxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue); ++ ++static void ethInitTxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue); ++ ++static void ethSetUcastTable(int portNo, int queue); ++ ++static MV_BOOL ethSetUcastAddr (int ethPortNum, MV_U8 lastNibble, int queue); ++static MV_BOOL ethSetSpecialMcastAddr(int ethPortNum, MV_U8 lastByte, int queue); ++static MV_BOOL ethSetOtherMcastAddr(int ethPortNum, MV_U8 crc8, int queue); ++ ++static void ethFreeDescrMemory(ETH_PORT_CTRL* pEthPortCtrl, MV_BUF_INFO* pDescBuf); ++static MV_U8* ethAllocDescrMemory(ETH_PORT_CTRL* pEthPortCtrl, int size, ++ MV_ULONG* pPhysAddr, MV_U32 *memHandle); ++ ++static MV_U32 mvEthMruGet(MV_U32 maxRxPktSize); ++ ++static void mvEthPortSgmiiConfig(int port); ++ ++ ++ ++/******************************************************************************/ ++/* EthDrv Initialization functions */ ++/******************************************************************************/ ++ ++/******************************************************************************* ++* mvEthHalInit - Initialize the Giga Ethernet unit ++* ++* DESCRIPTION: ++* This function initialize the Giga Ethernet unit. ++* 1) Configure Address decode windows of the unit ++* 2) Set registers to HW default values. ++* 3) Clear and Disable interrupts ++* ++* INPUT: NONE ++* ++* RETURN: NONE ++* ++* NOTE: this function is called once in the boot process. ++*******************************************************************************/ ++void mvEthHalInit(void) ++{ ++ int port; ++ ++ /* Init static data structures */ ++ for (port=0; port 0) ++ { ++ isSram = MV_TRUE; ++ #if (INTEG_SRAM_COHER == MV_CACHE_COHER_SW) ++ isSwCoher = MV_TRUE; ++ #else ++ isSwCoher = MV_FALSE; ++ #endif ++ } ++#endif /* ETH_DESCR_IN_SRAM */ ++ ++ if(pIsSram != NULL) ++ *pIsSram = isSram; ++ ++ if(pIsSwCoher != NULL) ++ *pIsSwCoher = isSwCoher; ++} ++ ++ ++ ++/******************************************************************************/ ++/* Port Initialization functions */ ++/******************************************************************************/ ++ ++/******************************************************************************* ++* mvEthPortInit - Initialize the Ethernet port driver ++* ++* DESCRIPTION: ++* This function initialize the ethernet port. ++* 1) Allocate and initialize internal port Control structure. ++* 2) Create RX and TX descriptor rings for default RX and TX queues ++* 3) Disable RX and TX operations, clear cause registers and ++* mask all interrupts. ++* 4) Set all registers to default values and clean all MAC tables. ++* ++* INPUT: ++* int portNo - Ethernet port number ++* ETH_PORT_INIT *pEthPortInit - Ethernet port init structure ++* ++* RETURN: ++* void* - ethernet port handler, that should be passed to the most other ++* functions dealing with this port. ++* ++* NOTE: This function is called once per port when loading the eth module. ++*******************************************************************************/ ++void* mvEthPortInit(int portNo, MV_ETH_PORT_INIT *pEthPortInit) ++{ ++ int queue, descSize; ++ ETH_PORT_CTRL* pPortCtrl; ++ ++ /* Check validity of parameters */ ++ if( (portNo >= (int)mvCtrlEthMaxPortGet()) || ++ (pEthPortInit->rxDefQ >= MV_ETH_RX_Q_NUM) || ++ (pEthPortInit->maxRxPktSize < 1518) ) ++ { ++ mvOsPrintf("EthPort #%d: Bad initialization parameters\n", portNo); ++ return NULL; ++ } ++ if( (pEthPortInit->rxDescrNum[pEthPortInit->rxDefQ]) == 0) ++ { ++ mvOsPrintf("EthPort #%d: rxDefQ (%d) must be created\n", ++ portNo, pEthPortInit->rxDefQ); ++ return NULL; ++ } ++ ++ pPortCtrl = (ETH_PORT_CTRL*)mvOsMalloc( sizeof(ETH_PORT_CTRL) ); ++ if(pPortCtrl == NULL) ++ { ++ mvOsPrintf("EthDrv: Can't allocate %dB for port #%d control structure!\n", ++ (int)sizeof(ETH_PORT_CTRL), portNo); ++ return NULL; ++ } ++ ++ memset(pPortCtrl, 0, sizeof(ETH_PORT_CTRL) ); ++ ethPortCtrl[portNo] = pPortCtrl; ++ ++ pPortCtrl->portState = MV_UNDEFINED_STATE; ++ ++ pPortCtrl->portNo = portNo; ++ ++ pPortCtrl->osHandle = pEthPortInit->osHandle; ++ ++ /* Copy Configuration parameters */ ++ pPortCtrl->portConfig.maxRxPktSize = pEthPortInit->maxRxPktSize; ++ pPortCtrl->portConfig.rxDefQ = pEthPortInit->rxDefQ; ++ pPortCtrl->portConfig.ejpMode = 0; ++ ++ for( queue=0; queuerxQueueConfig[queue].descrNum = pEthPortInit->rxDescrNum[queue]; ++ } ++ for( queue=0; queuetxQueueConfig[queue].descrNum = pEthPortInit->txDescrNum[queue]; ++ } ++ ++ mvEthPortDisable(pPortCtrl); ++ ++ /* Set the board information regarding PHY address */ ++ mvEthPhyAddrSet(pPortCtrl, mvBoardPhyAddrGet(portNo) ); ++ ++ /* Create all requested RX queues */ ++ for(queue=0; queuerxQueueConfig[queue].descrNum == 0) ++ continue; ++ ++ /* Allocate memory for RX descriptors */ ++ descSize = ((pPortCtrl->rxQueueConfig[queue].descrNum * ETH_RX_DESC_ALIGNED_SIZE) + ++ CPU_D_CACHE_LINE_SIZE); ++ ++ pPortCtrl->rxQueue[queue].descBuf.bufVirtPtr = ++ ethAllocDescrMemory(pPortCtrl, descSize, ++ &pPortCtrl->rxQueue[queue].descBuf.bufPhysAddr, ++ &pPortCtrl->rxQueue[queue].descBuf.memHandle); ++ pPortCtrl->rxQueue[queue].descBuf.bufSize = descSize; ++ if(pPortCtrl->rxQueue[queue].descBuf.bufVirtPtr == NULL) ++ { ++ mvOsPrintf("EthPort #%d, rxQ=%d: Can't allocate %d bytes in %s for %d RX descr\n", ++ pPortCtrl->portNo, queue, descSize, ++ ethDescInSram ? "SRAM" : "DRAM", ++ pPortCtrl->rxQueueConfig[queue].descrNum); ++ return NULL; ++ } ++ ++ ethInitRxDescRing(pPortCtrl, queue); ++ } ++ /* Create TX queues */ ++ for(queue=0; queuetxQueueConfig[queue].descrNum == 0) ++ continue; ++ ++ /* Allocate memory for TX descriptors */ ++ descSize = ((pPortCtrl->txQueueConfig[queue].descrNum * ETH_TX_DESC_ALIGNED_SIZE) + ++ CPU_D_CACHE_LINE_SIZE); ++ ++ pPortCtrl->txQueue[queue].descBuf.bufVirtPtr = ++ ethAllocDescrMemory(pPortCtrl, descSize, ++ &pPortCtrl->txQueue[queue].descBuf.bufPhysAddr, ++ &pPortCtrl->txQueue[queue].descBuf.memHandle); ++ pPortCtrl->txQueue[queue].descBuf.bufSize = descSize; ++ if(pPortCtrl->txQueue[queue].descBuf.bufVirtPtr == NULL) ++ { ++ mvOsPrintf("EthPort #%d, txQ=%d: Can't allocate %d bytes in %s for %d TX descr\n", ++ pPortCtrl->portNo, queue, descSize, ethDescInSram ? "SRAM" : "DRAM", ++ pPortCtrl->txQueueConfig[queue].descrNum); ++ return NULL; ++ } ++ ++ ethInitTxDescRing(pPortCtrl, queue); ++ } ++ mvEthDefaultsSet(pPortCtrl); ++ ++ pPortCtrl->portState = MV_IDLE; ++ return pPortCtrl; ++} ++ ++/******************************************************************************* ++* ethPortFinish - Finish the Ethernet port driver ++* ++* DESCRIPTION: ++* This function finish the ethernet port. ++* 1) Down ethernet port if needed. ++* 2) Delete RX and TX descriptor rings for all created RX and TX queues ++* 3) Free internal port Control structure. ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet port handler ++* ++* RETURN: NONE. ++* ++*******************************************************************************/ ++void mvEthPortFinish(void* pPortHndl) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ int queue, portNo = pPortCtrl->portNo; ++ ++ if(pPortCtrl->portState == MV_ACTIVE) ++ { ++ mvOsPrintf("ethPort #%d: Warning !!! Finish port in Active state\n", ++ portNo); ++ mvEthPortDisable(pPortHndl); ++ } ++ ++ /* Free all allocated RX queues */ ++ for(queue=0; queuerxQueue[queue].descBuf); ++ } ++ ++ /* Free all allocated TX queues */ ++ for(queue=0; queuetxQueue[queue].descBuf); ++ } ++ ++ /* Free port control structure */ ++ mvOsFree(pPortCtrl); ++ ++ ethPortCtrl[portNo] = NULL; ++} ++ ++/******************************************************************************* ++* mvEthDefaultsSet - Set defaults to the ethernet port ++* ++* DESCRIPTION: ++* This function set default values to the ethernet port. ++* 1) Clear Cause registers and Mask all interrupts ++* 2) Clear all MAC tables ++* 3) Set defaults to all registers ++* 4) Reset all created RX and TX descriptors ring ++* 5) Reset PHY ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet port handler ++* ++* RETURN: MV_STATUS ++* MV_OK - Success, Others - Failure ++* NOTE: ++* This function update all the port configuration except those set ++* Initialy by the OsGlue by MV_ETH_PORT_INIT. ++* This function can be called after portDown to return the port setting ++* to defaults. ++*******************************************************************************/ ++MV_STATUS mvEthDefaultsSet(void* pPortHndl) ++{ ++ int ethPortNo, queue; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ ETH_QUEUE_CTRL* pQueueCtrl; ++ MV_U32 txPrio; ++ MV_U32 portCfgReg, portCfgExtReg, portSerialCtrlReg, portSerialCtrl1Reg, portSdmaCfgReg; ++ MV_BOARD_MAC_SPEED boardMacCfg; ++ ++ ethPortNo = pPortCtrl->portNo; ++ ++ /* Clear Cause registers */ ++ MV_REG_WRITE(ETH_INTR_CAUSE_REG(ethPortNo),0); ++ MV_REG_WRITE(ETH_INTR_CAUSE_EXT_REG(ethPortNo),0); ++ ++ /* Mask all interrupts */ ++ MV_REG_WRITE(ETH_INTR_MASK_REG(ethPortNo),0); ++ MV_REG_WRITE(ETH_INTR_MASK_EXT_REG(ethPortNo),0); ++ ++ portCfgReg = PORT_CONFIG_VALUE; ++ portCfgExtReg = PORT_CONFIG_EXTEND_VALUE; ++ ++ boardMacCfg = mvBoardMacSpeedGet(ethPortNo); ++ ++ if(boardMacCfg == BOARD_MAC_SPEED_100M) ++ { ++ portSerialCtrlReg = PORT_SERIAL_CONTROL_100MB_FORCE_VALUE; ++ } ++ else if(boardMacCfg == BOARD_MAC_SPEED_1000M) ++ { ++ portSerialCtrlReg = PORT_SERIAL_CONTROL_1000MB_FORCE_VALUE; ++ } ++ else ++ { ++ portSerialCtrlReg = PORT_SERIAL_CONTROL_VALUE; ++ } ++ ++ /* build PORT_SDMA_CONFIG_REG */ ++ portSdmaCfgReg = ETH_TX_INTR_COAL_MASK(0); ++ portSdmaCfgReg |= ETH_TX_BURST_SIZE_MASK(ETH_BURST_SIZE_16_64BIT_VALUE); ++ ++#if ( (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WB) || \ ++ (ETHER_DRAM_COHER == MV_CACHE_COHER_HW_WT) ) ++ /* some devices have restricted RX burst size when using HW coherency */ ++ portSdmaCfgReg |= ETH_RX_BURST_SIZE_MASK(ETH_BURST_SIZE_4_64BIT_VALUE); ++#else ++ portSdmaCfgReg |= ETH_RX_BURST_SIZE_MASK(ETH_BURST_SIZE_16_64BIT_VALUE); ++#endif ++ ++#if defined(MV_CPU_BE) ++ /* big endian */ ++# if defined(MV_ARM) ++ portSdmaCfgReg |= (ETH_RX_NO_DATA_SWAP_MASK | ++ ETH_TX_NO_DATA_SWAP_MASK | ++ ETH_DESC_SWAP_MASK); ++# elif defined(MV_PPC) ++ portSdmaCfgReg |= (ETH_RX_DATA_SWAP_MASK | ++ ETH_TX_DATA_SWAP_MASK | ++ ETH_NO_DESC_SWAP_MASK); ++# else ++# error "Giga Ethernet Swap policy is not defined for the CPU_ARCH" ++# endif /* MV_ARM / MV_PPC */ ++ ++#else /* MV_CPU_LE */ ++ /* little endian */ ++ portSdmaCfgReg |= (ETH_RX_NO_DATA_SWAP_MASK | ++ ETH_TX_NO_DATA_SWAP_MASK | ++ ETH_NO_DESC_SWAP_MASK); ++#endif /* MV_CPU_BE / MV_CPU_LE */ ++ ++ pPortCtrl->portRxQueueCmdReg = 0; ++ pPortCtrl->portTxQueueCmdReg = 0; ++ ++#if (MV_ETH_VERSION >= 4) ++ if(pPortCtrl->portConfig.ejpMode == MV_TRUE) ++ { ++ MV_REG_WRITE(ETH_TXQ_CMD_1_REG(ethPortNo), ETH_TX_EJP_ENABLE_MASK); ++ } ++ else ++ { ++ MV_REG_WRITE(ETH_TXQ_CMD_1_REG(ethPortNo), 0) ++ } ++#endif /* (MV_ETH_VERSION >= 4) */ ++ ++ ethSetUcastTable(ethPortNo, -1); ++ mvEthSetSpecialMcastTable(ethPortNo, -1); ++ mvEthSetOtherMcastTable(ethPortNo, -1); ++ ++ portSerialCtrlReg &= ~ETH_MAX_RX_PACKET_SIZE_MASK; ++ ++ portSerialCtrlReg |= mvEthMruGet(pPortCtrl->portConfig.maxRxPktSize); ++ ++ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNo), portSerialCtrlReg); ++ ++ /* Update value of PortConfig register accordingly with all RxQueue types */ ++ pPortCtrl->portConfig.rxArpQ = pPortCtrl->portConfig.rxDefQ; ++ pPortCtrl->portConfig.rxBpduQ = pPortCtrl->portConfig.rxDefQ; ++ pPortCtrl->portConfig.rxTcpQ = pPortCtrl->portConfig.rxDefQ; ++ pPortCtrl->portConfig.rxUdpQ = pPortCtrl->portConfig.rxDefQ; ++ ++ portCfgReg &= ~ETH_DEF_RX_QUEUE_ALL_MASK; ++ portCfgReg |= ETH_DEF_RX_QUEUE_MASK(pPortCtrl->portConfig.rxDefQ); ++ ++ portCfgReg &= ~ETH_DEF_RX_ARP_QUEUE_ALL_MASK; ++ portCfgReg |= ETH_DEF_RX_ARP_QUEUE_MASK(pPortCtrl->portConfig.rxArpQ); ++ ++ portCfgReg &= ~ETH_DEF_RX_BPDU_QUEUE_ALL_MASK; ++ portCfgReg |= ETH_DEF_RX_BPDU_QUEUE_MASK(pPortCtrl->portConfig.rxBpduQ); ++ ++ portCfgReg &= ~ETH_DEF_RX_TCP_QUEUE_ALL_MASK; ++ portCfgReg |= ETH_DEF_RX_TCP_QUEUE_MASK(pPortCtrl->portConfig.rxTcpQ); ++ ++ portCfgReg &= ~ETH_DEF_RX_UDP_QUEUE_ALL_MASK; ++ portCfgReg |= ETH_DEF_RX_UDP_QUEUE_MASK(pPortCtrl->portConfig.rxUdpQ); ++ ++ /* Assignment of Tx CTRP of given queue */ ++ txPrio = 0; ++ ++ for(queue=0; queuetxQueue[queue]; ++ ++ if(pQueueCtrl->pFirstDescr != NULL) ++ { ++ ethResetTxDescRing(pPortCtrl, queue); ++ ++ MV_REG_WRITE(ETH_TXQ_TOKEN_COUNT_REG(ethPortNo, queue), ++ 0x3fffffff); ++ MV_REG_WRITE(ETH_TXQ_TOKEN_CFG_REG(ethPortNo, queue), ++ 0x03ffffff); ++ } ++ else ++ { ++ MV_REG_WRITE(ETH_TXQ_TOKEN_COUNT_REG(ethPortNo, queue), 0x0); ++ MV_REG_WRITE(ETH_TXQ_TOKEN_CFG_REG(ethPortNo, queue), 0x0); ++ } ++ } ++ ++ /* Assignment of Rx CRDP of given queue */ ++ for(queue=0; queueportNo; ++ ++ if( (pPortCtrl->portState != MV_ACTIVE) && ++ (pPortCtrl->portState != MV_PAUSED) ) ++ { ++ mvOsPrintf("ethDrv port%d: Unexpected port state %d\n", ++ ethPortNo, pPortCtrl->portState); ++ return MV_BAD_STATE; ++ } ++ ++ ethPortNo = pPortCtrl->portNo; ++ ++ /* Enable port RX. */ ++ MV_REG_WRITE(ETH_RX_QUEUE_COMMAND_REG(ethPortNo), pPortCtrl->portRxQueueCmdReg); ++ ++ /* Enable port TX. */ ++ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(ethPortNo)) = pPortCtrl->portTxQueueCmdReg; ++ ++ pPortCtrl->portState = MV_ACTIVE; ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* ethPortDown - Stop the Ethernet port activity. ++* ++* DESCRIPTION: ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet port handler ++* ++* RETURN: MV_STATUS ++* MV_OK - Success, Others - Failure. ++* ++* NOTE : used for port link down. ++*******************************************************************************/ ++MV_STATUS mvEthPortDown(void* pEthPortHndl) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; ++ int ethPortNum = pPortCtrl->portNo; ++ unsigned int regData; ++ volatile int uDelay, mDelay; ++ ++ /* Stop Rx port activity. Check port Rx activity. */ ++ regData = (MV_REG_READ(ETH_RX_QUEUE_COMMAND_REG(ethPortNum))) & ETH_RXQ_ENABLE_MASK; ++ if(regData != 0) ++ { ++ /* Issue stop command for active channels only */ ++ MV_REG_WRITE(ETH_RX_QUEUE_COMMAND_REG(ethPortNum), (regData << ETH_RXQ_DISABLE_OFFSET)); ++ } ++ ++ /* Stop Tx port activity. Check port Tx activity. */ ++ regData = (MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(ethPortNum))) & ETH_TXQ_ENABLE_MASK; ++ if(regData != 0) ++ { ++ /* Issue stop command for active channels only */ ++ MV_REG_WRITE(ETH_TX_QUEUE_COMMAND_REG(ethPortNum), ++ (regData << ETH_TXQ_DISABLE_OFFSET) ); ++ } ++ ++ /* Force link down */ ++/* ++ regData = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNum)); ++ regData &= ~(ETH_DO_NOT_FORCE_LINK_FAIL_MASK); ++ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNum), regData); ++*/ ++ /* Wait for all Rx activity to terminate. */ ++ mDelay = 0; ++ do ++ { ++ if(mDelay >= RX_DISABLE_TIMEOUT_MSEC) ++ { ++ mvOsPrintf("ethPort_%d: TIMEOUT for RX stopped !!! rxQueueCmd - 0x08%x\n", ++ ethPortNum, regData); ++ break; ++ } ++ mvOsDelay(1); ++ mDelay++; ++ ++ /* Check port RX Command register that all Rx queues are stopped */ ++ regData = MV_REG_READ(ETH_RX_QUEUE_COMMAND_REG(ethPortNum)); ++ } ++ while(regData & 0xFF); ++ ++ /* Wait for all Tx activity to terminate. */ ++ mDelay = 0; ++ do ++ { ++ if(mDelay >= TX_DISABLE_TIMEOUT_MSEC) ++ { ++ mvOsPrintf("ethPort_%d: TIMEOUT for TX stoped !!! txQueueCmd - 0x08%x\n", ++ ethPortNum, regData); ++ break; ++ } ++ mvOsDelay(1); ++ mDelay++; ++ ++ /* Check port TX Command register that all Tx queues are stopped */ ++ regData = MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(ethPortNum)); ++ } ++ while(regData & 0xFF); ++ ++ /* Double check to Verify that TX FIFO is Empty */ ++ mDelay = 0; ++ while(MV_TRUE) ++ { ++ do ++ { ++ if(mDelay >= TX_FIFO_EMPTY_TIMEOUT_MSEC) ++ { ++ mvOsPrintf("\n ethPort_%d: TIMEOUT for TX FIFO empty !!! portStatus - 0x08%x\n", ++ ethPortNum, regData); ++ break; ++ } ++ mvOsDelay(1); ++ mDelay++; ++ ++ regData = MV_REG_READ(ETH_PORT_STATUS_REG(ethPortNum)); ++ } ++ while( ((regData & ETH_TX_FIFO_EMPTY_MASK) == 0) || ++ ((regData & ETH_TX_IN_PROGRESS_MASK) != 0) ); ++ ++ if(mDelay >= TX_FIFO_EMPTY_TIMEOUT_MSEC) ++ break; ++ ++ /* Double check */ ++ regData = MV_REG_READ(ETH_PORT_STATUS_REG(ethPortNum)); ++ if( ((regData & ETH_TX_FIFO_EMPTY_MASK) != 0) && ++ ((regData & ETH_TX_IN_PROGRESS_MASK) == 0) ) ++ { ++ break; ++ } ++ else ++ mvOsPrintf("ethPort_%d: TX FIFO Empty double check failed. %d msec, portStatus=0x%x\n", ++ ethPortNum, mDelay, regData); ++ } ++ ++ /* Do NOT force link down */ ++/* ++ regData = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNum)); ++ regData |= (ETH_DO_NOT_FORCE_LINK_FAIL_MASK); ++ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNum), regData); ++*/ ++ /* Wait about 2500 tclk cycles */ ++ uDelay = (PORT_DISABLE_WAIT_TCLOCKS/(mvBoardTclkGet()/1000000)); ++ mvOsUDelay(uDelay); ++ ++ pPortCtrl->portState = MV_PAUSED; ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* ethPortEnable - Enable the Ethernet port and Start RX and TX. ++* ++* DESCRIPTION: ++* This routine enable the Ethernet port and Rx and Tx activity: ++* ++* Note: Each Rx and Tx queue descriptor's list must be initialized prior ++* to calling this function (use etherInitTxDescRing for Tx queues and ++* etherInitRxDescRing for Rx queues). ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet port handler ++* ++* RETURN: MV_STATUS ++* MV_OK - Success, Others - Failure. ++* ++* NOTE: main usage is to enable the port after ifconfig up. ++*******************************************************************************/ ++MV_STATUS mvEthPortEnable(void* pEthPortHndl) ++{ ++ int ethPortNo; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; ++ MV_U32 portSerialCtrlReg; ++ ++ ethPortNo = pPortCtrl->portNo; ++ ++ /* Enable port */ ++ portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNo)); ++ portSerialCtrlReg |= (ETH_DO_NOT_FORCE_LINK_FAIL_MASK | ETH_PORT_ENABLE_MASK); ++ ++ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNo), portSerialCtrlReg); ++ ++ mvEthMibCountersClear(pEthPortHndl); ++ ++ pPortCtrl->portState = MV_PAUSED; ++ ++ /* If Link is UP, Start RX and TX traffic */ ++ if( MV_REG_READ( ETH_PORT_STATUS_REG(ethPortNo) ) & ETH_LINK_UP_MASK) ++ return( mvEthPortUp(pEthPortHndl) ); ++ ++ return MV_NOT_READY; ++} ++ ++ ++/******************************************************************************* ++* mvEthPortDisable - Stop RX and TX activities and Disable the Ethernet port. ++* ++* DESCRIPTION: ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet port handler ++* ++* RETURN: MV_STATUS ++* MV_OK - Success, Others - Failure. ++* ++* NOTE: main usage is to disable the port after ifconfig down. ++*******************************************************************************/ ++MV_STATUS mvEthPortDisable(void* pEthPortHndl) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; ++ int ethPortNum = pPortCtrl->portNo; ++ unsigned int regData; ++ volatile int mvDelay; ++ ++ if(pPortCtrl->portState == MV_ACTIVE) ++ { ++ /* Stop RX and TX activities */ ++ mvEthPortDown(pEthPortHndl); ++ } ++ ++ /* Reset the Enable bit in the Serial Control Register */ ++ regData = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(ethPortNum)); ++ regData &= ~(ETH_PORT_ENABLE_MASK); ++ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(ethPortNum), regData); ++ ++ /* Wait about 2500 tclk cycles */ ++ mvDelay = (PORT_DISABLE_WAIT_TCLOCKS*(mvCpuPclkGet()/mvBoardTclkGet())); ++ for(mvDelay; mvDelay>0; mvDelay--); ++ ++ pPortCtrl->portState = MV_IDLE; ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvEthPortForceTxDone - Get next buffer from TX queue in spite of buffer ownership. ++* ++* DESCRIPTION: ++* This routine used to free buffers attached to the Tx ring and should ++* be called only when Giga Ethernet port is Down ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet Port handler. ++* int txQueue - Number of TX queue. ++* ++* OUTPUT: ++* MV_PKT_INFO *pPktInfo - Pointer to packet was sent. ++* ++* RETURN: ++* MV_EMPTY - There is no more buffers in this queue. ++* MV_OK - Buffer detached from the queue and pPktInfo structure ++* filled with relevant information. ++* ++*******************************************************************************/ ++MV_PKT_INFO* mvEthPortForceTxDone(void* pEthPortHndl, int txQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; ++ ETH_QUEUE_CTRL* pQueueCtrl; ++ MV_PKT_INFO* pPktInfo; ++ ETH_TX_DESC* pTxDesc; ++ int port = pPortCtrl->portNo; ++ ++ pQueueCtrl = &pPortCtrl->txQueue[txQueue]; ++ ++ while( (pQueueCtrl->pUsedDescr != pQueueCtrl->pCurrentDescr) || ++ (pQueueCtrl->resource == 0) ) ++ { ++ /* Free next descriptor */ ++ pQueueCtrl->resource++; ++ pTxDesc = (ETH_TX_DESC*)pQueueCtrl->pUsedDescr; ++ ++ /* pPktInfo is available only in descriptors which are last descriptors */ ++ pPktInfo = (MV_PKT_INFO*)pTxDesc->returnInfo; ++ if (pPktInfo) ++ pPktInfo->status = pTxDesc->cmdSts; ++ ++ pTxDesc->cmdSts = 0x0; ++ pTxDesc->returnInfo = 0x0; ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxDesc); ++ ++ pQueueCtrl->pUsedDescr = TX_NEXT_DESC_PTR(pTxDesc, pQueueCtrl); ++ ++ if (pPktInfo) ++ if (pPktInfo->status & ETH_TX_LAST_DESC_MASK) ++ return pPktInfo; ++ } ++ MV_REG_WRITE( ETH_TX_CUR_DESC_PTR_REG(port, txQueue), ++ (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); ++ return NULL; ++} ++ ++ ++ ++/******************************************************************************* ++* mvEthPortForceRx - Get next buffer from RX queue in spite of buffer ownership. ++* ++* DESCRIPTION: ++* This routine used to free buffers attached to the Rx ring and should ++* be called only when Giga Ethernet port is Down ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet Port handler. ++* int rxQueue - Number of Rx queue. ++* ++* OUTPUT: ++* MV_PKT_INFO *pPktInfo - Pointer to received packet. ++* ++* RETURN: ++* MV_EMPTY - There is no more buffers in this queue. ++* MV_OK - Buffer detached from the queue and pBufInfo structure ++* filled with relevant information. ++* ++*******************************************************************************/ ++MV_PKT_INFO* mvEthPortForceRx(void* pEthPortHndl, int rxQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; ++ ETH_QUEUE_CTRL* pQueueCtrl; ++ ETH_RX_DESC* pRxDesc; ++ MV_PKT_INFO* pPktInfo; ++ int port = pPortCtrl->portNo; ++ ++ pQueueCtrl = &pPortCtrl->rxQueue[rxQueue]; ++ ++ if(pQueueCtrl->resource == 0) ++ { ++ MV_REG_WRITE( ETH_RX_CUR_DESC_PTR_REG(port, rxQueue), ++ (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); ++ ++ return NULL; ++ } ++ /* Free next descriptor */ ++ pQueueCtrl->resource--; ++ pRxDesc = (ETH_RX_DESC*)pQueueCtrl->pCurrentDescr; ++ pPktInfo = (MV_PKT_INFO*)pRxDesc->returnInfo; ++ ++ pPktInfo->status = pRxDesc->cmdSts; ++ pRxDesc->cmdSts = 0x0; ++ pRxDesc->returnInfo = 0x0; ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxDesc); ++ ++ pQueueCtrl->pCurrentDescr = RX_NEXT_DESC_PTR(pRxDesc, pQueueCtrl); ++ return pPktInfo; ++} ++ ++ ++/******************************************************************************/ ++/* Port Configuration functions */ ++/******************************************************************************/ ++/******************************************************************************* ++* mvEthMruGet - Get MRU configuration for Max Rx packet size. ++* ++* INPUT: ++* MV_U32 maxRxPktSize - max packet size. ++* ++* RETURN: MV_U32 - MRU configuration. ++* ++*******************************************************************************/ ++static MV_U32 mvEthMruGet(MV_U32 maxRxPktSize) ++{ ++ MV_U32 portSerialCtrlReg = 0; ++ ++ if(maxRxPktSize > 9192) ++ portSerialCtrlReg |= ETH_MAX_RX_PACKET_9700BYTE; ++ else if(maxRxPktSize > 9022) ++ portSerialCtrlReg |= ETH_MAX_RX_PACKET_9192BYTE; ++ else if(maxRxPktSize > 1552) ++ portSerialCtrlReg |= ETH_MAX_RX_PACKET_9022BYTE; ++ else if(maxRxPktSize > 1522) ++ portSerialCtrlReg |= ETH_MAX_RX_PACKET_1552BYTE; ++ else if(maxRxPktSize > 1518) ++ portSerialCtrlReg |= ETH_MAX_RX_PACKET_1522BYTE; ++ else ++ portSerialCtrlReg |= ETH_MAX_RX_PACKET_1518BYTE; ++ ++ return portSerialCtrlReg; ++} ++ ++/******************************************************************************* ++* mvEthRxCoalSet - Sets coalescing interrupt mechanism on RX path ++* ++* DESCRIPTION: ++* This routine sets the RX coalescing interrupt mechanism parameter. ++* This parameter is a timeout counter, that counts in 64 tClk ++* chunks, that when timeout event occurs a maskable interrupt occurs. ++* The parameter is calculated using the tCLK frequency of the ++* MV-64xxx chip, and the required number is in micro seconds. ++* ++* INPUT: ++* void* pPortHndl - Ethernet Port handler. ++* MV_U32 uSec - Number of micro seconds between ++* RX interrupts ++* ++* RETURN: ++* None. ++* ++* COMMENT: ++* 1 sec - TCLK_RATE clocks ++* 1 uSec - TCLK_RATE / 1,000,000 clocks ++* ++* Register Value for N micro seconds - ((N * ( (TCLK_RATE / 1,000,000)) / 64) ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_U32 mvEthRxCoalSet (void* pPortHndl, MV_U32 uSec) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ MV_U32 coal = ((uSec * (mvBoardTclkGet() / 1000000)) / 64); ++ MV_U32 portSdmaCfgReg; ++ ++ portSdmaCfgReg = MV_REG_READ(ETH_SDMA_CONFIG_REG(pPortCtrl->portNo)); ++ portSdmaCfgReg &= ~ETH_RX_INTR_COAL_ALL_MASK; ++ ++ portSdmaCfgReg |= ETH_RX_INTR_COAL_MASK(coal); ++ ++#if (MV_ETH_VERSION >= 2) ++ /* Set additional bit if needed ETH_RX_INTR_COAL_MSB_BIT (25) */ ++ if(ETH_RX_INTR_COAL_MASK(coal) > ETH_RX_INTR_COAL_ALL_MASK) ++ portSdmaCfgReg |= ETH_RX_INTR_COAL_MSB_MASK; ++#endif /* MV_ETH_VERSION >= 2 */ ++ ++ MV_REG_WRITE (ETH_SDMA_CONFIG_REG(pPortCtrl->portNo), portSdmaCfgReg); ++ return coal; ++} ++ ++/******************************************************************************* ++* mvEthTxCoalSet - Sets coalescing interrupt mechanism on TX path ++* ++* DESCRIPTION: ++* This routine sets the TX coalescing interrupt mechanism parameter. ++* This parameter is a timeout counter, that counts in 64 tClk ++* chunks, that when timeout event occurs a maskable interrupt ++* occurs. ++* The parameter is calculated using the tCLK frequency of the ++* MV-64xxx chip, and the required number is in micro seconds. ++* ++* INPUT: ++* void* pPortHndl - Ethernet Port handler. ++* MV_U32 uSec - Number of micro seconds between ++* RX interrupts ++* ++* RETURN: ++* None. ++* ++* COMMENT: ++* 1 sec - TCLK_RATE clocks ++* 1 uSec - TCLK_RATE / 1,000,000 clocks ++* ++* Register Value for N micro seconds - ((N * ( (TCLK_RATE / 1,000,000)) / 64) ++* ++*******************************************************************************/ ++MV_U32 mvEthTxCoalSet(void* pPortHndl, MV_U32 uSec) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ MV_U32 coal = ((uSec * (mvBoardTclkGet() / 1000000)) / 64); ++ MV_U32 regVal; ++ ++ regVal = MV_REG_READ(ETH_TX_FIFO_URGENT_THRESH_REG(pPortCtrl->portNo)); ++ regVal &= ~ETH_TX_INTR_COAL_ALL_MASK; ++ regVal |= ETH_TX_INTR_COAL_MASK(coal); ++ ++ /* Set TX Coalescing mechanism */ ++ MV_REG_WRITE (ETH_TX_FIFO_URGENT_THRESH_REG(pPortCtrl->portNo), regVal); ++ return coal; ++} ++ ++/******************************************************************************* ++* mvEthCoalGet - Gets RX and TX coalescing values in micro seconds ++* ++* DESCRIPTION: ++* This routine gets the RX and TX coalescing interrupt values. ++* The parameter is calculated using the tCLK frequency of the ++* MV-64xxx chip, and the returned numbers are in micro seconds. ++* ++* INPUTs: ++* void* pPortHndl - Ethernet Port handler. ++* ++* OUTPUTs: ++* MV_U32* pRxCoal - Number of micro seconds between RX interrupts ++* MV_U32* pTxCoal - Number of micro seconds between TX interrupts ++* ++* RETURN: ++* MV_STATUS MV_OK - success ++* Others - failure. ++* ++* COMMENT: ++* 1 sec - TCLK_RATE clocks ++* 1 uSec - TCLK_RATE / 1,000,000 clocks ++* ++* Register Value for N micro seconds - ((N * ( (TCLK_RATE / 1,000,000)) / 64) ++* ++*******************************************************************************/ ++MV_STATUS mvEthCoalGet(void* pPortHndl, MV_U32* pRxCoal, MV_U32* pTxCoal) ++{ ++ MV_U32 regVal, coal, usec; ++ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ ++ /* get TX Coalescing */ ++ regVal = MV_REG_READ (ETH_TX_FIFO_URGENT_THRESH_REG(pPortCtrl->portNo)); ++ coal = ((regVal & ETH_TX_INTR_COAL_ALL_MASK) >> ETH_TX_INTR_COAL_OFFSET); ++ ++ usec = (coal * 64) / (mvBoardTclkGet() / 1000000); ++ if(pTxCoal != NULL) ++ *pTxCoal = usec; ++ ++ /* Get RX Coalescing */ ++ regVal = MV_REG_READ(ETH_SDMA_CONFIG_REG(pPortCtrl->portNo)); ++ coal = ((regVal & ETH_RX_INTR_COAL_ALL_MASK) >> ETH_RX_INTR_COAL_OFFSET); ++ ++#if (MV_ETH_VERSION >= 2) ++ if(regVal & ETH_RX_INTR_COAL_MSB_MASK) ++ { ++ /* Add MSB */ ++ coal |= (ETH_RX_INTR_COAL_ALL_MASK + 1); ++ } ++#endif /* MV_ETH_VERSION >= 2 */ ++ ++ usec = (coal * 64) / (mvBoardTclkGet() / 1000000); ++ if(pRxCoal != NULL) ++ *pRxCoal = usec; ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvEthMaxRxSizeSet - ++* ++* DESCRIPTION: ++* Change maximum receive size of the port. This configuration will take place ++* after next call of ethPortSetDefaults() function. ++* ++* INPUT: ++* ++* RETURN: ++*******************************************************************************/ ++MV_STATUS mvEthMaxRxSizeSet(void* pPortHndl, int maxRxSize) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ MV_U32 portSerialCtrlReg; ++ ++ if((maxRxSize < 1518) || (maxRxSize & ~ETH_RX_BUFFER_MASK)) ++ return MV_BAD_PARAM; ++ ++ pPortCtrl->portConfig.maxRxPktSize = maxRxSize; ++ ++ portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(pPortCtrl->portNo)); ++ portSerialCtrlReg &= ~ETH_MAX_RX_PACKET_SIZE_MASK; ++ portSerialCtrlReg |= mvEthMruGet(pPortCtrl->portConfig.maxRxPktSize); ++ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(pPortCtrl->portNo), portSerialCtrlReg); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************/ ++/* MAC Filtering functions */ ++/******************************************************************************/ ++ ++/******************************************************************************* ++* mvEthRxFilterModeSet - Configure Fitering mode of Ethernet port ++* ++* DESCRIPTION: ++* This routine used to free buffers attached to the Rx ring and should ++* be called only when Giga Ethernet port is Down ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet Port handler. ++* MV_BOOL isPromisc - Promiscous mode ++* MV_TRUE - accept all Broadcast, Multicast ++* and Unicast packets ++* MV_FALSE - accept all Broadcast, ++* specially added Multicast and ++* single Unicast packets ++* ++* RETURN: MV_STATUS MV_OK - Success, Other - Failure ++* ++*******************************************************************************/ ++MV_STATUS mvEthRxFilterModeSet(void* pEthPortHndl, MV_BOOL isPromisc) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; ++ int queue; ++ MV_U32 portCfgReg; ++ ++ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); ++ /* Set / Clear UPM bit in port configuration register */ ++ if(isPromisc) ++ { ++ /* Accept all multicast packets to RX default queue */ ++ queue = pPortCtrl->portConfig.rxDefQ; ++ portCfgReg |= ETH_UNICAST_PROMISCUOUS_MODE_MASK; ++ memset(pPortCtrl->mcastCount, 1, sizeof(pPortCtrl->mcastCount)); ++ MV_REG_WRITE(ETH_MAC_ADDR_LOW_REG(pPortCtrl->portNo),0xFFFF); ++ MV_REG_WRITE(ETH_MAC_ADDR_HIGH_REG(pPortCtrl->portNo),0xFFFFFFFF); ++ } ++ else ++ { ++ /* Reject all Multicast addresses */ ++ queue = -1; ++ portCfgReg &= ~ETH_UNICAST_PROMISCUOUS_MODE_MASK; ++ /* Clear all mcastCount */ ++ memset(pPortCtrl->mcastCount, 0, sizeof(pPortCtrl->mcastCount)); ++ } ++ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); ++ ++ /* Set Special Multicast and Other Multicast tables */ ++ mvEthSetSpecialMcastTable(pPortCtrl->portNo, queue); ++ mvEthSetOtherMcastTable(pPortCtrl->portNo, queue); ++ ethSetUcastTable(pPortCtrl->portNo, queue); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvEthMacAddrSet - This function Set the port Unicast address. ++* ++* DESCRIPTION: ++* This function Set the port Ethernet MAC address. This address ++* will be used to send Pause frames if enabled. Packets with this ++* address will be accepted and dispatched to default RX queue ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet port handler. ++* char* pAddr - Address to be set ++* ++* RETURN: MV_STATUS ++* MV_OK - Success, Other - Faulure ++* ++*******************************************************************************/ ++MV_STATUS mvEthMacAddrSet(void* pPortHndl, unsigned char *pAddr, int queue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ unsigned int macH; ++ unsigned int macL; ++ ++ if(queue >= MV_ETH_RX_Q_NUM) ++ { ++ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", queue); ++ return MV_BAD_PARAM; ++ } ++ ++ if(queue != -1) ++ { ++ macL = (pAddr[4] << 8) | (pAddr[5]); ++ macH = (pAddr[0] << 24)| (pAddr[1] << 16) | ++ (pAddr[2] << 8) | (pAddr[3] << 0); ++ ++ MV_REG_WRITE(ETH_MAC_ADDR_LOW_REG(pPortCtrl->portNo), macL); ++ MV_REG_WRITE(ETH_MAC_ADDR_HIGH_REG(pPortCtrl->portNo), macH); ++ } ++ ++ /* Accept frames of this address */ ++ ethSetUcastAddr(pPortCtrl->portNo, pAddr[5], queue); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvEthMacAddrGet - This function returns the port Unicast address. ++* ++* DESCRIPTION: ++* This function returns the port Ethernet MAC address. ++* ++* INPUT: ++* int portNo - Ethernet port number. ++* char* pAddr - Pointer where address will be written to ++* ++* RETURN: MV_STATUS ++* MV_OK - Success, Other - Faulure ++* ++*******************************************************************************/ ++MV_STATUS mvEthMacAddrGet(int portNo, unsigned char *pAddr) ++{ ++ unsigned int macH; ++ unsigned int macL; ++ ++ if(pAddr == NULL) ++ { ++ mvOsPrintf("mvEthMacAddrGet: NULL pointer.\n"); ++ return MV_BAD_PARAM; ++ } ++ ++ macH = MV_REG_READ(ETH_MAC_ADDR_HIGH_REG(portNo)); ++ macL = MV_REG_READ(ETH_MAC_ADDR_LOW_REG(portNo)); ++ pAddr[0] = (macH >> 24) & 0xff; ++ pAddr[1] = (macH >> 16) & 0xff; ++ pAddr[2] = (macH >> 8) & 0xff; ++ pAddr[3] = macH & 0xff; ++ pAddr[4] = (macL >> 8) & 0xff; ++ pAddr[5] = macL & 0xff; ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvEthMcastCrc8Get - Calculate CRC8 of MAC address. ++* ++* DESCRIPTION: ++* ++* INPUT: ++* MV_U8* pAddr - Address to calculate CRC-8 ++* ++* RETURN: MV_U8 - CRC-8 of this MAC address ++* ++*******************************************************************************/ ++MV_U8 mvEthMcastCrc8Get(MV_U8* pAddr) ++{ ++ unsigned int macH; ++ unsigned int macL; ++ int macArray[48]; ++ int crc[8]; ++ int i; ++ unsigned char crcResult = 0; ++ ++ /* Calculate CRC-8 out of the given address */ ++ macH = (pAddr[0] << 8) | (pAddr[1]); ++ macL = (pAddr[2] << 24)| (pAddr[3] << 16) | ++ (pAddr[4] << 8) | (pAddr[5] << 0); ++ ++ for(i=0; i<32; i++) ++ macArray[i] = (macL >> i) & 0x1; ++ ++ for(i=32; i<48; i++) ++ macArray[i] = (macH >> (i - 32)) & 0x1; ++ ++ crc[0] = macArray[45] ^ macArray[43] ^ macArray[40] ^ macArray[39] ^ ++ macArray[35] ^ macArray[34] ^ macArray[31] ^ macArray[30] ^ ++ macArray[28] ^ macArray[23] ^ macArray[21] ^ macArray[19] ^ ++ macArray[18] ^ macArray[16] ^ macArray[14] ^ macArray[12] ^ ++ macArray[8] ^ macArray[7] ^ macArray[6] ^ macArray[0]; ++ ++ crc[1] = macArray[46] ^ macArray[45] ^ macArray[44] ^ macArray[43] ^ ++ macArray[41] ^ macArray[39] ^ macArray[36] ^ macArray[34] ^ ++ macArray[32] ^ macArray[30] ^ macArray[29] ^ macArray[28] ^ ++ macArray[24] ^ macArray[23] ^ macArray[22] ^ macArray[21] ^ ++ macArray[20] ^ macArray[18] ^ macArray[17] ^ macArray[16] ^ ++ macArray[15] ^ macArray[14] ^ macArray[13] ^ macArray[12] ^ ++ macArray[9] ^ macArray[6] ^ macArray[1] ^ macArray[0]; ++ ++ crc[2] = macArray[47] ^ macArray[46] ^ macArray[44] ^ macArray[43] ^ ++ macArray[42] ^ macArray[39] ^ macArray[37] ^ macArray[34] ^ ++ macArray[33] ^ macArray[29] ^ macArray[28] ^ macArray[25] ^ ++ macArray[24] ^ macArray[22] ^ macArray[17] ^ macArray[15] ^ ++ macArray[13] ^ macArray[12] ^ macArray[10] ^ macArray[8] ^ ++ macArray[6] ^ macArray[2] ^ macArray[1] ^ macArray[0]; ++ ++ crc[3] = macArray[47] ^ macArray[45] ^ macArray[44] ^ macArray[43] ^ ++ macArray[40] ^ macArray[38] ^ macArray[35] ^ macArray[34] ^ ++ macArray[30] ^ macArray[29] ^ macArray[26] ^ macArray[25] ^ ++ macArray[23] ^ macArray[18] ^ macArray[16] ^ macArray[14] ^ ++ macArray[13] ^ macArray[11] ^ macArray[9] ^ macArray[7] ^ ++ macArray[3] ^ macArray[2] ^ macArray[1]; ++ ++ crc[4] = macArray[46] ^ macArray[45] ^ macArray[44] ^ macArray[41] ^ ++ macArray[39] ^ macArray[36] ^ macArray[35] ^ macArray[31] ^ ++ macArray[30] ^ macArray[27] ^ macArray[26] ^ macArray[24] ^ ++ macArray[19] ^ macArray[17] ^ macArray[15] ^ macArray[14] ^ ++ macArray[12] ^ macArray[10] ^ macArray[8] ^ macArray[4] ^ ++ macArray[3] ^ macArray[2]; ++ ++ crc[5] = macArray[47] ^ macArray[46] ^ macArray[45] ^ macArray[42] ^ ++ macArray[40] ^ macArray[37] ^ macArray[36] ^ macArray[32] ^ ++ macArray[31] ^ macArray[28] ^ macArray[27] ^ macArray[25] ^ ++ macArray[20] ^ macArray[18] ^ macArray[16] ^ macArray[15] ^ ++ macArray[13] ^ macArray[11] ^ macArray[9] ^ macArray[5] ^ ++ macArray[4] ^ macArray[3]; ++ ++ crc[6] = macArray[47] ^ macArray[46] ^ macArray[43] ^ macArray[41] ^ ++ macArray[38] ^ macArray[37] ^ macArray[33] ^ macArray[32] ^ ++ macArray[29] ^ macArray[28] ^ macArray[26] ^ macArray[21] ^ ++ macArray[19] ^ macArray[17] ^ macArray[16] ^ macArray[14] ^ ++ macArray[12] ^ macArray[10] ^ macArray[6] ^ macArray[5] ^ ++ macArray[4]; ++ ++ crc[7] = macArray[47] ^ macArray[44] ^ macArray[42] ^ macArray[39] ^ ++ macArray[38] ^ macArray[34] ^ macArray[33] ^ macArray[30] ^ ++ macArray[29] ^ macArray[27] ^ macArray[22] ^ macArray[20] ^ ++ macArray[18] ^ macArray[17] ^ macArray[15] ^ macArray[13] ^ ++ macArray[11] ^ macArray[7] ^ macArray[6] ^ macArray[5]; ++ ++ for(i=0; i<8; i++) ++ crcResult = crcResult | (crc[i] << i); ++ ++ return crcResult; ++} ++/******************************************************************************* ++* mvEthMcastAddrSet - Multicast address settings. ++* ++* DESCRIPTION: ++* This API controls the MV device MAC multicast support. ++* The MV device supports multicast using two tables: ++* 1) Special Multicast Table for MAC addresses of the form ++* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). ++* The MAC DA[7:0] bits are used as a pointer to the Special Multicast ++* Table entries in the DA-Filter table. ++* In this case, the function calls ethPortSmcAddr() routine to set the ++* Special Multicast Table. ++* 2) Other Multicast Table for multicast of another type. A CRC-8bit ++* is used as an index to the Other Multicast Table entries in the ++* DA-Filter table. ++* In this case, the function calculates the CRC-8bit value and calls ++* ethPortOmcAddr() routine to set the Other Multicast Table. ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet port handler. ++* MV_U8* pAddr - Address to be set ++* int queue - RX queue to capture all packets with this ++* Multicast MAC address. ++* -1 means delete this Multicast address. ++* ++* RETURN: MV_STATUS ++* MV_TRUE - Success, Other - Failure ++* ++*******************************************************************************/ ++MV_STATUS mvEthMcastAddrSet(void* pPortHndl, MV_U8 *pAddr, int queue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ unsigned char crcResult = 0; ++ ++ if(queue >= MV_ETH_RX_Q_NUM) ++ { ++ mvOsPrintf("ethPort %d: RX queue #%d is out of range\n", ++ pPortCtrl->portNo, queue); ++ return MV_BAD_PARAM; ++ } ++ ++ if((pAddr[0] == 0x01) && ++ (pAddr[1] == 0x00) && ++ (pAddr[2] == 0x5E) && ++ (pAddr[3] == 0x00) && ++ (pAddr[4] == 0x00)) ++ { ++ ethSetSpecialMcastAddr(pPortCtrl->portNo, pAddr[5], queue); ++ } ++ else ++ { ++ crcResult = mvEthMcastCrc8Get(pAddr); ++ ++ /* Check Add counter for this CRC value */ ++ if(queue == -1) ++ { ++ if(pPortCtrl->mcastCount[crcResult] == 0) ++ { ++ mvOsPrintf("ethPort #%d: No valid Mcast for crc8=0x%02x\n", ++ pPortCtrl->portNo, (unsigned)crcResult); ++ return MV_NO_SUCH; ++ } ++ ++ pPortCtrl->mcastCount[crcResult]--; ++ if(pPortCtrl->mcastCount[crcResult] != 0) ++ { ++ mvOsPrintf("ethPort #%d: After delete there are %d valid Mcast for crc8=0x%02x\n", ++ pPortCtrl->portNo, pPortCtrl->mcastCount[crcResult], ++ (unsigned)crcResult); ++ return MV_NO_CHANGE; ++ } ++ } ++ else ++ { ++ pPortCtrl->mcastCount[crcResult]++; ++ if(pPortCtrl->mcastCount[crcResult] > 1) ++ { ++ mvOsPrintf("ethPort #%d: Valid Mcast for crc8=0x%02x already exists\n", ++ pPortCtrl->portNo, (unsigned)crcResult); ++ return MV_NO_CHANGE; ++ } ++ } ++ ethSetOtherMcastAddr(pPortCtrl->portNo, crcResult, queue); ++ } ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* ethSetUcastTable - Unicast address settings. ++* ++* DESCRIPTION: ++* Set all entries in the Unicast MAC Table queue==-1 means reject all ++* INPUT: ++* ++* RETURN: ++* ++*******************************************************************************/ ++static void ethSetUcastTable(int portNo, int queue) ++{ ++ int offset; ++ MV_U32 regValue; ++ ++ if(queue == -1) ++ { ++ regValue = 0; ++ } ++ else ++ { ++ regValue = (((0x01 | (queue<<1)) << 0) | ++ ((0x01 | (queue<<1)) << 8) | ++ ((0x01 | (queue<<1)) << 16) | ++ ((0x01 | (queue<<1)) << 24)); ++ } ++ ++ for (offset=0; offset<=0xC; offset+=4) ++ MV_REG_WRITE((ETH_DA_FILTER_UCAST_BASE(portNo) + offset), regValue); ++} ++ ++/******************************************************************************* ++* mvEthSetSpecialMcastTable - Special Multicast address settings. ++* ++* DESCRIPTION: ++* Set all entries to the Special Multicast MAC Table. queue==-1 means reject all ++* INPUT: ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_VOID mvEthSetSpecialMcastTable(int portNo, int queue) ++{ ++ int offset; ++ MV_U32 regValue; ++ ++ if(queue == -1) ++ { ++ regValue = 0; ++ } ++ else ++ { ++ regValue = (((0x01 | (queue<<1)) << 0) | ++ ((0x01 | (queue<<1)) << 8) | ++ ((0x01 | (queue<<1)) << 16) | ++ ((0x01 | (queue<<1)) << 24)); ++ } ++ ++ for (offset=0; offset<=0xFC; offset+=4) ++ { ++ MV_REG_WRITE((ETH_DA_FILTER_SPEC_MCAST_BASE(portNo) + ++ offset), regValue); ++ } ++} ++ ++/******************************************************************************* ++* mvEthSetOtherMcastTable - Other Multicast address settings. ++* ++* DESCRIPTION: ++* Set all entries to the Other Multicast MAC Table. queue==-1 means reject all ++* INPUT: ++* ++* RETURN: ++* ++*******************************************************************************/ ++MV_VOID mvEthSetOtherMcastTable(int portNo, int queue) ++{ ++ int offset; ++ MV_U32 regValue; ++ ++ if(queue == -1) ++ { ++ regValue = 0; ++ } ++ else ++ { ++ regValue = (((0x01 | (queue<<1)) << 0) | ++ ((0x01 | (queue<<1)) << 8) | ++ ((0x01 | (queue<<1)) << 16) | ++ ((0x01 | (queue<<1)) << 24)); ++ } ++ ++ for (offset=0; offset<=0xFC; offset+=4) ++ { ++ MV_REG_WRITE((ETH_DA_FILTER_OTH_MCAST_BASE(portNo) + ++ offset), regValue); ++ } ++} ++ ++/******************************************************************************* ++* ethSetUcastAddr - This function Set the port unicast address table ++* ++* DESCRIPTION: ++* This function locates the proper entry in the Unicast table for the ++* specified MAC nibble and sets its properties according to function ++* parameters. ++* ++* INPUT: ++* int ethPortNum - Port number. ++* MV_U8 lastNibble - Unicast MAC Address last nibble. ++* int queue - Rx queue number for this MAC address. ++* value "-1" means remove address ++* ++* OUTPUT: ++* This function add/removes MAC addresses from the port unicast address ++* table. ++* ++* RETURN: ++* MV_TRUE is output succeeded. ++* MV_FALSE if option parameter is invalid. ++* ++*******************************************************************************/ ++static MV_BOOL ethSetUcastAddr(int portNo, MV_U8 lastNibble, int queue) ++{ ++ unsigned int unicastReg; ++ unsigned int tblOffset; ++ unsigned int regOffset; ++ ++ /* Locate the Unicast table entry */ ++ lastNibble = (0xf & lastNibble); ++ tblOffset = (lastNibble / 4) * 4; /* Register offset from unicast table base*/ ++ regOffset = lastNibble % 4; /* Entry offset within the above register */ ++ ++ ++ unicastReg = MV_REG_READ( (ETH_DA_FILTER_UCAST_BASE(portNo) + ++ tblOffset)); ++ ++ ++ if(queue == -1) ++ { ++ /* Clear accepts frame bit at specified unicast DA table entry */ ++ unicastReg &= ~(0xFF << (8*regOffset)); ++ } ++ else ++ { ++ unicastReg &= ~(0xFF << (8*regOffset)); ++ unicastReg |= ((0x01 | (queue<<1)) << (8*regOffset)); ++ } ++ MV_REG_WRITE( (ETH_DA_FILTER_UCAST_BASE(portNo) + tblOffset), ++ unicastReg); ++ ++ return MV_TRUE; ++} ++ ++/******************************************************************************* ++* ethSetSpecialMcastAddr - Special Multicast address settings. ++* ++* DESCRIPTION: ++* This routine controls the MV device special MAC multicast support. ++* The Special Multicast Table for MAC addresses supports MAC of the form ++* 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). ++* The MAC DA[7:0] bits are used as a pointer to the Special Multicast ++* Table entries in the DA-Filter table. ++* This function set the Special Multicast Table appropriate entry ++* according to the argument given. ++* ++* INPUT: ++* int ethPortNum Port number. ++* unsigned char mcByte Multicast addr last byte (MAC DA[7:0] bits). ++* int queue Rx queue number for this MAC address. ++* int option 0 = Add, 1 = remove address. ++* ++* OUTPUT: ++* See description. ++* ++* RETURN: ++* MV_TRUE is output succeeded. ++* MV_FALSE if option parameter is invalid. ++* ++*******************************************************************************/ ++static MV_BOOL ethSetSpecialMcastAddr(int ethPortNum, MV_U8 lastByte, int queue) ++{ ++ unsigned int smcTableReg; ++ unsigned int tblOffset; ++ unsigned int regOffset; ++ ++ /* Locate the SMC table entry */ ++ tblOffset = (lastByte / 4); /* Register offset from SMC table base */ ++ regOffset = lastByte % 4; /* Entry offset within the above register */ ++ ++ smcTableReg = MV_REG_READ((ETH_DA_FILTER_SPEC_MCAST_BASE(ethPortNum) + tblOffset*4)); ++ ++ if(queue == -1) ++ { ++ /* Clear accepts frame bit at specified Special DA table entry */ ++ smcTableReg &= ~(0xFF << (8 * regOffset)); ++ } ++ else ++ { ++ smcTableReg &= ~(0xFF << (8 * regOffset)); ++ smcTableReg |= ((0x01 | (queue<<1)) << (8 * regOffset)); ++ } ++ MV_REG_WRITE((ETH_DA_FILTER_SPEC_MCAST_BASE(ethPortNum) + ++ tblOffset*4), smcTableReg); ++ ++ return MV_TRUE; ++} ++ ++/******************************************************************************* ++* ethSetOtherMcastAddr - Multicast address settings. ++* ++* DESCRIPTION: ++* This routine controls the MV device Other MAC multicast support. ++* The Other Multicast Table is used for multicast of another type. ++* A CRC-8bit is used as an index to the Other Multicast Table entries ++* in the DA-Filter table. ++* The function gets the CRC-8bit value from the calling routine and ++* set the Other Multicast Table appropriate entry according to the ++* CRC-8 argument given. ++* ++* INPUT: ++* int ethPortNum Port number. ++* MV_U8 crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1). ++* int queue Rx queue number for this MAC address. ++* ++* OUTPUT: ++* See description. ++* ++* RETURN: ++* MV_TRUE is output succeeded. ++* MV_FALSE if option parameter is invalid. ++* ++*******************************************************************************/ ++static MV_BOOL ethSetOtherMcastAddr(int ethPortNum, MV_U8 crc8, int queue) ++{ ++ unsigned int omcTableReg; ++ unsigned int tblOffset; ++ unsigned int regOffset; ++ ++ /* Locate the OMC table entry */ ++ tblOffset = (crc8 / 4) * 4; /* Register offset from OMC table base */ ++ regOffset = crc8 % 4; /* Entry offset within the above register */ ++ ++ omcTableReg = MV_REG_READ( ++ (ETH_DA_FILTER_OTH_MCAST_BASE(ethPortNum) + tblOffset)); ++ ++ if(queue == -1) ++ { ++ /* Clear accepts frame bit at specified Other DA table entry */ ++ omcTableReg &= ~(0xFF << (8 * regOffset)); ++ } ++ else ++ { ++ omcTableReg &= ~(0xFF << (8 * regOffset)); ++ omcTableReg |= ((0x01 | (queue<<1)) << (8 * regOffset)); ++ } ++ ++ MV_REG_WRITE((ETH_DA_FILTER_OTH_MCAST_BASE(ethPortNum) + tblOffset), ++ omcTableReg); ++ ++ return MV_TRUE; ++} ++ ++ ++/******************************************************************************/ ++/* MIB Counters functions */ ++/******************************************************************************/ ++ ++ ++/******************************************************************************* ++* mvEthMibCounterRead - Read a MIB counter ++* ++* DESCRIPTION: ++* This function reads a MIB counter of a specific ethernet port. ++* NOTE - Read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW or ++* ETH_MIB_GOOD_OCTETS_SENT_LOW counters will return 64 bits value, ++* so pHigh32 pointer should not be NULL in this case. ++* ++* INPUT: ++* int ethPortNum - Ethernet Port number. ++* unsigned int mibOffset - MIB counter offset. ++* ++* OUTPUT: ++* MV_U32* pHigh32 - pointer to place where 32 most significant bits ++* of the counter will be stored. ++* ++* RETURN: ++* 32 low sgnificant bits of MIB counter value. ++* ++*******************************************************************************/ ++MV_U32 mvEthMibCounterRead(void* pPortHandle, unsigned int mibOffset, ++ MV_U32* pHigh32) ++{ ++ int portNo; ++ MV_U32 valLow32, valHigh32; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ ++ portNo = pPortCtrl->portNo; ++ ++ valLow32 = MV_REG_READ(ETH_MIB_COUNTERS_BASE(portNo) + mibOffset); ++ ++ /* Implement FEr ETH. Erroneous Value when Reading the Upper 32-bits */ ++ /* of a 64-bit MIB Counter. */ ++ if( (mibOffset == ETH_MIB_GOOD_OCTETS_RECEIVED_LOW) || ++ (mibOffset == ETH_MIB_GOOD_OCTETS_SENT_LOW) ) ++ { ++ valHigh32 = MV_REG_READ(ETH_MIB_COUNTERS_BASE(portNo) + mibOffset + 4); ++ if(pHigh32 != NULL) ++ *pHigh32 = valHigh32; ++ } ++ return valLow32; ++} ++ ++/******************************************************************************* ++* mvEthMibCountersClear - Clear all MIB counters ++* ++* DESCRIPTION: ++* This function clears all MIB counters ++* ++* INPUT: ++* int ethPortNum - Ethernet Port number. ++* ++* ++* RETURN: void ++* ++*******************************************************************************/ ++void mvEthMibCountersClear(void* pPortHandle) ++{ ++ int i, portNo; ++ unsigned int dummy; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ ++ portNo = pPortCtrl->portNo; ++ ++ /* Perform dummy reads from MIB counters */ ++ for(i=ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i 0xFF) ++ { ++ mvOsPrintf("eth_%d: tos=0x%x is out of range\n", pPortCtrl->portNo, tos); ++ return -1; ++ } ++ regIdx = mvOsDivide(tos>>2, 10); ++ regOffs = mvOsReminder(tos>>2, 10); ++ ++ regValue = MV_REG_READ(ETH_DIFF_SERV_PRIO_REG(pPortCtrl->portNo, regIdx) ); ++ rxq = (regValue >> (regOffs*3)); ++ rxq &= 0x7; ++ ++ return rxq; ++} ++ ++/******************************************************************************* ++* mvEthTosToRxqSet - Map packets with special TOS value to special RX queue ++* ++* DESCRIPTION: ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* int tos - TOS value in the IP header of the packet ++* int rxq - RX Queue for packets with the configured TOS value ++* Negative value (-1) means no special processing for these packets, ++* so they will be processed as regular packets. ++* ++* RETURN: MV_STATUS ++*******************************************************************************/ ++MV_STATUS mvEthTosToRxqSet(void* pPortHandle, int tos, int rxq) ++{ ++ MV_U32 regValue; ++ int regIdx, regOffs; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ ++ if( (rxq < 0) || (rxq >= MV_ETH_RX_Q_NUM) ) ++ { ++ mvOsPrintf("eth_%d: RX queue #%d is out of range\n", pPortCtrl->portNo, rxq); ++ return MV_BAD_PARAM; ++ } ++ if(tos > 0xFF) ++ { ++ mvOsPrintf("eth_%d: tos=0x%x is out of range\n", pPortCtrl->portNo, tos); ++ return MV_BAD_PARAM; ++ } ++ regIdx = mvOsDivide(tos>>2, 10); ++ regOffs = mvOsReminder(tos>>2, 10); ++ ++ regValue = MV_REG_READ(ETH_DIFF_SERV_PRIO_REG(pPortCtrl->portNo, regIdx) ); ++ regValue &= ~(0x7 << (regOffs*3)); ++ regValue |= (rxq << (regOffs*3)); ++ ++ MV_REG_WRITE(ETH_DIFF_SERV_PRIO_REG(pPortCtrl->portNo, regIdx), regValue); ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvEthVlanPrioRxQueue - Configure RX queue to capture VLAN tagged packets with ++* special priority bits [0-2] ++* ++* DESCRIPTION: ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* int bpduQueue - Special queue to capture VLAN tagged packets with special ++* priority. ++* Negative value (-1) means no special processing for these packets, ++* so they will be processed as regular packets. ++* ++* RETURN: MV_STATUS ++* MV_OK - Success ++* MV_FAIL - Failed. ++* ++*******************************************************************************/ ++MV_STATUS mvEthVlanPrioRxQueue(void* pPortHandle, int vlanPrio, int vlanPrioQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ MV_U32 vlanPrioReg; ++ ++ if(vlanPrioQueue >= MV_ETH_RX_Q_NUM) ++ { ++ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", vlanPrioQueue); ++ return MV_BAD_PARAM; ++ } ++ if(vlanPrio >= 8) ++ { ++ mvOsPrintf("ethDrv: vlanPrio=%d is out of range\n", vlanPrio); ++ return MV_BAD_PARAM; ++ } ++ ++ vlanPrioReg = MV_REG_READ(ETH_VLAN_TAG_TO_PRIO_REG(pPortCtrl->portNo)); ++ vlanPrioReg &= ~(0x7 << (vlanPrio*3)); ++ vlanPrioReg |= (vlanPrioQueue << (vlanPrio*3)); ++ MV_REG_WRITE(ETH_VLAN_TAG_TO_PRIO_REG(pPortCtrl->portNo), vlanPrioReg); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvEthBpduRxQueue - Configure RX queue to capture BPDU packets. ++* ++* DESCRIPTION: ++* This function defines processing of BPDU packets. ++* BPDU packets can be accepted and captured to one of RX queues ++* or can be processing as regular Multicast packets. ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* int bpduQueue - Special queue to capture BPDU packets (DA is equal to ++* 01-80-C2-00-00-00 through 01-80-C2-00-00-FF, ++* except for the Flow-Control Pause packets). ++* Negative value (-1) means no special processing for BPDU, ++* packets so they will be processed as regular Multicast packets. ++* ++* RETURN: MV_STATUS ++* MV_OK - Success ++* MV_FAIL - Failed. ++* ++*******************************************************************************/ ++MV_STATUS mvEthBpduRxQueue(void* pPortHandle, int bpduQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ MV_U32 portCfgReg; ++ MV_U32 portCfgExtReg; ++ ++ if(bpduQueue >= MV_ETH_RX_Q_NUM) ++ { ++ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", bpduQueue); ++ return MV_BAD_PARAM; ++ } ++ ++ portCfgExtReg = MV_REG_READ(ETH_PORT_CONFIG_EXTEND_REG(pPortCtrl->portNo)); ++ ++ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); ++ if(bpduQueue >= 0) ++ { ++ pPortCtrl->portConfig.rxBpduQ = bpduQueue; ++ ++ portCfgReg &= ~ETH_DEF_RX_BPDU_QUEUE_ALL_MASK; ++ portCfgReg |= ETH_DEF_RX_BPDU_QUEUE_MASK(pPortCtrl->portConfig.rxBpduQ); ++ ++ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); ++ ++ portCfgExtReg |= ETH_CAPTURE_SPAN_BPDU_ENABLE_MASK; ++ } ++ else ++ { ++ pPortCtrl->portConfig.rxBpduQ = -1; ++ /* no special processing for BPDU packets */ ++ portCfgExtReg &= (~ETH_CAPTURE_SPAN_BPDU_ENABLE_MASK); ++ } ++ ++ MV_REG_WRITE(ETH_PORT_CONFIG_EXTEND_REG(pPortCtrl->portNo), portCfgExtReg); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvEthArpRxQueue - Configure RX queue to capture ARP packets. ++* ++* DESCRIPTION: ++* This function defines processing of ARP (type=0x0806) packets. ++* ARP packets can be accepted and captured to one of RX queues ++* or can be processed as other Broadcast packets. ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* int arpQueue - Special queue to capture ARP packets (type=0x806). ++* Negative value (-1) means discard ARP packets ++* ++* RETURN: MV_STATUS ++* MV_OK - Success ++* MV_FAIL - Failed. ++* ++*******************************************************************************/ ++MV_STATUS mvEthArpRxQueue(void* pPortHandle, int arpQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ MV_U32 portCfgReg; ++ ++ if(arpQueue >= MV_ETH_RX_Q_NUM) ++ { ++ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", arpQueue); ++ return MV_BAD_PARAM; ++ } ++ ++ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); ++ ++ if(arpQueue >= 0) ++ { ++ pPortCtrl->portConfig.rxArpQ = arpQueue; ++ portCfgReg &= ~ETH_DEF_RX_ARP_QUEUE_ALL_MASK; ++ portCfgReg |= ETH_DEF_RX_ARP_QUEUE_MASK(pPortCtrl->portConfig.rxArpQ); ++ ++ portCfgReg &= (~ETH_REJECT_ARP_BCAST_MASK); ++ } ++ else ++ { ++ pPortCtrl->portConfig.rxArpQ = -1; ++ portCfgReg |= ETH_REJECT_ARP_BCAST_MASK; ++ } ++ ++ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvEthTcpRxQueue - Configure RX queue to capture TCP packets. ++* ++* DESCRIPTION: ++* This function defines processing of TCP packets. ++* TCP packets can be accepted and captured to one of RX queues ++* or can be processed as regular Unicast packets. ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* int tcpQueue - Special queue to capture TCP packets. Value "-1" ++* means no special processing for TCP packets, ++* so they will be processed as regular ++* ++* RETURN: MV_STATUS ++* MV_OK - Success ++* MV_FAIL - Failed. ++* ++*******************************************************************************/ ++MV_STATUS mvEthTcpRxQueue(void* pPortHandle, int tcpQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ MV_U32 portCfgReg; ++ ++ if(tcpQueue >= MV_ETH_RX_Q_NUM) ++ { ++ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", tcpQueue); ++ return MV_BAD_PARAM; ++ } ++ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); ++ ++ if(tcpQueue >= 0) ++ { ++ pPortCtrl->portConfig.rxTcpQ = tcpQueue; ++ portCfgReg &= ~ETH_DEF_RX_TCP_QUEUE_ALL_MASK; ++ portCfgReg |= ETH_DEF_RX_TCP_QUEUE_MASK(pPortCtrl->portConfig.rxTcpQ); ++ ++ portCfgReg |= ETH_CAPTURE_TCP_FRAMES_ENABLE_MASK; ++ } ++ else ++ { ++ pPortCtrl->portConfig.rxTcpQ = -1; ++ portCfgReg &= (~ETH_CAPTURE_TCP_FRAMES_ENABLE_MASK); ++ } ++ ++ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvEthUdpRxQueue - Configure RX queue to capture UDP packets. ++* ++* DESCRIPTION: ++* This function defines processing of UDP packets. ++* TCP packets can be accepted and captured to one of RX queues ++* or can be processed as regular Unicast packets. ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* int udpQueue - Special queue to capture UDP packets. Value "-1" ++* means no special processing for UDP packets, ++* so they will be processed as regular ++* ++* RETURN: MV_STATUS ++* MV_OK - Success ++* MV_FAIL - Failed. ++* ++*******************************************************************************/ ++MV_STATUS mvEthUdpRxQueue(void* pPortHandle, int udpQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ MV_U32 portCfgReg; ++ ++ if(udpQueue >= MV_ETH_RX_Q_NUM) ++ { ++ mvOsPrintf("ethDrv: RX queue #%d is out of range\n", udpQueue); ++ return MV_BAD_PARAM; ++ } ++ ++ portCfgReg = MV_REG_READ(ETH_PORT_CONFIG_REG(pPortCtrl->portNo)); ++ ++ if(udpQueue >= 0) ++ { ++ pPortCtrl->portConfig.rxUdpQ = udpQueue; ++ portCfgReg &= ~ETH_DEF_RX_UDP_QUEUE_ALL_MASK; ++ portCfgReg |= ETH_DEF_RX_UDP_QUEUE_MASK(pPortCtrl->portConfig.rxUdpQ); ++ ++ portCfgReg |= ETH_CAPTURE_UDP_FRAMES_ENABLE_MASK; ++ } ++ else ++ { ++ pPortCtrl->portConfig.rxUdpQ = -1; ++ portCfgReg &= ~ETH_CAPTURE_UDP_FRAMES_ENABLE_MASK; ++ } ++ ++ MV_REG_WRITE(ETH_PORT_CONFIG_REG(pPortCtrl->portNo), portCfgReg); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************/ ++/* Speed, Duplex, FlowControl routines */ ++/******************************************************************************/ ++ ++/******************************************************************************* ++* mvEthSpeedDuplexSet - Set Speed and Duplex of the port. ++* ++* DESCRIPTION: ++* This function configure the port to work with desirable Duplex and Speed. ++* Changing of these parameters are allowed only when port is disabled. ++* This function disable the port if was enabled, change duplex and speed ++* and, enable the port back if needed. ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* ETH_PORT_SPEED speed - Speed of the port. ++* ETH_PORT_SPEED duplex - Duplex of the port. ++* ++* RETURN: MV_STATUS ++* MV_OK - Success ++* MV_OUT_OF_RANGE - Failed. Port is out of valid range ++* MV_NOT_FOUND - Failed. Port is not initialized. ++* MV_BAD_PARAM - Input parameters (speed/duplex) in conflict. ++* MV_BAD_VALUE - Value of one of input parameters (speed, duplex) ++* is not valid ++* ++*******************************************************************************/ ++MV_STATUS mvEthSpeedDuplexSet(void* pPortHandle, MV_ETH_PORT_SPEED speed, ++ MV_ETH_PORT_DUPLEX duplex) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ int port = pPortCtrl->portNo; ++ MV_U32 portSerialCtrlReg; ++ ++ if( (port < 0) || (port >= (int)mvCtrlEthMaxPortGet()) ) ++ return MV_OUT_OF_RANGE; ++ ++ pPortCtrl = ethPortCtrl[port]; ++ if(pPortCtrl == NULL) ++ return MV_NOT_FOUND; ++ ++ /* Check validity */ ++ if( (speed == MV_ETH_SPEED_1000) && (duplex == MV_ETH_DUPLEX_HALF) ) ++ return MV_BAD_PARAM; ++ ++ portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port)); ++ /* Set Speed */ ++ switch(speed) ++ { ++ case MV_ETH_SPEED_AN: ++ portSerialCtrlReg &= ~ETH_DISABLE_SPEED_AUTO_NEG_MASK; ++ break; ++ ++ case MV_ETH_SPEED_10: ++ portSerialCtrlReg |= ETH_DISABLE_SPEED_AUTO_NEG_MASK; ++ portSerialCtrlReg &= ~ETH_SET_GMII_SPEED_1000_MASK; ++ portSerialCtrlReg &= ~ETH_SET_MII_SPEED_100_MASK; ++ break; ++ ++ case MV_ETH_SPEED_100: ++ portSerialCtrlReg |= ETH_DISABLE_SPEED_AUTO_NEG_MASK; ++ portSerialCtrlReg &= ~ETH_SET_GMII_SPEED_1000_MASK; ++ portSerialCtrlReg |= ETH_SET_MII_SPEED_100_MASK; ++ break; ++ ++ case MV_ETH_SPEED_1000: ++ portSerialCtrlReg |= ETH_DISABLE_SPEED_AUTO_NEG_MASK; ++ portSerialCtrlReg |= ETH_SET_GMII_SPEED_1000_MASK; ++ break; ++ ++ default: ++ mvOsPrintf("ethDrv: Unexpected Speed value %d\n", speed); ++ return MV_BAD_VALUE; ++ } ++ /* Set duplex */ ++ switch(duplex) ++ { ++ case MV_ETH_DUPLEX_AN: ++ portSerialCtrlReg &= ~ETH_DISABLE_DUPLEX_AUTO_NEG_MASK; ++ break; ++ ++ case MV_ETH_DUPLEX_HALF: ++ portSerialCtrlReg |= ETH_DISABLE_DUPLEX_AUTO_NEG_MASK; ++ portSerialCtrlReg &= ~ETH_SET_FULL_DUPLEX_MASK; ++ break; ++ ++ case MV_ETH_DUPLEX_FULL: ++ portSerialCtrlReg |= ETH_DISABLE_DUPLEX_AUTO_NEG_MASK; ++ portSerialCtrlReg |= ETH_SET_FULL_DUPLEX_MASK; ++ break; ++ ++ default: ++ mvOsPrintf("ethDrv: Unexpected Duplex value %d\n", duplex); ++ return MV_BAD_VALUE; ++ } ++ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(port), portSerialCtrlReg); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvEthFlowCtrlSet - Set Flow Control of the port. ++* ++* DESCRIPTION: ++* This function configure the port to work with desirable Duplex and ++* Speed. Changing of these parameters are allowed only when port is ++* disabled. This function disable the port if was enabled, change ++* duplex and speed and, enable the port back if needed. ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* MV_ETH_PORT_FC flowControl - Flow control of the port. ++* ++* RETURN: MV_STATUS ++* MV_OK - Success ++* MV_OUT_OF_RANGE - Failed. Port is out of valid range ++* MV_NOT_FOUND - Failed. Port is not initialized. ++* MV_BAD_VALUE - Value flowControl parameters is not valid ++* ++*******************************************************************************/ ++MV_STATUS mvEthFlowCtrlSet(void* pPortHandle, MV_ETH_PORT_FC flowControl) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ int port = pPortCtrl->portNo; ++ MV_U32 portSerialCtrlReg; ++ ++ if( (port < 0) || (port >= (int)mvCtrlEthMaxPortGet() ) ) ++ return MV_OUT_OF_RANGE; ++ ++ pPortCtrl = ethPortCtrl[port]; ++ if(pPortCtrl == NULL) ++ return MV_NOT_FOUND; ++ ++ portSerialCtrlReg = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port)); ++ switch(flowControl) ++ { ++ case MV_ETH_FC_AN_ADV_DIS: ++ portSerialCtrlReg &= ~ETH_DISABLE_FC_AUTO_NEG_MASK; ++ portSerialCtrlReg &= ~ETH_ADVERTISE_SYM_FC_MASK; ++ break; ++ ++ case MV_ETH_FC_AN_ADV_SYM: ++ portSerialCtrlReg &= ~ETH_DISABLE_FC_AUTO_NEG_MASK; ++ portSerialCtrlReg |= ETH_ADVERTISE_SYM_FC_MASK; ++ break; ++ ++ case MV_ETH_FC_DISABLE: ++ portSerialCtrlReg |= ETH_DISABLE_FC_AUTO_NEG_MASK; ++ portSerialCtrlReg &= ~ETH_SET_FLOW_CTRL_MASK; ++ break; ++ ++ case MV_ETH_FC_ENABLE: ++ portSerialCtrlReg |= ETH_DISABLE_FC_AUTO_NEG_MASK; ++ portSerialCtrlReg |= ETH_SET_FLOW_CTRL_MASK; ++ break; ++ ++ default: ++ mvOsPrintf("ethDrv: Unexpected FlowControl value %d\n", flowControl); ++ return MV_BAD_VALUE; ++ } ++ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_REG(port), portSerialCtrlReg); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvEthHeaderModeSet - Set port header mode. ++* ++* DESCRIPTION: ++* This function configures the port to work in Marvell-Header mode. ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* MV_ETH_HEADER_MODE headerMode - The header mode to set the port in. ++* ++* RETURN: MV_STATUS ++* MV_OK - Success ++* MV_NOT_SUPPORTED- Feature not supported. ++* MV_OUT_OF_RANGE - Failed. Port is out of valid range ++* MV_NOT_FOUND - Failed. Port is not initialized. ++* MV_BAD_VALUE - Value of headerMode or numRxQueue parameter is not valid. ++* ++*******************************************************************************/ ++MV_STATUS mvEthHeaderModeSet(void* pPortHandle, MV_ETH_HEADER_MODE headerMode) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ int port = pPortCtrl->portNo; ++ MV_U32 mvHeaderReg; ++ MV_U32 numRxQ = MV_ETH_RX_Q_NUM; ++ ++ if((port < 0) || (port >= mvCtrlEthMaxPortGet())) ++ return MV_OUT_OF_RANGE; ++ ++ pPortCtrl = ethPortCtrl[port]; ++ if(pPortCtrl == NULL) ++ return MV_NOT_FOUND; ++ ++ mvHeaderReg = MV_REG_READ(ETH_PORT_MARVELL_HEADER_REG(port)); ++ /* Disable header mode. */ ++ mvHeaderReg &= ~ETH_MVHDR_EN_MASK; ++ ++ if(headerMode != MV_ETH_DISABLE_HEADER_MODE) ++ { ++ /* Enable Header mode. */ ++ mvHeaderReg |= ETH_MVHDR_EN_MASK; ++ ++ /* Clear DA-Prefix & MHMask fields.*/ ++ mvHeaderReg &= ~(ETH_MVHDR_DAPREFIX_MASK | ETH_MVHDR_MHMASK_MASK); ++ ++ if(numRxQ > 1) ++ { ++ switch (headerMode) ++ { ++ case(MV_ETH_ENABLE_HEADER_MODE_PRI_2_1): ++ mvHeaderReg |= ETH_MVHDR_DAPREFIX_PRI_1_2; ++ break; ++ case(MV_ETH_ENABLE_HEADER_MODE_PRI_DBNUM): ++ mvHeaderReg |= ETH_MVHDR_DAPREFIX_DBNUM_PRI; ++ break; ++ case(MV_ETH_ENABLE_HEADER_MODE_PRI_SPID): ++ mvHeaderReg |= ETH_MVHDR_DAPREFIX_SPID_PRI; ++ break; ++ default: ++ break; ++ } ++ ++ switch (numRxQ) ++ { ++ case (4): ++ mvHeaderReg |= ETH_MVHDR_MHMASK_4_QUEUE; ++ break; ++ case (8): ++ mvHeaderReg |= ETH_MVHDR_MHMASK_8_QUEUE; ++ break; ++ default: ++ break; ++ } ++ } ++ } ++ ++ MV_REG_WRITE(ETH_PORT_MARVELL_HEADER_REG(port), mvHeaderReg); ++ ++ return MV_OK; ++} ++ ++#if (MV_ETH_VERSION >= 4) ++/******************************************************************************* ++* mvEthEjpModeSet - Enable / Disable EJP policy for TX. ++* ++* DESCRIPTION: ++* This function ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* MV_BOOL TRUE - enable EJP mode ++* FALSE - disable EJP mode ++* ++* OUTPUT: MV_STATUS ++* MV_OK - Success ++* Other - Failure ++* ++* RETURN: None. ++* ++*******************************************************************************/ ++MV_STATUS mvEthEjpModeSet(void* pPortHandle, int mode) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ int port = pPortCtrl->portNo; ++ ++ if((port < 0) || (port >= mvCtrlEthMaxPortGet())) ++ return MV_OUT_OF_RANGE; ++ ++ pPortCtrl = ethPortCtrl[port]; ++ if(pPortCtrl == NULL) ++ return MV_NOT_FOUND; ++ ++ pPortCtrl->portConfig.ejpMode = mode; ++ if(mode) ++ { ++ /* EJP enabled */ ++ MV_REG_WRITE(ETH_TXQ_CMD_1_REG(port), ETH_TX_EJP_ENABLE_MASK); ++ } ++ else ++ { ++ /* EJP disabled */ ++ MV_REG_WRITE(ETH_TXQ_CMD_1_REG(port), 0); ++ } ++ mvOsPrintf("eth_%d: EJP %s - ETH_TXQ_CMD_1_REG: 0x%x = 0x%08x\n", ++ port, mode ? "Enabled" : "Disabled", ETH_TXQ_CMD_1_REG(port), ++ MV_REG_READ(ETH_TXQ_CMD_1_REG(port))); ++ ++ return MV_OK; ++} ++#endif /* MV_ETH_VERSION >= 4 */ ++ ++/******************************************************************************* ++* mvEthStatusGet - Get major properties of the port . ++* ++* DESCRIPTION: ++* This function get major properties of the port (link, speed, duplex, ++* flowControl, etc) and return them using the single structure. ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* ++* OUTPUT: ++* MV_ETH_PORT_STATUS* pStatus - Pointer to structure, were port status ++* will be placed. ++* ++* RETURN: None. ++* ++*******************************************************************************/ ++void mvEthStatusGet(void* pPortHandle, MV_ETH_PORT_STATUS* pStatus) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ int port = pPortCtrl->portNo; ++ ++ MV_U32 regValue; ++ ++ regValue = MV_REG_READ( ETH_PORT_STATUS_REG(port) ); ++ ++ if(regValue & ETH_GMII_SPEED_1000_MASK) ++ pStatus->speed = MV_ETH_SPEED_1000; ++ else if(regValue & ETH_MII_SPEED_100_MASK) ++ pStatus->speed = MV_ETH_SPEED_100; ++ else ++ pStatus->speed = MV_ETH_SPEED_10; ++ ++ if(regValue & ETH_LINK_UP_MASK) ++ pStatus->isLinkUp = MV_TRUE; ++ else ++ pStatus->isLinkUp = MV_FALSE; ++ ++ if(regValue & ETH_FULL_DUPLEX_MASK) ++ pStatus->duplex = MV_ETH_DUPLEX_FULL; ++ else ++ pStatus->duplex = MV_ETH_DUPLEX_HALF; ++ ++ ++ if(regValue & ETH_ENABLE_RCV_FLOW_CTRL_MASK) ++ pStatus->flowControl = MV_ETH_FC_ENABLE; ++ else ++ pStatus->flowControl = MV_ETH_FC_DISABLE; ++} ++ ++ ++/******************************************************************************/ ++/* PHY Control Functions */ ++/******************************************************************************/ ++ ++ ++/******************************************************************************* ++* mvEthPhyAddrSet - Set the ethernet port PHY address. ++* ++* DESCRIPTION: ++* This routine set the ethernet port PHY address according to given ++* parameter. ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* int phyAddr - PHY address ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++void mvEthPhyAddrSet(void* pPortHandle, int phyAddr) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ int port = pPortCtrl->portNo; ++ unsigned int regData; ++ ++ regData = MV_REG_READ(ETH_PHY_ADDR_REG(port)); ++ ++ regData &= ~ETH_PHY_ADDR_MASK; ++ regData |= phyAddr; ++ ++ MV_REG_WRITE(ETH_PHY_ADDR_REG(port), regData); ++ ++ return; ++} ++ ++/******************************************************************************* ++* mvEthPhyAddrGet - Get the ethernet port PHY address. ++* ++* DESCRIPTION: ++* This routine returns the given ethernet port PHY address. ++* ++* INPUT: ++* void* pPortHandle - Pointer to port specific handler; ++* ++* ++* RETURN: int - PHY address. ++* ++*******************************************************************************/ ++int mvEthPhyAddrGet(void* pPortHandle) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHandle; ++ int port = pPortCtrl->portNo; ++ unsigned int regData; ++ ++ regData = MV_REG_READ(ETH_PHY_ADDR_REG(port)); ++ ++ return ((regData >> (5 * port)) & 0x1f); ++} ++ ++/******************************************************************************/ ++/* Descriptor handling Functions */ ++/******************************************************************************/ ++ ++/******************************************************************************* ++* etherInitRxDescRing - Curve a Rx chain desc list and buffer in memory. ++* ++* DESCRIPTION: ++* This function prepares a Rx chained list of descriptors and packet ++* buffers in a form of a ring. The routine must be called after port ++* initialization routine and before port start routine. ++* The Ethernet SDMA engine uses CPU bus addresses to access the various ++* devices in the system (i.e. DRAM). This function uses the ethernet ++* struct 'virtual to physical' routine (set by the user) to set the ring ++* with physical addresses. ++* ++* INPUT: ++* ETH_QUEUE_CTRL *pEthPortCtrl Ethernet Port Control srtuct. ++* int rxQueue Number of Rx queue. ++* int rxDescNum Number of Rx descriptors ++* MV_U8* rxDescBaseAddr Rx descriptors memory area base addr. ++* ++* OUTPUT: ++* The routine updates the Ethernet port control struct with information ++* regarding the Rx descriptors and buffers. ++* ++* RETURN: None ++* ++*******************************************************************************/ ++static void ethInitRxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue) ++{ ++ ETH_RX_DESC *pRxDescBase, *pRxDesc, *pRxPrevDesc; ++ int ix, rxDescNum = pPortCtrl->rxQueueConfig[queue].descrNum; ++ ETH_QUEUE_CTRL *pQueueCtrl = &pPortCtrl->rxQueue[queue]; ++ ++ /* Make sure descriptor address is cache line size aligned */ ++ pRxDescBase = (ETH_RX_DESC*)MV_ALIGN_UP((MV_ULONG)pQueueCtrl->descBuf.bufVirtPtr, ++ CPU_D_CACHE_LINE_SIZE); ++ ++ pRxDesc = (ETH_RX_DESC*)pRxDescBase; ++ pRxPrevDesc = pRxDesc; ++ ++ /* initialize the Rx descriptors ring */ ++ for (ix=0; ixbufSize = 0x0; ++ pRxDesc->byteCnt = 0x0; ++ pRxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; ++ pRxDesc->bufPtr = 0x0; ++ pRxDesc->returnInfo = 0x0; ++ pRxPrevDesc = pRxDesc; ++ if(ix == (rxDescNum-1)) ++ { ++ /* Closing Rx descriptors ring */ ++ pRxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pRxDescBase); ++ } ++ else ++ { ++ pRxDesc = (ETH_RX_DESC*)((MV_ULONG)pRxDesc + ETH_RX_DESC_ALIGNED_SIZE); ++ pRxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pRxDesc); ++ } ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxPrevDesc); ++ } ++ ++ pQueueCtrl->pCurrentDescr = pRxDescBase; ++ pQueueCtrl->pUsedDescr = pRxDescBase; ++ ++ pQueueCtrl->pFirstDescr = pRxDescBase; ++ pQueueCtrl->pLastDescr = pRxDesc; ++ pQueueCtrl->resource = 0; ++} ++ ++void ethResetRxDescRing(void* pPortHndl, int queue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->rxQueue[queue]; ++ ETH_RX_DESC* pRxDesc = (ETH_RX_DESC*)pQueueCtrl->pFirstDescr; ++ ++ pQueueCtrl->resource = 0; ++ if(pQueueCtrl->pFirstDescr != NULL) ++ { ++ while(MV_TRUE) ++ { ++ pRxDesc->bufSize = 0x0; ++ pRxDesc->byteCnt = 0x0; ++ pRxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; ++ pRxDesc->bufPtr = 0x0; ++ pRxDesc->returnInfo = 0x0; ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxDesc); ++ if( (void*)pRxDesc == pQueueCtrl->pLastDescr) ++ break; ++ pRxDesc = RX_NEXT_DESC_PTR(pRxDesc, pQueueCtrl); ++ } ++ pQueueCtrl->pCurrentDescr = pQueueCtrl->pFirstDescr; ++ pQueueCtrl->pUsedDescr = pQueueCtrl->pFirstDescr; ++ ++ /* Update RX Command register */ ++ pPortCtrl->portRxQueueCmdReg |= (1 << queue); ++ ++ /* update HW */ ++ MV_REG_WRITE( ETH_RX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), ++ (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); ++ } ++ else ++ { ++ /* Update RX Command register */ ++ pPortCtrl->portRxQueueCmdReg &= ~(1 << queue); ++ ++ /* update HW */ ++ MV_REG_WRITE( ETH_RX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), 0); ++ } ++} ++ ++/******************************************************************************* ++* etherInitTxDescRing - Curve a Tx chain desc list and buffer in memory. ++* ++* DESCRIPTION: ++* This function prepares a Tx chained list of descriptors and packet ++* buffers in a form of a ring. The routine must be called after port ++* initialization routine and before port start routine. ++* The Ethernet SDMA engine uses CPU bus addresses to access the various ++* devices in the system (i.e. DRAM). This function uses the ethernet ++* struct 'virtual to physical' routine (set by the user) to set the ring ++* with physical addresses. ++* ++* INPUT: ++* ETH_PORT_CTRL *pEthPortCtrl Ethernet Port Control srtuct. ++* int txQueue Number of Tx queue. ++* int txDescNum Number of Tx descriptors ++* int txBuffSize Size of Tx buffer ++* MV_U8* pTxDescBase Tx descriptors memory area base addr. ++* ++* OUTPUT: ++* The routine updates the Ethernet port control struct with information ++* regarding the Tx descriptors and buffers. ++* ++* RETURN: None. ++* ++*******************************************************************************/ ++static void ethInitTxDescRing(ETH_PORT_CTRL* pPortCtrl, int queue) ++{ ++ ETH_TX_DESC *pTxDescBase, *pTxDesc, *pTxPrevDesc; ++ int ix, txDescNum = pPortCtrl->txQueueConfig[queue].descrNum; ++ ETH_QUEUE_CTRL *pQueueCtrl = &pPortCtrl->txQueue[queue]; ++ ++ /* Make sure descriptor address is cache line size aligned */ ++ pTxDescBase = (ETH_TX_DESC*)MV_ALIGN_UP((MV_ULONG)pQueueCtrl->descBuf.bufVirtPtr, ++ CPU_D_CACHE_LINE_SIZE); ++ ++ pTxDesc = (ETH_TX_DESC*)pTxDescBase; ++ pTxPrevDesc = pTxDesc; ++ ++ /* initialize the Tx descriptors ring */ ++ for (ix=0; ixbyteCnt = 0x0000; ++ pTxDesc->L4iChk = 0x0000; ++ pTxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; ++ pTxDesc->bufPtr = 0x0; ++ pTxDesc->returnInfo = 0x0; ++ ++ pTxPrevDesc = pTxDesc; ++ ++ if(ix == (txDescNum-1)) ++ { ++ /* Closing Tx descriptors ring */ ++ pTxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pTxDescBase); ++ } ++ else ++ { ++ pTxDesc = (ETH_TX_DESC*)((MV_ULONG)pTxDesc + ETH_TX_DESC_ALIGNED_SIZE); ++ pTxPrevDesc->nextDescPtr = (MV_U32)ethDescVirtToPhy(pQueueCtrl, (void*)pTxDesc); ++ } ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxPrevDesc); ++ } ++ ++ pQueueCtrl->pCurrentDescr = pTxDescBase; ++ pQueueCtrl->pUsedDescr = pTxDescBase; ++ ++ pQueueCtrl->pFirstDescr = pTxDescBase; ++ pQueueCtrl->pLastDescr = pTxDesc; ++ /* Leave one TX descriptor out of use */ ++ pQueueCtrl->resource = txDescNum - 1; ++} ++ ++void ethResetTxDescRing(void* pPortHndl, int queue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->txQueue[queue]; ++ ETH_TX_DESC* pTxDesc = (ETH_TX_DESC*)pQueueCtrl->pFirstDescr; ++ ++ pQueueCtrl->resource = 0; ++ if(pQueueCtrl->pFirstDescr != NULL) ++ { ++ while(MV_TRUE) ++ { ++ pTxDesc->byteCnt = 0x0000; ++ pTxDesc->L4iChk = 0x0000; ++ pTxDesc->cmdSts = ETH_BUFFER_OWNED_BY_HOST; ++ pTxDesc->bufPtr = 0x0; ++ pTxDesc->returnInfo = 0x0; ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxDesc); ++ pQueueCtrl->resource++; ++ if( (void*)pTxDesc == pQueueCtrl->pLastDescr) ++ break; ++ pTxDesc = TX_NEXT_DESC_PTR(pTxDesc, pQueueCtrl); ++ } ++ /* Leave one TX descriptor out of use */ ++ pQueueCtrl->resource--; ++ pQueueCtrl->pCurrentDescr = pQueueCtrl->pFirstDescr; ++ pQueueCtrl->pUsedDescr = pQueueCtrl->pFirstDescr; ++ ++ /* Update TX Command register */ ++ pPortCtrl->portTxQueueCmdReg |= MV_32BIT_LE_FAST(1 << queue); ++ /* update HW */ ++ MV_REG_WRITE( ETH_TX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), ++ (MV_U32)ethDescVirtToPhy(pQueueCtrl, pQueueCtrl->pCurrentDescr) ); ++ } ++ else ++ { ++ /* Update TX Command register */ ++ pPortCtrl->portTxQueueCmdReg &= MV_32BIT_LE_FAST(~(1 << queue)); ++ /* update HW */ ++ MV_REG_WRITE( ETH_TX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue), 0 ); ++ } ++} ++ ++/******************************************************************************* ++* ethAllocDescrMemory - Free memory allocated for RX and TX descriptors. ++* ++* DESCRIPTION: ++* This function allocates memory for RX and TX descriptors. ++* - If ETH_DESCR_IN_SRAM defined, allocate memory from SRAM. ++* - If ETH_DESCR_IN_SDRAM defined, allocate memory in SDRAM. ++* ++* INPUT: ++* int size - size of memory should be allocated. ++* ++* RETURN: None ++* ++*******************************************************************************/ ++static MV_U8* ethAllocDescrMemory(ETH_PORT_CTRL* pPortCtrl, int descSize, ++ MV_ULONG* pPhysAddr, MV_U32 *memHandle) ++{ ++ MV_U8* pVirt; ++ ++#if defined(ETH_DESCR_IN_SRAM) ++ if(ethDescInSram == MV_TRUE) ++ pVirt = (char*)mvSramMalloc(descSize, pPhysAddr); ++ else ++#endif /* ETH_DESCR_IN_SRAM */ ++ { ++#ifdef ETH_DESCR_UNCACHED ++ pVirt = (MV_U8*)mvOsIoUncachedMalloc(pPortCtrl->osHandle, descSize, ++ pPhysAddr,memHandle); ++#else ++ pVirt = (MV_U8*)mvOsIoCachedMalloc(pPortCtrl->osHandle, descSize, ++ pPhysAddr, memHandle); ++#endif /* ETH_DESCR_UNCACHED */ ++ } ++ memset(pVirt, 0, descSize); ++ ++ return pVirt; ++} ++ ++/******************************************************************************* ++* ethFreeDescrMemory - Free memory allocated for RX and TX descriptors. ++* ++* DESCRIPTION: ++* This function frees memory allocated for RX and TX descriptors. ++* - If ETH_DESCR_IN_SRAM defined, free memory using gtSramFree() function. ++* - If ETH_DESCR_IN_SDRAM defined, free memory using mvOsFree() function. ++* ++* INPUT: ++* void* pVirtAddr - virtual pointer to memory allocated for RX and TX ++* desriptors. ++* ++* RETURN: None ++* ++*******************************************************************************/ ++void ethFreeDescrMemory(ETH_PORT_CTRL* pPortCtrl, MV_BUF_INFO* pDescBuf) ++{ ++ if( (pDescBuf == NULL) || (pDescBuf->bufVirtPtr == NULL) ) ++ return; ++ ++#if defined(ETH_DESCR_IN_SRAM) ++ if( ethDescInSram ) ++ { ++ mvSramFree(pDescBuf->bufSize, pDescBuf->bufPhysAddr, pDescBuf->bufVirtPtr); ++ return; ++ } ++#endif /* ETH_DESCR_IN_SRAM */ ++ ++#ifdef ETH_DESCR_UNCACHED ++ mvOsIoUncachedFree(pPortCtrl->osHandle, pDescBuf->bufSize, pDescBuf->bufPhysAddr, ++ pDescBuf->bufVirtPtr,pDescBuf->memHandle); ++#else ++ mvOsIoCachedFree(pPortCtrl->osHandle, pDescBuf->bufSize, pDescBuf->bufPhysAddr, ++ pDescBuf->bufVirtPtr,pDescBuf->memHandle); ++#endif /* ETH_DESCR_UNCACHED */ ++} ++ ++/******************************************************************************/ ++/* Other Functions */ ++/******************************************************************************/ ++ ++void mvEthPortPowerUp(int port) ++{ ++ MV_U32 regVal; ++ ++ /* MAC Cause register should be cleared */ ++ MV_REG_WRITE(ETH_UNIT_INTR_CAUSE_REG(port), 0); ++ ++ if (mvBoardIsPortInSgmii(port)) ++ mvEthPortSgmiiConfig(port); ++ ++ /* Cancel Port Reset */ ++ regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)); ++ regVal &= (~ETH_PORT_RESET_MASK); ++ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal); ++ while( (MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)) & ETH_PORT_RESET_MASK) != 0); ++} ++ ++void mvEthPortPowerDown(int port) ++{ ++ MV_U32 regVal; ++ ++ /* Port must be DISABLED */ ++ regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_REG(port)); ++ if( (regVal & ETH_PORT_ENABLE_MASK) != 0) ++ { ++ mvOsPrintf("ethPort #%d: PowerDown - port must be Disabled (PSC=0x%x)\n", ++ port, regVal); ++ return; ++ } ++ ++ /* Port Reset (Read after write the register as a precaution) */ ++ regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)); ++ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal | ETH_PORT_RESET_MASK); ++ while((MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)) & ETH_PORT_RESET_MASK) == 0); ++} ++ ++static void mvEthPortSgmiiConfig(int port) ++{ ++ MV_U32 regVal; ++ ++ regVal = MV_REG_READ(ETH_PORT_SERIAL_CTRL_1_REG(port)); ++ ++ regVal |= (ETH_SGMII_MODE_MASK /*| ETH_INBAND_AUTO_NEG_ENABLE_MASK */); ++ regVal &= (~ETH_INBAND_AUTO_NEG_BYPASS_MASK); ++ ++ MV_REG_WRITE(ETH_PORT_SERIAL_CTRL_1_REG(port), regVal); ++} ++ ++ ++ ++ ++ ++ ++ ++ ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,748 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++/******************************************************************************* ++* mvEthDebug.c - Source file for user friendly debug functions ++* ++* DESCRIPTION: ++* ++* DEPENDENCIES: ++* None. ++* ++*******************************************************************************/ ++ ++#include "mvOs.h" ++#include "mvCommon.h" ++#include "mvTypes.h" ++#include "mv802_3.h" ++#include "mvDebug.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "eth-phy/mvEthPhy.h" ++#include "eth/mvEth.h" ++#include "eth/gbe/mvEthDebug.h" ++ ++/* #define mvOsPrintf printf */ ++ ++void mvEthPortShow(void* pHndl); ++void mvEthQueuesShow(void* pHndl, int rxQueue, int txQueue, int mode); ++ ++/******************************************************************************/ ++/* Debug functions */ ++/******************************************************************************/ ++void ethRxCoal(int port, int usec) ++{ ++ void* pHndl; ++ ++ pHndl = mvEthPortHndlGet(port); ++ if(pHndl != NULL) ++ { ++ mvEthRxCoalSet(pHndl, usec); ++ } ++} ++ ++void ethTxCoal(int port, int usec) ++{ ++ void* pHndl; ++ ++ pHndl = mvEthPortHndlGet(port); ++ if(pHndl != NULL) ++ { ++ mvEthTxCoalSet(pHndl, usec); ++ } ++} ++ ++#if (MV_ETH_VERSION >= 4) ++void ethEjpModeSet(int port, int mode) ++{ ++ void* pHndl; ++ ++ pHndl = mvEthPortHndlGet(port); ++ if(pHndl != NULL) ++ { ++ mvEthEjpModeSet(pHndl, mode); ++ } ++} ++#endif /* (MV_ETH_VERSION >= 4) */ ++ ++void ethBpduRxQ(int port, int bpduQueue) ++{ ++ void* pHndl; ++ ++ pHndl = mvEthPortHndlGet(port); ++ if(pHndl != NULL) ++ { ++ mvEthBpduRxQueue(pHndl, bpduQueue); ++ } ++} ++ ++void ethArpRxQ(int port, int arpQueue) ++{ ++ void* pHndl; ++ ++ pHndl = mvEthPortHndlGet(port); ++ if(pHndl != NULL) ++ { ++ mvEthArpRxQueue(pHndl, arpQueue); ++ } ++} ++ ++void ethTcpRxQ(int port, int tcpQueue) ++{ ++ void* pHndl; ++ ++ pHndl = mvEthPortHndlGet(port); ++ if(pHndl != NULL) ++ { ++ mvEthTcpRxQueue(pHndl, tcpQueue); ++ } ++} ++ ++void ethUdpRxQ(int port, int udpQueue) ++{ ++ void* pHndl; ++ ++ pHndl = mvEthPortHndlGet(port); ++ if(pHndl != NULL) ++ { ++ mvEthUdpRxQueue(pHndl, udpQueue); ++ } ++} ++ ++void ethTxPolicyRegs(int port) ++{ ++ int queue; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)mvEthPortHndlGet(port); ++ ++ if(pPortCtrl == NULL) ++ { ++ return; ++ } ++ mvOsPrintf("Port #%d TX Policy: EJP=%d, TXQs: ", ++ port, pPortCtrl->portConfig.ejpMode); ++ for(queue=0; queuetxQueueConfig[queue].descrNum > 0) ++ mvOsPrintf("%d, ", queue); ++ } ++ mvOsPrintf("\n"); ++ ++ mvOsPrintf("\n\t TX policy Port #%d configuration registers\n", port); ++ ++ mvOsPrintf("ETH_TX_QUEUE_COMMAND_REG : 0x%X = 0x%08x\n", ++ ETH_TX_QUEUE_COMMAND_REG(port), ++ MV_REG_READ( ETH_TX_QUEUE_COMMAND_REG(port) ) ); ++ ++ mvOsPrintf("ETH_TX_FIXED_PRIO_CFG_REG : 0x%X = 0x%08x\n", ++ ETH_TX_FIXED_PRIO_CFG_REG(port), ++ MV_REG_READ( ETH_TX_FIXED_PRIO_CFG_REG(port) ) ); ++ ++ mvOsPrintf("ETH_TX_TOKEN_RATE_CFG_REG : 0x%X = 0x%08x\n", ++ ETH_TX_TOKEN_RATE_CFG_REG(port), ++ MV_REG_READ( ETH_TX_TOKEN_RATE_CFG_REG(port) ) ); ++ ++ mvOsPrintf("ETH_MAX_TRANSMIT_UNIT_REG : 0x%X = 0x%08x\n", ++ ETH_MAX_TRANSMIT_UNIT_REG(port), ++ MV_REG_READ( ETH_MAX_TRANSMIT_UNIT_REG(port) ) ); ++ ++ mvOsPrintf("ETH_TX_TOKEN_BUCKET_SIZE_REG : 0x%X = 0x%08x\n", ++ ETH_TX_TOKEN_BUCKET_SIZE_REG(port), ++ MV_REG_READ( ETH_TX_TOKEN_BUCKET_SIZE_REG(port) ) ); ++ ++ mvOsPrintf("ETH_TX_TOKEN_BUCKET_COUNT_REG : 0x%X = 0x%08x\n", ++ ETH_TX_TOKEN_BUCKET_COUNT_REG(port), ++ MV_REG_READ( ETH_TX_TOKEN_BUCKET_COUNT_REG(port) ) ); ++ ++ for(queue=0; queue> 24) & 0xff), ((macH >> 16) & 0xff), ++ ((macH >> 8) & 0xff), (macH & 0xff), ++ ((macL >> 8) & 0xff), (macL & 0xff) ); ++ ++ for (i=0; i<4; i++) ++ { ++ unicastReg = MV_REG_READ( (ETH_DA_FILTER_UCAST_BASE(port) + i*4)); ++ for(j=0; j<4; j++) ++ { ++ MV_U8 macEntry = (unicastReg >> (8*j)) & 0xFF; ++ ++ mvOsPrintf("%X: %8s, Q = %d\n", i*4+j, ++ (macEntry & BIT0) ? "Accept" : "Reject", (macEntry >> 1) & 0x7); ++ } ++ } ++} ++ ++void ethMcastAdd(int port, char* macStr, int queue) ++{ ++ void* pHndl; ++ MV_U8 macAddr[MV_MAC_ADDR_SIZE]; ++ ++ pHndl = mvEthPortHndlGet(port); ++ if(pHndl != NULL) ++ { ++ mvMacStrToHex(macStr, macAddr); ++ mvEthMcastAddrSet(pHndl, macAddr, queue); ++ } ++} ++ ++void ethPortMcast(int port) ++{ ++ int tblIdx, regIdx; ++ MV_U32 regVal; ++ ++ mvOsPrintf("\n\t Port #%d Special (IP) Multicast table: 01:00:5E:00:00:XX\n\n", ++ port); ++ ++ for(tblIdx=0; tblIdx<(256/4); tblIdx++) ++ { ++ regVal = MV_REG_READ((ETH_DA_FILTER_SPEC_MCAST_BASE(port) + tblIdx*4)); ++ for(regIdx=0; regIdx<4; regIdx++) ++ { ++ if((regVal & (0x01 << (regIdx*8))) != 0) ++ { ++ mvOsPrintf("0x%02X: Accepted, rxQ = %d\n", ++ tblIdx*4+regIdx, ((regVal >> (regIdx*8+1)) & 0x07)); ++ } ++ } ++ } ++ mvOsPrintf("\n\t Port #%d Other Multicast table\n\n", port); ++ for(tblIdx=0; tblIdx<(256/4); tblIdx++) ++ { ++ regVal = MV_REG_READ((ETH_DA_FILTER_OTH_MCAST_BASE(port) + tblIdx*4)); ++ for(regIdx=0; regIdx<4; regIdx++) ++ { ++ if((regVal & (0x01 << (regIdx*8))) != 0) ++ { ++ mvOsPrintf("Crc8=0x%02X: Accepted, rxQ = %d\n", ++ tblIdx*4+regIdx, ((regVal >> (regIdx*8+1)) & 0x07)); ++ } ++ } ++ } ++} ++ ++ ++/* Print status of Ethernet port */ ++void mvEthPortShow(void* pHndl) ++{ ++ MV_U32 regValue, rxCoal, txCoal; ++ int speed, queue, port; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pHndl; ++ ++ port = pPortCtrl->portNo; ++ ++ regValue = MV_REG_READ( ETH_PORT_STATUS_REG(port) ); ++ ++ mvOsPrintf("\n\t ethGiga #%d port Status: 0x%04x = 0x%08x\n\n", ++ port, ETH_PORT_STATUS_REG(port), regValue); ++ ++ mvOsPrintf("descInSram=%d, descSwCoher=%d\n", ++ ethDescInSram, ethDescSwCoher); ++ ++ if(regValue & ETH_GMII_SPEED_1000_MASK) ++ speed = 1000; ++ else if(regValue & ETH_MII_SPEED_100_MASK) ++ speed = 100; ++ else ++ speed = 10; ++ ++ mvEthCoalGet(pPortCtrl, &rxCoal, &txCoal); ++ ++ /* Link, Speed, Duplex, FlowControl */ ++ mvOsPrintf("Link=%s, Speed=%d, Duplex=%s, RxFlowControl=%s", ++ (regValue & ETH_LINK_UP_MASK) ? "UP" : "DOWN", ++ speed, ++ (regValue & ETH_FULL_DUPLEX_MASK) ? "FULL" : "HALF", ++ (regValue & ETH_ENABLE_RCV_FLOW_CTRL_MASK) ? "ENABLE" : "DISABLE"); ++ ++ mvOsPrintf("\n"); ++ ++ mvOsPrintf("RxCoal = %d usec, TxCoal = %d usec\n", ++ rxCoal, txCoal); ++ ++ mvOsPrintf("rxDefQ=%d, arpQ=%d, bpduQ=%d, tcpQ=%d, udpQ=%d\n\n", ++ pPortCtrl->portConfig.rxDefQ, pPortCtrl->portConfig.rxArpQ, ++ pPortCtrl->portConfig.rxBpduQ, ++ pPortCtrl->portConfig.rxTcpQ, pPortCtrl->portConfig.rxUdpQ); ++ ++ /* Print all RX and TX queues */ ++ for(queue=0; queuerxQueue[queue].pFirstDescr, ++ mvEthRxResourceGet(pPortCtrl, queue) ); ++ } ++ mvOsPrintf("\n"); ++ for(queue=0; queuetxQueue[queue].pFirstDescr, ++ mvEthTxResourceGet(pPortCtrl, queue) ); ++ } ++} ++ ++/* Print RX and TX queue of the Ethernet port */ ++void mvEthQueuesShow(void* pHndl, int rxQueue, int txQueue, int mode) ++{ ++ ETH_PORT_CTRL *pPortCtrl = (ETH_PORT_CTRL*)pHndl; ++ ETH_QUEUE_CTRL *pQueueCtrl; ++ MV_U32 regValue; ++ ETH_RX_DESC *pRxDescr; ++ ETH_TX_DESC *pTxDescr; ++ int i, port = pPortCtrl->portNo; ++ ++ if( (rxQueue >=0) && (rxQueue < MV_ETH_RX_Q_NUM) ) ++ { ++ pQueueCtrl = &(pPortCtrl->rxQueue[rxQueue]); ++ mvOsPrintf("Port #%d, RX Queue #%d\n\n", port, rxQueue); ++ ++ mvOsPrintf("CURR_RX_DESC_PTR : 0x%X = 0x%08x\n", ++ ETH_RX_CUR_DESC_PTR_REG(port, rxQueue), ++ MV_REG_READ( ETH_RX_CUR_DESC_PTR_REG(port, rxQueue))); ++ ++ ++ if(pQueueCtrl->pFirstDescr != NULL) ++ { ++ mvOsPrintf("pFirstDescr=0x%lx, pLastDescr=0x%lx, numOfResources=%d\n", ++ (MV_ULONG)pQueueCtrl->pFirstDescr, (MV_ULONG)pQueueCtrl->pLastDescr, ++ pQueueCtrl->resource); ++ mvOsPrintf("pCurrDescr: 0x%lx, pUsedDescr: 0x%lx\n", ++ (MV_ULONG)pQueueCtrl->pCurrentDescr, ++ (MV_ULONG)pQueueCtrl->pUsedDescr); ++ ++ if(mode == 1) ++ { ++ pRxDescr = (ETH_RX_DESC*)pQueueCtrl->pFirstDescr; ++ i = 0; ++ do ++ { ++ mvOsPrintf("%3d. desc=%08x (%08x), cmd=%08x, data=%4d, buf=%4d, buf=%08x, pkt=%lx, os=%lx\n", ++ i, (MV_U32)pRxDescr, (MV_U32)ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pRxDescr), ++ pRxDescr->cmdSts, pRxDescr->byteCnt, (MV_U32)pRxDescr->bufSize, ++ (unsigned int)pRxDescr->bufPtr, (MV_ULONG)pRxDescr->returnInfo, ++ ((MV_PKT_INFO*)pRxDescr->returnInfo)->osInfo); ++ ++ ETH_DESCR_INV(pPortCtrl, pRxDescr); ++ pRxDescr = RX_NEXT_DESC_PTR(pRxDescr, pQueueCtrl); ++ i++; ++ } while (pRxDescr != pQueueCtrl->pFirstDescr); ++ } ++ } ++ else ++ mvOsPrintf("RX Queue #%d is NOT CREATED\n", rxQueue); ++ } ++ ++ if( (txQueue >=0) && (txQueue < MV_ETH_TX_Q_NUM) ) ++ { ++ pQueueCtrl = &(pPortCtrl->txQueue[txQueue]); ++ mvOsPrintf("Port #%d, TX Queue #%d\n\n", port, txQueue); ++ ++ regValue = MV_REG_READ( ETH_TX_CUR_DESC_PTR_REG(port, txQueue)); ++ mvOsPrintf("CURR_TX_DESC_PTR : 0x%X = 0x%08x\n", ++ ETH_TX_CUR_DESC_PTR_REG(port, txQueue), regValue); ++ ++ if(pQueueCtrl->pFirstDescr != NULL) ++ { ++ mvOsPrintf("pFirstDescr=0x%lx, pLastDescr=0x%lx, numOfResources=%d\n", ++ (MV_ULONG)pQueueCtrl->pFirstDescr, ++ (MV_ULONG)pQueueCtrl->pLastDescr, ++ pQueueCtrl->resource); ++ mvOsPrintf("pCurrDescr: 0x%lx, pUsedDescr: 0x%lx\n", ++ (MV_ULONG)pQueueCtrl->pCurrentDescr, ++ (MV_ULONG)pQueueCtrl->pUsedDescr); ++ ++ if(mode == 1) ++ { ++ pTxDescr = (ETH_TX_DESC*)pQueueCtrl->pFirstDescr; ++ i = 0; ++ do ++ { ++ mvOsPrintf("%3d. desc=%08x (%08x), cmd=%08x, data=%4d, buf=%08x, pkt=%lx, os=%lx\n", ++ i, (MV_U32)pTxDescr, (MV_U32)ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pTxDescr), ++ pTxDescr->cmdSts, pTxDescr->byteCnt, ++ (MV_U32)pTxDescr->bufPtr, (MV_ULONG)pTxDescr->returnInfo, ++ pTxDescr->returnInfo ? (((MV_PKT_INFO*)pTxDescr->returnInfo)->osInfo) : 0x0); ++ ++ ETH_DESCR_INV(pPortCtrl, pTxDescr); ++ pTxDescr = TX_NEXT_DESC_PTR(pTxDescr, pQueueCtrl); ++ i++; ++ } while (pTxDescr != pQueueCtrl->pFirstDescr); ++ } ++ } ++ else ++ mvOsPrintf("TX Queue #%d is NOT CREATED\n", txQueue); ++ } ++} +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthDebug.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,146 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++#ifndef __MV_ETH_DEBUG_H__ ++#define __MV_ETH_DEBUG_H__ ++ ++#if 0 ++/* ++ ** Externs ++ */ ++void ethBpduRxQ(int port, int bpduQueue); ++void ethArpRxQ(int port, int bpduQueue); ++void ethTcpRxQ(int port, int bpduQueue); ++void ethUdpRxQ(int port, int bpduQueue); ++void ethMcastAdd(int port, char* macStr, int queue); ++ ++#ifdef INCLUDE_MULTI_QUEUE ++void ethRxPolicy( int port); ++void ethTxPolicy( int port); ++void ethTxPolDA(int port, char* macStr, int txQ, char* headerHexStr); ++void ethRxPolMode(int port, MV_ETH_PRIO_MODE prioMode); ++void ethRxPolQ(int port, int rxQueue, int rxQuota); ++#endif /* INCLUDE_MULTI_QUEUE */ ++ ++void print_egiga_stat(void *sc, unsigned int port); ++void ethPortStatus (int port); ++void ethPortQueues( int port, int rxQueue, int txQueue, int mode); ++void ethPortMcast(int port); ++void ethPortRegs(int port); ++void ethPortCounters(int port); ++void ethPortRmonCounters(int port); ++void ethRxCoal(int port, int usec); ++void ethTxCoal(int port, int usec); ++ ++void ethRegs(int port); ++void ethClearCounters(int port); ++void ethUcastSet(int port, char* macStr, int queue); ++void ethPortUcastShow(int port); ++ ++#ifdef CONFIG_MV_ETH_HEADER ++void run_com_header(const char *buffer); ++#endif ++ ++#ifdef INCLUDE_MULTI_QUEUE ++void ethRxPolMode(int port, MV_ETH_PRIO_MODE prioMode); ++void ethRxPolQ(int port, int queue, int quota); ++void ethRxPolicy(int port); ++void ethTxPolDef(int port, int txQ, char* headerHexStr); ++void ethTxPolDA(int port, char* macStr, int txQ, char* headerHexStr); ++void ethTxPolicy(int port); ++#endif /* INCLUDE_MULTI_QUEUE */ ++ ++#if (MV_ETH_VERSION >= 4) ++void ethEjpModeSet(int port, int mode) ++#endif ++#endif /* 0 */ ++ ++ ++ ++ ++void ethRxCoal(int port, int usec); ++void ethTxCoal(int port, int usec); ++#if (MV_ETH_VERSION >= 4) ++void ethEjpModeSet(int port, int mode); ++#endif /* (MV_ETH_VERSION >= 4) */ ++ ++void ethBpduRxQ(int port, int bpduQueue); ++void ethArpRxQ(int port, int arpQueue); ++void ethTcpRxQ(int port, int tcpQueue); ++void ethUdpRxQ(int port, int udpQueue); ++void ethTxPolicyRegs(int port); ++void ethPortRegs(int port); ++void ethRegs(int port); ++void ethClearCounters(int port); ++void ethPortCounters(int port); ++void ethPortRmonCounters(int port); ++void ethPortStatus(int port); ++void ethPortQueues(int port, int rxQueue, int txQueue, int mode); ++void ethUcastSet(int port, char* macStr, int queue); ++void ethPortUcastShow(int port); ++void ethMcastAdd(int port, char* macStr, int queue); ++void ethPortMcast(int port); ++void mvEthPortShow(void* pHndl); ++void mvEthQueuesShow(void* pHndl, int rxQueue, int txQueue, int mode); ++ ++#endif +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthGbe.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthGbe.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthGbe.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthGbe.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,751 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++/******************************************************************************* ++* mvEth.h - Header File for : Marvell Gigabit Ethernet Controller ++* ++* DESCRIPTION: ++* This header file contains macros typedefs and function declaration specific to ++* the Marvell Gigabit Ethernet Controller. ++* ++* DEPENDENCIES: ++* None. ++* ++*******************************************************************************/ ++ ++#ifndef __mvEthGbe_h__ ++#define __mvEthGbe_h__ ++ ++extern MV_BOOL ethDescInSram; ++extern MV_BOOL ethDescSwCoher; ++extern ETH_PORT_CTRL* ethPortCtrl[]; ++ ++static INLINE MV_ULONG ethDescVirtToPhy(ETH_QUEUE_CTRL* pQueueCtrl, MV_U8* pDesc) ++{ ++#if defined (ETH_DESCR_IN_SRAM) ++ if( ethDescInSram ) ++ return mvSramVirtToPhy(pDesc); ++ else ++#endif /* ETH_DESCR_IN_SRAM */ ++ return (pQueueCtrl->descBuf.bufPhysAddr + (pDesc - pQueueCtrl->descBuf.bufVirtPtr)); ++} ++/* Return port handler */ ++#define mvEthPortHndlGet(port) ethPortCtrl[port] ++ ++/* Used as WA for HW/SW race on TX */ ++static INLINE int mvEthPortTxEnable(void* pPortHndl, int queue, int max_deep) ++{ ++ int deep = 0; ++ MV_U32 txCurrReg, txEnReg; ++ ETH_TX_DESC* pTxLastDesc; ++ ETH_QUEUE_CTRL* pQueueCtrl; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ ++ txEnReg = MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)); ++ if( (txEnReg & MV_32BIT_LE_FAST(ETH_TXQ_ENABLE_MASK)) == 0) ++ { ++ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) = pPortCtrl->portTxQueueCmdReg; ++ return 0; ++ } ++ ++ pQueueCtrl = &pPortCtrl->txQueue[queue]; ++ pTxLastDesc = pQueueCtrl->pCurrentDescr; ++ txCurrReg = MV_REG_READ(ETH_TX_CUR_DESC_PTR_REG(pPortCtrl->portNo, queue)); ++ if(ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pTxLastDesc) == txCurrReg) ++ { ++ /* All descriptors are processed, no chance for race */ ++ return 0; ++ } ++ ++ /* Check distance betwee HW and SW location: */ ++ /* If distance between HW and SW pointers is less than max_deep descriptors */ ++ /* Race condition is possible, so wait end of TX and restart TXQ */ ++ while(deep < max_deep) ++ { ++ pTxLastDesc = TX_PREV_DESC_PTR(pTxLastDesc, pQueueCtrl); ++ if(ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pTxLastDesc) == txCurrReg) ++ { ++ int count = 0; ++ ++ while( (txEnReg & MV_32BIT_LE_FAST(ETH_TXQ_ENABLE_MASK)) != 0) ++ { ++ count++; ++ if(count > 10000) ++ { ++ mvOsPrintf("mvEthPortTxEnable: timeout - TXQ_CMD=0x%08x\n", ++ MV_REG_READ(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) ); ++ break; ++ } ++ txEnReg = MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)); ++ } ++ ++ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) = pPortCtrl->portTxQueueCmdReg; ++ return count; ++ } ++ deep++; ++ } ++ /* Distance between HW and SW pointers is more than max_deep descriptors, */ ++ /* So NO race condition - do nothing */ ++ return -1; ++} ++ ++ ++/* defines */ ++#define ETH_CSUM_MIN_BYTE_COUNT 72 ++ ++/* Tailgate and Kirwood have only 2K TX FIFO */ ++#if (MV_ETH_VERSION == 2) || (MV_ETH_VERSION == 4) ++#define ETH_CSUM_MAX_BYTE_COUNT 1600 ++#else ++#define ETH_CSUM_MAX_BYTE_COUNT 9*1024 ++#endif /* MV_ETH_VERSION */ ++ ++#define ETH_MV_HEADER_SIZE 2 ++#define ETH_MV_TX_EN ++ ++/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */ ++#define MIN_TX_BUFF_LOAD 8 ++#define TX_BUF_OFFSET_IN_DESC (ETH_TX_DESC_ALIGNED_SIZE - MIN_TX_BUFF_LOAD) ++ ++/* Default port configuration value */ ++#define PORT_CONFIG_VALUE \ ++ ETH_DEF_RX_QUEUE_MASK(0) | \ ++ ETH_DEF_RX_ARP_QUEUE_MASK(0) | \ ++ ETH_DEF_RX_TCP_QUEUE_MASK(0) | \ ++ ETH_DEF_RX_UDP_QUEUE_MASK(0) | \ ++ ETH_DEF_RX_BPDU_QUEUE_MASK(0) | \ ++ ETH_RX_CHECKSUM_WITH_PSEUDO_HDR ++ ++/* Default port extend configuration value */ ++#define PORT_CONFIG_EXTEND_VALUE 0 ++ ++#define PORT_SERIAL_CONTROL_VALUE \ ++ ETH_DISABLE_FC_AUTO_NEG_MASK | \ ++ BIT9 | \ ++ ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ ++ ETH_MAX_RX_PACKET_1552BYTE | \ ++ ETH_SET_FULL_DUPLEX_MASK ++ ++#define PORT_SERIAL_CONTROL_100MB_FORCE_VALUE \ ++ ETH_FORCE_LINK_PASS_MASK | \ ++ ETH_DISABLE_DUPLEX_AUTO_NEG_MASK | \ ++ ETH_DISABLE_FC_AUTO_NEG_MASK | \ ++ BIT9 | \ ++ ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ ++ ETH_DISABLE_SPEED_AUTO_NEG_MASK | \ ++ ETH_SET_FULL_DUPLEX_MASK | \ ++ ETH_SET_MII_SPEED_100_MASK | \ ++ ETH_MAX_RX_PACKET_1552BYTE ++ ++ ++#define PORT_SERIAL_CONTROL_1000MB_FORCE_VALUE \ ++ ETH_FORCE_LINK_PASS_MASK | \ ++ ETH_DISABLE_DUPLEX_AUTO_NEG_MASK | \ ++ ETH_DISABLE_FC_AUTO_NEG_MASK | \ ++ BIT9 | \ ++ ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ ++ ETH_DISABLE_SPEED_AUTO_NEG_MASK | \ ++ ETH_SET_FULL_DUPLEX_MASK | \ ++ ETH_SET_GMII_SPEED_1000_MASK | \ ++ ETH_MAX_RX_PACKET_1552BYTE ++ ++#define PORT_SERIAL_CONTROL_SGMII_IBAN_VALUE \ ++ ETH_DISABLE_FC_AUTO_NEG_MASK | \ ++ BIT9 | \ ++ ETH_IN_BAND_AN_EN_MASK | \ ++ ETH_DO_NOT_FORCE_LINK_FAIL_MASK | \ ++ ETH_MAX_RX_PACKET_1552BYTE ++ ++/* Function headers: */ ++MV_VOID mvEthSetSpecialMcastTable(int portNo, int queue); ++MV_STATUS mvEthArpRxQueue(void* pPortHandle, int arpQueue); ++MV_STATUS mvEthUdpRxQueue(void* pPortHandle, int udpQueue); ++MV_STATUS mvEthTcpRxQueue(void* pPortHandle, int tcpQueue); ++MV_STATUS mvEthMacAddrGet(int portNo, unsigned char *pAddr); ++MV_VOID mvEthSetOtherMcastTable(int portNo, int queue); ++MV_STATUS mvEthHeaderModeSet(void* pPortHandle, MV_ETH_HEADER_MODE headerMode); ++/* Interrupt Coalesting functions */ ++MV_U32 mvEthRxCoalSet(void* pPortHndl, MV_U32 uSec); ++MV_U32 mvEthTxCoalSet(void* pPortHndl, MV_U32 uSec); ++MV_STATUS mvEthCoalGet(void* pPortHndl, MV_U32* pRxCoal, MV_U32* pTxCoal); ++ ++/******************************************************************************/ ++/* Data Flow functions */ ++/******************************************************************************/ ++static INLINE void mvEthPortTxRestart(void* pPortHndl) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ ++ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(pPortCtrl->portNo)) = pPortCtrl->portTxQueueCmdReg; ++} ++ ++/* Get number of Free resources in specific TX queue */ ++static INLINE int mvEthTxResourceGet(void* pPortHndl, int txQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ ++ return (pPortCtrl->txQueue[txQueue].resource); ++} ++ ++/* Get number of Free resources in specific RX queue */ ++static INLINE int mvEthRxResourceGet(void* pPortHndl, int rxQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ ++ return (pPortCtrl->rxQueue[rxQueue].resource); ++} ++ ++static INLINE int mvEthTxQueueIsFull(void* pPortHndl, int txQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ ++ if(pPortCtrl->txQueue[txQueue].resource == 0) ++ return MV_TRUE; ++ ++ return MV_FALSE; ++} ++ ++/* Get number of Free resources in specific RX queue */ ++static INLINE int mvEthRxQueueIsFull(void* pPortHndl, int rxQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->rxQueue[rxQueue]; ++ ++ if( (pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) && ++ (pQueueCtrl->resource != 0) ) ++ return MV_TRUE; ++ ++ return MV_FALSE; ++} ++ ++static INLINE int mvEthTxQueueIsEmpty(void* pPortHndl, int txQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ ETH_QUEUE_CTRL* pQueueCtrl = &pPortCtrl->txQueue[txQueue]; ++ ++ if( (pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) && ++ (pQueueCtrl->resource != 0) ) ++ { ++ return MV_TRUE; ++ } ++ return MV_FALSE; ++} ++ ++/* Get number of Free resources in specific RX queue */ ++static INLINE int mvEthRxQueueIsEmpty(void* pPortHndl, int rxQueue) ++{ ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pPortHndl; ++ ++ if(pPortCtrl->rxQueue[rxQueue].resource == 0) ++ return MV_TRUE; ++ ++ return MV_FALSE; ++} ++ ++/******************************************************************************* ++* mvEthPortTx - Send an Ethernet packet ++* ++* DESCRIPTION: ++* This routine send a given packet described by pPktInfo parameter. ++* Single buffer only. ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet Port handler. ++* int txQueue - Number of Tx queue. ++* MV_PKT_INFO *pPktInfo - User packet to send. ++* ++* RETURN: ++* MV_NO_RESOURCE - No enough resources to send this packet. ++* MV_ERROR - Unexpected Fatal error. ++* MV_OK - Packet send successfully. ++* ++*******************************************************************************/ ++static INLINE MV_STATUS mvEthPortTx(void* pEthPortHndl, int txQueue, MV_PKT_INFO* pPktInfo) ++{ ++ ETH_TX_DESC* pTxCurrDesc; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; ++ ETH_QUEUE_CTRL* pQueueCtrl; ++ int portNo; ++ MV_BUF_INFO* pBufInfo = pPktInfo->pFrags; ++ ++#ifdef ETH_DEBUG ++ if(pPortCtrl->portState != MV_ACTIVE) ++ return MV_BAD_STATE; ++#endif /* ETH_DEBUG */ ++ ++ portNo = pPortCtrl->portNo; ++ pQueueCtrl = &pPortCtrl->txQueue[txQueue]; ++ ++ /* Get the Tx Desc ring indexes */ ++ pTxCurrDesc = pQueueCtrl->pCurrentDescr; ++ ++ /* Check if there is enough resources to send the packet */ ++ if(pQueueCtrl->resource == 0) ++ return MV_NO_RESOURCE; ++ ++ pTxCurrDesc->byteCnt = pBufInfo->dataSize; ++ ++ /* Flash Buffer */ ++ if(pPktInfo->pktSize != 0) ++ { ++#ifdef MV_NETBSD ++ pTxCurrDesc->bufPtr = pBufInfo->bufPhysAddr; ++ ETH_PACKET_CACHE_FLUSH(pBufInfo->bufVirtPtr, pPktInfo->pktSize); ++#else ++ pTxCurrDesc->bufPtr = ETH_PACKET_CACHE_FLUSH(pBufInfo->bufVirtPtr, pPktInfo->pktSize); ++#endif ++ pPktInfo->pktSize = 0; ++ } ++ else ++ pTxCurrDesc->bufPtr = pBufInfo->bufPhysAddr; ++ ++ pTxCurrDesc->returnInfo = (MV_ULONG)pPktInfo; ++ ++ /* There is only one buffer in the packet */ ++ /* The OSG might set some bits for checksum offload, so add them to first descriptor */ ++ pTxCurrDesc->cmdSts = pPktInfo->status | ++ ETH_BUFFER_OWNED_BY_DMA | ++ ETH_TX_GENERATE_CRC_MASK | ++ ETH_TX_ENABLE_INTERRUPT_MASK | ++ ETH_TX_ZERO_PADDING_MASK | ++ ETH_TX_FIRST_DESC_MASK | ++ ETH_TX_LAST_DESC_MASK; ++ ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); ++ ++ pQueueCtrl->resource--; ++ pQueueCtrl->pCurrentDescr = TX_NEXT_DESC_PTR(pTxCurrDesc, pQueueCtrl); ++ ++ /* Apply send command */ ++ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(portNo)) = pPortCtrl->portTxQueueCmdReg; ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvEthPortSgTx - Send an Ethernet packet ++* ++* DESCRIPTION: ++* This routine send a given packet described by pBufInfo parameter. It ++* supports transmitting of a packet spaned over multiple buffers. ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet Port handler. ++* int txQueue - Number of Tx queue. ++* MV_PKT_INFO *pPktInfo - User packet to send. ++* ++* RETURN: ++* MV_NO_RESOURCE - No enough resources to send this packet. ++* MV_ERROR - Unexpected Fatal error. ++* MV_OK - Packet send successfully. ++* ++*******************************************************************************/ ++static INLINE MV_STATUS mvEthPortSgTx(void* pEthPortHndl, int txQueue, MV_PKT_INFO* pPktInfo) ++{ ++ ETH_TX_DESC* pTxFirstDesc; ++ ETH_TX_DESC* pTxCurrDesc; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; ++ ETH_QUEUE_CTRL* pQueueCtrl; ++ int portNo, bufCount; ++ MV_BUF_INFO* pBufInfo = pPktInfo->pFrags; ++ MV_U8* pTxBuf; ++ ++#ifdef ETH_DEBUG ++ if(pPortCtrl->portState != MV_ACTIVE) ++ return MV_BAD_STATE; ++#endif /* ETH_DEBUG */ ++ ++ portNo = pPortCtrl->portNo; ++ pQueueCtrl = &pPortCtrl->txQueue[txQueue]; ++ ++ /* Get the Tx Desc ring indexes */ ++ pTxCurrDesc = pQueueCtrl->pCurrentDescr; ++ ++ /* Check if there is enough resources to send the packet */ ++ if(pQueueCtrl->resource < pPktInfo->numFrags) ++ return MV_NO_RESOURCE; ++ ++ /* Remember first desc */ ++ pTxFirstDesc = pTxCurrDesc; ++ ++ bufCount = 0; ++ while(MV_TRUE) ++ { ++ if(pBufInfo[bufCount].dataSize <= MIN_TX_BUFF_LOAD) ++ { ++ /* Buffers with a payload smaller than MIN_TX_BUFF_LOAD (8 bytes) must be aligned */ ++ /* to 64-bit boundary. Two options here: */ ++ /* 1) Usually, copy the payload to the reserved 8 bytes inside descriptor. */ ++ /* 2) In the Half duplex workaround, the reserved 8 bytes inside descriptor are used */ ++ /* as a pointer to the aligned buffer, copy the small payload to this buffer. */ ++ pTxBuf = ((MV_U8*)pTxCurrDesc)+TX_BUF_OFFSET_IN_DESC; ++ mvOsBCopy(pBufInfo[bufCount].bufVirtPtr, pTxBuf, pBufInfo[bufCount].dataSize); ++ pTxCurrDesc->bufPtr = ethDescVirtToPhy(pQueueCtrl, pTxBuf); ++ } ++ else ++ { ++ /* Flash Buffer */ ++#ifdef MV_NETBSD ++ pTxCurrDesc->bufPtr = pBufInfo[bufCount].bufPhysAddr; ++ ETH_PACKET_CACHE_FLUSH(pBufInfo[bufCount].bufVirtPtr, pBufInfo[bufCount].dataSize); ++#else ++ pTxCurrDesc->bufPtr = ETH_PACKET_CACHE_FLUSH(pBufInfo[bufCount].bufVirtPtr, pBufInfo[bufCount].dataSize); ++#endif ++ } ++ ++ pTxCurrDesc->byteCnt = pBufInfo[bufCount].dataSize; ++ bufCount++; ++ ++ if(bufCount >= pPktInfo->numFrags) ++ break; ++ ++ if(bufCount > 1) ++ { ++ /* There is middle buffer of the packet Not First and Not Last */ ++ pTxCurrDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA; ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); ++ } ++ /* Go to next descriptor and next buffer */ ++ pTxCurrDesc = TX_NEXT_DESC_PTR(pTxCurrDesc, pQueueCtrl); ++ } ++ /* Set last desc with DMA ownership and interrupt enable. */ ++ pTxCurrDesc->returnInfo = (MV_ULONG)pPktInfo; ++ if(bufCount == 1) ++ { ++ /* There is only one buffer in the packet */ ++ /* The OSG might set some bits for checksum offload, so add them to first descriptor */ ++ pTxCurrDesc->cmdSts = pPktInfo->status | ++ ETH_BUFFER_OWNED_BY_DMA | ++ ETH_TX_GENERATE_CRC_MASK | ++ ETH_TX_ENABLE_INTERRUPT_MASK | ++ ETH_TX_ZERO_PADDING_MASK | ++ ETH_TX_FIRST_DESC_MASK | ++ ETH_TX_LAST_DESC_MASK; ++ ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); ++ } ++ else ++ { ++ /* Last but not First */ ++ pTxCurrDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA | ++ ETH_TX_ENABLE_INTERRUPT_MASK | ++ ETH_TX_ZERO_PADDING_MASK | ++ ETH_TX_LAST_DESC_MASK; ++ ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxCurrDesc); ++ ++ /* Update First when more than one buffer in the packet */ ++ /* The OSG might set some bits for checksum offload, so add them to first descriptor */ ++ pTxFirstDesc->cmdSts = pPktInfo->status | ++ ETH_BUFFER_OWNED_BY_DMA | ++ ETH_TX_GENERATE_CRC_MASK | ++ ETH_TX_FIRST_DESC_MASK; ++ ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pTxFirstDesc); ++ } ++ /* Update txQueue state */ ++ pQueueCtrl->resource -= bufCount; ++ pQueueCtrl->pCurrentDescr = TX_NEXT_DESC_PTR(pTxCurrDesc, pQueueCtrl); ++ ++ /* Apply send command */ ++ MV_REG_VALUE(ETH_TX_QUEUE_COMMAND_REG(portNo)) = pPortCtrl->portTxQueueCmdReg; ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvEthPortTxDone - Free all used Tx descriptors and mBlks. ++* ++* DESCRIPTION: ++* This routine returns the transmitted packet information to the caller. ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet Port handler. ++* int txQueue - Number of Tx queue. ++* ++* OUTPUT: ++* MV_PKT_INFO *pPktInfo - Pointer to packet was sent. ++* ++* RETURN: ++* MV_NOT_FOUND - No transmitted packets to return. Transmit in progress. ++* MV_EMPTY - No transmitted packets to return. TX Queue is empty. ++* MV_ERROR - Unexpected Fatal error. ++* MV_OK - There is transmitted packet in the queue, ++* 'pPktInfo' filled with relevant information. ++* ++*******************************************************************************/ ++static INLINE MV_PKT_INFO* mvEthPortTxDone(void* pEthPortHndl, int txQueue) ++{ ++ ETH_TX_DESC* pTxCurrDesc; ++ ETH_TX_DESC* pTxUsedDesc; ++ ETH_QUEUE_CTRL* pQueueCtrl; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; ++ MV_PKT_INFO* pPktInfo; ++ MV_U32 commandStatus; ++ ++ pQueueCtrl = &pPortCtrl->txQueue[txQueue]; ++ ++ pTxUsedDesc = pQueueCtrl->pUsedDescr; ++ pTxCurrDesc = pQueueCtrl->pCurrentDescr; ++ ++ while(MV_TRUE) ++ { ++ /* No more used descriptors */ ++ commandStatus = pTxUsedDesc->cmdSts; ++ if (commandStatus & (ETH_BUFFER_OWNED_BY_DMA)) ++ { ++ ETH_DESCR_INV(pPortCtrl, pTxUsedDesc); ++ return NULL; ++ } ++ if( (pTxUsedDesc == pTxCurrDesc) && ++ (pQueueCtrl->resource != 0) ) ++ { ++ return NULL; ++ } ++ pQueueCtrl->resource++; ++ pQueueCtrl->pUsedDescr = TX_NEXT_DESC_PTR(pTxUsedDesc, pQueueCtrl); ++ if(commandStatus & (ETH_TX_LAST_DESC_MASK)) ++ { ++ pPktInfo = (MV_PKT_INFO*)pTxUsedDesc->returnInfo; ++ pPktInfo->status = commandStatus; ++ return pPktInfo; ++ } ++ pTxUsedDesc = pQueueCtrl->pUsedDescr; ++ } ++} ++ ++/******************************************************************************* ++* mvEthPortRx - Get new received packets from Rx queue. ++* ++* DESCRIPTION: ++* This routine returns the received data to the caller. There is no ++* data copying during routine operation. All information is returned ++* using pointer to packet information struct passed from the caller. ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet Port handler. ++* int rxQueue - Number of Rx queue. ++* ++* OUTPUT: ++* MV_PKT_INFO *pPktInfo - Pointer to received packet. ++* ++* RETURN: ++* MV_NO_RESOURCE - No free resources in RX queue. ++* MV_ERROR - Unexpected Fatal error. ++* MV_OK - New packet received and 'pBufInfo' structure filled ++* with relevant information. ++* ++*******************************************************************************/ ++static INLINE MV_PKT_INFO* mvEthPortRx(void* pEthPortHndl, int rxQueue) ++{ ++ ETH_RX_DESC *pRxCurrDesc; ++ MV_U32 commandStatus; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; ++ ETH_QUEUE_CTRL* pQueueCtrl; ++ MV_PKT_INFO* pPktInfo; ++ ++ pQueueCtrl = &(pPortCtrl->rxQueue[rxQueue]); ++ ++ /* Check resources */ ++ if(pQueueCtrl->resource == 0) ++ { ++ mvOsPrintf("ethPortRx: no more resources\n"); ++ return NULL; ++ } ++ while(MV_TRUE) ++ { ++ /* Get the Rx Desc ring 'curr and 'used' indexes */ ++ pRxCurrDesc = pQueueCtrl->pCurrentDescr; ++ ++ commandStatus = pRxCurrDesc->cmdSts; ++ if (commandStatus & (ETH_BUFFER_OWNED_BY_DMA)) ++ { ++ /* Nothing to receive... */ ++ ETH_DESCR_INV(pPortCtrl, pRxCurrDesc); ++ return NULL; ++ } ++ ++ /* Valid RX only if FIRST and LAST bits are set */ ++ if( (commandStatus & (ETH_RX_LAST_DESC_MASK | ETH_RX_FIRST_DESC_MASK)) == ++ (ETH_RX_LAST_DESC_MASK | ETH_RX_FIRST_DESC_MASK) ) ++ { ++ pPktInfo = (MV_PKT_INFO*)pRxCurrDesc->returnInfo; ++ pPktInfo->pFrags->dataSize = pRxCurrDesc->byteCnt - 4; ++ pPktInfo->status = commandStatus; ++ pPktInfo->fragIP = pRxCurrDesc->bufSize & ETH_RX_IP_FRAGMENTED_FRAME_MASK; ++ ++ pQueueCtrl->resource--; ++ /* Update 'curr' in data structure */ ++ pQueueCtrl->pCurrentDescr = RX_NEXT_DESC_PTR(pRxCurrDesc, pQueueCtrl); ++ ++#ifdef INCLUDE_SYNC_BARR ++ mvCpuIfSyncBarr(DRAM_TARGET); ++#endif ++ return pPktInfo; ++ } ++ else ++ { ++ ETH_RX_DESC* pRxUsedDesc = pQueueCtrl->pUsedDescr; ++ ++#ifdef ETH_DEBUG ++ mvOsPrintf("ethDrv: Unexpected Jumbo frame: " ++ "status=0x%08x, byteCnt=%d, pData=0x%x\n", ++ commandStatus, pRxCurrDesc->byteCnt, pRxCurrDesc->bufPtr); ++#endif /* ETH_DEBUG */ ++ ++ /* move buffer from pCurrentDescr position to pUsedDescr position */ ++ pRxUsedDesc->bufPtr = pRxCurrDesc->bufPtr; ++ pRxUsedDesc->returnInfo = pRxCurrDesc->returnInfo; ++ pRxUsedDesc->bufSize = pRxCurrDesc->bufSize & ETH_RX_BUFFER_MASK; ++ ++ /* Return the descriptor to DMA ownership */ ++ pRxUsedDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA | ++ ETH_RX_ENABLE_INTERRUPT_MASK; ++ ++ /* Flush descriptor and CPU pipe */ ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxUsedDesc); ++ ++ /* Move the used descriptor pointer to the next descriptor */ ++ pQueueCtrl->pUsedDescr = RX_NEXT_DESC_PTR(pRxUsedDesc, pQueueCtrl); ++ pQueueCtrl->pCurrentDescr = RX_NEXT_DESC_PTR(pRxCurrDesc, pQueueCtrl); ++ } ++ } ++} ++ ++/******************************************************************************* ++* mvEthPortRxDone - Returns a Rx buffer back to the Rx ring. ++* ++* DESCRIPTION: ++* This routine returns a Rx buffer back to the Rx ring. ++* ++* INPUT: ++* void* pEthPortHndl - Ethernet Port handler. ++* int rxQueue - Number of Rx queue. ++* MV_PKT_INFO *pPktInfo - Pointer to received packet. ++* ++* RETURN: ++* MV_ERROR - Unexpected Fatal error. ++* MV_OUT_OF_RANGE - RX queue is already FULL, so this buffer can't be ++* returned to this queue. ++* MV_FULL - Buffer returned successfully and RX queue became full. ++* More buffers should not be returned at the time. ++* MV_OK - Buffer returned successfully and there are more free ++* places in the queue. ++* ++*******************************************************************************/ ++static INLINE MV_STATUS mvEthPortRxDone(void* pEthPortHndl, int rxQueue, MV_PKT_INFO *pPktInfo) ++{ ++ ETH_RX_DESC* pRxUsedDesc; ++ ETH_QUEUE_CTRL* pQueueCtrl; ++ ETH_PORT_CTRL* pPortCtrl = (ETH_PORT_CTRL*)pEthPortHndl; ++ ++ pQueueCtrl = &pPortCtrl->rxQueue[rxQueue]; ++ ++ /* Get 'used' Rx descriptor */ ++ pRxUsedDesc = pQueueCtrl->pUsedDescr; ++ ++ /* Check that ring is not FULL */ ++ if( (pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) && ++ (pQueueCtrl->resource != 0) ) ++ { ++ mvOsPrintf("%s %d: out of range Error resource=%d, curr=%p, used=%p\n", ++ __FUNCTION__, pPortCtrl->portNo, pQueueCtrl->resource, ++ pQueueCtrl->pCurrentDescr, pQueueCtrl->pUsedDescr); ++ return MV_OUT_OF_RANGE; ++ } ++ ++ pRxUsedDesc->bufPtr = pPktInfo->pFrags->bufPhysAddr; ++ pRxUsedDesc->returnInfo = (MV_ULONG)pPktInfo; ++ pRxUsedDesc->bufSize = pPktInfo->pFrags->bufSize & ETH_RX_BUFFER_MASK; ++ ++ /* Invalidate data buffer accordingly with pktSize */ ++ if(pPktInfo->pktSize != 0) ++ { ++ ETH_PACKET_CACHE_INVALIDATE(pPktInfo->pFrags->bufVirtPtr, pPktInfo->pktSize); ++ pPktInfo->pktSize = 0; ++ } ++ ++ /* Return the descriptor to DMA ownership */ ++ pRxUsedDesc->cmdSts = ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT_MASK; ++ ++ /* Flush descriptor and CPU pipe */ ++ ETH_DESCR_FLUSH_INV(pPortCtrl, pRxUsedDesc); ++ ++ pQueueCtrl->resource++; ++ ++ /* Move the used descriptor pointer to the next descriptor */ ++ pQueueCtrl->pUsedDescr = RX_NEXT_DESC_PTR(pRxUsedDesc, pQueueCtrl); ++ ++ /* If ring became Full return MV_FULL */ ++ if(pQueueCtrl->pUsedDescr == pQueueCtrl->pCurrentDescr) ++ return MV_FULL; ++ ++ return MV_OK; ++} ++ ++ ++#endif /* __mvEthGbe_h__ */ ++ ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/mvEthRegs.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,700 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCmvEthRegsh ++#define __INCmvEthRegsh ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++ ++/****************************************/ ++/* Ethernet Unit Registers */ ++/****************************************/ ++#define ETH_REG_BASE MV_ETH_REG_BASE ++ ++#define ETH_PHY_ADDR_REG(port) (ETH_REG_BASE(port) + 0x000) ++#define ETH_SMI_REG(port) (ETH_REG_BASE(port) + 0x004) ++#define ETH_UNIT_DEF_ADDR_REG(port) (ETH_REG_BASE(port) + 0x008) ++#define ETH_UNIT_DEF_ID_REG(port) (ETH_REG_BASE(port) + 0x00c) ++#define ETH_UNIT_RESERVED(port) (ETH_REG_BASE(port) + 0x014) ++#define ETH_UNIT_INTR_CAUSE_REG(port) (ETH_REG_BASE(port) + 0x080) ++#define ETH_UNIT_INTR_MASK_REG(port) (ETH_REG_BASE(port) + 0x084) ++ ++ ++#define ETH_UNIT_ERROR_ADDR_REG(port) (ETH_REG_BASE(port) + 0x094) ++#define ETH_UNIT_INT_ADDR_ERROR_REG(port) (ETH_REG_BASE(port) + 0x098) ++#define ETH_UNIT_CONTROL_REG(port) (ETH_REG_BASE(port) + 0x0B0) ++ ++#define ETH_PORT_CONFIG_REG(port) (ETH_REG_BASE(port) + 0x400) ++#define ETH_PORT_CONFIG_EXTEND_REG(port) (ETH_REG_BASE(port) + 0x404) ++#define ETH_MII_SERIAL_PARAM_REG(port) (ETH_REG_BASE(port) + 0x408) ++#define ETH_GMII_SERIAL_PARAM_REG(port) (ETH_REG_BASE(port) + 0x40c) ++#define ETH_VLAN_ETHER_TYPE_REG(port) (ETH_REG_BASE(port) + 0x410) ++#define ETH_MAC_ADDR_LOW_REG(port) (ETH_REG_BASE(port) + 0x414) ++#define ETH_MAC_ADDR_HIGH_REG(port) (ETH_REG_BASE(port) + 0x418) ++#define ETH_SDMA_CONFIG_REG(port) (ETH_REG_BASE(port) + 0x41c) ++#define ETH_DIFF_SERV_PRIO_REG(port, code) (ETH_REG_BASE(port) + 0x420 + ((code)<<2)) ++#define ETH_PORT_SERIAL_CTRL_REG(port) (ETH_REG_BASE(port) + 0x43c) ++#define ETH_VLAN_TAG_TO_PRIO_REG(port) (ETH_REG_BASE(port) + 0x440) ++#define ETH_PORT_STATUS_REG(port) (ETH_REG_BASE(port) + 0x444) ++ ++#define ETH_RX_QUEUE_COMMAND_REG(port) (ETH_REG_BASE(port) + 0x680) ++#define ETH_TX_QUEUE_COMMAND_REG(port) (ETH_REG_BASE(port) + 0x448) ++ ++#define ETH_PORT_SERIAL_CTRL_1_REG(port) (ETH_REG_BASE(port) + 0x44c) ++#define ETH_PORT_STATUS_1_REG(port) (ETH_REG_BASE(port) + 0x450) ++#define ETH_PORT_MARVELL_HEADER_REG(port) (ETH_REG_BASE(port) + 0x454) ++#define ETH_PORT_FIFO_PARAMS_REG(port) (ETH_REG_BASE(port) + 0x458) ++#define ETH_MAX_TOKEN_BUCKET_SIZE_REG(port) (ETH_REG_BASE(port) + 0x45c) ++#define ETH_INTR_CAUSE_REG(port) (ETH_REG_BASE(port) + 0x460) ++#define ETH_INTR_CAUSE_EXT_REG(port) (ETH_REG_BASE(port) + 0x464) ++#define ETH_INTR_MASK_REG(port) (ETH_REG_BASE(port) + 0x468) ++#define ETH_INTR_MASK_EXT_REG(port) (ETH_REG_BASE(port) + 0x46c) ++#define ETH_TX_FIFO_URGENT_THRESH_REG(port) (ETH_REG_BASE(port) + 0x474) ++#define ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (ETH_REG_BASE(port) + 0x47c) ++#define ETH_RX_DISCARD_PKTS_CNTR_REG(port) (ETH_REG_BASE(port) + 0x484) ++#define ETH_RX_OVERRUN_PKTS_CNTR_REG(port) (ETH_REG_BASE(port) + 0x488) ++#define ETH_INTERNAL_ADDR_ERROR_REG(port) (ETH_REG_BASE(port) + 0x494) ++#define ETH_TX_FIXED_PRIO_CFG_REG(port) (ETH_REG_BASE(port) + 0x4dc) ++#define ETH_TX_TOKEN_RATE_CFG_REG(port) (ETH_REG_BASE(port) + 0x4e0) ++#define ETH_TX_QUEUE_COMMAND1_REG(port) (ETH_REG_BASE(port) + 0x4e4) ++#define ETH_MAX_TRANSMIT_UNIT_REG(port) (ETH_REG_BASE(port) + 0x4e8) ++#define ETH_TX_TOKEN_BUCKET_SIZE_REG(port) (ETH_REG_BASE(port) + 0x4ec) ++#define ETH_TX_TOKEN_BUCKET_COUNT_REG(port) (ETH_REG_BASE(port) + 0x780) ++#define ETH_RX_DESCR_STAT_CMD_REG(port, q) (ETH_REG_BASE(port) + 0x600 + ((q)<<4)) ++#define ETH_RX_BYTE_COUNT_REG(port, q) (ETH_REG_BASE(port) + 0x604 + ((q)<<4)) ++#define ETH_RX_BUF_PTR_REG(port, q) (ETH_REG_BASE(port) + 0x608 + ((q)<<4)) ++#define ETH_RX_CUR_DESC_PTR_REG(port, q) (ETH_REG_BASE(port) + 0x60c + ((q)<<4)) ++#define ETH_TX_CUR_DESC_PTR_REG(port, q) (ETH_REG_BASE(port) + 0x6c0 + ((q)<<2)) ++ ++#define ETH_TXQ_TOKEN_COUNT_REG(port, q) (ETH_REG_BASE(port) + 0x700 + ((q)<<4)) ++#define ETH_TXQ_TOKEN_CFG_REG(port, q) (ETH_REG_BASE(port) + 0x704 + ((q)<<4)) ++#define ETH_TXQ_ARBITER_CFG_REG(port, q) (ETH_REG_BASE(port) + 0x708 + ((q)<<4)) ++ ++#if (MV_ETH_VERSION >= 4) ++#define ETH_TXQ_CMD_1_REG(port) (ETH_REG_BASE(port) + 0x4E4) ++#define ETH_EJP_TX_HI_IPG_REG(port) (ETH_REG_BASE(port) + 0x7A8) ++#define ETH_EJP_TX_LO_IPG_REG(port) (ETH_REG_BASE(port) + 0x7B8) ++#define ETH_EJP_HI_TKN_LO_PKT_REG(port) (ETH_REG_BASE(port) + 0x7C0) ++#define ETH_EJP_HI_TKN_ASYNC_PKT_REG(port) (ETH_REG_BASE(port) + 0x7C4) ++#define ETH_EJP_LO_TKN_ASYNC_PKT_REG(port) (ETH_REG_BASE(port) + 0x7C8) ++#define ETH_EJP_TX_SPEED_REG(port) (ETH_REG_BASE(port) + 0x7D0) ++#endif /* MV_ETH_VERSION >= 4 */ ++ ++#define ETH_MIB_COUNTERS_BASE(port) (ETH_REG_BASE(port) + 0x1000) ++#define ETH_DA_FILTER_SPEC_MCAST_BASE(port) (ETH_REG_BASE(port) + 0x1400) ++#define ETH_DA_FILTER_OTH_MCAST_BASE(port) (ETH_REG_BASE(port) + 0x1500) ++#define ETH_DA_FILTER_UCAST_BASE(port) (ETH_REG_BASE(port) + 0x1600) ++ ++/* Phy address register definitions */ ++#define ETH_PHY_ADDR_OFFS 0 ++#define ETH_PHY_ADDR_MASK (0x1f <= 4) ++#define ETH_TX_EJP_RESET_BIT 0 ++#define ETH_TX_EJP_RESET_MASK (1 << ETH_TX_EJP_RESET_BIT) ++ ++#define ETH_TX_EJP_ENABLE_BIT 2 ++#define ETH_TX_EJP_ENABLE_MASK (1 << ETH_TX_EJP_ENABLE_BIT) ++ ++#define ETH_TX_LEGACY_WRR_BIT 3 ++#define ETH_TX_LEGACY_WRR_MASK (1 << ETH_TX_LEGACY_WRR_BIT) ++#endif /* (MV_ETH_VERSION >= 4) */ ++ ++/***** BITs of Ethernet Port Status reg (PSR) *****/ ++#define ETH_LINK_UP_BIT 1 ++#define ETH_LINK_UP_MASK (1<= 4) ++MV_STATUS mvEthEjpModeSet(void* pPortHandle, int mode); ++#endif /* (MV_ETH_VERSION >= 4) */ ++ ++void mvEthStatusGet(void* pPortHandle, MV_ETH_PORT_STATUS* pStatus); ++ ++/* Marvell Header control */ ++MV_STATUS mvEthHeaderModeSet(void* pPortHandle, MV_ETH_HEADER_MODE headerMode); ++ ++/* PHY routines */ ++void mvEthPhyAddrSet(void* pPortHandle, int phyAddr); ++int mvEthPhyAddrGet(void* pPortHandle); ++ ++/* Power management routines */ ++void mvEthPortPowerDown(int port); ++void mvEthPortPowerUp(int port); ++ ++/******************** ETH PRIVATE ************************/ ++ ++/*#define UNCACHED_TX_BUFFERS*/ ++/*#define UNCACHED_RX_BUFFERS*/ ++ ++ ++/* Port attributes */ ++/* Size of a Tx/Rx descriptor used in chain list data structure */ ++#define ETH_RX_DESC_ALIGNED_SIZE 32 ++#define ETH_TX_DESC_ALIGNED_SIZE 32 ++ ++#define TX_DISABLE_TIMEOUT_MSEC 1000 ++#define RX_DISABLE_TIMEOUT_MSEC 1000 ++#define TX_FIFO_EMPTY_TIMEOUT_MSEC 10000 ++#define PORT_DISABLE_WAIT_TCLOCKS 5000 ++ ++/* Macros that save access to desc in order to find next desc pointer */ ++#define RX_NEXT_DESC_PTR(pRxDescr, pQueueCtrl) \ ++ ((pRxDescr) == (pQueueCtrl)->pLastDescr) ? \ ++ (ETH_RX_DESC*)((pQueueCtrl)->pFirstDescr) : \ ++ (ETH_RX_DESC*)(((MV_ULONG)(pRxDescr)) + ETH_RX_DESC_ALIGNED_SIZE) ++ ++#define TX_NEXT_DESC_PTR(pTxDescr, pQueueCtrl) \ ++ ((pTxDescr) == (pQueueCtrl)->pLastDescr) ? \ ++ (ETH_TX_DESC*)((pQueueCtrl)->pFirstDescr) : \ ++ (ETH_TX_DESC*)(((MV_ULONG)(pTxDescr)) + ETH_TX_DESC_ALIGNED_SIZE) ++ ++#define RX_PREV_DESC_PTR(pRxDescr, pQueueCtrl) \ ++ ((pRxDescr) == (pQueueCtrl)->pFirstDescr) ? \ ++ (ETH_RX_DESC*)((pQueueCtrl)->pLastDescr) : \ ++ (ETH_RX_DESC*)(((MV_ULONG)(pRxDescr)) - ETH_RX_DESC_ALIGNED_SIZE) ++ ++#define TX_PREV_DESC_PTR(pTxDescr, pQueueCtrl) \ ++ ((pTxDescr) == (pQueueCtrl)->pFirstDescr) ? \ ++ (ETH_TX_DESC*)((pQueueCtrl)->pLastDescr) : \ ++ (ETH_TX_DESC*)(((MV_ULONG)(pTxDescr)) - ETH_TX_DESC_ALIGNED_SIZE) ++ ++ ++/* Queue specific information */ ++typedef struct ++{ ++ void* pFirstDescr; ++ void* pLastDescr; ++ void* pCurrentDescr; ++ void* pUsedDescr; ++ int resource; ++ MV_BUF_INFO descBuf; ++} ETH_QUEUE_CTRL; ++ ++ ++/* Ethernet port specific infomation */ ++typedef struct _ethPortCtrl ++{ ++ int portNo; ++ ETH_QUEUE_CTRL rxQueue[MV_ETH_RX_Q_NUM]; /* Rx ring resource */ ++ ETH_QUEUE_CTRL txQueue[MV_ETH_TX_Q_NUM]; /* Tx ring resource */ ++ ++ MV_ETH_PORT_CFG portConfig; ++ MV_ETH_RX_Q_CFG rxQueueConfig[MV_ETH_RX_Q_NUM]; ++ MV_ETH_TX_Q_CFG txQueueConfig[MV_ETH_TX_Q_NUM]; ++ ++ /* Register images - For DP */ ++ MV_U32 portTxQueueCmdReg; /* Port active Tx queues summary */ ++ MV_U32 portRxQueueCmdReg; /* Port active Rx queues summary */ ++ ++ MV_STATE portState; ++ ++ MV_U8 mcastCount[256]; ++ MV_U32* hashPtr; ++ void *osHandle; ++} ETH_PORT_CTRL; ++ ++/************** MACROs ****************/ ++ ++/* MACROs to Flush / Invalidate TX / RX Buffers */ ++#if (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) && !defined(UNCACHED_TX_BUFFERS) ++# define ETH_PACKET_CACHE_FLUSH(pAddr, size) \ ++ mvOsCacheClear(NULL, (pAddr), (size)); \ ++ /*CPU_PIPE_FLUSH;*/ ++#else ++# define ETH_PACKET_CACHE_FLUSH(pAddr, size) \ ++ mvOsIoVirtToPhy(NULL, (pAddr)); ++#endif /* ETHER_DRAM_COHER == MV_CACHE_COHER_SW */ ++ ++#if ( (ETHER_DRAM_COHER == MV_CACHE_COHER_SW) && !defined(UNCACHED_RX_BUFFERS) ) ++# define ETH_PACKET_CACHE_INVALIDATE(pAddr, size) \ ++ mvOsCacheInvalidate (NULL, (pAddr), (size)); \ ++ /*CPU_PIPE_FLUSH;*/ ++#else ++# define ETH_PACKET_CACHE_INVALIDATE(pAddr, size) ++#endif /* ETHER_DRAM_COHER == MV_CACHE_COHER_SW && !UNCACHED_RX_BUFFERS */ ++ ++#ifdef ETH_DESCR_UNCACHED ++ ++#define ETH_DESCR_FLUSH_INV(pPortCtrl, pDescr) ++#define ETH_DESCR_INV(pPortCtrl, pDescr) ++ ++#else ++ ++#define ETH_DESCR_FLUSH_INV(pPortCtrl, pDescr) \ ++ mvOsCacheLineFlushInv(pPortCtrl->osHandle, (MV_ULONG)(pDescr)) ++ ++#define ETH_DESCR_INV(pPortCtrl, pDescr) \ ++ mvOsCacheLineInv(pPortCtrl->osHandle, (MV_ULONG)(pDescr)) ++ ++#endif /* ETH_DESCR_UNCACHED */ ++ ++#include "eth/gbe/mvEthGbe.h" ++ ++#endif /* __mvEth_h__ */ ++ ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvCompVer.txt linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvCompVer.txt +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvCompVer.txt 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvCompVer.txt 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,4 @@ ++Global HAL Version: FEROCEON_HAL_3_1_7 ++Unit HAL Version: 3.1.4 ++Description: This component includes an implementation of the unit HAL drivers ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.c linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.c +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,362 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#include "gpp/mvGpp.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++/* defines */ ++#ifdef MV_DEBUG ++ #define DB(x) x ++#else ++ #define DB(x) ++#endif ++ ++static MV_VOID gppRegSet(MV_U32 group, MV_U32 regOffs,MV_U32 mask,MV_U32 value); ++ ++/******************************************************************************* ++* mvGppTypeSet - Enable a GPP (OUT) pin ++* ++* DESCRIPTION: ++* ++* INPUT: ++* group - GPP group number ++* mask - 32bit mask value. Each set bit in the mask means that the type ++* of corresponding GPP will be set. Other GPPs are ignored. ++* value - 32bit value that describes GPP type per pin. ++* ++* OUTPUT: ++* None. ++* ++* EXAMPLE: ++* Set GPP8 to input and GPP15 to output. ++* mvGppTypeSet(0, (GPP8 | GPP15), ++* ((MV_GPP_IN & GPP8) | (MV_GPP_OUT & GPP15)) ); ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_STATUS mvGppTypeSet(MV_U32 group, MV_U32 mask, MV_U32 value) ++{ ++ if (group >= MV_GPP_MAX_GROUP) ++ { ++ DB(mvOsPrintf("mvGppTypeSet: ERR. invalid group number \n")); ++ return MV_BAD_PARAM; ++ } ++ ++ gppRegSet(group, GPP_DATA_OUT_EN_REG(group), mask, value); ++ ++ /* Workaround for Erratum FE-MISC-70*/ ++ if(mvCtrlRevGet()==MV_88F6XXX_A0_REV && (group == 1)) ++ { ++ mask &= 0x2; ++ gppRegSet(0, GPP_DATA_OUT_EN_REG(0), mask, value); ++ } /*End of WA*/ ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvGppBlinkEn - Set a GPP (IN) Pin list to blink every ~100ms ++* ++* DESCRIPTION: ++* ++* INPUT: ++* group - GPP group number ++* mask - 32bit mask value. Each set bit in the mask means that the type ++* of corresponding GPP will be set. Other GPPs are ignored. ++* value - 32bit value that describes GPP blink per pin. ++* ++* OUTPUT: ++* None. ++* ++* EXAMPLE: ++* Set GPP8 to be static and GPP15 to be blinking. ++* mvGppBlinkEn(0, (GPP8 | GPP15), ++* ((MV_GPP_OUT_STATIC & GPP8) | (MV_GPP_OUT_BLINK & GPP15)) ); ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_STATUS mvGppBlinkEn(MV_U32 group, MV_U32 mask, MV_U32 value) ++{ ++ if (group >= MV_GPP_MAX_GROUP) ++ { ++ DB(mvOsPrintf("mvGppBlinkEn: ERR. invalid group number \n")); ++ return MV_BAD_PARAM; ++ } ++ ++ gppRegSet(group, GPP_BLINK_EN_REG(group), mask, value); ++ ++ return MV_OK; ++ ++} ++/******************************************************************************* ++* mvGppPolaritySet - Set a GPP (IN) Pin list Polarity mode ++* ++* DESCRIPTION: ++* ++* INPUT: ++* group - GPP group number ++* mask - 32bit mask value. Each set bit in the mask means that the type ++* of corresponding GPP will be set. Other GPPs are ignored. ++* value - 32bit value that describes GPP polarity per pin. ++* ++* OUTPUT: ++* None. ++* ++* EXAMPLE: ++* Set GPP8 to the actual pin value and GPP15 to be inverted. ++* mvGppPolaritySet(0, (GPP8 | GPP15), ++* ((MV_GPP_IN_ORIGIN & GPP8) | (MV_GPP_IN_INVERT & GPP15)) ); ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_STATUS mvGppPolaritySet(MV_U32 group, MV_U32 mask, MV_U32 value) ++{ ++ if (group >= MV_GPP_MAX_GROUP) ++ { ++ DB(mvOsPrintf("mvGppPolaritySet: ERR. invalid group number \n")); ++ return MV_BAD_PARAM; ++ } ++ ++ gppRegSet(group, GPP_DATA_IN_POL_REG(group), mask, value); ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvGppPolarityGet - Get a value of relevant bits from GPP Polarity register. ++* ++* DESCRIPTION: ++* ++* INPUT: ++* group - GPP group number ++* mask - 32bit mask value. Each set bit in the mask means that the ++* returned value is valid for it. ++* ++* OUTPUT: ++* None. ++* ++* EXAMPLE: ++* Get GPP8 and GPP15 value. ++* mvGppPolarityGet(0, (GPP8 | GPP15)); ++* ++* RETURN: ++* 32bit value that describes GPP polatity mode per pin. ++* ++*******************************************************************************/ ++MV_U32 mvGppPolarityGet(MV_U32 group, MV_U32 mask) ++{ ++ MV_U32 regVal; ++ ++ if (group >= MV_GPP_MAX_GROUP) ++ { ++ DB(mvOsPrintf("mvGppActiveSet: Error invalid group number \n")); ++ return MV_ERROR; ++ } ++ regVal = MV_REG_READ(GPP_DATA_IN_POL_REG(group)); ++ ++ return (regVal & mask); ++} ++ ++/******************************************************************************* ++* mvGppValueGet - Get a GPP Pin list value. ++* ++* DESCRIPTION: ++* This function get GPP value. ++* ++* INPUT: ++* group - GPP group number ++* mask - 32bit mask value. Each set bit in the mask means that the ++* returned value is valid for it. ++* ++* OUTPUT: ++* None. ++* ++* EXAMPLE: ++* Get GPP8 and GPP15 value. ++* mvGppValueGet(0, (GPP8 | GPP15)); ++* ++* RETURN: ++* 32bit value that describes GPP activity mode per pin. ++* ++*******************************************************************************/ ++MV_U32 mvGppValueGet(MV_U32 group, MV_U32 mask) ++{ ++ MV_U32 gppData; ++ ++ gppData = MV_REG_READ(GPP_DATA_IN_REG(group)); ++ ++ gppData &= mask; ++ ++ return gppData; ++ ++} ++ ++/******************************************************************************* ++* mvGppValueSet - Set a GPP Pin list value. ++* ++* DESCRIPTION: ++* This function set value for given GPP pin list. ++* ++* INPUT: ++* group - GPP group number ++* mask - 32bit mask value. Each set bit in the mask means that the ++* value of corresponding GPP will be set accordingly. Other GPP ++* are not affected. ++* value - 32bit value that describes GPP value per pin. ++* ++* OUTPUT: ++* None. ++* ++* EXAMPLE: ++* Set GPP8 value of '0' and GPP15 value of '1'. ++* mvGppActiveSet(0, (GPP8 | GPP15), ((0 & GPP8) | (GPP15)) ); ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_STATUS mvGppValueSet (MV_U32 group, MV_U32 mask, MV_U32 value) ++{ ++ MV_U32 outEnable, tmp; ++ MV_U32 i; ++ ++ if (group >= MV_GPP_MAX_GROUP) ++ { ++ DB(mvOsPrintf("mvGppValueSet: Error invalid group number \n")); ++ return MV_BAD_PARAM; ++ } ++ ++ /* verify that the gpp pin is configured as output */ ++ /* Note that in the register out enabled -> bit = '0'. */ ++ outEnable = ~MV_REG_READ(GPP_DATA_OUT_EN_REG(group)); ++ ++ /* Workaround for Erratum FE-MISC-70*/ ++ if(mvCtrlRevGet()==MV_88F6XXX_A0_REV && (group == 1)) ++ { ++ tmp = ~MV_REG_READ(GPP_DATA_OUT_EN_REG(0)); ++ outEnable &= 0xfffffffd; ++ outEnable |= (tmp & 0x2); ++ } /*End of WA*/ ++ ++ for (i = 0 ; i < 32 ;i++) ++ { ++ if (((mask & (1 << i)) & (outEnable & (1 << i))) != (mask & (1 << i))) ++ { ++ mvOsPrintf("mvGppValueSet: Err. An attempt to set output "\ ++ "value to GPP %d in input mode.\n", i); ++ return MV_ERROR; ++ } ++ } ++ ++ gppRegSet(group, GPP_DATA_OUT_REG(group), mask, value); ++ ++ return MV_OK; ++ ++} ++/******************************************************************************* ++* gppRegSet - Set a specific GPP pin on a specific GPP register ++* ++* DESCRIPTION: ++* This function set a specific GPP pin on a specific GPP register ++* ++* INPUT: ++* regOffs - GPP Register offset ++* group - GPP group number ++* mask - 32bit mask value. Each set bit in the mask means that the ++* value of corresponding GPP will be set accordingly. Other GPP ++* are not affected. ++* value - 32bit value that describes GPP value per pin. ++* ++* OUTPUT: ++* None. ++* ++* EXAMPLE: ++* Set GPP8 value of '0' and GPP15 value of '1'. ++* mvGppActiveSet(0, (GPP8 | GPP15), ((0 & GPP8) | (1 & GPP15)) ); ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++static MV_VOID gppRegSet (MV_U32 group, MV_U32 regOffs,MV_U32 mask,MV_U32 value) ++{ ++ MV_U32 gppData; ++ ++ gppData = MV_REG_READ(regOffs); ++ ++ gppData &= ~mask; ++ ++ gppData |= (value & mask); ++ ++ MV_REG_WRITE(regOffs, gppData); ++} ++ ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGpp.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,118 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvGppH ++#define __INCmvGppH ++ ++#include "mvCommon.h" ++#include "mvOs.h" ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++#include "gpp/mvGppRegs.h" ++ ++/* These macros describes the GPP type. Each of the GPPs pins can */ ++/* be assigned to act as a general purpose input or output pin. */ ++#define MV_GPP_IN 0xFFFFFFFF /* GPP input */ ++#define MV_GPP_OUT 0 /* GPP output */ ++ ++ ++/* These macros describes the GPP Out Enable. */ ++#define MV_GPP_OUT_DIS 0xFFFFFFFF /* Out pin disabled*/ ++#define MV_GPP_OUT_EN 0 /* Out pin enabled*/ ++ ++/* These macros describes the GPP Out Blinking. */ ++/* When set and the corresponding bit in GPIO Data Out Enable Control */ ++/* Register is enabled, the GPIO pin blinks every ~100 ms (a period of */ ++/* 2^24 TCLK clocks). */ ++#define MV_GPP_OUT_BLINK 0xFFFFFFFF /* Out pin blinking*/ ++#define MV_GPP_OUT_STATIC 0 /* Out pin static*/ ++ ++ ++/* These macros describes the GPP Polarity. */ ++/* When set to 1 GPIO Data In Register reflects the inverted value of the */ ++/* corresponding pin. */ ++ ++#define MV_GPP_IN_INVERT 0xFFFFFFFF /* Inverted value is got*/ ++#define MV_GPP_IN_ORIGIN 0 /* original value is got*/ ++ ++/* mvGppTypeSet - Set PP pin mode (IN or OUT) */ ++MV_STATUS mvGppTypeSet(MV_U32 group, MV_U32 mask, MV_U32 value); ++ ++/* mvGppBlinkEn - Set a GPP (IN) Pin list to blink every ~100ms */ ++MV_STATUS mvGppBlinkEn(MV_U32 group, MV_U32 mask, MV_U32 value); ++ ++/* mvGppPolaritySet - Set a GPP (IN) Pin list Polarity mode. */ ++MV_STATUS mvGppPolaritySet(MV_U32 group, MV_U32 mask, MV_U32 value); ++ ++/* mvGppPolarityGet - Get the Polarity of a GPP Pin */ ++MV_U32 mvGppPolarityGet(MV_U32 group, MV_U32 mask); ++ ++/* mvGppValueGet - Get a GPP Pin list value.*/ ++MV_U32 mvGppValueGet(MV_U32 group, MV_U32 mask); ++ ++ ++/* mvGppValueSet - Set a GPP Pin list value. */ ++MV_STATUS mvGppValueSet (MV_U32 group, MV_U32 mask, MV_U32 value); ++ ++#endif /* #ifndef __INCmvGppH */ ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGppRegs.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGppRegs.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGppRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/mvGppRegs.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,116 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvGppRegsH ++#define __INCmvGppRegsH ++ ++#define MV_GPP0 BIT0 ++#define MV_GPP1 BIT1 ++#define MV_GPP2 BIT2 ++#define MV_GPP3 BIT3 ++#define MV_GPP4 BIT4 ++#define MV_GPP5 BIT5 ++#define MV_GPP6 BIT6 ++#define MV_GPP7 BIT7 ++#define MV_GPP8 BIT8 ++#define MV_GPP9 BIT9 ++#define MV_GPP10 BIT10 ++#define MV_GPP11 BIT11 ++#define MV_GPP12 BIT12 ++#define MV_GPP13 BIT13 ++#define MV_GPP14 BIT14 ++#define MV_GPP15 BIT15 ++#define MV_GPP16 BIT16 ++#define MV_GPP17 BIT17 ++#define MV_GPP18 BIT18 ++#define MV_GPP19 BIT19 ++#define MV_GPP20 BIT20 ++#define MV_GPP21 BIT21 ++#define MV_GPP22 BIT22 ++#define MV_GPP23 BIT23 ++#define MV_GPP24 BIT24 ++#define MV_GPP25 BIT25 ++#define MV_GPP26 BIT26 ++#define MV_GPP27 BIT27 ++#define MV_GPP28 BIT28 ++#define MV_GPP29 BIT29 ++#define MV_GPP30 BIT30 ++#define MV_GPP31 BIT31 ++ ++ ++/* registers offsets */ ++ ++#define GPP_DATA_OUT_REG(grp) ((grp == 0) ? 0x10100 : 0x10140) ++#define GPP_DATA_OUT_EN_REG(grp) ((grp == 0) ? 0x10104 : 0x10144) ++#define GPP_BLINK_EN_REG(grp) ((grp == 0) ? 0x10108 : 0x10148) ++#define GPP_DATA_IN_POL_REG(grp) ((grp == 0) ? 0x1010C : 0x1014c) ++#define GPP_DATA_IN_REG(grp) ((grp == 0) ? 0x10110 : 0x10150) ++#define GPP_INT_CAUSE_REG(grp) ((grp == 0) ? 0x10114 : 0x10154) ++#define GPP_INT_MASK_REG(grp) ((grp == 0) ? 0x10118 : 0x10158) ++#define GPP_INT_LVL_REG(grp) ((grp == 0) ? 0x1011c : 0x1015c) ++ ++#define GPP_DATA_OUT_SET_REG 0x10120 ++#define GPP_DATA_OUT_CLEAR_REG 0x10124 ++ ++#endif /* #ifndef __INCmvGppRegsH */ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvCompVer.txt linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvCompVer.txt +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvCompVer.txt 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvCompVer.txt 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,4 @@ ++Global HAL Version: FEROCEON_HAL_3_1_7 ++Unit HAL Version: 3.1.2 ++Description: This component includes an implementation of the unit HAL drivers ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.c linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.c +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,1047 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++#include "pci/mvPci.h" ++ ++#include "ctrlEnv/mvCtrlEnvLib.h" ++ ++/* defines */ ++#ifdef MV_DEBUG ++ #define DB(x) x ++#else ++ #define DB(x) ++#endif ++ ++ ++ ++MV_VOID mvPciHalInit(MV_U32 pciIf, MV_PCI_MOD pciIfmod) ++{ ++ if (MV_PCI_MOD_HOST == pciIfmod) ++ { ++ ++ mvPciLocalBusNumSet(pciIf, PCI_HOST_BUS_NUM(pciIf)); ++ mvPciLocalDevNumSet(pciIf, PCI_HOST_DEV_NUM(pciIf)); ++ ++ /* Local device master Enable */ ++ mvPciMasterEnable(pciIf, MV_TRUE); ++ ++ /* Local device slave Enable */ ++ mvPciSlaveEnable(pciIf, mvPciLocalBusNumGet(pciIf), ++ mvPciLocalDevNumGet(pciIf), MV_TRUE); ++ } ++ /* enable CPU-2-PCI ordering */ ++ MV_REG_BIT_SET(PCI_CMD_REG(0), PCR_CPU_TO_PCI_ORDER_EN); ++} ++ ++/******************************************************************************* ++* mvPciCommandSet - Set PCI comman register value. ++* ++* DESCRIPTION: ++* This function sets a given PCI interface with its command register ++* value. ++* ++* INPUT: ++* pciIf - PCI interface number. ++* command - 32bit value to be written to comamnd register. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM if pciIf is not in range otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPciCommandSet(MV_U32 pciIf, MV_U32 command) ++{ ++ MV_U32 locBusNum, locDevNum, regVal; ++ ++ locBusNum = mvPciLocalBusNumGet(pciIf); ++ locDevNum = mvPciLocalDevNumGet(pciIf); ++ ++ /* Parameter checking */ ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciCommandSet: ERR. Invalid PCI IF num %d\n", pciIf); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Set command register */ ++ MV_REG_WRITE(PCI_CMD_REG(pciIf), command); ++ ++ /* Upodate device max outstanding split tarnsaction */ ++ if ((command & PCR_CPU_TO_PCI_ORDER_EN) && ++ (command & PCR_PCI_TO_CPU_ORDER_EN)) ++ { ++ /* Read PCI-X command register */ ++ regVal = mvPciConfigRead (pciIf, locBusNum, locDevNum, 0, PCIX_COMMAND); ++ ++ /* clear bits 22:20 */ ++ regVal &= 0xff8fffff; ++ ++ /* set reset value */ ++ regVal |= (0x3 << 20); ++ ++ /* Write back the value */ ++ mvPciConfigWrite (pciIf, locBusNum, locDevNum, 0, PCIX_COMMAND, regVal); ++ } ++ ++ return MV_OK; ++ ++ ++} ++ ++ ++/******************************************************************************* ++* mvPciModeGet - Get PCI interface mode. ++* ++* DESCRIPTION: ++* This function returns the given PCI interface mode. ++* ++* INPUT: ++* pciIf - PCI interface number. ++* ++* OUTPUT: ++* pPciMode - Pointer to PCI mode structure. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPciModeGet(MV_U32 pciIf, MV_PCI_MODE *pPciMode) ++{ ++ MV_U32 pciMode; ++ ++ /* Parameter checking */ ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciModeGet: ERR. Invalid PCI interface %d\n", pciIf); ++ return MV_BAD_PARAM; ++ } ++ if (NULL == pPciMode) ++ { ++ mvOsPrintf("mvPciModeGet: ERR. pPciMode = NULL \n"); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Read pci mode register */ ++ pciMode = MV_REG_READ(PCI_MODE_REG(pciIf)); ++ ++ switch (pciMode & PMR_PCI_MODE_MASK) ++ { ++ case PMR_PCI_MODE_CONV: ++ pPciMode->pciType = MV_PCI_CONV; ++ ++ if (MV_REG_READ(PCI_DLL_CTRL_REG(pciIf)) & PDC_DLL_EN) ++ { ++ pPciMode->pciSpeed = 66000000; /* 66MHZ */ ++ } ++ else ++ { ++ pPciMode->pciSpeed = 33000000; /* 33MHZ */ ++ } ++ ++ break; ++ ++ case PMR_PCI_MODE_PCIX_66MHZ: ++ pPciMode->pciType = MV_PCIX; ++ pPciMode->pciSpeed = 66000000; /* 66MHZ */ ++ break; ++ ++ case PMR_PCI_MODE_PCIX_100MHZ: ++ pPciMode->pciType = MV_PCIX; ++ pPciMode->pciSpeed = 100000000; /* 100MHZ */ ++ break; ++ ++ case PMR_PCI_MODE_PCIX_133MHZ: ++ pPciMode->pciType = MV_PCIX; ++ pPciMode->pciSpeed = 133000000; /* 133MHZ */ ++ break; ++ ++ default: ++ { ++ mvOsPrintf("mvPciModeGet: ERR. Non existing mode !!\n"); ++ return MV_ERROR; ++ } ++ } ++ ++ switch (pciMode & PMR_PCI_64_MASK) ++ { ++ case PMR_PCI_64_64BIT: ++ pPciMode->pciWidth = MV_PCI_64; ++ break; ++ ++ case PMR_PCI_64_32BIT: ++ pPciMode->pciWidth = MV_PCI_32; ++ break; ++ ++ default: ++ { ++ mvOsPrintf("mvPciModeGet: ERR. Non existing mode !!\n"); ++ return MV_ERROR; ++ } ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvPciRetrySet - Set PCI retry counters ++* ++* DESCRIPTION: ++* This function specifies the number of times the PCI controller ++* retries a transaction before it quits. ++* Applies to the PCI Master when acting as a requester. ++* Applies to the PCI slave when acting as a completer (PCI-X mode). ++* A 0x00 value means a "retry forever". ++* ++* INPUT: ++* pciIf - PCI interface number. ++* counter - Number of times PCI controller retry. Use counter value ++* up to PRR_RETRY_CNTR_MAX. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPciRetrySet(MV_U32 pciIf, MV_U32 counter) ++{ ++ MV_U32 pciRetry; ++ ++ /* Parameter checking */ ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciRetrySet: ERR. Invalid PCI interface %d\n", pciIf); ++ return MV_BAD_PARAM; ++ } ++ ++ if (counter >= PRR_RETRY_CNTR_MAX) ++ { ++ mvOsPrintf("mvPciRetrySet: ERR. Invalid counter: %d\n", counter); ++ return MV_BAD_PARAM; ++ ++ } ++ ++ /* Reading PCI retry register */ ++ pciRetry = MV_REG_READ(PCI_RETRY_REG(pciIf)); ++ ++ pciRetry &= ~PRR_RETRY_CNTR_MASK; ++ ++ pciRetry |= (counter << PRR_RETRY_CNTR_OFFS); ++ ++ /* write new value */ ++ MV_REG_WRITE(PCI_RETRY_REG(pciIf), pciRetry); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvPciDiscardTimerSet - Set PCI discard timer ++* ++* DESCRIPTION: ++* This function set PCI discard timer. ++* In conventional PCI mode: ++* Specifies the number of PCLK cycles the PCI slave keeps a non-accessed ++* read buffers (non-completed delayed read) before invalidate the buffer. ++* Set to '0' to disable the timer. The PCI slave waits for delayed ++* read completion forever. ++* In PCI-X mode: ++* Specifies the number of PCLK cycles the PCI master waits for split ++* completion transaction, before it invalidates the pre-allocated read ++* buffer. ++* Set to '0' to disable the timer. The PCI master waits for split ++* completion forever. ++* NOTE: Must be set to a number greater than MV_PCI_MAX_DISCARD_CLK, ++* unless using the "wait for ever" setting 0x0. ++* NOTE: Must not be updated while there are pending read requests. ++* ++* INPUT: ++* pciIf - PCI interface number. ++* pClkCycles - Number of PCI clock cycles. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPciDiscardTimerSet(MV_U32 pciIf, MV_U32 pClkCycles) ++{ ++ MV_U32 pciDiscardTimer; ++ ++ /* Parameter checking */ ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciDiscardTimerSet: ERR. Invalid PCI interface %d\n", ++ pciIf); ++ return MV_BAD_PARAM; ++ } ++ ++ if (pClkCycles >= PDTR_TIMER_MIN) ++ { ++ mvOsPrintf("mvPciDiscardTimerSet: ERR. Invalid Clk value: %d\n", ++ pClkCycles); ++ return MV_BAD_PARAM; ++ ++ } ++ ++ /* Read PCI Discard Timer */ ++ pciDiscardTimer = MV_REG_READ(PCI_DISCARD_TIMER_REG(pciIf)); ++ ++ pciDiscardTimer &= ~PDTR_TIMER_MASK; ++ ++ pciDiscardTimer |= (pClkCycles << PDTR_TIMER_OFFS); ++ ++ /* Write new value */ ++ MV_REG_WRITE(PCI_DISCARD_TIMER_REG(pciIf), pciDiscardTimer); ++ ++ return MV_OK; ++ ++} ++ ++/* PCI Arbiter routines */ ++ ++/******************************************************************************* ++* mvPciArbEnable - PCI arbiter enable/disable ++* ++* DESCRIPTION: ++* This fuction enable/disables a given PCI interface arbiter. ++* NOTE: Arbiter setting can not be changed while in work. It should only ++* be set once. ++* INPUT: ++* pciIf - PCI interface number. ++* enable - Enable/disable parameter. If enable = MV_TRUE then enable. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_STATUS mvPciArbEnable(MV_U32 pciIf, MV_BOOL enable) ++{ ++ MV_U32 regVal; ++ ++ /* Parameter checking */ ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciArbEnable: ERR. Invalid PCI interface %d\n", pciIf); ++ return MV_ERROR; ++ } ++ ++ /* Set PCI Arbiter Control register according to default configuration */ ++ regVal = MV_REG_READ(PCI_ARBITER_CTRL_REG(pciIf)); ++ ++ /* Make sure arbiter disabled before changing its values */ ++ MV_REG_BIT_RESET(PCI_ARBITER_CTRL_REG(pciIf), PACR_ARB_ENABLE); ++ ++ regVal &= ~PCI_ARBITER_CTRL_DEFAULT_MASK; ++ ++ regVal |= PCI_ARBITER_CTRL_DEFAULT; /* Set default configuration */ ++ ++ if (MV_TRUE == enable) ++ { ++ regVal |= PACR_ARB_ENABLE; ++ } ++ else ++ { ++ regVal &= ~PACR_ARB_ENABLE; ++ } ++ ++ /* Write to register */ ++ MV_REG_WRITE(PCI_ARBITER_CTRL_REG(pciIf), regVal); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvPciArbParkDis - Disable arbiter parking on agent ++* ++* DESCRIPTION: ++* This function disables the PCI arbiter from parking on the given agent ++* list. ++* ++* INPUT: ++* pciIf - PCI interface number. ++* pciAgentMask - When a bit in the mask is set to '1', parking on ++* the associated PCI master is disabled. Mask bit ++* refers to bit 0 - 6. For example disable parking on PCI ++* agent 3 set pciAgentMask 0x4 (bit 3 is set). ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++MV_STATUS mvPciArbParkDis(MV_U32 pciIf, MV_U32 pciAgentMask) ++{ ++ MV_U32 pciArbiterCtrl; ++ ++ /* Parameter checking */ ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciArbParkDis: ERR. Invalid PCI interface %d\n", pciIf); ++ return MV_ERROR; ++ } ++ ++ /* Reading Arbiter Control register */ ++ pciArbiterCtrl = MV_REG_READ(PCI_ARBITER_CTRL_REG(pciIf)); ++ ++ /* Arbiter must be disabled before changing parking */ ++ MV_REG_BIT_RESET(PCI_ARBITER_CTRL_REG(pciIf), PACR_ARB_ENABLE); ++ ++ /* do the change */ ++ pciArbiterCtrl &= ~PACR_PARK_DIS_MASK; ++ pciArbiterCtrl |= (pciAgentMask << PACR_PARK_DIS_OFFS); ++ ++ /* writing new value ( if th earbiter was enabled before the change */ ++ /* here it will be reenabled */ ++ MV_REG_WRITE(PCI_ARBITER_CTRL_REG(pciIf), pciArbiterCtrl); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvPciArbBrokDetectSet - Set PCI arbiter broken detection ++* ++* DESCRIPTION: ++* This function sets the maximum number of cycles that the arbiter ++* waits for a PCI master to respond to its grant assertion. If a ++* PCI agent fails to respond within this time, the PCI arbiter aborts ++* the transaction and performs a new arbitration cycle. ++* NOTE: Value must be greater than '1' for conventional PCI and ++* greater than '5' for PCI-X. ++* ++* INPUT: ++* pciIf - PCI interface number. ++* pClkCycles - Number of PCI clock cycles. If equal to '0' the broken ++* master detection is disabled. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPciArbBrokDetectSet(MV_U32 pciIf, MV_U32 pClkCycles) ++{ ++ MV_U32 pciArbiterCtrl; ++ MV_U32 pciMode; ++ ++ /* Parameter checking */ ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciArbBrokDetectSet: ERR. Invalid PCI interface %d\n", ++ pciIf); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Checking PCI mode and if pClkCycles is legal value */ ++ pciMode = MV_REG_READ(PCI_MODE_REG(pciIf)); ++ pciMode &= PMR_PCI_MODE_MASK; ++ ++ if (PMR_PCI_MODE_CONV == pciMode) ++ { ++ if (pClkCycles < PACR_BROKEN_VAL_CONV_MIN) ++ return MV_ERROR; ++ } ++ else ++ { ++ if (pClkCycles < PACR_BROKEN_VAL_PCIX_MIN) ++ return MV_ERROR; ++ } ++ ++ pClkCycles <<= PACR_BROKEN_VAL_OFFS; ++ ++ /* Reading Arbiter Control register */ ++ pciArbiterCtrl = MV_REG_READ(PCI_ARBITER_CTRL_REG(pciIf)); ++ pciArbiterCtrl &= ~PACR_BROKEN_VAL_MASK; ++ pciArbiterCtrl |= pClkCycles; ++ ++ /* Arbiter must be disabled before changing broken detection */ ++ MV_REG_BIT_RESET(PCI_ARBITER_CTRL_REG(pciIf), PACR_ARB_ENABLE); ++ ++ /* writing new value ( if th earbiter was enabled before the change */ ++ /* here it will be reenabled */ ++ ++ MV_REG_WRITE(PCI_ARBITER_CTRL_REG(pciIf), pciArbiterCtrl); ++ ++ return MV_OK; ++} ++ ++/* PCI configuration space read write */ ++ ++/******************************************************************************* ++* mvPciConfigRead - Read from configuration space ++* ++* DESCRIPTION: ++* This function performs a 32 bit read from PCI configuration space. ++* It supports both type 0 and type 1 of Configuration Transactions ++* (local and over bridge). In order to read from local bus segment, use ++* bus number retrieved from mvPciLocalBusNumGet(). Other bus numbers ++* will result configuration transaction of type 1 (over bridge). ++* ++* INPUT: ++* pciIf - PCI interface number. ++* bus - PCI segment bus number. ++* dev - PCI device number. ++* func - Function number. ++* regOffs - Register offset. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit register data, 0xffffffff on error ++* ++*******************************************************************************/ ++MV_U32 mvPciConfigRead (MV_U32 pciIf, MV_U32 bus, MV_U32 dev, MV_U32 func, ++ MV_U32 regOff) ++{ ++ MV_U32 pciData = 0; ++ ++ /* Parameter checking */ ++ if (PCI_DEFAULT_IF != pciIf) ++ { ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciConfigRead: ERR. Invalid PCI interface %d\n",pciIf); ++ return 0xFFFFFFFF; ++ } ++ } ++ ++ if (dev >= MAX_PCI_DEVICES) ++ { ++ DB(mvOsPrintf("mvPciConfigRead: ERR. device number illigal %d\n", dev)); ++ return 0xFFFFFFFF; ++ } ++ ++ if (func >= MAX_PCI_FUNCS) ++ { ++ DB(mvOsPrintf("mvPciConfigRead: ERR. function number illigal %d\n", func)); ++ return 0xFFFFFFFF; ++ } ++ ++ if (bus >= MAX_PCI_BUSSES) ++ { ++ DB(mvOsPrintf("mvPciConfigRead: ERR. bus number illigal %d\n", bus)); ++ return MV_ERROR; ++ } ++ ++ ++ /* Creating PCI address to be passed */ ++ pciData |= (bus << PCAR_BUS_NUM_OFFS); ++ pciData |= (dev << PCAR_DEVICE_NUM_OFFS); ++ pciData |= (func << PCAR_FUNC_NUM_OFFS); ++ pciData |= (regOff & PCAR_REG_NUM_MASK); ++ ++ pciData |= PCAR_CONFIG_EN; ++ ++ /* Write the address to the PCI configuration address register */ ++ MV_REG_WRITE(PCI_CONFIG_ADDR_REG(pciIf), pciData); ++ ++ /* In order to let the PCI controller absorbed the address of the read */ ++ /* transaction we perform a validity check that the address was written */ ++ if(pciData != MV_REG_READ(PCI_CONFIG_ADDR_REG(pciIf))) ++ { ++ return MV_ERROR; ++ } ++ /* Read the Data returned in the PCI Data register */ ++ pciData = MV_REG_READ(PCI_CONFIG_DATA_REG(pciIf)); ++ ++ return pciData; ++} ++ ++/******************************************************************************* ++* mvPciConfigWrite - Write to configuration space ++* ++* DESCRIPTION: ++* This function performs a 32 bit write to PCI configuration space. ++* It supports both type 0 and type 1 of Configuration Transactions ++* (local and over bridge). In order to write to local bus segment, use ++* bus number retrieved from mvPciLocalBusNumGet(). Other bus numbers ++* will result configuration transaction of type 1 (over bridge). ++* ++* INPUT: ++* pciIf - PCI interface number. ++* bus - PCI segment bus number. ++* dev - PCI device number. ++* func - Function number. ++* regOffs - Register offset. ++* data - 32bit data. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPciConfigWrite(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func, MV_U32 regOff, MV_U32 data) ++{ ++ MV_U32 pciData = 0; ++ ++ /* Parameter checking */ ++ if (PCI_DEFAULT_IF != pciIf) ++ { ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciConfigWrite: ERR. Invalid PCI interface %d\n", ++ pciIf); ++ return 0xFFFFFFFF; ++ } ++ } ++ ++ if (dev >= MAX_PCI_DEVICES) ++ { ++ mvOsPrintf("mvPciConfigWrite: ERR. device number illigal %d\n",dev); ++ return MV_BAD_PARAM; ++ } ++ ++ if (func >= MAX_PCI_FUNCS) ++ { ++ mvOsPrintf("mvPciConfigWrite: ERR. function number illigal %d\n", func); ++ return MV_ERROR; ++ } ++ ++ if (bus >= MAX_PCI_BUSSES) ++ { ++ mvOsPrintf("mvPciConfigWrite: ERR. bus number illigal %d\n", bus); ++ return MV_ERROR; ++ } ++ ++ /* Creating PCI address to be passed */ ++ pciData |= (bus << PCAR_BUS_NUM_OFFS); ++ pciData |= (dev << PCAR_DEVICE_NUM_OFFS); ++ pciData |= (func << PCAR_FUNC_NUM_OFFS); ++ pciData |= (regOff & PCAR_REG_NUM_MASK); ++ ++ pciData |= PCAR_CONFIG_EN; ++ ++ /* Write the address to the PCI configuration address register */ ++ MV_REG_WRITE(PCI_CONFIG_ADDR_REG(pciIf), pciData); ++ ++ /* In order to let the PCI controller absorbed the address of the read */ ++ /* transaction we perform a validity check that the address was written */ ++ if(pciData != MV_REG_READ(PCI_CONFIG_ADDR_REG(pciIf))) ++ { ++ return MV_ERROR; ++ } ++ ++ /* Write the Data passed to the PCI Data register */ ++ MV_REG_WRITE(PCI_CONFIG_DATA_REG(pciIf), data); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvPciMasterEnable - Enable/disale PCI interface master transactions. ++* ++* DESCRIPTION: ++* This function performs read modified write to PCI command status ++* (offset 0x4) to set/reset bit 2. After this bit is set, the PCI ++* master is allowed to gain ownership on the bus, otherwise it is ++* incapable to do so. ++* ++* INPUT: ++* pciIf - PCI interface number. ++* enable - Enable/disable parameter. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPciMasterEnable(MV_U32 pciIf, MV_BOOL enable) ++{ ++ MV_U32 pciCommandStatus; ++ MV_U32 RegOffs; ++ MV_U32 localBus; ++ MV_U32 localDev; ++ ++ /* Parameter checking */ ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciMasterEnable: ERR. Invalid PCI interface %d\n", pciIf); ++ return MV_ERROR; ++ } ++ ++ localBus = mvPciLocalBusNumGet(pciIf); ++ localDev = mvPciLocalDevNumGet(pciIf); ++ ++ RegOffs = PCI_STATUS_AND_COMMAND; ++ ++ pciCommandStatus = mvPciConfigRead(pciIf, localBus, localDev, 0, RegOffs); ++ ++ if (MV_TRUE == enable) ++ { ++ pciCommandStatus |= PSCR_MASTER_EN; ++ } ++ else ++ { ++ pciCommandStatus &= ~PSCR_MASTER_EN; ++ } ++ ++ mvPciConfigWrite(pciIf, localBus, localDev, 0, RegOffs, pciCommandStatus); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvPciSlaveEnable - Enable/disale PCI interface slave transactions. ++* ++* DESCRIPTION: ++* This function performs read modified write to PCI command status ++* (offset 0x4) to set/reset bit 0 and 1. After those bits are set, ++* the PCI slave is allowed to respond to PCI IO space access (bit 0) ++* and PCI memory space access (bit 1). ++* ++* INPUT: ++* pciIf - PCI interface number. ++* dev - PCI device number. ++* enable - Enable/disable parameter. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPciSlaveEnable(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, MV_BOOL enable) ++{ ++ MV_U32 pciCommandStatus; ++ MV_U32 RegOffs; ++ ++ /* Parameter checking */ ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciSlaveEnable: ERR. Invalid PCI interface %d\n", pciIf); ++ return MV_BAD_PARAM; ++ } ++ if (dev >= MAX_PCI_DEVICES) ++ { ++ mvOsPrintf("mvPciLocalDevNumSet: ERR. device number illigal %d\n", dev); ++ return MV_BAD_PARAM; ++ ++ } ++ ++ RegOffs = PCI_STATUS_AND_COMMAND; ++ ++ pciCommandStatus=mvPciConfigRead(pciIf, bus, dev, 0, RegOffs); ++ ++ if (MV_TRUE == enable) ++ { ++ pciCommandStatus |= (PSCR_IO_EN | PSCR_MEM_EN); ++ } ++ else ++ { ++ pciCommandStatus &= ~(PSCR_IO_EN | PSCR_MEM_EN); ++ } ++ ++ mvPciConfigWrite(pciIf, bus, dev, 0, RegOffs, pciCommandStatus); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvPciLocalBusNumSet - Set PCI interface local bus number. ++* ++* DESCRIPTION: ++* This function sets given PCI interface its local bus number. ++* Note: In case the PCI interface is PCI-X, the information is read-only. ++* ++* INPUT: ++* pciIf - PCI interface number. ++* busNum - Bus number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_NOT_ALLOWED in case PCI interface is PCI-X. ++* MV_BAD_PARAM on bad parameters , ++* otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPciLocalBusNumSet(MV_U32 pciIf, MV_U32 busNum) ++{ ++ MV_U32 pciP2PConfig; ++ MV_PCI_MODE pciMode; ++ MV_U32 localBus; ++ MV_U32 localDev; ++ ++ ++ /* Parameter checking */ ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciLocalBusNumSet: ERR. Invalid PCI interface %d\n",pciIf); ++ return MV_BAD_PARAM; ++ } ++ if (busNum >= MAX_PCI_BUSSES) ++ { ++ mvOsPrintf("mvPciLocalBusNumSet: ERR. bus number illigal %d\n", busNum); ++ return MV_ERROR; ++ ++ } ++ ++ localBus = mvPciLocalBusNumGet(pciIf); ++ localDev = mvPciLocalDevNumGet(pciIf); ++ ++ ++ /* PCI interface mode */ ++ mvPciModeGet(pciIf, &pciMode); ++ ++ /* if PCI type is PCI-X then it is not allowed to change the dev number */ ++ if (MV_PCIX == pciMode.pciType) ++ { ++ pciP2PConfig = mvPciConfigRead(pciIf, localBus, localDev, 0, PCIX_STATUS ); ++ ++ pciP2PConfig &= ~PXS_BN_MASK; ++ ++ pciP2PConfig |= (busNum << PXS_BN_OFFS) & PXS_BN_MASK; ++ ++ mvPciConfigWrite(pciIf, localBus, localDev, 0, PCIX_STATUS,pciP2PConfig ); ++ ++ } ++ else ++ { ++ pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); ++ ++ pciP2PConfig &= ~PPCR_BUS_NUM_MASK; ++ ++ pciP2PConfig |= (busNum << PPCR_BUS_NUM_OFFS) & PPCR_BUS_NUM_MASK; ++ ++ MV_REG_WRITE(PCI_P2P_CONFIG_REG(pciIf), pciP2PConfig); ++ ++ } ++ ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvPciLocalBusNumGet - Get PCI interface local bus number. ++* ++* DESCRIPTION: ++* This function gets the local bus number of a given PCI interface. ++* ++* INPUT: ++* pciIf - PCI interface number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Local bus number.0xffffffff on Error ++* ++*******************************************************************************/ ++MV_U32 mvPciLocalBusNumGet(MV_U32 pciIf) ++{ ++ MV_U32 pciP2PConfig; ++ ++ /* Parameter checking */ ++ if (PCI_DEFAULT_IF != pciIf) ++ { ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciLocalBusNumGet: ERR. Invalid PCI interface %d\n", ++ pciIf); ++ return 0xFFFFFFFF; ++ } ++ } ++ ++ pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); ++ pciP2PConfig &= PPCR_BUS_NUM_MASK; ++ return (pciP2PConfig >> PPCR_BUS_NUM_OFFS); ++} ++ ++ ++/******************************************************************************* ++* mvPciLocalDevNumSet - Set PCI interface local device number. ++* ++* DESCRIPTION: ++* This function sets given PCI interface its local device number. ++* Note: In case the PCI interface is PCI-X, the information is read-only. ++* ++* INPUT: ++* pciIf - PCI interface number. ++* devNum - Device number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_NOT_ALLOWED in case PCI interface is PCI-X. MV_BAD_PARAM on bad parameters , ++* otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPciLocalDevNumSet(MV_U32 pciIf, MV_U32 devNum) ++{ ++ MV_U32 pciP2PConfig; ++ MV_PCI_MODE pciMode; ++ MV_U32 localBus; ++ MV_U32 localDev; ++ ++ /* Parameter checking */ ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciLocalDevNumSet: ERR. Invalid PCI interface %d\n",pciIf); ++ return MV_BAD_PARAM; ++ } ++ if (devNum >= MAX_PCI_DEVICES) ++ { ++ mvOsPrintf("mvPciLocalDevNumSet: ERR. device number illigal %d\n", ++ devNum); ++ return MV_BAD_PARAM; ++ ++ } ++ ++ localBus = mvPciLocalBusNumGet(pciIf); ++ localDev = mvPciLocalDevNumGet(pciIf); ++ ++ /* PCI interface mode */ ++ mvPciModeGet(pciIf, &pciMode); ++ ++ /* if PCI type is PCIX then it is not allowed to change the dev number */ ++ if (MV_PCIX == pciMode.pciType) ++ { ++ pciP2PConfig = mvPciConfigRead(pciIf, localBus, localDev, 0, PCIX_STATUS ); ++ ++ pciP2PConfig &= ~PXS_DN_MASK; ++ ++ pciP2PConfig |= (devNum << PXS_DN_OFFS) & PXS_DN_MASK; ++ ++ mvPciConfigWrite(pciIf,localBus, localDev, 0, PCIX_STATUS,pciP2PConfig ); ++ } ++ else ++ { ++ pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); ++ ++ pciP2PConfig &= ~PPCR_DEV_NUM_MASK; ++ ++ pciP2PConfig |= (devNum << PPCR_DEV_NUM_OFFS) & PPCR_DEV_NUM_MASK; ++ ++ MV_REG_WRITE(PCI_P2P_CONFIG_REG(pciIf), pciP2PConfig); ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvPciLocalDevNumGet - Get PCI interface local device number. ++* ++* DESCRIPTION: ++* This function gets the local device number of a given PCI interface. ++* ++* INPUT: ++* pciIf - PCI interface number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Local device number. 0xffffffff on Error ++* ++*******************************************************************************/ ++MV_U32 mvPciLocalDevNumGet(MV_U32 pciIf) ++{ ++ MV_U32 pciP2PConfig; ++ ++ /* Parameter checking */ ++ ++ if (PCI_DEFAULT_IF != pciIf) ++ { ++ if (pciIf >= mvCtrlPciMaxIfGet()) ++ { ++ mvOsPrintf("mvPciLocalDevNumGet: ERR. Invalid PCI interface %d\n", ++ pciIf); ++ return 0xFFFFFFFF; ++ } ++ } ++ ++ pciP2PConfig = MV_REG_READ(PCI_P2P_CONFIG_REG(pciIf)); ++ ++ pciP2PConfig &= PPCR_DEV_NUM_MASK; ++ ++ return (pciP2PConfig >> PPCR_DEV_NUM_OFFS); ++} ++ ++ ++ ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPci.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,185 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#ifndef __INCPCIH ++#define __INCPCIH ++ ++#include "mvCommon.h" ++#include "mvOs.h" ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++#include "pci/mvPciRegs.h" ++ ++ ++/* NOTE not supported in this driver: ++ ++ Built In Self Test (BIST) ++ Vital Product Data (VPD) ++ Message Signaled Interrupt (MSI) ++ Power Management ++ Compact PCI Hot Swap ++ Header retarget ++ ++Registers not supported: ++1) PCI DLL Status and Control (PCI0 0x1D20, PCI1 0x1DA0) ++2) PCI/MPP Pads Calibration (CI0/MPP[31:16] 0x1D1C, PCI1/MPP[15:0] 0X1D9C) ++*/ ++ ++/* defines */ ++/* The number of supported PCI interfaces depend on Marvell controller */ ++/* device number. This device number ID is located on the PCI unit */ ++/* configuration header. This creates a loop where calling PCI */ ++/* configuration read/write routine results a call to get PCI configuration */ ++/* information etc. This macro defines a default PCI interface. This PCI */ ++/* interface is sure to exist. */ ++#define PCI_DEFAULT_IF 0 ++ ++ ++/* typedefs */ ++/* The Marvell controller supports both conventional PCI and PCI-X. */ ++/* This enumeration describes the PCI type. */ ++typedef enum _mvPciType ++{ ++ MV_PCI_CONV, /* Conventional PCI */ ++ MV_PCIX /* PCI-X */ ++}MV_PCI_TYPE; ++ ++typedef enum _mvPciMod ++{ ++ MV_PCI_MOD_HOST, ++ MV_PCI_MOD_DEVICE ++}MV_PCI_MOD; ++ ++ ++/* The Marvell controller supports both PCI width of 32 and 64 bit. */ ++/* This enumerator describes PCI width */ ++typedef enum _mvPciWidth ++{ ++ MV_PCI_32, /* PCI width 32bit */ ++ MV_PCI_64 /* PCI width 64bit */ ++}MV_PCI_WIDTH; ++ ++/* This structure describes the PCI unit configured type, speed and width. */ ++typedef struct _mvPciMode ++{ ++ MV_PCI_TYPE pciType; /* PCI type */ ++ MV_U32 pciSpeed; /* Assuming PCI base clock on board is 33MHz */ ++ MV_PCI_WIDTH pciWidth; /* PCI bus width */ ++}MV_PCI_MODE; ++ ++/* mvPciInit - Initialize PCI interfaces*/ ++MV_VOID mvPciHalInit(MV_U32 pciIf, MV_PCI_MOD pciIfmod); ++ ++/* mvPciCommandSet - Set PCI comman register value.*/ ++MV_STATUS mvPciCommandSet(MV_U32 pciIf, MV_U32 command); ++ ++/* mvPciModeGet - Get PCI interface mode.*/ ++MV_STATUS mvPciModeGet(MV_U32 pciIf, MV_PCI_MODE *pPciMode); ++ ++/* mvPciRetrySet - Set PCI retry counters*/ ++MV_STATUS mvPciRetrySet(MV_U32 pciIf, MV_U32 counter); ++ ++/* mvPciDiscardTimerSet - Set PCI discard timer*/ ++MV_STATUS mvPciDiscardTimerSet(MV_U32 pciIf, MV_U32 pClkCycles); ++ ++/* mvPciArbEnable - PCI arbiter enable/disable*/ ++MV_STATUS mvPciArbEnable(MV_U32 pciIf, MV_BOOL enable); ++ ++/* mvPciArbParkDis - Disable arbiter parking on agent */ ++MV_STATUS mvPciArbParkDis(MV_U32 pciIf, MV_U32 pciAgentMask); ++ ++/* mvPciArbBrokDetectSet - Set PCI arbiter broken detection */ ++MV_STATUS mvPciArbBrokDetectSet(MV_U32 pciIf, MV_U32 pClkCycles); ++ ++/* mvPciConfigRead - Read from configuration space */ ++MV_U32 mvPciConfigRead (MV_U32 pciIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func,MV_U32 regOff); ++ ++/* mvPciConfigWrite - Write to configuration space */ ++MV_STATUS mvPciConfigWrite(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func, MV_U32 regOff, MV_U32 data); ++ ++/* mvPciMasterEnable - Enable/disale PCI interface master transactions.*/ ++MV_STATUS mvPciMasterEnable(MV_U32 pciIf, MV_BOOL enable); ++ ++/* mvPciSlaveEnable - Enable/disale PCI interface slave transactions.*/ ++MV_STATUS mvPciSlaveEnable(MV_U32 pciIf, MV_U32 bus, MV_U32 dev,MV_BOOL enable); ++ ++/* mvPciLocalBusNumSet - Set PCI interface local bus number.*/ ++MV_STATUS mvPciLocalBusNumSet(MV_U32 pciIf, MV_U32 busNum); ++ ++/* mvPciLocalBusNumGet - Get PCI interface local bus number.*/ ++MV_U32 mvPciLocalBusNumGet(MV_U32 pciIf); ++ ++/* mvPciLocalDevNumSet - Set PCI interface local device number.*/ ++MV_STATUS mvPciLocalDevNumSet(MV_U32 pciIf, MV_U32 devNum); ++ ++/* mvPciLocalDevNumGet - Get PCI interface local device number.*/ ++MV_U32 mvPciLocalDevNumGet(MV_U32 pciIf); ++ ++ ++#endif /* #ifndef __INCPCIH */ ++ ++ ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,411 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCPCIREGSH ++#define __INCPCIREGSH ++ ++ ++#include "pci-if/mvPciIfRegs.h" ++/* defines */ ++#define MAX_PCI_DEVICES 32 ++#define MAX_PCI_FUNCS 8 ++#define MAX_PCI_BUSSES 128 ++ ++/* enumerators */ ++ ++/* This enumerator described the possible PCI slave targets. */ ++/* PCI slave targets are designated memory/IO address spaces that the */ ++/* PCI slave targets can access. They are also refered as "targets" */ ++/* this enumeratoe order is determined by the content of : ++ PCI_BASE_ADDR_ENABLE_REG */ ++ ++ ++/* registers offsetes defines */ ++ ++ ++ ++/*************************/ ++/* PCI control registers */ ++/*************************/ ++/* maen : should add new registers */ ++#define PCI_CMD_REG(pciIf) (0x30c00 + ((pciIf) * 0x80)) ++#define PCI_MODE_REG(pciIf) (0x30d00 + ((pciIf) * 0x80)) ++#define PCI_RETRY_REG(pciIf) (0x30c04 + ((pciIf) * 0x80)) ++#define PCI_DISCARD_TIMER_REG(pciIf) (0x30d04 + ((pciIf) * 0x80)) ++#define PCI_ARBITER_CTRL_REG(pciIf) (0x31d00 + ((pciIf) * 0x80)) ++#define PCI_P2P_CONFIG_REG(pciIf) (0x31d14 + ((pciIf) * 0x80)) ++#define PCI_ACCESS_CTRL_BASEL_REG(pciIf, targetWin) \ ++ (0x31e00 + ((pciIf) * 0x80) + ((targetWin) * 0x10)) ++#define PCI_ACCESS_CTRL_BASEH_REG(pciIf, targetWin) \ ++ (0x31e04 + ((pciIf) * 0x80) + ((targetWin) * 0x10)) ++#define PCI_ACCESS_CTRL_SIZE_REG(pciIf, targetWin) \ ++ (0x31e08 + ((pciIf) * 0x80) + ((targetWin) * 0x10)) ++ ++#define PCI_DLL_CTRL_REG(pciIf) (0x31d20 + ((pciIf) * 0x80)) ++ ++/* PCI Dll Control (PDC)*/ ++#define PDC_DLL_EN BIT0 ++ ++ ++/* PCI Command Register (PCR) */ ++#define PCR_MASTER_BYTE_SWAP_EN BIT0 ++#define PCR_MASTER_WR_COMBINE_EN BIT4 ++#define PCR_MASTER_RD_COMBINE_EN BIT5 ++#define PCR_MASTER_WR_TRIG_WHOLE BIT6 ++#define PCR_MASTER_RD_TRIG_WHOLE BIT7 ++#define PCR_MASTER_MEM_RD_LINE_EN BIT8 ++#define PCR_MASTER_MEM_RD_MULT_EN BIT9 ++#define PCR_MASTER_WORD_SWAP_EN BIT10 ++#define PCR_SLAVE_WORD_SWAP_EN BIT11 ++#define PCR_NS_ACCORDING_RCV_TRANS BIT14 ++#define PCR_MASTER_PCIX_REQ64N_EN BIT15 ++#define PCR_SLAVE_BYTE_SWAP_EN BIT16 ++#define PCR_MASTER_DAC_EN BIT17 ++#define PCR_MASTER_M64_ALLIGN BIT18 ++#define PCR_ERRORS_PROPAGATION_EN BIT19 ++#define PCR_SLAVE_SWAP_ENABLE BIT20 ++#define PCR_MASTER_SWAP_ENABLE BIT21 ++#define PCR_MASTER_INT_SWAP_EN BIT22 ++#define PCR_LOOP_BACK_ENABLE BIT23 ++#define PCR_SLAVE_INTREG_SWAP_OFFS 24 ++#define PCR_SLAVE_INTREG_SWAP_MASK 0x3 ++#define PCR_SLAVE_INTREG_BYTE_SWAP \ ++ (MV_BYTE_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) ++#define PCR_SLAVE_INTREG_NO_SWAP \ ++ (MV_NO_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) ++#define PCR_SLAVE_INTREG_BYTE_WORD \ ++ (MV_BYTE_WORD_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) ++#define PCR_SLAVE_INTREG_WORD_SWAP \ ++ (MV_WORD_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK) ++#define PCR_RESET_REASSERTION_EN BIT26 ++#define PCR_PCI_TO_CPU_REG_ORDER_EN BIT28 ++#define PCR_CPU_TO_PCI_ORDER_EN BIT29 ++#define PCR_PCI_TO_CPU_ORDER_EN BIT30 ++ ++/* PCI Mode Register (PMR) */ ++#define PMR_PCI_ID_OFFS 0 /* PCI Interface ID */ ++#define PMR_PCI_ID_MASK (0x1 << PMR_PCI_ID_OFFS) ++#define PMR_PCI_ID_PCI(pciNum) ((pciNum) << PCI_MODE_PCIID_OFFS) ++ ++#define PMR_PCI_64_OFFS 2 /* 64-bit PCI Interface */ ++#define PMR_PCI_64_MASK (0x1 << PMR_PCI_64_OFFS) ++#define PMR_PCI_64_64BIT (0x1 << PMR_PCI_64_OFFS) ++#define PMR_PCI_64_32BIT (0x0 << PMR_PCI_64_OFFS) ++ ++#define PMR_PCI_MODE_OFFS 4 /* PCI interface mode of operation */ ++#define PMR_PCI_MODE_MASK (0x3 << PMR_PCI_MODE_OFFS) ++#define PMR_PCI_MODE_CONV (0x0 << PMR_PCI_MODE_OFFS) ++#define PMR_PCI_MODE_PCIX_66MHZ (0x1 << PMR_PCI_MODE_OFFS) ++#define PMR_PCI_MODE_PCIX_100MHZ (0x2 << PMR_PCI_MODE_OFFS) ++#define PMR_PCI_MODE_PCIX_133MHZ (0x3 << PMR_PCI_MODE_OFFS) ++ ++#define PMR_EXP_ROM_SUPPORT BIT8 /* Expansion ROM Active */ ++ ++#define PMR_PCI_RESET_OFFS 31 /* PCI Interface Reset Indication */ ++#define PMR_PCI_RESET_MASK (0x1 << PMR_PCI_RESET_OFFS) ++#define PMR_PCI_RESET_PCIXRST (0x0 << PMR_PCI_RESET_OFFS) ++ ++ ++/* PCI Retry Register (PRR) */ ++#define PRR_RETRY_CNTR_OFFS 16 /* Retry Counter */ ++#define PRR_RETRY_CNTR_MAX 0xff ++#define PRR_RETRY_CNTR_MASK (PRR_RETRY_CNTR_MAX << PRR_RETRY_CNTR_OFFS) ++ ++ ++/* PCI Discard Timer Register (PDTR) */ ++#define PDTR_TIMER_OFFS 0 /* Timer */ ++#define PDTR_TIMER_MAX 0xffff ++#define PDTR_TIMER_MIN 0x7F ++#define PDTR_TIMER_MASK (PDTR_TIMER_MAX << PDTR_TIMER_OFFS) ++ ++ ++/* PCI Arbiter Control Register (PACR) */ ++#define PACR_BROKEN_DETECT_EN BIT1 /* Broken Detection Enable */ ++ ++#define PACR_BROKEN_VAL_OFFS 3 /* Broken Value */ ++#define PACR_BROKEN_VAL_MASK (0xf << PACR_BROKEN_VAL_OFFS) ++#define PACR_BROKEN_VAL_CONV_MIN 0x2 ++#define PACR_BROKEN_VAL_PCIX_MIN 0x6 ++ ++#define PACR_PARK_DIS_OFFS 14 /* Parking Disable */ ++#define PACR_PARK_DIS_MAX_AGENT 0x3f ++#define PACR_PARK_DIS_MASK (PACR_PARK_DIS_MAX_AGENT<= MV_PCI_START_IF)&&(pciIf < MV_PCI_MAX_IF + MV_PCI_START_IF)) ++ { ++ return PCI_IF_TYPE_CONVEN_PCIX; ++ } ++ else if ((pciIf >= MV_PEX_START_IF) && ++ (pciIf < MV_PEX_MAX_IF + MV_PEX_START_IF)) ++ { ++ return PCI_IF_TYPE_PEX; ++ ++ } ++ else ++ { ++ mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf); ++ } ++ ++ return 0xffffffff; ++ ++} ++ ++/******************************************************************************* ++* mvPciIfTypeGet - ++* ++* DESCRIPTION: ++* ++* INPUT: ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* ++*******************************************************************************/ ++ ++MV_U32 mvPciRealIfNumGet(MV_U32 pciIf) ++{ ++ ++ PCI_IF_TYPE pciIfType = mvPciIfTypeGet(pciIf); ++ ++ if (PCI_IF_TYPE_CONVEN_PCIX == pciIfType) ++ { ++ return (pciIf - MV_PCI_START_IF); ++ } ++ else if (PCI_IF_TYPE_PEX == pciIfType) ++ { ++ return (pciIf - MV_PEX_START_IF); ++ ++ } ++ else ++ { ++ mvOsPrintf("%s: ERROR!!! Invalid pciIf %d\n", __FUNCTION__, pciIf); ++ } ++ ++ return 0xffffffff; ++ ++} ++ ++ ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIf.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,134 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCPCIIFH ++#define __INCPCIIFH ++ ++#include "mvSysHwConfig.h" ++#include "pci-if/mvPciIfRegs.h" ++#if defined(MV_INCLUDE_PEX) ++#include "pex/mvPex.h" ++#endif ++#if defined(MV_INCLUDE_PCI) ++#include "pci/mvPci.h" ++#endif ++#include "ctrlEnv/mvCtrlEnvLib.h" ++#include "ctrlEnv/mvCtrlEnvAddrDec.h" ++ ++typedef enum _mvPCIIfType ++{ ++ PCI_IF_TYPE_CONVEN_PCIX, ++ PCI_IF_TYPE_PEX ++ ++}PCI_IF_TYPE; ++ ++typedef enum _mvPCIIfMode ++{ ++ PCI_IF_MODE_HOST, ++ PCI_IF_MODE_DEVICE ++}PCI_IF_MODE; ++ ++ ++/* Global Functions prototypes */ ++ ++/* mvPciIfInit - Initialize PCI interfaces*/ ++MV_STATUS mvPciIfInit(MV_U32 pciIf, PCI_IF_MODE pciIfmode); ++ ++/* mvPciIfConfigRead - Read from configuration space */ ++MV_U32 mvPciIfConfigRead (MV_U32 pciIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func,MV_U32 regOff); ++ ++/* mvPciIfConfigWrite - Write to configuration space */ ++MV_STATUS mvPciIfConfigWrite(MV_U32 pciIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func, MV_U32 regOff, MV_U32 data); ++ ++/* mvPciIfMasterEnable - Enable/disale PCI interface master transactions.*/ ++MV_STATUS mvPciIfMasterEnable(MV_U32 pciIf, MV_BOOL enable); ++ ++/* mvPciIfSlaveEnable - Enable/disale PCI interface slave transactions.*/ ++MV_STATUS mvPciIfSlaveEnable(MV_U32 pciIf,MV_U32 bus, MV_U32 dev, ++ MV_BOOL enable); ++ ++/* mvPciIfLocalBusNumSet - Set PCI interface local bus number.*/ ++MV_STATUS mvPciIfLocalBusNumSet(MV_U32 pciIf, MV_U32 busNum); ++ ++/* mvPciIfLocalBusNumGet - Get PCI interface local bus number.*/ ++MV_U32 mvPciIfLocalBusNumGet(MV_U32 pciIf); ++ ++/* mvPciIfLocalDevNumSet - Set PCI interface local device number.*/ ++MV_STATUS mvPciIfLocalDevNumSet(MV_U32 pciIf, MV_U32 devNum); ++ ++/* mvPciIfLocalDevNumGet - Get PCI interface local device number.*/ ++MV_U32 mvPciIfLocalDevNumGet(MV_U32 pciIf); ++ ++/* mvPciIfTypeGet - Get PCI If type*/ ++PCI_IF_TYPE mvPciIfTypeGet(MV_U32 pciIf); ++ ++MV_U32 mvPciRealIfNumGet(MV_U32 pciIf); ++ ++/* mvPciIfAddrDecShow - Display address decode windows attributes */ ++MV_VOID mvPciIfAddrDecShow(MV_VOID); ++ ++#endif /* #ifndef __INCPCIIFH */ ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/mvPciIfRegs.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,245 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCPCIIFREGSH ++#define __INCPCIIFREGSH ++ ++ ++/* defines */ ++#define MAX_PCI_DEVICES 32 ++#define MAX_PCI_FUNCS 8 ++#define MAX_PCI_BUSSES 128 ++ ++/***************************************/ ++/* PCI Configuration registers */ ++/***************************************/ ++ ++/*********************************************/ ++/* PCI Configuration, Function 0, Registers */ ++/*********************************************/ ++ ++ ++/* Standard registers */ ++#define PCI_DEVICE_AND_VENDOR_ID 0x000 ++#define PCI_STATUS_AND_COMMAND 0x004 ++#define PCI_CLASS_CODE_AND_REVISION_ID 0x008 ++#define PCI_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE 0x00C ++#define PCI_MEMORY_BAR_BASE_ADDR(barNum) (0x010 + ((barNum) << 2)) ++#define PCI_SUBSYS_ID_AND_SUBSYS_VENDOR_ID 0x02C ++#define PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030 ++#define PCI_CAPABILTY_LIST_POINTER 0x034 ++#define PCI_INTERRUPT_PIN_AND_LINE 0x03C ++ ++ ++/* PCI Device and Vendor ID Register (PDVIR) */ ++#define PDVIR_VEN_ID_OFFS 0 /* Vendor ID */ ++#define PDVIR_VEN_ID_MASK (0xffff << PDVIR_VEN_ID_OFFS) ++ ++#define PDVIR_DEV_ID_OFFS 16 /* Device ID */ ++#define PDVIR_DEV_ID_MASK (0xffff << PDVIR_DEV_ID_OFFS) ++ ++/* PCI Status and Command Register (PSCR) */ ++#define PSCR_IO_EN BIT0 /* IO Enable */ ++#define PSCR_MEM_EN BIT1 /* Memory Enable */ ++#define PSCR_MASTER_EN BIT2 /* Master Enable */ ++#define PSCR_SPECIAL_EN BIT3 /* Special Cycle Enable */ ++#define PSCR_MEM_WRI_INV BIT4 /* Memory Write and Invalidate Enable */ ++#define PSCR_VGA BIT5 /* VGA Palette Snoops */ ++#define PSCR_PERR_EN BIT6 /* Parity Errors Respond Enable */ ++#define PSCR_ADDR_STEP BIT7 /* Address Stepping Enable (Wait Cycle En)*/ ++#define PSCR_SERR_EN BIT8 /* Ability to assert SERR# line */ ++#define PSCR_FAST_BTB_EN BIT9 /* generate fast back-to-back transactions*/ ++#define PSCR_CAP_LIST BIT20 /* Capability List Support */ ++#define PSCR_66MHZ_EN BIT21 /* 66 MHz Capable */ ++#define PSCR_UDF_EN BIT22 /* User definable features */ ++#define PSCR_TAR_FAST_BB BIT23 /* fast back-to-back transactions capable */ ++#define PSCR_DATA_PERR BIT24 /* Data Parity reported */ ++ ++#define PSCR_DEVSEL_TIM_OFFS 25 /* DEVSEL timing */ ++#define PSCR_DEVSEL_TIM_MASK (0x3 << PSCR_DEVSEL_TIM_OFFS) ++#define PSCR_DEVSEL_TIM_FAST (0x0 << PSCR_DEVSEL_TIM_OFFS) ++#define PSCR_DEVSEL_TIM_MED (0x1 << PSCR_DEVSEL_TIM_OFFS) ++#define PSCR_DEVSEL_TIM_SLOW (0x2 << PSCR_DEVSEL_TIM_OFFS) ++ ++#define PSCR_SLAVE_TABORT BIT27 /* Signalled Target Abort */ ++#define PSCR_MASTER_TABORT BIT28 /* Recieved Target Abort */ ++#define PSCR_MABORT BIT29 /* Recieved Master Abort */ ++#define PSCR_SYSERR BIT30 /* Signalled system error */ ++#define PSCR_DET_PARERR BIT31 /* Detect Parity Error */ ++ ++/* PCI configuration register offset=0x08 fields ++ (PCI_CLASS_CODE_AND_REVISION_ID)(PCCRI) */ ++ ++#define PCCRIR_REVID_OFFS 0 /* Revision ID */ ++#define PCCRIR_REVID_MASK (0xff << PCCRIR_REVID_OFFS) ++ ++#define PCCRIR_FULL_CLASS_OFFS 8 /* Full Class Code */ ++#define PCCRIR_FULL_CLASS_MASK (0xffffff << PCCRIR_FULL_CLASS_OFFS) ++ ++#define PCCRIR_PROGIF_OFFS 8 /* Prog .I/F*/ ++#define PCCRIR_PROGIF_MASK (0xff << PCCRIR_PROGIF_OFFS) ++ ++#define PCCRIR_SUB_CLASS_OFFS 16 /* Sub Class*/ ++#define PCCRIR_SUB_CLASS_MASK (0xff << PCCRIR_SUB_CLASS_OFFS) ++ ++#define PCCRIR_BASE_CLASS_OFFS 24 /* Base Class*/ ++#define PCCRIR_BASE_CLASS_MASK (0xff << PCCRIR_BASE_CLASS_OFFS) ++ ++/* PCI configuration register offset=0x0C fields ++ (PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE)(PBHTLTCL) */ ++ ++#define PBHTLTCLR_CACHELINE_OFFS 0 /* Specifies the cache line size */ ++#define PBHTLTCLR_CACHELINE_MASK (0xff << PBHTLTCLR_CACHELINE_OFFS) ++ ++#define PBHTLTCLR_LATTIMER_OFFS 8 /* latency timer */ ++#define PBHTLTCLR_LATTIMER_MASK (0xff << PBHTLTCLR_LATTIMER_OFFS) ++ ++#define PBHTLTCLR_HEADTYPE_FULL_OFFS 16 /* Full Header Type */ ++#define PBHTLTCLR_HEADTYPE_FULL_MASK (0xff << PBHTLTCLR_HEADTYPE_FULL_OFFS) ++ ++#define PBHTLTCLR_MULTI_FUNC BIT23 /* Multi/Single function */ ++ ++#define PBHTLTCLR_HEADER_OFFS 16 /* Header type */ ++#define PBHTLTCLR_HEADER_MASK (0x7f << PBHTLTCLR_HEADER_OFFS) ++#define PBHTLTCLR_HEADER_STANDARD (0x0 << PBHTLTCLR_HEADER_OFFS) ++#define PBHTLTCLR_HEADER_PCI2PCI_BRIDGE (0x1 << PBHTLTCLR_HEADER_OFFS) ++ ++ ++#define PBHTLTCLR_BISTCOMP_OFFS 24 /* BIST Completion Code */ ++#define PBHTLTCLR_BISTCOMP_MASK (0xf << PBHTLTCLR_BISTCOMP_OFFS) ++ ++#define PBHTLTCLR_BISTACT BIT30 /* BIST Activate bit */ ++#define PBHTLTCLR_BISTCAP BIT31 /* BIST Capable Bit */ ++ ++ ++/* PCI Bar Base Low Register (PBBLR) */ ++#define PBBLR_IOSPACE BIT0 /* Memory Space Indicator */ ++ ++#define PBBLR_TYPE_OFFS 1 /* BAR Type/Init Val. */ ++#define PBBLR_TYPE_MASK (0x3 << PBBLR_TYPE_OFFS) ++#define PBBLR_TYPE_32BIT_ADDR (0x0 << PBBLR_TYPE_OFFS) ++#define PBBLR_TYPE_64BIT_ADDR (0x2 << PBBLR_TYPE_OFFS) ++ ++#define PBBLR_PREFETCH_EN BIT3 /* Prefetch Enable */ ++ ++ ++#define PBBLR_MEM_BASE_OFFS 4 /* Memory Bar Base address. Corresponds to ++ address bits [31:4] */ ++#define PBBLR_MEM_BASE_MASK (0xfffffff << PBBLR_MEM_BASE_OFFS) ++ ++#define PBBLR_IO_BASE_OFFS 2 /* IO Bar Base address. Corresponds to ++ address bits [31:2] */ ++#define PBBLR_IO_BASE_MASK (0x3fffffff << PBBLR_IO_BASE_OFFS) ++ ++ ++#define PBBLR_BASE_OFFS 12 /* Base address. Address bits [31:12] */ ++#define PBBLR_BASE_MASK (0xfffff << PBBLR_BASE_OFFS) ++#define PBBLR_BASE_ALIGNMET (1 << PBBLR_BASE_OFFS) ++ ++ ++/* PCI Bar Base High Fegister (PBBHR) */ ++#define PBBHR_BASE_OFFS 0 /* Base address. Address bits [31:12] */ ++#define PBBHR_BASE_MASK (0xffffffff << PBBHR_BASE_OFFS) ++ ++ ++/* PCI configuration register offset=0x2C fields ++ (PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID)(PSISVI) */ ++ ++#define PSISVIR_VENID_OFFS 0 /* Subsystem Manufacturer Vendor ID Number */ ++#define PSISVIR_VENID_MASK (0xffff << PSISVIR_VENID_OFFS) ++ ++#define PSISVIR_DEVID_OFFS 16 /* Subsystem Device ID Number */ ++#define PSISVIR_DEVID_MASK (0xffff << PSISVIR_DEVID_OFFS) ++ ++/* PCI configuration register offset=0x30 fields ++ (PCI_EXPANSION_ROM_BASE_ADDR_REG)(PERBA) */ ++ ++#define PERBAR_EXPROMEN BIT0 /* Expansion ROM Enable */ ++ ++#define PERBAR_BASE_OFFS 12 /* Expansion ROM Base Address */ ++#define PERBAR_BASE_MASK (0xfffff << PERBAR_BASE_OFFS) ++ ++/* PCI configuration register offset=0x34 fields ++ (PCI_CAPABILTY_LIST_POINTER)(PCLP) */ ++ ++#define PCLPR_CAPPTR_OFFS 0 /* Capability List Pointer */ ++#define PCLPR_CAPPTR_MASK (0xff << PCLPR_CAPPTR_OFFS) ++ ++/* PCI configuration register offset=0x3C fields ++ (PCI_INTERRUPT_PIN_AND_LINE)(PIPL) */ ++ ++#define PIPLR_INTLINE_OFFS 0 /* Interrupt line (IRQ) */ ++#define PIPLR_INTLINE_MASK (0xff << PIPLR_INTLINE_OFFS) ++ ++#define PIPLR_INTPIN_OFFS 8 /* interrupt pin (A,B,C,D) */ ++#define PIPLR_INTPIN_MASK (0xff << PIPLR_INTPIN_OFFS) ++ ++#define PIPLR_MINGRANT_OFFS 16 /* Minimum Grant on 250 nano seconds units */ ++#define PIPLR_MINGRANT_MASK (0xff << PIPLR_MINGRANT_OFFS) ++ ++#define PIPLR_MAXLATEN_OFFS 24 /* Maximum latency on 250 nano seconds units */ ++#define PIPLR_MAXLATEN_MASK (0xff << PIPLR_MAXLATEN_OFFS) ++ ++#endif /* #ifndef __INCPCIIFREGSH */ ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.c linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.c +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,1006 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++/* includes */ ++#include "mvPciUtils.h" ++ ++#include "ctrlEnv/mvCtrlEnvLib.h" ++ ++/* #define MV_DEBUG */ ++/* defines */ ++#ifdef MV_DEBUG ++ #define DB(x) x ++ #define mvOsPrintf printf ++#else ++ #define DB(x) ++#endif ++ ++/* ++This module only support scanning of Header type 00h of pci devices ++There is no suppotr for Header type 01h of pci devices ( PCI bridges ) ++*/ ++ ++ ++static MV_STATUS pciDetectDevice(MV_U32 pciIf, ++ MV_U32 bus, ++ MV_U32 dev, ++ MV_U32 func, ++ MV_PCI_DEVICE *pPciAgent); ++ ++static MV_U32 pciDetectDeviceBars(MV_U32 pciIf, ++ MV_U32 bus, ++ MV_U32 dev, ++ MV_U32 func, ++ MV_PCI_DEVICE *pPciAgent); ++ ++ ++ ++ ++ ++ ++/******************************************************************************* ++* mvPciScan - Scan a PCI interface bus ++* ++* DESCRIPTION: ++* Performs a full scan on a PCI interface and returns all possible details ++* on the agents found on the bus. ++* ++* INPUT: ++* pciIf - PCI Interface ++* pPciAgents - Pointer to an Array of the pci agents to be detected ++* pPciAgentsNum - pPciAgents array maximum number of elements ++* ++* OUTPUT: ++* pPciAgents - Array of the pci agents detected on the bus ++* pPciAgentsNum - Number of pci agents detected on the bus ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++ ++MV_STATUS mvPciScan(MV_U32 pciIf, ++ MV_PCI_DEVICE *pPciAgents, ++ MV_U32 *pPciAgentsNum) ++{ ++ ++ MV_U32 devIndex,funcIndex=0,busIndex=0,detectedDevNum=0; ++ MV_U32 localBus=mvPciIfLocalBusNumGet(pciIf); ++ MV_PCI_DEVICE *pPciDevice; ++ MV_PCI_DEVICE *pMainDevice; ++ ++ DB(mvOsPrintf("mvPciScan: PCI interface num %d\n", pciIf)); ++ /* Parameter checking */ ++ if (pciIf >= mvCtrlPexMaxIfGet()) ++ { ++ DB(mvOsPrintf("mvPciScan: ERR. Invalid PCI interface num %d\n", pciIf)); ++ return MV_BAD_PARAM; ++ } ++ if (NULL == pPciAgents) ++ { ++ DB(mvOsPrintf("mvPciScan: ERR. pPciAgents=NULL \n")); ++ return MV_BAD_PARAM; ++ } ++ if (NULL == pPciAgentsNum) ++ { ++ DB(mvOsPrintf("mvPciScan: ERR. pPciAgentsNum=NULL \n")); ++ return MV_BAD_PARAM; ++ } ++ ++ ++ DB(mvOsPrintf("mvPciScan: PCI interface num %d mvPciMasterEnable\n", pciIf)); ++ /* Master enable the MV PCI master */ ++ if (MV_OK != mvPciIfMasterEnable(pciIf,MV_TRUE)) ++ { ++ DB(mvOsPrintf("mvPciScan: ERR. mvPciMasterEnable failed \n")); ++ return MV_ERROR; ++ ++ } ++ ++ DB(mvOsPrintf("mvPciScan: PCI interface num scan%d\n", pciIf)); ++ ++ /* go through all busses */ ++ for (busIndex=localBus ; busIndex < MAX_PCI_BUSSES ; busIndex++) ++ { ++ /* go through all possible devices on the local bus */ ++ for (devIndex=0 ; devIndex < MAX_PCI_DEVICES ; devIndex++) ++ { ++ /* always start with function equal to zero */ ++ funcIndex=0; ++ ++ pPciDevice=&pPciAgents[detectedDevNum]; ++ DB(mvOsPrintf("mvPciScan: PCI interface num scan%d:%d\n", busIndex, devIndex)); ++ ++ if (MV_ERROR == pciDetectDevice(pciIf, ++ busIndex, ++ devIndex, ++ funcIndex, ++ pPciDevice)) ++ { ++ /* no device detected , try the next address */ ++ continue; ++ } ++ ++ /* We are here ! means we have detected a device*/ ++ /* always we start with only one function per device */ ++ pMainDevice = pPciDevice; ++ pPciDevice->funtionsNum = 1; ++ ++ ++ /* move on */ ++ detectedDevNum++; ++ ++ ++ /* check if we have no more room for a new device */ ++ if (detectedDevNum == *pPciAgentsNum) ++ { ++ DB(mvOsPrintf("mvPciScan: ERR. array passed too small \n")); ++ return MV_ERROR; ++ } ++ ++ /* check the detected device if it is a multi functional device then ++ scan all device functions*/ ++ if (pPciDevice->isMultiFunction == MV_TRUE) ++ { ++ /* start with function number 1 because we have already detected ++ function 0 */ ++ for (funcIndex=1; funcIndexfuntionsNum++; ++ detectedDevNum++; ++ ++ /* check if we have no more room for a new device */ ++ if (detectedDevNum == *pPciAgentsNum) ++ { ++ DB(mvOsPrintf("mvPciScan: ERR. Array too small\n")); ++ return MV_ERROR; ++ } ++ ++ ++ } ++ } ++ ++ } ++ ++ } ++ ++ /* return the number of devices actually detected on the bus ! */ ++ *pPciAgentsNum = detectedDevNum; ++ ++ return MV_OK; ++ ++} ++ ++ ++/******************************************************************************* ++* pciDetectDevice - Detect a pci device parameters ++* ++* DESCRIPTION: ++* This function detect if a pci agent exist on certain address ! ++* and if exists then it fills all possible information on the ++* agent ++* ++* INPUT: ++* pciIf - PCI Interface ++* bus - Bus number ++* dev - Device number ++* func - Function number ++* ++* ++* ++* OUTPUT: ++* pPciAgent - pointer to the pci agent filled with its information ++* ++* RETURN: ++* MV_ERROR if no device , MV_OK otherwise ++* ++*******************************************************************************/ ++ ++static MV_STATUS pciDetectDevice(MV_U32 pciIf, ++ MV_U32 bus, ++ MV_U32 dev, ++ MV_U32 func, ++ MV_PCI_DEVICE *pPciAgent) ++{ ++ MV_U32 pciData; ++ ++ /* no Parameters checking ! because it is static function and it is assumed ++ that all parameters were checked in the calling function */ ++ ++ ++ /* Try read the PCI Vendor ID and Device ID */ ++ ++ /* We will scan only ourselves and the PCI slots that exist on the ++ board, because we may have a case that we have one slot that has ++ a Cardbus connector, and because CardBus answers all IDsels we want ++ to scan only this slot and ourseleves. ++ ++ */ ++ #if defined(MV_INCLUDE_PCI) ++ if ((PCI_IF_TYPE_CONVEN_PCIX == mvPciIfTypeGet(pciIf)) && ++ (DB_88F5181_DDR1_PRPMC != mvBoardIdGet()) && ++ (DB_88F5181_DDR1_PEXPCI != mvBoardIdGet()) && ++ (DB_88F5181_DDR1_MNG != mvBoardIdGet())) ++ { ++ ++ if (mvBoardIsOurPciSlot(bus, dev) == MV_FALSE) ++ { ++ return MV_ERROR; ++ } ++ } ++ #endif /* defined(MV_INCLUDE_PCI) */ ++ ++ pciData = mvPciIfConfigRead(pciIf, bus,dev,func, PCI_DEVICE_AND_VENDOR_ID); ++ ++ if (PCI_ERROR_CODE == pciData) ++ { ++ /* no device exist */ ++ return MV_ERROR; ++ } ++ ++ /* we are here ! means a device is detected */ ++ ++ /* fill basic information */ ++ pPciAgent->busNumber=bus; ++ pPciAgent->deviceNum=dev; ++ pPciAgent->function=func; ++ ++ /* Fill the PCI Vendor ID and Device ID */ ++ ++ pPciAgent->venID = (pciData & PDVIR_VEN_ID_MASK) >> PDVIR_VEN_ID_OFFS; ++ pPciAgent->deviceID = (pciData & PDVIR_DEV_ID_MASK) >> PDVIR_DEV_ID_OFFS; ++ ++ /* Read Status and command */ ++ pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ PCI_STATUS_AND_COMMAND); ++ ++ ++ /* Fill related Status and Command information*/ ++ ++ if (pciData & PSCR_TAR_FAST_BB) ++ { ++ pPciAgent->isFastB2BCapable = MV_TRUE; ++ } ++ else ++ { ++ pPciAgent->isFastB2BCapable = MV_FALSE; ++ } ++ ++ if (pciData & PSCR_CAP_LIST) ++ { ++ pPciAgent->isCapListSupport=MV_TRUE; ++ } ++ else ++ { ++ pPciAgent->isCapListSupport=MV_FALSE; ++ } ++ ++ if (pciData & PSCR_66MHZ_EN) ++ { ++ pPciAgent->is66MHZCapable=MV_TRUE; ++ } ++ else ++ { ++ pPciAgent->is66MHZCapable=MV_FALSE; ++ } ++ ++ /* Read Class Code and Revision */ ++ pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ PCI_CLASS_CODE_AND_REVISION_ID); ++ ++ ++ pPciAgent->baseClassCode = ++ (pciData & PCCRIR_BASE_CLASS_MASK) >> PCCRIR_BASE_CLASS_OFFS; ++ ++ pPciAgent->subClassCode = ++ (pciData & PCCRIR_SUB_CLASS_MASK) >> PCCRIR_SUB_CLASS_OFFS; ++ ++ pPciAgent->progIf = ++ (pciData & PCCRIR_PROGIF_MASK) >> PCCRIR_PROGIF_OFFS; ++ ++ pPciAgent->revisionID = ++ (pciData & PCCRIR_REVID_MASK) >> PCCRIR_REVID_OFFS; ++ ++ /* Read PCI_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE */ ++ pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ PCI_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE); ++ ++ ++ ++ pPciAgent->pciCacheLine= ++ (pciData & PBHTLTCLR_CACHELINE_MASK ) >> PBHTLTCLR_CACHELINE_OFFS; ++ pPciAgent->pciLatencyTimer= ++ (pciData & PBHTLTCLR_LATTIMER_MASK) >> PBHTLTCLR_LATTIMER_OFFS; ++ ++ switch (pciData & PBHTLTCLR_HEADER_MASK) ++ { ++ case PBHTLTCLR_HEADER_STANDARD: ++ ++ pPciAgent->pciHeader=MV_PCI_STANDARD; ++ break; ++ case PBHTLTCLR_HEADER_PCI2PCI_BRIDGE: ++ ++ pPciAgent->pciHeader=MV_PCI_PCI2PCI_BRIDGE; ++ break; ++ ++ } ++ ++ if (pciData & PBHTLTCLR_MULTI_FUNC) ++ { ++ pPciAgent->isMultiFunction=MV_TRUE; ++ } ++ else ++ { ++ pPciAgent->isMultiFunction=MV_FALSE; ++ } ++ ++ if (pciData & PBHTLTCLR_BISTCAP) ++ { ++ pPciAgent->isBISTCapable=MV_TRUE; ++ } ++ else ++ { ++ pPciAgent->isBISTCapable=MV_FALSE; ++ } ++ ++ ++ /* read this device pci bars */ ++ ++ pciDetectDeviceBars(pciIf, ++ bus,dev,func, ++ pPciAgent); ++ ++ ++ /* check if we are bridge*/ ++ if ((pPciAgent->baseClassCode == PCI_BRIDGE_CLASS)&& ++ (pPciAgent->subClassCode == P2P_BRIDGE_SUB_CLASS_CODE)) ++ { ++ ++ /* Read P2P_BUSSES_NUM */ ++ pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ P2P_BUSSES_NUM); ++ ++ pPciAgent->p2pPrimBusNum = ++ (pciData & PBM_PRIME_BUS_NUM_MASK) >> PBM_PRIME_BUS_NUM_OFFS; ++ ++ pPciAgent->p2pSecBusNum = ++ (pciData & PBM_SEC_BUS_NUM_MASK) >> PBM_SEC_BUS_NUM_OFFS; ++ ++ pPciAgent->p2pSubBusNum = ++ (pciData & PBM_SUB_BUS_NUM_MASK) >> PBM_SUB_BUS_NUM_OFFS; ++ ++ pPciAgent->p2pSecLatencyTimer = ++ (pciData & PBM_SEC_LAT_TMR_MASK) >> PBM_SEC_LAT_TMR_OFFS; ++ ++ /* Read P2P_IO_BASE_LIMIT_SEC_STATUS */ ++ pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ P2P_IO_BASE_LIMIT_SEC_STATUS); ++ ++ pPciAgent->p2pSecStatus = ++ (pciData & PIBLSS_SEC_STATUS_MASK) >> PIBLSS_SEC_STATUS_OFFS; ++ ++ ++ pPciAgent->p2pIObase = ++ (pciData & PIBLSS_IO_BASE_MASK) << PIBLSS_IO_LIMIT_OFFS; ++ ++ /* clear low address (should be zero)*/ ++ pPciAgent->p2pIObase &= PIBLSS_HIGH_ADDR_MASK; ++ ++ pPciAgent->p2pIOLimit = ++ (pciData & PIBLSS_IO_LIMIT_MASK); ++ ++ /* fill low address with 0xfff */ ++ pPciAgent->p2pIOLimit |= PIBLSS_LOW_ADDR_MASK; ++ ++ ++ switch ((pciData & PIBLSS_ADD_CAP_MASK) >> PIBLSS_ADD_CAP_OFFS) ++ { ++ case PIBLSS_ADD_CAP_16BIT: ++ ++ pPciAgent->bIO32 = MV_FALSE; ++ ++ break; ++ case PIBLSS_ADD_CAP_32BIT: ++ ++ pPciAgent->bIO32 = MV_TRUE; ++ ++ /* Read P2P_IO_BASE_LIMIT_UPPER_16 */ ++ pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ P2P_IO_BASE_LIMIT_UPPER_16); ++ ++ pPciAgent->p2pIObase |= ++ (pciData & PRBU_IO_UPP_BASE_MASK) << PRBU_IO_UPP_LIMIT_OFFS; ++ ++ ++ pPciAgent->p2pIOLimit |= ++ (pciData & PRBU_IO_UPP_LIMIT_MASK); ++ ++ break; ++ ++ } ++ ++ ++ /* Read P2P_MEM_BASE_LIMIT */ ++ pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ P2P_MEM_BASE_LIMIT); ++ ++ pPciAgent->p2pMemBase = ++ (pciData & PMBL_MEM_BASE_MASK) << PMBL_MEM_LIMIT_OFFS; ++ ++ /* clear low address */ ++ pPciAgent->p2pMemBase &= PMBL_HIGH_ADDR_MASK; ++ ++ pPciAgent->p2pMemLimit = ++ (pciData & PMBL_MEM_LIMIT_MASK); ++ ++ /* add 0xfffff */ ++ pPciAgent->p2pMemLimit |= PMBL_LOW_ADDR_MASK; ++ ++ ++ /* Read P2P_PREF_MEM_BASE_LIMIT */ ++ pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ P2P_PREF_MEM_BASE_LIMIT); ++ ++ ++ pPciAgent->p2pPrefMemBase = ++ (pciData & PRMBL_PREF_MEM_BASE_MASK) << PRMBL_PREF_MEM_LIMIT_OFFS; ++ ++ /* get high address only */ ++ pPciAgent->p2pPrefMemBase &= PRMBL_HIGH_ADDR_MASK; ++ ++ ++ ++ pPciAgent->p2pPrefMemLimit = ++ (pciData & PRMBL_PREF_MEM_LIMIT_MASK); ++ ++ /* add 0xfffff */ ++ pPciAgent->p2pPrefMemLimit |= PRMBL_LOW_ADDR_MASK; ++ ++ switch (pciData & PRMBL_ADD_CAP_MASK) ++ { ++ case PRMBL_ADD_CAP_32BIT: ++ ++ pPciAgent->bPrefMem64 = MV_FALSE; ++ ++ /* Read P2P_PREF_BASE_UPPER_32 */ ++ pPciAgent->p2pPrefBaseUpper32Bits = 0; ++ ++ /* Read P2P_PREF_LIMIT_UPPER_32 */ ++ pPciAgent->p2pPrefLimitUpper32Bits = 0; ++ ++ break; ++ case PRMBL_ADD_CAP_64BIT: ++ ++ pPciAgent->bPrefMem64 = MV_TRUE; ++ ++ /* Read P2P_PREF_BASE_UPPER_32 */ ++ pPciAgent->p2pPrefBaseUpper32Bits = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ P2P_PREF_BASE_UPPER_32); ++ ++ /* Read P2P_PREF_LIMIT_UPPER_32 */ ++ pPciAgent->p2pPrefLimitUpper32Bits = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ P2P_PREF_LIMIT_UPPER_32); ++ ++ break; ++ ++ } ++ ++ } ++ else /* no bridge */ ++ { ++ /* Read PCI_SUBSYS_ID_AND_SUBSYS_VENDOR_ID */ ++ pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ PCI_SUBSYS_ID_AND_SUBSYS_VENDOR_ID); ++ ++ ++ pPciAgent->subSysVenID = ++ (pciData & PSISVIR_VENID_MASK) >> PSISVIR_VENID_OFFS; ++ pPciAgent->subSysID = ++ (pciData & PSISVIR_DEVID_MASK) >> PSISVIR_DEVID_OFFS; ++ ++ ++ /* Read PCI_EXPANSION_ROM_BASE_ADDR_REG */ ++ pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ PCI_EXPANSION_ROM_BASE_ADDR_REG); ++ ++ ++ if (pciData & PERBAR_EXPROMEN) ++ { ++ pPciAgent->isExpRom = MV_TRUE; ++ } ++ else ++ { ++ pPciAgent->isExpRom = MV_FALSE; ++ } ++ ++ pPciAgent->expRomAddr = ++ (pciData & PERBAR_BASE_MASK) >> PERBAR_BASE_OFFS; ++ ++ } ++ ++ ++ if (MV_TRUE == pPciAgent->isCapListSupport) ++ { ++ /* Read PCI_CAPABILTY_LIST_POINTER */ ++ pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ PCI_CAPABILTY_LIST_POINTER); ++ ++ pPciAgent->capListPointer = ++ (pciData & PCLPR_CAPPTR_MASK) >> PCLPR_CAPPTR_OFFS; ++ ++ } ++ ++ /* Read PCI_INTERRUPT_PIN_AND_LINE */ ++ pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ PCI_INTERRUPT_PIN_AND_LINE); ++ ++ ++ pPciAgent->irqLine= ++ (pciData & PIPLR_INTLINE_MASK) >> PIPLR_INTLINE_OFFS; ++ ++ pPciAgent->intPin= ++ (MV_PCI_INT_PIN)(pciData & PIPLR_INTPIN_MASK) >> PIPLR_INTPIN_OFFS; ++ ++ pPciAgent->minGrant= ++ (pciData & PIPLR_MINGRANT_MASK) >> PIPLR_MINGRANT_OFFS; ++ pPciAgent->maxLatency= ++ (pciData & PIPLR_MAXLATEN_MASK) >> PIPLR_MAXLATEN_OFFS; ++ ++ mvPciClassNameGet(pPciAgent->baseClassCode, ++ (MV_8 *)pPciAgent->type); ++ ++ return MV_OK; ++ ++ ++} ++ ++/******************************************************************************* ++* pciDetectDeviceBars - Detect a pci device bars ++* ++* DESCRIPTION: ++* This function detects all pci agent bars ++* ++* INPUT: ++* pciIf - PCI Interface ++* bus - Bus number ++* dev - Device number ++* func - Function number ++* ++* ++* ++* OUTPUT: ++* pPciAgent - pointer to the pci agent filled with its information ++* ++* RETURN: ++* detected bars number ++* ++*******************************************************************************/ ++static MV_U32 pciDetectDeviceBars(MV_U32 pciIf, ++ MV_U32 bus, ++ MV_U32 dev, ++ MV_U32 func, ++ MV_PCI_DEVICE *pPciAgent) ++{ ++ MV_U32 pciData,barIndex,detectedBar=0; ++ MV_U32 tmpBaseHigh=0,tmpBaseLow=0; ++ MV_U32 pciMaxBars=0; ++ ++ pPciAgent->barsNum=0; ++ ++ /* check if we are bridge*/ ++ if ((pPciAgent->baseClassCode == PCI_BRIDGE_CLASS)&& ++ (pPciAgent->subClassCode == P2P_BRIDGE_SUB_CLASS_CODE)) ++ { ++ pciMaxBars = 2; ++ } ++ else /* no bridge */ ++ { ++ pciMaxBars = 6; ++ } ++ ++ /* read this device pci bars */ ++ for (barIndex = 0 ; barIndex < pciMaxBars ; barIndex++ ) ++ { ++ /* Read PCI_MEMORY_BAR_BASE_ADDR */ ++ tmpBaseLow = pciData = mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ PCI_MEMORY_BAR_BASE_ADDR(barIndex)); ++ ++ pPciAgent->pciBar[detectedBar].barOffset = ++ PCI_MEMORY_BAR_BASE_ADDR(barIndex); ++ ++ /* check if the bar is 32bit or 64bit bar */ ++ switch (pciData & PBBLR_TYPE_MASK) ++ { ++ case PBBLR_TYPE_32BIT_ADDR: ++ pPciAgent->pciBar[detectedBar].barType = PCI_32BIT_BAR; ++ break; ++ case PBBLR_TYPE_64BIT_ADDR: ++ pPciAgent->pciBar[detectedBar].barType = PCI_64BIT_BAR; ++ break; ++ ++ } ++ ++ /* check if it is memory or IO bar */ ++ if (pciData & PBBLR_IOSPACE) ++ { ++ pPciAgent->pciBar[detectedBar].barMapping=PCI_IO_BAR; ++ } ++ else ++ { ++ pPciAgent->pciBar[detectedBar].barMapping=PCI_MEMORY_BAR; ++ } ++ ++ /* if it is memory bar then check if it is prefetchable */ ++ if (PCI_MEMORY_BAR == pPciAgent->pciBar[detectedBar].barMapping) ++ { ++ if (pciData & PBBLR_PREFETCH_EN) ++ { ++ pPciAgent->pciBar[detectedBar].isPrefetchable = MV_TRUE; ++ } ++ else ++ { ++ pPciAgent->pciBar[detectedBar].isPrefetchable = MV_FALSE; ++ } ++ ++ pPciAgent->pciBar[detectedBar].barBaseLow = ++ pciData & PBBLR_MEM_BASE_MASK; ++ ++ ++ } ++ else /* IO Bar */ ++ { ++ pPciAgent->pciBar[detectedBar].barBaseLow = ++ pciData & PBBLR_IO_BASE_MASK; ++ ++ } ++ ++ pPciAgent->pciBar[detectedBar].barBaseHigh=0; ++ ++ if (PCI_64BIT_BAR == pPciAgent->pciBar[detectedBar].barType) ++ { ++ barIndex++; ++ ++ tmpBaseHigh = pPciAgent->pciBar[detectedBar].barBaseHigh = ++ mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ PCI_MEMORY_BAR_BASE_ADDR(barIndex)); ++ ++ ++ } ++ ++ /* calculating full base address (64bit) */ ++ pPciAgent->pciBar[detectedBar].barBaseAddr = ++ (MV_U64)pPciAgent->pciBar[detectedBar].barBaseHigh; ++ ++ pPciAgent->pciBar[detectedBar].barBaseAddr <<= 32; ++ ++ pPciAgent->pciBar[detectedBar].barBaseAddr |= ++ (MV_U64)pPciAgent->pciBar[detectedBar].barBaseLow; ++ ++ ++ ++ /* get the sizes of the the bar */ ++ ++ pPciAgent->pciBar[detectedBar].barSizeHigh=0; ++ ++ if ((PCI_64BIT_BAR == pPciAgent->pciBar[detectedBar].barType) && ++ (PCI_MEMORY_BAR == pPciAgent->pciBar[detectedBar].barMapping)) ++ ++ { ++ /* write oxffffffff to the bar to get the size */ ++ /* start with sizelow ( original value was saved in tmpBaseLow ) */ ++ mvPciIfConfigWrite(pciIf, ++ bus,dev,func, ++ PCI_MEMORY_BAR_BASE_ADDR(barIndex-1), ++ 0xffffffff); ++ ++ /* read size */ ++ pPciAgent->pciBar[detectedBar].barSizeLow = ++ mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ PCI_MEMORY_BAR_BASE_ADDR(barIndex-1)); ++ ++ ++ ++ /* restore original value */ ++ mvPciIfConfigWrite(pciIf, ++ bus,dev,func, ++ PCI_MEMORY_BAR_BASE_ADDR(barIndex-1), ++ tmpBaseLow); ++ ++ ++ /* now do the same for BaseHigh */ ++ ++ /* write oxffffffff to the bar to get the size */ ++ mvPciIfConfigWrite(pciIf, ++ bus,dev,func, ++ PCI_MEMORY_BAR_BASE_ADDR(barIndex), ++ 0xffffffff); ++ ++ /* read size */ ++ pPciAgent->pciBar[detectedBar].barSizeHigh = ++ mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ PCI_MEMORY_BAR_BASE_ADDR(barIndex)); ++ ++ /* restore original value */ ++ mvPciIfConfigWrite(pciIf, ++ bus,dev,func, ++ PCI_MEMORY_BAR_BASE_ADDR(barIndex), ++ tmpBaseHigh); ++ ++ if ((0 == pPciAgent->pciBar[detectedBar].barSizeLow)&& ++ (0 == pPciAgent->pciBar[detectedBar].barSizeHigh)) ++ { ++ /* this bar is not applicable for this device, ++ ignore all previous settings and check the next bar*/ ++ ++ /* we though this was a 64bit bar , and it seems this ++ was wrong ! so decrement barIndex */ ++ barIndex--; ++ continue; ++ } ++ ++ /* calculate the full 64 bit size */ ++ ++ if (0 != pPciAgent->pciBar[detectedBar].barSizeHigh) ++ { ++ pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_MEM_BASE_MASK; ++ ++ pPciAgent->pciBar[detectedBar].barSizeLow = ++ ~pPciAgent->pciBar[detectedBar].barSizeLow + 1; ++ ++ pPciAgent->pciBar[detectedBar].barSizeHigh = 0; ++ ++ } ++ else ++ { ++ ++ pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_MEM_BASE_MASK; ++ ++ pPciAgent->pciBar[detectedBar].barSizeLow = ++ ~pPciAgent->pciBar[detectedBar].barSizeLow + 1; ++ ++ pPciAgent->pciBar[detectedBar].barSizeHigh = 0; ++ ++ } ++ ++ ++ ++ } ++ else /* 32bit bar */ ++ { ++ /* write oxffffffff to the bar to get the size */ ++ mvPciIfConfigWrite(pciIf, ++ bus,dev,func, ++ PCI_MEMORY_BAR_BASE_ADDR(barIndex), ++ 0xffffffff); ++ ++ /* read size */ ++ pPciAgent->pciBar[detectedBar].barSizeLow = ++ mvPciIfConfigRead(pciIf, ++ bus,dev,func, ++ PCI_MEMORY_BAR_BASE_ADDR(barIndex)); ++ ++ if (0 == pPciAgent->pciBar[detectedBar].barSizeLow) ++ { ++ /* this bar is not applicable for this device, ++ ignore all previous settings and check the next bar*/ ++ continue; ++ } ++ ++ ++ /* restore original value */ ++ mvPciIfConfigWrite(pciIf, ++ bus,dev,func, ++ PCI_MEMORY_BAR_BASE_ADDR(barIndex), ++ tmpBaseLow); ++ ++ /* calculate size low */ ++ ++ if (PCI_MEMORY_BAR == pPciAgent->pciBar[detectedBar].barMapping) ++ { ++ pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_MEM_BASE_MASK; ++ } ++ else ++ { ++ pPciAgent->pciBar[detectedBar].barSizeLow &= PBBLR_IO_BASE_MASK; ++ } ++ ++ pPciAgent->pciBar[detectedBar].barSizeLow = ++ ~pPciAgent->pciBar[detectedBar].barSizeLow + 1; ++ ++ pPciAgent->pciBar[detectedBar].barSizeHigh = 0; ++ pPciAgent->pciBar[detectedBar].barSize = ++ (MV_U64)pPciAgent->pciBar[detectedBar].barSizeLow; ++ ++ ++ } ++ ++ /* we are here ! this means we have already detected a bar for ++ this device , now move on */ ++ ++ detectedBar++; ++ pPciAgent->barsNum++; ++ } ++ ++ return detectedBar; ++} ++ ++ ++/******************************************************************************* ++* mvPciClassNameGet - get PCI class name ++* ++* DESCRIPTION: ++* This function returns the PCI class name ++* ++* INPUT: ++* baseClassCode - Base Class Code. ++* ++* OUTPUT: ++* pType - the class name ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPciClassNameGet(MV_U32 baseClassCode, MV_8 *pType) ++{ ++ ++ switch(baseClassCode) ++ { ++ case 0x0: ++ strcpy(pType,"Old generation device"); ++ break; ++ case 0x1: ++ strcpy(pType,"Mass storage controller"); ++ break; ++ case 0x2: ++ strcpy(pType,"Network controller"); ++ break; ++ case 0x3: ++ strcpy(pType,"Display controller"); ++ break; ++ case 0x4: ++ strcpy(pType,"Multimedia device"); ++ break; ++ case 0x5: ++ strcpy(pType,"Memory controller"); ++ break; ++ case 0x6: ++ strcpy(pType,"Bridge Device"); ++ break; ++ case 0x7: ++ strcpy(pType,"Simple Communication controllers"); ++ break; ++ case 0x8: ++ strcpy(pType,"Base system peripherals"); ++ break; ++ case 0x9: ++ strcpy(pType,"Input Devices"); ++ break; ++ case 0xa: ++ strcpy(pType,"Docking stations"); ++ break; ++ case 0xb: ++ strcpy(pType,"Processors"); ++ break; ++ case 0xc: ++ strcpy(pType,"Serial bus controllers"); ++ break; ++ case 0xd: ++ strcpy(pType,"Wireless controllers"); ++ break; ++ case 0xe: ++ strcpy(pType,"Intelligent I/O controllers"); ++ break; ++ case 0xf: ++ strcpy(pType,"Satellite communication controllers"); ++ break; ++ case 0x10: ++ strcpy(pType,"Encryption/Decryption controllers"); ++ break; ++ case 0x11: ++ strcpy(pType,"Data acquisition and signal processing controllers"); ++ break; ++ default: ++ strcpy(pType,"Unknown device"); ++ break; ++ } ++ ++ return MV_OK; ++ ++} ++ ++ ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/pci_util/mvPciUtils.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,323 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvPciUtilsh ++#define __INCmvPciUtilsh ++ ++/* ++This module only support scanning of Header type 00h of pci devices ++There is no suppotr for Header type 01h of pci devices ( PCI bridges ) ++*/ ++ ++/* includes */ ++#include "mvSysHwConfig.h" ++#include "pci-if/mvPciIf.h" ++#include "pci/mvPciRegs.h" ++ ++ ++ ++/* PCI base address low bar mask */ ++#define PCI_ERROR_CODE 0xffffffff ++ ++#define PCI_BRIDGE_CLASS 0x6 ++#define P2P_BRIDGE_SUB_CLASS_CODE 0x4 ++ ++ ++#define P2P_BUSSES_NUM 0x18 ++#define P2P_IO_BASE_LIMIT_SEC_STATUS 0x1C ++#define P2P_MEM_BASE_LIMIT 0x20 ++#define P2P_PREF_MEM_BASE_LIMIT 0x24 ++#define P2P_PREF_BASE_UPPER_32 0x28 ++#define P2P_PREF_LIMIT_UPPER_32 0x2C ++#define P2P_IO_BASE_LIMIT_UPPER_16 0x30 ++#define P2P_EXP_ROM 0x38 ++ ++/* P2P_BUSSES_NUM (PBM) */ ++ ++#define PBM_PRIME_BUS_NUM_OFFS 0 ++#define PBM_PRIME_BUS_NUM_MASK (0xff << PBM_PRIME_BUS_NUM_OFFS) ++ ++#define PBM_SEC_BUS_NUM_OFFS 8 ++#define PBM_SEC_BUS_NUM_MASK (0xff << PBM_SEC_BUS_NUM_OFFS) ++ ++#define PBM_SUB_BUS_NUM_OFFS 16 ++#define PBM_SUB_BUS_NUM_MASK (0xff << PBM_SUB_BUS_NUM_OFFS) ++ ++#define PBM_SEC_LAT_TMR_OFFS 24 ++#define PBM_SEC_LAT_TMR_MASK (0xff << PBM_SEC_LAT_TMR_OFFS) ++ ++/* P2P_IO_BASE_LIMIT_SEC_STATUS (PIBLSS) */ ++ ++#define PIBLSS_IO_BASE_OFFS 0 ++#define PIBLSS_IO_BASE_MASK (0xff << PIBLSS_IO_BASE_OFFS) ++ ++#define PIBLSS_ADD_CAP_OFFS 0 ++#define PIBLSS_ADD_CAP_MASK (0x3 << PIBLSS_ADD_CAP_OFFS) ++#define PIBLSS_ADD_CAP_16BIT (0x0 << PIBLSS_ADD_CAP_OFFS) ++#define PIBLSS_ADD_CAP_32BIT (0x1 << PIBLSS_ADD_CAP_OFFS) ++ ++#define PIBLSS_LOW_ADDR_OFFS 0 ++#define PIBLSS_LOW_ADDR_MASK (0xFFF << PIBLSS_LOW_ADDR_OFFS) ++ ++#define PIBLSS_HIGH_ADDR_OFFS 12 ++#define PIBLSS_HIGH_ADDR_MASK (0xF << PIBLSS_HIGH_ADDR_OFFS) ++ ++#define PIBLSS_IO_LIMIT_OFFS 8 ++#define PIBLSS_IO_LIMIT_MASK (0xff << PIBLSS_IO_LIMIT_OFFS) ++ ++#define PIBLSS_SEC_STATUS_OFFS 16 ++#define PIBLSS_SEC_STATUS_MASK (0xffff << PIBLSS_SEC_STATUS_OFFS) ++ ++ ++/* P2P_MEM_BASE_LIMIT (PMBL)*/ ++ ++#define PMBL_MEM_BASE_OFFS 0 ++#define PMBL_MEM_BASE_MASK (0xffff << PMBL_MEM_BASE_OFFS) ++ ++#define PMBL_MEM_LIMIT_OFFS 16 ++#define PMBL_MEM_LIMIT_MASK (0xffff << PMBL_MEM_LIMIT_OFFS) ++ ++ ++#define PMBL_LOW_ADDR_OFFS 0 ++#define PMBL_LOW_ADDR_MASK (0xFFFFF << PMBL_LOW_ADDR_OFFS) ++ ++#define PMBL_HIGH_ADDR_OFFS 20 ++#define PMBL_HIGH_ADDR_MASK (0xFFF << PMBL_HIGH_ADDR_OFFS) ++ ++ ++/* P2P_PREF_MEM_BASE_LIMIT (PRMBL) */ ++ ++#define PRMBL_PREF_MEM_BASE_OFFS 0 ++#define PRMBL_PREF_MEM_BASE_MASK (0xffff << PRMBL_PREF_MEM_BASE_OFFS) ++ ++#define PRMBL_PREF_MEM_LIMIT_OFFS 16 ++#define PRMBL_PREF_MEM_LIMIT_MASK (0xffff<= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexModeGet: ERR. Invalid PEX interface %d\n",pexIf); ++ return MV_ERROR; ++ } ++ } ++ ++ pexData = MV_REG_READ(PEX_CTRL_REG(pexIf)); ++ ++ switch (pexData & PXCR_DEV_TYPE_CTRL_MASK) ++ { ++ case PXCR_DEV_TYPE_CTRL_CMPLX: ++ pexMode->pexType = MV_PEX_ROOT_COMPLEX; ++ break; ++ case PXCR_DEV_TYPE_CTRL_POINT: ++ pexMode->pexType = MV_PEX_END_POINT; ++ break; ++ ++ } ++ ++ /* Check if we have link */ ++ if (MV_REG_READ(PEX_STATUS_REG(pexIf)) & PXSR_DL_DOWN) ++ { ++ pexMode->pexLinkUp = MV_FALSE; ++ ++ /* If there is no link, the auto negotiation data is worthless */ ++ pexMode->pexWidth = MV_PEX_WITDH_INVALID; ++ } ++ else ++ { ++ pexMode->pexLinkUp = MV_TRUE; ++ ++ /* We have link. The link width is now valid */ ++ pexData = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG)); ++ pexMode->pexWidth = ((pexData & PXLCSR_NEG_LNK_WDTH_MASK) >> ++ PXLCSR_NEG_LNK_WDTH_OFFS); ++ } ++ ++ return MV_OK; ++} ++ ++ ++/* PEX configuration space read write */ ++ ++/******************************************************************************* ++* mvPexConfigRead - Read from configuration space ++* ++* DESCRIPTION: ++* This function performs a 32 bit read from PEX configuration space. ++* It supports both type 0 and type 1 of Configuration Transactions ++* (local and over bridge). In order to read from local bus segment, use ++* bus number retrieved from mvPexLocalBusNumGet(). Other bus numbers ++* will result configuration transaction of type 1 (over bridge). ++* ++* INPUT: ++* pexIf - PEX interface number. ++* bus - PEX segment bus number. ++* dev - PEX device number. ++* func - Function number. ++* regOffs - Register offset. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* 32bit register data, 0xffffffff on error ++* ++*******************************************************************************/ ++MV_U32 mvPexConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, ++ MV_U32 regOff) ++{ ++#if defined(PCIE_VIRTUAL_BRIDGE_SUPPORT) ++ return mvPexVrtBrgConfigRead (pexIf, bus, dev, func, regOff); ++} ++ ++MV_U32 mvPexHwConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, ++ MV_U32 regOff) ++{ ++#endif ++ MV_U32 pexData = 0; ++ MV_U32 localDev,localBus; ++ ++ /* Parameter checking */ ++ if (PEX_DEFAULT_IF != pexIf) ++ { ++ if (pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexConfigRead: ERR. Invalid PEX interface %d\n",pexIf); ++ return 0xFFFFFFFF; ++ } ++ } ++ ++ if (dev >= MAX_PEX_DEVICES) ++ { ++ DB(mvOsPrintf("mvPexConfigRead: ERR. device number illigal %d\n", dev)); ++ return 0xFFFFFFFF; ++ } ++ ++ if (func >= MAX_PEX_FUNCS) ++ { ++ DB(mvOsPrintf("mvPexConfigRead: ERR. function num illigal %d\n", func)); ++ return 0xFFFFFFFF; ++ } ++ ++ if (bus >= MAX_PEX_BUSSES) ++ { ++ DB(mvOsPrintf("mvPexConfigRead: ERR. bus number illigal %d\n", bus)); ++ return MV_ERROR; ++ } ++ ++ DB(mvOsPrintf("mvPexConfigRead: pexIf %d, bus %d, dev %d, func %d, regOff 0x%x\n", ++ pexIf, bus, dev, func, regOff)); ++ ++ localDev = mvPexLocalDevNumGet(pexIf); ++ localBus = mvPexLocalBusNumGet(pexIf); ++ ++ /* Speed up the process. In case on no link, return MV_ERROR */ ++ if ((dev != localDev) || (bus != localBus)) ++ { ++ pexData = MV_REG_READ(PEX_STATUS_REG(pexIf)); ++ ++ if ((pexData & PXSR_DL_DOWN)) ++ { ++ return MV_ERROR; ++ } ++ } ++ ++ /* in PCI Express we have only one device number */ ++ /* and this number is the first number we encounter ++ else that the localDev*/ ++ /* spec pex define return on config read/write on any device */ ++ if (bus == localBus) ++ { ++ if (localDev == 0) ++ { ++ /* if local dev is 0 then the first number we encounter ++ after 0 is 1 */ ++ if ((dev != 1)&&(dev != localDev)) ++ { ++ return MV_ERROR; ++ } ++ } ++ else ++ { ++ /* if local dev is not 0 then the first number we encounter ++ is 0 */ ++ ++ if ((dev != 0)&&(dev != localDev)) ++ { ++ return MV_ERROR; ++ } ++ } ++ if(func != 0 ) /* i.e bridge */ ++ { ++ return MV_ERROR; ++ } ++ } ++ ++ ++ /* Creating PEX address to be passed */ ++ pexData = (bus << PXCAR_BUS_NUM_OFFS); ++ pexData |= (dev << PXCAR_DEVICE_NUM_OFFS); ++ pexData |= (func << PXCAR_FUNC_NUM_OFFS); ++ pexData |= (regOff & PXCAR_REG_NUM_MASK); /* lgacy register space */ ++ /* extended register space */ ++ pexData |=(((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >> ++ PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS); ++ ++ pexData |= PXCAR_CONFIG_EN; ++ ++ /* Write the address to the PEX configuration address register */ ++ MV_REG_WRITE(PEX_CFG_ADDR_REG(pexIf), pexData); ++ ++ DB(mvOsPrintf("mvPexConfigRead:address pexData=%x ",pexData)); ++ ++ ++ /* In order to let the PEX controller absorbed the address of the read */ ++ /* transaction we perform a validity check that the address was written */ ++ if(pexData != MV_REG_READ(PEX_CFG_ADDR_REG(pexIf))) ++ { ++ return MV_ERROR; ++ } ++ ++ /* cleaning Master Abort */ ++ MV_REG_BIT_SET(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_STATUS_AND_COMMAND), ++ PXSAC_MABORT); ++#if 0 ++ /* Guideline (GL# PCI Express-1) Erroneous Read Data on Configuration */ ++ /* This guideline is relevant for all devices except of the following devices: ++ 88F5281-BO and above, 88F5181L-A0 and above, 88F1281 A0 and above ++ 88F6183 A0 and above, 88F6183L */ ++ if ( ( (dev != localDev) || (bus != localBus) ) && ++ ( ++ !(MV_5281_DEV_ID == mvCtrlModelGet())&& ++ !((MV_5181_DEV_ID == mvCtrlModelGet())&& (mvCtrlRevGet() >= MV_5181L_A0_REV))&& ++ !(MV_1281_DEV_ID == mvCtrlModelGet())&& ++ !(MV_6183_DEV_ID == mvCtrlModelGet())&& ++ !(MV_6183L_DEV_ID == mvCtrlModelGet())&& ++ !(MV_6281_DEV_ID == mvCtrlModelGet())&& ++ !(MV_6192_DEV_ID == mvCtrlModelGet())&& ++ !(MV_6190_DEV_ID == mvCtrlModelGet())&& ++ !(MV_6180_DEV_ID == mvCtrlModelGet())&& ++ !(MV_78XX0_DEV_ID == mvCtrlModelGet()) ++ )) ++ { ++ ++ /* PCI-Express configuration read work-around */ ++ ++ /* we will use one of the Punit (AHBToMbus) windows to access the xbar ++ and read the data from there */ ++ /* ++ Need to configure the 2 free Punit (AHB to MBus bridge) ++ address decoding windows: ++ Configure the flash Window to handle Configuration space requests ++ for PEX0/1: ++ 1. write 0x7931/0x7941 to the flash window and the size, ++ 79-xbar attr (pci cfg), 3/4-xbar target (pex0/1), 1-WinEn ++ 2. write base to flash window ++ ++ Configuration transactions from the CPU should write/read the data ++ to/from address of the form: ++ addr[31:28] = 0x5 (for PEX0) or 0x6 (for PEX1) ++ addr[27:24] = extended register number ++ addr[23:16] = bus number ++ addr[15:11] = device number ++ addr[10:8] = function number ++ addr[7:0] = register number ++ */ ++ ++ #include "ctrlEnv/sys/mvAhbToMbus.h" ++ { ++ MV_U32 winNum; ++ MV_AHB_TO_MBUS_DEC_WIN originWin; ++ MV_U32 pciAddr=0; ++ MV_U32 remapLow=0,remapHigh=0; ++ ++ /* ++ We will use DEV_CS2\Flash window for this workarround ++ */ ++ ++ winNum = mvAhbToMbusWinTargetGet(PEX_CONFIG_RW_WA_TARGET); ++ ++ /* save remap values if exist */ ++ if ((1 == winNum)||(0 == winNum)) ++ { ++ remapLow = MV_REG_READ(AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum)); ++ remapHigh = MV_REG_READ(AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum)); ++ ++ } ++ ++ ++ /* save the original window values */ ++ mvAhbToMbusWinGet(winNum,&originWin); ++ ++ if (PEX_CONFIG_RW_WA_USE_ORIGINAL_WIN_VALUES) ++ { ++ /* set the window as xbar window */ ++ if (pexIf) ++ { ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ++ (0x7931 | (((originWin.addrWin.size >> 16)-1) ) << 16)); ++ } ++ else ++ { ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ++ (0x7941 | (((originWin.addrWin.size >> 16)-1) ) << 16)); ++ } ++ ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum), ++ originWin.addrWin.baseLow); ++ ++ /*pciAddr = originWin.addrWin.baseLow;*/ ++ pciAddr = (MV_U32)CPU_MEMIO_UNCACHED_ADDR( ++ (MV_U32)originWin.addrWin.baseLow); ++ ++ } ++ else ++ { ++ /* set the window as xbar window */ ++ if (pexIf) ++ { ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ++ (0x7931 | (((PEX_CONFIG_RW_WA_SIZE >> 16)-1) ) << 16)); ++ } ++ else ++ { ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), ++ (0x7941 | (((PEX_CONFIG_RW_WA_SIZE >> 16)-1) ) << 16)); ++ } ++ ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum), ++ PEX_CONFIG_RW_WA_BASE); ++ ++ pciAddr = (MV_U32)CPU_MEMIO_UNCACHED_ADDR(PEX_CONFIG_RW_WA_BASE); ++ } ++ ++ ++ /* remap should be as base */ ++ if ((1 == winNum)||(0 == winNum)) ++ { ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum),pciAddr); ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum),0); ++ ++ } ++ ++ /* extended register space */ ++ pciAddr |= (bus << 16); ++ pciAddr |= (dev << 11); ++ pciAddr |= (func << 8); ++ pciAddr |= (regOff & PXCAR_REG_NUM_MASK); /* lgacy register space */ ++ ++ pexData = *(MV_U32*)pciAddr; ++ pexData = MV_32BIT_LE(pexData); /* Data always in LE */ ++ ++ /* restore the original window values */ ++ mvAhbToMbusWinSet(winNum,&originWin); ++ ++ /* restore original remap values*/ ++ if ((1 == winNum)||(0 == winNum)) ++ { ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum),remapLow); ++ MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum),remapHigh); ++ ++ } ++ } ++ } ++ else ++#endif ++ { ++ /* Read the Data returned in the PEX Data register */ ++ pexData = MV_REG_READ(PEX_CFG_DATA_REG(pexIf)); ++ ++ } ++ ++ DB(mvOsPrintf("mvPexConfigRead: got : %x \n",pexData)); ++ ++ return pexData; ++ ++} ++ ++/******************************************************************************* ++* mvPexConfigWrite - Write to configuration space ++* ++* DESCRIPTION: ++* This function performs a 32 bit write to PEX configuration space. ++* It supports both type 0 and type 1 of Configuration Transactions ++* (local and over bridge). In order to write to local bus segment, use ++* bus number retrieved from mvPexLocalBusNumGet(). Other bus numbers ++* will result configuration transaction of type 1 (over bridge). ++* ++* INPUT: ++* pexIf - PEX interface number. ++* bus - PEX segment bus number. ++* dev - PEX device number. ++* func - Function number. ++* regOffs - Register offset. ++* data - 32bit data. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPexConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func, MV_U32 regOff, MV_U32 data) ++{ ++#if defined(PCIE_VIRTUAL_BRIDGE_SUPPORT) ++ return mvPexVrtBrgConfigWrite (pexIf, bus, dev, func, regOff, data); ++} ++ ++MV_STATUS mvPexHwConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func, MV_U32 regOff, MV_U32 data) ++{ ++#endif ++ MV_U32 pexData = 0; ++ MV_U32 localDev,localBus; ++ ++ /* Parameter checking */ ++ if (PEX_DEFAULT_IF != pexIf) ++ { ++ if (pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexConfigWrite: ERR. Invalid PEX interface %d\n", ++ pexIf); ++ return MV_ERROR; ++ } ++ } ++ ++ if (dev >= MAX_PEX_DEVICES) ++ { ++ mvOsPrintf("mvPexConfigWrite: ERR. device number illigal %d\n",dev); ++ return MV_BAD_PARAM; ++ } ++ ++ if (func >= MAX_PEX_FUNCS) ++ { ++ mvOsPrintf("mvPexConfigWrite: ERR. function number illigal %d\n", func); ++ return MV_ERROR; ++ } ++ ++ if (bus >= MAX_PEX_BUSSES) ++ { ++ mvOsPrintf("mvPexConfigWrite: ERR. bus number illigal %d\n", bus); ++ return MV_ERROR; ++ } ++ ++ ++ ++ localDev = mvPexLocalDevNumGet(pexIf); ++ localBus = mvPexLocalBusNumGet(pexIf); ++ ++ ++ /* in PCI Express we have only one device number other than ourselves*/ ++ /* and this number is the first number we encounter ++ else than the localDev that can be any valid dev number*/ ++ /* pex spec define return on config read/write on any device */ ++ if (bus == localBus) ++ { ++ ++ if (localDev == 0) ++ { ++ /* if local dev is 0 then the first number we encounter ++ after 0 is 1 */ ++ if ((dev != 1)&&(dev != localDev)) ++ { ++ return MV_ERROR; ++ } ++ ++ } ++ else ++ { ++ /* if local dev is not 0 then the first number we encounter ++ is 0 */ ++ ++ if ((dev != 0)&&(dev != localDev)) ++ { ++ return MV_ERROR; ++ } ++ } ++ ++ ++ } ++ ++ /* if we are not accessing ourselves , then check the link */ ++ if ((dev != localDev) || (bus != localBus) ) ++ { ++ /* workarround */ ++ /* when no link return MV_ERROR */ ++ ++ pexData = MV_REG_READ(PEX_STATUS_REG(pexIf)); ++ ++ if ((pexData & PXSR_DL_DOWN)) ++ { ++ return MV_ERROR; ++ } ++ ++ } ++ ++ pexData =0; ++ ++ /* Creating PEX address to be passed */ ++ pexData |= (bus << PXCAR_BUS_NUM_OFFS); ++ pexData |= (dev << PXCAR_DEVICE_NUM_OFFS); ++ pexData |= (func << PXCAR_FUNC_NUM_OFFS); ++ pexData |= (regOff & PXCAR_REG_NUM_MASK); /* lgacy register space */ ++ /* extended register space */ ++ pexData |=(((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >> ++ PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS); ++ pexData |= PXCAR_CONFIG_EN; ++ ++ DB(mvOsPrintf("mvPexConfigWrite: If=%x bus=%x func=%x dev=%x regOff=%x data=%x \n", ++ pexIf,bus,func,dev,regOff,data,pexData) ); ++ ++ /* Write the address to the PEX configuration address register */ ++ MV_REG_WRITE(PEX_CFG_ADDR_REG(pexIf), pexData); ++ ++ /* Clear CPU pipe. Important where CPU can perform OOO execution */ ++ CPU_PIPE_FLUSH; ++ ++ /* In order to let the PEX controller absorbed the address of the read */ ++ /* transaction we perform a validity check that the address was written */ ++ if(pexData != MV_REG_READ(PEX_CFG_ADDR_REG(pexIf))) ++ { ++ return MV_ERROR; ++ } ++ ++ /* Write the Data passed to the PEX Data register */ ++ MV_REG_WRITE(PEX_CFG_DATA_REG(pexIf), data); ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvPexMasterEnable - Enable/disale PEX interface master transactions. ++* ++* DESCRIPTION: ++* This function performs read modified write to PEX command status ++* (offset 0x4) to set/reset bit 2. After this bit is set, the PEX ++* master is allowed to gain ownership on the bus, otherwise it is ++* incapable to do so. ++* ++* INPUT: ++* pexIf - PEX interface number. ++* enable - Enable/disable parameter. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPexMasterEnable(MV_U32 pexIf, MV_BOOL enable) ++{ ++ MV_U32 pexCommandStatus; ++ MV_U32 localBus; ++ MV_U32 localDev; ++ ++ /* Parameter checking */ ++ if (pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexMasterEnable: ERR. Invalid PEX interface %d\n", pexIf); ++ return MV_ERROR; ++ } ++ ++ localBus = mvPexLocalBusNumGet(pexIf); ++ localDev = mvPexLocalDevNumGet(pexIf); ++ ++ pexCommandStatus = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, ++ PEX_STATUS_AND_COMMAND)); ++ ++ ++ if (MV_TRUE == enable) ++ { ++ pexCommandStatus |= PXSAC_MASTER_EN; ++ } ++ else ++ { ++ pexCommandStatus &= ~PXSAC_MASTER_EN; ++ } ++ ++ ++ MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_STATUS_AND_COMMAND), ++ pexCommandStatus); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvPexSlaveEnable - Enable/disale PEX interface slave transactions. ++* ++* DESCRIPTION: ++* This function performs read modified write to PEX command status ++* (offset 0x4) to set/reset bit 0 and 1. After those bits are set, ++* the PEX slave is allowed to respond to PEX IO space access (bit 0) ++* and PEX memory space access (bit 1). ++* ++* INPUT: ++* pexIf - PEX interface number. ++* dev - PEX device number. ++* enable - Enable/disable parameter. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPexSlaveEnable(MV_U32 pexIf, MV_U32 bus,MV_U32 dev, MV_BOOL enable) ++{ ++ MV_U32 pexCommandStatus; ++ MV_U32 RegOffs; ++ ++ /* Parameter checking */ ++ if (pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexSlaveEnable: ERR. Invalid PEX interface %d\n", pexIf); ++ return MV_BAD_PARAM; ++ } ++ if (dev >= MAX_PEX_DEVICES) ++ { ++ mvOsPrintf("mvPexLocalDevNumSet: ERR. device number illigal %d\n", dev); ++ return MV_BAD_PARAM; ++ ++ } ++ ++ ++ RegOffs = PEX_STATUS_AND_COMMAND; ++ ++ pexCommandStatus = mvPexConfigRead(pexIf, bus, dev, 0, RegOffs); ++ ++ if (MV_TRUE == enable) ++ { ++ pexCommandStatus |= (PXSAC_IO_EN | PXSAC_MEM_EN); ++ } ++ else ++ { ++ pexCommandStatus &= ~(PXSAC_IO_EN | PXSAC_MEM_EN); ++ } ++ ++ mvPexConfigWrite(pexIf, bus, dev, 0, RegOffs, pexCommandStatus); ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvPexLocalBusNumSet - Set PEX interface local bus number. ++* ++* DESCRIPTION: ++* This function sets given PEX interface its local bus number. ++* Note: In case the PEX interface is PEX-X, the information is read-only. ++* ++* INPUT: ++* pexIf - PEX interface number. ++* busNum - Bus number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_NOT_ALLOWED in case PEX interface is PEX-X. ++* MV_BAD_PARAM on bad parameters , ++* otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPexLocalBusNumSet(MV_U32 pexIf, MV_U32 busNum) ++{ ++ MV_U32 pexStatus; ++ MV_U32 localBus; ++ MV_U32 localDev; ++ ++ ++ /* Parameter checking */ ++ if (pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexLocalBusNumSet: ERR. Invalid PEX interface %d\n",pexIf); ++ return MV_BAD_PARAM; ++ } ++ if (busNum >= MAX_PEX_BUSSES) ++ { ++ mvOsPrintf("mvPexLocalBusNumSet: ERR. bus number illigal %d\n", busNum); ++ return MV_ERROR; ++ ++ } ++ ++ localBus = mvPexLocalBusNumGet(pexIf); ++ localDev = mvPexLocalDevNumGet(pexIf); ++ ++ ++ ++ pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); ++ ++ pexStatus &= ~PXSR_PEX_BUS_NUM_MASK; ++ ++ pexStatus |= (busNum << PXSR_PEX_BUS_NUM_OFFS) & PXSR_PEX_BUS_NUM_MASK; ++ ++ MV_REG_WRITE(PEX_STATUS_REG(pexIf), pexStatus); ++ ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvPexLocalBusNumGet - Get PEX interface local bus number. ++* ++* DESCRIPTION: ++* This function gets the local bus number of a given PEX interface. ++* ++* INPUT: ++* pexIf - PEX interface number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Local bus number.0xffffffff on Error ++* ++*******************************************************************************/ ++MV_U32 mvPexLocalBusNumGet(MV_U32 pexIf) ++{ ++ MV_U32 pexStatus; ++ ++ /* Parameter checking */ ++ if (PEX_DEFAULT_IF != pexIf) ++ { ++ if (pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexLocalBusNumGet: ERR. Invalid PEX interface %d\n",pexIf); ++ return 0xFFFFFFFF; ++ } ++ } ++ ++ ++ pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); ++ ++ pexStatus &= PXSR_PEX_BUS_NUM_MASK; ++ ++ return (pexStatus >> PXSR_PEX_BUS_NUM_OFFS); ++ ++} ++ ++ ++/******************************************************************************* ++* mvPexLocalDevNumSet - Set PEX interface local device number. ++* ++* DESCRIPTION: ++* This function sets given PEX interface its local device number. ++* Note: In case the PEX interface is PEX-X, the information is read-only. ++* ++* INPUT: ++* pexIf - PEX interface number. ++* devNum - Device number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_NOT_ALLOWED in case PEX interface is PEX-X. ++* MV_BAD_PARAM on bad parameters , ++* otherwise MV_OK ++* ++*******************************************************************************/ ++MV_STATUS mvPexLocalDevNumSet(MV_U32 pexIf, MV_U32 devNum) ++{ ++ MV_U32 pexStatus; ++ MV_U32 localBus; ++ MV_U32 localDev; ++ ++ /* Parameter checking */ ++ if (pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexLocalDevNumSet: ERR. Invalid PEX interface %d\n",pexIf); ++ return MV_BAD_PARAM; ++ } ++ if (devNum >= MAX_PEX_DEVICES) ++ { ++ mvOsPrintf("mvPexLocalDevNumSet: ERR. device number illigal %d\n", ++ devNum); ++ return MV_BAD_PARAM; ++ ++ } ++ ++ localBus = mvPexLocalBusNumGet(pexIf); ++ localDev = mvPexLocalDevNumGet(pexIf); ++ ++ ++ pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); ++ ++ pexStatus &= ~PXSR_PEX_DEV_NUM_MASK; ++ ++ pexStatus |= (devNum << PXSR_PEX_DEV_NUM_OFFS) & PXSR_PEX_DEV_NUM_MASK; ++ ++ MV_REG_WRITE(PEX_STATUS_REG(pexIf), pexStatus); ++ ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvPexLocalDevNumGet - Get PEX interface local device number. ++* ++* DESCRIPTION: ++* This function gets the local device number of a given PEX interface. ++* ++* INPUT: ++* pexIf - PEX interface number. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Local device number. 0xffffffff on Error ++* ++*******************************************************************************/ ++MV_U32 mvPexLocalDevNumGet(MV_U32 pexIf) ++{ ++ MV_U32 pexStatus; ++ ++ /* Parameter checking */ ++ ++ if (PEX_DEFAULT_IF != pexIf) ++ { ++ if (pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexLocalDevNumGet: ERR. Invalid PEX interface %d\n", ++ pexIf); ++ return 0xFFFFFFFF; ++ } ++ } ++ ++ pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); ++ ++ pexStatus &= PXSR_PEX_DEV_NUM_MASK; ++ ++ return (pexStatus >> PXSR_PEX_DEV_NUM_OFFS); ++} ++ ++MV_VOID mvPexPhyRegRead(MV_U32 pexIf, MV_U32 regOffset, MV_U16 *value) ++{ ++ ++ MV_U32 regAddr; ++ if (pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexPhyRegRead: ERR. Invalid PEX interface %d\n", pexIf); ++ return; ++ } ++ regAddr = (BIT31 | ((regOffset & 0x3fff) << 16)); ++ MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexIf), regAddr); ++ *value = MV_REG_READ(PEX_PHY_ACCESS_REG(pexIf)); ++} ++ ++ ++MV_VOID mvPexPhyRegWrite(MV_U32 pexIf, MV_U32 regOffset, MV_U16 value) ++{ ++ ++ MV_U32 regAddr; ++ if(pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexPhyRegWrite: ERR. Invalid PEX interface %d\n", pexIf); ++ return; ++ } ++ regAddr = (((regOffset & 0x3fff) << 16) | value); ++ MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexIf), regAddr); ++} ++ ++/******************************************************************************* ++* mvPexActiveStateLinkPMEnable ++* ++* DESCRIPTION: ++* Enable Active Link State Power Management ++* ++* INPUT: ++* pexIf - PEX interface number. ++* enable - MV_TRUE to enable ASPM, MV_FALSE to disable. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* MV_OK on success , MV_ERROR otherwise ++* ++*******************************************************************************/ ++MV_STATUS mvPexActiveStateLinkPMEnable(MV_U32 pexIf, MV_BOOL enable) ++{ ++ MV_U32 reg; ++ ++ if(pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexActiveStateLinkPMEnable: ERR. Invalid PEX interface %d\n", pexIf); ++ return MV_ERROR; ++ } ++ ++ reg = MV_REG_READ(PEX_PWR_MNG_EXT_REG(pexIf)) & ~PXPMER_L1_ASPM_EN_MASK; ++ if(enable == MV_TRUE) ++ reg |= PXPMER_L1_ASPM_EN_MASK; ++ MV_REG_WRITE(PEX_PWR_MNG_EXT_REG(pexIf), reg); ++ ++ /* Enable / Disable L0/1 entry */ ++ reg = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG)) ++ & ~PXLCSR_ASPM_CNT_MASK; ++ if(enable == MV_TRUE) ++ reg |= PXLCSR_ASPM_CNT_L0S_L1S_ENT_SUPP; ++ MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG), reg); ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvPexForceX1 ++* ++* DESCRIPTION: ++* shut down lanes 1-3 if recognize that attached to an x1 end-point ++* INPUT: ++* pexIf - PEX interface number. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* MV_OK on success , MV_ERROR otherwise ++* ++*******************************************************************************/ ++MV_U32 mvPexForceX1(MV_U32 pexIf) ++{ ++ MV_U32 regData = 0; ++ if(pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexForceX1: ERR. Invalid PEX interface %d\n", pexIf); ++ return MV_BAD_PARAM; ++ } ++ ++ regData = MV_REG_READ(PEX_CTRL_REG(pexIf)) & ~(PXCR_CONF_LINK_MASK) ; ++ regData |= PXCR_CONF_LINK_X1; ++ ++ MV_REG_WRITE(PEX_CTRL_REG(pexIf), regData); ++ return MV_OK; ++} ++ ++MV_BOOL mvPexIsPowerUp(MV_U32 pexIf) ++{ ++ if(pexIf >= mvCtrlPexMaxIfGet()) ++ { ++ mvOsPrintf("mvPexIsPowerUp: ERR. Invalid PEX interface %d\n", pexIf); ++ return MV_FALSE; ++ } ++ return mvCtrlPwrClckGet(PEX_UNIT_ID, pexIf); ++} ++ ++ ++MV_VOID mvPexPowerDown(MV_U32 pexIf) ++{ ++ if ( (mvCtrlModelGet() == MV_78XX0_DEV_ID) || ++ (mvCtrlModelGet() == MV_76100_DEV_ID) || ++ (mvCtrlModelGet() == MV_78100_DEV_ID) || ++ (mvCtrlModelGet() == MV_78200_DEV_ID) ) ++ { ++ mvCtrlPwrClckSet(PEX_UNIT_ID, pexIf, MV_FALSE); ++ } ++ else ++ { ++ MV_REG_WRITE((0x41B00 -(pexIf)*0x10000), 0x20800087); ++ } ++} ++ ++ ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,168 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCPEXH ++#define __INCPEXH ++ ++#include "mvCommon.h" ++#include "mvOs.h" ++#include "pex/mvPexRegs.h" ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++ ++ ++ ++/* NOTE not supported in this driver:*/ ++ ++ ++/* defines */ ++/* The number of supported PEX interfaces depend on Marvell controller */ ++/* device number. This device number ID is located on the PEX unit */ ++/* configuration header. This creates a loop where calling PEX */ ++/* configuration read/write routine results a call to get PEX configuration */ ++/* information etc. This macro defines a default PEX interface. This PEX */ ++/* interface is sure to exist. */ ++#define PEX_DEFAULT_IF 0 ++ ++ ++/* typedefs */ ++/* The Marvell controller supports both root complex and end point devices */ ++/* This enumeration describes the PEX type. */ ++typedef enum _mvPexType ++{ ++ MV_PEX_ROOT_COMPLEX, /* root complex device */ ++ MV_PEX_END_POINT /* end point device */ ++}MV_PEX_TYPE; ++ ++typedef enum _mvPexWidth ++{ ++ MV_PEX_WITDH_X1 = 1, ++ MV_PEX_WITDH_X2, ++ MV_PEX_WITDH_X3, ++ MV_PEX_WITDH_X4, ++ MV_PEX_WITDH_INVALID ++}MV_PEX_WIDTH; ++ ++/* PEX Bar attributes */ ++typedef struct _mvPexMode ++{ ++ MV_PEX_TYPE pexType; ++ MV_PEX_WIDTH pexWidth; ++ MV_BOOL pexLinkUp; ++}MV_PEX_MODE; ++ ++ ++ ++/* Global Functions prototypes */ ++/* mvPexInit - Initialize PEX interfaces*/ ++MV_STATUS mvPexHalInit(MV_U32 pexIf, MV_PEX_TYPE pexType); ++ ++/* mvPexModeGet - Get Pex If mode */ ++MV_U32 mvPexModeGet(MV_U32 pexIf,MV_PEX_MODE *pexMode); ++ ++/* mvPexConfigRead - Read from configuration space */ ++MV_U32 mvPexConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func,MV_U32 regOff); ++ ++/* mvPexConfigWrite - Write to configuration space */ ++MV_STATUS mvPexConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func, MV_U32 regOff, MV_U32 data); ++ ++/* mvPexMasterEnable - Enable/disale PEX interface master transactions.*/ ++MV_STATUS mvPexMasterEnable(MV_U32 pexIf, MV_BOOL enable); ++ ++/* mvPexSlaveEnable - Enable/disale PEX interface slave transactions.*/ ++MV_STATUS mvPexSlaveEnable(MV_U32 pexIf, MV_U32 bus,MV_U32 dev, MV_BOOL enable); ++ ++/* mvPexLocalBusNumSet - Set PEX interface local bus number.*/ ++MV_STATUS mvPexLocalBusNumSet(MV_U32 pexIf, MV_U32 busNum); ++ ++/* mvPexLocalBusNumGet - Get PEX interface local bus number.*/ ++MV_U32 mvPexLocalBusNumGet(MV_U32 pexIf); ++ ++/* mvPexLocalDevNumSet - Set PEX interface local device number.*/ ++MV_STATUS mvPexLocalDevNumSet(MV_U32 pexIf, MV_U32 devNum); ++ ++/* mvPexLocalDevNumGet - Get PEX interface local device number.*/ ++MV_U32 mvPexLocalDevNumGet(MV_U32 pexIf); ++/* mvPexForceX1 - Force PEX interface to X1 mode. */ ++MV_U32 mvPexForceX1(MV_U32 pexIf); ++ ++/* mvPexIsPowerUp - Is PEX interface Power up? */ ++MV_BOOL mvPexIsPowerUp(MV_U32 pexIf); ++ ++/* mvPexPowerDown - Power Down */ ++MV_VOID mvPexPowerDown(MV_U32 pexIf); ++ ++/* mvPexPowerUp - Power Up */ ++MV_VOID mvPexPowerUp(MV_U32 pexIf); ++ ++/* mvPexPhyRegRead - Pex phy read */ ++MV_VOID mvPexPhyRegRead(MV_U32 pexIf, MV_U32 regOffset, MV_U16 *value); ++ ++/* mvPexPhyRegWrite - Pex phy write */ ++MV_VOID mvPexPhyRegWrite(MV_U32 pexIf, MV_U32 regOffset, MV_U16 value); ++ ++MV_STATUS mvPexActiveStateLinkPMEnable(MV_U32 pexIf, MV_BOOL enable); ++ ++#endif /* #ifndef __INCPEXH */ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,751 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCPEXREGSH ++#define __INCPEXREGSH ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++/* defines */ ++#define MAX_PEX_DEVICES 32 ++#define MAX_PEX_FUNCS 8 ++#define MAX_PEX_BUSSES 256 ++ ++ ++ ++/*********************************************************/ ++/* PCI Express Configuration Cycles Generation Registers */ ++/*********************************************************/ ++ ++#define PEX_CFG_ADDR_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x18F8) ++#define PEX_CFG_DATA_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x18FC) ++#define PEX_PHY_ACCESS_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1B00) ++/* PCI Express Configuration Address Register */ ++/* PEX_CFG_ADDR_REG (PXCAR)*/ ++ ++#define PXCAR_REG_NUM_OFFS 2 ++#define PXCAR_REG_NUM_MAX 0x3F ++#define PXCAR_REG_NUM_MASK (PXCAR_REG_NUM_MAX << PXCAR_REG_NUM_OFFS) ++#define PXCAR_FUNC_NUM_OFFS 8 ++#define PXCAR_FUNC_NUM_MAX 0x7 ++#define PXCAR_FUNC_NUM_MASK (PXCAR_FUNC_NUM_MAX << PXCAR_FUNC_NUM_OFFS) ++#define PXCAR_DEVICE_NUM_OFFS 11 ++#define PXCAR_DEVICE_NUM_MAX 0x1F ++#define PXCAR_DEVICE_NUM_MASK (PXCAR_DEVICE_NUM_MAX << PXCAR_DEVICE_NUM_OFFS) ++#define PXCAR_BUS_NUM_OFFS 16 ++#define PXCAR_BUS_NUM_MAX 0xFF ++#define PXCAR_BUS_NUM_MASK (PXCAR_BUS_NUM_MAX << PXCAR_BUS_NUM_OFFS) ++#define PXCAR_EXT_REG_NUM_OFFS 24 ++#define PXCAR_EXT_REG_NUM_MAX 0xF ++ ++/* in pci express register address is now the legacy register address (8 bits) ++with the new extended register address (more 4 bits) , below is the mask of ++the upper 4 bits of the full register address */ ++ ++#define PXCAR_REAL_EXT_REG_NUM_OFFS 8 ++#define PXCAR_EXT_REG_NUM_MASK (PXCAR_EXT_REG_NUM_MAX << PXCAR_EXT_REG_NUM_OFFS) ++#define PXCAR_CONFIG_EN BIT31 ++ ++#define PXCAR_REAL_EXT_REG_NUM_OFFS 8 ++#define PXCAR_REAL_EXT_REG_NUM_MASK (0xF << PXCAR_REAL_EXT_REG_NUM_OFFS) ++ ++/* The traditional PCI spec defined 6-bit field to describe register offset.*/ ++/* The new PCI Express extend the register offset by an extra 4-bits. */ ++/* The below macro assign 10-bit register offset into the apprpreate */ ++/* fields in the CFG_ADDR_REG */ ++#define PXCAR_REG_OFFS_SET(regOffs) \ ++ ( (regOff & PXCAR_REG_NUM_MASK) | \ ++ ( ((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >> PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS) ) ++ ++/***********************************/ ++/* PCI Express Interrupt registers */ ++/***********************************/ ++#define PEX_CAUSE_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1900) ++#define PEX_MASK_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1910) ++ ++#define PXICR_TX_REQ_IN_DLDOWN_ERR BIT0 /* Transmit request while field */ ++ /* of the PCI Express */ ++/* PCI Express Interrupt Cause */ ++/* PEX_INT_CAUSE_REG (PXICR)*/ ++/* PEX_INT_MASK_REG*/ ++/* ++NOTE:All bits except bits[27:24] are Read/Write Clear only. A cause bit sets ++upon an error event occurrence. A write of 0 clears the bit. A write of 1 has ++no affect. Bits[24:27} are set and cleared upon reception of interrupt ++emulation messages. ++ ++Mask bit per cause bit. If a bit is set to 1, the corresponding event is ++enabled. Mask does not affect setting of the Interrupt Cause register bits; ++it only affects the assertion of the interrupt .*/ ++ ++ ++#define PXICR_MDIS_CAUSE BIT1 /* Attempt to generate PCI transaction ++ while master is disabled */ ++#define PXICR_ERR_WRTO_REG_CAUSE BIT3 /* Erroneous write attempt to ++ PCI Express internal register*/ ++#define PXICR_HIT_DFLT_WIN_ERR BIT4 /* Hit Default Window Error */ ++#define PXICR_RX_RAM_PAR_ERR BIT6 /* Rx RAM Parity Error */ ++#define PXICR_TX_RAM_PAR_ERR BIT7 /* Tx RAM Parity Error */ ++#define PXICR_COR_ERR_DET BIT8 /* Correctable Error Detected*/ ++#define PXICR_NF_ERR_DET BIT9 /* Non-Fatal Error Detected*/ ++#define PXICR_FERR_DET BIT10 /* Fatal Error Detected*/ ++#define PXICR_DSTATE_CHANGE BIT11 /* Dstate Change Indication*/ ++#define PXICR_BIST BIT12 /* PCI-Express BIST activated*/ ++#define PXICR_FLW_CTRL_PROT BIT14 /* Flow Control Protocol Error */ ++ ++#define PXICR_RCV_UR_CA_ERR BIT15 /* Received UR or CA status. */ ++#define PXICR_RCV_ERR_FATAL BIT16 /* Received ERR_FATAL message.*/ ++#define PXICR_RCV_ERR_NON_FATAL BIT17 /* Received ERR_NONFATAL message*/ ++#define PXICR_RCV_ERR_COR BIT18 /* Received ERR_COR message.*/ ++#define PXICR_RCV_CRS BIT19 /* Received CRS completion status*/ ++#define PXICR_SLV_HOT_RESET BIT20 /* Received Hot Reset Indication*/ ++#define PXICR_SLV_DIS_LINK BIT21 /* Slave Disable Link Indication*/ ++#define PXICR_SLV_LB BIT22 /* Slave Loopback Indication*/ ++#define PXICR_LINK_FAIL BIT23 /* Link Failure indication.*/ ++#define PXICR_RCV_INTA BIT24 /* IntA status.*/ ++#define PXICR_RCV_INTB BIT25 /* IntB status.*/ ++#define PXICR_RCV_INTC BIT26 /* IntC status.*/ ++#define PXICR_RCV_INTD BIT27 /* IntD status.*/ ++#define PXICR_RCV_PM_PME BIT28 /* Received PM_PME message. */ ++ ++ ++/********************************************/ ++/* PCI Express Control and Status Registers */ ++/********************************************/ ++#define PEX_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A00) ++#define PEX_STATUS_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A04) ++#define PEX_COMPLT_TMEOUT_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A10) ++#define PEX_PWR_MNG_EXT_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A18) ++#define PEX_FLOW_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A20) ++#define PEX_ACK_TMR_4X_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A30) ++#define PEX_ACK_TMR_1X_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A40) ++#define PEX_TL_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1AB0) ++ ++ ++#define PEX_RAM_PARITY_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A50) ++/* PCI Express Control Register */ ++/* PEX_CTRL_REG (PXCR) */ ++ ++#define PXCR_CONF_LINK_OFFS 0 ++#define PXCR_CONF_LINK_MASK (1 << PXCR_CONF_LINK_OFFS) ++#define PXCR_CONF_LINK_X4 (0 << PXCR_CONF_LINK_OFFS) ++#define PXCR_CONF_LINK_X1 (1 << PXCR_CONF_LINK_OFFS) ++#define PXCR_DEV_TYPE_CTRL_OFFS 1 /*PCI ExpressDevice Type Control*/ ++#define PXCR_DEV_TYPE_CTRL_MASK BIT1 ++#define PXCR_DEV_TYPE_CTRL_CMPLX (1 << PXCR_DEV_TYPE_CTRL_OFFS) ++#define PXCR_DEV_TYPE_CTRL_POINT (0 << PXCR_DEV_TYPE_CTRL_OFFS) ++#define PXCR_CFG_MAP_TO_MEM_EN BIT2 /* Configuration Header Mapping ++ to Memory Space Enable */ ++ ++#define PXCR_CFG_MAP_TO_MEM_EN BIT2 /* Configuration Header Mapping ++ to Memory Space Enable*/ ++ ++#define PXCR_RSRV1_OFFS 5 ++#define PXCR_RSRV1_MASK (0x7 << PXCR_RSRV1_OFFS) ++#define PXCR_RSRV1_VAL (0x0 << PXCR_RSRV1_OFFS) ++ ++#define PXCR_CONF_MAX_OUTSTND_OFFS 8 /*Maximum outstanding NP requests as a master*/ ++#define PXCR_CONF_MAX_OUTSTND_MASK (0x3 << PXCR_CONF_MAX_OUTSTND_OFFS) ++ ++ ++#define PXCR_CONF_NFTS_OFFS 16 /*number of FTS Ordered-Sets*/ ++#define PXCR_CONF_NFTS_MASK (0xff << PXCR_CONF_NFTS_OFFS) ++ ++#define PXCR_CONF_MSTR_HOT_RESET BIT24 /*Master Hot-Reset.*/ ++#define PXCR_CONF_MSTR_LB BIT26 /* Master Loopback */ ++#define PXCR_CONF_MSTR_DIS_SCRMB BIT27 /* Master Disable Scrambling*/ ++#define PXCR_CONF_DIRECT_DIS_SCRMB BIT28 /* Direct Disable Scrambling*/ ++ ++/* PCI Express Status Register */ ++/* PEX_STATUS_REG (PXSR) */ ++ ++#define PXSR_DL_DOWN BIT0 /* DL_Down indication.*/ ++ ++#define PXSR_PEX_BUS_NUM_OFFS 8 /* Bus Number Indication */ ++#define PXSR_PEX_BUS_NUM_MASK (0xff << PXSR_PEX_BUS_NUM_OFFS) ++ ++#define PXSR_PEX_DEV_NUM_OFFS 16 /* Device Number Indication */ ++#define PXSR_PEX_DEV_NUM_MASK (0x1f << PXSR_PEX_DEV_NUM_OFFS) ++ ++#define PXSR_PEX_SLV_HOT_RESET BIT24 /* Slave Hot Reset Indication*/ ++#define PXSR_PEX_SLV_DIS_LINK BIT25 /* Slave Disable Link Indication*/ ++#define PXSR_PEX_SLV_LB BIT26 /* Slave Loopback Indication*/ ++#define PXSR_PEX_SLV_DIS_SCRMB BIT27 /* Slave Disable Scrambling Indication*/ ++ ++ ++/* PCI Express Completion Timeout Register */ ++/* PEX_COMPLT_TMEOUT_REG (PXCTR)*/ ++ ++#define PXCTR_CMP_TO_THRSHLD_OFFS 0 /* Completion Timeout Threshold */ ++#define PXCTR_CMP_TO_THRSHLD_MASK (0xffff << PXCTR_CMP_TO_THRSHLD_OFFS) ++ ++/* PCI Express Power Management Extended Register */ ++/* PEX_PWR_MNG_EXT_REG (PXPMER) */ ++ ++#define PXPMER_L1_ASPM_EN_OFFS 1 ++#define PXPMER_L1_ASPM_EN_MASK (0x1 << PXPMER_L1_ASPM_EN_OFFS) ++ ++/* PCI Express Flow Control Register */ ++/* PEX_FLOW_CTRL_REG (PXFCR)*/ ++ ++#define PXFCR_PH_INIT_FC_OFFS 0 /*Posted Headers Flow Control Credit ++ Initial Value.*/ ++#define PXFCR_PH_INIT_FC_MASK (0xff << PXFCR_PH_INIT_FC_OFFS) ++ ++ ++#define PXFCR_NPH_INIT_FC_OFFS 8 /* Classified Non-Posted Headers ++ Flow Control Credit Initial Value*/ ++#define PXFCR_NPH_INIT_FC_MASK (0xff << PXFCR_NPH_INIT_FC_OFFS) ++ ++#define PXFCR_CH_INIT_FC_OFFS 16 /* Completion Headers Flow Control ++ Credit Initial Value Infinite*/ ++ ++#define PXFCR_CH_INIT_FC_MASK (0xff << PXFCR_CH_INIT_FC_OFFS) ++ ++#define PXFCR_FC_UPDATE_TO_OFFS 24 /* Flow Control Update Timeout */ ++#define PXFCR_FC_UPDATE_TO_MASK (0xff << PXFCR_FC_UPDATE_TO_OFFS) ++ ++/* PCI Express Acknowledge Timers (4X) Register */ ++/* PEX_ACK_TMR_4X_REG (PXAT4R) */ ++#define PXAT1R_ACK_LAT_TOX4_OFFS 0 /* Ack Latency Timer Timeout Value */ ++#define PXAT1R_ACK_LAT_TOX4_MASK (0xffff << PXAT4R_ACK_LAT_TOX1_OFFS) ++#define PXAT1R_ACK_RPLY_TOX4_OFFS 16 /* Ack Replay Timer Timeout Value */ ++#define PXAT1R_ACK_RPLY_TOX4_MASK (0xffff << PXAT1R_ACK_RPLY_TOX1_OFFS) ++ ++/* PCI Express Acknowledge Timers (1X) Register */ ++/* PEX_ACK_TMR_1X_REG (PXAT1R) */ ++ ++#define PXAT1R_ACK_LAT_TOX1_OFFS 0 /* Acknowledge Latency Timer Timeout ++ Value for 1X Link*/ ++#define PXAT1R_ACK_LAT_TOX1_MASK (0xffff << PXAT1R_ACK_LAT_TOX1_OFFS) ++ ++#define PXAT1R_ACK_RPLY_TOX1_OFFS 16 /* Acknowledge Replay Timer Timeout ++ Value for 1X*/ ++#define PXAT1R_ACK_RPLY_TOX1_MASK (0xffff << PXAT1R_ACK_RPLY_TOX1_OFFS) ++ ++ ++/* PCI Express TL Control Register */ ++/* PEX_TL_CTRL_REG (PXTCR) */ ++ ++#define PXTCR_TX_CMP_BUFF_NO_OFFS 8 /*Number of completion buffers in Tx*/ ++#define PXTCR_TX_CMP_BUFF_NO_MASK (0xf << PXTCR_TX_CMP_BUFF_NO_OFFS) ++ ++/* PCI Express Debug MAC Control Register */ ++/* PEX_DEBUG_MAC_CTRL_REG (PXDMCR) */ ++ ++#define PXDMCR_LINKUP BIT4 ++ ++ ++ ++/**********************************************/ ++/* PCI Express Configuration Header Registers */ ++/**********************************************/ ++#define PEX_CFG_DIRECT_ACCESS(pexIf,cfgReg) ((PEX_IF_BASE(pexIf)) + (cfgReg)) ++ ++#define PEX_DEVICE_AND_VENDOR_ID 0x000 ++#define PEX_STATUS_AND_COMMAND 0x004 ++#define PEX_CLASS_CODE_AND_REVISION_ID 0x008 ++#define PEX_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE 0x00C ++#define PEX_MEMORY_BAR_BASE_ADDR(barNum) (0x010 + ((barNum) << 2)) ++#define PEX_MV_BAR_BASE(barNum) (0x010 + (barNum) * 8) ++#define PEX_MV_BAR_BASE_HIGH(barNum) (0x014 + (barNum) * 8) ++#define PEX_BAR0_INTER_REG 0x010 ++#define PEX_BAR0_INTER_REG_HIGH 0x014 ++#define PEX_BAR1_REG 0x018 ++#define PEX_BAR1_REG_HIGH 0x01C ++#define PEX_BAR2_REG 0x020 ++#define PEX_BAR2_REG_HIGH 0x024 ++ ++#define PEX_SUBSYS_ID_AND_SUBSYS_VENDOR_ID 0x02C ++#define PEX_EXPANSION_ROM_BASE_ADDR_REG 0x030 ++#define PEX_CAPABILTY_LIST_POINTER 0x034 ++#define PEX_INTERRUPT_PIN_AND_LINE 0x03C ++ ++/* capability list */ ++#define PEX_POWER_MNG_CAPABILITY 0x040 ++#define PEX_POWER_MNG_STATUS_CONTROL 0x044 ++ ++#define PEX_MSI_MESSAGE_CONTROL 0x050 ++#define PEX_MSI_MESSAGE_ADDR 0x054 ++#define PEX_MSI_MESSAGE_HIGH_ADDR 0x058 ++#define PEX_MSI_MESSAGE_DATA 0x05C ++ ++#define PEX_CAPABILITY_REG 0x60 ++#define PEX_DEV_CAPABILITY_REG 0x64 ++#define PEX_DEV_CTRL_STAT_REG 0x68 ++#define PEX_LINK_CAPABILITY_REG 0x6C ++#define PEX_LINK_CTRL_STAT_REG 0x70 ++ ++#define PEX_ADV_ERR_RPRT_HDR_TRGT_REG 0x100 ++#define PEX_UNCORRECT_ERR_STAT_REG 0x104 ++#define PEX_UNCORRECT_ERR_MASK_REG 0x108 ++#define PEX_UNCORRECT_ERR_SERVITY_REG 0x10C ++#define PEX_CORRECT_ERR_STAT_REG 0x110 ++#define PEX_CORRECT_ERR_MASK_REG 0x114 ++#define PEX_ADV_ERR_CAPABILITY_CTRL_REG 0x118 ++#define PEX_HDR_LOG_FIRST_DWORD_REG 0x11C ++#define PEX_HDR_LOG_SECOND_DWORD_REG 0x120 ++#define PEX_HDR_LOG_THIRD_DWORD_REG 0x124 ++#define PEX_HDR_LOG_FOURTH_DWORD_REG 0x128 ++ ++ ++ ++/* PCI Express Device and Vendor ID Register*/ ++/*PEX_DEVICE_AND_VENDOR_ID (PXDAVI)*/ ++ ++#define PXDAVI_VEN_ID_OFFS 0 /* Vendor ID */ ++#define PXDAVI_VEN_ID_MASK (0xffff << PXDAVI_VEN_ID_OFFS) ++ ++#define PXDAVI_DEV_ID_OFFS 16 /* Device ID */ ++#define PXDAVI_DEV_ID_MASK (0xffff << PXDAVI_DEV_ID_OFFS) ++ ++ ++/* PCI Express Command and Status Register*/ ++/*PEX_STATUS_AND_COMMAND (PXSAC)*/ ++ ++#define PXSAC_IO_EN BIT0 /* IO Enable */ ++#define PXSAC_MEM_EN BIT1 /* Memory Enable */ ++#define PXSAC_MASTER_EN BIT2 /* Master Enable */ ++#define PXSAC_PERR_EN BIT6 /* Parity Errors Respond Enable */ ++#define PXSAC_SERR_EN BIT8 /* Ability to assert SERR# line */ ++#define PXSAC_INT_DIS BIT10 /* Interrupt Disable */ ++#define PXSAC_INT_STAT BIT19 /* Interrupt Status */ ++#define PXSAC_CAP_LIST BIT20 /* Capability List Support */ ++#define PXSAC_MAS_DATA_PERR BIT24 /* Master Data Parity Error */ ++#define PXSAC_SLAVE_TABORT BIT27 /* Signalled Target Abort */ ++#define PXSAC_RT_ABORT BIT28 /* Recieved Target Abort */ ++#define PXSAC_MABORT BIT29 /* Recieved Master Abort */ ++#define PXSAC_SYSERR BIT30 /* Signalled system error */ ++#define PXSAC_DET_PARERR BIT31 /* Detect Parity Error */ ++ ++ ++/* PCI Express Class Code and Revision ID Register*/ ++/*PEX_CLASS_CODE_AND_REVISION_ID (PXCCARI)*/ ++ ++#define PXCCARI_REVID_OFFS 0 /* Revision ID */ ++#define PXCCARI_REVID_MASK (0xff << PXCCARI_REVID_OFFS) ++ ++#define PXCCARI_FULL_CLASS_OFFS 8 /* Full Class Code */ ++#define PXCCARI_FULL_CLASS_MASK (0xffffff << PXCCARI_FULL_CLASS_OFFS) ++ ++#define PXCCARI_PROGIF_OFFS 8 /* Prog .I/F*/ ++#define PXCCARI_PROGIF_MASK (0xff << PXCCARI_PROGIF_OFFS) ++ ++#define PXCCARI_SUB_CLASS_OFFS 16 /* Sub Class*/ ++#define PXCCARI_SUB_CLASS_MASK (0xff << PXCCARI_SUB_CLASS_OFFS) ++ ++#define PXCCARI_BASE_CLASS_OFFS 24 /* Base Class*/ ++#define PXCCARI_BASE_CLASS_MASK (0xff << PXCCARI_BASE_CLASS_OFFS) ++ ++ ++/* PCI Express BIST, Header Type and Cache Line Size Register*/ ++/*PEX_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE (PXBHTLTCL)*/ ++ ++#define PXBHTLTCL_CACHELINE_OFFS 0 /* Specifies the cache line size */ ++#define PXBHTLTCL_CACHELINE_MASK (0xff << PXBHTLTCL_CACHELINE_OFFS) ++ ++#define PXBHTLTCL_HEADTYPE_FULL_OFFS 16 /* Full Header Type */ ++#define PXBHTLTCL_HEADTYPE_FULL_MASK (0xff << PXBHTLTCL_HEADTYPE_FULL_OFFS) ++ ++#define PXBHTLTCL_MULTI_FUNC BIT23 /* Multi/Single function */ ++ ++#define PXBHTLTCL_HEADER_OFFS 16 /* Header type */ ++#define PXBHTLTCL_HEADER_MASK (0x7f << PXBHTLTCL_HEADER_OFFS) ++#define PXBHTLTCL_HEADER_STANDARD (0x0 << PXBHTLTCL_HEADER_OFFS) ++#define PXBHTLTCL_HEADER_PCI2PCI_BRIDGE (0x1 << PXBHTLTCL_HEADER_OFFS) ++ ++ ++#define PXBHTLTCL_BISTCOMP_OFFS 24 /* BIST Completion Code */ ++#define PXBHTLTCL_BISTCOMP_MASK (0xf << PXBHTLTCL_BISTCOMP_OFFS) ++ ++#define PXBHTLTCL_BISTACT BIT30 /* BIST Activate bit */ ++#define PXBHTLTCL_BISTCAP BIT31 /* BIST Capable Bit */ ++#define PXBHTLTCL_BISTCAP_OFFS 31 ++#define PXBHTLTCL_BISTCAP_MASK BIT31 ++#define PXBHTLTCL_BISTCAP_VAL 0 ++ ++ ++/* PCI Express Subsystem Device and Vendor ID */ ++/*PEX_SUBSYS_ID_AND_SUBSYS_VENDOR_ID (PXSIASVI)*/ ++ ++#define PXSIASVI_VENID_OFFS 0 /* Subsystem Manufacturer Vendor ID Number */ ++#define PXSIASVI_VENID_MASK (0xffff << PXSIASVI_VENID_OFFS) ++ ++#define PXSIASVI_DEVID_OFFS 16 /* Subsystem Device ID Number */ ++#define PXSIASVI_DEVID_MASK (0xffff << PXSIASVI_DEVID_OFFS) ++ ++ ++/* PCI Express Capability List Pointer Register*/ ++/*PEX_CAPABILTY_LIST_POINTER (PXCLP)*/ ++ ++#define PXCLP_CAPPTR_OFFS 0 /* Capability List Pointer */ ++#define PXCLP_CAPPTR_MASK (0xff << PXCLP_CAPPTR_OFFS) ++ ++/* PCI Express Interrupt Pin and Line Register */ ++/*PEX_INTERRUPT_PIN_AND_LINE (PXIPAL)*/ ++ ++#define PXIPAL_INTLINE_OFFS 0 /* Interrupt line (IRQ) */ ++#define PXIPAL_INTLINE_MASK (0xff << PXIPAL_INTLINE_OFFS) ++ ++#define PXIPAL_INTPIN_OFFS 8 /* interrupt pin (A,B,C,D) */ ++#define PXIPAL_INTPIN_MASK (0xff << PXIPAL_INTPIN_OFFS) ++ ++ ++/* PCI Express Power Management Capability Header Register*/ ++/*PEX_POWER_MNG_CAPABILITY (PXPMC)*/ ++ ++#define PXPMC_CAP_ID_OFFS 0 /* Capability ID */ ++#define PXPMC_CAP_ID_MASK (0xff << PXPMC_CAP_ID_OFFS) ++ ++#define PXPMC_NEXT_PTR_OFFS 8 /* Next Item Pointer */ ++#define PXPMC_NEXT_PTR_MASK (0xff << PXPMC_NEXT_PTR_OFFS) ++ ++#define PXPMC_PMC_VER_OFFS 16 /* PCI Power Management Capability Version*/ ++#define PXPMC_PMC_VER_MASK (0x7 << PXPMC_PMC_VER_OFFS) ++ ++#define PXPMC_DSI BIT21/* Device Specific Initialization */ ++ ++#define PXPMC_AUX_CUR_OFFS 22 /* Auxiliary Current Requirements */ ++#define PXPMC_AUX_CUR_MASK (0x7 << PXPMC_AUX_CUR_OFFS) ++ ++#define PXPMC_D1_SUP BIT25 /* D1 Power Management support*/ ++ ++#define PXPMC_D2_SUP BIT26 /* D2 Power Management support*/ ++ ++#define PXPMC_PME_SUP_OFFS 27 /* PM Event generation support*/ ++#define PXPMC_PME_SUP_MASK (0x1f << PXPMC_PME_SUP_OFFS) ++ ++/* PCI Express Power Management Control and Status Register*/ ++/*PEX_POWER_MNG_STATUS_CONTROL (PXPMSC)*/ ++ ++#define PXPMSC_PM_STATE_OFFS 0 /* Power State */ ++#define PXPMSC_PM_STATE_MASK (0x3 << PXPMSC_PM_STATE_OFFS) ++#define PXPMSC_PM_STATE_D0 (0x0 << PXPMSC_PM_STATE_OFFS) ++#define PXPMSC_PM_STATE_D1 (0x1 << PXPMSC_PM_STATE_OFFS) ++#define PXPMSC_PM_STATE_D2 (0x2 << PXPMSC_PM_STATE_OFFS) ++#define PXPMSC_PM_STATE_D3 (0x3 << PXPMSC_PM_STATE_OFFS) ++ ++#define PXPMSC_PME_EN BIT8/* PM_PME Message Generation Enable */ ++ ++#define PXPMSC_PM_DATA_SEL_OFFS 9 /* Data Select*/ ++#define PXPMSC_PM_DATA_SEL_MASK (0xf << PXPMSC_PM_DATA_SEL_OFFS) ++ ++#define PXPMSC_PM_DATA_SCALE_OFFS 13 /* Data Scale */ ++#define PXPMSC_PM_DATA_SCALE_MASK (0x3 << PXPMSC_PM_DATA_SCALE_OFFS) ++ ++#define PXPMSC_PME_STAT BIT15/* PME Status */ ++ ++#define PXPMSC_PM_DATA_OFFS 24 /* State Data */ ++#define PXPMSC_PM_DATA_MASK (0xff << PXPMSC_PM_DATA_OFFS) ++ ++ ++/* PCI Express MSI Message Control Register*/ ++/*PEX_MSI_MESSAGE_CONTROL (PXMMC)*/ ++ ++#define PXMMC_CAP_ID_OFFS 0 /* Capability ID */ ++#define PXMMC_CAP_ID_MASK (0xff << PXMMC_CAP_ID_OFFS) ++ ++#define PXMMC_NEXT_PTR_OFFS 8 /* Next Item Pointer */ ++#define PXMMC_NEXT_PTR_MASK (0xff << PXMMC_NEXT_PTR_OFFS) ++ ++#define PXMMC_MSI_EN BIT18 /* MSI Enable */ ++ ++#define PXMMC_MULTI_CAP_OFFS 17 /* Multiple Message Capable */ ++#define PXMMC_MULTI_CAP_MASK (0x7 << PXMMC_MULTI_CAP_OFFS) ++ ++#define PXMMC_MULTI_EN_OFFS 20 /* Multiple Messages Enable */ ++#define PXMMC_MULTI_EN_MASK (0x7 << PXMMC_MULTI_EN_OFFS) ++ ++#define PXMMC_ADDR64 BIT23 /* 64-bit Addressing Capable */ ++ ++ ++/* PCI Express MSI Message Address Register*/ ++/*PEX_MSI_MESSAGE_ADDR (PXMMA)*/ ++ ++#define PXMMA_MSI_ADDR_OFFS 2 /* Message Address corresponds to ++ Address[31:2] of the MSI MWr TLP*/ ++#define PXMMA_MSI_ADDR_MASK (0x3fffffff << PXMMA_MSI_ADDR_OFFS) ++ ++ ++/* PCI Express MSI Message Address (High) Register */ ++/*PEX_MSI_MESSAGE_HIGH_ADDR (PXMMHA)*/ ++ ++#define PXMMA_MSI_ADDR_H_OFFS 0 /* Message Upper Address corresponds to ++ Address[63:32] of the MSI MWr TLP*/ ++#define PXMMA_MSI_ADDR_H_MASK (0xffffffff << PXMMA_MSI_ADDR_H_OFFS ) ++ ++ ++/* PCI Express MSI Message Data Register*/ ++/*PEX_MSI_MESSAGE_DATA (PXMMD)*/ ++ ++#define PXMMD_MSI_DATA_OFFS 0 /* Message Data */ ++#define PXMMD_MSI_DATA_MASK (0xffff << PXMMD_MSI_DATA_OFFS ) ++ ++ ++/* PCI Express Capability Register*/ ++/*PEX_CAPABILITY_REG (PXCR)*/ ++ ++#define PXCR_CAP_ID_OFFS 0 /* Capability ID*/ ++#define PXCR_CAP_ID_MASK (0xff << PXCR_CAP_ID_OFFS) ++ ++#define PXCR_NEXT_PTR_OFFS 8 /* Next Item Pointer*/ ++#define PXCR_NEXT_PTR_MASK (0xff << PXCR_NEXT_PTR_OFFS) ++ ++#define PXCR_CAP_VER_OFFS 16 /* Capability Version*/ ++#define PXCR_CAP_VER_MASK (0xf << PXCR_CAP_VER_OFFS) ++ ++#define PXCR_DEV_TYPE_OFFS 20 /* Device/Port Type*/ ++#define PXCR_DEV_TYPE_MASK (0xf << PXCR_DEV_TYPE_OFFS) ++ ++#define PXCR_SLOT_IMP BIT24 /* Slot Implemented*/ ++ ++#define PXCR_INT_MSG_NUM_OFFS 25 /* Interrupt Message Number*/ ++#define PXCR_INT_MSG_NUM_MASK (0x1f << PXCR_INT_MSG_NUM_OFFS) ++ ++ ++/* PCI Express Device Capabilities Register */ ++/*PEX_DEV_CAPABILITY_REG (PXDCR)*/ ++ ++#define PXDCR_MAX_PLD_SIZE_SUP_OFFS 0 /* Maximum Payload Size Supported*/ ++#define PXDCR_MAX_PLD_SIZE_SUP_MASK (0x7 << PXDCR_MAX_PLD_SIZE_SUP_OFFS) ++ ++#define PXDCR_EP_L0S_ACC_LAT_OFFS 6/* Endpoint L0s Acceptable Latency*/ ++#define PXDCR_EP_L0S_ACC_LAT_MASK (0x7 << PXDCR_EP_L0S_ACC_LAT_OFFS) ++#define PXDCR_EP_L0S_ACC_LAT_64NS_LESS (0x0 << PXDCR_EP_L0S_ACC_LAT_OFFS) ++#define PXDCR_EP_L0S_ACC_LAT_64NS_128NS (0x1 << PXDCR_EP_L0S_ACC_LAT_OFFS) ++#define PXDCR_EP_L0S_ACC_LAT_128NS_256NS (0x2 << PXDCR_EP_L0S_ACC_LAT_OFFS) ++#define PXDCR_EP_L0S_ACC_LAT_256NS_512NS (0x3 << PXDCR_EP_L0S_ACC_LAT_OFFS) ++#define PXDCR_EP_L0S_ACC_LAT_512NS_1US (0x4 << PXDCR_EP_L0S_ACC_LAT_OFFS) ++#define PXDCR_EP_L0S_ACC_LAT_1US_2US (0x5 << PXDCR_EP_L0S_ACC_LAT_OFFS) ++#define PXDCR_EP_L0S_ACC_LAT_2US_4US (0x6 << PXDCR_EP_L0S_ACC_LAT_OFFS) ++#define PXDCR_EP_L0S_ACC_LAT_4US_MORE (0x7 << PXDCR_EP_L0S_ACC_LAT_OFFS) ++ ++#define PXDCR_EP_L1_ACC_LAT_OFFS 9 /* Endpoint L1 Acceptable Latency*/ ++#define PXDCR_EP_L1_ACC_LAT_MASK (0x7 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXDCR_EP_L1_ACC_LAT_64NS_LESS (0x0 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXDCR_EP_L1_ACC_LAT_64NS_128NS (0x1 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXDCR_EP_L1_ACC_LAT_128NS_256NS (0x2 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXDCR_EP_L1_ACC_LAT_256NS_512NS (0x3 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXDCR_EP_L1_ACC_LAT_512NS_1US (0x4 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXDCR_EP_L1_ACC_LAT_1US_2US (0x5 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXDCR_EP_L1_ACC_LAT_2US_4US (0x6 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXDCR_EP_L1_ACC_LAT_4US_MORE (0x7 << PXDCR_EP_L1_ACC_LAT_OFFS) ++ ++ ++#define PXDCR_ATT_BUT_PRS_OFFS 12 /* Attention Button Present*/ ++#define PXDCR_ATT_BUT_PRS_MASK BIT12 ++#define PXDCR_ATT_BUT_PRS_IMPLEMENTED BIT12 ++ ++#define PXDCR_ATT_IND_PRS_OFFS 13 /* Attention Indicator Present*/ ++#define PXDCR_ATT_IND_PRS_MASK BIT13 ++#define PXDCR_ATT_IND_PRS_IMPLEMENTED BIT13 ++ ++#define PXDCR_PWR_IND_PRS_OFFS 14/* Power Indicator Present*/ ++#define PXDCR_PWR_IND_PRS_MASK BIT14 ++#define PXDCR_PWR_IND_PRS_IMPLEMENTED BIT14 ++ ++#define PXDCR_CAP_SPL_VAL_OFFS 18 /*Captured Slot Power Limit ++ Value*/ ++#define PXDCR_CAP_SPL_VAL_MASK (0xff << PXDCR_CAP_SPL_VAL_OFFS) ++ ++#define PXDCR_CAP_SP_LSCL_OFFS 26 /* Captured Slot Power Limit ++ Scale */ ++#define PXDCR_CAP_SP_LSCL_MASK (0x3 << PXDCR_CAP_SP_LSCL_OFFS) ++ ++/* PCI Express Device Control Status Register */ ++/*PEX_DEV_CTRL_STAT_REG (PXDCSR)*/ ++ ++#define PXDCSR_COR_ERR_REP_EN BIT0 /* Correctable Error Reporting Enable*/ ++#define PXDCSR_NF_ERR_REP_EN BIT1 /* Non-Fatal Error Reporting Enable*/ ++#define PXDCSR_F_ERR_REP_EN BIT2 /* Fatal Error Reporting Enable*/ ++#define PXDCSR_UR_REP_EN BIT3 /* Unsupported Request (UR) ++ Reporting Enable*/ ++#define PXDCSR_EN_RO BIT4 /* Enable Relaxed Ordering*/ ++ ++#define PXDCSR_MAX_PLD_SZ_OFFS 5 /* Maximum Payload Size*/ ++#define PXDCSR_MAX_PLD_SZ_MASK (0x7 << PXDCSR_MAX_PLD_SZ_OFFS) ++#define PXDCSR_MAX_PLD_SZ_128B (0x0 << PXDCSR_MAX_PLD_SZ_OFFS) ++#define PXDCSR_EN_NS BIT11 /* Enable No Snoop*/ ++ ++#define PXDCSR_MAX_RD_RQ_SZ_OFFS 12 /* Maximum Read Request Size*/ ++#define PXDCSR_MAX_RD_RQ_SZ_MASK (0x7 << PXDCSR_MAX_RD_RQ_SZ_OFFS) ++#define PXDCSR_MAX_RD_RQ_SZ_128B (0x0 << PXDCSR_MAX_RD_RQ_SZ_OFFS) ++#define PXDCSR_MAX_RD_RQ_SZ_256B (0x1 << PXDCSR_MAX_RD_RQ_SZ_OFFS) ++#define PXDCSR_MAX_RD_RQ_SZ_512B (0x2 << PXDCSR_MAX_RD_RQ_SZ_OFFS) ++#define PXDCSR_MAX_RD_RQ_SZ_1KB (0x3 << PXDCSR_MAX_RD_RQ_SZ_OFFS) ++#define PXDCSR_MAX_RD_RQ_SZ_2KB (0x4 << PXDCSR_MAX_RD_RQ_SZ_OFFS) ++#define PXDCSR_MAX_RD_RQ_SZ_4KB (0x5 << PXDCSR_MAX_RD_RQ_SZ_OFFS) ++ ++#define PXDCSR_COR_ERR_DET BIT16 /* Correctable Error Detected*/ ++#define PXDCSR_NF_ERR_DET BIT17 /* Non-Fatal Error Detected.*/ ++#define PXDCSR_F_ERR_DET BIT18 /* Fatal Error Detected.*/ ++#define PXDCSR_UR_DET BIT19 /* Unsupported Request Detected */ ++#define PXDCSR_AUX_PWR_DET BIT20 /* Reserved*/ ++ ++#define PXDCSR_TRANS_PEND_OFFS 21 /* Transactions Pending*/ ++#define PXDCSR_TRANS_PEND_MASK BIT21 ++#define PXDCSR_TRANS_PEND_NOT_COMPLETED (0x1 << PXDCSR_TRANS_PEND_OFFS) ++ ++ ++/* PCI Express Link Capabilities Register*/ ++/*PEX_LINK_CAPABILITY_REG (PXLCR)*/ ++ ++#define PXLCR_MAX_LINK_SPD_OFFS 0 /* Maximum Link Speed*/ ++#define PXLCR_MAX_LINK_SPD_MASK (0xf << PXLCR_MAX_LINK_SPD_OFFS) ++ ++#define PXLCR_MAX_LNK_WDTH_OFFS 3 /* Maximum Link Width*/ ++#define PXLCR_MAX_LNK_WDTH_MASK (0x3f << PXLCR_MAX_LNK_WDTH_OFFS) ++ ++#define PXLCR_ASPM_SUP_OFFS 10 /* Active State Link PM Support*/ ++#define PXLCR_ASPM_SUP_MASK (0x3 << PXLCR_ASPM_SUP_OFFS) ++ ++#define PXLCR_L0S_EXT_LAT_OFFS 12 /* L0s Exit Latency*/ ++#define PXLCR_L0S_EXT_LAT_MASK (0x7 << PXLCR_L0S_EXT_LAT_OFFS) ++#define PXLCR_L0S_EXT_LAT_64NS_LESS (0x0 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXLCR_L0S_EXT_LAT_64NS_128NS (0x1 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXLCR_L0S_EXT_LAT_128NS_256NS (0x2 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXLCR_L0S_EXT_LAT_256NS_512NS (0x3 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXLCR_L0S_EXT_LAT_512NS_1US (0x4 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXLCR_L0S_EXT_LAT_1US_2US (0x5 << PXDCR_EP_L1_ACC_LAT_OFFS) ++#define PXLCR_L0S_EXT_LAT_2US_4US (0x6 << PXDCR_EP_L1_ACC_LAT_OFFS) ++ ++#define PXLCR_POR_TNUM_OFFS 24 /* Port Number */ ++#define PXLCR_POR_TNUM_MASK (0xff << PXLCR_POR_TNUM_OFFS) ++ ++/* PCI Express Link Control Status Register */ ++/*PEX_LINK_CTRL_STAT_REG (PXLCSR)*/ ++ ++#define PXLCSR_ASPM_CNT_OFFS 0 /* Active State Link PM Control */ ++#define PXLCSR_ASPM_CNT_MASK (0x3 << PXLCSR_ASPM_CNT_OFFS) ++#define PXLCSR_ASPM_CNT_DISABLED (0x0 << PXLCSR_ASPM_CNT_OFFS) ++#define PXLCSR_ASPM_CNT_L0S_ENT_SUPP (0x1 << PXLCSR_ASPM_CNT_OFFS) ++#define PXLCSR_ASPM_CNT_L1S_ENT_SUPP (0x2 << PXLCSR_ASPM_CNT_OFFS) ++#define PXLCSR_ASPM_CNT_L0S_L1S_ENT_SUPP (0x3 << PXLCSR_ASPM_CNT_OFFS) ++ ++#define PXLCSR_RCB_OFFS 3 /* Read Completion Boundary */ ++#define PXLCSR_RCB_MASK BIT3 ++#define PXLCSR_RCB_64B (0 << PXLCSR_RCB_OFFS) ++#define PXLCSR_RCB_128B (1 << PXLCSR_RCB_OFFS) ++ ++#define PXLCSR_LNK_DIS BIT4 /* Link Disable */ ++#define PXLCSR_RETRN_LNK BIT5 /* Retrain Link */ ++#define PXLCSR_CMN_CLK_CFG BIT6 /* Common Clock Configuration */ ++#define PXLCSR_EXTD_SNC BIT7 /* Extended Sync */ ++ ++#define PXLCSR_LNK_SPD_OFFS 16 /* Link Speed */ ++#define PXLCSR_LNK_SPD_MASK (0xf << PXLCSR_LNK_SPD_OFFS) ++ ++#define PXLCSR_NEG_LNK_WDTH_OFFS 20 /* Negotiated Link Width */ ++#define PXLCSR_NEG_LNK_WDTH_MASK (0x3f << PXLCSR_NEG_LNK_WDTH_OFFS) ++#define PXLCSR_NEG_LNK_WDTH_X1 (0x1 << PXLCSR_NEG_LNK_WDTH_OFFS) ++ ++#define PXLCSR_LNK_TRN BIT27 /* Link Training */ ++ ++#define PXLCSR_SLT_CLK_CFG_OFFS 28 /* Slot Clock Configuration */ ++#define PXLCSR_SLT_CLK_CFG_MASK BIT28 ++#define PXLCSR_SLT_CLK_CFG_INDPNT (0x0 << PXLCSR_SLT_CLK_CFG_OFFS) ++#define PXLCSR_SLT_CLK_CFG_REF (0x1 << PXLCSR_SLT_CLK_CFG_OFFS) ++ ++/* PCI Express Advanced Error Report Header Register */ ++/*PEX_ADV_ERR_RPRT_HDR_TRGT_REG (PXAERHTR)*/ ++ ++/* PCI Express Uncorrectable Error Status Register*/ ++/*PEX_UNCORRECT_ERR_STAT_REG (PXUESR)*/ ++ ++/* PCI Express Uncorrectable Error Mask Register */ ++/*PEX_UNCORRECT_ERR_MASK_REG (PXUEMR)*/ ++ ++/* PCI Express Uncorrectable Error Severity Register */ ++/*PEX_UNCORRECT_ERR_SERVITY_REG (PXUESR)*/ ++ ++/* PCI Express Correctable Error Status Register */ ++/*PEX_CORRECT_ERR_STAT_REG (PXCESR)*/ ++ ++/* PCI Express Correctable Error Mask Register */ ++/*PEX_CORRECT_ERR_MASK_REG (PXCEMR)*/ ++ ++/* PCI Express Advanced Error Capability and Control Register*/ ++/*PEX_ADV_ERR_CAPABILITY_CTRL_REG (PXAECCR)*/ ++ ++/* PCI Express Header Log First DWORD Register*/ ++/*PEX_HDR_LOG_FIRST_DWORD_REG (PXHLFDR)*/ ++ ++/* PCI Express Header Log Second DWORD Register*/ ++/*PEX_HDR_LOG_SECOND_DWORD_REG (PXHLSDR)*/ ++ ++/* PCI Express Header Log Third DWORD Register*/ ++/*PEX_HDR_LOG_THIRD_DWORD_REG (PXHLTDR)*/ ++ ++/* PCI Express Header Log Fourth DWORD Register*/ ++/*PEX_HDR_LOG_FOURTH_DWORD_REG (PXHLFDR)*/ ++ ++#ifdef __cplusplus ++} ++#endif /* __cplusplus */ ++ ++#endif /* #ifndef __INCPEXREGSH */ ++ ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,313 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#include "mvPex.h" ++ ++//#define MV_DEBUG ++/* defines */ ++#ifdef MV_DEBUG ++ #define DB(x) x ++#else ++ #define DB(x) ++#endif ++ ++/* locals */ ++typedef struct ++{ ++ MV_U32 data; ++ MV_U32 mask; ++}PEX_HEADER_DATA; ++ ++/* local function forwad decleration */ ++MV_U32 mvPexHwConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, ++ MV_U32 regOff); ++MV_STATUS mvPexHwConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func, MV_U32 regOff, MV_U32 data); ++void resetPexConfig(MV_U32 pexIf, MV_U32 bus, MV_U32 dev); ++ ++ ++PEX_HEADER_DATA configHdr[16] = ++{ ++{0x888811ab, 0x00000000}, /*[device ID, vendor ID] */ ++{0x00100007, 0x0000ffff}, /*[status register, command register] */ ++{0x0604000e, 0x00000000}, /*[programming interface, sub class code, class code, revision ID] */ ++{0x00010008, 0x00000000}, /*[BIST, header type, latency time, cache line] */ ++{0x00000000, 0x00000000}, /*[base address 0] */ ++{0x00000000, 0x00000000}, /*[base address 1] */ ++{0x00000000, 0x00ffffff}, /*[secondary latency timersubordinate bus number, secondary bus number, primary bus number] */ ++{0x0000f101, 0x00000000}, /*[secondary status ,IO limit, IO base] */ ++{0x9ff0a000, 0x00000000}, /*[memory limit, memory base] */ ++{0x0001fff1, 0x00000000}, /*[prefetch memory limit, prefetch memory base] */ ++{0xffffffff, 0x00000000}, /*[prefetch memory base upper] */ ++{0x00000000, 0x00000000}, /*[prefetch memory limit upper] */ ++{0xeffff000, 0x00000000}, /*[IO limit upper 16 bits, IO base upper 16 bits] */ ++{0x00000000, 0x00000000}, /*[reserved, capability pointer] */ ++{0x00000000, 0x00000000}, /*[expansion ROM base address] */ ++{0x00000000, 0x000000FF}, /*[bridge control, interrupt pin, interrupt line] */ ++}; ++ ++ ++#define HEADER_WRITE(data, offset) configHdr[offset/4].data = ((configHdr[offset/4].data & ~configHdr[offset/4].mask) | \ ++ (data & configHdr[offset/4].mask)) ++#define HEADER_READ(offset) configHdr[offset/4].data ++ ++/******************************************************************************* ++* mvVrtBrgPexInit - Initialize PEX interfaces ++* ++* DESCRIPTION: ++* ++* This function is responsible of intialization of the Pex Interface , It ++* configure the Pex Bars and Windows in the following manner: ++* ++* Assumptions : ++* Bar0 is always internal registers bar ++* Bar1 is always the DRAM bar ++* Bar2 is always the Device bar ++* ++* 1) Sets the Internal registers bar base by obtaining the base from ++* the CPU Interface ++* 2) Sets the DRAM bar base and size by getting the base and size from ++* the CPU Interface when the size is the sum of all enabled DRAM ++* chip selects and the base is the base of CS0 . ++* 3) Sets the Device bar base and size by getting these values from the ++* CPU Interface when the base is the base of the lowest base of the ++* Device chip selects, and the ++* ++* ++* INPUT: ++* ++* pexIf - PEX interface number. ++* ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_OK if function success otherwise MV_ERROR or MV_BAD_PARAM ++* ++*******************************************************************************/ ++MV_STATUS mvPexVrtBrgInit(MV_U32 pexIf) ++{ ++ /* reset PEX tree to recover previous U-boot/Boot configurations */ ++ MV_U32 localBus = mvPexLocalBusNumGet(pexIf); ++ ++ ++ resetPexConfig(pexIf, localBus, 1); ++ return MV_OK; ++} ++ ++ ++MV_U32 mvPexVrtBrgConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, ++ MV_U32 regOff) ++{ ++ ++ MV_U32 localBus = mvPexLocalBusNumGet(pexIf); ++ MV_U32 localDev = mvPexLocalDevNumGet(pexIf); ++ MV_U32 val; ++ if(bus == localBus) ++ { ++ if(dev > 1) ++ { ++/* on the local device allow only device #0 & #1 */ ++ return 0xffffffff; ++ } ++ else ++ if (dev == localDev) ++ { ++ /* read the memory controller registers */ ++ return mvPexHwConfigRead (pexIf, bus, dev, func, regOff); ++ } ++ else ++ { ++ /* access the virtual brg header */ ++ return HEADER_READ(regOff); ++ } ++ } ++ else ++ if(bus == (localBus + 1)) ++ { ++ /* access the device behind the virtual bridge */ ++ if((dev == localDev) || (dev > 1)) ++ { ++ return 0xffffffff; ++ } ++ else ++ { ++ /* access the device behind the virtual bridge, in this case ++ * change the bus number to the local bus number in order to ++ * generate type 0 config cycle ++ */ ++ mvPexLocalBusNumSet(pexIf, bus); ++ mvPexLocalDevNumSet(pexIf, 1); ++ val = mvPexHwConfigRead (pexIf, bus, 0, func, regOff); ++ mvPexLocalBusNumSet(pexIf, localBus); ++ mvPexLocalDevNumSet(pexIf, localDev); ++ return val; ++ } ++ } ++ /* for all other devices use the HW function to get the ++ * requested registers ++ */ ++ mvPexLocalDevNumSet(pexIf, 1); ++ val = mvPexHwConfigRead (pexIf, bus, dev, func, regOff); ++ mvPexLocalDevNumSet(pexIf, localDev); ++ return val; ++} ++ ++ ++MV_STATUS mvPexVrtBrgConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func, MV_U32 regOff, MV_U32 data) ++{ ++ MV_U32 localBus = mvPexLocalBusNumGet(pexIf); ++ MV_U32 localDev = mvPexLocalDevNumGet(pexIf); ++ MV_STATUS status; ++ ++ if(bus == localBus) ++ { ++ if(dev > 1) ++ { ++ /* on the local device allow only device #0 & #1 */ ++ return MV_ERROR; ++ } ++ else ++ if (dev == localDev) ++ { ++ /* read the memory controller registers */ ++ return mvPexHwConfigWrite (pexIf, bus, dev, func, regOff, data); ++ } ++ else ++ { ++ /* access the virtual brg header */ ++ HEADER_WRITE(data, regOff); ++ return MV_OK; ++ } ++ } ++ else ++ if(bus == (localBus + 1)) ++ { ++ /* access the device behind the virtual bridge */ ++ if((dev == localDev) || (dev > 1)) ++ { ++ return MV_ERROR; ++ } ++ else ++ { ++ /* access the device behind the virtual bridge, in this case ++ * change the bus number to the local bus number in order to ++ * generate type 0 config cycle ++ */ ++ //return mvPexHwConfigWrite (pexIf, localBus, dev, func, regOff, data); ++ mvPexLocalBusNumSet(pexIf, bus); ++ mvPexLocalDevNumSet(pexIf, 1); ++ status = mvPexHwConfigWrite (pexIf, bus, 0, func, regOff, data); ++ mvPexLocalBusNumSet(pexIf, localBus); ++ mvPexLocalDevNumSet(pexIf, localDev); ++ return status; ++ ++ } ++ } ++ /* for all other devices use the HW function to get the ++ * requested registers ++ */ ++ mvPexLocalDevNumSet(pexIf, 1); ++ status = mvPexHwConfigWrite (pexIf, bus, dev, func, regOff, data); ++ mvPexLocalDevNumSet(pexIf, localDev); ++ return status; ++} ++ ++ ++ ++ ++void resetPexConfig(MV_U32 pexIf, MV_U32 bus, MV_U32 dev) ++{ ++ MV_U32 tData; ++ MV_U32 i; ++ ++ /* restore the PEX configuration to initialization state */ ++ /* in case PEX P2P call recursive and reset config */ ++ tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x0); ++ if(tData != 0xffffffff) ++ { ++ /* agent had been found - check whether P2P */ ++ tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x8); ++ if((tData & 0xffff0000) == 0x06040000) ++ {/* P2P */ ++ /* get the sec bus and the subordinate */ ++ MV_U32 secBus; ++ tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x18); ++ secBus = ((tData >> 8) & 0xff); ++ /* now scan on sec bus */ ++ for(i = 0;i < 0xff;i++) ++ { ++ resetPexConfig(pexIf, secBus, i); ++ } ++ /* now reset this device */ ++ DB(mvOsPrintf("Reset bus %d dev %d\n", bus, dev)); ++ mvPexHwConfigWrite(pexIf, bus, dev, 0x0, 0x18, 0x0); ++ DB(mvOsPrintf("Reset bus %d dev %d\n", bus, dev)); ++ } ++ } ++} ++ ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,82 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCVRTBRGPEXH ++#define __INCVRTBRGPEXH ++ ++ ++/* Global Functions prototypes */ ++/* mvPexInit - Initialize PEX interfaces*/ ++MV_STATUS mvPexVrtBrgInit(MV_U32 pexIf); ++ ++/* mvPexConfigRead - Read from configuration space */ ++MV_U32 mvPexVrtBrgConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func,MV_U32 regOff); ++ ++/* mvPexConfigWrite - Write to configuration space */ ++MV_STATUS mvPexVrtBrgConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, ++ MV_U32 func, MV_U32 regOff, MV_U32 data); ++ ++ ++#endif /* #ifndef __INCPEXH */ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvCompVer.txt linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvCompVer.txt +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvCompVer.txt 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvCompVer.txt 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,4 @@ ++Global HAL Version: FEROCEON_HAL_3_1_7 ++Unit HAL Version: 3.1.3 ++Description: This component includes an implementation of the unit HAL drivers ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.c linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.c +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,1522 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++#include "mvOs.h" ++#include "sflash/mvSFlash.h" ++#include "sflash/mvSFlashSpec.h" ++#include "spi/mvSpi.h" ++#include "spi/mvSpiCmnd.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++ ++/*#define MV_DEBUG*/ ++#ifdef MV_DEBUG ++#define DB(x) x ++#else ++#define DB(x) ++#endif ++ ++/* Globals */ ++static MV_SFLASH_DEVICE_PARAMS sflash[] = { ++ /* ST M25P32 SPI flash, 4MB, 64 sectors of 64K each */ ++ { ++ MV_M25P_WREN_CMND_OPCD, ++ MV_M25P_WRDI_CMND_OPCD, ++ MV_M25P_RDID_CMND_OPCD, ++ MV_M25P_RDSR_CMND_OPCD, ++ MV_M25P_WRSR_CMND_OPCD, ++ MV_M25P_READ_CMND_OPCD, ++ MV_M25P_FAST_RD_CMND_OPCD, ++ MV_M25P_PP_CMND_OPCD, ++ MV_M25P_SE_CMND_OPCD, ++ MV_M25P_BE_CMND_OPCD, ++ MV_M25P_RES_CMND_OPCD, ++ MV_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */ ++ MV_M25P32_SECTOR_SIZE, ++ MV_M25P32_SECTOR_NUMBER, ++ MV_M25P_PAGE_SIZE, ++ "ST M25P32", ++ MV_M25PXXX_ST_MANF_ID, ++ MV_M25P32_DEVICE_ID, ++ MV_M25P32_MAX_SPI_FREQ, ++ MV_M25P32_MAX_FAST_SPI_FREQ, ++ MV_M25P32_FAST_READ_DUMMY_BYTES ++ }, ++ /* ST M25P64 SPI flash, 8MB, 128 sectors of 64K each */ ++ { ++ MV_M25P_WREN_CMND_OPCD, ++ MV_M25P_WRDI_CMND_OPCD, ++ MV_M25P_RDID_CMND_OPCD, ++ MV_M25P_RDSR_CMND_OPCD, ++ MV_M25P_WRSR_CMND_OPCD, ++ MV_M25P_READ_CMND_OPCD, ++ MV_M25P_FAST_RD_CMND_OPCD, ++ MV_M25P_PP_CMND_OPCD, ++ MV_M25P_SE_CMND_OPCD, ++ MV_M25P_BE_CMND_OPCD, ++ MV_M25P_RES_CMND_OPCD, ++ MV_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */ ++ MV_M25P64_SECTOR_SIZE, ++ MV_M25P64_SECTOR_NUMBER, ++ MV_M25P_PAGE_SIZE, ++ "ST M25P64", ++ MV_M25PXXX_ST_MANF_ID, ++ MV_M25P64_DEVICE_ID, ++ MV_M25P64_MAX_SPI_FREQ, ++ MV_M25P64_MAX_FAST_SPI_FREQ, ++ MV_M25P64_FAST_READ_DUMMY_BYTES ++ }, ++ /* ST M25P128 SPI flash, 16MB, 64 sectors of 256K each */ ++ { ++ MV_M25P_WREN_CMND_OPCD, ++ MV_M25P_WRDI_CMND_OPCD, ++ MV_M25P_RDID_CMND_OPCD, ++ MV_M25P_RDSR_CMND_OPCD, ++ MV_M25P_WRSR_CMND_OPCD, ++ MV_M25P_READ_CMND_OPCD, ++ MV_M25P_FAST_RD_CMND_OPCD, ++ MV_M25P_PP_CMND_OPCD, ++ MV_M25P_SE_CMND_OPCD, ++ MV_M25P_BE_CMND_OPCD, ++ MV_M25P_RES_CMND_OPCD, ++ MV_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */ ++ MV_M25P128_SECTOR_SIZE, ++ MV_M25P128_SECTOR_NUMBER, ++ MV_M25P_PAGE_SIZE, ++ "ST M25P128", ++ MV_M25PXXX_ST_MANF_ID, ++ MV_M25P128_DEVICE_ID, ++ MV_M25P128_MAX_SPI_FREQ, ++ MV_M25P128_MAX_FAST_SPI_FREQ, ++ MV_M25P128_FAST_READ_DUMMY_BYTES ++ }, ++ /* Macronix MXIC MX25L6405 SPI flash, 8MB, 128 sectors of 64K each */ ++ { ++ MV_MX25L_WREN_CMND_OPCD, ++ MV_MX25L_WRDI_CMND_OPCD, ++ MV_MX25L_RDID_CMND_OPCD, ++ MV_MX25L_RDSR_CMND_OPCD, ++ MV_MX25L_WRSR_CMND_OPCD, ++ MV_MX25L_READ_CMND_OPCD, ++ MV_MX25L_FAST_RD_CMND_OPCD, ++ MV_MX25L_PP_CMND_OPCD, ++ MV_MX25L_SE_CMND_OPCD, ++ MV_MX25L_BE_CMND_OPCD, ++ MV_MX25L_RES_CMND_OPCD, ++ MV_MX25L_DP_CMND_OPCD, ++ MV_MX25L6405_SECTOR_SIZE, ++ MV_MX25L6405_SECTOR_NUMBER, ++ MV_MXIC_PAGE_SIZE, ++ "MXIC MX25L6405", ++ MV_MXIC_MANF_ID, ++ MV_MX25L6405_DEVICE_ID, ++ MV_MX25L6405_MAX_SPI_FREQ, ++ MV_MX25L6405_MAX_FAST_SPI_FREQ, ++ MV_MX25L6405_FAST_READ_DUMMY_BYTES ++ }, ++ /* SPANSION S25FL128P SPI flash, 16MB, 64 sectors of 256K each */ ++ { ++ MV_S25FL_WREN_CMND_OPCD, ++ MV_S25FL_WRDI_CMND_OPCD, ++ MV_S25FL_RDID_CMND_OPCD, ++ MV_S25FL_RDSR_CMND_OPCD, ++ MV_S25FL_WRSR_CMND_OPCD, ++ MV_S25FL_READ_CMND_OPCD, ++ MV_S25FL_FAST_RD_CMND_OPCD, ++ MV_S25FL_PP_CMND_OPCD, ++ MV_S25FL_SE_CMND_OPCD, ++ MV_S25FL_BE_CMND_OPCD, ++ MV_S25FL_RES_CMND_OPCD, ++ MV_S25FL_DP_CMND_OPCD, ++ MV_S25FL128_SECTOR_SIZE, ++ MV_S25FL128_SECTOR_NUMBER, ++ MV_S25FL_PAGE_SIZE, ++ "SPANSION S25FL128", ++ MV_SPANSION_MANF_ID, ++ MV_S25FL128_DEVICE_ID, ++ MV_S25FL128_MAX_SPI_FREQ, ++ MV_M25P128_MAX_FAST_SPI_FREQ, ++ MV_M25P128_FAST_READ_DUMMY_BYTES ++ } ++}; ++ ++/* Static Functions */ ++static MV_STATUS mvWriteEnable (MV_SFLASH_INFO * pFlinfo); ++static MV_STATUS mvStatusRegGet (MV_SFLASH_INFO * pFlinfo, MV_U8 * pStatReg); ++static MV_STATUS mvStatusRegSet (MV_SFLASH_INFO * pFlinfo, MV_U8 sr); ++static MV_STATUS mvWaitOnWipClear(MV_SFLASH_INFO * pFlinfo); ++static MV_STATUS mvSFlashPageWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, \ ++ MV_U8* pPageBuff, MV_U32 buffSize); ++static MV_STATUS mvSFlashWithDefaultsIdGet (MV_SFLASH_INFO * pFlinfo, \ ++ MV_U8* manId, MV_U16* devId); ++ ++/******************************************************************************* ++* mvWriteEnable - serialize the write enable sequence ++* ++* DESCRIPTION: ++* transmit the sequence for write enable ++* ++********************************************************************************/ ++static MV_STATUS mvWriteEnable(MV_SFLASH_INFO * pFlinfo) ++{ ++ MV_U8 cmd[MV_SFLASH_WREN_CMND_LENGTH]; ++ ++ ++ cmd[0] = sflash[pFlinfo->index].opcdWREN; ++ ++ return mvSpiWriteThenRead(cmd, MV_SFLASH_WREN_CMND_LENGTH, NULL, 0, 0); ++} ++ ++/******************************************************************************* ++* mvStatusRegGet - Retrieve the value of the status register ++* ++* DESCRIPTION: ++* perform the RDSR sequence to get the 8bit status register ++* ++********************************************************************************/ ++static MV_STATUS mvStatusRegGet(MV_SFLASH_INFO * pFlinfo, MV_U8 * pStatReg) ++{ ++ MV_STATUS ret; ++ MV_U8 cmd[MV_SFLASH_RDSR_CMND_LENGTH]; ++ MV_U8 sr[MV_SFLASH_RDSR_REPLY_LENGTH]; ++ ++ ++ ++ ++ cmd[0] = sflash[pFlinfo->index].opcdRDSR; ++ ++ if ((ret = mvSpiWriteThenRead(cmd, MV_SFLASH_RDSR_CMND_LENGTH, sr, ++ MV_SFLASH_RDSR_REPLY_LENGTH,0)) != MV_OK) ++ return ret; ++ ++ *pStatReg = sr[0]; ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvWaitOnWipClear - Block waiting for the WIP (write in progress) to be cleared ++* ++* DESCRIPTION: ++* Block waiting for the WIP (write in progress) to be cleared ++* ++********************************************************************************/ ++static MV_STATUS mvWaitOnWipClear(MV_SFLASH_INFO * pFlinfo) ++{ ++ MV_STATUS ret; ++ MV_U32 i; ++ MV_U8 stat; ++ ++ for (i=0; iindex].opcdWRSR; ++ cmd[1] = sr; ++ ++ if ((ret = mvSpiWriteThenRead(cmd, MV_SFLASH_WRSR_CMND_LENGTH, NULL, 0, 0)) != MV_OK) ++ return ret; ++ ++ if ((ret = mvWaitOnWipClear(pFlinfo)) != MV_OK) ++ return ret; ++ ++ mvOsDelay(1); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvSFlashPageWr - Write up to 256 Bytes in the same page ++* ++* DESCRIPTION: ++* Write a buffer up to the page size in length provided that the whole address ++* range is within the same page (alligned to page bounderies) ++* ++*******************************************************************************/ ++static MV_STATUS mvSFlashPageWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, ++ MV_U8* pPageBuff, MV_U32 buffSize) ++{ ++ MV_STATUS ret; ++ MV_U8 cmd[MV_SFLASH_PP_CMND_LENGTH]; ++ ++ ++ /* Protection - check if the model was detected */ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ { ++ DB(mvOsPrintf("%s WARNING: Invalid parameter device index!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ /* check that we do not cross the page bounderies */ ++ if (((offset & (sflash[pFlinfo->index].pageSize - 1)) + buffSize) > ++ sflash[pFlinfo->index].pageSize) ++ { ++ DB(mvOsPrintf("%s WARNING: Page allignment problem!\n", __FUNCTION__);) ++ return MV_OUT_OF_RANGE; ++ } ++ ++ /* Issue the Write enable command prior the page program command */ ++ if ((ret = mvWriteEnable(pFlinfo)) != MV_OK) ++ return ret; ++ ++ cmd[0] = sflash[pFlinfo->index].opcdPP; ++ cmd[1] = ((offset >> 16) & 0xFF); ++ cmd[2] = ((offset >> 8) & 0xFF); ++ cmd[3] = (offset & 0xFF); ++ ++ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_PP_CMND_LENGTH, pPageBuff, buffSize)) != MV_OK) ++ return ret; ++ ++ if ((ret = mvWaitOnWipClear(pFlinfo)) != MV_OK) ++ return ret; ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvSFlashWithDefaultsIdGet - Try to read the manufacturer and Device IDs from ++* the device using the default RDID opcode and the default WREN opcode. ++* ++* DESCRIPTION: ++* This is used to detect a generic device that uses the default opcodes ++* for the WREN and RDID. ++* ++********************************************************************************/ ++static MV_STATUS mvSFlashWithDefaultsIdGet (MV_SFLASH_INFO * pFlinfo, MV_U8* manId, MV_U16* devId) ++{ ++ MV_STATUS ret; ++ MV_U8 cmdRDID[MV_SFLASH_RDID_CMND_LENGTH]; ++ MV_U8 id[MV_SFLASH_RDID_REPLY_LENGTH]; ++ ++ ++ ++ /* Use the default RDID opcode to read the IDs */ ++ cmdRDID[0] = MV_SFLASH_DEFAULT_RDID_OPCD; /* unknown model try default */ ++ if ((ret = mvSpiWriteThenRead(cmdRDID, MV_SFLASH_RDID_CMND_LENGTH, id, MV_SFLASH_RDID_REPLY_LENGTH, 0)) != MV_OK) ++ return ret; ++ ++ *manId = id[0]; ++ *devId = 0; ++ *devId |= (id[1] << 8); ++ *devId |= id[2]; ++ ++ return MV_OK; ++} ++ ++/* ++##################################################################################### ++##################################################################################### ++*/ ++ ++/******************************************************************************* ++* mvSFlashInit - Initialize the serial flash device ++* ++* DESCRIPTION: ++* Perform the neccessary initialization and configuration ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* pFlinfo->baseAddr: base address in fast mode. ++* pFlinfo->index: Index of the flash in the sflash tabel. If the SPI ++* flash device does not support read Id command with ++* the standard opcode, then the user should supply this ++* as an input to skip the autodetection process!!!! ++* ++* OUTPUT: ++* pFlinfo: pointer to the Flash information structure after detection ++* pFlinfo->manufacturerId: Manufacturer ID ++* pFlinfo->deviceId: Device ID ++* pFlinfo->sectorSize: size of the sector (all sectors are the same). ++* pFlinfo->sectorNumber: number of sectors. ++* pFlinfo->pageSize: size of the page. ++* pFlinfo->index: Index of the detected flash in the sflash tabel ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSFlashInit (MV_SFLASH_INFO * pFlinfo) ++{ ++ MV_STATUS ret; ++ MV_U8 manf; ++ MV_U16 dev; ++ MV_U32 indx; ++ MV_BOOL detectFlag = MV_FALSE; ++ ++ /* check for NULL pointer */ ++ if (pFlinfo == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Initialize the SPI interface with low frequency to make sure that the read ID succeeds */ ++ if ((ret = mvSpiInit(MV_SFLASH_BASIC_SPI_FREQ)) != MV_OK) ++ { ++ mvOsPrintf("%s ERROR: Failed to initialize the SPI interface!\n", __FUNCTION__); ++ return ret; ++ } ++ ++ /* First try to read the Manufacturer and Device IDs */ ++ if ((ret = mvSFlashIdGet(pFlinfo, &manf, &dev)) != MV_OK) ++ { ++ mvOsPrintf("%s ERROR: Failed to get the SFlash ID!\n", __FUNCTION__); ++ return ret; ++ } ++ ++ /* loop over the whole table and look for the appropriate SFLASH */ ++ for (indx=0; indxmanufacturerId = manf; ++ pFlinfo->deviceId = dev; ++ pFlinfo->index = indx; ++ detectFlag = MV_TRUE; ++ } ++ } ++ ++ if(!detectFlag) ++ { ++ mvOsPrintf("%s ERROR: Unknown SPI flash device!\n", __FUNCTION__); ++ return MV_FAIL; ++ } ++ ++ /* fill the info based on the model detected */ ++ pFlinfo->sectorSize = sflash[pFlinfo->index].sectorSize; ++ pFlinfo->sectorNumber = sflash[pFlinfo->index].sectorNumber; ++ pFlinfo->pageSize = sflash[pFlinfo->index].pageSize; ++ ++ /* Set the SPI frequency to the MAX allowed for the device for best performance */ ++ if ((ret = mvSpiBaudRateSet(sflash[pFlinfo->index].spiMaxFreq)) != MV_OK) ++ { ++ mvOsPrintf("%s ERROR: Failed to set the SPI frequency!\n", __FUNCTION__); ++ return ret; ++ } ++ ++ /* As default lock the SR */ ++ if ((ret = mvSFlashStatRegLock(pFlinfo, MV_TRUE)) != MV_OK) ++ return ret; ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvSFlashSectorErase - Erasse a single sector of the serial flash ++* ++* DESCRIPTION: ++* Issue the erase sector command and address ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* secNumber: sector Number to erase (0 -> (sectorNumber-1)) ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSFlashSectorErase (MV_SFLASH_INFO * pFlinfo, MV_U32 secNumber) ++{ ++ MV_STATUS ret; ++ MV_U8 cmd[MV_SFLASH_SE_CMND_LENGTH]; ++ ++ MV_U32 secAddr = (secNumber * pFlinfo->sectorSize); ++#if 0 ++ MV_U32 i; ++ MV_U32 * pW = (MV_U32*) (secAddr + pFlinfo->baseAddr); ++ MV_U32 erasedWord = 0xFFFFFFFF; ++ MV_U32 wordsPerSector = (pFlinfo->sectorSize / sizeof(MV_U32)); ++ MV_BOOL eraseNeeded = MV_FALSE; ++#endif ++ /* check for NULL pointer */ ++ if (pFlinfo == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Protection - check if the model was detected */ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ /* check that the sector number is valid */ ++ if (secNumber >= pFlinfo->sectorNumber) ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter sector number!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ /* we don't want to access SPI in direct mode from in-direct API, ++ becasue of timing issue between CS asserts. */ ++#if 0 ++ /* First compare to FF and check if erase is needed */ ++ for (i=0; iindex].opcdSE; ++ cmd[1] = ((secAddr >> 16) & 0xFF); ++ cmd[2] = ((secAddr >> 8) & 0xFF); ++ cmd[3] = (secAddr & 0xFF); ++ ++ /* Issue the Write enable command prior the sector erase command */ ++ if ((ret = mvWriteEnable(pFlinfo)) != MV_OK) ++ return ret; ++ ++ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_SE_CMND_LENGTH, NULL, 0)) != MV_OK) ++ return ret; ++ ++ if ((ret = mvWaitOnWipClear(pFlinfo)) != MV_OK) ++ return ret; ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvSFlashChipErase - Erasse the whole serial flash ++* ++* DESCRIPTION: ++* Issue the bulk (chip) erase command ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSFlashChipErase (MV_SFLASH_INFO * pFlinfo) ++{ ++ MV_STATUS ret; ++ MV_U8 cmd[MV_SFLASH_BE_CMND_LENGTH]; ++ ++ ++ /* check for NULL pointer */ ++ if (pFlinfo == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Protection - check if the model was detected */ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ cmd[0] = sflash[pFlinfo->index].opcdBE; ++ ++ /* Issue the Write enable command prior the Bulk erase command */ ++ if ((ret = mvWriteEnable(pFlinfo)) != MV_OK) ++ return ret; ++ ++ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_BE_CMND_LENGTH, NULL, 0)) != MV_OK) ++ return ret; ++ ++ if ((ret = mvWaitOnChipEraseDone(pFlinfo)) != MV_OK) ++ return ret; ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvSFlashBlockRd - Read from the serial flash ++* ++* DESCRIPTION: ++* Issue the read command and address then perfom the needed read ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* offset: byte offset with the flash to start reading from ++* pReadBuff: pointer to the buffer to read the data in ++* buffSize: size of the buffer to read. ++* ++* OUTPUT: ++* pReadBuff: pointer to the buffer containing the read data ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSFlashBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, ++ MV_U8* pReadBuff, MV_U32 buffSize) ++{ ++ MV_U8 cmd[MV_SFLASH_READ_CMND_LENGTH]; ++ ++ ++ /* check for NULL pointer */ ++ if ((pFlinfo == NULL) || (pReadBuff == NULL)) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Protection - check if the model was detected */ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ cmd[0] = sflash[pFlinfo->index].opcdREAD; ++ cmd[1] = ((offset >> 16) & 0xFF); ++ cmd[2] = ((offset >> 8) & 0xFF); ++ cmd[3] = (offset & 0xFF); ++ ++ return mvSpiWriteThenRead(cmd, MV_SFLASH_READ_CMND_LENGTH, pReadBuff, buffSize, 0); ++} ++ ++/******************************************************************************* ++* mvSFlashFastBlockRd - Fast read from the serial flash ++* ++* DESCRIPTION: ++* Issue the fast read command and address then perfom the needed read ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* offset: byte offset with the flash to start reading from ++* pReadBuff: pointer to the buffer to read the data in ++* buffSize: size of the buffer to read. ++* ++* OUTPUT: ++* pReadBuff: pointer to the buffer containing the read data ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSFlashFastBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, ++ MV_U8* pReadBuff, MV_U32 buffSize) ++{ ++ MV_U8 cmd[MV_SFLASH_READ_CMND_LENGTH]; ++ MV_STATUS ret; ++ ++ /* check for NULL pointer */ ++ if ((pFlinfo == NULL) || (pReadBuff == NULL)) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Protection - check if the model was detected */ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ /* Set the SPI frequency to the MAX allowed for fast-read operations */ ++ mvOsPrintf("Setting freq to %d.\n",sflash[pFlinfo->index].spiMaxFastFreq); ++ if ((ret = mvSpiBaudRateSet(sflash[pFlinfo->index].spiMaxFastFreq)) != MV_OK) ++ { ++ mvOsPrintf("%s ERROR: Failed to set the SPI fast frequency!\n", __FUNCTION__); ++ return ret; ++ } ++ ++ cmd[0] = sflash[pFlinfo->index].opcdFSTRD; ++ cmd[1] = ((offset >> 16) & 0xFF); ++ cmd[2] = ((offset >> 8) & 0xFF); ++ cmd[3] = (offset & 0xFF); ++ ++ ++ ret = mvSpiWriteThenRead(cmd, MV_SFLASH_READ_CMND_LENGTH, pReadBuff, buffSize, ++ sflash[pFlinfo->index].spiFastRdDummyBytes); ++ ++ /* Reset the SPI frequency to the MAX allowed for the device for best performance */ ++ if ((ret = mvSpiBaudRateSet(sflash[pFlinfo->index].spiMaxFreq)) != MV_OK) ++ { ++ mvOsPrintf("%s ERROR: Failed to set the SPI frequency!\n", __FUNCTION__); ++ return ret; ++ } ++ ++ return ret; ++} ++ ++ ++/******************************************************************************* ++* mvSFlashBlockWr - Write a buffer with any size ++* ++* DESCRIPTION: ++* write regardless of the page boundaries and size limit per Page ++* program command ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* offset: byte offset within the flash region ++* pWriteBuff: pointer to the buffer holding the data to program ++* buffSize: size of the buffer to write ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSFlashBlockWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, ++ MV_U8* pWriteBuff, MV_U32 buffSize) ++{ ++ MV_STATUS ret; ++ MV_U32 data2write = buffSize; ++ MV_U32 preAllOffset = (offset & MV_SFLASH_PAGE_ALLIGN_MASK(MV_M25P_PAGE_SIZE)); ++ MV_U32 preAllSz = (preAllOffset ? (MV_M25P_PAGE_SIZE - preAllOffset) : 0); ++ MV_U32 writeOffset = offset; ++ ++ /* check for NULL pointer */ ++#ifndef CONFIG_MARVELL ++ if(NULL == pWriteBuff) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++#endif ++ ++ if (pFlinfo == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Protection - check if the model was detected */ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ /* check that the buffer size does not exceed the flash size */ ++ if ((offset + buffSize) > mvSFlashSizeGet(pFlinfo)) ++ { ++ DB(mvOsPrintf("%s WARNING: Write exceeds flash size!\n", __FUNCTION__);) ++ return MV_OUT_OF_RANGE; ++ } ++ ++ /* check if the total block size is less than the first chunk remainder */ ++ if (data2write < preAllSz) ++ preAllSz = data2write; ++ ++ /* check if programing does not start at a 64byte alligned offset */ ++ if (preAllSz) ++ { ++ if ((ret = mvSFlashPageWr(pFlinfo, writeOffset, pWriteBuff, preAllSz)) != MV_OK) ++ return ret; ++ ++ /* increment pointers and counters */ ++ writeOffset += preAllSz; ++ data2write -= preAllSz; ++ pWriteBuff += preAllSz; ++ } ++ ++ /* program the data that fits in complete page chunks */ ++ while (data2write >= sflash[pFlinfo->index].pageSize) ++ { ++ if ((ret = mvSFlashPageWr(pFlinfo, writeOffset, pWriteBuff, sflash[pFlinfo->index].pageSize)) != MV_OK) ++ return ret; ++ ++ /* increment pointers and counters */ ++ writeOffset += sflash[pFlinfo->index].pageSize; ++ data2write -= sflash[pFlinfo->index].pageSize; ++ pWriteBuff += sflash[pFlinfo->index].pageSize; ++ } ++ ++ /* program the last partial chunk */ ++ if (data2write) ++ { ++ if ((ret = mvSFlashPageWr(pFlinfo, writeOffset, pWriteBuff, data2write)) != MV_OK) ++ return ret; ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvSFlashIdGet - Get the manufacturer and device IDs. ++* ++* DESCRIPTION: ++* Get the Manufacturer and device IDs from the serial flash through ++* writing the RDID command then reading 3 bytes of data. In case that ++* this command was called for the first time in order to detect the ++* manufacturer and device IDs, then the default RDID opcode will be used ++* unless the device index is indicated by the user (in case the SPI flash ++* does not use the default RDID opcode). ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* pManId: pointer to the 8bit variable to hold the manufacturing ID ++* pDevId: pointer to the 16bit variable to hold the device ID ++* ++* OUTPUT: ++* pManId: pointer to the 8bit variable holding the manufacturing ID ++* pDevId: pointer to the 16bit variable holding the device ID ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSFlashIdGet (MV_SFLASH_INFO * pFlinfo, MV_U8* pManId, MV_U16* pDevId) ++{ ++ MV_STATUS ret; ++ MV_U8 cmd[MV_SFLASH_RDID_CMND_LENGTH]; ++ MV_U8 id[MV_SFLASH_RDID_REPLY_LENGTH]; ++ ++ ++ ++ /* check for NULL pointer */ ++ if ((pFlinfo == NULL) || (pManId == NULL) || (pDevId == NULL)) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ return mvSFlashWithDefaultsIdGet(pFlinfo, pManId, pDevId); ++ else ++ cmd[0] = sflash[pFlinfo->index].opcdRDID; ++ ++ if ((ret = mvSpiWriteThenRead(cmd, MV_SFLASH_RDID_CMND_LENGTH, id, MV_SFLASH_RDID_REPLY_LENGTH, 0)) != MV_OK) ++ return ret; ++ ++ *pManId = id[0]; ++ *pDevId = 0; ++ *pDevId |= (id[1] << 8); ++ *pDevId |= id[2]; ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvSFlashWpRegionSet - Set the Write-Protected region ++* ++* DESCRIPTION: ++* Set the Write-Protected region ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* wpRegion: which region will be protected ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSFlashWpRegionSet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION wpRegion) ++{ ++ MV_U8 wpMask; ++ ++ /* check for NULL pointer */ ++ if (pFlinfo == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Protection - check if the model was detected */ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check if the chip is an ST flash; then WP supports only 3 bits */ ++ if (pFlinfo->manufacturerId == MV_M25PXXX_ST_MANF_ID) ++ { ++ switch (wpRegion) ++ { ++ case MV_WP_NONE: ++ wpMask = MV_M25P_STATUS_BP_NONE; ++ break; ++ ++ case MV_WP_UPR_1OF128: ++ DB(mvOsPrintf("%s WARNING: Invaild option for this flash chip!\n", __FUNCTION__);) ++ return MV_NOT_SUPPORTED; ++ ++ case MV_WP_UPR_1OF64: ++ wpMask = MV_M25P_STATUS_BP_1_OF_64; ++ break; ++ ++ case MV_WP_UPR_1OF32: ++ wpMask = MV_M25P_STATUS_BP_1_OF_32; ++ break; ++ ++ case MV_WP_UPR_1OF16: ++ wpMask = MV_M25P_STATUS_BP_1_OF_16; ++ break; ++ ++ case MV_WP_UPR_1OF8: ++ wpMask = MV_M25P_STATUS_BP_1_OF_8; ++ break; ++ ++ case MV_WP_UPR_1OF4: ++ wpMask = MV_M25P_STATUS_BP_1_OF_4; ++ break; ++ ++ case MV_WP_UPR_1OF2: ++ wpMask = MV_M25P_STATUS_BP_1_OF_2; ++ break; ++ ++ case MV_WP_ALL: ++ wpMask = MV_M25P_STATUS_BP_ALL; ++ break; ++ ++ default: ++ DB(mvOsPrintf("%s WARNING: Invaild parameter WP region!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ } ++ /* check if the manufacturer is MXIC then the WP is 4bits */ ++ else if (pFlinfo->manufacturerId == MV_MXIC_MANF_ID) ++ { ++ switch (wpRegion) ++ { ++ case MV_WP_NONE: ++ wpMask = MV_MX25L_STATUS_BP_NONE; ++ break; ++ ++ case MV_WP_UPR_1OF128: ++ wpMask = MV_MX25L_STATUS_BP_1_OF_128; ++ break; ++ ++ case MV_WP_UPR_1OF64: ++ wpMask = MV_MX25L_STATUS_BP_1_OF_64; ++ break; ++ ++ case MV_WP_UPR_1OF32: ++ wpMask = MV_MX25L_STATUS_BP_1_OF_32; ++ break; ++ ++ case MV_WP_UPR_1OF16: ++ wpMask = MV_MX25L_STATUS_BP_1_OF_16; ++ break; ++ ++ case MV_WP_UPR_1OF8: ++ wpMask = MV_MX25L_STATUS_BP_1_OF_8; ++ break; ++ ++ case MV_WP_UPR_1OF4: ++ wpMask = MV_MX25L_STATUS_BP_1_OF_4; ++ break; ++ ++ case MV_WP_UPR_1OF2: ++ wpMask = MV_MX25L_STATUS_BP_1_OF_2; ++ break; ++ ++ case MV_WP_ALL: ++ wpMask = MV_MX25L_STATUS_BP_ALL; ++ break; ++ ++ default: ++ DB(mvOsPrintf("%s WARNING: Invaild parameter WP region!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ } ++ /* check if the manufacturer is SPANSION then the WP is 4bits */ ++ else if (pFlinfo->manufacturerId == MV_SPANSION_MANF_ID) ++ { ++ switch (wpRegion) ++ { ++ case MV_WP_NONE: ++ wpMask = MV_S25FL_STATUS_BP_NONE; ++ break; ++ ++ case MV_WP_UPR_1OF128: ++ DB(mvOsPrintf("%s WARNING: Invaild option for this flash chip!\n", __FUNCTION__);) ++ return MV_NOT_SUPPORTED; ++ ++ case MV_WP_UPR_1OF64: ++ wpMask = MV_S25FL_STATUS_BP_1_OF_64; ++ break; ++ ++ case MV_WP_UPR_1OF32: ++ wpMask = MV_S25FL_STATUS_BP_1_OF_32; ++ break; ++ ++ case MV_WP_UPR_1OF16: ++ wpMask = MV_S25FL_STATUS_BP_1_OF_16; ++ break; ++ ++ case MV_WP_UPR_1OF8: ++ wpMask = MV_S25FL_STATUS_BP_1_OF_8; ++ break; ++ ++ case MV_WP_UPR_1OF4: ++ wpMask = MV_S25FL_STATUS_BP_1_OF_4; ++ break; ++ ++ case MV_WP_UPR_1OF2: ++ wpMask = MV_S25FL_STATUS_BP_1_OF_2; ++ break; ++ ++ case MV_WP_ALL: ++ wpMask = MV_S25FL_STATUS_BP_ALL; ++ break; ++ ++ ++ default: ++ DB(mvOsPrintf("%s WARNING: Invaild parameter WP region!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ } ++ else ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter Manufacturer ID!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ /* Verify that the SRWD bit is always set - register is s/w locked */ ++ wpMask |= MV_SFLASH_STATUS_REG_SRWD_MASK; ++ ++ return mvStatusRegSet(pFlinfo, wpMask); ++} ++ ++/******************************************************************************* ++* mvSFlashWpRegionGet - Get the Write-Protected region configured ++* ++* DESCRIPTION: ++* Get from the chip the Write-Protected region configured ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* pWpRegion: pointer to the variable to return the WP region in ++* ++* OUTPUT: ++* wpRegion: pointer to the variable holding the WP region configured ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSFlashWpRegionGet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION * pWpRegion) ++{ ++ MV_STATUS ret; ++ MV_U8 reg; ++ ++ /* check for NULL pointer */ ++ if ((pFlinfo == NULL) || (pWpRegion == NULL)) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Protection - check if the model was detected */ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ if ((ret = mvStatusRegGet(pFlinfo, ®)) != MV_OK) ++ return ret; ++ ++ /* Check if the chip is an ST flash; then WP supports only 3 bits */ ++ if (pFlinfo->manufacturerId == MV_M25PXXX_ST_MANF_ID) ++ { ++ switch ((reg & MV_M25P_STATUS_REG_WP_MASK)) ++ { ++ case MV_M25P_STATUS_BP_NONE: ++ *pWpRegion = MV_WP_NONE; ++ break; ++ ++ case MV_M25P_STATUS_BP_1_OF_64: ++ *pWpRegion = MV_WP_UPR_1OF64; ++ break; ++ ++ case MV_M25P_STATUS_BP_1_OF_32: ++ *pWpRegion = MV_WP_UPR_1OF32; ++ break; ++ ++ case MV_M25P_STATUS_BP_1_OF_16: ++ *pWpRegion = MV_WP_UPR_1OF16; ++ break; ++ ++ case MV_M25P_STATUS_BP_1_OF_8: ++ *pWpRegion = MV_WP_UPR_1OF8; ++ break; ++ ++ case MV_M25P_STATUS_BP_1_OF_4: ++ *pWpRegion = MV_WP_UPR_1OF4; ++ break; ++ ++ case MV_M25P_STATUS_BP_1_OF_2: ++ *pWpRegion = MV_WP_UPR_1OF2; ++ break; ++ ++ case MV_M25P_STATUS_BP_ALL: ++ *pWpRegion = MV_WP_ALL; ++ break; ++ ++ default: ++ DB(mvOsPrintf("%s WARNING: Unidentified WP region in h/w!\n", __FUNCTION__);) ++ return MV_BAD_VALUE; ++ } ++ } ++ /* check if the manufacturer is MXIC then the WP is 4bits */ ++ else if (pFlinfo->manufacturerId == MV_MXIC_MANF_ID) ++ { ++ switch ((reg & MV_MX25L_STATUS_REG_WP_MASK)) ++ { ++ case MV_MX25L_STATUS_BP_NONE: ++ *pWpRegion = MV_WP_NONE; ++ break; ++ ++ case MV_MX25L_STATUS_BP_1_OF_128: ++ *pWpRegion = MV_WP_UPR_1OF128; ++ break; ++ ++ case MV_MX25L_STATUS_BP_1_OF_64: ++ *pWpRegion = MV_WP_UPR_1OF64; ++ break; ++ ++ case MV_MX25L_STATUS_BP_1_OF_32: ++ *pWpRegion = MV_WP_UPR_1OF32; ++ break; ++ ++ case MV_MX25L_STATUS_BP_1_OF_16: ++ *pWpRegion = MV_WP_UPR_1OF16; ++ break; ++ ++ case MV_MX25L_STATUS_BP_1_OF_8: ++ *pWpRegion = MV_WP_UPR_1OF8; ++ break; ++ ++ case MV_MX25L_STATUS_BP_1_OF_4: ++ *pWpRegion = MV_WP_UPR_1OF4; ++ break; ++ ++ case MV_MX25L_STATUS_BP_1_OF_2: ++ *pWpRegion = MV_WP_UPR_1OF2; ++ break; ++ ++ case MV_MX25L_STATUS_BP_ALL: ++ *pWpRegion = MV_WP_ALL; ++ break; ++ ++ default: ++ DB(mvOsPrintf("%s WARNING: Unidentified WP region in h/w!\n", __FUNCTION__);) ++ return MV_BAD_VALUE; ++ } ++ } ++ /* Check if the chip is an SPANSION flash; then WP supports only 3 bits */ ++ else if (pFlinfo->manufacturerId == MV_SPANSION_MANF_ID) ++ { ++ switch ((reg & MV_S25FL_STATUS_REG_WP_MASK)) ++ { ++ case MV_S25FL_STATUS_BP_NONE: ++ *pWpRegion = MV_WP_NONE; ++ break; ++ ++ case MV_S25FL_STATUS_BP_1_OF_64: ++ *pWpRegion = MV_WP_UPR_1OF64; ++ break; ++ ++ case MV_S25FL_STATUS_BP_1_OF_32: ++ *pWpRegion = MV_WP_UPR_1OF32; ++ break; ++ ++ case MV_S25FL_STATUS_BP_1_OF_16: ++ *pWpRegion = MV_WP_UPR_1OF16; ++ break; ++ ++ case MV_S25FL_STATUS_BP_1_OF_8: ++ *pWpRegion = MV_WP_UPR_1OF8; ++ break; ++ ++ case MV_S25FL_STATUS_BP_1_OF_4: ++ *pWpRegion = MV_WP_UPR_1OF4; ++ break; ++ ++ case MV_S25FL_STATUS_BP_1_OF_2: ++ *pWpRegion = MV_WP_UPR_1OF2; ++ break; ++ ++ case MV_S25FL_STATUS_BP_ALL: ++ *pWpRegion = MV_WP_ALL; ++ break; ++ ++ default: ++ DB(mvOsPrintf("%s WARNING: Unidentified WP region in h/w!\n", __FUNCTION__);) ++ return MV_BAD_VALUE; ++ } ++ } ++ else ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter Manufacturer ID!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvSFlashStatRegLock - Lock the status register for writing - W/Vpp ++* pin should be low to take effect ++* ++* DESCRIPTION: ++* Lock the access to the Status Register for writing. This will ++* cause the flash to enter the hardware protection mode if the W/Vpp ++* is low. If the W/Vpp is hi, the chip will be in soft protection mode, but ++* the register will continue to be writable if WREN sequence was used. ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* srLock: enable/disable (MV_TRUE/MV_FALSE) status registor lock mechanism ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSFlashStatRegLock (MV_SFLASH_INFO * pFlinfo, MV_BOOL srLock) ++{ ++ MV_STATUS ret; ++ MV_U8 reg; ++ ++ /* check for NULL pointer */ ++ if (pFlinfo == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Protection - check if the model was detected */ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ if ((ret = mvStatusRegGet(pFlinfo, ®)) != MV_OK) ++ return ret; ++ ++ if (srLock) ++ reg |= MV_SFLASH_STATUS_REG_SRWD_MASK; ++ else ++ reg &= ~MV_SFLASH_STATUS_REG_SRWD_MASK; ++ ++ return mvStatusRegSet(pFlinfo, reg); ++} ++ ++/******************************************************************************* ++* mvSFlashSizeGet - Get the size of the SPI flash ++* ++* DESCRIPTION: ++* based on the sector number and size of each sector calculate the total ++* size of the flash memory. ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Size of the flash in bytes. ++* ++* ++*******************************************************************************/ ++MV_U32 mvSFlashSizeGet (MV_SFLASH_INFO * pFlinfo) ++{ ++ /* check for NULL pointer */ ++ if (pFlinfo == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return 0; ++ } ++ ++ return (pFlinfo->sectorSize * pFlinfo->sectorNumber); ++} ++ ++/******************************************************************************* ++* mvSFlashPowerSaveEnter - Cause the falsh device to go into power save mode ++* ++* DESCRIPTION: ++* Enter a special power save mode. ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Size of the flash in bytes. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSFlashPowerSaveEnter(MV_SFLASH_INFO * pFlinfo) ++{ ++ MV_STATUS ret; ++ MV_U8 cmd[MV_SFLASH_DP_CMND_LENGTH]; ++ ++ ++ /* check for NULL pointer */ ++ if (pFlinfo == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return 0; ++ } ++ ++ /* Protection - check if the model was detected */ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ /* check that power save mode is supported in the specific device */ ++ if (sflash[pFlinfo->index].opcdPwrSave == MV_SFLASH_NO_SPECIFIC_OPCD) ++ { ++ DB(mvOsPrintf("%s WARNING: Power save not supported for this device!\n", __FUNCTION__);) ++ return MV_NOT_SUPPORTED; ++ } ++ ++ cmd[0] = sflash[pFlinfo->index].opcdPwrSave; ++ ++ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_DP_CMND_LENGTH, NULL, 0)) != MV_OK) ++ return ret; ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvSFlashPowerSaveExit - Cause the falsh device to exit the power save mode ++* ++* DESCRIPTION: ++* Exit the deep power save mode. ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Size of the flash in bytes. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSFlashPowerSaveExit (MV_SFLASH_INFO * pFlinfo) ++{ ++ MV_STATUS ret; ++ MV_U8 cmd[MV_SFLASH_RES_CMND_LENGTH]; ++ ++ ++ /* check for NULL pointer */ ++ if (pFlinfo == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return 0; ++ } ++ ++ /* Protection - check if the model was detected */ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) ++ return MV_BAD_PARAM; ++ } ++ ++ /* check that power save mode is supported in the specific device */ ++ if (sflash[pFlinfo->index].opcdRES == MV_SFLASH_NO_SPECIFIC_OPCD) ++ { ++ DB(mvOsPrintf("%s WARNING: Read Electronic Signature not supported for this device!\n", __FUNCTION__);) ++ return MV_NOT_SUPPORTED; ++ } ++ ++ cmd[0] = sflash[pFlinfo->index].opcdRES; ++ ++ if ((ret = mvSpiWriteThenWrite(cmd, MV_SFLASH_RES_CMND_LENGTH, NULL, 0)) != MV_OK) ++ return ret; ++ ++ /* add the delay needed for the device to wake up */ ++ mvOsDelay(MV_MXIC_DP_EXIT_DELAY); /* 30 ms */ ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvSFlashModelGet - Retreive the string with the device manufacturer and model ++* ++* DESCRIPTION: ++* Retreive the string with the device manufacturer and model ++* ++* INPUT: ++* pFlinfo: pointer to the Flash information structure ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* pointer to the string indicating the device manufacturer and model ++* ++* ++*******************************************************************************/ ++const MV_8 * mvSFlashModelGet (MV_SFLASH_INFO * pFlinfo) ++{ ++ static const MV_8 * unknModel = (const MV_8 *)"Unknown"; ++ ++ /* check for NULL pointer */ ++ if (pFlinfo == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return 0; ++ } ++ ++ /* Protection - check if the model was detected */ ++ if (pFlinfo->index >= MV_ARRAY_SIZE(sflash)) ++ { ++ DB(mvOsPrintf("%s WARNING: Invaild parameter index!\n", __FUNCTION__);) ++ return unknModel; ++ } ++ ++ return sflash[pFlinfo->index].deviceModel; ++} ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlash.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,166 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvSFlashH ++#define __INCmvSFlashH ++ ++#include "mvTypes.h" ++ ++/* MCAROS */ ++#define MV_SFLASH_PAGE_ALLIGN_MASK(pgSz) (pgSz-1) ++#define MV_ARRAY_SIZE(a) ((sizeof(a)) / (sizeof(a[0]))) ++ ++/* Constants */ ++#define MV_INVALID_DEVICE_NUMBER 0xFFFFFFFF ++/* 10 MHz is the minimum possible SPI frequency when tclk is set 200MHz*/ ++#define MV_SFLASH_BASIC_SPI_FREQ 10000000 ++/* enumerations */ ++typedef enum ++{ ++ MV_WP_NONE, /* Unprotect the whole chip */ ++ MV_WP_UPR_1OF128, /* Write protect the upper 1/128 part */ ++ MV_WP_UPR_1OF64, /* Write protect the upper 1/64 part */ ++ MV_WP_UPR_1OF32, /* Write protect the upper 1/32 part */ ++ MV_WP_UPR_1OF16, /* Write protect the upper 1/16 part */ ++ MV_WP_UPR_1OF8, /* Write protect the upper 1/8 part */ ++ MV_WP_UPR_1OF4, /* Write protect the upper 1/4 part */ ++ MV_WP_UPR_1OF2, /* Write protect the upper 1/2 part */ ++ MV_WP_ALL /* Write protect the whole chip */ ++} MV_SFLASH_WP_REGION; ++ ++/* Type Definitions */ ++typedef struct ++{ ++ MV_U8 opcdWREN; /* Write enable opcode */ ++ MV_U8 opcdWRDI; /* Write disable opcode */ ++ MV_U8 opcdRDID; /* Read ID opcode */ ++ MV_U8 opcdRDSR; /* Read Status Register opcode */ ++ MV_U8 opcdWRSR; /* Write Status register opcode */ ++ MV_U8 opcdREAD; /* Read opcode */ ++ MV_U8 opcdFSTRD; /* Fast Read opcode */ ++ MV_U8 opcdPP; /* Page program opcode */ ++ MV_U8 opcdSE; /* Sector erase opcode */ ++ MV_U8 opcdBE; /* Bulk erase opcode */ ++ MV_U8 opcdRES; /* Read electronic signature */ ++ MV_U8 opcdPwrSave; /* Go into power save mode */ ++ MV_U32 sectorSize; /* Size of each sector */ ++ MV_U32 sectorNumber; /* Number of sectors */ ++ MV_U32 pageSize; /* size of each page */ ++ const char * deviceModel; /* string with the device model */ ++ MV_U32 manufacturerId; /* The manufacturer ID */ ++ MV_U32 deviceId; /* Device ID */ ++ MV_U32 spiMaxFreq; /* The MAX frequency that can be used with the device */ ++ MV_U32 spiMaxFastFreq; /* The MAX frequency that can be used with the device for fast reads */ ++ MV_U32 spiFastRdDummyBytes; /* Number of dumy bytes to read before real data when working in fast read mode. */ ++} MV_SFLASH_DEVICE_PARAMS; ++ ++typedef struct ++{ ++ MV_U32 baseAddr; /* Flash Base Address used in fast mode */ ++ MV_U8 manufacturerId; /* Manufacturer ID */ ++ MV_U16 deviceId; /* Device ID */ ++ MV_U32 sectorSize; /* Size of each sector - all the same */ ++ MV_U32 sectorNumber; /* Number of sectors */ ++ MV_U32 pageSize; /* Page size - affect allignment */ ++ MV_U32 index; /* index of the device in the sflash table (internal parameter) */ ++} MV_SFLASH_INFO; ++ ++/* Function Prototypes */ ++/* Init */ ++MV_STATUS mvSFlashInit (MV_SFLASH_INFO * pFlinfo); ++ ++/* erase */ ++MV_STATUS mvSFlashSectorErase (MV_SFLASH_INFO * pFlinfo, MV_U32 secNumber); ++MV_STATUS mvSFlashChipErase (MV_SFLASH_INFO * pFlinfo); ++ ++/* Read */ ++MV_STATUS mvSFlashBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, ++ MV_U8* pReadBuff, MV_U32 buffSize); ++MV_STATUS mvSFlashFastBlockRd (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, ++ MV_U8* pReadBuff, MV_U32 buffSize); ++ ++/* write regardless of the page boundaries and size limit per Page program command */ ++MV_STATUS mvSFlashBlockWr (MV_SFLASH_INFO * pFlinfo, MV_U32 offset, ++ MV_U8* pWriteBuff, MV_U32 buffSize); ++/* Get IDs */ ++MV_STATUS mvSFlashIdGet (MV_SFLASH_INFO * pFlinfo, MV_U8* pManId, MV_U16* pDevId); ++ ++/* Set and Get the Write Protection region - if the Status register is not locked */ ++MV_STATUS mvSFlashWpRegionSet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION wpRegion); ++MV_STATUS mvSFlashWpRegionGet (MV_SFLASH_INFO * pFlinfo, MV_SFLASH_WP_REGION * pWpRegion); ++ ++/* Lock the status register for writing - W/Vpp pin should be low to take effect */ ++MV_STATUS mvSFlashStatRegLock (MV_SFLASH_INFO * pFlinfo, MV_BOOL srLock); ++ ++/* Get the regions sizes */ ++MV_U32 mvSFlashSizeGet (MV_SFLASH_INFO * pFlinfo); ++ ++/* Cause the falsh device to go into power save mode */ ++MV_STATUS mvSFlashPowerSaveEnter(MV_SFLASH_INFO * pFlinfo); ++MV_STATUS mvSFlashPowerSaveExit (MV_SFLASH_INFO * pFlinfo); ++ ++/* Retreive the string with the device manufacturer and model */ ++const MV_8 * mvSFlashModelGet (MV_SFLASH_INFO * pFlinfo); ++ ++#endif /* __INCmvSFlashH */ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlashSpec.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlashSpec.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlashSpec.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/sflash/mvSFlashSpec.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,233 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvSFlashSpecH ++#define __INCmvSFlashSpecH ++ ++/* Constants */ ++#define MV_SFLASH_READ_CMND_LENGTH 4 /* 1B opcode + 3B address */ ++#define MV_SFLASH_SE_CMND_LENGTH 4 /* 1B opcode + 3B address */ ++#define MV_SFLASH_BE_CMND_LENGTH 1 /* 1B opcode */ ++#define MV_SFLASH_PP_CMND_LENGTH 4 /* 1B opcode + 3B address */ ++#define MV_SFLASH_WREN_CMND_LENGTH 1 /* 1B opcode */ ++#define MV_SFLASH_WRDI_CMND_LENGTH 1 /* 1B opcode */ ++#define MV_SFLASH_RDID_CMND_LENGTH 1 /* 1B opcode */ ++#define MV_SFLASH_RDID_REPLY_LENGTH 3 /* 1B manf ID and 2B device ID */ ++#define MV_SFLASH_RDSR_CMND_LENGTH 1 /* 1B opcode */ ++#define MV_SFLASH_RDSR_REPLY_LENGTH 1 /* 1B status */ ++#define MV_SFLASH_WRSR_CMND_LENGTH 2 /* 1B opcode + 1B status value */ ++#define MV_SFLASH_DP_CMND_LENGTH 1 /* 1B opcode */ ++#define MV_SFLASH_RES_CMND_LENGTH 1 /* 1B opcode */ ++ ++/* Status Register Bit Masks */ ++#define MV_SFLASH_STATUS_REG_WIP_OFFSET 0 /* bit 0; write in progress */ ++#define MV_SFLASH_STATUS_REG_WP_OFFSET 2 /* bit 2-4; write protect option */ ++#define MV_SFLASH_STATUS_REG_SRWD_OFFSET 7 /* bit 7; lock status register write */ ++#define MV_SFLASH_STATUS_REG_WIP_MASK (0x1 << MV_SFLASH_STATUS_REG_WIP_OFFSET) ++#define MV_SFLASH_STATUS_REG_SRWD_MASK (0x1 << MV_SFLASH_STATUS_REG_SRWD_OFFSET) ++ ++#define MV_SFLASH_MAX_WAIT_LOOP 1000000 ++#define MV_SFLASH_CHIP_ERASE_MAX_WAIT_LOOP 0x50000000 ++ ++#define MV_SFLASH_DEFAULT_RDID_OPCD 0x9F /* Default Read ID */ ++#define MV_SFLASH_DEFAULT_WREN_OPCD 0x06 /* Default Write Enable */ ++#define MV_SFLASH_NO_SPECIFIC_OPCD 0x00 ++ ++/********************************/ ++/* ST M25Pxxx Device Specific */ ++/********************************/ ++ ++/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ ++#define MV_M25PXXX_ST_MANF_ID 0x20 ++#define MV_M25P32_DEVICE_ID 0x2016 ++#define MV_M25P32_MAX_SPI_FREQ 20000000 /* 20MHz */ ++#define MV_M25P32_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ ++#define MV_M25P32_FAST_READ_DUMMY_BYTES 1 ++#define MV_M25P64_DEVICE_ID 0x2017 ++#define MV_M25P64_MAX_SPI_FREQ 20000000 /* 20MHz */ ++#define MV_M25P64_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ ++#define MV_M25P64_FAST_READ_DUMMY_BYTES 1 ++#define MV_M25P128_DEVICE_ID 0x2018 ++#define MV_M25P128_MAX_SPI_FREQ 20000000 /* 20MHz */ ++#define MV_M25P128_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ ++#define MV_M25P128_FAST_READ_DUMMY_BYTES 1 ++ ++ ++/* Sector Sizes and population per device model*/ ++#define MV_M25P32_SECTOR_SIZE 0x10000 /* 64K */ ++#define MV_M25P64_SECTOR_SIZE 0x10000 /* 64K */ ++#define MV_M25P128_SECTOR_SIZE 0x40000 /* 256K */ ++#define MV_M25P32_SECTOR_NUMBER 64 ++#define MV_M25P64_SECTOR_NUMBER 128 ++#define MV_M25P128_SECTOR_NUMBER 64 ++#define MV_M25P_PAGE_SIZE 0x100 /* 256 byte */ ++ ++#define MV_M25P_WREN_CMND_OPCD 0x06 /* Write Enable */ ++#define MV_M25P_WRDI_CMND_OPCD 0x04 /* Write Disable */ ++#define MV_M25P_RDID_CMND_OPCD 0x9F /* Read ID */ ++#define MV_M25P_RDSR_CMND_OPCD 0x05 /* Read Status Register */ ++#define MV_M25P_WRSR_CMND_OPCD 0x01 /* Write Status Register */ ++#define MV_M25P_READ_CMND_OPCD 0x03 /* Sequential Read */ ++#define MV_M25P_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ ++#define MV_M25P_PP_CMND_OPCD 0x02 /* Page Program */ ++#define MV_M25P_SE_CMND_OPCD 0xD8 /* Sector Erase */ ++#define MV_M25P_BE_CMND_OPCD 0xC7 /* Bulk Erase */ ++#define MV_M25P_RES_CMND_OPCD 0xAB /* Read Electronic Signature */ ++ ++/* Status Register Write Protect Bit Masks - 3bits */ ++#define MV_M25P_STATUS_REG_WP_MASK (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_M25P_STATUS_BP_NONE (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_M25P_STATUS_BP_1_OF_64 (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_M25P_STATUS_BP_1_OF_32 (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_M25P_STATUS_BP_1_OF_16 (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_M25P_STATUS_BP_1_OF_8 (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_M25P_STATUS_BP_1_OF_4 (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_M25P_STATUS_BP_1_OF_2 (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_M25P_STATUS_BP_ALL (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++ ++/************************************/ ++/* MXIC MX25L6405 Device Specific */ ++/************************************/ ++ ++/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ ++#define MV_MXIC_MANF_ID 0xC2 ++#define MV_MX25L6405_DEVICE_ID 0x2017 ++#define MV_MX25L6405_MAX_SPI_FREQ 20000000 /* 20MHz */ ++#define MV_MX25L6405_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ ++#define MV_MX25L6405_FAST_READ_DUMMY_BYTES 1 ++#define MV_MXIC_DP_EXIT_DELAY 30 /* 30 ms */ ++ ++/* Sector Sizes and population per device model*/ ++#define MV_MX25L6405_SECTOR_SIZE 0x10000 /* 64K */ ++#define MV_MX25L6405_SECTOR_NUMBER 128 ++#define MV_MXIC_PAGE_SIZE 0x100 /* 256 byte */ ++ ++#define MV_MX25L_WREN_CMND_OPCD 0x06 /* Write Enable */ ++#define MV_MX25L_WRDI_CMND_OPCD 0x04 /* Write Disable */ ++#define MV_MX25L_RDID_CMND_OPCD 0x9F /* Read ID */ ++#define MV_MX25L_RDSR_CMND_OPCD 0x05 /* Read Status Register */ ++#define MV_MX25L_WRSR_CMND_OPCD 0x01 /* Write Status Register */ ++#define MV_MX25L_READ_CMND_OPCD 0x03 /* Sequential Read */ ++#define MV_MX25L_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ ++#define MV_MX25L_PP_CMND_OPCD 0x02 /* Page Program */ ++#define MV_MX25L_SE_CMND_OPCD 0xD8 /* Sector Erase */ ++#define MV_MX25L_BE_CMND_OPCD 0xC7 /* Bulk Erase */ ++#define MV_MX25L_DP_CMND_OPCD 0xB9 /* Deep Power Down */ ++#define MV_MX25L_RES_CMND_OPCD 0xAB /* Read Electronic Signature */ ++ ++/* Status Register Write Protect Bit Masks - 4bits */ ++#define MV_MX25L_STATUS_REG_WP_MASK (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_MX25L_STATUS_BP_NONE (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_MX25L_STATUS_BP_1_OF_128 (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_MX25L_STATUS_BP_1_OF_64 (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_MX25L_STATUS_BP_1_OF_32 (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_MX25L_STATUS_BP_1_OF_16 (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_MX25L_STATUS_BP_1_OF_8 (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_MX25L_STATUS_BP_1_OF_4 (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_MX25L_STATUS_BP_1_OF_2 (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_MX25L_STATUS_BP_ALL (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) ++ ++/************************************/ ++/* SPANSION S25FL128P Device Specific */ ++/************************************/ ++ ++/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ ++#define MV_SPANSION_MANF_ID 0x01 ++#define MV_S25FL128_DEVICE_ID 0x2018 ++#define MV_S25FL128_MAX_SPI_FREQ 33000000 /* 33MHz */ ++#define MV_S25FL128_MAX_FAST_SPI_FREQ 104000000 /* 104MHz */ ++#define MV_S25FL128_FAST_READ_DUMMY_BYTES 1 ++ ++/* Sector Sizes and population per device model*/ ++#define MV_S25FL128_SECTOR_SIZE 0x40000 /* 256K */ ++#define MV_S25FL128_SECTOR_NUMBER 64 ++#define MV_S25FL_PAGE_SIZE 0x100 /* 256 byte */ ++ ++#define MV_S25FL_WREN_CMND_OPCD 0x06 /* Write Enable */ ++#define MV_S25FL_WRDI_CMND_OPCD 0x04 /* Write Disable */ ++#define MV_S25FL_RDID_CMND_OPCD 0x9F /* Read ID */ ++#define MV_S25FL_RDSR_CMND_OPCD 0x05 /* Read Status Register */ ++#define MV_S25FL_WRSR_CMND_OPCD 0x01 /* Write Status Register */ ++#define MV_S25FL_READ_CMND_OPCD 0x03 /* Sequential Read */ ++#define MV_S25FL_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ ++#define MV_S25FL_PP_CMND_OPCD 0x02 /* Page Program */ ++#define MV_S25FL_SE_CMND_OPCD 0xD8 /* Sector Erase */ ++#define MV_S25FL_BE_CMND_OPCD 0xC7 /* Bulk Erase */ ++#define MV_S25FL_DP_CMND_OPCD 0xB9 /* Deep Power Down */ ++#define MV_S25FL_RES_CMND_OPCD 0xAB /* Read Electronic Signature */ ++ ++/* Status Register Write Protect Bit Masks - 4bits */ ++#define MV_S25FL_STATUS_REG_WP_MASK (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_S25FL_STATUS_BP_NONE (0x00 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_S25FL_STATUS_BP_1_OF_128 (0x01 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_S25FL_STATUS_BP_1_OF_64 (0x02 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_S25FL_STATUS_BP_1_OF_32 (0x03 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_S25FL_STATUS_BP_1_OF_16 (0x04 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_S25FL_STATUS_BP_1_OF_8 (0x05 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_S25FL_STATUS_BP_1_OF_4 (0x06 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_S25FL_STATUS_BP_1_OF_2 (0x07 << MV_SFLASH_STATUS_REG_WP_OFFSET) ++#define MV_S25FL_STATUS_BP_ALL (0x0F << MV_SFLASH_STATUS_REG_WP_OFFSET) ++ ++#endif /* __INCmvSFlashSpecH */ ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvCompVer.txt linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvCompVer.txt +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvCompVer.txt 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvCompVer.txt 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,4 @@ ++Global HAL Version: FEROCEON_HAL_3_1_7 ++Unit HAL Version: 3.1.3 ++Description: This component includes an implementation of the unit HAL drivers ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.c linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.c +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,576 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#include "spi/mvSpi.h" ++#include "spi/mvSpiSpec.h" ++ ++#include "ctrlEnv/mvCtrlEnvLib.h" ++ ++/* #define MV_DEBUG */ ++#ifdef MV_DEBUG ++#define DB(x) x ++#define mvOsPrintf printf ++#else ++#define DB(x) ++#endif ++ ++ ++/******************************************************************************* ++* mvSpi16bitDataTxRx - Transmt and receive data ++* ++* DESCRIPTION: ++* Tx data and block waiting for data to be transmitted ++* ++********************************************************************************/ ++static MV_STATUS mvSpi16bitDataTxRx (MV_U16 txData, MV_U16 * pRxData) ++{ ++ MV_U32 i; ++ MV_BOOL ready = MV_FALSE; ++ ++ /* First clear the bit in the interrupt cause register */ ++ MV_REG_WRITE(MV_SPI_INT_CAUSE_REG, 0x0); ++ ++ /* Transmit data */ ++ MV_REG_WRITE(MV_SPI_DATA_OUT_REG, MV_16BIT_LE(txData)); ++ ++ /* wait with timeout for memory ready */ ++ for (i=0; i> 8) & 0xFF); ++ ++#elif defined(MV_CPU_BE) ++ ++ /* perform the data write to the buffer in two stages with 8bit each */ ++ MV_U8 * bptr = (MV_U8 *)pRxData; ++ MV_U16 data = MV_16BIT_LE(MV_REG_READ(MV_SPI_DATA_IN_REG)); ++ *bptr = ((data >> 8) & 0xFF); ++ ++bptr; ++ *bptr = (data & 0xFF); ++ ++#else ++ #error "CPU endianess isn't defined!\n" ++#endif ++ ++ } ++ else ++ *pRxData = MV_16BIT_LE(MV_REG_READ(MV_SPI_DATA_IN_REG)); ++ } ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvSpi8bitDataTxRx - Transmt and receive data (8bits) ++* ++* DESCRIPTION: ++* Tx data and block waiting for data to be transmitted ++* ++********************************************************************************/ ++static MV_STATUS mvSpi8bitDataTxRx (MV_U8 txData, MV_U8 * pRxData) ++{ ++ MV_U32 i; ++ MV_BOOL ready = MV_FALSE; ++ ++ /* First clear the bit in the interrupt cause register */ ++ MV_REG_WRITE(MV_SPI_INT_CAUSE_REG, 0x0); ++ ++ /* Transmit data */ ++ MV_REG_WRITE(MV_SPI_DATA_OUT_REG, txData); ++ ++ /* wait with timeout for memory ready */ ++ for (i=0; i serialBaudRate) ++ continue; ++ ++ /* check for exact fit */ ++ if ((cpuClk / preScale[i]) == serialBaudRate) ++ { ++ bestPrescaleIndx = i; ++ break; ++ } ++ ++ /* check if this is better than the previous one */ ++ if ((serialBaudRate - (cpuClk / preScale[i])) < minBaudOffset) ++ { ++ minBaudOffset = (serialBaudRate - (cpuClk / preScale[i])); ++ bestPrescaleIndx = i; ++ } ++ } ++ ++ if (bestPrescaleIndx > 14) ++ { ++ mvOsPrintf("%s ERROR: SPI baud rate prescale error!\n", __FUNCTION__); ++ return MV_OUT_OF_RANGE; ++ } ++ ++ /* configure the Prescale */ ++ tempReg = MV_REG_READ(MV_SPI_IF_CONFIG_REG); ++ tempReg = ((tempReg & ~MV_SPI_CLK_PRESCALE_MASK) | (bestPrescaleIndx + 0x12)); ++ MV_REG_WRITE(MV_SPI_IF_CONFIG_REG, tempReg); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvSpiCsAssert - Assert the Chip Select pin indicating a new transfer ++* ++* DESCRIPTION: ++* Assert The chip select - used to select an external SPI device ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Success or Error code. ++* ++********************************************************************************/ ++MV_VOID mvSpiCsAssert(MV_VOID) ++{ ++ /* For devices in which the SPI is muxed on the MPP with other interfaces*/ ++ mvMPPConfigToSPI(); ++ mvOsUDelay(1); ++ MV_REG_BIT_SET(MV_SPI_IF_CTRL_REG, MV_SPI_CS_ENABLE_MASK); ++} ++ ++/******************************************************************************* ++* mvSpiCsDeassert - DeAssert the Chip Select pin indicating the end of a ++* SPI transfer sequence ++* ++* DESCRIPTION: ++* DeAssert the chip select pin ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Success or Error code. ++* ++********************************************************************************/ ++MV_VOID mvSpiCsDeassert(MV_VOID) ++{ ++ MV_REG_BIT_RESET(MV_SPI_IF_CTRL_REG, MV_SPI_CS_ENABLE_MASK); ++ ++ /* For devices in which the SPI is muxed on the MPP with other interfaces*/ ++ mvMPPConfigToDefault(); ++} ++ ++/******************************************************************************* ++* mvSpiRead - Read a buffer over the SPI interface ++* ++* DESCRIPTION: ++* Receive (read) a buffer over the SPI interface in 16bit chunks. If the ++* buffer size is odd, then the last chunk will be 8bits. Chip select is not ++* handled at this level. ++* ++* INPUT: ++* pRxBuff: Pointer to the buffer to hold the received data ++* buffSize: length of the pRxBuff ++* ++* OUTPUT: ++* pRxBuff: Pointer to the buffer with the received data ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSpiRead (MV_U8* pRxBuff, MV_U32 buffSize) ++{ ++ MV_STATUS ret; ++ MV_U32 bytesLeft = buffSize; ++ MV_U16* rxPtr = (MV_U16*)pRxBuff; ++ ++ /* check for null parameters */ ++ if (pRxBuff == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check that the buffer pointer and the buffer size are 16bit aligned */ ++ if ((((MV_U32)buffSize & 1) == 0) && (((MV_U32)pRxBuff & 1) == 0)) ++ { ++ /* Verify that the SPI mode is in 16bit mode */ ++ MV_REG_BIT_SET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); ++ ++ /* TX/RX as long we have complete 16bit chunks */ ++ while (bytesLeft >= MV_SPI_16_BIT_CHUNK_SIZE) ++ { ++ /* Transmitted and wait for the transfer to be completed */ ++ if ((ret = mvSpi16bitDataTxRx(MV_SPI_DUMMY_WRITE_16BITS, rxPtr)) != MV_OK) ++ return ret; ++ ++ /* increment the pointers */ ++ rxPtr++; ++ bytesLeft -= MV_SPI_16_BIT_CHUNK_SIZE; ++ } ++ ++ } ++ else ++ { ++ /* Verify that the SPI mode is in 8bit mode */ ++ MV_REG_BIT_RESET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); ++ ++ /* TX/RX in 8bit chanks */ ++ while (bytesLeft > 0) ++ { ++ /* Transmitted and wait for the transfer to be completed */ ++ if ((ret = mvSpi8bitDataTxRx(MV_SPI_DUMMY_WRITE_8BITS, pRxBuff)) != MV_OK) ++ return ret; ++ /* increment the pointers */ ++ pRxBuff++; ++ bytesLeft--; ++ } ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvSpiWrite - Transmit a buffer over the SPI interface ++* ++* DESCRIPTION: ++* Transmit a buffer over the SPI interface in 16bit chunks. If the ++* buffer size is odd, then the last chunk will be 8bits. No chip select ++* action is taken. ++* ++* INPUT: ++* pTxBuff: Pointer to the buffer holding the TX data ++* buffSize: length of the pTxBuff ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSpiWrite(MV_U8* pTxBuff, MV_U32 buffSize) ++{ ++ MV_STATUS ret; ++ MV_U32 bytesLeft = buffSize; ++ MV_U16* txPtr = (MV_U16*)pTxBuff; ++ ++ /* check for null parameters */ ++ if (pTxBuff == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check that the buffer pointer and the buffer size are 16bit aligned */ ++ if ((((MV_U32)buffSize & 1) == 0) && (((MV_U32)pTxBuff & 1) == 0)) ++ { ++ /* Verify that the SPI mode is in 16bit mode */ ++ MV_REG_BIT_SET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); ++ ++ /* TX/RX as long we have complete 16bit chunks */ ++ while (bytesLeft >= MV_SPI_16_BIT_CHUNK_SIZE) ++ { ++ /* Transmitted and wait for the transfer to be completed */ ++ if ((ret = mvSpi16bitDataTxRx(*txPtr, NULL)) != MV_OK) ++ return ret; ++ ++ /* increment the pointers */ ++ txPtr++; ++ bytesLeft -= MV_SPI_16_BIT_CHUNK_SIZE; ++ } ++ } ++ else ++ { ++ ++ /* Verify that the SPI mode is in 8bit mode */ ++ MV_REG_BIT_RESET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); ++ ++ /* TX/RX in 8bit chanks */ ++ while (bytesLeft > 0) ++ { ++ /* Transmitted and wait for the transfer to be completed */ ++ if ((ret = mvSpi8bitDataTxRx(*pTxBuff, NULL)) != MV_OK) ++ return ret; ++ ++ /* increment the pointers */ ++ pTxBuff++; ++ bytesLeft--; ++ } ++ } ++ ++ return MV_OK; ++} ++ ++ ++/******************************************************************************* ++* mvSpiReadWrite - Read and Write a buffer simultanuosely ++* ++* DESCRIPTION: ++* Transmit and receive a buffer over the SPI in 16bit chunks. If the ++* buffer size is odd, then the last chunk will be 8bits. The SPI chip ++* select is not handled implicitely. ++* ++* INPUT: ++* pRxBuff: Pointer to the buffer to write the RX info in ++* pTxBuff: Pointer to the buffer holding the TX info ++* buffSize: length of both the pTxBuff and pRxBuff ++* ++* OUTPUT: ++* pRxBuff: Pointer of the buffer holding the RX data ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSpiReadWrite(MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize) ++{ ++ MV_STATUS ret; ++ MV_U32 bytesLeft = buffSize; ++ MV_U16* txPtr = (MV_U16*)pTxBuff; ++ MV_U16* rxPtr = (MV_U16*)pRxBuff; ++ ++ /* check for null parameters */ ++ if ((pRxBuff == NULL) || (pTxBuff == NULL)) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* Check that the buffer pointer and the buffer size are 16bit aligned */ ++ if ((((MV_U32)buffSize & 1) == 0) && (((MV_U32)pTxBuff & 1) == 0) && (((MV_U32)pRxBuff & 1) == 0)) ++ { ++ /* Verify that the SPI mode is in 16bit mode */ ++ MV_REG_BIT_SET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); ++ ++ /* TX/RX as long we have complete 16bit chunks */ ++ while (bytesLeft >= MV_SPI_16_BIT_CHUNK_SIZE) ++ { ++ /* Transmitted and wait for the transfer to be completed */ ++ if ((ret = mvSpi16bitDataTxRx(*txPtr, rxPtr)) != MV_OK) ++ return ret; ++ ++ /* increment the pointers */ ++ txPtr++; ++ rxPtr++; ++ bytesLeft -= MV_SPI_16_BIT_CHUNK_SIZE; ++ } ++ } ++ else ++ { ++ /* Verify that the SPI mode is in 8bit mode */ ++ MV_REG_BIT_RESET(MV_SPI_IF_CONFIG_REG, MV_SPI_BYTE_LENGTH_MASK); ++ ++ /* TX/RX in 8bit chanks */ ++ while (bytesLeft > 0) ++ { ++ /* Transmitted and wait for the transfer to be completed */ ++ if ( (ret = mvSpi8bitDataTxRx(*pTxBuff, pRxBuff) ) != MV_OK) ++ return ret; ++ pRxBuff++; ++ pTxBuff++; ++ bytesLeft--; ++ } ++ } ++ ++ return MV_OK; ++} ++ ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpi.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,94 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvSpihH ++#define __INCmvSpihH ++ ++#include "mvCommon.h" ++#include "mvOs.h" ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++ ++/* Function Prototypes */ ++/* Init */ ++MV_STATUS mvSpiInit (MV_U32 serialBaudRate); ++ ++/* Set the Frequency of the Spi clock */ ++MV_STATUS mvSpiBaudRateSet(MV_U32 serialBaudRate); ++ ++/* Assert the SPI chip select */ ++MV_VOID mvSpiCsAssert (MV_VOID); ++ ++/* De-assert the SPI chip select */ ++MV_VOID mvSpiCsDeassert (MV_VOID); ++ ++/* Simultanuous Read and write */ ++MV_STATUS mvSpiReadWrite (MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize); ++ ++/* serialize a buffer on the TX line - Rx is ignored */ ++MV_STATUS mvSpiWrite (MV_U8* pTxBuff, MV_U32 buffSize); ++ ++/* read from the RX line by writing dummy values to the TX line */ ++MV_STATUS mvSpiRead (MV_U8* pRxBuff, MV_U32 buffSize); ++ ++#endif /* __INCmvSpihH */ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.c linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.c +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,249 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#include "spi/mvSpi.h" ++#include "spi/mvSpiSpec.h" ++ ++/*#define MV_DEBUG*/ ++#ifdef MV_DEBUG ++#define DB(x) x ++#else ++#define DB(x) ++#endif ++ ++ ++/******************************************************************************* ++* mvSpiReadAndWrite - Read and Write a buffer simultanuousely ++* ++* DESCRIPTION: ++* Transmit and receive a buffer over the SPI in 16bit chunks. If the ++* buffer size is odd, then the last chunk will be 8bits. ++* ++* INPUT: ++* pRxBuff: Pointer to the buffer to write the RX info in ++* pTxBuff: Pointer to the buffer holding the TX info ++* buffSize: length of both the pTxBuff and pRxBuff ++* ++* OUTPUT: ++* pRxBuff: Pointer of the buffer holding the RX data ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSpiReadAndWrite(MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize) ++{ ++ MV_STATUS ret; ++ ++ /* check for null parameters */ ++ if ((pRxBuff == NULL) || (pTxBuff == NULL) || (buffSize == 0)) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* First assert the chip select */ ++ mvSpiCsAssert(); ++ ++ ret = mvSpiReadWrite(pRxBuff, pTxBuff, buffSize); ++ ++ /* Finally deassert the chip select */ ++ mvSpiCsDeassert(); ++ ++ return ret; ++} ++ ++/******************************************************************************* ++* mvSpiWriteThenWrite - Serialize a command followed by the data over the TX line ++* ++* DESCRIPTION: ++* Assert the chip select line. Transmit the command buffer followed by ++* the data buffer. Then deassert the CS line. ++* ++* INPUT: ++* pCmndBuff: Pointer to the command buffer to transmit ++* cmndSize: length of the command size ++* pTxDataBuff: Pointer to the data buffer to transmit ++* txDataSize: length of the data buffer ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSpiWriteThenWrite (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pTxDataBuff, ++ MV_U32 txDataSize) ++{ ++ MV_STATUS ret = MV_OK, tempRet; ++ ++ /* check for null parameters */ ++#ifndef CONFIG_MARVELL ++ if(NULL == pTxDataBuff) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++#endif ++ ++ if (pCmndBuff == NULL) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* First assert the chip select */ ++ mvSpiCsAssert(); ++ ++ /* first write the command */ ++ if ((cmndSize) && (pCmndBuff != NULL)) ++ { ++ if ((tempRet = mvSpiWrite(pCmndBuff, cmndSize)) != MV_OK) ++ ret = tempRet; ++ } ++ ++ /* Then write the data buffer */ ++#ifndef CONFIG_MARVELL ++ if (txDataSize) ++#else ++ if ((txDataSize) && (pTxDataBuff != NULL)) ++#endif ++ { ++ if ((tempRet = mvSpiWrite(pTxDataBuff, txDataSize)) != MV_OK) ++ ret = tempRet; ++ } ++ ++ /* Finally deassert the chip select */ ++ mvSpiCsDeassert(); ++ ++ return ret; ++} ++ ++/******************************************************************************* ++* mvSpiWriteThenRead - Serialize a command then read a data buffer ++* ++* DESCRIPTION: ++* Assert the chip select line. Transmit the command buffer then read ++* the data buffer. Then deassert the CS line. ++* ++* INPUT: ++* pCmndBuff: Pointer to the command buffer to transmit ++* cmndSize: length of the command size ++* pRxDataBuff: Pointer to the buffer to read the data in ++* txDataSize: length of the data buffer ++* ++* OUTPUT: ++* pRxDataBuff: Pointer to the buffer holding the data ++* ++* RETURN: ++* Success or Error code. ++* ++* ++*******************************************************************************/ ++MV_STATUS mvSpiWriteThenRead (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pRxDataBuff, ++ MV_U32 rxDataSize,MV_U32 dummyBytesToRead) ++{ ++ MV_STATUS ret = MV_OK, tempRet; ++ MV_U8 dummyByte; ++ ++ /* check for null parameters */ ++ if ((pCmndBuff == NULL) && (pRxDataBuff == NULL)) ++ { ++ mvOsPrintf("%s ERROR: Null pointer parameter!\n", __FUNCTION__); ++ return MV_BAD_PARAM; ++ } ++ ++ /* First assert the chip select */ ++ mvSpiCsAssert(); ++ ++ /* first write the command */ ++ if ((cmndSize) && (pCmndBuff != NULL)) ++ { ++ if ((tempRet = mvSpiWrite(pCmndBuff, cmndSize)) != MV_OK) ++ ret = tempRet; ++ } ++ ++ /* Read dummy bytes before real data. */ ++ while(dummyBytesToRead) ++ { ++ mvSpiRead(&dummyByte,1); ++ dummyBytesToRead--; ++ } ++ ++ /* Then write the data buffer */ ++ if ((rxDataSize) && (pRxDataBuff != NULL)) ++ { ++ if ((tempRet = mvSpiRead(pRxDataBuff, rxDataSize)) != MV_OK) ++ ret = tempRet; ++ } ++ ++ /* Finally deassert the chip select */ ++ mvSpiCsDeassert(); ++ ++ return ret; ++} ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiCmnd.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,82 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvSpiCmndhH ++#define __INCmvSpiCmndhH ++ ++#include "mvTypes.h" ++ ++/* Function Prototypes */ ++ ++/* Simultanuous Read and write */ ++MV_STATUS mvSpiReadAndWrite (MV_U8* pRxBuff, MV_U8* pTxBuff, MV_U32 buffSize); ++ ++/* write command - write a command and then write data */ ++MV_STATUS mvSpiWriteThenWrite (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pTxDataBuff, MV_U32 txDataSize); ++ ++/* read command - write a command and then read data by writing dummy data */ ++MV_STATUS mvSpiWriteThenRead (MV_U8* pCmndBuff, MV_U32 cmndSize, MV_U8* pRxDataBuff, ++ MV_U32 rxDataSize,MV_U32 dummyBytesToRead); ++ ++#endif /* __INCmvSpiCmndhH */ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiSpec.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiSpec.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiSpec.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/spi/mvSpiSpec.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,98 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++#ifndef __INCmvSpiSpecH ++#define __INCmvSpiSpecH ++ ++/* Constants */ ++#define MV_SPI_WAIT_RDY_MAX_LOOP 100000 ++#define MV_SPI_16_BIT_CHUNK_SIZE 2 ++#define MV_SPI_DUMMY_WRITE_16BITS 0xFFFF ++#define MV_SPI_DUMMY_WRITE_8BITS 0xFF ++ ++/* Marvell Flash Device Controller Registers */ ++#define MV_SPI_CTRLR_OFST 0x10600 ++#define MV_SPI_IF_CTRL_REG (MV_SPI_CTRLR_OFST + 0x00) ++#define MV_SPI_IF_CONFIG_REG (MV_SPI_CTRLR_OFST + 0x04) ++#define MV_SPI_DATA_OUT_REG (MV_SPI_CTRLR_OFST + 0x08) ++#define MV_SPI_DATA_IN_REG (MV_SPI_CTRLR_OFST + 0x0c) ++#define MV_SPI_INT_CAUSE_REG (MV_SPI_CTRLR_OFST + 0x10) ++#define MV_SPI_INT_CAUSE_MASK_REG (MV_SPI_CTRLR_OFST + 0x14) ++ ++/* Serial Memory Interface Control Register Masks */ ++#define MV_SPI_CS_ENABLE_OFFSET 0 /* bit 0 */ ++#define MV_SPI_MEMORY_READY_OFFSET 1 /* bit 1 */ ++#define MV_SPI_CS_ENABLE_MASK (0x1 << MV_SPI_CS_ENABLE_OFFSET) ++#define MV_SPI_MEMORY_READY_MASK (0x1 << MV_SPI_MEMORY_READY_OFFSET) ++ ++/* Serial Memory Interface Configuration Register Masks */ ++#define MV_SPI_CLK_PRESCALE_OFFSET 0 /* bit 0-4 */ ++#define MV_SPI_BYTE_LENGTH_OFFSET 5 /* bit 5 */ ++#define MV_SPI_ADDRESS_BURST_LENGTH_OFFSET 8 /* bit 8-9 */ ++#define MV_SPI_CLK_PRESCALE_MASK (0x1F << MV_SPI_CLK_PRESCALE_OFFSET) ++#define MV_SPI_BYTE_LENGTH_MASK (0x1 << MV_SPI_BYTE_LENGTH_OFFSET) ++#define MV_SPI_ADDRESS_BURST_LENGTH_MASK (0x3 << MV_SPI_ADDRESS_BURST_LENGTH_OFFSET) ++ ++#endif /* __INCmvSpiSpecH */ ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvCompVer.txt linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvCompVer.txt +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvCompVer.txt 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvCompVer.txt 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,4 @@ ++Global HAL Version: FEROCEON_HAL_3_1_7 ++Unit HAL Version: 3.1.5 ++Description: This component includes an implementation of the unit HAL drivers ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.c linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.c +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,1023 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++#include "mvTwsi.h" ++#include "mvTwsiSpec.h" ++#include "cpu/mvCpu.h" ++ ++ ++/*#define MV_DEBUG*/ ++#ifdef MV_DEBUG ++#define DB(x) x ++#else ++#define DB(x) ++#endif ++ ++static MV_VOID twsiIntFlgClr(MV_U8 chanNum); ++static MV_BOOL twsiMainIntGet(MV_U8 chanNum); ++static MV_VOID twsiAckBitSet(MV_U8 chanNum); ++static MV_U32 twsiStsGet(MV_U8 chanNum); ++static MV_VOID twsiReset(MV_U8 chanNum); ++static MV_STATUS twsiAddr7BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command); ++static MV_STATUS twsiAddr10BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command); ++static MV_STATUS twsiDataTransmit(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize); ++static MV_STATUS twsiDataReceive(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize); ++static MV_STATUS twsiTargetOffsSet(MV_U8 chanNum, MV_U32 offset,MV_BOOL moreThen256); ++ ++ ++static MV_BOOL twsiTimeoutChk(MV_U32 timeout, const MV_8 *pString) ++{ ++ if(timeout >= TWSI_TIMEOUT_VALUE) ++ { ++ DB(mvOsPrintf("%s",pString)); ++ return MV_TRUE; ++ } ++ return MV_FALSE; ++ ++} ++/******************************************************************************* ++* mvTwsiStartBitSet - Set start bit on the bus ++* ++* DESCRIPTION: ++* This routine sets the start bit on the TWSI bus. ++* The routine first checks for interrupt flag condition, then it sets ++* the start bit in the TWSI Control register. ++* If the interrupt flag condition check previously was set, the function ++* will clear it. ++* The function then wait for the start bit to be cleared by the HW. ++* Then it waits for the interrupt flag to be set and eventually, the ++* TWSI status is checked to be 0x8 or 0x10(repeated start bit). ++* ++* INPUT: ++* chanNum - TWSI channel. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_OK is start bit was set successfuly on the bus. ++* MV_FAIL if interrupt flag was set before setting start bit. ++* ++*******************************************************************************/ ++MV_STATUS mvTwsiStartBitSet(MV_U8 chanNum) ++{ ++ MV_BOOL isIntFlag = MV_FALSE; ++ MV_U32 timeout, temp; ++ ++ DB(mvOsPrintf("TWSI: mvTwsiStartBitSet \n")); ++ /* check Int flag */ ++ if(twsiMainIntGet(chanNum)) ++ isIntFlag = MV_TRUE; ++ /* set start Bit */ ++ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); ++ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp | TWSI_CONTROL_START_BIT); ++ ++ /* in case that the int flag was set before i.e. repeated start bit */ ++ if(isIntFlag){ ++ DB(mvOsPrintf("TWSI: mvTwsiStartBitSet repeated start Bit\n")); ++ twsiIntFlgClr(chanNum); ++ } ++ ++ /* wait for interrupt */ ++ timeout = 0; ++ while(!twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); ++ ++ /* check for timeout */ ++ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: mvTwsiStartBitSet ERROR - Start Clear bit TimeOut .\n")) ++ return MV_TIMEOUT; ++ ++ ++ /* check that start bit went down */ ++ if((MV_REG_READ(TWSI_CONTROL_REG(chanNum)) & TWSI_CONTROL_START_BIT) != 0) ++ { ++ mvOsPrintf("TWSI: mvTwsiStartBitSet ERROR - start bit didn't went down\n"); ++ return MV_FAIL; ++ } ++ ++ /* check the status */ ++ temp = twsiStsGet(chanNum); ++ if(( temp != TWSI_START_CON_TRA ) && ( temp != TWSI_REPEATED_START_CON_TRA )) ++ { ++ mvOsPrintf("TWSI: mvTwsiStartBitSet ERROR - status %x after Set Start Bit. \n",temp); ++ return MV_FAIL; ++ } ++ ++ return MV_OK; ++ ++} ++ ++/******************************************************************************* ++* mvTwsiStopBitSet - Set stop bit on the bus ++* ++* DESCRIPTION: ++* This routine set the stop bit on the TWSI bus. ++* The function then wait for the stop bit to be cleared by the HW. ++* Finally the function checks for status of 0xF8. ++* ++* INPUT: ++* chanNum - TWSI channel ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE is stop bit was set successfuly on the bus. ++* ++*******************************************************************************/ ++MV_STATUS mvTwsiStopBitSet(MV_U8 chanNum) ++{ ++ MV_U32 timeout, temp; ++ ++ /* Generate stop bit */ ++ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); ++ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp | TWSI_CONTROL_STOP_BIT); ++ ++ twsiIntFlgClr(chanNum); ++ ++ /* wait for stop bit to come down */ ++ timeout = 0; ++ while( ((MV_REG_READ(TWSI_CONTROL_REG(chanNum)) & TWSI_CONTROL_STOP_BIT) != 0) && (timeout++ < TWSI_TIMEOUT_VALUE)); ++ ++ /* check for timeout */ ++ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: mvTwsiStopBitSet ERROR - Stop bit TimeOut .\n")) ++ return MV_TIMEOUT; ++ ++ /* check that the stop bit went down */ ++ if((MV_REG_READ(TWSI_CONTROL_REG(chanNum)) & TWSI_CONTROL_STOP_BIT) != 0) ++ { ++ mvOsPrintf("TWSI: mvTwsiStopBitSet ERROR - stop bit didn't went down. \n"); ++ return MV_FAIL; ++ } ++ ++ /* check the status */ ++ temp = twsiStsGet(chanNum); ++ if( temp != TWSI_NO_REL_STS_INT_FLAG_IS_KEPT_0){ ++ mvOsPrintf("TWSI: mvTwsiStopBitSet ERROR - status %x after Stop Bit. \n", temp); ++ return MV_FAIL; ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* twsiMainIntGet - Get twsi bit from main Interrupt cause. ++* ++* DESCRIPTION: ++* This routine returns the twsi interrupt flag value. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_TRUE is interrupt flag is set, MV_FALSE otherwise. ++* ++*******************************************************************************/ ++static MV_BOOL twsiMainIntGet(MV_U8 chanNum) ++{ ++ MV_U32 temp; ++ ++ /* get the int flag bit */ ++ ++ temp = MV_REG_READ(TWSI_CPU_MAIN_INT_CAUSE_REG); ++ if (temp & (TWSI0_CPU_MAIN_INT_BIT << chanNum)) ++ return MV_TRUE; ++ ++ return MV_FALSE; ++} ++/******************************************************************************* ++* twsiIntFlgClr - Clear Interrupt flag. ++* ++* DESCRIPTION: ++* This routine clears the interrupt flag. It does NOT poll the interrupt ++* to make sure the clear. After clearing the interrupt, it waits for at ++* least 1 miliseconds. ++* ++* INPUT: ++* chanNum - TWSI channel ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++static MV_VOID twsiIntFlgClr(MV_U8 chanNum) ++{ ++ MV_U32 temp; ++ ++ /* wait for 1 mili to prevent TWSI register write after write problems */ ++ mvOsDelay(1); ++ /* clear the int flag bit */ ++ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); ++ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum),temp & ~(TWSI_CONTROL_INT_FLAG_SET)); ++ ++ /* wait for 1 mili sec for the clear to take effect */ ++ mvOsDelay(1); ++ ++ return; ++} ++ ++ ++/******************************************************************************* ++* twsiAckBitSet - Set acknowledge bit on the bus ++* ++* DESCRIPTION: ++* This routine set the acknowledge bit on the TWSI bus. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++static MV_VOID twsiAckBitSet(MV_U8 chanNum) ++{ ++ MV_U32 temp; ++ ++ /*Set the Ack bit */ ++ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); ++ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp | TWSI_CONTROL_ACK); ++ ++ /* Add delay of 1ms */ ++ mvOsDelay(1); ++ return; ++} ++ ++ ++/******************************************************************************* ++* twsiInit - Initialize TWSI interface ++* ++* DESCRIPTION: ++* This routine: ++* -Reset the TWSI. ++* -Initialize the TWSI clock baud rate according to given frequancy ++* parameter based on Tclk frequancy and enables TWSI slave. ++* -Set the ack bit. ++* -Assign the TWSI slave address according to the TWSI address Type. ++* ++* ++* INPUT: ++* chanNum - TWSI channel ++* frequancy - TWSI frequancy in KHz. (up to 100KHZ) ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* Actual frequancy. ++* ++*******************************************************************************/ ++MV_U32 mvTwsiInit(MV_U8 chanNum, MV_HZ frequancy, MV_U32 Tclk, MV_TWSI_ADDR *pTwsiAddr, MV_BOOL generalCallEnable) ++{ ++ MV_U32 n,m,freq,margin,minMargin = 0xffffffff; ++ MV_U32 power; ++ MV_U32 actualFreq = 0,actualN = 0,actualM = 0,val; ++ ++ if(frequancy > 100000) ++ { ++ mvOsPrintf("Warning TWSI frequancy is too high, please use up tp 100Khz. \n"); ++ } ++ ++ DB(mvOsPrintf("TWSI: mvTwsiInit - Tclk = %d freq = %d\n",Tclk,frequancy)); ++ /* Calucalte N and M for the TWSI clock baud rate */ ++ for(n = 0 ; n < 8 ; n++) ++ { ++ for(m = 0 ; m < 16 ; m++) ++ { ++ power = 2 << n; /* power = 2^(n+1) */ ++ freq = Tclk/(10*(m+1)*power); ++ margin = MV_ABS(frequancy - freq); ++ if(margin < minMargin) ++ { ++ minMargin = margin; ++ actualFreq = freq; ++ actualN = n; ++ actualM = m; ++ } ++ } ++ } ++ DB(mvOsPrintf("TWSI: mvTwsiInit - actN %d actM %d actFreq %d\n",actualN , actualM, actualFreq)); ++ /* Reset the TWSI logic */ ++ twsiReset(chanNum); ++ ++ /* Set the baud rate */ ++ val = ((actualM<< TWSI_BAUD_RATE_M_OFFS) | actualN << TWSI_BAUD_RATE_N_OFFS); ++ MV_REG_WRITE(TWSI_STATUS_BAUDE_RATE_REG(chanNum),val); ++ ++ /* Enable the TWSI and slave */ ++ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), TWSI_CONTROL_ENA | TWSI_CONTROL_ACK); ++ ++ /* set the TWSI slave address */ ++ if( pTwsiAddr->type == ADDR10_BIT )/* 10 Bit deviceAddress */ ++ { ++ /* writing the 2 most significant bits of the 10 bit address*/ ++ val = ((pTwsiAddr->address & TWSI_SLAVE_ADDR_10BIT_MASK) >> TWSI_SLAVE_ADDR_10BIT_OFFS ); ++ /* bits 7:3 must be 0x11110 */ ++ val |= TWSI_SLAVE_ADDR_10BIT_CONST; ++ /* set GCE bit */ ++ if(generalCallEnable) ++ val |= TWSI_SLAVE_ADDR_GCE_ENA; ++ /* write slave address */ ++ MV_REG_WRITE(TWSI_SLAVE_ADDR_REG(chanNum),val); ++ ++ /* writing the 8 least significant bits of the 10 bit address*/ ++ val = (pTwsiAddr->address << TWSI_EXTENDED_SLAVE_OFFS) & TWSI_EXTENDED_SLAVE_MASK; ++ MV_REG_WRITE(TWSI_EXTENDED_SLAVE_ADDR_REG(chanNum), val); ++ } ++ else /*7 bit address*/ ++ { ++ /* set the 7 Bits address */ ++ MV_REG_WRITE(TWSI_EXTENDED_SLAVE_ADDR_REG(chanNum),0x0); ++ val = (pTwsiAddr->address << TWSI_SLAVE_ADDR_7BIT_OFFS) & TWSI_SLAVE_ADDR_7BIT_MASK; ++ MV_REG_WRITE(TWSI_SLAVE_ADDR_REG(chanNum), val); ++ } ++ ++ /* unmask twsi int */ ++ val = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); ++ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), val | TWSI_CONTROL_INT_ENA); ++ /* Add delay of 1ms */ ++ mvOsDelay(1); ++ ++ return actualFreq; ++} ++ ++ ++/******************************************************************************* ++* twsiStsGet - Get the TWSI status value. ++* ++* DESCRIPTION: ++* This routine returns the TWSI status value. ++* ++* INPUT: ++* chanNum - TWSI channel ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_U32 - the TWSI status. ++* ++*******************************************************************************/ ++static MV_U32 twsiStsGet(MV_U8 chanNum) ++{ ++ return MV_REG_READ(TWSI_STATUS_BAUDE_RATE_REG(chanNum)); ++ ++} ++ ++/******************************************************************************* ++* twsiReset - Reset the TWSI. ++* ++* DESCRIPTION: ++* Resets the TWSI logic and sets all TWSI registers to their reset values. ++* ++* INPUT: ++* chanNum - TWSI channel ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None ++* ++*******************************************************************************/ ++static MV_VOID twsiReset(MV_U8 chanNum) ++{ ++ /* Reset the TWSI logic */ ++ MV_REG_WRITE(TWSI_SOFT_RESET_REG(chanNum),0); ++ ++ /* wait for 2 mili sec */ ++ mvOsDelay(2); ++ ++ return; ++} ++ ++ ++ ++ ++/******************************* POLICY ****************************************/ ++ ++ ++ ++/******************************************************************************* ++* mvTwsiAddrSet - Set address on TWSI bus. ++* ++* DESCRIPTION: ++* This function Set address (7 or 10 Bit address) on the Twsi Bus. ++* ++* INPUT: ++* chanNum - TWSI channel ++* pTwsiAddr - twsi address. ++* command - read / write . ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_OK - if setting the address completed succesfully. ++* MV_FAIL otherwmise. ++* ++*******************************************************************************/ ++MV_STATUS mvTwsiAddrSet(MV_U8 chanNum, MV_TWSI_ADDR *pTwsiAddr, MV_TWSI_CMD command) ++{ ++ DB(mvOsPrintf("TWSI: mvTwsiAddr7BitSet addr %x , type %d, cmd is %s\n",pTwsiAddr->address,\ ++ pTwsiAddr->type, ((command==MV_TWSI_WRITE)?"Write":"Read") )); ++ /* 10 Bit address */ ++ if(pTwsiAddr->type == ADDR10_BIT) ++ { ++ return twsiAddr10BitSet(chanNum, pTwsiAddr->address,command); ++ } ++ /* 7 Bit address */ ++ else ++ { ++ return twsiAddr7BitSet(chanNum, pTwsiAddr->address,command); ++ } ++ ++} ++ ++/******************************************************************************* ++* twsiAddr10BitSet - Set 10 Bit address on TWSI bus. ++* ++* DESCRIPTION: ++* There are two address phases: ++* 1) Write '11110' to data register bits [7:3] and 10-bit address MSB ++* (bits [9:8]) to data register bits [2:1] plus a write(0) or read(1) bit ++* to the Data register. Then it clears interrupt flag which drive ++* the address on the TWSI bus. The function then waits for interrupt ++* flag to be active and status 0x18 (write) or 0x40 (read) to be set. ++* 2) write the rest of 10-bit address to data register and clears ++* interrupt flag which drive the address on the TWSI bus. The ++* function then waits for interrupt flag to be active and status ++* 0xD0 (write) or 0xE0 (read) to be set. ++* ++* INPUT: ++* chanNum - TWSI channel ++* deviceAddress - twsi address. ++* command - read / write . ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_OK - if setting the address completed succesfully. ++* MV_FAIL otherwmise. ++* ++*******************************************************************************/ ++static MV_STATUS twsiAddr10BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command) ++{ ++ MV_U32 val,timeout; ++ ++ /* writing the 2 most significant bits of the 10 bit address*/ ++ val = ((deviceAddress & TWSI_DATA_ADDR_10BIT_MASK) >> TWSI_DATA_ADDR_10BIT_OFFS ); ++ /* bits 7:3 must be 0x11110 */ ++ val |= TWSI_DATA_ADDR_10BIT_CONST; ++ /* set command */ ++ val |= command; ++ MV_REG_WRITE(TWSI_DATA_REG(chanNum), val); ++ /* WA add a delay */ ++ mvOsDelay(1); ++ ++ /* clear Int flag */ ++ twsiIntFlgClr(chanNum); ++ ++ /* wait for Int to be Set */ ++ timeout = 0; ++ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); ++ ++ /* check for timeout */ ++ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiAddr10BitSet ERROR - 1st addr (10Bit) Int TimeOut.\n")) ++ return MV_TIMEOUT; ++ ++ /* check the status */ ++ val = twsiStsGet(chanNum); ++ if(( (val != TWSI_AD_PLS_RD_BIT_TRA_ACK_REC) && (command == MV_TWSI_READ ) ) || ++ ( (val != TWSI_AD_PLS_WR_BIT_TRA_ACK_REC) && (command == MV_TWSI_WRITE) )) ++ { ++ mvOsPrintf("TWSI: twsiAddr10BitSet ERROR - status %x 1st addr (10 Bit) in %s mode.\n"\ ++ ,val, ((command==MV_TWSI_WRITE)?"Write":"Read") ); ++ return MV_FAIL; ++ } ++ ++ /* set 8 LSB of the address */ ++ val = (deviceAddress << TWSI_DATA_ADDR_7BIT_OFFS) & TWSI_DATA_ADDR_7BIT_MASK; ++ MV_REG_WRITE(TWSI_DATA_REG(chanNum), val); ++ ++ /* clear Int flag */ ++ twsiIntFlgClr(chanNum); ++ ++ /* wait for Int to be Set */ ++ timeout = 0; ++ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); ++ ++ /* check for timeout */ ++ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiAddr10BitSet ERROR - 2nd (10 Bit) Int TimOut.\n")) ++ return MV_TIMEOUT; ++ ++ /* check the status */ ++ val = twsiStsGet(chanNum); ++ if(( (val != TWSI_SEC_AD_PLS_RD_BIT_TRA_ACK_REC) && (command == MV_TWSI_READ ) ) || ++ ( (val != TWSI_SEC_AD_PLS_WR_BIT_TRA_ACK_REC) && (command == MV_TWSI_WRITE) )) ++ { ++ mvOsPrintf("TWSI: twsiAddr10BitSet ERROR - status %x 2nd addr(10 Bit) in %s mode.\n"\ ++ ,val, ((command==MV_TWSI_WRITE)?"Write":"Read") ); ++ return MV_FAIL; ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* twsiAddr7BitSet - Set 7 Bit address on TWSI bus. ++* ++* DESCRIPTION: ++* This function writes 7 bit address plus a write or read bit to the ++* Data register. Then it clears interrupt flag which drive the address on ++* the TWSI bus. The function then waits for interrupt flag to be active ++* and status 0x18 (write) or 0x40 (read) to be set. ++* ++* INPUT: ++* chanNum - TWSI channel ++* deviceAddress - twsi address. ++* command - read / write . ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_OK - if setting the address completed succesfully. ++* MV_FAIL otherwmise. ++* ++*******************************************************************************/ ++static MV_STATUS twsiAddr7BitSet(MV_U8 chanNum, MV_U32 deviceAddress,MV_TWSI_CMD command) ++{ ++ MV_U32 val,timeout; ++ ++ /* set the address */ ++ val = (deviceAddress << TWSI_DATA_ADDR_7BIT_OFFS) & TWSI_DATA_ADDR_7BIT_MASK; ++ /* set command */ ++ val |= command; ++ MV_REG_WRITE(TWSI_DATA_REG(chanNum), val); ++ /* WA add a delay */ ++ mvOsDelay(1); ++ ++ /* clear Int flag */ ++ twsiIntFlgClr(chanNum); ++ ++ /* wait for Int to be Set */ ++ timeout = 0; ++ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); ++ ++ /* check for timeout */ ++ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiAddr7BitSet ERROR - Addr (7 Bit) int TimeOut.\n")) ++ return MV_TIMEOUT; ++ ++ /* check the status */ ++ val = twsiStsGet(chanNum); ++ if(( (val != TWSI_AD_PLS_RD_BIT_TRA_ACK_REC) && (command == MV_TWSI_READ ) ) || ++ ( (val != TWSI_AD_PLS_WR_BIT_TRA_ACK_REC) && (command == MV_TWSI_WRITE) )) ++ { ++ /* only in debug, since in boot we try to read the SPD of both DRAM, and we don't ++ want error messeges in case DIMM doesn't exist. */ ++ DB(mvOsPrintf("TWSI: twsiAddr7BitSet ERROR - status %x addr (7 Bit) in %s mode.\n"\ ++ ,val,((command==MV_TWSI_WRITE)?"Write":"Read") )); ++ return MV_FAIL; ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* twsiDataWrite - Trnasmit a data block over TWSI bus. ++* ++* DESCRIPTION: ++* This function writes a given data block to TWSI bus in 8 bit granularity. ++* first The function waits for interrupt flag to be active then ++* For each 8-bit data: ++* The function writes data to data register. It then clears ++* interrupt flag which drives the data on the TWSI bus. ++* The function then waits for interrupt flag to be active and status ++* 0x28 to be set. ++* ++* ++* INPUT: ++* chanNum - TWSI channel ++* pBlock - Data block. ++* blockSize - number of chars in pBlock. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_OK - if transmiting the block completed succesfully, ++* MV_BAD_PARAM - if pBlock is NULL, ++* MV_FAIL otherwmise. ++* ++*******************************************************************************/ ++static MV_STATUS twsiDataTransmit(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize) ++{ ++ MV_U32 timeout, temp, blockSizeWr = blockSize; ++ ++ if(NULL == pBlock) ++ return MV_BAD_PARAM; ++ ++ /* wait for Int to be Set */ ++ timeout = 0; ++ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); ++ ++ /* check for timeout */ ++ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataTransmit ERROR - Read Data Int TimeOut.\n")) ++ return MV_TIMEOUT; ++ ++ while(blockSizeWr) ++ { ++ /* write the data*/ ++ MV_REG_WRITE(TWSI_DATA_REG(chanNum),(MV_U32)*pBlock); ++ DB(mvOsPrintf("TWSI: twsiDataTransmit place = %d write %x \n",\ ++ blockSize - blockSizeWr, *pBlock)); ++ pBlock++; ++ blockSizeWr--; ++ ++ twsiIntFlgClr(chanNum); ++ ++ /* wait for Int to be Set */ ++ timeout = 0; ++ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); ++ ++ /* check for timeout */ ++ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataTransmit ERROR - Read Data Int TimeOut.\n")) ++ return MV_TIMEOUT; ++ ++ /* check the status */ ++ temp = twsiStsGet(chanNum); ++ if(temp != TWSI_M_TRAN_DATA_BYTE_ACK_REC) ++ { ++ mvOsPrintf("TWSI: twsiDataTransmit ERROR - status %x in write trans\n",temp); ++ return MV_FAIL; ++ } ++ ++ } ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* twsiDataReceive - Receive data block from TWSI bus. ++* ++* DESCRIPTION: ++* This function receive data block from TWSI bus in 8bit granularity ++* into pBlock buffer. ++* first The function waits for interrupt flag to be active then ++* For each 8-bit data: ++* It clears the interrupt flag which allows the next data to be ++* received from TWSI bus. ++* The function waits for interrupt flag to be active, ++* and status reg is 0x50. ++* Then the function reads data from data register, and copies it to ++* the given buffer. ++* ++* INPUT: ++* chanNum - TWSI channel ++* blockSize - number of bytes to read. ++* ++* OUTPUT: ++* pBlock - Data block. ++* ++* RETURN: ++* MV_OK - if receive transaction completed succesfully, ++* MV_BAD_PARAM - if pBlock is NULL, ++* MV_FAIL otherwmise. ++* ++*******************************************************************************/ ++static MV_STATUS twsiDataReceive(MV_U8 chanNum, MV_U8 *pBlock, MV_U32 blockSize) ++{ ++ MV_U32 timeout, temp, blockSizeRd = blockSize; ++ if(NULL == pBlock) ++ return MV_BAD_PARAM; ++ ++ /* wait for Int to be Set */ ++ timeout = 0; ++ while( !twsiMainIntGet(chanNum) && (timeout++ < TWSI_TIMEOUT_VALUE)); ++ ++ /* check for timeout */ ++ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataReceive ERROR - Read Data int Time out .\n")) ++ return MV_TIMEOUT; ++ ++ while(blockSizeRd) ++ { ++ if(blockSizeRd == 1) ++ { ++ /* clear ack and Int flag */ ++ temp = MV_REG_READ(TWSI_CONTROL_REG(chanNum)); ++ temp &= ~(TWSI_CONTROL_ACK); ++ MV_REG_WRITE(TWSI_CONTROL_REG(chanNum), temp); ++ } ++ twsiIntFlgClr(chanNum); ++ /* wait for Int to be Set */ ++ timeout = 0; ++ while( (!twsiMainIntGet(chanNum)) && (timeout++ < TWSI_TIMEOUT_VALUE)); ++ ++ /* check for timeout */ ++ if(MV_TRUE == twsiTimeoutChk(timeout,"TWSI: twsiDataReceive ERROR - Read Data Int Time out .\n")) ++ return MV_TIMEOUT; ++ ++ /* check the status */ ++ temp = twsiStsGet(chanNum); ++ if((temp != TWSI_M_REC_RD_DATA_ACK_TRA) && (blockSizeRd !=1)) ++ { ++ mvOsPrintf("TWSI: twsiDataReceive ERROR - status %x in read trans \n",temp); ++ return MV_FAIL; ++ } ++ else if((temp != TWSI_M_REC_RD_DATA_ACK_NOT_TRA) && (blockSizeRd ==1)) ++ { ++ mvOsPrintf("TWSI: twsiDataReceive ERROR - status %x in Rd Terminate\n",temp); ++ return MV_FAIL; ++ } ++ ++ /* read the data*/ ++ *pBlock = (MV_U8)MV_REG_READ(TWSI_DATA_REG(chanNum)); ++ DB(mvOsPrintf("TWSI: twsiDataReceive place %d read %x \n",\ ++ blockSize - blockSizeRd,*pBlock)); ++ pBlock++; ++ blockSizeRd--; ++ } ++ ++ return MV_OK; ++} ++ ++ ++ ++/******************************************************************************* ++* twsiTargetOffsSet - Set TWST target offset on TWSI bus. ++* ++* DESCRIPTION: ++* The function support TWSI targets that have inside address space (for ++* example EEPROMs). The function: ++* 1) Convert the given offset into pBlock and size. ++* in case the offset should be set to a TWSI slave which support ++* more then 256 bytes offset, the offset setting will be done ++* in 2 transactions. ++* 2) Use twsiDataTransmit to place those on the bus. ++* ++* INPUT: ++* chanNum - TWSI channel ++* offset - offset to be set on the EEPROM device. ++* moreThen256 - whether the EEPROM device support more then 256 byte offset. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* MV_OK - if setting the offset completed succesfully. ++* MV_FAIL otherwmise. ++* ++*******************************************************************************/ ++static MV_STATUS twsiTargetOffsSet(MV_U8 chanNum, MV_U32 offset, MV_BOOL moreThen256) ++{ ++ MV_U8 offBlock[2]; ++ MV_U32 offSize; ++ ++ if(moreThen256 == MV_TRUE) ++ { ++ offBlock[0] = (offset >> 8) & 0xff; ++ offBlock[1] = offset & 0xff; ++ offSize = 2; ++ } ++ else ++ { ++ offBlock[0] = offset & 0xff; ++ offSize = 1; ++ } ++ DB(mvOsPrintf("TWSI: twsiTargetOffsSet offSize = %x addr1 = %x addr2 = %x\n",\ ++ offSize,offBlock[0],offBlock[1])); ++ return twsiDataTransmit(chanNum, offBlock, offSize); ++ ++} ++ ++/******************************************************************************* ++* mvTwsiRead - Read data block from a TWSI Slave. ++* ++* DESCRIPTION: ++* The function calls the following functions: ++* -) mvTwsiStartBitSet(); ++* if(EEPROM device) ++* -) mvTwsiAddrSet(w); ++* -) twsiTargetOffsSet(); ++* -) mvTwsiStartBitSet(); ++* -) mvTwsiAddrSet(r); ++* -) twsiDataReceive(); ++* -) mvTwsiStopBitSet(); ++* ++* INPUT: ++* chanNum - TWSI channel ++* pTwsiSlave - Twsi Slave structure. ++* blockSize - number of bytes to read. ++* ++* OUTPUT: ++* pBlock - Data block. ++* ++* RETURN: ++* MV_OK - if EEPROM read transaction completed succesfully, ++* MV_BAD_PARAM - if pBlock is NULL, ++* MV_FAIL otherwmise. ++* ++*******************************************************************************/ ++MV_STATUS mvTwsiRead(MV_U8 chanNum, MV_TWSI_SLAVE *pTwsiSlave, MV_U8 *pBlock, MV_U32 blockSize) ++{ ++ if((NULL == pBlock) || (NULL == pTwsiSlave)) ++ return MV_BAD_PARAM; ++ if(MV_OK != mvTwsiStartBitSet(chanNum)) ++ { ++ mvTwsiStopBitSet(chanNum); ++ return MV_FAIL; ++ } ++ ++ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiStartBitSet\n")); ++ ++ /* in case offset exsist (i.e. eeprom ) */ ++ if(MV_TRUE == pTwsiSlave->validOffset) ++ { ++ if(MV_OK != mvTwsiAddrSet(chanNum, &(pTwsiSlave->slaveAddr), MV_TWSI_WRITE)) ++ { ++ mvTwsiStopBitSet(chanNum); ++ return MV_FAIL; ++ } ++ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiAddrSet\n")); ++ if(MV_OK != twsiTargetOffsSet(chanNum, pTwsiSlave->offset, pTwsiSlave->moreThen256)) ++ { ++ mvTwsiStopBitSet(chanNum); ++ return MV_FAIL; ++ } ++ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after twsiTargetOffsSet\n")); ++ if(MV_OK != mvTwsiStartBitSet(chanNum)) ++ { ++ mvTwsiStopBitSet(chanNum); ++ return MV_FAIL; ++ } ++ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiStartBitSet\n")); ++ } ++ if(MV_OK != mvTwsiAddrSet(chanNum, &(pTwsiSlave->slaveAddr), MV_TWSI_READ)) ++ { ++ mvTwsiStopBitSet(chanNum); ++ return MV_FAIL; ++ } ++ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiAddrSet\n")); ++ if(MV_OK != twsiDataReceive(chanNum, pBlock, blockSize)) ++ { ++ mvTwsiStopBitSet(chanNum); ++ return MV_FAIL; ++ } ++ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after twsiDataReceive\n")); ++ ++ if(MV_OK != mvTwsiStopBitSet(chanNum)) ++ { ++ return MV_FAIL; ++ } ++ ++ twsiAckBitSet(chanNum); ++ ++ DB(mvOsPrintf("TWSI: mvTwsiEepromRead after mvTwsiStopBitSet\n")); ++ ++ return MV_OK; ++} ++ ++/******************************************************************************* ++* mvTwsiWrite - Write data block to a TWSI Slave. ++* ++* DESCRIPTION: ++* The function calls the following functions: ++* -) mvTwsiStartBitSet(); ++* -) mvTwsiAddrSet(); ++* -)if(EEPROM device) ++* -) twsiTargetOffsSet(); ++* -) twsiDataTransmit(); ++* -) mvTwsiStopBitSet(); ++* ++* INPUT: ++* chanNum - TWSI channel ++* eepromAddress - eeprom address. ++* blockSize - number of bytes to write. ++* pBlock - Data block. ++* ++* OUTPUT: ++* None ++* ++* RETURN: ++* MV_OK - if EEPROM read transaction completed succesfully. ++* MV_BAD_PARAM - if pBlock is NULL, ++* MV_FAIL otherwmise. ++* ++* NOTE: Part of the EEPROM, required that the offset will be aligned to the ++* max write burst supported. ++*******************************************************************************/ ++MV_STATUS mvTwsiWrite(MV_U8 chanNum, MV_TWSI_SLAVE *pTwsiSlave, MV_U8 *pBlock, MV_U32 blockSize) ++{ ++ if((NULL == pBlock) || (NULL == pTwsiSlave)) ++ return MV_BAD_PARAM; ++ ++ if(MV_OK != mvTwsiStartBitSet(chanNum)) ++ { ++ mvTwsiStopBitSet(chanNum); ++ return MV_FAIL; ++ } ++ ++ DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after mvTwsiStartBitSet\n")); ++ if(MV_OK != mvTwsiAddrSet(chanNum, &(pTwsiSlave->slaveAddr), MV_TWSI_WRITE)) ++ { ++ mvTwsiStopBitSet(chanNum); ++ return MV_FAIL; ++ } ++ DB(mvOsPrintf("TWSI :mvTwsiEepromWrite after mvTwsiAddrSet\n")); ++ ++ /* in case offset exsist (i.e. eeprom ) */ ++ if(MV_TRUE == pTwsiSlave->validOffset) ++ { ++ if(MV_OK != twsiTargetOffsSet(chanNum, pTwsiSlave->offset, pTwsiSlave->moreThen256)) ++ { ++ mvTwsiStopBitSet(chanNum); ++ return MV_FAIL; ++ } ++ DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after twsiTargetOffsSet\n")); ++ } ++ if(MV_OK != twsiDataTransmit(chanNum, pBlock, blockSize)) ++ { ++ mvTwsiStopBitSet(chanNum); ++ return MV_FAIL; ++ } ++ DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after twsiDataTransmit\n")); ++ if(MV_OK != mvTwsiStopBitSet(chanNum)) ++ { ++ return MV_FAIL; ++ } ++ DB(mvOsPrintf("TWSI: mvTwsiEepromWrite after mvTwsiStopBitSet\n")); ++ ++ return MV_OK; ++} +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsi.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,121 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++#ifndef __INCmvTwsiH ++#define __INCmvTwsiH ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++/* need to update this includes */ ++#include "twsi/mvTwsiSpec.h" ++#include "ctrlEnv/mvCtrlEnvLib.h" ++ ++ ++/* The TWSI interface supports both 7-bit and 10-bit addressing. */ ++/* This enumerator describes addressing type. */ ++typedef enum _mvTwsiAddrType ++{ ++ ADDR7_BIT, /* 7 bit address */ ++ ADDR10_BIT /* 10 bit address */ ++}MV_TWSI_ADDR_TYPE; ++ ++/* This structure describes TWSI address. */ ++typedef struct _mvTwsiAddr ++{ ++ MV_U32 address; /* address */ ++ MV_TWSI_ADDR_TYPE type; /* Address type */ ++}MV_TWSI_ADDR; ++ ++/* This structure describes a TWSI slave. */ ++typedef struct _mvTwsiSlave ++{ ++ MV_TWSI_ADDR slaveAddr; ++ MV_BOOL validOffset; /* whether the slave has offset (i.e. Eeprom etc.) */ ++ MV_U32 offset; /* offset in the slave. */ ++ MV_BOOL moreThen256; /* whether the ofset is bigger then 256 */ ++}MV_TWSI_SLAVE; ++ ++/* This enumerator describes TWSI protocol commands. */ ++typedef enum _mvTwsiCmd ++{ ++ MV_TWSI_WRITE, /* TWSI write command - 0 according to spec */ ++ MV_TWSI_READ /* TWSI read command - 1 according to spec */ ++}MV_TWSI_CMD; ++ ++MV_STATUS mvTwsiStartBitSet(MV_U8 chanNum); ++MV_STATUS mvTwsiStopBitSet(MV_U8 chanNum); ++MV_STATUS mvTwsiAddrSet(MV_U8 chanNum, MV_TWSI_ADDR *twsiAddr, MV_TWSI_CMD command); ++ ++MV_U32 mvTwsiInit(MV_U8 chanNum, MV_KHZ frequancy, MV_U32 Tclk, MV_TWSI_ADDR *twsiAddr, MV_BOOL generalCallEnable); ++MV_STATUS mvTwsiRead (MV_U8 chanNum, MV_TWSI_SLAVE *twsiSlave, MV_U8 *pBlock, MV_U32 blockSize); ++MV_STATUS mvTwsiWrite(MV_U8 chanNum, MV_TWSI_SLAVE *twsiSlave, MV_U8 *pBlock, MV_U32 blockSize); ++ ++ ++#ifdef __cplusplus ++} ++#endif /* __cplusplus */ ++ ++#endif /* __INCmvTwsiH */ ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiEeprom.S linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiEeprom.S +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiEeprom.S 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiEeprom.S 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,457 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++ ++ ++/* includes */ ++#define MV_ASMLANGUAGE ++#include "ctrlEnv/mvCtrlEnvSpec.h" ++#include "boardEnv/mvBoardEnvSpec.h" ++#include "mvOsAsm.h" ++#include "mvTwsiSpec.h" ++#include "mvSysHwConfig.h" ++#include "ctrlEnv/sys/mvCpuIfRegs.h" ++#include "mvCommon.h" ++ ++#define I2C_CH MV_BOARD_DIMM_I2C_CHANNEL ++ ++/* defines */ ++/* defines */ ++ ++ ++ .data ++ .global _i2cInit ++ .global _i2cRead ++ ++ .text ++ ++/******************************************************************************* ++* _i2cInit - Initialize TWSI interface ++* ++* DESCRIPTION: ++* The function performs TWSI interface initialization. It resets the ++* TWSI state machine and initialize its clock to 100KHz assuming Tclock ++* of 133MHz. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++_i2cInit: ++ mov r9, LR /* Save link register */ ++ mov r0, #0 /* Make sure r0 is zero */ ++ ++ /* Reset the i2c Mechanism first */ ++ MV_REG_WRITE_ASM (r0, r1, TWSI_SOFT_RESET_REG(I2C_CH)) ++ ++ bl _twsiDelay ++ bl _twsiDelay ++ ++ /* Initializing the I2C mechanism. Assuming Tclock frequency */ ++ /* of 166MHz. The I2C frequency in that case will be 100KHz. */ ++ /* For this settings, M = 9 and N = 3. Set the baud-rate with the */ ++ /* value of 0x2b (freq of ==> 100KHz */ ++ /* see spec for more details about the calculation of this value) */ ++ mov r6, #(9 << 3 | 3) ++ MV_REG_WRITE_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) ++ ++ /* Enable the I2C master */ ++ /* Enable TWSI interrupt in main mask reg */ ++ mov r6, #0xC4 ++ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ ++ /* Let the slow TWSI machine get used to the idea that it is enabled */ ++ bl _twsiDelay ++ ++ ++ mov PC, r9 /* r9 is saved link register */ ++ ++/******************************************************************************* ++* _twsiDelay - Perform delay. ++* ++* DESCRIPTION: ++* The function performs a delay to enable TWSI logic to stable. ++* ++* INPUT: ++* None. ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* None. ++* ++*******************************************************************************/ ++_twsiDelay: ++ mov r10, #0x100000 /*was 0x400*/ ++ ++_twsiDelayLoop: ++ subs r10, r10, #1 ++ bne _twsiDelayLoop ++ ++ mov PC, LR ++ ++/******************************************************************************* ++* _i2cRead - Read byte from I2C EEPROM device. ++* ++* DESCRIPTION: ++* The function returns a byte from I2C EEPROM device. ++* The EEPROM device is 7-bit address type. ++* ++* INPUT: ++* r4 has the DIMM0 base address with shift 1 bit to the left ++* r7 has the EEPROM offset ++* ++* OUTPUT: ++* None. ++* ++* RETURN: ++* r4 returns '0' if address can not be read. ++* r7 has byte value in case read is successful. ++* ++*******************************************************************************/ ++_i2cRead: ++ mov r9, LR /* Save link register */ ++ ++ /* Transmit the device address and desired offset within the EEPROM. */ ++ ++ /* Generate Start Bit */ ++ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ orr r6, r6, #TWSI_CONTROL_START_BIT ++ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ ++ /* Wait for the interrupt flag (bit3) to be set */ ++ mov r10, #0x50000 ++loop_1: ++ subs r10, r10, #1 ++ beq loop_1_timeout ++#ifdef MV78XX0 ++ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) ++ tst r6, #BIT2 ++#else ++ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) ++ tst r6, #BIT5 ++#endif ++ beq loop_1 ++ ++loop_1_timeout: ++ ++ /* Wait for the start bit to be reset by HW */ ++ mov r10, #0x50000 ++loop_2: ++ subs r10, r10, #1 ++ beq loop_2_timeout ++ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ tst r6, #TWSI_CONTROL_START_BIT ++ bne loop_2 ++ ++loop_2_timeout: ++ ++ /* Wait for the status TWSI_START_CONDITION_TRA = 0x8 */ ++ mov r10, #0x50000 ++loop_3: ++ subs r10, r10, #1 ++ beq loop_3_timeout ++ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) ++ cmp r6, #0x08 ++ bne loop_3 ++ ++loop_3_timeout: ++ ++ /* writing the address of (DIMM0/1 << 1) with write indication */ ++ mov r6, r4, LSL #1 /* Write operation address bit 0 must be 0 */ ++ MV_REG_WRITE_ASM (r6, r1, TWSI_DATA_REG(I2C_CH)) ++ ++ bl _twsiDelay ++ /* Clear the interrupt flag */ ++ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET ++ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ bl _twsiDelay ++ ++ /* Waiting for the interrupt flag to be set which means that the ++ address has been transmitted */ ++loop_4: ++#ifdef MV78XX0 ++ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) ++ tst r6, #BIT2 ++#else ++ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) ++ tst r6, #BIT5 ++#endif ++ beq loop_4 /* if tst = 0, then the bit is not set yet */ ++ ++ /* Wait for status TWSI_ADDR_PLUS_WRITE_BIT_TRA_ACK_REC = 0x18 */ ++ mov r10, #0x50000 /* Set r10 to 0x50000 =~ 328,000 */ ++ ++loop_5: ++ subs r10, r10, #1 /* timeout count down */ ++ bne testStatus ++ mov r4, #0 /* r4 = 0 -> operation failed */ ++ b exit_i2cRead /* Exit if timeout (No DIMM) */ ++ ++testStatus: ++ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) ++ cmp r6, #0x18 ++ bne loop_5 ++ ++ ++ /* check if the offset is bigger than 256 byte*/ ++ tst r7, #0x80000000 ++ bne great_than_256 ++ ++ /* Write the offset to be read from the DIMM EEPROM */ ++ MV_REG_WRITE_ASM (r7, r1, TWSI_DATA_REG(I2C_CH)) ++ ++ b after_offset ++ ++great_than_256: ++ mov r10, r7, LSR #8 ++ and r10, r10, #0xff ++ /* Write the offset0 to be read from the EEPROM */ ++ MV_REG_WRITE_ASM (r10, r1, TWSI_DATA_REG(I2C_CH)) ++ ++ /* Clear the interrupt flag ==> signaling that the address can now ++ be transmited */ ++ ++ bl _twsiDelay ++ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET ++ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ bl _twsiDelay ++ ++ /* Wait for the interrupt to be set again ==> address has transmited */ ++loop_6_1: ++#ifdef MV78XX0 ++ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) ++ tst r6, #BIT2 ++#else ++ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) ++ tst r6, #BIT5 ++#endif ++ beq loop_6_1 ++ ++ /* Wait for status TWSI_MAS_TRAN_DATA_BYTE_ACK_REC = 0x28 */ ++loop_7_1: ++ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) ++ cmp r6, #0x28 ++ bne loop_7_1 ++ ++ ++ mov r10, r7 ++ and r10, r10, #0xff ++ /* Write the offset1 to be read from the EEPROM */ ++ MV_REG_WRITE_ASM (r10, r1, TWSI_DATA_REG(I2C_CH)) ++ ++ ++ ++after_offset: ++ ++ /* Clear the interrupt flag ==> signaling that the address can now ++ be transmited */ ++ ++ bl _twsiDelay ++ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET ++ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ bl _twsiDelay ++ ++ /* Wait for the interrupt to be set again ==> address has transmited */ ++loop_6: ++#ifdef MV78XX0 ++ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) ++ tst r6, #BIT2 ++#else ++ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) ++ tst r6, #BIT5 ++#endif ++ beq loop_6 ++ ++ /* Wait for status TWSI_MAS_TRAN_DATA_BYTE_ACK_REC = 0x28 */ ++loop_7: ++ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) ++ cmp r6, #0x28 ++ bne loop_7 ++ ++ /* Retransmit the device address with read indication to get the data */ ++ ++ /* generate a repeated start bit */ ++ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ orr r6, r6, #TWSI_CONTROL_START_BIT ++ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ ++ ++ /* Clear the interrupt flag ==> the start bit will be transmitted. */ ++ bl _twsiDelay ++ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET ++ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ bl _twsiDelay ++ ++ /* Wait for the interrupt flag (bit3) to be set */ ++loop_9: ++#ifdef MV78XX0 ++ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) ++ tst r6, #BIT2 ++#else ++ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) ++ tst r6, #BIT5 ++#endif ++ beq loop_9 ++ ++ /* Wait for the start bit to be reset by HW */ ++loop_8: ++ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ tst r6, #TWSI_CONTROL_START_BIT ++ bne loop_8 ++ ++ /* Wait for status TWSI_REPEATED_START_CONDITION_TRA = 0x10 */ ++loop_10: ++ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) ++ cmp r6, #0x10 ++ bne loop_10 ++ ++ /* Writing the address of (DIMM0<<1) with read indication (bit0 is 1) */ ++ mov r6, r4, LSL #1 ++ orr r6, r6, #1 /* Read operation address bit 0 must be 1 */ ++ MV_REG_WRITE_ASM (r6, r1, TWSI_DATA_REG(I2C_CH)) ++ ++ /* Clear the interrupt flag ==> the address will be transmitted */ ++ bl _twsiDelay ++ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET ++ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ bl _twsiDelay ++ ++ /* Wait for the interrupt flag (bit3) to be set as a result of ++ transmitting the address. */ ++loop_11: ++#ifdef MV78XX0 ++ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) ++ tst r6, #BIT2 ++#else ++ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) ++ tst r6, #BIT5 ++#endif ++ beq loop_11 ++ ++ /* Wait for status TWSI_ADDR_PLUS_READ_BIT_TRA_ACK_REC = 0x40 */ ++loop_12: ++ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) ++ cmp r6, #0x40 ++ bne loop_12 ++ ++ /* Clear the interrupt flag and the Acknoledge bit */ ++ bl _twsiDelay ++ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ bic r6, r6, #(TWSI_CONTROL_INT_FLAG_SET | TWSI_CONTROL_ACK) ++ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ bl _twsiDelay ++ ++ /* Wait for the interrupt flag (bit3) to be set */ ++loop_14: ++#ifdef MV78XX0 ++ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH)) ++ tst r6, #BIT2 ++#else ++ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG) ++ tst r6, #BIT5 ++#endif ++ beq loop_14 ++ ++ /* Wait for status TWSI_MAS_REC_READ_DATA_ACK_NOT_TRA = 0x58 */ ++loop_15: ++ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH)) ++ cmp r6, #0x58 ++ bne loop_15 ++ ++ /* Store the data in r7. */ ++ MV_REG_READ_ASM (r7, r1, TWSI_DATA_REG(I2C_CH)) ++ ++ /* Generate stop bit */ ++ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ orr r6, r6, #TWSI_CONTROL_STOP_BIT ++ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ ++ ++ /* Clear the interrupt flag */ ++ bl _twsiDelay ++ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET ++ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ bl _twsiDelay ++ ++ /* Wait for the stop bit to be reset by HW */ ++loop_16: ++ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH)) ++ tst r6, #TWSI_CONTROL_INT_FLAG_SET ++ bne loop_16 ++ ++exit_i2cRead: ++ mov PC, r9 /* r9 is saved link register */ +diff -Nur linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiSpec.h linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiSpec.h +--- linux-3.1.4.orig/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiSpec.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/mvTwsiSpec.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,160 @@ ++/******************************************************************************* ++Copyright (C) Marvell International Ltd. and its affiliates ++ ++This software file (the "File") is owned and distributed by Marvell ++International Ltd. and/or its affiliates ("Marvell") under the following ++alternative licensing terms. Once you have made an election to distribute the ++File under one of the following license alternatives, please (i) delete this ++introductory statement regarding license alternatives, (ii) delete the two ++license alternatives that you have not elected to use and (iii) preserve the ++Marvell copyright notice above. ++ ++******************************************************************************** ++Marvell Commercial License Option ++ ++If you received this File from Marvell and you have entered into a commercial ++license agreement (a "Commercial License") with Marvell, the File is licensed ++to you under the terms of the applicable Commercial License. ++ ++******************************************************************************** ++Marvell GPL License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File in accordance with the terms and conditions of the General ++Public License Version 2, June 1991 (the "GPL License"), a copy of which is ++available along with the File in the license.txt file or by writing to the Free ++Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or ++on the worldwide web at http://www.gnu.org/licenses/gpl.txt. ++ ++THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED ++WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY ++DISCLAIMED. The GPL License provides additional details about this warranty ++disclaimer. ++******************************************************************************** ++Marvell BSD License Option ++ ++If you received this File from Marvell, you may opt to use, redistribute and/or ++modify this File under the following licensing terms. ++Redistribution and use in source and binary forms, with or without modification, ++are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright notice, ++ this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ ++ * Neither the name of Marvell nor the names of its contributors may be ++ used to endorse or promote products derived from this software without ++ specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ++ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++*******************************************************************************/ ++/****************************************/ ++/* TWSI Registers */ ++/****************************************/ ++#ifndef __INCmvTwsiSpech ++#define __INCmvTwsiSpech ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++/* defines */ ++#define TWSI_SLAVE_ADDR_REG(chanNum) (TWSI_SLAVE_BASE(chanNum)+ 0x00) ++ ++#define TWSI_SLAVE_ADDR_GCE_ENA BIT0 ++#define TWSI_SLAVE_ADDR_7BIT_OFFS 0x1 ++#define TWSI_SLAVE_ADDR_7BIT_MASK (0xFF << TWSI_SLAVE_ADDR_7BIT_OFFS) ++#define TWSI_SLAVE_ADDR_10BIT_OFFS 0x7 ++#define TWSI_SLAVE_ADDR_10BIT_MASK 0x300 ++#define TWSI_SLAVE_ADDR_10BIT_CONST 0xF0 ++ ++ ++#define TWSI_EXTENDED_SLAVE_ADDR_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x10) ++#define TWSI_EXTENDED_SLAVE_OFFS 0 ++#define TWSI_EXTENDED_SLAVE_MASK (0xFF << TWSI_EXTENDED_SLAVE_OFFS) ++ ++ ++#define TWSI_DATA_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x04) ++#define TWSI_DATA_COMMAND_OFFS 0x0 ++#define TWSI_DATA_COMMAND_MASK (0x1 << TWSI_DATA_COMMAND_OFFS) ++#define TWSI_DATA_COMMAND_WR (0x1 << TWSI_DATA_COMMAND_OFFS) ++#define TWSI_DATA_COMMAND_RD (0x0 << TWSI_DATA_COMMAND_OFFS) ++#define TWSI_DATA_ADDR_7BIT_OFFS 0x1 ++#define TWSI_DATA_ADDR_7BIT_MASK (0xFF << TWSI_DATA_ADDR_7BIT_OFFS) ++#define TWSI_DATA_ADDR_10BIT_OFFS 0x7 ++#define TWSI_DATA_ADDR_10BIT_MASK 0x300 ++#define TWSI_DATA_ADDR_10BIT_CONST 0xF0 ++ ++ ++#define TWSI_CONTROL_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x08) ++#define TWSI_CONTROL_ACK BIT2 ++#define TWSI_CONTROL_INT_FLAG_SET BIT3 ++#define TWSI_CONTROL_STOP_BIT BIT4 ++#define TWSI_CONTROL_START_BIT BIT5 ++#define TWSI_CONTROL_ENA BIT6 ++#define TWSI_CONTROL_INT_ENA BIT7 ++ ++ ++#define TWSI_STATUS_BAUDE_RATE_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x0c) ++#define TWSI_BAUD_RATE_N_OFFS 0 ++#define TWSI_BAUD_RATE_N_MASK (0x7 << TWSI_BAUD_RATE_N_OFFS) ++#define TWSI_BAUD_RATE_M_OFFS 3 ++#define TWSI_BAUD_RATE_M_MASK (0xF << TWSI_BAUD_RATE_M_OFFS) ++ ++#define TWSI_SOFT_RESET_REG(chanNum) (TWSI_SLAVE_BASE(chanNum) + 0x1c) ++ ++/* defines */ ++#define TWSI_TIMEOUT_VALUE 0x500 ++ ++/* TWSI status codes */ ++#define TWSI_BUS_ERROR 0x00 ++#define TWSI_START_CON_TRA 0x08 ++#define TWSI_REPEATED_START_CON_TRA 0x10 ++#define TWSI_AD_PLS_WR_BIT_TRA_ACK_REC 0x18 ++#define TWSI_AD_PLS_WR_BIT_TRA_ACK_NOT_REC 0x20 ++#define TWSI_M_TRAN_DATA_BYTE_ACK_REC 0x28 ++#define TWSI_M_TRAN_DATA_BYTE_ACK_NOT_REC 0x30 ++#define TWSI_M_LOST_ARB_DUR_AD_OR_DATA_TRA 0x38 ++#define TWSI_AD_PLS_RD_BIT_TRA_ACK_REC 0x40 ++#define TWSI_AD_PLS_RD_BIT_TRA_ACK_NOT_REC 0x48 ++#define TWSI_M_REC_RD_DATA_ACK_TRA 0x50 ++#define TWSI_M_REC_RD_DATA_ACK_NOT_TRA 0x58 ++#define TWSI_SLA_REC_AD_PLS_WR_BIT_ACK_TRA 0x60 ++#define TWSI_M_LOST_ARB_DUR_AD_TRA_AD_IS_TRGT_TO_SLA_ACK_TRA_W 0x68 ++#define TWSI_GNL_CALL_REC_ACK_TRA 0x70 ++#define TWSI_M_LOST_ARB_DUR_AD_TRA_GNL_CALL_AD_REC_ACK_TRA 0x78 ++#define TWSI_SLA_REC_WR_DATA_AF_REC_SLA_AD_ACK_TRAN 0x80 ++#define TWSI_SLA_REC_WR_DATA_AF_REC_SLA_AD_ACK_NOT_TRAN 0x88 ++#define TWSI_SLA_REC_WR_DATA_AF_REC_GNL_CALL_ACK_TRAN 0x90 ++#define TWSI_SLA_REC_WR_DATA_AF_REC_GNL_CALL_ACK_NOT_TRAN 0x98 ++#define TWSI_SLA_REC_STOP_OR_REPEATED_STRT_CON 0xA0 ++#define TWSI_SLA_REC_AD_PLS_RD_BIT_ACK_TRA 0xA8 ++#define TWSI_M_LOST_ARB_DUR_AD_TRA_AD_IS_TRGT_TO_SLA_ACK_TRA_R 0xB0 ++#define TWSI_SLA_TRA_RD_DATA_ACK_REC 0xB8 ++#define TWSI_SLA_TRA_RD_DATA_ACK_NOT_REC 0xC0 ++#define TWSI_SLA_TRA_LAST_RD_DATA_ACK_REC 0xC8 ++#define TWSI_SEC_AD_PLS_WR_BIT_TRA_ACK_REC 0xD0 ++#define TWSI_SEC_AD_PLS_WR_BIT_TRA_ACK_NOT_REC 0xD8 ++#define TWSI_SEC_AD_PLS_RD_BIT_TRA_ACK_REC 0xE0 ++#define TWSI_SEC_AD_PLS_RD_BIT_TRA_ACK_NOT_REC 0xE8 ++#define TWSI_NO_REL_STS_INT_FLAG_IS_KEPT_0 0xF8 ++ ++ ++#ifdef __cplusplus ++} ++#endif /* __cplusplus */ ++ ++#endif /* __INCmvTwsiSpech */ +diff -Nur linux-3.1.4.orig/crypto/ocf/ocf-bench.c linux-3.1.4/crypto/ocf/ocf-bench.c +--- linux-3.1.4.orig/crypto/ocf/ocf-bench.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/ocf-bench.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,514 @@ ++/* ++ * A loadable module that benchmarks the OCF crypto speed from kernel space. ++ * ++ * Copyright (C) 2004-2010 David McCullough ++ * ++ * LICENSE TERMS ++ * ++ * The free distribution and use of this software in both source and binary ++ * form is allowed (with or without changes) provided that: ++ * ++ * 1. distributions of this source code include the above copyright ++ * notice, this list of conditions and the following disclaimer; ++ * ++ * 2. distributions in binary form include the above copyright ++ * notice, this list of conditions and the following disclaimer ++ * in the documentation and/or other associated materials; ++ * ++ * 3. the copyright holder's name is not used to endorse products ++ * built using this software without specific written permission. ++ * ++ * ALTERNATIVELY, provided that this notice is retained in full, this product ++ * may be distributed under the terms of the GNU General Public License (GPL), ++ * in which case the provisions of the GPL apply INSTEAD OF those given above. ++ * ++ * DISCLAIMER ++ * ++ * This software is provided 'as is' with no explicit or implied warranties ++ * in respect of its properties, including, but not limited to, correctness ++ * and/or fitness for purpose. ++ */ ++ ++ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifdef I_HAVE_AN_XSCALE_WITH_INTEL_SDK ++#define BENCH_IXP_ACCESS_LIB 1 ++#endif ++#ifdef BENCH_IXP_ACCESS_LIB ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#endif ++ ++/* ++ * support for access lib version 1.4 ++ */ ++#ifndef IX_MBUF_PRIV ++#define IX_MBUF_PRIV(x) ((x)->priv) ++#endif ++ ++/* ++ * the number of simultaneously active requests ++ */ ++static int request_q_len = 40; ++module_param(request_q_len, int, 0); ++MODULE_PARM_DESC(request_q_len, "Number of outstanding requests"); ++ ++/* ++ * how many requests we want to have processed ++ */ ++static int request_num = 1024; ++module_param(request_num, int, 0); ++MODULE_PARM_DESC(request_num, "run for at least this many requests"); ++ ++/* ++ * the size of each request ++ */ ++static int request_size = 1488; ++module_param(request_size, int, 0); ++MODULE_PARM_DESC(request_size, "size of each request"); ++ ++/* ++ * OCF batching of requests ++ */ ++static int request_batch = 1; ++module_param(request_batch, int, 0); ++MODULE_PARM_DESC(request_batch, "enable OCF request batching"); ++ ++/* ++ * OCF immediate callback on completion ++ */ ++static int request_cbimm = 1; ++module_param(request_cbimm, int, 0); ++MODULE_PARM_DESC(request_cbimm, "enable OCF immediate callback on completion"); ++ ++/* ++ * a structure for each request ++ */ ++typedef struct { ++ struct work_struct work; ++#ifdef BENCH_IXP_ACCESS_LIB ++ IX_MBUF mbuf; ++#endif ++ unsigned char *buffer; ++} request_t; ++ ++static request_t *requests; ++ ++static spinlock_t ocfbench_counter_lock; ++static int outstanding; ++static int total; ++ ++/*************************************************************************/ ++/* ++ * OCF benchmark routines ++ */ ++ ++static uint64_t ocf_cryptoid; ++static unsigned long jstart, jstop; ++ ++static int ocf_init(void); ++static int ocf_cb(struct cryptop *crp); ++static void ocf_request(void *arg); ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++static void ocf_request_wq(struct work_struct *work); ++#endif ++ ++static int ++ocf_init(void) ++{ ++ int error; ++ struct cryptoini crie, cria; ++ struct cryptodesc crda, crde; ++ ++ memset(&crie, 0, sizeof(crie)); ++ memset(&cria, 0, sizeof(cria)); ++ memset(&crde, 0, sizeof(crde)); ++ memset(&crda, 0, sizeof(crda)); ++ ++ cria.cri_alg = CRYPTO_SHA1_HMAC; ++ cria.cri_klen = 20 * 8; ++ cria.cri_key = "0123456789abcdefghij"; ++ ++ //crie.cri_alg = CRYPTO_3DES_CBC; ++ crie.cri_alg = CRYPTO_AES_CBC; ++ crie.cri_klen = 24 * 8; ++ crie.cri_key = "0123456789abcdefghijklmn"; ++ ++ crie.cri_next = &cria; ++ ++ error = crypto_newsession(&ocf_cryptoid, &crie, ++ CRYPTOCAP_F_HARDWARE | CRYPTOCAP_F_SOFTWARE); ++ if (error) { ++ printk("crypto_newsession failed %d\n", error); ++ return -1; ++ } ++ return 0; ++} ++ ++static int ++ocf_cb(struct cryptop *crp) ++{ ++ request_t *r = (request_t *) crp->crp_opaque; ++ unsigned long flags; ++ ++ if (crp->crp_etype) ++ printk("Error in OCF processing: %d\n", crp->crp_etype); ++ crypto_freereq(crp); ++ crp = NULL; ++ ++ /* do all requests but take at least 1 second */ ++ spin_lock_irqsave(&ocfbench_counter_lock, flags); ++ total++; ++ if (total > request_num && jstart + HZ < jiffies) { ++ outstanding--; ++ spin_unlock_irqrestore(&ocfbench_counter_lock, flags); ++ return 0; ++ } ++ spin_unlock_irqrestore(&ocfbench_counter_lock, flags); ++ ++ schedule_work(&r->work); ++ return 0; ++} ++ ++ ++static void ++ocf_request(void *arg) ++{ ++ request_t *r = arg; ++ struct cryptop *crp = crypto_getreq(2); ++ struct cryptodesc *crde, *crda; ++ unsigned long flags; ++ ++ if (!crp) { ++ spin_lock_irqsave(&ocfbench_counter_lock, flags); ++ outstanding--; ++ spin_unlock_irqrestore(&ocfbench_counter_lock, flags); ++ return; ++ } ++ ++ crde = crp->crp_desc; ++ crda = crde->crd_next; ++ ++ crda->crd_skip = 0; ++ crda->crd_flags = 0; ++ crda->crd_len = request_size; ++ crda->crd_inject = request_size; ++ crda->crd_alg = CRYPTO_SHA1_HMAC; ++ crda->crd_key = "0123456789abcdefghij"; ++ crda->crd_klen = 20 * 8; ++ ++ crde->crd_skip = 0; ++ crde->crd_flags = CRD_F_IV_EXPLICIT | CRD_F_ENCRYPT; ++ crde->crd_len = request_size; ++ crde->crd_inject = request_size; ++ //crde->crd_alg = CRYPTO_3DES_CBC; ++ crde->crd_alg = CRYPTO_AES_CBC; ++ crde->crd_key = "0123456789abcdefghijklmn"; ++ crde->crd_klen = 24 * 8; ++ ++ crp->crp_ilen = request_size + 64; ++ crp->crp_flags = 0; ++ if (request_batch) ++ crp->crp_flags |= CRYPTO_F_BATCH; ++ if (request_cbimm) ++ crp->crp_flags |= CRYPTO_F_CBIMM; ++ crp->crp_buf = (caddr_t) r->buffer; ++ crp->crp_callback = ocf_cb; ++ crp->crp_sid = ocf_cryptoid; ++ crp->crp_opaque = (caddr_t) r; ++ crypto_dispatch(crp); ++} ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++static void ++ocf_request_wq(struct work_struct *work) ++{ ++ request_t *r = container_of(work, request_t, work); ++ ocf_request(r); ++} ++#endif ++ ++static void ++ocf_done(void) ++{ ++ crypto_freesession(ocf_cryptoid); ++} ++ ++/*************************************************************************/ ++#ifdef BENCH_IXP_ACCESS_LIB ++/*************************************************************************/ ++/* ++ * CryptoAcc benchmark routines ++ */ ++ ++static IxCryptoAccCtx ixp_ctx; ++static UINT32 ixp_ctx_id; ++static IX_MBUF ixp_pri; ++static IX_MBUF ixp_sec; ++static int ixp_registered = 0; ++ ++static void ixp_register_cb(UINT32 ctx_id, IX_MBUF *bufp, ++ IxCryptoAccStatus status); ++static void ixp_perform_cb(UINT32 ctx_id, IX_MBUF *sbufp, IX_MBUF *dbufp, ++ IxCryptoAccStatus status); ++static void ixp_request(void *arg); ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++static void ixp_request_wq(struct work_struct *work); ++#endif ++ ++static int ++ixp_init(void) ++{ ++ IxCryptoAccStatus status; ++ ++ ixp_ctx.cipherCtx.cipherAlgo = IX_CRYPTO_ACC_CIPHER_3DES; ++ ixp_ctx.cipherCtx.cipherMode = IX_CRYPTO_ACC_MODE_CBC; ++ ixp_ctx.cipherCtx.cipherKeyLen = 24; ++ ixp_ctx.cipherCtx.cipherBlockLen = IX_CRYPTO_ACC_DES_BLOCK_64; ++ ixp_ctx.cipherCtx.cipherInitialVectorLen = IX_CRYPTO_ACC_DES_IV_64; ++ memcpy(ixp_ctx.cipherCtx.key.cipherKey, "0123456789abcdefghijklmn", 24); ++ ++ ixp_ctx.authCtx.authAlgo = IX_CRYPTO_ACC_AUTH_SHA1; ++ ixp_ctx.authCtx.authDigestLen = 12; ++ ixp_ctx.authCtx.aadLen = 0; ++ ixp_ctx.authCtx.authKeyLen = 20; ++ memcpy(ixp_ctx.authCtx.key.authKey, "0123456789abcdefghij", 20); ++ ++ ixp_ctx.useDifferentSrcAndDestMbufs = 0; ++ ixp_ctx.operation = IX_CRYPTO_ACC_OP_ENCRYPT_AUTH ; ++ ++ IX_MBUF_MLEN(&ixp_pri) = IX_MBUF_PKT_LEN(&ixp_pri) = 128; ++ IX_MBUF_MDATA(&ixp_pri) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); ++ IX_MBUF_MLEN(&ixp_sec) = IX_MBUF_PKT_LEN(&ixp_sec) = 128; ++ IX_MBUF_MDATA(&ixp_sec) = (unsigned char *) kmalloc(128, SLAB_ATOMIC); ++ ++ status = ixCryptoAccCtxRegister(&ixp_ctx, &ixp_pri, &ixp_sec, ++ ixp_register_cb, ixp_perform_cb, &ixp_ctx_id); ++ ++ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) { ++ while (!ixp_registered) ++ schedule(); ++ return ixp_registered < 0 ? -1 : 0; ++ } ++ ++ printk("ixp: ixCryptoAccCtxRegister failed %d\n", status); ++ return -1; ++} ++ ++static void ++ixp_register_cb(UINT32 ctx_id, IX_MBUF *bufp, IxCryptoAccStatus status) ++{ ++ if (bufp) { ++ IX_MBUF_MLEN(bufp) = IX_MBUF_PKT_LEN(bufp) = 0; ++ kfree(IX_MBUF_MDATA(bufp)); ++ IX_MBUF_MDATA(bufp) = NULL; ++ } ++ ++ if (IX_CRYPTO_ACC_STATUS_WAIT == status) ++ return; ++ if (IX_CRYPTO_ACC_STATUS_SUCCESS == status) ++ ixp_registered = 1; ++ else ++ ixp_registered = -1; ++} ++ ++static void ++ixp_perform_cb( ++ UINT32 ctx_id, ++ IX_MBUF *sbufp, ++ IX_MBUF *dbufp, ++ IxCryptoAccStatus status) ++{ ++ request_t *r = NULL; ++ unsigned long flags; ++ ++ /* do all requests but take at least 1 second */ ++ spin_lock_irqsave(&ocfbench_counter_lock, flags); ++ total++; ++ if (total > request_num && jstart + HZ < jiffies) { ++ outstanding--; ++ spin_unlock_irqrestore(&ocfbench_counter_lock, flags); ++ return; ++ } ++ ++ if (!sbufp || !(r = IX_MBUF_PRIV(sbufp))) { ++ printk("crappo %p %p\n", sbufp, r); ++ outstanding--; ++ spin_unlock_irqrestore(&ocfbench_counter_lock, flags); ++ return; ++ } ++ spin_unlock_irqrestore(&ocfbench_counter_lock, flags); ++ ++ schedule_work(&r->work); ++} ++ ++static void ++ixp_request(void *arg) ++{ ++ request_t *r = arg; ++ IxCryptoAccStatus status; ++ unsigned long flags; ++ ++ memset(&r->mbuf, 0, sizeof(r->mbuf)); ++ IX_MBUF_MLEN(&r->mbuf) = IX_MBUF_PKT_LEN(&r->mbuf) = request_size + 64; ++ IX_MBUF_MDATA(&r->mbuf) = r->buffer; ++ IX_MBUF_PRIV(&r->mbuf) = r; ++ status = ixCryptoAccAuthCryptPerform(ixp_ctx_id, &r->mbuf, NULL, ++ 0, request_size, 0, request_size, request_size, r->buffer); ++ if (IX_CRYPTO_ACC_STATUS_SUCCESS != status) { ++ printk("status1 = %d\n", status); ++ spin_lock_irqsave(&ocfbench_counter_lock, flags); ++ outstanding--; ++ spin_unlock_irqrestore(&ocfbench_counter_lock, flags); ++ return; ++ } ++ return; ++} ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++static void ++ixp_request_wq(struct work_struct *work) ++{ ++ request_t *r = container_of(work, request_t, work); ++ ixp_request(r); ++} ++#endif ++ ++static void ++ixp_done(void) ++{ ++ /* we should free the session here but I am lazy :-) */ ++} ++ ++/*************************************************************************/ ++#endif /* BENCH_IXP_ACCESS_LIB */ ++/*************************************************************************/ ++ ++int ++ocfbench_init(void) ++{ ++ int i; ++ unsigned long mbps; ++ unsigned long flags; ++ ++ printk("Crypto Speed tests\n"); ++ ++ requests = kmalloc(sizeof(request_t) * request_q_len, GFP_KERNEL); ++ if (!requests) { ++ printk("malloc failed\n"); ++ return -EINVAL; ++ } ++ ++ for (i = 0; i < request_q_len; i++) { ++ /* +64 for return data */ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++ INIT_WORK(&requests[i].work, ocf_request_wq); ++#else ++ INIT_WORK(&requests[i].work, ocf_request, &requests[i]); ++#endif ++ requests[i].buffer = kmalloc(request_size + 128, GFP_DMA); ++ if (!requests[i].buffer) { ++ printk("malloc failed\n"); ++ return -EINVAL; ++ } ++ memset(requests[i].buffer, '0' + i, request_size + 128); ++ } ++ ++ /* ++ * OCF benchmark ++ */ ++ printk("OCF: testing ...\n"); ++ if (ocf_init() == -1) ++ return -EINVAL; ++ ++ spin_lock_init(&ocfbench_counter_lock); ++ total = outstanding = 0; ++ jstart = jiffies; ++ for (i = 0; i < request_q_len; i++) { ++ spin_lock_irqsave(&ocfbench_counter_lock, flags); ++ outstanding++; ++ spin_unlock_irqrestore(&ocfbench_counter_lock, flags); ++ ocf_request(&requests[i]); ++ } ++ while (outstanding > 0) ++ schedule(); ++ jstop = jiffies; ++ ++ mbps = 0; ++ if (jstop > jstart) { ++ mbps = (unsigned long) total * (unsigned long) request_size * 8; ++ mbps /= ((jstop - jstart) * 1000) / HZ; ++ } ++ printk("OCF: %d requests of %d bytes in %d jiffies (%d.%03d Mbps)\n", ++ total, request_size, (int)(jstop - jstart), ++ ((int)mbps) / 1000, ((int)mbps) % 1000); ++ ocf_done(); ++ ++#ifdef BENCH_IXP_ACCESS_LIB ++ /* ++ * IXP benchmark ++ */ ++ printk("IXP: testing ...\n"); ++ ixp_init(); ++ total = outstanding = 0; ++ jstart = jiffies; ++ for (i = 0; i < request_q_len; i++) { ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++ INIT_WORK(&requests[i].work, ixp_request_wq); ++#else ++ INIT_WORK(&requests[i].work, ixp_request, &requests[i]); ++#endif ++ spin_lock_irqsave(&ocfbench_counter_lock, flags); ++ outstanding++; ++ spin_unlock_irqrestore(&ocfbench_counter_lock, flags); ++ ixp_request(&requests[i]); ++ } ++ while (outstanding > 0) ++ schedule(); ++ jstop = jiffies; ++ ++ mbps = 0; ++ if (jstop > jstart) { ++ mbps = (unsigned long) total * (unsigned long) request_size * 8; ++ mbps /= ((jstop - jstart) * 1000) / HZ; ++ } ++ printk("IXP: %d requests of %d bytes in %d jiffies (%d.%03d Mbps)\n", ++ total, request_size, jstop - jstart, ++ ((int)mbps) / 1000, ((int)mbps) % 1000); ++ ixp_done(); ++#endif /* BENCH_IXP_ACCESS_LIB */ ++ ++ for (i = 0; i < request_q_len; i++) ++ kfree(requests[i].buffer); ++ kfree(requests); ++ return -EINVAL; /* always fail to load so it can be re-run quickly ;-) */ ++} ++ ++static void __exit ocfbench_exit(void) ++{ ++} ++ ++module_init(ocfbench_init); ++module_exit(ocfbench_exit); ++ ++MODULE_LICENSE("BSD"); ++MODULE_AUTHOR("David McCullough "); ++MODULE_DESCRIPTION("Benchmark various in-kernel crypto speeds"); +diff -Nur linux-3.1.4.orig/crypto/ocf/ocf-compat.h linux-3.1.4/crypto/ocf/ocf-compat.h +--- linux-3.1.4.orig/crypto/ocf/ocf-compat.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/ocf-compat.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,365 @@ ++#ifndef _BSD_COMPAT_H_ ++#define _BSD_COMPAT_H_ 1 ++/****************************************************************************/ ++/* ++ * Provide compat routines for older linux kernels and BSD kernels ++ * ++ * Written by David McCullough ++ * Copyright (C) 2010 David McCullough ++ * ++ * LICENSE TERMS ++ * ++ * The free distribution and use of this software in both source and binary ++ * form is allowed (with or without changes) provided that: ++ * ++ * 1. distributions of this source code include the above copyright ++ * notice, this list of conditions and the following disclaimer; ++ * ++ * 2. distributions in binary form include the above copyright ++ * notice, this list of conditions and the following disclaimer ++ * in the documentation and/or other associated materials; ++ * ++ * 3. the copyright holder's name is not used to endorse products ++ * built using this software without specific written permission. ++ * ++ * ALTERNATIVELY, provided that this notice is retained in full, this file ++ * may be distributed under the terms of the GNU General Public License (GPL), ++ * in which case the provisions of the GPL apply INSTEAD OF those given above. ++ * ++ * DISCLAIMER ++ * ++ * This software is provided 'as is' with no explicit or implied warranties ++ * in respect of its properties, including, but not limited to, correctness ++ * and/or fitness for purpose. ++ */ ++/****************************************************************************/ ++#ifdef __KERNEL__ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++ ++/* ++ * fake some BSD driver interface stuff specifically for OCF use ++ */ ++ ++typedef struct ocf_device *device_t; ++ ++typedef struct { ++ int (*cryptodev_newsession)(device_t dev, u_int32_t *sidp, struct cryptoini *cri); ++ int (*cryptodev_freesession)(device_t dev, u_int64_t tid); ++ int (*cryptodev_process)(device_t dev, struct cryptop *crp, int hint); ++ int (*cryptodev_kprocess)(device_t dev, struct cryptkop *krp, int hint); ++} device_method_t; ++#define DEVMETHOD(id, func) id: func ++ ++struct ocf_device { ++ char name[32]; /* the driver name */ ++ char nameunit[32]; /* the driver name + HW instance */ ++ int unit; ++ device_method_t methods; ++ void *softc; ++}; ++ ++#define CRYPTODEV_NEWSESSION(dev, sid, cri) \ ++ ((*(dev)->methods.cryptodev_newsession)(dev,sid,cri)) ++#define CRYPTODEV_FREESESSION(dev, sid) \ ++ ((*(dev)->methods.cryptodev_freesession)(dev, sid)) ++#define CRYPTODEV_PROCESS(dev, crp, hint) \ ++ ((*(dev)->methods.cryptodev_process)(dev, crp, hint)) ++#define CRYPTODEV_KPROCESS(dev, krp, hint) \ ++ ((*(dev)->methods.cryptodev_kprocess)(dev, krp, hint)) ++ ++#define device_get_name(dev) ((dev)->name) ++#define device_get_nameunit(dev) ((dev)->nameunit) ++#define device_get_unit(dev) ((dev)->unit) ++#define device_get_softc(dev) ((dev)->softc) ++ ++#define softc_device_decl \ ++ struct ocf_device _device; \ ++ device_t ++ ++#define softc_device_init(_sc, _name, _unit, _methods) \ ++ if (1) {\ ++ strncpy((_sc)->_device.name, _name, sizeof((_sc)->_device.name) - 1); \ ++ snprintf((_sc)->_device.nameunit, sizeof((_sc)->_device.name), "%s%d", _name, _unit); \ ++ (_sc)->_device.unit = _unit; \ ++ (_sc)->_device.methods = _methods; \ ++ (_sc)->_device.softc = (void *) _sc; \ ++ *(device_t *)((softc_get_device(_sc))+1) = &(_sc)->_device; \ ++ } else ++ ++#define softc_get_device(_sc) (&(_sc)->_device) ++ ++/* ++ * iomem support for 2.4 and 2.6 kernels ++ */ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++#define ocf_iomem_t unsigned long ++ ++/* ++ * implement simple workqueue like support for older kernels ++ */ ++ ++#include ++ ++#define work_struct tq_struct ++ ++#define INIT_WORK(wp, fp, ap) \ ++ do { \ ++ (wp)->sync = 0; \ ++ (wp)->routine = (fp); \ ++ (wp)->data = (ap); \ ++ } while (0) ++ ++#define schedule_work(wp) \ ++ do { \ ++ queue_task((wp), &tq_immediate); \ ++ mark_bh(IMMEDIATE_BH); \ ++ } while (0) ++ ++#define flush_scheduled_work() run_task_queue(&tq_immediate) ++ ++#else ++#define ocf_iomem_t void __iomem * ++ ++#include ++ ++#endif ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26) ++#include ++#elif LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) ++#define files_fdtable(files) (files) ++#endif ++ ++#ifdef MODULE_PARM ++#undef module_param /* just in case */ ++#define module_param(a,b,c) MODULE_PARM(a,"i") ++#endif ++ ++#define bzero(s,l) memset(s,0,l) ++#define bcopy(s,d,l) memcpy(d,s,l) ++#define bcmp(x, y, l) memcmp(x,y,l) ++ ++#define MIN(x,y) ((x) < (y) ? (x) : (y)) ++ ++#define device_printf(dev, a...) ({ \ ++ printk("%s: ", device_get_nameunit(dev)); printk(a); \ ++ }) ++ ++#undef printf ++#define printf(fmt...) printk(fmt) ++ ++#define KASSERT(c,p) if (!(c)) { printk p ; } else ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++#define ocf_daemonize(str) \ ++ daemonize(); \ ++ spin_lock_irq(¤t->sigmask_lock); \ ++ sigemptyset(¤t->blocked); \ ++ recalc_sigpending(current); \ ++ spin_unlock_irq(¤t->sigmask_lock); \ ++ sprintf(current->comm, str); ++#else ++#define ocf_daemonize(str) daemonize(str); ++#endif ++ ++#define TAILQ_INSERT_TAIL(q,d,m) list_add_tail(&(d)->m, (q)) ++#define TAILQ_EMPTY(q) list_empty(q) ++#define TAILQ_FOREACH(v, q, m) list_for_each_entry(v, q, m) ++ ++#define read_random(p,l) get_random_bytes(p,l) ++ ++#define DELAY(x) ((x) > 2000 ? mdelay((x)/1000) : udelay(x)) ++#define strtoul simple_strtoul ++ ++#define pci_get_vendor(dev) ((dev)->vendor) ++#define pci_get_device(dev) ((dev)->device) ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++#define pci_set_consistent_dma_mask(dev, mask) (0) ++#endif ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10) ++#define pci_dma_sync_single_for_cpu pci_dma_sync_single ++#endif ++ ++#ifndef DMA_32BIT_MASK ++#define DMA_32BIT_MASK 0x00000000ffffffffULL ++#endif ++ ++#ifndef htole32 ++#define htole32(x) cpu_to_le32(x) ++#endif ++#ifndef htobe32 ++#define htobe32(x) cpu_to_be32(x) ++#endif ++#ifndef htole16 ++#define htole16(x) cpu_to_le16(x) ++#endif ++#ifndef htobe16 ++#define htobe16(x) cpu_to_be16(x) ++#endif ++ ++/* older kernels don't have these */ ++ ++#include ++#if !defined(IRQ_NONE) && !defined(IRQ_RETVAL) ++#define IRQ_NONE ++#define IRQ_HANDLED ++#define IRQ_WAKE_THREAD ++#define IRQ_RETVAL ++#define irqreturn_t void ++typedef irqreturn_t (*irq_handler_t)(int irq, void *arg, struct pt_regs *regs); ++#endif ++#ifndef IRQF_SHARED ++#define IRQF_SHARED SA_SHIRQ ++#endif ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) ++# define strlcpy(dest,src,len) \ ++ ({strncpy(dest,src,(len)-1); ((char *)dest)[(len)-1] = '\0'; }) ++#endif ++ ++#ifndef MAX_ERRNO ++#define MAX_ERRNO 4095 ++#endif ++#ifndef IS_ERR_VALUE ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,5) ++#include ++#endif ++#ifndef IS_ERR_VALUE ++#define IS_ERR_VALUE(x) ((unsigned long)(x) >= (unsigned long)-MAX_ERRNO) ++#endif ++#endif ++ ++/* ++ * common debug for all ++ */ ++#if 1 ++#define dprintk(a...) do { if (debug) printk(a); } while(0) ++#else ++#define dprintk(a...) ++#endif ++ ++#ifndef SLAB_ATOMIC ++/* Changed in 2.6.20, must use GFP_ATOMIC now */ ++#define SLAB_ATOMIC GFP_ATOMIC ++#endif ++ ++/* ++ * need some additional support for older kernels */ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,2) ++#define pci_register_driver_compat(driver, rc) \ ++ do { \ ++ if ((rc) > 0) { \ ++ (rc) = 0; \ ++ } else if (rc == 0) { \ ++ (rc) = -ENODEV; \ ++ } else { \ ++ pci_unregister_driver(driver); \ ++ } \ ++ } while (0) ++#elif LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10) ++#define pci_register_driver_compat(driver,rc) ((rc) = (rc) < 0 ? (rc) : 0) ++#else ++#define pci_register_driver_compat(driver,rc) ++#endif ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) ++ ++#include ++#include ++ ++static inline void sg_set_page(struct scatterlist *sg, struct page *page, ++ unsigned int len, unsigned int offset) ++{ ++ sg->page = page; ++ sg->offset = offset; ++ sg->length = len; ++} ++ ++static inline void *sg_virt(struct scatterlist *sg) ++{ ++ return page_address(sg->page) + sg->offset; ++} ++ ++#define sg_init_table(sg, n) ++ ++#endif ++ ++#ifndef late_initcall ++#define late_initcall(init) module_init(init) ++#endif ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,4) || !defined(CONFIG_SMP) ++#define ocf_for_each_cpu(cpu) for ((cpu) = 0; (cpu) == 0; (cpu)++) ++#else ++#define ocf_for_each_cpu(cpu) for_each_present_cpu(cpu) ++#endif ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27) ++#include ++#define kill_proc(p,s,v) send_sig(s,find_task_by_vpid(p),0) ++#endif ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,4) ++ ++struct ocf_thread { ++ struct task_struct *task; ++ int (*func)(void *arg); ++ void *arg; ++}; ++ ++/* thread startup helper func */ ++static inline int ocf_run_thread(void *arg) ++{ ++ struct ocf_thread *t = (struct ocf_thread *) arg; ++ if (!t) ++ return -1; /* very bad */ ++ t->task = current; ++ daemonize(); ++ spin_lock_irq(¤t->sigmask_lock); ++ sigemptyset(¤t->blocked); ++ recalc_sigpending(current); ++ spin_unlock_irq(¤t->sigmask_lock); ++ return (*t->func)(t->arg); ++} ++ ++#define kthread_create(f,a,fmt...) \ ++ ({ \ ++ struct ocf_thread t; \ ++ pid_t p; \ ++ t.task = NULL; \ ++ t.func = (f); \ ++ t.arg = (a); \ ++ p = kernel_thread(ocf_run_thread, &t, CLONE_FS|CLONE_FILES); \ ++ while (p != (pid_t) -1 && t.task == NULL) \ ++ schedule(); \ ++ if (t.task) \ ++ snprintf(t.task->comm, sizeof(t.task->comm), fmt); \ ++ (t.task); \ ++ }) ++ ++#define kthread_bind(t,cpu) /**/ ++ ++#define kthread_should_stop() (strcmp(current->comm, "stopping") == 0) ++ ++#define kthread_stop(t) \ ++ ({ \ ++ strcpy((t)->comm, "stopping"); \ ++ kill_proc((t)->pid, SIGTERM, 1); \ ++ do { \ ++ schedule(); \ ++ } while (kill_proc((t)->pid, SIGTERM, 1) == 0); \ ++ }) ++ ++#else ++#include ++#endif ++ ++#endif /* __KERNEL__ */ ++ ++/****************************************************************************/ ++#endif /* _BSD_COMPAT_H_ */ +diff -Nur linux-3.1.4.orig/crypto/ocf/ocfnull/Makefile linux-3.1.4/crypto/ocf/ocfnull/Makefile +--- linux-3.1.4.orig/crypto/ocf/ocfnull/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/ocfnull/Makefile 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,12 @@ ++# for SGlinux builds ++-include $(ROOTDIR)/modules/.config ++ ++obj-$(CONFIG_OCF_OCFNULL) += ocfnull.o ++ ++obj ?= . ++EXTRA_CFLAGS += -I$(obj)/.. ++ ++ifdef TOPDIR ++-include $(TOPDIR)/Rules.make ++endif ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/ocfnull/ocfnull.c linux-3.1.4/crypto/ocf/ocfnull/ocfnull.c +--- linux-3.1.4.orig/crypto/ocf/ocfnull/ocfnull.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/ocfnull/ocfnull.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,204 @@ ++/* ++ * An OCF module for determining the cost of crypto versus the cost of ++ * IPSec processing outside of OCF. This modules gives us the effect of ++ * zero cost encryption, of course you will need to run it at both ends ++ * since it does no crypto at all. ++ * ++ * Written by David McCullough ++ * Copyright (C) 2006-2010 David McCullough ++ * ++ * LICENSE TERMS ++ * ++ * The free distribution and use of this software in both source and binary ++ * form is allowed (with or without changes) provided that: ++ * ++ * 1. distributions of this source code include the above copyright ++ * notice, this list of conditions and the following disclaimer; ++ * ++ * 2. distributions in binary form include the above copyright ++ * notice, this list of conditions and the following disclaimer ++ * in the documentation and/or other associated materials; ++ * ++ * 3. the copyright holder's name is not used to endorse products ++ * built using this software without specific written permission. ++ * ++ * ALTERNATIVELY, provided that this notice is retained in full, this product ++ * may be distributed under the terms of the GNU General Public License (GPL), ++ * in which case the provisions of the GPL apply INSTEAD OF those given above. ++ * ++ * DISCLAIMER ++ * ++ * This software is provided 'as is' with no explicit or implied warranties ++ * in respect of its properties, including, but not limited to, correctness ++ * and/or fitness for purpose. ++ */ ++ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++static int32_t null_id = -1; ++static u_int32_t null_sesnum = 0; ++ ++static int null_process(device_t, struct cryptop *, int); ++static int null_newsession(device_t, u_int32_t *, struct cryptoini *); ++static int null_freesession(device_t, u_int64_t); ++ ++#define debug ocfnull_debug ++int ocfnull_debug = 0; ++module_param(ocfnull_debug, int, 0644); ++MODULE_PARM_DESC(ocfnull_debug, "Enable debug"); ++ ++/* ++ * dummy device structure ++ */ ++ ++static struct { ++ softc_device_decl sc_dev; ++} nulldev; ++ ++static device_method_t null_methods = { ++ /* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, null_newsession), ++ DEVMETHOD(cryptodev_freesession,null_freesession), ++ DEVMETHOD(cryptodev_process, null_process), ++}; ++ ++/* ++ * Generate a new software session. ++ */ ++static int ++null_newsession(device_t arg, u_int32_t *sid, struct cryptoini *cri) ++{ ++ dprintk("%s()\n", __FUNCTION__); ++ if (sid == NULL || cri == NULL) { ++ dprintk("%s,%d - EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ if (null_sesnum == 0) ++ null_sesnum++; ++ *sid = null_sesnum++; ++ return 0; ++} ++ ++ ++/* ++ * Free a session. ++ */ ++static int ++null_freesession(device_t arg, u_int64_t tid) ++{ ++ u_int32_t sid = CRYPTO_SESID2LID(tid); ++ ++ dprintk("%s()\n", __FUNCTION__); ++ if (sid > null_sesnum) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ /* Silently accept and return */ ++ if (sid == 0) ++ return 0; ++ return 0; ++} ++ ++ ++/* ++ * Process a request. ++ */ ++static int ++null_process(device_t arg, struct cryptop *crp, int hint) ++{ ++ unsigned int lid; ++ ++ dprintk("%s()\n", __FUNCTION__); ++ ++ /* Sanity check */ ++ if (crp == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ ++ crp->crp_etype = 0; ++ ++ if (crp->crp_desc == NULL || crp->crp_buf == NULL) { ++ dprintk("%s,%d: EINVAL\n", __FILE__, __LINE__); ++ crp->crp_etype = EINVAL; ++ goto done; ++ } ++ ++ /* ++ * find the session we are using ++ */ ++ ++ lid = crp->crp_sid & 0xffffffff; ++ if (lid >= null_sesnum || lid == 0) { ++ crp->crp_etype = ENOENT; ++ dprintk("%s,%d: ENOENT\n", __FILE__, __LINE__); ++ goto done; ++ } ++ ++done: ++ crypto_done(crp); ++ return 0; ++} ++ ++ ++/* ++ * our driver startup and shutdown routines ++ */ ++ ++static int ++null_init(void) ++{ ++ dprintk("%s(%p)\n", __FUNCTION__, null_init); ++ ++ memset(&nulldev, 0, sizeof(nulldev)); ++ softc_device_init(&nulldev, "ocfnull", 0, null_methods); ++ ++ null_id = crypto_get_driverid(softc_get_device(&nulldev), ++ CRYPTOCAP_F_HARDWARE); ++ if (null_id < 0) ++ panic("ocfnull: crypto device cannot initialize!"); ++ ++#define REGISTER(alg) \ ++ crypto_register(null_id,alg,0,0) ++ REGISTER(CRYPTO_DES_CBC); ++ REGISTER(CRYPTO_3DES_CBC); ++ REGISTER(CRYPTO_RIJNDAEL128_CBC); ++ REGISTER(CRYPTO_MD5); ++ REGISTER(CRYPTO_SHA1); ++ REGISTER(CRYPTO_MD5_HMAC); ++ REGISTER(CRYPTO_SHA1_HMAC); ++#undef REGISTER ++ ++ return 0; ++} ++ ++static void ++null_exit(void) ++{ ++ dprintk("%s()\n", __FUNCTION__); ++ crypto_unregister_all(null_id); ++ null_id = -1; ++} ++ ++module_init(null_init); ++module_exit(null_exit); ++ ++MODULE_LICENSE("Dual BSD/GPL"); ++MODULE_AUTHOR("David McCullough "); ++MODULE_DESCRIPTION("ocfnull - claims a lot but does nothing"); +diff -Nur linux-3.1.4.orig/crypto/ocf/pasemi/Makefile linux-3.1.4/crypto/ocf/pasemi/Makefile +--- linux-3.1.4.orig/crypto/ocf/pasemi/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/pasemi/Makefile 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,12 @@ ++# for SGlinux builds ++-include $(ROOTDIR)/modules/.config ++ ++obj-$(CONFIG_OCF_PASEMI) += pasemi.o ++ ++obj ?= . ++EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ ++ ++ifdef TOPDIR ++-include $(TOPDIR)/Rules.make ++endif ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/pasemi/pasemi.c linux-3.1.4/crypto/ocf/pasemi/pasemi.c +--- linux-3.1.4.orig/crypto/ocf/pasemi/pasemi.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/pasemi/pasemi.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,1007 @@ ++/* ++ * Copyright (C) 2007 PA Semi, Inc ++ * ++ * Driver for the PA Semi PWRficient DMA Crypto Engine ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "pasemi_fnu.h" ++ ++#define DRV_NAME "pasemi" ++ ++#define TIMER_INTERVAL 1000 ++ ++static void __devexit pasemi_dma_remove(struct pci_dev *pdev); ++static struct pasdma_status volatile * dma_status; ++ ++static int debug; ++module_param(debug, int, 0644); ++MODULE_PARM_DESC(debug, "Enable debug"); ++ ++static void pasemi_desc_start(struct pasemi_desc *desc, u64 hdr) ++{ ++ desc->postop = 0; ++ desc->quad[0] = hdr; ++ desc->quad_cnt = 1; ++ desc->size = 1; ++} ++ ++static void pasemi_desc_build(struct pasemi_desc *desc, u64 val) ++{ ++ desc->quad[desc->quad_cnt++] = val; ++ desc->size = (desc->quad_cnt + 1) / 2; ++} ++ ++static void pasemi_desc_hdr(struct pasemi_desc *desc, u64 hdr) ++{ ++ desc->quad[0] |= hdr; ++} ++ ++static int pasemi_desc_size(struct pasemi_desc *desc) ++{ ++ return desc->size; ++} ++ ++static void pasemi_ring_add_desc( ++ struct pasemi_fnu_txring *ring, ++ struct pasemi_desc *desc, ++ struct cryptop *crp) { ++ int i; ++ int ring_index = 2 * (ring->next_to_fill & (TX_RING_SIZE-1)); ++ ++ TX_DESC_INFO(ring, ring->next_to_fill).desc_size = desc->size; ++ TX_DESC_INFO(ring, ring->next_to_fill).desc_postop = desc->postop; ++ TX_DESC_INFO(ring, ring->next_to_fill).cf_crp = crp; ++ ++ for (i = 0; i < desc->quad_cnt; i += 2) { ++ ring_index = 2 * (ring->next_to_fill & (TX_RING_SIZE-1)); ++ ring->desc[ring_index] = desc->quad[i]; ++ ring->desc[ring_index + 1] = desc->quad[i + 1]; ++ ring->next_to_fill++; ++ } ++ ++ if (desc->quad_cnt & 1) ++ ring->desc[ring_index + 1] = 0; ++} ++ ++static void pasemi_ring_incr(struct pasemi_softc *sc, int chan_index, int incr) ++{ ++ out_le32(sc->dma_regs + PAS_DMA_TXCHAN_INCR(sc->base_chan + chan_index), ++ incr); ++} ++ ++/* ++ * Generate a new software session. ++ */ ++static int ++pasemi_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) ++{ ++ struct cryptoini *c, *encini = NULL, *macini = NULL; ++ struct pasemi_softc *sc = device_get_softc(dev); ++ struct pasemi_session *ses = NULL, **sespp; ++ int sesn, blksz = 0; ++ u64 ccmd = 0; ++ unsigned long flags; ++ struct pasemi_desc init_desc; ++ struct pasemi_fnu_txring *txring; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ if (sidp == NULL || cri == NULL || sc == NULL) { ++ DPRINTF("%s,%d - EINVAL\n", __FILE__, __LINE__); ++ return -EINVAL; ++ } ++ for (c = cri; c != NULL; c = c->cri_next) { ++ if (ALG_IS_SIG(c->cri_alg)) { ++ if (macini) ++ return -EINVAL; ++ macini = c; ++ } else if (ALG_IS_CIPHER(c->cri_alg)) { ++ if (encini) ++ return -EINVAL; ++ encini = c; ++ } else { ++ DPRINTF("UNKNOWN c->cri_alg %d\n", c->cri_alg); ++ return -EINVAL; ++ } ++ } ++ if (encini == NULL && macini == NULL) ++ return -EINVAL; ++ if (encini) { ++ /* validate key length */ ++ switch (encini->cri_alg) { ++ case CRYPTO_DES_CBC: ++ if (encini->cri_klen != 64) ++ return -EINVAL; ++ ccmd = DMA_CALGO_DES; ++ break; ++ case CRYPTO_3DES_CBC: ++ if (encini->cri_klen != 192) ++ return -EINVAL; ++ ccmd = DMA_CALGO_3DES; ++ break; ++ case CRYPTO_AES_CBC: ++ if (encini->cri_klen != 128 && ++ encini->cri_klen != 192 && ++ encini->cri_klen != 256) ++ return -EINVAL; ++ ccmd = DMA_CALGO_AES; ++ break; ++ case CRYPTO_ARC4: ++ if (encini->cri_klen != 128) ++ return -EINVAL; ++ ccmd = DMA_CALGO_ARC; ++ break; ++ default: ++ DPRINTF("UNKNOWN encini->cri_alg %d\n", ++ encini->cri_alg); ++ return -EINVAL; ++ } ++ } ++ ++ if (macini) { ++ switch (macini->cri_alg) { ++ case CRYPTO_MD5: ++ case CRYPTO_MD5_HMAC: ++ blksz = 16; ++ break; ++ case CRYPTO_SHA1: ++ case CRYPTO_SHA1_HMAC: ++ blksz = 20; ++ break; ++ default: ++ DPRINTF("UNKNOWN macini->cri_alg %d\n", ++ macini->cri_alg); ++ return -EINVAL; ++ } ++ if (((macini->cri_klen + 7) / 8) > blksz) { ++ DPRINTF("key length %d bigger than blksize %d not supported\n", ++ ((macini->cri_klen + 7) / 8), blksz); ++ return -EINVAL; ++ } ++ } ++ ++ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { ++ if (sc->sc_sessions[sesn] == NULL) { ++ sc->sc_sessions[sesn] = (struct pasemi_session *) ++ kzalloc(sizeof(struct pasemi_session), GFP_ATOMIC); ++ ses = sc->sc_sessions[sesn]; ++ break; ++ } else if (sc->sc_sessions[sesn]->used == 0) { ++ ses = sc->sc_sessions[sesn]; ++ break; ++ } ++ } ++ ++ if (ses == NULL) { ++ sespp = (struct pasemi_session **) ++ kzalloc(sc->sc_nsessions * 2 * ++ sizeof(struct pasemi_session *), GFP_ATOMIC); ++ if (sespp == NULL) ++ return -ENOMEM; ++ memcpy(sespp, sc->sc_sessions, ++ sc->sc_nsessions * sizeof(struct pasemi_session *)); ++ kfree(sc->sc_sessions); ++ sc->sc_sessions = sespp; ++ sesn = sc->sc_nsessions; ++ ses = sc->sc_sessions[sesn] = (struct pasemi_session *) ++ kzalloc(sizeof(struct pasemi_session), GFP_ATOMIC); ++ if (ses == NULL) ++ return -ENOMEM; ++ sc->sc_nsessions *= 2; ++ } ++ ++ ses->used = 1; ++ ++ ses->dma_addr = pci_map_single(sc->dma_pdev, (void *) ses->civ, ++ sizeof(struct pasemi_session), DMA_TO_DEVICE); ++ ++ /* enter the channel scheduler */ ++ spin_lock_irqsave(&sc->sc_chnlock, flags); ++ ++ /* ARC4 has to be processed by the even channel */ ++ if (encini && (encini->cri_alg == CRYPTO_ARC4)) ++ ses->chan = sc->sc_lastchn & ~1; ++ else ++ ses->chan = sc->sc_lastchn; ++ sc->sc_lastchn = (sc->sc_lastchn + 1) % sc->sc_num_channels; ++ ++ spin_unlock_irqrestore(&sc->sc_chnlock, flags); ++ ++ txring = &sc->tx[ses->chan]; ++ ++ if (encini) { ++ ses->ccmd = ccmd; ++ ses->keysz = (encini->cri_klen - 63) / 64; ++ memcpy(ses->key, encini->cri_key, (ses->keysz + 1) * 8); ++ ++ pasemi_desc_start(&init_desc, ++ XCT_CTRL_HDR(ses->chan, (encini && macini) ? 0x68 : 0x40, DMA_FN_CIV0)); ++ pasemi_desc_build(&init_desc, ++ XCT_FUN_SRC_PTR((encini && macini) ? 0x68 : 0x40, ses->dma_addr)); ++ } ++ if (macini) { ++ if (macini->cri_alg == CRYPTO_MD5_HMAC || ++ macini->cri_alg == CRYPTO_SHA1_HMAC) ++ memcpy(ses->hkey, macini->cri_key, blksz); ++ else { ++ /* Load initialization constants(RFC 1321, 3174) */ ++ ses->hiv[0] = 0x67452301efcdab89ULL; ++ ses->hiv[1] = 0x98badcfe10325476ULL; ++ ses->hiv[2] = 0xc3d2e1f000000000ULL; ++ } ++ ses->hseq = 0ULL; ++ } ++ ++ spin_lock_irqsave(&txring->fill_lock, flags); ++ ++ if (((txring->next_to_fill + pasemi_desc_size(&init_desc)) - ++ txring->next_to_clean) > TX_RING_SIZE) { ++ spin_unlock_irqrestore(&txring->fill_lock, flags); ++ return ERESTART; ++ } ++ ++ if (encini) { ++ pasemi_ring_add_desc(txring, &init_desc, NULL); ++ pasemi_ring_incr(sc, ses->chan, ++ pasemi_desc_size(&init_desc)); ++ } ++ ++ txring->sesn = sesn; ++ spin_unlock_irqrestore(&txring->fill_lock, flags); ++ ++ *sidp = PASEMI_SID(sesn); ++ return 0; ++} ++ ++/* ++ * Deallocate a session. ++ */ ++static int ++pasemi_freesession(device_t dev, u_int64_t tid) ++{ ++ struct pasemi_softc *sc = device_get_softc(dev); ++ int session; ++ u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ if (sc == NULL) ++ return -EINVAL; ++ session = PASEMI_SESSION(sid); ++ if (session >= sc->sc_nsessions || !sc->sc_sessions[session]) ++ return -EINVAL; ++ ++ pci_unmap_single(sc->dma_pdev, ++ sc->sc_sessions[session]->dma_addr, ++ sizeof(struct pasemi_session), DMA_TO_DEVICE); ++ memset(sc->sc_sessions[session], 0, ++ sizeof(struct pasemi_session)); ++ ++ return 0; ++} ++ ++static int ++pasemi_process(device_t dev, struct cryptop *crp, int hint) ++{ ++ ++ int err = 0, ivsize, srclen = 0, reinit = 0, reinit_size = 0, chsel; ++ struct pasemi_softc *sc = device_get_softc(dev); ++ struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; ++ caddr_t ivp; ++ struct pasemi_desc init_desc, work_desc; ++ struct pasemi_session *ses; ++ struct sk_buff *skb; ++ struct uio *uiop; ++ unsigned long flags; ++ struct pasemi_fnu_txring *txring; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ if (crp == NULL || crp->crp_callback == NULL || sc == NULL) ++ return -EINVAL; ++ ++ crp->crp_etype = 0; ++ if (PASEMI_SESSION(crp->crp_sid) >= sc->sc_nsessions) ++ return -EINVAL; ++ ++ ses = sc->sc_sessions[PASEMI_SESSION(crp->crp_sid)]; ++ ++ crd1 = crp->crp_desc; ++ if (crd1 == NULL) { ++ err = -EINVAL; ++ goto errout; ++ } ++ crd2 = crd1->crd_next; ++ ++ if (ALG_IS_SIG(crd1->crd_alg)) { ++ maccrd = crd1; ++ if (crd2 == NULL) ++ enccrd = NULL; ++ else if (ALG_IS_CIPHER(crd2->crd_alg) && ++ (crd2->crd_flags & CRD_F_ENCRYPT) == 0) ++ enccrd = crd2; ++ else ++ goto erralg; ++ } else if (ALG_IS_CIPHER(crd1->crd_alg)) { ++ enccrd = crd1; ++ if (crd2 == NULL) ++ maccrd = NULL; ++ else if (ALG_IS_SIG(crd2->crd_alg) && ++ (crd1->crd_flags & CRD_F_ENCRYPT)) ++ maccrd = crd2; ++ else ++ goto erralg; ++ } else ++ goto erralg; ++ ++ chsel = ses->chan; ++ ++ txring = &sc->tx[chsel]; ++ ++ if (enccrd && !maccrd) { ++ if (enccrd->crd_alg == CRYPTO_ARC4) ++ reinit = 1; ++ reinit_size = 0x40; ++ srclen = crp->crp_ilen; ++ ++ pasemi_desc_start(&work_desc, XCT_FUN_O | XCT_FUN_I ++ | XCT_FUN_FUN(chsel)); ++ if (enccrd->crd_flags & CRD_F_ENCRYPT) ++ pasemi_desc_hdr(&work_desc, XCT_FUN_CRM_ENC); ++ else ++ pasemi_desc_hdr(&work_desc, XCT_FUN_CRM_DEC); ++ } else if (enccrd && maccrd) { ++ if (enccrd->crd_alg == CRYPTO_ARC4) ++ reinit = 1; ++ reinit_size = 0x68; ++ ++ if (enccrd->crd_flags & CRD_F_ENCRYPT) { ++ /* Encrypt -> Authenticate */ ++ pasemi_desc_start(&work_desc, XCT_FUN_O | XCT_FUN_I | XCT_FUN_CRM_ENC_SIG ++ | XCT_FUN_A | XCT_FUN_FUN(chsel)); ++ srclen = maccrd->crd_skip + maccrd->crd_len; ++ } else { ++ /* Authenticate -> Decrypt */ ++ pasemi_desc_start(&work_desc, XCT_FUN_O | XCT_FUN_I | XCT_FUN_CRM_SIG_DEC ++ | XCT_FUN_24BRES | XCT_FUN_FUN(chsel)); ++ pasemi_desc_build(&work_desc, 0); ++ pasemi_desc_build(&work_desc, 0); ++ pasemi_desc_build(&work_desc, 0); ++ work_desc.postop = PASEMI_CHECK_SIG; ++ srclen = crp->crp_ilen; ++ } ++ ++ pasemi_desc_hdr(&work_desc, XCT_FUN_SHL(maccrd->crd_skip / 4)); ++ pasemi_desc_hdr(&work_desc, XCT_FUN_CHL(enccrd->crd_skip - maccrd->crd_skip)); ++ } else if (!enccrd && maccrd) { ++ srclen = maccrd->crd_len; ++ ++ pasemi_desc_start(&init_desc, ++ XCT_CTRL_HDR(chsel, 0x58, DMA_FN_HKEY0)); ++ pasemi_desc_build(&init_desc, ++ XCT_FUN_SRC_PTR(0x58, ((struct pasemi_session *)ses->dma_addr)->hkey)); ++ ++ pasemi_desc_start(&work_desc, XCT_FUN_O | XCT_FUN_I | XCT_FUN_CRM_SIG ++ | XCT_FUN_A | XCT_FUN_FUN(chsel)); ++ } ++ ++ if (enccrd) { ++ switch (enccrd->crd_alg) { ++ case CRYPTO_3DES_CBC: ++ pasemi_desc_hdr(&work_desc, XCT_FUN_ALG_3DES | ++ XCT_FUN_BCM_CBC); ++ ivsize = sizeof(u64); ++ break; ++ case CRYPTO_DES_CBC: ++ pasemi_desc_hdr(&work_desc, XCT_FUN_ALG_DES | ++ XCT_FUN_BCM_CBC); ++ ivsize = sizeof(u64); ++ break; ++ case CRYPTO_AES_CBC: ++ pasemi_desc_hdr(&work_desc, XCT_FUN_ALG_AES | ++ XCT_FUN_BCM_CBC); ++ ivsize = 2 * sizeof(u64); ++ break; ++ case CRYPTO_ARC4: ++ pasemi_desc_hdr(&work_desc, XCT_FUN_ALG_ARC); ++ ivsize = 0; ++ break; ++ default: ++ printk(DRV_NAME ": unimplemented enccrd->crd_alg %d\n", ++ enccrd->crd_alg); ++ err = -EINVAL; ++ goto errout; ++ } ++ ++ ivp = (ivsize == sizeof(u64)) ? (caddr_t) &ses->civ[1] : (caddr_t) &ses->civ[0]; ++ if (enccrd->crd_flags & CRD_F_ENCRYPT) { ++ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) ++ memcpy(ivp, enccrd->crd_iv, ivsize); ++ else ++ read_random(ivp, ivsize); ++ /* If IV is not present in the buffer already, it has to be copied there */ ++ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ enccrd->crd_inject, ivsize, ivp); ++ } else { ++ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) ++ /* IV is provided expicitly in descriptor */ ++ memcpy(ivp, enccrd->crd_iv, ivsize); ++ else ++ /* IV is provided in the packet */ ++ crypto_copydata(crp->crp_flags, crp->crp_buf, ++ enccrd->crd_inject, ivsize, ++ ivp); ++ } ++ } ++ ++ if (maccrd) { ++ switch (maccrd->crd_alg) { ++ case CRYPTO_MD5: ++ pasemi_desc_hdr(&work_desc, XCT_FUN_SIG_MD5 | ++ XCT_FUN_HSZ((crp->crp_ilen - maccrd->crd_inject) / 4)); ++ break; ++ case CRYPTO_SHA1: ++ pasemi_desc_hdr(&work_desc, XCT_FUN_SIG_SHA1 | ++ XCT_FUN_HSZ((crp->crp_ilen - maccrd->crd_inject) / 4)); ++ break; ++ case CRYPTO_MD5_HMAC: ++ pasemi_desc_hdr(&work_desc, XCT_FUN_SIG_HMAC_MD5 | ++ XCT_FUN_HSZ((crp->crp_ilen - maccrd->crd_inject) / 4)); ++ break; ++ case CRYPTO_SHA1_HMAC: ++ pasemi_desc_hdr(&work_desc, XCT_FUN_SIG_HMAC_SHA1 | ++ XCT_FUN_HSZ((crp->crp_ilen - maccrd->crd_inject) / 4)); ++ break; ++ default: ++ printk(DRV_NAME ": unimplemented maccrd->crd_alg %d\n", ++ maccrd->crd_alg); ++ err = -EINVAL; ++ goto errout; ++ } ++ } ++ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ /* using SKB buffers */ ++ skb = (struct sk_buff *)crp->crp_buf; ++ if (skb_shinfo(skb)->nr_frags) { ++ printk(DRV_NAME ": skb frags unimplemented\n"); ++ err = -EINVAL; ++ goto errout; ++ } ++ pasemi_desc_build( ++ &work_desc, ++ XCT_FUN_DST_PTR(skb->len, pci_map_single( ++ sc->dma_pdev, skb->data, ++ skb->len, DMA_TO_DEVICE))); ++ pasemi_desc_build( ++ &work_desc, ++ XCT_FUN_SRC_PTR( ++ srclen, pci_map_single( ++ sc->dma_pdev, skb->data, ++ srclen, DMA_TO_DEVICE))); ++ pasemi_desc_hdr(&work_desc, XCT_FUN_LLEN(srclen)); ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ /* using IOV buffers */ ++ uiop = (struct uio *)crp->crp_buf; ++ if (uiop->uio_iovcnt > 1) { ++ printk(DRV_NAME ": iov frags unimplemented\n"); ++ err = -EINVAL; ++ goto errout; ++ } ++ ++ /* crp_olen is never set; always use crp_ilen */ ++ pasemi_desc_build( ++ &work_desc, ++ XCT_FUN_DST_PTR(crp->crp_ilen, pci_map_single( ++ sc->dma_pdev, ++ uiop->uio_iov->iov_base, ++ crp->crp_ilen, DMA_TO_DEVICE))); ++ pasemi_desc_hdr(&work_desc, XCT_FUN_LLEN(srclen)); ++ ++ pasemi_desc_build( ++ &work_desc, ++ XCT_FUN_SRC_PTR(srclen, pci_map_single( ++ sc->dma_pdev, ++ uiop->uio_iov->iov_base, ++ srclen, DMA_TO_DEVICE))); ++ } else { ++ /* using contig buffers */ ++ pasemi_desc_build( ++ &work_desc, ++ XCT_FUN_DST_PTR(crp->crp_ilen, pci_map_single( ++ sc->dma_pdev, ++ crp->crp_buf, ++ crp->crp_ilen, DMA_TO_DEVICE))); ++ pasemi_desc_build( ++ &work_desc, ++ XCT_FUN_SRC_PTR(srclen, pci_map_single( ++ sc->dma_pdev, ++ crp->crp_buf, srclen, ++ DMA_TO_DEVICE))); ++ pasemi_desc_hdr(&work_desc, XCT_FUN_LLEN(srclen)); ++ } ++ ++ spin_lock_irqsave(&txring->fill_lock, flags); ++ ++ if (txring->sesn != PASEMI_SESSION(crp->crp_sid)) { ++ txring->sesn = PASEMI_SESSION(crp->crp_sid); ++ reinit = 1; ++ } ++ ++ if (enccrd) { ++ pasemi_desc_start(&init_desc, ++ XCT_CTRL_HDR(chsel, reinit ? reinit_size : 0x10, DMA_FN_CIV0)); ++ pasemi_desc_build(&init_desc, ++ XCT_FUN_SRC_PTR(reinit ? reinit_size : 0x10, ses->dma_addr)); ++ } ++ ++ if (((txring->next_to_fill + pasemi_desc_size(&init_desc) + ++ pasemi_desc_size(&work_desc)) - ++ txring->next_to_clean) > TX_RING_SIZE) { ++ spin_unlock_irqrestore(&txring->fill_lock, flags); ++ err = ERESTART; ++ goto errout; ++ } ++ ++ pasemi_ring_add_desc(txring, &init_desc, NULL); ++ pasemi_ring_add_desc(txring, &work_desc, crp); ++ ++ pasemi_ring_incr(sc, chsel, ++ pasemi_desc_size(&init_desc) + ++ pasemi_desc_size(&work_desc)); ++ ++ spin_unlock_irqrestore(&txring->fill_lock, flags); ++ ++ mod_timer(&txring->crypto_timer, jiffies + TIMER_INTERVAL); ++ ++ return 0; ++ ++erralg: ++ printk(DRV_NAME ": unsupported algorithm or algorithm order alg1 %d alg2 %d\n", ++ crd1->crd_alg, crd2->crd_alg); ++ err = -EINVAL; ++ ++errout: ++ if (err != ERESTART) { ++ crp->crp_etype = err; ++ crypto_done(crp); ++ } ++ return err; ++} ++ ++static int pasemi_clean_tx(struct pasemi_softc *sc, int chan) ++{ ++ int i, j, ring_idx; ++ struct pasemi_fnu_txring *ring = &sc->tx[chan]; ++ u16 delta_cnt; ++ int flags, loops = 10; ++ int desc_size; ++ struct cryptop *crp; ++ ++ spin_lock_irqsave(&ring->clean_lock, flags); ++ ++ while ((delta_cnt = (dma_status->tx_sta[sc->base_chan + chan] ++ & PAS_STATUS_PCNT_M) - ring->total_pktcnt) ++ && loops--) { ++ ++ for (i = 0; i < delta_cnt; i++) { ++ desc_size = TX_DESC_INFO(ring, ring->next_to_clean).desc_size; ++ crp = TX_DESC_INFO(ring, ring->next_to_clean).cf_crp; ++ if (crp) { ++ ring_idx = 2 * (ring->next_to_clean & (TX_RING_SIZE-1)); ++ if (TX_DESC_INFO(ring, ring->next_to_clean).desc_postop & PASEMI_CHECK_SIG) { ++ /* Need to make sure signature matched, ++ * if not - return error */ ++ if (!(ring->desc[ring_idx + 1] & (1ULL << 63))) ++ crp->crp_etype = -EINVAL; ++ } ++ crypto_done(TX_DESC_INFO(ring, ++ ring->next_to_clean).cf_crp); ++ TX_DESC_INFO(ring, ring->next_to_clean).cf_crp = NULL; ++ pci_unmap_single( ++ sc->dma_pdev, ++ XCT_PTR_ADDR_LEN(ring->desc[ring_idx + 1]), ++ PCI_DMA_TODEVICE); ++ ++ ring->desc[ring_idx] = ring->desc[ring_idx + 1] = 0; ++ ++ ring->next_to_clean++; ++ for (j = 1; j < desc_size; j++) { ++ ring_idx = 2 * ++ (ring->next_to_clean & ++ (TX_RING_SIZE-1)); ++ pci_unmap_single( ++ sc->dma_pdev, ++ XCT_PTR_ADDR_LEN(ring->desc[ring_idx]), ++ PCI_DMA_TODEVICE); ++ if (ring->desc[ring_idx + 1]) ++ pci_unmap_single( ++ sc->dma_pdev, ++ XCT_PTR_ADDR_LEN( ++ ring->desc[ ++ ring_idx + 1]), ++ PCI_DMA_TODEVICE); ++ ring->desc[ring_idx] = ++ ring->desc[ring_idx + 1] = 0; ++ ring->next_to_clean++; ++ } ++ } else { ++ for (j = 0; j < desc_size; j++) { ++ ring_idx = 2 * (ring->next_to_clean & (TX_RING_SIZE-1)); ++ ring->desc[ring_idx] = ++ ring->desc[ring_idx + 1] = 0; ++ ring->next_to_clean++; ++ } ++ } ++ } ++ ++ ring->total_pktcnt += delta_cnt; ++ } ++ spin_unlock_irqrestore(&ring->clean_lock, flags); ++ ++ return 0; ++} ++ ++static void sweepup_tx(struct pasemi_softc *sc) ++{ ++ int i; ++ ++ for (i = 0; i < sc->sc_num_channels; i++) ++ pasemi_clean_tx(sc, i); ++} ++ ++static irqreturn_t pasemi_intr(int irq, void *arg, struct pt_regs *regs) ++{ ++ struct pasemi_softc *sc = arg; ++ unsigned int reg; ++ int chan = irq - sc->base_irq; ++ int chan_index = sc->base_chan + chan; ++ u64 stat = dma_status->tx_sta[chan_index]; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ if (!(stat & PAS_STATUS_CAUSE_M)) ++ return IRQ_NONE; ++ ++ pasemi_clean_tx(sc, chan); ++ ++ stat = dma_status->tx_sta[chan_index]; ++ ++ reg = PAS_IOB_DMA_TXCH_RESET_PINTC | ++ PAS_IOB_DMA_TXCH_RESET_PCNT(sc->tx[chan].total_pktcnt); ++ ++ if (stat & PAS_STATUS_SOFT) ++ reg |= PAS_IOB_DMA_RXCH_RESET_SINTC; ++ ++ out_le32(sc->iob_regs + PAS_IOB_DMA_TXCH_RESET(chan_index), reg); ++ ++ ++ return IRQ_HANDLED; ++} ++ ++static int pasemi_dma_setup_tx_resources(struct pasemi_softc *sc, int chan) ++{ ++ u32 val; ++ int chan_index = chan + sc->base_chan; ++ int ret; ++ struct pasemi_fnu_txring *ring; ++ ++ ring = &sc->tx[chan]; ++ ++ spin_lock_init(&ring->fill_lock); ++ spin_lock_init(&ring->clean_lock); ++ ++ ring->desc_info = kzalloc(sizeof(struct pasemi_desc_info) * ++ TX_RING_SIZE, GFP_KERNEL); ++ if (!ring->desc_info) ++ return -ENOMEM; ++ ++ /* Allocate descriptors */ ++ ring->desc = dma_alloc_coherent(&sc->dma_pdev->dev, ++ TX_RING_SIZE * ++ 2 * sizeof(u64), ++ &ring->dma, GFP_KERNEL); ++ if (!ring->desc) ++ return -ENOMEM; ++ ++ memset((void *) ring->desc, 0, TX_RING_SIZE * 2 * sizeof(u64)); ++ ++ out_le32(sc->iob_regs + PAS_IOB_DMA_TXCH_RESET(chan_index), 0x30); ++ ++ ring->total_pktcnt = 0; ++ ++ out_le32(sc->dma_regs + PAS_DMA_TXCHAN_BASEL(chan_index), ++ PAS_DMA_TXCHAN_BASEL_BRBL(ring->dma)); ++ ++ val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->dma >> 32); ++ val |= PAS_DMA_TXCHAN_BASEU_SIZ(TX_RING_SIZE >> 2); ++ ++ out_le32(sc->dma_regs + PAS_DMA_TXCHAN_BASEU(chan_index), val); ++ ++ out_le32(sc->dma_regs + PAS_DMA_TXCHAN_CFG(chan_index), ++ PAS_DMA_TXCHAN_CFG_TY_FUNC | ++ PAS_DMA_TXCHAN_CFG_TATTR(chan) | ++ PAS_DMA_TXCHAN_CFG_WT(2)); ++ ++ /* enable tx channel */ ++ out_le32(sc->dma_regs + ++ PAS_DMA_TXCHAN_TCMDSTA(chan_index), ++ PAS_DMA_TXCHAN_TCMDSTA_EN); ++ ++ out_le32(sc->iob_regs + PAS_IOB_DMA_TXCH_CFG(chan_index), ++ PAS_IOB_DMA_TXCH_CFG_CNTTH(1000)); ++ ++ ring->next_to_fill = 0; ++ ring->next_to_clean = 0; ++ ++ snprintf(ring->irq_name, sizeof(ring->irq_name), ++ "%s%d", "crypto", chan); ++ ++ ring->irq = irq_create_mapping(NULL, sc->base_irq + chan); ++ ret = request_irq(ring->irq, (irq_handler_t) ++ pasemi_intr, IRQF_DISABLED, ring->irq_name, sc); ++ if (ret) { ++ printk(KERN_ERR DRV_NAME ": failed to hook irq %d ret %d\n", ++ ring->irq, ret); ++ ring->irq = -1; ++ return ret; ++ } ++ ++ setup_timer(&ring->crypto_timer, (void *) sweepup_tx, (unsigned long) sc); ++ ++ return 0; ++} ++ ++static device_method_t pasemi_methods = { ++ /* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, pasemi_newsession), ++ DEVMETHOD(cryptodev_freesession, pasemi_freesession), ++ DEVMETHOD(cryptodev_process, pasemi_process), ++}; ++ ++/* Set up the crypto device structure, private data, ++ * and anything else we need before we start */ ++ ++static int __devinit ++pasemi_dma_probe(struct pci_dev *pdev, const struct pci_device_id *ent) ++{ ++ struct pasemi_softc *sc; ++ int ret, i; ++ ++ DPRINTF(KERN_ERR "%s()\n", __FUNCTION__); ++ ++ sc = kzalloc(sizeof(*sc), GFP_KERNEL); ++ if (!sc) ++ return -ENOMEM; ++ ++ softc_device_init(sc, DRV_NAME, 1, pasemi_methods); ++ ++ pci_set_drvdata(pdev, sc); ++ ++ spin_lock_init(&sc->sc_chnlock); ++ ++ sc->sc_sessions = (struct pasemi_session **) ++ kzalloc(PASEMI_INITIAL_SESSIONS * ++ sizeof(struct pasemi_session *), GFP_ATOMIC); ++ if (sc->sc_sessions == NULL) { ++ ret = -ENOMEM; ++ goto out; ++ } ++ ++ sc->sc_nsessions = PASEMI_INITIAL_SESSIONS; ++ sc->sc_lastchn = 0; ++ sc->base_irq = pdev->irq + 6; ++ sc->base_chan = 6; ++ sc->sc_cid = -1; ++ sc->dma_pdev = pdev; ++ ++ sc->iob_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL); ++ if (!sc->iob_pdev) { ++ dev_err(&pdev->dev, "Can't find I/O Bridge\n"); ++ ret = -ENODEV; ++ goto out; ++ } ++ ++ /* This is hardcoded and ugly, but we have some firmware versions ++ * who don't provide the register space in the device tree. Luckily ++ * they are at well-known locations so we can just do the math here. ++ */ ++ sc->dma_regs = ++ ioremap(0xe0000000 + (sc->dma_pdev->devfn << 12), 0x2000); ++ sc->iob_regs = ++ ioremap(0xe0000000 + (sc->iob_pdev->devfn << 12), 0x2000); ++ if (!sc->dma_regs || !sc->iob_regs) { ++ dev_err(&pdev->dev, "Can't map registers\n"); ++ ret = -ENODEV; ++ goto out; ++ } ++ ++ dma_status = __ioremap(0xfd800000, 0x1000, 0); ++ if (!dma_status) { ++ ret = -ENODEV; ++ dev_err(&pdev->dev, "Can't map dmastatus space\n"); ++ goto out; ++ } ++ ++ sc->tx = (struct pasemi_fnu_txring *) ++ kzalloc(sizeof(struct pasemi_fnu_txring) ++ * 8, GFP_KERNEL); ++ if (!sc->tx) { ++ ret = -ENOMEM; ++ goto out; ++ } ++ ++ /* Initialize the h/w */ ++ out_le32(sc->dma_regs + PAS_DMA_COM_CFG, ++ (in_le32(sc->dma_regs + PAS_DMA_COM_CFG) | ++ PAS_DMA_COM_CFG_FWF)); ++ out_le32(sc->dma_regs + PAS_DMA_COM_TXCMD, PAS_DMA_COM_TXCMD_EN); ++ ++ for (i = 0; i < PASEMI_FNU_CHANNELS; i++) { ++ sc->sc_num_channels++; ++ ret = pasemi_dma_setup_tx_resources(sc, i); ++ if (ret) ++ goto out; ++ } ++ ++ sc->sc_cid = crypto_get_driverid(softc_get_device(sc), ++ CRYPTOCAP_F_HARDWARE); ++ if (sc->sc_cid < 0) { ++ printk(KERN_ERR DRV_NAME ": could not get crypto driver id\n"); ++ ret = -ENXIO; ++ goto out; ++ } ++ ++ /* register algorithms with the framework */ ++ printk(DRV_NAME ":"); ++ ++ crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); ++ ++ return 0; ++ ++out: ++ pasemi_dma_remove(pdev); ++ return ret; ++} ++ ++#define MAX_RETRIES 5000 ++ ++static void pasemi_free_tx_resources(struct pasemi_softc *sc, int chan) ++{ ++ struct pasemi_fnu_txring *ring = &sc->tx[chan]; ++ int chan_index = chan + sc->base_chan; ++ int retries; ++ u32 stat; ++ ++ /* Stop the channel */ ++ out_le32(sc->dma_regs + ++ PAS_DMA_TXCHAN_TCMDSTA(chan_index), ++ PAS_DMA_TXCHAN_TCMDSTA_ST); ++ ++ for (retries = 0; retries < MAX_RETRIES; retries++) { ++ stat = in_le32(sc->dma_regs + ++ PAS_DMA_TXCHAN_TCMDSTA(chan_index)); ++ if (!(stat & PAS_DMA_TXCHAN_TCMDSTA_ACT)) ++ break; ++ cond_resched(); ++ } ++ ++ if (stat & PAS_DMA_TXCHAN_TCMDSTA_ACT) ++ dev_err(&sc->dma_pdev->dev, "Failed to stop tx channel %d\n", ++ chan_index); ++ ++ /* Disable the channel */ ++ out_le32(sc->dma_regs + ++ PAS_DMA_TXCHAN_TCMDSTA(chan_index), ++ 0); ++ ++ if (ring->desc_info) ++ kfree((void *) ring->desc_info); ++ if (ring->desc) ++ dma_free_coherent(&sc->dma_pdev->dev, ++ TX_RING_SIZE * ++ 2 * sizeof(u64), ++ (void *) ring->desc, ring->dma); ++ if (ring->irq != -1) ++ free_irq(ring->irq, sc); ++ ++ del_timer(&ring->crypto_timer); ++} ++ ++static void __devexit pasemi_dma_remove(struct pci_dev *pdev) ++{ ++ struct pasemi_softc *sc = pci_get_drvdata(pdev); ++ int i; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ if (sc->sc_cid >= 0) { ++ crypto_unregister_all(sc->sc_cid); ++ } ++ ++ if (sc->tx) { ++ for (i = 0; i < sc->sc_num_channels; i++) ++ pasemi_free_tx_resources(sc, i); ++ ++ kfree(sc->tx); ++ } ++ if (sc->sc_sessions) { ++ for (i = 0; i < sc->sc_nsessions; i++) ++ kfree(sc->sc_sessions[i]); ++ kfree(sc->sc_sessions); ++ } ++ if (sc->iob_pdev) ++ pci_dev_put(sc->iob_pdev); ++ if (sc->dma_regs) ++ iounmap(sc->dma_regs); ++ if (sc->iob_regs) ++ iounmap(sc->iob_regs); ++ kfree(sc); ++} ++ ++static struct pci_device_id pasemi_dma_pci_tbl[] = { ++ { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa007) }, ++}; ++ ++MODULE_DEVICE_TABLE(pci, pasemi_dma_pci_tbl); ++ ++static struct pci_driver pasemi_dma_driver = { ++ .name = "pasemi_dma", ++ .id_table = pasemi_dma_pci_tbl, ++ .probe = pasemi_dma_probe, ++ .remove = __devexit_p(pasemi_dma_remove), ++}; ++ ++static void __exit pasemi_dma_cleanup_module(void) ++{ ++ pci_unregister_driver(&pasemi_dma_driver); ++ __iounmap(dma_status); ++ dma_status = NULL; ++} ++ ++int pasemi_dma_init_module(void) ++{ ++ return pci_register_driver(&pasemi_dma_driver); ++} ++ ++module_init(pasemi_dma_init_module); ++module_exit(pasemi_dma_cleanup_module); ++ ++MODULE_LICENSE("Dual BSD/GPL"); ++MODULE_AUTHOR("Egor Martovetsky egor@pasemi.com"); ++MODULE_DESCRIPTION("OCF driver for PA Semi PWRficient DMA Crypto Engine"); +diff -Nur linux-3.1.4.orig/crypto/ocf/pasemi/pasemi_fnu.h linux-3.1.4/crypto/ocf/pasemi/pasemi_fnu.h +--- linux-3.1.4.orig/crypto/ocf/pasemi/pasemi_fnu.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/pasemi/pasemi_fnu.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,410 @@ ++/* ++ * Copyright (C) 2007 PA Semi, Inc ++ * ++ * Driver for the PA Semi PWRficient DMA Crypto Engine, soft state and ++ * hardware register layouts. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef PASEMI_FNU_H ++#define PASEMI_FNU_H ++ ++#include ++ ++#define PASEMI_SESSION(sid) ((sid) & 0xffffffff) ++#define PASEMI_SID(sesn) ((sesn) & 0xffffffff) ++#define DPRINTF(a...) if (debug) { printk(DRV_NAME ": " a); } ++ ++/* Must be a power of two */ ++#define RX_RING_SIZE 512 ++#define TX_RING_SIZE 512 ++#define TX_DESC(ring, num) ((ring)->desc[2 * (num & (TX_RING_SIZE-1))]) ++#define TX_DESC_INFO(ring, num) ((ring)->desc_info[(num) & (TX_RING_SIZE-1)]) ++#define MAX_DESC_SIZE 8 ++#define PASEMI_INITIAL_SESSIONS 10 ++#define PASEMI_FNU_CHANNELS 8 ++ ++/* DMA descriptor */ ++struct pasemi_desc { ++ u64 quad[2*MAX_DESC_SIZE]; ++ int quad_cnt; ++ int size; ++ int postop; ++}; ++ ++/* ++ * Holds per descriptor data ++ */ ++struct pasemi_desc_info { ++ int desc_size; ++ int desc_postop; ++#define PASEMI_CHECK_SIG 0x1 ++ ++ struct cryptop *cf_crp; ++}; ++ ++/* ++ * Holds per channel data ++ */ ++struct pasemi_fnu_txring { ++ volatile u64 *desc; ++ volatile struct ++ pasemi_desc_info *desc_info; ++ dma_addr_t dma; ++ struct timer_list crypto_timer; ++ spinlock_t fill_lock; ++ spinlock_t clean_lock; ++ unsigned int next_to_fill; ++ unsigned int next_to_clean; ++ u16 total_pktcnt; ++ int irq; ++ int sesn; ++ char irq_name[10]; ++}; ++ ++/* ++ * Holds data specific to a single pasemi device. ++ */ ++struct pasemi_softc { ++ softc_device_decl sc_cdev; ++ struct pci_dev *dma_pdev; /* device backpointer */ ++ struct pci_dev *iob_pdev; /* device backpointer */ ++ void __iomem *dma_regs; ++ void __iomem *iob_regs; ++ int base_irq; ++ int base_chan; ++ int32_t sc_cid; /* crypto tag */ ++ int sc_nsessions; ++ struct pasemi_session **sc_sessions; ++ int sc_num_channels;/* number of crypto channels */ ++ ++ /* pointer to the array of txring datastructures, one txring per channel */ ++ struct pasemi_fnu_txring *tx; ++ ++ /* ++ * mutual exclusion for the channel scheduler ++ */ ++ spinlock_t sc_chnlock; ++ /* last channel used, for now use round-robin to allocate channels */ ++ int sc_lastchn; ++}; ++ ++struct pasemi_session { ++ u64 civ[2]; ++ u64 keysz; ++ u64 key[4]; ++ u64 ccmd; ++ u64 hkey[4]; ++ u64 hseq; ++ u64 giv[2]; ++ u64 hiv[4]; ++ ++ int used; ++ dma_addr_t dma_addr; ++ int chan; ++}; ++ ++/* status register layout in IOB region, at 0xfd800000 */ ++struct pasdma_status { ++ u64 rx_sta[64]; ++ u64 tx_sta[20]; ++}; ++ ++#define ALG_IS_CIPHER(alg) ((alg == CRYPTO_DES_CBC) || \ ++ (alg == CRYPTO_3DES_CBC) || \ ++ (alg == CRYPTO_AES_CBC) || \ ++ (alg == CRYPTO_ARC4) || \ ++ (alg == CRYPTO_NULL_CBC)) ++ ++#define ALG_IS_SIG(alg) ((alg == CRYPTO_MD5) || \ ++ (alg == CRYPTO_MD5_HMAC) || \ ++ (alg == CRYPTO_SHA1) || \ ++ (alg == CRYPTO_SHA1_HMAC) || \ ++ (alg == CRYPTO_NULL_HMAC)) ++ ++enum { ++ PAS_DMA_COM_TXCMD = 0x100, /* Transmit Command Register */ ++ PAS_DMA_COM_TXSTA = 0x104, /* Transmit Status Register */ ++ PAS_DMA_COM_RXCMD = 0x108, /* Receive Command Register */ ++ PAS_DMA_COM_RXSTA = 0x10c, /* Receive Status Register */ ++ PAS_DMA_COM_CFG = 0x114, /* DMA Configuration Register */ ++}; ++ ++/* All these registers live in the PCI configuration space for the DMA PCI ++ * device. Use the normal PCI config access functions for them. ++ */ ++ ++#define PAS_DMA_COM_CFG_FWF 0x18000000 ++ ++#define PAS_DMA_COM_TXCMD_EN 0x00000001 /* enable */ ++#define PAS_DMA_COM_TXSTA_ACT 0x00000001 /* active */ ++#define PAS_DMA_COM_RXCMD_EN 0x00000001 /* enable */ ++#define PAS_DMA_COM_RXSTA_ACT 0x00000001 /* active */ ++ ++#define _PAS_DMA_TXCHAN_STRIDE 0x20 /* Size per channel */ ++#define _PAS_DMA_TXCHAN_TCMDSTA 0x300 /* Command / Status */ ++#define _PAS_DMA_TXCHAN_CFG 0x304 /* Configuration */ ++#define _PAS_DMA_TXCHAN_DSCRBU 0x308 /* Descriptor BU Allocation */ ++#define _PAS_DMA_TXCHAN_INCR 0x310 /* Descriptor increment */ ++#define _PAS_DMA_TXCHAN_CNT 0x314 /* Descriptor count/offset */ ++#define _PAS_DMA_TXCHAN_BASEL 0x318 /* Descriptor ring base (low) */ ++#define _PAS_DMA_TXCHAN_BASEU 0x31c /* (high) */ ++#define PAS_DMA_TXCHAN_TCMDSTA(c) (0x300+(c)*_PAS_DMA_TXCHAN_STRIDE) ++#define PAS_DMA_TXCHAN_TCMDSTA_EN 0x00000001 /* Enabled */ ++#define PAS_DMA_TXCHAN_TCMDSTA_ST 0x00000002 /* Stop interface */ ++#define PAS_DMA_TXCHAN_TCMDSTA_ACT 0x00010000 /* Active */ ++#define PAS_DMA_TXCHAN_CFG(c) (0x304+(c)*_PAS_DMA_TXCHAN_STRIDE) ++#define PAS_DMA_TXCHAN_CFG_TY_FUNC 0x00000002 /* Type = interface */ ++#define PAS_DMA_TXCHAN_CFG_TY_IFACE 0x00000000 /* Type = interface */ ++#define PAS_DMA_TXCHAN_CFG_TATTR_M 0x0000003c ++#define PAS_DMA_TXCHAN_CFG_TATTR_S 2 ++#define PAS_DMA_TXCHAN_CFG_TATTR(x) (((x) << PAS_DMA_TXCHAN_CFG_TATTR_S) & \ ++ PAS_DMA_TXCHAN_CFG_TATTR_M) ++#define PAS_DMA_TXCHAN_CFG_WT_M 0x000001c0 ++#define PAS_DMA_TXCHAN_CFG_WT_S 6 ++#define PAS_DMA_TXCHAN_CFG_WT(x) (((x) << PAS_DMA_TXCHAN_CFG_WT_S) & \ ++ PAS_DMA_TXCHAN_CFG_WT_M) ++#define PAS_DMA_TXCHAN_CFG_LPSQ_FAST 0x00000400 ++#define PAS_DMA_TXCHAN_CFG_LPDQ_FAST 0x00000800 ++#define PAS_DMA_TXCHAN_CFG_CF 0x00001000 /* Clean first line */ ++#define PAS_DMA_TXCHAN_CFG_CL 0x00002000 /* Clean last line */ ++#define PAS_DMA_TXCHAN_CFG_UP 0x00004000 /* update tx descr when sent */ ++#define PAS_DMA_TXCHAN_INCR(c) (0x310+(c)*_PAS_DMA_TXCHAN_STRIDE) ++#define PAS_DMA_TXCHAN_BASEL(c) (0x318+(c)*_PAS_DMA_TXCHAN_STRIDE) ++#define PAS_DMA_TXCHAN_BASEL_BRBL_M 0xffffffc0 ++#define PAS_DMA_TXCHAN_BASEL_BRBL_S 0 ++#define PAS_DMA_TXCHAN_BASEL_BRBL(x) (((x) << PAS_DMA_TXCHAN_BASEL_BRBL_S) & \ ++ PAS_DMA_TXCHAN_BASEL_BRBL_M) ++#define PAS_DMA_TXCHAN_BASEU(c) (0x31c+(c)*_PAS_DMA_TXCHAN_STRIDE) ++#define PAS_DMA_TXCHAN_BASEU_BRBH_M 0x00000fff ++#define PAS_DMA_TXCHAN_BASEU_BRBH_S 0 ++#define PAS_DMA_TXCHAN_BASEU_BRBH(x) (((x) << PAS_DMA_TXCHAN_BASEU_BRBH_S) & \ ++ PAS_DMA_TXCHAN_BASEU_BRBH_M) ++/* # of cache lines worth of buffer ring */ ++#define PAS_DMA_TXCHAN_BASEU_SIZ_M 0x3fff0000 ++#define PAS_DMA_TXCHAN_BASEU_SIZ_S 16 /* 0 = 16K */ ++#define PAS_DMA_TXCHAN_BASEU_SIZ(x) (((x) << PAS_DMA_TXCHAN_BASEU_SIZ_S) & \ ++ PAS_DMA_TXCHAN_BASEU_SIZ_M) ++ ++#define PAS_STATUS_PCNT_M 0x000000000000ffffull ++#define PAS_STATUS_PCNT_S 0 ++#define PAS_STATUS_DCNT_M 0x00000000ffff0000ull ++#define PAS_STATUS_DCNT_S 16 ++#define PAS_STATUS_BPCNT_M 0x0000ffff00000000ull ++#define PAS_STATUS_BPCNT_S 32 ++#define PAS_STATUS_CAUSE_M 0xf000000000000000ull ++#define PAS_STATUS_TIMER 0x1000000000000000ull ++#define PAS_STATUS_ERROR 0x2000000000000000ull ++#define PAS_STATUS_SOFT 0x4000000000000000ull ++#define PAS_STATUS_INT 0x8000000000000000ull ++ ++#define PAS_IOB_DMA_RXCH_CFG(i) (0x1100 + (i)*4) ++#define PAS_IOB_DMA_RXCH_CFG_CNTTH_M 0x00000fff ++#define PAS_IOB_DMA_RXCH_CFG_CNTTH_S 0 ++#define PAS_IOB_DMA_RXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_RXCH_CFG_CNTTH_S) & \ ++ PAS_IOB_DMA_RXCH_CFG_CNTTH_M) ++#define PAS_IOB_DMA_TXCH_CFG(i) (0x1200 + (i)*4) ++#define PAS_IOB_DMA_TXCH_CFG_CNTTH_M 0x00000fff ++#define PAS_IOB_DMA_TXCH_CFG_CNTTH_S 0 ++#define PAS_IOB_DMA_TXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_TXCH_CFG_CNTTH_S) & \ ++ PAS_IOB_DMA_TXCH_CFG_CNTTH_M) ++#define PAS_IOB_DMA_RXCH_STAT(i) (0x1300 + (i)*4) ++#define PAS_IOB_DMA_RXCH_STAT_INTGEN 0x00001000 ++#define PAS_IOB_DMA_RXCH_STAT_CNTDEL_M 0x00000fff ++#define PAS_IOB_DMA_RXCH_STAT_CNTDEL_S 0 ++#define PAS_IOB_DMA_RXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_RXCH_STAT_CNTDEL_S) &\ ++ PAS_IOB_DMA_RXCH_STAT_CNTDEL_M) ++#define PAS_IOB_DMA_TXCH_STAT(i) (0x1400 + (i)*4) ++#define PAS_IOB_DMA_TXCH_STAT_INTGEN 0x00001000 ++#define PAS_IOB_DMA_TXCH_STAT_CNTDEL_M 0x00000fff ++#define PAS_IOB_DMA_TXCH_STAT_CNTDEL_S 0 ++#define PAS_IOB_DMA_TXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_TXCH_STAT_CNTDEL_S) &\ ++ PAS_IOB_DMA_TXCH_STAT_CNTDEL_M) ++#define PAS_IOB_DMA_RXCH_RESET(i) (0x1500 + (i)*4) ++#define PAS_IOB_DMA_RXCH_RESET_PCNT_M 0xffff0000 ++#define PAS_IOB_DMA_RXCH_RESET_PCNT_S 16 ++#define PAS_IOB_DMA_RXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_RXCH_RESET_PCNT_S) & \ ++ PAS_IOB_DMA_RXCH_RESET_PCNT_M) ++#define PAS_IOB_DMA_RXCH_RESET_PCNTRST 0x00000020 ++#define PAS_IOB_DMA_RXCH_RESET_DCNTRST 0x00000010 ++#define PAS_IOB_DMA_RXCH_RESET_TINTC 0x00000008 ++#define PAS_IOB_DMA_RXCH_RESET_DINTC 0x00000004 ++#define PAS_IOB_DMA_RXCH_RESET_SINTC 0x00000002 ++#define PAS_IOB_DMA_RXCH_RESET_PINTC 0x00000001 ++#define PAS_IOB_DMA_TXCH_RESET(i) (0x1600 + (i)*4) ++#define PAS_IOB_DMA_TXCH_RESET_PCNT_M 0xffff0000 ++#define PAS_IOB_DMA_TXCH_RESET_PCNT_S 16 ++#define PAS_IOB_DMA_TXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_TXCH_RESET_PCNT_S) & \ ++ PAS_IOB_DMA_TXCH_RESET_PCNT_M) ++#define PAS_IOB_DMA_TXCH_RESET_PCNTRST 0x00000020 ++#define PAS_IOB_DMA_TXCH_RESET_DCNTRST 0x00000010 ++#define PAS_IOB_DMA_TXCH_RESET_TINTC 0x00000008 ++#define PAS_IOB_DMA_TXCH_RESET_DINTC 0x00000004 ++#define PAS_IOB_DMA_TXCH_RESET_SINTC 0x00000002 ++#define PAS_IOB_DMA_TXCH_RESET_PINTC 0x00000001 ++ ++#define PAS_IOB_DMA_COM_TIMEOUTCFG 0x1700 ++#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M 0x00ffffff ++#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S 0 ++#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(x) (((x) << PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S) & \ ++ PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M) ++ ++/* Transmit descriptor fields */ ++#define XCT_MACTX_T 0x8000000000000000ull ++#define XCT_MACTX_ST 0x4000000000000000ull ++#define XCT_MACTX_NORES 0x0000000000000000ull ++#define XCT_MACTX_8BRES 0x1000000000000000ull ++#define XCT_MACTX_24BRES 0x2000000000000000ull ++#define XCT_MACTX_40BRES 0x3000000000000000ull ++#define XCT_MACTX_I 0x0800000000000000ull ++#define XCT_MACTX_O 0x0400000000000000ull ++#define XCT_MACTX_E 0x0200000000000000ull ++#define XCT_MACTX_VLAN_M 0x0180000000000000ull ++#define XCT_MACTX_VLAN_NOP 0x0000000000000000ull ++#define XCT_MACTX_VLAN_REMOVE 0x0080000000000000ull ++#define XCT_MACTX_VLAN_INSERT 0x0100000000000000ull ++#define XCT_MACTX_VLAN_REPLACE 0x0180000000000000ull ++#define XCT_MACTX_CRC_M 0x0060000000000000ull ++#define XCT_MACTX_CRC_NOP 0x0000000000000000ull ++#define XCT_MACTX_CRC_INSERT 0x0020000000000000ull ++#define XCT_MACTX_CRC_PAD 0x0040000000000000ull ++#define XCT_MACTX_CRC_REPLACE 0x0060000000000000ull ++#define XCT_MACTX_SS 0x0010000000000000ull ++#define XCT_MACTX_LLEN_M 0x00007fff00000000ull ++#define XCT_MACTX_LLEN_S 32ull ++#define XCT_MACTX_LLEN(x) ((((long)(x)) << XCT_MACTX_LLEN_S) & \ ++ XCT_MACTX_LLEN_M) ++#define XCT_MACTX_IPH_M 0x00000000f8000000ull ++#define XCT_MACTX_IPH_S 27ull ++#define XCT_MACTX_IPH(x) ((((long)(x)) << XCT_MACTX_IPH_S) & \ ++ XCT_MACTX_IPH_M) ++#define XCT_MACTX_IPO_M 0x0000000007c00000ull ++#define XCT_MACTX_IPO_S 22ull ++#define XCT_MACTX_IPO(x) ((((long)(x)) << XCT_MACTX_IPO_S) & \ ++ XCT_MACTX_IPO_M) ++#define XCT_MACTX_CSUM_M 0x0000000000000060ull ++#define XCT_MACTX_CSUM_NOP 0x0000000000000000ull ++#define XCT_MACTX_CSUM_TCP 0x0000000000000040ull ++#define XCT_MACTX_CSUM_UDP 0x0000000000000060ull ++#define XCT_MACTX_V6 0x0000000000000010ull ++#define XCT_MACTX_C 0x0000000000000004ull ++#define XCT_MACTX_AL2 0x0000000000000002ull ++ ++#define XCT_PTR_T 0x8000000000000000ull ++#define XCT_PTR_LEN_M 0x7ffff00000000000ull ++#define XCT_PTR_LEN_S 44 ++#define XCT_PTR_LEN(x) ((((long)(x)) << XCT_PTR_LEN_S) & \ ++ XCT_PTR_LEN_M) ++#define XCT_PTR_ADDR_M 0x00000fffffffffffull ++#define XCT_PTR_ADDR_S 0 ++#define XCT_PTR_ADDR(x) ((((long)(x)) << XCT_PTR_ADDR_S) & \ ++ XCT_PTR_ADDR_M) ++ ++/* Function descriptor fields */ ++#define XCT_FUN_T 0x8000000000000000ull ++#define XCT_FUN_ST 0x4000000000000000ull ++#define XCT_FUN_NORES 0x0000000000000000ull ++#define XCT_FUN_8BRES 0x1000000000000000ull ++#define XCT_FUN_24BRES 0x2000000000000000ull ++#define XCT_FUN_40BRES 0x3000000000000000ull ++#define XCT_FUN_I 0x0800000000000000ull ++#define XCT_FUN_O 0x0400000000000000ull ++#define XCT_FUN_E 0x0200000000000000ull ++#define XCT_FUN_FUN_S 54 ++#define XCT_FUN_FUN_M 0x01c0000000000000ull ++#define XCT_FUN_FUN(num) ((((long)(num)) << XCT_FUN_FUN_S) & \ ++ XCT_FUN_FUN_M) ++#define XCT_FUN_CRM_NOP 0x0000000000000000ull ++#define XCT_FUN_CRM_SIG 0x0008000000000000ull ++#define XCT_FUN_CRM_ENC 0x0010000000000000ull ++#define XCT_FUN_CRM_DEC 0x0018000000000000ull ++#define XCT_FUN_CRM_SIG_ENC 0x0020000000000000ull ++#define XCT_FUN_CRM_ENC_SIG 0x0028000000000000ull ++#define XCT_FUN_CRM_SIG_DEC 0x0030000000000000ull ++#define XCT_FUN_CRM_DEC_SIG 0x0038000000000000ull ++#define XCT_FUN_LLEN_M 0x0007ffff00000000ull ++#define XCT_FUN_LLEN_S 32ULL ++#define XCT_FUN_LLEN(x) ((((long)(x)) << XCT_FUN_LLEN_S) & \ ++ XCT_FUN_LLEN_M) ++#define XCT_FUN_SHL_M 0x00000000f8000000ull ++#define XCT_FUN_SHL_S 27ull ++#define XCT_FUN_SHL(x) ((((long)(x)) << XCT_FUN_SHL_S) & \ ++ XCT_FUN_SHL_M) ++#define XCT_FUN_CHL_M 0x0000000007c00000ull ++#define XCT_FUN_CHL_S 22ull ++#define XCT_FUN_CHL(x) ((((long)(x)) << XCT_FUN_CHL_S) & \ ++ XCT_FUN_CHL_M) ++#define XCT_FUN_HSZ_M 0x00000000003c0000ull ++#define XCT_FUN_HSZ_S 18ull ++#define XCT_FUN_HSZ(x) ((((long)(x)) << XCT_FUN_HSZ_S) & \ ++ XCT_FUN_HSZ_M) ++#define XCT_FUN_ALG_DES 0x0000000000000000ull ++#define XCT_FUN_ALG_3DES 0x0000000000008000ull ++#define XCT_FUN_ALG_AES 0x0000000000010000ull ++#define XCT_FUN_ALG_ARC 0x0000000000018000ull ++#define XCT_FUN_ALG_KASUMI 0x0000000000020000ull ++#define XCT_FUN_BCM_ECB 0x0000000000000000ull ++#define XCT_FUN_BCM_CBC 0x0000000000001000ull ++#define XCT_FUN_BCM_CFB 0x0000000000002000ull ++#define XCT_FUN_BCM_OFB 0x0000000000003000ull ++#define XCT_FUN_BCM_CNT 0x0000000000003800ull ++#define XCT_FUN_BCM_KAS_F8 0x0000000000002800ull ++#define XCT_FUN_BCM_KAS_F9 0x0000000000001800ull ++#define XCT_FUN_BCP_NO_PAD 0x0000000000000000ull ++#define XCT_FUN_BCP_ZRO 0x0000000000000200ull ++#define XCT_FUN_BCP_PL 0x0000000000000400ull ++#define XCT_FUN_BCP_INCR 0x0000000000000600ull ++#define XCT_FUN_SIG_MD5 (0ull << 4) ++#define XCT_FUN_SIG_SHA1 (2ull << 4) ++#define XCT_FUN_SIG_HMAC_MD5 (8ull << 4) ++#define XCT_FUN_SIG_HMAC_SHA1 (10ull << 4) ++#define XCT_FUN_A 0x0000000000000008ull ++#define XCT_FUN_C 0x0000000000000004ull ++#define XCT_FUN_AL2 0x0000000000000002ull ++#define XCT_FUN_SE 0x0000000000000001ull ++ ++#define XCT_FUN_SRC_PTR(len, addr) (XCT_PTR_LEN(len) | XCT_PTR_ADDR(addr)) ++#define XCT_FUN_DST_PTR(len, addr) (XCT_FUN_SRC_PTR(len, addr) | \ ++ 0x8000000000000000ull) ++ ++#define XCT_CTRL_HDR_FUN_NUM_M 0x01c0000000000000ull ++#define XCT_CTRL_HDR_FUN_NUM_S 54 ++#define XCT_CTRL_HDR_LEN_M 0x0007ffff00000000ull ++#define XCT_CTRL_HDR_LEN_S 32 ++#define XCT_CTRL_HDR_REG_M 0x00000000000000ffull ++#define XCT_CTRL_HDR_REG_S 0 ++ ++#define XCT_CTRL_HDR(funcN,len,reg) (0x9400000000000000ull | \ ++ ((((long)(funcN)) << XCT_CTRL_HDR_FUN_NUM_S) \ ++ & XCT_CTRL_HDR_FUN_NUM_M) | \ ++ ((((long)(len)) << \ ++ XCT_CTRL_HDR_LEN_S) & XCT_CTRL_HDR_LEN_M) | \ ++ ((((long)(reg)) << \ ++ XCT_CTRL_HDR_REG_S) & XCT_CTRL_HDR_REG_M)) ++ ++/* Function config command options */ ++#define DMA_CALGO_DES 0x00 ++#define DMA_CALGO_3DES 0x01 ++#define DMA_CALGO_AES 0x02 ++#define DMA_CALGO_ARC 0x03 ++ ++#define DMA_FN_CIV0 0x02 ++#define DMA_FN_CIV1 0x03 ++#define DMA_FN_HKEY0 0x0a ++ ++#define XCT_PTR_ADDR_LEN(ptr) ((ptr) & XCT_PTR_ADDR_M), \ ++ (((ptr) & XCT_PTR_LEN_M) >> XCT_PTR_LEN_S) ++ ++#endif /* PASEMI_FNU_H */ +diff -Nur linux-3.1.4.orig/crypto/ocf/random.c linux-3.1.4/crypto/ocf/random.c +--- linux-3.1.4.orig/crypto/ocf/random.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/random.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,317 @@ ++/* ++ * A system independant way of adding entropy to the kernels pool ++ * this way the drivers can focus on the real work and we can take ++ * care of pushing it to the appropriate place in the kernel. ++ * ++ * This should be fast and callable from timers/interrupts ++ * ++ * Written by David McCullough ++ * Copyright (C) 2006-2010 David McCullough ++ * Copyright (C) 2004-2005 Intel Corporation. ++ * ++ * LICENSE TERMS ++ * ++ * The free distribution and use of this software in both source and binary ++ * form is allowed (with or without changes) provided that: ++ * ++ * 1. distributions of this source code include the above copyright ++ * notice, this list of conditions and the following disclaimer; ++ * ++ * 2. distributions in binary form include the above copyright ++ * notice, this list of conditions and the following disclaimer ++ * in the documentation and/or other associated materials; ++ * ++ * 3. the copyright holder's name is not used to endorse products ++ * built using this software without specific written permission. ++ * ++ * ALTERNATIVELY, provided that this notice is retained in full, this product ++ * may be distributed under the terms of the GNU General Public License (GPL), ++ * in which case the provisions of the GPL apply INSTEAD OF those given above. ++ * ++ * DISCLAIMER ++ * ++ * This software is provided 'as is' with no explicit or implied warranties ++ * in respect of its properties, including, but not limited to, correctness ++ * and/or fitness for purpose. ++ */ ++ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifdef CONFIG_OCF_FIPS ++#include "rndtest.h" ++#endif ++ ++#ifndef HAS_RANDOM_INPUT_WAIT ++#error "Please do not enable OCF_RANDOMHARVEST unless you have applied patches" ++#endif ++ ++/* ++ * a hack to access the debug levels from the crypto driver ++ */ ++extern int crypto_debug; ++#define debug crypto_debug ++ ++/* ++ * a list of all registered random providers ++ */ ++static LIST_HEAD(random_ops); ++static int started = 0; ++static int initted = 0; ++ ++struct random_op { ++ struct list_head random_list; ++ u_int32_t driverid; ++ int (*read_random)(void *arg, u_int32_t *buf, int len); ++ void *arg; ++}; ++ ++static int random_proc(void *arg); ++ ++static pid_t randomproc = (pid_t) -1; ++static spinlock_t random_lock; ++ ++/* ++ * just init the spin locks ++ */ ++static int ++crypto_random_init(void) ++{ ++ spin_lock_init(&random_lock); ++ initted = 1; ++ return(0); ++} ++ ++/* ++ * Add the given random reader to our list (if not present) ++ * and start the thread (if not already started) ++ * ++ * we have to assume that driver id is ok for now ++ */ ++int ++crypto_rregister( ++ u_int32_t driverid, ++ int (*read_random)(void *arg, u_int32_t *buf, int len), ++ void *arg) ++{ ++ unsigned long flags; ++ int ret = 0; ++ struct random_op *rops, *tmp; ++ ++ dprintk("%s,%d: %s(0x%x, %p, %p)\n", __FILE__, __LINE__, ++ __FUNCTION__, driverid, read_random, arg); ++ ++ if (!initted) ++ crypto_random_init(); ++ ++#if 0 ++ struct cryptocap *cap; ++ ++ cap = crypto_checkdriver(driverid); ++ if (!cap) ++ return EINVAL; ++#endif ++ ++ list_for_each_entry_safe(rops, tmp, &random_ops, random_list) { ++ if (rops->driverid == driverid && rops->read_random == read_random) ++ return EEXIST; ++ } ++ ++ rops = (struct random_op *) kmalloc(sizeof(*rops), GFP_KERNEL); ++ if (!rops) ++ return ENOMEM; ++ ++ rops->driverid = driverid; ++ rops->read_random = read_random; ++ rops->arg = arg; ++ ++ spin_lock_irqsave(&random_lock, flags); ++ list_add_tail(&rops->random_list, &random_ops); ++ if (!started) { ++ randomproc = kernel_thread(random_proc, NULL, CLONE_FS|CLONE_FILES); ++ if (randomproc < 0) { ++ ret = randomproc; ++ printk("crypto: crypto_rregister cannot start random thread; " ++ "error %d", ret); ++ } else ++ started = 1; ++ } ++ spin_unlock_irqrestore(&random_lock, flags); ++ ++ return ret; ++} ++EXPORT_SYMBOL(crypto_rregister); ++ ++int ++crypto_runregister_all(u_int32_t driverid) ++{ ++ struct random_op *rops, *tmp; ++ unsigned long flags; ++ ++ dprintk("%s,%d: %s(0x%x)\n", __FILE__, __LINE__, __FUNCTION__, driverid); ++ ++ list_for_each_entry_safe(rops, tmp, &random_ops, random_list) { ++ if (rops->driverid == driverid) { ++ list_del(&rops->random_list); ++ kfree(rops); ++ } ++ } ++ ++ spin_lock_irqsave(&random_lock, flags); ++ if (list_empty(&random_ops) && started) ++ kill_proc(randomproc, SIGKILL, 1); ++ spin_unlock_irqrestore(&random_lock, flags); ++ return(0); ++} ++EXPORT_SYMBOL(crypto_runregister_all); ++ ++/* ++ * while we can add entropy to random.c continue to read random data from ++ * the drivers and push it to random. ++ */ ++static int ++random_proc(void *arg) ++{ ++ int n; ++ int wantcnt; ++ int bufcnt = 0; ++ int retval = 0; ++ int *buf = NULL; ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++ daemonize(); ++ spin_lock_irq(¤t->sigmask_lock); ++ sigemptyset(¤t->blocked); ++ recalc_sigpending(current); ++ spin_unlock_irq(¤t->sigmask_lock); ++ sprintf(current->comm, "ocf-random"); ++#else ++ daemonize("ocf-random"); ++ allow_signal(SIGKILL); ++#endif ++ ++ (void) get_fs(); ++ set_fs(get_ds()); ++ ++#ifdef CONFIG_OCF_FIPS ++#define NUM_INT (RNDTEST_NBYTES/sizeof(int)) ++#else ++#define NUM_INT 32 ++#endif ++ ++ /* ++ * some devices can transferr their RNG data direct into memory, ++ * so make sure it is device friendly ++ */ ++ buf = kmalloc(NUM_INT * sizeof(int), GFP_DMA); ++ if (NULL == buf) { ++ printk("crypto: RNG could not allocate memory\n"); ++ retval = -ENOMEM; ++ goto bad_alloc; ++ } ++ ++ wantcnt = NUM_INT; /* start by adding some entropy */ ++ ++ /* ++ * its possible due to errors or driver removal that we no longer ++ * have anything to do, if so exit or we will consume all the CPU ++ * doing nothing ++ */ ++ while (!list_empty(&random_ops)) { ++ struct random_op *rops, *tmp; ++ ++#ifdef CONFIG_OCF_FIPS ++ if (wantcnt) ++ wantcnt = NUM_INT; /* FIPs mode can do 20000 bits or none */ ++#endif ++ ++ /* see if we can get enough entropy to make the world ++ * a better place. ++ */ ++ while (bufcnt < wantcnt && bufcnt < NUM_INT) { ++ list_for_each_entry_safe(rops, tmp, &random_ops, random_list) { ++ ++ n = (*rops->read_random)(rops->arg, &buf[bufcnt], ++ NUM_INT - bufcnt); ++ ++ /* on failure remove the random number generator */ ++ if (n == -1) { ++ list_del(&rops->random_list); ++ printk("crypto: RNG (driverid=0x%x) failed, disabling\n", ++ rops->driverid); ++ kfree(rops); ++ } else if (n > 0) ++ bufcnt += n; ++ } ++ /* give up CPU for a bit, just in case as this is a loop */ ++ schedule(); ++ } ++ ++ ++#ifdef CONFIG_OCF_FIPS ++ if (bufcnt > 0 && rndtest_buf((unsigned char *) &buf[0])) { ++ dprintk("crypto: buffer had fips errors, discarding\n"); ++ bufcnt = 0; ++ } ++#endif ++ ++ /* ++ * if we have a certified buffer, we can send some data ++ * to /dev/random and move along ++ */ ++ if (bufcnt > 0) { ++ /* add what we have */ ++ random_input_words(buf, bufcnt, bufcnt*sizeof(int)*8); ++ bufcnt = 0; ++ } ++ ++ /* give up CPU for a bit so we don't hog while filling */ ++ schedule(); ++ ++ /* wait for needing more */ ++ wantcnt = random_input_wait(); ++ ++ if (wantcnt <= 0) ++ wantcnt = 0; /* try to get some info again */ ++ else ++ /* round up to one word or we can loop forever */ ++ wantcnt = (wantcnt + (sizeof(int)*8)) / (sizeof(int)*8); ++ if (wantcnt > NUM_INT) { ++ wantcnt = NUM_INT; ++ } ++ ++ if (signal_pending(current)) { ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++ spin_lock_irq(¤t->sigmask_lock); ++#endif ++ flush_signals(current); ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++ spin_unlock_irq(¤t->sigmask_lock); ++#endif ++ } ++ } ++ ++ kfree(buf); ++ ++bad_alloc: ++ spin_lock_irq(&random_lock); ++ randomproc = (pid_t) -1; ++ started = 0; ++ spin_unlock_irq(&random_lock); ++ ++ return retval; ++} ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/rndtest.c linux-3.1.4/crypto/ocf/rndtest.c +--- linux-3.1.4.orig/crypto/ocf/rndtest.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/rndtest.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,300 @@ ++/* $OpenBSD$ */ ++ ++/* ++ * OCF/Linux port done by David McCullough ++ * Copyright (C) 2006-2010 David McCullough ++ * Copyright (C) 2004-2005 Intel Corporation. ++ * The license and original author are listed below. ++ * ++ * Copyright (c) 2002 Jason L. Wright (jason@thought.net) ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. All advertising materials mentioning features or use of this software ++ * must display the following acknowledgement: ++ * This product includes software developed by Jason L. Wright ++ * 4. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++ * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, ++ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ++ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "rndtest.h" ++ ++static struct rndtest_stats rndstats; ++ ++static void rndtest_test(struct rndtest_state *); ++ ++/* The tests themselves */ ++static int rndtest_monobit(struct rndtest_state *); ++static int rndtest_runs(struct rndtest_state *); ++static int rndtest_longruns(struct rndtest_state *); ++static int rndtest_chi_4(struct rndtest_state *); ++ ++static int rndtest_runs_check(struct rndtest_state *, int, int *); ++static void rndtest_runs_record(struct rndtest_state *, int, int *); ++ ++static const struct rndtest_testfunc { ++ int (*test)(struct rndtest_state *); ++} rndtest_funcs[] = { ++ { rndtest_monobit }, ++ { rndtest_runs }, ++ { rndtest_chi_4 }, ++ { rndtest_longruns }, ++}; ++ ++#define RNDTEST_NTESTS (sizeof(rndtest_funcs)/sizeof(rndtest_funcs[0])) ++ ++static void ++rndtest_test(struct rndtest_state *rsp) ++{ ++ int i, rv = 0; ++ ++ rndstats.rst_tests++; ++ for (i = 0; i < RNDTEST_NTESTS; i++) ++ rv |= (*rndtest_funcs[i].test)(rsp); ++ rsp->rs_discard = (rv != 0); ++} ++ ++ ++extern int crypto_debug; ++#define rndtest_verbose 2 ++#define rndtest_report(rsp, failure, fmt, a...) \ ++ { if (failure || crypto_debug) { printk("rng_test: " fmt "\n", a); } else; } ++ ++#define RNDTEST_MONOBIT_MINONES 9725 ++#define RNDTEST_MONOBIT_MAXONES 10275 ++ ++static int ++rndtest_monobit(struct rndtest_state *rsp) ++{ ++ int i, ones = 0, j; ++ u_int8_t r; ++ ++ for (i = 0; i < RNDTEST_NBYTES; i++) { ++ r = rsp->rs_buf[i]; ++ for (j = 0; j < 8; j++, r <<= 1) ++ if (r & 0x80) ++ ones++; ++ } ++ if (ones > RNDTEST_MONOBIT_MINONES && ++ ones < RNDTEST_MONOBIT_MAXONES) { ++ if (rndtest_verbose > 1) ++ rndtest_report(rsp, 0, "monobit pass (%d < %d < %d)", ++ RNDTEST_MONOBIT_MINONES, ones, ++ RNDTEST_MONOBIT_MAXONES); ++ return (0); ++ } else { ++ if (rndtest_verbose) ++ rndtest_report(rsp, 1, ++ "monobit failed (%d ones)", ones); ++ rndstats.rst_monobit++; ++ return (-1); ++ } ++} ++ ++#define RNDTEST_RUNS_NINTERVAL 6 ++ ++static const struct rndtest_runs_tabs { ++ u_int16_t min, max; ++} rndtest_runs_tab[] = { ++ { 2343, 2657 }, ++ { 1135, 1365 }, ++ { 542, 708 }, ++ { 251, 373 }, ++ { 111, 201 }, ++ { 111, 201 }, ++}; ++ ++static int ++rndtest_runs(struct rndtest_state *rsp) ++{ ++ int i, j, ones, zeros, rv = 0; ++ int onei[RNDTEST_RUNS_NINTERVAL], zeroi[RNDTEST_RUNS_NINTERVAL]; ++ u_int8_t c; ++ ++ bzero(onei, sizeof(onei)); ++ bzero(zeroi, sizeof(zeroi)); ++ ones = zeros = 0; ++ for (i = 0; i < RNDTEST_NBYTES; i++) { ++ c = rsp->rs_buf[i]; ++ for (j = 0; j < 8; j++, c <<= 1) { ++ if (c & 0x80) { ++ ones++; ++ rndtest_runs_record(rsp, zeros, zeroi); ++ zeros = 0; ++ } else { ++ zeros++; ++ rndtest_runs_record(rsp, ones, onei); ++ ones = 0; ++ } ++ } ++ } ++ rndtest_runs_record(rsp, ones, onei); ++ rndtest_runs_record(rsp, zeros, zeroi); ++ ++ rv |= rndtest_runs_check(rsp, 0, zeroi); ++ rv |= rndtest_runs_check(rsp, 1, onei); ++ ++ if (rv) ++ rndstats.rst_runs++; ++ ++ return (rv); ++} ++ ++static void ++rndtest_runs_record(struct rndtest_state *rsp, int len, int *intrv) ++{ ++ if (len == 0) ++ return; ++ if (len > RNDTEST_RUNS_NINTERVAL) ++ len = RNDTEST_RUNS_NINTERVAL; ++ len -= 1; ++ intrv[len]++; ++} ++ ++static int ++rndtest_runs_check(struct rndtest_state *rsp, int val, int *src) ++{ ++ int i, rv = 0; ++ ++ for (i = 0; i < RNDTEST_RUNS_NINTERVAL; i++) { ++ if (src[i] < rndtest_runs_tab[i].min || ++ src[i] > rndtest_runs_tab[i].max) { ++ rndtest_report(rsp, 1, ++ "%s interval %d failed (%d, %d-%d)", ++ val ? "ones" : "zeros", ++ i + 1, src[i], rndtest_runs_tab[i].min, ++ rndtest_runs_tab[i].max); ++ rv = -1; ++ } else { ++ rndtest_report(rsp, 0, ++ "runs pass %s interval %d (%d < %d < %d)", ++ val ? "ones" : "zeros", ++ i + 1, rndtest_runs_tab[i].min, src[i], ++ rndtest_runs_tab[i].max); ++ } ++ } ++ return (rv); ++} ++ ++static int ++rndtest_longruns(struct rndtest_state *rsp) ++{ ++ int i, j, ones = 0, zeros = 0, maxones = 0, maxzeros = 0; ++ u_int8_t c; ++ ++ for (i = 0; i < RNDTEST_NBYTES; i++) { ++ c = rsp->rs_buf[i]; ++ for (j = 0; j < 8; j++, c <<= 1) { ++ if (c & 0x80) { ++ zeros = 0; ++ ones++; ++ if (ones > maxones) ++ maxones = ones; ++ } else { ++ ones = 0; ++ zeros++; ++ if (zeros > maxzeros) ++ maxzeros = zeros; ++ } ++ } ++ } ++ ++ if (maxones < 26 && maxzeros < 26) { ++ rndtest_report(rsp, 0, "longruns pass (%d ones, %d zeros)", ++ maxones, maxzeros); ++ return (0); ++ } else { ++ rndtest_report(rsp, 1, "longruns fail (%d ones, %d zeros)", ++ maxones, maxzeros); ++ rndstats.rst_longruns++; ++ return (-1); ++ } ++} ++ ++/* ++ * chi^2 test over 4 bits: (this is called the poker test in FIPS 140-2, ++ * but it is really the chi^2 test over 4 bits (the poker test as described ++ * by Knuth vol 2 is something different, and I take him as authoritative ++ * on nomenclature over NIST). ++ */ ++#define RNDTEST_CHI4_K 16 ++#define RNDTEST_CHI4_K_MASK (RNDTEST_CHI4_K - 1) ++ ++/* ++ * The unnormalized values are used so that we don't have to worry about ++ * fractional precision. The "real" value is found by: ++ * (V - 1562500) * (16 / 5000) = Vn (where V is the unnormalized value) ++ */ ++#define RNDTEST_CHI4_VMIN 1563181 /* 2.1792 */ ++#define RNDTEST_CHI4_VMAX 1576929 /* 46.1728 */ ++ ++static int ++rndtest_chi_4(struct rndtest_state *rsp) ++{ ++ unsigned int freq[RNDTEST_CHI4_K], i, sum; ++ ++ for (i = 0; i < RNDTEST_CHI4_K; i++) ++ freq[i] = 0; ++ ++ /* Get number of occurances of each 4 bit pattern */ ++ for (i = 0; i < RNDTEST_NBYTES; i++) { ++ freq[(rsp->rs_buf[i] >> 4) & RNDTEST_CHI4_K_MASK]++; ++ freq[(rsp->rs_buf[i] >> 0) & RNDTEST_CHI4_K_MASK]++; ++ } ++ ++ for (i = 0, sum = 0; i < RNDTEST_CHI4_K; i++) ++ sum += freq[i] * freq[i]; ++ ++ if (sum >= 1563181 && sum <= 1576929) { ++ rndtest_report(rsp, 0, "chi^2(4): pass (sum %u)", sum); ++ return (0); ++ } else { ++ rndtest_report(rsp, 1, "chi^2(4): failed (sum %u)", sum); ++ rndstats.rst_chi++; ++ return (-1); ++ } ++} ++ ++int ++rndtest_buf(unsigned char *buf) ++{ ++ struct rndtest_state rsp; ++ ++ memset(&rsp, 0, sizeof(rsp)); ++ rsp.rs_buf = buf; ++ rndtest_test(&rsp); ++ return(rsp.rs_discard); ++} ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/rndtest.h linux-3.1.4/crypto/ocf/rndtest.h +--- linux-3.1.4.orig/crypto/ocf/rndtest.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/rndtest.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,54 @@ ++/* $FreeBSD: src/sys/dev/rndtest/rndtest.h,v 1.1 2003/03/11 22:54:44 sam Exp $ */ ++/* $OpenBSD$ */ ++ ++/* ++ * Copyright (c) 2002 Jason L. Wright (jason@thought.net) ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. All advertising materials mentioning features or use of this software ++ * must display the following acknowledgement: ++ * This product includes software developed by Jason L. Wright ++ * 4. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++ * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, ++ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ++ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++ ++/* Some of the tests depend on these values */ ++#define RNDTEST_NBYTES 2500 ++#define RNDTEST_NBITS (8 * RNDTEST_NBYTES) ++ ++struct rndtest_state { ++ int rs_discard; /* discard/accept random data */ ++ u_int8_t *rs_buf; ++}; ++ ++struct rndtest_stats { ++ u_int32_t rst_discard; /* number of bytes discarded */ ++ u_int32_t rst_tests; /* number of test runs */ ++ u_int32_t rst_monobit; /* monobit test failures */ ++ u_int32_t rst_runs; /* 0/1 runs failures */ ++ u_int32_t rst_longruns; /* longruns failures */ ++ u_int32_t rst_chi; /* chi^2 failures */ ++}; ++ ++extern int rndtest_buf(unsigned char *buf); +diff -Nur linux-3.1.4.orig/crypto/ocf/safe/Makefile linux-3.1.4/crypto/ocf/safe/Makefile +--- linux-3.1.4.orig/crypto/ocf/safe/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/safe/Makefile 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,12 @@ ++# for SGlinux builds ++-include $(ROOTDIR)/modules/.config ++ ++obj-$(CONFIG_OCF_SAFE) += safe.o ++ ++obj ?= . ++EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ ++ ++ifdef TOPDIR ++-include $(TOPDIR)/Rules.make ++endif ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/safe/hmachack.h linux-3.1.4/crypto/ocf/safe/hmachack.h +--- linux-3.1.4.orig/crypto/ocf/safe/hmachack.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/safe/hmachack.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,37 @@ ++/* ++ * until we find a cleaner way, include the BSD md5/sha1 code ++ * here ++ */ ++#ifdef HMAC_HACK ++#define LITTLE_ENDIAN 1234 ++#define BIG_ENDIAN 4321 ++#ifdef __LITTLE_ENDIAN ++#define BYTE_ORDER LITTLE_ENDIAN ++#endif ++#ifdef __BIG_ENDIAN ++#define BYTE_ORDER BIG_ENDIAN ++#endif ++ ++u_int8_t hmac_ipad_buffer[64] = { ++ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, ++ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, ++ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, ++ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, ++ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, ++ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, ++ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, ++ 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36, 0x36 ++}; ++ ++u_int8_t hmac_opad_buffer[64] = { ++ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, ++ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, ++ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, ++ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, ++ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, ++ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, ++ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, ++ 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C, 0x5C ++}; ++#endif /* HMAC_HACK */ ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/safe/md5.c linux-3.1.4/crypto/ocf/safe/md5.c +--- linux-3.1.4.orig/crypto/ocf/safe/md5.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/safe/md5.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,308 @@ ++/* $KAME: md5.c,v 1.5 2000/11/08 06:13:08 itojun Exp $ */ ++/* ++ * Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. Neither the name of the project nor the names of its contributors ++ * may be used to endorse or promote products derived from this software ++ * without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND ++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE ++ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ++ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ++ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF ++ * SUCH DAMAGE. ++ */ ++ ++#if 0 ++#include ++__FBSDID("$FreeBSD: src/sys/crypto/md5.c,v 1.9 2004/01/27 19:49:19 des Exp $"); ++ ++#include ++#include ++#include ++#include ++#include ++#endif ++ ++#define SHIFT(X, s) (((X) << (s)) | ((X) >> (32 - (s)))) ++ ++#define F(X, Y, Z) (((X) & (Y)) | ((~X) & (Z))) ++#define G(X, Y, Z) (((X) & (Z)) | ((Y) & (~Z))) ++#define H(X, Y, Z) ((X) ^ (Y) ^ (Z)) ++#define I(X, Y, Z) ((Y) ^ ((X) | (~Z))) ++ ++#define ROUND1(a, b, c, d, k, s, i) { \ ++ (a) = (a) + F((b), (c), (d)) + X[(k)] + T[(i)]; \ ++ (a) = SHIFT((a), (s)); \ ++ (a) = (b) + (a); \ ++} ++ ++#define ROUND2(a, b, c, d, k, s, i) { \ ++ (a) = (a) + G((b), (c), (d)) + X[(k)] + T[(i)]; \ ++ (a) = SHIFT((a), (s)); \ ++ (a) = (b) + (a); \ ++} ++ ++#define ROUND3(a, b, c, d, k, s, i) { \ ++ (a) = (a) + H((b), (c), (d)) + X[(k)] + T[(i)]; \ ++ (a) = SHIFT((a), (s)); \ ++ (a) = (b) + (a); \ ++} ++ ++#define ROUND4(a, b, c, d, k, s, i) { \ ++ (a) = (a) + I((b), (c), (d)) + X[(k)] + T[(i)]; \ ++ (a) = SHIFT((a), (s)); \ ++ (a) = (b) + (a); \ ++} ++ ++#define Sa 7 ++#define Sb 12 ++#define Sc 17 ++#define Sd 22 ++ ++#define Se 5 ++#define Sf 9 ++#define Sg 14 ++#define Sh 20 ++ ++#define Si 4 ++#define Sj 11 ++#define Sk 16 ++#define Sl 23 ++ ++#define Sm 6 ++#define Sn 10 ++#define So 15 ++#define Sp 21 ++ ++#define MD5_A0 0x67452301 ++#define MD5_B0 0xefcdab89 ++#define MD5_C0 0x98badcfe ++#define MD5_D0 0x10325476 ++ ++/* Integer part of 4294967296 times abs(sin(i)), where i is in radians. */ ++static const u_int32_t T[65] = { ++ 0, ++ 0xd76aa478, 0xe8c7b756, 0x242070db, 0xc1bdceee, ++ 0xf57c0faf, 0x4787c62a, 0xa8304613, 0xfd469501, ++ 0x698098d8, 0x8b44f7af, 0xffff5bb1, 0x895cd7be, ++ 0x6b901122, 0xfd987193, 0xa679438e, 0x49b40821, ++ ++ 0xf61e2562, 0xc040b340, 0x265e5a51, 0xe9b6c7aa, ++ 0xd62f105d, 0x2441453, 0xd8a1e681, 0xe7d3fbc8, ++ 0x21e1cde6, 0xc33707d6, 0xf4d50d87, 0x455a14ed, ++ 0xa9e3e905, 0xfcefa3f8, 0x676f02d9, 0x8d2a4c8a, ++ ++ 0xfffa3942, 0x8771f681, 0x6d9d6122, 0xfde5380c, ++ 0xa4beea44, 0x4bdecfa9, 0xf6bb4b60, 0xbebfbc70, ++ 0x289b7ec6, 0xeaa127fa, 0xd4ef3085, 0x4881d05, ++ 0xd9d4d039, 0xe6db99e5, 0x1fa27cf8, 0xc4ac5665, ++ ++ 0xf4292244, 0x432aff97, 0xab9423a7, 0xfc93a039, ++ 0x655b59c3, 0x8f0ccc92, 0xffeff47d, 0x85845dd1, ++ 0x6fa87e4f, 0xfe2ce6e0, 0xa3014314, 0x4e0811a1, ++ 0xf7537e82, 0xbd3af235, 0x2ad7d2bb, 0xeb86d391, ++}; ++ ++static const u_int8_t md5_paddat[MD5_BUFLEN] = { ++ 0x80, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, ++}; ++ ++static void md5_calc(u_int8_t *, md5_ctxt *); ++ ++void md5_init(ctxt) ++ md5_ctxt *ctxt; ++{ ++ ctxt->md5_n = 0; ++ ctxt->md5_i = 0; ++ ctxt->md5_sta = MD5_A0; ++ ctxt->md5_stb = MD5_B0; ++ ctxt->md5_stc = MD5_C0; ++ ctxt->md5_std = MD5_D0; ++ bzero(ctxt->md5_buf, sizeof(ctxt->md5_buf)); ++} ++ ++void md5_loop(ctxt, input, len) ++ md5_ctxt *ctxt; ++ u_int8_t *input; ++ u_int len; /* number of bytes */ ++{ ++ u_int gap, i; ++ ++ ctxt->md5_n += len * 8; /* byte to bit */ ++ gap = MD5_BUFLEN - ctxt->md5_i; ++ ++ if (len >= gap) { ++ bcopy((void *)input, (void *)(ctxt->md5_buf + ctxt->md5_i), ++ gap); ++ md5_calc(ctxt->md5_buf, ctxt); ++ ++ for (i = gap; i + MD5_BUFLEN <= len; i += MD5_BUFLEN) { ++ md5_calc((u_int8_t *)(input + i), ctxt); ++ } ++ ++ ctxt->md5_i = len - i; ++ bcopy((void *)(input + i), (void *)ctxt->md5_buf, ctxt->md5_i); ++ } else { ++ bcopy((void *)input, (void *)(ctxt->md5_buf + ctxt->md5_i), ++ len); ++ ctxt->md5_i += len; ++ } ++} ++ ++void md5_pad(ctxt) ++ md5_ctxt *ctxt; ++{ ++ u_int gap; ++ ++ /* Don't count up padding. Keep md5_n. */ ++ gap = MD5_BUFLEN - ctxt->md5_i; ++ if (gap > 8) { ++ bcopy(md5_paddat, ++ (void *)(ctxt->md5_buf + ctxt->md5_i), ++ gap - sizeof(ctxt->md5_n)); ++ } else { ++ /* including gap == 8 */ ++ bcopy(md5_paddat, (void *)(ctxt->md5_buf + ctxt->md5_i), ++ gap); ++ md5_calc(ctxt->md5_buf, ctxt); ++ bcopy((md5_paddat + gap), ++ (void *)ctxt->md5_buf, ++ MD5_BUFLEN - sizeof(ctxt->md5_n)); ++ } ++ ++ /* 8 byte word */ ++#if BYTE_ORDER == LITTLE_ENDIAN ++ bcopy(&ctxt->md5_n8[0], &ctxt->md5_buf[56], 8); ++#endif ++#if BYTE_ORDER == BIG_ENDIAN ++ ctxt->md5_buf[56] = ctxt->md5_n8[7]; ++ ctxt->md5_buf[57] = ctxt->md5_n8[6]; ++ ctxt->md5_buf[58] = ctxt->md5_n8[5]; ++ ctxt->md5_buf[59] = ctxt->md5_n8[4]; ++ ctxt->md5_buf[60] = ctxt->md5_n8[3]; ++ ctxt->md5_buf[61] = ctxt->md5_n8[2]; ++ ctxt->md5_buf[62] = ctxt->md5_n8[1]; ++ ctxt->md5_buf[63] = ctxt->md5_n8[0]; ++#endif ++ ++ md5_calc(ctxt->md5_buf, ctxt); ++} ++ ++void md5_result(digest, ctxt) ++ u_int8_t *digest; ++ md5_ctxt *ctxt; ++{ ++ /* 4 byte words */ ++#if BYTE_ORDER == LITTLE_ENDIAN ++ bcopy(&ctxt->md5_st8[0], digest, 16); ++#endif ++#if BYTE_ORDER == BIG_ENDIAN ++ digest[ 0] = ctxt->md5_st8[ 3]; digest[ 1] = ctxt->md5_st8[ 2]; ++ digest[ 2] = ctxt->md5_st8[ 1]; digest[ 3] = ctxt->md5_st8[ 0]; ++ digest[ 4] = ctxt->md5_st8[ 7]; digest[ 5] = ctxt->md5_st8[ 6]; ++ digest[ 6] = ctxt->md5_st8[ 5]; digest[ 7] = ctxt->md5_st8[ 4]; ++ digest[ 8] = ctxt->md5_st8[11]; digest[ 9] = ctxt->md5_st8[10]; ++ digest[10] = ctxt->md5_st8[ 9]; digest[11] = ctxt->md5_st8[ 8]; ++ digest[12] = ctxt->md5_st8[15]; digest[13] = ctxt->md5_st8[14]; ++ digest[14] = ctxt->md5_st8[13]; digest[15] = ctxt->md5_st8[12]; ++#endif ++} ++ ++static void md5_calc(b64, ctxt) ++ u_int8_t *b64; ++ md5_ctxt *ctxt; ++{ ++ u_int32_t A = ctxt->md5_sta; ++ u_int32_t B = ctxt->md5_stb; ++ u_int32_t C = ctxt->md5_stc; ++ u_int32_t D = ctxt->md5_std; ++#if BYTE_ORDER == LITTLE_ENDIAN ++ u_int32_t *X = (u_int32_t *)b64; ++#endif ++#if BYTE_ORDER == BIG_ENDIAN ++ /* 4 byte words */ ++ /* what a brute force but fast! */ ++ u_int32_t X[16]; ++ u_int8_t *y = (u_int8_t *)X; ++ y[ 0] = b64[ 3]; y[ 1] = b64[ 2]; y[ 2] = b64[ 1]; y[ 3] = b64[ 0]; ++ y[ 4] = b64[ 7]; y[ 5] = b64[ 6]; y[ 6] = b64[ 5]; y[ 7] = b64[ 4]; ++ y[ 8] = b64[11]; y[ 9] = b64[10]; y[10] = b64[ 9]; y[11] = b64[ 8]; ++ y[12] = b64[15]; y[13] = b64[14]; y[14] = b64[13]; y[15] = b64[12]; ++ y[16] = b64[19]; y[17] = b64[18]; y[18] = b64[17]; y[19] = b64[16]; ++ y[20] = b64[23]; y[21] = b64[22]; y[22] = b64[21]; y[23] = b64[20]; ++ y[24] = b64[27]; y[25] = b64[26]; y[26] = b64[25]; y[27] = b64[24]; ++ y[28] = b64[31]; y[29] = b64[30]; y[30] = b64[29]; y[31] = b64[28]; ++ y[32] = b64[35]; y[33] = b64[34]; y[34] = b64[33]; y[35] = b64[32]; ++ y[36] = b64[39]; y[37] = b64[38]; y[38] = b64[37]; y[39] = b64[36]; ++ y[40] = b64[43]; y[41] = b64[42]; y[42] = b64[41]; y[43] = b64[40]; ++ y[44] = b64[47]; y[45] = b64[46]; y[46] = b64[45]; y[47] = b64[44]; ++ y[48] = b64[51]; y[49] = b64[50]; y[50] = b64[49]; y[51] = b64[48]; ++ y[52] = b64[55]; y[53] = b64[54]; y[54] = b64[53]; y[55] = b64[52]; ++ y[56] = b64[59]; y[57] = b64[58]; y[58] = b64[57]; y[59] = b64[56]; ++ y[60] = b64[63]; y[61] = b64[62]; y[62] = b64[61]; y[63] = b64[60]; ++#endif ++ ++ ROUND1(A, B, C, D, 0, Sa, 1); ROUND1(D, A, B, C, 1, Sb, 2); ++ ROUND1(C, D, A, B, 2, Sc, 3); ROUND1(B, C, D, A, 3, Sd, 4); ++ ROUND1(A, B, C, D, 4, Sa, 5); ROUND1(D, A, B, C, 5, Sb, 6); ++ ROUND1(C, D, A, B, 6, Sc, 7); ROUND1(B, C, D, A, 7, Sd, 8); ++ ROUND1(A, B, C, D, 8, Sa, 9); ROUND1(D, A, B, C, 9, Sb, 10); ++ ROUND1(C, D, A, B, 10, Sc, 11); ROUND1(B, C, D, A, 11, Sd, 12); ++ ROUND1(A, B, C, D, 12, Sa, 13); ROUND1(D, A, B, C, 13, Sb, 14); ++ ROUND1(C, D, A, B, 14, Sc, 15); ROUND1(B, C, D, A, 15, Sd, 16); ++ ++ ROUND2(A, B, C, D, 1, Se, 17); ROUND2(D, A, B, C, 6, Sf, 18); ++ ROUND2(C, D, A, B, 11, Sg, 19); ROUND2(B, C, D, A, 0, Sh, 20); ++ ROUND2(A, B, C, D, 5, Se, 21); ROUND2(D, A, B, C, 10, Sf, 22); ++ ROUND2(C, D, A, B, 15, Sg, 23); ROUND2(B, C, D, A, 4, Sh, 24); ++ ROUND2(A, B, C, D, 9, Se, 25); ROUND2(D, A, B, C, 14, Sf, 26); ++ ROUND2(C, D, A, B, 3, Sg, 27); ROUND2(B, C, D, A, 8, Sh, 28); ++ ROUND2(A, B, C, D, 13, Se, 29); ROUND2(D, A, B, C, 2, Sf, 30); ++ ROUND2(C, D, A, B, 7, Sg, 31); ROUND2(B, C, D, A, 12, Sh, 32); ++ ++ ROUND3(A, B, C, D, 5, Si, 33); ROUND3(D, A, B, C, 8, Sj, 34); ++ ROUND3(C, D, A, B, 11, Sk, 35); ROUND3(B, C, D, A, 14, Sl, 36); ++ ROUND3(A, B, C, D, 1, Si, 37); ROUND3(D, A, B, C, 4, Sj, 38); ++ ROUND3(C, D, A, B, 7, Sk, 39); ROUND3(B, C, D, A, 10, Sl, 40); ++ ROUND3(A, B, C, D, 13, Si, 41); ROUND3(D, A, B, C, 0, Sj, 42); ++ ROUND3(C, D, A, B, 3, Sk, 43); ROUND3(B, C, D, A, 6, Sl, 44); ++ ROUND3(A, B, C, D, 9, Si, 45); ROUND3(D, A, B, C, 12, Sj, 46); ++ ROUND3(C, D, A, B, 15, Sk, 47); ROUND3(B, C, D, A, 2, Sl, 48); ++ ++ ROUND4(A, B, C, D, 0, Sm, 49); ROUND4(D, A, B, C, 7, Sn, 50); ++ ROUND4(C, D, A, B, 14, So, 51); ROUND4(B, C, D, A, 5, Sp, 52); ++ ROUND4(A, B, C, D, 12, Sm, 53); ROUND4(D, A, B, C, 3, Sn, 54); ++ ROUND4(C, D, A, B, 10, So, 55); ROUND4(B, C, D, A, 1, Sp, 56); ++ ROUND4(A, B, C, D, 8, Sm, 57); ROUND4(D, A, B, C, 15, Sn, 58); ++ ROUND4(C, D, A, B, 6, So, 59); ROUND4(B, C, D, A, 13, Sp, 60); ++ ROUND4(A, B, C, D, 4, Sm, 61); ROUND4(D, A, B, C, 11, Sn, 62); ++ ROUND4(C, D, A, B, 2, So, 63); ROUND4(B, C, D, A, 9, Sp, 64); ++ ++ ctxt->md5_sta += A; ++ ctxt->md5_stb += B; ++ ctxt->md5_stc += C; ++ ctxt->md5_std += D; ++} +diff -Nur linux-3.1.4.orig/crypto/ocf/safe/md5.h linux-3.1.4/crypto/ocf/safe/md5.h +--- linux-3.1.4.orig/crypto/ocf/safe/md5.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/safe/md5.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,76 @@ ++/* $FreeBSD: src/sys/crypto/md5.h,v 1.4 2002/03/20 05:13:50 alfred Exp $ */ ++/* $KAME: md5.h,v 1.4 2000/03/27 04:36:22 sumikawa Exp $ */ ++ ++/* ++ * Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. Neither the name of the project nor the names of its contributors ++ * may be used to endorse or promote products derived from this software ++ * without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND ++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE ++ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ++ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ++ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF ++ * SUCH DAMAGE. ++ */ ++ ++#ifndef _NETINET6_MD5_H_ ++#define _NETINET6_MD5_H_ ++ ++#define MD5_BUFLEN 64 ++ ++typedef struct { ++ union { ++ u_int32_t md5_state32[4]; ++ u_int8_t md5_state8[16]; ++ } md5_st; ++ ++#define md5_sta md5_st.md5_state32[0] ++#define md5_stb md5_st.md5_state32[1] ++#define md5_stc md5_st.md5_state32[2] ++#define md5_std md5_st.md5_state32[3] ++#define md5_st8 md5_st.md5_state8 ++ ++ union { ++ u_int64_t md5_count64; ++ u_int8_t md5_count8[8]; ++ } md5_count; ++#define md5_n md5_count.md5_count64 ++#define md5_n8 md5_count.md5_count8 ++ ++ u_int md5_i; ++ u_int8_t md5_buf[MD5_BUFLEN]; ++} md5_ctxt; ++ ++extern void md5_init(md5_ctxt *); ++extern void md5_loop(md5_ctxt *, u_int8_t *, u_int); ++extern void md5_pad(md5_ctxt *); ++extern void md5_result(u_int8_t *, md5_ctxt *); ++ ++/* compatibility */ ++#define MD5_CTX md5_ctxt ++#define MD5Init(x) md5_init((x)) ++#define MD5Update(x, y, z) md5_loop((x), (y), (z)) ++#define MD5Final(x, y) \ ++do { \ ++ md5_pad((y)); \ ++ md5_result((x), (y)); \ ++} while (0) ++ ++#endif /* ! _NETINET6_MD5_H_*/ +diff -Nur linux-3.1.4.orig/crypto/ocf/safe/safe.c linux-3.1.4/crypto/ocf/safe/safe.c +--- linux-3.1.4.orig/crypto/ocf/safe/safe.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/safe/safe.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,2230 @@ ++/*- ++ * Linux port done by David McCullough ++ * Copyright (C) 2004-2010 David McCullough ++ * The license and original author are listed below. ++ * ++ * Copyright (c) 2003 Sam Leffler, Errno Consulting ++ * Copyright (c) 2003 Global Technology Associates, Inc. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE ++ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ++ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ++ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF ++ * SUCH DAMAGE. ++ * ++__FBSDID("$FreeBSD: src/sys/dev/safe/safe.c,v 1.18 2007/03/21 03:42:50 sam Exp $"); ++ */ ++ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* ++ * SafeNet SafeXcel-1141 hardware crypto accelerator ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#if 1 ++#define DPRINTF(a) do { \ ++ if (debug) { \ ++ printk("%s: ", sc ? \ ++ device_get_nameunit(sc->sc_dev) : "safe"); \ ++ printk a; \ ++ } \ ++ } while (0) ++#else ++#define DPRINTF(a) ++#endif ++ ++/* ++ * until we find a cleaner way, include the BSD md5/sha1 code ++ * here ++ */ ++#define HMAC_HACK 1 ++#ifdef HMAC_HACK ++#include ++#include ++#include ++#include ++#include ++#endif /* HMAC_HACK */ ++ ++/* add proc entry for this */ ++struct safe_stats safestats; ++ ++#define debug safe_debug ++int safe_debug = 0; ++module_param(safe_debug, int, 0644); ++MODULE_PARM_DESC(safe_debug, "Enable debug"); ++ ++static void safe_callback(struct safe_softc *, struct safe_ringentry *); ++static void safe_feed(struct safe_softc *, struct safe_ringentry *); ++#if defined(CONFIG_OCF_RANDOMHARVEST) && !defined(SAFE_NO_RNG) ++static void safe_rng_init(struct safe_softc *); ++int safe_rngbufsize = 8; /* 32 bytes each read */ ++module_param(safe_rngbufsize, int, 0644); ++MODULE_PARM_DESC(safe_rngbufsize, "RNG polling buffer size (32-bit words)"); ++int safe_rngmaxalarm = 8; /* max alarms before reset */ ++module_param(safe_rngmaxalarm, int, 0644); ++MODULE_PARM_DESC(safe_rngmaxalarm, "RNG max alarms before reset"); ++#endif /* SAFE_NO_RNG */ ++ ++static void safe_totalreset(struct safe_softc *sc); ++static int safe_dmamap_aligned(struct safe_softc *sc, const struct safe_operand *op); ++static int safe_dmamap_uniform(struct safe_softc *sc, const struct safe_operand *op); ++static int safe_free_entry(struct safe_softc *sc, struct safe_ringentry *re); ++static int safe_kprocess(device_t dev, struct cryptkop *krp, int hint); ++static int safe_kstart(struct safe_softc *sc); ++static int safe_ksigbits(struct safe_softc *sc, struct crparam *cr); ++static void safe_kfeed(struct safe_softc *sc); ++static void safe_kpoll(unsigned long arg); ++static void safe_kload_reg(struct safe_softc *sc, u_int32_t off, ++ u_int32_t len, struct crparam *n); ++ ++static int safe_newsession(device_t, u_int32_t *, struct cryptoini *); ++static int safe_freesession(device_t, u_int64_t); ++static int safe_process(device_t, struct cryptop *, int); ++ ++static device_method_t safe_methods = { ++ /* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, safe_newsession), ++ DEVMETHOD(cryptodev_freesession,safe_freesession), ++ DEVMETHOD(cryptodev_process, safe_process), ++ DEVMETHOD(cryptodev_kprocess, safe_kprocess), ++}; ++ ++#define READ_REG(sc,r) readl((sc)->sc_base_addr + (r)) ++#define WRITE_REG(sc,r,val) writel((val), (sc)->sc_base_addr + (r)) ++ ++#define SAFE_MAX_CHIPS 8 ++static struct safe_softc *safe_chip_idx[SAFE_MAX_CHIPS]; ++ ++/* ++ * split our buffers up into safe DMAable byte fragments to avoid lockup ++ * bug in 1141 HW on rev 1.0. ++ */ ++ ++static int ++pci_map_linear( ++ struct safe_softc *sc, ++ struct safe_operand *buf, ++ void *addr, ++ int len) ++{ ++ dma_addr_t tmp; ++ int chunk, tlen = len; ++ ++ tmp = pci_map_single(sc->sc_pcidev, addr, len, PCI_DMA_BIDIRECTIONAL); ++ ++ buf->mapsize += len; ++ while (len > 0) { ++ chunk = (len > sc->sc_max_dsize) ? sc->sc_max_dsize : len; ++ buf->segs[buf->nsegs].ds_addr = tmp; ++ buf->segs[buf->nsegs].ds_len = chunk; ++ buf->segs[buf->nsegs].ds_tlen = tlen; ++ buf->nsegs++; ++ tmp += chunk; ++ len -= chunk; ++ tlen = 0; ++ } ++ return 0; ++} ++ ++/* ++ * map in a given uio buffer (great on some arches :-) ++ */ ++ ++static int ++pci_map_uio(struct safe_softc *sc, struct safe_operand *buf, struct uio *uio) ++{ ++ struct iovec *iov = uio->uio_iov; ++ int n; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ buf->mapsize = 0; ++ buf->nsegs = 0; ++ ++ for (n = 0; n < uio->uio_iovcnt; n++) { ++ pci_map_linear(sc, buf, iov->iov_base, iov->iov_len); ++ iov++; ++ } ++ ++ /* identify this buffer by the first segment */ ++ buf->map = (void *) buf->segs[0].ds_addr; ++ return(0); ++} ++ ++/* ++ * map in a given sk_buff ++ */ ++ ++static int ++pci_map_skb(struct safe_softc *sc,struct safe_operand *buf,struct sk_buff *skb) ++{ ++ int i; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ buf->mapsize = 0; ++ buf->nsegs = 0; ++ ++ pci_map_linear(sc, buf, skb->data, skb_headlen(skb)); ++ ++ for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { ++ pci_map_linear(sc, buf, ++ page_address(skb_shinfo(skb)->frags[i].page) + ++ skb_shinfo(skb)->frags[i].page_offset, ++ skb_shinfo(skb)->frags[i].size); ++ } ++ ++ /* identify this buffer by the first segment */ ++ buf->map = (void *) buf->segs[0].ds_addr; ++ return(0); ++} ++ ++ ++#if 0 /* not needed at this time */ ++static void ++pci_sync_operand(struct safe_softc *sc, struct safe_operand *buf) ++{ ++ int i; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ for (i = 0; i < buf->nsegs; i++) ++ pci_dma_sync_single_for_cpu(sc->sc_pcidev, buf->segs[i].ds_addr, ++ buf->segs[i].ds_len, PCI_DMA_BIDIRECTIONAL); ++} ++#endif ++ ++static void ++pci_unmap_operand(struct safe_softc *sc, struct safe_operand *buf) ++{ ++ int i; ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ for (i = 0; i < buf->nsegs; i++) { ++ if (buf->segs[i].ds_tlen) { ++ DPRINTF(("%s - unmap %d 0x%x %d\n", __FUNCTION__, i, buf->segs[i].ds_addr, buf->segs[i].ds_tlen)); ++ pci_unmap_single(sc->sc_pcidev, buf->segs[i].ds_addr, ++ buf->segs[i].ds_tlen, PCI_DMA_BIDIRECTIONAL); ++ DPRINTF(("%s - unmap %d 0x%x %d done\n", __FUNCTION__, i, buf->segs[i].ds_addr, buf->segs[i].ds_tlen)); ++ } ++ buf->segs[i].ds_addr = 0; ++ buf->segs[i].ds_len = 0; ++ buf->segs[i].ds_tlen = 0; ++ } ++ buf->nsegs = 0; ++ buf->mapsize = 0; ++ buf->map = 0; ++} ++ ++ ++/* ++ * SafeXcel Interrupt routine ++ */ ++static irqreturn_t ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) ++safe_intr(int irq, void *arg) ++#else ++safe_intr(int irq, void *arg, struct pt_regs *regs) ++#endif ++{ ++ struct safe_softc *sc = arg; ++ int stat; ++ unsigned long flags; ++ ++ stat = READ_REG(sc, SAFE_HM_STAT); ++ ++ DPRINTF(("%s(stat=0x%x)\n", __FUNCTION__, stat)); ++ ++ if (stat == 0) /* shared irq, not for us */ ++ return IRQ_NONE; ++ ++ WRITE_REG(sc, SAFE_HI_CLR, stat); /* IACK */ ++ ++ if ((stat & SAFE_INT_PE_DDONE)) { ++ /* ++ * Descriptor(s) done; scan the ring and ++ * process completed operations. ++ */ ++ spin_lock_irqsave(&sc->sc_ringmtx, flags); ++ while (sc->sc_back != sc->sc_front) { ++ struct safe_ringentry *re = sc->sc_back; ++ ++#ifdef SAFE_DEBUG ++ if (debug) { ++ safe_dump_ringstate(sc, __func__); ++ safe_dump_request(sc, __func__, re); ++ } ++#endif ++ /* ++ * safe_process marks ring entries that were allocated ++ * but not used with a csr of zero. This insures the ++ * ring front pointer never needs to be set backwards ++ * in the event that an entry is allocated but not used ++ * because of a setup error. ++ */ ++ DPRINTF(("%s re->re_desc.d_csr=0x%x\n", __FUNCTION__, re->re_desc.d_csr)); ++ if (re->re_desc.d_csr != 0) { ++ if (!SAFE_PE_CSR_IS_DONE(re->re_desc.d_csr)) { ++ DPRINTF(("%s !CSR_IS_DONE\n", __FUNCTION__)); ++ break; ++ } ++ if (!SAFE_PE_LEN_IS_DONE(re->re_desc.d_len)) { ++ DPRINTF(("%s !LEN_IS_DONE\n", __FUNCTION__)); ++ break; ++ } ++ sc->sc_nqchip--; ++ safe_callback(sc, re); ++ } ++ if (++(sc->sc_back) == sc->sc_ringtop) ++ sc->sc_back = sc->sc_ring; ++ } ++ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); ++ } ++ ++ /* ++ * Check to see if we got any DMA Error ++ */ ++ if (stat & SAFE_INT_PE_ERROR) { ++ printk("%s: dmaerr dmastat %08x\n", device_get_nameunit(sc->sc_dev), ++ (int)READ_REG(sc, SAFE_PE_DMASTAT)); ++ safestats.st_dmaerr++; ++ safe_totalreset(sc); ++#if 0 ++ safe_feed(sc); ++#endif ++ } ++ ++ if (sc->sc_needwakeup) { /* XXX check high watermark */ ++ int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); ++ DPRINTF(("%s: wakeup crypto %x\n", __func__, ++ sc->sc_needwakeup)); ++ sc->sc_needwakeup &= ~wakeup; ++ crypto_unblock(sc->sc_cid, wakeup); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++/* ++ * safe_feed() - post a request to chip ++ */ ++static void ++safe_feed(struct safe_softc *sc, struct safe_ringentry *re) ++{ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++#ifdef SAFE_DEBUG ++ if (debug) { ++ safe_dump_ringstate(sc, __func__); ++ safe_dump_request(sc, __func__, re); ++ } ++#endif ++ sc->sc_nqchip++; ++ if (sc->sc_nqchip > safestats.st_maxqchip) ++ safestats.st_maxqchip = sc->sc_nqchip; ++ /* poke h/w to check descriptor ring, any value can be written */ ++ WRITE_REG(sc, SAFE_HI_RD_DESCR, 0); ++} ++ ++#define N(a) (sizeof(a) / sizeof (a[0])) ++static void ++safe_setup_enckey(struct safe_session *ses, caddr_t key) ++{ ++ int i; ++ ++ bcopy(key, ses->ses_key, ses->ses_klen / 8); ++ ++ /* PE is little-endian, insure proper byte order */ ++ for (i = 0; i < N(ses->ses_key); i++) ++ ses->ses_key[i] = htole32(ses->ses_key[i]); ++} ++ ++static void ++safe_setup_mackey(struct safe_session *ses, int algo, caddr_t key, int klen) ++{ ++#ifdef HMAC_HACK ++ MD5_CTX md5ctx; ++ SHA1_CTX sha1ctx; ++ int i; ++ ++ ++ for (i = 0; i < klen; i++) ++ key[i] ^= HMAC_IPAD_VAL; ++ ++ if (algo == CRYPTO_MD5_HMAC) { ++ MD5Init(&md5ctx); ++ MD5Update(&md5ctx, key, klen); ++ MD5Update(&md5ctx, hmac_ipad_buffer, MD5_HMAC_BLOCK_LEN - klen); ++ bcopy(md5ctx.md5_st8, ses->ses_hminner, sizeof(md5ctx.md5_st8)); ++ } else { ++ SHA1Init(&sha1ctx); ++ SHA1Update(&sha1ctx, key, klen); ++ SHA1Update(&sha1ctx, hmac_ipad_buffer, ++ SHA1_HMAC_BLOCK_LEN - klen); ++ bcopy(sha1ctx.h.b32, ses->ses_hminner, sizeof(sha1ctx.h.b32)); ++ } ++ ++ for (i = 0; i < klen; i++) ++ key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); ++ ++ if (algo == CRYPTO_MD5_HMAC) { ++ MD5Init(&md5ctx); ++ MD5Update(&md5ctx, key, klen); ++ MD5Update(&md5ctx, hmac_opad_buffer, MD5_HMAC_BLOCK_LEN - klen); ++ bcopy(md5ctx.md5_st8, ses->ses_hmouter, sizeof(md5ctx.md5_st8)); ++ } else { ++ SHA1Init(&sha1ctx); ++ SHA1Update(&sha1ctx, key, klen); ++ SHA1Update(&sha1ctx, hmac_opad_buffer, ++ SHA1_HMAC_BLOCK_LEN - klen); ++ bcopy(sha1ctx.h.b32, ses->ses_hmouter, sizeof(sha1ctx.h.b32)); ++ } ++ ++ for (i = 0; i < klen; i++) ++ key[i] ^= HMAC_OPAD_VAL; ++ ++#if 0 ++ /* ++ * this code prevents SHA working on a BE host, ++ * so it is obviously wrong. I think the byte ++ * swap setup we do with the chip fixes this for us ++ */ ++ ++ /* PE is little-endian, insure proper byte order */ ++ for (i = 0; i < N(ses->ses_hminner); i++) { ++ ses->ses_hminner[i] = htole32(ses->ses_hminner[i]); ++ ses->ses_hmouter[i] = htole32(ses->ses_hmouter[i]); ++ } ++#endif ++#else /* HMAC_HACK */ ++ printk("safe: md5/sha not implemented\n"); ++#endif /* HMAC_HACK */ ++} ++#undef N ++ ++/* ++ * Allocate a new 'session' and return an encoded session id. 'sidp' ++ * contains our registration id, and should contain an encoded session ++ * id on successful allocation. ++ */ ++static int ++safe_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) ++{ ++ struct safe_softc *sc = device_get_softc(dev); ++ struct cryptoini *c, *encini = NULL, *macini = NULL; ++ struct safe_session *ses = NULL; ++ int sesn; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ if (sidp == NULL || cri == NULL || sc == NULL) ++ return (EINVAL); ++ ++ for (c = cri; c != NULL; c = c->cri_next) { ++ if (c->cri_alg == CRYPTO_MD5_HMAC || ++ c->cri_alg == CRYPTO_SHA1_HMAC || ++ c->cri_alg == CRYPTO_NULL_HMAC) { ++ if (macini) ++ return (EINVAL); ++ macini = c; ++ } else if (c->cri_alg == CRYPTO_DES_CBC || ++ c->cri_alg == CRYPTO_3DES_CBC || ++ c->cri_alg == CRYPTO_AES_CBC || ++ c->cri_alg == CRYPTO_NULL_CBC) { ++ if (encini) ++ return (EINVAL); ++ encini = c; ++ } else ++ return (EINVAL); ++ } ++ if (encini == NULL && macini == NULL) ++ return (EINVAL); ++ if (encini) { /* validate key length */ ++ switch (encini->cri_alg) { ++ case CRYPTO_DES_CBC: ++ if (encini->cri_klen != 64) ++ return (EINVAL); ++ break; ++ case CRYPTO_3DES_CBC: ++ if (encini->cri_klen != 192) ++ return (EINVAL); ++ break; ++ case CRYPTO_AES_CBC: ++ if (encini->cri_klen != 128 && ++ encini->cri_klen != 192 && ++ encini->cri_klen != 256) ++ return (EINVAL); ++ break; ++ } ++ } ++ ++ if (sc->sc_sessions == NULL) { ++ ses = sc->sc_sessions = (struct safe_session *) ++ kmalloc(sizeof(struct safe_session), SLAB_ATOMIC); ++ if (ses == NULL) ++ return (ENOMEM); ++ memset(ses, 0, sizeof(struct safe_session)); ++ sesn = 0; ++ sc->sc_nsessions = 1; ++ } else { ++ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { ++ if (sc->sc_sessions[sesn].ses_used == 0) { ++ ses = &sc->sc_sessions[sesn]; ++ break; ++ } ++ } ++ ++ if (ses == NULL) { ++ sesn = sc->sc_nsessions; ++ ses = (struct safe_session *) ++ kmalloc((sesn + 1) * sizeof(struct safe_session), SLAB_ATOMIC); ++ if (ses == NULL) ++ return (ENOMEM); ++ memset(ses, 0, (sesn + 1) * sizeof(struct safe_session)); ++ bcopy(sc->sc_sessions, ses, sesn * ++ sizeof(struct safe_session)); ++ bzero(sc->sc_sessions, sesn * ++ sizeof(struct safe_session)); ++ kfree(sc->sc_sessions); ++ sc->sc_sessions = ses; ++ ses = &sc->sc_sessions[sesn]; ++ sc->sc_nsessions++; ++ } ++ } ++ ++ bzero(ses, sizeof(struct safe_session)); ++ ses->ses_used = 1; ++ ++ if (encini) { ++ ses->ses_klen = encini->cri_klen; ++ if (encini->cri_key != NULL) ++ safe_setup_enckey(ses, encini->cri_key); ++ } ++ ++ if (macini) { ++ ses->ses_mlen = macini->cri_mlen; ++ if (ses->ses_mlen == 0) { ++ if (macini->cri_alg == CRYPTO_MD5_HMAC) ++ ses->ses_mlen = MD5_HASH_LEN; ++ else ++ ses->ses_mlen = SHA1_HASH_LEN; ++ } ++ ++ if (macini->cri_key != NULL) { ++ safe_setup_mackey(ses, macini->cri_alg, macini->cri_key, ++ macini->cri_klen / 8); ++ } ++ } ++ ++ *sidp = SAFE_SID(device_get_unit(sc->sc_dev), sesn); ++ return (0); ++} ++ ++/* ++ * Deallocate a session. ++ */ ++static int ++safe_freesession(device_t dev, u_int64_t tid) ++{ ++ struct safe_softc *sc = device_get_softc(dev); ++ int session, ret; ++ u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ if (sc == NULL) ++ return (EINVAL); ++ ++ session = SAFE_SESSION(sid); ++ if (session < sc->sc_nsessions) { ++ bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session])); ++ ret = 0; ++ } else ++ ret = EINVAL; ++ return (ret); ++} ++ ++ ++static int ++safe_process(device_t dev, struct cryptop *crp, int hint) ++{ ++ struct safe_softc *sc = device_get_softc(dev); ++ int err = 0, i, nicealign, uniform; ++ struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; ++ int bypass, oplen, ivsize; ++ caddr_t iv; ++ int16_t coffset; ++ struct safe_session *ses; ++ struct safe_ringentry *re; ++ struct safe_sarec *sa; ++ struct safe_pdesc *pd; ++ u_int32_t cmd0, cmd1, staterec, rand_iv[4]; ++ unsigned long flags; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { ++ safestats.st_invalid++; ++ return (EINVAL); ++ } ++ if (SAFE_SESSION(crp->crp_sid) >= sc->sc_nsessions) { ++ safestats.st_badsession++; ++ return (EINVAL); ++ } ++ ++ spin_lock_irqsave(&sc->sc_ringmtx, flags); ++ if (sc->sc_front == sc->sc_back && sc->sc_nqchip != 0) { ++ safestats.st_ringfull++; ++ sc->sc_needwakeup |= CRYPTO_SYMQ; ++ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); ++ return (ERESTART); ++ } ++ re = sc->sc_front; ++ ++ staterec = re->re_sa.sa_staterec; /* save */ ++ /* NB: zero everything but the PE descriptor */ ++ bzero(&re->re_sa, sizeof(struct safe_ringentry) - sizeof(re->re_desc)); ++ re->re_sa.sa_staterec = staterec; /* restore */ ++ ++ re->re_crp = crp; ++ re->re_sesn = SAFE_SESSION(crp->crp_sid); ++ ++ re->re_src.nsegs = 0; ++ re->re_dst.nsegs = 0; ++ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ re->re_src_skb = (struct sk_buff *)crp->crp_buf; ++ re->re_dst_skb = (struct sk_buff *)crp->crp_buf; ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ re->re_src_io = (struct uio *)crp->crp_buf; ++ re->re_dst_io = (struct uio *)crp->crp_buf; ++ } else { ++ safestats.st_badflags++; ++ err = EINVAL; ++ goto errout; /* XXX we don't handle contiguous blocks! */ ++ } ++ ++ sa = &re->re_sa; ++ ses = &sc->sc_sessions[re->re_sesn]; ++ ++ crd1 = crp->crp_desc; ++ if (crd1 == NULL) { ++ safestats.st_nodesc++; ++ err = EINVAL; ++ goto errout; ++ } ++ crd2 = crd1->crd_next; ++ ++ cmd0 = SAFE_SA_CMD0_BASIC; /* basic group operation */ ++ cmd1 = 0; ++ if (crd2 == NULL) { ++ if (crd1->crd_alg == CRYPTO_MD5_HMAC || ++ crd1->crd_alg == CRYPTO_SHA1_HMAC || ++ crd1->crd_alg == CRYPTO_NULL_HMAC) { ++ maccrd = crd1; ++ enccrd = NULL; ++ cmd0 |= SAFE_SA_CMD0_OP_HASH; ++ } else if (crd1->crd_alg == CRYPTO_DES_CBC || ++ crd1->crd_alg == CRYPTO_3DES_CBC || ++ crd1->crd_alg == CRYPTO_AES_CBC || ++ crd1->crd_alg == CRYPTO_NULL_CBC) { ++ maccrd = NULL; ++ enccrd = crd1; ++ cmd0 |= SAFE_SA_CMD0_OP_CRYPT; ++ } else { ++ safestats.st_badalg++; ++ err = EINVAL; ++ goto errout; ++ } ++ } else { ++ if ((crd1->crd_alg == CRYPTO_MD5_HMAC || ++ crd1->crd_alg == CRYPTO_SHA1_HMAC || ++ crd1->crd_alg == CRYPTO_NULL_HMAC) && ++ (crd2->crd_alg == CRYPTO_DES_CBC || ++ crd2->crd_alg == CRYPTO_3DES_CBC || ++ crd2->crd_alg == CRYPTO_AES_CBC || ++ crd2->crd_alg == CRYPTO_NULL_CBC) && ++ ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { ++ maccrd = crd1; ++ enccrd = crd2; ++ } else if ((crd1->crd_alg == CRYPTO_DES_CBC || ++ crd1->crd_alg == CRYPTO_3DES_CBC || ++ crd1->crd_alg == CRYPTO_AES_CBC || ++ crd1->crd_alg == CRYPTO_NULL_CBC) && ++ (crd2->crd_alg == CRYPTO_MD5_HMAC || ++ crd2->crd_alg == CRYPTO_SHA1_HMAC || ++ crd2->crd_alg == CRYPTO_NULL_HMAC) && ++ (crd1->crd_flags & CRD_F_ENCRYPT)) { ++ enccrd = crd1; ++ maccrd = crd2; ++ } else { ++ safestats.st_badalg++; ++ err = EINVAL; ++ goto errout; ++ } ++ cmd0 |= SAFE_SA_CMD0_OP_BOTH; ++ } ++ ++ if (enccrd) { ++ if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) ++ safe_setup_enckey(ses, enccrd->crd_key); ++ ++ if (enccrd->crd_alg == CRYPTO_DES_CBC) { ++ cmd0 |= SAFE_SA_CMD0_DES; ++ cmd1 |= SAFE_SA_CMD1_CBC; ++ ivsize = 2*sizeof(u_int32_t); ++ } else if (enccrd->crd_alg == CRYPTO_3DES_CBC) { ++ cmd0 |= SAFE_SA_CMD0_3DES; ++ cmd1 |= SAFE_SA_CMD1_CBC; ++ ivsize = 2*sizeof(u_int32_t); ++ } else if (enccrd->crd_alg == CRYPTO_AES_CBC) { ++ cmd0 |= SAFE_SA_CMD0_AES; ++ cmd1 |= SAFE_SA_CMD1_CBC; ++ if (ses->ses_klen == 128) ++ cmd1 |= SAFE_SA_CMD1_AES128; ++ else if (ses->ses_klen == 192) ++ cmd1 |= SAFE_SA_CMD1_AES192; ++ else ++ cmd1 |= SAFE_SA_CMD1_AES256; ++ ivsize = 4*sizeof(u_int32_t); ++ } else { ++ cmd0 |= SAFE_SA_CMD0_CRYPT_NULL; ++ ivsize = 0; ++ } ++ ++ /* ++ * Setup encrypt/decrypt state. When using basic ops ++ * we can't use an inline IV because hash/crypt offset ++ * must be from the end of the IV to the start of the ++ * crypt data and this leaves out the preceding header ++ * from the hash calculation. Instead we place the IV ++ * in the state record and set the hash/crypt offset to ++ * copy both the header+IV. ++ */ ++ if (enccrd->crd_flags & CRD_F_ENCRYPT) { ++ cmd0 |= SAFE_SA_CMD0_OUTBOUND; ++ ++ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) ++ iv = enccrd->crd_iv; ++ else ++ read_random((iv = (caddr_t) &rand_iv[0]), sizeof(rand_iv)); ++ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ enccrd->crd_inject, ivsize, iv); ++ } ++ bcopy(iv, re->re_sastate.sa_saved_iv, ivsize); ++ /* make iv LE */ ++ for (i = 0; i < ivsize/sizeof(re->re_sastate.sa_saved_iv[0]); i++) ++ re->re_sastate.sa_saved_iv[i] = ++ cpu_to_le32(re->re_sastate.sa_saved_iv[i]); ++ cmd0 |= SAFE_SA_CMD0_IVLD_STATE | SAFE_SA_CMD0_SAVEIV; ++ re->re_flags |= SAFE_QFLAGS_COPYOUTIV; ++ } else { ++ cmd0 |= SAFE_SA_CMD0_INBOUND; ++ ++ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) { ++ bcopy(enccrd->crd_iv, ++ re->re_sastate.sa_saved_iv, ivsize); ++ } else { ++ crypto_copydata(crp->crp_flags, crp->crp_buf, ++ enccrd->crd_inject, ivsize, ++ (caddr_t)re->re_sastate.sa_saved_iv); ++ } ++ /* make iv LE */ ++ for (i = 0; i < ivsize/sizeof(re->re_sastate.sa_saved_iv[0]); i++) ++ re->re_sastate.sa_saved_iv[i] = ++ cpu_to_le32(re->re_sastate.sa_saved_iv[i]); ++ cmd0 |= SAFE_SA_CMD0_IVLD_STATE; ++ } ++ /* ++ * For basic encryption use the zero pad algorithm. ++ * This pads results to an 8-byte boundary and ++ * suppresses padding verification for inbound (i.e. ++ * decrypt) operations. ++ * ++ * NB: Not sure if the 8-byte pad boundary is a problem. ++ */ ++ cmd0 |= SAFE_SA_CMD0_PAD_ZERO; ++ ++ /* XXX assert key bufs have the same size */ ++ bcopy(ses->ses_key, sa->sa_key, sizeof(sa->sa_key)); ++ } ++ ++ if (maccrd) { ++ if (maccrd->crd_flags & CRD_F_KEY_EXPLICIT) { ++ safe_setup_mackey(ses, maccrd->crd_alg, ++ maccrd->crd_key, maccrd->crd_klen / 8); ++ } ++ ++ if (maccrd->crd_alg == CRYPTO_MD5_HMAC) { ++ cmd0 |= SAFE_SA_CMD0_MD5; ++ cmd1 |= SAFE_SA_CMD1_HMAC; /* NB: enable HMAC */ ++ } else if (maccrd->crd_alg == CRYPTO_SHA1_HMAC) { ++ cmd0 |= SAFE_SA_CMD0_SHA1; ++ cmd1 |= SAFE_SA_CMD1_HMAC; /* NB: enable HMAC */ ++ } else { ++ cmd0 |= SAFE_SA_CMD0_HASH_NULL; ++ } ++ /* ++ * Digest data is loaded from the SA and the hash ++ * result is saved to the state block where we ++ * retrieve it for return to the caller. ++ */ ++ /* XXX assert digest bufs have the same size */ ++ bcopy(ses->ses_hminner, sa->sa_indigest, ++ sizeof(sa->sa_indigest)); ++ bcopy(ses->ses_hmouter, sa->sa_outdigest, ++ sizeof(sa->sa_outdigest)); ++ ++ cmd0 |= SAFE_SA_CMD0_HSLD_SA | SAFE_SA_CMD0_SAVEHASH; ++ re->re_flags |= SAFE_QFLAGS_COPYOUTICV; ++ } ++ ++ if (enccrd && maccrd) { ++ /* ++ * The offset from hash data to the start of ++ * crypt data is the difference in the skips. ++ */ ++ bypass = maccrd->crd_skip; ++ coffset = enccrd->crd_skip - maccrd->crd_skip; ++ if (coffset < 0) { ++ DPRINTF(("%s: hash does not precede crypt; " ++ "mac skip %u enc skip %u\n", ++ __func__, maccrd->crd_skip, enccrd->crd_skip)); ++ safestats.st_skipmismatch++; ++ err = EINVAL; ++ goto errout; ++ } ++ oplen = enccrd->crd_skip + enccrd->crd_len; ++ if (maccrd->crd_skip + maccrd->crd_len != oplen) { ++ DPRINTF(("%s: hash amount %u != crypt amount %u\n", ++ __func__, maccrd->crd_skip + maccrd->crd_len, ++ oplen)); ++ safestats.st_lenmismatch++; ++ err = EINVAL; ++ goto errout; ++ } ++#ifdef SAFE_DEBUG ++ if (debug) { ++ printf("mac: skip %d, len %d, inject %d\n", ++ maccrd->crd_skip, maccrd->crd_len, ++ maccrd->crd_inject); ++ printf("enc: skip %d, len %d, inject %d\n", ++ enccrd->crd_skip, enccrd->crd_len, ++ enccrd->crd_inject); ++ printf("bypass %d coffset %d oplen %d\n", ++ bypass, coffset, oplen); ++ } ++#endif ++ if (coffset & 3) { /* offset must be 32-bit aligned */ ++ DPRINTF(("%s: coffset %u misaligned\n", ++ __func__, coffset)); ++ safestats.st_coffmisaligned++; ++ err = EINVAL; ++ goto errout; ++ } ++ coffset >>= 2; ++ if (coffset > 255) { /* offset must be <256 dwords */ ++ DPRINTF(("%s: coffset %u too big\n", ++ __func__, coffset)); ++ safestats.st_cofftoobig++; ++ err = EINVAL; ++ goto errout; ++ } ++ /* ++ * Tell the hardware to copy the header to the output. ++ * The header is defined as the data from the end of ++ * the bypass to the start of data to be encrypted. ++ * Typically this is the inline IV. Note that you need ++ * to do this even if src+dst are the same; it appears ++ * that w/o this bit the crypted data is written ++ * immediately after the bypass data. ++ */ ++ cmd1 |= SAFE_SA_CMD1_HDRCOPY; ++ /* ++ * Disable IP header mutable bit handling. This is ++ * needed to get correct HMAC calculations. ++ */ ++ cmd1 |= SAFE_SA_CMD1_MUTABLE; ++ } else { ++ if (enccrd) { ++ bypass = enccrd->crd_skip; ++ oplen = bypass + enccrd->crd_len; ++ } else { ++ bypass = maccrd->crd_skip; ++ oplen = bypass + maccrd->crd_len; ++ } ++ coffset = 0; ++ } ++ /* XXX verify multiple of 4 when using s/g */ ++ if (bypass > 96) { /* bypass offset must be <= 96 bytes */ ++ DPRINTF(("%s: bypass %u too big\n", __func__, bypass)); ++ safestats.st_bypasstoobig++; ++ err = EINVAL; ++ goto errout; ++ } ++ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ if (pci_map_skb(sc, &re->re_src, re->re_src_skb)) { ++ safestats.st_noload++; ++ err = ENOMEM; ++ goto errout; ++ } ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ if (pci_map_uio(sc, &re->re_src, re->re_src_io)) { ++ safestats.st_noload++; ++ err = ENOMEM; ++ goto errout; ++ } ++ } ++ nicealign = safe_dmamap_aligned(sc, &re->re_src); ++ uniform = safe_dmamap_uniform(sc, &re->re_src); ++ ++ DPRINTF(("src nicealign %u uniform %u nsegs %u\n", ++ nicealign, uniform, re->re_src.nsegs)); ++ if (re->re_src.nsegs > 1) { ++ re->re_desc.d_src = sc->sc_spalloc.dma_paddr + ++ ((caddr_t) sc->sc_spfree - (caddr_t) sc->sc_spring); ++ for (i = 0; i < re->re_src_nsegs; i++) { ++ /* NB: no need to check if there's space */ ++ pd = sc->sc_spfree; ++ if (++(sc->sc_spfree) == sc->sc_springtop) ++ sc->sc_spfree = sc->sc_spring; ++ ++ KASSERT((pd->pd_flags&3) == 0 || ++ (pd->pd_flags&3) == SAFE_PD_DONE, ++ ("bogus source particle descriptor; flags %x", ++ pd->pd_flags)); ++ pd->pd_addr = re->re_src_segs[i].ds_addr; ++ pd->pd_size = re->re_src_segs[i].ds_len; ++ pd->pd_flags = SAFE_PD_READY; ++ } ++ cmd0 |= SAFE_SA_CMD0_IGATHER; ++ } else { ++ /* ++ * No need for gather, reference the operand directly. ++ */ ++ re->re_desc.d_src = re->re_src_segs[0].ds_addr; ++ } ++ ++ if (enccrd == NULL && maccrd != NULL) { ++ /* ++ * Hash op; no destination needed. ++ */ ++ } else { ++ if (crp->crp_flags & (CRYPTO_F_IOV|CRYPTO_F_SKBUF)) { ++ if (!nicealign) { ++ safestats.st_iovmisaligned++; ++ err = EINVAL; ++ goto errout; ++ } ++ if (uniform != 1) { ++ device_printf(sc->sc_dev, "!uniform source\n"); ++ if (!uniform) { ++ /* ++ * There's no way to handle the DMA ++ * requirements with this uio. We ++ * could create a separate DMA area for ++ * the result and then copy it back, ++ * but for now we just bail and return ++ * an error. Note that uio requests ++ * > SAFE_MAX_DSIZE are handled because ++ * the DMA map and segment list for the ++ * destination wil result in a ++ * destination particle list that does ++ * the necessary scatter DMA. ++ */ ++ safestats.st_iovnotuniform++; ++ err = EINVAL; ++ goto errout; ++ } ++ } else ++ re->re_dst = re->re_src; ++ } else { ++ safestats.st_badflags++; ++ err = EINVAL; ++ goto errout; ++ } ++ ++ if (re->re_dst.nsegs > 1) { ++ re->re_desc.d_dst = sc->sc_dpalloc.dma_paddr + ++ ((caddr_t) sc->sc_dpfree - (caddr_t) sc->sc_dpring); ++ for (i = 0; i < re->re_dst_nsegs; i++) { ++ pd = sc->sc_dpfree; ++ KASSERT((pd->pd_flags&3) == 0 || ++ (pd->pd_flags&3) == SAFE_PD_DONE, ++ ("bogus dest particle descriptor; flags %x", ++ pd->pd_flags)); ++ if (++(sc->sc_dpfree) == sc->sc_dpringtop) ++ sc->sc_dpfree = sc->sc_dpring; ++ pd->pd_addr = re->re_dst_segs[i].ds_addr; ++ pd->pd_flags = SAFE_PD_READY; ++ } ++ cmd0 |= SAFE_SA_CMD0_OSCATTER; ++ } else { ++ /* ++ * No need for scatter, reference the operand directly. ++ */ ++ re->re_desc.d_dst = re->re_dst_segs[0].ds_addr; ++ } ++ } ++ ++ /* ++ * All done with setup; fillin the SA command words ++ * and the packet engine descriptor. The operation ++ * is now ready for submission to the hardware. ++ */ ++ sa->sa_cmd0 = cmd0 | SAFE_SA_CMD0_IPCI | SAFE_SA_CMD0_OPCI; ++ sa->sa_cmd1 = cmd1 ++ | (coffset << SAFE_SA_CMD1_OFFSET_S) ++ | SAFE_SA_CMD1_SAREV1 /* Rev 1 SA data structure */ ++ | SAFE_SA_CMD1_SRPCI ++ ; ++ /* ++ * NB: the order of writes is important here. In case the ++ * chip is scanning the ring because of an outstanding request ++ * it might nab this one too. In that case we need to make ++ * sure the setup is complete before we write the length ++ * field of the descriptor as it signals the descriptor is ++ * ready for processing. ++ */ ++ re->re_desc.d_csr = SAFE_PE_CSR_READY | SAFE_PE_CSR_SAPCI; ++ if (maccrd) ++ re->re_desc.d_csr |= SAFE_PE_CSR_LOADSA | SAFE_PE_CSR_HASHFINAL; ++ wmb(); ++ re->re_desc.d_len = oplen ++ | SAFE_PE_LEN_READY ++ | (bypass << SAFE_PE_LEN_BYPASS_S) ++ ; ++ ++ safestats.st_ipackets++; ++ safestats.st_ibytes += oplen; ++ ++ if (++(sc->sc_front) == sc->sc_ringtop) ++ sc->sc_front = sc->sc_ring; ++ ++ /* XXX honor batching */ ++ safe_feed(sc, re); ++ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); ++ return (0); ++ ++errout: ++ if (re->re_src.map != re->re_dst.map) ++ pci_unmap_operand(sc, &re->re_dst); ++ if (re->re_src.map) ++ pci_unmap_operand(sc, &re->re_src); ++ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); ++ if (err != ERESTART) { ++ crp->crp_etype = err; ++ crypto_done(crp); ++ } else { ++ sc->sc_needwakeup |= CRYPTO_SYMQ; ++ } ++ return (err); ++} ++ ++static void ++safe_callback(struct safe_softc *sc, struct safe_ringentry *re) ++{ ++ struct cryptop *crp = (struct cryptop *)re->re_crp; ++ struct cryptodesc *crd; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ safestats.st_opackets++; ++ safestats.st_obytes += re->re_dst.mapsize; ++ ++ if (re->re_desc.d_csr & SAFE_PE_CSR_STATUS) { ++ device_printf(sc->sc_dev, "csr 0x%x cmd0 0x%x cmd1 0x%x\n", ++ re->re_desc.d_csr, ++ re->re_sa.sa_cmd0, re->re_sa.sa_cmd1); ++ safestats.st_peoperr++; ++ crp->crp_etype = EIO; /* something more meaningful? */ ++ } ++ ++ if (re->re_dst.map != NULL && re->re_dst.map != re->re_src.map) ++ pci_unmap_operand(sc, &re->re_dst); ++ pci_unmap_operand(sc, &re->re_src); ++ ++ /* ++ * If result was written to a differet mbuf chain, swap ++ * it in as the return value and reclaim the original. ++ */ ++ if ((crp->crp_flags & CRYPTO_F_SKBUF) && re->re_src_skb != re->re_dst_skb) { ++ device_printf(sc->sc_dev, "no CRYPTO_F_SKBUF swapping support\n"); ++ /* kfree_skb(skb) */ ++ /* crp->crp_buf = (caddr_t)re->re_dst_skb */ ++ return; ++ } ++ ++ if (re->re_flags & SAFE_QFLAGS_COPYOUTICV) { ++ /* copy out ICV result */ ++ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { ++ if (!(crd->crd_alg == CRYPTO_MD5_HMAC || ++ crd->crd_alg == CRYPTO_SHA1_HMAC || ++ crd->crd_alg == CRYPTO_NULL_HMAC)) ++ continue; ++ if (crd->crd_alg == CRYPTO_SHA1_HMAC) { ++ /* ++ * SHA-1 ICV's are byte-swapped; fix 'em up ++ * before copy them to their destination. ++ */ ++ re->re_sastate.sa_saved_indigest[0] = ++ cpu_to_be32(re->re_sastate.sa_saved_indigest[0]); ++ re->re_sastate.sa_saved_indigest[1] = ++ cpu_to_be32(re->re_sastate.sa_saved_indigest[1]); ++ re->re_sastate.sa_saved_indigest[2] = ++ cpu_to_be32(re->re_sastate.sa_saved_indigest[2]); ++ } else { ++ re->re_sastate.sa_saved_indigest[0] = ++ cpu_to_le32(re->re_sastate.sa_saved_indigest[0]); ++ re->re_sastate.sa_saved_indigest[1] = ++ cpu_to_le32(re->re_sastate.sa_saved_indigest[1]); ++ re->re_sastate.sa_saved_indigest[2] = ++ cpu_to_le32(re->re_sastate.sa_saved_indigest[2]); ++ } ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ crd->crd_inject, ++ sc->sc_sessions[re->re_sesn].ses_mlen, ++ (caddr_t)re->re_sastate.sa_saved_indigest); ++ break; ++ } ++ } ++ crypto_done(crp); ++} ++ ++ ++#if defined(CONFIG_OCF_RANDOMHARVEST) && !defined(SAFE_NO_RNG) ++#define SAFE_RNG_MAXWAIT 1000 ++ ++static void ++safe_rng_init(struct safe_softc *sc) ++{ ++ u_int32_t w, v; ++ int i; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ WRITE_REG(sc, SAFE_RNG_CTRL, 0); ++ /* use default value according to the manual */ ++ WRITE_REG(sc, SAFE_RNG_CNFG, 0x834); /* magic from SafeNet */ ++ WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); ++ ++ /* ++ * There is a bug in rev 1.0 of the 1140 that when the RNG ++ * is brought out of reset the ready status flag does not ++ * work until the RNG has finished its internal initialization. ++ * ++ * So in order to determine the device is through its ++ * initialization we must read the data register, using the ++ * status reg in the read in case it is initialized. Then read ++ * the data register until it changes from the first read. ++ * Once it changes read the data register until it changes ++ * again. At this time the RNG is considered initialized. ++ * This could take between 750ms - 1000ms in time. ++ */ ++ i = 0; ++ w = READ_REG(sc, SAFE_RNG_OUT); ++ do { ++ v = READ_REG(sc, SAFE_RNG_OUT); ++ if (v != w) { ++ w = v; ++ break; ++ } ++ DELAY(10); ++ } while (++i < SAFE_RNG_MAXWAIT); ++ ++ /* Wait Until data changes again */ ++ i = 0; ++ do { ++ v = READ_REG(sc, SAFE_RNG_OUT); ++ if (v != w) ++ break; ++ DELAY(10); ++ } while (++i < SAFE_RNG_MAXWAIT); ++} ++ ++static __inline void ++safe_rng_disable_short_cycle(struct safe_softc *sc) ++{ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ WRITE_REG(sc, SAFE_RNG_CTRL, ++ READ_REG(sc, SAFE_RNG_CTRL) &~ SAFE_RNG_CTRL_SHORTEN); ++} ++ ++static __inline void ++safe_rng_enable_short_cycle(struct safe_softc *sc) ++{ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ WRITE_REG(sc, SAFE_RNG_CTRL, ++ READ_REG(sc, SAFE_RNG_CTRL) | SAFE_RNG_CTRL_SHORTEN); ++} ++ ++static __inline u_int32_t ++safe_rng_read(struct safe_softc *sc) ++{ ++ int i; ++ ++ i = 0; ++ while (READ_REG(sc, SAFE_RNG_STAT) != 0 && ++i < SAFE_RNG_MAXWAIT) ++ ; ++ return READ_REG(sc, SAFE_RNG_OUT); ++} ++ ++static int ++safe_read_random(void *arg, u_int32_t *buf, int maxwords) ++{ ++ struct safe_softc *sc = (struct safe_softc *) arg; ++ int i, rc; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ safestats.st_rng++; ++ /* ++ * Fetch the next block of data. ++ */ ++ if (maxwords > safe_rngbufsize) ++ maxwords = safe_rngbufsize; ++ if (maxwords > SAFE_RNG_MAXBUFSIZ) ++ maxwords = SAFE_RNG_MAXBUFSIZ; ++retry: ++ /* read as much as we can */ ++ for (rc = 0; rc < maxwords; rc++) { ++ if (READ_REG(sc, SAFE_RNG_STAT) != 0) ++ break; ++ buf[rc] = READ_REG(sc, SAFE_RNG_OUT); ++ } ++ if (rc == 0) ++ return 0; ++ /* ++ * Check the comparator alarm count and reset the h/w if ++ * it exceeds our threshold. This guards against the ++ * hardware oscillators resonating with external signals. ++ */ ++ if (READ_REG(sc, SAFE_RNG_ALM_CNT) > safe_rngmaxalarm) { ++ u_int32_t freq_inc, w; ++ ++ DPRINTF(("%s: alarm count %u exceeds threshold %u\n", __func__, ++ (unsigned)READ_REG(sc, SAFE_RNG_ALM_CNT), safe_rngmaxalarm)); ++ safestats.st_rngalarm++; ++ safe_rng_enable_short_cycle(sc); ++ freq_inc = 18; ++ for (i = 0; i < 64; i++) { ++ w = READ_REG(sc, SAFE_RNG_CNFG); ++ freq_inc = ((w + freq_inc) & 0x3fL); ++ w = ((w & ~0x3fL) | freq_inc); ++ WRITE_REG(sc, SAFE_RNG_CNFG, w); ++ ++ WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); ++ ++ (void) safe_rng_read(sc); ++ DELAY(25); ++ ++ if (READ_REG(sc, SAFE_RNG_ALM_CNT) == 0) { ++ safe_rng_disable_short_cycle(sc); ++ goto retry; ++ } ++ freq_inc = 1; ++ } ++ safe_rng_disable_short_cycle(sc); ++ } else ++ WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0); ++ ++ return(rc); ++} ++#endif /* defined(CONFIG_OCF_RANDOMHARVEST) && !defined(SAFE_NO_RNG) */ ++ ++ ++/* ++ * Resets the board. Values in the regesters are left as is ++ * from the reset (i.e. initial values are assigned elsewhere). ++ */ ++static void ++safe_reset_board(struct safe_softc *sc) ++{ ++ u_int32_t v; ++ /* ++ * Reset the device. The manual says no delay ++ * is needed between marking and clearing reset. ++ */ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ v = READ_REG(sc, SAFE_PE_DMACFG) &~ ++ (SAFE_PE_DMACFG_PERESET | SAFE_PE_DMACFG_PDRRESET | ++ SAFE_PE_DMACFG_SGRESET); ++ WRITE_REG(sc, SAFE_PE_DMACFG, v ++ | SAFE_PE_DMACFG_PERESET ++ | SAFE_PE_DMACFG_PDRRESET ++ | SAFE_PE_DMACFG_SGRESET); ++ WRITE_REG(sc, SAFE_PE_DMACFG, v); ++} ++ ++/* ++ * Initialize registers we need to touch only once. ++ */ ++static void ++safe_init_board(struct safe_softc *sc) ++{ ++ u_int32_t v, dwords; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ v = READ_REG(sc, SAFE_PE_DMACFG); ++ v &=~ ( SAFE_PE_DMACFG_PEMODE ++ | SAFE_PE_DMACFG_FSENA /* failsafe enable */ ++ | SAFE_PE_DMACFG_GPRPCI /* gather ring on PCI */ ++ | SAFE_PE_DMACFG_SPRPCI /* scatter ring on PCI */ ++ | SAFE_PE_DMACFG_ESDESC /* endian-swap descriptors */ ++ | SAFE_PE_DMACFG_ESPDESC /* endian-swap part. desc's */ ++ | SAFE_PE_DMACFG_ESSA /* endian-swap SA's */ ++ | SAFE_PE_DMACFG_ESPACKET /* swap the packet data */ ++ ); ++ v |= SAFE_PE_DMACFG_FSENA /* failsafe enable */ ++ | SAFE_PE_DMACFG_GPRPCI /* gather ring on PCI */ ++ | SAFE_PE_DMACFG_SPRPCI /* scatter ring on PCI */ ++ | SAFE_PE_DMACFG_ESDESC /* endian-swap descriptors */ ++ | SAFE_PE_DMACFG_ESPDESC /* endian-swap part. desc's */ ++ | SAFE_PE_DMACFG_ESSA /* endian-swap SA's */ ++#if 0 ++ | SAFE_PE_DMACFG_ESPACKET /* swap the packet data */ ++#endif ++ ; ++ WRITE_REG(sc, SAFE_PE_DMACFG, v); ++ ++#ifdef __BIG_ENDIAN ++ /* tell the safenet that we are 4321 and not 1234 */ ++ WRITE_REG(sc, SAFE_ENDIAN, 0xe4e41b1b); ++#endif ++ ++ if (sc->sc_chiprev == SAFE_REV(1,0)) { ++ /* ++ * Avoid large PCI DMA transfers. Rev 1.0 has a bug where ++ * "target mode transfers" done while the chip is DMA'ing ++ * >1020 bytes cause the hardware to lockup. To avoid this ++ * we reduce the max PCI transfer size and use small source ++ * particle descriptors (<= 256 bytes). ++ */ ++ WRITE_REG(sc, SAFE_DMA_CFG, 256); ++ device_printf(sc->sc_dev, ++ "Reduce max DMA size to %u words for rev %u.%u WAR\n", ++ (unsigned) ((READ_REG(sc, SAFE_DMA_CFG)>>2) & 0xff), ++ (unsigned) SAFE_REV_MAJ(sc->sc_chiprev), ++ (unsigned) SAFE_REV_MIN(sc->sc_chiprev)); ++ sc->sc_max_dsize = 256; ++ } else { ++ sc->sc_max_dsize = SAFE_MAX_DSIZE; ++ } ++ ++ /* NB: operands+results are overlaid */ ++ WRITE_REG(sc, SAFE_PE_PDRBASE, sc->sc_ringalloc.dma_paddr); ++ WRITE_REG(sc, SAFE_PE_RDRBASE, sc->sc_ringalloc.dma_paddr); ++ /* ++ * Configure ring entry size and number of items in the ring. ++ */ ++ KASSERT((sizeof(struct safe_ringentry) % sizeof(u_int32_t)) == 0, ++ ("PE ring entry not 32-bit aligned!")); ++ dwords = sizeof(struct safe_ringentry) / sizeof(u_int32_t); ++ WRITE_REG(sc, SAFE_PE_RINGCFG, ++ (dwords << SAFE_PE_RINGCFG_OFFSET_S) | SAFE_MAX_NQUEUE); ++ WRITE_REG(sc, SAFE_PE_RINGPOLL, 0); /* disable polling */ ++ ++ WRITE_REG(sc, SAFE_PE_GRNGBASE, sc->sc_spalloc.dma_paddr); ++ WRITE_REG(sc, SAFE_PE_SRNGBASE, sc->sc_dpalloc.dma_paddr); ++ WRITE_REG(sc, SAFE_PE_PARTSIZE, ++ (SAFE_TOTAL_DPART<<16) | SAFE_TOTAL_SPART); ++ /* ++ * NB: destination particles are fixed size. We use ++ * an mbuf cluster and require all results go to ++ * clusters or smaller. ++ */ ++ WRITE_REG(sc, SAFE_PE_PARTCFG, sc->sc_max_dsize); ++ ++ /* it's now safe to enable PE mode, do it */ ++ WRITE_REG(sc, SAFE_PE_DMACFG, v | SAFE_PE_DMACFG_PEMODE); ++ ++ /* ++ * Configure hardware to use level-triggered interrupts and ++ * to interrupt after each descriptor is processed. ++ */ ++ WRITE_REG(sc, SAFE_HI_CFG, SAFE_HI_CFG_LEVEL); ++ WRITE_REG(sc, SAFE_HI_CLR, 0xffffffff); ++ WRITE_REG(sc, SAFE_HI_DESC_CNT, 1); ++ WRITE_REG(sc, SAFE_HI_MASK, SAFE_INT_PE_DDONE | SAFE_INT_PE_ERROR); ++} ++ ++ ++/* ++ * Clean up after a chip crash. ++ * It is assumed that the caller in splimp() ++ */ ++static void ++safe_cleanchip(struct safe_softc *sc) ++{ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ if (sc->sc_nqchip != 0) { ++ struct safe_ringentry *re = sc->sc_back; ++ ++ while (re != sc->sc_front) { ++ if (re->re_desc.d_csr != 0) ++ safe_free_entry(sc, re); ++ if (++re == sc->sc_ringtop) ++ re = sc->sc_ring; ++ } ++ sc->sc_back = re; ++ sc->sc_nqchip = 0; ++ } ++} ++ ++/* ++ * free a safe_q ++ * It is assumed that the caller is within splimp(). ++ */ ++static int ++safe_free_entry(struct safe_softc *sc, struct safe_ringentry *re) ++{ ++ struct cryptop *crp; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ /* ++ * Free header MCR ++ */ ++ if ((re->re_dst_skb != NULL) && (re->re_src_skb != re->re_dst_skb)) ++#ifdef NOTYET ++ m_freem(re->re_dst_m); ++#else ++ printk("%s,%d: SKB not supported\n", __FILE__, __LINE__); ++#endif ++ ++ crp = (struct cryptop *)re->re_crp; ++ ++ re->re_desc.d_csr = 0; ++ ++ crp->crp_etype = EFAULT; ++ crypto_done(crp); ++ return(0); ++} ++ ++/* ++ * Routine to reset the chip and clean up. ++ * It is assumed that the caller is in splimp() ++ */ ++static void ++safe_totalreset(struct safe_softc *sc) ++{ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ safe_reset_board(sc); ++ safe_init_board(sc); ++ safe_cleanchip(sc); ++} ++ ++/* ++ * Is the operand suitable aligned for direct DMA. Each ++ * segment must be aligned on a 32-bit boundary and all ++ * but the last segment must be a multiple of 4 bytes. ++ */ ++static int ++safe_dmamap_aligned(struct safe_softc *sc, const struct safe_operand *op) ++{ ++ int i; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ for (i = 0; i < op->nsegs; i++) { ++ if (op->segs[i].ds_addr & 3) ++ return (0); ++ if (i != (op->nsegs - 1) && (op->segs[i].ds_len & 3)) ++ return (0); ++ } ++ return (1); ++} ++ ++/* ++ * Is the operand suitable for direct DMA as the destination ++ * of an operation. The hardware requires that each ``particle'' ++ * but the last in an operation result have the same size. We ++ * fix that size at SAFE_MAX_DSIZE bytes. This routine returns ++ * 0 if some segment is not a multiple of of this size, 1 if all ++ * segments are exactly this size, or 2 if segments are at worst ++ * a multple of this size. ++ */ ++static int ++safe_dmamap_uniform(struct safe_softc *sc, const struct safe_operand *op) ++{ ++ int result = 1; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ if (op->nsegs > 0) { ++ int i; ++ ++ for (i = 0; i < op->nsegs-1; i++) { ++ if (op->segs[i].ds_len % sc->sc_max_dsize) ++ return (0); ++ if (op->segs[i].ds_len != sc->sc_max_dsize) ++ result = 2; ++ } ++ } ++ return (result); ++} ++ ++static int ++safe_kprocess(device_t dev, struct cryptkop *krp, int hint) ++{ ++ struct safe_softc *sc = device_get_softc(dev); ++ struct safe_pkq *q; ++ unsigned long flags; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ if (sc == NULL) { ++ krp->krp_status = EINVAL; ++ goto err; ++ } ++ ++ if (krp->krp_op != CRK_MOD_EXP) { ++ krp->krp_status = EOPNOTSUPP; ++ goto err; ++ } ++ ++ q = (struct safe_pkq *) kmalloc(sizeof(*q), GFP_KERNEL); ++ if (q == NULL) { ++ krp->krp_status = ENOMEM; ++ goto err; ++ } ++ memset(q, 0, sizeof(*q)); ++ q->pkq_krp = krp; ++ INIT_LIST_HEAD(&q->pkq_list); ++ ++ spin_lock_irqsave(&sc->sc_pkmtx, flags); ++ list_add_tail(&q->pkq_list, &sc->sc_pkq); ++ safe_kfeed(sc); ++ spin_unlock_irqrestore(&sc->sc_pkmtx, flags); ++ return (0); ++ ++err: ++ crypto_kdone(krp); ++ return (0); ++} ++ ++#define SAFE_CRK_PARAM_BASE 0 ++#define SAFE_CRK_PARAM_EXP 1 ++#define SAFE_CRK_PARAM_MOD 2 ++ ++static int ++safe_kstart(struct safe_softc *sc) ++{ ++ struct cryptkop *krp = sc->sc_pkq_cur->pkq_krp; ++ int exp_bits, mod_bits, base_bits; ++ u_int32_t op, a_off, b_off, c_off, d_off; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ if (krp->krp_iparams < 3 || krp->krp_oparams != 1) { ++ krp->krp_status = EINVAL; ++ return (1); ++ } ++ ++ base_bits = safe_ksigbits(sc, &krp->krp_param[SAFE_CRK_PARAM_BASE]); ++ if (base_bits > 2048) ++ goto too_big; ++ if (base_bits <= 0) /* 5. base not zero */ ++ goto too_small; ++ ++ exp_bits = safe_ksigbits(sc, &krp->krp_param[SAFE_CRK_PARAM_EXP]); ++ if (exp_bits > 2048) ++ goto too_big; ++ if (exp_bits <= 0) /* 1. exponent word length > 0 */ ++ goto too_small; /* 4. exponent not zero */ ++ ++ mod_bits = safe_ksigbits(sc, &krp->krp_param[SAFE_CRK_PARAM_MOD]); ++ if (mod_bits > 2048) ++ goto too_big; ++ if (mod_bits <= 32) /* 2. modulus word length > 1 */ ++ goto too_small; /* 8. MSW of modulus != zero */ ++ if (mod_bits < exp_bits) /* 3 modulus len >= exponent len */ ++ goto too_small; ++ if ((krp->krp_param[SAFE_CRK_PARAM_MOD].crp_p[0] & 1) == 0) ++ goto bad_domain; /* 6. modulus is odd */ ++ if (mod_bits > krp->krp_param[krp->krp_iparams].crp_nbits) ++ goto too_small; /* make sure result will fit */ ++ ++ /* 7. modulus > base */ ++ if (mod_bits < base_bits) ++ goto too_small; ++ if (mod_bits == base_bits) { ++ u_int8_t *basep, *modp; ++ int i; ++ ++ basep = krp->krp_param[SAFE_CRK_PARAM_BASE].crp_p + ++ ((base_bits + 7) / 8) - 1; ++ modp = krp->krp_param[SAFE_CRK_PARAM_MOD].crp_p + ++ ((mod_bits + 7) / 8) - 1; ++ ++ for (i = 0; i < (mod_bits + 7) / 8; i++, basep--, modp--) { ++ if (*modp < *basep) ++ goto too_small; ++ if (*modp > *basep) ++ break; ++ } ++ } ++ ++ /* And on the 9th step, he rested. */ ++ ++ WRITE_REG(sc, SAFE_PK_A_LEN, (exp_bits + 31) / 32); ++ WRITE_REG(sc, SAFE_PK_B_LEN, (mod_bits + 31) / 32); ++ if (mod_bits > 1024) { ++ op = SAFE_PK_FUNC_EXP4; ++ a_off = 0x000; ++ b_off = 0x100; ++ c_off = 0x200; ++ d_off = 0x300; ++ } else { ++ op = SAFE_PK_FUNC_EXP16; ++ a_off = 0x000; ++ b_off = 0x080; ++ c_off = 0x100; ++ d_off = 0x180; ++ } ++ sc->sc_pk_reslen = b_off - a_off; ++ sc->sc_pk_resoff = d_off; ++ ++ /* A is exponent, B is modulus, C is base, D is result */ ++ safe_kload_reg(sc, a_off, b_off - a_off, ++ &krp->krp_param[SAFE_CRK_PARAM_EXP]); ++ WRITE_REG(sc, SAFE_PK_A_ADDR, a_off >> 2); ++ safe_kload_reg(sc, b_off, b_off - a_off, ++ &krp->krp_param[SAFE_CRK_PARAM_MOD]); ++ WRITE_REG(sc, SAFE_PK_B_ADDR, b_off >> 2); ++ safe_kload_reg(sc, c_off, b_off - a_off, ++ &krp->krp_param[SAFE_CRK_PARAM_BASE]); ++ WRITE_REG(sc, SAFE_PK_C_ADDR, c_off >> 2); ++ WRITE_REG(sc, SAFE_PK_D_ADDR, d_off >> 2); ++ ++ WRITE_REG(sc, SAFE_PK_FUNC, op | SAFE_PK_FUNC_RUN); ++ ++ return (0); ++ ++too_big: ++ krp->krp_status = E2BIG; ++ return (1); ++too_small: ++ krp->krp_status = ERANGE; ++ return (1); ++bad_domain: ++ krp->krp_status = EDOM; ++ return (1); ++} ++ ++static int ++safe_ksigbits(struct safe_softc *sc, struct crparam *cr) ++{ ++ u_int plen = (cr->crp_nbits + 7) / 8; ++ int i, sig = plen * 8; ++ u_int8_t c, *p = cr->crp_p; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ for (i = plen - 1; i >= 0; i--) { ++ c = p[i]; ++ if (c != 0) { ++ while ((c & 0x80) == 0) { ++ sig--; ++ c <<= 1; ++ } ++ break; ++ } ++ sig -= 8; ++ } ++ return (sig); ++} ++ ++static void ++safe_kfeed(struct safe_softc *sc) ++{ ++ struct safe_pkq *q, *tmp; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ if (list_empty(&sc->sc_pkq) && sc->sc_pkq_cur == NULL) ++ return; ++ if (sc->sc_pkq_cur != NULL) ++ return; ++ list_for_each_entry_safe(q, tmp, &sc->sc_pkq, pkq_list) { ++ sc->sc_pkq_cur = q; ++ list_del(&q->pkq_list); ++ if (safe_kstart(sc) != 0) { ++ crypto_kdone(q->pkq_krp); ++ kfree(q); ++ sc->sc_pkq_cur = NULL; ++ } else { ++ /* op started, start polling */ ++ mod_timer(&sc->sc_pkto, jiffies + 1); ++ break; ++ } ++ } ++} ++ ++static void ++safe_kpoll(unsigned long arg) ++{ ++ struct safe_softc *sc = NULL; ++ struct safe_pkq *q; ++ struct crparam *res; ++ int i; ++ u_int32_t buf[64]; ++ unsigned long flags; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ if (arg >= SAFE_MAX_CHIPS) ++ return; ++ sc = safe_chip_idx[arg]; ++ if (!sc) { ++ DPRINTF(("%s() - bad callback\n", __FUNCTION__)); ++ return; ++ } ++ ++ spin_lock_irqsave(&sc->sc_pkmtx, flags); ++ if (sc->sc_pkq_cur == NULL) ++ goto out; ++ if (READ_REG(sc, SAFE_PK_FUNC) & SAFE_PK_FUNC_RUN) { ++ /* still running, check back later */ ++ mod_timer(&sc->sc_pkto, jiffies + 1); ++ goto out; ++ } ++ ++ q = sc->sc_pkq_cur; ++ res = &q->pkq_krp->krp_param[q->pkq_krp->krp_iparams]; ++ bzero(buf, sizeof(buf)); ++ bzero(res->crp_p, (res->crp_nbits + 7) / 8); ++ for (i = 0; i < sc->sc_pk_reslen >> 2; i++) ++ buf[i] = le32_to_cpu(READ_REG(sc, SAFE_PK_RAM_START + ++ sc->sc_pk_resoff + (i << 2))); ++ bcopy(buf, res->crp_p, (res->crp_nbits + 7) / 8); ++ /* ++ * reduce the bits that need copying if possible ++ */ ++ res->crp_nbits = min(res->crp_nbits,sc->sc_pk_reslen * 8); ++ res->crp_nbits = safe_ksigbits(sc, res); ++ ++ for (i = SAFE_PK_RAM_START; i < SAFE_PK_RAM_END; i += 4) ++ WRITE_REG(sc, i, 0); ++ ++ crypto_kdone(q->pkq_krp); ++ kfree(q); ++ sc->sc_pkq_cur = NULL; ++ ++ safe_kfeed(sc); ++out: ++ spin_unlock_irqrestore(&sc->sc_pkmtx, flags); ++} ++ ++static void ++safe_kload_reg(struct safe_softc *sc, u_int32_t off, u_int32_t len, ++ struct crparam *n) ++{ ++ u_int32_t buf[64], i; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ bzero(buf, sizeof(buf)); ++ bcopy(n->crp_p, buf, (n->crp_nbits + 7) / 8); ++ ++ for (i = 0; i < len >> 2; i++) ++ WRITE_REG(sc, SAFE_PK_RAM_START + off + (i << 2), ++ cpu_to_le32(buf[i])); ++} ++ ++#ifdef SAFE_DEBUG ++static void ++safe_dump_dmastatus(struct safe_softc *sc, const char *tag) ++{ ++ printf("%s: ENDIAN 0x%x SRC 0x%x DST 0x%x STAT 0x%x\n" ++ , tag ++ , READ_REG(sc, SAFE_DMA_ENDIAN) ++ , READ_REG(sc, SAFE_DMA_SRCADDR) ++ , READ_REG(sc, SAFE_DMA_DSTADDR) ++ , READ_REG(sc, SAFE_DMA_STAT) ++ ); ++} ++ ++static void ++safe_dump_intrstate(struct safe_softc *sc, const char *tag) ++{ ++ printf("%s: HI_CFG 0x%x HI_MASK 0x%x HI_DESC_CNT 0x%x HU_STAT 0x%x HM_STAT 0x%x\n" ++ , tag ++ , READ_REG(sc, SAFE_HI_CFG) ++ , READ_REG(sc, SAFE_HI_MASK) ++ , READ_REG(sc, SAFE_HI_DESC_CNT) ++ , READ_REG(sc, SAFE_HU_STAT) ++ , READ_REG(sc, SAFE_HM_STAT) ++ ); ++} ++ ++static void ++safe_dump_ringstate(struct safe_softc *sc, const char *tag) ++{ ++ u_int32_t estat = READ_REG(sc, SAFE_PE_ERNGSTAT); ++ ++ /* NB: assume caller has lock on ring */ ++ printf("%s: ERNGSTAT %x (next %u) back %lu front %lu\n", ++ tag, ++ estat, (estat >> SAFE_PE_ERNGSTAT_NEXT_S), ++ (unsigned long)(sc->sc_back - sc->sc_ring), ++ (unsigned long)(sc->sc_front - sc->sc_ring)); ++} ++ ++static void ++safe_dump_request(struct safe_softc *sc, const char* tag, struct safe_ringentry *re) ++{ ++ int ix, nsegs; ++ ++ ix = re - sc->sc_ring; ++ printf("%s: %p (%u): csr %x src %x dst %x sa %x len %x\n" ++ , tag ++ , re, ix ++ , re->re_desc.d_csr ++ , re->re_desc.d_src ++ , re->re_desc.d_dst ++ , re->re_desc.d_sa ++ , re->re_desc.d_len ++ ); ++ if (re->re_src.nsegs > 1) { ++ ix = (re->re_desc.d_src - sc->sc_spalloc.dma_paddr) / ++ sizeof(struct safe_pdesc); ++ for (nsegs = re->re_src.nsegs; nsegs; nsegs--) { ++ printf(" spd[%u] %p: %p size %u flags %x" ++ , ix, &sc->sc_spring[ix] ++ , (caddr_t)(uintptr_t) sc->sc_spring[ix].pd_addr ++ , sc->sc_spring[ix].pd_size ++ , sc->sc_spring[ix].pd_flags ++ ); ++ if (sc->sc_spring[ix].pd_size == 0) ++ printf(" (zero!)"); ++ printf("\n"); ++ if (++ix == SAFE_TOTAL_SPART) ++ ix = 0; ++ } ++ } ++ if (re->re_dst.nsegs > 1) { ++ ix = (re->re_desc.d_dst - sc->sc_dpalloc.dma_paddr) / ++ sizeof(struct safe_pdesc); ++ for (nsegs = re->re_dst.nsegs; nsegs; nsegs--) { ++ printf(" dpd[%u] %p: %p flags %x\n" ++ , ix, &sc->sc_dpring[ix] ++ , (caddr_t)(uintptr_t) sc->sc_dpring[ix].pd_addr ++ , sc->sc_dpring[ix].pd_flags ++ ); ++ if (++ix == SAFE_TOTAL_DPART) ++ ix = 0; ++ } ++ } ++ printf("sa: cmd0 %08x cmd1 %08x staterec %x\n", ++ re->re_sa.sa_cmd0, re->re_sa.sa_cmd1, re->re_sa.sa_staterec); ++ printf("sa: key %x %x %x %x %x %x %x %x\n" ++ , re->re_sa.sa_key[0] ++ , re->re_sa.sa_key[1] ++ , re->re_sa.sa_key[2] ++ , re->re_sa.sa_key[3] ++ , re->re_sa.sa_key[4] ++ , re->re_sa.sa_key[5] ++ , re->re_sa.sa_key[6] ++ , re->re_sa.sa_key[7] ++ ); ++ printf("sa: indigest %x %x %x %x %x\n" ++ , re->re_sa.sa_indigest[0] ++ , re->re_sa.sa_indigest[1] ++ , re->re_sa.sa_indigest[2] ++ , re->re_sa.sa_indigest[3] ++ , re->re_sa.sa_indigest[4] ++ ); ++ printf("sa: outdigest %x %x %x %x %x\n" ++ , re->re_sa.sa_outdigest[0] ++ , re->re_sa.sa_outdigest[1] ++ , re->re_sa.sa_outdigest[2] ++ , re->re_sa.sa_outdigest[3] ++ , re->re_sa.sa_outdigest[4] ++ ); ++ printf("sr: iv %x %x %x %x\n" ++ , re->re_sastate.sa_saved_iv[0] ++ , re->re_sastate.sa_saved_iv[1] ++ , re->re_sastate.sa_saved_iv[2] ++ , re->re_sastate.sa_saved_iv[3] ++ ); ++ printf("sr: hashbc %u indigest %x %x %x %x %x\n" ++ , re->re_sastate.sa_saved_hashbc ++ , re->re_sastate.sa_saved_indigest[0] ++ , re->re_sastate.sa_saved_indigest[1] ++ , re->re_sastate.sa_saved_indigest[2] ++ , re->re_sastate.sa_saved_indigest[3] ++ , re->re_sastate.sa_saved_indigest[4] ++ ); ++} ++ ++static void ++safe_dump_ring(struct safe_softc *sc, const char *tag) ++{ ++ unsigned long flags; ++ ++ spin_lock_irqsave(&sc->sc_ringmtx, flags); ++ printf("\nSafeNet Ring State:\n"); ++ safe_dump_intrstate(sc, tag); ++ safe_dump_dmastatus(sc, tag); ++ safe_dump_ringstate(sc, tag); ++ if (sc->sc_nqchip) { ++ struct safe_ringentry *re = sc->sc_back; ++ do { ++ safe_dump_request(sc, tag, re); ++ if (++re == sc->sc_ringtop) ++ re = sc->sc_ring; ++ } while (re != sc->sc_front); ++ } ++ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); ++} ++#endif /* SAFE_DEBUG */ ++ ++ ++static int safe_probe(struct pci_dev *dev, const struct pci_device_id *ent) ++{ ++ struct safe_softc *sc = NULL; ++ u32 mem_start, mem_len, cmd; ++ int i, rc, devinfo; ++ dma_addr_t raddr; ++ static int num_chips = 0; ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ if (pci_enable_device(dev) < 0) ++ return(-ENODEV); ++ ++ if (!dev->irq) { ++ printk("safe: found device with no IRQ assigned. check BIOS settings!"); ++ pci_disable_device(dev); ++ return(-ENODEV); ++ } ++ ++ if (pci_set_mwi(dev)) { ++ printk("safe: pci_set_mwi failed!"); ++ return(-ENODEV); ++ } ++ ++ sc = (struct safe_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); ++ if (!sc) ++ return(-ENOMEM); ++ memset(sc, 0, sizeof(*sc)); ++ ++ softc_device_init(sc, "safe", num_chips, safe_methods); ++ ++ sc->sc_irq = -1; ++ sc->sc_cid = -1; ++ sc->sc_pcidev = dev; ++ if (num_chips < SAFE_MAX_CHIPS) { ++ safe_chip_idx[device_get_unit(sc->sc_dev)] = sc; ++ num_chips++; ++ } ++ ++ INIT_LIST_HEAD(&sc->sc_pkq); ++ spin_lock_init(&sc->sc_pkmtx); ++ ++ pci_set_drvdata(sc->sc_pcidev, sc); ++ ++ /* we read its hardware registers as memory */ ++ mem_start = pci_resource_start(sc->sc_pcidev, 0); ++ mem_len = pci_resource_len(sc->sc_pcidev, 0); ++ ++ sc->sc_base_addr = (ocf_iomem_t) ioremap(mem_start, mem_len); ++ if (!sc->sc_base_addr) { ++ device_printf(sc->sc_dev, "failed to ioremap 0x%x-0x%x\n", ++ mem_start, mem_start + mem_len - 1); ++ goto out; ++ } ++ ++ /* fix up the bus size */ ++ if (pci_set_dma_mask(sc->sc_pcidev, DMA_32BIT_MASK)) { ++ device_printf(sc->sc_dev, "No usable DMA configuration, aborting.\n"); ++ goto out; ++ } ++ if (pci_set_consistent_dma_mask(sc->sc_pcidev, DMA_32BIT_MASK)) { ++ device_printf(sc->sc_dev, "No usable consistent DMA configuration, aborting.\n"); ++ goto out; ++ } ++ ++ pci_set_master(sc->sc_pcidev); ++ ++ pci_read_config_dword(sc->sc_pcidev, PCI_COMMAND, &cmd); ++ ++ if (!(cmd & PCI_COMMAND_MEMORY)) { ++ device_printf(sc->sc_dev, "failed to enable memory mapping\n"); ++ goto out; ++ } ++ ++ if (!(cmd & PCI_COMMAND_MASTER)) { ++ device_printf(sc->sc_dev, "failed to enable bus mastering\n"); ++ goto out; ++ } ++ ++ rc = request_irq(dev->irq, safe_intr, IRQF_SHARED, "safe", sc); ++ if (rc) { ++ device_printf(sc->sc_dev, "failed to hook irq %d\n", sc->sc_irq); ++ goto out; ++ } ++ sc->sc_irq = dev->irq; ++ ++ sc->sc_chiprev = READ_REG(sc, SAFE_DEVINFO) & ++ (SAFE_DEVINFO_REV_MAJ | SAFE_DEVINFO_REV_MIN); ++ ++ /* ++ * Allocate packet engine descriptors. ++ */ ++ sc->sc_ringalloc.dma_vaddr = pci_alloc_consistent(sc->sc_pcidev, ++ SAFE_MAX_NQUEUE * sizeof (struct safe_ringentry), ++ &sc->sc_ringalloc.dma_paddr); ++ if (!sc->sc_ringalloc.dma_vaddr) { ++ device_printf(sc->sc_dev, "cannot allocate PE descriptor ring\n"); ++ goto out; ++ } ++ ++ /* ++ * Hookup the static portion of all our data structures. ++ */ ++ sc->sc_ring = (struct safe_ringentry *) sc->sc_ringalloc.dma_vaddr; ++ sc->sc_ringtop = sc->sc_ring + SAFE_MAX_NQUEUE; ++ sc->sc_front = sc->sc_ring; ++ sc->sc_back = sc->sc_ring; ++ raddr = sc->sc_ringalloc.dma_paddr; ++ bzero(sc->sc_ring, SAFE_MAX_NQUEUE * sizeof(struct safe_ringentry)); ++ for (i = 0; i < SAFE_MAX_NQUEUE; i++) { ++ struct safe_ringentry *re = &sc->sc_ring[i]; ++ ++ re->re_desc.d_sa = raddr + ++ offsetof(struct safe_ringentry, re_sa); ++ re->re_sa.sa_staterec = raddr + ++ offsetof(struct safe_ringentry, re_sastate); ++ ++ raddr += sizeof (struct safe_ringentry); ++ } ++ spin_lock_init(&sc->sc_ringmtx); ++ ++ /* ++ * Allocate scatter and gather particle descriptors. ++ */ ++ sc->sc_spalloc.dma_vaddr = pci_alloc_consistent(sc->sc_pcidev, ++ SAFE_TOTAL_SPART * sizeof (struct safe_pdesc), ++ &sc->sc_spalloc.dma_paddr); ++ if (!sc->sc_spalloc.dma_vaddr) { ++ device_printf(sc->sc_dev, "cannot allocate source particle descriptor ring\n"); ++ goto out; ++ } ++ sc->sc_spring = (struct safe_pdesc *) sc->sc_spalloc.dma_vaddr; ++ sc->sc_springtop = sc->sc_spring + SAFE_TOTAL_SPART; ++ sc->sc_spfree = sc->sc_spring; ++ bzero(sc->sc_spring, SAFE_TOTAL_SPART * sizeof(struct safe_pdesc)); ++ ++ sc->sc_dpalloc.dma_vaddr = pci_alloc_consistent(sc->sc_pcidev, ++ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), ++ &sc->sc_dpalloc.dma_paddr); ++ if (!sc->sc_dpalloc.dma_vaddr) { ++ device_printf(sc->sc_dev, "cannot allocate destination particle descriptor ring\n"); ++ goto out; ++ } ++ sc->sc_dpring = (struct safe_pdesc *) sc->sc_dpalloc.dma_vaddr; ++ sc->sc_dpringtop = sc->sc_dpring + SAFE_TOTAL_DPART; ++ sc->sc_dpfree = sc->sc_dpring; ++ bzero(sc->sc_dpring, SAFE_TOTAL_DPART * sizeof(struct safe_pdesc)); ++ ++ sc->sc_cid = crypto_get_driverid(softc_get_device(sc), CRYPTOCAP_F_HARDWARE); ++ if (sc->sc_cid < 0) { ++ device_printf(sc->sc_dev, "could not get crypto driver id\n"); ++ goto out; ++ } ++ ++ printf("%s:", device_get_nameunit(sc->sc_dev)); ++ ++ devinfo = READ_REG(sc, SAFE_DEVINFO); ++ if (devinfo & SAFE_DEVINFO_RNG) { ++ sc->sc_flags |= SAFE_FLAGS_RNG; ++ printf(" rng"); ++ } ++ if (devinfo & SAFE_DEVINFO_PKEY) { ++ printf(" key"); ++ sc->sc_flags |= SAFE_FLAGS_KEY; ++ crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0); ++#if 0 ++ crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0); ++#endif ++ init_timer(&sc->sc_pkto); ++ sc->sc_pkto.function = safe_kpoll; ++ sc->sc_pkto.data = (unsigned long) device_get_unit(sc->sc_dev); ++ } ++ if (devinfo & SAFE_DEVINFO_DES) { ++ printf(" des/3des"); ++ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); ++ } ++ if (devinfo & SAFE_DEVINFO_AES) { ++ printf(" aes"); ++ crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); ++ } ++ if (devinfo & SAFE_DEVINFO_MD5) { ++ printf(" md5"); ++ crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); ++ } ++ if (devinfo & SAFE_DEVINFO_SHA1) { ++ printf(" sha1"); ++ crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); ++ } ++ printf(" null"); ++ crypto_register(sc->sc_cid, CRYPTO_NULL_CBC, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_NULL_HMAC, 0, 0); ++ /* XXX other supported algorithms */ ++ printf("\n"); ++ ++ safe_reset_board(sc); /* reset h/w */ ++ safe_init_board(sc); /* init h/w */ ++ ++#if defined(CONFIG_OCF_RANDOMHARVEST) && !defined(SAFE_NO_RNG) ++ if (sc->sc_flags & SAFE_FLAGS_RNG) { ++ safe_rng_init(sc); ++ crypto_rregister(sc->sc_cid, safe_read_random, sc); ++ } ++#endif /* SAFE_NO_RNG */ ++ ++ return (0); ++ ++out: ++ if (sc->sc_cid >= 0) ++ crypto_unregister_all(sc->sc_cid); ++ if (sc->sc_irq != -1) ++ free_irq(sc->sc_irq, sc); ++ if (sc->sc_ringalloc.dma_vaddr) ++ pci_free_consistent(sc->sc_pcidev, ++ SAFE_MAX_NQUEUE * sizeof (struct safe_ringentry), ++ sc->sc_ringalloc.dma_vaddr, sc->sc_ringalloc.dma_paddr); ++ if (sc->sc_spalloc.dma_vaddr) ++ pci_free_consistent(sc->sc_pcidev, ++ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), ++ sc->sc_spalloc.dma_vaddr, sc->sc_spalloc.dma_paddr); ++ if (sc->sc_dpalloc.dma_vaddr) ++ pci_free_consistent(sc->sc_pcidev, ++ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), ++ sc->sc_dpalloc.dma_vaddr, sc->sc_dpalloc.dma_paddr); ++ kfree(sc); ++ return(-ENODEV); ++} ++ ++static void safe_remove(struct pci_dev *dev) ++{ ++ struct safe_softc *sc = pci_get_drvdata(dev); ++ ++ DPRINTF(("%s()\n", __FUNCTION__)); ++ ++ /* XXX wait/abort active ops */ ++ ++ WRITE_REG(sc, SAFE_HI_MASK, 0); /* disable interrupts */ ++ ++ del_timer_sync(&sc->sc_pkto); ++ ++ crypto_unregister_all(sc->sc_cid); ++ ++ safe_cleanchip(sc); ++ ++ if (sc->sc_irq != -1) ++ free_irq(sc->sc_irq, sc); ++ if (sc->sc_ringalloc.dma_vaddr) ++ pci_free_consistent(sc->sc_pcidev, ++ SAFE_MAX_NQUEUE * sizeof (struct safe_ringentry), ++ sc->sc_ringalloc.dma_vaddr, sc->sc_ringalloc.dma_paddr); ++ if (sc->sc_spalloc.dma_vaddr) ++ pci_free_consistent(sc->sc_pcidev, ++ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), ++ sc->sc_spalloc.dma_vaddr, sc->sc_spalloc.dma_paddr); ++ if (sc->sc_dpalloc.dma_vaddr) ++ pci_free_consistent(sc->sc_pcidev, ++ SAFE_TOTAL_DPART * sizeof (struct safe_pdesc), ++ sc->sc_dpalloc.dma_vaddr, sc->sc_dpalloc.dma_paddr); ++ sc->sc_irq = -1; ++ sc->sc_ringalloc.dma_vaddr = NULL; ++ sc->sc_spalloc.dma_vaddr = NULL; ++ sc->sc_dpalloc.dma_vaddr = NULL; ++} ++ ++static struct pci_device_id safe_pci_tbl[] = { ++ { PCI_VENDOR_SAFENET, PCI_PRODUCT_SAFEXCEL, ++ PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(pci, safe_pci_tbl); ++ ++static struct pci_driver safe_driver = { ++ .name = "safe", ++ .id_table = safe_pci_tbl, ++ .probe = safe_probe, ++ .remove = safe_remove, ++ /* add PM stuff here one day */ ++}; ++ ++static int __init safe_init (void) ++{ ++ struct safe_softc *sc = NULL; ++ int rc; ++ ++ DPRINTF(("%s(%p)\n", __FUNCTION__, safe_init)); ++ ++ rc = pci_register_driver(&safe_driver); ++ pci_register_driver_compat(&safe_driver, rc); ++ ++ return rc; ++} ++ ++static void __exit safe_exit (void) ++{ ++ pci_unregister_driver(&safe_driver); ++} ++ ++module_init(safe_init); ++module_exit(safe_exit); ++ ++MODULE_LICENSE("BSD"); ++MODULE_AUTHOR("David McCullough "); ++MODULE_DESCRIPTION("OCF driver for safenet PCI crypto devices"); +diff -Nur linux-3.1.4.orig/crypto/ocf/safe/safereg.h linux-3.1.4/crypto/ocf/safe/safereg.h +--- linux-3.1.4.orig/crypto/ocf/safe/safereg.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/safe/safereg.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,421 @@ ++/*- ++ * Copyright (c) 2003 Sam Leffler, Errno Consulting ++ * Copyright (c) 2003 Global Technology Associates, Inc. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE ++ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ++ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ++ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF ++ * SUCH DAMAGE. ++ * ++ * $FreeBSD: src/sys/dev/safe/safereg.h,v 1.1 2003/07/21 21:46:07 sam Exp $ ++ */ ++#ifndef _SAFE_SAFEREG_H_ ++#define _SAFE_SAFEREG_H_ ++ ++/* ++ * Register definitions for SafeNet SafeXcel-1141 crypto device. ++ * Definitions from revision 1.3 (Nov 6 2002) of the User's Manual. ++ */ ++ ++#define BS_BAR 0x10 /* DMA base address register */ ++#define BS_TRDY_TIMEOUT 0x40 /* TRDY timeout */ ++#define BS_RETRY_TIMEOUT 0x41 /* DMA retry timeout */ ++ ++#define PCI_VENDOR_SAFENET 0x16ae /* SafeNet, Inc. */ ++ ++/* SafeNet */ ++#define PCI_PRODUCT_SAFEXCEL 0x1141 /* 1141 */ ++ ++#define SAFE_PE_CSR 0x0000 /* Packet Enginge Ctrl/Status */ ++#define SAFE_PE_SRC 0x0004 /* Packet Engine Source */ ++#define SAFE_PE_DST 0x0008 /* Packet Engine Destination */ ++#define SAFE_PE_SA 0x000c /* Packet Engine SA */ ++#define SAFE_PE_LEN 0x0010 /* Packet Engine Length */ ++#define SAFE_PE_DMACFG 0x0040 /* Packet Engine DMA Configuration */ ++#define SAFE_PE_DMASTAT 0x0044 /* Packet Engine DMA Status */ ++#define SAFE_PE_PDRBASE 0x0048 /* Packet Engine Descriptor Ring Base */ ++#define SAFE_PE_RDRBASE 0x004c /* Packet Engine Result Ring Base */ ++#define SAFE_PE_RINGCFG 0x0050 /* Packet Engine Ring Configuration */ ++#define SAFE_PE_RINGPOLL 0x0054 /* Packet Engine Ring Poll */ ++#define SAFE_PE_IRNGSTAT 0x0058 /* Packet Engine Internal Ring Status */ ++#define SAFE_PE_ERNGSTAT 0x005c /* Packet Engine External Ring Status */ ++#define SAFE_PE_IOTHRESH 0x0060 /* Packet Engine I/O Threshold */ ++#define SAFE_PE_GRNGBASE 0x0064 /* Packet Engine Gather Ring Base */ ++#define SAFE_PE_SRNGBASE 0x0068 /* Packet Engine Scatter Ring Base */ ++#define SAFE_PE_PARTSIZE 0x006c /* Packet Engine Particlar Ring Size */ ++#define SAFE_PE_PARTCFG 0x0070 /* Packet Engine Particle Ring Config */ ++#define SAFE_CRYPTO_CTRL 0x0080 /* Crypto Control */ ++#define SAFE_DEVID 0x0084 /* Device ID */ ++#define SAFE_DEVINFO 0x0088 /* Device Info */ ++#define SAFE_HU_STAT 0x00a0 /* Host Unmasked Status */ ++#define SAFE_HM_STAT 0x00a4 /* Host Masked Status (read-only) */ ++#define SAFE_HI_CLR 0x00a4 /* Host Clear Interrupt (write-only) */ ++#define SAFE_HI_MASK 0x00a8 /* Host Mask Control */ ++#define SAFE_HI_CFG 0x00ac /* Interrupt Configuration */ ++#define SAFE_HI_RD_DESCR 0x00b4 /* Force Descriptor Read */ ++#define SAFE_HI_DESC_CNT 0x00b8 /* Host Descriptor Done Count */ ++#define SAFE_DMA_ENDIAN 0x00c0 /* Master Endian Status */ ++#define SAFE_DMA_SRCADDR 0x00c4 /* DMA Source Address Status */ ++#define SAFE_DMA_DSTADDR 0x00c8 /* DMA Destination Address Status */ ++#define SAFE_DMA_STAT 0x00cc /* DMA Current Status */ ++#define SAFE_DMA_CFG 0x00d4 /* DMA Configuration/Status */ ++#define SAFE_ENDIAN 0x00e0 /* Endian Configuration */ ++#define SAFE_PK_A_ADDR 0x0800 /* Public Key A Address */ ++#define SAFE_PK_B_ADDR 0x0804 /* Public Key B Address */ ++#define SAFE_PK_C_ADDR 0x0808 /* Public Key C Address */ ++#define SAFE_PK_D_ADDR 0x080c /* Public Key D Address */ ++#define SAFE_PK_A_LEN 0x0810 /* Public Key A Length */ ++#define SAFE_PK_B_LEN 0x0814 /* Public Key B Length */ ++#define SAFE_PK_SHIFT 0x0818 /* Public Key Shift */ ++#define SAFE_PK_FUNC 0x081c /* Public Key Function */ ++#define SAFE_PK_RAM_START 0x1000 /* Public Key RAM start address */ ++#define SAFE_PK_RAM_END 0x1fff /* Public Key RAM end address */ ++ ++#define SAFE_RNG_OUT 0x0100 /* RNG Output */ ++#define SAFE_RNG_STAT 0x0104 /* RNG Status */ ++#define SAFE_RNG_CTRL 0x0108 /* RNG Control */ ++#define SAFE_RNG_A 0x010c /* RNG A */ ++#define SAFE_RNG_B 0x0110 /* RNG B */ ++#define SAFE_RNG_X_LO 0x0114 /* RNG X [31:0] */ ++#define SAFE_RNG_X_MID 0x0118 /* RNG X [63:32] */ ++#define SAFE_RNG_X_HI 0x011c /* RNG X [80:64] */ ++#define SAFE_RNG_X_CNTR 0x0120 /* RNG Counter */ ++#define SAFE_RNG_ALM_CNT 0x0124 /* RNG Alarm Count */ ++#define SAFE_RNG_CNFG 0x0128 /* RNG Configuration */ ++#define SAFE_RNG_LFSR1_LO 0x012c /* RNG LFSR1 [31:0] */ ++#define SAFE_RNG_LFSR1_HI 0x0130 /* RNG LFSR1 [47:32] */ ++#define SAFE_RNG_LFSR2_LO 0x0134 /* RNG LFSR1 [31:0] */ ++#define SAFE_RNG_LFSR2_HI 0x0138 /* RNG LFSR1 [47:32] */ ++ ++#define SAFE_PE_CSR_READY 0x00000001 /* ready for processing */ ++#define SAFE_PE_CSR_DONE 0x00000002 /* h/w completed processing */ ++#define SAFE_PE_CSR_LOADSA 0x00000004 /* load SA digests */ ++#define SAFE_PE_CSR_HASHFINAL 0x00000010 /* do hash pad & write result */ ++#define SAFE_PE_CSR_SABUSID 0x000000c0 /* bus id for SA */ ++#define SAFE_PE_CSR_SAPCI 0x00000040 /* PCI bus id for SA */ ++#define SAFE_PE_CSR_NXTHDR 0x0000ff00 /* next hdr value for IPsec */ ++#define SAFE_PE_CSR_FPAD 0x0000ff00 /* fixed pad for basic ops */ ++#define SAFE_PE_CSR_STATUS 0x00ff0000 /* operation result status */ ++#define SAFE_PE_CSR_AUTH_FAIL 0x00010000 /* ICV mismatch (inbound) */ ++#define SAFE_PE_CSR_PAD_FAIL 0x00020000 /* pad verify fail (inbound) */ ++#define SAFE_PE_CSR_SEQ_FAIL 0x00040000 /* sequence number (inbound) */ ++#define SAFE_PE_CSR_XERROR 0x00080000 /* extended error follows */ ++#define SAFE_PE_CSR_XECODE 0x00f00000 /* extended error code */ ++#define SAFE_PE_CSR_XECODE_S 20 ++#define SAFE_PE_CSR_XECODE_BADCMD 0 /* invalid command */ ++#define SAFE_PE_CSR_XECODE_BADALG 1 /* invalid algorithm */ ++#define SAFE_PE_CSR_XECODE_ALGDIS 2 /* algorithm disabled */ ++#define SAFE_PE_CSR_XECODE_ZEROLEN 3 /* zero packet length */ ++#define SAFE_PE_CSR_XECODE_DMAERR 4 /* bus DMA error */ ++#define SAFE_PE_CSR_XECODE_PIPEABORT 5 /* secondary bus DMA error */ ++#define SAFE_PE_CSR_XECODE_BADSPI 6 /* IPsec SPI mismatch */ ++#define SAFE_PE_CSR_XECODE_TIMEOUT 10 /* failsafe timeout */ ++#define SAFE_PE_CSR_PAD 0xff000000 /* ESP padding control/status */ ++#define SAFE_PE_CSR_PAD_MIN 0x00000000 /* minimum IPsec padding */ ++#define SAFE_PE_CSR_PAD_16 0x08000000 /* pad to 16-byte boundary */ ++#define SAFE_PE_CSR_PAD_32 0x10000000 /* pad to 32-byte boundary */ ++#define SAFE_PE_CSR_PAD_64 0x20000000 /* pad to 64-byte boundary */ ++#define SAFE_PE_CSR_PAD_128 0x40000000 /* pad to 128-byte boundary */ ++#define SAFE_PE_CSR_PAD_256 0x80000000 /* pad to 256-byte boundary */ ++ ++/* ++ * Check the CSR to see if the PE has returned ownership to ++ * the host. Note that before processing a descriptor this ++ * must be done followed by a check of the SAFE_PE_LEN register ++ * status bits to avoid premature processing of a descriptor ++ * on its way back to the host. ++ */ ++#define SAFE_PE_CSR_IS_DONE(_csr) \ ++ (((_csr) & (SAFE_PE_CSR_READY | SAFE_PE_CSR_DONE)) == SAFE_PE_CSR_DONE) ++ ++#define SAFE_PE_LEN_LENGTH 0x000fffff /* total length (bytes) */ ++#define SAFE_PE_LEN_READY 0x00400000 /* ready for processing */ ++#define SAFE_PE_LEN_DONE 0x00800000 /* h/w completed processing */ ++#define SAFE_PE_LEN_BYPASS 0xff000000 /* bypass offset (bytes) */ ++#define SAFE_PE_LEN_BYPASS_S 24 ++ ++#define SAFE_PE_LEN_IS_DONE(_len) \ ++ (((_len) & (SAFE_PE_LEN_READY | SAFE_PE_LEN_DONE)) == SAFE_PE_LEN_DONE) ++ ++/* NB: these apply to HU_STAT, HM_STAT, HI_CLR, and HI_MASK */ ++#define SAFE_INT_PE_CDONE 0x00000002 /* PE context done */ ++#define SAFE_INT_PE_DDONE 0x00000008 /* PE descriptor done */ ++#define SAFE_INT_PE_ERROR 0x00000010 /* PE error */ ++#define SAFE_INT_PE_ODONE 0x00000020 /* PE operation done */ ++ ++#define SAFE_HI_CFG_PULSE 0x00000001 /* use pulse interrupt */ ++#define SAFE_HI_CFG_LEVEL 0x00000000 /* use level interrupt */ ++#define SAFE_HI_CFG_AUTOCLR 0x00000002 /* auto-clear pulse interrupt */ ++ ++#define SAFE_ENDIAN_PASS 0x000000e4 /* straight pass-thru */ ++#define SAFE_ENDIAN_SWAB 0x0000001b /* swap bytes in 32-bit word */ ++ ++#define SAFE_PE_DMACFG_PERESET 0x00000001 /* reset packet engine */ ++#define SAFE_PE_DMACFG_PDRRESET 0x00000002 /* reset PDR counters/ptrs */ ++#define SAFE_PE_DMACFG_SGRESET 0x00000004 /* reset scatter/gather cache */ ++#define SAFE_PE_DMACFG_FSENA 0x00000008 /* enable failsafe reset */ ++#define SAFE_PE_DMACFG_PEMODE 0x00000100 /* packet engine mode */ ++#define SAFE_PE_DMACFG_SAPREC 0x00000200 /* SA precedes packet */ ++#define SAFE_PE_DMACFG_PKFOLL 0x00000400 /* packet follows descriptor */ ++#define SAFE_PE_DMACFG_GPRBID 0x00003000 /* gather particle ring busid */ ++#define SAFE_PE_DMACFG_GPRPCI 0x00001000 /* PCI gather particle ring */ ++#define SAFE_PE_DMACFG_SPRBID 0x0000c000 /* scatter part. ring busid */ ++#define SAFE_PE_DMACFG_SPRPCI 0x00004000 /* PCI scatter part. ring */ ++#define SAFE_PE_DMACFG_ESDESC 0x00010000 /* endian swap descriptors */ ++#define SAFE_PE_DMACFG_ESSA 0x00020000 /* endian swap SA data */ ++#define SAFE_PE_DMACFG_ESPACKET 0x00040000 /* endian swap packet data */ ++#define SAFE_PE_DMACFG_ESPDESC 0x00080000 /* endian swap particle desc. */ ++#define SAFE_PE_DMACFG_NOPDRUP 0x00100000 /* supp. PDR ownership update */ ++#define SAFE_PD_EDMACFG_PCIMODE 0x01000000 /* PCI target mode */ ++ ++#define SAFE_PE_DMASTAT_PEIDONE 0x00000001 /* PE core input done */ ++#define SAFE_PE_DMASTAT_PEODONE 0x00000002 /* PE core output done */ ++#define SAFE_PE_DMASTAT_ENCDONE 0x00000004 /* encryption done */ ++#define SAFE_PE_DMASTAT_IHDONE 0x00000008 /* inner hash done */ ++#define SAFE_PE_DMASTAT_OHDONE 0x00000010 /* outer hash (HMAC) done */ ++#define SAFE_PE_DMASTAT_PADFLT 0x00000020 /* crypto pad fault */ ++#define SAFE_PE_DMASTAT_ICVFLT 0x00000040 /* ICV fault */ ++#define SAFE_PE_DMASTAT_SPIMIS 0x00000080 /* SPI mismatch */ ++#define SAFE_PE_DMASTAT_CRYPTO 0x00000100 /* crypto engine timeout */ ++#define SAFE_PE_DMASTAT_CQACT 0x00000200 /* command queue active */ ++#define SAFE_PE_DMASTAT_IRACT 0x00000400 /* input request active */ ++#define SAFE_PE_DMASTAT_ORACT 0x00000800 /* output request active */ ++#define SAFE_PE_DMASTAT_PEISIZE 0x003ff000 /* PE input size:32-bit words */ ++#define SAFE_PE_DMASTAT_PEOSIZE 0xffc00000 /* PE out. size:32-bit words */ ++ ++#define SAFE_PE_RINGCFG_SIZE 0x000003ff /* ring size (descriptors) */ ++#define SAFE_PE_RINGCFG_OFFSET 0xffff0000 /* offset btw desc's (dwords) */ ++#define SAFE_PE_RINGCFG_OFFSET_S 16 ++ ++#define SAFE_PE_RINGPOLL_POLL 0x00000fff /* polling frequency/divisor */ ++#define SAFE_PE_RINGPOLL_RETRY 0x03ff0000 /* polling frequency/divisor */ ++#define SAFE_PE_RINGPOLL_CONT 0x80000000 /* continuously poll */ ++ ++#define SAFE_PE_IRNGSTAT_CQAVAIL 0x00000001 /* command queue available */ ++ ++#define SAFE_PE_ERNGSTAT_NEXT 0x03ff0000 /* index of next packet desc. */ ++#define SAFE_PE_ERNGSTAT_NEXT_S 16 ++ ++#define SAFE_PE_IOTHRESH_INPUT 0x000003ff /* input threshold (dwords) */ ++#define SAFE_PE_IOTHRESH_OUTPUT 0x03ff0000 /* output threshold (dwords) */ ++ ++#define SAFE_PE_PARTCFG_SIZE 0x0000ffff /* scatter particle size */ ++#define SAFE_PE_PARTCFG_GBURST 0x00030000 /* gather particle burst */ ++#define SAFE_PE_PARTCFG_GBURST_2 0x00000000 ++#define SAFE_PE_PARTCFG_GBURST_4 0x00010000 ++#define SAFE_PE_PARTCFG_GBURST_8 0x00020000 ++#define SAFE_PE_PARTCFG_GBURST_16 0x00030000 ++#define SAFE_PE_PARTCFG_SBURST 0x000c0000 /* scatter particle burst */ ++#define SAFE_PE_PARTCFG_SBURST_2 0x00000000 ++#define SAFE_PE_PARTCFG_SBURST_4 0x00040000 ++#define SAFE_PE_PARTCFG_SBURST_8 0x00080000 ++#define SAFE_PE_PARTCFG_SBURST_16 0x000c0000 ++ ++#define SAFE_PE_PARTSIZE_SCAT 0xffff0000 /* scatter particle ring size */ ++#define SAFE_PE_PARTSIZE_GATH 0x0000ffff /* gather particle ring size */ ++ ++#define SAFE_CRYPTO_CTRL_3DES 0x00000001 /* enable 3DES support */ ++#define SAFE_CRYPTO_CTRL_PKEY 0x00010000 /* enable public key support */ ++#define SAFE_CRYPTO_CTRL_RNG 0x00020000 /* enable RNG support */ ++ ++#define SAFE_DEVINFO_REV_MIN 0x0000000f /* minor rev for chip */ ++#define SAFE_DEVINFO_REV_MAJ 0x000000f0 /* major rev for chip */ ++#define SAFE_DEVINFO_REV_MAJ_S 4 ++#define SAFE_DEVINFO_DES 0x00000100 /* DES/3DES support present */ ++#define SAFE_DEVINFO_ARC4 0x00000200 /* ARC4 support present */ ++#define SAFE_DEVINFO_AES 0x00000400 /* AES support present */ ++#define SAFE_DEVINFO_MD5 0x00001000 /* MD5 support present */ ++#define SAFE_DEVINFO_SHA1 0x00002000 /* SHA-1 support present */ ++#define SAFE_DEVINFO_RIPEMD 0x00004000 /* RIPEMD support present */ ++#define SAFE_DEVINFO_DEFLATE 0x00010000 /* Deflate support present */ ++#define SAFE_DEVINFO_SARAM 0x00100000 /* on-chip SA RAM present */ ++#define SAFE_DEVINFO_EMIBUS 0x00200000 /* EMI bus present */ ++#define SAFE_DEVINFO_PKEY 0x00400000 /* public key support present */ ++#define SAFE_DEVINFO_RNG 0x00800000 /* RNG present */ ++ ++#define SAFE_REV(_maj, _min) (((_maj) << SAFE_DEVINFO_REV_MAJ_S) | (_min)) ++#define SAFE_REV_MAJ(_chiprev) \ ++ (((_chiprev) & SAFE_DEVINFO_REV_MAJ) >> SAFE_DEVINFO_REV_MAJ_S) ++#define SAFE_REV_MIN(_chiprev) ((_chiprev) & SAFE_DEVINFO_REV_MIN) ++ ++#define SAFE_PK_FUNC_MULT 0x00000001 /* Multiply function */ ++#define SAFE_PK_FUNC_SQUARE 0x00000004 /* Square function */ ++#define SAFE_PK_FUNC_ADD 0x00000010 /* Add function */ ++#define SAFE_PK_FUNC_SUB 0x00000020 /* Subtract function */ ++#define SAFE_PK_FUNC_LSHIFT 0x00000040 /* Left-shift function */ ++#define SAFE_PK_FUNC_RSHIFT 0x00000080 /* Right-shift function */ ++#define SAFE_PK_FUNC_DIV 0x00000100 /* Divide function */ ++#define SAFE_PK_FUNC_CMP 0x00000400 /* Compare function */ ++#define SAFE_PK_FUNC_COPY 0x00000800 /* Copy function */ ++#define SAFE_PK_FUNC_EXP16 0x00002000 /* Exponentiate (4-bit ACT) */ ++#define SAFE_PK_FUNC_EXP4 0x00004000 /* Exponentiate (2-bit ACT) */ ++#define SAFE_PK_FUNC_RUN 0x00008000 /* start/status */ ++ ++#define SAFE_RNG_STAT_BUSY 0x00000001 /* busy, data not valid */ ++ ++#define SAFE_RNG_CTRL_PRE_LFSR 0x00000001 /* enable output pre-LFSR */ ++#define SAFE_RNG_CTRL_TST_MODE 0x00000002 /* enable test mode */ ++#define SAFE_RNG_CTRL_TST_RUN 0x00000004 /* start test state machine */ ++#define SAFE_RNG_CTRL_ENA_RING1 0x00000008 /* test entropy oscillator #1 */ ++#define SAFE_RNG_CTRL_ENA_RING2 0x00000010 /* test entropy oscillator #2 */ ++#define SAFE_RNG_CTRL_DIS_ALARM 0x00000020 /* disable RNG alarm reports */ ++#define SAFE_RNG_CTRL_TST_CLOCK 0x00000040 /* enable test clock */ ++#define SAFE_RNG_CTRL_SHORTEN 0x00000080 /* shorten state timers */ ++#define SAFE_RNG_CTRL_TST_ALARM 0x00000100 /* simulate alarm state */ ++#define SAFE_RNG_CTRL_RST_LFSR 0x00000200 /* reset LFSR */ ++ ++/* ++ * Packet engine descriptor. Note that d_csr is a copy of the ++ * SAFE_PE_CSR register and all definitions apply, and d_len ++ * is a copy of the SAFE_PE_LEN register and all definitions apply. ++ * d_src and d_len may point directly to contiguous data or to a ++ * list of ``particle descriptors'' when using scatter/gather i/o. ++ */ ++struct safe_desc { ++ u_int32_t d_csr; /* per-packet control/status */ ++ u_int32_t d_src; /* source address */ ++ u_int32_t d_dst; /* destination address */ ++ u_int32_t d_sa; /* SA address */ ++ u_int32_t d_len; /* length, bypass, status */ ++}; ++ ++/* ++ * Scatter/Gather particle descriptor. ++ * ++ * NB: scatter descriptors do not specify a size; this is fixed ++ * by the setting of the SAFE_PE_PARTCFG register. ++ */ ++struct safe_pdesc { ++ u_int32_t pd_addr; /* particle address */ ++#ifdef __BIG_ENDIAN ++ u_int16_t pd_flags; /* control word */ ++ u_int16_t pd_size; /* particle size (bytes) */ ++#else ++ u_int16_t pd_flags; /* control word */ ++ u_int16_t pd_size; /* particle size (bytes) */ ++#endif ++}; ++ ++#define SAFE_PD_READY 0x0001 /* ready for processing */ ++#define SAFE_PD_DONE 0x0002 /* h/w completed processing */ ++ ++/* ++ * Security Association (SA) Record (Rev 1). One of these is ++ * required for each operation processed by the packet engine. ++ */ ++struct safe_sarec { ++ u_int32_t sa_cmd0; ++ u_int32_t sa_cmd1; ++ u_int32_t sa_resv0; ++ u_int32_t sa_resv1; ++ u_int32_t sa_key[8]; /* DES/3DES/AES key */ ++ u_int32_t sa_indigest[5]; /* inner digest */ ++ u_int32_t sa_outdigest[5]; /* outer digest */ ++ u_int32_t sa_spi; /* SPI */ ++ u_int32_t sa_seqnum; /* sequence number */ ++ u_int32_t sa_seqmask[2]; /* sequence number mask */ ++ u_int32_t sa_resv2; ++ u_int32_t sa_staterec; /* address of state record */ ++ u_int32_t sa_resv3[2]; ++ u_int32_t sa_samgmt0; /* SA management field 0 */ ++ u_int32_t sa_samgmt1; /* SA management field 0 */ ++}; ++ ++#define SAFE_SA_CMD0_OP 0x00000007 /* operation code */ ++#define SAFE_SA_CMD0_OP_CRYPT 0x00000000 /* encrypt/decrypt (basic) */ ++#define SAFE_SA_CMD0_OP_BOTH 0x00000001 /* encrypt-hash/hash-decrypto */ ++#define SAFE_SA_CMD0_OP_HASH 0x00000003 /* hash (outbound-only) */ ++#define SAFE_SA_CMD0_OP_ESP 0x00000000 /* ESP in/out (proto) */ ++#define SAFE_SA_CMD0_OP_AH 0x00000001 /* AH in/out (proto) */ ++#define SAFE_SA_CMD0_INBOUND 0x00000008 /* inbound operation */ ++#define SAFE_SA_CMD0_OUTBOUND 0x00000000 /* outbound operation */ ++#define SAFE_SA_CMD0_GROUP 0x00000030 /* operation group */ ++#define SAFE_SA_CMD0_BASIC 0x00000000 /* basic operation */ ++#define SAFE_SA_CMD0_PROTO 0x00000010 /* protocol/packet operation */ ++#define SAFE_SA_CMD0_BUNDLE 0x00000020 /* bundled operation (resvd) */ ++#define SAFE_SA_CMD0_PAD 0x000000c0 /* crypto pad method */ ++#define SAFE_SA_CMD0_PAD_IPSEC 0x00000000 /* IPsec padding */ ++#define SAFE_SA_CMD0_PAD_PKCS7 0x00000040 /* PKCS#7 padding */ ++#define SAFE_SA_CMD0_PAD_CONS 0x00000080 /* constant padding */ ++#define SAFE_SA_CMD0_PAD_ZERO 0x000000c0 /* zero padding */ ++#define SAFE_SA_CMD0_CRYPT_ALG 0x00000f00 /* symmetric crypto algorithm */ ++#define SAFE_SA_CMD0_DES 0x00000000 /* DES crypto algorithm */ ++#define SAFE_SA_CMD0_3DES 0x00000100 /* 3DES crypto algorithm */ ++#define SAFE_SA_CMD0_AES 0x00000300 /* AES crypto algorithm */ ++#define SAFE_SA_CMD0_CRYPT_NULL 0x00000f00 /* null crypto algorithm */ ++#define SAFE_SA_CMD0_HASH_ALG 0x0000f000 /* hash algorithm */ ++#define SAFE_SA_CMD0_MD5 0x00000000 /* MD5 hash algorithm */ ++#define SAFE_SA_CMD0_SHA1 0x00001000 /* SHA-1 hash algorithm */ ++#define SAFE_SA_CMD0_HASH_NULL 0x0000f000 /* null hash algorithm */ ++#define SAFE_SA_CMD0_HDR_PROC 0x00080000 /* header processing */ ++#define SAFE_SA_CMD0_IBUSID 0x00300000 /* input bus id */ ++#define SAFE_SA_CMD0_IPCI 0x00100000 /* PCI input bus id */ ++#define SAFE_SA_CMD0_OBUSID 0x00c00000 /* output bus id */ ++#define SAFE_SA_CMD0_OPCI 0x00400000 /* PCI output bus id */ ++#define SAFE_SA_CMD0_IVLD 0x03000000 /* IV loading */ ++#define SAFE_SA_CMD0_IVLD_NONE 0x00000000 /* IV no load (reuse) */ ++#define SAFE_SA_CMD0_IVLD_IBUF 0x01000000 /* IV load from input buffer */ ++#define SAFE_SA_CMD0_IVLD_STATE 0x02000000 /* IV load from state */ ++#define SAFE_SA_CMD0_HSLD 0x0c000000 /* hash state loading */ ++#define SAFE_SA_CMD0_HSLD_SA 0x00000000 /* hash state load from SA */ ++#define SAFE_SA_CMD0_HSLD_STATE 0x08000000 /* hash state load from state */ ++#define SAFE_SA_CMD0_HSLD_NONE 0x0c000000 /* hash state no load */ ++#define SAFE_SA_CMD0_SAVEIV 0x10000000 /* save IV */ ++#define SAFE_SA_CMD0_SAVEHASH 0x20000000 /* save hash state */ ++#define SAFE_SA_CMD0_IGATHER 0x40000000 /* input gather */ ++#define SAFE_SA_CMD0_OSCATTER 0x80000000 /* output scatter */ ++ ++#define SAFE_SA_CMD1_HDRCOPY 0x00000002 /* copy header to output */ ++#define SAFE_SA_CMD1_PAYCOPY 0x00000004 /* copy payload to output */ ++#define SAFE_SA_CMD1_PADCOPY 0x00000008 /* copy pad to output */ ++#define SAFE_SA_CMD1_IPV4 0x00000000 /* IPv4 protocol */ ++#define SAFE_SA_CMD1_IPV6 0x00000010 /* IPv6 protocol */ ++#define SAFE_SA_CMD1_MUTABLE 0x00000020 /* mutable bit processing */ ++#define SAFE_SA_CMD1_SRBUSID 0x000000c0 /* state record bus id */ ++#define SAFE_SA_CMD1_SRPCI 0x00000040 /* state record from PCI */ ++#define SAFE_SA_CMD1_CRMODE 0x00000300 /* crypto mode */ ++#define SAFE_SA_CMD1_ECB 0x00000000 /* ECB crypto mode */ ++#define SAFE_SA_CMD1_CBC 0x00000100 /* CBC crypto mode */ ++#define SAFE_SA_CMD1_OFB 0x00000200 /* OFB crypto mode */ ++#define SAFE_SA_CMD1_CFB 0x00000300 /* CFB crypto mode */ ++#define SAFE_SA_CMD1_CRFEEDBACK 0x00000c00 /* crypto feedback mode */ ++#define SAFE_SA_CMD1_64BIT 0x00000000 /* 64-bit crypto feedback */ ++#define SAFE_SA_CMD1_8BIT 0x00000400 /* 8-bit crypto feedback */ ++#define SAFE_SA_CMD1_1BIT 0x00000800 /* 1-bit crypto feedback */ ++#define SAFE_SA_CMD1_128BIT 0x00000c00 /* 128-bit crypto feedback */ ++#define SAFE_SA_CMD1_OPTIONS 0x00001000 /* HMAC/options mutable bit */ ++#define SAFE_SA_CMD1_HMAC SAFE_SA_CMD1_OPTIONS ++#define SAFE_SA_CMD1_SAREV1 0x00008000 /* SA Revision 1 */ ++#define SAFE_SA_CMD1_OFFSET 0x00ff0000 /* hash/crypto offset(dwords) */ ++#define SAFE_SA_CMD1_OFFSET_S 16 ++#define SAFE_SA_CMD1_AESKEYLEN 0x0f000000 /* AES key length */ ++#define SAFE_SA_CMD1_AES128 0x02000000 /* 128-bit AES key */ ++#define SAFE_SA_CMD1_AES192 0x03000000 /* 192-bit AES key */ ++#define SAFE_SA_CMD1_AES256 0x04000000 /* 256-bit AES key */ ++ ++/* ++ * Security Associate State Record (Rev 1). ++ */ ++struct safe_sastate { ++ u_int32_t sa_saved_iv[4]; /* saved IV (DES/3DES/AES) */ ++ u_int32_t sa_saved_hashbc; /* saved hash byte count */ ++ u_int32_t sa_saved_indigest[5]; /* saved inner digest */ ++}; ++#endif /* _SAFE_SAFEREG_H_ */ +diff -Nur linux-3.1.4.orig/crypto/ocf/safe/safevar.h linux-3.1.4/crypto/ocf/safe/safevar.h +--- linux-3.1.4.orig/crypto/ocf/safe/safevar.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/safe/safevar.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,229 @@ ++/*- ++ * The linux port of this code done by David McCullough ++ * Copyright (C) 2004-2010 David McCullough ++ * The license and original author are listed below. ++ * ++ * Copyright (c) 2003 Sam Leffler, Errno Consulting ++ * Copyright (c) 2003 Global Technology Associates, Inc. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE ++ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ++ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ++ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF ++ * SUCH DAMAGE. ++ * ++ * $FreeBSD: src/sys/dev/safe/safevar.h,v 1.2 2006/05/17 18:34:26 pjd Exp $ ++ */ ++#ifndef _SAFE_SAFEVAR_H_ ++#define _SAFE_SAFEVAR_H_ ++ ++/* Maximum queue length */ ++#ifndef SAFE_MAX_NQUEUE ++#define SAFE_MAX_NQUEUE 60 ++#endif ++ ++#define SAFE_MAX_PART 64 /* Maximum scatter/gather depth */ ++#define SAFE_DMA_BOUNDARY 0 /* No boundary for source DMA ops */ ++#define SAFE_MAX_DSIZE 2048 /* MCLBYTES Fixed scatter particle size */ ++#define SAFE_MAX_SSIZE 0x0ffff /* Maximum gather particle size */ ++#define SAFE_MAX_DMA 0xfffff /* Maximum PE operand size (20 bits) */ ++/* total src+dst particle descriptors */ ++#define SAFE_TOTAL_DPART (SAFE_MAX_NQUEUE * SAFE_MAX_PART) ++#define SAFE_TOTAL_SPART (SAFE_MAX_NQUEUE * SAFE_MAX_PART) ++ ++#define SAFE_RNG_MAXBUFSIZ 128 /* 32-bit words */ ++ ++#define SAFE_CARD(sid) (((sid) & 0xf0000000) >> 28) ++#define SAFE_SESSION(sid) ( (sid) & 0x0fffffff) ++#define SAFE_SID(crd, sesn) (((crd) << 28) | ((sesn) & 0x0fffffff)) ++ ++#define SAFE_DEF_RTY 0xff /* PCI Retry Timeout */ ++#define SAFE_DEF_TOUT 0xff /* PCI TRDY Timeout */ ++#define SAFE_DEF_CACHELINE 0x01 /* Cache Line setting */ ++ ++#ifdef __KERNEL__ ++/* ++ * State associated with the allocation of each chunk ++ * of memory setup for DMA. ++ */ ++struct safe_dma_alloc { ++ dma_addr_t dma_paddr; ++ void *dma_vaddr; ++}; ++ ++/* ++ * Cryptographic operand state. One of these exists for each ++ * source and destination operand passed in from the crypto ++ * subsystem. When possible source and destination operands ++ * refer to the same memory. More often they are distinct. ++ * We track the virtual address of each operand as well as ++ * where each is mapped for DMA. ++ */ ++struct safe_operand { ++ union { ++ struct sk_buff *skb; ++ struct uio *io; ++ } u; ++ void *map; ++ int mapsize; /* total number of bytes in segs */ ++ struct { ++ dma_addr_t ds_addr; ++ int ds_len; ++ int ds_tlen; ++ } segs[SAFE_MAX_PART]; ++ int nsegs; ++}; ++ ++/* ++ * Packet engine ring entry and cryptographic operation state. ++ * The packet engine requires a ring of descriptors that contain ++ * pointers to various cryptographic state. However the ring ++ * configuration register allows you to specify an arbitrary size ++ * for ring entries. We use this feature to collect most of the ++ * state for each cryptographic request into one spot. Other than ++ * ring entries only the ``particle descriptors'' (scatter/gather ++ * lists) and the actual operand data are kept separate. The ++ * particle descriptors must also be organized in rings. The ++ * operand data can be located aribtrarily (modulo alignment constraints). ++ * ++ * Note that the descriptor ring is mapped onto the PCI bus so ++ * the hardware can DMA data. This means the entire ring must be ++ * contiguous. ++ */ ++struct safe_ringentry { ++ struct safe_desc re_desc; /* command descriptor */ ++ struct safe_sarec re_sa; /* SA record */ ++ struct safe_sastate re_sastate; /* SA state record */ ++ ++ struct cryptop *re_crp; /* crypto operation */ ++ ++ struct safe_operand re_src; /* source operand */ ++ struct safe_operand re_dst; /* destination operand */ ++ ++ int re_sesn; /* crypto session ID */ ++ int re_flags; ++#define SAFE_QFLAGS_COPYOUTIV 0x1 /* copy back on completion */ ++#define SAFE_QFLAGS_COPYOUTICV 0x2 /* copy back on completion */ ++}; ++ ++#define re_src_skb re_src.u.skb ++#define re_src_io re_src.u.io ++#define re_src_map re_src.map ++#define re_src_nsegs re_src.nsegs ++#define re_src_segs re_src.segs ++#define re_src_mapsize re_src.mapsize ++ ++#define re_dst_skb re_dst.u.skb ++#define re_dst_io re_dst.u.io ++#define re_dst_map re_dst.map ++#define re_dst_nsegs re_dst.nsegs ++#define re_dst_segs re_dst.segs ++#define re_dst_mapsize re_dst.mapsize ++ ++struct rndstate_test; ++ ++struct safe_session { ++ u_int32_t ses_used; ++ u_int32_t ses_klen; /* key length in bits */ ++ u_int32_t ses_key[8]; /* DES/3DES/AES key */ ++ u_int32_t ses_mlen; /* hmac length in bytes */ ++ u_int32_t ses_hminner[5]; /* hmac inner state */ ++ u_int32_t ses_hmouter[5]; /* hmac outer state */ ++}; ++ ++struct safe_pkq { ++ struct list_head pkq_list; ++ struct cryptkop *pkq_krp; ++}; ++ ++struct safe_softc { ++ softc_device_decl sc_dev; ++ u32 sc_irq; ++ ++ struct pci_dev *sc_pcidev; ++ ocf_iomem_t sc_base_addr; ++ ++ u_int sc_chiprev; /* major/minor chip revision */ ++ int sc_flags; /* device specific flags */ ++#define SAFE_FLAGS_KEY 0x01 /* has key accelerator */ ++#define SAFE_FLAGS_RNG 0x02 /* hardware rng */ ++ int sc_suspended; ++ int sc_needwakeup; /* notify crypto layer */ ++ int32_t sc_cid; /* crypto tag */ ++ ++ struct safe_dma_alloc sc_ringalloc; /* PE ring allocation state */ ++ struct safe_ringentry *sc_ring; /* PE ring */ ++ struct safe_ringentry *sc_ringtop; /* PE ring top */ ++ struct safe_ringentry *sc_front; /* next free entry */ ++ struct safe_ringentry *sc_back; /* next pending entry */ ++ int sc_nqchip; /* # passed to chip */ ++ spinlock_t sc_ringmtx; /* PE ring lock */ ++ struct safe_pdesc *sc_spring; /* src particle ring */ ++ struct safe_pdesc *sc_springtop; /* src particle ring top */ ++ struct safe_pdesc *sc_spfree; /* next free src particle */ ++ struct safe_dma_alloc sc_spalloc; /* src particle ring state */ ++ struct safe_pdesc *sc_dpring; /* dest particle ring */ ++ struct safe_pdesc *sc_dpringtop; /* dest particle ring top */ ++ struct safe_pdesc *sc_dpfree; /* next free dest particle */ ++ struct safe_dma_alloc sc_dpalloc; /* dst particle ring state */ ++ int sc_nsessions; /* # of sessions */ ++ struct safe_session *sc_sessions; /* sessions */ ++ ++ struct timer_list sc_pkto; /* PK polling */ ++ spinlock_t sc_pkmtx; /* PK lock */ ++ struct list_head sc_pkq; /* queue of PK requests */ ++ struct safe_pkq *sc_pkq_cur; /* current processing request */ ++ u_int32_t sc_pk_reslen, sc_pk_resoff; ++ ++ int sc_max_dsize; /* maximum safe DMA size */ ++}; ++#endif /* __KERNEL__ */ ++ ++struct safe_stats { ++ u_int64_t st_ibytes; ++ u_int64_t st_obytes; ++ u_int32_t st_ipackets; ++ u_int32_t st_opackets; ++ u_int32_t st_invalid; /* invalid argument */ ++ u_int32_t st_badsession; /* invalid session id */ ++ u_int32_t st_badflags; /* flags indicate !(mbuf | uio) */ ++ u_int32_t st_nodesc; /* op submitted w/o descriptors */ ++ u_int32_t st_badalg; /* unsupported algorithm */ ++ u_int32_t st_ringfull; /* PE descriptor ring full */ ++ u_int32_t st_peoperr; /* PE marked error */ ++ u_int32_t st_dmaerr; /* PE DMA error */ ++ u_int32_t st_bypasstoobig; /* bypass > 96 bytes */ ++ u_int32_t st_skipmismatch; /* enc part begins before auth part */ ++ u_int32_t st_lenmismatch; /* enc length different auth length */ ++ u_int32_t st_coffmisaligned; /* crypto offset not 32-bit aligned */ ++ u_int32_t st_cofftoobig; /* crypto offset > 255 words */ ++ u_int32_t st_iovmisaligned; /* iov op not aligned */ ++ u_int32_t st_iovnotuniform; /* iov op not suitable */ ++ u_int32_t st_unaligned; /* unaligned src caused copy */ ++ u_int32_t st_notuniform; /* non-uniform src caused copy */ ++ u_int32_t st_nomap; /* bus_dmamap_create failed */ ++ u_int32_t st_noload; /* bus_dmamap_load_* failed */ ++ u_int32_t st_nombuf; /* MGET* failed */ ++ u_int32_t st_nomcl; /* MCLGET* failed */ ++ u_int32_t st_maxqchip; /* max mcr1 ops out for processing */ ++ u_int32_t st_rng; /* RNG requests */ ++ u_int32_t st_rngalarm; /* RNG alarm requests */ ++ u_int32_t st_noicvcopy; /* ICV data copies suppressed */ ++}; ++#endif /* _SAFE_SAFEVAR_H_ */ +diff -Nur linux-3.1.4.orig/crypto/ocf/safe/sha1.c linux-3.1.4/crypto/ocf/safe/sha1.c +--- linux-3.1.4.orig/crypto/ocf/safe/sha1.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/safe/sha1.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,279 @@ ++/* $KAME: sha1.c,v 1.5 2000/11/08 06:13:08 itojun Exp $ */ ++/* ++ * Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. Neither the name of the project nor the names of its contributors ++ * may be used to endorse or promote products derived from this software ++ * without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND ++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE ++ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ++ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ++ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF ++ * SUCH DAMAGE. ++ */ ++ ++/* ++ * FIPS pub 180-1: Secure Hash Algorithm (SHA-1) ++ * based on: http://csrc.nist.gov/fips/fip180-1.txt ++ * implemented by Jun-ichiro itojun Itoh ++ */ ++ ++#if 0 ++#include ++__FBSDID("$FreeBSD: src/sys/crypto/sha1.c,v 1.9 2003/06/10 21:36:57 obrien Exp $"); ++ ++#include ++#include ++#include ++#include ++ ++#include ++#endif ++ ++/* sanity check */ ++#if BYTE_ORDER != BIG_ENDIAN ++# if BYTE_ORDER != LITTLE_ENDIAN ++# define unsupported 1 ++# endif ++#endif ++ ++#ifndef unsupported ++ ++/* constant table */ ++static u_int32_t _K[] = { 0x5a827999, 0x6ed9eba1, 0x8f1bbcdc, 0xca62c1d6 }; ++#define K(t) _K[(t) / 20] ++ ++#define F0(b, c, d) (((b) & (c)) | ((~(b)) & (d))) ++#define F1(b, c, d) (((b) ^ (c)) ^ (d)) ++#define F2(b, c, d) (((b) & (c)) | ((b) & (d)) | ((c) & (d))) ++#define F3(b, c, d) (((b) ^ (c)) ^ (d)) ++ ++#define S(n, x) (((x) << (n)) | ((x) >> (32 - n))) ++ ++#undef H ++#define H(n) (ctxt->h.b32[(n)]) ++#define COUNT (ctxt->count) ++#define BCOUNT (ctxt->c.b64[0] / 8) ++#define W(n) (ctxt->m.b32[(n)]) ++ ++#define PUTBYTE(x) { \ ++ ctxt->m.b8[(COUNT % 64)] = (x); \ ++ COUNT++; \ ++ COUNT %= 64; \ ++ ctxt->c.b64[0] += 8; \ ++ if (COUNT % 64 == 0) \ ++ sha1_step(ctxt); \ ++ } ++ ++#define PUTPAD(x) { \ ++ ctxt->m.b8[(COUNT % 64)] = (x); \ ++ COUNT++; \ ++ COUNT %= 64; \ ++ if (COUNT % 64 == 0) \ ++ sha1_step(ctxt); \ ++ } ++ ++static void sha1_step(struct sha1_ctxt *); ++ ++static void ++sha1_step(ctxt) ++ struct sha1_ctxt *ctxt; ++{ ++ u_int32_t a, b, c, d, e; ++ size_t t, s; ++ u_int32_t tmp; ++ ++#if BYTE_ORDER == LITTLE_ENDIAN ++ struct sha1_ctxt tctxt; ++ bcopy(&ctxt->m.b8[0], &tctxt.m.b8[0], 64); ++ ctxt->m.b8[0] = tctxt.m.b8[3]; ctxt->m.b8[1] = tctxt.m.b8[2]; ++ ctxt->m.b8[2] = tctxt.m.b8[1]; ctxt->m.b8[3] = tctxt.m.b8[0]; ++ ctxt->m.b8[4] = tctxt.m.b8[7]; ctxt->m.b8[5] = tctxt.m.b8[6]; ++ ctxt->m.b8[6] = tctxt.m.b8[5]; ctxt->m.b8[7] = tctxt.m.b8[4]; ++ ctxt->m.b8[8] = tctxt.m.b8[11]; ctxt->m.b8[9] = tctxt.m.b8[10]; ++ ctxt->m.b8[10] = tctxt.m.b8[9]; ctxt->m.b8[11] = tctxt.m.b8[8]; ++ ctxt->m.b8[12] = tctxt.m.b8[15]; ctxt->m.b8[13] = tctxt.m.b8[14]; ++ ctxt->m.b8[14] = tctxt.m.b8[13]; ctxt->m.b8[15] = tctxt.m.b8[12]; ++ ctxt->m.b8[16] = tctxt.m.b8[19]; ctxt->m.b8[17] = tctxt.m.b8[18]; ++ ctxt->m.b8[18] = tctxt.m.b8[17]; ctxt->m.b8[19] = tctxt.m.b8[16]; ++ ctxt->m.b8[20] = tctxt.m.b8[23]; ctxt->m.b8[21] = tctxt.m.b8[22]; ++ ctxt->m.b8[22] = tctxt.m.b8[21]; ctxt->m.b8[23] = tctxt.m.b8[20]; ++ ctxt->m.b8[24] = tctxt.m.b8[27]; ctxt->m.b8[25] = tctxt.m.b8[26]; ++ ctxt->m.b8[26] = tctxt.m.b8[25]; ctxt->m.b8[27] = tctxt.m.b8[24]; ++ ctxt->m.b8[28] = tctxt.m.b8[31]; ctxt->m.b8[29] = tctxt.m.b8[30]; ++ ctxt->m.b8[30] = tctxt.m.b8[29]; ctxt->m.b8[31] = tctxt.m.b8[28]; ++ ctxt->m.b8[32] = tctxt.m.b8[35]; ctxt->m.b8[33] = tctxt.m.b8[34]; ++ ctxt->m.b8[34] = tctxt.m.b8[33]; ctxt->m.b8[35] = tctxt.m.b8[32]; ++ ctxt->m.b8[36] = tctxt.m.b8[39]; ctxt->m.b8[37] = tctxt.m.b8[38]; ++ ctxt->m.b8[38] = tctxt.m.b8[37]; ctxt->m.b8[39] = tctxt.m.b8[36]; ++ ctxt->m.b8[40] = tctxt.m.b8[43]; ctxt->m.b8[41] = tctxt.m.b8[42]; ++ ctxt->m.b8[42] = tctxt.m.b8[41]; ctxt->m.b8[43] = tctxt.m.b8[40]; ++ ctxt->m.b8[44] = tctxt.m.b8[47]; ctxt->m.b8[45] = tctxt.m.b8[46]; ++ ctxt->m.b8[46] = tctxt.m.b8[45]; ctxt->m.b8[47] = tctxt.m.b8[44]; ++ ctxt->m.b8[48] = tctxt.m.b8[51]; ctxt->m.b8[49] = tctxt.m.b8[50]; ++ ctxt->m.b8[50] = tctxt.m.b8[49]; ctxt->m.b8[51] = tctxt.m.b8[48]; ++ ctxt->m.b8[52] = tctxt.m.b8[55]; ctxt->m.b8[53] = tctxt.m.b8[54]; ++ ctxt->m.b8[54] = tctxt.m.b8[53]; ctxt->m.b8[55] = tctxt.m.b8[52]; ++ ctxt->m.b8[56] = tctxt.m.b8[59]; ctxt->m.b8[57] = tctxt.m.b8[58]; ++ ctxt->m.b8[58] = tctxt.m.b8[57]; ctxt->m.b8[59] = tctxt.m.b8[56]; ++ ctxt->m.b8[60] = tctxt.m.b8[63]; ctxt->m.b8[61] = tctxt.m.b8[62]; ++ ctxt->m.b8[62] = tctxt.m.b8[61]; ctxt->m.b8[63] = tctxt.m.b8[60]; ++#endif ++ ++ a = H(0); b = H(1); c = H(2); d = H(3); e = H(4); ++ ++ for (t = 0; t < 20; t++) { ++ s = t & 0x0f; ++ if (t >= 16) { ++ W(s) = S(1, W((s+13) & 0x0f) ^ W((s+8) & 0x0f) ^ W((s+2) & 0x0f) ^ W(s)); ++ } ++ tmp = S(5, a) + F0(b, c, d) + e + W(s) + K(t); ++ e = d; d = c; c = S(30, b); b = a; a = tmp; ++ } ++ for (t = 20; t < 40; t++) { ++ s = t & 0x0f; ++ W(s) = S(1, W((s+13) & 0x0f) ^ W((s+8) & 0x0f) ^ W((s+2) & 0x0f) ^ W(s)); ++ tmp = S(5, a) + F1(b, c, d) + e + W(s) + K(t); ++ e = d; d = c; c = S(30, b); b = a; a = tmp; ++ } ++ for (t = 40; t < 60; t++) { ++ s = t & 0x0f; ++ W(s) = S(1, W((s+13) & 0x0f) ^ W((s+8) & 0x0f) ^ W((s+2) & 0x0f) ^ W(s)); ++ tmp = S(5, a) + F2(b, c, d) + e + W(s) + K(t); ++ e = d; d = c; c = S(30, b); b = a; a = tmp; ++ } ++ for (t = 60; t < 80; t++) { ++ s = t & 0x0f; ++ W(s) = S(1, W((s+13) & 0x0f) ^ W((s+8) & 0x0f) ^ W((s+2) & 0x0f) ^ W(s)); ++ tmp = S(5, a) + F3(b, c, d) + e + W(s) + K(t); ++ e = d; d = c; c = S(30, b); b = a; a = tmp; ++ } ++ ++ H(0) = H(0) + a; ++ H(1) = H(1) + b; ++ H(2) = H(2) + c; ++ H(3) = H(3) + d; ++ H(4) = H(4) + e; ++ ++ bzero(&ctxt->m.b8[0], 64); ++} ++ ++/*------------------------------------------------------------*/ ++ ++void ++sha1_init(ctxt) ++ struct sha1_ctxt *ctxt; ++{ ++ bzero(ctxt, sizeof(struct sha1_ctxt)); ++ H(0) = 0x67452301; ++ H(1) = 0xefcdab89; ++ H(2) = 0x98badcfe; ++ H(3) = 0x10325476; ++ H(4) = 0xc3d2e1f0; ++} ++ ++void ++sha1_pad(ctxt) ++ struct sha1_ctxt *ctxt; ++{ ++ size_t padlen; /*pad length in bytes*/ ++ size_t padstart; ++ ++ PUTPAD(0x80); ++ ++ padstart = COUNT % 64; ++ padlen = 64 - padstart; ++ if (padlen < 8) { ++ bzero(&ctxt->m.b8[padstart], padlen); ++ COUNT += padlen; ++ COUNT %= 64; ++ sha1_step(ctxt); ++ padstart = COUNT % 64; /* should be 0 */ ++ padlen = 64 - padstart; /* should be 64 */ ++ } ++ bzero(&ctxt->m.b8[padstart], padlen - 8); ++ COUNT += (padlen - 8); ++ COUNT %= 64; ++#if BYTE_ORDER == BIG_ENDIAN ++ PUTPAD(ctxt->c.b8[0]); PUTPAD(ctxt->c.b8[1]); ++ PUTPAD(ctxt->c.b8[2]); PUTPAD(ctxt->c.b8[3]); ++ PUTPAD(ctxt->c.b8[4]); PUTPAD(ctxt->c.b8[5]); ++ PUTPAD(ctxt->c.b8[6]); PUTPAD(ctxt->c.b8[7]); ++#else ++ PUTPAD(ctxt->c.b8[7]); PUTPAD(ctxt->c.b8[6]); ++ PUTPAD(ctxt->c.b8[5]); PUTPAD(ctxt->c.b8[4]); ++ PUTPAD(ctxt->c.b8[3]); PUTPAD(ctxt->c.b8[2]); ++ PUTPAD(ctxt->c.b8[1]); PUTPAD(ctxt->c.b8[0]); ++#endif ++} ++ ++void ++sha1_loop(ctxt, input, len) ++ struct sha1_ctxt *ctxt; ++ const u_int8_t *input; ++ size_t len; ++{ ++ size_t gaplen; ++ size_t gapstart; ++ size_t off; ++ size_t copysiz; ++ ++ off = 0; ++ ++ while (off < len) { ++ gapstart = COUNT % 64; ++ gaplen = 64 - gapstart; ++ ++ copysiz = (gaplen < len - off) ? gaplen : len - off; ++ bcopy(&input[off], &ctxt->m.b8[gapstart], copysiz); ++ COUNT += copysiz; ++ COUNT %= 64; ++ ctxt->c.b64[0] += copysiz * 8; ++ if (COUNT % 64 == 0) ++ sha1_step(ctxt); ++ off += copysiz; ++ } ++} ++ ++void ++sha1_result(ctxt, digest0) ++ struct sha1_ctxt *ctxt; ++ caddr_t digest0; ++{ ++ u_int8_t *digest; ++ ++ digest = (u_int8_t *)digest0; ++ sha1_pad(ctxt); ++#if BYTE_ORDER == BIG_ENDIAN ++ bcopy(&ctxt->h.b8[0], digest, 20); ++#else ++ digest[0] = ctxt->h.b8[3]; digest[1] = ctxt->h.b8[2]; ++ digest[2] = ctxt->h.b8[1]; digest[3] = ctxt->h.b8[0]; ++ digest[4] = ctxt->h.b8[7]; digest[5] = ctxt->h.b8[6]; ++ digest[6] = ctxt->h.b8[5]; digest[7] = ctxt->h.b8[4]; ++ digest[8] = ctxt->h.b8[11]; digest[9] = ctxt->h.b8[10]; ++ digest[10] = ctxt->h.b8[9]; digest[11] = ctxt->h.b8[8]; ++ digest[12] = ctxt->h.b8[15]; digest[13] = ctxt->h.b8[14]; ++ digest[14] = ctxt->h.b8[13]; digest[15] = ctxt->h.b8[12]; ++ digest[16] = ctxt->h.b8[19]; digest[17] = ctxt->h.b8[18]; ++ digest[18] = ctxt->h.b8[17]; digest[19] = ctxt->h.b8[16]; ++#endif ++} ++ ++#endif /*unsupported*/ +diff -Nur linux-3.1.4.orig/crypto/ocf/safe/sha1.h linux-3.1.4/crypto/ocf/safe/sha1.h +--- linux-3.1.4.orig/crypto/ocf/safe/sha1.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/safe/sha1.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,72 @@ ++/* $FreeBSD: src/sys/crypto/sha1.h,v 1.8 2002/03/20 05:13:50 alfred Exp $ */ ++/* $KAME: sha1.h,v 1.5 2000/03/27 04:36:23 sumikawa Exp $ */ ++ ++/* ++ * Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. Neither the name of the project nor the names of its contributors ++ * may be used to endorse or promote products derived from this software ++ * without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND ++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE ++ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ++ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ++ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF ++ * SUCH DAMAGE. ++ */ ++/* ++ * FIPS pub 180-1: Secure Hash Algorithm (SHA-1) ++ * based on: http://csrc.nist.gov/fips/fip180-1.txt ++ * implemented by Jun-ichiro itojun Itoh ++ */ ++ ++#ifndef _NETINET6_SHA1_H_ ++#define _NETINET6_SHA1_H_ ++ ++struct sha1_ctxt { ++ union { ++ u_int8_t b8[20]; ++ u_int32_t b32[5]; ++ } h; ++ union { ++ u_int8_t b8[8]; ++ u_int64_t b64[1]; ++ } c; ++ union { ++ u_int8_t b8[64]; ++ u_int32_t b32[16]; ++ } m; ++ u_int8_t count; ++}; ++ ++#ifdef __KERNEL__ ++extern void sha1_init(struct sha1_ctxt *); ++extern void sha1_pad(struct sha1_ctxt *); ++extern void sha1_loop(struct sha1_ctxt *, const u_int8_t *, size_t); ++extern void sha1_result(struct sha1_ctxt *, caddr_t); ++ ++/* compatibilty with other SHA1 source codes */ ++typedef struct sha1_ctxt SHA1_CTX; ++#define SHA1Init(x) sha1_init((x)) ++#define SHA1Update(x, y, z) sha1_loop((x), (y), (z)) ++#define SHA1Final(x, y) sha1_result((y), (x)) ++#endif /* __KERNEL__ */ ++ ++#define SHA1_RESULTLEN (160/8) ++ ++#endif /*_NETINET6_SHA1_H_*/ +diff -Nur linux-3.1.4.orig/crypto/ocf/talitos/Makefile linux-3.1.4/crypto/ocf/talitos/Makefile +--- linux-3.1.4.orig/crypto/ocf/talitos/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/talitos/Makefile 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,12 @@ ++# for SGlinux builds ++-include $(ROOTDIR)/modules/.config ++ ++obj-$(CONFIG_OCF_TALITOS) += talitos.o ++ ++obj ?= . ++EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ ++ ++ifdef TOPDIR ++-include $(TOPDIR)/Rules.make ++endif ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/talitos/talitos.c linux-3.1.4/crypto/ocf/talitos/talitos.c +--- linux-3.1.4.orig/crypto/ocf/talitos/talitos.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/talitos/talitos.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,1355 @@ ++/* ++ * crypto/ocf/talitos/talitos.c ++ * ++ * An OCF-Linux module that uses Freescale's SEC to do the crypto. ++ * Based on crypto/ocf/hifn and crypto/ocf/safe OCF drivers ++ * ++ * Copyright (c) 2006 Freescale Semiconductor, Inc. ++ * ++ * This code written by Kim A. B. Phillips ++ * some code copied from files with the following: ++ * Copyright (C) 2004-2007 David McCullough ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * --------------------------------------------------------------------------- ++ * ++ * NOTES: ++ * ++ * The Freescale SEC (also known as 'talitos') resides on the ++ * internal bus, and runs asynchronous to the processor core. It has ++ * a wide gamut of cryptographic acceleration features, including single- ++ * pass IPsec (also known as algorithm chaining). To properly utilize ++ * all of the SEC's performance enhancing features, further reworking ++ * of higher level code (framework, applications) will be necessary. ++ * ++ * The following table shows which SEC version is present in which devices: ++ * ++ * Devices SEC version ++ * ++ * 8272, 8248 SEC 1.0 ++ * 885, 875 SEC 1.2 ++ * 8555E, 8541E SEC 2.0 ++ * 8349E SEC 2.01 ++ * 8548E SEC 2.1 ++ * ++ * The following table shows the features offered by each SEC version: ++ * ++ * Max. chan- ++ * version Bus I/F Clock nels DEU AESU AFEU MDEU PKEU RNG KEU ++ * ++ * SEC 1.0 internal 64b 100MHz 4 1 1 1 1 1 1 0 ++ * SEC 1.2 internal 32b 66MHz 1 1 1 0 1 0 0 0 ++ * SEC 2.0 internal 64b 166MHz 4 1 1 1 1 1 1 0 ++ * SEC 2.01 internal 64b 166MHz 4 1 1 1 1 1 1 0 ++ * SEC 2.1 internal 64b 333MHz 4 1 1 1 1 1 1 1 ++ * ++ * Each execution unit in the SEC has two modes of execution; channel and ++ * slave/debug. This driver employs the channel infrastructure in the ++ * device for convenience. Only the RNG is directly accessed due to the ++ * convenience of its random fifo pool. The relationship between the ++ * channels and execution units is depicted in the following diagram: ++ * ++ * ------- ------------ ++ * ---| ch0 |---| | ++ * ------- | | ++ * | |------+-------+-------+-------+------------ ++ * ------- | | | | | | | ++ * ---| ch1 |---| | | | | | | ++ * ------- | | ------ ------ ------ ------ ------ ++ * |controller| |DEU | |AESU| |MDEU| |PKEU| ... |RNG | ++ * ------- | | ------ ------ ------ ------ ------ ++ * ---| ch2 |---| | | | | | | ++ * ------- | | | | | | | ++ * | |------+-------+-------+-------+------------ ++ * ------- | | ++ * ---| ch3 |---| | ++ * ------- ------------ ++ * ++ * Channel ch0 may drive an aes operation to the aes unit (AESU), ++ * and, at the same time, ch1 may drive a message digest operation ++ * to the mdeu. Each channel has an input descriptor FIFO, and the ++ * FIFO can contain, e.g. on the 8541E, up to 24 entries, before a ++ * a buffer overrun error is triggered. The controller is responsible ++ * for fetching the data from descriptor pointers, and passing the ++ * data to the appropriate EUs. The controller also writes the ++ * cryptographic operation's result to memory. The SEC notifies ++ * completion by triggering an interrupt and/or setting the 1st byte ++ * of the hdr field to 0xff. ++ * ++ * TODO: ++ * o support more algorithms ++ * o support more versions of the SEC ++ * o add support for linux 2.4 ++ * o scatter-gather (sg) support ++ * o add support for public key ops (PKEU) ++ * o add statistics ++ */ ++ ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) && !defined(AUTOCONF_INCLUDED) ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include /* dma_map_single() */ ++#include ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,15) ++#include ++#endif ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) ++#include ++#endif ++ ++#include ++#include ++ ++#define DRV_NAME "talitos" ++ ++#include "talitos_dev.h" ++#include "talitos_soft.h" ++ ++#define read_random(p,l) get_random_bytes(p,l) ++ ++const char talitos_driver_name[] = "Talitos OCF"; ++const char talitos_driver_version[] = "0.2"; ++ ++static int talitos_newsession(device_t dev, u_int32_t *sidp, ++ struct cryptoini *cri); ++static int talitos_freesession(device_t dev, u_int64_t tid); ++static int talitos_process(device_t dev, struct cryptop *crp, int hint); ++static void dump_talitos_status(struct talitos_softc *sc); ++static int talitos_submit(struct talitos_softc *sc, struct talitos_desc *td, ++ int chsel); ++static void talitos_doneprocessing(struct talitos_softc *sc); ++static void talitos_init_device(struct talitos_softc *sc); ++static void talitos_reset_device_master(struct talitos_softc *sc); ++static void talitos_reset_device(struct talitos_softc *sc); ++static void talitos_errorprocessing(struct talitos_softc *sc); ++#ifdef CONFIG_PPC_MERGE ++static int talitos_probe(struct of_device *ofdev, const struct of_device_id *match); ++static int talitos_remove(struct of_device *ofdev); ++#else ++static int talitos_probe(struct platform_device *pdev); ++static int talitos_remove(struct platform_device *pdev); ++#endif ++#ifdef CONFIG_OCF_RANDOMHARVEST ++static int talitos_read_random(void *arg, u_int32_t *buf, int maxwords); ++static void talitos_rng_init(struct talitos_softc *sc); ++#endif ++ ++static device_method_t talitos_methods = { ++ /* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, talitos_newsession), ++ DEVMETHOD(cryptodev_freesession,talitos_freesession), ++ DEVMETHOD(cryptodev_process, talitos_process), ++}; ++ ++#define debug talitos_debug ++int talitos_debug = 0; ++module_param(talitos_debug, int, 0644); ++MODULE_PARM_DESC(talitos_debug, "Enable debug"); ++ ++static inline void talitos_write(volatile unsigned *addr, u32 val) ++{ ++ out_be32(addr, val); ++} ++ ++static inline u32 talitos_read(volatile unsigned *addr) ++{ ++ u32 val; ++ val = in_be32(addr); ++ return val; ++} ++ ++static void dump_talitos_status(struct talitos_softc *sc) ++{ ++ unsigned int v, v_hi, i, *ptr; ++ v = talitos_read(sc->sc_base_addr + TALITOS_MCR); ++ v_hi = talitos_read(sc->sc_base_addr + TALITOS_MCR_HI); ++ printk(KERN_INFO "%s: MCR 0x%08x_%08x\n", ++ device_get_nameunit(sc->sc_cdev), v, v_hi); ++ v = talitos_read(sc->sc_base_addr + TALITOS_IMR); ++ v_hi = talitos_read(sc->sc_base_addr + TALITOS_IMR_HI); ++ printk(KERN_INFO "%s: IMR 0x%08x_%08x\n", ++ device_get_nameunit(sc->sc_cdev), v, v_hi); ++ v = talitos_read(sc->sc_base_addr + TALITOS_ISR); ++ v_hi = talitos_read(sc->sc_base_addr + TALITOS_ISR_HI); ++ printk(KERN_INFO "%s: ISR 0x%08x_%08x\n", ++ device_get_nameunit(sc->sc_cdev), v, v_hi); ++ for (i = 0; i < sc->sc_num_channels; i++) { ++ v = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + ++ TALITOS_CH_CDPR); ++ v_hi = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + ++ TALITOS_CH_CDPR_HI); ++ printk(KERN_INFO "%s: CDPR ch%d 0x%08x_%08x\n", ++ device_get_nameunit(sc->sc_cdev), i, v, v_hi); ++ } ++ for (i = 0; i < sc->sc_num_channels; i++) { ++ v = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + ++ TALITOS_CH_CCPSR); ++ v_hi = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + ++ TALITOS_CH_CCPSR_HI); ++ printk(KERN_INFO "%s: CCPSR ch%d 0x%08x_%08x\n", ++ device_get_nameunit(sc->sc_cdev), i, v, v_hi); ++ } ++ ptr = sc->sc_base_addr + TALITOS_CH_DESCBUF; ++ for (i = 0; i < 16; i++) { ++ v = talitos_read(ptr++); v_hi = talitos_read(ptr++); ++ printk(KERN_INFO "%s: DESCBUF ch0 0x%08x_%08x (tdp%02d)\n", ++ device_get_nameunit(sc->sc_cdev), v, v_hi, i); ++ } ++ return; ++} ++ ++ ++#ifdef CONFIG_OCF_RANDOMHARVEST ++/* ++ * pull random numbers off the RNG FIFO, not exceeding amount available ++ */ ++static int ++talitos_read_random(void *arg, u_int32_t *buf, int maxwords) ++{ ++ struct talitos_softc *sc = (struct talitos_softc *) arg; ++ int rc; ++ u_int32_t v; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ /* check for things like FIFO underflow */ ++ v = talitos_read(sc->sc_base_addr + TALITOS_RNGISR_HI); ++ if (unlikely(v)) { ++ printk(KERN_ERR "%s: RNGISR_HI error %08x\n", ++ device_get_nameunit(sc->sc_cdev), v); ++ return 0; ++ } ++ /* ++ * OFL is number of available 64-bit words, ++ * shift and convert to a 32-bit word count ++ */ ++ v = talitos_read(sc->sc_base_addr + TALITOS_RNGSR_HI); ++ v = (v & TALITOS_RNGSR_HI_OFL) >> (16 - 1); ++ if (maxwords > v) ++ maxwords = v; ++ for (rc = 0; rc < maxwords; rc++) { ++ buf[rc] = talitos_read(sc->sc_base_addr + ++ TALITOS_RNG_FIFO + rc*sizeof(u_int32_t)); ++ } ++ if (maxwords & 1) { ++ /* ++ * RNG will complain with an AE in the RNGISR ++ * if we don't complete the pairs of 32-bit reads ++ * to its 64-bit register based FIFO ++ */ ++ v = talitos_read(sc->sc_base_addr + ++ TALITOS_RNG_FIFO + rc*sizeof(u_int32_t)); ++ } ++ ++ return rc; ++} ++ ++static void ++talitos_rng_init(struct talitos_softc *sc) ++{ ++ u_int32_t v; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ /* reset RNG EU */ ++ v = talitos_read(sc->sc_base_addr + TALITOS_RNGRCR_HI); ++ v |= TALITOS_RNGRCR_HI_SR; ++ talitos_write(sc->sc_base_addr + TALITOS_RNGRCR_HI, v); ++ while ((talitos_read(sc->sc_base_addr + TALITOS_RNGSR_HI) ++ & TALITOS_RNGSR_HI_RD) == 0) ++ cpu_relax(); ++ /* ++ * we tell the RNG to start filling the RNG FIFO ++ * by writing the RNGDSR ++ */ ++ v = talitos_read(sc->sc_base_addr + TALITOS_RNGDSR_HI); ++ talitos_write(sc->sc_base_addr + TALITOS_RNGDSR_HI, v); ++ /* ++ * 64 bits of data will be pushed onto the FIFO every ++ * 256 SEC cycles until the FIFO is full. The RNG then ++ * attempts to keep the FIFO full. ++ */ ++ v = talitos_read(sc->sc_base_addr + TALITOS_RNGISR_HI); ++ if (v) { ++ printk(KERN_ERR "%s: RNGISR_HI error %08x\n", ++ device_get_nameunit(sc->sc_cdev), v); ++ return; ++ } ++ /* ++ * n.b. we need to add a FIPS test here - if the RNG is going ++ * to fail, it's going to fail at reset time ++ */ ++ return; ++} ++#endif /* CONFIG_OCF_RANDOMHARVEST */ ++ ++/* ++ * Generate a new software session. ++ */ ++static int ++talitos_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) ++{ ++ struct cryptoini *c, *encini = NULL, *macini = NULL; ++ struct talitos_softc *sc = device_get_softc(dev); ++ struct talitos_session *ses = NULL; ++ int sesn; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ if (sidp == NULL || cri == NULL || sc == NULL) { ++ DPRINTF("%s,%d - EINVAL\n", __FILE__, __LINE__); ++ return EINVAL; ++ } ++ for (c = cri; c != NULL; c = c->cri_next) { ++ if (c->cri_alg == CRYPTO_MD5 || ++ c->cri_alg == CRYPTO_MD5_HMAC || ++ c->cri_alg == CRYPTO_SHA1 || ++ c->cri_alg == CRYPTO_SHA1_HMAC || ++ c->cri_alg == CRYPTO_NULL_HMAC) { ++ if (macini) ++ return EINVAL; ++ macini = c; ++ } else if (c->cri_alg == CRYPTO_DES_CBC || ++ c->cri_alg == CRYPTO_3DES_CBC || ++ c->cri_alg == CRYPTO_AES_CBC || ++ c->cri_alg == CRYPTO_NULL_CBC) { ++ if (encini) ++ return EINVAL; ++ encini = c; ++ } else { ++ DPRINTF("UNKNOWN c->cri_alg %d\n", encini->cri_alg); ++ return EINVAL; ++ } ++ } ++ if (encini == NULL && macini == NULL) ++ return EINVAL; ++ if (encini) { ++ /* validate key length */ ++ switch (encini->cri_alg) { ++ case CRYPTO_DES_CBC: ++ if (encini->cri_klen != 64) ++ return EINVAL; ++ break; ++ case CRYPTO_3DES_CBC: ++ if (encini->cri_klen != 192) { ++ return EINVAL; ++ } ++ break; ++ case CRYPTO_AES_CBC: ++ if (encini->cri_klen != 128 && ++ encini->cri_klen != 192 && ++ encini->cri_klen != 256) ++ return EINVAL; ++ break; ++ default: ++ DPRINTF("UNKNOWN encini->cri_alg %d\n", ++ encini->cri_alg); ++ return EINVAL; ++ } ++ } ++ ++ if (sc->sc_sessions == NULL) { ++ ses = sc->sc_sessions = (struct talitos_session *) ++ kmalloc(sizeof(struct talitos_session), SLAB_ATOMIC); ++ if (ses == NULL) ++ return ENOMEM; ++ memset(ses, 0, sizeof(struct talitos_session)); ++ sesn = 0; ++ sc->sc_nsessions = 1; ++ } else { ++ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { ++ if (sc->sc_sessions[sesn].ses_used == 0) { ++ ses = &sc->sc_sessions[sesn]; ++ break; ++ } ++ } ++ ++ if (ses == NULL) { ++ /* allocating session */ ++ sesn = sc->sc_nsessions; ++ ses = (struct talitos_session *) kmalloc( ++ (sesn + 1) * sizeof(struct talitos_session), ++ SLAB_ATOMIC); ++ if (ses == NULL) ++ return ENOMEM; ++ memset(ses, 0, ++ (sesn + 1) * sizeof(struct talitos_session)); ++ memcpy(ses, sc->sc_sessions, ++ sesn * sizeof(struct talitos_session)); ++ memset(sc->sc_sessions, 0, ++ sesn * sizeof(struct talitos_session)); ++ kfree(sc->sc_sessions); ++ sc->sc_sessions = ses; ++ ses = &sc->sc_sessions[sesn]; ++ sc->sc_nsessions++; ++ } ++ } ++ ++ ses->ses_used = 1; ++ ++ if (encini) { ++ ses->ses_klen = (encini->cri_klen + 7) / 8; ++ memcpy(ses->ses_key, encini->cri_key, ses->ses_klen); ++ if (macini) { ++ /* doing hash on top of cipher */ ++ ses->ses_hmac_len = (macini->cri_klen + 7) / 8; ++ memcpy(ses->ses_hmac, macini->cri_key, ++ ses->ses_hmac_len); ++ } ++ } else if (macini) { ++ /* doing hash */ ++ ses->ses_klen = (macini->cri_klen + 7) / 8; ++ memcpy(ses->ses_key, macini->cri_key, ses->ses_klen); ++ } ++ ++ /* back compat way of determining MSC result len */ ++ if (macini) { ++ ses->ses_mlen = macini->cri_mlen; ++ if (ses->ses_mlen == 0) { ++ if (macini->cri_alg == CRYPTO_MD5_HMAC) ++ ses->ses_mlen = MD5_HASH_LEN; ++ else ++ ses->ses_mlen = SHA1_HASH_LEN; ++ } ++ } ++ ++ /* really should make up a template td here, ++ * and only fill things like i/o and direction in process() */ ++ ++ /* assign session ID */ ++ *sidp = TALITOS_SID(sc->sc_num, sesn); ++ return 0; ++} ++ ++/* ++ * Deallocate a session. ++ */ ++static int ++talitos_freesession(device_t dev, u_int64_t tid) ++{ ++ struct talitos_softc *sc = device_get_softc(dev); ++ int session, ret; ++ u_int32_t sid = ((u_int32_t) tid) & 0xffffffff; ++ ++ if (sc == NULL) ++ return EINVAL; ++ session = TALITOS_SESSION(sid); ++ if (session < sc->sc_nsessions) { ++ memset(&sc->sc_sessions[session], 0, ++ sizeof(sc->sc_sessions[session])); ++ ret = 0; ++ } else ++ ret = EINVAL; ++ return ret; ++} ++ ++/* ++ * launch device processing - it will come back with done notification ++ * in the form of an interrupt and/or HDR_DONE_BITS in header ++ */ ++static int ++talitos_submit( ++ struct talitos_softc *sc, ++ struct talitos_desc *td, ++ int chsel) ++{ ++ u_int32_t v; ++ ++ v = dma_map_single(NULL, td, sizeof(*td), DMA_TO_DEVICE); ++ talitos_write(sc->sc_base_addr + ++ chsel*TALITOS_CH_OFFSET + TALITOS_CH_FF, 0); ++ talitos_write(sc->sc_base_addr + ++ chsel*TALITOS_CH_OFFSET + TALITOS_CH_FF_HI, v); ++ return 0; ++} ++ ++static int ++talitos_process(device_t dev, struct cryptop *crp, int hint) ++{ ++ int i, err = 0, ivsize; ++ struct talitos_softc *sc = device_get_softc(dev); ++ struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; ++ caddr_t iv; ++ struct talitos_session *ses; ++ struct talitos_desc *td; ++ unsigned long flags; ++ /* descriptor mappings */ ++ int hmac_key, hmac_data, cipher_iv, cipher_key, ++ in_fifo, out_fifo, cipher_iv_out; ++ static int chsel = -1; ++ u_int32_t rand_iv[4]; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { ++ return EINVAL; ++ } ++ crp->crp_etype = 0; ++ if (TALITOS_SESSION(crp->crp_sid) >= sc->sc_nsessions) { ++ return EINVAL; ++ } ++ ++ ses = &sc->sc_sessions[TALITOS_SESSION(crp->crp_sid)]; ++ ++ /* enter the channel scheduler */ ++ spin_lock_irqsave(&sc->sc_chnfifolock[sc->sc_num_channels], flags); ++ ++ /* reuse channel that already had/has requests for the required EU */ ++ for (i = 0; i < sc->sc_num_channels; i++) { ++ if (sc->sc_chnlastalg[i] == crp->crp_desc->crd_alg) ++ break; ++ } ++ if (i == sc->sc_num_channels) { ++ /* ++ * haven't seen this algo the last sc_num_channels or more ++ * use round robin in this case ++ * nb: sc->sc_num_channels must be power of 2 ++ */ ++ chsel = (chsel + 1) & (sc->sc_num_channels - 1); ++ } else { ++ /* ++ * matches channel with same target execution unit; ++ * use same channel in this case ++ */ ++ chsel = i; ++ } ++ sc->sc_chnlastalg[chsel] = crp->crp_desc->crd_alg; ++ ++ /* release the channel scheduler lock */ ++ spin_unlock_irqrestore(&sc->sc_chnfifolock[sc->sc_num_channels], flags); ++ ++ /* acquire the selected channel fifo lock */ ++ spin_lock_irqsave(&sc->sc_chnfifolock[chsel], flags); ++ ++ /* find and reserve next available descriptor-cryptop pair */ ++ for (i = 0; i < sc->sc_chfifo_len; i++) { ++ if (sc->sc_chnfifo[chsel][i].cf_desc.hdr == 0) { ++ /* ++ * ensure correct descriptor formation by ++ * avoiding inadvertently setting "optional" entries ++ * e.g. not using "optional" dptr2 for MD/HMAC descs ++ */ ++ memset(&sc->sc_chnfifo[chsel][i].cf_desc, ++ 0, sizeof(*td)); ++ /* reserve it with done notification request bit */ ++ sc->sc_chnfifo[chsel][i].cf_desc.hdr |= ++ TALITOS_DONE_NOTIFY; ++ break; ++ } ++ } ++ spin_unlock_irqrestore(&sc->sc_chnfifolock[chsel], flags); ++ ++ if (i == sc->sc_chfifo_len) { ++ /* fifo full */ ++ err = ERESTART; ++ goto errout; ++ } ++ ++ td = &sc->sc_chnfifo[chsel][i].cf_desc; ++ sc->sc_chnfifo[chsel][i].cf_crp = crp; ++ ++ crd1 = crp->crp_desc; ++ if (crd1 == NULL) { ++ err = EINVAL; ++ goto errout; ++ } ++ crd2 = crd1->crd_next; ++ /* prevent compiler warning */ ++ hmac_key = 0; ++ hmac_data = 0; ++ if (crd2 == NULL) { ++ td->hdr |= TD_TYPE_COMMON_NONSNOOP_NO_AFEU; ++ /* assign descriptor dword ptr mappings for this desc. type */ ++ cipher_iv = 1; ++ cipher_key = 2; ++ in_fifo = 3; ++ cipher_iv_out = 5; ++ if (crd1->crd_alg == CRYPTO_MD5_HMAC || ++ crd1->crd_alg == CRYPTO_SHA1_HMAC || ++ crd1->crd_alg == CRYPTO_SHA1 || ++ crd1->crd_alg == CRYPTO_MD5) { ++ out_fifo = 5; ++ maccrd = crd1; ++ enccrd = NULL; ++ } else if (crd1->crd_alg == CRYPTO_DES_CBC || ++ crd1->crd_alg == CRYPTO_3DES_CBC || ++ crd1->crd_alg == CRYPTO_AES_CBC || ++ crd1->crd_alg == CRYPTO_ARC4) { ++ out_fifo = 4; ++ maccrd = NULL; ++ enccrd = crd1; ++ } else { ++ DPRINTF("UNKNOWN crd1->crd_alg %d\n", crd1->crd_alg); ++ err = EINVAL; ++ goto errout; ++ } ++ } else { ++ if (sc->sc_desc_types & TALITOS_HAS_DT_IPSEC_ESP) { ++ td->hdr |= TD_TYPE_IPSEC_ESP; ++ } else { ++ DPRINTF("unimplemented: multiple descriptor ipsec\n"); ++ err = EINVAL; ++ goto errout; ++ } ++ /* assign descriptor dword ptr mappings for this desc. type */ ++ hmac_key = 0; ++ hmac_data = 1; ++ cipher_iv = 2; ++ cipher_key = 3; ++ in_fifo = 4; ++ out_fifo = 5; ++ cipher_iv_out = 6; ++ if ((crd1->crd_alg == CRYPTO_MD5_HMAC || ++ crd1->crd_alg == CRYPTO_SHA1_HMAC || ++ crd1->crd_alg == CRYPTO_MD5 || ++ crd1->crd_alg == CRYPTO_SHA1) && ++ (crd2->crd_alg == CRYPTO_DES_CBC || ++ crd2->crd_alg == CRYPTO_3DES_CBC || ++ crd2->crd_alg == CRYPTO_AES_CBC || ++ crd2->crd_alg == CRYPTO_ARC4) && ++ ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { ++ maccrd = crd1; ++ enccrd = crd2; ++ } else if ((crd1->crd_alg == CRYPTO_DES_CBC || ++ crd1->crd_alg == CRYPTO_ARC4 || ++ crd1->crd_alg == CRYPTO_3DES_CBC || ++ crd1->crd_alg == CRYPTO_AES_CBC) && ++ (crd2->crd_alg == CRYPTO_MD5_HMAC || ++ crd2->crd_alg == CRYPTO_SHA1_HMAC || ++ crd2->crd_alg == CRYPTO_MD5 || ++ crd2->crd_alg == CRYPTO_SHA1) && ++ (crd1->crd_flags & CRD_F_ENCRYPT)) { ++ enccrd = crd1; ++ maccrd = crd2; ++ } else { ++ /* We cannot order the SEC as requested */ ++ printk("%s: cannot do the order\n", ++ device_get_nameunit(sc->sc_cdev)); ++ err = EINVAL; ++ goto errout; ++ } ++ } ++ /* assign in_fifo and out_fifo based on input/output struct type */ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ /* using SKB buffers */ ++ struct sk_buff *skb = (struct sk_buff *)crp->crp_buf; ++ if (skb_shinfo(skb)->nr_frags) { ++ printk("%s: skb frags unimplemented\n", ++ device_get_nameunit(sc->sc_cdev)); ++ err = EINVAL; ++ goto errout; ++ } ++ td->ptr[in_fifo].ptr = dma_map_single(NULL, skb->data, ++ skb->len, DMA_TO_DEVICE); ++ td->ptr[in_fifo].len = skb->len; ++ td->ptr[out_fifo].ptr = dma_map_single(NULL, skb->data, ++ skb->len, DMA_TO_DEVICE); ++ td->ptr[out_fifo].len = skb->len; ++ td->ptr[hmac_data].ptr = dma_map_single(NULL, skb->data, ++ skb->len, DMA_TO_DEVICE); ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ /* using IOV buffers */ ++ struct uio *uiop = (struct uio *)crp->crp_buf; ++ if (uiop->uio_iovcnt > 1) { ++ printk("%s: iov frags unimplemented\n", ++ device_get_nameunit(sc->sc_cdev)); ++ err = EINVAL; ++ goto errout; ++ } ++ td->ptr[in_fifo].ptr = dma_map_single(NULL, ++ uiop->uio_iov->iov_base, crp->crp_ilen, DMA_TO_DEVICE); ++ td->ptr[in_fifo].len = crp->crp_ilen; ++ /* crp_olen is never set; always use crp_ilen */ ++ td->ptr[out_fifo].ptr = dma_map_single(NULL, ++ uiop->uio_iov->iov_base, ++ crp->crp_ilen, DMA_TO_DEVICE); ++ td->ptr[out_fifo].len = crp->crp_ilen; ++ } else { ++ /* using contig buffers */ ++ td->ptr[in_fifo].ptr = dma_map_single(NULL, ++ crp->crp_buf, crp->crp_ilen, DMA_TO_DEVICE); ++ td->ptr[in_fifo].len = crp->crp_ilen; ++ td->ptr[out_fifo].ptr = dma_map_single(NULL, ++ crp->crp_buf, crp->crp_ilen, DMA_TO_DEVICE); ++ td->ptr[out_fifo].len = crp->crp_ilen; ++ } ++ if (enccrd) { ++ switch (enccrd->crd_alg) { ++ case CRYPTO_3DES_CBC: ++ td->hdr |= TALITOS_MODE0_DEU_3DES; ++ /* FALLTHROUGH */ ++ case CRYPTO_DES_CBC: ++ td->hdr |= TALITOS_SEL0_DEU ++ | TALITOS_MODE0_DEU_CBC; ++ if (enccrd->crd_flags & CRD_F_ENCRYPT) ++ td->hdr |= TALITOS_MODE0_DEU_ENC; ++ ivsize = 2*sizeof(u_int32_t); ++ DPRINTF("%cDES ses %d ch %d len %d\n", ++ (td->hdr & TALITOS_MODE0_DEU_3DES)?'3':'1', ++ (u32)TALITOS_SESSION(crp->crp_sid), ++ chsel, td->ptr[in_fifo].len); ++ break; ++ case CRYPTO_AES_CBC: ++ td->hdr |= TALITOS_SEL0_AESU ++ | TALITOS_MODE0_AESU_CBC; ++ if (enccrd->crd_flags & CRD_F_ENCRYPT) ++ td->hdr |= TALITOS_MODE0_AESU_ENC; ++ ivsize = 4*sizeof(u_int32_t); ++ DPRINTF("AES ses %d ch %d len %d\n", ++ (u32)TALITOS_SESSION(crp->crp_sid), ++ chsel, td->ptr[in_fifo].len); ++ break; ++ default: ++ printk("%s: unimplemented enccrd->crd_alg %d\n", ++ device_get_nameunit(sc->sc_cdev), enccrd->crd_alg); ++ err = EINVAL; ++ goto errout; ++ } ++ /* ++ * Setup encrypt/decrypt state. When using basic ops ++ * we can't use an inline IV because hash/crypt offset ++ * must be from the end of the IV to the start of the ++ * crypt data and this leaves out the preceding header ++ * from the hash calculation. Instead we place the IV ++ * in the state record and set the hash/crypt offset to ++ * copy both the header+IV. ++ */ ++ if (enccrd->crd_flags & CRD_F_ENCRYPT) { ++ td->hdr |= TALITOS_DIR_OUTBOUND; ++ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) ++ iv = enccrd->crd_iv; ++ else ++ read_random((iv = (caddr_t) rand_iv), sizeof(rand_iv)); ++ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ enccrd->crd_inject, ivsize, iv); ++ } ++ } else { ++ td->hdr |= TALITOS_DIR_INBOUND; ++ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) { ++ iv = enccrd->crd_iv; ++ } else { ++ iv = (caddr_t) rand_iv; ++ crypto_copydata(crp->crp_flags, crp->crp_buf, ++ enccrd->crd_inject, ivsize, iv); ++ } ++ } ++ td->ptr[cipher_iv].ptr = dma_map_single(NULL, iv, ivsize, ++ DMA_TO_DEVICE); ++ td->ptr[cipher_iv].len = ivsize; ++ /* ++ * we don't need the cipher iv out length/pointer ++ * field to do ESP IPsec. Therefore we set the len field as 0, ++ * which tells the SEC not to do anything with this len/ptr ++ * field. Previously, when length/pointer as pointing to iv, ++ * it gave us corruption of packets. ++ */ ++ td->ptr[cipher_iv_out].len = 0; ++ } ++ if (enccrd && maccrd) { ++ /* this is ipsec only for now */ ++ td->hdr |= TALITOS_SEL1_MDEU ++ | TALITOS_MODE1_MDEU_INIT ++ | TALITOS_MODE1_MDEU_PAD; ++ switch (maccrd->crd_alg) { ++ case CRYPTO_MD5: ++ td->hdr |= TALITOS_MODE1_MDEU_MD5; ++ break; ++ case CRYPTO_MD5_HMAC: ++ td->hdr |= TALITOS_MODE1_MDEU_MD5_HMAC; ++ break; ++ case CRYPTO_SHA1: ++ td->hdr |= TALITOS_MODE1_MDEU_SHA1; ++ break; ++ case CRYPTO_SHA1_HMAC: ++ td->hdr |= TALITOS_MODE1_MDEU_SHA1_HMAC; ++ break; ++ default: ++ /* We cannot order the SEC as requested */ ++ printk("%s: cannot do the order\n", ++ device_get_nameunit(sc->sc_cdev)); ++ err = EINVAL; ++ goto errout; ++ } ++ if ((maccrd->crd_alg == CRYPTO_MD5_HMAC) || ++ (maccrd->crd_alg == CRYPTO_SHA1_HMAC)) { ++ /* ++ * The offset from hash data to the start of ++ * crypt data is the difference in the skips. ++ */ ++ /* ipsec only for now */ ++ td->ptr[hmac_key].ptr = dma_map_single(NULL, ++ ses->ses_hmac, ses->ses_hmac_len, DMA_TO_DEVICE); ++ td->ptr[hmac_key].len = ses->ses_hmac_len; ++ td->ptr[in_fifo].ptr += enccrd->crd_skip; ++ td->ptr[in_fifo].len = enccrd->crd_len; ++ td->ptr[out_fifo].ptr += enccrd->crd_skip; ++ td->ptr[out_fifo].len = enccrd->crd_len; ++ /* bytes of HMAC to postpend to ciphertext */ ++ td->ptr[out_fifo].extent = ses->ses_mlen; ++ td->ptr[hmac_data].ptr += maccrd->crd_skip; ++ td->ptr[hmac_data].len = enccrd->crd_skip - maccrd->crd_skip; ++ } ++ if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) { ++ printk("%s: CRD_F_KEY_EXPLICIT unimplemented\n", ++ device_get_nameunit(sc->sc_cdev)); ++ } ++ } ++ if (!enccrd && maccrd) { ++ /* single MD5 or SHA */ ++ td->hdr |= TALITOS_SEL0_MDEU ++ | TALITOS_MODE0_MDEU_INIT ++ | TALITOS_MODE0_MDEU_PAD; ++ switch (maccrd->crd_alg) { ++ case CRYPTO_MD5: ++ td->hdr |= TALITOS_MODE0_MDEU_MD5; ++ DPRINTF("MD5 ses %d ch %d len %d\n", ++ (u32)TALITOS_SESSION(crp->crp_sid), ++ chsel, td->ptr[in_fifo].len); ++ break; ++ case CRYPTO_MD5_HMAC: ++ td->hdr |= TALITOS_MODE0_MDEU_MD5_HMAC; ++ break; ++ case CRYPTO_SHA1: ++ td->hdr |= TALITOS_MODE0_MDEU_SHA1; ++ DPRINTF("SHA1 ses %d ch %d len %d\n", ++ (u32)TALITOS_SESSION(crp->crp_sid), ++ chsel, td->ptr[in_fifo].len); ++ break; ++ case CRYPTO_SHA1_HMAC: ++ td->hdr |= TALITOS_MODE0_MDEU_SHA1_HMAC; ++ break; ++ default: ++ /* We cannot order the SEC as requested */ ++ DPRINTF("cannot do the order\n"); ++ err = EINVAL; ++ goto errout; ++ } ++ ++ if (crp->crp_flags & CRYPTO_F_IOV) ++ td->ptr[out_fifo].ptr += maccrd->crd_inject; ++ ++ if ((maccrd->crd_alg == CRYPTO_MD5_HMAC) || ++ (maccrd->crd_alg == CRYPTO_SHA1_HMAC)) { ++ td->ptr[hmac_key].ptr = dma_map_single(NULL, ++ ses->ses_hmac, ses->ses_hmac_len, ++ DMA_TO_DEVICE); ++ td->ptr[hmac_key].len = ses->ses_hmac_len; ++ } ++ } ++ else { ++ /* using process key (session data has duplicate) */ ++ td->ptr[cipher_key].ptr = dma_map_single(NULL, ++ enccrd->crd_key, (enccrd->crd_klen + 7) / 8, ++ DMA_TO_DEVICE); ++ td->ptr[cipher_key].len = (enccrd->crd_klen + 7) / 8; ++ } ++ /* descriptor complete - GO! */ ++ return talitos_submit(sc, td, chsel); ++ ++errout: ++ if (err != ERESTART) { ++ crp->crp_etype = err; ++ crypto_done(crp); ++ } ++ return err; ++} ++ ++/* go through all channels descriptors, notifying OCF what has ++ * _and_hasn't_ successfully completed and reset the device ++ * (otherwise it's up to decoding desc hdrs!) ++ */ ++static void talitos_errorprocessing(struct talitos_softc *sc) ++{ ++ unsigned long flags; ++ int i, j; ++ ++ /* disable further scheduling until under control */ ++ spin_lock_irqsave(&sc->sc_chnfifolock[sc->sc_num_channels], flags); ++ ++ if (debug) dump_talitos_status(sc); ++ /* go through descriptors, try and salvage those successfully done, ++ * and EIO those that weren't ++ */ ++ for (i = 0; i < sc->sc_num_channels; i++) { ++ spin_lock_irqsave(&sc->sc_chnfifolock[i], flags); ++ for (j = 0; j < sc->sc_chfifo_len; j++) { ++ if (sc->sc_chnfifo[i][j].cf_desc.hdr) { ++ if ((sc->sc_chnfifo[i][j].cf_desc.hdr ++ & TALITOS_HDR_DONE_BITS) ++ != TALITOS_HDR_DONE_BITS) { ++ /* this one didn't finish */ ++ /* signify in crp->etype */ ++ sc->sc_chnfifo[i][j].cf_crp->crp_etype ++ = EIO; ++ } ++ } else ++ continue; /* free entry */ ++ /* either way, notify ocf */ ++ crypto_done(sc->sc_chnfifo[i][j].cf_crp); ++ /* and tag it available again ++ * ++ * memset to ensure correct descriptor formation by ++ * avoiding inadvertently setting "optional" entries ++ * e.g. not using "optional" dptr2 MD/HMAC processing ++ */ ++ memset(&sc->sc_chnfifo[i][j].cf_desc, ++ 0, sizeof(struct talitos_desc)); ++ } ++ spin_unlock_irqrestore(&sc->sc_chnfifolock[i], flags); ++ } ++ /* reset and initialize the SEC h/w device */ ++ talitos_reset_device(sc); ++ talitos_init_device(sc); ++#ifdef CONFIG_OCF_RANDOMHARVEST ++ if (sc->sc_exec_units & TALITOS_HAS_EU_RNG) ++ talitos_rng_init(sc); ++#endif ++ ++ /* Okay. Stand by. */ ++ spin_unlock_irqrestore(&sc->sc_chnfifolock[sc->sc_num_channels], flags); ++ ++ return; ++} ++ ++/* go through all channels descriptors, notifying OCF what's been done */ ++static void talitos_doneprocessing(struct talitos_softc *sc) ++{ ++ unsigned long flags; ++ int i, j; ++ ++ /* go through descriptors looking for done bits */ ++ for (i = 0; i < sc->sc_num_channels; i++) { ++ spin_lock_irqsave(&sc->sc_chnfifolock[i], flags); ++ for (j = 0; j < sc->sc_chfifo_len; j++) { ++ /* descriptor has done bits set? */ ++ if ((sc->sc_chnfifo[i][j].cf_desc.hdr ++ & TALITOS_HDR_DONE_BITS) ++ == TALITOS_HDR_DONE_BITS) { ++ /* notify ocf */ ++ crypto_done(sc->sc_chnfifo[i][j].cf_crp); ++ /* and tag it available again ++ * ++ * memset to ensure correct descriptor formation by ++ * avoiding inadvertently setting "optional" entries ++ * e.g. not using "optional" dptr2 MD/HMAC processing ++ */ ++ memset(&sc->sc_chnfifo[i][j].cf_desc, ++ 0, sizeof(struct talitos_desc)); ++ } ++ } ++ spin_unlock_irqrestore(&sc->sc_chnfifolock[i], flags); ++ } ++ return; ++} ++ ++static irqreturn_t ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19) ++talitos_intr(int irq, void *arg) ++#else ++talitos_intr(int irq, void *arg, struct pt_regs *regs) ++#endif ++{ ++ struct talitos_softc *sc = arg; ++ u_int32_t v, v_hi; ++ ++ /* ack */ ++ v = talitos_read(sc->sc_base_addr + TALITOS_ISR); ++ v_hi = talitos_read(sc->sc_base_addr + TALITOS_ISR_HI); ++ talitos_write(sc->sc_base_addr + TALITOS_ICR, v); ++ talitos_write(sc->sc_base_addr + TALITOS_ICR_HI, v_hi); ++ ++ if (unlikely(v & TALITOS_ISR_ERROR)) { ++ /* Okay, Houston, we've had a problem here. */ ++ printk(KERN_DEBUG "%s: got error interrupt - ISR 0x%08x_%08x\n", ++ device_get_nameunit(sc->sc_cdev), v, v_hi); ++ talitos_errorprocessing(sc); ++ } else ++ if (likely(v & TALITOS_ISR_DONE)) { ++ talitos_doneprocessing(sc); ++ } ++ return IRQ_HANDLED; ++} ++ ++/* ++ * Initialize registers we need to touch only once. ++ */ ++static void ++talitos_init_device(struct talitos_softc *sc) ++{ ++ u_int32_t v; ++ int i; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ /* init all channels */ ++ for (i = 0; i < sc->sc_num_channels; i++) { ++ v = talitos_read(sc->sc_base_addr + ++ i*TALITOS_CH_OFFSET + TALITOS_CH_CCCR_HI); ++ v |= TALITOS_CH_CCCR_HI_CDWE ++ | TALITOS_CH_CCCR_HI_CDIE; /* invoke interrupt if done */ ++ talitos_write(sc->sc_base_addr + ++ i*TALITOS_CH_OFFSET + TALITOS_CH_CCCR_HI, v); ++ } ++ /* enable all interrupts */ ++ v = talitos_read(sc->sc_base_addr + TALITOS_IMR); ++ v |= TALITOS_IMR_ALL; ++ talitos_write(sc->sc_base_addr + TALITOS_IMR, v); ++ v = talitos_read(sc->sc_base_addr + TALITOS_IMR_HI); ++ v |= TALITOS_IMR_HI_ERRONLY; ++ talitos_write(sc->sc_base_addr + TALITOS_IMR_HI, v); ++ return; ++} ++ ++/* ++ * set the master reset bit on the device. ++ */ ++static void ++talitos_reset_device_master(struct talitos_softc *sc) ++{ ++ u_int32_t v; ++ ++ /* Reset the device by writing 1 to MCR:SWR and waiting 'til cleared */ ++ v = talitos_read(sc->sc_base_addr + TALITOS_MCR); ++ talitos_write(sc->sc_base_addr + TALITOS_MCR, v | TALITOS_MCR_SWR); ++ ++ while (talitos_read(sc->sc_base_addr + TALITOS_MCR) & TALITOS_MCR_SWR) ++ cpu_relax(); ++ ++ return; ++} ++ ++/* ++ * Resets the device. Values in the registers are left as is ++ * from the reset (i.e. initial values are assigned elsewhere). ++ */ ++static void ++talitos_reset_device(struct talitos_softc *sc) ++{ ++ u_int32_t v; ++ int i; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ /* ++ * Master reset ++ * errata documentation: warning: certain SEC interrupts ++ * are not fully cleared by writing the MCR:SWR bit, ++ * set bit twice to completely reset ++ */ ++ talitos_reset_device_master(sc); /* once */ ++ talitos_reset_device_master(sc); /* and once again */ ++ ++ /* reset all channels */ ++ for (i = 0; i < sc->sc_num_channels; i++) { ++ v = talitos_read(sc->sc_base_addr + i*TALITOS_CH_OFFSET + ++ TALITOS_CH_CCCR); ++ talitos_write(sc->sc_base_addr + i*TALITOS_CH_OFFSET + ++ TALITOS_CH_CCCR, v | TALITOS_CH_CCCR_RESET); ++ } ++} ++ ++/* Set up the crypto device structure, private data, ++ * and anything else we need before we start */ ++#ifdef CONFIG_PPC_MERGE ++static int talitos_probe(struct of_device *ofdev, const struct of_device_id *match) ++#else ++static int talitos_probe(struct platform_device *pdev) ++#endif ++{ ++ struct talitos_softc *sc = NULL; ++ struct resource *r; ++#ifdef CONFIG_PPC_MERGE ++ struct device *device = &ofdev->dev; ++ struct device_node *np = ofdev->node; ++ const unsigned int *prop; ++ int err; ++ struct resource res; ++#endif ++ static int num_chips = 0; ++ int rc; ++ int i; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ ++ sc = (struct talitos_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); ++ if (!sc) ++ return -ENOMEM; ++ memset(sc, 0, sizeof(*sc)); ++ ++ softc_device_init(sc, DRV_NAME, num_chips, talitos_methods); ++ ++ sc->sc_irq = -1; ++ sc->sc_cid = -1; ++#ifndef CONFIG_PPC_MERGE ++ sc->sc_dev = pdev; ++#endif ++ sc->sc_num = num_chips++; ++ ++#ifdef CONFIG_PPC_MERGE ++ dev_set_drvdata(device, sc); ++#else ++ platform_set_drvdata(sc->sc_dev, sc); ++#endif ++ ++ /* get the irq line */ ++#ifdef CONFIG_PPC_MERGE ++ err = of_address_to_resource(np, 0, &res); ++ if (err) ++ return -EINVAL; ++ r = &res; ++ ++ sc->sc_irq = irq_of_parse_and_map(np, 0); ++#else ++ /* get a pointer to the register memory */ ++ r = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ ++ sc->sc_irq = platform_get_irq(pdev, 0); ++#endif ++ rc = request_irq(sc->sc_irq, talitos_intr, 0, ++ device_get_nameunit(sc->sc_cdev), sc); ++ if (rc) { ++ printk(KERN_ERR "%s: failed to hook irq %d\n", ++ device_get_nameunit(sc->sc_cdev), sc->sc_irq); ++ sc->sc_irq = -1; ++ goto out; ++ } ++ ++ sc->sc_base_addr = (ocf_iomem_t) ioremap(r->start, (r->end - r->start)); ++ if (!sc->sc_base_addr) { ++ printk(KERN_ERR "%s: failed to ioremap\n", ++ device_get_nameunit(sc->sc_cdev)); ++ goto out; ++ } ++ ++ /* figure out our SEC's properties and capabilities */ ++ sc->sc_chiprev = (u64)talitos_read(sc->sc_base_addr + TALITOS_ID) << 32 ++ | talitos_read(sc->sc_base_addr + TALITOS_ID_HI); ++ DPRINTF("sec id 0x%llx\n", sc->sc_chiprev); ++ ++#ifdef CONFIG_PPC_MERGE ++ /* get SEC properties from device tree, defaulting to SEC 2.0 */ ++ ++ prop = of_get_property(np, "num-channels", NULL); ++ sc->sc_num_channels = prop ? *prop : TALITOS_NCHANNELS_SEC_2_0; ++ ++ prop = of_get_property(np, "channel-fifo-len", NULL); ++ sc->sc_chfifo_len = prop ? *prop : TALITOS_CHFIFOLEN_SEC_2_0; ++ ++ prop = of_get_property(np, "exec-units-mask", NULL); ++ sc->sc_exec_units = prop ? *prop : TALITOS_HAS_EUS_SEC_2_0; ++ ++ prop = of_get_property(np, "descriptor-types-mask", NULL); ++ sc->sc_desc_types = prop ? *prop : TALITOS_HAS_DESCTYPES_SEC_2_0; ++#else ++ /* bulk should go away with openfirmware flat device tree support */ ++ if (sc->sc_chiprev & TALITOS_ID_SEC_2_0) { ++ sc->sc_num_channels = TALITOS_NCHANNELS_SEC_2_0; ++ sc->sc_chfifo_len = TALITOS_CHFIFOLEN_SEC_2_0; ++ sc->sc_exec_units = TALITOS_HAS_EUS_SEC_2_0; ++ sc->sc_desc_types = TALITOS_HAS_DESCTYPES_SEC_2_0; ++ } else { ++ printk(KERN_ERR "%s: failed to id device\n", ++ device_get_nameunit(sc->sc_cdev)); ++ goto out; ++ } ++#endif ++ ++ /* + 1 is for the meta-channel lock used by the channel scheduler */ ++ sc->sc_chnfifolock = (spinlock_t *) kmalloc( ++ (sc->sc_num_channels + 1) * sizeof(spinlock_t), GFP_KERNEL); ++ if (!sc->sc_chnfifolock) ++ goto out; ++ for (i = 0; i < sc->sc_num_channels + 1; i++) { ++ spin_lock_init(&sc->sc_chnfifolock[i]); ++ } ++ ++ sc->sc_chnlastalg = (int *) kmalloc( ++ sc->sc_num_channels * sizeof(int), GFP_KERNEL); ++ if (!sc->sc_chnlastalg) ++ goto out; ++ memset(sc->sc_chnlastalg, 0, sc->sc_num_channels * sizeof(int)); ++ ++ sc->sc_chnfifo = (struct desc_cryptop_pair **) kmalloc( ++ sc->sc_num_channels * sizeof(struct desc_cryptop_pair *), ++ GFP_KERNEL); ++ if (!sc->sc_chnfifo) ++ goto out; ++ for (i = 0; i < sc->sc_num_channels; i++) { ++ sc->sc_chnfifo[i] = (struct desc_cryptop_pair *) kmalloc( ++ sc->sc_chfifo_len * sizeof(struct desc_cryptop_pair), ++ GFP_KERNEL); ++ if (!sc->sc_chnfifo[i]) ++ goto out; ++ memset(sc->sc_chnfifo[i], 0, ++ sc->sc_chfifo_len * sizeof(struct desc_cryptop_pair)); ++ } ++ ++ /* reset and initialize the SEC h/w device */ ++ talitos_reset_device(sc); ++ talitos_init_device(sc); ++ ++ sc->sc_cid = crypto_get_driverid(softc_get_device(sc),CRYPTOCAP_F_HARDWARE); ++ if (sc->sc_cid < 0) { ++ printk(KERN_ERR "%s: could not get crypto driver id\n", ++ device_get_nameunit(sc->sc_cdev)); ++ goto out; ++ } ++ ++ /* register algorithms with the framework */ ++ printk("%s:", device_get_nameunit(sc->sc_cdev)); ++ ++ if (sc->sc_exec_units & TALITOS_HAS_EU_RNG) { ++ printk(" rng"); ++#ifdef CONFIG_OCF_RANDOMHARVEST ++ talitos_rng_init(sc); ++ crypto_rregister(sc->sc_cid, talitos_read_random, sc); ++#endif ++ } ++ if (sc->sc_exec_units & TALITOS_HAS_EU_DEU) { ++ printk(" des/3des"); ++ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); ++ } ++ if (sc->sc_exec_units & TALITOS_HAS_EU_AESU) { ++ printk(" aes"); ++ crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); ++ } ++ if (sc->sc_exec_units & TALITOS_HAS_EU_MDEU) { ++ printk(" md5"); ++ crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0); ++ /* HMAC support only with IPsec for now */ ++ crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); ++ printk(" sha1"); ++ crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0); ++ /* HMAC support only with IPsec for now */ ++ crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); ++ } ++ printk("\n"); ++ return 0; ++ ++out: ++#ifndef CONFIG_PPC_MERGE ++ talitos_remove(pdev); ++#endif ++ return -ENOMEM; ++} ++ ++#ifdef CONFIG_PPC_MERGE ++static int talitos_remove(struct of_device *ofdev) ++#else ++static int talitos_remove(struct platform_device *pdev) ++#endif ++{ ++#ifdef CONFIG_PPC_MERGE ++ struct talitos_softc *sc = dev_get_drvdata(&ofdev->dev); ++#else ++ struct talitos_softc *sc = platform_get_drvdata(pdev); ++#endif ++ int i; ++ ++ DPRINTF("%s()\n", __FUNCTION__); ++ if (sc->sc_cid >= 0) ++ crypto_unregister_all(sc->sc_cid); ++ if (sc->sc_chnfifo) { ++ for (i = 0; i < sc->sc_num_channels; i++) ++ if (sc->sc_chnfifo[i]) ++ kfree(sc->sc_chnfifo[i]); ++ kfree(sc->sc_chnfifo); ++ } ++ if (sc->sc_chnlastalg) ++ kfree(sc->sc_chnlastalg); ++ if (sc->sc_chnfifolock) ++ kfree(sc->sc_chnfifolock); ++ if (sc->sc_irq != -1) ++ free_irq(sc->sc_irq, sc); ++ if (sc->sc_base_addr) ++ iounmap((void *) sc->sc_base_addr); ++ kfree(sc); ++ return 0; ++} ++ ++#ifdef CONFIG_PPC_MERGE ++static struct of_device_id talitos_match[] = { ++ { ++ .type = "crypto", ++ .compatible = "talitos", ++ }, ++ {}, ++}; ++ ++MODULE_DEVICE_TABLE(of, talitos_match); ++ ++static struct of_platform_driver talitos_driver = { ++ .name = DRV_NAME, ++ .match_table = talitos_match, ++ .probe = talitos_probe, ++ .remove = talitos_remove, ++}; ++ ++static int __init talitos_init(void) ++{ ++ return of_register_platform_driver(&talitos_driver); ++} ++ ++static void __exit talitos_exit(void) ++{ ++ of_unregister_platform_driver(&talitos_driver); ++} ++#else ++/* Structure for a platform device driver */ ++static struct platform_driver talitos_driver = { ++ .probe = talitos_probe, ++ .remove = talitos_remove, ++ .driver = { ++ .name = "fsl-sec2", ++ } ++}; ++ ++static int __init talitos_init(void) ++{ ++ return platform_driver_register(&talitos_driver); ++} ++ ++static void __exit talitos_exit(void) ++{ ++ platform_driver_unregister(&talitos_driver); ++} ++#endif ++ ++module_init(talitos_init); ++module_exit(talitos_exit); ++ ++MODULE_LICENSE("Dual BSD/GPL"); ++MODULE_AUTHOR("kim.phillips@freescale.com"); ++MODULE_DESCRIPTION("OCF driver for Freescale SEC (talitos)"); +diff -Nur linux-3.1.4.orig/crypto/ocf/talitos/talitos_dev.h linux-3.1.4/crypto/ocf/talitos/talitos_dev.h +--- linux-3.1.4.orig/crypto/ocf/talitos/talitos_dev.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/talitos/talitos_dev.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,277 @@ ++/* ++ * Freescale SEC (talitos) device dependent data structures ++ * ++ * Copyright (c) 2006 Freescale Semiconductor, Inc. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ */ ++ ++/* device ID register values */ ++#define TALITOS_ID_SEC_2_0 0x40 ++#define TALITOS_ID_SEC_2_1 0x40 /* cross ref with IP block revision reg */ ++ ++/* ++ * following num_channels, channel-fifo-depth, exec-unit-mask, and ++ * descriptor-types-mask are for forward-compatibility with openfirmware ++ * flat device trees ++ */ ++ ++/* ++ * num_channels : the number of channels available in each SEC version. ++ */ ++ ++/* n.b. this driver requires these values be a power of 2 */ ++#define TALITOS_NCHANNELS_SEC_1_0 4 ++#define TALITOS_NCHANNELS_SEC_1_2 1 ++#define TALITOS_NCHANNELS_SEC_2_0 4 ++#define TALITOS_NCHANNELS_SEC_2_01 4 ++#define TALITOS_NCHANNELS_SEC_2_1 4 ++#define TALITOS_NCHANNELS_SEC_2_4 4 ++ ++/* ++ * channel-fifo-depth : The number of descriptor ++ * pointers a channel fetch fifo can hold. ++ */ ++#define TALITOS_CHFIFOLEN_SEC_1_0 1 ++#define TALITOS_CHFIFOLEN_SEC_1_2 1 ++#define TALITOS_CHFIFOLEN_SEC_2_0 24 ++#define TALITOS_CHFIFOLEN_SEC_2_01 24 ++#define TALITOS_CHFIFOLEN_SEC_2_1 24 ++#define TALITOS_CHFIFOLEN_SEC_2_4 24 ++ ++/* ++ * exec-unit-mask : The bitmask representing what Execution Units (EUs) ++ * are available. EU information should be encoded following the SEC's ++ * EU_SEL0 bitfield documentation, i.e. as follows: ++ * ++ * bit 31 = set if SEC permits no-EU selection (should be always set) ++ * bit 30 = set if SEC has the ARC4 EU (AFEU) ++ * bit 29 = set if SEC has the des/3des EU (DEU) ++ * bit 28 = set if SEC has the message digest EU (MDEU) ++ * bit 27 = set if SEC has the random number generator EU (RNG) ++ * bit 26 = set if SEC has the public key EU (PKEU) ++ * bit 25 = set if SEC has the aes EU (AESU) ++ * bit 24 = set if SEC has the Kasumi EU (KEU) ++ * ++ */ ++#define TALITOS_HAS_EU_NONE (1<<0) ++#define TALITOS_HAS_EU_AFEU (1<<1) ++#define TALITOS_HAS_EU_DEU (1<<2) ++#define TALITOS_HAS_EU_MDEU (1<<3) ++#define TALITOS_HAS_EU_RNG (1<<4) ++#define TALITOS_HAS_EU_PKEU (1<<5) ++#define TALITOS_HAS_EU_AESU (1<<6) ++#define TALITOS_HAS_EU_KEU (1<<7) ++ ++/* the corresponding masks for each SEC version */ ++#define TALITOS_HAS_EUS_SEC_1_0 0x7f ++#define TALITOS_HAS_EUS_SEC_1_2 0x4d ++#define TALITOS_HAS_EUS_SEC_2_0 0x7f ++#define TALITOS_HAS_EUS_SEC_2_01 0x7f ++#define TALITOS_HAS_EUS_SEC_2_1 0xff ++#define TALITOS_HAS_EUS_SEC_2_4 0x7f ++ ++/* ++ * descriptor-types-mask : The bitmask representing what descriptors ++ * are available. Descriptor type information should be encoded ++ * following the SEC's Descriptor Header Dword DESC_TYPE field ++ * documentation, i.e. as follows: ++ * ++ * bit 0 = set if SEC supports the aesu_ctr_nonsnoop desc. type ++ * bit 1 = set if SEC supports the ipsec_esp descriptor type ++ * bit 2 = set if SEC supports the common_nonsnoop desc. type ++ * bit 3 = set if SEC supports the 802.11i AES ccmp desc. type ++ * bit 4 = set if SEC supports the hmac_snoop_no_afeu desc. type ++ * bit 5 = set if SEC supports the srtp descriptor type ++ * bit 6 = set if SEC supports the non_hmac_snoop_no_afeu desc.type ++ * bit 7 = set if SEC supports the pkeu_assemble descriptor type ++ * bit 8 = set if SEC supports the aesu_key_expand_output desc.type ++ * bit 9 = set if SEC supports the pkeu_ptmul descriptor type ++ * bit 10 = set if SEC supports the common_nonsnoop_afeu desc. type ++ * bit 11 = set if SEC supports the pkeu_ptadd_dbl descriptor type ++ * ++ * ..and so on and so forth. ++ */ ++#define TALITOS_HAS_DT_AESU_CTR_NONSNOOP (1<<0) ++#define TALITOS_HAS_DT_IPSEC_ESP (1<<1) ++#define TALITOS_HAS_DT_COMMON_NONSNOOP (1<<2) ++ ++/* the corresponding masks for each SEC version */ ++#define TALITOS_HAS_DESCTYPES_SEC_2_0 0x01010ebf ++#define TALITOS_HAS_DESCTYPES_SEC_2_1 0x012b0ebf ++ ++/* ++ * a TALITOS_xxx_HI address points to the low data bits (32-63) of the register ++ */ ++ ++/* global register offset addresses */ ++#define TALITOS_ID 0x1020 ++#define TALITOS_ID_HI 0x1024 ++#define TALITOS_MCR 0x1030 /* master control register */ ++#define TALITOS_MCR_HI 0x1038 /* master control register */ ++#define TALITOS_MCR_SWR 0x1 ++#define TALITOS_IMR 0x1008 /* interrupt mask register */ ++#define TALITOS_IMR_ALL 0x00010fff /* enable all interrupts mask */ ++#define TALITOS_IMR_ERRONLY 0x00010aaa /* enable error interrupts */ ++#define TALITOS_IMR_HI 0x100C /* interrupt mask register */ ++#define TALITOS_IMR_HI_ALL 0x00323333 /* enable all interrupts mask */ ++#define TALITOS_IMR_HI_ERRONLY 0x00222222 /* enable error interrupts */ ++#define TALITOS_ISR 0x1010 /* interrupt status register */ ++#define TALITOS_ISR_ERROR 0x00010faa /* errors mask */ ++#define TALITOS_ISR_DONE 0x00000055 /* channel(s) done mask */ ++#define TALITOS_ISR_HI 0x1014 /* interrupt status register */ ++#define TALITOS_ICR 0x1018 /* interrupt clear register */ ++#define TALITOS_ICR_HI 0x101C /* interrupt clear register */ ++ ++/* channel register address stride */ ++#define TALITOS_CH_OFFSET 0x100 ++ ++/* channel register offset addresses and bits */ ++#define TALITOS_CH_CCCR 0x1108 /* Crypto-Channel Config Register */ ++#define TALITOS_CH_CCCR_RESET 0x1 /* Channel Reset bit */ ++#define TALITOS_CH_CCCR_HI 0x110c /* Crypto-Channel Config Register */ ++#define TALITOS_CH_CCCR_HI_CDWE 0x10 /* Channel done writeback enable bit */ ++#define TALITOS_CH_CCCR_HI_NT 0x4 /* Notification type bit */ ++#define TALITOS_CH_CCCR_HI_CDIE 0x2 /* Channel Done Interrupt Enable bit */ ++#define TALITOS_CH_CCPSR 0x1110 /* Crypto-Channel Pointer Status Reg */ ++#define TALITOS_CH_CCPSR_HI 0x1114 /* Crypto-Channel Pointer Status Reg */ ++#define TALITOS_CH_FF 0x1148 /* Fetch FIFO */ ++#define TALITOS_CH_FF_HI 0x114c /* Fetch FIFO's FETCH_ADRS */ ++#define TALITOS_CH_CDPR 0x1140 /* Crypto-Channel Pointer Status Reg */ ++#define TALITOS_CH_CDPR_HI 0x1144 /* Crypto-Channel Pointer Status Reg */ ++#define TALITOS_CH_DESCBUF 0x1180 /* (thru 11bf) Crypto-Channel ++ * Descriptor Buffer (debug) */ ++ ++/* execution unit register offset addresses and bits */ ++#define TALITOS_DEUSR 0x2028 /* DEU status register */ ++#define TALITOS_DEUSR_HI 0x202c /* DEU status register */ ++#define TALITOS_DEUISR 0x2030 /* DEU interrupt status register */ ++#define TALITOS_DEUISR_HI 0x2034 /* DEU interrupt status register */ ++#define TALITOS_DEUICR 0x2038 /* DEU interrupt control register */ ++#define TALITOS_DEUICR_HI 0x203c /* DEU interrupt control register */ ++#define TALITOS_AESUISR 0x4030 /* AESU interrupt status register */ ++#define TALITOS_AESUISR_HI 0x4034 /* AESU interrupt status register */ ++#define TALITOS_AESUICR 0x4038 /* AESU interrupt control register */ ++#define TALITOS_AESUICR_HI 0x403c /* AESU interrupt control register */ ++#define TALITOS_MDEUISR 0x6030 /* MDEU interrupt status register */ ++#define TALITOS_MDEUISR_HI 0x6034 /* MDEU interrupt status register */ ++#define TALITOS_RNGSR 0xa028 /* RNG status register */ ++#define TALITOS_RNGSR_HI 0xa02c /* RNG status register */ ++#define TALITOS_RNGSR_HI_RD 0x1 /* RNG Reset done */ ++#define TALITOS_RNGSR_HI_OFL 0xff0000/* number of dwords in RNG output FIFO*/ ++#define TALITOS_RNGDSR 0xa010 /* RNG data size register */ ++#define TALITOS_RNGDSR_HI 0xa014 /* RNG data size register */ ++#define TALITOS_RNG_FIFO 0xa800 /* RNG FIFO - pool of random numbers */ ++#define TALITOS_RNGISR 0xa030 /* RNG Interrupt status register */ ++#define TALITOS_RNGISR_HI 0xa034 /* RNG Interrupt status register */ ++#define TALITOS_RNGRCR 0xa018 /* RNG Reset control register */ ++#define TALITOS_RNGRCR_HI 0xa01c /* RNG Reset control register */ ++#define TALITOS_RNGRCR_HI_SR 0x1 /* RNG RNGRCR:Software Reset */ ++ ++/* descriptor pointer entry */ ++struct talitos_desc_ptr { ++ u16 len; /* length */ ++ u8 extent; /* jump (to s/g link table) and extent */ ++ u8 res; /* reserved */ ++ u32 ptr; /* pointer */ ++}; ++ ++/* descriptor */ ++struct talitos_desc { ++ u32 hdr; /* header */ ++ u32 res; /* reserved */ ++ struct talitos_desc_ptr ptr[7]; /* ptr/len pair array */ ++}; ++ ++/* talitos descriptor header (hdr) bits */ ++ ++/* primary execution unit select */ ++#define TALITOS_SEL0_AFEU 0x10000000 ++#define TALITOS_SEL0_DEU 0x20000000 ++#define TALITOS_SEL0_MDEU 0x30000000 ++#define TALITOS_SEL0_RNG 0x40000000 ++#define TALITOS_SEL0_PKEU 0x50000000 ++#define TALITOS_SEL0_AESU 0x60000000 ++ ++/* primary execution unit mode (MODE0) and derivatives */ ++#define TALITOS_MODE0_AESU_CBC 0x00200000 ++#define TALITOS_MODE0_AESU_ENC 0x00100000 ++#define TALITOS_MODE0_DEU_CBC 0x00400000 ++#define TALITOS_MODE0_DEU_3DES 0x00200000 ++#define TALITOS_MODE0_DEU_ENC 0x00100000 ++#define TALITOS_MODE0_MDEU_INIT 0x01000000 /* init starting regs */ ++#define TALITOS_MODE0_MDEU_HMAC 0x00800000 ++#define TALITOS_MODE0_MDEU_PAD 0x00400000 /* PD */ ++#define TALITOS_MODE0_MDEU_MD5 0x00200000 ++#define TALITOS_MODE0_MDEU_SHA256 0x00100000 ++#define TALITOS_MODE0_MDEU_SHA1 0x00000000 /* SHA-160 */ ++#define TALITOS_MODE0_MDEU_MD5_HMAC \ ++ (TALITOS_MODE0_MDEU_MD5 | TALITOS_MODE0_MDEU_HMAC) ++#define TALITOS_MODE0_MDEU_SHA256_HMAC \ ++ (TALITOS_MODE0_MDEU_SHA256 | TALITOS_MODE0_MDEU_HMAC) ++#define TALITOS_MODE0_MDEU_SHA1_HMAC \ ++ (TALITOS_MODE0_MDEU_SHA1 | TALITOS_MODE0_MDEU_HMAC) ++ ++/* secondary execution unit select (SEL1) */ ++/* it's MDEU or nothing */ ++#define TALITOS_SEL1_MDEU 0x00030000 ++ ++/* secondary execution unit mode (MODE1) and derivatives */ ++#define TALITOS_MODE1_MDEU_INIT 0x00001000 /* init starting regs */ ++#define TALITOS_MODE1_MDEU_HMAC 0x00000800 ++#define TALITOS_MODE1_MDEU_PAD 0x00000400 /* PD */ ++#define TALITOS_MODE1_MDEU_MD5 0x00000200 ++#define TALITOS_MODE1_MDEU_SHA256 0x00000100 ++#define TALITOS_MODE1_MDEU_SHA1 0x00000000 /* SHA-160 */ ++#define TALITOS_MODE1_MDEU_MD5_HMAC \ ++ (TALITOS_MODE1_MDEU_MD5 | TALITOS_MODE1_MDEU_HMAC) ++#define TALITOS_MODE1_MDEU_SHA256_HMAC \ ++ (TALITOS_MODE1_MDEU_SHA256 | TALITOS_MODE1_MDEU_HMAC) ++#define TALITOS_MODE1_MDEU_SHA1_HMAC \ ++ (TALITOS_MODE1_MDEU_SHA1 | TALITOS_MODE1_MDEU_HMAC) ++ ++/* direction of overall data flow (DIR) */ ++#define TALITOS_DIR_OUTBOUND 0x00000000 ++#define TALITOS_DIR_INBOUND 0x00000002 ++ ++/* done notification (DN) */ ++#define TALITOS_DONE_NOTIFY 0x00000001 ++ ++/* descriptor types */ ++/* odd numbers here are valid on SEC2 and greater only (e.g. ipsec_esp) */ ++#define TD_TYPE_AESU_CTR_NONSNOOP (0 << 3) ++#define TD_TYPE_IPSEC_ESP (1 << 3) ++#define TD_TYPE_COMMON_NONSNOOP_NO_AFEU (2 << 3) ++#define TD_TYPE_HMAC_SNOOP_NO_AFEU (4 << 3) ++ ++#define TALITOS_HDR_DONE_BITS 0xff000000 ++ ++#define DPRINTF(a...) do { \ ++ if (debug) { \ ++ printk("%s: ", sc ? \ ++ device_get_nameunit(sc->sc_cdev) : "talitos"); \ ++ printk(a); \ ++ } \ ++ } while (0) +diff -Nur linux-3.1.4.orig/crypto/ocf/talitos/talitos_soft.h linux-3.1.4/crypto/ocf/talitos/talitos_soft.h +--- linux-3.1.4.orig/crypto/ocf/talitos/talitos_soft.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/talitos/talitos_soft.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,76 @@ ++/* ++ * Freescale SEC data structures for integration with ocf-linux ++ * ++ * Copyright (c) 2006 Freescale Semiconductor, Inc. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The name of the author may not be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++/* ++ * paired descriptor and associated crypto operation ++ */ ++struct desc_cryptop_pair { ++ struct talitos_desc cf_desc; /* descriptor ptr */ ++ struct cryptop *cf_crp; /* cryptop ptr */ ++}; ++ ++/* ++ * Holds data specific to a single talitos device. ++ */ ++struct talitos_softc { ++ softc_device_decl sc_cdev; ++ struct platform_device *sc_dev; /* device backpointer */ ++ ocf_iomem_t sc_base_addr; ++ int sc_irq; ++ int sc_num; /* if we have multiple chips */ ++ int32_t sc_cid; /* crypto tag */ ++ u64 sc_chiprev; /* major/minor chip revision */ ++ int sc_nsessions; ++ struct talitos_session *sc_sessions; ++ int sc_num_channels;/* number of crypto channels */ ++ int sc_chfifo_len; /* channel fetch fifo len */ ++ int sc_exec_units; /* execution units mask */ ++ int sc_desc_types; /* descriptor types mask */ ++ /* ++ * mutual exclusion for intra-channel resources, e.g. fetch fifos ++ * the last entry is a meta-channel lock used by the channel scheduler ++ */ ++ spinlock_t *sc_chnfifolock; ++ /* sc_chnlastalgo contains last algorithm for that channel */ ++ int *sc_chnlastalg; ++ /* sc_chnfifo holds pending descriptor--crypto operation pairs */ ++ struct desc_cryptop_pair **sc_chnfifo; ++}; ++ ++struct talitos_session { ++ u_int32_t ses_used; ++ u_int32_t ses_klen; /* key length in bits */ ++ u_int32_t ses_key[8]; /* DES/3DES/AES key */ ++ u_int32_t ses_hmac[5]; /* hmac inner state */ ++ u_int32_t ses_hmac_len; /* hmac length */ ++ u_int32_t ses_mlen; /* desired hash result len (12=ipsec or 16) */ ++}; ++ ++#define TALITOS_SESSION(sid) ((sid) & 0x0fffffff) ++#define TALITOS_SID(crd, sesn) (((crd) << 28) | ((sesn) & 0x0fffffff)) +diff -Nur linux-3.1.4.orig/crypto/ocf/ubsec_ssb/Makefile linux-3.1.4/crypto/ocf/ubsec_ssb/Makefile +--- linux-3.1.4.orig/crypto/ocf/ubsec_ssb/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/ubsec_ssb/Makefile 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,12 @@ ++# for SGlinux builds ++-include $(ROOTDIR)/modules/.config ++ ++obj-$(CONFIG_OCF_UBSEC_SSB) += ubsec_ssb.o ++ ++obj ?= . ++EXTRA_CFLAGS += -I$(obj)/.. -I$(obj)/ ++ ++ifdef TOPDIR ++-include $(TOPDIR)/Rules.make ++endif ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/ubsec_ssb/bsdqueue.h linux-3.1.4/crypto/ocf/ubsec_ssb/bsdqueue.h +--- linux-3.1.4.orig/crypto/ocf/ubsec_ssb/bsdqueue.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/ubsec_ssb/bsdqueue.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,527 @@ ++/* $OpenBSD: queue.h,v 1.32 2007/04/30 18:42:34 pedro Exp $ */ ++/* $NetBSD: queue.h,v 1.11 1996/05/16 05:17:14 mycroft Exp $ */ ++ ++/* ++ * Copyright (c) 1991, 1993 ++ * The Regents of the University of California. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. Neither the name of the University nor the names of its contributors ++ * may be used to endorse or promote products derived from this software ++ * without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE ++ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ++ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS ++ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF ++ * SUCH DAMAGE. ++ * ++ * @(#)queue.h 8.5 (Berkeley) 8/20/94 ++ */ ++ ++#ifndef _BSD_SYS_QUEUE_H_ ++#define _BSD_SYS_QUEUE_H_ ++ ++/* ++ * This file defines five types of data structures: singly-linked lists, ++ * lists, simple queues, tail queues, and circular queues. ++ * ++ * ++ * A singly-linked list is headed by a single forward pointer. The elements ++ * are singly linked for minimum space and pointer manipulation overhead at ++ * the expense of O(n) removal for arbitrary elements. New elements can be ++ * added to the list after an existing element or at the head of the list. ++ * Elements being removed from the head of the list should use the explicit ++ * macro for this purpose for optimum efficiency. A singly-linked list may ++ * only be traversed in the forward direction. Singly-linked lists are ideal ++ * for applications with large datasets and few or no removals or for ++ * implementing a LIFO queue. ++ * ++ * A list is headed by a single forward pointer (or an array of forward ++ * pointers for a hash table header). The elements are doubly linked ++ * so that an arbitrary element can be removed without a need to ++ * traverse the list. New elements can be added to the list before ++ * or after an existing element or at the head of the list. A list ++ * may only be traversed in the forward direction. ++ * ++ * A simple queue is headed by a pair of pointers, one the head of the ++ * list and the other to the tail of the list. The elements are singly ++ * linked to save space, so elements can only be removed from the ++ * head of the list. New elements can be added to the list before or after ++ * an existing element, at the head of the list, or at the end of the ++ * list. A simple queue may only be traversed in the forward direction. ++ * ++ * A tail queue is headed by a pair of pointers, one to the head of the ++ * list and the other to the tail of the list. The elements are doubly ++ * linked so that an arbitrary element can be removed without a need to ++ * traverse the list. New elements can be added to the list before or ++ * after an existing element, at the head of the list, or at the end of ++ * the list. A tail queue may be traversed in either direction. ++ * ++ * A circle queue is headed by a pair of pointers, one to the head of the ++ * list and the other to the tail of the list. The elements are doubly ++ * linked so that an arbitrary element can be removed without a need to ++ * traverse the list. New elements can be added to the list before or after ++ * an existing element, at the head of the list, or at the end of the list. ++ * A circle queue may be traversed in either direction, but has a more ++ * complex end of list detection. ++ * ++ * For details on the use of these macros, see the queue(3) manual page. ++ */ ++ ++#if defined(QUEUE_MACRO_DEBUG) || (defined(_KERNEL) && defined(DIAGNOSTIC)) ++#define _Q_INVALIDATE(a) (a) = ((void *)-1) ++#else ++#define _Q_INVALIDATE(a) ++#endif ++ ++/* ++ * Singly-linked List definitions. ++ */ ++#define BSD_SLIST_HEAD(name, type) \ ++struct name { \ ++ struct type *slh_first; /* first element */ \ ++} ++ ++#define BSD_SLIST_HEAD_INITIALIZER(head) \ ++ { NULL } ++ ++#define BSD_SLIST_ENTRY(type) \ ++struct { \ ++ struct type *sle_next; /* next element */ \ ++} ++ ++/* ++ * Singly-linked List access methods. ++ */ ++#define BSD_SLIST_FIRST(head) ((head)->slh_first) ++#define BSD_SLIST_END(head) NULL ++#define BSD_SLIST_EMPTY(head) (BSD_SLIST_FIRST(head) == BSD_SLIST_END(head)) ++#define BSD_SLIST_NEXT(elm, field) ((elm)->field.sle_next) ++ ++#define BSD_SLIST_FOREACH(var, head, field) \ ++ for((var) = BSD_SLIST_FIRST(head); \ ++ (var) != BSD_SLIST_END(head); \ ++ (var) = BSD_SLIST_NEXT(var, field)) ++ ++#define BSD_SLIST_FOREACH_PREVPTR(var, varp, head, field) \ ++ for ((varp) = &BSD_SLIST_FIRST((head)); \ ++ ((var) = *(varp)) != BSD_SLIST_END(head); \ ++ (varp) = &BSD_SLIST_NEXT((var), field)) ++ ++/* ++ * Singly-linked List functions. ++ */ ++#define BSD_SLIST_INIT(head) { \ ++ BSD_SLIST_FIRST(head) = BSD_SLIST_END(head); \ ++} ++ ++#define BSD_SLIST_INSERT_AFTER(slistelm, elm, field) do { \ ++ (elm)->field.sle_next = (slistelm)->field.sle_next; \ ++ (slistelm)->field.sle_next = (elm); \ ++} while (0) ++ ++#define BSD_SLIST_INSERT_HEAD(head, elm, field) do { \ ++ (elm)->field.sle_next = (head)->slh_first; \ ++ (head)->slh_first = (elm); \ ++} while (0) ++ ++#define BSD_SLIST_REMOVE_NEXT(head, elm, field) do { \ ++ (elm)->field.sle_next = (elm)->field.sle_next->field.sle_next; \ ++} while (0) ++ ++#define BSD_SLIST_REMOVE_HEAD(head, field) do { \ ++ (head)->slh_first = (head)->slh_first->field.sle_next; \ ++} while (0) ++ ++#define BSD_SLIST_REMOVE(head, elm, type, field) do { \ ++ if ((head)->slh_first == (elm)) { \ ++ BSD_SLIST_REMOVE_HEAD((head), field); \ ++ } else { \ ++ struct type *curelm = (head)->slh_first; \ ++ \ ++ while (curelm->field.sle_next != (elm)) \ ++ curelm = curelm->field.sle_next; \ ++ curelm->field.sle_next = \ ++ curelm->field.sle_next->field.sle_next; \ ++ _Q_INVALIDATE((elm)->field.sle_next); \ ++ } \ ++} while (0) ++ ++/* ++ * List definitions. ++ */ ++#define BSD_LIST_HEAD(name, type) \ ++struct name { \ ++ struct type *lh_first; /* first element */ \ ++} ++ ++#define BSD_LIST_HEAD_INITIALIZER(head) \ ++ { NULL } ++ ++#define BSD_LIST_ENTRY(type) \ ++struct { \ ++ struct type *le_next; /* next element */ \ ++ struct type **le_prev; /* address of previous next element */ \ ++} ++ ++/* ++ * List access methods ++ */ ++#define BSD_LIST_FIRST(head) ((head)->lh_first) ++#define BSD_LIST_END(head) NULL ++#define BSD_LIST_EMPTY(head) (BSD_LIST_FIRST(head) == BSD_LIST_END(head)) ++#define BSD_LIST_NEXT(elm, field) ((elm)->field.le_next) ++ ++#define BSD_LIST_FOREACH(var, head, field) \ ++ for((var) = BSD_LIST_FIRST(head); \ ++ (var)!= BSD_LIST_END(head); \ ++ (var) = BSD_LIST_NEXT(var, field)) ++ ++/* ++ * List functions. ++ */ ++#define BSD_LIST_INIT(head) do { \ ++ BSD_LIST_FIRST(head) = BSD_LIST_END(head); \ ++} while (0) ++ ++#define BSD_LIST_INSERT_AFTER(listelm, elm, field) do { \ ++ if (((elm)->field.le_next = (listelm)->field.le_next) != NULL) \ ++ (listelm)->field.le_next->field.le_prev = \ ++ &(elm)->field.le_next; \ ++ (listelm)->field.le_next = (elm); \ ++ (elm)->field.le_prev = &(listelm)->field.le_next; \ ++} while (0) ++ ++#define BSD_LIST_INSERT_BEFORE(listelm, elm, field) do { \ ++ (elm)->field.le_prev = (listelm)->field.le_prev; \ ++ (elm)->field.le_next = (listelm); \ ++ *(listelm)->field.le_prev = (elm); \ ++ (listelm)->field.le_prev = &(elm)->field.le_next; \ ++} while (0) ++ ++#define BSD_LIST_INSERT_HEAD(head, elm, field) do { \ ++ if (((elm)->field.le_next = (head)->lh_first) != NULL) \ ++ (head)->lh_first->field.le_prev = &(elm)->field.le_next;\ ++ (head)->lh_first = (elm); \ ++ (elm)->field.le_prev = &(head)->lh_first; \ ++} while (0) ++ ++#define BSD_LIST_REMOVE(elm, field) do { \ ++ if ((elm)->field.le_next != NULL) \ ++ (elm)->field.le_next->field.le_prev = \ ++ (elm)->field.le_prev; \ ++ *(elm)->field.le_prev = (elm)->field.le_next; \ ++ _Q_INVALIDATE((elm)->field.le_prev); \ ++ _Q_INVALIDATE((elm)->field.le_next); \ ++} while (0) ++ ++#define BSD_LIST_REPLACE(elm, elm2, field) do { \ ++ if (((elm2)->field.le_next = (elm)->field.le_next) != NULL) \ ++ (elm2)->field.le_next->field.le_prev = \ ++ &(elm2)->field.le_next; \ ++ (elm2)->field.le_prev = (elm)->field.le_prev; \ ++ *(elm2)->field.le_prev = (elm2); \ ++ _Q_INVALIDATE((elm)->field.le_prev); \ ++ _Q_INVALIDATE((elm)->field.le_next); \ ++} while (0) ++ ++/* ++ * Simple queue definitions. ++ */ ++#define BSD_SIMPLEQ_HEAD(name, type) \ ++struct name { \ ++ struct type *sqh_first; /* first element */ \ ++ struct type **sqh_last; /* addr of last next element */ \ ++} ++ ++#define BSD_SIMPLEQ_HEAD_INITIALIZER(head) \ ++ { NULL, &(head).sqh_first } ++ ++#define BSD_SIMPLEQ_ENTRY(type) \ ++struct { \ ++ struct type *sqe_next; /* next element */ \ ++} ++ ++/* ++ * Simple queue access methods. ++ */ ++#define BSD_SIMPLEQ_FIRST(head) ((head)->sqh_first) ++#define BSD_SIMPLEQ_END(head) NULL ++#define BSD_SIMPLEQ_EMPTY(head) (BSD_SIMPLEQ_FIRST(head) == BSD_SIMPLEQ_END(head)) ++#define BSD_SIMPLEQ_NEXT(elm, field) ((elm)->field.sqe_next) ++ ++#define BSD_SIMPLEQ_FOREACH(var, head, field) \ ++ for((var) = BSD_SIMPLEQ_FIRST(head); \ ++ (var) != BSD_SIMPLEQ_END(head); \ ++ (var) = BSD_SIMPLEQ_NEXT(var, field)) ++ ++/* ++ * Simple queue functions. ++ */ ++#define BSD_SIMPLEQ_INIT(head) do { \ ++ (head)->sqh_first = NULL; \ ++ (head)->sqh_last = &(head)->sqh_first; \ ++} while (0) ++ ++#define BSD_SIMPLEQ_INSERT_HEAD(head, elm, field) do { \ ++ if (((elm)->field.sqe_next = (head)->sqh_first) == NULL) \ ++ (head)->sqh_last = &(elm)->field.sqe_next; \ ++ (head)->sqh_first = (elm); \ ++} while (0) ++ ++#define BSD_SIMPLEQ_INSERT_TAIL(head, elm, field) do { \ ++ (elm)->field.sqe_next = NULL; \ ++ *(head)->sqh_last = (elm); \ ++ (head)->sqh_last = &(elm)->field.sqe_next; \ ++} while (0) ++ ++#define BSD_SIMPLEQ_INSERT_AFTER(head, listelm, elm, field) do { \ ++ if (((elm)->field.sqe_next = (listelm)->field.sqe_next) == NULL)\ ++ (head)->sqh_last = &(elm)->field.sqe_next; \ ++ (listelm)->field.sqe_next = (elm); \ ++} while (0) ++ ++#define BSD_SIMPLEQ_REMOVE_HEAD(head, field) do { \ ++ if (((head)->sqh_first = (head)->sqh_first->field.sqe_next) == NULL) \ ++ (head)->sqh_last = &(head)->sqh_first; \ ++} while (0) ++ ++/* ++ * Tail queue definitions. ++ */ ++#define BSD_TAILQ_HEAD(name, type) \ ++struct name { \ ++ struct type *tqh_first; /* first element */ \ ++ struct type **tqh_last; /* addr of last next element */ \ ++} ++ ++#define BSD_TAILQ_HEAD_INITIALIZER(head) \ ++ { NULL, &(head).tqh_first } ++ ++#define BSD_TAILQ_ENTRY(type) \ ++struct { \ ++ struct type *tqe_next; /* next element */ \ ++ struct type **tqe_prev; /* address of previous next element */ \ ++} ++ ++/* ++ * tail queue access methods ++ */ ++#define BSD_TAILQ_FIRST(head) ((head)->tqh_first) ++#define BSD_TAILQ_END(head) NULL ++#define BSD_TAILQ_NEXT(elm, field) ((elm)->field.tqe_next) ++#define BSD_TAILQ_LAST(head, headname) \ ++ (*(((struct headname *)((head)->tqh_last))->tqh_last)) ++/* XXX */ ++#define BSD_TAILQ_PREV(elm, headname, field) \ ++ (*(((struct headname *)((elm)->field.tqe_prev))->tqh_last)) ++#define BSD_TAILQ_EMPTY(head) \ ++ (BSD_TAILQ_FIRST(head) == BSD_TAILQ_END(head)) ++ ++#define BSD_TAILQ_FOREACH(var, head, field) \ ++ for((var) = BSD_TAILQ_FIRST(head); \ ++ (var) != BSD_TAILQ_END(head); \ ++ (var) = BSD_TAILQ_NEXT(var, field)) ++ ++#define BSD_TAILQ_FOREACH_REVERSE(var, head, headname, field) \ ++ for((var) = BSD_TAILQ_LAST(head, headname); \ ++ (var) != BSD_TAILQ_END(head); \ ++ (var) = BSD_TAILQ_PREV(var, headname, field)) ++ ++/* ++ * Tail queue functions. ++ */ ++#define BSD_TAILQ_INIT(head) do { \ ++ (head)->tqh_first = NULL; \ ++ (head)->tqh_last = &(head)->tqh_first; \ ++} while (0) ++ ++#define BSD_TAILQ_INSERT_HEAD(head, elm, field) do { \ ++ if (((elm)->field.tqe_next = (head)->tqh_first) != NULL) \ ++ (head)->tqh_first->field.tqe_prev = \ ++ &(elm)->field.tqe_next; \ ++ else \ ++ (head)->tqh_last = &(elm)->field.tqe_next; \ ++ (head)->tqh_first = (elm); \ ++ (elm)->field.tqe_prev = &(head)->tqh_first; \ ++} while (0) ++ ++#define BSD_TAILQ_INSERT_TAIL(head, elm, field) do { \ ++ (elm)->field.tqe_next = NULL; \ ++ (elm)->field.tqe_prev = (head)->tqh_last; \ ++ *(head)->tqh_last = (elm); \ ++ (head)->tqh_last = &(elm)->field.tqe_next; \ ++} while (0) ++ ++#define BSD_TAILQ_INSERT_AFTER(head, listelm, elm, field) do { \ ++ if (((elm)->field.tqe_next = (listelm)->field.tqe_next) != NULL)\ ++ (elm)->field.tqe_next->field.tqe_prev = \ ++ &(elm)->field.tqe_next; \ ++ else \ ++ (head)->tqh_last = &(elm)->field.tqe_next; \ ++ (listelm)->field.tqe_next = (elm); \ ++ (elm)->field.tqe_prev = &(listelm)->field.tqe_next; \ ++} while (0) ++ ++#define BSD_TAILQ_INSERT_BEFORE(listelm, elm, field) do { \ ++ (elm)->field.tqe_prev = (listelm)->field.tqe_prev; \ ++ (elm)->field.tqe_next = (listelm); \ ++ *(listelm)->field.tqe_prev = (elm); \ ++ (listelm)->field.tqe_prev = &(elm)->field.tqe_next; \ ++} while (0) ++ ++#define BSD_TAILQ_REMOVE(head, elm, field) do { \ ++ if (((elm)->field.tqe_next) != NULL) \ ++ (elm)->field.tqe_next->field.tqe_prev = \ ++ (elm)->field.tqe_prev; \ ++ else \ ++ (head)->tqh_last = (elm)->field.tqe_prev; \ ++ *(elm)->field.tqe_prev = (elm)->field.tqe_next; \ ++ _Q_INVALIDATE((elm)->field.tqe_prev); \ ++ _Q_INVALIDATE((elm)->field.tqe_next); \ ++} while (0) ++ ++#define BSD_TAILQ_REPLACE(head, elm, elm2, field) do { \ ++ if (((elm2)->field.tqe_next = (elm)->field.tqe_next) != NULL) \ ++ (elm2)->field.tqe_next->field.tqe_prev = \ ++ &(elm2)->field.tqe_next; \ ++ else \ ++ (head)->tqh_last = &(elm2)->field.tqe_next; \ ++ (elm2)->field.tqe_prev = (elm)->field.tqe_prev; \ ++ *(elm2)->field.tqe_prev = (elm2); \ ++ _Q_INVALIDATE((elm)->field.tqe_prev); \ ++ _Q_INVALIDATE((elm)->field.tqe_next); \ ++} while (0) ++ ++/* ++ * Circular queue definitions. ++ */ ++#define BSD_CIRCLEQ_HEAD(name, type) \ ++struct name { \ ++ struct type *cqh_first; /* first element */ \ ++ struct type *cqh_last; /* last element */ \ ++} ++ ++#define BSD_CIRCLEQ_HEAD_INITIALIZER(head) \ ++ { BSD_CIRCLEQ_END(&head), BSD_CIRCLEQ_END(&head) } ++ ++#define BSD_CIRCLEQ_ENTRY(type) \ ++struct { \ ++ struct type *cqe_next; /* next element */ \ ++ struct type *cqe_prev; /* previous element */ \ ++} ++ ++/* ++ * Circular queue access methods ++ */ ++#define BSD_CIRCLEQ_FIRST(head) ((head)->cqh_first) ++#define BSD_CIRCLEQ_LAST(head) ((head)->cqh_last) ++#define BSD_CIRCLEQ_END(head) ((void *)(head)) ++#define BSD_CIRCLEQ_NEXT(elm, field) ((elm)->field.cqe_next) ++#define BSD_CIRCLEQ_PREV(elm, field) ((elm)->field.cqe_prev) ++#define BSD_CIRCLEQ_EMPTY(head) \ ++ (BSD_CIRCLEQ_FIRST(head) == BSD_CIRCLEQ_END(head)) ++ ++#define BSD_CIRCLEQ_FOREACH(var, head, field) \ ++ for((var) = BSD_CIRCLEQ_FIRST(head); \ ++ (var) != BSD_CIRCLEQ_END(head); \ ++ (var) = BSD_CIRCLEQ_NEXT(var, field)) ++ ++#define BSD_CIRCLEQ_FOREACH_REVERSE(var, head, field) \ ++ for((var) = BSD_CIRCLEQ_LAST(head); \ ++ (var) != BSD_CIRCLEQ_END(head); \ ++ (var) = BSD_CIRCLEQ_PREV(var, field)) ++ ++/* ++ * Circular queue functions. ++ */ ++#define BSD_CIRCLEQ_INIT(head) do { \ ++ (head)->cqh_first = BSD_CIRCLEQ_END(head); \ ++ (head)->cqh_last = BSD_CIRCLEQ_END(head); \ ++} while (0) ++ ++#define BSD_CIRCLEQ_INSERT_AFTER(head, listelm, elm, field) do { \ ++ (elm)->field.cqe_next = (listelm)->field.cqe_next; \ ++ (elm)->field.cqe_prev = (listelm); \ ++ if ((listelm)->field.cqe_next == BSD_CIRCLEQ_END(head)) \ ++ (head)->cqh_last = (elm); \ ++ else \ ++ (listelm)->field.cqe_next->field.cqe_prev = (elm); \ ++ (listelm)->field.cqe_next = (elm); \ ++} while (0) ++ ++#define BSD_CIRCLEQ_INSERT_BEFORE(head, listelm, elm, field) do { \ ++ (elm)->field.cqe_next = (listelm); \ ++ (elm)->field.cqe_prev = (listelm)->field.cqe_prev; \ ++ if ((listelm)->field.cqe_prev == BSD_CIRCLEQ_END(head)) \ ++ (head)->cqh_first = (elm); \ ++ else \ ++ (listelm)->field.cqe_prev->field.cqe_next = (elm); \ ++ (listelm)->field.cqe_prev = (elm); \ ++} while (0) ++ ++#define BSD_CIRCLEQ_INSERT_HEAD(head, elm, field) do { \ ++ (elm)->field.cqe_next = (head)->cqh_first; \ ++ (elm)->field.cqe_prev = BSD_CIRCLEQ_END(head); \ ++ if ((head)->cqh_last == BSD_CIRCLEQ_END(head)) \ ++ (head)->cqh_last = (elm); \ ++ else \ ++ (head)->cqh_first->field.cqe_prev = (elm); \ ++ (head)->cqh_first = (elm); \ ++} while (0) ++ ++#define BSD_CIRCLEQ_INSERT_TAIL(head, elm, field) do { \ ++ (elm)->field.cqe_next = BSD_CIRCLEQ_END(head); \ ++ (elm)->field.cqe_prev = (head)->cqh_last; \ ++ if ((head)->cqh_first == BSD_CIRCLEQ_END(head)) \ ++ (head)->cqh_first = (elm); \ ++ else \ ++ (head)->cqh_last->field.cqe_next = (elm); \ ++ (head)->cqh_last = (elm); \ ++} while (0) ++ ++#define BSD_CIRCLEQ_REMOVE(head, elm, field) do { \ ++ if ((elm)->field.cqe_next == BSD_CIRCLEQ_END(head)) \ ++ (head)->cqh_last = (elm)->field.cqe_prev; \ ++ else \ ++ (elm)->field.cqe_next->field.cqe_prev = \ ++ (elm)->field.cqe_prev; \ ++ if ((elm)->field.cqe_prev == BSD_CIRCLEQ_END(head)) \ ++ (head)->cqh_first = (elm)->field.cqe_next; \ ++ else \ ++ (elm)->field.cqe_prev->field.cqe_next = \ ++ (elm)->field.cqe_next; \ ++ _Q_INVALIDATE((elm)->field.cqe_prev); \ ++ _Q_INVALIDATE((elm)->field.cqe_next); \ ++} while (0) ++ ++#define BSD_CIRCLEQ_REPLACE(head, elm, elm2, field) do { \ ++ if (((elm2)->field.cqe_next = (elm)->field.cqe_next) == \ ++ BSD_CIRCLEQ_END(head)) \ ++ (head).cqh_last = (elm2); \ ++ else \ ++ (elm2)->field.cqe_next->field.cqe_prev = (elm2); \ ++ if (((elm2)->field.cqe_prev = (elm)->field.cqe_prev) == \ ++ BSD_CIRCLEQ_END(head)) \ ++ (head).cqh_first = (elm2); \ ++ else \ ++ (elm2)->field.cqe_prev->field.cqe_next = (elm2); \ ++ _Q_INVALIDATE((elm)->field.cqe_prev); \ ++ _Q_INVALIDATE((elm)->field.cqe_next); \ ++} while (0) ++ ++#endif /* !_BSD_SYS_QUEUE_H_ */ +diff -Nur linux-3.1.4.orig/crypto/ocf/ubsec_ssb/ubsec_ssb.c linux-3.1.4/crypto/ocf/ubsec_ssb/ubsec_ssb.c +--- linux-3.1.4.orig/crypto/ocf/ubsec_ssb/ubsec_ssb.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/ubsec_ssb/ubsec_ssb.c 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,2220 @@ ++ ++/* ++ * Copyright (c) 2008 Daniel Mueller (daniel@danm.de) ++ * Copyright (c) 2007 David McCullough (david_mccullough@securecomputing.com) ++ * Copyright (c) 2000 Jason L. Wright (jason@thought.net) ++ * Copyright (c) 2000 Theo de Raadt (deraadt@openbsd.org) ++ * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com) ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++ * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, ++ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ++ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored in part by the Defense Advanced Research Projects ++ * Agency (DARPA) and Air Force Research Laboratory, Air Force ++ * Materiel Command, USAF, under agreement number F30602-01-2-0537. ++ * ++ */ ++#undef UBSEC_DEBUG ++#undef UBSEC_VERBOSE_DEBUG ++ ++#ifdef UBSEC_VERBOSE_DEBUG ++#define UBSEC_DEBUG ++#endif ++ ++/* ++ * uBsec BCM5365 hardware crypto accelerator ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++/* ++ * BSD queue ++ */ ++//#include "bsdqueue.h" ++ ++/* ++ * OCF ++ */ ++#include ++#include ++ ++#define HMAC_HACK 1 ++ ++#define HMAC_HACK 1 ++#ifdef HMAC_HACK ++#include ++#include ++#include ++#include ++#include ++#endif ++ ++#include "bsdqueue.h" ++#include "ubsecreg.h" ++#include "ubsecvar.h" ++ ++#define DRV_MODULE_NAME "ubsec_ssb" ++#define PFX DRV_MODULE_NAME ": " ++#define DRV_MODULE_VERSION "0.02" ++#define DRV_MODULE_RELDATE "Feb 21, 2009" ++ ++#if 1 ++#define DPRINTF(a...) \ ++ if (debug) \ ++ { \ ++ printk(DRV_MODULE_NAME ": " a); \ ++ } ++#else ++#define DPRINTF(a...) ++#endif ++ ++/* ++ * Prototypes ++ */ ++static irqreturn_t ubsec_ssb_isr(int, void *, struct pt_regs *); ++static int __devinit ubsec_ssb_probe(struct ssb_device *sdev, ++ const struct ssb_device_id *ent); ++static void __devexit ubsec_ssb_remove(struct ssb_device *sdev); ++int ubsec_attach(struct ssb_device *sdev, const struct ssb_device_id *ent, ++ struct device *self); ++static void ubsec_setup_mackey(struct ubsec_session *ses, int algo, ++ caddr_t key, int klen); ++static int dma_map_skb(struct ubsec_softc *sc, ++ struct ubsec_dma_alloc* q_map, struct sk_buff *skb, int *mlen); ++static int dma_map_uio(struct ubsec_softc *sc, ++ struct ubsec_dma_alloc *q_map, struct uio *uio, int *mlen); ++static void dma_unmap(struct ubsec_softc *sc, ++ struct ubsec_dma_alloc *q_map, int mlen); ++static int ubsec_dmamap_aligned(struct ubsec_softc *sc, ++ const struct ubsec_dma_alloc *q_map, int mlen); ++ ++#ifdef UBSEC_DEBUG ++static int proc_read(char *buf, char **start, off_t offset, ++ int size, int *peof, void *data); ++#endif ++ ++void ubsec_reset_board(struct ubsec_softc *); ++void ubsec_init_board(struct ubsec_softc *); ++void ubsec_cleanchip(struct ubsec_softc *); ++void ubsec_totalreset(struct ubsec_softc *); ++int ubsec_free_q(struct ubsec_softc*, struct ubsec_q *); ++ ++static int ubsec_newsession(device_t, u_int32_t *, struct cryptoini *); ++static int ubsec_freesession(device_t, u_int64_t); ++static int ubsec_process(device_t, struct cryptop *, int); ++ ++void ubsec_callback(struct ubsec_softc *, struct ubsec_q *); ++void ubsec_feed(struct ubsec_softc *); ++void ubsec_mcopy(struct sk_buff *, struct sk_buff *, int, int); ++void ubsec_dma_free(struct ubsec_softc *, struct ubsec_dma_alloc *); ++int ubsec_dma_malloc(struct ubsec_softc *, struct ubsec_dma_alloc *, ++ size_t, int); ++ ++/* DEBUG crap... */ ++void ubsec_dump_pb(struct ubsec_pktbuf *); ++void ubsec_dump_mcr(struct ubsec_mcr *); ++ ++#define READ_REG(sc,r) \ ++ ssb_read32((sc)->sdev, (r)); ++#define WRITE_REG(sc,r,val) \ ++ ssb_write32((sc)->sdev, (r), (val)); ++#define READ_REG_SDEV(sdev,r) \ ++ ssb_read32((sdev), (r)); ++#define WRITE_REG_SDEV(sdev,r,val) \ ++ ssb_write32((sdev), (r), (val)); ++ ++#define SWAP32(x) (x) = htole32(ntohl((x))) ++#define HTOLE32(x) (x) = htole32(x) ++ ++#ifdef __LITTLE_ENDIAN ++#define letoh16(x) (x) ++#define letoh32(x) (x) ++#endif ++ ++static int debug; ++module_param(debug, int, 0644); ++MODULE_PARM_DESC(debug, "Enable debug output"); ++ ++#define UBSEC_SSB_MAX_CHIPS 1 ++static struct ubsec_softc *ubsec_chip_idx[UBSEC_SSB_MAX_CHIPS]; ++static struct ubsec_stats ubsecstats; ++ ++#ifdef UBSEC_DEBUG ++static struct proc_dir_entry *procdebug; ++#endif ++ ++static struct ssb_device_id ubsec_ssb_tbl[] = { ++ /* Broadcom BCM5365P IPSec Core */ ++ SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_IPSEC, SSB_ANY_REV), ++ SSB_DEVTABLE_END ++}; ++ ++static struct ssb_driver ubsec_ssb_driver = { ++ .name = DRV_MODULE_NAME, ++ .id_table = ubsec_ssb_tbl, ++ .probe = ubsec_ssb_probe, ++ .remove = __devexit_p(ubsec_ssb_remove), ++ /* ++ .suspend = ubsec_ssb_suspend, ++ .resume = ubsec_ssb_resume ++ */ ++}; ++ ++static device_method_t ubsec_ssb_methods = { ++ /* crypto device methods */ ++ DEVMETHOD(cryptodev_newsession, ubsec_newsession), ++ DEVMETHOD(cryptodev_freesession,ubsec_freesession), ++ DEVMETHOD(cryptodev_process, ubsec_process), ++}; ++ ++#ifdef UBSEC_DEBUG ++static int ++proc_read(char *buf, char **start, off_t offset, ++ int size, int *peof, void *data) ++{ ++ int i = 0, byteswritten = 0, ret; ++ unsigned int stat, ctrl; ++#ifdef UBSEC_VERBOSE_DEBUG ++ struct ubsec_q *q; ++ struct ubsec_dma *dmap; ++#endif ++ ++ while ((i < UBSEC_SSB_MAX_CHIPS) && (ubsec_chip_idx[i] != NULL)) ++ { ++ struct ubsec_softc *sc = ubsec_chip_idx[i]; ++ ++ stat = READ_REG(sc, BS_STAT); ++ ctrl = READ_REG(sc, BS_CTRL); ++ ret = snprintf((buf + byteswritten), ++ (size - byteswritten) , ++ "DEV %d, DMASTAT %08x, DMACTRL %08x\n", i, stat, ctrl); ++ ++ byteswritten += ret; ++ ++#ifdef UBSEC_VERBOSE_DEBUG ++ printf("DEV %d, DMASTAT %08x, DMACTRL %08x\n", i, stat, ctrl); ++ ++ /* Dump all queues MCRs */ ++ if (!BSD_SIMPLEQ_EMPTY(&sc->sc_qchip)) { ++ BSD_SIMPLEQ_FOREACH(q, &sc->sc_qchip, q_next) ++ { ++ dmap = q->q_dma; ++ ubsec_dump_mcr(&dmap->d_dma->d_mcr); ++ } ++ } ++#endif ++ ++ i++; ++ } ++ ++ *peof = 1; ++ ++ return byteswritten; ++} ++#endif ++ ++/* ++ * map in a given sk_buff ++ */ ++static int ++dma_map_skb(struct ubsec_softc *sc, struct ubsec_dma_alloc* q_map, struct sk_buff *skb, int *mlen) ++{ ++ int i = 0; ++ dma_addr_t tmp; ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ ++ /* ++ * We support only a limited number of fragments. ++ */ ++ if (unlikely((skb_shinfo(skb)->nr_frags + 1) >= UBS_MAX_SCATTER)) ++ { ++ printk(KERN_ERR "Only %d scatter fragments are supported.\n", UBS_MAX_SCATTER); ++ return (-ENOMEM); ++ } ++ ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("%s - map %d 0x%x %d\n", __FUNCTION__, 0, (unsigned int)skb->data, skb_headlen(skb)); ++#endif ++ ++ /* first data package */ ++ tmp = dma_map_single(sc->sc_dv, ++ skb->data, ++ skb_headlen(skb), ++ DMA_BIDIRECTIONAL); ++ ++ q_map[i].dma_paddr = tmp; ++ q_map[i].dma_vaddr = skb->data; ++ q_map[i].dma_size = skb_headlen(skb); ++ ++ if (unlikely(tmp == 0)) ++ { ++ printk(KERN_ERR "Could not map memory region for dma.\n"); ++ return (-EINVAL); ++ } ++ ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("%s - map %d done physical addr 0x%x\n", __FUNCTION__, 0, (unsigned int)tmp); ++#endif ++ ++ ++ /* all other data packages */ ++ for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { ++ ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("%s - map %d 0x%x %d\n", __FUNCTION__, i + 1, ++ (unsigned int)page_address(skb_shinfo(skb)->frags[i].page) + ++ skb_shinfo(skb)->frags[i].page_offset, skb_shinfo(skb)->frags[i].size); ++#endif ++ ++ tmp = dma_map_single(sc->sc_dv, ++ page_address(skb_shinfo(skb)->frags[i].page) + ++ skb_shinfo(skb)->frags[i].page_offset, ++ skb_shinfo(skb)->frags[i].size, ++ DMA_BIDIRECTIONAL); ++ ++ q_map[i + 1].dma_paddr = tmp; ++ q_map[i + 1].dma_vaddr = (void*)(page_address(skb_shinfo(skb)->frags[i].page) + ++ skb_shinfo(skb)->frags[i].page_offset); ++ q_map[i + 1].dma_size = skb_shinfo(skb)->frags[i].size; ++ ++ if (unlikely(tmp == 0)) ++ { ++ printk(KERN_ERR "Could not map memory region for dma.\n"); ++ return (-EINVAL); ++ } ++ ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("%s - map %d done physical addr 0x%x\n", __FUNCTION__, i + 1, (unsigned int)tmp); ++#endif ++ ++ } ++ *mlen = i + 1; ++ ++ return(0); ++} ++ ++/* ++ * map in a given uio buffer ++ */ ++ ++static int ++dma_map_uio(struct ubsec_softc *sc, struct ubsec_dma_alloc *q_map, struct uio *uio, int *mlen) ++{ ++ struct iovec *iov = uio->uio_iov; ++ int n; ++ dma_addr_t tmp; ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ ++ /* ++ * We support only a limited number of fragments. ++ */ ++ if (unlikely(uio->uio_iovcnt >= UBS_MAX_SCATTER)) ++ { ++ printk(KERN_ERR "Only %d scatter fragments are supported.\n", UBS_MAX_SCATTER); ++ return (-ENOMEM); ++ } ++ ++ for (n = 0; n < uio->uio_iovcnt; n++) { ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("%s - map %d 0x%x %d\n", __FUNCTION__, n, (unsigned int)iov->iov_base, iov->iov_len); ++#endif ++ tmp = dma_map_single(sc->sc_dv, ++ iov->iov_base, ++ iov->iov_len, ++ DMA_BIDIRECTIONAL); ++ ++ q_map[n].dma_paddr = tmp; ++ q_map[n].dma_vaddr = iov->iov_base; ++ q_map[n].dma_size = iov->iov_len; ++ ++ if (unlikely(tmp == 0)) ++ { ++ printk(KERN_ERR "Could not map memory region for dma.\n"); ++ return (-EINVAL); ++ } ++ ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("%s - map %d done physical addr 0x%x\n", __FUNCTION__, n, (unsigned int)tmp); ++#endif ++ ++ iov++; ++ } ++ *mlen = n; ++ ++ return(0); ++} ++ ++static void ++dma_unmap(struct ubsec_softc *sc, struct ubsec_dma_alloc *q_map, int mlen) ++{ ++ int i; ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ ++ for(i = 0; i < mlen; i++) ++ { ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("%s - unmap %d 0x%x %d\n", __FUNCTION__, i, (unsigned int)q_map[i].dma_paddr, q_map[i].dma_size); ++#endif ++ dma_unmap_single(sc->sc_dv, ++ q_map[i].dma_paddr, ++ q_map[i].dma_size, ++ DMA_BIDIRECTIONAL); ++ } ++ return; ++} ++ ++/* ++ * Is the operand suitable aligned for direct DMA. Each ++ * segment must be aligned on a 32-bit boundary and all ++ * but the last segment must be a multiple of 4 bytes. ++ */ ++static int ++ubsec_dmamap_aligned(struct ubsec_softc *sc, const struct ubsec_dma_alloc *q_map, int mlen) ++{ ++ int i; ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ ++ for (i = 0; i < mlen; i++) { ++ if (q_map[i].dma_paddr & 3) ++ return (0); ++ if (i != (mlen - 1) && (q_map[i].dma_size & 3)) ++ return (0); ++ } ++ return (1); ++} ++ ++ ++#define N(a) (sizeof(a) / sizeof (a[0])) ++static void ++ubsec_setup_mackey(struct ubsec_session *ses, int algo, caddr_t key, int klen) ++{ ++#ifdef HMAC_HACK ++ MD5_CTX md5ctx; ++ SHA1_CTX sha1ctx; ++ int i; ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ ++ for (i = 0; i < klen; i++) ++ key[i] ^= HMAC_IPAD_VAL; ++ ++ if (algo == CRYPTO_MD5_HMAC) { ++ MD5Init(&md5ctx); ++ MD5Update(&md5ctx, key, klen); ++ MD5Update(&md5ctx, hmac_ipad_buffer, MD5_HMAC_BLOCK_LEN - klen); ++ bcopy(md5ctx.md5_st8, ses->ses_hminner, sizeof(md5ctx.md5_st8)); ++ } else { ++ SHA1Init(&sha1ctx); ++ SHA1Update(&sha1ctx, key, klen); ++ SHA1Update(&sha1ctx, hmac_ipad_buffer, ++ SHA1_HMAC_BLOCK_LEN - klen); ++ bcopy(sha1ctx.h.b32, ses->ses_hminner, sizeof(sha1ctx.h.b32)); ++ } ++ ++ for (i = 0; i < klen; i++) ++ key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); ++ ++ if (algo == CRYPTO_MD5_HMAC) { ++ MD5Init(&md5ctx); ++ MD5Update(&md5ctx, key, klen); ++ MD5Update(&md5ctx, hmac_opad_buffer, MD5_HMAC_BLOCK_LEN - klen); ++ bcopy(md5ctx.md5_st8, ses->ses_hmouter, sizeof(md5ctx.md5_st8)); ++ } else { ++ SHA1Init(&sha1ctx); ++ SHA1Update(&sha1ctx, key, klen); ++ SHA1Update(&sha1ctx, hmac_opad_buffer, ++ SHA1_HMAC_BLOCK_LEN - klen); ++ bcopy(sha1ctx.h.b32, ses->ses_hmouter, sizeof(sha1ctx.h.b32)); ++ } ++ ++ for (i = 0; i < klen; i++) ++ key[i] ^= HMAC_OPAD_VAL; ++ ++#else /* HMAC_HACK */ ++ DPRINTF("md5/sha not implemented\n"); ++#endif /* HMAC_HACK */ ++} ++#undef N ++ ++static int ++__devinit ubsec_ssb_probe(struct ssb_device *sdev, ++ const struct ssb_device_id *ent) ++{ ++ int err; ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ ++ err = ssb_bus_powerup(sdev->bus, 0); ++ if (err) { ++ dev_err(sdev->dev, "Failed to powerup the bus\n"); ++ goto err_out; ++ } ++ ++ err = request_irq(sdev->irq, (irq_handler_t)ubsec_ssb_isr, ++ IRQF_DISABLED | IRQF_SHARED, DRV_MODULE_NAME, sdev); ++ if (err) { ++ dev_err(sdev->dev, "Could not request irq\n"); ++ goto err_out_powerdown; ++ } ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,36)) ++ err = dma_set_mask(sdev->dma_dev, DMA_BIT_MASK(32)) || ++ dma_set_coherent_mask(sdev->dma_dev, DMA_BIT_MASK(32)); ++#else ++ err = ssb_dma_set_mask(sdev, DMA_32BIT_MASK); ++#endif ++ if (err) { ++ dev_err(sdev->dev, ++ "Required 32BIT DMA mask unsupported by the system.\n"); ++ goto err_out_free_irq; ++ } ++ ++ printk(KERN_INFO "Sentry5(tm) ROBOGateway(tm) IPSec Core at IRQ %u\n", ++ sdev->irq); ++ ++ DPRINTF("Vendor: %x, core id: %x, revision: %x\n", ++ sdev->id.vendor, sdev->id.coreid, sdev->id.revision); ++ ++ ssb_device_enable(sdev, 0); ++ ++ if (ubsec_attach(sdev, ent, sdev->dev) != 0) ++ goto err_out_disable; ++ ++#ifdef UBSEC_DEBUG ++ procdebug = create_proc_entry(DRV_MODULE_NAME, S_IRUSR, NULL); ++ if (procdebug) ++ { ++ procdebug->read_proc = proc_read; ++ procdebug->data = NULL; ++ } else ++ DPRINTF("Unable to create proc file.\n"); ++#endif ++ ++ return 0; ++ ++err_out_disable: ++ ssb_device_disable(sdev, 0); ++ ++err_out_free_irq: ++ free_irq(sdev->irq, sdev); ++ ++err_out_powerdown: ++ ssb_bus_may_powerdown(sdev->bus); ++ ++err_out: ++ return err; ++} ++ ++static void __devexit ubsec_ssb_remove(struct ssb_device *sdev) { ++ ++ struct ubsec_softc *sc; ++ unsigned int ctrlflgs; ++ struct ubsec_dma *dmap; ++ u_int32_t i; ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ ++ ctrlflgs = READ_REG_SDEV(sdev, BS_CTRL); ++ /* disable all IPSec Core interrupts globally */ ++ ctrlflgs ^= (BS_CTRL_MCR1INT | BS_CTRL_MCR2INT | ++ BS_CTRL_DMAERR); ++ WRITE_REG_SDEV(sdev, BS_CTRL, ctrlflgs); ++ ++ free_irq(sdev->irq, sdev); ++ ++ sc = (struct ubsec_softc *)ssb_get_drvdata(sdev); ++ ++ /* unregister all crypto algorithms */ ++ crypto_unregister_all(sc->sc_cid); ++ ++ /* Free queue / dma memory */ ++ for (i = 0; i < UBS_MAX_NQUEUE; i++) { ++ struct ubsec_q *q; ++ ++ q = sc->sc_queuea[i]; ++ if (q != NULL) ++ { ++ dmap = q->q_dma; ++ if (dmap != NULL) ++ { ++ ubsec_dma_free(sc, &dmap->d_alloc); ++ q->q_dma = NULL; ++ } ++ kfree(q); ++ } ++ sc->sc_queuea[i] = NULL; ++ } ++ ++ ssb_device_disable(sdev, 0); ++ ssb_bus_may_powerdown(sdev->bus); ++ ssb_set_drvdata(sdev, NULL); ++ ++#ifdef UBSEC_DEBUG ++ if (procdebug) ++ remove_proc_entry(DRV_MODULE_NAME, NULL); ++#endif ++ ++} ++ ++ ++int ++ubsec_attach(struct ssb_device *sdev, const struct ssb_device_id *ent, ++ struct device *self) ++{ ++ struct ubsec_softc *sc = NULL; ++ struct ubsec_dma *dmap; ++ u_int32_t i; ++ static int num_chips = 0; ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ ++ sc = (struct ubsec_softc *) kmalloc(sizeof(*sc), GFP_KERNEL); ++ if (!sc) ++ return(-ENOMEM); ++ memset(sc, 0, sizeof(*sc)); ++ ++ sc->sc_dv = sdev->dev; ++ sc->sdev = sdev; ++ ++ spin_lock_init(&sc->sc_ringmtx); ++ ++ softc_device_init(sc, "ubsec_ssb", num_chips, ubsec_ssb_methods); ++ ++ /* Maybe someday there are boards with more than one chip available */ ++ if (num_chips < UBSEC_SSB_MAX_CHIPS) { ++ ubsec_chip_idx[device_get_unit(sc->sc_dev)] = sc; ++ num_chips++; ++ } ++ ++ ssb_set_drvdata(sdev, sc); ++ ++ BSD_SIMPLEQ_INIT(&sc->sc_queue); ++ BSD_SIMPLEQ_INIT(&sc->sc_qchip); ++ BSD_SIMPLEQ_INIT(&sc->sc_queue2); ++ BSD_SIMPLEQ_INIT(&sc->sc_qchip2); ++ BSD_SIMPLEQ_INIT(&sc->sc_q2free); ++ ++ sc->sc_statmask = BS_STAT_MCR1_DONE | BS_STAT_DMAERR; ++ ++ sc->sc_cid = crypto_get_driverid(softc_get_device(sc), CRYPTOCAP_F_HARDWARE); ++ if (sc->sc_cid < 0) { ++ device_printf(sc->sc_dev, "could not get crypto driver id\n"); ++ return -1; ++ } ++ ++ BSD_SIMPLEQ_INIT(&sc->sc_freequeue); ++ dmap = sc->sc_dmaa; ++ for (i = 0; i < UBS_MAX_NQUEUE; i++, dmap++) { ++ struct ubsec_q *q; ++ ++ q = (struct ubsec_q *)kmalloc(sizeof(struct ubsec_q), GFP_KERNEL); ++ if (q == NULL) { ++ printf(": can't allocate queue buffers\n"); ++ break; ++ } ++ ++ if (ubsec_dma_malloc(sc, &dmap->d_alloc, sizeof(struct ubsec_dmachunk),0)) { ++ printf(": can't allocate dma buffers\n"); ++ kfree(q); ++ break; ++ } ++ dmap->d_dma = (struct ubsec_dmachunk *)dmap->d_alloc.dma_vaddr; ++ ++ q->q_dma = dmap; ++ sc->sc_queuea[i] = q; ++ ++ BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); ++ } ++ ++ /* ++ * Reset Broadcom chip ++ */ ++ ubsec_reset_board(sc); ++ ++ /* ++ * Init Broadcom chip ++ */ ++ ubsec_init_board(sc); ++ ++ /* supported crypto algorithms */ ++ crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); ++ ++ if (sc->sc_flags & UBS_FLAGS_AES) { ++ crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); ++ printf(KERN_INFO DRV_MODULE_NAME ": DES 3DES AES128 AES192 AES256 MD5_HMAC SHA1_HMAC\n"); ++ } ++ else ++ printf(KERN_INFO DRV_MODULE_NAME ": DES 3DES MD5_HMAC SHA1_HMAC\n"); ++ ++ crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); ++ crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); ++ ++ return 0; ++} ++ ++/* ++ * UBSEC Interrupt routine ++ */ ++static irqreturn_t ++ubsec_ssb_isr(int irq, void *arg, struct pt_regs *regs) ++{ ++ struct ubsec_softc *sc = NULL; ++ volatile u_int32_t stat; ++ struct ubsec_q *q; ++ struct ubsec_dma *dmap; ++ int npkts = 0, i; ++ ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ ++ sc = (struct ubsec_softc *)ssb_get_drvdata(arg); ++ ++ stat = READ_REG(sc, BS_STAT); ++ ++ stat &= sc->sc_statmask; ++ if (stat == 0) ++ return IRQ_NONE; ++ ++ WRITE_REG(sc, BS_STAT, stat); /* IACK */ ++ ++ /* ++ * Check to see if we have any packets waiting for us ++ */ ++ if ((stat & BS_STAT_MCR1_DONE)) { ++ while (!BSD_SIMPLEQ_EMPTY(&sc->sc_qchip)) { ++ q = BSD_SIMPLEQ_FIRST(&sc->sc_qchip); ++ dmap = q->q_dma; ++ ++ if ((dmap->d_dma->d_mcr.mcr_flags & htole16(UBS_MCR_DONE)) == 0) ++ { ++ DPRINTF("error while processing MCR. Flags = %x\n", dmap->d_dma->d_mcr.mcr_flags); ++ break; ++ } ++ ++ BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q_next); ++ ++ npkts = q->q_nstacked_mcrs; ++ /* ++ * search for further sc_qchip ubsec_q's that share ++ * the same MCR, and complete them too, they must be ++ * at the top. ++ */ ++ for (i = 0; i < npkts; i++) { ++ if(q->q_stacked_mcr[i]) ++ ubsec_callback(sc, q->q_stacked_mcr[i]); ++ else ++ break; ++ } ++ ubsec_callback(sc, q); ++ } ++ ++ /* ++ * Don't send any more packet to chip if there has been ++ * a DMAERR. ++ */ ++ if (likely(!(stat & BS_STAT_DMAERR))) ++ ubsec_feed(sc); ++ else ++ DPRINTF("DMA error occurred. Stop feeding crypto chip.\n"); ++ } ++ ++ /* ++ * Check to see if we got any DMA Error ++ */ ++ if (stat & BS_STAT_DMAERR) { ++ volatile u_int32_t a = READ_REG(sc, BS_ERR); ++ ++ printf(KERN_ERR "%s: dmaerr %s@%08x\n", DRV_MODULE_NAME, ++ (a & BS_ERR_READ) ? "read" : "write", a & BS_ERR_ADDR); ++ ++ ubsecstats.hst_dmaerr++; ++ ubsec_totalreset(sc); ++ ubsec_feed(sc); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++/* ++ * ubsec_feed() - aggregate and post requests to chip ++ * It is assumed that the caller set splnet() ++ */ ++void ++ubsec_feed(struct ubsec_softc *sc) ++{ ++#ifdef UBSEC_VERBOSE_DEBUG ++ static int max; ++#endif ++ struct ubsec_q *q, *q2; ++ int npkts, i; ++ void *v; ++ u_int32_t stat; ++ ++ npkts = sc->sc_nqueue; ++ if (npkts > UBS_MAX_AGGR) ++ npkts = UBS_MAX_AGGR; ++ if (npkts < 2) ++ goto feed1; ++ ++ stat = READ_REG(sc, BS_STAT); ++ ++ if (stat & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) { ++ if(stat & BS_STAT_DMAERR) { ++ ubsec_totalreset(sc); ++ ubsecstats.hst_dmaerr++; ++ } ++ return; ++ } ++ ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("merging %d records\n", npkts); ++ ++ /* XXX temporary aggregation statistics reporting code */ ++ if (max < npkts) { ++ max = npkts; ++ DPRINTF("%s: new max aggregate %d\n", DRV_MODULE_NAME, max); ++ } ++#endif /* UBSEC_VERBOSE_DEBUG */ ++ ++ q = BSD_SIMPLEQ_FIRST(&sc->sc_queue); ++ BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next); ++ --sc->sc_nqueue; ++ ++#if 0 ++ /* ++ * XXX ++ * We use dma_map_single() - no sync required! ++ */ ++ ++ bus_dmamap_sync(sc->sc_dmat, q->q_src_map, ++ 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE); ++ if (q->q_dst_map != NULL) ++ bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, ++ 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD); ++#endif ++ ++ q->q_nstacked_mcrs = npkts - 1; /* Number of packets stacked */ ++ ++ for (i = 0; i < q->q_nstacked_mcrs; i++) { ++ q2 = BSD_SIMPLEQ_FIRST(&sc->sc_queue); ++ ++#if 0 ++ bus_dmamap_sync(sc->sc_dmat, q2->q_src_map, ++ 0, q2->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE); ++ if (q2->q_dst_map != NULL) ++ bus_dmamap_sync(sc->sc_dmat, q2->q_dst_map, ++ 0, q2->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD); ++#endif ++ BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next); ++ --sc->sc_nqueue; ++ ++ v = ((char *)&q2->q_dma->d_dma->d_mcr) + sizeof(struct ubsec_mcr) - ++ sizeof(struct ubsec_mcr_add); ++ bcopy(v, &q->q_dma->d_dma->d_mcradd[i], sizeof(struct ubsec_mcr_add)); ++ q->q_stacked_mcr[i] = q2; ++ } ++ q->q_dma->d_dma->d_mcr.mcr_pkts = htole16(npkts); ++ BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); ++#if 0 ++ bus_dmamap_sync(sc->sc_dmat, q->q_dma->d_alloc.dma_map, ++ 0, q->q_dma->d_alloc.dma_map->dm_mapsize, ++ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ++#endif ++ WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + ++ offsetof(struct ubsec_dmachunk, d_mcr)); ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("feed (1): q->chip %p %08x %08x\n", q, ++ (u_int32_t)q->q_dma->d_alloc.dma_paddr, ++ (u_int32_t)(q->q_dma->d_alloc.dma_paddr + ++ offsetof(struct ubsec_dmachunk, d_mcr))); ++#endif /* UBSEC_DEBUG */ ++ return; ++ ++feed1: ++ while (!BSD_SIMPLEQ_EMPTY(&sc->sc_queue)) { ++ stat = READ_REG(sc, BS_STAT); ++ ++ if (stat & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) { ++ if(stat & BS_STAT_DMAERR) { ++ ubsec_totalreset(sc); ++ ubsecstats.hst_dmaerr++; ++ } ++ break; ++ } ++ ++ q = BSD_SIMPLEQ_FIRST(&sc->sc_queue); ++ ++#if 0 ++ bus_dmamap_sync(sc->sc_dmat, q->q_src_map, ++ 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE); ++ if (q->q_dst_map != NULL) ++ bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, ++ 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD); ++ bus_dmamap_sync(sc->sc_dmat, q->q_dma->d_alloc.dma_map, ++ 0, q->q_dma->d_alloc.dma_map->dm_mapsize, ++ BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); ++#endif ++ ++ WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + ++ offsetof(struct ubsec_dmachunk, d_mcr)); ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("feed (2): q->chip %p %08x %08x\n", q, ++ (u_int32_t)q->q_dma->d_alloc.dma_paddr, ++ (u_int32_t)(q->q_dma->d_alloc.dma_paddr + ++ offsetof(struct ubsec_dmachunk, d_mcr))); ++#endif /* UBSEC_DEBUG */ ++ BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next); ++ --sc->sc_nqueue; ++ BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); ++ } ++} ++ ++/* ++ * Allocate a new 'session' and return an encoded session id. 'sidp' ++ * contains our registration id, and should contain an encoded session ++ * id on successful allocation. ++ */ ++static int ++ubsec_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) ++{ ++ struct cryptoini *c, *encini = NULL, *macini = NULL; ++ struct ubsec_softc *sc = NULL; ++ struct ubsec_session *ses = NULL; ++ int sesn, i; ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ ++ if (sidp == NULL || cri == NULL) ++ return (EINVAL); ++ ++ sc = device_get_softc(dev); ++ ++ if (sc == NULL) ++ return (EINVAL); ++ ++ for (c = cri; c != NULL; c = c->cri_next) { ++ if (c->cri_alg == CRYPTO_MD5_HMAC || ++ c->cri_alg == CRYPTO_SHA1_HMAC) { ++ if (macini) ++ return (EINVAL); ++ macini = c; ++ } else if (c->cri_alg == CRYPTO_DES_CBC || ++ c->cri_alg == CRYPTO_3DES_CBC || ++ c->cri_alg == CRYPTO_AES_CBC) { ++ if (encini) ++ return (EINVAL); ++ encini = c; ++ } else ++ return (EINVAL); ++ } ++ if (encini == NULL && macini == NULL) ++ return (EINVAL); ++ ++ if (sc->sc_sessions == NULL) { ++ ses = sc->sc_sessions = (struct ubsec_session *)kmalloc( ++ sizeof(struct ubsec_session), SLAB_ATOMIC); ++ if (ses == NULL) ++ return (ENOMEM); ++ memset(ses, 0, sizeof(struct ubsec_session)); ++ sesn = 0; ++ sc->sc_nsessions = 1; ++ } else { ++ for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { ++ if (sc->sc_sessions[sesn].ses_used == 0) { ++ ses = &sc->sc_sessions[sesn]; ++ break; ++ } ++ } ++ ++ if (ses == NULL) { ++ sesn = sc->sc_nsessions; ++ ses = (struct ubsec_session *)kmalloc((sesn + 1) * ++ sizeof(struct ubsec_session), SLAB_ATOMIC); ++ if (ses == NULL) ++ return (ENOMEM); ++ memset(ses, 0, (sesn + 1) * sizeof(struct ubsec_session)); ++ bcopy(sc->sc_sessions, ses, sesn * ++ sizeof(struct ubsec_session)); ++ bzero(sc->sc_sessions, sesn * ++ sizeof(struct ubsec_session)); ++ kfree(sc->sc_sessions); ++ sc->sc_sessions = ses; ++ ses = &sc->sc_sessions[sesn]; ++ sc->sc_nsessions++; ++ } ++ } ++ ++ bzero(ses, sizeof(struct ubsec_session)); ++ ses->ses_used = 1; ++ if (encini) { ++ /* get an IV */ ++ /* XXX may read fewer than requested */ ++ read_random(ses->ses_iv, sizeof(ses->ses_iv)); ++ ++ /* Go ahead and compute key in ubsec's byte order */ ++ if (encini->cri_alg == CRYPTO_DES_CBC) { ++ /* DES uses the same key three times: ++ * 1st encrypt -> 2nd decrypt -> 3nd encrypt */ ++ bcopy(encini->cri_key, &ses->ses_key[0], 8); ++ bcopy(encini->cri_key, &ses->ses_key[2], 8); ++ bcopy(encini->cri_key, &ses->ses_key[4], 8); ++ ses->ses_keysize = 192; /* Fake! Actually its only 64bits .. ++ oh no it is even less: 54bits. */ ++ } else if(encini->cri_alg == CRYPTO_3DES_CBC) { ++ bcopy(encini->cri_key, ses->ses_key, 24); ++ ses->ses_keysize = 192; ++ } else if(encini->cri_alg == CRYPTO_AES_CBC) { ++ ses->ses_keysize = encini->cri_klen; ++ ++ if (ses->ses_keysize != 128 && ++ ses->ses_keysize != 192 && ++ ses->ses_keysize != 256) ++ { ++ DPRINTF("unsupported AES key size: %d\n", ses->ses_keysize); ++ return (EINVAL); ++ } ++ bcopy(encini->cri_key, ses->ses_key, (ses->ses_keysize / 8)); ++ } ++ ++ /* Hardware requires the keys in little endian byte order */ ++ for (i=0; i < (ses->ses_keysize / 32); i++) ++ SWAP32(ses->ses_key[i]); ++ } ++ ++ if (macini) { ++ ses->ses_mlen = macini->cri_mlen; ++ ++ if (ses->ses_mlen == 0 || ++ ses->ses_mlen > SHA1_HASH_LEN) { ++ ++ if (macini->cri_alg == CRYPTO_MD5_HMAC || ++ macini->cri_alg == CRYPTO_SHA1_HMAC) ++ { ++ ses->ses_mlen = DEFAULT_HMAC_LEN; ++ } else ++ { ++ /* ++ * Reserved for future usage. MD5/SHA1 calculations have ++ * different hash sizes. ++ */ ++ printk(KERN_ERR DRV_MODULE_NAME ": unsupported hash operation with mac/hash len: %d\n", ses->ses_mlen); ++ return (EINVAL); ++ } ++ ++ } ++ ++ if (macini->cri_key != NULL) { ++ ubsec_setup_mackey(ses, macini->cri_alg, macini->cri_key, ++ macini->cri_klen / 8); ++ } ++ } ++ ++ *sidp = UBSEC_SID(device_get_unit(sc->sc_dev), sesn); ++ return (0); ++} ++ ++/* ++ * Deallocate a session. ++ */ ++static int ++ubsec_freesession(device_t dev, u_int64_t tid) ++{ ++ struct ubsec_softc *sc = device_get_softc(dev); ++ int session; ++ u_int32_t sid = ((u_int32_t)tid) & 0xffffffff; ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ ++ if (sc == NULL) ++ return (EINVAL); ++ ++ session = UBSEC_SESSION(sid); ++ if (session < sc->sc_nsessions) { ++ bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session])); ++ return (0); ++ } else ++ return (EINVAL); ++} ++ ++static int ++ubsec_process(device_t dev, struct cryptop *crp, int hint) ++{ ++ struct ubsec_q *q = NULL; ++ int err = 0, i, j, nicealign; ++ struct ubsec_softc *sc = device_get_softc(dev); ++ struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; ++ int encoffset = 0, macoffset = 0, cpskip, cpoffset; ++ int sskip, dskip, stheend, dtheend, ivsize = 8; ++ int16_t coffset; ++ struct ubsec_session *ses; ++ struct ubsec_generic_ctx ctx; ++ struct ubsec_dma *dmap = NULL; ++ unsigned long flags; ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ ++ if (unlikely(crp == NULL || crp->crp_callback == NULL)) { ++ ubsecstats.hst_invalid++; ++ return (EINVAL); ++ } ++ ++ if (unlikely(sc == NULL)) ++ return (EINVAL); ++ ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("spin_lock_irqsave\n"); ++#endif ++ spin_lock_irqsave(&sc->sc_ringmtx, flags); ++ //spin_lock_irq(&sc->sc_ringmtx); ++ ++ if (BSD_SIMPLEQ_EMPTY(&sc->sc_freequeue)) { ++ ubsecstats.hst_queuefull++; ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("spin_unlock_irqrestore\n"); ++#endif ++ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); ++ //spin_unlock_irq(&sc->sc_ringmtx); ++ err = ENOMEM; ++ goto errout2; ++ } ++ ++ q = BSD_SIMPLEQ_FIRST(&sc->sc_freequeue); ++ BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q_next); ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("spin_unlock_irqrestore\n"); ++#endif ++ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); ++ //spin_unlock_irq(&sc->sc_ringmtx); ++ ++ dmap = q->q_dma; /* Save dma pointer */ ++ bzero(q, sizeof(struct ubsec_q)); ++ bzero(&ctx, sizeof(ctx)); ++ ++ q->q_sesn = UBSEC_SESSION(crp->crp_sid); ++ q->q_dma = dmap; ++ ses = &sc->sc_sessions[q->q_sesn]; ++ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ q->q_src_m = (struct sk_buff *)crp->crp_buf; ++ q->q_dst_m = (struct sk_buff *)crp->crp_buf; ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++ q->q_src_io = (struct uio *)crp->crp_buf; ++ q->q_dst_io = (struct uio *)crp->crp_buf; ++ } else { ++ err = EINVAL; ++ goto errout; /* XXX we don't handle contiguous blocks! */ ++ } ++ ++ bzero(&dmap->d_dma->d_mcr, sizeof(struct ubsec_mcr)); ++ ++ dmap->d_dma->d_mcr.mcr_pkts = htole16(1); ++ dmap->d_dma->d_mcr.mcr_flags = 0; ++ q->q_crp = crp; ++ ++ crd1 = crp->crp_desc; ++ if (crd1 == NULL) { ++ err = EINVAL; ++ goto errout; ++ } ++ crd2 = crd1->crd_next; ++ ++ if (crd2 == NULL) { ++ if (crd1->crd_alg == CRYPTO_MD5_HMAC || ++ crd1->crd_alg == CRYPTO_SHA1_HMAC) { ++ maccrd = crd1; ++ enccrd = NULL; ++ } else if (crd1->crd_alg == CRYPTO_DES_CBC || ++ crd1->crd_alg == CRYPTO_3DES_CBC || ++ crd1->crd_alg == CRYPTO_AES_CBC) { ++ maccrd = NULL; ++ enccrd = crd1; ++ } else { ++ err = EINVAL; ++ goto errout; ++ } ++ } else { ++ if ((crd1->crd_alg == CRYPTO_MD5_HMAC || ++ crd1->crd_alg == CRYPTO_SHA1_HMAC) && ++ (crd2->crd_alg == CRYPTO_DES_CBC || ++ crd2->crd_alg == CRYPTO_3DES_CBC || ++ crd2->crd_alg == CRYPTO_AES_CBC) && ++ ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { ++ maccrd = crd1; ++ enccrd = crd2; ++ } else if ((crd1->crd_alg == CRYPTO_DES_CBC || ++ crd1->crd_alg == CRYPTO_3DES_CBC || ++ crd1->crd_alg == CRYPTO_AES_CBC) && ++ (crd2->crd_alg == CRYPTO_MD5_HMAC || ++ crd2->crd_alg == CRYPTO_SHA1_HMAC) && ++ (crd1->crd_flags & CRD_F_ENCRYPT)) { ++ enccrd = crd1; ++ maccrd = crd2; ++ } else { ++ /* ++ * We cannot order the ubsec as requested ++ */ ++ printk(KERN_ERR DRV_MODULE_NAME ": got wrong algorithm/signature order.\n"); ++ err = EINVAL; ++ goto errout; ++ } ++ } ++ ++ /* Encryption/Decryption requested */ ++ if (enccrd) { ++ encoffset = enccrd->crd_skip; ++ ++ if (enccrd->crd_alg == CRYPTO_DES_CBC || ++ enccrd->crd_alg == CRYPTO_3DES_CBC) ++ { ++ ctx.pc_flags |= htole16(UBS_PKTCTX_ENC_3DES); ++ ctx.pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC_DES); ++ ivsize = 8; /* [3]DES uses 64bit IVs */ ++ } else { ++ ctx.pc_flags |= htole16(UBS_PKTCTX_ENC_AES); ++ ctx.pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC_AES); ++ ivsize = 16; /* AES uses 128bit IVs / [3]DES 64bit IVs */ ++ ++ switch(ses->ses_keysize) ++ { ++ case 128: ++ ctx.pc_flags |= htole16(UBS_PKTCTX_AES128); ++ break; ++ case 192: ++ ctx.pc_flags |= htole16(UBS_PKTCTX_AES192); ++ break; ++ case 256: ++ ctx.pc_flags |= htole16(UBS_PKTCTX_AES256); ++ break; ++ default: ++ DPRINTF("invalid AES key size: %d\n", ses->ses_keysize); ++ err = EINVAL; ++ goto errout; ++ } ++ } ++ ++ if (enccrd->crd_flags & CRD_F_ENCRYPT) { ++ /* Direction: Outbound */ ++ ++ q->q_flags |= UBSEC_QFLAGS_COPYOUTIV; ++ ++ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) { ++ bcopy(enccrd->crd_iv, ctx.pc_iv, ivsize); ++ } else { ++ for(i=0; i < (ivsize / 4); i++) ++ ctx.pc_iv[i] = ses->ses_iv[i]; ++ } ++ ++ /* If there is no IV in the buffer -> copy it here */ ++ if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { ++ if (crp->crp_flags & CRYPTO_F_SKBUF) ++ /* ++ m_copyback(q->q_src_m, ++ enccrd->crd_inject, ++ 8, ctx.pc_iv); ++ */ ++ crypto_copyback(crp->crp_flags, (caddr_t)q->q_src_m, ++ enccrd->crd_inject, ivsize, (caddr_t)ctx.pc_iv); ++ else if (crp->crp_flags & CRYPTO_F_IOV) ++ /* ++ cuio_copyback(q->q_src_io, ++ enccrd->crd_inject, ++ 8, ctx.pc_iv); ++ */ ++ crypto_copyback(crp->crp_flags, (caddr_t)q->q_src_io, ++ enccrd->crd_inject, ivsize, (caddr_t)ctx.pc_iv); ++ } ++ } else { ++ /* Direction: Inbound */ ++ ++ ctx.pc_flags |= htole16(UBS_PKTCTX_INBOUND); ++ ++ if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) ++ bcopy(enccrd->crd_iv, ctx.pc_iv, ivsize); ++ else if (crp->crp_flags & CRYPTO_F_SKBUF) ++ /* ++ m_copydata(q->q_src_m, enccrd->crd_inject, ++ 8, (caddr_t)ctx.pc_iv); ++ */ ++ crypto_copydata(crp->crp_flags, (caddr_t)q->q_src_m, ++ enccrd->crd_inject, ivsize, ++ (caddr_t)ctx.pc_iv); ++ else if (crp->crp_flags & CRYPTO_F_IOV) ++ /* ++ cuio_copydata(q->q_src_io, ++ enccrd->crd_inject, 8, ++ (caddr_t)ctx.pc_iv); ++ */ ++ crypto_copydata(crp->crp_flags, (caddr_t)q->q_src_io, ++ enccrd->crd_inject, ivsize, ++ (caddr_t)ctx.pc_iv); ++ ++ } ++ ++ /* Even though key & IV sizes differ from cipher to cipher ++ * copy / swap the full array lengths. Let the compiler unroll ++ * the loop to increase the cpu pipeline performance... */ ++ for(i=0; i < 8; i++) ++ ctx.pc_key[i] = ses->ses_key[i]; ++ for(i=0; i < 4; i++) ++ SWAP32(ctx.pc_iv[i]); ++ } ++ ++ /* Authentication requested */ ++ if (maccrd) { ++ macoffset = maccrd->crd_skip; ++ ++ if (maccrd->crd_alg == CRYPTO_MD5_HMAC) ++ ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_MD5); ++ else ++ ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_SHA1); ++ ++ for (i = 0; i < 5; i++) { ++ ctx.pc_hminner[i] = ses->ses_hminner[i]; ++ ctx.pc_hmouter[i] = ses->ses_hmouter[i]; ++ ++ HTOLE32(ctx.pc_hminner[i]); ++ HTOLE32(ctx.pc_hmouter[i]); ++ } ++ } ++ ++ if (enccrd && maccrd) { ++ /* ++ * ubsec cannot handle packets where the end of encryption ++ * and authentication are not the same, or where the ++ * encrypted part begins before the authenticated part. ++ */ ++ if (((encoffset + enccrd->crd_len) != ++ (macoffset + maccrd->crd_len)) || ++ (enccrd->crd_skip < maccrd->crd_skip)) { ++ err = EINVAL; ++ goto errout; ++ } ++ sskip = maccrd->crd_skip; ++ cpskip = dskip = enccrd->crd_skip; ++ stheend = maccrd->crd_len; ++ dtheend = enccrd->crd_len; ++ coffset = enccrd->crd_skip - maccrd->crd_skip; ++ cpoffset = cpskip + dtheend; ++#ifdef UBSEC_DEBUG ++ DPRINTF("mac: skip %d, len %d, inject %d\n", ++ maccrd->crd_skip, maccrd->crd_len, maccrd->crd_inject); ++ DPRINTF("enc: skip %d, len %d, inject %d\n", ++ enccrd->crd_skip, enccrd->crd_len, enccrd->crd_inject); ++ DPRINTF("src: skip %d, len %d\n", sskip, stheend); ++ DPRINTF("dst: skip %d, len %d\n", dskip, dtheend); ++ DPRINTF("ubs: coffset %d, pktlen %d, cpskip %d, cpoffset %d\n", ++ coffset, stheend, cpskip, cpoffset); ++#endif ++ } else { ++ cpskip = dskip = sskip = macoffset + encoffset; ++ dtheend = stheend = (enccrd)?enccrd->crd_len:maccrd->crd_len; ++ cpoffset = cpskip + dtheend; ++ coffset = 0; ++ } ++ ctx.pc_offset = htole16(coffset >> 2); ++ ++#if 0 ++ if (bus_dmamap_create(sc->sc_dmat, 0xfff0, UBS_MAX_SCATTER, ++ 0xfff0, 0, BUS_DMA_NOWAIT, &q->q_src_map) != 0) { ++ err = ENOMEM; ++ goto errout; ++ } ++#endif ++ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) { ++#if 0 ++ if (bus_dmamap_load_mbuf(sc->sc_dmat, q->q_src_map, ++ q->q_src_m, BUS_DMA_NOWAIT) != 0) { ++ bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); ++ q->q_src_map = NULL; ++ err = ENOMEM; ++ goto errout; ++ } ++#endif ++ err = dma_map_skb(sc, q->q_src_map, q->q_src_m, &q->q_src_len); ++ if (unlikely(err != 0)) ++ goto errout; ++ ++ } else if (crp->crp_flags & CRYPTO_F_IOV) { ++#if 0 ++ if (bus_dmamap_load_uio(sc->sc_dmat, q->q_src_map, ++ q->q_src_io, BUS_DMA_NOWAIT) != 0) { ++ bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); ++ q->q_src_map = NULL; ++ err = ENOMEM; ++ goto errout; ++ } ++#endif ++ err = dma_map_uio(sc, q->q_src_map, q->q_src_io, &q->q_src_len); ++ if (unlikely(err != 0)) ++ goto errout; ++ } ++ ++ /* ++ * Check alignment ++ */ ++ nicealign = ubsec_dmamap_aligned(sc, q->q_src_map, q->q_src_len); ++ ++ dmap->d_dma->d_mcr.mcr_pktlen = htole16(stheend); ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("src skip: %d\n", sskip); ++#endif ++ for (i = j = 0; i < q->q_src_len; i++) { ++ struct ubsec_pktbuf *pb; ++ size_t packl = q->q_src_map[i].dma_size; ++ dma_addr_t packp = q->q_src_map[i].dma_paddr; ++ ++ if (sskip >= packl) { ++ sskip -= packl; ++ continue; ++ } ++ ++ packl -= sskip; ++ packp += sskip; ++ sskip = 0; ++ ++ /* maximum fragment size is 0xfffc */ ++ if (packl > 0xfffc) { ++ DPRINTF("Error: fragment size is bigger than 0xfffc.\n"); ++ err = EIO; ++ goto errout; ++ } ++ ++ if (j == 0) ++ pb = &dmap->d_dma->d_mcr.mcr_ipktbuf; ++ else ++ pb = &dmap->d_dma->d_sbuf[j - 1]; ++ ++ pb->pb_addr = htole32(packp); ++ ++ if (stheend) { ++ if (packl > stheend) { ++ pb->pb_len = htole32(stheend); ++ stheend = 0; ++ } else { ++ pb->pb_len = htole32(packl); ++ stheend -= packl; ++ } ++ } else ++ pb->pb_len = htole32(packl); ++ ++ if ((i + 1) == q->q_src_len) ++ pb->pb_next = 0; ++ else ++ pb->pb_next = htole32(dmap->d_alloc.dma_paddr + ++ offsetof(struct ubsec_dmachunk, d_sbuf[j])); ++ j++; ++ } ++ ++ if (enccrd == NULL && maccrd != NULL) { ++ /* Authentication only */ ++ dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr = 0; ++ dmap->d_dma->d_mcr.mcr_opktbuf.pb_len = 0; ++ dmap->d_dma->d_mcr.mcr_opktbuf.pb_next = ++ htole32(dmap->d_alloc.dma_paddr + ++ offsetof(struct ubsec_dmachunk, d_macbuf[0])); ++#ifdef UBSEC_DEBUG ++ DPRINTF("opkt: %x %x %x\n", ++ dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr, ++ dmap->d_dma->d_mcr.mcr_opktbuf.pb_len, ++ dmap->d_dma->d_mcr.mcr_opktbuf.pb_next); ++#endif ++ } else { ++ if (crp->crp_flags & CRYPTO_F_IOV) { ++ if (!nicealign) { ++ err = EINVAL; ++ goto errout; ++ } ++#if 0 ++ if (bus_dmamap_create(sc->sc_dmat, 0xfff0, ++ UBS_MAX_SCATTER, 0xfff0, 0, BUS_DMA_NOWAIT, ++ &q->q_dst_map) != 0) { ++ err = ENOMEM; ++ goto errout; ++ } ++ if (bus_dmamap_load_uio(sc->sc_dmat, q->q_dst_map, ++ q->q_dst_io, BUS_DMA_NOWAIT) != 0) { ++ bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); ++ q->q_dst_map = NULL; ++ goto errout; ++ } ++#endif ++ ++ /* HW shall copy the result into the source memory */ ++ for(i = 0; i < q->q_src_len; i++) ++ q->q_dst_map[i] = q->q_src_map[i]; ++ ++ q->q_dst_len = q->q_src_len; ++ q->q_has_dst = 0; ++ ++ } else if (crp->crp_flags & CRYPTO_F_SKBUF) { ++ if (nicealign) { ++ ++ /* HW shall copy the result into the source memory */ ++ q->q_dst_m = q->q_src_m; ++ for(i = 0; i < q->q_src_len; i++) ++ q->q_dst_map[i] = q->q_src_map[i]; ++ ++ q->q_dst_len = q->q_src_len; ++ q->q_has_dst = 0; ++ ++ } else { ++#ifdef NOTYET ++ int totlen, len; ++ struct sk_buff *m, *top, **mp; ++ ++ totlen = q->q_src_map->dm_mapsize; ++ if (q->q_src_m->m_flags & M_PKTHDR) { ++ len = MHLEN; ++ MGETHDR(m, M_DONTWAIT, MT_DATA); ++ } else { ++ len = MLEN; ++ MGET(m, M_DONTWAIT, MT_DATA); ++ } ++ if (m == NULL) { ++ err = ENOMEM; ++ goto errout; ++ } ++ if (len == MHLEN) ++ M_DUP_PKTHDR(m, q->q_src_m); ++ if (totlen >= MINCLSIZE) { ++ MCLGET(m, M_DONTWAIT); ++ if (m->m_flags & M_EXT) ++ len = MCLBYTES; ++ } ++ m->m_len = len; ++ top = NULL; ++ mp = ⊤ ++ ++ while (totlen > 0) { ++ if (top) { ++ MGET(m, M_DONTWAIT, MT_DATA); ++ if (m == NULL) { ++ m_freem(top); ++ err = ENOMEM; ++ goto errout; ++ } ++ len = MLEN; ++ } ++ if (top && totlen >= MINCLSIZE) { ++ MCLGET(m, M_DONTWAIT); ++ if (m->m_flags & M_EXT) ++ len = MCLBYTES; ++ } ++ m->m_len = len = min(totlen, len); ++ totlen -= len; ++ *mp = m; ++ mp = &m->m_next; ++ } ++ q->q_dst_m = top; ++ ubsec_mcopy(q->q_src_m, q->q_dst_m, ++ cpskip, cpoffset); ++ if (bus_dmamap_create(sc->sc_dmat, 0xfff0, ++ UBS_MAX_SCATTER, 0xfff0, 0, BUS_DMA_NOWAIT, ++ &q->q_dst_map) != 0) { ++ err = ENOMEM; ++ goto errout; ++ } ++ if (bus_dmamap_load_mbuf(sc->sc_dmat, ++ q->q_dst_map, q->q_dst_m, ++ BUS_DMA_NOWAIT) != 0) { ++ bus_dmamap_destroy(sc->sc_dmat, ++ q->q_dst_map); ++ q->q_dst_map = NULL; ++ err = ENOMEM; ++ goto errout; ++ } ++#else ++ device_printf(sc->sc_dev, ++ "%s,%d: CRYPTO_F_SKBUF unaligned not implemented\n", ++ __FILE__, __LINE__); ++ err = EINVAL; ++ goto errout; ++#endif ++ } ++ } else { ++ err = EINVAL; ++ goto errout; ++ } ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("dst skip: %d\n", dskip); ++#endif ++ for (i = j = 0; i < q->q_dst_len; i++) { ++ struct ubsec_pktbuf *pb; ++ size_t packl = q->q_dst_map[i].dma_size; ++ dma_addr_t packp = q->q_dst_map[i].dma_paddr; ++ ++ if (dskip >= packl) { ++ dskip -= packl; ++ continue; ++ } ++ ++ packl -= dskip; ++ packp += dskip; ++ dskip = 0; ++ ++ if (packl > 0xfffc) { ++ DPRINTF("Error: fragment size is bigger than 0xfffc.\n"); ++ err = EIO; ++ goto errout; ++ } ++ ++ if (j == 0) ++ pb = &dmap->d_dma->d_mcr.mcr_opktbuf; ++ else ++ pb = &dmap->d_dma->d_dbuf[j - 1]; ++ ++ pb->pb_addr = htole32(packp); ++ ++ if (dtheend) { ++ if (packl > dtheend) { ++ pb->pb_len = htole32(dtheend); ++ dtheend = 0; ++ } else { ++ pb->pb_len = htole32(packl); ++ dtheend -= packl; ++ } ++ } else ++ pb->pb_len = htole32(packl); ++ ++ if ((i + 1) == q->q_dst_len) { ++ if (maccrd) ++ /* Authentication: ++ * The last fragment of the output buffer ++ * contains the HMAC. */ ++ pb->pb_next = htole32(dmap->d_alloc.dma_paddr + ++ offsetof(struct ubsec_dmachunk, d_macbuf[0])); ++ else ++ pb->pb_next = 0; ++ } else ++ pb->pb_next = htole32(dmap->d_alloc.dma_paddr + ++ offsetof(struct ubsec_dmachunk, d_dbuf[j])); ++ j++; ++ } ++ } ++ ++ dmap->d_dma->d_mcr.mcr_cmdctxp = htole32(dmap->d_alloc.dma_paddr + ++ offsetof(struct ubsec_dmachunk, d_ctx)); ++ ++ if (sc->sc_flags & UBS_FLAGS_LONGCTX) { ++ /* new Broadcom cards with dynamic long command context structure */ ++ ++ if (enccrd != NULL && ++ enccrd->crd_alg == CRYPTO_AES_CBC) ++ { ++ struct ubsec_pktctx_aes128 *ctxaes128; ++ struct ubsec_pktctx_aes192 *ctxaes192; ++ struct ubsec_pktctx_aes256 *ctxaes256; ++ ++ switch(ses->ses_keysize) ++ { ++ /* AES 128bit */ ++ case 128: ++ ctxaes128 = (struct ubsec_pktctx_aes128 *) ++ (dmap->d_alloc.dma_vaddr + ++ offsetof(struct ubsec_dmachunk, d_ctx)); ++ ++ ctxaes128->pc_len = htole16(sizeof(struct ubsec_pktctx_aes128)); ++ ctxaes128->pc_type = ctx.pc_type; ++ ctxaes128->pc_flags = ctx.pc_flags; ++ ctxaes128->pc_offset = ctx.pc_offset; ++ for (i = 0; i < 4; i++) ++ ctxaes128->pc_aeskey[i] = ctx.pc_key[i]; ++ for (i = 0; i < 5; i++) ++ ctxaes128->pc_hminner[i] = ctx.pc_hminner[i]; ++ for (i = 0; i < 5; i++) ++ ctxaes128->pc_hmouter[i] = ctx.pc_hmouter[i]; ++ for (i = 0; i < 4; i++) ++ ctxaes128->pc_iv[i] = ctx.pc_iv[i]; ++ break; ++ ++ /* AES 192bit */ ++ case 192: ++ ctxaes192 = (struct ubsec_pktctx_aes192 *) ++ (dmap->d_alloc.dma_vaddr + ++ offsetof(struct ubsec_dmachunk, d_ctx)); ++ ++ ctxaes192->pc_len = htole16(sizeof(struct ubsec_pktctx_aes192)); ++ ctxaes192->pc_type = ctx.pc_type; ++ ctxaes192->pc_flags = ctx.pc_flags; ++ ctxaes192->pc_offset = ctx.pc_offset; ++ for (i = 0; i < 6; i++) ++ ctxaes192->pc_aeskey[i] = ctx.pc_key[i]; ++ for (i = 0; i < 5; i++) ++ ctxaes192->pc_hminner[i] = ctx.pc_hminner[i]; ++ for (i = 0; i < 5; i++) ++ ctxaes192->pc_hmouter[i] = ctx.pc_hmouter[i]; ++ for (i = 0; i < 4; i++) ++ ctxaes192->pc_iv[i] = ctx.pc_iv[i]; ++ break; ++ ++ /* AES 256bit */ ++ case 256: ++ ctxaes256 = (struct ubsec_pktctx_aes256 *) ++ (dmap->d_alloc.dma_vaddr + ++ offsetof(struct ubsec_dmachunk, d_ctx)); ++ ++ ctxaes256->pc_len = htole16(sizeof(struct ubsec_pktctx_aes256)); ++ ctxaes256->pc_type = ctx.pc_type; ++ ctxaes256->pc_flags = ctx.pc_flags; ++ ctxaes256->pc_offset = ctx.pc_offset; ++ for (i = 0; i < 8; i++) ++ ctxaes256->pc_aeskey[i] = ctx.pc_key[i]; ++ for (i = 0; i < 5; i++) ++ ctxaes256->pc_hminner[i] = ctx.pc_hminner[i]; ++ for (i = 0; i < 5; i++) ++ ctxaes256->pc_hmouter[i] = ctx.pc_hmouter[i]; ++ for (i = 0; i < 4; i++) ++ ctxaes256->pc_iv[i] = ctx.pc_iv[i]; ++ break; ++ ++ } ++ } else { ++ /* ++ * [3]DES / MD5_HMAC / SHA1_HMAC ++ * ++ * MD5_HMAC / SHA1_HMAC can use the IPSEC 3DES operation without ++ * encryption. ++ */ ++ struct ubsec_pktctx_des *ctxdes; ++ ++ ctxdes = (struct ubsec_pktctx_des *)(dmap->d_alloc.dma_vaddr + ++ offsetof(struct ubsec_dmachunk, d_ctx)); ++ ++ ctxdes->pc_len = htole16(sizeof(struct ubsec_pktctx_des)); ++ ctxdes->pc_type = ctx.pc_type; ++ ctxdes->pc_flags = ctx.pc_flags; ++ ctxdes->pc_offset = ctx.pc_offset; ++ for (i = 0; i < 6; i++) ++ ctxdes->pc_deskey[i] = ctx.pc_key[i]; ++ for (i = 0; i < 5; i++) ++ ctxdes->pc_hminner[i] = ctx.pc_hminner[i]; ++ for (i = 0; i < 5; i++) ++ ctxdes->pc_hmouter[i] = ctx.pc_hmouter[i]; ++ ctxdes->pc_iv[0] = ctx.pc_iv[0]; ++ ctxdes->pc_iv[1] = ctx.pc_iv[1]; ++ } ++ } else ++ { ++ /* old Broadcom card with fixed small command context structure */ ++ ++ /* ++ * [3]DES / MD5_HMAC / SHA1_HMAC ++ */ ++ struct ubsec_pktctx *ctxs; ++ ++ ctxs = (struct ubsec_pktctx *)(dmap->d_alloc.dma_vaddr + ++ offsetof(struct ubsec_dmachunk, d_ctx)); ++ ++ /* transform generic context into small context */ ++ for (i = 0; i < 6; i++) ++ ctxs->pc_deskey[i] = ctx.pc_key[i]; ++ for (i = 0; i < 5; i++) ++ ctxs->pc_hminner[i] = ctx.pc_hminner[i]; ++ for (i = 0; i < 5; i++) ++ ctxs->pc_hmouter[i] = ctx.pc_hmouter[i]; ++ ctxs->pc_iv[0] = ctx.pc_iv[0]; ++ ctxs->pc_iv[1] = ctx.pc_iv[1]; ++ ctxs->pc_flags = ctx.pc_flags; ++ ctxs->pc_offset = ctx.pc_offset; ++ } ++ ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("spin_lock_irqsave\n"); ++#endif ++ spin_lock_irqsave(&sc->sc_ringmtx, flags); ++ //spin_lock_irq(&sc->sc_ringmtx); ++ ++ BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_queue, q, q_next); ++ sc->sc_nqueue++; ++ ubsecstats.hst_ipackets++; ++ ubsecstats.hst_ibytes += stheend; ++ ubsec_feed(sc); ++ ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("spin_unlock_irqrestore\n"); ++#endif ++ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); ++ //spin_unlock_irq(&sc->sc_ringmtx); ++ ++ return (0); ++ ++errout: ++ if (q != NULL) { ++#ifdef NOTYET ++ if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) ++ m_freem(q->q_dst_m); ++#endif ++ ++ if ((q->q_has_dst == 1) && q->q_dst_len > 0) { ++#if 0 ++ bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); ++ bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); ++#endif ++ dma_unmap(sc, q->q_dst_map, q->q_dst_len); ++ } ++ if (q->q_src_len > 0) { ++#if 0 ++ bus_dmamap_unload(sc->sc_dmat, q->q_src_map); ++ bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); ++#endif ++ dma_unmap(sc, q->q_src_map, q->q_src_len); ++ } ++ ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("spin_lock_irqsave\n"); ++#endif ++ spin_lock_irqsave(&sc->sc_ringmtx, flags); ++ //spin_lock_irq(&sc->sc_ringmtx); ++ ++ BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); ++ ++#ifdef UBSEC_VERBOSE_DEBUG ++ DPRINTF("spin_unlock_irqrestore\n"); ++#endif ++ spin_unlock_irqrestore(&sc->sc_ringmtx, flags); ++ //spin_unlock_irq(&sc->sc_ringmtx); ++ ++ } ++ if (err == EINVAL) ++ ubsecstats.hst_invalid++; ++ else ++ ubsecstats.hst_nomem++; ++errout2: ++ crp->crp_etype = err; ++ crypto_done(crp); ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s() err = %x\n", __FUNCTION__, err); ++#endif ++ ++ return (0); ++} ++ ++void ++ubsec_callback(struct ubsec_softc *sc, struct ubsec_q *q) ++{ ++ struct cryptop *crp = (struct cryptop *)q->q_crp; ++ struct cryptodesc *crd; ++ struct ubsec_dma *dmap = q->q_dma; ++ int ivsize = 8; ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ ++ ubsecstats.hst_opackets++; ++ ubsecstats.hst_obytes += dmap->d_alloc.dma_size; ++ ++#if 0 ++ bus_dmamap_sync(sc->sc_dmat, dmap->d_alloc.dma_map, 0, ++ dmap->d_alloc.dma_map->dm_mapsize, ++ BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); ++ if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { ++ bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, ++ 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_POSTREAD); ++ bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); ++ bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); ++ } ++ bus_dmamap_sync(sc->sc_dmat, q->q_src_map, ++ 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); ++ bus_dmamap_unload(sc->sc_dmat, q->q_src_map); ++ bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); ++#endif ++ ++ if ((q->q_has_dst == 1) && q->q_dst_len > 0) ++ dma_unmap(sc, q->q_dst_map, q->q_dst_len); ++ ++ dma_unmap(sc, q->q_src_map, q->q_src_len); ++ ++#ifdef NOTYET ++ if ((crp->crp_flags & CRYPTO_F_SKBUF) && (q->q_src_m != q->q_dst_m)) { ++ m_freem(q->q_src_m); ++ crp->crp_buf = (caddr_t)q->q_dst_m; ++ } ++#endif ++ ++ /* copy out IV for future use */ ++ if (q->q_flags & UBSEC_QFLAGS_COPYOUTIV) { ++ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { ++ if (crd->crd_alg != CRYPTO_DES_CBC && ++ crd->crd_alg != CRYPTO_3DES_CBC && ++ crd->crd_alg != CRYPTO_AES_CBC) ++ continue; ++ ++ if (crd->crd_alg == CRYPTO_AES_CBC) ++ ivsize = 16; ++ else ++ ivsize = 8; ++ ++ if (crp->crp_flags & CRYPTO_F_SKBUF) ++#if 0 ++ m_copydata((struct sk_buff *)crp->crp_buf, ++ crd->crd_skip + crd->crd_len - 8, 8, ++ (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv); ++#endif ++ crypto_copydata(crp->crp_flags, (caddr_t)crp->crp_buf, ++ crd->crd_skip + crd->crd_len - ivsize, ivsize, ++ (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv); ++ ++ else if (crp->crp_flags & CRYPTO_F_IOV) { ++#if 0 ++ cuio_copydata((struct uio *)crp->crp_buf, ++ crd->crd_skip + crd->crd_len - 8, 8, ++ (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv); ++#endif ++ crypto_copydata(crp->crp_flags, (caddr_t)crp->crp_buf, ++ crd->crd_skip + crd->crd_len - ivsize, ivsize, ++ (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv); ++ ++ } ++ break; ++ } ++ } ++ ++ for (crd = crp->crp_desc; crd; crd = crd->crd_next) { ++ if (crd->crd_alg != CRYPTO_MD5_HMAC && ++ crd->crd_alg != CRYPTO_SHA1_HMAC) ++ continue; ++#if 0 ++ if (crp->crp_flags & CRYPTO_F_SKBUF) ++ m_copyback((struct sk_buff *)crp->crp_buf, ++ crd->crd_inject, 12, ++ dmap->d_dma->d_macbuf); ++#endif ++#if 0 ++ /* BUG? it does not honor the mac len.. */ ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ crd->crd_inject, 12, ++ (caddr_t)dmap->d_dma->d_macbuf); ++#endif ++ crypto_copyback(crp->crp_flags, crp->crp_buf, ++ crd->crd_inject, ++ sc->sc_sessions[q->q_sesn].ses_mlen, ++ (caddr_t)dmap->d_dma->d_macbuf); ++#if 0 ++ else if (crp->crp_flags & CRYPTO_F_IOV && crp->crp_mac) ++ bcopy((caddr_t)dmap->d_dma->d_macbuf, ++ crp->crp_mac, 12); ++#endif ++ break; ++ } ++ BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); ++ crypto_done(crp); ++} ++ ++void ++ubsec_mcopy(struct sk_buff *srcm, struct sk_buff *dstm, int hoffset, int toffset) ++{ ++ int i, j, dlen, slen; ++ caddr_t dptr, sptr; ++ ++ j = 0; ++ sptr = srcm->data; ++ slen = srcm->len; ++ dptr = dstm->data; ++ dlen = dstm->len; ++ ++ while (1) { ++ for (i = 0; i < min(slen, dlen); i++) { ++ if (j < hoffset || j >= toffset) ++ *dptr++ = *sptr++; ++ slen--; ++ dlen--; ++ j++; ++ } ++ if (slen == 0) { ++ srcm = srcm->next; ++ if (srcm == NULL) ++ return; ++ sptr = srcm->data; ++ slen = srcm->len; ++ } ++ if (dlen == 0) { ++ dstm = dstm->next; ++ if (dstm == NULL) ++ return; ++ dptr = dstm->data; ++ dlen = dstm->len; ++ } ++ } ++} ++ ++int ++ubsec_dma_malloc(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma, ++ size_t size, int mapflags) ++{ ++ dma->dma_vaddr = dma_alloc_coherent(sc->sc_dv, ++ size, &dma->dma_paddr, GFP_KERNEL); ++ ++ if (likely(dma->dma_vaddr)) ++ { ++ dma->dma_size = size; ++ return (0); ++ } ++ ++ DPRINTF("could not allocate %d bytes of coherent memory.\n", size); ++ ++ return (1); ++} ++ ++void ++ubsec_dma_free(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma) ++{ ++ dma_free_coherent(sc->sc_dv, dma->dma_size, dma->dma_vaddr, ++ dma->dma_paddr); ++} ++ ++/* ++ * Resets the board. Values in the regesters are left as is ++ * from the reset (i.e. initial values are assigned elsewhere). ++ */ ++void ++ubsec_reset_board(struct ubsec_softc *sc) ++{ ++ volatile u_int32_t ctrl; ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ DPRINTF("Send reset signal to chip.\n"); ++ ++ ctrl = READ_REG(sc, BS_CTRL); ++ ctrl |= BS_CTRL_RESET; ++ WRITE_REG(sc, BS_CTRL, ctrl); ++ ++ /* ++ * Wait aprox. 30 PCI clocks = 900 ns = 0.9 us ++ */ ++ DELAY(10); ++} ++ ++/* ++ * Init Broadcom registers ++ */ ++void ++ubsec_init_board(struct ubsec_softc *sc) ++{ ++ u_int32_t ctrl; ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ DPRINTF("Initialize chip.\n"); ++ ++ ctrl = READ_REG(sc, BS_CTRL); ++ ctrl &= ~(BS_CTRL_BE32 | BS_CTRL_BE64); ++ ctrl |= BS_CTRL_LITTLE_ENDIAN | BS_CTRL_MCR1INT | BS_CTRL_DMAERR; ++ ++ WRITE_REG(sc, BS_CTRL, ctrl); ++ ++ /* Set chip capabilities (BCM5365P) */ ++ sc->sc_flags |= UBS_FLAGS_LONGCTX | UBS_FLAGS_AES; ++} ++ ++/* ++ * Clean up after a chip crash. ++ * It is assumed that the caller has spin_lock_irq(sc_ringmtx). ++ */ ++void ++ubsec_cleanchip(struct ubsec_softc *sc) ++{ ++ struct ubsec_q *q; ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ DPRINTF("Clean up queues after chip crash.\n"); ++ ++ while (!BSD_SIMPLEQ_EMPTY(&sc->sc_qchip)) { ++ q = BSD_SIMPLEQ_FIRST(&sc->sc_qchip); ++ BSD_SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q_next); ++ ubsec_free_q(sc, q); ++ } ++} ++ ++/* ++ * free a ubsec_q ++ * It is assumed that the caller has spin_lock_irq(sc_ringmtx). ++ */ ++int ++ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q) ++{ ++ struct ubsec_q *q2; ++ struct cryptop *crp; ++ int npkts; ++ int i; ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ ++ npkts = q->q_nstacked_mcrs; ++ ++ for (i = 0; i < npkts; i++) { ++ if(q->q_stacked_mcr[i]) { ++ q2 = q->q_stacked_mcr[i]; ++ ++ if ((q2->q_dst_m != NULL) && (q2->q_src_m != q2->q_dst_m)) ++#ifdef NOTYET ++ m_freem(q2->q_dst_m); ++#else ++ printk(KERN_ERR "%s,%d: SKB not supported\n", __FILE__, __LINE__); ++#endif ++ ++ crp = (struct cryptop *)q2->q_crp; ++ ++ BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q2, q_next); ++ ++ crp->crp_etype = EFAULT; ++ crypto_done(crp); ++ } else { ++ break; ++ } ++ } ++ ++ /* ++ * Free header MCR ++ */ ++ if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) ++#ifdef NOTYET ++ m_freem(q->q_dst_m); ++#else ++ printk(KERN_ERR "%s,%d: SKB not supported\n", __FILE__, __LINE__); ++#endif ++ ++ crp = (struct cryptop *)q->q_crp; ++ ++ BSD_SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); ++ ++ crp->crp_etype = EFAULT; ++ crypto_done(crp); ++ return(0); ++} ++ ++/* ++ * Routine to reset the chip and clean up. ++ * It is assumed that the caller has spin_lock_irq(sc_ringmtx). ++ */ ++void ++ubsec_totalreset(struct ubsec_softc *sc) ++{ ++ ++#ifdef UBSEC_DEBUG ++ DPRINTF("%s()\n", __FUNCTION__); ++#endif ++ DPRINTF("initiate total chip reset.. \n"); ++ ubsec_reset_board(sc); ++ ubsec_init_board(sc); ++ ubsec_cleanchip(sc); ++} ++ ++void ++ubsec_dump_pb(struct ubsec_pktbuf *pb) ++{ ++ printf("addr 0x%x (0x%x) next 0x%x\n", ++ pb->pb_addr, pb->pb_len, pb->pb_next); ++} ++ ++void ++ubsec_dump_mcr(struct ubsec_mcr *mcr) ++{ ++ struct ubsec_mcr_add *ma; ++ int i; ++ ++ printf("MCR:\n"); ++ printf(" pkts: %u, flags 0x%x\n", ++ letoh16(mcr->mcr_pkts), letoh16(mcr->mcr_flags)); ++ ma = (struct ubsec_mcr_add *)&mcr->mcr_cmdctxp; ++ for (i = 0; i < letoh16(mcr->mcr_pkts); i++) { ++ printf(" %d: ctx 0x%x len 0x%x rsvd 0x%x\n", i, ++ letoh32(ma->mcr_cmdctxp), letoh16(ma->mcr_pktlen), ++ letoh16(ma->mcr_reserved)); ++ printf(" %d: ipkt ", i); ++ ubsec_dump_pb(&ma->mcr_ipktbuf); ++ printf(" %d: opkt ", i); ++ ubsec_dump_pb(&ma->mcr_opktbuf); ++ ma++; ++ } ++ printf("END MCR\n"); ++} ++ ++static int __init mod_init(void) { ++ return ssb_driver_register(&ubsec_ssb_driver); ++} ++ ++static void __exit mod_exit(void) { ++ ssb_driver_unregister(&ubsec_ssb_driver); ++} ++ ++module_init(mod_init); ++module_exit(mod_exit); ++ ++// Meta information ++MODULE_AUTHOR("Daniel Mueller "); ++MODULE_LICENSE("BSD"); ++MODULE_DESCRIPTION("OCF driver for BCM5365P IPSec Core"); ++MODULE_VERSION(DRV_MODULE_VERSION); ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/ubsec_ssb/ubsecreg.h linux-3.1.4/crypto/ocf/ubsec_ssb/ubsecreg.h +--- linux-3.1.4.orig/crypto/ocf/ubsec_ssb/ubsecreg.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/ubsec_ssb/ubsecreg.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,233 @@ ++ ++/* ++ * Copyright (c) 2008 Daniel Mueller (daniel@danm.de) ++ * Copyright (c) 2000 Theo de Raadt ++ * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com) ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored in part by the Defense Advanced Research Projects ++ * Agency (DARPA) and Air Force Research Laboratory, Air Force ++ * Materiel Command, USAF, under agreement number F30602-01-2-0537. ++ * ++ */ ++ ++/* ++ * Register definitions for 5601 BlueSteel Networks Ubiquitous Broadband ++ * Security "uBSec" chip. Definitions from revision 2.8 of the product ++ * datasheet. ++ */ ++ ++#define BS_BAR 0x10 /* DMA base address register */ ++#define BS_TRDY_TIMEOUT 0x40 /* TRDY timeout */ ++#define BS_RETRY_TIMEOUT 0x41 /* DMA retry timeout */ ++ ++#define UBS_PCI_RTY_SHIFT 8 ++#define UBS_PCI_RTY_MASK 0xff ++#define UBS_PCI_RTY(misc) \ ++ (((misc) >> UBS_PCI_RTY_SHIFT) & UBS_PCI_RTY_MASK) ++ ++#define UBS_PCI_TOUT_SHIFT 0 ++#define UBS_PCI_TOUT_MASK 0xff ++#define UBS_PCI_TOUT(misc) \ ++ (((misc) >> PCI_TOUT_SHIFT) & PCI_TOUT_MASK) ++ ++/* ++ * DMA Control & Status Registers (offset from BS_BAR) ++ */ ++#define BS_MCR1 0x20 /* DMA Master Command Record 1 */ ++#define BS_CTRL 0x24 /* DMA Control */ ++#define BS_STAT 0x28 /* DMA Status */ ++#define BS_ERR 0x2c /* DMA Error Address */ ++#define BS_DEV_ID 0x34 /* IPSec Device ID */ ++ ++/* BS_CTRL - DMA Control */ ++#define BS_CTRL_RESET 0x80000000 /* hardware reset, 5805/5820 */ ++#define BS_CTRL_MCR2INT 0x40000000 /* enable intr MCR for MCR2 */ ++#define BS_CTRL_MCR1INT 0x20000000 /* enable intr MCR for MCR1 */ ++#define BS_CTRL_OFM 0x10000000 /* Output fragment mode */ ++#define BS_CTRL_BE32 0x08000000 /* big-endian, 32bit bytes */ ++#define BS_CTRL_BE64 0x04000000 /* big-endian, 64bit bytes */ ++#define BS_CTRL_DMAERR 0x02000000 /* enable intr DMA error */ ++#define BS_CTRL_RNG_M 0x01800000 /* RNG mode */ ++#define BS_CTRL_RNG_1 0x00000000 /* 1bit rn/one slow clock */ ++#define BS_CTRL_RNG_4 0x00800000 /* 1bit rn/four slow clocks */ ++#define BS_CTRL_RNG_8 0x01000000 /* 1bit rn/eight slow clocks */ ++#define BS_CTRL_RNG_16 0x01800000 /* 1bit rn/16 slow clocks */ ++#define BS_CTRL_SWNORM 0x00400000 /* 582[01], sw normalization */ ++#define BS_CTRL_FRAG_M 0x0000ffff /* output fragment size mask */ ++#define BS_CTRL_LITTLE_ENDIAN (BS_CTRL_BE32 | BS_CTRL_BE64) ++ ++/* BS_STAT - DMA Status */ ++#define BS_STAT_MCR1_BUSY 0x80000000 /* MCR1 is busy */ ++#define BS_STAT_MCR1_FULL 0x40000000 /* MCR1 is full */ ++#define BS_STAT_MCR1_DONE 0x20000000 /* MCR1 is done */ ++#define BS_STAT_DMAERR 0x10000000 /* DMA error */ ++#define BS_STAT_MCR2_FULL 0x08000000 /* MCR2 is full */ ++#define BS_STAT_MCR2_DONE 0x04000000 /* MCR2 is done */ ++#define BS_STAT_MCR1_ALLEMPTY 0x02000000 /* 5821, MCR1 is empty */ ++#define BS_STAT_MCR2_ALLEMPTY 0x01000000 /* 5821, MCR2 is empty */ ++ ++/* BS_ERR - DMA Error Address */ ++#define BS_ERR_ADDR 0xfffffffc /* error address mask */ ++#define BS_ERR_READ 0x00000002 /* fault was on read */ ++ ++struct ubsec_pktctx { ++ u_int32_t pc_deskey[6]; /* 3DES key */ ++ u_int32_t pc_hminner[5]; /* hmac inner state */ ++ u_int32_t pc_hmouter[5]; /* hmac outer state */ ++ u_int32_t pc_iv[2]; /* [3]DES iv */ ++ u_int16_t pc_flags; /* flags, below */ ++ u_int16_t pc_offset; /* crypto offset */ ++} __attribute__ ((packed)); ++ ++#define UBS_PKTCTX_ENC_3DES 0x8000 /* use 3des */ ++#define UBS_PKTCTX_ENC_AES 0x8000 /* use aes */ ++#define UBS_PKTCTX_ENC_NONE 0x0000 /* no encryption */ ++#define UBS_PKTCTX_INBOUND 0x4000 /* inbound packet */ ++#define UBS_PKTCTX_AUTH 0x3000 /* authentication mask */ ++#define UBS_PKTCTX_AUTH_NONE 0x0000 /* no authentication */ ++#define UBS_PKTCTX_AUTH_MD5 0x1000 /* use hmac-md5 */ ++#define UBS_PKTCTX_AUTH_SHA1 0x2000 /* use hmac-sha1 */ ++#define UBS_PKTCTX_AES128 0x0 /* AES 128bit keys */ ++#define UBS_PKTCTX_AES192 0x100 /* AES 192bit keys */ ++#define UBS_PKTCTX_AES256 0x200 /* AES 256bit keys */ ++ ++struct ubsec_pktctx_des { ++ volatile u_int16_t pc_len; /* length of ctx struct */ ++ volatile u_int16_t pc_type; /* context type */ ++ volatile u_int16_t pc_flags; /* flags, same as above */ ++ volatile u_int16_t pc_offset; /* crypto/auth offset */ ++ volatile u_int32_t pc_deskey[6]; /* 3DES key */ ++ volatile u_int32_t pc_iv[2]; /* [3]DES iv */ ++ volatile u_int32_t pc_hminner[5]; /* hmac inner state */ ++ volatile u_int32_t pc_hmouter[5]; /* hmac outer state */ ++} __attribute__ ((packed)); ++ ++struct ubsec_pktctx_aes128 { ++ volatile u_int16_t pc_len; /* length of ctx struct */ ++ volatile u_int16_t pc_type; /* context type */ ++ volatile u_int16_t pc_flags; /* flags, same as above */ ++ volatile u_int16_t pc_offset; /* crypto/auth offset */ ++ volatile u_int32_t pc_aeskey[4]; /* AES 128bit key */ ++ volatile u_int32_t pc_iv[4]; /* AES iv */ ++ volatile u_int32_t pc_hminner[5]; /* hmac inner state */ ++ volatile u_int32_t pc_hmouter[5]; /* hmac outer state */ ++} __attribute__ ((packed)); ++ ++struct ubsec_pktctx_aes192 { ++ volatile u_int16_t pc_len; /* length of ctx struct */ ++ volatile u_int16_t pc_type; /* context type */ ++ volatile u_int16_t pc_flags; /* flags, same as above */ ++ volatile u_int16_t pc_offset; /* crypto/auth offset */ ++ volatile u_int32_t pc_aeskey[6]; /* AES 192bit key */ ++ volatile u_int32_t pc_iv[4]; /* AES iv */ ++ volatile u_int32_t pc_hminner[5]; /* hmac inner state */ ++ volatile u_int32_t pc_hmouter[5]; /* hmac outer state */ ++} __attribute__ ((packed)); ++ ++struct ubsec_pktctx_aes256 { ++ volatile u_int16_t pc_len; /* length of ctx struct */ ++ volatile u_int16_t pc_type; /* context type */ ++ volatile u_int16_t pc_flags; /* flags, same as above */ ++ volatile u_int16_t pc_offset; /* crypto/auth offset */ ++ volatile u_int32_t pc_aeskey[8]; /* AES 256bit key */ ++ volatile u_int32_t pc_iv[4]; /* AES iv */ ++ volatile u_int32_t pc_hminner[5]; /* hmac inner state */ ++ volatile u_int32_t pc_hmouter[5]; /* hmac outer state */ ++} __attribute__ ((packed)); ++ ++#define UBS_PKTCTX_TYPE_IPSEC_DES 0x0000 ++#define UBS_PKTCTX_TYPE_IPSEC_AES 0x0040 ++ ++struct ubsec_pktbuf { ++ volatile u_int32_t pb_addr; /* address of buffer start */ ++ volatile u_int32_t pb_next; /* pointer to next pktbuf */ ++ volatile u_int32_t pb_len; /* packet length */ ++} __attribute__ ((packed)); ++#define UBS_PKTBUF_LEN 0x0000ffff /* length mask */ ++ ++struct ubsec_mcr { ++ volatile u_int16_t mcr_pkts; /* #pkts in this mcr */ ++ volatile u_int16_t mcr_flags; /* mcr flags (below) */ ++ volatile u_int32_t mcr_cmdctxp; /* command ctx pointer */ ++ struct ubsec_pktbuf mcr_ipktbuf; /* input chain header */ ++ volatile u_int16_t mcr_reserved; ++ volatile u_int16_t mcr_pktlen; ++ struct ubsec_pktbuf mcr_opktbuf; /* output chain header */ ++} __attribute__ ((packed)); ++ ++struct ubsec_mcr_add { ++ volatile u_int32_t mcr_cmdctxp; /* command ctx pointer */ ++ struct ubsec_pktbuf mcr_ipktbuf; /* input chain header */ ++ volatile u_int16_t mcr_reserved; ++ volatile u_int16_t mcr_pktlen; ++ struct ubsec_pktbuf mcr_opktbuf; /* output chain header */ ++} __attribute__ ((packed)); ++ ++#define UBS_MCR_DONE 0x0001 /* mcr has been processed */ ++#define UBS_MCR_ERROR 0x0002 /* error in processing */ ++#define UBS_MCR_ERRORCODE 0xff00 /* error type */ ++ ++struct ubsec_ctx_keyop { ++ volatile u_int16_t ctx_len; /* command length */ ++ volatile u_int16_t ctx_op; /* operation code */ ++ volatile u_int8_t ctx_pad[60]; /* padding */ ++} __attribute__ ((packed)); ++#define UBS_CTXOP_DHPKGEN 0x01 /* dh public key generation */ ++#define UBS_CTXOP_DHSSGEN 0x02 /* dh shared secret gen. */ ++#define UBS_CTXOP_RSAPUB 0x03 /* rsa public key op */ ++#define UBS_CTXOP_RSAPRIV 0x04 /* rsa private key op */ ++#define UBS_CTXOP_DSASIGN 0x05 /* dsa signing op */ ++#define UBS_CTXOP_DSAVRFY 0x06 /* dsa verification */ ++#define UBS_CTXOP_RNGBYPASS 0x41 /* rng direct test mode */ ++#define UBS_CTXOP_RNGSHA1 0x42 /* rng sha1 test mode */ ++#define UBS_CTXOP_MODADD 0x43 /* modular addition */ ++#define UBS_CTXOP_MODSUB 0x44 /* modular subtraction */ ++#define UBS_CTXOP_MODMUL 0x45 /* modular multiplication */ ++#define UBS_CTXOP_MODRED 0x46 /* modular reduction */ ++#define UBS_CTXOP_MODEXP 0x47 /* modular exponentiation */ ++#define UBS_CTXOP_MODINV 0x48 /* modular inverse */ ++ ++struct ubsec_ctx_rngbypass { ++ volatile u_int16_t rbp_len; /* command length, 64 */ ++ volatile u_int16_t rbp_op; /* rng bypass, 0x41 */ ++ volatile u_int8_t rbp_pad[60]; /* padding */ ++} __attribute__ ((packed)); ++ ++/* modexp: C = (M ^ E) mod N */ ++struct ubsec_ctx_modexp { ++ volatile u_int16_t me_len; /* command length */ ++ volatile u_int16_t me_op; /* modexp, 0x47 */ ++ volatile u_int16_t me_E_len; /* E (bits) */ ++ volatile u_int16_t me_N_len; /* N (bits) */ ++ u_int8_t me_N[2048/8]; /* N */ ++} __attribute__ ((packed)); ++ ++struct ubsec_ctx_rsapriv { ++ volatile u_int16_t rpr_len; /* command length */ ++ volatile u_int16_t rpr_op; /* rsaprivate, 0x04 */ ++ volatile u_int16_t rpr_q_len; /* q (bits) */ ++ volatile u_int16_t rpr_p_len; /* p (bits) */ ++ u_int8_t rpr_buf[5 * 1024 / 8]; /* parameters: */ ++ /* p, q, dp, dq, pinv */ ++} __attribute__ ((packed)); +diff -Nur linux-3.1.4.orig/crypto/ocf/ubsec_ssb/ubsecvar.h linux-3.1.4/crypto/ocf/ubsec_ssb/ubsecvar.h +--- linux-3.1.4.orig/crypto/ocf/ubsec_ssb/ubsecvar.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/ubsec_ssb/ubsecvar.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,228 @@ ++ ++/* ++ * Copyright (c) 2008 Daniel Mueller (daniel@danm.de) ++ * Copyright (c) 2000 Theo de Raadt ++ * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com) ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ++ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ++ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ++ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * Effort sponsored in part by the Defense Advanced Research Projects ++ * Agency (DARPA) and Air Force Research Laboratory, Air Force ++ * Materiel Command, USAF, under agreement number F30602-01-2-0537. ++ * ++ */ ++ ++/* Maximum queue length */ ++#ifndef UBS_MAX_NQUEUE ++#define UBS_MAX_NQUEUE 60 ++#endif ++ ++#define UBS_MAX_SCATTER 64 /* Maximum scatter/gather depth */ ++ ++#ifndef UBS_MAX_AGGR ++#define UBS_MAX_AGGR 5 /* Maximum aggregation count */ ++#endif ++ ++#define UBSEC_CARD(sid) (((sid) & 0xf0000000) >> 28) ++#define UBSEC_SESSION(sid) ( (sid) & 0x0fffffff) ++#define UBSEC_SID(crd, sesn) (((crd) << 28) | ((sesn) & 0x0fffffff)) ++ ++#define UBS_DEF_RTY 0xff /* PCI Retry Timeout */ ++#define UBS_DEF_TOUT 0xff /* PCI TRDY Timeout */ ++#define UBS_DEF_CACHELINE 0x01 /* Cache Line setting */ ++ ++#define DEFAULT_HMAC_LEN 12 ++ ++struct ubsec_dma_alloc { ++ dma_addr_t dma_paddr; ++ void *dma_vaddr; ++ /* ++ bus_dmamap_t dma_map; ++ bus_dma_segment_t dma_seg; ++ */ ++ size_t dma_size; ++ /* ++ int dma_nseg; ++ */ ++}; ++ ++struct ubsec_q2 { ++ BSD_SIMPLEQ_ENTRY(ubsec_q2) q_next; ++ struct ubsec_dma_alloc q_mcr; ++ struct ubsec_dma_alloc q_ctx; ++ u_int q_type; ++}; ++ ++struct ubsec_q2_rng { ++ struct ubsec_q2 rng_q; ++ struct ubsec_dma_alloc rng_buf; ++ int rng_used; ++}; ++ ++/* C = (M ^ E) mod N */ ++#define UBS_MODEXP_PAR_M 0 ++#define UBS_MODEXP_PAR_E 1 ++#define UBS_MODEXP_PAR_N 2 ++struct ubsec_q2_modexp { ++ struct ubsec_q2 me_q; ++ struct cryptkop * me_krp; ++ struct ubsec_dma_alloc me_M; ++ struct ubsec_dma_alloc me_E; ++ struct ubsec_dma_alloc me_C; ++ struct ubsec_dma_alloc me_epb; ++ int me_modbits; ++ int me_shiftbits; ++ int me_normbits; ++}; ++ ++#define UBS_RSAPRIV_PAR_P 0 ++#define UBS_RSAPRIV_PAR_Q 1 ++#define UBS_RSAPRIV_PAR_DP 2 ++#define UBS_RSAPRIV_PAR_DQ 3 ++#define UBS_RSAPRIV_PAR_PINV 4 ++#define UBS_RSAPRIV_PAR_MSGIN 5 ++#define UBS_RSAPRIV_PAR_MSGOUT 6 ++struct ubsec_q2_rsapriv { ++ struct ubsec_q2 rpr_q; ++ struct cryptkop * rpr_krp; ++ struct ubsec_dma_alloc rpr_msgin; ++ struct ubsec_dma_alloc rpr_msgout; ++}; ++ ++#define UBSEC_RNG_BUFSIZ 16 /* measured in 32bit words */ ++ ++struct ubsec_dmachunk { ++ struct ubsec_mcr d_mcr; ++ struct ubsec_mcr_add d_mcradd[UBS_MAX_AGGR-1]; ++ struct ubsec_pktbuf d_sbuf[UBS_MAX_SCATTER-1]; ++ struct ubsec_pktbuf d_dbuf[UBS_MAX_SCATTER-1]; ++ u_int32_t d_macbuf[5]; ++ union { ++ struct ubsec_pktctx_aes256 ctxaes256; ++ struct ubsec_pktctx_aes192 ctxaes192; ++ struct ubsec_pktctx_des ctxdes; ++ struct ubsec_pktctx_aes128 ctxaes128; ++ struct ubsec_pktctx ctx; ++ } d_ctx; ++}; ++ ++struct ubsec_dma { ++ BSD_SIMPLEQ_ENTRY(ubsec_dma) d_next; ++ struct ubsec_dmachunk *d_dma; ++ struct ubsec_dma_alloc d_alloc; ++}; ++ ++#define UBS_FLAGS_KEY 0x01 /* has key accelerator */ ++#define UBS_FLAGS_LONGCTX 0x02 /* uses long ipsec ctx */ ++#define UBS_FLAGS_BIGKEY 0x04 /* 2048bit keys */ ++#define UBS_FLAGS_HWNORM 0x08 /* hardware normalization */ ++#define UBS_FLAGS_RNG 0x10 /* hardware rng */ ++#define UBS_FLAGS_AES 0x20 /* hardware AES support */ ++ ++struct ubsec_q { ++ BSD_SIMPLEQ_ENTRY(ubsec_q) q_next; ++ int q_nstacked_mcrs; ++ struct ubsec_q *q_stacked_mcr[UBS_MAX_AGGR-1]; ++ struct cryptop *q_crp; ++ struct ubsec_dma *q_dma; ++ ++ //struct mbuf *q_src_m, *q_dst_m; ++ struct sk_buff *q_src_m, *q_dst_m; ++ struct uio *q_src_io, *q_dst_io; ++ ++ /* ++ bus_dmamap_t q_src_map; ++ bus_dmamap_t q_dst_map; ++ */ ++ ++ /* DMA addresses for In-/Out packages */ ++ int q_src_len; ++ int q_dst_len; ++ struct ubsec_dma_alloc q_src_map[UBS_MAX_SCATTER]; ++ struct ubsec_dma_alloc q_dst_map[UBS_MAX_SCATTER]; ++ int q_has_dst; ++ ++ int q_sesn; ++ int q_flags; ++}; ++ ++struct ubsec_softc { ++ softc_device_decl sc_dev; ++ struct ssb_device *sdev; /* device backpointer */ ++ ++ struct device *sc_dv; /* generic device */ ++ void *sc_ih; /* interrupt handler cookie */ ++ int sc_flags; /* device specific flags */ ++ u_int32_t sc_statmask; /* interrupt status mask */ ++ int32_t sc_cid; /* crypto tag */ ++ BSD_SIMPLEQ_HEAD(,ubsec_q) sc_queue; /* packet queue, mcr1 */ ++ int sc_nqueue; /* count enqueued, mcr1 */ ++ BSD_SIMPLEQ_HEAD(,ubsec_q) sc_qchip; /* on chip, mcr1 */ ++ BSD_SIMPLEQ_HEAD(,ubsec_q) sc_freequeue; /* list of free queue elements */ ++ BSD_SIMPLEQ_HEAD(,ubsec_q2) sc_queue2; /* packet queue, mcr2 */ ++ int sc_nqueue2; /* count enqueued, mcr2 */ ++ BSD_SIMPLEQ_HEAD(,ubsec_q2) sc_qchip2; /* on chip, mcr2 */ ++ int sc_nsessions; /* # of sessions */ ++ struct ubsec_session *sc_sessions; /* sessions */ ++ int sc_rnghz; /* rng poll time */ ++ struct ubsec_q2_rng sc_rng; ++ struct ubsec_dma sc_dmaa[UBS_MAX_NQUEUE]; ++ struct ubsec_q *sc_queuea[UBS_MAX_NQUEUE]; ++ BSD_SIMPLEQ_HEAD(,ubsec_q2) sc_q2free; /* free list */ ++ spinlock_t sc_ringmtx; /* PE ring lock */ ++}; ++ ++#define UBSEC_QFLAGS_COPYOUTIV 0x1 ++ ++struct ubsec_session { ++ u_int32_t ses_used; ++ u_int32_t ses_key[8]; /* 3DES/AES key */ ++ u_int32_t ses_hminner[5]; /* hmac inner state */ ++ u_int32_t ses_hmouter[5]; /* hmac outer state */ ++ u_int32_t ses_iv[4]; /* [3]DES/AES iv */ ++ u_int32_t ses_keysize; /* AES key size */ ++ u_int32_t ses_mlen; /* hmac/hash length */ ++}; ++ ++struct ubsec_stats { ++ u_int64_t hst_ibytes; ++ u_int64_t hst_obytes; ++ u_int32_t hst_ipackets; ++ u_int32_t hst_opackets; ++ u_int32_t hst_invalid; ++ u_int32_t hst_nomem; ++ u_int32_t hst_queuefull; ++ u_int32_t hst_dmaerr; ++ u_int32_t hst_mcrerr; ++ u_int32_t hst_nodmafree; ++}; ++ ++struct ubsec_generic_ctx { ++ u_int32_t pc_key[8]; /* [3]DES/AES key */ ++ u_int32_t pc_hminner[5]; /* hmac inner state */ ++ u_int32_t pc_hmouter[5]; /* hmac outer state */ ++ u_int32_t pc_iv[4]; /* [3]DES/AES iv */ ++ u_int16_t pc_flags; /* flags, below */ ++ u_int16_t pc_offset; /* crypto offset */ ++ u_int16_t pc_type; /* Cryptographic operation */ ++}; ++ +diff -Nur linux-3.1.4.orig/crypto/ocf/uio.h linux-3.1.4/crypto/ocf/uio.h +--- linux-3.1.4.orig/crypto/ocf/uio.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-3.1.4/crypto/ocf/uio.h 2011-12-01 12:54:17.000000000 +0100 +@@ -0,0 +1,54 @@ ++#ifndef _OCF_UIO_H_ ++#define _OCF_UIO_H_ ++ ++#include ++ ++/* ++ * The linux uio.h doesn't have all we need. To be fully api compatible ++ * with the BSD cryptodev, we need to keep this around. Perhaps this can ++ * be moved back into the linux/uio.h ++ * ++ * Linux port done by David McCullough ++ * Copyright (C) 2006-2010 David McCullough ++ * Copyright (C) 2004-2005 Intel Corporation. ++ * ++ * LICENSE TERMS ++ * ++ * The free distribution and use of this software in both source and binary ++ * form is allowed (with or without changes) provided that: ++ * ++ * 1. distributions of this source code include the above copyright ++ * notice, this list of conditions and the following disclaimer; ++ * ++ * 2. distributions in binary form include the above copyright ++ * notice, this list of conditions and the following disclaimer ++ * in the documentation and/or other associated materials; ++ * ++ * 3. the copyright holder's name is not used to endorse products ++ * built using this software without specific written permission. ++ * ++ * ALTERNATIVELY, provided that this notice is retained in full, this product ++ * may be distributed under the terms of the GNU General Public License (GPL), ++ * in which case the provisions of the GPL apply INSTEAD OF those given above. ++ * ++ * DISCLAIMER ++ * ++ * This software is provided 'as is' with no explicit or implied warranties ++ * in respect of its properties, including, but not limited to, correctness ++ * and/or fitness for purpose. ++ * --------------------------------------------------------------------------- ++ */ ++ ++struct uio { ++ struct iovec *uio_iov; ++ int uio_iovcnt; ++ off_t uio_offset; ++ int uio_resid; ++#if 0 ++ enum uio_seg uio_segflg; ++ enum uio_rw uio_rw; ++ struct thread *uio_td; ++#endif ++}; ++ ++#endif +diff -Nur linux-3.1.4.orig/drivers/char/random.c linux-3.1.4/drivers/char/random.c +--- linux-3.1.4.orig/drivers/char/random.c 2011-11-28 23:48:14.000000000 +0100 ++++ linux-3.1.4/drivers/char/random.c 2011-12-01 12:54:17.000000000 +0100 +@@ -130,6 +130,9 @@ + * void add_interrupt_randomness(int irq); + * void add_disk_randomness(struct gendisk *disk); + * ++ * void random_input_words(__u32 *buf, size_t wordcount, int ent_count) ++ * int random_input_wait(void); ++ * + * add_input_randomness() uses the input layer interrupt timing, as well as + * the event type information from the hardware. + * +@@ -147,6 +150,13 @@ + * seek times do not make for good sources of entropy, as their seek + * times are usually fairly consistent. + * ++ * random_input_words() just provides a raw block of entropy to the input ++ * pool, such as from a hardware entropy generator. ++ * ++ * random_input_wait() suspends the caller until such time as the ++ * entropy pool falls below the write threshold, and returns a count of how ++ * much entropy (in bits) is needed to sustain the pool. ++ * + * All of these routines try to estimate how many bits of randomness a + * particular randomness source. They do this by keeping track of the + * first and second order deltas of the event timings. +@@ -722,6 +732,63 @@ + } + #endif + ++/* ++ * random_input_words - add bulk entropy to pool ++ * ++ * @buf: buffer to add ++ * @wordcount: number of __u32 words to add ++ * @ent_count: total amount of entropy (in bits) to credit ++ * ++ * this provides bulk input of entropy to the input pool ++ * ++ */ ++void random_input_words(__u32 *buf, size_t wordcount, int ent_count) ++{ ++ mix_pool_bytes(&input_pool, buf, wordcount*4); ++ ++ credit_entropy_bits(&input_pool, ent_count); ++ ++ DEBUG_ENT("crediting %d bits => %d\n", ++ ent_count, input_pool.entropy_count); ++ /* ++ * Wake up waiting processes if we have enough ++ * entropy. ++ */ ++ if (input_pool.entropy_count >= random_read_wakeup_thresh) ++ wake_up_interruptible(&random_read_wait); ++} ++EXPORT_SYMBOL(random_input_words); ++ ++/* ++ * random_input_wait - wait until random needs entropy ++ * ++ * this function sleeps until the /dev/random subsystem actually ++ * needs more entropy, and then return the amount of entropy ++ * that it would be nice to have added to the system. ++ */ ++int random_input_wait(void) ++{ ++ int count; ++ ++ wait_event_interruptible(random_write_wait, ++ input_pool.entropy_count < random_write_wakeup_thresh); ++ ++ count = random_write_wakeup_thresh - input_pool.entropy_count; ++ ++ /* likely we got woken up due to a signal */ ++ if (count <= 0) count = random_read_wakeup_thresh; ++ ++ DEBUG_ENT("requesting %d bits from input_wait()er %d<%d\n", ++ count, ++ input_pool.entropy_count, random_write_wakeup_thresh); ++ ++ return count; ++} ++EXPORT_SYMBOL(random_input_wait); ++ ++ ++#define EXTRACT_SIZE 10 ++ + /********************************************************************* + * + * Entropy extraction routines +diff -Nur linux-3.1.4.orig/fs/fcntl.c linux-3.1.4/fs/fcntl.c +--- linux-3.1.4.orig/fs/fcntl.c 2011-11-28 23:48:14.000000000 +0100 ++++ linux-3.1.4/fs/fcntl.c 2011-12-01 12:54:17.000000000 +0100 +@@ -142,6 +142,7 @@ + } + return ret; + } ++EXPORT_SYMBOL(sys_dup); + + #define SETFL_MASK (O_APPEND | O_NONBLOCK | O_NDELAY | O_DIRECT | O_NOATIME) + +diff -Nur linux-3.1.4.orig/include/linux/miscdevice.h linux-3.1.4/include/linux/miscdevice.h +--- linux-3.1.4.orig/include/linux/miscdevice.h 2011-11-28 23:48:14.000000000 +0100 ++++ linux-3.1.4/include/linux/miscdevice.h 2011-12-01 12:54:17.000000000 +0100 +@@ -18,6 +18,7 @@ + #define APOLLO_MOUSE_MINOR 7 + #define PC110PAD_MINOR 9 + /*#define ADB_MOUSE_MINOR 10 FIXME OBSOLETE */ ++#define CRYPTODEV_MINOR 70 /* /dev/crypto */ + #define WATCHDOG_MINOR 130 /* Watchdog timer */ + #define TEMP_MINOR 131 /* Temperature Sensor */ + #define RTC_MINOR 135 +diff -Nur linux-3.1.4.orig/include/linux/random.h linux-3.1.4/include/linux/random.h +--- linux-3.1.4.orig/include/linux/random.h 2011-11-28 23:48:14.000000000 +0100 ++++ linux-3.1.4/include/linux/random.h 2011-12-01 12:54:17.000000000 +0100 +@@ -54,6 +54,10 @@ + unsigned int value); + extern void add_interrupt_randomness(int irq); + ++extern void random_input_words(__u32 *buf, size_t wordcount, int ent_count); ++extern int random_input_wait(void); ++#define HAS_RANDOM_INPUT_WAIT 1 ++ + extern void get_random_bytes(void *buf, int nbytes); + void generate_random_uuid(unsigned char uuid_out[16]); + +diff -Nur linux-3.1.4.orig/kernel/pid.c linux-3.1.4/kernel/pid.c +--- linux-3.1.4.orig/kernel/pid.c 2011-11-28 23:48:14.000000000 +0100 ++++ linux-3.1.4/kernel/pid.c 2011-12-01 12:54:17.000000000 +0100 +@@ -426,6 +426,7 @@ + { + return find_task_by_pid_ns(vnr, current->nsproxy->pid_ns); + } ++EXPORT_SYMBOL(find_task_by_vpid); + + struct pid *get_task_pid(struct task_struct *task, enum pid_type type) + { diff --git a/target/linux/patches/3.1.4/sparc-include.patch b/target/linux/patches/3.1.4/sparc-include.patch new file mode 100644 index 000000000..2f8ffd061 --- /dev/null +++ b/target/linux/patches/3.1.4/sparc-include.patch @@ -0,0 +1,11 @@ +diff -Nur linux-2.6.39-rc7.orig/arch/sparc/boot/btfixupprep.c linux-2.6.39-rc7/arch/sparc/boot/btfixupprep.c +--- linux-2.6.39-rc7.orig/arch/sparc/boot/btfixupprep.c 2011-05-10 04:33:54.000000000 +0200 ++++ linux-2.6.39-rc7/arch/sparc/boot/btfixupprep.c 2011-05-21 13:34:40.000000000 +0200 +@@ -25,7 +25,6 @@ + #include + #include + #include +-#include + + #define MAXSYMS 1024 + diff --git a/target/linux/patches/3.1.4/startup.patch b/target/linux/patches/3.1.4/startup.patch new file mode 100644 index 000000000..68e8987b0 --- /dev/null +++ b/target/linux/patches/3.1.4/startup.patch @@ -0,0 +1,20 @@ +diff -Nur linux-2.6.34.orig/init/main.c linux-2.6.34/init/main.c +--- linux-2.6.34.orig/init/main.c 2010-05-16 23:17:36.000000000 +0200 ++++ linux-2.6.34/init/main.c 2010-05-20 20:13:26.321613615 +0200 +@@ -842,6 +842,7 @@ + printk(KERN_WARNING "Failed to execute %s. Attempting " + "defaults...\n", execute_command); + } ++ run_init_process("/init"); + run_init_process("/sbin/init"); + run_init_process("/etc/init"); + run_init_process("/bin/init"); +@@ -889,6 +890,8 @@ + if (sys_open((const char __user *) "/dev/console", O_RDWR, 0) < 0) + printk(KERN_WARNING "Warning: unable to open an initial console.\n"); + ++ printk(KERN_WARNING "Starting Linux (built with OpenADK).\n"); ++ + (void) sys_dup(0); + (void) sys_dup(0); + /* diff --git a/target/linux/patches/3.1.4/usb-defaults-off.patch b/target/linux/patches/3.1.4/usb-defaults-off.patch new file mode 100644 index 000000000..31367108a --- /dev/null +++ b/target/linux/patches/3.1.4/usb-defaults-off.patch @@ -0,0 +1,32 @@ +diff -Nur linux-2.6.37.orig//drivers/usb/core/Kconfig linux-2.6.37/drivers/usb/core/Kconfig +--- linux-2.6.37.orig//drivers/usb/core/Kconfig 2011-01-05 01:50:19.000000000 +0100 ++++ linux-2.6.37/drivers/usb/core/Kconfig 2011-04-12 19:04:23.000000000 +0200 +@@ -59,7 +59,7 @@ + config USB_DEVICE_CLASS + bool "USB device class-devices (DEPRECATED)" + depends on USB +- default y ++ default n + ---help--- + Userspace access to USB devices is granted by device-nodes exported + directly from the usbdev in sysfs. Old versions of the driver +diff -Nur linux-2.6.37.orig//drivers/usb/host/Kconfig linux-2.6.37/drivers/usb/host/Kconfig +--- linux-2.6.37.orig//drivers/usb/host/Kconfig 2011-01-05 01:50:19.000000000 +0100 ++++ linux-2.6.37/drivers/usb/host/Kconfig 2011-04-12 19:04:48.000000000 +0200 +@@ -62,6 +62,7 @@ + config USB_EHCI_ROOT_HUB_TT + bool "Root Hub Transaction Translators" + depends on USB_EHCI_HCD ++ default n + ---help--- + Some EHCI chips have vendor-specific extensions to integrate + transaction translators, so that no OHCI or UHCI companion +@@ -74,7 +75,7 @@ + config USB_EHCI_TT_NEWSCHED + bool "Improved Transaction Translator scheduling" + depends on USB_EHCI_HCD +- default y ++ default n + ---help--- + This changes the periodic scheduling code to fill more of the low + and full speed bandwidth available from the Transaction Translator diff --git a/target/linux/patches/3.1.4/uuid.patch b/target/linux/patches/3.1.4/uuid.patch new file mode 100644 index 000000000..2529fdab5 --- /dev/null +++ b/target/linux/patches/3.1.4/uuid.patch @@ -0,0 +1,255 @@ +diff -Nur linux-2.6.38.4.orig/block/genhd.c linux-2.6.38.4/block/genhd.c +--- linux-2.6.38.4.orig/block/genhd.c 2011-04-21 23:34:46.000000000 +0200 ++++ linux-2.6.38.4/block/genhd.c 2011-04-27 19:21:18.668912036 +0200 +@@ -34,7 +34,7 @@ + static DEFINE_MUTEX(ext_devt_mutex); + static DEFINE_IDR(ext_devt_idr); + +-static struct device_type disk_type; ++struct device_type disk_type; + + static void disk_add_events(struct gendisk *disk); + static void disk_del_events(struct gendisk *disk); +@@ -1118,7 +1118,7 @@ + return NULL; + } + +-static struct device_type disk_type = { ++struct device_type disk_type = { + .name = "disk", + .groups = disk_attr_groups, + .release = disk_release, +diff -Nur linux-2.6.38.4.orig/init/do_mounts.c linux-2.6.38.4/init/do_mounts.c +--- linux-2.6.38.4.orig/init/do_mounts.c 2011-04-21 23:34:46.000000000 +0200 ++++ linux-2.6.38.4/init/do_mounts.c 2011-04-27 19:26:52.721413000 +0200 +@@ -32,6 +32,132 @@ + + dev_t ROOT_DEV; + ++#ifdef CONFIG_EXT2_FS ++/* support for root=UUID=ce40d6b2-18eb-4a75-aefe-7ddb0995ce63 bootargs */ ++ ++#include ++ ++__u8 root_dev_uuid[16]; ++int root_dev_type; /* 0 = normal (/dev/hda1, 0301); 1 = UUID; 3 = bad */ ++ ++/* imported from block/genhd.c after removing its static qualifier */ ++extern struct device_type disk_type; ++ ++/* helper function */ ++static __u8 __init fromhex(char c) ++{ ++ if (c >= '0' && c <= '9') ++ return (c - '0'); ++ c &= ~32; ++ if (c >= 'A' && c <= 'F') ++ return (c - 'A' + 10); ++ return (0xFF); ++} ++ ++static void __init parse_uuid(const char *s) ++{ ++ int i; ++ __u8 j, k; ++ ++ if (strlen(s) != 36 || s[8] != '-' || s[13] != '-' || ++ s[18] != '-' || s[23] != '-') ++ goto bad_uuid; ++ for (i = 0; i < 16; i++) { ++ if (*s == '-') ++ ++s; ++ j = fromhex(*s++); ++ k = fromhex(*s++); ++ if (j == 0xFF || k == 0xFF) ++ goto bad_uuid; ++ root_dev_uuid[i] = (j << 4) | k; ++ } ++ return; ++ bad_uuid: ++ /* we cannot panic here, defer */ ++ root_dev_type = 3; ++} ++ ++/* from drivers/md/md.c */ ++static void __init initcode_bi_complete(struct bio *bio, int error) ++{ ++ complete((struct completion*)bio->bi_private); ++} ++ ++static int __init initcode_sync_page_read(struct block_device *bdev, ++ sector_t sector, int size, struct page *page) ++{ ++ struct bio *bio = bio_alloc(GFP_NOIO, 1); ++ struct completion event; ++ int ret, rw = READ; ++ ++ rw |= REQ_SYNC; ++ ++ bio->bi_bdev = bdev; ++ bio->bi_sector = sector; ++ bio_add_page(bio, page, size, 0); ++ init_completion(&event); ++ bio->bi_private = &event; ++ bio->bi_end_io = initcode_bi_complete; ++ submit_bio(rw, bio); ++ wait_for_completion(&event); ++ ++ ret = test_bit(BIO_UPTODATE, &bio->bi_flags); ++ bio_put(bio); ++ /* 0 = failure */ ++ return ret; ++} ++ ++/* most of this taken from fs/ext2/super.c */ ++static int __init check_dev(struct gendisk *thedisk, dev_t devt, ++ int blocksize, struct page *page) ++{ ++ struct ext2_super_block * es; ++ struct block_device *bdev; ++ unsigned long sb_block = 1; ++ unsigned long logic_sb_block; ++ unsigned long offset = 0; ++ int rv = /* not found */ 0; ++ char bff[22]; ++ ++ bdev = bdget(devt); ++ if (blkdev_get(bdev, FMODE_READ, NULL)) { ++ printk(KERN_ERR "VFS: opening block device %s failed!\n", ++ format_dev_t(bff, devt)); ++ return (0); ++ } ++ ++ if (blocksize != BLOCK_SIZE) { ++ logic_sb_block = (sb_block*BLOCK_SIZE) / blocksize; ++ offset = (sb_block*BLOCK_SIZE) % blocksize; ++ } else { ++ logic_sb_block = sb_block; ++ } ++ ++// printk(KERN_ERR "D: attempting to read %d @%lu from " ++// "bdev %p devt %08X %s\n", blocksize, logic_sb_block, ++// bdev, devt, format_dev_t(bff, devt)); ++ if (!initcode_sync_page_read(bdev, logic_sb_block, blocksize, page)) { ++// printk(KERN_ERR "D: failed!\n"); ++ goto out; ++ } ++ es = (struct ext2_super_block *)(((char *)page_address(page)) + offset); ++ if (le16_to_cpu(es->s_magic) == EXT2_SUPER_MAGIC) { ++// printk(KERN_ERR "D: has uuid " ++// "%02X%02X%02X%02X-%02X%02X-%02X%02X-%02X%02X-%02X%02X%02X%02X%02X%02X\n", ++// es->s_uuid[0], es->s_uuid[1], es->s_uuid[2], es->s_uuid[3], ++// es->s_uuid[4], es->s_uuid[5], es->s_uuid[6], es->s_uuid[7], ++// es->s_uuid[8], es->s_uuid[9], es->s_uuid[10], es->s_uuid[11], ++// es->s_uuid[12], es->s_uuid[13], es->s_uuid[14], es->s_uuid[15]); ++ if (!memcmp(es->s_uuid, root_dev_uuid, 16)) ++ rv = /* found */ 1; ++ } ++// else printk(KERN_ERR "D: bad ext2fs magic\n"); ++ out: ++ blkdev_put(bdev, FMODE_READ); ++ return (rv); ++} ++#endif /* CONFIG_EXT2_FS for UUID support */ ++ + static int __init load_ramdisk(char *str) + { + rd_doload = simple_strtol(str,NULL,0) & 3; +@@ -218,6 +344,13 @@ + static int __init root_dev_setup(char *line) + { + strlcpy(saved_root_name, line, sizeof(saved_root_name)); ++#ifdef CONFIG_EXT2_FS ++ root_dev_type = 0; ++ if (!strncmp(line, "UUID=", 5)) { ++ root_dev_type = 1; ++ parse_uuid(line + 5); ++ } ++#endif /* CONFIG_EXT2_FS for UUID support */ + return 1; + } + +@@ -403,6 +536,83 @@ + + void __init mount_root(void) + { ++#ifdef CONFIG_EXT2_FS ++ /* UUID support */ ++// printk_all_partitions(); ++ if (root_dev_type == 1) { ++ int blocksize; ++ ++ /* from block/genhd.c printk_all_partitions */ ++ struct class_dev_iter iter; ++ struct device *dev; ++ ++ /* from drivers/md/md.c */ ++ struct page *sb_page; ++ ++ if (!(sb_page = alloc_page(GFP_KERNEL))) { ++ printk(KERN_ERR "VFS: no memory for bio page\n"); ++ goto nomemforbio; ++ } ++ ++// printk(KERN_ERR "D: root is: " ++// "%02X%02X%02X%02X-%02X%02X-%02X%02X-%02X%02X-%02X%02X%02X%02X%02X%02X\n", ++// root_dev_uuid[0], root_dev_uuid[1], root_dev_uuid[2], root_dev_uuid[3], ++// root_dev_uuid[4], root_dev_uuid[5], root_dev_uuid[6], root_dev_uuid[7], ++// root_dev_uuid[8], root_dev_uuid[9], root_dev_uuid[10], root_dev_uuid[11], ++// root_dev_uuid[12], root_dev_uuid[13], root_dev_uuid[14], root_dev_uuid[15]); ++ /* from block/genhd.c printk_all_partitions */ ++// printk(KERN_ERR "D: begin iter\n"); ++ class_dev_iter_init(&iter, &block_class, NULL, &disk_type); ++ while (root_dev_type && (dev = class_dev_iter_next(&iter))) { ++// char bff[22]; ++ struct gendisk *disk = dev_to_disk(dev); ++ struct disk_part_iter piter; ++ struct hd_struct *part; ++ if (get_capacity(disk) == 0 || ++ (disk->flags & GENHD_FL_SUPPRESS_PARTITION_INFO)) { ++// printk(KERN_ERR "D: ignoring\n"); ++ continue; ++ } ++ blocksize = queue_logical_block_size(disk->queue); ++// printk(KERN_ERR "D: gendisk, blocksize %d " ++// "name '%s' devt %08X %s #part %d\n", blocksize, ++// disk->disk_name, dev->devt, ++// format_dev_t(bff, dev->devt), ++// disk_max_parts(disk)); ++ disk_part_iter_init(&piter, disk, DISK_PITER_INCL_PART0); ++ while (root_dev_type && (part = disk_part_iter_next(&piter))) { ++ /* avoid empty or too small partitions */ ++// printk(KERN_ERR "D: part #%d start %llu " ++// "nr %llu\n", part->partno, ++// (__u64)part->start_sect, ++// (__u64)part->nr_sects); ++ if (part->nr_sects < 8) ++ continue; ++ if (check_dev(disk, MKDEV(MAJOR(dev->devt), ++ MINOR(dev->devt) + part->partno), ++ blocksize, sb_page)) { ++ ROOT_DEV = part_devt(part); ++// printk(KERN_ERR "D: got match!\n"); ++ // comment out below for debugging ++ root_dev_type = 0; ++ } ++ } ++ disk_part_iter_exit(&piter); ++ } ++// printk(KERN_ERR "D: end iter\n"); ++ class_dev_iter_exit(&iter); ++ put_page(sb_page); ++ } ++ nomemforbio: ++ if (root_dev_type == 1) ++ printk(KERN_ERR "VFS: Unable to find root by UUID %s.\n", ++ saved_root_name + 5); ++ else if (root_dev_type == 3) ++ /* execute deferred panic from parse_uuid */ ++ panic("Badly formatted UUID %s was supplied as kernel " ++ "parameter root", saved_root_name + 5); ++#endif /* CONFIG_EXT2_FS for UUID support */ ++ + #ifdef CONFIG_ROOT_NFS + if (MAJOR(ROOT_DEV) == UNNAMED_MAJOR) { + if (mount_nfs_root()) diff --git a/target/linux/patches/3.1.4/vga-cons-default-off.patch b/target/linux/patches/3.1.4/vga-cons-default-off.patch new file mode 100644 index 000000000..178aeeeb9 --- /dev/null +++ b/target/linux/patches/3.1.4/vga-cons-default-off.patch @@ -0,0 +1,12 @@ +diff -Nur linux-2.6.37.orig//drivers/video/console/Kconfig linux-2.6.37/drivers/video/console/Kconfig +--- linux-2.6.37.orig//drivers/video/console/Kconfig 2011-01-05 01:50:19.000000000 +0100 ++++ linux-2.6.37/drivers/video/console/Kconfig 2011-04-12 16:29:34.000000000 +0200 +@@ -7,7 +7,7 @@ + config VGA_CONSOLE + bool "VGA text console" if EMBEDDED || !X86 + depends on !4xx && !8xx && !SPARC && !M68K && !PARISC && !FRV && !SUPERH && !BLACKFIN && !AVR32 && !MN10300 && (!ARM || ARCH_FOOTBRIDGE || ARCH_INTEGRATOR || ARCH_NETWINDER) +- default y ++ default n + help + Saying Y here will allow you to use Linux in text mode through a + display that complies with the generic VGA standard. Virtually diff --git a/target/linux/patches/3.1.4/wlan-cf.patch b/target/linux/patches/3.1.4/wlan-cf.patch new file mode 100644 index 000000000..fc20759e2 --- /dev/null +++ b/target/linux/patches/3.1.4/wlan-cf.patch @@ -0,0 +1,11 @@ +diff -Nur linux-2.6.39.orig/drivers/net/wireless/hostap/hostap_cs.c linux-2.6.39/drivers/net/wireless/hostap/hostap_cs.c +--- linux-2.6.39.orig/drivers/net/wireless/hostap/hostap_cs.c 2011-05-19 06:06:34.000000000 +0200 ++++ linux-2.6.39/drivers/net/wireless/hostap/hostap_cs.c 2011-09-12 02:46:26.987984145 +0200 +@@ -623,6 +623,7 @@ + static struct pcmcia_device_id hostap_cs_ids[] = { + PCMCIA_DEVICE_MANF_CARD(0x000b, 0x7100), + PCMCIA_DEVICE_MANF_CARD(0x000b, 0x7300), ++ PCMCIA_DEVICE_MANF_CARD(0x0004, 0x2003), + PCMCIA_DEVICE_MANF_CARD(0x0101, 0x0777), + PCMCIA_DEVICE_MANF_CARD(0x0126, 0x8000), + PCMCIA_DEVICE_MANF_CARD(0x0138, 0x0002), diff --git a/target/linux/patches/3.1.4/x86-build.patch b/target/linux/patches/3.1.4/x86-build.patch new file mode 100644 index 000000000..339140f41 --- /dev/null +++ b/target/linux/patches/3.1.4/x86-build.patch @@ -0,0 +1,11 @@ +diff -Nur linux-2.6.39-rc6.orig/arch/x86/boot/tools/build.c linux-2.6.39-rc6/arch/x86/boot/tools/build.c +--- linux-2.6.39-rc6.orig/arch/x86/boot/tools/build.c 2011-05-04 04:59:13.000000000 +0200 ++++ linux-2.6.39-rc6/arch/x86/boot/tools/build.c 2011-05-05 20:10:07.000000000 +0200 +@@ -29,7 +29,6 @@ + #include + #include + #include +-#include + #include + #include + #include diff --git a/target/linux/patches/3.1.4/zlib-inflate.patch b/target/linux/patches/3.1.4/zlib-inflate.patch new file mode 100644 index 000000000..58e1f6d21 --- /dev/null +++ b/target/linux/patches/3.1.4/zlib-inflate.patch @@ -0,0 +1,12 @@ +diff -Nur linux-2.6.37.orig/lib/Kconfig linux-2.6.37/lib/Kconfig +--- linux-2.6.37.orig/lib/Kconfig 2011-01-05 01:50:19.000000000 +0100 ++++ linux-2.6.37/lib/Kconfig 2011-03-01 20:10:29.833370667 +0100 +@@ -95,7 +95,7 @@ + # compression support is select'ed if needed + # + config ZLIB_INFLATE +- tristate ++ boolean + + config ZLIB_DEFLATE + tristate -- cgit v1.2.3